Abstract:
A method for avoiding using CMP for eliminating electroplated copper facets and reusing barrier layer in the back end of line (“BEOL”) manufacturing processes. Electropolishing is employed to remove the deposited surface metal, stopping at the barrier layer to form a smooth surface that may be utilized in subsequent steps. The method is suitable for the electropolishing of metal surfaces after formation of filled vias for through-silicon via processes employing metals such as copper, tungsten, aluminum, or alloys thereof. The remaining barrier layer may be reused to fabricate the redistribution layer.

Description:
PRIOR APPLICATION 
       [0001]    This application claims priority to CN 201310412558.6, filed Sep. 11, 2013, the entire contents of which are incorporated by reference herein. 
       FIELD OF THE INVENTION 
       [0002]    Embodiments of the invention relate generally to semiconductor device packaging technology, particularly to a process of removing electroplated metal facets, such as copper facets. 
       BACKGROUND OF THE INVENTION 
       [0003]    Many different electropolishing processes may be used for the processing of various metals and its alloy. The purpose of the process of electrochemical polishing or electropolishing is to produce metal surfaces of high purity, and to smooth and deburr the metal surfaces. Smoothing in the micro range can also produce gloss in the treated wafer surfaces. Furthermore, electropolishing can also remove any stresses from the outer layers of the metal layers. 
         [0004]    The electroplating deposition (“ECD”) of copper is the main technology for through-silicon via (“TSV”) filling in advanced packaging. In the ECD process, rapid deposition of copper requires the prior formation of barrier and seed layers. Then, chemical mechanical polishing (“CMP”) is used to removing the copper overburden on the wafer. The redistribution layer is typically formed after these steps. Due to the high cost of CMP equipment and slurry consumption, one cannot significantly decreasing the cost of the total process that includes a CMP step. 
         [0005]    The patent EP1382065 “Electropolishing metal layers on wafers having trenches or vias with dummy structure” appears to disclose an electropolishing technology in a dual-damascene process. The method of forming copper interconnect in the front end of line semiconductor procedure is presented. But the patent does not appear to address removing copper facets formed by electroplating, and does not suggest barrier layer reuse. 
         [0006]    An appreciable obstacle to the removal of overburden copper facets is the difficulty of smoothing and deburring the metal layer surface in semiconductor manufacturing in recent years. This is due to the difficulty in volatilizing the compound formed during inductively coupled plasma (“ICP”) etching processes. CMP of such surfaces is rather expensive and may produce stress in the surface structure of the wafer, which can have an adverse effect on the corrosion resistance of the wafer. The barrier layer, instead of being recycled for use in the subsequent step, is removed in the CMP process. Accordingly, the CMP produces waste and may be harmful to the environment. 
         [0007]    Electrochemical polishing of metal surfaces in semiconductor manufacturing is one alternative. U.S. Pat. No. 6,679,980B1 presents an electropolishing process that can be used for a metal and its alloy layer, which consists of cobalt-chromium-tungsten. As described in H. Surmann, “Automatiserter Entwurf von Fuzzy Systemen”, VDI Verlag (1995) Series 8, No. 452, the papers presented in this field concentrate primarily on special equipment and control systems of the electropolishing process. 
       SUMMARY 
       [0008]    Embodiments of the process of the invention allow the removal of irregularities as well as of stressed and damaged layers of material, and to obtain a barrier layer of high quality by electropolishing. 
         [0009]    Embodiments of the present invention relate to resolving the disadvantage of available technology by removing the electroplated copper facets and reusing the barrier layer, through the enablement of the production of a smooth, level and deburred barrier layer surface. Taking advantage of electropolishing technology combined with a wet etch process to remove the surface overburden copper produced in previous ECD process and smoothing the exposed barrier layer allows the attainment of a perfect surface of the remaining barrier layer. This method enables the reuse of the barrier layer, thereby decreasing the integration process cost. 
         [0010]    In an aspect, embodiments of the invention relate to a method for forming a filled blind via that may be used to subsequently form a through-silicon via. The method includes defining a blind via in a substrate. An insulation layer is deposited over the substrate and in the blind via. A barrier layer comprising a first metal and a seed layer comprising a second metal are formed over the insulation layer, with the barrier layer and seed layer extending into the blind via. A third metal layer is formed over the barrier and seed layers, filling the blind via. Overburden metal facets disposed outside the blind via are removed by electropolishing, the overburden metal facets including the second and third metals, to expose the barrier layer disposed over the wafer surface and to define a smooth surface. A first redistribution layer is formed over the exposed barrier layer. The barrier layer is patterned by removing portions of the barrier layer extending beyond the patterned first redistribution layer. 
         [0011]    One or more of the following features may be included. The blind via may be defined by deep reactive ion etching. The insulation layer may include a material such as an oxide, a nitride and/or a polymer. The first metal may include, e.g., Ti, Ta, TiN, TaN, W, WN, V, VN, Nb, and/or NbN. The second metal may include, e.g., copper, tungsten, nickel, nickel boron, gold, and silver. 
         [0012]    The third metal layer may include a metal such as, e.g., copper, tungsten, nickel, nickel boron, gold, and silver. Forming the third metal layer may include depositing copper by electrochemical deposition. Patterning the barrier layer may include performing a wet etch. 
         [0013]    A dielectric layer may be formed over the first redistribution layer. The dielectric layer may include a low K dielectric, an oxide, spin-on glass, and/or a polymer. 
         [0014]    The seed layer may be formed on the barrier layer prior to forming the third metal layer. The seed layer may be formed by depositing copper by physical vapor deposition. 
         [0015]    An annealing step may be performed after forming the third metal layer. 
         [0016]    The following additional steps may be performed: a dielectric layer may be provided over the redistribution layer, a via/trench defined in the dielectric layer, and a bump and joint plate fabricated over the via. The dielectric layer may include an oxide, nitride, spin-on glass, and/or a polymer. The via may be filled by at least one of electro chemical deposition or chemical vapor deposition. 
         [0017]    Embodiments of the method of the invention may satisfy the requirements of TSV integration processes, decrease the cost of TSV processes, and lower the threshold of TSV technology industrialization and the cost of manufacture. 
     
    
     
       Brief Description of the Drawings 
         [0018]      FIG. 1  illustrates the fabrication of a blind via and formation of an insulation layer on a wafer. 
           [0019]      FIG. 2  illustrates the fabrication of the barrier layer and seed layer on the structure of  FIG. 1 . 
           [0020]      FIG. 3  illustrates the structure of  FIG. 2  after the formation of the second metal material filling the blind via. 
           [0021]      FIG. 4  illustrates the structure of  FIG. 3  after removal of the seed layer from the wafer surface. 
           [0022]      FIG. 5  illustrates the process of wafer annealing. 
           [0023]      FIG. 6  illustrates the height modification step with respect to the second filled metal in the blind via and barrier layer. 
           [0024]      FIG. 7  illustrates the structure of  FIG. 6  after formation of the first redistribution layer. 
           [0025]      FIG. 8  illustrates the structure of  FIG. 7  after patterning of the barrier layer. 
           [0026]      FIG. 9  illustrates the fabrication of the dielectric layer. 
           [0027]      FIG. 10  illustrates the structure of  FIG. 9  after a via is defined in the dielectric layer. 
           [0028]      FIG. 11  illustrates the structure of  FIG. 10  after fabrication of a micro bump and joint plate. 
           [0029]      FIG. 12  illustrates the flow chart of a process in accordance with an embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0030]    An exemplary method in accordance with an embodiment of the invention for removing electroplated metal, e.g., copper, facets and reusing the barrier layer includes the following steps. 
         [0031]    As used herein, a through-silicon via is an electrical connection extending through a silicon or other semiconductor wafer or through a die. 
         [0032]    Referring to  FIG. 1 , in step S 1 , a substrate, such as a silicon wafer  1 , is provided. A blind via i.e., a via such as a TSV, is defined in the wafer. The blind via depth and diameter are set according to specific requirement. The blind via with the vertical sidewall may be defined by, e.g., deep reactive-ion etching (“DRIE”) or laser drilling. Generally the ratio of depth to diameter is at least 3:1. 
         [0033]    Thereafter, an insulation layer  2  is deposited on the wafer  1 , lining the blind via. The insulation layer may include, for example, silicon dioxide, silicon nitride, silicon oxynitride, an organic polymer , et cetera. The insulation layer may include a single layer or multiple layers, having a thickness of, e.g., 10 nanometers to 3 micrometers The insulation layer is formed by, e.g., plasma-enhanced chemical vapor deposition (“PECVD”), over the wafer surface and lining the via. The insulation layer isolates the copper in TSV from the silicon substrate, thereby reducing the probability of occurrence of electrical shorts. 
         [0034]    Referring to  FIG. 2 , in step S 2 , a barrier layer  401  and a seed layer  402  are deposited on the insulation layer  2  over the wafer surface and in the blind via. The barrier and seed layers may be formed by, e.g., physical vapor deposition for example such as physical vapor deposition (“PVD”) over the insulation layer on the wafer surface and lining the blind via. The seed layer is fabricated by metal deposition on the barrier layer. The barrier and seed layers together define a metal layer  4 , with the seed layer  402  including sputtered metal disposed on the barrier layer  401 . The barrier layer material includes a first metal such as, e.g., titanium, titanium nitride, tantalum nitride, tungsten, tungsten nitride, vanadium, vanadium nitride, niobium, niobium nitride, etc. The seed layer  402  includes a second metal that is preferably copper, but may also be, e.g., tungsten, nickel, nickel boron, gold, or silver. 
         [0035]    Referring to  FIG. 3 , in step S 3 , a third metallic material  5  is deposited by, e.g., an electroplating process. The blind via  3  may be filled by the third metallic material  5 . Preferably, the third metallic material is the same metal as the seed layer  402 , e.g., copper, tungsten, nickel, nickel boron, gold, or silver. The filling capability may be customized by varying organic and inorganic concentrations. Optimization of deposition conditions such as bath composition, waveform, bath temperature and flow condition, allows the via, e.g., the TSV, to be filled with little or no voids or seams. 
         [0036]    Referring to  FIG. 4 , in step S 4 , electropolishing technology may be used to remove the overburden metal facets, e.g., overburden copper, produced during the blind via filling process outside the blind via over the seed layer and over the wafer surface. The overburden facets include the second and third metals, i.e., portions of the seed layer and third metal layer. The electrolyte used for copper removal may be maintained in a temperature selected from a range of 20° C. to 50° C., which has been proven to be especially suitable. The electrolyte temperature control and monitoring can be performed in any manner known to one of skill in the art. The step height difference between the top of the filling metal material and the barrier layer may be controlled to range from, e.g., −3 micrometers to 3 micrometers. 
         [0037]    The duration of the electropolishing process depends on the roughness of the wafer surface and the required target smoothing. The optimal process parameters can be determined by a person skilled in the art by routine experimentation with respect to electrolytic temperature, current density, material to be polished, composition of the electrolyte and of the electropolishing equipment used. 
         [0038]    Other features of electropolishing technology known to persons of skill in the art may be utilized to produce high quality, microsmooth surfaces of the ECD metal and metal barrier layer. 
         [0039]    The electrolyte may be reused, so the consumption cost of ownership can decrease 70% in comparison to CMP technology. Moreover, the difficulty of process integration may be reduced. The step height  6  between the third filled metal material and the barrier layer in the surface is preferably controlled to range from 3 micrometers to −3 micrometers. 
         [0040]    Referring to  FIG. 5 , in step S 5 , the wafer may undergo an annealing step in a vertical batch system in an inert gas, such as N 2 , Ar, or a suitable gas mixture. The temperature variation rate may be controlled with a precision of better than ±1° C. The annealing results in the metal grain becoming stable. The annealing temperature may be selected from a range of 100 to 400° C. in an inert atmosphere. The heat treatment times may be selected from a range of 10 seconds to 300 minutes. It will be apparent to one skilled in the art that other suitable heating methods, such as infrared, microwave, laser lamp, scanning laser source or conventional hot plates or ovens may be used. 
         [0041]    The annealing may cause deformation of the metal, thereby leading to a variation  7  in the step height. 
         [0042]    Referring to  FIG. 6 , in step S 6 , since the electrolyte cannot dissolve the barrier layer  401  material, electropolishing may be used to modify the step height  8  between the third metal surface and the barrier layer, visibly reducing the step. The step height may approach  0  micrometers. The smaller step height facilitates the formation of a smoother distribution layer, leading to improved reliability. It may be desirable to electropolish the copper layer down to the barrier layer. 
         [0043]    Following the electropolish of the overburden copper facet , the treated wafer after Step S 6  is removed from the polishing electrolytic and typically rinsed with demineralized water, and dried by N2 if necessary. 
         [0044]    Referring to  FIG. 7 , in step S 7 , a first redistribution layer  9  is fabricated over the wafer surface, including over the barrier layer, reusing the barrier layer that was used in step S 6 , thereby not requiring the formation of a new barrier layer. This includes deposition of the first redistribution layer by, e.g., electrochemical deposition. Typically, the redistribution layer material may include copper deposited by an ECD process. The redistribution layer may have a thickness selected from a range of 0.5 micrometers to 15 micrometers. The redistribution layer pattern may be defined by a lithographic process, including PVD formation of a titanium and copper layer, forming a photoresist coating, exposure, developing, electrochemical deposition, photoresist removal, and copper and titanium etching. In accordance with embodiments of the invention, the titanium layer is reused. The method differs from conventional CMP processes that require the removal of the barrier layer until the end reference point of the insulation layer is attained. Then, in a conventional process, the barrier layer is re-deposited before the redistribution layer made. Using methods in accordance with embodiments of the invention can decrease the total cost of processes integration and lower the time of manufacture. 
         [0045]    Referring to  FIG. 8 , in step S 8 , the wet etch process may be used to remove the barrier layer disposed outside the area occupied by the first redistribution layer, thereby patterning the barrier layer. This process allows removing the electroplated copper facet without CMP by substituting a wet etch for CMP, and enabling the reuse of the barrier layer. Process costs are thereby reduced. The additional following steps may also be performed. 
         [0046]    Referring to  FIG. 9 , in step S 9 , a dielectric layer  10  may be deposited over the wafer. The dielectric layer may be a low-k dielectric. The dielectric layer may be, e.g., polyimide (“PI”), polybenzoxazole (“PBO”), a polymer such as an organic polymeric material, a spin-on glass, and/or a doped oxide, silicon dioxide, silicon nitride or silicon oxynitride, etc. The dielectric layer may be formed by PECVD or spun onto the wafer surface. 
         [0047]    Referring to  FIG. 10 , in step S 10 , a via  11  may be made in the dielectric layer to provide a connection to the first distribution layer. 
         [0048]    Referring to  FIG. 11 , in step S 11 , a micro-bump and joint plate may be fabricated over the wafer surface. Electrical connectivity may be provided by the via formed in step S 10  from the first redistribution layer and extending to the subsequently formed micro-bump and joint plate. 
         [0049]    In some embodiments (not shown), a through-silicon via may be formed by creating a blind via, filling the blind via, and performing front side processing. Then, the blind via may be opened up by a combination of back-grinding/chemical-mechanical polishing/etching to define a through-silicon via. 
         [0050]    The described embodiments of the invention are intended to be merely exemplary and numerous variations and modifications will be apparent to those skilled in the art. All such variations and modifications are intended to be within the scope of the present invention as defined in the appended claims. For example, the described embodiments of avoiding the CMP removal of overburden metal facets and reuse of the barrier layer are exemplary and should not in any way imply a restriction to the conditions to be used.