Abstract:
Methods are provided for manufacturing a wiring circuit element or wiring board in which a set of rough wiring patterns are formed by selectively etching a metal layer of a patternable member which includes a carrier layer having a rough surface and a thin rough-surfaced etch stop layer between the carrier layer and the metal layer. The etch stop layer and wiring patterns are joined to an insulating layer such that the wiring patterns adhere to the insulating layer and the insulating layer acquires a rough surface. Thereafter, the carrier layer and the etch stop layer are removed, after which openings are formed in the insulating layer in contact with at least some of the wiring patterns. A layer of metal is electrolessly plated onto the rough major surface of the insulating layer, and then a conductive wiring pattern is selectively electroplated over the electrolessly plated layer to form plated openings that interconnect at least some of the wiring patterns.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation of U.S. patent application Ser. No. 11/585,064, filed Oct. 23, 2006, which is a continuation of U.S. patent application Ser. No. 11/356,672, filed Feb. 17, 2006, which is based upon and claims the benefit of priority from Japanese Patent Application No. 2005-43784, filed Feb. 21, 2005, the disclosures of which are hereby incorporated by reference herein. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    Wiring boards typically have a wiring layer formed on the surface of an insulating substrate such that the thickness of the wiring layer protrudes above the surface of the insulating substrate. In boards which have high wiring pattern densities, such structures are prone to short-circuiting problems, particularly where contacts to the wiring layers are formed. 
         [0003]    Wiring boards are known in which the surfaces of wiring patterns themselves are embedded in the insulating material at the surface of the substrate so as to be coplanar (located at the same plane) with the surface of the insulating material. Examples of such wiring board structures are described in Japanese Examined Patent Application Publication H 6-21619. 
         [0004]      FIGS. 4(A) through 4(G)  show one example of the production steps in a method of manufacturing a wiring board having such structure. In a typical method, a transfer technique is used to make a wiring board in which exposed surfaces of the insulating material and the wiring layer embedded therein are coplanar. 
         [0005]    (A) As shown in  FIG. 4(A) , a three-layer metal member is prepared by providing a nickel layer b as an etch stop layer overlying a copper carrier layer a, and a copper layer c overlying the surface of the nickel layer b as a layer from which wiring patterns will be formed. 
         [0006]    (B) Next, as shown in  FIG. 4(B) , by selectively etching the copper layer c, wiring layers d, d, are formed to provide a wiring member “e”. In the etching process, the nickel layer b prevents the copper carrier layer a from being etched. 
         [0007]    (C) Two wiring members e as shown in  FIG. 4(B)  are prepared and disposed in opposition to each other such that the wiring layers d, d face each other. The wiring members e are pressed together with a glass fiber epoxy resin member f disposed between them to form a combined structure as shown in  FIG. 4(C) . 
         [0008]    (D) The copper carrier layer a and the nickel layer b are no longer needed and are then removed, as shown in  FIG. 4(D) . In so doing, a wiring board is completed in which the wiring layers d, d, . . . have exposed surfaces d 1  which are coplanar with the exposed surfaces f 1  of the insulating material f. 
         [0009]    (E) Next, as shown in  FIG. 4(E) , through holes g are formed where needed to provide interlayer connections between the wiring patterns on the top and bottom surfaces of the insulating material. 
         [0010]    (F) Next, as shown in  FIG. 4(F) , a thin metallic film h is formed by electrolessly plating the entire exposed surface of the wiring board, and subsequently a photoresist layer i is formed and patterned as a mask for forming the through holes. 
         [0011]    Having done so, using this photoresist layer i as a mask for electroplating, copper layer j is deposited electrolytically onto exposed surfaces of the electrolessly formed film to form plated through holes  24 .  FIG. 4(F)  shows the condition after this copper layer j is formed. 
         [0012]    (G) Next, this photoresist layer is removed and the thin layer h formed by electroless plating is removed to complete the wiring board ( FIG. 4(G) ) which includes a copper layer j covering through holes g to connect the wiring patterns exposed at opposite surfaces of the wiring board. Next, although not indicated in the drawings, the electrodes of electronic parts are connected by means of solder, etc. to the copper layer j, etc., in areas of the wiring board not covered by a selectively-formed solder resist. 
         [0013]    However, the background technology shown in  FIGS. 4(A) through 4(G)  has the following problems: 
         [0014]    First, it is difficult to form the copper layer j by the additive process shown in  FIGS. 4(   a ) through  4 (G) because of poor connection, poor bonding, and peeling of the copper layer j from the through holes due to the process of electrolytic plating used to form copper layer j and the electroless plating process which is assumed to be unavoidable for forming the copper underlayer h. 
         [0015]    Second, a selective electrolytic etching process used to form the resist layer i interferes with the additive process of forming the copper layer j, making copper layer j prone to poor connection, poor bonding, and peeling. 
         [0016]    Third, upon completing the steps outlined in  FIG. 4(G) , it is necessary to selectively form a solder resist layer overlying wiring layers d. 
         [0017]    These problems, in large part, are due to the exposed surfaces f 1  of the glass fiber epoxy resin member f of the insulating material being smooth and failing to adequately grip the electroless and electrolytic metal layers disposed thereon. 
       SUMMARY OF THE INVENTION 
       [0018]    According to various embodiments of the invention described herein, methods are provided herein for manufacturing a wiring circuit element or wiring board. In a method in accordance with one embodiment of the invention, a patternable member is provided which includes a carrier layer having a rough surface, a thin etch stop layer overlying the rough surface and a metal layer overlying the etch stop layer. As a result, corresponding surfaces of the etch stop layer and the metal layer overlying and adjacent to the rough surface of the carrier layer are rough. The metal layer is etched selectively to a material of the etch stop layer to form a plurality of wiring patterns and to expose the rough surface of the etch stop layer between the wiring patterns. An insulating layer is joined to the wiring patterns and to the exposed rough surface of the etch stop layer. Thereafter, the carrier layer and the etch stop layer are removed from the insulating layer to expose the wiring patterns and expose a rough major surface of the insulating layer between the wiring patterns. Openings are then formed in the insulating layer in contact with at least some of the wiring patterns. A layer of metal is electrolessly plated onto the rough major surface of the insulating layer and within the openings in the insulating layer. Thereafter, a conductive wiring pattern is selectively electrolytically plated over the electrolessly plated layer and within the openings to form plated openings which conductively interconnect at least some of the wiring patterns. Portions of the electrolessly plated layer exposed by the conductive wiring pattern can then be removed. 
         [0019]    In accordance with a particular embodiment of the invention, at least two patternable members are used such that first and second exposed surfaces of the insulating layer are joined to the wiring patterns and exposed rough surfaces of the etch stop layers. In such embodiment, the step of forming openings in the insulating layer includes forming through holes extending from the first surface through the insulating layer to the second surface. In addition, the step of selectively electrolytically plating a conductive wiring pattern conductively interconnects wiring patterns exposed at the first surface with wiring patterns exposed at the second surface of the insulating layer. 
         [0020]    In accordance with one or more embodiments of the invention, the etch stop layer includes a metal which is not attacked by an etchant which attacks a metal included in the metal layer overlying the etch stop layer. 
         [0021]    Preferably, the etch stop layer consists essentially of nickel and the carrier layer and the metal layer overlying the etch stop layer each consists essentially of copper. 
         [0022]    In a particular embodiment of the invention, the patternable member is formed by forming the thin etch stop layer over the rough surface of the carrier layer and forming a second metal layer over the etch stop layer. Preferably, the carrier layer includes a metal. 
         [0023]    The roughness of the exposed surface of the carrier layer in contact with the etch stop layer is such that it has unevenness of between about 0.1 micron and about 10 microns. 
         [0024]    Preferably, a solder mask is formed to overlie surfaces of the wiring circuit element in such manner that the solder mask exposes the electrolytically plated conductive wiring patterns. 
         [0025]    In accordance with one or more preferred aspects of the invention, the wiring patterns are embedded in the insulating layer such that the rough major surface of the insulating layer is co-planar with exposed major surfaces of the wiring patterns. 
         [0026]    In accordance with another embodiment of the invention, a method of manufacturing a multi-layer wiring circuit element is provided. In such method, a first patternable member and a second patternable member are provided in which each of the first and second patternable members includes a carrier layer having a rough surface, a thin etch stop layer overlying the rough surface and a metal layer overlying the etch stop layer. In this way, corresponding surfaces of the etch stop layer and the metal layer overlying and adjacent to the rough surfaces of the carrier layer are rough. The metal layers of the first and second patternable members are etched selective to a material of the etch stop layer to form first wiring patterns overlying the etch stop layer of the first patternable member and form second wiring patterns overlying the etch stop layer of the second patternable member and expose the rough surfaces of the etch stop layers in areas exposed by the first or second wiring patterns. Thereafter, the first and second insulating layers are joined to the wiring patterns and exposed etch stop layers of the first and second patternable members, respectively. An interconnection element including at least a third insulating layer is subsequently joined to the first and second insulating layers, the interconnection element having a plurality of interconnect wiring patterns extending in one or more directions parallel to an exposed surface of the third insulating layer. Thereafter, the carrier layers and the etch stop layers are removed to expose the wiring patterns joined to the first and second insulating layers and rough major surfaces of the first and second insulating layers between the wiring patterns. Through holes are formed which extend through the first, second and third insulating layers, the through holes contacting at least some of the wiring patterns. Subsequently, a layer of metal is electrolessly plated onto the rough major surfaces of the first and second insulating layers and within the through holes. Thereafter, conductive wiring patterns are selectively electrolytically plated over the electrolessly plated layers and within the through holes. Portions of the electrolessly plated layers exposed between the electrolytically plated conductive wiring patterns are removed. 
         [0027]    In a preferred embodiment of the invention, blind openings are formed which extend through at least one of the first and second insulating layers to the interconnect wiring patterns. In such case, the step of selectively electrolytically plating conductive wiring patterns includes electrolytically plating the conductive wiring patterns in the blind openings to connect the interconnect wiring patterns with at least some of the first or second wiring patterns. 
         [0028]    Preferably, the interconnect wiring patterns of the interconnection element are disposed in a plurality of wiring layers separated by respective insulating layers, and the interconnection element further includes plated through holes which conductively interconnect the plurality of wiring layers of the interconnection element. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0029]      FIGS. 1(A) through 1(M)  are cross sectional views illustrating a method of manufacturing a wiring board in accordance with a first embodiment of the invention. 
           [0030]      FIGS. 2(A) through 2(H)  are cross sectional views illustrating a method of manufacturing a wiring board in accordance with a second embodiment of the invention. 
           [0031]      FIG. 3  is a cross sectional view illustrating a wiring board in accordance with the invention. 
           [0032]      FIGS. 4(A) through 4(G)  are cross sectional views illustrating a method of manufacturing a wiring board according to the prior art. 
       
    
    
     DETAILED DESCRIPTION 
       [0033]    In the embodiments of the invention described below, one of the major surfaces of a carrier layer which serves as a member for the manufacture of a circuit board is a rough surface. This rough surface is transferred to a metal etch stop layer and, in turn, to a metal wiring layer formed on that rough surface. The rough surface is then transferred to insulating material which forms a base of the board. The insulating material which forms the base of the wiring board preferably includes epoxy resin in which glass fibers are embedded. After the metal wiring layer is patterned, the metal wiring layer and the insulating material retain the rough surface when the carrier layer is removed. 
         [0034]    A preferred method of interconnecting wiring layers of the wiring board is to form through holes and then line the through holes by electroless plating of copper or other metal. A resist layer is then formed and copper or other metal is then selectively deposited by electrolytic plating. Preferably a dry resist layer is used as this resist layer. 
         [0035]    The embodiments of the invention provided herein are described with reference to the drawings. 
         [0036]      FIGS. 1(A) through 1(M)  are cross sectional views showing the production steps in manufacturing a wiring board according to a first embodiment of this invention. 
         [0037]    (A) As shown in  FIG. 1(A) , a carrier layer  2  is prepared which preferably includes or consists essentially of copper and has a thickness of several microns to several hundred microns. At least one of the major surfaces of this carrier layer  2  has an average roughness of approximately 0.1 microns to about 10 microns measured by unevenness in the surface. Commercially available copper foil exists which has approximately this degree of roughness on at least one of its major surfaces. It is also acceptable to use a copper foil or other metal foil as the metal carrier layer  2  which has unevenness on both of its surfaces. 
         [0038]    (B) Next, as shown in  FIG. 1(A) , an etch stop layer  6  including or consisting essentially of nickel, for example, and preferably having a thickness of under 1.0 microns is formed on the rough major surface  4  of the carrier layer  2 . 
         [0039]    Like the surface  4  of the carrier layer, the surface of the etch stop layer  6  is also rough. This is because the etch stop layer  6  is thin, preferably under 1.0 microns and follows the roughness of the uneven major surface  4  of the carrier layer  2 . 
         [0040]    (C) Next, as shown in  FIG. 1(C) , a metal layer  8 , preferably consisting essentially of copper and having a thickness of several microns to several hundred microns is formed on the surface of the etch stop layer  6  to complete a member  10  for use in manufacturing a wiring board. The metal layer  8  will be subsequently patterned into wiring patterns of the wiring board. 
         [0041]    (D) Next, as shown in  FIG. 1(D) , wiring patterns  12 ,  12 , . . . are formed by selectively etching the metal layer  8 . The rough surface of the etch stop layer  6  is exposed by this etching process in areas between the wiring patterns  12 ,  12 . The member obtained after performing this step (D) is  10   a.    
         [0042]    (E) Next, as shown in  FIG. 1  (E), the two members  10   a ,  10   a  are disposed opposite each other so that the surfaces on which wiring patterns  12 ,  12 , . . . are formed face each other, with a layer of insulating material  14  disposed between them, the layer  14  preferably including glass fiber and epoxy resin. The members  10   a  and insulating material  14  are joined by heat and pressure. 
         [0043]    At this time, the rough surfaces of the metal members  10   a  are transferred to the surfaces  16  of the insulating material  14  to make them rough as well, except where the insulating material contacts the wiring patterns  12 ,  12  . . . . The rough surfaces of the etch stop layers  6  are transferred to the major surfaces  16  of the insulating material  14 . 
         [0044]    Although in the embodiment illustrated in  FIGS. 1(A) through 1(E)  wiring patterns  12 ,  12 , . . . are formed on both major surfaces of the insulating material  14 , in other embodiments wiring patterns  12 ,  12 , . . . can be provided at only one major surface of the insulating material  14 . 
         [0045]    (F) Next, as shown in FIG. (F), the carrier layer  2  and the etch stop layer  6  are removed because they are no longer needed. In so doing, a wiring board is completed in which the exposed surfaces  15  of the wiring patterns  12 ,  12 , . . . are coplanar with the exposed major surfaces  16  of the insulating material  14  and both the exposed surfaces  15  of the wiring patterns and the exposed major surfaces of the insulating material are rough surfaces. 
         [0046]    (G) Next, as shown in  FIG. 1(G) , through holes  18  are formed which cut through or adjoin the wiring patterns  12  on both sides of the insulating material. The through holes, after further processing, facilitate interlayer connections between the wiring patterns  12 . 
         [0047]    (H) Next, as shown in  FIG. 1  (H), a thin metal layer  20 , preferably including or consisting essentially of copper, is formed by electroless plating over the entire surfaces of the wiring board including within through holes  18  and over major surfaces  16  of the insulating material and exposed surfaces  15  of the wiring patterns. The copper layer  20  preferably is thin, from about 0.02 microns up to several microns in thickness. Since the copper layer  20  is formed on the rough surface  16  of the insulating material  14 , it avoids problems of poor bonding and a tendency to peel that plague the electroless copper layer of the wiring bond formed according to the prior art method ( FIGS. 4(A) through 4(G) ). 
         [0048]    (I) Next, as shown in  FIG. 1(I) , a resist layer  22  is selectively formed, e.g., either by selective deposition or subtractive patterning, as a mask for further processing of the metal layer  20  overlying through holes  18 . The selective formation of this resist mask  22  preferably is performed by applying a photoresist that is a dry film over the entire surface of the wiring board  10   a , exposing the resist to light and developing it. Since the resist layer  22  is formed on the rough-surfaced copper layer  20 , it bonds more strongly to the insulating material  14  and is better able to avoid the problems of the prior art of poor bonding and the tendency to peel. 
         [0049]    (J) Next, as shown in  FIG. 1(J) , a metal layer, e.g., copper layer  24  is formed by electrolytic plating in the through holes, with the resist layer  22  functioning as the mask. 
         [0050]    (K) Next, as shown in  FIG. 1(K) , the resist layer  22  is removed. 
         [0051]    (L) Next, as shown in  FIG. 1(L) , the copper layer  20  is removed. 
         [0052]    (M) Next, as shown in  FIG. 1(M) , a solder resist layer  26  is selectively formed. 
         [0053]    This solder resist layer  26  is formed on the rough surface of the insulating material  14 . Therefore, the solder resist layer strongly adheres to the underlying insulating material  14 , avoiding the above-described problems of poor bonding and the tendency to peel. 
         [0054]      FIGS. 2(A)  through (M) are cross sectional views showing production steps in a method of manufacturing a wiring board in accordance with a second embodiment of the invention. 
         [0055]    (A) First, a member for the manufacture of a wiring board  10  is prepared in a manner as described above with reference to  FIG. 1(C) , and wiring patterns  12 ,  12 , . . . are formed by selectively etching the metal layer  8 , to form the wiring board member  10   a  having a carrier layer  2  and etch stop layer  6  having an exposed rough-surface as shown in  FIG. 2(A) . 
         [0056]    (B) Next, as shown in  FIG. 2(B) , an insulating layer  40  consisting, for example of resin, is bonded to the rough surface of the member  10   a  upon which the wiring patterns  12 ,  12 , . . . are formed. 
         [0057]    (C) As shown in  FIG. 2(C) , a base is prepared that includes metal layers  44 ,  44  on both sides of a layer of insulating material  42 . Layer  42  preferably includes or consists essentially of a resin, for example. 
         [0058]    (D) Next, referring to  FIG. 2(D) , two members  10   a ,  10   a  are bonded to the metal layers  44 ,  44  on both sides of the base. 
         [0059]    Next, the carrier layers  2 , 2  of the members  10   a ,  10   a  on both sides are removed, and the etch stop layers  6 ,  6  are removed, leaving rough surfaces  15  of the wiring patterns and rough surfaces  41  of the insulating material  40  exposed. 
         [0060]    After that, blind openings  46 ,  46 , serving as the interlayer connection means, and through holes  48  are formed, to provide the structure shown in  FIG. 2(D) . 
         [0061]    Next, referring to  FIG. 2(E) , a metal layer  50  of copper or the like is formed by electroless plating over the exposed surfaces. Subsequently, the through holes are selectively electrolytically plated with copper or other suitable metal at which time resist patterns  52 ,  52  serve as the required plating mask. 
         [0062]    In such manner, plated through holes  54  and plated blind openings  56  provide interlayer connections between the wiring patterns  12  on each side of the insulating material  40 .  FIG. 2(E)  shows the plated through holes  54  and plated blind openings  56  after they are formed. 
         [0063]    (F) Next, as shown in  FIG. 2(F) , the resist layers  52 ,  52  are removed. 
         [0064]    (G) Next, as shown in  FIG. 2(G) , the metal layer  50  that was formed by electroless plating is removed in exposed areas not covered by the electrolytically plated layer. 
         [0065]    (H) Next, as shown in  FIG. 2(H) , a solder resist layer  58  is selectively formed to cover areas other than the plated through holes  54  and plated blind openings  56 . 
         [0066]    The embodiment shown in  FIGS. 2(A) through 2(H)  is configured to obtain a wiring board that is slightly different in structure from the embodiment shown in  FIG. 1 . However, by using the member  10  shown in  FIG. 1(C)  the technological effect of the embodiment that is shown in  FIGS. 1(A) through 1(M)  can be obtained. 
         [0067]      FIG. 3  is a cross sectional view showing a wiring board according to a third embodiment of the invention in which a plated through hole  55  conductively interconnects internal wiring pattern layers  60  and  62  but does not conductively interconnect those layers to the outermost wiring patterns  12 . Internal wiring pattern layers  60  or  62  are conductively interconnected to another plated through hole  54  which provides conductive interconnection to outermost wiring patterns  12 . Plated blind vias  56  provide further interconnection between wiring patterns  12  and wiring pattern layers  60 . 
         [0068]    Thus, this embodiment of the invention facilitates manufacture of a more multi-layered structure, a greater diversity of through-hole shapes, and can facilitate the manufacture of wiring boards with a variety of structures. 
         [0069]    Layers including copper or the like used to plate the through holes are formed using electrolytic plating of copper or the like in this particular embodiment, but the invention is not limited to this, and can be formed using, for example, conductive fillers. 
         [0070]    Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.