Abstract:
The present invention discloses a driving module for a liquid crystal display device. The driving module includes a data line signal processing unit, for generating a plurality of data driving signals, a scan line signal processing unit, for generating a plurality of gate driving signals, and a control unit, for controlling the data line signal processing unit and the gate line signal processing unit, such that a plurality of sub-pixels corresponding to a data line are with different charging orders in different frames, or are charged with different charging periods in a same frame.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a driving module and driving method, and more particularly, to a driving module and driving method charging subpixels with different charging orders in different frames, or charging subpixels with different charging periods in a same frame, to avoid charging inequality among the subpixels. 
         [0003]    2. Description of the Prior Art 
         [0004]    A liquid crystal display (LCD) device utilizes a source driver and a gate driver to drive pixels on a panel to display images. Since cost of a source driver is higher than that of a gate driver, in order to reduce number of source drivers, a pixel structure evolves from a single gate structure to a dual gate structure or a tri-gate structure. Taking the tri-gate structure as an example, for the same number of pixels, compared to the single gate structure, the tri-gate structure only has one-third as many data lines, and thrice as many scan lines for reducing the cost. However, since a gate driving signal has only a third of the conventional active cycle, a data line can only charge pixels with a third of the conventional charging time, and the pixels are likely charged insufficiently. 
         [0005]    Please refer to  FIG. 1 , which is a schematic diagram of an LCD device  10  with a stripe tri-gate pixel structure in the prior art. For clear illustration, the LCD device  10  only includes a source driver  100 , a gate driver  102 , a timing controller  104 , an LCD panel  106 , data lines S 1 -Sm, scan lines G 1 -Gn and a pixel matrix Mat_S. The timing controller  104  utilizes a horizontal synchronization signal Hsync and an output enable signal Ena to control the source driver  100  and the gate driver  102 , respectively, to generate data driving signals Sig_S 1 -Sig_Sm and gate driving signals Sig_G 1 -Sig_Gn, so as to charge the pixel matrix Mat_S. In the pixel matrix Mat_S, each pixel includes a red subpixel R, a green subpixel G and a blue subpixel B, and each subpixel includes a transistor and a capacitor, which are denoted by blocks for simplicity. In one cycle of the horizontal synchronization signal Hsync, the data driving signals Sig_S 1 -Sig_Sm charge a corresponding pixel, respectively. For example, in one cycle of the horizontal synchronization signal Hsync, the data driving signal Sig_S 1  charges a pixel corresponding to the data line S 1  and the scan lines G 1 -G 3 , i.e. a red subpixel, a green subpixel and a blue subpixel. Under such a situation, since charging period for a subpixel in the tri-gate structure is only a third of that of the single gate structure, the subpixels are likely charged insufficiently. 
         [0006]    Please refer to  FIG. 2 , which is a schematic diagram of the LCD device  10  driving subpixels corresponding to the data line S 1  in frames F 1 , F 2 .  FIG. 2  indicates charging orders of the scan lines G 1 -Gn and corresponding subpixels thereof, and a waveform of the data driving signal Sig_S 1  in horizontal synchronization cycles Hsync_C 1 , Hsync_C 2 . As shown in  FIG. 2 , since the data driving signal Sig_S 1  has circuit RC delay, the data driving signal Sig_S 1  needs a period to reach a settled state when the data driving signal Sig_S 1  has polarity change. Besides, subpixels within the same horizontal synchronization cycle have the same charging period. As a result, for subpixels corresponding to the same horizontal synchronization cycle, a subpixel with the most prior charging order of the data driving signal Sig_S 1  is charged insufficiently. For example, in the frame F 1 , the charging orders are scan lines G 1 →G 2 →G 3  and subpixels R→G→B in the horizontal synchronization cycle Hsync_C 1 . Since the data driving signal Sig_S 1  does not reach the settled state when charging the red subpixel R, the red subpixel R is charged less sufficiently compared to the green subpixel G and the blue subpixel B. Similarly, in the frame F 2 , since the red subpixel R is still the subpixel with the most prior charging order of the data driving signal Sig_S 1  in the horizontal synchronization cycle Hsync_C 1 , the red subpixel R is still charged less sufficiently. By the same token, the red subpixels R corresponding to the scan line G 1  and the data lines S 1 -Sm are all charged less sufficiently, causing the LCD device  10  to exhibit light and dark lines and color inequality due to charging inequality among subpixels. 
         [0007]    Please refer to  FIG. 3A  and  FIG. 3B , which are schematic diagrams of utilizing double gate pulses and overlap gate pulse to drive subpixels in the prior art, respectively. In order to eliminate charging inequality, the prior art utilizes the double gate pulses or the overlap gate pulse to pre-charge the subpixels, such that the subpixels are not charged unequally when the data driving signals charge the subpixels. As shown in  FIG. 3A , compared to the driving method shown in  FIG. 2 , the double gate pulses pre-charges the subpixels before the horizontal synchronization cycle Hsync_D 1 , Hsync_D 2 , such that the LCD device  10  does not have light and dark lines and color inequality due to charging inequality among subpixels in the horizontal synchronization cycle Hsync_C 1 , Hsync_C 2 . Similarly, as shown in  FIG. 3B , the overlap gate pulse pre-charges the subpixels before a third of the horizontal synchronization cycle Hsync_C 1 , i.e. charging period for a subpixel, such that the LCD device  10  does not have light and dark lines and color inequality due to charging inequality among subpixels in the horizontal synchronization cycle Hsync_C 1 , Hsync_C 2 . 
         [0008]    However, driving methods of the double gate pulses and the overlap gate pulse in the prior art need extra pulses to avoid charging inequality, which increase power consumption and inconvenience. Thus, there is a need for improvement. 
       SUMMARY OF THE INVENTION 
       [0009]    It is therefore an objective of the present invention to provide a driving module and driving method. 
         [0010]    The present invention discloses a driving module for a liquid crystal display device. The driving module includes a data line signal processing unit, for generating a plurality of data driving signals, a scan line signal processing unit, for generating a plurality of gate driving signals, and a control unit, for controlling the data line signal processing unit and the scan line signal processing unit, to charge a plurality of subpixels corresponding to a data line with different charging orders in different frames. 
         [0011]    The present invention further discloses a driving method for liquid crystal display device. The driving method includes the steps of providing a plurality of data driving signals, and providing a plurality of gate driving signals, and charging a plurality of subpixels corresponding to a data line with different charging orders indifferent frames according to the plurality of data driving signals and the plurality of gate driving signals. 
         [0012]    The present invention further discloses a driving module for a liquid crystal display device. The driving module includes a data line signal processing unit, for generating a plurality of data driving signals, a scan line signal processing unit, for generating a plurality of gate driving signals, and a control unit, for controlling the data line signal processing unit and the scan line signal processing unit, to charge a plurality of subpixels corresponding to a data line and a horizontal synchronization cycle with different charging periods in a same frame. 
         [0013]    The present invention further discloses a driving method for liquid crystal display device. The driving method including the steps of providing a plurality of data driving signals, and providing a plurality of gate driving signals, and charging a plurality of subpixels corresponding to a data line and a horizontal synchronization cycle with different charging periods in a same frame according to the plurality of data driving signals and the plurality of gate driving signals. 
         [0014]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]      FIG. 1  is a schematic diagram of a LCD device with a stripe tri-gate pixel structure in the prior art. 
           [0016]      FIG. 2  is a schematic diagram of the LCD device driving subpixels corresponding to a data line in frames. 
           [0017]      FIG. 3A  and  FIG. 3B  are schematic diagrams of utilizing double gate pulses and overlap gate pulse to drive subpixels in the prior art, respectively. 
           [0018]      FIG. 4  is a schematic diagram of a driving module according to an embodiment of the present invention. 
           [0019]      FIG. 5A  to  FIG. 5C  are schematic diagrams of the driving module of  FIG. 4  charging subpixels with different charging orders in different frames. 
           [0020]      FIG. 6  is a schematic diagram of the driving module of  FIG. 4  charging subpixels with different charging period in the same frame. 
           [0021]      FIG. 7  is a schematic diagram of the present invention applied in an LCD device with a zigzag tri-gate pixel structure in the prior art. 
           [0022]      FIG. 8  is a schematic diagram of a driving process according to an embodiment of the present invention. 
           [0023]      FIG. 9  is a schematic diagram of a driving process according to another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0024]    Please refer to  FIG. 4 , which is a schematic diagram of a driving module  40  according to an embodiment of the present invention. For clear illustration, elements with the same function and structure of those shown in  FIG. 1  are denoted by the same figures and symbols in  FIG. 1 . The driving module  40  drives the pixel matrix Mat_S via the data lines S 1 -Sm and the scan line G 1 -Gn, to avoid charging inequality. The driving module  40  includes a data line signal processing unit  400 , a scan line signal processing unit  402  and a control unit  404 . The control unit  404  generates the horizontal synchronization signal Hsync and the output enable signal Ena, to control the data line signal processing unit  400  and the scan line signal processing unit  402 , so as to output the data driving signals Sig_S 1 -Sig_Sm to the data lines S 1 -Sm, and output the gate driving signals Sig_G 1 -Sig_Gn to the scan lines G 1 -Gn. In order to avoid charging inequality, the control unit  404  controls the data line signal processing unit  400  and the scan line signal processing unit  402 , to charge subpixels corresponding to the same data line with different charging orders indifferent frames, or to charge subpixels corresponding to the same data line and the same horizontal synchronization cycle with different charging periods in a same frame. 
         [0025]    In short, the present invention adjusts the data driving signals Data_ 1 -Data_p and the gate driving signals Gate_ 1 -Gate_q, to charge subpixels corresponding to the same data line with different charging orders in different frames, or to charge subpixels corresponding to the same data line and the same horizontal synchronization cycle with different charging periods in a same frame. 
         [0026]    For example, please refer to  FIG. 5A  to  FIG. 5C , which are schematic diagrams of the driving module  40  of  FIG. 4  charging subpixels with different charging orders indifferent frames. As shown in  FIG. 5A , the driving module  40  utilizes the corresponding data driving signals to charge subpixels with reverse charging orders in two adjacent frames. In detail, in the frame F 1 , a charge charging order of the horizontal synchronization cycle Hsync_C 1  is scan lines G 1 →G 2 →G 3  and subpixels R→G→B, and in the frame F 2 , the data driving signal Sig_S 1  charges subpixels with a reverse charging order of that of the frame F 1 , i.e. a charge charging order in the horizontal synchronization cycle Hsync_C 1  is scan lines G 3 →G 2 →G 1  and subpixels B→G→R, and in the frame F 3 , the data driving signal Sig_S 1  charges subpixels with a reverse charging order of that of the frame F 2 , i.e. a charge charging order in the horizontal synchronization cycle Hsync_C 1  is scan lines G 1 →G 2 →G 3  and subpixels R→G→B. As a result, the red subpixels R and the blue subpixels B are subpixels charged less sufficiently in turn, which can prevent light and dark lines and color inequality due to charging inequality among subpixels. 
         [0027]    Similarly, as shown in  FIG. 5B , the driving module  40  utilizes the corresponding data driving signals to sequentially charge each subpixel with a most prior charging order in adjacent frames according to a charging priority. In detail, in the frame F 1 , the data driving signal Sig_S 1  charges the red subpixel R with the most prior charging order, i.e. a charge charging order of the horizontal synchronization cycle Hsync_C 1  is scan lines G 1 →G 2 →G 3  and subpixels R→G→B, and in the frame F 2 , the data driving signal Sig_S 1  charges the green subpixel G with the most prior charging order, i.e. a charge charging order of the horizontal synchronization cycle Hsync_C 1  is scan lines G 2 →G 3 →G 1  and subpixels G→B→R, and in the frame F 3 , the data driving signal Sig_S 1  charges the blue subpixel B with the most prior charging order, i.e. a charge charging order of the horizontal synchronization cycle Hsync_C 1  is scan lines G 3 →G 1 →G 2  and subpixels B→R→G. In other words, the data driving signal Sig_S 1  charges the subpixels with a charging order of subpixels R→G→B as the charging priority. As a result, the red subpixel R, the green subpixel G and the blue subpixel B are subpixels charged less sufficiently in turn, which can prevent light and dark lines and color inequality due to charging inequality among subpixels. 
         [0028]    As shown in  FIG. 5C , after the driving module  40  utilizes the corresponding data driving signals to sequentially charge each subpixel with the most prior charging order, the driving module  40  can further utilize the data driving signals to sequentially charge each subpixel with the most prior charging order according to a reverse charging order of the charging priority. In detail, difference between operations of  FIG. 5C  and  FIG. 5B  is: after the data driving signal Sig_S 1  charges subpixels with a charging order of subpixels R→G→B as the charging priority, the data driving signal Sig_S 1  charges subpixels with a charging order of subpixels B→G→R as the charging priority in frames F 4 -F 6 , i.e. the data driving signal Sig_S 1  charges subpixels with a charging order of subpixels R→G→B→B→G→R as the charging priority. As a result, other than the red subpixel R, the green subpixel G and the blue subpixel B are subpixels charged less sufficiently in turn, subpixels are more equally charged insufficiently, to prevent light and dark lines and color inequality due to charging inequality among subpixels. 
         [0029]    On the other hand, please refer to  FIG. 6 , which is a schematic diagram of the driving module  40  of  FIG. 4  charging subpixels with different charging periods in the same frame. As shown in  FIG. 6 , the driving module  40  utilizes corresponding data driving signals to charge a subpixel with a most prior charging order with a longest charging period in the same frame. In detail, the prior art charges subpixels with a ratio Ratio_ 1 , and the exemplary embodiment charges subpixels with a ratio Ratio_ 2  or Ratio_ 3 . The prior art charges subpixels with the ratio Ratio_ 1 , i.e. each subpixel R, G, or B is charged with the same charging period in the horizontal synchronization cycle Hsync_C 1 . In comparison, the exemplary embodiment charges subpixels with a ratio Ratio_ 2  or Ratio_ 3 , i.e. the red subpixel R is charged with a charging period longer than that of the subpixel G or B in the horizontal synchronization cycle Hsync_C 1 , whereas the green subpixel G is charged with a charging period the same with that of the blue subpixel B when the exemplary embodiment charges subpixels with a ratio Ratio_ 3 . As a result, by increasing the charging period for the red subpixel R and decreasing the charging periods for the green subpixel G and the blue subpixel B, the present invention can solve the problem that the red subpixel R is charged less sufficiently, to prevent light and dark lines and color inequality due to charging inequality among subpixels. 
         [0030]    Noticeably, the above description is only an embodiment of the present invention. The spirit of the present invention is to charge subpixels corresponding to the same data line with different charging orders in different frames, such that each subpixel is charged less sufficiently in turn, or to charge subpixels corresponding to the same data line and the same horizontal synchronization cycle with different charging periods in the same frame, such that the subpixel with the most prior charging order is charged with the longest charging period, to prevent light and dark lines and color inequality due to charging inequality among subpixels. Those skilled in the art may make alterations or modifications according to the concept of the present invention. For example, an arrangement of subpixels is not limited to an arrangement of red subpixel, green subpixel, blue subpixel, and the present invention is not limited to the stripe tri-gate pixel structure, and can be applied to a zigzag tri-gate pixel structure (as shown in  FIG. 7 , in a pixel matrix Mat_Z, subpixels corresponding to the data lines S 1 -Sm are interlaced between two subpixel columns), or the dual gate structure. Noticeably, how the scan line signal processing unit  402  outputs the gate driving signals Sig_G 1 -Sig_Gn and how the data line signal processing unit  400  and the control unit  404  are realized do not affect the scope of the present invention, as long as the subpixels corresponding to the same data line are charged with different charging orders in different frames, or subpixels corresponding to the same data line and the same horizontal synchronization cycle are charged with different charging periods in a same frame, to prevent light and dark lines and color inequality due to charging inequality among subpixels. 
         [0031]    Noticeably, the driving module  40  is only utilized for illustrating operations of the present invention, and is not limited to be realized by software or hardware. Those skilled in the art may make proper modifications or adjust conventional driving modules to realize the driving module  40  according to system requirements. For example, if the source driver  100  and the gate driver  102  in  FIG. 1  only have a signal amplification function (i.e. the data driving signals Sig_S 1 -Sig_Sm and the gate driving signals Sig_G 1 -Sig_Gn sent to the scan lines G 1 -Gn are generated by the timing controller  104 ), the function of the driving module  40  can be achieved by modifying a signal output sequence of the timing controller  104 , or by modifying internal circuits of the source driver  100  and the gate driver  102  instead of the signal output sequence of the timing controller  104 . Otherwise, if the source driver  100  and the gate driver  102  in  FIG. 1  have both signal amplification and processing functions (i.e. the timing controller  104  only outputs display data and timing), the function of the driving module  40  can be achieved by modifying signal processing logic of the source driver  100  and the gate driver  102 . All of the above description is directed to charging subpixels corresponding to the same data line with different charging orders in different frames, or charging subpixels corresponding to the same data line and the same horizontal synchronization cycle with different charging periods in the same frame. 
         [0032]    Operations of the driving module  40  charging subpixels corresponding to the same data line with different charging orders in different frames can be summarized into a driving process  80 . As shown in  FIG. 8 , the driving process  80  includes the following steps:
       Step  800 : Start.   Step  802 : Provide the data driving signals Sig_S 1 -Sig_Sm.   Step  804 : Provide the gate driving signals Sig_G 1 -Sig_Gn, and charge subpixels corresponding to a data line with different charging orders in different frames according to the data driving signals Sig_S 1 -Sig_Sm and the gate driving signals Sig_G 1 -Sig_Gn.   Step  806 : End.       
 
         [0037]    Operations of the driving module  40  charging subpixels corresponding to the same data line and the same horizontal synchronization cycle with different charging periods in the same frame can be summarized into a driving process  90 . As shown in  FIG. 9 , the driving process  90  includes:
       Step  900 : Start.   Step  902 : Provide the data driving signals Sig_S 1 -Sig_Sm.   Step  904 : Provide the gate driving signals Sig_G 1 -Sig_Gn, and charge subpixels corresponding to the same data line and the same horizontal synchronization cycle with different charging periods in the same frame according to the data driving signals Sig_S 1 -Sig_Sm and the gate driving signals Sig_G 1 -Sig_Gn.   Step  906 : End.       
 
         [0042]    For the LCD panel with the tri-gate structure, subpixels are charged with the double gate pulses or the overlap gate pulse in the prior art to avoid charging inequality by increasing pulses, which increase power consumption and inconvenience. In comparison, without increasing pulses, the present invention can charge subpixels corresponding to the same data line with different charging orders in different frames, such that each subpixel is charged less sufficiently in turn, or charge subpixels corresponding to the same data line and the same horizontal synchronization cycle with different charging periods in a same frame, such that the subpixel with the most prior charging order is charged with the longest charging period, to prevent light and dark lines and color inequality due to charging inequality among subpixels. 
         [0043]    To sum up, without increasing pulses, the present invention can charge subpixels corresponding to the same data line with different charging orders in different frames, or charge subpixels corresponding to the same data line and the same horizontal synchronization cycle with different charging periods in a same frame, to avoid light and dark lines and color inequality due to charging inequality among subpixels. 
         [0044]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.