Abstract:
A light-emitting diode (LED) package structure and a packaging method thereof are provided. The packaging method includes: forming first conductive layers on a silicon substrate, and forming a reflection cavity and electrode via holes from a top surface of the silicon substrate; forming a reflection layer on predetermined areas of a surface of the reflection cavity, and forming second conductive layers and metal layers on surfaces of the electrode via holes; and mounting a chip and forming an encapsulant, so as to fabricate the LED package structure. In the present invention, there is no need to perform at least two plating processes for connecting upper and lower conductive layers of the silicon substrate in the electrode via holes, and the problem of poor connection of the conductive layers in the electrode via holes can be avoided, thereby making the fabrication processes simplified and time-effective and also improving the overall production yield.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to package structures and packaging methods thereof, and more particularly, to a light-emitting diode (LED) package structure and a packaging method thereof. 
         [0003]    2. Description of Related Art 
         [0004]    Applying semiconductor fabrication processes to silicon (Si) wafer advantageously allows massive production of LED submounts, and also favors cost reduction and yield increase for package manufacturers as well as provides packages with better heat dissipating performance. 
         [0005]    Taiwanese Patent No. I331415 has disclosed an LED packaging technique in the use of the semiconductor fabrication processes. According to the specification and drawings of this patent, a silicon substrate covered with insulating layers thereon is provided, and conductive layers and electrodes connected thereto are formed on upper and lower surfaces of the silicon substrate and in electrode via holes of the silicon substrate. Then, a chip is mounted on the conductive layer formed on the upper surface of the silicon substrate, and wire-bonding and encapsulating processes are subsequently performed. 
         [0006]    However, the above patent&#39;s technique requires the conductive layers and the electrodes to be formed on the upper and lower surfaces of the silicon substrate and to be electrically connected to each other in the electrode via holes of the silicon substrate. This must use the relatively complicated sputter process to form the conductive layers, thereby making the packaging technique time-ineffective and cost-ineffective. Further, it is found that the electrical connection between the conductive layers and the electrodes in the electrode via holes of the silicon substrate is not good enough when actually carrying out the above patent&#39;s technique. That is, it is not easy for the conductive layers and the electrodes to be completely electrically connected to each other in the electrode via holes of the silicon substrate. This directly impairs the light emitting effect of the chip and adversely affects the production yields. Moreover, during the encapsulating process to form a molding compound for filling the electrode via holes of the silicon substrate, a mold flash problem easily arises. 
         [0007]    Therefore, how to overcome the above drawbacks of the conventional technology is becoming one of the most popular issues in the art. 
       SUMMARY OF THE INVENTION 
       [0008]    In view of the drawbacks of the prior art, the present invention provides a light-emitting diode (LED) package structure, comprising: a silicon substrate including a first surface, a second surface opposing to the first surface, a reflection cavity formed in the silicon substrate and communicating with the first surface, and a plurality of electrode via holes formed through a bottom surface of the reflection cavity and the second surface; first conductive layers formed on the second surface of the silicon substrate; first insulating layers formed on the first surface of the silicon substrate, a surface of the reflection cavity and surfaces of the electrode via holes; a reflection layer formed on the first insulating layers located on predetermined areas of the surface of the reflection cavity; second conductive layers formed on the surfaces of the electrode via holes and connected to the first conductive layers; metal layers formed on the second conductive layers; a chip mounted in the reflection cavity and electrically connected to the metal layers; and an encapsulant formed in the reflection cavity and the electrode via holes, and covering the first insulating layers, the reflection layer, the metal layers and the chip. 
         [0009]    In order to fabricate the LED package structure, the present invention also provides a packaging method of the LED package structure, comprising the steps of: providing a silicon substrate having a first surface and a second surface opposing to the first surface, and forming first conductive layers on the second surface of the silicon substrate; forming a reflection cavity from the first surface into the silicon substrate, and forming a plurality of electrode via holes penetrating through a bottom surface of the reflection cavity and the second surface of the silicon substrate; forming first insulating layers on the first surface of the silicon substrate, a surface of the reflection cavity and surfaces of the electrode via holes; forming a reflection layer on the first insulating layers located on predetermined areas of the surface of the reflection cavity; forming second conductive layers on the surfaces of the electrode via holes, wherein the second conductive layers are connected to the first conductive layers; forming metal layers on the second conductive layers; mounting a chip in the reflection cavity, and electrically connecting the chip to the metal layers; and forming an encapsulant in the reflection cavity and the electrode via holes, allowing the encapsulant to cover the first insulating layers, the reflection layer, the metal layers and the chip. 
         [0010]    Compared to the conventional technology, the present invention does not need to perform at least two plating processes for connecting upper and lower conductive layers of the silicon substrate in the electrode via holes, and the problem of poor connection of the conductive layers in the electrode via holes can be avoided, thereby making the fabrication processes simplified and time-effective and also improving the overall production yield. Moreover, the present invention allows the electrode via holes to be covered by the first conductive layers, such that a mold flash problem does not occur during the subsequent process of forming the encapsulant. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0011]    The present invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein: 
           [0012]      FIGS. 1A to 1T  are schematic diagrams illustrating an LED package structure and a packaging method thereof according to the present invention, wherein FIG.  1 K′ is a top view of  FIG. 1K , and FIG.  1 T′ is a schematic diagram showing a flip chip provided in a reflection cavity. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0013]    The following illustrative embodiments are provided to illustrate the disclosure of the present invention; those in the art can apparently understand these and other advantages and effects after reading the disclosure of this specification. The present invention can also be performed or applied by other different embodiments. Some terms such as “first”, “second” and “bottom surface” used in the specification are only for easy illustration but not for limiting the scope of the present invention. The details of the specification may be on the basis of different points and applications, and numerous modifications and variations can be devised without departing from the spirit of the present invention. 
         [0014]      FIGS. 1A to 1T  illustrate a light-emitting diode (LED) package structure and a packaging method thereof according to the present invention. 
         [0015]    Referring to  FIGS. 1A to 1E , firstly, a silicon substrate  10  having a first surface  100  and a second surface  101  opposing to the first surface  100  is provided. First conductive layers  11   a ,  11   b  are formed on the second surface  101  of the silicon substrate  10 . 
         [0016]    More specifically, as shown in  FIG. 1A , a dielectric layer  20   a  (such as SiO 2 ) and another dielectric layer  21   a  (such as SiNx) can be sequentially formed on the first surface  100  of the silicon substrate  10 . Similarly, a dielectric layer  20   b  (such as SiO 2 ) and another dielectric layer  21   b  (such as SiNx) can also be sequentially formed on the second surface  101  of the silicon substrate  10 . It should be understood that there may only be formed one dielectric layer on either surface of the silicon substrate  10  depending on the requirements. 
         [0017]    As shown in  FIGS. 1B and 1C , a dry film  22  is applied on the dielectric layers  20   b ,  21   b  on the second surface  101  of the silicon substrate  10  and is subjected to a patterning process so as to form a patterned dry film  22 ′. Then, portions of the dielectric layers  20   b ,  21   b , which are not covered by the patterned dry film  22 ′, are removed to partly expose the second surface  101  of the silicon substrate  10 . 
         [0018]    As shown in  FIG. 1D , the first conductive layers  11   a ,  11   b  are deposited on the exposed parts of the second surface  101  of the silicon substrate  10 . Further, another first conductive layer  11   c  can be deposited on the patterned dry film  22 ′ that is located on a central area of the second surface  101  of the silicon substrate  10 . 
         [0019]    As shown in  FIG. 1E , the patterned dry film  22 ′ and the dielectric layers  20   b ,  21   b  covered thereby are removed, that is, the first conductive layer  11   c , the patterned dry film  22 ′ and the dielectric layers  20   b ,  21   b  remaining on the central area of the second surface  101  of the silicon substrate  10  are stripped, such that a portion (or the central area) of the second surface  101  of the silicon substrate  10  can be exposed between the first conductive layers  11   a ,  11   b.    
         [0020]    Referring to  FIGS. 1F to 1L , after forming the first conductive layers  11   a ,  11   b , a reflection cavity  12  is provided on the first surface  100  of the silicon substrate  10 , and a plurality of electrode via holes  13   a ,  13   b  are formed through the first and second surfaces  100 ,  101  of the silicon substrate  10 . 
         [0021]    More specifically, as shown in  FIG. 1F , patterned photo resist layers  23   a ,  23   b  are formed on the first surface  100  of the silicon substrate  10  and have an opening  24  therebetween, wherein the opening  24  exposes a portion of the dielectric layer  21   a . The exposed portion of dielectric layer  21   a  has a projection area beyond an area of the portion of the second surface  101  exposed from the first conductive layers  11   a ,  11   b . Then, the portions of the dielectric layers  20   a ,  21   a  exposed from the opening  24  are removed by e.g. etching, such that a portion of the first surface  100  of the silicon substrate  10  is exposed, as shown in  FIG. 1G . 
         [0022]    As shown in  FIG. 1H , the patterned photo resist layers  23   a ,  23   b  further serve as a mask, and etching is performed to form the reflection cavity  12  (such as a trapezoid cavity) into the silicon substrate  10 , wherein the reflection cavity  12  communicates with the first surface  100  of the silicon substrate  10 . 
         [0023]    As shown in  FIG. 1I , after forming the reflection cavity  12 , the patterned photo resist layers  23   a ,  23   b  are removed, and the dielectric layers  20   a ,  21   a  covered by the patterned photo resist layers  23   a ,  23   b  are also removed. With those layers being removed, a first resist layer  25  (such as parylene) can be applied on the first surface  100  of the silicon substrate  10  and a surface of the reflection cavity  12 , and then is subjected to patterning (e.g. by laser) to form first resist openings  250  by which portions of a bottom surface of the reflection cavity  12  are exposed, as shown in  FIG. 1J . 
         [0024]    After forming the first resist layer  25 , reactive-ion etching (RIE) can be performed on the exposed portions of the bottom surface of the reflection cavity  12  to form the plurality of electrode via holes  13   a ,  13   b  penetrating through the bottom surface of the reflection cavity  12  and the second surface  101  of the silicon substrate  10 , thereby exposing portions of the first conductive layers  11   a ,  11   b , as shown in FIG  1 K. Further as shown in the top view of FIG.  1 K′, the electrode via holes  13   a ,  13   b  can have an oval shape or any other shape such as rectangle. According to the cross-section line  1 K- 1 K of FIG.  1 K′, the silicon substrate  10  can be divided into sections  10   a ,  10   b ,  10   c , as shown in  FIG. 1K . 
         [0025]    After forming the electrode via holes  13   a ,  13   b , the first resist layer  25  can be removed, as shown in  FIG. 1L . 
         [0026]    As shown in  FIG. 1M , after removing the first resist layer  25 , first insulating layers  14   a ,  14   b ,  14   c  are formed on the first surface  100  of the silicon substrate  10 , in the reflection cavity  12  and on walls of the electrode via holes  13   a ,  13   b . The first insulating layers  14   a ,  14   b ,  14   c  can have their bottom portions being in contact with the first conductive layers  11   a ,  11   b.    
         [0027]    Further as shown in  FIG. 1M , the first insulating layers  14   a ,  14   b ,  14   c  can be applied respectively on the silicon substrate sections  10   a ,  10   b ,  10   c . More specifically, the first insulating layer  14   a  is connected to the first conductive layer  11   a  by the wall of the electrode via hole  13   a . The first insulating layer  14   b  is connected to the first conductive layers  11   a ,  11   b  by the walls of the electrode via holes  13   a ,  13   b . The first insulating layer  14   c  is connected to the first conductive layer  11   b  by the wall of the electrode via hole  13   b . And, the first insulating layers  14   a ,  14   b ,  14   c  can be made of SiO 2 . 
         [0028]    Referring to  FIGS. 1N to 1O , with the first insulating layers  14   a ,  14   b ,  14   c  being provided, a reflection layer is formed on the first insulating layers  14   a ,  14   b ,  14   c  and on walls of the reflection cavity  12 . The reflection layer can comprise metal films and second insulating layers. 
         [0029]    As shown in  FIG. 1N , metal films  15   a ,  15   b ,  15   c  (such as aluminum) are coated on the first insulating layers  14   a ,  14   b ,  14   c . More specifically, the metal films  15   a ,  15   c  are located on the walls of the reflection cavity  12 , and the metal film  15   b  is located on a central area of the bottom surface of the reflection cavity  12 . 
         [0030]    As shown in  FIG. 10 , second insulating layers  16   a ,  16   b ,  16   c  (made of such as SiO 2 ) are formed on the metal films  15   a ,  15   b ,  15   c , and are respectively connected to the first insulating layers  14   a ,  14   b ,  14   c  so as to completely cover the metal films  15   a ,  15   b ,  15   c . It should be understood that, depending on practical requirements, the metal film  15   b  and the second insulating layer  16   b  located on the bottom surface of the reflection cavity  12  may not be formed. 
         [0031]    Referring to  FIGS. 1P to 1Q , after forming the second insulating layers  16   a ,  16   b ,  16   c , second conductive layers are formed on the first insulating layers  14   a ,  14   b ,  14   c  or the second insulating layers  16   a ,  16   b ,  16   c , and can be connected to the first conductive layers by the electrode via holes. 
         [0032]    As shown in  FIG. 1P , second resist layers  26   a ,  26   b ,  26   c ,  26   d  (such as parylene) are applied on the first or second insulating layers. More specifically, the second resist layer  26   a  covers the first insulating layer  14   a  and the second insulating layer  16   a . The second resist layer  26   d  covers the first insulating layer  14   c  and the second insulating layer  16   c . The second resist layers  26   b ,  26   c  are located on peripheral areas of the second insulating layer  16   b , with a central area of the second insulating layer  16   b  being exposed. 
         [0033]    As shown in  FIG. 1Q , after the second resist layers  26   a ,  26   b ,  26   c ,  26   d  are applied, a second conductive material is formed to cover the second resist layers  26   a ,  26   b ,  26   c ,  26   d  and the walls of the electrode via holes  13   a ,  13   b . Then, a laser drilling process is performed to remove portions of the second resist layers  26   a ,  26   d  on peripheral areas of the electrode via holes  13   a ,  13   b  and remove the second conductive material on those portions of the second resist layers  26   a ,  26   d , so as to form second conductive layers  17   a ,  17   b ,  17   c ,  17   d ,  17   e ,  17   f ,  17   g.    
         [0034]    The second conductive layers  17   a ,  17   b  are formed by laser drilling that also removes portions of the second resist layers  26   a ,  26   d , such that a gap is left between the second conductive layers  17   a ,  17   b , and a portion of the first insulating layer  14   a  is exposed through the gap. Similarly, a portion of the second resist layer  26   b  is exposed through a gap between second conductive layers  17   c ,  17   d . A portion of the second resist layer  26   c  is exposed through a gap between second conductive layers  17   d ,  17   e . And, a portion of the first insulating layer  14   c  is exposed through a gap between the second conductive layers  17   f ,  17   g.    
         [0035]    It should be understood that, the second conductive layers  17   b ,  17   c  and the second conductive layers  17   e ,  17   f  can be connected to the first conductive layer  11   a  and the first conductive layer  11   b  respectively by the electrode via hole  13   a  and the electrode via hole  13   b . Moreover, the second conductive layers  17   b ,  17   c  and the second conductive layers  17   e ,  17   f  can be protruded upwardly on the bottom surface of the reflection cavity  12  from the first conductive layers  11   a ,  11   b.    
         [0036]    Referring to  FIG. 1R to 1S , with the second conductive layers  17   a ,  17   b ,  17   c ,  17   d ,  17   e ,  17   f ,  17   g  being provided, metal layers are further formed on the second conductive layers  17   b ,  17   c ,  17   e ,  17   f  that are connected to the first conductive layers  11   a ,  11   b  by the electrode via holes  13   a ,  13   b.    
         [0037]    As shown in  FIG. 1R , an electroplating process is performed to form metal layers  18   a ,  18   b ,  18   c ,  18   d ,  18   e ,  18   f ,  18   g  on the second conductive layers  17   a ,  17   b ,  17   c ,  17   d ,  17   e ,  17   f ,  17   g.    
         [0038]    Then, as shown in  FIG. 1S , the second resist layers  26   a ,  26   b ,  26   c ,  26   d  and the second conductive layers  17   a ,  17   g  and metal layers  18   a ,  18   g  thereon are removed. In other words, the second conductive layers  17   b ,  17   c  and the metal layers  18   b ,  18   c , which are protruded on the bottom surface of the reflection cavity  12  from the first conductive layer  11   a  along the electrode via hole  13   a , are retained. And, the second conductive layers  17   e ,  17   f  and the metal layers  18   e ,  18   f , which are protruded on the bottom surface of the reflection cavity  12  from the first conductive layer  11   b  along the electrode via hole  13   b , are retained. 
         [0039]    Subsequently, referring to  FIG. 1T , a chip  19  is mounted in the reflection cavity  12  and is electrically connected to the metal layers  18   b ,  18   f . For example, the chip  19  can be mounted on the second conductive layer  17   d  and the metal layer  18   d  that are provided on the second insulating layer  16   b , and can be electrically connected to the metal layers  18   b ,  18   f  by e.g. bonding wires. Alternatively, the chip  19  can be mounted on and electrically connected to the metal layers  18   c ,  18   e  in a flip-chip manner, as shown in FIG.  1 T′. In such case, the second conductive layer  17   d  and the metal layer  18   d  are removed. 
         [0040]    Finally, an encapsulant  30  is formed in the reflection cavity  12  and the electrode via holes  13   a ,  13   b  to cover the first insulating layers, the reflection layer, the metal layers and the chip. 
         [0041]    Further as shown in  FIGS. 1T ,  1 T′, more specifically, the encapsulant  30  covers the exposed first insulating layers  14   a ,  14   c , the exposed second insulating layers  16   a ,  16   b ,  16   c , the exposed second conductive layers  17   b ,  17   c ,  17   d ,  17   e ,  17   f , the exposed metal layers  18   b ,  18   c ,  18   d ,  18   e ,  18   f  and the chip  19 . The encapsulant  30  also fills the electrode via holes  13   a ,  13   b.    
         [0042]    The LED package structure provided in the present invention, as shown in  FIG. 1S ,  1 T or  1 T′, comprises: a silicon substrate (having sections  10   a ,  10   b ,  10   c ) including a first surface  100 , a second surface  101 , a reflection cavity  12 , and electrode via holes  13   a ,  13   b  penetrating through the reflection cavity  12  and the second surface  101 ; first conductive layers  11   a ,  11   b  formed on the second surface  101  and optionally covering the electrode via holes  13   a ,  13   b , wherein a portion of the second surface  101  is exposed from the first conductive layers  11   a ,  11   b ; first insulating layers  14   a ,  14   b ,  14   c  formed on the first surface  100 , surfaces of the reflection cavity  12  and surfaces of the electrode via holes  13   a ,  13   b , wherein the first insulating layers  14   a ,  14   b ,  14   c  are connected to the first conductive layers  11   a ,  11   b ; metal films  15   a ,  15   b ,  15   c  formed on the first insulating layers  14   a ,  14   b ,  14   c  and in a central region and peripheral regions of the reflection cavity  12 ; and second insulating layers  16   a ,  16   b ,  16   c  formed on the metal films  15   a ,  15   b ,  15   c  and connected to the first insulating layers  14   a ,  14   b ,  14   c.    
         [0043]    The LED package structure further comprises: a second conductive layer  17   b  formed on the first insulating layer  14   a  and connected to the first conductive layer  11   a  by the electrode via hole  13   a ; a second conductive layer  17   c  formed on the first insulating layer  14   b  in the electrode via hole  13   a  and connected to the first conductive layer  11   a  by the electrode via hole  13   a ; a second conductive layer  17   e  formed on the first insulating layer  14   b  in the electrode via hole  13   b  and connected to the first conductive layer  11   b  by the electrode via hole  13   b ; a second conductive layer  17   f  formed on the first insulating layer  14   c  and connected to the first conductive layer  11   b  by the electrode via hole  13   b ; and a second conductive layer  17   d  only formed on the second insulating layer  16   b.    
         [0044]    The LED package structure further comprises: metal layers  18   b ,  18   c  formed on the second conductive layers  17   b ,  17   c  that are connected to the first conductive layer  11   a  by the electrode via hole  13   a ; and metal layers  18   e ,  18   f  formed on the second conductive layers  17   e ,  17   f  that are connected to the first conductive layer  11   b  by the electrode via hole  13   b.    
         [0045]    The LED package structure further comprises: a chip  19  mounted on metal layer  18   d  formed on the second insulating layer  16   b , wherein the chip  19  is electrically connected to the metal layers  18   b ,  18   f ; and an encapsulant  30  covering the exposed first insulating layers  14   a ,  14   c , the exposed second insulating layers  16   a ,  16   b ,  16   c , the exposed second conductive layers  17   b ,  17   c ,  17   d ,  17   e ,  17   f , the exposed metal layers  18   b ,  18   c ,  18   e ,  18   f , and the chip  19 , wherein the encapsulant  30  fills the electrode via holes  13   a ,  13   b.    
         [0046]    Compared to the conventional technology, the present invention advantageously uses a deposition technique to form conductive layers, without having to connect upper and lower conductive layers in electrode via holes, such that the conventional problems of impaired connection and poor light emitting effect do not arise and also the process complexity and cost can be reduced, thereby greatly improving the production yield. Moreover, the present invention allows the electrode via holes to be covered by the first conductive layers, such that a mold flash process does not occur during the subsequent problem of forming the encapsulant. 
         [0047]    The invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.