Abstract:
A low error, plugged test lead detecting circuit for providing accurate current measurement and the method using the same. When a test lead of the plugged detecting circuit is plugged into a split contact jack of the plugged detecting circuit, the circuit stops oscillating during operations for a test lead detecting mode or a fuse open detecting mode. During the test lead detecting mode, if the test lead is plugged into the split contact jack, the oscillating unit stops automatically and outputs a quiescent state. Conversely, if the test lead is unplugged into the split contact jack, the oscillating unit generates a pre-determined frequency pulse according to the oscillating unit. During the fuse open detecting mode, the test lead is plugged into the split contact jack. If a fuse is presented, the oscillating unit stops automatically and outputs a quiescent state. If the fuse is not presented or blown, the oscillating unit generates a pre-determined frequency pulse according to the oscillating unit. During the current measurement mode, the protecting unit and the shunt form a series parallel circuit when the test lead is plugged into the split contact jack. The impedance of the shunt is negligible in comparison to the impedance of the protecting unit, and the voltage drop across the shunt is proportional to the injected current.

Description:
TECHNICAL FIELD 
       [0001]    The present invention relates to electrically measuring instruments, and more particularly, to test lead detecting circuits. 
       BACKGROUND 
       [0002]    In various electrically measuring instruments, test leads are needed to couple to the measuring instrument so as to connect to a DUT (device under test) for measuring. Typical test lead includes two terminals, one terminal coupled to a DUT (device under test), and another terminal inserted into receptacles of the electrically measuring measurement so that physical quantities, for example voltage, current and power, measured by the DUT (device under test) are transmitted to the electrically measuring instrument through the test lead in order to measure for acquiring the data of the physical quantities. Generally speaking, an electrical measuring instrument has multiple receptacles used to measure different physical quantities. For example, one set of the receptacles is employed during a voltage measuring and another set of the receptacles is used during a current measuring. Because impedance of the measurement circuitry connected to the current measurement receptacle is very low, applying a large voltage to the current measurement receptacle may result in an extremely high currents flowing through the current measurement circuitry thereby causing the electrically measuring instrument being damaged or destroyed. 
       SUMMARY OF THE INVENTION 
       [0003]    The present invention disclosed a detecting circuit with a plugged test lead for detecting the contacting condition of a test lead plug which is present in a split jack with contact plates of an electrical measuring instrument or not. The detecting circuit comprises a split contact jack of an electrical measuring instrument, a shunt coupled to ground and the first terminal of the split contact jack, an oscillating unit coupled to the second terminal of the split contact jack through a protecting unit for generating a pulse or a quiescent state output, and a recognizing unit coupled to the oscillating unit for receiving an output signal transmitted from the oscillating unit, and determining a condition of the detecting circuit by utilizing the oscillating unit. 
         [0004]    The present invention disclosed also a detecting method of a detecting circuit with a plugged test lead. Firstly, setting an operation mode of the detecting circuit by a recognizing unit is provided. Next, a signal is transmitted to the recognizing unit by an oscillating unit whereas the test lead plugs into a split contact jack. The signal is received from the oscillating unit by the recognizing unit, determining a condition of the detecting circuit. Finally, a message is sent to a user in accordance with the determining result of the recognizing unit. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]      FIG. 1  is a schematic diagram illustrating structure of the plugged test lead detecting circuits in accordance with the present invention. 
           [0006]      FIG. 2  is a circuitry for use in  FIG. 1  in accordance with the present invention. 
           [0007]      FIG. 3  is a flow chart illustrating the plugged test lead detecting method in accordance with the present invention. 
           [0008]      FIG. 4  illustrates an example of the test lead detecting circuits and the method using the same in accordance with the present invention. 
           [0009]      FIG. 5  is an oscillogram with an expected frequency generated by the oscillating circuits according to  FIG. 4 . 
           [0010]      FIG. 6  is an oscillogram with a quiescent state voltage generated by the oscillating circuits according to  FIG. 4 . 
       
    
    
     DETAILED DESCRIPTION 
       [0011]    The following embodiments and drawings thereof are described and illustrated in the specification that are meant to be exemplary and illustrative, not limiting in scope. One skilled in the relevant art will identify that the invention may be practiced without one or more of the specific details, not limiting in scope. 
         [0012]    Referenced throughout the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment and included in at least one embodiment of the present invention. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment” in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. 
         [0013]      FIG. 1  depicts a block diagram illustrating a detecting circuit  100  with a plugged test lead in accordance with an embodiment of present invention. The detecting circuit  100  comprises a shunt  102  coupled to ground for bypassing and measuring the current of a DUT (device under test); a oscillating unit  110  used to generate a pulse or a quiescent state output; a recognizing unit  112  coupled to the oscillating unit  110  for receiving a output signal transmitted from the oscillating unit  110 , and determining a condition of the detecting circuit  100 ; a fuse  104  in serial with the shunt  102  to prevent over-current flowing into the shunt  102  through the fuse  104  ; a protecting unit  108  coupled to the oscillating unit  110  having high impedance to prevent error current from the oscillating unit  110  into the shunt  102 ; a split contact jack  106  with contact plates including two contact plates, the contact plate  114  and contact plate  116 . The contact plate  114  is coupled to ground through a series circuit of the fuse  104  and the shunt  102 . The contact plate  116  is coupled to the protecting unit  108 . 
         [0014]    Return to  FIG. 1 , in one embodiment of the present invention, when the test lead is plugged into the split contact jack  106 , the test lead bridges over the contact plate  116  and contact plate  114  to form an electrical path such that the protecting unit  108 , the fuse  104  and the shunt  102  form a series circuit to ground. Consequently, the oscillating unit  110  stops oscillating automatically and keeps a quiescent state output to the recognizing unit  112 . Conversely, when the test lead does not plug in the split contact jack  106 , the contact plate  114  and the contact plate  116  are open, and the oscillating unit  110  generates a pre-determined frequency pulse to the recognizing unit  112 . Then, the recognizing unit  112  receives the signal transmitted from the oscillating unit  110  to identify the state of the oscillation unit. 
         [0015]      FIG. 2  is a circuitry for use in  FIG. 1  in accordance with an embodiment of the present invention.  FIG. 2  depicts in detail the shunt  102 , the protecting unit  108 , the oscillating unit  110  and recognizing unit  112 . 
         [0016]    The shunt  102  expounded in  FIG. 2  includes a resistor with an extremely little resistance which is neglected in comparison with the impedance of the protecting unit  108 . The protecting unit  108  includes a resistor R 3  with a high resistance for protecting an unexpected high voltage applied to the split contact jack  106 . The oscillating unit  110  includes an oscillating circuit which is consisted of an operational amplifier (OPA), resistors R 1 , R 2 , R 5 , R 6  and a capacitor C. The output state of the oscillating circuit is changed alternatively by charging and discharging into and from the resistor R 6  and the capacitor C thereby reaching the function of output oscillating signal. The recognizing unit  112  includes a central processing unit (CPU)  118  used to determine the condition of the detecting circuit  100 ; an input/output port (I/O port)  120  to act as a communicating channel for the central processing unit  118 ; a Random Access Memory (RAM)  122  (referring as a counter) for counting the duty cycle of the output signal from the oscillating unit  110 , and storing the output state of the oscillating unit  110 . Subsequently, the counting information is transmitted from the counter  122  to the central processing unit  118  through the I/O port  120 . A timer  124  is to pre-set a set time, and then the counter  124  stops counting when the set time is reach, and a message is transmitted to notice the central processing unit  118  through the I/O port  120 . 
         [0017]    Referring to  FIG. 2 , firstly, when the test lead does not plug in the split contact jack  106 , the contact plate  114  and contact plate  116  are not coupled together. This means that a series circuits constituted by the contact plate  114  connected to the fuse  104 , the shunt  102  do not couple to another series circuits constituted by the contact plate  116  coupled to the resistor R 3  of the protecting unit  108  such that the detecting circuit is to be open. Therefore, no current created by the oscillating unit  110  flows into the series circuits constituted by the resistor R 3 , the split contact jack  106 , the fuse  104  and the shunt  102  to ground. 
         [0018]    Referring to  FIG. 2 , the terminal  4  of the operational amplifier in the oscillating circuit  110  is applied to a voltage V − , and the terminal  8  of the operational amplifier is applied to a voltage V + . The output terminal  1  of the operational amplifier is outputted voltage V o  which is determined by comparing the voltage V c  between the terminal  2  of the operational amplifier to ground with a reference voltage V ref . The reference voltage V ref  is the voltage as a function of R 1 , R 2  followed by the equation 
         [0000]    
       
         
           
             
               V 
               ref 
             
             = 
             
               
                 
                   R 
                    
                   
                       
                   
                    
                   1 
                 
                 
                   
                     R 
                      
                     
                         
                     
                      
                     1 
                   
                   + 
                   
                     R 
                      
                     
                         
                     
                      
                     2 
                   
                 
               
               × 
               
                 
                   V 
                   o 
                 
                 . 
               
             
           
         
       
     
         [0000]    When the test lead does not plug in the split contact jack  106 , the output voltage V o  is equal to the voltage V +  of the terminal  8  if the voltage V c  of the capacitor C is equal to zero, and then, the capacitor C is charged until the voltage V c  is greater than the reference voltage V ref  through the path from the output terminal of operational amplifier connected to the resistor R 6  and capacitor C to ground. Thus, the output voltage V o  of the operational amplifier converted into the voltage V −  so that the capacitor C is discharge and charged inversely according to the path from the output terminal of operational amplifier connected to the resistor R 6  and capacitor C to ground until the voltage V c  is less than the reference voltage V ref . Consequently, the voltage of the terminal  3  of the operational amplifier is greater than the voltage of the terminal  2  of the operational amplifier so that the output voltage V o  is equal to the voltage V +  to cause the capacitor C to be charged according the above mentioned path. In this way, the output voltage V o  is oscillating alternatively between the voltage V +  and V − . 
         [0019]    If the test lead is plugged into the split contact jack  106 , the test lead bridges the contact plate  116  and contact plate  114  to form an electrical path through the series circuit constituted by the protecting unit  108 , the fuse  104  and the shunt  102  coupled to ground. The output current of the operational amplifier flowing by the resistor R 6 , capacitor C will flow to the series circuit constituted by the resistor R 3 , the fuse  104  and the shunt  102  coupled to ground. Thus, the capacitor C stops being charged and discharged alternatively to hold the same potential as a node A, and then the oscillating circuit  110  stops oscillating, and outputs a quiescent state voltage to the recognizing unit  112 . 
         [0020]    The recognizing unit  112  receives the signal transmitted from the oscillating unit  110  so as to identify the state of the oscillating unit  110 . The recognizing unit  112  may utilize an A/D converter or a comparator or the similar device to identify the condition of the detecting circuit  100  through a filter transfer or a level shift. Also, the recognizing unit  112  may utilize frequency, duty cycle or pulse width measured by a measurement device to identify the condition of the detecting circuit  100  by a central processing unit or a microprocessor unit. 
         [0021]    Referring to  FIG. 3 , it illustrates the detecting method in accordance with an embodiment of present invention. Firstly, a user sets an operation mode of a detecting circuit  100  with a plugged test lead though a recognizing unit  112  in the step  110 . The operation mode of the detecting circuit  100  includes a test lead detecting mode, a fuse open detecting mode, and a current measurement mode. The user can select one operation mode according to the need for the user. 
         [0022]    The user sets the operation mode of the detecting circuit  100  through the recognizing unit  112 . Whether the test lead is plugged in the split contact jack  106  or not, the oscillating unit  110  can transmit the signal to the recognizing unit  112  in any operation mode in the step  120 . The oscillating circuit  110  stops oscillating and outputs a quiescent state voltage to the recognizing unit  112  when the user plugs the test lead into the split contact jack  106 . Conversely, when the test lead does not plug into the split contact jack  106 , the contact plate  114  does not couple to the contact plate  116  to form an open state, and the oscillating unit  110  generates a pre-determined frequency pulse to the recognizing unit  112 . 
         [0023]    The recognizing unit  112  receives the signal generated by the oscillating unit  110 , and determines the condition of the detecting circuit  100  according to the operation mode set by the user in the step  140 . The oscillating pulse or quiescent state voltage received by the recognizing unit  112  has different meanings at various operation modes. For instance, when the user sets the operation mode of the detecting circuit  100  through the recognizing unit  112  as the test lead detecting mode, the oscillating unit  110  transmits the quiescent state voltage to the recognizing unit  112 . If the user plugs the test lead into the split contact jack  106 , and the recognizing unit  112  receives the quiescent state voltage from the oscillating unit  110 , then the recognizing unit  112  determines the result that the user plugs the test lead into the split contact jack  106  in error and reminds the user that do not plug the test lead into the split contact jack  106  in the step  160 . 
         [0024]    For example, when the operation mode of the detection circuit  100  is the current measurement mode, the oscillating unit  110  transmits the oscillating signal to the recognizing unit  112  if the test lead does not plug in the split contact jack  106 . The recognizing unit  112  receives the oscillating signal from the oscillating unit  110  to determine that the fuse  104  is blown or the user does not plug the test lead into the split contact jack  106 , and the recognizing unit  112  sends a message to remind that the user plugs the test lead into the split contact jack  106  or checks whether the fuse  104  is blown or not in the step  160 . For another example, when the operation mode of the detecting circuit  100  is the fuse open detection mode, the oscillating unit  110  transmits the oscillating signal to the recognizing unit  112  if the test lead is plugged into the split contact jack  106 . The recognizing unit  112  receives the signal from the oscillating unit  110  to determine that the fuse  104  is open or blown, and the recognizing unit  112  sends a message to remind the user so as to replace the fuse in the step  160 . 
         [0025]    As seen in  FIG. 4 , it illustrates an example of the plugged test lead detecting circuit and the method using the same in accordance with an embodiment of the present invention. An application circuit  400  includes a resistor R 4  with an extremely little resistance connected to ground, the resistance of the resistor R 4  is negligible in comparison with the resistance of the resistor R 3 . A fuse F (maximum tolerant current  15  ampere) is connected to the resistor R 4  in series to prevent the over-current flowing into the resistor R 4  through the fuse F. A split contact jack A-INPUT has two contact plates, an upper contact plate and lower contact plate. The lower contact plate is coupled to ground through the series circuit formed by the fuse F and the resistor R 4 , and the upper contact plate is coupled to the resistor R 3 . The resistor R 3  has a high resistance for preventing an unexpected high voltage applying to the split jack A-INPUT. The application circuit  400  also comprises an oscillating circuit  402  coupled to a resistor R 3 . The oscillating circuit  402  includes an operational amplifier (TL062), resistors R 1 , R 2 , R 5 , R 6 , and a capacitor C. The output oscillating signal is generated by charging and discharging alternatively on the resistor R 6  and the capacitor C. The application circuit  400  also comprises a recognizing unit  404  coupled to the output terminal (the terminal  1  of the operational amplifier) of the oscillating circuit  402 . The recognizing unit  404  includes a central processing unit  406  used to determine the condition of the detecting circuit  400 ; a input/output port (I/O port)  408  to be a channel for the central processing unit  406  communicating with outside device; a counter  410  for counting the duty cycle of output signal generated from the oscillating circuit  402 , and storing the output state of the oscillating circuit  402 , and transmitting the information counted from the counter  410  to the central processing unit  406  through the I/O port  120 ; a timer  412  used to pre-set a set time. The timer  412  stops counting when the set time is reached, and then transmits a message to the central processing unit  406  through the I/O port  408 . 
       Table 1 shows the various parameters of the oscillation circuit  402  in FIG. 4: 
       [0026]      
         [0000]    
       
         
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
             
           
               
                   
                   
               
               
                   
                   
                   
                 C + 10% 
                   
                 C − 10% 
                   
               
               
                   
                   
                   
                 R6 + 5% 
                   
                 R6 − 5% 
               
               
                   
                   
                   
                 R1 + 1% 
                   
                 R1 − 1% 
               
               
                   
                 Standard 
                   
                 R2 − 1% 
                   
                 R2 + 1% 
               
               
                   
                 TYPICAL 
                   
                 MIN 
                   
                 MAX 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                 C 
                 1.00E−09 
                 F. 
                 1.10E−09 
                 F. 
                 9.00E−10 
                 F. 
               
               
                 R6 
                 3.60E+06 
                 Ω 
                 3.96E+06 
                 Ω 
                 3.24E+06 
                 Ω 
               
               
                 R1 
                 1.00E+04 
                 Ω 
                 1.10E+04 
                 Ω 
                 9.00E+03 
                 Ω 
               
               
                 R2 
                 4.99E+03 
                 Ω 
                 4.94E+03 
                 Ω 
                 5.04E+03 
                 Ω 
               
               
                 Frequency, f 
                 86.21071054 
                 Hz 
                 67.670177 
                 Hz 
                 112.8195 
                 Hz 
               
               
                 Maximum f 
                 67.670177 
                 Hz 
               
               
                 Minimum f 
                 112.81952 
                 Hz 
               
               
                   
               
             
          
         
       
     
         [0027]    The frequency in table 1 can be solved by a typical formula of oscillating frequency. 
         [0028]    Turning to  FIG. 4 , firstly, when the test lead does not plug in the split contact jack A-INPUT, the upper contact plate and lower contact plate are not to be coupled together such that the path between the series circuit formed by the fuse F and the resistor R 4 , and the series circuit formed by the upper contact plate coupled to the resistor R 3  is open. Therefore, current generated by the oscillation circuit  402  does not flow through the series circuit formed by the resistor R 3 , the split contact jack A-INPUT, the fuse F and the resistor R 4  coupled to ground. Thus, the oscillating circuit  402  generates a pre-determined frequency pulse to the recognizing unit  404 , for example, the waveform shown in  FIG. 5 . 
         [0029]    When the test lead is plugged into the split contact jack A-INPUT, the test lead bridges the upper contact plate and lower contact plate to form an electrical path through the series circuit formed by the resistor R 3 , the fuse F and the R 4  coupled to ground. The current flowing from the output terminal(terminal  1 ) of the operational amplifier via the resistor R 6  to capacitor C will flow to the series circuit formed by the resistor R 3 , the split contact jack A-INPUT, the fuse F and the resistor R 4  coupled to ground. Thus, the capacitor C stops being charged and discharged alternatively to hold the same potential as a node A. The oscillating circuit  402  stops oscillating, and outputs a quiescent state voltage to the recognizing unit  404 . The quiescent state voltage can be termed as a high level or a low level, shown as the waveform in  FIG. 6 . 
         [0030]    The recognizing unit  404  receives the signal (oscillating signal or the quiescent state output) from the oscillating circuit  402  to recognize the state of the oscillating circuit  402 . The central processing unit  406  determines oscillating status and the frequency, the pulse width or duty cycle of the oscillating circuit  402  according to the test lead plugged in the split contact jack A-INPUT or not. 
         [0031]    For example, the central processing unit  406  pulling the oscillating signal is shown as follows:
       1. Setting the time per 6.6 ms to pull the output signal from the oscillating circuit  402 .   2. Setting by the timer  412  for 264 ms.   3. Initializing the timer  412 , and setting initial state of the counter  410  to zero, and storing the output state of the oscillating circuit  402  to the counter  410 .   4. Pulling the output signal from the oscillating circuit  402  per 6.6 ms, thereby the counter  410  increases one transient output, and stores the output state.   5. The timer  412  is performed to reach the setting time to determine the condition of the counter  410 ;
           a. The counter&gt;1 means that the test lead does not plug into the split contact jack A-INPUT.   b. The counter≦1 means the test lead plugged into the split contact jack A-INPUT.   
           6. Backing to the steps 3-5 for cycling pulling.       
 
         [0040]    It will be appreciated to those skilled in the art that the preceding examples and preferred embodiments are exemplary and not limiting to the scope of the present invention. It is intended that all permutations, enhancements, equivalents, and improvements thereto that are apparent to those skilled in the art upon a reading of the specification and a study of the drawings are included within the true spirit and scope of the present invention.