Abstract:
Contact via holes are etched in a dielectric material layer overlying a semiconductor layer to expose the topmost surface of the semiconductor layer. The contact via holes are extended into the semiconductor material layer by continuing to etch the semiconductor layer so that a trench having semiconductor sidewalls is formed in the semiconductor material layer. A metal layer is deposited over the dielectric material layer and the sidewalls and bottom surface of the trench. Upon an anneal at an elevated temperature, a metal semiconductor alloy region is formed, which includes a top metal semiconductor alloy portion that includes a cavity therein and a bottom metal semiconductor alloy portion that underlies the cavity and including a horizontal portion. A metal contact via is formed within the cavity so that the top metal semiconductor alloy portion laterally surrounds a bottom portion of a bottom portion of the metal contact via.

Description:
BACKGROUND 
     The present disclosure relates to metal semiconductor alloy structures for providing low contact resistance and methods of forming the same. 
     Metal semiconductor alloys such as metal silicides, metal germanides, metal germano-silicides reduce contact resistance between a metal structure such as a metal contact via structure and a semiconductor region such as a source region, a drain region, and a gate conductor line. Formation of metal semiconductor alloys requires an interdiffusion between a metal and a semiconductor material. Typically, the metal is provided as a metal layer, which is deposited after deposition of a dielectric material layer overlying a semiconductor layer and formation of holes within the dielectric material layer to expose the semiconductor material on the top surface of the semiconductor layer. The interface between the metal layer and the underlying semiconductor material is subjected to an anneal at an elevated temperature, typically from 400 degrees Celsius to 700 degrees Celsius, to effect the interdiffusion of the metal and the semiconductor material. 
     The interdiffusion of the metal and the semiconductor material is self-limiting at a given anneal temperature. Thus, the volume of the metal semiconductor alloy formed by the anneal is limited by the area of the contact between the metal layer and the underlying semiconductor material. As the dimensions of semiconductor devices scale down, the total area available for forming a metal semiconductor alloy per contact is reduced in proportion to the square of the rate of scaling for a linear dimension because the area of contact is scaled in two dimensions. Thus, the contact resistance of a metal semiconductor alloy region between a metal contact via and an underlying semiconductor region becomes significant with the scaling of semiconductor devices. In other words, the reduction in the available area per contact limits the volume of a metal semiconductor alloy region that can be formed, and thereby raises the contact resistance of the metal semiconductor alloy region with the scaling down of device dimensions. However, a high contact resistance of a metal semiconductor alloy region adversely impacts device performance by introducing extra parasitic resistance. 
     BRIEF SUMMARY 
     Contact via holes are etched in a dielectric material layer overlying a semiconductor layer to expose the topmost surface of the semiconductor layer. The contact via holes are extended into the semiconductor material layer by continuing to etch the semiconductor layer so that a trench having semiconductor sidewalls is formed in the semiconductor material layer. A metal layer is deposited over the dielectric material layer and the sidewalls and bottom surface of the trench. Upon an anneal at an elevated temperature, a metal semiconductor alloy region is formed, which includes a top metal semiconductor alloy portion that includes a cavity therein and a bottom metal semiconductor alloy portion that underlies the cavity and including a horizontal portion. A metal contact via is formed within the cavity so that the top metal semiconductor alloy portion laterally surrounds a bottom portion of a bottom portion of the metal contact via. 
     According to an aspect of the present disclosure, a semiconductor structure includes: a trench located in a semiconductor material region in a semiconductor substrate; a metal semiconductor alloy region located within the trench; and a contact via structure including a lower contact via portion that is located within the metal semiconductor alloy region and laterally and vertically spaced from the semiconductor material region by the metal semiconductor alloy region. 
     According to another aspect of the present disclosure, a method of forming a semiconductor structure includes: forming at least one dielectric material layer over a semiconductor structure including a semiconductor material region; forming a trench that extends from a top surface of the at least one dielectric material layer into the semiconductor material portion; and forming a metal semiconductor alloy region by diffusing a metal into the semiconductor material region through a sidewall of the trench. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         FIG. 1  is a vertical cross-sectional view of an exemplary semiconductor structure after formation of gate stacks on a semiconductor substrate. 
         FIG. 2  is a vertical cross-sectional view of the exemplary semiconductor structure after formation of first source/drain extension regions. 
         FIG. 3  is a vertical cross-sectional view of the exemplary semiconductor structure after formation of a first dielectric layer. 
         FIG. 4  is a vertical cross-sectional view of the exemplary semiconductor structure after patterning the first dielectric layer. 
         FIG. 5  is a vertical cross-sectional view of the exemplary semiconductor structure after formation of first source/drain trenches. 
         FIG. 6  is a vertical cross-sectional view of the exemplary semiconductor structure after formation of embedded first-semiconductor-material source/drain regions. 
         FIG. 7  is a vertical cross-sectional view of the exemplary semiconductor structure after formation of a second dielectric layer. 
         FIG. 8  is a vertical cross-sectional view of the exemplary semiconductor structure after patterning the first dielectric layer and formation of second source/drain extension regions. 
         FIG. 9  is a vertical cross-sectional view of the exemplary semiconductor structure after formation of second source/drain trenches. 
         FIG. 10  is a vertical cross-sectional view of the exemplary semiconductor structure after formation of embedded second-semiconductor-material source/drain regions. 
         FIG. 11  is a vertical cross-sectional view of the exemplary semiconductor structure after removal of the second dielectric layer and formation of a first stress-generating dielectric liner and a second stress-generating dielectric liner. 
         FIG. 12  is a vertical cross-sectional view of the exemplary semiconductor structure after formation of a contact level dielectric material layer. 
         FIG. 13  is a vertical cross-sectional view of the exemplary semiconductor structure after formation of trenches that extend into various source/drain regions. 
         FIG. 14  is a vertical cross-sectional view of the exemplary semiconductor structure after formation of a metal layer. 
         FIG. 15  is a vertical cross-sectional view of the exemplary semiconductor structure after formation of various metal semiconductor alloy regions. 
         FIG. 16  is a vertical cross-sectional view of the exemplary semiconductor structure after application and patterning of a photoresist. 
         FIG. 17  is a vertical cross-sectional view of the exemplary semiconductor structure after removal of the exposed portions of the contact level dielectric material layer. 
         FIG. 18  is a vertical cross-sectional view of the exemplary semiconductor structure after formation of contact via structures. 
         FIG. 19  is a vertical cross-sectional view of the exemplary semiconductor structure after formation of various upper level metal interconnect structures. 
         FIG. 20  is a vertical cross-sectional view of a first variation of the exemplary semiconductor structure. 
         FIG. 21  is a vertical cross-sectional view of a second variation of the exemplary semiconductor structure. 
     
    
    
     DETAILED DESCRIPTION 
     As stated above, the present disclosure relates to metal semiconductor alloy structures for providing low contact resistance and methods of forming the same, which are now described in detail with accompanying figures. It is noted that like and corresponding elements are referred to by like reference numerals across the various drawings. 
     Referring to  FIG. 1 , an exemplary semiconductor structure according to a first embodiment of the present disclosure is shown, which includes a semiconductor substrate  8  containing a first semiconductor region  10  and a shallow trench isolation structure  20 . The semiconductor substrate  8  can be a bulk substrate including a bulk semiconductor material throughout, or a semiconductor-in-insulator (SOI) substrate (not shown) containing a top semiconductor layer, a buried insulator layer located under the top semiconductor layer, and a bottom semiconductor layer located under the buried insulator layer. The semiconductor material of the semiconductor substrate  8  may be selected from, but is not limited to, silicon, germanium, silicon-germanium alloy, silicon carbon alloy, silicon-germanium-carbon alloy, gallium arsenide, indium arsenide, indium phosphide, III-V compound semiconductor materials, II-VI compound semiconductor materials, organic semiconductor materials, and other compound semiconductor materials. 
     The first semiconductor region  10  includes a semiconductor material having a doping of a first conductivity type at a first dopant concentration. The semiconductor substrate  8  further contains a second semiconductor region  11  including the semiconductor material and having a doping of a second conductivity type, wherein the second conductivity type is the opposite of the first conductivity type. The first semiconductor region  10  may have a p-type doping and the second semiconductor region  11  may have an n-type doping, or vice versa. For example, the first semiconductor region  10  can have a p-type doping, and the second semiconductor region  11  can have an n-type doping. In one embodiment, the second semiconductor region  11  includes a well extending from a top surface  21  of the semiconductor substrate  8  to a well depth Dw into the semiconductor substrate  8 . Preferably, the first and second semiconductor regions ( 10 ,  11 ) are single crystalline, i.e., have the same crystallographic orientations throughout the volume of the semiconductor substrate  8 . In another embodiment, the first semiconductor region  10  and/or the second semiconductor region  11  can be undoped semiconductor regions depending on the type of devices to be built therein. For example, fully depleted semiconductor-on-insulator devices can employ an undoped semiconductor material for the first and/or second semiconductor regions ( 10 ,  11 ) that are bounded by a buried insulator layer at the bottom. 
     The semiconductor substrate  8  may be a bulk substrate, a semiconductor-on-insulator (SOI) substrate, or a hybrid substrate having a bulk portion and an SOI portion. While the present disclosure is described with a bulk substrate, embodiments employing an SOI substrate or a hybrid substrate are explicitly contemplated herein. 
     The first semiconductor region  10  and the second semiconductor region  11  can be lightly doped, i.e., have a dopant concentration from 1.0×10 15 /cm 3  to 3.0×10 18 /cm 3 , and preferably from 1.0×10 15 /cm 3  to 3.0×10 17 /cm 3 , although lesser and greater dopant concentrations are explicitly contemplated herein. Alternately, the first semiconductor region  10  and the second semiconductor region  11  can include intrinsic semiconductor materials. 
     The exemplary semiconductor structure includes a first device region  100  and a second device region  200 , each formed on and containing a portion of the semiconductor substrate  8 . The first device region  100  may include a metal-oxide-semiconductor field effect transistor (MOSFET) of one conductivity type, and the second device region  200  may include a MOSFET of the opposite conductivity type. For illustrative purposes, the first device region  100  includes a p-type field effect transistor (PFET), and the second device region  200  may include an n-type field effect transistor (NFET). 
     The first device region  100  includes a portion of the second semiconductor region  11  and a first gate electrode formed thereupon. Likewise, the second device region  200  includes a portion of the first semiconductor region  10  and a second gate electrode formed thereupon. Each of the first gate electrode and the second gate electrode includes a gate dielectric ( 30 A or  30 B) and a gate conductor ( 32 A or  32 B), and may be formed by methods well known in the art. The gate dielectrics ( 30 A,  30 B) may include a conventional semiconductor oxide based gate dielectric material or a high-k gate dielectric material known in the art. The gate conductor in the first device region  100  is herein referred to as a first gate conductor  32 A and the gate conductor in the second device region  200  is herein referred to as a second gate conductor  32 B. The gate conductors ( 32 A,  32 B) may include a doped semiconductor material such as doped polysilicon or a doped polycrystalline silicon alloy, or may include a metal gate material known in the art. Alternately, a replacement gate integration scheme may be employed, in which a dummy gate stack is formed first, followed by deposition of a gate-level dielectric material layer and planarization thereof, removal of the material of the dummy gate stack, and deposition of a permanent gate dielectric and a permanent gate electrode. 
     Dielectric gate caps may be formed on top of the first gate electrode and the second gate electrode. The dielectric gate cap in the first device region  100  is herein referred to as a first dielectric gate cap  52 A and the dielectric gate cap in the second device region  200  is herein referred to as a second dielectric gate cap  52 B. 
     A first gate spacer  54 A is formed on the sidewalls of the first gate conductor  32 A, or on the sidewalls of the semiconductor oxide layers ( 36 A,  36 B), if present, in the first device region  100 . A second gate spacer  54 B is formed on the sidewalls of the second gate conductor  32 B, or on the sidewalls of the semiconductor oxide layers ( 36 A,  36 B), if present, in the second device region  200 . Preferably, the first and second gate spacers ( 54 A,  54 B) include silicon nitride. The thickness of the first and second gate spacers ( 54 A,  54 B) may be adjusted to optimize the offset distance of source/drain extension regions to be subsequently formed from the sidewalls of the first gate electrode and the second gate electrode. The first and second gate spacers ( 54 A,  54 B) have a thickness from 3 nm to 30 nm, and typically from 5 nm to 20 nm, although lesser and greater thicknesses are contemplated herein also. 
     Referring to  FIG. 2 , a masked ion implantation is performed into the second semiconductor region  11  employing a first photoresist  61  to form first source/drain extension regions ( 72 A,  72 B). Each of the first source/drain extension regions ( 72 A,  72 B) is a semiconductor material region including a doped semiconductor material. Specifically, the first photoresist  61  is applied on the semiconductor substrate  8  and lithographically patterned with a first block mask such that the first device region  100  is exposed and the second device region  200  is covered by the first photoresist  61 . A first source extension region  72 A and a first drain extension region  72 B are formed in the first device region  100  by ion implantation of p-type dopants such as B, Ga, In, or a combination thereof. The dopant concentration of the first source/drain extension regions ( 72 A,  72 B) may be from 3.0×10 18 /cm 3  to 3.0×10 21 /cm 3 , and typically from 3.0×10 19 /cm 3  to 3.0×10 20 /cm 3 , although lesser and greater dopant concentrations are herein contemplated also. Halo regions (not shown) may be formed in the second semiconductor region  11  directly beneath the first source/drain extension regions ( 72 A,  72 B). After ion implantation, the first photoresist  61  is typically removed utilizing a conventional resist removal process. Alternate doping techniques such as plasma doping can be employed to form the first source/drain extension regions ( 72 A,  72 B) and/or the halo regions. Further, the formation of the first source/drain extension regions ( 72 A,  72 B) and/or the halo regions can be performed at other processing steps, such as after formation of source and drain regions illustrated in  FIG. 6 . 
     Referring to  FIG. 3 , a first dielectric layer  62  is formed on the first and second gate spacers ( 54 A,  54 B) and first and second gate nitride caps ( 52 A,  52 B). The first dielectric layer  62  includes a dielectric nitride or dielectric oxide. For example, the first dielectric layer  62  may include silicon nitride. The first dielectric layer  62  may be formed by plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD), high density plasma chemical vapor deposition (HDPCVD), or other known deposition techniques. The thickness of the first dielectric layer  62  may be from 20 nm to 100 nm, although lesser and greater thicknesses are also contemplated herein. 
     Referring to  FIG. 4 , a second photoresist  63  is applied to the first dielectric layer  62  and lithographically patterned to cover the second device region  200 , while exposing the first device region  100 . The portion of the first dielectric layer  62  in the first device region  100  is removed by an etch, which may be a dry etch or a wet etch. The exposed portion of the first semiconductor oxide layer  36 A, if present, is removed. The first source/drain extension regions ( 72 A,  72 B) are exposed. The second photoresist  63  may be removed at this step, or alternately, may be removed after the formation of first source/drain trenches to be subsequently formed at the next step. 
     Referring to  FIG. 5 , first source/drain trenches  18  are formed by removing portions of the second semiconductor region  11  within the first device region  100  by an anisotropic etch such as a reactive ion etch. The first source/drain trenches  18  include a first source side trench formed on one side of the first gate electrode and a first drain side trench formed on the other side of the first gate electrode. Preferably, the reactive ion etch is selective to the first dielectric layer  62 , the first gate nitride cap  52 A, the first gate spacer  54 A, and the shallow trench isolation structure  20 . Some edges of the first source/drain trenches  18  are substantially self-aligned to the outer sidewalls of the first gate spacer  54 A. Other edges of the first source/drain trenches  18  may be self-aligned to the edges of the shallow trench isolation structures  20 . Preferably, the depth of the first source/drain trenches  18  is less than the depth of the shallow trench isolation structure  20 . In case the semiconductor substrate  8  is an SOI substrate, the depth of the first source/drain trenches  18  is less than the thickness of a top semiconductor layer, i.e., a buried insulator layer is not exposed at the bottom of the first source/drain trenches. Presence of the second semiconductor region  11  at the bottom of the first source/drain trenches  18  enables epitaxial alignment of a first-semiconductor-material region (to be subsequently formed within the first source/drain trenches  18 ) to the lattice structure of the second semiconductor region  11 . The depth of the first source/drain trenches  18  may be from 10 nm to 150 nm, and typically from 20 nm to 100 nm, although lesser and greater depths are contemplated herein also. The second photoresist  63  is subsequently removed. Alternately, it is also possible to omit formation of the first source/drain trenches  18  and to form source and drain regions in the original semiconductor material of the second semiconductor region  11 . 
     Referring to  FIG. 6 , embedded first-semiconductor-material regions including a first semiconductor material can be formed by in-situ doped selective epitaxy within the first source/drain trenches  18 . The first semiconductor material is different from the semiconductor material of the second semiconductor region  11  in lattice spacing. For example, the embedded first-semiconductor-material regions can be embedded SiGe regions. The embedded first-semiconductor-material regions include single crystalline first semiconductor material portions, and include an embedded first-semiconductor-material source region  76 A and an embedded first-semiconductor-material drain region  76 B, which are herein collectively termed “embedded first-semiconductor-material source/drain regions” ( 76 A,  76 B). The embedded first-semiconductor-material source/drain regions ( 76 A,  76 B) are semiconductor material regions that include a p-type dopant, e.g., B, Ga, In, or a combination thereof, at a concentration from 3.0×10 19 /cm 3  to 3.0×10 21 /cm 3 , and typically from 1.0×10 20 /cm 3  to 1.0×10 21 /cm 3 , although lesser and greater concentrations are also contemplated herein. 
     In one embodiment, the embedded first-semiconductor-material source/drain regions ( 76 A,  76 B) include a silicon germanium alloy having a p-type doping. Preferably, the embedded first-semiconductor-material source/drain regions ( 76 A,  76 B) include germanium from 15% to 35% in atomic concentration, although lesser and greater concentration are explicitly contemplated herein also. 
     The embedded first-semiconductor-material source/drain regions ( 76 A,  76 B) are epitaxially aligned to the second semiconductor region  11 . Due to the forced epitaxial alignment of the embedded first-semiconductor-material source/drain regions ( 76 A,  76 B) to the second semiconductor region  11 , the embedded first-semiconductor-material source/drain regions ( 76 A,  76 B) apply a compressive uniaxial stress to a first channel C 1  directly underneath the first gate dielectric  30 A in the first device region  100 . 
     Alternately, if formation of the first source/drain trenches is omitted at the processing step of  FIG. 5 , a raised source region and/or a raised drain region can be grown over exposed source and drain regions, e.g., on exposed surfaces of the first source/drain extension regions ( 72 A,  72 B), by selective epitaxial growth of a doped semiconductor material. Yet alternately, source and drain regions may be formed by introduction of electrical dopants by ion implantation and/or plasma doping without forming first source drain/trenches and without forming raised source/drain regions. 
     Referring to  FIG. 7 , an etch-stop dielectric layer  64  and a second dielectric layer  66  are formed on the embedded first-semiconductor-material source/drain regions ( 76 A,  76 B) and the first and second gate spacers ( 54 A,  54 B). The second dielectric layer  66  includes a dielectric oxide or a dielectric nitride. For example, the second dielectric layer  66  may include silicon nitride. The etch-stop dielectric layer  64  includes a dielectric material that is different from the material of the second dielectric layer  66 . If the second dielectric layer  66  includes silicon nitride, the etch-stop dielectric layer  64  may include silicon oxide. The thickness of the second dielectric layer  66  may be from 20 nm to 100 nm, although lesser and greater thicknesses are also contemplated herein. The thickness of the etch-stop dielectric layer  64  may be from 5 nm to 30 nm, although lesser and greater thicknesses are also contemplated herein. 
     Referring to  FIG. 8 , a third photoresist  67  is applied over the second dielectric layer  66  and lithographically patterned to expose the second device region  200 , while blocking the first device region  100 . The exposed portions of the second dielectric layer  66  in the second device region  200  is removed by a first etch, which may be a wet etch or a dry etch employing the third photoresist  67  as an etch mask. Preferably, the first etch is selective to the etch-stop dielectric layer  64 . Exposed portions of the etch-stop dielectric layer  64  in the second device region  200  are removed by a second etch employing the third photoresist  67  as an etch mask. Preferably, the second etch is selective to the second gate spacer  54 B, the second gate cap nitride  52 B, and the first semiconductor region  10 . 
     A masked ion implantation may be performed into the first semiconductor region  10  employing the third photoresist  67  as a blocking mask to form second source/drain extension regions ( 73 A,  73 B). A second source extension region  73 A and a second drain extension region  73 B are formed in the second device region  200  by ion implantation of n-type dopants such as P, As, Sb, or a combination thereof. The dopant concentration of the second source/drain extension regions ( 73 A,  73 B) may be from 3.0×10 18 /cm 3  to 3.0×10 21 /cm 3 , and typically from 3.0×10 19 /cm 3  to 3.0×10 20 /cm 3 , although lesser and greater dopant concentrations are herein contemplated also. Halo regions (not shown) may be formed in the first semiconductor region directly  10  beneath the second source/drain extension regions ( 73 A,  73 B). The third photoresist  67  may be removed at this point, or alternately, may be removed after the formation of second source/drain trenches to be subsequently formed at the next step. Alternate doping techniques such as plasma doping can be employed to form the second source/drain extension regions ( 73 A,  73 B) and/or the halo regions. Further, the formation of the first source/drain extension regions ( 73 A,  73 B) and/or the halo regions can be performed at other processing steps, such as after formation of source and drain regions illustrated in  FIG. 10 . 
     Referring to  FIG. 9 , second source/drain trenches  19  are formed by removing portions of the first semiconductor region  10  within the second device region  200  by an anisotropic etch such as a reactive ion etch. The second source/drain trenches  19  include a second source side trench formed on one side of the second gate electrode and a second drain side trench formed on the other side of the second gate electrode. Preferably, the reactive ion etch is selective to the second dielectric layer  66 , the second gate nitride cap  52 B, the second gate spacer  54 B, and the shallow trench isolation structure  20 . Some edges of the second source/drain trenches  19  are substantially self-aligned to the outer sidewalls of the second gate spacer  54 B. Other edges of the second source/drain trenches  19  may be self-aligned to the edges of the shallow trench isolation structures  20 . Preferably, the depth of the second source/drain trenches  19  is less than the depth of the shallow trench isolation structure  20 . In case the semiconductor substrate  8  is an SOI substrate, the depth of the second source/drain trenches  19  is less than the thickness of a top semiconductor layer, i.e., a buried insulator layer is not exposed at the bottom of the second source/drain trenches. Presence of the first semiconductor region  10  at the bottom of the second source/drain trenches  19  enables epitaxial alignment of a second-semiconductor-material alloy to be subsequently formed within the second source/drain trenches  19  to the lattice structure of the first semiconductor region  10 . The depth of the second source/drain trenches  19  may be from 10 nm to 150 nm, and typically from 20 nm to 100 nm, although lesser and greater depths are contemplated herein also. Alternately, it is also possible to omit formation of the second source/drain trenches  19  and to form source and drain regions in the original semiconductor material of the first semiconductor region  10 . 
     Referring to  FIG. 10 , embedded second-semiconductor-material regions including a second semiconductor material can be formed by in-situ doped selective epitaxy within the second source/drain trenches  19 . The second semiconductor material is different from the semiconductor material of the first semiconductor region  10  and the first semiconductor material in lattice spacing. For example, the embedded second-semiconductor-material regions can be embedded silicon-carbon alloy regions. The embedded second-semiconductor-material regions include single crystalline second-semiconductor-material alloy portions, and include an embedded second-semiconductor-material source region  77 A and an embedded second-semiconductor-material drain region  77 B, which are herein collectively termed “embedded second-semiconductor-material source/drain regions” ( 77 A,  77 B). The embedded second-semiconductor-material source/drain regions ( 77 A,  77 B) are semiconductor regions that include an n-type dopant, e.g., P, As, Sb, or a combination thereof, at a concentration from 3.0×10 19 /cm 3  to 3.0×10 21 /cm 3 , and typically from 1.0×10 20 /cm 3  to 1.0×10 21 /cm 3 , although lesser and greater concentrations are also contemplated herein. 
     In one embodiment, the embedded second-semiconductor-material source/drain regions ( 77 A,  77 B) can include a silicon carbon alloy having an n-type doping. Preferably, the embedded second-semiconductor-material source/drain regions ( 77 A,  77 B) include carbon from 0.5% to 4.0% in atomic concentration, although lesser and greater concentration are explicitly contemplated herein also. 
     The embedded second-semiconductor-material source/drain regions ( 77 A,  77 B) are epitaxially aligned to the first semiconductor region  10 . Due to the forced epitaxial alignment of the embedded second-semiconductor-material source/drain regions ( 77 A,  77 B) to the first semiconductor region  10 , the embedded second-semiconductor-material source/drain regions ( 77 A,  77 B) apply a tensile uniaxial stress to a second channel C 2  directly underneath the second gate dielectric  30 B in the second device region  200 . 
     Alternately, if formation of the second source/drain trenches is omitted at the processing step of  FIG. 9 , a raised source region and/or a raised drain region can be grown over exposed source and drain regions, e.g., on exposed surfaces of the second source/drain extension regions ( 73 A,  73 B), by selective epitaxial growth of a doped semiconductor material. Yet alternately, source and drain regions may be formed by introduction of electrical dopants by ion implantation and/or plasma doping without forming first source drain/trenches and without forming raised source/drain regions. 
     Referring to  FIG. 11 , the etch-stop dielectric layer  64  and the second dielectric layer  66  can be removed selective to semiconductor materials and the materials of the first and second dielectric gate caps ( 52 A,  52 B) and the first and second gate spacers ( 54 A,  54 B). A first stress-generating dielectric liner  68  and a second stress-generating dielectric liner  69  can be formed in the first device region  100  and the second device region, respectively. The first stress-generating dielectric liner  68  overlies a first gate structure ( 30 A,  32 A,  36 A,  52 A,  54 A) and the embedded first-semiconductor-material source/drain regions ( 76 A,  76 B). The second stress-generating dielectric liner  69  overlies a second gate structure ( 30 B,  32 B,  36 B,  52 B,  54 B) and the embedded second-semiconductor-material source/drain regions ( 77 A,  77 B). The first stress-generating dielectric liner  68  and the second stress-generating dielectric liner  69  are typically dielectric silicon nitride layers that are formed by plasma enhanced chemical vapor deposition. If the first device region  100  includes a p-type field effect transistor and the second device region  200  includes an n-type field effect transistor, the first stress-generating dielectric liner  68  can be a dielectric liner that applies a compressive stress to underlying structures and a second stress-generating dielectric liner  69  can be a dielectric liner that applies a tensile stress to underlying structures. The first stress-generating dielectric liner  68  and the second stress-generating dielectric liner  69  are optional, i.e., may, or may not, be present. 
     Referring to  FIG. 12 , a contact level dielectric material layer  82  is deposited over the first stress-generating dielectric liner  68  and the second stress-generating dielectric liner  69 , if present, and/or over the first gate structure ( 30 A,  32 A,  36 A,  52 A,  54 A), the embedded first-semiconductor-material source/drain regions ( 76 A,  76 B), the second gate structure ( 30 B,  32 B,  36 B,  52 B,  54 B), and the embedded second-semiconductor-material source/drain regions ( 77 A,  77 B). The contact level dielectric layer  82  may include a mobile ion barrier layer (not shown). The contact level dielectric layer  82  may include, for example, a CVD oxide such as undoped silicate glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), or a combination thereof. The contact dielectric material layer  82  is planarized, for example, by chemical mechanical planarization, a recess etch, or a combination thereof. For example, the topmost surface of the contact level dielectric layer  82  as planarized can have a planar top surface that lies within the same horizontal plane as the top surfaces of the first stress-generating dielectric liner  68  and the second stress-generating dielectric liner  69 , if present, or within the same horizontal plane as the top surfaces of the first and second dielectric gate caps ( 52 A,  52 B). 
     Referring to  FIG. 13 , a first photoresist  81  is applied to the top surface of the contact level dielectric layer  82  and is lithographically patterned to form openings therein. The openings in the first photoresist  81  overlie areas in which formation of metal semiconductor alloys are desired. For example, the openings in the first photoresist  81  may be within areas of the embedded first-semiconductor-material source/drain regions ( 76 A,  76 B) and the embedded second-semiconductor-material source/drain regions ( 77 A,  77 B). Optionally, additional openings (not shown) in the first photoresist  81  may be formed in portions of areas of the first and second gate conductors ( 32 A,  32 B). 
     Trenches  83  are formed through the contact level dielectric layer  82  and the first and second stress-generating dielectric liners ( 68 ,  69 ) and upper portions of the embedded first-semiconductor-material source/drain regions ( 76 A,  76 B) and the embedded second-semiconductor-material source/drain regions ( 77 A,  77 B). Each trench  83  can be formed by first anisotropically etching through the contact level dielectric layer  82  and one of the first and second stress-generating dielectric liners ( 68 ,  69 ) to expose top surfaces of the embedded first-semiconductor-material source/drain regions ( 76 A,  76 B) and the embedded second-semiconductor-material source/drain regions ( 77 A,  77 B). Employing the first photoresist  81  as an etch mask, the anisotropic etch continues employing a different etch chemistry or the same chemistry into the upper portions of the embedded first-semiconductor-material source/drain regions ( 76 A,  76 B) and the embedded second-semiconductor-material source/drain regions ( 77 A,  77 B). Thus, each trench  83  extends from a top surface of the contact level dielectric material layer  82  into a semiconductor material portion. Alternately, an anisotropic etch may be employed first to expose a semiconductor surface, and then a semiconductor specific wet etch chemistry such as a KOH etch may be employed. 
     The sidewalls of each trench  83  contiguously extend from the topmost surface of the contact level dielectric material layer  83  into the semiconductor material region, which can be one of the embedded first-semiconductor-material source/drain regions ( 76 A,  76 B) and the embedded second-semiconductor-material source/drain regions ( 77 A,  77 B). The depth of the anisotropic etch can be controlled so that the trenches  83  extend below a planar top surface of the semiconductor substrate  8  such as the interface between the first semiconductor region  10  and the second gate dielectric  30 B or the interface between the second semiconductor region  11  and the first gate dielectric  30 A. Thus, the bottom surface of each trench  83  can be located between a horizontal plane that includes the bottom surface of the first and second gate dielectrics ( 30 A,  30 B) and another horizontal plane that coincides with a bottommost surface of the embedded first-semiconductor-material source/drain regions ( 76 A,  76 B) and the embedded second-semiconductor-material source/drain regions ( 77 A,  77 B). 
     Referring to  FIG. 14 , a metal layer  78  is deposited on all exposed surfaces in the trenches  83  and the top surface of the contact level dielectric layer. The metal layer  78  includes a metal that can form a metal semiconductor alloy by interacting with the semiconductor materials of the embedded first-semiconductor-material source/drain regions ( 76 A,  76 B) and the embedded second-semiconductor-material source/drain regions ( 77 A,  77 B). Materials that can be employed for the metal layer  78  include, but are not limited to, Ti, Ta, V, W, Mo, Ni, Pt, and alloys thereof. The thickness of the metal layer  78  is typically less than one half of the width of the bottom portion of the trenches  83  prior to deposition of the metal layer  83 . Typically, the thickness of the metal layer  78  is from 10 nm to 30 nm, although lesser and greater thicknesses can also be employed. 
     Referring to  FIG. 15 , various metal semiconductor alloy regions are formed by inducing an interdiffusion and reaction between the metal in the metal layer  78  and the semiconductor materials that contact the metal layer  78 . The semiconductor materials are located within surface portions of semiconductor material regions, i.e., on the sidewalls and bottom surface of the trench  83  that form interfaces between the metal layer  78  and the semiconductor material regions. The semiconductor material regions include the embedded first-semiconductor-material source/drain regions ( 76 A,  76 B) and the embedded second-semiconductor-material source/drain regions ( 77 A,  77 B). The various metal semiconductor alloy regions include a first metal semiconductor alloy region  84 A formed on the embedded first-semiconductor-material source region  76 A, a second metal semiconductor alloy region  84 B formed on the embedded first-semiconductor-material drain region  76 B, a third metal semiconductor alloy region  84 C formed on the embedded second-semiconductor-material source region  77 A, a fourth metal semiconductor alloy region  84 D formed on the embedded second-semiconductor-material drain region  77 B. The various metal semiconductor alloy regions ( 84 A,  84 B,  84 C,  84 D) are formed by diffusion the metal into the various semiconductor material regions ( 76 A,  76 B,  77 A,  77 B) through sidewalls and bottom surfaces of the trenches  83 . The unreacted portions of the metal layer  78  are removed selective to the various metal semiconductor alloy regions ( 84 A,  84 B,  84 C,  84 D). 
     The entirety of each metal semiconductor alloy region ( 84 A,  84 B,  84 C, or  84 D) is of integral construction, i.e., contiguously connected throughout. Each metal semiconductor alloy region ( 84 A,  84 B,  84 C, or  84 D) includes an upper metal semiconductor alloy portion and a lower metal semiconductor alloy portion. The bottommost surface of each metal semiconductor alloy region ( 84 A,  84 B,  84 C, or  84 D) can be at a first depth d 1  from the topmost portions of the embedded first-semiconductor-material source/drain regions ( 76 A,  76 B) and the embedded second-semiconductor-material source/drain regions ( 77 A,  77 B). 
     Within each upper metal semiconductor alloy portion, an inner sidewall and an outer sidewall of the upper metal semiconductor alloy portion are laterally spaced by a substantially constant width throughout. Each lower metal semiconductor alloy portion does not include a pair of an inner sidewall and an outer sidewall having a constant spacing therebetween. If a metal semiconductor alloy region ( 84 A,  84 B,  84 C,  84 D) includes a horizontal bottom portion having a substantially constant thickness, the top surface of the horizontal portion can be at a second depth d 2  from the topmost portion of the embedded first-semiconductor-material source/drain regions ( 76 A,  76 B) and the embedded second-semiconductor-material source/drain regions ( 77 A,  77 B). In this case, the boundary between the upper metal semiconductor alloy portion and the lower metal semiconductor alloy portion in any of the metal semiconductor alloy region ( 84 A,  84 B,  84 C, or  84 D) can be at the depth of the upper surface of the horizontal portion. 
     The boundary between the upper metal semiconductor alloy portion and the lower metal semiconductor alloy portion within the third metal semiconductor alloy region  84 C is represented by a horizontal dotted line. The lower metal semiconductor alloy portions of the metal semiconductor alloy regions ( 84 A,  84 B,  84 C, or  84 D) can be formed between a horizontal plane that includes the bottom surface of the gate dielectrics ( 30 A,  30 B) and a bottommost surface of the embedded first-semiconductor-material source/drain regions ( 76 A,  76 B) or the embedded second-semiconductor-material source/drain regions ( 77 A,  77 B). Inner sidewalls of a metal semiconductor alloy regions ( 84 A,  84 B,  84 C,  84 D) are laterally spaced at least by a spacing s throughout the entirety of the upper metal semiconductor alloy portion therein. 
     Referring to  FIG. 16 , a first optional processing step may be employed if formation of a local interconnect structure within the contact level dielectric layer  82  is desired. In this case, a second photoresist  85  can be optionally applied and lithographically patterned to form openings in an area overlapping with at least two trenches  83 . 
     Referring to  FIG. 17 , a second optional processing step may be employed if formation of a local interconnect structure within the contact level dielectric layer  82  is desired. In an etch process that employs the second photoresist  85  as an etch mask, the exposed portions of the contact level dielectric material layer  82  and any portion of the first and second stress-generating dielectric liners ( 68 ,  69 ), if present, are removed selective to the underlying semiconductor materials, underlying metal semiconductor alloy portions (i.e., portions of the first and second metal semiconductor alloy regions ( 84 A,  84 B), and underlying portions of the shallow trench isolation structure  20 . The second photoresist  85  is subsequently removed, for example, by ashing. 
     Referring to  FIG. 18 , various contact via structures are formed by deposition of a conductive material into the trenches  83  and by filling the trenches  83  with the conductive material. The conductive material is typically a metal, which can be the same as, or different from the metal in the metal layer  78 . (See  FIG. 14 .) Excess conductive material above the top surface of the contact level dielectric layer  82  is removed by planarization, which can be effected by, for example, chemical mechanical planarization, a recess etch, or a combination thereof. Remaining portions of the deposited conductive material form various contact via structures after the planarization. A topmost surface of each of the various contact via structures is coplanar with the topmost surface of the contact level dielectric layer  82 . 
     The various contact via structures can include, for example, a first-type contact via structures that contact only one of the metal semiconductor alloy regions ( 84 C,  84 D). The first-type contact via structures include a first first-type contact via structure  86 A that contacts the third metal semiconductor alloy region  84 C and a second first-type contact via structure  86 B that contacts the fourth metal semiconductor alloy region  84 D. Each of the first-type contact via structures ( 86 A,  86 B) includes a lower contact via portion that is laterally surrounded by a metal semiconductor alloy region ( 84 C,  84 D) and an upper contact via portion that overlies a metal semiconductor alloy region ( 84 C,  84 D). 
     The various contact via structures can further include, for example, a second-type contact via structure  88  that contacts a plurality of metal semiconductor alloy regions ( 84 A,  84 B). The second-type contact via structure  88  includes a plurality of lower contact via portions and an upper contact via portion. Each of the lower contact via portions is laterally surrounded by a metal semiconductor alloy region ( 84 A or  84 B) and an upper contact via portion that overlies a plurality of metal semiconductor alloy region ( 84 A and  84 B). The shallow trench isolation structure  20  may the bottom surface of the second-type contact via structure  88 . 
     For each metal semiconductor alloy region that underlies a first-type contact via structure ( 86 A,  86 B) or a second-type contact via structure  88 , an upper metal semiconductor alloy portion of the metal semiconductor alloy region laterally surrounds a lower contact via portion of a contact via structure ( 86 A,  86 B,  88 ), and a lower metal semiconductor alloy portion of the metal semiconductor alloy region underlies the lower contact via portion of the contact via structure ( 86 A,  86 B,  88 ). 
     Because the trenches  83  are formed below a planar top surface of the semiconductor substrate  8  (See  FIG. 13 ), each lower contact via portion of a contact via structure ( 86 A,  86 B,  88 ) extends below the planar top surface of the semiconductor substrate  8 , which can be the coplanar with the bottom surfaces of the first and second gate dielectrics ( 30 A,  30 B). A lower metal semiconductor alloy portion of each metal semiconductor alloy region ( 84 A,  84 B,  84 C,  84 D) is located between the horizontal plane (that can includes the bottom surfaces of the first and second gate dielectrics ( 30 A,  30 B)), and a bottommost surface of the embedded first-semiconductor-material source/drain regions ( 76 A,  76 B) and the embedded second-semiconductor-material source/drain regions ( 77 A,  77 B), which are source regions and drain regions of field effect transistors. 
     At the bottommost portion of each upper portion of a contact via structure ( 86 A,  86 B,  88 ), a sidewall of the upper portion of the contact via structure ( 86 A,  86 B,  88 ) contacts the topmost portion of a metal semiconductor alloy region. The location at which the sidewall of the upper portion of the contact via structure ( 86 A,  86 B,  88 ) contacts the topmost portion of a metal semiconductor alloy region is laterally confined between an uppermost portion of an inner sidewall of the metal semiconductor alloy region ( 84 A,  84 B,  84 C,  84 D) and an uppermost portion of an outer sidewall of the metal semiconductor alloy region ( 84 A,  84 B,  84 C,  84 D) because the inner sidewall and the outer sidewall are laterally spaced by a constant distance. At the bottommost portion of each upper portion of a contact via structure ( 86 A,  86 B,  88 ), an entirety of a periphery of the upper contact via portion contacts an upper surface of the underlying metal semiconductor alloy region ( 84 A,  84 B,  84 C,  84 D). 
     Because the metal diffused into semiconductor material regions during formation of the various metal semiconductor alloy regions ( 84 A,  84 B,  84 C,  84 D), the outer sidewalls of the various metal semiconductor alloy regions ( 84 A,  84 B,  84 C,  84 D) expand outward compared with the original size of the trenches  83  as formed by etching. Thus, surfaces of the various metal semiconductor alloy regions ( 84 A,  84 B,  84 C,  84 D) contact the first or second stress-generating dielectric liners ( 68 ,  69 ), if present, or the contact level dielectric material layer  82  if first or second stress-generating dielectric liners are not present. The entirety of each upper contact via portion of the various contact via structures is embedded in the first and second stress-generating dielectric liners ( 68 ,  69 ) and the contact level dielectric material layer  82 . 
     Referring to  FIG. 19 , various upper level metal interconnect structures can be subsequently formed. The upper level metal interconnect structures can include at least one interconnect level dielectric material layer  89 , at least one conductive via structures ( 90 A,  90 B,  90 C,  90 D,  90 E), and at least one conductive line structures  92 . 
     Referring to  FIG. 20 , a first variation of the exemplary semiconductor structure can be derived from the exemplary structure by omitting formation of the first source/drain trenches  18  and the accompanying embedded first-semiconductor-material source/drain regions ( 76 A,  76 B) and/or by omitting formation of the second source/drain trenches  19  and the accompanying embedded second-semiconductor-material source/drain regions ( 77 A,  77 B). Instead, first implanted source/drain regions ( 76 A′,  76 B′) and/or second implanted source/drain regions ( 77 A′,  77 B′) are formed by employing masked ion implantation steps. Correspondingly, the top surfaces of the implanted source/drain regions ( 76 A′,  76 B′) and/or second implanted source/drain regions ( 77 A′,  77 B′) can be coplanar with the bottom surfaces of the first and second gate dielectrics ( 30 A,  30 B). 
     The bottommost surface of each metal semiconductor alloy region ( 84 A,  84 B,  84 C, or  84 D) can be at a first depth d 1  from the topmost portions of the embedded first-semiconductor-material source/drain regions ( 76 A,  76 B) and the embedded second-semiconductor-material source/drain regions ( 77 A,  77 B). Within each upper metal semiconductor alloy portion, an inner sidewall and an outer sidewall of the upper metal semiconductor alloy portion are laterally spaced by a substantially constant width throughout. Each lower metal semiconductor alloy portion does not include a pair of an inner sidewall and an outer sidewall having a constant spacing therebetween. 
     If a metal semiconductor alloy region ( 84 A,  84 B,  84 C,  84 D) includes a horizontal bottom portion having a substantially constant thickness, the top surface of the horizontal portion can be at a second depth d 2  from the topmost portion of the embedded first-semiconductor-material source/drain regions ( 76 A,  76 B) and the embedded second-semiconductor-material source/drain regions ( 77 A,  77 B). In this case, the boundary between the upper metal semiconductor alloy portion and the lower metal semiconductor alloy portion in any of the metal semiconductor alloy region ( 84 A,  84 B,  84 C, or  84 D) can be at the depth of the upper surface of the horizontal portion. The boundary between the upper metal semiconductor alloy portion and the lower metal semiconductor alloy portion within the third metal semiconductor alloy region  84 C is represented by a horizontal dotted line. The lower metal semiconductor alloy portions of the metal semiconductor alloy regions ( 84 A,  84 B,  84 C, or  84 D) can be formed between a horizontal plane that includes the bottom surface of the gate dielectrics ( 30 A,  30 B) and a bottommost surface of the embedded first-semiconductor-material source/drain regions ( 76 A,  76 B) or the embedded second-semiconductor-material source/drain regions ( 77 A,  77 B). Inner sidewalls of a metal semiconductor alloy regions ( 84 A,  84 B,  84 C,  84 D) are laterally spaced at least by a spacing s throughout the entirety of the upper metal semiconductor alloy portion therein. 
     Referring to  FIG. 21 , a second variation of the exemplary semiconductor structure can be derived from the first exemplary semiconductor structure or the first variation of the first exemplary semiconductor structure by employing an etch process that rounds the bottom surfaces of the trenches  83  at a processing step corresponding to  FIG. 13 . The bottommost surface of each metal semiconductor alloy region ( 84 A,  84 B,  84 C, or  84 D) can be at a first depth d 1  from the topmost portions of the embedded first-semiconductor-material source/drain regions ( 76 A,  76 B) and the embedded second-semiconductor-material source/drain regions ( 77 A,  77 B). The boundary between the upper metal semiconductor alloy portion and the lower metal semiconductor alloy portion in any of the metal semiconductor alloy region ( 84 A,  84 B,  84 C, or  84 D) can be at a depth at which an inner sidewall and an outer sidewall of the metal semiconductor alloy region ( 84 A,  84 B,  84 C, or  84 D) becomes no longer parallel to each other. The boundary between the upper metal semiconductor alloy portion and the lower metal semiconductor alloy portion within the third metal semiconductor alloy region  84 C is represented by a horizontal dotted line. Thus, the inner sidewalls of a metal semiconductor alloy regions ( 84 A,  84 B,  84 C,  84 D) are laterally spaced at least by a spacing s throughout the entirety of the upper metal semiconductor alloy portion therein. 
     The structure of the present disclosure can be implemented on any type of field effect transistors including conventional planar field effect transistors and finFETs, as well as bipolar transistors that require contacts to the emitter, base, and collector, and other semiconductor devices such as varactors, silicon controlled rectifiers, diodes, capacitors, resistors, and inductors that include at least one metal semiconductor alloy region. 
     While the disclosure has been described in terms of specific embodiments, it is evident in view of the foregoing description that numerous alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, the disclosure is intended to encompass all such alternatives, modifications and variations which fall within the scope and spirit of the disclosure and the following claims.