Abstract:
A duty cycle converter generating a pair of output signals whose cross-point duty cycle is substantially equal to the edge duty cycle of a pair of input signals. The duty cycle converter includes an edge detector and a signal generator. The edge detector detects and indicates a first transition of a first input signal and a second transition of a second input signal. The signal generator takes the outputs of the edge detector and generates a first output signal and a second output signal. The signal generator causes the cross-point duty cycle of the first output signal to substantially equal the edge duty cycle of the first input cycle. The signal generator does so by forcing a first time delay between adjacent crossover points of the first and second output signals to be substantially equal to a second time delay between the first transition and the second transition.

Description:
[0001]    This application is a continuation of and claims priority on U.S. patent application Ser. No. 09/513,721, filed Feb. 24, 2000, which is hereby incorporated by reference in its entirety. 
     
    
     
       BRIEF DESCRIPTION OF THE INVENTION  
         [0002]    The present invention relates generally to integrated circuits and more particularly to an apparatus for duty cycle conversion.  
         BACKGROUND OF THE INVENTION  
         [0003]    Some integrated circuits decrease their associated delay times by doubling their data rates. Typically, to support data rate doubling a single phase clock input is split into true and complement clocks by a clock generator. These two internal clocks allow data sampling to occur on both the rising and falling edges of the single phase clock input. FIG. 1 illustrates a prior art Double Data Rate input Receiver (DRR)  26 , which receives true and complement clocks from Clock Generator  20 . From the single phase clock, the CLK signal, Clock Generator  20  generates the internal true and complement clock signals, which are labeled CLKL and CLKB, respectively. To promote satisfactory receive timing margins, the CLKL and CLKB signals should be 180° apart in phase. A Duty Cycle Correction Circuit may be used to force the CLKL and CLKB signals into this relationship.  
           [0004]    [0004]FIG. 2 illustrates a prior art Duty Cycle Correction Circuit  30  coupled to a Clock Generator  20 . The complementary clock signals, CLKL and CLKB, are input to the Duty Cycle Correction Circuit  30 . Working in concert, Duty Cycle Correction Circuit  30  and Adjustor Circuit  40  set the duty cycle of the CLK signal such that the two cross points of the CLKL and CLKB signals are separated by half the cycle time. In contrast, DRR  26  is sensitive only to the rising edges of the CLKL and CLKB signals; for optimal timing, these rising edges should be separated in phase by 180 degrees. The DCCV and DCCVB signals allow Adjustor Circuit  40  to modify the duty cycle of the CLK signal. Measuring the differences between the CLKL and CLKB signals, the Duty Cycle Correction Circuit  30  is sensitive to the cross points of the CLKL and CLKB signals. In contrast, DRR  26  is sensitive only to the rising edges of the CLKL and CLKB signals. Thus, DRR  26  and Duty Cycle Correction Circuit (DCCC)  30  use different definitions of duty cycle.  
           [0005]    [0005]FIG. 3 plots the CLKL and CLKB signals and indicates their duty cycles using a number of definitions. Generally, duty cycle is defined as a signal&#39;s high time divided by the sum of the signal&#39;s high and low time; i.e., the total cycle time. No disagreement exists as to what constitutes a signal&#39;s total cycle time; however, there are a number of competing definitions of cycle high time. In FIG. 3 “t 1 ” indicates the high time of the CLKL signal as the time between when the rising edge of the CLKL signal crosses the falling edge of the CLKB signal and when the falling edge of the CLKL signal intersects the rising edge of the CLKB signal. Thus, t 1  represents the cross-point high time to which the DCCC  30  is sensitive. In FIG. 3 “t 2 ” indicates the high time of the CLKL signal as the time from when the voltage of the rising edge of the CLKL signal exceeds a selected threshold level to when the voltage of the rising edge of the CLKB signal exceeds the selected threshold level. Thus, t 2  represents the rising edge high time to which the DRR  26  is sensitive. Within an integrated circuit using a DRR  26  and a Duty Cycle Correction Circuit  30  even a small difference between the cross-point high time and the rising edge high time substantially impacts receive time margins. Thus, a need exists for a converter circuit to generate a pair of signals whose cross-point duty cycle is equal to the midpoint duty cycle of the CLKL and CLKB signals. Inserted between a DRR  26  and a Duty Cycle Correction Circuit  30 , such a converter circuit would improve receive time margins.  
         SUMMARY OF THE INVENTION  
         [0006]    The apparatus of the present invention generates a pair of output signals whose cross-point duty cycle is substantially equal to the edge duty cycle of a pair of input signals. The apparatus of the present invention includes an edge detector and a signal generator. The edge detector detects and indicates a first transition of a first input signal and a second transition of a second input signal. The signal generator takes the outputs of the edge detector and generates a first output signal and a second output signal offset from the first output signal. The signal generator does so by forcing a first time delay between adjacent cross-over points of the first and second output signals to be substantially equal to a second time delay between the first transition and the second transition. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]    Additional features of the invention will be more readily apparent from the following detailed description and appended claims when taken in conjunction with the drawings, in which:  
         [0008]    [0008]FIG. 1 illustrates a prior art Double Data Rate input Receiver (DRR).  
         [0009]    [0009]FIG. 2 illustrates a prior art Duty Cycle Correction Circuit coupled to a DRR.  
         [0010]    [0010]FIG. 3 plots the clock signals input to the DRR of FIG. 1 and indicates their duty cycles using a number of definitions.  
         [0011]    [0011]FIG. 4 illustrates an integrated circuit including the Duty Cycle Converter of the present invention.  
         [0012]    [0012]FIG. 5 is a timing diagram of the input and output signals associated with the Duty Cycle Converter of FIG. 4.  
         [0013]    [0013]FIG. 6 illustrates in block diagram form an embodiment of the Duty Cycle Converter.  
         [0014]    [0014]FIG. 7 illustrates an embodiment of the Edge Detector of the Duty Cycle Converter.  
         [0015]    [0015]FIG. 8 illustrates an embodiment of the Signal Generator of FIG. 6.  
         [0016]    [0016]FIG. 9 illustrates schematically the embodiment of the Signal Generator of FIG. 8.  
         [0017]    [0017]FIG. 10 illustrates another embodiment of Edge Detector of FIG. 6. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0018]    [0018]FIG. 4 illustrates an Integrated Circuit  50  including the Duty Cycle Converter  60  of the present invention. Clock Generator  20  generates a true clock, the CLKL signal on line  22 , and a complement clock, the CLKB signal on line  24 , from a single phase clock, the CLK signal on line  21 . Duty Cycle Converter  60 , Duty Cycle Correction Circuit  30  and Adjustor Circuit  40  cooperate to bring to 180° the phase difference between the CLKL and CLKB signals, which are used to clock DRR  26 . Duty Cycle Converter  60  receives the CLKL and CLKB signals and determines when their selected polarity transitions occur. The selected polarity transitions may be positive or negative. The time delay between the selected polarity transitions of the CLKL and CLKB signals are indicative of their selected polarity duty cycle. Duty Cycle Converter  60  uses these selected polarity transitions to generate a pair of output signals, the CCLKL and CCLKB signals, whose cross-points are substantially equal to the difference between the selected edge transitions of the CLKL and CLKB signals. Thus, Duty Cycle Converter  60  enables Duty Cycle Correction Circuit  30  and Adjustor Circuit  40  to offset the CLKB signal by 180° from the CLKL signal, thereby improving receive timing margins within Integrated Circuit  50 . Receive timing margins may be improved by as much as 50 picoseconds using Duty Cycle Converter  60 .  
         [0019]    A. A Duty Cycle Converter Sensitive to Positive Polarity Transitions  
         [0020]    [0020]FIG. 5 is a timing diagram of the input and output signals associated with a Duty Cycle Converter  60   a  sensitive to positive polarity transitions; i.e., rising edges. FIG. 5 shows the CLKL signal  23  on line  22  and the CLKB signal  25  on line  24 . The Figure also shows the CCLKL signal  63  output on line  62  and the CCLKB signal  65  on line  64 . FIG. 5 illustrates that the time t 3  between the rising edge midpoints of the CLKL signal and the CLKB signal equals the time t 4  between adjacent cross-points of CCLKL signal  63  and CCLKB signal  65 .  
         [0021]    [0021]FIG. 6 illustrates in block diagram form a Duty Cycle Converter  60   a  sensitive to positive polarity transitions. Duty Cycle Converter  60  includes Edge Detector  66   a  and Signal Generator  68   a . Edge Detector  66   a  receives as inputs the CLKL signal on line  22  and the CLKB signal on line  24 . Edge Detector  66   a  detects the midpoint of the rising edges of the both the CLKL and CLKB signals and generates output signals indicating these events, which are coupled to Signal Generator  68 . Edge Detector  66   a  indicates the midpoint of the rising edge of the CLKL signal via the TrueRiseDetect signal on line  80 . FIG. 5 illustrates the TrueRiseDetect signal as Waveform  81 . Waveform  81  indicates the rising edge of the CLKL signal with pulse  85 . Referring again to FIG. 6, Edge Detector  66   a  indicates the midpoint of the CLKB signal with the ComplementRiseDetect signal on line  82 . FIG. 5 illustrates the ComplementRiseDetect signal via Waveform  83 , which indicates the rising edge of the CLKB signal with pulse  87 .  
         [0022]    While an embodiment of Edge Detector  66  that is sensitive to the midpoints of rising edges of the CLKL and CLKB signals has been discussed, other embodiments are possible. Another embodiment of Edge Detector  66  sensitive to falling, rather than rising, edges of the CLKL and CLKB signals will be discussed below with respect to FIGS.  11 - 13 . In yet another embodiment, Edge Detector  66  may be sensitive to voltage levels other than the midpoints of the CLKL and CLKB signals, for example, such as voltage levels representing 20% or 80% of the maximum voltage level of the CLKL and CLKB signals.  
         [0023]    Referring to FIG. 6, Signal Generator  68   a  takes the TrueRiseDetect and ComplementRiseDetect signals and generates the CCLKL signal on line  62   a  and the CCLKB signal on line  64   a . Signal Generator  68   a  responds to the active state of the TrueRiseDetect signal by forcing the CCLKL signal to an active state and the CCLKB signal to an inactive state. FIG. 5 represents the active state as a high voltage level and the inactive state as a low voltage level; however, other voltage levels may be used to represent the active and inactive states consistent with the present invention.  
         [0024]    Referring once again to FIG. 6, Signal Generator  68   a  responds to the active state of the ComplementRiseDetect signal by forcing the CCLKL signal to an inactive state and the CCLKB to an active state. By forcing both the CCLKL and CCLKB signals to transition between states at the same time, Signal Generator  68  forces the cross-point duty cycle of these signals to equal the rising edge duty cycle of the CLKL and the CLKB signals.  
         [0025]    [0025]FIG. 7 illustrates an embodiment of Duty Cycle Converter  60   a  that realizes Edge Detector  66   a  as two Positive Edge Detectors  67   a  and  67   b . Positive Edge Detector  67   a  recognizes the midpoint of the CLKL signal and in response generates the TrueRiseDetect signal on line  80 . Positive Edge Detector  67   b  recognizes the midpoint of the CLKB signal and in response generates the ComplementRiseDetect signal on line  82 .  
         [0026]    [0026]FIG. 8 illustrates in greater detail the embodiment of Edge Detector  66   a  of FIG. 7. In the illustrated embodiment, each Positive Edge Detector  67   a  and  67   b  includes a logical NAND gate  100  and a group of serially coupled Inverters  102 . Within Positive Edge Detector  67   a , one input to logical NAND gate  100   a  is coupled directly to the CLKL signal. The CLKL signal is also input to the group of serially coupled Inverters  102   a , the output of which is coupled to the other input of logical NAND gate  100   a . Observe that prior to a digital low to high transition, serially coupled Inverters  102   a  apply a digital high value to one input node of logical NAND gate  100   a . Therefore, the output of logical NAND gate  100   a  will go low when a digital high signal is received at the other input node of logical NAND gate  100   a . Thus, Positive Edge Detector  100   a  responds to a selected point on the rising edge of the CLKL signal by pulsing low the TrueRiseDetect signal on line  80 . The location of the selected point on the rising edge is a function of the threshold voltage, V TH  of logical NAND gate  100   a . Thus, control of V TH  allows the selected point of the rising edge to be set at any desired percentage of the CLKL signal. The duration of the low pulse of TrueRiseDetect signal is determined by the number of inverters included within the group of serially coupled Inverters  102   a . The total delay produced by the group of serially coupled Inverters  102   a  should be sufficient to cause Signal Generator  68  to change state. Positive Edge Detector  67   b  operates in a similar fashion, and is preferably matched, to Positive Edge Detector  67   a.    
         [0027]    In the embodiment of FIG. 8, Signal Generator  68   a  is realized as a Set-Bar Reset-Bar (SBRB) Flip-Flop  68   a . FIG. 9 illustrates schematically SBRB Flip-Flop  68   a , which includes a pair of logical NAND gates  110  and  112 , coupled together in the classic Flip-Flop configuration. One input of logical NAND gate  110  is coupled to the TrueRiseDetect signal on line  80 , while the other input of logical NAND gate  110  is coupled to the output of logical NAND gate  112 , on line  64 . One input of logical NAND gate  112  is coupled to the ComplementRiseDetect signal on line  82 , while the other input of the logical NAND gate  112  is coupled to the output of logical NAND gate  110 . FIG. 5 illustrates the operation of SBRB Flip-Flip  68   a , plotting both its input signals  81  and  83 , and its output signals  63  and  65 .  
         [0028]    [0028]FIG. 10 illustrates another embodiment of Edge Detector  66   a , which, in addition to Positive Edge Detectors  67   a  and  67   b , includes Matching Input Circuits  69   a  and  69   b . Inserted between an input signal and a Positive Edge Detector  67 , each Matching Input Circuit  69  helps match the loads driven by the CLKL and CLKB signals, as well as matching the switching thresholds. Each Matching Input Circuit  69   a  and  69   b  is an identical DRR, which includes a D Flip-Flop (D-FF)  120  and an Inverter  122 , coupled between the Q output and the D input of D-FF  120 .  
         [0029]    B. A Duty Cycle Converter Sensitive to Negative Polarity Transitions  
         [0030]    [0030]FIG. 11 illustrates schematically Duty Cycle Converter  60   b , which is sensitive to negative polarity transitions; i.e, falling edges. Duty Cycle Converter  60   b  includes Edge Detector  66   b  and Signal Generator  68   b . Edge Detector  66   b  is realized as two Negative Edge Detectors  130   a  and  130   b . Negative Edge Detector  130   a  recognizes the midpoint of the falling CLKL signal and in response generates the TrueRiseDetect signal on line  136 . Negative Edge Detector  130   b  recognizes the midpoint of the falling CLKB signal and in response generates the ComplementRiseDetect signal on line  138 . Each Negative Edge Detector  130  is realized as a group of serially coupled inverters an a logical NOR gate, coupled together in the same configuration as used in the Positive Edge Detectors. Signal Generator  68   b  is realized a pair of logical NOR gates  150  &amp;  152 , coupled together in the classic Flip-Flop configuration.  
         [0031]    [0031]FIG. 12 is a timing diagram of the input and output signals associated with a Duty Cycle Converter  60   b . FIG. 12 shows the CLKL signal  160  and the CLKB signal  162 . The Figure also shows the CCLKL signal  164  and the CCLKB signal  166 . Observe that the time t 5  between the falling edge cross-points of the CLKL signal  160  and CLKB signal  162  equals the time t 6  between adjacent cross-points of CCLKL signal  164  and CCLKB signal  166 .  
       Alternate Embodiments  
       [0032]    While the present invention has been described with reference to a few specific embodiments, the description is illustrative of the invention and is not to be construed as limiting the invention. Various modifications may occur to those skilled in the art without departing from the true spirit and scope of the invention as defined by the appended claims.