Abstract:
Techniques pertaining to designs of a compensation voltage controlled current source (VCCS) used in low dropout voltage regulators are disclosed. According to one aspect of the present invention, a compensation voltage controlled current source (VCCS) is so designed to meet the low input/output voltage requirements. Various features of the VCCS are demonstrated through several embodiments.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a voltage regulator, more particularly to a low dropout voltage regulator with an improved voltage controlled current source. 
         [0003]    2. Description of Related Art 
         [0004]    Voltage regulators with low dropout (LDO) are widely used in power management systems of PC motherboards, notebooks computers, mobile phones, and many other products. As a voltage supply, the LDO voltage regulator demonstrates many advantages in the field. Perfect line and load regulation, high power supply rejection ratio (PSRR), fast response, very small quiescent current, and low noise make the LDO voltage regulator irreplaceable. Stabilizing the LDO voltage regulator with 1 uF low ESR (equivalent series resistance) ceramic capacitor under a large output current is still a challenge. 
         [0005]      FIG. 1  shows a typically conventional LDO voltage regulator  100  with a compensation voltage controlled current source (VCCS). The specific description to the conventional LDO voltage regulator may be referred in a reference entitled “A Frequency Compensation Scheme for LDO Voltage Regulators”, invented by Chaitanya K. Chava and Jose Silva-Martinez, published on IEEE J. Solid-State Circuits, vol. 51, pp. 1041-1050, June 2004, which is hereby incorporated by reference. 
         [0006]    The LDO voltage regulator  100  comprises a differential amplifier circuit  102 , an intermediate amplifier circuit  104 , an output pass circuit  106 , a feedback circuit  108  and a voltage controlled current source (VCCS)  110 . These circuits are intercoupled to form a voltage negative feedback loop. 
         [0007]    The differential amplifier circuit  102  includes a differential amplifier gm 1 , a resistor R 1  and a capacitor C 1  coupled in parallel between an output terminal of the differential amplifier gm 1  and a ground reference. The resistor R 1  and the capacitor C 1  may be an equivalent series resistance (ESR) and an equivalent series capacitance (ESC) of the differential amplifier circuit, respectively. 
         [0008]    The intermediate amplifier circuit  104  includes an amplifier gm 2  a resistor R 2  and a capacitor C 2  coupled in parallel between an output terminal of the amplifier gm 2  and the ground reference. An input terminal of the amplifier gm 2  is coupled to the output terminal of the differential amplifier gm 1 . The resistor R and the capacitor C 2  may be the ESR and the ESC of the intermediate amplifier circuit, respectively. 
         [0009]    The output pass circuit gm 3   106  includes a pass transistor MPass and an output capacitor Co. The pass transistor MPass is usually a P-type MOS field effect transistor. A control terminal of the pass transistor MPass such as a gate electrode of the MOS transistor is coupled to the output terminal of the amplifier gm 2 . An input terminal of the pass transistor MPass such as a source electrode of the MOS transistor is coupled to a power supply Vcc. An output voltage Vout is leaded from an output terminal of the pass transistor MPass such as a drain electrode of the MOS transistor. The output capacitor Co and a resistor R L  representative of a load are coupled in parallel between the output voltage Vout and the ground reference. 
         [0010]    The feedback circuit  108  includes a pair of ladder resistors R f1  and R f2  coupled in series between the output voltage Vout and the ground reference. One terminal of the resistor R f1  is coupled to the output terminal of the pass transistor MPass. A middle node B between the resistor R f1  and the resistor R f2  is coupled to an input terminal of the differential amplifier gm 1  for feedback. Another input terminal of the differential amplifier is coupled to a predetermined reference voltage. 
         [0011]    An input terminal of the VCCS  110  is coupled to a node A between the pass transistor and the feedback circuit, and an output terminal of the voltage controlled current source circuit is coupled to the node B. The VCCS  110  is designed for outputting a constant current into the node B depending on a voltage of the input terminal thereof. The VCCS  110  includes a NMOS transistor MN 1 , a current mirror, a first current source I 1 , a second current source I 2  and a compensation capacitor C C . A gate electrode of the MN 1  serves as the input terminal of the VCCS, a drain electrode of the MN 1  is coupled to an input terminal of the current mirror and a source electrode of the MN 1  is coupled to a terminal of the first current source I 1 . The other terminal of the first current source I 1  is grounded. One terminal of the compensation capacitor C C  is coupled to the source electrode of the MN 1 , and the other terminal of the compensation capacitor C C  is grounded. One terminal of the second current source I 2  is grounded, and the other terminal of the second current source I 2  serves as the output terminal of the VCCS  110 . An output terminal of the current mirror is coupled to the output terminal of the VCCS  110 . 
         [0012]    A small signal transfer function of the VCCS  110  is shown below: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       I 
                       fb 
                     
                     
                       V 
                       O 
                     
                   
                   = 
                   
                     
                       SC 
                       C 
                     
                     
                       1 
                       + 
                       
                         
                           SC 
                           C 
                         
                         
                           gm 
                           
                             MN 
                              
                             
                                 
                             
                              
                             1 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where I fb  denotes an output current of VCCS, V O  denotes a control voltage of the VCCS namely the output voltage Vout, SC C  denotes a conductance of the compensation capacitor C C  and gm MN1  denotes a transconductance between the drain and source electrodes of the MN 1 . 
         [0013]    A minimum operating supply voltage for the LDO voltage regulator is V drop     —     I1 +V drop     —     CurrentMirror +V dsat     —     MN1 , wherein V drop     —     I1  denotes a dropout voltage on the first current source I 1 , V drop     —     CurrentMirror  denotes a dropout voltage on the current mirror and V dsat     —     MN1  denotes a saturated dropout voltage between the drain and source electrodes of the MN 1 . A minimum output voltage of the LDO voltage regulator is V th     —     MN1 +V drop     —     I1 , wherein V th     —     MN1  denotes a threshold voltage of the MN 1 . 
         [0014]    In the standard CMOS, a body effect of the NMOS transistor can&#39;t be neglected. Usually, the NMOS transistor is formed on a substrate thereof directly. In  FIG. 1 , the body effect of the MN 1  may degrade its performance. If the body effect is considered, the equation (1) may become: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       I 
                       fb 
                     
                     
                       V 
                       O 
                     
                   
                   = 
                   
                     
                       SC 
                       C 
                     
                     
                       1 
                       + 
                       
                         
                           SC 
                           C 
                         
                         
                           ( 
                           
                             
                               gm 
                               
                                 MN 
                                  
                                 
                                     
                                 
                                  
                                 1 
                               
                             
                             - 
                             
                               gmb 
                               
                                 MN 
                                  
                                 
                                     
                                 
                                  
                                 1 
                               
                             
                           
                           ) 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
         [0000]    An item gmb MN1  which denotes a body effect conductance of the MN 1  is added. 
         [0015]    The minimum output voltage of the LDO voltage regulator is adversely affected because the threshold voltage of the MN 1  V th     —     MN1  has a relation to the body effect of the MN 1  according to following equation. 
         [0000]        V   th     —     MN1   =V   th0 +γ(√{square root over ( V   SB +2φ F |)}−√{square root over (|2φ F |)}) 
         [0000]    where V th0  denotes an intrinsic threshold voltage of the MN 1 , γ denotes a body effect constant, V SB  denotes a dropout voltage between the source electrode and the substrate of the MN 1  and φ F  denotes a fermi potential. The threshold voltage of the MN 1  V th     —     MN1  may become higher because the dropout voltage V SB  is larger than zero, thereby the minimum output voltage can&#39;t be low enough. This should limit the applications of the LDO voltage regulator. 
         [0016]    The LDO voltage regulator is mainly used to supply power for system level chips. With the size of system level chips gradually being reduced, supply voltages required by the system level chips are reduced in proportion. Hence, the LDO voltage regulator is required to operate with the low input voltage and the low output voltage. In some cases, the output voltage of the LDO voltage regulator may be 1.2V or more lower, and the input voltage of the LDO voltage regulator may be 2V or more lower. 
         [0017]    However, the threshold voltage V th  of the NMOS transistor in standard CMOS process commonly is 0.7V˜1.1V and can&#39;t be adjusted. Furthermore, a maximum technical error 1.0V should be considered usually. The dropout voltage V drop     —     I1  commonly is 0.4˜0.8V since it is twice of the saturated dropout voltage V dsat , which is 0.20.4V, between the gate and source electrodes of the NMOS transistor in standard CMOS process. Hence, the minimum output voltage V th     —     MN1 +V drop     —     I1  of the LDO voltage regulator shown in  FIG. 1  may be higher than 1.5V. At the same time, the dropout voltage V drop     —     CurrentMirror  on the current mirror is approximately equal to V dsat +V th , thereby the minimum operating supply voltage V drop     —     I1 +V drop     —     CurrentMirror +V dsat     —     MN1  for the LDO voltage regulator may be higher than 1.9V. As a result, the conventional LDO voltage regulator may not completely satisfy the low input/output voltage requirements. 
         [0018]    Thus, there is a need for LDO voltage regulators with an improved VCCS to overcome the above disadvantages. 
       SUMMARY OF THE INVENTION 
       [0019]    This section is for the purpose of summarizing some aspects of the present invention and to briefly introduce some preferred embodiments. Simplifications or omissions in this section as well as in the abstract or the title of this description may be made to avoid obscuring the purpose of this section, the abstract and the title. Such simplifications or omissions are not intended to limit the scope of the present invention. 
         [0020]    In general, the present invention is related to designs of a compensation voltage controlled current source (VCCS) used in low dropout voltage regulators. According to one aspect of the present invention, a compensation voltage controlled current source (VCCS) is so designed to meet the low input/output voltage requirements. In one embodiment, a LDO voltage regulator comprises:
       a differential amplifier circuit having a pair of input terminals and an output terminal, one input terminal coupled to a predetermined reference voltage;   an intermediate amplifier circuit having an output terminal and an input terminal coupled to the output terminal of the differential; and   an output pass circuit comprising a pass transistor and an output capacitor, the pass transistor having a control terminal coupled to the output terminal of the intermediate amplifier circuit, an input terminal coupled to a power supply and an output terminal taken as a voltage output node, the output capacitor coupled between the voltage output node and a ground reference;   a feedback circuit comprising a pair of ladder resistors coupled in series between the voltage output node and the ground reference, a node between the ladder resistors coupled to the other input terminal of the differential amplifier circuit; and   a voltage controlled current source (VCCS) having an input terminal coupled to the voltage output node and an output terminal coupled to the node between the ladder resistors; wherein   the VCCS comprises four NMOS field effect transistors MN 1 , MN 2 , MN 3  and MN 4 , a current mirror and a compensation capacitor Cc, a gate electrode of the MN 1  is coupled to a first predetermined voltage Vb 1  and a source electrode of the MN 1  is grounded, a gate electrode of the MN 2  is coupled to the first predetermined voltage Vb 1  and a source electrode of the MN 2  is grounded, a gate electrode of the MN 3  is coupled to a second predetermined voltage Vb 2 , a source electrode of the MN 3  is coupled to a drain electrode of the MN 1  and a drain electrode of the MN 3  is coupled to an input terminal of the current mirror, a gate electrode of the MN 4  is coupled to the second predetermined voltage Vb 2 , a source electrode of the MN 4  is coupled to a drain electrode of the MN 2  and a drain electrode of the MN 4  is coupled to an output terminal of the current mirror, the drain electrode of the MN 4  serves as the output terminal of the VCCS, one terminal of the compensation capacitor Cc is coupled to the drain electrode of the MN 2  and the other terminal of the compensation capacitor Cc serves as the input terminal of the VCCS.       
 
         [0027]    There are many objects, features, and advantages in the present invention, which will become apparent upon examining the following detailed description of an embodiment thereof, taken in conjunction with the attached drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0028]    These and other features, aspects, and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where: 
           [0029]      FIG. 1  shows a conventional LDO voltage regulator with a compensation voltage controlled current source (VCCS); 
           [0030]      FIG. 2  shows a LDO voltage regulator with an improved VCCS according to a first embodiment of the present invention; 
           [0031]      FIG. 3  is a circuit diagram showing the improved VCCS in  FIG. 2 ; 
           [0032]      FIG. 4  is a diagram showing a small signal equivalence circuit of  FIG. 3 ; 
           [0033]      FIG. 5  is a circuit diagram showing the LDO voltage regulator according to a second embodiment of the present invention; 
           [0034]      FIG. 6  is a diagram showing a small signal equivalence circuit from Vg to Vf in  FIG. 5 ; and 
           [0035]      FIG. 7  is a circuit diagram showing the LDO voltage regulator according to a third embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0036]    The detailed description of the present invention is presented largely in terms of procedures, steps, logic blocks, processing, or other symbolic representations that directly or indirectly resemble the operations of devices or systems contemplated in the present invention. These descriptions and representations are typically used by those skilled in the art to most effectively convey the substance of their work to others skilled in the art. 
         [0037]    Reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Further, the order of blocks in process flowcharts or diagrams or the use of sequence numbers representing one or more embodiments of the invention do not inherently indicate any particular order nor imply any limitations in the invention. 
         [0038]    Embodiments of the present invention are discussed herein with reference to  FIGS. 2-7 . However, those skilled in the art will readily appreciate that the detailed description given herein with respect to these figures is for explanatory purposes only as the invention extends beyond these limited embodiments. 
         [0039]    Several embodiments are provided to fully describe a low dropout (LDO) voltage regulator with an improved voltage controlled current source (VCCS) in the present invention.  FIG. 2  shows an exemplary LDO voltage regulator  200  according to one embodiment of the present invention. The LDO voltage regulator  200  of  FIG. 2  has a similar structure with the LDO voltage regulator in the prior art except for the VCCS  210 . The VCCS  210  according to the embodiment of the present invention comprises four NMOS field effect transistors MN 1 , MN 2 , MN 3  and MN 4 , a current mirror and a compensation capacitor Cc. A gate electrode of the MN 1  is coupled to a first predetermined voltage Vb 1  and a source electrode of the MN 1  is grounded. A gate electrode of the MN 2  is coupled to the first predetermined voltage Vb 1  and a source electrode of the MN 2  is grounded. Agate electrode of the MN 3  is coupled to a second predetermined voltage Vb 2 , a source electrode of the MN 3  is coupled to a drain electrode of the MN 1  and a drain electrode of the MN 3  is coupled to an input terminal of the current mirror. A gate electrode of the MN 4  is coupled to the second predetermined voltage Vb 2 , a source electrode of the MN 4  is coupled to a drain electrode of the MN 2  and a drain electrode of the MN 4  is coupled to an output terminal of the current mirror. The drain electrode of the MN 4  serves as an output terminal of the VCCS and is coupled to a node B between resistors R f1  and R f2  of a feedback circuit. One terminal of the compensation capacitor Cc is coupled to the drain electrode of the MN 2 , and the other terminal of the compensation capacitor Cc serves as an input terminal of the VCCS and is coupled to a node A between a pass transistor MPass and the feedback circuit. 
         [0040]    The improved VCCS  210  is designed for injecting only a small signal current into the node B shown in  FIG. 2 . In another word, there is no direct current injected into the node B. In order to ensure that the direct current injected into the node B is zero, a direct current which flows out of the current mirror after a direct current of the MN 1  and MN 3  pass through the current mirror is required to be equal to a direct current of the MN 2  and MN 4 . In one embodiment, the gate voltages of the MN 1  and the MN 2  are equal and both are Vb 1 , so a ratio of the direct current of the MN 2  to the direct current of the MN 1  is (W/L) MN2 /(W/L) MN1 , wherein (W/L) MN2  denotes a ratio of width to length of the MN 2 , (W/L) MN1  denotes a ratio of width to length of the MN 1 . The width or length means a geometric size of the MOS transistor. Provided that a ratio of an input direct current to an output direct current of the current mirror is M, so (W/L) MN2 /(W/L) MN1  should be equal to M in this embodiment. For further matching the direct currents of the MN 3  and the MN 4 , the ratios of width to length of the MN 3  and the MN 4  should satisfy (W/L) MN4 /(W/L) MN3 =(W/L) MN2 /(W/L) MN1 . Thus, the direct current flowing out of the current mirror may be cancelled by the direct current of the MN 2  and the MN 4  so that there is no direct current injected into the node B. 
         [0041]      FIG. 3  is a circuit diagram showing the improved VCCS used in  FIG. 2 . 
         [0042]      FIG. 4  is a small signal equivalence circuit diagram of  FIG. 3 . For simplifying analysis, an output resistor Ro 2  of the MN 2  and an output resistor Ro 4  of the MN 4  is neglected since the resistances thereof are such big that an open circuit is equivalent. Usually, a condition of gm 4 &gt;&gt;1/ro 2  should be satisfied, wherein much more than means that one value is an order of magnitude higher than the other value, e.g. gm 4 &gt;10/ro 2 . According to KCL (Kirchhoff&#39;s Current Law), following equations are got. 
         [0000]      ( V   O   −V   X ) SC   C   +gm 4(− V   X )=0 
         [0000]        gm 4(− V   X )+ I   fb =0 
         [0000]    Solve these equations: 
         [0000]    
       
         
           
             
               I 
               fb 
             
             = 
             
               
                 V 
                 O 
               
                
               
                 SC 
                 C 
               
                
               
                 
                   gm 
                    
                   
                       
                   
                    
                   4 
                 
                 
                   
                     gm 
                      
                     
                         
                     
                      
                     4 
                   
                   + 
                   
                     SC 
                     C 
                   
                 
               
             
           
         
       
     
         [0000]    Then, following equation is got. 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       I 
                       fb 
                     
                     
                       V 
                       O 
                     
                   
                   = 
                   
                     
                       SC 
                       C 
                     
                     
                       1 
                       + 
                       
                         
                           SC 
                           C 
                         
                         
                           gm 
                            
                           
                               
                           
                            
                           4 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where gm 4  denotes a transconductance between the drain electrode and the source electrode of the MN 4 , Vx denotes a voltage of a node between the MN 2  and the MN 4 , SC C  denotes a conductance of the compensation capacitor Cc, and I fb  denotes the output current of the VCCS. 
         [0043]    Referring to  FIG. 4 , when a body effect of the NMOS transistor is considered, the equation (4) may become: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       I 
                       fb 
                     
                     
                       V 
                       O 
                     
                   
                   = 
                   
                     
                       SC 
                       C 
                     
                     
                       1 
                       + 
                       
                         
                           SC 
                           C 
                         
                         
                           ( 
                           
                             
                               gm 
                                
                               
                                   
                               
                                
                               4 
                             
                             + 
                             
                               gmb 
                                
                               
                                   
                               
                                
                               4 
                             
                           
                           ) 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
         [0044]    An item gmb 4  which denotes a body effect conductance of the MN 4  is added. Comparing the equation (5) to the equation (2), gm 4 +gmb 4  in the present invention is larger than gm MN1 −gmb MN1  in the prior art because both gmb MN1  and gmb 4  are positive, gm 4  is approximately equal to gm 1  and gmb MN1  is approximately equal to gmb 4 . Hence, a frequency 
         [0000]    
       
         
           
             
               ( 
               
                 
                   gm 
                    
                   
                       
                   
                    
                   4 
                 
                 + 
                 
                   gmb 
                    
                   
                       
                   
                    
                   4 
                 
               
               ) 
             
             
               2 
                
               
                   
               
                
               π 
                
               
                   
               
                
               
                 C 
                 C 
               
             
           
         
       
     
         [0000]    of an undesirable pole in the present invention is higher than a frequency 
         [0000]    
       
         
           
             
               ( 
               
                 
                   gm 
                   
                     MN 
                      
                     
                         
                     
                      
                     1 
                   
                 
                 - 
                 
                   gmb 
                    
                   
                       
                   
                    
                   
                     1 
                     
                       MN 
                        
                       
                           
                       
                        
                       1 
                     
                   
                 
               
               ) 
             
             
               2 
                
               
                   
               
                
               π 
                
               
                   
               
                
               
                 C 
                 C 
               
             
           
         
       
     
         [0000]    of an undesirable pole in the prior art so that the undesirable pole in the present invention is more apt to be neglected. It can be observed that gmb 4  helps to push the undesirable pole to high frequency. As a result, the stability of the LDO voltage regulator is compensated by the improved VCCS. 
         [0045]    In the present invention, a minimum output voltage of the LDO voltage regulator shown in  FIG. 2  is V dsat     —     MN2 , wherein V dsat     —     MN2  denotes a saturated dropout voltage between the drain and source electrodes of the MN 2 . The saturated dropout voltage between the gate and source electrodes of the NMOS transistor in standard CMOS process is 0.2˜0.4V and can be adjusted by size of elements. However, the threshold voltage V th  of the NMOS transistor in standard CMOS process commonly is 0.7V˜1.1V and can&#39;t be adjusted. Furthermore, a maximum technical error 1.0V should also be also considered. Hence, the minimum output voltage, which is 0.2˜0.4V, of the LDO voltage regulator shown in  FIG. 2  is lower than the minimum output voltage V th     —     MN1 +V drop     —     I1  of the LDO voltage regulator in the prior art. An operating supply voltage for the LDO voltage regulator shown in  FIG. 2  is V dsat     —     MN1 +V dsat     —     MN2 +V drop     —     CurrentMirror , wherein the dropout voltage V drop     —     CurrentMirror  on the current mirror is approximately equal to V dsat +V th . If V dsat  is designed to be 0.2V and the maximum V th  1.1v is considered, then the minimum operating supply voltage for the LDO voltage regulator shown in  FIG. 2  is 1.7V, which is lower than the minimum operation supply voltage 1.9V for the LDO voltage regulator in the prior art. 
         [0046]    In  FIG. 1 , an output capacitor Co and an ESR (not shown) of the output capacitor Co forms a zero. The zero frequency is shown in an equation below: 
         [0000]    
       
         
           
             
               f 
               ESR 
             
             = 
             
               1 
               
                 2 
                  
                 
                     
                 
                  
                 π 
                  
                 
                     
                 
                  
                 
                   R 
                   ESR 
                 
                  
                 
                   C 
                   o 
                 
               
             
           
         
       
     
         [0000]    For the small ceramic output capacitor Co with low ESR, the zero f ESR  can be neglected usually because it is at a very high frequency. 
         [0047]    In  FIG. 1 , there are three poles and one zero listed hereafter: 
         [0000]    
       
         
           
             
               
                 f 
                 
                   P 
                    
                   
                       
                   
                    
                   1 
                 
               
               = 
               
                 1 
                 
                   2 
                    
                   
                       
                   
                    
                   π 
                    
                   
                       
                   
                    
                   
                     R 
                     1 
                   
                    
                   
                     C 
                     1 
                   
                 
               
             
             , 
             
               
                 f 
                 
                   P 
                    
                   
                       
                   
                    
                   2 
                 
               
               = 
               
                 1 
                 
                   2 
                    
                   
                       
                   
                    
                   π 
                    
                   
                       
                   
                    
                   
                     R 
                     2 
                   
                    
                   
                     C 
                     2 
                   
                 
               
             
             , 
             
               
                 f 
                 
                   P 
                    
                   
                       
                   
                    
                   3 
                 
               
               = 
               
                 1 
                 
                   2 
                    
                   
                       
                   
                    
                   π 
                    
                   
                       
                   
                    
                   
                     R 
                     L 
                   
                    
                   
                     C 
                     O 
                   
                 
               
             
             , 
             
               
 
             
              
             
               
                 f 
                 
                   Z 
                    
                   
                       
                   
                    
                   1 
                 
               
               = 
               
                 1 
                 
                   2 
                    
                   
                       
                   
                    
                   π 
                    
                   
                       
                   
                    
                   
                     R 
                     
                       f 
                        
                       
                           
                       
                        
                       1 
                     
                   
                    
                   
                     C 
                     C 
                   
                 
               
             
           
         
       
     
         [0000]    where the pole f p1  is formed by the output resistor R 1  and the output capacitor C 1  of the differential amplifier circuit. The pole f p2  is formed by the output resistor R 2  and the output capacitor C 2  of the intermediate amplifier circuit. The pole f p3  is formed by the load resistor RL and the output capacitor C 2  of the output pass circuit. To stabilize the voltage negative feedback loop, one zero must be designed to cancel one pole, another pole must be pushed beyond the cross-over frequency and only one pole may be designed to be a domain pole. In the reference mentioned above, the pole f P3  is designed to be the dominant pole, the zero f Z1  is designed to cancel the pole f p2 , and the pole f P1  is pushed to high frequency beyond bandwidth. It should be noted that the pole f p2  may be cancelled by the zero f Z1  as long as the zero f Z1  is adjacent to the pole f p2 , but not requiring the zero f Z1  to be equal to the pole f p2 . 
         [0048]    However, in order to push the pole f P1  to high frequency, the differential amplifier circuit must be designed with very small size to minimize capacitance and resistance at the signal path thereof. It may lead to big mismatch. At the same time, the bandwidth is limited and the PSRR over 10 KHz may be poor. 
         [0049]    In order to overcome the above problem, the LDO voltage regulator according to the second embodiment is proposed in the present invention.  FIG. 5  shows the LDO voltage regulator according to the second embodiment of the present invention. The LDO voltage regulator shown in  FIG. 5  has two differences from the LDO voltage regulator shown in  FIG. 2 . One is that a resistor Ra is added between an output terminal of a pass transistor MPass and a voltage output node A. The other is that the input terminal of the improved VCCS is coupled to a node C between the pass transistor MPass and the resistor R a . With the new structure, another zero is added. 
         [0050]    Provided that a voltage of the node C is Vx, and a voltage of a node B between a resistors R f1  and a resistor R f2  of a feedback circuit is Vf.  FIG. 6  is a diagram showing a small signal equivalence circuit from the Vg to the Vf in  FIG. 5 , wherein the VCCS is replaced by a current source. According to KCL (Kirchhoff&#39;s Current Law) at the nodes A, B and C, following three equations is got. 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       g 
                       
                         m 
                          
                         
                             
                         
                          
                         3 
                       
                     
                      
                     
                       V 
                       g 
                     
                   
                   = 
                   
                     
                       
                         V 
                         x 
                       
                        
                       
                         ( 
                         
                           SC 
                           C 
                         
                         ) 
                       
                     
                     + 
                     
                       
                         ( 
                         
                           
                             V 
                             x 
                           
                           - 
                           
                             V 
                             O 
                           
                         
                         ) 
                       
                       / 
                       
                         R 
                         a 
                       
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
             
               
                 
                   
                     
                       ( 
                       
                         
                           V 
                           x 
                         
                         - 
                         
                           V 
                           O 
                         
                       
                       ) 
                     
                     / 
                     
                       R 
                       a 
                     
                   
                   = 
                   
                     
                       
                         ( 
                         
                           
                             V 
                             O 
                           
                           - 
                           
                             V 
                             f 
                           
                         
                         ) 
                       
                       / 
                       
                         R 
                         
                           f 
                            
                           
                               
                           
                            
                           1 
                         
                       
                     
                     + 
                     
                       
                         V 
                         O 
                       
                       / 
                       
                         ( 
                         
                           
                             R 
                             L 
                           
                           // 
                           
                             1 
                             
                               SC 
                               O 
                             
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
             
               
                 
                   
                     
                       
                         V 
                         x 
                       
                        
                       
                         ( 
                         
                           SC 
                           C 
                         
                         ) 
                       
                     
                     + 
                     
                       
                         ( 
                         
                           
                             V 
                             O 
                           
                           - 
                           
                             V 
                             f 
                           
                         
                         ) 
                       
                       / 
                       
                         R 
                         
                           f 
                            
                           
                               
                           
                            
                           1 
                         
                       
                     
                   
                   = 
                   
                     
                       V 
                       f 
                     
                     / 
                     
                       R 
                       
                         f 
                          
                         
                             
                         
                          
                         2 
                       
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
           
         
       
     
         [0051]    Solving these equations and supposing that R a &lt;&lt;R L &lt;&lt;R f1  and R a &lt;&lt;R L &lt;&lt;R f2 , we obtain: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       V 
                       f 
                     
                     / 
                     
                       V 
                       g 
                     
                   
                   = 
                   
                     
                       
                         g 
                         
                           m 
                            
                           
                               
                           
                            
                           3 
                         
                       
                        
                       
                         [ 
                         
                           
                             
                               R 
                               a 
                             
                              
                             
                               R 
                               
                                 f 
                                  
                                 
                                     
                                 
                                  
                                 1 
                               
                             
                              
                             
                               S 
                               2 
                             
                              
                             
                               C 
                               C 
                             
                              
                             
                               C 
                               O 
                             
                           
                           + 
                           
                             
                               SC 
                               C 
                             
                              
                             
                               R 
                               
                                 f 
                                  
                                 
                                     
                                 
                                  
                                 1 
                               
                             
                           
                           + 
                           1 
                         
                         ] 
                       
                     
                     
                       
                         ( 
                         
                           1 
                           + 
                           
                             
                               R 
                               
                                 f 
                                  
                                 
                                     
                                 
                                  
                                 1 
                               
                             
                             
                               R 
                               
                                 f 
                                  
                                 
                                     
                                 
                                  
                                 2 
                               
                             
                           
                         
                         ) 
                       
                        
                       
                         [ 
                         
                           
                             
                               C 
                               C 
                             
                              
                             
                               C 
                               O 
                             
                              
                             
                               R 
                               a 
                             
                              
                             
                               S 
                               2 
                             
                           
                           + 
                           
                             SC 
                             O 
                           
                           + 
                           
                             1 
                             
                               R 
                               L 
                             
                           
                         
                         ] 
                       
                     
                   
                 
               
               
                 
                   ( 
                   9 
                   ) 
                 
               
             
           
         
       
     
         [0000]    The equation (9) is a transfer function for the circuit in  FIG. 6 . The transfer function includes two poles and two zeros. The R a &lt;&lt;R L  means that a resistance value of the resistor R L  is an order of magnitude higher than that of the resistor R a  (e.g. R a &lt;R L /10). Provided that R a =0, the equation (9) becomes: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       V 
                       f 
                     
                     / 
                     
                       V 
                       g 
                     
                   
                   = 
                   
                     
                       
                         g 
                         
                           m 
                            
                           
                               
                           
                            
                           3 
                         
                       
                        
                       
                         ⌊ 
                         
                           
                             
                               SC 
                               C 
                             
                              
                             
                               R 
                               
                                 f 
                                  
                                 
                                     
                                 
                                  
                                 1 
                               
                             
                           
                           + 
                           1 
                         
                         ⌋ 
                       
                     
                     
                       
                         ( 
                         
                           1 
                           + 
                           
                             
                               R 
                               
                                 f 
                                  
                                 
                                     
                                 
                                  
                                 1 
                               
                             
                             
                               R 
                               
                                 f 
                                  
                                 
                                     
                                 
                                  
                                 2 
                               
                             
                           
                         
                         ) 
                       
                        
                       
                         [ 
                         
                           
                             SC 
                             O 
                           
                           + 
                           
                             1 
                             
                               R 
                               L 
                             
                           
                         
                         ] 
                       
                     
                   
                 
               
               
                 
                   ( 
                   10 
                   ) 
                 
               
             
           
         
       
     
         [0000]    Then, one pole and one zero are obtained according to the equation (10). 
         [0000]    
       
         
           
             
               
                 f 
                 
                   P 
                    
                   
                       
                   
                    
                   a 
                    
                   
                       
                   
                    
                   1 
                 
               
               = 
               
                 1 
                 
                   2 
                    
                   
                       
                   
                    
                   π 
                    
                   
                       
                   
                    
                   
                     R 
                     L 
                   
                    
                   
                     C 
                     O 
                   
                 
               
             
             , 
             
               
                 f 
                 
                   Z 
                    
                   
                       
                   
                    
                   a 
                    
                   
                       
                   
                    
                   1 
                 
               
               = 
               
                 1 
                 
                   2 
                    
                   
                       
                   
                    
                   π 
                    
                   
                       
                   
                    
                   
                     R 
                     
                       f 
                        
                       
                           
                       
                        
                       1 
                     
                   
                    
                   
                     C 
                     C 
                   
                 
               
             
           
         
       
     
         [0000]    Finally, another pole and another zero are got after calculation. 
         [0000]    
       
         
           
             
               
                 f 
                 
                   P 
                    
                   
                       
                   
                    
                   a 
                    
                   
                       
                   
                    
                   2 
                 
               
               = 
               
                 1 
                 
                   2 
                    
                   
                       
                   
                    
                   π 
                    
                   
                       
                   
                    
                   
                     R 
                     a 
                   
                    
                   
                     C 
                     C 
                   
                 
               
             
             , 
             
               
                 f 
                 
                   Z 
                    
                   
                       
                   
                    
                   a 
                    
                   
                       
                   
                    
                   2 
                 
               
               = 
               
                 1 
                 
                   2 
                    
                   
                       
                   
                    
                   π 
                    
                   
                       
                   
                    
                   
                     R 
                     a 
                   
                    
                   
                     C 
                     O 
                   
                 
               
             
           
         
       
     
         [0052]    In designs, C C  usually is far lower than any one of Co, C 1  and C 2 . Since the resistor R a  and the capacitor Cc both are very small, e.g. R a  is about 0.1 ohm and Cc is 1 pF, the pole f Pa2  is pushed to very high frequency and can be neglected. 
         [0053]    Taking the pole f p1  formed by an output resistor R 1  and an output capacitor C 1  of the differential amplifier circuit and the pole f, formed by an output resistor R 2  and an output capacitor C 2  of the intermediate amplifier circuit into account, the LDO regulator shown in  FIG. 5  has three poles and two zeros in all. 
         [0000]    
       
         
           
             
               
                 f 
                 
                   P 
                    
                   
                       
                   
                    
                   1 
                 
               
               = 
               
                 1 
                 
                   2 
                    
                   
                       
                   
                    
                   π 
                    
                   
                       
                   
                    
                   
                     R 
                     1 
                   
                    
                   
                     C 
                     1 
                   
                 
               
             
             , 
             
               
                 f 
                 
                   P 
                    
                   
                       
                   
                    
                   2 
                 
               
               = 
               
                 1 
                 
                   2 
                    
                   
                       
                   
                    
                   π 
                    
                   
                       
                   
                    
                   
                     R 
                     2 
                   
                    
                   
                     C 
                     2 
                   
                 
               
             
             , 
             
               
                 f 
                 
                   P 
                    
                   
                       
                   
                    
                   3 
                 
               
               = 
               
                 1 
                 
                   2 
                    
                   
                       
                   
                    
                   π 
                    
                   
                       
                   
                    
                   
                     R 
                     L 
                   
                    
                   
                     C 
                     O 
                   
                 
               
             
             , 
             
               
                 f 
                 
                   Z 
                    
                   
                       
                   
                    
                   1 
                 
               
               = 
               
                 1 
                 
                   2 
                    
                   
                       
                   
                    
                   π 
                    
                   
                       
                   
                    
                   
                     R 
                     
                       f 
                        
                       
                           
                       
                        
                       1 
                     
                   
                    
                   
                     C 
                     C 
                   
                 
               
             
             , 
             
               
 
             
              
             
               
                 f 
                 
                   Z 
                    
                   
                       
                   
                    
                   2 
                 
               
               = 
               
                 1 
                 
                   2 
                    
                   
                       
                   
                    
                   π 
                    
                   
                       
                   
                    
                   
                     R 
                     a 
                   
                    
                   
                     C 
                     O 
                   
                 
               
             
           
         
       
     
         [0054]    Comparing to the LDO voltage regulator shown in  FIG. 1 , another zero f a2  formed by the resistor R a  and the output capacitor Co is added within bandwidth of the LDO regulator shown in  FIG. 2 . 
         [0055]    To drive 300 mA or bigger current, the pass transistor MPass is designed with a big size so that a big capacitance at node of the gate electrode thereof is generated. The big capacitance of the pass transistor MPass is a part of the capacitor C 2 . Thus, the pole f P2  is taken as a dominant pole. The pole f P1  and the pole f P3  are canceled by the zero f Z1  and the zero f Z2 , respectively. As a result, the voltage negative feedback loop is very stable and has a phase margin of about 90 degree. 
         [0056]    For example, the pole f p1  is designed to be adjacent to the zero f z2  by choosing values of R 1 , C 1 , R a  and C o  so that the pole f P1  can be canceled by the zero f Z2 . In a preferred embodiment, a value of f p1 /f z2  may be within ⅓˜3. Correspondingly, the pole f p3  is designed to be adjacent to the zero f z1  by choosing values of R 2 , C 2 , R f1  and Cc so that the pole f p3  can be canceled by the zero f z1 . In a preferred embodiment, a value of f p3 /f z1  may be within ⅓˜3. 
         [0057]    A specific design is that R L =11Ω, C O =0.5 uF, f p3 ≈29 KHz; R f1 =1450 KΩ, Cc=3.8 pF, f z1 ≈29 KHz; R a =0.44Ω, C O =0.5 uF, f z2 ≈716 KHz; R 1 =112 KΩ, C 1 =2 pF, f p1 ≈711 KHz. 
         [0058]    It should be noted that there are various selections for values of the above parameters. Different parameter selections may result in different domain poles. Furthermore, there is no fixed mode in cancellation of the poles via the zero. Due to addition of the resistor R a , another zero within the bandwidth is provided in the LDO voltage regulator shown in  FIG. 2  to cancel one redundant pole so that stability of the feedback loop is increased. For avoiding adversely influence of the resistor R a , the value of the resistor R a  is designed to far less than that of the resistor R L , namely R a &lt;R L /10. Usually, the value of the resistor R a  is designed to less than 1Ω. 
         [0059]    The VCCS in  FIG. 5  has a similar structure with the VCCS of  FIG. 2 . The output terminal of the VCCS is coupled to the node B between the resistors R f1  and R f2  of the feedback circuit. The input terminal of the VCCS is coupled to a node C between the pass transistor MPass and the resistor R a . In this situation, the voltage on the input terminal of the VCCS has a proportion relation to the output voltage of the LDO voltage regulator. Hence, the minimum output voltage of the LDO voltage regulator shown in  FIG. 5  is reduced thereupon. 
         [0060]    In the embodiment of  FIG. 5 , since the resistor R a  requires to satisfy a predetermined condition and avoid an obvious dropout voltage thereon, the resistor R a  must be designed to be very small. The value of the resistor R a  is designed to less than 1Ω. It is difficult to fabricate such a resistor with so small resistance. Hence, the LDO voltage regulator according to the one embodiment is proposed in the present invention to overcome the problem. 
         [0061]      FIG. 7  shows the LDO voltage regulator according to another embodiment of the present invention. In  FIG. 7 , the output pass circuit includes a pair of P-type pass transistors coupled in parallel between the voltage output node A and the power supply Vcc. One is referred to as the first pass transistor MPass 1 , the other is referred to as the second pass transistor MPass. The resistor R a  is coupled between the second pass transistor MPass and the voltage output node A. The input terminal of the voltage controlled current source circuit is coupled to the node C between the second pass transistor MPass and the resistor R a . 
         [0062]    The ratio P of width to length of the second pass transistor MPass is far less than that 0 of the first pass transistor MPass 1 . The ratio N of P to O is within 1/1000˜1/100 in a preferred embodiment. The ratio N is 1/900 in this embodiment. Thereby, the current flowing through the second pass transistor MPass is far less than that flowing through the first pass transistor MPass 1 . In fabrication, one transistor from thousands of P-type MOS transistors coupled in parallel is taken as the second pass transistor MPass, the other transistors are taken as the first pass transistor MPass 1 . 
         [0063]    According to a small signal equivalence circuit from the Vg to the Vf in the LDO regulator shown in  FIG. 7 , the transfer function can be got by a same way mentioned above. Subsequently, a zero can be got according to similar method in the embodiment of  FIG. 4 . 
         [0000]    
       
         
           
             
               f 
               
                 Z 
                  
                 
                     
                 
                  
                 2 
               
             
             = 
             
               1 
               
                 2 
                  
                 
                     
                 
                  
                 π 
                  
                 
                     
                 
                  
                 
                   R 
                   a 
                 
                  
                 
                   
                     C 
                     O 
                   
                   / 
                   N 
                 
               
             
           
         
       
     
         [0000]    The value of the R a /N in this embodiment may be near to the value of the R a  in the embodiment of  FIG. 4 , thereby the resistor R a  may has an order of magnitude of 100 Ω. 
         [0064]    The VCCS in the embodiment has a similar structure with the VCCS in the embodiment of  FIG. 2 . The output terminal of the VCCS is coupled to the node B between the resistors R f1  and R f2  of the feedback circuit. The input terminal of the VCCS is coupled to a node C between the second pass transistor MPass and the resistor R a . In this situation, the voltage on the input terminal of the VCCS has a proportion relation to the output voltage of the LDO voltage regulator. Hence, the minimum output voltage of the LDO voltage regulator shown in  FIG. 7  is reduced thereupon. 
         [0065]    The present invention has been described in sufficient details with a certain degree of particularity. It is understood to those skilled in the art that the present disclosure of embodiments has been made by way of examples only and that numerous changes in the arrangement and combination of parts may be resorted without departing from the spirit and scope of the invention as claimed. Accordingly, the scope of the present invention is defined by the appended claims rather than the foregoing description of embodiments.