Abstract:
Methods for program verifying a memory cell include generating an access line voltage in response to a count and applying the access line voltage to a control gate of the memory cell, and generating a pass signal in response to the access line voltage activating the memory cell. Methods further include comparing at least a portion of the count to an indication of a desired threshold voltage of the memory cell, and when the at least a portion of the count matches the indication of the desired threshold voltage of the memory cell, determining if the pass signal is present. Methods further include generating a signal indicative of a desire to inhibit further programming of the memory cell if the pass signal is present when the match is indicated.

Description:
RELATED APPLICATION 
     This Application is a Continuation of U.S. application Ser. No. 12/949,876, titled “PROGRAM VERIFY OPERATION IN A MEMORY DEVICE,” filed Nov. 19, 2010, (Allowed), which is commonly assigned and incorporated herein by reference. 
    
    
     TECHNICAL FIELD 
     The present embodiments relate generally to memory and a particular embodiment relates to program verify of a memory. 
     BACKGROUND 
     Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, flash drives, digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems. 
     A typical flash memory device is a type of memory in which the array of memory cells is typically organized into memory blocks that can be erased and reprogrammed on block-by-block basis instead of one byte at a time. Changes in a threshold voltage of each of the memory cells, through erasing or programming of a charge storage structure (e.g., floating gate or charge trap) or other physical phenomena (e.g., phase change or polarization), determine the data value of each cell. The data in a cell of this type is determined by the presence or absence of the charge in the charge storage structure. 
     A programming operation typically comprises a series of incrementally increasing programming pulses that are applied to a control gate of a memory cell being programmed. A program verify operation after each programming pulse determines the threshold voltage of the memory cell resulting from the preceding programming pulse. 
     A typical program verify operation includes storing a target threshold voltage in a page buffer that is coupled to each data line (e.g., bit line) and applying a ramped voltage to the control gate of the memory cell being verified. When the ramped voltage reaches the threshold voltage to which the memory cell has been programmed, the memory cell turns on and sense circuitry detects a current on a bit line coupled to the memory cell. The detected current activates the sense circuitry to compare if the present threshold voltage is greater than or equal to the stored target threshold voltage. If the present threshold voltage is greater than or equal to the target threshold voltage, further programming is inhibited. 
     Performing a “greater than” comparison in the page buffer uses additional circuitry. For example, each page buffer might use two additional transistors just to perform the “greater than” comparison. Since each bit line is coupled to a different page buffer and a typical NAND flash memory device can have hundreds of thousands of bit lines, the additional circuitry just to perform the “greater than” comparison can add up to be millions of transistors. Such a large number of transistors take up valuable real estate on the integrated circuit die that can be used for additional memory cells. 
     For the reasons stated above, and for other reasons that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for reducing the size of comparison circuitry in a memory device. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a schematic diagram of a portion of one embodiment of a NAND memory array. 
         FIG. 2  shows a block diagram of one embodiment of a program verify circuit. 
         FIG. 3  shows a flowchart of one embodiment of a program verify operation in accordance with the program verify circuit of  FIG. 2 . 
         FIG. 4  shows a block diagram of one embodiment of a memory system that can incorporate the program verify circuit of  FIG. 2 . 
     
    
    
     DETAILED DESCRIPTION 
     In the following detailed description, reference is made to the accompanying drawings that form a part hereof and in which is shown, by way of illustration, specific embodiments. In the drawings, like numerals describe substantially similar components throughout the several views. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense. 
       FIG. 1  illustrates a schematic diagram of one embodiment of a portion of a NAND architecture memory array  101  comprising series strings of non-volatile memory cells. The schematic diagram of  FIG. 1  is for purposes of illustration only as the memory array architecture is not limited to the illustrated NAND architecture. Alternate embodiments can use NOR or other architectures as well. 
     The memory array  101  comprises an array of non-volatile memory cells (e.g., floating gate) arranged in columns such as series strings  104 ,  105 . Each of the cells is coupled drain to source in each series string  104 ,  105 . An access line (e.g. word line) WL 0 -WL 31  that spans across multiple series strings  104 ,  105  is coupled to the control gates of each memory cell in a row in order to bias the control gates of the memory cells in the row. Data lines, such as even/odd bit lines BL_E, BL_O, are coupled to the series strings and eventually each bit line is coupled to a page buffer with sense circuitry that detects the state of each cell by sensing current or voltage on a selected bit line. 
     Each series string  104 ,  105  of memory cells is coupled to a source line  106  by a source select gate  116 ,  117  (e.g., transistor) and to an individual bit line BL_E, BL_O by a drain select gate  112 ,  113  (e.g., transistor). The source select gates  116 ,  117  are controlled by a source select gate control line SG(S)  118  coupled to their control gates. The drain select gates  112 ,  113  are controlled by a drain select gate control line SG(D)  114 . 
     Each memory cell can be programmed as a single level cell (SLC) or a multiple level cell (MLC). Each cell&#39;s threshold voltage (V t ) is indicative of the data that is stored in the cell. For example, in an SLC, a V t  of 2.5V might indicate a programmed cell while a V t  of −0.5V might indicate an erased cell. An MLC uses multiple V t  ranges that each indicates a different state. Multilevel cells can take advantage of the analog nature of a traditional flash cell by assigning a bit pattern to a specific V t  range. This technology permits the storage of data values representing two or more bits per cell, depending on the quantity of V t  ranges assigned to the cell. 
     During a program verify operation, a word line digital-to-analog converter (DAC) generates a ramped voltage, from a digital count, that is applied via a word line to the control gate of each selected memory cell. When the ramped voltage reaches the voltage to which the selected memory cell is programmed (e.g., V t ), the selected memory cell conducts and generates a current on the bit line to which it is coupled. The digital count that generated the particular voltage that activated the selected memory cell can then be used as being indicative of the particular voltage. 
       FIG. 2  illustrates a block diagram of one embodiment of a page buffer  200  that is coupled to one of the bit lines of  FIG. 1 . Each bit line of a memory array can be coupled to a different page buffer. In one embodiment, each page buffer is substantially similar to the block diagram of  FIG. 2 . 
       FIG. 2  also illustrates an example of a digital counter  210  and digital-to-analog converter (DAC)  211 . The digital counter  210  is an n-bit digital counter that inputs an incrementing digital count signal to the DAC  211 . The DAC  211  uses the digital count to generate the ramped voltage. 
     The page buffer  200  includes sense circuitry (e.g., sense amplifier)  201  that is coupled to the bit line. The sense circuitry  201  is responsible for detecting a current on the bit line when a selected memory cell that is coupled to the bit line is activated. The sense circuitry  201  is configured to output a pass/fail signal in response to the detected current. The pass signal (e.g., a positive pulse) indicates that a current was detected. The fail signal (e.g., no pulse) indicates that a current has not been detected. 
     The page buffer  200  further includes match circuitry, such as a target threshold voltage data cache  203  that is coupled to the n-bit digital counter  210 . The target threshold voltage data cache  203  is configured to store an indication of a desired target V t  at the start of a programming operation. In one embodiment, the indication of the target V t  is stored as a digital representation of the threshold voltage. The digital representation of the threshold voltage, in one embodiment, is the digital count that generates the particular voltage, of a ramped voltage, that activates the selected memory cell. In an alternate embodiment, the indication of the target V t  may be stored as an analog voltage. 
     The digital count from the digital counter  210 , in the illustrated embodiment, is an m-bit digital word. In one embodiment, m&lt;n. In such an embodiment, the indication of the target Vt should also be an m-bit digital word. In an alternate embodiment, m can equal n. 
     The output of the target threshold voltage data cache  203  is a match signal (e.g., positive pulse) that indicates when the digital count (or, in the case of m&lt;n, when at least a portion of the digital count) from the n-bit counter  210  matches the target V t  stored at the start of the programming operation. The target threshold voltage data cache  203  performs a comparison when a digital count (or at least a portion of the digital count, such as when m&lt;n) is input to the target threshold data cache  203  and outputs the match signal when the two digital values match. 
     The page buffer  200  further includes an inhibit latch  205  that is coupled to both the sense circuitry  201  and the target threshold voltage data cache  203 . The inhibit latch  205  is set when both the MATCH signal and the PASS/FAIL signal are true. In other words, the inhibit latch is set when the PASS/FAIL signal indicates that current has been detected on the bit line and the MATCH signal indicates that the stored V t  is equal to the digital count input to the page buffer  200 . The INHIBIT signal is an indication that the selected memory cell is programmed to the target threshold voltage. 
     The INHIBIT signal indicates to the memory control circuitry to inhibit further programming of the selected memory cell. In one embodiment, the memory control circuitry controls biasing of the bit lines during programming of the memory cells. A bit line that is biased at 0V enables memory cells coupled to that particular bit line to be programmed by the proper word line programming voltage. Increasing the bit line voltage slows the programming of the memory cells coupled to that particular bit line. The memory control circuitry can control generation of an inhibit voltage (e.g., V CC ) to bias the selected bit line when the INHIBIT signal is true. 
     A flowchart of one embodiment of a program verify operation, in accordance with  FIG. 2 , is illustrated in  FIG. 3 . Reference can be made to  FIG. 2  for operation of the various components of the block diagram. 
     A programming pulse is applied to the control gate of the selected memory cell  300  via a selected word line. The programming pulse can increase the threshold voltage of the memory cell being programmed. An indication of a target V t  (e.g., digital data) is stored in the target threshold voltage data cache  301  prior to attempting to verify the memory cell. An initial digital count is generated  303  and input to the DAC  305  to begin generation of the ramped voltage that is applied  307 , via a word line, to a control gate of each selected memory cell coupled to the selected word line. The digital count or a particular number of bits of the digital count is input to the target threshold voltage data cache  309 . Each digital count of the count signal that is input to the target threshold voltage data cache is compared to the stored target V t    311 . 
     If the digital count is not equal to the stored target V t    311  the counter is incremented  315  and the incremented count is input to the DAC  305 . The ramped voltage continues to be generated and the count compared to the target V t  until the input count is equal to the stored target V t    311 . The sense circuitry is then checked for the PASS/FAIL signal  317 . 
     If the PASS/FAIL signal indicates a PASS condition  319 , the inhibit latch is set  321  to indicate that the threshold voltage of the memory cell has reached the stored target V t . Further programming of the selected memory cell can now be inhibited. 
     If the PASS/FAIL signal indicates a FAIL condition  319 , the verify operation that particular memory cell has failed  323 . Even though the DAC counter and DAC will continue to generate a ramped voltage for other memory cells being verified on the same word line, the particular memory cell that failed can receive another programming pulse and the program verify operation repeated. 
       FIG. 4  illustrates a functional block diagram of a memory device  400 . The memory device  400  is coupled to an external processor  410 . The processor  410  may be a microprocessor or some other type of controller. The memory device  400  and the processor  410  form part of a memory system  420 . 
     The memory device  400  includes an array  430  of memory cells (e.g., non-volatile memory cells). The memory array  430  is arranged in banks of word line rows and bit line columns. In one embodiment, the columns of the memory array  430  comprise series strings of memory cells. 
     Address buffer circuitry  440  is provided to latch address signals provided through I/O circuitry  460 . Address signals are received and decoded by a row decoder  444  and a column decoder  446  to access the memory array  430 . 
     The memory device  400  reads data in the memory array  430  by sensing voltage or current changes in the memory array columns using sense amplifier circuitry  450 . The page buffers  450 , in one embodiment, are coupled to read and latch a row of data from the memory array  430 . The page buffers  450 , as previously described, include the sense circuitry as well as other circuits for performing a program verify operation. Data input and output buffer circuitry  460  is included for bidirectional data communication as well as the address communication over a plurality of data connections  462  with the controller  410 . Write circuitry  455  is provided to write data to the memory array. 
     Memory control circuitry  470  decodes signals provided on control connections  472  from the processor  410 . These signals are used to control the operations on the memory array  430 , including data read, data write (program), and erase operations. The memory control circuitry  470  may be a state machine, a sequencer, or some other type of controller to generate the memory control signals. In one embodiment, the memory control circuitry  470  is configured to control execution of the program verify embodiments of the present disclosure. 
     The memory device illustrated in  FIG. 4  has been simplified to facilitate a basic understanding of the features of the memory. A more detailed understanding of internal circuitry and functions of flash memories are known to those skilled in the art. 
     CONCLUSION 
     In summary, one or more embodiments of the program verify operation and program verify circuit can provide a program verify function of a memory cell using a reduced quantity of components as compared to the prior art. The circuit typically used for the “greater than” function in the page buffer can be eliminated by comparing at least a portion of a count, used to generate a ramped word line voltage, with a stored target V t . When the at least a portion of the count and target V t  are equal, a sense circuitry is then checked to determine if the memory cell has been activated by the voltage generated by the count. If the memory cell is activated, further programming of the memory cell can be inhibited. Otherwise, the memory cell continues with the programming operation. 
     Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the invention will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the invention.