Abstract:
This invention discloses charge pump apparati, where a charge pump apparatus, including a positive charge pump circuit and a negative charge pump circuit, providing multiple positive and negative voltages, comprises: a capacitor set shared by said positive charge pump circuit and said negative charge pump circuit; multiple electronic switches connected to said capacitor set and a plurality of voltage sources; multiple output capacitors connected to selected ones of said multiple electronic switches and one or more output terminals; and a non-overlapping time sequence that controls the on and off states of said multiple electronic switches; wherein under the control of said non-overlapping time sequence, corresponding electronic switches are turned on and off to control the output of the positive and negative voltages provided by said output capacitors to generate output voltages that are pre-determined multiples of the one or more input voltages. With this invention, coupling capacitors are shared during the processes of charging and discharging, and operate at alternating intervals through time sequence-control. As a result, both positive and negative output voltages can be simultaneously adjusted to provide different boost levels. The charge pump is both low in cost and has a design that is simple and easy to produce.

Description:
CROSS REFERENCE 
       [0001]    This application claims priority from a Chinese patent application entitled “A Type of Charge Pump Apparatus and Power Source Circuit” filed on May 17, 2007, having a Chinese Application No. 200710074500.x. This Chinese application is incorporated here by reference. 
       FIELD OF THE INVENTION 
       [0002]    This invention is related to electrical charge pump circuits and, in particular to, charge pump circuits capable of providing multiple levels of power levels. 
       BACKGROUND TECHNOLOGY 
       [0003]    In most integrated circuit systems, it is necessary for a semiconductor chip (“on-chip”) to produce positive high voltage output (VP) and negative high voltage output (VN), the absolute values of which are higher than the input power source voltage (VDD). For example, in liquid crystal display driver apparati, in order to achieve high display quality, both positive and negative high voltage power sources and positive and negative high voltage driving voltages are needed when driving the liquid crystal screen. At this time, a charge pump comprising of one or more electronic switches, such as metal oxide semiconductors (MOS), and one or more coupling capacitors is used to raise an externally-provided voltage to the required high voltage. 
         [0004]      FIG. 1  shows the structure of the current charge pump that produces a 2× increased voltage, including input voltage Vin; two electronic switches, S 1  and S 2 , used for charging; two electronic switches, S 3  and S 4 , used for discharging; a coupling capacitor C 1 ; and an output capacitor Co. 
         [0005]      FIG. 2  shows the control sequence for the four electronic switches used in the operation of this circuit. Herein, the control signal for electronic switches S 1  and S 2  and the control signal for electronic switches S 3  and S 4  do not overlap, and have Break Before Make (BBM) time. During time t 1 , electronic switches S 1  and S 2  are on, and electronic switches S 3  and S 4  are off; input voltage Vin charges capacitor C 1 ; after capacitor C 1  has stored a full charge, capacitor C 1  stores a charge of value Vin. During time t 2 , electronic switches S 3  and S 4  are on, and electronic switches S 1  and S 2  are off; when input voltage Vin has gone through capacitor C 1  to output terminal Vo, output terminal Vo then passes through output capacitor Co to the zero-potential voltage VSS line, and stores a charge with value 2Vin/(C 1 +Co) in output capacitor Co. Suppose C 1 =Co, without considering the power consumption of the electronic switches and capacitors; through repeated charging and discharging, a charge of value 2Vin can be stored in output capacitor Co, therby obtaining  2 x voltage output, i.e. Vo=2Vin. 
         [0006]      FIG. 3  shows the structure of the current charge pump that produces −1× increased voltage, including input voltage Vin; two electronic switches, S 1  and S 2 , used for charging; two electronic switches, S 3  and S 4 , used for discharging; a coupling capacitor C 1 ; and an output capacitor Co. 
         [0007]    Illustration  4  shows the control sequence for the four electronic switches used in the operation of this circuit. Herein, the control signal for electronic switches S 1  and S 2  and the control signal for electronic switches S 3  and S 4  do not overlap, and have BBM time. During time t 1 , electronic switches S 1  and S 2  are on, and electronic switches S 3  and S 4  are off; input voltage Vin charges capacitor C 1 ; after capacitor C 1  has stored a full charge, capacitor C 1  stores a charge of value Vin. During time t 2 , electronic switches S 3  and S 4  are on, and electronic switches S 1  and S 2  are off; when input voltage Vin has gone through capacitor C 1  to output terminal Vo, output terminal Vo then passes through output capacitor Co to the zero-potential voltage VSS line, and stores a charge with value (0−Vin)/(C 1 +Co) in output capacitor Co. Suppose C 1 =Co, without considering the power consumption of the electronic switches and capacitors; through repeated charging and discharging, −1× voltage can be obtained, i.e. Vo=−1Vin. 
         [0008]    In current charge pump circuits, positive m-times voltage and negative n-times voltage must be simultaneously obtained, usually requiring (m+n−1) coupling capacitors, m≧2, n≧1, resulting in a rather large number of coupling capacitors in the charge pump. If the charge pump&#39;s coupling capacitors use on-chip capacitors, a large chip area is required, thereby increasing the cost of producing the circuit. If off-chip capacitors are used, the size and cost of the electronic equipment used to install the chip will also be increased. If a system requires multiple charge pumps, this problem only becomes more serious. Therefore, it is desirable to have a charge pump circuit that overcomes the problems of the prior art charge pump circuits. 
       SUMMARY OF THE INVENTION 
       [0009]    An object of this invention is to provide a type of charge pump apparatus that shares capacitors in generating the corresponding boosted positive and negative output voltages. 
         [0010]    Another object of this invention is to provide charge pump circuits having low component costs in realizing such an apparatus. 
         [0011]    Briefly, the present invention discloses in one aspect a charge pump apparatus, including a positive charge pump circuit and a negative charge pump circuit, providing multiple positive and negative voltages, comprising: a capacitor set shared by said positive charge pump circuit and said negative charge pump circuit; multiple electronic switches connected to said capacitor set and a plurality of voltage sources; multiple output capacitors connected to selected ones of said multiple electronic switches and one or more output terminals; and a non-overlapping time sequence that controls the on and off states of said multiple electronic switches; wherein under the control of said non-overlapping time sequence, corresponding electronic switches are turned on and off to control the output of the positive and negative voltages provided by said output capacitors to generate output voltages that are pre-determined multiples of the one or more input voltages. The embodiments of this invention share one or more coupling capacitors in the process of the charge pump charging and discharging, and, by controlling through time sequences operating at different time intervals, they can simultaneously generate multiples-adjustable, boosted positive voltages and negative voltages. 
         [0012]    An advantage of this invention is that it provides a type of charge pump apparatus that shares capacitors in generating the corresponding boosted positive and negative output voltages. 
         [0013]    Another advantage of this invention is that it provides charge pump circuits having low component costs in realizing such an apparatus. 
     
    
     
       DESCRIPTION OF THE FIGURES 
         [0014]      FIG. 1  is a structural diagram of a prior art charge pump, which provides a two time boost; 
           [0015]      FIG. 2  is a diagram of the control time-sequence for the electronic switches of the charge pump illustrated in  FIG. 1 ; 
           [0016]      FIG. 3  is a structural diagram of a prior art charge pump, which provides a −1 time boost; 
           [0017]      FIG. 4  is a diagram of the control time-sequence for the electronic switches of the charge pump illustrated in  FIG. 3 ; 
           [0018]      FIG. 5  is a structural diagram showing the sharing of a single coupling capacitor for the charge pumps provided by the embodiments of this invention; 
           [0019]      FIG. 6  is a structural diagram serving as a demonstrative example of the sharing of a single coupling capacitor for the charge pumps provided by the embodiments of this invention; 
           [0020]      FIG. 7  is a diagram of the control time-sequence for the electronic switches of the charge pump illustrated in  FIG. 6 ; 
           [0021]      FIG. 8  is a structural diagram showing the sharing of multiple coupling capacitors for the charge pumps provided by the embodiments of this invention; 
           [0022]      FIG. 9  is a structural diagram serving as a demonstrative example of the sharing of multiple coupling capacitors for the charge pump illustrated in  FIG. 8 , as provided by the embodiments of this invention; 
           [0023]      FIG. 10  is a structural diagram serving as a demonstrative example of a two-stage charge pump provided by embodiments of the present invention, where the second stage charge pump shares two coupling capacitors; 
           [0024]      FIG. 11  illustrates, through the numeric logic of  FIG. 10 , the realization conceptual diagram illustrating control by using the control time-sequence for the electronic switches of the second stage charge pump; 
           [0025]      FIG. 12  is the control time sequence diagram for the electronic switches of the second stage charge pump illustrated in  FIG. 10  when the positive and negative output voltages are 6 times and −5 times, respectively; 
           [0026]      FIG. 13  is the control time sequence diagram for the electronic switches of the second stage charge pump illustrated in  FIG. 10  when the positive and negative output voltages are 6 times and −4 times, respectively; 
           [0027]      FIG. 14  is the control time sequence diagram for the electronic switches of the second stage charge pump illustrated in  FIG. 10  when the positive and negative output voltages are 6 times and −3 times, respectively; 
           [0028]      FIG. 15  is the control time sequence diagram for the electronic switches of the second stage charge pump illustrated in  FIG. 10  when the positive and negative output voltages are 5 times and −5 times, respectively; 
           [0029]      FIG. 16  is the control time sequence diagram for the electronic switches of the second stage charge pump illustrated in  FIG. 10  when the positive and negative output voltages are 5 times and −4 times, respectively; 
           [0030]      FIG. 17  is the control time sequence diagram for the electronic switches of the second stage charge pump illustrated in  FIG. 10  when the positive and negative output voltages are respectively 5 times and −3 times; 
           [0031]      FIG. 18  is the control time sequence diagram for the electronic switches of the second stage charge pump illustrated in  FIG. 10  when the positive and negative output voltages are respectively 4 times and −5 times; 
           [0032]      FIG. 19  is the control time sequence diagram for the electronic switches of the second stage charge pump illustrated in  FIG. 10  when the positive and negative output voltages are respectively 4 times and −4 times; 
           [0033]      FIG. 20  is the control time sequence diagram for the electronic switches of the second stage charge pump illustrated in  FIG. 10  when the positive and negative output voltages are 4 times and −3 times, respectively; 
           [0034]      FIG. 21  is a structural diagram illustrating a second stage charge pump provided by the embodiments of this invention that shares three coupling capacitors; 
           [0035]      FIG. 22  is a structural diagram of a second stage charge pump of the embodiments of the present invention, providning a two-stage charge pump sharing m−1 coupling capacitors; and 
           [0036]      FIG. 23  is a structural diagram of the second stage charge pump illustrated in  FIG. 22 . 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0037]    In order to further clarify the goals, technology, and advantages of this invention, some illustrations and examples are provided below for more precise explanation. It should be understood that the descriptions provided here are only for clarification purposes, and not to limit the scope of this invention. 
         [0038]    In the embodiments of the present invention, the positive and negative charge pump in the charging and discharging process shares the same coupling capacitor; by controlling through time sequence to operate at different time intervals, multiples-adjustable, boosted positive voltage and negative voltage can be generated at the same time, where the boost multiple can be controlled through numeric logic. 
         [0039]      FIG. 5  illustrates a structure where a coupling capacitor is shared in realizing the charge pump structure where the circuit shares the same coupling capacitor; by controlling through the described non-overlapping time sequence, the electronic switches are conducting and non-conducting, controlling the charging and discharging of the capacitors. 
         [0040]    One terminal of capacitor C 1  connects to three electronic switches s 12 , s 13 , and s 16 ; electronic switches s 12 , s 13  and s 16  separately connect to voltages VSS 1 , VDD 1  and output terminal VN 1 . The other terminal of capacitor C 1  connects to three electronic switches s 11 , s 14 , and s 15 ; electronic switches s 11 , s 14 , and s 15  separately connect to voltage VDD 2 , output terminal VP 2  and voltage VSS 2 . Through control by using the non-overlapping time sequence, the switches are conducting or non-conducting, and thereby capacitor C 1  is charged and discharged, accomplishing 
         [0041]    In the embodiments of the invention, as illustrated by  FIG. 6 , when VDD 1 =VDD 2 =VDD and VSS 1 =VSS 2 =VSS=0, the charge pump can obtain 2 times and −1 time in voltage boost, or VP 2 =VDD 1 +VDD 2 =2VDD and VN 1 =−VDD 2 =−VDD. Compared to prior art charge pumps, only one capacitor is needed to obtain 2 times and −1 time in voltage boost, and the cost of the charge pump is lowered.  FIG. 7  illustrates the operating time sequence for operating the electronic switches of the charge pumps of  FIGS. 5 and 6 . 
         [0042]    For example, in  FIG. 6  during time t 1 , electronic switches s 11  and s 12  are conductive, and electronic switches s 13 , s 14 , s 15 , and s 16  are non-conductive. The C 1 B terminal of capacitor C 1  connects to the input voltage VDD, and the C 1 A terminal connects to the zero voltage VSS. Through connecting the input voltage VDD through capacitor C 1  to the zero voltage, VSS capacitor C 1  is charged and has VDD voltage potential. 
         [0043]    During time t 2 , electronic switches s 13  and s 14  conduct, electronic switches s 11 , s 12 , s 15 , and s 16  do not conduct, the C 1 A terminal of capacitor C 1  connects to voltage source VDD, and the C 1  terminal connects to the positive voltage terminal VP 2 , resulting in a route where input voltage VDD goes through capacitor C 1 , positive voltage terminal VP 2 , and output capacitor C 2  to zero voltage VSS, where the voltage at positive voltage terminal VP 2  is voltage VDD plus the VDD voltage stored in capacitor C 1  during time t 1  to realize a 2 times boost. 
         [0044]    During time t 3 , the operation of the electronic switches is the same as during time t 1 , where there is voltage potential VDD between the two terminals of capacitor C 1 . During time t 4 , electronic switches s 15  and s 16  are conductive, electronic switches s 11 , s 12 , s 13 , and s 14  are non-conductive, terminal C 1 B of capacitor C 1  connects to zero voltage VSS, and terminal C 1 A of capacitor C 1  connects to negative voltage output terminal VN 1 , forming a route from zero voltage VSS through capacitor C 1 , negative voltage terminal VN 1 , and output capacitor C 3  to zero voltage VSS, where the voltage at negative voltage terminal VN 1  equals zero voltage VSS minus the voltage potential stored in capacitor C 1  during time t 3 , realizing a boost of −1 time. 
         [0045]    If the loss between electronic switches and capacitors is not considered after repeatedly charging and discharging, 2 times positive high output voltage and −1 time negative high output voltage VN 1  can be obtained, or VP 2 =2VDD and VN 1 =−1VDD. 
         [0046]      FIG. 8  illustrates structures of the embodiments of the present invention, where multiple coupling capacitors are shared by the charge pump embodiments of the present invention. Through sharing of m coupling capacitors C 1 , C 2  to Cm and using the non-overlapping control time sequence to control the conductiveness and non-conductiveness of the electronic switches, the capacitors are charged, discharged, and simultaneous generating VPx and VNx output voltage, where the charge pumps have 4 operating modes. 
         [0047]    C 1 , C 2  to Cm totaling m capacitors are serially connected and controlled by electronic switches S(2m+1) and S(2m+2) . . . S(3m−1), where m is a whole number larger or equal to 1. The first terminals of capacitors C 1 , C 2  . . . Cm (C 1 A, C 2 A . . . CmA) respectively connect to electronic switches S 1 , S 2  . . . Sm; electronic switches S 1 , S 2  . . . Sm respectively connect to VCC 1  and VCC 2  . . . VCCm, and respectively connect to capacitors C 1 , C 2  . . . Cm to connect/disconnect to voltages VCC 1 , VCC 2  . . . VCCm. 
         [0048]    The second terminals of the capacitors C 1 , C 2  . . . Cm (C 1 B, C 2 B . . . CmB) respectively are connected to electronic switches S(m+1), S(m+2) . . . S(2m); electronic switches S(m+1), S(m+2) . . . S(2m) respectively connects to voltages VEE 1 , VEE 2  . . . VEEm, respectively controlling capacitors C 1 , C 2  . . . Cm to connect/disconnect to voltages VEE 1 , VEE 2  . . . VEEm. 
         [0049]    Additionally, the first terminal of capacitor C 1  is connected to two electronic switches Sn(m), Sn(m−1), electronic switches Sn(m), Sn(m−1) respectively connect to voltages VGG 1  and VGG 2 , separately controlling capacitor C 2  to connect/disconnect to voltages VGG 1  and VGG 2 . The first terminal of capacitor C 1  is connected to switch Sp; electronic switch Sp is connected to the output terminal VPx, controlling capacitor C 1  to output VPx. 
         [0050]    The second terminal of capacitor Cm is connected to electronic switches Sp(m) and Sp(m−1); electronic switches Sp(m+1), Sp(m) respectively connect to voltages VHH 1  and VHH 2 , separately controlling capacitor Cm to connect/disconnect to voltages VHH 1  and VHH 2 . One terminal of electronic switch Sn is connected to the output terminal VNx, and the other terminal is connected to the second terminal of Cm, controlling capacitor Cm to output VNx. 
         [0051]    As illustrated in  FIG. 9 , when VCC 1 =VCC 2 = . . . =VCCm=VDD, VEE 1 =VEE 2 = . . . =VEEm=VSS, VGG 1 =VSS, VGG 2 =VDD, VHH 1 =VDD, and VHH 2 =VSS, there are four operating modes in the circuit structure: VPx=mVDD and VNx=−mVDD, or VPx=mVDD and VNx=−(m−1)VDD, or VPx=(m+1)VDD and VNx=−mVDD, or VPx=(m+1)VDD and VNx=−(m−1)VDD. 
         [0052]    When simultaneously charging capacitors C 1 , C 2  to Cm, electronic switches S 1 , S 2  to S(2m) are conductive, S(2m+1), S(2m+2) to S(3m−1) are non-conductive, electronic switches Sp, Sn, Sp(m), Sp(m+1), Sn(m−1) and Sn(m) are non-conductive, with voltage VDD respectively charging capacitors C 1 , C 2  to Cm, forming voltage potentials VDD across the two terminals of capacitors C 1 , C 2  to Cm. 
         [0053]    When simultaneously charging capacitors C 1 , C 2  to Cm, when a pathway is opened, the electronic switches of the other pathways are disconnected; thus, voltage VPx=(m+1)VDD can be obtained through the path from voltage VDD through electronic switch Sp(m+1), capacitors Cm to C 1 , output terminal VPx, and output capacitors C(m+1) to VSS. High positive voltage VPx=mVDD can be obtained through the path from voltage VSS going through electronic switch Sp(m), capacitors Cm to C 1 , output terminal VPx, and output capacitors C(m+1) to VSS. High negative voltage VNx=−mVDD can be obtained through the path from voltage VSS through electronic switch Sn(m), capacitors C 1 , C 2  to Cm, output terminal VNx, and output capacitors C(m+2) to VSS. High negative voltage VNx=−(m−1)VDD can be obtained through the pathway from voltage VDD going through electronic switch Sn(m−1), capacitors C 1 , C 2  to Cm, output terminal VNx, and output capacitors C(m+2) to VSS. 
         [0054]    When m=−1, disconnecting electronic switch Sn(m−1) and the connection for connecting voltage VDD to the capacitor(s), and electronic switch Sp(m) and the connection for connecting voltage VSS to the capacitor(s), the embodiment for a charge pump structure for sharing one coupling capacitor can be accomplished, realizing 2 times and −1 time output boost. 
         [0055]    By the embodiments of the present invention, by connecting multiple charge pump stages, multiple output combinations of positive and negative voltages can be outputted, where the charge pump of each stage shares a capacitor set capable of charging and discharging operations. In one embodiment of the present invention, a prior stage charge pump output voltage can be the next stage input voltage of the charge pump. 
         [0056]    Two stage, column-connected charge pumps are described below. For ease of description, the above described charge pump sharing 1 capacitor and generating 2 times positive voltage and −1 time negative voltage is the stage 1 charge pump; its output voltage is the input voltage of the second stage charge pump, and is delivered to the second stage charge pump. The second stage charge pump, through the shared (m−1) capacitors C 2 , C 3  to Cm, generates VPx and VNx high voltage output. 
         [0057]      FIG. 10  illustrates the structure of a second stage charge pump sharing two coupling capacitors. At this time, the charge pump includes 9 types of operation modes, which can be selected by numeric logic for a specific operating mode to output 9 different types of positive and negative high voltage. 
         [0058]    As illustrated in  FIG. 11 , through numeric logic to control the time sequence for controlling the electronic switches of the charge pumps, the following can be generated: VPx=6VDD and VNx=−5VDD, VPx=6VDD and VNx=−4VDD, VPx=6VDD and VNx=−3VDD, VPx=5VDD and VNx=−5VDD, VPx=5VDD and VNx=−4VDD, VPx=5VDD and VNx=−3VDD, VPx=4VDD and VNx=−5VDD, VPx=4VDD and VNx=−4VDD, and VPx=4VDD, and VNx=−3VDD etc. There are 9 different types of positive and negative high voltage output conditions. 
         [0059]    When positive and negative high voltage outputs are 6 times and −5 times, the time sequence for controlling the electronic switches of the charge pump is illustrated by  FIG. 12 . In the process of charging and discharging, electronic switches Sp 4 , Sp 5 , Sn 3  and Sn 4  are in the disconnected state. 
         [0060]    During time t 1 , electronic switches S 21 , S 22 , S 23 , and S 24  are conductive, and electronic switches S 23 , Sp, Sp 6 , Sn, and Sn 5  are not conductive; the C 2 A terminal of capacitor C 2  through electronic switch S 2  connects with voltage Vp 2 , and the C 2 B terminal through electronic switch S 23  connects with zero voltage VSS; through the path from voltage VP 2  through coupling capacitor C 2  to zero voltage VSS, VP 2  charges capacitor C 2  and forms the voltage potential VP 2  across the two terminals of capacitor C 2 . At the same time, the C 3 A terminal of capacitor C 3  through electronic switch S 22  and connects with voltage Vp 2 , and the C 3 B terminal through electronic switch S 24  and connects with zero voltage VSS; through the path from voltage VP 2  through coupling capacitor C 3  to zero voltage VSS, VP 2  charges capacitor C 3 , and forms the voltage potential VP 2  across the two terminals of capacitor C 3 . 
         [0061]    During time t 2 , electronic switches S 21 , S 22 , S 23 , S 24 , Sn and Sn 5  are disconnected, and electronic switches S 25 , Sp, and Sp 6  are conductive; the C 3 B terminal of capacitor C 3  through electronic switch Sp 6  connects with voltage Vp 2 , and the C 3 A terminal through electronic switch S 25  connects with the C 2 B terminal of capacitor C 2 , and the C 2 A terminal of capacitor C 2  through electronic switch Sp, and connects to output terminal VPx; through the path from voltage VP 2  through electronic switch Sp 6 , capacitor C 3 , electronic switch S 25 , capacitor C 2 , electronic switch Sp, output terminal VPx, and output capacitor C 7  to zero voltage VSS, the output voltage at output terminal VPx is the input voltage VP 2  plus the voltage VP 2  stored in capacitor C 2  during t 1  and voltage VP 2  stored in capacitor C 3  to realize the 6 times VDD positive high voltage boost. 
         [0062]    During time t 3 , the operating conditions of the electronic switches are the same as during time t 1 ; through the path from voltage VP 2  through capacitor C 2  to zero voltage VSS, VP 2  charges capacitor C 2  and forms the voltage potential VP 2  across the two terminals of capacitor C 2 . At the same time, the C 3 A terminal of capacitor C 3  through electronic switch S 22  connects with voltage Vp 2 , and the C 3 B terminal through electronic switch S 24  connects with zero voltage VSS; through the path from voltage VP 2  through coupling capacitor C 3  to zero voltage VSS, VP 2  charges capacitor C 3  and forms the voltage potential VP 2  across the two terminals of capacitor C 3 . 
         [0063]    During time t 4 , electronic switches S 21 , S 22 , S 23 , S 24 , Sp and Sp 6  are disconnected, and electronic switches S 25 , Sn, and Sn 5  are conductive; the C 2 A terminal of capacitor C 2  through electronic switch Sn 5  connects to the output terminal VN 1  of the first stage charge pump, and the C 2 B terminal through electronic switch S 25  connects to the C 3 A terminal of capacitor C 3 , and the C 3 B terminal of capacitor C 3  through electronic switch Sn connects to output terminal VNx; through the path from input voltage VN 1  through electronic switch Sn 5 , capacitor C 2 , electronic switch S 25 , capacitor C 3 , electronic switch Sn, output terminal VNx, and output capacitor C 5  to zero voltage VSS, the output voltage at output terminal VNx is the input voltage VN 1  minus the voltage VP 2  stored in capacitor C 2  during time t 3  and voltage VP 2  stored in capacitor C 3  to realize the −5 times VDD negative high voltage boost. If the power consumption of the electronic switches and capacitors are not considered, after repeatedly charging and discharging, high positive ouput voltage VPx=VP 2 +VP 2 +VP 2 =6VDD, and negative high output voltage VNx=VN 1 −VP 2 −VP 2 =−5VDD can be obtained. 
         [0064]    When positive and negative high voltage outputs are 6 times and −4 times, the time sequence for controlling the electronic switches of the charge pump is illustrated by  FIG. 13 . In the process of charging and discharging, electronic switches Sp 4 , Sp 5 , Sn 3  and Sn 5  are in the disconnected state. 
         [0065]    During time t 1 , electronic switches S 21 , S 22 , S 23 , and S 24  are conductive, and electronic switches S 25 , Sp, Sp 6 , Sn, and Sn 4  are not conductive; the C 2 A terminal of capacitor C 2  through electronic switch S 21  connects with voltage Vp 2 , and the C 2 B terminal through electronic switch S 23  connects with zero voltage VSS; through the path from voltage VP 2  through capacitor C 2  to zero voltage VSS, VP 2  charges capacitor C 2  and forms the voltage potential VP 2  across the two terminals of capacitor C 2 . At the same time, the C 3 A terminal of capacitor C 3  through electronic switch S 22  connects with voltage Vp 2 , and the C 3 B terminal through electronic switch S 24  connects with zero voltage VSS; through the path where voltage VP 2  through coupling capacitor C 3  to zero voltage VSS, VP 2  charges capacitor C 3  and forms the voltage potential VP 2  across the two terminals of capacitor C 3 . 
         [0066]    During time t 2 , electronic switches S 21 , S 22 , S 23 , S 24 , Sn and Sn 4  are disconnected, and electronic switches S 25 , Sp, and Sp 6 , are conductive; the C 3 B terminal of capacitor C 3  through electronic switch Sp 6  connects with voltage Vp 2 , and the C 3 A terminal through electronic switch S 25  connects with the C 2 B terminal of capacitor C 2 , and the C 2 A terminal of capacitor C 2  through electronic switch Sp connects to output terminal VPx; through the path from voltage VP 2  through electronic switch Sp 6 , capacitor C 3 , electronic switch S 25 , capacitor C 2 , electronic switch Sp, output terminal VPx, and output capacitor C 7  to zero voltage VSS, the output voltage at output terminal VPx is the input voltage VP 2  plus the voltage VP 2  stored in capacitor C 2  during time t 1  and voltage VP 2  stored in capacitor C 3  to realize the 6 times VDD positive high voltage boost. 
         [0067]    During time t 3 , the operating conditions of the electronic switches are the same as during time t 1 ; through the path from voltage VP 2  through capacitor C 2  to zero voltage VSS, VP 2  charges capacitor C 2  and forms the voltage potential VP 2  across the two terminals of capacitor C 2 . At the same time, through the path from voltage VP 2  through capacitor C 3  to zero voltage VSS, VP 2  charges capacitor C 3  and forms the voltage potential VP 2  across the two terminals of capacitor C 3 . 
         [0068]    During time t 4 , electronic switches S 21 , S 22 , S 23 , S 24 , Sp and Sp 6  are disconnected, and electronic switches S 25 , Sn, and Sn 4  are conductive; the C 2 A terminal of capacitor C 2  through electronic switch Sn 4  connects to the zero voltage potential VSS, and the C 2 B terminal through electronic switch S 25  connects to the C 3 A terminal of capacitor C 3 , and the C 3 B terminal of capacitor C 3  through electronic switch Sn connects to output terminal VNx; through the path from zero voltage VSS through electronic switch Sn 4 , capacitor C 2 , electronic switch S 25 , capacitor C 3 , electronic switch Sn, output terminal VNx, and output capacitor C 5  to zero voltage VSS, the output voltage at output terminal VNx is the zero voltage VSS minus the voltage VP 2  stored in capacitor C 2  during time t 3  and voltage VP 2  stored in capacitor C 3  to realize the −4 times VDD negative high voltage boost. If the power consumption of the electronic switches and capacitors are not considered, after repeatedly charging and discharging, high positive ouput voltage VPx=VP 2 +VP 2 +VP 2 =6VDD, and negative high output voltage VNx=VSS−VP 2 −VP 2 =−4VDD can be obtained. 
         [0069]    When positive and negative high voltage outputs are 6 times and −3 times, the time sequence for controlling the electronic switches of the second stage charge pump is illustrated by  FIG. 14 . In the process of charging and discharging, electronic switches Sp 4 , Sp 5 , Sn 4  and Sn 5  are in the disconnected state. 
         [0070]    When positive and negative high voltage outputs are 6 times and −3 times, the time sequence for controlling the electronic switches of the second stage charge pump is illustrated by  FIG. 14 . In the process of charging and discharging, electronic switches Sp 4 , Sp 5 , Sn 4  and Sn 5  are in the disconnected state. 
         [0071]    During time t 1 , electronic switches S 21 , S 22 , S 23 , and S 24  are conductive, and electronic switches S 25 , Sp, Sp 6 , Sn, and Sn 3  are not conductive; the C 2 A terminal of capacitor C 2  through electronic switch S 21  connects with voltage Vp 2 , and the C 2 B terminal through electronic switch S 23  connects with zero voltage VSS; through the path from voltage VP 2  through capacitor C 2  to zero voltage VSS, VP 2  charges capacitor C 2  and forms the voltage potential VP 2  across the two terminals of capacitor C 2 . At the same time, the C 3 A terminal of capacitor C 3  through electronic switch S 22  connects with voltage Vp 2 , and the C 3 B terminal through electronic switch S 24  connects with zero voltage VSS; through the path from voltage VP 2  through coupling capacitor C 3  to zero voltage VSS, VP 2  charges capacitor C 3  and forms the voltage potential VP 2  across the two terminals of capacitor C 3 . 
         [0072]    During time t 2 , electronic switches S 21 , S 22 , S 23 , S 24 , Sn and Sn 3  are disconnected, and electronic switches S 25 , Sp, and Sp 6 , are conductive; the C 3 B terminal of capacitor C 3  through electronic switch Sp 6  connects with voltage Vp 2 , and the C 3 A terminal through electronic switch S 25  connects with the C 2 B terminal of capacitor C 2 , and the C 2 A terminal of capacitor C 2  through electronic switch Sp connects to output terminal VPx; through the path from voltage VP 2  through electronic switch Sp 6 , capacitor C 3 , electronic switch S 25 , capacitor C 2 , electronic switch Sp, output terminal VPx, and output capacitor C 7  to zero voltage VSS, the output voltage at output terminal VPx is voltage VP 2  plus the voltage VP 2  stored in capacitor C 2  during time t 1  and voltage VP 2  stored in capacitor C 3  to realize the 6 times VDD positive high voltage boost. 
         [0073]    During time t 3 , the operating conditions of the electronic switches are the same as during time t 1 ; through the path from voltage VP 2  through capacitor C 2  to zero voltage VSS, VP 2  charges capacitor C 2  and forms the voltage potential VP 2  across the two terminals of capacitor C 2 . At the same time, the C 3 A terminal of capacitor C 3  connects to VP 2 , and the C 3 B terminal connects to zero voltage VSS; through the path from voltage VP 2  through capacitor C 3  to zero voltage VSS, VP 2  charges capacitor C 3  and forms the voltage potential VP 2  across the two terminals of capacitor C 3 . 
         [0074]    During time t 4 , electronic switches S 21 , S 22 , S 23 , S 24 , Sp and Sp 6  are disconnected, and electronic switches S 25 , Sn, and Sn 3  are conductive; the C 2 A terminal of capacitor C 2  through electronic switch Sn 3  connects to the input voltage VDD, and the C 2 B terminal through electronic switch S 25  connects to the C 3 A terminal of capacitor C 3 , and the C 3 B terminal of capacitor C 3  through electronic switch Sn connects to output terminal VNx; through the path from voltage VDD through electronic switch Sn 3 , capacitor C 2 , electronic switch S 25 , capacitor C 3 , electronic switch Sn, output terminal VNx, and output capacitor C 5  to zero voltage VSS, the output voltage at output terminal VNx is voltage VDD minus the voltage VP 2  stored in capacitor C 2  during time t 3  and voltage VP 2  stored in capacitor C 3  to realize the −3 times VDD negative high voltage boost. If the power consumption of the electronic switches and capacitors are not considered, after repeatedly charging and discharging, high positive ouput voltage VPx=VP 2 +VP 2 +VP 2 =6VDD, and negative high output voltage VNx=VDD−VP 2 −VP 2 =−3VDD can be obtained. 
         [0075]    When positive and negative high voltage outputs are 5 times and −5 times, the time sequence for controlling the electronic switches of the charge pump is illustrated in  FIG. 15 . In the process of charging and discharging, electronic switches Sp 4 , Sp 6 , Sn 3  and Sn 4  are in the disconnected state. 
         [0076]    During time t 1 , electronic switches S 21 , S 22 , S 23 , and S 24  are conductive, and electronic switches S 25 , Sp, Sp 5 , Sn, and Sn 5  are not conductive; the C 2 A terminal of capacitor C 2  through electronic switch S 21  connects with voltage Vp 2 , and the C 2 B terminal through electronic switch S 23  connects with zero voltage VSS; through the path from voltage VP 2  through capacitor C 2  to zero voltage VSS, VP 2  charges capacitor C 2  and forms the voltage potential VP 2  across the two terminals of capacitor C 2 . At the same time, the C 3 A terminal of capacitor C 3  through electronic switch S 22  connects with voltage Vp 2 , and the C 3 B terminal through electronic switch S 24  connects with zero voltage VSS; through the path from voltage VP 2  through coupling capacitor C 3  to zero voltage VSS, VP 2  charges capacitor C 3  and forms the voltage potential VP 2  across the two terminals of capacitor C 3 . 
         [0077]    During time t 2 , electronic switches S 21 , S 22 , S 23 , S 24 , Sn and Sn 5  are disconnected, and electronic switches S 25 , Sp, and Sp 5 , are conductive; the C 3 B terminal of capacitor C 3  through electronic switch Sp 5  connects with voltage VDD, and the C 3 A terminal through electronic switch S 25  connects with the C 2 B terminal of capacitor C 2 , and the C 2 A terminal of capacitor C 2  through electronic switch Sp connects to output terminal VPx; through the path from voltage VDD through electronic switch Sp 5 , capacitor C 3 , electronic switch S 25 , capacitor C 2 , electronic switch Sp, output terminal VPx, and output capacitor C 7  to zero voltage VSS, the output voltage at output terminal VPx is input voltage VDD plus the voltage VP 2  stored in capacitor C 2  and voltage VP 2  stored in capacitor C 3  during time t 1 , to realize the 5 times VDD positive high voltage boost. 
         [0078]    During time t 3 , the operating conditions of the electronic switches are the same as during time t 1 ; through the path from voltage VP 2  through capacitor C 2  to zero voltage VSS, VP 2  charges capacitor C 2  and forms the voltage potential VP 2  across the two terminals of capacitor C 2 . At the same time, the C 3 A terminal of capacitor C 3  connects to VP 2 , and the C 3 B terminal connects to zero voltage VSS; through the path from voltage VP 2  through capacitor C 3  to zero voltage VSS, VP 2  charges capacitor C 3  and forms the voltage potential VP 2  across the two terminals of capacitor C 3 . 
         [0079]    During time t 4 , electronic switches S 21 , S 22 , S 23 , S 24 , Sp and Sp 5  are disconnected, and electronic switches S 25 , Sn, and Sn 5  are conductive; the C 2 A terminal of capacitor C 2  connects to the output voltage VN 1  at the output terminal of the first stage charge pump, and the C 2 B terminal through electronic switch S 25  connects to the C 3 A terminal of capacitor C 3 , and the C 3 B terminal of capacitor C 3  through electronic switch Sn connects to output terminal VNx; through the path from voltage VN 1  through electronic switch Sn 5 , capacitor C 2 , electronic switch S 25 , capacitor C 3 , electronic switch Sn, output terminal VNx, and output capacitor C 5  to zero voltage VSS, the output voltage at output terminal VNx is voltage VN 1  minus the voltage VP 2  stored in capacitor C 2  and voltage VP 2  stored in capacitor C 3  during time t 3  to realize the −5 times VDD negative high voltage boost. If the power consumption of the electronic switches and capacitors are not considered, after repeatedly charging and discharging, high positive ouput voltage VPx=VDD+VP 2 +VP 2 =5VDD, and negative high output voltage VNx=VN 1 −VP 2 −VP 2 =−5VDD can be obtained. 
         [0080]    When positive and negative high voltage outputs are 5 times and −4 times, the time sequence for controlling the electronic switches of the second stage charge pump is illustrated in  FIG. 16 . In the process of charging and discharging, electronic switches Sp 4 , Sp 6 , Sn 3  and Sn 5  are in the disconnected state. 
         [0081]    During time t 1 , electronic switches S 21 , S 22 , S 23 , and S 24  are conductive, and electronic switches S 25 , Sp, Sp 5 , Sn, and Sn 5  are not conductive; the C 2 A terminal of capacitor C 2  through electronic switch S 21  connects with voltage Vp 2 , and the C 2 B terminal through electronic switch S 23  connects with zero voltage VSS; through the path from voltage VP 2  through capacitor C 2  to zero voltage VSS, VP 2  charges capacitor C 2  and forms the voltage potential VP 2  across the two terminals of capacitor C 2 . At the same time, the C 3 A terminal of capacitor C 3  through electronic switch S 22  connects with voltage Vp 2 , and the C 3 B terminal through electronic switch S 24  connects with zero voltage VSS; through the path from voltage VP 2  through capacitor C 3  to zero voltage VSS, VP 2  charges capacitor C 3  and forms the voltage potential VP 2  across the two terminals of capacitor C 3 . 
         [0082]    During time t 2 , electronic switches S 21 , S 22 , S 23 , S 24 , Sn and Sn 4  are disconnected, and electronic switches S 25 , Sp, and Sp 5 , are conductive; the C 3 B terminal of capacitor C 3  through electronic switch Sp 5  connects with voltage VDD, the C 3 A terminal through electronic switch S 25  connects with the C 2 B terminal of capacitor C 2 , and the C 2 A terminal of capacitor C 2  connects to output terminal VPx; through the path from voltage VDD through electronic switch Sp 5 , capacitor C 3 , electronic switch S 25 , capacitor C 2 , electronic switch Sp, output terminal VPx, and output capacitor C 7  to zero voltage VSS, the output voltage at output terminal VPx is voltage VDD plus the voltage VP 2  stored in capacitor C 2  and voltage VP 2  stored in capacitor C 3  during time t 1  to realize the 5 times VDD positive high voltage boost. 
         [0083]    During time t 3 , the operating conditions of the electronic switches are the same as during time t 1 ; through the path from voltage VP 2  through capacitor C 2  to zero voltage VSS, VP 2  charges capacitor C 2  and forms the voltage potential VP 2  across the two terminals of capacitor C 2 . At the same time, the C 3 A terminal of capacitor C 3  connects to VP 2 , and the C 3 B terminal connects to zero voltage VSS; through the path from voltage VP 2  through capacitor C 3  to zero voltage VSS, VP 2  charges capacitor C 3  and forms the voltage potential VP 2  across the two terminals of capacitor C 3 . 
         [0084]    During time t 4 , electronic switches S 21 , S 22 , S 23 , S 24 , Sp and Sp 5  are disconnected, and electronic switches S 25 , Sn, and Sn 4  are conductive; the C 2 A terminal of capacitor C 2  connects through electronic switch S 21  to zero voltage VSS, the C 2 B terminal through electronic switch S 25  connects to the C 3 A terminal of capacitor C 3 , and the C 3 B terminal of capacitor C 3  through electronic switch Sn connects to output terminal VNx; through the path from zero voltage VSS through electronic switch Sn 4 , capacitor C 2 , electronic switch S 25 , capacitor C 3 , electronic switch Sn, output terminal VNx, and output capacitor C 5  to zero voltage VSS, the output voltage at output terminal VNx is voltage VSS minus the voltage VP 2  stored in capacitor C 2  and voltage VP 2  stored in capacitor C 3  during time t 3  to realize the −4 times VDD negative high voltage boost. If the power consumption of the electronic switches and capacitors are not considered, after repeatedly charging and discharging, high positive ouput voltage VPx=VDD+VP 2 +VP 2 =5VDD, and negative high output voltage VNx=VSS−VP 2 −VP 2 =−4VDD can be obtained. 
         [0085]    When positive and negative high voltage outputs are 5 times and −3 times, the time sequence for controlling the electronic switches of the charge pump is illustrated in  FIG. 17 . In the process of charging and discharging, electronic switches Sp 4 , Sp 6 , Sn 4  and Sn 5  are in the disconnected state. 
         [0086]    During t 1 , electronic switches S 21 , S 22 , S 23 , and S 24  are conductive, and electronic switches S 25 , Sp, Sp 5 , Sn, and Sn 3  are not conductive; the C 2 A terminal of capacitor C 2  through electronic switch S 21  connects with voltage VP 2 , and the C 2 B terminal through electronic switch S 23  connects with zero voltage VSS; through the path from voltage VP 2  through capacitor C 2  to zero voltage VSS, VP 2  charges capacitor C 2  and forms the voltage potential VP 2  across the two terminals of capacitor C 2 . At the same time, the C 3 A terminal of capacitor C 3  through electronic switch S 22  connects with voltage VP 2 , and the C 3 B terminal through electronic switch S 24  connects with zero voltage VSS; through the path from voltage VP 2  through capacitor C 3  to zero voltage VSS, VP 2  charges capacitor C 3  and forms the voltage potential VP 2  across the two terminals of capacitor C 3 . 
         [0087]    During time t 2 , electronic switches S 21 , S 22 , S 23 , S 24 , Sn and Sn 3  are disconnected, and electronic switches S 25 , Sp, and Sp 5  are conductive; the C 3 B terminal of capacitor C 3  through electronic switch Sp 5  connects with voltage VDD, the C 3 A terminal through electronic switch S 25  connects with the C 2 B terminal of capacitor C 2 , and the C 2 A terminal of capacitor C 2  connects through electronic switch Sp to output terminal VPx; through the path from voltage VDD through electronic switch Sp 5 , capacitor C 3 , electronic switch S 25 , capacitor C 2 , electronic switch Sp, output terminal VPx, and output capacitor C 7  to zero voltage VSS, the output voltage at output terminal VPx is voltage VDD plus the voltage VP 2  stored in capacitor C 2  and voltage VP 2  stored in capacitor C 3  during time t 1  to realize the 5 times VDD positive high voltage boost. 
         [0088]    During time t 3 , the operating conditions of the electronic switches are the same as during time t 1 ; through the path from voltage VP 2  through capacitor C 2  to zero voltage VSS, VP 2  charges capacitor C 2  and forms the voltage potential VP 2  across the two terminals of capacitor C 2 . At the same time, the C 3 A terminal of capacitor C 3  connects to VP 2 , and the C 3 B terminal connects to zero voltage VSS; through the path from voltage VP 2  through capacitor C 3  to zero voltage VSS, VP 2  charges capacitor C 3  and forms the voltage potential VP 2  across the two terminals of capacitor C 3 . 
         [0089]    During time t 4 , electronic switches S 21 , S 22 , S 23 , S 24 , Sp and Sp 5  are disconnected, and electronic switches S 25 , Sn, and Sn 3  are conductive; the C 2 B terminal of capacitor C 2  connects through electronic switch S 25  to the C 3 A terminal of capacitor C 3 , and the C 3 B terminal of capacitor C 3  connects to output terminal VNx; through the path from voltage VDD through electronic switch Sn 3 , capacitor C 2 , electronic switch S 25 , capacitor C 3 , electronic switch Sn, output terminal VNx, and output capacitor C 5  to zero voltage VSS, the output voltage at output terminal VNx is voltage VDD minus the voltage VP 2  stored in capacitor C 2  and voltage VP 2  stored in capacitor C 3  during time t 3  to realize the −3 times VDD negative high voltage boost. If the power consumption of the electronic switches and capacitors is not considered, after repeatedly charging and discharging, high positive ouput voltage VPx=VDD+VP 2 +VP 2 =5VDD, and negative high output voltage VNx=VDD−VP 2 −VP 2 =−3VDD can be obtained. 
         [0090]    When positive and negative high voltage outputs are 4 times and −5 times, the time sequence for controlling the electronic switches of the second stage charge pump is illustrated in  FIG. 18 . In the process of charging and discharging, electronic switches Sp 5 , Sp 6 , Sn 3  and Sn 4  are in the disconnected state. 
         [0091]    During time t 1 , electronic switches S 21 , S 22 , S 23 , and S 24  are conductive, and electronic switches S 25 , Sp, Sp 4 , Sn, and Sn 5  are not conductive; the C 2 A terminal of capacitor C 2  through electronic switch S 21  connects with voltage VP 2 , and the C 2 B terminal through electronic switch S 23  connects with zero voltage VSS; through the path from voltage VP 2  through capacitor C 2  to zero voltage VSS, VP 2  charges capacitor C 2  and forms the voltage potential VP 2  across the two terminals of capacitor C 2 . At the same time, the C 3 A terminal of capacitor C 3  connects to voltage VP 2 , and the C 3 B terminal through electronic switch S 24  connects with zero voltage VSS; through the path from voltage VP 2  through capacitor C 3  to zero voltage VSS, VP 2  charges capacitor C 3  and forms the voltage potential VP 2  across the two terminals of capacitor C 3 . 
         [0092]    During time t 2 , electronic switches S 21 , S 22 , S 23 , S 24 , Sn and Sn 5  are disconnected, and electronic switches S 25 , Sp, and Sp 4  are conductive; the C 3 B terminal of capacitor C 3  through electronic switch Sp 4  connects with zero voltage VSS, the C 3 A terminal through electronic switch S 25  connects with the C 2 B terminal of capacitor C 2 , and the C 2 A terminal of capacitor C 2  connects through electronic switch Sp to output terminal VPx; through the path from voltage VSS through electronic switch Sp 4 , capacitor C 3 , electronic switch S 25 , capacitor C 2 , electronic switch Sp, output terminal VPx, and output capacitor C 7  to zero voltage VSS, the output voltage at output terminal VPx is zero voltage VSS plus the voltage VP 2  stored in capacitor C 2  and voltage VP 2  stored in capacitor C 3  during time t 1  to realize the 4 times VDD positive high voltage boost. 
         [0093]    During time t 3 , the operating conditions of the electronic switches are the same as during time t 1 ; through the path from voltage VP 2  through capacitor C 2  to zero voltage VSS, VP 2  charges capacitor C 2  and forms the voltage potential VP 2  across the two terminals of capacitor C 2 . At the same time, the C 3 A terminal of capacitor C 3  connects to VP 2 , and the C 3 B terminal connects to zero voltage VSS; through the path from voltage VP 2  through capacitor C 3  to zero voltage VSS, VP 2  charges capacitor C 3  and forms the voltage potential VP 2  across the two terminals of capacitor C 3 . 
         [0094]    During time t 4 , electronic switches S 21 , S 22 , S 23 , S 24 , Sp and Sp 4  are disconnected, and electronic switches S 25 , Sn, and Sn 5  are conductive; the C 2 A terminal of capacitor C 2  connects through electronic switch Sn 5  to the output voltage VN 1  at the output terminal of the first stage charge pump, the C 2 B terminal through electronic switch S 25  connects to the C 3 A terminal of capacitor C 3 , and the C 3 B terminal of capacitor C 3  through electronic switch Sn connects to output terminal VNx; through the path from voltage VN 1  through electronic switch Sn 5 , capacitor C 2 , electronic switch S 25 , capacitor C 3 , electronic switch Sn, output terminal VNx, and negative high output voltage VNx=VN 1 −VP 2 −VP 2 =−5VDD can be obtained negative high output voltage VNx=VN 1 −VP 2 −VP 2 =−5VDD can be obtained. 
         [0095]    When positive and negative high voltage outputs are 4 times and −4 times, the time sequence for controlling the electronic switches of the charge pump is illustrated in  FIG. 19 . In the process of charging and discharging, negative high output voltage VNx=VN 1 −VP 2 −VP 2 =−5VDD can be obtained. 
         [0096]    When positive and negative high voltage outputs are 4 times and −4 times, the time sequence for controlling the electronic switches of the charge pump is illustrated in  FIG. 19 . In the process of charging and discharging, electronic switches Sp 5 , Sp 6 , Sn 3  and Sn 5  are in the disconnected state. 
         [0097]    During time t 1 , electronic switches S 21 , S 22 , S 23 , and S 24  are conductive, and electronic switches S 25 , Sp, Sp 4 , Sn, and Sn 4  are not conductive; the C 2 A terminal of capacitor C 2  connects to voltage VP 2 , and the C 2 B terminal connects to zero voltage VSS; through the path from voltage VP 2  through capacitor C 2  to zero voltage VSS, VP 2  charges capacitor C 2  and forms the voltage potential VP 2  across the two terminals of capacitor C 2 . At the same time, the C 3 A terminal of capacitor C 3  through electronic switch S 21  connects to voltage VP 2 , and the C 3 B terminal through electronic switch S 23  connects with zero voltage VSS; through the path from voltage VP 2  through capacitor C 3  to zero voltage VSS, VP 2  charges capacitor C 3  and forms the voltage potential VP 2  across the two terminals of capacitor C 3 . 
         [0098]    During time t 2 , electronic switches S 21 , S 22 , S 23 , S 24 , Sn and Sn 4  are disconnected, and electronic switches S 25 , Sp, and Sp 4  are conductive; the C 3 B terminal of capacitor C 3  through electronic switch Sp 4  connects with zero voltage VSS, the C 3 A terminal through electronic switch S 25  connects with the C 2 B terminal of capacitor C 2 , and the C 2 A terminal of capacitor C 2  connects through electronic switch Sp to output terminal VPx; through the path from voltage VSS through electronic switch Sp 4 , capacitor C 3 , electronic switch S 25 , capacitor C 2 , electronic switch Sp, output terminal VPx, and output capacitor C 7  to zero voltage VSS, the output voltage at output terminal VPx is zero voltage VSS plus the voltage VP 2  stored in capacitor C 2  and voltage VP 2  stored in capacitor C 3  during time t 1  to realize the 4 times VDD positive high voltage boost. 
         [0099]    During time t 3 , the operating conditions of the electronic switches are the same as during time t 1 ; through the path from voltage VP 2  through capacitor C 2  to zero voltage VSS, VP 2  charges capacitor C 2  and forms the voltage potential VP 2  across the two terminals of capacitor C 2 . At the same time, the C 3 A terminal of capacitor C 3  connects to VP 2 , and the C 3 B terminal connects to zero voltage VSS; through the path from voltage VP 2  through capacitor C 3  to zero voltage VSS, VP 2  charges capacitor C 3  and forms the voltage potential VP 2  across the two terminals of capacitor C 3 . 
         [0100]    During time t 4 , electronic switches S 21 , S 22 , S 23 , S 24 , Sp and Sp 4  are disconnected, and electronic switches S 25 , Sn, and Sn 4  are conductive; the C 2 A terminal of capacitor C 2  connects through electronic switch Sn 4  to zero voltage VSS, the C 2 B terminal through electronic switch S 25  connects to the C 3 A terminal of capacitor C 3 , and the C 3 B terminal of capacitor C 3  through electronic switch Sn connects to output terminal VNx; through the path from zero voltage VSS through electronic switch Sn 4 , capacitor C 2 , electronic switch S 25 , capacitor C 3 , electronic switch Sn, output terminal VNx, and output capacitor C 5  to zero voltage VSS, the output voltage at output terminal VNx is voltage VSS minus the voltage VP 2  stored in capacitor C 2  and voltage VP 2  stored in capacitor C 3  during time t 3  to realize the −4 times VDD negative high voltage boost. If the power consumption of the electronic switches and capacitors are not considered, after repeatedly charging and discharging, high positive ouput voltage VPx=VSS+VP 2 +VP 2 =4VDD, and negative high output voltage VNx=VSS−VP 2 −VP 2 =−4VDD can be obtained. 
         [0101]    When positive and negative high voltage outputs are 4 times and −3 times, the time sequence for controlling the electronic switches of the second stage charge pump is illustrated in  FIG. 14 . In the process of charging and discharging, electronic switches Sp 5 , Sp 6 , Sn 4  and Sn 5  are in the disconnected state. 
         [0102]    During time t 1 , electronic switches S 21 , S 22 , S 23 , and S 24  are conductive, and electronic switches S 25 , Sp, Sp 4 , Sn, and Sn 3  are not conductive; the C 2 A terminal of capacitor C 2  connects to voltage VP 2 , and the C 2 B terminal connects to zero voltage VSS; through the path from voltage VP 2  through capacitor C 2  to zero voltage VSS, VP 2  charges capacitor C 2  and forms the voltage potential VP 2  across the two terminals of capacitor C 2 . At the same time, the C 3 A terminal of capacitor C 3  through electronic switch S 21  connects to voltage VP 2 , and the C 3 B terminal through electronic switch S 23  connects with zero voltage VSS; through the path from voltage VP 2  through capacitor C 3  to zero voltage VSS, VP 2  charges capacitor C 3  and forms the voltage potential VP 2  across the two terminals of capacitor C 3 . 
         [0103]    During time t 2 , electronic switches S 21 , S 22 , S 23 , S 24 , Sn and Sn 3  are disconnected, and electronic switches S 25 , Sp, and Sp 4  are conductive; the C 3 B terminal of capacitor C 3  through electronic switch Sp 4  connects with zero voltage VSS, the C 3 A terminal through electronic switch S 25  connects with the C 2 B terminal of capacitor C 2 , and the C 2 A terminal of capacitor C 2  connects through electronic switch Sp to output terminal VPx; through the path from voltage VSS through electronic switch Sp 4 , capacitor C 3 , electronic switch S 25 , capacitor C 2 , electronic switch Sp, output terminal VPx, and output capacitor C 7  to zero voltage VSS, the output voltage at output terminal VPx is zero voltage VSS plus the voltage VP 2  stored in capacitor C 2  and voltage VP 2  stored in capacitor C 3  during time t 1  to realize the 4 times VDD positive high voltage boost. 
         [0104]    During time t 3 , the operating conditions of the electronic switches are the same as during time t 1 ; through the path from voltage VP 2  through capacitor C 2  to zero voltage VSS, VP 2  charges capacitor C 2  and forms the voltage potential VP 2  across the two terminals of capacitor C 2 . At the same time, the C 3 A terminal of capacitor C 3  connects to VP 2 , and the C 3 B terminal connects to zero voltage VSS; through the path from voltage VP 2  through capacitor C 3  to zero voltage VSS, VP 2  charges capacitor C 3  and forms the voltage potential VP 2  across the two terminals of capacitor C 3 . 
         [0105]    During time t 4 , electronic switches S 21 , S 22 , S 23 , S 24 , Sp and Sp 4  are disconnected, and electronic switches S 25 , Sn, and Sn 3  are conductive; the C 2 A terminal of capacitor C 2  through electronic switch Sn 3  connects to the input voltage VDD, the C 2 B terminal through electronic switch S 25  connects to the C 3 A terminal of capacitor C 3 , and the C 3 B terminal of capacitor C 3  through electronic switch Sn connects to output terminal VNx; through the path from voltage VDD through electronic switch Sn 3 , capacitor C 2 , electronic switch S 25 , capacitor C 3 , electronic switch Sn, output terminal VNx, and output capacitor C 5  to zero voltage VSS, the output voltage at output terminal VNx is voltage VDD minus the voltage VP 2  stored in capacitor C 2  and voltage VP 2  stored in capacitor C 3  during time t 3  to realize the −3 times VDD negative high voltage boost. If the power consumption of the electronic switches and capacitors are not considered, after repeatedly charging and discharging, high positive ouput voltage VPx=VSS+VP 2 +VP 2 =4VDD, and negative high output voltage VNx=VDD−VP 2 −VP 2 =−3VDD can be obtained. 
         [0106]      FIG. 21  illustrates a structure for a second stage charge pump sharing 3 coupling capacitors, which can generate the positive and negative high voltages VPx=5VDD (or 6VDD, or 7VDD, or 8VDD) and VNx=−4VDD (or −5VDD, or −6VDD, or −7VDD). By controlling through the non-overlapping time sequences,the electronic switches are operated to be conducting and non-conducting to charge and discharge the capacitors. The charge pump has 16 types of operating conditions, each one of which can be controlled and selected by numeric logic to provide  16  types of positive and negative output voltages. 
         [0107]    In charging capacitors C 2 , C 3  and C 4  during the same time, electronic switches S 21 , S 21 , S 23 , S 24 , S 25  and S 26  are conducting, electronic switches S 27 , S 28 , Sp 5 , Sp 6 , Sp 7 , Sp 8 , Sn 4 , Sn 5 , Sn 6 , and Sn 7  are disconnected. VP 2  charges capacitors C 2 , C 3 , and C 4  and forms VP 2  voltage potential across the capacitors. 
         [0108]    When capacitors C 2 , C 3  and C 4  are simultaneously pumping, when a pathway is opened (connected), the electronic switches of the other pathways are disconnected; voltage VPx=5VDD can be obtained through the pathway from input voltage VN 1  through electronic switch Sp 5 , capacitor C 4 , capacitor C 3 , capacitor C 2 , output terminal VPx, and output capacitors C 6  to VSS; voltage VPx=6VDD can be obtained through the pathway from zero voltage VSS through electronic switch Sp 6 , capacitor C 4 , capacitor C 3 , capacitor C 2 , output terminal VPx, and output capacitors C 6  to VSS; voltage VPx=7VDD can be obtained through the pathway from voltage VDD through electronic switch Sp 7 , capacitor C 4 , capacitor C 3 , capacitor C 2 , output terminal VPx, and output capacitors C 6  to VSS; voltage VPx=8VDD can be obtained through the pathway from voltage VP 2  through electronic switch Sp 8 , capacitor C 4 , capacitor C 3 , capacitor C 2 , output terminal VPx, and output capacitors C 6  to VSS; voltage VPx=−4VDD can be obtained through the pathway from voltage VP 2  through electronic switch Sn 4 , capacitor C 2 , capacitor C 3 , capacitor C 4 , output terminal VNx, and output capacitors C 5  to VSS; voltage VPx=−5VDD can be obtained through the pathway from voltage VP 2  through electronic switch Sn 5 , capacitor C 2 , capacitor C 3 , capacitor C 4 , output terminal VNx, and output capacitors C 5  to VSS; voltage VPx=−6VDD can be obtained through the pathway from voltage VSS through electronic switch Sn 6 , capacitor C 2 , capacitor C 3 , capacitor C 4 , output terminal VNx, and output capacitors C 5  to VSS; and voltage VPx=−7VDD can be obtained through the pathway from voltage VN 1  through electronic switch Sn 7 , capacitor C 2 , capacitor C 3 , capacitor C 4 , output terminal VNx, and output capacitors C 5  to VSS. 
         [0109]    As illustrated by  FIG. 22 , in a second stage charge pump, in sharing (m−1) capacitors C 2  and C 3  to Cm, the positive and negative high voltages VPx and VNx are generated. By controlling through the non-overlapping time sequences, the electronic switches are operated to be conducting and non-conducting, and capacitors C 2  and C 3  to Cm are charged and discharged to realize the charge pump charging and discharging. The charge pump includes positive voltage charge pump(s) and negative voltage charge pump(s), and in this charging and discharging process, they share the same coupling capacitor(s). 
         [0110]    C 1  and C 2  to Cm totaling (m−1) capacitors are serially connected under the control of the electronic switches S(2m−1) and S(2m) . . . S(3m−4), where m is a whole number larger or equal to 2. The first terminals of capacitors C 2  and C 3  . . . Cm respectively connect to electronic switches S 1  and S 2  . . . Sm−1; electronic switches S 1  and S 2  . . . Sm−1 respectively connect to VCC 2  and VCC 3  . . . VCCm, and respectively connect to capacitors C 2  and C 3  . . . Cm to connect/disconnect to voltages VCC 2  and VCC 3  . . . VCCm. 
         [0111]    The second terminals of capacitors C 2  and C 3  . . . Cm respectively connect to electronic switches Sm and Sm+1 . . . S(2m−2), and respectively connect to VEE 2  and VEE 3  . . . VEEm, and respectively connect to capacitors C 2  and C 3  . . . Cm to connect/disconnect to voltages VEE 2  and VEE 3  . . . VEEm. 
         [0112]    Additionally, the first terminal of capacitor C 2  connects to 4 electronic switches: Sn(2m−1), Sn(2m−2), Sn(2m−3), and Sn(2m−4); electronic switches Sn(2m−1), Sn(2m−2), Sn(2m−3), and Sn(2m−4), respectively, connect to VGG 1 , VGG 2 , VGG 3 , and VGG 4  to control whether capacitor C 2  is to connect to voltages VGG 1 , VGG 2 , VGG 3 , and VGG 4 . The first terminal of capacitor C 2  connects to switch Sp, and the electronic switch connects to output terminal VPx to control whether capacitor C 2  is to connect to output terminal VPx. 
         [0113]    The first terminal of capacitor Cm, respectively, connects to electronic switches Sp(2m), Sp(2m−1), Sp(2m−2), and Sp(2m−3); electronic switches Sp(2m), Sp(2m−1), Sp(2m−2), and Sp(2m−3), respectively, connect to VHH 1 , VHH 2 , VHH 3 , and VHH 4  to control whether capacitor Cm is to connect to voltages VHH 1 , VHH 2 , VHH 3 , and VHH 4 . The first terminal of electronic switch Sn connects to output terminal VNx, and the other terminal connects to the second terminal of capacitor Cm to control whether capacitor Cm is to connect to output terminal VNx. 
         [0114]    The charge pump has  16  operating modes, which can be selected by numeric logic for a specific operating mode to output  16  different types of positive and negative high voltage. When disregarding electronic switch S(2m−4) that connects to the first terminal of capacitor C 2  and the control for connecting capacitor C 2  to input voltage VGG 4 , and disregarding electronic switch Sp(2m−3) that connects to the second terminal of capacitor Cm and the control for connecting capacitor Cm to input voltage VHH 4 , the charge pump has 9 operating modes. 
         [0115]    When VCC 2 =VCC 3 = . . . =VCCm=VP 2 , VEE 2 =VEE 3 = . . . =VEEm=VSS, VGG 1 =VN 1 , VGG 2 =VSS, VGG 3 =VDD, VGG 4 =VP 2 , VHH 1 =VP 2 , VHH 2 =VDD, VHH 3 =VSS, and VHH 4 =VN 1 , the following positive and negative high voltage output can be obtained: VPx=(2m−3)VDD, or VPx=(2m−2)VDD, or VPx=(2m−1)VDD, or VPx=(2m)VDD; VNx=−(2m−4)VDD, or VNx=−(2m−3)VDD, or VNx=−(2m−2)VDD, or VNx=−(2m−1)VDD, where the structure of the charge pump is as illustrated in  FIG. 23 . 
         [0116]    When simultaneously charging capacitors C 2 , C 3  to Cm, electronic switches S 1 , S 2  to S(2m−2) are conductive, S(2m−1), S(2m) to S(3m−4) are non-conductive, electronic switches Sp, Sn, Sp(2m−3), Sp(2m−2), Sp(2m−1), Sp(2m), Sn(2m−4), Sn(2m−3), Sn(2m−2) and Sn(2m−1) are non-conductive, and input voltage VP 2  is respectively charging C 2 , C 3  to Cm, forming voltage potentials VP 2  across the two terminals of capacitors. 
         [0117]    When capacitors C 2 , C 3  to Cm are simultaneously pumping, when a pathway is opened (connected), the electronic switches of the other pathways are disconnected; voltage VPx=(2m−3)VDD can be obtained through the pathway from voltage VN 1  at the negative output terminal of first stage charge pump through electronic switch Sp(2m−3), capacitor Cm to capacitor C 2 , electronic switch Sp, output terminal VPx, and output capacitor C(m+3) to VSS; voltage VPx=(2m−2)VDD can be obtained through the pathway from voltage VSS through electronic switch Sp(2m−2), capacitor Cm to capacitor C 2 , electronic switch Sp, output terminal VPx, and output capacitor C(m+3) to VSS; voltage VPx=(2m−1)VDD can be obtained through the pathway from voltage VDD through electronic switch Sp(2m−1), capacitor Cm to capacitor C 2 , electronic switch Sp, output terminal VPx, and output capacitor C(m+3) to VSS; voltage VPx=(2m)VDD can be obtained through the pathway from voltage VP 2  through electronic switch Sp(2m), capacitor Cm to capacitor C 2 , electronic switch Sp, output terminal VPx, and output capacitor C(m+3) to VSS; negative high voltage VNx=−Sn(2m−4)VDD can be obtained through the pathway from voltage VP 2  through electronic switch Sn(2m−4), capacitor C 2 , capacitor C 3  to capacitor Cm, electronic switch Sn, output terminal VNx, and output capacitor C(m+4) to VSS; negative high voltage VNx=−Sn(2m−3)VDD can be obtained through the pathway from voltage VDD through electronic switch Sn(2m−3), capacitor C 2 , capacitor C 3  to capacitor Cm, electronic switch Sn, output terminal VNx, and output capacitor C(m+4) to VSS; negative high voltage VNx=−Sn(2m−2)VDD can be obtained through the pathway from voltage VSS through electronic switch Sn(2m−2), capacitor C 2 , capacitor C 3  to capacitor Cm, electronic switch Sn, output terminal VNx, and output capacitor C(m+4) to VSS; and negative high voltage VNx=−Sn(2m−1)VDD can be obtained through the pathway from voltage VN 1  at the negative output terminal of the first stage charge pump through electronic switch Sn(2m−1), capacitor C 2 , capacitor C 3  to capacitor Cm, electronic switch Sn, output terminal VNx, and output capacitor C(m+4) to VSS. 
         [0118]    In the embodiments of the present invention, the capacitors can be inside the chip or outside of the chip, and the switches can be MOS transistor or likewise on-off components. 
         [0119]    In the embodiments of the present invention, coupling capacitors are shared during the processes of the positive and negative charge pumps charging and discharging, and operate at alternating intervals through sequence-control. As a result, both positive and negative voltage output with adjustable voltage boost can be simultaneously achieved where the boost rate can be selected through numeric logic. Through the embodiments of the present invention, the die size and the manufacturing cost of the charge pump can be greatly reduced, and the charge pump has a design that is simple and easy to produce. 
         [0120]    While the present invention has been described with reference to certain preferred embodiments, it is to be understood that the present invention is not limited to such specific embodiments. Rather, it is the inventor&#39;s contention that the invention be understood and construed in its broadest meaning as reflected by the following claims. Thus, these claims are to be understood as incorporating not only the preferred embodiments described herein but also all those other and further alterations and modifications as would be apparent to those of ordinary skilled in the art.