Abstract:
In a multicore type error correction processing system which can simultaneously cope with a plurality of error correction methods and a plurality of code lengths, an interconnect part  11  has a barrel shifter which extends across a plurality of error correction processing parts  12   a - 12   c.  An error correction process can be selectively performed by collectively using a group of the plurality of the error correction processing parts  12   a - 12   c  or by individually using each of individual error correction processing parts  12   a - 12   c  in response to interconnection configuration information. With this structure, the plurality of the error correction processing parts  12   a - 12   c  are collectively used if computation resources are insufficient and an idling error correction processing part is assigned to another error correction process if computation resources are excessive.

Description:
TECHNICAL FIELD 
       [0001]    The present invention relates to a field of error correction process such as turbo decoding or LDPC decoding in wireless communication, and more particularly to a system having a parallel architecture using a multicore processor for aiming at a high throughput. 
       BACKGROUND ART 
       [0002]    A high throughput and a high resistance to error have been required for recent wireless communication systems. In order to meet such demands, various techniques including error correction processes such as turbo coding, LDPC (Low Density Parity Check) coding, and convolutional coding have been used in a variety of wireless communication systems, such as LTE (Long Term Evolution) and WiMax. Those error correction processes, particularly decoding algorithms, require a large amount of bit processing and many repetitional processes and, as a result, need a great amount of calculations. Therefore, various proposals have been presented so far with regard to dedicated hardware engines suitable for decoding algorithms. Use of those dedicated hardware engines can provide a high throughput and high capability of error correction as required. 
         [0003]    However, each of those dedicated hardware engines deals with a single decoding method in order to achieve high performance requirements. Herein, it is assumed that those dedicated hardware engines which would be a key technology to a next-generation wireless communication system are used in a software radio apparatus required for a multi-standard wireless system. In this event, such engines suitable for all of error correction algorithms used in a required communication method should be installed individually. In such a case, the scale of the circuit becomes large as an increase of the number of those dedicated hardware engines and results in an influence on the scale of the entire system. Furthermore, multiple types of dedicated hardware engines should be developed on all such occasions or on demand. This causes an increase of development cost. 
         [0004]    With regard to those problems, there has been proposed a programmable engine that deals with multiple types of error correction algorithms Form the viewpoint of achieving a high throughput as required, proposals have been made about the architecture of the programmable engine formed by a single processor having a high operating frequency (see Non-Patent Document 1) or a plurality of processors arranged in parallel (see Non-Patent Document 2). The latter method using a plurality of processors would be effective in a wireless communication system in terms of a reduction of the electrical power consumption. 
         [0005]    As shown in  FIG. 6 , a programmable engine disclosed in Non-Patent Document 2 includes a plurality of memory banks  50   a,    50   b , and  50   c,  a plurality of error correction processing parts  52   a,    52   b,  and  52   c,  and an interconnect part  51 . The memory banks  50   a - 50   c  are connected to the error correction processing parts  52   a - 52   c  via the interconnect part  51 . Multiple sets of data can simultaneously be read from or written in each of the memory banks  50   a - 50   c.  The engine having the above configuration as disclosed in Non-Patent Document 2 operates as follows. 
         [0006]    It is assumed that each of the memory banks and the error correction processing parts is equal to N in number and that M words of data can simultaneously be read from or written in one of the memory banks. For the sake of brevity,  FIG. 6  shows an example where N=3 and M=32. Input data for an error correction process are stored in the memory banks. A plurality of data that can simultaneously be accessed in one memory bank are referred to as a data row. 
         [0007]    First, an operation for LDPC decoding will be described. Data rows are read from the memory banks  50   a - 50   c.  The read data rows are subjected to a predetermined amount of shift in barrel shifters  51   a,    51   b,  and  51   c  which are connected to the memory banks  50   a,    50   b,  and  50   c , respectively. The amount of shift differs depending upon the type of LDPC coding. The shifted data rows are inputted to the error correction processing parts  52   a,    52   b,  and  52   c.  When the data rows are inputted to the error correction processing parts  52   a - 52   c,  a program for LDPC decoding is executed in each of the error correction processing parts  52   a - 52   c,  so that one repetition cycle of the LDPC decoding process is performed. The resultant computation results are outputted to the interconnect part  51 . In the interconnect part  51 , the inputted data rows are subjected to a reverse shift operation that is reverse to the shift operation performed at the time of input, so that the order of the data rows is recovered to the original one. The data rows in the original order are written back to the memory banks. This sequence is repeated a predetermined number of times. Thus, LDPC decoding for one code is conducted. 
         [0008]    Next, an operation for turbo decoding will be described. In the case of the turbo decoding, the interconnect part  51  is operated in a different manner between an even number one of repetitive times and an odd number one of the repetitive times. When the repetition times are even, data rows inputted from the memory banks  50   a - 50   c  are inputted to the error correction processing parts  52   a - 52   c  without any change of the order of the data. When the repetition times are odd, data rows inputted from the memory banks  50   a - 50   c  are subjected to interleaving processing by a cross bar  51   d  of the interconnect part  51  and are inputted to the error correction processing parts  52   a - 52   c  after the order of the data has been changed. When the data rows are thus inputted, a program for turbo decoding is executed in the error correction process, so that a turbo decoding process is performed. The resultant computation results are subjected to de-interleaving depending upon whether the repetition times are even or odd like in the case of the input of the data rows from the memory banks and then are written back to the memory banks. This sequence is repeated a predetermined number of times. Thus, turbo decoding is conducted. 
         [0009]    As described above, Non-Patent Document 2 can perform typical error correction processes, including LDPC decoding and turbo decoding, by the use of the same architecture. 
         [0010]    As shown in  FIG. 6 , however, it should be pointed out that the architecture of Non-Patent Document 2 has limited or fixed connections between memory banks and the error correction processing parts. When multiple types of error correction methods are to be processed, only one type of error correction methods can be processed during a single operation in Non-Patent Document 2. This shows that a plurality of error correction processes should be successively or sequentially performed. Accordingly, even if a single error correction method is processed in connection with a certain code length an error correction process cannot be performed simultaneously on different code lengths from the certain code length. A next-generation wireless communication system, particularly a base station, requires decoding processes for a plurality of users. Furthermore, it would be desirable to effectively process a plurality of error correction methods and a plurality of code lengths. In most of the existing wireless communication systems, different error correction processes are performed for different communication channels. Thus, it would be desirable also to process a plurality of error correction methods and a plurality of different code lengths at one time. 
       CITATION LIST 
     Non-Patent Literature 
       [0011]    Non-Patent Document 1: “FlexiChaP: A reconfigurable ASIP for convolutional, turbo, and LDPC code decoding,” M. Alles, T. Vogt, and N. Wehn, in Proc. Int. SyMposiuM on Turbo Coding (TURBO CODING &#39;08), 2008, pp. 13-18. 
         [0012]    Non-Patent Document 2: “A UNIFIED INSTRUCTION SET PROGRAMMABLE ARCHITECTURE FOR MULTISTANDARD ADVANCED FORWARD ERROR CORRECTION,” Frederik Naessens, et al., IEEE Sips08, 2008, pp. 31-36. 
       SUMMARY OF INVENTION 
     Technical Problem 
       [0013]    Problems to be solved by the present invention are that computation resources cannot be used effectively for a plurality of error correction methods or a plurality of code lengths in a multicore type error correction processing apparatus and that only one type of error correction process can be performed in one operation. This is because of limited or fixed connections between the memory banks and the error correction processing parts as in Non-Patent Document 2 shown in  FIG. 6 . When processes that meet various performance requirements are to be performed with this configuration, it is difficult to perform a plurality of error correction processes simultaneously or to provide computation resources suitable for the performance requirements. Particularly, a barrel shifter can only perform a single shift operation with a single amount of shift at one time in an LDPC decoding process. Therefore, in a case where a plurality of error correction processes are to be performed, or an LDPC decoding process is to be performed on different code lengths, each error correction process or each code length should be sequentially performed in Non-Patent Document 2. 
         [0014]    The present invention has been made in order to solve the above problems. It is, therefore, an object of the present invention to provide a multicore type error correction processing system that can achieve efficient computation and data transfer to respective processing portions to meet various performance requirements and that can simultaneously perform error correction processes with a plurality of error correction methods and a plurality of code lengths. 
       Solution to Problem 
       [0015]    According to an aspect of the present invention, there is provided a multicore type error correction processing system comprising a plurality of data storage parts, a data row conversion part for receiving data from the plurality of data storages and converting an order of data in a data row, and a plurality of error correction processing parts for receiving data from the data row conversion part and performing a predetermined error correction process based upon the parameter data stored in the external parameter storage part, wherein the data row conversion part performs a data row conversion in response to control information by using a barrel shifter operation which includes a rotation operation based upon a shift process and which collectively indicates a group of the plurality of the error correction processing parts to be outputted or which individually indicates the plurality of the error correction processing parts. 
         [0016]    According to another aspect of the present invention, there is provided a multicore type error correction processing apparatus characterized by comprising: a plurality of memory banks; an interconnect part including a barrel shifter operable to receive data from the plurality of memory banks and to shift a data row of the data for converting an order of the data; an external interface operable to receive a control parameter from an exterior of the external interface; an external parameter holding part operable to store data received from the external interface; and a plurality of error correction processing parts operable to receive data from the interconnect part and perform a predetermined error correction process based upon a parameter stored in the external parameter holding part, wherein the error correction processing parts each include an error correction computation part and an error correction processing control part operable to control the error correction computation part so as to perform the error correction process based upon the parameter stored in the external parameter holding part, and the interconnect part performs a data row conversion using a barrel shifter operation which includes a rotation operation based upon a shift process and which collectively indicates a group of the plurality of error correction processing parts to be outputted or which individually indicates each of the plurality of error correction processing parts to be outputted. 
         [0017]    In the multicore type error correction processing apparatus according to the above aspect, control parameters regarding the error correction processing parts are inputted to the interconnect part from the exterior of the apparatus or within the apparatus. The apparatus operates such that a barrel shifter in the interconnect part is configured to have one or more types of groups by those data. The object of the present invention can be achieved by using the above configuration and connecting a plurality of memory banks to a plurality of error correction processing parts via an interconnect part. 
         [0018]    According to still another aspect of the present invention, there is provided a processing method comprising: receiving a data row and control information concerned with the data row; performing a barrel shifter operation of the data row in response to the control information to collectively indicate a group of a plurality of output devices or to individually indicate each of the output devices; and selectively processing the data row subjected to the barrel shifter operation by the group of the output devices or by the individual output devices. 
         [0019]    The processing method may be used in a multicore type error correction processing system which includes: a plurality of data storages, a data row conversion part which receives data from the plurality of the data storages and which converts an order of data in the data row, an external input register which receives the control information, and a plurality of error correction processing parts as the output devices, the plurality of the error correction processing parts receiving data from the data row conversion part and performing a predetermined error correction process based upon the control information, wherein; the performing the barrel shifter operation comprising: receiving the control information; and carrying out, in response to the control information, the barrel shifter operation which includes a rotation operation based upon a shift process and which collectively indicates the group of the error correction processing parts as the output devices or which individually indicates each of the error correction processing parts as the output devices. 
       Advantageous Effects of Invention 
       [0020]    With the above configuration, the following advantageous effects can be attained. 
         [0021]    The present invention is advantageous in that a plurality of data rows having different configurations can simultaneously be processed. This is because an interconnect part is structured so that a plurality of species or groups are formed in response to a control parameter inputted from error correction processing parts or the exterior of the system. 
     
    
     
       BRIEF DESCRIPTION OF DRAWING 
         [0022]      FIG. 1  is a block diagram showing an arrangement of an error correction processing apparatus according to a first embodiment of the present invention. 
           [0023]      FIG. 2  is a block diagram showing an arrangement of an error correction processing apparatus according to a second embodiment of the present invention. 
           [0024]      FIG. 3  is a block diagram showing an arrangement of an error correction processing apparatus according to a third embodiment of the present invention. 
           [0025]      FIG. 4  is a block diagram showing an arrangement of an error correction processing apparatus according to a fourth embodiment of the present invention. 
           [0026]      FIG. 5  is a diagram showing a specific example of group configuration of a barrel shifter for carrying out the present invention. 
           [0027]      FIG. 6  is a block diagram showing an arrangement of an error correction processing apparatus related to the present invention. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0028]    Next, some embodiments of the present invention will be described in detail with reference to the drawings. 
         [0029]    The following embodiments are applicable to a multicore type error correction processing system or error correction processing apparatus. The following embodiments describe a case in which the present invention is applied to a multicore type error correction processing apparatus. 
       First Exemplary Embodiment 
       [0030]    Referring to  FIG. 1 , a multicore type error correction processing apparatus according to a first embodiment of the present invention includes a plurality of memory banks  10   a,    10   b,  and  10   c,  an interconnect part  11 , and a plurality of error correction processing parts  12   a,    12   b,  and  12   c.  For the sake of brevity,  FIG. 1  shows an example of three memory banks and three error correction processing parts. As a matter of course, the present invention is not limited to three memory banks and three error correction processing parts. This holds true for other embodiments described later. 
         [0031]    The memory banks  10   a - 10   c  are used to store data to be processed (referred to as input data), data being computed, and the results. The interconnect part (data row conversion means or part)  11  includes a cross bar  11   a  primarily used in turbo decoding process, a barrel shifter  11   b  used in an LDPC decoding process, and an interconnect control part  11   c  operable to control the group configuration, operation, and the like. The interconnect part  11  is connected to the error correction processing parts as well as the memory banks The error correction processing parts  12   a - 12   c  each perform an error correction process. The error correction processing parts  12   a - 12   c  are connected to the interconnect part  11 . The error correction processing parts  12   a,    12   b , and  12   c  respectively include error correction computation parts  13   a,    13   b,  and  13   c  operable to actually process received input data and error correction processing control parts  15   a,    15   b,  and  15   c  operable to control the error correction computation parts  13   a,    13   b,  and  13   c.  The error correction computation parts  13   a - 13   c  may be called processing elements (abbreviated to PE) while the processing control parts  15   a - 15   c  may be abbreviated to Ctrl. The error correction processing control parts  15   a - 15   c  also serve to generate memory addresses for the memory banks  10   a ,  10   b,  and  10   c  and interconnect parameters required for the interconnect part  11 . The error correction processing parts  12   a,    12   b,  and  12   c  further include configuration data holding parts (external parameter storage means or registers)  14   a,    14   b,  and  14   c  operable to hold configuration parameters indicative of how to group the error correction processing parts  12   a,    12   b,  and  12  and the interconnect part  11 . The configuration data holding registers  14   a,    14   b,  and  14   c  are abbreviated to CREG. In the illustrated example, the configuration parameters are received from an external IF (interface) (external input means)  16 . 
         [0032]    Those components operate as follows. 
         [0033]    The memory banks  10   a,    10   b,  and  10   c  are controlled by the error correction processing control parts  15   a,    15   b,  and  15   c.  The memory banks  10   a,    10   b,  and  10   c  receive addresses generated by the error correction processing control parts  15   a,    15   b,  and  15   c  and output data stored in those addresses to the interconnect part  11 . Furthermore, the memory banks  10   a,    10   b , and  10   c  store data outputted from the interconnect part  11  into addresses generated by the error correction processing control parts  15   a,    15   b,  and  15   c.  M data can be accessed simultaneously in one memory bank by one address where M is an integer not less than 2. 
         [0034]    The error correction processing parts  12   a,    12   b,  and  12   c  each perform. an actual error correction process. The error correction processing control parts  15   a,    15   b,  and  15   c  included therein execute a program sequence corresponding to a predetermined decoding algorithm and issue control signals to the error correction computation parts  13   a,    13   b,  and  13   c,  the memory banks  10   a,    10   b,  and  10   c,  and the interconnect part  11 . Each error correction computation part  13   a - 13   c  that has received the control signal executes the predetermined decoding algorithm with use of a data row inputted from the memory bank  10   a,    10   b,  or  10   c.  The configuration data holding parts  14   a,    14   b,  and  14   c  are connected to the external IF  16  so as to receive error correction configuration data from an external module. 
         [0035]    The interconnect part  11  operates based upon group configuration information (data conversion configuration information or interconnect configuration information) obtained from the configuration data holding parts  14   a,    14   b,  and  14   c  together with interconnect parameters (data conversion control information or interconnect control information) obtained from the error correction processing control parts  15   a,    15   b,  and  15   c  in the error correction processing parts  12   a - 12   c.  The group configuration information and the interconnect parameters may be collectively referred to as control information. 
         [0036]    The interconnect control part  11   c  determines group configuration of the cross bar  1   a  and the barrel shifter  11   b  based upon the group configuration information. Furthermore, the interconnect control part  11   c  controls a connection change in the cross bar  11   a  and a shift process of the barrel shifter  11   b  based upon the interconnect parameters. This allows a data row conversion such as interleaving for turbo decoding or barrel shifting for LDPC decoding. 
         [0037]      FIG. 5  shows an arrangement of a barrel shifter  61  as an example of a group configuration method. As shown in  FIG. 5 , the barrel shifter  61  can be configured such that the three error correction processing parts  12   a,    12   b,  and  12   c  are regarded as one group (see the reference numeral  62  of  FIG. 5 ). In this case, the error correction processing apparatus of the present invention can deal with an error correction process of parallelism (specified by M×3). 
         [0038]    As another example, by changing the group configuration information, the barrel shifter  61  can be configured such that each of the error correction processing parts  12   a,    12   b,  and  12   c  is regarded as one group (see the reference numeral  63  of  FIG. 5 ). In this case, the error correction processing apparatus has three groups in total and can deal with three error correction processes of parallelism specified by M. The three error correction processes can be executed simultaneously. 
         [0039]    Furthermore, the barrel shifter  61  can be configured to have two groups, one of which includes the two error correction processing parts  12   a  and  12   b  and the other of which includes the error correction processing part  12   c  (see the reference numeral  64  of  FIG. 5 ). In this case, the error correction processing apparatus can deal with an error correction process of parallelism specified by M×2 and an error correction process of parallelism specified by M. Both of the error correction processes can be executed simultaneously. 
         [0040]    An overall operation of the multicore type error correction processing apparatus according to the first exemplary embodiment will be described in detail with reference to  FIG. 1 . The overall operation differs depending upon the group configuration of the interconnect part  11 . Therefore, the overall operation will be described in connection with each of the aforementioned three cases described in the operation of the interconnect part  11 . 
         [0041]    Now, description would be made about the first case, i.e., the case where the barrel shifter in the interconnect part  11  is configured to have one group (capable of dealing with an error correction process having parallelism: M×3) by the group configuration information. Herein, let an LDPC decoding process be performed. The data to be subjected to LDPC decoding is assumed to have the code length equal to  768 . In other words, it is assumed that  768  input data for an error correction process are stored in total in the memory banks  10   a,    10   b , and  10   c.  It is presumed that the number of data of 1 data row that can be stored in each of the memory banks  10   a,    10   b,  and  10   c  is defined such that M=32. Specifically, since the number of the memory banks is three, the number of data readable and writable when all of the memory banks are simultaneously accessed is calculated by M×3=96. In this case, the error correction processing apparatus can perform one type of error correction process at one time. The operation of the error correction processing apparatus will be described below. 
         [0042]    First, the external IF  16  supplies, to the configuration data holding parts  14   a,    14   b,  and  14   c,  the group configuration information for the interconnect part  11  and information indicative of what error correction method is used for a process in the error correction processing parts  12   a ,  12   b,  and  12   c  (information corresponding to LDPC in this example). Then, based upon the obtained information, the error correction processing control parts  15   a,    15   b,  and  15   c  in the error correction processing parts  12   a,    12   b,  and  12   c  start to execute a program corresponding to an LDPC decoding process. When the program is executed, the error correction processing control parts  15   a,    15   b,  and  15   c  output a read address to the memory banks  10   a,    10   b,  and  10   c.    
         [0043]    Furthermore, the error correction processing control parts  15   a,    15   b,  and  15   c  output interconnect parameters to the interconnect part  11 . In the illustrated example, the interconnect parameters are sent to the interconnect control part  11   c  of the interconnect part  11 . The memory banks  10   a ,  10   b,  and  10   c  read a desired data row based upon the received address. The read data row is outputted to the interconnect part  11 . 
         [0044]    Under control of the interconnect control part,  11   c , the interconnect part  11  uses the barrel shifter  11   b  as a barrel shifter ( 62  of  FIG. 5 ) for 96-data on the basis of the inputted data row, the interconnect parameters, and the group configuration information in the configuration data holding parts  14   a,    14   b,  and  14   c.  At any rate, the interconnect part  11  performs a data row conversion under control of the interconnect control part  11   c.  After the data row conversion, the data rows are supplied to the error correction processing parts  12   a,    12   b,  and  12   c.  When the data rows are inputted to the error correction computation parts  13   a,    13   b,  and  13   c,  the error correction computation parts  13   a,    13   b,  and  13   c  perform an LDPC decoding process for one repetition time. The obtained results are inputted to the interconnect part  11  again. Based upon the data rows inputted as computation results and the interconnect parameters, the interconnect part  11  performs a barrel shifter process that is reverse to the operation performed at the time of input to the error correction processing parts  12   a - 12   c.  The data rows recovered into the original order by the interconnect part  11  are inputted to the memory banks  10   a,    10   b,  and  10   c  again. The data rows inputted as computation results to the memory banks  10   a,    10   b,  and  10   c  are stored into predetermined addresses by write addresses generated in the error correction processing control parts  15   a,    15   b,  and  15   c.    
         [0045]    An LDPC decoding process can be performed one repetition time by the above steps. This operation is repeated a predetermined number of times, so that desired LDPC decoding results can be obtained. 
         [0046]    Next, description would be made about the second case, i.e., the case where the barrel shifter  11   b  in the interconnect part  11  is configured to have three groups (each being capable of dealing with an error correction process of parallelism: M) by the group configuration information. It is assumed that an LDPC decoding process is performed for three codes. The code length of data to be subjected to LDPC decoding is assumed to be  768 . In other words, it is assumed that  768  input data for an error correction process are stored in each of the memory banks  10   a - 10   c.  It is assumed that the number of data of 1 data row that can be stored in each of the memory banks  10   a,    10   b,  and  10   c  is defined such that M=32. Specifically, the number of data readable and writable when one of the memory banks is accessed becomes equal to M=32. In this case, the error correction processing apparatus can perform three different error correction processes at one time. The operation of the error correction processing apparatus will be described below. 
         [0047]    First, the external IF  16  supplies, to the configuration data holding parts  14   a,    14   b,  and  14   c,  the group configuration information for the interconnect part  11  and information indicative of what error correction method is used for a process in the error correction processing parts  12   a ,  12   b,  and  12   c  (information corresponding to LDPC in this example). Then, based upon the obtained information, the error correction processing control parts  15   a,    15   b,  and  15   c  in the error correction processing parts  12   a,    12   b,  and  12   c  start to execute a program corresponding to an LDPC decoding process. When the program is executed, the error correction processing control parts  15   a,    15   b,  and  15   c  output a read address to the memory banks  10   a,    10   b,  and  10   c , respectively. Furthermore, the error correction processing control parts  15   a,    15   b,  and  15   c  output interconnect parameters to the interconnect part  11 . The memory banks  10   a,    10   b,  and  10   c  read a desired data row based upon the received address. The three read data rows are outputted to the interconnect part  11 . 
         [0048]    The interconnect part  11  changes the barrel shifter  11   b  into three barrel shifters ( 63  of  FIG. 5 ) for 32-data on the basis of the inputted data rows, the interconnect parameters, and the group configuration information in the configuration data holding parts  14   a,    14   b,  and  14   c,  and performs a data row conversion. After the data row conversion, the data rows are supplied to the error correction processing parts  12   a,    12   b,  and  12   c,  respectively. When the data rows are respectively inputted to the error correction computation parts  13   a,    13   b,  and  13   c,  the error correction computation parts  13   a,    13   b,  and  13   c  perform an LDPC decoding process for one repetition time. The obtained results are inputted to the interconnect part  11  again. Based upon the data rows inputted as computation results and the interconnect parameters, the interconnect part  11  performs a barrel shifter process that is reverse to the operation performed at the time of input to the error correction processing parts  12   a - 12   c  (i.e., a barrel shifter process for three barrel shifters for 32-data). The data rows recovered into the original order by the interconnect part  11  are inputted to the memory banks  10   a,    10   b,  and  10   c  again. The data rows inputted as computation results to the memory banks  10   a,    10   b,  and  10   c  are stored into predetermined addresses by write addresses generated in the error correction processing control parts  15   a,    15   b,  and  15   c.    
         [0049]    The LDPC decoding process can be performed one repetition time by the above steps. This operation is repeated a predetermined number of repetition times, so that desired LDPC decoding results for three codes can be obtained. 
         [0050]    Description would be made about the third case, i.e., the case where the barrel shifter  11   b  in the interconnect part  11  is configured to have two groups (one capable of dealing with an error correction process having parallelism of M×2 and one capable of dealing with an error correction process having parallelism of M) by the group configuration information. It is assumed that a turbo decoding process is to be performed for one code by the error correction processing parts  12   a  and  12   b  and that an LDPC decoding process is to be performed for one code by the error correction processing part  12   c.  The code length of data to be subjected to turbo decoding is assumed to be 512. The coding rate of turbo decoding is assumed to be 1/3. Specifically, the total code length of data to be subjected to turbo decoding is 1536. The code length of data to be subjected to LDPC decoding is assumed to be 768. In other words, it is assumed that 1536 input data for a turbo decoding process are stored in the memory banks  10   a  and  10   b.  It is assumed that 768 input data for an LDPC decoding process are stored in the memory bank  10   c.  It is assumed that the number of data of a single data row that can be stored in the memory banks  10   a,    10   b,  and  10   c  is defined such that M=32. Specifically, the number of data readable and writable when one of the memory banks is accessed is calculated by M=32. In this case, the error correction processing apparatus can perform two types of error correction processes on data used at one time. The operation of the error correction processing apparatus will be described below. 
         [0051]    First, the external IF  16  supplies, to the configuration data holding parts  14   a,    14   b,  and  14   c,  group configuration information for the interconnect part  11  and information indicative of what error correction method is used for a process in the error correction processing parts  12   a ,  12   b,  and  12   c  (information commanding the error correction processing parts  12   a  and  12   b  to conduct turbo decoding and the error correction processing part  12   c  to conduct LDPC decoding in this example). Then, based upon the obtained information, the error correction processing control parts  15   a,    15   b,  and  15   c  in the error correction processing parts  12   a,    12   b,  and  12   c  start to execute a program corresponding to a turbo decoding process or an LDPC decoding process. 
         [0052]    When the program is executed, the error correction processing control parts  15   a,    15   b,  and  15   c  output a read address to the memory banks  10   a,    10   b,  and  10   c,  respectively. Furthermore, the error correction processing control parts  15   a,    15   b,  and  15   c  output interconnect parameters to the interconnect part  11 . The memory banks  10   a,    10   b,  and  10   c  read a desired data row based upon the received address. The three read data rows are outputted to the interconnect part  11 . 
         [0053]    The interconnect part  11  changes the barrel shifter  11   b  into one 32-data barrel shifter ( 62  of  FIG. 5 ) based upon the inputted data rows, the interconnect parameters, and the group configuration information in the configuration data holding parts  14   a,    14   b,  and  14   c,  and changes the configuration of the cross bar  11   a  such that the cross bar  11   a  is connected only to the two error correction processing parts  12   a  and  12   b.  The interconnect part  11  performs a data row conversion on the inputted data rows with the changed configuration. Specifically, the interconnect part  11  performs an interleaving process on the input data rows from the memory banks  10   a  and  10   b  when the repetition times are odd, and outputs the input data rows from the memory banks  10   a  and  10   b  without any data row conversion when the repetition times are even. Furthermore, the interconnect part  11  performs a barrel shifter process on the input data from the memory bank  10   c.    
         [0054]    After the data row conversion, the data rows are inputted to the error correction processing parts  12   a,    12   b,  and  12   c,  respectively. When the data rows are respectively inputted to the error correction computation parts  13   a,    13   b,  and  13   c,  the error correction computation parts  13   a  and  13   b  perform one repetition cycle of a turbo decoding process whereas the error correction computation part  13   c  performs one repetition cycle of an LDPC decoding process. The obtained results are inputted to the interconnect part  11  again. Based upon the data rows inputted as computation results and the interconnect parameters, the interconnect part  11  performs a data row conversion. Specifically, the interconnect part  11  allows the data rows outputted from the error correction computation parts  13   a  and  13   b  to go through when the count of repeated cycles is odd, and performs a de-interleaving process on the data rows outputted from the error correction computation parts  13   a  and  13   b  when the count of repeated cycles is even. Furthermore, the interconnect part  11  performs, on the data row outputted from the error correction computation part  13   c,  a barrel shifter process that is reverse to the operation performed at the time of input to the error correction processing part (i.e., a barrel shifter process for one 32-data barrel shifter). The data rows recovered into the original order by the interconnect part  11  are inputted to the memory banks  10   a,    10   b,  and  10   c  again. The data rows inputted as computation results to the memory banks  10   a,    10   b,  and  10   c  are stored into predetermined addresses by write addresses generated in the error correction processing control parts  15   a,    15   b,  and  15   c.    
         [0055]    The turbo decoding process and the LDPC decoding process can be performed simultaneously with each other for the single repetition time. This operation is repeated a predetermined number of times, so that desired results of turbo decoding and LDPC decoding can be obtained. 
         [0056]    As described above, in the first exemplary embodiment, the numbers of the error correction processing parts and the memory banks are equal to three. This is for the sake of brevity. The numbers of the error correction processing parts and the memory banks are not limited to three. Furthermore, in the first exemplary embodiment, a turbo decoding process and an LDPC decoding process have been described. However, since the three error correction processing parts  12   a,    12   b,  and  12   c  can operate independently of each other, the error correction processing apparatus may process a combination of turbo decoding, LDPC decoding, and other error correction methods such as Viterbi decoding, or may process one method selected from among those methods. Any combination can be selected. 
         [0057]    At any rate, it should be noted that the barrel shifter  11 B performs a barrel shifter operation which includes a rotation operation based upon a shift process and which collectively indicates a group of the plurality of the error correction processing parts to be outputted or which individually indicates each of the plurality of the error correction processing parts in response to the control information. In this event, the rotation operation of the barrel shifter operation is implemented by successively shifting each data row within the barrel shifter  11   b  in a rotatable or cyclical manner. 
         [0058]    Next, advantageous effects of the first exemplary embodiment will be described below. 
         [0059]    In the multicore type error correction processing apparatus according to the first exemplary embodiment, the barrel shifter  11   b  in the interconnect part  11  is configured such that a plurality of error correction processing parts can form a variety of groups based upon the group configuration information stored in the configuration data holding parts  14   a,    14   b,  and  14   c  and the interconnect parameters obtained from the error correction processing control parts  15   a,    15   b , and  15   c.  Therefore, one or more types of error correction processes, such as LDPC decoding and turbo coding, can simultaneously be performed with parallelism corresponding to various performance requirements as described above. 
       Second Exemplary Embodiment 
       [0060]    Next, a multicore type error correction processing apparatus according to a second exemplary embodiment of the present invention will be described in detail with reference to the drawings. 
         [0061]    The second embodiment is a variation of the first exemplary embodiment. Differences between the second exemplary embodiment and the first exemplary embodiment are as follows: In the first exemplary embodiment, the interconnect control part  11   c  in the interconnect part  11  is supplied with input signals through two lines of the error correction processing control parts  15   a ,  15   b,  and  15   c  and the configuration data holding parts  14   a,    14   b,  and  14   c.  In the second exemplary embodiment, an interconnect control part  21   c  in an interconnect part  21  is supplied with input signals only through the configuration data holding parts  24 . 
         [0062]    Specifically, the multicore type error correction processing apparatus according to the second exemplary embodiment includes a plurality of memory banks  20   a,    20   b,  and  20   c,  a plurality of error correction processing parts  22   a,    22   b,  and  22   c,  and the interconnect part  21 , as illustrated in  FIG. 2 . The memory banks  20   a,    20   b,  and  20   c  are used to store data to be processed (referred to as input data), data being computed, and the results. The error correction processing parts  22   a,    22   b,  and  22   c  each perform an error correction process. The error correction processing parts  22   a,    22   b,  and  22   c  include error correction computation parts  23   a ,  23   b,  and  23   c  operable to actually process received input data, error correction processing control parts  25   a,    25   b,  and  25   c  operable to control the error correction computation parts  23   a,    23   b,  and  23   c  and to generate memory addresses for the memory banks  20   a,    20   b,  and  20   c  and interconnect parameters required for the interconnect part  21 . In addition, configuration data holding parts  24   a,    24   b,  and  24   c  are included in the error correction processing parts  22   a,    22   b,  and  22   c  so as to hold group configuration information which is received from an external IF  26 . The interconnect part  21  includes a cross bar  21   a  primarily used in turbo decoding, a barrel shifter  21   b  used in an LDPC decoding process, and the interconnect control part  21   c  operable to control the group configuration, operation, and the like. 
         [0063]    Those components operate as follows. 
         [0064]    The memory banks  20   a,    20   b,  and  20   c  store data to be processed or computed. This is the same as in the first exemplary embodiment. 
         [0065]    The error correction processing parts  22   a,    22   b,  and  22   c  perform an actual error correction process. This is also the same as in the first exemplary embodiment. 
         [0066]    The interconnect part  21  operates based upon group configuration information and interconnect parameters obtained from the configuration data holding parts  24   a,    24   b,  and  24   c . The interconnect control part  21   c  determines group configuration of the cross bar  21   a  and the barrel shifter  21   b  based upon the group configuration information. Furthermore, the interconnect control part  21   c  controls a connection change in the cross bar  21   a  and a shift process of the barrel shifter  21   b  based upon the interconnect parameters. This structure makes it possible to perform a data row conversion such as interleaving for turbo decoding and/or barrel shifting for LDPC decoding. 
         [0067]    An example of a group configuration method will be described with reference to the barrel shifter  61  illustrated in  FIG. 5  again. As shown in  FIG. 5 , the barrel shifter  61  can be configured such that the three error correction processing parts  22   a,    22   b,  and  22   c  are regarded as one group (see the reference numeral  62  of  FIG. 5 ). In this case, the error correction processing apparatus can deal with an error correction process of parallelism specified by M×3. As another example, by changing the group configuration information, the barrel shifter  21   b  can be configured such that each of the error correction processing parts  22   a,    22   b,  and  22   c  is regarded as one group (see the reference numeral  63  of  FIG. 5 ). In this case, the error correction processing apparatus has three groups in total and can deal with three error correction processes each having parallelism of M, which can be executed simultaneously with one another. Furthermore, the barrel shifter  21   b  can be configured to have two groups, one of which includes the two error correction processing parts  22   a  and  22   b  and the other of which includes the error correction processing part  22   c  (see the reference numeral  64  of  FIG. 5 ). In this case, the error correction processing apparatus can deal with an error correction process having parallelism of M×2 and an error correction process having parallelism of M, which can be executed simultaneously with one another. 
         [0068]    An overall operation of the multicore type error correction processing apparatus according to the second embodiment will be described in detail with reference to  FIG. 2 . The overall operation differs depending upon the group configuration of the interconnect part  21 . Therefore, the overall operation will be described in connection with each of the aforementioned three cases described in the operation of the interconnect part  21 . 
         [0069]    Description will be made about the first case, i.e., the case where the barrel shifter in the interconnect part  21  is configured to have one group (capable of dealing with an error correction process having parallelism of M×3) by the group configuration information. It is assumed that an LDPC decoding process is to be performed. The code length of data to be subjected to LDPC decoding is assumed to be 768. In other words, it is assumed that 768 input data for an error correction process are stored in total in the memory banks. It is assumed that each of the memory banks  20   a,    20   b,  and  20   c  can store data of a single data row defined by M=32 in number. Specifically, since the illustrated memory banks are equal in number to three, data simultaneously readable and writable are equal to M×3=96 in number. In this case, the error correction processing apparatus can perform one type of error correction process at one time. The operation of the error correction processing apparatus will be described below. 
         [0070]    First, the external IF  26  supplies, to the configuration data holding parts  24   a,    24   b,  and  24   c,  the group configuration information for the interconnect part  21 , the interconnect parameters, and the information indicative of what error correction method is used for a process in the error correction processing parts  22   a,    22   b,  and  22   c  (information corresponding to LDPC in this example). Then, based upon the obtained information, the error correction processing control parts  25   a,    25   b,  and  25   c  in the error correction processing parts  22   a,    22   b,  and  22   c  start to execute a program corresponding to an LDPC decoding process. When the program is executed, the error correction processing control parts  25   a,    25   b,  and  25   c  output a read address to the memory banks  20   a,    20   b,  and  20   c.  The memory banks  20   a,    20   b,  and  20   c  read a desired data row based upon the received address. The read data row is outputted to the interconnect part  21 . 
         [0071]    The interconnect part  21  uses the barrel shifter  21   b  as a barrel shifter ( 62  of  FIG. 5 ) for 96-data on the basis of the inputted data row, the group configuration information in the configuration data holding parts  24   a,    24   b,  and  24   c,  and the interconnect parameters, and performs a data row conversion. After the data row conversion, the data rows are supplied to the error correction processing parts  22   a,    22   b,  and  22   c.  When the data rows are given to the error correction computation parts  23   a,    23   b,  and  23   e,  the error correction computation parts  23   a ,  23   b,  and  23   e  perform an LDPC decoding process of one repetition time. The obtained results are inputted to the interconnect part  21  again. Based upon the data rows inputted as computation results and the interconnect parameters, the interconnect part  21  performs a barrel shifter process that is reverse to the operation performed at the time of input to the error correction processing parts  22   a - 22   c.  The data rows recovered into the original order by the interconnect part  21  are inputted to the memory banks  20   a,    20   b,  and  20   c  again. The data rows inputted as computation results to the memory banks  20   a,    20   b,  and  20   c  are stored into predetermined addresses by write addresses generated in the error correction processing control parts  25   a,    25   b,  and  25   c.    
         [0072]    Thus, the LDPC decoding process can be performed one repetition time by the above steps. This operation is repeated a predetermined number of times, so that desired LDPC decoding results can be obtained. 
         [0073]    Description will be made about the second case, i.e., the case where the barrel shifter  21   b  in the interconnect part  21  is configured to have three groups (each being capable of dealing with an error correction process having parallelism of M) by the group configuration information. Let the LDPC decoding process be performed for three codes. The code length of data to be subjected to LDPC decoding is assumed to be 768. In other words, it is assumed that 768 input data for an error correction process are stored in each of the memory banks. It is also assumed that data of the single data row stored in each of the memory banks  20   a,    20   b,  and  20   c  are equal in number to M=32. Specifically, the number of data readable and writable when one of the memory banks is accessed is defined by M=32. In this case, the error correction processing apparatus can perform three types of error correction processes at one time. The operation of the error correction processing apparatus will be described below. 
         [0074]    First, the external IF  26  supplies, to the configuration data holding parts  24   a,    24   b,  and  24   c,  the group configuration information for the interconnect part  21 , the interconnect parameters, and the information indicative of what error correction method is used for a process in the error correction processing parts  22   a,    22   b,  and  22   c  (information corresponding to LDPC in this example). Then, based upon the obtained information, the error correction processing control parts  25   a,    25   b,  and  25   c  in the error correction processing parts  22   a,    22   b,  and  22   c  start to execute a program corresponding to an LDPC decoding process. When the program is executed, the error correction processing control parts  25   a,    25   b,  and  25   c  output a read address to the memory banks  20   a,    20   b,  and  20   c,  respectively. The memory banks  20   a,    20   b,  and  20   c  read a desired data row based upon the received address. The three read data rows are outputted to the interconnect part  21 . 
         [0075]    The interconnect part  21  changes the barrel shifter  21   b  into three barrel shifters ( 63  of  FIG. 5 ) for 32-data on the basis of the inputted data rows, the group configuration information in the configuration data holding parts  24   a,    24   b,  and  24   c,  and the interconnect parameters, and performs a data row conversion. After the data row conversion, the data rows are supplied to the error correction processing parts  22   a,    22   b,  and  22   c,  respectively. When the data rows are respectively inputted to the error correction computation parts  23   a,    23   b,  and  23   c,  the error correction computation parts  23   a,    23   b,  and  23   c  perform an LDPC decoding process of one repetition time. The obtained results are inputted to the interconnect part  21  again. Based upon the data rows inputted as computation results and the interconnect parameters, the interconnect part  21  performs a barrel shifter process that is reverse to the operation performed at the time of input to the error correction processing parts (i.e., a barrel shifter process for three barrel shifters for 32-data). The data rows recovered into the original order by the interconnect part  21  are inputted to the memory banks  20   a,    20   b,  and  20   c  again. The data rows inputted as computation results to the memory banks  20   a,    20   b,  and  20   c  are stored into predetermined addresses by write addresses generated in the error correction processing control parts  25   a,    25   b , and  25   c.    
         [0076]    The LDPC decoding process can be performed one repetition time by the above steps. This process is repeated a predetermined number of times, so that desired LDPC decoding results for three codes can be obtained. 
         [0077]    Description will be made about the third case, i.e., the case where the barrel shifter  21   b  in the interconnect part  21  is configured to have two groups (one capable of dealing with an error correction process having parallelism of M×2 and one capable of dealing with an error correction process having parallelism of M) by the group configuration information. It is assumed that a turbo decoding process is to be performed for one code by the error correction processing parts  22   a  and  22   b  and that an LDPC decoding process is to be performed for one code by the error correction processing part  22   c.  The code length of data to be subjected to turbo decoding is assumed to be 512. The coding rate of turbo decoding is assumed to be 1/3. Specifically, the total code length of data to be subjected to turbo decoding is 1536. The code length of data to be subjected to LDPC decoding is assumed to be 768. In other words, it is assumed that 1536 input data for a turbo decoding process are stored in the memory banks  20   a  and  20   b.  it is assumed that 768 input data for an LDPC decoding process are stored in the memory bank  20   c.  It is assumed that the number of data of the single data row that can be stored in the memory banks  20   a,    20   b,  and  20   c  is defined such that M=32. Specifically, the number of data readable and writable when one of the memory banks is accessed is calculated by M=32. In this case, the error correction processing apparatus can perform two types of error correction processes on data used at one time. The operation of the error correction processing apparatus will be described below. 
         [0078]    First, the external IF  26  supplies, to the configuration data holding parts  24   a,    24   b,  and  24   c,  the group configuration information for the interconnect part  21 , the interconnect parameters, and the information indicative of what error correction method is used for a process in the error correction processing parts  22   a,    22   b,  and  22   c  (information commanding the error correction processing parts  22   a  and  22   b  to conduct turbo decoding and the error correction processing part  22   c  to conduct LDPC decoding in this example). Then, based upon the obtained information, the error correction processing control parts  25   a,    25   b,  and  25   c  in the error correction processing parts  22   a,    22   b,  and  22   c  start to execute a program corresponding to a turbo decoding process or an LDPC decoding process. When the program is executed, the error correction processing control parts  25   a,    25   b,  and  25   c  output a read address to the memory banks  20   a,    20   b,  and  20   c,  respectively. The memory banks  20   a,    20   b,  and  20   c  read a desired data row based upon the received address. The three read data rows are outputted to the interconnect part  21 . 
         [0079]    The interconnect part  21  changes the barrel shifter  21   b  into one barrel shifter ( 62  of  FIG. 5 ) for 32-data in response to the inputted data rows, the group configuration information in the configuration data holding parts  24   a,    24   b,  and  24   c,  and the interconnect parameters, and changes the configuration of the cross bar  21   a  such that the cross bar  21   a  is connected only to the two error correction processing parts  22   a  and  22   b.  The interconnect part  21  performs a data row conversion on the inputted data rows with the changed configuration. Specifically, the interconnect part  21  performs an interleaving process on the input data rows from the memory banks  20   a  and  20   b  when the repetition times are odd, and outputs the input data rows from the memory banks  20   a  and  20   b  without any data row conversion when the repetition times are even. Furthermore, the interconnect part  21  performs a barrel shifter process on the input data from the memory bank  20   c.  After the data row conversion, the data rows are supplied to the error correction processing parts  22   a,    22   b,  and  22   c,  respectively. When the data rows are respectively inputted to the error correction computation parts  23   a,    23   b,  and  23   c,  the error correction computation parts  23   a  and  23   b  perform a turbo decoding process of one repetition time whereas the error correction computation part  23   c  performs the LDPC decoding process one repetition time. The obtained results are inputted to the interconnect part  21  again. 
         [0080]    Based upon the data rows inputted as computation results and the interconnect parameters, the interconnect part  21  performs a data row conversion. Specifically, the interconnect part  21  makes it possible to pass through the data rows outputted from the error correction computation parts  23   a  and  23   b  when the repetition times are odd, and to perform a de-interleaving process on the data rows outputted from the error correction computation parts  23   a  and  23   b  when the repetition times are even. Furthermore, the interconnect part  21  performs, on the data row outputted from the error correction part  23   c,  a barrel shifter process that is reverse to the operation performed at the time of input to the error correction processing part (i.e., a barrel shifter process for one barrel shifter for 32-data). The data rows recovered into the original order by the interconnect part  21  are supplied to the memory banks  20   a,    20   b,  and  20   c  again. The data rows inputted as computation results to the memory banks  20   a,    20   b,  and  20   c  are stored into predetermined addresses by write addresses generated in the error correction processing control parts  25   a,    25   b,  and  25   c.    
         [0081]    The turbo decoding process and the LDPC decoding process can be performed simultaneously one repetition time by the above steps. This process is repeated a predetermined number of times, so that desired results of turbo decoding and LDPC decoding can be obtained. 
         [0082]    In the second exemplary embodiment, the numbers of the error correction processing parts and the memory banks are three. This is for the sake of brevity. The numbers of the error correction processing parts and the memory banks are not limited to three. Furthermore, in the second exemplary embodiment, the turbo decoding process and the LDPC decoding process have been described. However, since the three error correction processing parts  22   a ,  22   b,  and  22   c  can operate independently of each other, the error correction processing apparatus may process a combination of turbo decoding, LDPC decoding, and other error correction methods such as Viterbi decoding, or may process one method selected from among those methods. Any combination can be selected. 
         [0083]    Next, advantageous effects of the second exemplary embodiment will be described below. 
         [0084]    In the multicore type error correction processing apparatus according to the second exemplary embodiment, the barrel shifter  21   b  in the interconnect part  21  is configured such that a plurality of error correction processing parts can form various groups based upon group configuration information stored in the configuration data holding parts  24   a,    24   b,  and  24   c . Therefore, one or more types of error correction, such as LDPC decoding, can simultaneously be performed with parallelism corresponding to various performance requirements. Furthermore, unlike the first exemplary embodiment, data required to control the interconnect part  21  may be stored only in the configuration data holding parts  24   a,    24   b,  and  24   c  in the second exemplary embodiment. Accordingly, a programming process becomes relatively simple, and reduction of the circuit scale can be expected with regard to the control system. 
       Third Exemplary Embodiment 
       [0085]    Next, a third exemplary embodiment of the present invention will be described in detail with reference to the drawings. The third exemplary embodiment is also a variation of the first exemplary embodiment. Differences between the third exemplary embodiment and the first exemplary embodiment are as follows: In the first exemplary embodiment, the interconnect control part  11   c  in the interconnect part  11  are supplied with input signals through two lines of the error correction processing control parts  15   a,    15   b,  and  15   c  and the configuration data holding parts  14   a,    14   b,  and  14   c.  In the third exemplary embodiment, the interconnect control part  31   c  in the interconnect part  31  is supplied with input signals only from the error correction processing control parts  35   a,    35   b,  and  35   c.  This structure is also different from that illustrated in  FIG. 3  because the latter has the interconnect part  21  connected to the configuration data holding parts  24   a,    24   b,  and  24   c    24   a - 24   c.    
         [0086]    Referring to  FIG. 3 , the multicore type error correction processing apparatus according to the third exemplary embodiment includes a plurality of memory banks  30   a,    30   b,  and  30   c,  a plurality of error correction processing parts  32   a,    32   b,  and  32   c,  and the interconnect part  31 . 
         [0087]    The memory banks  30   a,    30   b,  and  30   c  are used to store data to be processed (referred to as input data), data being computed, and the results. The error correction processing parts  32   a,    32   b,  and  32   c  perform an error correction process. The error correction processing parts  32   a,    32   b,  and  32   c  include error correction computation parts  33   a,    33   b,  and  33   c  operable to actually process received input data and error correction processing control parts  35   a,    35   b,  and  35   c  operable to control the error correction computation parts  33   a,    33   b,  and  33   c  and to generate memory addresses for the memory banks  30   a,    30   b,  and  30   c  and interconnect parameters required for the interconnect part  31 . In addition, configuration data holding parts  34   a,    34   b,  and  34   c  hold configuration parameters which are indicative of the error correction processing parts  32   a,    32   b , and  32   c  and which are received from the external IF  36 . The interconnect part  31  includes a cross bar  31   a  primarily used in turbo decoding, a barrel shifter  31   b  used in an LDPC decoding process, and an interconnect control part  31   c  operable to control the group configuration, operation, and the like. 
         [0088]    Those components operate as follows. 
         [0089]    The memory banks  30   a,    30   b,  and  30   c  store data to be computed or processed. This is the same as in the first exemplary embodiment. 
         [0090]    The error correction processing parts  32   a,    32   b,  and  32   c  perform an actual error correction process. This is also the same as in the first exemplary embodiment. The interconnect part  31  operates on the basis of the group configuration information and the interconnect parameters obtained from the error correction processing control parts  35   a ,  35   b,  and  35   c  in the error correction processing part  32   a,    32   b,  and  32   c.  The interconnect control part  31   c  determines group configuration of the cross bar  31   a  and the barrel shifter  31   b  with reference to the group configuration information. Furthermore, the interconnect control part  31   c  controls a connection change in the cross bar  31   a  and a shift process of the barrel shifter  31   b  based upon the interconnect parameters. This makes it possible to perform a data row conversion such as interleaving for turbo decoding or barrel shifting for LDPC decoding. 
         [0091]    An example of a group configuration method of the third exemplary embodiment is explained again by the use of the barrel shifter  61  illustrated in  FIG. 5 . As shown in  FIG. 5 , the barrel shifter  61  can be configured such that the three error correction processing parts  32   a,    32   b , and  32   c  are regarded as one group (see the reference numeral  62  of  FIG. 5 ). In this case, the error correction processing apparatus can deal with an error correction process having parallelism of M×3. As another example, by changing the group configuration information, the barrel shifter  61  can be configured such that each of the error correction processing parts  32   a ,  32   b,  and  32   c  is regarded as one group (see the reference numeral  63  of  FIG. 5 ). In this case, the error correction processing apparatus has three groups in total and can deal with three error correction processes each having parallelism of M, which can be executed simultaneously. Furthermore, the barrel shifter  61  can be configured to have two groups, one of which includes the two error correction processing parts  32   a  and  32   b,  the other of which includes the error correction processing part  32   c  (see the reference numeral  64  of  FIG. 5 ). In this case, the error correction processing apparatus can deal with an error correction process having parallelism of M×2 and an error correction process having parallelism of M, which can be executed simultaneously. 
         [0092]    An overall operation of the multicore type error correction processing apparatus according to the third exemplary embodiment will be described in detail with reference to  FIG. 3 . The overall operation differs depending upon the group configuration of the interconnect part  31 . Therefore, the overall operation will be described in connection with each of the aforementioned three cases described in the operation of the interconnect part  31 . 
         [0093]    Description will be made about the first case, i.e., the case where the barrel shifter  31   b  in the interconnect part  31  is configured to have one group (capable of dealing with an error correction process having parallelism of M×3). It is assumed that an LDPC decoding process is to be performed. The code length of data to be subjected to LDPC decoding is assumed to be 768. In other words, it is assumed that 768 input data for an error correction process are stored in total in the memory banks. It is assumed that the number of data of 1 data row that can be stored in each of the memory banks  30   a,    30   b,  and  30   c  is defined such that M=32. Specifically, since the number of the memory banks is three, the number of data readable and writable when all of the memory banks are simultaneously accessed is calculated by M×3=96. In this case, the error correction processing apparatus can perform one type of error correction process at one time. The operation of the error correction processing apparatus will be described below. 
         [0094]    First, the external IF  36  supplies, to the configuration data holding parts  34   a,    34   b,  and  34   c,  the group configuration information for the interconnect part  31  and information indicative of what error correction method is used for a process in the error correction processing parts  32   a ,  32   b,  and  32   c  (information corresponding to LDPC in this example). Then, based upon the obtained information, the error correction processing control parts  35   a,    35   b,  and  35   c  in the error correction processing parts  32   a,    32   b,  and  32   c  start to execute a program corresponding to an LDPC decoding process. When the program is executed, the error correction processing control parts  35   a,    35   b,  and  35   c  output a read address to the memory banks  30   a,    30   b,  and  30   c . The error correction processing control parts  35   a,    35   b,  and  35   c  output interconnect parameters and group configuration information to the interconnect part  31 . The memory banks  30   a,    30   b , and  30   c  read a desired data row based upon the received address. The read data row is outputted to the interconnect part  31 . 
         [0095]    The interconnect part  31  uses the barrel shifter  31   b  as a barrel shifter ( 62  of  FIG. 5 ) for 96-data on the basis of the inputted data row, the interconnect parameters, and the group configuration information, and performs a data row conversion. After the data row conversion, the data rows are supplied to the error correction processing parts  32   a - 32   c.  When the data rows are inputted to the error correction computation parts  33   a,    33   b,  and  33   c,  the error correction computation parts  33   a,    33   b,  and  33   c  perform the LDPC decoding process one repetition time. The obtained results are supplied to the interconnect part  31  again. Based upon the data rows inputted as computation results and the interconnect parameters, the interconnect part  31  performs a barrel shifter process that is reverse to the operation performed at the time of input to the error correction processing parts. The data rows recovered into the original order by the interconnect part  31  are supplied to the memory banks  30   a,    30   b,  and  30   c  again. The data rows supplied as computation results to the memory banks  30   a,    30   b,  and  30   c  are stored into predetermined addresses by write addresses generated in the error correction processing control parts  35   a,    35   b,  and  35   c.    
         [0096]    The LDPC decoding process can be performed one repetition time by the above steps. This process is repeated a predetermined number of times, so that desired LDPC decoding results can be obtained. 
         [0097]    Description will be made about the second case, i.e., the case where the barrel shifter  31   b  in the interconnect part  31  is configured to have three groups (each being capable of dealing with an error correction process having parallelism of M). It is assumed that the LDPC decoding process is to be performed for three codes. The code length of data to be subjected to LDPC decoding is assumed to be 768. In other words, it is assumed that 768 input data for an error correction process are stored in each of the memory banks. It is assumed that data of the single data row that can be stored in each of the memory banks  30   a,    30   b,  and  30   c  are equal in number to M=32. Specifically, the number of data readable and writable when one of the memory banks is accessed is calculated such that M=32. In this case, the error correction processing apparatus can perform three types of error correction processes at one time. The operation of the error correction processing apparatus will be described below. 
         [0098]    First, the external IF  36  supplies, to the configuration data holding parts  34   a,    34   b,  and  34   c,  the group configuration information for the interconnect part  31  and the information indicative of what error correction method is used for a process in the error correction processing parts  32   a,    32   b,  and  32   c  (information corresponding to LDPC in this example). Then, based upon the obtained information, the error correction processing control parts  35   a,    35   b,  and  35   c  in the error correction processing parts  32   a,    32   b,  and  32   c  start to execute a program corresponding to the LDPC decoding process. When the program is executed, the error correction processing control parts  35   a,    35   b,  and  35   c  output a read address to the memory banks  30   a,    30   b,  and  30   c , respectively. Furthermore, the error correction processing control parts  35   a,    35   b,  and  35   c  output interconnect parameters and group configuration information to the interconnect part  31 . The memory banks  30   a,    30   b,  and  30   c  read a desired data row based upon the received address. The three read data rows are outputted to the interconnect part  31 . 
         [0099]    The interconnect part  31  changes the barrel shifter  31   b  into three barrel shifters ( 63  of  FIG. 5 ) for 32-data on the basis of the inputted data rows, the interconnect parameters, and the group configuration information, and performs a data row conversion. After the data row conversion, the data rows are supplied to the error correction processing parts  32   a,    32   b,  and  32   c , respectively. When the data rows are respectively inputted to the error correction computation parts  33   a,    33   b,  and  33   c,  the error correction computation parts  33   a,    33   b,  and  33   c  perform the LDPC decoding process one repetition time. The obtained results are inputted to the interconnect part  31  again. 
         [0100]    Based upon the data rows inputted as computation results and the interconnect parameters, the interconnect part  31  performs a barrel shifter process that is reverse to the operation performed at the time of input to the error correction processing parts (i.e., a barrel shifter process for three 32-data barrel shifters). The data rows recovered into the original order by the interconnect part  31  are supplied to the memory banks  30   a,    30   b,  and  30   c  again. The data rows inputted as computation results to the memory banks  30   a,    30   b,  and  30   c  are stored into predetermined addresses by write addresses generated in the error correction processing control parts  35   a,    35   b,  and  35   c.    
         [0101]    The LDPC decoding process can be performed one repetition time by the above steps. This process is repeated a predetermined number of times, so that desired LDPC decoding results for three codes can be obtained. 
         [0102]    Description will be made about the third case, i.e., the case where the barrel shifter  31   b  in the interconnect part  31  is configured to have two groups (one capable of dealing with an error correction process having parallelism of M×2 and one capable of dealing with an error correction process having parallelism of M). It is assumed that a turbo decoding process is to be performed for one code by the error correction processing parts  32   a  and  32   b  and that an LDPC decoding process is to be performed for one code by the error correction processing part  32   c.  The code length of data to be subjected to turbo decoding is assumed to be 512. The coding rate of turbo decoding is assumed to be 1/3. Specifically, the total code length of data to be subjected to turbo decoding is 1536. The code length of data to be subjected to LDPC decoding is assumed to be 768. In other words, it is assumed that 1536 input data for a turbo decoding process are stored in the memory banks  30   a  and  30   b.  It is assumed that 768 input data for an LDPC decoding process are stored in the memory bank  30   c.  It is assumed that the number of data of the single data row that can be stored in the memory banks  30   a,    30   b,  and  30   c  is defined such that M=32. Specifically, the number of data readable and writable when one of the memory banks is accessed is calculated by M=32. In this case, the error correction processing apparatus can perform two types of error correction processes on data used at one time. The operation of the error correction processing apparatus will be described below. 
         [0103]    First, the external IF  36  supplies, to the configuration data holding parts  34   a,    34   b,  and  34   c,  the group configuration information for the interconnect part  31  and information indicative of what error correction method is used for a process in the error correction processing parts  32   a ,  32   b,  and  32   c  (information commanding the error correction processing parts  32   a  and  32   b  to conduct turbo decoding and the error correction processing part  32   c  to conduct LDPC decoding in this example). Then, based upon the obtained information, the error correction processing control parts  35   a,    35   b,  and  35   c  in the error correction processing parts  32   a,    32   b,  and  32   c  start to execute a program corresponding to a turbo decoding process or an LDPC decoding process. When the program is executed, the error correction processing control parts  35   a,    35   b,  and  35   c  output a read address to the memory banks  30   a,    30   b,  and  30   c,  respectively. Furthermore, the error correction processing control parts  35   a,    35   b,  and  35   c  output interconnect parameters and group information to the interconnect part  31 . The memory banks  30   a,    30   b,  and  30   c  read a desired data row based upon the received address. The three read data rows are outputted to the interconnect part  31 . 
         [0104]    The interconnect part  31  changes the barrel shifter  31   b  into one barrel shifter ( 62  of  FIG. 5 ) for 32-data on the basis of the inputted data rows, the interconnect parameters, and the group configuration information, and changes the configuration of the cross bar  31   a  such that the cross bar is connected only to the two error correction processing parts  32   a  and  32   b.  The interconnect part  31  performs a data row conversion on the inputted data rows with the changed configuration. Specifically, the interconnect part  31  performs an interleaving process on the input data rows from the memory banks  30   a  and  30   b  when the repetition times are odd, and outputs the input data rows from the memory banks  30   a  and  30   b  without any data row conversion when the repetition times are even. Furthermore, the interconnect part  31  performs a barrel shifter process on the input data from the memory bank  30   c.    
         [0105]    After the data row conversion, the data rows are supplied to the error correction processing parts  32   a,    32   b,  and  32   c,  respectively. When the data rows are respectively inputted to the error correction computation parts  33   a,    33   b,  and  33   c,  the error correction computation parts  33   a  and  33   b  perform one repetition time of a turbo decoding process whereas the error correction computation part  33   c  performs one repetition time of an LDPC decoding process. 
         [0106]    The obtained results are inputted to the interconnect part  31  again. Based upon the data rows inputted as computation results and the interconnect parameters, the interconnect part  31  performs a data row conversion. Specifically, the interconnect part  31  allows the data rows outputted from the error correction computation parts  33   a  and  33   b  to go through when the repetition times are odd, and performs a de-interleaving process on the data rows outputted from the error correction computation parts  33   a  and  33   b  when the repetition times are even. Furthermore, the interconnect part  31  performs, on the data row supplied from the error correction computation part  33   c,  a barrel shifter process that is reverse to the operation performed at the time of input to the error correction processing part (i.e., a barrel shifter process for one barrel shifter for 32-data). The data rows recovered into the original order by the interconnect part  31  are inputted to the memory banks  30   a,    30   b,  and  30   c  again. The data rows supplied as computation results to the memory banks  30   a,    30   b,  and  30   c  are stored into predetermined addresses by write addresses generated in the error correction processing control parts  35   a,    35   b,  and  35   c.    
         [0107]    Thus, the turbo decoding process and the LDPC decoding process can be performed simultaneously one repetition time by the above steps. This process is repeated a predetermined number of times, so that desired results of turbo decoding and LDPC decoding can be obtained. 
         [0108]    In the third exemplary embodiment, the numbers of the error correction processing parts and the memory banks are three. This is for the sake of brevity. The numbers of the en - or correction processing parts and the memory banks are not limited to three. Furthermore, in the third exemplary embodiment, the turbo decoding process and the LDPC decoding process have been described. However, since the three error correction processing parts  32   a,    32   b,  and  32   c  can operate independently of each other, the error correction processing apparatus may process a combination of turbo decoding, LDPC decoding, and other error correction methods such as Viterbi decoding, or may process one method selected from among those methods. Any combination can be selected. 
         [0109]    Next, advantageous effects of the third embodiment will be described below. 
         [0110]    In the multicore type error correction processing apparatus according to the third exemplary embodiment, the barrel shifter  31   b  in the interconnect part  31  is configured such that a plurality of error correction processing parts can form various groups based upon interconnect parameters and group configuration information obtained from the error correction processing control parts  35   a,    35   b,  and  35   c.  Therefore, one or more types of error correction, such as turbo decoding and LDPC decoding, can simultaneously be performed with parallelism corresponding to various performance requirements. Furthermore, unlike the second exemplary embodiment, data required to control the interconnect part  31  are generated by the error correction processing control parts  35   a - 35   c.  Accordingly, the interconnect part  31  can be controlled without any latency inputted from the exterior of the interconnect part  31 . Thus, reduction of the circuit scale can be expected with regard to the control system. 
       Fourth Exemplary Embodiment 
       [0111]    Next, a fourth exemplary embodiment of the present invention will be described in detail with reference to the drawings. The fourth embodiment is a variation of the first embodiment. Differences between the fourth exemplary embodiment and the first exemplary embodiment are as follows: The cross bar  11   a  of the first exemplary embodiment is omitted from the multicore type error correction processing apparatus in the fourth exemplary embodiment. In other words, the error correction processing apparatus of the fourth exemplary embodiment has an interconnect part  41  only including a barrel shifter  41   b  and an interconnect control part  41   c.  The operation of the error correction processing apparatus is the same as in the first exemplary embodiment. According to the fourth exemplary embodiment, an error correction processing system can be applicable to LDPC coding which has different code lengths, and the circuit scale can further be reduced. 
       INDUSTRIAL APPLICABILITY 
       [0112]    The present invention is applicable to an error correction processing apparatus in a wireless communication system or the like. 
         [0113]    Next, additional features of the present invention would be enumerated below. 
         [0114]    A multicore type error correction processing system according to an embodiment of the present invention may comprise: a plurality of data storage parts; a data row conversion part for receiving data from the plurality of data storage parts and converting an order of data in a data row; an external input part for receiving a control parameter from an exterior of the external input part; an external parameter storage part for storing data received from the external input part; and a plurality of error correction processing parts for receiving data from the data row conversion part and performing a predetermined error correction process based upon a parameter stored in the external parameter storage part, wherein the error correction processing part includes an error correction computation part and an error correction processing control part for controlling the error correction computation part so as to perform the error correction process based upon the parameter stored in the external parameter storage part, and the data row conversion part performs a data row conversion using a barrel shifter operation which includes a rotation operation based upon a shift process and which collectively indicates a group of the plurality of the error correction processing parts to be outputted or which individually indicates each of the plurality of the error correction processing parts in response to the control information. 
         [0115]    The multicore type error correction processing system may further comprise a cross bar located between the plurality of the data storages and the barrel shifter to deliver the data row from each of the data storages to the barrel shifter in response to the control information. The above-mentioned multicore type correction processing system is effective to process a plurality of different codes, such as LDPC codes and turbo codes. 
         [0116]    A multicore type error correction processing method according to another embodiment of the present invention is used in a multicore type error correction processing system including: a plurality of data storage parts, a data row conversion part for receiving data from the plurality of data storage parts and converting an order of data in a data row, an external input part for receiving a control parameter from an exterior of the external input part, an external parameter storage part for storing data received from the external input part, and a plurality of error correction processing parts for receiving data from the data row conversion part and performing a predetermined error correction process based upon a parameter stored in the external parameter storage part. The error correction processing method is characterized in that: the error correction processing part performs an error correction computation process and an error correction processing control for controlling the error correction computation process so as to perform a predetermined error correction process based upon a parameter stored in the external parameter storage part, and the data row conversion part performs a data row conversion by using a barrel shifter operation which includes a rotation operation based upon a shift process and which collectively indicates a group of the plurality of error correction processing parts to be outputted or which individually indicates each of the error correction processing parts to be outputted in response to the control information. 
         [0117]    This application is based upon and claims the benefit of priority from Japanese patent application No. 2010-225403, filed on Oct. 5, 2010, the disclosure of which is incorporated herein in its entirety by reference. 
       REFERENCE SIGNS LIST 
       [0000]    
       
           10   a - 10   c,    20   a - 20   c,    30   a - 30   c,    40   a - 40   c,    50   a - 50   c  Memory bank 
           11 ,  21 ,  31 ,  41 ,  51  Interconnection part 
           11   a,    21   a,    31   a,    51   a  Cross bar 
           11   b,    21   b,    31   b,    41   b,    51   b,    61  Barrel shifter 
           11   c,    21   c,    31   c,    41   c,    51   c  Interconnection control part 
           12   a - 12   c,    22   a - 22   c,    32   a - 32   c,    42   a - 42   c,    52   a - 52   c  Error correction processing part 
           13   a - 13   c,    23   a - 23   c,    33   a - 33   c,    43   a - 43   c,    53   a - 53   c  Error correction computation part 
           14   a - 14   c,    24   a - 24   c,    34   a - 34   c,    44   a - 44   c  Configuration data holding part 
           15   a - 15   c,    25   a - 25   c,    35   a - 35   c,    45   a - 45   c,    55   a - 55   c  Error correction processing control part 
           16 ,  26 ,  36 ,  46  External IF