Abstract:
A differential input stage including two input branches each with a pair of transistors. A bias circuit supplies a separate bias current to each of the input branches. A first transistor of each branch has a first current terminal coupled to a source node receiving a bias current, a second current terminal coupled to an output node, and a control terminal coupled to an input node. A second transistor of each branch has a first current terminal coupled to the corresponding source node, a control terminal coupled to the corresponding input node, and a second current terminal coupled to an intermediate node. The second transistors operate as a current path in higher differential voltage conditions to keep the first transistor active to avoid violating the maximum gate-source voltage.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of U.S. Provisional Application Ser. No. 61/807,831, filed on Apr. 3, 2013, which is hereby incorporated by reference in its entirety for all intents and purposes. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates in general to a MOS differential input stage, and more particularly to a high voltage MOS differential input stage incorporating input gate protection. 
     2. Description of the Related Art 
     Years ago, 15 Volt (V) MOS field-effect transistors (MOSFETs) had thick gate oxides in which the breakdown voltage of the gate oxide exceeded the drain-source breakdown voltage. There was not a problem with rupturing the gate oxide of amplifiers or comparators having input stages that used these earlier MOSFET configurations. As oxides got thinner, the breakdown voltage got smaller. Eventually, DMOS (double-diffused MOS) transistors came out that had higher voltages. But there was a problem inasmuch as the operating voltage of the FETs, such as, for example, 40V, was far greater than the rated breakdown voltage of the gate oxides for these devices. 
     One solution to this problem was to add back-to-back external diodes across the input pair. This worked for some amplifier applications but not for comparators in which one input might be connected to a voltage reference while the other input might be at any voltage. Conventional methods have been proposed for solving this problem with internal designs in which the input transistor devices are operated as source followers. Then the voltages at their sources became a new input signal pair for an internal amplifier that was configured to handle large input voltage differences. The conventional methods have been complicated in that they require significant design effort for each implementation. 
     JFET (junction FET) amplifiers have also been available. Although JFETs do not have a gate oxide breakdown problem, they do incorporate fairly large diodes that leak current, especially at high temperatures, and are thus undesirable for many applications. 
     SUMMARY OF THE INVENTION 
     A differential input stage including first and second input circuits, a load circuit and a bias circuit. The first input circuit includes first and second transistors. The first transistor has a first current terminal coupled to a first source node, a second current terminal coupled to a first output node, and a control terminal coupled to a first input node. The second transistor has a first current terminal coupled to the first source node, a second current terminal coupled to an intermediate node, and a control terminal coupled to the first input node. The second input circuit includes third and fourth transistors. The third transistor has a first current terminal coupled to a second source node, a second current terminal coupled to a second output node, and a control terminal coupled to a second input node. The fourth transistor has a first current terminal coupled to the second source node, a second current terminal coupled to the intermediate node, and a control terminal coupled to the second input node. The load circuit is coupled between the first and second output nodes and a first supply node. The bias circuit is coupled to the first supply node and a second supply node and develops a first bias current at the first source node and a second bias current to the second source node. 
     The transistors may be implemented as PMOS transistors or NMOS transistors or the like. The transistors may each be implemented with a thin gate oxide. The W/L ratio of the second and fourth transistors may be different than the W/L ratio of the first and third transistors. For example, the W/L ratio of the inner transistors coupled to the intermediate node may be made with a larger W/L ratio than the outer transistors to increase the voltage swing at the output. In a particular embodiment, the inner transistors are short channel field-effect transistors. The differential input stage may be used as the input stage of an amplifying device, such as an amplifier or comparator or the like. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. 
         FIG. 1  is a schematic diagram of a conventional MOS differential input stage; 
         FIG. 2  is a schematic diagram of a high voltage MOS differential input stage implemented according to one embodiment of the present invention incorporating input gate protection; 
         FIG. 3  is a simplified diagram of an amplifier incorporating the high voltage MOS differential input stage of  FIG. 2 ; and 
         FIG. 4  shows a series of simulation timing diagrams illustrating operation of the high voltage MOS differential input stage of  FIG. 2 . 
     
    
    
     DETAILED DESCRIPTION 
     The benefits, features, and advantages of the present invention will become better understood with regard to the following description, and accompanying drawings. The following description is presented to enable one of ordinary skill in the art to make and use the present invention as provided within the context of a particular application and its requirements. Various modifications to the preferred embodiment will, however, be apparent to one skilled in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described herein, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed. 
       FIG. 1  is a schematic diagram of a conventional MOS differential input stage  100 . The MOS differential input stage  100  includes P-type or P channel MOS (PMOS) devices (or FETs) PA, PB, P 1  and P 2 , a bias current source  115 , and load resistors R 1  and R 2 . A supply node  113  is a reference node with any suitable positive, negative or ground supply voltage level. In the illustrated embodiment, the supply node  113  is coupled to a reference supply voltage level, such as ground (GND) having a voltage level of 0 Volts (V). A supply node  101  receives and provides a supply voltage VDD, which is any suitable supply voltage level. In one embodiment, VDD is 12V although other supply voltage levels are contemplated. In the illustrated embodiment, PA, PB, P 1  and P 2  are rated at about 18V (source to drain), but the gate-source voltages of these devices have a maximum operating voltage range of 5V due to their thin gate oxides. 
     The sources of PA and PB are coupled to VDD, and the gate and drain of diode-coupled PB is coupled to a bias node  103 , which is further coupled to the gate of PA. The bias current source  115  is coupled between nodes  103  and  113  to draw a bias current IB from node  103  to the GND node  113 . 
     The drain of PA is coupled to a source node  105 , which is further coupled to the sources of P 1  and P 2 . The gate of P 1  receives an input voltage VIN 1  at input node  107  and its drain is coupled to one end of the load resistor R 1  at a first output node  111 . The gate of P 2  receives an input voltage VIN 2  at input node  109  and its drain is coupled to one end of the load resistor R 2  at a second output node  113 . The other ends of the load resistors R 1  and R 2  are coupled to GND at node  113 . 
     The PMOS devices PA and PB are coupled in a mirror configuration so that the bias current IB developed by the bias current source  115  is mirrored into the source node  105 . In the illustrated embodiment, PA is sized relative to PB to double the bias current IB to provide a bias current 21B to the source node  105 . In one embodiment, for example, PA is twice the size of PB (or is configured with twice as many parallel-coupled devices of the same size) to double the bias current through PA. 
     As understood by those of ordinary skill in the art, VIN 1  and VIN 2  apply a differential input voltage between input nodes  107  and  109  and a corresponding differential output voltage is developed between output nodes  111  and  113 . A significant and known problem of the conventional MOS differential input stage  100  is that if a substantial voltage difference is applied between VIN 1  and VIN 2 , the maximum gate-source voltage rating of at least one of the input PMOS devices P 1  and P 2  is exceeded thereby damaging that PMOS device. 
     Suppose, for example, that VIN 2  is pulled low to GND and VIN 1  is pulled high to 10V in the 12V configuration. Since the gate of P 1  is reverse biased, P 1  is shut off. Thus, substantially all of the bias current of 21B from PA flows through the source and drain of P 2  to the load resistor R 2 . Since VIN 2  is at 0.0V, the source voltage of P 2  is at about 1V. The source of P 1  is also connected to the source of P 2 , so that P 1  has a gate-source voltage of 10V−1V=9V. This exceeds the 5V oxide voltage rating of P 1 , which would likely cause the oxide to rupture thereby damaging P 1 . A similar result occurs when the voltages are reversed likely rupturing the oxide of P 2  thus damaging P 2 . 
       FIG. 2  is a schematic diagram of a high voltage MOS differential input stage  200  implemented according to one embodiment of the present invention incorporating input gate protection. The high voltage MOS differential input stage  200  includes PMOS devices (or FETs) PA 1 , PA 2 , PB, P 11 , P 12 , P 21  and P 22 , the current source  115  and the load resistors R 1  and R 2 . The current source  115  and PB are coupled together in similar manner between nodes  101  and  113  and to bias node  103  in which PB is diode-coupled to mirror bias current in a similar manner. Although the high voltage MOS differential input stage  200  is shown with load resistors (R 1  and R 2 ), it is understood that other types of load devices may be used, such as transistors or the like. 
     In this case, PA is replaced by two PMOS devices PA 1  and PA 2 , each having a source coupled to node  101  and a gate coupled to the bias node  103 . The drain of PA 1  is coupled to a source node  201  and the drain of PA 2  is coupled to a source node  203 . P 1  is replaced by P 11  and P 12 , in which the sources of P 11  and P 12  are coupled to the source node  201 . P 2  is replaced by P 21  and P 22 , in which the sources of P 21  and P 22  are coupled to the source node  203 . The gates of P 11  and P 12  are coupled to the input node  107  receiving the input voltage VIN 1  and the gates of P 21  and P 22  are coupled to the input node  109  receiving the input voltage VIN 2 . The drain of P 11  is coupled to one end of the resistor R 1  at a first output node  211  and the drain of P 21  is coupled to one end of the resistor R 2  at a second output node  213 . The other ends of R 1  and R 2  are coupled to GND at node  113 . The drains of P 12  and P 22  are coupled together at an intermediate node  205 . 
     The source current of P 11  is a current IS 1  flowing from source node  201 , the source current of P 12  is a current IS 2  flowing from source node  201 , the source current of P 21  is a current IS 3  flowing from source node  203 , and the source current of P 22  is a current IS 4  flowing from source node  203 . 
     The PMOS devices PA 1  and PA 2  are coupled in a mirror configuration with PB so that the bias current IB developed by the bias current source  115  is mirrored into the source nodes  201  and  203 . In the illustrated embodiment, PA 1  and PA 2  are both sized relative to PB to provide the same bias current IB to the source nodes  201  and  203 . In one embodiment, for example, PA 1 , PA 2  and PB are the same size or otherwise include the same number of parallel-coupled devices of the same size. 
     The high voltage MOS differential input stage  200  incorporates gate protection which is configured to protect the input devices by always keeping both P 11  and P 21  on. Consider operation of the input devices P 11  and P 21  when VIN 1  and VIN 2  are equal. It is first noted that since PA 1  and PA 2  each supply a bias current of IB, the total bias current is the same as in the conventional circuit (2IB) except split between two branches. Assuming that P 11  and P 21  are matched, their source voltages at nodes  201  and  203 , respectively, are the same so that no current flows between nodes  201  and  203 . Thus, the source currents of both P 11  and P 21  flow through their drains to the load resistors R 1  and R 2 , respectively. The output nodes  211  and  213  have the same voltage assuming that the resistances of R 1  and R 2  are equal. 
     It is noted that P 11  and P 12  have their sources and gates connected together and that P 21  and P 22  also have their sources and gates connected together. When VIN 1  and VIN 2  are sufficiently close to each other, say within 50 millivolts (mV), then P 12  and P 22  are both in the “triode” region of operation. More specifically, P 12  and P 22  both behave like resistors. In this condition, however, P 11  and P 21  are in the “active” region of operation. 
     When instead VIN 1  and VIN 2  are “far” apart in voltages otherwise indicating a fault condition, such as separated by 5V or more, operation responds in order to protect the input devices. Consider the above example in which VIN 1  is 10V and VIN 2  is 0V. PA 1  is supplying a current of “IB” into the sources of P 11  and P 12  at source node  201 . If P 11  and P 12  are identical, the current splits with half the current flowing through P 11  and the other half flowing through P 12 . Both of these devices are now in the active region of operation. A bias current of IB is also flowing into the common sources of P 21  and P 22  at source node  203 . Whereas P 12  is in the active region of operation, P 22  is in the triode region of operation and thus still behaves like a resistor. Therefore, the drain current of P 12  flows through P 22 , operating similar to a resistor, to node  203  and this current is added to the source current of P 21 . Thus, the current flowing through P 21  is now 1.5×IB. This increases the source-gate voltage of both P 22  and P 21  which decreases the drain-source resistance of P 22 . 
     Operation is similar when the input voltages are reversed, that is, when VIN 1  is 0V and VIN 2  is 10V. In this case, P 21  and P 22  are active whereas P 12  operates in the triode region and behaves like a resistor. About half of the bias current IB flows through P 22  to P 12  so that a current of 1.5-IB flows through P 11 . 
     In one embodiment, P 11 , P 12 , P 21  and P 22  have the same width (W) per length (L) ratio, or W/L. With devices having the same W/L ratio, the differential output current is 1.5×IB−0.5×IB=IB. In another embodiment, P 12  and P 21  do not have the same channel values as P 11  and P 22 , respectively. In one embodiment, P 12  and P 22  are short channel FETs, which means that their lengths are reduced relative to their widths as compared to that of P 11  and P 12 . In this manner, for the stated fault condition in which the input voltages are separated by a significant amount and VIN 1 &gt;VIN 2 , P 12  receives a greater amount of the bias current provided by PA 1 . Also, when the input voltages are separated by a significant amount and VIN 2 &gt;VIN 1 , P 22  receives a greater amount of the bias current provided by PA 2 . The sizing of P 12  and P 22  relative to P 11  and P 21  allows a greater amount of bias current to flow through the intermediate node  205  to enable a larger differential output signal. Using short channel FETs allows the differential output current to increase above IB and approach 21B. 
     A simple formula for the drain current I d  of MOSFETs that are in their active region of operation is according to equation (1):
 
I d =μC ox /2×W/L×(V gs −V t ) 2   (1)
 
where “μ” is the mobility, C ox  is the oxide capacitance, W is the width of the FET&#39;s channel, L is its channel length, V gs  is the gate-source voltage, and V t  is the threshold voltage. In the triode mode region operation is according to equation (2):
 
I d =μC ox /2×W/L×[2(V gs −V t )×V ds −V ds   2 ]  (2)
 
where V ds  is the drain-source voltage. It is noted that if V ds =(V gs −V t ), then the two equations are the same. For simplicity&#39;s sake, let μC ox /2×W/L=K. Then equations (1) and (2) may be re-written as the following two equations (3) and (4):
 
I d =K×(V gs −V t ) 2  and  (3)
 
I d =K×[2(V gs −V t )×V ds −V ds   2 ]  (4)
 
where equation (4) may further be re-written as the following equation (5):
 
I d ≈K×[2(V gs −V t )×V ds ]  (5)
 
if V ds  is small compared with 2(V gs −V t ), and where “≈” denotes an approximation.
 
     In the active region the transconductance (g m ) of the FET is ∂I d /∂V gs  or 2K×(V gs −V t ). In the triode region I d /V ds  is ≈2K×(V gs −V t ) which is the same as in the active mode. Note that these results are for substantially identical FETs since they have the same K value (in other words, W/L is the same for the FETs). If W/L for a given FET is increased, like in the short channel FET, then the corresponding g m  is larger and the corresponding ON resistance (1/g m ) is smaller for the FET. Reducing the ON resistance of the intermediate devices P 12  and P 22  relative to the outer devices P 11  and P 21  allows greater current flow through intermediate node  205  providing a greater range for the differential output current. 
       FIG. 3  is a simplified diagram of an amplifying device  300  incorporating the high voltage MOS differential input stage  200 . The amplifying device  300  represents any type of amplifier or comparator, such as an operational amplifier, transconductance amplifier, comparator, etc. The amplifying device  300  includes a positive (+) or non-inverting input receiving VIN 1  and a negative (−) or inverting input receiving VIN 2  internally provided across the high voltage MOS differential input stage  200  incorporated within the amplifying device  300 . The high voltage MOS differential input stage  200  develops internal output voltages on nodes  211  and  213 . The amplifying device  300  also receives the source voltages VDD and GND. The output portion of the amplifying device  300  is not shown. A single-ended output VOUT is shown at the output of the amplifying device  300 , although a differential output is also contemplated. 
     Although the high voltage MOS differential input stage  200  is particularly advantageous as the input stage of an amplifying device, such as an amplifier or comparator or the like, it is understood that it may be used for any circuit having a differential input. The high voltage MOS differential input stage  200  may be implemented in a discrete circuit or implemented on an integrated circuit (IC) or the like. 
       FIG. 4  shows a series of simulation timing diagrams illustrating operation of the high voltage MOS differential input stage  200 . The first graph  401  plots the voltage of VIN 1  and the corresponding voltage of node  201 , labeled V 201 , in Volts (V), the second graph  403  plots VIN 2  and the corresponding voltage of node  203 , labeled V 203 , in Volts (V), the third graph  405  plots the corresponding source voltages IS 1 , IS 2 , IS 3  and IS 4  in response to application of the VIN 1  and VIN 2  voltages of plots  401  and  403 , in nano-amperes (nA), and the fourth graph  407  plots the corresponding voltages of the output nodes  211  and  213 , labeled V 211  and V 213 , respectively, in response to application of the VIN 1  and VIN 2  voltages of plots  401  and  403 , in milli-volts (mV), all versus time (in seconds, s). 
     For this simulation, the bias current IB is approximately 100 nA. The load resistors R 1  and R 2  are each approximately 2 megohms (MΩ). 
     For the simulation, the voltage of VIN 1  is linearly swept from 10V to 0V for a time period of 10 seconds, while the voltage of VIN 2  is linearly swept in the opposite direction from 0V to 10V during the same time period. In this manner, VIN 1  starts at 10V while VIN 2  starts at 0V which would violate the maximum gate voltage rating of input device P 1  in the conventional MOS differential input stage  100 . For the high voltage MOS differential input stage  200 , however, the voltage V 201  of the source node  201  remains at about 0.5V above VIN 1  while VIN 1  sweeps from 10V to just above about 5V. When the voltages of VIN 1  and VIN 2  are close near 5V at about 5 seconds, both V 201  and V 203  experience a slight non-linearity. After 5 seconds, V 201  remains at about 0.65V above VIN 1  while VIN 1  continues to sweep from about 5V down to 0V. 
     Since the source voltage V 201  of P 11  essentially tracks its gate voltage well below the 5V fault voltage, the gate-source voltage rating is not exceeded regardless of the input voltage range between VIN 1  and VIN 2  (within the supply voltage range). 
     As shown by graph  403 , V 203  also tracks the voltage of VIN 2  which is swept in the opposite direction from 0V to 10V during the 10 second period. V 203  starts at about 0.65V above VIN 2 , and ends up at about 0.5V above VIN 2  in a similar albeit opposite manner as described for V 201  and VIN 1 . Since the source voltage V 203  of P 21  also tracks its gate voltage well below the 5V fault voltage, the gate-source voltage rating is not exceeded regardless of input voltage range applied between VIN 1  and VIN 2  (within the supply voltage range). 
     As shown by graph  405 , while VIN 1  is greater than VIN 2 , IS 1  is about 14 nA, IS 2  is about 86 nA, IS 3  is about 186 nA, and IS 4  is about −86 nA. During the entire time, IS 1 +IS 2 =100 nA, and IS 3 +IS 4 =100 nA. IS 1 , which is the source current for P 11 , illustrates that P 11  remains on during this otherwise initial fault condition. P 12  receives most of the bias current IB (100 nA−14 nA=86 nA) which flows through P 22  (−86 nA) to combine with IB (100 nA) to increase IS 3  (186 nA). 
     When VIN 1  and VIN 2  approach the same voltage level (˜5V) at about 5 seconds into the simulation, the source currents begin to reverse. IS 1  increases while IS 2  decreases until IS 1  rises to about 186 nA while IS 2  decreases to about −86 nA after 5 seconds. Meanwhile, IS 3  decreases from 186 nA to about 14nA while IS 4  increases from −86 nA to about 86 nA. Again, during the entire time, IS 1 +IS 2 =100 nA and IS 3 +IS 4 =100 nA. Near the end of the simulation, IS 3 , which is the source current for P 21 , illustrates that P 21  remains on during this otherwise initial fault condition. P 22  receives most of the bias current IB (100 nA−14 nA=86 nA) which flows through P 12  (−86 nA) to combine with IB (100 nA) to increase IS 1  (186 nA). 
     Graph  407  illustrates the corresponding output voltages V 211  and V 213  during the simulation. V 211  is initially about 28 mV and V 213  is about 372 mV while VIN 1 &gt;VIN 2 . As VIN 1  approaches the same voltage level as VIN 2 , V 211  increases while V 213  decreases by the same amount so that the voltage levels effectively reverse. Thus, V 211  increases to about 372 mV while V 213  decreases to about 28 mV. Since the combined bias currents remain constant (21B), V 211 +V 213  remains constant at about 400 mV during the simulation (assuming constant load resistance of 2 MΩ each). 
     It is noted that although the high voltage MOS differential input stage  200  is illustrated using PMOS transistor devices, operation is substantially similar for configuration using N-type or N channel (NMOS) transistor devices. The NMOS configuration is essentially implemented by replacing the PMOS devices with NMOS devices, by swapping the reference voltages (VDD to GND, and GND to VDD), and by reversing direction of the bias current IB of the current source  115  as understood by those skilled in the art. Operation is substantially similar. It is noted that PMOS devices may be better matched than corresponding NMOS devices providing more accurate results for the PMOS configuration illustrated. 
     It is noted that although the high voltage MOS differential input stage  200  is illustrated using PMOS transistor devices rated at about 18V (drain-source) with maximum gate voltages of 5V and using VDD of 12V, operation is substantially the same for other voltage ranges and ratings. The present invention is useful to protect higher voltage devices (e.g., 100V or more) with correspondingly lower maximum gate voltage ratings. The bias currents and load resistors may be suitably adjusted for any configuration. 
     Although the present invention has been described in considerable detail with reference to certain preferred versions thereof, other versions and variations are possible and contemplated. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for providing the same purposes of the present invention without departing from the spirit and scope of the invention.