Abstract:
A circuit is presented having many transistors connected in parallel between a supply node and a pre-drive stage. The many transistors each have a gate connected to a delay select line to control current through the pre-drive stage. Also presented is a circuit having a first stack of transistors connected between a first supply node and a pre-drive stage. The circuit also has a second stack of transistors connected between a second supply node and the pre-drive stage, and many delay select lines. The stack of transistors each have a gate connected to one of the delay select lines.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    The application is a Divisional of co-pending application Serial No. 09/476,425, filed Dec. 30, 1999 by applicants Jed Griffin and Ernest Khaw, entitled “A Constant CMOS Driver,” of which is a continuation-in-part of U.S. patent application Ser. No. 09/108,606, filed Jul. 1, 1998.  
           [0002]    1. Field of the Invention  
           [0003]    Embodiments of the present invention relate to driver circuits for driving transmission lines, and more particularly to complementary metal oxide semiconductor (CMOS) driver circuits.  
           [0004]    2. Background  
           [0005]    A dominant limitation of conventional manufactured driver circuits is their artificially low transmission rates due to widely varying operating conditions, such as voltage, temperature, and process variation. Due to varied operating conditions, the propagation delay and the output impedance of drivers varies widely, thus, hampering impedance matching.  
           [0006]    Propagation delay can vary typically by a factor of two to three across two extreme operating conditions. This variation of propagation delay seriously impacts system timing at higher frequencies. Without a constant delay across all operating conditions, system timing is adversely impaired such that timing margins have to be introduced to handle any delay time variations due to varying operating conditions.  
           [0007]    A most common and useful communication topology is peer-to-peer connections with full duplex transmission. To achieve optimal impedance matching in this type of topology, the output impedance of the transmitting side must match the characteristic impedance of the transmission line. Impedance matching at the transmitting end has traditionally been accomplished by placing a series resistor between the output driver and the transmission line. For this method to work, the output impedance of the output driver must be kept much lower than the characteristic impedance of the transmission line. This results in a much higher cost in area and power than required for merely transmitting a signal. Moreover, impedance matching is degraded due to varying resistance across operating conditions and the non-linearity of the driver. Another method is to use the nonlinear transistors of the output driver to approximate the linear characteristic impedance of the transmission line. This attempt, however, results in even worse impedance matching than a series resistor placed at the transmitting end.  
           [0008]    [0008]FIG. 1 illustrates an I/O (input/output) driver  102  communicating with a receiver  104  via a transmission line  106 . The transmission line  106  has a characteristic impedance Z o , and may be the physical layer of a bus. The driver  102  and the receiver  104  are complementary metal oxide semiconductor (CMOS) circuits. For purposes of mathematical analysis, the input impedance (Z in ) of the receiver  104  is approximated as being infinite relative to other impedances in the circuit. The receiver  104  may be one or more CMOS logic gates, or a differential amplifier.  
           [0009]    The driver  102  is transmitting an electromagnetic wave travelling in the transmit direction  108 . If Z in  of the receiver  104  is not equal to Z o , then a reflected wave will propagate in the receiver direction  110 . If the impedance of the driver  102  is not matched to the characteristic impedance Z o  then another reflected wave will again be generated, but now travelling in the transmit direction  108 . There will be many multiple reflections, and the electric and magnetic field vectors at any point along the transmission line  106  is the vector sum (superposition) of the transmitted field vector and all reflected field vectors at that point. This superposition of the transmitted wave and the reflected waves may cause signal degradation, which typically limits, for longer transmission lines, the speed at which digital data is reliably transmitted from the driver  102  to the receiver  104 .  
           [0010]    The first reflected wave can be reduced by terminating the receiving end of the transmission line  106  with a receiver or stub having an impedance matched to Z o . This may, however, require the use of an off-chip resistor, and furthermore, power may be wasted due to ohmic losses in the resistor. Another negative impact of impedance matching at the receiver end is loss of amplitude, potentially halving the amplitude, which can then make the transmitting signal susceptible to noise.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]    [0011]FIG. 1 is an illustration of a driver in communication with a receiver over a transmission line, where the receiver is not matched to the transmission line.  
         [0012]    [0012]FIG. 2 is an embodiment of the present invention.  
         [0013]    [0013]FIGS. 3 a  and  3   b  are approximations to the embodiment of FIG. 2 for two particular sets of conditions.  
         [0014]    [0014]FIG. 4 is an embodiment of the present invention having programmed linear output impedance.  
         [0015]    [0015]FIG. 5 is an embodiment of the invention comprising a pre-drive stage having programmable constant delay.  
         [0016]    [0016]FIG. 6 is an illustration of a plurality of p-channel and n-channel stacks with delay/impedance select lines.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0017]    Embodiments of the invention are described for input/output (I/O) drivers having an output impedance that is approximately independent of the output voltage, and which can be adjusted based upon variations in temperature, supply rail voltage, and variations in transistor dimensions (channel length, width, etc.). This allows for matching the driver&#39;s output impedance with the characteristic impedance of a transmission line driven by the I/O driver. If the output impedance is matched to the impedance of the transmission line, an electromagnetic wave that is reflected toward the driver will substantially cease from reflecting again. Therefore, signal degradation is reduced, thus, allowing for faster, more reliable data transmission. The exemplary embodiments are provided to illustrate the embodiments of the invention and should not be construed as limiting the scope of the embodiments of the invention.  
         [0018]    Reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “other embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments, of the invention. The various appearances “an embodiment,” “one embodiment,” or “some embodiments” are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic “may”, “might”, or “could” be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to “a” or “an” element, that does not mean there is only one of the element. If the specification or claims refer to “an additional” element, that does not preclude there being more than one of the additional element.  
         [0019]    Relevant terminology will first be introduced. Two element Boolean algebra is relevant to switching circuits. For any point in a circuit, the term LOW will denote a set of voltages that map into one of the two Boolean elements. The term HIGH will denote a set of voltages that map into the other of the two Boolean elements. The particular mapping into Boolean elements depends upon the technology used, and may be different for different parts of a single circuit. To avoid dealing with set terminology, we shall say that a voltage is LOW/HIGH if it belongs to the set LOW/HIGH. We also follow the convention that for any given node within a circuit, LOW voltages are generally less than HIGH voltages. Referring to the figures, exemplary embodiments of the invention will now be described.  
         [0020]    In one embodiment of the invention circuit  200  in FIG. 2 is part of an I/O driver or buffer suitable for driving a transmission line. The circuit  200  provides an approximately constant output impedance when the transmission line is being driven. That is, the impedance of the circuit  200 , when “looking into” a port defined by the terminal  202  and power supply ground is approximately constant when the transmission line is being driven by the circuit  200 .  
         [0021]    Transistor set  206  and  212  and transistor set  208  and  216  are switched in complementary fashion with respect to each other to drive the transmission line. The circuit  200  is shown in FIG. 1 without the capability to tristate the output node  202  because V n  and V p  are shorted to the input node  204 . In some embodiments, however, they are approximately synchronous, and V p  and V n  are such that V p  transitions from HIGH to LOW before V n  transitions from HIGH to LOW, and V p  transitions from LOW to HIGH after V n  transitions from LOW to HIGH, so that p-channel metal oxide semiconductor field effect transistor (pMOSFET) set  206  and  212 , and n-channel metal oxide semiconductor field effect transistor (nMOSFET) set  208  and  216  are not simultaneously ON. Circuit  200  can be tristated if V p  is set HIGH and V n  is set LOW. Note that transistors  212  and  210  are considered a stack of pMOSFETs, and transistors  214  and  216  are considered a stack of nMOSFETs, where a stack of transistors consists of at least two transistors that are stacked together.  
         [0022]    The combination of  200  is such that, when V p  and V n  are both LOW the drain of pMOSFET  206  is approximately at the output voltage V o  and nMOSFET  208  is OFF; the drain of pMOSFET  210  is approximately at the output voltage V o  and nMOSFET  214  is OFF; and pMOSFET  212  is ON and nMOSFET  216  is OFF. When V  p  and V  n  are both HIGH, the drain of nMOSFET  208  is approximately at the output voltage V o , and pMOSFET  206  is OFF; the drain of nMOSFET  214  is approximately at the output voltage V o , and pMOSFET  210  is OFF; and nMOSFET  216  is off and its drain is approximately zero volts (ground) and pMOSFET  212  is OFF. Transistors  206  and  208  are considered to be the drive-stage of circuit  200 .  
         [0023]    The approximate constant output impedance property of circuit  200  can be understood by considering FIGS. 3 a  and  3   b  which provide approximations to FIG. 2 for the cases in which V p  and V n  are both LOW and in which V p  and V n  are both HIGH, respectively. The circuits of FIGS. 3 a  and  3   b , however, do not model circuit  200  during logic transitions of voltages V  p  and V  n  .  
         [0024]    For purposes of finding an approximate expression for the output impedance of the circuit in FIG. 3 a  when transistors  208 ,  214 , and  216  are ON, let I dsl  denote the drain-source current of nMOSFET  208 , and I ds2  denote the drain-source current between nMOSFETs  216  and  214 . Let Z  out  denote the output impedance of the circuit of FIG. 3 a . Then the output impedance is given by  
           V   O   =Z   out ( I   ds2 ).  
         [0025]    Noting that the drain-source voltage (VDS) of nMOSFET  208  is equal to V o , and assuming that the threshold voltage of nMOSFET  208  is much less than the supply node V DD , then an approximate expression for the drain-source current of nMOSFET  208  is given by  
         I     ds                 1       =         β   1     2          [       2        V   DD          V   o       -     V   o   2       ]                             
 
         [0026]    Where β 1  is the beta for nMOSFET  208  and we assume that nMOSFET  208  is in its linear or nonsaturation region. Transistors nMOSFET  214  and  216  are configured to be in their saturation region when ON, and provided their threshold voltage V T  is much less than V o , an approximate expression for the drain-source current of nMOSFET  214  and  216  is given by  
         I     ds                 2       =           β   2     2          [       2        V   o   2       -     V   o   2       ]       =         β   2     2          V   o   2                               
 
         [0027]    where β 2  is the beta of nMOSFETs  214  and  216 . Substituting the above two expressions into the expression for the output impedance yields  
         V   o     =       Z   out          [         β   1          V   DD          V   o       -       β   1            V   o   2     2       +       β   2            V   o   2     2         ]                             
 
         [0028]    If the betas of transistors  208 ,  214  and  216  are matched and denoted by β, then the above expression yields  
         Z   out     =     1     β                   V   DD                               
 
         [0029]    As seen from the above displayed equation, the output impedance of the circuit of FIG. 3 a  (when transistors  208 ,  214  and  216  are ON) is approximately constant (i.e., independent of V o ). A similar analysis shows that the output impedance of circuit  3   b  is also (approximately) given by the above displayed equation, provided the betas are also properly matched. Also note that the capacitance and inductance seen at the output node are also approximately constant, whether the driver is driving high or low. This is key to ensure that the imaginary part of the impedance also remains approximately constant, neglecting slight variations due to voltage coefficients from different levels of V o . This, however, has more direct impact on the output driver slew rate than it does on impedance matching.  
         [0030]    In another class of embodiments, in FIG. 4 transistors  206  and  208  in Block  0  may be joined by a first and second plurality of drive transistors, such as transistors  410  and  412  in Block N, respectively, so that subsets of the first and second pluralities of drive transistors can be selected so as to provide a programmable output impedance. In this case, to match betas, transistors  210 ,  212  (upper impedance elements),  214  and  216  (lower impedance elements) in Block  0  would be joined by a plurality of transistors, such as transistors  414 ,  416 , (upper impedance elements),  418  and  420  (lower impedance elements), so that the proper subset of plurality transistors can be selected, depending upon the selected subset of the drive transistors, so that the output impedance is programmable and approximately independent of output voltage V o .  
         [0031]    An embodiment belonging to the previously described class of embodiments is illustrated in FIG. 4, where corresponding components in FIGS. 2 and 4 have the same numeric label. In FIG. 4, signals Sp o , Sp n , Sn o  and Sn n , on impedance select lines  402 ,  424 ,  404 , and  426 , respectively, are select signals. If Sp n  and S n , are LOW, and Sp o  and Sn o  are HIGH, then transistors associated with Sp n , and Sn n  are OFF and circuit  400  behaves as circuit  200  in FIG. 2. If Sp n  and Sn n  are each HIGH, then the transistors associated with Sp n  and Sn n  affect the output impedance.  
         [0032]    To determine the output impedance when Sp n , Sn n , Sp o  and Sn o  are each HIGH, consider betas of transistors  208 ,  214  to be matched and denoted as β 1 , the beta of  216  to be much greater than β 1 , the betas of transistors  412 ,  418  to be matched and denoted as β 2 , and that of  420  to be much greater than β 2 . Then a similar analysis as discussed earlier yields the approximate expression for the output impedance,  
         Z   out          1       [       β   1     +     β   2       ]          V   DD                               
 
         [0033]    By utilizing a plurality of transmission gates, impedance select lines, and matched pairs of transistors as in FIG. 4, the output impedance can be programmed and still remain approximately independent of output voltage.  
         [0034]    The circuit illustrated in FIG. 5 illustrates one embodiment of the invention having a pre-drive stage ( 502 ,  504 ,  518 ,  520 ) coupled with a programmable bias circuit that may be used with previous discussed embodiments. This embodiment of the invention features a programmable technique for keeping constant the propagation delay of the driver, which causes the propagation delay to vary from its design value. The particular operating conditions can be compensated for by programming the actual, observed delay via delay select lines Sp o  ( 514 ) to Sp n  ( 516 ) and Sn o  ( 510 ) to Sn n  ( 512 ). Note that Sp b  ( 522 ) and Sn b  ( 524 ) are always ON. The delay value of delay select lines Sp o  ( 514 ) to Sp n  ( 516 ) and Sn o  ( 510 ) to Sn n  ( 512 ) would correspond to proportionally large transistors which they are coupled with, namely  526 ,  528 ,  532 , and  534  respectively. To reduce the amount of delay (for faster operating conditions), smaller transistors and fewer delay select lines would be asserted. Contrarily, to increase the amount of delay (for slower operating conditions), larger transistors and more delay select lines would be asserted. The sensitivity at which the operating conditions are sampled determines the number of delay select lines and correspondingly how tight the interval around a nominal delay can be set to. If delay select lines Sp o  ( 514 ) to Sp n  ( 516 ), and Sn o  ( 510 ) to Sn n  ( 512 ) are OFF, then transistors  526 ,  528 ,  532 , and  534  are OFF, and circuit  500  would only consist of transistors  518 ,  520 ,  530  and  536 . If Sp o  ( 514 ) to Sp n  ( 516 ) are ON, then transistors  526 ,  528  affect the propagation delay. If Sn o  ( 510 ) to Sn n  ( 512 ) are ON, then transistors  532  and  534  affect the propagation delay. Typically, to ensure that V o  is substantially equal to V i , Sn o  ( 514 ) and Sn n  ( 510 ), are both turned on together. Accordingly, Sp n  ( 516 ) and Sn n  ( 512 ) would be turned ON together. The stacked configuration of the selected transistors with the actual drive transistors also serves to prevent hot electrons.  
         [0035]    The embodiments of the invention described above are, of course, subject to other variations in structure and implementation. For instance, additional devices may be inserted between various nodes, terminals, and devices in the above embodiments without materially changing their overall function. For example, voltage drops may be introduced by resistors, diodes, or transistors configured as diodes, to change various voltage levels, or buffers may be inserted between various nodes, terminals, and devices. In general, the scope of the invention should be determined not by the embodiments illustrated but by the appended claims and their legal equivalents.