Abstract:
A pad driver is presented that in one form is capable of driving a wide range of capacitive loads with constant rise and fall times, over a wide range of temperature and process corners. A desirable form of the pad driver is characterized by the ability to charge and discharge rail-to-rail with a constant charging and discharging rate over the whole charging and discharging cycles. Furthermore, desirably the driver is independent of any load present at the output pad.

Description:
TECHNICAL FIELD  
       [0001]     The technical field relates to input/output pads of an integrated circuit. More particularly, the field relates to circuits for driving output signals via the pads of an integrated circuit chip.  
       BACKGROUND  
       [0002]     There has been significant research on various implementations of pad drivers for computer data communication and modern portable peripherals. The Universal Serial Bus (USB) standard is one of these common modern standards that result in tough specifications for pad drivers. Pad drivers ideally have a limited range of rise and fall times over a broad range of capacitive loads, process corners, supply voltages and temperature variations.  
         [0003]     There are several known implementations of pad drivers. One known form of a current controlled pad driver is presented, in  FIG. 1 . In the pad driver of  FIG. 1 , the charging and discharging of the output is done through a current source. One drawback of this architecture is that the charging and discharging rates (slope=I/C L ) are a function of the load capacitance, and thus, rise and fall times are load dependent.  
         [0004]     Another known implementation is illustrated in  FIG. 2 . The pad driver of  FIG. 2  has a negative feedback to control the charging and discharging rates. In the pad driver of  FIG. 2 , the output is compared with a reference signal by a high-speed rail-to-rail common mode amplifier. However, one drawback of this architecture is the need for a high-speed operational amplifier, which introduces unnecessary complexities to modern high-speed communication applications.  
         [0005]     Yet another known pad driver circuit is shown in  FIG. 3 . In the pad driver of  FIG. 3 , current sources I 1  and I 2  are used to charge and discharge capacitors C 1  and C 2 , respectively. This in turn charges and discharges points V 1  and V 2 , respectively, at a constant charging and discharging rate (I 1 /C 1 =I 2 /C 2 ). The source followers MN 1  and MP 2  buffer the constant-rate charging and discharging of nodes V 1  and V 2 , respectively, to the output load capacitance C LOAD , thus, sustaining equal charging and discharging rates independent of the load value C LOAD . A potential problem with the configuration of  FIG. 3  is that, during the charging phase, node V 1  reaches V DD , but the output voltage will remain at V DD −V TN  such that MN 1  is just on (wherein V TN  is the threshold voltage of the NMOS driver MN 1 ).  
         [0006]     In addition, during discharging, node V 2  drops to zero, but the output voltage will drop to V TP  such that MP 2  is just on, (wherein V TP  is the threshold voltage of the PMOS driver MP 2 ). In order to address these problems, the pad driver circuit of  FIG. 3  uses two amplifiers. Amplifier A 1  turns on the switch MP 1  during charging when the voltage at node V 1  approaches V DD . In this case, the capacitive load charges through the on-resistance of MP 1  to V DD . Amplifier A 2  is used to turn on the switch MN 2  during discharging when the voltage at node V 2  approaches zero. In this case, the capacitive load discharges through the on-resistance of MN 2  to zero. However, this adds to the complexity of the circuit design because of the two high-speed amplifiers A 1  and A 2 . Another drawback of this architecture arises during the charging and discharging phases when the output voltage approaches V DD −V TN  and V TP , respectively. Under these conditions, the charging and discharging process becomes dependent on the load capacitance and the on-resistance of switches MP 1  and MN 2 , respectively.  
         [0007]     Therefore, a need exists for improved pad drivers.  
       SUMMARY  
       [0008]     Described herein are electronic pad driver circuits for driving one or more input/output pads of an integrated circuit device. In one aspect, the circuits described herein allow for rail-to-rail charging and discharging of input/output pads. In a further aspect, the rates of charging and discharging of the input/output pads by the pad driver circuits disclosed herein are constant and not dependent on the load capacitance.  
         [0009]     In one aspect, the pad driver circuits described herein comprise a voltage source, such as a battery, adaptable for maintaining the NMOS and PMOS transistors of one or more source follower circuits at saturation in order to ensure the rail-to-rail charging and discharging of the input/output pads. In a further aspect, one or more switches are provided to connect the source follower circuits to a voltage generator appropriately during a pre-charging or a pre-discharging phase. In one more aspect, the components of the exemplary pad driver circuit described herein are simple and easy to assemble and hence do not add to the complexity of the larger circuit comprised within the subject integrated circuit.  
         [0010]     Additional features and advantages will become apparent from the following detailed description of the illustrated embodiments, which proceeds with reference to the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE FIGURES  
       [0011]      FIG. 1  is a circuit diagram illustrating one known pad driver circuit charging and discharging directly through a current source.  
         [0012]      FIG. 2  is a circuit diagram illustrating one known pad driver circuit comprising a negative feedback to control charging and discharging.  
         [0013]      FIG. 3  is a circuit diagram illustrating one known pad driver circuit comprising operational amplifiers for buffering during charging and discharging.  
         [0014]      FIG. 4  is a circuit diagram illustrating a conventional NMOS source follower circuit.  
         [0015]      FIG. 5  is a block diagram illustrating the comparison between the output and input signals of the source follower circuit of  FIG. 4 .  
         [0016]      FIG. 6  is a circuit diagram illustrating an NMOS source follower circuit comprising battery for maintaining the NMOS transistor of the circuit in saturation.  
         [0017]      FIG. 7  is a block diagram illustrating the comparison between the input and output signals of the source follower circuit of  FIG. 6 .  
         [0018]      FIG. 8  is block diagram illustrating the source follower circuit of  FIG. 6  coupled to a voltage generator via a closed switch during a pre-charge phase.  
         [0019]      FIG. 9  is a block diagram illustrating the source follower circuit of  FIG. 6  in a charge phase with the voltage generator disconnected from the circuit.  
         [0020]      FIG. 10  is a detailed pad driver circuit comprising charge capacitors for preserving threshold voltages needed to retain the NMOS and PMOS driver transistors in saturation during the charging and discharging phases, respectively.  
         [0021]      FIG. 11  is a circuit diagram illustrating the condition of the pad driver circuit of  FIG. 10  during a pre-charge phase.  
         [0022]      FIG. 12  is a circuit diagram illustrating the condition of the pad driver circuit of  FIG. 10  during a charge phase.  
         [0023]      FIG. 13  is a circuit diagram illustrating the condition of the pad driver circuit of  FIG. 10  during a pre-discharge phase.  
         [0024]      FIG. 14  is a circuit diagram illustrating the condition of the pad driver circuit of  FIG. 10  during a discharge phase.  
     
    
     DETAILED DESCRIPTION  
       [0025]     The disclosed invention is direct toward all novel and unobvious features and aspects of the embodiments of the system and methods described herein both alone and in various combinations and sub-combinations thereof. The disclosed features and aspects of the embodiments can be used alone or in various novel and unobvious combinations and sub-combinations with one another. The invention is not limited to embodiment have all of the advantages of the embodiment disclosed herein or that solves all of the problems of prior designs.  
         [0026]     The circuits disclosed herein are merely exemplary in nature and are used to illustrate the principles described below. Other circuits that implement the principles taught herein are within the scope of this disclosure. Also, the circuits described herein can be implemented as a software model stored on a computer-readable medium and executed on a computer to emulate the operation of a circuit. Some of the disclosed circuits, for example, can be implemented as software representations that are part of an Electronic Design Automation (EDA) tool for simulating the operation of a collection of electronic devices. Such models or software representations can be executed on a single computer or a networked computer. For clarity, only those aspects of the software germane to these disclosed methods are described; product details well known in the art are omitted. For the same reason, the computer hardware is not described in detail.  
         [0027]     An exemplary load insensitive pad driver is based on modifications to the source follower architecture, as shown in  FIG. 4 . Provided that the transistor size (W/L) is large enough compared to the capacitive load  32 , the source follower is characterized by a low output impedance of its driver transistor  30 . This circuit thus acts as a voltage source where the output (V OUT ) tracks the input signal (V IN ) regardless of the value of the output load. The main disadvantage of this conventional source follower is the limitation of the output swing to V DD −V T  when the input reaches V DD . (See  FIG. 5 ). This can be explained as follows: When V IN  increases from zero to V T , the driver transistor  30  is off and the output voltage is zero. When the input V IN  exceeds V T , the driver goes into saturation and the output follows the input as shown in  FIG. 5 . When the input reaches V DD , the output settles on V DD −V T . The output in this example cannot exceed V DD −V T , because if it does, the driver transistor  30  is turned off.  
         [0028]     Conceptually speaking, as shown in  FIG. 6 , a load independent pad driver circuit that swings rail-to rail (e.g., from zero to V DD ) can be implemented by placing a voltage source, such as a series DC supply  40  of value V t  between the input  41  and the gate  42  of the driver  50 , which causes the input to the driver gate at  42  to shift from the input by V T . Thus, while the input V IN  ( 41 ) charges up from zero to V DD , the input to the driver gate at  42  charges up from V t  to V DD +V T . In addition, in this case, the output also charges from zero to V DD , and follows the input signal, as shown in  FIG. 7 . This assures that the driver transistor  50  is in saturation at all times and that the output at  43  swings rail-to-rail (e.g., from zero to V DD ).  
         [0029]     An exemplary implementation of this concept is shown in  FIGS. 8 and 9 . In this example, a series capacitor  60  (serving as a voltage source, in this case like a battery) is connected between the input  61  and the driver gate  62  of driver transistor  70 . The operation of this circuit has precharging and charging phases. During the precharging phase, see  FIG. 8 , switch  72  is closed and a voltage threshold generator circuit  74  that generates a voltage V T  precharges the series capacitor  60  to voltage V T . The voltage V T  corresponds to the threshold voltage of the driver (e.g., the NMOS threshold voltage of the driver in this example). During the charging phase, see  FIG. 9 , the switch  72  is open and the voltage generator V T    74  is disconnected from the driver gate  62  and the input  61  charges from zero to V DD . In this case, the capacitor sustains its initial charge of V T  due to the absence of a charge leakage path, and the driver gate  62  will charge (ramp up) from V T  to V DD +V T  in response to the input signal ramping up from zero to V DD . This is so because, the voltage across the capacitor  60  is maintained at V T , and thus, the output (V OUT ) follows the input and charges from zero to V DD  as the input voltage charge from zero to V DD . This is possible at least in part because the driver remains in saturation during the entire charging phase.  
         [0030]     At least based on the foregoing discussion, a load independent pad driver circuit  100  can be implemented, such as in the exemplary embodiment shown in  FIG. 10 . Transistors MN 1  at  80  and MP 1  at  81  represent the source follower drivers. Transistors MP 2 -MP 5  ( 83 ,  84 ,  85 , and  86 ) are PMOS switches. Transistors MN 2 -MN 5  ( 87 ,  88 ,  89 , and  90 ) are NMOS switches. The circuit  100  is driven by two simple V T  extractors  95  and  96 , one for the NMOS driver at  95  and the other for the PMOS driver at  96 .  
         [0031]     Referring to the circuit  100  of  FIG. 10 , during the pre-charge phase when the input {overscore (D IN )} goes high (rises), transistor MN 2  ( 87 ) is switched on. As a result, capacitor C C  at  97  is discharged to zero and the transistor MN 5  at  90  is turned on so that the gate  99  of transistor MN 1  at  80  is charged with V TN , which is the threshold voltage for the transistor MN 1  at  80 . Then during the charging phase, when {overscore (D IN )} goes low, MN 2  at  87  and MN 5  at  90  turn off, while MP 3  at  84  and MP 4  at  85  turn on, the current source I C  at  101  starts to charge C C  at  97  at a constant rate according to the relation:  
         V   1     =         I   c       C   c       ⁢   t         
 
         [0032]     In addition, since voltage at V 2  is shifted from V 1  by a voltage of V TN , V 2  can be determined by:  
         V   2     =           I   c       C   c       ⁢   t     +     V   TN           
 
         [0033]     Because of this shift, as node V 1  ramps from zero to V DD , node V 2  ramps from V TN  to V DD +V TN  and the output  102  ramps from zero to V DD  and follows the ramping of the node V 1 .  
         [0034]     The discharging process is done in a manner similar to the charging process, but with the aid of a lower inverter pair  83  and  88 . When {overscore (D IN )} goes low, MP 2  at  83  and MP 5  at  86  turn on, thus, the capacitor C C  at  98  is charged to V DD  and the driver gate at  105  of MP 1  at  81  is charged to V DD −V TP , where V TP  is threshold voltage for MP 1  at  81 . Then during the discharging phase when {overscore (D IN )} goes low, MP 2  at  83  and MP 5  at  86  turn off, while MN 3  at  88  and MN 4  at  89  turn on. Thus, the current source I C  at  103  discharges the capacitor C c  at  98  with a constant rate and voltage, which is given by:  
         V   3     =       V   DD     -         I   c       C   c       ⁢   t           
 
 Since the voltage at node V 4  is shifted from the voltage at V 3  by −V TP , the voltage at V 4  can be given by:  
         V   4     =       V   DD     -         I   c       C   c       ⁢   t     -     V   TP           
 
 As a result, as the voltage at node V 3  discharges from V DD  to zero, the voltage at node V 4  discharges from V DD −V TP  to −V TP  and the output voltage at  103  discharges from V DD  to zero following the voltage discharge at node V 3 . 
 
         [0035]     The charging of MP 1  at  81  gate by V DD −V TP  and the charging of the output pad load by MN 1  at  80  occurs simultaneously in this example during the falling edge of the input signal {overscore (D IN )}. In addition, charging of MN 1  at  80  gate with V TN  and the discharging of output pad load by MP 1  at  80  occurs simultaneously during the rising edge of the input signal {overscore (D IN )}.  
         [0036]      FIGS. 11-14  illustrate various exemplary scenarios and paths for charging and discharging of the output pad in conjunction with the rise and fall of the input signal {overscore (D IN )}.  FIG. 11  illustrates the exemplary precharging scenario. In this case, the input {overscore (D IN )} is pulled high, thus, turning on MN 2  at  87 , and pulling the upper inverter pair at  110  high and discharging the capacitor at  97  to zero. Meanwhile, the gate  99  is charged to the threshold voltage V TN  by transistor MN 5  at  90  being turned on.  
         [0037]      FIG. 12  illustrates the charging phase. In this phase, the input {overscore (D IN )} is low. The output of this upper inverter pair at  110  is ramped up to V DD  at a constant rate of I C /C C . Meanwhile, the gate  99  is ramps up to V DD +V TN , and thus, causing the output  102  to ramp up from zero to V DD .  
         [0038]      FIG. 13  illustrates the exemplary pre-discharging phase. In this phase, the input {overscore (D IN )} is pulled low. As a result, the output of the lower inverter pair at  115  is pulled high and MP 5  at  86  conducts voltage −V TP  to the gate  105  of MP 1  at  81 , which is eventually charged to V DD −V TP .  
         [0039]      FIG. 14  illustrates the discharging phase. In this phase {overscore (D IN )} is set high and the output of the lower inverter pair at  115  ramps down at the rate of I C /C C . The gate  105  of transistor MP 1  at  81  ramps down to −V TP  causing the output  102  to follow by discharging down from V DD  to zero. In these examples described above, the rate of charging or discharging as the case may be is not dependent on the load capacitance C L , which may vary. Instead, the charge and discharge rates are held constant (e.g., I C /C C ).  
         [0040]     Having described and illustrated the principles of our invention with reference to the illustrated embodiments, it will be recognized that the illustrated embodiments can be modified in arrangement and detail without departing from such principles. Elements of the illustrated embodiment simulated in software may be implemented in hardware and vice versa. Also, the technologies from any example can be combined with the technologies described in any one or more of the other examples.  
         [0041]     In view of the many possible embodiments to which the principles of the invention may be applied, it should be recognized that the illustrated embodiments are examples of the invention and should not be taken as a limitation on the scope of the invention. For instance, various components of systems and tools described herein may be combined in function and use. We therefore claim as our invention all subject matter that comes within the scope and spirit of these claims.