Abstract:
A ternary content addressable memory (TCAM) having an array of cells arranged in rows and columns, each cell comprising of a main memory cell for storing a data bit and its complement and a pair of bit lines for carrying the data bit and its complement. A compare circuit having a pair of compare lines and an output node, the compare circuit coupled to the main memory cell for comparing the data bit and its complement with corresponding compare lines and outputting a compared signal at the output node. A match circuit coupled to the output node of the compare circuit and a match input line and a match output line, the match circuit for selectively connecting the match input line to the match output line based on the compared signal. A mask memory cell for storing and outputting mask data and a mask circuit coupled to the match circuit and the match input line and the match output line for masking the compared signal or for selectively connecting the match input line to the match output line based on the mask data.

Description:
This application claims priority to Korean Patent Application No. 2002-36626, filed on Jun. 28, 2002, the contents of which are herein incorporated by reference in their entirety. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a content addressable memory cell (hereinafter referred to as “CAM cell”) and, more particularly, to a ternary content addressable memory cell (hereinafter referred to as “TCAM cell”) capable of storing three states of information. 
     2. Discussion of Related Art 
     A CAM is a memory which is addressed by its own contents. Different from a RAM or ROM wherein an address is used to indicate a specific position in its memory cell array and outputs data stored in the addressed position, a CAM is externally supplied with data, and searches are made within the contents of the CAM for a match with the supplied data, and outputs an address depending on a comparison result. Each cell of a CAM includes comparison logic. A data value input to the CAM is compared with data stored in all the cells simultaneously. The matched result is the address. A CAM is commonly used in applications requiring fast searches for a pattern, a list, image data, etc. 
     A CAM cell may be classified into a binary CAM cell and a TCAM cell. A typical binary CAM cell is configured with a RAM cell to store one of two states of information, i.e., a logic “1” state and a logic “0” state. The binary CAM cell includes a compare circuit that compares data supplied externally (hereinafter, ‘comparand data’) with data stored in the RAM cell and drives a corresponding match line to a predetermined state when the comparand data and the stored data are matched. Examples of the binary CAM cells are disclosed in U.S. Pat. No. 4,646,271 entitled “CONTENT ADDRESSABLE MEMORY HAVING DUAL ACCESS MODE”, U.S. Pat. No. 4,780,845 entitled “HIGH DENSITY, DYNAMIC, CONTENT-ADDRESSABLE MEMORY CELL”, U.S. Pat. No. 5,490,102 entitled “LOW CAPACITANCE CONTENT-ADDRESSABLE MEMORY CELL”, and U.S. Pat. No. 5,495,382 entitled “CONTENTS ADDRESSABLE MEMORY”. 
     A TCAM cell can store one of three states of information, i.e., a logic “1” state, a logic “0” state, and a “don&#39;t care” state. The TCAM cell includes a main RAM cell to store one of two states of information, i.e., a logic “1” state or a logic “0” state, and a mask RAM cell to store local mask data. A comparison result of comparand data with data stored in the main RAM cell is masked with the mask data such that the comparison result does not affect a corresponding match line. Such a TCAM cell offers the user more flexibility to determine what data bits in a word will be masked during a compare operation. TCAM cells are further described, for example, in U.S. Pat. No. 6,044,055 entitled “CONTENT ADDRESSABLE MEMORY STORAGE DEVICE” and U.S. Pat. No. 6,514,384 entitled “TERNARY CONTENT ADDRESSABLE MEMORY CELL”. FIG. 1 shows a conventional TCAM cell which includes a main memory cell having two NMOS transistors T 1  and T 2  and two inverters INV 1  and INV 2 , a compare circuit consisting of three NMOS transistors T 3 , T 4 , and T 5 , a mask circuit consisting of an NMOS transistor T 6 , and a mask memory cell consisting of two NMOS transistors T 7  and T 8  and two inverters INV 3  and INV 4 . The TCAM cell shown in FIG. 1 is described in U.S. Pat. No. 6,154,384. Signal lines represented as “BL” and “BLB” are used for data transmission of a main memory cell. Signal lines represented as “CL” and “CLB” are used for comparand data transmission. Signal lines represented as “ML” and “MLB” are used for mask data transmission of a mask memory cell. A TCAM is made from TCAM cells arranged in a matrix of rows and columns. TCAM cells in a row constitute one word, which may be 32, 64, 128 bits, or higher. Transistors T 5  and T 6  of the respective TCAM cells in a row constitute a wired-OR logic for a match line MATCH. 
     Although TCAMS afford advantages such as speedy access for numerous applications, drawbacks do exist. For example, when comparand data of the TCAM cell of FIG. 1 is not matched with data stored in a main memory cell, a discharge operation of a match line is carried out. Because the occurrence of unmatched words is usually greater than the occurrence of matched words, match lines (MATCH) corresponding to the unmatched words are frequently discharged, and more power is thereby consumed. 
     Another problem is shown in FIG. 2A. A logic high level at node DX of FIG. 1 (VCL-Vtn4 or VCLB-Vtn3, wherein VCL represents a voltage of a CL line, VCLB represents a voltage of a CLB line, and the Vtn3 and Vtn4 represent threshold voltages of transistors T 3  and T 4 , respectively) approaches a voltage only slightly higher than the threshold voltage of transistor T 3  or T 4 . This high level voltage at DX is used to turn on transistor T 5 . To compensate for the lowered high voltage level, a big-sized transistor T 5  must be used. The need for a bigger size transistor in each cell lowers the overall density of the TCAM. Even more problematic, if an operation voltage is lowered, the TCAM cell may not operate properly as the high level voltage at DX fails to meet the threshold voltage of transistor T 5 . For illustration, assuming that an operation voltage is 1.2V and a threshold voltage of an NMOS transistor T 5  is 0.5V, a high level of the DX node thus becomes 0.7V, as shown in FIGS. 2A and 2B. Since this level is not high enough to turn on the NMOS transistor T 5 , the signal level on match line MATCH cannot be used to properly indicate a match or no-match. 
     Referring back to the TCAM cell of FIG. 1, if the compare result is not masked (by transistor T 6 ), transistor T 5  is turned off when comparand data is matched to data stored in a main memory cell and is turned on when there is no match. That is, when there is a match, a match line MATCH is maintained at a precharge state. When there is no match, charges of the match line are discharged through transistors T 5  and T 6 . The discharge speed of the match line MATCH is a function of the number of unmatched bits in one word. For example, when only one bit of one word is unmatched, the charges of the match line MATCH are discharged through the transistors T 5  and T 6  of the unmatched TCAM cell. When n bits are unmatched among an m-bit word (n being a positive integer smaller than m), the charges of the match line MATCH are discharged through transistors nx (T 5 , T 6 ) in n TCAM cells. The time needed to discharge the match line MATCH varies depending on the number of mismatched cells. To minimize the discharge speed variation, larger sized transistors T 5  and T 6  are needed. This, however, results in larger size TCAM cells. Therefore, a discharge speed difference also negatively affects the density of a TCAM. 
     In view of the foregoing, a need exists for a content addressable memory cell that is stably operable at low operation voltage, low power consumption, and facilitates manufacture of a high density CAM. 
     SUMMARY OF THE INVENTION 
     According to an aspect of the present invention, a ternary content addressable memory (TCAM) having an array of cells arranged in rows and columns is provided, each cell comprising: a main memory cell for storing a data bit and its complement and a pair of bit lines for carrying the data bit and its complement; a compare circuit having a pair of compare lines and an output node, the compare circuit coupled to the main memory cell for comparing the data bit and its complement with corresponding compare lines and outputting a compared signal at the output node; a match circuit coupled to the output node of the compare circuit and a match input line and a match output line, the match circuit for selectively connecting the match input line to the match output line based on the compared signal; a mask memory cell for storing and outputting mask data; and a mask circuit coupled to the match circuit and the match input line and the match output line for masking the compared signal or for selectively connecting the match input line to the match output line based on the mask data. 
     Preferably, the compare circuit includes a pair of PMOS transistors, and the pair of PMOS transistors are correspondingly coupled to the pair of compare lines and commonly connected at the output node of the compare circuit. Further, each of the match circuit and the mask circuit includes an NMOS transistor, wherein the NMOS transistors of the match circuit and the mask circuit are commonly connected at the match input line and the match output line. In one embodiment, the match input line is connected to the match output line upon an indication of a match from the compared signal. 
     According to another aspect of the invention, the match input line is connected to the match output line upon an indication of a mask condition from the mask data. The match input line is also preferably cascaded from and connected to a match output line of a preceding cell or the match output line is cascaded and connected to a match input line of a subsequent cell along the same row. The TCAM further includes a discharge circuit coupled to ground and to the match input line of the first cell of the same row and a precharge circuit coupled to a preset voltage and to the match output line of the last cell of the same row, wherein when all cells of the same row output a match, all the match input and output lines of the same row are discharged to substantially ground. According to this embodiment, the compare circuit includes a pair of PMOS and a pair of NMOS transistors, each PMOS transistor being commonly connected to a corresponding NMOS transistor and a corresponding compare line, and each of the match circuit and the mask circuit includes an NMOS transistor. 
     According to another aspect of the invention, each of the match circuit and the mask circuit includes a PMOS transistor, and the compare circuit includes a pair of NMOS transistors. The PMOS transistors are commonly connected at the match input line and at the match output line. The TCAM of this embodiment further includes a precharge circuit coupled to a preset voltage and to the match input line of the first cell of the same row and a discharge circuit coupled to ground and to the match output line of the last cell of the same row, wherein when all cells of the same row output a match, all the match input and output lines of the same row are precharged to substantially the preset voltage. 
     Preferably, the main memory cell and the mask memory cell are at least one of SRAM, DRAM, or nonvolatile memory (NVM) cells. The TCAM further includes a main word line and a mask word line which are connected to each other. Further, each of the match circuit and the mask circuit includes a PMOS transistor. 
     According to another embodiment of the invention, a content addressable memory (CAM) having an array of cells arranged in rows and columns is provided, each cell comprising: a main memory cell for storing a data bit and its complement and a pair of bit lines for carrying the data bit and its complement; a compare circuit having a pair of compare lines and an output node, the compare circuit coupled to the main memory cell for comparing the data bit and its complement with corresponding compare lines and outputting a compared signal at the output node; a match circuit coupled to the output node of the compare circuit and a match input line and a match output line, the match circuit for selectively connecting the match input line to the match output line based on the compared signal; a discharge circuit coupled to ground; a precharge circuit coupled to a preset voltage; the discharge circuit or the precharge circuit coupled to the match input line of the same row or the match output line of the same row, wherein when all cells of the same row output a match, all the match input and output lines of the same row are either precharged or discharged. 
     Preferably, the compared circuit includes a pair of PMOS transistors and the match circuit includes a NMOS transistor. According to an alternative embodiment, the compare circuit includes a pair of NMOS transistors and the match circuit includes a PMOS transistor. 
     Preferably, the TCAM further includes a mask circuit coupled to the match circuit and the match input line and the match output line for masking the compared signal or for selectively connecting the match input line to the match output line based on a mask data. A memory controller is further included for providing operation mode to the CAM. 
     A method is also provided for operating a content addressable memory (CAM) having an array of cells arranged in rows and columns, comprising the steps of: storing in a main memory cell a data bit and its complement; comparing the data bit and its complement with signals at corresponding compare lines and outputting a compared signal; selectively connecting a match input line to a match output line based on an indication of a match from the compared signal to form a match line; and setting the match line at a first voltage level when all of memory cells of the same row are matched, wherein said first voltage is a ground voltage or a power supply voltage. 
     These and other aspects and features of the present invention will become more apparent from the fully detailed description of preferred embodiments when read in connection with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of a conventional TCAM cell. 
     FIG. 2A shows a voltage level of an internal node of the TCAM cell of FIG. 1 during a compare operation. 
     FIG. 2B shows voltage levels of internal nodes of the TCAM cell of FIG.  1 . 
     FIG. 3 is a block diagram of a ternary content addressable memory (TCAM) according to an embodiment of the present invention. 
     FIG. 4 is a circuit diagram of a TCAM cell in the TCAM shown in FIG.  3 . 
     FIG. 5 shows a voltage level of an internal node of the TCAM cell shown in FIG. 4 during a compare operation of the TCAM cell. 
     FIG. 6 is a circuit diagram of another embodiment of a TCAM cell in the TCAM shown in FIG.  3 . 
     FIG. 7 is a block diagram of a ternary content addressable memory (TCAM) according to another embodiment of the present invention. 
     FIG. 8 is a circuit diagram of a TCAM cell in the TCAM shown in FIG.  7 . 
     FIG. 9 is a circuit diagram of another embodiment of a TCAM cell in the TCAM shown in FIG.  7 . 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Referring to FIG. 3, a TCAM  100  according to the present invention includes an array  120  having a plurality of TCAM cells TCCij arranged in a matrix of rows and columns having ‘i’ rows and ‘j’ columns with i=0 to m and j=0 to n, m and n being natural integers. TCAM cells in each row are commonly coupled to the same wordline. For example, TCAM cells TCC 00 -TCC 0   n  in a first row are commonly coupled to a wordline WL 0 . TCAM cells TCC 10 -TCC 1   n  in a second row are commonly coupled to a wordline WL 1 . TCAM cells TCCm 0 -TCCmn in an mth row are commonly coupled to a wordline WLm. The wordlines WL 0 -WLm are coupled to a decoder  140 , which selectively drives the wordlines WL 0 -WLm based on an operation mode instruction from a memory controller (not shown). For example, the decoder  140  selectively drives one of the wordlines WL 0 -WLm when storing data information in TCAM cells of any row or reading out data information therefrom. In a case where comparand data bits (constituting a search word) are compared with data bits (constituting a word) stored in TCAM cells of each row, the decoder  140  does not select all the wordlines WL 0 -WLm at the same time. TCAM cells of each row are commonly coupled to a bitline pair, a mask line pair, and a compare line pair. For example, TCAM cells TCC 00 -TCCm 0  of a first column are commonly coupled to a bitline pair BL 0  and BL 0 B, a mask line pair ML 0  and ML 0 B, and a compare line pair CL 0  and CL 0 B. TCAM cells TCC 01 -TCCm 1  of a second column are commonly coupled to a bitline pair BL 1  and BL 1 B, a mask line pair ML 1  and ML 1 B, and a compare line pair CL 1  and CL 1 B. TCAM cells TCC 0   n -TCCm n of an nth column are commonly coupled to a bitline pair BLn and BLnB, a mask line pair MLn and MLnB, and a compare line pair CLn and CLnB. A bitline pair BLi and BLiB of each column is used for transmitting data to be stored/read out to/from TCAM cells in a corresponding column. A mask line pair MLi and MLiB of each column is used for transmitting mask data to be stored/read out to/from TCAM cells in a corresponding column. A compare line pair CLi and CLiB of each column is used for transmitting comparand data. 
     The TCAM cell  100  according to an embodiment of the present invention includes match lines MATCH 0 -MATCHm that correspond to rows or wordlines WL 0 -WLm, respectively. Each of the match lines MATCH 0 -MATCHm is divided into a plurality of match line segments. For example, a match line MATCH 0  of a first row is divided into match line segments MATCH 00  to MATCH 0   n+ 1. A match line MATCH 1  of a second row is divided into match line segments MATCH 10  to MATCH 1   n+ 1. A match line MATCHm of an mth row is divided into match line segments MATCHm 0  to MATCHmn+1. At each row, TCAM cells are coupled between adjacent match line segments, respectively. For example, a TCAM cell TCC 00  positioned at a first row and a first column is coupled between match line segments MATCH 00  and MATCH 01 . A TCAM cell TCC 01  positioned at the first row and a second column is coupled between match line segments MATCH 01  and MATCH 02 . A TCAM cell TCC 0   n  positioned at the first row and an nth column is coupled between match line segments MATCH 0   n  and MATCH 0   n+ 1. TCAM cells of the other rows are arranged the same as described above. 
     Discharge circuits  160 D 0 ,  106 D 1 , . . . , and  160 Dm are coupled to corresponding first match line segments MATCH 00 , MATCH 10 , . . . , and MATCHm 0 , each constituting match lines MATCH 0  to MATCHm, respectively. The discharge circuits  160 D 0 - 160 Dm electrically connect corresponding match line segments MATCH 00  to MATCHm 0  to a ground voltage, respectively for discharging the match lines. Precharge circuits  180 P 0 ,  180 P 1 , . . . , and  180 Pm are coupled to the last match line segments MATCH 0   n+ 1, MATCH 1   n+ 1, . . . , and MATCHmn+1, respectively. The precharge circuits  180 P 0 - 180 Pm electrically connect corresponding match line segments MATCH 0   n+ 1-MATCHmn+1 to a power supply voltage, respectively. The discharge circuits  160 D 0 - 160 Dm and the precharge circuits  180 P 0 - 180 Pm operate or selectively operate based on an operation mode, preferably from a memory controller (not shown). The last match line segments MATCH 0   n+ 1-MATCHmn+1 of all rows are coupled to a match circuit  200 , which generates an address corresponding to currently inputted comparand data in response to logic states of the match line segments MATCH 0   n+ 1-MATCHmn+1. 
     FIG. 4 shows a preferred embodiment of one TCAM cell, e.g., TCC 00 , shown in FIG.  3 . The TCAM cell includes a main memory cell and a mask memory cell. Although the main memory cell and the mask memory cell shown herein is an SRAM cell, it is apparent to one ordinary skilled in the art that other types of memory cells e.g., DRAM cell, FRAM cells, or the like can be used. 
     The main memory cell is coupled to a bitline pair BL 0  and BL 0 B, and includes two NMOS transistors T 10  and T 12  and two inverters INV 10  and INV 12 . When the stored data in the main memory cell is “0”, cell node CN 10  has a logic low level and cell node CN 12  has a logic high level. When the stored data in the main memory cell is “1”, the cell node CN 10  has a logic high level and the cell node CN 12  has a logic low level. The mask memory cell is coupled to a mask line pair ML 0  and MLB and a wordline WL 0 , and includes two NMOS transistors T 22  and T 24  and two inverters INV 14  and INV 16 . When the mask data stored in mask memory cell is “0”, cell node CN 14  has a logic low level and cell node CN 16  has a logic high level. When the stored mask data in mask memory cell is “1”, the cell node CN 14  has a logic high level and the cell node CN 16  has a logic low level. 
     The CAM cell TCC 00  further includes two PMOS transistors T 14  and T 16  and two NMOS transistors T 18  and T 20 . The PMOS transistor T 14  has a first electrode (drain or source) coupled to a complementary compare line CL 0 B, a second electrode (source or drain) coupled to an internal node DX, and a control electrode coupled to the cell node CN 10  of the main memory cell. The PMOS transistor T 16  has a first electrode (source or drain) coupled to a compare line CL 0 , a second electrode (drain or source) coupled to the internal node DX, and a control electrode coupled to the cell node CN 12  of the main memory cell. The PMOS transistors T 14  and T 16  constitute a detection circuit for detecting whether comparand data transmitted through a compare line pair is matched with data stored in the main memory cell. 
     The NMOS transistor T 18  has a first electrode (or source) coupled to a match line segment MATCH 00 , a second electrode (or drain) coupled to a match line segment MATCH 01 , and a control electrode coupled to the internal node DX. The NMOS transistor T 18  constitutes a match circuit that electrically connects the match segments MATCH 00  and MATCH 01  when the comparand data is matched with the data stored in the main memory cell. The NMOS transistor T 20  has a first electrode (or source) coupled to the match line segment MATCH 00 , a second electrode (or drain) coupled to the match line segment MATCH 01 , and a control electrode coupled to the cell node CN 16  of the mask memory cell. The NMOS transistor T 20  constitutes a mask circuit that electrically connects the match line segments MATCH 00  and MATCH 01  in response to the mask data stored in the mask memory cell. Although the main memory cell and the mask memory cell are coupled to the same wordline WL 0 , as shown in FIG. 4, it is apparent that the wordline may be separated into two wordline sections each for separately connecting to the main memory cell and the mask memory cell. 
     In the TCAM cell having the above-described structure, when the mask data is “0”, the TCAM cell TCC 00  is in an “X” or “don&#39;t care” state. When the mask data is “1”, the TCAM cell TCC 00  carries out a compare operation. More specifically, in the “X” state where the mask data is “0”, the cell node CN 14  of the mask memory cell has a logic low level and the cell node CN 16  thereof has a logic high level. In this case, the NMOS transistor T 20  is turned on and match line segments MATCH 00  and MATCH 01  are electrically connected to each other. This means the match line segments MATCH 00  and MATCH 01  are electrically connected to each other irrespective of the compare result of the comparand data with the data stored in the main memory cell. When the mask data is “1”, the cell node CN 14  of the mask memory cell has a logic high level and the cell node CN 16  thereof has a logic low level. In this case, the NMOS transistor T 20  is turned off. The match line segments MATCH 00  and MATCH 01  are electrically connected depending upon the compare result of the comparand data with the data stored in the main memory cell. 
     An exemplary compare function of the TCAM cell will now be described. When the stored data in the main memory cell is “0”, the cell node CN 10  of the main memory cell has a logic low level and the cell node CN 12  thereof has a logic high level. When the TCAM cell is not masked, the TCAM cell carries out a compare function. When the stored data in the main memory cell is “1”, the cell node CN 10  has a logic high level and the cell node CN 12  has a logic low level. A logic state of the internal node DX is determined depending on the compare result of the comparand data with the data stored in the main memory cell. As an illustration, when the stored data in the main memory cell is “0”, the PMOS transistor T 14  is turned on and the PMOS transistor T 16  is turned off. When “0” comparand data is transmitted through the compare line pair CL 0  and CL 0 B, a “1” data on the complementary compare line CL 0 B is transmitted to the internal node DX through the PMOS transistor T 14 . This causes the NMOS transistor T 18  to be turned on, and causes the match line segments MATCH 00  and MATCH 01  to be electrically connected to each other. On the other hand, when a “1” comparand data is transmitted through the compare line pair CL 0  and CL 0 B, a “0” data on the complementary compare line CL 0 B is transmitted to the internal node DX through the PMS transistor T 14 . This causes the NMOS transistor T 18  to be turned off, and the match line segments MATCH 00  and MATCH 01  are not electrically connected. 
     FIG. 5 shows a voltage level of an internal node of the TCAM cell shown in FIG. 4 during a compare operation of the TCAM cell. When the internal node DX is discharged, the voltage at DX is dropped to a threshold voltage Vtp14 or Vtp 16 of the PMOS transistor T 14  or T 16 . 
     When the data stored in the main memory is “1”, the PMOS transistor T 14  is turned off and the PMOS transistor T 16  is turned on. When a “0” comparand data is transmitted through the compare line pair CL 0  and CL 0 B, a “0” data on the compare line CL 0  is transmitted to the internal node DX through the PMOS transistor T 14 . This causes the NMOS transistor T 18  to be turned off, and causes the match line segments MATCH 00  and MATCH 01  to be electrically separated from each other. On the other hand, when a “1” compare data is transmitted through the compare line pair CL 0  and CL 0 B, a “1” data on the compare line CL 0  is transmitted to the internal node DX through the PMOS transistor T 14 . This causes the NMOS transistor T 18  to be turned on, and causes the match line segments MATCH 00  and MATCH 01  to be electrically connected to each other. Therefore, when comparand data is matched with data stored in the main memory cell, match line segments MATCH 00  and MATCH 01  are electrically connected to each other. On the other hand, when the comparand data is not matched therewith, the match line segments MATCH 00  and MATCH 01  are electrically separated from each other. At any row, when data bits stored in all the TCAM cells of the same row are matched with comparand data bits transmitted through corresponding compare line pairs, match line segments constituting a match line corresponding to the row are electrically connected to each other and to the corresponding discharge circuit  160  D[X]m. As a result, the match line corresponding to the row is substantially discharged to ground. 
     In the TCAM cell according to the invention, a first match line segment of each row is coupled to a ground voltage through a discharge circuit, and the last match line segment is coupled to a power supply voltage through a precharge circuit. The MATCH output in each row will be at the ‘precharge’ level or at ‘1’ unless there is a match from the compare of stored data of all TCAM cells in the same row, in which case the MATCH output is discharged to ‘0’. Accordingly, a logic state of a match line of each row is varied only when all data bits of each word are matched with comparand data bits. This means the logic state of the match line is varied with the same speed irrespective of the number of unmatched data bits of one word. 
     As previously discussed, in the convention TCAM cell structure shown in FIG. 1, if an operation voltage is dropped, the TCAM cell cannot perform a compare function. Advantageously, according to the first embodiment of the TCAM cell structure according to the present invention, a logic high level of a compare line CL 0  or a complementary compare line CL 0 B is transmitted to an internal node DX through a PMOS transistor T 14  or T 16 , without reduction of threshold voltage. Thus, the TCAM cell normally carries out a compare function even when an operation voltage is low, thereby improving reliability of the TCAM cell. Additionally, because the logic high level of the compare line CL 0  or the complementary compare line CL 0 B is transmitted to the internal node DX through the PMOS transistor T 14  or T 16  without reduction by threshold voltage, the driving capability of the NMOS transistor T 18  is improved. With improved driving capability, the NMOS transistor T 18  can be reduced in size. And, the overall density of the TCAM is higher. 
     Further, since the number of unmatched words is much greater than that of matched words, the conventional TCAM cell structure of FIG. 1 has a considerably higher power consumption because the logic state of a match line is varied when a mismatch arises. On the other hand, the TCAM structure according to the invention requires considerably less power consumption because a logic state of a match line is varied only when a match arises. FIG. 6 shows a circuit diagram of a TCAM cell shown according to another embodiment of the present invention. In FIG.  6  and FIG. 4, same numerals denote same components. A TCAM cell of FIG. 6 is substantially identical to the TCAM cell of FIG. 4 except that NMOS transistors T 26  and T 28  are added in the circuit of FIG.  6 . An NMOS transistor T 26  has a first electrode coupled to a complementary compare line CL 0 B, a second electrode coupled to an internal node DX, and a control electrode coupled to a cell node CN 12  of a main memory cell. An NMOS transistor T 28  has a first electrode coupled to a compare line CL 0 , a second electrode coupled to the internal node DX, and a control electrode coupled to a cell node CN 10  of the main memory cell. According to such a structure, a voltage of the internal node DX fully swings from a power supply voltage to a ground voltage. 
     FIG. 7 shows a block diagram of a content addressable memory (CAM) according to a second embodiment of the present invention is illustrated in FIG.  7 . In FIG.  7  and FIG. 3, same numerals denote same components. As shown in FIG. 7, a precharge circuit is coupled to a first match line segment of each row, and a discharge circuit is coupled to the last match line segment thereof. For example, a precharge circuit  180 P 0 ′ is coupled to a first match line segment MATCH 00  of a first row, and a discharge circuit  160 D 0 ′ is coupled to the last match line segment MATCH 0   n+ 1 thereof. A precharge circuit  180 P 1 ′ is coupled to a first match line segment MATCH 10  of a second row, and a discharge circuit  160 D 1 ′ is coupled to the last match line segment MATCH 1   n+ 1 thereof. A precharge circuit  180 Pm′ is coupled to a first match line segment MATCHm 0  of the last row, and a discharge circuit  160 Dm′ is coupled to the last match line segment MATCHmn+1 thereof. FIG. 8 is a circuit diagram of one preferred embodiment of the TCAM cell structure in the TCAM in FIG.  7 . Although a TCAM cell positioned at a first row and a first column is illustrated in FIG. 8, it will be understood that the other cells in the TCAM of FIG. 7 have the same structure. The TCAM cell TCC 00  according to this embodiment of the invention includes a main memory cell and a mask memory cell. Although an SRAM cell is shown as the main memory cell and the mask memory cell, it is apparent to one skilled in the art that other memory cells e.g., DRAM cell, FRAM cell, and the like can also be used. The main memory cell is coupled to a bitline pair BL 0  and BL 0 B and a wordline WL 0 , and includes two NMOS transistors T 30 , T 32  and two inverters INV 30  and INV 32 . When the stored data in the main memory is “0”, cell node CN 30  of the main memory cell has a logic low level and cell node CN 32  has a logic high level. When the data stored in the main memory cell is “1”, the cell node CN 30  of the main memory cell has a logic high level and the cell node CN 32  thereof has a logic low level. A mask memory cell is coupled to a mask line pair ML 0  and ML 0 B and the wordline WL 0 , and includes two NMOS transistors T 42  and T 44  and two inverters INV 34  and INV 36 . When the stored mask data in the mask memory cell is “0”, cell node CN 34  of the mask memory cell has a logic low level and cell node CN 36  has a logic high level. When the mask data in this mask memory cell is “1”, the cell node CN 34  of the mask memory cell has a logic high level and the cell node CN 36  has a logic low level. 
     The TCAM cell TCC 00  according to this embodiment of the invention further includes two NMOS transistors T 34  and T 36  and two PMOS transistors T 38  and T 40 . The NMOS transistor T 34  has a first electrode (source or drain) coupled to a complementary compare line CL 0 B, a second electrode (drain or source) coupled to an internal node DX, and a control electrode coupled to a cell node CN 30  of the main memory cell. The NMOS transistor T 36  has a first electrode (source or drain) coupled to the compare line CL 0 , a second electrode (drain or source) coupled to the internal node DX, and a control electrode coupled to a cell node CN 32  of the main memory cell. The NMOS transistors T 34  and T 36  constitute a detection circuit for detecting whether comparand data transmitted to a compare line pair is matched with data stored in a main memory cell. The PMOS transistor T 38  has a first electrode (or source) coupled to a match line segment MATCH 00 , a second electrode (or drain) coupled to a match line segment MATCH 01 , and a control electrode coupled to the internal node DX. The PMOS transistor T 38  constitutes a match circuit for electrically connecting the match line segments MATCH 00  and MATCH 01  to each other when the comparand data is matched with stored data. The PMOS transistor T 40  has a first electrode (or source) coupled to the match line segment MATCH 00 , a second electrode (or drain) coupled to the match line segment MATCH 01 , and a control electrode coupled to a cell node CN 34  of the mask memory cell. The PMOS transistor T 40  constitutes a mask circuit for electrically connecting the match line segments MATCH 00  and MATCH 01  to each other in response to mask data stored in the mask memory cell. 
     According to such a circuit structure, when mask data is “0”, the match line segments MATCH 00  and MATCH 01  are electrically connected to each other through the PMOS transistor P 40  irrespective of compare result. Thus, the match line segment MATCH 01  is charged to a power supply voltage from the precharge circuit  180 P 0 ′ (see FIG. 7) through the match line segment MATCH 00  and the PMOS transistor T 40 . When the mask data is “1”, the electrical connection thereof is determined depending on the compare result. When the comparand data is matched with the data stored in the main memory cell, a logic level of the internal node DX becomes substantially a ground voltage, turning on transistor T 38  to electrically connect the match line segments MATCH 00  and MATCH 01  to each other. On the other hand, when the comparand data is not matched therewith, the internal node DX is coupled to a signal line CL 0  or CL 0 B (at a high level) turning off transistor T 38  to electrically separate the match line segments MATCH 00  and MATCH 01  from each other. 
     FIG. 9 is a circuit diagram showing another TCAM cell in the TCAM shown in FIG.  7 . In FIG.  9  and FIG. 8, same numerals denote same components. The TCAM cell of FIG. 9 is substantially identical to the TCAM cell of FIG. 8, except that PMOS transistors T 46  and T 48  are added in FIG.  9 . The PMOS transistor T 46  has a first electrode coupled to a complementary compare line CL 0 B, a second electrode coupled to an internal node DX, and a control electrode coupled to a cell node CN 32  of a main memory cell. The PMOS transistor T 48  has a first electrode coupled to a compare line CL 0 , a second electrode coupled to the internal node DX, and a control electrode coupled to a cell node CN 30  of the main memory cell. According to such a structure, a voltage of the internal node DX fully swings from a power supply voltage to a ground voltage. Otherwise, the TCAM cell of FIG. 9 may operate and obtain the same effect as the TCAM cell of FIG.  8 . 
     As explained above, a ternary content addressable memory (TCAM) according to the embodiments of the present invention has a NAND-type match line structure, in which the level of a match line is changed, e.g., discharged/charged only when all data bits stored in TCAM cells of one word are matched with corresponding comparand data bits. This results in a reduction in power consumption and increased reliability and density. Transistors (e.g., T 14  and T 16  of FIG. 4) constituting a detection circuit are constructed to be complementary with a transistor (e.g., T 18  of FIG. 4) constituting a match circuit. 
     As a result, the TCAM cells according to embodiments of the invention are suitable for use in a high-density CAM and is stably operable at a low voltage. 
     While this invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.