Abstract:
A LED driving arrangement constituted of: a control circuitry; an inductance element having a primary side and a secondary side; the inductance element arranged, responsive to a switching circuit, to receive power at the primary side from a power source, and the inductance element further arranged, responsive to the received power at the primary side, to output at the secondary side a function of the received power; at least LED based luminaire; a parasitic capacitance between the at least one LED based luminaire and a chassis; and an electronically controlled switch coupled between the secondary side of the inductance element and the at least one LED based luminaire, wherein the electronically controlled switch and the secondary side of the inductance element and a discharge path of the parasitic capacitance are coupled in series.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application is a continuation-in-part of U.S. patent application Ser. No. 14/559,135, filed Dec. 3, 2014 and titled “MULTIPLE OUTPUT SYNCHRONOUS POWER CONVERTER”, which is a continuation-in-part of U.S. patent application Ser. No. 14/296,544, filed Jun. 5, 2014 and titled “SYNCHRONOUS REGULATION FOR LED STRING DRIVER”, which is a continuation of U.S. patent application Ser. No. 13/279,445, filed Oct. 24, 2011 and titled “SYNCHRONOUS REGULATION FOR LED STRING DRIVER”, which claims priority from U.S. provisional patent application 61/406,136, filed Oct. 24, 2010 and titled “SYNCHRONOUS REGULATION FOR LED STRING DRIVER”. U.S. patent application Ser. No. 14/559,135 further claims priority from U.S. provisional application 61/910,975, filed Dec. 3, 2013 and titled “MULTIPLE OUTPUT SYNCHRONOUS POWER CONVERTER”. The present application further claims priority from U.S. provisional patent application 62/137,377, filed Mar. 24, 2015 and titled “SYNCHRONOUSLY REGULATED LED DRIVE METHOD”. The entire contents of all of the above documents are incorporated herein by reference. 
    
    
     TECHNICAL FIELD 
     The present invention relates to the field of LED driving arrangement, and in particular to an LED driving arrangement with spike suppression. 
     BACKGROUND OF THE INVENTION 
     In liquid crystal display (LCD) TVs the power system needs to supply DC voltages for the electronic circuitry of the TV and further provide a controllable power to drive the light emitting diode (LED) backlight unit. A popular architecture presently used is to supply both the DC voltage and the LED power from a single power transformer, thus saving the cost of additional power transformers and the associated primary side drive stage. In such an approach the primary side power stage control is usually utilized to provide regulation for the main DC output voltage. In such an architecture, since the power supplied to the LED drive stage is thus not well regulated, a separate LED drive circuit has to be deployed to control the LED current as well as any dimming operation. A technique has been developed to drive the LED string(s) with a switching device with its one switching edge synchronized with the primary side switching action and regulate the LED current by modulating its conduction pulse width, as described in U.S. Pat. No. 8,779,686 issued Jul. 15, 2014 to Jin, to which the present application claims priority, the entire contents of which is incorporated herein by reference. 
       FIGS. 1 and 2  herein illustrate typical circuit examples of such a technique, with  FIG. 1  showing an application example with a fly back topology on the primary side, and  FIG. 2  showing a half bridge LLC topology on the primary side. In the example circuits illustrated in  FIGS. 1 and 2 , the energy storage capacitor, inductor and freewheel diode of a conventional secondary side buck or boost circuit are removed, hence yielding a significant cost savings. 
     Particularly,  FIG. 1  illustrates a high level schematic diagram of an LED driving arrangement  10  comprising: an inductance element  20 , illustrated and described herein as a transformer  20  and comprising a primary winding  30  and a secondary winding  40  magnetically coupled to primary winding  30 ; a switching circuit  50 , switching circuit  50  comprising a primary side electronically controlled switch Q 1 , illustrated and described herein as an n-channel metal-oxide-semiconductor field-effect-transistor (NFET) Q 1 ; a unidirectional electronic valve D 1 , illustrated and described herein as a diode D 1 ; a capacitive element C 1 , illustrated and described herein as a capacitor C 1 ; a secondary side electronically controlled switch Q 2 , illustrated and described herein as an NFET Q 2 ; an LED based luminaire  60 , illustrated and described herein as an LED string  60 ; and a control circuitry  70 . 
     A first end of primary winding  30  is coupled to a power lead and a second end of primary winding  30 , whose polarity is denoted with a dot, is coupled to the drain of NFET Q 1 . The source of NFET Q 1  is coupled to a return lead and the gate of NFET Q 1  is coupled to a respective output of control circuitry  70  (connection not showed). A first end of secondary winding  40 , whose polarity is denoted with a dot, is coupled to the anode of diode D 1  and the cathode of diode D 1  is coupled to a first end of capacitor C 1  and the anode end of LED string  60 . A second end of capacitor C 1  and the cathode end of LED string  60  are commonly coupled to the drain of NFET Q 2 . The gate of NFET Q 2  is coupled to a respective output of control circuitry  70  (connection not shown). The source of NFET Q 2  and the second end of secondary winding  40  are each coupled to a common potential. The common potential is further coupled to the metal chassis of a device. Further illustrated is the parasitic capacitance generated between LED string  60  and the metal chassis, the parasitic capacitance denoted CS. 
     In operation, control circuitry  70  is arranged to alternately switch NFET Q 1  between an open state and a closed state. When NFET Q 1  is in a closed state, transformer  20  is charged. When NFET Q 2  is opened, the charge of transformer  20  is output at secondary winding  40  due to the opposing polarities of primary winding  30  and secondary winding  40 . Control circuitry  70  is further arranged to alternately switch NFET Q 2  between an open state and a closed state in order to maintain a desired voltage across LED string  60 . When NFET Q 2  is in a closed state, the power output at secondary winding is provided to LED string  60  and capacitor C 1 . As a result, current flows through LED string  60  and light is emitted. When NFET Q 2  is in an open state there is no current path through LED string  60 . 
     This works well under many application circumstances. However, a particular issue occurs when LED string  60  bears a large parasitic capacitance CS and such parasitic capacitance is loaded to the regulating NFET Q 2 . As described above, parasitic capacitance CS exists between LED string  60  and the metal chassis when LED string  60  is installed tightly onto the metal chassis, in most occasions to utilize the metal chassis as a heat sink. When the ground of the LED drive circuit is connected to the metal chassis, as described above, the parasitic capacitance is loaded to the switching loop of NFET Q 2 . Particularly, when NFET Q 2  is opened parasitic capacitance CS is charged by the power output at secondary winding  40 , and no discharge path is provided. When NFET Q 2  is then closed, a current spike will occur due to the discharge of CS through LED string  60  and NFET Q 2 . This result is different from the charging of the LED string  60  current at turn on of NFET Q 2 , since at turn on edge the current rising rate dI/dt is limited by the inductance of secondary winding  40  of transformer  20 , whereas the discharge spike of parasitic capacitance CS shows a sharp wave shape due to the lack of dI/dt limiting element in the discharging path. This current spike may be sufficient to damage one or more of NFET Q 2  and LED string  60 . 
     Similarly,  FIG. 2  illustrates a high level schematic diagram of an LED driving arrangement  100  comprising: an inductance element  120 , illustrated and described herein as a transformer  120  and comprising a primary winding  130  and a secondary winding  140  magnetically coupled to primary winding  130 ; a switching circuit  150 , switching circuit  150  comprising a first primary side electronically controlled switch Q 3 , illustrated and described herein as an NFET Q 3  and a second primary side electronically controlled switch Q 4 , illustrated and described herein as an NFET Q 4 ; a capacitance element CX, illustrated and described herein as a capacitor CX; a unidirectional electronic valve D 2 , illustrated and described herein as a diode D 2 ; a unidirectional electronic valve D 3 , illustrated and described herein as a diode D 3 ; a capacitor C 1 ; an NFET Q 2 ; an LED string  60 ; and a control circuitry  160 . 
     The drain of NFET Q 3  is coupled to a power lead and the gate of NFET Q 3  is coupled to a respective output of control circuitry  160  (the connection not shown). The source of NFET Q 3  is coupled to the drain of NFET Q 4  and a first end of capacitor CX. A second end of capacitor CX is coupled to a first end of primary winding  130 . A second end of primary winding  130  is coupled to the source of NFET Q 4  and a return lead. The gate of NFET Q 3  and the gate of NFET Q 4  are each coupled to a respective output of control circuitry  160  (the connection not shown). 
     A first end of secondary winding  140  is coupled to the anode of diode D 2  and a second end of secondary winding  140  is coupled to the anode of diode D 3 . The cathodes of diode D 2  and diode D 3  are commonly coupled to the first end of capacitor C 1  and the anode end of LED string  60 . The second end of capacitor C 1  and the cathode end of LED string  60  are commonly coupled to the drain of NFET Q 2 . The gate of NFET Q 2  is coupled to a respective output of control circuitry  160 . The source of NFET Q 2  and a center tap of secondary winding  140  are each coupled to a common potential. The common potential is further coupled to the metal chassis, as described above in relation to LED driving arrangement  10 . Parasitic capacitance CS is further illustrated, between the anode end of LED string  60  and the metal chassis, as described above. 
     In operation, control circuitry  160  is arranged to alternately switch each of NFETs Q 3  and Q 4  between an open state and a closed state, with a dead time insertion, while ensuring that NFETs Q 3  and Q 4  are not both in a closed state contemporaneously. When NFET Q 3  is in a closed state, and NFET Q 4  is in an open state, primary winding  130  is charged in a first direction and a power is output from a first half of secondary winding  140  via diode D 2 . When NFET Q 4  is in a closed state, and NFET Q 3  is in an open state, primary winding  130  is charged in the opposite direction and a power is output from a second half of secondary winding  140  via diode D 3 . Capacitor CX is arranged to balance the charge of primary winding  130  during the cycle. 
     Control circuitry  160  is further arranged to alternately switch NFET Q 2  between an open state and a closed state in order to maintain a desired voltage across LED string  60 . As described above, when NFET Q 2  is in a closed state, the power output at secondary winding is provided to LED string  60  and capacitor C 1 , and parasitic capacitance CS is charged. As a result, current flows through LED string  60  and light is emitted. When NFET Q 2  is in an open state, parasitic capacitance CS is left charged, with no discharge path, as described above. Thus, when NFET Q 2  switches to a closed state, a current spike is created by the discharge of parasitic capacitance CS through the series path of LED string  60  and NFET Q 2 . This current spike may be sufficient to damage one or more of NFET Q 2  and LED string  60 . 
     What is desired, and not provided by the prior art, is an arrangement to reduce the effect of the parasitic capacitance in the switching operation that causes sharp discharging current spikes. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is a principal object of the present invention to overcome at least some of the disadvantages of the prior art. This is provided in one embodiment by an LED driving arrangement comprising: a control circuitry; an inductance element having a primary side and a secondary side; a switching circuit, the inductance element arranged, responsive to the switching circuit, to receive power at the primary side from a power source, and the inductance element further arranged, responsive to the received power at the primary side, to output at the secondary side a function of the received power; at least one LED based luminaire; a parasitic capacitance between the at least one LED based luminaire and a chassis; and an electronically controlled switch coupled between the secondary side of the inductance element and the at least one LED based luminaire, wherein the electronically controlled switch is arranged, responsive to the control circuitry, to alternately switch between an open state and a closed state, the at least one LED based luminaire arranged to receive the output power when the electronically controlled switch is in the closed state and not receive the output power when the electronically controlled switch is in the open state, and wherein the electronically controlled switch, the secondary side of the inductance element and a discharge path of said parasitic capacitance are coupled in series. 
     Additional features and advantages of the invention will become apparent from the following drawings and description. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a better understanding of the invention and to show how the same may be carried into effect, reference will now be made, purely by way of example, to the accompanying drawings in which like numerals designate corresponding elements or sections throughout. 
       With specific reference now to the drawings in detail, it is stressed that the particulars shown are by way of example and for purposes of illustrative discussion of the preferred embodiments of the present invention only, and are presented in the cause of providing what is believed to be the most useful and readily understood description of the principles and conceptual aspects of the invention. In this regard, no attempt is made to show structural details of the invention in more detail than is necessary for a fundamental understanding of the invention, the description taken with the drawings making apparent to those skilled in the art how the several forms of the invention may be embodied in practice. In the accompanying drawing: 
         FIG. 1  illustrates a high level schematic diagram of a prior art LED driving arrangement with a fly back arrangement on the primary side; 
         FIG. 2  illustrates a high level schematic diagram of a prior art LED driving arrangement with an LLC half bridge arrangement on the primary side; 
         FIG. 3A  illustrates a high level schematic diagram of a first embodiment of an LED driving arrangement for a single LED string with a fly back arrangement on the primary side and a synchronously driven NFET inserted between chassis ground and one winding end of the driving transformer secondary, according to certain embodiments; 
         FIG. 3B  illustrates various waveforms of a first embodiment of the operation of the LED driving arrangement of  FIG. 3A ; 
         FIG. 3C  illustrates various waveforms of a second embodiment of the operation of the LED driving arrangement of  FIG. 3A ; 
         FIG. 3D  illustrates a high level schematic diagram of a second embodiment of an LED driving arrangement for a single LED string with a fly back arrangement on the primary side and a synchronously driven NFET inserted between chassis ground and one winding end of the driving transformer secondary, according to certain embodiments; 
         FIG. 4A  illustrates a high level schematic diagram of an LED driving arrangement for a single LED string with a fly back arrangement on the primary side and a synchronously driven PFET inserted between one winding end of the driving transformer secondary and the anode end of the LED string, according to certain embodiments; 
         FIG. 4B  illustrates various waveforms of a first embodiment of the operation of the LED driving arrangement of  FIG. 4A ; 
         FIG. 4C  illustrates various waveforms of a second embodiment of the operation of the LED driving arrangement of  FIG. 4A ; 
         FIG. 5A  illustrates a high level schematic diagram of an LED driving arrangement for multiple LED strings with a fly back arrangement on the primary side, where a respective synchronously driven NFET is inserted between one winding end of the driving transformer secondary and the anode end of the respective LED string, according to certain embodiments; 
         FIG. 5B  illustrates various waveforms of the operation of the LED driving arrangement of  FIG. 5A ; 
         FIG. 6A  illustrates a high level schematic diagram of an LED driving arrangement for multiple LED strings with a fly back arrangement on the primary side, where a respective synchronously driven PFET is inserted between one winding end of the driving transformer secondary and the anode end of the respective LED string, according to certain embodiments; 
         FIG. 6B  illustrates various waveforms of the operation of the LED driving arrangement of  FIG. 6A ; 
         FIG. 7A  illustrates a high level schematic diagram of an LED driving arrangement for a single LED string with an LLC half bridge arrangement on the primary side and a synchronously driven NFET inserted between chassis ground and one winding end of the driving transformer secondary, according to certain embodiments; 
         FIG. 7B  illustrates various waveforms of the operation of the LED driving arrangement of  FIG. 7A ; 
         FIG. 8A  illustrates a high level schematic diagram of an LED driving arrangement for a single LED string with an LLC half bridge arrangement on the primary side and a synchronously driven PFET inserted between chassis ground and a center tap of the driving transformer secondary, according to certain embodiments; 
         FIG. 8B  illustrates various waveforms of the operation of the LED driving arrangement of  FIG. 8A ; 
         FIG. 9A  illustrates a high level schematic diagram of an LED driving arrangement for multiple LED strings with an LLC half bridge arrangement on the primary side, where a respective synchronously driven NFET is inserted between a respective winding end of the driving transformer secondary and the anode end of the respective LED string; 
         FIG. 9B  illustrates various waveforms of the operation of the LED driving arrangement of  FIG. 9A ; 
         FIG. 10A  illustrates a high level schematic diagram of an LED driving arrangement for multiple LED strings with an LLC half bridge arrangement on the primary side, where a respective synchronously driven PFET is inserted between a respective winding end of the driving transformer secondary and the anode end of the respective LED string, according to certain embodiments; 
         FIG. 10B  illustrates various waveforms of the operation of the LED driving arrangement of  FIG. 10A ; 
         FIG. 11A  illustrates a high level schematic diagram of an LED driving arrangement for multiple LED strings with an LLC half bridge arrangement on the primary side, where a respective synchronously driven NFET is inserted between a respective winding end of the driving transformer secondary and the anode end of the respective LED string, according to certain embodiments; 
         FIG. 11B  illustrates various waveforms of the operation of the LED driving arrangement of  FIG. 11A ; 
         FIG. 12A  illustrates a high level schematic diagram of an LED driving arrangement for multiple LED strings with an LLC half bridge arrangement on the primary side, where a respective synchronously driven NFET is inserted between a common potential and the cathode end of the respective LED string, according to certain embodiments; and 
         FIG. 12B  illustrates various waveforms of the operation of the LED driving arrangement of  FIG. 12A . 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Before explaining at least one embodiment of the invention in detail, it is to be understood that the invention is not limited in its application to the details of construction and the arrangement of the components set forth in the following description or illustrated in the drawings. The invention is applicable to other embodiments or of being practiced or carried out in various ways. Also, it is to be understood that the phraseology and terminology employed herein is for the purpose of description and should not be regarded as limiting. In particular, the term “coupled” as used herein is not meant to be limited to a direct connection, and allows for intermediary devices or components without limitation. 
       FIG. 3A  illustrates a high level schematic diagram of an LED driving arrangement  200 , according to certain embodiments. LED driving arrangement  200  comprises: an inductance element  220 , illustrated and described herein as a transformer  220  and comprising a primary winding  230 , a first secondary winding  240  and a second secondary winding  245 , each magnetically coupled to primary winding  230 ; an NFET Q 1 ; a diode D 1 ; a capacitor C 1 ; an NFET Q 2 ; an LED string  60 ; a unidirectional electronic valve D 4 , illustrated and described herein as a diode D 4 ; a capacitance element C 2 , illustrated and described herein as a capacitor C 2 ; and a control circuitry  250 . 
     A first end of primary winding  230  is coupled to a power lead and a second end of primary winding  230 , whose polarity is denoted with a dot, is coupled to the drain of NFET Q 1 . The source of NFET Q 1  is coupled to a return lead and the gate of NFET Q 1  is coupled to a respective output of control circuitry  250  (connection not showed), the signal at the gate of NFET Q 1  denoted VG 1 . A first end of first secondary winding  240 , whose voltage potential in relation to a common potential is denoted VS 2 , is coupled to the cathode of diode D 1  and the anode of diode D 1  is coupled to a first end of capacitor C 1  and the cathode end of LED string  60 . The parasitic capacitance CS of LED string  60  is further illustrated between the cathode end of LED string  60  and the metal chassis, as described above. A second end of capacitor C 1  and the anode end of LED string  60  are each coupled to the common potential, the common potential further coupled to a metal chassis. The second end of first secondary winding  240 , whose polarity is denoted with a dot, is coupled to the drain of NFET Q 2  and the gate of NFET Q 2  is coupled to a respective output of control circuitry  250  (connection not shown), the signal at the gate of NFET Q 2  denoted VG 2 . The source of NFET Q 2  is coupled to the common potential. The current of first secondary winding  40  is denoted I 1 . 
     A first end of second secondary winding  245 , whose polarity is denoted with a dot, is coupled to the anode of diode D 4  and the cathode of diode D 4  is coupled to a first end of capacitor C 2 , and to an output node denoted VO 1 . The second end of second secondary winding  245  and the second end of capacitor C 2  are coupled to the common potential. 
     A first embodiment of the operation of LED driving arrangement  200  will be described herein in relation to the waveform graphs of  FIG. 3B  where the x-axis represents time and the y-axis represents amplitude in arbitrary units. Particularly, signal VG 1  is illustrated by trace  260 , voltage VS 2  is illustrated by trace  270 , signal VG 2  is illustrated by trace  280  and the amplitude of current I 1  is illustrated by trace  290 . 
     At time T 1 , control circuitry  250  is arranged to output a high signal VG 1  to the gate of NFET Q 1 , thereby switching NFET Q 1  to a closed state. Primary winding  230  is thereby charged and voltage VS 2  rises, diodes D 1  and D 4  preventing power from being output at the respective secondary windings  240  and  245 . Signal VG 2  is low, thus NFET Q 2  is in an open state. Since diode D 1  is reverse biased to block current flow I 1  during the whole conduction period of NFET Q 1 , the turn on edge of NFET Q 2  can be deployed at any time point between T 1  and T 2  without affecting the regulation operation of NFET Q 2 . 
     At time T 2 , control circuitry  250  is arranged to output a low signal VG 1  and a high signal VG 2 , thereby opening NFET Q 1  and closing NFET Q 2 . Voltage VS 2  thus becomes negative in relation to the common potential and diodes D 1  and D 4  are forward biased and are able to conduct. Additionally, closed NFET Q 2  provides a path for current I 1  which rises and causes LED string  60  to output light. 
     When regulating NFET Q 2  is turned on, the currents flowing through LED string  60 , smoothing capacitor C 1 , and the parasitic capacitance CS are merged at the source of NFET Q 2 . These currents, including the current through the parasitic capacitance CS, which form current I 1 , all flow through NFET Q 2  and first secondary winding  240 . Because of the existence of secondary winding  240  of transformer  220  in the current flowing loop, the dI/dt of these currents are all limited by the inductance of first secondary winding  240 . Thus, with the dI/dt limiting function caused by the inductance of first secondary winding  240 , the sharp discharging current spike of parasitic capacitance CS is effectively eliminated, and instead a smooth decline towards the normal operating current of I 1  is shown. In further explanation, NFET Q 2 , secondary winding  240  and a discharge path of parasitic capacitance CS are advantageously coupled in series, thus preventing any current spike. In one embodiment, the position of diode D 1  can also be changed, with its cathode connected to the drain of NFET Q 2  and the anode connected to the dotted terminal of first secondary winding  240 . 
     At time T 3 , control circuitry  250  is arranged to output a low signal VG 2  thereby switching NFET Q 2  into an open state and ceasing current flow I 1  through LED string  60  in accordance with the desired luminance output of LED string  60 . At time T 4 , NFET Q 1  is closed, as described above in relation to time T 1 . 
     At time T 2 , power is also output by second secondary winding  245  to output VO 1 . In one embodiment (now shown), a feedback loop is provided to control the duty cycle of NFET Q 1  so as to maintain the voltage of output VO 1  at a predetermined value. 
     A second embodiment of the operation of LED driving arrangement  200  will be described herein in relation to the waveform graphs of  FIG. 3C  where the x-axis represents time and the y-axis represents amplitude in arbitrary units. Particularly, signal VG 1  is illustrated by trace  260 , voltage VS 2  is illustrated by trace  270 , signal VG 2  is illustrated by trace  280  and the amplitude of current I 1  is illustrated by trace  290 . At time T 1 , control circuitry  250  is arranged to output a high signal VG 1  to the gate of NFET Q 1 , thereby switching NFET Q 1  to a closed state. Primary winding  230  is thereby charged and voltage VS 2  rises, diodes D 1  and D 4  preventing power from being output at the respective secondary windings  240  and  245 . Control circuitry  250  is further arranged to output a high signal VG 2 , thus NFET Q 2  is in a closed state, however due to the polarity of diode D 1  current I 1  remains zero. 
     At time T 2 , control circuitry  250  is arranged to output a low signal VG 1 , thereby opening NFET Q 1 . Voltage VS 2  thus becomes negative and diodes D 1  and D 4  are forward biased and begin to conduct, as described above. 
     As described above, the currents flowing through LED string  60 , smoothing capacitor C 1 , and the parasitic capacitance CS are merged at the source of NFET Q 2 . These currents, including the current through the parasitic capacitance CS, which form current I 1 , all flow through NFET Q 2  and first secondary winding  240 . Because of the existence of secondary winding  240  of transformer  220  in the current flowing loop, the dI/dt of these currents are all limited by the inductance of first secondary winding  240 . Thus, with the dI/dt limiting function by the inductance of first secondary winding  240 , the sharp discharging current spike of parasitic capacitance CS is effectively eliminated, resulting instead in a smooth decline towards the normal operating current of I 1 , as shown. 
     At time T 3 , control circuitry  250  is arranged to output a low signal VG 2  thereby switching NFET Q 2  into an open state and ceasing current flow through LED string  60  in accordance with the desired luminance output of LED string  60 . At time T 4 , NFET Q 1  is closed and NFET Q 2  is opened, as described above in relation to time T 1 . 
       FIG. 3D  illustrates a high level schematic diagram of an LED driving arrangement  295 , according to certain embodiments. The construction and operation of LED driving arrangement  295  is in all respects similar to the construction and operation of LED driving arrangement  200 , with the exception that second secondary winding  245  is not provided, and in the interest of brevity will not be further described. Control of the primary winding switching timing is then accomplished responsive to a voltage detected across a secondary winding, or across the LED string  60 . 
       FIG. 4A  illustrates a high level schematic diagram of an LED driving arrangement  300 . LED driving arrangement  300  is in all respects similar to LED driving arrangement  200 , with the exception that NFET Q 2  is replaced with a p-channel metal-oxide-semiconductor field-effect-transistor (PFET) Q 5 . Additionally, diode D 1 , LED string  60  and the polarity of first secondary winding  240  are reversed. Particularly, the first end of first secondary winding  240 , whose polarity is denoted with a dot, is coupled to the anode of diode D 1  and the cathode of diode D 1  is coupled to the first end of capacitor C 1  and the anode end of LED string  60 . The second end of first secondary winding  240  is coupled to the drain of PFET Q 5  and the gate of PFET Q 5  is coupled to a respective output of control circuitry  250  (connection not shown), the signal on the gate of PFET Q 5  denoted VG 5 . The source of PFET Q 5 , the second end of capacitor C 1  and the cathode end of LED string  60  are each coupled to the common potential, as described above. The parasitic capacitance CS of LED string  60  is further illustrated between the anode end of LED string  60  and the metal chassis, as described above. As will be described below, the current flows in the opposite direction of current I 1 , and is thus denoted  12 . 
     A first embodiment of the operation of LED driving arrangement  300  will be described herein in relation to the waveform graphs of  FIG. 4B  where the x-axis represents time and the y-axis represents amplitude in arbitrary units. Particularly, signal VG 1  is illustrated by trace  260 , voltage VS 2  is illustrated by trace  270 , signal VG 5  is illustrated by trace  310  and the amplitude of current I 1  is illustrated by trace  290 . At time T 1 , control circuitry  250  is arranged to output a high signal VG 1  to the gate of NFET Q 1 , thereby switching NFET Q 1  to a closed state. Primary winding  230  is thereby charged and voltage VS 2  becomes negative, diodes D 1  and D 4  preventing power from being output at the respective secondary windings  240  and  245 . Signal VG 5  is high, thus PFET Q 5  is in an open state. Since diode D 1  is reverse biased to block current flow  12  during the whole conduction period of NFET Q 1 , the turn on edge of PFET Q 5  can be deployed at any time point between T 1  and T 2  without affecting the regulation operation of PFET Q 5 . 
     At time T 2 , control circuitry  250  is arranged to output a low signal VG 1  and a low signal VG 5 , thereby opening NFET Q 1  and closing PFET Q 5 . Voltage VS 2  thus becomes positive and diodes D 1  and D 4  are forward biased and are able to conduct. Additionally, closed PFET Q 5  provides a path for current I 2  which rises and causes LED string  60  to output light. 
     When PFET Q 5  is turned on, the currents flowing through LED string  60 , smoothing capacitor C 1 , and the parasitic capacitance CS are merged to form current I 2 , which flows through PFET Q 5  and first secondary winding  240 . Because of the existence of secondary winding  240  of transformer  220  in the current flowing loop, the dI/dt of these currents are all limited by the inductance of first secondary winding  240 , as described above. Thus, with the dI/dt limiting function by the inductance of first secondary winding  240 , the sharp discharging current spike of parasitic capacitance CS is effectively eliminated resulting instead in a smooth decline towards the normal operating current of I 1  is shown. In one embodiment, the position of diode D 1  can also be changed, with its anode connected to the drain of PFET Q 5  and the cathode connected to the second end of first secondary winding  240 . 
     At time T 3 , control circuitry  250  is arranged to output a high signal VG 5  thereby switching PFET Q 5  into an open state and ceasing current flow through LED string  60  in accordance with the desired luminance output of LED string  60 . At time T 4 , NFET Q 1  is closed, as described above in relation to time T 1 . 
     At time T 2 , power is also output by second secondary winding  245  to output VO 1 . In one embodiment (now shown), a feedback loop is provided to control the duty cycle of NFET Q 1  so as to maintain the voltage of output VO 1  at a predetermined value. 
     A second embodiment of the operation of LED driving arrangement  200  is illustrated in the waveform graphs of  FIG. 4C  where the x-axis represents time and the y-axis represents amplitude in arbitrary units. Particularly, signal VG 1  is illustrated by trace  260 , voltage VS 2  is illustrated by trace  270 , signal VG 5  is illustrated by trace  310  and the amplitude of current I 1  is illustrated by trace  290 . The waveforms of  FIG. 4C  is similar to the waveforms of  FIG. 4B  with the exception that VG 5  is switched to low at time T 1 . As described above in relation to  FIG. 3C , similar to NFET Q 2 , PFET Q 5  can be switched at any point during the cycle of NFET Q 1  without affecting current I 2 . 
       FIG. 5A  illustrates a high level schematic diagram of a LED driving arrangement  400 . LED driving arrangement  400  comprises: a transformer  220 , comprising a primary winding  230 , a first secondary winding  240  and a second secondary winding  245 , each magnetically coupled to primary winding  240 ; an NFET Q 1 ; a pair of diodes D 1 ; a diode D 4 ; a pair of NFETs Q 2 ; a pair of capacitors C 1 ; a capacitor C 2 ; a pair of LED strings  60 ; and a control circuitry  410 . 
     A first end of primary winding  230  is coupled to a power lead and a second end of primary winding  230 , whose polarity is denoted with a dot, is coupled to the drain of NFET Q 1 . The source of NFET Q 1  is coupled to a return lead and the gate of NFET Q 1  is coupled to a respective output of control circuitry  250  (connection not showed), the signal at the gate of NFET Q 1  denoted VG 1 . 
     A first end of first secondary winding  240 , whose polarity is denoted by a dot, is coupled to the anode of each diode D 1  and the cathode of each diode D 1  is coupled to the drain of a respective NFET Q 2 . The gate of a first NFET Q 2  is coupled to a respective output of control circuitry  410  (connection not shown), the signal at the gate of first NFET Q 2  denoted VG 2 A, and the gate of a second NFET Q 2  is coupled to a respective output of control circuitry  410  (connection not shown), the signal at the gate of second NFET Q 2  denoted VG 2 B. The source of each NFET Q 2  is coupled to a first end of a respective capacitor C 1  and the anode end of a respective LED string  60 . A second end of each capacitor C 1  and the cathode end of each LED string  60  are each coupled to a common potential, which is further connected to a metal chassis. The second end of first primary winding  240  is coupled to the common potential. The parasitic capacitance CS of each LED string  60  is further illustrated between the anode end of the respective LED string  60  and the metal chassis, as described above. 
     A first end of second secondary winding  245 , whose polarity is denoted with a dot, is coupled to the anode of diode D 4  and the cathode of diode D 4  is coupled to a first end of capacitor C 2 , and to an output node denoted VO 1 . The second end of second secondary winding  45  and the second end of capacitor C 2  are coupled to the common potential. 
     The operation of LED driving arrangement  400  will be described herein in relation to the waveform graphs of  FIG. 5B  where the x-axis represents time and the y-axis represents amplitude in arbitrary units. Particularly, signal VG 1  is illustrated by trace  260 , voltage VS 2  is illustrated by trace  270 , signal VG 2 A is illustrated by trace  420  and signal VG 2 B is illustrated by trace  430 . At time T 1 , control circuitry  410  is arranged to output a high signal VG 1  to the gate of NFET Q 1 , thereby switching NFET Q 1  to a closed state. Primary winding  230  is thereby charged and voltage VS 2  becomes negative, diodes D 1  and D 4  preventing power from being output at the respective secondary windings  240  and  245 . Control circuitry  410  is further arranged to output high signals VG 2 A and VG 2 B, thereby closing both NFETs Q 2 , however as indicated above due to the polarity of diodes D 1  no current flows through LED strings  60 . 
     At time T 2 , control circuitry  250  is arranged to output a low signal VG 1  thereby opening NFET Q 1 . Voltage VS 2  thus becomes positive and diodes D 1  and D 4  are forward biased and are able to conduct. As described above, the current through each parasitic capacitance flows through first secondary winding  240 , the dI/dt limiting function of first secondary winding  240  effectively eliminating the sharp discharging current spike of parasitic capacitances CS. 
     At time T 3 , control circuitry  410  is arranged to output a low signal VG 2 A thereby switching the respective NFET Q 2  into an open state and ceasing current flow through the respective LED string  60  in accordance with the desired luminance output of LED string  60 . At time T 4 , control circuitry  410  is arranged to output a low signal VG 2 B thereby switching the respective NFET Q 2  into an open state and ceasing current flow through the respective LED string  60  in accordance with the desired luminance output of LED string  60 . At time T 5 , NFET Q 1  is closed, as described above in relation to time T 1 . 
     At time T 2 , power is also output by second secondary winding  245  to output VO 1 . In one embodiment (now shown), a feedback loop is provided to control the duty cycle of NFET Q 1  so as to maintain the voltage of output VO 1  at a predetermined value. 
       FIG. 6A  illustrates a high level schematic diagram of an LED driving arrangement  500 , according to certain embodiments. LED driving arrangement  500  is in all respects similar to LED driving arrangement  400 , with the exception that each NFET Q 2  is replaced with a PFET Q 5 . Additionally, diodes D 1 , LED strings  60  and the polarity of first secondary winding  240  are reversed. Particularly, the first end of first secondary winding  240  is coupled to the cathode of each diode D 1  and the anode of each diode D 1  is coupled to the drain of a respective PFET Q 5 . The source of each PFET Q 5  is coupled to the first end of a respective capacitor C 1  and the cathode end of a respective LED string  60 . The gate of each PFET Q 5  is coupled to a respective output of control circuitry  410  (the connection not shown), the signal on the gate of PFET Q 5  denoted VG 5 A and VG 5 B, respectively. The second end of first secondary winding  240 , whose polarity is denoted with a dot, is coupled to the common potential. Similarly, the anode end of each LED string  60  and the second end of each capacitor C 1  are each coupled to the common potential. The parasitic capacitance CS of each LED string  60  is further illustrated between the cathode end of the respective LED string  60  and the metal chassis, as described above. 
     The operation of LED driving arrangement  500  will be described herein in relation to the waveform graphs of  FIG. 6B  where the x-axis represents time and the y-axis represents amplitude in arbitrary units. Particularly, signal VG 1  is illustrated by trace  260 , voltage VS 2  is illustrated by trace  270 , signal VG 5 A is illustrated by trace  510  and signal VG 5 B is illustrated by trace  520 . At time T 1 , control circuitry  410  is arranged to output a high signal VG 1  to the gate of NFET Q 1 , thereby switching NFET Q 1  to a closed state. Primary winding  230  is thereby charged and voltage VS 2  rises, diodes D 1  and D 4  preventing current flow from the respective secondary windings  240  and  245 . Control circuitry  410  is further arranged to output low signals VG 5 A and VG 5 B, thereby closing both PFETs Q 5 , however due to the polarity of diodes D 1  no current flow occurs through LED strings  60 . 
     At time T 2 , control circuitry  250  is arranged to output a low signal VG 1  thereby opening NFET Q 1 . Voltage VS 2  thus becomes negative and diodes D 1  and D 4  are forward biased and are able to conduct. As described above, the current through each parasitic capacitance CS flows through first secondary winding  240 , the dI/dt limiting function of first secondary winding  240  effectively eliminating the sharp discharging current spike of parasitic capacitances CS. 
     At time T 3 , control circuitry  410  is arranged to output a high signal VG 5 A thereby switching the respective PFET Q 5  into an open state and ceasing current flow through the respective LED string  60  in accordance with the desired luminance output of LED string  60 . At time T 4 , control circuitry  410  is arranged to output a high signal VG 5 B thereby switching the respective NFET Q 2  into an open state and ceasing current flow through the respective LED string  60  in accordance with the desired luminance output of LED string  60 . At time T 5 , NFET Q 1  is closed, as described above in relation to time T 1 . 
     At time T 2 , power is also output by second secondary winding  245  to output VO 1 . In one embodiment (now shown), a feedback loop is provided to control the duty cycle of NFET Q 1  so as to maintain the voltage of output VO 1  at a predetermined value. 
       FIG. 7A  illustrates a high level schematic diagram of an LED driving arrangement  600 , according to certain embodiments. LED driving arrangement  600  comprises: an inductance element  620 , illustrated and described herein as a transformer  620  and comprising a primary winding  630 , a first secondary winding  640  and a second secondary winding  645 , each magnetically coupled to primary winding  630 ; a switching circuit  650 , switching circuit  650  comprising an NFET Q 3  and an NFET Q 4 ; a capacitor CX; a diode D 2 ; a diode D 3 ; a capacitor C 1 ; an NFET Q 2 ; an LED string  60 ; a unidirectional electronic valve D 5 , illustrated and described herein as a diode D 5 ; a unidirectional electronic valve D 6 , illustrated and described herein as a diode D 6 ; a capacitor C 2 ; and a control circuitry  660 . 
     The drain of NFET Q 3  is coupled to a power lead and the gate of NFET Q 3  is coupled to a respective output of control circuitry  660  (the connection not shown), the signal at the gate of NFET Q 3  denoted VG 1 A. The source of NFET Q 3  is coupled to the drain of NFET Q 4  and a first end of capacitor CX. A second end of capacitor CX is coupled to a first end of primary winding  630 . A second end of primary winding  630  is coupled to the source of NFET Q 4  and a return lead. The gate of NFET Q 4  is coupled to a respective output of control circuitry  660  (the connection not shown), the signal at the gate of NFET Q 4  denoted VG 1 B. 
     A first end of first secondary winding  640  is coupled to the cathode of diode D 2  and a second end of first secondary winding  640  is coupled to the cathode of diode D 3 . The anodes of diode D 2  and diode D 3  are commonly coupled to the first end of capacitor C 1  and the cathode end of LED string  60 . The second end of capacitor C 1  and the anode end of LED string  60  are each coupled to a common potential, the common potential further coupled to a metal chassis. A center tap of first secondary winding  640  is coupled to the drain of NFET Q 2  and the source of NFET Q 2  is coupled to the common potential. The gate of NFET Q 2  is coupled to a respective output of control circuitry  660  (connection not shown), the signal at the gate of NFET Q 2  denoted VG 2 . Parasitic capacitance CS is further illustrated, between the cathode end of LED string  60  and the metal chassis, as described above. 
     A first end of second secondary winding  645  is coupled to the anode of diode D 5  and a second end of second secondary winding  645  is coupled to the anode of diode D 6 . The cathodes of diodes D 5  and D 6  are commonly coupled to a first end of capacitor C 2 , and to an output node denoted VO 1 . A second end of capacitor C 2  and a center tap of second secondary winding  645  are each coupled to the common potential. 
     The operation of LED driving arrangement  600  will be described herein in relation to the waveform graphs of  FIG. 7B  where the x-axis represents time and the y-axis represents amplitude in arbitrary units. Particularly, signal VG 1 A is illustrated by trace  670 , signal VG 1 B is illustrated by trace  680 , voltage VS 2  is illustrated by trace  690  and signal VG 2  is illustrated by trace  695 . 
     At time T 1 , control circuitry  660  is arranged to output a high signal VG 1 A and a low signal VG 1 B, thereby closing NFET Q 3  and opening NFET Q 4 . As a result, primary winding  630  is charged and voltage VS 2  rises. At time T 2 , control circuitry  660  is arranged to output a high signal VG 2 , thereby closing NFET Q 2  and allowing current to flow through LED string  60  via diode D 3 . 
     The parasitic capacitance CS is shunted in parallel with LED string  60  and capacitor C 1 . Thus, when NFET Q 2  is turned on, the currents flowing through LED string  60 , capacitor C 1  and parasitic capacitance CS are merged at the source of NFET Q 2 . These currents, including the current through parasitic capacitance CS all flow through NFET Q 2  and first secondary winding  640 . Because of the existence of first secondary winding  640  of transformer  620  in the current flowing loop, the dI/dt of these currents are all limited by the inductance of first secondary winding  640 . Thus, with the dI/dt limiting function provided by the winding inductance, the sharp discharging current spike of parasitic capacitance CS is effectively eliminated. 
     At time T 3 , control circuitry  660  is arranged to output a low signal VG 1 A, thereby opening NFET Q 3  and causing voltage VS 2  to fall to zero. Additionally, control circuitry  660  is arranged to output a low signal VG 2 , thereby opening NFET Q 2 . Synchronizing the turn off edge of NFET Q 2  with the zero value of voltage VS 2  minimizes the turn off loss of NFET Q 2 . In fact, voltage VS 2  stays at zero during the dead time period between T 3  and T 4 , and the turn off edge of NFET Q 2  can be deployed at any time point between T 3  and T 4 . The current of LED string  60  is regulated by the on time of NFET Q 2  between T 2  and T 3 . At time T 4 , control circuitry  660  is arranged to output a high signal VG 1 B, thereby closing NFET Q 4  and causing voltage VS 2  to become negative, which will allow the second half of the cycle through diode D 2 , which for brevity will not be detailed. 
       FIG. 8A  illustrates a high level schematic diagram of an LED driving arrangement  700 , according to certain embodiments. LED driving arrangement  700  is in all respects similar to LED driving arrangement  600 , with the exception that NFET Q 2  is replaced with a PFET Q 5 . Additionally, the polarities of diodes D 2 , D 3  and LED string  60  are reversed. Particularly, the first end of first secondary winding  640  is coupled to the anode of diode D 2  and the second end of first secondary winding  640  is coupled to the anode of diode D 3 . The cathodes of diodes D 2  and D 3  are commonly coupled to the first end of capacitor C 1  and the anode end of LED string  60 . The center tap of first secondary winding  640  is coupled to the drain of PFET Q 5  and the source of PFET Q 5  is coupled to the common potential. Additionally, the second end of capacitor C 1  and the cathode end of LED string  60  are each coupled to the common potential. The gate of PFET Q 5  is coupled to a respective output of control circuitry  660  (connection not shown), the signal at the gate of PFET Q 5  denoted VG 5 . 
     The operation of LED driving arrangement  700  will be described herein in relation to the waveform graphs of  FIG. 8B  where the x-axis represents time and the y-axis represents amplitude in arbitrary units. Particularly, signal VG 1 A is illustrated by trace  670 , signal VG 1 B is illustrated by trace  680 , voltage VS 2  is illustrated by trace  690  and signal VG 5  is illustrated by trace  710 . 
     At time T 1 , control circuitry  660  is arranged to output a high signal VG 1 A and a low signal VG 1 B, thereby closing NFET Q 3  and opening NFET Q 4 . As a result, primary winding  630  is charged and voltage VS 2  rises. At time T 2 , control circuitry  660  is arranged to output a low signal VG 5 , thereby closing PFET Q 5  and allowing current to flow through LED string  60  via diode D 2 . 
     The parasitic capacitance CS is shunted in parallel with LED string  60  and capacitor C 1 . Thus, when PFET Q 5  is turned on, the currents flowing through LED string  60 , capacitor C 1  and parasitic capacitance CS are merged at the source of PFET Q 5 . These currents, including the current through parasitic capacitance CS all flow through PFET Q 5  and first secondary winding  640 . Because of the existence of first secondary winding  640  of transformer  620  in the current flowing loop, the dI/dt of these currents are all limited by the leakage inductance of first secondary winding  640 . Thus, with the dI/dt limiting function by the winding leakage inductance, the sharp discharging current spike of parasitic capacitance CS is effectively eliminated. 
     At time T 3 , control circuitry  660  is arranged to output a low signal VG 1 A, thereby opening NFET Q 3  and causing voltage VS 2  to fall to zero. Additionally, control circuitry  660  is arranged to output a high signal VG 5 , thereby opening NFET Q 2 . Synchronizing the turn off edge of PFET Q 5  with the zero value of voltage VS 2  minimizes the turn off loss of PFET Q 5 . At time T 4 , control circuitry  660  is arranged to output a high signal VG 1 B, thereby closing NFET Q 4  and causing voltage VS 2  to become negative, which will allow the second half of the cycle through diode D 3 , which for brevity will not be detailed. 
       FIG. 9A  illustrates a high level schematic diagram of an LED driving arrangement  800 . LED driving arrangement  800  comprises: a transformer  620  comprising a primary winding  630 , a first secondary winding  640  and a second secondary winding  645 , each magnetically coupled to primary winding  630 ; a switching circuit  650 , switching circuit  650  comprising an NFET Q 3  and an NFET Q 4 ; a capacitor CX; a pair of diodes D 1 ; a diode D 2 ; a diode D 3 ; a capacitor C 1 ; a pair of NFETs Q 2 ; a pair of LED strings  60 ; a diode D 5 ; a diode D 6 ; a capacitor C 2 ; and a control circuitry  810 . 
     The drain of NFET Q 3  is coupled to a power lead and the gate of NFET Q 3  is coupled to a respective output of control circuitry  810  (the connection not shown), the signal at the gate of NFET Q 3  denoted VG 1 A. The source of NFET Q 3  is coupled to the drain of NFET Q 4  and a first end of capacitor CX. A second end of capacitor CX is coupled to a first end of primary winding  630 . A second end of primary winding  630  is coupled to the source of NFET Q 4  and a return lead. The gate of NFET Q 4  is coupled to a respective output of control circuitry  810  (the connection not shown), the signal at the gate of NFET Q 4  denoted VG 1 B. 
     A first end of first secondary winding  640  is coupled to the anode of diode D 2  and a second end of first secondary winding  640  is coupled to the anode of diode D 3 . The cathodes of diode D 2  and diode D 3  are commonly coupled to the anodes of diodes D 1 . The cathode of each diode D 1  is coupled to the drain of the respective NFET Q 2 . The gate of a first NFET Q 2  is coupled to a respective output of control circuitry  810  (connection not shown), the signal at the gate of NFET Q 2  denoted VG 2 A, and the gate of a second NFET Q 2  is coupled to a respective output of control circuitry  810  (connection not shown), the signal at the gate of NFET Q 3  denoted VG 2 B. The source of each NFET Q 2  is coupled to a first end of a respective capacitor C 1  and the anode end of a respective LED string  60 . A second end of each capacitor C 1  and the cathode end of each LED string  60  are each coupled to a common potential, which is further connected to a metal chassis. A center tap of first primary winding  640  is coupled to the common potential. The parasitic capacitance CS of each LED string  60  is further illustrated, between the anode end of the respective LED string  60  and the metal chassis, as described above. 
     A first end of second secondary winding  645  is coupled to the anode of diode D 5  and a second end of second secondary winding  645  is coupled to the anode of diode D 6 . The cathodes of diodes D 5  and D 6  are commonly coupled to a first end of capacitor C 2 , and an output node denoted VO 1 . A second end of capacitor C 2  and a center tap of second secondary winding  645  are each coupled to the common potential. 
     The operation of LED driving arrangement  800  will be described herein in relation to the waveform graphs of  FIG. 9B  where the x-axis represents time and the y-axis represents amplitude in arbitrary units. Particularly, signal VG 1 A is illustrated by trace  670 , signal VG 1 B is illustrated by trace  680 , voltage VS 2  is illustrated by trace  690 , signal VG 2 A is illustrated by trace  820  and signal VG 2 B is illustrated by trace  830 . 
     At time T 1 , control circuitry  810  is arranged to output a high signal VG 1 A and a low signal VG 1 B, thereby closing NFET Q 3  and opening NFET Q 4 . As a result, primary winding  630  is charged and voltage VS 2  rises. At time T 2 , control circuitry  810  is arranged to output a high signal VG 2 A, thereby closing the respective NFET Q 2  and generating current through the respective LED string  60 . At time T 3 , control circuitry  810  is arranged to output a high signal VG 2 B, thereby closing the respective NFET Q 2  and generating current through the respective LED string  60 . As described above, the current through each parasitic capacitance CS flows through first secondary winding  640 , the dI/dt limiting function of first secondary winding  640  effectively eliminating the sharp discharging current spike of parasitic capacitances CS. 
     At time T 4 , control circuitry  810  is arranged to output a low signal VG 1 A, thereby opening NFET Q 3 . As a result, voltage VS 2  drops to zero. Additionally, control circuitry  810  is arranged to output low signals VG 2 A and VG 2 B, thereby opening NFETs Q 2 . Synchronizing the turn off edge of NFETs Q 2  with the zero value of voltage VS 2  minimizes the turn off loss of NFETs Q 2 . 
     At time T 5 , control circuitry  810  is arranged to output a high signal VG 1 B, thereby closing NFET Q 4 . As a result, voltage VS 2  is negative and diode D 3  is forward biased, which begins the second half of the cycle where current flows through diode D 3 , which in the interest of brevity will not be detailed. 
     At time T 1 , power is also output by second secondary winding  645  to output VO 1 . In one embodiment (now shown), a feedback loop is provided to control the duty cycle of NFET Q 1  so as to maintain the voltage of output VO 1  at a predetermined value. 
       FIG. 10A  illustrates a high level schematic diagram of an LED driving arrangement  900 , according to certain embodiments. LED driving arrangement  900  is in all respects similar to LED driving arrangement  800 , with the exception that NFETs Q 2  are replaced with a pair of PFETs Q 5 . Additionally, the polarity of diodes D 1 , D 2  and D 3  are reversed, as is the polarity of LED strings  60 . Particularly, the first end of first secondary winding  640  is coupled to the cathode of diode D 2  and the second end of first secondary winding  640  is coupled to the cathode of diode D 3 . The anodes of diodes D 2  and D 3  are commonly coupled to the cathodes of both diodes D 1 . The anode of each diode D 1  is coupled to the drain of a respective PFET Q 5 . The gate of each PFET Q 5  is coupled to a respective output of control circuitry  810  (the connections not shown) and the signal on the gate is denoted VG 5 A and VG 5 B, respectively. The source of each PFET Q 5  is coupled to the first end of the respective capacitor C 1  and the cathode end of the respective LED string  60 . The anode end of each LED string  60  is coupled to the common potential. The second end of each capacitor C 1  and the center tap of first primary winding  640  are each coupled to the common potential. 
     The operation of LED driving arrangement  900  will be described herein in relation to the waveform graphs of  FIG. 10B  where the x-axis represents time and the y-axis represents amplitude in arbitrary units. Particularly, signal VG 1 A is illustrated by trace  670 , signal VG 1 B is illustrated by trace  680 , voltage VS 2  is illustrated by trace  690 , signal VG 5 A is illustrated by trace  910  and signal VG 5 B is illustrated by trace  920 . 
     At time T 1 , control circuitry  810  is arranged to output a high signal VG 1 A and a low signal VG 1 B, thereby closing NFET Q 3  and opening NFET Q 4 . As a result, primary winding  630  is charged and voltage VS 2  rises. At time T 2 , control circuitry  810  is arranged to output a low signal VG 5 A, thereby closing the respective PFET Q 5  and generating current through the respective LED string  60 . At time T 3 , control circuitry  810  is arranged to output a low signal VG 5 B, thereby closing the respective PFET Q 5  and generating current through the respective LED string  60 . As described above, the current through each parasitic capacitance CS flows through first secondary winding  640 , the dI/dt limiting function of first secondary winding  640  effectively eliminating the sharp discharging current spike of parasitic capacitances CS. 
     At time T 4 , control circuitry  810  is arranged to output a low signal VG 1 A, thereby opening NFET Q 3 . As a result, voltage VS 2  drops to zero. Additionally, control circuitry  810  is arranged to output high signals VG 5 A and VG 5 B, thereby opening PFETs Q 5 . Synchronizing the turn off edge of PFETs Q 5  with the zero value of voltage VS 2  minimizes the turn off loss of PFETs Q 5 . 
     At time T 5 , control circuitry  810  is arranged to output a high signal VG 1 B, thereby closing NFET Q 4 . As a result, voltage VS 2  is negative and diode D 2  is forward biased, which begins the second half of the cycle where current flows through diode D 3 , which in the interest of brevity will not be detailed 
     At time T 1 , power is also output by second secondary winding  645  to output VO 1 . In one embodiment (now shown), a feedback loop is provided to control the duty cycle of NFET Q 1  so as to maintain the voltage of output VO 1  at a predetermined value. 
       FIG. 11A  illustrates a high level schematic diagram of an LED driving arrangement  1000 . LED driving arrangement  1000  comprises: an inductance element  1020 , illustrated and described herein as a transformer  1020  comprising a primary winding  1030 , a first secondary winding  1040  and a second secondary winding  1045 , each magnetically coupled to primary winding  1030 ; a switching circuit  650 , switching circuit  650  comprising an NFET Q 3  and an NFET Q 4 ; a capacitor CX; a diode D 5 ; a diode D 6 ; a pair of unidirectional electronic valves D 7 , illustrated and described herein as diodes D 7 ; a pair of unidirectional electronic valves D 8 , illustrated and described herein as diodes D 8 ; a pair of capacitors C 1 ; a capacitance element CB, illustrated and described herein as a capacitor CB; an NFET Q 2 ; a pair of LED strings  60 A and  60 B; a capacitor C 2 ; and a control circuitry  1060 . 
     The drain of NFET Q 3  is coupled to a power lead and the gate of NFET Q 3  is coupled to a respective output of control circuitry  1060  (the connection not shown), the signal on the gate of NFET Q 3  denoted VG 1 A. The source of NFET Q 3  is coupled to the drain of NFET Q 4  and a first end of capacitor CX. A second end of capacitor CX is coupled to a first end of primary winding  630 . A second end of primary winding  630  is coupled to the source of NFET Q 4  and a return lead. The gate of NFET Q 4  is coupled to a respective output of control circuitry  1060  (the connection not shown), the signal on the gate of NFET Q 4  denoted VG 1 B. 
     A first end of first secondary winding  1040  is coupled to a first end of capacitor CB. A second end of capacitor CB is coupled to the cathode of a first diode D 7  and to the anode of the second diode D 7 . The anode of the first diode D 7  is coupled to the cathode end of LED string  60 B and a first end of a respective capacitor C 1 . A second end of first secondary winding  1040  is coupled to the cathode of a first diode D 8  and the anode of the second diode D 8 . The anode of the first diode D 8  is coupled to the cathode end of LED string  60 A and a first end of a respective capacitor C 1 . The cathodes of the second diode D 7  and the second diode D 8  are commonly coupled to the drain of NFET Q 2 . The gate of NFET Q 2  is coupled to a respective output of control circuitry  1060  (the connection not shown), the signal on the gate of NFET Q 2  denoted VG 2 . The source of NFET Q 2 , the second end of each capacitor C 1  and the anode end of each LED string  60 A,  60 B are each coupled to a common potential, the common potential further coupled to a metal chassis. Further illustrated is the parasitic capacitance CS of each LED string, from the cathode end of the respective LED string to the metal chassis, as described above. 
     A first end of second secondary winding  1045  is coupled to the anode of diode D 5  and a second end of second secondary winding  1045  is coupled to the anode of diode D 6 . The cathodes of diodes D 5  and D 6  are commonly coupled to a first end of capacitor C 2 , representing an output node denoted VO 1 . A second end of capacitor C 2  and a center tap of second secondary winding  645  are each coupled to the common potential. 
     The operation of LED driving arrangement  1000  will be described herein in relation to the waveform graph of  FIG. 11B  where the x-axis represents time and the y-axis represents amplitude in arbitrary units. Particularly, signal VG 1 A is illustrated by trace  670 , signal VG 1 B is illustrated by trace  680 , voltage VS 2  is illustrated by trace  690  and signal VG 2  is illustrated by trace  1070 . 
     At time T 1 , control circuitry  1060  is arranged to output a high signal VG 1 A and a low signal VG 1 B, thereby closing NFET Q 3  and opening NFET Q 4 . As a result, primary winding  1030  is charged and voltage VS 2  rises. At time T 2 , control circuitry  1060  is arranged to output a high signal VG 2 , thereby closing NFET Q 2  and generating current through LED strings  60 A and  60 B. Capacitor CB balances the currents of LED strings  60 A and  60 B, and ensures that the currents are equal. As shown, balancing capacitor CB is in the AC current flowing path, i.e. during the positive half cycle of voltage VS 2  the current of LED string  60 A flows through NFET Q 2  and then capacitor CB from left side to right side, while during the negative half cycle of voltage VS 2  the current of LED string  60 B flows through NFET Q 2  and then capacitor CB from right side to left side. A capacitor can only couple AC current at steady state, or in other words, the voltage across a capacitor can only be maintained unchanged when the positive charge and negative charge are equal. With this natural property of the capacitor, the current of the two LED strings  60 A and  60 B will automatically be maintained equal at steady state operation. If the forward operating voltages of LED strings  60 A and  60 B are not equal, a DC bias voltage will be automatically established across capacitor CB. For example, in the event that the forward operating voltage of LED string  60 A is greater than the forward operating voltage of LED string  60 B, the DC bias voltage will exhibit a polarity of positive on the right side of capacitor CB, and the amplitude will be:
 
(½)*( V LED1 −V LED2)  EQ. 1
 
where VLED 1  is the forward operating voltage of LED string  60 A and VLED 2  is the forward operating voltage of LED string  60 B.
 
     The DC bias voltage causes an increase in the voltage across LED string  60 A and a decrease in the voltage across LED string  60 B so as to maintain the balance of the current of the two LED strings  60 A and  60 B. 
     As described above, for each LED string  60 A and  60 B, the current thereof flows through NFET Q 2  and capacitor CB, via first secondary winding  1040 . Thus, the effect of the parasitic capacitance CS on the switching operation is eliminated. 
     At time T 3 , control circuitry  1060  is arranged to output a low signal VG 1 A, thereby opening NFET Q 3 . As a result, voltage VS 2  drops to zero. Additionally, control circuitry  1060  is arranged to output a low signal VG 2 , thereby opening NFET Q 2 . Synchronizing the turn off edge of NFET Q 2  with the zero value of voltage VS 2  minimizes the turn off loss of NFET Q 2 . 
     At time T 4 , control circuitry  1060  is arranged to output a high signal VG 1 B, thereby closing NFET Q 4 . As a result, voltage VS 2  is negative and current flows through LED string  60 B, which begins the second half of the cycle where current flows through the respective diodes D 7 , D 8  which in the interest of brevity will not be detailed. 
     At time T 1 , power is also output by second secondary winding  1045  to output VO 1 . In one embodiment (now shown), a feedback loop is provided to control the duty cycle of NFET Q 1  so as to maintain the voltage of output VO 1  at a predetermined value. 
       FIG. 12A  illustrates a high level schematic diagram of a LED driving arrangement  1100 . LED driving arrangement  1100  is in all respects similar to LED driving arrangement  1000 , with the exception that NFET Q 2  is coupled between LED strings  60 A,  60 B and the common potential. Additionally, the polarity of diodes D 7 , diodes D 8  and LED string  60 A,  60 B are reversed. Particularly, the second end of capacitor CB is coupled to the anode of the first diode D 7  and the cathode of the second diode D 7 . The cathode of the first diode D 7  is coupled to the anode end of LED string  60 B and the first end of the respective capacitor C 1 . The second end of first secondary winding  1040  is coupled to the anode of a first diode D 8  and the cathode of the second diode D 8 . The cathode of the first diode D 8  is coupled to the anode end of LED string  60 A and the first end of the respective capacitor C 1 . The anodes of the second diode D 7  and the second diode D 8  are coupled to the common potential. The gate of NFET Q 2  is coupled to a respective output of control circuitry  1060  (the connection not shown), the signal on the gate of NFET Q 2  denoted VG 2 . The second end of each capacitor C 1  and the cathode end of each LED string  60 A,  60 B are commonly coupled to the drain of NFET Q 2 . The source of NFET Q 2  is coupled to the common potential. 
     The operation of LED driving arrangement  1100  will be described herein in relation to the waveform graphs of  FIG. 12B  where the x-axis represents time and the y-axis represents amplitude in arbitrary units. Particularly, signal VG 1 A is illustrated by trace  670 , signal VG 1 B is illustrated by trace  680 , voltage VS 2  is illustrated by trace  690  and signal VG 2  is illustrated by trace  1070 . 
     At time T 1 , control circuitry  1060  is arranged to output a high signal VG 1 A and a low signal VG 1 B, thereby closing NFET Q 3  and opening NFET Q 4 . As a result, primary winding  1030  is charged and voltage VS 2  rises. At time T 2 , control circuitry  1060  is arranged to output a high signal VG 2 , thereby closing NFET Q 2  and generating current through LED strings  60 A and  60 B. Capacitor CB balances the currents of LED strings  60 A and  60 B, and ensures that the currents are equal, as described above in relation to LED driving arrangement  1000 . 
     In applications where the LED drive ground is not connected to the chassis ground or the parasitic capacitance is small enough to not cause significant switching stress, the configuration of LED driving arrangement  1100  is also a viable solution for a low cost two string LED drive. 
     At time T 3 , control circuitry  1060  is arranged to output a low signal VG 1 A, thereby opening NFET Q 3 . As a result, voltage VS 2  drops to zero. Additionally, control circuitry  1060  is arranged to output a low signal VG 2 , thereby opening NFET Q 2 . Synchronizing the turn off edge of NFET Q 2  with the zero value of voltage VS 2  minimizes the turn off loss of NFET Q 2 . 
     At time T 4 , control circuitry  1060  is arranged to output a high signal VG 1 B, thereby closing NFET Q 4 . As a result, voltage VS 2  is negative and current flows through LED string  60 B, as described above thus providing the second half of the cycle. 
     At time T 1 , power is also output by second secondary winding  1045  to output VO 1 . In one embodiment (now shown), a feedback loop is provided to control the duty cycle of NFET Q 1  so as to maintain the voltage of output VO 1  at a predetermined value. 
     It is appreciated that certain features of the invention, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the invention which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub-combination. 
     Unless otherwise defined, all technical and scientific terms used herein have the same meanings as are commonly understood by one of ordinary skill in the art to which this invention belongs. Although methods similar or equivalent to those described herein can be used in the practice or testing of the present invention, suitable methods are described herein. 
     All publications, patent applications, patents, and other references mentioned herein are incorporated by reference in their entirety. In case of conflict, the patent specification, including definitions, will prevail. In addition, the materials, methods, and examples are illustrative only and not intended to be limiting. 
     It will be appreciated by persons skilled in the art that the present invention is not limited to what has been particularly shown and described herein above. Rather the scope of the present invention is defined by the appended claims and includes both combinations and sub-combinations of the various features described hereinabove as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not in the prior art.