Abstract:
Vertically stacked Field Effect Transistors (FETs) are created where a first FET and a second FET are controllable independently. The vertically stacked FETs may be connected in series or in parallel, thereby suitable for use as a portion of a NAND circuit or a NOR circuit. Epitaxial growth over a source and drain of a first FET, and having similar doping to the source and drain of the first FET provide a source and drain of a second FET. An additional epitaxial growth of a type opposite the doping of the source and drain of the first FET provides a body for the second FET.

Description:
FIELD OF THE INVENTION 
       [0001]    This invention relates generally to Field Effect Transistors (FETs), and more particularly to vertically stacked FETs suitable for NAND and NOR configuration. 
       SUMMARY OF EMBODIMENTS OF THE INVENTION 
       [0002]    Semiconductor chips are expensive to manufacture. Therefore, it is important to place as much function as possible on a semiconductor chip of a given size. Engineers constantly strive to place logic gates as densely as possible. Embodiments of the current invention vertically stack Field Effect Transistors (FETs) in order to improve density. In particular, embodiments of the invention provide for stacking N-channel Field Effect Transistors (NFETs) and for stacking P-channel Field Effect Transistors (PFETs). The NFETs are independently controllable and can be used for an NFET portion of a NAND circuit or a NOR circuit. Likewise, the PFETs are independently controllable and can be used for a PFET portion of a NAND circuit or a NOR circuit. Conventional Complementary Metal Oxide Semiconductor (CMOS) logic has NFETs arranged side-by-side and PFETs also arranged side-by-side. 
         [0003]    Vertically stacked FETs are constructed on a semiconductor substrate. A first FET on the semiconductor substrate has a first source, a first drain, a first gate dielectric, a first body, and a first gate electrode. A second FET has a second source, a second drain, a second gate dielectric, a second body, and a second gate electrode. The first and second gate electrodes are connected to different logical signals. The second gate electrode is physically above the first gate electrode relative to a top surface of the semiconductor substrate. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]      FIG. 1  shows a vertical structure having a silicon substrate (P-silicon assumed). Alternating layers of dielectric material (HfO 2  used for exemplary purposes) and FET gate conductor (“metal” used for exemplary purposes) are depicted. 
           [0005]      FIG. 2  shows the vertical structure of  FIG. 1  in isometric style, further showing how a gate area is formed of the vertical stack. The gate area includes “dogbone” ends suitable for etching and forming contacts with the FET gate conductors. 
           [0006]      FIG. 3  shows the items in  FIG. 2  further covered in silicon dioxide. 
           [0007]      FIG. 4  shows the silicon dioxide etched to expose a top of the dielectric (HfO 2 ). Two contact holes are shown etched for making contacts to an FET gate conductor. A cross section AA is identified. 
           [0008]      FIG. 5  shows the cross section AA identified in  FIG. 4 . A dielectric (SiO 2  shown) spacer has been conformally deposited. 
           [0009]      FIG. 6  shows the spacer after an anisotropic etch. Source and drain areas have been implanted. 
           [0010]      FIG. 7  shows a first growth of an epitaxial layer. The doping of the first epitaxial layer is similar to the doping of the source and drain area (i.e., if the source and drain area are N+, then the first epitaxial layer is also N+). 
           [0011]      FIG. 8  shows an oxygen implant that creates a SiO 2  later isolating a source (or drain) area from the first growth of epitaxial layer. A photoresist layer may be used to prevent SiO 2  formation over another source (or drain) area, as shown. 
           [0012]      FIG. 9  shows a growth of a second epitaxial layer, the second epitaxial layer doped similarly to the first epitaxial layer. A third epitaxial layer is grown over the second epitaxial layer, the third epitaxial layer being of opposite doping to the first and second epitaxial layers (“opposite doping” meaning that if, e.g., the first and second epitaxial layers are “N” doped, the third epitaxial layer being of opposite doping would be “P” doped). 
           [0013]      FIG. 10  shows the structure of  FIG. 9 , planarized. 
           [0014]      FIG. 11  shows an etching of a hole through the first and second epitaxial layers and the SiO 2  later of  FIG. 8 . This etching will be further processed to form a lined contact hole. 
           [0015]      FIG. 12  shows the hole of  FIG. 11  after deposition of a dielectric liner in the lined contact hole. 
           [0016]      FIG. 13  shows the lined contact hole filled with a conductive fill. A contact has been made as shown for making contact to the source or drain area not contacted by the lined contact hole. 
           [0017]      FIG. 14  shows, schematically, two NFETs (N-channel Field Effect Transistors) connected in parallel, suitable for an NFET portion of a NOR circuit. 
           [0018]      FIG. 15  shows, schematically, two NFETs connected in series, suitable for an NFET portion of a NAND circuit. 
           [0019]      FIG. 16  shows a completed NAND circuit having parallel-connected PFETs (P-channel Field Effect Transistors) connected in parallel and series-connected NFETs. 
           [0020]      FIG. 17  shows an alternative structure to connect to a source or drain area using an unlined contact hole if the photoresist of  FIG. 8  is not used. Holes are etched to both source and drain areas. 
           [0021]      FIG. 18  shows the structure of  FIG. 17 , with the hole to one of the source and drain areas being lined with a dielectric. 
           [0022]      FIG. 19  shows both holes etched in  FIG. 17  being filled with a conductive fill. 
           [0023]      FIG. 20  shows a schematic overlaying the structure of  FIG. 19  showing two NFETs being connected in parallel, suitable for an NFET portion of a NOR gate. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0024]    In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form a part hereof, and within which are shown by way of illustration specific embodiments by which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the invention. 
         [0025]    Embodiments of the present invention provide for vertical structures of field effect transistors suitable for NAND and NOR logic gates. Detailed drawings and description focus on N-channel Field Effect Transistors (NFETs); however, it will be clear that a similar process, with appropriate dopings, will create analogous PFET (P-channel Field Effect Transistors). 
         [0026]    With reference now to  FIG. 1 , a stack  10  comprises a silicon substrate  108 , shown as being doped P-, forms a substrate for further processing of NFET transistors as will be explained below. It is understood that PFET transistors will be formed above an N-doped region, for example, an N-well in the silicon substrate  108 . Alternating layers of a dielectric material (HfO 2  shown for exemplary purposes) and gate conductor material (e.g., metal or polysilicon; “metal” used for exemplary purposes) are stacked above silicon substrate  108 . HfO 2    101 ,  102 , and  103  are shown in  FIG. 1  as the dielectric layers. Metal  105  is layered between HfO 2    101  and HfO 2    102 ; Metal  106  is layered between HfO 2    102  and HfO 2    103 . HfO 2    101  and HfO 2    103  will form gate oxides for a first and a second NFET and therefore need to be of appropriate thickness for gate oxide purposes. HfO 2    102  electrically isolates metal  105  from metal  106  and needs to be of appropriate thickness for this purpose. 
         [0027]      FIG. 2  shows stack  10  after some processing in a semiconductor fabrication facility to produce a vertical structure  100 . An area for NFETs shows a “dog bone” shape. A middle area of the dog bone shape is an area in which NFETs will be created. In the “dog bone”, the orthogonal areas (portions) at the ends are for contacting the gate conductor material. A left orthogonal area shows HfO 2    101 , metal  105 , and HfO 2    102  etched away so that metal  106  can be contacted with dual contacts. Shapes other than “dog bones” are contemplated for dual contacts, for example, an “L” shape having a portion long enough to have a dual contact. An “L” having a shorter portion may be used if only a single contact is allowed in a particular technology. The right orthogonal area may be used to make contact(s) to metal  105  in a similar manner. For example the right and left orthogonal areas may be etched at the same time to remove a portion of HfO 2    101 . In subsequent etches, the left orthogonal area is further etched, as shown, while the right orthogonal area is masked to prevent further etching. Note that neither the right nor the left orthogonal “dog bone” portion needs to be etched as shown, nor is a “dog bone” required, if metal  105  or metal  106  is otherwise connected to a source of a logical signal intended to be applied as a gate voltage on an FET that is created as explained below. For example, metal  105  (or metal  106 ), during processing in creation of vertical stack  100 , may be routed to such a signal source and therefore a “dog bone” and vias to metal  105  or metal  106  is not required. 
         [0028]      FIG. 3  shows the vertical structure  100  after further deposition of SIO 2    120 , or other suitable dielectric material, to cover vertical structure  100 . Note that the right orthogonal “dog bone” portion is shown as not etched, whereas the left orthogonal “dog bone” portion has been etched. For example, metal  105  (referenced in  FIG. 2 ) may be routed on the same conductor level of metal  105  to a source of a signal and therefore not require a via. 
         [0029]      FIG. 4  shows the vertical structure  100  of  FIG. 3  after etching SiO 2    120  until HfO 2    101  is exposed. Also, holes for gate contacts  125  provide, when filled with conductive material, contacts to metal  106 . Holes  121 , shown with bold lines, are etched on either side of the remaining vertical structure  100 . Holes  121  provide access for subsequent processing that will, for example, deposit spacers, etch the spacers, grow epitaxial regions, as will be explained below.  FIG. 4  shows cross section AA which will be used in following figures. Cross section AA cuts through a portion of the remaining vertical structure  100  and holes  121  as depicted. 
         [0030]      FIG. 5  shows the structure of  FIG. 4  at cross section AA, after conformal deposition of a SiO 2  spacer  130 . 
         [0031]      FIG. 6  shows the structure of  FIG. 5  following an anisotropic etch of SiO 2  spacer  130 . The anisotropic etch bares a top surface of HfO 2    101  and a top surface of P-Si  108 . Source/drain regions  132  ( 132 A,  132 B) are implanted into P-Si  108 . At this stage of the process, source/drain regions  132  are the source/drains of a first NFET; HfO 2    103  is a gate dielectric of the first NFET; metal  106  is a gate electrode of the first NFET. 
         [0032]    Source/drain regions  132 A and  132 B are created by the same implant processing step and are generically called source/drain regions  132 . However, for clarity as to which source/drain region is intended, a suffix “A” is appended to  132  for the “right hand” (in the drawing) source/drain region  132 , and a suffix “B” is appended to  132  for the “left hand” source/drain region  132 . A similar convention is used hereinafter to designate “left hand” and “right hand” portions of a particular element. 
         [0033]      FIG. 7  shows the structure of  FIG. 6  with addition of N+ Epi  133  grown over source/drain regions  132 . Note the “right hand” and “left hand” “A”, “B” suffix convention. N+ Epi  133  has a doping similar to doping of source/drain regions  132 . That is, if source/drain regions  132  are doped “N”, N+ Epi  133  is also doped “N”, with appropriate concentration of dopants. 
         [0034]    While detail is given herein for creation of NFETs, it will be understood that PFETs may be created in a similar manner, for example starting with an N-Nwell in P-Si  108 , P+ implantation forming source/drain regions for a PFET, and P+ epitaxial growth of the source/drain regions of the PFET. 
         [0035]      FIG. 8  shows the structure of  FIG. 7  with addition of photoresist  134  and an oxygen implant of suitable energy to create SiO 2    135 A over source/drain region  132 A. Photoresist  134  blocks the oxygen implant from forming a SiO 2    1358  over source/drain region  1328 , as shown in  FIG. 7 . SiO 2    135 A electrically isolates source/drain region  132 A from an overlying N+ epi  133 A. Source/drain region  1328  remains in electrical connection with similarly doped overlying N+ epi  1338 . 
         [0036]      FIG. 9  shows the structure of  FIG. 8  with addition of continued growth of suitably doped epitaxial silicon, N+ epi  136 , shown as N+ epi  136 A,  1368 . N+ epi  136  is grown over N+ epi  133  until N+ epi  136  grows above the top surface of HfO 2    101 . N+ epi  136  will “bulge” slightly over the spacer and a portion of HfO 2    101 , as shown. P− epi  137  is grown on N+ epi  136 , as depicted. P− epi  137  is grown until the top surface of HfO 2    101  is covered to a suitable depth for a body of a second NFET. The P− epi  137  is of opposite doping to the N+ doping of N+ epi  136 , where opposite doping means “P” doping versus “N” doping, with appropriate concentration of dopants for the intended purpose. 
         [0037]    N+ epi  133  and N+ epi  136  may be considered a single epitaxial layer. The two-part growth facilitates the oxygen implant to form SiO 2    135 A. 
         [0038]      FIG. 10  shows the structure of  FIG. 9 , following planarization. The planarization removes P− epi  137  except for an area above the top surface of HfO 2    101 . The remaining P− epi  137  forms a body of a second NFET; HfO 2    101  forms a gate dielectric of the second NFET. N+ epi  136  forms source/drain regions N+ epi  136 A and  1368  for the second NFET; metal  105  forms a gate electrode of the second NFET. 
         [0039]      FIG. 11  shows the structure of  FIG. 10  following etching of a lined contact hole  150 . Lined contact hole  150  is formed by an etch through N+ epi  136 A and N+ epi  133 A, followed by a second etch through SiO 2    135 A. 
         [0040]      FIG. 12  shows the structure of  FIG. 11  following deposition of a dielectric material lining around the vertical surfaces of lined contact hole  150 . The dielectric material lining is shown as SiO 2  liner  151 . SiO 2  liner  151  may, in embodiments, use a dielectric other than SiO 2 , so long as the dielectric is compatible with the processing steps described herein. Deposition of SiO 2  liner  151  will also form SiO 2  on source/drain region  132 A, and that SiO 2  is removed by etching so that source/drain region  132 A is exposed under lined contact hole  150 . 
         [0041]      FIG. 13  shows the structure of  FIG. 12  following addition of conductive fill  153  in lined contact hole  150 . SiO 2    135 A and SiO 2  liner  151  electrically isolates the source/drain region  132 A from the N+ epi  133 A and N+ epi  136 A. Contact  154  is added, as shown, on N+ epi  136 B. Contact  154  is effectively connected to source/drain region  132 B through N+ epi  133 B and N+ epi  136 B. In  FIG. 13 , a contact  149  is made to the N+ epi  136 A, and, in an embodiment, contact  149  may be placed as shown, that is, closer to the second NFET than is the lined contact hole  150 . However, in other embodiments, one or more lined contact holes  150  may be alternated with one or more contacts  149  as shown in the “top view” in  FIG. 13 , wherein the one or more lined contact holes  150  are approximately lined up with contacts  149  in order to make the layout more compact. 
         [0042]      FIG. 14  shows the structure of  FIG. 13 , including a schematic of a first NFET N 1  and a second NFET N 2  overlaid on the structure of  FIG. 13 . Contact  149  is shown not “lined up” with the lined contact hole  150  in order to more clearly and completely show connections. Sources of N 1  and N 2  are shown connected to ground; drains of N 1  and N 2  are shown connected together at node output  155 . Gate controls of N 1  (metal  106 ) and N 2  (metal  105 ) are independent, assuming that metal  106  and metal  105  are connected to independent logical sources. In  FIG. 14 , N 1  and N 2  are connected as NFETs are in a logical NOR configuration; that is, if either N 1  or N 2  is “on”, output  155  will be pulled to Gnd. 
         [0043]      FIG. 15  shows N 1  and N 2  connected in series, as NFETs are connected in a NAND configuration. Output  155  will be pulled to Gnd if logical signals on both metal  105  and metal  106  are at high logical levels (e.g., Vdd) so that both N 1  and N 2  are “on”. 
         [0044]      FIG. 16  shows a completed NAND, with PFETs P 1  and P 2  having sources connected to Vdd and drains connected to output  155 . NFETs N 1  and N 2  are connected as shown in  FIG. 15 ; that is, N 1  and N 2  are connected in series between output  155  and Gnd. PFETs P 1  and P 2  are created, as described earlier, in a manner similar to that used in creation of N 1  and N 1 , but built over an N-well N-Si  208 , with PFET source/drain regions  232  doped P+ further designated  232 A and  232 B implanted in N-Si  208 . Again, note that suffix “A” is appended to “right hand” portions of the PFET structure; “B” is added to the “left hand” portions so that those portions can be clearly identified when needed. PFET processing, similar to the detailed NFET processing creates a P+ epi  233 , a P+ epi  236 , and an N− epi  238 . Appropriate interconnections of gate electrodes are created on metal  105  and metal  106  (or, through vias, other conducting levels) to provide logical values on the gates of N 1 , N 2 , P 1 , and P 2 . For example, Metal  105  of N 2  is connected to metal  105  of P 2 ; metal  106  of N 1  is connected to metal  106  of P 1 . The connections may be done on those metal levels (i.e., metal  105  and metal  106 ) or through vias such as gate contacts  125  shown in  FIG. 4  to other wiring levels suitable for circuit interconnect from the metal  105  and  106  gate electrodes of N 1 , N 2 , P 1 , and P 2 . Whereas  FIG. 16  explicitly depicts a NAND, a NOR configuration may be configured by connecting N 1  and N 2  as shown in  FIG. 14 , and having P 1  and P 2  connected in series between Vdd and output  155  in a manner similar to the series N 1  and N 2  shown in  FIG. 15 . 
         [0045]    Whereas N 1  has been shown earlier as having a lined contact hole  150  to connect to the source/drain region  132 A, and relying on a low impedance path through similarly doped silicon areas (N+  1328 , N+ Epi  133 B, and N+ Epi  136 B) to connect source/drain region  132 B to contact  154  ( FIG. 13 ), in another embodiment, shown in  FIGS. 17-20 , photoresist  134  ( FIG. 8 ) is not used, and therefore the oxygen implant creates a SiO 2    135  ( 135 A,  135 B) barrier above both source/drain regions  132 A and  132 B.  FIG. 17  shows both lined contact hole  150  and unlined contact hole  156  being created at the same time using a silicon etch to etch through N+ epi  136 A and  136 B and N+ epi  133 A and  133 B, followed by an oxide etch through SiO 2    135 A and  135 B. In  FIG. 18 , SiO 2  liner  151  is created in lined contact hole  150 , but a mask over unlined contact hole  156  prevents creation of a similar SiO 2  liner  151  being formed in unlined contact hole  156 .  FIG. 19  shows both lined contact hole  150  and unlined contact hole  156  being filled with a conductive fill  153 . Conductive fill  153  may be a metal, such as tungsten, or a suitably doped polysilicon fill. A polysilicon fill would typically make a higher resistance contact than a metal fill. Note that one or more contacts  149  “in-line” (see top view portion of  FIG. 13 ) is assumed in  FIG. 19 , so that N+ epi  136 A can be contacted, but do not appear in  FIG. 19  because they would be “behind” the lined contact hole  150 . In an alternative embodiment, a second lined contact hole may be used in place of the unlined contact hole  156  shown in  FIG. 17  and carried through  FIGS. 17-20 ; however, one or more contacts such as contact  149  shown in  FIG. 20  would be required to contact a drain of N 2  (i.e., N+ Epi  1368 ) to output  155 . 
         [0046]      FIG. 20  shows the structure of  FIG. 19  overlaid with a schematic of N 1  and N 2  connected in a NOR configuration; that is, if either N 1  or N 2  is turned on (i.e., if either the voltage on gate electrode metal  105  (for N 2 ) is high, or the voltage on gate electrode metal  106  (for N 1 ) is high) output  155  is pulled to Gnd. PFETs to complete the NOR would be as in  FIG. 16 , with one or more unlined vias used to contact  232 B. If a lined via is used in the PFET structure, a contact would also need to be made to P+ Epi  236 B.