Abstract:
A structure of power semiconductor device integrated with clamp diodes having separated gate metal pads is disclosed. The separated gate metal pads are wire bonded together on the gate lead frame. This improved structure can prevent the degradation of breakdown voltage due to electric field in termination region blocked by polysilicon or gate metal.

Description:
This application is a continuation in part of co-pending U.S. patent application Ser. No. 12/453,630 filed on May 18, 2009, the entire disclosure of co-pending application Ser. No. 12/453,630 is herein incorporated by reference. 
    
    
     FIELD OF THE INVENTION 
     This invention relates generally to the cell structure and device configuration of semiconductor devices. More particularly, this invention relates to an improved device configuration of power semiconductor devices integrated with clamp diodes having separated gate metal pad. 
     BACKGROUND OF THE INVENTION 
     In order to enhance avalanche capability, clamp diodes are formed between Gate and Drain for MOSFET and between Gate and Collector for IGBT, respectively. However, breakdown voltage degradation in main devices may be introduced while forming this integrated configuration in prior art if the clamp diodes are made on a polysilicon layer placed across the edge termination. The interaction between the electric fields in the polysilicon clamp diodes and edge termination may significantly degrade breakdown voltage of the main devices. 
       FIG. 1  is a circuit diagram of a MOSFET with gate-drain clamp diodes and  FIG. 2  is the cross section view of a MOSFET of prior art (U.S. Pat. No. 5,631,187) where the cell is formed on N substrate  200 . On the top surface of the substrate  200 , there is an N+ source region  210  surrounded by a P body region  211 . A metal layer  220  makes electrical contact to both said N+ source region  210  and P body region  211  acting as a source electrode. Meanwhile, metal layer  222  and  221  are deposited to function as a gate electrode and a drain electrode of the cell structure, respectively. Between the gate electrode and drain electrode, a serial of back-to-back polysilicon diodes  230  are formed across over the termination to enhance the avalanche capability of the semiconductor power device. 
     The prior art discussed above is encountering a technical difficulty which is that, as the gate-drain (or gate-collector for IGBT) clamp diode crosses over termination, a problem of breakdown voltage degradation will be arisen due to electric field in termination region is blocked by polysilicon. 
     Accordingly, it would be desirable to provide a new and improved device configuration to prevent the degradation of breakdown voltage from happening. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide a new and improve device configuration to solve the problem discussed above. 
     One advantage of the present invention is that, separated gate metal pads are used to integrate MOSFET with gate-drain clamp diodes and gate-source clamp diodes (or to integrate IGBT with gate-collector clamp diodes and gate-emitter clamp diodes), as shown in  FIG. 3A  (or  FIG. 3B  for IGBT) of circuit Diagrams and  FIG. 4  of top view. The first gate metal pad  550  in  FIG. 4  located inside of the metal field plate ring area  552  is connected directly to trench gate of MOSFET (IGBT) or through a resistor (not shown). The first gate metal pad  550  is also connected to source metal  553  (or emitter metal for IGBT) through a gate-source clamp diode  554  of MOSFET (or gate-emitter clamp diode for IGBT) and the metal field plate  552  as gate metal runner as well. The second gate metal pad  551  located outside of edge termination including the metal field plate ring area  552  is connected to drain of MOSFET (or collector of IGBT) through a gate-drain clamp diode  555  (or gate-collector clamp diode for IGBT). Said first and second gate metal pads are wire bonded together on the gate lead frame with separated bond wires. Because the gate-drain clamp diode  555  (or gate-collector clamp diode for IGBT) is located outside of the edge termination, there will be no degradation in breakdown voltage due to no polysilicon clamp diodes crossing over the edge termination. Alternatively, as shown in  FIG. 5 , the same above result can be achieved with a single gate bond wire which is bonded from the gate lead frame to the first gate metal pad  550 , and then bonded to the second gate metal pad  551 . 
     Briefly in a preferred embodiment according to the present invention, as shown in  FIG. 6 , which is also the A-B cross section view of  FIG. 4 . The present invention discloses a trench MOSFET device formed on a substrate heavily doped with a first semiconductor doping type, e.g., N+ doping type. Onto said substrate, grown an N epitaxial layer and a plurality of trenches were etched wherein. Doped poly was filled within a plurality of trenches over a gate oxide layer along the inner surface of said trenches to serve as trench gates. Especially, the trench gates underneath contact trenches of gate-drain clamp diodes and gate-source clamp diodes are employed to prevent shortage may caused by over etching of contact trenches. Near the top surface of P-body regions, N+ source regions are formed between two adjacent trench gates. A thick oxide interlayer is deposited over epitaxial layer, as well as over the top surface and sidewalls of a doped polysilicon layer comprising multiple back to back Zener diodes which composed of alternated doping areas of a first semiconductor doping type next to doping areas of a second semiconductor doping type. Through the thick oxide interlayer, source-body contact trenches, gate contact trenches and drain contact trenches are etched into epitaxial layer for source-body connection, gate connection and drain connection, respectively. Around the bottom of these contact trenches, a p+ contact area is formed. Especially, N+ contact regions are implanted near the bottom of the drain contacts trenches to further reduce the contact resistance. Meanwhile, other contact trenches are etched into cathodes of the Zener diodes for the formation of gate-drain clamp diodes and gate-source clamp diodes. To fill these contact trenches, a barrier layer and tungsten material are deposited and then etched back to act as metal plug. The first gate metal pad  550  and the second gate metal pad  551  is deposited to contact one electrode of gate-source clamp diodes and gate-drain clamp diodes via trench contacts etched into Zener diodes, respectively. At the same time, source metal is deposited to contact another electrode of gate-source clamp diodes with source region and body regions; drain metal is deposited to contact the other electrode of gate-drain clamp diodes with drain region. Said two separated gate metal pads are wire bonded together on the gate lead frame. In termination area, gate metal runner which also serving as metal field plate is formed overlying P-body and top surface of epitaxial layer. The gate-drain clamp diode as shown in  FIG. 6  is located outside of termination and has no gate metal or polysilicon cross over the edge termination, therefore resulting in no degradation in breakdown voltage which occurred in the prior art. Nevertheless, the second metal pad  551  in the gate-drain clamp diode is still able to be connected to the gate of main device through bond wire instead of metal or polysilicon cross over the edge termination. 
     Briefly in another preferred embodiment according to the present invention, as shown in  FIG. 7 , which also shows the A-B cross section view of  FIG. 4 , the trench MOSFET structure disclosed is similar to the structure in  FIG. 6  except that there is a deep guard ring under said metal field plate in termination area. 
     Briefly in another preferred embodiment according to the present invention, as shown in  FIG. 8 , which also shows the A-B cross section view of  FIG. 4 , the trench MOSFET structure disclosed is similar to the structure in  FIG. 6  except that there are n* regions in top surface of said epitaxial layer next to P-body region as termination and there are n* regions having higher doping concentration than the epitaxial layer underneath trench bottom for Rds reduction. 
     Briefly in another preferred embodiment according to the present invention, as shown in  FIG. 9 , which also shows the A-B cross section view of  FIG. 4 , the trench MOSFET structure disclosed is similar to the structure in  FIG. 8  except that there is a deep guard ring under said metal field plate in termination area. 
     Briefly in a preferred embodiment according to the present invention, as shown in  FIG. 10 , which is also the A-B cross section view of  FIG. 4 . The present invention discloses a trench IGBT device formed on a substrate heavily doped with a second semiconductor doping type, e.g., P+ doping type. Onto said substrate, grown a heavily doped epitaxial layer with a first semiconductor doping type, e.g., N+ doping type, onto which a second epitaxial layer lightly doped with the same first doping type is formed, and a plurality of trenches were etched wherein. Doped poly was filled within a plurality of trenches over a gate oxide layer along the inner surface of said trenches to serve as trench gates. Especially, the trench gates underneath contact trenches of gate-collector clamp diodes and gate-emitter clamp diodes are employed to prevent shortage may caused by over etching of contact trenches. Near the top surface of P-body regions, N+ emitter regions are formed between two adjacent trench gates. A thick oxide interlayer is deposited over front surface of epitaxial layer, as well as over the top surface and sidewalls of doped polysilicon layer comprising multiple back to back Zener diodes which composed of alternated doping areas of a first semiconductor doping type next to doping areas of a second semiconductor doping type. Through the thick oxide interlayer, emitter-base contact trenches, gate contact trenches and collector contact trenches are etched into the second epitaxial layer for emitter-base connection, gate connection and collector connection, respectively. Around the bottom of these contact trenches, a p+ contact area is formed. Especially, N+ contact regions are implanted near the bottom of the collector contacts trenches to further reduce the contact resistance. Meanwhile, other contact trenches are etched into cathodes of the Zener diodes for the formation of gate-collector clamp diodes and gate-emitter clamp diodes. To fill these contact trenches, a barrier layer and tungsten material are deposited and then etched back to act as metal plug. The first gate metal pad and the second gate metal pad is deposited to contact one electrode of gate-collector clamp diodes and gate-emitter clamp diodes via trench contacts etched into Zener diodes, respectively. At the same time, emitter metal is deposited to contact another electrode of gate-emitter clamp diodes with emitter region and base regions; collector metal is deposited to contact the other electrode of gate-collector clamp diodes with collector region. Said two separated gate metal pads are wire bonded together on the gate lead frame. In termination area, gate metal runner which also serving as metal field plate is formed overlying P-base and top surface of epitaxial layer and there is a deep guard ring and a floating ring under said metal field plate under said metal field plate as termination. 
     Briefly in another preferred embodiment according to the present invention, as shown in  FIG. 11 , which also shows the A-B cross section view of  FIG. 4 , the trench NPT IGBT device disclosed is similar to the structure in  FIG. 10  except that the device is built on a lightly doped N substrate and P+ is formed on rear side of the N substrate after backside grinding. 
     Briefly in another preferred embodiment according to the present invention, as shown in  FIG. 12B , which also shows the A-B cross section view of  FIG. 4 , the present invention discloses a trench NPT IGBT device with gate-collector diode, gate-emitter diode and collector shorting diode having separated gate metal pad.  FIG. 12A  shows a circuit diagram that illustrates the implementation of gate-emitter clamp diode, gate-collector clamp diode and collector shorting diode with IGBT device. The trench NPT IGBT device disclosed is similar to the structure in  FIG. 11  except the collector comprising alternated P+ and N+ regions. 
     Another aspect of the present invention is to provide improved semiconductor power device configuration for providing trench MOSFET devices integrated with a gate-drain clamp diode on a single semiconductor chip as shown in  FIG. 1 , a first gate metal connected to trenched gates; a first drain metal connected to a first drain region; source regions, body regions, the trenched gates and the first drain region formed in a top side of semiconductor chip; the gate-drain clamp diode is connected between a second gate metal on the gate-drain clamp diode and the first drain metal, composed of multiple back-to-back polysilicon Zener diodes disposed outside of edge termination area without having the polysilicon Zener diode or the second gate metal cross over the edge termination; a second drain region formed on the bottom side of the single semiconductor chip; a second drain metal layer connected to the second drain region; and the first and second gate metals are connected together at a gate lead frame through at least one bonding wire. The first gate metal and second gate metal connect together to the gate lead frame through two separated bond wires. Alternatively, the second gate metal connects to said first gate metal and then the gate lead frame through a single bond wire. 
     Another aspect of the present invention is to provide improved semiconductor power device configuration for providing Punch-Through (PT) type trench IGBT devices integrated with a gate-collector clamp diode on a single semiconductor chip. a first gate metal connected to trenched gates; a first collector metal connected to a first collector region; emitter regions, base regions, the trenched gates and the first collector region formed in a top side of the semiconductor chip; the gate-collector clamp diode is connected between a second gate metal on the gate-collector clamp diode and the first collector metal, composed of multiple back-to-back polysilicon Zener diodes disposed outside of edge termination area without having the polysilicon Zener diode or the second gate metal cross over the edge termination; a second collector region formed on the bottom side of the semiconductor chip; a second collector metal layer connected to the second collector region; and the first and the second gate metals are connected together at a gate lead frame through at least one bonding wire. The first gate metal and second gate metal connect together to the gate lead frame through two separated bond wires. Alternatively, the second gate metal connects to the first gate metal and then said gate lead frame through a single bond wire. The PT trench IGBT further comprises a heavily doped P+ substrate; a first N+ epitaxial layer grown on the P+ substrate; a second N epitaxial layer grown on the first epitaxial layer, having less doping concentration than the first N+ epitaxial layer; and the second collector region is disposed on said bottom side of the P+ substrate. 
     Another aspect of the present invention is to provide improved semiconductor power device configuration for providing Non-Punch-Through (NPT) type trench IGBT devices integrated with a gate-collector clamp diode on a single semiconductor chip. a first gate metal connected to trenched gates; a first collector metal connected to a first collector region; emitter regions, base regions, the trenched gates and the first collector region formed in a top side of the semiconductor chip; the gate-collector clamp diode is connected between a second gate metal on the gate-collector clamp diode and the first collector metal, composed of multiple back-to-back polysilicon Zener diodes disposed outside of edge termination area without having the polysilicon Zener diode or the second gate metal cross over the edge termination; a second collector region formed on the bottom side of the semiconductor chip; a second collector metal layer connected to the second collector region; and the first and the second gate metals are connected together at a gate lead frame through at least one bonding wire. The first gate metal and second gate metal connect together to the gate lead frame through two separated bond wires. Alternatively, the second gate metal connects to the first gate metal and then said gate lead frame through a single bond wire. The NPT trench IGBT further comprises a lightly doped N substrate; and the second collector region of P+ conductivity type is disposed on said bottom side of the lightly doped substrate. 
     Another aspect of the present invention is to provide improved semiconductor power device configuration for providing Non-Punch-Through (NPT) type trench IGBT devices integrated with a gate-collector clamp diode on a single semiconductor chip. The NPT trench IGBT configuration is same as the NPT IGBT described above except that the second collector region comprises alternately heavily P+ doped regions and N+ doped regions on the bottom side of said lightly doped substrate. 
     These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment, which is illustrated in the various drawing figures. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein: 
         FIG. 1  is a circuit diagram illustrates the implementation of a MOSFET cell with gate-drain clamp diodes of prior art. 
         FIG. 2  is a side cross-sectional view of prior art shown in  FIG. 1 . 
         FIG. 3A  is a circuit diagram that illustrates the implementation of a MOSFET cell with gate-drain clamp diodes and gate-source clamp diodes of this invention. 
         FIG. 3B  is a circuit diagram that illustrates the implementation of an IGBT cell with gate-emitter clamp diodes and gate-collector clamp diodes of this invention. 
         FIG. 4  is top view of this invention with two bonding wires connected to separate gate metal pads. 
         FIG. 5  is a top view of this invention with a single bonding wire connected to separate gate metal pads. 
         FIG. 6  is a side cross-sectional view of a trench MOSFET along A-B axis marked in  FIG. 4  of a preferred embodiment according to the present invention. 
         FIG. 7  is a side cross-sectional view of a trench MOSFET along A-B axis marked in  FIG. 4  of another preferred embodiment according to the present invention. 
         FIG. 8  is a side cross-sectional view of a trench MOSFET along A-B axis marked in  FIG. 4  of another preferred embodiment according to the present invention. 
         FIG. 9  is a side cross-sectional view of a trench MOSFET along A-B axis marked in  FIG. 4  of another preferred embodiment according to the present invention. 
         FIG. 10  is a side cross-sectional view of a trench PT IGBT along A-B axis marked in  FIG. 4  of another preferred embodiment according to the present invention. 
         FIG. 11  is a side cross-sectional view of a trench NPT IGBT along A-B axis marked in  FIG. 4  of another preferred embodiment according to the present invention. 
         FIG. 12A  shows a circuit diagram that illustrates the implementation of an IGBT cell with gate-emitter clamp diode, gate-collector clamp diode and collector shorting diode of this invention. 
         FIG. 12B  is a side cross-sectional view of a trench NPT IGBT along A-B axis marked in  FIG. 4  of another preferred embodiment according to the present invention shown in  FIG. 12A . 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Please refer to  FIG. 6  for a preferred embodiment of this invention showing the A-B cross section of  FIG. 4  where a trench MOSFET device cell integrated with gate-drain and gate-source clamp diodes is formed on a heavily N+ doped substrate  600  coated with back metal  690  on rear side as drain electrode. Onto the substrate  200 , a lighter N doped epitaxial layer  601  is grown, and a plurality of trenches is etched wherein. Doped poly is filled into the trenches padded with a gate insulation layer  620  formed over the inner surface of said trenches. Within these gate trenches filled with doped poly, gate trenches  611  with a wider trench width than contact trenches  612  right below the center of the contact trenches  612  are formed as buffer trenched gates to prevent shortage of the contact trenches  612  to the epitaxial layer  601  may caused by over etching of the contact trenches  612 . P-body regions  602  are extending between every adjacent trench gates  610  with N+ source region  603  near the top surface only within active area  640 . Trench source-body contacts  613  filled with tungsten plug are formed penetrating through a thick oxide interlayer  604  and source region  603 , and extending into P-body region  602 , and surrounded with p+ contact area  622  underneath each source-body contact bottom to contact source region  603  and P-body region  602  with source metal  605 . Trench gate contacts  614  filled with the tungsten plugs are formed penetrating through the thick oxide interlayer  604  and extending into the trench gates  610  to connect the trench gates  610  with gate metal. Trench drain contacts  615  filled with tungsten plug are formed penetrating through said oxide interlayer and source region  603 , and extending into the epitaxial layer  601  to connect drain region with drain metal  607 . There are gate-drain clamp diodes  630  above an oxide layer  624  between the second gate metal pad  608  and drain metal  607 , and gate-source clamp diodes  631  above said oxide layer  624  between the first gate metal pad  606  and source metal  605 . Said two gate metal pads are wire bonded together on the gate lead frame as shown in  FIG. 4 . In termination area  650 , gate metal overlying P-body region  602  and top surface of epitaxial layer  601  also serves as metal field plate. 
     Please refer to  FIG. 7  for another preferred embodiment of this invention showing the A-B cross section of  FIG. 4  where the trench MOSFET structure disclosed is similar to the structure in  FIG. 6  except that there is a deep guard ring  760  under the said metal field plate in termination area  750 . 
     Please refer to  FIG. 8  for another preferred embodiment of this invention showing the A-B cross section of  FIG. 4  where the trench MOSFET structure disclosed is similar to the structure in  FIG. 6  except that there are n* regions  861  in top surface of said epitaxial layer next to P-body region  802  as termination and there are n* regions  862  having higher doping concentration than the epitaxial layer underneath trench bottom for Rds reduction. 
     Please refer to  FIG. 9  for another preferred embodiment of this invention showing the A-B cross section of  FIG. 4  where the trench MOSFET structure disclosed is similar to the structure in  FIG. 8  except that there is a deep guard ring  960  under said metal field plate in termination area  950 . 
     Please refer to  FIG. 10  for a preferred embodiment of this invention showing the A-B cross section of  FIG. 4  where a trench PT (Punch-through) Type IGBT device cell integrated with gate-collector and gate-emitter clamp diodes is formed on a heavily P+ doped substrate  100  coated with back metal  190  on rear side as collector electrode. Onto said substrate  100 , a heavily N+ doped epitaxial layer  101 ′ and a lightly N doped epitaxial layer  101  are successively grown, and a plurality of trenches are etched wherein. Doped poly is filled into the said trenches padded with a gate insulation layer  120  formed over the inner surface of said trenches. Within these gate trenches filled with doped poly, gate trenches  111  with a wider trench width than contact trenches  612  right below the center of the contact trenches  112  are formed as buffer trenched gates to prevent shortage of the contact trenches  112  to the epitaxial Layer  101  may caused by over etching of contact trenches  112 . P-base regions  102  are extending between every adjacent trench gates  110  with N+ emitter region  103  near the top surface only within active area  140 . Trench emitter-base contacts filled with tungsten plug  113  are formed penetrating through a thick oxide interlayer  104  and emitter region  103 , and extending into P base region  102 , and surrounded with p+ contact area  122  underneath each emitter-base contact bottom to contact the emitter region  103  and the P-base region  102  with emitter metal  105 . Trench gate contacts  114  filled with the tungsten plug are formed penetrating through said oxide interlayer  104  and extending into trench gates  110  to connect the trench gates  110  to gate metal. Collector contacts  115  filled with tungsten plug are formed penetrating through said oxide interlayer and emitter region  103 , and extending into the epitaxial layer  101  to connect collector region with collector metal  107 . There are gate-collector clamp diodes  130  above an oxide layer  124  between the second gate metal pad  108  and collector metal  107 , and gate-emitter clamp diodes  131  above said oxide layer  124  between the first gate metal pad  106  and emitter metal  105 . Said two gate metal pads are wire bonded together on the gate lead frame as shown in  FIG. 5  In termination area  150 , gate metal overlying P-base region  102  and top surface of epitaxial layer  101  also serves as metal field plate and there is a deep guard ring  164  and a floating ring  165  under said metal field plate under said metal field plate as termination. 
     Please refer to  FIG. 11  for another preferred embodiment of this invention showing the A-B cross section of  FIG. 4  where trench NPT (Non-punch-through) type IGBT structure disclosed is similar to the structure in  FIG. 10  except that the device is built on a lightly doped N substrate and P+ region  300  is formed on rear side of the N substrate after backside grinding. 
       FIG. 12A  shows a circuit diagram that illustrates the implementation of an IGBT cell with gate-emitter clamp diode, gate-collector clamp diode and collector shorting diode. Please refer to  FIG. 12B  for another preferred embodiment of this invention showing the A-B cross section of  FIG. 4  where the trench NPT IGBT device disclosed is similar to the structure in  FIG. 11  except the collector comprising alternated P+ and N+ regions on the rear side of the lightly doped N substrate. 
     Although the present invention has been described in terms of the presently preferred embodiments, it is to be understood that such disclosure is not to be interpreted as limiting. Various alternations and modifications will no doubt become apparent to those skilled in the art after reading the above disclosure. Accordingly, it is intended that the appended claims be interpreted as covering all alternations and modifications as fall within the true spirit and scope of the invention.