Abstract:
In accordance with an aspect of the invention, there is provided an SPI interface including a plurality of synchronizers configured to receive a plurality of SPI signals and an internal clock signal and synchronize the received SPI signals using the internal clock signal. The SPI interface also includes an SPI protocol handler configured to receive the synchronized SPI signals and the internal clock signal, and detect and evaluate signal transitions of at least one of the synchronized SPI signals according to an SPI protocol.

Description:
FIELD 
     The invention relates to serial communication with peripheral devices using the Serial Peripheral Interface (SPI) protocol, in particular to an SPI interface for a noisy environment and a method for serial communication via an SPI interface in a noisy environment. 
     BACKGROUND 
     The Serial Peripheral Interface (SPI) protocol is a widely used protocol for data transfer between integrated circuits (ICs), in particular, between a host processor, also called SPI master, and one or more peripherals, also called SPI slaves. The SPI protocol specifies four signals:
     CS: chip select   SCLK: shift clock or serial clock   SDI: shift data in or serial data in   SDO: shift data out or serial data out   It is, however, to be appreciated that alternative naming conventions are also widely used.   

     The SPI protocol is a synchronous protocol which requires a defined timing for correct operation. If an SPI device is working in a noisy environment (e.g. power converters with large switching currents/voltages), glitches may occur on the SPI signals which cause timing violations on the SPI device. The behavior of a conventional SPI device, which receives a timing violation, is unknown. It depends on the implementation (use of analog filters, etc.), but, in the worst case, all flip-flops of the interface become metastable (i.e. the flip-flops are in an unstable state between the “low” and “high” state and will change to one of the stable states “low” or “high” after an undetermined period of time) and may cause random behaviour with severe consequences. 
     In a noisy environment, however, correct timing can not be guaranteed due to the unpredictability of random noise events. In conventional SPI devices, analog filters are commonly used to suppress glitches on the clock signal, but also the use of analog filters cannot totally exclude timing violations due to noise induced events. An analog filter, for example, may pass through a clock pulse which is too small resulting in SPI flip flops becoming metastable. 
     Therefore, there exists a need for a serial peripheral interface which is unsusceptible to timing violations due to e.g. noisy SPI signals and is thus suitable for applications in a noisy environment and a method for serial communication via an SPI interface which is unsusceptible to timing violations and is thus suitable for applications in a noisy environment. 
     SUMMARY 
     In accordance with an aspect of the invention, there is provided an SPI interface comprising a plurality of synchronizers configured to receive a plurality of SPI signals and an internal clock signal to synchronize the received SPI signals using the internal clock signal. The SPI interface also comprises an SPI protocol handler configured to receive the synchronized SPI signals and the internal clock signal and detect and evaluate signal transitions of at least one of the synchronized SPI signals according to an SPI protocol. 
     In accordance with a further aspect of the invention, there is provided a method for serial communication via an SPI interface. The method comprises receiving a plurality of SPI signals and an internal clock signal, synchronizing the plurality of SPI signals using the internal clock signal, and detecting and evaluating signal transitions of at least one of the synchronized SPI signals according to an SPI protocol. 
     Further features, aspects and advantages of the present invention will become apparent from the following detailed description of the invention made with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING(S) 
       The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. 
         FIG. 1  exemplarily shows a simplified schematic diagram of an SPI interface according to an embodiment of the invention. 
         FIG. 2  shows an exemplary method according to an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural or other changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. 
       FIG. 1  exemplarily shows a simplified schematic diagram of an SPI interface according to an embodiment of the invention. 
     The SPI interface illustrated in  FIG. 1  comprises a serial data in (SDI) signal input  11   a , a chip select (CS) signal input  11   b , a serial clock (SCLK) signal input  11   c , a serial data out (SDO) signal output  11   d , an internal clock input  13 , first, second and third synchronizers  12   a ,  12   b  and  12   c , first, second and third digital filters  14   a ,  14   b  and  14   c , an SPI protocol handler  16 , and an output stage  18 . 
     In the embodiment shown in  FIG. 1  the synchronizers  12   a ,  12   b  and  12   c , the digital filters  14   a ,  14   b  and  14   c , the SPI protocol handler  16  and the SPI output stage  18  are connected to the internal clock signal input  13  to receive the internal clock signal. The internal clock signal is provided by an internal well-defined clock, for example, an on-chip oscillator which is not subjected to noise from outside of the chip. Thus, all devices of the SPI are clocked by a well-defined internal clock. 
     In one embodiment of the invention, the synchronizers  12   a ,  12   b  and  12   c  are synchronizer flip-flops. Synchronizer flip-flops are allowed to experience metastability for a certain time interval as they recover from the metastable state after a predefined recovery time. The length of the recovery time has to be smaller than the internal clock period so that the output or result of the synchronizer flip-flops is not used by other synchronous logic (e.g. digital filters and SPI protocol handler) before the predefined recovery time has elapsed. 
     The first synchronizer  12   a  is further connected to the SDI input  11   a  and the first digital filter  14   a . The first synchronizer  12   a  receives an SDI signal from the SDI input  11   a , synchronizes the received SDI signal and outputs the synchronized SDI signal to the first digital filter  14   a.    
     The second synchronizer  12   b  is further connected to the CS input  11   b  and the second digital filter  14   b . The second synchronizer  12   b  receives a CS signal from the CS input  11   b , synchronizes the received CS signal and outputs the synchronized CS signal to the second digital filter  14   b.    
     The third synchronizer  12   c  is further connected to the SCLK input  11   c  and the third digital filter  14   c . The third synchronizer  12   c  receives an SCLK signal from the SCLK input  11   c , synchronizes the received SCLK signal and outputs the synchronized SCLK signal to the third digital filter  14   c.    
     The digital filters  14   a ,  14   b  and  14   c  may check whether a certain number (e.g. 3, 5, 8, etc.) of consecutive samples comprise the same value (e.g. 1) and, if so, output this value as filtering result. Alternatively, the digital filters  14   a ,  14   b  and  14   c  may check whether a certain ratio of a number of consecutive samples (e.g. 4 out of 5, 5 out of 7, etc.) comprise the same value (e.g. 1) and, if so, output this value as filtering result. It is, however, to be appreciated that the invention is not limited to the exemplary filter designs mentioned above but also other filter designs may be utilized. 
     The first digital filter  14   a  receives the synchronized SDI signal from the first synchronizer  12   a , filters the synchronized SDI signal and outputs the synchronized and filtered SDI signal (SDI filt) to the SPI protocol handler  16 . 
     The second digital filter  14   b  receives the synchronized CS signal from the second synchronizer  12   b , filters the synchronized CS signal and outputs the synchronized and filtered CS signal (CS filt) to the SPI protocol handler  16 . 
     The third digital filter  14   c  receives the synchronized SCLK signal from the third synchronizer  12   c , filters the synchronized SCLK signal and outputs the synchronized and filtered SCLK signal (SCLK filt) to the SPI protocol handler  16 . Additionally, the third filter also generates a separate SCLK signal (SCLK fast) which is output to the SPI output stage  18 . This signal, SCLK fast, has a smaller delay than SCLK filt, i.e. SCLK fast has passed less filtering stages than SCLK filt has done. 
     Accordingly, all SPI input signals are synchronized by the synchronizers (in particular synchronizer flip-flops)  12   a ,  12   b  and  12   c  and filtered by the digital filters  14   a ,  14   b  and  14   c  to suppress e.g. single noise events before they get to the SPI protocol handler. Further, all SPI related flip-flops, hereinafter referred to as “SPI flip-flops”, which are the flip-flops comprised in the SPI protocol handler, are clocked with the internal (well-defined) clock. In the SPI interface of  FIG. 1  it is important that the internal clock is faster than the external SPI clock SCLK as, otherwise, the synchronizers  12   a ,  12   b  and  12   c  and digital filters  14   a ,  14   b  and  14   c  would loose some of the transitions contained in the SPI signals. 
     In one embodiment of the invention the digital filter stages of the digital filters  14   a ,  14   b  and  14   c  are equivalent so that the different synchronized and filtered SPI input signals are delayed by the same amount of time. 
     Advantageously, power consumption may be reduced by using clock gating, which, for example, may effect that the digital filters  14   a ,  14   b  and  14   c  are not clocked when the chip select signal is inactive. 
     In this context, it is to be appreciated that in certain embodiments of the invention the chip select signal is a “high-active” signal: When the CS signal is high, “chip select” is active, and when the CS signal is low “chip select” is inactive. In alternative embodiments the chip select signal may also be a “low-active” signal which may be referred to as “nCS signal”. In this case, when the nCS signal is low, “chip select” is active, and when the nCS signal is high, “chip select” is inactive. 
     Hence, in the SPI interface shown in  FIG. 1 , external noise events or glitches (causing SPI timing violations) do not cause timing violations at the SPI flip-flops (i.e. the flip-flops contained in the SPI protocol handler  16 ). Otherwise the SPI flip-flops could become metastable due to external glitches which could cause random behaviour of the SPI flip-flops/SPI interface with severe consequences. 
     The synchronizer flip-flops are the only flip-flops comprised in the SPI interface shown in  FIG. 1  which may experience metastability for a certain time interval as these synchronizer flip-flops recover from the metastable state after a predefined recovery time. 
     The SPI protocol handler  16  receives the synchronized and filtered SPI input signals SDI filt, CS filt, SCLK filt, detects signals transitions (i.e. rising/falling edges) in the received SPI input signals and evaluates the detected signal transitions according to the SPI protocol. 
     In one embodiment of the invention, the digital filters  14   a ,  14   b  and  14   c  additionally generate signals that indicate signal transitions (i.e. rising/falling edges) of the filtered SPI signals. In this case, the SPI protocol handler  16  receives the synchronized and filtered SPI input signals as well as the corresponding signals that indicate the signal transitions of the SPI input signals for evaluation from the digital filters  14   a ,  14   b  and  14   c.    
     An exemplary evaluation of SPI input signals according to the SPI protocol will briefly be described in the following. An SDI access may start with an (e.g. rising) edge of the CS signal. At this point, a shift register comprised in the SPI protocol handler  16  is initialized, i.e. a parallel output value provided by an external source is sampled into the shift register of the SPI protocol handler  16 . 
     The output stage  18  additionally receives a separate SCLK signal, SCLK fast, having a smaller intrinsic delay, which is less filtered than the SCLK signal provided to the SPI protocol handler, SCLK filt. Thus, the reaction time can be reduced so that the output stage  18  can provide the output bit to the SDO output  11   d  shortly after an (e.g. rising) edge of the SCLK signal. 
     The clock signal SCLK fast may comprise some timing variance as it is less filtered than SCLK filt. However, these timing variances can not lead to undefined states as the forwarded values (output bits) are solely provided (and thus defined) by the shift register of the SPI protocol handler which is clocked by the fully filtered SCLK filt signal. 
     Then, after an (e.g. falling) edge of the SCLK signal, the SDI value is “shifted” into the shift register and all bits contained in the shift register are shifted by one position such that the SDI value is sampled into the “first” position of the shift register and the bit located in the “last” position of the shift register, e.g. the MSB, is shifted out of the shift register whereas all other bits in the shift register are shifted by one position. 
     Again, the output stage  18  receives a separate SCLK signal, SCLK fast, having a smaller intrinsic delay, as it is less filtered than the SCLK signal provided to the SPI protocol handler, SCLK filt. Thus, the reaction time can be reduced so that the output stage can provide the output bit to the SDO output  11   d  shortly after a (e.g. rising) edge of the SCLK signal. 
     Then, after another e.g. falling edge of the SCLK signal, the next SDI value is “shifted” into the shift register and all bits contained in the shift register are shifted by one position such that the next SDI value is sampled into the “first” position of the shift register and the bit located in the “last” position of the shift register is shifted out of the shift register whereas all other bits in the shift register are shifted by one position. 
     The above steps are reiterated as long as the chip select signal is active (e.g. CS is high). When the chip select signal becomes inactive (e.g. CS changes to low) the access is completed and the content may be read out and provided as a parallel input value to another on-chip device. In certain embodiments, the chip select signal is active for a fixed number of SCLK cycles which equals the number of bits contained in the shift register so that the whole content of the shift register is replaced during a single SPI access, i.e. all “former” bits are shifted out and are replaced by a corresponding number of received SDI values successively sampled into the shift register. 
     In one embodiment of the invention, the SPI protocol handler additionally monitors the outputs of the digital filters in order to perform additional SPI protocol checks and/or evaluations, such as:
         checking whether there was an active edge on the chip select signal before the SPI clock started clocking;   checking whether at least one (e.g. falling) edge of the SCLK signal occurred;   checking whether a predefined number of (e.g. falling) edges of the SCLK signal occurred;   evaluating time intervals between edges of the SCLK signal; and   evaluating lengths of the SPI signals.       

     Based on the result of the SPI protocol checks and/or evaluations, the SPI protocol handler  16  determines whether the SPI access was valid or not. In case the access was invalid, the access is ignored and identified as invalid, i.e. all data received in this access is dropped, and the SPI protocol handler  16  advantageously sets an error flag bit. 
     Hence, the SPI interface shown in  FIG. 1  ensures defined SPI behaviour by preventing external SPI signals from being (directly) connected to critical SPI flip-flop inputs. Even in the case of SPI timing violations during an access, defined SPI behaviour is guaranteed: If timing violations in an SPI access are detected, the respective SPI access is identified as corrupt, all data received in this access is dropped and an error flag may additionally be set. 
       FIG. 2  shows an exemplary method according to an embodiment of the invention. The method for serial communication via an SPI interface comprises: receiving a plurality of SPI signals and an internal clock signal at  202 , and synchronizing the plurality of SPI signals using the internal clock signal at  204 . The method further comprises digitally filtering the synchronized SPI signals at  206 , and detecting and evaluating signal transitions of at least one of the synchronized and filtered SPI signals according to the SPI protocol at  208 . 
     Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.