Abstract:
A system and a method for protecting vias is disclosed. An embodiment comprises forming an opening in a substrate. A barrier layer disposed in the opening including along the sidewalls of the opening. The barrier layer may include a metal component and an alloying material. A conductive material is formed on the barrier layer and fills the opening. The conductive material to form a via (e.g., TSV).

Description:
PRIORITY CLAIM AND CROSS-REFERENCE 
       [0001]    This application is a continuation of U.S. patent application Ser. No. 13/730,162, filed Dec. 28, 2012 which is a continuation of U.S. patent application Ser. No. 12/631,172, filed on Dec. 4, 2009, which claims the benefit of U.S. Provisional Patent Application Ser. No. 61/162,529, filed on Mar. 23, 2009, which applications are incorporated herein by reference. 
     
    
     TECHNICAL FIELD 
       [0002]    The present invention relates generally to semiconductor devices and, more particularly, to barrier layers for through-silicon vias. 
       BACKGROUND 
       [0003]    Generally, through-silicon vias (TSVs) are formed in a semiconductor wafer by initially forming an opening at least partially through a substrate. A barrier layer is formed to line the opening in order to prevent a later-formed conductive material (e.g., copper) from diffusing into the substrate, where it might deteriorate the overall performance of other devices formed on the semiconductor wafer. As such, this barrier layer prevents damage caused by the conductive material. 
         [0004]    However, the barrier layer is typically formed through a physical vapor deposition (PVD) process, which generally has a poor step coverage. This poor step coverage results in the barrier layer having a smaller thickness at the bottom of the TSV opening along the sidewalls, and can induce a problem with the continuity of the barrier. Such a problem with continuity may result in gaps of coverage, which would not only allow conductive material to diffuse into the substrate, but may also cause problems during subsequent electroplating of conductive material into the opening. 
         [0005]    One solution to this discontinuity is to simply continue the PVD barrier formation process until the continuity of the barrier layer in the TSV opening has been assured. However, this process also increases the thickness of the barrier layer on the surface of the substrate (outside of the TSV opening). This increase in thickness can cause variation problems after the barrier layer has been removed from the surface by a chemical mechanical polishing (CMP) process. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
           [0007]      FIG. 1  illustrates a through-silicon via (TSV) opening formed through a substrate and an interlayer dielectric in accordance with an embodiment of the present invention; 
           [0008]      FIG. 2  illustrates the formation of a liner to cover the sidewalls and bottom of the opening in accordance with an embodiment of the present invention; 
           [0009]      FIG. 3  illustrates the formation of a barrier layer over the liner in accordance with an embodiment of the present invention; 
           [0010]      FIG. 4  illustrates the formation of a seed layer over the barrier layer in accordance with an embodiment of the present invention; 
           [0011]      FIG. 5  illustrates the formation of conductive material over the seed layer in accordance with an embodiment of the present invention; 
           [0012]      FIG. 6  illustrates the formation of additional connections to the TSV in accordance with an embodiment of the present invention; 
           [0013]      FIG. 7  illustrates an embodiment of the present invention in which an adhesion layer is formed between a liner and a barrier layer in accordance with an embodiment of the present invention; and 
           [0014]      FIG. 8  illustrates an embodiment of the present invention in which adhesion layers are formed on opposing sides of the barrier layer. 
           [0015]    Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. 
       
    
    
     DETAILED DESCRIPTION 
       [0016]    The making and using of embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention. 
         [0017]    The present invention will be described with respect to embodiments in a specific context, namely a barrier layer for a through-silicon via (TSV). The invention may also be applied, however, to other barrier layers. 
         [0018]    With reference now to  FIG. 1 , there is shown a substrate  101 , active devices  103  formed on the substrate  101 , an interlayer dielectric (ILD)  105  over the substrate  101 , a contact  107  to the active devices  103  through the ILD  105 , and an opening  109  formed through the ILD  105  and into the substrate  101 . The substrate  101  comprises a first side  111  and a second side  113  opposite the first side  111 , and may comprise bulk silicon, doped or undoped, or an active layer of a silicon-on-insulator (SOl) substrate. Generally, a SOl substrate comprises a layer of a semiconductor material such as silicon, germanium, silicon germanium, SOl, silicon germanium on insulator (SGOI), or combinations thereof. Other substrates that may be used include multi-layered substrates, gradient substrates, or hybrid orientation substrates. 
         [0019]    The active devices  103  are represented on  FIG. 1  as a single transistor on the first side  111  of the substrate  101 . However, as one of ordinary skill in the art will recognize, a wide variety of active devices such as capacitors, resistors, inductors, combinations of these, or the like may be used to generate the desired structural and functional requirements of the overall design. The active devices  103  may be formed using any suitable methods either within or on the surface of the substrate  101 . 
         [0020]    The ILD  105  is formed over the substrate  101  and active devices  103  by chemical vapor deposition, sputtering, or any other method known and used in the art for forming an ILD  105 . The ILD  105  typically has a planarized surface and may be comprised of silicon oxide, although other materials, such as high-k materials, could alternatively be utilized. Optionally, the ILD  105  may be formed so as to impart a strain to the substrate  101  within the active devices  103 , which will increase the overall performance of the active devices  103 , as is known in the art. 
         [0021]    The contact  107  extends through the ILD  105  to make electrical contact with at least one of the active devices  103 . The contact  107  may be formed through the ILD  105  in accordance with known photolithography and etching techniques. Generally, photolithography techniques involve depositing a photoresist material, which is masked, exposed, and developed to expose portions of the ILD  105  that are to be removed. The remaining photoresist material protects the underlying material from subsequent processing steps, such as etching. Photoresist material is utilized to create a patterned mask to define the contact  107 . Alternative masks, such as a hardmask, may also be used. 
         [0022]    The contact  107  may comprise a barrier/adhesion layer (not shown) to prevent diffusion and provide better adhesion between the contact  107  and the ILD  105 . In an embodiment, the barrier layer is formed of one or more layers of titanium, titanium nitride, tantalum, tantalum nitride, or the like. The barrier layer may be formed through chemical vapor deposition, although other techniques could alternatively be used. The barrier layer may be formed to a combined thickness of about 10 Å to about 500 Å. 
         [0023]    The contact  107  may be formed of any suitable conductive material, such as a highly-conductive, low-resistive metal, elemental metal, transition metal, or the like. In an exemplary embodiment the contacts  107  are formed of tungsten, although other materials, such as copper, could alternatively be utilized. In an embodiment in which the contact  107  is formed of tungsten, the contact  107  may be deposited by CVD techniques known in the art, although any method of formation could alternatively be used. 
         [0024]    The opening  109  may be formed by applying and developing a suitable photoresist (not shown), and then etching the ILD  105  and at least a portion of the substrate  101 . The opening  109  is formed so as to extend into the substrate  101  at least further than the active devices  103  formed within and on the substrate  101 , and at least to a depth greater than the eventual desired height of the substrate  101 . Accordingly, while the depth of the opening  109  from the surface of the substrate  101  is dependent upon the overall design of the desired chip, the depth may be between about 20 μm and about 190 μm, such as about 50 μm. Further, the opening  109  may have a diameter of between about 2 μm and about 70 μm, such as about 5 μm. 
         [0025]    However, as one of ordinary skill in the art will recognize, the method described to form the opening  109  through only the ILD  105  and the substrate  101  is not the sole method of formation that may be utilized. Alternatively, the opening  109  may be formed concurrently with the formation of the ILD  105  and any other individual layers (e.g., dielectric and metal layers) as the layers are being built upwards from the substrate  101 . Any method of formation to form the opening  109  is intended to be included within the scope of the present invention. 
         [0026]      FIG. 2  illustrates the formation of a liner  201  over the ILD  105 , the liner  201  covering the sidewalls and bottom of the opening  109 . The liner  201  may be either tetraethylorthosilicate (TEOS) or silicon nitride, although any suitable dielectric may alternatively be used. The liner  201  may be formed using a plasma enhanced chemical vapor deposition (PECVD) process, although other suitable processes, such as physical vapor deposition or a thermal process, may alternatively be used. 
         [0027]      FIG. 3  illustrates the formation of a barrier layer  301  over the liner  201  and also covering the sidewalls and bottom of the opening  109 . The barrier layer  301  may be formed so as to conformally cover the liner  201  and the sidewalls and bottom of the TSV opening  109  with a thickness of between about 10 Å and about 1,000 Å, such as between about 20 Å and about 100 Å. By forming the barrier layer  301  conformally, the barrier layer will have a substantially equal thickness along the sidewalls of the opening  109  and also along the bottom of the openings  109 , which will reduce or eliminate problems with the continuity of the barrier layer  301  without increasing the thickness of the barrier layer  301  outside of the opening  109 . 
         [0028]    Furthermore, while the barrier layer  301  may be a completely conformal barrier layer  301 , some variation in the conformality of the barrier layer thickness has been found to still have beneficial effects. For example, a barrier layer  301  with variations in thickness of less than about 20% still maintain beneficial effects over prior art methods of forming the barrier layer  301 . 
         [0029]    The barrier layer  301  may be formed using a process that will promote a conformal formation, such as atomic layer deposition (ALD). In this process the liner  201  is exposed to chemical precursors that may contain carbon or fluorine, such as a metal-organic material or TaF 5 , that will form a single atomic layer of the material of the barrier layer  301  without the addition of extra material. As such, a completely conformal layer of material is formed. This process is then repeated in order to build up multiple single layers of either the same material or different materials until a desired thickness is obtained. 
         [0030]    However, ALD is not the only acceptable method of formation. Other processes such as plasma enhanced chemical vapor deposition (PECVD) or plasma enhanced physical vapor deposition (PEPVD), wherein a bias is applied to the substrate in order to lessen variations in the thickness of the barrier layer  301 , may alternatively be used. However, if these processes are used, the process parameters, such as the bias on the substrate, are controlled to at least reduce the variation in the thickness of the barrier layer  301  to below the variation of less than about 20% as described above. Given this, the bias applied to the substrate may range from between about 100 Wand about 3000 W, depending upon the process conditions and the depth of the opening  109 . As merely one example, for an opening with a depth of about 50 μm, a bias of between about 500 W and about 2,000 W may be applied to the substrate  101 . 
         [0031]    The barrier layer  301  comprises tantalum nitride, although other materials, such as tantalum, titanium, titanium nitride, combinations of these, and the like may alternatively be used. Additionally, in this embodiment the barrier layer  301  may be alloyed with an alloying material such as carbon or fluorine, although the alloyed material content is generally no greater than about 15% of the barrier layer  301 , and may be less than about 5% of the barrier layer  301 . The alloying material may be introduced by one of the precursors during formation of the barrier layer  301  in the ALD, PECVD, or PEPVD processes. 
         [0032]      FIG. 4  illustrates the formation of a seed layer  401  over the barrier layer  301 . The seed layer  401  may be deposited by PVD or CVD, and may be formed of copper, although other methods and materials may alternatively be used if desired. Additionally, while the thickness of the seed layer  401  will be dependent at least in part on the depth of the opening  109 , the seed layer  401  may have a thickness of between about 50 Å and about 1,000 Å. For example, for an opening  109  with a depth of about 50 μm, the seed layer  401  may have a depth of between about 50 Å and about 500 Å, such as about 200 Å. 
         [0033]    Optionally, the seed layer  401  may also be alloyed with a material that improves the adhesive properties of the seed layer  401  so that it can act as an adhesion layer. For example, the seed layer  401  may be alloyed with a material such as manganese or aluminum, which will migrate to the interface between the seed layer  401  and the barrier layer  301  and will enhance the adhesion between the two layers. The alloying material may be introduced during formation of the seed layer, and may comprise no more than about 10% of the seed layer, such as about less than 5%. 
         [0034]      FIG. 5  illustrates the plating of a conductive material  501  onto the seed layer  401 . The conductive material  501  may comprise copper, although other suitable materials such as aluminum, alloys, doped polysilicon, combinations thereof, and the like, may alternatively be utilized. The conductive material  501  may be formed by electroplating copper onto the seed layer  401 , filling and overfilling the openings  109 . Once the openings  109  have been filled, excess liner  201 , barrier layer  301 , seed layer  401 , and conductive material  501  outside of the openings  109  may be removed through a planarization process such as chemical mechanical polishing (CMP), although any suitable removal process may be used. 
         [0035]      FIG. 6  illustrates further process steps in the formation of a TSV. Metallization layers  607  may be formed over the first side  111  of the substrate  101  and are designed to connect the active devices  103  to form functional circuitry and also to form a connection to the second side  113  of the substrate  101  through the TSV  601 . The metallization layers  607  may be formed of alternating layers of dielectric and conductive material and may be formed through any suitable process (such as deposition, dual damascene, etc.). Furthermore, while there may be four or more layers of metallization separated from the substrate  101  by the ILD  105 , the precise number of metallization layers  607  is dependent upon the overall design of the structure. 
         [0036]    A second passivation layer  609  may be formed over the metallization layers  607 , in order to seal and protect the metallization layers  607 . The second passivation layer  609  may comprise a dielectric material such as an oxide or silicon nitride, although other suitable dielectrics, such as a high-k dielectric or polyimide, may alternatively be used. The second passivation layer  609  may be formed using a PECVD process, although any other suitable process may alternatively be used. The second passivation layer  609  has a thickness of between about 0.6 μm and about 1.4 μm, such as about 1 μm. 
         [0037]    Once formed the second passivation layer  609  is patterned to expose at least a portion of an uppermost conductive layer of the metallization layers  607 . The second passivation layer  609  may be patterned using a suitable photolithographic technique, wherein a light-sensitive photoresist (not shown) is applied to the second passivation layer  609  exposed and developed to form a photoresist. Once developed, exposed portions of the second passivation layer  609  may be removed using a suitable etchant to expose at least a portion of the uppermost conductive layer of the metallization layers  607 . 
         [0038]      FIG. 6  also illustrates the formation of an underbump metallization (UBM)  611  through the second passivation layer  609 . The UBM  611  is intended to act as an intermediary between the metallization layer  607  and contacts (not shown) that are intended to connect the circuitry to other devices. The UBM  611  may be formed so as to make physical and electrical contact with the uppermost conductive layer of the metallization layers  607 . The UBM  611  may be made of at least three layers of conductive materials, such as a layer of chrome, a layer of a chrome-copper alloy, and a layer of copper, with an optional layer of gold over the top of the copper layer. However, one of ordinary skill in the art will recognize that there are many suitable arrangements of materials and layers, such as an arrangement of titanium/titanium tungsten/copper or an arrangement of copper/nickel/gold, that are suitable for the formation of the UBM  611 . Any suitable materials or layers of material that may be used for the UBM  611  are fully intended to be included within the scope of the current application. 
         [0039]    The UBM  611  may be created by forming each layer conformally over an opening through the second passivation layer  609 . The forming of each layer may be performed using a CVD process, such as PECVD, although other processes of formation, such as sputtering, evaporation, or plating process, may alternatively be used depending upon the desired materials. Each of the layers within the UBM  611  may have a thickness of between about 10 μm and about 100 μm, such as about 45 μm. Once the desired layers have been formed, portions of the layers are then removed through a suitable photolithographic masking and etching process to remove the undesired material and to leave the patterned UBM  611 . 
         [0040]    Once excess conductive material  501  has been removed from the front side of the substrate  101 , portions of the second side  113  of the substrate  101  are then removed to expose the conductive material  501  located within the opening  109  to complete the TSV  601 . The removal may be performed with a grinding process such as a chemical mechanical polish (CMP), although other suitable processes, such as etching, may alternatively be used. The removal of the second side  113  of the substrate  101  may be continued until the substrate  101  has a thickness of between about 10 μm and about 200 μm, such as between about 25 μm and about 100 μm. 
         [0041]    After the removal of a portion of the second side  113  of the substrate  101 , a second etch may be performed. This second etch is intended to clean and polish the substrate  101  after the CMP. Additionally, this second etch also helps release stresses that may have formed during the CMP process of grinding the substrate  101 . The second etch may use HNO3, although other suitable etchants may alternatively be used. 
         [0042]    Finally, after a cleaning process to remove any remaining polishing residue such as copper oxide, a contact  605  may be formed on the second side  113  of the substrate  101  in electrical contact with the conductive material  501  located within the TSV  601 . The contact  605  may comprise a conductive layer (not shown) and an ENIG layer (not shown). The conductive layer may comprise aluminum and may be formed through a sputter deposition process. However, other materials, such as nickel or copper, and other formation processes, such as electroplating or electroless plating, may alternatively be used. The conductive layer may be formed with a thickness of between about 0.5 μm and about 3 μm, such as about 2 μm. 
         [0043]    The formation of the conductive layer may be followed by an Electroless Nickel Gold (ENIG) process to form an ENIG layer opposite the conductive layer from the substrate  101 . The ENIG process provides for a flat, uniform metal surface finish for the formation of contacts to other devices (not shown). The ENIG process may comprise cleaning the conductive layer, immersing the substrate  101  in a zincate activation solution, electrolessly plating nickel onto the conductive layer, and electrolessly plating gold onto the nickel. The ENIG layer may be formed to a thickness of between about 2 μm and about 4 μm, such as about 3 μm. Once formed, the conductive layer and the ENIG layer are patterned into the shape of the contact  605  by a suitable photolithographic process and unwanted material is removed through a suitable etching process. 
         [0044]    A first passivation layer  608  may be formed over the contact  605  in order to seal and protect the structures on the second side  113  of the substrate  101 . The first passivation layer  608  may comprise a dielectric material such as an oxide or silicon nitride, although other suitable dielectrics, such as a high-k dielectric, may alternatively be used. The first passivation layer  608  may be formed using a plasma enhanced chemical vapor deposition (PECVD) process, although any other suitable process may alternatively be used. The first passivation layer  608  may have a thickness of between about 0.6 μm and about 1.4 μm, such as about 1 μm. Once formed, the first passivation layer  608  may be patterned using a suitable masking and etching technique in order to expose at least a portion of the contact  605 , in order to allow exterior devices (not shown) to be connected to the contact  605 . 
         [0045]      FIG. 7  illustrates an alternative embodiment of the present invention. In this embodiment, the substrate  101 , the ILD  105 , the opening  109 , liner  201 , and the barrier layer  301  may be formed in a similar manner as the method described above with respect to  FIGS. 1-2 . In this embodiment, a first adhesion layer  701  is formed between the barrier layer  301  and the seed layer  401 . The first adhesion layer  701  may be formed of a combination of tantalum and tantalum nitride using a PVD process, although other adhesive materials, such as titanium or titanium nitride, and other methods of formation, such as CVD or ALD, may alternatively be utilized. The first adhesion layer  701  may comprise a first adhesive layer of tantalum with a thickness of between about 10 Å and about 300 Å, such as about 150 Å, and a second adhesive layer of tantalum nitride with a thickness between about 10 Å and about 100 Å, such as about 30 Å. 
         [0046]    Additionally, because the first adhesion layer  701  is used at the interface of the barrier layer  301  and the seed layer  401 , the seed layer  401  may not contain the adhesive alloys that were utilized to enhance the adhesion of the seed layer  401  to the barrier layer  301  in the embodiment described above with respect to  FIGS. 1-6 . As such, a pure conductive material, such as pure copper, may be utilized for the seed layer  401  with this addition of a separate adhesive layer such as tantalum. 
         [0047]    In this embodiment, once the seed layer  401  has been formed, the remainder of the formation process may be completed in a similar fashion as the method described above with respect to  FIGS. 1-6 . 
         [0048]      FIG. 8  illustrates an alternative to the embodiment described above in  FIG. 7 . In this embodiment, in addition to the first adhesion layer  701  formed between the barrier layer  301  and the seed layer  401 , a second adhesion layer  801  is formed between the barrier layer  301  and the liner  201 . In this fashion, the first adhesion layer  701  and the second adhesion layer  801  are located on either side of the barrier layer  301 . Furthermore, in this embodiment, the second adhesion layer  801  may be formed of similar materials and in a similar fashion as the first adhesion layer  701  described above with respect to  FIG. 7 . 
         [0049]    These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by embodiments of the present invention which provide for a semiconductor barrier layer that reduces problems associated with processing variations. 
         [0050]    In accordance with an embodiment of the present invention, a semiconductor device comprises a substrate having an opening and a liner formed along sidewalls of the opening. A barrier layer overlies the liner along the sidewalls of the openings, and the barrier layer comprises carbon or fluorine. A seed layer overlies the barrier layer along the sidewalls of the opening, and a conductive material is formed on the seed layer and filling the opening. 
         [0051]    In accordance with another embodiment of the present invention, a method of manufacturing a semiconductor device comprises providing a substrate with an opening located therein and forming a barrier layer along sidewalls and a bottom of the opening using an atomic layer deposition process. A seed layer is formed overlying the barrier layer and a conductive material is formed on the seed layer filling the opening. 
         [0052]    An advantage of an embodiment of the present invention allows for better coverage of the sidewalls without causing variation problems in other parts of the device. 
         [0053]    Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. 
         [0054]    For example, the openings may be formed in a variety of methods, and the barrier layer may be formed using a variety of conformal methods. 
         [0055]    Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods, and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.