Abstract:
A method for fabricating a semiconductor lighting chip includes steps of providing a substrate with an epitaxial layer thereon. The epitaxial layer comprises a first semiconductor layer, an active layer and a second semiconductor layer successively grown on the substrate. The epitaxial layer has dislocation defects traversing the first semiconductor layer, the active layer and the second semiconductor layer. The epitaxial layer is then subjected to an etching process which remove parts of the second semiconductor layer and the active layer along the dislocation defects to form recesses recessing from the second semiconductor layer to the active layer. Thereafter a first electrode and a second electrode are formed on the first semiconductor layer and the second semiconductor layer, respectively.

Description:
TECHNICAL FIELD 
       [0001]    The disclosure generally relates to a method for fabricating a semiconductor lighting chip. 
       DESCRIPTION OF RELATED ART 
       [0002]    In recent years, due to excellent light quality and high luminous efficiency, light emitting diodes (LEDs) have increasingly been used as substitutes for incandescent bulbs, compact fluorescent lamps and fluorescent tubes as light sources of illumination devices. 
         [0003]    Due to lattice mismatch between epitaxial layers and epitaxial substrates, dislocation will appear during the growth of the epitaxial layers. The minority carriers will be captured by the dislocation and release heat in a form of nonradiative recombination, therefore reducing luminescent efficiency of the lighting chip. 
         [0004]    Therefore, a method for fabricating a semiconductor lighting chip is desired to overcome the above described shortcomings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]    Many aspects of the disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views. 
           [0006]      FIG. 1  is a diagram showing a first step of a method for fabricating a semiconductor lighting chip according to an embodiment of the present disclosure. 
           [0007]      FIG. 2  is a diagram showing a second step of the method for fabricating a semiconductor lighting chip. 
           [0008]      FIG. 3  is a diagram showing a third step of the method for fabricating a semiconductor lighting chip. 
           [0009]      FIG. 4  is a diagram showing a fourth step of the method for fabricating a semiconductor lighting chip. 
           [0010]      FIG. 5  is a diagram showing a fifth step of the method for fabricating a semiconductor lighting chip. 
       
    
    
     DETAILED DESCRIPTION 
       [0011]    An embodiment of a method for fabricating a semiconductor lighting chip will now be described in detail below and with reference to the drawings. 
         [0012]    Referring to  FIG. 1 , a substrate  10  with an epitaxial layer  20  formed thereon is provided. Materials of the substrate  10  can be selected from a group consisting of sapphire, SiC, Si and GaN. In this embodiment, the substrate  10  is made of sapphire and a thickness of the substrate  10  ranges between 300 μm and 600 μm. In this embodiment, the thickness of the substrate  10  is 430 μm. 
         [0013]    The substrate  10  defines a number of grooves  12  in an upper surface thereof. The grooves  12  are arranged at intervals and formed by wet etching or other method, whereby the remaining portion of the upper surface of the substrate  10  between the grooves  12  is formed with protrusions  14 . The grooves  12  and the protrusions  14  are alternatively positioned along the upper surface of the substrate  10  from a lateral side to an opposite lateral side of the substrate  10 . That is, each of the protrusions  14  is formed between each two neighboring grooves  12 , and each of the grooves  12  is formed between each two neighboring protrusions  14 . A depth of each of the grooves  12  ranges between 0.3 μm and 1.5 μm, which is determined by etching time and etching solutions. In this embodiment, the depth of each of the grooves  12  is 1 μm to achieve a desired pattern on the substrate  10 . 
         [0014]    In order to improve growth quality of the epitaxial layer  20  on the substrate  10 , a buffer layer  60  is formed in the groove  12  of the substrate  10  by low-temperature growth techniques before growing the epitaxial layer  20 . A thickness of the buffer layer  60  is 20 nm, which is suitable for growth of the epitaxial layers  20 . The buffer layer  60  can be made of AlN or GaN and has a lattice constant matching that of the epitaxial layers  20 , therefore reducing dislocation defects  22  in the epitaxial layer  20 . 
         [0015]    The epitaxial layer  20  includes a first semiconductor layer  30 , an active layer  40  and a second semiconductor layer  50  subsequently formed on the substrate  10 . In this embodiment, the first semiconductor layer  30  is an n-type GaN layer, the second semiconductor layer  50  is a p-type GaN layer and the active layer  40  is a multiple quantum well (MQW) layer. A thickness of the first semiconductor layer  30  is 4 μm, a thickness of the second semiconductor layer  50  is 0.1 μm and a thickness of the active layer  40  is 0.125 μm. 
         [0016]    For further reducing the dislocation defects  22 , the epitaxial layer  20  can be formed on the substrate  10  by epitaxial lateral overgrowth (ELO), FIELO (facet-initialed ELO), Pendeo-epitaxy, or facet-controlled ELO (FACELO). In this embodiment, the epitaxial layer  20  is grown by FIELO technique. The dislocation defects  22  formed in the epitaxial layer  20  will mostly gather at a region right above the protrusions  14  of the substrate  10 , because the dislocation defects  22  above the grooves  12  shift from their original positions. The dislocation defects  22  traverse the first semiconductor layer  30 , the active layer  40  and the second semiconductor layer  50 . 
         [0017]    Referring to  FIG. 2 , a number of recesses  24  are formed by wet etching the upper surface of the second semiconductor layer  50 . The etching solution of the wet etching can be KOH or H 3 PO 4 . Because a surface energy of the dislocation defects  22  is lower than that of other portion of the epitaxial layer  20 , and the dislocation defects  22  can easily react with the etching solution, the etching will begin from the position of the dislocation defects  22  in the second semiconductor layer  50  and downwards to the first semiconductor layer  30 . Due to that a surface energy of the (10-1-1) plane of the epitaxial layer  20  is the lowest, the etching solution will etch the (10-1-1) plane to form the recesses  24  with a triangle-shaped profile. 
         [0018]    By controlling the etching time, a depth of each of the recesses  24  can be controlled in a range from 0.1 μm to 1 μm. In this embodiment, the recesses  24  extend downwards to the bottom of active layer  40  and a depth of each of the recesses  24  is about 0.225 μm. Accordingly, most of the dislocation defects  22  in the active layer  40  will be removed by etching. Recombination rate of holes and electrons will be improved and therefore increasing lighting efficiency of the semiconductor lighting chip. 
         [0019]    Furthermore, the recesses  24  formed by etching can increase the surface area of the active layer  40  and help light emitted from the active layer  40  to travel to a surrounding environment. Besides, due to inclined sidewalls of the recesses  24 , a width of each of the recesses  24  formed by the wet etching gradually decreases along a top-to-bottom direction of the epitaxial layer  20 . Compared with recesses with vertical sidewalls by dry etching, light emitted from the active layer  40  will easily travel to the surrounding environment via the inclined sidewalls of the recesses  24  and light extraction efficiency of the semiconductor lighting chip is improved thereby. On the other hand, downward light emitted from the active layer  40  will be reflected back by the protrusion  14 , as shown in  FIG. 5 . 
         [0020]    Referring to  FIG. 3 , an insulation layer  70  is formed on the epitaxial layer  20  by plasma chemical vapor deposition (PECVD), sol-gel method, E-beam gun evaporation, ion beam sputtering or physical vapor deposition. The insulation layer  70  fills the recesses  24  and covers the upper surface of the second semiconductor layer  50 . The insulation layer  70  is for limiting the current path in the cone-shaped active layer  40  and the second semiconductor layer  50 , and preventing conducive materials employed in later processes from entering the recesses  24 . The insulation layer  70  can be made of SiO 2 , and a thickness of the insulation layer  70  ranges between 0.1 μm and 0.2 μm. 
         [0021]    After that, referring to  FIG. 4 , a part of the insulation layer  70  right above the second semiconductor layer  50  is removed, and the other part of the insulation layer  70  remains in the recesses  24 . The method for removing the insulation layer  70  includes but is not limited to chemical-mechanical polish (CMP), wet etching and dry etching. Thereafter, a transparent conductive layer  80  is formed on the upper surfaces of the second semiconductor layer  50  and the insulation layer  70  by vacuum evaporation, sputtering, chemical vapor deposition or E-gun evaporation. The transparent conductive layer  80  can be made of conductive materials such as indium-tin oxide (ITO) or Ni—Au alloy, therefore making current distributing uniformly on the second semiconductor layer  50 . Due to the current blocking function of the insulation layer  70  remained in the recesses  24 , current will flow to the first semiconductor layer  30  through the second semiconductor layer  50  and the active layer  40  sandwiched between each two adjacent recesses  24 . 
         [0022]    Finally, referring to  FIG. 5 , parts of the transparent conductive layer  80 , the insulation layer  70  and the first semiconductor layer  30  are etched away by photolithography technology to expose a part of a top of the first semiconductor layer  30 , which functions as an electrode supporting region. And then, a first electrode  90  is formed on the electrode supporting region by vacuum evaporation, sputtering, chemical vapor deposition or E-gun evaporation. After that, a second electrode  92  is formed on an upper surface of the transparent conductive layer  80 . 
         [0023]    The semiconductor lighting chip fabricated by the above-disclosed method has a relatively high lighting efficiency, and therefore can be widely used in high lumen solid state lamps. 
         [0024]    The semiconductor lighting structure in the present invention relates to light-emitting diode chips and laser diode chips, which is formed by semiconductor materials and capable of emitting light. 
         [0025]    It is believed that the present embodiments and their advantages will be understood from the foregoing description, and it will be apparent that various changes may be made thereto without departing from the spirit and scope of the disclosure or sacrificing all of its material advantages, the examples hereinbefore described merely being preferred or exemplary embodiments of the disclosure.