Abstract:
A method and apparatus for Time Division Duplex (TDD) synchronization of Access Points (APEs) uses the 1 pulse-per-second timing pulses of the Global Positioning System (GPS) and synchronization state machines for its Time Division Multiple Access (TDMA) structure. As a result, the present invention obviates the need for expensive voltage-controlled oscillators used by the prior art, and achieves stable timing accuracy within approximately 7.5 minutes, as opposed to the 12 to 24-hour period needed by prior art methods.

Description:
FIELD OF THE INVENTION 
   The present invention broadly relates to Time Division Duplex systems. More particularly, the present invention relates to improvements in the temporal alignment of the components in Time Division Duplex systems. 
   BACKGROUND OF RELATED ART 
   Time Division Duplex (TDD) systems allow one or more Access Points (APEs) to bidirectionally communicate with Customer Premises Equipment (CPE) such as mobile telephones. As many APEs (also known as hubs) and a multitude of CPEs may be operational in a system, it is important that strict timing protocols be observed to avoid communication conflicts. In multi-sectored systems, time slots allotted to each sector also include guard times to prevent the activity of one sector from encroaching upon the designated time slots of other sectors. 
   Typical prior art TDD systems incorporate highly stable voltage controlled oscillators (VCOs) in the hubs to provide accurate timing control. In addition to being expensive, such approaches also require transient periods of up to twenty-four hours before the local oscillator has achieved suitable stabilization. 
   There is a great need to provide in a TDD system, a Time Division Multiple Access architecture that incorporates timing generators that are both low cost, and that achieve stabilization shortly after they are activated. 
   SUMMARY OF THE INVENTION 
   In view of the above-identified problems and limitations of the prior art, the present invention provides in a Time Division Duplex (TDD) system, an apparatus for temporally aligning Access Points (APEs) in the system. The apparatus at least includes a Global Positioning System (GPS) receiver adapted to receive GPS timing signals, an APE local oscillator, and a timing generator having a dead time counter, the timing generator coupled to the local oscillator and adapted to generate a System Timing signal. The apparatus also at least includes a phase error detector adapted to compare the GPS timing signals with a symbol clock signal derived from the System Timing signal, and a synchronization state machine coupled to the phase error detector. The synchronization state machine generates synchronization information in response to the output of the phase error detector; and the synchronization information is adapted to adjust the frequency of the local oscillator via the dead time counter. 
   The present invention also provides in a TDD system, a method for temporally aligning APEs in the system. The method at least includes the steps of receiving GPS timing signals, via an APE local oscillator, generating an APE reference clock signal, and via a timing generator having a dead time counter, generating a System Timing signal. The method also at least includes the steps of detecting a phase error between the GPS timing signals and a symbol clock signal derived from the System Timing signal, and via a synchronization state machine coupled to the phase error detector, generating synchronization information in response to the output of the phase error detector. The synchronization information in response to the output of the phase error detector. The synchronization information is adapted to adjust the frequency of the local oscillator via the dead time counter. 
   The present invention is described in detail below, with reference to the drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Features and advantages of the present invention will become apparent to those skilled in the art from the following description with reference to the drawings, in which: 
       FIG. 1  is a general schematic block diagram of a time division duplex system with synchronization according to the present invention; 
       FIG. 2  is a schematic block diagram of an Access Point (Hub) constructed according to the present invention; 
       FIG. 3  is a schematic block diagram of a baseband combiner used in the Access Point of  FIG. 2 , which baseband combiner is constructed according to the present invention; and 
       FIG. 4  is schematic block diagram of a modem subsumed by customer premises equipment, which modem is constructed according to the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1  is a general schematic block diagram of a Time Division Duplex system  100  with components that are temporally aligned according to the present invention. As is shown in the figure, several Access Points (APEs), which are also known as “hubs,” engage in duplex communication with a number of Customer Premises Equipment (CPE) devices  120 , such as mobile telephones. Each hub is responsible for communicating with all of the CPEs currently located in its designated cell. 
   In the example of  FIG. 1 , each of the cells ( 101 ,  102  and  103 ) has a different number of sectors for illustrative purposes. APE  1  in cell  101  has a three sector configuration, while APE  2  in cell  102  has a six sector configuration. However, APE  3  in cell  103  has an “omni” configuration (one sector representing 360 degrees). Those skilled in the art will appreciate that different numbers of sectors of different sizes can be included in the cells of the system  100  without departing from the essence of the present invention. The APE  2  is of the master/slave variety, having a master component APE  2  M and a slave component APE  2  S. 
   Proper operation of the TDD system  100  requires that the APEs have synchronized clocks so that the transmit and receive operations of one sector occur during a designated time slot, and do not overlap into the designated time slots of other sectors. Proper operation of the TDD system also requires that all of the CPEs  120  in communication with an APE  110  be synchronized with the APE  110 . 
   The synchronization of the components of the present-inventive TDD system is explained below, with reference to  FIGS. 2–4 . 
   A general schematic block diagram of the APEs  110  of the present invention appears in  FIG. 2 . The APE  110  is connected to a Global Positioning System (GPS) antenna  210  via an egress panel  220 . A GPS receiver  230  receives a GPS signal via the egress panel and the GPS antenna. Under the control of an APE Control Processor  240  which is interfaced to the GPS receiver, the GPS receiver  230  separates a 1 pulse-per-second (“1 PPS”) timing signal (“GPS timing signal”) from the GPS signal and forwards it to the APE System Timing Generator. In addition to other functions, a system timing generator  260  is responsible for synchronizing the operation of the APE  110  to other APEs  110  and CPEs  120  in the TDD system ( FIG. 1 , Item  100 ). 
   The present invention utilizes the stable and accurate timing signal of the GPS, which is accepted to be accurate to within 50 nanoseconds of Universal Time Coordinated (UTC). The 1 PPS GPS timing signal is used to synchronize low-cost reference clocks on the APEs  110  and in CPEs  120 . Synchronizing state machines provide adjustments in the System Timing signals generated by timing generators, and to the Master Clock Reference based upon the phase difference between a hub symbol clock and the GPS timing signal. The reference oscillators used need not be voltage-controlled. GPS receivers are known to be stable in approximately 450 seconds after power-up. This is in stark contrast to the 12 to 24 hours needed by VCOs used in prior art TDD synchronization methods. 
     FIG. 3  gives greater detail of system timing generators ( 260 ) constructed in accordance with the present invention. As was previously mentioned, synchronization (or “alignment”) of the APEs  110  is carried out in the system timing generator in the preferred embodiment of the present invention, although it will be appreciated by those skilled in the art, that it is possible to implement the synchronization functions of the present invention elsewhere, given the description in this Letters Patent. 
   While the system timing generator  260  in  FIG. 3  belongs to a master APE, system timing generators in slave APEs are similarly constructed in the preferred embodiment. A symbol clock signal output via line  344  from a timing generator  340  is divided by a divider  330  to approximate 1 hertz pulses. The output of the divider  330  is presented to a first input of an error detector  320 , while a second input  310  of the error detector  320  receives the aforementioned GPS timing signal (1 pulse per second, or 1 hertz). The error detector  320  determines whether there is a phase difference between the GPS timing signal and the divided version of the System Timing (SBT) signal generated by the system burst timer  340 . The phase error, vel non, between the output of the divider  330  and the GPS timing signal causes a synchronization state machine  370  to either output an “add n time units” signal when the SBT signal is too fast, a “subtract n time units” signal when the SBT signal is too slow, or no signal when there is no appreciable phase error, and the SBT signal and the GPS timing signal are synchronized within a predefined tolerance. The time units added or subtracted can be chips, symbols, or any multiple or fraction thereof, but must be synchronous with the chip timing. 
   The output (“synchronization information”) of the synchronization state machine  370  is fed to the inputs of a dead time counter  350  in the timing generator, responsible for adjusting both the system timing (SBT) signal via output  396  and the symbol clock signal. The system timing signal (SBT) synchronizes the operation of components in the particular APE  110 . The synchronization information is also stored in a synchronization register  380  and a CPE control register  390 . The synchronization information includes both add/subtract n time unit signals, as appropriate, and a timing marker indicating when the timing is to be changed. 
   The timing information from the synchronization register  380  is output (via output  382 ) to the slave APEs and to the APE receivers. The APE receivers (not shown) have similar timing generator with a dead time counter, and makes the indicated timing change as required. The synchronization state machine in the slave APEs receive the synchronization information from the synchronization register in the master APE to adjust their System Timing signals to the master. 
   The synchronization of the CPEs with the APEs in the present-inventive TDD system is carried out by each CPE&#39;s modem. As an example, the CPE modem  410  (which is subsumed by a CPE  120 ) shown in  FIG. 4 , periodically receives APE synchronization information from its associated APE. The synchronization information, which is first stored in a CPE control register  420 , is in the form of an “add n” or “subtract n” time units, along with the aforementioned time marker. To insure the integrity of the system, the synchronization information is repeated for several bursts. The synchronization information is then stored in a synchronization register  430 . Meanwhile, a confidence counter  450  serves as an error detector to examine the synchronization information bursts, and to detect whether the synchronization information contains transmission errors. 
   If the confidence counter  450  does not detect transmission errors above a set threshold, it enables a synchronization state machine  440  to output either an “add n” time units, a “subtract n” time units, or no change at all in response to the synchronization information. A timing generator  460 , responsible for outputting a System Timing (SBT) signal to the rest of the CPE via output line  490  uses a reference oscillator  480  to derive its output. The timing generator  460  contains a dead time generator  470  which is used to either speed up, slow down, or maintain the System Timing signal (SBT), as was previously described with respect to the APEs. 
   The Timing Generator  460  adjusts as is needed, the System Timing (SBT) in the following manner. The Dead Time Counter is instructed by the Synchronization state machine  440  to add n time units when the APE local oscillator is running faster than the GPS timing signal, and subtract n time units when the APE local oscillator is running slower than the GPS timing signal. 
   Thus has been disclosed, a novel method and system for synchronizing Access Points and CPEs in a time division duplex system without expensive voltage controlled oscillators in the Access Points. 
   Variations and modifications of the present invention are possible, given the above description. However, all variations and modifications which are obvious to those skilled in the art to which the present invention pertains are considered to be within the scope of the protection granted by this Letters Patent.