Abstract:
An integrated circuit device generates a reference voltage (V ref ) at a load node (B) to which internal load circuitry (not shown) is connected. An amplifier ( 22 ) has an output (A) whose impedance has an effective inductive component (L amp ) in a desired range of operating frequencies of the load circuitry. A first resistance element (R 1 ) is connected between the amplifier output and the load node for supplying the reference voltage to that node. An external capacitor (C ext ) is connected to a connection terminal (C) of the device. A second resistance element (R 2 ) is connected between the load node and the connection terminal. The resistances of the resistance elements and the capacitance of the external capacitor are chosen so as to reduce an impedance variation with frequency of the load node over the desired range of operating frequencies of the load circuitry that would otherwise result from the effective inductive component. An internal capacitor (C int ) is preferably connected to the amplifier output to compensate for an inductance (L pin ) associated with the connection terminal.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to reference voltage generating circuitry, and more particularly to reference voltage generating circuitry in an integrated circuit device. 
     2. Description of the Related Art 
     In conventional reference voltage generating circuitry, a basic regulated voltage is derived from an unregulated supply, and this basic regulated voltage is then buffered to produce at an output of the circuitry a reference voltage having a desired current driving capability. The basic regulated voltage may be derived, for example, by a reverse-biased Zener diode, or a bandgap reference circuit, and the buffering may be provided by an operational amplifier. 
     An output impedance of such circuitry typically appears to be inductive, as the gain of the output buffering stage generally falls off with increasing frequency. As shown in FIG. 1 of the accompanying drawings, the output impedance can be modelled to a reasonable approximation as a fixed inductor. In practice, the actual inductance will not be fixed, but may vary in dependence upon such factors as output current (since the transconductance of an operational amplifier changes with current) and temperature. 
     Because of the essentially inductive output impedance, the output impedance Z O , as seen by load circuitry connected to the output, increases linearly with a frequency ω of operation of the load circuitry. This does not pose any problems in the case when the generated reference voltage is fed into “static” load circuitry, i.e. load circuitry that has no varying signals, or has signals varying only in a low frequency range where the inductor has very low impedance. 
     In practice, however, the load circuitry to which the reference voltage generating circuitry is connected may include elements which switch at high frequencies. For example, FIG. 2 of the accompanying drawings shows an example in which reference voltage generating circuitry  1 , with an inductive output impedance Z O , is connected to load circuitry  10  which incorporates switching elements  12 , such as transistors. The load circuitry in this example also includes a constant current sink element  14 . A constant current I is sunk by the current sink element  14 . The effect of the element  14  is to make less significant the changes in the total current drawn by the load circuitry. In this example, the switching elements  12  may be switching currents at a high frequency, for example up to 100 MHz in some applications. This inevitably produces small high-frequency spikes or glitches in the total current drawn from the reference voltage circuitry. At high frequencies the output impedance Z O , which is essentially inductive, will be high. Accordingly, any high-frequency variation in current will cause an undesirable corresponding variation in the reference voltage which is delivered from the voltage reference generating circuitry (at node A in FIG.  2 ). 
     In practice, it is desirable that the output impedance of the reference voltage generating circuitry is stable beyond the actual clock frequency applied to the switching elements themselves, as the fast switching times of the switching elements will cause higher-frequency transients to be generated. 
     In precision applications, for example in high-speed digital-to-analog converters (DACs) or analog-to-digital converters (ADCs) which are clocked at rates of around 100 MHz or more, the variation in reference voltage caused by high-frequency variation in the load circuitry is highly significant. 
     Accordingly, it is desirable to provide reference voltage generating circuitry capable of generating a reference voltage which is less susceptible to the effects of such high-frequency load variation. 
     SUMMARY OF THE INVENTION 
     According to a first aspect of the present invention there is provided an integrated circuit device comprising: a load node at which a reference voltage is generated when the device is in use; load circuitry connected to said load node for receiving therefrom said reference voltage; a reference voltage amplifier having an output whose impedance has an effective inductive component in a desired range of operating frequencies of said load circuitry; a first resistance element, having a preselected resistance, connected between said output and said load node for supplying said reference voltage to that node; a connection terminal to which external capacitance having a preselected capacitance is connected when the device is in use; a second resistance element, having a preselected resistance, connected between said load node and said connection terminal; thereby to reduce an impedance variation with frequency of the load node over said desired range of operating frequencies of the load circuitry. 
     According to a second aspect of the present invention there is provided an integrated circuit device comprising: a plurality of load nodes at which a reference voltage is generated when the device is in use, each said load node having load circuitry connected thereto for receiving said reference voltage therefrom; a reference voltage amplifier having an output whose impedance has an effective inductive component in a desired range of operating frequencies of said load circuitry; and a connection terminal to which external capacitance having a preselected capacitance is connected when the device is in use; said device further comprising, for each said load node: a first resistance element, having a preselected resistance, connected between said output and said load node concerned for supplying said reference voltage to that node; and a second resistance element, having a preselected resistance, connected between said load node concerned and said connection terminal; thereby to reduce an impedance variation with frequency of said plurality of load nodes over said desired range of operating frequencies of the load circuitry. 
     According to a third aspect of the present invention there is provided an integrated circuit device comprising: a first load node at which a first reference voltage is generated when the device is in use; a second load node at which a second reference voltage is generated when the device is in use; load circuitry connected between said first and second load nodes for receiving therefrom said first and second reference voltages; respective first and second reference voltage amplifiers, each having an output whose impedance has an effective inductive component in a desired range of operating frequencies of said load circuitry; respective first and second connection terminals to which external capacitance having a preselected capacitance is connected when the device is in use; a first resistance element connected between said output of the first reference voltage amplifier and said first load node for supplying said first reference voltage to that node; a second resistance element connected between said first load node and said first connection terminal; a third resistance element connected between said output of said second reference voltage amplifier and said second load node for supplying said second reference voltage to that node; and a fourth resistance element connected between the second load node and said second connection terminal; each of said first to fourth resistance elements having a preselected resistance; thereby to reduce an impedance variation with frequency of the load node over said desired range of operating frequencies of the load circuitry. 
     According to a fourth aspect of the present invention there is provided an integrated circuit device comprising: a plurality of pairs of load nodes, each pair being made up of a first load node at which a first reference voltage is generated when the device is in use and a second load node at which a second reference voltage is generated when the device is in use, each pair of said plurality having load circuitry connected between said first and second load nodes of that pair for receiving therefrom said first and second reference voltages; respective first and second reference voltage amplifiers, each having an output whose impedance has an effective inductive component in a desired range of operating frequencies of said load circuitry; and respective first and second connection terminals to which external capacitance having a preselected capacitance is connected when the device is in use; said device further comprising, for each said pair of load nodes: a first resistance element connected between said output of the first reference voltage amplifier and said first load node of the pair concerned for supplying said first reference voltage to that node; a second resistance element connected between said first load node of the pair concerned and said first connection terminal; a third resistance element connected between said output of said second reference voltage amplifier and said second load node of the pair concerned for supplying said second reference voltage to that node; and a fourth resistance element connected between the second load node of the pair concerned and said second connection terminal; each of said first to fourth resistance elements having a preselected resistance; thereby to reduce an impedance variation with frequency of the load node over said desired range of operating frequencies of the load circuitry. 
     With an integrated circuit device embodying any one of the above-mentioned first to fourth aspects of the present invention, said preselected resistance of each said resistance element is preferably such that a resonator circuit associated with said output of the or each said amplifier is overdamped, said resonator circuit being formed by said effective inductive component of the output impedance of the amplifier concerned and by the resistance elements connected between that output and the connection terminal associated with that output and by said external capacitance connected to that connection terminal. A quality factor of said resonator circuit is preferably in the range from 0.3 to 0.7. 
     An integrated circuit device embodying any one of the above-mentioned first to fourth aspects of the present invention preferably further comprises internal capacitance connected for compensating for an inductance associated with said connection terminal. Said internal capacitance is preferably connected directly to said output(s) of the reference voltage amplifier(s). Said internal capacitance is preferably connected to the or each said load node via a further resistance element having a resistance of the same order as the resistance of each of said first and second resistance elements. 
     With an integrated circuit device embodying any one of the above-mentioned first to fourth aspects of the present invention, the impedance of the or each said load node is preferably less than 20 ohms throughout said range of operating frequencies. Said range of operating frequencies is preferably from DC to a frequency higher than 100 MHz. At least one of said resistance elements is preferably provided by a metal tracking portion within the device. 
     According to a fifth aspect of the present invention there is provided circuitry comprising an integrated circuit device of any one of the above-described first to fourth aspects of the present invention, and further comprising one or more capacitors connected externally of the device to the or each said connection terminal thereof to serve as said external capacitance. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a circuit model of previously-considered reference voltage generating circuitry; 
     FIG. 2 shows an example in which the FIG. 1 reference voltage generating circuitry is connected to load circuitry; 
     FIG. 3A shows a first embodiment of reference voltage generating circuitry according to the present invention; 
     FIG. 3B shows a graph for illustrating impedance variation of components of the FIG. 3A circuitry; 
     FIG. 4A shows an enhanced circuit model of reference voltage generating circuitry embodying the present invention; 
     FIG. 4B shows a graph for illustrating impedance variation of components of the FIG. 4A model; 
     FIG. 5A shows a second embodiment of reference voltage generating circuitry according to the present invention; 
     FIG. 5B shows a graph for illustrating impedance variation of components of the FIG. 5A circuitry; 
     FIG. 6 shows the variation with frequency of an output impedance of reference voltage generating circuitry embodying the present invention for various capacitance values of an internal capacitor included in the circuitry; 
     FIG. 7 shows a third embodiment of reference voltage generating circuitry according to the present invention; 
     FIG. 8 shows a modification applicable to the second embodiment of FIG. 5A; 
     FIG. 9 shows a fourth embodiment of reference voltage generating circuitry according to the present invention; and 
     FIG. 10 shows a circuit model of parts of the FIG. 9 circuitry. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 3A shows reference voltage generating circuitry  20  embodying the present invention. The circuitry  20  is divided into two parts as shown by the dotted line in FIG.  3 A. The parts to the left of the dotted line are included in an integrated circuit (IC) which, in general, will also contain further circuitry. For example, the IC may be an ADC IC. The parts to the right of the dotted line are external of the IC (offchip). 
     As mentioned above, an output impedance of an amplifier in an output stage  22  (buffering stage) of the reference voltage generating circuitry is modelled by a fixed inductance L amp . In the FIG. 3A circuitry, a first resistor R 1  is connected in series between a node A at the output of the output stage  22  and a node B (load node) at which the reference voltage V ref  is output from the circuitry. A second resistor R 2  is connected in series between the node B and a node C which is a connection pin of the IC. An external capacitor C ext  is connected in series between the node C and a reference line GND. 
     The reference voltage V ref  is fed to load circuitry (not shown) inside the IC which is connected to the node B. 
     The magnitude Z of the impedance which is seen by the load circuitry connected to node B in FIG. 3 can be shown to be given by:        Z   =       {         [           R   1            R   2          (       R   1     +     R   2       )         +       ω   2          L   2          R   2       +       R   1         ω   2          C   2                 (       R   1     +     R   2       )     2     +       (       ω                 L     -     1     ω                 C         )     2         ]     2     +       [         ω                 L                   R   2   2       -       R   1   2       ω                 C       -       L   C          (       ω                 L     -     1     ω                 C         )               (       R   1     +     R   2       )     2     +       (       ω                 L     -     1     ω                 C         )     2         ]     2       }       1   2                              
     FIG. 3B shows schematically to a logarithmic scale the variation with frequency ω of the magnitude |Z C | of the impedance Z C  of the capacitor C ext  and the magnitude |Z L | of the impedance Z L  of the inductance L amp . As |Z C | falls with increasing frequency and |Z L | rises with increasing frequency, at some frequency ω x  the magnitudes of the two impedances cross over so that both have an impedance of Z X . 
     It can be shown that, in the circuitry of FIG. 3A, by setting R 1 =R 2 =R and further setting R to be equal to the cross-over impedance Z x  of L and C, the magnitude of the impedance Z seen at node B of FIG. 3A reduces to:        Z   =       L   C                              
     With the configuration shown in FIG. 3A, therefore, the node B appears to the load circuitry to have a constant impedance which is purely resistive and is independent of frequency ω. In practice, of course, the output impedance of the amplifier in the reference voltage generating circuitry will not be precisely modelled by a fixed inductance L amp  and there will be departures from ideal behaviour in other respects too, so the node-B impedance will not be completely resistive and independent of frequency. 
     The resistors R 1  and R 2  effectively act as damping resistors in an LC resonator circuit made up of those resistors and the inductance L amp  and the capacitor C ext . The above-described constant impedance situation occurs when the values of R 1  and R 2  are set to give critical damping for the LC resonator circuit. In practice it is not usually possible reliably to design the circuitry to be critically damped, for example due to component tolerances and non-ideal behaviour of the operational amplifier. It is therefore preferable to set the values of R 1  and R 2  to give slight over-damping (e.g. a nominal quality factor Q in the range from 0.3 to 0.7), so that, allowing for component tolerances and other factors, under-damping does not occur. 
     Based on simulations and/or actual measurements, in one embodiment of the invention L amp  is approximately 1 μH. The capacitor C ext  can be set to any arbitrary value, although it is preferably within the range from 10 nF to 1 μF. If C ext  is below 10 nF the output impedance Z will be too large, and if C is greater than 1 μF the capacitor will be too bulky and expensive. In one embodiment, a capacitor C of 0.1 μF is used. In this case the cross-over impedance, and therefore the value of the resistance R, is 3.16Ω. To design for slight over-damping, a resistance value R of, for example, 3.5Ω can be used. 
     In the FIG. 3A circuitry to obtain a desirably low output impedance Z (e.g. a few ohms), the capacitor needs to be quite large, and so is placed offchip. Because the capacitor is offchip there may be a potentially-significant stray inductance L pin  associated with the connection via the connection pin of the IC to the external capacitor. This connection inductance L pin  can be included in an enhanced circuit model of the circuitry  20 , as shown in FIG.  4 A. The connection inductance L pin  also includes any inductance associated with the external capacitor C ext  itself, as well as with external wiring such as printed-circuit-board tracks connecting the capacitor to the IC connection pin. 
     The variation with frequency of the magnitude of the impedance of each of the components in FIG. 4A is shown schematically in FIG.  4 B. The inclusion of the connection inductance has the effect of increasing the overall output impedance of the reference voltage generating circuitry at high frequencies, e.g. frequencies higher than 10 MHz. The connection inductance L pin  for example, in the region of 5 nH. 
     In a second embodiment of the present invention, shown in FIG. 5A, the effect of increasing impedance at high frequencies caused by the connection inductance is compensated for by adding an internal (on-chip) capacitor C int  at the output of the amplifier. The variation with frequency of the magnitude of the impedance of each of the components of FIG. 5A is shown schematically in FIG.  5 B. The value of the on-chip capacitor C int  should preferably be chosen so that it has an impedance equal to the constant resistance at the frequency at which the impedance of the connection inductance L pin  crosses the constant resistance line R. Using the same component values as described above (with L amp =1 μH, C ext =0.1 μF, R=3.16Ω and L pin =5 nH) it can be shown that the on-chip capacitor C int  should have a value of 0.5 nF. With these component values, the impedance seen at node B in the FIG. 5A circuitry is a constant 3.16Ω across all frequencies. 
     For circuits where a constant impedance at high frequencies is not required, the on-chip capacitor C int  can be omitted. 
     FIG. 6 shows the variation of the output impedance, as measured at node B in the FIG. 5A circuitry, with frequency for several different values of on-chip capacitance C int . In this example it can be seen that the above-mentioned value of 0.5 nF gives the most constant output impedance among the values tested. It can be also seen that other values from 200 pF to 1 nF or more give useful results in terms of providing a relatively constant output impedance at frequencies higher than 10 MHz. 
     Incidentally, the respective resistive components of the amplifier output impedance, the connection impedance (L pin  etc.) and the internal-capacitor impedance and the external-capacitor impedance are typically very small. For example, usually these resistive components may be of the order of 0.1Ω. For this reason the resistive components have been ignored in the above-mentioned embodiments. 
     If any of these resistive components is not negligible for some reason, then the or each significant resistive component should be taken into account when setting the resistance values of the “additional” resistors R 1  and R 2 . In particular, the sum of the additional resistance R 1  and any significant resistive components of the amplifier output impedance and of the internal-capacitor impedance should then be set equal to the sum of the additional resistance R 2  and any significant resistive components of the connection impedance and external-capacitor impedance. 
     The above-described embodiments of the present invention have employed the reference voltage generating circuitry in a “single-ended” configuration. The present invention is also applicable to a differential or “bridged” configuration, such as in the third embodiment shown in FIG.  7 . 
     In the FIG. 7 embodiment, reference voltage generating circuitry 50 in an IC includes two operational amplifiers  22   1  and  22   2  in place of the single operational amplifier  22  in the single-ended configuration. Each amplifier  22  receives at its input a reference potential V HI  or V LO  and buffers the reference potential at its output (nodes A 1  and A 2 ). As for the single-ended embodiments, an output impedance of each of the amplifiers  22  may be adequately modelled by a fixed inductance L amp . 
     In the FIG. 7 circuitry, load circuitry  10 , to which a reference voltage V ref  (=V HI −V LO ) generated by the circuitry  50  is to be applied, is connected between nodes B 1  and B 2  (load nodes). The node B 1  is connected to the node A 1  by a resistor R 1 . Similarly, the node B 2  is connected to the node A 2  by a resistor R 3 . 
     The IC device including the circuitry  50  also has respective first and second connection pins (nodes C 1  and C 2 ) associated respectively with the nodes B 1  and B 2 . The node C 1  associated with the node B 1  is connected to the node B 1  via a resistor R 2 . Similarly, the node C 2  associated with the node B 2  is connected to the node B 2  via a resistor R 4 . Each of the connection pins has associated with it a connection-pin inductance L pin , as described previously. 
     In the FIG. 7 circuitry, each of the resistors R 1  to R 4  should have the same resistance value R as each of the resistors R 1  and R 2  in the single-ended embodiments described above. 
     It would be possible in the FIG. 7 circuitry to connect a separate external capacitor to each of the connection pins (nodes C 1  and C 2 ), each external capacitor serving to compensate for an output inductance L amp  of its associated one of the amplifier element  51 . In this case, each external capacitor would be connected between the connection pin and ground, and would have its capacitance value selected in the same way as in the single-ended embodiments described above. 
     However, it will be appreciated that, because the two external capacitors would effectively be connected in series (via ground) between the two connection pins (nodes C 1  and C 2 ), those two external capacitors can be replaced by a single external capacitor C ext  as shown in FIG.  7 . This reduces cost, and also makes the arrangements for the external capacitor more compact and simple on a circuit board on which the IC is mounted. Furthermore, the single external capacitor C ext  used in the bridged configuration of FIG. 7 can provide as low an output impedance as the single-ended embodiments with only half the capacitance value of the external capacitor used in the single-ended embodiments (assuming that the inductance L amp  of each of the amplifiers  51  in the FIG. 7 circuitry is the same as the output inductance of the amplifier  22  used in the single-ended embodiments). This leads to further cost reductions and space savings. 
     Similarly, in the FIG. 7 circuitry a single internal capacitor C int  is connected directly between the amplifier output nodes A 1  and A 2  to compensate for the connection inductances associated with the connection pins (nodes C 1  and C 2 ) and with the external capacitor(s). Again, two separate internal capacitors could be used for this purpose, each being connected between one of the amplifier output nodes A 1  and A 2  and ground, but the same effect can be achieved using a single internal capacitor C int  having half the capacitance value of the internal capacitor used in the single-ended embodiments described above. This again can lead to a more compact arrangement within the IC itself. 
     Incidentally, in the FIG. 7 circuitry it is also possible to employ both a “bridging” external capacitor connected between the two connection pins (nodes C 1  and C 2 ) and two further external capacitors, each connected between one of the connection pins and ground. In this, any suitable combination of capacitance values giving each connection pin an effective associated capacitance equal to the capacitance employed in the single-ended embodiments can be used. For example, all three external capacitors could have a capacitance of one quarter the capacitance employed in the single-ended embodiments. 
     In the second embodiment (FIG.  5 A), the internal capacitor C int  used to compensate for the connection inductance L pin  was connected between the node A and ground. However, as shown in FIG. 8, it is also possible to achieve the same effect by connecting the internal capacitor C int  between ground and the node B (load node), although in this case a further resistor having the same resistance value R as the other resistors in the circuitry is connected in series with the internal capacitor C int . It is also possible to apply the same modification to the bridged configuration shown in FIG.  7 . In this case, instead of connecting the internal capacitance C int  between the nodes A 1  and A 2 , the internal capacitor C int  is connected between the nodes B 1  and B 2 , with a series resistor having a resistance of  2 R in series with it. 
     FIG. 9 shows a fourth embodiment of the present invention in which reference voltage generating circuitry  70  embodying the present invention is also applied in a bridged configuration. In this embodiment, instead of a single set of load circuitry, four sets of load circuitry  10   1  to  10   4  are provided within the same IC device. For example, each set of load circuitry  10   1  to  10   4  may comprise an analog-to-digital converter (ADC). 
     In the FIG. 9 circuitry, different reference potentials V HI  and V LO  are applied respectively to the input of a pair of amplifiers  22   1  and  22   2 , and the resulting buffered potentials are output by the amplifiers  22  at nodes A 1  and A 2  respectively. Each amplifier output node A 1  or A 2  is connected via a resistor network RN 1  or RN 2  made up of eight individual resistors to an associated connection pin of the IC (node C 1  or C 2 ). Each of the eight resistors in the resistor network has a resistance value of  4 R, where R is the resistance value of each of the resistors R 1  and R 2  in the single-ended embodiments described above. 
     Each resistor network RN 1  or RN 2  has four parallel branches, each branch having two of the individual  4 R resistors connected in series. The nodes B 1  to B 8  are the common nodes at which the two resistors in each branch are connected together. Each set of load circuitry  10   1  to  10   4  is connected between one of the common nodes B 1 , B 3 , B 5  and B 7  of the first resistor network RN 1  and a corresponding one of the common nodes B 2 , B 4 , B 6  and B 8  of the second resistor network RN 2 . Also connected across each set of load circuitry  10   1  to  10   4  is a decoupling capacitor C d1  to C d4 . 
     It can be seen that, as the four branches of each resistor network RN 1 /RN 2  are connected in parallel with one another between the node A 1 /A 2  and the node C 1 /C 2 , a combined resistance of the eight resistors in the network is  2 R, as in the previous embodiments. 
     In this embodiment, each connection pin (node C 1  or C 2 ) has its own external capacitor C ext1  or C ext2  connected between the pin and ground. Each external capacitor C ext1  and C ext2  serves, as described previously, to compensate for an effective inductive component of the output impedance of an associated one of the amplifiers  22 , and the capacitance value is selected as described previously in relation to the single-ended embodiments. Alternatively, in place of the two external capacitors C ext1  and C ext2 , a single external capacitor having half the value of each of the external capacitors C ext1  and C ext2  may be used, as in the FIG. 7 embodiment. 
     In use of the circuitry  70 , each set of load circuitry  10   1  to  10   4  receives the same reference voltage V ref  determined by the difference between the reference potentials V HI  and V LO  applied to the two amplifiers  22 . An impedance of the circuitry  70 , as seen by each set of load circuitry  10   1  to  10   4 , is substantially constant over a wide range of frequencies, as in the previous embodiments. 
     Because each set of load circuitry  10   1  to  10   4  has its own associated branch within each of the resistor networks RN 1  and RN 2  the amount of coupling between the different sets of load circuitry is reduced substantially as compared to a situation in which all of the sets were supplied from the same pair of nodes (e.g. the nodes B 1  and B 2  in FIG.  7 ). 
     FIG. 10 shows an equivalent circuit of the first set of load circuitry  10   1  in the FIG. 9 circuitry. When, for example, R is approximately 3Ω (as in the single-ended embodiments described above),  4 R is approximately 12Ω. If the load circuitry  10   1  is clocked at a rate of, for example, 100 MHz, a suitable value for the decoupling capacitor C d1  is of the order of 80 pF, giving an effective RC time constant τ for the decoupling arrangement of approximately 1 ns. In this way, the different sets of load circuitry can be decoupled from one another highly effectively. 
     The FIG. 9 embodiment can also be adapted for use in a single-ended configuration in which, for example, the different sets of load circuitry each receive the same reference voltage that is referenced to ground. In this case, the second resistor network RN 2  is not required, but the first resistor network RN 1  is retained to supply the reference voltage “separately” to each set of load circuitry. 
     In the above-described FIG. 9 embodiment, each resistor in each resistor network RN 1 /RN 2  had a resistance value of  4 R, in order that the combined resistance of the eight resistors in each network was  2 R. It will be appreciated that it is not necessary that the value of each resistor in one branch of a resistor network is the same as that of each resistor in another branch of that resistor network, simply that the combined resistance of the resistor network is  2 R. For instance, if a first set of the load circuitry  10  draws a larger current than a second set of load circuitry  10 , then the resistance value chosen for the branch associated with the first set of load circuitry  10  may be set lower than the resistance value chosen for the branch associated with the second set of load circuitry  10 , whilst keeping the combined resistance of the resistor network as  2 R. If, for example, binary-weighted current is drawn from adjacent loads  10 , then binary-weighted branch resistance values may be used, in inverse proportion to the current loading on that branch. Such binary-weighted values would be (15/8)R, (15/4)R, (15/2)R and 15R. 
     Since it can be difficult to fabricate resistors which have a small resistance value reliably (for example using polysilicon), resistors for use in embodiments of the present invention may be formed from internal metal tracking. For example, resistor R 1  in FIG. 5A may be formed from metal tracking leading from the output of amplifier  22  (node A) to node B. Such metal tracking typically has a resistance of 0.1 Ω/square. If a resistance of 2Ω is required then 20 squares are needed, and if the physical distance between nodes A and B in FIG. 5A is 500 μm, then the width of the tracking should be 25 μm. 
     It will be appreciated that, although in the embodiments described above, the amplifiers have simply buffered the reference potentials applied to them, an amplifier which produces an output voltage of a different level from the input voltage it receives could also be used. For example, the or each amplifier could perform a voltage doubling function or other level adjustment function. 
     It will also be appreciated that embodiments of the present invention are applicable in any situation in which it is desired to generate, in an integrated circuit, a reference voltage for use by circuitry within integrated circuit. The load circuitry to which the reference voltage is applied need not be analog-to-digital conversion circuitry or digital-to-analog conversion circuitry, as described previously, but can be any suitable kind of circuitry. 
     Similarly, it is not necessary for the reference voltage generated by the reference voltage generating circuitry embodying the present invention to be completely constant over time. For example, it would be possible to apply the invention in applications in which it is necessary for the reference voltage to change slowly over time.