Abstract:
A redistribution film for IC package is disclosed, which comprises a top redistribution layer configured on top of a bottom redistribution layer. The top redistribution layer is fabricated following PCB design rule, and the bottom redistribution layer is fabricated following IC design rule. Further, the interface between the top redistribution layer and the bottom redistribution layer is optionally made roughed to increase bonding forces therebetween.

Description:
[0001]    This application is a continuation of U.S. application Ser. No. 14/542,191 filed Nov. 14, 2014 the disclosure of which is incorporated by reference herein in its entirety. 
     
    
     BACKGROUND 
       [0002]    Technical Field 
         [0003]    The present invention relates to a redistribution film for IC package, especially relates to a film composed of double redistribution layers where a top redistribution layer is made and configured on top of a bottom redistribution layer. The top redistribution layer is fabricated following PCB design rule and the bottom redistribution layer is fabricated following IC design rule. 
         [0004]    Description of Related Art 
         [0005]      FIG. 1A  shows a prior art substrate for IC package. 
         [0006]      FIG. 1A  shows a prior art substrate for IC package disclosed in US2014/0102777A1 which has an embedded silicon interposer  20 . The silicon interposer  20  has four lateral sides  206 . A molding compound  22  wraps the silicon interposer  20  around the four lateral sides  206 . A plurality of via metal  200  is made through the silicon interposer  20 . An insulation liner  201  is made between the through via  200  and the silicon interposer  20  for an electrical insulation there-between. A top redistribution layer  21  is made on top of the silicon interposer  20  with a plurality of metal pad  210  exposed on top. The plurality of metal pad  210  on top is provided for accommodating an IC chip (not shown) to mount. A circuit built-up layer  25  is made on bottom of the silicon interposer  20  with a plurality of metal pad  220  configured on bottom. A plurality of solder ball  24  is configured and each solder ball  24  is configured on bottom of a corresponding bottom metal pad  220 . 
         [0007]      FIG. 1B  shows a reversed view of  FIG. 1A .  FIG. 1B  is made to present the prior art of  FIG. 1A  in a position similar to a package substrate of the present invention to facilitate a comparison there between.  FIG. 1B  shows an up-down view of  FIG. 1A . The top solder ball  24  is configured for mounting the package substrate onto a mother board (not shown). The bottom metal pad  210  is configured for a chip or chips to mount. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]      FIGS. 1A ˜ 1 B show a prior art substrate for IC package. 
           [0009]      FIGS. 2A ˜ 2 I show a fabricating process for a first embodiment according to the present invention. 
           [0010]      FIGS. 3A ˜ 3 I show a fabricating process for a second embodiment according to the present invention. 
           [0011]      FIGS. 4A ˜ 4 N show a fabricating process for a third embodiment according to the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0012]      FIGS. 2A ˜ 2 I show a fabricating process for a first embodiment according to the present invention. 
         [0013]      FIG. 2A  shows: preparing a temporary carrier; applying a release layer  31  on top of the temporary carrier; and applying a seed layer  32  on top of the release layer  31 . 
         [0014]      FIG. 2B  shows: applying a patterned photoresist PR on top of the seed layer  32 . 
         [0015]      FIG. 2C  shows: forming a patterned bottom metal pad  341 . 
         [0016]      FIG. 2D  shows: stripping the photoresist  33 ; and leaving a plurality of bottom metal pad  341 . 
         [0017]      FIG. 2E  shows: forming a bottom redistribution layer RDL 1 , at least one redistribution circuit  342  is included in the RDL 1 , the redistribution circuit  342  is made using the bottom metal pad  341  as a start point according to IC design rule or equivalent; forming a plurality of first top metal pad  343  on top of the bottom redistribution layer RDL 1 . A plurality of dielectric layer  351 ,  352  is intervened among the circuit  341 ,  342 ,  343  according to conventional IC fabricating processes. The circuit  341 ,  342 ,  343  are collectively called redistribution circuit. 
         [0018]      FIG. 2F  shows: forming a top redistribution layer RDL 2  according to conventional PCB fabricating processes or equivalent on top of the bottom redistribution layer RDL 1 ; forming a plurality of second top metal pad  443  on top of the top redistribution layer RDL 2 ; at least one redistribution circuit  442  is included and is made using the first top metal pad  343  as a start point. The redistribution  442  is electrically coupled to the second top metal pad  443 . The circuit  443 ,  442  are collectively called redistribution circuit. Dielectric layers  451 ,  452 ,  453  are intervened among the redistribution circuit  443 ,  442 . The dielectric material for PCB fabricating process can be one of polyimide (PI), prepreg (PP) or benzocyclobutene (BCB). 
         [0019]      FIG. 2G  shows: planting a plurality of solder ball  38 , each is planted on top of a corresponding second top metal pad  443 . 
         [0020]      FIG. 2H  shows: removing the temporary carrier; and removing the seed layer  32  from bottom of the bottom redistribution layer RDL 1 ; and mounting at least a chip  391  on bottom of the bottom metal pad  341 . Underfill  392  is configured in a space between the chip  391  and the metal pad  341 . 
         [0021]      FIG. 2I  shows: a single unit IC package singulated from the product of  FIG. 2H . 
         [0022]      FIG. 3A ˜ 3 I fabricating process for a second embodiment according to the present invention. 
         [0023]      FIGS. 3A ˜ 3 D are the same as  FIGS. 2A ˜ 2 D, for simplification, the description to  FIGS. 3A ˜ 3 D is omitted. 
         [0024]      FIG. 3E  shows: a plurality of recess  382  is made on top of a top dielectric layer of the bottom redistribution layer RDL 1 . The recess  382  is made to enhance the roughness of the top surface of the bottom redistribution layer RDL 1 . The increased roughness enhances bonding force to a layer formed on top of the bottom redistribution layer RDL 1  in a later fabricating process. 
         [0025]      FIGS. 3F ˜ 3 I are similar to  FIGS. 2F ˜ 2 I, we describe again as follows: 
         [0026]      FIG. 3F  shows: forming a top redistribution layer RDL 2  according to conventional PCB fabricating processes or equivalent on top of the bottom redistribution layer RDL 1 ; forming a plurality of second top metal pad  443  on top of the top redistribution layer RDL 2 ; at least one redistribution circuit  442  is included and is made using the first top metal pad  343  as a start point. The redistribution  442  is electrically coupled to the second top metal pad  443 . The circuit  443 ,  442  are collectively called redistribution circuit. Dielectric layers  451 ,  452 ,  453  are intervened among the redistribution circuit  443 ,  442 . The dielectric material for PCB fabricating process can be one of polyimide (PI), prepreg (PP) or benzocyclobutene (BCB). 
         [0027]      FIG. 3G  shows: planting a plurality of solder ball  38 , each is planted on top of a corresponding second top metal pad  443 . 
         [0028]      FIG. 3H  shows: removing the temporary carrier; and removing the seed layer  32  from bottom of the bottom redistribution layer RDL 1 ; and mounting at least a chip  391  on bottom of the bottom metal pad  341 . Underfill  392  is configured in a space between the chip  391  and the metal pad  341 . 
         [0029]      FIG. 3I  shows: a single unit IC package singulated from the product of  FIG. 3H . 
         [0030]      FIG. 3I  is a single unit of IC package with a roughed interface between top redistribution layer RDL 2  and bottom redistribution layer RDL 1 . The roughness is caused by the plurality of recess  382 . 
         [0031]      FIG. 4A ˜ 4 M fabricating process for a third embodiment according to the present invention. 
         [0032]      FIGS. 4A ˜ 4 E are the same as  FIGS. 2A ˜ 2 E, for simplification, the description to  FIGS. 4A ˜ 4 E is omitted. 
         [0033]      FIG. 4F ˜ 4 J shows: a plurality of recess  382  is made on a top dielectric layer of the bottom redistribution layer RDL 1 . The plurality of recess  382  is made to enhance the roughness of the top surface of the bottom redistribution layer RDL 1 . The increased roughness enhances bonding force to a layer formed on top of the bottom redistribution layer RDL 1  in a later fabricating process. 
         [0034]      FIG. 4F  shows: applying a first patterned photoresist PR 1  on top of the bottom redistribution layer RDL 1  and exposing partial top surface of the bottom redistribution layer RDL 1 . 
         [0035]      FIG. 4G  shows: applying a seed layer  42  on top of the first photoresist PR 1  and on the exposed top surface of the bottom redistribution layer RDL 1 . 
         [0036]      FIG. 4H  shows: applying a second patterned photoresist PR 2  on top of the seed layer  42 ; forming a plurality of trench  45  to expose the seed layer  42  on a bottom of each corresponding trench  45 . 
         [0037]      FIG. 4I  shows: forming a metal bump  46  in each corresponding trench  45  using the seed layer  42  as a start point. 
         [0038]      FIG. 4J  shows: stripping the second photoresist PR 2 ; stripping the seed layer  42 ; stripping the first photoresist PR 1 ; and leaving a plurality of metal bump  46  on top of a top dielectric layer of the bottom redistribution layer RDL 1 . 
         [0039]      FIGS. 4K ˜ 4 N are the same as  FIGS. 2F ˜ 2 I, we describe again as follows: 
         [0040]      FIG. 4K  shows: forming a top redistribution layer RDL 2  according to conventional PCB fabricating processes or equivalent on top of the bottom redistribution layer RDL 1 ; forming a plurality of second top metal pad  443  on top of the top redistribution layer RDL 2 ; at least one redistribution circuit  442  is included and is made using the first top metal pad  343  as a start point. The redistribution  442  is electrically coupled to the second top metal pad  443 . The circuit  443 ,  442  are collectively called redistribution circuit. Dielectric layers  451 ,  452 ,  453  are intervened among the redistribution circuit  443 ,  442 . The dielectric material for PCB fabricating process can be one of polyimide (PI), prepreg (PP) or benzocyclobutene (BCB). 
         [0041]      FIG. 4L  shows: planting a plurality of solder ball  38 , each is planted on top of a corresponding second top metal pad  443 . 
         [0042]      FIG. 4M  shows: removing the temporary carrier; and removing the seed layer  32  from bottom of the bottom redistribution layer RDL 1 ; and mounting at least a chip  391  on bottom of the bottom metal pad  341 . Underfill  392  is configured in a space between the chip  391  and the metal pad  341 . 
         [0043]      FIG. 4N  shows: a single unit IC package singulated from the product of  FIG. 4M . 
         [0044]      FIG. 4N  is a single unit of IC package with a roughed interface between top redistribution layer RDL 2  and bottom redistribution layer RDL 1 . The roughness is caused by the plurality of metal bump  46 . 
         [0045]    While several embodiments have been described by way of example, it will be apparent to those skilled in the art that various modifications may be configured without departs from the spirit of the present invention. Such modifications are all within the scope of the present invention, as defined by the appended claims.