Abstract:
In a logic circuit which is logically divided into partial circuits each consisting of a logic block, data holding stages on the input and output sides therof, and a scan circuit segment associated with them, diagnostic data for a logic circuit section is obtained using the scan circuit segments in the respective partial circuits and wherein, only the scan circuit segments in the respective partial circuits are actuated to set values in the output side data holding stages and to read out the contents thereof as diagnostic test data for a scan circuit section.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to the testing of logic circuits and, more particularly, to a method for testing a logic circuit which has a built-in scan circuit for a diagnosis. 
     A logic circuit of a scale larger than a certain degree is constructed of a plurality of logic blocks (each block including a plurality of combinational logic circuit stages) which are interconnected through data holding stages (such as flip-flops or latches). The logic circuit of a specified type which is formed as an LSI or which is mounted on a printed circuit board is ordinarily provided with a scan circuit which directly controls the respective data holding stages in order to set diagnostic input data and to read out diagnostic output data, and the logic block and the scan circuit are activated during exclusive time periods with respect to each other, in other words, so that while one is operating, the other is kept in an non-operating state, by a signal which is applied to a scan enable edge pin. 
     According to a prior-art method for diagnosing or testing the logic circuit of the above type, as described in Japanese Patent Application Laid-open No. 60-102021, the entire circuit is logically divided into partial circuits each consisting of one of the logic blocks, an input side data holding stage and an output side data holding stage thereof, and a scan circuit segment associated with them. Subsequently, in each of the partial circuits, the scan circuit segment is actuated to set diagnostic input data in the input side data holding stage, and then the operation of the scan circuit segment is inhibited while the logic block is actuated. Thereafter the output of the logic block set in the output side data holding stage is read out as diagnostic data. Although this method is intended to obtain the diagnostic data for the logic circuit section composed of the logic blocks and the data holding stages, it cannot produce diagnostic data for the scan circuit section (including the various edge pins connected to the scan circuit). Therefore, if the scan circuit section is faulty, a correct diagnosis cannot be drawn from the diagnostic data obtained in the foregoing way. Accordingly, satisfactory diagnostic data cannot be produced without the diagnostic data for the scan circuit section also. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a method of collecting overall diagnostic data which includes diagnostic data for the scan circuit section also when testing a logic circuit which has a built-in diagnostic scan circuit. 
     According to the present invention, in a testing method for gathering diagnostic data for a logic circuit comprising partial circuits each consisting of a logic block, an input side and an output side data holding stages thereof, and a scan circuit segment associated with them for gathering the diagnostic data, there is also included, in addition to the steps of diagnosing the logic circuit section as in the prior art, the step of gathering diagnostic data for the scan circuit section by actuating only the scan circuit segments in the respective partial circuits so as to set data in and read out the data from the data holding stages. 
     Since the logic blocks do not operate during the operation of the scan circuit segments, the diagnostic data for the scan circuit section can be produced by this additional step. Since the scan circuit section accounts for 20 to 30% of the whole logic circuit, enhancement in the percentage of fault detection equal, at least, to that extent can be expected. 
     The aforementioned and other objects, features and advantages of the present invention will become apparent from the following description. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram schematically showing the whole logic circuit which is to be tested according to the present invention; 
     FIG. 2 is a block diagram schematically showing a partial circuit which is formed for testing a logic circuit section according to the prior art; 
     FIG. 3 is a block diagram schematically showing a partial circuit which is formed for testing a logic circuit section according to the present invention; and 
     FIG. 4 is a flow chart showing a diagnosing process in an embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1 conceptually shows an example of a logic circuit which is to be tested according to the present invention. A rectangle 1 denotes the whole logic circuit which is formed as an LSI or which is mounted on a printed circuit board. This logic circuit is logically divided into a plurality of partial circuits 2 (only one of which is shown in the figure) for the diagnostic purpose. Each partial circuit 2 consists of a logic block 3 made up of combinational logic circuits, an input side flip-flop stage (referred to as &#34;input FF stage&#34; hereinafter) 4, an output side flip-flop stage (referred to as &#34;output FF stage&#34; hereinafter) 5, and a scan circuit segment 6 associated with them. When a scan enable edge pin 7 is at a value &#34;0&#34;, the scan circuit segment 6 is in the non-operating state thereof and the logic block 3 is in the operating state thereof, whereas when the scan enable edge pin 7 is at a value &#34;1&#34;, the scan circuit segment 6 is in the operating state and the logic block 3 is in the non-operating state. During the normal mode of operation, the value &#34;0&#34; is applied to the scan enable edge pin 7, whereby the scan circuit segment 6 is inhibited from operating, and the logic block 3 subjects the content of the input FF stage 4 to a logical operation and sets the result of the operation in the output FF stage 5. 
     FIG. 2 shows the partial circuit 2 which is formed for the testing of the logic cirucit section according to the aforementioned prior-art method. The input FF stage 4 is used as an input terminal point (an input value setting point), while the output FF stage 5 is used as an output terminal point (an output value observing point). First, the value &#34;1&#34; is applied to the scan enable edge pin 7 to actuate the scan circuit segment 6, whereby predetermined diagnostic input data is set, or scanned-in, in the input FF stage 4. Subsequently, the value &#34;0&#34; is applied to the scan enable edge pin 7, thereby inhibiting the operation of the scan circuit segment 6 and actuating the logic block 3. The logic block 3 sets the result of a logical operation based on the content of in input FF stage 4, in the output FF stage 5. The content of the output FF stage 5 is extracted, or scanned-out, as diagnostic data by again applying the value &#34;1&#34; to the scan enable edge pin 7 to operate the scan circuit segment 6. If the scan circuit segment 6 continues to operate during the operation of the logic block 3, the content of the input FF stage 4 might change as a result of a charge on the input terminal point by the scan circuit segment. In such a case, the testing operation may be based on data different from the designated diagnostic input data that may result in an improper diagnostic data read-out. In order to avoid this difficulty, the operation of the logic block 3 and that of the scan circuit segment 6 are activated during exclusive time periods with respect to each other. However, the faults (especially &#34;stuck-at-0&#34; and &#34;stuck-at1&#34; ) of the scan circuit segment 6 itself cannot be detected from the diagnostic data thus obtained as the result of the operation of the logic block 3. 
     FIG. 3 shows the partial circuit 2&#39; which is formed for diagnosis of the scan circuit section according to the present invention. The value &#34;1&#34; is applied to the scan enable edge pin 7 to bring the scan circuit segment 6 into the operating state and the logic block 3 into the non-operating state. The input FF stage 4 is treated as a group of indeterminate value (hazard) inserting elements e.g. flip-flops. Accordingly, even when the scan circuit segment 6 is actuated, any specified value is not set in the input FF stage 4. This disposal for the input FF stage 4 precludes the input FF stage from being adversely affected by the scan circuit element diagnostic data and resulting in the reduction in the quantity of diagnostic input data. The scan circuit segment 6 scans diagnostic input data into the output FF stage 5 and scans the content out of the same, thereby producing diagnostic data. This diagnostic data is useful particularly for the detection of the stuck faults of the scan circuit section. 
     FIG. 4 is a flow chart showing an example of a diagnosing process according to the present invention. Steps 10 and 11 correspond to the diagnosis of the logic circuit section based on the prior-art method. At the step 10, a single partial circuit 2 as shown in FIG. 2 is formed. At the step 11, diagnostic data for the logic block 3 and the input and output FF stages 4, 5 in this partial circuit is produced. These steps are repeated for the successive partial circuits, whereby diagnostic data for the whole logic circuit section in the circuit 1 to be tested are collected. 
     Subsequently, the diagnosis of the scan circuit section forming the characterizing feature of the present invention is made. At a step 12, a single partial circuit 2&#39; as shown in FIG. 3 is formed. At a step 13, diagnostic data for the scan circuit segment 6 in this partial circuit is produced as described before. These steps are repeated for the successive partial circuits, whereby diagnostic data for the whole scan circuit section are collected. In this way, complete diagnostic data for the whole circuit 1 (both the logic circuit section and the scan circuit section) to be tested are obtained. 
     Either the collection of the diagnostic data for the entire logic circuit section or that of the diagnostic data for the entire scan circuit section may well be performed first, or one may well be directly followed by the other for each of the partial circuits.