Abstract:
A method of reducing stress in a cascode common-source amplifier including a first transistor and a second transistor connected in a cascode arrangement. The method includes providing an input voltage and a bias voltage to the first transistor and the second transistor, respectively, connected in the cascode arrangement, generating, based on the input voltage and the bias voltage, an output current, and equalizing stress associated with operation of each of the first transistor and the second transistor. Equalizing the stress includes, in response to the input voltage decreasing by an amount sufficient to cause the first transistor and the second transistor to turn off, equalizing respective voltage drops across the first transistor and the second transistor.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present disclosure is a continuation of U.S. patent application Ser. No. 13/656,181 (now U.S. Pat. No. 8,742,853), filed on Oct. 19, 2012, which claims the benefit of U.S. Provisional Application No. 61/551,322, filed on Oct. 25, 2011. The disclosure of the above application is incorporated herein by reference in its entirety. 
    
    
     FIELD 
     The present disclosure relates to amplifiers, and more particularly to cascode common-source amplifiers. 
     BACKGROUND 
     The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure. 
     Maximum power deliverable by a cascode common-source (CS) amplifier is limited by the maximum stress that the device can tolerate. One stress parameter relates to a drain-source voltage V DS  across a transistor. Referring now to  FIG. 1 , a cascode CS amplifier may be used to increase the maximum power deliverable in a single stage. The cascode CS amplifier includes a transistor N 1  and a transistor N 2 . A control terminal of the transistor N 2  may be connected to a bias signal V b . A first terminal of the transistor N 1  is connected to a second terminal of the transistor N 2 . A second terminal of the transistor N 1  is connected to a reference potential such as ground. A control terminal of the transistor N 1  receives an input voltage V in  and an output current I out  is generated. 
     The cascode CS amplifier transforms an input voltage into an output current. The voltage at the output of the cascode CS amplifier depends on a load. When the input swings low, the output will swing high due to the inverting nature of the cascode CS amplifier. In this state, the transistors N 1  and N 2  will turn off. In order for the transistor N 2  to turn off, the source voltage only needs to rise to the level of V G2 −V TH2 , where V G2  is a gate bias voltage of the transistor N 2  and V TH2  is the threshold voltage of the transistor N 2 . 
     For example, if a drain voltage V D  of the transistor N 2  has a quiescent value of 3.6 V, the quiescent drain voltage V D  of the transistor N 1  is 1.8 V, and the quiescent gate voltage V G  of the transistor N 1  is 0.6 V, then the quiescent gate voltage V G  of the transistor N 2  should be approximately 2.4 V. If the threshold voltage V TH  is 0.4 V, then the maximum voltage that the drain voltage V D  of the transistor N 1  can swing to is approximately 2.4−0.4=2.0 V. If the output voltage of the cascode CS amplifier swings to 7.2 V (which may occur in an inductively loaded cascode CS amplifier), then the drain-source voltage V DS  across the transistor N 1  will reach a maximum of 2.0 V, while the drain-source voltage V DS  of the transistor N 2  will reach a maximum of 5.2 V. This large voltage across the transistor N 2  can cause long term stress, and limit the useful lifetime of the device. 
     SUMMARY 
     An amplifier system comprises a cascode common-source (CS) amplifier including a plurality of transistors connected in a common-source configuration. A stress reducing circuit is connected to at least one of the plurality of transistors to equalize a voltage drop across the plurality of transistors. 
     In other features, the cascode CS amplifier includes a first transistor including a control terminal, a first terminal and a second terminal. A second transistor includes a control terminal, a first terminal and a second terminal, wherein the first terminal of the second transistor is connected to the second terminal of the first transistor. 
     In other features, the stress reducing circuit includes a first transistor including a control terminal, a first terminal and a second terminal. The second terminal of the first transistor is connected to a first terminal of a first one of the plurality of transistors. A capacitance has a first terminal connected to the control terminal of the first transistor and a second terminal connected to a control terminal of a second one of the plurality of transistors. 
     In other features, the stress reducing circuit includes a first transistor including a control terminal, a first terminal and a second terminal. The first terminal of the first transistor is connected to a first terminal of a first one of the plurality of transistors. A capacitance has a first terminal connected to the control terminal of a third transistor and a second terminal connected to a control terminal of a second one of the plurality of transistors. 
     In other features, the cascode CS amplifier includes N first transistors, each including a control terminal, a first terminal and a second terminal, wherein N is an integer greater than two. The stress reducing circuit includes N−1 second transistors each including a control terminal, a first terminal and a second terminal. The second terminals of the N−1 second transistors are connected to the second terminals of N−1 of the N first transistors, respectively. N−1 capacitances each have first terminals connected to the control terminals of the N−1 second transistors, respectively, and second terminals connected to the control terminal of one of the N first transistors. 
     Further areas of applicability of the present disclosure will become apparent from the detailed description, the claims and the drawings. The detailed description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the disclosure. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       The present disclosure will become more fully understood from the detailed description and the accompanying drawings, wherein: 
         FIG. 1  is a schematic diagram of a cascode common-source (CS) amplifier according to the prior art; 
         FIG. 2  is a functional block diagram of an example of an amplifier system including a stress reducing circuit according to the present disclosure; 
         FIG. 3  is a schematic diagram of another example of an amplifier system including a stress reducing circuit according to the present disclosure; 
         FIG. 4  is a graph illustrating examples of V D , V S  and V DS  as a function of time for the amplifier system according to the prior art; 
         FIG. 5  is a graph illustrating examples of V D , V S  and V DS  as a function of time for the amplifier system including the stress reducing circuit according to the present disclosure; 
         FIG. 6  is a functional block diagram of an example of a power amplifier system according to the present disclosure; 
         FIG. 7  is a more detailed functional block diagram and schematic of an example of a power amplifier including the amplifier system with the stress reducing circuit according to the present disclosure; 
         FIG. 8  is a schematic diagram of another example of an amplifier system including a stress reducing circuit according to the present disclosure; 
         FIG. 9  is a schematic diagram of an example of a differential amplifier system with stress reducing circuits according to the present disclosure; 
         FIG. 10  is a schematic diagram of another example of an amplifier system with additional stages according to the present disclosure; and 
         FIG. 11  is a schematic diagram of another example of a differential amplifier system with another stress reducing circuit according to the present disclosure. 
     
    
    
     DESCRIPTION 
     According to the present disclosure, an amplifier system includes a cascode CS amplifier and a stress reducing circuit. The stress reducing circuit helps to equalize stress on transistors in the cascode CS amplifier. In one approach, the stress reducing circuit is connected to a gate of a first or input transistor and between the transistors of the cascode CS amplifier. In another approach, the stress reducing circuit is connected to a gate of one of the transistors. 
     Referring now to  FIG. 2 , an example of an amplifier system  50  according to the present disclosure is shown to include a cascode CS amplifier  56  and a stress reducing circuit  58 . The stress reducing circuit  58  works with the cascode CS amplifier  56  and helps to equalize stress on transistors in the cascode CS amplifier  56 . In other words, the stress reducing circuit  58  attempts to equalize a voltage drop across the two or more transistors of the cascode CS amplifier  56 . An optional output circuit  60  communicates with an output of the cascode CS amplifier  56 . A load  64  is connected to an output of the cascode CS amplifier  56  or the optional output circuit  60 . 
     Referring now to  FIG. 3 , an example of an amplifier system  100  according to the present disclosure is shown. The amplifier system  100  includes a cascode CS amplifier  56  including a transistor N 1  and a transistor N 2 . A control terminal of the transistor N 2  may be connected to a reference potential. A first terminal of the transistor N 1  is connected to a second terminal of the transistor N 2 . The transistors N 1  and N 2  may be NMOS transistors. A second terminal of the transistor N 1  is connected to a reference potential such as ground. 
     The amplifier system  100  further includes the stress reducing circuit  58 , which includes a transistor P 1  having a first terminal connected to a reference potential and a second terminal connected between the first terminal of N 1  and the second terminal of N 2 . The transistor P 1  may be a PMOS transistor. The stress reducing circuit  56  further includes a capacitor C 1  that is connected between a control terminal of the transistor P 1  and a control terminal of the transistor N 1 . A control terminal of the transistor N 1  receives an input voltage V in  and an output current I out  is generated. 
     Transistors in the amplifier system  100  have reduced stress, which improves the useful life of the device. When the input swings low and the transistors N 1  and N 2  turn off, the impedance at the drain of the transistor N 1  becomes large. According to the present disclosure, the transistor P 1  may be used to pull the drain voltage up to the supply voltage of the transistor P 1 . In some examples, the transistor P 1  may be smaller than transistor N 1 . 
     In order to ensure that the transistor P 1  does not affect the quiescent operating point between the transistor N 1  and the transistor N 2 , the transistor P 1  can be biased so that a conduction angle thereof is less than 180 degrees. In this way, the transistor P 1  only turns on when the signal swings are large, and specifically, when the transistor N 1  and the transistor N 2  are both off. 
     Following the previous example, when the input voltage swings low, the transistors N 1  and N 2  will turn off. The drain voltage V D  of the transistor N 2  may then swing as high as 7.2 V. At the same time, the transistor P 1  will turn on, and if a supply voltage of the transistor P 1  is 3.6 V, then the drain voltage V D  of the transistor N 1  will swing to 3.6 V. Therefore, the maximum drain-source voltage across the transistors N 1 , N 2 , and P 1  will all be 3.6 V. The even distribution of voltage across the devices will ensure minimum stress to the devices. 
     Referring now to  FIGS. 4-5 , the drain voltage V D , the source voltage V S  and the drain-source voltage V DS  are shown as a function of time. In  FIG. 4 , example waveforms for the source and drain of N 2  in the cascode CS amplifier of  FIG. 1 . In  FIG. 5 , example waveforms for the source and drain of the transistor N 2  in the cascode CS amplifier  100  according to the present disclosure. 
     For example only, the cascode CS amplifier may be designed to work at 900 MHz. For example only, the peak voltage across the transistor N 2  is 3.6 V, while the peak voltage across the transistor N 1  is 3.8 V. In the classical design, the peak voltage across the transistor N 2  is 4.4 V. The transistor P 1  was sized to ⅙th the size of the transistor N 1 . 
     The cascode CS amplifier according to the present disclosure is more effective at lower frequencies as the transistor P 1  charges the capacitance of the transistor N 1  and N 2 . The transistor P 1  will introduce some additional capacitance to the input, although it will be small if the device is not sized too large. 
     Referring now to  FIGS. 6-7 , an example of a power amplifier system  200  according to the present disclosure is shown. In  FIG. 6 , a driver  202  receives an input signal. The driver  202  drives a power amplifier  204 , which generates an output signal. In  FIG. 7 , the driver  202  includes a transistor N 3  having a control terminal that receives an input signal. A first terminal of the transistor N 3  is connected to an inductor I 1 . Another terminal of the inductor I 1  is connected to a first voltage source V s1 . For example only, the first voltage source V s1  may operate at 1.8V. 
     A capacitor C 2  is connected between the inductor I 1  and the power amplifier  204 , which includes the cascode CS amplifier  56  and the stress reducing circuit  58 . More particularly, the capacitor C 2  is connected to the control terminal of the transistor N 1 . A first terminal of the transistor P 1  is connected to a second voltage source V 52 . A first bias voltage V b1  is connected to the control terminal of the transistor N 1 . A second bias voltage V b2  is connected to a control terminal of the transistor P 1 . A third bias voltage V b3  is connected to a control terminal of the transistor N 2 . A primary side of a transformer T is connected to the first terminal of the transistor N 2  and to a third voltage source V s3 . For example only, the third voltage source V s3  may operate at 3.6V. A secondary side of the transformer T provides the output signal. 
     For example only, the input signal may be a 1 mW signal at 900 MHz and the output signal may be a 1 W signal at 900 MHz. The input signal may be a sinusoidal signal having 0.3V amplitude and the output signal may be a sinusoidal signal having a 10V amplitude based on a 50 ohm termination. 
     A matching network is used at the output of the driver  202  in order to optimize the load impedance seen by the input transistor. Likewise the transformer T is used at the output of the power amplifier  204  in order to optimize the load impedance. To optimize the efficiency of the power amplifier stage, the voltage swing at the input of the transformer T may be nearly two times rail-to-rail (for example, 7.2 V). The present disclosure prevents unwanted stress to the transistors in the cascode CS amplifier under large signal conditions. 
     Referring now to  FIG. 8 , another example of an amplifier system  300  according to the present disclosure is shown. The amplifier system  300  includes a cascode CS amplifier  56 ′ and a stress reducing circuit  58 ′. The cascode CS amplifier  56 ′ includes transistors P 1  and P 2 , which include PMOS transistors. The stress reducing circuit  58 ′ includes a transistor N 1  and a capacitor C 1 . The transistor N 1  includes an NMOS transistor. The capacitor C 1  is connected between a control input of the transistor N 1  and a control input of the transistor P 2 . An inductor I 1  or other load may be connected to a first terminal of the transistor P 1 . Bias voltages V b1  and V b2  may be connected to control terminals of the transistor N 1  and the transistor P 1 . An input voltage is supplied to the control terminal of the transistor P 2 . The circuit in  FIG. 8  operates in a manner that is similar to the circuit in  FIG. 3 . 
     Referring now to  FIG. 9 , an example of a differential amplifier system  400  according to the present disclosure is shown. While the differential amplifier system  400  is a differential configuration of the amplifier in  FIG. 8 , other amplifiers described herein can also be arranged in a differential configuration. Circuit  402  is the same circuit as that shown in  FIG. 8  (with subscript _A added), while circuit  404  is a mirror image of the circuit  402  (with the subscript _B added). First and second differential signal inputs are connected (at P and N) to control terminals of the transistors P 2P  and P 2N . 
     Referring now to  FIG. 10 , another example of an amplifier system  500  with additional stages according to the present disclosure is shown. The amplifier system  500  includes T transistors (such as the transistors N 1 , N 2 , . . . , and N T ) and the stress reducing circuits  56 - 1 , . . . , and  56 -T−1 can include T−1 transistors (such as transistors P 1 , . . . , and P T-1 ) and capacitors (such as C 1 , . . . , and C T-1 ), where T is an integer greater than two. 
     By connecting the stress reducing circuits described above to a node between the transistors of the cascode CS amplifier, some leakage may occur. These circuits have a fixed vias voltage V b . Another stress reducing circuit according to the present disclosure adjusts the voltage input to a gate of one of the transistors as needed to adjust distribution of voltage across the transistors to ensure minimum stress. This approach eliminates the leakage. 
     Referring now to  FIG. 11 , an example of a differential amplifier system  600  including cascode CS amplifiers  602 - 1  and  602 - 2  and stress reducing circuits  604 - 1  and  604 - 2  according to the present disclosure is shown. The cascode CS amplifiers  602 - 1  and  602 - 2  include transistors N 1A  and N 2A  and N 1B  and N 2B , respectively, which may be NMOS transistors. The stress reducing circuits  604 - 1  and  604 - 2  includes transistors N 3A  and N 3B  and capacitors C 2A  and C 2B . Transistors N 3A  and N 3B  may be NMOS transistors. A bias voltage is connected via a resistance R A1  and R A2  to control inputs of the transistors N 2A  and N 2B , respectively. Capacitors C 1A  and C 1B  are also connected to control inputs of the transistors N 2A  and N 2B , respectively. One end of resistances R B1  and R B2  may be connected to control inputs of the transistors N 3A  and N 3B , respectively. An opposite end of the resistances R B1  and R B2  may be connected to a bias voltage or a reference potential. 
     When the input voltage to the cascode CS amplifier  602 - 1  swings low, the transistors N 2A  and N 2B  will turn off. The drain voltage V D  of the transistor N 2B  may then swing as high as a load voltage. Since the control terminal of the transistor N 3A  is connected to the other input signal, the transistor N 3A  will turn on after the charging of the capacitor C 2A . When N 3A  turns on, the voltage at the gate of N 2A  increases as needed to adjust distribution of voltage across the transistors to ensure minimum stress. As can be appreciated, while NMOS transistors are shown in  FIG. 11 , PMOS transistors may be used. 
     The foregoing description is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. The broad teachings of the disclosure can be implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since other modifications will become apparent upon a study of the drawings, the specification, and the following claims. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. As used herein, the phrase at least one of A, B, and C should be construed to mean a logical (A or B or C), using a non-exclusive logical OR. It should be understood that one or more steps within a method may be executed in different order (or concurrently) without altering the principles of the present disclosure.