Abstract:
A communication system, such as an ATM network, is disclosed having a multiplexing device formed by a plurality of access terminals for users who have cells to be transmitted at a certain rate, and at least one connecting terminal. An allocation circuit determines, at a current date, the supply of a cell (called chosen cell) to the connecting terminal. The allocation circuit includes a circuit for producing a first destination identifier (VP), a theoretical date determining circuit, a tree circuit, a sub-tree circuit, a root date determining circuit, and an extracting circuit. The theoretical date determining circuit is for determining a theoretical date for the transmission of the available cells of each service circuit as a function of the rate. The tree circuit is for presenting &#34;leaves&#34; for receiving the theoretical dates for each service circuit, a root for containing dates called root dates, on the basis of which dates a date called priority date is established from the theoretical dates, and nodes connecting said leaves to said root. The sub-tree circuit is for selecting leaves from the leaves of the tree circuit in response to the first destination identifier, and for creating a partition in the first destination identifier. The root date determining circuit is for determining at least one root date in said partition. The extracting circuit is for determining the chosen cell based upon the root dates.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a communication system comprising at least a network of the ATM type, notably a network in which information cells comprising a first destination identifier which defines a set of destinations, and a second destination identifier which defines a sub-set of said set, are transmitted from one of its access points to another access point, and at least one multiplexing device comprising: 
     a plurality of access terminals for users who have cells to be transmitted at a certain rate to a certain destination defined by said destination identifiers, 
     at least one connecting terminal for at least one access point of said network, 
     a plurality of service circuits connected to the access terminals, comprising queue elements for storing each the user cells which have the same destination identifiers, and for rendering the stored cells available on cell outputs, 
     an allocation circuit for determining the supply of a cell called chosen cell selected from the available cells to said connecting terminal via an output circuit at a current date, which allocation circuit comprises: 
     a circuit for producing a first destination identifier. 
     The present invention also relates to a multiplexing device suitable for such a system. 
     2. Discussion of the Related Art 
     The ATM (Asynchronous Transfer Mode) technique permits to transmit different types of data (sound, image, files etc.) on the same carrier. These data are arranged in packets called cells of a normalized length of 53 octets. An address contained in the header and formed by two sub-fields, the VPI (Virtual Path Identifier) and the VCI (Virtual Channel Identifier) ensures the routing of the cells inside the ATM network. The payload content of the transmission frame is called the ATM path. A succession of ATM cells having the same VPI form a virtual path VP. The route followed by a succession of ATM cells for the same VPI and the same VCI forms a virtual circuit VC. 
     For accessing an ATM network, one is confronted with certain rate restraints and jitter restraints both as regards the virtual path VP and the virtual channel VC imposed for reasons of security and call charge rate. A policing system connected to the network accesses makes tests and may even suppress the cells that lead to an overhead. 
     The access point to the network is ensured by a multiplexing device which, in consequence, is to comprise means for arranging the cells in the ATM path, so that they correspond to this policing system and also produce the least possible jitter. 
     The French Patent document filed in the name of the Applicants under no. 94 07664, 22 Jun. 1994 (FR 2 721 777), describes a mechanism which is particularly suitable for regulating cells &#34;parametered&#34; with a maximum rate PCR (Peak Cell Rate) and a factor τ&lt;1 (jitter less than one period). As, on the one hand, in the document &#34;ATM User-Network Interface Specification Version 3.0&#34; by the ATM Forum, the idea of mean SCR rate (Sustainable Cell Rate) was defined in September 1993, and as, on the other hand, it becomes necessary to handle the statistical multiplexing between cell streams, the known mechanisms are thus to be modified to take account of these new requirements. 
     SUMMARY OF THE INVENTION 
     The present invention proposes a system of the type described above, which takes account of these new requirements and makes it possible to regulate the transmission of cells both at the VP level and at the VC level. Needless to observe that the invention also applies to other networks than the ATM networks. 
     Therefore, such a system is characterized in that the allocation circuit additionally comprises: 
     a theoretical date determining circuit for determining a theoretical date for the transmission of the available cells of each service circuit as a function of, more particularly, the certain rate, 
     a tree circuit presenting: 
     &#34;leaves&#34; for receiving the theoretical dates for each service circuit, 
     a root for containing dates called root dates, on the basis of which dates a date called priority date is established from the theoretical dates, 
     nodes established in layers and connecting said leaves to said root, 
     a sub-tree circuit for selecting leaves from the leaves of the tree circuit in response to the first destination identifier, and for creating a partition in the first destination identifier, 
     a root date determining circuit for determining at least one root date in said partition. 
     These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the drawings: 
     FIG. 1 shows a network to which a multiplexing device according to the invention is connected, 
     FIG. 2 shows the structure of the information cells transmitted in the network, 
     FIG. 3 shows a multiplexing device according to the invention, 
     FIG. 4 shows the structure of an allocation circuit which forms part of the device of FIG. 3, 
     FIG. 5 shows the tree-like structure managed by the tree circuit which forms part of the system according to the invention, 
     FIG. 6 shows the structure of the tree circuit, 
     FIG. 7 shows the structure of the tree circuit in more detail, 
     FIG. 8 shows a first operating mode of the tree circuit, 
     FIG. 9 shows a second operating mode of the tree circuit, 
     FIG. 10A and 10B show a third operating mode of the tree circuit, and 
     FIG. 11 shows the function relations established by the calculation circuit. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     FIG. 1 shows in a diagrammatic manner an ATM network referenced 100 in the drawing Figure. A description of this network will be found in the publication entitled &#34;ASYNCHRONOUS TRANSFER MODE&#34; by MARTIN de PRYCKER, published in the ALICE HORWOOD Series in Britain in 1991. This network is formed by various nodes 102, 103, 104, 105, 106, 107 and 108, interconnected by links 110 to 118, for connecting the nodes 102-103, 102-107, 103-105, 103-104, 104-105, 104-108, 104-106, 107-108 and 106-107, respectively. Various access points to this network are designated as 120 to 128. These access points are connected to the nodes 108, 106, 107, 102, 103 and 105 via the links 130 to 138, respectively. Various multiplexing and demultiplexing devices 160, 161 and 162 are connected to these access points. Among these devices there is to be distinguished: a multiplexing device 160 which form part of the present invention, and two demultiplexing devices 161 and 162, which perform reverse operations to those of device 160 and form part of the system according to the invention. In European Patent Specification EP 0 632 669, filed 23 Jun. 1994, a description is found of such demultiplexing devices. To be connected to the four points 120, 121, 122 and 123, the multiplexing device 160 has four connecting terminals 170, 171, 172 and 173. Thus, within the scope of that described example, the information signals can go from device 160 to the devices 162 and 161 by passing through the network 100. These transmit information signals are applied to a plurality of access terminals 180 0  to 180 4095  which the multiplexing device 160 has and can be produced, for example, on output terminals 185 1  to 185 N  of device 161 and 190 1  to 190 N , of device 162. The order of magnitude of N and N&#39; is the order of one thousand. The information signals transmitted through the network are produced in the form of cells whose shape is shown in FIG. 2. These cells are formed by 53 octets of which 5 form the header HD and the 48 remaining octets referenced PL contain the data for a service to be transmitted. In the header field, two codes VPI and VCI are distinguished which correspond to virtual path identifier and virtual circuit identifier, respectively. The path identifiers are controlled by the transmission operator and the virtual circuit identifier is controlled by the user. To each VP are assigned sub-sets of VC values: a sub-set of CBR and a sub-set of VBR, itself formed by two sub-sets, a PCR and a SCR value. A data channel can be of the CBR type (Constant Bit Rate), in which case its rate is normally regulated by the source. Thus, only the jitter is optimized, without a test of the rate and an arbitration is carried out between VC values of the CBR type of the same VP to minimize the jitter. 
     A VC can be of the VBR type (Variable Bit Rate), which is considered to have less priority than the VC of the CBR type. It is normally characterized by its &#34;mean&#34; rate SCR (Sustainable Cell Rate), and its &#34;peak&#34; rate PCR (Peak Cell Rate). The PCR is higher than the SCR and can only hold for a specified duration (cell burst). The ATM Forum cited above defines exactly the VCR type seen from the policing point of view. The ABR type (Available Bit Rate) defined by the ATM Forum can easily be adapted to the present device. A process with an EPRCA algorithm (Enhanced Proportional Rate Control Algorithm), not described here, will dynamically modify the rate parameters linked with the virtual paths or virtual circuits. 
     FIG. 3 shows a diagram of the multiplexing device 160. For simplicity of the expose, attention is only paid in this drawing Figure to the cells to be supplied to the terminal 170 from access terminals 180 0  to 180 4095 . The priority classification has already been coded in the algorithms in an indirect way via PT --  SCR and PT --  SCR of the VC descriptor described in Table 1. 
     Each of these terminals 180 0  to 180 4095  receives cells that have the same identifiers and the same traffic constraints. Index i (0≦i≦4095) determines the index of the accesses 180 0  to 180 4095 . The cells are stored in service circuits 200 0  to 200 4095 . These various elements 200 0  to 200 4095  are formed by memories of the FIFO type 201 0  to 201 4095  queue elements, respectively. These memories restore on their output the data to the order in which they have come in. A recognition code &#34;i&#34; is assigned to each of these elements 200 0  to 200 4095 . A common data line 210 connects the output of the queue elements to the terminal 170 via an output circuit 211 which is a simple circuit for adapting the signals to terminal 120. Each service circuit 200 0  to 200 4095  comprises a notification circuit 250 0  to 250 4095  respectively, for notifying the presence of a cell on its input. This circuit transmits this notification accompanied by the recognition code over a common line 260. The service circuits 200 0  to 200 4095  also comprise send authorization elements which are shown in the form of a switch 270 0  to 270 4095 , on the one hand, and a decoding element 280 0  to 280 4095  on the other. The input of this decoding element is connected to a third common line 290 which interconnects all the service circuits 200 0  to 200 4095 . 
     By processing the notifications transmitted over line 260, an allocation circuit 300 produces the recognition code on the last line 290 to authorize the service circuit indicated by this code to transmit a cell called chosen cell. This allocation circuit 300 operates in timing with a clock 302 which also supplies other signals (in a manner not shown) to the various elements of the multiplexing circuit. 
     DESCRIPTION OF THE ALLOCATION CIRCUIT (300) 
     FIG. 4 shows the structure of the allocation circuit 300. It comprises a tree circuit 400, a date counter 405 which gives the current date &#34;Dc&#34; based upon clock signals 302. It also comprises a calculation element 410 which ensures the management of the allocation circuit 300 in collaboration with a working memory 412 which notably contains information signals linked with the various VP and VCs. A second tree circuit 420 produces the VP. This circuit 420 may advantageously be of the type described in the EP Patent Specification mentioned above, or by a cyclically polled allocation table described in European Patent Specification No. 0 618 748. The VC selected by the circuit is outputted via line 290. 
     Description of the Tree Structure 
     FIG. 5 shows the tree structure which the tree circuit 400 is to produce. 
     This tree structure is of the quaternary type and is formed by six levels LV1 to LV6 comprising 1 to 1024 nodes. Each node is formed by four locations implicitly numbered from left to right &#34;00&#34;, &#34;01&#34;, &#34;10&#34; and &#34;11&#34;. Each of these locations is connected to a node of a lower level. The locations of the last level LV6 form the leaves of the tree. The level LV1 comprises a single node, called root node, referenced NR. The level LV2 comprises four nodes whose references are formed by the letter N followed by a number in a binary order, that is: N00, N01, N10 and N11; only the nodes N10 and N11 are shown in the Figure. The level LV3 comprises 16 nodes of which only the nodes referenced N1011 and N1100 are shown. For the other levels there are thus: 
     LV4 64 nodes, of which only the nodes N101111 and N110000 are shown. 
     LV5 256 nodes, of which only the nodes N10111111 and N11000000 are shown, and 
     LV6 1024 nodes, of which only the nodes N1011111111 and N1100000000 are indicated. 
     It will be evident that the numbering of each node is formed, on the one hand, by the binary part of the node of the higher level to which it is connected and, on the other hand, by the number of the location to which it is particularly allocated. 
     According to the invention, the tree is divided into sub-trees. In FIG. 5 three sub-trees relating to the same VP are shown. One of these sub-trees relates to VC PCR, another one to VC SCR and the last one to VC CBR. These various sub-branches are defined by parameters MIN and MAX. In principle, each VC CBR has an input in the sub-tree CBR of its VP, while the VC VBRs have two: one input in the sub-tree SCR and the other input in the sub-tree PCR. For obtaining optimum regulation of the rates on the VC VBR of a VP, it is necessary that the inputs of a sub-tree SCR or PCR be graded in priority levels depending on the rate of their associated VC, from the higher to the lower rate, and thus from left to right of the sub-tree. 
     FIG. 6 shows the structure of the tree circuit 400. This circuit 400 comprises a succession of processors P1 to P6, assigned each to a level LV1 to LV6, respectively. To the processor P1 is connected a memory MEM1 formed by a line containing four dates coming from the processor P2. To this processor P2 is connected a memory MEM2 formed by four lines containing each four dates coming from the processor P3 and so on and so forth up to the processor P6 to which is connected a memory MEM6 organized in 1024 lines which contain each four dates relating to four leaves, so that the various leaves numbered from 0 to 4095 can be processed. The leaves are intended to receive dates by insertion. The dates to be inserted into the leaves form part of the arguments of an &#34;Ins&#34; function. 
     In response to an information signal relating to a &#34;Rch&#34; function, the tree circuit 400 produces a result &#34;RtRch&#34; which represents, indirectly through the Table &#34;Ind&#34; 412 (FIG. 4), the number of the service circuit that is to transmit its cell. A distribution circuit 480 makes it possible to apply the information signals which have to travel in the direction of leaves-root and in the direction of root-leaves. 
     FIG. 7 shows a detailed diagram of the structure of the processors P5 and P6. Their associated memories carry references MEM5 and MEM6, respectively. 
     Leaves-Root Processing 
     This processing relates to the arguments of the &#34;Ins&#34; function, that is, in the calling order: 
     EMP: the location of the leaf likely to receive a new date. 
     Dtln: the date likely to be inserted. 
     V/F: insertion valid or false. 
     MINM and then MAXM: determine the limits of the sub-tree in which one works in the indicated direction. 
     The two least significant bits of the information signal EMP which are denoted &#34;C EMP  &#34; are applied to an input management circuit GES6 to define the location of the node of level LV6, whereas the rest of the bits denoted &#34;N EMP  &#34; are applied to the addressing input of memory MEM6 via an addressing switch SB6 to define the number of the node. As memory MEM6 is organized in lines which contain four codes each, the management circuit GES6 has for its task to put this code in the proper line location. Therefore, in a first period of time, it stores the four stored codes in the addressed line via the two-position addressing switch SB6, via another part of the code coming from the line EMP. In a second period of time, the management circuit GES6 overwrites with the code coming from the line Dtln one of the four stored dates in response to the afore-mentioned two bits. In a third period of time, all the codes stored in this management circuit are written in the memory MEM6. In a fourth period of time, these same codes are read out again from MEM6 and offered to a date determining element CP6 which determines the date code to be transmitted on a line LP6,5. 
     The date determining element CP6 increases the code that has the smallest value by taking account of MINM and MAXM in the following manner: 
     If N min  is noted to be the value of the node contained in MINM during N EMP , and C min  the value of its two bits having less significance, CP6 ignores the codes to the left of the code defined by &#34;C min  &#34; if N min  is N EMP . Similarly, if N max  is noted to be the value of the node contained in MAXM during N EMP , and C max  the value of its two bits having less significance, CP6 ignores the codes to the right of the code defined by &#34;C max  &#34; if, however, N max  =N EMP . The tests N min  =N EMP  and N max  =N EMP  are carried out by C6,1 and C6,2, respectively. A similar processing is carried out by the other processors P5 to P1. A register Dr finally contains the root date produced by P1 at the output of CP1. However, the presence of a signal V/F applied to the single management circuit GES6 will be noticed which, when the signal has the value FAUX, makes it possible to cancel the writing of a new date in the memory MEM6. Thus, when considering the last processor PE, it contains in its memory MEM1 the theoretical dates which have the values resulting from the choice of the preceding processors. This forms the leaves-root processing. 
     FIG. 5 represents the tree after an insertion with the leaves having binary notations &#34;10 11 11 11 11 01&#34; and &#34;11 00 00 00 00 01&#34;, by taking these same values for values of MINM and MAXM. It will be found that Dr contains the lowest date between MIND and MAXD. An insertion at the limits of a sub-tree forms the first partitioning step of the tree (applied here to the sub-tree CBR). 
     Root-Leaves Processing 
     This processing relates to the arguments of the function &#34;Rch&#34;, that is, in the calling order: 
     V/CD: permits to have two different criteria for selecting the circuit VC, 
     MIND and then MAXD: determine the sub-tree in which one works, 
     RT --  PRI: gives a priority for the VCs in order to avoid that it is always the same circuits that are chosen. 
     The output parameters of this function &#34;Rch&#34; are: 
     ELEM: number of the leaf and from there the virtual circuit that is chosen; this number is complete by concatenation with each change of level. 
     RSPRI: gives a change of priority for a new selection of VC. This value constitutes the argument RT --  PRI for a following search. That is to say, RSPRI crosses over at the next level to act as input RT --  PRI. 
     The root-leaves processing consists of producing, indirectly, the address that corresponds to the leaf associated to the service circuit that is authorized to transmit its cell. This code is formed by concatenation in a similar manner to the one described in the Patent Specification mentioned above, and appears on the line ELEM. This choice is also made as a function of magnitudes MAXD and MIND, which limit this choice. Furthermore, a magnitude V/CD permits to change this criterion for making this choice. Another code is also formed by concatenation, which appears on a line RSPRI. This permits to make a turning priority as this will be described in the following with respect to the present memory. 
     This turning priority processing consists first of all of changing the positions of the switching circuits SA6 and SB6. The memory MEM6 is in that case addressed by a code coming from the line ELEM, a searching element PH6 whose input is connected to the data output of the memory MEM6 via the switching circuit SA6 determines the last two bits of the final code of ELEM and RSPRI. This is effected notably by comparing codes contained in the line addressed by those produced by the dating element 405. The circuits PH j , with j=1 to 6, can be conceived as a function of the explanations that follow. 
     The circuit Phj chooses a code from those present on the output of the switching circuit SAj. For being selected, an exclusion principle analogous to the one used on insertion is applied to the codes present. 
     With respect to level j, it is required that: 
     N min ,j is the value of MIND relating to its &#34;2*(j-1)&#34; most significant bits, and 
     C min ,j is the value of MIND relating to the 2 least significant bits, 
     N max ,j is the value of MAXD relating to its &#34;2*(j-1)&#34; most significant bits, and 
     C max ,j is the value of MAXD relating to the 2 least significant bits, 
     N rt ,j is the value of RT --  PRI relating to its &#34;2*(j-1)&#34; most significant bits, and 
     C rt ,j is the value of RT --  PRI relating to the 2 least significant bits. 
     One proceeds as follows: 
     The codes to the left of the code defined by &#34;C min ,j &#34; are ignored if N nin ,j =ELEMj, 
     The codes to the right of the code defined by &#34;C max ,j &#34; are ignored if N max ,j =ELEMj. 
     Phj only takes into account only the remaining codes for that which follows. 
     If V/CD=VBR, Phj chooses the priority code in the following manner: &#34;C rt ,i &#34; turns to the right are first made with the priority codes. 
     The number of the chosen location is that which contains a date that is lower than the current date Dc and which has the most priority. The number of this location is then concatenated to ELEMj with its least significant bits and then goes to the stage j+1. If other locations contain a lower date than the current date Dc, the number of the location having the lowest priority of them is concatenated to ELEMj to form RSPRI. In the opposite case, &#34;00&#34; is concatenated to the former value of RSPRI. 
     If V/CD=CBR, Phj chooses the priority code by choosing simply the lowest date. 
     The number of its associated location is then concatenated to ELEMj with its least significant bits and then goes to stage j+1. &#34;C rt ,j &#34; and RSPRI are not evaluated. 
     The following three examples represent that which has just been described. 
     a) Determining RSPRI and ELEM for RT --  PRI=&#34;00 . . . 00&#34;. 
     Reference is made to FIG. 8 for the explanation. In this Figure, reference KO represents the value of the current date &#34;Dc&#34;, reference K1 represents the values of the locations of the root node NR. Each location is numbered from &#34;00&#34; to &#34;11&#34; in binary notation from left to right and is assigned a priority number &#34;Pty&#34; running from 3 to 0 in decimal notation from left to right. A high priority number indicates a high priority. Only the locations containing a date lower than the current date Dc are considered. As the locations of the node NR contain only dates lower than the date &#34;Dc&#34;, the date 961 having priority 3 is chosen, of which the location is numbered &#34;00&#34;: this forms the first two bits of the code ELEM. Then is chosen the lower-priority date, that is, 922, which corresponds to location &#34;01&#34; having priority 2. The first two bits of RSPRI are thus &#34;01&#34;. Then the node of the level LV2 is proceeded to. The number of the node is given by the value ELEM, thus node N00 is considered. Here it will be obvious that the date having the highest priority is not suitable, because its value 1012 is higher than the current date. If one goes back to the date 971, having priority 2, which is situated at location &#34;01&#34;, the code ELEM becomes &#34;00 01&#34;. The value of RSPRI passes &#34;00 10&#34;, because the location &#34;10&#34; corresponds to the lower priority. Then level LV3 is proceeded to, where the node N0001 defined by the code ELEM established above is considered. This node N0001 contains only one date 971 which is lower than the current date. As this date is situated at the location &#34;10&#34;, the code ELEM becomes ELEM=&#34;00 01 10&#34;. Under these circumstances &#34;00&#34; is added by concatenation to the value RSPRI already evaluated, so that RSPRI=&#34;00 10 00&#34;. 
     Then level LV4 is proceeded to where the node N000110 is considered. This node contains two dates lower than the current date. One thus chooses the date 971 which corresponds to the location &#34;01&#34; having priority 2, that is, the new value of ELEM=&#34;00011001&#34;. Subsequently, the lower priority is chosen, that is, 950, which corresponds to the location &#34;11&#34;. A new value of RSPRI is thus &#34;00011011&#34;. It should be noted that, contrary to ELEM which is extended by two bits for each stage without a modification of the previously acquired bits, the value of RSPRI is changed by concatenating the node--thus by erasing the previous value--and the location of the chosen element with second priority. One proceeds in this manner up to the level of the leaves. 
     b) Determination of RSPRI and ELEM for RT --  PRI=&#34;01101 . . . &#34;. 
     Reference is now made to FIG. 9. The same root node as in the preceding Figure is considered. This time the initial priority is modified by the first two bits of the code RT --  PRI. As these bits are &#34;01&#34;, the priority codes are shifted to the right, so that the date 922 gets the highest priority and the date 954 the next priority, so that ELEM=&#34;01&#34; and RSPRI=&#34;10&#34;. For the level LV2, the selected location is &#34;10&#34;, which corresponds to the highest priority, because the priorities have been changed by the third and fourth bits which follow, that is: &#34;10&#34;, finally there is obtained RSPRI=&#34;0111&#34; and ELEM=&#34;0110&#34;. 
     c) Determining RSPRI and ELEM for RT --  PRI=&#34;0110 . . . &#34; taking into account MIND and MAXD. 
     Reference is made to FIG. 10A. It is supposed that the first two bits having the value MIND are &#34;10&#34;, that is to say, this value points at the date 954, all the dates situated to the left of this value are invalidated as is indicated by the lines through the dates 961 and 922. The first two bits of the value MAXD are &#34;11&#34;, so that none of the date bits is invalidated by MAXD. The bits of RT --  PRI that relate to the node NR are &#34;01&#34;, so that the priority values are shifted. As the date having the highest priority 922 is crossed out, the date 954 having second priority is taken and the bits of RSPRI represent the location having the priority &#34;11&#34;. 
     Reference is made to FIG. 10B. MIND is supposed to be equal to &#34;0010 . . . &#34; and MAXD to &#34;1000 . . . &#34;, and the node N10 of LV1 is considered. Only MAXD is taken into consideration, because the value of the node &#34;10&#34; is equal to that contained in MAXD in its two most significant bits. The dates standing to the right of the arrow MAX are crossed out, that is: 971, 961 and 915. Only the date 995 remains, which results in the two bits &#34;00&#34; for ELEM. Since there is no date having a lower priority, RESPRI thus has the bits &#34;00&#34; concatenated to its previous value. 
     The circuits thus described permit to operate as a pipeline if registers referenced PA6,5, PB6,5 and PC6,5 in FIG. 7 are utilized. That is to say, while one processor manages a code, the next processor manages a preceding code. The fact that one processor is taken for each level of the tree permits to increase the rate of the notifications introduced in the tree circuit. If this rate is low, a person skilled in the art will not find any difficulty in diminishing the number of gates used by the device by assigning various stages to the same processor. One will find that the root-leaves processing will take account of an updating with a code after its leaves-root processing. 
     The dates are coded in &#34;N&#34; bits in the tree. This quantity depends on the lowest rates one wishes to process. Two additional Booleans +∞/-∞ make it possible to declare a date that can never be chosen (always higher than the current date) and a date that can always be chosen (always lower than the current date), respectively. 
     It should be observed that the device supports a date coding with 0 bits, the date permitting to be summarized to the Booleans +∞/-∞ possibly coded with 1 bit and marking the absence (+∞) or the presence (-∞) of stand-by cell(s) for a virtual circuit: the interest of the device is no longer its cell spacing function (which can be realized upstream of a device), but its capacity to select a part of the virtual circuits and choose a priority bit therefrom. 
     CALCULATION ELEMENT 410 
     FIG. 11 shows the logic structure of this element. The element is established around three drivers which drive concurrently. These processes communicate by mailbox. They interact with the Arbo function produced by tree 400 via primitives Rch and Ins, and the result RtRch which have just been described. A person of ordinary skill in the art will not find any difficulty in translating into HDL (Hardware Description Language) to &#34;compile&#34; them on silicon. 
     Among these various drivers there are distinguished: 
     PrRch: search driver. This process cooperates, on the one hand, with a describer of VP (DesVP) and indirect variables Ind --  A --  VC (link Acc --  VAR1) and, on the other hand, with the current date &#34;Dc&#34; produced by the date counter 405 and the values MINIMUM and MAXIMUM which define the sub-trees (link Acc --  VAR2). This process triggers the search Rch for the Arbo function and restores therefrom the result RtRch. This process receives search requests by a link DRch and supplies the final result by a link RRch. It also communicates by a link MJSSA with a process PrIns. 
     PrIns: insertion driver which triggers the date insertions in the Arbo tree function via the link that corresponds to the function Ins. This process communicates with a VC describer table, called DesVC, via the link Acc --  VAR3 and also via the variables MINIMUM, MAXIMUM, and Dc via the link Acc --  VAR4. It is triggered after a notification coming from the line 260 (cf. FIG. 3), which is indicated by the link Not. This process is also triggered by the process PrRch, as observed above. It is finally triggered by a process PrCoh (link DMJS). 
     PrCoh: coherence driver which updates the various dates in the tree circuit 400. Below, these various drivers will be shown in detail. 
     a) Insertion Driver 
     The insertion driver has for its function to update a describer of each VC and to update the tree by insertions. It comprises the describer table VC (DesVC) indexed by the notification number (equivalent to the number VC). 
     The form of a describer is given in the following Table I: 
     
                       TABLE I______________________________________Type.sub.-- VC        selection VBR/CBRPT.sub.-- PCR        input sub-tree PCRPT.sub.-- SCR        input sub-tree SCRPT.sub.-- CBR        input sub-tree CBRStop.sub.-- CBR        maximum permissible jitter in CBR modeStop.sub.-- date.sub.-- CBR*        maximum theoretical send date sub-tree CBRTh.sub.-- PCR*        minimum theoretical send date sub-tree PCRTh.sub.-- SCR*        minimum theoretical send date sub-tree SCRPCR.sub.-- period        Sub-tree period PCRSCR.sub.-- period        Sub-tree period SCRCell.sub.-- counter        cell counter for this VCBurst-time   maximum permissible burst time PCR______________________________________ *These variables have two markers +∞ and -∞. 
    
     The set of functions EFunc1 executed upon the arrival of a notification &#34;i&#34; (Not) is the following: 
     EFunc1 
     
         __________________________________________________________________________STARTCell.sub.-- counter  i! = Cell.sub.-- counter  i! + 1if Cell.sub.-- counter  i! = 1if Type.sub.-- VC i! = CBRthenStop.sub.-- date.sub.-- CBR i! = DC+Stop CBR i!&#34;Ins&#34; (PT.sub.-- CBR i!, Stop.sub.-- date.sub.-- CBR i!, TRUE, MINIMUM,MAXIMUM)elsecalculate and update Th.sub.-- PCR i! and Th.sub.-- SCR i! as a functionof table II&#34;Ins&#34; (PT.sub.-- PCR i!, Th.sub.-- PCR i!, TRUE, MINIMUM,MAXIMUM)&#34;Ins&#34; (PT.sub.-- SCR i!, Th.sub.-- SCR i!, TRUE, MINIMUM,MAXIMUM)endifendifEND__________________________________________________________________________ 
    
     The set of functions EFunc2 carried out upon the arrival of a request for updating coming from the search process with a VC having number `i`, transmitted by the link MJSSA, is the following: 
     EFunc2 
     
         ______________________________________STARTCell.sub.-- counter  i! = Cell.sub.-- counter  i! - 1if Cell.sub.-- counter  i! &lt; &gt; 0thenif Type.sub.-- VC i! = CBRthen   Stop.sub.-- date.sub.-- CBR i! = DC + Stop.sub.-- CBR i!   &#34;Ins&#34; (PT.sub.-- CBR i!, Stop.sub.-- date.sub.-- CBR i!, TRUE,   MINIMUM, MAXIMUM)else   calculate and update Th.sub.-- PCR i! and Th.sub.-- SCR i! as   a function of Table II.   &#34;Ins&#34; (PT.sub.-- PCR i!, Th.sub.-- PCR i!, TRUE,   MINIMUM, MAXIMUM)   &#34;Ins&#34; (PT.sub.-- SCR i!, Th.sub.-- SCR i!, TRUE,   MINIMUM, MAXIMUM)endifelseif Type.sub.-- VC i! = CBR   then     &#34;Ins&#34; (PT.sub.-- CBR i!, + ∞, TRUE,     MINIMUM, MAXIMUM)   else     &#34;Ins&#34; (PT.sub.-- PCR i!, + ∞, TRUE,     MINIMUM, MAXIMUM)     &#34;Ins&#34; (PT.sub.-- SCR i!, + ∞, TRUE,     MINIMUM, MAXIMUM)endifendifEND______________________________________ 
    
     The set of functions EFunc3 carried out upon the arrival of a request for selecting a sub-tree coming from the search process is the following: 
     EFunc3 
     
         ______________________________________START&#34;Ins&#34; (MINIMUM, xxx, FALSE, MINIMUM, MAXIMUM)&#34;Ins&#34; (MAXIMUM, xxx, FALSE, MINIMUM, MAXIMUM)END______________________________________ 
    
     The set of functions EFunc4 carried out upon the arrival of a request to update coming from the coherence process (link DMJS) is the following: 
     EFunc4 
     
         ______________________________________STARTif Type.sub.-- VC i! = CBRthen&#34;Ins&#34; (PT.sub.-- CBR i!, - ∞, TRUE, MINIMUM, MAXIMUM)else&#34;Ins&#34; (PT.sub.-- SCR i!, - ∞, TRUE, MINIMUM, MAXIMUM)&#34;Ins&#34; (PT.sub.-- PCR i!, - ∞, TRUE, MINIMUM, MAXIMUM)endifEND______________________________________ 
    
     The calculation of the new values of Th --  SCR and Th --  PCR for a given VC is shown in the following Table II 
     
                                           TABLE II__________________________________________________________________________Th.sub.-- SCR +   Th.sub.-- PCR +         Th.sub.-- SCR +SCR.sub.-- period   PCR.sub.-- period         SCR.sub.-- period                  New values of Th.sub.-- SCR&lt; Dc    &lt; Dc  &lt;Dc + Burst.sub.-- time                  and Th.sub.-- PCR__________________________________________________________________________no      no    no       Th.sub.-- SCR =                        Th.sub.-- SCR +         (PCR burst     SCR.sub.-- period         forbidden)                  Th.sub.-- PCR =                        Dc +                        SCR.sub.-- periodno      no    yes      Th.sub.-- SCR =                        Th.sub.-- SCR +         (PCR burst     SCR.sub.-- period         permitted)                  Th.sub.-- PCR =                        Th.sub.-- PCR +                        PCR.sub.-- periodno      yes   no       Th.sub.-- SCR =                        Th.sub.-- SCR +   (ruptured         (PCR burst     SCR.sub.-- period   stream)         forbidden)                  Th.sub.-- PCR =                        Dc +                        SCR.sub.-- periodno      yes   yes      Th.sub.-- SCR =                        Th.sub.-- SCR +   (ruptured         (PCR burst     SCR.sub.-- period   stream)         permitted)                  Th.sub.-- PCR =                        Dcyes     no    --       Th.sub.-- SCR =                        Dc(ruptured stream)            (impossible case)                  Th.sub.-- PCR =                        Dc                        (SCR.sub.-- period                        &gt;PCR.sub.-- period)yes     yes   --       Th.sub.-- SCR =                        Dc(ruptured stream)   (ruptured      Th.sub.-- PCR =                        Dc   stream)__________________________________________________________________________ Dc: Current date 
    
     The device receives in the search phase an argument VP which indicates in which sub-set of VC (the VCs contained in this VP) the selection of the VC has taken place. 
     Each VP possesses a describer (DesVP) with the following arguments: 
     
                       TABLE III______________________________________PTmin.sub.-- PCR      minimum pointer of the VP sub-tree PCRPTmax.sub.-- PCR      maximum pointer of the VP sub-tree PCRPTmin.sub.-- SCR      minimum pointer of the VP sub-tree SRCPTmax.sub.-- SCR      maximum pointer of the VP sub-tree SCRPTmin.sub.-- CBR      minimum pointer of the VP sub-tree CBRPTmax.sub.-- CBR      maximum pointer of the VP sub-tree CBRROT.sub.-- SCR*      turning priority index on sub-tree SCRROT.sub.-- PCR*      turning priority index on sub-tree PCROPT.sub.-- ROT.sub.-- SCR      turning priority activation/inactivation Boolean SCROPT.sub.-- ROT.sub.-- PCR      turning priority activation/inactivation Boolean______________________________________      PCR *ROT.sub.-- SCR and ROT.sub.-- PCR are initialized at 0 at the start. 
    
     An appended table Ins --  A --  VC permits to find back a VC on the basis of one of its leaf elements in the tree. 
     The set of functions EFunc5 carried out upon the arrival of a search request in a given VP (link &#34;DRch&#34;) denoted `i` is the following: 
     EFunc5 
     
         __________________________________________________________________________STARTy = -1 (impossible value)MINIMUM = PTmin.sub.-- CBR i!MAXIMUM = PTmax.sub.-- CBR i!send a request for selecting a sub-branch to the inserting processwait for its execution, that is to say, the root date is to be updated.ifRoot.sub.-- date &lt; &gt;+ ∞then&#34;Rech&#34; (CBR,MINIMUM, MAXIMUM,xxx)the search return gives `y` the number of the chosen leaf in the tree.elseMINIMUM = PTmin.sub.-- SCR i!MAXIMUM = PTmax.sub.-- SCR i!send a request to select a sub-tree to the insertion process;wait for its execution, that is, the root date is to be updated.If Root.sub.-- date (&lt; or =) Current datethen&#34;Rech (VBR, MINIMUM, MAXIMUM ROT.sub.-- SCR i!)the search return gives `y` the number of the chosen leaf in the tree.the return gives `resprio` which is the priority index found.if OPT.sub.-- ROT SCR i! = TRUEthen ROT.sub.-- SCR i! = resprioendifelseMINIMUM = PTmin.sub.-- PCR i!MAXIMUM = PTmax.sub.-- PCR i!Send a tree selection request ss to the insertion process; wait for itsexecution, that is, the root date is to be updated.if Root.sub.-- date (&lt; or =) Current datethen`Rech` (VBR, MINIMUM, MAXIMUM, ROT.sub.-- PCR i! )the search return gives `y` the number of the chosen leaf in thetree.the return gives resprio the priority index foundif OPT.sub.-- ROT.sub.-- PCR i! = TRUEthen   ROT.sub.-- SCR i! = resprioendifendifendifendifif y &lt;&gt;-1thenvc.sub.-- found = Ind.sub.-- A.sub.-- VCsend an update request with vc.sub.-- found to the insertion processvc.sub.-- found is the VC number returned by the device in &#34;RRch&#34;elseno VC is returned by the device, because no one can beselected.endifEND__________________________________________________________________________ 
    
     This process scans the various VCs and &#34;cleans&#34; the dates becoming too negative relatively to the current date. This process is slow and can take various milliseconds to scrutinize all the VCs. 
     The associated set of functions EFunc6 is the following, with N being the number of VCs tested by the device: 
     EFunc6 
     
         __________________________________________________________________________STARTfor i running from 0 to N-1repeatif Type.sub.-- VC = CBRthenif Stop.sub.-- date.sub.-- CBR i! .sub.-- Current date &lt; THRESHOLDthen   Stop.sub.-- datae.sub.-- CBR I! = -∞   request the insertion driver for an insertion with `i`endifelseCurrent date&lt; THRESHOLD or Th.sub.-- SCR i!Current date &lt; THRESHOLD   then     Th.sub.-- PCR i! = -∞     Th.sub.-- SCR i! = -∞     request the insertion driver for an     insertion with `i`   endifendifend-of-repetitionEND__________________________________________________________________________ 
    
     In a simplified version, the device can function very well without a notification with all or part of its service circuits. In the mode called &#34;autonotified&#34;, the tree is supplied a first time to &#34;trigger&#34; its service circuits without notification. The calculation element does not take into consideration the cell counter in the stand-by mode which is associated to each &#34;autonotified&#34; service circuit, so that the latter are periodically chosen in the tree, even if there are no stand-by cells. 
     Direct access to the table which contains the period of each service circuit renders the modification of the rates direct and makes the system attractive to apply the methods of flow control which necessitate a rapid rate variation without much jitter.