Abstract:
The present invention is related to a method for fabricating a semiconductor device capable of preventing a bit line pattern from being attacked during a storage node contact hole formation. The method includes the steps of: forming a bit line insulation layer on a substrate structure having a plurality of plugs; forming a group of trenches exposing a group of the plugs by etching the bit line insulation layer; burying each trench by a conductive material to form a bit line electrically connected to the exposed plug; isolating the bit line by performing a chemical mechanical polishing process until the bit line insulation layer is exposed; forming an inter-layer insulation layer on the above structure including the bit line; and etching selectively the inter-layer insulation layer and the bit line insulation layer to form storage node contact holes exposing another group of the plugs.

Description:
FIELD OF THE INVENTION 
     The present invention relates to a method for fabricating a semiconductor device; and, more particularly, to a method for forming a bit line and a storage node contact through the use of a damascene process. 
     DESCRIPTION OF RELATED ARTS 
     Hereinafter, with reference to FIGS. 1A to  1 D, there are provided descriptions on problems arose by a conventional method for forming a contact hole. 
     Referring to FIG. 1A, a first inter-layer insulation layer  13  is formed on a substrate  11  providing various elements for constructing a semiconductor device such as a word line (not shown), an impurity contact region  12  and so forth. The first inter-layer insulation layer  13  is also called as a word line insulation layer. The first inter-layer insulation layer  13  is selectively etched to form a contact hole exposing the impurity contact region  12 . 
     Next, a plurality of plugs  14  for storage node contacts or bit line contacts are formed. The plug  14  is formed in the contact hole and is contacted to the exposed impurity contact region  12 . 
     It is general to use polysilicon for the plug  14 . However, instead of the polysilicon, a multi-layered structure stacked of a tungsten layer and a barrier metal layer including Ti/TiN typically used in a diffusion barrier layer is recently used for the plug  14 . 
     After the plug  14  formation, a diffusion barrier layer  15  having the typical structure of Ti/TiN structure is formed on the plug  14  in order to prevent a source gas used in a deposition of a bit line metal layer  16  from reacting with the plug  14  and the impurity contact region  12 . Then, on an upper surface of the diffusion barrier layer  15 , the bit line metal layer  16  is formed by using such materials as polysilicon, tungsten and so forth or metal alloys such as tungsten nitride, tungsten silicide and so forth. 
     Next, a plasma enhanced chemical vapor deposition (PECVD) technique or a low pressure chemical vapor deposition (LPCVD) technique is performed to form a hard mask nitride layer  17 . Herein, the hard mask nitride layer  17  is made of nitride-based materials including silicon oxynitride or silicon nitride. 
     As shown, it is also possible to additionally form a buffer layer using undoped silicate glass (USG) in order to reduce stress generated between the bit line metal layer  16  and the hard mask nitride layer  17 . 
     Referring to FIG. 1B, the hard mask nitride layer  17 , the bit line metal layer  16  and the diffusion barrier layer  15  are selectively etched through the use of a bit line etch mask to thereby form a bit line. 
     The high level of integration in a semiconductor device makes it difficult to stably secure a pattern formation process margin and overlay accuracy. Thus, a self-align contact (SAC) process is adopted to solve the above problems because it uses pre-deposited materials instead of an additional mask during an etch process for forming various patterns such as a contact hole pattern. As a result of this approach, the SAC process is capable of reducing costs for a semiconductor device fabrication process. Among various etch methods of the SAC process, a nitride layer is typically used as an etch stop layer. 
     Therefore, during the SAC process, an insulation layer is etched under conditions that the nitride layer encompasses an upper part and lateral walls of a conductive pattern such as a gate electrode or a bit line and an oxide layer is subsequently etched in a higher rate than the nitride layer. 
     Since the SAC process is applied to a storage node contact formation process, a nitride-based etch stop layer  18  is deposited on the above entire structure including the bit line in order to prevent a bit line loss during the SAC process. FIG. 1C is a cross-sectional view showing an etch profile of the etch stop layer  18  formed along an upper part and lateral walls of the bit line. 
     With reference to FIG. 1D, a second inter-layer insulation layer  19  is formed on top of the etch stop layer  18 . The second inter-layer insulation layer is called bit line insulation layer. At this time, the bit line insulation layer  19  is commonly made of USG. 
     Next, under a target that the second inter-layer insulation layer  19  remains in a predetermined thickness on the etch stop layer  18 , a chemical mechanical polishing process (CMP) is performed to planarize the second inter-layer insulation layer  19 . After the CMP process, a photoresist pattern  20  for forming a storage node contact, and the second inter-layer insulation layer  19  and the etch stop layer  18  are sequentially etched by using the photoresist pattern  20  as an etch mask. This process is the SAC process. From this SAC process, a contact hole  21  exposing a surface of the plug  14  allocated between the bit lines is formed. As shown in FIG. 1D, the etch stop layer  18  is etched during the SAC process and remains as a spacer at lateral sides of the diffusion barrier layer  15 , the bit line metal layer  16  and the hard mask nitride layer  17 . 
     Prior to forming the contact hole  21 , an additional process for forming a contact pad is generally performed to improve an overlap margin. However, descriptions on this additional process are omitted. 
     Meanwhile, because of the high integration of the semiconductor device, such a unit element as a word line, a bit line or so forth is arrayed vertically, and a contact pad is introduced. However, a width of the bottom structure gets narrower. As a result, an aspect ratio progressively increases. For instance, in case that the aspect ratio is above about 3, a gap-fill property is diminished. Particularly, a void is generated in the course of filling-up a space between the bit lines when the second inter-layer insulation layer  19  is deposited. 
     Accordingly, during the SAC process for forming the contact hole  21 , the hard mask nitride layer  17  is attacked by this etching. This attacked portion is denoted as the reference numeral  22  in FIG.  1 D. Also, there is a problem in an insulation property between the bit line metal layer  16  and a subsequent storage node. Furthermore, an overall electrical property is deteriorated. 
     SUMMARY OF THE INVENTION 
     It is, therefore, an object of the present invention to provide a method for fabricating a semiconductor device with use of damascene process in order to prevent a conductive pattern from being attacked during a storage node contact hole formation process. 
     In accordance with an aspect of the present invention, there is provided a method for fabricating a semiconductor device, including the steps of: forming a bit line insulation layer on a substrate structure having a plurality of plugs; forming a group of trenches exposing a group of the plugs by etching the bit line insulation layer; burying each trench by a conductive material to form a bit line electrically connected to the exposed plug; isolating the bit line by performing a chemical mechanical polishing process until the bit line insulation layer is exposed; forming an inter-layer insulation layer on the above structure including the bit line; and etching selectively the inter-layer insulation layer and the bit line insulation layer to form storage node contact holes exposing another group of the plugs. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING(S) 
     The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which: 
     FIGS. 1A to  1 D are cross-sectional views showing a conventional process for forming a storage node contact hole; 
     FIGS. 2A to  2 D are cross-sectional views showing a process for forming a storage node contact hole in accordance with a first preferred embodiment of the present invention; and 
     FIGS. 3A and 3B are cross-sectional views showing a process for forming a storage node contact hole in accordance with a second preferred embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Hereinafter, an inventive method for forming a storage node contact hole will be described in detail. 
     Referring to FIG. 2A, a first inter-layer insulation layer  32  is deposited on a substrate  30  providing various elements including a word line (not shown), impurity contact regions  31  and so forth. The first inter-layer insulation layer  32  is selectively etched to form a contact hole exposing the impurity contact region  31 . 
     Next, a plurality of plugs  33  for bit line or storage node contacts are formed. At this time, each plug  33  buries the contact hole and is contacted to the exposed impurity contact region  31 . Herein, for the bit line or the storage node contacts, the plug  33  includes a typical landing plug contact (LPC) contacted to the impurity contact region  31 . 
     In addition, the plug  33  is made of, e.g., polysilicon. Recently, a multi-layer structure including a tungsten layer and a barrier metal layer such as Ti/TiN used in the typical diffusion barrier layer can be used for the plug  33  instead of the polysilicon. 
     Next, an etch stop layer  34  is deposited on the above entire structure including the plug  33 . A surface of the plug  33  for only the storage node contact is exposed among the plurality of the plugs  33 . This exposed surface of the plug  33  for the storage node contact is denoted as the reference numeral  35 . Also, the etch stop layer  34  preferably uses nitride based materials including silicon nitride or silicon oxynitride. 
     A second inter-layer insulation layer  36  is deposited on the above structure including the exposed plug  33 . Herein, the second inter-layer insulation layer  36  is called as a bit line insulation layer. After the deposition, an upper part of the second inter-layer insulation layer  36  is planarized. The second inter-layer insulation layer  36  uses high density plasma (HDP) oxide, boron phosphorus silicate glass (BPSG), phosphorus silicate glass (PSG), boron silicate glass (BSG), spin-on-dopant (SOD) or advanced planarization layer (APL). 
     Meanwhile, the deposition of the second inter-layer insulation layer  36  prior to forming a bit line prevents a generation of void. The void is generated when the second inter-layer insulation  36  is deposited after the bit line formation. 
     On top of the second inter-layer insulation layer  36 , a photoresist pattern  37  for forming trenches  38  exposing a group of the plugs  33  for bit line contacts is formed. Then, the second inter-layer insulation layer  36  and the etch stop layer  34  are selectively etched with use of the photoresist pattern  37  so that the trenches  38  exposing the group of the plugs  33  for the bit line contacts are formed. 
     Afterwards, a photoresist strip process is performed to remove the photoresist pattern  37 . In the meantime, it is possible to form an additional anti-reflection layer on between the photoresist pattern  37  and the second inter-layer insulation layer  36 . However, such an anti-reflection layer is not illustrated. 
     Referring to FIG. 2C, a diffusion barrier layer  39  is deposited along the trench  38  in such a manner to encompass lateral walls and a bottom side of the trench  38 . Preferably, the diffusion barrier layer  39  has the typical structure of Ti/TiN or Ta/TaN in order to suppress a source gas used for depositing a bit line metal layer  40  from reacting with the plug  33  and the impurity contact region  31 . 
     The bit line metal layer  40  is then formed on the diffusion barrier layer  39  by using metal such as polysilicon, tungsten and so forth or metal alloys such as tungsten nitride, tungsten silicide and so forth. 
     A plasma enhanced chemical vapor deposition (PECVD) technique or a low pressure chemical vapor deposition (LPCVD) technique is used to deposit a bit line hard mask insulation layer  41  on the bit line metal layer  40 . It is preferable to use nitride-based materials for the bit line hard mask insulation layer  41  in order to prevent the bit line metal layer  40  from being attacked during an etch process for forming a storage node contact and to obtain an etch profile by having a different etch selectivity from an oxide-based inter-layer insulation layer  36 . 
     Next, a chemical mechanical polishing (CMP) process is performed under a target of exposing the second inter-layer insulation layer  36  so to form a bit line having a damascene structure that the diffusion barrier layer  39 , the bit line metal layer  40  and the bit line hard mask insulation layer  41  are buried into the trench  38 . FIG. 2C represents a cross-sectional view of the above structure including the bit line with the damascene structure. 
     It is also possible to form additionally a buffer layer with use of undoped silicate glass (USG) in order to reduce stress possibly generated between the bit line metal layer  40  and the bit line hard mask insulation layer  41 . 
     As shown in FIG. 2D, a third inter-layer insulation layer  42  is deposited on the bit line having the damascene structure, and a planarization process is performed thereafter. The third inter-layer insulation layer  42  uses BPSG, BSG, PSG, HDP oxide or APL. 
     Another photoresist pattern  43  for forming storage node contacts is formed on the third inter-layer insulation layer  42 . Then, a self-align contact (SAC) process is performed. That is, the third inter-layer insulation layer  42  and the second inter-layer insulation layer  36  are sequentially etched by using the photoresist pattern  43  as an etch mask. From this SAC process, a storage node contact hole  44  exposing the surface of the plug  33  allocated between the bit lines is formed. 
     The above etch process is a dry-type etch process combined with a recipe for the SAC process. For this etch process, it is possible to use different types of etch gas. Such gas containing lots of carbons inducing polymers can be used as the etch gas so that the oxide-based second inter-layer insulation layer  36 , the nitride-based etch stop layer  34  and the third inter-layer insulation layer  42  have a high etch selectivity. Examples of this etch gas are C 3 F 8 , C 4 F 8 , C 5 F 8 , C 4 F 6  or C 2 F 4 . Such gas as CHF 3 , C 2 HF 5 , CH 2 F 2 , CH 3 F or H 2  can be also used as the etch gas for providing a reliable etch process by enhancing an etch process margin. Also, such inert gas as He, Ne, Ar, Kr or Xe can be also used as the etch gas for improving an etch stop function by increasing a sputtering effect and plasma stability. It is also possible to use a gas obtained by combining the aforementioned etch gases with each other. It is further possible to add C x H y F z , where x, y and z is equal to or greater than about 2, to the etch gas containing lots of carbons to secure a margin of the etch process. 
     FIGS. 3A and 3B are cross-sectional views showing a process for forming a storage node contact hole in accordance with a second preferred embodiment of the present invention. Also, the same constitution elements used in FIGS. 2A to  2 D are denoted with the same reference numerals used in the second preferred embodiments. 
     A first inter-layer insulation layer  32  is deposited on a substrate  30  providing various elements such as a word line (not shown), impurity contact regions  31  and so forth. The first inter-layer insulation layer  32  is called as a word line insulation layer. Then, a contact hole is formed by selectively etching the first inter-layer insulation layer  32 . 
     Next, a plurality of plugs  33  for storage node contacts or bit line contacts are formed. At this time, each plug  33  buries the contact hole and is contacted to the impurity contact region  31 . Herein, for the bit line or the storage node contacts, the plug  33  includes a typical landing plug contact (LPC) contacted to the impurity adhesion region  31 . Also, the plug  33  is made of polysilicon. Recently, a multi-layer structure including stacked layers of a barrier metal layer such as Ti/TiN and a tungsten layer can be also used. 
     Afterwards, an etch stop layer  34  is formed on the above structure including the plug  33 . It is preferable to use nitride-based materials such as silicon nitride or silicon oxynitride for the etch stop layer  34 . 
     Meanwhile, a partial portion of the etch stop layer  34  is etched so that a group of the plugs  33  for the storage node contact is exposed. However, explanations on the etch process for the etch stop layer  34  is omitted. 
     A second inter-layer insulation layer  36  is deposited on an entire surface of the above structure including the etch stop layer  34 , and an upper part of the second inter-layer insulation layer  36  is planarized thereafter. The second inter-layer insulation layer  36  is called as a bit line insulation layer. Additionally, the second inter-layer insulation layer uses HDP oxide, BPSG, PSG, BSG, SOD or APL. As a result, the second inter-layer insulation layer  36  deposition prior to forming a bit line can prevent a generation of void. The void is generated when the second inter-layer insulation layer  36  is deposited after the bit line formation. 
     On top of the second inter-layer insulation layer  36 , a photoresist pattern  37  for forming trenches  38  exposing a group of the plugs  33  for bit line contacts is formed. Then, the second inter-layer insulation layer  36  and the etch stop layer  34  are selectively etched with use of the photoresist pattern  37  so that the trenches  38  exposing the group of the plugs  33  for the bit line contacts are formed. 
     Afterwards, a photoresist strip process is performed to remove the photoresist pattern  37 . In the mean time, it is possible to form an additional anti-reflection layer on between the photoresist pattern  37  and the second inter-layer insulation layer  36 . However, such an anti-reflection layer is not illustrated. 
     Referring to FIG. 3B, a diffusion barrier layer  39  is deposited along the trench  38  in such a manner to encompass lateral walls and a bottom side of the trench  38 . The diffusion barrier layer  39  has the typical structure of Ti/TiN or Ta/TaN in order to suppress a source gas used for depositing a bit line metal layer  40  from reacting with the plug  33  and the impurity contact region  31 . 
     The bit line metal layer  40  is then formed on the diffusion barrier layer  39  by using metal such as polysilicon, tungsten and so forth or metal alloys such as tungsten nitride, tungsten silicide and so forth. 
     A PECVD technique or a LPCVD technique is used to deposit a bit line hard mask insulation layer  41  on the bit line metal layer  40 . It is preferable to use nitride-based materials for the bit line hard mask insulation layer  41  in order to prevent the bit line metal layer  40  from being attacked during an etch process for forming a storage node contact and to obtain an etch profile by having a different etch selectivity from an oxide-based inter-layer insulation layer  36 . 
     Next, a chemical mechanical polishing (CMP) process is performed under a target of exposing the second inter-layer insulation layer  36  so to form a bit line having a damascene structure that the diffusion barrier layer  39 , the bit line metal layer  40  and the bit line hard mask insulation layer  41  are buried into the trench  38 . FIG. 3B represents a cross-sectional view of the above structure including the bit line with the damascene structure. 
     It is also possible to form additionally a buffer layer with use of USG in order to reduce stress possibly generated between the bit line metal layer  40  and the bit line hard mask insulation layer  41 . 
     Such processes described in FIG. 2D in the above are performed. However, at this time, a portion of the etch stop layer  34  corresponding to the exposed plug  33  for the storage node contact is removed. 
     Since the bit line is formed by using the damascene process, the void is not generated at the bit line insulation layer. Therefore, it is possible to prevent the bit line from being attacked during the SAC process. Also, the bit line formation with use of the damascene process makes it possible that the bit line insulation layer is not exposed to the upper part of the bit line. Because of this non-exposure of the bit line insulation layer, the etch target is decreased during the etch process for forming the storage node contact hole. Accordingly, it is possible to improve the etch profile. Due to these effects, yields of the semiconductor device can be ultimately enhanced. 
     In addition to the storage node contact plug formation, the present invention can be applied to other semiconductor device fabrication processes for which the SAC process is employed. A process for opening an active region between gate electrodes is one example. 
     While the present invention has been described with respect to certain preferred embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims.