Abstract:
A wiring structure in a semiconductor device includes a substrate; a first conductive layer on the substrate; a second conductive layer covering a portion of the first conductive layer, wherein another portion of the first conductive layer is not covered by the second conductive layer; an insulation layer on the first and second conductive layer; a penetrating part passing through the insulation layer from the uncovered portion of the first conductive layer; and a third conductive layer on the insulation layer, the third conductive layer connecting the penetrating part.

Description:
This is a divisional of application Ser. No. 09/033,161 filed on Mar. 2, 1998, now U.S. Pat. No. 6,211,076. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a bus line wiring structure and a method of manufacturing the same that connects overlapping bus line layers with an intervening insulation layer between them, and more particularly, to a bus line wiring structure between a gate line and another line in a micro electrical device having a plurality of thin film transistors (TFTs) such as a liquid crystal display (LCD) device, a memory device, or a non-memory semiconductor device. 
     2. Discussion of the Related Art 
     In semiconductor fabrication, it is very important to maximize the number of TFTs that are integrated per unit area in a high density, micro-sized semiconductor device, such as a high resolution LCD device. In order to design a memory device having a higher capacitance or a higher resolution LCD device than an XGA (eXtended video Graphic Array) device, the number of TFTs per unit area must be increased. Thus, the bus lines connected with the TFTs are designed to be disposed in smaller spaces. Therefore, the space for connecting the gate line of the TFT and another line must be reduced. 
     The conventional method for connecting the bus lines formed in a separate layer to the wiring structure is shown in FIGS. 1 a - 2   d . Specifically, FIG. 1 a  shows a cross sectional view of the connection for bus lines formed in a separate layer according to the conventional method, FIG. 1 b  shows the plan view of the wiring structure according to the conventional method, and FIGS. 2 a - 2   d  show the steps of the conventional manufacturing process. 
     As shown in FIG. 2 a , a metal, such as aluminum or an aluminum alloy, is deposited on a substrate  11 . The metal layer is patterned to form a low resistance gate line  15   a . The surface of the low resistance gate line  15   a  is easily susceptible to hillock growth problem. The hillock growth is formed by being enlarged a grain of aluminum on the surface under high temperature during the following depositing processor such as an insulating layer depositing. The hillock of Al can be growing at 300° C. or higher. Generally, the aluminum is deposited about 200° C., so the hillock of Al can not be growing during the formation of the aluminum layer. However, the insulating layer is deposited at about 390° C. So, when the insulating layer is deposited the hillocks of Al can be growing. A metal, such as chromium or molybdenum, is deposited on the substrate  11 . The metal layer is patterned to form a gate line  15  covering the low resistance gate line  15   a . The gate line  15  prevents the hillock problem from occurring in the low resistance gate line  15   a.    
     As shown in FIG. 2 b , an insulation material such as silicon oxide or silicon nitride is deposited on the substrate having the gate line  15  to form a gate insulation layer  19 . A metal, such as chromium or a chromium alloy, is deposited on the gate insulation layer  19 . The metal layer is patterned to form a source line  35 . The source line  35  is connected with the source electrode of the switching elements, such as a TFT. 
     As shown in FIG. 2 c , an insulating material, such as a silicon nitride or a silicon oxide, is deposited on the substrate having the source line  35  to form a protection layer  39 . The gate line  15  and the source line  35  are disposed on the separated layer with the intervening gate insulation layer  19  between them. Here, the gate line  15  and the source line  35  must not be connected to each other because they are used for different objects. However, they can be connected to each other as needed during some of the processing steps to protect them from static electricity. In addition, if a repair line for source line  35  is formed in the same layer and with the same material of the gate line  15 , then the source line  35  should be connected to the repair line. 
     In order to connect the source line  35  and the gate line  15  (or the repair line in the same layer of the gate line  15 ), a gate contact hole  41  and a source contact hole  51  are formed, as shown in FIG. 2 c . That is, at least a portion of a gate line  15  is exposed by etching the protection layer  39  and the gate insulation layer  19  to form the gate contact hole  41 . Also, at least a portion of the source line  35  is exposed by etching the protection layer  39  to form the source contact hole. 
     As shown in FIG. 2 d , a conductive material, such as an indium tin oxide (ITO), is deposited on the protection layer  39 . The ITO layer is patterned to form a connecting terminal  53 . The connecting terminal  53  connects the gate line  15  and the source line  35  through the gate contact hole  41  and the source contact hole  51 . 
     In the conventional method for connecting the bus lines, the lines are connected by a third conductive material through the contact holes arrayed in horizontal. Hence, space is needed for the contact holes, thereby limiting the density of the semiconductor device. For example, in manufacturing a high density semiconductor device, all elements in the device are made smaller. Accordingly, the width of the gate line and the source line correspondingly becomes narrower. Furthermore, the number of connecting parts is increased, thereby hindering the reduction of the connection area. 
     SUMMARY OF THE INVENTION 
     Accordingly, the present invention is directed to a bus line wiring structure in a semiconductor device and method of manufacturing the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art. 
     An object of the present invention is to provide connection lines in a narrow space for the manufacturing of an electrical circuit board having multi-layered bus lines. 
     Another object of the present invention is to provide a simplified process for connecting lines formed in separate layers. 
     Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings. 
     To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the method for manufacturing a wiring structure in a semiconductor device comprises the steps of forming a first conductive layer on a substrate; forming a second conductive layer covering a portion of the first conductive layer wherein another portion of the first conductive layer is not covered by the second conductive layer; forming an insulation layer on the first and the second conductive layers; and forming a third conductive layer connecting with the portion of the first conductive layer not covered by the second conductive layer. 
     In another aspect, the method for manufacturing a wiring structure in a semiconductor device comprises the steps of forming a first line and a connecting portion at an end portion of the first line; forming a second line covering the first line wherein at least a portion of the connecting portion is not covered by the second line; forming an insulation layer on the second line and the connecting portion; forming a penetrating part by growing a hillock through the insulation layer from the connecting portion; and forming a third line connecting with the penetrating part. 
     In another aspect, the wiring structure in a semiconductor device comprises a substrate; a first conductive layer on the substrate; a second conductive layer covering a portion of the first conductive layer, wherein another portion of the first conductive layer is not covered by the second conductive layer; an insulation layer on the first and second conductive layers; a penetrating part passing through the insulation layer from the uncovered portion of the first conductive layer; and a third conductive layer on the insulation layer, the third conductive layer connecting the penetrating part. 
     In another aspect, the wiring structure in a semiconductor device comprises a substrate; a first line on the substrate; a connecting portion at the end of the first line; a second line covering the first line; an insulation layer covering the second line and the connecting portion; a penetrating part passing through the insulation layer from the connecting portion; a third line on the insulation layer, the third line connecting the penetrating part. 
     In another aspect, the method for manufacturing a wiring structure in a semiconductor device comprises the steps of forming a line including an aluminum on a substrate; and forming a first metal layer covering the aluminum layer. Here, the portion of the aluminum layer which will be connected with another line is not covered by the first metal layer. The present invention further comprises the steps of an insulation layer on the aluminum layer and the first metal layer; and forming a second metal layer on the insulation layer with overlapping with the aluminum layer not covered by the first metal layer. Here, the aluminum layer not covered by the first metal layer has a hillock penetrating the insulation layer. Thus, the aluminum layer connects with the second metal layer through the hillock. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings: 
     FIG. 1 a  shows a cross sectional view of the conventional wiring structure for connecting two lines; 
     FIG. 1 b  shows a plan view of the conventional wiring structure for connecting two lines; 
     FIGS. 2 a - 2   d  show a process for connecting the two metal lines in the conventional art; 
     FIG. 3 a  shows a cross sectional view of a wiring structure for connecting two lines according to the first embodiment of the present invention; 
     FIG. 3 b  shows a plan view of a wiring structure for connecting two lines according to the first embodiment of the present invention; 
     FIGS. 4 a - 4   d  show a process for connecting the two metal lines according to the first embodiment of the present invention; 
     FIG. 5 shows a plan view of an LCD having a data shorting bar according to the second embodiment of the present invention; and 
     FIGS. 6 a - 6   d  show a process for connecting the odd data shorting bar to the odd data pad, and connecting the odd data shorting bar to the even data shorting bar, according to the second embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. 
     The present invention provides a bus line wiring structure and a method for connecting the bus lines formed in separate layers without forming a contact hole. The present invention further provides a method for protecting a wire during LCD production from static electricity by using a hillock grown on the surface of the aluminum layer. Accordingly, the present invention provides a wiring structure for connecting lines in a narrower space. 
     PREFERRED EMBODIMENT 1 
     FIG. 3 a  shows a cross sectional view of the wiring structure for connecting a gate line, formed of aluminum, for example, and another metal layer formed in a different layer. FIG. 3 b  shows a plan view of the wiring structure according to an embodiment of the present invention. 
     FIGS. 4 a - 4   d  show a manufacturing process according to an embodiment of the present invention. As shown in FIG. 4 a , a first metal, such as aluminum or aluminum alloy, is deposited on a substrate  111  to form an aluminum layer. Then, the aluminum layer is patterned to form a low resistance gate line  115   a  and a connecting portion  115   b.    
     As shown in FIG. 4 b , a second metal, such as chromium, molybdenum, tantalum, or antimony, is deposited on the substrate including the low resistance gate line  115   a . The second metal layer is patterned to form a gate line  115 , which covers the low resistance gate line  115   a  to prevent hillock growth on the surface. However, the connecting portion  115   b  formed at the end of the low resistance gate line  115   a  to be connected later with another metal layer is not covered by the gate line  115 . 
     As shown in FIG. 4 c , an insulating material, such as silicon oxide or silicon nitride, is deposited on the substrate including the gate line  115  to form a gate insulation layer  119 . Then, hillocks are grown on the surface of the portion  115   b  that is not covered by the gate line  115 . As mention in the description of the conventional art, the hillock of Al can be growing at 300° C. or higher. The metals, the first and the second metal, are deposited about 200° C., so the hillock of Al can not be growing when metal layers are formed. However, the insulating layer is deposited at about 390° C. So, when the insulating layer is deposited the hillocks of Al can be growing. 
     As shown in FIG. 4 d , a third metal, such as chromium or a chromium alloy, is deposited on the gate insulation layer  119 . The third metal layer is patterned to form a source line  135 . The source line  135  connects with the hillock passing through the gate insulation layer  119 , thereby electrically connecting the gate line  115  with the source line  135 . 
     Here, if the hillocks are not grown, then the connecting part that penetrate the gate insulation layer  119  does not form. Therefore, it is preferable to have the connecting portion  115   b  be wider than the covered portion of the low resistance gate line  115   a.    
     PREFERRED EMBODIMENT 2 
     This embodiment provides a shorting bar structure and a method for connecting the shorting bars formed in separate layers without forming a contact hole. 
     FIG. 5 shows a plan view of an LCD having an odd data shorting bar made of the material used in gate and an even data shorting bar made of the material used in source. 
     FIGS. 6 a - 6   d  show a manufacturing process according to this embodiment of the present invention. As shown in FIG. 6 a , a first metal, such as an aluminum or an aluminum ally, is deposited on a substrate  111  to form an aluminum layer. Then, the aluminum layer is patterned to form a low resistance source shoring bar  161   a , a first connecting portion  161   b  and a second connecting portion  161   c.    
     As shown in FIG. 6 b , a second metal, such as chromium, molybdenum, tantalum, or antimony, is deposited on the substrate including the low resistance odd source shorting bar  161   a , the first connecting portion  161   b  and the second connecting portion  161   c . The second metal layer is patterned to form an odd data shorting bar  161  which covers the low resistance odd source shorting bar  161   a  only to prevent hillock growth on the surface. However, the first connecting portion  161   b  and the second connecting portion  161   c  are not covered any other metal layer. 
     As shown in FIG. 6 c , an insulating material, such as silicon oxide or silicon nitride, is deposited on the substrate including the odd source shorting bar  161 , the first connecting portion  161   b  and the second connecting portion  161   c  to form a gate insulating layer  119 . Then, hillocks are grown on the surface of the first  161   b  and the second connecting portion  161   c . As mentioned in the first embodiment, the hillock of Al can be growing. 
     As shown in FIG. 6 d , a third metal, such as chromium or a chromium alloy, is deposited on the gate insulating layer  119 . The third metal layer is patterned to form a source line  135 , a source pad  137  and an even source shorting bar  165 . The source pad  137  is formed at the end of the source line  135 . The odd source pad  137  is connected with the hillocks  163  passing through the gate insulating layer  119  on the first connecting portion  161   b , thereby electrically connecting the odd source shorting bar  161  with the odd source pad  137 . The even source shorting bar  165  is connected with the hillocks  163  passing through the gate insulating layer  119  on the second connecting portion  161   c , thereby electrically connecting the odd source shorting bar  161  with the even source shorting bar  165 . Therefore, all source lines  135  and source pads  137  are in equal electric potential state, so the electrical static can be prevented. 
     As in the preferred embodiment 1, if the hillocks  163  are not grown, then the connecting part that penetrates the gate insulating layer  119  does not form. Therefore it is preferable to have the first  161   b  and the second connecting portion  161   c  be wider than the covered portion of the low resistance odd source shorting bar  161   a.    
     According to the present invention, the gate line, formed of aluminum, connects with the source line which formed in different layer. This is accomplished by growing the hillock on the aluminum surface that passes through the intervening insulation layer between the gate line and the source line. Therefore, contact holes and connectors are not needed to connect the two lines, thereby simplifying the connecting method. 
     Furthermore, the wiring structure does not require any contact holes formed in the same plane. The two lines overlap each other with the intervening insulation layer. Thus, they can be connected at the overlapped portion. Accordingly, the two lines can be connected in a narrow space. Therefore, the present invention provides an improved connecting method for high density semiconductor materials. 
     It will be apparent to those skilled in the art that various modifications and variations can be made in the bus line wiring structure in a semiconductor device and method of manufacturing the same of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.