Abstract:
NAND memory arrays and methods are provided. A plurality of first gate stacks is formed on a first dielectric layer that is formed on a substrate of a NAND memory array. The first dielectric layer and the plurality of first gate stacks formed thereon form a NAND string of memory cells of the memory array. A second gate stack is formed on a second dielectric layer that is formed on the substrate adjacent the first dielectric layer. The second dielectric layer with the second gate stack formed thereon forms a drain select gate adjacent an end of the NAND string. The second dielectric layer is thicker than the first dielectric layer.

Description:
TECHNICAL FIELD OF THE INVENTION  
       [0001]     The present invention relates generally to memory devices and in particular the present invention relates to NAND memory arrays and methods.  
       BACKGROUND OF THE INVENTION  
       [0002]     Memory devices are typically provided as internal storage areas in computers. The term memory identifies data storage that comes in the form of integrated circuit chips. In general, memory devices contain an array of memory cells for storing data, and row and column decoder circuits coupled to the array of memory cells for accessing the array of memory cells in response to an external address.  
         [0003]     One type of memory is a non-volatile memory known as flash memory. A flash memory is a type of EEPROM (electrically-erasable programmable read-only memory) that can be erased and reprogrammed in blocks. Many modern personal computers (PCs) have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in wireless electronic devices because it enables the manufacturer to support new communication protocols as they become standardized and to provide the ability to remotely upgrade the device for enhanced features.  
         [0004]     A typical flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating-gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed on an individual basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge on the floating gate.  
         [0005]     A NAND flash memory device is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged. Typically, the array of memory cells for NAND flash memory devices is arranged such that the control gate of each memory cell of a row of the array is connected to a word-select line. Columns of the array include strings (often termed NAND strings) of memory cells connected together in series, source to drain, between a pair of select lines, a source select line and a drain select line. The source select line includes a source select gate at each intersection between a NAND string and the source select line, and the drain select line includes a drain select gate at each intersection between a NAND string and the drain select line. The select gates are typically field-effect transistors. Each source select gate is connected to a source line, while each drain select gate is connected to a column bit line.  
         [0006]     The memory array is accessed by a row decoder activating a row of memory cells by selecting the word-select line connected to a control gate of a memory cell. In addition, the word-select lines connected to the control gates of unselected memory cells of each string are driven to operate the unselected memory cells of each string as pass transistors, so that they pass current in a manner that is unrestricted by their stored data values. Current then flows from the source line to the column bit line through each NAND string via the corresponding select gates, restricted only by the selected memory cells of each string. This places the current-encoded data values of the row of selected memory cells on the column bit lines.  
         [0007]     To prevent programming of unselected strings while selected strings are being programmed, the voltage level of the unselected strings is increased. However, current leakage (often referred to as gate-induced drain leakage or GIDL) through the drain select gates acts to reduce the increased voltage level of the unselected strings that can cause inadvertent programming of these strings and can reduce programming speeds.  
         [0008]     For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for reducing current leakage from drain select gates of unselected NAND strings.  
       SUMMARY  
       [0009]     The above-mentioned problems with current leakage from drain select gates of unselected NAND strings and other problems are addressed by the present invention and will be understood by reading and studying the following specification.  
         [0010]     For one embodiment, the invention provides a method of forming a NAND memory array that includes forming a plurality of first gate stacks on a first dielectric layer formed on a substrate, where the first dielectric layer and the plurality of first gate stacks formed thereon form a NAND string of memory cells of the memory array. The method includes forming a second gate stack on a second dielectric layer formed on the substrate adjacent the first dielectric layer, where the second dielectric layer with the second gate stack formed thereon forms a drain select gate adjacent an end of the NAND string and where the second dielectric layer is thicker than the first dielectric layer.  
         [0011]     For another embodiment, the invention provides a method of forming a NAND memory array that includes forming a first dielectric layer on a semiconductor substrate, forming a hard mask layer on the first dielectric layer, and removing a portion of the hard mask layer and the first dielectric layer to expose a portion of the substrate adjacent a remaining portion of the first dielectric layer. The method includes forming a second dielectric layer on the exposed portion of the substrate, where the second dielectric layer is thinner than the first dielectric layer. Removing the hard mask layer from the remaining portion of the first dielectric layer and forming a first gate stack on the first dielectric layer to form a drain select gate is included in the method. The method also includes forming a string of second gate stacks on the second dielectric layer to form a NAND string of floating-gate memory cells, where a first memory cell of the NAND string is adjacent the drain select gate.  
         [0012]     For another embodiment, the invention provides a NAND memory array having a plurality of rows of memory cells and a plurality of columns of NAND strings of memory cells. Each NAND string selectively connected to a bit line through a drain select gate of the respective column. Each of the drain select gates has a first dielectric layer formed on a semiconductor substrate of the memory array and a control gate formed on the first dielectric layer. Each of the memory cells of the NAND strings has a second dielectric layer formed on the substrate adjacent the first dielectric layer, a floating gate formed on the second dielectric layer, a third dielectric layer formed on the floating gate, and a control gate formed on the third dielectric layer, where the first dielectric layer is thicker than the second dielectric layer.  
         [0013]     Further embodiments of the invention include methods and apparatus of varying scope. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]      FIG. 1  is a simplified block diagram of a memory system, according to an embodiment of the invention.  
         [0015]      FIG. 2  is a schematic of a NAND memory array in accordance with another embodiment of the invention.  
         [0016]      FIGS. 3A-3F  are cross-sectional views of a portion of a memory array during various stages of fabrication, according to another embodiment of the invention. 
     
    
     DETAILED DESCRIPTION  
       [0017]     In the following detailed description of the invention, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The term wafer or substrate used in the following description includes any base semiconductor structure. Both are to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of a silicon supported by a base semiconductor structure, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a wafer or substrate in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure, and terms wafer or substrate include the underlying layers containing such regions/junctions. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and equivalents thereof.  
         [0018]      FIG. 1  is a simplified block diagram of a memory system  100 , according to an embodiment of the invention. Memory system  100  includes an integrated circuit flash memory device  102 , e.g., a NAND memory device, that includes an array of flash memory cells  104 , an address decoder  106 , row access circuitry  108 , column access circuitry  10 , control circuitry  112 , Input/Output (I/O) circuitry  114 , and an address buffer  116 . Memory system  100  includes an external microprocessor  120 , or memory controller, electrically connected to memory device  102  for memory accessing as part of an electronic system.  
         [0019]     The memory device  102  receives control signals from the processor  120  over a control link  122 . The memory cells are used to store data that are accessed via a data (DQ) link  124 . Address signals are received via an address link  126  that are decoded at address decoder  106  to access the memory array  104 . Address buffer circuit  116  latches the address signals. The memory cells are accessed in response to the control signals and the address signals. It will be appreciated by those skilled in the art that additional circuitry and control signals can be provided, and that the memory device of  FIG. 1  has been simplified to help focus on the invention.  
         [0020]      FIG. 2  is a schematic of a NAND memory array  200  as a portion of memory array  104  in accordance with another embodiment of the invention. As shown in  FIG. 2 , the memory array  200  includes word lines  202   1  to  202   N  and intersecting local bit lines  204   1  to  204   M . For ease of addressing in the digital environment, the number of word lines  202  and the number of bit lines  204  are each some power of two, e.g., 256 word lines  202  by 4,096 bit lines  204 . The local bit lines  204  are coupled to global bit lines (not shown) in a many-to-one relationship.  
         [0021]     Memory array  200  includes NAND strings  206   1  to  206   M . Each NAND string includes floating-gate transistors  208   1  to  208   N , each located at an intersection of a word line  202  and a local bit line  204 . The floating-gate transistors  208  represent non-volatile memory cells for storage of data. The floating-gate transistors  208  of each NAND string  206  are connected in series source to drain between a source select line  214  and a drain select line  215 . Source select line  214  includes a source select gate  210 , e.g., a field-effect transistor (FET), at each intersection between a NAND string  206  and source select line  214 , and drain select line  215  includes a drain select gate  212 , e.g., a field-effect transistor (FET), at each intersection between a NAND string  206  and drain select line  215 . In this way, the floating-gate transistors  208  of each NAND string  206  are connected between a source select gate  210  and a drain select gate  212 .  
         [0022]     A source of each source select gate  210  is connected to a common source line  216 . The drain of each source select gate  210  is connected to the source of the first floating-gate transistor  208  of the corresponding NAND string  206 . For example, the drain of source select gate  210   1  is connected to the source of floating-gate transistor  208   1  of the corresponding NAND string  206   1 . Each source select gate  210  includes a control gate  220 .  
         [0023]     The drain of each drain select gate  212  is connected to the local bit line  204  for the corresponding NAND string at a drain contact  228 . For example, the drain of drain select gate  212   1  is connected to the local bit line  204   1  for the corresponding NAND string  206   1  at drain contact  228   1 . The source of each drain select gate  212  is connected to the drain of the last floating-gate transistor  208   N  of the corresponding NAND string  206 . For example, the source of drain select gate  212   1  is connected to the drain of floating-gate transistor  208   N  of the corresponding NAND string  206   1 .  
         [0024]     Typical construction of floating-gate transistors  208  includes a source  230  and a drain  232 , a floating gate  234 , and a control gate  236 , as shown in  FIG. 2 . Floating-gate transistors  208  have their control gates  236  coupled to a word line  202 . A column of memory array  200  includes a NAND string  206  and the source and drain select gates connected thereto. A row of the floating-gate transistors  208  are those transistors commonly coupled to a given word line  202 .  
         [0025]      FIGS. 3A-3F  are cross-sectional views of a portion of a memory array, such as a portion of the memory array  200  of  FIG. 2 , during various stages of fabrication, according to another embodiment of the invention. In  FIG. 3A  a first dielectric layer  302 , e.g., an oxide layer, is formed, e.g., blanket deposited or thermally grown, on a semiconductor substrate  300  that is of monocrystalline silicon or the like. A hard mask layer  304  is formed on the first dielectric layer  302 . The hard mask layer  304  can be a second dielectric layer, such as a nitride layer, e.g., a silicon nitride (Si 3 N 4 ) layer, that is blanket deposited on the first dielectric layer  302 . Hard mask layer  304  is patterned and portions thereof are removed, e.g., by dry etching, in regions  310  where NAND strings of memory cells, such as floating gate memory cells, e.g., floating-gate transistors, will be formed, as shown in  FIG. 3B . For one embodiment, the first dielectric layer  302  is removed from regions  310  to expose portions  312  of substrate  300  in regions  310 , as shown in  FIG. 3B . For one embodiment, a selective dry etch that stops at substrate  300  accomplishes this.  
         [0026]     A third dielectric layer  314 , e.g., an oxide layer, is formed, e.g., thermally grown, on the exposed portions  312  of substrate  300  in  FIG. 3C . The third dielectric layer  314  is subsequently nitridized. For one embodiment, nitridation is performed by exposing the third dielectric layer  314  to a nitrogen-containing environment, e.g., an environment containing NO, N 2 O, NH 3 , etc. at an elevated temperature, in  FIG. 3D . The remaining portion of hard mask layer  304  is removed in  FIG. 3E .  
         [0027]     The resulting structure of  FIG. 3E  includes the first dielectric layer (or gate dielectric layer)  302  in a region  320  where drain select gates will be formed and the third dielectric layer (or tunnel dielectric layer)  314  in the regions  310  where the NAND strings will be formed. Note that the first dielectric layer  302  in region  320  can be thicker than the third dielectric layer  314  in the regions  310 . The thicker first dielectric layer  302  acts to reduce gate-induced drain leakage or GIDL through the drain select gates. Note further that hard mask layer  304  prevents nitridation of first dielectric layer  302 , where nitridation may negatively affect performance of the drain select gates and is not desired, but allows nitridation of third dielectric layer  314 , where the nitridation acts to improve reliability of the memory cells.  
         [0028]      FIG. 3F  illustrates gate stacks  322  and  324  formed on the first dielectric layer  302  and gate stacks  326  and  328  formed on the third dielectric layer  314 . Note that  FIG. 3F  has been enlarged for clarity. Gate stacks  322  and  324  and the first dielectric layer  302  form drain select gates  323  and  325 , e.g., field effect transistors (FETs), where the first dielectric layer  302  acts as a gate dielectric layer of drain select gates  323  and  325 . Gate stacks  326  and the third dielectric layer  314  form floating-gate memory cells  327 , such as floating-gate transistors, and gate stacks  328  and the third dielectric layer  314  form floating-gate memory cells  329 , such as floating-gate transistors, where the third dielectric layer  314  acts as a tunnel dielectric layer for memory cells  327  and  329 . Gate stacks  330  and  332  are also formed on the third dielectric layer  314 . Gate stacks  330  and  332  and the third dielectric layer  314  form source select gates  331  and  333 , e.g., field effect transistors (FETs), where the third dielectric layer  314  acts as a gate dielectric layer of source select gates  331  and  333 . It will be apparent that the process could be readily modified to form a source select gates  331  and  333  on portions of the first dielectric layer  302  similar to drain select gates  323  and  325  if desired.  
         [0029]     Memory cells  327  are connected in series, source to drain, between drain select gate  323  and source select gate  331  to form a NAND string  334  between drain select gate  323  and source select gate  331 . Memory cells  329  are connected in series, source to drain, between drain select gate  325  and source select gate  333  to form a NAND string  335  between drain select gate  325  and source select gate  333 . For one embodiment, source/drain regions  336  are formed in substrate  300 . For another embodiment, successive memory cells of the respective NAND strings share a source/drain region  336 , drain select gate  323  and memory cell  327   1  of NAND string  334  share a source/drain region  336 , source select gate  331  and memory cell  327   K  of NAND string  334  of NAND string  334  share a source/drain region  336 , drain select gate  325  and memory cell  329   1  of NAND string  335  share a source/drain region  336 , and source select gate  333  and memory cell  329   L  of NAND string  335  share a source/drain region  336 .  
         [0030]     Each of gate stacks  323  and  325  include a first conductive layer  338 , such as a conductively doped polysilicon layer, formed on the first dielectric layer  302 , a fourth dielectric layer  340  formed on the first conductive layer  338 , and a second conductive layer  350  formed on the fourth dielectric layer  340 . Each of gate stacks  326 ,  328 ,  330 , and  332  include the first conductive layer  338  formed on the third dielectric layer  314 , the fourth dielectric layer  340  formed on the first conductive layer  338 , and the second conductive layer  350  formed on the fourth dielectric layer  340 .  
         [0031]     For one embodiment, the second conductive layer  350  is a conductively doped polysilicon layer or a metal or metal-containing layer, such as a refractory metal or refractory metal silicide layer. The metals of chromium (Cr), cobalt (Co), hafnium (Hf), molybdenum (Mo), niobium (Nb), tantalum (Ta), titanium (Ti), tungsten (W), vanadium(V) and zirconium (Zr) are generally recognized as refractory metals. For another embodiment, the second conductive layer  350  may be a single conductive layer of one or more conductive materials, e.g., metal or metal-containing materials, or two or more conductive layers, such as a metal or metal-containing layer formed on a conductively doped polysilicon layer. For one embodiment, the fourth dielectric layer  340  may be an oxide layer, a nitride layer, an oxide-nitride-oxide (ONO) layer, etc.  
         [0032]     For each of the memory cells  327  and  329 , the second conductive layer  350  is a control gate (or a word line, such as a word line  202  of  FIG. 2 ), the first conductive layer  338  is a floating gate, and the fourth dielectric layer interposed between the first conductive layer  338  and the second conductive layer  350  is an intergate dielectric layer. For each of the drain select gates  323  and  325  and the source select gates  331  and  333 , for some embodiments, the first conductive layer  338  and the second conductive layer  350  may be strapped (or shorted) together so that the shorted together first conductive layer  338  and second conductive layer  350  form a control gate of the respective select gates, where the control gate of each of the source select gates  331  and  333  is a source select line, such as a source select line  214  of  FIG. 2 , and the control gate of each of the drain select gates  323  and  325  is a drain select line, such as a drain select line  215  of  FIG. 2 . For another embodiment, the first conductive layer  338  and the second conductive layer  350  are not shorted together, and first conductive layer  338  forms the control gate of the respective select gates.  
         [0033]     Formation of gate stacks  322 ,  324 ,  326 ,  328 ,  330 , and  332  is well known and will not be detailed herein. Generally, the first conductive layer  338  is formed on the first dielectric layer  302  and the third dielectric layer  314 . After the first conductive layer  338  is formed, it is patterned parallel to the plane of  FIG. 3F . The fourth dielectric layer  340  is then formed on the first conductive layer  338 , and the second conductive layer  350  is formed on the fourth dielectric layer  340 . The second conductive layer  350  is patterned orthogonally to the patterning of the first conductive layer  338 , and the second conductive layer  350 , the fourth dielectric layer  340 , and the first conductive layer  338  are removed, e.g., by selective etching that stops at the first dielectric layer  302  and the third dielectric layer  314 , to expose portions of the first dielectric layer  302  between gate stacks  322  and  324 , between gate stacks  322  and  326   1 , and between gate stacks  324  and  328   1 . This also exposes portions of the third dielectric layer  314  between gate stacks  322  and  326   1 , between gate stacks  324  and  328   1 , between gate stacks  330  and  326   K , between gate stacks  332  and  328   L , and between successive gate stacks  326  and successive gate stacks  328 .  
         [0034]     It is generally desirable to use the same processing for all of the gate stacks and to short the first and second conductive layers of the gate stacks of the drain and source select gates together, as described above. However, since the select gates function differently than the memory cells, the gate stacks of the select gates can be formed independently of the gate stacks of the memory cells.  
       CONCLUSION  
       [0035]     Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the invention will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the invention. It is manifestly intended that this invention be limited only by the following claims and equivalents thereof.