Abstract:
A spread spectrum clock signal generator and an accompanying method provide a spread spectrum clock signal of a reduced electromagnetic interference. The spread spectrum clock signal generator includes (a) a state machine, which maintains a current state of the spread spectrum clock signal generator, receives as input value a next state of the spread spectrum clock signal generator and generates a clock phase selection signal based on the current and next states; (b) a random number generator for generating the next state; and (c) a waveform generation circuit for generating a spread spectrum clock signal based on the clock phase selection signal.

Description:
REFERENCE TO RELATED APPLICATIONS  
       [0001]     The present application is related to and claims priority to copending U.S. provisional patent application, entitled “Spread Spectrum Clock Generator and Method,” Ser. No. 60/822,311, filed on Aug. 14, 2006. The disclosure of the copending provisional application is hereby incorporated by reference in its entirety. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to high speed data communication (e.g., 1 G-bit/second or higher). In particular, the present invention relates to a signaling technique that reduces electromagnetic interference (EMI) associated with parallel data.  
         [0004]     2. Discussion of the Related Art  
         [0005]     Parallel data provided at a high data rate transitioning at a fixed frequency (i.e., at fixed regular data intervals) may generate electromagnetic noise with sufficient energy to interfere with operations in other electronic devices (e.g., wireless or cellular telephones). Such electromagnetic noise is characterized by having a large amount of energy concentrated at the frequencies of the data transitions. It is known that a spread spectrum technique can be applied to alleviate the interference by distributing the energy of the electromagnetic noise over a wider range of frequencies.  
         [0006]     Significant EMI problems may arise in a deserializer application in which data in a serial data signal are converted to parallel data. Spread spectrum techniques may be applied to reduce EMI. However, to apply spread spectrum techniques to such an application requires an additional external spread spectrum crystal source, a complicated phase-locked loop (PLL) for the receiving the input serial signal and a digital spread spectrum clock generator to modulate the serial data. These additional components increase both the cost and design time for the deserializer circuit.  
       SUMMARY OF THE INVENTION  
       [0007]     According to one embodiment of the present invention, a spread spectrum clock signal generator and an accompanying method provide a spread spectrum clock signal of a reduced electromagnetic interference. The spread spectrum clock signal generator includes (a) a state machine, which (i) maintains a current state of the spread spectrum clock signal generator, (ii) receives as input value a next state of the spread spectrum clock signal generator and (iii) generates a clock phase selection signal based on the current and next states; (b) a random number generator for generating the next state; and (c) a waveform generation circuit for generating the spread spectrum clock signal based on the clock phase selection signal.  
         [0008]     In one embodiment of the present invention, a receiver including the spread spectrum signal generator receives a serial data signal to provide parallel data signals clocked at by the spread spectrum clock signal generated by the spread spectrum signal generator. In that embodiment, the spread spectrum clock signal has an average frequency that is a predetermined fraction of the clock signal that clocks the serial data signal. In one implementation, the clock signal for the serial data signal is embedded in the serial data signal and recovered in the receiver.  
         [0009]     The present invention is better understood upon consideration of the detailed description below and the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]      FIG. 1  shows serializer/deserializer circuit  100  which is an exemplary circuit suitable for implementing a spread spectrum clock generation circuit, according to one embodiment of the present invention.  
         [0011]      FIG. 2  shows spread spectrum clock generator circuit  200 , in accordance with one embodiment of the present invention.  
         [0012]      FIG. 3  shows a state transition table which indicates the duration, in number of 1× clock cycles, for the next state.  
         [0013]      FIG. 4  shows selected clock waveforms in clock signal generator  203 , in accordance with one embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0014]     The present invention generates a spread spectrum clock signal to be used for modulating data transitions in parallel data lines, so as to reduce electromagnetic interference (EMI).  
         [0015]     One application of the present application may be the data transmission between a video decoder (e.g., a DVD player) and a video display system (e.g., an LCD monitor).  FIG. 1  shows serializer/deserializer circuit  100  which is an exemplary circuit suitable for implementing the spread spectrum clock generator circuit, according to one embodiment of the present invention. In the application between the video decoder and the video display system, a copy of serializer/deserializer circuit  100  may be provided at each end. The serializer/deserializer circuits are then connected by a single serial cable.  
         [0016]     As shown in  FIG. 1 , serializer/deserializer circuit  100  includes 3-1 serializer circuit  101 , which serializes three 8-bit parallel data streams into a single 3× 8-bit parallel data stream at 3 times the data rate of the input data streams 1 . The three input data streams may be, for example, three video data streams for driving three or more graphical displays (e.g., LCD monitors). Multiplexer  102  may select, in addition to the 3× 8-bit data stream from 3-1 serializer circuit  101 , one or more additional 8-bit data streams (e.g., video data control signals and a control data stream) for transmission. Video data control signals may include V_SYNC (vertical synchronization), H_SYNC (horizontal synchronization) and DE (display enable). The selected 8-bit data stream from multiplexer  102  is encoded in 8/10-bit encoder  103 , using an 8/10 b coding scheme for serial data transmission known to those skilled in the art. 8-bit test data may be injected into the data stream at 8/10-bit encoder  103 . The 10-bit encoded data is serialized in serializing circuit  104  for transmission by transmitter  105  into the communication channel (i.e., the serial cable). In this embodiment, as in many high speed communication schemes, the communication channel may use low voltage differential signaling (LVDS). Transmission circuit  105  may include a pre-emphasis circuit to shape the output waveform to compensate anticipated distortion in the communication channel. Management unit  106  provides the necessary 1×, 3× and 30× system clock signals.    1 The 3-1 serialization combining three 10-bit data streams into a single serial data stream is provided herein merely as an example. Other serialization scheme (e.g., combining two serial 10-bit data streams into a single serial data stream) are possible and falls within the scope of the present invention.    
         [0017]     Serializer/deserializer circuit  100  includes a receiver circuit for receiving data in the reverse direction from the communication channel. The receiver circuit includes equalizer  107 , which further compensates for distortion in the communication channel. Clock recovery circuit  108  recovers the 30× system clock signal, which is then used to provide the 1×, 3× and 30× clock signals used in the receiver circuit. The received serial data stream is deserialized in deserializer  109  into a 10-bit data stream, which is decoded by 8/10 b decoder  110  according to the coding scheme back to an 8-bit data stream. From this decoded 8-bit data stream (at three times data rate), demultiplexer  111  recovers the 3× 8-bit data stream and the control data stream. The video data control signals are also recovered from the decoded 8-bit data stream by receiver controller  114 . The individual input 8-bit data streams are recovered in 3-1 deserializer  112  from the 3× 8-bit data stream. Clock randomizer circuit  115  modulates the individual data signals and the 1× clock signal to reduce electromagnetic interference (EMI). The control data to be transmitted and the control data received are stored respectively in registers  113   a  and  113   b  respectively. The control data may originate from or directed to devices attached to an I 2 C interface bus.  
         [0018]     In the above description, serializer/deserializer circuit  100  operates in a 24-to-1 mode (i.e., serializing three 8-bit data streams). Serializer/deserializer circuit  100  may also operate in a 16-to-1 data mode. Data may be grouped under either mode in units of “pixel”. Under 24-to-1 mode, each pixel transmitted consists of three 10-bit bytes, and under 16-t0-1 mode, each pixel consists of two 10-bit bytes.  
         [0019]     For this embodiment, the spread spectrum clock generator of the present invention may provide the 1× clock signal by dividing down the input clock clk_in (i.e., the 30× clock signal) to a clock signal having a frequency that varies between frequencies clk_in/27 and clk_in/33. The frequency variation may be provided, for example, in accordance with a Gaussian distribution that has a mean frequency of clk_in/30. To implement such a scheme, clock randomizer circuit  115  includes a spread spectrum clock generator, which may be implemented by clock generator circuit  200  of  FIG. 2 . As shown in  FIG. 2 , clock signal circuit  200  includes state machine  201 , random number generator  202 , and clock signal generator  203 . Clock signal generator  203  generates the 1× clock signal by selecting one of seven clock phases to drive 3-1 deserializer  112 . State machine  201  implements seven states: −3, −2, −1, 0, 1, 2 and 3. The state number represents the phase offset in clk_in periods (“t_clk_in&#39;s”) between corresponding edges of the selected clock signal relative to the clk_in/30 signal. For example, if the previous state of the 1× clock signal is −2, the previous rising edge of the 1× clock signal is two_t_clk_in&#39;s earlier than the rising edge of the clk_in/30 clock signal; similarly, if the previous state of the 1× clock signal is 3, the rising or falling edge of the 1× clock signal is three t_clk_in&#39;s later than the corresponding edge in the clk_in/30 signal.)  
         [0020]      FIG. 3  shows a state transition table which indicates the time in t_clk_in&#39;s between previous rising or falling edge and the present corresponding edge. For example, if the previous state is −3 and the present state is −1, there are 32 t_clk_in&#39;s between the previous rising edge and the present rising edge, so that the average frequency for the 1× clock is maintained at clk_in/30.  
         [0021]      FIG. 4  shows selected clock waveforms in clock signal generator  203 . As shown in  FIG. 4 , waveform  401  indicates the transition times for various clock phase offsets. For example, transition times  401   a  and  401   b  indicate the transition times for leading edges of clock phases −3 and −2 respectively. Similarly, transition times  401   c  and  401   d  indicating the trailing edges of clock phases −3 and −2, respectively. In this embodiment, differential signaling is used. Waveforms  402  and  403  are the waveforms at the terminals of the 1× clock signal for phase −3. Similarly, waveforms  404  and  405  are the waveforms at the terminals of 1× clock signal −2.  FIG. 4  shows state machine entering states −3, −2, −3 and −2 in sequence. Waveforms  406  and  407  show the selection of the transition times at the terminals of the 1× clock signal according to this transition sequence. Waveform  408  represents the single-ended clock signal derived from differential waveforms  406  and  407 .  
         [0022]     The detailed description above is provided to illustrate the specific embodiments of the present invention and is not intended to be limiting. Numerous variations and modifications within the scope of the present invention are possible. The present invention is set forth in the following claims.