Abstract:
A process and apparatus directed to forming low resistance contacts in both the memory cell array and peripheral logic circuitry areas of a semiconductor device, for example, a DRAM memory device, is disclosed. In a buried bit line connection process flow, the present invention utilizes chemical vapor deposition of titanium to form titanium silicide in contact structures of the peripheral logic circuitry areas and physical vapor deposition to provide a metal mode (metallic) titanium layer in contact with the poly plugs in the memory cell array area of a semiconductor device, for example, a DRAM memory device according to the present invention. In this manner, the present invention avoids the potential drawbacks such as voiding in the poly plugs of the memory cell array due to the present of titanium silicide, which can cause significant reduction of device drain current and in extreme cases cause electrical discontinuity.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to the field of integrated circuits and, in particular, the use of low resistance peripheral contacts while maintaining memory cell array integrity of a memory device, such as dynamic random access memories (DRAMs).  
       BACKGROUND OF THE INVENTION  
       [0002]     Complex integrated circuits, such as dynamic random access memories (DRAMs), have multiple levels of conductors above the surface of a silicon substrate that are used to interconnect various portions of a fabricated circuit. For DRAM devices, the doped regions or active area of a transistor fabricated in a substrate are typically contacted using polysilicon (poly) plugs, which may connect with a capacitor, a bit line, or other conductor layers. Metal contacts would provide better conductivity than poly plugs; however, metal contacts are typically not used to contact the doped regions of a substrate because of processing restraints including the heat sensitivity of a metal contact to later high temperature fabrication processes and possible active area contamination caused by metal diffusing into the active area of the substrate.  
         [0003]     In DRAM devices, heat cycles are often used to anneal capacitor structures formed after formulation of the substrate contacts, which would melt the metal and cause the metal to diffuse into the substrate and thereby contaminate the active area and ruin conductivity between the contact and the substrate. Nevertheless, because of its better conductive properties, it is preferable, if at least some of the contacts to the substrate surface were made of metal instead of polysilicon.  
         [0004]     One method of increasing conductivity involves the deposition of a thin titanium film, over the wafer so that it covers the enhanced region at the bottom of the contact opening prior to deposition of additional conductive layers. However, as contact structures, such as trenches, contact openings, and vias, are made smaller, they become more difficult to fill. To begin to appreciate this problem, it should be understood that the lateral dimension of such structures is typically referred to as the “width” and the vertical dimension of such structures is typically referred to as the “depth.” The aspect ratio is the ratio of depth to width. Thus, as the features have become smaller, the aspect ratio has risen, resulting in high aspect structures, which as mentioned above, become more difficult to fill void-free, and preferably seam-free, with an appropriate material. Accordingly, many different techniques have been developed in an effort to address this problem. For example, films may be deposited by several different methods, such as spin-on deposition, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), and physical deposition.  
         [0005]     Of the methods mentioned above, it is arguable that CVD and PECVD are best suited to deposit the thinnest films in high aspect ration contact structures. However, utilizing CVD or PECVD in order to provide a titanium film layer in the high aspect ratio contact structures in the peripheral circuit logic area at the processing level for forming bit line connections when typically doped polysilicon (poly) plugs in the memory cell array area are exposed, thereby contacting CVD titanium with the poly plugs, is problematic. Through subsequent heat cycles, titanium in the film layer covering the poly plugs will migrate into the doped poly plug and form titanium silicide. The formation of titanium silicide, however, causes voids to form in the poly plugs and titanium layer due to the respective volume changes, which can cause significant reduction of device drain current and in extreme cases cause electrical discontinuity. Additionally, titanium silicide formation will also cause dry etch issues in subsequent processing steps as the titanium silicide will etch faster than the poly plug, cause undercutting and lifting of laid lines. As a result, using a titanium layer deposited by chemical vapor deposition, which can make low resistance contacts, is excluded during the buried bit line connection process flow due to the above mentioned potential drawbacks.  
       SUMMARY OF THE INVENTION  
       [0006]     It is against the above background that the present invention provides a method and apparatus directed to forming low resistance contacts in both memory cell array and peripheral logic circuitry areas of a semiconductor device, for example, a DRAM device, which provides a number of advancements and advantages over the prior art. In a buried bit line connection process flow, the present invention utilizes chemically vapor deposition of titanium to form a titanium/titanium silicide layer in the contacts of the peripheral logic circuitry areas, and physical vapor deposition to provide a metal mode (metallic) titanium layer contacting the poly plugs in the memory cell array areas of a semiconductor device according to the present invention. When the layers are annealed at temperatures above 650° C. in subsequent heat cycles, titanium silicide is only formed in the peripheral logic circuitry areas as the metal mode titanium layer in contact with the poly plugs provides a suitable thermal barrier as nitrogen is denuded from an overlaying tungsten nitride film and ties up dangling bonds in the metal mode titanium layer, so less titanium reacts with the poly plus, thereby forming insignificant amounts of titanium silicide. In this manner, the present invention avoids the potential drawbacks such as voiding in the poly plugs of the memory cell array due to the presence of titanium and subsequent volume change due to titanium silicide formation, which can cause significant reduction of device drain current and in extreme cases cause electrical discontinuity.  
         [0007]     In one embodiment, a method of forming a memory device is disclosed. The method comprises providing a substrate having a memory cell array area and a peripheral circuitry area, wherein said memory cell array area comprises at least one polysilicon plug; providing an insulating layer over said substrate; defining at least one periphery contact opening in material layers over said substrate at said periphery circuitry area of said substrate, wherein said material layers is at least said insulating layer, and said at least one periphery contact opening exposes said substrate; forming a titanium film layer over said insulating layer and into said at least one periphery contact opening to contact said substrate and form titanium suicide; defining at least one memory cell array contact in said material layers over said substrate at said memory cell array area of said substrate, said at least one memory cell array contact opening exposes said at least one polysilicon plug; and forming a metal mode (metallic) titanium film layer over said substrate and into said at least one memory cell array contact opening to contact said at least one polysilicon plug.  
         [0008]     These and other features and advantages of the invention will be more fully understood from the following description of various embodiments of the invention taken together with the accompanying drawings.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]     The following detailed description of the embodiments of the present invention can be best understood when read in conjunction with the following drawings, where like structure is indicated with like reference numerals and in which:  
         [0010]      FIG. 1  is a cross-sectional view of the early stages of fabrication of a semiconductor device in accordance with an exemplary embodiment of the present invention.  
         [0011]      FIG. 2  shows the semiconductor device of  FIG. 1  at a processing step subsequent to that shown in  FIG. 1 .  
         [0012]      FIG. 3  shows the semiconductor device of  FIG. 1  at a processing step subsequent to that shown in  FIG. 2 .  
         [0013]      FIG. 4  shows the semiconductor device of  FIG. 1  at a processing step subsequent to that shown in  FIG. 3 .  
         [0014]      FIG. 5  shows the semiconductor device of  FIG. 1  at a processing step subsequent to that shown in  FIG. 4 .  
         [0015]      FIG. 6  shows the semiconductor device of  FIG. 1  at a processing step subsequent to that shown in  FIG. 5 .  
         [0016]      FIG. 7  shows the semiconductor device of  FIG. 1  at a processing step subsequent to that shown in  FIG. 6 .  
         [0017]      FIG. 8  shows the semiconductor device of  FIG. 1  at a processing step subsequent to that shown in  FIG. 7 .  
         [0018]      FIG. 9  shows the semiconductor device of  FIG. 1  at a processing step according to an alternate embodiment of the present invention.  
         [0019]      FIG. 10  shows the semiconductor device of  FIG. 1  at a processing step subsequent to that shown in  FIG. 9  according to an alternate embodiment of the present invention.  
         [0020]      FIG. 11  shows the semiconductor device of  FIG. 1  at a processing step subsequent to that shown in  FIG. 10  according to an alternate embodiment of the present invention.  
         [0021]      FIG. 12  shows the semiconductor device of  FIG. 1  at a processing step subsequent to that shown in  FIG. 11  according to an alternate embodiment of the present invention.  
         [0022]      FIG. 13  shows the semiconductor device of  FIG. 1  at a processing step subsequent to that shown in  FIG. 12  according to an alternate embodiment of the present invention.  
         [0023]      FIG. 14  shows the semiconductor device of  FIG. 1  at a processing step subsequent to that shown in  FIG. 13  according to an alternate embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0024]     In the following detailed description, reference is made to various specific embodiments in which the invention may be practiced. These embodiments are described with sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be employed, and that various structural, logical, and electrical changes may be made without departing from the spirit or scope of the invention. Additionally, well-known structures, processes, and materials associated with microelectronic device fabrication have not been shown in detail in order to avoid unnecessarily obscuring the description of the embodiments of the invention.  
         [0025]     Furthermore, skilled artisans appreciate that elements in the figure are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figure may be exaggerated relative to other elements to help to improve understanding of the various embodiments of the present invention.  
         [0026]     The term “substrate” used in the following description may include any semiconductor-based structure that has an exposed substrate surface. Structure should be understood to include silicon-on-insulator (SOI), silicon-on-sapphire (SOS), doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. When reference is made to a substrate or wafer in the following description, previous process steps may have been utilized to form regions or junctions in or over the base semiconductor or foundation.  
         [0027]     The present invention relates to forming, during a buried bit line connection process flow, low resistance contacts to a substrate in the peripheral circuit logic area and to poly plugs in the memory cell array area formed as part of a memory device, such as a DRAM memory device. The present invention will be described as set forth in an exemplary embodiment illustrated below. Other embodiments may be used and structural or logical changes may be made without departing from the spirit or the scope of the present invention.  
         [0028]     In accordance with the present invention, a method is provided for forming low resistance contacts for both N and P doped active regions in a peripheral logic circuitry area, which is typically formed outside of and around a memory cell array area. Referring now to the drawings, where like elements are designated by like reference numerals,  FIGS. 1 through 14  illustrate exemplary embodiments of the fabrication steps and resulting structures in accordance with the present invention.  
         [0029]     Referring to  FIG. 1 , on a substrate  100 , a memory cell array indicated generally by reference numeral  102  and a peripheral circuitry area, indicated generally by reference numeral  104  are shown during an early stage of fabrication. The peripheral circuitry area  104  is typically either an N-channel transistor area or a P-channel transistor area. The memory cell array  102  includes gate stacks  106 ,  108 ,  110 ,  112 , where in one embodiment, gate stacks  108  and  110  in the memory cell array comprise electrically isolated word lines  114 ,  116 . Active areas are provided about the gate stacks  106 ,  108 ,  110 ,  112 , such as the doped active areas  120 ,  122 ,  124  that form Field Effect Transistors (FETs) provided between field isolation areas  118 ,  126 .  
         [0030]     Each of the gate stacks  106 ,  108 ,  112  includes a layer of oxide  128 , such as silicon dioxide in contact with the substrate, a layer of polysilicon  129  provided on the oxide, a conductive gate layer  130  provided on the poly, an insulating cap layer  132 , and insulating sidewalls  134 . Provided between the gate stacks  106 ,  108 ,  110 ,  112  are polysilicon (poly) plugs  136 ,  138 ,  140 . The polysilicon (poly) plugs  136 ,  140  shown in  FIG. 1  will connect with subsequently formed memory cell capacitors and poly plug  138  will connect with a subsequently formed bit line. Accordingly, gate stacks  108 ,  110  are part of access transistors  142 ,  144  for respective memory cells. Additionally, gate stacks  106 ,  112  formed pair of other memory cells in a different cross-sectional plane from that illustrated, which are used for self-aligned fabrication processes, and field oxide regions  118 ,  126  are used to isolating the memory cells in the memory cell array  102 .  
         [0031]     A doped well  146  may be provided in the substrate  100  and associated with a respective memory cell array  102  and peripheral circuitry area  104 . For the N-channel transistors, the doped well  146  is a p-well, while for the P-channel transistors the doped well is a n-well, as is well known in the art.  
         [0032]     As further shown in  FIG. 1 , planarized first insulating layer  148 , formed of, for example, borophosphosilicate glass (BPSG) or silicon dioxide has been formed over the gate stacks and active areas. The first insulating layer  148  is then planarized by chemical mechanical polishing (CMP) or other suitable means. A second insulating layer  150 , formed of, for example, tetraethylorthosilicate (TEOS) or other oxide, is formed over the first insulating layer  148 . The second insulating layer  150  is deposited with a thickness, for low resistance contacts of current integration size and levels, in a range of about 5 Angstroms to about 10,000 Angstroms. Of course, one skilled in the art will be able to easily vary the relevant dimensions to fit the particular application. If desired, the second insulating layer  150  may also by planarized by chemical mechanical polishing (CMP) or other suitable means, however, this step may be skipped as the first insulating layer  148  is planar. The structure shown in  FIG. 1  serves as the starling foundation for the invention which is discussed hereafter.  
         [0033]     The process of the present invention begins by applying a photoresist mask  152  to the second insulating layer  150 . Opening  154  in the mask defines an etch location of a peripheral contact to other wordlines and actives areas. As shown in  FIG. 2 , a first portion of the first and second insulating layers is removed by etching to expose, for example, an active area  156  which is N+ doped for N-channel transistors, and P+ doped for P-channel transistors. It is also possible to dope the active area  156  after the etching operation instead of doping such areas prior to etching. The contact opening  158  is thus provided, as shown in  FIG. 2 .  
         [0034]     As shown by the structure illustrated in  FIG. 3 , after contact opening  158  is formed, such as by reactive ion etching (RIE), the photoresist mask  152  is removed and a low resistance metal film layer  160  is deposited by CVD over the second insulating layer  150 . The metal film layer  160  is titanium which will cover the contact opening  158 , and form titanium silicide (TiSi x ) in the peripheral circuitry area  104  in a subsequent heating cycle when the layers are annealed at temperatures above 650° C. The metal film layer  160  is deposited with a thickness in a range of about 1 Angstrom to about 5,000 Angstroms. As the second insulating layer  150  is intact over the memory cell array area  102 , no CVD Ti comes into contact with poly plug  138 , which will connect with a subsequently formed bit connection.  
         [0035]     In another embodiment, TiSi x  can be provided in the contact opening  158  by reacting chemically vapor deposited Ti with Si from the substrate  100  or with Si simultaneously added from the vapor phase. For example, the titanium silicide areas in the contact opening  158  may be formed by depositing Ti from the precursor TiCl4, with the Si coming from the substrate  100  or from added gas-phase SiH 4  or SiH 2 Cl 2 .  
         [0036]     As illustrated by  FIG. 4 , after Ti deposition, a second photoresist mask  162  is provided over the Ti film layer  160  to a thickness standard in the art, and patterned to provide an opening  164  located over the memory cell array area  102 , and in particular, poly plug  138 . As shown by the structure illustrated in  FIG. 5 , bit connection opening  166  is formed by anisotropically etching through the first and second insulating layers  150 ,  160 , thereby opening the bit connections in the memory cell array area  102 . It is to be appreciated that the etching process to form the bit connection openings in the memory cell array area  102  can be one or more process steps (in-situ or ex-situ).  
         [0037]     For example, in one embodiment, in a first part of the bit connection opening formation process, the Ti metal film layer  160  is anisotropically etched using a reactive halogen containing plasma etch process, such as chlorine, fluorine, and the like, which is very selective and stops at the first insulating layer  150 . In a second pair of the bit connection opening formation process, the first insulating layer  150  is then anisotropically etched using a reactive halogen containing plasma etch process to remove the portion of the first insulating layer  150  over the bit connections, thereby exposing the bit connection poly plugs, such as for example, poly plug  138 .  
         [0038]     As shown by  FIG. 6 , the second photoresist mask  162  is stripped and then a standard metal deposition pre-clean step is performed. Referring now to  FIG. 7 , after the formation and cleaning of the contact opening  166 , a low-resistivity metal mode titanium/tungsten nitride/tungsten (MMTI/WN/W) film stack is provided. First, a metal mode (metallic) titanium film layer  170  is deposited, using a physical vapor deposition (PVD) process, over the memory cell array and peripheral circuitry areas  102  and  104 , respectively, which fills into the openings  154 ,  166  ( FIG. 6 ). It is to be appreciated that the metal mode titanium film layer  170  does not form silicides or ultra thin silicides, thus providing good contact to the poly plug  138  without voiding. The metal mode titanium film layer  170  is deposited with a thickness in a range of about 1 Angstrom to about 5000 Angstroms.  
         [0039]     Next, the WN/W layer  172  is deposited using either a PVD or CVD process, which completely fills the peripheral contact opening  154  and partially fills contact opening  166  ( FIG. 6 ). The WN/W film layer  172  is deposited with a thickness in a range of about 5 Angstroms to about 5000 Angstroms. Finally, a nitride capping layer  174  is deposited over the substrate filling completely the contact opening  166 , and planarized to have a thickness in a range of about 100 Angstroms to about 10,000 Angstroms.  
         [0040]     As shown in  FIG. 8 , a directional etching process or other suitable process is used to etch through a photoresist mask (not shown) to remove portions of layers  160 ,  170 ,  172 ,  174  in areas not desired and in order to form low resistance contacts  176 ,  178 . The contacts  176 ,  178  may be of any suitable size and shape so as to provide a low resistance vertical path to the active areas  122 ,  146 . The contacts, such as contact  176 , in the peripheral circuitry area  104  are preferably of a smaller area than the contacts, such as contact  178 , in the memory cell array area  102 .  
         [0041]     An alternate embodiment is described with reference to  FIGS. 9-14 . Like numerals from the first described embodiment are utilized where appropriate, with differences being indicated by 200 series numerals or with different numerals.  FIG. 9 , shows a processing step conducted similar to the processing steps shown in  FIG. 1 , except that the first photoresist mask  152  is patterned to provide the contact opening  164  in the memory cell array area  102 , and not the peripheral circuitry area  104  as in  FIG. 1 . A directional etching process or other suitable process occurs to etch through the first insulating layer  150  as indicated by the dotted lines in  FIG. 9 , thus exposing poly plug  138 .  
         [0042]     Referring to  FIG. 10 , the photoresist mask layer  152  is then removed after the etching process, and the metal mode titanium layer  170  is deposited over the memory cell array and the peripheral circuitry areas  102  and  104 , respectively. The metal mode deposition is then followed by a deposition of a tungsten nitride layer  200 . Accordingly, the metal mode titanium layer  170  is formed over the exposed outer surfaces of poly plug  138 . Alternatively, layer  170  may comprise titanium, titanium nitride, tungsten, cobalt, molybdenum or tantalum, but any suitable metal may be used. Additionally, each layer  170 ,  200  may be planarized by, for example, by CMP after deposition.  
         [0043]     As shown in  FIG. 11 , the second photoresist layer  162  has been deposited over the substrate to fill opening  164  above the poly plug  138 . The photoresist layer  162  is then patterned to form the etching opening  154  for the subsequently formed peripheral contact.  
         [0044]     As shown in  FIG. 12 , a directional etching or other suitable etch process is performed to etch through layers  148 ,  150 ,  170 , and  200  to form the contact opening  154  so as to expose a contact area in the substrate  100 . It is to be appreciated that the metal mode titanium layer  170  and tungsten nitride layer  200  are used as a hard mask if needed, such that only the first and second insulating layers  148 ,  150  are etched after etching portions of layers  170 ,  200  with the directional etching process. The contact opening  154  in one embodiment is of a smaller diameter than the opening  164  above the poly plug  138 .  
         [0045]     After formation of the peripheral contact opening  154 , the second photoresist layer  162  is striped away, and the titanium layer  160  is deposited by CVD as shown by  FIG. 13 . As mentioned previously above, the CVD Ti layer  160  provides a low resistance periphery contact, which due to the process flow illustrated in  FIGS. 9-12 , does not coming into contact with the poly plug  138  in the memory cell array area  102 , thus preventing voiding. An adhesion/barrier layer  202  formed from a suitable material such as titanium nitride is then deposited by CVD or other suitable deposition process. This deposition is then followed by a conductive layer  204  formed from a suitable conductive material such as tungsten or other metal to fill the contact opening  154  as illustrated by  FIG. 14 . The nitride capping layer  174  is then deposited and layers  174 ,  204 ,  202 ,  160 ,  200 ,  170  are etched and patterned so as to form contacts  206 ,  208  having a top portion situated on the second insulating layer  150  as also shown by  FIG. 14 . The contacts  206 ,  208  may be of any suitable size and shape so as to provide a low resistance vertical path to the active areas of the memory cell array and peripheral circuitry areas  102  and  104 , respectively.  
         [0046]     In accordance with the present invention the contacts are formed after the formation of the capacitors. In particular, the process of forming the contacts begins after the completion of all high temperature processing steps utilized in wafer fabrication and after any other temperature changes that affect the metal layers provided in the contact formation process. In one embodiment, the process begins after the heat cycles used for cell poly activation and capacitor formation. The contacts may be formed prior to forming upper cell plate contacts to the capacitor of the memory device but subsequent to high temperature processing treatment for the capacitor. Furthermore, the present invention is not limited to the illustrated layers. Any suitable number and/or arrangement of conductive and insulating layers may be used without departing from the spirit of the invention.  
         [0047]     The above description and drawings are only to be considered illustrative of exemplary embodiments, which achieve the features and advantages of the present invention. Modification and substitutions to specific process conditions and structures can be made without departing from the spirit and scope of the present invention. Accordingly, the invention is not to be considered as being limited by the foregoing description and drawings, but is only limited by the scope of the appended claims.