Abstract:
A charge multiplication amplifier device comprises a series arrangement of a first separation barrier facility, a temporary storage well for charge carriers, a second charge transfer barrier facility, an impact ionization facility that is operative through electric field strength effective on mobile charge carriers, and a charge collection well for receiving charge carriers so multiplied. 
     Advantageously, the device comprises a charge collection and transfer facility ( 32 ) that is geometrically disposed next to the impact ionization facility ( 31 ) whereas impact ionization facility is controlled at a substantially static electric potential (DC 1,  DC 2 ) for controlling the electric field strength. 
     Advantageously, another embodiment of this device comprises charge collection and transfer facilities ( 41, 42 ) implemented as two (or more) independently clocked signals Φ 1, Φ2  that require nearly two times less swing to achieve same effect.

Description:
BACKGROUND OF THE INVENTION 
   The invention relates to a semiconductor charge multiplication amplifier device stage that comprises a series arrangement of a plurality of clock electrodes ( 81 , 82 ) on top of a semiconductor body for transporting through the semiconductor body packages of charge carriers from an image sensor section towards an output section, the device further comprising an impact ionization facility for by means of applying an electric field strength multiplying the charge carriers during their transport from the image section to the output section, 
   Prior art, as represented by U.S. Pat. No. 5,337,340 to Jaroslav Hynecek and assigned to Texas Instruments of Dallas, Tex., has recognized advantageous properties of charge multiplication devices which are operative through ionizing field strengths, or colloquially called “avalanche devices” that are especially, but not exclusively, intended for use in image sensor devices based on CCD technology. This technology allows charge signal amplification before detection in a CCD readout node, for so almost completely eliminating any noise that could be associated with an electronic on-chip pre-amplifier. For the case of CCD imagers, this latter aspect fortunately allows application at extremely low input light intensities. 
   However, various drawbacks are associated to the prior art technology. Firstly, the technology requires a high frequency clock source for controlling various voltages at precisely monitored and tightly controlled voltage levels for ensuring both high and also time-uniform amplification factors. Secondly, and even more pertinent, the recited prior art is deficient in providing a linear amplification, because the charge multiplication in an output register strongly depends on the effective potential difference under adjacent gates in a multiplication stage. This difference in potential is in particular modulated by the accumulated charge packet itself, and therefore, the amount of modulation depends on the amount of accumulation. 
   SUMMARY TO THE INVENTION 
   In consequence, amongst other things, it is an object of the present invention to isolate the amplification to a large degree from dynamic effects by separating the amplification proper from the gating and switch-over and storage aspects of the device. 
   Now therefore, according to one of its aspects, the invention is characterized in that it comprises a charge-biasing facility below which as viewed in projection the impact ionization facility is formed in the semiconductor body, which is positioned as viewed in projection between two neighboring clock electrodes and which is arranged for being driven at a first substantially static electric potential (DC 2 ) for controlling the electric field strength in the impact ionization facility. Especially, the static control of the output side of the amplification allows for mitigating the above modulating effects. 
   Advantageously, the impact ionization facility is arranged for being driven at a second substantially static electric potential (DC 1 ) for collectively with said first substantially static electric potential (DC 2 ) controlling the electric field strength in the impact ionization facility. Now, the difference between two static voltages will completely and precisely control the electric field strength in the impact ionization region. 
   Advantageously, an electrode for applying said first substantially static electric potential (DC 2 ) is followed by at least one output electrode that is arranged for being driven by at least one first dynamic electric potential ( 30 ,  32 ) for removing charge carriers away from said impact ionization facility. This raises the operational stability of the device still further by resorting to stable and straightforward DC potentials. 
   Advantageously, such device stage is arranged in a multi-stage amplification facility, wherein successive impact ionization facilities are separated by a sequence of at least a first and a second pulsed control electrode, that are driven by a first and a second dynamic partial electric potential, respectively, wherein said first and second partial potentials are overlapping for collectively bringing charge carriers from the first static electric potential (DC 2 ) of a preceding stage to the second static electric potential (DC 1 ) of a next succeeding stage. Combined with earlier advantageous features, this arrangement will diminish the necessary amplitudes of the pulsed control voltages. 
   Further advantageous aspects of the invention are recited in dependent Claims. 

   
     BRIEF DESCRIPTION OF THE DRAWING 
     These and further features, aspects and advantages of the invention will be discussed more in detail hereinafter with reference to the disclosure of preferred embodiments of the invention, and in particular with reference to the appended Figures that illustrate: 
       FIG. 1 , a comprehensive cross-sectional view of a prior art device with associated controls; 
       FIG. 2 , a timing diagram for charge multiplication operation of  FIG. 1 ; 
       FIG. 2   a , an overall schematic of an image intensifier device; 
       FIG. 3   a , a view of various controls used for a first embodiment of the present invention; 
       FIGS. 3   b - 3   d , various time-sequential voltage profiles in the device of  FIG. 3   a;    
       FIG. 3   e , showing timing diagram with overlapping clock signals Φ 1 , Φ 2 ; 
       FIG. 4   a , a view of various controls used for a second embodiment of the present invention; 
       FIG. 4   b , combined time-sequential voltage profiles in the device of  FIG. 4   a    
       FIG. 4   c , showing timing diagram with time- and voltage-overlapping clock signals Φ 1 , Φ 2  with different DC bias. 
   

   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
   First, for better understanding of the invention, a device according to the prior art will be briefly presented. In this respect,  FIG. 1  illustrates a comprehensive cross-sectional view  50  of such prior art device together with associated controls. First, a solid-state circuitry representation is shown at the top of the Figure. As shown, a repetitive pattern of electrodes  52  through  58  is present from left to right, each electrode of a group of four adjacent electrodes having its own clock pulse sequence numbered from Φ 1  to Φ 4 . As shown, the electrodes are disposed on a silicon gate oxide layer  60  that itself sits on p-type silicon substrate  62 . For brevity, driving electronics and input/output facilities have been omitted. The present invention lends itself to various alternative implementations such as n-type silicon, which alternatives will furthermore not be specifically discussed for brevity. 
   As furthermore shown, a potential curve for the channel from left to right has been shown at the bottom of the picture, the charge carrier electrons traveling from left to right. Only a single amplification stage has been shown, and furthermore, with voltage levels being represented in an inverse manner. First, item  64  represents a pixel separation barrier under the electrode  52 , that provides separation between adjacent pixel charges. Item  66  is a temporary storage well for containing the charge carriers, in particular electrons that have been propagated from a previous stage. Note that charge carriers are shown as small circles with negative (−) and positive (+) charges, respectively. Item  68  is a charge transfer barrier that keeps the contents of storage well  66  guarded as long as its barrier potential is sufficient. With the impact ionizing field  70  operative, charge carriers that surmount barrier  68  will be accelerated and collectively result in amplification by impact ionization. Subsequently the amplified charge will be kept contained in charge collection well  72  under the electrode  58 . 
   Generally, the amplification factor that is implemented for a single step or stage is quite low, such as in the range of a few percent or even much lower. A succession of many such steps may produce a much higher amplification factor, such as in the range of 100 or 1000. Furthermore, the relatively few charges of opposing sign (+) will travel back the slope  70  upward but will get quickly trapped in the semiconductor structure of the device. This removal feature will furthermore keep noise levels low. 
     FIG. 2  illustrates a timing diagram for charge multiplication operation of  FIG. 1 . Time runs from left to right and as shown, electrodes  54 ,  56  and  58  are cyclically pulsed. Electrode  56  gets a constant voltage Φ 3  applied. A falling potential Φ 2  will inject stored charge carriers over the transfer barrier  68  into the high field region  70  as indicated by the arrows. Thereupon, potential Φ 1  is driven high and Φ 4  is driven low, followed by making  54  (Φ 2 ) high and  52  (Φ 1 ) back low again. It should be clear that the potential difference between barrier  68  and well  72  will influence the amplification factor. Experience has shown that the amplification is roughly exponential in the voltage difference, amplification factors running over several orders of magnitude. Note that applicable voltage differences can go up to 20-30 volts, and that perfect voltage steps are extremely difficult to achieve. 
     FIG. 2   a  illustrates an overall schematic of an image sensor device. First, block  80  symbolizes the two-dimensional image that can be of any applicable origin, but a prime example are medical images. Through applicable pickup elements not specifically shown, the pixel-associated charges are stored in storage matrix facility  82 . Through line wise addressing of the storage matrix  82 , a row of pixels is transferred in parallel to serial shift register  84 . Thereupon, linear shifting of the pixels through shift register  84  will successively present their charges to avalanche amplifier arrangement  86  that comprises a succession of stages. The output of the amplifier feeds processing facility  88  for further usage. Control facility  90  as indicated by various arrows, produces row selection for matrix  82 , clocking for shift register  84  and amplifier  86 , and overall control for processing facility  88  and other elements that need control. 
     FIG. 3   a  illustrates a view of various controls used for a first device of the present invention. A principal difference with regards to  FIG. 1  is the providing of two DC electrodes DC 1  ( 151 ) and DC 2  ( 152 ) for each stage of the amplification chain. As shown in  FIG. 3   b  by means of the dashed line, the amplification is controlled exclusively by the high voltage difference between the two direct-current electrodes at either side of the steep slope. It has been found that the amplification factor, by means of the DC voltage difference, is now much easier to control in a reliable and temporally uniform manner. The additionally required space for these electrodes is considered negligible, especially, when the amplification is executed within a single serial arrangement such as amplifier  86  in  FIG. 2   a.    
     FIGS. 3   b - 3   d  illustrate various time-sequential voltage profiles in the device of  FIG. 3   a , with timing diagrams for signals Φ 1 , Φ 2  being shown in  FIG. 3   e . In  FIG. 3   b , the charge carriers are contained through Φ 1  ( 31 ) at location  22  before the barrier at  26 . 
   In  FIG. 3   c , Φ 1  is pulsed somewhat below voltage at DC 1 , so that charge is injected over barrier  26 . The differences between voltages at locations  27 / 28 / 26  are now too small to cause any measurable amplification. The two voltages ( 27 ,  28 ) induced by Φ 1  differ by a relatively small step, that can be implemented by various technological steps, such as through different thicknesses of the Silicon oxide layer, by giving one of the electrodes somewhat additional p-dope, or rather introducing some n-dope in the other electrode. Persons skilled in the art will recognize the relevance of these steps. The combination of the small voltage steps ( 27 ,  28 ,  26 ) will propel the electrons from well  22  towards the accelerating voltage slope  31 , for so effecting the amplification. 
   The difference between the low pulse level at electrode  81  and the voltage at DC 1  ( 151 ) is too small to cause any amplification. The same applies to the two small steps upward from level DC 2  ( 52 ) to pulsed levels at Φ 2  ( 82 ) and channel potentials  30  and  32 , respectively. The latter two will quickly remove any electrons (either primary or amplification results) away from the acceleration region  29 ,  31  towards charge collection well  32 .  FIG. 3   d  replicates  FIG. 3   c , wherein the amplified charge has been fully propelled to the next amplifier stage. Thereafter, the voltage profile is once more returned to the one shown in  FIG. 3   b.    
   As shown in  FIG. 3   a - 3   d , between successive clock pulse electrodes ( 81 ,  82 ,  81 , etcetera) a pair of avalanche electrodes ( 151 ,  152 ) has been provided for so realizing a two-phase organization. Naturally an embodiment in a four-phase CCD is feasible, an advantage of the two-phase configuration as shown being the small voltage step between DC 2  and clock level  30 . This will provide additional stability to the avalanching, because this step will pull charge carriers away from the transition immediately upon their arrival. A similar small voltage step exists between  28  and  26  for pushing charge carriers towards the ionizing field region. 
   Advantageous as compared to prior art, neither voltage Φ 1  nor Φ 2  participate in the amplification process; therefore, their temporal variations or instability have no effect on device performance. 
   Now, the arrangement of  FIGS. 3   a - d  is the preferred embodiment of the invention. However, it may be advantageous in certain applications to omit certain of the above features. In fact, the maintaining of voltage DC 2  ( 29 ) at its correct value is considered the prime rationale of the invention for maintaining the amplification factor. Further refinements are then the further providing of an essentially DC voltage at DC 1   26 , the stepping of the voltage in one or in two steps ( 29 ,  30 ) to the charge collection well at  32 , and the stepping of the voltage in one or in two steps ( 27 ,  28 ) towards the impact ionization facility  31 . 
     FIG. 3   e  shows a timing diagram with overlapping clock signals Φ 1  and Φ 2 . Note as visible in the figure, that for both traces the higher level is kept for longer time than the lower level of the other trace at the same instant. 
     FIG. 4   a  illustrates a view of various controls used for a second embodiment of the present invention. Here, each avalanche pair of DC 1 /DC 2  electrodes is separated by a sequence of two clocked electrodes Φ 1 ( 41 )/Φ 2 ( 42 ) that combine in the way of a roller-coaster: the potential is lowered in two successive steps, so that the swing of each individual signal (both Φ 1  and Φ 2 ) need only be approximately half of the original one of  FIGS. 3   b, c,  for a given acceleration voltage difference between adjacent DC 1 , DC 2  electrodes. This design facilitates the need of extremely high clock voltages. By itself, the serialization of the embodiment can be augmented to three or more electrodes (such as according to Φ 41 /Φ 42 /Φ 41 , et cetera, the next stage then starting with the correct alternating electrode). Again, the embodiment shown pertains to a two-phase CCD, although a four-phase CCD would be feasible in principle. 
     FIG. 4   b  illustrates combined time-sequential voltage profiles in the device of  FIG. 4   a . Next to the dashed avalanching step, the two phases of Φ 1 ( 41 )/Φ 2 ( 42 ) are clear in their mutual alternating. First, level  52  is driven high to create a temporary storage well for the amplified electrons from level  50 ; next, level  54  is lowered to propel the electrons to level  50  across barrier  56  and execute the amplification. 
     FIG. 4   c  shows a time diagram with time- and voltage-overlapping clock signals Φ 1 , Φ 2 , each with a respective different DC bias, as shown by the dashed traces, as being applicable in the arrangement discussed hereabove. Apart from the bias,  FIGS. 3   e  and  4   c  follow quite similar traces. 
   A few further comments are due. First, internal avalanching is feasible for both Frame Transfer FT and Interline IL types CCD image sensors, or even for mixed type CCD&#39;s. In principle, the approach of the present invention would be applicable to CMOS, be it that at present the required voltages cannot yet been realized. 
   Second, in theory, avalanche multiplication can be done internally in the sensor (item  82  in  FIG. 2   a ), but for practical reasons, generally only an extra (linear) CCD register will apply. 
   The multiplication starts with electrons as charge carriers, which is advantageous for effecting a low noise figure. The charge carrying holes will almost immediately vanish into the semiconductor structure, which feature will keep noise still lower. Advantageously, although by no means mandatory, the multiplication is effected in a series of small steps each in their own electronic stage, as opposed to using a single large avalanche. The number of stages is usually found as a trade-off. 
   A few supplemental points are as follows. Due to the physical separation of temporary storage well from the avalanche field, channel potentials are not modulated by the charge packets, and linear amplification is possible. Exact value of the clock swing does not affect multiplication factors as long as appropriate charge transfer conditions are provided, which simplifies control electronics design. 
   Now, the present invention has hereabove been disclosed with reference to preferred embodiments thereof. Persons skilled in the art will recognize that numerous modifications and changes may be made thereto without exceeding the scope of the appended claims. In consequence, the embodiments should be considered as being illustrative, and no restrictions should be construed from those embodiments, other than as have been recited in the Claims.