Abstract:
A gate modulation circuit is provided. A comparator compares a triangular wave voltage of a capacitor with a second reference voltage. If the triangular wave voltage of the capacitor exceeds the second reference voltage, a conduction path is turned off. A comparator controls desired discharge to a capacitor through a discharge resistor. Based on the discharge, power voltage (high level power voltage of the scanning driver) provided to the scanning driver is modulated, and outputted from the gate modulation circuit to the scanning driver as high level power voltage of the scanning driver.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This present application is a continuation application of and claims priority from U.S. patent application Ser. No. 11/939,591, filed Nov. 3, 2007, the content of which is hereby incorporated by reference in its entirety. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The invention relates generally to a liquid crystal display, and more particularly, to a liquid crystal display for reducing image mura. 
         [0004]    2. Description of the Related Art 
         [0005]    A liquid crystal display (LCD) is a high-resolution display with features of being thin, lightweight, and having low-voltage and low-power consumption. Sizes of LCDs, as broadly used, range from small-sized panels for mobile phones and digital cameras to over 40-inch large-sized panels for TVs. 
         [0006]    An LCD operates by applying a voltage across liquid crystal material, sandwiched between two (i.e., a pair of) substrates with at least one transparent substrate, which changes the direction of liquid crystal orientation to control flux of light. Transparent electrical conduction films are formed on each pixel sandwiched between the two substrates for constructing a liquid crystal panel (i.e., between a pixel electrode arranged on a thin film transistor side substrate module and a counter electrode arranged on a counter electrode side substrate module). Therethrough, voltage is selectively applied to determine whether light of a specific pixel is transmitted or not. 
         [0007]      FIG. 1  illustrates an equivalent circuit of a pixel of a conventional liquid crystal panel. As shown in  FIG. 1 , a thin film transistor (TFT)  13 , as a switching component, and a storage capacitor  14  are formed on the intersection of a matrix respectively arranged by a scan line  11  and a data line  12  along X-axis and Y-axis on the substrate, wherein the storage capacitor  14  is formed to allow charging of an initial signal after inputting the signal to a pixel and before inputting a following signal. 
         [0008]    Meanwhile, the drain electrode of the TFT  13  is coupled to one of the pixel electrodes, the source electrode is coupled to the data line  12 , and the gate electrode is connect to the scan line  11 . Also, an electrode (storage capacitor electrode) of a storage capacitor  14  installed on the same substrate with the TFT  13  is coupled to the drain electrode of the TFT  13 . In addition, another electrode of the pixel is a common electrode connected to a common voltage V COM  formed on an opposing substrate. 
         [0009]    As shown in  FIG. 1 , C lc  illustrates an equivalent capacitor of a liquid crystal cell, C gd  illustrates a parasitic capacitor across the drain and the gate of the TFT  13 , and C s  illustrates a storage capacitor. C s  is connected in parallel to the liquid crystal capacitor C lc  formed by liquid crystal material, and is utilized to be the load of the TFT  13 . A terminal of C s  is connected to the drain/source of the TFT  13  and the other terminal of C s  is connected to the scan line or the voltage V COM . The other electrode of the storage capacitor  14  shown in  FIG. 1  is coupled to a part of the display electrode (an auxiliary voltage V S  as shown in  FIG. 1 . 
         [0010]    If the scan line is at a high level (V GH ), the data voltage is stored in the pixel capacitor C lc  according to the voltage provided by the data line. When the level of the scanning signal transitions from a high level (V GH ) to a low level (V GL ), the drain voltage of the TFT  13  generates a level shift, which is called feed-through voltage, wherein the level shift (ΔV d ) is represented by the following formula: 
         [0000]      Δ V   d   =C   gd /( C   gd   +C   lc   +C   s )×( V   GH   −V   GL )
 
         [0011]      FIG. 2  illustrates a level shift of a drain voltage V d  of a TFT according a conventional driving method. As shown in  FIG. 2 , in the same scan line (the j th  scan line), a gate voltage (V g ) and a drain voltage (V d ) of the TFT is corresponding to the pixels on the first and the n th  location near the input of the scanning signal. 
         [0012]    When the voltage level of the scanning signal drops rapidly, the falling inclination edge on each scan line of the TFT is dependent on where it is located on the scan line due to the delay effect. The TFT turns off after the scan line voltage is below a threshold voltage, thereby increasing the level shift (ΔV d  (1, j) as shown in  FIG. 2  near the input on the scan line, and decreasing the level shift (ΔV d  (n, j) as shown in  FIG. 2  near the end on the scan line. That is, the level shift ΔV d  of the drain voltage of the TFT on the same scan line becomes inconsistent and causes image mura such as flickers and residues, thus lowering display image quality for large liquid crystal panels. 
         [0013]    As a result, various researches, e.g., Patent Reference 1 (Japan Pat. Appl. Kokai Publication No. 6-110025) and Patent Reference 2 (Japan Pat. Appl. Kokoku Publication No. 3406508), were directed to a method of changing the falling edge of the scanning signal as an inclination (ramp waveform) to reduce the aforementioned image mura. 
         [0014]    For controlling the falling edge of the scanning signal as an inclination, the conventional and broadly-used timing integrated circuits and a scan line driver need to be modified, and thus it raises a problem of developing new timing integrated circuits and scan line drivers. 
       BRIEF SUMMARY OF THE INVENTION 
       [0015]    Accordingly, the present invention provides a gate signal modulation circuit for eliminating or decreasing display image mura such as flickers and residues without specially modifying structures of a timing integrated circuit and a scanning driver installed in a liquid crystal display. 
         [0016]    In order to solve the above described problems, the present invention provides a liquid crystal display, comprising a plurality of parallel data lines, a plurality of scan lines perpendicular to a plurality of data lines, pixels installed at each intersection of the plurality of data lines and the plurality of scan lines, thin film transistors (TFTs) corresponding to each pixel, a data line driving circuit for providing a data line signal, and a scan line driving circuit for providing a scan line. The liquid crystal display further comprises a gate signal modulation circuit. The gate signal modulation circuit comprises a first capacitor coupled to a constant current circuit, a voltage generation circuit for discharging a voltage of the first capacitor to synchronize with the timing scanning signal and generating a triangle wave voltage, a second capacitor coupled to a high level power of the scan line driving circuit, and a discharging circuit to stop providing the high level power voltage of the scan line driving circuit according to a result of comparing the triangle wave voltage and a basis voltage and discharge the voltage of the second capacitor to modulate a falling edge waveform of the scan line timing signal being outputted to the scan line driving circuit. 
         [0017]    A gate signal modulation circuit according to the present invention comprises a power voltage for supplying operating power to the circuit, a basis voltage for supplying a basis voltage to the circuit, a constant current generator for generating a constant current, a first capacitor coupled to the constant current generator for generating a charging voltage, a triangle wave generator with a control node coupled to a timing signal for controlling a falling edge and a rising edge of a gate signal, which generate a triangle wave voltage for the first capacitor voltage according to the timing signal, a modulation controller for outputting a modulated control signal based on a comparison result between the triangle wave voltage and the basis voltage, and a modulated voltage generator comprising a second capacitor coupled to the power voltage, wherein the modulated voltage generator determines whether the second capacitor is charged by the source or discharged according to the modulated control signal and generates a modulated voltage. 
         [0018]    In order to easily understand the purposes, features, and advantages of the present invention, a detailed description is given in the following embodiments with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0019]    The present invention can be more fully understood by reading the subsequent detailed description and examples with references to the accompanying drawings, where: 
           [0020]      FIG. 1  illustrates an equivalent circuit of a pixel of a conventional liquid crystal display panel; 
           [0021]      FIG. 2  illustrates a level shift of a drain voltage of a TFT according to a conventional driving method; 
           [0022]      FIG. 3  illustrates a liquid crystal display according to an embodiment of the present invention; 
           [0023]      FIG. 4  illustrates a gate signal modulation circuit of a liquid crystal display according to another embodiment of the present invention; and 
           [0024]      FIG. 5  illustrates timing waveforms of GOE signal (A), charging voltage of a capacitor C 2  (B), output of a comparator IC 1 A (C), output of a comparator IC 1 B (D), modulation of power voltage provided to a scan line driver (E), and scan lines of the scan line driver ((F)˜(I)). 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0025]      FIG. 3  illustrates a schematic diagram of a liquid crystal display according to the present invention. A TFT  104  as a switch component and a storage capacitor (not shown) are installed at each intersection of a data line  102  and a scan line  103  arranged in an n row by n column matrix on a substrate  101  of a liquid crystal display  100 , wherein the drain of the TFT  104  is coupled to a pixel electrode  105 , the source of the TFT  104  is coupled to the data line  102 , and the gate of the TFT  104  is coupled to the scan line  103 . 
         [0026]    An image data circuit  108  outputs an image signal to a data driving circuit (a data driver)  106  and a time-divided timing control circuit  109  outputs a timing signal to a scan line driving circuit (a scan line driver)  107  through a gate signal modulation circuit  110 . 
         [0027]      FIG. 4  illustrates a gate signal modulation circuit  110  of a liquid crystal display according to another embodiment of the present invention. In  FIG. 4 , a block  111  represents a constant current circuit (or a constant current generator) of the gate signal modulation circuit  110  and a capacitor C 2 . A block  112  represents a modulation kernel circuit for controlling a gate signal, which comprising a voltage generation circuit  112   a  (in the embodiment, for example, a triangle wave generation circuit composed of a transistor Q 2  and a resistor R 3 ), a discharging circuit (not shown) composed of a modulation controller  112   b  and a modulated voltage generator  112   c . According to the embodiment, the discharging circuit at least comprises comparators IC 1 A and IC 1 B, a transistor Q 3 , resistors R 7 ˜R 9 , and a capacitor C 5 . 
         [0028]    The constant current circuit  111  comprises a complex PNP bipolar junction transistor Q 1 B and a complex NPN bipolar junction transistor Q 1 A with an emitter coupled to the ground. The base of the NPN bipolar junction transistor Q 1 A is supplied by a basis voltage VREF, wherein the basis voltage VREF is outputted to the base of the PNP bipolar junction transistor Q 1 B through the emitter of the NPN bipolar junction transistor Q 1 A. 
         [0029]    At this time, the emitter voltage of the NPN bipolar junction transistor Q 1 A is lower than the basis voltage VREF by a base-emitter voltage VBE A  of the NPN bipolar junction transistor Q 1 A (=VRFE−VBE A ), wherein the voltage VRFE−VBE A  is applied to the base of the PNP bipolar junction transistor Q 1 B coupled to the emitter of the NPN bipolar junction transistor Q 1 A. 
         [0030]    The emitter voltage Ve of the PNP bipolar junction transistor Q 1 B is higher than the base voltage of the PNP bipolar junction transistor Q 1 B by a base-emitter voltage VBE B  of the PNP bipolar junction transistor Q 1 B (=VRFE−VBE A +VBE B ). 
         [0031]    Here, the base-emitter voltage of the complex NPN bipolar junction transistor Q 1 A is almost the same with that of the PNP bipolar junction transistor Q 1 B. Consequently, the emitter voltage Ve of the PNP bipolar junction transistor Q 1 B almost equal to the basis voltage VREF and is a voltage independent of the base-emitter voltage VBE of the bipolar junction transistor. Therefore, a stable constant voltage independent of temperature variation is implemented. 
         [0032]    The emitter voltage Ve of the PNP bipolar junction transistor Q 1 B is coupled to a digital power VDD through a transistor R 1 , and a capacitor C 2  coupled to the collector of the PNP bipolar junction transistor Q 1 B flows a constant current I=(VDD−VREF)/R 1 . 
         [0033]    The collector of the PNP bipolar junction transistor Q 1 B is coupled to the emitter of the transistor Q 2  of a triangle generation circuit  112 . A gate output enable signal GOE is inputted to the base of the transistor Q 2  through a resistor R 3 , wherein the gate output enable signal GOE is a timing signal for controlling a rising edge and a falling edge of the gate signal. 
         [0034]    The collector voltage Vc of the PNP bipolar junction transistor Q 1 B is determined by the formula Vc=I×t/C 2 , and the charge stored in the capacitor C 2  is correlated with the constant current (I=(VDD−VREF)/R 1 ). 
         [0035]    The charge stored in the capacitor C 2  (charging voltage) is discharged through the transistor Q 2 . The discharging through the transistor Q 2  is performed according to the GOE signal to control the rising edge and the falling edge of the gate signal (timing signal). 
         [0036]    Consequently, as shown in a timing diagram of  FIG. 5 , the charging voltage waveform of the capacitor C 2  synchronously varying with the GOE signal (as shown in  FIG. 5(A) ) and the charge voltage of C 2  is a triangle wave that rises at a predetermined inclination angle from the falling edge of the GOE signal, and drops rapidly at the rising edge of the GOE signal (as shown in  FIG. 5(B) ). 
         [0037]    According to one embodiment of the present invention, the rising edge of the GOE signal is synchronous with the falling edge of the output of the scan line driver  107 , and the falling edge of the GOE signal is synchronous with the rising edge of output of the scan line driver  107 , so as to control the output of the scan line driver. Therefore, the charging voltage of the capacitor C 2  rises in the predetermined inclination angle synchronously with the rising edge of the output of the scan line driver, and falls synchronously with the falling edge of the output of the scan line driver. 
         [0038]    The charging voltage of the capacitor C 2  is respectively outputted to a non-inverter node (+) of a comparator IC 1 A and an inverter node (−) of a comparator IC 1 B through a resistor R 4 . The inverter node (−) of the comparator IC 1 A and the non-inverter node (+) of the comparator IC 1 B are coupled to a second basis voltage point (VREF 2 =(R 6 ×VREF)/(R 5 +R 6 )), wherein the second basis voltage is determined by a resistance ratio of two resistors (R 5 , R 6 ) which are serially connected between the basis voltage VREF and the ground. 
         [0039]    The comparator IC 1 A compares the voltage of the capacitor C 2  and the second basis voltage VREF 2 . The turn-on path (referring to  FIG. 5(C) ) of the transistor Q 3  is turned off when the voltage of the capacitor C 2  exceeds the second basis voltage VERF 2 . 
         [0040]    Moreover, the comparator IC 1 B outputs a logic “0” when the comparator IC 1 A outputs a logic “1” and outputs a logic “1” when the comparator IC 1 A outputs a logic “0” (referring to  FIG. 5(D) ). When the voltage of the capacitor C 2  exceeds the second basis voltage VREF 2 , the voltage of a capacitor C 5  is discharged through a discharging resistor R 9 . According to the discharging operation, the power voltage (a high level power voltage VGH of the scan line driver) provided for the scan line driver  107  is modulated and outputted from the gate signal modulation circuit  110  to the scan line driving circuit  107  as the high level power voltage of the scan line driving circuit. 
         [0041]    Specifically, a comparator utilizes an open collector output. The comparator utilizing the open collector output can reduce essential transistors (such as a transistor for turning on/off the Q 3  and a transistor for discharging the capacitor C 5 ). 
         [0042]    When the comparator IC 1 A outputs a logic “1” (i.e., an internal transistor is turned off), no current flows through a resistor R 8  and the transistor Q 3  is off to cut off a conduction path. In addition, when the comparator IC 1 A outputs a logic “0” (i.e., the internal transistor is turned on), a current flows through the resistor R 8  and the transistor Q 3  is turned on to conduct the path. 
         [0043]    Moreover, the operation of the comparator IC 1 B and the comparator IC 1 A is opposite to each other. When the comparator IC 1 B outputs a logic “1” (the internal transistor is off), the voltage of the capacitor C 5  is maintained due to no current flowing through the path from the capacitor C 5  to the resistor R 9 . When the comparator IC 1 B outputs a logic “0” (the internal transistor is on), the charge of the charged capacitor C 5  is discharged through the resistor R 9 . Therefore, the discharging curve is determined by a time constant of the capacitor C 5  and the resistor R 9 . 
         [0044]    According to one embodiment of the present invention, a modulated waveform of power voltage provided to the scan line driver begins to incline before the output of the scan line driver  107  falls, and stops inclining during falling of the output of the scan line driver  107  (referring to  FIG. 5(E) ). 
         [0045]    The period of providing the power voltage to the scan line driver is determined by the second basis voltage VREF 2  and the inclination angle of the triangle wave from the charging voltage of the capacitor C 2 . Additionally, the inclination angle of the modulated waveform from the power voltage of the scan line driver is determined by the capacitor C 5  and the discharging resistor R 9 . 
         [0046]    Further, the high level power voltage of the gate signal modulation circuit  110  coupled to the scan line driver  107  sequentially outputs scan line signals Gate_out(k)˜(k+3) with inclination at the falling edge from the gate of the scan line driver, referring to FIG.  5 (F)˜(I), through the k th  scan line, the k+1 th  scan line, the k+2 th  scan line, and the k+3 th  scan line (below skipped). 
         [0047]    As shown in  FIG. 4 , at the output side of the gate signal modulation circuit  110 , a diode D 1  is installed between the high level power VGH of the scan line driver and the digital power VDD. When the output voltage of the gate signal modulation circuit is lower than the digital power VDD, short circuit of the scan line driver  107  may occur. Therefore, the diode D 1  is installed to avoid the above problem, thereby improving reliability of the scan line driver  107 . 
         [0048]    As described above, the present invention provides a liquid crystal display which can easily modulate the falling edge of the scan line signal as a ramp and reduce liquid crystal display image mura. 
         [0049]    While the present invention has been described by way of examples and in terms of preferred embodiment, it is to be understood that the present invention is not limited to thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.