Abstract:
Embodiments of the present invention provide a sample and hold amplifier that provides a preamplifier with a multi-stage zeroing architecture. The multi-stage architecture reduces effects of parasitic capacitance exponentially over prior attempts, which yields increased accuracy.

Description:
RELATED APPLICATION 
       [0001]    This application claims benefit of priority from U.S. provisional application “ADC Preamplifier and the Multistage Auto-zero Technique,” Ser. No. 61/454,828, filed Mar. 21, 2011, the disclosure of which is incorporated herein by reference in its entirety. 
     
    
     BACKGROUND 
       [0002]    The present invention relates to sample and hold amplifiers (SHAs) and, in particular, to reducing voltage offset errors that can be induced by pre-amplifiers that drive SHAs. 
         [0003]    Sample and hold amplifiers, as their name implies, are electronic devices that sample a time-varying voltage and amplify it with predetermined gain (sometimes, unity gain). Switched capacitor amplifiers, switched capacitor integrators and switched capacitor filters are examples of circuit systems that use SHAs at their input. An input voltage is sampled by the SHA and held for a predetermined time so that it may be processed by subsequent circuit stages in the system. A pre-amplifier is often used at the input of a SHA. 
         [0004]    SHAs, therefore, include a switch array that connects internal capacitors to an input voltage during a sampling operation. The switch array disconnects the capacitors from the input signal and connects the capacitors to other reference voltages during other phases of operation. The switch array is made up of a variety of transistor switches that are driven to be conductive and non-conductive as appropriate during the various phases of operation. Although transistors ideally should conduct no current when driven to be non-conductive, current leakage can occur at times, particularly when the SHA is operating at high temperature (in excess of 120° C.). The leakage problem manifests itself as a current drawn from the input source. If the input voltage source cannot supply the current that SHA demands, a pre-amplifier is often placed at the input of the SHA. Use of preamplifiers, however, induces errors of their own, discussed below in the context of an analog to digital converter. 
         [0005]    Analog to digital converters (ADCs) are known circuits that sample an analog voltage within a predetermined voltage range and generate a digital code representing the voltage&#39;s magnitude. A variety of ADC architectures are available to circuit designers, including the successive approximation register (SAR) ADC  100 , shown in  FIG. 1  in block diagram form. 
         [0006]    The SAR ADC  100  typically includes a sample &amp; hold digital to analog converter (“SHA/DAC”)  110 , a comparator  120 , and a decode logic  130 . The SHA/DAC  110  may sample the analog input signal (V IN ) and generate test voltages (V TEST ) during bit trials. The SHA/DAC  110  may include a capacitor array that includes a plurality of binary weighted capacitors (C to 2 N-1 C) The array may include a capacitor for each of the N bit positions of the output code. Each capacitor may be coupled at a bottom plate to a three-position switch that selectively connects the plate to the input voltage V IN , to a reference voltage (V REF ) or to ground. 
         [0007]    The comparator  120  may compare the SHA/DAC&#39;s test voltage to ground or some other reference voltage. The decode logic  130  may interpret the comparator&#39;s output and generate an N bit output code. In the ADC  100  illustrated in  FIG. 1 , the SHA is integrated with a SHA/DAC  110  to generate test voltages to the comparator. The SHA/DAC  110  includes the switched capacitor array in which the above-mentioned errors can arise. 
         [0008]    The ADC may operate in two modes, a sampling mode and a bit-trial mode. During the sampling mode, bottom plates of all switchable SHA/DAC capacitors are connected to V IN , and top plates of all capacitors are connected to ground. Therefore, all switchable capacitors develop a voltage −V IN  across them (measured from top plate to bottom plate). 
         [0009]    During the bit-trial mode, the SHA/DAC  110  iteratively tests each bit position in order, starting with a most significant bit (MSB). The top plates of all capacitors are disconnected from ground and connected to the input of the comparator. Switches of any previously-tested bit position are set to their derived values. Bit positions deemed to be a “1” are connected to V REF , and bit positions deemed to be a “0” are connected to ground. A switch of a next bit position to be tested is connected to V REF . 
         [0010]    The comparator  120  compares the resulting voltage V TEST  to the voltage on its second input (ground). If the V TEST &lt;ground, the next bit position is determined to be a “1”. Otherwise, the next bit position is determined to be “0”. This operation repeats until all bit positions have been tested. 
         [0011]    For example, to test the MSB bit position, the switch corresponding to the 2 N-1 C capacitor is connected to V REF  and the switches of all other bit positions are connected to ground. Due to charge sharing among the capacitors, a test voltage V TEST  is developed corresponding to ½*V REF −V IN . If the comparator determines that V TEST &lt;ground, the MSB will be determined to be a “1”. Otherwise, the MSB will be determined to be a “0”. 
         [0012]    For the next iteration, the MSB switch will be set to V REF  if a “1” or to ground if a “0” and the switch of the next bit position (the 2 N-2 C capacitor) will be set to V REF . In this iteration, the SHA/DAC will develop a V TEST  voltage corresponding to ¾*V REF −V IN  if the MSB was determined to be a “1” or ¼*V REF −V IN  if the MSB was determined to be a “0”. The SHA/DAC  110  proceeds in this manner until all N bits have been tested. 
         [0013]      FIG. 2  is a circuit diagram illustrating implementation of the switched capacitor array used in a SHA. The switch is implemented as three transistors  210 - 230 , each coupled to the bottom plate of its associated capacitor C. Transistor  210  is coupled to the input voltage V IN . Transistor  220  is coupled to V REF . Transistor  230  is coupled to ground. 
         [0014]    In an ideal case, when the ADC is operating in sampling mode, transistors  220  and  230  are non-conductive, which causes the capacitor C i  to charge to input voltage V IN . In practice, however, the transistors  220 ,  230  are not perfectly non-conductive and, therefore, the capacitor C i  charges to an incorrect level. This problem can be pronounced when the system runs at high temperatures (ex., 150° C.). Thus, when the SHA/DAC  110  runs through its bit trials, it does so with an erroneous sampled voltage. 
         [0015]      FIG. 3  is a block diagram of an ADC  300  with a preamplifier. The ADC  300  may include a preamplifier  310 , a SHA/DAC  320 , a comparator  330 , and a decoder  340 . The preamplifier  310  may receive an input signal V IN  and generates an amplified signal V AMP  at a predetermined gain (which may be unity in appropriate circumstances). The SHA/DAC  320  may receive the amplified signal V AMP  and digital control signals B[N−1: 0 ] and generates test voltages V TEST  for bit trials. The comparator  340  may include inputs for the test voltages V TEST  from the SHA/DAC and for a reference voltage (typically, ground). The decoder  340  may interpret output from the comparator  330  and build a digital code therefrom during the bit trials. 
         [0016]    At the end of operation, the ADC  300  may generate an N bit digital code comprised of bits B[N−1: 0 ]. The preamplifier  310  may amplify the input signal V IN  to a level sufficient to drive the SHA/DAC capacitors and overcome current loss through the V REF - and ground-coupled transistor switches. Preamplifiers typically generate signal artifacts of their own, including voltage offsets that may reach as high as ±3 mV in an ADC that has a least significant bit (LSB) step size of 300 μV. Moreover, the voltage offsets tend to manifest themselves randomly from device to device because they arise from manufacturing process variations. Voltage offsets also can arise from insufficient open loop gain of the amplifier. 
         [0017]    To overcome this problem, Enz proposed a preamplifier with an auto-zeroing operation. Enz, et al.,  Circuit Techniques for Reducing the Effects of Op - Amp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization , Proc. IEEE, vol. 84, no. 11, pp. 1584-1614 (November 1996). However, the Enz scheme tends to have issues with stability and settling. In high accuracy ADC applications, it is necessary to reduce contributions of voltage offsets even further than is possible in the  FIG. 3  architecture. 
         [0018]    Therefore, there is a need in the art for a preamplification scheme for a sample and hold unit that substantially reduces preamplifier voltage offsets without requiring large capacitances. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0019]      FIG. 1  is a simplified block diagram a successive approximation register (SAR) ADC. 
           [0020]      FIG. 2  is a circuit diagram of a switched capacitor array used in a SHA. 
           [0021]      FIG. 3  is a simplified block diagram of an ADC with a preamplifier. 
           [0022]      FIG. 4  illustrates an amplifier system with single stage auto-zeroing according to an embodiment of the present invention. 
           [0023]      FIG. 5(   a ) illustrates a model operation during a first phase of an amplifier system according to an embodiment of the present invention. 
           [0024]      FIG. 5(   b ) illustrates a model operation during a second phase of an amplifier system according to an embodiment of the present invention. 
           [0025]      FIG. 6  illustrates an amplifier system with dual stage auto-zeroing according to an embodiment of the present invention. 
           [0026]      FIG. 7(   a ) illustrates a model operation during a first phase of an amplifier system according to an embodiment of the present invention. 
           [0027]      FIG. 7(   b ) illustrates a model operation during a second phase of an amplifier system according to an embodiment of the present invention. 
           [0028]      FIG. 7(   c ) illustrates a model operation during a third phase of an amplifier system according to an embodiment of the present invention. 
           [0029]      FIG. 8(   a ) illustrates a timing diagram of an amplifier system according to an embodiment of the present invention. 
           [0030]      FIG. 8(   b ) illustrates a simulation result of an amplifier system according to an embodiment of the present invention. 
           [0031]      FIG. 8(   c ) illustrates a simulation result of an amplifier system according to an embodiment of the present invention. 
           [0032]      FIG. 9  illustrates an amplifier system with multiple auto-zeroing stages according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0033]    Embodiments of the present invention may provide a sample and hold amplifier system including an amplifier with a pair of input terminals and an output terminal, and an auto-zeroing stage. The auto-zeroing stage includes a capacitor coupled to an input terminal of the amplifier, and a plurality of switches. The capacitor is switchably coupled to the output terminal, and an upper and lower plate of the capacitor are switchably coupled to an input voltage terminal. 
         [0034]    Embodiments of the present invention may provide a method of capturing an input voltage. In a first phase, the method includes applying the input voltage to an amplifier to generate an output voltage and developing a voltage across a capacitor representing a difference between the input voltage and the output voltage. In a second phase, the method includes reversing orientation of the capacitor voltage and applying a combination of the input voltage and the reversed capacitor voltage to the amplifier. 
         [0035]    Embodiments of the present invention may provide an amplifier system including an amplifier with a pair of input terminals and an output terminal, and a plurality of auto-zeroing stages. Each stage includes a capacitor and a plurality of switches. Each capacitor is switchably coupled to the output terminal and switchably coupled to an input voltage terminal. 
         [0036]    Embodiments of present invention may provide an amplifier system including an amplifier with an output terminal, and a plurality of auto-zeroing stages. Each stage may include a capacitor, a first pair of switches that, when activated, couple a first capacitor terminal of the capacitor to an input of the respective stage and a second capacitor terminal to the amplifier output terminal, and a third switch that, when activated, couples the second capacitor terminal to the input of the stage. 
         [0037]    Embodiments of the present invention may provide a method of capturing an input voltage. The method includes in a first phase, in a first phase, applying the input voltage to an amplifier to generate an output voltage and developing a voltage across a capacitor of a first stage representing a difference between the input voltage and the output voltage. In successive phases, reversing orientation of the capacitor voltage of a preceding stage, applying a combination of the input voltage and the reversed capacitor voltages of all preceding stages to the amplifier, and developing a voltage across a capacitor of a next stage representing a difference between the input voltage and the output voltage. 
         [0038]      FIG. 4  illustrates a preamplifier  400  for use with an ADC according to an embodiment of the present invention. The preamplifier  400  may include an amplifier  410 , a capacitor  420 , and a plurality of switches  430 - 450 . The amplifier  410  may include a pair of input terminals and an output. The pair of input terminals may include an inverting input and a non-inverting input. The inverting input may be coupled to the amplifier&#39;s output. 
         [0039]    The capacitor  410  may have an upper plate and a lower plate separated by a dielectric. The upper plate may be coupled to the non-inverting input of the amplifier  410 . The plurality of switches  430 - 450  may include a first switch  430 , a second switch  440 , and a third switch  450 . The first switch  430  may couple an input voltage terminal (V IN ) to the upper plate of the capacitor  420 . The second switch  440  may couple the amplifier&#39;s output terminal to the lower plate of the capacitor  420 . The third switch  450  may couple the input voltage terminal V IN  of to the lower plate of the capacitor  420 . 
         [0040]    The preamplifier  400  may be manufactured as an integrated circuit. Further, the switches  430 - 450  may be embodied as transistors. 
         [0041]    The preamplifier  400  may operate in two non-overlapping phases of operation. Switches  430  and  440  may be closed during a first phase of operation and open during the second phase of operation. Switch  450  may be open during the first phase and closed during the second phase. 
         [0042]      FIGS. 5(   a ) and  5 ( b ) model operation of the preamplifier of  FIG. 4  during the two phases of operation, according to an embodiment of the present invention. As noted, the preamplifier  410  of  FIG. 4  may introduce its own voltage offset during operation and, therefore,  FIGS. 5(   a ) and  5 ( b ) illustrate the amplifier as an ideal amplifier with an associated voltage source V OFF . 
         [0043]      FIG. 5(   a ) illustrates a configuration of the preamplifier during the first phase of operation, when switches  430  and  440  are closed but switch  450  is open. During this first phase, the amplifier may generate an output of V OUT =V IN +V OFF . The capacitor, therefore, may develop a voltage of V OFF  across it because V IN  may charge the upper plate of the capacitor while V OUT , which is V IN +V OFF , may charge the lower plate of the capacitor. 
         [0044]      FIG. 5(   b ) illustrates a configuration of the preamplifier during the second phase of operation, when switch  450  is closed but switches  430  and  440  are open. During this second phase, the non-inverting input of the amplifier may receive an input voltage of (V IN −V OFF +V OFF ). The offset voltage of the amplifier then may be canceled by the offset voltage developed across the capacitor during the first phase of operation. Therefore, the output of the amplifier is very close to the input voltage (V OUT ≈V IN ), and the amplifier is working closer to its ideal characteristics. 
         [0045]    In practice, the amplifier may have a parasitic capacitance associated with it, which induces a charge sharing between the capacitor  420  of  FIG. 4  and the parasitic capacitance. Thus, the preamplifier  400  of  FIG. 4  may generate an output voltage according to: 
         [0000]    
       
         
           
             
               
                 V 
                 OUT 
               
               ≈ 
               
                 
                   V 
                   IN 
                 
                 + 
                 
                   
                     V 
                     OFF 
                   
                   * 
                   
                     
                       C 
                       P 
                     
                     
                       C 
                       + 
                       
                         C 
                         P 
                       
                     
                   
                 
               
             
             , 
           
         
       
     
         [0000]    where
 
C P  represents the parasitic capacitance of the amplifier and C represents the capacitance of the capacitor  420 .
 
         [0046]      FIG. 6  illustrates a preamplifier  600  according to another embodiment of the present invention. This amplifier design of preamplifier  600  may provide improved accuracy by reducing the parasitic effects. 
         [0047]    The preamplifier  600  may include an amplifier  610  and a pair of auto-zeroing stages. The amplifier  610  may include a pair of input terminals and an output. An inverting input of the amplifier may be coupled to amplifier&#39;s output. Each auto-zeroing stage may include a capacitor  650 . 1 ,  650 . 2  and a plurality of switches  620 . 1 , 620 . 2 - 640 . 1 ,  640 . 2 . 
         [0048]    In the first stage (stage  1 ), the first switch  620 . 1  may be coupled to an upper plate of the capacitor  650 . 1  and to an input of the stage. The second switch  630 . 1  may couple the amplifier&#39;s output terminal to the lower plate of the capacitor  650 . 1 . The third switch  640 . 1  may couple the lower plate of the capacitor  650 . 1  to an input of the first switch  630 . 1  of the first stage. 
         [0049]    In the second stage (stage  2 ), the first switch  620 . 2  may be coupled to an upper plate of the capacitor  650 . 2  and to an input of the stage. The second switch  630 . 2  may couple the amplifier&#39;s output terminal to the lower plate of the capacitor  650 . 2 . The third switch  640 . 2  may couple the lower plate of the capacitor  650 . 2  to an input of the first switch  630 . 2  of the second stage. 
         [0050]    The preamplifier  600  may be manufactured as an integrated circuit. Further, the switches may be embodied as transistors. 
         [0051]    The preamplifier  600  may operate over three phases of operation to sample the input signal and generate a mirroring output voltage with substantially reduced offset, as shown below. 
         [0052]      FIGS. 7(   a )-( c ) model operation of the preamplifier of  FIG. 6  during its operation according to an embodiment of the present invention. As noted, the amplifier  610  of  FIG. 6  may introduce its own voltage offset during operation and may have its own parasitic capacitance associated with it. Therefore,  FIGS. 7(   a )-( c ) model the amplifier as an ideal amplifier, an associated voltage source V OFF  and parasitic capacitor C P . Further, capacitance values of capacitors  650 . 1  and  650 . 2  both are taken as C. 
         [0053]      FIG. 7(   a ) illustrates a configuration of the preamplifier during the first phase of operation. During this first phase, switches  620 . 1  and  630 . 1  in stage  1  are closed but switch  640 . 1  is open. Switches  620 . 2  and  630 . 2  in stage  2  are closed but switch  640 . 2  is open. The amplifier may generate an output of V OUT =V IN +V OFF . The capacitors  650 . 1  and  650 . 2  both may develop a voltage of V OFF  across them. 
         [0054]      FIG. 7(   b ) illustrates a configuration of the preamplifier during the second phase of operation. During the second phase, switches  620 . 1  and  630 . 1  in stage  1  are open but switch  640 . 1  is closed. Switches  620 . 2  and  630 . 2  in stage  2  are closed but switch  640 . 2  is open. The amplifier may generate an output of 
         [0000]    
       
         
           
             
               V 
               OUT 
             
             = 
             
               
                 V 
                 IN 
               
               + 
               
                 
                   V 
                   OFF 
                 
                 * 
                 
                   
                     
                       C 
                       P 
                     
                     
                       C 
                       + 
                       
                         C 
                         P 
                       
                     
                   
                   . 
                 
               
             
           
         
       
     
         [0000]    The capacitor  650 . 2  in stage  2  develop a voltage of 
         [0000]    
       
         
           
             
               V 
               OFF 
             
             * 
             
               
                 C 
                 P 
               
               
                 C 
                 + 
                 
                   C 
                   P 
                 
               
             
           
         
       
     
         [0000]    across it. 
         [0055]      FIG. 7(   c ) illustrates a configuration of the preamplifier during the third phase of operation. During the third phase, switches  620 . 1  and  630 . 1  in stage  1  are open but switch  640 . 1  is closed. Switches  620 . 2  and  630 . 2  in stage  2  are open but switch  640 . 2  is closed. The amplifier may generate an output as 
         [0000]    
       
         
           
             
               
                 V 
                 OUT 
               
               = 
               
                 
                   V 
                   IN 
                 
                 + 
                 
                   
                     V 
                     OFF 
                   
                   * 
                   
                     
                       C 
                       P 
                     
                     
                       C 
                       + 
                       
                         C 
                         P 
                       
                     
                   
                   * 
                   
                     
                       C 
                       
                         P 
                          
                         
                             
                         
                          
                         1 
                       
                     
                     
                       C 
                       + 
                       
                         C 
                         
                           P 
                            
                           
                               
                           
                            
                           1 
                         
                       
                     
                   
                 
               
             
             , 
           
         
       
     
         [0000]    where 
         [0000]    
       
         
           
             
               C 
               
                 P 
                  
                 
                     
                 
                  
                 1 
               
             
             = 
             
               C 
               * 
               
                 
                   
                     C 
                     P 
                   
                   
                     C 
                     + 
                     
                       C 
                       P 
                     
                   
                 
                 . 
               
             
           
         
       
     
         [0056]    The output voltage may be approximated as: 
         [0000]    
       
         
           
             
               
                 V 
                 OUT 
               
               ≈ 
               
                 
                   V 
                   IN 
                 
                 + 
                 
                   
                     V 
                     OFF 
                   
                   * 
                   
                     
                       C 
                       P 
                     
                     
                       C 
                       + 
                       
                         C 
                         P 
                       
                     
                   
                   * 
                   
                     
                       C 
                       P 
                     
                     
                       C 
                       + 
                       
                         C 
                         P 
                       
                     
                   
                 
               
             
             = 
             
               
                 V 
                 
                   IN 
                    
                   
                       
                   
                 
               
               + 
               
                 
                   V 
                   OFF 
                 
                 * 
                 
                   
                     
                       ( 
                       
                         
                           C 
                           P 
                         
                         
                           C 
                           + 
                           
                             C 
                             P 
                           
                         
                       
                       ) 
                     
                     2 
                   
                   . 
                 
               
             
           
         
       
     
         [0057]    The design of  FIG. 6  improves accuracy of the preamplifier by mitigating the effects of parasitic capacitance. As noted above, the contribution of the offset voltage V OFF  is reduced by approximately the square of a fractional scalar 
         [0000]    
       
         
           
             
               
                 ( 
                 
                   
                     C 
                     P 
                   
                   
                     C 
                     + 
                     
                       C 
                       P 
                     
                   
                 
                 ) 
               
               2 
             
             . 
           
         
       
     
       This 
       [0058]    
       
         
           
             
               ( 
               
                 
                   C 
                   P 
                 
                 
                   C 
                   + 
                   
                     C 
                     P 
                   
                 
               
               ) 
             
             2 
           
         
       
     
         [0000]    term has a value less than one and, therefore, it&#39;s square has an even smaller value. 
         [0059]    Therefore, the dual-stage embodiment of  FIG. 6  provides improved offset mitigation over the embodiment of  FIG. 4  even when the same overall capacitance is used in each system. That is, capacitors  650 . 1 ,  650 . 2  of  FIG. 6  each are half the capacitance of capacitor  420  of  FIG. 4 . Taking C 1  (capacitor  650 . 1 )=C 2  (capacitor  650 . 2 )=½ C (capacitor  420 ) and common values of V IN  and V OFF , the voltages output from the  FIG. 4  embodiment may compare to those of the  FIG. 6  embodiment as follows: 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     OUT 
                   
                   ≈ 
                   
                     
                       V 
                       IN 
                     
                     + 
                     
                       
                         V 
                         OFF 
                       
                       * 
                       
                         
                           C 
                           P 
                         
                         
                           C 
                           + 
                           
                             C 
                             P 
                           
                         
                       
                     
                   
                 
               
               
                 
                   FIG 
                   . 
                   
                       
                   
                    
                   4 
                 
               
             
             
               
                 
                   
                     V 
                     OUT 
                   
                   ≈ 
                   
                     
                       V 
                       IN 
                     
                     + 
                     
                       
                         V 
                         OFF 
                       
                       * 
                       
                         
                           
                             ( 
                             
                               
                                 C 
                                 P 
                               
                               
                                 
                                   C 
                                   2 
                                 
                                 + 
                                 
                                   C 
                                   P 
                                 
                               
                             
                             ) 
                           
                           2 
                         
                         . 
                       
                     
                   
                 
               
               
                 
                   FIG 
                   . 
                   
                       
                   
                    
                   6 
                 
               
             
           
         
       
     
         [0000]    Thus, the output voltage generated by the  FIG. 6  will be more accurate than the  FIG. 4  output for all values of C P . If C P  is large as compared to C, the advantages of the  FIG. 6  embodiment may be reduced. 
         [0060]    The output of the preamplifier may be sampled by the SHA/DAC after all the auto-zeroing stages have completed their performances.  FIG. 8(   a ) illustrates a timing diagram of auto-zeroing and sampling performance, and  FIGS. 8(   b ) and  8 ( c ) illustrate simulated preamplifier performances of a single auto-zeroing stage and a pair of auto-zeroing stages respectively. At time T AZ1 , the performance of the first auto-zero stage, which is the first phase, may be complete. At time T AZ2 , the performance of the second auto-zero stage, which is the second phase, may be complete if the pre-amplifier includes a pair of auto-zeroing stages. And at time T S , which is subsequent to time T AZ2 , the SHA/DAC may sample the output generated by the preamplifier. In a single auto-zero embodiment, T S  may be subsequent to time T AZ1 . 
         [0061]      FIG. 8(   b ) simulates a preamplifier performance with a single auto-zero stage. The simulation shows the relationship between V OUT  and V IN .  FIG. 8(   c ) simulates a preamplifier performance with a pair of auto-zero stages As graph  FIG. 8(   c ) shows, V OUT  may follow V IN  more closely after the second auto-zero stage performance is complete at time T AZ2  compared to after the first auto-zero stage performance is complete at time T AZ1 . Therefore, the two auto-zero stage embodiment provides better performance than a single auto-zero stage embodiment for the same overall capacitance. 
         [0062]    The principles of the present invention may be extended to greater numbers of auto-zeroing stages.  FIG. 9  is a block diagram of a preamplifier  900  with an amplifier  910  and M stages  920 - 940  according to an embodiment of the present invention. 
         [0063]    The stages of this embodiment may be constructed as in the foregoing embodiments, with a capacitor and associated switches. Operation of the amplifier  900  also may proceed over multiple stages in which, during each stage, an output voltage from a preceding stage is input to the amplifier&#39;s input to cancel some of the V OFF  contribution and parasitic capacitance generated by the amplifier. The output voltage from that phase may be stored on a capacitor of another stage which may be input to the amplifier in a succeeding phase of operation. 
         [0064]    At the conclusion of all phases of operation, the amplifier  900  may generate an output voltage of the form: 
         [0000]    
       
         
           
             
               V 
               OUT 
             
             ≈ 
             
               
                 V 
                 IN 
               
               + 
               
                 
                   V 
                   OFF 
                 
                 * 
                 
                   
                     
                       ( 
                       
                         
                           C 
                           P 
                         
                         
                           C 
                           + 
                           
                             C 
                             P 
                           
                         
                       
                       ) 
                     
                     M 
                   
                   . 
                 
               
             
           
         
       
     
         [0000]    The M th  order contribution of the 
         [0000]    
       
         
           
             ( 
             
               
                 C 
                 P 
               
               
                 C 
                 + 
                 
                   C 
                   P 
                 
               
             
             ) 
           
         
       
     
         [0000]    renders the embodiment of  FIG. 9  more accurate than the  FIG. 4  or  FIG. 6  embodiments (assuming M&gt;2), where C is the capacitance used per stage. 
         [0065]    An increase in the number of preamplifier stages, however, can introduce signal corruption due to charge injection. When considering the effects of charge injection, the preamplifier may generate an output voltage as follows: 
         [0000]    
       
         
           
             
               
                 V 
                 OUT 
               
               ≈ 
               
                 
                   V 
                   IN 
                 
                 + 
                 
                   
                     V 
                     OFF 
                   
                   * 
                   
                     
                       ( 
                       
                         
                           C 
                           P 
                         
                         
                           C 
                           + 
                           
                             C 
                             P 
                           
                         
                       
                       ) 
                     
                     M 
                   
                 
                 + 
                 
                   
                     
                       Q 
                       ch 
                     
                      
                     M 
                   
                   C 
                 
               
             
             , 
           
         
       
     
         [0000]    where
 
C represents the size of each capacitor per stage, C P  is the amplifier parasitic capacitance, M is the number of stages, and Q ch  represents channel charge of the switches in the auto-zero stages. Thus, the
 
         [0000]    
       
         
           
             
               
                 Q 
                 ch 
               
                
               M 
             
             C 
           
         
       
     
         [0000]    term above represents voltage errors induced by the  FIG. 9  design. Circuit designers may optimize the number of stages needed for their applications by considering trade offs presented by the 
         [0000]    
       
         
           
             ( 
             
               
                 C 
                 P 
               
               
                 C 
                 + 
                 
                   C 
                   P 
                 
               
             
             ) 
           
         
       
     
         [0000]    scalar and the 
         [0000]    
       
         
           
             
               
                 Q 
                 ch 
               
                
               M 
             
             C 
           
         
       
     
         [0000]    error term and the overall timing complexity of managing multiple stages in the circuit. 
         [0066]    Although the foregoing discussion illustrates preamplification for a sample and hold amplifier in an ADC system, the principles of the present invention are not so limited. The techniques illustrated above may be employed in almost any system that includes a sample and hold amplifier or any system that works on sampled data requiring a pre-amplifier. For example, the auto-zeroing preamplifiers of the present invention may be used with SHAs in the other circuit systems mentioned above in the background, such as switched capacitor amplifiers, switched capacitor integrators and switched capacitor filters. 
         [0067]    Several embodiments of the present invention are specifically illustrated and described herein. However, it will be appreciated that modifications and variations of the present invention are covered by the above teachings. In other instances, well-known operations, components and circuits have not been described in detail so as not to obscure the embodiments. It can be appreciated that the specific structural and functional details disclosed herein may be representative and do not necessarily limit the scope of the embodiments. 
         [0068]    Those skilled in the art may appreciate from the foregoing description that the present invention may be implemented in a variety of forms, and that the various embodiments may be implemented alone or in combination. Therefore, while the embodiments of the present invention have been described in connection with particular examples thereof, the true scope of the embodiments and/or methods of the present invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, specification, and following claims.