Abstract:
Memory address decoder circuitry including a decoder for activating a corresponding memory access control conductor in response to registered address bits. An address register stores received address bits for presentation to the inputs of the decoder and includes reset circuitry for resetting the outputs of the address register to an inactive state during an inactive time period to reduce transition glitches in the decoder during latching in a subsequent active period.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates in general to electronic memories and in particular to glitch-free memory address decoding circuits and methods and memory subsystems using the same. 
   2. Background of Invention 
   A typical electronic memory system, such as a random access memory (RAM) system or a read-only memory (ROM) system, is based on an array of rows and columns of memory cells. Depending on the architecture, these memory cells are organized into data storage locations for storing data words of a given width. For example, in a “16 by 16” memory system, data are stored as 16-bit wide words in 16-column wide locations along a corresponding row. Data are then accessed (read and written) to a given location at the intersection of the corresponding row and columns using associated row and column addresses. 
   In synchronous memory systems, row and column addresses are latched into an address register and held until the next set of row and column addresses arrives. The current address in the address register is decoded into row and column select signals which control the selection of the rows and columns corresponding to the addressed location. Once these row and column signals have settled into the proper state, the decoder outputs are enabled, and the access is performed. 
   The process of latching and decoding each address, including allowing the decoder outputs to settle, requires a finite, although variable, time period. If the decoder outputs are enabled before this process is complete, glitches may occur which corrupt the data and/or misdirect the access to the wrong memory location. These glitches may also add noise to the system and cause excess power dissipation. Hence, a time delay is typically introduced between address latching and decoder output enablement to allow for circuit activation and signal settling. This delay normally includes sufficient margin to account for fabrication process, voltage and temperature variation, noise, and similar factors that impact circuit timing. 
   Designing timing circuitry to provide the sufficient timing margins required to ensure glitch-free memory operation across a range of fabrication and operating variables is a relatively complicated effort. For example, the timing margins should be minimized since holding-off the enablement of the decoder outputs directly increases the time to access the array. In high-speed memory systems, minimized access time is a critical design parameter. On the other hand, decoder output enablement must be delayed by a sufficient amount of time to avoid the problem of glitches described above. Hence, new circuits and methods are required which relax the design constraints on the access timing circuitry while still allowing high-speed glitch-free accesses. 
   SUMMARY OF INVENTION 
   The principles of the present invention provide for the resetting of the outputs of an address latch or register following memory address decoding to avoid glitches during a subsequent address cycle. According to one particular embodiment, memory address decoder circuitry, which includes a decoder for activating a corresponding memory access control conductor in response to registered address bits, is disclosed. An address register stores received address bits for presentation to the inputs of the decoder and includes reset circuitry for resetting the outputs of the address register to an inactive state during an inactive time period to reduce transition glitches in the decoder during latching in a subsequent active period. 
   Circuits, systems, and methods embodying the inventive principles afford significant advantages over the prior art when applied to electronic memories. For example, resettable latches (registers) not only reduce or eliminate glitches during address decoding but also allow the complexity of the associated timing circuits to be substantially reduced. In particular, since the register (latch) outputs are reset to an inactive state, no location select signals are generated, even if the decoder output enable signals transition to an active state. The select signal is not generated and passed to the access control logic to enable the row and column selection until all of the registered address bits reach their final state. Furthermore, the inventive principles are embodied in a range of volatile and non-volatile electronic memory devices, including RAM devices, ROM devices, and Flash memory devices. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
     For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
       FIG. 1  is a high level functional block diagram of an exemplary memory subsystem suitable for describing the present inventive principles; 
       FIG. 2  is an electrical schematic diagram of portions of an exemplary address latch (register) and an exemplary associated row decoder embodying the principles of the present invention; 
       FIG. 3A  is an electrical schematic diagram of an exemplary resettable latch which resets to a logic low inactive state and is suitable for use in constructing in one embodiment of the address latch shown in  FIG. 2 ; 
       FIG. 3B  is an electrical schematic diagram of an exemplary resettable latch which resets to a logic high inactive state and is suitable for use in constructing in a second embodiment of the decoder of  FIG. 2 ; 
       FIG. 4A  is an electrical schematic diagram of an exemplary resettable latch which resets to a logic low inactive state and includes a second output latch for holding data for an additional clock cycle, the latch of  FIG. 4A  is suitable for use in constructing a third embodiment of the latch of  FIG. 2 ; 
       FIG. 4B  is an electrical schematic diagram of an exemplary resettable latch which resets to a logic high inactive state and includes a second output latch for holding data for an additional clock cycle, the latch of  FIG. 4B  is suitable for use in constructing a fourth embodiment of the latch of  FIG. 2 ; and 
       FIG. 5  is a timing diagram illustrating the typical operation of the address latching and decoding circuitry of  FIG. 2  according to the inventive principles. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The principles of the present invention and their advantages are best understood by referring to the illustrated embodiment depicted in  FIGS. 1–5  of the drawings, in which like numbers designate like parts. 
     FIG. 1  is a high-level functional block diagram of an exemplary memory subsystem  100  suitable for describing the application of the present inventive principles. Memory subsystem  100  may be, for example, a stand-alone integrated circuit or an embedded memory subsystem within a system-on-a-chip. 
   Memory system  100  is based on an array  101  of memory cells  102  organized in M number of rows and N number of columns. Memory cells  102  are, for example, volatile memory cells, such as dynamic random access memory (DRAM) and static random access memory (SRAM) cells, or non-volatile memory cells, such as mask programmed read-only memory (ROM) and Flash (electrically-erasable and programmable) ROM cells. Array  101  may be divided into subarrays as known in the art. 
   Each memory cell  102  is accessed through a conductive wordline  0 ,  1 , or  2  associated with the corresponding row and a conductive bitline  104  associated with the intersecting column. A row in array  101  is selected using a row decoder  105  which activates the corresponding wordline  0 ,  1 , or  2  in response to row address received at the Y-bit wide subsystem multiplexed address port  106  (ADD[ 0 :Y- 1 ]) ( FIG. 1  shows ADD[ 0 :Y]. Therefore, either drawing or spec. needs to be corrected.). A location along the selected row is accessed through X-bit wide data port  107  (DQ[ 0 :X- 1 ]) ( FIG. 1  shows DQ [ 0 :X]. Therefore, either drawing or spec. needs to be corrected.) and the corresponding bitlines  104  through a column decoder  108  and sense amplifiers  109  in response to a column address received through address port  106 . In other words, exemplary memory subsystem  100  has a “by-X” configuration in which each location is X number of cells (columns) wide and accessed through an X-bit wide data port  107 , in which X is an integer greater than one (1). The address port width Y is a function of the number of rows and columns in array  101  and the width of each addressable location. 
   In the illustrated embodiment, row and column addresses are multiplexed through address port  106  using conventional row and column address strobes (/RAS and /CAS) presented at /RAS input  113  and /CAS input  114 . For each row address, multiple column addresses may be generated and clocked-in with /CAS in the page mode to access multiple locations along the selected row during the same /RAS cycle. Read and write operations are controlled by the read—write signal R-/W presented at R-/W input  115 . In synchronous embodiments, the timing base is derived from the master clock CLK presented at clock port  116 . 
   A read operation to an addressed location in array  101  is generally implemented by sensing and latching the data from the row of cells along the active wordline  0 ,  1 , or  2  through the column decoder  108  and into sense amplifiers  109 . Data from the X-bit location or page of X-bit wide locations being read are then passed by sense amplifier  109  and a read buffer/amplifier  110  to data port  107 . During a write operation, data at data port  107  are driven to the location or locations selected by column decoder  108  by a write amplifier  111  through the corresponding bitlines  104 . 
   Address latches, clock generators, buffers, power distribution circuitry are generally represented by block  112  in  FIG. 1 . Address latches suitable for use in memory system  100  embodying the inventive principles are further discussed below. 
     FIG. 2  is a more detailed functional block diagram of a portion of a row address latch (register)  200  corresponding to address bits A 0 , A 1 , and A 2  of a Y-bit wide row address received through address port  106 . Additionally, the complement /A i  of each address bit A i , in which i is an integer index between 0 and Y−1, is generated by a corresponding input inverter  201 . Each address bit A i  is latched by a self-resetting latch  202  and each complementary address bit/A i  by a self-resetting latch  203 , in response to a timing signal CLK and its complement /CLK which are derived from the system clock. For illustrative purposes, three latches  202   a – 202   c  corresponding to address bits A 0 –A 2  and three latches  203   a – 203   c  corresponding to complementary address bits /A 0  –/A 2  are shown in  FIG. 2 . Embodiments of self-resetting latches  203  and  204  embodying the inventive principles are discussed in detail below. The complementary registered address bits latched in self-resetting latches  202  and  203  (A i reg and /A i reg) are respectively driven by output buffers/drivers  204  and  205  to the inputs of row decoder  105 . 
   The complementary address bit pairs A i , /A i  held in the corresponding latches  202  and  203  drive row decoders  212  within row decoder block  105  (see also,  FIG. 1 ). Portions of three row decoders  212   a – 212   c  controlling wordlines  0 – 2  are shown in  FIG. 2  for discussion purposes. Generally, each decoder  212  includes one decoder transistor for each complementary address bit pair Ai, /Ai and each wordline  0 ,  1 , or  2 . The current paths of the decoder transistors of a given decoder  212  are coupled in series between the corresponding wordlines  0 ,  1 , or  2  and ground, and the gates are coupled to either the corresponding latch  202  (registered bit A i reg) or latch  203  (registered bit /A i reg), depending on the decode logic. For example, representative transistors  206   a – 206   c  of row decoder  212   a  control in part Wordline  0  in response to representative address bits A 0 reg, A 1 reg, and A 2 reg. Similarly, address bits /A 0 reg, A 1 reg, and A 2 reg control in part Wordline  1  through representative transistors  207   a – 207   c  of row decoder  212   b  and address bits A 0 reg, /A 1 reg, and A 2 reg control in part Wordline  2  through transistors  208   a – 208   c  of row decoder  212   c . In the illustrative embodiment of  FIG. 2 , NMOS decoder transistors  206 – 208  are shown which turn-on in response to active high states of A i reg and/A i reg. In the alternate embodiments of the inventive principles, an active low decoder logic may be used. 
   Each wordline  0 ,  1 , or  2  is enabled/disabled by a PMOS transistor  209  and an NMOS transistor  210  in response to the W ORDLINE  E NABLE  control signal and driven by an associated inverting driver  211 . Representative PMOS transistors  209   a – 209   c , NMOS transistors  210   a – 210   c , and inverters  211   a – 211   c  associated with Wordlines  0 – 3  are shown for the partial decoder array  105  of  FIG. 2 . 
   Row decoders  212   a – 212   c  uniquely decode complementary address bit pairs A i , /A i  to activate the selected wordlines  0  to  3  (Delete  103   a  to  103   c  from  FIG. 2  to avoid double-numbering of the wordlines.) being accessed. During the inactive period, W ORDLINE  E NABLE  control signal is held in a logic low level such that PMOS transistors  209   a – 209   c  and inverters  211   a – 211   c  hold wordlines  0  to  3  of array  101  in an inactive low state. The complementary address bit pairs A i , /A i  are then latched into latches  202   a – 202   c  and  203   a – 203   c , and the resulting registered address bits A i reg, /A i reg are presented to the gates of transistors  206   a – 206   c ,  207   a – 207   c , and  209   a  – 209   c  are allowed to settle to their final levels. Registered address bits A i reg, /A i reg selectively turn-on the decoder transistors of decoders  212   a – 212   c , in the case of decoders  212   a – 212   c , transistors  206   a – 206   c ,  207   a – 207   c  and  209   a – 209   c , corresponding to the wordlines  0  to  3  to be selected. Decoders  212   a – 212   c  for the deselected wordlines remain turned-off. The W ORDLINE  E NABLE  control signal transitions to an active high state turning on NMOS transistors  210   a – 210   c . With the active decoders  212   a – 212   c  of the selected wordlines  0  to  3  turned on and conducting, the input to the associated inverter  211   a – 211   c  is pulled down to ground. In turn, the selected wordline is driven to an active high state for the access. 
   In conventional decoding schemes, when the address bits within latches  202   a – 202   c  and  203   a – 203   c  transition, one or more row decoders  212   a – 212   c  may turn-on or turn-off randomly until the registered address bits A i reg, /A i reg settle. Therefore, normally, in order to ensure that the correct wordlines  0  to  3  is selected, the activation of the W ORDLINE  E NABLE  control signal must be held-off long enough to allow decoders  212   a – 212   c  to settle to their proper states. On the other hand, to minimize access times to cell array  101 , the hold-off time designed into W ORDLINE  E NABLE  control signal must be minimized. In a conventional system, a number of variables must be considered in determining the margins on W ORDLINE  E NABLE  control signal. 
   The time between receipt of the address word and the decoding of each complementary address bit pair A i , /A i  by decoders  212   a – 212   c  varies between address bit paths due to both chip-wide effects (e.g. process, temperature, and supply voltage) and local effects (e.g. the fabrication and layout of transistors). In other words, the delay between the latching of the address, the settling of registered address bits A i reg, /A i reg, and consequently the proper activation and deactivation of the correct decoder transistors  206   a – 206   c ,  207   a – 207   c , and  208   a – 208   c , will vary between address bits. In sum, the delay in the activation of W ORDLINE  E NABLE  control signal must include sufficient margin to cover the worst case expected delay to decode all of the bits Ai, /Ai of the entire address word. This delay margin must also be sufficient to account for variations in W ORDLINE  E NABLE  control signal itself with the same chip-wide and local effects. 
   According to the principles of the present invention, self-resetting latches  202   a – 202   c  and  203   a – 203   c  reset to an inactive state after each access such that decoders  212   a – 212   c  are disabled, no matter what the current state of W ORDLINE  E NABLE  control signal. When the new address word and its complement are latched into latches  202   a – 202   c  and  203   a – 203   c , only those control signals required to turn-on transistors (e.g. transistors  206   a – 206   c ,  207   a – 207   c , and  208   a – 208   c ) within decoders  212   a – 212   c  are active. The remaining control signals A i reg, /A i reg are maintained in an inactive state and thus cannot cause indeterminate activation of the transistors of decoders  212   a – 212   c . Glitches are thereby prevented, even if W ORDLINE  E NABLE  control signal transitions to an active state before signals A i reg, /A i reg settle. As a result, the timing margins on W ORDLINE  E NABLE  control signal are relaxed, which result in a simplified circuit design and improved access times. 
     FIG. 3A  is an electrical schematic diagram of a first self-resetting latch  300  suitable for use in applications such as latches  202   a – 202   c  and  203   a – 203   c  of  FIG. 2  requiring an active high output. At the start of the address cycle, the clock CLK is in a low state and its complement /CLK is in a logic high state. The corresponding address bit A i  or /A i  (A i  in the case of latches  202   a – 202   c  and /A i  in the case of latches  203   a – 203   c ) is passed through the transfer gate  301  formed by PMOS transistor  302  and NMOS transistor  303  and then inverted by an inverter  304  formed by PMOS transistor  305  and NMOS transistor  306 . The output of inverter  304  (Node A) drives the input of a second inverter  307  formed by PMOS transistor  308  and NMOS transistor  309 . At the same time, transfer gate  310  (PMOS transistor  311  and NMOS transistor  312 ) and transfer gate  313  (PMOS transistor  314  and NMOS transistor  315 ) are turned-off. 
   During the period when CLK is low, PMOS reset transistor  316  holds the input to output inverter  317  (PMOS transistor  318  and NMOS transistor  319 ) high. Consequently, the latch  300  output (A i reg in the case of latches  202   a – 202   c  or /A i reg in the case of latches  203   a – 203   c ) is held in a reset (inactive) low state. On the transitions of CLK to a logic high and /CLK to a logic low, transfer gate  301  turns-off and transfer gates  310  and  313  turn-on. Inverters  304  and  307  latch the bit at Node A. Reset transistor  316  releases the input to output inverter  317  which in turn drives the output A i reg (/A i reg) of latch  300  from Node A. At the end of the address cycle, CLK transitions back to a logic low state, and the latch  300  output A i reg or /A i reg resets to the inactive (logic low) state by reset transistor  316 . 
     FIG. 3B  illustrates a second self-resetting latch  320  suitable for use in such applications requiring an active low output. The structure and operation of latch  320  is similar to that of latch  300 . However, in this case, an NMOS transistor  321  pulls down the input to output inverter  317  to ground when /CLK transitions to a logic high state. With /CLK high, the output A i reg or /A i reg, of latch  320  is reset to an inactive high state. 
   Address latch  400  shown in  FIG. 4A  adds an additional register function to latch  300  of  FIG. 3A  which holds the latched address bit at a double-registered output A i dreg or /A i dreg until the next active cycle of clock CLK. This embodiment also generates the resettable single-registered output A i reg (/A i reg) discussed above. The operation described above with respect to latch  300  applies to that of latch  400  with the following additions. 
   Transfer gate  401  (PMOS transistor  402  and NMOS transistor  403 ) passes the bit at Node A to Node B (Nodes A and B are not labeled in  FIG. 4A  or  4 B) when CLK transitions to a logic high and /CLK transitions to a logic low. Inverter  404  (PMOS transistor  405  and NMOS transistor  406 ) which drives the input of a second inverter  407  (PMOS transistor  408  and NMOS transistor  409 ) inverts the bit at Node B. Inverters  404  and  407  form a latch. On the next transition of CLK low and /CLK high, transfer gate  410 , formed by PMOS transistor  411  and NMOS transistor  412 , turn-on to latch the bit at Node B. Transfer gate  401  at the same time turns-off. The registered output A i dreg is driven from Node B by an inverter  413  formed by PMOS transistor  414  and NMOS transistor  415 . The bit at registered output A i dreg is held until the next transition of CLK and /CLK low at which time the next bit passed to Node A is clocked to Node B and latched. 
   A similar embodiment  420  is shown in  FIG. 4B  in which the additional register function described in conjunction with  FIG. 4A  is added to the output of the latch  320  of  FIG. 3B . In this case, the complementary couple-registered bit/A i dreg is held until the next active cycle of clock CLK. 
     FIG. 5  is a timing diagram illustrating the advantages of using self-resetting latches according to the inventive principles. In particular, immediately following the transition of CLK to an active high state, the registered complementary address bits A i reg and /A i reg are in their inactive states. As a result, no wordline  0 ,  1 , or  2  is decoded, even if W ORDLINE  E NABLE  control signal transitions to an active high state before A i reg and /A i reg have settled. A wordline  0 ,  1 , or  2  is selected only after all A i reg and /A i reg bits reach their final states. The constraints on circuitry generating W ORDLINE  E NABLE  control signal is therefore relaxed leading to a simplified design. 
   Although the invention has been described with reference to a specific embodiments, these descriptions are not meant to be construed in a limiting sense. Various modifications of the disclosed embodiments, as well as alternative embodiments of the invention will become apparent to persons skilled in the art upon reference to the description of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. 
   It is therefore, contemplated that the claims will cover any such modifications or embodiments that fall within the true scope of the invention.