Abstract:
A method of testing a reflection-type LCD projector is disclosed. The present invention provides a method of testing the digital-circuit portion of the data drivers of the silicon wafer LCD of the reflection-type LCD projector, and a method of testing the panel pixel area of the silicon wafer LCD display. The present invention can be applied to LCD display panels manufactured by CMOS process and polysilicon thin film transistor process for the benefits of helping to resolve manufacturing issues during the development stage, thereby shortening the required production time schedule, and reducing the production cost.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a method for testing a reflection-type LCD projector. More specifically, it relates to a method for testing the digital-circuit portion of the data driver of the silicon wafer LCD of a reflection-type LCD projector, and a method for testing the panel pixel area of the silicon wafer LCD display of a reflection-type LCD projector. 
     2. Description of Related Art 
     At present, the silicon wafer liquid crystal display, which is manufactured by CMOS fabrication process, is applied to the reflection-type LCD projector. The silicon wafer liquid crystal display is characterized by integrating data drivers, scan drivers, and the pixel area onto a single insulating substrate by making the best of the high electronic mobility of the CMOS process. The structure of the silicon wafer liquid crystal display (LCD) is illustrated in FIG.  1 . 
     For a reflection-type LCD projector using a silicon wafer liquid crystal display (or silicon wafer LCD hereafter) to project images onto a screen, its fabrication must integrate technologies including applied circuit design, driver IC (integrated circuits) design, photo-etching of patterned electrodes, filling of liquid crystals, packaging, and mounting of a back-light assembly, etc. Therefore, the silicon wafer LCD is a complicated product that relies on a highly coordinated manufacturing process. If the fabricated driver ICs can not be adequately and reliably tested, then the following steps for filling the LCD module with liquid crystals, packaging, and mounting back-light assembly can not be carried out. When the silicon wafer LCD fails to function properly during the final stages of manufacturing, then the subsequent process of debugging and reworking will prove to be costly and the real problems can not be identified and resolved. For a profit-seeking manufacturer, the subsequent waste of labor and material during mass-production stage, to fill liquid crystals, packaging, and mount back-light assembly will in time become costly. 
     The conventional method for testing the pixel area of the TFT-LCD panel includes a method that involves CCD image contrasting. When applying the CCD contrasting method, the panel is first back-lighted by a lighting source. The CCD device then takes an image of the pixels on the display panel, converts the image into digital data, and finally compare the data in contrast to the controlled sets of data in order to find pixel defects appearing on the display panel. However, the above described method only apply to conventional LCD manufacturing process where data drivers, scan drivers, and display panel are each fabricated and tested separately. 
     However, a CMOS silicon wafer LCD is an integrated device of data drivers, scan drivers, and display panel. Therefore, in order to apply the CCD image contrasting method on testing the CMOS silicon wafer LCD, the above mentioned manufacturing process of filling of liquid crystals and mounting of driver ICs and back-light assembly has to be completed before a test can be carried out. The need for a silicon wafer LCD module to be fully assembled before a functional test can be administered makes the CCD image contrast test impractical and uneconomical. 
     As shown in FIG. 1, the three main components to be tested on a silicon wafer LCD are the scan drivers, the data drivers, and the pixel area. Among them, the test implemented on the scan drivers only compares the input and output signals in series. The crucial task, then, is to find highly reliable and efficient testing methods for each of the data drivers and the pixel area components. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is the object of the present invention to provide a highly reliable and efficient testing method for a CMOS silicon wafer LCD in a reflection-type LCD projector for the purpose of mass-production, and research and development. 
     A first testing method for testing the digital-circuit portion of data drivers of a silicon wafer LCD comprises the following steps: 
     Provide the first and the second test patterns. The first test pattern has 2n bits of digital data P 1 ˜P 2n  where P 2j−1 =0, P 2j =1, and 1≦j≦n. The second test pattern has 2n bits of digital data Q 1 ˜Q 2n  where Q 2j−1 =0, Q 2j =1. 
     The digital data of the first test pattern are inputted to the digital-circuit portion, and the 2n digital data are processed and outputted by the digital-circuit portion, thereby obtaining 2n bits of a first processed data Pr 1 ˜Pr 2n . Every value of P 1 , P 3 , ˜P 2n−1  processed by the digital-circuit portion is assigned to each of the respective Pr 2j−1 , while every value of P2, 2 4 , ˜P2n processed by the digital-circuit portion is assigned to each of the respective Pr 2j . 
     The digital data of the second test pattern are inputted to the digital-circuit portion, and the 2n digital data are processed and outputted by the digital-circuit portion, thereby obtaining 2n bits of a second processed data Qr 1 ˜l Qr 2n . Every value of Q 1 , Q 3 , ˜Q 2n−1  processed by the digital-circuit portion is assigned to each of the respective Qr 2j−1 , while every value of Q 2 , Q 4 , ˜Q 2n  processed by the digital-circuit portion is assigned to each of the respective Qr 2j . 
     Consequently, both a first and second testing apparatus are provided; the first testing apparatus accepts a first specific value and the first processed data Pr 1 ˜Pr 2n  while the second testing apparatus accepts a second specific value and the second processed data Qr 1 ˜Qr 2n . If the first and second testing apparatuses output the first and second specific values respectively, then the digital-circuit portion processes the first and second test patterns without any error. 
     A second testing method for testing the display panel pixel area of a silicon wafer LCD that has M scan-lines with N pixel units located on each of the scan-lines to detect damaged pixels comprises the following steps: 
     (1) Divide the N pixels (data lines) into K pixel groups. Provide a group-data parallel-in series-out device. Provide a first test pattern of data length K, which is formed by outputting a first-type data and a second-type data alternately. Provide a second test pattern of data length K which is complementary to the first test pattern. 
     (2) Selecting one of the M scan-lines, write the first test pattern of data length K into K corresponding pixel group; wherein each pixel within the same pixel group is written with the same data value, and the N pixel units located on the selected scan-line are written with the K data of the first test pattern. 
     Input, in parallel, the data written into the N pixel units to the group-data parallel-in series-out device; wherein the group-data parallel-in series-out device processes the data written into every pixel within each of the K pixel groups and outputs a first processed outcome with a data length K. Complete the data output of the first processed outcome, in series, after K time cycles. 
     (3) Write the K data of the second test pattern into the K pixel groups respectively; where each pixel within the same pixel group has the same data, and the N pixels are written with the K data of the second test pattern. 
     Input, in parallel, the data written into the N pixel units to the group-data parallel-in series-out device; wherein the group-data parallel-in series-out device processes the data written into every pixel unit within each of the K pixel groups and outputs a second processed outcome with a data length K. Complete the data output of the second processed outcome, in series, after K time cycles. 
     (4) Repeat the above steps (2) and (3) until all of the M scan-lines are tested completely; wherein, when each of the M scan-lines is tested according the above steps, the first test pattern is contrasted with the first processed outcome while the second test pattern is contrasted with the second processed outcome in order to detect any damaged pixels. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other objects, features, and advantages of the present invention will become apparent from the following detailed description of the preferred but non-limiting embodiment. The description is made with reference to the accompanying drawings in which: 
     FIG. 1 illustrates the structure of a silicon wafer liquid crystal display; 
     FIG. 2 schematically illustrates the structure of a data driver; 
     FIG. 3 schematically illustrates the structure of a circuit-testing apparatus  23 ; 
     FIG. 4 schematically illustrates the structure of a first testing method of the present invention; 
     FIG. 5 schematically illustrates the structure of the first test apparatus  23   a;    
     FIG. 6 schematically illustrates the structure of a second testing method of the present invention; 
     FIG. 7 schematically illustrates the structure of the second test apparatus  23   b;    
     FIG. 8 depicts routing arrangement of the test apparatus within the structure of the data driver in consideration of the first test pattern; 
     FIG. 9 schematically illustrates the conventional structure for testing the pixel area of a display panel; 
     FIG. 10 schematically illustrates the structure for testing the display panel pixel area according to the present invention; and 
     FIG. 11 illustrates the circuit arrangement for the group-data parallel-in series-out apparatus. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The following are preferred embodiments according to the present invention that describe a testing method for the CMOS silicon wafer LCD data driver as well as a testing method for the display panel pixel area. 
     EMBODIMENT I: Method for Testing the Digital-circuit Portion of the Data Driver 
     As shown in FIG. 2 (without the Digital testing circuit  23 ), the general structure of a conventional data driver comprises at least the following units: a shift register  20 , a sample register  21 , a hold register  22 , a DAC (Digital-to-Analog Converter)  24 , an OP AMP (operational amplifier)  25 , etc. The data driver contains both analog and digital circuits; nevertheless, the present invention is specifically designed for testing the digital-circuit portion DT. 
     With regard to the digital-circuit portion of the data driver, the shift register  20 , sample register  21 , and the hold register  22  all have iterative characteristics; the digital-circuit portion is thus a typical iterative logic circuit. Consequently, the present invention discloses a method of error detection, specifically for the digital-circuit portion of the data driver. The testing method according to the present invention is carried out in conjunction with less testing circuits, thereby reducing the cost for testing. As shown in the data driver structure of FIG.  2 , there is an additional digital testing circuit  23  provided between the digital-circuits portion DT and the DAC  24  such that the testing method according to the present invention can be carried out. 
     Table 1 is a tabulation of the failure analysis statistics obtained after the LCD passes through the stages of design, production, and testing without utilizing the digital testing circuit  23 . 
     As shown in Table 1, the failure for the shift register  20  is about 8.2%; the error detection of the shift register  20  is done by checking the serial output signal of the shift register  20 . If the data driver structure of FIG. 2 is tested without the digital testing circuit  23 , then all four different circuits of the sample register  21 , hold register  22 , DAC  24 , and OP AMP  25  will be tested. However, the combined percentage failure for all of the four circuit tests can be as high as 91.8%. 
     
       
         
               
             
               
               
             
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 STATISTICS OF CIRCUIT DEFECT OCCURRING LOCATIONS 
               
             
          
           
               
                 CIRCUIT DEFECT OCCURRING 
                 PERCENTAGE SHARE AMONG 
               
               
                 LOCATIONS 
                 ALL CIRCUIT DEFECTS 
               
               
                   
               
             
          
           
               
                 Shift register 
                   
                  8.2% 
               
               
                 Sample register 
                 + 
                 91.8% 
               
               
                 Hold register 
                 + 
               
               
                 DAC  
                 + 
               
               
                 OP AMP 
               
               
                   
               
             
          
         
       
     
     Consequently, it is difficult to accurately locate and distinguish the essential points of the 91.8% failure rate; for instance, the failure could be caused by the DAC  24 , or it could be caused by circuits before the DAC  24 . 
     The data outputted from the shift register  20  is processed by the sample register  21 , the hold register  22 , the DAC  24 , and the OP AMP  25 . Then the OP AMP  25  outputs an analog signal. In order to sample the analog signal for analyzing, an additional step for using a low-frequency horizontal synchronization (Hsync) signal as a sampling frequency signal is required, and thus the testing time is increased inevitable. 
     In order to accurately point out the cause of the failure, or fault, reduce the cost of testing and production, and expand the logic fault coverage of testing, the present invention discloses a digital testing circuit  23  which is designed specifically for testing the digital-circuit portion of the data driver. 
     The testing method carried out in conjunction with the digital testing circuit  23  depicted in FIG. 3, is described in detail hereinafter. 
     The testing method comprises the following steps: 
     First, provide a first test pattern which has 2n bits of digital data P 1 ˜P 2n  where P 2j−1 =0, P 2j =1, and 1≦j≦n. 
     Second, provide a second test pattern which has 2n bits of digital data Q 1 ˜Q 2n  where Q 2j−1 =1, Q 2j =0, and 1≦j≦n. 
     Next, input the digital data of the -first test pattern (P 1 ˜P 2n ) to the digital-circuit portion DT of the data driver. The digital-circuit portion DT outputs a first processed data (Pr 1 ˜Pr 2n ) of 2n bits. The value of each of the first processed data Pr 1 , ˜Pr 2j−1  is selected respectively from one of the values of the different data P 1 , P 3 , ˜P 2n−1  after being processed. 
     Then, input the digital data of the second test pattern (Q 1 ˜Q 2n ) to the digital-circuit portion DT of the data driver. The digital-circuit portion DT outputs a second processed data (Qr 1 ˜Qr 2n ) of 2n bits. The value of each of the second processed data Qr 1 , ˜Qr 2j−1  is selected respectively from one of the values of the different data P 1 , P 3 , ˜P 2n−1  after being processed. 
     Provide the digital testing circuit  23 , which is composed by a first testing apparatus  23   a  and a second testing apparatus  23   b , as depicted in FIG.  3 . The first testing apparatus  23   a  receives a first specific value S 1  and the first processed data Pr 1 ˜Pr 2n ; the second testing apparatus  23   b  receives a second specific value S 2  and the second processed data Qr 1 ˜Qr 2n . 
     The first testing apparatus  23   a  comprises m first-type testers T 1 # 1 ˜T 1 #m, and m second-type testers T 2 # 1 ˜T 2 #m, alternately connected to each other in series. Each of the first-type and second-type testers has k input terminals, where mx (k−1)=n. 
     Further, the first input terminal of the first-type tester T 1 # 1  is coupled to the first specific value S 1 , and the output of the first-type tester T 1 # 1  is coupled to the first input terminal of the second-type tester T 2 # 1 . The first input terminal of the y th  (2≦y≦m) first-type tester (T 1 #y) is coupled to the output of the (y−1) th  second-type tester (T 2 # (y−1)), and the output of the y th  first-type tester (T 1 #y) is coupled to the first input terminal of the y th  second-type tester (T 2 #y) The rest of the (k−1) input terminals of each of the first-type testers (T 1 # 1 ˜T 1 #m) then selectively receives (k−1) different Pr 2j−1  data from the respective first processed data, and the rest of the (k−1) input terminals of each of the second-type tester (T 2 # 1 ˜T 2 #m) then selectively receives (k−1) different Pr 2j  data from the respective first processed data. 
     Similarly, the second testing apparatus  23   b  comprises m first-type testers U 1 # 1 ˜U 1 #m, and m second-type testers U 2 # 1 ˜U 2 #m, alternately connected to each other in series. Each of the first-type and second-type testers has k input terminals, where mx (k−1)=n. 
     Further, the second input terminal of the second-type tester U 2 # 1  is coupled to the second specific value S 2 , and the output of the second-type tester U 2 # 1  is coupled to the first input terminal of the first-type tester U 1 # 1 . The first input terminal of the y th  (2≦y≦m) second-type tester (U 2 #y) is coupled to the output of the (y−1) th  first-type tester (U 1 # (y−1)), and the output of the y th  second-type tester (U 2 #y) is coupled to the first input terminal of the y th  first-type tester (U 1 #y). The rest of the (k−1) input terminals of each of the second-type testers (U 2 # 1 ˜U 2 #m) then selectively receives (k−1) different data from the respective second processed data (Qr 2j−1 ), and the rest of the (k−1) input terminals of each of the first-type tester (U 1 # 1 ˜U 1 #m) then selectively receives (k−1) different data from the respective second processed data (Qr 2j ) 
     The first specific value S 1  and the second specific value S 2  are selectively inputted to the first testing apparatus  23   a  or the second testing apparatus  23   b  according to the test pattern selected. 
     The following describes the method for testing the digital-circuit portion DT of the data driver in detail, and the method is divided into two separate test patterns for clarity. 
     1. The First Test Pattern 
     The first test pattern (P 1 ˜P 2n , n=16) contains 32-bit digital data (P 1 ˜P 32 ), where P 2j−1 =0, P 2j =1, and 1≦j≦16, so the first test pattern has the form of [P 1  P 2  P 3  P 4  . . . P 31  P 32 ]=[0 1 0 1 . . . 0 1]. 
     Referring to FIG. 4, the above first test pattern [P 1  P 2  P 3  P 4  . . . P 31  P 32 ] is equally divided into four sets of data, [P 1 ˜P 8 ], [P 9 ˜P 16 ], [P 17 ˜P 24 ], and [P 25 ˜P 32 ]. Then these four sets of data are to be processed by four shift registers (SHR 1 ˜SHR 4 ) four sample registers (SAR 1 ˜SAR 4 ), and four hold registers (HOR 1 ˜HOR 4 ) separately (i.e. processed by the digital-circuit portion of the data driver), in such a way that the first processed data [Pr 1  Pr 2  Pr 3  Pr 4  . . . Pr 31  Pr 32 ] are outputted from the output terminals (out 1 ˜out 32 ) of the hold registers (HOR 1 ˜HOR 4 ). Consequently, the circuit layout and/or test pattern can be arranged in such a way that each of the processed data (Pr 1 , Pr 3 , Pr 5 , . . . Pr 29 , Pr 31 ) outputted via the odd-numbered output terminals of the hold registers (out 1 , out 3 , out 5 , . . . out 29 , out 31 ) corresponds to one of the different odd-numbered input data P 2j−1 , where 1≦j≦16, of the first test pattern after being processed. By the same token, the circuit layout and/or test pattern can be arranged in such a way that each of the processed data (Pr 2 , Pr 4 , Pr 6 , . . . Pr 30 , Pr 32 ) outputted via the even-numbered output terminals of the hold registers (out 2 , out 4 , out 6 , . . . out 30 , out 32 ) corresponds to one of the different even-numbered input data P 2j , where 1≦j≦16, of the first test pattern after being processed. 
     In the present embodiment, the [P 1  P 8  P 7  P 2  P 3  P 6  P 5  P 4 ] data, after being processed, serve as the processed data Pr 1 ˜Pr 8  outputted via the output terminals out 1 ˜out 8 , respectively; the [P 9  P 16  P 15  P 10  P 11  P 14  P 13  P 12 ] data, after being processed, serve as the processed data Pr 9 ˜Pr 16  outputted via the output terminals out 9 ˜out 16 , respectively; the [P 17  P 24  P 23  P 18  P 19  P 22  P 21  P 20 ] data, after being processed, serve as the processed data Pr 17 ˜Pr 24  outputted via the output terminals out 17 ˜out 24 , respectively; and the [P 25  P 32  P 31  P 26  P 27  P 30  P 29  P 28 ] data, after being processed, serve as the processed data Pr 25 ˜Pr 32  outputted via the output terminals out 25 ˜out 32 . 
     Accordingly, the first testing apparatus  23   a  receives inputs of both the first processed data [Pr 1  Pr 2  Pr 3  Pr 4  . . . Pr 31  Pr 32 ] and the first specific value Sl, and it then outputs processed data Dout 1 . 
     Referring to FIG. 5, in this embodiment the first testing apparatus  23   a  comprises eight NOR gates and eight NAND gates alternately interconnecting with each other in series. The eight NOR gates (NOR 1 ˜NOR 8 ) are logic devices serving as the first-type testers (T 1 # 1 ˜T 1 # 8 , m=8) ; every NOR gate has three input terminals and one output terminal. Further, the eight NAND gates (NAND 1 ˜NAND 8 ) are logic devices serving as the second-type testers (T 2 # 1 ˜T 2 # 8 ); every NAND gate has three input terminals and one output terminal. 
     The second and third input terminals of each of the NOR gates (NOR 1 ˜NOR 8 ) receive the first processed data (Pr 1 , Pr 3 ), (Pr 5 , Pr 7 ), . . . (Pr 29 , Pr 31 ) respectively; the second and third input terminals of each of the NAND gates (NAND 1 ˜NAND 8 ) receives the first processed data (Pr 2 , Pr 4 ), (Pr 6 , Pr 8 ), . . . (Pr 30  Pr 32 ) respectively. 
     If the first test pattern [P 1  P 2  P 3  P 4  . . . P 31  P 32 ], which has been processed by the digital-circuit portion DT (i.e. shift register, sample register, and hold register), does not produce any error during the process, then none of the data will be changed throughout the process. 
     From above descriptions, the data [P 1  P 8  P 7  P 2  P 3  P 6  P 5  P 4 ] after being processed are outputted via out 1 ˜out 8  output terminals and serve as the first processed data Pr 1 ˜Pr 8 ; the data [P 9  P 16  P 15  P 10  P 11  P 14  P 13  P 12 ] after being processed are outputted via out 9 ˜out 16  output terminals and serve as the first processed data Pr 9 ˜Pr 16 ; the data [P 17  P 24  P 23  P 18  P 19  P 22  P 21  P 20 ] after being processed are outputted via out 17 ˜out 24  output terminals and serve as the first processed data Pr 17 ˜Pr 24 ; and the data [P 25  P 32  P 31  P 26  P 27  P 30  P 29  P 28 ] after being processed are outputted via out 25 ˜out 32  output terminals and serve as the first processed data Pr 25 ˜Pr 32 . Therefore, if the digital-circuit portion DT processes the first data pattern without any error, then the value of the first processed data [Pr 1  Pr 2  Pr 3  Pr 4  . . . Pr 31  Pr 32 ] outputted by terminals out 1 ˜out 32  of the hold registers (HOR 1 ˜HOR 4 ) should be [0 1 0 1 . . . 0 1], the same as the first data pattern, where Pr 2j−1 =0 and Pr 2j =1 (1≦j≦16). 
     Consequently, the first NOR gate (NOR 1 ) would receive the first specific value S 1  (the value S 1  is “0” in this embodiment) and the first processed data [Pr 1 , Pr 3 ] then output the value “1” ; the first NAND gate (NAND 1 ) would receive the value “1” outputted by NOR 1  and the data [Pr 2 , Pr 4 ] then output the value “0”. In a like manner, when the eighth NOR gate (NOR 8 ) receives the value “0” outputted by NAND 7  and the processed data [Pr 29 , Pr 31 ], it will then output a value “1”, and when the eighth NAND gate (NAND 8 ) receives the value “1” outputted by NOR 8  and the value [Pr 30 , Pr 32 ], it will then output a value “0” . As a result, if no error is produced or generated by the processing of the digital-circuit portion DT, then the output data value Dout 1  of the first testing apparatus  23   a  should be “0”. 
     On the other hand, if, during the operating process of the digital-circuit portion DT, an error is generated in that at least one data value of the first test pattern [P 1  P 2  P 3  P 4  . . . P 31  P 32 ] has been changed, for example, a certain P 2j−1  changes its value from “0” to “1” or a certain P 2j  changes its value from “1” to “0”, then the output Dout 1  of the first testing apparatus  23   a  would not have been “0” but “1”. Thus, the error caused by the digital-circuit portion DT can be detected. 
     Another example of an error caused by the digital-circuit portion DT would be that when P 26  changes its value from “1” to “0”; since Pr 25 ˜Pr 32  are the processed data of [P 25  P 32  P 31  P 26  P 27  P 30  P 29  P 28 ] outputted via output terminals Out 25 ˜out 32 , Pr 28  also changes its value from “1” to “0”, corresponding to P 26 . Because there is no error generated at Pr 1 ˜Pr 27 , the output value of NOR 1 ˜NOR 7  will all be “1” and the output value of NAND 1 ˜NAND 6  will all be “0” after the first testing apparatus  23   a  receives the first specific value S 1 =“0”. Then, the gate NAND  7  receives both the output value “1” from the gate NOR 7  and the first processed data Pr 26  and Pr 28  (“1” and “0”, respectively), so the output of NAND 7  becomes “1” which, in turn, makes the output of NOR 8  “0”. The final output of the gate NAND  8  then becomes “1” as a consequence. Since the output Dout 1 , of the first testing apparatus  23   a , of value “1” does not equal the first specific value Si of value “0”, the error generated by the digital-circuit portion can be detected. 
     Similarly, if the digital-circuit portion generates any error that causes the processed first test pattern to contain more than one error in it, this will also cause the output Dout 1  of the first testing apparatus  23   a  to not equalize the first specific value S 1 . Consequently, multiple errors generated by the digital-circuit portion can also be detected. 
     2. The Second Test Pattern 
     The second test pattern (Q 1 ˜Q 2n , n=16) contains 32-bit digital data (Q 1 ˜Q 32 ), where P 2j−1 =0, P 2j =1, and 1≦j≦16, so the second test pattern has the form of [Q 1  Q 2  Q 3  Q 4  . . . Q 31  Q 32 ]=[0 1 0 1 . . . 0 1]. 
     Referring to FIG. 6, the above second test pattern [Q 1  Q 2  Q 3  Q 4  . . . Q 31  Q 32  ] is equally divided into four sets of data, [Q 1 ˜Q 8 ], [Q 9 ˜Q 16 ], [Q 17 ˜Q 24 ], and [Q 25 ˜Q 32 ]. Then these four sets of data are to be processed by four shift registers (SHR 1 ˜SHR 4 ), four sample registers (SAR 1 ˜SAR 4 ), and four hold registers (HOR 1 ˜HOR 4 ) separately (i.e. processed by the digital-circuit portion of the data driver), in such a way that the first processed data [Qr 1  Qr 2  Qr 3  Qr 4  . . . Qr 31  Qr 32 ] are outputted from the output terminals (out 1 ˜out 32 ) of the hold registers (HOR 1 ˜HOR 4 ). 
     Analogous to the first test pattern, the circuit layout and/or test pattern can be arranged in such a way that each of the processed data (Qr 1 , Qr 3 , Qr 5 , . . . Qr 29 , Qr 3 ) outputted via the odd-numbered output terminals of the hold registers (out 1 , out 3 , out 5 , . . . out 29 , out 31 ) corresponds to one of the different odd-numbered input data Q 2j−1 , where 1≦j≦16, of the second test pattern. By the same token, the circuit layout and/or test pattern can be arranged in such a way that each of the processed data (Qr 2 , Qr 4 , Qr 6 , . . . Qr 30 , Qr 32 ) outputted via the even-numbered output terminals of the hold registers (out 2 , out 4 , out 6 , . . . out 30 , out 32 ) corresponds to one of the different even-numbered input data Q 2j , where 1≦j≦16, of the second test pattern. 
     In the present embodiment, the [Q 1  Q 8  Q 7  Q 2  Q 3  Q 6  Q 5  Q 4 ] data, after being processed, serve as the processed data Qr 1 ˜Qr 8  outputted via the output terminals out 1 ˜out 8 , respectively; the [Q 9  Q 16  Q 15  Q 10  Q 11  Q 14  Q 13  Q 12 ] data, after being processed, serve as the processed data Qr 9 ˜Qr 16  outputted via the output terminals out 9 ˜out 16 , respectively; the [Q 17  Q 24  Q 23  Q 18  Q 19  Q 22  Q 21  Q 20 ] data, after being processed, serve as the processed data Qr 17 ˜Qr 24  outputted via the output terminals out 17 ˜out 24 , respectively; and the [Q 25  Q 32  Q 31  Q 26  Q 27  Q 30  Q 29  Q 28 ] data, after being processed, serve as the processed data Qr 25 ˜Qr 32  outputted via the output terminals out 25 ˜out 32 . 
     Accordingly, the second testing apparatus  23   b  receives inputs of both the second processed data [Qr 1  Qr 2  Qr 3  Qr 4  . . . Qr 31  Qr 32 ] and the second specific value S 2 , and it then outputs processed data Dout 2 . 
     Referring to FIG. 7, in this embodiment the second testing apparatus  23   b  comprises eight NOR gates and eight NAND gates alternately interconnecting with each other in series. The eight NAND gates (NAND* 1 ˜NAND* 8 ) serve as the second-type tester (U 2 # 1 ˜U 2 # 8 , m=8); every NAND gate has three input terminals and one output terminal. Further, the eight NOR gates (NOR* 1 ˜NOR* 8 ) serve as the first-type tester (U 1 # 1 ˜U 1 # 8 ); every NOR gate has three input terminals and one output terminal. 
     The second and third input terminals of each of the NAND gates (NAND* 1 ˜NAND* 8 ) receive the first processed data (Qr 1 , Qr 3 ), (Qr 5 , Qr 7 ), . . . (Qr 29  Qr 31 ) respectively; the second and third input terminals of each of the NOR gates (NOR* 1 ˜NOR* 8 ) receives the first processed data (Qr 2 , Qr 4 ), (Qr 6 , Qr 8 ), . . . (Qr 30  Qr 32 ) respectively. 
     Analogous to the first test pattern, if the second test pattern [Q 1  Q 2  Q 3  Q 4  . . . Q 31  Q 32 ], which has been processed by the digital-circuit portion DT (i.e. shift register, sample register, and hold register), does not produce any error during the process, then none of the data of [Q 1  Q 2  Q 3  Q 4  . . . Q 31  Q 32 ] will be changed throughout the process. 
     From above descriptions, the data [Q 1  Q 8  Q 7  Q 2  Q 3  Q 6  Q 5  Q 4 ] after being processed are outputted via out 1 ˜out 8  output terminals and serve as the second processed data Qr 1 ˜Qr 8 ; the data [Q 9  Q 16  Q 15  Q 10  Q 11  Q 14  Q 13  Q 12 ] after being processed are outputted via out 9 ˜out 16  output terminals and serve as the second processed data Qr 9 ˜Qr 16 ; the data [Q 17  Q 24  Q 23  Q 18  Q 19  Q 22  Q 21  Q 20 ] after being processed are outputted via out 17 ˜out 24  output terminals and serve as the second processed data Qr 17˜Qr   24 ; and the data [Q 25  Q 32  Q 31  Q 26  Q 27  Q 30  Q 29  Q 28 ] after being processed are outputted via out 25 ˜out 32  output terminals and serve as the second processed data Pr 25 ˜Pr 32 . Therefore, if the digital-circuit portion DT processes the second data pattern without any error, then the value of the second processed data [Qr 1  Qr 2  Qr 3  Qr 4  . . . Qr 31  Qr 32 ] outputted by terminals out 1 ˜out 32  of the hold registers (HOR 1 ˜HOR 4 ) should be [1 0 1 0 . . . 1 0], where Qr 2j−1 =1 and Qr 2j =0 (1≦j≦16). 
     Consequently, the first NAND gate (NAND* 1 ) would receive the second specific value S 2  (the value S 2  is “1” in this embodiment) and the second processed data [Qr 1 , Qr 3 ] then output the value “0”; the first NOR gate (NOR* 1 ) would receive the value “0” outputted by NAND* 1  and the data [Qr 2 , Qr 4 ] then output the value “1” . In a like manner, when the eighth NAND gate (NAND* 8 ) receives the value “1” outputted by NOR* 7  and the processed data [Qr 29 , Qr 31 ], it will then output a value “0”, and when the eighth NOR gate (NOR* 8 ) receives the value “0” outputted by NAND* 8  and the data [Qr 30 , Qr 32 ], it will then output a value “1”. As a result, if no error is produced or generated by the processing of the digital-circuit portion DT, then the output data value Dout 2  of the second testing apparatus  23   b  should be “1”. 
     On the other hand, if, during the operating process of the digital-circuit portion DT, an error is generated in that at least one data value of the first test pattern [Q 1  Q 2  Q 3  Q 4  . . . Q 31  Q 32 ] has been changed, for example, a certain Q 2j−1  changes its value from “1” to “0” or a certain Q 2j  changes its value from “0” to “1”, then the output Dout 2  of the second testing apparatus  23   b  would not have been “1” but “0”. Thus, the error caused by the digital-circuit portion DT can be detected. 
     Another example of an error caused by the digital-circuit portion would be that when Q 26  changes its value from “0” to “1” ; since Qr 25 ˜Qr 32  are the processed data of [Q 25  Q 32  Q 31  Q 26  Q 27  Q 30  Q 29  Q 28 ] outputted via terminals out 25 ˜out 32 , Qr 28  also changes its value from “0” to “1”, corresponding to Q 26 . Because there is no error generated at Qr 1 ˜Qr 27 , the output value of NAND* 1 ˜NAND* 7  will all be “0” and the output value of NOR* 1 ˜NOR* 6  will all be “1” after the second testing apparatus  23   b  receives the second specific value S 2 =“1”. Then, the gate NOR* 7  receives both the output value “0” from the gate NAND* 7  and the second processed data Qr 26  and Qr 28  (“0” and “1”, respectively), so the output of NOR* 7  becomes “0” which, in turn, makes the output of NAND* 8  “1”. The final output of the gate NOR* 8  then becomes “0” as a consequence. Since the output Dout 2 , of the second testing apparatus  23   b , of value “0” does not equal the second specific value S 2  of value “1”, thus the error generated by the digital-circuit portion can be detected. 
     Similarly, if the digital-circuit portion generates any error that causes the processed second test pattern to contain more than one error in it, this will also cause the output Dout 2  of the second testing apparatus  23   b  to not equalize the second specific value S 2 . Consequently, multiple errors generated by the digital-circuit portion can also be detected. 
     From the aforementioned examples, when the digital-circuit portion of an IC is being tested, it can be seen that the circuit layout and test pattern are arranged in such a way that the data values stored in every shift register and every hold register at any adjacent location (left/right or up/down) are to be logic “0” and logic “1”, respectively. Accordingly, from any shift register to any corresponding hold register and from any hold register to any corresponding DAC, every two adjacent signal lines of the 8-bit connecting lines also transmit the data of logic “0” and logic “1” respectively. Therefore, if the transmitted data on any signal line is stuck at “0” or stuck at “1” due to error operation or circuit defect, it will be detected according the present invention. 
     On the other hand, if a short circuit occurs between any of the two adjacent signal lines, then these two lines must both be either logic “0” or logic “1”. For instance, if the two adjacent signal lines that transmit the data Pr 1  and Pr 2  (0, 1) in FIG. 5 are incidentally short-circuited, from FIG. 5 it can be seen that the value of Pr 1  to be inputted to NOR 1  will be changed from “0” to “1” (or that the value of Pr 2  to be inputted to NAND 1  will be changed from “1” to “0”). When the output Dout 1  (or the output Dout 2 ) of the first testing apparatus  23   a  (or the second testing apparatus  23   b ) does not equal S 1  (or S 2 ), NOR 1  (or NAND 1 ) will detect and identify this status as an error. 
     Furthermore, if any input terminal of each of the NOR gates or NAND gates in FIG. 5 is short-circuited, the short circuit error will be detected as well. For instance, the NOR 1  gate receives data from both Pr 1  and Pr 3 . The signal line transmitting the data Pr 2 , which is supposed to have opposite logic value to Pr 1  and Pr 3 , is arranged between the signal lines transmitting the data Pr 1  and Pr 3 . From a planar point of view, if the signal lines transmitting Pr 1  and Pr 3  are incidentally shorted together, the signal lines that transmit Pr 1  Pr 2 , and Pr 3  are certainly shorted together. Consequently, if the electrical potentials of Pr 1  and Pr 2  are correct, then the error due signal line shorted to Pr 3  will be detected and identified. 
     In this embodiment, the input image data are 32-bit as an example. The image data are separately processed by four shift registers (SHR 1 ˜SHR 4 ), four sample registers (SAR 1 ˜SAR 4 ), and four hold registers (HOR 1 ˜HOR 4 ). Then, the hold registers (HOR 1 ˜HOR 4 ) output these processed 32-bit data to a digital-to-analog converter DAC 1  via the output terminals out 1 ˜out 32 ; the DAC 1  comprises four 8-bit DAC. 
     Referring to FIG. 8, in order to grasp the idea of test circuit routing applied to the method for testing the digital-circuit portion of a data driver, consider the condition under which the first test pattern is inputted. First of all, the data P 1 ˜P 8  of the first test pattern are processed through the shift register (SHR 1 ), the sample register (SAR 1 ) and the hold register (HOR 1 ) depicted in FIG. 4, then outputted from the output terminals of the hold register (HOR 1 ), and assigned as the first processed data Pr 1 ˜Pr 8  respectively. 
     In order to demonstrate the concept of test circuit routing in brevity, the demonstration as follows will be limited to routing of digital data Pr 1 ˜Pr 8  between the output terminals out 1 ˜out 8  of hold register (HOR 1 ) and the input terminals of an 8-bit DAC. The data output and routing between the other output terminals out 9 ˜out 32  and the other three 8-bit DAC will be temporarily ignored since the concept can be derived directly. 
     As shown in FIG. 8, the output terminals out 1 ˜out 8  of the hold register (HOR 1 ) is coupled directly to the 8-bit digital-to-analog converter DAC 1  for the normal operation of image data processing by the data driver. After the first test pattern is inputted, the data [P 1  P 8  P 7  P 2  P 3  P 6  P 5  P 4 ] are processed and outputted as the processed data Pr 1 ˜Pr 8  via out 1 ˜out 8 . The NOR 1  gate of the first testing apparatus  23   a  is coupled to Pr 1 , Pr 3 , and S 1 ; the NAND 1  gate of the first testing apparatus  23   a  is coupled to Pr 2 , Pr 4 , and the output of NOR 1 ; the NOR 2  gate of the first testing apparatus  23   a  is coupled to Pr 5 , Pr 7 , and the output of NAND 1 ; the NAND 2  gate of the first testing apparatus  23   a  is coupled to Pr 6 , Pr 8 , and the output of NOR 2 . 
     In addition, the testing circuit routing of the present invention comprises certain dummy signal lines shown as dotted lines in FIG.  8 . 
     Further, the dummy signal line branched from the signal line transmitting the data Pr 2  (or Pr 4 ) is arranged between and in parallel to the signal lines transmitting the data Pr 1  and Pr 3  (or the data S 1  and Pr 1 ), and it extends toward the NOR gate NOR 1 . The dummy signal line branched from the signal line transmitting the data Pr 6  (or Pr 8 ) is arranged between and in parallel to the signal lines transmitting the data Pr 5  and Pr 7  (or the data Pr 7  and the output of the NAND gate NANDL), and it extends toward the NOR gate NOR 2 . The dummy signal line branched from the signal line transmitting the data Pr 3  (or Pr 1 ) is arranged between and in parallel to the signal lines transmitting the data Pr 2  and Pr 4  (or the data Pr 2  and the output of the NOR gate NOR 1 ), and it extends toward the NAND gate NAND 1 . And finally, the dummy signal line branched from the signal line transmitting the data Pr 7  (or Pr 5 ) between and in parallel to Pr 6  and Pr 8  (or the data Pr 8  and the output of the NOR gate NOR 2 ), and it extends toward NAND 2 . With the help of all these dummy signal lines, detection of every possible short circuit can be achieved. 
     The arrangement of the dummy signal lines will not require additional layout area since the width of each of the dummy signal lines only occupies 0.6 μm, with 0.6 μm line pitch. The area occupied by NOR/NAND provides the additional layout area. 
     The aforementioned routing layout in FIG. 8 is used for illustrating the testing scheme based on the first test pattern. Similarly, the routing layout for illustrating the testing scheme based on the second test pattern, in reference with FIG. 7, requires only the switching of NOR and NAND gate locations and changing of the data outputted via terminals out 1 ˜out 32 , to the second processed signals Qr 1 ˜Qr 32 . 
     In the first (or second) testing apparatus  23   a  (or  23   b ) of the aforementioned embodiment, each of the NOR gate and NAND gate has three input terminals and one output terminal. Alternatively, the present invention can be adapted to utilize the NOR gate and NAND gate with a number of k input terminals, such as four input terminals, depending on the requirements of the overall design of the test pattern. 
     Based on the above analysis, it should be stressed that the testing method of the present invention has the capability to detect LCD defects, including short circuit, “stuck at 1”, and “stuck at 0”, which are caused mainly by photo-mask shifting, poor manufacturing quality, and airborne dust particles. Therefore, the fault coverage rate by this testing method is very high, and the method only requires two types of test pattern. Further, the cycle time for each circuit test is equal to the time needed to sample the horizontal synchronization signal of the silicon on wafer LCD twice. In other words, the testing method of the present invention is simultaneously quick and accurate. 
     EMBODIMENT II: Method for Pixel Area Testing 
     The purpose of pixel area testing is to detect and identify the existence of any pixel defect in the pixel area and to calculate the total number of pixel defects and their location distribution thereto. As show in FIG. 9, the conventional pixel area testing method takes to input both the highest and lowest pixel voltages of the pixel units in parallel to the pixel units, and then the voltages written to the pixel units are read out in serial and compared with the original input voltages. 
     In general, the conventional method takes a long time for testing pixel area. For instance, the pixel area structure depicted in FIG. 9 comprises M scan-lines (SCAN_ 1  ˜SCAN_M), and N data input terminals along every scan-line. Therefore, it takes M×N clock cycles to carry out the entire testing for the M×N pixel units completely. The pattern for testing always has a long data format. Therefore, besides the problems of being time-consuming and not very cost effective, the exceedingly long test pattern might even surpass the capacity of the testing apparatus buffer for it to function properly, or it might cause the testing apparatus not to function at all. Eventually, as the resolution of the display panels increase, it will be a major task to find a pixel area testing method with a short test pattern in order to lower the production time, cost and testing cost while maintaining the quality of the products. 
     Referring to FIG. 10, a testing structure used for working in conjunction with the pixel area testing method of the present invention is shown; the testing method is realized by additionally providing a group-data parallel-in series-out device  100 . Under the normal operation of panel display, a normal signal is enabled (Normal=1) such that image data DAC_OP 1 , DAC_OP 2 ˜DAC_OPN outputted from the digital-to-analog converter (DAC) can be written in sequence to the pixel units through the every corresponding buffer B 1  and the each of the data lines (L 1 ˜LN). 
     Otherwise, if the Normal signal is set to be “0”, then the pixel area of the display panel is under test. While under test, the signal Charge is set to the logical value “1” (that is Charge=1), thereby activating all of the B 2  buffers. The activated B 2  buffers, in turn, enable electrical connections between the L 1 ˜LN data lines and corresponding signal lines SR 1  and SR 2  such that the testing data can be written into each of the pixel units at all the scan-lines. According to the status of the parallel/series control signal S, the aforementioned group-data parallel-in series-out device  100  will receive the pixel data P 1 ˜PN read via the data lines L 1 ˜LN in parallel when S=1; when S=0, the group-data parallel-in series-out device  100  outputs the received pixel data P 1 ˜PN in series after they are processed by device  100 . 
     In order to carry out the testing method of the present invention, the N data lines (L 1 ˜LN) are divided into K pixel groups such as group  1 ˜group K. Each of the pixel groups comprises i data lines, where i≧2 and K=N/i. In this embodiment, every pixel group is defined as comprising two adjacent data lines. Accordingly, the data lines L 1  and L 2  via which DAC_OP 1  and DAC_OP 2  are written into the pixel units, are defined as the first pixel group; the data lines L 3  and L 4  via which DAC_OP 3  and DAC_OP 4  are written into the pixel units, are defined as the second pixel group. Analogously, it is evident that the data lines L(N−1) and LN via which DAC_OP(N−1) and DAC_OPN are written into the pixel units, are defined as the K th  pixel group. 
     Furthermore, the electrical circuit structure diagram of the group-data parallel-in series-out device  100  in FIG. 10 is shown in FIG.  11 . The group-data parallel-in series-out device  100  comprises: K NAND gates (NAND_ 1 ˜NAND_K) and K NOR gates (NOR_ 1  ˜NOR_K), wherein each of the NAND gates and NOR gates have two input terminals; K first multiplexing devices (MUX 1 _ 1 ˜MUX 1 _K) and K second multiplexing devices (MUX 2 _ 1 ˜MUX 2 _K); and K flip-flops (FF_ 1 ˜FF_K). 
     Both of the NAND_ 1  and NOR_ 1  gates are coupled to the P 1  and P 2  data inputs, and their outputs are both coupled to the input terminals of the MUX 1 _ 1 ; both of the NAND_ 2  and NOR_ 2  gates are coupled to the P 3  and P 4  data inputs, and their outputs are both coupled to the input terminals of the MUX 1 _ 2 . Analogously, it can be derived that both of the NAND_K and NOR_K gates are coupled to the P(N−1) and PN data inputs, and their outputs are both coupled to the input terminals of the MUX 1 _K. 
     According to the status of the signal G, each of the first multiplexing devices (MUX 1 _ 1 ˜MUX 1 K) selectively outputs the output of the NAND gate or the NOR gate to the second input terminal of the corresponding second multiplexing device (one of the MUX 2 _ 1 , ˜MUX 2 _K). When G=0, each of the first multiplexing devices chooses to output data from the NAND gate; when G=1, the first multiplexing device chooses to output data from the NOR gate. 
     The outputs of each of the second multiplexing devices (MUX 2 _ 1 ˜MUX 2 _K) is coupled to one of the flip-flops (FF_ 1 ˜FF_K) respectively. Further, the output of the flip-flop FF_ 1  is coupled to the first input terminal of MUX 2 _ 2 ; the output of the flip-flop FF_ 2  is coupled to the first input terminal of MUX 2 _ 3 . Analogously, it is evident that the output of FF_(K−1) is coupled to the first input terminal of MUX 2 _K. When the parallel/series control signal S equals 1, each of the second multiplexing devices (MUX 2 _ 1 ˜MUX 2 _K) would output the data appearing at the second input terminal thereof, in parallel, to each of the corresponding flip-flop devices (FF_ 1 ˜FF_K). When the parallel/series control signal S equals 0, then the data inputted to each of the flip-flop devices (FF_ 1 ˜FF_K), after K clock cycles, would all eventually be outputted via the output terminal (TEST_out) of the flip-flop FF_K in series. 
     Referring to FIG. 10 and 11, the testing steps of the method according to the present invention will be described in detail hereinafter. Note, the Normal signal is set to “0”, so testing of the pixel area of the display panel can proceeds. 
     Step 1 
     Make signal G equal 0, so that the first multiplexing devices (MUX 1 _ 1 ˜MUX 1 _K) are set to output the data of the NAND gates to the second input terminals of the second multiplexing devices (MUX 2 _ 1 ˜MUX 2 _K). 
     Selectively activate the first scan-line (SCAN_ 1 ). 
     Make the signal Charge equal 1 to enable all buffers (B 2 ), and then write a low voltage signal (such as 0V), via signal line SR 1 , into the capacitors in the pixel units of the odd-numbered pixel groups (group  1 ,  3 ,  5 , . . . ). Moreover, write a high voltage signal (such as 10V), via signal line SR 2 , into the capacitors in the pixel units of the even-numbered pixel groups (group  2 ,  4 ,  6 , . . . ). 
     Disable the First Scan-line SCAN_ 1   
     Write the mean voltage signal (such as 5V), via signal lines SR 1  and SR 2 , into each parasitic capacitor in each of the data lines L 1 ˜LN. 
     Make the signal Charge equal 0, cut off the electrical connection between the data lines (L 1 ˜LN) and the signal lines (SR 1 , SR 2 ), so that each of the data lines (L 1 ˜LN) becomes floating, and the floating voltage is about 5V. 
     Make parallel/series control signal S equal 1 to enable all buffers (B 3 ), so that the group-data parallel-in series-out device  100  is standby to accept the parallel input of data (P 1 ˜PN). 
     Further, selectively activate the first scan-line SCAN_ 1 . At this time, the charges stored in the parasitic capacitors of the data lines (L 1 ˜LN) and the charges stored in the pixel units at the scan-line (SCAN_ 1 ) are re-distributed. Assuming the capacitance of each of the parasitic capacitors equals that of each of the capacitors in the pixel units. Then after the re-distribution, the output data from each of the data lines L 1 -L 2 , L 5 -L 6 , L 9 -L 10 , . . . has a low voltage signal of about 2.5V; the output data from each of the data lines L 3 -L 4 , L 7 -L 8 , L 11 -L 12 , . . . has a high voltage signal of about 7.5V. Thus, the data of the first test pattern of length K are written into K pixel groups (from group  1  to group K). 
     The signals at the data lines (or pixel groups) are converted to logic signals P 1 ˜PN, via the buffers B 3  and converters CONV. The logical signals P 1 ˜PN are inputted, in parallel, to the group-data parallel-in series-out device  100 , and processed through the NAND gates, the NOR gates, the first multiplexing devices, and the second multiplexing devices as described in FIG.  11 . Therefore, K processed data are generated and stored in the flip-flops (FF_ 1 ˜FF_K). 
     Make the parallel/series control signal S equal 0, the processed data in each of the flip-flops (FF_ 1 ˜FF_K), after K clock cycles, will eventually be outputted in series via the output terminal (TEST_out) of the flip-flop FF_K as the first processed data. 
     Step 2 
     Make signal G equal 1, so that the first multiplexing devices (MUX 1 _ 1 ˜MUX 1 _K) are set to output the data of the NOR gates to the second input terminals of the second multiplexing devices (MUX 2 _ 1 ˜MUX 2 _K). 
     Selectively activate the first scan-line (SCAN_ 1 ). 
     Make the signal Charge equal 1 to enable all buffers (B 2 ), and then write a high voltage signal (such as 10V), via signal line SR 1 , into the capacitors in the pixel units of the odd-numbered pixel groups (group  1 ,  3 ,  5 , . . . ). Moreover, write a low voltage signal (such as 0V), via signal line SR 2 , into the capacitors in the pixel units of the even-numbered pixel groups (group  2 ,  4 ,  6 , . . . ). 
     Disable the First Scan-line SCAN_ 1   
     Write the mean voltage signal (such as 5V), via signal lines SR 1  and SR 2 , into each parasitic capacitor in each of the data lines L 1 ˜LN. 
     Make the signal Charge equal 0, cut off the electrical connection between the data lines (L 1 ˜LN) and the signal lines (SR 1 , SR 2 ), so that each of the data lines (L 1 ˜LN) becomes floating, and the floating voltage is about 5V. 
     Make parallel/series control signal S equal 1 to enable all buffers (B 3 ), so that the group-data parallel-in series-out device  100  is standby to accept the parallel input of data (P 1 ˜PN). 
     Further, selectively activate the first scan-line SCAN_ 1 . At this time, the charges stored in the parasitic capacitors of the data lines (L 1 ˜LN) and the charges stored in the pixel units at the scan-line (SCAN_ 1 ) are re-distributed. Assuming the capacitance of each of the parasitic capacitors equals that of each of the capacitors in the pixel units, then, after the re-distribution, the output data from each of the data lines L 1 -L 2 , L 5 -L 6 , L 9 -L 10 , . . . has a high voltage signal of about 7.5V; the output data from each of the data lines L 3 -L 4 , L 7 -L 8 , L 11 -L 12 , . . . has a low voltage signal of about 2.5V. Thus, the data of the second test pattern of length K are written into K pixel groups (from group  1  to group K). 
     The signals at the data lines (or pixel groups) are converted to logic signals P 1 ˜PN, via the buffers B 3  and converters CONV. The logical signals P 1 ˜PN are inputted, in parallel, to the group-data parallel-in series-out device  100 , and processed through the NAND gates, the NOR gates, the first multiplexing devices, and the second multiplexing devices as described in FIG.  11 . Therefore, K processed data are generated and stored in the flip-flops (FF_ 1 ˜FF_K). 
     Make the parallel/series control signal S equal 0, the processed data in each of the flip-flops (FF_ 1 ˜FF_K), after K clock cycles, will eventually be outputted in series via the output terminal (TEST_out) of the flip-flop FF_K as the second processed data. 
     Step 3 
     Repeat STEP  1  and STEP  2  until all M scan-lines are tested. Accordingly, every time a scan-line is tested, the aforementioned first test pattern is compared with the first processed data, and the aforementioned second test pattern is compared with the second processed data, so that any pixel defect can be detected and identified. 
     The conventional test cycle, according to the pixel area testing method depicted in FIG. 9, requires a total of n flip-flops, so it takes about M×N clock cycles to complete a single test. However, the pixel area testing method according to the present invention, described in reference with FIG. 10 and 11, requires only n/i flip-flops, n/i NAND gates, n/i NOR gates, and n/i multiplexing devices, so it takes about M×(N/i) clock cycles to complete a single test. 
     Therefore, the present invention reduces the time for each test cycle while keeping the cost of circuit test down. 
     Although the present invention has been explained by the embodiments shown in the drawings described above, it should be understood to the ordinary skilled person in the art that the invention is not limited to the embodiments, but rather that various changes or modifications thereof are possible without departing from the spirit of the invention. Accordingly, the scope of the invention shall be determined only by the appended claims and their equivalents.