Abstract:
A data transfer system transfers data via a plurality of signal lines and controls to select the signal lines to adapt reduction and lane reversal. The signal line control unit has a signal creation unit that creates a first selection signal when the signal lines are reduced according to the abnormal detection from the abnormal detection unit, and a signal output unit that outputs a second selection signal when a connection of the second selection signal indicating that any one or both signal line of a second pair of signal lines is changed in case of a lane reversal that connects a plurality of signal lines in a down order from a highest bit to a lowest bit of a sending device side with a plurality of signal in a up order from a highest bit to a lowest bit of a reception device side.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2010-061947, filed on Mar. 18, 2010, the entire contents of which are incorporated herein by reference. 
       FIELD 
       [0002]    The embodiments discussed herein are related to a data transfer system, a reception device of the data transfer device and a control method of the data transfer system. 
       BACKGROUND 
       [0003]    When data are transferred between devices, in order to improve speed of the data transfer, a sending side sends data after dividing packets into a plurality of parallel signal lines and a reception side restores received data into original packets. In the data transfer, it is difficult to transfer data when one of the parallel signal lines is failed. Therefore, the data transfer continues by utilizing normal signal lines except the failed signal line. 
         [0004]      FIG. 18˜FIG .  21  illustrate diagrams that related arts are explained.  FIG. 18  illustrates a data transfer control device that connects a sending signal line selection unit  102  of the sending device  100  with a reception signal line selection unit  202  of the reception device  200  via eight signal lines  300 - 0 - 300 - 7 . However, a number of the signal lines is limited to eight. 
         [0005]    In the sending device  100 , the sending signal line selection unit  102  distributes serial sending data D 0 ˜D 7  into parallel signal lines  300 - 0 ˜ 300 - 7  via drivers  106 - 0 ˜ 106 - 7 . In the reception device  200 , the reception signal line selection unit  202  receives the data D 0 ˜D 7  through drivers  206 - 0 ˜ 206 - 7  from the signal lines  300 - 0 ˜ 300 - 7 , arranges and converts into the serial data D 0 ˜D 7  and outputs as reception data. 
         [0006]    When such parallel signal lines are utilized, it is difficult to transfer data when any one of the eight signal line paths # 0 ˜# 7  (the signal lines  300 - 0 ˜ 300 - 7 , the drivers  106 - 0 ˜ 106 - 7  and the receivers  206 - 0 ˜ 206 - 7 ) is failed. Therefore, it is proposed to divide the signal line path (called as lane as below) into two groups of [# 0 ˜# 3 ] and [# 4 ˜# 7 ] and manage whether failure signal line is existed in each group. 
         [0007]    In  FIG. 18 , a signal line control unit  104  is provided to the sending device  100  and a failure detection circuit  208  and a signal line control unit  204  are provided to the reception device  200 . The failure detection circuit  208  detects whether each signal line path (lane) is failed. The signal line control units  104  and  204  permits a selection of all signal lines to corresponding the signal line selection unit  102  and the reception signal line selection unit  202  when any one of each signal line path (lane) is not failed. 
         [0008]    As illustrated in  FIG. 19 , when the failure detection circuit  208  detects the failure of single signal line (lane # 5 : a path of the signal line  300 - 5 , the driver  106 - 5  and the receiver  206 - 5  in  FIG. 19 ), the signal line control units  104  and  204  control that the signal line selection unit  102  and the reception signal line selection unit  202  separate the failure signal line # 5  and not-failed signal lines (the lane # 4 , # 6  and # 7 ) within the group [# 4 ˜# 7 ] belonging to the failure signal line # 5  from the data transfer. 
         [0009]    By the separation, the data transfer continues by using remaining four signal lines  300 - 0 ˜ 300 - 3  to reduce the lane # 0 ˜# 3 . That is, the data transfer continues by reducing x 4  link width construction from x 8  link width construction.  FIG. 20  and  FIG. 21  illustrate a flow of the reduction. In x 8  link width construction ‘A’ that all lanes of # 0 ˜# 7  are not failed, when one lane is failed, the construction reduces x 4  link width construction ‘B’ that utilizes lane # 0 ˜# 3  if the lanes # 0 ˜# 3  are not failed. As same as, when one lane is failed, the construction reduces x 4  link width construction ‘C’ that utilizes lane # 4 ˜# 7  if the lanes # 4 ˜# 7  are not failed. 
         [0010]    However, it is difficult to continue data transfer with the x 4  link width construction that has half link width of x 8  link width construction when one of four signal lines that is utilized for data transfer is failed. 
         [0011]      FIG. 22 ,  FIG. 23  and  FIG. 24  illustrate diagrams of explanation in other related art.  FIG. 22  illustrates an example of the bi-directional data transfer. That is, the sending unit  100  in the first device sends data to the reception unit  200  of the second device through lanes # 0 ˜# 7  and the reception unit  400  of the first device receives the data from the sending unit  300  in the second device through the lanes # 0 ˜# 7 . The lane # 0 ˜# 7  are same as an example in  FIG. 18 . 
         [0012]    In this example, a number of combinations of four lanes are increased at the reduction. As illustrated in  FIG. 23  and  FIG. 24 , in the x 8  (eight) link width construction ‘A’ that all lanes of # 0 ˜# 7  are not failed, when one lane is failed, the construction reduces x 4  link width construction ‘B’ that utilizes lane # 0 ˜# 3  if the lanes # 0 ˜# 3  are not failed. As same as, when one lane is failed, the construction reduces x 4  link width construction ‘C’ that utilizes lane # 4 ˜# 7  if the lanes # 4 ˜# 7  are not failed. 
         [0013]    And in an example in  FIG. 23 , it is provided four patterns as the reduction patterns of four lanes. When one lane is failed in status that reduced x 4  link width construction, in x 4  link width construction ‘B’ which utilizes lanes # 0 ˜# 3  or in x 4  link width construction ‘C’ which utilizes lanes # 4 ˜# 7 , it is reduced to x 4  link width construction ‘D’ that utilizes the lane # 0 , # 1 , # 4 , # 5  when all lanes of # 0 , # 1 , # 4 , # 5  are not failed. As same as, it is reduced to x 4  link width construction ‘E’ that utilizes the lane # 2 , # 3 , # 6 , # 7  when all lanes of # 2 , # 3 , # 6 , # 7  are not failed. It is reduced to x 4  link width construction ‘F’ that utilizes the lane # 0  # 1  # 6 , # 7  when all lanes of # 0 , # 1 , # 6 , # 7  are not failed. It is reduced to x 4  link width construction ‘G’ that utilizes the lane # 2 , # 3 , # 4 , # 5  when all lanes of # 2 , # 3 , # 4 , # 5  are not failed. 
         [0014]    For example, as illustrated in  FIG. 22 , when detecting the failure of single signal line (lane # 4 : a path of the signal line  300 - 4 , the driver  106 - 4  and the receiver  206 - 4  in  FIG. 22 ), the signal line control units  104  and  204  of the sending device and the reception device control that the signal line selection unit  102  and the reception signal line selection unit  202  separate the failure signal line # 4  and not-failed signal lines (the lane # 5 , # 6  and # 7 ) within the group [# 4 ˜# 7 ] belonging to the failure signal line # 4  from the data transfer. By the separation, the data transfer continues by using remaining four signal lines  300 - 0 ˜ 300 - 3  to reduce the lane # 0 ˜# 3 . 
         [0015]    Further, when one lane # 0  among four lanes # 0 ˜# 3 , that is utilized for data transfer, is failed, a pair lanes # 6  and # 7 , that is non-failed signal lines in a separated group, are utilized and the failed lane # 0  and its pair lane # 1  are separated. In this timing, same lane change is achieved to the reception device  300  and the sending device  400 . 
         [0016]    In this way, it is possible to suppress the reduction width to half by selecting the signal line which is not utilized in the reduction even though two signal lines are failed among eight signal lines. 
         [0017]    Patent Document 1: Japanese Laid-open Patent Publication No. 05-250317 
         [0018]    Patent Document 2 Japanese Laid-open Patent Publication No. 05-173922 
         [0019]    Patent Document 3 Japanese Laid-open Patent Publication No. 05-257871 
         [0020]    Patent Document 4 Japanese Laid-open Patent Publication No. 02-234254 
       SUMMARY 
       [0021]    Recently, LSI (Large Scale Integrated Circuit) and IC (Integrated Circuit) are mounted on a circuit board with a high density, so short wiring distance is required. For the requirement, lane reversal technique is effective. The lane reversal technique is a function of reversing the order of arrangement of the lane number in order that the wiring of a printed circuit is easy. 
         [0022]      FIG. 25  illustrates a diagram of explanation of a lane reversal function. As illustrated in  FIG. 18˜FIG .  21 , when the arrangement of the lane number in the sending side and the arrangement of the lane number in the reception side are same, the sending side  100  and the reception side  200  are connected so that the connected lane numbers are same. While, as illustrated in  FIG. 25 , when the sending device  100  and the reception device  200  are arranged in parallel position, the wiring becomes complex if the sending side  100  and the reception side  200  are connected so that the lane numbers are same. Therefore, the sending side  100  and the reception side  200  are connected so that the connected lane numbers are reverse. 
         [0023]    In an example in  FIG. 25 , the lane # 7 ˜# 0  of the sending device  100  are connected to the lane # 0 ˜# 7  of the reception device  200 . By this connection, the wiring becomes easy. 
         [0024]    In the related art explained in  FIG. 18˜FIG .  21 , when the failed signal line is occurred in x 8  link construction ‘A’, x 4  link construction ‘B’ is constructed when the lane group [# 0 ˜# 3 ] are not failed, or x 4  link construction ‘C’ is constructed when the lane group [# 4 ˜# 7 ] are not failed. However, it is not possible to construct x 4  link if both the lane group [# 0 ˜# 3 ] and the lane group [# 4 ˜# 7 ] are failed, thereby stopping of the data transfer. 
         [0025]    The detail is explained in  FIG. 26 . For example, when detecting the failure of single signal line (lane # 4 : a path of the signal line  300 - 4 , the driver  106 - 4  and the receiver  206 - 4  in  FIG. 26 ), the control separate the failure signal line # 4  and not-failed signal lines (the lane # 5 , # 6  and # 7 ) within the group [# 4  ˜# 7 ] belonging to the failure signal line # 4  from the data transfer. By the separation, the data transfer continues by using remaining four signal lines  300 - 0 ˜ 300 - 3  to reduce the lane # 0 ˜# 3 . Further, when one lane # 0  among four lanes # 0 ˜# 3 , that is utilized for data transfer, is failed, the lane # 0 ˜# 3  which continue in the use of the data transfer cannot be selected and utilized. 
         [0026]    While, in another related art explained in  FIG. 22˜FIG .  24 , when one lane # 0  among four lanes # 0 ˜# 3 , that is utilized for data transfer, is failed, a pair of lanes # 6  and # 7 , that is non-failed signal lines in a separated group, are utilized and the failed lane # 0  and its pair lane # 1  are separated. Therefore, the data transfer can continue by x 4  link construction. 
         [0027]    However, since the data transfer continues by x 4  link construction that a pair of lanes # 6  and # 7 , that is non-failed signal lines in a separated group, are utilized, multiplexers of which a number of input is large are required in the sending device  100  and the reception device  200 . The sizes of the sending device and the reception device are large, so the size of the LSI becomes large. And it is difficult to improve an operating frequency. 
         [0028]    If further reducing the link width (for example, x 2  link construction), the transfer speed becomes lower. 
         [0029]    According to an aspect of the invention, a data transfer system for transferring data between devices connected via a plurality of signal lines, has a sending signal line selection unit that selects signal lines for data transferring among the plurality of signal lines and sends data via the selected signal lines, a reception signal line selection unit that receives the data via the selected signal lines, an abnormality detection unit that detects whether the selected signal lines are abnormal, and a signal line control unit that controls so that the sending signal line selection unit and the reception signal line selection unit select signal lines except an abnormal detected signal line according to an abnormal detection from the abnormal detection unit. And the signal line control unit includes a signal creation unit that creates a first selection signal indicating that any one or both signal line of a first pair of combination of reduction signal line and no-reduction signal line is or are not failed when the signal lines are reduced according to the abnormal detection from the abnormal detection unit, and a signal output unit that outputs a second selection signal indicating that any one or both signal line of a second pair of signal lines is or are not failed when a connection of the second selection signal indicating that any one or both signal line of a second pair of signal lines is changed in case of a lane reversal that connects a plurality of signal lines in a down order from a highest bit to a lowest bit of a sending device side with a plurality of signal in a up order from a highest bit to a lowest bit of a reception device side. 
         [0030]    According to the other aspect of the invention, a reception device of a data transfer system that receives transferred data from a sending device via a plurality of signal lines, includes a reception signal line selection unit that receives the data via a plurality of signal lines selected among the plurality of signal lines as signal lines for data transferring, an abnormality detection unit that detects whether the selected signal lines are abnormal, and a signal line control unit that controls so that the reception signal line selection unit selects signal lines except an abnormal detected signal line according to an abnormal detection from the abnormal detection unit. And the signal line control unit includes a signal creation unit that creates a first selection signal indicating that any one or both signal line of a first pair of combination of reduction signal line and no-reduction signal line is or are not failed when the signal lines are reduced according to the abnormal detection from the abnormal detection unit, and a signal output unit that outputs a second selection signal indicating that any one or both signal line of a second pair of signal lines is or are not failed when a connection of the second selection signal indicating that any one or both signal line of a second pair of signal lines is changed in case of a lane reversal that connects a plurality of signal lines in a down order from a highest bit to a lowest bit of a sending device side with a plurality of signal in a up order from a highest bit to a lowest bit of a reception device side. 
         [0031]    Further, according to the other aspect of the invention, a control method of a data transfer system for transferring data between devices connected via a plurality of signal lines, including: selecting signal lines for data transferring among the plurality of signal lines, sending data via the selected signal lines, receiving the data via the selected signal lines, detecting whether the selected signal lines are abnormal, and selecting signal lines except an abnormal detected signal line based on an abnormal detection. And the selecting includes creating a first selection signal indicating that any one or both signal line of a first pair of combination of reduction signal line and no-reduction signal line is or are not failed when the signal lines are reduced according to the abnormal detection from the abnormal detection unit, and outputting a second selection signal indicating that any one or both signal line of a second pair of signal lines is or are not failed when a connection of the second selection signal indicating that any one or both signal line of a second pair of signal lines is changed in case of a lane reversal that connects a plurality of signal lines in a down order from a highest bit to a lowest bit of a sending device side with a plurality of signal in a up order from a highest bit to a lowest bit of a reception device side. 
         [0032]    The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims. 
         [0033]    It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0034]      FIG. 1  is a configuration diagram of an information processing system according to an embodiment of the invention; 
           [0035]      FIG. 2  is a block diagram of an data transfer control system in  FIG. 1 ; 
           [0036]      FIG. 3  is an explanatory diagram of a reduction process according to a first embodiment of the invention; 
           [0037]      FIG. 4  is an explanation diagram of a reduction pattern according to a first embodiment of the invention; 
           [0038]      FIG. 5  is a flow diagram of a reduction according to a first embodiment of the invention; 
           [0039]      FIG. 6  is a circuit diagram of a first embodiment of the invention of a signal line control unit in  FIG. 2 ; 
           [0040]      FIG. 7  is a circuit diagram of a first embodiment of a sending signal line selection unit in  FIG. 2 ; 
           [0041]      FIG. 8  is a circuit diagram of a first embodiment of a reception signal line selection unit in  FIG. 2 ; 
           [0042]      FIG. 9  is a circuit diagram of a comparative example of a signal line control unit; 
           [0043]      FIG. 10  is a circuit diagram of a comparative example of a sending signal line selection unit; 
           [0044]      FIG. 11  is a circuit diagram of a comparative example of a reception signal line selection unit; 
           [0045]      FIG. 12  is a circuit diagram of a second embodiment of the invention of a signal line control unit in  FIG. 2 ; 
           [0046]      FIG. 13  is a circuit diagram of a second embodiment of a sending signal line selection unit in  FIG. 2 ; 
           [0047]      FIG. 14  is a circuit diagram of a second embodiment of a reception signal line selection unit in  FIG. 2 ; 
           [0048]      FIG. 15  is a circuit diagram of a third embodiment of the invention of a signal line control unit in  FIG. 2 ; 
           [0049]      FIG. 16  is a circuit diagram of a third embodiment of a sending signal line selection unit in  FIG. 2 ; 
           [0050]      FIG. 17  is a circuit diagram of a third embodiment of a reception signal line selection unit in  FIG. 2 ; 
           [0051]      FIG. 18  is a block diagram of a data transfer system; 
           [0052]      FIG. 19  is an explanatory diagram of a data transfer system at a reduction in  FIG. 18 ; 
           [0053]      FIG. 20  is an explanatory diagram of a reduction process in a related art; 
           [0054]      FIG. 21  is a flow diagram of a reduction process in a related art; 
           [0055]      FIG. 22  is an explanatory diagram of another reduction process in a related art; 
           [0056]      FIG. 23  is an explanatory diagram of another reduction pattern in a related art; 
           [0057]      FIG. 24  is a flow diagram of another reduction process in a related art; 
           [0058]      FIG. 25  is an explanatory diagram of a lane reversal; and 
           [0059]      FIG. 26  is an explanatory diagram of an operation at a lane reversal in a related art in  FIG. 20 . 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0060]    The embodiments will be explained below in the following order; an information processing system, a first embodiment of a data transfer control device, a second embodiment of the data transfer control device, a third embodiment of the data transfer control device, and the other embodiments, but the disclosed information processing system and the data transfer control device are not limited to these embodiments. 
         [0061]    (Information Processing System) 
         [0062]      FIG. 1  illustrates a configuration diagram of an information processing system according to an embodiment.  FIG. 2  illustrates a configuration diagram of a data transfer control device according an embodiment in  FIG. 1 . As illustrated in  FIG. 1 , an information processing system includes a CPU (Central Processing Unit)  1 , a MCU (Memory control Unit)  2 , a memory  3 , an IOU (Input/Output Unit)  4  and I/O adapters (Input/Output adapters)  5 A˜ 5 C. These elements are constructed by a LSI (Large Scale Integration Circuit). 
         [0063]    The CPU  1  are connected to the MCU  2  via a signal line (serial bus)  6 A, the MCU  2  is connected to the memory  3  via a signal line  6 - 1 , the MCU  2  is connected to the IOU  4  via a signal line (serial bus)  6 B, and the IOU  4  is connected to a plurality of the I/O adapter  5 A˜ 5 C via signal lines  6 C- 6 E respectively. 
         [0064]    In this embodiment, the signal lines  6 A˜ 6 E are targets. Data transfer control devices  7  and  8  are provided to both ends of the signal lines  6 A˜ 6 E. In an operation of the information processing system, the CPU  1  reads and writes from and to the memory  3  via the MCU  2  and executes necessary data processing. The I/O adapters  5 A˜ 5 C preferably include a network adapter and the IOU  4  preferably includes a bridge circuit. The CPU  1  executes transmission and reception to and from the I/O adapters  5 A˜ 5 C via the MCU  2  and the IOU  4 . 
         [0065]      FIG. 2  illustrates a block diagram of signal lines  6 A˜ 6 E and the data transfer control devices  7 ,  8  in  FIG. 1 . In this embodiment, an example is explained by a first device and a second device which are connected to each other via eight signal lines for data transfer (sending and reception) each other. However, a number of signal lines is not limited to eight. 
         [0066]    In  FIG. 2 , in order to transfer data between the first and the second devices, eight signal lines for a single direction, that is, sixteen signal lines for bi-direction are connected to the devices. The first device  7  sends data to the second device  8  through eight signal lines  60 - 0 ˜ 60 - 7 . The second device  8  sends data to the first device  7  through eight signal lines  62 - 0 ˜ 62 - 7 . 
         [0067]    Each sending side of the first and the second devices  7  and  8  has a sending data creation unit  70 ,  88  that prepares data to be sent and a sending line selection unit  72 ,  87  that distributes the sending data into each signal lines which is utilized by data transfer. A reception side of the first and the second devices  7  and  8  has a reception data analysis unit  78 ,  84  that analyzes the reception data and a reception line selection unit  82 ,  77  that collects and arranges the reception data from each signal lines which is utilized by data transfer. 
         [0068]    Each of the reception line selection units  82 ,  77  has a failure detection unit  89 ,  79  that detects a failed signal line. And each of the first and the second devices  7  and  8  has a signal line control unit  75 ,  85  that controls switches of the sending line selection unit  72 ,  87  and the reception line selection unit  82 ,  77  which is utilized by data transfer, according to a failure detection of the signal lines from the failure detection unit  89 ,  79 . The signal line control unit  75 ,  85  communicates the failure detection of the signal line via notification signal lines  64 - 0 ,  64 - 1  each other. 
         [0069]    When any one of the failure detection unit  89 ,  79  in the reception line selection units  82 ,  77  detects the failure signal line, the signal line control unit  75 ,  85  instructs the signal line to utilize for data transfer to the sending line selection unit  72 ,  87  and the reception line selection unit  82 ,  77 . By this operation, link construction between the first and the second devices  7 ,  8  is determined. 
         [0070]    In the first device  7 , the sending line selection unit  72  distributes serial sending data D 0 ˜D 7 , which is created by the sending data creation unit  70 , to parallel signal lines  60 - 0 ˜ 60 - 7  through drivers  74 - 0 ˜ 74 - 7  according to the link construction. In the second device  8 , the reception line selection unit  82  receives the data D 0 ˜D 7  from the parallel signal lines  60 - 0 ˜ 60 - 7  through receivers  80 - 0 ˜ 80 - 7  according to the link construction, converts the reception data into serial data D 0 ˜D 7  by arranging the reception data and outputs the serial data to the reception data analysis unit  84 . 
         [0071]    As same as, in the second device  8 , the sending line selection unit  87  distributes serial sending data D 0 ˜D 7 , which is created by the sending data creation unit  88 , to parallel signal lines  62 - 0 ˜ 62 - 7  through drivers  86 - 0 ˜ 86 - 7  according to the link construction. In the first device  7 , the reception line selection unit  77  receives the data D 0 ˜D 7  from the parallel signal lines  62 - 0 ˜ 62 - 7  through receivers  76 - 0 ˜ 76 - 7  according to the link construction, converts the reception data into serial data D 0 ˜D 7  by arranging the reception data and outputs the serial data to the reception data analysis unit  78 . 
         [0072]    (A First Embodiment of the Data Transfer Control Device) 
         [0073]      FIG. 3  illustrates a diagram of explanation of reduction operation according to a first embodiment of the data transfer control device.  FIG. 4  illustrates a relation diagram between the link construction and the reduction operation.  FIG. 5  illustrates a flow diagram of the reduction operation. 
         [0074]      FIG. 3  illustrates an example of the bi-directional data transfer according to the construction in  FIG. 2 . That is, the sending line selection unit  72  in the first device  7  sends data to the reception line selection unit  82  of the second device  8  through lanes # 0 ˜# 7 , and the reception line selection unit  77  of the first device  7  receives the data from the sending line selection unit  87  in the second device  8  through the lanes # 0 ˜# 7 . And the lane # 0 ˜# 7  includes the driver, the signal line and the receiver as illustrated in  FIG. 2 . 
         [0075]    In this embodiment, a number of combinations of four lanes are increased at the reduction, as below. As illustrated in  FIG. 4  and  FIG. 5 , in the x 8  (eight) link width construction ‘A’ that utilizes lanes # 0 ˜# 7 , a not-failed lane is selected from any one of the lane group [# 0 , # 4 ], the lane group [# 1 , # 5 ], the lane group [# 2 , # 6 ] and the lane group [# 3 , # 7 ], that each combines two lanes, if one lane is failed, and is selected from each of the groups of the lane group [# 0 , # 4 ], the lane group [# 1 , # 5 ], the lane group [# 2 , # 6 ] and the lane group [# 3 , # 7 ] if any one of the lanes or both of the lanes are failed, thereby reducing x 4  (four) link width construction ‘B’ that utilizes four lanes. 
         [0076]    And, in the x 4  (four) link width construction ‘B’, a not-failed lane is selected from each of the lane group [# 0 , # 7 ], the lane group [# 1 , # 6 ], the lane group [# 2 , # 5 ] and the lane group [# 3 , # 4 ], further if one lane of the selected lane is failed and the four link width construction ‘B’ cannot be constructed, thereby reducing the x 4  (four) link width construction ‘C’. In this case, it is required that any one or both of each of the lane group [# 0 , # 7 ], the lane group [# 1 , # 6 ], the lane group [# 2 , # 5 ] and the lane group [# 3 , # 4 ] is or are not failed. 
         [0077]    For example, as illustrated in  FIG. 3 , in the x 8  (eight) link width construction ‘A’, when the lane  4  is failed, because any one or both of each group in all of the lane group [# 0 , # 4 ], the lane group [# 1 , # 5 ], the lane group [# 2 , # 6 ] and the lane group [# 3 , # 7 ] is or are not failed, that is, the lane # 0  of the lane group [# 0 , # 4 ] and both lane of the other lane group are not failed, four lane including the lanes # 0 , # 1 , # 2 , # 4  are selected, thereby reducing the x 4  (four) link width construction ‘B’. 
         [0078]    Next, in the x 4  (four) link width construction ‘B’, when the lane  0  is further failed, because any one or both of each lane group in all of the lane group [# 0 , # 7 ], the lane group [# 1 , # 6 ], the lane group [# 2 , # 5 ] and the lane group [# 3 , # 4 ] is or are not failed, that is, the lane # 7  of the lane group [# 0 , # 7 ], the lane # 3  of the lane group [# 3 , # 4 ] and both lane of the other lane group are not failed, the lane  7  is selected as replacement for the lane # 0 , thereby reducing the x 4  (four) link width construction ‘C’ that are utilized the lane # 1 , the lane # 2 , the lane # 3  and the lane # 7 . 
         [0079]    In this reduction, a no-failed lane that is utilized in a previous reduction is remained and the replace lane is selected from no-failed lane that is not utilized as a replacement lane of the failed lane. 
         [0080]    In this way, a reduction management is performed for an unit of a pair of lanes. And as a combination of the pair of lanes, a first group including a first lane for target that reduce and a second lane for target that does not reduce and a second group including a third lane for target that reduce and a fourth lane that changes at lane reversal are provided. Further, the no-failed lane is selected from the group that any one lane is or both lanes are not failed (that is, both lanes are not failed). 
         [0081]    That is, it is possible to suppress the reduction width into a half by selecting the signal line that is not utilized at reduction, even though two signal lines are occurred failure among eight signal lines and lane reversal is executed. Further it is possible to become that a size of a multiplexer for reduction is small, thereby reducing a circuit size, as explained below. 
         [0082]      FIG. 6  illustrates a circuit diagram of the signal line control unit  75  ( 85 ) according to a first embodiment in  FIG. 2 .  FIG. 7  illustrates a circuit diagram of the sending signal line selection unit  72  ( 87 ) in  FIG. 2 .  FIG. 8  illustrates a circuit diagram of the reception signal line selection unit  82  ( 77 ) in  FIG. 2 . 
         [0083]    In  FIG. 6 , the signal line control unit  75  ( 85 ) has a first circuit  700  that instructs the x 8  (eight) link construction when judging that all signal lines are not failed, a second circuit  710  that instructs the x 4  (four) link construction when judging that any one lane is or both lanes are not failed in each of the lane group [# 0 , # 4 ], the lane group [# 1 , # 5 ], the lane group [# 2 , # 6 ] and the lane group [# 3 , # 7 ], and a third circuit  720  that instructs the x 4  (four) link construction when judging that any one lane is or both lanes are not failed in each of the lane group [# 0 , # 7 ], the lane group [# 1 , # 6 ], the lane group [# 2 , # 5 ] and the lane group [# 3 , # 4 ]. 
         [0084]    The failure detection circuit  79  ( 89 ) becomes the lane 0  ok˜lane 7  ok signals to high level (“1”) when not detecting the failure of each lanes # 018  # 7 , and becomes the lane ok signal of the lane that is detected the failure to low level (“0”) when detecting the failure of the lanes # 0 ˜# 7 . 
         [0085]    The first circuit  700  has AND circuits that arithmetic calculates a logical product of the lane 0  ok signal to the lane 7  ok signal. The second circuit  710  has a first OR circuit  712 - 0  that arithmetic calculates a logical sum of the lane 0  ok signal and the lane 4  ok signal of the lane group [# 0 , # 4 ], a second OR circuit  712 - 1  that arithmetic calculates a logical sum of the lane 1  ok signal and the lane 5  ok signal of the lane group [# 1 , # 5 ], a third OR circuit  712 - 2  that arithmetic calculates a logical sum of the lane 2  ok signal and the lane 6  ok signal of the lane group [# 2 , # 6 ], a fourth OR circuit  712 - 3  that arithmetic calculates a logical sum of the lane 3  ok signal and the lane 7  ok signal of the lane group [# 3 , # 7 ] and a AND circuit  714  that arithmetic calculates a logical product of the outputs from four OR circuits  712 -O˜ 712 - 3 . 
         [0086]    The second circuit  710  has a AND circuit  716  that arithmetic calculates a logical product of the output from the AND circuit  714  and a reverse signal of the x 8  (eight) link signal that instructs the x 8  (eight) link construction from the first circuit  700  and outputs x 4  link 1  signal that instructs x 4  link construction, and four AND circuits  718 - 0 ˜ 718 - 3  that each arithmetic calculates a logical product of the output of the AND circuit  714  and a reverse signal of the lane 0  ok signal of the lane# 0 , a reverse signal of the lane 1  ok signal of the lane# 1 , a reverse signal of the lane 2  ok signal of the lane# 2  and a reverse signal of the lane 3  ok signal of the lane# 3 . 
         [0087]    Accordingly, the second circuit  710  outputs x 4  link construction instruction from the AND circuit  716  and the lane select signals (lane_slct  0 _ 4 ,  1 _ 5 ,  2 _ 6  and  3 _ 7 ) in x 4  link construction from the four AND circuit  718 - 0 ˜ 718 - 3  when one lane is failed. That is, when all the outputs of the four AND circuits  718 - 0 ˜ 718 - 3  are ‘0’, a selection of the lanes # 0 , # 1 , # 2  and # 3  is instructed. And when all the outputs of the four AND circuits  718 - 0 ˜ 718 - 3  are ‘1’, a selection of the lanes # 4 , # 5 , # 6  and # 7  is instructed. 
         [0088]    The third circuit  720  has, as same as the second circuit  710 , a first OR circuit  722 - 0  that arithmetic calculates a logical sum of the lane 0  ok signal and the lane 7  ok signal of the lane group [# 0 , # 7 ], a second OR circuit  722 - 1  that arithmetic calculates a logical sum of the lane 1  ok signal and the lane 6  ok signal of the lane group [# 1 , # 6 ], a third OR circuit  722 - 2  that arithmetic calculates a logical sum of the lane 2  ok signal and the lane 5  ok signal of the lane group [# 2 , # 5 ], a fourth OR circuit  722 - 3  that arithmetic calculates a logical sum of the lane 3  ok signal and the lane 4  ok signal of the lane group [# 3 , # 4 ] and a AND circuit  724  that arithmetic calculates a logical product of the outputs from four OR circuits  722 - 0 ˜ 722 - 3 . 
         [0089]    The third circuit  720  has a AND circuit  726  that arithmetic calculates a logical product of the output from the AND circuit  724 , a reverse signal of the x 8  (eight) link signal that instructs the x 8  (eight) link construction from the first circuit  700  and a reverse signal of the x 4  link  1  signal that instructs x 4  link construction, and outputs x 4  link 2  signal that instructs x 4  link construction, and four AND circuits  728 - 0 ˜ 728 - 3  that each arithmetic calculates a logical product of the output of the AND circuit  724  and a reverse signal of the lane 0  ok signal of the lane# 0 , a reverse signal of the lane 1  ok signal of the lane# 1 , a reverse signal of the lane 2  ok signal of the lane# 2  and a reverse signal of the lane 3  ok signal of the lane# 3 . 
         [0090]    Accordingly, the third circuit  720  outputs x 4  link construction instruction from the AND circuit  726  and the lane select signals (lane_slct  0 _ 7 ,  1 _ 6 ,  2 _ 5  and  3 _ 4 ) in x 4  link construction from the four AND circuits  728 - 0 ˜ 728 - 3  when x 4  link  1  construction cannot be constructed and the x 4 link  2  construction can be constructed. That is, when all the outputs of the four AND circuits  728 - 0 ˜ 728 - 3  are ‘0’, the third circuit  720  instructs a selection of the lanes # 0 , # 1 , # 2  and # 3 . And when all the outputs of the four AND circuits  728 - 0 ˜ 728 - 3  are ‘1’, the third circuit  720  instructs a selection of the lanes # 7 , # 6 , # 5  and # 4 . 
         [0091]    By this construction, x 8  Link construction is instructed when all signal lines (lanes) are not failed, because of the signal “x 8 _link”=1, signal “x 4 _link_ 1 ”=0 and the signal “x 4 _link_ 2 ”=0. And when any signal line is failed, x 4  Link construction is instructed when any one or both signal lines of each lane group [# 0 , # 4 ], [# 1 , # 5 ], [# 2 , # 6 ] and [# 3 , # 7 ] is or are not failed, because of the signal “x 8 _link”=0, signal “x 4 _link_ 1 ”=1 and the signal “x 4 _link_ 2 ”=0. 
         [0092]    Further, when the x 4  link construction cannot be constructed by occurring a failure of the signal line in above x 4  link construction, x 4  Link construction is instructed when any one or both signal lines of each lane group [# 0 , # 7 ], [# 1 , # 6 ], [# 2 , # 5 ] and [# 3 , # 4 ] is or are not failed, because of the signal “x 8 _link”=0, signal “x 4 _link_ 1 ”=0 and the signal “x 4 _link_ 2 ”=1. Here, in this embodiment, young number lane is selected when both lanes of the group are not failed. 
         [0093]    Next, the sending signal line selection circuit  72  ( 87 ) in  FIG. 7  is explained. The sending signal line selection circuit  72  ( 87 ) has eight (eight lanes) multiplexers  730 - 0 ˜ 730 - 7  that select one among four inputs (sending data). Four inputs of each multiplexers  730 - 0 ˜ 730 - 3  are defined from top of the Figure, as below. 
         [0094]    (1) first data that is utilized at the time of x 8  link, x 4  link  1  and  2 , and x 4  link 2  of the lane reversal applied. 
         [0095]    (2) second data that is utilized at the time of x 4  link  1  and  2 , and x 4  link 2  of the lane reversal applied. 
         [0096]    (3) third data that is utilized at the time of x 4  link 1  of the lane reversal applied. 
         [0097]    (4) fourth data that is utilized at the time of x 8  link and x 4  link 1  of the lane reversal applied. 
         [0098]    And four inputs of each multiplexers  730 - 4 ˜ 730 - 7  are defined from top of the Figure, as below. 
         [0099]    (1) first data that is utilized at the time of x 8  link, x 4  link  1 . 
         [0100]    (2) second data that is utilized at the time of x 4  link  1 . 
         [0101]    (3) third data that is utilized at the time of x 4  link  2  and x 4  link 1  and  2  of the lane reversal applied. 
         [0102]    (4) fourth data that is utilized at the time of x 4  link  2  and x 8  link, x 4  link 1  and x 4  link 2  of the lane reversal applied. 
         [0103]    For example, in the first multiplexer  730 - 0 , the input ( 1 ) is data D 0 , the input ( 2 ) is data D 4 , the input ( 3 ) is data D 3  and the input ( 4 ) is data D 7 . As control signals, the link construction instruction, the lane select signals (x 8  link, x 4  link 1  and the lane_slct  0 _ 4 ,  1 _ 5 ,  2 _ 6  and  3 _ 7  and x 4  link 2  and the lane_slct  0 _ 7 ,  1 _ 6 ,  2 _ 5  and  3 _ 4 ), sending timing signal at x 4  link and the lane reversal instruction signal from the signal line control unit are input to all multiplexers  730 - 0 ˜ 730 - 7 . 
         [0104]    According to these control signals, eight multiplexers  730 - 0 ˜ 730 - 7  select the input ( 1 ) and simultaneously outputs it to the eight lanes  0 ˜ 7  when x 8  link construction instruction is ‘1’ and the lane reversal instruction signal that instructs the lane reversal is ‘0’ (not applied). And the eight multiplexers  730 - 0 ˜ 730 - 7  select the input ( 4 ) and simultaneously outputs it to the eight lanes  0 ˜ 7  when x 8  link construction instruction is ‘1’ and the lane reversal instruction signal that instructs the lane reversal is ‘1’ (applied). 
         [0105]    In the eight multiplexers  730 - 0 ˜ 730 - 7 , four multiplexers are selected by the lane select signal lane_slct  0 _ 4 ,  1 _ 5 ,  2 _ 6 ,  3 _ 7  when x 4  link 1  construction instruction is ‘1’. 
         [0106]    The selected four multiplexers select the inputs ( 1 ) and ( 2 ) and sequentially outputs it to the lane according to the sending timing signal when the lane reversal instruction signal that instructs the lane reversal is ‘0’ (not applied). And the selected four multiplexers select the inputs ( 3 ) and ( 4 ) and sequentially output it to the lane according to the sending timing signal when the lane reversal instruction signal that instructs the lane reversal is ‘1’ (applied). 
         [0107]    In the eight multiplexers  730 - 0 ˜ 730 - 7 , four multiplexers are selected by the lane select signal lane_slct  0 _ 7 ,  1 _ 6 ,  2 _ 5 ,  3 _ 4  when x 4  link 2  construction instruction is ‘1’. 
         [0108]    The selected four multiplexers, for example the multiplexers  730 - 0 ˜ 730 - 3  select the inputs ( 1 ) and ( 2 ) and sequentially outputs it to the lane according to the sending timing signal when the lane reversal instruction signal that instructs the lane reversal is ‘0’ (not applied). And in the selected four multiplexers, the multiplexers  730 - 0 ˜ 730 - 3  select the inputs ( 1 ) and ( 2 ) and the multiplexers  730 - 4 ˜ 730 - 7  select the inputs ( 3 ) and ( 4 ) and sequentially output it to the lane according to the sending timing signal when the lane reversal instruction signal that instructs the lane reversal is ‘1’ (applied). 
         [0109]    Next, the reception signal line selection circuit  82  ( 77 ) in  FIG. 8  is explained. The reception signal line selection circuit  82  ( 77 ) has eight (eight lanes) multiplexers  820 - 0 ˜ 820 - 7  that select one among four inputs (reception data from four lanes) and delay circuits (buffers)  822 - 0 ˜ 822 - 7 . Four inputs of each multiplexers  820 - 0 ˜ 820 - 3  are defined from top of the Figure, as below. 
         [0110]    (1) first signal line (lane) that is utilized at the time of x 8  link, x 4  link  1  and  2 , and x 4  link 2  of the lane reversal applied. 
         [0111]    (2) second signal line (lane) that is utilized at the time of x 4  link  1 . 
         [0112]    (3) third signal line (lane) that is utilized at the time of x 4  link 1  of the lane reversal applied. 
         [0113]    (4) fourth signal line (lane) that is utilized at the time of x 4  link 2  and x 8  link and x 4  link 1  and x 4  link 2  of the lane reversal applied. 
         [0114]    And four inputs of each multiplexers  820 - 4 - 820 - 7  are defined from top of the Figure, as below. 
         [0115]    (1) first signal line (lane) that is utilized at the time of x 8  link and x 4  link  1 . 
         [0116]    (2) second signal line (lane) that is utilized at the time of x 4  link  1  and x 4  link 2  and x 4  link  2  of the lane reversal applied. 
         [0117]    (3) third signal line (lane) that is utilized at the time of x 4  link  2  and x 4  link 1  and  2  of the lane reversal applied. 
         [0118]    (4) fourth signal line (lane) that is utilized at the time of x 8  link, x 4  link 1  of the lane reversal applied. 
         [0119]    For example, in the first multiplexer  820 - 0 , the input ( 1 ) is the lane# 0 , the input ( 2 ) is the lane# 4 , the input ( 3 ) is the lane# 3  and the input ( 4 ) is the lane # 7 . As control signals, the link construction instruction, the lane select signals (x 8  link, x 4  link 1  and the lane_slct  0 _ 4 ,  1 _ 5 ,  2 _ 6  and  3 _ 7  and x 4  link 2  and the lane_slct  0 _ 7 ,  1 _ 6 ,  2 _ 5  and  3 _ 4 ), and the lane reversal instruction signal from the signal line control unit are input to all multiplexers  820 - 0 ˜ 820 - 7 . 
         [0120]    According to these control signals, eight multiplexers  820 - 0 ˜ 820 - 7  select the input ( 1 ) and outputs it to the delay circuits  822 - 0 ˜ 822 - 7  respectively when x 8  link construction instruction is ‘1’ and the lane reversal instruction signal that instructs the lane reversal is ‘0’ (not applied). And the eight multiplexers  820 - 0 ˜ 820 - 7  select the input ( 4 ) and outputs it to the delay circuit  822 - 0 ˜ 822 - 7  respectively when x 8  link construction instruction is ‘1’ and the lane reversal instruction signal that instructs the lane reversal is ‘1’ (applied). 
         [0121]    In the eight multiplexers  820 - 0 ˜ 820 - 7 , four multiplexers are selected by the lane select signal lane_slct  0 _ 4 ,  1 _ 5 ,  2 _ 6 ,  3 _ 7  when x 4  link 1  construction instruction is ‘1’. 
         [0122]    The selected four multiplexers select the inputs ( 1 ) or ( 2 ) and output it when the lane reversal instruction signal that instructs the lane reversal is ‘0’ (not applied). And the selected four multiplexers select the inputs ( 3 ) or ( 4 ) and output it when the lane reversal instruction signal that instructs the lane reversal is ‘1’ (applied). 
         [0123]    In the eight multiplexers  820 - 0 ˜ 820 - 7 , four multiplexers are selected by the lane select signal lane_slct  0 _ 7 ,  1 _ 6 ,  2 _ 5 ,  3 _ 4  when x 4  link 2  construction instruction is ‘1’. 
         [0124]    The selected four multiplexers, for example the multiplexers  820 - 0 ˜ 820 - 3  select the inputs ( 1 ) or ( 4 ) and outputs it when the lane reversal instruction signal that instructs the lane reversal is ‘0’ (not applied). And in the selected four multiplexers, the multiplexers  820 - 0 ˜ 820 - 3  select the inputs ( 1 ) or ( 4 ) and the multiplexers  730 - 4 - 730 - 7  select the inputs ( 2 ) or ( 3 ) and output it when the lane reversal instruction signal that instructs the lane reversal is ‘1’ (applied). 
         [0125]    The delay circuits  822 - 0 ˜ 822 - 7  latch the outputs of each multiplexers  820 - 0 ˜ 820 - 7  by the reception timing signal. 
         [0126]    As a comparative example, the construction of the signal line control unit  104 , the sending signal line selection unit  102  and the reception signal line selection unit  202  of another related art explained in  FIG. 22 ,  FIG. 23  and  FIG. 24  will be explained by using  FIG. 9 ,  FIG. 10  and  FIG. 11 . In  FIG. 9 , the failure detection unit  208  maintains the lane 0  ok signal˜lane 7  ok signal to high level (“1”) when the failure detection unit  208  does not detect failures of each lane # 0 ˜# 7 , and changes the lane ok signal of the lane which is detected the failure to low level (“0”) when detecting the failure of the lane. 
         [0127]    In  FIG. 9 , the signal line control unit  104  has a pair no-failure detection circuit  110  that outputs a signal indicating no-failure of both pair signal lines of each of the lane groups [# 0 , # 1 ], [# 2 , # 3 ], [# 4 , # 5 ] and [# 6 , # 7 ] and four AND circuits  112 - 0 ˜ 112 - 3  that each arithmetic calculates a logical product of the lane 0  ok signal˜lane 7  ok signal of the lane groups [# 0 , # 1 ], [# 2 , # 3 ], [# 4 , # 5 ] and [# 6 , # 7 ]. 
         [0128]    An eight link/four link selection circuit  120  has a first AND circuit  122  that arithmetic calculates a logical product of the outputs of four AND circuits  112 - 0 ˜ 112 - 3  and outputs x 8  link signal that instructs x 8  link construction. And the eight link/four link selection circuit  120  has six AND circuits  124 - 0 ˜ 124 - 5  that each arithmetic calculates a logical product of two outputs of four AND circuits  112 - 0 ˜ 112 - 3  and outputs six combination signal for x 4  link selection, a second AND circuit  126 - 0  that arithmetic calculates a logical product of a reverse signal of the output from the first AND circuit  122  and the output signal of the AND circuit  124 - 0 , and a third AND circuit  126 - 1  that arithmetic calculates a logical product of a reverse signal of the output from the first AND circuit  122  and the output signal of the AND circuit  124 - 1 . 
         [0129]    Further, the eight link/four link selection circuit  120  has a first four input type AND circuit  126 - 2  that arithmetic calculates a logical product of a reverse signal of the output from the first AND circuit  122 , reverse signals of the outputs from the second and third AND circuits  124 - 0 ,  124 - 1  and the output signal of the AND circuit  124 - 2 , a second four input type AND circuit  126 - 3  that arithmetic calculates a logical product of a reverse signal of the output from the first AND circuit  122 , reverse signals of the outputs from the second and third AND circuits  124 - 0 ,  124 - 1  and the output signal of the AND circuit  124 - 3 , a third four input type AND circuit  126 - 4  that arithmetic calculates a logical product of a reverse signal of the output from the first AND circuit  122 , reverse signals of the outputs from the second and third AND circuits  124 - 0 ,  124 - 1  and the output signal of the AND circuit  124 - 4 , and a fourth four input type AND circuit  126 - 5  that arithmetic calculates a logical product of a reverse signal of the output from the first AND circuit  122 , reverse signals of the outputs from the second and third AND circuits  124 - 0 ,  124 - 1  and the output signal of the AND circuit  124 - 5 . 
         [0130]    By this construction, as explained in  FIG. 23 , six way four link width construction instructions B˜G are output. That is, x 8  link construction is instructed when all signal lines are not failed, because “x 8 _link” signal is “1”, “x 4 _link — 0123” signal is “0”, “x 4 _link — 4567” signal is “0”, “x 4 _link — 0145” signal is “0”, “x 4 _link — 2367” signal is “0”, “x 4 _link — 0167” signal is “0”, “x 4 _link — 2345” signal is “0”. 
         [0131]    When the signal line is occurred a failure, x 4  link construction of the lane group [# 0 ˜# 3 ] is instructed when the lane group [# 0 ˜# 3 ] are not failed, because “x 8 _link” signal is “0”, “x 4 _link — 0123” signal is “1”, “x 4 _link — 4567” signal is “0”, “x 4 _link — 0145” signal is “0”, “x 4 _link — 2367” signal is “0”, “x 4 _link — 0167” signal is “0”, “x 4 _link — 2345” signal is “0”. While, x 4  link construction of the lane [# 4 ˜# 7 ] is instructed when the lane group [# 4 ˜# 7 ] are not failed, because “x 8 _link” signal is “0”, “x 4 _link — 0123” signal is “0”, “x 4 _link — 4567” signal is “1”, “x 4 _link — 0145” signal is “0”, “x 4 _link — 2367” signal is “0”, “x 4 _link — 0167” signal is “0”, “x 4 _link — 2345” signal is “0”. 
         [0132]    When further failure occurs and above link construction cannot be realized, x 4  link construction of the lane group [# 0 , # 1 , # 4 , # 5 ] is instructed when the lane group [# 0 , # 1 , # 4 , # 5 ] are not failed, because “x 8 _link” signal is “0”, “x 4 _link — 0123” signal is “0”, “x 4 _link — 4567” signal is “0”, “x 4 _link — 0145” signal is “1”, “x 4 _link — 2367” signal is “0”, “x 4 _link — 0167” signal is “0”, “x 4 _link — 2345” signal is “0”. 
         [0133]    While, when the lane group [# 2 , # 3 , # 6 , # 7 ] are not failed, x 4  link construction of the lane group [# 2 , # 3 , # 6 , # 7 ] is instructed, because “x 8 _link” signal is “0”, “x 4 _link — 0123” signal is “0”, “x 4 _link — 4567” signal is “0”, “x 4 _link — 0145” signal is “0”, “x 4 _link — 2367” signal is “1”, “x 4 _link — 0167” signal is “0”, “x 4 _link — 2345” signal is “0”. 
         [0134]    And when the lane group [# 0 , # 1 , # 6 , # 7 ] are not failed, x 4  link construction of the lane group [# 0 , # 1 , # 6 , # 7 ] is instructed, because “x 8 _link” signal is “0”, “x 4 _link — 0123” signal is “0”, “x 4 _link — 4567” signal is “0”, “x 4 _link — 0145” signal is “0”, “x 4 _link — 2367” signal is “0”, “x 4 _link — 0167” signal is “1”, “x 4 _link — 2345” signal is “0”. 
         [0135]    Further, when the lane group [# 2 , # 3 , # 4 , # 5 ] are not failed, x 4  link construction of the lane group [# 2 , # 3 , # 4 , # 5 ] is instructed, because “x 8 _link” signal is “0”, “x 4 _link — 0123” signal is “0”, “x 4 _link — 4567” signal is “0”, “x 4 _link — 0145” signal is “0”, “x 4 _link — 2367” signal is “0”, “x 4 _link — 0167” signal is “0”, “x 4 _link — 2345” signal is “1”. 
         [0136]    Next, the signal line selection circuit for realize above link construction is explained by using  FIG. 10  and  FIG. 11 . In  FIG. 10 , the signal line selection  102  has four first multiplexers having four inputs and four second multiplexers having eight inputs. Four inputs of each first multiplexers  102 - 0 ,  102 - 1 ,  102 - 6  and  102 - 7  are defined from top of the Figure, as below. 
         [0137]    (1) first signal line (lane) that is utilized at the time of x 8  link and x 4  link. 
         [0138]    (2) second signal line (lane) that is utilized at the time of x 4  link. 
         [0139]    (3) third signal line (lane) that is utilized at the time of x 4  link of the lane reversal applied. 
         [0140]    (4) fourth signal line (lane) that is utilized at the time of x 8  link and x 4  link of the lane reversal applied. 
         [0141]    And eight inputs of each multiplexers  102 - 2 ˜ 102 - 5  are defined from top of the Figure, as below. 
         [0142]    (1) first signal line (lane) that is utilized at the time of x 8  link and x 4  link. 
         [0143]    (2)˜(4) second signal lines (lanes) that are utilized at the time of x 4  link. 
         [0144]    (5)˜(7) third signal lines (lanes) that are utilized at the time of x 4  link of the lane reversal applied. 
         [0145]    (8) fourth signal line (lane) that is utilized at the time of x 8  link and x 4  link of the lane reversal applied. 
         [0146]    In  FIG. 11 , the reception signal line selection unit  202  has eight multiplexers having six inputs. The six inputs of each multiplexers  202 - 0 ˜ 202 - 7  are defined from top of the Figure, as below. 
         [0147]    (1) first signal line (lane) that is utilized at the time of x 8  link and x 4  link. 
         [0148]    (2)˜(3) second signal lines (lanes) that are utilized at the time of x 4  link. 
         [0149]    (4)˜(5) third signal lines (lanes) that are utilized at the time of x 4  link of the lane reversal applied. 
         [0150]    (6) fourth signal line (lane) that is utilized at the time of x 8  link and x 4  link of the lane reversal applied. 
         [0151]    As illustrated in  FIG. 11 , furthermore, the reception signal line selection unit  202  has delay (buffer) circuits for receiving the outputs of the multiplexers  203 - 0 ˜ 203 - 7 . 
         [0152]    By above construction of the related art, the reduction is performed according to the description in  FIG. 23  and  FIG. 24  and x 4  link can be constructed even though any two lanes are failed. However, large sized multiplexers are required in the signal line selection units  102  and  202  and a delay time is long. That is, for both sending and reception, four multiplexers  102 - 2 ˜ 102 - 5  having eight inputs and eight multiplexers  202 - 0 ˜ 202 - 7  having six inputs are required. Further, when operating in a high operating frequency, the timing adjustment is required by inserting a flip-flop circuit of one stage. 
         [0153]    In contrary, in this embodiment, it is possible to construct both the signal line selection circuits  72  ( 87 ) and  82  ( 77 ) by four-input type multiplexer. Therefore, a circuit scale becomes small and this embodiment contributes a compact of a LSI (Large Scale Integrated circuit). 
         [0154]    (A Second Embodiment of the Data Transfer Control Device) 
         [0155]      FIG. 12  illustrates a circuit diagram of the signal line control unit  75  ( 85 ) according to a second embodiment in  FIG. 2 .  FIG. 13  illustrates a circuit diagram of the sending signal line selection unit  72  ( 87 ) in  FIG. 2 .  FIG. 14  illustrates a circuit diagram of the reception signal line selection unit  82  ( 77 ) in  FIG. 2 .  FIGS. 12-14  illustrate an example of four signal lines. Accordingly, the link construction has x 4  link construction and x 2  link construction at reduction. 
         [0156]    In  FIG. 12 , the signal line control unit  75  ( 85 ) has a first circuit  740  that instructs the x 4  (four) link construction when judging that all signal lines are not failed, a second circuit  750  that instructs the x 2  (two) link construction when judging that any one lane is or both lanes are not failed in each of the lane group [# 0 , # 2 ] and the lane group [# 1 , # 3 ] and a third circuit  760  that instructs the x 2  (two) link construction when judging that any one lane is or both lanes are not failed in each of the lane group [# 0 , # 3 ] and the lane group [# 1 , # 2 ]. 
         [0157]    The failure detection circuit  79  ( 89 ) as illustrated in  FIG. 2  becomes the lane 0  ok˜lane 3  ok signals to high level (“1”) when not detecting the failure of each lanes # 0 ˜# 3 , and becomes the lane ok signal of the lane that is detected the failure to low level (“0”) when detecting the failure of the lanes # 0 ˜# 3 . 
         [0158]    The first circuit  740  has a AND circuit that arithmetic calculates a logical product of the lane 0  ok signal˜the lane 3  ok signal. The second circuit  750  has a first OR circuit  752 - 0  that arithmetic calculates a logical sum of the lane 0  ok signal and the lane 2  ok signal of the lane group [# 0 , # 2 ], a second OR circuit  752 - 1  that arithmetic calculates a logical sum of the lane 1  ok signal and the lane 3  ok signal of the lane group [# 1 , # 3 ], and a AND circuit  754  that arithmetic calculates a logical product of the outputs from two OR circuits  752 - 0 ˜ 752 - 1 . 
         [0159]    The second circuit  750  has a AND circuit  756  that arithmetic calculates a logical product of the output from the AND circuit  754  and a reverse signal of the x 4  (four) link signal that instructs the x 4  (four) link construction from the first circuit  740  and outputs x 2  link 1  signal that instructs x 2  link construction, and two AND circuits  758 - 0 ˜ 758 - 1  that each arithmetic calculates a logical product of the output of the AND circuit  754 , a reverse signal of the lane 0  ok signal of the lane# 0  and a reverse signal of the lane 1  ok signal of the lane# 1 . 
         [0160]    Accordingly, the second circuit  750  outputs x 2  link construction instruction from the AND circuit  756  and the lane select signals (lane_slct  0 _ 2  and  1 _ 3 ) in x 2  link construction from the two AND circuits  758 - 0 ˜ 758 - 1  when one lane is failed. That is, when two outputs of the two AND circuits  758 - 0 ˜ 758 - 1  are ‘0’, selections of the lanes # 0  and # 1  are instructed. And when the outputs of the two AND circuits  758 - 0 ˜ 758 - 1  are ‘1’, selections of the lanes # 2  and # 3  are instructed. 
         [0161]    The third circuit  760  has, as same as the second circuit  750 , a first OR circuit  762 - 0  that arithmetic calculates a logical sum of the lane 0  ok signal and the lane 3  ok signal of the lane group [# 0 , # 3 ], a second OR circuit  762 - 1  that arithmetic calculates a logical sum of the lane 1  ok signal and the lane 2  ok signal of the lane group [# 1 , # 2 ], and a AND circuit  764  that arithmetic calculates a logical product of the outputs from two OR circuits  762 - 0 ˜ 762 - 1 . 
         [0162]    The third circuit  760  has a AND circuit  766  that arithmetic calculates a logical product of the output from the AND circuit  764 , a reverse signal of the x 4  (four) link signal that instructs the x 4  (four) link construction from the first circuit  740  and x 2  link  1  signal that instructs x 2  link construction from the AND circuit  756 , and outputs x 2  link 2  signal that instructs x 2  link construction, and two AND circuits  768 - 0 ˜ 768 - 1  that each arithmetic calculates a logical product of the output of the AND circuit  764  and a reverse signal of the lane 0  ok signal of the lane# 0 , a reverse signal of the lane 1  ok signal of the lane# 1 . 
         [0163]    Accordingly, the third circuit  760  outputs x 2  link construction instruction from the AND circuit  766  and the lane select signals (lane_slct  0 _ 3  and  1 _ 2 ) in x 2  link construction from the two AND circuits  768 - 0 ˜ 768 - 1  when x 2  link  1  construction cannot be constructed and the x 2  link  2  construction can be constructed. That is, when all the outputs of the two AND circuits  768 - 0 ˜ 768 - 1  are ‘0’, the two AND circuits  768 - 0 ˜ 768 - 1  instruct selections of the lanes # 0 , # 1 . And when all the outputs of the two AND circuits  768 - 0 ˜ 768 - 1  are ‘1’, the two AND circuits  768 - 0 ˜ 768 - 1  instruct selections of the lanes # 3  and # 2 . 
         [0164]    By this construction, x 4  link construction is instructed when all signal lines (lanes) are not failed, because of the signal “x 4 _link”=1, signal “x 2 _link_ 1 ”=0 and the signal “x 2 _link_ 2 ”=0. And when any signal line is failed, x 2  Link construction is instructed when any one or both signal lines of each lane group [# 0 , # 2 ] and [# 1 , # 3 ] is or are not failed, because of the signal “x 4 _link”=0, signal “x 2 _link_ 1 ”=1 and the signal “x 2 _link_ 2 ”=0. 
         [0165]    Further, when the x 2  link construction cannot be constructed by occurring a failure of the signal line in above x 2  link construction, x 2  Link construction is instructed when any one or both signal lines of each lane group [# 0 , # 3 ] and [# 1 , # 2 ] is or are not failed, because of the signal “x 4 _link”=0, signal “x 2 _link_ 1 ”=0 and the signal “x 2 _link_ 2 ”=1. Here, in this embodiment, young number lane is selected when both lanes of the group are not failed. 
         [0166]    Next, the sending signal line selection circuit  72  ( 87 ) in  FIG. 13  is explained. The sending signal line selection circuit  72  ( 87 ) has four (four lanes) multiplexers  770 - 0 ˜ 770 - 3  that select one among four inputs (sending data). Four inputs of each multiplexers  770 - 0 ˜ 770 - 1  are defined from top of the Figure, as below. 
         [0167]    (1) first data that is utilized at the time of x 4  link, x 2  link  1 , x 2  link  2  and x 2  link 2  of the lane reversal applied. 
         [0168]    (2) second data that is utilized at the time of x 2  link  1 , x 2  link  2 , and x 2  link 2  of the lane reversal applied. 
         [0169]    (3) third data that is utilized at the time of x 2  link 1  of the lane reversal applied. 
         [0170]    (4) fourth data that is utilized at the time of x 4  link and x 2  link 1  of the lane reversal applied. 
         [0171]    And four inputs of each multiplexers  770 - 2 ˜ 770 - 3  are defined from top of the Figure, as below. 
         [0172]    (1) first data that is utilized at the time of x 4  link and x 2  link 1 . 
         [0173]    (2) second data that is utilized at the time of x 2  link  1 . 
         [0174]    (3) third data that is utilized at the time of x 2  link  2  and x 2  link 1  and  2  of the lane reversal applied. 
         [0175]    (4) fourth data that is utilized at the time of x 2  link  2  and x 4  link, x 2  link 1  and x 2  link 2  of the lane reversal applied. 
         [0176]    For example, in the first multiplexer  770 - 0 , the input ( 1 ) is data D 0 , the input ( 2 ) is data D 2 , the input ( 3 ) is data D 1  and the input ( 4 ) is data D 3 . As control signals, the link construction instruction, the lane select signals (x 4  link, x 2  link 1  and the lane_slct  0 _ 2 ,  1 _ 3  and x 2  link 2  and the lane_slct  0 _ 3 ,  1 _ 2 ), sending timing signal at x 2  link and the lane reversal instruction signal from the signal line control unit are input to all multiplexers  770 - 0 ˜ 770 - 3 . 
         [0177]    According to these control signals, four multiplexers  770 - 0 ˜ 770 - 3  select the input ( 1 ) and simultaneously outputs it to the four lanes  0 ˜ 3  when x 4  link construction instruction is ‘1’ and the lane reversal instruction signal that instructs the lane reversal is ‘0’ (not applied). And the four multiplexers  770 - 0 ˜ 770 - 3  select the input ( 4 ) and simultaneously outputs it to the four lanes  0 ˜ 3  when x 4  link construction instruction is ‘1’ and the lane reversal instruction signal that instructs the lane reversal is ‘1’ (applied). 
         [0178]    In the four multiplexers  770 - 0 ˜ 770 - 3 , two multiplexers are selected by the lane select signal lane_slct  0 _ 2 ,  1 _ 3  when x 2  link 1  construction instruction is ‘1’ 
         [0179]    The selected two multiplexers select the inputs ( 1 ) and ( 2 ) and sequentially outputs it to the lane according to the sending timing signal when the lane reversal instruction signal that instructs the lane reversal is ‘0’ (not applied). And the selected two multiplexers select the inputs ( 3 ) and ( 4 ) and sequentially output it to the lane according to the sending timing signal when the lane reversal instruction signal that instructs the lane reversal is ‘1’ (applied). 
         [0180]    In the four multiplexers  770 - 0 ˜ 770 - 3 , two multiplexers are selected by the lane select signal lane_slct  0 _ 3 ,  1 _ 2  when x 2  link 2  construction instruction is ‘1’ 
         [0181]    In the selected two multiplexers, the multiplexers  770 - 0 ˜ 770 - 1  select the inputs ( 1 ) and ( 2 ) or the multiplexers  770 - 2 ˜ 770 - 3  select the inputs ( 3 ) and ( 4 ) and sequentially outputs it to the lane according to the sending timing signal when the lane reversal instruction signal that instructs the lane reversal is ‘0’ (not applied). And in the selected two multiplexers, the multiplexers  770 - 0 ˜ 770 - 1  select the inputs ( 1 ) and ( 2 ) or the multiplexers  770 - 2 ˜ 770 - 2  select the inputs ( 3 ) and ( 4 ) and sequentially output it to the lane according to the sending timing signal when the lane reversal instruction signal that instructs the lane reversal is ‘1’ (applied). 
         [0182]    Next, the reception signal line selection circuit  82  ( 77 ) in  FIG. 14  is explained. The reception signal line selection circuit  82  ( 77 ) has four (four lanes) multiplexers  840 - 0 ˜ 840 - 3  that select one among four inputs (reception data from four lanes) and delay circuits (buffers)  842 - 0 ˜ 842 - 3 . Four inputs of each multiplexers  840 - 0 ˜ 840 - 1  are defined from top of the Figure, as below. 
         [0183]    (1) first signal line (lane) that is utilized at the time of x 4  link, x 2  link  1  and x 2  link  2 , and x 2  link 2  of the lane reversal applied. 
         [0184]    (2) second signal line (lane) that is utilized at the time of x 2  link  1 . 
         [0185]    (3) third signal line (lane) that is utilized at the time of x 2  link 1  of the lane reversal applied. 
         [0186]    (4) fourth signal line (lane) that is utilized at the time of x 2  link 2  and x 4  link and x 2  link 1  and x 2  link 2  of the lane reversal applied. 
         [0187]    And four inputs of each multiplexers  840 - 2 ˜ 840 - 3  are defined from top of the Figure, as below. 
         [0188]    (1) first signal line (lane) that is utilized at the time of x 4  link and x 2  link  1 . 
         [0189]    (2) second signal line (lane) that is utilized at the time of x 2  link  1  and x 2  link 2  and x 2  link  2  of the lane reversal applied. 
         [0190]    (3) third signal line (lane) that is utilized at the time of x 2  link  2  and x 2  link 1  and  2  of the lane reversal applied. 
         [0191]    (4) fourth signal line (lane) that is utilized at the time of x 4  link, x 2  link 1  of the lane reversal applied. 
         [0192]    For example, in the first multiplexer  840 - 0 , the input ( 1 ) is the lane# 0 , the input ( 2 ) is the lane# 2 , the input ( 3 ) is the lane# 1  and the input ( 4 ) is the lane # 3 . As control signals, the link construction instruction, the lane select signals (x 4  link, x 2  link 1  and the lane_slct  0 _ 2 ,  1 _ 3  and x 2  link 2  and the lane_slct  0 _ 3 ,  1 _ 2 ), and the lane reversal instruction signal from the signal line control unit are input to all multiplexers  840 - 0 ˜ 840 - 3 . 
         [0193]    According to these control signals, four multiplexers  840 - 0 ˜ 840 - 3  select the input ( 1 ) and outputs it to the delay circuits  842 - 0 ˜ 842 - 3  respectively when x 4  link construction instruction is ‘1’ and the lane reversal instruction signal that instructs the lane reversal is ‘0’ (not applied). And the four multiplexers  840 - 0 ˜ 840 - 3  select the input ( 4 ) and outputs it to the delay circuit  842 - 0 ˜ 842 - 3  respectively when x 4  link construction instruction is ‘1’ and the lane reversal instruction signal that instructs the lane reversal is ‘1’ (applied). 
         [0194]    In the four multiplexers  840 - 0 ˜ 840 - 3 , two multiplexers are selected by the lane select signal lane_slct  0 _ 2 ,  1 _ 3  when x 2  link 1  construction instruction is ‘1’ 
         [0195]    The selected two multiplexers select the inputs ( 1 ) or ( 2 ) and output it when the lane reversal instruction signal that instructs the lane reversal is ‘0’ (not applied). And the selected two multiplexers select the inputs ( 3 ) or ( 4 ) and output it when the lane reversal instruction signal that instructs the lane reversal is ‘1’ (applied). 
         [0196]    In the four multiplexers  840 - 0 ˜ 840 - 3 , two multiplexers are selected by the lane select signal lane_slct  0 _ 3 ,  1 _ 2  when x 2  link 2  construction instruction is ‘1’ 
         [0197]    In the selected two multiplexers, when the multiplexers  840 - 0 ˜ 840 - 1  are selected, the multiplexers  840 - 0 ˜ 840 - 1  select the inputs ( 1 ) or ( 4 ) and when the multiplexers  840 - 2 - 840 - 3  are selected, the multiplexers  840 - 2 ˜ 840 - 3  select the inputs ( 2 ) or ( 3 ) and the selected multiplexers outputs it when the lane reversal instruction signal that instructs the lane reversal is ‘0’ (not applied). And in the selected two multiplexers, the multiplexers  820 - 0 ˜ 820 - 1  select the inputs ( 1 ) or ( 4 ) or the multiplexers  820 - 2 ˜ 820 - 3  select the inputs ( 2 ) or ( 3 ) and output it when the lane reversal instruction signal that instructs the lane reversal is ‘1’ (applied). 
         [0198]    The delay circuits  842 - 0 ˜ 842 - 3  latch the outputs of each multiplexers  840 - 0 ˜ 840 - 3  by the reception timing signal. 
         [0199]    In this four lane construction, as same as eight lane construction, it is possible to continue data transfer by reducing a half link width and to prevent that the size of the multiplexer becomes large. Therefore it is prevented that a circuit scale becomes large and it is possible to improve the operating frequency. 
         [0200]    (A Third Embodiment of the Data Transfer Control Device) 
         [0201]      FIG. 15  illustrates a circuit diagram of the signal line control unit  75  ( 85 ) according to a third embodiment in  FIG. 2 .  FIG. 16  illustrates a circuit diagram of the sending signal line selection unit  72  ( 87 ) according to a third embodiment in  FIG. 2 .  FIG. 17  illustrates a circuit diagram of the reception signal line selection unit  82  ( 77 ) according to a third embodiment in  FIG. 2 .  FIGS. 15-17  illustrate an example of twelve signal lines. 
         [0202]    In  FIG. 15 , the signal line control unit  75  ( 85 ) has a first circuit  772  that instructs the x 12  (twelve) link construction when judging that all signal lines are not failed, a second circuit  780  that instructs the x 6  (six) link construction when judging that any one lane is or both lanes are not failed in each of the lane groups [# 0 , # 6 ], [# 1 , # 7 ], [# 2 , # 8 ], [# 3 , # 9 ], [# 4 , # 10 ] and [# 5 , # 11 ] and a third circuit  796  that instructs the x 6  (six) link construction when judging that any one lane is or both lanes are not failed in each of the lane groups [# 0 , # 11 ], [# 1 , # 10 ], [# 2 , # 9 ], [# 3 , # 8 ], [# 4 , # 7 ] and [# 5 , # 6 ]. 
         [0203]    The failure detection circuit  79  ( 89 ) as illustrated in  FIG. 2  becomes the lane 0  ok˜lane 11  ok signals to high level (“1”) when not detecting the failure of each lanes # 0 ˜# 11 , and becomes the lane ok signal of the lane that is detected the failure to low level (“0”) when detecting the failure of the lanes # 0 ˜# 11 . 
         [0204]    The first circuit  772  has a AND circuit that arithmetic calculates a logical product of the lane 0  ok signal˜the lane 11  ok signal. The second circuit  780  has a first OR circuit  782 - 0  that arithmetic calculates a logical sum of the lane 0  ok signal and the lane 6  ok signal of the lane group [# 0 , # 6 ], a second OR circuit  782 - 2  that arithmetic calculates a logical sum of the lane 1  ok signal and the lane 7  ok signal of the lane group [# 1 , # 7 ], a third OR circuit  782 - 3  that arithmetic calculates a logical sum of the lane 2  ok signal and the lane 8  ok signal of the lane group [# 2 , # 8 ], a fourth OR circuit  782 - 4  that arithmetic calculates a logical sum of the lane 3  ok signal and the lane 9  ok signal of the lane group [# 3 , # 9 ], a fifth OR circuit  782 - 5  that arithmetic calculates a logical sum of the lane 4  ok signal and the lane 10  ok signal of the lane group [# 4 , # 10 ], a sixth OR circuit  782 - 6  that arithmetic calculates a logical sum of the lane 5  ok signal and the lane 11  ok signal of the lane group [# 5 , # 11 ], and a AND circuit  784  that arithmetic calculates a logical product of the outputs from six OR circuits  782 - 0 ,  782 - 2 ˜ 752 - 6 . 
         [0205]    The second circuit  780  has a AND circuit  786  that arithmetic calculates a logical product of the output from the AND circuit  784  and a reverse signal of the x 12  (twelve) link signal that instructs the x 12  (twelve) link construction from the first circuit  772  and outputs x 8  link 1  signal that instructs x 8  link construction, and six AND circuits  788 - 0 ˜ 788 - 5  that each arithmetic calculates a logical product of the output of the AND circuit  784 , a reverse signal of the lane 0  ok signal of the lane# 0 , a reverse signal of the lane 1  ok signal of the lane# 1 , a reverse signal of the lane 2  ok signal of the lane# 2 , a reverse signal of the lane 3  ok signal of the lane# 3 , a reverse signal of the lane 4  ok signal of the lane# 4  and a reverse signal of the lane 5  ok signal of the lane# 5 . 
         [0206]    Accordingly, the second circuit  780  outputs x 6  link construction instruction from the AND circuit  786  and the lane select signals (lane_slct  0 _ 6 ,  1 _ 7 ,  2 _ 8 ,  3 _ 9 ,  4 _ 10  and  5 _ 11 ) in x 6  link construction from the six AND circuits  788 - 0 ˜ 788 - 5  when one lane is failed. That is, when six outputs of the six AND circuits  788 - 0 ˜ 788 - 5  are ‘0’, selections of the lanes # 0 , # 1 , # 2 , # 3 , # 4  and # 5  are instructed. And when the outputs of the six AND circuits  788 - 0 ˜ 788 - 1  are ‘1’, selections of the lanes # 6 , # 7 , # 8 , # 9 , # 10  and # 11  are instructed. 
         [0207]    The third circuit  796  has, as same as the second circuit  780 , a first OR circuit  790 - 0  that arithmetic calculates a logical sum of the lane 0  ok signal and the lane 11  ok signal of the lane group [# 0 , # 11 ], a second OR circuit  790 - 1  that arithmetic calculates a logical sum of the lane 1  ok signal and the lane 10  ok signal of the lane group [# 1 , # 10 ], a third OR circuit  790 - 2  that arithmetic calculates a logical sum of the lane 2  ok signal and the lane 9  ok signal of the lane group [# 2 , # 9 ], a fourth OR circuit  790 - 3  that arithmetic calculates a logical sum of the lane 3  ok signal and the lane 8  ok signal of the lane group [# 3 , # 8 ], a fifth OR circuit  790 - 4  that arithmetic calculates a logical sum of the lane 4  ok signal and the lane 7  ok signal of the lane group [# 4 , # 7 ], a sixth OR circuit  790 - 5  that arithmetic calculates a logical sum of the lane 5  ok signal and the lane 11  ok signal of the lane group [# 5 , # 11 ], and a AND circuit  792 - 1  that arithmetic calculates a logical product of the outputs from six OR circuits  790 - 0 ˜ 790 - 5 . 
         [0208]    The third circuit  796  has a AND circuit  792 - 2  that arithmetic calculates a logical product of the output from the AND circuit  792 - 1 , a reverse signal of the x 12  (twelve) link signal that instructs the x 12  (twelve) link construction from the first circuit  772  and x 6  link  1  signal that instructs x 6  link construction from the AND circuit  786 , and outputs x 6  link 2  signal that instructs x 6  link construction, and six AND circuits  794 - 0 ˜ 794 - 5  that each arithmetic calculates a logical product of the output of the AND circuit  792 - 1  and a reverse signal of the lane 0  ok signal of the lane# 0 , a reverse signal of the lane 1  ok signal of the lane# 1 , a reverse signal of the lane 2  ok signal of the lane# 2 , a reverse signal of the lane 3  ok signal of the lane# 3 , a reverse signal of the lane 4  ok signal of the lane# 0 , a reverse signal of the lane 1  ok signal of the lane# 5 . 
         [0209]    Accordingly, the third circuit  796  outputs x 6  link construction instruction from the AND circuit  792 - 2  and the lane select signals (lane_slct  0 _ 11 ,  1 _ 10 ,  2 _ 9 ,  3 _ 8 ,  4 _ 7  and  5 _ 6 ) in x 6  link construction from the SIX AND circuits  794 - 0 ˜ 794 - 5  when x 6  link  1  construction cannot be constructed and the x 6  link  2  construction can be constructed. That is, when all the outputs of the six AND circuits  794 - 0 ˜ 794 - 5  are ‘0’, the six AND circuits  794 - 0 ˜ 794 - 5  instruct selections of the lanes # 0 , # 1 , # 2 , # 3 , # 4 , # 5 . And when all the outputs of the six AND circuits  794 - 0 ˜ 794 - 5  are ‘1’, the six AND circuits  794 - 0 ˜ 794 - 5  instruct selections of the lanes # 11 , # 10 , # 9 , # 8 , # 7  and # 6 . 
         [0210]    By this construction, x 12  link construction is instructed when all signal lines (lanes) are not failed, because of the signal “x 12 _link”=1, signal “x 6 _link_ 1 ”=0 and the signal “x 6 _link_ 2 ”=0. And when any signal line is failed, x 6  Link construction is instructed when any one or both signal lines of each lane group [# 0 , # 6 ], [# 1 , # 7 ], [# 2 , # 8 ], [# 3 , # 9 ], [# 4 , # 10 ] and [# 5 , # 11 ] is or are not failed, because of the signal “x 12 _link”=0, signal “x 6 _link_ 1 ”=1 and the signal “x 6 _link_ 2 ”=0. 
         [0211]    Further, when the x 6  link construction cannot be constructed by occurring a failure of the signal line in above x 6  link construction, x 6  Link construction is instructed when any one or both signal lines of each lane group [# 0 , # 11 ], [# 1 , # 10 ], [# 2 , # 9 ], [# 3 , # 8 ], [# 4 , # 7 ] and [# 5 , # 6 ] is or are not failed, because of the signal “x 12 _link”=0, signal “x 6 _link_ 1 ”=0 and the signal “x 6 _link_ 2 ”=1. Here, in this embodiment, young number lane is selected when both lanes of the group are not failed. 
         [0212]    Next, the sending signal line selection circuit  72  ( 87 ) in  FIG. 16  is explained. The sending signal line selection circuit  72  ( 87 ) has twelve (twelve lanes) multiplexers  798 - 0 ˜ 798 - 11  that select one among four inputs (sending data). Four inputs of each multiplexers  798 - 0 ˜ 798 - 5  are defined from top of the Figure, as below. 
         [0213]    (1) first data that is utilized at the time of x 12  link, x 6  link  1 , x 6  link  2  and x 6  link 2  of the lane reversal applied. 
         [0214]    (2) second data that is utilized at the time of x 6  link  1 , x 6  link  2 , and x 6  link 2  of the lane reversal applied. 
         [0215]    (3) third data that is utilized at the time of x 6  link 1  of the lane reversal applied. 
         [0216]    (4) fourth data that is utilized at the time of x 12  link and x 6  link 1  of the lane reversal applied. 
         [0217]    And four inputs of each multiplexers  798 - 6 ˜ 798 - 11  are defined from top of the Figure, as below. 
         [0218]    (1) first data that is utilized at the time of x 12  link and x 6  link 2 . 
         [0219]    (2) second data that is utilized at the time of x 6  link  2 . 
         [0220]    (3) third data that is utilized at the time of x 6  link  2  and x 6  link 1  and  2  of the lane reversal applied. 
         [0221]    (4) fourth data that is utilized at the time of x 6  link  2  and x 12  link, x 6  link 1  and x 6  link 2  of the lane reversal applied. 
         [0222]    For example, in the first multiplexer  798 - 0 , the input ( 1 ) is data D 0 , the input ( 2 ) is data D 6 , the input ( 3 ) is data D 5  and the input ( 4 ) is data D 11 . As control signals, the link construction instruction, the lane select signals (x 12  link, x 6  link 1  and the lane_slct  0 _ 6 ,  1 _ 7 ,  2 _ 8 ,  3 _ 9 ,  4 _ 10 ,  5 _ 11  and x 6  link 2  and the lane_slct  0 _ 11 ,  1 _ 10 ,  2 _ 9 ,  3 _ 8 ,  4 _ 7 ,  5 _ 6 ), sending timing signal at x 6  link and the lane reversal instruction signal from the signal line control unit are input to all multiplexers  798 - 0 ˜ 798 - 11 . 
         [0223]    According to these control signals, twelve multiplexers  798 - 0 ˜ 798 - 11  select the input ( 1 ) and simultaneously outputs it to the twelve lanes  0 ˜ 11  when x 12  link construction instruction is ‘1’ and the lane reversal instruction signal that instructs the lane reversal is ‘0’ (not applied). And the twelve multiplexers  798 - 0 ˜ 798 - 11  select the input ( 4 ) and simultaneously outputs it to the twelve lanes  0 ˜ 11  when x 12  link construction instruction is ‘1’ and the lane reversal instruction signal that instructs the lane reversal is ‘1’ (applied). 
         [0224]    In the twelve multiplexers  798 - 0 ˜ 798 - 11 , six multiplexers are selected by the lane select signal lane_slct  0 _ 6 ,  1 _ 7 ,  2 _ 8 ,  3 _ 9 ,  4 _ 10 ,  5 _ 11  when x 6  link 1  construction instruction is ‘1’. 
         [0225]    The selected six multiplexers select the inputs ( 1 ) and ( 2 ) and sequentially outputs it to the lane according to the sending timing signal when the lane reversal instruction signal that instructs the lane reversal is ‘0’ (not applied). And the selected six multiplexers select the inputs ( 3 ) and ( 4 ) and sequentially output it to the lane according to the sending timing signal when the lane reversal instruction signal that instructs the lane reversal is ‘1’ (applied). 
         [0226]    In the twelve multiplexers  798 - 0 ˜ 798 - 11 , six multiplexers are selected by the lane select signal lane_slct  0 _ 11 ,  1 _ 10 ,  2 _ 9 ,  3 _ 8 ,  4 _ 7 ,  5 _ 6  when x 6  link 2  construction instruction is ‘1’. 
         [0227]    In the selected six multiplexers, the multiplexers  798 - 0 ˜ 798 - 5  select the inputs ( 1 ) and ( 2 ) or the multiplexers  798 - 6 ˜ 798 - 11  select the inputs ( 3 ) and ( 4 ) and sequentially outputs it to the lane according to the sending timing signal when the lane reversal instruction signal that instructs the lane reversal is ‘0’ (not applied). And in the selected six multiplexers, the multiplexers  798 - 0 ˜ 798 - 5  select the inputs ( 1 ) and ( 2 ) or the multiplexers  798 - 6 ˜ 798 - 11  select the inputs ( 3 ) and ( 4 ) and sequentially output it to the lane according to the sending timing signal when the lane reversal instruction signal that instructs the lane reversal is ‘1’ (applied). 
         [0228]    Next, the reception signal line selection circuit  82  ( 77 ) in  FIG. 17  is explained. The reception signal line selection circuit  82  ( 77 ) has twelve (twelve lanes) multiplexers  850 - 0 ˜ 850 - 11  that select one among four inputs (reception data from four lanes) and delay circuits (buffers)  852 - 0 ˜ 852 - 11 . Four inputs of each multiplexers  850 - 0 ˜ 850 - 11  are defined from top of the Figure, as below. 
         [0229]    (1) first signal line (lane) that is utilized at the time of x 12  link, x 6  link  1  and x 6  link  2 , and x 6  link 2  of the lane reversal applied. 
         [0230]    (2) second signal line (lane) that is utilized at the time of x 6  link  1 . 
         [0231]    (3) third signal line (lane) that is utilized at the time of x 6  link 1  of the lane reversal applied. 
         [0232]    (4) fourth signal line (lane) that is utilized at the time of x 6  link 2  and x 12  link and x 6  link 1  and x 6  link 2  of the lane reversal applied. 
         [0233]    And four inputs of each multiplexers  850 - 6 ˜ 850 - 11  are defined from top of the Figure, as below. 
         [0234]    (1) first signal line (lane) that is utilized at the time of x 12  link, x 6  link  1  and x 6  link  2 . 
         [0235]    (2) second signal line (lane) that is utilized at the time of x 6  link  1  and x 6  link 2  and x 6  link  2  of the lane reversal applied. 
         [0236]    (3) third signal line (lane) that is utilized at the time of x 6  link  2  and x 6  link 1  and x 6  link 2  of the lane reversal applied. 
         [0237]    (4) fourth signal line (lane) that is utilized at the time of x 12  link, x 6  link 1  of the lane reversal applied. 
         [0238]    For example, in the first multiplexer  850 - 0 , the input ( 1 ) is the lane# 0 , the input ( 2 ) is the lane# 6 , the input ( 3 ) is the lane# 5 , and the input ( 4 ) is the lane # 11 . As control signals, the link construction instruction, the lane select signals (x 12  link, x 6  link 1  and the lane_slct  0 _ 6 ,  1 _ 7 ,  2 _ 8 ,  3 _ 9 ,  4 _ 10 ,  5 _ 11  and x 6  link 2  and the lane_slct  0 _ 11 ,  1 _ 10 ,  2 _ 9 ,  3 _ 8 ,  4 _ 7 ,  5 _ 6 ), and the lane reversal instruction signal from the signal line control unit are input to all multiplexers  850 - 0 ˜ 850 - 11 . 
         [0239]    According to these control signals, twelve multiplexers  850 - 0 ˜ 850 - 11  select the input ( 1 ) and outputs it to the delay circuits  850 - 0 ˜ 850 - 11  respectively when x 12  link construction instruction is ‘1’ and the lane reversal instruction signal that instructs the lane reversal is ‘0’ (not applied). And the twelve multiplexers  850 - 0 ˜ 850 - 11  select the input ( 4 ) and outputs it to the delay circuit  850 - 0 -˜ 850 - 11  respectively when x 12  link construction instruction is ‘ 1 ’ and the lane reversal instruction signal that instructs the lane reversal is ‘1’ (applied). 
         [0240]    In the twelve multiplexers  850 - 0 ˜ 850 - 11 , six multiplexers (lanes) are selected by the lane select signal lane_slct  0 _ 6 ,  1 _ 7 ,  2 _ 8 ,  3 _ 9 ,  4 _ 10 ,  5 _ 11  when x 6  link 1  construction instruction is ‘1’. 
         [0241]    The selected six multiplexers select the inputs ( 1 ) or ( 2 ) and output it when the lane reversal instruction signal that instructs the lane reversal is ‘0’ (not applied). And the selected six multiplexers select the inputs ( 3 ) or ( 4 ) and output it when the lane reversal instruction signal that instructs the lane reversal is ‘1’ (applied). 
         [0242]    In the six multiplexers  850 - 0 ˜ 850 - 11 , six multiplexers are selected by the lane select signal lane_slct  0 _ 11 ,  1 _ 10 ,  2 _ 9 ,  3 _ 8 ,  4 _ 7 ,  5 _ 6  when x 6  link 2  construction instruction is ‘1’. 
         [0243]    In the selected six multiplexers, when the multiplexers  850 - 0 ˜ 850 - 5  are selected, the multiplexers  850 - 0 ˜ 850 - 5  select the inputs ( 1 ) or ( 4 ) and when the multiplexers  850 - 6 ˜ 850 - 11  are selected, the multiplexers  850 - 6 ˜ 850 - 11  select the inputs ( 2 ) or ( 3 ) and the selected multiplexers outputs it when the lane reversal instruction signal that instructs the lane reversal is ‘0’ (not applied). And in the selected six multiplexers, the multiplexers  850 - 0 ˜ 850 - 5  select the inputs ( 1 ) or ( 4 ) or the multiplexers  850 - 6 ˜ 850 - 11  select the inputs ( 2 ) or ( 3 ) and output it when the lane reversal instruction signal that instructs the lane reversal is ‘1’ (applied). 
         [0244]    The delay circuits  852 - 0 ˜ 852 - 11  latch the outputs of each multiplexers  850 - 0 ˜ 850 - 11  by the reception timing signal. 
         [0245]    In this twelve lane construction, as same as eight lane construction, it is possible to continue data transfer by reducing a half link width and to prevent that the size of the multiplexer becomes large. Therefore it is prevented that a circuit scale becomes large and it is possible to improve the operating frequency. In this way, the embodiments are utilized that the lane width is 2N (N is integer). 
       The Other Embodiments 
       [0246]    In the above embodiments, the examples are described when a number of lane is four, eight and twelve. However, the invention is applied in case that a number of lane at reduction is a multiple of two, such as sixteen, twenty, twenty four, twenty eight, thirty two and thirty six. And the examples of data transfer of both sending and reception are described, but one of the sending and reception is applied. The reduction width may be applied to the link width of half or quarter if the transfer speed is within an allowable range. 
         [0247]    In this way, since a first circuit that creates a first selection signal indicating that any one or both signal line of a pair of reduction signal line and no-reduction signal line is or are not failed and a second circuit that creates a second selection signal indicating that any one or both signal line of a pair of signal lines, that is changed at lane reversal, is or are not failed, are provided, it is possible to continue data transfer by reducing a half link width even though two signal lines are failed and the lane reversal is executed. And it is possible to prevent that the size of the multiplexer becomes large. Therefore it is prevented that a circuit scale becomes large and it is possible to improve the operating frequency. 
         [0248]    All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.