Abstract:
A lateral Insulated Gate Bipolar Transistor (LIGBT) includes a semiconductor substrate and an anode region in the semiconductor substrate. A cathode region of a first conductivity type in the substrate is laterally spaced from the anode region, and a cathode region of a second conductivity type in the substrate is located proximate to and on a side of the cathode region of the first conductivity type opposite from the anode region. A drift region in the semiconductor substrate extends between the anode region and the cathode region of the first conductivity type. An insulated gate is operatively coupled to the cathode region of the first conductivity type and is located on a side of the cathode region of the first conductivity type opposite from the anode region. An insulating spacer overlies the cathode region of the second conductivity type. The lateral dimensions of the insulating spacer and the cathode region of the second conductivity type are substantially equal and substantially smaller than the lateral dimension of the cathode region of the first conductivity type.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation of application Ser. No. 11/564,948, filed Nov. 30, 2006, which is hereby incorporated by reference. 
     
    
     FIELD OF THE INVENTION 
       [0002]    This invention relates in general to semiconductor devices and more particularly to an integrated latch-up free insulated gate bipolar transistor. 
       BACKGROUND OF THE INVENTION 
       [0003]    The Insulated Gate Bipolar Transistor (IGBT) is an integrated combination of a bipolar transistor and a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and has become commercially successful due to its superior on-state characteristics, reasonable switching speed, and excellent safe-operating area. The typical lateral IGBT has a gate that is located laterally between the anode and cathode. (See, e. g., U.S. Pat. No. 4,963,951, issued Oct. 16, 1990, inventors Adler et al.; U.S. Pat. No. 5,654,561, issued Aug. 5, 1997, inventor Watabe; U.S. Pat. No. 5,869,850, issued Feb. 9, 1999, inventors Endo et al.). U.S. Pat. No. 6,528,849, issued Mar. 4, 2003, inventors Khemka et al., is of interest in disclosing a super junction dual gate lateral DMOSFET device 
         [0004]    Super junction Double Diffused Metal Oxide Semiconductor (DMOS) devices are desirable because they overcome the one dimension silicon device limits for high off-state breakdown voltage and low on-state resistance. In a super junction device, depletion regions are formed in the n and p pillars for high device breakdown voltage. The relatively high doping concentration of the n pillars (for an n channel MOSFET) can reduce device on-state resistance. However, because the p pillars occupy a significant percentage of the device drift area, they do not contribute to reducing device resistance in the on-state in MOSFETS. It would be desirable to have the super junction device designed so that the p pillars make a contribution to reduce the on-state device resistance (Ron). 
         [0005]    Lateral IGBTs (LIGBTs) are commonly used power devices for Power Integrated Circuit (PIC) applications because of their superior device characteristics. However, device latch-up, which leads to loss of gate control, may occur at high current due to the existence of the parasitic thyristor (n+ cathode/p−body/n−drift/p+ anode) in IGBT architecture. It therefore is desirable to make a virtually latch-up free IGBT. 
         [0006]    There is thus a need for a lateral IGBT device that has reduced on-state resistance and the parasitic npn of the device is never turned on in normal operation, and therefore the lateral IGBT device is effectively latch-up free. 
       SUMMARY OF THE INVENTION 
       [0007]    According to the present invention, there is provided a fulfillment of the needs and a solution to the problems discussed above. 
         [0008]    According to a feature of the present invention, there is provided a lateral insulated gate bipolar transistor (LIGBT) device, comprising: 
         [0009]    a semiconductor substrate; 
         [0010]    an anode region in said semiconductor substrate; 
         [0011]    a cathode region of a first conductivity type in said substrate laterally spaced from said anode region; 
         [0012]    a cathode region of a second conductivity type in said substrate located proximate to and on a side of said cathode region of said first conductivity type opposite from said anode region; 
         [0013]    a drift region in said semiconductor substrate between said anode region and said cathode region of said first conductivity type; 
         [0014]    an insulated gate operatively coupled to said cathode region of said first conductivity type located on a side of said cathode region of said first conductivity type opposite from said anode region; and 
         [0015]    an insulating spacer overlying said cathode region of said second conductivity type; 
         [0016]    wherein the lateral dimensions of said insulating spacer and said cathode region of said second conductivity type are substantially equal. 
         [0017]    According to another feature of the present invention there is provided a lateral insulated gate bipolar transistor (LIGBT) device, comprising: 
         [0018]    a p substrate; 
         [0019]    an n region formed on said p substrate; 
         [0020]    a p body region formed in said n region; 
         [0021]    an anode region; 
         [0022]    a p+ cathode region formed in said p body region laterally spaced from said anode region; 
         [0023]    an n+ cathode region formed in said p body region located proximate to and on a side of said p+ cathode region opposite from said anode region; 
         [0024]    a conductive layer formed on said p+ cathode region and coupled to said n+ cathode region; 
         [0025]    a drift region formed on said p substrate between said anode region and said p+ cathode region; 
         [0026]    an insulated gate operatively coupled to said p+ cathode region located on a side of said p+ cathode region opposite from said anode region; and 
         [0027]    an insulating spacer overlying said n+ cathode region; 
         [0028]    wherein the lateral dimensions of said insulating spacer and said n+ cathode region are substantially equal and substantially smaller than the lateral dimension of said p+ cathode region. 
         [0029]    According to still another feature of the present invention there is provided a process for making a lateral insulated gate bipolar transistor (LIGBT) device by: 
         [0030]    forming an anode region in an active region of a semiconductor substrate; 
         [0031]    forming a cathode region of a first conductivity type in said active region laterally spaced from said anode region; 
         [0032]    forming a cathode region of a second conductivity type in said active region located proximate to and on a side of said cathode region of said first conductivity type opposite from said anode region; 
         [0033]    forming a drift region in said active region between said anode region and said cathode region of said first conductivity type; 
         [0034]    forming an insulated gate operatively coupled to said cathode region of said first conductivity type and located on a side of said cathode region of said first conductivity type opposite from said anode region; and 
         [0035]    forming an insulating spacer overlying said cathode region of said second conductivity type; 
         [0036]    wherein the lateral dimensions of said insulating spacer and said cathode region of said second conductivity type are substantially equal. 
     
    
     
       DESCRIPTION OF THE DRAWINGS 
         [0037]    The aforementioned and other features, characteristics, advantages, and the invention in general will be better understood from the following more detailed description taken in conjunction with the accompanying drawings, in which: 
           [0038]      FIG. 1A  is a perspective, diagrammatic view showing an embodiment of the present invention; 
           [0039]      FIG. 1B  is a perspective, diagrammatic view showing another embodiment of the present invention; 
           [0040]      FIG. 1C  is a perspective, diagrammatic view showing another embodiment of the present invention; 
           [0041]      FIG. 2  is a sectional diagrammatic view showing a portion of the embodiment of  FIG. 1 ; 
           [0042]      FIGS. 3 and 4  are respective cross-sectional side and top diagrammatic views showing a portion of the embodiment of  FIG. 1 ; 
           [0043]      FIGS. 5A ,  5 B,  5 C, and  5 D are respective perspective diagrammatic views showing alternative anode region designs for the embodiment of  FIG. 1 ; 
           [0044]      FIG. 6  is a perspective diagrammatic view of another embodiment of the present invention; 
           [0045]      FIG. 7  is a graphical view showing forward conduction characteristics of three LIGBT devices and a LDMOS device; 
           [0046]      FIG. 8  is a graphical view showing reverse bias characteristics of the devices of  FIG. 8 ; 
           [0047]      FIG. 9  is a graphical view showing the forward conduction characteristics of the present invention; 
           [0048]      FIGS. 10A ,  10 B,  11 A,  11 B,  12 A,  12 B,  13 A,  13 B,  14 A, and  14 B are graphical views of hole vectors and electron vectors useful in explaining the operation of the present invention; and 
           [0049]      FIGS. 15A ,  15 B, and  15 C are sectional diagrammatic views showing the forming of the n+ cathode spacer shown in  FIG. 1 . 
       
    
    
       [0050]    It will be appreciated that for purposes of clarity and where deemed appropriate, reference numeral have been repeated in the figures to indicate corresponding features. Also, the relative size of various objects in the drawings has in some cases been distorted to more clearly show the invention. 
       DESCRIPTION OF THE INVENTION 
       [0051]    Referring now to  FIG. 1 , there is shown an embodiment  10  of a LIGBT device according to the present invention. As shown, the LIGBT device  10  includes a p− substrate  12  with an optional oxide layer  14  on top of the substrate  12 . The LIGBT device  10  also includes a buried n well region  16 , an n− epi region  18 , a p body  20 , a p− well  22 , a p+ cathode layer  24 , an n+ cathode spacer  26 , a gate  28 , a gate oxide  30 , an oxide spacer  32 , a cathode silicide layer  34 , a gate terminal  36 , a cathode terminal  38 , a super junction drift region  40 , an n well region  42 , a p+ anode  44 , an anode silicide layer  46 , and an anode terminal  48 . As can be seen in  FIG. 1A  the gate  28  is offset from the region between the cathode  34  and the anode  46 . As explained in more detail below, the offset gate along with the n+ cathode spacer  26  and the p regions  20 ,  22 ,  24 , and the tiny n+ cathode spacer  26  underneath the oxide spacer  32  greatly reduce the latch-up susceptibility of the LIGBT device  10 . 
         [0052]      FIG. 1B  is a perspective, diagrammatic view showing another embodiment  50  of the present invention in which the super junction drift region  40  has been replaced with a conventional RESURF drift region  52  which consists of the buried n well  16  and part of the n− epi region  18 . 
         [0053]      FIG. 1C  is a perspective, diagrammatic view showing another embodiment  60  of the present invention in which the buried n well region  16  has been replaced with a buried p well region  17  which can make n pillars easily depleted in the device off-state for higher device breakdown voltage, but with more current crowded in the n− epi  18  under the p regions  20 ,  22  inducing a little bit higher on-state resistance when compared to  FIG. 1A . 
         [0054]      FIG. 2  is an enlarged view of the upper left hand corner of  FIG. 1A  to better show the offset gate  28 , the silicide cathode  34 , the p body  20 , the p− well  22 , the p+ cathode layer  24 , and the n+ cathode spacer  26  along with first and second metal layers  60 . In the on-state the existence of the p body  20  and the p− well  22  facilitate the collection of holes by the p+ cathode layer  24  so that holes will have less tendency to flow through the area of the n+ cathode  26  which might otherwise cause device latch-up. The depletion region underneath the n+ cathode spacer  26  can also divert hole flow away from that region and reduces the number of holes that flow underneath the n+ cathode  26 . All of these allow the holes to be collected effectively by the p+ cathode  24  through the p body  20  and p− well  22  before reaching the n+ cathode  26 . Latch-up of device  10  is thereby effectively prevented during normal operation of the LIGBT device  10 . 
         [0055]    To further improve the latch-up characteristics the width of the n+ cathode spacer  26  is minimized. Preferably the lateral dimension of the n+ cathode region  26  is substantially smaller than the lateral dimension of the p+ cathode layer  24 . In the conventional process of forming an n+ cathode region the width is limited by the photolithography capability. As discussed below with respect to  FIGS. 15A ,  15 B, and  15 C the oxide spacer  32  is used as a hard mask to define the width of the n+ cathode spacer  26 . 
         [0056]    As diagrammatically shown in  FIGS. 3 and 4 , the super junction drift region  40  may be formed from one or more interleaved p and n pillars  48  and  50 , respectively, separated into two vertical sections  52  and  54  by a p− buried layer  56 . The upper section  52  has a p− top layer  58 , and the lower section  54  has a bottom layer of the oxide  14  in the embodiment shown in  FIG. 1A . The interleaved p and n pillars  48 ,  50  form multiple, stacked Junction Field Effect Transistors (JFETs)  60 ,  62  in the top section  52  and the bottom section  54 , respectively. 
         [0057]    When the LIGBT device  10  is in the forward conduction mode of operation when a positive voltage is applied to the p+ anode  46  relative to the p+ cathode layer  24 , when the voltage applied to the gate  28  is higher than the device threshold voltage, and when an anode voltage is higher than one diode drop with respect to the cathode voltage. Under these conditions, the p+ anode  44  pn junction injects holes into the n−pillars  50  and the p−pillars  48  of the super junction drift region  40 . Some of these holes will recombine with the electrons flowing in from the device channel in the n pillar regions  50  and modulate the conductivity in the n pillars  50  to reduce the n pillar resistance of the LIGBT device  10 . Some of the holes will flow through p pillars  48 , which cause the p pillars  48  to also make a contribution in reducing device resistance during the on-state of the LIGBT device  10 . Almost all of the holes will flow from the super junction drift region  40  (from both the n and the p pillars  50 ,  48 ) to the p body  20  and the p−well  22  and be collected by the p+ cathode layer  24  without flowing through the area of the n+ cathode spacer  26 . Thus, in normal operation of device  10  the holes do not cause latch-up of device  10 . 
         [0058]    When the LIGBT device  10  is reverse biased, the LIGBT device  10  operates like a conventional super junction device. In the super junction drift region  40 , depletion starts at the lateral pn junctions at the cathode and anode ends of the n and p pillars  50 ,  48 . All of the n and p pillars can be fully depleted to achieve a high device breakdown voltage. 
         [0059]      FIGS. 5A ,  5 B,  5 C, and  5 D show optional anode region designs.  FIG. 5A  shows the design used in the embodiment of  FIG. 1  and includes a p+ anode  44 , n− well region  42 , conductive silicide layer  46  and anode terminal  48 .  FIG. 5B  shows an anode design which includes interleaved n+ anode segments  66  and p+ anode segments  68 .  FIG. 5C  shows a silicided Schottky anode (which can also be segmented) including silicide layer  46  and n− type layer  70 .  FIG. 5D  shows the same anode region as  FIG. 5B  except that the n+ segments  74  have a larger cross-sectional area than the p+ segments  72 . 
         [0060]    The anode design of  FIG. 5A  produces the most hole injection of the four anode region designs. The hole injection modulates the conductivity of the super junction drift region  40  and provides the lowest on-state resistance. The anode design of  FIG. 5B  has n+ and p+ regions  66  and  68 , respectively, of equal cross sectional area and provides faster switching and a higher breakdown voltage of the anode design of  FIG. 5A . The anode design of  FIG. 5C  provides a faster switching than the anode region of  FIG. 5A . The anode region of  FIG. 5D , in which the area of the n+ segments  74  are 50% larger than the area of the p+ segments  72 , has faster switching than the anode region of  FIG. 5C . 
         [0061]      FIG. 6  shows a deep trench isolation design  80  with an SOI substrate  14  and deep trench isolation  82  that provides the best isolation but which is more expensive. An alternate substrate design is a p− substrate with p buried well and p+ sink isolation. The latter design offers less perfect isolation but is more economical. 
         [0062]      FIG. 7  is a simulated graphical view showing simulated forward conduction characteristics of three LIGBT devices and a LDMOS device having similar doping profiles and a drift length of 70 μm. Curve  90  shows the current-voltage forward conduction characteristics of an off-set gate LIGBT with n+ cathode spacer according to the invention; curve  92  shows the current-voltage forward conduction characteristics of an off-set gate with 1.5 μm n+ cathode; curve  94  shows the current-voltage forward conduction characteristics of a conventional LIGBT; and curve  96  shows the current-voltage forward conduction characteristics of a conventional LDMOS. The LDMOS (curve  96 ) has a much lower current handling capability as compared to the LIGBT devices, but is latch-up free. This is due to the lack of conductivity modulation in the LDMOS drift region, and the lack of a parasitic thyristor structure in the device. 
         [0063]    It is to be noted that the static latch-up current densities of the conventional LIGBT (curve  94 ) and the off-set gate LIGBT with an n+ cathode length of 1.5 μm (curve  92 ) are approximately 3 e-4 A/μm and over 7 e-4 A/μm, respectively. However, more importantly, effectively no latch-up occurs in the off-set gate LIGBT with the n+ cathode spacer according to the present invention (curve  90 ), even when the forward current density is greater than 1.7 e 3 A/μm, which exceeds the Si limitation for 600V-700V devices. Thus the off-set gate LIGBT with an n+ cathode spacer of the present invention has very high current handling capability and is also effectively free of latch-up. 
         [0064]      FIG. 8  shows the simulated reversed bias characteristics of the devices shown in  FIG. 7 . With a similar doping profile and the same drift length of 70 μm, the simulated breakdown voltage of the three LIGBTs tested in  FIG. 7  is approximately 640V, about 130V lower when compared to the LDMOS breakdown voltage of 770V. This is due to a parasitic pnp existing in LIGBT devices that can easily induce a leakage when the anode voltage is very high. The breakdown voltage of LIGBT devices can be increased by optimizing the n− buffer layer (located in the p+ anode area) to reduce the parasitic pnp beta. However, this needs to be traded off with process cost because one more buffer mask layer is needed. 
         [0065]      FIG. 9  shows the simulated forward conduction characteristics of the present invention with expanded current density and voltage ranges. As shown, no latch-up occurs even though the forward current density is greater than 2.8 e-3 A/μm, which exceeds the Si limitation for 600V-700V devices. Thus, the offset gate LIGBT with n+ cathode spacer of the present invention has very high current handling capability and is also effectively latch-up free. 
         [0066]      FIGS. 10A ,  10 B to  14 A,  14 B are simulated graphical views closer to the cathode and the gate area showing numerical analysis of latch-up useful in explaining the present invention.  FIGS. 10A ,  11 A and  12 A show hole vectors in the cathode region of the LIGBT of the present invention at current of 2 e-4 A/μm, 5 e-4 A/μm, and 1 e-3 A/μm, respectively. It will be noted that no hole vectors are found at the n+ cathode spacer even at a current of 1 e-3 A/μm, meaning that the n+ cathode/p−well diode did not turn on, with the result that no latch-up occurred.  FIGS. 10B ,  11 B, and  12 B show electron vectors at currents of 2 e-4 A/μm, 5 e-4 A/μm, and 1 e-3 A/μm, respectively. 
         [0067]      FIGS. 13A and 13B  show respective hole and electron vectors in a conventional LIGBT structure at a current of 2 e-4 A/μm. No hole vectors are found in the n+ cathode area, meaning that the n+ cathode/p−well diode did not turn on at that current and no latch-up occurred.  FIGS. 14A and 14B  show respective hole and electron vectors in a conventional LIGBT structure at a current of 5 e-4 A/μm. Injection of holes to the n+ cathode is obvious at a current of 5 e-4 A/μm, meaning that the n+ cathode/p− well diode did turn on and latch-up occurred. 
         [0068]      FIGS. 15A ,  15 B, and  15 C show the process steps which may be used to form the cathode region of LIGBT devices  10 ,  50 , and  60 . Shown in  FIG. 15A  is the n− epi layer  18  with a p− well  100  diffused therein. P body  104  and shallow n+  106  implanted regions are formed self-aligned to the gate poly  28  in the n− epi layer  18 . In  FIG. 15B  the p− well  100 , the p body  104  and the n+ implanted region  106  have been diffused out to form the p− well  22 , the p body  20  and an n+ layer  110 , respectively. After an oxide layer  108  deposition and the deposited oxide is anisotropically etched, the sidewall oxide  32  is left as shown in  FIG. 5C . Using the sidewall oxide  32  and the field oxide  102  as a mask, the p+ cathode layer  24  is formed leaving the portion of the n+ layer  110  under the gate  28  and the sidewall oxide  28  in place which is the n+ cathode spacer  26  shown in  FIGS. 1A ,  1 B,  1 C,  2 , and  6 . A portion of the p+ cathode layer  24  is converted to the silicide layer  34 . In the preferred embodiment the width of the n+ cathode spacer  26  is on the order of 0.05 to 0.3 μm. 
         [0069]    Although the invention has been described in detail with particular reference to certain preferred embodiments thereof, it will be understood that variations and modifications can be effected within the spirit and scope of the invention.