Abstract:
A voltage regulator provides a regulated output load voltage at either a positive level or an inverted level relative to an input supply voltage. A switching circuit and control circuit are formed on an integrated circuit having a single pin for coupling to regulator feedback signal. The feedback signal is applied directly to the feedback pin during both positive voltage level regulation and inverted voltage level regulation. The feedback signal may be produced by a feedback circuit comprising an impedance element formed in the integrated circuit.

Description:
TECHNICAL FIELD 
   The present disclosure relates to control of a voltage regulator, more particularly to a regulator that can be operated for positive or inverted voltage level regulation with the same feedback configuration. 
   BACKGROUND 
   Voltage converters are known that provide regulated output load voltages at levels above, at, or below nominal input supply voltages at the same or inverted polarity. Diagrams of two such known converters are broadly shown in  FIGS. 1A and 1B .  FIG. 1A  depicts a step-up, or boost, converter that includes an integrated circuit switching regulator such as, for example, the LT1930 produced by Linear Technology.  FIG. 1B  depicts an inverting converter that includes a switching regulator such as, for example, the LT1931 produced by Linear Technology, or equivalent. In each device, the switching regulator and control circuit therefor are incorporated in an integrated circuit chip  10 , which has a plurality of pins formed thereon for interfacing with external elements. 
   Each converter comprises an input capacitor  12 , coupled between voltage supply input node V IN  and ground, and an output capacitor  14  coupled between output node V OUT  and ground. The output node is coupled to a load to provide regulated voltage thereto. Resistors  16  and  18  are coupled in series between the output node and ground. The junction between resistors  16  and  18  provides a feedback voltage that is proportional to the load voltage. 
   The conversion functionality is dependent upon the configuration of the external elements and their connections with the pins of chip  10 . In the boost converter of  FIG. 1A , inductor  20  and diode  22  are coupled in series between the V IN  and V OUT  nodes. The junction between inductor  20  and diode  22  is coupled to a switch internal to the chip  10  via a pin SW. The feedback voltage is coupled to a switch control circuit internal to the chip  10  via a pin FB. In the inverting converter of  FIG. 1B , inductor  20  capacitor  24  and inductor  26  are coupled in series between the V IN  and V OUT  nodes. Diode  22  is coupled between the junction of capacitor  24  and inductor  26  and ground. Capacitor  28  is coupled in parallel with resistor  16 . The feedback voltage is coupled to via a pin NFB. 
   The integrated circuit chip  10  for both converters comprises similar, well-known, circuitry.  FIG. 2  is a partial block diagram that illustrates chip elements to the left of the dashed line area and typical external regulator elements represented by block  15 . Signal responsive switch  30  and resistor  32  are connected in series between inductor  20  and ground. The switch current I SW  is sensed at the junction between switch  30  and resistor  32 . Switch  30  is controlled by circuit  34 . When switch  30  is in a conductive state, current flows from source V IN  through inductor  20  and resistor  32  to ground. When the switch is turned off, energy stored in the inductor is transferred to the capacitor  14 . By appropriately timing the on and off states of the switch  30 , a regulated boost voltage is maintained at the output node of capacitor in the configuration of  FIG. 1A , or a regulated inverted voltage is maintained at the output node of capacitor in the configuration of  FIG. 1B . 
   Switching control circuit  34  typically comprises latch circuitry and switch driver circuitry. A set input is coupled to clock  36 , which may generate pulses in response to an oscillator. During normal operation, the latch is activated to initiate a switched current pulse when the set input receives each clock pulse. The switched current pulse is terminated when the reset input receives an input signal, thereby determining the width of the switched current pulse. The reset input is coupled to the output of comparator  38 . For boost regulation, output voltage feedback signal V FB  is coupled to a negative input of error amplifier  40 . A voltage reference V REF  is applied to the positive input of error amplifier  40 . Capacitor  42  is coupled between the output of error amplifier  40  and ground. 
   The level of charge of capacitor  42 , and thus its voltage V C , is varied in dependence upon the output of amplifier  40 . As load current increases, the output voltage, and thus V FB , decreases. As the feedback voltage V FB  decreases, V C  increases. Thus, V C  is proportional to load current. V C  is coupled to the inverting input of comparator  38 . The non-inverting input is coupled to adder  44 . Adder  44  combines signal I SW , which is proportional to the sensed switch current, with a compensation signal. Upon switch activation in response to a clock set signal, switch current builds through inductor  20 . When the level of the signal received from adder  44  exceeds V C , comparator  38  generates a reset signal to terminate the switched current pulse. During heavier loads, V C  increases and the switched current pulse accordingly increases in length to appropriately regulate the output voltage V OUT  at the boost level. Such operation is typical current mode control. Alternatively, duty cycle can be regulated in voltage mode control. 
   In the boost configuration of  FIG. 2 , the output voltage is a positive level and the positive feedback voltage V FB  is applied to the FB pin, shown in  FIG. 1A . For an inverting converter, the output voltage is a negative level and the negative feedback voltage V FB  is applied to the NFB pin, shown in  FIG. 1B . The feedback voltage is then changed in sign to a positive value and applied to the negative input of error amplifier  40 . Thus the elements, of a single integrated circuit chip, shown in  FIG. 2 , can be made operable for both boost and inverting regulation. 
   Traditional methods for implementing a single integrated circuit chip for use in either a boost or inverting voltage converter require the use of two or three pins of the chip. One conventional method is illustrated in  FIGS. 3A-3C .  FIG. 3A  depicts chip  10  with pins A, B and C illustrated. Pin A is permanently connected to voltage reference V REF , supplied by an external source. Pin B is connected internally to the positive input of error amplifier  40 . Pin C is connected internally to the negative input of error amplifier  40 . Additional connections are made externally to pins A, B and C to provide for the boost regulation configuration, as illustrated in  FIG. 3B , or the inverting regulation configuration, as illustrated in  FIG. 3C . 
   In the  FIG. 3B  arrangement, pins A and B are connected together externally. Thus V REF  is applied to the positive input of error amplifier  40 . Feedback voltage V FB , from the junction of resistors  16  and  18  is applied to the negative input of error amplifier  40  via pin C. This configuration is the same as that illustrated in  FIG. 2 . The output of error amplifier  40  will vary in accordance with the output load and the switch  30  is controlled accordingly. 
   In the  FIG. 3C  arrangement, pin C is connected externally to ground. Pin B is connected externally to the junction between resistors  16  and  18 . Resistors  16  and  18  are coupled in series across V REF , at resistor  16 , and −V OUT , at resistor  18 . When the load increases, the absolute value of V OUT  decreases, and thus the V C , output of error amplifier  40 , increases. The conductive period of the switch  30  is controlled to vary in accordance with load current in the same manner as in the boost operation. 
   Another known method for boost conversion and inverting conversion implementation is illustrated in  FIGS. 4A-4C .  FIG. 4A  depicts chip  10  with pins A and B illustrated. Pin A is connected internally to the negative input of error amplifier  40 . The positive input of error amplifier  40  is connected internally to ground. The output of error amplifier  40  is connected to the negative input of error amplifier  41  through diode  43 . Pin B is connected internally to the negative input of error amplifier  41 . The positive input of error amplifier  41  is connected to V REF , which may be generated internally within chip  10 . The output of error amplifier  41  produces voltage V C . 
     FIG. 4B  illustrates the external connections to pins A and B for the arrangement shown in  FIG. 4A  for boost converter operation. Pin A is externally connected to the junction of resistors  16  and  18 , which produces the feedback voltage V FB . Pins A and B are connected, externally, to each other. With this configuration, the feedback voltage V FB  is applied to the negative input of error amplifier  41  with V REF  applied at the positive input. V C  is output to vary with load, as in the operation of  FIG. 2 , described above. 
     FIG. 4C  illustrates the pin connections of the  FIG. 4A  arrangement for inverting operation. Pin A is externally connected to the junction of resistors  16  and  18 , which produces the feedback voltage V FB . Pin B is connected externally to the other end of resistor  18 . As V OUT  has negative polarity in inverting operation, V FB  is negative. Error amplifier  40  produces a positive output, which is applied via diode  43  to the negative input of error amplifier  41 . The absolute value of feedback voltage V FB , increases for lighter load currents and decreases for heavier load currents. When the input to pin A becomes more negative (lighter load), the output of error amplifier  40 , applied to the negative input of error amplifier  41 , increases to decrease the output V C  of error amplifier  41 . Thus V C  varies in correspondence with the increase and decrease of load current to obtain the same manner of regulation of switch  30  as in the operation of  FIG. 2 , described above. 
   The known arrangements require dedication of a plurality of IC pins to be externally reconfigured for operation as both boost and inverting conversion. The arrangement of  FIGS. 3A-3C  utilizes a single error amplifier, a permanent external connection of pin A to the reference voltage, and a reconfiguration of external connections to pins A through C when changing between boost and inverting converter operation. The arrangement of  FIGS. 4A-4C  utilizes two error amplifiers but still requires two pins for circuit reconfiguration when changing between boost and inverting converter operation. A need still exists for an integrated circuit switching regulator that needs no internal change for operation at either boost of inverting conversion while minimizing the number of pins needed to reconfigure operation. 
   SUMMARY OF THE DISCLOSURE 
   The subject matter described herein fulfills the above-described needs of the prior art. In one aspect, a voltage regulator can be configured to provide a regulated output load voltage at either a positive level or an inverted level relative to an input supply voltage. A feedback signal is derived that varies with load voltage. A control signal is generated that is variable proportionately with load current and is applied to control a switching circuit of the regulator. To generate the control signal, a control current is supplied from a current source to a control circuit of the switching circuit. The supplied current is diverted from the control circuit when the voltage of the feedback signal is greater than a positive reference voltage and when the voltage of the feedback signal is less than ground voltage. The switching circuit and the control circuit are formed on an integrated circuit having a single feedback pin. The feedback signal is applied directly to the feedback pin during both positive voltage level regulation and inverted voltage level regulation. The feedback signal may be produced by a feedback circuit comprising an impedance element formed in the integrated circuit. 
   Additional aspects and advantages will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiments are shown and described, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the disclosed concepts are applicable to other and different embodiments, and the disclosed details are capable of modifications in various obvious respects. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Implementations of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements. 
       FIGS. 1A and 1B  are diagrams of a known voltage regulator that can be configured as shown, respectively, for boost or inverting voltage regulation. 
       FIG. 2  is a partial block diagram that illustrates typical regulator elements that may be utilized in the voltage regulator of  FIGS. 1A and 1B . 
       FIGS. 3A-3C  are partial diagrams illustrative of a known method for implementing a single integrated circuit chip for use in either a boost or inverting voltage converter. 
       FIGS. 4A-4C  are partial diagrams illustrative of another known method for implementing a single integrated circuit chip for use in either a boost or inverting voltage converter. 
       FIG. 5  is a partial circuit diagram of a feedback control scheme for a voltage regulator capable of boost or inverting voltage conversion illustrative of the disclosed concepts. 
       FIG. 6  is a waveform of a transfer function from a feedback node to a control node in the circuit of  FIG. 5 . 
       FIG. 7  is a circuit diagram by which the scheme of  FIG. 5  may be implemented. 
   

   DETAILED DESCRIPTION 
   The feedback control scheme illustrated in  FIG. 5  is implemented in an integrated circuit chip  10 , indicated within the dash line border. Output voltage V OUT  is coupled via feedback resistor  16  to a chip pin to apply the feedback voltage V FB  thereto. The remainder of the elements illustrated are formed in the integrated circuit. Coupled in series between an internally generated voltage reference V REF  and ground are resistors  50  and  52 , which may be of equal resistance. The junction of resistors  50  and  52  is internally connected to the feedback pin. V REF  is connected to the positive input of error amplifier  40 . The negative input of error amplifier  40  is connected to the positive input of error amplifier  41 . The negative input of error amplifier  41  is connected to ground. The feedback pin is connected to the junction  51  between the negative input of error amplifier  40  and the positive input of error amplifier  41 . 
   Control signal line V C  is coupled to current source  54 . Error amplifier  40  is coupled to current source  54  through diode  56 , which is poled in a direction to draw current from the current source. Error amplifier  41  is coupled to current source  54  through diode  58 , which is poled in a direction to draw current from the current source. 
   In operation, V FB  is at a positive voltage level for boost voltage conversion and at a negative voltage level for inverting voltage conversion. During boost operation the positive input to error amplifier  41  is greater than its negative input, which is grounded. The output of error amplifier  41  thus will be high, turning off diode  58 . Error amplifier  41  is thus of no effect on V C  during boost operation. V FB , a function of feedback circuit resistors  16 ,  50  and  52 , is applied to the negative input of error amplifier  40 . 
   When V FB  is less than V REF , the output of error amplifier will be high to prevent conduction of current through diode  56 . This condition corresponds to high load current converter operation. The current of current source  54  is completely directed to V C . The switching regulator will deliver high current to the output in response to the resulting high level of V C . When the output voltage increases during low load conditions such that V FB  exceeds V REF , the output of error amplifier  40  will be negative, rendering diode  56  conductive. Current from current source  54  will be diverted to error amplifier  40 , thereby lowering the level of V C . In response, the switching regulator will deliver lower current to the output. Thus V C  will decrease in accordance with a decrease in load. The switching regulator functions in this manner in both current mode regulation and voltage mode regulation. 
   During inverting voltage conversion operation, V OUT  is at negative polarity. The positive input to error amplifier  40 , V REF , is greater than the feedback voltage, V FB , at its negative input. The output of error amplifier  40  thus will be high, turning off diode  56 . Error amplifier  40  is thus of no effect on V C  during inverting operation. During high load condition operation, the absolute value V OUT  is lower than the nominal regulated level. V FB  at the positive input to error amplifier  41  will be equal to or greater than its grounded negative input. The output of error amplifier  41  will be high to prevent conduction of current through diode  56 . The current of current source  54  is completely directed to V C . The switching regulator will deliver high current to the output in response to the resulting high level of V C . 
   During low load conditions, V OUT  becomes more negative such that voltage at the grounded negative input to error amplifier  41  exceeds the value of V FB  applied to its positive input. The output of error amplifier  41  will be negative to render diode  58  conductive. Current from current source  54  will be diverted to error amplifier  41 , thereby lowering the level of V C . In response, the switching regulator will deliver lower current to the output. 
   The internal resistor  52  can replace the external resistor, such as resistor  18 , conventionally used in a load feedback circuit. The circuit of  FIG. 5  provides for appropriate regulation in accordance with load conditions in both boost and inverting operations. In both operations, current applied to the V C  node by the feedback network is based on the resistance of internal resistors  50  and  52 , external resistance  16  and the value of V OUT . Only a single pin (V FB ) of the integrated circuit chip is necessary for implementing selection between boost converter or inverting converter operation. 
     FIG. 6  is a waveform of a transfer function from the feedback node V FB  to the V C  node in the circuit of  FIG. 5 . The Y axis represents the voltage or current level at line V C . The X axis represents the level at the V FB  pin. At a V FB  level of V REF , the level of V C  transitions steeply between levels A and B. This operation represents boost mode in which the high gain of error amplifier  40  causes V C  to servo about the V REF  feedback level. When V FB  falls below the V REF  level, V C  assumes the high B level. When V FB  is above the V REF  level, the level of V C  is driven at the lower A level. In inverting mode operation, the level of V C  servos between levels A and B at zero feedback level by means of high gain error amplifier  41 . 
     FIG. 7  is a circuit diagram for implementing the scheme of  FIG. 5 . The functionality of the error amplifiers  40  and  41  of  FIG. 5  is obtained by the configuration of PNP transistors  70 ,  72 ,  74  and  76 , and NPN transistors  78  and  80 . Emitters of transistors  70  and  72  are connected together and to current source  71 . Emitters of transistors  74  and  76  are connected together and to current source  75 . The base of transistor  70  is connected to V REF . The bases of transistors  72  and  74  are connected together and to V FB . The base of transistor  76  is connected to ground. 
   The collector of transistor  78  is connected to its base and to current source  79 . The collector of transistor  80  is coupled to current source  81 , a junction therebetween producing the output V C . The base of transistor  78  is connected to the base of transistor  80 . Resistors  86  and  90  are connected in series between the emitter of transistor  78  and ground. Resistors  88  and  92  are connected in series between the emitter of transistor  80  and ground. The collectors of transistors  70  and  74  are connected to the emitter of transistor  78 . The collectors of transistors  72  and  76  are connected to the junction between resistors  88  and  92 , respectively via resistors  82  and  84 . Transistors  78  and  80  are matched and are connected in a current mirror configuration. 
   In operation, transistors  70  and  72  steer current from current source  71  to the current paths in series with transistors  78  and  80 . When V FB  is higher than V REF , most of the current traverses transistor  70 . The current from current source  71  is then directly primarily to the series connected resistors  86  and  90 . When V FB  is lower than V REF , most of the current traverses transistor  72 . The current from current source  71  is then directed primarily to the series connected resistors  82  and  92 . 
   Transistors  74  and  76  steer current from current source  75  to the current paths in series with transistors  78  and  80 . When V FB  is higher than ground, most of the current traverses transistor  76 . The current from current source  75  is then directed primarily to the series connected resistors  84  and  92 . When V FB  is lower than ground, most of the current traverses transistor  74 . Current from current source  75  is then directed primarily to the series connected resistors  86  and  90 . 
   The values of current sources  71 ,  75 ,  79 , and  81 , and resistors  82 ,  84 ,  86 ,  88 ,  90 , and  92  can be selected to obtain the boost mode and inverting mode operation transfer function illustrated in  FIG. 6 . As an example, the following values are set. Current sources  71  and  75  provide currents of 4 μamp and current sources  79  and  81  provide currents of 2 μamp. Resistors  82 ,  84 ,  86  and  88  are 20 kΩ and resistors  90  and  92  are 10 kΩ. V REF  is set at 1.25 volt. 
   In boost operation, the voltage level of V FB  that corresponds to the V C  transition in the transfer function of  FIG. 6  is 1.25 volt. At this value of V FB , transistor  74  will be non-conductive, transistor  76  will conduct 4 μamp from current source  75 , and transistors  70  and  72  will each conduct 2 μamp from current source  71 . 2 μamp from current source  81  will traverse transistor  80 . The current at resistor  92  is a superposition of 2 μamp from current source  71  via transistor  72 , 4 μamp from current source  75  via transistor  76 , and 2 μamp from current source  81  via transistor  80 . The voltage at the emitter of transistor  80 , V C , is substantially the sum of the voltages across resistors  88  (40 mv) and  92  (80 mv), or 120 mv. Current of 4 μamp traverses resistors  86  and  90 . The voltage at the emitter of transistor  78  is the sum of the voltages across resistors  86  (80 mv) and  90  (40 mv), or 120 mv. Transistors  78  and  80  are thus evenly balanced at the higher transition level. 
   As the load decreases, V FB  increases above the 1.25 volt V REF . Current through transistor  72  will decrease and current through transistor  70  will increase. As the current steered to resistor  92  from current source  71  decreases, V C  decreases. As the load increases, V FB  decreases. Current through transistor  72  will increase and current through transistor  70  will decrease. As the current steered to resistor  92  from current source  71  increases, V C  increases. 
   In inverting mode operation, the voltage level of V FB  that corresponds to the V C  transition in the transfer function of  FIG. 6  is 0 volt. At this value of V FB , transistor  70  will be nonconductive, transistor  72  will conduct 4 μamp from current source  71 , and transistors  74  and  76  will each conduct 2 μamp from current source  75 . 2 μamp from current source  81  will traverse transistor  88 . The current at resistor  92  is a superposition of 2 μamp from current source  81  via transistor  80 , 4 μamp from current source  71  via transistor  72 , and 2 μamp from current source  75  via transistor  76 . The voltage at the emitter of transistor  80 , V C , is substantially the sum of the voltages across resistors  88  (40 mv) and  92  (80 mv), or 120 mv. Current of 4 μamp traverses resistors  86  and  90 . The voltage at the emitter of transistor  78  is the sum of the voltages across resistors  86  (80 mv) and  90  (40 mv), or 120 mv. Transistors  78  and  80  are thus evenly balanced at the lower transition level. 
   As the load increases, V FB  increases above ground level. Current through transistor  74  will decrease and current through transistor  76  will increase. As the current steered to resistor  92  from current source  75  increases, V C  increases. As the load decreases, V FB  decreases. Current through transistor  74  will increase and current through transistor  76  will decrease. As the current steered to resistor  92  from current source  75  decreases, V C  decreases. 
   In this disclosure there are shown and described only preferred embodiments of the invention and but a few examples of its versatility. It is to be understood that the invention is capable of use in various other combinations and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein. For example, the transistor pairs depicted in  FIG. 7  may be selected to match a particular ratio other than being evenly matched. Circuit elements of this figure may be selected to obtain different feedback voltage transition points, which can be correlated to various selected values of voltage regulation for boost mode and inverted mode operation. The functionality of the disclosed embodiments are applicable to supply voltages of negative polarity as well as positive polarity.