Abstract:
A serial peripheral interface is configurable to operate in a I 2 S transmission mode. The interface has a transmission unit connected with external pins for data, bit clock, and left/right clock signal, a first-in-first-out (FIFO) buffer with a plurality of memory lines, and a control unit operable to read data portions from two memory lines, to assemble them into a transmission word, and to forward the assembled transmission word to the transmission unit, wherein the transmission unit is configured to serially transmit the assembled transmission word through the external data pin.

Description:
TECHNICAL FIELD 
       [0001]    The present disclosure relates to a synchronous serial bus, in particular of the I 2 S type. 
       BACKGROUND 
       [0002]    Various synchronous serial protocols exist in which clock and data are transmitted on separate lines. One of the most common implementations of a synchronous serial interface is the serial peripheral interface (SPI) bus which comprises separate data lines for input and output, a clock line, optionally a select line and/or a slave select line. 
         [0003]    The I 2 S bus uses a similar number of lines, but provides for a different transmission protocol. Microcontrollers often implement the SPI protocol to be enhanced so that the SPI interface can emulate an I2S interface. The I2S protocol uses a bit clock signal BCLK on the clock line and a separate word clock line. The word clock is often referred to as a left/right clock signal LRCLK. Generally, with each edge of the LRCLK a left or right channel data word is serially transmitted using the bit clock signal. The I2S protocol is optimized for audio data. Depending on the configuration, the audio data word having 16, 24, or 32 bits is transferred between devices. In particular, the 24 bit mode is often emulated by using 32 bits or requires some data processing to be implemented correctly. 
         [0004]    There exists a need for an improved implementation of an I 2 S interface, in particular in a microcontroller. 
       SUMMARY 
       [0005]    According to an embodiment, a serial peripheral interface is configurable to operate in a I2S transmission mode and may comprise a transmission unit connected with external pins for data, bit clock, and left/right clock signal, a first-in-first-out (FIFO) buffer comprising a plurality of memory lines and a control unit operable to read data portions from two memory lines, to assemble them into a transmission word, and to forward the assembled transmission word to the transmission unit, wherein the transmission unit is configured to serially transmit the assembled transmission word through the external data pin. 
         [0006]    According to a further embodiment, the FIFO buffer may comprise three 32-bit memory lines. According to a further embodiment, in a 24-bit operating mode the control unit is configured to access the first memory line to read bits the upper 24 bits and to transfer them to the transmission unit, then to access the first memory line to read the lower 8 bits and the second memory line to read the upper 16 bits and to transfer a combined 24 bit word to the transmission unit, then to access the second memory line to read the lower 16 bits and the third memory line to read the upper 8 bits and to transfer a combined 24 bit word to the transmission unit, and then to access the third memory line to read the lower 24 bits and to transfer them to the transmission unit. According to a further embodiment, in a 16-bit operating mode the control unit is configured to access the first memory line to read bits the upper 16 bits and to transfer them to the transmission unit, then to access the first memory line to read the lower 16 bits to transfer them to the transmission unit, then to repeat the access and transfer for the second and third memory line. 
         [0007]    According to another embodiment, a serial peripheral interface is configurable to operate in a I2S transmission mode and may comprise a plurality of transmission units each connected with at least an external data pin; associated first-in-first-out (FIFO) buffers each comprising a plurality of memory lines; and a control unit operable to read data portions from two memory lines, to assemble them into a transmission word, and to forward the assembled transmission word to the transmission unit, wherein the transmission unit is configured to serially transmit the assembled transmission word through the external data pin. 
         [0008]    According to a further embodiment, each FIFO buffer comprises three 32-bit memory lines. According to a further embodiment, one of the transmission units may be configured as a master unit and the remaining transmission units are configured as slave units. According to a further embodiment, input operations are performed on all FIFO buffers such that a write operations writes data to the same address in each FIFO buffer. According to a further embodiment, each transmission unit reads a single data word from an associated FIFO buffer, wherein the address of the single data word is defined in an associated control register. According to a further embodiment, in a 24-bit operating mode, a first transmission unit reads the upper 24 bits of a first memory line, a second transmission unit read the lower 8 bits of the first memory line and the upper 16 bits of the second memory, the third transmission unit reads the lower 16 bits of the second memory line and the upper 8 bits of the third memory line, and the fourth transmission unit reads the lower 24 bits of the third memory line of an associated FIFO buffer, respectively. According to a further embodiment, in a 16-bit operating mode, a first transmission unit reads the upper 16 bits of each memory line and a second transmission unit read the lower 16 bits of each memory line, respectively. According to a further embodiment, in the 16-bit operating mode, the FIFO buffers only uses a single 32 bit memory line. According to a further embodiment, only one of the FIFO buffers is used for all four transmission units. According to a further embodiment, in the 24-bit operating mode, the control unit is configured to access the first memory line of a selected FIFO buffer to read the upper 24 bits and to transfer them to the first transmission unit, then to access the first memory line of the selected FIFO buffer to read the lower 8 bits and the second memory line to read the upper 16 bits and to transfer a combined 24 bit word to the second transmission unit, then to access the second memory line of the selected FIFO buffer to read the lower 16 bits and the third memory line to read the upper 8 bits and to transfer a combined 24 bit word to the third transmission unit, and then to access the third memory line of the selected FIFO buffer to read the lower 24 bits and to transfer them to the fourth transmission unit. According to a further embodiment, in a 16-bit operating mode, the control unit is configured to access each memory line of a selected FIFO buffer to read the upper 16 bits and to transfer them to the first transmission unit, and then to access each memory line of the selected FIFO buffer to read the lower 16 bits and to transfer them to the second transmission unit. According to a further embodiment, in the 16-bit operating mode, the FIFO buffer only uses a single 32 bit memory line. 
         [0009]    According to yet another embodiment, a method of operating a serial peripheral interface configurable to operate in a I2S transmission mode, may comprise the steps: configuring the serial peripheral interface to operate in I2S mode, wherein the serial peripheral interface comprises a transmission unit connected with external pins for data, bit clock, and left/right clock signal; providing a first-in-first-out (FIFO) buffer comprising a plurality of memory lines; and controlling the serial peripheral interface to read data portions from two memory lines, to assemble them into a transmission word, to forward the assembled transmission word to the transmission unit, and serially transmitting the assembled transmission word through the external data pin. 
         [0010]    According to a further embodiment of the method, the FIFO buffer may comprise three 32-bit memory lines. According to a further embodiment of the method, in a 24-bit operating mode the method comprises: accessing the first memory line to read bits the upper 24 bits and transferring them to the transmission unit, then accessing the first memory line to read the lower 8 bits and the second memory line to read the upper 16 bits and transferring a combined 24 bit word to the transmission unit, then accessing the second memory line to read the lower 16 bits and the third memory line to read the upper 8 bits and transferring a combined 24 bit word to the transmission unit, and then accessing the third memory line to read the lower 24 bits and transferring them to the transmission unit. According to a further embodiment of the method, in a 16-bit operating mode the method comprises: accessing the first memory line to read bits the upper 16 bits and transferring them to the transmission unit, then accessing the first memory line to read the lower 16 bits transferring them to the transmission unit, then repeating the steps of accessing and transferring for the second and third memory line. 
         [0011]    According to yet another embodiment, a method for operating a serial peripheral interface configurable to operate in a I2S transmission mode, may comprise the steps: providing a plurality of transmission units each connected with at least an external data pin; providing associated first-in-first-out (FIFO) buffers each comprising a plurality of memory lines; and reading data portions from two memory lines, assembling them into a transmission word, forwarding the assembled transmission word to the transmission unit, and serially transmitting the assembled transmission word through the external data pin. 
         [0012]    According to a further embodiment of the method, each FIFO buffer may comprise three 32-bit memory lines. According to a further embodiment of the method, the method may comprise the step of configuring one of the transmission units as a master unit and the remaining transmission units as slave units. According to a further embodiment of the method, the method may comprise performing input operations on all FIFO buffers such that a write operations writes data to the same address in each FIFO buffer. According to a further embodiment of the method, each transmission unit may read a single data word from an associated FIFO buffer, wherein the address of the single data word is defined in an associated control register. According to a further embodiment of the method, in a 24-bit operating mode, a first transmission unit reads the upper 24 bits of a first memory line, a second transmission unit read the lower 8 bits of the first memory line and the upper 16 bits of the second memory, the third transmission unit reads the lower 16 bits of the second memory line and the upper 8 bits of the third memory line, and the fourth transmission unit reads the lower 24 bits of the third memory line of an associated FIFO buffer, respectively. According to a further embodiment of the method, in a 16-bit operating mode, a first transmission unit reads the upper 16 bits of each memory line and a second transmission unit read the lower 16 bits of each memory line, respectively. According to a further embodiment of the method, in the 16-bit operating mode, the FIFO buffers only uses a single 32 bit memory line. According to a further embodiment of the method, only one of the FIFO buffers is used for all four transmission units. According to a further embodiment of the method, in a 24-bit operating mode, the method comprises: accessing the first memory line of a selected FIFO buffer to read the upper 24 bits and transferring them to the first transmission unit, then accessing the first memory line of the selected FIFO buffer to read the lower 8 bits and the second memory line to read the upper 16 bits and transferring a combined 24 bit word to the second transmission unit, then accessing the second memory line of the selected FIFO buffer to read the lower 16 bits and the third memory line to read the upper 8 bits and transferring a combined 24 bit word to the third transmission unit, and then accessing the third memory line of the selected FIFO buffer to read the lower 24 bits and transferring them to the fourth transmission unit. According to a further embodiment of the method, in a 16-bit operating mode, the method comprises: accessing each memory line of a selected FIFO buffer to read the upper 16 bits and transferring them to the first transmission unit, and then accessing each memory line of the selected FIFO buffer to read the lower 16 bits and transferring them to the second transmission unit. According to a further embodiment of the method, in the 16-bit operating mode, the FIFO buffer only uses a single 32 bit memory line. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]      FIG. 1  shows a conventional serial peripheral interface; 
           [0014]      FIG. 2  shows FIFO buffers according to various operating modes of various embodiments; 
           [0015]      FIG. 3  shows a block diagram of an embodiment; 
           [0016]      FIG. 4  shows a block diagram of another embodiment; 
           [0017]      FIGS. 5 and 6  show operating modes of an embodiment according to  FIG. 4 ; and 
           [0018]      FIGS. 7-10  show flow charts of operating modes according to various embodiments. 
       
    
    
     DETAILED DESCRIPTION 
       [0019]      FIG. 1  shows a conventional SPI interface peripheral device  100  that may be implemented within a microcontroller. Data to be transferred by the device externally is written into the buffer register  120  via an internal bus  110 . The buffer register may be implemented as a first-in-first-out (FIFO) memory  130  with separate transmit and receipt buffers as shown in  FIG. 1  and may have any suitable size. According to some embodiments, the FIFO functionality of the buffer may be programmable to be enabled or disabled. The input buffer  120 / 130  is coupled with a transfer shift register  140  which is connected with external input pins SDIx and external output pin SDOx. The ‘x’ indicates that multiple units may be present in the microcontroller. 
         [0020]    Slave select and frame synchronization control unit  150  is provided and coupled with external slave select pin SSx and may control a tri-state buffer between the output of register  140  and output pin SDOx. A clock control unit  160  provides the shift clock signal which operates shift register  140 . Clock control unit  160  is also coupled with slave select and frame synchronization control unit  150  and an edge select unit  170 . A baud rate generator  180  can be driven programmably by various internal clock signals and is coupled via a controllable driver with external pin SCKx and edge select unit  170 . Various control registers may be implemented that can be used to configure the SPI. 
         [0021]    This SPI peripheral  100  is designed to operate as a normal SPI interface with various operating modes, such as master or slave mode, framed operation, DSP mode etc. In addition, this peripheral can be configured to operate as an I 2 5 interface. In this mode, the SSx pin is used as the LRCLK pin, the SCKx operates as the BCLK line and the SDIx and SDOx operate as the data signal input/output pins. Depending on whether the unit  100  is operated as master or slave, pins SSx and SCKx are either output (master) or input (slave) pins. 
         [0022]    Once a data word is written into the buffer, the peripheral will transfer the written data via the shift register to output pin SDOx. If the unit is configured as a master device, then the respective clock signals are generated by the device  100 . When operating as a slave, the device  100  fetches a new data word from the buffer upon receipt of the respective LRCLK signal. The device is programmable to transfer data words with 16, 24 or 32 bits, wherein the FIFO is designed to have a plurality of 32 bit registers. When programmed to transmit 16 bits words, only the lower 16 bits in each buffer register are transmitted and the upper 16 bits will be ignored. When programmed to transmit 24 bits words, only the lower 24 bits in each buffer register are transmitted and the upper 8 bits will be ignored. When programmed to transmit 32 bits words, each entire buffer register is transmitted. Thus, this implementation requires some pre-processing of the data as audio data is generally stored in mass storage device in a packed manner. Thus, only the 32-bit transfer mode requires no pre-processing as the data can be directly written from memory into the buffer. 
         [0023]    However, in 16 bit and 24 bit mode, the respective audio data is stored in a packed fashion, in other words, no alignment of the 24 bits takes place to save memory. If data would be written directly into the buffer  120 / 130  using 32 bit write operations, the data would be misaligned and truncated. In fact no usable transmission could take place. Thus, the data must be pre-processed before it can be written into the buffer. In particular for 24-bit audio data, this causes time intensive processing. If 32 bit read operations are used to retrieve the data from memory, then 8 or 16 bits must be buffered and combined with a following read. Alternatively, only 8 bit reads could be used and the 24 bits would be assembled by using three consecutive read operations. In any way, the transfer of 24 bit audio data from memory would require some processing which uses up processing power that could be required for other tasks. Similar operations are required for 16 bit audio data even though less processing power is needed due to the alignment of all 16 bit data. However, each 16 bit word must be separately stored in a 32 bit buffer register  120 / 130  to ensure proper operation of the I 2 S interface. 
         [0024]      FIG. 2  shows the alignment of 32 bit, 24 bit, and 16 bit packed data in memory. The data is stored in the most efficient way such that no memory space is wasted. Hence, Each subsequent data word immediately follows the preceding word without any memory space disregarding any type of alignment misplacement. This is generally not an issue for 32 bit words in a 32 bit system because 32 bit data will be automatically aligned if the first word is aligned as shown in example  300 . Thus, reading the memory with 32 bit instructions allows placing the respective word into the FIFO with a single write command. 
         [0025]    Example  310  shows the storage of 24 bit data. As can be seen in  FIG. 3 , only data  0  and  4  are aligned with respect to 32 bit. Thus, either several 8-bit read operations and merging of the data, combined 16-bit and 8-bit read instructions, or 32-bit read instructions and intermediate storage of those parts that are needed for the next 24-bit word are necessary to fill the FIFO correctly. 
         [0026]    For 16 bit data width as shown in the example  320 , every other word will be aligned to a 32 bit boundary. Thus, either single 16-bit read instructions or a 32-bit read instruction with intermediate buffering are required. 
         [0027]    Obviously, the 24-bit scenario as shown in example  310  causes the most processing.  FIG. 3  shows an enhanced SPI interface with I 2 S transmission capability. Here, a FIFO  210  is not connected directly to a SPI transmission unit  220  but rather the access to the FIFO  210  is controlled by a control unit  260  which, for example may include a finite state machine (FSM) that provides the data to the transmission unit  220  depending on a programmable operating mode. 
         [0028]    When this unit is programmed to operate in I 2 S mode, the transmission unit  220  uses its external connections as shown in  FIG. 3 , namely, the data line is used for audio data, the clock line provides the bit clock signal BCLK, and the SSx pin is used for the LRCLK signal. The bottom of  FIG. 3  assumes that the SPI interface operates in the 24-bit audio mode using the I2S protocol. The FIFO  210  will thus be filled directly from memory with 4 audio 24-bit data words. Once the FIFO  210  has been filled with three 32-bit words, the control unit can access the FIFO  210  as shown in the bottom of  FIG. 3 . A first access the FSM transfers Line 0 [ 31 .. 8 ] to transmission unit  220 . A second access transfers Line 0 [ 7 .. 0 ] concatenated with Line 1 [ 31 .. 16 ]. A third access transfers Line 1 [ 15 .. 0 ] concatenated with Line 2 [ 31 .. 24 ] and a fourth access transfers Line 2 [ 23 .. 0 ]. The system then indicates to the microprocessor that the FIFO is empty and more data can be transferred from memory into the buffer. The microprocessor can then transfer directly the next three 32-bit words from memory into the buffer without any processing or rearranging of the data. 
         [0029]    In 16-bit operating mode, the state machine  260  accesses the FIFO  210  to alternately read the upper word Linex[ 31 .. 16 ] and the lower word Linex[ 15 .. 0 ]. Again, the processor can transfer data directly using only 32-bit read/write instructions for optimum speed without the necessity to realign the data retrieved from memory. According to another embodiment, in the 16-bit operating mode, the FIFO  210  may only use a single memory line. 
         [0030]      FIG. 4  shows yet another embodiment of a synchronous serial interface peripheral  400 , in which multiple SPI or I 2 S interface units  410 ,  420 ,  230 ,  240  operate with a FIFOs  210 - 240  to provide for a multi-channel functionality. In this example four channels are provided. However, according to other embodiments, more or less channels may be provided. In such implementations the number of FIFO lines for each FIFO  210 - 240  may be increased accordingly such that a block of audio data that is transferred is aligned with respect to a 32 bit memory structure. Due to the fact that 24-bit data words are aligned for every four words in a 32-bit memory system, multiples of four channels may have to be considered in a 32-bit system. However, the concept discussed above may also be used in 16-bit system which would require 3 16-bit FIFO lines storing 2 two 24-bit words at a minimum or multiples thereof for more channels. Higher bit systems would be able to store more 24-bit words in three FIFO lines. 
         [0031]    Again, a control unit  260  may be used to configure these four channel units and may comprise a finite state machine (FSM) that coordinates the transfer of data stored in the buffer FIFOs  210 - 240 . Each unit comprises separate data, LRCD and CLK lines. One unit may be selected as a master, for example unit  440  and the remaining units  410 - 430  may operate as slave devices. Which unit is master may be selectable or may be fixed according to respective implementations. As shown in  FIG. 4 , the respective clock lines of these units are connected with each other such that the master unit  440  provides the clock signals to units  410 - 420 . Hence, all transmissions of audio signals over the four channels occurs synchronously. 
         [0032]    Externally, the device may provide only one set of LRC and CLK pins and respective associated pins of the slave SPI units  410 - 430  may be available for other purposes, such as general purpose input/output pin functionality. Hence, when the device operates in the various modes shown in  FIGS. 4-6  a plurality of external pins may be available for other functions. 
         [0033]    According to various embodiments, the control unit  260  can be configured to allow packed data to be directly transferred from a single buffer FIFO, for example FIFO  240 , or from each buffer FIFO  210 - 240  associated with the respective transmission unit  410 - 440 . The controller is configured to read the buffer line by line and coordinate the transfer/assembly of the stored data to the correct I 2 S unit  410 - 440  in a similar fashion as explained with respect to  FIG. 3 . In one embodiment, in the 24-bit operating mode, the four 24 bit words would be distributed to all four channels for synchronous transmission. Because the master  440  triggers the transmission, the master  440  is the last channel that receives its data. Thus, once the data has been transferred to the master  440 , the master starts the transmission which sends the respective clock signals to all other units to trigger their transmission simultaneously. This could be done by a separate command or through completion of writing to the FIFO. 
         [0034]      FIG. 5  shows the same configuration as  FIG. 4  in more detail when the system is configured in the I 2 S mode with 24-bit audio data. The SPI Master controller  240  and up to 3 SPI slaves  210 - 230  are provided for decoding and transmitting data in a packed 32-bit format of 3 quadlets for 4 channels 24-bit data or 1 quadlet for 2 channels 16-bit data. When the FIFO data is read, the Master and slave combinations transmit decoded data for all 4 (Or 2) channels at the same time, with the Master CLK and LRC (sync pulse) as discussed above. As mentioned above, according some embodiments, in the 16-bit operating mode, the FIFOs  210 - 240  may only use a single memory line as indicated with the top representation of FIFOs  210 - 240  in  FIG. 5 . 
         [0035]    As shown, the system may operate with “one write to many FIFOs” in one embodiment, wherein data in the form of 3 or 1 (32-bit) quadlets are written to all spy FIFOs  210 - 240 . According to this embodiment, this is done with one write cycle in which all FIFO&#39;s would be addressed at the same time, each getting the same data values, but could be done with separate writes to FIFOs  210 - 240  which obviously would require more processing time. According to some embodiments, the user can define which SPI unit  210 - 240  gets which Bits of data from each quadlet in the FIFO with a user settable SPI register value. Only one SPI is defined as a Master and the remaining SPI&#39;s are defined as slaves. Table 1 shows the possible settings for unit  210 - 250 . 
         [0000]    
       
         
               
             
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 SLAVE_EN[2:0] 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 000 -- Master decode enable 
               
               
                   
                 001 -- Slave 1 decode enable 
               
               
                   
                 010 -- Slave 2 decode enable 
               
               
                   
                 011 -- Slave 3 decode enable 
               
               
                   
                 100 -- Master 16-bit decode [15:0] enable 
               
               
                   
                 101 -- Master 16-bit decode [31:16]enable 
               
               
                   
                 110 -- Slave 1 16-bit decode [31:16] enable 
               
               
                   
                 111 -- Slave 1 16-bit decode [15:0] enable 
               
               
                   
                   
               
             
          
         
       
     
         [0036]    A finite state machine (FSM) for data decode from the FIFO is the same for Master or Slave. The FSM controls reading FIFO data along with user defined SPI register values determines which bits of data from the quadlet is supposed to be shift out of the SPI. The Master/Slave SPI is commanded to start sending the data either by a signal from the CPU or in auto Mastermode when the Master SPI FSM commands to send the data out. 
         [0037]    According to another embodiment “Master only FIFO write with a side band bus” can be implemented as shown in  FIG. 6 . In this embodiment, data in the form of 3 or 1 (32-bit) quadlets is written only to the Master FIFO, for example, FIFO  240 . The user has defined which Slave SPI gets which Bits of data from each quadlet in the FIFO  240  with a user settable SPI register value. Only one SPI is defined as a Master and the remaining SPI&#39;s are defined as slaves. The FSM for data decode from the FIFO  240  is the same for Master or Slave, but only enabled in the SLAVE. The FSM controls reading FIFO data along with user defined SPI register values determines which bits of data from the quadlet is supposed to be shift out of the SPI. The Master/Slave SPI is commanded to start sending the data either by a signal CMD_SPI_GO from the CPU or in auto Mastermode when the Master SPI FSM commands to send the data out. A data bus MST_SLV_DATA[24:0] connects to all SPI units for transmission of data. A second bus MST_SLV_BUS[2:0] provides control values according to table 2. As shown in  FIG. 6 , the data and control signals can be channeled through the SPI master unit  440 . However, other embodiments may provide these signals by the control unit  260 . As mentioned above, according some embodiments, in the 16-bit operating mode, the FIFO  210  may only use a single memory line. 
         [0000]    
       
         
               
             
               
               
             
           
               
                 TABLE 2 
               
               
                   
               
               
                 MST_SLV_BUS[2:0] 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 000 -- nothing default 
               
               
                   
                 1xx -- Master start transmit slave 
               
               
                   
                 x01 -- SPI slave#1 get data 
               
               
                   
                 x10 -- SPI slave#2 get data 
               
               
                   
                 x11 -- SPI slave#3 get data 
               
               
                   
                   
               
             
          
         
       
     
         [0038]    All functionalities as described above may be combined as appropriate. For example, a device may be designed to operate in a first and a second operating mode as shown in  FIGS. 5 and 6 . The FIFOs may be designed to have a programmable size of for example more than three memory lines. Thus, other operating modes, e.g. using 32-bit wide audio data with one or more channels may benefit from a larger FIFO size. 
         [0039]      FIG. 7  shows a general flow chart including three consecutive read operations for the 24-bit operating mode which feeds four channels and a single read operation in the 16-bit operating mode which feeds two channels according to various embodiments. Note: The next values of the FIFO can be loaded when a respective signal cmd_spi_go is asserted during the wait state. This is so the next FIFO value can be preloaded into the transmit register. The master_latch_next_data signal is asserted for a pulse equal to the system clock period when the signal cmd_spi_go is asserted during the wait state to register the data into the SPI shifter before the last bit of the previous rdy_tx_reg_data to be shifted out. On the first time through the FSM after enabled during the stall state the pre_tx_reg and rdy_tx_reg are loaded with the same value at cmd_spi_go pulse. 
         [0040]      FIG. 8  shows a flow chart for the 24-bit operating mode according to an embodiment.  FIG. 10  shows a flow chart for the 16-bit operating mode with a single memory line in the FIFO being operative according to an embodiment. Note: The load_next_value is asserted for a pulse equal to the system clock at the start of the shift of the tx_reg. So the next fifo values can be preloaded into the pre_tx_reg prior to be being needed for shifting in the tx_reg. The mst_latch_next_data is asserted for a pulse equal to the system clock when the go signal from the cpu is high or in auto-mode during state stall and before the SPI shifter has shifted out the last bit of the tx_reg data to be shifted out. On the first time through the state machine after enabled at the stall state the pre_tx_reg and tx_reg are loaded with the same value with the latch_next_data. 
         [0041]      FIG. 9  shows a flow chart for the 24-bit mode with four channels and the respective data assembly paths according to an embodiment. Note: Load_next_value : is asserted for a pulse equal to the system clock at the start of the shift of the master tx_ms_reg. So the next fifo values can be preloaded into the pre_tx_xx_reg prior to be being needed for shifting in the tx_xx_reg. Latch_next_data : is asserted for a pulse equal to the system clock when the go signal from the cpu is high or in automode during state stall and before the SPI master shifter has shifted out the last bit of the tx_ms_reg data to be shifted out. On the first time through the state machine after enabled at the stall state the pre_tx_xx_reg and tx_xx_reg are loaded with the same value with the latch_next_data.