Abstract:
A method and apparatus is disclosed to extend a dynamic input range of an analog to digital converter (ADC). A composite ADC may include one or more ADCs. The one or more ADCs compare a signal metric of an analog input signal to quantization levels to produce intermediate digital output signals using one or more non-clipping input values. The composite ADC may select among the one or more intermediate digital output signals based on the signal metric of the analog input signal to produce a final digital output.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application claims the benefit of U.S. Provisional Patent Appl. No. 61/136,353, filed Aug. 29, 2008, entitled “Analog to Digital Converter (ADC) with Extended Dynamic Input Range”, which is incorporated by reference herein in its entirety. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates generally to analog to digital converters (ADC) communications receiver, more specifically to extending a dynamic input range of an ADC. 
         [0004]    2. Related Art 
         [0005]    An analog to digital converter (ADC) is an electronic circuit that converts an analog input to a digital output signal. The ADC includes one or more quantization levels to produce the digital output signal. Each quantization level may be assigned to a combination of bits, referred to as a codeword. The ADC selects a corresponding one of the quantization levels as a representation of the analog input. The ADC assigns the codeword corresponding to a selected quantization level to the digital output signal to convert the analog input to a digital representation. 
         [0006]    A ratio between a most miniscule nonzero quantization level and a maximum quantization level may be referred to as a dynamic input range of the ADC, r, such that the dynamic range r is greater than or equal to one. Generally, the dynamic input range of the ADC is determined such that a maximum value of the analog input is less than or equal to the maximum quantization level, and/or a minimum value of the analog input is greater than or equal to the minimum quantization level. However, the minimum value of the analog input and/or the maximum value of the analog input may fall below the minimum quantization level and/or rise above the maximum quantization level, respectively, causing the ADC to saturate or clip. When clipping occurs, the digital output signal no longer accurately represents the analog input. 
         [0007]    A conventional ADC may attenuate the analog input before conversion to the digital representation. Attenuation of the analog input in this manner ensures the maximum value level of the analog input does not exceed the maximum quantization level too often or by too much. As a result of this attenuation, each quantization level of the conventional ADC is required to convert a greater range of the analog input as observed prior to the attenuation, thereby reducing a resolution of the conventional ADC. This reduction in resolution of the conventional ADC corresponds to an increase in quantization noise of the conventional ADC relative to the analog input prior to its attenuation. To avoid this increased quantization noise in the presence of the attenuation, a number of the quantization levels of the conventional ADC may be increased in proportion to the attenuation. Increasing the number of quantization levels in this manner increases the dynamic input range of the conventional ADC. However, increasing the number of the quantization levels increases an area and a power consumption of the conventional ADC. Further, increasing the number of the quantization levels may cause an increase in a number of bits to be processed by signal processors that rely on the conventional ADC to provide an input. 
         [0008]    Therefore, what is needed is an ADC with an extended dynamic input range but achieved without proportionately increasing the number of the quantization levels and/or reducing the effective resolution of the ADC. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES 
         [0009]    The accompanying drawings illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable one skilled in the pertinent art to make and use the invention. 
           [0010]      FIG. 1  illustrates a block diagram of a conventional analog to digital converter (ADC) module. 
           [0011]      FIG. 2A  illustrates a first block diagram of a composite ADC module according to a first embodiment of the present invention. 
           [0012]      FIG. 2B  illustrates a second block diagram of a composite ADC module according to a second embodiment of the present invention. 
           [0013]      FIG. 3  is a flowchart of exemplary operational steps of a first logic module used in the composite ADC module according to a first of the present invention. 
           [0014]      FIG. 4  illustrates a third block diagram of a composite ADC module according to a third embodiment of the present invention. 
           [0015]      FIG. 5  is a flowchart of exemplary operational steps of a second logic module used in the composite ADC module according to a second aspect of the present invention. 
           [0016]      FIG. 6  illustrates a fourth block diagram of a composite ADC module according to a fourth embodiment of the present invention. 
           [0017]      FIG. 7  is a flowchart of exemplary operational steps of a third logic module used in the composite ADC module according to a third aspect of the present invention. 
       
    
    
       [0018]    The present invention will now be described with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the reference number. 
       DETAILED DESCRIPTION OF THE INVENTION 
       [0019]    The following Detailed Description refers to accompanying drawings to illustrate exemplary embodiments consistent with the present invention. References in the Detailed Description to “one exemplary embodiment,” “an exemplary embodiment,” “an example exemplary embodiment,” etc., indicate that the exemplary embodiment described may include a particular feature, structure, or characteristic, but every exemplary embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same exemplary embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an exemplary embodiment, it is within the knowledge of those skilled in the relevant art(s) to effect such feature, structure, or characteristic in connection with other exemplary embodiments whether or not explicitly described. 
         [0020]    The exemplary embodiments described herein are provided for illustrative purposes, and are not limiting. Other exemplary embodiments are possible, and modifications may be made to the exemplary embodiments within the spirit and scope of the present invention. Therefore, the Detailed Description is not meant to limit the present invention. Rather, the scope of the present invention is defined only in accordance with the following claims and their equivalents. 
         [0021]    The following Detailed Description of the exemplary embodiments will so fully reveal the general nature of the present invention that others can, by applying knowledge of those skilled in relevant art(s), readily modify and/or adapt for various applications such exemplary embodiments, without undue experimentation, without departing from the spirit and scope of the present invention. Therefore, such adaptations and modifications are intended to be within the meaning and plurality of equivalents of the exemplary embodiments based upon the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by those skilled in relevant art(s) in light of the teachings herein. 
         [0022]      FIG. 1  illustrates a block diagram of a conventional analog to digital converter (ADC) module. A conventional ADC module  100  includes a conventional ADC  102  to convert an analog input signal  150  to a digital output signal  152 . The analog input signal  150  may be greater than and/or less than a conventional non-clipping input value m c . The analog input signal  150  may represent a total energy, a mean square, an instantaneous power, a root mean square, a variance, a norm, a voltage level, and/or any other suitable statistic of the analog input signal  150  which will be apparent to one skilled in the relevant art(s). The conventional non-clipping input value m c  represents a value of the analog input signal  150  that when exceeded causes the conventional ADC  102  to saturate or clip. For example, the analog input  150  may represent a signed value including both positive values and negative values. In this situation, the conventional non-clipping input value m c  may represent a maximum value of the analog input  150  for which the conventional ADC  102  does not clip. Alternatively, the analog input  150  may represent an unsigned value including only positive values. In this situation, the conventional non-clipping input value m c  may represent the maximum value of the analog input  150  for which the conventional ADC  102  does not clip. In another alternative, the analog input  150  may represent another unsigned value including only negative values. In this situation, the conventional non-clipping input value m c  may represent a minimum value of the analog input  150  for which the conventional ADC  102  does not clip. 
         [0023]    The conventional ADC  102  determines a respective one of n quantization levels to assign to the analog input signal  150  to convert the analog input signal  150  from an analog representation to a digital representation. For example, when the analog input signal  150  is less than or equal to the conventional non-clipping input value m c , the conventional ADC  102  assigns a unique digital value corresponding to a respective one of the n quantization levels to k bits of the digital output signal  152 . However, when the analog input signal  150  is greater than or equal to the conventional non-clipping input value m c , the conventional ADC  102  saturates or clips. In this situation, the conventional ADC  102  assigns the unique digital value corresponding to a maximum quantization level or a minimum quantization level to the k bits of the digital output signal  152 . As a result of this clipping, the digital output signal  152  no longer accurately represents a digital representation of the analog input signal  150  that in turn causes a reduction in an output signal to noise ratio (SNR) of the conventional ADC module  100  as compared to the output SNR of the conventional ADC module  100  when not clipped. 
         [0024]      FIG. 2A  illustrates a first block diagram of a composite ADC module according to a first embodiment of the present invention. A composite ADC module  200  converts the analog input signal  150  to a final digital output signal  250 . The analog input signal  150  may be greater than and/or less than one or more non-clipping input values m r1  through m ri . Each of the non-clipping input values m r1  through m ri  may include a mean, a total energy, an average power, a mean square, an instantaneous power, a root mean square, a variance, a norm, a voltage level and/or any other suitable signal metric of the analog input signal  150  which will be apparent to one skilled in the relevant art(s). 
         [0025]    The composite ADC module  200  includes one or more ADCs  202 . 1  through  202 . i  and a combining logic module  204 . Each one of the ADCs  202 . 1  through  202 . i  corresponds to one of the non-clipping input values m r1  through m ri . In an exemplary embodiment, the non-clipping input values m r1  through m ri  are implemented in an increasing order such that a non-clipping input value having a lesser subscript, such as the non-clipping input value m r1  to provide an example, is smaller than a non-clipping input value having a greater subscript, such as the non-clipping input value m r2  to provide an example. Assuming that each one of the ADCs  202 . 1  through  202 . i  may be separated into a similar number of quantization levels, the ADCs  202 . 1  through  202 . i  corresponding to the non-clipping input value having the lesser subscript, such as the ADC  202 . 1  to provide an example, have a lesser quantization step size Δ Q  when compared to the ADCs  202 . 1  through  202 . i  corresponding to the non-clipping input value having the greater subscript. As a result of the lesser quantization step size Δ Q , a resolution of an ADC  202 . 1  through  202 . i  having a lesser subscript, such as the ADC  202 . 1  to provide an example, is substantially greater than or equal to a resolution of an ADC  202 . 1  through  202 . i  having a greater subscript, such as the ADC  202 . 2  to provide an example. However, this example is not limiting, those skilled in the relevant art(s) will recognize that each one of the ADCs  202 . 1  through  202 . i  may be separated into a dissimilar number of quantization levels without departing from the spirit and scope of the present invention. 
         [0026]    The analog input signal  150  may be less than or equal to one or more of the non-clipping input values m r1  through m ri . In this situation, the ADCs  202 . 1  through  202 . i  having their corresponding non-clipping input value m r1  through m ri  greater than or equal to the analog input signal  150  assign a unique digital value corresponding to one of n 1  through n k  quantization levels to j bits of the corresponding intermediate digital output signal  252 . 1  through  252 . i.  The ADCs  202 . 1  through  202 . i  may include a similar number of quantization levels or a dissimilar number of quantization levels. In an exemplary embodiment, each of the j bits of the ADCs  202 . 1  through  202 . i  corresponds to an equivalent number of bits. In another exemplary embodiment, at least one of the j bits may represent unique identifiers corresponding to the ADC  202 . 1  through  202 . i  that has generated the corresponding intermediate digital output signal  252 . 1  through  252 . i.  These unique identifiers are available to be used by one or more processors operating on the ADC output  250  to interpret scaling of the intermediate digital output signals  252 . 1  through  252 . i.  In general, the scaling of the intermediate digital output signals  252 . 1  through  252 . i  may differ between the ADCs  202 . 1  through  202 . i,  but the downstream processing associates the ADC with the scaling it used through the unique identifier bits. In another exemplary embodiment, the ADCs  202 . 1  through  202 . i  having their corresponding non-clipping input value m r1  through m ri  greater than or equal to the analog input signal  150  compare a signal metric of the analog input signal  150  to one or more of the n 1  through n k  quantization levels to assign the unique digital value. The signal metric of the analog input signal  150  may include the mean, the total energy, the average power, the mean square, the instantaneous power, the root mean square, the variance, the norm, the voltage level and/or any other suitable signal metric of the analog input signal  150  which will be apparent to one skilled in the relevant art(s). 
         [0027]    Alternatively, the analog input signal  150  may be greater than or equal to one or more of the non-clipping input values m r1  through m ri . In this situation, the ADCs  202 . 1  through  202 . i  having their corresponding non-clipping input value m r1  through m ri  less than or equal to the analog input signal  150  assign the unique digital value corresponding to a maximum quantization level or a minimum quantization level to the j bits of the corresponding intermediate digital output signal  252 . 1  through  252 . i.    
         [0028]    In another alternate, the analog input signal  150  may be greater than or equal to all of the non-clipping input values m r1  through m ri . In this situation, the ADCs  202 . 1  through  202 . i  assign the unique digital value corresponding to the maximum quantization level or the minimum quantization level to the j bits of the corresponding intermediate digital output signal  252 . 1  through  252 . i.    
         [0029]    The combining logic module  204  selects one of the intermediate digital output signals  252 . 1  through  252 . i  to represent the final digital output signal  250  based upon a selection signal  254 . The combining logic module  204  includes a switching module  206 . The switching module  206  selects one of the intermediate digital output signals  252 . 1  through  252 . i  to represent the final digital output signal  250  based on a selection signal  254 . In general, the combining logic module  204  selects the intermediate digital output signal  252 . 1  through  252 . i  which has a smallest resolution among all the ADCs  202 . 1  through  202 . i  having their corresponding non-clipping input value m r1  through m ri  less than or equal to the analog input signal  150  to represent the final digital output signal  250 . 
         [0030]    The logic module  208  generates the selection signal  254  based on a signal metric of the analog input signal  150 . The logic module  208  provides the selection signal  254  that causes the switching module  206  to select a first intermediate digital output signal, such as the intermediate digital output signal  252 . 1  to provide an example, as the final output  250  when the signal metric of the analog input signal  150  is less than or equal to a first non-clipping input value, such as the non-clipping input value m r1  to provide an example. In an exemplary embodiment, the logic module  208  may include one or more thresholds, wherein each threshold from the one or more thresholds may be assigned to one of the non-clipping input values m r1  through m ri . For example, the logic module  208  provides the selection signal  254  that causes the switching module  206  to select the first intermediate digital output signal when the signal metric of the analog input signal  150  is less than or equal to a threshold corresponding to the first non-clipping input value. However, this example is not limiting, the logic module  208  may utilize other means to provide the selection signal  254  differently in accordance with the teaching herein without departing from the sprit and scope of the present invention. 
         [0031]    Alternatively, the logic module  208  provides the selection signal  254  that causes the switching module  206  to select a second intermediate digital output signal, such as the intermediate digital output signal  252 . 2  to provide an example, as the final output  250  when the signal metric of the analog input signal  150  is greater than or equal to the first non-clipping input value, but less than a second non-clipping input value, such as the non-clipping input value m r2  to provide an example. However, if the signal metric of the analog input signal  150  returns to being less than or equal the first non-clipping input value, the logic module  208  provides the selection signal  254  that causes the switching module  206  to once again select the first intermediate digital output signal as the final output  250 . 
         [0032]    In another alternate, the logic module  208  provides the selection signal  254  that causes the switching module  206  to select any of the intermediate digital output signals  252 . 1  through  252 . i  as the final output  250  when the signal metric of the analog input signal  150  exceeds a maximum non-clipping input value, such as the non-clipping input value m ri  to provide an example. In this situation, the logic module  208  usually produces the selection signal  254  that causes the switching module  206  to select the intermediate digital output signal  252 . 1  through  252 . i  corresponding to an ADC  202 . 1  through  202 . i  corresponding to the maximum non-clipping input value. 
         [0033]      FIG. 2B  illustrates a second block diagram of a composite ADC module according to a second embodiment of the present invention. A composite ADC module  220  converts the analog input signal  150  to the final digital output signal  250 . The composite ADC module  200  includes the one or more ADCs  202 . 1  through  202 . i,  as described above in  FIG. 2A , and a combining logic module  224 . 
         [0034]    The combining logic module  224  may provide one or more linear combinations of the intermediate digital output signals  252 . 1  through  252 . i  to represent the final digital output signal  250 . The combining logic module  224  includes multipliers  226 . 1  through  226 . i  and a summation network  228 . The multipliers  226 . 1  through  226 . i  multiply the intermediate digital output signals  252 . 1  through  252 . i  and a corresponding coefficient c 1  through c i  to provide a corresponding partial product output  256 . 1  through  256 . i.  For example, the multiplier  226 . 1  may multiply the intermediate digital output signal  252 . 1  and the coefficient c 1  to provide the partial product  256 . 1 . The summation network  228  combines the partial product output  256 . 1  through  256 . i  to provide the final output  250 . 
         [0035]    The logic module  230  provides the coefficients c 1  through c i  based on the signal metric of the analog input signal  150 . The logic module  230  provides the coefficients c 1  through c i  to the multipliers  226 . 1  through  226 . i  such that the final output  250  may be represented as: 
         [0000]      OUT FINAL   =c   1 *ADC 1   +c   2 *ADC 2   + . . . +c   1 *ADC i ,   (1) 
         [0000]    where OUT FINAL  represents the final output  250 , c 1  through c i  represent the coefficients c 1  through c i , and ADC 1  through ADC i  represent outputs of the ADCs  202 . 1  through  202 . i,  namely the intermediate digital output signals  252 . 1  through  252 . i.    
         [0036]    The logic module  230  provides a first set of the coefficients c 1  through c i  that cause the combining logic module  224  to provide a first linear combination of the intermediate digital output signals  252 . 1  through  252 . i  as the final output  250  when the signal metric of the analog input signal  150  is less than a first non-clipping input value, such as the non-clipping input value m r1  to provide an example. In an exemplary embodiment, the logic module  230  may include one or more thresholds, wherein each threshold from the one or more thresholds may be assigned to one of the non-clipping input values m r1  through m ri . For example, the logic module  230  provides the first set of the coefficients c 1  through c i  when the signal metric of the analog input signal  150  is less than or equal to a threshold corresponding to the first non-clipping input value. However, this example is not limiting, the logic module  230  may utilize other means to provide the set of the coefficients c 1  through c i  differently in accordance with the teaching herein without departing from the sprit and scope of the present invention. 
         [0037]    Alternatively, the logic module  230  provides a second set of the coefficients c 1  through c i  that cause the combining logic module  224  to provide a second linear combination of the intermediate digital output signals  252 . 1  through  252 . i  as the final output  250  when the signal metric of the analog input signal  150  is greater than or equal the first non-clipping input value, but less a second non-clipping input value, such as the non-clipping input value m r2  to provide an example. In an exemplary embodiment, those coefficients in the second set of the coefficients c 1  through c i  corresponding to one or more ADCs whose non-clipping input value is less than the signal metric of the analog input signal  150  are set to zero, such that its respective intermediate digital output signals  252 . 1  through  252 . i  does not contribute to the final output  250 . However, if the signal metric of the analog input signal  150  returns to being less than or equal to the first non-clipping input value, the logic module  230  provides the first set of the coefficients c 1  through c i  that cause the combining logic module  224  to provide the first linear combination of the intermediate digital output signals  252 . 1  through  252 . i  as the final output  250 . 
         [0038]    In another alternate, the logic module  230  provides any set of the coefficients c 1  through c i  that cause the combining logic module  224  to provide any linear combination of the intermediate digital output signals  252 . 1  through  252 . i  as the final output  250  when the signal metric of the analog input signal  150  exceeds all non-clipping input values. In this situation, the logic module  230  usually provides the coefficients c 1  through c i  that cause the combining logic module  224  to provide one of the intermediate digital output signals  252 . 1  through  252 . i  associated with one of the ADCs  202 . 1  through  202 . i  having a largest non-clipping input value as the final output  250 . For example, the logic module  230  usually provides the coefficients c 1  through c i  that causes only the intermediate digital output signal  252 . i  to contribute to final output  250 . 
         [0039]      FIG. 3  is a flowchart of exemplary operational steps of a first logic module used in the composite ADC module according to a first embodiment of the present invention. The invention is not limited to this operational description. Rather, it will be apparent to persons skilled in the relevant art(s) from the teachings herein that other operational control flows are within the scope and spirit of the present invention. The following discussion describes the steps in  FIG. 3 . 
         [0040]    At step  302 , an operational control flow  300  selects a non-clipping input value from one or more non-clipping input values, such as the non-clipping input values m r1  through m ri . Each of the non-clipping input values may include a mean, a total energy, an average power, a mean square, an instantaneous power, a root mean square, a variance, a norm, a voltage level and/or any other suitable signal metric of an analog input signal, such as the analog signal  150  to provide an example, which will be apparent to one skilled in the relevant art(s). In an exemplary embodiment, the operational control flow  300  may include one or more thresholds, wherein each threshold from the one or more thresholds may be assigned to one of the non-clipping input values. 
         [0041]    At step  304 , the operational control flow  300  compares a signal metric of the analog input signal and the non-clipping input value of step  302 . The signal metric of the analog input signal may include the mean, the total energy, the average power, the mean square, the instantaneous power, the root mean square, the variance, the norm, the voltage level and/or any other suitable signal metric of the analog input signal which will be apparent to one skilled in the relevant art(s). 
         [0042]    At step  306 , the operational control flow  300  proceeds to step  308  when the signal metric from step  304  is greater than or equal to the non-clipping input value of step  302 . Otherwise, the operational control flow  300  proceeds to step  310  when the signal metric from step  304  is less than or equal to the non-clipping input value of step  302   
         [0043]    At step  308 , the signal metric from step  304  is greater than or equal to the non-clipping input value of step  302  and/or the another non-clipping input value from step  308 . The operational control flow  300  selects another non-clipping input value from the one or more non-clipping input values. The operational control flow  300  reverts back to step  306  to compare the signal metric of the analog input signal from step  304  and the another non-clipping input value. 
         [0044]    At step  310 , the signal metric from step  304  is less than or equal to the non-clipping input value of step  302 . The operational control flow  300  provides an indicator of the non-clipping input value of step  302  and/or the another non-clipping input value from step  308  that is greater than or equal to the signal metric from step  304 . The operational control flow  300  may provide a selection signal, such as the selection signal  254  to provide an example, that corresponds to the non-clipping input value of step  302  and/or the another non-clipping input value from step  308 . The selection signal causes one or more digital representations of the analog input signal corresponding to the non-clipping input value of step  302  and/or the another non-clipping input value from step  308  to be selected as a final digital output, such as the final output  250  to provide an example. Alternatively, the operational control flow  300  may provide a set of coefficients, such as the coefficients c 1  through c i  to provide an example, that corresponds to the non-clipping input value of step  302  and/or the another non-clipping input value from step  308 . The set of coefficients may be used to provide a linear combination of the one or more digital representations of the analog input signal as the final digital output. 
         [0045]      FIG. 4  illustrates a third block diagram of a composite ADC module according to a third embodiment of the present invention. A composite ADC module  400  converts the analog input signal  150  to a final digital output signal  450 . The composite ADC module  400  includes one or more first scaling modules  402 . 1  through  402 . i,  one or more ADCs  404 . 1  through  404 . i,  one or more second scaling modules  406 . 1  through  406 . i,  a combining logic module  408 , and a logic module  410 . 
         [0046]    The first scaling modules  402 . 1  through  402 . i  scale the analog input signal  150  by a scaling factor f 1  through f i  to provide one or more scaled analog input signals  452 . 1  through  452 . i.  More specifically, the first scaling modules  402 . 1  through  402 . i  divide the analog input signal  150  by the scaling factors f 1  through fto provide the scaled analog input signals  452 . 1  through  452 . i.  For example, the first scaling module  402 . 1  divides the analog input signal  150  by the scaling factor f 1  to provide the scaled analog input signal  452 . 1 . In an exemplary embodiment, the scaling factors f 1  through f i  are implemented in an increasing order such that a scaling factor having a lesser subscript, such as the scaling factor f 1  to provide an example, is smaller than a scaling factor having a greater subscript, such as the scaling factor f 2  to provide an example. 
         [0047]    The ADCs  404 . 1  through  404 . i  may include a corresponding scaling step size As. The scaling step size As for a respective ADC  404 . 1  through  404 . i  represents an effective quantization step size of the respective ADC  404 . 1  through  404 . i  referenced to the analog input signal  150 . The scaling step size Δ S  may be represented as: 
         [0000]      Δ s =(scaling factor)*(quantization step size),   (2) 
         [0000]    where Δ S  represents the scaling step size Δ S  of a respective one of the ADCs  404 . 1  through  404 . i,  scaling factor represents one of the scaling factors f 1  through f i  corresponding to the respective one of the ADCs  404 . 1  through  404 . i,  and quantization step size represents quantization step size of the respective one of the ADCs  404 . 1  through  404 . i.  For example, the scaling step size Δ S  of the ADCs  404 . 1  may be represented as: 
         [0000]      Δ S1 =( f   1  )*(Δ Q1 ),   (3) 
         [0000]    where Δ S1  represents the scaling step size Δ S  of the ADC  404 . 1 , f 1  represents the scaling factor f 1  corresponding to the ADC  404 . 1 , and Δ Q1  represents the quantization step size of the ADC  404 . 1  through  404 . i.  The first scaling module  402 . 1  through  402 . i  corresponding to the scaling factor having the lesser subscript, such as the first scaling module  402 . 1  to provide an example, have a lesser scaling step size As when compared to the first scaling modules  402 . 1  through  402 . i  corresponding to the scaling factor having the greater subscript. As a result of the lesser scaling step size As, a resolution of an ADC  402 . 1  through  402 . i  having a lesser subscript, such as the ADC  402 . 1  to provide an example, is substantially greater than or equal to a resolution of an ADC  402 . 1  through  402 . i  having a greater subscript, such as the ADC  402 . 2  to provide an example. 
         [0048]    The ADCs  404 . 1  through  404 . i  convert the scaled analog input signals  452 . 1  through  452 . i  to scaled digital output signals  454 . 1  through  454 . i.  Each of the ADCs  404 . 1  through  404 . i  may have a non-clipping input value m r , which in one embodiment, is substantially the same for each of the ADCs  404 . 1  through  404 . i.  The non-clipping input value m r  represents a value of the scaled analog input signals  452 . 1  through  452 . i  that when exceeded causes a corresponding ADC  404 . 1  through  404 . i  to clip. More specifically, the non-clipping input value m r  represents a ratio of the analog input signal  150  and a corresponding scaling factor f 1  through f i  that when exceeded causes the corresponding ADC  404 . 1  through  404 . i  to clip. For example, the ADC  404 . 1  clips when the ratio of the analog input signal  150  and the scaling factor f 1  exceeds the non-clipping input value m r . Likewise, the ADC  404 . i  clips when the ratio of the analog input signal  150  and the scaling factor f i  exceeds the non-clipping input value m r . 
         [0049]    One or more of the scaled analog input signals  452 . 1  through  452 . i  may be less than or equal to the non-clipping input value m r . In this situation, the ADCs  402 . 1  through  402 . i  having their corresponding non-clipping input value m r  greater than or equal to the one or more scaled analog input signals  452 . 1  through  452 . i  assign a unique digital value corresponding to one of n 1  through n k  quantization levels to p bits of the corresponding scaled digital output signal  454 . 1  through  454 . i.  The ADCs  402 . 1  through  402 . i  may include a similar number of quantization levels or a dissimilar number of quantization levels. In an exemplary embodiment, each of the p bits of the ADCs  404 . 1  through  404 . i  corresponds to an equivalent number of bits. In another exemplary embodiment, the ADCs  402 . 1  through  402 . i  having their corresponding non-clipping input value m r  greater than or equal to the analog input signal  150  compare a signal metric of the corresponding scaled analog input signal  452 . 1  through  452 . i  to one or more of n 1  through n k  quantization levels to assign the unique digital value. The signal metric of the corresponding scaled analog input signal  452 . 1  through  452 . i  may include the mean, the total energy, the average power, the mean square, the instantaneous power, the root mean square, the variance, the norm, the voltage level and/or any other suitable signal metric of the analog input signal  150  which will be apparent to one skilled in the relevant art(s). 
         [0050]    Alternatively, one or more of the scaled analog input signals  452 . 1  through  452 . i  may be greater than or equal to one or more of the non-clipping input value m r . In this situation, the ADCs  402 . 1  through  402 . i  having their corresponding non-clipping input value m r  less than or equal to the one or more scaled analog input signals  452 . 1  through  452 . i  assign the unique digital value corresponding to a maximum quantization level or a minimum quantization level to the p bits of the corresponding intermediate digital output signal  452 . 1  through  452 . i.    
         [0051]    In another alternate, all of the of the scaled analog input signals  452 . 1  through  452 . i  may be greater than or equal to one or more of the non-clipping input value m r . In this situation the ADCs  402 . 1  through  402 . i  assign the unique digital value corresponding to a maximum quantization level or a minimum quantization level to the p bits of the corresponding intermediate digital output signal  452 . 1  through  452 . i.    
         [0052]    The second scaling modules  406 . 1  through  406 . i  scale the scaled digital output signals  454 . 1  through  454 . i  by the corresponding scaling factor f 1  through f i  to provide composite digital output signals  456 . 1  through  456 . i.  More specifically, the second scaling modules  406 . 1  through  406 . i  multiply the scaled digital output signals  454 . 1  through  454 . i  by the corresponding scaling factor f 1  through f i . For example, the second scaling module  406 . 1  multiplies the scaled digital output signal  454 . 1  by the scaling factor f 1  to provide the composite digital output signal  456 . 1 . The scaling factors f 1  through f i  of the second scaling modules  406 . 1  through  406 . i  are substantially similar to the scaling factors f 1  through f i  of the first scaling modules  402 . 1  through  402 . i.  In an exemplary embodiment, the scaling factors f 1  , through f i  of the second scaling modules  406 . 1  through  406 . i  are equal to the scaling factors f 1  , through f i  of the first scaling modules  402 . 1  through  402 . i.    
         [0053]    In a first exemplary embodiment, the combining logic module  408  selects one of the composite digital output signals  456 . 1  through  456 . i  to represent the final digital output signal  450  based upon a logic control signal  458  in a similar manner as the combining logic module  204  as discussed above. The logic module  410  generates the logic control signal  458  based on a signal metric of the analog input signal  150 . The logic module  410  provides the logic control signal  458  that causes the combining logic module  408  to select a first composite digital output signal, such as the composite digital output  456 . 1  to provide an example, as the final output  450  when a ratio of a first scaling factor, such as the scaling factor f 1  to provide an example, and the signal metric of the analog input signal  150  is less than or equal the non-clipping input value m r . In an exemplary embodiment, the logic module  410  may include a threshold assigned to the non-clipping input value m r . For example, the logic module  410  provides the logic control signal  458  that causes the combining logic module  408  to select the first composite digital output signal when the ratio of a first scaling factor, such as the scaling factor f 1  to provide an example, and the signal metric of the analog input signal  150  is less than or equal the threshold. However, this example is not limiting, the logic module  410  may utilize other means to provide the logic control signal  458  differently in accordance with the teaching herein without departing from the sprit and scope of the present invention. 
         [0054]    Alternatively, the logic module  410  provides the logic control signal  458  that causes the combining logic module  408  to select a second composite digital output signal, such as the composite digital output signal  456 . 2  to provide an example, as the final output  450  when a ratio of a second scaling factor, such as the scaling factor f 2  to provide an example, and the signal metric of the analog input signal  150  is less than or equal to the non-clipping input value m r  and the ratio of the first scaling factor and the signal metric of the analog input signal  150  is greater than the non-clipping input value m r . However, if the ratio of the first scaling factor and the signal metric of the analog input signal  150  returns to being less than or equal non-clipping input value m r , the logic module  410  provides the logic control signal  458  that causes the combining logic module  408  to once again select the first composite digital output signal as the final output  450 . 
         [0055]    In another alternate, the logic module  410  provides the logic control signal  458  that causes the combining logic module  408  to select any of the composite digital output signals  456 . 1  through  456 . i  as the final output  450  when ratios for each of the scaling factors f 1  through f i  and the signal metric of the analog input signal  150  exceed the non-clipping input value m r . In this situation, the logic module  410  usually produces the logic control signal  458  that causes the combining logic module  408  to select the composite digital output signal  456 . 1  through  456 . i  corresponding to a combination of a first scaling module  402 . 1  through  402 . i  and a second scaling module  406 . 1  through  406 . i  corresponding to a maximum scaling factor, such as the scaling factor f i  to provide an example. 
         [0056]    Alternatively, in a second exemplary embodiment, the combining logic module  408  may provide one or more linear combinations of the composite digital output signals  456 . 1  through  456 . i  to represent the final digital output signal  450  based upon the logic control signal  458  in a similar manner as the combining logic module  224  as discussed above. 
         [0057]    The logic module  410  provides a first set of the coefficients c 1  through c i  that cause the combining logic module  408  to provide a first linear combination of the composite digital output signals  456 . 1  through  456 . i  as the final output  450  when a ratio of a first scaling factor, such as the scaling factor f 1  to provide an example, and the signal metric of the analog input signal  150  is less than or equal the non-clipping input value m r . In an exemplary embodiment, the logic module  410  may include a threshold assigned to the non-clipping input value m r . For example, the logic module  410  provides the first set of the coefficients c 1  through c i  that cause the combining logic module  408  to provide a first linear combination of the composite digital output signals  456 . 1  through  456 . i  as the final output  450  when a ratio of a first scaling factor, such as the scaling factor f 1  to provide an example, and the signal metric of the analog input signal  150  is less than or equal to the threshold. However, this example is not limiting, the logic module  410  may utilize other means to provide the logic control signal  458  differently in accordance with the teaching herein without departing from the sprit and scope of the present invention. 
         [0058]    Alternatively, the logic module  410  provides a second set of the coefficients c 1  through c i  that cause the combining logic module  408  to provide a second linear combination of the composite digital output signals  456 . 1  through  456 . i  as the final output  450  when a ratio of a second scaling factor, such as the scaling factor f 2  to provide an example, and the signal metric of the analog input signal  150  is less than or equal to the non-clipping input value m r  and the ratio of the first scaling factor and the signal metric of the analog input signal  150  is greater than the non-clipping input value m r . However, if the ratio of the first scaling factor and the signal metric of the analog input signal  150  returns to being less than or equal non-clipping input value m r , the logic module  410  provides the first set of the coefficients c 1  through c i  that causes the combining logic module  408  to once again provide the first linear combination of the composite digital output signals  456 . 1  through  456 . i  as the final output  450 . 
         [0059]    In another alternate, the logic module  410  provides any set of the coefficients c 1  through c i  that cause the combining logic module  408  to provide any linear combination of the composite digital output signals  456 . 1  through  456 . i  as the final output  450  when ratios for each of the scaling factors f 1  through fand the signal metric of the analog input signal  150  exceed the non-clipping input value m r . In this situation, the combining logic module  408  usually provides the coefficients c 1  through c i  that cause the combining logic module  408  to provide one of the composite digital output signals  456 . 1  through  456 . i  associated with one of the ADCs  404 . 1  through  404 . i  having a largest scaling factor as the final output  450 . For example, the combining logic module  408  usually provides the coefficients c 1  through c i  that causes only the composite digital output signal  456 . i  to contribute to final output  250 . 
         [0060]    In a further alternate, the second scaling modules  406 . 1  through  406 . i  are optional. In this situation, the scaling factors f 1  through f i  corresponding to the second scaling modules  406 . 1  through  406 . i  may be incorporated into the coefficients c 1  through c i  by the logic module  410 . 
         [0061]      FIG. 5  is a flowchart of exemplary operational steps of a second logic module used in the composite ADC module according to a second aspect of the present invention. The invention is not limited to this operational description. Rather, it will be apparent to persons skilled in the relevant art(s) from the teachings herein that other operational control flows are within the scope and spirit of the present invention. The following discussion describes the steps in  FIG. 5 . 
         [0062]    At step  502 , an operational control flow  500  selects a scaling factor from one or scaling factors, such as the scaling factor f 1  through f i . 
         [0063]    At step  504 , the operational control flow  500  compares a ratio of a signal metric of an analog input and the scaling factor from step  502  to a non-clipping input value, such as the non-clipping input value m r  to provide an example. The non-clipping input value represents a ratio of the signal metric of the analog input signal and the scaling factor from step  502  that when exceeded causes one or more ADCs, such as the ADCs  404 . 1  through  404 . i  to provide an example, to clip. The signal metric of the analog input signal may include the mean, the total energy, the average power, the mean square, the instantaneous power, the root mean square, the variance, the norm, the voltage level and/or any other suitable signal metric of the analog input signal which will be apparent to one skilled in the relevant art(s). 
         [0064]    At step  506 , the operational control flow  500  proceeds to step  508  when the ratio of the signal metric of an analog input from step  504  and the scaling factor from step  502  is greater than or equal to the non-clipping input value of step  504 . Otherwise, the operational control flow  500  proceeds to step  510  when the ratio of the signal metric of the analog input from step  504  and the scaling factor from step  502  is less than or equal to the non-clipping input value of step  502 . 
         [0065]    At step  508 , the ratio of the signal metric of the analog input from step  504  and the scaling factor from step  502  is greater than or equal to the non-clipping input value of step  502  and/or the another non-clipping input value from step  508 . The operational control flow  500  selects another scaling factor from the one or more scaling factors. The operational control flow  500  reverts back to step  506  to compare the ratio of the signal metric of an analog input and the another scaling factor to the non-clipping input value. 
         [0066]    At step  510 , the ratio of the signal metric of the analog input from step  504  and the scaling factor from step  502  is less than or equal to the non-clipping input value of step  502 . The operational control flow  500  provides an indicator of the scaling factor of step  502  being greater than a ratio of the signal metric of the analog input from step  504  and the non-clipping input value of step  502 . The operational control flow  500  may provide a logic control signal, such as the logic control signal  410  to provide an example, that corresponds to the scaling factor of step  502 . The logic control signal causes one or more digital representations of the analog input signal corresponding to the logic control signal to be selected as a final digital output, such as the final output  450  to provide an example. Alternatively, the operational control flow  500  may provide a set of coefficients, such as the coefficients c 1  through c i  to provide an example, via the logic control signal that corresponds to the scaling factor of step  502 . The set of coefficients may be used to provide a linear combination of the one or more digital representations of the analog input signal as the final digital output. 
         [0067]      FIG. 6  illustrates a fourth block diagram of a composite ADC module according to a fourth embodiment of the present invention. A composite ADC module  600  converts the analog input signal  150  to a final digital output signal  450 . The composite ADC module  600  includes the first scaling modules  402 . 1  through  402 . i,  the second scaling modules  406 . 1  through  406 . i,  the combining logic module  408 , a selecting module  602 , an ADC  604 , and a logic module  606 . 
         [0068]    The first scaling modules  402 . 1  through  402 . i  scale the analog input signal  150  by the scaling factors f 1  through f i , as discussed above, to provide the scaled analog input signals  452 . 1  through  452 . i.  More specifically, the first scaling modules  402 . 1  through  402 . i  divide the analog input signal  150  by the scaling factors f 1  through f i  to provide the scaled analog input signals  452 . 1  through  452 . i.    
         [0069]    The ADC  604  converts the final analog input signal  652  to a scaled digital output signal  654 . The ADC  604  may have a non-clipping input value m r . The non-clipping input value m r  represents a value of the final analog input signal  652  that when exceeded causes the ADC  604  to clip. More specifically, the non-clipping input value m r  represents a ratio of the analog input signal  150  and a corresponding scaling factor f 1  through f i  that when exceeded causes the ADC  604  to clip. For example, the ADC  604  clips when the ratio of the analog input signal  150  and the scaling factor f 1  exceeds the non-clipping input value m r . 
         [0070]    The selecting module  602  selects one of the scaled analog input signals  452 . 1  through  452 . i  to represent a final analog input signal  652  based upon an analog selection signal  656 . Alternatively, the selecting module  602  selects more than one of the scaled analog input signals  452 . 1  through  452 . i  in a sequence using a track-and-hold functionality. In this situation, the first scaling modules  402 . 1  through  402 . i  includes the track-and-hold functionality such that each of the scaled analog input signals  452 . 1  through  452 . i  represents a sample of the analog input signal  150  at substantially similar instance in time with a different scaling factor f 1  through f i  applied. With either one or more than one scaled sample from a given sampling time, one or more of the scaled analog input signals  452 . 1  through  452 . i  may be less than or equal to the non-clipping input value m r . In this situation, the selecting module  602  selects the scaled analog input signal  452 . 1  through  452 . i  corresponding to a greatest scaling factor that is less than or equal to the non-clipping input value m r  to represent the final analog input signal  652 . The ADC  604  assigns a unique digital value corresponding to one of n 1  through n k  quantization levels to r bits of the scaled digital output signal  654 . In an exemplary embodiment, the ADC  604  compares a signal metric of the final analog input signal  652  to one or more of the n 1  through n k  quantization levels to assign the unique digital value. The signal metric of the final analog input signal  652  may include the mean, the total energy, the average power, the mean square, the instantaneous power, the root mean square, the variance, the norm, the voltage level and/or any other suitable signal metric of the analog input signal  150  which will be apparent to one skilled in the relevant art(s). 
         [0071]    Alternatively, all of the of the scaled analog input signals  452 . 1  through  452 . i  may be greater than or equal to the non-clipping input value m r . The selecting module  602  selects any one of the scaled analog input signals  452 . 1  through  452 . i  to represent the final analog input signal  652 . In this situation, the selecting module  602  usually selects the scaled analog input signal  452 . 1  through  452 . i  corresponding to a greatest scaling factor. The ADC  604  assigns the unique digital value corresponding to a maximum quantization level or a minimum quantization level to the r bits of the scaled digital output signal  654 . 
         [0072]    The second scaling modules  406 . 1  through  406 . i  scale the scaled digital output signal  654  by the corresponding scaling factor f 1  through f i  to provide composite digital output signals  456 . 1  through  456 . i.  More specifically, the second scaling modules  406 . 1  through  406 . i  multiply the scaled digital output signals  454 . 1  through  454 . i  by the corresponding scaling factor f 1  through f i . 
         [0073]    In a first exemplary embodiment, the combining logic module  408  selects one of the composite digital output signals  456 . 1  through  456 . i  to represent the final digital output signal  450  based upon a logic control signal  458  as discussed above. Alternatively, in a second exemplary embodiment, the combining logic module  408  may provide one or more linear combinations of the composite digital output signals  456 . 1  through  456 . i  to represent the final digital output signal  450  based upon the logic control signal  458  in a similar manner as discussed above. 
         [0074]    The logic module  606  provides the logic control signal  458  in a similar manner as the logic module  410  as discussed above. In an exemplary embodiment, the analog selection signal  656  is equal to the logic control signal  458 . In another exemplary embodiment, the logic module  606  generates the analog selection signal  656  based on the signal metric of the analog input signal  150 . The logic module  606  provides the analog selection signal  656  that causes the selecting module  602  to select a scaled analog input signal, such as scaled analog input signal  452 . 1  to provide an example, as the final analog input signal  652  when a ratio of a first scaling factor, such as the scaling factor f 1  to provide an example, and the signal metric of the analog input signal  150  is less than or equal the non-clipping input value m r . 
         [0075]    Alternatively, the logic module  606  provides the analog selection signal  656  that causes the selecting module  602  to select any of the scaled analog input signals  452 . 1  through  452 . i  as the final analog input signal  652  when ratios for each of the scaling factors f 1  through f i  and the signal metric of the analog input signal  150  exceed the non-clipping input value m r . In this situation, the logic module  606  usually produces the analog selection signal  656  that causes the selecting module  602  to select the scaled analog input signal  452 . 1  through  452 . i  corresponding to a greatest scaling factor. 
         [0076]      FIG. 7  is a flowchart of exemplary operational steps of a third logic module used in the composite ADC module according to a third aspect of the present invention. The invention is not limited to this operational description. Rather, it will be apparent to persons skilled in the relevant art(s) from the teachings herein that other operational control flows are within the scope and spirit of the present invention. The following discussion describes the steps in  FIG. 7 . 
         [0077]    At step  702 , an operational control flow  700  selects a scaling factor from one or scaling factors, such as the scaling factor f 1  through f i . 
         [0078]    At step  704 , the operational control flow  700  compares a ratio of a signal metric of an analog input and the scaling factor from step  702  to a non-clipping input value, such as the non-clipping input value m r  to provide an example. The non-clipping input value represents a ratio of the signal metric of the analog input signal and the scaling factor from step  702  that when exceeded causes one or more ADCs, such as the ADCs  404 . 1  through  404 . i  to provide an example, to clip. The signal metric of the analog input signal may include the mean, the total energy, the average power, the mean square, the instantaneous power, the root mean square, the variance, the norm, the voltage level and/or any other suitable signal metric of the analog input signal which will be apparent to one skilled in the relevant art(s). 
         [0079]    At step  706 , the operational control flow  700  proceeds to step  708  when the ratio of the signal metric of an analog input from step  704  and the scaling factor from step  702  is greater than or equal to the non-clipping input value of step  704 . Otherwise, the operational control flow  700  proceeds to step  710  when the ratio of the signal metric of the analog input from step  704  and the scaling factor from step  702  is less than or equal to the non-clipping input value of step  702 . 
         [0080]    At step  708 , the ratio of the signal metric of the analog input from step  704  and the scaling factor from step  702  is greater than or equal to the non-clipping input value of step  702  and/or the another non-clipping input value from step  708 . The operational control flow  700  selects another scaling factor from the one or more scaling factors. The operational control flow  700  reverts back to step  706  to compare the ratio of the signal metric of an analog input and the another scaling factor to the non-clipping input value. 
         [0081]    At step  710 , the ratio of the signal metric of the analog input from step  704  and the scaling factor from step  702  is less than or equal to the non-clipping input value of step  702 . The operational control flow  700  provides an indicator of the scaling factor of step  702  being greater than a ratio of the signal metric of the analog input from step  704  and the non-clipping input value of step  702 . The operational control flow  700  may provide one or more logic control signals, such as the logic control signal  410  and/or the analog selection signal  656  to provide some examples, that corresponds to the scaling factor of step  702 . The logic control signals cause one or more digital representations of the analog input signal corresponding to the logic control signals to be selected as a final digital output, such as the final output  450  to provide an example. Alternatively, the operational control flow  700  may provide a set of coefficients, such as the coefficients c 1  through c i  to provide an example, via the logic control signals that corresponds to the scaling factor of step  702 . The set of coefficients may be used to provide a linear combination of the one or more digital representations of the analog input signal as the final digital output. 
       CONCLUSION 
       [0082]    It is to be appreciated that the Detailed Description section, and not the Abstract section, is intended to be used to interpret the claims. The Abstract section may set forth one or more, but not all exemplary embodiments, of the present invention, and thus, are not intended to limit the present invention and the appended claims in any way. 
         [0083]    The present invention has been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries may be defined so long as the specified functions and relationships thereof are appropriately performed. 
         [0084]    It will be apparent to those skilled in the relevant art(s) that various changes in form and detail may be made therein without departing from the spirit and scope of the invention. Thus, the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.