Abstract:
Decoding apparatus comprises EX-OR circuit exclusive ORing the Reed-Muller code and exclusive Ored value of mask symbol candidate pattern and the information data corresponding to the pattern, first decoder calculating checksum of the EX-OR circuit output and majority-judging the checksum to decode a part of the second portion of the information data, second decoder exclusive ORing the EX-OR circuit output and a product of the part of the second portion and the orthogonal codes and majority-judging the exclusive OR result to decode a remaining part of the second portion, Reed-Muller encoder encoding the information data, and minimum detector detecting the minimum of Euclidean distance between an output from the Reed-Muller encoder and the Reed-Muller code supplied to the arithmetic operation unit while a plurality of candidate patterns of the mask symbols are supplied to the arithmetic operation unit.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-092163, filed Mar. 29, 2000; and No. 2001-071358, filed Mar. 14, 2001, the entire contents of both of which are incorporated herein by reference. 
   BACKGROUND OF THE INVENTION 
   The present invention relates to Reed-Muller decoding apparatus and decoding method. 
   Reed-Muller code is known as a kind of error correction code. An ordinary Reed-Muller code is (32, 6) Reed-Muller code for converting 6-bit information data into a 32-bit code word. For the Reed-Muller code, it is known that, suppose n=2 m  (n is a code length, m is a natural number (if n=32, m=5)), the minimum Euclidean distance between code words is 2 m-r  (r is an order of code). In general, if the minimum Euclidean distance between code words is longer, the error correction code has better performance (resistant to errors). However, the longer the minimum Euclidean distance, the lower the transmission rate or coding efficiency. Therefore, in order to improve the performance of the Reed-Muller code without greatly lowering the transmission rate, a method is proposed to increase the minimum Euclidean distance by adding mask symbols to the conventional Reed-Muller code (3rd Generation Partnership Project; Technical Specification Group Radio Access Network; Multiplexing and channel coding (FDD) (Release 1999) 3G TS 25.212 V3.3.0 (2000-06). This code is called “(32, 10) Reed-Muller code” for converting a total 10-bit information data where 4-bit mask symbols are added to a 6-bit information data into a 32-bit code word. 
   It is known that the Reed-Muller code decoding apparatus can be realized by a simple majority decision circuit (Jpn. Pat. Appln. KOKAI Publication No. 9-74359). The majority decision circuit for (32, 6) Reed-Muller code can be realized relatively easily. However, for (32, 10) Reed-Muller code, it is difficult to calculate the checksum to be determined for the majority decision. 
   As an example of decoding without using a majority decision circuit, a maximum likelihood decoding by calculating a correlation value is known (Harmonization impact of TFCI and New Optimal Coding for extended TFCI with almost no complexity increase (rev 1) TSGR #6 (99) 970). However, calculating the correlation of all code words for a received coded signal, essentially, operation load is high in this method, increasing the hardware scale; therefore, this method is difficult to realize for (32, 10) Reed-Muller code. 
   As mentioned above, it has been difficult to realize the decoding apparatus for recently proposed Reed-Muller code containing mask symbols which is resistant to the error. 
   BRIEF SUMMARY OF THE INVENTION 
   Accordingly, the present invention is directed to method and apparatus that substantially obviates one or more of the problems due to limitations and disadvantages of the related art. 
   In accordance with the purpose of the invention, as embodied and broadly described, the invention is directed to reduce the operation load and hardware scale of the decoding apparatus using mask symbols. 
   According to the present invention, there is provided an apparatus for decoding Reed-Muller code in which information data is encoded by using mask symbols and orthogonal codes, the information data including a first portion and a second portion, the apparatus comprising: 
   an arithmetic operation unit configured to calculate a first exclusive OR of the Reed-Muller code and an exclusive ORed value of a candidate pattern of the mask symbols and the information data corresponding to the candidate pattern; 
   a first decoder configured to calculate a checksum of the first exclusive OR and majority-decide the checksum to decode a part of the second portion of the information data corresponding to the orthogonal codes; 
   a second decoder configured to calculate a second exclusive OR of the first exclusive OR and a product of the part of the second portion of the information data and the orthogonal codes and majority-decide the second exclusive OR to decode a remaining part of the second portion of the information data corresponding to the orthogonal codes; 
   a Reed-Muller encoder configured to Reed-Muller encode the second portion of the information data output from the first decoder and the second decoder and the first portion of the information data; 
   a minimum distance detector configured to detect the minimum of a Euclidean distance between an output from the Reed-Muller encoder and the Reed-Muller code supplied to the arithmetic operation unit while a plurality of candidate patterns of the mask symbols are supplied to the arithmetic operation unit, 
   whereby the first portion of the information data is decoded based on the mask symbols corresponding to the minimum of the Euclidean distance. 
   According to the present invention, there is provided a method of decoding Reed-Muller code in which information data is encoded by using mask symbols and orthogonal codes, the information data including a first portion and a second portion, the method comprising: 
   calculating a first exclusive OR of the Reed-Muller code and an exclusive ORed value of a candidate pattern of the mask symbols and the information data corresponding to the candidate pattern; 
   calculating a checksum of the first exclusive OR and majority-judging the checksum to decode a part of the second portion of the information data corresponding to the orthogonal codes; 
   calculating a second exclusive OR of the first exclusive OR and a product of the part of the second portion of the information data and the orthogonal codes and majority-judging the second exclusive OR to decode a remaining part of the second portion of the information data corresponding to the orthogonal codes; 
   Reed-Muller encoding the decoded second portion of the information data and the first portion of the information data; and 
   detecting the minimum of a Euclidean distance between the Reed-Muller encoded data and an input Reed-Muller code while a plurality of first exclusive ORs are calculated, whereby the first portion of the information data is decoded based on the mask symbols corresponding to the minimum of the Euclidean distance. 
   According to the present invention, there is provided another apparatus for decoding Reed-Muller code in which information data is encoded by using mask symbols and orthogonal codes, the information data including a first portion and a second portion, the apparatus comprising: 
   an arithmetic operation unit configured to calculate a first product of the Reed-Muller code and an exclusive ORed value of a candidate pattern of the mask symbols and the information data corresponding to the candidate pattern; 
   a first decoder configured to calculate a checksum of the first product and majority-decide the checksum to decode a part of the second portion of the information data corresponding to the orthogonal codes; 
   a second decoder configured to calculate a second product of the first product and a product of the part of the second portion of the information data and the orthogonal codes and majority-decides the second product to decode a remaining part of the second portion of the information data corresponding to the orthogonal codes; 
   a Reed-Muller encoder configured to Reed-Muller encode the second portion of the information data output from the first decoder and the second decoder and the first portion of the information data; 
   a maximum correlation detector configured to detect the maximum of a correlation between an output from the Reed-Muller encoder and the Reed-Muller code supplied to the arithmetic operation unit while a plurality of candidate patterns of the mask symbols are supplied to the arithmetic operation unit, 
   whereby the first portion of the information data is decoded based on the mask symbols corresponding to the maximum of the correlation. 
   According to the present invention, there is provided another method of decoding Reed-Muller code in which information data is encoded by using mask symbols and orthogonal codes, the information data including a first portion and a second portion, the method comprising: 
   calculating a first product of the Reed-Muller code and an exclusive ORed value of a candidate pattern of the mask symbols and the information data corresponding to the candidate pattern; 
   calculating a checksum of the first product and majority-decide the checksum to decode a part of the second portion of the information data corresponding to the orthogonal codes; 
   calculating a second product of the first product and a product of the part of the second portion of the information data and the orthogonal codes and majority-decides the second product to decode a remaining part of the second portion of the information data corresponding to the orthogonal codes; 
   Reed-Muller encoding the second portion of the information data and the first portion of the information data; 
   detecting the maximum of a correlation between the Reed-Muller encoded data and an input Reed-Muller code while a plurality of first products are calculated, whereby the first portion of the information data is decoded based on the mask symbols corresponding to the maximum of the correlation. 

   
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING 
       FIG. 1  shows the first embodiment of the decoding apparatus according to the present invention; 
       FIG. 2  is a flow chart showing an operation flow of the first embodiment; 
       FIG. 3  shows a modification of the checksum calculator and the majority decision circuit of the first embodiment; 
       FIG. 4  shows the second embodiment of the decoding apparatus according to the present invention; 
       FIG. 5  is a flow chart showing an operation flow of the second embodiment; 
       FIG. 6  shows the third embodiment of the decoding apparatus according to the present invention; 
       FIG. 7  is a flow chart showing an operation flow of the third embodiment; 
       FIG. 8  shows a modification of the checksum calculator and the majority decision circuit of the third embodiment; 
       FIG. 9  shows the fourth embodiment of the decoding apparatus according to the present invention; and 
       FIG. 10  is a flow chart showing an operation flow of the fourth embodiment. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   An embodiment of a decoding apparatus according to the present invention will now be described with reference to the accompanying drawings. 
   First Embodiment 
     FIG. 1  shows a decoding apparatus of (32, 10) Reed-Muller code according to the first embodiment of the present invention. In (32, 10) Reed-Muller code, as the mask symbols are selected by 4-bit information data, patterns of the mask symbols (mask patterns) are 2 4 =16 patterns in total. 
   The following definition will be used for the description below. 
   “^” means an exclusive OR operation. For two vectors, A and B, “A^B” represents the exclusive OR of components of respective vectors A and B. 
   m(A) represents the vector A in which each of components 0 and 1 is changed to +1 and −1. 
   10-bit information data to be encoded are assumed to be d 0 , d 1 , d 2 , d 3 , d 4 , d 5 , d 6 , d 7 , d 8  and d 9 . Each bit data d n  is 0 or 1. 
   Orthogonal codes used for encoding are assumed to be C 0 , C 1 , C 2 , C 3 , C 4  and C 5 . Each code C n  is a 32-bit data, and 32 elements thereof are 0 or 1. Note that C 0  is a series of all 1. 
   Similarly, assuming mask symbols used for encoding be M 1 , M 2 , M 3  and M 4 . Each mask symbol M n  is a 32-bit data. The mask patterns d 6 M 1 ^d 7 M 2 ^d 8 M 3 ^d 9 M 4 , which are exclusive ORs of the mask symbols and the information data, have 24=16 patterns. 
   Examples of the orthogonal codes C 0  to C 5  and the mask symbols M 1  to M 4  are shown in Table 1. 
   
     
       
             
             
             
             
             
             
             
             
             
             
             
           
             
             
             
             
             
             
             
             
             
             
             
           
         
             
               TABLE 1 
             
             
                 
             
             
               i 
               C i,0   
               C i,1   
               C i,2   
               C i,3   
               C i,4   
               C i,5   
               M i.1   
               M i,2   
               M i,3   
               M i,4   
             
             
                 
             
           
           
             
                 
             
           
        
         
             
               0 
               1 
               0 
               0 
               0 
               0 
               1 
               0 
               0 
               0 
               0 
             
             
               1 
               1 
               0 
               0 
               0 
               1 
               0 
               1 
               0 
               0 
               0 
             
             
               2 
               1 
               0 
               0 
               0 
               1 
               1 
               0 
               0 
               0 
               1 
             
             
               3 
               1 
               0 
               0 
               1 
               0 
               0 
               1 
               0 
               1 
               1 
             
             
               4 
               1 
               0 
               0 
               1 
               0 
               1 
               0 
               0 
               0 
               1 
             
             
               5 
               1 
               0 
               0 
               1 
               1 
               0 
               0 
               0 
               1 
               0 
             
             
               6 
               1 
               0 
               1 
               1 
               1 
               1 
               0 
               1 
               0 
               0 
             
             
               7 
               1 
               0 
               1 
               0 
               0 
               0 
               0 
               1 
               1 
               0 
             
             
               8 
               1 
               0 
               1 
               0 
               0 
               1 
               1 
               1 
               1 
               0 
             
             
               9 
               1 
               0 
               1 
               0 
               1 
               0 
               1 
               0 
               1 
               1 
             
             
               10 
               1 
               0 
               1 
               0 
               1 
               1 
               0 
               0 
               1 
               1 
             
             
               11 
               1 
               0 
               1 
               1 
               0 
               0 
               0 
               1 
               1 
               0 
             
             
               12 
               1 
               0 
               1 
               1 
               0 
               1 
               0 
               1 
               0 
               1 
             
             
               13 
               1 
               0 
               1 
               1 
               1 
               0 
               1 
               0 
               0 
               1 
             
             
               14 
               1 
               0 
               1 
               1 
               1 
               1 
               1 
               1 
               1 
               1 
             
             
               15 
               1 
               1 
               0 
               0 
               0 
               1 
               1 
               1 
               0 
               0 
             
             
               16 
               1 
               1 
               0 
               0 
               1 
               0 
               1 
               1 
               0 
               1 
             
             
               17 
               1 
               1 
               0 
               0 
               1 
               1 
               1 
               0 
               1 
               0 
             
             
               18 
               1 
               1 
               0 
               1 
               0 
               0 
               0 
               1 
               1 
               1 
             
             
               19 
               1 
               1 
               0 
               1 
               0 
               1 
               0 
               1 
               0 
               1 
             
             
               20 
               1 
               1 
               0 
               1 
               1 
               0 
               0 
               0 
               1 
               1 
             
             
               21 
               1 
               1 
               0 
               1 
               1 
               1 
               0 
               1 
               1 
               1 
             
             
               22 
               1 
               1 
               1 
               0 
               0 
               0 
               0 
               1 
               0 
               0 
             
             
               23 
               1 
               1 
               1 
               0 
               0 
               1 
               1 
               1 
               0 
               1 
             
             
               24 
               1 
               1 
               1 
               0 
               1 
               0 
               1 
               0 
               1 
               0 
             
             
               25 
               1 
               1 
               1 
               0 
               1 
               1 
               1 
               0 
               0 
               1 
             
             
               26 
               1 
               1 
               1 
               1 
               0 
               0 
               0 
               0 
               1 
               0 
             
             
               27 
               1 
               1 
               1 
               1 
               0 
               1 
               1 
               1 
               0 
               0 
             
             
               28 
               1 
               1 
               1 
               1 
               1 
               0 
               1 
               1 
               1 
               0 
             
             
               29 
               1 
               1 
               1 
               1 
               1 
               1 
               1 
               1 
               1 
               1 
             
             
               30 
               1 
               0 
               0 
               0 
               0 
               0 
               0 
               0 
               0 
               0 
             
             
               31 
               1 
               1 
               0 
               0 
               0 
               0 
               1 
               0 
               0 
               0 
             
             
                 
             
           
        
       
     
   
   An encoding apparatus encodes the aforementioned information data “d” based on the orthogonal codes C 0  to C 5  and the mask symbols M 1  to M 4 , and outputs the following 32-bit coded signal “s.” Here, the orthogonal codes and the mask symbols to be multiplied with each bit of the information data are predetermined.
 
s=d 0 C 0 ^d 1 C 1 ^d 2 C 2 ^d 3 C 3 ^d 4 C 4 ^d 5 C 5 ^d 6 M 1 ^d 7 M 2 ^d 8 M 3 ^d 9 M 4   (1)
 
   The 32-bit coded signal “s” is modulated and output as m(s). In this embodiment, the following signal in which an error due to transfer path or noise is added to the modulated signal m(s) is input to the decoding apparatus of  FIG. 1 , and hard-decided by a hard decision unit  10 . 
   The hard decision unit  10  reproduces the original values 0 and 1, when the value +1 and −1 corresponding to the original values 0 and 1 becomes other values such as 0.2, 1.8, −1.2 or the like due to noise or the like. Thus, the hard decision unit  10  outputs a sum of the 32-bit coded signal “s” and an error signal “e.” 
   A memory  12  stores the orthogonal codes C 0  to C 5 , the mask symbols M 1  to M 4  of Table 1, and 16 mask patterns d 6 M 1 ^d 7 M 2 ^d 8 M 3 ^d 9 M 4  not shown in Table 1. Here, “i” represents a bit position. 
   An exclusive OR circuit  14  calculates an exclusive OR of one of the mask patterns stored in the memory  12  and the output from the hard decision circuit  10 . 
   An output from the exclusive OR circuit  14  is supplied to a checksum calculator  16 . The calculator  16  calculates 16 checksums for each of 5 bits of d 1  to d 5  (80 checksums in total), among 10-bit information data d 0  to d 9 . 
   A majority decision unit  18  decides a majority of the 80 checksums output from the checksum calculator  16  to decode bits d 1 ′ to d 5 ′ corresponding to the orthogonal codes C 1  to C 5 . To be more specific, concerning the checksum, it is decided to be 0 if 0 is majority, and 1 if 1 is majority. 
   An orthogonal code multiplier  20  multiplies 5-bit data d 1 ′ to d 5 ′ by the orthogonal codes. 
   An exclusive OR circuit  22  calculates an exclusive OR of the exclusive OR output from the exclusive OR circuit  14  and the output from the orthogonal code multiplier  20 . A majority decision unit  24  decides a majority of the exclusive OR output from the exclusive OR circuit  22  to decode bit d 0 ′. To be more specific, concerning the exclusive OR, it is decided to be 0 if 0 is majority, and 1 if 1 is majority. When the bit d 0 ′ of the information data is determined by the majority decision unit  24 , bits d 6 ′ to d 9 ′ of the information data can be determined based on the mask pattern used for determining the bit d 0 ′. 
   The operation mentioned above, i.e., exclusive ORing the Reed-Muller code input to the decoding apparatus and the exclusive OR of the mask pattern and the information data, allows to exclude the mask pattern from the Reed-Muller code. The Reed-Muller code excluding the mask pattern is easily majority-decided. The bit data d 0 ′ to d 9 ′ are determined by multiplying the result of the majority-decision by the orthogonal codes. The bit data d 0 ′ to d 9 ′ are Reed-Muller encoded by a Reed-Muller encoder  26 . The output from the Reed-Muller encoder  26  is supplied to a Euclidean distance calculator  28 . The Euclidean distance between the output from the Reed-Muller encoder  26  and the received coded signal output from the hard decision unit  10  is calculated. 
   The aforementioned processing is performed for all 16 kinds of mask patterns, and the minimum Euclidean distance is detected by a minimum distance detector  30 . Bit data d 0 ′ to d 9 ′ at the time when the minimum distance is detected are considered to be correct, completing the decoding. 
     FIG. 2  is a flow chart of the first embodiment. 
   In step S 10 , the hard decision unit  10  hard-decides the coded signal. The coded signal input in this decoding apparatus is not the modulated signal m(s) output from the encoding apparatus, but the following signal in which error “e” due to transfer path or noise is added to m(s). 
    d 0 C 0  {circumflex over ( 0  )}d 1 C 1  {circumflex over ( 0  )}d 2 C 2  {circumflex over ( 0  )}d 3 C 3  {circumflex over ( 0  )}d 4 C 4  {circumflex over ( 0  )}d 5 C5 {circumflex over ( 0  )}d 6 M 1 {circumflex over ( 0  )}d 7 M 2 {circumflex over ( 0  )}d 8 M 3  {circumflex over ( 0  )}d 9 M 4 {circumflex over ( 0  )}e  (2) 
   In the hard decision, the original values 0 and 1 are reproduced when the values +1 and −1 corresponding to the original values 0 and 1 become other values such as 0.2, 1.8, −1.2 or the like due to noise or the like. 
   One mask pattern is specified in step S 12 , this specified mask pattern is read out from the memory  12  in step S 14 , and the exclusive OR circuit  14  calculates in step S 16  the exclusive OR of the coded signal output from the hard decision unit  10  and the mask pattern. 
   The memory  12  stores the orthogonal codes C 0  to C 5 , mask symbols M 1  to M 4 , and 16 mask patterns d 6 M 1 ^d 7 M 2 ^d 8 M 3 ^d 9 M 4  not shown in Table 1. “i” represents a bit position. 
   Supposing the mask pattern read out from the memory  12  be M′=d 6 ′M 1 ^d 7 ′M 2 ^d 8 ′M 3 ^d 9 ′M 4 , the exclusive OR output from the exclusive OR circuit  14  will be as follows.
 
d 0 C 0 ^d 1 C 1 ^d 2 C 2 ^d 3 C 3 ^d 4 
 
C 4 ^d 5 C 5 ^(d 6 ^d 6 ′)M 1 ^(d 7 
 
^d 7 ′)M 2 ^(d 8 ^d 8 ′)M 3 ^(d 9 ^
 
d 9 ′)M 4 ^e  (3)
 
   In step S 18 , the checksum calculator  16  calculates the checksum of the expression (3) output from the exclusive OR circuit  14 . Respectively,  16  checksums are calculated for 5 bits of d 1  to d 5 , in the 10-bit information data of d 0  to d 9 . 
   Checksums for d 1   
     d   1   ′=r   0   ×r   30 
 
 d   1   ′=r   1   ×r   2 
 
 d   1   ′=r   3   ×r   4 
 
 d   1   ′=r   5   ×r   6 
 
 d   1   ′=r   7   ×r   8 
 
 d   1   ′=r   9   ×r   10 
 
 d   1   ′=r   11   ×r   12 
 
 d   1   ′=r   13   ×r   14 
 
 d   1   ′=r   15   ×r   31 
 
 d   1   ′=r   16   ×r   17 
 
 d   1   ′=r   18   ×r   19 
 
 d   1   ′=r   20   ×r   21 
 
 d   1   ′=r   22   ×r   23 
 
 d   1   ′=r   24   ×r   25 
 
 d   1   ′=r   26   ×r   27 
 
 d   1   ′=r   28   ×r   29 
 
   Checksums for d 2 
 
 d   2   ′=r   0   ×r   2 
 
 d   2   ′=r   1   ×r   30 
 
 d   2   ′=r   3   ×r   5 
 
 d   2   ′=r   4   ×r   6 
 
 d   2   ′=r   7   ×r   9 
 
 d   2   ′=r   8   ×r   10 
 
 d   2   ′=r   11   ×r   13 
 
 d   2   ′=r   12   ×r   14 
 
 d   2   ′=r   15   ×r   17 
 
 d   2   ′=r   16   ×r   31 
 
  d   2   ′=r   18   ×r   20 
 
 d   2   ′=r   19   ×r   21 
 
 d   2   ′=r   22   ×r   24 
 
 d   2   ′=r   23   ×r   25 
 
 d   2   ′=r   26   ×r   28 
 
 d   2   ′=r   27   ×r   29 
 
   Checksums for d 3 
 
 d   3   ′=r   0   ×r   4 
 
 d   3   ′=r   1   ×r   5 
 
 d   3   ′=r   2   ×r   6 
 
 d   3   ′=r   3   ×r   30 
 
 d   3   ′=r   7   ×r   11 
 
 d   3   ′=r   8   ×r   12 
 
 d   3   ′=r   9   ×r   13 
 
 d   3   ′=r   10   ×r   14 
 
 d   3   ′=r   15   ×r   19 
 
 d   3   ′=r   16   ×r   20 
 
 d   3   ′=r   17   ×r   21 
 
 d   3   ′=r   18   ×r   31 
 
 d   3   ′=r   22   ×r   26 
 
 d   3   ′=r   23   ×r   27 
 
 d   3   ′=r   24   ×r   28 
 
 d   3   ′=r   25   ×r   29 
 
   Checksums for d 4 
 
 d   4   ′=r   0   ×r   8 
 
 d   4   ′=r   1   ×r   9 
 
 d   4   ′=r   2   ×r   10 
 
  d   4   ′=r   3   ×r   11 
 
 d   4   ′=r   4   ×r   12 
 
 d   4   ′=r   5   ×r   13 
 
 d   4   ′=r   6   ×r   14 
 
 d   4   ′=r   7   ×r   30 
 
 d   4   ′=r   15   ×r   23 
 
 d   4   ′=r   16   ×r   24 
 
 d   4   ′=r   17   ×r   25 
 
 d   4   ′=r   18   ×r   26 
 
 d   4   ′=r   19   ×r   27 
 
 d   4   ′=r   20   ×r   28 
 
 d   4   ′=r   21   ×r   29 
 
 d   4   ′=r   22   ×r   31 
 
   Checksums for d 5 
 
 d   5   ′=r   0   ×r   15 
 
 d   5   ′=r   1   ×r   16 
 
 d   5   ′=r   2   ×r   17 
 
 d   5   ′=r   3   ×r   18 
 
 d   5   ′=r   4   ×r   19 
 
 d   5   ′=r   5   ×r   20 
 
 d   5   ′=r   6   ×r   21 
 
 d   5   ′=r   7   ×r   22 
 
 d   5   ′=r   8   ×r   23 
 
 d   5   ′=r   9   ×r   24 
 
 d   5   ′=r   10   ×r   25 
 
 d   5   ′=r   11   ×r   26 
 
 d   5   ′=r   12   ×r   27 
 
  d   5   ′=r   13   ×r   28 
 
 d   5   ′=r   14   ×r   29 
 
 d   5   ′=r   30   ×r   31 
 
   r n  (n=0, 1, . . . 31) represents the 31-level (31-bit in the case of hard decision) signal supplied to the checksum calculator  16  after being multiplied by the mask pattern. 
   In step S 20 , these 80 outputs in total are decided by majority by the majority decision unit  18 , and d 1 ′ to d 5 ′ are decoded. To be more specific, concerning the checksum output, it is decided to be 0 if 0 is majority, and 1 if 1 is majority. 
   In step S 22 , the orthogonal code multiplier  20  multiplies 5-bit information data d 1 ′ to d 5 ′ by the orthogonal codes corresponding to the 5-bit information data d 1 ′ to d 5 ′. The output from the orthogonal code multiplier  20  is as follows.
 
d 1 ′C 1 ^d 2 ′C 2 ^d 3 ′C 3 ^d 4 ′C 4 ^d 5 C 5   (4)
 
   In step S 24 , the exclusive OR circuit  22  calculates the exclusive OR of the output (expression (3)) from the exclusive OR circuit  14  and the output (expression (4)) from the orthogonal code multiplier  20 . The exclusive OR, which is output from the exclusive OR circuit  22  is as follows.
 
d 0 C 0 ^(d 1 ^d 1 ′)C 1 ^(d 2 ^d 2 ′)
 
C 2 ^(d 3 ^d 3 ′)C 3 ^(d 4 ^
 
d 4 ′)C 4 ^(d 5 ^d 5 ′)C 5 ^(d 6 ^d 6 ′)
 
M 1 ^(d 7 ^d 7 ′)M 2 ^(d 8 ^d 8 ′)M 3 
 
^(d 9 ^d 9 ′)M 4 ^e  (5)
 
   Here, if d 1 ′ to d 9 ′ are correctly decoded, the term of (d n ^d n ′)C n  (n=1, 2, . . . 9) becomes a 0 vector. In this case, the output (expression (5)) from the exclusive OR circuit  22  is as follows.
 
d 0 C 0 ^e  (6)
 
   Since C 0  is all 1, d 0 ′ can be obtained by judging the output (expression (6)) from the exclusive OR circuit  22  by the majority decision unit  24  (step S 26 ). To be more specific, each bit of the information data is decided to be 0 if 0 is majority, and 1 if 1 is majority in the output (expression (6)) from the exclusive OR circuit  22 . When bit d 0 ′ of the information data is determined by the majority decision unit  24 , bits d 6 ′ to d 9 ′ of the information data can be determined from the mask pattern used for this determination. The operation mentioned above allows to determine respective bits d 0 ′ to d 9 ′ of the information data. 
   This information data d 0 ′ to d 9 ′ is Reed-Muller encoded by the Reed-Muller encoder  26  as follows, in step S 28 .
 
d 0 ′C 0 ^d 1 ′C 1 ^d 2 ′C 2 ^d 3 ′C 3 ^d 4 ′C 4 ^d 5 ′C 5 ^d 6 ′M 1 ^d 7 ′M 2 ^d 8 ′M 3 ^d 9 ′M 4   (7)
 
   In step S 30 , the Euclidean distance calculator  28  calculates the Euclidean distance between the output (expression (7)) from the Reed-Muller encoder  26  and the received coded signal (expression (2)) output from the hard decision unit  10 . To be more specific, first, the exclusive OR of the output (expression (7)) from the Reed-Muller encoder  26  and the output (expression (2)) from the hard decision unit  10  is obtained as follows:
 
(d 0 ^d 0 ′)C 0 ^(d 1 ^d 1 ′)C 1 ^
 
(d 2 ^d 2 ′)C 2 ^(d 3 ^d 3 ′)C 3 ^
 
(d 4 ^d 4 ′)C 4 ^(d 5 ^d 5 ′)C 5 ^(d 6 
 
^d 6 ′)M 1 ^(d 7 ^d 7 ′)M 2 ^(d 8 ^
 
d 8 ′)M 3 ^(d 9 ^d 9 ′)M 4 ^e  (8)
 
   Expression (8) represents a 32-bit signal, and the sum of these 32 bits represents the Euclidean distance between the output (expression (7)) from the Reed-Muller encoder  26  and the output (expression (2)) from the hard decision unit  10 . 
   In step S 32 , it is determined whether the aforementioned processing is performed for all 16 kinds of mask patterns stored in the memory  12 . If non-processed mask patterns remain, the next mask pattern is designated in step S 34 , and the readout of mask pattern in step S 14  and following processing is repeated. 
   When the aforementioned processing is performed for all 16 kinds of mask patterns stored in the memory  12 , the minimum distance detector  30  detects the minimum Euclidean distance in step S 36 . The information data d 6 ′ to d 9 ′ are decoded based on the mask pattern at the time when the minimum Euclidean distance is detected. The information data d 0 ′ to d 9 ′ are decoded based on the information data d 6 ′ to d 9 ′ together with d 0  to d 5 ′ decoded by the majority decision unit  18  and d 0 ′ decoded by the majority decision unit  24 . 
   As mentioned above, according to the present embodiment, a processing of Reed-Muller decoding by majority decision with the mask symbols removed from a Reed-Muller code using mask symbols, Reed-Muller coding the sum of this decoding result and the mask symbols, and calculating the Euclidean distance between this coded output and the original code is repeated for the number of times as the number of mask patterns, mask symbols corresponding to the minimum distance are determined. The information data are decoded by using these mask symbols. Therefore, the number of checksums to be calculated for the majority decision does not increase compared to the case of Reed-Muller code decoding without using mask symbols. Consequently, a decoding apparatus that can reduce the operation load and the hardware scale can be supplied. 
   This embodiment can also be used as decoding apparatus of (32, 6) Reed-Muller code, without limiting to (32, 10) Reed-Muller code. For this purpose, a changeover switch  32  is connected between the hard decision unit  10  and the exclusive OR circuit  14 , and provides a path for directly supplying the output from the hard decision unit  10  to the checksum calculator  16  bypassing the exclusive OR circuit  14 . A changeover switch  34  is connected also between the majority decision unit  24  and the Reed-Muller encoder  26 , and the output of the majority decision unit  24  may be output as it is as decoding result. 
   In the case of the maximum likelihood decoding, it is necessary to calculate correlations between the coded signal and all the code words. However, the present invention enables to decrease the amount of calculation of the correlations by multiplying the coded signal and the mask symbols beforehand. 
     FIG. 3  is a modification of the first embodiment in which the checksum calculator  16  and the majority decision unit  18  of  FIG. 1  is modified. The modification comprises a memory  40  storing the output from the exclusive OR circuit  14 , exclusive OR circuits  42  reading out bit data from the memory  40  and calculating the exclusive ORs, a checksum selector  44  selecting the outputs from the exclusive OR circuits  42  according to the kind of Reed-Muller code, an accumulator  46  accumulatively adding the outputs from the checksum selector  44 , and a decision device  48  for hard judging the output from the accumulator  46  and decoding the information bit. 
   The Reed-Muller code is stored in the memory  40 . The combinations of checksums are determined according to the kind of the Reed-Muller code, and exclusive ORs of the combinations according to this are obtained by the exclusive OR circuit  42 . For example, 80 checksums are calculated for (32, 6) Reed-Muller code, while only 32 checksums are calculated for (16, 5) Reed-Muller code. The outputs from the exclusive OR circuits  42  are selected by the checksum selector  44  for which bit to be used as code, accumulatively added by the accumulator  46 , and the bit is decided by the decision device  48 . 
   Other embodiments of the decoding apparatus according to the present invention will be described. The same portions as those of the first embodiment will be indicated in the same reference numerals and their detailed description will be omitted. 
   Second Embodiment 
     FIG. 4  shows a second embodiment of the decoding apparatus which is simplifier than the first embodiment. 
   Comparing the output (expression (5)) of the exclusive OR circuit  22  and the Euclidean distance (expression (8)) between the output (expression (7)) of the Reed-Muller encoder  26  and the output (expression (2)) of the hard decision circuit  10 , it is found that the expression (8) includes d 0 ′C 0  which is not included in the expression (5). If d 0 ′=1, the expression (8) is an inversion of the expression (5) since C 0  is a code of all 1. 
   Therefore, it can be determined that one of the output (expression (5)) of the exclusive OR circuit  22  and the inverted signal of the output of the exclusive OR circuit  22  which has the shorter Euclidean distance is a correct code. Thus, it is unnecessary to provide the majority decision unit  24 , the Reed-Muller encoder  26 , and the Euclidean distance calculator  28  of FIG.  1 . 
   A result of accumulation of each bit of the expression (5) represents the Euclidean distance between the output (expression (7)) of the Reed-Muller encoder  26  (where d 0 ′=0) and the received coded data. A result of accumulation of each bit of an inversion of the expression (5) represents the Euclidean distance between the output (expression (7)) of the Reed-Muller encoder  26  (where d 0 ′=1) and the received coded data. The number of “1”s included in the accumulation result equals to the Euclidean distance. 
   Therefore, the output from the exclusive OR circuit  22  is supplied to an inversion detector  54  and the accumulation result of the expression (5) and the accumulation result of an inversion of the expression (5) are compared. Smaller one is supplied to the minimum distance detector  30 . 
   The aforementioned processing is performed for all 16 kinds of mask patterns corresponding to d 6  to d 9 , and the minimum Euclidean distance is detected by the minimum distance detector  30 . Bit data d 0 ′ to d 9 ′ at the time when the minimum distance is detected are considered to be correct, completing the decoding. 
   This embodiment can also be used as decoding apparatus of (32, 6) Reed-Muller code. Thus, the changeover switch  32  is connected between the hard decision unit  10  and the exclusive OR circuit  14 , and the changeover switch  34  is connected between the inversion detector  54  and the minimum distance detector  30 . 
     FIG. 5  is a flow chart of the second embodiment. Step S 10  to step S 24  of  FIG. 5  are the same as those of FIG.  2 . In the second embodiment, after step S 24  in which the exclusive OR circuit  22  calculates the exclusive OR of the output (expression (3)) from the exclusive OR circuit  22  and the output (expression (4)) from the orthogonal code multiplier  20 , the inversion detector  54  calculates in step S 40  the accumulation result of bits of the output from the exclusive OR circuit  22  and the accumulation result of bits of the inverted output from the exclusive OR circuit  22 . In step S 42 , the smaller one of the two accumulation results is selected and is supplied to the minimum distance detector  30 . 
   In step S 32 , it is determined whether the aforementioned processing is performed for all 16 kinds of mask patterns stored in the memory  12 . If non-processed mask patterns remain, the next mask pattern is designated in step S 34 , and the readout of mask pattern in step S 14  and following processing is repeated. 
   When the aforementioned processing is performed for all 16 kinds of mask patterns stored in the memory  12 , the minimum distance detector  30  detects in step S 36  the minimum Euclidean distance. 
   Third Embodiment 
     FIG. 6  shows a decoding apparatus of (32, 10) Reed-Muller code according to the third embodiment. Though the first and second embodiments relate to the hard decision, the third embodiment relates to a soft decision. 
   The following definition will be used for the description below. 
   “^” means an exclusive OR operation. For two vectors, A and B, “A^B” represents the exclusive OR of components of respective vectors A and B. 
   m(A) represents the vector A in which each of components 0 and 1 is changed to +1 and −1. 
   10-bit information data to be encoded are assumed to be d 0 , d 1 , d 2 , d 3 , d 4 , d 5 , d 6 , d 7 , d 8  and d 9 . Each bit data d n  is 0 or 1. 
   Orthogonal codes used for encoding are assumed to be C 0 , C 1 , C 2 , C 3 , C 4  and C 5 . Each code C n  is a 32-bit data, and 32 elements thereof are 0 or 1. Note that C 0  is a series of all 1. 
   Similarly, assuming mask symbols used for encoding be M 1 , M 2 , M 3  and M 4 . Each mask symbol M n  is a 32-bit data. The mask patterns d 6 M 1 ^d 7 M 2 ^d 8 M 3 ^d 9 M 4 , which are exclusive ORs of the mask symbols and the information data, have 2 4 =16 patterns. 
   An encoding apparatus encodes the aforementioned information data “d” based on the orthogonal codes C 0  to C 5  and the mask symbols M 1  to M 4 , and outputs the following 32-bit coded signal m(s). Here, the orthogonal codes and the mask symbols to be multiplied with each bit of the information data are predetermined.
 
M(s)=m(d 0 C 0 ^d 1 C 1 ^d 2 C 2 ^
 
d 3 C 3 ^d 4 C 4 ^d 5 C 5 ^d 6 M 1 ^
 
d 7 M 2 ^d 8 M 3 ^d 9 M 4 )  (21)
 
   In this embodiment, the following signal in which an error “e” due to transfer path or noise is added to the 32-bit coded signal m(s) is input to the decoding apparatus of FIG.  6 .
 
m(d 0 C 0 ^d 1 C 1 ^d 2 C 2 ^d 3 C 3 ^
 
d 4 C 4 ^d 5 C 5 ^d 6 M 1 ^d 7 M 2 ^
 
d 8 M 3 ^d 9 M 4 )+E  (22)
 
   A multiplier  60  multiplies the received coded signal by the mask pattern which is represented by +1 and −1 and read from the memory  12 . 
   The output from the multiplier  60  is supplied to the checksum calculator  16  in the same manner as the first embodiment. The calculator  16  calculates  16  checksums for each of 5 bits of d 1  to d 5  (80 checksums in total), among 10-bit information data d 0  to d 9 . 
   The majority decision unit  18  decides a majority of the 80 checksums output from the checksum calculator  16  to decode bits d 1 ′ to d 5 ′ corresponding to the orthogonal codes C 1  to C 5 . To be more specific, concerning the checksum, it is decided to be 0 if it is positive, and 1 if it is negative. 
   The orthogonal code multiplier  20  multiplies 5-bit data d 1  to d 5 ′ by the orthogonal codes. 
   A multiplier  62  multiplies the output from the multiplier  60  and the output from the orthogonal code multiplier  20  which is represented by +1 and −1. In the same manner as the first embodiment, the majority decision unit  24  decides a majority of the output from the multiplier  62  to decode bit d 0 ′. To be more specific, concerning the output from the multiplier  62 , it is decided to be 0 if it is positive, and 1 if it is negative. When the bit d 0 ′ of the information data is determined by the majority decision unit  24 , bits d 6 ′ to d 9 ′ of the information data can be determined based on the mask pattern used for determining the bit d 0 ′. 
   Thus, the information data d 0 ′ to d 9 ′ are determined. The Reed-Muller encoder  26  encodes the determined information data d 0 ′ to d 9 ′. A correlation calculator  64  calculates a correlation between the received coded signal and the output from the Reed-Muller encoder  26 . 
   The aforementioned processing is performed for all 16 kinds of the mask patterns, and the maximum correlation is detected by a maximum detector  66 . Bit data d 0 ′ to d 9 ′ at the time when the maximum correlation is detected are considered to be correct, completing the decoding. 
   One mask pattern is specified in step S 60 , this specified mask pattern is read out from the memory  12  in step S 62 , and the multiplier  60  multiplies the received coded signal by the mask pattern. 
   The memory  12  stores the orthogonal codes C 0  to C 5 , mask symbols M 1  to M 4 , and 16 mask patterns d 6 M 1 ^d 7 M 2 ^d 8 M 3 ^d 9 M 4  not shown in Table 1. “i” represents a bit position. 
   Supposing the mask pattern read out from the memory  12  be M′=m(d 6 ′M 1 ^d 7 ′M 2 ^d 8 ′M 3 ^d 9 ′M 4 ), the product of the received coded signal and the mask pattern will be as follows.
 
m(d 0 C 0 ^d 1 C 1 ^d 2 C 2 ^d 3 C 3 ^
 
d 4 C 4 ^d 5 C 5 ^(d 6 ^d 6 ′)M 1 ^
 
(d 7 ^d 7 ′)M 2 ^(d 8 ^d 8 ′)M 3 ^(d 9 
 
^d 9 ′)M 4 )+E  (23)
 
   In step S 66 , the checksum calculator  16  calculates the checksum of the expression (23) output from the multiplier  60 . Respectively, 16 checksums are calculated for 5 bits of d 1  to d 5 , in the 10-bit information data of d 0  to d 9 . 
   In step S 68 , these 80 outputs in total are decided by majority by the majority decision unit  18 , and d 1 ′ to d 5 ′ are decoded. To be more specific, concerning the checksum output, it is decided to be 0 if it is positive, and 1 if it is negative. 
   In step S 70 , the orthogonal code multiplier  20  multiplies 5-bit information data d 1 ′ to d 5 ′ by the orthogonal codes corresponding to the 5-bit information data d 1 ′ to d 5 ′. The output from the orthogonal code multiplier  20  is as follows.
 
m(d 1 ′C 1 ^d 2 ′C 2 ^d 3 ′C 3 ^d 4 ′C 4 ^d 5 ′C 5 )  (24)
 
   In step S 72 , the multiplier  62  multiplies the output (expression (23)) from the multiplier  60  and the output (expression (24)) from the orthogonal code multiplier  20 . The output from the multiplier  62  is as follows.
 
m(d 0 C 0 ^(d 1 ^d 1 ′)C 1 ^(d 2 ^
 
d 2 ′)C 2 ^(d 3 ^d 3 ′)C 3 ^(d 4 ^
 
d 4 ′)C 4 ^(d 5 ^d 5 ′)C 5 ^(d 6 ^
 
d 6 ′)M 1 ^(d 7 ^d 7 ′)M 2 ^(d 8 ^
 
d 8 ′)M 3 ^
 
(d 9 ^d 9 ′)M 4 )+E  (25)
 
   Here, if d 1 ′ to d 9 ′ are correctly decoded, the term of (d n ^d n ′)C n  (n=1, 2, . . . 9) becomes a 0 vector. In this case, the output (expression (25)) from the multiplier  62  is as follows.
 
m(d 0 C 0 )+E  (26)
 
   Since C 0  is all 1, d 0 ′ can be obtained by judging the output (expression (26)) from the multiplier  62  by the majority decision unit  24  (step S 74 ). To be more specific, each bit of the information data is decided to be 0 if it is positive, and 1 if it is negative in the output (expression (26)) from the multiplier  62 . When bit d 0 ′ of the information data is determined by the majority decision unit  24 , bits d 6 ′ to d 9 ′ of the information data can be determined from the mask pattern used for this determination. The operation mentioned above allows to determine respective bits d 0 ′ to d 9 ′ of the information data. 
   This information data d 0 ′ to d 9 ′ is Reed-Muller encoded by the Reed-Muller encoder  26  as follows, in step S 76 .
 
m(d 0 ′C 0 ^d 1 ′C 1 ^d 2 ′C 2 ^d 3 ′
 
C 3 ^d 4 ′C 4 ^d 5 ′C 5 ^d 6 ′M 1 ^
 
d 7 ′M 2 ^d 8 ′M 3 ^d 9 ′M 4 )  (27)
 
   In step S 78 , the correlation calculator  64  calculates the correlation between the output (expression (27)) from the Reed-Muller encoder  26  and the received coded signal (expression (22)). To be more specific, first, the product of the output (expression (27)) from the Reed-Muller encoder  26  and the received coded signal (expression (22)) is obtained as follows:
 
m((d 0 ^d 0 ′)C 0 ^(d 1 ^d 1 ′)C 1 ^
 
(d 2 ^d 2 ′)C 2 ^(d 3 ^d 3 ′)C 3 ^
 
(d 4 ^d 4 ′)C 4 ^(d 5 ^d 5 ′)C 5 ^
 
(d 6 ^d 6 ′)M 1 ^(d 7 ^d 7 ′)M 2 ^(d 8 ^
 
d 8 ′)M 3 ^(d 9 ^d 9 ′)M 4 )+E  (28)
 
   Expression (28) represents a 32-bit signal, and the accumulation result of these 32 bits represents the correlation between the output (expression (27)) from the Reed-Muller encoder  26  and the received coded signal (expression (22)). 
   In step S 80 , it is determined whether the aforementioned processing is performed for all 16 kinds of mask patterns stored in the memory  12 . If non-processed mask patterns remain, the next mask pattern is designated in step S 82 , and the readout of mask pattern in step S 62  and following processing is repeated. 
   When the aforementioned processing is performed for all 16 kinds of mask patterns stored in the memory  12 , the maximum detector  66  detects the maximum correlation in step S 84 . The information data d 6 ′ to d 9 ′ are decoded based on the mask pattern at the time when the maximum correlation is detected. The information data d 0 ′ to d 9 ′ are decoded based on the information data d 6 ′ to d 9 ′ together with d 0 ′ to d 5 ′ decoded by the majority decision unit  18  and d 0 ′ decoded by the majority decision unit  24 . 
   As mentioned above, according to the present embodiment, a processing of Reed-Muller decoding by majority decision with the mask symbols removed from a Reed-Muller code using mask symbols, Reed-Muller coding the sum of this decoding result and the mask symbols, and calculating the correlation between this coded output and the original code is repeated for the number of times as the number of mask patterns, mask patterns corresponding to the maximum correlation are determined. The information data are decoded by using these mask symbols. Therefore, the number of checksums to be calculated for the majority decision does not increase compared to the case of Reed-Muller code decoding without using mask symbols. Consequently, a decoding apparatus that can reduce the operation load and the hardware scale can be supplied. Further, this embodiment utilizes the soft decision. The majority decision in the soft decision system is performed at a higher precision than in the hard decision system. 
   This embodiment can also be used as decoding apparatus of (32, 6) Reed-Muller code. Thus, the changeover switch  32  is connected between the coded signal input terminal and the multiplier  60 , and the changeover switch  34  is connected between the majority decision unit  24  and the Reed-Muller encoder  26 . 
     FIG. 8  is a modification of the third embodiment in which the checksum calculator  16  and the majority decision unit  18  of  FIG. 6  is modified. The modification comprises the memory  40  storing the output from the multiplier  60 , multipliers  62  reading out bit data from the memory  40  and calculating products, the checksum selector  44  selecting the outputs from the multipliers  70  according to the kind of Reed-Muller code, the accumulator  46  accumulatively adding the outputs from the checksum selector  44 , and the decision device  48  for hard judging the output from the accumulator  46  and decoding the information bit. 
   Fourth Embodiment 
     FIG. 9  shows the fourth embodiment of the decoding apparatus which is simplifier than the third embodiment. 
   Comparing the output (expression (25)) of the multiplier  62  and the correlation (expression (28)) between the output (expression (27)) of the Reed-Muller encoder  26  and the output (expression (22)) of the received coded signal, it is found that the expression (28) includes d 0 ′C 0  which is not included in the expression (25). If d 0 ′=1, the expression (28)is an inversion of the expression (25) since C 0  is a code of all 1. 
   Therefore, it can be determined that one of the accumulation result of the output (expression (25)) of the multiplier  62  and the accumulation result of the inverted signal of the output of the multiplier  62  which is larger can be used as the correlation. Thus, it is unnecessary to provide the majority decision unit  24 , the Reed-Muller encoder  26 , and the correlation calculator  64  of FIG.  6 . 
   A result of accumulation of each bit of the expression (25) equals to the correlation between the output (expression (27)) of the Reed-Muller encoder  26  (where d 0 ′=0) and the received coded data (expression (22)). A result of accumulation of each bit of an inversion of the expression (25) equals to the correlation between the output (expression (27)) of the Reed-Muller encoder  26  (where d 0 ′=1) and the received coded data. 
   Therefore, the output from the multiplier  62  is supplied to an inversion detector  78  and the accumulation result of the expression (25) and the accumulation result of an inversion of the expression (25) are compared. Larger one is supplied to the maximum distance detector  66 . 
   The aforementioned processing is performed for all 16 kinds of mask patterns corresponding to d 6  to d 9 , and the maximum correlation is detected by the maximum detector  66 . Bit data d 0 ′ to d 9 ′ at the time when the maximum correlation is detected are considered to be correct, completing the decoding. 
   This embodiment can also be used as decoding apparatus of (32, 6) Reed-Muller code. Thus, the changeover switch  32  is connected between the coded signal input terminal and the multiplier  60 , and the changeover switch  34  is connected between the inversion detector  78  and the maximum detector  66 . 
     FIG. 10  is a flow chart of the fourth embodiment. Step S 60  to step S 72  of  FIG. 10  are the same as those of FIG.  7 . In the fourth embodiment, after step S 72  in which the multiplier  62  calculates the product of the output (expression (23)) from the multiplier  60  and the output (expression (24)) from the orthogonal code multiplier  20 , the inversion detector  78  calculates in step S 90  the accumulation result of bits of the output from the multiplier  62  and the accumulation result of bits of the inverted output from the multiplier  62 . In step S 92 , the larger one of the two accumulation results is selected and is supplied to the maximum detector  66 . 
   In step S 80 , it is determined whether the aforementioned processing is performed for all 16 kinds of mask patterns stored in the memory  12 . If non-processed mask patterns remain, the next mask pattern is designated in step S 82 , and the readout of mask pattern in step S 62  and following processing is repeated. 
   When the aforementioned processing is performed for all 16 kinds of mask patterns stored in the memory  12 , the maximum detector  66  detects in step S 84  the maximum correlation. 
   Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.