Abstract:
An output driver circuit for coupling a logic circuit to load includes an input node, an output node for coupling to the load and a pull down switch which discharges the output node in response to a signal received at the input node. A current sink circuit includes a feeder transistor which provides current to the control terminal of the pull down switch to render the pull down switch conductive when the voltage at the output node exceeds a first threshold value between a logic high and a logic low. The feeder transistor is charged by a first charging path having a first impedance by which it takes a first time period to render the pull down switch conductive, the first impedance providing a low standby current when the voltage at the output node is below about the first value. A jump start circuit having a second current path with a lower impedance than the first current path charges the control terminal of the feeder transistor to said threshold faster than said first path and is disabled when the voltage at the output node falls below about the first value, thereby saving power.

Description:
BACKGROUND OF THE INVENTION 
     The invention relates to an output driver circuit connected between a first supply terminal and second, lower supply terminal for driving a load and having 
     an input node for receiving an input signal and an output node for connection to the load; 
     a pull down switch having a control terminal and a current channel coupled between the output node and the second, lower supply terminal, the control terminal being coupled to the input node and rendering the current channel conductive to discharge the output node in response to a selected signal at the input node; and 
     a current sink circuit controlling the pull down switch to discharge the output node in response to a selected voltage at the output node, the current sink circuit including (i) a feeder switch having a control input and a current channel coupling the first supply to the control terminal of the pull down switch, and (ii) a first charging path coupling the first supply to the control terminal of the feeder switch in response to receipt of the selected signal at the input node. 
     Such an output driver circuit is known from U.S. Pat. No. 5,570,044 (Martin et al). One use of the circuit is for interfacing a logic circuit with a load, such as a bus. For example, upon a transition from a logic high to a logic low at the input terminal, the pull down transistor is rendered conductive, rapidly pulling the output terminal from logic high to logic low. The pull down transistor is then turned off, saving power. Under certain load conditions, it is possible for the voltage at the output terminal after having been initially pulled to a logic low to bounce back up to a higher voltage sufficient to be read as a logic high. Thus, an error or glitch is present in that the logic level at the output terminal does not mirror the signal at the input terminal. 
     To overcome this glitch, the current sink circuit further includes a feeder switch that provides current to charge the control terminal of the pull down switch if the voltage at the output node bounces above a first selected value. The feeder switch is charged by a charging path from the first supply terminal to the base of the feeder switch, and is enabled when the input transitions to a logic low. The response of the circuit in turning on the pull down switch to discharge voltage bounces at the output node is a limiting factor in the speed of the circuit. 
     Accordingly, it is the object of the invention to improve the speed of the driver circuit in responding to and discharging voltage bounces. 
     It is another object of the invention to improve the speed without increasing the static power consumption of the circuit. 
     SUMMARY OF THE INVENTION 
     Generally speaking, according to the invention, a driver circuit according to the opening paragraph is characterized in that: 
     the first charging path has a first impedance by which it takes a first time period after receipt of the selected signal at the input node to charge the control terminal of the feeder switch to a threshold which renders the feeder switch conductive, and 
     the driver circuit further includes an auxiliary charging path coupling the first supply to the control terminal of the feeder switch in response to the selected signal at the input node, the second current path having a lower impedance than the first charging path and charging the control terminal of the feeder switch to the threshold in a time period shorter than the first time period. 
     The invention is based on the recognition that the speed of the circuit in reacting to voltage bounces after the initial discharge of the output node was limited by the speed of charging of the feeder switch to its conductive state. The speed of charging was limited in turn by the need to have a low standby current when the output voltage was at logic low, so as to be near the ideal of zero static power. The first charging path then was required to include a fairly high resistance, which together with inherent capacitance in the circuit, resulted in a high impedance (RC time constant) and an undesirably slow initial charging of the feeder switch. By the measure according to the invention, the auxiliary charging path has a much lower impedance than the first charging path of the current sink circuit, and charges the feeder switch to its conducive state more quickly than the first charging path. 
     Favorably, the current sink circuit includes a discharge circuit for discharging the control terminal of the switch whenever the voltage at the output node is pulled below a first value between logic high and logic low. When the output voltage is below the first value, no current is supplied from the first voltage supply to the control terminal of the pull down switch, and only a low standby current flows through the first charging path to the control terminal of the feeder switch and from the base of the feeder switch to the output node via the discharge circuit. The auxiliary path is enabled only when the output voltage is above the first voltage value. In operation, therefore, the auxiliary charging path is enabled for only a relatively short time, beginning when the input signal has transitioned to the selected logic value until the output node has been pulled from the initially high logic level. Once the output node is pulled below the first value, only the low standby of the first charging path flows. Accordingly, low power dissipation is maintained in the static state while the response of the circuit is greatly improved due to the more rapid charging of the feeder switch to its conductive state. 
     These and other object, features and advantages of the invention will become apparent with reference to the following detailed description and the drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic of a preferred embodiment of the output driver circuit according to the invention; and 
     FIG. 2 is a graph comparing the charging time of the base of the feeder switch with and without the improvement according to the invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     With reference to FIG. 1, the output driver circuit according to the invention includes a first circuit portion 10, a second circuit portion 20 which provides a current-sink on demand function, and a third circuit portion 30 which provides a jump start function to the current-sink on demand function. 
     The first circuit portion 10 includes an input node IN and an output node OUT, which output node is normally connected to and drives an external load, such as a bus. A pull down device in the form of a bipolar NPN transistor Q1 has its collector coupled to the output node OUT and its emitter connected to a reference supply terminal, in this case ground. The input node IN is coupled to an input device, an inverter U1, whose output is coupled to the control terminal of the pull down device, i.e. the base of the transistor Q1, by an NMOS switch N1. The control terminal of NMOS device N1 is connected to the output node via series inverters U7 and U8. In the initial condition, both nodes IN and OUT are logic high (the node OUT being pulled high by circuitry not shown), and device N1 is conductive. When the logic signal at the input node IN transitions from a logic high to a logic low, the output of the inverter U1 transitions from low to high. This logic high voltage applied to the base of transistor Q1 renders transistor Q1 conductive, pulling the voltage at the output node OUT from a high logic level to a low logic level, in other words to a voltage of V SAT  above the ground potential. After the output is pulled to logic low, switch N1 opens, depriving Q1 of base drive current. 
     In practice, the voltage at the output node OUT does not always smoothly transition from logic high to logic low and remain at the logic low level. Rather, the voltage at the node OUT is subject to a so-called &#34;bounce effect&#34;. Because a fair amount of charge is discharged from the output node in a rapid fashion, the voltage at the output node does not fall smoothly from logic high (in this case about 3V) to logic low (about V SAT ). Rather the voltage first overshoots logic low in the negative direction, reverses back in the positive direction towards logic high and then reverses again towards logic low. In other words, it takes a finite time for the output voltage to settle to a stable logic low, during which settling time the voltage may bounce back up sufficiently high to be considered a logic high. This settling time reduces the speed of the circuit. Ringing or noise in the external load may also cause the voltage at node OUT to become logic high again, despite the input node IN being logic low. Thus, an error occurs since the output node does not reflect the input condition. While transistor Q1 could be kept conductive to always discharge the output node, this would significantly increase the power demand of the device and is not an acceptable solution for most applications, especially ones powered by battery. 
     The second circuit portion 20 provides a current-sink on on demand function which acts to turn on the transistor Q1 if the voltage at the output bounces above a predetermined level, but which supplies no current to the base of switch Q1 when the output node is at a logic low level. Thus, the extra sink current is suppled only when needed to prevent such glitches. The second circuit portion includes a bipolar feeder transistor Q3, whose collector is connected to supply Vcc and whose emitter is connected to the base of the transistor Q1. The base of the transistor Q3 is connected to the drain of a first P-type MOSFET P2, whose source is connected to the drain of a second P-type MOSFET P1. The source of MOSFET P1 is connected to the supply Vcc via the resistor R2. The control gate of the MOSFET P1 is coupled to an enable input by inverter U3, and the control gate of the MOSFET P2 is coupled to the output of the inverter U1 by a second inverter U2. The base voltage of the transistor Q3 is controlled by the series connection of the resistor R1, the Schottky diode D1 and the transistor Q2. 
     The current-sink on demand circuit 20 functions as follows. When the enable signal is high, the output of inverter U3 is low, which renders the main current path of the switch P1 conductive. In the initial condition, both the input IN and the output OUT are logic high, and both the pull down transistor Q1 and the feeder transistor Q3 are non-conductive. When the logic signal at the input IN transitions from high to low, the output of the inverter U1 switches high and the output of the inverter U2 goes low, also rendering conductive the main current path of the second switch P2. In this instant, a conductive path extends from the supply terminal Vcc to the base of the feeder transistor Q3 via the resistor R2 and the main current paths of MOSFETs P1 and P2. This enables the base of transistor Q3 to be charged sufficiently to render it conductive, depending on the voltage at the node OUT. Typically, pull-down transistor Q1 sinks node OUT and then its base drive is cut off by switch N1 before the base of device Q3 is charged sufficiently to be conductive. When the voltage at node OUT is below a first value of about 200 mV, the diode D1 and transistor Q2 (which functions as a diode) are forward biased and drain current from the base of transistor Q3, so that it is not conductive and does not provide current to the base of the pull down device Q1. Now, if the voltage at node OUT increases above the first value of about 200 mV due to bounce or effects from the bus, the diodes D1 and Q2 are no longer forward biased, so that the base of feeder transistor Q3 is not discharged. This renders transistor Q3 conductive, which supplies base drive to pull down transistor Q1, which then sinks node OUT. When the voltage at node OUT falls again below about 200 mV, transistor Q3 and subsequently transistor Q1 are turned off and will remain off until the voltage at node OUT again rises above about 200 mV. 
     Thus, the circuit portion 10 acts to rapidly pull the node OUT low upon initial transition of the input signal from high to low by sinking large load currents quickly to ground. The circuit 20 is used to suppress glitches at the output node by turning the pull down switch Q1 back on as a result of voltage bounce. However, the response time of circuit 20 in sinking voltage bounces has been found to be a limiting factor in the speed of the circuit. This is due to the amount of time it takes for circuit 20 to charge up sufficiently to turn on pull down device Q1 and is caused by capacitance in the circuit which, in conjunction with the resistance of the resistor R2, imposes an RC time constant which limits the rate of charging of the base of feeder transistor Q3. Lowering the resistance of the resistor R2 would lower the RC time constant and its associated delay. However, this resistance must be kept sufficiently high to limit the standby current which flows through devices R2, P1, P2, Q2, D1 and R1 when the voltage at the output node is low enough for the devices D1 and Q2 to be forward biased. This standby current flows whenever the input signal is at logic low and the voltage at the output node is at logic low (i.e. after node OUT has been pulled low initially and after any bounce has been pulled low). In practice it has been found that the resistance of resistor R2 cannot be lowered sufficiently to decrease this delay to a satisfactory level. 
     In order to overcome this problem, in accordance with the invention, an additional circuit portion 30 is provided which charges the base of feeder transistor Q3 more rapidly than the devices R2, P1, P2. Circuit portion 30 includes three inverters U4, U5, U6 and three additional P-type MOSFETs P3, P4, P5. The base of the transistor Q3 is connected to the drain of MOSFET P5. The source of MOSFET P5 is connected to the drain of MOSFET P4, whose source is in turn connected to the drain of MOSFET P3. The source of MOSFET P3 is coupled to the supply Vcc. The output of inverter U2 is coupled to the control terminal of the MOSFET P5. The control terminal of the MOSFET P4 is coupled to the enable input via the inverter U3. The control terminal of switch P3 is coupled to the output node OUT via the series connection of the inverters U4, U5 and U6. 
     Now, whenever the enable signal is logic high the MOSFET P4 (and also MOSFET P1) are conductive. When the input signal IN is high, the node OUT is pulled high (by circuitry not shown). With node OUT high, the output of inverter U6 is logic low and the MOSFET P3 is conductive. Thus, before the input transitions from a logic high to a logic low, both MOSFETS P3 and P4 are conductive, but MOSFET P5 is non-conductive. Now, when the input signal transitions, the output of inverter U1 becomes high and the output of inverter U2 becomes low. This turns device P5 and P2 conductive at the same time. The series connection of the MOSFETs P3-P5 has a much lower resistance than the series string consisting of devices R2, P1, P2, so the RC time constant of string P3-P5 is also much lower. Consequently, the base of transistor Q3 is charged much more rapidly by circuit portion 30 than by the string containing device R2. Circuit 30 thus effectively jump starts the current-sink on demand circuit 20 by enabling feeder transistor Q3 to be conductive at an earlier time after the high-to-low transition of the input signal. Now, when the voltage at node OUT is pulled low initially by transistor Q1, this signal propagates though the inverter string U4, U5, U6 to turn off (render non-conductive) the MOSFET P3. This stops the charging of the base of transistor Q3. However, this occurs after P5 turns on because the propagation of the signal through inverter U2 (after inverter U1 goes high) is faster than the time it takes for pull down transistor Q1 to initially pull node OUT low and for this signal to propagate through the string U4, U5 and U6 to render MOSFET P3 non-conductive. Thus, upon the high to low transition of the input signal, the jump start circuit rapidly charges the base of feeder transistor Q3 and then turns off when the node OUT is initially pulled low. Since the current-on-demand circuitry suppresses the bouncing at node OUT, node OUT does not get high enough for a time long enough to propagate a signal back through to turn P3 back on, so no further charging from the jump-start path occurs. Consequently, there is no further power drain from the path P3, P4, P5. The combination of the jump start circuit 30 with the current-sink on demand circuit 20 therefore has the advantage of ensuring that the voltage bounce at the output can be handled more quickly while maintaining the advantage of the very low standby current as a result of the resistor R2. 
     FIG. 2 is a graph illustrating the reduced charging time of the base of the feeder switch Q3 by the circuit according to the inventor. The vertical axis is the voltage on the base of Q3 in volts while the horizontal axis is time in nanoseconds, with time 0 representing when the input is still logic high prior to transition to logic low. The dashed line A represents the base voltage of switch Q3 with the jump start circuit according to the invention while the solid line B represents the base voltage of switch Q3 without the jump start circuit 30. As illustrated in FIG. 2, with the circuit according to the invention, the base of switch Q3 is charged to about 1.4V (to render it conductive) in just over 6 nanoseconds. At this same time, the prior art circuit as represented by the solid line B has only charged the base of switch Q3 to about 400 mV. With the prior art circuit the base voltage of switch Q3 would not be charged to 1.4V until about 12 nanoseconds, or twice the charging time of the jump start circuit according to the invention. The slope of line B could be increased to decrease the charging time by decreasing the resistance of resistor R2, but this would undesirably increase the standby current of the current sink circuit 20. 
     The above circuit was implemented in BiCMOS technology due to its favorable characteristics with respect to low power consumption. However, the principles of the invention can be embodied in other processes or technologies, such as any of the standard bipolar, NMOS or CMOS processes. Also, it will be clear from the foregoing that other variations can be made without departing from the principles described herein. For example, the devices P1 and P4 could be eliminated where control by an enable signal is not required. Also, for example, the number and nature of the components may be varied to trigger the disclosed functions at different voltage levels. Accordingly, while the preferred embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the claims. 
     The many features and advantages of the invention are apparent from the detailed specification and it is intended by the appended claims to cover all such features and advantages which fall within the true spirit and scope of the invention. Since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and operation illustrated and described, and accordingly all suitable modifications and equivalents may be resorted to, falling within the scope of the invention.