Abstract:
A circuit for clocking includes an input data path, a receiver, a set of flip-flops, at least one interpolator and a controller. The receiver is coupled to the input data path for receiving input data. The flip-flops, coupled to the receiver, sample the input data. A first interpolator, coupled to one or more of the flip-flops, receives the sampled input data. The controller, coupled to the first interpolator, controls the first interpolator by providing phase information regarding the input data to the first interpolator. The circuit reduces any jitter transferred from the input path to an output path.

Description:
FIELD 
       [0001]    The present invention is related to the field of clocking, and is more specifically directed to a repeater architecture with a single clock multiplier unit. 
       BACKGROUND 
       [0002]    Clock synthesis circuits are used to generate clock signals. Typically, the clock signals provide timing for operation of a circuit. In some applications, multiple timing references or clocks, which operate at different frequencies, are required. For example, some communication standards require operation of transmitter and receiver circuits at pre-determined clock frequencies. If a circuit supports multiple timing references, then multiple clock synthesis circuits are used. Typically, each clock synthesis circuit includes a timing reference, such as a crystal. 
         [0003]    Some circuit applications require a variable frequency clock. In general, a variable frequency clock is a clock that changes frequency over time. One application to vary the clock frequency is spread spectrum clock generation. Some personal computers employ spread spectrum clock generation techniques to vary the clock frequency used for timing in an interface between a disk controller and a hard disk drive. The variable frequency for the timing clock helps reduce electromagnetic interference (EMI) that emanates from the personal computer. 
         [0004]    For the spread spectrum clock application, clock synthesis circuits must generate a variable output frequency. Typically, to achieve this, the clock synthesis circuits use a traditional phase locked loop. The phase locked loop includes a feed-forward divider that divides the reference clock by a variable, M. The output of the divider is then fed into a phase locked loop that multiplies the signal by a variable, N. To obtain greater frequency resolution in such a circuit, the value of the divider and multiplier (e.g., the variables N and M) must be increased. This, in turn, reduces the phase locked loop update rate, and thus limits the phase locked loop bandwidth so as to make the loop more susceptible to power supply, substrate and inherent device noise. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]    The novel features of the invention are set forth in the appended claims. However, for purpose of explanation, several embodiments of the invention are set forth in the following figures. 
           [0006]      FIG. 1  illustrates a single and/or common clock-multiplier-unit architecture in accordance with some embodiments. 
           [0007]      FIG. 2  illustrates a split dual loop control circuit of some embodiments. 
           [0008]      FIG. 3  illustrates tracking for a single/common clock-multiplier-unit architecture of some embodiments. 
           [0009]      FIG. 4  illustrates a jitter transfer for example input jitter. 
           [0010]      FIG. 5  illustrates jitter transfer at 40 kHz, according to some embodiments. 
       
    
    
     DETAILED DESCRIPTION 
       [0011]    In the following description, numerous details are set forth for purpose of explanation. However, one of ordinary skill in the art will realize that the invention may be practiced without the use of these specific details. In other instances, well-known structures and devices are shown in block diagram form in order not to obscure the description of the invention with unnecessary detail. A conventional transceiver architecture has two clock multiplier units (CMU), one for each of a transmitter and a receiver. The receiver clock multiplier unit or receiver phase locked loop tries to lock and/or recover the clock based on the incoming data stream such that the transmitter operates synchronously with the received data stream. The conventional architecture further includes an onboard reference clock. Preferably, the outgoing data stream locks onto the clock of the incoming data stream rather than the reference clock. Accordingly, the incoming data stream and the outgoing data stream preferably have the same frequency. 
       There are shortcomings associated with the conventional two CMU architecture implementation. For instance, the receiver clock multiplier unit uses a clean reference, while the transmitter clock multiplier unit uses a recovered clock as a reference. Hence, the recovered clock can undesirably degrade the transmitter performance. In a particular case, dithering degrades or causes jitter in the recovered clock, which thereby causes transmitter jitter. If there is jitter in the receive path, the jitter is undesirably transferred to the transmit path. There are additional disadvantages of using two clock multiplier units such as, for example, greater cost, greater power consumption, higher overheard, space and/or area requirements. 
       [0012]      FIG. 1  illustrates a single and/or common clock multiplier unit (CMU) system architecture  100  according to some embodiments. As shown in  FIG. 1 , the system  100  includes an input data path  102 , and an output data path  134 . The input data path  102  is coupled to a receiver  104  that is coupled to several data slicers  105 ,  106 ,  107  and  108 . In one embodiment, the data slicers  105 - 108  may be implemented by using D-type flip-flops that are coupled in pairs to phase interpolators  110  and  112 . The phase interpolators  110  and  112  are also coupled to a control module  114  such as, for example, a finite state machine (FSM), and a divider  116 . The control module  114 , in one embodiment, comprises a second order finite state machine, and provides control signals to the phase interpolators  110  and  112 . Such an embodiment is further described below in relation to  FIG. 2 . 
         [0013]    The phase interpolators  110  and  112  are further coupled to a divider  116  that is coupled to a voltage controlled oscillator (VCO)  118  within a phase locked loop (PLL)  103 . In one embodiment, the divider  116  divides by two. However, other division schemes may be implemented without deviating from the spirit or scope of the invention. Within the phase locked loop  103 , the voltage-controlled oscillator  118  is coupled to a charge pump low pass (CP/LP) filter  120 , which is coupled to a phase-and-frequency detector (PFD)  122 . The phase-and-frequency detector  122  receives a reference signal and a feedback signal from a divider  124  in a feedback loop. In one embodiment, the divider  124  divides by 64 to match the implementation of the voltage controlled oscillator  118 . Regardless of the particular implementation, the divider  124  couples the phase-frequency detector  122  to an interpolator  126 . The interpolator  126  preferably receives a frequency control signal from the control module  114 . The interpolator  126  is further coupled to a divider  128 , which is coupled to the voltage controlled oscillator  118 . The divider  128  and the voltage controlled oscillator  118  are both coupled to a first-in-first-out (FIFO) buffer  130 . The FIFO buffer  130  receives input from data slicers  105  and  106 , and outputs to a transmitter  132 , which outputs to the output data path  134 . 
         [0014]    The single/common clock multiplier unit architecture  100  of a particular embodiment advantageously uses a digital control module  114 , such as a digital finite state machine controller, to control the phase of the transmitter  132 . With an interpolator  126  in the feedback loop, the system  100  recovers the timing, and generates the clock necessary for operation of the transmitter  132 . The system  100  advantageously eliminates the need for additional/multiple clock multiplier units, and further reduces the amount of jitter transfer. More specifically, the system  100  embodiment reduces the amount of jitter in the transmitter transmits due to jitter in the receive path. In operation, data enters the input data path  102  and passes through the receiver  104 . The data, generally serial data, is sliced and/or sampled in the sets of data slicers  105 - 106  and  107 - 108  prior to input to the phase interpolators  110  and  112 . The phase interpolators  110  and  112  interpolate and/or generate a clock by using two clock phases having some phase separation. The phase of the generated clock is preferably between the phases of the two received clock phases. The control module  114  controls the resolution of the phase interpolation. The purpose of the control module  114  is to recover the clock and to control the phase of the transmitter  132 . 
         [0015]    As mentioned above, the top portions of  FIG. 1  form a phase locked loop  103 , with an interpolator  126  in the feedback path. The bottom portions of  FIG. 1  form a clock-and-data recover (CDR) circuit  101 . The purpose of the phase locked loop  103  is to generate the multiple clock phases for use by the clock-and-data recovery circuit  101 . The control module  114  controls both the phase interpolator  126 , the phase locked loop  103 , and the interpolators  110  and  112  in the clock-and-data recovery circuit  101 . 
         [0016]    Within the system  100 , the frequency of the incoming data and the frequency of the outgoing data are matched. The frequencies are matched in the nominal sense, but there may be instantaneous jitter in the incoming and outgoing data. The FIFO buffer  130  advantageously reduces instantaneous jitter. In some embodiment, only a shallow FIFO buffer  130  is required to reduce jitter. 
         [0017]    The divider  116  changes the rate of operation of the system  100 . Some embodiments more specifically use a divide-by-two divider  116  in the receiver to implement a half-rate architecture, where half rate operation is advantageous. 
         [0018]    The following text describes the interpolator(s)  110 ,  112 , and  126 , of some embodiments in further detail. More specifically, the interpolator(s)  110 ,  112 , and  126  may comprise an analog circuit capable of generating continuous phase delays. In another embodiment, the interpolator(s) comprise a digital circuit that varies the phase of an output signal or clock in discrete intervals. The disclosure herein sets forth digital circuit embodiments for the interpolator(s); however, the interpolator(s) may be implemented using analog circuits without deviating from the spirit or scope of the invention. 
         [0019]    In one embodiment, the interpolator  126  comprises a phase interpolator that generates a feedback clock from two reference clocks (e.g., a clock with two different phases). The phase of the feedback clock is a weighted sum, based on an interpolator control word, of the phases of the two reference clocks. Implementing a phase interpolator is further described in an article entitled “A Semidigital Dual Delay-Locked Loop”, IEEE Journal of Solid State Circuits, Vol. 32, No. 11, November 1997, authors Stefanos Sidiropoulos and Mark A. Horowitz. Additional information is also found in U.S. Pat. No. 7,432,750, filed Dec. 7, 2005, Ser. No. 11/296,786, entitled “Methods and Apparatus For Frequency Synthesis With Feedback Interpolation,” which is hereby expressly incorporated by reference. 
         [0020]    A time variable delay, introduced in the feedback path of the phase locked loop, generates an output clock with a variable frequency. In general, the phase of the output clock may be varied over time by changing the delay of the interpolator in discrete increments. Furthermore, the size of these increments may be varied over time. For the digital circuit embodiment, the feedback delay, introduced by the interpolator  126 , is controlled by an interpolator control word. In one embodiment, the interpolator control word is a digital word comprising “n” bits. As shown in  FIG. 1  and further described below in relation to  FIG. 2 , an interpolator control module  114  and/or  214  controls the phase delay in the interpolator  126 , by generating the interpolator control word. The interpolator control module  114  and/or  214  modulates the value of the “n” bit interpolator control word. In turn, the “n” bit control word controls the phase delay in the interpolator(s). As a result, a desired frequency is generated at the output of the phase locked loop. Thus, by continuously incrementing or “slewing” the interpolator control word, the phase delay is also slewed over time so as to generate a variable output frequency. 
         [0021]      FIG. 2  illustrates a control module and/or circuit  214  of some embodiments. As shown in  FIG. 2 , the control circuit  214  may be advantageously implemented by using a split dual-loop finite state machine (FSM). In the illustrated implementation  214 , an input signal  236  is input to an adder  238  and a subtracter  240 . As indicated, the input signal  236  is labeled “cdrinc2” and may have a three-bit format [2:0]. Other implementations, however, are also contemplated. 
         [0022]    In this example, the adder  238  receives a fourteen bit accumulated value, labeled freqAcc [13:0], and outputs to subtracter  240  and multiplexer  242 . The subtracter  240  also outputs to the multiplexer  242 . An up/down (“up/dn”) signal is generated based on the data stream using an Alexander algorithm. One implementation for an Alexander algorithm is disclosed in J. D. H. Alexander, “Clock Recovery from Random Binary Signals”, Electron Lett., Vol. 11, No. 22, pp. 541-542, October, 1975. The multiplexer  242  receives select input from the up/down signal  244 , and selects either the output of the adder  238  or the output of the subtracter  240 . The multiplexer  242  outputs to 14 flip-flops (e.g., flip-flops  246 - 247 ) that implement saturating two&#39;s complement. The flip-flops  246 - 247  output signals to an adder  248 , and also provides the accumulated value, freqAcc, that is fed back to the adder  238 . The adder  248  receives an internal control feedback value, interCtlFB, and outputs a 10 bit value to flip-flops  250 . The flip-flops  250  provide the feedback value, interCtlFB, and provide frequency information to the phase interpolator  126  in the feedback of the phase locked loop  103  of  FIG. 1 . Some control circuits  214  provide the information in the form of a control word. 
         [0023]    The control circuit  214  also provides phase control information to the clock-and-data recovery circuit  101  of  FIG. 1 . A separate input signal  254  is input to an adder  256  and a subtracter  258 . In the illustrated implementation, the input signal  254  comprises four bits, and is labeled “cdrinc [3:0].” The adder  256  receives an internal control value, interCtl [10:0], outputs to the subtracter  258 , and outputs to a multiplexer  252 . The subtracter  258  also outputs to the multiplexer  252 , which receives a selection from the up/down signal  244 . Based on the up/down select signal  244 , the multiplexer selects either the output of the adder  256 , or the output of the subtracter  258 . The multiplexer  252  outputs a signal to a flip-flop  260 , and the flip-flop  260  provides an internal control signal, interCtl, to the adder  256 . The flip-flop  260  also provides phase information to the clock-and-data recovery circuit  101  of  FIG. 1 . Some embodiments provide the information in the form of a control word. 
         [0024]    Hence, within circuit  214 , the phase and frequency (control) information is split and/or divided into separate loops, and the controls based on each type of information have two separate outputs. Accordingly, the control circuit  214  has particular advantages for use with the single clock multiplier unit architecture  100  of  FIG. 1 . In the architecture  100 , the interpolator  126  within the phase locked loop  103  of the top portion of  FIG. 1  requires only frequency information, while the interpolators  110  and  112 , within the clock-and-data recovery circuit  101  of the bottom portion of the  FIG. 1 , requires only phase information. 
         [0025]    Accordingly the (second order) loop of the upper portion of  FIG. 2  has an accumulator that accumulates the frequency, and the loop outputs and/or tracks the frequency information. The (first order) loop of the lower portion of  FIG. 2  gives and/or tracks the phase information. Since the frequency used by the interpolator  126  has already been tracked by the (upper) second order loop, a simpler (first order) loop is used to track only the phase information. 
         [0026]    In operation, the interpolator  126  adjusts the phase of the output of the voltage controlled oscillator  118 . The interpolator  126  preferably adjusts the phase at a constant rate, which changes the frequency of the output of the voltage controlled oscillator  118 . When the interpolator  126  advances the phase, it makes the operation of the voltage controlled oscillator  118  seem faster. When the interpolator  126  retards the phase, it makes the operation of the voltage controlled oscillator  118  seem slower. 
         [0027]    As mentioned above, the interpolator  126  changes the phase at a constant rate, which changes the frequency of the output of the voltage controlled oscillator  118 . Stated in relation to a digital implementation, the control code/word from the finite state machine  114  to the interpolator  126  requires constant updating. To change the phase at a constant rate, the control circuit  114  and/or  214  uses two integrators, and/or a cascade of summers, as described above in relation to  FIG. 2 . Advantageously, the loop having the accumulated frequency information, freqAcc, accumulates the error to obtain the frequency information. In these implementations, the error is the up and/or down difference between the clock of the incoming data and the clock of the voltage controlled oscillator  118 . 
         [0028]      FIG. 3  is a plot  300  that illustrates the frequency offset tracking in parts per million (PPM) for a single/common clock multiplier unit architecture of some embodiments. The offset is between the reference clock and the incoming data stream. As shown in  FIG. 3 , the frequency loop accumulator illustrated in  FIG. 2  tracks up to 840 PPM. The plot  300  shows that the system  100  and control module  114  and/or  214  tracks the frequency offset between the reference clock and the incoming data stream at approximately four times the maximum tracking of a conventional architecture that has a maximum tracking of about 200 PPM. 
         [0029]      FIG. 4  is a plot  400  that illustrates an example of input jitter and corresponding output jitter in accordance with the present invention. Specifically, as shown in  FIG. 4 , the curve  410  shows an example of input jitter magnitude across a range of frequencies. The curve  420  illustrates zero jitter across the same frequency range. As such,  FIG. 4  illustrates zero jitter transfer between the example input jitter and the resulting output jitter when using a JTol mask. Accordingly, as shown in  FIG. 4 , zero jitter is transferred when using the JTol mask as a test. 
         [0030]      FIG. 5  is a plot  500  that illustrates jitter transfer for an example embodiment at 40 kHz according to some embodiments. As shown in  FIG. 5 , no jitter is transferred until the jitter amplitude reaches greater than 8.00 UI peak-to-peak. Moreover, the plot  500  shows that there is less than 50% jitter transfer for jitter amplitude between 8.00 and 16.00 UI peak-to-peak, and that there is only about 50% jitter transfer at a jitter amplitude of 18 UI peak-to-peak at 40 kHz. The amount of jitter transfer may be reduced by increasing the size of the accumulator ( FIG. 1 ). 
       Advantages of Single/Common CMU Architecture: 
       [0031]    Sharing a single and/or common clock multiplier unit reduces the power consumption of some embodiments by about ˜40 mA. A further advantage is that there is low and/or reduced jitter transfer from the receive path to the transmit path of a transceiver using the single/common CMU system and appropriate control module such as described above. 
         [0032]    In some implementations, however, a reference spur from the reference clock/signal may undesirably increase. For instance, in some of these implementations, the interpolator in the feedback of the phase locked loop pushes the voltage-controlled oscillator each compare cycle. Accordingly, a reference clock that has high jitter may undesirably transfer the jitter to the transmitter. Advantageously, some embodiments of the invention preferably include a loop filter to reduce the reference spur. 
         [0033]    There are a number of clock-multiplier-unit loop-filter options. (1) One option is to add a third order ripple capacitor. The capacitor of these options is optimally sized to target the narrow frequency range of the reference clock. (2) Another option is to use a switched-capacitor architecture. Using a switched capacitor advantageously results in a significant reduction in the reference spur, but typically requires charge injection from the switches, which may undesirably limit performance. (3) A further option is to use a digital sigma-delta type loop filter. The sigma-delta type filter advantageously has the properties of the switched capacitor option, but without the need for charge injection. Some digital cascaded sigma-delta loop filter implementations also use error cancellation logic. 
         [0034]    While the invention has been described with reference to numerous specific details, one of ordinary skill in the art will recognize that the invention can be embodied in other specific forms without departing from the spirit of the invention. Thus, one of ordinary skill in the art would understand that the invention is not to be limited by the foregoing illustrative details, but rather is to be defined by the appended claims.