Abstract:
A DC converter includes: a transformer (T 1 ) including a primary winding (P 1 ) and a secondary winding (S 1 ); a series resonant circuit in which a current resonant reactor (Lr), the primary winding (P 1 ) of the transformer, and a current resonant capacitor (Cri) are connected in series; conversion circuits (Q 1 , Q 2 ) for converting a DC voltage of a DC power supply (Vin) into a rectangular-wave voltage, so as to output the rectangular-wave voltage to the series resonant circuit; and a rectifier smoothing circuit (D 3 , D 4 , Co) for rectifying and smoothing a voltage generated at the secondary winding (S 1 ) of the transformer, so as to output a DC output voltage to a load, wherein a capacitive element (Cr) including a capacitive component corresponding to a floating capacitance (Cp) equivalently present between the primary winding of the transformer was connected to the current resonant reactor (Lr) in parallel.

Description:
TECHNICAL FIELD 
     The present invention relates to a DC converter that is highly efficient, small in size and inexpensive. 
     BACKGROUND ART 
       FIG. 1  illustrates a circuit configuration diagram of a conventional DC converter (PLT 1). This DC converter is composed of a half-bridge circuit, in which a series circuit including switching elements Q 1  and Q 2  consisting of MOSFETs is connected to both ends of a DC power supply Vin. A drain of the switching element Q 2  is connected to a positive electrode of the DC power supply Vin and a source of the switching element Q 1  is connected to a negative electrode of the DC power supply Vin. 
     Between the drain and source of the switching element Q 1 , a diode D 1  and a voltage resonant capacitor Cry are connected in parallel. In addition, a reactor Lr 1 , a primary winding P 1  of a transformer T 1 , and a current resonant capacitor Cri are connected in series. The reactor Lr 1  is a leakage inductance between the primary and secondary sides of the transformer T 1 . The primary winding P 1  is connected to a magnetizing inductance as an equivalent reactor Lp. Between a drain and a source of the switching element Q 2 , a diode D 2  is connected in parallel. 
     A winding start of each winding of the transformer T 1  is depicted as a dot. One end (dot side) of a secondary winding S 1  of the transformer T 1  is connected to an anode of a diode D 3 . The other end of the secondary winding S 1  of the transformer T 1  and one end (dot side) of a secondary winding S 2  of the transformer T 1  are connected to one end of a smoothing capacitor Co. The other end of the secondary winding S 2  of the transformer T 1  is connected to an anode of a diode D 4 . A cathode of the diode D 3  and a cathode of the diode D 4  are connected to another end of the capacitor Co. The both ends of the capacitor Co are connected to a load Ro. 
     A PFM controller  10  alternately turns on/off the switching elements Q 1  and Q 2  according to an output voltage Vo from the capacitor Co, thereby fixing an on-duty of the switching elements Q 1  and Q 2  so as to vary a frequency of the switching elements Q 1  and Q 2 . Thus, PFM control (frequency control) is carried out so that the output voltage Vo from the capacitor Co is kept constant. 
     Next, operations of the conventional DC converter with the above-mentioned configuration will be explained with reference to a timing chart of signals of each part at rated load illustrated in  FIG. 2 . 
     In  FIG. 2 , VQ 1  is a drain-source voltage of the switching element Q 1 , IQ 1  is a drain current of the switching element Q 1 , VQ 2  is a drain-source voltage of the switching element Q 2 , IQ 2  is a drain current of the switching element Q 2 , VCri is a voltage between both ends of the current resonant capacitor Cri, VD 3  is a voltage between both ends of the diode D 3 , ID 3  is a current of the diode D 3 , VD 4  is a voltage between both ends of the diode D 4 , and ID 4  is a current of the diode D 4 . 
     Note that, there is a dead time during which the switching elements Q 1  and Q 2  are both off, and the switching elements Q 1  and Q 2  are alternately turned on and off. 
     In an interval between time t 0  and time t 1 , the switching element Q 2  is switched from on to off at time t 0 . In a state where the switching element Q 2  is an on state, the primary side of the transformer T 1  passes a current in a route along Vin-&gt;Q 2 -&gt;Lr 1 -&gt;Lp-&gt;Cri-&gt;Vin. Similarly, the secondary side of the transformer T 1  passes a current in a route along Co-&gt;Ro-&gt;Co. 
     When the switching element Q 2  is turned off, the current flowing the primary side of the transformer T 1  is shifted from the switching element Q 2  to the voltage resonant capacitor Crv, and passes in a route along Crv-&gt;Lr 1 -&gt;Lp-&gt;Cri-&gt;Crv. 
     As a result, the voltage resonant capacitor Crv, which substantially has the voltage of the DC power supply Vin in the state where the switching element Q 2  is an on state, discharges to 0 V by turning off the switching element Q 2  (hereinafter, the voltage of the DC power supply Vin is also represented by Vin). 
     Since the voltage of the voltage resonant capacitor Cry is equal to the voltage VQ 1  of the switching element Q 1 , the voltage VQ 1  of the switching element Q 1  decreases from Vin to 0 V. In addition, the voltage VQ 2  of the switching element Q 2  is equal to (Vin−VQ 1 ), and therefore, increases from 0 V to Vin. 
     In an interval from time t 1  to time t 2 , the voltage of the voltage resonant capacitor Cry decreases to 0 V at time t 1 . Then, the diode D 1  becomes conductive to pass a current in a route along D 1 -&gt;Lr 1 -&gt;Lp (P 1 )-&gt;Cri-&gt;D 1 . When the voltage of the secondary winding S 2  of the transformer T 1  reaches the output voltage Vo, the secondary side of the transformer T 1  passes currents in a route along Co-&gt;Ro-&gt;Co and in a route along S 2 -&gt;D 4 -&gt;Co-&gt;S 2 . Also in the interval from time t 1  to time t 2 , a gate signal to the switching element Q 1  turns on, so that the switching element Q 1  conducts a zero-voltage switching (ZVS) operation and a zero-current switching (ZCS) operation. 
     In an interval from time t 2  to time t 3 , the switching element Q 1  is an on state at time t 2 , so as to pass a current in a route along Cri-&gt;Lp (P 1 )-&gt;Lr 1 -&gt;Q 1 -&gt;Cri. Thus, the voltage VCri of the current resonant capacitor Cri decreases. In addition, the secondary side of the transformer T 1  passes currents in a route along S 2 -&gt;D 4 -&gt;Co-&gt;S 2  and in a route along Co-&gt;Ro-&gt;Co. The voltage of the secondary winding S 2  is clamped at the output voltage Vo, and the voltage of the primary winding P 1  is clamped at a voltage that the output voltage Vo is multiplied by a turn ratio of the transformer T 1 . Therefore, the primary side of the transformer T 1  passes a resonant current produced by the reactor Lr 1  and the current resonant capacitor Cri. 
     In an interval from time t 3  to time t 4 , the voltage of the secondary winding S 2  becomes lower than the output voltage Vo at time t 3 , and the current on the secondary side of the transformer T 1  becomes zero. Thus, the secondary side of the transformer T 1  passes a current in a route along Co-&gt;Ro-&gt;Co. Also, the primary side of the transformer T 1  passes a current in a route along Cri-&gt;Lp-&gt;Lr 1 -&gt;Q 1 -&gt;Cri. In other words, the primary side of the transformer T 1  passes a resonant current produced by the sum of the two reactors Lr 1  and Lp (Lr 1 +Lp) and the current resonant capacitor Cri. 
     In an interval from time t 4  to time t 5 , the switching element Q 1  turns off at time t 4 . Then, the current flowing the primary side of the transformer T 1  is shifted from the switching element Q 1  to the voltage resonant capacitor Crv, thereby passing in a route along Lp-&gt;Lr 1 -&gt;Crv-&gt;Cri-&gt;Lp. 
     As a result, the voltage resonant capacitor Crv, which substantially has 0 V in the state where the switching element Q 1  is an on state, is charged to Vin by turning off the switching element Q 1 . Since the voltage of the voltage resonant capacitor Cry is equal to the voltage VQ 1  of the switching element Q 1 , the voltage VQ 1  also increases from 0 V to Vin. In addition, the voltage VQ 2  of the switching element Q 2  is equal to (Vin−VQ 1 ), and therefore, decreases from Vin to 0 V. 
     In an interval from time t 5  to time t 6 , the voltage of the voltage resonant capacitor Cry increases to Vin at time t 5 . Then, the diode D 2  becomes conductive to pass a current in a route along Lp (P 1 )-&gt;Lr 1 -&gt;D 2 -&gt;Vin-&gt;Cri-&gt;Lp (P 1 ). Since the voltage of the secondary winding S 1  of the transformer T 1  reaches the output voltage Vo, the secondary side of the transformer T 1  passes currents in a route along Co-&gt;Ro-&gt;Co and in a route along S 1 -&gt;D 3 -&gt;Co-&gt;S 1 . Also in the interval from time t 5  to time t 6 , a gate signal of the switching element Q 2  is turned on, so that the switching element Q 2  conducts a zero-voltage switching operation and a zero-current switching operation. 
     In an interval from time t 6  to time t 7 , the switching element Q 2  is an on state at time t 6  to pass a current in a route along Vin-&gt;Q 2 -&gt;Lr 1 -&gt;Lp (P 1 )-&gt;Cri-&gt;Vin. Thus, the voltage VCri of the current resonant capacitor Cri increases. In addition, the secondary side of the transformer T 1  passes currents in a route along S 1 -&gt;D 3 -&gt;Co-&gt;S 1  and in a route along Co-&gt;Ro-&gt;Co. The voltage of the secondary winding S 1  is clamped at the output voltage Vo, and the voltage of the primary winding P 1  is clamped at a voltage that the output voltage Vo is multiplied by a turn ratio of the transformer T 1 . Therefore, the primary side of the transformer T 1  passes a resonant current produced by the reactor Lr 1  and current resonant capacitor Cri. 
     In an interval from time t 7  to time t 8 , the voltage of the secondary winding S 1  becomes lower than the output voltage Vo at time t 7 . Thus, the secondary side of the transformer T 1  passes a current in a route along Co-&gt;Ro-&gt;Co. Also, the primary side of the transformer T 1  passes a current in a route along Vin-&gt;Q 2 -&gt;Lr 1 -&gt;Lp-&gt;Cri-&gt;Vin. In other words, the primary side of the transformer T 1  passes a resonant current produced by the sum of the two reactors Lr 1  and Lp (Lr 1 +Lp) and the current resonant capacitor Cri. 
     In this way, the conventional DC converter illustrated in  FIG. 1  employs pulse signals having an on-duty configured to be approximately 50% so as to control the switching frequency of the switching elements Q 1  and Q 2 . Therefore, the resonant current produced by the reactor Lr 1 , the reactor Lp, and the current resonant capacitor Cri is varied, thereby controlling the output voltage Vo. Namely, increasing the switching frequency results in decreasing the output voltage Vo. 
       FIG. 3  is a timing chart of signals of each part at no load. In  FIG. 3 , the load Ro is infinite. Currents ID 3  and ID 4  flowing in diodes D 3  and D 4 , respectively, are the currents only to detect the output voltage Vo. 
     The frequency of the switching element at no load is calculated according to the following formula, 
     
       
         
           
             [ 
             
               Math 
               ⁢ 
               
                   
               
               ⁢ 
               1 
             
             ] 
           
         
       
       
         
           
             
               
                 
                   f 
                   = 
                   
                     
                       1 
                       
                         4 
                         · 
                         
                           
                             { 
                             
                               
                                 ( 
                                 
                                   Lp 
                                   + 
                                   
                                     Lr 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     1 
                                   
                                 
                                 ) 
                               
                               · 
                               Cri 
                             
                             } 
                           
                           
                             1 
                             / 
                             2 
                           
                         
                         · 
                         
                           
                             cos 
                             
                               - 
                               1 
                             
                           
                           ⁡ 
                           
                             [ 
                             
                               
                                 
                                   
                                     
                                       V 
                                       ⁢ 
                                       in 
                                     
                                     · 
                                     Lp 
                                     · 
                                     
                                       Ns 
                                       / 
                                     
                                   
                                 
                               
                               
                                 
                                   
                                     { 
                                     
                                       
                                         
                                           
                                             2 
                                             · 
                                             
                                               ( 
                                               
                                                 
                                                   V 
                                                   ⁢ 
                                                   o 
                                                 
                                                 + 
                                                 
                                                   V 
                                                   ⁢ 
                                                   f 
                                                 
                                               
                                               ) 
                                             
                                             · 
                                           
                                         
                                       
                                       
                                         
                                           
                                             
                                               
                                                 ( 
                                                 
                                                   Lp 
                                                   + 
                                                   
                                                     Lr 
                                                     ⁢ 
                                                     
                                                         
                                                     
                                                     ⁢ 
                                                     1 
                                                   
                                                 
                                                 ) 
                                               
                                               · 
                                               N 
                                             
                                             ⁢ 
                                             
                                                 
                                             
                                             ⁢ 
                                             p 
                                           
                                         
                                       
                                     
                                     } 
                                   
                                 
                               
                             
                             ] 
                           
                         
                       
                     
                     . 
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
     In the formula, Vf is a forward voltage of the diodes D 3  and D 4 , Np is a number of turns of the primary winding P 1  of the transformer T 1 , and Ns is a number of turns of the secondary winding S 1  of the transformer T 1 . 
     However, the actual frequency in the actual circuit becomes higher than a frequency of a theoretical value calculated by the formula (I) due to an influence of parasitic capacitances of the diodes on the secondary winding side of the transformer T 1 , and a parasitic capacitance between the primary winding and parasitic capacitances between the secondary windings of the transformer. 
       FIG. 4  is a circuit configuration diagram of the conventional DC converter in view of the parasitic capacitances. In  FIG. 4 , Cd 1  is a parasitic capacitance of the diode D 3 , Cd 2  is a parasitic capacitance of the diode D 4 , Cp  1  is a parasitic capacitance between the primary winding P 1  of the transformer T 1 , CS 1  is a parasitic capacitance between the secondary winding S 1 , and CS 2  is a parasitic capacitance between the secondary winding S 2 , respectively.  FIG. 5  is a timing chart of signals of each part at no load in the conventional DC converter in view of the parasitic capacitances illustrated in  FIG. 4 .  FIG. 6  is a detail of certain intervals of the timing chart in  FIG. 5 . 
       FIG. 7  is an equivalent circuit diagram, in which the parasitic capacitances Cp 1 , Cd 1 , Cd 2 , CS 1 , and CS 2  are concentrated between the primary winding P 1  of the transformer T 1  and illustrated as one floating capacitance Cp in the conventional DC converter in view of the parasitic capacitances illustrated in  FIG. 4 . 
     In the current resonant circuit illustrated in  FIG. 1  as described above, the frequency at no load or at light load increases over the frequency of the theoretical value. Therefore, there are advantages of preventing the frequency from increasing more than the theoretical value by changing into an intermittent mode at light load, and reducing power consumption due to intermittent oscillation. 
     CITATION LIST 
     Patent Literature 
     
         
         
           
             [PTL 1] Japanese Patent Application Laid-Open Publication No. 2003-319650 
           
         
       
    
     SUMMARY OF INVENTION 
     Meanwhile, when the DC converter is configured to have a multi-output configuration, a cross regulation becomes worse under a combined load condition of no load (light load) in one side and heavy load in the other side. 
     Fundamentally, in the current resonant circuit, the secondary windings of the transformer T 1  are tightly coupled. Therefore, the cross regulation should be in good condition theoretically even under the combined load condition of no load and heavy load. 
     In addition, in order to maintain the cross regulation in good condition, it is necessary to prevent the frequency even at no load from increasing and design the circuit under the resonant condition so as not to cause intermittent oscillation. However, since the frequency increases over the theoretical value, the frequency at rated load cannot be set at such a high level under present circumstances. 
     It is an object of the present invention to provide a small, inexpensive, and high-efficiency DC converter capable of preventing a frequency at no load from increasing. 
     A DC converter according to a first aspect of the present invention includes: a transformer comprising a primary winding and a secondary winding; a series resonant circuit in which a current resonant reactor, the primary winding of the transformer, and a current resonant capacitor are connected in series; a conversion circuit for converting a DC voltage of a DC power supply into a rectangular-wave voltage, so as to output the rectangular-wave voltage to the series resonant circuit; a rectifier smoothing circuit for rectifying and smoothing a voltage generated at the secondary winding of the transformer, so as to output a DC output voltage to a load; and a capacitive element including a capacitive component corresponding to a floating capacitance equivalently present between the primary winding of the transformer and connected to the current resonant reactor in parallel. 
     The conversion circuit can include: a first switching element of which one end is connected to a negative electrode of the DC power supply; and a second switching element of which one end is connected to the other end of the first switching element and of which the other end is connected to a positive electrode of the DC power supply. In this case, the DC voltage of the DC power supply is converted into a rectangular-wave voltage by alternatively turning on/off the first switching element and the second switching element. In addition, the rectangular-wave voltage is outputted to the series resonant circuit connected between both ends of the first switching element or both ends of the second switching element. 
     Alternatively, the conversion circuit can include: a first switching element of which one end is connected to a negative electrode of the DC power supply; a second switching element of which one end is connected to the other end of the first switching element and of which the other end is connected to a positive electrode of the DC power supply, a third switching element of which one end is connected to a negative electrode of the DC power supply; and a fourth switching element of which one end is connected to the other end of the third switching element and of which the other end is connected to a positive electrode of the DC power supply. In this case, the DC voltage of the DC power supply is converted into an AC rectangular-wave voltage by alternatively turning on/off the first switching element and the fourth switching element, and the second switching element and the third switching element. In addition, the AC rectangular-wave voltage is outputted to the series resonant circuit connected between a node of the first switching element and the second switching element and a node of the third switching element and the fourth switching element. 
     The DC converter according to the first aspect of the present invention can include: a controller that controls the DC output voltage by fixing an on-time of one of the switching elements alternatively turned on/off and varying an on-time of the other switching element alternatively turned on/off. 
     Moreover, the DC converter according to the first aspect of the present invention can include: a controller that controls the DC output voltage by fixing an on-time of the first switching element and the fourth switching element and varying an on-time of the second switching element and the third switching element, or by fixing the on-time of the second switching element and the third switching element and varying the on-time of the first switching element and the fourth switching element. 
     The DC converter according to the first aspect of the present invention can include a controller that controls the DC output voltage by fixing an on-duty of each of the switching elements and varying a frequency of each of the switching elements instead of the above-mentioned controller. 
     Alternatively, the DC converter according to the first aspect of the present invention can include a controller that controls the DC output voltage by fixing a frequency of each of the switching elements and varying an on-duty of each of the switching elements. 
     Furthermore, a value of the capacitive element is determined based on a value of a magnetizing inductance of the primary winding of the transformer, a value of the floating capacitance present between the primary winding of the transformer, and a value of the current resonant reactor. 
     According to the first aspect of the present invention, since the capacitive element is connected to the current resonant reactor in parallel, the current passes through the capacitive element, and the floating capacitance equivalently present between the primary winding of the transformer is charged and discharged without passing a current through the current resonant reactor. Thus, it is possible to provide a small, inexpensive, and high-efficiency DC converter capable of preventing a frequency at no load from increasing. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  is a circuit configuration diagram of a conventional DC converter. 
         FIG. 2  is a timing chart of signals of each part at rated load in the conventional DC converter illustrated in  FIG. 1 . 
         FIG. 3  is a timing chart of signals of each part at no load in the conventional DC converter illustrated in  FIG. 1 . 
         FIG. 4  is a circuit configuration diagram of a conventional DC converter in view of parasitic capacitances. 
         FIG. 5  is a timing chart of signals of each part at no load in the conventional DC converter in view of the parasitic capacitances illustrated in  FIG. 4 . 
         FIG. 6  is a detail of certain intervals of the timing chart illustrated in  FIG. 5 . 
         FIG. 7  is an equivalent circuit diagram illustrating each parasitic capacitance to be concentrated between a primary winding of a transformer as one floating capacitance in a conventional DC converter in view of parasitic capacitances. 
         FIG. 8  is a circuit configuration diagram of a DC converter in Example 1 of the present invention. 
         FIG. 9  is a timing chart of signals of each part at no load in the DC converter in Example 1 of the present invention. 
         FIG. 10  is a detail of certain interval of the timing chart illustrated in  FIG. 9 . 
         FIG. 11  is a circuit configuration diagram of a DC converter in Example 2 of the present invention. 
         FIG. 12  is a circuit configuration diagram of a DC converter in Example 3 of the present invention. 
         FIG. 13  is a circuit configuration diagram of a DC converter in Example 4 of the present invention. 
         FIG. 14  is a circuit configuration diagram of a DC converter in Example 5 of the present invention. 
         FIG. 15  is a circuit configuration diagram of a DC converter in Example 6 of the present invention. 
         FIG. 16  is a circuit configuration diagram of a DC converter in Example 7 of the present invention. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     Hereinafter, embodiments of DC converters of the present invention will be described in detail with reference to the drawings. 
     First, in the conventional circuit illustrated in  FIG. 7 , there is a problem of increasing frequency at no load caused by a floating capacitance Cp present between a primary winding P 1  of a transformer T 1 . This floating capacitance is mostly parasitic capacitances of diodes D 3  and D 4  on a secondary side of the transformer T 1 . When dV/dt of switching elements Q 1  and Q 2  composed of a half bridge on a primary side of the transformer T 1  is changed, energy for charging and discharging the parasitic capacitances of the diodes D 3  and D 4  on the secondary side of the transformer T 1  is stored in a current resonant reactor Lr 1 . Then, the above-mentioned problem occurs since this energy is transmitted to the secondary side of the transformer T 1 . 
     Example 1 
     In Example 1 illustrated in  FIG. 8 , in order to bypass a charge amount corresponding to charge and discharge of the floating capacitance Cp equivalently present between the primary winding P 1  of the transformer T 1 , a capacitor Cr (capacitive element) connected to a current resonant reactor Lr in parallel is provided. Thus, charge and discharge energy of the parasitic capacitances of the diodes D 3  and D 4  has been configured not to be stored in the current resonant reactor Lr. That means the capacitor Cr is connected to the current resonant reactor Lr in parallel, whereby a current due to charge and discharge of the floating capacitance Cp between the primary winding P 1  of the transformer T 1  has been configured not to pass through the current resonant reactor Lr. 
     In Example 1 illustrated in  FIG. 8 , a series resonant circuit composed of the current resonant reactor Lr, the primary winding P 1  of the transformer T 1 , and the current resonant capacitor Cri is connected to the switching element Q 1  in parallel. Meanwhile, the series resonant circuit may be connected to the switching element Q 2  in parallel, for example. 
     The current resonant reactor Lr is an external component, and is not a leakage inductance between the primary winding P 1  and the secondary winding S 1  of the transformer T 1 . 
     Another configuration illustrated in  FIG. 8  is the same as the circuit configuration illustrated in  FIG. 1 . Therefore, the same components are indicated by the same reference signs as  FIG. 1 , and explanations thereof are omitted. Note that, the diodes D 1  and D 2  may be parasitic capacitances of the switching elements Q 1  and Q 2 . 
       FIG. 9  is a timing chart of signals of each part at no load in the DC converter in Example 1 of the present invention. Operation waveforms of the signals in Example 1 illustrated in  FIG. 9  are approximately the same as operation waveforms of signals in the conventional circuit illustrated in  FIG. 3 , and those performances are approximately the same as well. Thus, only different performances are described. 
     After the switching element Q 1  or Q 2  is switched from on to off, a voltage between both ends of the switching element Q 1  or Q 2  is shifted from 0 V to a power supply voltage Vin or from the power supply voltage Vin to 0 V by a voltage resonance. In such a case (e.g. interval from time t 0  to t 1 , and interval from time t 4  to t 5 ), the current does not pass through the current resonant reactor Lr, but passes through the capacitor Cr. Thus, the floating capacitance Cp between the primary winding P 1  of the transformer T 1  is charged and discharged. 
     When the floating capacitance Cp is not present, a voltage proportional to an inductance value of the current resonant reactor Lr and a reactor Lp is applied to the primary winding P 1  of the transformer T 1 . Therefore, the same voltage as the case where the floating capacitance Cp is not present may be applied to the primary winding P 1  of the transformer T 1  even when the floating capacitance Cp is present. Thus, a capacitance value of the capacitor Cr can be obtained from an inductance value of the reactor Lp, an inductance value of the current resonant reactor Lr, and a capacitance value of the floating capacitance Cp. 
     Namely, the capacitor Cr may be configured so that a ratio of an impedance between both ends of the current resonant reactor Lr and an impedance between both ends of the reactor Lp is equal to a ratio of the inductances of the current resonant reactor Lr and the reactor Lp. Therefore, the capacitor Cr is configured to have the following condition, 
     
       
         
           
             
               
                 
                   Cr 
                   = 
                   
                     
                       Lp 
                       Lr 
                     
                     · 
                     
                       Cp 
                       . 
                     
                   
                 
               
               
                 
                   [ 
                   
                     Math 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                   
                   ] 
                 
               
             
           
         
       
     
     Accordingly, the capacitor Cr is connected to the current resonant reactor Lr in parallel. Therefore, when dV/dt of the switching elements Q 1  and Q 2  are changed, the current does not pass through the current resonant reactor Lr, but passes through the capacitor Cr. Then, the floating capacitance Cp between the primary winding P 1  of the transformer T 1  is charged and discharged. As a result, energy for charging and discharging the parasitic capacitances of the diodes D 3  and D 4  is not stored in the current resonant reactor Lr, and therefore, the energy is not transmitted to the secondary side of the transformer T 1 . Thus, it is possible to provide the low-noise, small, inexpensive and, high-efficiency DC converter capable of preventing the frequency at no load from increasing, and achieving a downsized transformer. 
     Example 2 
       FIG. 11  is a circuit configuration diagram of a DC converter in Example 2 of the present invention. The floating capacitance Cp between the primary winding P 1  of the transformer T 1  includes a resistance component in series. Therefore, Example 2 can be represented by an equivalent circuit, which is composed of a series circuit of the floating capacitance Cp and a resistance Rp as illustrated in  FIG. 11 . 
     Thus, as illustrated in  FIG. 11 , the circuit configuration, in which a series circuit of the capacitor Cr and a resistor Rr is connected to the current resonant reactor Lr in parallel while corresponding to the series circuit of the floating capacitance Cp and the resistance Rp, is appropriate as the actual circuit configuration. 
     In Example 2 illustrated in  FIG. 11 , similar to Example 1, an influence of the reactor Lp can be cancelled by setting the capacitor Cr and the resistor Rr to meet the following formulae, 
     
       
         
           
             
               
                 
                   
                     Cr 
                     = 
                     
                       
                         Lp 
                         Lr 
                       
                       · 
                       Cp 
                     
                   
                   , 
                   
                     
 
                   
                   ⁢ 
                   
                     Rr 
                     = 
                     
                       
                         Lr 
                         Lp 
                       
                       · 
                       
                         Rp 
                         . 
                       
                     
                   
                 
               
               
                 
                   [ 
                   
                     Math 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     3 
                   
                   ] 
                 
               
             
           
         
       
     
     That means the value of the capacitor Cr and the resistor Rr may be configured so that a ratio of an impedance of the capacitor Cr and the resistor Rr and an impedance of the floating capacitance Cp between the primary winding P 1  of the transformer T 1  and the resistor Rp is equal to a ratio of the reactor Lp and the current resonant reactor Lr. 
     The floating capacitance Cp is mostly the parasitic capacitances of D 3  and D 4 . Magnitude of the parasitic capacitance of the diode varies according to applied voltage. Therefore, a value of the capacitor Cr may be configured to be a capacitance capable of charging and discharging a charge amount of charge and discharge of parasitic capacitances Cd 1  and Cd 2  of the diodes D 3  and D 4 . When the charge amount of charge and discharge of the parasitic capacitances Cd 1  and Cd 2  is to be Q, the capacitor Cr is set based on an averaged capacitance within the applied voltages. 
     Example 3 
       FIG. 12  is a circuit configuration diagram of a DC converter in Example 3 of the present invention. In Example 3 illustrated in  FIG. 12 , compared to Example 2 illustrated in  FIG. 11 , a transformer T 2  including the primary winding P 1  and the secondary winding S 1  is provided while removing the secondary winding S 2  and the diode D 4 , and a PRC controller  11  is employed. 
     The PRC controller  11  fixes an on-time of one switching element Q 1  (or Q 2 ), and varies an ontime of the other switching element Q 2  (or Q 1 ). Thus, a DC output voltage Vo is controlled. Note that, both of the switching elements Q 1  and Q 2  have a dead time that is in an off state of both of the switching elements Q 1  and Q 2  simultaneously. 
     According to such a configuration, when the switching element Q 2  is an on state, a current passes through the capacitor Co via the diode D 3  from the secondary winding S 1  of the transformer T 2 . Accordingly, power is applied to a load Ro. While, when the switching element Q 1  is an on state, the diode D 3  turns off. Thus, a half-wave rectifier output is applied to the load Ro. Other operations are completely the same as that in Example 1, and the same effect as Example 1 can be achieved. 
     Example 4 
       FIG. 13  is a circuit configuration diagram of a DC converter in Example 4 of the present invention. In Example 4 illustrated in  FIG. 13 , compared to Example 3 illustrated in  FIG. 12 , a PWM controller  12  is employed instead of the PRC controller  11 . 
     The PWM controller  12  fixes frequency of the switching elements Q 1  and Q 2 , and varies on-duty of the switching elements Q 1  and Q 2 . Thus, the DC output voltage Vo is controlled. Note that, both of the switching elements Q 1  and Q 2  have a dead time that is in an off state of both of the switching elements Q 1  and Q 2  simultaneously. 
     According to such a configuration in Example 4, operations are also completely the same as that in Example 1, and the same effect as Example 1 can be achieved. 
     Example 5 
       FIG. 14  is a circuit configuration diagram of a DC converter in Example 5 of the present invention. In Example 5 illustrated in  FIG. 14 , compared to Example 1 illustrated in  FIG. 8 , switching elements Q 3  and Q 4  are added, and a PFM controller  10   a  is employed. Note that, diodes D 1  to D 4  may be parasitic capacitances of the switching elements Q 1  to Q 4 . 
     Both terminals of the DC power supply Vin are additionally connected to a series circuit of the switching elements Q 3  and Q 4  composed of a MOSFET, compared to the configuration in Example 1. In this case, a drain of the switching element Q 4  is connected to a positive electrode of the DC power supply Vin. Also, a source of the switching element Q 3  is connected to a negative electrode of the DC power supply Vin. 
     One end of the current resonant capacitor Cri and one end of the voltage resonant capacitor Cry are connected to a node of the switching elements Q 3  and Q 4 . 
     The PFM controller  10   a  alternately turns on/off the switching elements Q 1  and Q 4 , and the switching elements Q 2  and Q 3 , so as to carry out a PFM control. Thus, the DC output voltage Vo is controlled. 
     Note that, each pair of the switching elements Q 1  and Q 4  and the switching elements Q 2  and Q 3  has a dead time that is in an off state of both pair of the switching elements simultaneously. 
     According to such a configuration in Example 5, the operations are also completely the same as that in Example 1, and the same effect as Example 1 can be achieved. 
     Example 6 
       FIG. 15  is a circuit configuration diagram of a DC converter in Example 6 of the present invention. In Example 6 illustrated in  FIG. 15 , compared to Example 3 illustrated in  FIG. 12 , the switching elements Q 3  and Q 4  are added, and a PRC controller  11   a  is employed. 
     Both terminals of the DC power supply Vin are connected to a series circuit of the switching elements Q 3  and Q 4  composed of a MOSFET. A drain of the switching element Q 4  is connected to a positive electrode of the DC power supply Vin. Also, a source of the switching element Q 3  is connected to a negative electrode of the DC power supply Vin. 
     One end of the current resonant capacitor Cri and one end of the voltage resonant capacitor Cry are connected to a node of the switching elements Q 3  and Q 4 . 
     The PRC controller  11   a  alternately turns on/off the switching elements Q 1  and Q 4 , and the switching elements Q 2  and Q 3 . In this case, on-time of one pair of the switching elements Q 1  and Q 4  (or Q 2  and Q 3 ) is fixed, and on-time of the other pair of the switching elements Q 2  and Q 3  (or Q 1  and Q 4 ) is varied. Thus, the DC output voltage Vo is controlled. 
     Note that, each pair of the switching elements Q 1  and Q 4  and the switching elements Q 2  and Q 3  has a dead time that is in an off state of both pair of the switching elements simultaneously. 
     According to such a configuration in Example 6, the operations are also completely the same as that in Example 1, and the same effect as Example 1 can be achieved. 
     Example 7 
       FIG. 16  is a circuit configuration diagram of a DC converter in Example 7 of the present invention. In Example 7 illustrated in  FIG. 16 , compared to Example 4 illustrated in  FIG. 13 , the switching elements Q 3  and Q 4  are added, and a PWM controller  12   a  is employed. 
     Both terminals of the DC power supply Vin are connected to a series circuit of the switching elements Q 3  and Q 4  composed of a MOSFET. A drain of the switching element Q 4  is connected to a positive electrode of the DC power supply Vin. Also, a source of the switching element Q 3  is connected to a negative electrode of the DC power supply Vin. 
     One end of the current resonant capacitor Cri and one end of the voltage resonant capacitor Cry are connected to a node of the switching elements Q 3  and Q 4 . 
     The PWM controller  12   a  alternately turns on/off the switching elements Q 1  and Q 4 , and the switching elements Q 2  and Q 3 . In this case, frequencies of the switching elements Q 1  to Q 4  are fixed, and on-duties of the switching elements Q 1  to Q 4  are varied. Thus, the DC output voltage Vo is controlled. 
     Note that, each pair of the switching elements Q 1  and Q 4  and the switching elements Q 2  and Q 3  has a dead time that is in an off state of both pair of the switching elements simultaneously. 
     According to such a configuration in Example 7, the operations are also completely the same as that in Example 1, and the same effect as Example 1 can be achieved.