Abstract:
The invention relates to a circuit for highly efficient driving of piezoelectric loads, comprising a linear driving circuit portion connected to the load through an inductive-resistive connection whereto a voltage waveform is applied. Advantageously, the circuit comprises further respective circuit portions, structurally independent, connected in turn to the inductive-resistive connection through respective inductors to supply a considerable fraction of the overall current required by the load in the transient and steady state respectively.

Description:
TECHNICAL FIELD  
         [0001]    The present invention relates to an electronic circuit for highly efficient driving of piezoelectric loads, comprising a driver circuit portion connected to at least one load terminal by means of an inductive-resistive connection whereon a voltage waveform is applied. The invention relates also to a method for driving a piezoelectric load with inductive-resistive connection. The invention relates particularly, but not exclusively, to a driver circuit adapted to follow the current profile required by a piezoelectric printer head connected to the driver circuit by means of an inductive and resistive cable referred to as flat cable and similar to a resistance and to a series inductor.  
         BACKGROUND OF THE INVENTION  
         [0002]    As is well known in this specific technical field, a wide range of transducers are available such as, for example, those described in the U.S. Pat. No. 5,895,998. Various types of printer heads are among the wide variety of disclosed transducers. In a piezoelectric load such as a printer head, the electronic circuit is driven by applying voltage waveforms generally formed by a series of ramps having a predetermined slew-rate. An example of such an application is disclosed in the U.S. Pat. No. 4,767,959 in the name of Nippondenso Co.  
           [0003]    The special accuracy required for applying said voltage waveform to the load terminals, along with the high frequency of the driver signal, leads to the use of linear-mode driver circuits involving high power dissipation. Moreover, the presence of a parasitic inductance in the flat connection cable to the load, which is connected in series to the real capacitive load, requires the current demanded by the load to be filtered. The profile of this current is not rectangular and has a beveled pattern with over- and under-elongations, as shown in the attached FIG. 1. Therefore, with respect to an ideal case of a merely capacitive load, it is necessary to manage adequately a current slew-rate at the ramp base and a current queue at the ramp end of the capacitive load.  
           [0004]    The features of these front end electronic circuits depend on the parasite parameters inserted by the flat cable. The structure conventionally used to apply a voltage waveform to a piezoelectric load with an inductive-resistive connection is also shown in FIG. 1 which illustrates a linear driving example. In practice, the driver circuit of FIG. 1 comprises an operational amplifier having a power output stage sufficient for load driving. The piezoelectric load is typically a non-dissipating capacitive load wherein all electric power is dissipated at the transistors incorporated in the linear driving stage. The linear driving solution is not particularly effective because of the considerable electric power dissipation.  
           [0005]    The technical problem underlying the present invention is to provide a driver circuit, particularly for piezoelectric loads, with such functional and structural features to allow a highly efficient load driving without reducing the quality of the waveform generated at the load terminals.  
         BRIEF SUMMARY OF THE INVENTION  
         [0006]    An embodiment of the present invention is directed to a system and method for providing a driver circuit coupled with further driver portions if compared to the linear portions of the prior art, each further portion having to supply as much current as possible during both the transient and the steady condition. The linear driving stage is charged to supply a residual current portion required for following precisely the reference signal. In this manner it is possible to supply the highest amount of current required by the load avoiding in the meantime too frequent switching, which would be required in case of switching-mode driving.  
           [0007]    The disclosed embodiments of the invention relate also to a method for driving a piezoelectric load with inductive-resistive connection and wherein at least a linear driving of said load is provided by means of a driver circuit equipped with a linear circuit portion connected to the load by means of said connection. The method is characterized in that it provides two different driving modes, in the transient and in the steady state, wherein the respective circuit portions supply a considerable portion of the overall current required by the load.  
           [0008]    The characteristics and advantages of the circuit and method according to the invention will be apparent from the following description of an embodiment thereof given by way of non-limiting example with reference to the attached drawings. 
       
    
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0009]    [0009]FIG. 1 is a schematic view of a piezoelectric load driver circuit according to the prior art;  
         [0010]    [0010]FIG. 2 is a schematic view of a piezoelectric load driver circuit according to an embodiment of the invention;  
         [0011]    [0011]FIGS. 3, 4 and  5  are respective schematic views of the circuit of FIG. 2 in three different operating phases;  
         [0012]    [0012]FIG. 6 is a diagram comparing the waveform of the current absorbed by the load with the voltage applied at the load terminals;  
         [0013]    [0013]FIG. 7 is a current vs. time diagram for current signals present in the circuit of FIG. 2;  
         [0014]    [0014]FIG. 8 is a schematic view of a different embodiment of the circuit of FIG. 2;  
         [0015]    [0015]FIGS. 9, 10,  11  and  12  are respective current vs. time diagrams indicating some time periods of activation of the circuit of the invention according to an embodiment of the driving method of the invention;  
         [0016]    [0016]FIGS. 13 and 14 are respective schematic views of circuit portions accompanying the circuit according to an embodiment of the invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0017]    With reference to the drawings, and particularly to the example of FIG. 2, a driver circuit according to an embodiment of the present invention for driving a piezoelectric load  2  is generally and schematically indicated with circuit  1 .  
         [0018]    The circuit  1 , comprises an operational amplifier  3  having the output in feedback to its inverting input (−) and further connected to one terminal of the load  2 , in a node X, to supply a current IAMP. The other non-inverting (+) input of the amplifier  3  receives a reference signal from an input terminal IN of the circuit  1 . This amplifier  3  can be considered as the core of the linear portion of the circuit  1 . The circuit  1  comprises at least a half-bridge circuit portion, including at least a switching device, connected to the node X through an inductance. More particularly, the circuit  1  further comprises respective half-bridge circuit portions  4 ,  5 , each portion being connected to the node X through a corresponding inductor L 1 , L 2 . The portions  4 ,  5  are structurally independent one from the other. The inductors L 1  and L 2  have preferably different value, although it is possible to use inductors having the same value. The half-bridge circuit portion  4 , indicated with LF, is associated to the inductor L 1  with higher value. Likewise, the half-bridge circuit portion  5 , indicated with HF, is associated to the inductor L 2  with lower value. A control block  7  is provided to drive the half-bridge circuit portions  4  and  5 .  
         [0019]    The embodiment of FIG. 2 is aimed at supplying the highest amount of current required by the load  2  by means of the two half-bridges  4  and  5 , while also avoiding frequent switching. The linear portion  3  therefore supplies the current difference I AMP  that is required to follow precisely the voltage reference signal, formed, for instance, by a series of predetermined slew-rate ramps. Thus, the half-bridge circuit portions  4  and  5  supply with high efficiency, in the transient and in the steady state respectively, a considerable portion of the overall current required by the load  2 , during which the linear circuit portion  3  ensures the accuracy of the voltage waveform by supplying only the current difference I AMP , with considerable power saving.  
         [0020]    As just mentioned, in order to meet the load  2  current demands, the half-bridge portion LF utilizes a switching device. More particularly, the switching device comprises a pair of transistors M 1 , M 2  are interconnected together in a node XI. The half-bridge LF is powered between a first supply voltage reference V ALIM  and a second ground reference GND. The inductor L 1  is inserted between the nodes XI and X. In one embodiment, the half-bridge LF comprises MOS power transistors; however, it is also possible to use a bipolar transistor bridge or half-bridge.  
         [0021]    The control terminals of the half-bridge LF transistors M 1  and M 2  are connected to the control block  7 . The control block  7  acts on the transistors M 1  and M 2  to obtain a current profile as close as possible to the required profile. For this reason, the control block  7  requires information about the duration, the ramp slew-rate and the load C LOAD  value.  
         [0022]    In a similar and symmetrical manner, the half-bridge HF comprises a pair of transistors M 3 , M 4  interconnected together at a node X 2 . The half-bridge HF is powered, in turn, between the first supply voltage reference V ALIM  and the second ground reference GND. The inductor L 2  is inserted between the nodes X 2  and X. The control terminals of the half-bridge HF transistors M 3  and M 4  are all connected to a respective output of the control block  7 .  
         [0023]    The use of two half-bridges  4  and  5  allows, by an appropriate strategy for closing the transistor switches incorporated therein, an approximation of the profile of the signal in voltage applied to the load. The lower value inductor L 2  is suitably sized as to be able to follow the initial transient and the current final queue. The half-bridge  4  with higher value inductor L 1  follows the waveform supplying the steady state current value without the need for too frequent switching, which might be required if the half-bridge  5  were used during this phase.  
         [0024]    The control strategy is important since it determines the efficiency which can be obtained in terms of power dissipation, as well as the switching frequency of half-bridge switches. The control method for the circuit  1  is based on the measurement of the current I AMP  outputted by the operational amplifier  3  and is implemented by dividing the piezoelectric load charge period into three phases. These three method phases are described with reference to the schematic FIGS. 3, 4 and  5 .  
         [0025]    The diagram of the circuit  1  shown in FIGS. 3, 4 and  5  has been modified to show the current I AMP  outputted by the linear portion  3  as variable. A sensor  8  is located downstream of the portion  3 , upstream of the node X and connected to the control block  7  to detect the current I AMP  value. The control block  7  comprises a logic interface coupled with the current sensor  8  and a digital-technology logic network having analog output stages connected to the control terminals of the half-bridge  4  and  5  transistors. Depending on the value of the current I AMP , the half-bridge devices are switched according to appropriate control strategies described hereinafter. Steady state transient, T1: During this phase, the switch M 1  of the half-bridge LF is closed for the time needed by the current on the inductor L 1  to reach the value Io required in the steady condition by the load  2 . In this phase, the switch M 3  of the half-bridge HF is conveniently switched so that the current injected by the system on the load approximates at best that demand, with the aim, once again, of minimizing the amount of current supplied by the linear portion  3 . The control flow is represented by the dot-line  9 .  
         [0026]    Steady state, T2: Once the current value on the inductor L 1  has reached the steady state value Io, the half-bridge HF is deactivated, i.e. the switch M 3  is open. At the same time, the half-bridge LF, through the switch M 1  control, keeps the output current close to the current required. The control flow is represented by the dot-line  11 .  
         [0027]    Fall phase, T3: during this phase, it is necessary to shut the half-bridge LF off so that the inductor LI is not charged at a current value other than zero when the current is no longer required by the load  2 . This current would otherwise be absorbed by the linear stage in a dissipating manner. During this phase, the half-bridge HF is activated and follows the fast-changing signals having faster charge and discharge transistors. The control flow is represented by the dot-line  12 .  
         [0028]    The circuit substantially splits the current necessary to be generated for the load  2  into three distinct parts:  
         [0029]    (1) two current peaks supplied by the half-bridge HF in correspondence with the fronts I LOAD ; (2) most of the current in the central portion, in the steady state, supplied by the half-bridge LF; and (3) a corrective current supplied by the linear portion  3 .  
         [0030]    [0030]FIG. 6 shows graphical plots of the currents injected by the two half-bridges, I LF  for the bridge LF and I HF  for the bridge HF, of the current I AMP  supplied by the operational and of I LOAD  required by the load  2 . For implementing the control method according to an embodiment of the invention, two procedures are used: a feedback and a feed-forward procedure.  
         [0031]    The times T1 and T3 are derived analytically. In feed-forward mode, once the inductor LI value, the voltage supply V ALIM , the load value C LOAD , the slew-rate and the initial and final ramp voltages are known, the times T1 and T3 can be ascertained The feedback variable used in the diagram is represented, on the contrary, by the current I AMP  outputted by the linear stage. Depending on this current I AMP  value, the stage LF is switched during the phase T2 and the stage HF during the phases T1 and T3, according to the criteria described hereinafter.  
         [0032]    The feedback variable I AMP  may be controlled in several ways. For example, the transistor M 1  can be opened at predetermined times and closed again when the current I AMP  exceeds a predetermined threshold. A different control scheme provides the use of a hysteresis loop. In this control scheme for example, when the current outputted by the linear portion  3  exceeds an appropriate threshold I HIGH , the switch M 1  or M 3  of the half-bridge LF or HF connected to the supply is closed and, consequently, the current outputted by the non-linear portion increases, whereas the current I AMP  of the linear portion decreases until the latter reaches a lower threshold I LOW  at which the switch M 1  or M 3  is opened, thus repeating the cycle. In this way the hysteresis type of control is:  
         
       I 
       HYST 
       =I 
       HIGH 
       −I 
       LOW  
     
         [0033]    The outcome of this control and the corresponding waveforms are shown in FIG. 7 for a time period indicated with T2 at which the feedback variable acts on the half-bridge LF. During the times indicated with T* the switch M 1  is closed since the operational  3  current is higher than the value I LOW . The switch M 1  is closed until the threshold I LOW  is reached. The I HYST  value choice is a compromise-choice. A small value results in a high half-bridge switching speed whereas a high value results in a higher dissipation by the linear portion.  
         [0034]    The previous comments are based on the use of a single feedback variable acting on the two half-bridges LF and HF in time-distinct phases. FIG. 8 shows schematically a different embodiment illustrating the possibility of measuring a second quantity in addition to the linear portion current I AMP . In this embodiment, a second current sensor  9  inserted between the inductor L 2  and the node X is provided. Therefore, if another quantity is measurable through the second sensor  9 , this quantity can be so used as to control both half-bridges. Knowing, for example, the current outputted by the half-bridge HF, I AMP  could be used as variable for controlling both the switching of the half-bridge HF during the whole period and the sum I AMP +I HF  (equal to I LOAD −I LF ) to drive the LF stage.  
         [0035]    The manner for determining the three times T1, T2, and T3 in an analytical manner will now be described. The following formulas, obtained analytically, allow a real time calculation of said times during the load  2  control phase to be achieved.  
         [0036]    Another method for formulating the differential equation which determines the time pattern of the inductor current can be used in other embodiments of the invention A finite difference equation is determined in which the current value, in a precise instant, is given by the sum of the value in the previous instant plus an increase depending on the voltage present at the inductor terminals. Through simple addition using accumulating circuit blocks, it is possible to calculate the inductor current and assess (as clock stroke number) the time required by the current to reach the steady state value Io, thus obtaining T1. Likewise, it is possible to calculate T3 by inverting the time scale. If the inductor starts from a current value equal to zero and reaches the steady state value Io, it is possible to obtain a transient having the same duration as the discharge transient T3 by using a voltage signal which is time-inverted with respect to the signal required. In this case too, simple addition using accumulating circuit blocks are sufficient for the assessment.  
         [0037]    [0037]FIGS. 13 and 14 show respective embodiments of circuit networks comprising adding and accumulating blocks which can be used for the above purposes. FIG. 13 shows a circuit for calculating the time T1. The current In value is compared with the current Io value, T1 being reached when these values coincide. FIG. 14 shows a circuit for calculating the time T3. The current In value is compared with the current Io value, T3 being reached when these values coincide.  
         [0038]    From the control point of view, four different situations shown in FIGS. 9, 10,  11  and  12  can occur. The cases shown in FIGS. 10 and 11 require a special control. In the case of FIG. 10, the time T3 is known later than the moment of its use for shutting the half-bridge LF off. This occurs because the algorithm does not produce the desired results in the instant of their application. In the case of FIG. 11, the current is so high that the sum of times T1 and T3 is higher than the ramp duration, the assessment being, therefore, useless for control purposes.  
         [0039]    In both cases, it is useful to know a time Tx defined as the instant of intersection between the charge and discharge currents of the inductor L 1 . The time Tx allows the inductor L 1  charge to be interrupted so that no residual current is present at the ramp end, the current being otherwise recovered by the linear stage, with subsequent detrimental power dissipation.  
         [0040]    Steady state rise time for the inductor L 1 , i.e. the time required by L 1  to reach the current theoretic value (SRC):  
         rise                   ramp   :     
          t   1         =             V   ALIM     -     V   O         S                 R                (         V   ALIM     -     V   O         S                 R       )     2         -     2      L                 C                 fall                   ramp   :     
          t   1         =           V   O       S                 R                (       V   O       S                 R       )     2         -     2      L                 C                             
 
         [0041]    Discharge time required to let the inductor L 1  have no residual current at the ramp end:  
         rise                   ramp   :     
          t   3         =           V   D     +     V   F         S                 R                  (         V   D     +     V   F         S                 R       )     2     -     2      L                 C                     fall                   ramp   :     
          t   3         =             V   D     +     V   ALIM     -     V   F         S                 R                (         V   D     +     V   ALIM     -     V   F         S                 R       )     2         -     2      L                 C                             
 
         [0042]    where  
         [0043]    V D =direct voltage on the feedback diode;  
         [0044]    V F =final voltage;  
         [0045]    V O =initial voltage;  
         [0046]    L=inductor L 1 ;  
         [0047]    C=overall load capacity;  
         [0048]    S R =voltage ramp slew rate;  
         [0049]    V ALIM =supply voltage  
         [0050]    TIME T1 CALCULATION: At the inductor L 1  terminals (L indicating the inductor L 1  value) the following differential equation applies:  
         V   L     =         V     A                 L                 I                 M       -     V   C       =     L   ·          i          t                                 
 
         [0051]    by solving it in a discrete form, it becomes  
           Δ                 i       T   CL       =         V   ALIM     -     V   C       L                           
 
         [0052]    by solving it in a discrete form also the voltage at the capacitive load terminals:  
         
       V 
       C 
       =SR·t+V 
       O  
     
         
       V 
       C 
       =SR·n·T 
       CL 
       +V 
       O  
     
         [0053]    where  
         S                 R     =         V   F     -     V   O         T     O                 N                   S                 R     =         V   F     -     V   O           n     O                 N       ·     T     C                 L                   w                 i                 t                 h               S                 R     _     =         V   F     -     V   O         N     O                 N                 a                 n                 d             S                 R     =         S                 R     _       T     C                 L                               
 
         [0054]    it becomes  
         
       V 
       Cn 
       ={overscore (SR)}·n+V 
       O  
     
         [0055]    and then:  
         
       V 
       Cn+1 
       =V 
       Cn 
       +{overscore (SR)} 
     
         [0056]    with  
         V CO   =V   O            i     n   +   1       =       I   n     +           V     A                 L                 I                 M       -     V   O     -         S                 R     _     ·   n       L          T     C                 L                                   
         [0057]    through the temporary variable  
           i   n     _     =       i   n     ·     L     T     C                 L                                 
 {overscore ( i   n+1 )}={overscore ( i   n )}+ V   ALIM   −V   O   −{overscore (SR)}·n    
         [0058]    TIME T3 CALCULATION: to calculate the discharge time, when the inductor passes from a current Io to a current equal to zero at the real end of the voltage ramp, assuming to be in said last instant and to go back in time till the instant T3 when the current Io flows through the inductor, it is evident that (by applying the variable replacement t=−τ) that the system is analogue to another one being advanced in time, but with negative voltage ramp, in formulas:  
         L   ·          i          i         =       -     V   D       -       V   C          (   t   )                               
 
         [0059]    With  
           V   C ( t )= V   F   +SR·t    
         [0060]    The previous equation with negative t is equivalent to the following one with positive t:  
         L   ·          i          i         =       V   D     +       V   C          (   t   )                               
 
         [0061]    With  
           V   C ( t )= V   F   −SR·t    
         [0062]    By solving the latter in a discrete form, it becomes:  
           Δ                 i       T     C                 L         =         V   D     -     V   C       L                           
 
         [0063]    by solving the voltage value in a discrete form at the capacitive load terminals:  
         
       V 
       C 
       =SR·t+V 
       O  
     
         
       V 
       C 
       =V 
       F 
       −SR·n·T 
       CL  
     
         [0064]    where  
         S                 R     =         V   F     -     V   O         T     O                 N                   S                 R     =         V   F     -     V   O           n     O                 N       ·     T     C                 L                   w                 i                 t                 h               S                 R     _     =         V   F     -     V   O         N     O                 N                 a                 n                 d             S                 R     =         S                 R     _       T     C                 L                               
 
         [0065]    it becomes  
         
       V 
       Cn 
       =V 
       F 
       −{overscore (SR)}·n  
     
         [0066]    and then:  
         
       V 
       Cn+1 
       =V 
       Cn 
       −{overscore (SR)} 
     
         [0067]    with  
         V CO =V F    
         [0068]    through the temporary variable  
           i   n     _     =       i   n     ·     L     T     C                 L                                 
 {overscore ( I   n+1 )}={overscore ( i   n )}+ V   D   +V   F   −{overscore (SR)}·n    
         [0069]    Tx TIME CALCULATION: simple calculations generate the following formula:  
         T   X     =       T     O                 N       ·         V   D     +         V   F     +     V   O       2           V   D     +     V     D                 D                                   
 
         [0070]    From the foregoing description, it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.