Abstract:
In a conventional gated clock generating circuit, different signal delay times are produced depending on the arrangement of interconnection of circuit elements, often causing glitches. To avoid this, a gated clock generating circuit of the invention has a circuit that generates a first gate signal having inversion points synchronous with edges of a continuously pulsating clock signal, a circuit that generates a second gate signal deviated by half the period of the clock signal relative to the first gate signal, and a circuit that turns on and off the output of the clock signal in accordance with the first and second gate signals. Even when inversion points of the first or second gate signal deviate from edges of the clock signal, no glitches result.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a gated clock generating circuit that outputs a clock signal while turning it on and off. 
     2. Description of the Prior Art 
     In a semiconductor integrated circuit that operates in synchronism with a clock signal (hereinafter such a circuit will be referred to as a “clock-synchronous circuit”), too large a difference between the delay times with which the clock signal is fed to different flip-flops (hereinafter such a difference will be referred to as a “skew”) causes a fault such as nonfunctioning or malfunctioning of the circuit. To avoid this, clock-synchronous circuits are generally given a synchronized design. 
     A synchronized design consists in feeding an external clock signal directly to the clock input terminals of flip-flops within a circuit without dividing, turning on or off, or inverting the clock signal inside the circuit, and in addition arranging circuit elements and interconnecting them (hereinafter referred to as “arrangement and interconnection”) so as to minimize skews in the clock signal. 
     However, in a clock-synchronous circuit so designed, the clock signal is fed to all the flip-flops simultaneously all the time. This increases the electric power consumption of the flip-flops, and thus increases the electric power consumption of the clock-synchronous circuit as a whole. 
     One effective way proposed to reduce the electric power consumption of a clock-synchronous circuit is to provide it with a gated clock generating circuit so that a gated clock signal generated by the gated clock generating circuit is fed to the clock input terminals of flip-flops that need not operate under certain conditions. 
       FIGS. 14 and 16  show examples of the configuration of conventional gated clock generating circuits. 
     First, the gated clock generating circuit shown in  FIG. 14  will be described. A clock signal CLK 1  is received at an input terminal  1 , which is connected through a buffer gate BUF 1  to the input terminal of a buffer gate BUF 2  and to the input terminal of a buffer gate BUF 3 . 
     The output terminal of the buffer gate BUF 2  is connected to the clock input terminal of a flip-flop FF 1 . The output terminal of the buffer gate BUF 3  is connected to the second input terminal of an AND gate AN 1 . 
     A data signal Data 1  is received at an input terminal  2 , which is connected to the data input terminal of the flip-flop FF 1 . The output terminal of the flip-flop FF 1  is connected to the first input terminal of the AND gate AN 1 . The output terminal of the AND gate AN 1  is connected to an output terminal  3 , at which a gated clock signal GCLK 1  is fed out. 
     Now, the operation of the gated clock generating circuit configured in this way will be described with reference to the circuit configuration diagram of  FIG. 14  and a timing chart of  FIG. 15A . The clock signal CLK 1  received at the input terminal  1 , through the buffer gate BUF 1  and the buffer gate BUF 2 , reaches the clock input terminal of the flip-flop FF 1 . The data signal Data 1  received at the input terminal  2  reaches the data input terminal of the flip-flop FF 1 . As a result, from the output terminal  1  of the flip-flop FF 1  to the first input terminal of the AND gate AN 1  is fed a gate signal Gate 1 , which has, as shown in  FIG. 15A , a waveform having inversion points of the data signal Data 1  delayed up to rising edges of the clock signal CLK 1 . 
     The clock signal CLK 1  received at the input terminal  1  reaches the second input terminal of the AND gate AN 1  as well. Thus, the AND gate AN 1  outputs to the output terminal  3  the gated clock signal GCLK 1 , which is the AND of the gate signal Gate 1  and the clock signal CLK 1 . 
     In this way, by designating with the input of the data signal the period in which the clock signal is needed, it is possible to output the clock signal only in the period in which it is needed, in the form of the gated clock signal GCLK 1 . 
     Next, the gated clock generating circuit shown in  FIG. 16  will be described. A clock signal CLK 2  is received at an input terminal  4 , which is connected to the input terminal of an inverter INV 2  and to the input terminal of a buffer gate BUF 5 . 
     The output terminal of the inverter INV 2  is connected through a buffer gate BUF 4  to the clock input terminal of a flip-flop FF 3 . The output terminal of the buffer gate BUF 5  is connected to the second input terminal of an AND gate AN 3 . 
     A data signal Data 2  is received at an input terminal  5 , which is connected to the data input terminal of the flip-flop FF 3 . The output terminal of the flip-flop FF 3  is connected to the first input terminal of the AND gate AN 3 . The output terminal of the AND gate AN 3  is connected to an output terminal  6 , at which a gated clock signal GCLK 2  is fed out. 
     Now, the operation of the gated clock generating circuit configured in this way will be described with reference to the circuit configuration diagram of  FIG. 16  and a timing chart of  FIG. 17A . The clock signal CLK 2  received at the input terminal  4  is inverted by the inverter INV 2 , and then, through the buffer gate BUF 4 , reaches the clock input terminal of the flip-flop FF 3 . The data signal Data 2  received at the input terminal  5  reaches the data input terminal of the flip-flop FF 3 . As a result, from the output terminal of the flip-flop FF 3  to the first input terminal of the AND gate AN 3  is fed a gate signal Gate 3 , which has, as shown in  FIG. 17A , a waveform having inversion points of the data signal Data 2  delayed up to trailing edges of the clock signal CLK 2 . 
     The clock signal CLK 2  received at the input terminal  4 , through the buffer gate BUF 5 , reaches the second input terminal of the AND gate AN 3  as well. Thus, the AND gate AN 3  outputs to the output terminal  6  the gated clock signal GCLKC 2 , which is the AND of the gate signal Gate 3  and the clock signal CLK 2 . 
     In this way, by designating with the input of the data signal the period in which the clock signal is needed, it is possible to output the clock signal only in the period in which it is needed, in the form of the gated clock signal GCLK 2 . 
     However, different delays are produced depending on arrangement and interconnection, and therefore an edge of the gate signal reaching the first input terminal of the AND gate outputting the gated clock signal does not necessarily coincides with the corresponding edge of the clock signal reaching the second input terminal of the same AND gate as shown in  FIG. 15A  or  17 A. 
     For example, in the gated clock generating circuit shown in  FIG. 14 , if the clock signal CLK 1  reaches the AND gate AN 1  earlier than the gate signal Gate 1  does, then, as shown in  FIG. 15B , in the vicinity of an inversion points of the gate signal Gate 1 , there is created a period t 1  in which the clock signal CLK 1  and the gate signal Gate 1  are simultaneously high. This produces a glitch in the gated clock signal GCLK 1  in the period t 1 . By contrast, if the gate signal Gate 1  reaches the AND gate AN 1  earlier than the clock signal CLK 1  does, then, as shown in  FIG. 15C , in the vicinity of an inversion points of the gate signal Gate 1 , no period is created in which the clock signal CLK 1  and the gate signal Gate 1  are simultaneously high. Thus, no glitch is produced in the gated clock signal GCLK 1 . 
     On the other hand, in the gated clock generating circuit shown in  FIG. 16 , if the gate signal Gate 3  reaches the AND gate AN 3  earlier than the clock signal CLK 2  does, then, as shown in  FIG. 17C , in the vicinity of an inversion points of the gate signal Gate 3 , there is created a period t 2  in which the clock signal CLK 2  and the gate signal Gate 3  are simultaneously high. This produces a glitch in the gated clock signal GCLK 2  in the period t 2 . By contrast, if the clock signal CLK 2  reaches the AND gate AN 3  earlier than the gate signal Gate 3  does, then, as shown in  FIG. 17B , in the vicinity of an inversion points of the gate signal Gate 3 , no period is created in which the clock signal CLK 2  and the gate signal Gate 3  are simultaneously high. Thus, no glitch is produced in the gated clock signal GCLK 2 . 
     Such glitches in the gated clock signal may cause malfunctioning of the circuit to which it is fed. To avoid this, in a clock-synchronous circuit, after arrangement and interconnection, it is essential to check the delay times produced in the clock and gate signals before they reach the AND gate outputting the gated clock signal. If glitches are found to appear in the gated clock signal, it is inevitable to retry arrangement and interconnection, as by inserting redundant circuits, or even to redesign the whole circuit in order to adjust the delay times in the clock and gate signals. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a gated clock generating circuit free from glitches. 
     To achieve the above object, according to the present invention, a gated clock generating circuit is provided with: a first gate signal generating circuit that receives a continuously pulsating clock signal and that generates a first gate signal having inversion points synchronous with edges of the clock signal; a second gate signal generating circuit that generates a second gate signal deviated by half the period of the clock signal relative to the first gate signal; and an output control circuit that turns on and off the output of the clock signal in accordance with the first and second gate signals. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       This and other objects and features of the present invention will become clear from the following description, taken in conjunction with the preferred embodiments with reference to the accompanying drawings in which: 
         FIG. 1  is a diagram showing the configuration of the gated clock generating circuit of a first embodiment of the invention; 
         FIG. 2  is a diagram showing the configuration of the gated clock generating circuit of a second embodiment of the invention; 
         FIG. 3  is a timing chart showing the operation of the gated clock generating circuit of  FIG. 1 ; 
         FIG. 4  is a diagram showing the state changes taking place in the periods T 1  through T 3  shown in  FIG. 3 ; 
         FIG. 5  is a diagram showing the state changes taking place in the periods T 4  through T 6  shown in  FIG. 3 ; 
         FIG. 6  is a timing chart showing the operation of the gated clock generating circuit of  FIG. 2 ; 
         FIG. 7  is a diagram showing the state changes taking place in the periods T 7  through T 9  shown in  FIG. 6 ; 
         FIG. 8  is a diagram showing the state changes taking place in the periods T 10  through T 12  shown in  FIG. 6 ; 
         FIG. 9  is a diagram showing the circuit configuration of a clock-synchronous circuit incorporating the gated clock generating circuit of the  FIG. 1 ; 
         FIG. 10  is a diagram showing the configuration of a circuit modifying apparatus; 
         FIG. 11A  is a flow chart of the procedure for modifying the net list, showing its portion up to the step of adding a flip-flop; 
         FIG. 11B  is a flow chart of the procedure for modifying the net list, showing its portion after the step of adding a flip-flop; 
         FIG. 12  is a diagram showing a description in HDL representing the clock-synchronous circuit of  FIG. 9 ; 
         FIG. 13A  is a flow chart of the procedure for modifying the description in HDL, showing its portion up to the step of adding a description representing a flip-flop; 
         FIG. 13B  is a flow chart of the procedure for modifying the description in HDL, showing its portion after the step of adding a description representing a flip-flop; 
         FIG. 14  is a diagram showing an example of the configuration of a conventional gated clock generating circuit; 
         FIG. 15A  is a timing chart showing the operation of the gated clock generating circuit of  FIG. 14 , in a case where the delay times in the gate and clock signals are equal; 
         FIG. 15B  is a timing chart showing the operation of the gated clock generating circuit of  FIG. 14 , in a case where the gate signal is delayed more than the clock signal; 
         FIG. 15C  is a timing chart showing the operation of the gated clock generating circuit of  FIG. 14 , in a case where the clock signal is delayed more than the gate signal; 
         FIG. 16  is a diagram showing another example of the configuration of a conventional gated clock generating circuit; 
         FIG. 17A  is a timing chart showing the operation of the gated clock generating circuit of  FIG. 16  in a case where the delay times in the gate and clock signals are equal; 
         FIG. 17B  is a timing chart showing the operation of the gated clock generating circuit of  FIG. 16 , in a case where the gate signal is delayed more than the clock signal; 
         FIG. 17C  is a timing chart showing the operation of the gated clock generating circuit of  FIG. 16 , in a case where the clock signal is delayed more than the gate signal,; 
         FIGS. 18A ,  18 B, and  18 C are diagrams showing the configuration of a clock-synchronous circuit; 
         FIG. 19  is a diagram showing the configuration of a clock-synchronous circuit incorporating the gated clock generating circuit of  FIG. 14 ; and 
         FIG. 20  is a diagram showing a description in HDL representing the clock-synchronous circuit of  FIG. 19 . 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Hereinafter, embodiments of the present invention will be described with reference to the drawings.  FIG. 1  shows the configuration of the gated clock generating circuit of a first embodiment of the invention. It is to be noted that such circuit elements and signals as are found also in  FIG. 14  are identified with the same symbols. 
     A clock signal CLK 1  is received at an input terminal  1 , which is connected through the buffer gate BUF 1  to the input terminal of a buffer gate BUF 2 , to the input terminal of the buffer gate BUF 3 , and to the input terminal of an inverter INV 1 . 
     The output terminal of the buffer gate BUF 2  is connected to the clock input terminal of a flip-flop FF 1 . The output terminal of the buffer gate BUF 3  is connected to the second input terminal of an AND gate AN 1 . The output terminal of the inverter INV 1  is connected to the clock input terminal of a flip-flop FF 2 . 
     A data signal Data 1  is received at an input terminal  2 , which is connected to the data input terminal of the flip-flop FF 1  and to the data input terminal of the flip-flop FF 2 . The output terminal of the flip-flop FF 1  is connected to the first input terminal of the AND gate AN 1 . The output terminal of the AND gate AN 1  is connected to the first input terminal of an AND gate AN 2 . The output terminal of the flip-flop FF 2  is connected to the second input terminal of the AND gate AN 2 . The output terminal of the AND gate AN 2  is connected to an output terminal  3 , at which a gated clock signal GCLK 1  is fed out. 
     Now, the operation of the gated clock generating circuit configured in this way will be described with reference to the circuit configuration diagram of  FIG. 1  and a timing chart of  FIG. 3 . It is to be noted that the clock signal CLK 1  and the data signal Data 1  fed to the gated clock generating circuit shown in  FIG. 1  have the same waveforms as those shown in  FIG. 15A . 
     The clock signal CLK 1  received at the input terminal  1 , through the buffer gate BUF 1  and the buffer gate BUF 2 , reaches the clock input terminal of the flip-flop FF 1 . The data signal Data 1  received at the input terminal  2  reaches the data input terminal of the flip-flop FF 1 . As a result, from the output terminal of the flip-flop FF 1  to the first input terminal of the AND gate AN 1  is fed a gate signal Gate 1 , which has, as shown in  FIG. 3 , a waveform having inversion points of the data signal Data 1  delayed up to rising edges of the clock signal CLK 1 . 
     The clock signal CLK 1  received at the input terminal  1 , through the buffer gate BUF 3 , reaches the second input terminal of the AND gate AN 1  too. The AND gate AN 1  outputs to the first input terminal of the AND gate AN 2  a signal that is the AND of the gate signal Gate 1  and the clock signal CLK 1 . 
     The clock signal CLK 1  received at the input terminal  1 , through the buffer gate BUF 1  and the inverter INV 1 , reaches the clock input terminal of the flip-flop FF 2  as well. The data signal Data 1  received at the input terminal  2  reaches the data input terminal of the flip-flop FF 2  as well. As a result, from the output terminal of the flip-flop FF 2  to the second input terminal of the AND gate AN 2  is fed a gate signal Gate 2 , which has, as shown in  FIG. 3 , a waveform having inversion points of the data signal Data 1  delayed up to trailing edges of the clock signal CLK 1 . 
     The data signal Data 1  fed to the data input terminal of the flip-flop FF 1  is generated somewhere in a clock-synchronous circuit that incorporates the gated clock generating circuit of  FIG. 1 . Since the clock-synchronous circuit has a synchronized design, the data signal Data 1  is a signal generated from a signal that changes states on rising edges of the clock signal CLK 1 . Therefore, the gate signal Gate 2  output from the flip-flop FF 2  is a signal advanced by half the period of the clock signal CLK 1  relative to the gate signal Gate 1 . 
     As described above, the AND gate AN 2  receives, at its first input terminal, a signal which is the AND of the gate signal Gate 1  and the clock signal CLK 1  and, at its second input terminal, the gate signal Gate 2 . Thus, the AND gate AN 2  outputs to the output terminal  3  the gated clock signal GCLK 1 , which is the AND of the gate signal Gate 1 , the gate signal Gate 2 , and the clock signal CLK 1 . It is to be noted that the gate signal Gate 1  and the gated clock signal GCLK 1  have the same waveforms as those shown in  FIG. 15A . 
     In this way, by designating with the input of the data signal the period in which the clock signal is needed, it is possible to output the clock signal only in the period in which it is needed, in the form of the gated clock signal GCLK 1 . 
     The gated clock generating circuit of  FIG. 1  is free from glitches, and now how this is achieved will be described.  FIG. 4  shows the state changes of the input signals to the AND gate AN 1  and the input and output signals to and from the AND gate AN 2  in the periods T 1 , T 2 , and T 3  shown in  FIG. 3 .  FIG. 5  shows the state changes of the input signals to the AND gate AN 1  and the input and output signals to and from the AND gate AN 2  in the periods T 4 , T 5 , and T 6  shown in  FIG. 3 . In  FIGS. 4 and 5 , in each circle are indicated, from left, the logic state of the clock signal CLK 1 , the logic state of the gate signal Gate 1 , the logic state of the gate signal Gate 2 , and then, on the right of the symbol “/,” the output state of the AND gate AN 2 , i.e., the logic state of the gated clock signal GCLK 1 . 
     First,  FIG. 4  will be described. In the period T 1 , the states are “100/0.” In the transition from the period T 1  to the period T 2 , the clock signal CLK 1  and the gate signal Gate 2  are inverted, so that the states eventually change to “001/0.” Here, depending on arrangement and interconnection in the gated clock generating circuit, the states can change in one of the following two ways: if the clock signal CLK 1  is inverted earlier than the gate signal Gate 2 , the states change from “100/0” to “000/0” to “001/0”; if the gate signal Gate 2  is inverted earlier than the clock signal CLK 1 , the states change from “100/0” to “101/0” to “001/0.” 
     In whichever way the states may change, the logic state of the gated clock signal GCLK 1  remains “0.” Thus, in the transition from the period T 1  to the period T 2 , no glitch appears in the gated clock signal GCLK 1 . 
     In the period T 2 , the states are “001/0.” In the transition from the period T 2  to the period T 3 , the clock signal CLK 1  and the gate signal Gate 1  are inverted, so that the states eventually change to “111/1.” Here, depending on arrangement and interconnection in the gated clock generating circuit, the states can change in one of the following two ways: if the clock signal CLK 1  is inverted earlier than the gate signal Gate 1 , the states change from “001/0” to “101/0” to “111/1”; if the gate signal Gate 1  is inverted earlier than the clock signal CLK 1 , the states change from “001/0” to “011/0” to “111/1.” 
     In whichever way the states may change, the logic state of the gated clock signal GCLK 1  changes from “0” to “1” only once before the period T 3  has started. Thus, in the transition from the period T 2  to the period T 3 , no glitch appears in the gated clock signal GCLK 1 . 
     Next,  FIG. 5  will be described. In the period T 4 , the states are “111/1.” In the transition from the period T 4  to the period T 5 , the clock signal CLK 1  and the gate signal Gate 2  are inverted, so that the states eventually change to “010/0.” Here, depending on arrangement and interconnection in the gated clock generating circuit, the states can change in one of the following two ways: if the clock signal CLK 1  is inverted earlier than the gate signal Gate 2 , the states change from “111/1” to “011/0” to “010/0”; if the gate signal Gate 2  is inverted earlier than the clock signal CLK 1 , the states change from “111/1” to “110/0” to “010/0.” 
     In whichever way the states may change, the logic state of the gated clock signal GCLK 1  changes from “1” to “0” only once and thereafter remains “0.” Thus, in the transition from the period T 4  to the period T 5 , no glitch appears in the gated clock signal GCLK 1 . 
     In the period T 5 , the states are “010/0.” In the transition from the period T 5  to the period T 6 , the clock signal CLK 1  and the gate signal Gate 1  are inverted, so that the states eventually change to “100/0.” Here, depending on arrangement and interconnection in the gated clock generating circuit, the states can change in one of the following two ways: if the clock signal CLK 1  is inverted earlier than the gate signal Gate 1 , the states change from “010/0” to “110/0” to “100/0”; if the gate signal Gate 1  is inverted earlier than the clock signal CLK 1 , the states change from “010/0” to “000/0” to “100/0.” 
     In whichever way the states may change, the logic state of the gated clock signal GCLK 1  remains “0” Thus, in the transition from the period T 5  to the period T 6 , no glitch appears in the gated clock signal GCLK 1 . 
     In this way, the gated clock generating circuit of  FIG. 1  produces no glitches. This prevents malfunctioning of a circuit that is fed with the gated clock signal output from the gated clock generating circuit of  FIG. 1 . Thus, there is no need to retry arrangement and interconnection, as by inserting redundant circuits, or redesign the whole circuit in order to adjust delay times. 
       FIG. 2  shows the configuration of the gated clock generating circuit of a second embodiment of the invention. It is to be noted that such circuit elements and signals as are found also in  FIG. 16  are identified with the same symbols. 
     A clock signal CLK 2  is received at an input terminal  4 , which is connected to the input terminal of an inverter INV 2  and to the input terminal of a buffer gate BUF 5 . 
     The output terminal of the inverter INV 2  is connected to the input terminal of a buffer gate BUF 4  and to the input terminal of an inverter INV 3 . The output terminal of the buffer gate BUF 5  is connected to the second input terminal of an AND gate AN 3 . 
     The output terminal of the buffer gate BUF 4  is connected to the clock input terminal of a flip-flop FF 3 . The output terminal of the inverter INV 3  is connected to the clock input terminal of a flip-flop FF 4 . 
     A data signal Data 2  is received at an input terminal  5 , which is connected to the data input terminal of the flip-flop FF 3 . The output terminal of the flip-flop FF 3  is connected to the first input terminal of the AND gate AN 3  and to the data input terminal of the flip-flop FF 4 . The output terminal of the AND gate AN 3  is connected to the first input terminal of an AND gate AN 4 . The output terminal of the flip-flop FF 4  is connected to the second input terminal of the AND gate AN 4 . The output terminal of the AND gate AN 4  is connected to an output terminal  6 , at which a gated clock signal GCLK 2  is fed out. 
     Now, the operation of the gated clock generating circuit configured in this way will be described with reference to the circuit configuration diagram of  FIG. 2  and a timing chart of  FIG. 6 . The clock signal CLK 2  received at the input terminal  4  is inverted by the inverter INV 2 , and then, through the buffer gate BUF 4 , reaches the clock input terminal of the flip-flop FF 3 . The data signal Data 2  received at the input terminal  5  reaches the data input terminal of the flip-flop FF 3 . As a result, from the output terminal of the flip-flop FF 3  to the first input terminal of the AND gate AN 3  is fed a gate signal Gate 3 , which has, as shown in  FIG. 6 , a waveform having inversion points of the data signal Data 2  delayed up to trailing edges of the clock signal CLK 2 . 
     The clock signal CLK 2  received at the input terminal  4 , through the buffer gate BUF 5 , reaches the second input terminal of the AND gate AN 3  too. The AND gate AN 3  outputs to the first input terminal of the AND gate AN 4  a signal that is the AND of the gate signal Gate 3  and the clock signal CLK 2 . 
     The clock signal CLK 2  received at the input terminal  4 , through the inverters INV 2  and INV 3 , reaches the clock input terminal of the flip-flop FF 4  as well. The gate signal Gate 3  output from the output terminal of the flip-flop FF 3  reaches the data input terminal of the flip-flop FF 4 . As a result, from the output terminal of the flip-flop FF 4  to the second input terminal of the AND gate AN 4  is fed a gate signal Gate 4 , which has a waveform having inversion points of the gate signal Gate 3  delayed up to rising edges of the clock signal CLK 2 . 
     The gate signal Gate 4  output from the flip-flop FF 4  is a delayed version of the gate signal Gate 3  output from the flip-flop FF 3 , and therefore the gate signal Gate 4  output from the flip-flop FF 4  is a signal delayed by half the period of the clock signal CLK 1  relative to the gate signal Gate 3  output from the flip-flop FF 3 . 
     As described above, the AND gate AN 4  receives, at its first input terminal, a signal which is the AND of the gate signal Gate 3  and the clock signal CLK 2  and, at its second input terminal, the gate signal Gate 4 . Thus, the AND gate AN 4  outputs to the output terminal  6  the gated clock signal GCLK 2 , which is the AND of the gate signal Gate 3 , the gate signal Gate 4 , and the clock signal CLK 2 . It is to be noted that the gate signal Gate 3  and the gated clock signal GCLK 2  have the same waveforms as those shown in  FIG. 17A . 
     In this way, by designating with the input of the data signal the period in which the clock signal is needed, it is possible to output the clock signal only in the period in which it is needed, in the form of the gated clock signal GCLK 2 . 
     The gated clock generating circuit of  FIG. 2  is free from glitches, and now how this is achieved will be described.  FIG. 7  shows the state changes of the input signals to the AND gate AN 3  and the input and output signals to and from the AND gate AN 4  in the periods T 7 , T 8 , and T 9  shown in  FIG. 6 .  FIG. 8  shows the state changes of the input signals to the AND gate AN 3  and the input and output signals to and from the AND gate AN 4  in the periods T 10 , T 11 , and T 12  shown in  FIG. 6 . In  FIGS. 7 and 8 , in each circle are indicated, from left, the logic state of the clock signal CLK 2 , the logic state of the gate signal Gate 3 , the logic state of the gate signal Gate 4 , and then, on the right of the symbol “/,” the output state of the AND gate AN 4 , i.e., the logic state of the gated clock signal GCLK 2 . 
     First,  FIG. 7  will be described. In the period T 7 , the states are “100/0.” In the transition from the period T 7  to the period T 8 , the clock signal CLK 2  and the gate signal Gate 3  are inverted, so that the states eventually change to “010/0.” Here, depending on arrangement and interconnection in the gated clock generating circuit, the states can change in one of the following two ways: if the clock signal CLK 2  is inverted earlier than the gate signal Gate 3 , the states change from “100/0” to “000/0” to “010/0”; if the gate signal Gate 3  is inverted earlier than the clock signal CLK 2 , the states change from “100/0” to “110/0” to “010/0.” 
     In whichever way the states may change, the logic state of the gated clock signal GCLK 2  remains “0.” Thus, in the transition from the period T 7  to the period T 8 , no glitch appears in the gated clock signal GCLK 2 . 
     In the period T 8 , the states are “010/0.” In the transition from the period T 8  to the period T 9 , the clock signal CLK 2  and the gate signal Gate 4  are inverted, so that the states eventually change to “111/1.” Here, depending on arrangement and interconnection in the gated clock generating circuit, the states can change in one of the following two ways: if the clock signal CLK 2  is inverted earlier than the gate signal Gate 4 , the states change from “010/0” to “110/0” to “111/1”; if the gate signal Gate 4  is inverted earlier than the clock signal CLK 2 , the states change from “010/0” to “011/0” to “111/1.” 
     In whichever way the states may change, the logic state of the gated clock signal GCLK 2  changes from “0” to “1” only once before the period T 9  has started. Thus, in the transition from the period T 8  to the period T 9 , no glitch appears in the gated clock signal GCLK 2 . 
     Next,  FIG. 8  will be described. In the period T 10 , the states are “111/1.” In the transition from the period T 10  to the period T 11 , the clock signal CLK 2  and the gate signal Gate 3  are inverted, so that the states eventually change to “001/0.” Here, depending on arrangement and interconnection in the gated clock generating circuit, the states can change in one of the following two ways: if the clock signal CLK 2  is inverted earlier than the gate signal Gate 3 , the states change from “111/1” to “011/0” to “001/0”; if the gate signal Gate 3  is inverted earlier than the clock signal CLK 2 , the states change from “111/1” to “101/0” to “001/0.” 
     In whichever way the states may change, the logic state of the gated clock signal GCLK 2  changes from “1” to “0” only once and thereafter remains “0.” Thus, in the transition from the period T 10  to the period T 11 , no glitch appears in the gated clock signal GCLK 2 . 
     In the period T 11 , the states are “001/0.” In the transition from the period T 11  to the period T 12 , the clock signal CLK 2  and the gate signal Gate 4  are inverted, so that the states eventually change to “100/0.” Here, depending on arrangement and interconnection in the gated clock generating circuit, the states can change in one of the following two ways: if the clock signal CLK 2  is inverted earlier than the gate signal Gate 4 , the states change from “001/0” to “101/0” to “100/0”; if the gate signal Gate 4  is inverted earlier than the clock signal CLK 2 , the states change from “001/0” to “000/0” to “100/0.” 
     In whichever way the states may change, the logic state of the gated clock signal GCLK 2  remains “0.” Thus, in the transition from the period T 11  to the period T 12 , no glitch appears in the gated clock signal GCLK 2 . 
     In this way, the gated clock generating circuit of  FIG. 2  produces no glitches. This prevents malfunctioning of a circuit that is fed with the gated clock signal output from the gated clock generating circuit of  FIG. 2 . Thus, there is no need to retry arrangement and interconnection, as by inserting redundant circuits, or redesign the whole circuit in order to adjust delay times. 
     As described earlier, clock-synchronous circuits are generally given a synchronized design. In a synchronized design that uses not only an external clock signal as it is but also an inverted clock signal obtained by inverting that external clock signal, arrangement and interconnection need to be done counting the inverted clock signal as another clock signal. An increased number, like this, of clock signals in which skews need to be minimized not only make arrangement and interconnection difficult, but also increase the number of buffer gates to and from which the clock signals are input and output. This increases the area of the chip on which the clock-synchronous circuit is mounted, and thus increases costs. 
     To avoid this, it is preferable to design a clock-synchronous circuit not as shown in  FIG. 18C , where the clock signals fed to flip-flops FF 28  to FF 31  are grouped into two types, but as shown in  FIG. 18A , where the clock signals fed to flip-flops FF 20  to FF 23  are of a single type, or as shown in  FIG. 18B , where also the clock signals fed to flip-flops FF 24  to FF 27  are of a single type. 
     In the clock-synchronous circuit shown in  FIG. 18A , the clock signals fed to the flip-flops FF 20  to FF 23  are of a single type because a clock signal CLK is fed to all the flip-flops FF 20  to FF 23  directly, i.e. without being passed through an inverter. In the clock-synchronous circuit shown in  FIG. 18B , the clock signals fed to the flip-flops FF 24  to FF 27  are of a single type because a clock signal CLK is fed to all the flip-flops FF 24  to FF 27  through an inverter INV 20 . In the clock-synchronous circuit shown in  FIG. 18C , a clock signal CLK is fed to the flip-flops FF 28  and  29  without being passed through an inverter and to the flip-flops FF 30  and FF 31  through an inverter INV 21 ; thus, the clock signals fed to the flip-flops FF 28  to FF 31  are grouped into two types. 
     When one of the gated clock generating circuits of the invention described above, for example that shown in  FIG. 1 , is incorporated in a clock-synchronous circuit, the overall circuit configuration will be as shown in  FIG. 9 . It is to be noted that, in  FIG. 9 , such circuit elements and signals as are found also in  FIG. 1  are identified with the same symbols. 
     Conventionally, the clock-synchronous circuit of  FIG. 9  needs to be designed counting the clock signal fed to the flip-flop FF 2  as a separate clock signal. This makes it difficult for the designer to give a synchronized design to a clock-synchronous circuit incorporating a gated clock generating circuit according to the invention. 
     To overcome the difficulty, it is advisable to first design a clock-synchronous circuit using a conventional gated clock generating circuit, and then modify the clock-synchronous circuit so that its portion corresponding to the conventional gated clock generating circuit is altered into a gated clock generating circuit according to the invention. Now, how this is achieved will be described specifically. 
       FIG. 10  shows a circuit modifying apparatus for modifying a clock-synchronous circuit so that a conventional gated clock generating circuit incorporated in it is altered into a gated clock generating circuit according to the invention. The circuit modifying apparatus of  FIG. 10  is provided with an input device  11  to which input data is fed such as circuit diagram information or a net list, or a description in hardware description language (herein referred to as “HDL”), an output device  12  that outputs the modified result, a hard disk  13  on which the input data and the modified result are stored, a memory  14  in which data necessary to execute modification is held, a recording medium  15  on which a program for executing modification is recorded, and a CPU (central processor unit)  16  that executes modification according to the program recorded on the recording medium  15 . The CPU  16  is connected through a bus  17  to the input device  11 , output device  12 , hard disk  13 , memory  14 , and recording medium  15 . 
     The CPU  16  reads the program recorded on the recording medium  15 , and, according to the program, executes the procedure described later. The data stored in the memory  14  beforehand includes data of the circuit information and net list of circuit elements to be added to the input data and data of the description in HDL representing the circuit elements to be added to the input data. 
     Now, the procedure executed by the circuit modifying apparatus of  FIG. 10  when it is fed with a net list will be described with reference to the configuration diagram of  FIG. 10  and a flow chart in  FIGS. 11A and 11B . 
       FIG. 11A  shows the procedure up to the step of adding a flip-flop. First, the input device  11  is fed with the net list of a clock-synchronous circuit incorporating a conventional gated clock generating circuit, for example the net list of a circuit as shown in  FIG. 19  (step S 10 ). It is to be noted that, in  FIG. 19 , such circuit elements and signals as are found also in  FIG. 9  are identified with the same symbols. The input device  11  is fed also with the information on at which terminal a clock signal is received, i.e. the information indicating that a clock signal is received at the input terminal  1  (S 20 ). 
     The data fed to the input device  11  is transferred to the memory  14  by the CPU  16 . According to the data transferred to the memory  14 , the CPU  16  then searches the net list for circuit elements connected to the terminal at which the clock signal is received, and enumerates the circuit elements constituting it (step S 30 ). Here, buffer gates and inverters are regarded as part of the wiring, and the circuit elements connected beyond them are searched for. Thus, specifically, the flip-flops FF 1  and FF 10  to FF 12  and the AND gate AN 1  are enumerated. 
     Next, the CPU  16  extracts, from the circuit elements enumerated in step S 30 , those other than the flip-flops receiving the clock signal at their clock input terminals, i.e. only the AND gate AN 1  (step S 40 ). In step S 40 , the AND gate AN 1  is identified as the circuit element that generates a gated clock signal on the basis of the clock signal. 
     Then, the CPU  16  extracts the flip-flop that generates the input signal to the circuit element extracted in step S 40 , i.e. the flip-flop FF 1  (step S 50 ). 
     Next, the CPU  16  checks whether inversion points of the input signal to the circuit element extracted in step S 40  are synchronous with rising edges of the clock signal or not (step S 60 ). Here, the input device  11  may be fed with information indicating whether inversion points of the input signal to the circuit element extracted in step S 40  are synchronous with rising edges of the clock signal or not. Alternatively, it is also possible to search for inverters connected between the input terminal at which the clock signal is received and the flip-flops and, on the basis of the number of inverters found, check whether inversion points of the input signal to the circuit element extracted in step S 40  are synchronous with rising edges of the clock signal or not. 
     If inversion points of the input signal to the circuit element extracted in step S 40  are synchronous with rising edges of the clock signal (“Yes” in step S 60 ), the CPU  16  takes out a flip-flop from the data stored in the memory  14  beforehand, and adds it to the net list as a new flip-flop that receives the same data input as the flip-flop extracted in step S 50  (step S 70 ). The procedure then proceeds to step S 90  shown in  FIG. 11B . 
     On the other hand, if inversion points of the input signal to the circuit element extracted in step S 40  are synchronous not with rising edges of the clock signal but with its trailing edges (“No” in step S 60 ), the CPU  16  takes out a flip-flop from the data stored in the memory  14  beforehand, and adds it to the net list as a new flip-flop that receives, as its data input, the output of the flip-flop extracted in step S 50  (step S 80 ). The procedure then proceeds to step S 90  shown in  FIG. 11B . 
     In the particular case under discussion, it was the net list of the circuit of  FIG. 19  that was fed in in step S 10 , and therefore inversion points of the input signal to the AND gate are synchronous with rising edges of the clock signal. Accordingly, the CPU  16  does not execute step S 80 , but executes step S 70 . That is, it adds to the net list a new flip-flop that receives the same data input as the flip-flop FF 1 . 
       FIG. 11B  shows the procedure after the addition of the flip-flop. In step S 90 , the CPU  16  takes out an inverter from the data stored in the memory  14  beforehand, and adds it to the net list as an inverter that receives the clock signal. Then, the CPU  16  rewrites the net list so that the output of the inverter thus added is connected to the clock input of the flip-flop added in step S 70  or S 80  (step S 100 ). 
     Next, the CPU  16  takes out an AND gate from the data stored in the memory  14  beforehand, adds it to the net list (step S 110 ), and rewrites the net list so that the output of the circuit element extracted in step S 40  and the output of the flip-flop added in step S 70  or S 80  are connected to the inputs of the AND gate thus added (step S 120 ). 
     Then, the CPU  16  rewrites the net list so that the output of the AND gate added in step S 110  is connected to the output terminal that has thus far been connected to the output of the circuit element extracted in step S 40  (step S 130 ), and ends the procedure. The CPU  16  then stores the net list modified through the procedure as the modified result on the hard disk  13 . 
     As the result of the circuit modifying apparatus of  FIG. 10  executing this procedure, the net list of the clock-synchronous circuit of  FIG. 19  is modified to the net list of the clock-synchronous circuit of  FIG. 9 . This permits the designer to design simply a clock-synchronous circuit incorporating a gated clock generating circuit that turns on and off the output of a clock signal on the basis of a single gate signal as conventionally practiced, and thus frees the designer from designing with an increased number of clocks in mind. 
     However, when a circuit is modified by feeding its net list to the circuit modifying apparatus of  FIG. 10  as described above, the modified circuit may turn out to be nonfunctional. For example, in a case where the modified circuit is the clock-synchronous circuit shown in  FIG. 9 , the data signal fed to the data input terminal of the added flip-flop FF 2  there is the data signal Data 1  fed to the data input terminal of the flip-flop FF 1  in the yet-to-be-modified clock-synchronous circuit shown in  FIG. 19 . In the yet-to-be-modified clock-synchronous circuit shown in  FIG. 19 , the data signal Data 1  has only to reach the data input terminal of the flip-flop FF 1  within one whole period, from one rising edge to the next, of the clock signal CLK 1 . On the other hand, in the modified clock-synchronous circuit shown in  FIG. 9 , the data signal Data 1  needs to reach the data input terminal of the added flip-flop FF 2  within the period from one rising edge to the next trailing edge of the clock signal CLK 1 . That is, in the modified clock-synchronous circuit shown in  FIG. 9 , the data signal Data 1  needs to reach the flip-flop FF 2  within half the period conventionally tolerated. In this way, the restrictions on the delay time are now stricter, and therefore the modified clock-synchronous circuit does not always operate normally. 
     To avoid this, instead of modifying what has already been put into a circuit diagram, such as circuit diagram information or a net list, it is advisable to execute modification in a description in HDL before it is subjected to logic synthesis. By executing modification in a description in HDL before logic synthesis, it is possible to check whether the restrictions on delay times are met or not during logic synthesis and thereby check whether a circuit so modified operates normally or not. In addition, it is also possible to optimize various aspects, including delay times, of the circuit. 
     Now, the procedure executed by the circuit modifying apparatus of  FIG. 10  when it is fed with a description in HDL before logic synthesis will be described with reference to a flow chart in  FIGS. 13A and 13B . 
       FIG. 13A  shows the procedure up to the step of adding a description representing a flip-flop. First, the input device  11  is fed with a description in HDL as shown in  FIG. 20  which is logically equivalent to, for example, the clock-synchronous circuit shown in  FIG. 19  (step S 210 ). In  FIG. 20  is shown a description written in VHDL (VHSIC hardware description language), where the portion of the description other than that logically equivalent to the portion  20  of the clock-synchronous circuit of  FIG. 19  is omitted. For simplicity&#39;s sake, in the following explanation, it is assumed that the portion of the description omitted in  FIG. 20  is not dealt with by the procedure. 
     The input device  11  is then fed with information indicating that “clk1” in the description in HDL represents a clock signal (step S 220 ). 
     The data fed to the input device  11  is transferred to the memory  14  by the CPU  16 . According to the data transferred to the memory  14 , the CPU  16  then searches the description in HDL for process statements or concurrent processing statements that use “clk1” as their input, and enumerates them (step S 230 ). As a result, from the description in HDL shown in  FIG. 20 , the process statement A 1  and the concurrent processing statement B 1  are found and enumerated. 
     Next, from the process statements or concurrent processing statements enumerated in step S 230 , the CPU  16  extracts the process statement or concurrent processing statement other than that which substitutes “clk1” for the description “event” representing edges of a signal (step S 240 ). As a result, the concurrent processing statement B 1  alone is extracted. The concurrent processing statement B 1  is a description of receiving “clk1” and “gate1” and outputting a gated clock signal “gclk1.” 
     Then, the CPU  16  extracts the process statement or concurrent processing statement that outputs a signal to be used as an input to the process statement or concurrent processing statement extracted in step S 240  (step S 250 ). As a result, the process statement A 1  that outputs the “gate1” to be used as an input signal to the concurrent processing statement B 1  is extracted. 
     Next, the CPU  16  checks whether edges of the input signal to the process statement or concurrent processing statement extracted in step S 240  are synchronous with rising edges of “clk1” or not (step S 260 ). Edges of the input signal to the process statement or concurrent processing statement extracted in step S 240  are judged to be synchronous with rising edges of “clk1” if the description around “event” is “clk1′ event and clk1=‘1’” and with trailing edges if the description around “event” is “clk1′ event and clk1=‘0.’” 
     If edges of the input signal to the process statement or concurrent processing statement extracted in step S 240  are synchronous with rising edges of “clk1” (“Yes” in step S 260 ), the CPU  16  checks whether the process statement or concurrent processing statement extracted in step S 250  is a description representing only a flip-flop or not. If it includes a description of a circuit other than a flip-flop, the CPU  16  separates it into a description representing only the flip-flop and a description representing the circuit other than the flip-flop. 
     Then, the CPU  16  extracts a description representing a flip-flop from the data stored in the memory  14  beforehand, and adds it to the description in HDL as a new description representing a flip-flop that receives the same data input as the flip-flop represented by the process statement or concurrent processing statement extracted in step S 250  (step S 270 ). The procedure then proceeds to step S 290  shown in  FIG. 13B . 
     On the other hand, if edges of the input signal to the process statement or concurrent processing statement extracted in step S 240  are synchronous not with rising edges of “clk1” but with trailing edges of “clk1” (“No” in step S 260 ), the CPU  16  checks whether the process statement or concurrent processing statement extracted in step S 250  is a description representing only a flip-flop or not. If it includes a description of a circuit other than a flip-flop, the CPU  16  separates it into a description representing only the flip-flop and a description representing the circuit other than the flip-flop. 
     Then, the CPU  16  extracts a description representing a flip-flop from the data stored in the memory  14  beforehand, and adds it to the description in HDL as a new description representing a flip-flop that receives, as its data input, the output of the flip-flop represented by the process statement or concurrent processing statement extracted in step S 250  (step S 280 ). The procedure then proceeds to step S 290  shown in  FIG. 13B . 
     In the particular case under discussion, it was the description in HDL of  FIG. 20  that was fed in in step S 210 , and therefore edges of the input signal to the concurrent processing statement B 1  extracted in step S 240  are synchronous with rising edges of the clock signal. Accordingly, the CPU  16  does not execute step S 280 , but executes step S 270 . Specifically, it operates as follows. 
     Of the description of the process statement A 1 , the portion other than that representing the flip-flop is separated, and is added as a process statement A 2  in  FIG. 12 . Moreover, a new signal name “data_input_to_ff1” representing a data signal fed to the data input terminal of the flip-flop is introduced. To cope with this, the process statement A 1  is modified to a process statement A 3  in  FIG. 12 . That is, the process statement A 1  is separated into the process statements A 2  and A 3  so that the latter after the separation are together logically equivalent to the former before the separation. 
     Furthermore, a new process statement representing a flip-flop that receives the signal “data_input_to_ff1” at its data input terminal is added to the description in HDL. These are the operations specifically performed in step  270 . 
       FIG. 13B  shows the procedure after the addition of the description representing the flip-flop. In step S 290 , the CPU  16  takes out a description representing an inverter from the data stored in the memory  14  beforehand, and adds it to the description in HDL as a description representing an inverter that receives the clock signal. Specifically, the CPU  16  introduces a new signal name “inv_clk1,” and adds to the description in HDL a new concurrent processing statement B 2  shown in  FIG. 12 . 
     Then, the CPU  16  rewrites the description in HDL so that the output of the inverter represented by the description thus added is connected to the clock input terminal of the flip-flop represented by the description added in step S 270  or S 280  (step S 300 ). Specifically, the signal “inv_clk1” is introduced into “event” in the process statement added in step S 270  or S 280 , and thus a process statement A 4  shown in  FIG. 12  is created. 
     Next, the CPU  16  takes out a description representing an AND gate from the data stored in the memory  14  beforehand, and adds it to the description in HDL (step S 310 ). 
     Moreover, the CPU  16  rewrites the description in HDL, by introducing a new signal name “gate1_tmp,” so that the output of the process statement or concurrent processing statement extracted in step S 240  and the output of the flip-flop represented by the description added in step S 270  or S 280  are connected to the inputs of the AND gate represented by the description thus added (step S 320 ). As a result, the process statement B 1  is modified to a concurrent processing statement B 3  shown in  FIG. 12 . 
     Then, the CPU  16  rewrites the description in HDL so that the output signal of the AND gate represented by the description added in step S 310  is identical with the output signal of the process statement or concurrent processing statement extracted in step S 230  (step S 330 ), and ends the procedure. As a result, the description added in step S 310  becomes a concurrent processing statement B 4  shown in  FIG. 12 . 
     Furthermore, the CPU  16  stores the description in HDL modified through the procedure as the modified result on the hard disk  13 . As the result of the circuit modifying apparatus of  FIG. 10  executing this procedure, the description in HDL shown in  FIG. 20  is modified to the description in HDL shown in  FIG. 12 . The description in HDL shown in  FIG. 12  represents the clock-synchronous circuit of  FIG. 9 . It is to be noted that, in the description in HDL shown in  FIG. 12 , the portion other than that logically equivalent to the portion  21  of the clock-synchronous circuit of  FIG. 9  is omitted. 
     Thereafter, when the description in HDL thus modified is subjected to logic synthesis, the designer, by performing the logic synthesis with adequate restrictions imposed on delay times, can check whether the clock-synchronous circuit as a whole, including the added circuit elements, operates normally or not. Moreover, when the clock-synchronous circuit is found to operate normally, the designer can make adjustments in terms of not only delay times but also other restricting factors such as the fan-out and signal transition times. This permits logic synthesis of a clock-synchronous circuit that is more likely to operate as designed than when designed by the use of circuit information or a net list, and thus enhances the reliability of the clock-synchronous circuit so designed.