Abstract:
A method of configuring a FET amplifier with two inputs demonstrating similar-phased response to similar-phased inputs. One input can be used as a feedback path in suitable amplifier circuits, improving frequency performance by decreasing feedback resistance. The second input provides the means for a high impedance connection to a drive signal. The present invention is particularly applicable to applications involving constant voltage sources and constant current active sources with or without cascoding, in both single-ended and differential configurations.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    There are several methods currently used to develop feedback in an amplifier. One technique is to use a differential pair to accommodate negative feedback by using one side of the differential pair for a single-ended input and the other as a feedback path. This can be accomplished directly, as illustrated by U.S. Pat Nos. #4,107,619, #4,188,588 and #5,260,672, or more abstractly in high gain amplifiers vis-a-vis well known operational amplifier feedback methods. Both of these methods require numerous active devices in the form of current sources, current mirrors, gain stages, and the initial differential pair itself In addition to the employment of numerous active devices, high gain amplifiers used in the manner of operational amplifiers suffer the problem of relatively low input resistance and relatively high feedback resistance. 
       BRIEF SUMMARY OF THE INVENTION 
       [0002]    The present invention depicts a method of configuring FET-based amplifiers in a current balancing circuit that allows for two direct gate inputs demonstrating arbitrary shunted input resistance and low series gate resistance. Used in a circuit with an output signal that is out of phase with the input, negative feedback can be introduced into the circuit while utilizing minimal active circuit components and simultaneously raising the input impedance and decreasing the feedback path impedance. The realization of this invention is an amplifier with decreased distortion and lowered output impedance with improved frequency performance. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0003]      FIG. 1 : Illustration of invention using N-channel MOSFETs with a constant current source. 
           [0004]      FIG. 2 : Illustration of invention using N-channel JFETs with a constant current source. 
           [0005]      FIG. 3 : Illustration of invention using P-channel MOSFETs with a constant current source. 
           [0006]      FIG. 4 : Illustration of invention using P-channel JFETs with a constant current source. 
           [0007]      FIG. 5 : Illustration of the invention using N-channel MOSFETs in a cascode configuration with a constant current source. 
           [0008]      FIG. 6 : Illustration of the invention in a differential application using N-channel MOSFETs in a cascode configuration with constant current sources. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0009]    The topology of the amplifier depicted in  FIG. 1  comprises a symmetrical arrangement of similar N-channel MOSFETs Q 11  and Q 12 . A constant current source K 1 , fed by power supply +V 1 , produces a current I 10  that is divided as evenly as is practical in the quiescent state between the two N-channel MOSFETs Q 11  and Q 12  at node N 1 , resulting in channel currents I 11  and I 12 , respectively. It should be appreciated by those trained in the art that, while the invention is demonstrated by way of example using active, constant current sources, effects consistent with the spirit of the present invention can be achieved with constant voltage sources. Source resistors R 11  and R 12  have an induced voltage I 11 R 11  and I 12 R 12  that biases Q 11  and Q 12 , respectively, resulting in, effectively, a two transistor degenerated amplifier with resistors R 11  and R 12  terminating in power supply −V 1 . R 11  and R 12  are typically similar in value, though gate-source offset variations in Q 11  and Q 12  can be accommodated with small relative changes in the values of R 11  and R 12 . R 11  and R 12  may be omitted depending on the operating characteristics of transistors Q 11  and Q 12 . The gate of Q 11  is connected to a bias voltage V bias1  by an input resistor R 10 , where V bias1  is a common reference point for the input V in1  and the output V out1 . Given the high impedance of the gate of Q 11 , R 10  is effectively the input impedance experienced by the source V in1 . 
         [0010]    Capacitor C 1  provides quiescent DC immunity from the voltage at node N 1  to the resistor divider network comprised of resistors R 13  and R 14 . Those trained in the art will observe that, notwithstanding the effects of transistor Q 12 , the amplifier comprising constant current source K 1  and transistor Q 11  will create an amplified, out of phase signal at terminal V out1 . The gate of transistor Q 12  is driven out of phase from the input the magnitude of which is selectable by the values of resistors R 13  and R 14 . Negative feedback is injected at the gate of Q 12 , manifesting as negative feedback in the cumulative current I 11 +I 12  and the resultant voltage at node N 1 . 
         [0011]    Signal variations driven by input V in1  manifest as output V out1 , as node N 1  observes deviations between constant current I 10  and cumulative transistor current I 11 +I 12 . This results in a change in the voltage at node N 1  and induces output voltage V out1  across the total load resistance, which is R 13 +R 14  in parallel with any external load resistance. The series resistance of R 13  and R 14  is chosen to reflect minimal change of the total load resistance when the external load is applied while simultaneously being as low in value as possible to reduce the deleterious effects of the gate capacitance of Q 12 . The value of C 1  at frequencies of interest must be chosen such that the reactance of C 1  is small compared with the total load resistance. 
         [0012]    It should be noted that the feedback network formed by decoupling capacitor C 1  and resistors R 13  and R 14  is not specific to the present invention. Any feedback network, passive or active, accomplishing the objective of introducing an out of phase signal at the gate of Q 12  originating at node N 1  that is consistent with the DC operating parameters of the amplifier given specific choices of power supplies +V 1  and −V 1 , currents I 10 , I 11  and I 12 , source resistors R 11  and R 12 , gate bias voltage V bias1 , and transistor types Q 11  and Q 12 , accomplishes the claims of the present invention. The network shown, being versatile with respect to application, is a preferred embodiment of the use of the invention in a practical circuit. 
         [0013]      FIG. 2  depicts a claimed topology of the present invention that is identical except for transistors Q 21  and Q 22  being replaced by N-channel JFETs.  FIG. 3  depicts a claimed topology involving P-channel MOSFETs Q 31  and Q 32 . In this illustration it should be noted that, relative to the similarly drawn circuits previously presented, power supplies +V 3  and −V 3  are reversed. Furthermore, the active constant current source K 3  induces a current I 30  that is reverse the complimentary topology.  FIG. 4  depicts the present invention using P-channel JFETs Q 41  and Q 42 . 
         [0014]    The amplifier is further improved in  FIG. 5  with the addition of a cascode stage comprising transistor Q 53  and associated gate bias voltage V ref5 . As a result, capacitor C 5  decouples the drain of Q 53  rather than node N 5 . Those trained in the art will recognize the enhanced benefit of this arrangement vis-a-vis improving frequency performance by decreasing the effective gate capacitance of transistors Q 51  and Q 52 . While improved with respect to the mitigation of effective gate capacitance, this amplifier experiences the same relationship between values of external load resistance and capacitor C 5  with respect to frequency performance. 
         [0015]    The amplifier is made differential as illustrated in  FIG. 6  by combining two symmetrical copies of the amplifier depicted in  FIG. 5 . In this case the two halves of the resulting differential amplifier are identified by diagram suffixes a and b. The two halves of the amplifier are driven by inputs V in6a  and V in6b  with signals that are out of phase with each other with respect to bias voltage V bias6 . This results in a differential signal output exhibiting voltages V out6a  and V out6b , respectively. The symmetrical arrangement of the differential amplifier allows the position of output decoupling capacitors C 6a  and C 6b  to be altered such that the external load resistance is connected directly between terminal V out6a  and V out6b . Cascode transistor gate reference voltages V ref6a  and V ref6b  can be adjusted to null the quiescent voltage differential between V out6a  and V out6b . Since series resistance R 63a +R 64a  (as well as R 63b +R 64b ) is designed to be large compared to the external load resistance between terminals V out6a  and V out6b , the values of C 6a  and C 6b  can be decreased from that of the non-differential variations of the invention while maintaining similar frequency performance. It is only the feedback to transistors Q 62a  and Q 62b  that is effected by this change in topology (compared to that of transistor Q 52 ,  FIG. 5 , for example). 
         [0016]    As with the amplifier topology depicted in  FIG. 1 , the amplifier topologies depicted in  FIG. 5  and  FIG. 6  are amenable to the transistor type alternatives presented in  FIG. 2 ,  FIG. 3  and  FIG. 4  (namely N-channel JFETs, P-channel MOSFETs and P-channel JFETs).  FIG. 5  and  FIG. 6  are illustrated as exemplars of these alternatives while abiding the spirit of the present invention.