Abstract:
CMOS static RAM based memory system, which reduces power consumption and increases operation speed by disconnecting cell power supply during write operation. Additional transistors are provided between Sources of the SRAM cell transistors and supply voltage or ground voltage connection. These are switched off during write, in order to interrupt a dynamic current path to supply or to ground. Additionally, implementation of inductive elements into the power supply can help to reduce current spikes during switching.

Description:
CROSS REFERENCE OF RELATED APPLICATIONS  
       [0001]     U.S. Pat. No. 6,314,041 B1 (Frey Christophe) 6 Nov. 2001 (2001-11-06).  
         [0002]     Patent abstracts of Japan vol. 007, no. 241 (P-232), 26 Oct. 1983 (1983-10-26) &amp; JP 58 128087 A (Nippon Denshin Denwa Kosha), 30 Jul. 1983 (1983-07-30).  
         [0003]     US 2005/018520 A1 (Marshall Andrew) 27 Jan. 2005 (2005-01-27).  
         [0004]     U.S. Pat. No. 4,864,544 A (SPAK ET AL) 5 Sep. 1989 (1989-09-05).  
         [0005]     U.S. Pat. No. 6,147,898 A (YAMADA ET AL) 14 Nov. 2000 (2000-11-14).  
         [0006]     Patent Abstracts of Japan Vol. 005, no. 088 (P-065), 9 Jun. 1981 (1981-06-09) &amp; JP 56 034189 A (Toshiba corp.), 6 Apr. 1981 (1981-04-06).  
         [0007]     This patent application is referred to the international application PCT/IB2005/001931 filed on Jun. 23 rd  2005, together with amendments according to PCT rule 52 &amp; article 28.  
       TECHNICAL FIELD  
       [0008]     This design is a digital CMOS SRAM cell based implementation of a static memory system, at the level of electronic implementation.  
       BACKGROUND ART  
       [0009]     The background art is the CMOS memory cell, where the Pull-up FETs were coupled to the Supply line directly, and the Pull-down FETs were coupled to Ground directly, the advantages of this model were:  
         [0010]     1- Every point in a memory cell was a strong point, due to absence of resistive components, so every point inside the memory cell was coupled to either Supply line or Ground via a very low resistance (The FET Drain to Source resistance), this led to high immunity of a memory cell against any interference when used at high operating frequencies.  
         [0011]     2- The absence of resistive components in the dynamic current path led to a very fast response during writing process where FETs switch ON and OFF very fast.  
         [0012]     The main disadvantage for this model was due to its advantages where the presence of strong points everywhere in the memory cell made the introduction of an external signal to any of those points a trigger for a very high dynamic current which occurs due to the low resistance—Source to Drain resistance of a FET in “On” status—between the Supply/Ground points and the Source of the introduced Input signal.  
       BRIEF SUMMARY OF INVENTION  
       [0013]     As mentioned above in the “Background art section” The barrier between the CMOS SRAM cell and integrability was the short circuit occurrence during writing process between the Supply/Ground points and the Input points.  
         [0014]     The solution I introduce here is based on the approach of omitting the Supply &amp; Ground points during the writing process.  
         [0015]     The Supply &amp; Ground points should be omitted for all the changing cells during their transient status only, so that any dynamic current occurs will be due to the charges accumulated on the parasitic capacitances of FETs, which will lead to slight heat emission where the mentioned parasitic capacitances will be in the range of fF (Femto Farad), and in case of negligible resistance in the current path, the resultant current will occur only for fSECs (Femto Seconds), which will result in a negligible heat emission.  
         [0016]     The suggested mean of temporary omission of Supply and Ground points is by coupling the Pull-up FETs of every n cell/s to supply line via 2 switch select FETs in parallel and coupling the Pull-down FETs of every n cell/s to Ground via 2 other switch select FETs in parallel, all the four switch select FETs will be called “Supply switch select FETs” and those supply switch select FETs will be normally ON when no CAS or RAS signals are introduced, while a part of those supply switch select FETs will be switched OFF during writing process so as to isolate only n memory cells from Ground and Supply points at a time.  
         [0017]     The last point to be mentioned in this section is related to the CAS &amp; RAS signals, those signals will be introduced in new forms rather than their old forms to the enable select FETs per cell for all the cells included in the writing process and to the supply switch select FETs common between every n memory Cell/s, so each of those signals will be divided into 4 different time frames, this point will be discussed later in the drawing description section.  
       BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]      FIG. 1  shows a proposed implementation for the system:  
         [0019]     The FETs  18 ,  19 ,  20 ,  21 ,  22  &amp;  23  form a CMOS SRAM cell with no additional components where  20  &amp;  21  are the pull-up FETs,  22  &amp;  23  are the pull-down FETs,  18  &amp;  19  are the Input/Output switch select FETs, FETs  24  &amp;  25  couple between the pull-up FETs  20 &amp; 21  and the memory system on chip supply line  1 , FETs  26  &amp;  27  couple between the pull-down FETs  22  &amp;  23  and the memory system on chip Ground line  2 , the coil  13  can be added so as to couple between the on chip Ground line  2  and the external Ground of the power supply  11 , and the coil  14  can be added so as to couple between the on chip supply line  1  and the external supply line of the power supply  12 , both coils are put so as to match the average effective capacitance in the current path between the external supply  12  and Ground  11  respectively from a side and the Input/Output lines  9  &amp;  10  from the other side at the operating frequency of the memory system, FETs  24 ,  25 ,  26  &amp;  27  are normally ON so that the pull-up FETs are coupled to the on chip supply line  1  and the pull-down FETs are coupled to the on chip Ground line  2  via a low resistance (Source to Drain resistance of a FET in ON status).  
         [0020]     Note 1: The on chip supply and ground lines are a part of the memory chip and should be implemented together with the memory groups and control lines within the chip while the external supply and ground lines are the feeding lines from the power supply that will either be a part of the chip or the power supply depending on the nature and position of the implemented coils.  
         [0021]     Note: The introduction of any coil to the memory system is optional because the frequency response of this memory system is already high, and may be higher than the available operating frequencies of the processing system to which this memory system is added.  
         [0022]     Note 2: The FETs  24 ,  25 ,  26  &amp;  27  are common between more than a single memory cell, because during the writing process in a memory system, logic change occurs in a whole memory word or n words at a time, where all the cells included in those n words have the same CAS &amp; RAS address lines.  
         [0023]     The aggreGate of cells included in an N words together with their Supply switch select FETs are dealt with as a single block i.e. Block  28 . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0024]     Now it is the time to speak about how the system operates according to the control signals to be introduced to each of the lines  3 ,  4 ,  5 ,  6 ,  7  &amp;  8 .  
         [0025]     For simplicity, will assume all the switch select FETs like  18 ,  19 ,  24 ,  25 ,  26  &amp;  27  are all NFETs.  
         [0026]      FIG. 2  shows the CAS/RAS positive duty cycles (During the writing process) divided into 4 time frames, and each of the signals to be applied to the 6 control lines  3 ,  4 ,  5 ,  6 ,  7  &amp;  8  is illustrated during the 4 time frames  1 ,  2 ,  3  &amp;  4 .  
         [0027]     The upper signal represents the positive duty cycle of the signal introduced to lines  3 ,  4 ,  5  &amp;  6 , the transient response is given a complete time frame so as to take into consideration any possible synchronization or delay issue between CAS &amp; RAS signals.  
         [0028]     The lower signal represents the positive duty cycle of the signal introduced to lines  7  &amp;  8 , the transient response is given a complete time frame so as to take into consideration any possible synchronization or delay issue between CAS &amp; RAS signals.  
         [0029]     Note: Those resultant signals can be obtained by multiplying the original CAS &amp; RAS signals by other new signals that can develop the resultant required signals illustrated in  FIG. 2   
         [0030]     Note 2: Practically a time frame should be calculated so that at its beginning the signals are guaranteed to be in their initial statuses, while at its end the signals are guaranteed to be in their final statuses, taking in consideration any delay or synchronization issues.  
         [0031]     Note 3: Practically the 4 time frames  1 ,  2 ,  3  &amp;  4  are not equal but here we can assume they are equal for the purpose of simplicity.  
         [0032]     Note 4: The highest values for both the upper and the lower signals are supposed to be enough to switch the FETs to which they are introduced ON, while the lowest values for both the upper and lower signals are supposed to be enough to switch the FETs to which they are introduced OFF.  
         [0033]     For simplicity, the highest logic  1  will be assumed to have a value Vcc, while the logic  0  will be assumed to have a value equals ground.  
         [0034]     1- During the first time frame ( 1 ), the Gates of the FETs  24 ,  25 ,  26  &amp;  27  are subjected to an OFF signal via lines  3 ,  4 ,  5  &amp;  6  to break the connection between the Supply/Ground points and the SRAM cells selected to change their statuses, while no change is introduced to the lines  7  or  8  yet.  
         [0035]     2- During the second time frame ( 2 ), the Gates of FETs  18  &amp;  19  are subjected to an ON signal coming from lines  7  &amp;  8 , to allow the Voltage on the lines  9  &amp;  10  to be transferred to the Gates &amp; Drains of the Pull-up &amp; Pull-down FETs, in this stage we need to study the status of the Pull-up and Pull-down FETs of a cell.  
         [0036]     Lets take the case a Vcc signal is introduced though Line  9  and a Ground Signal introduced through line  10 , in this case the NFET  22  has a Vcc on its Gate while having a Ground on its Drain, this should be enough to drive it ON and thus its Source will acquire a Ground signal too introduced from its Drain, also PFET  21  will have a Ground signal on its Gate while it has a Vcc signal on its Drain, and this also should be enough for it to be driven ON, and thus a Vcc signal will be introduced to its Source via its Drain, but NFET  23  will have a Vcc signal on its Drain while both its Gate and Source have a Ground signal, this condition is enough to keep it OFF, also the PFET  20  will have a Ground signal on its Drain while both its Gate and Source have a Vcc signal, this condition is also enough to keep it OFF, so all the Pull-up &amp; Pull-down FETs acquired their final status during the second time frame and they need to keep them after the I/P signals are not maintained, so lets go to the third time frame.  
         [0037]     3- During the third time frame ( 3 ), the lines  7  &amp;  8  maintain their statuses while the lines  3 ,  4 ,  5  &amp;  6  begin to acquire a Vcc signal to bring the supply switch FETs ON, and thus returning to their initial statuses and the memory cells are fed normally to keep the logic they carry.  
         [0038]     4- During the forth time frame ( 4 ), lines  7  &amp;  8  get back to their initial values so as to disable the Input/Output switch FETs and thus returning to static status, while the lines  3 ,  4 ,  5  &amp;  6  are already back to their original statuses and they face no change during this time frame.