Abstract:
The present invention discloses a read and match circuit for a low-voltage content addressable memory, wherein the write circuit inputs the signals needing storing into the memory cells, and the read circuit retrieves the stored signals from the memory cells, and the match circuit compares the data stored in the memory cell with the data searched by the match circuit. As the circuits for writing, reading and matching are separated from each other and exempt from mutual interference, the present invention can achieve high reliability and low power consumption under a low-voltage operation environment without using a special fabrication process. In the present invention, the circuit is optimized to meet different requirements. The present invention enables the user to determine whether to have high speed or to have low power consumption. Further, the present invention can overcome the problems of current leakage and noise allowance in a low-voltage environment.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a logic circuit, particularly to a read and match circuit for a low-voltage content addressable memory. 
         [0003]    2. Description of the Related Art 
         [0004]    A content addressable memory (CAM) not only stores data but also compares data. Therefore, a CAM cell not only has circuits for reading and writing data but also has transistors for matching data, wherein the data in the memory array is simultaneously compared with the searched data input externally. The mass parallel comparison operation has an advantage of high speed and a disadvantage of high power consumption. 
         [0005]    Refer to  FIG. 1  for the architecture of bit lines in a conventional technology. Suppose that Node n 1  is at a logic state of 1 and Node n 2  is at a logic state of 0 in the memory cell  10 , and suppose that the word line WLv is at a logic state of 1 and the bit lines BL and BLn are at a logic state of 1 in a reading activity. The partial voltage will cause a slight voltage rise in Node n 2 . Thus, the static noise margin is decreased, and the external noise is more likely to affect the stability of the stored data. Once the noise exceeds the allowance, the stored data is damaged. 
         [0006]    The influence of current leakage is another problem. Suppose that Node n 1 , Node n 2 , Node n 3 , and Node n 4  are respectively at logic states of 1, 0, 0, and 1 in the memory cell  10 , and suppose that Node n 1  and Node n 3  are at a logic state of 0 in the memory cell  12 . In a reading activity, the word line WLv is at a logic state of 1, and the bit lines BL and BLn are at a logic state of 1 and at a floating state. The current leakage in the transistor  122  of the memory cell  12  will cause a voltage decrease in the bit line BL, and an error thus occurs. 
         [0007]    Refer to  FIG. 2  for a NOR-type match-line circuit in a conventional technology. When executing a reading activity at a low voltage, the memory cell  20  also has the problems of static noise margin and bit-line current leakage. The circuit further has a problem that the match line ML is affected by leakage current. Suppose that Node n 1  is at a logic state of 1 and Node n 2  is at a logic state of 0 in the memory cell  20 , and suppose that the search line SL is at a logic state of 1 and the search line SLn is at a logic state of 0. Then, the transistors  201  and  204  are at a conduction state, and the transistors  202  and  203  are at a disconnection state. The current leakage in the transistors  202  and  203  will lower the voltage level of the match line ML, and an error thus occurs. 
         [0008]    Accordingly, the present invention proposes a read and match circuit for a low-voltage content addressable memory to overcome the abovementioned problems. 
       SUMMARY OF THE INVENTION 
       [0009]    The primary objective of the present invention is to provide a read and match circuit for a low-voltage content addressable memory, wherein the data stored in memory cells is not read directly but controls the gates of the transistors of the read circuit to realize reading activities, whereby the static noise margin of reading stored signal of the memory cells is increased, and the memory cells have higher stability. 
         [0010]    Another objective of the present invention is to provide a read and match circuit for a low-voltage content addressable memory, wherein the transistor stack technology is used to increase the threshold voltage of transistors and decrease the leakage current of the bit lines in the unread memory cells, whereby the bit lines are less likely to be affected by leakage current. 
         [0011]    Still another objective of the present invention is to provide a read and match circuit for a low-voltage content addressable memory, wherein the transistor stack technology is used to increase the threshold voltage of transistors and decrease the leakage current of the match lines in the memory cells, whereby the match lines are less likely to be affected by leakage current. 
         [0012]    A further objective of the present invention is to provide a read and match circuit for a low-voltage content addressable memory, whereby the user can determine whether to have high speed or to have low power consumption. 
         [0013]    To achieve the abovementioned objectives, the present invention proposes a read and match circuit for a low-voltage content addressable memory, which comprises a write circuit undertaking writing activities and storing data; a binary/ternary setting circuit controlling transmission of match signals; a read circuit connected with the write circuit and reading a logic signal stored in a memory cell; and a match circuit including a data match circuit, a binary/ternary transmission circuit and a match output circuit, connected with the write circuit and the binary/ternary setting circuit, and comparing the stored data with the searched data input externally. 
         [0014]    Below, the embodiments are described in detail to make easily understood the objectives, technical contents, characteristics and accomplishments of the present invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]      FIG. 1  is a diagram showing the architecture of bit lines in a conventional technology; 
           [0016]      FIG. 2  is a diagram showing a NOR-type match-line circuit in a conventional technology; 
           [0017]      FIG. 3  is a diagram showing a NAND-type ternary CAM cell and a NOR-type ternary CAM cell according to the present invention; 
           [0018]      FIG. 4  is a diagram showing the waveforms of a NAND-type ternary CAM cell in a reading activity according to the present invention; 
           [0019]      FIG. 5  is a diagram showing a read circuit of a NAND-type ternary CAM cell according to the present invention; 
           [0020]      FIG. 6  is a diagram showing the waveforms of a read circuit of a NAND-type ternary CAM cell according to the present invention; 
           [0021]      FIG. 7  is a diagram showing a data match circuit, a binary/ternary transmission circuit and a match output circuit of a NAND-type ternary CAM cell according to the present invention; 
           [0022]      FIG. 8  is a diagram showing the waveforms of a data match circuit, a binary/ternary transmission circuit and a match output circuit of a NAND-type ternary CAM cell according to the present invention; 
           [0023]      FIG. 9  is a diagram showing a data match circuit, a binary/ternary transmission circuit and a match output circuit of a NOR-type ternary CAM cell according to the present invention; 
           [0024]      FIG. 10  is a diagram showing the waveforms of a data match circuit, a binary/ternary transmission circuit and a match output circuit of a NOR-type ternary CAM cell according to the present invention; 
           [0025]      FIG. 11  is a diagram showing a binary NAND-type CAM cell according to the present invention; 
           [0026]      FIG. 12  is a diagram showing a binary NOR-type CAM cell according to the present invention; 
           [0027]      FIG. 13  is a diagram showing a first embodiment of the application of the present invention; 
           [0028]      FIG. 14  is a diagram showing a second embodiment of the application of the present invention; 
           [0029]      FIG. 15  is a diagram showing a third embodiment of the application of the present invention; 
           [0030]      FIG. 16  is a diagram showing that the NAND-type cell of the present invention is realized in a binary/ternary CAM; 
           [0031]      FIG. 17  is a diagram showing that the NOR-type cell of the present invention is realized in a binary/ternary CAM; and 
           [0032]      FIG. 18  is a diagram showing that the NAND-type cell and the NOR-type cell of the present invention are realized in a binary/ternary CAM. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0033]    In the conventional technologies, none CAM can be operated in a sub-threshold voltage. The present invention revises the original CAM circuit to realize the sub-threshold operation of CAM. At the same time, the present invention also takes into consideration of CAM size. Thus, the present invention proposes an optimized design of CAM to compromise the stability, reliability and size thereof. 
         [0034]    The present invention proposes a read and match circuit for a low-voltage content addressable memory. Refer to  FIG. 3  for a NAND-type ternary CAM cell and a NOR-type ternary CAM cell according to the present invention. The CAM cell  31  is a NAND-type ternary CAM cell and comprises a write circuit  30 , a binary/ternary setting circuit  40 , a read circuit  50 , a match circuit  60  and a match-line pre-charge circuit  70 . The write circuit  30  undertakes writing activities. In a writing activity, the write word line WWL is at a logic state of 1. If a logic value  0  is to be stored, the write bit line WBL 0  is at a logic state of 0, and the write bit line WBLn 0  is at a logic state of 1. Thus, Node n 1  is shifted to a logic state of 0, and Node n 2  is shifted to a logic state of 1. If a logic value  1  is to be stored, the write bit line WBL 0  is at a logic state of 1, and the write bit line WBLn 0  is at a logic state of 0. Thus, Node n 1  is shifted to a logic state of 1, and Node n 2  is shifted to a logic state of 0. The binary/ternary setting circuit  40  controls the transmission of match signals. If a binary data is stored, the mask write bit line WBLX 0  is at a logic state of 1, and the mask write bit line WBLXn 0  is at a logic state of 0. Thus, Node n 3  is shifted to a logic state of 1, and Node n 4  is shifted to a logic state of 0. If a ternary data is stored, the mask write bit line WBLX 0  is at a logic state of 0, and the mask write bit line WBLXn 0  is at a logic state of 1. Thus, Node n 3  is shifted to a logic state of 0, and Node n 4  is shifted to a logic state of 1. The read circuit  50  is connected with the write circuit  30  and reads the data stored in the CAM cell. The read circuit  50  enables the read bit lines to detect the signals stored in the CAM cell. One terminal of the read circuit  50  is connected with a read bit line, and another terminal of the read circuit  50  is connected to a virtual ground. The read word line and the signals stored in the CAM cell determine whether the read bit line and the virtual ground are short-circuited. In a reading activity, the read word line RWL is at a logic state of 1, and the read word line RWLn is at a logic state of 0, and the read bit line RBL 0  is at a logic state of 1 and at a floating state. If Node n 2  is at a logic state of 0, the read bit line RBL 0  is maintained at the logic state  1 . If Node n 2  is at a logic state of 1, the read bit line RBL 0  is discharged to have a logic state of 0. Separating the read circuit  50  from other circuits can exempt the stored data from the influence of the read bit lines in a reading activity. The principle of static noise margin is as well as store state. Refer to  FIG. 4  for the waveforms of the NAND-type ternary CAM cell in a reading activity. Suppose that Node n 2  stores a logic value  0 . When the read word line RWL is at a logic state of 1, the voltage level of Node n 2  will not drift but maintains at the original stability. The X in  FIG. 4  represents that the voltage rise denoted by the dotted line dose not occur in Node n 2 . When the system does not read data from the CAM cell, the read word line RWL is at a logic state of 0, and the read word line RWLn is at a logic state of 1. The read circuit  50  has two stacked transistors: one is an N-type transistor controlled by the read word lines, and the other is an N-type transistor controlled by the stored value. The stack effect will result in the rise of the threshold voltage of the N-type transistor controlled by the read word lines and thus decrease the leakage current of the read circuit of the CAM cell. Therefore, the floating-state read bit line RBL 0  is less likely to be affected by the leakage current of the unread CAM cell. Refer to  FIG. 5  for a read circuit of a NAND-type ternary CAM cell according to the present invention, and refer to  FIG. 6  for the waveforms of a read circuit of a NAND-type ternary CAM cell according to the present invention. Suppose that Node n 2  stores a logic value  1 . When the read word line RWL is at a logic state of 0, the read word line RWLn is at a logic state of 1. Then, the voltage level of Node m 1  rises slightly, and the bulk effect causes the threshold voltage (Vth) of the transistor  502  to rise. Thus, the leakage current of the transistor  502  is reduced. 
         [0035]    The match circuit  60  is connected to the write circuit  30  and compares the stored data with the data searched by the match circuit  60 . The match circuit  60  includes a data match circuit  602 , a binary/ternary transmission circuit  604  and a match output circuit  606 . The data match circuit  602  is connected with the search lines and the stored data, compares the stored data with the search lines and transfers the comparison result to the binary/ternary transmission circuit  604 . The data match circuit  602  has two transmission switches. The gates of the transistors in the transmission switches are controlled by the signals stored in the CAM cell; the sources of the transmission switches are connected with the search lines; the drains of the transmission switches are connected to each other. The node where the drains are connected to each other is the comparison result. In the binary/ternary transmission circuit  604 , one terminal thereof is connected with the result of the data match circuit  602 ; two terminals thereof are connected with the binary/ternary setting circuit  40 ; one terminal thereof is connected with the match output circuit  606 . The binary/ternary transmission circuit  604  determines whether the result of the data match circuit  602  is transmitted to the match output circuit  606 . One terminal of the match output circuit  606  is connected with the binary/ternary transmission circuit  604 , and another terminal of the match output circuit  606  is connected with the match line. The match output circuit  606  controls the conduction of the transistor connecting the CAM cell with the match line. In a matching activity, if the stored data is a binary signal, Node n 3  is at a logic state of 1, and Node n 4  is at a logic state of 0, and the search lines SL 0  and SLn 0  store the searched data. When a logic value  1  is searched for, the search line SL 0  has a logic value  1 , and the search line SLn 0  has a logic value  0 . If Node n 1  is at a logic state of 1, Node n 5  is shifted to have a logic value  1 . When the signal is transmitted to Node n 6 , Node n 6  will also have a logic value  1 . 
         [0036]    Refer to  FIG. 7  for a data match circuit, a binary/ternary transmission circuit and a match output circuit of a NAND-type ternary CAM cell according to the present invention. Refer to  FIG. 8  for the waveforms of a data match circuit, a binary/ternary transmission circuit and a match output circuit of a NAND-type ternary CAM cell according to the present invention. When the comparison result makes the match output circuit  606  turn on, it means that the bit matches the searched value. When the comparison result makes the match output circuit  606  disconnect, it means that the bit mismatches the searched value. When the stored data is a ternary signal, it means that Node n 3  has a logic value  0  and Node n 4  has a logic value  1 , and that Node n 6  has nothing to do with Node n 5 . If Node n 6  has a logic value  1 , the match output circuit  606  turns on, and it means that the bit matches the searched value. The match-line pre-charge circuit  70  is used to charge the match lines shown in  FIG. 3 . The NAND-type CAM cell and the match-line pre-charge circuit  70  can form a dynamic NAND-type match-line circuit. The NOR-type CAM cell and the match-line pre-charge circuit  70  can form a dynamic NOR-type match-line circuit. The NAND-type CAM cell, the NOR-type CAM cell, and the match-line pre-charge circuit  70  can form a dynamic NAND-NOR type or AND-NOR type match-line circuit. 
         [0037]    The CAM cell  32  in  FIG. 3  is a NOR-type ternary CAM cell. Refer to  FIG. 9  for a data match circuit, a binary/ternary transmission circuit and a match output circuit of a NOR-type ternary CAM cell according to the present invention. The NOR-type ternary CAM cell  32  comprises a write circuit  80 , a binary/ternary setting circuit  90 , a read circuit  100  and a match circuit  110 . The write circuit  80  undertakes writing activities. In a writing activity, the write word line WWL is at a logic state of 1. If a logic value  0  is to be stored, the write bit line WBL 1  is at a logic state of 0, and the write bit line WBLn 1  is at a logic state of 1. Thus, Node n 8  is shifted to a logic state of 1, and Node n 7  is shifted to a logic state of 0. If a logic value  1  is to be stored, the write bit line WBL 1  is at a logic state of 1, and the write bit line WBLn 1  is at a logic state of 0. Thus, Node n 8  is shifted to a logic state of 0, and Node n 7  is shifted to a logic state of 1. The binary/ternary setting circuit  90  controls the transmission of match signals. If a binary data is stored, the mask write bit line WBLX 1  is at a logic state of 1, and the mask write bit line WBLXn 1  is at a logic state of 0. Thus, Node n 9  is shifted to a logic state of 1, and Node n 10  is shifted to a logic state of 0. If a ternary data is stored, the mask write bit line WBLX 1  is at a logic state of 0, and the mask write bit line WBLXn 1  is at a logic state of 1. Thus, Node n 9  is shifted to a logic state of 0, and Node n 10  is shifted to a logic state of 1. The read circuit  100  is connected with the write circuit  80  and reads the data stored in the CAM cell. In a reading activity, the read word line RWL is at a logic state of 1, and the read word line RWLn is at a logic state of 0, and the read bit line RBL 1  is at a logic state of 1 and at a floating state. If Node n 8  is at a logic state of 0, the read bit line RBL 1  is maintained at the logic state  1 . If Node n 8  is at a logic state of 1, the read bit line RBL 1  is discharged to have a logic state of 0. 
         [0038]    The match circuit  110  is connected to the write circuit  80  and compares the stored data with the data searched by the match circuit  110 . The match circuit  110  includes a data match circuit  1102 , a binary/ternary transmission circuit  1104  and a match output circuit  1106 . The data match circuit  1102  is connected with the search lines (SL 1  and SLn 1 ) and the stored data, compares the stored data with the match lines and transfers the comparison result to the binary/ternary transmission circuit  1104 . The data match circuit  1102  has two transmission switches. The gates of the transistors in the transmission switches are controlled by the signals stored in the CAM cell; the sources of the transmission switches are connected with the search lines; the drains of the transmission switches are connected to each other. The node where the drains are connected to each other is the comparison result. In the binary/ternary transmission circuit  1104 , one terminal thereof is connected with the result of the data match circuit  1102 ; two terminals thereof are connected with the binary/ternary setting circuit  90 ; one terminal thereof is connected with the match output circuit  1106 . The binary/ternary transmission circuit  1104  determines whether the result of the data match circuit  1102  is transmitted to the match output circuit  1106 . One terminal of the match output circuit  1106  is connected with the binary/ternary transmission circuit  1104 , and another terminal of the match output circuit  1106  is connected with the match line. The match output circuit  1106  controls the conduction of the transistor connecting the CAM cell with the match line. In a matching activity, if the stored data is a binary signal, Node n 9  is at a logic state of 1, and Node n 10  is at a logic state of 0, and the search lines SL 1  and SLn 1  store the searched data. When a logic value  1  is searched for, the search line SL 1  has a logic value  1 , and the search line SLn 1  has a logic value  0 . If Node n 7  is at a logic state of 1, Node n 1  is shifted to have a logic value  0 . When the signal is transmitted to Node n 12 , Node n 12  will also have a logic value  0 . 
         [0039]    Refer to  FIG. 9  for a data match circuit, a binary/ternary transmission circuit and a match output circuit of a NOR-type ternary CAM cell according to the present invention. Refer to  FIG. 10  for the waveforms of a data match circuit, a binary/ternary transmission circuit and a match output circuit of a NOR-type ternary CAM cell according to the present invention. When the comparison result makes the match output circuit  1106  disconnect, it means that the bit matches the searched value. When the stored data is a binary signal, it means that Node n 3  has a logic value  1  and Node n 4  has a logic value  0 . When the comparison result makes Node n 5  have a logic value  1 , Node n 6  is shifted to a logic state of 1, and the match output circuit  1106  turns on. It means that the bit mismatches the searched value. When the stored data is a ternary signal, it means that Node n 3  has a logic value  0  and Node n 4  has a logic value  1 , and that Node n 6  has nothing to do with Node n 5 . If Node n 6  has a logic value  0 , the match output circuit  1106  disconnects, and it means that the bit matches the searched value. The stack technology is applied to the circuit shown in  FIG. 9 . When the bit matches the searched value, Node n 6  has a logic value  0 , and Node m 1  has a logic value  1 . Thus, the stack effect increases the threshold voltage (Vth) of a transistor  1107  and then decreases the leakage current of the transistor  1107 . Thereby, the match line ML is less likely to be affected by the leakage current of the transistor connected with the match line. 
         [0040]    According to the application, the size of transistors is optimized to prevent from mutual interference. According to requirement, the CAM cell may be revised into a binary CAM cell. Refer to  FIG. 11  a diagram showing a binary NAND-type CAM cell according to the present invention. The binary NAND-type CAM cell comprises a write circuit  120 , a read circuit  130  and a match circuit  140 . The match circuit  140  includes a data match circuit  1402  and a match output circuit  1404 . The reading operation and writing operation of the binary NAND-type CAM cell are similar to that of the NAND-type ternary CAM cell  31  in  FIG. 3 , but the matching operation is slightly different. The binary NAND-type CAM cell in  FIG. 11  does not have the binary/ternary setting circuit in the NAND-type ternary CAM cell  31  of  FIG. 3 . The operation of Node n 5  in  Fig. 11  is similar to Node n 5  in  FIG. 3 . When Node n 5  has a logic value  1 , the match output circuit  1404  turns on, and it means that the bit matches the searched value. When Node n 5  has a logic value  0 , the match output circuit  1404  disconnects, and it means that the bit mismatches the searched value. Refer to  FIG. 12  a diagram showing a binary NOR-type CAM cell according to the present invention. The binary NOR-type CAM cell comprises a write circuit  140 , a read circuit  160  and a match circuit  170 . The match circuit  170  includes a data match circuit  1702  and a match output circuit  1704 . The reading operation and writing operation of the binary NOR-type CAM cell are similar to that of the NOR-type ternary CAM cell  32  in  FIG. 3 , but the binary NOR-type CAM cell in  FIG. 12  does not have the binary/ternary setting circuit in the NOR-type ternary CAM cell  32  of  FIG. 3 . The operation of Node n 5  in  FIG. 12  is similar to Node n 1  in  FIG. 3 . When Node n 5  has a logic value  0 , the N-type transistor of the match output circuit  1704  disconnects, and it means that the bit matches the searched value. When Node n 5  has a logic value  1 , the N-type transistor of the match output circuit  1704  turns on, and it means that the bit mismatches the searched value. 
         [0041]    The NAND-type CAM cell can apply to the NAND-type match-line circuit and the AND-type match-line circuit. Refer to  FIG. 13  for a first embodiment of the application of the present invention. The NAND-type CAM cell  180  may be the NAND-type ternary CAM cell  31  in  FIG. 3  or the binary NAND-type CAM cell in  FIG. 11 , and the match output circuit  1802  may be the match output circuit  606  in  FIG. 7  or the match output circuit  1404  in  FIG. 11 . In a pre-charge state, the control line clk of the match-line pre-charge circuit  70  has a logic value  0 , and Node n 1  has a logic value  1 , and Node n 2  has a logic value  0 . Whether the bit matches the searched value determines whether the transistor of the match output circuit  1802  turns on or disconnects. When the bit matches the searched value, the corresponding transistor turns on. When the bit mismatches the searched value, the corresponding transistor disconnects. In an evaluate state, the control line clk has a logic value  1 . If all the bits in the match output circuit  1802  match the searched values, Node n 1  will be discharged to have a logic value  0 , and Node n 2  is shifted to a logic state of 1. If at least one of the bits in the match output circuit  1802  does not match the searched values, Nodes n 1  and n 2  are maintained at the pre-charge state. 
         [0042]    The NOR-type CAM cell can apply to the NOR-type match-line circuit. Refer to  FIG. 14  for a second embodiment of the application of the present invention. The NOR-type CAM cell  190  may be the NOR-type ternary CAM cell  32  in  FIG. 3  or the binary NOR-type CAM cell in  FIG. 12 , and the match output circuit  1902  may be the match output circuit  1106  in  FIG. 9  or the match output circuit  1704  in  FIG. 12 . In a pre-charge state, the control line clk has a logic value  0 , and Node n 1  has a logic value  1 . Whether the bit matches the searched value determines whether the transistor of the match output circuit  1902  turns on or disconnects. If the bit matches the searched value, the corresponding transistor of the match output circuit  1902  disconnects. If the bit mismatches the searched value, the corresponding transistor of the match output circuit  1902  turns on. In an evaluate state, the control line clk has a logic value  1 , and Node n 2  has a logic value  0 . If all the bits in the match output circuit  1902  match the searched values, Node n 1  is maintained at a logic state of 1. If at least one of the bits in the NOR-type CAM cell  190  does not match the searched values, Node n 1  is discharged to have a logic value  0 . 
         [0043]    The NAND-type CAM cell and the NOR-type CAM cell may also be used in an identical match line simultaneously. Refer to  FIG. 15  for a third embodiment of the application of the present invention. The NAND-type CAM cell group  200  may be the same as that shown in  FIG. 13 , and the NOR-type CAM cell group  210  may be the same as that shown in  FIG. 14 . In a pre-charge state, the control line clk has a logic value  0 ; Node n 1  has a logic value  1 ; Node n 2  has a logic value  0 ; Node n 3  has a logic value  1 ; Node n 5  has a logic value  0 . The NAND-type CAM cell group  200  and the NOR-type CAM cell group  210  simultaneously undertake bit matching activities. In an evaluate state, the control line clk has a logic value  1 . If all the bits of the NAND-type CAM cell  200  hit the searched values, Node n 2  is shifted to a logic state of 1. If the bits of the NAND-type CAM cell  200  do not all hit the searched values, Node n 2  is maintained at a logic state of 0, and Node n 5  also has a logic value  0 . When Node n 1  is shifted to a logic state of 1, Node n 4  is shifted to a logic state of 0. If all the bits of the NOR-type CAM cell  210  hit the searched values, Node n 3  is maintained at a logic state of 1, and Node n 5  also has a logic value  1 . If at least one of the bits does not hit, Node n 3  is discharged to have a logic value  0 , and Node n 5  is shifted to a logic state of 0. 
         [0044]    Refer to  FIG. 16  a diagram showing that the NAND-type cell of the present invention is realized in a binary/ternary CAM, wherein the CAM comprises NAND-type match-line circuits  220  having the architecture shown in  FIG. 13 , an address decoder  230  where control lines WWL, RWL and RWLn originate, and a write/read/search buffer  240 . When performing writing or searching, the write/read/search buffer  240  transmits external signals into the memory cells. When performing reading, the write/read/search buffer  240  transfers the data stored in the memory cells to the external circuit. The operating process thereof is similar to that mentioned above. Refer to  FIG. 17  a diagram showing that the NOR-type cell of the present invention is realized in a binary/ternary CAM, wherein the CAM comprises NOR-type match-line circuits  220  having the architecture shown in  FIG. 14 , an address decoder  260  where control lines WWL, RWL and RWLn originate, and a write/read/search buffer  270 . When performing writing or searching, the write/read/search buffer  270  transmits external signals into the memory cells. When performing reading, the write/read/search buffer  270  transfers the data stored in the memory cells to the external circuit. The operating process thereof is similar to that mentioned above. Refer to  FIG. 18  a diagram showing that the NAND-type cell and the NOR-type cell of the present invention are realized in a binary/ternary CAM, wherein the CAM comprises NAND-NOR-type match-line circuits  280  having the architecture shown in  FIG. 15 , an address decoder  290 , and a write/read/search buffer  300 . The operating process thereof is similar to that mentioned above. 
         [0045]    In conclusion, the present invention has the advantages of achieving lower power consumption in a low-voltage system and optimizing the read, write and match sub-circuits to overcome the problems of current leakage and noise allowance. 
         [0046]    The embodiments described above are only to exemplify the present invention but not to limit the scope of the present invention. Therefore, any equivalent modification or variation according to the characteristics or spirit of the present invention is to be also included within the scope of the present invention.