Abstract:
Disclosed is a squelch circuit capable of detecting whether an absolute value of input voltage is over a specific voltage difference or not. The squelch circuit according to the present invention comprises: a first differential amplifier for receiving first and second input signals, for sensing a first voltage difference between the first and second input signals and for outputting a first sensing signal when the first voltage difference is over a specific positive value; a second differential amplifier for receiving the first and second input signals, for sensing a second voltage difference between the first and second input signals and for outputting a second sensing signal when the second voltage difference is over a specific negative value; an offset current determining unit coupled to the first and second differential amplifiers for respectively controlling first and second offset currents of the first and second differential amplifiers to determine the specific positive and negative values; and an output unit for outputting a squelch signal in response to the first and second sensing signals.

Description:
FIELD OF THE INVENTION 
     The present invention relates to a squelch circuit to create a squelch waveform prescribed in the universal serial bus 2.0; and, more particularly, to a squelch circuit capable of detecting whether an absolute value of input voltage is over a specific voltage difference or not. 
     DESCRIPTION OF THE RELATED ART 
     Generally, a squelch circuit has been used to reduce noises of signals received from telecommunication equipments. For example, when a noise of input signals is over a specific value, the squelch circuit in a receiver stops receiving the signals in order that the input noise from outside is not outputted through an output terminal in the receiver and it automatically blocks the power of the receiver. Further, in other fields, the squelch circuit has been widely used in various circuits, which are required to output a signal when it is over a specific value. 
     In the universal serial bus (hereinafter, referred to as USB), the squelch circuit detects an input signal that is over a specific voltage difference and then outputs a squelch signal, the USB operates in a high-speed mode. 
     Referring to FIG. 1, a conventional squelch circuit includes a detector and an output unit  20 . The detector  10  determines whether a voltage difference between two input signals (dummy input data) Din and DinB is over a specific value. The detector  10  includes: a buffer U 1  receiving the two input signals Din and DinB and then outputting an output signal having a hysteresis characteristic; an AND gate U 3  combining the output signal from the buffer U 1  and an inverted output signal via a delay inverter U 2 ; and a diode U 4  connected in series to the AND gate U 3 . 
     The output unit  20  receiving an output signal from the diode U 4  includes a resistor R 1 , a capacitor C 1  and an output buffer U 5 . The resistor R 1  and the capacitor C 1  are provided to determine whether a voltage difference between the output signals from the output buffer U 5  and the input signal from the diode U 4  is maintained at a specific value. 
     Referring to FIG. 2, when the voltage difference between the two input signal Din and DinB is over a specific value (V 1 ), the input buffer U 1  outputs an output signal having a hysteresis characteristic. The output signal from the input buffer U 1  is inverted via the delay inverter U 2  and the output signals from both the input buffer U 1  and the delay inverter U 2  undergoes a logic multiplication in the AND gate U 3 , thereby forming one-shot-pulses with a shorten pulse width. These one-shot-pulses are continuously transferred to the output unit  20  via the diode U 4 . Accordingly, an input voltage of the output buffer U 5 , which is over a specific value, is made by these transferred pulses. If the input voltage of the output buffer U 5  is over a specific value, a squelch signal is created in a high voltage level in the output unit  20 , and if not, it is created in a low voltage level in the output unit  20 . 
     As a result, if the voltage difference between two input data is V 1 , a logic high squelch is issued and if the voltage difference between two input data is −V 1 , a logic low squelch is issued. FIG. 2 is a waveform of the typical squelch signal. 
     However, the squelch signal required in USB 2.0, which is issued when an absolute value is over a specific value, cannot be provided by the squelch circuit of FIG.  1 . 
     SUMMARY OF THE INVENTION 
     It is, therefore, an object of the present invention to provide a squelch circuit in compliance with the specifications of USB 2.0. 
     It is another object of the present invention to provide, a squelch circuit, which is not dependant on a common mode voltage of input signals and then has a wide operating range for the input signals. 
     In accordance with an aspect of the present invention, there is provided a squelch circuit comprising: a first differential amplifier for receiving first and second input signals, for sensing a first voltage difference between the first and second input signals and for outputting a first sensing signal when the first voltage difference is over a specific positive value; a second differential amplifier for receiving the first and second input signals, for sensing a second voltage difference between the first and second input signals and for outputting a second sensing signal when the second voltage difference is over a specific negative value; an offset current determining unit coupled to the first and second differential amplifiers for respectively controlling first and second offset currents of the first and second differential amplifiers to determine the specific positive and negative values; and an output unit for outputting a squelch signal in response to the first and second sensing signals. 
     In accordance with another aspect of the present invention, there is provided a squelch circuit comprising: a first differential amplifier for receiving first and second input signals, for sensing a first voltage difference between the first and second input signals and for outputting a first sensing signal when the first voltage difference is over a specific positive value; a second differential amplifier for receiving the first and second input signals, for sensing a second voltage difference between the first and second input signals and for outputting a second sensing signal when the second voltage difference is over a specific negative value; a first current path coupled to the first differential amplifier for by-passing an offset current of the first differential amplifier to determine the specific positive value in response to the first and second input signals; a second current path coupled to the second differential amplifier for by-passing an offset current of the second differential amplifier to determine the specific negative value in response to the first and second input signals; and an output unit for outputting a squelch signal in response to the first and second sensing signals. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other objects and aspects of the present invention will become apparent from the following description of the embodiments with reference to the accompanying drawings, in which: 
     FIG. 1 is a block diagram illustrating a conventional squelch circuit; 
     FIG. 2 is a waveform of a squelch signal generated in the squelch circuit of FIG. 1; 
     FIG. 3 is a block diagram illustrating a squelch circuit in accordance with an embodiment of the present invention; 
     FIG. 4A is a circuit diagram of first and second differential amplifiers and an offset current determining unit of FIG. 3; 
     FIG. 4B is a circuit diagram an output unit of FIG. 3; 
     FIG. 5 is a waveform of a squelch signal generated in accordance with the present invention; and 
     FIG. 6 is a circuit diagram of first and second differential amplifiers and an offset current determining unit of FIG. 3 in accordance with an embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Hereinafter, the present invention will be described in detail referring to the accompanying drawings. 
     Referring to FIG. 3, a squelch circuit according to the present invention includes first and second differential amplifiers  100  and  300 , an offset current determining unit  200  and an output unit  400 . The first differential amplifier  100  outputs a sensing signal when the voltage difference between input voltages Din and DinB is over a specific positive value and the second differential amplifier  300  outputs a sensing signal when the voltage difference between input voltages Din and DinB is over a specific negative value. The offset current determining unit  200  controls offset currents of the first and second differential amplifiers  100  and  300  and the output unit  400  finally outputs a squelch signal by using the output signals from the first and second differential amplifiers  100  and  300 . 
     A typical differential amplifier has an operation point where a voltage difference between differential input signals is zero (0). In the present invention, the operation point of the differential amplifier is movable by providing a bias voltage, which makes an offset current thereof so that a sensing signal from the differential amplifier is produced only when a voltage difference between the differential input signals is over a specific value. 
     On the other hand, the Early effect is achieved by changing a bias voltage applied to a gate of a MOS transistor for a current source in the typical differential amplifier; however, in the present invention, such an Early effect is achieved by the offset current determining unit  200  as shown in FIG.  3 . 
     Generally, a current of a current source in typical differential amplifiers is changed according to a common mode voltage of two differential input signals. Accordingly, the present invention determines an operation point of the first and second differential amplifiers  100  and  300 , by providing the offset current determining unit  200  with a current source which changes a current according to the common mode voltage of two differential input signals Din and DinB. 
     Referring to FIG. 4A, the first differential amplifier  100  includes a first input unit  120  receiving differential input signals Din and DinB, a first current source  130  receiving a bias voltage V bias  and making a current toward a ground voltage level, and a first load  110  between the first differential amplifier  100  and a power supply to produce a hysteresis characteristic to a squelch signal. 
     The first input unit  120  includes NMOS transistors MN 4  and MN 5 , which receive input signals Din and DinB through their gates, respectively, and sources of the NMOS transistors MN 4  and MN 5  are commonly connected to node N 1 . Drains of NMOS transistors MN 4  and MN 5  are respectively connected to node N 2  and N 3 . 
     In such a same manner, the first load  110  includes cross-coupled PMOS transistors MP 2  and MP 3  between the power supply VDD and nodes N 2  and N 3 . Further, the first load  110  includes a diode-connected PMOS transistor MP 1  between the power supply VDD and node N 2  and another diode-connected PMOS transistor MP 4  between the power supply VDD and node N 3 . 
     The first current source  130  is made up of an NMOS transistor MN 1  of which gate receive the bias voltage V bias . 
     The first differential amplifier  300  includes a second input unit  320  receiving the differential input signals Din and DinB, a second current source  330  receiving the bias voltage V bias  and making a current toward a ground voltage level, and a second load  310  between the second differential amplifier  300  and the power supply to produce a hysteresis characteristic to a squelch signal. 
     The second input unit  320  includes NMOS transistors MN 6  and MN 6 , which receive input signals Din and DinB through their gates, respectively, and sources of the NMOS transistors MN 10  and MN 11  are commonly connected to node N 5 . Drains of NMOS transistors MN 10  and MN 11  are respectively connected to node N 6  and N 7 . 
     The second load  310  includes cross-coupled PMOS transistors MP 6  and MP 7  between the power supply VDD and nodes N 6  and N 7 . Further, the second load  310  includes a diode-connected PMOS transistor MP 5  between the power supply VDD and node N 6  and another diode-connected PMOS transistor MP 8  between the power supply VDD and node N 7 . 
     The second current source  330  is also made up of an NMOS transistor MN 3  of which gate receive the bias voltage V bias . 
     The offset current determining unit  200  coupled to output terminals (N 3  and N 6 ) of the first and second differential amplifiers  100  and  300  forms current paths under the control of the differential input signals Din and DinB, including a third current source  230 . The first current path is coupled to an output terminal of the first differential amplifier  100  and the second current path is coupled to an output terminal of the second differential amplifier  300 . First and second current paths  210  and  220  are respectively provided on the first and second current paths, being controlled by the differential input signals Din and DinB. Accordingly, the offset current determining unit  200  controls the offset currents of the first and second differential amplifiers  100  and  300 . 
     The first current path  210  includes NMOS transistors MN 6  and MN 7 , which are responsive to the differential input signals DinB and Din, respectively, so that the first current path  210  selectively connects node N 3  to node N 4  in response to the differential input signals Din and DinB. Likewise, the second current path  220  includes NMOS transistors MN 8  and MN 9 , which are responsive to the differential input signals DinB and Din, respectively, so that the second current path  220  selectively connects node N 6  to node N 4  in response to the differential input signals Din and DinB. 
     The third current source  230  includes an NMOS transistor MN 2  to electrically connect node N 4  to a ground voltage level in response to a bias voltage signal V bias . The bias voltage signal V bias  is used as an enable signal for the first and second differential amplifiers  100  and  300  and the offset current determining unit  200 . 
     FIG. 4B is a configuration illustrating the output unit  400  in FIG.  3 . As shown in FIG. 4B, the output unit  400  includes an input unit  410 , an inverting unit  420  and an output unit  430 . The input unit  410  includes a NAND gate U 1 , an inverter U 4  and a NOR gate U 2 . The NAND gate U 1  receives output signals from an output terminal ( 01 ) of the first differential amplifier  100  and an output terminal ( 02 ) of the second differential amplifier  300 . The inverter U 4  inverts an output signal from the NAND gate U 1 . It should be noted that the output terminal ( 01 ) of the first differential amplifier  100  is not connected to the offset current determining unit  200  and the output terminal ( 02 ) of the second differential amplifier  300  is connected to the offset current determining unit  200 . The NOR gate U 2  receives output signals from an output terminal ( 01 B) of the first differential amplifier  100  and an output terminal ( 02 B) of the second differential amplifier  300 . 
     The inverting unit  420  is made up of a CMOS inverter having a PMOS transistor MP 9  and an NMOS transistor MN 12 . A gate of the PMOS transistor MP 9  is connected to the inverter U 4  and a gate of the NMOS transistor MN 12  is connected to the NOR gate U 2 . 
     The output unit  430  is connected to an output node N 8  of the inverting unit  420 , including a capacitor C 1  to store a specific value of electric charges and a buffer U 3  to produce a squelch signal in response to an amount of electric charges in the capacitor C 1 . Accordingly, when a voltage across the capacitor C 1  is over a specific voltage, the buffer U 3  issues the squelch signal. 
     FIG. 5 is a plot illustrating characteristics of the squelch signal according to the present invention. In FIG. 5, line A ((V 1 +V 2 )/2) denotes an operating point of the first differential amplifier  100  and it is determined by a drivability difference between the first and third current sources  130  and  230 . Line A′ ((−V 1 +(−V 2 ))/2) denotes an operation point of the second differential amplifier  300  and line A′ is determined by a drivability difference between the second and third current sources  130  and  230 . Accordingly, the more the drivability of the third current source increases, the more lines A and A′ are moved away from the center ( 0 ). 
     Referring again to FIG. 4A, since the first differential amplifier  100  has the third current source  230  for an offset current, the voltage difference required to amplify a signal is determined by the third current source  230 . As a result, the first differential amplifier  100  generates output signals  01  and  01 B only when the voltage difference between the differential input signals Din and DinB is over a specific positive value and this specific positive value is also determined by the drivability of the third current source  230 . Likewise, in the second differential amplifier  300 , output signals  02  and  02 B are generated only when the voltage difference between the differential input signals Din and DinB is over a specific negative value and this specific negative value is determined by the drivability of the third current source  230 . 
     Accordingly, it is possible to obtain the squelch signals prescribed in USB 2.0, by symmetrically coupling the first differential amplifier  100  to the second differential amplifier  300  via the third current source  200  and by achieving the same current drivability ratio between the first and second differential amplifiers  100  and  300  via the third current source  200 . That is, the squelch signals are obtained according to an absolute value of the difference between the differential input signals Din and DinB. 
     Further, if the cross-coupled PMOS transistors MP 2  and MP 3  in the first load  110  are designed to be lager than the diode-connected PMOS transistors MP 1  and MP 4 , the width (B) of the hysteresis becomes wider. 
     When the differential input signals Din and DinB are gradually rising and falling, the NMOS transistor MN 4  is turned on and the current flows from node N 2  to node N 1 . At this time, since the NMOS transistor MN 1  is turned on by the bias voltage signal V bias , the current flows to the ground voltage level Vss. Accordingly, an amount of current at node N 3  is decreased and an amount of current at node N 1  is increased so that a hysteresis characteristic does not appear in the first deferential amplifier  100 . 
     On the other hand, the voltage drops at node N 2  so that the PMOS transistor MP 3  is turned on. However, in the present invention, the diode-connected PMOS transistors MP 1  and MP 4  in the first load  110  are different from the cross coupled PMOS transistors MP 3  and MP 2  in their current drivability, that is, the drivability of the PMOS transistors MP 2  and MP 3  are higher than that of the PMOS transistors MP 1  and MP 4 . Accordingly, the current at node N 3  is the same as that at node N 2  for a predetermine time and then a sensing voltage does not appear. When the voltage continuously drops at node N 2  and the drivability of the PMOS transistor MP 3  is higher than that of the PMOS transistor MP 1 , a sensing voltage (differential voltage) appears. 
     Likewise, if the differential input signals Din and DinB are gradually falling and rising, the current decreases at node N 2  and the current at node N 3  is increased. The PMOS transistor MP 2  is turned on so that the current is provided to node N 2 . Accordingly, the current at node N 2  is the same as that at node N 3  for a predetermine time and then a sensing voltage does not appear (width of “B” in FIG.  5 ). When the differential input signal DinB is continuously rising, the current at node N 3  is more increased than that at node N 2  because the voltage drop at node N 3  is much more. Accordingly, a sensing voltage (differential voltage) appears. 
     Being different from conventional differential amplifiers for amplifying a difference between two input signals base on a constant operating current (the first current source), the first deferential amplifier  100  is characterized in that a point causing a current difference at node N 2  is different from that at node N 3  due to the diode-connected PMOS transistors MP 1  and MP 4  and the cross-coupled PMOS transistors MP 2  and MP 3 . 
     Likewise, the second load  310  in the second differential amplifier  300  has a hysteresis characteristic with a width of “B′” as shown in FIG.  5 . 
     The third current  230  in the offset current determining unit  200  is coupled to the first and second differential amplifiers  100  and  300  via first and second current paths  210  an  220 . The third current  230  flows an offset current in order to control an operation point of the first and second differential amplifiers  100  and  300 . 
     The currents which flow in the current sources  130  and  330  of the first and second differential amplifiers  100  and  300  are varied according to the voltages at nodes N 1  and N 5  due to the Eearly effect. Gates of the NMOS transistors MN 6  and MN 7  in the first current path  210  are connected to the differential input signals Din and DinB, respectively. Accordingly, when the differential input signals Din and DinB are at a common mode (namely, when two input voltages are the same), the offset current of the third current source  230  is also varied according to the voltage of the common mode so that the squelch signal is not influenced on the variation of voltage of the common mode. This means that the squelch signal of the present invention is in a wide operation range. 
     In similar to the first differential amplifiers  100 , since the second current path  220  has the same functions as the first current path  210 , it is also in a wide operation range. 
     As a result, the squelch signals, which comply with the specifications of USB 2.0, are obtained by means of the offset current of the third current source  230  and the cross-coupled PMOS transistors MP 2 , MP 3 , MP 6  and MP 7  in the first and second load  110  and  310 . 
     Referring to FIG. 4 b,  output signals  01  and  02  from the first and second differential amplifiers  100  and  300  are inputted to a NAND gate U 1  and the NAND gate U 1  outputs a high voltage signal. A PMOS transistor MP 9  is turned on by a low voltage signal from an inverter U 4 . A capacitor C 1 , which is connected in parallel to an output buffer U 3 , is provided to output the squelch signal after a voltage difference between the input signals is maintained for a predetermined time. 
     FIG. 6 is a circuit diagram of first and second differential amplifiers  100  and  300  and an offset current determining unit  200  which are implemented by PMOS current source. As shown in FIG. 6, the PMOS and NMOS transistors in FIG. 4A are replaced with NMOS and PMOS transistors, respectively. 
     As apparent from the above, the squelch circuit according to the present invention is in compliance with the specifications of USB 2.0 and has a wide operating range for the input signals because it is not dependant on a common mode voltage of input signals. 
     While the present invention has been described with respect to certain preferred embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims.