Abstract:
Memory controllers and methods of optimizing pad sequences thereof are provided. At least two different preferred trace sequences on printed circuit boards for at least one memory device are first provided. One memory controller is then provided to have a core logic circuit, a plurality of input/output (I/O) devices, and a reorderer. The core logic has I/O terminals. Each I/O device on the single chip has a pad. The reorderer is coupled between the core logic circuit and the input/output devices, programmable to selectively connect the input/output devices to the input/output terminals. The reorderer is later programmed to select and connect a portion of the input/output devices to the input/output terminals such that one of the different preferred trace sequences is substantially supported.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The invention relates to memory control, and in particular to memory controllers providing alternative pad sequences and pinout sequences. 
   2. Description of the Related Art 
   Memory is essential in most electronic applications, generally requiring not only high capacity but also high data transfer rate. One type of DRAM is DDR (Double Data Rate), providing increased bandwidth over preceding single-data-rate SDRAM (synchronous dynamic random access memory) by transferring data on both the rising and falling edges of a clock signal. 
   DDR (DDR1) is superseded by DDR2, implementing modifications to allow higher clock frequency, but operating on the same principle as DDR1. DDR2 has become a logical progression for memory standards and speeds, incorporating several new designs and specifications which play a part in increased speed. For example, DDR2 requires on-die termination (ODT) to eliminate excess signal noise while DDR1 requires only on-board termination. DDR2 and DDR1 use different external voltages (2.5 V and 1.8 V). DDR2 requires off-chip driver (OCD) impedance calibration while DDR1 does not. DDR2 uses a 4-bit prefetch while DDR1 uses a 2-bit prefetch. DDR2, using a Fine Ball Grid Array (FBGA), can be made smaller then DDR1 which uses Thin Small Outline Package (TSOP). 
   DDR2 and DDR1 are currently in a transitional stage in the field of electronic applications. Some cost-sensitive electronic applications may prefer DDR1 to DDR2, even though DDR2 is superior in performance. To support evolving requirements, the two designs and specifications are often combined in a single chip such that timely development and supply of various types of DRAMs or memory controllers can be achieved. A circuit supporting DDR1 and DDR2 on the same chip through interconnection layer switching has been introduced. Switching to accommodate different standardized on-chip designs and specifications for DDR1 and DDR2 has been implemented in the DDR1/DDR2 mixed chip. Nevertheless, satisfactory support of both DDR1 and DDR2 entails more than standardized on-chip designs and specifications. 
   BRIEF SUMMARY OF THE INVENTION 
   Embodiments of the invention provide a memory controller on a single chip. The memory controller comprises a core logic circuit, input/output (I/O) devices and a reorderer. The core logic circuit on the single chip has I/O terminals. Each I/O device has a pad. The reorderer is coupled between the input/output terminals and the input/output devices, programmable to selectively connect the input/output devices to the input/output terminals. Thus, at least two different pad sequences, each communicating with at least one memory device, are provided and supported by the single chip. 
   Embodiments of the invention provide a method of optimizing pad sequence of a memory controller. At least two different preferred trace sequences on printed circuit boards for at least one memory device are first provided. The memory controller comprises a core logic circuit, a plurality of input/output (I/O) devices, and a reorderer. The core logic circuit has I/O terminals. Each I/O device on the single chip has a pad. The reorderer is coupled between the core logic circuit and the input/output devices, programmable to selectively connect the input/output devices to the input/output terminals. The reorderer is later programmed to select and connect a portion of the input/output devices to the input/output terminals such that one of the different preferred trace sequences is substantially supported. 
   A detailed description is given in the following embodiments with reference to the accompanying drawings. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
     The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
       FIG. 1  illustrates a system with a chip having a memory controller according to embodiments of the present invention. 
       FIGS. 2A and 2B  show two pinouts respectively corresponding to DDR1 and DDR2 SDRAMs. 
       FIGS. 3A and 3B  show two different pad sequences provided by a memory controller in a single chip to support DDR1 and DDR2 SDRAMs, respectively. 
       FIG. 4  illustrates a memory controller with no reorderer between a DDR core logic and I/O devices. 
       FIGS. 5A and 5B  disclose possible implementations of a reorderer in a memory controller. 
       FIGS. 6A-6D  illustrate different preferred trace sequences on different PCBs requiring support from a memory controller on a single chip. 
       FIG. 7  shows a pad placement supporting the trace sequences in  FIGS. 6A-6D . 
       FIG. 8  illustrates relationships between trace sequences in  FIGS. 6A-6D  and an alternative pad sequence provided by a memory controller. 
       FIGS. 9 and 10  illustrate a Multi Chip Module and a stacked-die package according to embodiments of the invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
     FIG. 1  illustrates a system with a chip having a memory controller according to embodiments of the present invention. On a single chip, memory controller  100  comprises DDR core logic  102 , reorderer  104  and input/output (I/O) devices  106 . DDR logic core  102  has several I/O terminals  108 . DDR core logic  102  supports both DDR1 and DDR2. Each I/O device  106  has a pad  110 , through which memory controller  100  can be electrically connected to a printed circuit board (PCB)  120  to access data in a memory. Reorderer  104  between DDR core logic  102  and I/O devices  106  is programmable to selectively connect input/output devices  106  to input/output terminals  108 , enabling memory controller  100  to provide different pad sequences accordingly. For example, the pad sequence of memory controller  100  for controlling a DDR1 SDRAM may be different from that controlling a DDR2 SDRAM. Alternatively, the pad sequence of memory controller  100  for a PCB supporting a DDR1 SDRAM may be different from that for another PCB supporting the same DDR1 SDRAM, since layouts of the PCBs may vary. 
     FIGS. 2A and 2B  show two pinouts respectively corresponding to DDR1 and DDR2 SDRAMs. JEDEC (Joint Electron Device Engineering Council) has standardized the packages and corresponding pinouts for DDR1 and DDR2 SDRAMs. A DDR1 SDRAM is in a TSOP (Thin Small-Outline Package) with pinout shown in  FIG. 2A , while a DDR2 SDRAM is in a FBGA (Fine Ball Grid Array) with pinout shown in  FIG. 2B .  FIGS. 2A and 2B  evidence that pinout sequences for DDR1 and DDR2 SDRAMs are totally different from each other. 
     FIGS. 3A and 3B  show different pad sequences provided by memory controller  100  in a single chip to support DDR1 and DDR2 SDRAMs, respectively. It is supposed in  FIG. 3A  that a PCB supporting a DDR1 SDRAM is generally preferred to have a trace sequence of [A 0 , A 1 , A 2 , A 3 ], from top to bottom, when connected to a memory controller, in consideration of PCB shape constraints, transmitted signal quality, pinout of a mounted memory, and the like. To completely or substantially match a pad sequence to the trace sequence, reorderer  104  of memory controller  100  is programmed to connect A 0  terminal of DDR core logic  102  to the first I/O device, A 1  terminal to the second I/O device, A 2  terminal to the third I/O device, and A 3  terminal to the fourth I/O device, such that a pad sequence  202   a  of [A 0 , A 1 , A 2 , A 3 ] as shown in  FIG. 3A  is generated. Again, another PCB supporting a DDR2 SDRAM preferably comprises a trace sequence of [A 1 , A 2 , A 3 , A 0 ], from top to bottom, when connected to a memory controller. Thus, the same reorderer  104  of memory controller  100  is programmed to generate a pad sequence  202   b  of [A 1 , A 2 , A 3 , A 0 ], matching the trace sequence shown in  FIG. 3B . Performance of both DDR1 and DDR2 systems in  FIGS. 3A and 3B  is optimized since both the trace sequences of  FIGS. 3A and 3B  are preferred. 
     FIG. 4  illustrates a memory controller with no reorderer between a DDR core logic and I/O devices, wherein the pad sequence of a memory controller is unchangeable. The unchangeable pad sequence may be designed or optimized to match the trace sequence on a PCB in certain situations, but likely to mismatch a different trace sequence on another PCB. For example, pad sequence  202   c  in  FIG. 4 , [A 0 , A 1 , A 2 , A 3 ], has been optimized to perfectly match the preferable trace sequence in  FIG. 3A  for supporting a DDR1 SDRAM. When it is used to control a DDR2 SDRAM, however, as shown in  FIG. 4 , the unchangeable pad sequence of the memory controller mismatches the preferable trace sequence shown in  FIG. 3B , such that a crisscross pattern  402  inevitably occurs in the PCB, degrading the quality of signal transmitted therein or PCB routing. 
     FIGS. 5A and 5B  disclose two possible implementations of a reorderer in a memory controller. The reorderer  104   a  in  FIG. 5A  comprises multiplexers  1042  and a register set  1041  having at least one register. Register set  1041  can be set by, for example, uploading or updating firmware into the memory controller  100   a , to determine the selected port in each multiplexer  1042 . For instance, register set  1041 , under a register setting, directs multiplexers  1042  to connect terminal S 1  to I/O device I/O 1 , terminal S 3  to I/O device I/O 2 , terminal S 2  to I/O device I/O 3 , and the like. Further, a reorderer can be implemented to program by interconnection layer switching, as exemplified in  FIG. 5B . While every interconnection layer is available, a top metal layer of a memory controller chip is preferable to perform metal options because the time-to-market of the chip is the shortest. Several predetermined masks, each corresponding to one programmed reorderer, are prepared for the top metal layer. After completing semiconductor manufacturing, one of the predetermined masks connects I/O devices and terminals of a DDR core logic circuit, while another mask provides another kind of connection. For example, in a programmed reorderer  104   b  of memory controller  100   b  of  FIG. 5B , metal strips  1044  developed in a top layer by selecting and using one of the predetermined masks connect terminal S 1  to I/O device I/O 1 , terminal S 3  to I/O device I/O 2 , terminal S 2  to I/O device I/O 3 . Also shown in  FIG. 5B , a programmed reorderer  104   b  must have several open ends dangled inside the area of reorderer  104   b . Some of these open ends may disappear, being connected between I/O devices and I/O terminals, when using another determined mask for producing another programmed reorderer. 
   A DDR core logic and I/O devices may be programmed at the same time when a reorderer is programmed, to switch and accommodate different on-chip designs and specifications for DDR1 and DDR2. 
   Memory controllers in embodiments of the invention may require registration of several preferred trace sequences on PCBs. These preferred trace sequences may be predetermined by circuit designers or supplied by potential system users.  FIGS. 6A-6D  illustrate different preferred trace sequences for different PCBs requiring support from a memory controller on a single chip. 
   The trace sequence in  FIG. 6A  connects two DDR1 SDRAMs that share common control signal traces and common address traces to communicate with a memory controller, while one DDR1 SDRAM uses a group of independent data traces and the other uses the other group of independent data traces. To balance the trace lengths respectively for the two DDR1 SDRAMs, all the control traces commonly-used by the two DDR1 SDRAMs are located in the middle of the trace sequence in  FIG. 6A  and separate the two groups of independent data traces. The package type for the memory controller supporting the trace sequence in  FIG. 6A  is BGA. Likewise, the trace sequence in  FIG. 6B  connects two DDR2 SDRAMs. Similar to  FIG. 6A , the control traces commonly used by two DDR2 SDRAMs are located in the middle of the trace sequence in  FIG. 6B  and separate the two groups of independent data traces. The package type for the memory controller supporting the trace sequence in  FIG. 6B  is also BGA. As mentioned, to straighten the traces or minimize the number of crisscrosses on a PCB, the data trace sequences in  FIGS. 6A and 6B  are completely different, even though a DDR2 SDRAM has only two additional data pins over a DDR1 SDRAM. The sequence variation for the commonly-used traces can also be found in  FIGS. 6A and 6B . 
   The trace sequence in  FIG. 6C  connects one DDR1 SDRAM and that in  FIG. 6D  connects one DDR2 SDRAM. A memory controller supporting the trace sequence in  FIG. 6C  or  6 D is packaged in the form of Low Profile Quad Flat Pack (LQFP). Similar to the trace sequence difference between  FIGS. 6A and 6B ,  FIGS. 6C and 6D  differ completely in their trace sequences even though the trace count of the trace sequence in  FIG. 6D  outnumbers that of  FIG. 6C  by only three. 
   For a single chip supporting the trace sequences in  FIGS. 6A-6D , memory controller  100  as exemplified in  FIG. 1  is designed to have a pad placement as shown in  FIG. 7 . Pads numbered from 1-22 form a group of data pads and those numbered from 48-69 form another group of data pads. Furthermore, reorderer  104  in memory controller  100  might be capable of rendering alternative pad sequences for each corresponding trace sequence in  FIGS. 6A-6D .  FIG. 8  has four major columns  802   a - 802   d , each defined by a bold-lined frame and representing the relationship between a trace sequence in  FIGS. 6A-6D  and an alternative pad sequence provided by memory controller  100 . Major columns  802   a - 802   d  correspond to the trace sequences shown in  FIGS. 6A-6D , respectively. As an example, when memory controller  100  supports the PCB with a trace sequence shown in  FIG. 6A , reorderer  104  is programmed, providing memory controller  100  with a pad sequence of [DQ 3 , DQ 2 , DQ 4 , DQ 6 , . . . ] as shown by sub-column  804   a  in major column  802   a . An entry with “xxxx”, for example entry  806  of sub-column  804   a , indicates the I/O device corresponding to the 10 th  pad is not connected or selected by the programmed reorderer  104 , not acting as an I/O device for DDR core logic  102 . Other major columns  802   b - 802   d  are self-explanatory in view of the above description such that their explanation is omitted. 
   Please note that in  FIG. 8  the connection between I/O terminals for data, such as DQ 0 -DQ 15 , and pads is not reordered when a memory controller is used to support another PCB. For example, the first pad in  FIG. 8  is constantly connected to I/O terminal DQ 3 , irrespective of whether a memory controller is programmed to support which one of the trace sequences shown in  FIGS. 6A-6D . It is because that as long as a memory controller is capable of accessing the same byte in a memory, the pad sequence for the memory controller accessing that byte does not matter. For example, the first eight traces in each of  FIGS. 6A-6D  are for the same byte consisting of DQ 0 -DQ 7 , and thus the pad sequence in a memory controller for that byte can be any pad sequence consisting of DQ 0 -DQ 7 . A constant connection between data I/O terminals and corresponding pads needs no reordering. 
   Address pad sequences alone provided by a reorderor might not be reordered when applied for different PCBs if each address from the reorderor exactly mapping to only one memory location. Nevertheless, as can be found from the trace sequences in  FIG. 6A-6D , the common address traces for memories do not stand alone, but are inevitably switched with the common control signal traces while applied for another PCB. A reorderor is capable of maximizing the matching between pads and the common control signal traces in every application, for example, the address pads and the control pads for a core logic circuit are reordered in different applications shown in  FIG. 8 . 
   It can be derived from  FIG. 8  that after programming, reorderer  104  in this embodiment must be able to connect the I/O device of the 32 th  pad to I/O terminal RA 7 , RA 8 , RA 11 , and RA 6  of a DDR core logic circuit. In the other words, the reorderer in this embodiment must be able to connect I/O terminal RA 7  of a DDR core logic circuit to the I/O device of the 32 th , 39 th , 40 th , or 31 th  pad. The pad sequence difference as shown between major columns  802   a  and  802   b  or between major columns  802   c  and  802   d  also discloses that the pinout sequence of the same type of package for memory controller  100  changes based on programming of reorderer  104  in memory controller  100 . 
   Programming of reorderer  104  may take place during manufacture of the chip with the memory controller or after packaging. For example, if interconnection layer switching is employed, reorderer  104  is first programmed by selecting and using a mask among alternatives and the chip with reorderer  104  is then packaged. If register setting is employed, the chip with reorderer  104  may be first manufactured and packaged, and then programmed by uploading firmware into memory controller  100  through package pins. Programming by register setting is preferred because of its relatively shorter time-to-market. The packaging may be multiple chip module packaging or stack-die packaging. 
   The embodiments of the invention provide alternative pad sequences for a memory controller on a single chip and alternative pinout sequences for a package with the memory controller. The signal paths between a memory controller and a DDR1 or DDR2 memory can be optimized to have minimum trace crisscross on a PCB, such that the quality of the signal transmitted therein is guaranteed. 
   Even though the invention is embodied utilizing memory controllers for controlling DDR1 and DDR2 memories, it is not limited thereto. DDR3 memories or more advanced DDR memories can be candidates for a memory controller according to the invention to control. Furthermore, a memory controller according to the invention may control other kinds of memory, such as SRAMs, flash memories, etc. 
   The invention is also applicable to a single chip in a Multi Chip Module (MCM).  FIG. 9  illustrates an exemplified MCM, having a package socket  94  with conductive fingers  96  and packaging a single chip  90  and a neighboring memory chip  92 . As shown in  FIG. 9 , both single chip  90  and memory chip  92  have several pads connected to some of the conductive fingers  96  of a socket  94  by bonding wires  98  while single chip  90  is also internally connected to memory chip  92  by internal wires  97 . In order to support a different memory chip having a preferred pad sequence different from that of memory chip  92 , single chip  90  is designed with the ability of being programmed to provide another pad sequence for those pads purposely connected to a memory chip. Single chip  90  may have a memory controller with a core logic circuit, a reorderer and input/output (I/O) devices as disclosed in  FIG. 1 . In other words, single chip  90  can be programmed to provide at least two different pad sequences for those pads connected by internal wires  97 . 
     FIG. 10  illustrates a stacked-die package, in which memory chip  92  stacks over single chip  90  inside a package socket  94  with conductive fingers  96 . Single chip  90  has pads bonded to either fingers or pads of memory chip  92 , or to both. If memory chip  92  is replaced with another memory chip having a different preferred pad sequence, it is preferred that single chip  90  has the ability to provide a corresponding pad sequence and reduces any possible bonding wire crisscrosses occurring above the area between the pads of memory chip  92  and the pads of single chip  90 . Accordingly, single chip  90  of  FIG. 10  in an embodiment of the invention may have a core logic circuit, a reorderer and input/output (I/O) devices of  FIG. 1 , being programmable of providing at least two different pad sequences for those pads connected to memory chip  92 . 
   While the invention has been described by way of examples and in terms of preferred embodiment, it is to be understood that the invention is not limited to thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Thus, the scope of the appended claims should be accorded the broadest interpretation to encompass all such modifications and similar arrangements.