Abstract:
Control methods and controller thereof for a power supply including a power switch and an inductor. The power switch is turned on to increase the inductor current through the inductor, which is sensed to generate a current-sense signal. The current-sense signal is added up with an adjusting signal to generate a summation signal. The power switch is turned off if the summation signal is higher than a peak limit. The turn-on time of the power switch is detected to update the adjusting signal.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention is related to an over current protection (OCP) method for use in a switched-mode power supply (SMPS) and related device. 
     2. Description of the Prior Art 
     A power supply is a power management device which supplies power to electronic devices or elements after performing power conversion.  FIG. 1  is a diagram of a prior art flyback power supply  60 . A bridge rectifier  62  is configured to rectify an alternative-current (AC) voltage V AC  and provide an input voltage V IN  to an inverter  64 . When a switch  72  is short-circuited, energy may be stored in the primary coil L P  of the inverter  64 ; when the switch  72  is open-circuited, energy stored in the secondary coil L S  of the inverter  64  may be discharged to a load capacitor  69  via a rectifier  66 , thereby establishing an output voltage V OUT . An error amplifier EA is configured to compare the output voltage V OUT  with a target voltage V Target , thereby generating a compensation signal V COM . According to the compensation signal V COM  and a current-sense signal V CS , a controller  74  is configured to generate a control signal V GATE  for operating the switch  72 . The current-sense signal V CS  is associated with the inductor current flowing through the primary coil L P . 
       FIG. 2  is a detailed diagram illustrating the controller  74  in  FIG. 1 . A clock generator  76  controls a logic unit  79  so as to turn on the switch  72  periodically. Comparators  77  and  78  are configured to limit the maximum value of the current-sense signal V CS  to a value which is the smaller one among a peak limit V CS     —     LIMIT  and the compensation signal V COM . Over current protection may be performed by the comparator  78  and the logic unit  79  so that the current-sense signal V CS  does not exceed the peak limit V CS     —     LIMIT . 
     However, after the comparator  78  detects that the current-sense signal V CS  exceeds the peak limit V CS     —     LIMIT , there is a signal delay time before the switch  72  is actually turned off. Since the current-sense signal V CS  continues to increase during the signal delay time, the current-sense signal V CS  often exceeds the peak limit V CS     —     LIMIT  by an amount ΔV which varies with the input voltage V IN . In the prior art power supply  60 , the maximum power of the output voltage V OUT  may vary with the input voltage V IN , which is an undesirable condition to be overcome. 
     SUMMARY OF THE INVENTION 
     The present invention provides a control method applied in a power supply having a switch and an inductor coupled in series. The method includes turning on the switch for increasing an inductor current of the inductor; detecting the inductor current for generating a current-sense signal; generating a summation signal by adding the current-sense signal to an adjusting signal; comparing the summation signal with a peak limit and turning off the switch when the summation signal exceeds the peak limit; and detecting a turn-on time or a duty cycle of the switch for updating the adjusting signal accordingly. 
     The present invention further provides a controller for use in a power supply having a switch and an inductor coupled in series. The controller includes a logic processing unit used to turn on the switch; a comparator used to turn off the switch when a voltage at a sensing node exceeds a peak limit; and a current generator used to generate and adjust an adjusting current which flows to an end of the switch via the detecting end according to a turn-on time or a duty cycle of the switch; wherein the adjusting current is adjusted to lower when the turn-on time or the duty cycle increases and remains constant during the turn-on time or the duty cycle. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram of a prior art flyback power supply. 
         FIG. 2  is a detailed diagram illustrating a controller in  FIG. 1 . 
         FIG. 3  is a diagram of a power supply according to the present invention. 
         FIG. 4  is a detailed diagram illustrating a controller in  FIG. 3 . 
         FIG. 5  is a diagram illustrating the operation of the power supply according to the present invention. 
         FIG. 6  is a detailed diagram illustrating a current generator in  FIG. 4 . 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 3  is a diagram of a power supply  90  according to the present invention.  FIG. 4  is a detailed diagram illustrating a controller  80  in  FIG. 3 . For explanation purposes, components, devices or signals with equivalent or similar functionalities are represented by the same symbols in  FIGS. 1-4 . However, the embodiment illustrated in  FIGS. 3 and 4  may adopt components, devices or signals other than those labeled by the same symbols in  FIGS. 1 and 2 . It is to be noted that the present invention is not limited thereto. 
     Different from  FIG. 1 , an adjusting resistor FCS is further disposed between a sensing node (SS in  FIG. 4 ) of the controller  80  and a detecting resistor CS in  FIG. 3 . Different from  FIG. 2 , the controller  80  in  FIG. 4  further includes a current generator  82  for providing an adjusting current I CS     —     OUT  which flows through the adjusting resistor FCS and the detecting resistor CS via the sensing node SS. The controller  80  in  FIG. 4  may be implemented using an integrated circuit which is connected to the adjusting resistor FCS via its pin. 
     Based on the control signal V GATE , the current generator  82  is configured to detect the turn-on time T ON  or the duty cycle D of the switch  72 , thereby updating the adjusting current I CS     —     OUT  The duty cycle D is the turn-on time T ON  divided by one switch period. When the switch  72  is turned on, the value of the adjusting current I CS     —     OUT  remains substantially constant. The current generator  82  provides a feedback scheme in which the adjusting current I CS     —     OUT  is altered once in a switch period so that the turn-on time T ON  or the duty cycle D is substantially inversely proportional to the adjusting current I CS     —     OUT . For example, if the turn-on time T ON  or the duty cycle D of the switch  72  increase in the current switch period, the adjusting current I CS     —     OUT  for the next switch period may be lowered. 
     Equivalently speaking, updating the adjusting current I CS     —     OUT  means updating the current limit I CS     —     LIMIT  of the inductor current I P  which flows through the primary coil L P . Referring to  FIGS. 3 and 4 , the comparator  78  is triggered when the voltage at the sensing node SS is equal to the peak limit V CS     —     LIMIT , as depicted by the following equation (1):
 
 V   CS     —     LIMIT   =V   FCS   +V   CS   (1)
 
     The adjusting signal V FCS  is the voltage established across the adjusting resistor FCS and the current-sense signal V CS  is the voltage established across the detecting resistor CS. The voltage at the sensing node SS is equal to the sum of the adjusting signal V FCS  and the current-sense signal V CS . Assuming the resistance R FCS  of the adjusting resistor FCS is much larger than the resistance R CS  of the detecting resistor CS, equation (1) may be summarized as follows:
 
 V   CS     —     LIMIT   =I   CS     —     OUT   *R   FCS   +I   CS     —     LIMIT   *R   CS )
 
 I   CS     —     LIMIT =( V   CS     —     LIMIT   −I   CS     —     OUT   *R   FCS )/ R   CS   (2)
 
     Assume that the relation between the adjusting current I CS     —     OUT  and the turn-on time T ON  is as follows:
 
 I   CS     —     OUT   *T   ON   =K   (3)
 
     wherein K is a constant. 
     Equation (2) may be summarized as follows:
 
 I   CS     —     LIMIT =( V   CS     —     LIMIT   /R   CS )− K*R   FCS /( R   CS   *T   ON )  (4)
 
     In Equation (4), K*R FCS /(R CS *T ON ) may be viewed as a deduction amount for reducing the original current limit (V CS     —     LIMIT /R CS ) corresponding to the peak limit V CS     —     LIMIT , thereby limiting the inductor current I P  in advance. In  FIG. 5 , curve C LIMIT  illustrates the relationship between the current limit I CS     —     LIMIT  and the turn-on time T ON  in equation (4), and S 1 ˜S 2  illustrate the values of the inductor current I P  under different input voltage V IN . Assuming that curve S 1  corresponds to a larger input voltage V IN  and curve S 2  corresponds to a smaller input voltage V IN , then T ON1 &lt;T ON2  and I P1 &lt;I P2 . As depicted in  FIG. 5 , the maximum value of the inductor current I P  may be maintained at the original current limit (V CS     —     LIMIT /R CS ) instead of varying with the input voltage V IN  by selecting the appropriate R FCS . The issues caused by signal delay may thus be solved. Meanwhile, the duty cycle D may be used in place of the turn-on time in the above-mentioned equations and embodiments of the present invention. 
       FIG. 6  is a detailed diagram illustrating the current generator  82  in  FIG. 4 . A constant current source  86  is configured to provide a constant current I SET  for charging the capacitor  89 . A constant current source  88  is configured to provide a constant current I EXP  for discharging the capacitor  89  when the control signal V GATE  is logic “1” (the switch  72  is turned on). When the switch  72  is turned on, the control signal V GATE , which determines the current I CTL  and I EXP , substantially remains constant. A current mirror  84  is configured to proportionize the adjusting current I CS     —     OUT  and the current I CTL , as follows:
 
 I   SET   *T   CYCLE   =I   EXP   *T   ON   (5)
 
     T CYCLE  is the switch cycle of the switch  72 . For example, if (I SET *T CYCLE ) is larger than (I EXP *T ON ) after a switch cycle, the control voltage V CTL , raises so as to increase the current I CTL  and the constant current I EXP . The feedback path from the control voltage V CTL  to the constant current I EXP  equalizes both sides of equation (5). The relationship between the adjusting current I CS     —     OUT  and the turn-on time T ON  may be derived from equation (5), as follows
 
 I   CS     —     OUT   =K 1 *I   CTL   =K 2 *I   EXP   =K 3 *I   SET   *T   CYCLE /TON  (6)
 
     When the duty cycle D is introduced, Equation (6) may be represented as follows:
 
 I   CS     —     OUT   =K 3 *I   SET   /D   (7)
 
     I SET  and T CYCLE  are constant. The adjusting current I CS     —     OUT  is inversely proportional to the turn-on time T ON  or the duty cycle D. 
     The adjusting current I CS     —     OUT  only needs to be provided during OCP when the power supply is heavily loaded. Therefore, a transconductance comparator GM may be used as a control unit which decides whether the adjusting current I CS     —     OUT  needs to be generated by detecting the compensation signal V COM . In  FIG. 6 , when the compensation signal V COM  is lower than a predetermined value V REF , it is determined that the power supply is lightly loaded or not loaded at all. The adjusting current I CS     —     OUT  becomes 0 and the current limit I CS     —     LIMIT  is no longer influenced by the turn-on time T ON  or the duty cycle D. 
     In the embodiment illustrated in  FIG. 4 , the inductor current I P  may be limited in advance for overcoming issues caused by signal delay time. System manufacturers may select an appropriate external adjusting resistor FCS for achieving a certain design. 
     Although a flyback SMPS is used for illustration, the present invention may also be applied to other types of SMPS, such as buck converters or boost converters. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.