Abstract:
Structures and methods for high speed signaling over single sided/ended current sense amplifiers are provided. The present invention introduces hysteresis within a pseudo-differential current sense amplifier and provides it with adjustable thresholds for the detection of valid signals coupled with the rejection of small noise current transients or reflections and ringing when using low impedance interconnections and/or current signaling. The circuit provides a fast response time in a low power CMOS environment, and conserves circuit design space by allowing for single sided/ended sensing. 
     A first embodiment includes a current sense amplifier having a first amplifier and a second amplifier which are electrically coupled. Each amplifier includes a first transistor of a first conductivity type and a second transistor of a second conductivity type, where the first and second transistors are coupled at a drain region. A single signal input node is coupled to a source region of the first transistor of the first amplifier and receives a signal input current. A first signal output node is coupled to the drain region of the first and the second transistors in the second amplifier. The first signal output node is further coupled to a gate of a third transistor. A second signal output node is coupled to the drain region of the first and the second transistor in the first amplifier, and is further coupled to a gate of a fourth transistor. In one embodiment, a current mirror is coupled to the signal input node and the source regions of the first transistors in the first and the second amplifiers.

Description:
RELATED APPLICATIONS 
     This application is related to co-pending application Ser. No. 09/255,077, filed on Feb. 2, 1999, entitled “Pseudo-Differential Amplifiers” by inventor Leonard Forbes, which is hereby incorporated by reference. Further, this application is related to co-pending application Ser. No. 09/300,099, filed on Apr. 27, 1999, entitled “Current Sense Amplifier and Current Comparator with Hysteresis,” by inventors Leonard Forbes and Eugene H. Cloud, which application is also incorporated herein by reference. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates generally to integrated circuits. More particularly, it pertains to structures and methods for pseudo-differential current sense amplifiers and current comparators with hysteresis. 
     BACKGROUND OF THE INVENTION 
     The use of voltage sense amplifiers with hysteresis for noise rejection is known. The simplest voltage sense amplifier is an operational amplifier in a positive feedback configuration. In the case of voltage hysteresis two different trip points (Tph and Tpl) are defined and circuits are designed such that when a high signal is to be recognized it must exhibit a voltage higher than Tph before it is recognized and declared a high signal. In a similar manner, before a low signal is recognized it must exhibit a low voltage lower than the second trip point Tpl. A simple illustration of this is provided in FIGS. 1A,  1 B and  1 C. 
     Presently, most CMOS integrated circuit interconnections rely on the transmission of a voltage step or signal from one location to another. The driver may simply be a CMOS inverter or NMOS transistor with a passive pull up load resistor and the receiver a simple CMOS amplifier, differential amplifier or comparator. The CMOS receiver presents a high impedance termination or load to the interconnection line. This fact is problematic for several identifiable reasons. For example, the high impedance termination is troublesome because the switching time response or signal delay is determined mainly by the ability of the driver to charge up the capacitance of the line and the load capacitance. Also, the interconnection line is not terminated by its characteristic impedance resulting in reflections and ringing, and large noise voltages may be induced on the signal transmission line due to capacitive coupling and large voltage switching on adjacent lines. The result is that the noise voltage can be a large fraction of the signal voltage. 
     The transmission of voltage step signals works well if the interconnection transmission line is short so that the stray capacitance of the line is small. However, in longer low impedance transmission lines, such as those which exist on most CMOS integrated circuits, the noise voltage presents a difficult problem. These longer low impedance transmission lines are in fact more amenable to current signaling. These longer transmission lines may be on the CMOS integrated circuit itself, an interconnection line between integrated circuits mounted in a module as for instance a memory module, an interposer upon which these integrated circuits are mounted, or on a printed circuit board upon which the integrated circuits are mounted. 
     In the quest for higher speed signaling it has recently been proposed to use current mode interconnections rather than voltage mode. The goal is to provide impedance matching on signal interconnection lines to reduce or avoid reflections and ringing on the lines. The technique proposed is matching termination of the signal line(s) to the signal receiver by using current mode interconnections and current mode sense amplifiers or current mode comparators. Signal interconnection and clock distribution lines with low controlled impedances are most amenable to current mode signaling. Metal lines separated from metal ground planes or metal power supply distribution planes (which are at AC ground) by oxide or other integrated circuit insulators will have low characteristic impedances of the order 50 or 75 ohms. To avoid reflections and ringing these need to be terminated in their characteristic impedance which requires sense amplifiers or receivers with low input impedances and implies small voltage swings on the lines. 
     Independent of whether voltage signals or current-mode signals are employed two different types of interconnections exist, the first type includes single sided/single ended interconnections and the second type includes differential interconnections. Differential interconnections are often desirable in that they reduce common mode noise. However, differential interconnections require two interconnection transmission lines and, in I/O applications, they require twice as many input/output pads and packaging pins which is a problem in some applications. The requirement of two interconnection transmission lines creates twice as much crowding on the precious chip surface area available in certain CMOS applications. Single sided/single ended pseudo differential interconnections have some of the advantages of differential interconnections, like power supply noise rejection. Single sided/single ended pseudo differential interconnections use a single transmission line interconnection. 
     In the “quasi-differential” amplifier, a single transmission line interconnection is utilized and one input of the voltage sense amplifier driven with a reference potential. The “quasi-differential” technique, and with voltage sensing on a terminated line has been used in 400 Mbs CMOS systems. FIG. 2 provides a schematic for a conventional “pseudo-differential” amplifier. In the “pseudo-differential” amplifier technique one side of the different type of voltage sense amplifier is driven with a combination of ground potential and a reference potential. Unfortunately, achieving high data rates is difficult with single-ended or unbalanced signal transmission lines at high frequencies because a large amount of noise is generated in the interconnection system including crosstalk and radiation in backplanes, connectors and cables. 
     FIG. 3 provides an illustration of the conventional differential current sense amplifier. This conventional current sense amplifier, receiving fully differential input signals, can respond more rapidly than those single ended/single sided amplifiers mentioned above. Also, the fully differential sense amplifier has lower power constraints and can be driven with a small 0.5 mA input signal on the input transmission lines. However, the conventional differential current sense amplifier is not very responsive to single sided or single ended input signals where one side, or input, is driven with a reference current signal, e.g. zero Amperes and the other input is used in an attempt to detect a current signal. When used in such a manner the response of the current sense amplifier with a single sided input is very poor. There is simply not enough gain and feedback in the positive feedback latch to result in a large output signal for a 1 milliampere (mA) input signal. Instead a larger 5 mA input signal is required which places greater power demands on the overall CMOS circuit. 
     For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, it is desirable to develop sense amplifiers which are even less susceptible to induced noise, current reflections or ringing. It is further desirable to develop low power sense amplifiers which provide rapid response times using single sided/ended inputs. 
     SUMMARY OF THE INVENTION 
     The above mentioned problems for high speed signaling over single sided/ended current sense amplifiers as well as other problems are addressed by the present invention and will be understood by reading and studying the following specification. The present invention introduces hysteresis within a pseudo-differential current sense amplifier and provides it with adjustable thresholds for the detection of valid signals coupled with the rejection of small noise current transients or reflections and ringing when using low impedance interconnections and/or current signaling. 
     In particular, an illustrative embodiment of the present invention includes a novel pseudo-differential current sense amplifier circuit with hysteresis. The circuit provides a fast response time in a low power CMOS environment. A first embodiment includes a current sense amplifier having a first amplifier and a second amplifier which are electrically coupled. Each amplifier includes a first transistor of a first conductivity type and a second transistor of a second conductivity type, where the first and second transistors are coupled at a drain region. A single signal input node is coupled to a source region of the first transistor of the first amplifier and receives a signal input current. A first signal output node is coupled to the drain region of the first and the second transistor in the second amplifier. The first signal output node is further coupled to a gate of a third transistor. A second signal output node is coupled to the drain region of the first and the second transistor in the first amplifier, and is further coupled to a gate of a fourth transistor. In one embodiment, a current mirror is coupled to the signal input node and the source regions of the first transistors in the first and the second amplifiers. 
     Integrated circuits, electrical systems, methods of operation and methods of forming the novel current sense amplifier are similarly included. The novel pseudo differential current sense amplifier circuit facilitates the introduction of hysteresis which provides the added ability to differentiate true signals from noise transients, and conserves circuit design space by allowing for single sided/ended sensing. 
     These and other method embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1A,  1 B and  1 C provide a representation of high and low trip points for a conventional voltage sense amplifier with hysteresis. 
     FIG. 2 provides a schematic for a conventional “pseudo-differential” amplifier. 
     FIG. 3 is an illustration of a conventional differential current sense amplifier. 
     FIG. 4 is a schematic diagram which illustrates a novel pseudo-differential amplifier circuit according to the teachings provided in co-pending application Ser. No. 09/255,077. 
     FIG. 5A is a schematic illustration of another conventional differential current sense amplifier similar to that shown in FIG. 4 but having only a single output node. 
     FIG. 5B is a graphical representation of the current versus voltage (I-V) curve of the conventional current sense amplifier shown in FIG.  5 A. 
     FIG. 5C is another graphical representation of the current versus voltage (I-V) curve of the conventional current sense amplifier shown in FIG. 5A, when current is fed to its second signal input node. 
     FIG. 6A is a schematic illustration of a current sense amplifier or current comparator according to the teachings co-pending application Ser. No. 09/300,099. 
     FIG. 6B is an I-V graph illustrating one embodiment of the operation of the current sense amplifier shown in FIG. 6A, according to the teachings copending application Ser. No. 09/300,099. 
     FIG. 7A is a schematic illustration of a current sense amplifier or current comparator according to the teachings of the present invention which provides for pseudo-differential current sensing capabilities with the added capability of introducing hysteresis into the circuit. 
     FIG. 7B is an I-V graph illustrating one embodiment of the operation of the novel pseudo-differential current sense amplifier shown in FIG. 7A, according to the teachings of the present invention. 
     FIG. 8 is a block diagram illustrating an electronic system or integrated circuit according to the teachings of the present invention. 
    
    
     DETAILED DESCRIPTION 
     In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, a specific embodiment in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. The embodiment is described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled. 
     FIG. 4 is a schematic diagram which illustrates a novel pseudo-differential amplifier circuit according to the teachings provided in co-pending application Ser. No. 09/255,077, by inventor Leonard Forbes, which is hereby incorporated by reference. FIG. 4 illustrates a pair of cross coupled amplifiers, A 1  and A 2 . In the embodiment shown in FIG. 4, the pair of cross coupled amplifiers, A 1  and A 2 , comprise two cross coupled inverters. Each amplifier, A 1  and A 2 , includes a first transistor, Q 1  and Q 2  respectively, of a first conductivity type. Each first transistor Q 1  and Q 2  includes a source region,  407 A and  407 B respectively. Each first transistor Q 1  and Q 2  includes a drain region,  408 A and  408 B. Also, each first transistor Q 1  and Q 2  includes a gate,  409 A and  409 B, opposing a body region  410 A and  410 B. Each amplifier, A 1  and A 2 , includes a second transistor Q 3  and Q 4  of a second conductivity type. Each second transistor Q 3  and Q 4  includes a source region,  414 A and  414 B respectively. Each second transistor Q 3  and Q 4  includes a drain region,  416 A and  416 B. Also, each second transistor Q 3  and Q 4  includes a gate,  418 A and  418 B, opposing a body region  420 A and  420 B. In one embodiment, each first transistor, Q 1  and Q 2 , of a first conductivity type includes a metal oxide semiconductor field effect transistor (MOSFET). In one embodiment, each first transistor, Q 1  and Q 2 , of a first conductivity type includes an n-channel metal-oxide semiconductor (NMOS) transistor. In one embodiment, each second transistor, Q 3  and Q 4 , of a second conductivity type includes a metal oxide semiconductor field effect transistor (MOSFET). In one embodiment, each second transistor, Q 3  and Q 4 , of a second conductivity type includes a p-channel metal-oxide semiconductor (PMOS) transistor. In an exemplary embodiment, the NMOS and PMOS transistors are fabricated according to a complementary metal oxide semiconductor (CMOS) process technology. 
     In FIG. 4, a single signal input node  422  is coupled to the source region,  407 A or  407 B for one of the first transistors, Q 1  and Q 2 , in the pair of cross coupled amplifiers A 1  and A 2 . By way of illustration, and not by way of limitation, FIG. 4 shows the single signal input node  422  coupled to the source region  407 A of transistor Q 1 . A signal output node  424 A and  424 B in each inverter A 1  and A 2  is coupled to the drain regions  408 A and  408 B of the first transistors Q 1  and Q 2  as well as to the drain regions  416 A and  416 B of each second transistor Q 3  and Q 4 . The signal output nodes  424 A and  424 B in each one of the cross coupled inverters A 1  and A 2  is further coupled to the gates of the first and the second transistors in the other inverter. Hence, signal output node  424 A is coupled to gates  409 B and  418 B of inverter A 2 , and signal output node  424 B is coupled to gates  409 A and  418 A of inverter A 1 . In one embodiment, the signal output nodes  424 A and  424 B are coupled respectively to a pair of output transmission lines  454 A and  454 B. The single signal input node  422  is additionally coupled to a current mirror M 1 . In one embodiment, a transmission line  452  which has a characteristic impedance (Zo) of less than 50 Ohms is coupled to the signal input node  422 . 
     In FIG. 4, a third transistor, Q 5  and Q 6  respectively, of a first conductivity type is coupled to each amplifier, A 1  and A 2 . Each third transistor Q 5  and Q 6  includes a source region,  444 A and  444 B respectively. Each third transistor Q 5  and Q 6  includes a drain region,  446 A and  446 B. Also, each third transistor Q 5  and Q 6  includes a gate,  448 A and  448 B, opposing a body region  450 A and  450 B. The drain region  446 A and  446 B for each third transistor, Q 5  and Q 6 , is coupled to the source region,  407 A and  407 B, for each first transistor Q 1  and Q 2  in the pair of cross coupled amplifiers A 1  and A 2 . The single signal input node  422  additionally couples to the gate,  448 A and  448 B, for each third transistor Q 5  and Q 6 . In one embodiment, each third transistor, Q 5  and Q 6 , of a first conductivity type comprise a second pair of MOSFETs of a first conductivity type for the novel pseudo differential amplifier circuit  400 . In this embodiment, the second pair of MOSFETs of a first conductivity type includes a pair of NMOS transistors Q 5  and Q 6 . Also in this embodiment, the pair of NMOS transistors Q 5  and Q 6  are part of the current mirror M 1 . Here, a drain region,  446 A and  446 B, for each one of the pair of NMOS transistors Q 5  and Q 6  in the current mirror M 1  is coupled to a source region,  407 A and  407 B respectively, for each NMOS transistor Q 1  and Q 2  in the pair of cross coupled inverters A 1  and A 2 . The single signal input node  422  is coupled to a gate on each one of the pair of NMOS transistors Q 5  and Q 6  in the current mirror M 1 . 
     FIG. 3 has been provided in illustration of a conventional differential current sense amplifier. In operation, the conventional differential current sense amplifier employs two input signal lines, I 1  and I 2  for fully differential signaling. In the illustration of FIG. 3, a signal current injected at node  5  causes the source current of transistor T 1  to decrease. Likewise, a signal current being extracted from node  6  causes the source current of transistor T 2  to increase. The ratio of the currents being injected into the source of T 1  and the drain of T 5  is determined by the input impedances looking into these terminals. Again, the problem has been stated that in certain circuit applications the requirement of two input signal lines I 1  and I 2  can quickly exhaust available chip surface area. 
     In contrast, the novel pseudo-differential amplifier circuit according to the teachings provided in co-pending application Ser. No. 09/255,077 eliminates this special problem by facilitating differential sensing capability using a single ended receiver. The manner in which the same can be achieved is explained using FIG.  4 . In FIG. 4, the two independent transistors, T 5  and T 6 , shown at the bottom of FIG. 3 for the conventional differential current sense amplifier, have been replaced by current mirror M 1 . The current mirror M 1  in FIG. 4 converts a single ended input current received at the single signal input node  422  into a differential input signal. In example, output nodes  424 A and  424 B are precharged to a voltage potential prior to the sensing operation. Next, a current signal is input from input transmission line  452  into single signal input node  422 . When the current signal arrives at single signal input node  422  a portion of the signal flows into the gates  448 A and  448 B for transistors Q 5  and Q 6  serving to turn “on” these transistors. This creates conduction between source region  444 A and drain region  446 A of transistor Q 5  as well as between source region  444 B and drain region  446 B of transistor Q 6 . If the input current signal flows into the drain region  446 A of transistor Q 5  then some current will also flow into the source region  407 A of transistor Q 1 . The current flowing into the source region  407 A of transistor Q 1  will decrease the current flowing out of the drain region  416 A of transistor Q 3  and out of the source region  407 A of transistor Q 1 . The precharged voltage potential, or node voltage V 1 , at output node  424 A will subsequently increase which serves to turn transistor Q 2  on and turn off transistor Q 4 . At the same time, an increase in the conduction between source region  444 A and drain region  446 A in transistor Q 5  will cause the potential, or node voltage V 3 , at the signal input node  422  to increase which in turn increases the voltage on gate  448 B of transistor Q 6 . An increasing gate voltage on transistor Q 6  will further turn on transistor Q 6  such that transistor Q 6  conducts more current through transistor Q 6  between drain region  446 B and source region  444 B. This increase in conduction through transistor Q 6  will tend to cause the current flowing out of the source region  407 B of transistor Q 2  to increase. The increased conduction through transistors Q 2  and Q 6  tend to pull signal output node  424 B to ground reducing the node voltage V 2  at signal output node  424 B. As the node voltage V 2  of signal output node  424 B is reduced, transistor Q 3  is further turned on. In this manner, the single ended receiver, or pseudo differential amplifier circuit  400  operates in a differential amplifier fashion. The single ended current signal which was input from transmission line  452  into signal input  422  is thus converted into a differential current signal in that the source current at source region  407 A of transistor Q 1  tends to decrease and the source current at source region  407 B of transistor Q 2  tends to increase. In result, the novel pseudo-differential amplifier circuit according to the teachings provided in co-pending application Ser. No. 09/255,077 produces the same effect that a fully differential signal would have on a conventional differential current sense amplifier as that shown in FIG.  3 . Meanwhile, the novel pseudo-differential amplifier circuit according to the teachings provided in co-pending application Ser. No. 09/255,077 circumvents the necessity of having two transmission lines as in a conventional differential current sense amplifier. The novel pseudo-differential amplifier circuit  400  according to the teachings provided in co-pending application Ser. No. 09/255,077 can latch a voltage output signal on the pair of signal output nodes,  424 A and  424 B, and thus the pair of output transmission lines  454 A and  454 B when a single sided current signal of 2.0 mA or less is received at the single signal input node  422 . The novel pseudo-differential amplifier circuit  400  according to the teachings provided in co-pending application Ser. No. 09/255,077 can latch this voltage output signal to the pair of signal output nodes,  424 A and  424 B in less than 300 nanoseconds (ns). This is a very rapid response time on par with that provided by conventional differential current sense amplifiers. Further, the novel pseudo-differential amplifier circuit according to the teachings provided in co-pending application Ser. No. 09/255,077 is fully capable of fabrication in a streamlined CMOS process. However, novel pseudo-differential amplifier circuit according to the teachings provided in co-pending application Ser. No. 09/255,077 does not provide a means for introducing hysteresis into the circuit  400 . 
     FIG. 5A is a schematic illustration of another conventional differential current sense amplifier  500  similar to that shown in FIG. 4 but having only a single output node. In FIG. 5A, the conventional current sense amplifier  500  is shown driven with a single ended or single sided input, I 1 . The other differential input, I 2 , is held at zero amperes. The output voltage (V 2 ) is given by −Zv(I 1 -I 2 ), where Zv is the transimpedance (Gain) for the conventional current sense amplifier  500 . This transimpedance, Zv, is very high until the output voltage, V 2 , clamps at either a high level or a low level. In operation, the conventional current sense amplifier  500  wants to be symmetrically balanced. A current, I 1 , injected into node  5  will see a high impedance looking into transistor T 5  and a lower impedance looking into transistor T 1 . Therefore, the injected current, I 1 , flows mostly into transistor T 1 . This will subtract, or reduce, the amount of current flowing down the left hand side of the conventional current sense amplifier  500  through transistor T 3 . In result, the potential at node  1  increases which places a higher potential on the gate of T 4 . As the gate potential of transistor T 4  increases, transistors T 2  and T 6  operate to pull the output voltage, V 2 , down toward ground. FIG. 5B is a graphical representation of the current versus voltage (I-V) curve of the conventional current sense amplifier  500  shown in FIG.  5 A. 
     FIG. 5C is another graphical representation of the current versus voltage (I-V) curve of the conventional current sense amplifier  500  shown in FIG.  5 A. In this embodiment, the conventional current sense amplifier is driven with two inputs, or a differential signal, where I 2 =−250 microAmperes (μA). Here, the output voltage, V 2 , changes states when I 1 =−250 μA, so that (I 1 -I 2 ) first becomes positive and −Zv(I 1 -I 2 ) goes to the most negative value. 
     FIG. 6A is a schematic illustration of a current sense amplifier  600 , or current comparator  600 , according to the teachings of co-pending application Ser. No. 09/300,099. As shown in FIG. 6A, the current sense amplifier  600  includes a first amplifier  610 , or left side  610 , and a second amplifier  620 , or right side  620 . Each amplifier,  610  and  620 , includes a first transistor of a first conductivity type, M 1  and M 2  respectively. Each amplifier,  610  and  620 , includes a second transistor of a second conductivity type, M 3  and M 4  respectively. In one embodiment, the first transistor of a first conductivity type, M 1  and M 2 , includes an n-channel metal oxide semiconductor (NMOS) transistor, M 1  and M 2 . In this embodiment, the second transistor of a second conductivity type, M 3  and M 4 , includes a p-channel metal oxide semiconductor (PMOS) transistor, M 3  and M 4 . Transistors M 1  and M 2  are driven by a gate potential at node  7 . Each amplifier,  610  and  620 , includes a current sink, shown in FIG. 6A as transistors M 5  and M 6  which are driven by a gate potential at node  6 . The first and second transistors, M 1  and M 3 , of the first amplifier  610  are coupled at a drain region,  621  and  622  respectively, to node  1 . 
     Node  1  couples the drain region,  621  and  622 , for the first and the second transistor, M 1  and M 3 , in the first amplifier  610  to gates,  640  and  641 , of the second transistor, M 3  and M 4 , in the first and the second amplifier  610  and  620 . The first and second transistors, M 2  and M 4 , of the second amplifier  620  are coupled at a drain region,  623  and  624  respectively. In the embodiment shown in FIG. 6A, a signal output node  2  is coupled to the drain region,  623  and  624 , of the first and the second transistor, M 2  and M 4 , in the second amplifier  620 . In an alternative embodiment, the signal output node  2  can be coupled to the drain region,  621  and  622 , of the first and the second transistor, M 1  and M 3 , in the first amplifier  610 . As shown in FIG. 6A the signal output node is further coupled to a gate  630  of a third transistor M 7 . In one embodiment, the third transistor M 7  is a p-channel metal oxide semiconductor (PMOS). Each amplifier,  610  and  620 , includes a signal input node,  5  and  4  respectively, which is coupled to a source region,  625  and  626 , of the first transistor, M 1  and M 2 . 
     A source region,  627  and  628 , for the second transistor, M 3  and M 4  respectively, in the first and second amplifier,  610  and  620 , is coupled to a voltage supply Vdd at node  3 . In one embodiment, a source region  631  of the third transistor M 7  is coupled to a source region  627  of the second transistor M 3  in the first amplifier  610 . In this embodiment, a drain region  632  of the third transistor M 7  is coupled to the signal input node  5  of the first amplifier  610 . In one embodiment, the signal input node  5  of the first amplifier  610  receives an input current, I 1 , and the signal input node  4  of the second amplifier  620  receives a reference current, I 2 . 
     FIG. 6B is an I-V graph illustrating one embodiment of the operation of the current sense amplifier  600 , shown in FIG. 6A, according to the teachings of co-pending application Ser. No. 09/300,099. The operation of the novel current sense amplifier circuit  600  is explained by reference to FIGS. 6A and 6B. The third transistor M 7  introduces a controlled hysteresis into the current sense amplifier  600  of FIG.  6 A. Beginning at the right hand side of the graph, FIG. 6B illustrates the output voltage, V 2 , at a low state, or first state, output voltage. The low, or first state, output voltage, V 2 , turns on third transistor M 7  which then drives a current, IM 7 , into node  5 , the signal input node  5  for the first amplifier  610 . In other words, the third transistor M 7  provides an input current, IM 7 , into node  5 . A single ended input current, I 1 , injected into input signal node  5  is supplement by the input current, IM 7 . In order for the current sense amplifier  600  to switch the state of output voltage, V 2 , the current injected into the signal input node  5  must upset, or “trip” the balance of the current sense amplifier  600 . In this embodiment, the signal input node  4  is held at a differential/reference signal, I 2 , of zero amperes. At this point, the output voltage, V 2 , of the current sense amplifier  400  is given by V 2 =−Zv((I 1 +IM 7 )− 12 ). Here, the value of ((I 1 +IM 7 )−I 2 ) must become negative for the output voltage, V 2 , to go to a second state, or high state. 
     Because of the supplemented current, IM 7 , being driven by the third transistor M 7 , the input current I 1  will not “trip” the state of the current sense amplifier  600  until I 1  passes below a certain negative current value, i.e. a low trip point, shown at  660  in FIG.  6 B. As one of ordinary skill in the art will understand upon reading this disclosure, the size and doping levels of the third transistor M 7  can be varied to provide a set magnitude of input current, IM 7 , into node  4 . In this manner, the circuit design of the current sense amplifier  600 , shown in FIG. 6A, according to the teachings of co-pending application Ser. No. 09/300,099 can be manipulated to introduce a range of hysteresis for negative or low values of input current I 1  into the current sense amplifier  600 . The set hysteresis introduced, by the addition of the third transistor M 7 , allows the current sense amplifier  600 , shown in FIG. 6A, according to the teachings of co-pending application Ser. No. 09/300,099 to discriminate against small transient noise values which would otherwise cause the current sense amplifier to switch states prematurely and provide an inaccurate output voltage, V 2 . 
     In reverse operation, the single ended input current, I 1 , is increased from a lower value, e.g. below trip point value  650 . As shown in FIG. 6B, while the input current, I 1 , is below trip point  650  the output voltage, V 2 , will be at a high state, or second state, output voltage. In this high, second state, the voltage potential applied to gate  630  of the third transistor M 7  will not turn “on” transistor M 7 . Thus, the third transistor M 7  is effectively removed from the current sense amplifier circuit  600 . In the embodiment of FIGS. 6A and 6B, node  4  will see a reference current, I 2 , here held at zero amperes. With the third transistor M 7  turned “off,” the third transistor M 7  is not providing any input current, IM 7 , into node  5 . As explained above, the single ended input current, I 1 , must upset the balance of the current sense amplifier  600  in the opposite direction in order for the current sense amplifier  600  to switch states again, e.g. the input current, I 1 , must overcome the differential signal, I 2 , of zero amperes. At this point, the output voltage, V 2 , of the current sense amplifier  600  is given by V 2 =−Zv(I 1 -I 2 ) since the third transistor M 7  is removed from the current sense amplifier circuit  600 . However, the current sense amplifier  600 , shown in FIG. 6A, according to the teachings of co-pending application Ser. No. 09/300,099 does not provide single sided/ended sensing capabilities. 
     FIG. 7A is a schematic illustration of a current sense amplifier  700 , or current comparator  700 , according to the teachings of the present invention which provides for pseudo-differential current sensing capabilities with the added capability of introducing hysteresis into the circuit  700 . 
     As shown in FIG. 7A, the novel pseudo-differential current sense amplifier  700  includes a first amplifier  710 , or left side  710 , and a second amplifier  720 , or right side  720 . Each amplifier,  710  and  720 , includes a first transistor of a first conductivity type, M 1  and M 2  respectively. Each first transistor M 1  and M 2  includes a source region,  725  and  726  respectively. Each first transistor M 1  and M 2  includes a drain region,  721  and  723 . Also, each first transistor M 1  and M 2  includes a gate opposing a body region. Each amplifier,  710  and  720 , includes a second transistor of a second conductivity type, M 3  and M 4  respectively. Each second transistor M 3  and M 4  includes a source region,  727  and  728  respectively. Each second transistor M 3  and M 4  includes a drain region,  722  and  724 . Also, each second transistor M 3  and M 4  includes a gate,  740  and  741 , opposing a body region. In one embodiment, the first transistor of a first conductivity type, M 1  and M 2 , includes an n-channel metal oxide semiconductor (NMOS) transistor, M 1  and M 2 . In this embodiment, the second transistor of a second conductivity type, M 3  and M 4 , includes a p-channel metal oxide semiconductor (PMOS) transistor, M 3  and M 4 . Transistors M 1  and M 2  are driven by a gate potential at node  7 . The first and second transistors, M 1  and M 3 , of the first amplifier  710  are coupled at drain regions,  721  and  722  respectively, to node  1 . 
     Node  1  further couples the drain regions,  721  and  722 , for the first and the second transistor, M 1  and M 3 , in the first amplifier  710  to gates,  740  and  741 , of the second transistor, M 3  and M 4 , in the first and the second amplifier  710  and  720 . The first and second transistors, M 2  and M 4 , of the second amplifier  720  are coupled at a drain region,  723  and  724  respectively. 
     In FIG. 7A, a first signal output node  2  is coupled to the drain region,  723  and  724 , of the first and the second transistor, M 2  and M 4 , in the second amplifier  720 . The first signal output node  2  couples to an output transmission line  760 . As shown in FIG. 7A the first signal output node  2  is further coupled to a gate  730  of a third transistor M 7 . A source region,  727  and  728 , for the second transistor, M 3  and M 4  respectively, in the first and second amplifier,  710  and  720 , is coupled to a voltage supply Vdd at node  3 . 
     As shown in FIG. 7A, a single input transmission line  770  is coupled to a single signal input node  5  in the first amplifier  710 . In one embodiment, the single input transmission line  770  has a characteristic impedance (Zo) of less than 50 Ohms. As shown in FIG. 7A, the signal input node  5  of the first amplifier  710  receives an input current, I 1 . The single signal input node  5  is coupled to the source region  725  for the first transistor, M 1 , in the first amplifier  710 . In one embodiment, the source region  731  of the third transistor M 7  is coupled to a source region  727  of the second transistor M 3  in the first amplifier  710 . In this embodiment, a drain region  732  of the third transistor M 7  is coupled to the signal input node  5  on the first amplifier  710 , thereby providing a first feedback from the first signal output node  2  of the current sense amplifier (M 7 ) to a signal input node  5 , wherein providing a first feedback from a first signal output node  5  to the signal input node  2  introduces a hysteresis into the current sense amplifier in order to discriminate against noise transients. In one embodiment, the third transistor M 7  is an p-channel metal oxide semiconductor (PMOS). 
     Node  1  further serves as a second output node  1 . Node  1  is coupled to a fourth transistor M 8 . Transistor M 8  includes a source region  737 , a drain region  736 , and a gate  780  opposing a body region. As shown in FIG. 7A, node  1  couples to the drain region  736  and the gate  780  of transistor M 8 . In the embodiment, shown in FIG. 7A, the source region  737  of transistor M 8  is coupled to ground, thereby providing a path from the second signal output node  1  of the current sense amplifier M 8  to ground, wherein providing a path from the second signal output node  1  to ground introduces a hysteresis into the current sense amplifier in order to discriminate against noise transients. In one embodiment, the fourth transistor M 8  includes an n-channel metal oxide semiconductor (NMOS). 
     As shown in FIG. 7A, the single signal input node  5  is additionally coupled to a current mirror Z 1 . Current mirror Z 1  includes a fifth transistor M 5  and a sixth transistor M 6 . The fifth and sixth transistors, M 5  and M 6 , include a source region,  766  and  767  respectively. The fifth and sixth transistors, MS and M 6 , include a drain region,  768  and  769  respectively. The fifth and sixth transistors, MS and M 6 , each have a gate,  771  and  772  respectively. As shown in FIG. 7A, the gates,  771  and  772 , of the fifth and sixth transistors are coupled to one another. The source regions,  766  and  767 , of the fifth and sixth transistors, M 5  and M 6 , are coupled to ground. The drain regions,  768  and  769 , of the fifth and sixth transistors, M 5  and M 6 , are coupled to the source regions,  725  and  726  respectively, in the first transistors, M 1  and M 2 , in the first and second amplifiers,  710  and  720 . As shown in FIG. 7A, the single signal input node  5  is coupled to the gates,  771  and  772 , of the fifth and sixth transistors, M 5  and M 6 . 
     FIG. 7B is an I-V graph illustrating one embodiment of the operation of the novel pseudo-differential current sense amplifier  700 , shown in FIG. 7A, according to the teachings of the present invention. The operation of the novel pseudo-differential current sense amplifier circuit  700  is best explained in reference to FIGS. 7A and 7B and FIG.  3 . FIG. 3 has been provided in illustration of a conventional differential current sense amplifier. In operation, the conventional differential current sense amplifier employs two input signal lines, I 1  and I 2  for fully differential signaling. In the illustration of FIG. 3, a signal current injected at node  5  causes the source current of transistor T 1  to decrease. Likewise, a signal current being extracted from node  6  causes the source current of transistor T 2  to increase. Thus the differential effect of the conventional current sense amplifier is shown. The ratio of the currents being injected into the source of T 1  and the drain of T 5  is determined by the input impedances looking into these terminals. Again, the problem has been stated that in certain circuit applications the requirement of two input signal lines I 1  and I 2  can quickly exhaust available chip surface area. 
     In contrast, the novel pseudo-differential current sense amplifier circuit  700  according to the teachings of the present invention eliminates this special problem by facilitating differential sensing capability using a single ended receiver. The manner in which the same can be achieved is explained using FIG.  7 A. In FIG. 7A, the two independent transistors, T 5  and T 6 , shown at the bottom of FIG. 3 for the conventional differential current sense amplifier, have been replaced by current mirror Z 1 . The current mirror Z 1  in FIG. 7A converts a single ended input current received at the single signal input node  5  into a differential input signal. In example, transistors M 1  and M 2  are driven with a gate potential from node  7  prior to the sensing operation. Next, a current signal I 1  is injected from the single signal input transmission line  770  into single signal input node  5 . When the current signal arrives at single signal input node  5  a portion of the signal flows into the gates  771  and  772  for transistors M 5  and M 6  serving to turn “on” these transistors. This creates conduction between source region  766  and drain region  768  of transistor M 5  as well as between source region  767  and drain region  769  of transistor M 6 . If the input current signal flows into the drain region  768  of transistor M 5  then some current will also flow into the source region  725  of transistor M 1 . 
     The current flowing into the source region  725  of transistor M 1  will decrease the current flowing out of the drain region  722  of transistor M 3  and out of the source region  725  of transistor M 1 . The node voltage V 1 , at the second output node  1  will subsequently increase which acts to turn “off” transistor M 4 . At the same time, an increase in the conduction between source region  766  and drain region  768  in transistor M 5  will cause the potential, or node voltage V 5 , at the signal input node  5  to increase which in turn increases the voltage on gate  772  of transistor M 6 . An increasing gate voltage on transistor M 6  will further turn on transistor M 6  such that transistor M 6  conducts more current through transistor M 6  between drain region  769  and source region  767 . This increase in conduction through transistor Q 6  will tend to cause the current flowing out of the source region  767  of transistor M 2  to increase. The increased conduction through transistors M 2  and M 6  tends to pull second signal output node  2  to ground reducing the node voltage V 2  at signal output node  2 . In this manner, the single ended receiver, or pseudo differential amplifier circuit  400  operates in a differential amplifier fashion. The single ended current signal which was input from transmission line  770  into signal input  5  is thus converted into a differential current signal in that the source current at source region  725  of transistor M 1  tends to decrease and the source current at source region  726  of transistor M 2  tends to increase. 
     However, in this whole process the third transistor M 7  and the fourth transistor M 8  introduce a controlled hysteresis into the novel pseudo-differential current sense amplifier  700  of FIG.  7 A. The fourth transistor M 8  serves to retard the increase of a node voltage V 1  at the second signal output node  1 . In other words, M 8  is providing a current path from a second signal output node  1 , of the current sense amplifier to ground, wherein providing a path from a second signal output node  1 , to ground introduces a hysteresis into the current sense amplifier in order to discriminate against noise transients. The graph of FIG. 7B is used to illustrate this effect. Beginning on the left hand side of the graph in FIG. 7B, the first signal output node  2  is in a high output potential state, shown in FIG. 7B as state  1 . At the same time the second signal output node  1  is in a low output potential state. The third transistor M 7 , a PMOS transistor is “off” and essentially removed from the novel pseudo-differential current sense amplifier circuit  700 . With the third transistor M 7  turned “off,” the third transistor M 7  is not providing any input current, IM 7 , into node  5 . 
     In order for the novel pseudo-differential current sense amplifier circuit  700  to switch the state of an output voltage signal V 2  at the first signal output node  2 , the current signal, I 1 , injected into the signal input node  5  must upset, or “trip” the balance of the circuit  700 . As an increasing input current signal I 1  is injected at node  5 , the node voltage V 1  of the second signal output node  1  is increasing with current flowing into the source region  725  of the first transistor M 1  of the first amplifier  710 . The increasing node voltage V 1  serves to turn “on” the fourth transistor M 8 , increasing the conduction between the drain region  736  and the source region  737  of the fourth transistor M 8 . This action draws current away from node  1  thus retarding the node voltage V 1  increase at node  1 . This reduced node voltage V 1  at node  1  means a larger amount of signal current must be injected into node  5  before the node voltage V 1  can shut “off” transistor M 4  and the circuit  700  can switch states at the first signal output node  2 . Thus the addition of transistor M 8  sets a high voltage threshold trip point (Tph)  750  in the novel pseudo differential current sense amplifier circuit  700  for switching from the high output potential, state  1 , at first signal output node  1 , to a low output potential, state  2 . This distinguishes a true “trip” signal from noise transients in the circuit  700 . 
     As shown on the right hand side of graph  7 B, the node voltage V 2  at the first signal output node  2  is now in a low output potential state, state  2 . The second signal output node  1  is in a high potential state. As explained above, the single ended signal input current I 1  must upset the balance of the circuit  700  in the opposite direction in order for the circuit  700  to switch states again. In other word, the signal input current must pass a low voltage threshold “trip” point (Tpl). Now that the node voltage V 2  at the first signal output node  1  is in a low output potential state, state  2 , the third transistor is activated into circuit  700 . The low node voltage V 2  at the first signal output node  2  is coupled to the gate  730  of transistor M 7 , turning transistor M 7  “on.” Turning “on” transistor M 7  drives a current, IM 7 , into the signal input node  5 . Thus, M 7  is providing a first feedback from a first signal output node  2 , of the current sense amplifier to a signal input node  5 , wherein providing a first feedback from the first signal output to the signal input node introduces a hysteresis into the current sense amplifier in order to discriminate against noise transients. In other words, the third transistor M 7  provides an input current, IM 7 , into node  5 . A single ended input current, I 1 , injected into input signal node  5  is thus supplemented by the input current IM 7 . Since the current injected into input signal node  5  is supplemented by input current IM 7 , the injected current I 1  must drop to some lower value for the node voltage, V 2 , to return to the high output potential, state  1 . In other words, because of the supplemented current, IM 7 , being driven by the third transistor M 7 , a signal input current I 1  will not “trip” the state of the circuit  700  until I 1  passes below a certain low current value, i.e. a low voltage threshold trip point (Tpl)  790  as shown in FIG.  7 B. 
     Thus the addition of transistor M 7  sets a low voltage threshold trip point (Tpl)  790  in the novel pseudo differential current sense amplifier circuit  700  for switching node voltage V 2  from the low output potential, state  2 , at first signal output node  1 , to a high output potential, state  1 . This again distinguishes a true “trip” signal from noise transients in the circuit  700 . As one of ordinary skill in the art will understand upon reading this disclosure, the size and doping levels of the third transistor M 7  and fourth transistor M 8  can be varied to set desired high and low trip points, Tph and Tpl. For example, the size and doping level of the third transistor M 7  can be varied to provide a set magnitude of input current, IM 7 , into node  5 . In this manner, the circuit design of circuit  700  can be manipulated to introduce a range of hysteresis for high and low values of single ended signal input currents I 1  injected into circuit  700 . 
     FIG. 8 is a block diagram illustrating an electronic system or integrated circuit according to the teachings of the present invention. As shown in FIG. 8, the electronic system includes a memory  810  and a processor  820  coupled to the memory by a system bus  830 . In one embodiment, the processor and memory are located on a single semiconductor chip. The memory  810  includes a novel pseudo-differential current sense amplifier circuit according to the teachings of the present invention and as explained and described in detailed in connection with FIGS. 7A and 7B. 
     CONCLUSION 
     Thus, novel structures and methods for improving high speed signaling on and between integrated circuits while improving power requirements has been described. The set hysteresis introduced, by the addition of the third transistor M 7  and fourth transistor M 8  allows the novel pseudo-differential current sense amplifier circuit to discriminate against small transient noise values which would otherwise cause the circuit  700  to switch states prematurely and provide an inaccurate output node voltage, V 2 . The introduction of hysteresis into the pseudo-differential current sense amplifier will allow them to discriminate against noise transients since the output will not change states unless the signal input current I 1  is increased above a high trip point, Tph, or is reduced below a low trip point, Tpl. 
     Additionally, the current mirror configuration in the novel pseudo-differential current sense amplifier lowers power constraints and reduces the cost of manufacturing by reducing the amount of hardware required to achieve reliable single-ended signaling. The novel pseudo-differential current sense amplifier circuit produces the same effect that a fully differential signal would have on a conventional differential current sense amplifier as that shown in FIG.  3 . Meanwhile, the novel circuit circumvents the necessity having two input transmission lines as in a conventional differential current sense amplifier. The novel pseudo-differential current sense amplifier circuit  700  can latch a voltage output signal on the first signal output node  2  when a single sided current signal of 2.0 mA or less is received at the single signal input node  5 . The circuit  700  can latch this voltage output signal to the first signal output node  2  in less than 300 nanoseconds (ns). This is a very rapid response time on par with that provided by conventional differential current sense amplifiers. Further, the novel circuit according to the teachings of the present invention is fully capable of fabrication in a streamlined CMOS process. 
     Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. It is to be understood that the above description is intended to be illustrative, and not restrictive. Combinations of the above embodiments, and other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention includes any other applications in which the above structures and fabrication methods are used. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.