Abstract:
A power-on-reset circuit (POR) for integrated circuits that detects the minimum power levels needed to operate the most critical circuit(s) reliably. The circuit is implemented in a customized POR built into a custom IC, and emulates the critical circuit transistors in the custom IC using mimicking counterparts which are similarly affected by changes in temperature and process variations as the main circuit components. The mimicking counterparts may have smaller dimensions, to draw less current but still emulate the characteristics of the main working circuit components. Each critical sub-circuit of the main circuit may have a mimicking POR, and the multiple PORs may have their outputs combined by logic so that subtle failure modes can be modeled in the POR. The POR allows operation of the main circuit to continue at the lowest possible voltage levels while reducing the risk of unexpected results or undetected non-catastrophic failures. The POR also implements safety margins for the operation of the main circuit and tracks process sensitivity.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to low power electronic measuring instruments and, more particularly, to a power-on reset (POR) circuit which may be customized based on critical circuit counterparts in an integrated circuit (IC). The invention may be of particular utility in low voltage, low power custom IC&#39;s, such as may be used in portable measuring instruments, or the like. However, the invention is not limited to such applications. 
       BACKGROUND OF THE INVENTION 
       [0002]    Various portable electronic measuring instruments are currently available for which low power utilization is an important design consideration. One example of such a device is a displacement measuring instrument, such as a hand-held electronic caliper that can be used for making precise geometric measurements, such as that shown in U.S. Pat. Nos. 5,901,458, and 5,886,519, each of which is commonly assigned and hereby incorporated by reference in its entirety. The &#39;519 patent discloses an inductive absolute position transducer for high accuracy applications, such as linear or rotary encoders, electronic calipers and the like. Such devices may utilize low power circuits, such as those shown in U.S. Pat. Nos. 6,859,762 and 6,747,500, each of which is commonly assigned and hereby incorporated by reference in its entirety. It is obvious that the less power such instruments use, the fewer batteries (or other power sources) they will require and the longer they will operate before the batteries (or other power sources) need to be replaced or replenished. However, reducing the power requirements of such devices is a complex task. Such devices are required to make highly accurate measurements, and the signal processing techniques that have been developed for such are required to both accomplish the desired accuracy and operate at low voltage and power levels, and be relatively insensitive to reasonable variations in supply voltage and operating temperature. 
         [0003]    When such devices are operated at low power levels, one type of circuit that may be utilized to monitor the power to make sure it is above a minimum threshold is a power-on reset (POR) circuit, such as those disclosed in U.S. Pat. Nos. 7,161,396 and 7,015,744. As described in the &#39;396 patent, most integrated circuit devices include a power-on reset circuit that asserts a reset signal when a supply voltage is detected and then de-asserts the reset signal when the supply voltage has reached an acceptable level that is sufficient for the device&#39;s normal operation. The power-on reset circuit can also be used to assert the reset signal when the supply voltage falls below an acceptable level. When asserted, the reset signal is typically used to reset the device&#39;s internal logic to a known state. When de-asserted, the reset signal is typically used to terminate the reset operation and allow the device to commence normal operation. 
         [0004]    Many power-on reset circuits include both a voltage based circuit and a time-delay based circuit. The voltage based circuit is intended to reset the circuit when the supply voltage is too low, by generating a reliable reset signal when a slow rising power on is encountered. It also prevents the circuit from entering an undefined state if the voltage drops, by resetting it when the supply voltage goes below a minimum threshold. In contrast, the time-delay based circuit provides a reset pulse in the case of a fast rising power on. The two outputs from the voltage-based and time-delay based circuits are combined to provide an overall reset signal. 
         [0005]    For certain applications, different implementations of the voltage-based and time-delay based circuits may be utilized. For example, in the case of discrete systems, a fixed threshold voltage implementation may be preferred for the voltage-based circuit, in that each integrated circuit of the discrete system will typically have a specified minimum operating voltage, and the reset signal can be set according to the specified minimum operating voltages. However, one drawback of this solution is that the specified minimum operating voltage may in some cases be inaccurate, in that the actual minimum operating voltage (i.e. when the supply voltage VDD is above the threshold for reliable circuit operation), will vary with process and temperature. In such cases, if the fixed threshold voltage for triggering the reset signal is set at an incorrect level, then power inefficiencies or circuit failure may result. 
         [0006]    The present invention is directed to a customizable power-on reset circuit that determines the minimum power levels needed to reliably operate critical circuits of an integrated circuit, such as may be included in low voltage low power devices. 
       SUMMARY OF THE INVENTION 
       [0007]    This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This summary is not intended to identify key features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. 
         [0008]    A power-on-reset circuit (POR) for integrated circuits is provided. In accordance with one aspect of the invention, the power-on reset circuit detects the minimum power levels needed to operate the most critical sub-circuit(s) reliably. The power-on reset circuit is implemented in a custom integrated circuit, and emulates the critical circuit transistors in the main circuit using mimicking counterparts which are similarly affected by changes in temperature and process variations as the main circuit components. The mimicking counterparts may have smaller dimensions, to draw less current but still emulate the characteristics of the main working circuit components. Each critical sub-circuit of the main circuit may have a corresponding mimicking power-on reset circuit, and the multiple mimicking power-on reset circuits may have their outputs combined by logic so that subtle failure modes can be modeled in the power-on reset circuit. The power-on reset circuit allows operation of the main circuit to continue at the lowest possible voltage levels while reducing the risk of unexpected results or undetected non-catastrophic failures. The power-on reset circuit also implements safety margins for the operation of the main circuit, and tracks process sensitivity. 
         [0009]    In accordance with another aspect of the invention, the power-on-reset circuit includes one or more mimicking transistor elements which are designed to have a current density that approximates the current density of corresponding critical sub-circuit transistor elements from the main circuit. The power-on reset circuit also includes a margin voltage drop portion (e.g. formed by one or more resistors). The mimicking transistors provide mimicking voltage drops that approximate the voltage drops across each of the corresponding critical sub-circuit transistor elements. The margin drop portion provides a margin voltage drop which provides a safety margin for the operation of the main working circuit. The total mimicking plus margin voltage drop approximates the total sub-circuit operating voltage drop plus the margin voltage drop during the operation of the integrated circuit. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same become better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein: 
           [0011]      FIG. 1  is a block diagram of a generic prior art circuit which performs critical operations and which may be modeled by a power-on reset circuit in accordance with the present invention; 
           [0012]      FIG. 2  is a schematic diagram of a power-on reset circuit which models a critical circuit with a single NMOS transistor; 
           [0013]      FIG. 3  is a timing diagram illustrating certain aspects of the operation of the power-on reset circuit of  FIG. 2 ; 
           [0014]      FIG. 4  is a schematic diagram of a power-on reset circuit which models a critical circuit with both NMOS and PMOS transistors; 
           [0015]      FIG. 5  is a schematic diagram of a power-on reset circuit which models a critical circuit with a CMOS inverter; 
           [0016]      FIG. 6  is a schematic diagram of the power-on reset circuit of  FIG. 5  with the addition of hysteresis components; 
           [0017]      FIG. 7  is a schematic diagram of a prior art single stage op-amp circuit which may be modeled by a power-on reset circuit in accordance with the present invention; 
           [0018]      FIG. 8  is a schematic diagram of a power-on reset circuit which models the single stage op-amp circuit of  FIG. 7 ; 
           [0019]      FIG. 9  is a schematic diagram of a power-on reset circuit which models four critical sub-circuits; and 
           [0020]      FIG. 10  is a schematic diagram of a general power-on reset circuit for modeling a general critical circuit. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0021]      FIG. 1  is a block diagram of a generic prior art circuit  100  which performs critical operations and which may be modeled by a power-on reset circuit in accordance with the present invention. The critical circuit  100  may be part of a larger circuit on an integrated circuit chip. As will be described in more detail below, the critical circuit  100  is presumed to include one or more critical sub-circuit transistor elements (not shown) which in combination draw a current ICC. A voltage drop VCC occurs across the critical circuit  100 . As will be described in more detail below with respect to  FIG. 3 , the critical circuit  100  may have a minimum desired operating voltage for reliable circuit operation. As process and temperature changes occur, the minimum desired operating voltage for the circuit  100  may change. As will be described in more detail below, in accordance with the present invention a power-on reset circuit may be provided which mimics these changes and thus allows the circuit to continue reliable operation at the most energy efficient levels. 
         [0022]    More generally, when a custom integrated circuit is being utilized for which a power-on reset circuit is being designed, it is advantageous to detect a reset condition by determining an actual desired operating voltage for the critical circuit, which may vary with process and temperature. In other words, the minimum operating voltage specified by the manufacturer of the integrated circuit chip may be inaccurate depending on the changes in the operating characteristics of the circuit components, which may vary with process and temperature. By tracking the actual minimum desired operating voltage as it varies with process and temperature, greater energy efficiencies may be achieved in that the critical circuits will be allowed to operate at their true lowest acceptable power levels. In addition, the system is made more robust in that the specifications designated by the manufacturer may not have sufficient safety margins for certain operating conditions (e.g. extreme temperatures or process variations) in which case circuit failure may be avoided by mimicking the actual minimum desired operating voltage. 
         [0023]    As will be described in more detail below with respect to  FIGS. 2-10 , various embodiments of power-on reset circuits of increasing complexity may be provided. As an overall summary of the design principles for the various embodiments, a power-on reset circuit formed in accordance with the present invention mimics the minimum desired operating voltage of the critical circuit  100  in the following manner. The critical circuit  100  is presumed to include one or more critical sub-circuit transistor elements. For each critical sub-circuit transistor element, the power-on reset circuit may include a mimic transistor element designed to have a current density that approximates a current density of the corresponding critical sub-circuit transistor element. In other words, the mimic transistor element is designed to mimic the corresponding critical sub-circuit transistor element, such that for a similar supply voltage VDD, the transistors will become operational at a similar time, and the mimic transistor element may therefore be utilized to mimic the actual desired minimum operating voltage of the corresponding critical sub-circuit transistor element. Furthermore, because both the critical circuit  100  and the power-on reset circuit are implemented in the same custom integrated circuit, temperature changes and process variations will similarly affect the components in both circuits, and will therefore cause similar changes in the voltage/current characteristics of the transistors. The mimic transistor elements thus mimic the operations of the corresponding critical sub-circuit transistor elements. In one embodiment, the mimic transistor elements may be sized with a lower W/L ratio than the corresponding critical sub-circuit transistor elements, so as to limit the current drain in the power-on reset circuit. Various implementations of power-on reset circuits of increasing complexity will be described in more detail below with reference to  FIGS. 2-10 . 
         [0024]      FIG. 2  is a schematic diagram of a power-on reset circuit  200  with a mimic NMOS transistor MM 21  which models a critical circuit with a single NMOS transistor. As will be described in more detail below, the power-on reset circuit  200  is designed to ensure that the power supply voltage VDD is high enough that the mimic transistor MM 21  will operate with a certain current. For example, this could be used to ensure that all NMOS transistors in digital gates in the critical circuit  100  are capable of a minimum drive strength. To minimize the current drain in the power-on reset circuit  200 , in one embodiment the mimic transistor MM 21  can be sized with a lower W/L ratio than a corresponding transistor in the critical circuit  100 , with the current densities still being the same. 
         [0025]    As shown in  FIG. 2 , the power-on reset circuit  200  includes a margin resistor RM 21 , a load resistor RL 22 , a mimic transistor MM 21 , a mirror transistor MT 22  and an output component U 21 . The mimic transistor MM 21  and the mirror transistor MT 22  are both NMOS type transistors. The output component U 21  may in various embodiments be an element such as an inverter or a Schmidt Trigger, as will be described in more detail below. 
         [0026]    As shown in  FIG. 2 , on the left side of the circuit  200 , the margin resistor RM 21  is coupled in series with the mimic transistor MM 21  between the power supply VDD and ground. The circuit node between the margin resistor RM 21  and the mimic transistor MM 21  has a mimic voltage VMPOR and is coupled to the gate of the mimic transistor MM 21 . A margin voltage drop VRM 21  occurs across the margin resistor RM 21 , while a mimic voltage drop VD 21  occurs across the mimic transistor MM 21 . 
         [0027]    On the right side of the circuit  200 , the load resistor RL 22  and the mirror transistor MT 22  are coupled in series between the power supply VDD and ground. The gate of the mirror transistor MT 22  is coupled to the gate of the mimic transistor MM 21 . The circuit node between the load resistor RL 22  and the mirror transistor MT 22  is used for an output for the power-on reset circuit  200  in the form of an output signal POROUT. The output component U 21  receives the signal POROUT and outputs the reset signal CLRN which is utilized to reset the critical circuit  100 , as described above. In this description, all the reset signal outputs (CLRN) will be designated as being active low, as is commonly used. 
         [0028]    In one embodiment, the values of the components of the power-on reset circuit  200  may be selected in accordance with certain desired design parameters. More specifically, certain equations may be utilized to determine the desired component values. For example, for reliable circuit operation a desired operating current ID 1  may be designated as flowing through the margin resistor RM 21  and the mimic transistor MM 21 . The margin resistor RM 21  limits the current when the power supply voltage VDD increases, thus conserving power, and can also be sized to provide certain operating margins, as will be described in more detail below. The equation for sizing the margin resistor RM 21  is: 
         [0000]        VDD   0   =VGS   1   +ID   1   ·RM 21  (Eq. 1) 
         [0029]    Where the voltage VDD 0  is the supply voltage at the trip point under nominal conditions, and the voltage VGS 1  is the expected operating gate-source voltage of the mimic transistor MM 21  at a corresponding current ID 1 . As a specific example, if it is desired to have a 1 uA current as the minimum operating condition, with a margin of 100 mV on the power supply voltage VDD, the gate voltage V GS1  of the mimic transistor MM 21  at that current is expected to be about 1V. The value of the margin resistor RM 21  will be 100K, and VDD 0 =1.1V. 
         [0030]    The current ID 1  is mirrored by the mirror transistor MT 22  and drives the load resistor RL 22 . The output component U 21  may be an inverter, or in one embodiment preferably a Schmidt Trigger, which will trip around VDD/2. When designing the output component U 21 , it is important that it be able to operate at voltages lower than VDD 0 . That means that it will in some implementations use transistors wider than the mimic transistor MM 21  so it can operate effectively in weak inversion at very low voltages. The load resistor RL 22  can be sized to give: 
         [0000]    
       
         
           
             
               
                 
                   
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         [0031]    or RL 22 =550K in the above example. This circuit will reset for voltages lower than 1.1V (VDD 0 ) under nominal conditions, and adjust as the gate voltage V GS1  of the mimic transistor MM 21  changes with process and temperature. 
         [0032]      FIG. 3  is a timing diagram  300  illustrating certain aspects of the operation of the power-on reset circuit  200  of  FIG. 2 , with a slowly rising supply voltage. It will be appreciated that for clarity of illustration, the relationships between various timings and voltages shown in the diagram  300  are not necessarily to scale. As shown in  FIG. 3 , the timing for various signals is illustrated, including a power supply voltage VDD, a power-on-reset circuit current IPOR, an output voltage VPOROUT, a reset signal CLRN, and a modeled critical circuit current ICC. At a time T 0 , all of the signals are at their initial states. Starting at the time T 0 , the power supply is turned on or connected and the power supply voltage VDD begins to ramp up in a linear fashion. The increase in the power supply voltage VDD causes a corresponding increase in the output voltage VPOROUT from the power-on-reset circuit  200 . After a certain interval, the modeled critical circuit current ICC also starts to increase relatively linearly. 
         [0033]    At a time T 1 , the power supply voltage VDD reaches a threshold voltage VTHMPOR for turning on the mimic transistor MM 21  of the power-on-reset circuit  200 . This causes the current IPOR through the power-on-reset circuit  200  to begin increasing in a somewhat linear fashion. In addition, the output voltage VPOROUT begins declining as current begins to flow through the mirror transistor MT 22 . 
         [0034]    At a time T 2 , the power supply voltage VDD reaches a voltage level VOPCC, which is a desired operating voltage for the critical circuit  100 . In addition, the corresponding modeled current ICC of the critical circuit  100  reaches a desired operating current level IOPCC for reliable circuit operation. While the desired operating levels for the critical circuit  100  are thus reached at the time T 2 , as will be described in more detail below, an additional safety margin is implemented which does not allow the critical circuit  100  to become operational until a time T 3 . 
         [0035]    At the time T 3 , the power supply voltage VDD reaches a voltage level VSWITCHPOR for switching the reset signal CLRN, as will be described in more detail below. The difference between the voltage level VOPCC for the desired operating voltage of the critical circuit  100  and the voltage level VSWITCHPOR at which the power-on-reset circuit  200  actually switches the reset signal CLRN, is the margin voltage VMARGIN. The margin voltage VMARGIN is utilized to address issues such as potential mismatches in the integrated circuit. As shown at time T 3 , once the power supply voltage VDD reaches the voltage level VSWITCHPOR, the current IPOR in the power-on-reset circuit  200  reaches a threshold current level ISWITCHPOR, which is a sufficient current for switching the output component U 21 , and the output voltage VPOROUT reaches the threshold voltage level VINVERTER, at which the output component U 21  switches. The switching of the output component U 21  causes the reset signal CLRN to go high, which thus enables the critical circuit  100  to enter a normal operating mode. It will be appreciated that if the steady state level of a power supply voltage is low, such that the power supply voltage VDD never reaches the voltage level VSWITCHPOR, then the reset signal CLRN will remain low, indicating a failure condition and/or inhibiting operation of the critical circuit. 
         [0036]      FIG. 4  is a schematic diagram of a power-on reset circuit  400  for a critical circuit with both NMOS and PMOS transistors. The circuit  200  of  FIG. 2  described above only addresses NMOS transistors, which in certain implementations may not be sufficient for typical CMOS circuits. In contrast,  FIG. 4  shows a power-on reset circuit  400  with two circuits  400 A and  400 B, one with NMOS transistors and one with PMOS transistors. The two outputs OUT 1  and OUT 2  of the circuits  400 A and  400 B are gated with an AND gate to provide the reset signal CLRN. The PMOS and NMOS circuits  400 A and  400 B can be designed to ensure a minimum operating current density in the CMOS digital gates of a critical circuit, which results in ensuring a minimum operating speed. 
         [0037]    The NMOS circuit  400 A is similar to the circuit  200  of  FIG. 2 , and contains similarly numbered components which are connected and operate in a similar fashion as was described above. For the output of the circuit  400 A, the circuit node between the load resistor RL 22  and the mirror transistor MT 22  provides the output signal POROUT 1 . The output component U 21  receives the signal POROUT 1  and outputs a signal OUT 1 . 
         [0038]    The PMOS circuit  400 B is formed similar to the NMOS circuit  400 A, except generally reversed as is known for PMOS circuitry. More specifically, the PMOS circuit  400 B includes a margin resistor RM 43 , a load resistor RL 44 , a mimic transistor MM 43 , a mirror transistor MT 44 , and an output component U 42 . On the left side of the circuit  400 B, the mimic transistor MM 43  and the margin resistor RM 43  are coupled in series between the power supply VDD and ground. The circuit node between the mimic transistor MM 43  and the margin resistor RM 43  is coupled to the gate of the mimic transistor MM 43 , and has a voltage level VMPOR 2 . A mimic voltage drop VD 43  occurs across the mimic transistor MM 43 , while a margin voltage drop VRM 43  occurs across the margin resistor RM 43 . 
         [0039]    On the right side of the circuit  400 B, the mirror transistor MT 44  and the load resistor RL 44  are coupled in series between the power supply VDD and ground. The gate of the mirror transistor MT 44  is coupled to the gate of the mimic transistor MM 43 . The circuit node between the mirror transistor MT 44  and the load resistor RL 44  provides an output signal POROUT 2 . The output component U 42  receives the signal POROUT 2  and outputs a signal OUT 2 . As noted above, the output signal OUT 1  from the NMOS circuit  400 A and the output signal OUT 2  from the PMOS circuit  400 B are combined by the AND gate U 43  to produce the reset signal CLRN. 
         [0040]      FIG. 5  is a schematic diagram of a power-on reset circuit  500  for a critical circuit with a CMOS inverter. In one embodiment, the circuit  500  may be considered to utilize a more conservative approach than the circuit  400  of  FIG. 4 , in that in the circuit  500  the PMOS and NMOS transistors are combined in an inverter configuration. This ensures that the supply voltage VDD is at least greater than the sum of the operating gate to source voltages of both the PMOS and NMOS transistors of the circuit  500 . This is more conservative than what is needed to guarantee the operation of digital circuits, and has the advantage of being a suitable condition for certain implementations of more complex digital and analog circuits. 
         [0041]    As shown in  FIG. 5 , the power-on reset circuit  500  includes a margin resistor RM 51 , a load resistor RL 52 , a mimic transistor MM 51 , a mirror transistor MT 52 , a mimic transistor MM 53 , and an output component U 51 . The mimic transistor MM 51  and the mirror transistor MT 52  are NMOS type transistors, while the mimic transistor MM 53  is a PMOS type transistor. On the left side of the circuit  500 , the margin resistor RM 51 , the mimic transistor MM 53  and the mimic transistor MM 51  are coupled in series between the power supply VDD and ground. The circuit node between the margin resistor RM 51  and the mimic transistor MM 53  has a voltage VMPOR. The circuit node between the mimic transistor MM 53  and the mimic transistor MM 51  is coupled to the gates of the mimic transistor MM 51  and the mimic transistor MM 53 . A margin voltage drop VRM 51  occurs across the margin resistor RM 51 , while a mimic voltage drop VD  53  occurs across the mimic transistor MM 53 , and a mimic voltage drop VD 51  occurs across the mimic transistor MM 51 . 
         [0042]    On the right side of the circuit  500 , the load resistor RL 52  and the mirror transistor MT 52  are coupled in series between the power supply VDD and ground. The gate of the mirror transistor MT 52  is coupled to the gate of the mimic transistor MM 51 . The circuit node between the load resistor RL 52  and the mirror transistor MT 52  provides an output signal POROUT. The output component U 51  receives the signal POROUT and outputs the reset signal CLRN. 
         [0043]      FIG. 6  is a schematic diagram of a power-on reset circuit  600  including the power-on reset circuit  500  of  FIG. 5  with the addition of hysteresis components. The hysteresis components are utilized to create two thresholds. More specifically, when the power supply voltage VDD slowly rises, the circuit  600  will trip at a higher voltage than when it is falling. This means that the ‘turn-on’ condition may have an additional margin, where the ‘brownout’ condition (for a power supply voltage VDD drop when the circuit is already on) may be set at the lowest safe operating voltage. 
         [0044]    As shown in  FIG. 6 , the power-on reset circuit  600  includes all of the components of the circuit  500 , with the addition of certain hysteresis components. More specifically, the margin resistor RM 51  of the circuit  500  has been divided into a hysteresis resistor RH 61  and a margin resistor RM 63  in the circuit  600 . In addition, the circuit  600  further includes a hysteresis transistor MH 64  and a hysteresis inverter U 62 . 
         [0045]    The hysteresis resistor RH 61  and the margin resistor RM 63  are coupled in series between the power supply VDD and the mimic transistor MM 53 . The hysteresis transistor MH 64  is coupled in parallel with the hysteresis resistor RH 61 . The gate of the hysteresis transistor MH 64  is coupled to the output of the hysteresis inverter U 62 , which receives as an input the reset signal CLRN. A hysteresis voltage drop VRH 61  occurs across the hysteresis resistor RH 61 , while a margin voltage drop VRM 63  occurs across the margin resistor RM 63 . 
         [0046]      FIG. 7  is a schematic diagram of a prior art single stage op-amp circuit  700  which may be modeled with a power-on reset circuit in accordance with the present invention, as will be described in more detail below with respect to  FIG. 8 . As shown in  FIG. 7 , the op-amp circuit  700  includes transistors M 71 , M 72 , M 73 , M 74  and M 75 . The transistors M 71 , M 72  and M 73  are PMOS type transistors, while the transistors M 74  and M 75  are NMOS type transistors. The source and body of the transistor M 71  are coupled to the power supply VDD, while the drain is coupled to a circuit node between the sources of the transistors M 72  and M 73 , and to the bodies of the transistors M 72  and M 73 . The drain of the transistor M 72  is coupled to the drain of the transistor M 74 , while the drain of the transistor M 73  is coupled to the drain of the transistor M 75 . The gates of the transistors M 74  and M 75  are coupled to the circuit node between the transistor M 72  and the transistor M 74 . The sources of the transistors M 74  and M 75  are coupled to ground. The gate of the transistor M 71  receives a signal BIAS, while the gate of the transistor M 72  receives a signal IN+, and the gate of the transistor M 73  receives a signal IN−. The circuit node between the transistor M 73  and the transistor M 75  provides an output signal OUT. 
         [0047]      FIG. 8  is a schematic diagram of a power-on reset circuit  800  for the critical single stage op-amp circuit of  FIG. 7 . In the power-on reset circuit  800 , a set of transistors MM 81 , MM 82  and MM 84  reproduce the basic structure of the op-amp circuit  700 . For the op-amp circuit  700  to operate, the supply voltage VDD needs to be high enough to supply the gate voltage of the transistor MM 81 , and the drain-source voltages of the transistors MM 82  and MM 84  at the desired current. In one implementation, such a circuit may have a limited range, but provision for the minimum desired range may be included in the voltage margin provided by the voltage drop across a resistor RM 81 . 
         [0048]    As shown in  FIG. 8 , the power-on reset circuit  800  includes the margin resistor RM 81 , a load resistor RL 82 , the mimic transistors MM 81 , MM 82 , MM 84 , a mirror transistor MT 85 , and an output component U 81 . The mimic transistors MM 81  and MM 82  are PMOS type transistors, while the mimic transistor MM 84  and the mirror transistor MT 85  are NMOS type transistors. On the left side of the circuit  800 , the margin resistor RM 81  and the mimic transistors MM 81 , MM 82  and MM 84  are all coupled in series between the power supply VDD and ground. The circuit node between the margin resistor RM 81  and the mimic transistor MM 81  has a voltage VMPOR. The gates of the mimic transistors MM 81  and MM 82  are coupled to ground. The body of the mimic transistor MM 81  is coupled to its source. The drain of the mimic transistor MM 81  is coupled to the source and body of the mimic transistor MM 82 . The drain of the mimic transistor MM 82  is coupled to the drain of the mimic transistor MM 84 . The gate of the mimic transistor MM 84  is coupled to the circuit node between the mimic transistors MM 82  and MM 84 . A margin voltage drop VM 81  occurs across the margin resistor RM 81 , while a mimic voltage drop VD 81  occurs across the mimic transistor MM 81 , and a mimic voltage drop VD 82  occurs across the mimic transistor MM 82 , and a mimic voltage drop VD 84  occurs across the mimic transistor MM 84 . 
         [0049]    On the right side of the circuit  800 , the load resistor RL 82  and the mirror transistor MT 85  are coupled in series between the power supply VDD and ground. The gate of the mirror transistor MT 85  is coupled to the gate of the mimic transistor MM 84 . The circuit node between the load resistor RL 82  and the mirror transistor MT 85  provides the output signal POROUT. The output component U 81  receives the signal POROUT and provides the reset signal CLRN. 
         [0050]      FIG. 9  is a schematic diagram of a power-on reset circuit  900  for four critical sub-circuits. More specifically, in a complex integrated circuit, several power-on reset circuits can be used to ensure the operation of several critical circuits.  FIG. 9  shows a complete power-on reset system, where the four critical circuits have been identified and included in the voltage-based power-on reset circuits, and a time-delay power-on reset has further been added to protect against a fast rising power-on. 
         [0051]    As shown in  FIG. 9 , the power-on reset circuit  900  includes power-on reset subcircuits U 91 , U 92 , U 93 , U 94 , U 95 , and an AND gate U 96 . The power-on reset circuit U 95  is a time-delay based circuit, and will provide a reset pulse in the case of a fast rising power on. The outputs OUT 1 -OUT 5  of the power-on reset circuits U 91 -U 95  are combined by the AND gate U 96 , which outputs the reset signal CLRN. 
         [0052]      FIG. 10  is a schematic diagram of a general power-on reset circuit  1000  for modeling a general critical circuit. The circuit  1000  illustrates a general version of the power-on reset circuit concept, where a mimic circuit U 111  represents the structure of the critical circuit that defines the minimum safe operating supply voltage, with a current output IMIRROR to drive a load resistor RL 112 . 
         [0053]    As shown in  FIG. 10 , the power-on reset circuit  1000  includes a margin resistor RM 111 , the load resistor RL 112 , the mimic circuit U 111  and an output component U 112 . The margin resistor RM 111  and the mimic circuit U 111  are coupled in series between the power supply VDD and ground. The circuit node between the margin resistor RM 111  and the mimic circuit U 111  has a voltage VMPOR. A voltage drop VRM 111  occurs across the margin resistor RM 111 , while a voltage drop VD 111  occurs across the mimic circuit U 111 . The load resistor RL 112  is coupled in series with a mirror portion (not shown) of the mimic circuit U 111  between the power supply VDD and ground. The circuit node between the load resistor RL 112  and the mirror portion of the mimic circuit U 111  provides the output signal POROUT. The output component U 112  receives the signal POROUT and outputs the reset signal CLRN. 
         [0054]    While the preferred embodiment of the invention has been illustrated and described, numerous variations in the illustrated and described arrangements of features and sequences of operations will be apparent to one skilled in the art based on this disclosure. Thus, it will be appreciated that various changes can be made therein without departing from the spirit and scope of the invention.