Abstract:
One or more portions of the design (e.g., components, channels, or portions thereof) can be assigned instances of one or more component power domains (CPDs). Assigning an instance of a CPD to a design element (or to a portion thereof) can indicate, for example, whether the element can be switched on and off, or whether the element can operate over a range of voltages. The CPD instances can, in turn, be assigned to one or more design power domains (DPDs). Assignments of a CPD to a DPD can be evaluated according to a set of compatibility rules. Two or more electronic design elements can be connected by one or more signal paths. Organizing the CPD instances into DPDs can aid in finding signal paths that cross from a first DPD to a second DPD. To improve the reliability of signal paths traversing a DPD boundary, one or more power domain interface (PDI) components can be created to handle the signal paths at the boundary.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims the benefit of U.S. Provisional Patent Application No. 60/706,188, titled “Automating Power Domain,” filed Aug. 5, 2005, which is incorporated herein by reference. 
     
    
     TECHNICAL FIELD  
       [0002]     This disclosure relates to electronic design automation tools.  
       BACKGROUND  
       [0003]     Power consumption in an integrated circuit (IC) can be a factor in IC design. For example, increases in complexity and speed of IC designs can outstrip the benefits of advances such as voltage reduction and feature size scaling. Given higher clock rates and larger die sizes, power dissipation can, in some cases, become a limiting factor of performance in IC designs, e.g., in system-on-chip (SoC) designs.  
         [0004]     One approach to managing power consumption in an IC is to design some areas of the chip to be “turned off” or otherwise consume less power. For example, a processor in a TV or other device can be designed to turn off selected areas of the processor when in a “standby” mode, while another area of the processor monitors for a “wake-up” call, e.g., from a remote control. In another example, a processor in a computer can run at full power when executing a processing-intensive task, and scale down the power used by the chip when executing a less-demanding task.  
       SUMMARY  
       [0005]     To aid power management in an IC design, one or more portions of the design (e.g., components, channels, or portions thereof) can be assigned instances of one or more component power domains (CPDs). Assigning an instance of a CPD to a design element (or to a portion thereof) can indicate, for example, whether the element can be switched on and off, or whether the element can operate over a range of voltages. The CPD instances can, in turn, be assigned to one or more design power domains (DPDs). Two or more electronic design elements can be connected by one or more signal paths. Organizing the CPD instances into DPDs can aid in finding signal paths that cross from a first DPD to a second DPD. To improve the reliability of signal paths traversing a DPD boundary, one or more power domain interface (PDI) components can be created to handle the signal paths at the boundary. The PDI components themselves can be wrapped (e.g., in a hardware description language (HDL) file) to aid incorporating the PDI components into the design.  
         [0006]     The disclosed technologies can aid in addressing power management issues at a high-level stage in an IC design process (although the disclosed technologies are not limited to any particular stage or stages of the design process), and at least some of the steps can be automated. This can make incorporating power domains into IC designs faster and more efficient.  
         [0007]     One embodiment comprises, in a method for an electronic circuit design comprised of one or more circuit design elements, receiving a first set of assignments based on one or more descriptors of the one or more circuit design elements in the electronic circuit design, the first set comprising one or more assignments of instances of a first set of power domains to one or more of the circuit design elements, receiving a second set of assignments comprising one or more assignments of the instances to a second set of power domains, applying one or more compatibility rules to the second set of assignments, and identifying one or more power domain boundaries in the circuit design based on the second set of assignments. Some embodiments further comprise creating, according to one or more templates, one or more boundary circuit design elements for handling one or more transmission signals crossing from a first member of the second set of power domains to a second member of the second set of power domains. Creating one or more boundary circuit design elements can comprise instantiating in the electronic design transmission gate logic for the one or more transmission signals, and instantiating in the electronic design one or more blocks of control logic. In further embodiments, the first set of power domains comprises a default power domain. In additional embodiments, the second set of power domains comprises a default power domain. In some embodiments, the default power domain is a switchable and a scaleable power domain. In other embodiments, the first set of power domains has one or more switchability indicators and the second set of power domains has one or more switchability indicators, and applying one or more compatibility rules comprises comparing at least one switchability indicator of the second set of power domains with at least one switchability indicator of the first set of power domains. In another embodiment, the first set of power domains has one or more voltage range indicators and the second set of power domains has one or more voltage range indicators, and applying one or more compatibility rules comprises comparing at least one voltage range indicator of the second set of power domains with at least one voltage indicator of the first set of power domains. An integrated circuit can be made according to one or more of the above methods.  
         [0008]     In another embodiment, a computer-readable storage medium containing a data structure describing a power domain for an element in an electronic design, the data structure comprising: indicators of one or more bus interfaces associated with the power domain; indicators of one or more signals associated with the power domain; a scalability indicator indicating whether a power domain voltage can be scaled; and a switchability indicator indicating whether the power domain can be switched on and off. The data structure can be described using a mark-up language. In some embodiments, the scalability indicator comprises an approximate minimum voltage for the power domain and an approximate maximum voltage for the power domain. The approximate minimum voltage for the power domain and an approximate maximum voltage for the power domain are approximately equal. The data structure can further comprise a power domain name.  
         [0009]     In an additional embodiment, a system for performing electronic design automation comprises a processor and a computer-readable medium comprising instructions for performing a method, the method comprising receiving a first set of assignments based on one or more descriptors of one or more circuit design elements in the electronic circuit design, the first set comprising one or more assignments of instances of a first set of power domains to one or more of the circuit design elements, receiving a second set of assignments comprising one or more assignments of the instances to a second set of power domains, applying one or more compatibility rules to the second set of assignments, and identifying one or more power domain boundaries in the circuit design based on the second set of assignments. In some embodiments, the method further comprises creating, according to one or more templates, one or more boundary circuit design elements for handling one or more signals crossing from a first member of the second set of power domains to a second member of the second set of power domains. Creating one or more boundary circuit design elements can comprise receiving one or more indications of the one or more common boundaries, receiving a selection of a template, the template comprising signal connection information, generating transmission gate logic for at least some of the one or more signals at the common boundaries, and generating control logic. The template can be provided in a mark-up language description. In some embodiments, the method further comprises inserting into the electronic design the one or more boundary circuit design elements.  
         [0010]     Additional features and advantages will become apparent from the following detailed description of illustrated embodiments, which proceeds with reference to the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]      FIG. 1  shows a block diagram of an exemplary embodiment of an electronic circuit design.  
         [0012]      FIG. 2  shows an example of the circuit design  100  of  FIG. 1  with CPDs assigned to some components and channels.  
         [0013]      FIG. 3  shows an example of an extensible mark-up language (XML) passage that describes CPD information.  
         [0014]      FIG. 4  shows one embodiment of a user interface for creating DPDs and managing CPDs and DPDs.  
         [0015]      FIG. 5  shows the user interface of  FIG. 4  displaying CPD instances assigned to DPDs.  
         [0016]      FIG. 6  shows an exemplary electronic circuit design with one embodiment of a conceptual boundary domain loop.  
         [0017]      FIG. 7  shows a flowchart of one embodiment of a method of adding a PDI component to an electronic design.  
         [0018]      FIG. 8  shows one embodiment of an exemplary user interface for selecting a template for generating a PDI component.  
         [0019]      FIG. 9  shows one embodiment of a description of a template for generating a PDI component.  
         [0020]      FIG. 10  shows a block diagram of an exemplary electronic circuit design.  
         [0021]      FIG. 11  shows a flowchart of one embodiment of a method for power domain handling in an electronic design.  
         [0022]      FIG. 12  is a diagram illustrating an exemplary client-server network environment.  
         [0023]      FIG. 13  is a diagram illustrating an exemplary method of exchanging electronic design automation information using a client-server network, such as the one illustrated in  FIG. 12 . 
     
    
     DETAILED DESCRIPTION  
       [0024]     The disclosed technologies are directed toward novel and unobvious features and aspects of the embodiments of the system and methods described herein. The disclosed features and aspects of the embodiments can be used alone or in various novel and unobvious combinations and sub-combinations with one another.  
         [0025]     Although the operations of the disclosed methods are described in a particular, sequential order for convenient presentation, it should be understood that this manner of description encompasses rearrangements, unless a particular ordering is required by specific language set forth below. For example, operations described sequentially can in some cases be rearranged or performed concurrently. Moreover, for the sake of simplicity, the disclosed flow charts and block diagrams typically do not show the various ways in which particular methods can be used in conjunction with other methods. Additionally, the detailed description sometimes uses terms like “provide” or “determine” to describe the disclosed methods. Such terms are high-level abstractions of the actual operations that are performed. The actual operations that correspond to these terms will vary depending on the particular implementation and are readily discernible by one of ordinary skill in the art.  
         [0026]     Some of the methods described herein can be implemented in software stored on a computer-readable medium and executed on a computer. Some of the disclosed methods, for example, can be implemented as part of an electronic design automation (EDA) tool. Such methods can be executed on a single computer or on a networked computer. For clarity, only those aspects of the software germane to these disclosed methods are described; product details well-known in the art are omitted. For the same reason, the computer hardware is not described in detail.  
         [0000]     Exemplary Electronic Design Elements  
         [0027]     Some embodiments of the disclosed technology can be implemented with electronic circuit designs comprised of one or more circuit design elements. In some embodiments, one type of element is a component, sometimes also referred to as an “intellectual property block” or an “IP block.” Components can comprise input and output interfaces, and (as is explained below) they can also comprise additional components. In some embodiments, another type of element is a type of bus called a channel. Signals, such as individual signals and/or signal buses, can be carried to or from a component using a channel.  
         [0028]     As is well known in the art, an electronic design can be represented in a number of ways at a number of different abstraction levels. In some embodiments, an electronic design can be converted from a higher-level representation (e.g., a high-level representation in a hardware description language (HDL)) to one or more lower-level representation, e.g., a transistor-level representation. An electronic design can also be prepared for fabrication and then fabricated into an actual semiconductor product.  
         [0029]     In some embodiments, an EDA tool can create a hierarchical component (HC) by creating an abstraction of one or more other components and/or channels. For example, an HC can be created by “packaging” several components together, such that an EDA tool user can treat the several components, at least in some circumstances, as a unitary component. Accordingly, components and channels can themselves be HCs comprised of one or more components and/or channels.  
         [0030]     In further embodiments, an EDA tool can create and/or use one or more ad-hoc components. An ad-hoc component is a component that does not have an interface that is consistent with one or more other component interfaces in a design.  
         [0031]      FIG. 1  is a block diagram of an exemplary embodiment of an electronic design  100 . The design  100  comprises components cmp 1 , cmp 2 , cmp 3 , and cmp 4 , as well as channels ch 1 , ch 2  and ch 3 . Data connections between the components and channels are indicated in  FIG. 1  by thick arrows. For example, the arrow  110  indicates a data connection between the component cmp 2  and the channel ch 2 . Arrows that have one end not connected to a component or channel indicate data connections with elements external to the design  100 . For example, the arrow  112  indicates one or more input signals entering cmp 2  from outside of the design  100 , while arrow  114  indicates one or more output signals from cmp 4  to an element outside of the design  100 .  
         [0032]     In some embodiments, components can be configured with various interfaces. For example, the components in  FIG. 1  can comprise one or more “controller” interfaces (also called “master” interfaces, sometimes indicated in this application by “M”) and one or more controlled interfaces (also called “slave” interfaces, sometimes indicated in this application by “S”). Generally, controller interfaces handle output signals or buses, while controlled interfaces handle input signals or buses. For example, the component cmp 1  of  FIG. 1  comprises two controlled interfaces and one controller interface, as indicated by the labels “S” and “M” on the component cmp 1 .  
         [0033]     In further embodiments, channels can similarly be configured with one or more interfaces. For example, the individual channels in  FIG. 1  can comprise one or more “controller mirror” interfaces (also called “master mirror” interfaces, sometimes indicated in this application by “MM”) and one or more “controlled mirror” interfaces (also called “slave mirror” interfaces, sometimes indicated in this application by “SM”). Generally, a controller mirror interface receives one or more signals or buses from a controller interface on a component, while a controlled mirror interface provides one or more signals or buses to a controlled interface on a component. For example, the channel ch 1  in  FIG. 1  comprises a controller mirror interface (MM) coupled to a controller interface on the component cmp 1 . The channel ch 1  further comprises two controlled mirror interfaces (SM) coupled to a controlled interface on the component cmp 3  and to the controlled interface (S) on the component cmp 4 . In some embodiments, a controlled interface (S) can be configured to act as a controller interface for another controlled interface.  
         [0000]     Exemplary Embodiments of Power Domains  
         [0034]     A “power domain” is a logical organization of one or more elements of an electronic design, such as a component and/or channel, a portion of a component and/or channel, or combinations of several components and/or channels. A component power domain (CPD) can be assigned to one or more components, channels, and/or portions thereof. A particular assignment of a CPD to a component or channel is referred to as an “instance” of the CPD. A CPD can comprise a set of properties. For example, in some embodiments a CPD comprises: a list of one or more bus interfaces that belong to the CPD; a list of one or more signals that belong to the CPD; minimum and maximum voltage information for the CPD; and whether the CPD can be switched on and off. For the purposes of this application, a signal or bus interface “belongs” to a CPD if the CPD contains information regarding handling the signal or bus interface.  
         [0035]     The power consumption of a power domain can be controlled several ways. In some embodiments, power consumption is controlled by scaling the voltage used by elements associated with the power domain. For example, to reduce power consumption, the voltage provided to elements in a given power domain can be reduced from a first level to a second, lower lever, e.g., changed from 5.5V to 2.2V, or to one or more voltage values in between these values. (Generally speaking, voltage values can be selected according to design constraints of a particular component or electronic design.) In other embodiments consumption can be controlled by switching elements associated with the domain on or off as desired. Further embodiments can use one or more combinations of these techniques. (For the purposes of this application, statements such as “scaling the voltage of a power domain,” or “turning a power domain on or off” refer to actions carried out on elements associated with the power domain.)  
         [0036]      FIG. 2  shows an example of the electronic circuit design  100  of  FIG. 1  with CPD instances assigned to some components and channels. For example an instance of the component power domain CPD 1  is assigned to the MM interface of channel ch 1 , and an instance of the component power domain CPD 2  is assigned to the SM interfaces of channel ch 1 . Similarly, component cmp 4  has a first M interface and a first S interface assigned to CPD 1 , as well as a second M interface and a second S interface assigned to CPD 2 . In the figures of this application, a thin-thick-thin line (e.g., line  202  on channel ch 1 , or line  204  on component cmp 3 ) indicates an interface within a component or channel between two or more component power domains. In some embodiments such interfaces can occur because of the hierarchical nature of electronic designs.  
         [0037]     In some embodiments, not all elements have one or more CPD instances explicitly to them. For example, in  FIG. 2  component cmp 1  and channels ch 2 , ch 3  do not have CPD instances explicitly assigned to them. One or more components and channels such as these can have a default CPD assigned to them, or the elements can have no CPD assigned to them.  
         [0038]     In some embodiments, an instance of a CPD can be assigned to an element by providing CPD information in a descriptor of the element. This description can be provided in a number of formats well known to those of ordinary skill in the art. For example, the description can be provided in one or more data structures. In some embodiments, the data structures can be stored in a mark-up language such as XML.  FIG. 3  provides an example of an XML passage  300  that can be included in an element description to provide CPD information for two CPDs, “amba” and “vpb.” For a CPD associated with the element, the exemplary description can comprise: 
        a name tag  302 ,  304 ;     a list of bus interfaces  306 ,  308  that belong to the named CPD;     a list of signals  310  in the element that belong to the CPD;     a scalability indicator  312 ,  314 , such as comprising a Boolean value and a voltage range; and     a switchability indicator  316 ,  318 , which can also comprise a Boolean value.        
 
         [0044]     The scalability indicator can indicate that a range of voltages is supported by the CPD. The voltage range provided in the scalability indicator can be stated in relative and/or absolute values and can comprise a minimum and maximum voltage value supported by the CPD. In some embodiments, if the Boolean value for the scalability indicator states that the CPD is not scalable, the voltage range can be omitted for the CPD. The switchability indicator can indicate that the CPD can be switched off.  
         [0045]     Some embodiments do not require a description to contain all of the information listed above. For example, a list of bus interfaces or a list of component signals can be omitted from a description of a given CPD. If CPD information is not provided for a signal or bus interface in a component or channel, a default CPD can be assigned to the signal or bus interface, or no CPD can be assigned to them. In some embodiments, the default CPD is not scalable and/or not switchable. Some further embodiments can use descriptions comprising additional information.  
         [0046]     In further embodiments, CPD information for a component can be configured via a user interface, e.g., a graphical user interface or a command-line interface.  
         [0047]     One or more CPD instances can be grouped into a logical organization called a design power domain (DPD). In some embodiments, a DPD can, like a CPD, comprise a scalability indicator (such as, for example, comprising a Boolean value and a voltage range) and a switchability indicator. In further embodiments, CPD instances can be assigned to a DPD based on an algorithm and/or based on user input. For example, in some embodiments, CPD instances can be assigned to one or more DPDs based on scalability values for the CPD instances.  
         [0048]      FIG. 4  shows one embodiment of a user interface (UI)  400  for creating DPDs and managing CPDs and DPDs. Lists  410 ,  420  display the existing CPD instances and the existing DPDs, respectively. For example, list  410  indicates (among others) that instances of CPD 1  and CPD 2  are assigned to component cmp 3 , and that no CPD instances are explicitly assigned to component cmp 1 . (However, as mentioned above, in some embodiments if no CPD instance is explicitly assigned to a component or channel, a default CPD can be assigned to the component or channel.) UI elements such as buttons  430 ,  432  can be used to create or delete a DPD. In the depicted user interface  400 , clicking on the create button  430  can cause a dialog box  434  to appear, in which a user can indicate properties for a new DPD, such as a name, scalability and switchability indicators, and minimum and maximum voltages. If a DPD is indicated as being non-scalable, a single voltage can be provided (e.g., the maximum and minimum voltages can be set to the same value). Alternatively, the EDA tool can be configured to assume that one voltage or the other is to be always used for the DPD. In further embodiments, for a DPD indicated as being scalable, setting the maximum and minimum voltages both to zero can be used to indicate an unlimited voltage range. In the example embodiment shown here, the list  420  shows two DPDs: “PowerDomain 1 ” and “RealTimeClock.” For the purposes of this example, “PowerDomain 1 ” is a default DPD. In some embodiments, a multiple number of DPDs can be created.  
         [0049]      FIG. 5  shows the user interface  400  displaying CPD instances assigned to DPDs. In this particular embodiment, the nomenclature [element name]/[CPD name] indicates the instance of a particular CPD assigned to a particular element. For example, “cmp 3 /cpd 2 ” indicates the instance of CPD 2  assigned to component cmp 3 . In this embodiment, where only a component or channel label is listed (e.g., “cmp 1 ”), this indicates that an instance of the default CPD is assigned to this component or channel.  
         [0050]     In  FIG. 5 , the exemplary list  420  shows that the CPD instances cmp 2 /cpd 2 , cmp 4 /cpd 2  and ch 1 /cpd 2  are assigned to the DPD “RealTimeClock.” The list  420  also shows that the remaining CPD instances (including instances of the default CPD) are assigned to the default DPD, “PowerDomain 1 .” CPD instances can be assigned to (or unassigned from) a DPD by selecting the instance name and then “moving” the instance onto or off of the list  420 , such as by using user interface buttons  440 ,  442 . Other user interfaces can be used for assigning CPD instances to a DPD.  
         [0051]     In some embodiments, it is possible for two or more CPD instances with “conflicting” properties to be assigned to the same DPD. For example, an instance of a first CPD can have a different voltage range than an instance of a second CPD. Some embodiments of an EDA tool can apply one or more compatibility rules to “validate” a given set of CPD instances assigned to a DPD. The following are some non-limiting, examplary rules that an embodiment of an EDA tool can apply to resolve possible conflicts: 
        If a DPD is switchable, all CPD instances assigned to the DPD must also be switchable.     If a DPD is not switchable, then a CPD instance can be assigned to that DPD regardless of the switchability of the CPD.     If a DPD is scalable, then: CPDs for CPD instances assigned to the DPD must be scalable; the maximum voltages of the CPDs must be equal to or greater than the maximum DPD voltage; and the minimum voltage of the CPDs must be equal to or less than the minimum DPD; or, both the maximum and minimum CPD voltages must be equal to zero (indicating an unlimited range for the CPD).     If a DPD is not scalable, the minimum voltage is always or almost always used by the DPD. In some embodiments, the maximum and minimum voltages of a non-scalable DPD must match.     If a DPD is not scalable, an instance of a scalable CPD can be added to the DPD if the minimum and maximum voltages of the CPD encompass the DPD voltage setting.     If a DPD is not scalable, then an instance of a non-scalable CPD can be added if the CPD voltage setting matches the DPD voltage setting.     * The default CPD and DPD are switchable and scalable.     The default CPD and DPD have an unlimited voltage range (this can be indicated by, e.g., setting the minimum and maximum voltages to 0).        
 
         [0060]     In some embodiments, the EDA tool can be configured to resolve one or more conflicts by altering properties of one or more CPDs and/or DPDs. For example, an assignment of a CPD instance can be changed from a first DPD to a second DPD. Alternatively, the EDA tool can present an error message to a user and allow a user to resolve a conflict. Other, alternative rules that can be created and applied to assignments of a CPD instance to a DPD.  
         [0061]      FIG. 6  shows the electronic design  100  of  FIGS. 1 and 2  with one embodiment of a conceptual boundary domain loop  610  drawn according to the list  420  of  FIG. 5 . More specifically, line  610  provides a visual indication of CPD instances assigned to the RealTimeClock DPD (in this case, ch 1 /cpd 2 , cmp 2 /cpd 2  and cmp 4 /cpd 2 ). The remaining CPD instances in the design (including instances of the default CPD) are shown as being assigned to the default DPD PowerDomain 1  (e.g., by their position outside of the loop  610 ).  
         [0000]     Exemplary Embodiments of a Power Domain Interface Component  
         [0062]     Figures such as  FIG. 6  can, in some embodiments, indicate data connections in the design that pass from a first DPD to a second DPD. Examples of such connections are indicated at connections  620 ,  630 . Data signals that cross from one DPD to another DPD can, in some cases, be interpreted incorrectly by components or channels in the other DPD. For example, in some embodiments a first component in a first DPD of a design operating at a scaled-down voltage can provide a ‘1’ signal at a relatively high voltage to a second component in a second DPD of the design. If the second component is operating at a higher voltage and receives the signal in an unbuffered state, it can erroneously interpret the signal as being a ‘0’. Accordingly, it can be useful to generate one or more power domain interface (PDI components (sometimes referred to herein as a “boundary circuit design elements”), which can be configured to correctly interpret signals between DPDs. The PDI components can then be inserted into the design at interfaces between two DPDs.  
         [0063]     Generally, in one specific exemplary approach involving a design with N DPDs, a maximum of  
           (     N   -   1     )     ⁢   N     2       
 
         [0064]     PDI components are needed. This expression can be derived as follows: In a design with two DPDs (A, B), conceptually one PDI component is needed to interface DPD A to DPD B, and another component to connect DPD B to DPD A. In embodiments where a PDI component is bi-directional, these two PDI components can be bundled together into the same PDI component.  
         [0065]     In a design with three DPDs (A, B, C), conceptually PDI components are required from A to B and from A to C; from B to A and B to C; and from C to A and C to B. Again, given bidirectional PDI components, the A to B and B to A signals, and so forth, can be bundled together into the same component.  
         [0066]     Thus, for an overall design with N DPDs, there are potentially connections to all other DPDs (i.e., (N- 1 )N). This figure is then halved because the PDI components are presumed to be bi-directional.  
         [0067]     In some embodiments, one or more PDI components can be created individually by a user. For example, the user can provide a detailed description of how signals are handled between domains, and the EDA tool can construct a PDI component accordingly. The user can also provide information concerning PDI control signals, including whether the signals are input or output signals, as well as how those signals are connected in the overall circuit design.  
         [0068]     In other embodiments, individual or multiple PDI components (e.g., all PDI components for a design) can be generated automatically according to one or more templates. Accordingly, in some embodiments the use of templates can make incorporation of power domains into a design faster and more efficient. Generally speaking, a template can provide a connection policy containing one or more descriptions of how signals from the DPDs are to be handled in a PDI component. Electronic design generation using templates is well known in the art, and in some embodiments a template used to generate a PDI component can be conceptually similar to a template used for a design controller, design arbitration, bus decoding, etc. The content of template can vary with, for example, one or more design objectives. In some embodiments, a template contains control signal information. In other embodiments a template contains an indicator of the language or languages the PDI component will be generated in, which can ease the PDI component&#39;s integration into a design.  
         [0069]      FIG. 7  shows a flowchart of one exemplary embodiment of a method  700  of adding a PDI component to an electronic design. A list of a power domain crossings is received (step  710 ). This list can be provided by the user or by an EDA tool. A template selection is received (step  720 ) from a user or from the EDA tool. Using the received template, transmission gate logic for one or more signals crossing the DPD boundaries is instantiated in the design (step  730 ), and a control logic block for the PDI component is instantiated in the design (step  740 ). Adding the control logic block can increase the number of pins in PDI component. In some embodiments, one control logic block is instantiated for all PDI components in the electronic design. In other embodiments, multiple control logic blocks are instantiated.  
         [0070]      FIG. 8  shows one embodiment of a user interface  800  for selecting a template for generating a PDI component. The UI  800  comprises a dialogue box  810 , the dialogue box further comprising a list  820  of DPD interfaces and a list  830  of template interfaces. A user can select a template for a corresponding DPD interface. In the depicted embodiment, a template “And-Gate” or “Cross-Coupled-And” can be selected for the DPD interface “PowerDomain 1 &lt;=&gt;RealTimeClock.” Other user interfaces can also be used.  
         [0071]      FIG. 9  shows one embodiment of a description  900  of a template for generating a PDI component. (This embodiment is written in XML, but other embodiments can use other formats.) The description  900  comprises a section  910  of external signals, in addition to the transmission signals crossing the DPD boundaries, to be added to the PDI component. Those of ordinary skill in the art will recognize that the number and type of external signals can vary. A section  920  comprises code (e.g., HDL or similar code) which describes the functions of the control logic block(s). A section  930  describes handling of one or more transmission signals. In some embodiments, a template causes transmission gate logic to be instantiated identically for every transmission signal. In other embodiments, a template causes transmission gate logic to be instantiated differently for at least some transmission signals.  
         [0072]      FIG. 10  shows a block diagram of one embodiment of an electronic design  1000 , which is similar to the electronic design  100  of  FIG. 1 . In addition to the components and channels shown in previous figures, electronic design  1000  further comprises a PDI component placed at the boundary between the DPDs. The PDI component is shown in this figure as two separate PDI components  1010 ,  1020 , but functionally they are one component handling signals passing between the DPDs. In other embodiments, however, they can be structured as two separate components. A PDI component can be configured to handle one or more signals. A control block  1030  provides control signals for the PDI components  1010 ,  1020 . In some embodiments, additional signals, such as control 1  and testOut, are used by control block  1030 . In  FIG. 10 , arrows  1032 ,  1034  represent one or more signals (e.g., control signals) passing between the control block  1030  and the PDI components  1010 ,  1020 . In the embodiment shown in  FIG. 10 , the PDI components  1010 ,  1020  comprise interfaces complementary to the interfaces of the respective components and channels to which the PDI components  1010 ,  1020  are logically adjacent. For example, PDI component  1010  comprises an S interface and an SM interface, which can interface with an SM interface of channel ch 1  and the S interface of component cmp 3 , respectively. PDI component  1020  comprises an MM interface and an M interface, which can interface with the M interface of component cmp 2  and the MM interface of channel ch 2 , respective.  
         [0073]     Some EDA tool embodiments can require that the PDI component be wrapped in an HDL file (or a file in a similar language) to create an ad-hoc component. A PDI template can be used to generate the HDL file.  
         [0074]     Exemplary Embodiments of the Disclosed Method  FIG. 11  shows a flowchart of one embodiment of a method  1100  for power domain handling in an electronic design. CPD assignments are received (step  1110 ) and DPD assignments are received (step  1120 ). Compatibility rules can be applied to the DPD assignments (step  1130 ), and one or more boundaries between DPDs can be identified in the design (step  1140 ). The compatibility rules can comprise, for example, one or more of the rules discussed above. A PDI can be constructed (step  1150 ). In some embodiments the PDI in constructed according to the method  700  described above. The PDI can be inserted into the electronic design (step  1160 ). In some embodiments, the electronic design can be represented as an HC. Information regarding any CPDs and DPDs in the HC can be included in a descriptor of the HC.  
         [0000]     Exemplary Computing Environment  
         [0075]     Any of the aspects of the technology described above can be performed or designed using a distributed computer network.  FIG. 12  shows one such exemplary network. A server computer  1200  can have an associated storage device  1202  (internal or external to the server computer). For example, the server computer  1200  can be configured to process EDA information related to electronic designs using any of the embodiments described above (e.g., as part of an EDA tool). The server computer  1200  can be coupled to a network, shown generally at  1204 , which can comprise, for example, a wide-area network, a local-area network, a client-server network, the Internet, or other such network. One or more client computers, such as those shown at  1206 ,  1208 , can be coupled to the network  1204  using a network protocol.  
         [0076]      FIG. 13  shows one embodiment in which a client computer (e.g., computers  1206  and  1208  of  FIG. 12 ) can receive results (e.g., power domain information) related to processing EDA related information (e.g., power domain rules) according to any of the embodiments disclosed herein using a remote server computer, such as the server computer  1200  shown in  FIG. 12 . In step  1350 , for example, a client computer sends data related to EDA. For instance, a client computer can send a rule file, one or more proposed IC design layouts and other EDA information from a design database. In step  1354 , the data is received by the server computer and processed according to any of the disclosed embodiments. In step  1356 , the server computer sends the results (e.g., revised electronic circuit designs) to the client computer, which receives the results in step  1358 .  
         [0077]     Having described and illustrated the principles of the disclosed technologies with reference to the illustrated embodiments, it will be recognized that the illustrated embodiments can be modified in arrangement and detail without departing from such principles. For example, elements of the illustrated embodiment shown or described in software can be implemented in hardware and vice versa. Also, the technologies from any example can be combined with the technologies described in any one or more of the other examples. Thus, for instance, any method, process, system, or tool described herein with respect to power domains can be used in conjunction with other EDA related information for other EDA uses in other EDA related tools. In view of the many possible embodiments to which the principles of the technologies can be applied, it should be recognized that the illustrated embodiments are examples and should not be taken as a limitation on the scope of the invention. For instance, various components of systems and tools described herein can be combined in function and use. We therefore claim as our invention all subject matter that comes within the scope and spirit of these claims.