Abstract:
A method and system for a multi-rate Media Access Control layer (MAC) to Physical layer (PHY) interface is provided. The method to provide a multi-rate Media Access Control layer (MAC) interface comprises receiving a first set of signals, sampling the first set of signals to determine a type of interface to be used to transmit or receive the first set of signals or a subset of the first set of signals, generating a select signal indicating type of interface to be used based on the sampling step and transmitting the first set of signals or a subset of the first set of signals using the interface indicated by the select signal. The method to provide a multi-rate Physical layer (PHY) interface comprises receiving a select signal from a Physical layer (PHY) layer indicating data rate of a first set of signals, selecting a first interface and turning off the second interface if the select signal indicates the first interface is to be used, selecting the second interface and turning off the first interface if the select signal indicates the second interface is to be used and transmitting the first set of signals using the second interface or a subset of the first set of signals using the first interface based on the select signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 12/007,343 filed on Jan. 9, 2008, which claims the benefit of U.S. Provisional Application No. 60/880,006 filed Jan. 12, 2007, all of which are incorporated herein by reference in their entireties. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention generally relates to networking and more specifically to an multi-rate interface between a MAC layer and a PHY layer. 
     2. Background Art 
     In computer network systems there is typically a natural division between chips handling the physical layer, which is responsible for transmitting data on the network, and the system chips, which perform logical operations with data transmitted on the network. Each port in an Ethernet device is typically composed of a system chip, which includes a media access controller (MAC) layer or “MAC” and a physical (PHY) layer or “PHY”. Most multi-port Ethernet devices integrate one or more MACs into one system chip (MAC chip) as well as one or more PHYs into another chip (PHY chip). An interface is required on each chip to transfer signals between the MACs and the PHYs. 
     IEEE standard 802.3 standards define protocols for interfaces between a MAC layer and a PHY for specific known data rate on a backplane link. However, if the data rate on a backplane link to a PHY is variable then there is lack of an interface that can support the variable data rate. Methods and systems are needed to overcome the above deficiencies. 
     BRIEF SUMMARY OF THE INVENTION 
     The invention comprises a method and system for a multi-rate Media Access Control layer (MAC) to Physical layer (PHY) interface. The method to provide a multi-rate Media Access Control layer (MAC) interface comprises receiving a first set of signals, sampling the first set of signals to determine a type of interface to be used to transmit or receive the first set of signals or a subset of the first set of signals, generating a select signal indicating type of interface to be used based on the sampling step and transmitting the first set of signals or a subset of the first set of signals using the interface indicated by the select signal. The method further comprises generating a third signal indicating data rate of the first set of signals to a MAC layer. 
     A method to provide a multi-rate Physical layer (PHY) interface is also described. The method comprises receiving a select signal from a Physical layer (PHY) indicating data rate of a first set of signals, selecting a first interface and turning off the second interface if the select signal indicates the first interface is to be used, selecting the second interface and turning off the first interface if the select signal indicates the second interface is to be used and transmitting the first set of signals using the first interface or a subset of the first set of signals using the second interface based on the select signal. 
     A multi-rate Media Access Control layer (MAC) interface is also provided. The interface comprises a first interface configured to transmit and receive a first set of signals from a Physical layer (PHY) and generate a first signal indicating whether the first set of signals correspond to the first interface, a second interface configured to transmit and receive the first set of signals from the (PHY) interface and generate a second signal indicating whether the first set of signals correspond to the second interface. The interface also comprises an auto-detect module coupled to the first and second interfaces and configured to generate a third signal indicating the type of interface to be used and a mux coupled to the first interface, the second interface, the auto-detect unit and configured to transmit the first set of signals using the first interface or a subset of the first set of signals using the second interface based on the third signal. 
     A multi-rate Physical layer (PHY) interface is also provided. The multi-rate PHY interface comprises a first interface configured to transmit and receive a first set of signals from a Media Access Control (MAC) interface and a second interface configured to transmit and receive the first set of signals from the MAC interface. The PHY interface also includes a mux coupled to the first interface, the second interface and configured to transmit the first set of signals or a subset of the first set of signals to or from a PHY layer based on a select signal received from a PHY layer. 
     In an embodiment, the type of interface is one of 10 Gigabit Attachment Unit Interface (XAUI) or Serial Gigabit Media Independent Interface (SGMII). 
     Additional features and advantages of the invention will be set forth in the description that follows, and in part will be apparent from the description, or may be learned by practice of the invention. The advantages of the invention will be realized and attained by the structure and particularly pointed out in the written description and claims hereof as well as the appended drawings. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES 
       The accompanying drawings illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable one skilled in the pertinent art to make and use the invention. 
         FIG. 1A  illustrates an example 10 Gbps interface between a MAC and a PHY. 
         FIG. 1B  illustrates an example 10/100/1000 Mbps interface between a MAC and a PHY. 
         FIG. 1C  illustrates an interface that includes XAUI and SGMII. 
         FIG. 2A  illustrates a multi-rate interface for between a MAC and a PHY in a first mode of operation according to an embodiment of the invention. 
         FIG. 2B  illustrates a multi-rate interface between a MAC and a PHY in a second mode of operation according to an embodiment of the invention. 
         FIG. 3A  illustrates MAC interface in further detail according to an embodiment of the invention. 
         FIG. 3B  illustrates a flowchart showing steps performed by a MAC interface according to an embodiment of the invention. 
         FIG. 4A  illustrates a PHY interface in further detail according to an embodiment of the invention. 
         FIG. 4B  illustrates a flowchart showing steps performed by a PHY interface according to an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention provides a multi-rate interface between a MAC and PHY layers, and applications thereof. Methods and systems are provided for a multi-rate MAC to PHY interface that is enabled to utilize a 10 Gbps Attachment Unit Interface (XAUI) protocol for 10 Gbps link connections and a Serial Gigabit Media Independent Interface (SGMII) protocol for 10/100/1000 Mbps link connections by using one set of interface signals. A combined interface that can operate on either the XAUI or SGMII protocol eliminates an extra set of pins that a MAC chip and PHY chip would require if interfaces for both XAUI and SGMII protocols are separately implemented. In another aspect of the invention, the need for the MAC to read registers in the PHY to determine what speed the interface between MAC and PHY needs to run at is avoided. 
     In an embodiment, the multi-rate interface comprises a PHY interface, a MAC interface and lanes coupling the MAC interface to the PHY interface. The interface speed is unknown until the line/cable side or “backplane link” of the PHY has negotiated the desired rate with its link partner. Once this negotiation has taken place the PHY layer switches the PHY interface to the desired standard, XAUI or SGMII, where upon the MAC layer either detects XAUI signals or the negotiated rate through SGMII and switches the MAC interface accordingly. Through the use of parallel detecting the differences between the SGMII protocol and the XAUI protocol, the combined multi-rate interface is automatically configured to match the speed of the link connection. 
     In the detailed description of the invention that follows, references to “one embodiment”, “an embodiment”, “an example embodiment”, etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. 
     Overview 
     In Ethernet design, MAC and PHY layer protocols are typically implemented on two distinct micro-chips mounted on a circuit board. An interface is required between the MAC chip and the PHY chip. The interface is dependent on rate of operation of the PHY, which in turn is dependent on the speed of the backplane link of the Ethernet network. 
       FIG. 1A  illustrates a system  100  with an example 10 Gbps Attachment Unit Interface (XAUI)  106 . In this example, backplane link  122  is a 10 Gbps signal. XAUI interface  106  includes a XAUI MAC interface  110 , XAUI PHY interface  112  and four transmit/receive lanes  114   a - n , each running at 3.125 Gbit/s using 8B/10B encoding. XAUI interface  108  is designed to the IEEE 802.3ae 10 Gbit Ethernet specification. XAUI is typically used as a 16-pin replacement for the 72-pin 10 Gigabit Medium-Independent Interface (XGMII). In an alternate embodiment, interface  106  may operate according to XGMII protocol to route 10 Gbps signals between MAC  102  and PHY  104 . In yet another embodiment, interface  106  is a 10 Gigabit Serial Electrical Interface (XFI). XFI provides a single lane running at 10.3125 Gbit/s with a 64B/66B encoding scheme. 
       FIG. 1B  illustrates a system  100  with an example SGMII interface  108  between MAC layer  102  and PHY layer  104 . In this example, backplane link  122  carries a 10/100/1000 Mbps signal. Interface  108  comprises SGMII MAC interface  116 , SGMII PHY interface  112  and transmit/receive lanes  114   a - n . SGMII is a standard 10/100/1000 Mbps protocol used to connect a MAC to a PHY. SGMII is typically used for Gigabit Ethernet, as opposed to Media Independent Interface (MII) which is used for 10/100 Mbps Ethernet. SGMII interface  108  uses a double data rate technology enabling an effective rate of 1.25 Gbaud between MAC  102  and PHY  104 . In this format, eight pins are allocated to four channels with one pair each for receiving data and clock signals and one pair each for transmitting data and clock signals. Backplane link  122  determines the rate at which PHY  104  operates. 
       FIG. 1C  illustrates an interface  130  that includes both a XAUI interface  106  and a SGMII interface  108 . With current definition for MAC to PHY interfaces, a distinct SGMII interface  108  is required if link  122  resolves to a 10/100/1000 Mbps speed and a distinct XAUI interface is required if link  122  resolves to a 10 Gbps speed. However, as seen in  FIG. 1C , implementing distinct interfaces for both SGMII and XAUI protocols significantly increases the number of pins and lanes on limited chip and printed circuit board (PCB) real estate. Furthermore, the conventional means for determining whether SGMII interface  108  or XAUI interface  106  is to be used is to read internal management registers of PHY  104 . 
     With a multi-rate PHY  104  that can support both 10/100/1000 Mbps and 10 Gbps speeds, there is a need for a single interface between MAC  102  and PHY  104  that can support both SGMII and XAUI protocols while utilizing minimum number of lanes between MAC  102  and PHY  104 . Embodiments presented below provide a multi-rate MAC to PHY interface that supports both SGMII and XAUI protocols. 
     Example Embodiments 
       FIG. 2A  illustrates a multi-rate interface  200  operating in SGMII mode according to an embodiment of the invention. Interface  200  includes MAC interface  202 , PHY interface  204  and lanes  206   a - d . Each of signal  206  includes a transmit lane and a receive lane. Interface  200  is a XAUI interface modified to support SGMII mode in addition to XAUI mode. In an embodiment, during startup, PHY  104  sets PHY interface  204  to transmit in SGMII mode using signal  206   a . MAC  102  parallel detects SGMII signal on lane  206   a  and also sets MAC interface  202  to SGMII mode on lane  206   a . Lanes  206   b - d  are inactive and propagate no signals. In this example, backplane link  122  resolves to a 10/100/1000 Mbps rate and interface  200  remains in SGMII mode. PHY  104  passes control information to MAC  102  via standard SGMII auto-negotiation.  FIG. 2B  described below illustrates the case where link  122  resolves to a 10 Gbps rate. 
       FIG. 2B  illustrates multi-rate interface  200  operating in XAUI mode according to an embodiment of the invention. In the present example, backplane link  122  resolves to a 10 Gbps speed. PHY  104  is enabled to detect a 10 Gbps signal on backplane  122 . PHY interface  202  is in SGMII mode upon startup as described above with reference to  FIG. 2A . Upon detecting a 10 Gbps signal on link  122 , PHY  104  switches PHY interface  204  from SGMII mode to XAUI mode and transmits/receives on all four lanes  206   a - d . MAC  102  is enabled to parallel detect XAUI signals, set MAC interface  202  to XAUI mode and transmit/receive on all four lanes  206   a - d.    
     In an alternate embodiment, during startup, PHY interface  204  is automatically set to XAUI mode on lanes  206   a - d . MAC  102  parallel detects XAUI signals on lanes  206   a - d  and also sets MAC interface  202  to XAUI mode. If backplane link  122  resolves to a 10/100/1000 Mbps rate, PHY  102  switches PHY interface  204  to SGMII mode on lane  206   a  and lanes  206   b - d  are rendered inactive. MAC  102  parallel detects SGMII signal and sets MAC interface  202  to SGMII mode on lane  206   a  while rendering lanes  204   b - d  inactive. Interface  200  may be referred to as a 10 Gbps Serial Media Independent Interface (XGSMII). 
       FIG. 3A  illustrates MAC interface  202  in further detail according to an embodiment of the invention. 
     MAC interface  202  includes auto-detect module  300 , SGMII MAC interface  116 , XAUI MAC interface  110  and mux  312 . Auto-detect module  300  is coupled to mux  312 , SGMII MAC interface  116 , XAUI MAC interface  110  and MAC  102 . Mux  312  is coupled to auto-detect module  300 , SGMII MAC interface  116 , XAUI MAC interface  110  and MAC  102 . XAUI MAC interface  110  is coupled to PHY interface  204 , mux  312 , auto-detect module  300  and MAC  102 . SGMII MAC interface  116  is coupled to PHY interface  204 , auto-detect module  300 , mux  312  and MAC  102 . 
     Mux  312  transmits and receives signals  302   a  to/from MAC  102 . Mux  312  transmits and receives signal  302   a   1  to/from SGMII MAC interface  116 . Mux  312  also transmits and receives signal  302   a   2  to/from XAUI MAC interface  110 . Auto-detect module  300  is configured to generate select signal  310  which is fed to mux  312 . Auto-detect module  300  is also configured to generate signal  308  which is sent to MAC  102 . XAUI MAC interface  110  is configured to generate signal  314  which is fed to auto-detect module  300 . SGMII MAC interface  116  is configured to generate signal  316  which is fed to auto-detect module  300 . XAUI MAC interface transmits and receives signals  206  to/from PHY interface. SGMII MAC interface  116  transmits and receives signal  206   a  to/from PHY interface  204 . 
     Upon detecting a signal on one of lanes  206  from PHY interface  204 , XAUI MAC interface  110  and SGMII MAC interface  116  sample the link to determine whether XAUI or SGMII is to be used. XAUI MAC interface  110  is configured to generate signal  314  indicating whether XAUI mode is to be used. SGMII MAC interface  116  is configured to generate signal  316  indicating to auto-detect module  300  whether SGMII mode is to be used. Signal  316  is also used to indicate whether the connections speed of link  206  is 10 Mbps, 100 Mbps or 1000 Mbps. 
     Auto-detect module  300  is configured to, based on signals  314  and  316 , determine whether XAUI or SGMII is to be used for signal  206 . Auto detect module  300  is enabled to generate signal  308  which indicates SGMII 10 Mbps, 100 Mbps or 1000 Mbps speed or XAUI 10 Gbps speed to MAC  102 . 
     Auto-detect module  300 , based on signals  314  and signals  316  generates a select signal  310  which is sent to mux  312 . Select signal  310  indicates whether SGMII mode or XAUI mode is in use. Based on select signal  310 , mux  312  routes either signal  302   a   1  from SGMII MAC interface  116  or signal  302   a   2  from XAUI MAC interface  110  to MAC  102 . In SGMII mode, only signal  302   a  is transmitted and the remaining lanes  302   b - d  are inactive. In XAUI mode, mux  312  selects signal  302   a   2  to be routed to  302   a  and lanes  302   b - d  are also active. Signals  302   a - d  correspond to signals  206  received from PHY interface  204 . 
       FIG. 3B  illustrates a flowchart  320  showing steps performed by MAC interface  202  according to an embodiment of the invention. Flowchart  320  will be described with reference to the example operating environment illustrated in  FIG. 3A . In an embodiment, steps  320  are performed by MAC interface  202 . However, the flowchart is not limited to that embodiment. Note that some steps shown in flowchart  320  do not necessarily have to occur in the order that is shown. 
     In step  322 , a signal is received from PHY interface  204 . For example, MAC interface  202  receives signal  206  from PHY interface  104 . 
     In step  324 , the signal received in step  322  is sampled to determine the type of interface to be used to transmit and receive the signal from step  322 . For example, SGMII MAC interface  116  and XAUI MAC interface  110  sample signal  206  received in step  322 . 
     In step  326 , one of SGMII or XAUI interfaces generate a signal to indicate whether they have linked with the signal received in step  322 . For example, XAUI MAC interface  110  generates signal  314  to indicate to auto-detect module  300  whether it has linked with signal  206 . SGMII MAC interface  116  is configured to generate signal  316  to indicate to auto-detect module  300  whether it has linked with signal  206 . 
     In step  328 , the link speed of the signal received in step  322  is indicated to a MAC layer. For example, auto-detect module  300  indicates the speed of link  206  to MAC  102  via signal  308 . 
     In step  330 , based on the signals received from SGMII and XAUI interfaces in step  326 , a signal is generated to select either SGMII mode or XAUI mode. For example, based on signal  314  received from XAUI MAC interface  110  and signal  316  received from SGMII MAC interface  116 , auto-detect module  300  is configured to generate a signal  310  which is used by mux  312  to route either signal  302   a   1  from SGMII MAC interface  116  onto  302   a  or route signals  302   a   2  from XAUI MAC interface  110  to MAC  102 . In SGMII mode, only lane  302   a  is active and in XAUI mode, lanes  302   a - d  are active. 
       FIG. 4A  illustrates PHY interface  204  in further detail according to an embodiment of the invention. 
     PHY interface  204  comprises SGMII PHY interface  118 , XAUI PHY interface  112  and mux  402 . Mux  402  is coupled to MAC interface  202 , PHY  104 , SGMII PHY interface  118  and XAUI PHY interface  112 . SGMII PHY interface  118  is coupled to mux  402  and PHY interface  104 . XAUI PHY interface  112  is coupled to PHY interface  104  and mux  402 . XAUI PHY interface  112  is configured to transmit/receive signals  206   b - d  and  206   a   2  and SGMII PHY interface  118  is configured to transmit/receive signal  206   a   1  both of which are fed to mux  402 . Mux  402  is configured to transmit/receive signals  206   a . Mux  402  selects either signals  206   a   1  or signal  206   a   2  to be transmitted onto signal  206   a  based on speed select signal  400 . SGMII PHY interface  118  and XAUI PHY interface  112  transmit and receive signals  408  to/from PHY layer  104 . Signals  408  are derived from backplane link  122 . 
     PHY  104  generates signal  400  to indicate whether a 10 Mbps/100 Mbps/1000 Mbps data rate (SGMII mode) or a 10 Gpbs data rate (XAUI mode) is selected. If signal  400  indicates SGMII mode then, XAUI PHY interface  112  is turned off and mux  402  receives and transmits signals  206   a   1  onto signal  206   a  and lanes  206   b - d  are inactive. If signal  400  indicates XAUI mode to be used, then SGMII PHY interface  118  is turned off and mux  402  receives and transmits signal  206   a   2  onto signal  206   a . Lanes  206   b - d  are active and transmit signals in XAUI mode. 
       FIG. 4B  illustrates a flowchart  420  showing steps performed by PHY interface  204  according to an embodiment of the invention. Flowchart  420  will be described with reference to the example operating environment illustrated in  FIG. 4A . However, the flowchart is not limited to that embodiment. Note that some steps shown in flowchart  420  do not necessarily have to occur in the order that is shown. 
     In step  422 , a signal is generated to select either SGMII or XAUI transmission mode. For example, PHY layer  104  generates select signal  400  to select either SGMII or XAUI mode. 
     In step  424 , it is determined whether SGMII or XAUI mode has been selected. For example, based on signal  400 , SGMII interface  118 , XAUI interface  112  and mux  402  determine whether SGMII or XAUI mode is selected. 
     If SGMII mode is selected then control proceeds to step  426 . If XAUI mode is selected then control proceeds to step  428 . 
     In step  426 , based on the signal generated in step  422 , a XAUI interface is turned off. For example, based on signal  400  XAUI PHY interface  112  is turned off. 
     In step  430 , based on the signal received in step  422  the mux is set to select signals from the SGMII interface. For example, based on signal  400 , mux  402  selects signal  206   a   1  from SGMII PHY interface  118  to transmit and receive to/from MAC interface  202 . Lanes  206   b - d  are inactive. 
     In step  428 , based on the signal received in step  422 , a SGMII interface  118  is turned off. For example, SGMII PHY interface  118  is turned off based on signals  400 . 
     In step  432 , mux  402  is set to select signals from the XAUI interface. For example, based on signal  400 , mux  402  selects signal  206   a   2  from XAUI PHY interface  112  to transmit and receive to/from MAC interface  202 . Lanes  206   b - d  are also active in XAUI mode. 
     Alternate Embodiments 
     In an alternate embodiment, interface  200  supports SGMII and XFI modes. In yet another embodiment, interface  200  may support SGMII and 10 GBASE-KR mode. It is to be appreciated that the number of lanes, data rates and protocols used are a design choice and arbitrary. 
     Conclusion 
     While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example and not limitation. It will be apparent to one skilled in the pertinent art that various changes in form and detail can be made therein without departing from the spirit and scope of the invention. Therefore, the present invention should only be defined in accordance with the following claims and their equivalents.