Abstract:
When a gate voltage V GS  is applied, the Schottky barrier width due to the metallic spin band in the ferromagnetic source is decreased, and up-spin electrons from the metallic spin band are tunnel-injected into the channel region. However, down-spin electrons from the nonmagnetic contact ( 3   b ) are not injected because of the energy barrier due to semiconductive spin band of the ferromagnetic source ( 3   a ). That is, only up-spin electrons are injected into the channel layer from the ferromagnetic source ( 3   a ). If the ferromagnetic source ( 3   a ) and the ferromagnetic drain ( 5   a ) are parallel magnetized, up-spin electrons are conducted through the metallic spin band of the ferromagnetic drain to become the drain current. Contrarily, if the ferromagnetic source ( 3   a ) and the (ferromagnetic drain ( 5   a ) are antiparallel magnetized, up-spin electrons cannot be conducted through the ferromagnetic drain ( 5   a ) because of the energy barrier Ec due to the semiconductive spin band in the ferromagnetic drain ( 5   a ). Thus, a high-performance high-degree of integration nonvolatile memory composed of MISFETs operating on the above operating principle can be fabricated.

Description:
FIELD OF THE INVENTION 
     The present invention relates to novel transistors, and more particularly, to a field-effect transistor with spin-dependent transmission characteristics and a non-volatile memory using the field-effect transistor. 
     BACKGROUND OF THE INVENTION 
     Today&#39;s highly advanced information society has dramatically developed, and particularly, “mobile communication devices” are being widely spread in the general public. The great demand for “mobile communication devices” is regarded as one of the essential elements in the future semiconductor industry. To satisfy the demand, however, it is necessary to achieve non-volatility of information, as well as high-speed performance, lower electric consumption, and large capacities that have conventionally be required in semiconductor integrated circuits. In response to such demands, attention has been drawn to a novel memory device in which the ferromagnetic storage technique that excels in non-volatile high-density recording combined with the semiconductor integration electronics. This device is called a magnetic random access memory (hereinafter referred to as “MRAM”), and a magnetic tunnel junction (hereinafter referred to as “MTJ”) having a thin insulating tunnel barrier sandwiched between ferromagnetic electrodes is used as a memory device for the MRAM (disclosed in “Present and Future of Magnetic RAM Technology”, K. Inomata, IEICE Trans. Electron. Vol. E84-C, pp. 740-746, 2001, for example). 
     In the MTJ, the tunneling resistance differs depending on the relative magnetization direction between the ferromagnetic electrodes. This is called a tunneling magneto-resistance (TMR) effect. Utilizing TMR, it is possible to electrically detect the magnetizing state of each ferromagnetic body. Accordingly, the information non-volatile storage technique using ferromagnetic bodies can be ideally incorporated into the semiconductor integration electronics by virtue of the MTJ. 
     In the following, an example of the conventional technique is described in conjunction with  FIG. 10 . As shown in  FIG. 10 , in a MRAM memory cell  100 , a 1-bit memory cell is formed with a MTJ  101  and a metal-oxide-semiconductor field-effect transistor (hereinafter referred to as “MOSFET”)  103 . The MTJ  101  is a tunnel junction that is formed with a first ferromagnetic electrode  105 , a second ferromagnetic electrode  107 , and a tunnel barrier (an insulator)  108  formed with an insulator provided between the first and second ferromagnetic electrodes  105  and  107 . 
     The source (S) of the MOSFET  103  is grounded (GND), and the drain (D) of the MOSFET  103  is connected to the ferromagnetic electrode  107  of the MTJ  101  with a plug PL or the like. The ferromagnetic electrode  105  of the MTJ  101  is connected to a bit line BL. A rewrite word line  111  is disposed to cross the bit line BL immediately above or below the MTJ  101 , being electrically insulated from the MTJ  101  and the other lines by the insulating film  115 . A read word line WL is connected to the gate electrode G of the MOSFET  103 . 
     Since the magnetization direction can be maintained in a non-volatile manner in a ferromagnetic body, binary information can be stored in a non-volatile manner by adjusting the relative magnetization state between the ferromagnetic electrodes of the MTJ to parallel magnetization or antiparallel magnetization. In the MTJ, the tunneling resistance differs depending on the relative magnetization state between the two ferromagnetic electrodes, due to the TMR effect. Accordingly, the magnetization state in the MTJ can be electrically detected, using the tunneling resistance that depends on the magnetization state such as parallel magnetization and antiparallel magnetization. 
     To rewrite information, the retentivity of the ferromagnetic electrode  105  is made different from the retentivity of the ferromagnetic electrode  107  in the MTJ  101 , or the magnetization of the ferromagnetic electrode with lower retentivity or an unfixed magnetization direction is inverted while the magnetization direction of the other ferromagnetic electrode is fixed. Hereinafter, the ferromagnetic electrode having the magnetization varied will be referred to as the “free layer”, and the ferromagnetic electrode having the fixed magnetization will be referred to as the “pin layer”. More specifically, currents are applied to the bit line BL and the rewrite word line  111  that cross each other on the selected cell, and the magnetization state of the MTJ  101  in the memory cell  100  selected by the compound magnetic field of the magnetic fields induced by the currents is changed to parallel magnetization or antiparallel magnetization. Here, the size of each current to be applied to each corresponding line is set so that the magnetization of each MTJ  101  of the unselected cells having the same bit line BL or the rewrite word line  111  as that of the selected cell is not inverted by the magnetic fields generated from only either the bit line BL or the rewrite word line  111 . To read information, a voltage is applied to the read word lines WL connected to the selected cell so as to energize the MOSFET  103 , and a read driving current is then applied to the MTJ  101  via the bit line BL. In the MTJ  101 , the tunneling resistance differs depending on the magnetization state such as parallel magnetization or antiparallel magnetization, due to the TMR effect. Accordingly, the magnetization state can be checked by detecting a voltage drop (hereinafter referred to as “output voltage”) caused by the read driving current in the MTJ  101  (see “Present and Future of Magnetic RAM Technology”, K. Inomata, IEICE Trans. Electron. Vol. E84-C, pp. 740-746, 2001). 
     DISCLOSURE OF THE INVENTION 
     A MTJ has a binary resistance value that depends on whether the magnetization state between the ferromagnetic electrodes opposed to each other via a tunnel barrier is parallel magnetization or antiparallel magnetization. To accurately detect the binary information with a driving current, it is necessary to optimize the size of the output voltage through adjustment of the impedance (the junction resistance) of the MTJ. 
     To accurately read the contents of stored information, the ratio of output signals between the two magnetization states of parallel magnetization and antiparallel magnetization needs to be high. Therefore, it is necessary to maximize the rate of change in TMR between the case where the MTJ exhibits parallel magnetization and the case where the MTJ exhibits antiparallel magnetization. The MTR ratio depends on the spin polarization rate P of the ferromagnetic electrodes. To increase the TMR ratio, a ferromagnetic material with a high P value needs to be employed for the ferromagnetic electrodes. 
     The TMR ratio in a MTJ greatly depends on the bias voltage to be applied to the MTJ, and rapidly decreases according to the bias voltage. When a high driving current is applied to the MTJ to read information with high precision and at a high speed, the voltage drop becomes large in the MTJ, and the TMR ratio decreases accordingly. Therefore, bias resistance is required for the TMR ratio, so as to prevent the TMR ratio from decreasing even if a large voltage drop is caused in the MTJ. 
     A MRAM is suitable for high-density integration, having a simple structure. Also, a MRAM is desirable because each MTJ can be reduced to a nanoscale structure. When high integration of several gigabits or higher is to be realized, the channel length of the MOSFET is expected to be 0.1 μm or shorter. However, if minute MTJs are integrated in conformity with such minute transistors, the contacts and multilayer lines take up a large portion of the cell area, and high-density integration of both components becomes difficult. Therefore, there is a demand for memory cells with simpler structures. 
     The present invention provides a metal-insulator-semiconductor field-effect transistor (MISFET), using Schottky junctions for the source and the drain formed with a ferromagnetic material. The present invention also provides a large-capacity non-volatile memory device in which each 1-bit memory cell is formed with the transistor. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a cross-sectional view schematically illustrating the structure of a MISFET in accordance with a first embodiment of the present invention; 
         FIG. 2A  shows the energy band structure of the ferromagnetic source, the semiconductor layer, and the ferromagnetic drain of a MISFET of the accumulation n-channel type that employs a ferromagnetic metal for the ferromagnetic source and the ferromagnetic drain in the structure of  FIG. 1 ; 
         FIG. 2B  shows the energy band structure of the ferromagnetic source, the semiconductor layer, and the ferromagnetic drain of a MISFET of the inversion n-channel type; 
         FIG. 3A  shows the energy band structure of the ferromagnetic source, the semiconductor layer, and the ferromagnetic drain of a MISFET of the accumulation n-channel type that employs a half metal for the ferromagnetic source and the ferromagnetic drain in a structure in accordance with a second embodiment of the present invention; 
         FIG. 3B  shows the energy band structure of the ferromagnetic source, the semiconductor layer, and the ferromagnetic drain of a MISFET of the inversion n-channel type in the structure in accordance with the second embodiment; 
         FIG. 4A  illustrates the principles of the operation of a MISFET having the energy band structure shown in  FIG. 2A , and shows the energy band structure in a case of parallel magnetization; 
         FIG. 4B  shows the energy band structure that is obtained when a bias V DS  is applied in the case where the ferromagnetic source and the ferromagnetic drain exhibit parallel magnetization; 
         FIG. 4C  shows the energy band structure that is obtained when a bias V GS  is further applied in the situation shown in  FIG. 4B ; 
         FIG. 4D  shows the energy band structure that is obtained in a case where the ferromagnetic source and the ferromagnetic drain exhibit antiparallel magnetization with the same bias as that of  FIG. 4C ; 
         FIG. 5A  illustrates the principles of the operation of a MISFET having the energy band structure shown in  FIG. 2B , and shows the energy band structure in a case of parallel magnetization; 
         FIG. 5B  shows the energy band structure that is obtained when a bias V DS  is applied in the case where the ferromagnetic source and the ferromagnetic drain exhibit parallel magnetization; 
         FIG. 5C  shows the energy band structure that is obtained when a bias V GS  is further applied in the situation shown in  FIG. 5B ; 
         FIG. 5D  shows the energy band structure that is obtained in a case where the ferromagnetic source and the ferromagnetic drain exhibit antiparallel magnetization with the same bias as that of  FIG. 5C ; 
         FIG. 6A  illustrates the principles of the operation of a MISFET having the energy band structure shown in  FIG. 3A , and shows the energy band structure in a case of parallel magnetization; 
         FIG. 6B  shows the energy band structure that is obtained when a bias V DS  is applied in the case where the ferromagnetic source and the ferromagnetic drain exhibit parallel magnetization; 
         FIG. 6C  shows the energy band structure that is obtained when a bias V GS  is further applied in the situation shown in  FIG. 6B ; 
         FIG. 6D  shows the energy band structure that is obtained in a case where the ferromagnetic source and the ferromagnetic drain exhibit antiparallel magnetization with the same bias as that of  FIG. 6C ; 
         FIG. 7A  illustrates the principles of the operation of a MISFET having the energy band structure shown in  FIG. 3B , and shows the energy band structure in a case of parallel magnetization; 
         FIG. 7B  shows the energy band structure that is obtained when a bias V DS  is applied in the case where the ferromagnetic source and the ferromagnetic drain exhibit parallel magnetization; 
         FIG. 7C  shows the energy band structure that is obtained when a bias V GS  is further applied in the situation shown in  FIG. 7B ; 
         FIG. 7D  shows the energy band structure that is obtained in a case where the ferromagnetic source and the ferromagnetic drain exhibit antiparallel magnetization with the same bias as that of  FIG. 7C ; 
         FIG. 8  schematically shows the drain current-voltage characteristics of the source ground of a MISFET in accordance with this embodiment; 
         FIG. 9A  illustrates an example structure of a memory circuit that employs MISFETs in accordance with this embodiment; 
         FIG. 9B  illustrates a memory circuit that has an output terminal V o  connected to the bit line end of the memory circuit of  FIG. 9A , and is connected to a supply voltage V DD  via a load R L  branching from the output terminal V o ; 
         FIG. 9C  shows the static characteristics and operating points of the memory cell of  FIG. 9B ; 
         FIG. 10  is a cross-sectional view of a memory cell that is used in a conventional MRAM; 
         FIG. 11  illustrates an example structure of a memory cell in accordance with any of the embodiments of the present invention, in which a ferromagnetic source is shared; 
         FIG. 12  shows the energy band structure of a MISFET in accordance with a third embodiment of the present invention; 
         FIG. 13A  shows the energy band structure of a MISFET in which an n-type ferromagnetic semiconductor is used for the source and the drain, and an intrinsic semiconductor is interposed between the source and the drain, in accordance with a fourth embodiment of the present invention; and 
         FIG. 13B  shows the energy band structure of a MISFET in which an n-type ferromagnetic semiconductor is used for the source and the drain, and a p-type semiconductor is interposed between the source and the drain, in accordance with a fifth embodiment of the present invention. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A metal-insulator-semiconductor field-effect transistor (hereinafter referred to as “MISFET”) in accordance with the present invention stores information as the relative magnetization direction of a drain made of a ferromagnetic body with respect to a source made of a ferromagnetic body (hereinafter referred to as “ferromagnetic drain” and “ferromagnetic source”), and reads the stored information utilizing the transmission characteristics depending on the relative magnetization direction. With such a MISFET in accordance with the present invention, a single transistor can form a 1-bit non-volatile memory cell. Accordingly, a high-speed, high-capacity non-volatile memory can be produced. 
     First, a MISFET in accordance with a first embodiment of the present invention is described, with reference to the accompanying drawings. 
       FIG. 1  is a cross-sectional view of the MISFET in accordance with the first embodiment of the present invention. As shown in  FIG. 1 , the MISFET of this embodiment includes a MIS structure that is the same as that of a general MISFET (a SiMOSFET, for example) that is formed with a gate electrode  7 , a gate insulating film  11 , and a non-magnetic semiconductor layer  1 , and a source (a ferromagnetic source)  3  and a drain (a ferromagnetic drain)  5  that form a Schottky junction with the non-magnetic semiconductor film  1 . The ferromagnetic source and the ferromagnetic drain may be made of: a ferromagnetic metal such as Fe, Ni, Co, Permalloy, CoFe alloy (CO 1-x Fe x ), and CoFeB alloy (Co 1-x-y Fe x B y ); or a half metal such as Heusler alloy such as CO 2 MnSi, zinc-blende CrAs, CrSb, and MnAs. Alternatively, the ferromagnetic source and the ferromagnetic drain may be formed with ferromagnetic semiconductors each having a ferromagnetic-metal band structure, or ferromagnetic semiconductors each having a half-metal band structure. The ferromagnetic source  3  and the ferromagnetic drain  5  are formed by epitaxially growing or depositing a ferromagnetic material on the non-magnetic semiconductor layer  1 . Alternatively, the ferromagnetic source  3  and the ferromagnetic drain  5  may be formed by introducing magnetic atoms into the non-magnetic semiconductor layer  1  through thermal diffusion or ion implanting. The arrows shown on the ferromagnetic source and the ferromagnetic drain in  FIG. 1  indicate the magnetization direction. The gate insulating film may be made of SiO 2 , Al 2 O 3 , or HfO 2 , which is a high dielectric constant material. 
     In the MISFET of this embodiment, a carrier of the same conduction type as the non-magnetic semiconductor layer (or a semiconductor substrate)  1  can be made a conduction carrier. Alternatively, a carrier of the opposite conduction type to the non-magnetic semiconductor layer  1  may be induced and used as a conduction carrier. Here, the former is referred to as an accumulation channel type, and the latter is referred to as an inversion channel type, for ease of explanation. In a case where an n-channel MISFET is formed, an n-type semiconductor is used for the accumulation channel type, while a p-type semiconductor is used for the inversion channel type. Likewise, in a case where a p-channel MISFET is formed, a p-type semiconductor is used for the accumulation channel type, while an n-type semiconductor is used for the inversion channel type. Hereinafter, an n-channel accumulation channel type will be referred to as an accumulation n-channel type, and an n-channel inversion channel type will be referred to as an inversion n-channel type. Likewise, a p-channel accumulation channel type will be referred to as an accumulation p-channel type, and a p-channel inversion channel type will be referred to as an inversion p-channel type. 
     Regardless of whether or not a channel actually exists, the semiconductor region immediately below the interface between the gate insulating film and the semiconductor is referred to as a channel region. In the following, the energy band structures of a transistor of the accumulation n-channel type and a transistor of the inversion n-channel type are described with respect to a case where a ferromagnetic metal is used for the ferromagnetic source and the ferromagnetic drain, and a case where a half metal is used for the ferromagnetic source and the ferromagnetic drain. Although not described in detail, a MISFET of the accumulation p-channel type and a MISFET of the inversion p-channel type can be formed in the same manner as described below. In accordance with the present invention, enhancement-type MISFETs and depression-type MISFETs can be formed. In the following, enhancement-type MISFETs will be described. Originally, the term “spin” is used as in “spin angular momentum”. In the following description, however, electrons with up spins may be referred to simply as “up spins” in terms of carriers. 
       FIGS. 2A and 2B  show energy band structures in the case where a ferromagnetic metal is employed as the ferromagnetic body.  FIGS. 3A and 3B  show energy band structures in the case where a half metal is employed as the ferromagnetic body. 
       FIG. 2A  shows the energy band structure in the vicinity of the channel region of a MISFET of the accumulation n-channel type in the case where a ferromagnetic metal is used for the ferromagnetic source and the ferromagnetic drain. The ferromagnetic source  3  and the ferromagnetic drain  5  are formed by Schottky junction the non-magnetic n-type semiconductor layer  1  to the ferromagnetic metal ( 3 ,  5 ). The solid lines on the ferromagnetic source  3  and the ferromagnetic drain  5 , and the dotted line on the n-type semiconductor layer  1  in  FIG. 2A  indicate Fermi energy E F . E G  indicates the band gap of the semiconductor. 
     E C  and E V  indicate the bottom of the conduction band of the semiconductor layer  1  and the top of the valence band, respectively. In the drawings hereafter, E F , E C , E V , and E G  indicate the same as above. The height of the barrier of the Schottky junction between the ferromagnetic metal and the n-type semiconductor is denoted by φ n , which represents the energy difference between the Fermi energy E F  and the energy E C  at the bottom of the conduction band of the n-type semiconductor layer  1  on the junction interface. The arrows shown over the Fermi energy of the ferromagnetic source  3  and the ferromagnetic drain  5  indicate the direction of majority spins. An upward arrow indicates up spins, and a downward arrow indicates down spins. It should be noted that minority spins are not shown in the drawings. In the following cases where ferromagnetic metal is used, the direction of the majority spins is shown in the band structure. 
       FIG. 2B  shows the energy band structure in the vicinity of the channel region of a MISFET of the inversion n-channel type in the case where a ferromagnetic metal is used for the ferromagnetic source and the ferromagnetic drain. The ferromagnetic source  3  and the ferromagnetic drain  5  made of the ferromagnetic metal and the p-type semiconductor layer  1  form a Schottky junction. The height of the barrier of the Schottky junction between the ferromagnetic metal and the p-type semiconductor is denoted by φ p , which represents the energy difference between the Fermi energy E F  and the energy E V  at the top of the valence band of the p-type semiconductor layer  1  on the junction interface. The energy difference between the Fermi energy E F  and the energy E C  at the bottom of the conduction band of the p-type semiconductor layer  1  on the junction interface is denoted by φ n . 
     Next, a MISFET in accordance with a second embodiment of the present invention is described, with reference to the accompanying drawings. 
       FIG. 3A  illustrates a MISFET in accordance with this embodiment, and shows the energy band structure in the vicinity of the channel region of a MISFET of the accumulation n-channel type in the case where a half metal is used for the ferromagnetic source and the ferromagnetic drain. A half metal exhibits a metallic band structure (hereinafter referred to as the “metallic spin band”) for one direction of spins, while exhibiting a semiconductor (or insulating) band structure (hereinafter referred to as the “semiconductor spin band”) for the opposite spins. With a half metal, a half-occupied band for one spin is provided, and a fully-occupied band (a valence band) is separated for the other spin from an empty band (a conduction band) by a band gap. Accordingly, the Fermi energy E F  crosses the metallic spin band of one spin, but crosses the band gap with respect to the other spin. The carrier conduction is realized only by the spin belonging to the metallic spin band. 
     In  FIG. 3A , the solid line shown in the middle of each of a ferromagnetic source  3   a  and a ferromagnetic drain  5   a  indicates the Fermi energy E F . Accordingly, E F  also represents the Fermi surface of the metallic spin band. The solid lines E C   HM  and E V   HM  represent the bottom of the conduction band in the semiconductor spin band and the top of the valence band, respectively. The band gap of the semiconductor spin band of the half metal ( 3   a ,  5   a ) is denoted by E G   HM . In the case where a MISFET of the accumulation n-channel type is formed with the half metal ( 3   a ,  5   a ), the metallic spin band of the half metal ( 3   a ,  5   a ) and the n-type semiconductor layer  1  need to form a Schottky junction with a barrier height φ n . With the junction, the bottom of the conduction band of the semiconductor spin band of the half metal ( 3   a ,  5   a ) exhibits higher energy than the bottom of the conduction band of the n-type semiconductor layer  1 , and preferably forms an energy discontinuity ΔE C  at the interface. 
     An energy discontinuity ΔE V  represents the energy difference between the energy at the top of the valence band of the semiconductor spin band in the half metal ( 3   a ,  5   a ) and the energy at the top of the valence band of the n-type semiconductor layer  1  at the junction interface. In the following cases, the energy discontinuities at the junction interface between the semiconductor layer  1  and the conduction and valence bands in the semiconductor spin band are denoted by ΔE C  and ΔE V  in the case where a half metal is employed for the ferromagnetic source and the ferromagnetic drain. 
     In the drawing, the Fermi energy of non-magnetic contacts  3   b  and  5   b  joined to the ferromagnetic source  3   a  and the ferromagnetic drain  5   a  made of the half metal is also shown. Accordingly, in the case of employing a half metal, the ferromagnetic source  3  is formed with the ferromagnetic source  3   a  and the non-magnetic contact  3   b . The same applies to the ferromagnetic drain. Hereinafter, if the ferromagnetic source  3  and the ferromagnetic drain  5  are described without specifying whether they are made of a ferromagnetic metal or a half metal, the ferromagnetic source  3  and the ferromagnetic drain  5  include the ferromagnetic source  3   a  and the ferromagnetic drain  5 . The energy difference between the Fermi energy E F  of the non-magnetic contacts  3   b  and  5   b  and the conduction band E C   HM  in the semiconductor spin band is denoted by φ n ′. 
       FIG. 3B  shows the energy band structure in the vicinity of the channel region of a MISFET of the inversion n-channel type in the case where a half metal is used for the ferromagnetic source and the ferromagnetic drain. 
     The ferromagnetic source  3   a  and the ferromagnetic drain  5   a  need to be formed by Schottky junction the p-type semiconductor layer  1  to the metallic spin band of the half metal. The height of the Schottky junction barrier between the metallic spin band of the half metal ( 3   a ,  5   a ) and the p-type semiconductor layer  1  is denoted by φ p . The energy difference between the Fermi energy E F  in the half metal ( 3   a ,  5   a ) and the energy E C  at the bottom of the conduction band of the p-type semiconductor layer  1  at the junction interface is denoted by φ n . The bottom of the conduction band of the semiconductor spin band of the half metal ( 3   a ,  5   a ) exhibits higher energy than the bottom of the conduction band of the p-type semiconductor layer  1 , and preferably forms an energy discontinuity ΔE C  at the interface. 
     The difference between the Fermi energy and the energy E C   HM  at the bottom of the conduction band of the semiconductor spin band in the half metal ( 3   a ,  5   a ) is denoted by φ n ′. The difference between the Fermi energy and the energy E V   HM  at the top of the valence band of the semiconductor spin band in the half metal ( 3   a ,  5   a ) is denoted by φ p ′. 
     In the following, the principles of the operation of each MISFET in accordance with this embodiment are described, with reference to the accompanying drawings. In each MISFET in accordance with this embodiment, the ferromagnetic source functions as a spin injector that inject spins to the channel, while the ferromagnetic drain functions as a spin analyzer that detects, as en electric signal, the orientation of the spins of conduction carriers injected to the channel. In each MISFET in accordance with this embodiment, it is possible to employ either a ferromagnetic metal or a half metal for the ferromagnetic source and the ferromagnetic drain, as described above. Further, it is possible to use a ferromagnetic metal for one of the ferromagnetic source and the ferromagnetic drain, and a half metal for the other one of the ferromagnetic source and the ferromagnetic drain. 
     Hereinafter, the situation in which the relative magnetization direction of the ferromagnetic drain is the same as that of the ferromagnetic source will be referred to as “parallel magnetization”, and the situation in which the relative magnetization direction of the ferromagnetic drain is opposite to that of the ferromagnetic source will be referred to as “antiparallel magnetization”. The channel length of each MISFET is sufficiently shorter than the spin relaxation length, and the Rashba effect due to a gate voltage should be ignored. 
     Referring now to  FIGS. 4A through 4D , the principles of the operation of a MISFET of the accumulation n-channel type using a ferromagnetic metal for the ferromagnetic source and the ferromagnetic drain are described.  FIG. 4A  shows an energy band structure in the parallel state, and corresponds to  FIG. 2A . 
     In the parallel state shown in  FIG. 4A , a bias V GS  (=0) is applied between the ferromagnetic source  3  and the gate electrode  7 , and a bias V DS  is applied between the ferromagnetic source  3  and the ferromagnetic drain  5 . The bias V DS  is then divided between the Schottky junction of the ferromagnetic source  3  and the Schottky junction of the ferromagnetic drain  5 , and accordingly, the potential shown in  FIG. 4B  is obtained. The Schottky junction of the ferromagnetic drain  5  is forward-biased, and the height of the Schottky barrier on the drain side, seen from the bottom of the conduction band of the center portion of the channel, decreases (or disappears). On the other hand, the Schottky junction of the ferromagnetic source  3  is reverse-biased, and the height of the Schottky barrier on the source side, seen from the bottom of the conduction band of the center portion of the channel, increases. Here, the bias V DS  is applied in such a manner that the Fermi energy E F  crosses the band edge of the Schottky barrier on the source side, but the bias V DS  is of such a size as to hardly cause a current through a tunneling effect. Accordingly, the distance d between the Schottky junction interface on the source side and the crossing point of the Fermi energy of the ferromagnetic source  3  and the band edge of the Schottky barrier is adequately thick so that a carrier tunneling effect is not caused in the channel from the ferromagnetic source  3 . Since the Schottky junction on the source side is reverse-biased, a current almost equivalent to a reverse saturation current of the Schottky junction due to the carriers thermally beyond the barrier with a height φ n  is generated from the ferromagnetic source  3 . However, the current can be sufficiently restricted and made smaller by properly adjusting the height φ n . Accordingly, the MISFET is put into a shut-off state, when the bias V GS  is 0. 
     Next, the bias V GS  (&gt;0) is applied to the gate electrode  7 . The electric field in the vicinity of the Schottky barrier on the source side is intensified by the line of electric force directed from the gate electrode  7  to the ferromagnetic source  3 . The width of the Schottky barrier decreases as shown in  FIG. 4C  (indicated by d′). Accordingly, the conduction electrons of the ferromagnetic source  3  pass through the potential barrier by virtue of a tunneling effect, and are injected to the channel region immediately below the gate insulating film  11 . At this point, majority spins and minority spins are injected from the ferromagnetic source  3 . Since the carrier density of the majority spins is higher than that of the minority spins, the injected electrons are spin-polarized. The spin polarization rate of the injected electrons depends on the spin polarization rate in the vicinity of the Fermi energy. As the spin polarization rate in the vicinity of the Fermi energy becomes higher, the spin polarization rate of the injected electrons becomes higher. 
     Hereinafter, electrons that are spin-polarized will be referred to as spin-polarized electrons. The majority spins and the minority spins of spin-polarized electrons are in parallel with the majority spins and the minority spins of the ferromagnetic source  3 . The spin-polarized electrons injected to the channel are transported to the Schottky barrier interface of the ferromagnetic drain  5  by virtue of the bias V DS , while being attracted toward the interface between the gate insulating film and the semiconductor by virtue of the bias V GS . In the case where the ferromagnetic source  3  and the ferromagnetic drain  5  exhibit a parallel magnetization configuration, the majority spins and the minority spins of spin-polarized electrons are in parallel with the majority spins and the minority spins of the ferromagnetic drain  5 . Accordingly, the spin-polarized electrons injected to the ferromagnetic drain  5  pass through the ferromagnetic drain  5 , and become a current flowing into the ferromagnetic drain (hereinafter, the current will be referred to as “drain current”), without adverse influence of spin-dependent diffusion. Particularly, in the case where the ferromagnetic source  3  and the ferromagnetic drain  5  are in a parallel magnetization configuration, the bias V GS  of a predetermined drain current is set as a threshold voltage V T . 
     On the other hand, in a case where the ferromagnetic source  3  and the ferromagnetic drain  5  are in an antiparallel magnetization configuration, the majority spins among spin-polarized electrons injected to the channel are in antiparallel with the majority spins of the ferromagnetic drain  5  (see  FIG. 4D ). Accordingly, the spin-polarized electrons of the channel cause electric resistance due to spin-dependent scattering in the ferromagnetic drain  5 . Therefore, even if the MISFET has a uniform bias, the drain current becomes smaller due to the spin-dependent scattering in the antiparallel magnetization configuration, compared with the case of parallel magnetization. In short, the transmission (mutual) conductance in the case where the relative magnetization between the ferromagnetic source  3  and the ferromagnetic drain  5  is in an antiparallel state is smaller than that in the case where the relative magnetization is in a parallel state. If the channel length is equal to or shorter than the mean free path with respect to the carrier energy relaxation, the carriers in the channel are conducted in a ballistic manner. Therefore, a magnetoresistive effect that is similar to a tunneling magnetoresistive effect can be expected. In such a case, the variation in tarns-conductance becomes even wider between the parallel magnetization and the antiparallel magnetization. 
       FIGS. 5A through 5D  illustrate the principles of the operation of an inversion n-channel MISFET having the ferromagnetic source  3  and the ferromagnetic drain  5 . When the bias V DS  (&gt;0) is applied in a parallel magnetization configuration (see  FIG. 5A ), with the bias V GS  being 0, the ferromagnetic source  3  is forward-biased as shown in  FIG. 5B , and the ferromagnetic drain  5  is reverse-biased. Since the channel region is of p type, a current is generated when holes are injected from the ferromagnetic drain  5 . However, few holes are injected due to the reverse-biased Schottky junction of the ferromagnetic drain  5 . Although a low current of a size almost equal to the reverse saturation current of the Schottky junction formed by the holes thermally beyond φ p  is generated, this current can be sufficiently reduced by properly adjusting φ p . Accordingly, the MISFET is put into a shut-off state, with the bias V GS  being 0. 
     When a bias V GS  (&gt;V T ) greater than a certain threshold voltage V T  determined from the device structure is applied to the gate electrode  7  (shown in  FIG. 1 ), electrons are induced at the interface between the gate insulating film and the semiconductor, thereby forming an inversion layer (although the threshold voltage V T  differs between the inversion channel type and the accumulation channel type, the threshold voltage is denoted by V T  in either case, for ease of explanation). At this point, a barrier with a height φ p  against the electrons in the inversion layer is formed at each junction interface with the ferromagnetic source  3  and the ferromagnetic drain  5  in the channel region. However, the junction of the ferromagnetic drain  5  and the junction of the ferromagnetic source  3  are biased with the bias V DS , as shown in  FIG. 5C . 
     As described above, by selecting a sufficiently large height φ p , the height φ n  (=E G −φ p ) is made small, and spin-polarized electrons are injected to the channel due to heat radiation from the ferromagnetic source  3 . Also, even if the height φ n  is not so small as to thermally discharge the carriers from the ferromagnetic source  3 , the Schottky barrier on the side of the ferromagnetic source  3  is tunneled to inject spin-polarized electrons from the ferromagnetic source  3  to the channel, as in the case of the accumulation channel type. 
     The spin-polarized electrons injected to the channel are transported to the Schottky barrier interface on the side of the ferromagnetic drain  5  by the bias V DS . In the case where the ferromagnetic source  3  and the ferromagnetic drain  5  are in the parallel magnetization configuration, the majority spins and the minority spins of the spin-polarized electrons are in parallel with the majority spins and the minority spins of the ferromagnetic drain  5 . Accordingly, in the case of parallel magnetization, the spin-polarized electrons injected to the ferromagnetic drain  5  pass through the ferromagnetic drain  5  and become a drain current, without adverse influence of spin-dependent scattering, as in the case of the accumulation channel type. 
     Meanwhile, in the case where the ferromagnetic source  3  and the ferromagnetic drain  5  are in the antiparallel magnetization configuration as shown in  FIG. 5D , the majority spins of the spin-polarized electrons injected to the channel are in antiparallel with the majority spins of the ferromagnetic drain  5 . Accordingly, the spin-polarized electrons cause electric resistance due to spin-dependent scattering in the ferromagnetic drain  5 . In this manner, the tarns-conductance of a MISFET of the inversion channel type also varies depending on the relative magnetization between the ferromagnetic source  3  and the ferromagnetic drain  5 . Even with the same bias, the drain current in the case where the ferromagnetic source  3  and the ferromagnetic drain  5  are in an antiparallel magnetization configuration becomes lower than that in the case of parallel magnetization. Also, if the channel length is equal to or shorter than the mean free path with respect to the carrier energy relaxation, a magnetoresistive effect that is similar to a tunneling magnetoresistive effect can be expected. In such a case, the variation in tarns-conductance becomes even wider between the parallel magnetization and the antiparallel magnetization. 
     Next, a case where a half metal is used as a ferromagnetic body is described. Referring to  FIGS. 6A through 6D , the principles of the operation of a MISFET of the accumulation n-channel type in the case where a half metal is used for the ferromagnetic source and the ferromagnetic drain are described.  FIG. 6A  shows the energy band structure in a parallel magnetization configuration, and corresponds to  FIG. 3A . 
       FIG. 6B  shows the potential shape in a case where a bias V DS  (&gt;0) is applied, with a bias V GS  being 0. Hereinafter, the spins belonging to the metallic spins band of the ferromagnetic source  3   a  will be referred to as “up spins”, while the spins belonging to the semiconductor spins band will be referred to as “down spins”. For the up spins belonging to the metallic spin band, a Schottky junction with a height of φ n  is formed at the junction interface with the semiconductor layer  1 , and the bias V DS  is divided between the source-side Schottky junction and the drain-side Schottky junction. Accordingly, the Schottky junction of the ferromagnetic drain  5   a  is forward-biased, while the Schottky junction of the ferromagnetic source  3   a  is reverse-biased. At this point, the bias V DS  is applied in such a manner that the Fermi energy E F  of the ferromagnetic source  3   a  crosses the band edge of the source-side Schottky barrier, but the barrier width d of the Schottky junction is made so thick that the up spins are not tunneled from the metallic spin band of the ferromagnetic source  3   a . With the V GS  being 0, tunnel injection of the up spins in the metallic spin band of the ferromagnetic source  3   a  is restricted in the channel region. Also, the up spins can be injected as a reverse saturation current of the Schottky junction caused by holes thermally beyond the barrier height φ n  of the Schottky junction. However, the current can be made sufficiently lower by properly adjusting the value of φ n . 
     Meanwhile, the band gap of the semiconductor spin band of the ferromagnetic source  3   a  having down spins forms an energy barrier with a height φ n ′ between the semiconductor spins band of the ferromagnetic source  3   a  and the non-magnetic contact  3   b . Since no conduction carriers exist in the semiconductor spin band of the ferromagnetic source  3   a , the down spins tunnels the semiconductor spin band of the ferromagnetic source  3   a  from the non-magnetic contact  3   b , or thermally go beyond the barrier, so as to inject the down spins to the semiconductor layer  1 . The ferromagnetic source  3   a  is made sufficiently thick, and the height φ n ′ of the energy barrier, seen from the non-magnetic metal electrode  3   b , is made sufficiently large, so that the probability of the down spins being injected to the channel region can be made very low, and carriers are not injected. Accordingly, with the bias V GS  being 0, a current due to up spins and down spins is hardly generated, and the MISFET is put into a shut-off state. 
     When a bias V GS  (&gt;0) is applied to the gate electrode  7  (shown in  FIG. 1 ), the electric field in the vicinity of the Schottky barrier on the source side is intensified by the electric flux line directed from the gate electrode  7  to the ferromagnetic source  3   a , as shown in  FIG. 6C . The width of the Schottky barrier then decreases as shown in  FIG. 6C  (indicated by d′). Accordingly, the up spins from the metallic spin band of the ferromagnetic source  3   a  tunnel the Schottky barrier, and are injected to the channel region in the semiconductor layer  1  immediately below the gate insulating film. Here, the down spins from the non-magnetic contact  3   b  are hardly injected due to the energy barrier with a height φ n ′ of the semiconductor spin band of the ferromagnetic source  3   a . Therefore, the ferromagnetic source  3   a  made of a half metal selectively injects up spins. 
     The up spins injected to the channel are transported to the Schottky barrier interface of the ferromagnetic drain  5   a  by virtue of the bias V DS . In the case where the ferromagnetic source  3   a  and the ferromagnetic drain  5   a  exhibit parallel magnetization, the injected up spins are in parallel with the spins in the metallic spins band of the ferromagnetic drain  5   a . Accordingly, the up spins injected to the ferromagnetic drain  5   a  pass through the ferromagnetic drain  5   a , and become a drain current, without adverse influence of spin-dependent diffusion. Particularly, in the case where the ferromagnetic source  3   a  and the ferromagnetic drain  5   a  exhibit parallel magnetization, the bias V GS  that generates a predetermined drain current is set as a threshold voltage V T . 
     On the other hand, in a case where the ferromagnetic source  3   a  and the ferromagnetic drain  5   a  exhibit antiparallel magnetization, the up spins injected to the channel are in antiparallel with the spins in the metallic spin band of the ferromagnetic drain  5   a , but are in parallel with the spins in the semiconductor spin band, as shown in  FIG. 6D . Accordingly, the up spins injected to the channel sense the ferromagnetic drain  5   a  as the energy barrier with a height of ΔE C . The film thickness of the ferromagnetic drain  5   a  and the height ΔE C  are adjusted so that the up spins in the channel cannot tunnel the barrier or cannot thermally go beyond the barrier. In this manner, the up spins injected from the non-magnetic source electrode  3   b  can hardly pass through the ferromagnetic drain  5   a , and a drain current is hardly generated. Thus, the half metal of the ferromagnetic drain  5   a  transmits only the spins in parallel with the spins in the metallic spin band, but does not transmit the spins in antiparallel with the spins in the metallic spins band. 
     From the ferromagnetic source  3   a  made of a half metal, spin-polarized electrons with a very high spin polarization rate can be injected to the channel. Also, since the spin selection rate of the ferromagnetic drain  5   a  made of a half metal is very high, the drain current in the case where the ferromagnetic source  3   a  and the ferromagnetic drain  5  are in an antiparallel magnetization configuration is much lower than the drain current in the case of parallel magnetization. Accordingly, using a half metal, the difference can be made very large between the drain current in the case where the relative magnetization state of the ferromagnetic source  3   a  and the ferromagnetic drain  5   a  exhibits parallel magnetization, and the drain current in the case of antiparallel magnetization, compared with a case of using a regular ferromagnetic metal. 
     Next, Referring to  FIGS. 7A through 7D , the principles of the operation of a MISFET of the inversion n-channel type in the case where a half metal is used for the ferromagnetic source and the ferromagnetic drain are described. In the following, the spins belonging to the metallic spin band of the ferromagnetic source  3   a  made of a half metal will be referred to “up spins”, while the spins belonging to the semiconductor spin band will be referred to “down spins”. 
       FIG. 7A  shows the energy band structure in a parallel magnetization configuration, and corresponds to  FIG. 3B . In a case where a bias V DS  is applied, with a bias V GS  being 0, a current is generated in the MISFET when holes are injected from the drain side, as the semiconductor layer  1  is a p-type semiconductor. However, the Schottky junction by the metal spin band of the half metal of the ferromagnetic drain  5   a  is reverse-biased, and hole injection is restricted. Although a current almost the same size as the reverse saturation current of the Schottky junction is generated, it can be made sufficiently lower by properly adjusting φ p . 
     Also, hole injection from the drain-side non-magnetic contact  5   b  is also restricted by the energy barrier φ p ′ of the semiconductor spin band of the ferromagnetic drain  5   a . Thus, the MISFET is put into a shut-off state in the case shown in  FIG. 7B . 
     When a bias V GS  greater than the threshold voltage V T  is applied to the gate electrode  7 , electrons are induced at the interface between the gate insulating film and the semiconductor, thereby forming an inversion layer (the threshold voltage V T  differs between the inversion channel type and the accumulation channel type). At this point, a barrier with a height φ n  is formed with the metallic spin band made of a half metal at each junction interface between the inversion layer and the ferromagnetic source  3   a  and the ferromagnetic drain  5   a , as shown in  FIG. 7C . 
     By applying the bias V DS , the junctions of the ferromagnetic drain  5   a  and the ferromagnetic source  3   a  are biased as shown in  FIG. 7C . By selecting a sufficiently large height φ p , the height φ n  (=E G −φ p ) is made small, and up spins are injected to the channel due to thermal emission from the metallic spin band of the ferromagnetic source  3   a . Also, even if the height φ n  is not so small as to thermally inject up spins from the ferromagnetic source  3   a , the up spins can be tunnel-injected from the metallic spin band of the ferromagnetic source  3   a  to the channel as in the case of the accumulation channel type. On the other hand, the down spins in the semiconductor spin band of the ferromagnetic source  3   a  are hardly injected. 
     The up spins injected to the channel are transported to the junction interface on the drain side by the bias V DS . In the case where the ferromagnetic source  3   a  and the ferromagnetic drain  5   a  exhibit parallel magnetization, the up spins injected to the channel are in parallel with the spins in the metallic spin band of the ferromagnetic drain  5   a . Accordingly, in the case of parallel magnetization, the up spins pass through the metallic spin band of the ferromagnetic drain  5  and become a drain current. 
     On the other hand, in a case where the ferromagnetic source  3   a  and the ferromagnetic drain  5   a  exhibit antiparallel magnetization, the up spins injected to the channel are in antiparallel with the spins in the metallic spin band of the ferromagnetic drain  5   a , but are in parallel with the spins in the semiconductor spin band of the ferromagnetic drain  5   a , as shown in  FIG. 7D . Accordingly, the up spins injected to the channel sense the ferromagnetic drain  5   a  as the energy barrier with a height of ΔE C . The film thickness of the ferromagnetic drain  5   a  and the height ΔE C  are adjusted so that the up spins in the channel cannot tunnel the barrier or cannot thermally go beyond the energy barrier with a height of ΔE C . In this manner, drain current components are hardly generated. 
     As described above, the half metal of the ferromagnetic drain  5   a  transmits only the spins that are in parallel with the spins in the metallic spin band. Accordingly, the tarns-conductance can be controlled depending on the relative magnetization state between the ferromagnetic source  3   a  and the ferromagnetic drain  5   a . Thus, the drain current in the case where the ferromagnetic source  3   a  and the ferromagnetic drain  5   a  exhibit antiparallel magnetization is lower than that in the case of parallel magnetization. 
     In the above described MISFET that has a ferromagnetic source ( 3  or  3   a ) and a ferromagnetic drain  5  ( 5  or  5   a ) made of a ferromagnetic metal or a half metal, the semiconductor layer  1  may be replaced with an undoped semiconductor or an intrinsic semiconductor. In such a case, the barrier structure formed with the junctions caused between the ferromagnetic metal and the semiconductor differs from a Schottky barrier, but the same MISFET operation can be expected with this barrier structure. In this MISFET, the channel region is formed with an intrinsic semiconductor. Accordingly, adverse influence of impurity scattering is not seen in the channel region, and higher mobility of conduction carriers can be expected. Particularly, in a MISFET with a nanoscale short channel, ballistic conduction of carriers that are effective for high-speed operations can be expected. Also in this MISFET, a variation in threshold voltage is not basically caused, even in a case where scale-downed MISFETs with small threshold voltages are highly integrated. Furthermore, a channel formed with an intrinsic semiconductor is suitable for a SOI structure. Accordingly, with an intrinsic semiconductor used for a channel region, the performance of the MISFET of the present invention and the performance of a non-volatile memory (described later) in which the MISFET is employed can be further increased. 
     Next, a MISFET in accordance with a third embodiment of the present invention is described in conjunction with the accompanying drawings. In a MISFET in accordance with this embodiment, the ferromagnetic source and the ferromagnetic drain form Schottky junctions with a semiconductor layer and a thin metal layer with a height desired for a barrier. A ferromagnetic metal or a half metal is formed on the metal layer.  FIG. 12  shows an energy band structure of a MISFET in accordance with this embodiment. As shown in  FIG. 12 , the MISFET in accordance with this embodiment has ferromagnetic metal members  23  and  25  as a source and a drain, and thin metal layers  23   a  and  25   a  introduced at the interfaces between a semiconductor layer and the ferromagnetic metal members  23   a  and  25   a . The thin metal layers  23   a  and  25   a  are used to control the barrier height. Schottky junctions of the metal layers  23   a  and  25   a  and the semiconductor layer  21  with which a desired barrier height φ n  can be obtained are first formed, and the ferromagnetic metal layers  23  and  25  are formed on the metal layer  23   a  and  25   a , respectively. The specific example of the materials for the metal layers  23   a  and  25   a  include silicides such as ErSi x  or PtSi x , with the Si being the semiconductor layer  21 . 
     As in the structure shown in  FIG. 12 , the Schottky barrier height can also be controlled with a structure in which the ferromagnetic metal layers  23  and  25  are replaced with the half metal employed in the second embodiment, or a MISFET having a half-metal ferromagnetic source and a half-metal ferromagnetic drain. Such a structure can also be provided in accordance with the present invention. Alternatively, another semiconductor with which a desired Schottky barrier height at the interface with the ferromagnetic metal or the half metal may be inserted at the interface between the semiconductor layer and the ferromagnetic metal or the half metal. To control the Schottky barrier height, a metal/semiconductor heterostructure may also be inserted at the interface between the semiconductor layer and the ferromagnetic metal or the half metal. 
     By the above described technique, the material for the ferromagnetic source and the ferromagnetic drain can be arbitrarily selected, regardless of the Schottky height between the semiconductor layer and the ferromagnetic metal or the half metal. 
     Next, a MISFET in accordance with a fourth embodiment of the present invention is described in conjunction with the accompanying drawings. In the first through third embodiments, the ferromagnetic source and the ferromagnetic drain are formed with Schottky junctions of a ferromagnetic metal or a half metal. The MISFET in accordance with this embodiment, on the other hand, has a ferromagnetic source and a ferromagnetic drain made of ferromagnetic semiconductors. With this structure, the same effects as those of the MISFETs of the first through third embodiments can be expected, without Schottky junctions. 
     As shown in  FIG. 13A , for example, the MISFET has an intrinsic semiconductor  31  used as a channel region, and also has a gate insulator  41  and a gate (electrode)  37  stacked on the intrinsic semiconductor  31 . In this MISFET, n-type ferromagnetic semiconductors are used for a ferromagnetic source  33  and a ferromagnetic drain  35 , so as to form an n-channel MISFET that can exhibit the same characteristics as those of any of the MISFETs (the MISFET shown in  FIG. 2A , for example). To produce a p-channel MISFET, p-channel ferromagnetic semiconductors should be used for the ferromagnetic source and the ferromagnetic drain. 
     Next, a MISFET in accordance with a fifth embodiment of the present invention is described in conjunction with the accompanying drawings. The MISFET in accordance with this embodiment has a ferromagnetic source and a ferromagnetic drain formed with pn junctions between a semiconductor and ferromagnetic semiconductors (in this case, the MISFET operates as an inversion channel type). As shown in  FIG. 13B , for example, n-type ferromagnetic semiconductors are used for a source  53  and a drain  55 , and a p-type semiconductor is used for a semiconductor layer  51  that includes the channel region. In this structure, a gate insulating film  61  and a gate (electrode)  57  are also stacked on the p-type semiconductor layer  51 . Likewise, p-type ferromagnetic semiconductors may be used for the source and the drain, while an n-type semiconductor is used for the channel region. 
     As described in the fourth and fifth embodiments of the present invention, even in a where the ferromagnetic source and the ferromagnetic drain are formed with ferromagnetic semiconductors, the drain current differs between parallel magnetization and antiparallel magnetization, due to the spin-dependent scattering at the drain. Also, if the channel length is shorter than the mean free path with respect to the carrier energy relaxation, spin-dependent conduction that is similar to a tunneling magnetoresistive effect can be obtained from the ballistic conduction of the carriers. In such a case, the variation in tarns-conductance between parallel magnetization and antiparallel magnetization can be made wider. 
     Examples of the ferromagnetic semiconductors used for the MISFETs in accordance with the fourth and fifth embodiments include those with transition metal elements or rare-metal elements such as Mn and Cr incorporated into semiconductors of Si, Ge, Si x Fe 1-x , or SiC. 
     Next, examples of output characteristics of the MISFETs in accordance with the above described embodiments are described.  FIG. 8  shows the V DS  dependence of a drain current ID, with V GS  being a parameter. Whether a ferromagnetic metal or a half metal is used for the ferromagnetic source  3  and the ferromagnetic drain  5  in the MISFET in accordance with this embodiment, and whether the MISFET is of the inversion channel type or the accumulation channel type, the MISFET is put into a shutoff state when a voltage equal to or lower than a predetermined threshold voltage V T  determined from the device structure is applied to the gate electrode  7 . The state of the MISFET does not depend on the relative magnetization state between the ferromagnetic source  3  and the ferromagnetic drain  5 . 
     A voltage V 1  (&gt;V T ) equal to or higher than the threshold voltage is applied to the gate electrode  7 , so that the transistor can be put into a conductive state. Here, the drain current I D  generated between the ferromagnetic source  3  and the ferromagnetic drain  5  varies depending on the relative magnetization state of the ferromagnetic drain  5  with respect to the ferromagnetic source  3 . With the same bias being applied, the drain current I D  is higher (I D↑↑  in  FIG. 8 ) in the case of parallel magnetization, and the drain current I D  is lower (I D↑↓  in  FIG. 8 ) in the case of antiparallel magnetization. In other words, the transmission (mutual) conductance of the MISFET is controlled by adjusting the magnetization state between the ferromagnetic source  3  and the ferromagnetic drain  5 . Accordingly, in the MISFET of this embodiment, the drain current I D  can be controlled by adjusting the voltage to be applied to the gate electrode  7 , and the tarns-conductance depends on the relative magnetization state of the ferromagnetic drain  5  with respect to the ferromagnetic source  3 . 
     A ferromagnetic body can maintain a magnetization direction unless a magnetic field greater than its coercive force is applied from the outside. Accordingly, in the MISFET in accordance with this embodiment, binary information can be stored in accordance with the relative magnetization state between the ferromagnetic source and the ferromagnetic drain to parallel magnetization or antiparallel magnetization. 
     In the above described MISFET, the relative magnetization state between the ferromagnetic source and the ferromagnetic drain can be electrically sensed based on the size of the drain current or the tarns-conductance. Accordingly, the above described MISFET alone can form a 1-bit non-volatile memory cell. 
       FIG. 9A  illustrates an example structure of a memory circuit that employs MISFETs in accordance with this embodiment. In the memory circuit shown in  FIG. 9A , MISFETs are arranged in a matrix fashion. In each MISFET, a source terminal S is grounded while a drain terminal D and a gate terminal G are respectively connected to a read bit line BL and a read word line WL. Also, a rewrite word line and a rewrite bit line are arranged to cross each other, while being electrically insulated from the other lines in the MISFET. The read bit line BL and the read word line WL may also serve as the rewrite bit line and the rewrite word line.  FIG. 9A  shows the cell structure in the case where the read bit line BL and the read word line WL also serve as the rewrite bit line and the rewrite word line. In the example shown in  FIG. 9A , each MISFET alone can form a memory cell, and a very simple line arrangement can be employed. 
     A conventional MRAM memory cell includes one MTJ, one MISFET, and four lines (see  FIG. 10 ). In this structure, it is difficult to reduce the cell area by sharing a source between adjacent cells, due to the existence of the MTJ and a rewrite word line. On the other hand, a memory cell in accordance with this embodiment has a simplest structure that is formed with one MISFET and three lines, as shown in  FIG. 9A . With such memory cells, a layout suitable for a small-sized memory can be readily employed. 
     For example, it is possible to form a structure in which one ferromagnetic source is shared between two MISFETs of this embodiment.  FIG. 11  is a cross-sectional view of a memory cell with the shared source structure. The memory cell shown in  FIG. 11  includes a first MISFET and a second MISFET that are adjacent to each other, a word line WL that connects the gate electrode G 1  of the first MISFET and the gate electrode G 2  of the second MISFET, a first bit line BL 1  that is connected to the first ferromagnetic drain D 1  of the first MISFET, a second bit line BL 2  that is connected to the second ferromagnetic drain D 2  of the second MISFET, a ferromagnetic source S that is shared between the first and second MISFETs, and a line for grounding the ferromagnetic source S. Since the source is shared in this structure, a cell structure that is more suitable for a high-density memory can be formed. 
     In the following, the operation of a memory cell is described in conjunction with  FIG. 9A . The above described rewrite/read bit line and the rewrite/read word line that are shared are referred to simply as the bit line BL and the word line WL. To rewrite information, the coercive force of the ferromagnetic source  3  or the ferromagnetic drain  5  is changed, of the relative magnetization direction of the ferromagnetic drain  5  with respect to the ferromagnetic source  3  is adjusted to either parallel magnetization or antiparallel magnetization in the MISFET in accordance with this embodiment. For example, parallel magnetization and antiparallel magnetization are represented by the binary information of “0” and “1”, respectively. More specifically, a current is applied to the bit line BL and the word line WL that crosses each other on the selected memory cell, and information is stored by inverting the magnetization of the ferromagnetic body with smaller coercive force or the ferromagnetic body without a fixed magnetization direction of the memory cell selected by a compound magnetic field induced by the current flowing through the respective lines. Here, the value of the current to be applied to the respective lines should be determined so as not to cause magnetization inversion with a magnetic field induced only from one of the lines. Thus, the unselected cells connected to the bit line BL or the word line WL to which the selected cell is also connected can be protected from magnetization inversion. 
     To read information, a voltage is applied to the word line WL connected to the selected cell, so as to energize the MISFET of this embodiment. A drain voltage is then applied to the bit line BL, so as to detect the size of the drain current I D . In the MISFET in accordance with this embodiment, in the case where the relative magnetization state of the ferromagnetic drain with respect to the ferromagnetic source exhibits parallel magnetization, the tarns-conductance is great, and a high drain current I D  is generated. In the case of antiparallel magnetization, on the other hand, the tarns-conductance is small, and the drain current I D  is low. Based on the size of the drain current I D , the relative magnetization between the ferromagnetic source and the ferromagnetic drain can be detected. Alternatively, the detection may be carried out by applying a necessary bias through precharging. 
     In a regular MTJ, the current in the case of parallel magnetization is generated by the tunneling between the state densities of the majority spins in the two ferromagnetic electrodes, and the tunneling between the state densities of the minority spins in the two ferromagnetic electrodes. In the case of antiparallel magnetization, the current is generated by the tunneling from the state density of the minority spins to the state density of the majority spins, and the tunneling from the state density of the majority spins to the state density of the minority spins. Accordingly, the currents flowing in the case of parallel magnetization and antiparallel magnetization contains current components generated from minority spins. Therefore, it is not easy to increase the ratio of the current in the case of parallel magnetization to the current in the case of antiparallel magnetization. 
     In the MISFET having the ferromagnetic source and the ferromagnetic drain made of a half metal in accordance with this embodiment, on the other hand, only the spins belonging to the metallic spin band in the ferromagnetic source can be injected to the channel, due to the junction between the half metal and the semiconductor layer. Further, only the spins in parallel with the spins belonging to the metallic spin band in the ferromagnetic drain can be extracted and used as a drain current (hereinafter, this effect of a half metal will be referred to as the “spin filter effect”). 
     In the MISFET having the ferromagnetic source and the ferromagnetic drain made of a half metal in accordance with this embodiment, the current ratio (the drain current ratio) between parallel magnetization and antiparallel magnetization can be made higher than the current ratio that is obtained in a MTJ. Accordingly, with the MISFET in accordance with this embodiment, a magnetization state can be readily detected in the above described memory circuit. 
     Also, in the case where the ferromagnetic source and the ferromagnetic drain are made of a ferromagnetic metal, the spin polarization rate (the spin injection rate) of the carriers injected from the ferromagnetic source can be made higher than the spin polarization rate of the ferromagnetic metal by virtue of a strong field effect that is generated at the source-side Schottky barrier due to the gate bias. With such a strong field effect, the drain current ratio between parallel magnetization and antiparallel magnetization can be made higher than the current ratio in a MTJ. 
     With a conventional MTJ, there also has been the problem that the TMR ratio greatly decreases with a bias necessary in the circuit, as the TMR ratio rapidly drops with a decrease in bias voltage. In the MISFET in accordance with this embodiment, on the other hand, the spin-dependent scattering due to the ferromagnetic metal, or the spin filter effect due to the half metal is utilized. Therefore, the bias dependence that is seen in a conventional MTJ is not observed. Accordingly, a high drain current ratio can be achieved with a bias necessary for the circuit. 
       FIG. 9B  shows a memory circuit that has an output terminal V o  connected to the bit line end of the memory circuit of  FIG. 9A , and is connected to a supply voltage V DD  via a load R L  branching from the output terminal V o .  FIG. 9C  shows the static characteristics and operating points of the memory cell of  FIG. 9B . Here, a net resistance is used as a load, but it is also possible to use an active load formed with a transistor. As shown in  FIG. 9C , the gate voltage V GS  is applied to the gate electrode of the MISFET at the time of reading information, and the supply voltage V DD  is applied to the bit line BL via the load resistance R L . The operating point determined by the load resistance R L  moves on the load line shown in  FIG. 9C , in accordance with the magnetization state between the ferromagnetic source and the ferromagnetic drain. The output signals V o  in the cases of parallel magnetization and antiparallel magnetization can be represented by V o↑↑  and V o↑↓  shown in  FIG. 9C . The absolute values and the ratio (V o↑↑ /V o↑↓ ) of the output signals can be optimized with the external circuit parameters such as R L  and V DD . For example, in a case where the drain current ratio I D↑↑ /I D↑↓  is small, a large output signal ratio can be obtained by adjusting (reducing, in this case) the inclination of the load line. Thus, the memory circuit of this embodiment is advantageous in that output signals of desired size can be obtained. 
     As described so far, a MISFET having a ferromagnetic source and a ferromagnetic drain in accordance with any of the embodiments of the present invention functions as a transistor that can control the drain current by adjusting the gate voltage, and characteristically controls the transmission (mutual) conductance by adjusting the relative magnetization direction of the ferromagnetic drain with respect to the ferromagnetic source. The relative magnetization between the ferromagnetic source and the ferromagnetic drain can be maintained as it is, without energy supply. This feature is referred to as the non-volatile characteristics. Accordingly, binary information can be stored in a non-volatile manner in accordance with the relative magnetization direction between the ferromagnetic source and the ferromagnetic drain. Furthermore, with the above described transmission characteristics, the relative magnetization direction can be electrically detected. With the MISFET, one transistor alone can form a 1-bit non-volatile memory cell. Accordingly, with a MISFET of the present invention, a non-volatile memory cell can be readily formed. Thus, a more highly-integrated non-volatile memory circuit that can operate at a higher speed can be obtained. 
     Although the preferred embodiments of the present invention have been described, the present invention is not limited to those specific examples. It should be obvious to those skilled in the art that various changes and modifications can be made to the above described embodiments. For instance, any MISFET described in this specification can of course be applied to any memory device or memory circuit described in this specification. 
     INDUSTRIAL APPLICABILITY 
     In a MISFET of the present invention that has a ferromagnetic source and a ferromagnetic drain formed with Schottky junctions made of a ferromagnetic metal or a half metal, binary information can be stored in accordance with the relative magnetization direction of the ferromagnetic drain with respect to the ferromagnetic source, and the relative magnetization direction can be electrically detected. Accordingly, with such a MISFET, a single transistor alone can form a non-volatile memory cell. Thus, a high-speed, highly integrated non-volatile memory circuit can be realized.