Abstract:
A serial peripheral interface of an integrated circuit includes: a first transfer pin for receiving an instruction and an address; and a clock pin for inputting a plurality of timing pulses each having a rising edge and a falling edge. After the first transfer pin receives the instruction, the integrated circuit receives the address through the first transfer pin in continuity with the receipt of the instruction. The first transfer pin receives the instruction at either of the rising edges and the falling edges of the timing pulses and receives the address at both of the rising edges and falling edges of the timing pulses.

Description:
[0001]    This application is a continuation application of co-pending U.S. application Ser. No. 13/687,586, filed Nov. 28, 2012, which is a continuation application of co-pending U.S. application Ser. No. 13/362,801, filed Jan. 31, 2012, now U.S. Pat. No. 8,341,324, which is a continuation application of co-pending U.S. application Ser. No. 12/851,156, filed Aug. 5, 2010, now U.S. Pat. No. 8,135,896, which is a continuation application of co-pending U.S. application Ser. No. 11/896,846 filed Sep. 6, 2007, now U.S. Pat. No. 7,788,438. These related applications are incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The invention relates in general to a serial peripheral interface and a data transmitting method thereof, and more particularly to a serial peripheral interface having a better overall behavior and a data transmitting method thereof. 
         [0004]    2. Description of the Related Art 
         [0005]      FIG. 1  (Prior Art) is a block diagram showing a conventional data transmission system. Referring to  FIG. 1 , the data transmission system  100  includes an integrated circuit  110  and a serial peripheral interface  120 . The serial peripheral interface  120  has many pins, for example, including an input pin  122 , an output pin  124 , a chip select pin  126  and a clock pin  128 . The input pin  122  receives a piece of serial data, including instructions and addresses, and transmits the piece of serial data to the integrated circuit  110 . The output pin  124  reads a piece of serial data, including dummy cycles and multiple read out data, from the integrated circuit  110  and outputs the piece of serial data. The chip select pin  126  provides a chip select signal CS, and the clock pin  128  provides a clock signal SCLK. 
         [0006]      FIG. 2  (Prior Art) shows timings for reading serial data in the conventional data transmission system. As shown in  FIG. 2 , for example, the piece of serial data includes an 8-bit instruction, a 24-bit address, n dummy cycles and multiple 8-bit read out data, wherein n is an integer greater than or equal to 0 and is not particularly limited. It can be determined according to the design of data transmission system  100 . As shown in  FIG. 2 , when the chip select signal CS is low, the clock signal SCLK has many timing pulses. At this time, the input pin first receives the 8-bit instruction, and then receives the 24-bit address, which is the initial address of the data to be read. Then, n dummy cycles are provided for buffering. Next, the output pin reads and outputs the multiple 8-bit read out data. 
         [0007]    The data transmission system  100  utilizes one single input pin and one single output pin of the serial peripheral interface  120  to perform the serial data transmitting operation. Consequently, only one bit of data is transmitted in one timing pulse, and the efficiency is not high. So, the overall behavior of the data transmission system  100  cannot be optimized. 
       SUMMARY OF THE INVENTION 
       [0008]    The invention is directed to a serial peripheral interface and a data transmitting method thereof, in which many control pins of the serial peripheral interface are utilized to achieve a serial data transmission through multiple input pins and multiple output pins, and enhance the overall behavior of data transmission. 
         [0009]    According to an embodiment of the present invention, a serial peripheral interface of an integrated circuit is provided. The serial peripheral interface includes a first transfer pin for receiving an instruction and an address; and a clock pin for inputting a plurality of timing pulses each having a rising edge and a falling edge. After the first transfer pin receives the instruction, the integrated circuit receives the address through the first transfer pin in continuity with the receipt of the instruction. The first transfer pin receives the instruction at either of the rising edges and the falling edges of the timing pulses and receives the address at both of the rising edges and falling edges of the timing pulses. 
         [0010]    According to another embodiment of the present invention, a data transmitting method applied to a serial peripheral interface of an integrated circuit is provided. The serial peripheral interface includes a plurality of pins and a clock pin. The method includes inputting a plurality of timing pulses by the clock pin; and receiving an instruction and receives an address by a first transfer pin of the plurality of pins, wherein the instruction is received at either of rising edges and falling edges of the timing pulses and the address is received at both of the rising edges or the falling edges of the timing pulses. 
         [0011]    The invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]      FIG. 1  (Prior Art) is a block diagram showing a conventional data transmission system. 
           [0013]      FIG. 2  (Prior Art) shows timings for reading serial data in the conventional data transmission system. 
           [0014]      FIG. 3  is a block diagram showing an example of a data transmission system according to a preferred embodiment of the invention. 
           [0015]      FIG. 4A  shows timings of serial data according to a first embodiment of the invention. 
           [0016]      FIG. 4B  shows timings of serial data according to a second embodiment of the invention. 
           [0017]      FIG. 5  is a flow chart showing a method for transmitting random data according to the preferred embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0018]    The invention provides a serial peripheral interface and a data transmitting method thereof, in which many control pins of the serial peripheral interface are utilized to achieve the serial data transmission through multiple input pins and multiple output pins, and enhance the overall behavior of data transmission. 
         [0019]      FIG. 3  is a block diagram showing an example of a data transmission system  300  according to a preferred embodiment of the invention. Referring to  FIG. 3 , the data transmission system  300  includes an integrated circuit  310  and a serial peripheral interface  320 . Take the integrated circuit  310  is a memory device as exemplified, but is not limited. The integrated circuit  310  may be any circuit having a function of storing data. When the integrated circuit  310  is the memory device, the integrated circuit  310  includes a data register  312 , a memory cell array  314  and an output buffer  316 . The memory cell array  314  stores data. 
         [0020]    The serial peripheral interface  320  has many pins  321  to  324  which are coupled to the integrated circuit  310 . The integrated circuit  300  receives an instruction using only the first pin  321  or the first pin  321 , the second pin  322 , the third pin  323 , and the fourth pin  324  of the serial peripheral interface  320 . The integrated circuit receives  300  an address using the first pin  321 , the second pin  322 , the third pin  323 , and the fourth pin  324  of the serial peripheral interface 320 . The instruction and the address are transmitted to the data register  312 , temporarily stored in the data register  312 , and then transmitted to the memory cell array  314 . 
         [0021]    When a read out data is read from the integrated circuit  310  (i.e., when the read out data is to be read from the memory cell array  314 ), the read out data is transmitted to the output buffer  316  from the memory cell array  314 , and temporarily stored in the output buffer  316 . Then the read out data is sent through the first pin  321 , the second pin  322 , the third pin  323 , and the fourth pin  324  of the serial peripheral interface 320 . There may exist multiple dummy cycles before the read out data is sent. 
         [0022]    The multiple pins of the serial peripheral interface  320  substantially include the first pin  321  and the second pin  322 . When the first pin  321  is not for transmitting the instruction, the address or the read out data, the first pin  321  is used to temporarily stop transmitting the read out data. When the second pin  322  is not for transmitting the instruction, the address or the read out data, the second pin  322  can prevent the read out data from being read from the memory cell array  314 . The first pin  321  and the second pin  322  substantially pertain to the control pins in the conventional serial peripheral interface, and are utilized to achieve the transmission of a piece of serial data, including instructions, addresses, dummy cycles and multiple read out data, through multiple input pins and multiple output pins in this embodiment. 
         [0023]    The serial peripheral interface  320  further includes a chip select pin  325  for outputting a chip select signal CS. When the voltage level of the chip select signal CS is low, the first pin  321  to the fourth pin 324  transmit the instruction, the address or the read out data. In addition, the serial peripheral interface  320  also includes a clock pin  326  for inputting a timing signal SCLK, and the first pin 321  to the fourth pin  324  transmit the instruction, the address or the read out data according to the timing signal. It is possible to utilize the first pin 321  to the fourth pin  324  to simultaneously transmit the instruction, the address or the read out data, or to utilize some of the first pin 321  to the fourth pin  324  to simultaneously transmit the instruction, the address or the read out data. Compared with the conventional serial peripheral interface, the serial peripheral interface  300  according to the embodiment of the invention can increase the overall data transmission rate at most three times. 
         [0024]    The timing signal SCLK includes many timing pulses. The first pin 321  to the fourth pin  324  transmit data according to the timing pulses. In addition, the first pin 321  to the fourth pin  324  may also transmit the data at rising edges, falling edges or both of the timing pulses. That is, a selection of the function of the double data rate (DDR) is provided. 
         [0025]      FIG. 4A  shows timings of serial data according to a first embodiment of the invention. As shown in  FIG. 4A , for example, the serial data includes an 8-bit instruction, a 24-bit address, n dummy cycles and multiple 8-bit read out data, wherein n is an integer greater than or equal to 0 and is not particularly restricted. In  FIG. 4A , when the chip select signal CS is low, the timing signal SCLK has many timing pulses. The first pin 321  to the fourth pin  324  receive the serial data at the rising edges and the falling edges of the timing pulses. 
         [0026]    The first pin  321  to the fourth pin  324  receive the 8-bit instruction at the timing pulse 0, and then receive the 24-bit address at the timing pulses 1 to 3, wherein this address is the initial address of the data to be read. Then, n dummy cycles are provided for buffering. Next, the multiple 8-bit read out data are read and outputted after the timing pulse n+3. Compared with the conventional serial peripheral interface, the data transmission rate of the first embodiment of the invention may be increased seven times. In  FIG. 4A , the transmission of all of the instruction, the address, the dummy cycles and the read out data is made according to the function of the double data rate. However, the transmission of the instruction, the address, the dummy cycles or the read out data may be also individually made according to the function of the double data rate or not. For example, only the transmission of the read out data is made according to, without limitation to, the function of the double data rate. 
         [0027]      FIG. 4B  shows timings of serial data according to a second embodiment of the invention. As shown in  FIG. 4B , the first pin  321  receives the 8-bit instruction at the timing pulse 0 to 7. Then the first pin  321  to the fourth pin  324  receive the 24-bit address at the timing pulses 8 to 10. Then, n dummy cycles are provided for buffering. Next, the multiple 8-bit read out data are read and outputted after the timing pulse n+10. The 8-bit instruction is received only by the first pin  321 . The 24-bit address is received by the function of double data rate. The multiple 8-bit read out data are received without the function of double data rate. In the invention, whether the transmission of the instruction, the address, the dummy cycles or the read out data applies the function of double data rate is decided according to the practical requirement and not limited hereinabove. 
         [0028]    The data transmitting method mentioned hereinabove is performed to transmit the continuous data. If the random data has to be transmitted, it is necessary to make a judgment according to the time, for which the voltage level of the chip select signal CS is kept high.  FIG. 5  is a flow chart showing a method for transmitting random data according to the preferred embodiment of the invention. First, the instruction, the address, the dummy cycles and the read out data are sequentially transmitted in steps  510  to  540 . Then, step  550  judges whether the voltage level of the chip select signal is continuously kept high for a period exceeding a predetermined time, such as 240 nanoseconds (ns). If the voltage level of the chip select signal is continuously kept high for a period not exceeding the predetermined time, it represents that the instruction is a random access instruction. So, the procedure goes back to step  520 , and the address, the dummy cycles and the read out data are transmitted again. If the voltage level of the chip select signal is continuously kept high for a period exceeding the predetermined time, it represents that the data transmission ends. 
         [0029]    The serial peripheral interface and the data transmitting method according to the embodiment of the invention utilize many control pins on the serial peripheral interface to perform the data transmitting operation with the integrated circuit. The integrated circuit may be any type circuit with the function of data storage. Consequently, the serial data transmission can be through the multiple input pins and the multiple output pins, and the overall performance of data transmission can be enhanced. 
         [0030]    While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.