Abstract:
A scanning system for use in an imaging apparatus includes a mirror assembly having a rotating mirror with a plurality of facets, a motor operatively coupled to the rotating mirror and closed loop control circuitry coupled to the motor. The mirror assembly generates a lock signal indicative of whether or not the motor is substantially at a target speed. A controller is communicatively coupled to the mirror assembly for controlling rotation of the rotating mirror, the controller generating a reference signal received by the motor assembly indicating the target speed for the rotating mirror. The reference signal is varied based at least in part upon an acceleration profile that accelerates the motor so that overshoot of the target speed is substantially reduced.

Description:
CROSS REFERENCES TO RELATED APPLICATIONS 
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     STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
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     REFERENCE TO SEQUENTIAL LISTING, ETC. 
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     BACKGROUND 
     1. Field of the Disclosure 
     The present disclosure relates generally to electrophotographic imaging devices such as a printer or multifunction device having printing capability, and in particular to a control system for rotating the mirror of the laser scan unit thereof. 
     2. Description of the Related Art 
     Precise motor speed control is a requirement of a broad array of motor-driven applications. Traditional motor speed control is accomplished with phase-lock loop (PLL) circuitry. PLL circuitry is generally well known in the electronics and communications arts, where they are commonly used for the synthesis and regulation of high frequency, oscillating, electrical signals. PLL circuitry generally synchronizes two signals in frequency by eliminating phase errors between the two. Application of PLL circuitry to motor control systems typically includes generating a periodic signal representative of motor speed and comparing the signal to a reference signal of a desired or target frequency. The PLL circuitry attempts to match the phase, and hence frequency, of the two signals in a single control loop. Based on the phase error signal from the PLL circuitry, the voltage to the motor is increased or decreased to increase or retard its speed, respectively, so as to match the reference frequency signal. 
     In electrophotographic imaging devices, such as laser printers and copiers, a polygonal mirror, rotated at a substantially constant velocity, deflects one or more modulated laser beams as scan lines that are impinged onto a photoconductive drum. Some existing imaging devices utilize a mirror assembly which include the polygonal mirror, a mirror motor for rotating the polygonal mirror, one or more sensors associated with the motor for sensing the motor speed and/or position, and circuitry including PLL circuitry for use in locking onto an input reference signal. In such assemblies, the sole output signal generated by a mirror assembly is a binary lock signal which indicates whether or not the motor is at the desired speed according to the input reference signal. Electrophotographic imaging devices typically interface with mirror assemblies only through use of the reference signal input thereto and the output lock signal from the mirror assembly. 
     The circuitry of existing mirror assemblies includes an integrator having an operational amplifier and a passive component network. If the actual mirror motor speed is significantly above or below the target speed corresponding to the reference signal, the integrator can accumulate significant integral error. 
     In the situation in which the mirror motor starts from a standstill, a full acceleration current amount from the mirror assembly circuitry is provided to the mirror motor. As the motor approaches the target speed, the integrator has sufficient time during startup to add and accumulate significant integral error. Thus, as the motor approaches the target speed and accelerates in a substantially linear manner, the integrator cannot subtract the accumulated error fast enough, and the motor speed overshoots. As the motor speed overshoots the target speed, the integrator begins subtracting from the accumulated integral error. By the time the motor speed falls back into the linear operating range, the integral error has been reduced too much. As a result, the mirror motor reports an under-speed condition and begins repeating cycles of full acceleration, overshoot, undriven, and under-speed until the motor is finally able to settle into the linear operating range. This inability to relatively quickly reach a constant speed band because the energy storage in the system as well as the accumulated integral error, thereby leading to overshoot and undershoot of motor speed, is referred to as “chatter.” 
     SUMMARY 
     Embodiments of the present disclosure overcome shortcomings in prior motor control systems for polygonal mirrors and thereby satisfy a significant need for improved motor control of the polygonal mirror in electrophotographic imaging devices. In an example embodiment, there is shown a laser scanning unit including a mirror assembly with a rotating mirror having a plurality of facets, a motor operatively coupled to the rotating mirror and closed loop control circuitry coupled to the motor. The closed loop control circuitry generates a lock signal indicative of whether or not the motor is substantially at a target speed. A controller is communicatively coupled to the mirror assembly for controlling rotation of the rotating mirror. The controller generates a reference signal which is received by the motor assembly having a frequency that indicates the target speed for the rotating mirror. The frequency of the reference signal gradually increases towards the target speed according to an acceleration profile. The acceleration profile causes the closed loop control circuitry to gradually accumulate integral error before reaching steady state in which the integral error is substantially constant. By gradually accumulating integral error, the closed loop control circuitry is able to substantially prevent overshoot and undershoot of the accumulated integral error, thereby substantially eliminating chatter and shortening the time to reach steady state such that the laser scan unit becomes available to participate in an imaging operation sooner. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above-mentioned and other features and advantages of the disclosed embodiments, and the manner of attaining them, will become more apparent and will be better understood by reference to the following description of the disclosed embodiments in conjunction with the accompanying drawings, wherein: 
         FIG. 1  is cross sectional side view of an electrophotographic imaging device; 
         FIG. 2  is a block diagram of the motor control portion of the laser scan unit of the imaging device of  FIG. 1  according to an example embodiment; 
         FIG. 3  is an illustration of an acceleration profile utilized by the motor control portion of  FIG. 2 , together with waveforms of error signals thereof generated during acceleration of the motor of the motor control portion; 
         FIG. 4  is graph illustrating the time to stabilize the motor control portion of  FIG. 2 ; and 
         FIG. 5  is a block diagram of the motor control portion of the laser scan unit of the imaging device of  FIG. 1  according to another example embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     It is to be understood that the present disclosure is not limited in its application to the details of construction and the arrangement of components set forth in the following description or illustrated in the drawings. The present disclosure is capable of other embodiments and of being practiced or of being carried out in various ways. Also, it is to be understood that the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of “including,” “comprising,” or “having” and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. Unless limited otherwise, the terms “connected,” “coupled,” and “mounted,” and variations thereof herein are used broadly and encompass direct and indirect connections, couplings, and mountings. In addition, the terms “connected” and “coupled” and variations thereof are not restricted to physical or mechanical connections or couplings. 
     Terms such as “first”, “second”, and the like, are used to describe various elements, regions, sections, etc. and are not intended to be limiting. Further, the terms “a” and “an” herein do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced item. 
     Furthermore, and as described in subsequent paragraphs, the specific configurations illustrated in the drawings are intended to exemplify embodiments of the disclosure and that other alternative configurations are possible. 
     Reference will now be made in detail to the example embodiments, as illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts. 
       FIG. 1  illustrates an imaging apparatus  20  according to an example embodiment. An image to be printed is electronically transmitted to a main system controller  22  from a source such as an external device (not shown). The main system controller  22  may include one or more processors, and other software, firmware and/or hardware logic necessary to control the functions of imaging apparatus  20 , and may be implemented as one or more application specific integrated circuits (ASICs). Controller  22  may also include or be associated with a memory  24  which may be any volatile and/or non-volatile memory such as, for example, random access memory (RAM), read only memory (ROM), flash memory and/or non-volatile RAM (NVRAM). Alternatively, memory  24  may be in the form of a separate electronic memory (e.g., RAM, ROM, and/or NVRAM), a hard drive, a CD or DVD drive, or any memory device convenient for use with controller  22 . 
     In the example embodiment shown, imaging apparatus  20  is illustrated as a color laser printer for purposes of discussion and should not be regarded as limiting. For color operation, the image to be printed may be de-constructed into four bitmap images or image data, each corresponding to an associated one of the cyan, yellow, magenta and black (CYMK) image planes, for example, by the controller  22 . The controller  22  may initiate an imaging operation whereby a laser scanning unit (LSU)  26  may output first, second, third and fourth modulated light beams  27 K,  27 Y,  27 M, and  27 C. 
     In one example embodiment, LSU  26  may be configured to emit first modulated light beam  27 K which forms a latent image on a photoconductive surface or drum  29 K of a first image forming station  30 K based upon the bitmap image data corresponding to the black image plane. Second modulated light beam  27 M from LSU  26  forms a latent image on a photoconductive drum  29 M of a second image forming station  30 M based upon the bitmap image data corresponding to the magenta image plane. Third modulated light beam  27 C forms a latent image on a photoconductive drum  29 C of a third image forming station  30 C based upon the bitmap image data corresponding to the cyan image plane. Similarly, fourth modulated light beam  27 Y forms a latent image on a photoconductive drum  29 Y of a fourth image forming station  30 Y based upon the bitmap image data corresponding to the yellow image plane. During an imaging operation, each modulated light beam  27  sweeps across its corresponding photoconductive drum  29  in a scan direction that is perpendicular to a media process direction. 
     LSU  26  may include a laser light source  49 , illustrated in  FIG. 2  as laser light sources  49 K,  49 M,  49 C and  49 Y, for each modulated light beam  27 . A rotating polygonal mirror  52  deflects the modulated light beams from each mirror facet towards pre-scan optical components, such as mirrors and lenses, so that the modulated light beams  27  impinge the surface of the associated photoconductive drums  29 . A motor  54  spins mirror  52  under control of controller  22 , as explained in more detail below. 
     Controller  22  may also coordinate the timing of a printing operation to correspond with the imaging operation by LSU  26 , whereby a top sheet of a stack of media is picked up from a media tray  35  by a pick mechanism  37  and is delivered to a media transport belt  39 . The media transport belt  39  may carry the sheet past the four image forming stations  30 , which selectively apply toner to the sheet in patterns corresponding to the latent images written to their associated photoconductive drums  29 . The media transport belt  39  may then carry the sheet  32  with the toned mono or composite color image registered thereon to a fuser assembly  41 . The fuser assembly  41  includes a nip that applies heat and pressure to adhere the toned image to the sheet. Upon exiting the fuser assembly  41 , the sheet is may either be fed into a duplex path  43  for printing on a second surface thereof, or ejected from the imaging apparatus  20  to an output area  45 . 
     Imaging apparatus  20  is illustrated in  FIG. 1  and described above as a color imaging device in which toner from each image forming station  30  is transferred directly to a sheet of media in one step. It is understood that imaging apparatus  20  may be a color imaging device in which toner is transferred from each image forming station  30  onto an intermediate transfer mechanism in a first step, and from the intermediate transfer mechanism to a media sheet in a second step. It is further understood that imaging apparatus  20  may be a monochrome imaging device having only one image forming station  30  for depositing black toner to a media sheet. The general architectures of color imaging devices transferring toner in two steps and monochrome imaging devices are well known and will not be discussed in further detail herein for reasons of simplicity. 
     Referring now to  FIG. 2 , a schematic of at least a portion of LSU  26  is shown. LSU  26  includes mirror assembly  50  having polygonal mirror  52 , motor  54  and electronics  56 , each of which may be mounted to a substrate, such as a printed circuit board  58 . As mentioned, motor  54  rotates polygonal mirror  52 . Electronics  56  may include PLL circuitry  60  which generally receives a reference signal Ref, in this case from controller  22 , and generates output signal  62  for driving motor  54  so that the speed of motor  54  substantially follows the frequency of reference signal Ref. PLL circuitry  60  synchronizes output signal  62  in frequency by eliminating phase errors between it and reference signal Ref. The PLL circuitry  60  attempts to match the phase, and hence frequency, of the two signals in a single control loop. Based on the phase error signal from PLL circuitry  60 , the voltage applied to motor  54  is increased or decreased to change its speed so as to match the frequency of reference signal Ref. 
     Mirror assembly  50  may include a sensing arrangement  63  which senses the actual frequency of motor  54  and provides to phase comparator circuit  64  an output signal corresponding to the sensed frequency. Sensing arrangement  63  may be implemented as, for example, Hall sensors or a field generator winding associated with motor  54 . Phase comparator circuit  64  receives reference signal Ref and the output of sensing arrangement  63 , and generates a phase error output signal having a voltage according to the phase difference between the two signals. Amplifier  66  receives the output of phase comparator circuit  64  and provides at its output an amplified version thereof. Low pass filter  68  integrates the amplified phase error output signal. The output of filter  68  is provided to the input of power transistors  70  which are configured for driving the windings of motor  54 . In this way, PLL circuitry  60  uses the actual frequency of motor  54  in its feedback loop for generating output signal  62  having a frequency that locks to reference signal Ref. PLL circuitry  60  also generates binary lock signal Lock, which may be the output of logic circuitry  70  having as its input the output of phase comparator circuit  64 . During the time when PLL circuitry  60  is attempting to lock onto the frequency of reference signal Ref, the value of lock signal Lock is in a first binary state. Once PLL circuitry  60  becomes locked or substantially locked onto reference signal Ref, PLL circuitry  60  drives lock signal Lock to a second binary state. 
     Because the operation of PLLs is well known, a more detailed description thereof will not be provided for reasons of simplicity. 
     It is understood that PLL circuitry  60  may include additional circuitry. For example, a counter or divider circuit may be placed in the signal path, such as between the output of sensing arrangement  63  and the input of phase comparator circuit  64  so as to generate an output signal  62  having a frequency that is a multiple of the frequency of reference signal Ref. 
     It is noted that with mirror assembly  50  being available as a single, integral unit, controller  22  is unable to receive any signal from mirror assembly  50  other than lock signal Lock. As a result, the only available feedback to controller  22  as to motor  54  being accelerated to the target speed is when the target speed is actually reached, indicated by lock signal Lock changing its binary state. 
     As mentioned, output signal  62  is used to drive motor  54 . In an example embodiment, motor  54  is a brushless DC motor. However, it is understood that motor  54  may be other types of motors. It is further understood that electronics  56  and/or PLL circuitry  60  may include additional circuitry for controlling motor  54 . 
     As discussed, existing control systems for spinning a polygonal mirror create an undesirable amount of chatter which results in an extended period of time for the mirror motor to reach steady state and otherwise lock onto target speeds. According to an example embodiment, controller  22  controls PLL circuitry  60  so that the integral error of PLL circuitry  60 , corresponding to the output of low-pass filter  68 , is gradually accumulated in a more controlled manner so the PLL circuitry  60  reaches steady state, i.e., locks onto reference signal Ref, sooner than seen using prior techniques. 
     In particular, when motor  54  is locked at the target speed, the proportional error appearing at the output of phase comparator circuit  64  and its derivative error are approximately zero. The integral error, appearing at the output of filter  68 , is thus a substantially constant, non-zero value at steady state. Near the operating target speed, it is desirable that the integral error remain non-zero in order to provide a drive signal for mirror  54 . In order to reach steady state sooner, the integral error is accumulated gradually and/or relatively slowly until it reaches steady state with a substantially constant value. By controlling the accumulation of the integral error in a more gradual manner, instances of overshoot and undershoot of the integral error, which result in motor chatter, are substantially avoided, thereby allowing the integral error to reach substantially constant, steady state sooner than in prior techniques. Reaching steady state sooner results in LSU  26  being ready to participate in a print operation sooner. 
     Specifically, instead of setting the frequency of reference signal Ref to the target frequency from the time motor  54  is initially commanded to start rotating, in an example embodiment the frequency of reference signal Ref is gradually increased from a predetermined initial value toward the target frequency. Controller  22  gradually increases the frequency of reference signal Ref using an acceleration profile maintained in memory  24 . According to an example embodiment, the acceleration profile forms a substantially S-shape.  FIG. 3  illustrates a substantially S-shaped acceleration profile in which the frequency of reference signal Ref gradually increases to the target speed over a predetermined period of time, which in this embodiment is less than about 2 seconds. The substantially S-shaped acceleration profile may be obtained through characterization of motor  54  and mirror assembly  50 .  FIG. 3  also illustrates the proportional error, derivative error, integral error IE and total error over the predetermined period of time. The total error may be represented as
 
Total error= Kp *proportional error+ Ki *integral error+ Kd *derivative error,
 
where Kp, Ki and Kd are constants. As can be seen, the gradual increase in the frequency of reference signal Ref results in a more controlled proportional error and derivative error which are both approximately zero at the end of the ramp up in frequency of reference signal Ref to the target speed. The integral error IE is shown as also being controlled without overshoot and reaching a substantially constant level sooner. Also shown is the integral error IE′ from a prior technique in which overshoot and undershoot is observed from reference signal Ref having the target frequency at the onset of the acceleration ramp. In  FIG. 3 , the integral error IE can be seen to reach a substantially constant value noticeably sooner than integral error IE′, thereby resulting in the total error TE to reach a substantially constant value sooner and allowing PLL circuitry  60  to reach steady state more quickly.
 
       FIG. 4  illustrates the frequency response of motor  54  in which a ramped, substantially S-shaped acceleration profile is used, relative to an existing system in which the reference signal is constant at the target frequency from the beginning of initial ramping of motor  54  thereto. As can be seen in  FIG. 4 , there is no motor speed overshoot using the substantially S-shaped acceleration profile, and the time to lock to the target frequency is reduced compared to the existing system. LSU  26  having an acceleration profile as described above has been seen to reach steady state speeds for performing an imaging operation in noticeably less than two seconds. 
     It is understood that other acceleration profiles may be utilized instead of a substantially S-shaped acceleration profile for gradually increasing the speed of motor  54 . For example, controller  22  may utilize a profile having one or more linear ramps of the same or different slopes, a stepped profile in which the steps are largely the same size and duration or may vary, a multiple slope ramp, or a combination thereof. 
     It is further understood that controller  22  may choose an acceleration profile from a plurality of different acceleration profiles maintained in memory  24 , for use in controlling motor  54 . Different target speeds for motor  54  may be used by imaging apparatus  20  dependent upon a number of factors including desired performance and operating and/or environmental factors, for example. In an example embodiment, an acceleration profile may be selected from a plurality of acceleration profiles based upon a desired target speed of motor  54 . Specifically, controller  22  may store a first acceleration profile for bringing motor  54  to a first predetermined target speed, and a second acceleration profile for bringing motor  54  to a second predetermined target speed different from the first predetermined target speed. Memory  24  may store more than two acceleration profiles, any one of which may be selected by controller  22  for use in performing an imaging operation. 
     The operation of LSU  26  to reach a steady state speed for mirror  52  will be described. When a decision is made by controller  22  that mirror  52  is to be brought to a target speed for use in performing an imaging operation, controller  22  selects from memory  24  an acceleration profile based upon the target speed and having gradually increasing speed values for setting the frequency of reference signal Ref. In the example embodiment described above, the gradually increasing speed values may follow a substantially S-shaped acceleration profile as shown in  FIG. 3 . Because there is no feedback to controller  22  as to the present speed or position of motor  54 , due to only having motor speed information from binary lock signal Lock, the entire acceleration profile may be utilized. Having the frequency of reference signal Ref gradually increased as the speed of motor  54  is increased towards the target speed results in the speed of motor  54  not surpassing or overshooting the target speed and reaching steady state in a shorter period of time. 
       FIG. 5  illustrates a portion of LSU  26  according to another example embodiment. Electronics  56  may include a different implementation of PLL circuitry. In this embodiment, PLL circuitry  80  generates a periodic signal  82  representative of motor speed and compares the periodic signal  82  to reference signal Ref having the desired frequency. PLL circuitry  80  synchronizes periodic signal  82  in frequency by eliminating phase errors between reference signal Ref and periodic signal  82 . The PLL circuitry attempts to match the phase, and hence frequency, of the two signals in a single control loop. Based on the phase error signal from PLL circuitry  80 , the voltage to motor  54  is increased or decreased to change its speed so as to match the frequency of reference signal Ref. As shown in  FIG. 5 , PLL circuitry  80  may include phase comparator circuit  64  which compares the phase of its two input signals, in this case reference signal Ref and periodic signal  82 , and generates a phase error output signal having a voltage according to the phase difference between the two signals. Amplifier  66  may receive the output of phase comparator circuit  64  and provide at its output an amplified version thereof. Low pass filter  88  filters the output from amplifier  66  and removes any components of the signals of which the phase is being compared from periodic signal  62 . Voltage controlled oscillator (VCO)  90  generates periodic signal  82 , the frequency of which can be controlled and swung over the operational frequency band for the closed loop based upon the voltage of the output of filter  88 . Combined, PLL circuitry  80  serves to lock periodic signal  82  to the frequency of reference signal Ref. PLL circuitry  80  generates binary lock signal Lock, which may be the output of logic circuitry  90  having as its input the output of phase comparator circuit  64 . During the time when PLL circuitry  80  is attempting to lock onto the frequency of reference signal Ref, the value of lock signal Lock is in a first binary state. Once PLL circuitry  80  becomes locked or substantially locked onto reference signal Ref, PLL circuitry  80  drives lock signal Lock to a second binary state. 
     With respect to the implementation shown in  FIG. 5 , controller  22  controls PLL circuitry  80  so that motor  54  is maintained at or near its linear range during substantially the entire time motor  54  accelerates to a steady state target speed. By largely maintaining motor  54  so that it accelerates linearly, the accumulation of significant integral error is substantially avoided or otherwise reduced, thereby reducing or substantially eliminating chatter and reducing the time needed for PLL circuitry  80  to lock onto the target speed. 
     The foregoing description of several methods and example embodiments has been presented for purposes of illustration. It is not intended to be exhaustive or to limit the invention to the precise steps and/or forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be defined by the claims appended hereto.