Abstract:
The charge pump circuit, includes an amplifier, a condenser, and a modifying circuit. The amplifier has a plurality of first voltage transfer stages, and each first voltage transfer stage transfers a voltage from an input to an output thereof such that the output voltage equals the input voltage minus a voltage drop. The condenser increases the output voltage at the output of at least one of the voltage transfer stages, and the voltage modifying circuit modifies each increased output voltage to compensate for the voltage drop.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a charge pump circuit, and more particularly, to a charge pump circuit which improves reliability and economic efficiency of a circuit. 
     2. Discussion of the Related Art 
     FIG. 1 is a circuit diagram illustrating a conventional charge pump circuit. As shown in FIG. 1, the conventional charge pump circuit includes an amplifier  11 , a condenser  12 , a first clock input  13  and a second clock input  14 . The amplifier  11  includes first, second, third, fourth and fifth NMOS transistors  15 ,  16 ,  17 ,  18  and  19  connected in series. Gates and drains of the first, second, third, fourth and fifth NMOS transistors  15 ,  16 ,  17 ,  18  and  19  are connected with one another, and their substrates are connected to a ground voltage VSS. 
     The drain of the first NMOS transistor  15  is connected to a driving voltage V DD , and the drain of the second NMOS transistor  16  is connected to a source of the first NMOS transistor  15 . In the same manner as the second NMOS transistor  16 , the drains of the third and fourth NMOS transistors  17  and  18  are respectively connected to sources of respective previous NMOS transistors. 
     The drain of the fifth NMOS transistor  19  is connected to the source of the fourth NMOS transistor  18 , and the source of the fifth NMOS transistor  19  is connected to an output  24 . 
     The condenser  12  includes first, second, third and fourth capacitors  20 ,  21 ,  22  and  23 . Each capacitor is formed by an NMOS transistor with the gate thereof serving as one electrode and the source, drain and substrate connected together serving as the other electrode. The first, second, third and fourth capacitors  20 ,  21 ,  22  and  23  are connected with gates and drains of the second, third, fourth, and fifth NMOS transistors  16 ,  17 ,  18 , and  19 , respectively. 
     The first and third capacitors  20  and  22 , connected to the drains of the second and fourth NMOS transistors  16  and  18 , are connected with the first clock input  13 . The second and fourth capacitors  21  and  23 , connected to the drains of the third and fifth NMOS transistors  17  and  19 , are connected with the second clock input  14 . 
     The operation of the aforementioned conventional charge pump circuit will be described below. 
     In the charge pump circuit, a voltage drop V T  occurs when the first—fifth NMOS transistors  15 - 19  transfer a voltage at their drains to their sources because the same voltage at each respective drain is applied to the respective gate. 
     The driving voltage V DD  is applied to the gate and drain of the first NMOS transistor  15 , so that the source of the first NMOS transistor  15  is charged to V DD −V T . In this state, if the first clock goes from 0V to V DD , the source of the first NMOS transistor  15  increases by V DD  because the charge across the first capacitor  20  must remain constant. Accordingly, the charge at the source of the first NMOS transistor  15  is pumped to 2V DD −V T . 
     If 2V DD −V T  is applied to the gate and drain of the second NMOS transistor  16 , the source voltage of the second NMOS transistor  16  becomes 2V DD −2V T . At this time, if the second clock  14  goes from 0V to V DD , the source voltage of the second NMOS transistor  16  increases by V DD  and becomes 3V DD −2V T . 
     In the same manner as above, the operation at the third and fourth NMOS transistors  17  and  18  is performed. 
     Then, if 5V DD −4V T  is applied to the gate and drain of the fifth NMOS transistor  19 , the source voltage of the fifth NMOS transistor  19  becomes 5V DD −5V T . Accordingly, an output voltage V PP  of 5V DD −5V T  appears at the output  24 . The output voltage V PP  can be expressed as follows: 
     
       
         V PP =[V DD +n(V CLK −V T )]−V T   (1) 
       
     
     assuming that both the first and second clocks transition by the same voltage V CLK , and where n is the number of pumping stages (i.e., the number of capacitors in the condenser  12 ). 
     The conventional charge pump circuit has several problems. 
     First, because of the cummulative of the voltage drop V T  occurring at each NMOS transistor in the amplifier  11 , a voltage lower than desired is output. This reduces the reliability of the circuit. In addition, more stages are required to output the desired voltage, but the additional stages reduce current driving ability and economic efficiency, in terms of size, of the circuit. 
     SUMMARY OF THE INVENTION 
     Accordingly, the present invention is directed to a charge pump circuit that substantially obviates one or more of the problems due to limitations and disadvantages of the related art. 
     An object of the present invention is to provide a charge pump circuit which compensates for the voltage drop to improve reliability and economic efficiency of a circuit. 
     Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings. 
     These and other objects are achieved by providing a charge pump circuit, comprising: an amplifier having a plurality of first voltage transfer stages, each first voltage transfer stage transferring a voltage from an input to an output thereof such that the output voltage equals the input voltage minus a voltage drop; a first condenser increasing the output voltage at the output of at least one of the voltage transfer stages; and voltage modifying means for modifying each increased output voltage to compensate for the voltage drop. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will become more fully understood from the detailed description given below and the accompanying drawings which are given by way of illustration only, wherein like reference numerals designate corresponding parts in the various drawings, and wherein: 
     FIG. 1 is a circuit diagram illustrating a conventional charge pump circuit; 
     FIG. 2 is a circuit diagram illustrating a charge pump circuit according the embodiment of the present invention; 
     FIG. 3 is a comparative view illustrating an output voltage of a conventional charge pump circuit and an output voltage of a charge pump circuit according to the present invention; and 
     FIG. 4 is a pulse view illustrating each clock of a charge pump circuit according to the embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. 
     FIG. 2 illustrates an embodiment of the charge pump circuit according to the present invention. As shown, the circuit includes an amplifier  31  connected to a first condenser  32  and a moving portion  35 . The circuit further includes a controller  36  connected to the moving portion  35  and a second condenser  37 . 
     The amplifier  31  includes first, second, third, fourth, and fifth NMOS transistors  40 ,  41 ,  42 ,  43 , and  44  connected in series. The respective drain and gate of each of the first—fifth NMOS transistors  40 - 44  are connected together. The drain of the first NMOS transistor  40  is also connected to a driving voltage V DD , and the source of the fifth NMOS transistor is connected to an output  64 . 
     The first condenser  32  includes first, second, third, and fourth capacitors  45 ,  46 ,  47  and  48 . Each capacitor is formed by an NMOS transistor with the gate thereof serving as one electrode and the source and drain connected together serving as the other electrode. As shown in FIG. 2, the first capacitor  45  is connected between a first clock input  33  and the source of the first NMOS transistor  40 , the second capacitor  46  is connected between a second clock input  34  and the source of the second NMOS transistor  41 , the third capacitor  47  is connected between the first clock input  33  and the source of the third NMOS transistor  42 , and the fourth capacitor  48  is connected between a second clock input  34  and the source of the fourth NMOS transistor  43 . 
     The moving portion  35  includes sixth, seventh, eighth, ninth and tenth NMOS transistors  49 ,  50 ,  51 ,  52  and  53  connected in series. The drain of the sixth NMOS transistor  49  receives the driving voltage V DD , and the source of the tenth NMOS transistor  53  is connected to the output  64 . The substrate of the sixth—tenth NMOS transistors  49 - 53  are respectively connected to the substrate of the first—fifth NMOS transistors  40 - 44 . 
     The controller  36  includes eleventh, twelfth, thirteenth, fourteenth and fifteenth NMOS transistors  54 ,  55 ,  56 ,  57 , and  58 . The drain of the eleventh NMOS transistor  54  receives the driving voltage V DD , and the source is connected to the gate of the sixth transistor  49 . The drain and source of the twelfth NMOS transistor  55  are connected to the gate of the eleventh NMOS transistor  54  and the source of the seventh NMOS transistor  50 , respectively. The drain and gate of the thirteenth NMOS transistor  56  are connected to the gate of the twelfth NMOS transistor  55  and the gate of the eighth NMOS transistor  51 , respectively. The drain and source of the fourteenth NMOS transistor  57  are connected to the gate of the thirteenth NMOS transistor  56  and the gate of the ninth NMOS transistor  52 , respectively. The drain and source of the fifteenth NMOS transistor  58  are connected to the gate of the fourteenth NMOS transistor  57  and the gate of the tenth NMOS transistor  53 , respectively. The gate of the fifteenth NMOS transistor  58  is connected to the output  64 . 
     The second condenser  37  includes fifth, sixth, seventh, eighth and ninth capacitors  59 ,  60 ,  61 ,  62  and  63 . Each capacitor is formed by an NMOS transistor with the gate thereof serving as one electrode and the source and drain connected together serving as the other electrode. As shown in FIG. 2, the fifth capacitor  59  is connected between a third clock input  38  and the source of the eleventh NMOS transistor  54 , the sixth capacitor  60  is connected between a fourth clock input  39  and the source of the twelfth NMOS transistor  55 , the seventh capacitor  61  is connected between the third clock input  38  and the source of the thirteenth NMOS transistor  56 , the eight capacitor  62  is connected between a fourth clock input  39  and the source of the fourteenth NMOS transistor  57 , and the ninth capacitor  63  is connected between the third clock input  38  and the source of the fifteenth NMOS transistor  58 . 
     The operation of the charge pump circuit will now be described. With the driving voltage V DD  applied to both the drain and the gate of the first NMOS transistor  40 , voltage at the source thereof becomes the driving voltage V DD  less the voltage drop V T . At this time, the first clock signal at the first clock input  33  transitions from 0V to V DD  as shown in FIG.  4 . As a result, the voltage at the source of the first NMOS transistor  40  increases by V DD  to 2V DD −V T . 
     Because this voltage of 2V DD −V T , also applied to the gate of the eleventh NMOS transistor  54 , is greater than the voltage V DD  at the drain of the eleventh transistor  54 , the voltage V DD  at the drain is transferred to the source without the voltage drop V T . Accordingly, the voltage at the source of the eleventh NMOS transistor  54  becomes V DD . 
     Next, the first clock transitions from V DD  to 0V, and the voltage at the source of the first NMOS transistor  40  returns to V DD −V T . Then, the third clock shown in FIG. 4 at the third clock input  38  transitions from 0V to V DD . This causes the voltage at the source of the eleventh NMOS transistor  54  to increase to 2V DD . Because the voltage 2V DD  at the gate of the sixth NMOS transistor  49  is greater than the voltage V DD  at the drain of the sixth NMOS transistor  49 , the voltage V DD  at the drain is transferred to the source without the voltage drop V T . Consequently, the voltage V DD  appears at the source of the sixth NMOS transistor  49 . With the source of the first NMOS transistor  40  connected to the source of the sixth NMOS transistor  49 , the voltage at the source of the first NMOS transistor  40  also becomes V DD . 
     Then, the first clock transitions from 0V to V DD  again, and the voltage at the source of the first NMOS transistor  40  becomes 2V DD . The next stage of the second NMOS transistor  41 , the seventh NMOS transistor  50  and the twelfth NMOS transistor  55  operates in the same manner with respect to the second and fourth clocks received at the second and fourth clock inputs  34  and  39 . The second and fourth clocks are illustrated in FIG. 4 as being the same as the third and first clocks, respectively. As a result, 3V DD  appears at the source of the second NMOS transistor  41 . 
     The same operation is repeated for the next two stages such that 4V DD  appears at the source of the third NMOS transistor  42  and 5V DD  appears at the source of the fourth NMOS transistor  43 . Because 5V DD  is applied to both the drain and the gate of the fifth NMOS transistor  44 , the voltage at the source thereof becomes 5V DD  less the voltage drop V T . Accordingly, the voltage 5V DD −V T  at the source of the fifth NMOS transistor  44  is applied to the gate of the fifteenth transistor  58 . But, because this gate voltage is less than the drain voltage of 5V DD , the drain voltage is not transferred to the source. Instead the voltage at the source of the fifteenth transistor  58  becomes 5V DD −2V T . 
     Then, the third clock transitions from 0V to V DD , and the ninth capacitor  63  causes the voltage at the source of the fifteenth transistor  58  to increase to 6V DD −2V T . In a preferred embodiment, the charge pump circuit of FIG. 2 is designed so that 6V DD −2V T  is greater than 5V DD . Therefore, in this preferred embodiment, the voltage 6V DD −2V T  at the gate of the tenth transistor  53  is greater than the voltage 5V DD  at the drain of the tenth transistor  53 , and the drain voltage is transferred to the source. Accordingly, the output voltage V PP  becomes 5V DD , and the reduction in voltage caused by the voltage drop across the first—fifth transistors  40 - 44  has been completed compensated. 
     In an alternative embodiment, however, the gate voltage of 6V DD −2V T  is less than the drain voltage of 5V DD . As a result, the voltage at the drain of the tenth transistor  53  is not transferred to the source, and the voltage at the source of the tenth transistor  53  becomes 6V DD −3V T . Accordingly, the output voltage V PP  becomes 6V DD −3V T , and the reduction in voltage caused by the voltage drop across the first—fifth transistors  40 - 44  has been partially compensated. 
     The output voltage V PP  can be expressed as follows when 6V DD −2V T  is greater than 5V DD : 
     
       
         V PP =V DD +nV CLK   (2) 
       
     
     assuming that the first, second, third and fourth clocks transition by the same voltage V CLK , and where n is the number of pumping stages (i.e., the number of capacitors in the first condenser  32 ). 
     The output voltage V PP  can be expressed as follows when 6V DD −2V T  is less than 5V DD : 
     
       
         V PP =V DD +(n+1)V CLK −3V T   (3) 
       
     
     assuming that the first, second, third and fourth clocks transition by the same voltage V CLK , and where n is the number of pumping stages (i.e., the number of capacitors in the first condenser  32 ). 
     As shown in FIG.  3  and equation (2), a voltage  70  output by the charge pumping circuit according to the preferred embodiment of the present invention does not suffer from a decease in voltage corresponding to the voltage drop V T  unlike a voltage  71  output by the conventional charge pump circuit. 
     As aforementioned, the charge pump circuit according to the present invention has the following advantages. 
     Since the charge pump circuit of the present invention includes a controller and moving portion for removing the voltage drop V T  at each stage of the amplifier, it is possible to obtain a desired voltage in low voltage (low VCC) applications. This improves reliability of the circuit. In addition, since the desired voltage is output while maintaining the number of the stages, it is possible to improve the current driving ability and economic efficiency, in the of size, of the circuit. 
     It will be apparent to those skilled in the art that various modifications and variations can be made in the charge pump circuit according to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention covers the modifications and variations of the invention provided they come within the scope of the appended claims and their equivalents.