Abstract:
In a voltage dividing circuit, a first circuit where only a first switch is connected, a second circuit where a first resistor and a second switch are connected in series, a third circuit where a second resistor and a third switch are connected in series and a fourth circuit where a third resistor and a fourth switch are connected in series are connected in parallel. One end of the parallel circuit is connected to a limit resistor and the other end of the parallel circuit is connected to a ground point. One switch is provided between a connecting point in one circuit and a connecting point in another circuit, and each resistor of at least two circuits is connected in parallel by said one switch.

Description:
TECHNICAL FIELD 
     The present invention relates to a key input device identifying an operated key in a plurality of keys. 
     BACKGROUND ART 
     Conventional electronic equipment has a number of keys for performing various setup and switching of operation with respect to the equipment at a front or a side thereof. In such electronic equipment, when any key is operated, a signal (voltage signal) corresponding to the key is supplied to, for example, a microcomputer provided in the electronic equipment. The microcomputer identifies the operated key based on the supplied signal (voltage signal) and controls the operation of the electronic equipment based on a result of identification. 
     Patent literatures No. 1 to No. 3 mentioned below describe common means for identifying the operated key based on the signal (voltage signal) supplied to the microcomputer. 
     Patent literature No. 1 describes a key matrix circuit. In this circuit, when any selection key is pressed in a keyboard with a plurality of selection keys arranged in a matrix, two pairs of voltage levels corresponding to the pressed selection key are detected, and the pressed selection key is identified based on the detection result. 
     Patent literature No. 2 describes a key switch circuit comprising a plurality of switch groups and a hold switch for holding an operation command by a key switch. The key switch circuit is provided with a hold circuit. When no key switch in the key switch groups is operated, the hold circuit holds a voltage at a particular value different from a value of an output voltage generated in the key switch circuit, whereby it is capable of determining whether the key switch circuit is connected or not, without increasing the number of input ports for such as CPU (Central Processing Unit). 
     Patent literature No. 3 describes a key input device. In this key input device, each one end of a plurality of resistor string parts to produce the resistance value corresponding to the input key is connected electrically to a power supply, and a selection part electrically connects one of the plurality of resistor string parts to ground in response to a selection command from a control unit. Further, one of the resistor string parts corresponding to the selection command from the control unit is electrically connected to the power supply and, when a value of the voltage corresponding to the input key at the resistor string part is generated at a connecting node, the control unit identifies the input key based on the value of the voltage generated at the connecting node and the selection command given to the selection part. 
     CITATION LIST 
     Patent Literature 
     
         
         Patent Literature 1: Japanese Laid-Open Patent Publication No. 2001-51774 
         Patent Literature 2: Japanese Laid-Open Patent Publication No. 2000-137567 
         Patent Literature 3: Japanese Laid-Open Patent Publication No. 2007-323295 
       
    
     SUMMARY OF INVENTION 
     Technical Problems 
     In the circuits and the device described in the above patent literatures, a plurality of resistors are connected in series as means for identifying the operated key based on the signal (voltage signal) supplied to the microcomputer, and the operated key is identified based on a divided voltage according to the series-connected resistors. 
     Accordingly, if the number of keys to be identified is increased, the number of resistors required for identifying keys should be also increased. This causes a problem that the cost increases as the number of keys increases. In addition, increase in the number of resistors causes enlargement of circuit and more power consumption. 
     In view of the above problems, the present invention aims to provide a key input device capable of reducing the cost by suppressing the increase in the number of resistors even if the number of keys to be identified increases. 
     Solution to Problems 
     A key input device according to the present invention includes a plurality of keys, a limit resistor whose one end is connected to a power supply and a voltage dividing circuit connected to the other end of the limit resistor to generate different voltages corresponding to each key when any of the plurality of keys is operated, and identifies the operated key based on the voltage generated by the voltage dividing circuit. The voltage dividing circuit includes a plurality of resistors and a plurality of switches each of which is corresponding to each of the plurality of keys. The plurality of switches are composed of a first switch group and a second switch group. A plurality of circuits each of which has one resistor out of the plurality of resistors and one switch in the first switch group are provided, where the resistor and the switch are connected in series. The plurality of circuits are connected in parallel so that one end thereof is connected to the limit resistor and the other end thereof is grounded. Each circuit in the parallel-connected circuits has a connecting point between the resistor and the switch, and one switch in the second switch group is connected between the connecting point in one circuit and the connecting point in another circuit, and each resistor of at least two circuits is connected in parallel by said one switch. 
     In the above configuration, the circuits having the switch (first group) and the resistor connected in series are connected in parallel, and the switch (second group) is arranged between the connecting points of the switch (first group) and the resistor in each circuit. Thus, compared to the voltage dividing circuit where the plurality of resistors are connected in series, it is possible to generate more various divided voltages of different voltage values. Therefore, if a voltage dividing circuit is configured with the same number of resistors, the device of the present invention can identify more keys than conventional devices. Accordingly, it is possible to reduce the cost by suppressing the increase in the number of resistors even if the number of keys increases. 
     In the key input device of the present invention, the plurality of resistors may have different resistance values with each other. 
     According to this, the voltage dividing circuit can generate divided voltages of different values easily, thereby preventing the misidentification of keys due to the voltage values being close to each other. 
     Advantageous Effects of Invention 
     According to the present invention, it is possible to provide the key input device capable of reducing the cost by suppressing the increase in the number of resistors, even if the number of keys to be identified increases. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  is a block diagram showing a configuration of a key input device. 
         FIG. 2  is a diagram showing an example of a configuration of a voltage dividing circuit according to an embodiment of the present invention. 
         FIG. 3  is a diagram showing another example of a configuration of a voltage dividing circuit according to an embodiment of the present invention. 
         FIG. 4  is a diagram showing an example of a conversion table. 
         FIG. 5  is a diagram showing another example of a conversion table. 
         FIG. 6  is a diagram showing an example of a configuration of a conventional voltage dividing circuit. 
         FIG. 7  is another example of a configuration of a conventional voltage dividing circuit. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     An embodiment of the present invention will be described hereinafter with reference to the drawings. 
     First, a configuration of the general key input device will be described with a block diagram of  FIG. 1 . As illustrated in  FIG. 1 , a key input device  1  comprises an input circuit  10  having a plurality of keys and an arithmetic processing circuit  20  for identifying keys to which the input operation is performed based on a voltage signal supplied from the input circuit  10 . 
     The input circuit  10  comprises a key K, a power supply  11 , a voltage dividing circuit  12 , an output port  13  outputting a voltage signal, and a limit resistor  14  whose one end is connected to the power supply  11  and the other end is connected to the voltage dividing circuit  12  through a connecting line  15 . The output port  13  is connected to a connecting point P of the limit resistor  14  and the voltage dividing circuit  12 . The voltage value of the power supply  11  is V 0  and the resistance value of the limit resistor  14  is R 1 . 
     The arithmetic processing circuit  20  is an LSI (Large Scale Integration) and includes, for example, a control unit  21 , an input port  22 , an A/D converter  23 , a temporary memory  24 , a memory  25  and the output unit  26 . 
     The control unit  21  is a CPU (Central Processing Unit), and generally controls each part of the arithmetic processing circuit  20 . 
     The input port  22  receives a voltage signal supplied from the output port  13  of the input circuit  10 , and then supplies the signal to the A/D converter  23 . The A/D converter  23  converts the input voltage signal from an analog signal to a digital signal. 
     The temporary memory  24  is, for example, a RAM (Random Access Memory) and is provided with a storage area to store the voltage signal outputted from the A/D converter  23  temporarily. 
     The memory  25  is, for example, a ROM (Read Only Memory) and includes various programs which are executed by the control unit  21  and data which is read when the various programs are executed. 
     Specifically, the memory  25  includes a identification program  25   a  which performs key identification based on the voltage signal (voltage value) supplied from the input circuit  10 , and a conversion table  25   b  recording the voltage signal (voltage value) supplied to the input port  22  and the kind of the key to be identified so that they are associated with each other. The conversion table  25   b  will be described below in detail. 
     The output unit  26  supplies information regarding the key (hereinafter, described as “key information”) identified by execution of the identification program  25   a  to a device (not illustrated) such as a DVD (Digital Versatile Disc) player connected with the key input device  1 . 
     In the key input device  1  configured as above, when identification of the key to which the input operation is performed, a voltage which is previously set for every key is generated by the voltage dividing circuit  12 . The generated divided voltage i.e. a voltage signal is supplied to the arithmetic processing circuit  20  through a connecting line  15  and the output port  13 . Then in the arithmetic processing circuit  20 , under control of the control unit  21 , key identification based on the voltage signal inputted to the input port  22  is executed with the identification program  25   a  and the conversion table  25   b.    
     Here, a voltage dividing circuit  12   c  indicated in  FIG. 6  and a voltage dividing circuit  12   d  indicated in  FIG. 7  are taken as conventional examples of the voltage dividing circuit  12 . 
     First, in  FIG. 6 , the voltage dividing circuit  12   c  includes three resistors  16   c  to  18   c  and four switches (SW 51  to SW 54 ) corresponding to, respectively, four keys (KEY 51  to KEY 54 ) to which the input operation is performed. Resistance values of the resistors  16   c  to  18   c  are R 2  to R 4 , respectively. 
     In the voltage dividing circuit  12   c , the resistors  16   c  to  18   c  are connected in series. One end of the switch SW 51  is connected to a connecting point P 51  of the connecting line  15  and the resistor  16   c . Similarly, one end of the switch SW 52  is connected to a connecting point P 52  of the resistor  16   c  and the resistor  17   c , one end of the switch SW 53  is connected to a connecting point P 53  of the resistor  17   c  and the resistor  18   c , and one end of the switch SW 54  is connected to an end of the resistor  18   c.    
     The other end of the switch SW 51  is connected to a connecting point P 54  provided on one end of a ground line L 21  connecting the switches (SW 51  to SW 54 ) in common. Similarly, the other end of the switch SW 52  is connected to a connecting point P 55  provided on the ground line L 21 , the other end of the switch SW 53  is connected to a connecting point P 56  provided on the ground line L 21 , and the other end of the switch SW 54  is connected to a connecting point P 57  provided on the other end of the ground line L 21 . 
     Further, since the connecting point P 54  provided on one end of the ground line L 21  is also connected to a ground point G, the other ends of the switches (SW 51  to SW 54 ) are connected to the ground point G in common through the ground line L 21 . 
     In the above configuration, when the KEY  51  is operated, for example, one end of the connecting line  15  and the ground point G are short-circuited by the switch SW 51  connected between the connecting points P 51  and P 54 . Therefore, a divided voltage generated in the voltage dividing circuit  12   c , that is, an input voltage V 1  which is supplied from the connecting point P to the output port  13  ( FIG. 1 ) is indicated as V 1 =0. 
     Similarly, when the KEY  52  is operated, for example, one end of the resistor  16   c  and the ground point G are short-circuited by the switch SW 52  connected between the connecting points P 52  and P 55 . Therefore, the input voltage V 1  is indicated as V 1 =V 0 ·R 2 /(R 1 +R 2 ). 
     When the KEY  53  is operated, one end of the resistor  17   c  and the ground point G are short-circuited by the switch SW 53  connected between the connecting points P 53  and P 56 . Therefore, the input voltage V 1  is indicated as V 1 =V 0 ·(R 2 +R 3 )/(R 1 +R 2 +R 3 ). 
     When the KEY  54  is operated, one end of the resistor  18   c  and the ground point G are short-circuited by the switch SW 54  connected between an end of the resistor  18   c  and the connecting point P 57 . Therefore, the input voltage V 1  is indicated as V 1 =V 0 ·(R 2 +R 3 +R 4 )/(R 1 +R 2 +R 3 +R 4 ). 
     As described above, in the voltage dividing circuit  12   c , four kinds of divided voltages of different values are generated by short-circuiting the predetermined portion in the circuit  12   c  with one of the switches SW 51  to SW 54  by key operation. And the divided voltages generated in the circuit  12   c  are supplied to the output port  13  through the connecting point P as the input voltage V 1 . 
     Next, in  FIG. 7 , the voltage dividing circuit  12   d  includes four resistors  16   d  to  19   d  and five switches (SW 61  to SW 65 ) corresponding to, respectively, five keys (KEY 61  to KEY 65 ) to which the input operation is performed. Resistance values of the resistors  16   d  to  19   d  are R 2  to R 5 , respectively. 
     In the voltage dividing circuit  12   d , the resistors  16   d  to  19   d  are connected in series. One end of the switch SW 61  is connected to a connecting point P 61  of the connecting line  15  and the resistor  16   d . Similarly, one end of the switch SW 62  is connected to a connecting point P 62  of the resistors  16   d  and  17   d , one end of the switch SW 63  is connected to a connecting point P 63  of the resistors  17   d  and  18   d , one end of the switch SW 64  is connected to a connecting point P 64  of the resistors  18   d  and  19   d , and one end of the switch SW 65  is connected to an end of the resistor  19   d.    
     The other end of the switch SW 61  is connected to a connecting point P 65  provided on one end of a ground line L 31  connecting the switches (SW 61  to SW 65 ) in common. Similarly, the other end of the switch SW 62  is connected to a connecting point P 66  provided on the ground line L 31 , the other end of the switch SW 63  is connected to a connecting point P 67  provided on the ground line L 31 , the other end of the switch SW 64  is connected to a connecting point P 68  provided on the ground line L 31 , and the other end of the switch SW 65  is connected to a connecting point P 69  provided on the other end of the ground line L 31 . 
     Further, since the connecting point P 65  provided on one end of the ground line L 31  is also connected to the ground point G, the other ends of the switches (SW 61  to SW 65 ) are connected to the ground point G in common through the ground line L 31 . 
     In the above configuration, when the KEY 61  is operated, for example, one end of the connecting line  15  and the ground point G are short-circuited by the switch SW 61  connected between the connecting points P 61  and P 65 . Therefore, a divided voltage generated in the voltage dividing circuit  12   d , that is, an input voltage V 1  supplied from the connecting point P to the output port  13  is indicated as V 1 =0. 
     When the KEY 62  is operated, one end of the resistor  16   d  and the ground point G are short-circuited by the switch SW 62  connected between the connecting points P 62  and P 66 . Therefore, the input voltage V 1  is indicated as V 1 =V 0 ·R 2 /(R 1 +R 2 ). 
     When the KEY 63  is operated, one end of the resistor  17   d  and the ground point G are short-circuited by the switch SW 63  connected between the connecting points P 63  and P 67 . Therefore, the input voltage V 1  is indicated as V 1 =V 0 ·(R 2 +R 3 )/(R 1 +R 2 +R 3 ) When the KEY 64  is operated, one end of the resistor  18   d  and the ground point G are short-circuited by the switch SW 64  connected between the connecting points P 64  and P 68 . Therefore, the input voltage V 1  is indicated as V 1 =V 0 ·(R 2 +R 3 +R 4 )/(R 1 +R 2 +R 3 +R 4 ). 
     When the KEY 65  is operated, an end of the resistor  19   d  and the ground point G are short-circuited by the switch SW 65  connected between the end of the resistor  19   d  and the connecting point P 69 . Therefore, the input voltage V 1  is indicated as V 1 =V 0 ·(R 2 +R 3 +R 4 +R 5 )/(R 1 +R 2 +R 3 +R 4 +R 5 ). 
     As described above, in the voltage dividing circuit  12   d , five kinds of divided voltages of different values are generated by short-circuiting the predetermined portion in the circuit  12   d  with one of the switches SW 61  to SW 65  by key operation. And the divided voltages generated in the circuit  12   d  are supplied to the output port  13  through the connecting point P as the input voltage V 1 . 
     When no key is operated in the voltage dividing circuits  12   c  and  12   d , the above-mentioned divided voltages are not generated in each voltage dividing circuit. Therefore, the input voltage V 1  having voltage value of V 0  is supplied from the power supply  11  to the output port  13  through the limit resistor  14 . 
     Consequently, if the voltage dividing circuit  12  in  FIG. 1  is the conventional voltage dividing circuit  12   c  ( FIG. 6 ) having three resistors  16   c  to  18   c , five kinds of input voltages V 1  of different values are supplied to the arithmetic processing circuit  20  through the output port  13 . Therefore, the arithmetic processing circuit  20  can identify five different kinds of keys by performing a predetermined process based on the input voltage V 1 . 
     Similarly, if the voltage dividing circuit  12  in  FIG. 1  is the conventional voltage dividing circuit  12   d  ( FIG. 7 ) having four resistors  16   d  to  19   d , six kinds of input voltages V 1  of different values are supplied to the arithmetic processing circuit  20  through the output port  13 . Therefore, the arithmetic processing circuit  20  can identify six different kinds of keys by performing a predetermined process based on the input voltage V 1 . 
     However, in such configuration as the voltage dividing circuits  12   c  and  12   d  where resistors are connected in series, if the number of keys to be identified increases, a large number of resistors should be provided and the cost increases as the number of components increases. 
     Therefore, in the present embodiment, the circuit configurations such as the voltage dividing circuit  12   a  in  FIG. 2  and the voltage dividing circuit  12   b  in  FIG. 3  are employed to solve the above problem. 
     First, the voltage dividing circuit  12   a  in  FIG. 2  includes three resistors, i.e. a resistor  16   a  whose resistance value is R 2 , a resistor  17   a  whose resistance value is R 3  and a resistor  18   a  whose resistance value is R 4 . The voltage dividing circuit  12   a  is composed of a circuit L 1  where only a switch SW 1  is connected, a circuit L 2  where the resistor  16   a  and a switch SW 2  are connected in series, a circuit L 3  where the resistor  17   a  and a switch SW 3  are connected in series, and a circuit L 4  where the resistor  18   a  and a switch SW 4  are connected in series. The resistance values R 2  to R 4  are different from each other. For example, R 2 =0.8 kΩ, R 3 =1.5 kΩ and R 4 =3.0 kΩ. With such different resistance values, divided voltages of different voltage values can be easily generated. 
     Specifically, the circuits L 1  to L 4  are connected in parallel. One end of this parallel circuit is connected to the limit resistor  14  through the connecting line  15 , and the other end of the parallel circuit is connected to the ground point G. 
     Also, between the resistor  16   a  and the switch SW 2  of the circuit L 2 , three connecting points P 1  to P 3  are provided in order from the resistor  16   a  side. Similarly, between the resistor  17   a  and the switch SW 3  of the circuit L 3 , three connecting points P 4  to P 6  are provided in order from the resistor  17   a  side, and between the resistor  18   a  and the switch SW 4  of the circuit L 4 , three connecting points P 7  to P 9  are provided in order from the resistor  18   a  side. 
     Further, a switch SW 5  for short-circuiting the resistors  16   a  and  17   a  is provided between the connecting points P 1  and P 4 . Similarly, a switch SW 6  for short-circuiting the resistors  16   a  and  18   a  is provided between the connecting points P 2  and P 8 , a switch SW 7  for short-circuiting the resistors  17   a  and  18   a  is provided between the connecting points P 5  and P 7 , and a switch SW 8  for short-circuiting the resistors  16   a ,  17   a  and  18   a  is provided between the connecting points P 3  and P 6  (P 9 ). 
     The above four switches SW 5  to SW 8  have three contacts respectively and the middle contacts thereof are connected to the ground point G in common. 
     In the voltage dividing circuit  12   a  having above-described configuration, the switches SW 1  to SW 8  correspond to, respectively, eight keys (KEY 1  to KEY 8 ) to which the input operation is performed. The switches SW 1  to SW 4  compose the first switch group in the present invention and the switches SW 5  to SW 8  compose the second switch group in the present invention. 
     Thus, when the KEY 1  is operated, for example, one end of the connecting line  15  and the ground point G are short-circuited by the switch SW 1 . Therefore, a divided voltage generated in the voltage dividing circuit  12   a , that is, the input voltage V 1  supplied from the connecting point P to the output port  13  is indicated as V 1 =0. 
     When the KEY 2  is operated, one end of the resistor  16   a  and the ground point G are short-circuited by the switch SW 2 . Therefore, the input voltage V 1  is indicated as V 1 =V 0 ·R 2 /(R 1 +R 2 ). 
     When the KEY 3  is operated, one end of the resistor  17   a  and the ground point G are short-circuited by the switch SW 3 . Therefore, the input voltage V 1  is indicated as V 1 =V 0 ·R 3 /(R 1 +R 3 ). 
     When the KEY 4  is operated, one end of the resistor  18   a  and the ground point G are short-circuited by the switch SW 4 . Therefore, the input voltage V 1  is indicated as V 1 =V 0 ·R 4 /(R 1 +R 4 ). 
     When the KEY 5  is operated, one end of the resistor  16   a  and one end of the resistor  17   a  are short-circuited by the switch SW 5  and connected to the ground point G through the switch SW 5 . Therefore, the input voltage V 1  is indicated as V 1 =V 0 ·R 2 ·R 3 /(R 1 ·R 2 +R 1 ·R 3 +R 2 ·R 3 ). 
     When the KEY 6  is operated, one end of the resistor  16   a  and one end of the resistor  18   a  are short-circuited by the switch SW 6  and connected to the ground point G through the switch SW 6 . Therefore, the input voltage V 1  is indicated as V 1 =V 0 ·R 2 ·R 4 /(R 1 ·R 2 +R 1 ·R 4 +R 2 ·R 4 ). 
     When the KEY 7  is operated, one end of the resistor  17   a  and one end of the resistor  18   a  are short-circuited by the switch SW 7  and connected to the ground point G through the switch SW 7 . Therefore, the input voltage V 1  is indicated as V 1 =V 0 ·R 3 ·R 4 /(R 1 ·R 3 +R 1 ·R 4 +R 3 ·R 4 ). 
     When the KEY 8  is operated, one end of the resistor  16   a , one end of the resistor  17   a  and one end of the resistor  18   a  are short-circuited by the switch SW 8  and connected to the ground point G through the switch SW 8 . Therefore, the input voltage V 1  is indicated as V 1 =V 0 ·R 2 ·R 3 ·R 4 /(R 1 ·R 2 ·R 3 +R 1 ·R 2 ·R 4 +R 1 ·R 3 ·R 4 +R 2 ·R 3 ·R 4 ). 
     As described above, in the voltage dividing circuit  12   a , eight kinds of divided voltages of different values are generated by short-circuiting the predetermined portion in the circuit  12   a  with one of the switches SW 1  to SW 8  by key operation. And the divided voltages generated in the voltage dividing circuit  12   a  are supplied to the output port  13  through the connecting point P as the input voltage V 1 . 
     Next, the voltage dividing circuit  12   b  in  FIG. 3  includes four resistors, i.e. a resistor  16   b  whose resistance value is R 2 , a resistor  17   b  whose resistance value is R 3 , a resistor  18   b  whose resistance value is R 4  and a resistor  19   b  whose resistance value is R 5 . The voltage dividing circuit  12   b  is composed of a circuit L 11  where only a switch SW 11  is connected, a circuit L 12  where the resistor  16   b  and a switch SW 12  are connected, a circuit L 13  where the resistor  17   b  and a switch SW 13  are connected, a circuit L 14  where the resistor  18   b  and a switch SW 14  are connected, and a circuit L 15  where the resistor  19   b  and a switch SW 15  are connected. 
     Specifically, the circuits L 11  to L 15  are connected in parallel. One end of this parallel circuit is connected to the limit resistor  14  through the connecting line  15 , and the other end of the parallel circuit is connected to the ground point G. 
     Also, between the resistor  16   b  and the switch SW 12  of the circuit L 12 , seven connecting points P 11  to P 17  are provided in order from the resistor  16   b  side. Similarly, between the resistor  17   b  and the switch SW 13  of the circuit L 13 , seven connecting points P 18  to P 24  are provided in order from the resistor  17   b  side. Between the resistor  18   b  and the switch SW 14  of the circuit L 14 , seven connecting points P 25  to P 31  are provided in order from the resistor  18   b  side. Between the resistor  19   b  and the switch SW 15  of the circuit L 15 , seven connecting points P 32  to P 38  are provided in order from the resistor  19   b  side. 
     Further, between the connecting points P 11  and P 18 , a switch SW 16  for short-circuiting the resistors  16   b  and  17   b  is provided. Similarly, between the connecting points P 12 , and P 27 , a switch SW 17  for short-circuiting the resistors  16   b  and  18   b  is provided, and between the connecting points P 13  and P 33 , a switch SW 18  for short-circuiting the resistors  16   b  and  19   b  is provided. 
     Between the connecting points P 19  and P 25 , a switch SW 19  for short-circuiting the resistors  17   b  and  18   b  is provided. Between the connecting points P 20  and P 34 , a switch SW 20  for short-circuiting the resistors  17   b  and  19   b  is provided. Between the connecting points P 26  and P 32 , a switch SW 21  for short-circuiting the resistors  18   b  and  19   b  is provided. 
     Between the connecting points P 14  and P 21  (P 28 ), a switch SW 22  for short-circuiting the resistors  16   b ,  17   b  and  18   b  is provided. Between the connecting points P 15  and P 22  (P 35 ), a switch SW 23  for short-circuiting the resistors  16   b ,  17   b  and  19   b  is provided. 
     Between the connecting points P 16  and P 30  (P 37 ), a switch SW 24  for short-circuiting the resistors  16   b ,  18   b  and  19   b  is provided. Between the connecting points P 23  and P 29  (P 36 ), a switch SW 25  for short-circuiting the resistors  17   b ,  18   b  and  19   b  is provided. 
     Finally, between the connecting points P 17  and P 24  (P 31 , P 38 ), a switch SW 26  for short-circuiting the resistors  16   b ,  17   b ,  18   b  and  19   b  is provided. 
     The above eleven switches SW 16  to SW 26  have three contacts respectively and the middle contacts thereof are connected to the ground point G in common. 
     In the voltage dividing circuit  12   b  having above-described configuration, the switches SW 11  to SW 26  correspond to, respectively, sixteen keys (KEY 11  to KEY 26 ) to which the input operation is performed. The switches SW 11  to SW 15  compose the first switch group in the present invention and the switches SW 16  to SW 26  compose the second switch group in the present invention. 
     Thus, when the KEY 11  is operated, for example, one end of the connecting line  15  and the ground point G are short-circuited by the switch SW 11 . Therefore, the divided voltage generated in the voltage dividing circuit  12   b , that is, the input voltage V 1  supplied from the connecting point P to the output port  13  is indicated as V 1 =0. 
     Similarly, when the KEY 12  is operated, for example, one end of the resistor  16   b  and the ground point G are short-circuited by the switch SW 12 . Therefore, the input voltage V 1  is indicated as V 1 =V 0 ·R 2 /(R 1 +R 2 ). 
     Similarly, when any key of the KEY 13  to KEY 26  is operated, the predetermined input voltage V 1  is generated according to the circuit state produced by short-circuiting a resistor (resistors) with the switch corresponding to the operated key. 
     For example, when the KEY 16  is operated, one end of the resistor  16   b  and one end of the resistor  17   b  are short-circuited by the switch SW 16  and connected to the ground point G through the switch SW 16 . Therefore, the input voltage V 1  is indicated as V 1 =V 0 ·R 2 ·R 3 /(R 1 ·R 2 +R 1 ·R 3 +R 2 ·R 3 ). 
     Further, when the KEY 22  is operated, for example, one end of the resistor  16   b , one end of the resistor  17   b  and one end of the resistor  18   b  are short-circuited by the switch SW 22  and connected to the ground point G through the switch SW 22 . Therefore, the input voltage V 1  is indicated as V 1 =V 0 ·R 2 ·R 3 ·R 4 /(R 1 ·R 2 ·R 3 +R 1 ·R 2 ·R 4 +R 1 ·R 3 ·R 4 +R 2 ·R 3 ·R 4 . 
     As described above, in the voltage dividing circuit  12   b , sixteen kinds of divided voltages of different values are generated by short-circuiting the predetermined portion in the circuit  12   b  with one of the switches SW 11  to SW 26  by key operation. And the divided voltages generated in the voltage dividing circuit  12   b  are supplied to the output port  13  through the connecting point P as the input voltage V 1 . 
     When no key is operated in the voltage dividing circuits  12   a  and  12   b , the above-mentioned divided voltages are not generated in each voltage dividing circuit. Therefore, the input voltage V 1  having voltage value of V 0  is supplied from the power supply  11  to the output port  13  through the limit resistor  14 . 
     Consequently, if the voltage dividing circuit  12  in  FIG. 1  is the voltage dividing circuit  12   a  ( FIG. 2 ) including three resistors  16   a  to  18   a , nine kinds of input voltages V 1  of different values are supplied to the arithmetic processing circuit  20  through the output port  13 . Therefore, the arithmetic processing circuit  20  can identify nine different kinds of keys by performing a predetermined process based on the input voltages V 1 . Accordingly, compared to the circuit  12   c  in  FIG. 6  which can identify only five kinds of keys with three resistors, it is capable of identifying more keys, even though the voltage dividing circuit  12   a  has just the same three resistors as the circuit  12   c  in  FIG. 6 . 
     Similarly, if the voltage dividing circuit  12  in  FIG. 1  is the voltage dividing circuit  12   b  ( FIG. 3 ) including four resistors  16   b  to  19   b , seventeen kinds of input voltages V 1  of different values are supplied to the arithmetic processing circuit  20  through the output port  13 . Therefore, the arithmetic processing circuit  20  can identify seventeen different kinds of keys by performing a predetermined process based on the input voltages V 1 . Accordingly, compared to the circuit  12   d  in  FIG. 7  which can identify only six kinds of keys with four resistors, it is capable of identifying more keys, even though the voltage dividing circuit  12   b  has just the same four resistors as the circuit  12   d  in  FIG. 7 . 
     Next, the key identification will be described in detail. The key identification is executed using the conversion table  25   b  ( FIG. 1 ). Specifically, if the voltage dividing circuit  12  is the above-described voltage dividing circuit  12   a , the conversion table  25   b  has a table format illustrated in  FIG. 4 . If the voltage dividing circuit  12  is the above-described voltage dividing circuit  12   b , the conversion table  25   b  has a table format illustrated in  FIG. 5 . 
     In the conversion table  25   b  in  FIG. 4 , column  25   e  indicates keys to which the input operation is performed (hereinafter, described as “operation key”) and column  25   f  indicates a divided voltage generated in the voltage dividing circuit  12   a  when a corresponding key is operated, that is, the voltage value of the input voltage V 1  supplied to the output port  13 . Column  25   g  indicates key information outputted to the output unit  26  by the identification program  25   a  based on each voltage value of column  25   f.    
     Similarly, in the conversion table  25   b  in  FIG. 5 , column  25   q  indicates the operation key, column  25   r  indicates the divided voltage generated in the voltage dividing circuit  12   b  when a corresponding key is operated, that is, the voltage value of the input voltage V 1  supplied to the output port  13 . Column  25   s  indicates key information outputted to the output unit  26  by the identification program  25   a  based on the each voltage value of column  25   r.    
     When the voltage value of the input voltage V 1  which is supplied from the input circuit  10  having the voltage dividing circuit  12   a  to the arithmetic processing circuit  20  is, for example, V 1 =V 0 ·R 2 ·R 3 /(R 1 ·R 2 +R 1 ·R 3 +R 2 ·R 3 ), the identification program  25   a  executes the key identification under control of the control unit  21  with reference to the conversion table  25   b  in  FIG. 4  and determines that the KEY 5 , which is corresponding to the above voltage value V 1 , has been operated. Then, the identification program  25   a  outputs “CH UP”, which is key information of the KEY 5 , to the output unit  26 . 
     Similarly, when the voltage value of the input voltage V 1  which is supplied from the input circuit  10  having the voltage dividing circuit  12   b  to the arithmetic processing circuit  20  is, for example, V 1 =V 0 ·R 2 ·R 3 ·R 4 /(R 1 ·R 2 ·R 3 +R 1 ·R 2 ·R 4 +R 1 ·R 3 ·R 4 +R 2 ·R 3 ·R 4 ), the identification program  25   a  executes the key identification under control of the control unit  21  with reference to the conversion table  25   b  in  FIG. 5  and determines that the KEY 12 , which is corresponding to the above voltage value V 1 , has been operated. Then, the identification program  25   a  outputs “TILT DOWN”, which is key information of the KEY 12 , to the output unit  26 . 
     In this manner, in the voltage dividing circuits  12   a  and  12   b  of the present embodiment described above, a plurality of resistors included in the voltage dividing circuits are connected in parallel, and a plurality of switches for producing a short-circuit between each resistor and the ground point G or between a plurality of resistors and the ground point G are provided. Therefore, more switches are provided in comparison with the conventional voltage dividing circuits  12   c  and  12   d  where a plurality of resistors are connected in series. 
     Consequently, even if a voltage dividing circuit employs the same number of resistors as the conventional circuit, it is possible to generate more kinds of divided voltages than the conventional circuit. Therefore, it is capable of identifying more keys even though the voltage dividing circuit has just the same number of resistors as the conventional circuit. As a result, if the number of keys to be identified increases, it is possible to reduce the cost by suppressing the increase in the number of resistors. 
     The present invention can employ not only the aforementioned embodiment but also other various embodiments. For example, although the key input device  1  is described as a single device in the above embodiment, it is not limited thereto and the key input device  1  may be incorporated in the equipment such as DVD (Digital Versatile Disc) player as a part thereof. 
     In addition, in the above embodiment, although the conversion table  25   b  is formed as shown in  FIGS. 4 and 5 , it is not limited thereto and the key information may be set arbitrarily with respect to each voltage value. 
     Furthermore, in the above embodiment, resistance value of each resistor may be set arbitrarily as long as voltage values of the divided voltages (input voltages V 1 ) generated in the voltage dividing circuits  12   a  and  12   b  in  FIGS. 2 and 3  are not identical mutually. 
     
       
         
               
             
               
               
               
             
           
               
                   
               
               
                 Reference Signs List 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                   
                  1 
                 key input device 
               
               
                   
                 10 
                 input circuit 
               
               
                   
                 11 
                 power supply 
               
               
                   
                 12 
                 voltage dividing circuit 
               
               
                   
                 12a, 12b 
                 voltage dividing circuits 
               
               
                   
                 13 
                 output port 
               
               
                   
                 14 
                 limit resistor 
               
               
                   
                 15 
                 connecting line 
               
               
                   
                 16a-18a, 16b-19b 
                 resistors 
               
               
                   
                 20 
                 arithmetic processing circuit 
               
               
                   
                 21 
                 control unit 
               
               
                   
                 22 
                 input port 
               
               
                   
                 23 
                 A/D converter 
               
               
                   
                 24 
                 temporary memory 
               
               
                   
                 25 
                 memory 
               
               
                   
                 25a 
                 identification program 
               
               
                   
                 25b 
                 conversion table 
               
               
                   
                 26 
                 output unit 
               
               
                   
                 P1-P9, P11-P38 
                 connecting points 
               
               
                   
                 L1-L4, L11-L15 
                 circuits 
               
               
                   
                 SW1-SW8, SW11-SW26 
                 switches 
               
               
                   
                 G 
                 ground point 
               
               
                   
                 K 
                 key