Abstract:
A multi-layer printed circuit board for mounting memories, includes: laminated wiring layers on which wiring are arranged; and a plurality of interlayer connection components which electrically connect at least two of the wiring layers. At least one of the plurality of interlayer connection components is a blind via-hole.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a multi-layer printed circuit board. This application is based on Japanese Patent application No. 2006-347849, the disclosure of which is incorporated herein by reference. 
         [0003]    2. Description of Related Art 
         [0004]    In recent years, the package shape of a semiconductor device (hereafter, to be referred to as a logic part) for controlling a storage unit such as a memory is changed from a lead type to a CSP (Chip Size Package) type in which power source pins, ground pins and input/output pins can be arranged in a high density. At the same time, the increase in the number of the pins in the package is advanced, and restriction on pattern design of the printed circuit board on which the package is mounted is also increased. 
         [0005]      FIGS. 1 to 3  show the outer appearance of a logic part.  FIG. 1  is a top view of the logic part,  FIG. 2  is a side view, and  FIG. 3  is a view showing the rear side of the logic part. As shown in  FIG. 3 , many terminals are arranged on the rear side of the logic part. It should be noted that in  FIG. 3 , terminals for power sources and ground pins are shown inside the dashed line. 
         [0006]    The configuration of the printed circuit board for mounting the above logic part will be described below with reference to  FIGS. 4 to 8 . In  FIGS. 5 to 8 , an inter-layer connection component  1  for the connection between wiring layers, a conductor pattern  2 , and a mounting pad of the logic part are shown in  FIGS. 5 to 8 .  FIG. 4  shows a part mounting surface of the printed circuit board,  FIG. 5  shows a rear surface thereof, and  FIGS. 6 and 7  show the inner wiring layers, respectively.  FIG. 8  is an expanded view of a portion of the part mounting surface. 
         [0007]    As shown in  FIG. 4 , a large number of mounting pads  3  for mounting the logic part are provided on the part mounting surface in correspondence to terminals on the rear surface of the logic part. Conductors for signal lines are connected to the respective mounting pads  3 . Here, a conductor pattern  2  extending on the part-mounting surface is connected to the mounting pad  3  arranged on the relatively outer section side. 
         [0008]    On the other hand, by a wiring only on the part mounting surface, the signal line cannot be connected to the mounting pad  3  arranged on the central section side among the mounting pads  3 . This is because a space between the mounting pads  3  is occupied by the conductor patterns  2  extending for the mounting pads  3  on the relatively outer section side. Thus, an inter-layer connection component  1  is arranged to connect the mounting pad  3  on the central section side. That is, as shown in  FIGS. 6 and 7 , in the inner layer, the conductor pattern  2  as the signal line is extended to the central section and connected through the inter-layer connection component  1  to the mounting pad  3  on the part mounting surface. 
         [0009]    As the above-mentioned inter-layer connection component  1 , there are known a through-hole penetrating from the front to the rear of the board, a lead insertion hole described in a first conventional example (Japanese Laid Open Patent Application (JP-P2000-4086A)) and a via-holes described in a second conventional example (Japanese Laid Open Patent Application (JP-A-Heisei, 10-322027)). 
         [0010]    If the via-hole and the lead insertion hole are used as the inter-layer connection components  1 , it is possible to selectively connect a segment between the wiring layers. However, they require the manufacturing steps whose number is greater than that of the through-hole. Thus, in a memory mounting printed circuit board, the penetration through-holes have been used as the inter-layer connection components. 
         [0011]    In association with the increase in the number of pins in the logic part, wiring layers in the printed circuit board trend to be increased. As a specific example, when a wiring rule is considered in which one conductive pattern is arranged between the penetration through-holes, one wiring layer is required to be added to the printed circuit board each time the terminals of the logic part are increased for one line.  FIGS. 6 and 7  show such states. The increase in the wiring layer causes severe restriction on the printed circuit board design for a memory module. In the printed circuit board for the memory module, since the current form factors such as a socket are used, it is difficult to change the thickness of the printed circuit board. That is, the number of the layers must be increased without any change in the total thickness of the printed circuit board, and the thickness for one layer must be made thin. However, in case of the trial to make the thickness of each layer thin, a limit is in the process of manufacturing a fine structure of a conductor wiring and a constraint is from the viewpoint of the characteristic impedance of the wiring. Specifically, in the current memory module printed circuit board, it is difficult to exceed the 10 layers. 
         [0012]    Also, the increase in the number of pins in the logic part is required to be attained without any increase in the impedances of a power source wiring and a ground wiring on the printed circuit board. Anti-pads  5  to protect a short-circuit are required to be arranged at the positions corresponding to the penetration through-holes in all of the power source and ground layers in the printed circuit board.  FIG. 9  is a diagram showing the anti-pad  5 . In  FIG. 9 , the inter-layer connection component  1 , a conductor  6 , and a space  4  to prevent the short-circuit are shown. 
         [0013]      FIG. 10  shows a design example of the power source layer and ground layer in the board design shown in  FIGS. 4 to 6 . As shown in  FIG. 10 , a power source and ground area  6  is removed by the anti-pads  5 . That is, the power source and ground area is removed, resulting in the increase in the impedances of the power source and ground wirings in the printed circuit board. 
         [0014]    Therefore, the printed circuit board is demanded in which the number of pins in the logic part can be increased while suppressing the increase in the impedances of the power source and the ground wiring. 
         [0015]    Also, in the memory module, the memories and the logic parts must be efficiently mounted on the printed circuit board. Thus, parts for decreasing the impedances of the power source and the ground wirings can be efficiently mounted on the opposite side to the logic parts,  FIGS. 11 and 12  show this situation. 
         [0016]      FIG. 11  shows an example in which a typical logic part  8  and impedance decreasing parts  9  ( 9   a  to  9   e ) such as a chip capacitor are mounted, and  FIG. 12  shows an example in which the logic part  8  for the memory module, the memories  10   a  and  10   b  and an impedance decreasing part  9  are mounted. As shown in  FIG. 11 , in case of a typical module, many impedance decreasing parts  9  can be mounted on the side opposite to the logic part  8 . On the contrary, in case of the memory module shown in  FIG. 12 , the memories  10  must be mounted on the side opposite to the logic part  8 . Accordingly, the number of the mountable impedance decreasing parts  9  is extremely reduced. Thus, in the printed circuit board on which the memories are mounted, it is difficult to desirably decrease the impedance. That is, in particular, in the printed circuit board on which the memories are mounted, a technique is demanded that the increase of the impedance can be suppressed. 
       SUMMARY 
       [0017]    An object of the present invention is provide a multi-layer printed circuit board that can suppress the increase in the impedance. 
         [0018]    In a first aspect of the present invention, a multi-layer printed circuit board for mounting memories, includes: laminated wiring layers on which wiring are arranged; and a plurality of interlayer connection components which electrically connect at least two of the wiring layers. At least one of the plurality of interlayer connection components is a blind via-hole. 
         [0019]    According to the present invention, a multi-layer printed circuit board that can suppress the increase in the impedance is provided. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0020]    The above and other objects, advantages and features of the present invention will be more apparent from the following description of certain embodiments taken in conjunction with the accompanying drawings, in which: 
           [0021]      FIG. 1  is a top view of a logic part; 
           [0022]      FIG. 2  is a side view of the logic part; 
           [0023]      FIG. 3  is a rear view of the logic part; 
           [0024]      FIG. 4  is a plan view showing a layout in a part mounting surface of a conventional multi-layer printed circuit board; 
           [0025]      FIG. 5  is a plan view showing a layout in a rear surface of the conventional multi-layer printed circuit board; 
           [0026]      FIGS. 6 and 7  are diagrams showing layouts in an inner wiring layers of the conventional multi-layer printed circuit board; 
           [0027]      FIG. 8  is an expanded view of a portion of the part mounting surface; 
           [0028]      FIG. 9  is a view showing an anti-pad; 
           [0029]      FIG. 10  is a diagram showing a power source and ground layer of the conventional multi-layer printed circuit board; 
           [0030]      FIG. 11  is a sectional view showing an example in which a typical logic part and impedance decreasing parts are mounted; 
           [0031]      FIG. 12  is a sectional view showing an example in which a logic part for a memory module is mounted; 
           [0032]      FIG. 13  is a top view of a multi-layer printed circuit board according to a first embodiment of the present invention; 
           [0033]      FIG. 14  is a rear view of the multi-layer printed circuit board according to the first embodiment; 
           [0034]      FIGS. 15 and 16  are partially expanded views showing portions of the multi-layer printed circuit board in the first embodiment; 
           [0035]      FIG. 17  is a sectional view of the multi-layer printed circuit board in the first embodiment along the line AA′ shown in  FIG. 15 ; 
           [0036]      FIG. 18  is a view showing a layout of a layout on an inner wiring layer in the first embodiment; 
           [0037]      FIG. 19  is a partially expanded view of a portion of the multi-layer printed circuit board in the first embodiment shown in  FIG. 18 ; 
           [0038]      FIG. 20  is another partially expanded view of a portion of the multi-layer printed circuit board in the first embodiment shown in  FIG. 18 ; 
           [0039]      FIG. 21  is a view showing the wirings of a number Na that can be laid between inter-layer connection components; 
           [0040]      FIGS. 22A and 22B  are views showing different types of wirings; 
           [0041]      FIG. 23  is a view showing a power source and ground layer of the multi-layer printed circuit board according to the first embodiment; 
           [0042]      FIG. 24  is a view showing the power source and ground layer in which penetration through-holes are used; 
           [0043]      FIG. 25  is a sectional view of the multi-layer printed circuit board in which a penetration through-hole is used; 
           [0044]      FIG. 26  is a sectional view of a multi-layer printed circuit board in which a blind via-hole is used; 
           [0045]      FIG. 27  is a sectional view of the multi-layer printed circuit board in which a blind via-hole is used; 
           [0046]      FIG. 28  is a plan view showing the part mounting surface of the multi-layer printed circuit board according to a second embodiment of the present invention; 
           [0047]      FIG. 29  is a rear view showing a rear surface of the multi-layer printed circuit board according to the second embodiment; 
           [0048]      FIG. 30  is a plan view showing an inner wiring layer of the multi-layer printed circuit board according to the second embodiment; 
           [0049]      FIG. 31  is a view showing the power source and ground layer of the multi-layer printed circuit board according to the second embodiment; and 
           [0050]      FIG. 32  is a sectional view of the multi-layer printed circuit board according to the second embodiment. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0051]    Hereinafter, a multi-layer printed circuit board of embodiments of the present invention will be described in detail with reference to the attached drawings. 
       First Embodiment 
       [0052]      FIG. 13  is a top view of a multi-layer printed circuit board  11  according to a first embodiment of the present invention, and  FIG. 14  is a rear view showing the rear surface thereof. As shown in  FIGS. 13 and 14 , areas  12  ( 12   a  to  12   u ) for mounting memories, an area  13  for mounting a logic part and board connectors  14  ( 14   a ,  14   b ) are provided on the top and rear surfaces of the multi-layer printed circuit board  11 . 
         [0053]      FIGS. 15 and 16  are expanded views of portions of the multi-layer printed circuit board  11  shown in  FIGS. 13 and 14 . As shown in  FIGS. 15 and 16 , many terminals  15  are arranged in each of the areas  12  and the area  13  for connections to the logic part and the memories. 
         [0054]      FIG. 17  is a cross sectional view along the line AA′ shown in  FIG. 15 . As shown in  FIG. 17 , the multi-layer printed circuit board  11  has a structure in which a plurality of wiring layers (10 layers;  16   a  to  16   k ) are laminated. It should be noted that in this embodiment, a case that the wiring layers of 10 layers are laminated is described. However, the present invention can be applied to a case of 3 layers or more. 
         [0055]    In  FIG. 17 , terminals  15   a  to  15   d  for mounting a logic part  8  are shown on the uppermost layer  16   a  among the plurality of wiring layers  16   a  to  16   k . Also, terminals  17   a  and  17   b  for the board connector  14  are provided on the uppermost layer  16   a  and the lowermost layer  16   k  among the plurality of wiring layers  16   a  to  16   k , respectively. Among the plurality of wiring layers  16   a  to  16   k , the wiring layer  16   d  is an inner power source layer, and the wiring layer  16   g  is a ground layer. 
         [0056]    Inter-layer connection components  18  are connected to the respective terminals  15   a  to  15   d . These inter-layer connection components  18  are blind via-holes for carrying out the selective connections between the plurality of wiring layers. It should be noted that in this specification, the blind via-hole implies an inter-layer connection component for carrying out the connection between the layers without penetrating any wiring layer. Among the inter-layer connection components  18 , the inter-layer connection component  18  corresponding to the terminal  15   d  extends to the wiring layer  16   c  and is connected to a wiring  19   a  formed on the wiring layer  16   c . The wiring  19   a  is connected through a different inter-layer connection component to the terminal  17   a . That is, the terminal  15   d  for the logic part is electrically connected to the terminal  17   a  for the board connector. Similarly, the inter-layer connection component  18  connected to the terminal  15   b  extends to the wiring layer  16   h  and is connected to the wiring  19   b  formed on the wiring layer  16   h . The wiring  19   b  is connected through a different inter-layer connection component to the terminal  17   b . That is, the terminal  15   b  for the logic part is electrically connected to the terminal  17   b  for the board connector. 
         [0057]    In this way, since the blind via-holes are used as the inter-layer connection components  18 , the wiring  19   b  connected with the logic part terminal  15   b  and the board connector terminal  17   b  and the wiring  19   a  connected with the logic part terminal  15   d  and the board connector terminal  17   a  can be laid on a same section. Since the inter-layer connection component  18  connected to the terminal  15   d  does not extend to the wiring layer  16   h , the wiring  19   b  is not required to make a detour in a direction that is not parallel to the paper surface. This fact contributes to the improvement of the wiring density. 
         [0058]    Also, when the wiring layers  16   d  and  16   g  are the power source and ground layers, there is no case that the inter-layer connection components  18  corresponding to the terminal  15   d  penetrate through the power source and ground layers. Accordingly, the areas of the power source and ground layers can be made larger than those in a case that the penetration through-holes are used as the inter-layer connection components  18 . Also, even when the power source and ground layers  16   d  and  16   g  are reference layers of the wirings  19   a  and  19   b , the transmission line configuration, which is electrically uniform, can be attained without any suffering from the shape influence of the inter-layer connection components  18 . 
         [0059]    In succession, the wiring layout of the wiring layer as the inner layer will be described.  FIG. 18  is a diagram showing the wiring layout on the wiring layer (a first wiring layer)  16   h  among the plurality of wiring layers  16   a  to  16   k .  FIG. 19  is an expanded view of a region R shown in  FIG. 18 . 
         [0060]      FIG. 19  shows the arrangement of the plurality of inter-layer connection components  18  and the wirings  19 . A plurality of the inter-layer connection components  18  are the blind via-holes as mentioned above. Among the plurality of inter-layer connection components  18 , the inter-layer connection component  18  connected to the first wiring layer  16   h  is shown as a black circle. It should be noted that although being not electrically connected to any wiring  19  on the first layer  16   h , an inter-layer connection component  16  formed to extend the first layer  16   h  in a lamination direction without a connection is shown as if it is connected to the first layer  16   h . Also, the inter-layer connection component  18   b  that is not connected to the first layer  16   h  is shown by using a dotted line. On the other hand, the wiring  19  functions together with a different wiring as a differential wiring. 
         [0061]    Among all the inter-layer connection components  18  shown in  FIG. 19 , the inter-layer connection component  18   a  is adjacent to the inter-layer connection component  18   b . On the other hand, when only the inter-layer connection components  18  connected to the first layer  16   h  are considered, the inter-layer connection component  18   a  is adjacent to the inter-layer connection component  18   c  while putting the position corresponding to the inter-layer connection component  18   b  between them. 
         [0062]    In such a layout, the number Na of the wirings  19  that can be laid between the inter-layer connection component  18   a  and the inter-layer connection component  18   b  will be described with reference to  FIG. 21 .  FIG. 21  shows the wirings  19  of the number Na laid between the inter-layer connection components  18  ( 18   a  and  18   b ) adjacent to each other. It is supposed that the outer dimensions of the inter-layer connection components  18   a  and  18   c  are D 1  and D 2 , respectively, a minimal space between the (n)-th and (n+1)-th wirings  19  in view of the designing and manufacturing rules is G n , a width of the n-th wiring  19  is W n , minimal spaces between the inter-layer connection components  18  and the wirings adjacent thereto are E 1 , E 2 , respectively, and a distance between the centers of the inter-layer connection components  18  is P. In this case, as shown in  FIG. 21 , the wirings can be arranged for the number that satisfies the equation of P≧{(W 1 +W 2 + . . . +W Na−1 +W Na )+(G 1 +G 2 + - - - +G Na−1 )+(E 1 )+(E 2 )+(D 1 +D 2 )/2}. Oppositely, the wirings for the number that can satisfy the above equation can be laid. It should be noted that the width of a segment exceeding 50% of the wiring length is defined as W n  in the above equation, when the wiring width W n  changes in the middle of the wiring, as shown in  FIGS. 22A and 22B . Also, if there is no segment exceeding 50%, the width of the segment having the longest length of the wiring is defined as W n . In addition, if the inter-layer connection component  18   a  is, for example, circular, the foregoing “outer dimension” indicates an “outer diameter”. 
         [0063]    In the example shown in  FIG. 19 , the number Na of the wirings  19  that can be laid between the inter-layer connection component  18   a  and the inter-layer connection component  18   c  is 7 at the maximum because of the above-mentioned restraint on the number of wirings  19 . Actually, the 7 wirings  19  are laid. It should be noted that the inter-layer connection component  18   b  is the blind via-hole that is not connected to the first layer  16   h , and does not prevent the arrangement of the wirings  19 . 
         [0064]    On the other hand,  FIG. 20  shows an example when the inter-layer connection component  18   b ′ is assumed to be a penetration through-hole, for the sake of a comparison. In the example shown in  FIG. 20 , the existence of the inter-layer connection component  18   b ′ cannot be ignored. Thus, the maximal number Nb of the wirings that can be laid between the inter-layer connection components  18   a ′ and  18   b ′ is smaller than the number when the blind via-hole is used, and is 5. 
         [0065]    In this way, as can be understood from the comparison between  FIG. 19  and  FIG. 20 , since the inter-layer connection component  18   b  is the blind via-hole, many wirings, e.g., 7 wirings can be laid between the inter-layer connection components adjacent to each other in this embodiment. 
         [0066]    Also, in the example shown in  FIG. 20 , the inter-layer connection component  18   b ′ serves as an obstacle. Accordingly, there is a case that the width of the wiring  19 ′ must be made thin between the inter-layer connection component  18   a ′ and  18 ′. When the wiring width is changed depending on the position, the characteristics of transmission signals are not uniform. That is, this example indicates that the wirings are not electrically uniform. On the contrary, in the example shown in  FIG. 19 , the wirings  19  are constant in width, and are the electrically uniform wirings. In particular, when the wiring  19  is the differential wiring, the wiring cannot be laid on a different layer. Therefore, as described in the example shown in  FIG. 20 , the width of the wiring  19 ′ must be made thin and laid in many cases. 
         [0067]    Moreover, in the example shown in  FIG. 20 , the wiring  19 ′ is required to extend while being bent in order to avoid the inter-layer connection component  18   b ′. The bent segment has influence on the characteristic impedance of the wiring pattern and results in the factor that degrades the quality of the transmission signal. On the contrary, in the example shown in  FIG. 19 , the wiring  19  can extend straightly, and the bent segment can be reduced, which is preferable from the viewpoint of the signal quality. 
         [0068]    Next, the shapes of the layouts of the power source and ground layers will be described.  FIG. 23  shows a layout of the wiring layer  16   d  in the multi-layer printed circuit board according to this embodiment. That is,  FIG. 23  shows the layout of the power source layer. It should be noted that a layout of the ground layer that is the wiring layer  16   g  is also similar. On the other hand,  FIG. 24  shows the shape of the power source layer in the example in which all of the inter-layer connection components  18  are assumed to be the penetration through-holes, for a comparison. 
         [0069]    As can be understood from the comparison between  FIG. 23  and  FIG. 24 , since the inter-layer connection component  18  is the penetration through-hole, the number of the openings (the anti-pads) formed in the power source layer is decreased in this embodiment. That is, it is known that the impedance increase in the power source layer can be minimized since the area of the conductor can be set large. 
         [0070]    Also, as described in this embodiment, the use of the blind via-hole improves the quality of the transmission signal from the viewpoint of a stub (branch). The quality of the transmission signal and the stub will be described with reference to  FIGS. 25 to 27 .  FIG. 25  shows a sectional shape of a printed circuit board when a penetration through-hole is used as the inter-layer connection component  1 B. On the other hand,  FIGS. 26 and 27  are sectional views when the blind via-hole is used as the inter-layer connection component  18 . In all the examples shown in  FIGS. 25 to 27 , the wiring provided in the wiring layer  16   o  is connected to the terminal mounted on the uppermost layer  16   l  through the inter-layer connection component  18 . However, although the inter-layer connection component  18  penetrates through the board in the example shown in  FIG. 25 , the inter-layer connection component  18  only extends to the wiring layer  16   o  in the example shown in  FIG. 26 . Also, in the example shown in  FIG. 27 , the inter-layer connection component  18  extended to the wiring layer  16   p.    
         [0071]    In the example shown in  FIG. 25 , among the inter-layer connection components  18 , the segment (a stub  29 ) between the wiring layer  16   o  and the wiring layer  16   r  serves as a capacitive load. Such a capacitive load results in a factor that degrades the quality of the transmission signal. On the contrary, in the examples shown in  FIGS. 26 and 27 , the stub segment is perfectly removed ( FIG. 26 ) or reduced ( FIG. 27 ). That is, since the inter-layer connection component  18  is formed as the blind via-hole, the stub  29  can be removed or reduced, which can prevent the quality degradation in the transmission signal that is caused by the existence of the stub. 
       Second Embodiment 
       [0072]    Next, the multi-layer printed circuit board according to a second embodiment of the present invention will be described below with reference to  FIGS. 28 to 32 .  FIGS. 28 to 32  are diagrams showing the wiring layouts of the respective wiring layers in the multi-layer printed circuit board  11  according to this embodiment,  FIG. 28  shows a mounting surface  20  on which the memories are mounted,  FIG. 29  shows a rear surface  21 ,  FIG. 30  shows an inner wiring layer  22 , and  FIG. 31  shows a power source and ground layer  23 . Also,  FIG. 32  is a sectional view of the multi-layer printed circuit board  11 . As shown in  FIG. 32 , the rear surface layer  21 , the power source and ground layer  23 , the inner wiring layer  22  and the mounting surface  20  are laminated in this order in the multi-layer printed circuit board  11 . This multi-layer printed circuit board  11  contains penetration through-holes and blind via-holes as the inter-layer connection components  18 . 
         [0073]    As shown in  FIG. 28 , many terminals  24  for mounting the memories are arranged on the mounting surface  20 . Wirings  25  extending on the mounting surface  20  are connected to terminals  24  located on the outer side, among the terminals  24 . On the other hand, the wirings  25  extending from the inter-layer connection components  18  are connected to the terminals  24  located on the central side. 
         [0074]    As shown in  FIG. 30 , in the inner wiring layer  22 , wirings  26  are connected to the inter-layer connection components  18  on the outer side. The wirings  26  are not connected to the inter-layer connection components  18  on the central side. The inter-layer connection components  18  on the central side are formed to penetrate through the power source and ground layer  23  and further extend to the rear surface  21  of the lowermost layer. 
         [0075]    As shown in  FIGS. 29 and 32 , only the inter-layer connection components  18  on the central side are connected to the rear surface  21 . The wirings  27  extending on the rear surface  21  are connected to the inter-layer connection components  18  on the central side. 
         [0076]    As shown in  FIG. 31 , in the power source and ground layer  23 , anti-pads  28  are formed only in the positions corresponding to the inter-layer connection components  18  on the central side. The inter-layer connection components  18  connected to the wirings  26  on the inner wiring layer  22  are not required to further extend to the lower layer side. Thus, this has no influence on a layout of the power source and ground layer  23 . In this embodiment, an area of the anti-pad region in the power source and ground layer  23  can be reduced, as compared with the penetration through-holes shown in  FIG. 10 . As a result, the area of a conductor region in the power source and ground layer  23  can be increased, which can suppress the impedance increase that is caused by the formation of the anti-pads  28 . 
         [0077]    Although the present invention has been described above in connection with several embodiments thereof, it would be apparent to those skilled in the art that those embodiments are provided solely for illustrating the present invention, and should not be relied upon to construe the appended claims in a limiting sense.