Abstract:
A semiconductor integrated circuit comprises: a first signal delay circuit including a first precharge element configured to precharge a first node with a leakage current and a first signal output circuit configured to output a first signal; a second signal delay circuit including a second precharge element configured to precharge a second node with a leakage current and a second signal output circuit configured to output a second signal. The first signal delay circuit is configured to discharge the first node via a first discharge element, while the second signal delay circuit precharges the second node via the second precharge element and outputs the second signal. The second signal delay circuit is configured to discharge the second node via a second discharge element, while the first signal delay circuit precharges the first node via the first precharge element and outputs the first signal.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is based on and claims the benefit of priority from prior Japanese Patent Application No. 2008-207680, filed on Aug. 12, 2008, the entire contents of which are incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit that measures leakage currents flowing in transistors formed on a semiconductor substrate. 
         [0004]    2. Description of the Related Art 
         [0005]    Conventionally, there have been known various measuring devices for measuring a quality of a semiconductor integrated circuit formed on a semiconductor substrate (see Japanese Patent Application Laid-Open No. 11-101851). Japanese Patent Application Laid-Open No. 11-101851 discloses a delay time measuring circuit and a delay time measuring method for determining whether a semiconductor integrated circuit being tested is acceptable by measuring a transmission delay time in the semiconductor integrated circuit. 
         [0006]    There has also been a known structure that restricts variations in transistor characteristics in the semiconductor integrated circuit by measuring a leakage current in the transistor of the semiconductor integrated circuit and controlling a source voltage and a substrate bias in the semiconductor integrated circuit based on the measurement result. To measure the quality of each transistor formed on the semiconductor substrate, four-terminal transistors may be provided as a process monitor on a chip dicing line. In this case, however, it is necessary to prepare a special-purpose external measuring device that is connected to the transistors on the dicing line and measures the quality of each transistor. With this method, there is another problem that it is difficult to detect the locations of the transistors, after chips are cut out. 
         [0007]    As a transistor quality measuring method to counter those problems, there has been a method by which a monitor circuit is provided in the form of a ring oscillator or delay chain together with a semiconductor integrated circuit formed on each chip (disclosed by Tschanz, J. W., Narendra, S., Nair, R., and De, V., “Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors”, IEEE Journal of Solid-State Circuits, May 2003, Volume 38, Issue 5, p.p. 826-829). In the transistor measuring device using ring oscillators disclosed by Tschanz, et al, however, the rise time and the fall time of n-MOS transistors and p-MOS transistors affect respectively. As a result, the characteristics of the n-MOS transistors cannot be detected separately from the characteristics of the p-MOS transistors. 
       SUMMARY OF THE INVENTION 
       [0008]    A semiconductor integrated circuit according to one aspect of the present invention includes: a first signal delay circuit including a first discharge element having one end connected to a first node and configured to be switched between a conductive state and a nonconductive state by a first control signal to discharge the first node, a first precharge element connected between the first node and a power supply and configured to precharge the first node with a leakage current, and a first signal output circuit configured to compare a potential of the first node with a reference potential to output a first signal; a second signal delay circuit including a second discharge element having one end connected to a second node and configured to be switched between a conductive state and a nonconductive state by a second control signal to discharge the second node, a second precharge element connected between the second node and a power supply and configured to precharge the second node with a leakage current, and a second signal output circuit configured to compare a potential of the second node with a reference potential to output a second signal; a pulse signal generating circuit configured to generate a pulse signal having a pulse width determined by the first and second signals; a first delay circuit configured to delay the pulse signal to output the first control signal; and a second delay circuit configured to delay an inverted signal of the pulse signal to output the second control signal, the first signal delay circuit being configured to discharge the first node via the first discharge element, while the second signal delay circuit precharges the second node via the second precharge element and outputs the second signal; and the second signal delay circuit being configured to discharge the second node via the second discharge element, while the first signal delay circuit precharges the first node via the first precharge element and outputs the first signal. 
         [0009]    A semiconductor integrated circuit according to another aspect of the present invention includes: a third signal delay circuit including a third precharge element connected between a third node and a power supply and configured to be switched between a conductive state and a nonconductive state by a third control signal to precharge the third node, a third discharge element having one end connected to the third node and configured to discharge the third node with a leakage current, and a third signal output circuit configured to compare a potential of the third node with a reference potential to output a third signal; a fourth signal delay circuit including a fourth precharge element connected between a fourth node and a power supply and configured to be switched between a conductive state and a nonconductive state by a fourth control signal to precharge the fourth node, a fourth discharge element having one end connected to the fourth node and configured to discharge the fourth node with a leakage current, and a fourth signal output circuit configured to compare a potential of the fourth node with a reference potential to output a fourth signal; a pulse signal generating circuit configured to generate a pulse signal having a pulse width determined by the third and fourth signals; a third delay circuit configured to delay the pulse signal to output the third control signal; and a fourth delay circuit configured to delay an inverted signal of the pulse signal to output the fourth control signal, the third signal delay circuit being configured to precharge the third node via the third precharge element, while the fourth signal delay circuit discharges the fourth node via the fourth discharge element and outputs the fourth signal; and the fourth signal delay circuit being configured to precharge the fourth node via the fourth precharge element, while the third signal delay circuit discharges the third node via the third discharge element and outputs the third signal. 
         [0010]    A semiconductor integrated circuit according to still another aspect of the present invention includes: a first signal output circuit including a first precharge element connected between a first node and a power supply and configured to precharge the first node with a leakage current, the first signal output circuit being configured to output a first signal corresponding to a precharge speed of the first node; a second signal output circuit including a second precharge element connected between a second node and a power supply and configured to precharge the second node with a leakage current, the second signal output circuit being configured to output a second signal corresponding to a precharge speed of the second node; and a pulse signal generating circuit configured to generate a pulse signal having a pulse width determined by the first and second signals, the first signal output circuit being configured to discharge the first node, while the second signal output circuit precharges the second node via the second precharge element and outputs the second signal; and the second signal output circuit being configured to discharge the second node, while the first signal output circuit precharges the first node via the first precharge element and outputs the first signal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a block diagram showing a structure of a semiconductor integrated circuit in accordance with a first embodiment; 
           [0012]      FIG. 2  is a circuit diagram showing the semiconductor integrated circuit in accordance with the first embodiment; 
           [0013]      FIG. 3  is a timing chart showing the potentials of the respective nodes in the operation of the semiconductor integrated circuit in accordance with the first embodiment; 
           [0014]      FIG. 4  is a graph illustrating the advantages of the semiconductor integrated circuit in accordance with the first embodiment; 
           [0015]      FIG. 5  is a circuit diagram showing a semiconductor integrated circuit in accordance with a second embodiment; 
           [0016]      FIG. 6  is a timing chart showing the potentials of the respective nodes in the operation of the semiconductor integrated circuit in accordance with the second embodiment; and 
           [0017]      FIG. 7  is a graph illustrating the advantages of the semiconductor integrated circuit in accordance with the second embodiment. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0018]    The following is a description of embodiments of the present invention, with reference to the accompanying drawings. 
       First Embodiment 
     Structure of the Semiconductor Integrated Circuit of the First Embodiment 
       [0019]      FIG. 1  shows a fundamental structure of a semiconductor integrated circuit in accordance with an embodiment of the present invention, or structures of cores C having an integrated circuit formed on a semiconductor substrate and control circuits formed in the cores C. 
         [0020]    As shown in  FIG. 1 , the cores C (C 1  through C 4  in this embodiment) are formed on the semiconductor substrate. The control circuits are provided in the respective cores C 1  through C 4 . The control circuits measure the characteristics of transistors of the respective cores C. Based on the measured characteristics of the transistors, the source voltage and substrate bias of each core C are controlled, and variations in the transistor characteristics are restricted. In this embodiment, description is made of a structure in which a leakage current of each n-MOS transistor is measured, and the source voltage and substrate bias are controlled based on the measured characteristics of the n-MOS transistor. On the other hand, in a second embodiment that will be described later, description is made of a structure in which a leakage current of each p-MOS transistor is measured, and the source voltage and substrate bias are controlled based on the measured characteristics of the p-MOS transistor. The leakage current measurement may be collectively carried out on n-MOS transistors and p-MOS transistors. 
         [0021]    Although only the structure of each control circuit in the cores C is shown in  FIG. 1  for ease of explanation, a semiconductor integrated circuit is provided in each of the cores C, so that the cores C perform the respective certain operations. The cores C are not limited to arithmetic cores, but may be memory macros, small block units each forming part of a memory macro, or large block units each including arithmetic core group or the like. 
         [0022]    The control circuit in each of the cores C includes an n-MOS leak monitor  1 , a p-MOS leak monitor  2 , an oscillation counter  3 , an n-MOS substrate control circuit  4 , a p-MOS substrate control circuit  5 , and a source voltage control circuit  6 . 
         [0023]    The n-MOS leak monitor  1  measures the leakage current flowing in the n-MOS transistors formed in the core C. The p-MOS leak monitor  2  measures the leakage current flowing in the p-MOS transistors formed in the core C. The n-MOS leak monitor  1  and the p-MOS leak monitor  2  output pulse signals having a pulse width based on the leakage current amounts of the respective transistors. 
         [0024]    The oscillation counter  3  counts the number of oscillation of the pulse signal output from the n-MOS leak monitor  1  or the p-MOS leak monitor  2  within a certain period, so as to measure the leakage current amount of the n-MOS or p-MOS transistors. The n-MOS substrate control circuit  4  and the p-MOS substrate control circuit  5  each apply a forward substrate bias to the semiconductor substrate, if the leakage current amount of the n-MOS or p-MOS transistor is smaller than a certain value. The n-MOS substrate control circuit  4  and the p-MOS substrate control circuit  5  each apply a reverse substrate bias to the semiconductor substrate, if the leakage current amount of the n-MOS or p-MOS transistor is larger than the certain value. The source voltage control circuit  6  reduces the source voltage, if the leakage current amount of the n-MOS or p-MOS transistor is smaller than a certain value. The source voltage control circuit  6  increases the source voltage, if the leakage current amount of the n-MOS or p-MOS transistor is larger than the certain value. The n-MOS substrate control circuit  4 , the p-MOS substrate control circuit  5 , and the source voltage control circuit  6  may be designed to control the substrate bias and the source voltage, so that the number of oscillations, which is dependent on the leakage current amount of each transistor and counted by the oscillation counter  3 , has a constant value. 
         [0025]    Referring now to  FIG. 2 , an example structure of the n-MOS leak monitor  1  is described.  FIG. 2  is a circuit diagram showing the example structure of the n-MOS leak monitor  1  in accordance with this embodiment. 
         [0026]    The n-MOS leak monitor  1  includes signal delay circuits  10  and  20 , delay circuits  12  and  22 , a pulse signal generating circuit  30 , and an inverter  40 . 
         [0027]    The signal delay circuit  10  includes p-MOS transistors QP 11  and QP 12 , an n-MOS transistor QN 10 , and a comparator  11 . 
         [0028]    The two p-MOS transistors QP 11  and QP 12  are connected in series. The source of the transistor QP 12  is connected to a power supply VPRE (a voltage Vpre), and the drain of the transistor QP 11  is connected to a node N 12 . A node N 11  is connected to the gates of the two transistors QP 11  and QP 12 . When the potential of the node N 11  is in a “L” state, the two transistors QP 11  and QP 12  become conductive, so as to precharge the node N 12  up to the voltage Vpre of the power supply VPRE and increase the potential of the node N 12 . 
         [0029]    The n-MOS transistor QN 10  has its drain connected to the node N 12 , and has its gate and source grounded. The transistor QN 10  discharges the node N 12  by the leakage current flowing from the drain thereof connected to the node N 12  to the grounded source thereof, so as to reduce the potential of the node N 12 . The n-MOS leak monitor  1  measures the leakage current amount of the n-MOS transistor QN 10 . Here, the transistor QN 10  subject to the leakage current measurement is formed by the same procedures as the transistors used in the other circuits in the cores C, and has a certain relationship with other n-MOS transistors in the cores C in terms of characteristics. 
         [0030]    The comparator  11  has input terminals connected to the node N 12  and a node N 13  connected to a power supply VREF (a potential Vref). If the potential of the node N 12  is higher than the potential Vref of the node N 13 , the comparator  11  outputs a “H” signal to a node N 14 . If the potential of the node N 12  is lower than the potential Vref of the node N 13 , the comparator  11  outputs a “L” signal to the node N 14 . 
         [0031]    The signal delay circuit  10 , as a whole, delays the signal input from the node N 11  by the amount based on the leakage current amount of the n-MOS transistor QN 10 , and outputs the delayed signal to the node N 14 . 
         [0032]    The delay circuit  12  is formed by a plurality of inverters as buffers. The delay circuit  12  delays the later-described “H” signal or “L” signal of a node N 32  output from the pulse signal generating circuit  30  by a certain amount of time. The delay circuit  12  then provides the delayed signal to the node N 11 . 
         [0033]    The signal delay circuit  20  includes p-MOS transistors QP 21  and QP 22 , an n-MOS transistor QN 20 , and a comparator  21 . The transistors QP 21  and QP 22  of the signal delay circuit  20  are equivalent to the transistors QP 11  and QP 12  of the signal delay circuit  10 , and the n-MOS transistor QN 20  and the comparator  21  have the same structures as the n-MOS transistor QN 10  and the comparator  11 , respectively. Therefore, explanation of them is omitted herein. 
         [0034]    In the signal delay circuits  10  and  20  in the n-MOS leak monitor  1 , while discharging is performed on one of the nodes (the node N 12 , for example) and the leakage current amount of the transistor QN 10  is measured, precharging is performed on the other node (the node N 22 , for example). Accordingly, the precharging time of each of the nodes N 12  and N 22  does not affect the leakage current measurement based on the discharging time of each of the n-MOS transistors QN 10  and QN 20 . 
         [0035]    The delay circuit  22  is formed by a plurality of inverters as buffers. The delay circuit  22  delays the later-described “H” signal or “L” signal of a node N 31  output from the pulse signal generating circuit  30  by a certain amount of time. The delay circuit  22  then provides the delayed signal to the node N 21 . 
         [0036]    The pulse signal generating circuit  30  is a set/reset flip-flop circuit that has the node N 14  and the node N 24  connected to the input terminals of a logic gate  31  and a logic gate  32 , respectively. The pulse signal generating circuit  30  generates a pulse signal that has a pulse width determined based on the signals of the node N 14  and the node N 24 . The pulse signal is output as an output signal of the n-MOS leak monitor  1  via the inverter  40 . The node N 31  connected to the output terminal of the logic gate  31  is also connected to the node N 21  via the delay circuit  22 , and the node N 32  connected to the output terminal of the logic gate  32  is also connected to the node N 11  via the delay circuit  12 . 
       Operation of the Semiconductor Integrated Circuit of the First Embodiment 
       [0037]    Referring now to  FIG. 3 , the operation of the n-MOS leak monitor  1  is described.  FIG. 3  is a timing chart showing the potentials of the respective nodes in the operation of the n-MOS leak monitor  1  in accordance with this embodiment. 
         [0038]    The n-MOS leak monitor  1  starts measuring the leakage currents of the n-MOS transistors QN 10  and QN 20 , as the semiconductor integrated circuit starts operating. At time t 0 , the states of the nodes N 31  and N 32  that are output from the two logic gates  31  and  32  of the pulse signal generating circuit  30  switch from a “L” state to a “H” state, and from a “H” state to a “L” state, respectively. At time t 0 , each of the potentials of the nodes N 11 , N 22 , and N 24  is in a “H” state, and each of the potentials of the nodes N 12 , N 24 , and N 21  is in a “L” state. 
         [0039]    At time t 1 , the potential of the node N 31  in the “H” state is supplied to the node N 21 , with a certain delay being caused by the delay circuit  22 . As a result, the node N 21  changes from the “L” state to the “H” state. Likewise, the potential of the node N 32  in the “L” state is supplied to the node N 11 , with a certain delay being caused by the delay circuit  12 . As a result, the node N 11  changes from the “H” state to the “L” state. Here, the delay time caused by the delay circuits  12  and  22  is expressed as t 1 -t 0 . 
         [0040]    Since the potential of the node N 11  is in the “L” state, the gate of each of the p-MOS transistors QP 11  and QP 12  is put into the “L” state. As a result, the p-MOS transistors QP 11  and QP 12  become conductive, and the node N 12  is precharged by the power supply VPRE to have its potential switched to the “H” state. When the potential of the node N 12  exceeds the potential Vref of the node N 13 , the output signal of the comparator  11  is inverted, and the potential of the node N 14  switches from the “L” state to the “H” state. 
         [0041]    Meanwhile, due to the “H”-state potential supplied to the node N 21 , the p-MOS transistors QP 21  and QP 22  become nonconductive, and the precharging of the node N 22  is stopped. A leakage current flows from the node N 22  having the precharging stopped via the transistor QN 20 , and the potential gradually becomes smaller. 
         [0042]    At time t 2 , when the potential of the node N 22  becomes lower than the potential Vref of the node N 23 , the “H” state of the node N 24  output from the comparator  21  is inverted to the “L” state. 
         [0043]    At time t 3 , the potential of the node N 24  switches from the “H” state to the “L” state, and the output signal of the pulse signal generating circuit  30  is also inverted. Accordingly, the “L” state of the node N 24  is supplied to the logic gate  32 , and the node N 32  switches from the “L” state to the “H” state. The “H” state of the node N 32  and the “H” state of the node N 14  are supplied to the logic gate  31 , and the node N 31  switches from the “H” state to the “L” state. 
         [0044]    At time t 4 , the potential of the node N 32  having switched to the “H” state is supplied to the node N 11 , with a certain delay being caused by the delay circuit  12 . As a result, the node N 11  switches from the “L” state to the “H” state. Likewise, the potential of the node N 31  having switched to the “L” state is supplied to the node N 21 , with a certain delay being caused by the delay circuit  22 . As a result, the node N 21  switches from the “H” state to the “L” state. Here, the delay time caused by the delay circuits  12  and  22  is expressed as t 4 −t 3  (=t 1 −t 0 ). 
         [0045]    Due to the “H”-state potential supplied to the node N 11 , the p-MOS transistors QP 11  and QP 12  become nonconductive, and the precharging of the node N 12  is stopped after time t 4 . A leakage current flows from the node N 12  having the precharging stopped via the transistor QN 10 , and the potential gradually becomes smaller. 
         [0046]    Since the potential of the node N 21  is in the “L” state, the gate of each of the p-MOS transistors QP 21  and QP 22  is put into the “L” state. As a result, the p-MOS transistors QP 21  and QP 22  become conductive, and the node N 22  is precharged by the power supply VPRE to have its potential switched to the “H” state. When the potential of the node N 22  exceeds the potential Vref of the node N 23  (time t 4 −1), the output signal of the comparator  21  is inverted, and the potential of the node N 24  switches from the “L” state to the “H” state. 
         [0047]    As described above, in the n-MOS leak monitor  1 , while discharging is performed on the node N 12  of the signal delay circuit  10  and the amount of the leakage current flowing in the transistor QN 10  is measured, precharging is performed on the node N 22  of the signal delay circuit  20 . Accordingly, the precharging time of the node N 22  does not affect the leakage current measurement based on the discharging time of the n-MOS transistor QN 10 . 
         [0048]    At time t 5 , when the potential of the node N 12  becomes lower than the potential Vref of the node N 13 , the “H” state of the node N 14  output from the comparator  11  is inverted to the “L” state. 
         [0049]    At time t 6 , the potential of the node N 14  switches from the “H” state to the “L” state, and the output signal of the pulse signal generating circuit  30  is also inverted. Accordingly, the “L” state of the node N 14  is supplied to the logic gate  31 , and the node N 31  switches from the “L” state to the “H” state. The “H” state of the node N 31  and the “H” state of the node N 24  are supplied to the logic gate  32 , and the node N 32  switches from the “H” state to the “L” state. 
         [0050]    At time t 7 , the potential of the node N 31  having switched to the “H” state is supplied to the node N 21 , with a certain delay being caused by the delay circuit  22 . As a result, the node N 21  switches from the “L” state to the “H” state. Likewise, the potential of the node N 32  having switched to the “L” state is supplied to the node N 11 , with a certain delay being caused by the delay circuit  12 . As a result, the node N 11  switches from the “H” state to the “L” state. Here, the delay time caused by the delay circuits  12  and  22  is expressed as t 7 −t 6  (=t 4 −t 3 =t 1 −t 0 ). 
         [0051]    Since the potential of the node N 11  is in the “L” state, the gate of each of the p-MOS transistors QP 11  and QP 12  is put into the “L” state. As a result, the p-MOS transistors QP 11  and QP 12  become conductive, and the node N 12  is precharged by the power supply VPRE to have its potential switched to the “H” state. When the potential of the node N 12  exceeds the potential Vref of the node N 13 , the output signal of the comparator  11  is inverted, and the potential of the node N 14  switches from the “L” state to the “H” state. 
         [0052]    Due to the “H”-state potential supplied to the node N 21 , the p-MOS transistors QP 21  and QP 22  become nonconductive, and the precharging of the node N 22  is stopped after time t 7 . A leakage current flows from the node N 22  having the precharging stopped via the transistor QN 20 , and the potential gradually becomes smaller. 
         [0053]    At time t 8 , the potentials of the respective nodes become the same as the potentials observed at time t 2 . At time t 8 , time t 9 , time t 10  . . . , the n-MOS leak monitor  1  repeats a procedure carried out at time t 2 , time t 3 , time t 4  . . . , in a similar way. 
         [0054]    Accordingly, the state of the node N 31  repeatedly switches between the “H” state and the “L” state. The state of the node N 31  is output as an output signal of the n-MOS leak monitor  1  via the inverter  40 . 
         [0055]    In the measurement of the leakage current amount, the delay time caused by the delay circuits  12  and  22  (t 7 −t 6 =t 4 −t 3 =t 1 −t 0 ) is determined by the structure of the delay circuits  12  and  22 , and becomes a certain value. In addition, the time required for changing the state of the pulse signal generating circuit  30  (t 3 −t 2 , t 6 −t 5 , and t 9 −t 8 ) is also determined by the structure of the pulse signal generating circuit  30 , and becomes a certain value. 
         [0056]    Therefore, the time required for half a cycle of oscillations of the node N 31  (time t 2  through time t 5 ) is determined based on the time required for the potential of the node N 12  to decrease to the potential Vref (time t 4  to time t 5 ) due to the leakage current flowing in the transistor QN 10 . Likewise, the time required for half a cycle of oscillations of the node N 31  (time t 5  through time t 8 ) is determined based on the time required for the potential of the node N 22  to decrease to the potential Vref (time t 7  to time t 8 ) due to the leakage current flowing in the transistor QN 20 . Accordingly, the pulse signal output from the n-MOS leak monitor  1  has a frequency determined based on the leakage currents flowing in the n-MOS transistors QN 10  and QN 20 . 
         [0057]    In the n-MOS leak monitor  1 , while discharging is performed on the node N 12  of the signal delay circuit  10  and the amount of the leakage current flowing in the transistor QN 10  is measured, precharging is performed on the node N 22  of the signal delay circuit  20 . Likewise, while discharging is performed on the node N 22  of the signal delay circuit  20  and the amount of the leakage current flowing in the transistor QN 20  is measured, precharging is performed on the node N 12  of the signal delay circuit  10 . Since the n-MOS leak monitor  1  outputs the pulse signal based on the time required for the discharging of the nodes  12  and  22 , the time required for the precharging of the nodes N 12  and N 22  is not reflected in the pulse signal output from the n-MOS leak monitor  1 . 
         [0058]    The oscillation counter  3  measures the leakage current amounts of the n-MOS transistors QN 10  and QN 20  by counting the number of oscillation of the pulse signal output from the n-MOS leak monitor  1 . The n-MOS substrate control circuit  4  increases the substrate bias to be applied to the semiconductor substrate, if the values of the leakage current amounts in the n-MOS transistors QN 10  and QN 20  are smaller than a certain value. The n-MOS substrate control circuit  4  reduces the substrate bias to be applied to the semiconductor substrate, if the value of the leakage current amount in each transistor is equal to or larger than the certain value. The source voltage control circuit  6  reduces the source voltage, if the values of the leakage current amounts in the n-MOS transistors QN 10  and QN 20  are smaller than a certain value. The source voltage control circuit  6  increases the source voltage, if the value of the leakage current amount in each transistor is larger than the certain value. 
       Advantages of the Semiconductor Integrated Circuit of the First Embodiment 
       [0059]    As described above, the semiconductor integrated circuit of this embodiment has the n-MOS leak monitor  1  that outputs a signal having a frequency that is determined based on the leakage currents in the n-MOS transistors QN 10  and QN 20 . The signal output from the n-MOS leak monitor  1  corresponds to a discharge speed of the node N 11  and N 12 .  FIG. 4  shows the results of a simulation performed to measure the leakage currents in the n-MOS transistors with the use of the n-MOS leak monitor  1  shown in  FIG. 2 . In  FIG. 4 , the axis Vtn indicates the threshold voltage of the n-MOS transistors QN 10  and QN 20  of the n-MOS leak monitor  1 . The axis Vtp indicates the threshold voltage of the p-MOS transistors QP 11  and QP 12  or QP 21  and QP 22  of the n-MOS leak monitor  1 . The points of the threshold voltage  0  (V) on the axis Vtn and the axis Vtp indicate cases where there are the threshold voltages required for the respective transistors, and the axis Vtn and the axis Vtp indicate the fluctuations from the required threshold voltages. The ordinate axis indicates the oscillation cycle of the pulse signal output from the n-MOS leak monitor  1 . 
         [0060]    As shown in  FIG. 4 , if the threshold voltage fluctuates as the leakage current amounts in the n-MOS transistors QN 10  and QN 20  change in the n-MOS leak monitor  1 , the oscillation cycle of the pulse signal greatly changes. Meanwhile, if the threshold voltage fluctuates as the leakage currents in the p-MOS transistors QP 11  and QP 12  or QP 21  and QP 22  change, the oscillation cycle of the pulse signal hardly changes. Accordingly, the n-MOS leak monitor  1  can measure the leakage current amounts in the n-MOS transistors QN 10  and QN 20 , regardless of the leakage current amounts in the p-MOS transistors QP 11  and QP 12  or QP 21  and QP 22 . 
         [0061]    In the n-MOS leak monitor  1 , while discharging is performed on the node of one of the two n-MOS transistors QN 10  and QN 20  and the leakage current amount in the transistor is measured, precharging is performed on the node connected to the other transistor. Accordingly, the precharging time of the nodes N 12  and N 22  does not affect the measurement of the leakage currents in the n-MOS transistors QN 10  and QN 20 . 
         [0062]    In the n-MOS leak monitor  1 , the p-MOS transistors QP 11  and QP 12  or QP 21  and QP 22  are connected in series. When the p-MOS transistors become nonconductive and the leakage currents in the n-MOS transistors are measured, the voltage of the intermediate node between the two p-MOS transistors becomes lower. As a result, the drain-source voltage of each p-MOS transistor becomes lower, and the leakage currents from the p-MOS transistors decrease. At the same time, a substrate bias is applied to the p-MOS transistors QP 11  and QP 21 , and the leakage currents from the p-MOS transistors can be further reduced. In this manner, the measurement error due to the leakage currents from the p-MOS transistors QP 11  and QP 12  or QP 21  and QP 22  can be reduced. 
         [0063]    As described above, the semiconductor integrated circuit in accordance with this embodiment can accurately measure the leakage current of each n-MOS transistor, without adverse influence from the p-MOS transistors. 
       Second Embodiment 
     Structure of the Semiconductor Integrated Circuit of the Second Embodiment 
       [0064]    Referring now to  FIG. 5 , a second embodiment of a semiconductor integrated circuit in accordance with the present invention is described.  FIG. 5  is a circuit diagram showing an example structure of a p-MOS leak monitor  2  in accordance with this embodiment. 
         [0065]    The structure of the p-MOS leak monitor  2  in accordance with the second embodiment is substantially the same as the n-MOS leak monitor  1  in accordance with the first embodiment. In the p-MOS leak monitor  2  in accordance with the second embodiment, the same components as those of the first embodiment are denoted by the same reference numerals used in the first embodiment, and explanation of them is omitted herein. In the p-MOS leak monitor  2  in accordance with this embodiment, the structure of the signal delay circuit  10 ′ differs from the structure of the signal delay circuit  10  of the first embodiment. The p-MOS leak monitor  2  of this embodiment also differs from the n-MOS leak monitor  1  of the first embodiment in that each of the delay circuits  12  and  22  is formed with an odd number of inverters. 
         [0066]    The signal delay circuit  10 ′ includes an n-MOS transistor QP 13 , n-MOS transistors QN 14  and QN 15 , a comparator  11 , and an inverter  14 . 
         [0067]    The p-MOS transistor QP 13  has its drain connected to the node N 12 , and has its gate and source connected to a power supply VPRE (a voltage Vpre). The transistor QP 13  precharges the node N 12  by the leakage current flowing from the source thereof connected to the power supply VPRE to the drain thereof connected to the node N 12 , so as to increase the potential of the node N 12 . The p-MOS leak monitor  2  measures the leakage current amount in the p-MOS transistor QP 13 . Here, the transistor QP 13  subject to the leakage current measurement is formed by the same procedures as the transistors used in the other circuits in the cores C, and has a certain relationship with other p-MOS transistors in the cores C in terms of characteristics. 
         [0068]    The two n-MOS transistors QN 14  and QN 15  are connected in series. The drain of the transistor QN 14  is connected to the node N 12 , and the source of the transistor QN 15  is grounded. A node N 11  is connected to the gates of the two transistors QN 14  and QN 15 . When the potential of the node N 11  is in a “H” state, the two transistors QN 14  and QN 15  become conductive, so as to discharge the node N 12  and reduce the potential of the node N 12 . 
         [0069]    The comparator  11  has input terminals connected to the node N 12  and a node N 13  connected to the power supply VREF (a potential Vref). If the potential of the node N 12  is higher than the potential Vref of the node N 13 , the comparator  11  outputs a “H” signal to the inverter  14 , and the inverter  14  outputs a “L” signal to the node N 14 . If the potential of the node N 12  is lower than the potential Vref of the node N 13 , the comparator  11  outputs a “L” signal to the inverter  14 , and the inverter  14  outputs a “H” signal to the node N 14 . 
         [0070]    The signal delay circuit  10 ′, as a whole, delays the signal input from the node N 11  by the amount based on the leakage current amount in the p-MOS transistor QP 13 , and outputs the delayed signal to the node N 14 . 
         [0071]    The delay circuits  12  and  22  each formed with an odd number of inverters invert the “H” signal or “L” signal of nodes N 31  and N 32  output from the pulse signal generating circuit  30 , and then provide the inverted signal to the node N 11 . 
         [0072]    The signal delay circuit  20 ′ includes a p-MOS transistor QP 23 , n-MOS transistors QN 24  and QN 25 , a comparator  21 , and an inverter  24 . The transistor QP 23  of the signal delay circuit  20 ′ is equivalent to the transistor QP 13  of the signal delay circuit  10 ′, and the n-MOS transistors QN 24  and QN 25 , the comparator  21 , and the inverter  24  have the same structures as the n-MOS transistors QN 14  and  15 , the comparator  11 , and the inverter  14 , respectively. Therefore, explanation of them is omitted herein. 
         [0073]    In the signal delay circuits  10 ′ and  20 ′ in the p-MOS leak monitor  2 , while precharging is performed on one of the nodes (the node N 12 , for example) and the leakage current amount in the transistor QP 13  is measured, discharging is performed on the other node (the node N 22 , for example). Accordingly, the discharging time of one of the nodes N 12  and N 22  does not affect the leakage current measurement based on the precharging time of the other node. 
       Operation of the Semiconductor Integrated Circuit of the Second Embodiment 
       [0074]    Referring now to  FIG. 6 , the operation of the p-MOS leak monitor  2  is described.  FIG. 6  is a timing chart showing the potentials of the respective nodes in the operation of the p-MOS leak monitor  2  in accordance with this embodiment. 
         [0075]    The p-MOS leak monitor  2  starts measuring the leakage currents in the p-MOS transistors QP 13  and QP 23 , as the semiconductor integrated circuit starts operating. At time t 20 , the states of the nodes N 31  and N 32  that are output from the two logic gates  31  and  32  of the pulse signal generating circuit  30  switch from a “L” state to a “H” state, and from a “H” state to a “L” state, respectively. At time t 20 , each of the potentials of the nodes N 12 , N 21 , and N 24  is in a “H” state, and each of the potentials of the nodes N 11 , N 14 , and N 22  is in a “L” state. 
         [0076]    At time t 21 , the potential of the node N 31  having switched to the “H” state is inverted by the delay circuit  22 , and is supplied to the node N 21  with a certain delay. As a result, the node N 21  changes from the “H” state to the “L” state. Likewise, the potential of the node N 32  having switched to the “L” state is inverted by the delay circuit  12 , and is supplied to the node N 11  with a certain delay. As a result, the node N 11  changes from the “L” state to the “H” state. Here, the delay time caused by the delay circuits  12  and  22  is expressed as t 21 −t 20 . 
         [0077]    Due to the “H” state potential supplied to the node N 11 , the n-MOS transistors QN 14  and QN 15  become conductive, and the precharging of the node N 12  is stopped. A current flows from the node N 12  having the precharging stopped via the transistors QN 14  and QN 15 , and the potential switches from the “H” state to the “L” state. 
         [0078]    Meanwhile, since the potential of the node N 21  is in the “L” state, the gates of the n-MOS transistors QN 24  and QN 25  are put into the “L” state. As a result, the n-MOS transistors QN 24  and QN 25  become nonconductive, and the node N 22  is precharged with the leakage current from the p-MOS transistor QP 23 . 
         [0079]    At time t 22 , when the potential of the node N 22  becomes higher than the potential Vref of the node N 23 , the “H” state of the node N 24  output from the comparator  21  via the inverter  24  is inverted to the “L” state. 
         [0080]    At time t 23 , the potential of the node N 24  switches from the “H” state to the “L” state, and the output signal of the pulse signal generating circuit  30  is also inverted. Accordingly, the “L” state of the node N 24  is supplied to the logic gate  32 , and the node N 32  switches from the “L” state to the “H” state. The “H” state of the node N 32  and the “H” state of the node N 14  are supplied to the logic gate  31 , and the node N 31  switches from the “H” state to the “L” state. 
         [0081]    At time t 24 , the potential of the node N 32  having switched to the “H” state is inverted by the delay circuit  12 , and is supplied to the node N 11  with a certain delay. As a result, the node N 11  switches from the “H” state to the “L” state. Likewise, the potential of the node N 31  having switched to the “L” state is inverted by the delay circuit  22 , and is supplied to the node N 21  with a certain delay. As a result, the node N 21  switches from the “L” state to the “H” state. Here, the delay time caused by the delay circuits  12  and  22  is expressed as t 24 −t 23  (=t 21 −t 20 ). 
         [0082]    Since the potential of the node N 11  is in the “L” state, the gate of each of the n-MOS transistors QN 14  and QN 15  is put into the “L” state. As a result, the n-MOS transistors QN 14  and QN 15  become nonconductive, and the node N 12  is precharged with the leakage current from the p-MOS transistor QP 13 . 
         [0083]    Due to the “H”-state potential supplied to the node N 21 , the n-MOS transistors QN 24  and QN 25  become conductive, and the precharging of the node N 22  is stopped. A current flows from the node N 22  having the precharging stopped via the transistors QN 24  and QN 25 , and the potential switches from the “H” state to the “L” state. 
         [0084]    As described above, in the p-MOS leak monitor  2 , while precharging is performed on the node N 12  of the signal delay circuit  10 ′ and the amount of the leakage current flowing in the transistor QP 13  is measured, discharging is performed on the node N 22  of the signal delay circuit  20 ′. Accordingly, the discharging time of the node N 22  does not affect the leakage current measurement based on the precharging time of the node N 12 . 
         [0085]    At time t 25 , when the potential of the node N 12  becomes higher than the potential Vref of the node N 13 , the “H” state of the node N 14  output from the comparator  11  via the inverter  14  is inverted to the “L” state. 
         [0086]    At time t 26 , the potential of the node N 14  switches from the “H” state to the “L” state, and the output signal of the pulse signal generating circuit  30  is also inverted. Accordingly, the “L” state of the node N 14  is supplied to the logic gate  31 , and the node N 31  switches from the “L” state to the “H” state. The “H” state of the node N 31  and the “H” state of the node N 24  are supplied to the logic gate  32 , and the node N 32  switches from the “H” state to the “L” state. 
         [0087]    At time t 27 , the potential of the node N 31  having switched to the “H” state is inverted by the delay circuit  22 , and is supplied to the node N 21  with a certain delay. As a result, the node N 21  switches from the “H” state to the “L” state. Likewise, the potential of the node N 32  having switched to the “L” state is inverted by the delay circuit  12 , and is supplied to the node N 11  with a certain delay. As a result, the node N 11  switches from the “L” state to the “H” state. Here, the delay time caused by the delay circuits  12  and  22  is expressed as t 27 −t 26  (=t 24 −t 23 =t 21 −t 20 ). 
         [0088]    Due to the “H”-state potential supplied to the node N 11 , the n-MOS transistors QN 14  and QN 15  become conductive, and the precharging of the node N 12  is stopped. A current flows from the node N 12  having the precharging stopped via the transistors QN 14  and QN 15 , and the potential switches from the “H” state to the “L” state. 
         [0089]    Meanwhile, since the potential of the node N 21  is in the “L” state, the gate of each of the n-MOS transistors QN 24  and QN 25  is put into the “L” state. As a result, the n-MOS transistors QN 24  and QN 25  become nonconductive, and the node N 22  is precharged with the leakage current from the p-MOS transistor QP 23 . 
         [0090]    At time t 28 , the potentials of the respective nodes become the same as the potentials observed at time t 22 . At time t 28 , time t 29 , time t 30  . . . , the p-MOS leak monitor  2  repeats a procedure carried out at time t 22 , time t 23 , time t 24  in a similar way. 
         [0091]    Accordingly, the state of the node N 31  repeatedly switches between the “H” state and the “L” state. The state of the node N 31  is output as an output signal of the p-MOS leak monitor  2  via the inverter  40 . 
         [0092]    In the measurement of the leakage current amount, the delay time caused by the delay circuits  12  and  22  (t 27 −t 26 =t 24 −t 23 =t 21 −t 20 ) is determined by the structure of the delay circuits  12  and  22 , and becomes a certain value. In addition, the time required for changing the state of the pulse signal generating circuit  30  (t 23 −t 22 , t 26 −t 25 , and t 29 −t 28 ) is also determined by the structure of the pulse signal generating circuit  30 , and becomes a certain value. 
         [0093]    Therefore, the time required for half a cycle of oscillations of the node N 31  (time t 22  through time t 25 ) is determined based on the time required for the potential of the node N 12  to increase to the potential Vref (time t 24  to time t 25 ) due to the leakage current flowing in the transistor QP 13 . Likewise, the time required for half a cycle of oscillations of the node N 31  (time t 25  through time t 28 ) is determined based on the time required for the potential of the node N 22  to increase to the potential Vref (time t 27  to time t 28 ) due to the leakage current flowing in the transistor QP 23 . Accordingly, the pulse signal output from the p-MOS leak monitor  2  has a frequency determined based on the leakage currents flowing in the p-MOS transistors QP 13  and QP 23 . 
         [0094]    In the p-MOS leak monitor  2 , while precharging is performed on the node N 12  of the signal delay circuit  10 ′ and the amount of the leakage current flowing in the transistor QP 13  is measured, discharging is performed on the node N 22  of the signal delay circuit  20 ′. Likewise, while precharging is performed on the node N 22  of the signal delay circuit  20 ′ and the amount of the leakage current flowing in the transistor QP 23  is measured, discharging is performed on the node N 12  of the signal delay circuit  10 ′. Since the p-MOS leak monitor  2  outputs the pulse signal based on the time required for the precharging of the nodes  12  and  22 , the time required for the discharging of the nodes N 12  and N 22  is not reflected in the pulse signal output from the p-MOS leak monitor  2 . 
         [0095]    The oscillation counter  3  measures the leakage current amounts of the p-MOS transistors QP 13  and QP 23  by counting the number of oscillation of the pulse signal output from the p-MOS leak monitor  2 . The p-MOS substrate control circuit  5  increases the substrate bias to be applied to the semiconductor substrate, if the values of the leakage current amounts in the p-MOS transistors QP 13  and QP 23  are smaller than a certain value. The p-MOS substrate control circuit  5  reduces the substrate bias to be applied to the semiconductor substrate, if the value of the leakage current amount in each transistor is equal to or larger than the certain value. The source voltage control circuit  6  reduces the source voltage, if the values of the leakage current amounts in the p-MOS transistors QP 13  and QP 23  are smaller than a certain value. The source voltage control circuit  6  increases the source voltage, if the value of the leakage current amount in each transistor is larger than the certain value. 
       Advantages of the Semiconductor Integrated Circuit of the Second Embodiment 
       [0096]    As described above, the semiconductor integrated circuit of this embodiment has the p-MOS leak monitor  2  that outputs a signal having a frequency that is determined based on the leakage currents in the p-MOS transistors QP 13  and QP 23 . The signal output from the p-MOS leak monitor  2  corresponds to a precharge speed of the node N 11  and N 12 .  FIG. 7  shows the results of a simulation performed to measure the leakage currents in the p-MOS transistors with the use of the p-MOS leak monitor  2  shown in  FIG. 5 . 
         [0097]    As shown in  FIG. 7 , if the threshold voltage fluctuates as the leakage current amounts in the p-MOS transistors QP 13  and QP 23  change in the p-MOS leak monitor  2 , the oscillation cycle of the pulse signal greatly changes. Meanwhile, if the threshold voltage fluctuates as the leakage currents in the n-MOS transistors QN 14  and QN 15  or QN 24  and QN 25  change, the oscillation cycle of the pulse signal hardly changes. Accordingly, the p-MOS leak monitor  2  can measure the leakage current amounts in the p-MOS transistors QP 13  and QP 23 , regardless of the leakage current amounts in the n-MOS transistors QN 14  and QN 15  or QN 24  and QN 25 . 
         [0098]    In the p-MOS leak monitor  2 , while precharging is performed on the node of one of the two p-MOS transistors QP 13  and QP 23  and the leakage current amount in the transistor is measured, discharging is performed on the node connected to the other transistor. Accordingly, the discharging time of the nodes N 12  and N 22  does not affect the measurement of the leakage currents in the p-MOS transistors QP 13  and QP 23 . 
         [0099]    In the p-MOS leak monitor  2 , the n-MOS transistors QN 14  and QN 15  or QN 24  and QN 25  are connected in series. Accordingly, the measurement error due to the leakage currents to the n-MOS transistors QN 14  and QN 15  or QN 24  and QN 25  can be reduced, as in the first embodiment. 
         [0100]    As described above, the semiconductor integrated circuit in accordance with this embodiment can accurately measure the leakage current of each p-MOS transistor, without adverse influence from the n-MOS transistors. 
         [0101]    Although the embodiments of the present invention have been described, the present invention is not limited to those specific examples, and various modifications, additions, and combinations may be made to them in a range without departing from the scope of the invention. For example, each pair of the p-MOS transistors QP 11  and QP 12  and the p-MOS transistors QP 21  and QP 22  of the first embodiment, and then-MOS transistors QN 14  and QN 15  and the n-MOS transistors QN 24  and QN 25  of the second embodiment are connected in series. However, each of those pairs may be formed with one transistor. Also, the pulse signal generating unit  30  includes NAND gates as the logic gates  31  and  32 . However, NOR gates may be used as the logic gates to form the pulse signal generating unit  30 .