Abstract:
An apparatus comprising a first loss of signal circuit, a second loss of a signal circuit and a gate circuit. The first loss of a signal circuit may be configured to (i) receive an input signal containing a series of data and (ii) generate a first indication signal when the input signal is operating within a first frequency range. The second loss of signal circuit may be configured to (i) receive the input signal and (ii) generate a second indication signal when the input signal is operating within a second frequency range. The gate circuit may be configured to generate an output signal in response to either the first indication signal or the second indication signal being active.

Description:
FIELD OF THE INVENTION 
     The present invention relates to data transmission generally and, more particularly, to a method and/or apparatus for implementing an ultra-wideband loss of signal detector at a receiver in a high speed SERDES application. 
     BACKGROUND OF THE INVENTION 
     Conventional serializer and deserializer circuits (SERDES) are often used to transmit high speed parallel data across a lossy channel. For a set of high speed parallel data, the timing or synchronization is difficult to achieve when the set of data is sent out through different paths. 
     For this reason, the parallel data can be first converted into serial data in a transmitter. Then the transmitter will send out the serial data with a certain amplitude to a remote receiver across a lossy channel. The receiver then amplifies the attenuated input signal. The amplified signal is sampled by a clean clock to remove noise. The phase of the received signal is aligned to a well defined clock phase. The received serial signal is then converted back to a parallel digital signal. The channel is usually built by transmission lines in a printed circuit board. With higher data rates and longer channels, the loss is large. 
     Conventional approaches often implement a pre-emphasis circuit in the transmitter and a linear equalizer and decision feedback equalizer (DFE) in the receiver. The pre-emphasis and equalization circuits are built in the SERDES to remove inter-symbol interference (ISI). 
     The equalization circuits implemented in receivers tend to use a lot of power. If there are no real data received in the receivers, the equalization circuit can be powered down in order to save power, which needs a circuit to determine the effectiveness of the received signal. In general, a circuit with this function is called loss of signal detector (LOS). Conventional approaches implement a loss of signal detector at a receiver to continuously monitor the channel data and the link status. If the output of the loss of signal detector is high (or effective), an indication is sent that the channel data is lost or the received data is too small to power up the other signal processing circuit in the receiver. 
     A loss of signal detector includes a linear amplifier to amplify the received data, a rectifier to convert the amplified AC signal to DC voltage, a comparator to compare the rectified DC voltage with a reference voltage. The output of the comparator is sent to the digital control core of the SERDES. For data communication, the data rate processed by a SERDES is increased from a few Gbps up to 30 Gbps. Data rates tend to continuously increase as designs evolve. 
     To enable the loss of signal circuit to differentiate significantly attenuated data from noise is challenging. With the progress of CMOS technology, supply voltages tend to scale down, but the data rates tend to increase. The attenuation across a circuit board proportionally decreases the data rate. The overall effect is that with a smaller feature size, a lower supply voltage, a faster operating speed and a larger attenuation, the signal amplitude at the far end of a remote receiver decreases. The signal to noise ratio (SNR) also decreases. Therefore, the sensitivity of a LOS circuit has to increase. Since the received data could be in any frequency range (from 100 Mbps up to 30 Gbps), LOS circuits need to maintain an ultra wide bandwidth. 
     U.S. Pat. No. 6,377,082, entitled “Loss-of-Signal Detector for Clock Data Recovery Circuit”, discloses using clock and data recovery (CDR) circuit to detect the loss of signal. One drawback with such an approach is the reliance on the function of the CDR decision circuit. The pre-requirement for the functionality of a CDR decision circuit is that the input signal amplitude has to be large enough. Such an approach is power hungry since most of the blocks in receiver need to be powered on. 
     U.S. Pat. No. 4,868,470, entitled “Apparatus and Method for Detecting a True Average of N Signal Samples”, discloses an average detector in bipolar technology, which uses an input capacitor C, an output capacitor nC, and a number of diodes. Such an architecture can not be applied in low voltage CMOS process. 
     U.S. Pat. No. 7,102,392, entitled “Signal Detector for High-Speed SerDes”, discloses an improved signal detector by using two peaking amplifiers to amplify simultaneously the differential received signals and differential reference voltages. The major drawback is that such an approach consumes large amounts of power due to the power consumption of the peaking amplifier. Another issue is that the gain for the reference voltage from a peaking amplifier is a DC gain. The gain for input signal is a large-signal AC gain. The gain from these two peaking amplifiers can not be accurately matched. 
     It would be desirable to implement an ultra-wideband loss of signal detector that may be used at a receiver for high speed SERDES application. 
     SUMMARY OF THE INVENTION 
     The present invention concerns an apparatus comprising a first loss of signal circuit, a second loss of signal circuit and a gate circuit. The first loss of a signal circuit may be configured to (i) receive an input signal containing a series of data and (ii) generate a first indication signal when the input signal is operating within a first frequency range. The second loss of signal circuit may be configured to (i) receive the input signal and (ii) generate a second indication signal when the input signal is operating within a second frequency range. The gate circuit may be configured to generate an output signal in response to either the first indication signal or the second indication signal being active. In one example, three or more loss of signal circuits may be implemented. 
     The features and advantages of the present invention include providing a signal detector that may (i) detect signal loss at a receiver, (ii) operate in an ultra-wideband range, (iii) operate with a SERDES, (iv) implement multiple RXLOS circuits in parallel, (v) optimize each sub RXLOS block for a certain input frequency range, (vi) determine the final RXLOS digital output based on the outputs of individual RXLOS block, and/or (v) be easy to implement. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
         FIG. 1  is a block diagram of an embodiment of the present invention; 
         FIG. 2  is a block diagram of an individual circuit of  FIG. 1 ; 
         FIG. 3  is a detailed diagram of a CML buffer and peak detector; 
         FIG. 4  is a circuit diagram of a reference bias circuit; 
         FIG. 5  is a diagram of a comparator with boosted gain; 
         FIG. 6  is a block diagram of a receive front end; and 
         FIG. 7  is a waveform diagram of various signals of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Example embodiments of the present invention generally relate to a CMOS signal detector that may be used in a high speed data link to indicate the presence and/or absence of data on a receive channel. Embodiments of the present invention may implement a loss of signal detector in a high-speed SERDES receiver core that may determine the effectiveness of data received over an ultra-wide bandwidth range. 
     Referring to  FIG. 1 , a block diagram of a circuit  100  is shown in accordance with an embodiment of the present invention. The circuit  100  generally comprises a number of blocks (or circuits)  110   a - 110   n  and a block (or circuit)  112 . The circuits  110   a - 110   n  may be implemented as receive/loss circuits. The circuit  112  may be implemented as a gate, such as a logical AND gate. The circuit  100  may receive a signal (e.g., IN) and present a signal (e.g., OUT). The signal IN may represent an input signal. The signal IN may be an input signal that may contain a series of data. The data contained in the signal IN may operate at various frequencies. The signal OUT may represent an output signal. 
     Each of the circuits  110   a - 110   n  may receive the signal IN. The circuit  110   a  may present a signal (e.g., DOUT 1 ), the circuit  110   b  may present a signal (e.g., DOUT 2 ), and the signal  110   n  may present a signal (e.g., DOUTn). The circuit  112  may determine if one or more of the circuits  110   a - 110   n  present a corresponding one of the output signals DOUT 1 , DOUT 2 , DOUTn, etc. The signal OUT may represent a composite output that indicates when one or more of the circuits  110   a - 110   n  have detected a signal present at a particular frequency range. For example, if any one of the circuits  110   a - 110   n  detects data, then the signal OUT normally indicates data is present. The circuits  110   a - 110   n  may be each optimized (or calibrated) to detect activity on the signal IN at a particular frequency range. 
     The circuit  100  generally includes n (e.g., an integer greater than one) sub-RXLOS circuits  110   a - 110   n , generally operating in parallel. The particular number of circuits  110   a - 110   n  implemented may be varied to meet the design criteria of a particular implementation. For example, one of the RXLOS circuits  110   a - 110   n  may be designed to detect data having rates from around 100 Mbps to 4 Gbps. Another one of the circuits  110   a - 110   n  may be designed to detect data having a rate from 3 Gbps to 8 Gbps. Another one of the circuits  110   a - 110   n  may be designed to detect data having the highest input data rate, for example above 8 Gbps. If any one of the circuits  110   a - 110   n  indicates that the input signal is effective (e.g., present), the final digital output would be effective (e.g., present). With such a multi-detector approach, an ultra-wideband RXLOS may be implemented. 
     With current techniques, the design of a one loss of signal circuit having an ultra wide bandwidth (e.g., from 100 Mbps up to 30 Gbps) is almost impossible. However, the circuit  100  provides a design with a number of individual RXLOS circuits  110   a - 110   n , each operating within a certain bandwidth (e.g., from 100 Mbps to 2 Gbps, from 6 Gbps to 10 Gbps, etc.). 
     To further reduce the power consumption for low frequency band operation (e.g., from 100 Mbps to 2 Gbps), the design of the circuit  100  may be simplified so that power may be minimized. To further save the silicon area, if the circuit  100  is applied to a higher frequency range, capacitors in a rectifier block (to be discussed in more detail in connection with  FIG. 2  and  FIG. 3 ) may be minimized. In this way, the overall design may be optimized within a reasonable area and/or power consumption target. The general detected bandwidth of the circuit  100  may be extended to cover ranges up to 100 Mbps to 30 Gbps, or more. 
     Referring to  FIG. 2 , a block diagram of one of the RXLOS circuits (e.g.,  110   a ) is shown. The circuit  110   a  generally comprises a block (or circuit)  120 , a block (or circuit)  122  and a block (or circuit)  124 . The circuit  120  may be implemented as an amplifier circuit. The circuit  122  may be implemented as a rectifier/peak detector circuit. The circuit  124  may be implemented as a comparator circuit. The signal IN is shown broken into differential signal components (e.g., IN(RXP) and IN(RXN)). The circuit  120  may be implemented as a linear amplifier. The circuit  120  may amplify the input signals RXP and RXN to generate a signal VCMS (e.g., an amplified differential AC signal). The rectifier circuit  122  may convert the signal VCMS to DC value (e.g., VPK). The comparator circuit  124  may compare the rectified DC value VPK to a fixed reference (e.g., VREFP). The signal VCMS may also be presented to another input of the comparator  124 . The signal VCMS may be compared to a fixed reference (e.g., VREFN). The reference voltages VREFP and VREFN are generally designed to be adjustable in order to support different applications. The reference voltages VREFP and VREFN may be generated by a reference bias circuit (to be described in connection with  FIG. 3 ). 
     Referring to  FIG. 3 , a detailed diagram of the circuit  110   a  is shown along with a circuit  126 . The circuit  126  may be implemented as a reference bias circuit. The CML buffer circuit  120  generally comprises a resistor R 1 , a resistor R 2 , a transistor M 1 , a transistor M 2  and a transistor M 3 . The peak detector circuit  122  generally comprises a transistor M 5 , a transistor M 6 , a transistor M 7  and a capacitor CPD. In one example, the transistors M 1 , M 2 , M 3 , M 5 , M 6  and M 7  may be implemented as NMOS transistors. 
     The transistors M 6  and M 7  may be configured to pass voltages larger than a threshold voltage. The input signals to the gate of the transistors M 6  and M 7  are normally differential signals. A signal (e.g., VBN) may be presented to the transistor M 3  and/or the transistor M 5 . The signal VBN may be a bias voltage received from the reference bias circuit  126 . In half of the signal period, the input to the gate of the transistor M 7  is high and the input to the gate of the transistor M 6  is low. Therefore, in the first half of the signal period, the transistor M 6  is normally on, but the transistor M 7  is normally off. In another half period, the transistor M 6  would normally be turned off and the transistor M 7  would normally be turned on. In order to detect the envelope of the input signal, which may operate similar to an AM demodulator after rectification, an RC low pass filter may be applied to detect the signal envelope. The transistor M 5  and the capacitor CPD show one example of how to implement such an RC low pass filter. The corner frequency of the RC filter may be set based on the designed frequency range. For example, to implement a range of 100 Mbps to 4 Gbps, the capacitor CPD may have a value of 4 pF. To implement a range of 3 Gbps to BBbps, the capacitor CPD may have a value of 2 pF. To implement a range of above 8 Gbps, the capacitor CPD may have a value of 1 pF. However, the particular value of the capacitor CPD may be varied for each of the circuits  110   a - 110   n  to meet the design criteria of a particular implementation. 
     A poly resistor and/or poly current may be applied to the amplifier  120  (to be described in more detail in connection with  FIG. 4 ). An output common mode voltage is normally affected by supply variation. The variation of output common mode voltage may directly affect the rectified DC voltage VCMS. In order to reduce the negative impact of the output common mode voltage, the output common mode voltage is subtracted from the VPK. 
     Referring to  FIG. 4 , a more detailed diagram of the reference bias circuit  126  is shown. The reference bias circuit  126  is shown comprising a transistor MB 1 , a transistor MB 2 , a transistor MB 3 , an amplifier  160 , a transistor MB 4 , a resistor R 1   a , a resistor R 2   a , a resistor R 3   a , a resistor R 4   a , a resistor R 5 , a resistor R 6   a  transistor Q 1  and a transistor Q 2 . The resistor R 4   a , R 5  and R 6  form a divider network used to generate the signal VREFP and/or VREFN. The resistors R 1   a , R 2   a , R 3   a , R 4   a , R 5  and/or R 6  may be implemented as poly resistors. A poly current (e.g., I_POLY), which is equal to the ratio of a constant bandgap voltage and poly resistors flowing through MB 3  and MB 4 , is generated from the reference bias block. 
     Referring to  FIG. 5 , the circuit  124  generally comprises a number of transistors M 8 -M 23 . As shown in  FIG. 4 , to track the supply voltage variation, the input reference VREFP and VREFN are generated by a resistive divider. In an example implementation, a four input comparator is shown. The transistors M 13  and M 14  may be cross-coupled to provide a negative impedance that may cancel the relatively small positive impedance from the transistors M 12  and/or M 15  to boost the DC gain of the comparator circuit  124 . 
     Referring to  FIG. 6 , a receiver front end illustrating a differential signal received by the circuit  100  is shown. The signals RXP and/or RXN may be AC coupled (e.g., through a capacitor  162  and/or  164 ) to the circuit  100  and/or to a circuit  170 , and/or a circuit  172 . A common mode voltage in the signal RX may be generated after the AC coupling capacitor so that the following circuits are able to further process this received signal. In a high speed SERDES architecture, the signals after AC coupling capacitors  162  and/or  164  may be sent to voltage controlled amplifier (VGA)  172  and the RXLOS circuit  100  in parallel. 
     As described in connection with  FIG. 1 , the circuit  100  may implement multiple individual RXLOS blocks  110   a - 110   n  in parallel. For each of the individual RXLOS block  110   a - 110   n , parameters may be optimized to implement certain desired frequency ranges. An ultra-wide bandwidth operation may be achieved without much tuning and/or without large power consumption. 
     For each RXLOS block (as shown in  FIG. 3 ) the AC coupled differential signals are shown being sent to the differential pair of NMOS transistors M 1  and M 2 . The transistors M 3  and M 5  may provide the necessary bias current. The transistors M 1  and M 2  and the resistors R 1  and R 2  may implement an amplifier (or CML buffer) to linearly amplify the received signal. In order to maintain a constant output common mode voltage, the bias current VBN is specially designed (e.g., using the poly current I_POLY), which may be generated from bandgap core and may be equal to the ratio of a constant bandgap voltage and poly resistor. The poly resistors R 1  and R 2  may be used as the load of the amplifier. A product of a value of the poly resistor and the poly current I_POLY may be implemented to be constant over process, voltage and temperature (PVT) variations, which would secure the stability of output common mode voltage. 
     The circuit  100  divides a large frequency range (e.g., from 100 Mbps to 30 Gbps) into multiple smaller frequency ranges. Each smaller range has a narrower frequency band than the overall operating range. The amplifier  120  may be optimized to have a relatively flat gain response. The detection errors due to gain variation may be minimized. 
     The amplified signals may be differential signals and may have a high speed signal swing. In order to rectify the output signals, a diode and/or a RC low pass filter are generally applied. Due to the low supply voltage (e.g., 0.95V nominal) and standard CMOS technology, a current CMOS rectifier may be used to convert the differential high speed AC signals to low speed DC signals. The DC signal may then be sent to a low speed comparator. 
     Referring to  FIG. 7 , a waveform illustrating an example illustration of one of the RXLOS circuits  110   a - 110   n  is shown. The signal RX is shown as an AC coupled square wave. The signal DOUT is shown as being set high when the input amplitude is smaller than a certain threshold, which is generally called loss of signal. The signal DOUT is set to be low when the input amplitude is larger than the predetermined target threshold. The signal VPK_VCMS may be a rectified and/or low pass filtered signal. When the input amplitude is high, the voltage VPK_VCMS is DC high. When the input amplitude is low, the voltage VPK_VCMS is DC low. The reference voltage does not change with the input amplitude, which is set to be a standard to evaluate the amplitude of the rectified signal. 
     If the RXLOS circuit  110   a  is optimized for a frequency range from 10 Gbps to 30 Gbps, the RXLOS circuit  110   b  is optimized for a frequency range from 2 Gbps to 10 Gbps and the RXLOS circuit  110   n  is optimized for a frequency range from 100 Mbps to 2 Gbps, the overall circuit  100  may be set to meet the frequency range from 100 Mbsp to 30 Gbps. The overall digital output signal OUT may be derived from the individual RXLOS digital outputs DOUT 1 -Doutn. The combinational logic  112  may be implemented by a CMOS AND gate. 
     An example truth table for digital output of the circuit  100  is shown as the following TABLE 1: 
     
       
         
               
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 RXLOS1 
                 RXLOS2 
                 RXLOS3 
                 RXLOS Total 
               
               
                   
                   
               
             
             
               
                   
                 0 
                 0 
                 0 
                 0 
               
               
                   
                 0 
                 0 
                 1 
                 0 
               
               
                   
                 0 
                 1 
                 0 
                 0 
               
               
                   
                 0 
                 1 
                 1 
                 0 
               
               
                   
                 1 
                 0 
                 0 
                 0 
               
               
                   
                 1 
                 0 
                 1 
                 0 
               
               
                   
                 1 
                 1 
                 0 
                 0 
               
               
                   
                 1 
                 1 
                 1 
                 1 
               
               
                   
                   
               
             
          
         
       
     
     The various signals of the present invention are generally “on” (e.g., a digital HIGH, or 1) or “off” (e.g., a digital LOW, or 0). However, the particular polarities of the on (e.g., asserted) and off (e.g., de-asserted) states of the signals may be adjusted (e.g., reversed) accordingly to meet the design criteria of a particular implementation. 
     The terms “may” and “generally” when used herein in conjunction with “is(are)” and verbs are meant to communicate the intention that the description is exemplary and believed to be broad enough to encompass both the specific examples presented in the disclosure as well as alternative examples that could be derived based on the disclosure. The terms “may” and “generally” as used herein should not be construed to necessarily imply the desirability or possibility of omitting a corresponding element. 
     The present invention may also be implemented by the preparation of ASICs (application specific integrated circuits), Platform ASICs, FPGAs (field programmable gate arrays), PLDs (programmable logic devices), CPLDs (complex programmable logic device), sea-of-gates, RFICs (radio frequency integrated circuits), ASSPs (application specific standard products), one or more integrated circuits, one or more chips or die arranged as flip-chip modules and/or multi-chip modules or by interconnecting an appropriate network of conventional component circuits, as is described herein, modifications of which will be readily apparent to those skilled in the art(s). 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the invention.