Abstract:
A method of fabricating a three dimensional integrated circuit comprises forming a redistribution layer on a first side of a packaging component, forming a holding chamber in the redistribution layer, attaching an integrated circuit die on the first side of the packaging component, wherein an interconnect bump of the integrated circuit die is inserted into the holding chamber, applying a reflow process to the integrated circuit die and the packaging component and forming an encapsulation layer on the packaging component.

Description:
This application is a divisional of U.S. patent application Ser. No. 13/452,636, entitled “Method of Fabricating Three Dimensional Integrated Circuit,” filed on Apr. 20, 2012, which application is incorporated herein by reference. 
    
    
     BACKGROUND 
     The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. As the demand for even smaller electronic devices has grown recently, there has grown a need for smaller and more creative packaging techniques of semiconductor dies. 
     As semiconductor technologies evolve, three dimensional integrated circuits have emerged as an effective alternative to further reduce the physical size of a semiconductor chip. In a three dimensional integrated circuit, active circuits such as logic, memory, processor circuits and the like are fabricated on different wafers and each wafer die is stacked on top of a packaging component using pick-and-place techniques. Much higher density can be achieved by employing three dimensional integrated circuits. In sum, three dimensional integrated circuits can achieve smaller form factors, cost-effectiveness, increased performance and lower power consumption. 
     A three dimensional integrated circuit may comprise an integrated circuit die, an interposer and a package substrate. More particularly, the integrated circuit die is attached to a first side of the interposer through a plurality of solder bumps. Solder bumps are used to provide electrical connection between the integrated circuit die and the interposer. A second side of the interposer is attached to the package substrate by a plurality of interconnect bumps. Interconnect bumps such as solder balls may provide electrical connection between the interposer and the package substrate, which in turn makes electrical connection to a printed circuit board through a plurality of package leads. 
     In order to reduce the potential solder failure between the integrated circuit die and the package substrate caused by thermal stresses, the interposer is employed to provide a matching coefficient of thermal expansion to the integrated circuit die. The interposer also provides adaptation between smaller contact pads with reduced pitch on an integrated circuit die and larger contact pads with increased pitch on a package substrate. In addition, the interposer may further comprise a variety of circuit elements. These circuit elements may be active, passive, or a combination of active and passive elements. 
     Three dimensional integrated circuits have some advantages. One advantageous feature of packaging multiple semiconductor dies vertically is that three dimensional package techniques may reduce fabrication costs. Another advantageous feature of three dimensional semiconductor devices is that parasitic losses are reduced by employing various interconnect bumps. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  illustrates a cross sectional view of a three dimensional integrated circuit in accordance with an embodiment; 
         FIG. 2  illustrates a cross sectional view of placing an interposer on a carrier in accordance with an embodiment; 
         FIG. 3  illustrates a cross sectional view of forming a plurality of openings in a dielectric layer in accordance with an embodiment; 
         FIG. 4  illustrates a cross sectional view of the semiconductor device shown in  FIG. 3  after a seed layer is formed on top of the dielectric layer in accordance with an embodiment; 
         FIG. 5  illustrates a cross sectional view of forming a plurality of openings in a photoresist layer in accordance with an embodiment; 
         FIG. 6  illustrates a cross sectional view of the semiconductor device shown in  FIG. 5  after a redistribution layer is formed on top of the seed layer in accordance with an embodiment; 
         FIG. 7  illustrates a cross sectional view of the semiconductor device shown in  FIG. 6  after the photoresist layer has been removed in accordance with an embodiment; 
         FIG. 8A  illustrates a top view of a portion of a redistribution layer in accordance with an embodiment; 
         FIG. 8B  illustrates a perspective view of placing a micro bump into a holding structure in accordance with an embodiment; 
         FIG. 9  illustrates a cross sectional view of the semiconductor device shown in  FIG. 7  after an integrated circuit die is bonded on the interposer in accordance with an embodiment; 
         FIG. 10  illustrates a process of removing the carrier from the semiconductor device shown in  FIG. 9 ; 
         FIG. 11  illustrates a cross sectional view of the semiconductor device shown in  FIG. 10  after a redistribution layer is formed on the second side of the interposer; 
         FIG. 12  illustrates a cross section view of the semiconductor device shown in  FIG. 11  after a plurality of under bump metallization structures have been formed in accordance with an embodiment; and 
         FIG. 13  illustrates a process of separating the semiconductor device shown in  FIG. 12  into individual chip packages using a dicing process. 
     
    
    
     Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale. 
     DETAILED DESCRIPTION 
     The making and using of the present embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the embodiments of the disclosure, and do not limit the scope of the disclosure. 
     The present disclosure will be described with respect to embodiments in a specific context, a three dimensional integrated circuit. The embodiments of the disclosure may also be applied, however, to a variety of semiconductor devices. Hereinafter, various embodiments will be explained in detail with reference to the accompanying drawings. 
       FIG. 1  illustrates a cross sectional view of a three dimensional integrated circuit in accordance with an embodiment. A three dimensional integrated circuit  100  may comprise an integrated circuit die  102  stacked on a package component  106 . As shown in  FIG. 1 , the integrated circuit die  102  is attached to a first side of the package component  106  through a plurality of interconnect components including metal pillar bumps  122 , micro bumps  120  and redistribution layers  124 . In addition, there may be an encapsulation layer  104  formed on top of the packaging component  106 . In particular, the integrated circuit  102  and the interconnect components (e.g., micro bumps  120  and redistribution layer  124 ) are embedded in the encapsulation layer  104 . 
     In accordance with an embodiment, the packaging component  106  may be an interposer. For simplicity, throughout the description, the packaging component  106  may be alternatively referred to as an interposer  106 . The interposer  106  may be made of silicon, glass and/or the like. As shown in  FIG. 1 , the interposer  106  may comprise a plurality of vias  116  embedded in the interposer  106 . The interposer  106  may further comprise a first side redistribution layer  124  formed on top of a seed layer  118  over the first side of the interposer  106 . After the integrated circuit dies  102  is bonded on the interposer  106 , the active circuits of the integrated circuit die  102  are coupled to the vias of the interposer  106  through a conductive channel formed by the seed layer  118 , the redistribution layer  124 , micro bumps  120  and the metal pillar bumps  122 . 
     A second side of the interposer  106  may be attached to a package substrate (not shown) by a plurality of interconnect bumps  110 . In accordance with an embodiment, these interconnect bumps  110  may be solder balls. As shown in  FIG. 1 , the redistribution layer  124  is connected to its corresponding through via  116  by a seed layer  118 . Furthermore, the through via  116  is connected to its corresponding interconnect bump  110  through a redistribution layer  114  and an under bump metallization structure  112 . As such, the metal pillar bump  122 , solder ball  120 , the redistribution layer  124 , the seed layer  118 , the through via  116 , the redistribution layer  114 , the under bump metallization structure  112  and the interconnect bump  110  may form a conductive path between the active circuits of the integrated circuit die  102  and the package substrate (not shown), which in turn makes electrical connection to a printed circuit board through a plurality of package leads. 
       FIGS. 2-13  are cross sectional views of intermediate stages in the making of a three dimensional integrated circuit in accordance with an embodiment.  FIG. 2  illustrates a cross sectional view of placing an interposer on a carrier in accordance with an embodiment. As shown in  FIG. 2 , a second side of the interposer  106  is mounted on the carrier  202 . In particular, the second side of the interposer  106  is glued on top of the carrier  202  by employing an adhesive  204 . In accordance with an embodiment, the adhesive  204  may be epoxy and/or the like. 
     The carrier  202  may be formed of a wide variety of materials comprising glass, silicon, ceramics, polymers and/or the like. 
       FIG. 3  illustrates a cross sectional view of forming a plurality of openings in a dielectric layer in accordance with an embodiment. A dielectric layer  128  is formed on top of the interposer  106 . The dielectric material may comprise polybenzoxazole (PBO), SU-8 photo-sensitive epoxy, film type polymer materials and/or the like. In consideration of electrical and thermal needs, selective areas of the dielectric layer  128  are exposed to light. As a result, a variety of openings (e.g., opening  302 ) are formed. The formation of the openings such as opening  302  in the dielectric layer  128  involves lithography operations, which are well known, and hence are not discussed in further detail herein. 
       FIG. 4  illustrates a cross sectional view of the semiconductor device shown in  FIG. 3  after a seed layer is formed on top of the dielectric layer in accordance with an embodiment. In order to provide a nucleation site for the subsequent bulk metal deposition, a thin seed layer  402  is deposited on the dielectric layer  128 . The thin seed layer  402  may comprise copper. The thin seed layer  402  may be implemented by using suitable fabrication techniques such as physical vapor deposition (PVD), chemical vapor deposition (CVD) or the like. 
       FIG. 5  illustrates a cross sectional view of forming a plurality of openings in a photoresist layer in accordance with an embodiment. A photoresist layer  502  is formed on top of the thin seed layer  402 . The photoresist layer  502  may comprise SU-8 photo-sensitive epoxy, film type polymer materials and/or the like. In consideration of electrical needs, selective areas of the photoresist layer  502  are exposed to light. As a result, a variety of openings (e.g., opening  504 ) are formed. 
       FIG. 6  illustrates a cross sectional view of the semiconductor device shown in  FIG. 5  after a redistribution layer is formed on top of the seed layer in accordance with an embodiment. As shown in  FIG. 6 , a conductive material fills the openings (e.g., opening  504 ) to form a redistribution layer  124 . The conductive material may be copper, but can be any suitable conductive materials, such as copper alloys, aluminum, tungsten, silver and combinations thereof. The redistribution layer  124  may be formed by suitable techniques such as an electrochemical plating process. 
       FIG. 7  illustrates a cross sectional view of the semiconductor device shown in  FIG. 6  after the photoresist layer has been removed in accordance with an embodiment. The remaining photoresist layer  502  shown in  FIG. 6  may be removed by using suitable photoresist stripping techniques such as plasma ashing, dry stripping and/or the like. The photoresist stripping techniques are well known and hence are not discussed in further detail herein to avoid repetition. 
     In accordance with an embodiment, a suitable etching process such as wet-etching or dry-etching may be applied to the exposed portion of the thin seed layer  402 . As a result, the exposed portion of the thin seed layer  402  has been removed. The detailed operations of either the dry etching process or the wet etching process are well known, and hence are not discussed herein to avoid repetition. 
     It should be recognized that while  FIG. 7  illustrates the interposer  106  with a single redistribution layer, the interposer  106  could accommodate any number of redistribution layers. The number of redistribution layers illustrated herein is limited solely for the purpose of clearly illustrating the inventive aspects of the various embodiments. The present disclosure is not limited to any specific number of redistribution layers. 
       FIG. 8A  illustrates a top view of a portion of a redistribution layer in accordance with an embodiment. The redistribution layer  804  may comprise a holding structure for accommodating a micro bump in the subsequent fabrication process. In accordance with an embodiment, the holding structure includes a holding chamber  802  and a trench  801 . The holding chamber  802  may be a cavity having a circular shape so that the micro bump can fit into the holding chamber  802 . 
     It should be noted that the cavity (e.g., the holding chamber  802 ) are substantially circular in shape as shown in  FIG. 8A . It is within the scope and spirit of various embodiments for the cavity to comprise other shapes, such as, but no limited to oval, square, rectangular and the like. 
     Both the holding chamber  802  and the trench  801  may be formed by employing suitable patterning techniques. Referring back to  FIG. 5 , in order to form the trench  801  and the holding chamber  802 , after patterning, photoresist materials may cover the portions of the holding chamber and the trench. As a result, during the fabrication step shown in  FIG. 6 , the metal material cannot fill the holding chamber and the trench. After a photoresist stripping process, the holding chamber  802  and the trench  801  are formed after the remaining photoresist materials in the holding chamber and the trench have been removed. 
       FIG. 8B  illustrates a perspective view of placing a micro bump into a holding structure in accordance with an embodiment. The micro bump  806  has a round terminal. The cavity of the redistribution layer  804  can accommodate the round terminal of the micro bump  806 . As such, when an integrated circuit die having micro bumps are bonded on an interposer, the micro bumps can be held by the cavities of the redistribution layer without bonding pads. In addition, the trench  801  is employed to provide a passage through which the solder and flux gases may flow during the subsequent reflowing process shown in  FIG. 9 . 
     One advantageous feature of having the holding structure shown in  FIG. 8B  is that the holding structure enables finer spacing between adjacent interconnects. In addition, by employing the holding structure without bonding pads, smaller keep-out zones can be achieved so as to reduce bump-to-bump clearance. 
       FIG. 9  illustrates a cross sectional view of the semiconductor device shown in  FIG. 7  after an integrated circuit die is bonded on the interposer in accordance with an embodiment. An integrated circuit die  102  is mounted on the interposer  106 . More particularly, each micro bump of the integrated circuit die  102  is inserted into a corresponding holding chamber in the redistribution layer (not shown but illustrated in  FIG. 8B ). A reflow process is performed so that the integrated circuit die  102  is connected to the interposer  106  through the melted micro bumps. Furthermore, an encapsulation layer  104  is formed on top of the interposer  106  to protect the top surface of the redistribution layer from erosion. In addition, the encapsulation layer  104  is thick enough to mechanically support the integrated circuit die  102  in the subsequent fabrication steps. As such, the three dimensional integrated circuit can be detached from the carrier  202 . 
       FIG. 9  shows the integrated circuit die  102  without details. It should be noted that the integrated circuit die  102  may comprise basic semiconductor layers such as active circuit layers, substrate layers, inter-layer dielectric (ILD) layers and inter-metal dielectric (IMD) layers (not shown). The integrated circuit die  102  may comprise a silicon substrate. Alternatively, the integrated circuit die  102  may comprise a silicon-on-insulator substrate. The integrated circuit die  102  may further comprise a variety of electrical circuits (not shown). The electrical circuits formed in the integrated circuit die  102  may be any type of circuitry suitable for a particular application. 
     In accordance with an embodiment, the electrical circuits may include various n-type metal-oxide semiconductor (NMOS) and/or p-type metal-oxide semiconductor (PMOS) devices such as transistors, capacitors, resistors, diodes, photo-diodes, fuses and the like. The electrical circuits may be interconnected to perform one or more functions. The functions may include memory structures, processing structures, sensors, amplifiers, power distribution, input/output circuitry or the like. One of ordinary skill in the art will appreciate that the above examples are provided for illustrative purposes only to further explain applications of the present disclosure and are not meant to limit the present disclosure in any manner. 
     The encapsulation layer  104  may be formed of underfill materials. In accordance with an embodiment, the underfill material may be an epoxy, which is dispensed at the gap between the interposer  106  and the integrated circuit die  102 . The epoxy may be applied in a liquid form, and may harden after a curing process. In accordance with another embodiment, encapsulation layer  104  may be formed of curable materials such as polymer based materials, resin based materials, polyimide, epoxy and any combinations of thereof. The encapsulation layer  104  can be formed by a spin-on coating process, dry film lamination process and/or the like. 
     Alternatively, the encapsulation layer  104  may be a molding compound layer formed on top of the wafer stack. The molding compound layer may be formed of curable materials such as polymer based materials, resin based materials, polyimide, epoxy and any combinations of thereof. The molding compound layer can be formed by a spin-on coating process, an injection molding process and/or the like. In order to reliably handle the integrated circuit die  102  mounted on top of the interposer  106  during subsequent fabrication process steps such as a backside fabrication process of the interposer  106 , the molding compound layer is employed to keep the interposer  106  and the integrated circuit die  102  on top of the interposer  106  from cracking, bending, warping and/or the like. 
       FIG. 10  illustrates a process of removing the carrier from the semiconductor device shown in  FIG. 9 . In accordance with an embodiment, the carrier  202  can be detached from the three dimensional integrated circuit including the integrated circuit die  102  and the interposer  106 . A variety of detaching processes may be employed to separate the three dimensional integrated circuit from the carrier  202 . The variety of detaching processes may comprise a chemical solvent, a UV exposure and the like. 
       FIG. 11  illustrates a cross sectional view of the semiconductor device shown in  FIG. 10  after a redistribution layer is formed on the second side of the interposer. The redistribution layer  114  is formed of conductive materials such as copper, copper alloys, aluminum, tungsten, silver and combinations thereof. The formation of a redistribution layer has been described above with respect to  FIGS. 5-7 , and hence is not discussed in further detail to avoid unnecessary repetition. 
       FIG. 12  illustrates a cross section view of the semiconductor device shown in  FIG. 11  after a plurality of under bump metallization structures have been formed in accordance with an embodiment. A dielectric layer  108  is formed over the redistribution layer  114 . A plurality of under bump metallization structures  112  may be formed on top of the redistribution layers  114 . The under bump metallization structures  112  may help to prevent diffusion between the interconnect bumps  110  and the interposer  106 , while providing a low resistance electrical connection. 
     A plurality of interconnect bumps  110  are formed on the under bump metallization structures  112 . The interconnect bumps  110  provide an effective way to connect the three dimensional integrated circuit with external circuits (not shown). In accordance with an embodiment, the interconnect bumps  110  may be a plurality of solder balls. Alternatively, the interconnect bumps  110  may be a plurality of land grid array (LGA) pads. 
       FIG. 13  illustrates a process of separating the semiconductor device shown in  FIG. 12  into individual chip packages  1302  and  1304  using a dicing process. The dicing process is well known in the art, and hence is not discussed in detail herein. 
     Although embodiments of the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. 
     Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.