Abstract:
A method of manufacturing a semiconductor integrated circuit device is provided. The method includes forming a plurality of pillars in a semiconductor substrate, forming an insulating layer between the plurality of pillars in such a manner that an upper region of each pillar protrudes, forming a silicide layer on an exposed surface of the pillar, and forming an insulating layer for planarization in a space between pillars.

Description:
CROSS-REFERENCES TO RELATED APPLICATION 
       [0001]    This application claims priority under 35 U.S.C. 119(a) to Korean application No. 10-2014-0070977, filed on Jun. 11, 2014, in the Korean intellectual property Office, which is incorporated by reference in its entirety as set forth in full. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    The inventive concept relates to a method of manufacturing a three dimensional (3D) semiconductor integrated circuit device, and more particularly, to a switching device of a 3D semiconductor integrated circuit device. 
         [0004]    2. Related Art 
         [0005]    Memory devices are generally provided as internal semiconductor integrated circuit devices of computers or other electronic apparatuses. As is well-known, typical examples of memory devices include random access memories (RAMs), read only memories (ROMs), dynamic RAMs (DRAMs), synchronous DRAM (SDRAM), flash memories, and variable resistive memory devices. Variable resistive memory devices include programmable conductive memory devices, resistive RAMs (ReRAMs), and phase-change RAMs (PCRAMs). 
         [0006]    Nonvolatile memory devices, such as PCRAMs, may be used in broad electronic applications to provide high integration density, high reliability, and low power consumption. 
         [0007]    The variable resistive memory devices may include a plurality of memory cells arranged in matrix form. The memory cell may include an access device such as a diode, an electric field effect (FET) transistor, or a bipolar junction transistor (BJT), and may be coupled to a word line arranged along a row direction of an array. Memory elements in the memory cells may be coupled to a bit line arranged in a column direction of the array. Through this manner, the access device of the memory cell may select a word line coupled to a gate. The memory cell may be accessed through a row decoder which activates the row of the memory cell. 
         [0008]    Currently, transistors having a 3D vertical channel structure are used as the access device of memory cells to increase integration density. As is well-known, transistors having 3D vertical channel structures include pillar-shaped active regions, gates formed on a circumference of the active region, drains formed in an upper portion of the active region and at a higher level than the gates, and sources formed in a lower portion of the active region and at a lower level than the gate or formed in a semiconductor substrate which is in contact with the lower portion of the active region. A heating electrode and a variable resistance layer electrically coupled to a bit line are further formed on the transistor. To facilitate ohmic contact between the drain and the heating electrode, an ohmic contact layer, for example, a silicide layer, is formed between the drain and the heating electrode. 
         [0009]    Endeavors for improving the operation current in variable resistive memory devices using 3D transistors as access devices continue, and various methods for improving the operation current have been suggested. 
       SUMMARY 
       [0010]    According to an embodiment, there is provided a method of manufacturing a semiconductor integrated circuit device. The method may include forming a plurality of pillars in a semiconductor substrate having a first conductivity type, forming a first Insulating layer between the plurality of pillars in such a manner that an upper portion of each of the plurality of pillars protrudes over the first insulating layer, forming a silicide layer over the upper portion of the plurality of pillars, and forming a second insulating layer between the plurality of pillars in which silicide layers are formed. 
         [0011]    According to an embodiment, there is provided a method of manufacturing a semiconductor integrated circuit device. The method may include forming a plurality of pillars in a semiconductor substrate having a first conductivity type, forming a gate surrounding a circumference of each of the plurality of pillar; forming a preliminary common source region in the semiconductor substrate between the gate and a neighboring gate, wherein the preliminary common source region is provided between the plurality of pillars, forming a drain in an upper portion of each of the plurality of pillars, wherein the drain is located at a level higher than the gate, filling a first insulating layer between the plurality of pillars in such a manner that a drain which is formed in each of the plurality of the pillars protrudes over the first insulating layer, forming a silicide layer over the drain, forming a second insulating layer filling in a space between the plurality of pillars, and forming a lower electrode coupled to the silicide layer. 
         [0012]    According to an embodiment, there is provided a method of manufacturing a semiconductor integrated circuit device. The method may include forming a pillar extending from a semiconductor substrate, the pillar including a lower portion, a middle portion and an upper portion, forming a gate over a sidewall of the middle portion of the pillar, forming a first high concentration impurity region in the upper portion of the pillar, forming a second high concentration impurity region along a surface of the first high concentration impurity region, forming a conductive layer over the second high concentration impurity region, and performing heat treatment to react the conductive layer and the second high concentration impurity region to form a silicide layer. 
         [0013]    The method may further comprises forming a preliminary common source region in the substrate between the pillar and a neighboring pillar, wherein impurities included in the preliminary common source region are diffused during the heat treatment to form a common source, and wherein the common source is commonly coupled to the lower portion of the pillar and a lower portion of the neighboring pillar. 
         [0014]    These and other features, aspects, and embodiments are described below in the section entitled “DETAILED DESCRIPTION”. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]    The above and other aspects, features and advantages of the subject matter of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: 
           [0016]      FIGS. 1A to 1L  are plan views illustrating a method of manufacturing a semiconductor integrated circuit device according to an embodiment; 
           [0017]      FIGS. 2A to 2L  are cross-sectional views illustrating the method of manufacturing a semiconductor integrated circuit device taken along line II-II′ of  FIGS. 1A to 1L ; and 
           [0018]      FIGS. 3A to 3L  are cross-sectional views illustrating the method of manufacturing a semiconductor integrated circuit device taken along line III-III′ of  FIGS. 1A to 1L . 
       
    
    
     DETAILED DESCRIPTION 
       [0019]    Exemplary embodiments will be described in greater detail with reference to the accompanying drawings. Exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic Illustrations of exemplary embodiments (and intermediate structures). As such, variations from the shapes of the illustrations depending on, for example, manufacturing techniques and/or tolerances are to be expected. Thus, exemplary embodiments should not be construed as limited to the particular shapes illustrated but may include deviations that may result, for example, from manufacturing techniques. In the drawings, lengths and sizes of layers and regions may be exaggerated for clarity. Like reference numerals in the drawings denote like elements. It is also to be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other or substrate, or intervening layers may also be present. 
         [0020]    Referring to  FIGS. 1A ,  2 A, and  3 A, a pad insulating layer  115  and a hard mask layer  120  are sequentially formed on a semiconductor substrate  100 . Predetermined portions of the hard mask layer  120  and the pad insulating layer  115  may be patterned to define an active region. The semiconductor substrate  100  may be etched by a predetermined depth using the patterned hard mask layer  120  as a mask pattern to form an active pillar P. The active pillar P may be formed by etching the semiconductor substrate  100  by a predetermined depth, but the method of forming the active pillar is not limited thereto. The active pillar may be formed by forming an additional semiconductor layer (not shown) on the semiconductor substrate  100  and etching the additional semiconductor layer. Further, in an embodiment, the semiconductor substrate  100  may be a silicon substrate having a first conductivity type. 
         [0021]    Referring to  FIGS. 1B ,  2 B, and  3 B, a gate insulating layer  125  may be formed on an exposed sidewall surface of the active pillar P. The gate insulating layer  125  may include, for example, a silicon oxide material. A gate material layer  130  is formed on the semiconductor substrate  100  in which the gate insulating layer  125  is formed. The gate material layer  130  may be formed along the surface of the active pillar P. When a distance between active pillars P is sufficiently narrow, the gate material layer  130  may be formed in a buried form in a space between the active pillars P. 
         [0022]    A predetermined portion of the gate material layer  130  is etched to expose a predetermined portion of the semiconductor substrate  100 , forming a gate extending in an x-direction as shown in  FIG. 1B . Alternatively, the gate material layer  130  may be anisotropically etched to expose the predetermined portion of the semiconductor substrate  100 , forming the gate material layer  130  surrounding a circumference of the active pillar P. The etch process for exposing the semiconductor substrate  100  may be performed through an over etching process by considering the thickness of the gate material layer  130 . In the over etching process, the semiconductor substrate  100  may be additionally etched by a predetermined depth d. An exposed region  135  of the semiconductor substrate may be a node separation region for separation between cells. For example, the node separation region  135  may extend to the x-direction of  FIG. 1B  and be substantially in parallel to the remaining gate material layer  130 . 
         [0023]    Referring to  FIGS. 1C ,  2 C, and  3 C, a preliminary common source region  140  is formed by implanting Impurities into the exposed node separation region  135 . The impurities may have a second conductivity type opposite to the first conductivity type. The impurities may have substantially the same concentration as a source which will be formed later. A first interlayer insulating layer  145  is formed on the semiconductor substrate  100  in which the preliminary common source region  140  is defined. The first interlayer insulating layer  145  may be formed to a thickness sufficient to gap-fill a space between gate material layers. 
         [0024]    Referring to  FIGS. 1D ,  2 D, and  3 D, the first interlayer insulating layer  145  is recessed by a predetermined thickness to define a gate mask  145   a . An upper surface of the gate mask  145   a  may be located at a lower level than an upper surface of the active pillar P, and may be provided to control a height of the gate material layer  130 . 
         [0025]    Referring to  FIGS. 1E ,  2 E, and  3 E, the gate material layer  130  is recessed by a predetermined thickness using the gate mask  145   a  to form a gate  130   a . In an embodiment, the gate  130   a  may be referred to as a word line. The gate  130   a  may extend up to the same level as the upper surface of the gate mask  145   a , and the gate mask  145   a  may be formed of an insulating material. Therefore, gates  130   a  extending in parallel to the x-direction of  FIG. 1E  may be insulated by the gate mask  145   a . An upper sidewall of the active pillar P may be exposed through the formation of the gate  130   a.    
         [0026]    Referring to  FIGS. 1F ,  2 F, and  3 F, lightly doped drain (LDD) ions are implanted into the upper sidewall of the active pillar P which is exposed by the gate  130   a  to form a first LDD region  150 . The LDD ions may be implanted through a tilt ion Implantation process, and may have the second conductivity type. 
         [0027]    Referring to  FIGS. 1G ,  2 G, and  3 G, a liner  155  formed of, for example, a silicon nitride layer is formed on the upper sidewall of the active pillar P and on the gate  130   a  and the gate mask  145   a . A second interlayer insulating layer  160  is formed on the liner  155  and may be, for example, silicon nitride. The second interlayer insulating layer  160  may be formed to a thickness sufficient to fill a space between the active pillars P, and recessed by a predetermined thickness to expose the upper sidewall of the active pillar P where a drain is formed in a subsequent process. 
         [0028]    Referring to  FIGS. 1H ,  2 H, and  3 H, the hard mask layer  120  and the pad oxide layer  115  and portions of the gate insulating layer  125  and the liner  155 , which are exposed by the second interlayer insulating layer  160 , are removed. Therefore, an upper portion of the bare active pillar P may be exposed. 
         [0029]    Referring to  FIGS. 1I ,  2 I, and  3 I, a first high concentration impurity region  165  is formed by implanting impurities having the second conductivity type into the exposed upper portion of the active pillar P, more specifically, into the first LDD region  150  of the active pillar P. A second high concentration impurity region  167  may be formed by shallowly implanting a second high concentration impurity having the second conductivity type into a surface of the first high concentration region  165 . The second high concentration impurity region  167  may have a higher impurity concentration than the first high concentration impurity region  165 , and thus may serve to reduce contact resistance, with a silicide layer that will be formed later, and ohmic contact resistance. For example, the second high concentration impurity region  167  may substantially have the same concentration as the preliminary common source region  140 . 
         [0030]    Referring to  FIGS. 1J ,  2 J, and  3 J, a transition metal layer  170  is coated on the pillar P and the second interlayer insulating layer  160 . The transition metal layer  170  may be uniformly formed on top in a liner pattern and on an entire lateral surface of the active pillar P. For example, the transition metal layer  170  may include a titanium layer. 
         [0031]    Referring to  FIGS. 1K ,  2 K, and  3 K, an activation process is performed on the semiconductor substrate  100  on which the transition metal layer  170  is transformed to a silicide layer  175  on the top and entire lateral surface of the pillar P. As is well-known, a silicide reaction is performed between a silicon material and a transition metal layer material, and thus the silicide layer  175  may be formed only on the surface of the pillar P including a silicon material. In the activation treatment for the silicide reaction, impurities of the preliminary common source region  140  may be diffused, so a third high concentration impurity region  180   a , a fourth high concentration impurity region  180   b , and a second LDD region  180   c  are spontaneously formed. The third high concentration impurity region  180   a  is located close to the preliminary common source region  140 , and thus the third high concentration impurity region  180   a  may have a higher concentration than the fourth high concentration impurity region  180   b . The third and fourth high concentration impurity regions  180   a  and  180   b  may be formed in the entire semiconductor substrate to extend through a lower portion of the active pillar P. Thus, a drain D of a vertical transistor is defined by the first LDD region  150  and the first high concentration impurity region  165 , and a source S of the vertical transistor is defined by the third high concentration impurity region  180   a , the fourth high concentration impurity region  180   b , and the second LDD region  180   c . The non-reacted transition metal layer  170  in  FIGS. 1J ,  2 J, and  3 J may be removed. 
         [0032]    Referring to  FIGS. 1L ,  2 L, and  3 L, a first planarization insulating layer  180  is formed on the semiconductor substrate  100  in which the source S and the drain D are defined. The first planarization insulating layer  180  may be planarized to expose a surface of the silicide layer  175  on the pillar P. An etch stopper  185  is formed on the first planarization insulating layer  180 . A second planarization insulating layer  190  is formed on the etch stopper  185 . The second planarization insulating layer  190  is etched to expose the etch stopper  185  located on the pillar P, and the exposed etch stopper  185  is selectively removed to form a lower electrode region (not shown) exposing the silicide layer  175 . Subsequently, a conductive material is filled within the lower electrode region to form a lower electrode  195 . Although not shown in  FIGS. 1L ,  2 L, and  3 L, a variable resistance layer, for example, a phase-change layer may be formed on the lower electrode  195 . 
         [0033]    According to an embodiment, a silicide layer may be formed on a top and a circumference of an upper portion of a pillar to form a drain region of a vertical transistor in a cap form, reducing contact resistance. 
         [0034]    In an embodiment, the silicide layer is formed in a manner surrounding the pillar protruding outside before a first planarization insulating layer is formed. Thus, the silicide layer is easily formed on an upper surface and a sidewall surface of the pillar P. 
         [0035]    In conventional art, a pillar structure is buried in a planarized insulating layer. The silicide formation region is formed by etching the planarized insulating layer to expose an upper surface and a sidewall of the pillar. However, according to an embodiment, the additional etching process for forming a silicide formation region (an upper surface and a sidewall surface of the pillar P) is unnecessary because the silicide layer  175  is formed by reacting the second high concentration impurity region  167  and the transition metal layer  170  coated on the second high concentration impurity region  167 . 
         [0036]    The pillar protruding outwards may be formed with in a self-aligned manner, and thus an additional process for protruding the pillar is not necessary. 
         [0037]    The above embodiments are illustrative and not limitative. Various alternatives and modifications are possible that would fail within the spirit and scope of the appended claims.