Abstract:
Apparatus and methods for implementation of mathematical functions apparatus providing both speed and accuracy. Disclosed are specific circuits and methods of operation thereof that may be used for the purpose of implementing an exponential function, a squaring function, and a cubic function, using the same basic circuit. By applying a desired weighting function on a current source, an output current provides a value that corresponds exactly to the desired mathematical functions at discrete points, and closely tracks values in between the discrete points. The precision is defined by the selection of a voltage reference for the circuit. Various embodiments are disclosed, as well as embodiments implementing other exemplary functions.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims the benefit of U.S. Provisional Patent Application No. 60/625,979 filed Nov. 9, 2004. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to electronic circuits for generating mathematical functions, and more specifically to ascending or descending mathematical functions or combinations thereof, and even more specifically, but without limitation thereto, to electronic circuits for generating an output current that is a function of an input voltage, such as an exponential function, using one set of weights, a square function, using another set of weights, or a cubic function, using yet another set of weights.  
         [0004]     2. Prior Art  
         [0005]     The need for computation of functions such as exponential and trigonometric functions is well-known and documented in the art. There are a multitude of ways to generate the results of such functions for a variety of purposes, all of which are targeted toward a circuit level implementation. Each solution has certain advantages and certain deficiencies that may render a solution not suitable for a specific application. Generally the circuit level implementation can be described as belonging to one of two groups of implementations: digital, i.e., receiving a result through a numerical computation of one sort or another, and analog, i.e., having a circuit generate an output value that is proportionate to an input value in a way that implements the desired mathematical function.  
         [0006]     Among the known digital types of solutions are the table lookup methods, polynomial approximation methods, digit-by-digit methods, and rational approximation. An analog circuit is disclosed in U.S. Pat. No. 6,771,111 by Sheng et al. That circuit attempts to use a single stage differential amplifier set-up to provide exponential function circuitry. However, the methods and circuits disclosed by prior art solutions are deficient in at least chip area, speed, or accuracy.  
         [0007]     In view of the deficiencies of prior art solutions and in view of the need to provide fast and accurate mathematical functions, for example in wireless communication, it would be advantageous to provide circuits that are capable of providing mathematical functions. It would be further advantageous if such circuits were able to implement several mathematical functions without the need to use different circuit techniques or designs, i.e., be generally dependent on parameters of the circuit, not the circuit itself. It would be further beneficial if the output result was independent of process and temperature variations.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]      FIG. 1  is an exemplary circuit for implementation of a mathematical function in accordance with the disclosed invention.  
         [0009]      FIG. 2  is an exemplary graph of the output current as a function of the input voltage from a circuit designed in accordance with the disclosed invention.  
         [0010]      FIG. 3  is an exemplary circuit for implementation of an inverse mathematical function in accordance with the disclosed invention.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0011]     Reference is now made to  FIG. 1  where an exemplary and non-limiting circuit  100 , for implementing a mathematical function in accordance with the disclosed invention, is shown. Circuit  100  comprises n cells  110 - 1  through  110 - n , each cell  110  comprising two transistors  112  and  114 , the transistors being, for example, bipolar NPN transistors, and further having their respective emitters coupled to each other. Each cell  110  has two input ports. At one port, i.e., the base of transistor  112 , the input voltage V in  is applied. At the other port, i.e., the base of transistor  114 , a reference voltage is supplied. Each cell  110  receives a linearly increasing reference voltage, such that cell  110 - 1  receives a reference voltage V r , cell  110 - 2  receives a reference voltage of 2V r , cell  110 - 3  receives a reference voltage of 3V r , and so forth, until cell  110 - n  receives a reference voltage of nV r  at the base of each respective transistor  114 . The voltage (n+1)V r  preferably defines the maximum input range for a minimum error of the output value, i.e., V in  cannot exceed the value of (n+1)V r . V r  may be provided in various ways, such as by way of example, by a bandgap voltage reference. The collectors of transistors  114  are connected to the positive voltage supply while the collectors of transistors  112  are connected to the output node. The coupled emitters of transistors  112  and  114  are connected to a current source  116 , configured to be able to supply a current which is an integer multiple of a weighting factor, i.e., I r  is a constant current and w i , i=1, 2 . . . n are the weights by which the current I r  varies. By using different weighting factors w i , it is possible to cause circuit  100  to generate different mathematical functions as demonstrated in more detail below.  
         [0012]     In one embodiment of the disclosed invention, circuit  100  is used for exponential function generation. In such a case, the weights of current sources  116  are w 1 =1, for k=1, while w 2 =2; w 3 =4 . . . , w k =2 k−1 , . . . w n =2 n−1  for k&gt;1. When the input voltage V in  satisfies kV r &lt;V in &lt;(k+1) V r , then V in &gt;V r , V in &gt;2V r , . . . V in &gt;kV r , V in &lt;(k+1)V r , . . . , V in &lt;nV r . Therefore, the cells  110 - 1 ,  110 - 2 , . . . ,  110 - k  are active (directing respective currents to the output I out ) while cells  110 -(k+1), . . . ,  110 - n  are disabled (directing respective currents to the supply). Assuming that when a cell  110 - k  is active, then the collector current of transistor  112 - k  is equal to w k I r , contributing to the output current, e.g., when V in  is between 3V r  and 4V r , it means that k=3, therefore cells  110 - 1 ,  110 - 2 ,  110 - 3  are active and the output current gets the value I out =8I r . The output current I out  is therefore given by the relation:  
                 I   out     ⁡     (   k   )       =       I   r     ⁢       ∑     i   =   1     k     ⁢     w   i                 Eq   .           ⁢     (   1   )               
 
         [0013]     Using inductive reasoning, it can be proved that:  
                 ∑     i   =   1     k     ⁢     w   i       =     2   k             Eq   .           ⁢     (   2   )               
 
         [0014]     The proof of equation (2) deviates from the scope of this document.  
         [0015]     Thus, based on equation (1) and (2), we take: 
 
 I   out ( k )= I   r 10 klog2   Eq. (3) 
 
         [0016]     This may be further understood when referring to  FIG. 2  where an exemplary and non-limiting graph of the output current from circuit  100 , as a function of the input voltage to circuit  100 , is shown. Precise values of the exponential function are achieved at points  220 - 1 ,  220 - 2 ,  220 - 3 , and so forth until point  220 - n . When substituting k by V in /V r  in equation (2) then output current from circuit  100  is:  
                 I   out     ⁡     (     V   in     )       =       I   r     ⁢     10     Vin     (       Vr   /   log     ⁢           ⁢   2     )                   Eq   .           ⁢     (   4   )               
 
         [0017]     This equation is exact at integer values of V in /(kV r ), and approximate at other values. Equation (4) shows that I out  is an exponential function of the input voltage V in .  
         [0018]     Thus the exponential function is generated using circuit  100 . It should be noted that equation (4) is valid only at the discrete points V in =V r , 2V r  . . . nV r . When V in  is a value between the reference voltages, for example between 2V r  and 3V r , then the above relation is only approximately valid. Therefore between points [V r , 2V r ], [2V r , 3V r ], . . . , [(n−1)V r , nV r ] there may be an error that can be made very small and is dependent on the choice of V r . The optimum value for V r  in order to achieve a minimum error for bipolar transistors is approximately 75 mV. This value of the voltage reference has been chosen empirically. Ir has a typical value of approximately 1 μA, though I r  will depend on the number of the cells used and the maximum value of the output current. Notably the output current at any point  220  ( FIG. 2 ) of the exponential function of circuit  100  is substantially independent of process and temperature, as is shown in equation (4), since both V r  and I r  are constant. The variation of the error due to process and temperature is actually very small, especially when the optimal value for V r  is used. More specifically, the relevant error of the output current is about ±1% for an input range from 1.2V to 1.7V. An exemplary circuit  100  may be designed using ten cells  110 , with a 2.7V voltage supply, in a five metal 0.5 μm SiGe BiCMOS process. In this exemplary case, the worst case relevant error for ± 3 σ process variation and for a temperature range from −20° C. to 100° C. becomes ±2%. The circuit implementing the exponential function may be used, for example but is not limited to, a linear in dB gain control circuit of a variable gain amplifier (VGA) of a wireless transceiver integrated circuit. In some applications, but not necessarily all applications, the current sources are programmable so that the output as a function of the input may be changed, or at least initially programmed to provide the specific function desired.  
         [0019]     In another embodiment of the disclosed invention, circuit  100  is used for the implementation of a squaring function. While circuit  100  remains the same, the weights of current sources  116  are set to w 1 =2, w 2 =4, . . . , w i =2i, . . . , w n =2n. When input voltage V in  satisfies V in =kV r  then V in &gt;V r , V in &gt;2V r , . . . , V in =kV r , V in &lt;(k+1)V r , . . . , V in &lt;nV r . Therefore, the cells  110 - 1 ,  110 - 2 , . . . ,  110 -(k−1) are active while cells  110 -(k+1), . . . ,  110 - n  are disabled. In the cell  110 - k  the collector current of transistor  112 - k  is equal to (w k /2) I r , contributing to the output current, e.g., when V in , is V in =3V r  it means that k=3, therefore cells  110 - 1 ,  110 - 2  are active (directing current to the output I out ) while the cell  110 - 3  contributes with a current (w 3 /2) I r  to the output current. In that case the output current gets the value I out =9I r . The output current is therefore given by the relation:  
                 I   out     ⁡     (   k   )       =       I   r     ⁡     [         ∑     i   =   1       k   -   1       ⁢     w   i       +       w   k     2       ]               Eq   .           ⁢     (   5   )               
 
 where it is assumed that in the case of k=1,  
           ∑     i   =   1       k   -   1       ⁢     w   i       =   0.       
 
         [0020]     Equation (5) can be transformed to equation (6) as explained in more detail below: 
 
 I   out ( k )= I   r   k   2   Eq. (6) 
 
 where k is defined by the maximum reference voltage kV r  that the maximum input voltage V in  may equal. 
 
         [0021]     The transformation of equation (5) to equation (6) is based on the well-known formula:  
                 ∑     i   =   1     k     ⁢   i     =       k   ⁡     (     k   +   1     )       2             Eq   .           ⁢     (   7   )               
 
         [0022]     Solving equation (7) for k 2  it is concluded that:  
               k   2     =         ∑     i   =   1       k   -   1       ⁢     2   ⁢           ⁢   i       +   k             Eq   .           ⁢     (   8   )               
 
 where it is assumed that in the case of  
         k   =   1     ,         ∑     i   =   1       k   -   1       ⁢     2   ⁢           ⁢   i       =   0.         
 
 As is mentioned above, the weights of current sources  116  are set to w i =2i. Thus equation (8) yields:  
               k   2     =     [         ∑     i   =   1       k   -   1       ⁢     w   i       +       w   k     2       ]             Eq   .           ⁢     (   9   )               
 
         [0023]     Substituting k by V in /V r  in equation (6), the output current of circuit  100  is:  
                 I   out     ⁡     (     V   in     )       =         I   r       V   r   2       ⁢     V   in   2               Eq   .           ⁢     (   10   )               
 
 resulting in a squaring function of V in , since both I r  and V r  are constants. The optimum value for V r , in order to achieve the minimum error, for bipolar transistors is 75 mV. This value of the voltage reference has been chosen empirically. I r  has a typical value of approximately 10 μA, while the specific value of I r  used will depend on the number of cells used and the maximum value of the output current. Notably, the output current at any point  220 , of squaring function of circuit  200 , is independent of process and temperature, as is shown in equation (10), since both V r  and I r  are constant. The actual variation of the error due to process and temperature is very small, especially when the optimal value for V r  is used. More specifically, the relevant error of the output current is about ±0.4% for an input range from 1.1V to 1.7V. An exemplary circuit  100  may be designed with ten cells  110  with 2.7V voltage supply, in a five metal 0.5 μm SiGe BiCMOS process. The worst-case relevant error for a +3σ process variation and for a temperature range from −20° C. to 100° C. becomes ±0.6%. The circuit implementing the squaring function may be used, for example, as a power detector of a wireless transceiver integrated circuit. 
 
         [0024]     In another embodiment of the disclosed invention, circuit  100  is used for the implementation of a cubic function. While circuit  100  remains the same, the weights of current sources  116  are set to w 1 =2, w 2 =12, w 3 =26, . . . , w n =w n-1 +w n-2 −w n-3 +12. The output current is therefore given by the relation:  
                 I   out     ⁡     (   k   )       =       I   r     ⁡     [         ∑     i   =   1       k   -   1       ⁢     w   i       +       w   k     2       ]               Eq   .           ⁢     (   11   )               
 
 where k is defined by the maximum reference voltage kV r  that the maximum input voltage V in  may equal. The above equation is transformed to: 
 
 I   out ( k )= I   r   k   3   Eq. (12) 
 
         [0025]     A person skilled-in-the-art would be able to perform the transformation of equation (11) to equation (12) and hence such is not provided herein. Substituting k=V in /V r  in equation (12) the output current of circuit  100  is:  
                 I   out     ⁡     (     V   in     )       =         I   r       V   r   3       ⁢     V   in   3               Eq   .           ⁢     (   13   )               
 
 resulting in a cubic function of V in , since both I r  and V r  are constants. The optimum value for V r , in order to achieve the minimum error, is 75 mV. I r  has a typical value of 1 μA, while the specific value of I r  used would depend on the desirable number of cells and the maximum value of the output current. Notably, the output current at any point  220 , of cubic function of circuit  200 , is independent of process and temperature as is shown in equation (13) since both V r  and I r  are constant. The variation of the error due to process and temperature is very small, especially when the optimal value for V r  is used. More specifically, the relevant error of the output current is about ±0.45% for an input range from 1.25V to 1.75V. An exemplary circuit  100  may be designed with ten cells  110 , in a five metal 0.5 μm SiGe BiCMOS process for 2.7V voltage supply. The worst-case relevant error versus process and for a temperature range from −20° C. to 100° C. is ±2.5%. 
 
         [0026]     The implementation of the circuit as it was described above generates ascending functions. The circuit can be easily transformed in order to implement descending functions. Reference is made to  FIG. 3  of circuit  300  where the collectors of transistors  112  are connected to the voltage supply and the collectors of transistors  114  are connected to the output node, then the circuit generates the descending functions. In this case, the output current is given by:  
                 I   out_descending     ⁡     (   k   )       =         I   r     ⁢       ∑     i   =   1     n     ⁢     w   i         -       I   out     ⁡     (   k   )                 Eq   .           ⁢     (   14   )               
 
 where I out  (k) is the current given by the equation (4) when the circuit generates exponential function, or by equation when the circuit generates squaring function, or finally by equation (13) when the circuit generates cubic function. In each case w i  are the weights that corresponds to the generating function. 
 
         [0027]     While circuit inputs for an exponential function, a square function, and a cubic function, have been specifically disclosed herein, the circuits of the present invention may be used to generate other functions, easily mathematically expressible or not. By way of but one example, because of the speed of the circuits of the present invention, such circuits might be used to predistort a multi-channel RF input signal to a power amplifier, or to control the gain of the power amplifier with input signal amplitude, to linearize the output of the amplifier to prevent crosstalk between channels. Here, using bipolar transistors, one may still use V r =75 mv, though pick (program) values of w i  that generate the desired function such as by using Eq. (11), normally an increasing function of input signal amplitude, to offset the normal decrease in gain of an amplifier with input signal amplitude. One could even mix increasing and decreasing functions to obtain a function having a maximum or a minimum between the ends of the function by using a circuit, part of which is in accordance with  FIG. 1  and part of which is in accordance with  FIG. 3 , if such a function were desired.  
         [0028]     Also other transistor types and implementations are possible, including, but not limited to, metal-oxide semiconductor (MOS) transistors, without departing from the disclosures made herein. In the case of MOS transistors, one may use a different V r , typically chosen to be sufficiently large so that when the input voltage V in  equals a multiple of V r , one half the respective current source is directed to the output, substantially all the prior current sources are directed to the output ( FIG. 1 ) or a power supply terminal ( FIG. 3 ) and substantially all the subsequent current sources are directed to the power supply terminal ( FIG. 1 ) or to the output ( FIG. 3 ) to minimize the number of cells required, but sufficiently small to provide a smooth transition from cell to cell as the input voltage changes. In one embodiment of the disclosed invention, circuit  100  is part of an integrated circuit (IC), preferably manufactured as a monolithic semiconductor device.  
         [0029]     Thus while certain preferred embodiments of the present invention have been disclosed and described herein for purposes of illustration and not for purposes of limitation, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.