Abstract:
A single amplifier is arranged in an immittance network for simulating a pure frequency dependent negative resistor (FDNR).

Description:
BACKGROUND OF THE INVENTION 
     The invention relates to simulation networks and more particularly to a network for simulating a frequency dependent negative resistor (FDNR). 
     In spite of increased success of active resistor-capacitor filters, voice-frequency passive filters remain useful because of two properties. First of all, a doubly terminated lossless ladder network and some other lossless topologies have low sensitivity to component variations. Secondly, passive filters operate bilaterally. 
     These same two properties also can be useful in active resistor-capacitor filters when passive filters having inductors are transformed into an active equivalent form. Such a transformation is used for synthesizing a passive filter by means of an active filter. As a part of the transformation, inductors are replaced by resistors, resistors are replaced by capacitors and capacitors are replaced by a simulation network which is a frequency dependent negative resistor. The FDNR can be realized as an active integrated circuit. 
     There are two important types of network response. One response is the current conducted through network terminals to which a potential is applied. A second response is the potential created across a pair of terminals when a current is conducted through the network connected between the terminals. These responses are characterized, respectively, by the impedance and the admittance of the respective networks. The name immittance is associated with those responses whenever the impedance and the admittance are not to be singled out individually. The word immittance can be considered to be a contraction for the expression &#34;impedance or admittance&#34; and is understood to mean a form of network response. 
     In the aforementioned transformation, each impedance of the filter is divided by a complex frequency variable s = jω so that each inductor becomes a resistor, each resistor becomes a capacitor, and each capacitor becomes an element with an impedance proportional to 1/s 2  in the transformed equivalent network. This latter element is the one called the frequency dependent negative resistor (FDNR). 
     Although FDNR circuits have been developed previously, such prior art FDNR circuits are relatively complex. In addition to the FDNR, the prior art circuits also include one or more additional equivalent circuit elements which cannot be separated from the FDNR and therefore make it either difficult or impossible to simulate some transformed passive filter arrangements. 
     SUMMARY OF THE INVENTION 
     Therefore it is an object of the invention to provide a single amplifier immittance circuit. 
     It is also an object of this invention to provide a single amplifier FDNR arrangement. 
     It is a further object to simulate a pure FDNR with a single amplifier circuit. 
     These and other objects of the invention are realized by a single amplifier circuit including an input terminal and an amplifier having first and second inputs and an output, a conductance coupling the output to the first input, a capacitance coupling the input terminal to the first input, a conductance coupling the input terminal to the second input, conductances coupling the first and second inputs to ground, a capacitance directly coupling the output to the input terminal, and a conductance coupling the output to the input terminal, wherein an admittance between the input terminal and ground equals Ds 2 , where D is a real number and s is the complex frequency variable. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     A better understanding of the invention may be derived by reading the following detailed description of several embodiments thereof with reference to the attached drawings wherein 
     FIG. 1 is a schematic diagram of an illustrative embodiment of the invention; 
     FIG. 2 is a symbolic representation of an FDNR element; 
     FIG. 3 is an alternative embodiment of the invention; 
     FIG. 4 is another alternative embodiment of the invention; 
     FIG. 5 is a symbolic representation of the embodiment of FIG. 4; 
     FIG. 6 is another alternative embodiment of the invention; and 
     FIG. 7 is a symbolic representation of the embodiment of FIG. 6. 
     DETAILED DESCRIPTION 
     Referring now to FIG. 1, there is shown a single amplifier FDNR circuit arrangement including an operational amplifier 50 having a large gain, an output terminal 51 and first and second input terminals 53 and 54. In all of the figures, components which are similar to one another have been given the same designation. The two input terminals 53 and 54 are designated respectively with negative and positive polarity signs. The negative polarity sign indicates that the input 53 is an inverting input. The positive polarity sign indicates that the input 54 is a non-inverting input. Although the polarity signs are used to identify the input terminals, the gain actually can have either a positive or a negative sign. The output 51 of the amplifier 50 is coupled through a conductance G 2  to the negative input terminal 53 and by way of a conductance G B  to the positive input terminal 54. 
     An input terminal 60 of the FDNR is coupled through a series branch circuit including a conductance G 4  and a capacitor C 1  to the negative input terminal 53 of the amplifier 50. The input terminal 60 of the FDNR also is coupled through a conductance G 6  to the negative input 53 of the amplifier and by way of a conductance G C  to the positive input 54 of the amplifier. The negative and positive inputs 53 and 54 of the amplifier, respectively, are coupled through conductances G 7  and G D  to a ground reference terminal. A circuit node 62 between the conductance G 4  and the capacitor C 1  is coupled to the ground reference terminal through a conductance G 5 . A capacitor C 2  directly couples the output 51 of the amplifier 50 to the circuit node 62, and a conductance G Y  directly couples the output to the input terminal 60 of the FDNR arrangement. The capacitor C 2  is interposed in the circuit such that a first plate is connected directly to the output 51 and a second plate is connected directly to the circuit node 62. A first terminal of the conductance G Y  is connected directly to the output 51, and a second terminal of the conductance G Y  is connected directly to the input terminal 60. Another terminal 65 of the FDNR arrangement is connected directly to a reference potential or ground. 
     It is noted that in some respects the circuit of FIG. 1 is similar to an active RC filter circuit disclosed in U.S. Pat. No. 3,919,658, issued to J. J. Friend, except that in the circuit of FIG. 1 there is no arrangement for connecting a separate load device with output terminals and except that the conductance G Y  is coupled directly between the output 51 of the amplifier 50 and the input terminal 60 of the FDNR. The input admittance Y IN  of the embodiment of FIG. 1 is represented by the expression ##EQU1## where 
     
         ν.sub.2 = C.sub.1 C.sub.2 G.sub.D (G.sub.4 +G.sub.C +G.sub.6 +G.sub.Y) (2) 
    
     
         ν.sub.1 = [g.sub.4 +g.sub.c +g.sub.6 +g.sub.y ][(c.sub.1 +c.sub.2)(g.sub.2 g.sub.d -g.sub.7 g.sub.b) -c.sub.1 c.sub.5 g.sub.b ] + c.sub.2 (g.sub.4 +g.sub.y)(g.sub.6 g.sub.d -g.sub.7 g.sub.c) + c.sub.1 g.sub.y [g.sub.d (g.sub.4 +g.sub.6)-g.sub.c (g.sub.5 +g.sub.7)](3) 
    
     
         ν.sub.0 = g.sub.1 (g.sub.6 +g.sub.c +g.sub.y)(g.sub.2 g.sub.d -g.sub.7 g.sub.b) + g.sub.4 g.sub.5 (g.sub.2 g.sub.a -g.sub.3 g.sub.b) + g.sub.1 g.sub.y (g.sub.6 g.sub.d -g.sub.7 g.sub.c)                (4) 
    
     
         d.sub.2 = C.sub.1 C.sub.2 G.sub.A                          (5) 
    
     
         d.sub.1 = (C.sub.1 +C.sub.2)(G.sub.2 G.sub.A -G.sub.3 G.sub.B) - G.sub.1 G.sub.B C.sub.1                                           (6) 
    
     
         d.sub.0 = G.sub.1 (G.sub.2 G.sub.A -G.sub.3 G.sub.B)       (7) 
    
     
         g.sub.i ≠ 1/R.sub.i for i = 1,2,3,4,5,6,7,A,B,C,D,Y  (8) 
    
     
         g.sub.a ≠ g.sub.c + g.sub.d                          (9) 
    
     
         g.sub.1 ≠ g.sub.4 + g.sub.5                          (10) 
    
     
         g.sub.3 ≠ g.sub.6 + g.sub.7.                         (11) 
    
     the denominator of the input admittance function is the same as that of the transfer function of the circuit arrangement shown in the aforementioned Friend patent. It is noted that the input admittance of the Friend circuit arrangement has not been investigated in the past, as a synthesis tool, because designers working with the Friend circuit have only been interested in the ratio of the output voltage to the input voltage. When the single amplifier biquad arrangement disclosed by Friend is used for an immittance synthesis, there is no concern for the output voltage. Instead there is a concern for the input current. 
     For determining a pure FDNR arrangement with the set of coefficients (2)-(7) mentioned above, one should make the input admittance equal to Ds 2 , where D is a real number and s is the complex frequency variable. One solution for the set of equations is determined by eliminating the conductance G 4  through making it infinite. By making the conductance G 4  infinite, the second plate of the capacitor C 2  is connected directly to the input terminal 60. Thereby the capacitance C 2  directly couples the output of the amplifier to the input terminal. When one takes the limit in equations (1) through (11) with G 4  going to infinity, one obtains 
     
         ν.sub.2 =C.sub.1 C.sub.2 G.sub.D                        (12) 
    
     
         ν.sub.1 = (c.sub.1 +c.sub.2)(g.sub.2 g.sub.d -g.sub.7 g.sub.b) - (c.sub.1 g.sub.5 g.sub.b) + (c.sub.2)(g.sub.6 g.sub.d -g.sub.7 g.sub.c) + (c.sub.1 g.sub.d g.sub.y)                                 (13) 
    
     
         ν.sub.0 = (g.sub.6 +g.sub.c +g.sub.y)(g.sub.2 g.sub.d -g.sub.7 g.sub.b) + (g.sub.5)(g.sub.2 g.sub.a -g.sub.3 g.sub.b) + (g.sub.y)(g.sub.6 g.sub.d -g.sub.7 g.sub.c)                                         (14) 
    
     
         d.sub.2 = 0                                                (15) 
    
     
         d.sub.1 = - G.sub.B C.sub.1                                (16) 
    
     
         d.sub.0 = (G.sub.2 G.sub.A) - (G.sub.3 G.sub.B)            (17) 
    
     to realize an FDNR immittance, the following assignments can be made in equations (12) through (17): G B  = 0, G 5  = 0, and G 6  = 0. Then 
     
         G.sub.C = (G.sub.Y)[(C.sub.1 /C.sub.2)+(G.sub.Y D/C.sub.2.sup.2)]/[1-(G.sub.Y.sup.2 D/C.sub.2.sup.2 G.sub.D)], (18) 
    
     
         g.sub.2 = (c.sub.1 c.sub.2 g.sub.d)/(d)(g.sub.c +g.sub.d), and (19) 
    
     
         G.sub.7 = (G.sub.D) {1+[1+(C.sub.2 /C.sub.1)][G.sub.2 /G.sub.Y ]}/[1+(G.sub.Y /G.sub.2)].                                (20) 
    
     these equations give an input admittance 
     
         Y.sub.IN = ν.sub.2 s.sup.2 /d.sub.0 ≠ Ds.sup.2    (21) 
    
     so that 
     
         D = (C.sub.1 C.sub.2 G.sub.D)/(G.sub.C +G.sub.D)(G.sub.2). (22) 
    
     a positive value for the conductance G C  is determined by choosing the free parameters, such as the conductance G Y  and the capacitance C 2 , to satisfy 
     
         (G.sub.Y.sup.2 D)/(C.sub.2.sup.2 G.sub.D) &lt; 1.             (23) 
    
     fig. 2 shows a symbol 70 representing the circuit of FIG. 1 when it satisfies the equation (21). By so satisfying the conditions of equation (21), the circuit of FIG. 1 operates as a pure FDNR without any other equivalent circuit elements being connected thereto. Since the second terminal of the input port is grounded, FIG. 2 also shows the pure FDNR grounded. 
     FIG. 3 is an alternative arrangement for the circuit of FIG. 1 wherein the conductance G 4  is infinite and the conductances G 5 , G 6  and G B  are zero to satisfy the conditions of equation (21). In FIG. 3, the capacitor C 2  is shown directly coupling the output of the amplifier 50 to the input terminal 60. The symbol 70 of FIG. 2 also represents the circuit of FIG. 3. 
     It is important to note that because the foregoing describes a pure FDNR arrangement, no component in the arrangement can be identified as a load device. The resulting FDNR is simply in a grounded configuration. 
     Referring now to FIG. 4, a circuit arrangement, which differs from that of FIG. 1 by the absence of conductances G 5  and G 6  because they are chosen to equal zero, exhibits an input inpedance function given by the following expression: 
     
         Z.sub.IN = e.sub.i /i.sub.i = R + 1/Ds.sup.2,              (24) 
    
     where e i  equals input voltage and i i  equals input current. The input impedance Z IN  represents a series resonant immittance including an FDNR and a load resistance connected to ground. No single component in FIG. 4, however, can be identified specifically as the load resistance R. 
     A solution for the equations (12) through (17) is determined by setting G 5  and G 6  = 0, by choosing a constant K 4  ≧ 1, and by choosing 
     
         G.sub.Y &gt; 1/(RK.sub.4)[1+(C.sub.1 /C.sub.2)].              (25) 
    
     then 
     
         G.sub.4 = (K.sub.4 G.sub.Y)[1+(C.sub.1 /C.sub.2)]          (26) 
    
     
         g.sub.c = g.sub.y {k.sub.4 c.sub.1 +c.sub.2 +(drg.sub.4.sup.2)/(c.sub.1 +c.sub.2)}/(c.sub.2)(k.sub.4 -1)                          (27) 
    
     
         g.sub.d = g.sub.c /{(r)(g.sub.4 +g.sub.c +g.sub.y)-1}      (28) 
    
     
         g.sub.b = c.sub.2 (g.sub.c +g.sub.d)(c.sub.1 +c.sub.2)/(rdg.sub.4.sup.2) (29) 
    
     
         g.sub.7 = [(g.sub.c /c.sub.1){(c.sub.1 +c.sub.2)/(g.sub.4 g.sub.d) + (c.sub.2)/(g.sub.y g.sub.d +g.sub.b /r)}].sup.-1          (30) 
    
     
         g.sub.2 = c.sub.2 {c.sub.1 g.sub.4 +(g.sub.7)(c.sub.1 +c.sub.2)}/(g.sub.4.sup.2 dr).                            (31) 
    
     referring now to FIG. 5 there is shown a symbolic representation of the circuit of FIG. 4, showing an FDNR 70 connected in a series circuit arrangement with a load resistance R further connected to ground. 
     Referring now to FIG. 6, a further circuit arrangement, which differs from that of FIG. 1 by the absence of conductances G 5 , G 6 , and G Y  because they are chosen to equal zero and by the substitution of a capacitance C 7  for the conductance G 7 , exhibits an input admittance function given by the following expression: 
     
         Y.sub.IN = i.sub.i /e.sub.i = G + Ds.sup.2,                (32) 
    
     wherein i i  equals input current and e i  equal input voltage. 
     This input admittance Y IN  represents a parallel resonant immittance including an FDNR and a conductance connected to ground. No specific component in FIG. 6 is identifiable as the conductance G. 
     A solution for the equations (12) through (17) is determined by setting conductances G 5 , G 6 , and G Y  = 0 and by replacing the conductance G 7  with a capacitance C 7  which couples the negative input of the amplifier 50 to the ground reference terminal. This arrangement provides the following set of coefficients for equation (1): 
     
         ν.sub.2 = (C.sub.1 C.sub.2 G.sub.D)(G.sub.4 +G.sub.C) - (G.sub.B C.sub.7)(C.sub.1 +C.sub.2)(G.sub.4 +G.sub.C) - G.sub.4 G.sub.C C.sub.7 C.sub.2                                                   (33) 
    
     
         ν.sub.1 = (g.sub.2 g.sub.d)(g.sub.4 +g.sub.c)(c.sub.1 +c.sub.2) - g.sub.c g.sub.4 g.sub.b c.sub.7                           (34) 
    
     
         ν.sub.0 = g.sub.c g.sub.d g.sub.2 g.sub.4               (35) 
    
     
         d.sub.2 = C.sub.1 C.sub.2 G.sub.A - (C.sub.7 G.sub.B)(C.sub.1 +C.sub.2) (36) 
    
     
         d.sub.1 = (C.sub.1 +C.sub.2)(G.sub.2 G.sub.A -G.sub.4 G.sub.B) (37) 
    
     
         d.sub.0 = G.sub.2 G.sub.4 G.sub.A                          (38) 
    
     where G A  is defined as in equation (9). 
     To realize the input admittance 
     
         Y.sub.IN = G + Ds.sup.2                                    (39) 
    
     one solution is to choose another constant K &gt; 1 
     
         g.sub.a = k[1+(c.sub.1 /c.sub.7)]                          (40) 
    
     
         α ≠ (c.sub.7)(c.sub.1 +c.sub.2).sup.2 /(c.sub.1 c.sub.2)(c.sub.1 +c.sub.7)                                (41) 
    
     
         g.sub.2 = (g.sub.c)(k-1)/α                           (42) 
    
     
         g.sub.4 = (g.sub.c)(k-1)                                   (43) 
    
     
         g.sub.b = (c.sub.1 c.sub.2 g.sub.a)/(c.sub.7)(c.sub.1 +c.sub.2) (44) 
    
     it is noted that the circuit of FIG. 6 uses a three capacitor arrangement rather than the simpler two capacitor arrangements of FIGS. 1, 3 and 4. 
     The circuit of FIG. 6 is shown symbolically in FIG. 7 as a parallel arrangement of a conductance G and FDNR 70 connected to ground. 
     The foregoing describes several illustrative embodiments of applicant&#39;s invention. These embodiments together with other embodiments obvious to those skilled in the art are considered to be included within the scope of the invention.