Abstract:
A differential signal generator circuit includes: a first amplifier for comparing an input signal with a threshold voltage and outputting differential signals; and a second amplifier for adjusting the threshold voltage in response to the differential signals. The second amplifier includes: a first transistor and a second transistor forming a differential pair, the gate of each transistor receiving a respective one of the differential signals; a third transistor and a fourth transistor forming a current mirror, the third transistor being connected between the drain of the first transistor and a reference potential point, the fourth transistor being connected between the drain of the second transistor and the reference potential point; a current source connected to the sources of the first and second transistors; and an adjusting section for adjusting drain current of the first transistor in response to an externally applied current or voltage. The threshold voltage is adjusted in response to drain voltage of the second transistor.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to differential signal generator circuits in which a first amplifier compares the input signal with a threshold voltage and outputs differential signals and a second amplifier adjusts the threshold voltage in response to the differential signals. More particularly, the invention relates to differential signal generator circuits that allow for easy adjustment of the cross-point of the differential signals. 
     2. Background Art 
     In a typical optical signal receiver, etc., the optical signal is converted into an electrical signal by a photodiode preamplifier and then into differential signals by a differential signal generator circuit which are then discriminated by a discriminator circuit. The optical signal is a two-state signal that has a high intensity state (called the “mark” or “mark state”) and a low intensity state (called the “space” or “space state”), each representing a different value. It should be noted that generally the optical signal includes greater noise when in the mark state than when in the space state. Therefore, it might happen that noise in the optical signal in the mark state prevents the discriminator circuit from properly discriminating the differential signals. To avoid this, the cross-point of the differential signals input to the discriminator circuit may be adjusted such that the discrimination level is slightly lower than the average value of the input signal. In many cases the appropriate amount of such adjustment of the cross-point is 10 mV or less, although this may vary depending on the performance of the amplifier. 
     One well known differential signal generator circuit includes a first amplifier for comparing the input signal with a threshold voltage and outputting differential signals and a second amplifier for adjusting the threshold voltage in response to the differential signals (see, e.g., JP-A-7-250105). 
       FIG. 7  is a block diagram showing a conventional differential signal generator circuit. Referring to  FIG. 7 , a first amplifier  11  compares the input signal V IN  with a threshold voltage V th  and outputs differential signals V +  and V − . A second amplifier  12  made up of a differential amplifier receives the differential signals V +  and V −  and outputs an output voltage V out . One end of a resistance  13  is connected to the output of the second amplifier  12  to convert the output voltage V out  to the threshold voltage V th . That is, in response to the differential signals V +  and V − , the second amplifier  12  automatically adjusts the threshold voltage V th  to be equal to the average value (or voltage) of the input signal V IN . The other end of the resistance  13  is grounded through a capacitance  14 . The discriminator circuit ( 15 ) is a clock and data recovery (or CDR) circuit, etc., and determines, based on the average values of the differential signals V +  and V −  output from the first amplifier  11 , whether the input signal V IN  is at a logical high level or a logical low level. 
     This conventional differential signal generator circuit is designed such that if the optical signal includes significant noise when in its mark state, a voltage may be externally applied through an adjustment terminal ADJUST and a resistance  17  to adjust the threshold voltage V th  to be slightly lower than the average value (or voltage) of the input signal V IN . 
     SUMMARY OF THE INVENTION 
     Thus, conventionally, the cross-point of the differential signals V +  and V −  is adjusted by externally adjusting the threshold voltage V th  or the differential signals V +  and V −  directly. Therefore, although the internal circuit has a simple configuration, the external control circuit must be adapted to be able to finely adjust the cross-point of the differential signals, for example, by approximately a few millivolts. That is, it has been difficult to precisely adjust the cross-point of the differential signals. Furthermore, this configuration prevents the use of a small common DA converter, etc., and hence is not practical for most applications. 
     The present invention has been devised to solve the above problems. It is, therefore, an object of the present invention to provide a differential signal generator circuit that allows for easy adjustment of the cross-point of the differential signals. 
     According to one aspect of the present invention, a differential signal generator circuit includes: a first amplifier for comparing an input signal with a threshold voltage and outputting differential signals; and a second amplifier for adjusting the threshold voltage in response to the differential signals; wherein the second amplifier includes: a first transistor and a second transistor forming a differential pair, the gate of each transistor receiving a respective one of the differential signals; a third transistor and a fourth transistor forming a current mirror, the third transistor being connected between the drain of the first transistor and a reference potential point, the fourth transistor being connected between the drain of the second transistor and the reference potential point; a current source connected to the sources of the first and second transistors; and an adjusting section for adjusting the drain current of the first transistor in response to an externally applied current or voltage. The threshold voltage is adjusted in response to the drain voltage of the second transistor. 
     Thus, the present invention provides a differential signal generator circuit that allows for easy adjustment of the cross-point of the differential signals. 
     Other and further objects, features and advantages of the invention will appear more fully from the following description. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram showing a differential signal generator circuit according to a first embodiment of the present invention. 
         FIG. 2  is a circuit diagram of the second amplifier of the present embodiment. 
         FIG. 3  is a circuit diagram of a second amplifier according to a second embodiment of the present invention. 
         FIG. 4  is a circuit diagram of a second amplifier according to a third embodiment of the present invention. 
         FIG. 5  is a block diagram showing a differential signal generator circuit of the present embodiment. 
         FIG. 6  is a circuit diagram of the second amplifier  12  of the present embodiment. 
         FIG. 7  is a block diagram showing a conventional differential signal generator circuit. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     First Embodiment 
       FIG. 1  is a block diagram showing a differential signal generator circuit according to a first embodiment of the present invention. Referring to  FIG. 1 , a first amplifier  11  compares the input signal V IN  with a threshold voltage V th  and outputs differential signals V +  and V − . A second amplifier  12  receives the differential signals V +  and V −  and outputs an output voltage V out . One end of a resistance  13  is connected to the output of the second amplifier  12  to convert the output voltage V out  to the threshold voltage V th . That is, the second amplifier  12  adjusts the threshold voltage V th  in response to the differential signals V +  and V − . The other end of the resistance  13  is grounded through a capacitance  14 . The discriminator circuit ( 15 ) is a clock and data recovery (or CDR) circuit, etc., and determines, based on the average values of the differential signals V +  and V −  output from the first amplifier  11 , whether the input signal V IN  is at a logical high level or a logical low level. 
       FIG. 2  is a circuit diagram of the second amplifier of the present embodiment. As shown, the second amplifier is a differential input, single-ended output amplifier. Referring to  FIG. 2 , NMOS transistors M 1  and M 2  (referred to as a “first transistor” and a “second transistor,” respectively, in the appended claims) form a differential pair. The differential signals V +  and V −  are applied to the gates of the NMOS transistors M 1  and M 2 , respectively. 
     Referring still to  FIG. 2 , PMOS transistors M 3  and M 4  (referred to as a “third transistor” and a “fourth transistor,” respectively, in the appended claims) form a current mirror. The PMOS transistor M 3  is connected between the drain of the NMOS transistor M 1  and a voltage source (or reference potential point), and the PMOS transistor M 4  is connected between the drain of the NMOS transistor M 2  and the voltage source. The sources of the NMOS transistors M 1  and M 2  are connected together at a node, and an NMOS transistor M 5  is connected between this node and ground potential. A predetermined voltage V bias  is applied to the gate of the NMOS transistor M 5  so that the NMOS transistor M 5  functions as a current source. The drain voltage of the NMOS transistor M 2  is output as the output voltage V out . That is, the second amplifier  12  adjusts the threshold voltage V th  by applying the drain voltage of its NMOS transistor M 2 . 
     Further, the gate and drain of an NMOS transistor M 6  are connected to an adjustment terminal ADJUST, and its source is grounded. The drain of an NMOS transistor M 7  is connected to the drain of the NMOS transistor M 1 , and the source of the NMOS transistor M 7  is grounded. The NMOS transistors M 6  and M 7  constitute an adjusting section  16  which adjusts the drain current of the NMOS transistor M 1  in response to the current externally applied to the adjustment terminal ADJUST. 
     When no current is externally applied to the adjustment terminal ADJUST, the adjusting section  16  does not make any adjustment or changes to the drain current of the NMOS transistor M 1 . Therefore, the current flowing through the NMOS transistor M 1  and the PMOS transistor M 3  is equal to that flowing through the NMOS transistor M 2  and the PMOS transistor M 4 . As a result, the output voltage V out  is set such that the average values of the differential signals V +  and V −  are equal. 
     On the other hand, when a current is externally applied to the adjustment terminal ADJUST, a portion of the current flowing through the NMOS transistor M 3  flows through the NMOS transistor M 7  instead of through the NMOS transistor M 1 . That is, the adjustment section  16  draws a portion of the current that flows through the NMOS transistor M 3 , allowing only the remaining portion of the current to flow in the NMOS transistor M 1  as its drain current. This means that a disparity occurs between the currents flowing through the NMOS transistors M 1  and M 2 , causing a change in the output voltage V out . This results in a difference between (the average values of) the differential signals V +  and V − , that is, results in displacement of the cross-point of the differential signals V +  and V − . 
     As described above, the adjusting section  16  allows for easy adjustment of the cross-point of the differential signals V +  and V − . Furthermore, since the NMOS transistors M 6  and M 7  in the adjusting section  16  form a current mirror, the adjusting section  16  can be set such that applying a large current to the adjustment terminal ADJUST results in only a small change in the drain current of the NMOS transistor M 1 . This means that, for example, the current or voltage externally applied to the adjusting section  16  is changed by as much as a few milliamperes or a few hundreds of millivolts when finely adjusting the output voltage V out  of the second amplifier  12 , e.g., by a few millivolts. Therefore, the cross-point of the differential signals V +  and V −  can be finely adjusted externally using a common chipset. 
     It should be noted that the adjusting section  16  may be adapted to adjust the drain current of the NMOS transistor M 1  in response to the voltage, not current, externally applied to the adjustment terminal ADJUST, with the same effect. That is, the present embodiment can be applied to the “voltage-forcing current-monitoring” mode, as well as the “current-forcing voltage-monitoring” mode. 
     Second Embodiment 
       FIG. 3  is a circuit diagram of a second amplifier according to a second embodiment of the present invention. This second amplifier differs from that of the first embodiment in that the adjusting section  16  has a different configuration. 
     Referring to  FIG. 3 , the gate and drain of a PMOS transistor M 6  are connected to an adjustment terminal ADJUST, and its source is connected to a voltage source. The drain of a PMOS transistor M 7  is connected to the drain of the NMOS transistor M 1 , and the source of the PMOS transistor M 7  is connected to the voltage source. 
     When a current or a voltage is externally applied to the adjustment terminal ADJUST, a current flows from the PMOS transistor  7  into the NMOS transistor M 1 . Thus, the adjusting section  16  adjusts the drain current of the NMOS transistor M 1  in response to the current or voltage externally applied to the adjustment terminal ADJUST. This allows for easy adjustment of the cross-point of the differential signals, as in the first embodiment. 
     Third Embodiment 
       FIG. 4  is a circuit diagram of a second amplifier according to a third embodiment of the present invention. As shown, this second amplifier is a differential input, single-ended output amplifier. Referring to  FIG. 4 , PMOS transistors M 1  and M 2  (referred to as a “first transistor” and a “second transistor,” respectively, in the appended claims) form a differential pair. Differential signals V +  and V −  are applied to the gates of the PMOS transistors M 1  and M 2 , respectively. 
     Referring still to  FIG. 4 , NMOS transistors M 3  and M 4  (referred to as a “third transistor” and a “fourth transistor,” respectively, in the appended claims) form a current mirror. The NMOS transistor M 3  is connected between the drain of the PMOS transistor M 1  and ground potential (or reference potential point), and the NMOS transistor M 4  is connected between the drain of the PMOS transistor M 2  and ground potential. The sources of the PMOS transistors M 1  and M 2  are connected together at a node, and a PMOS transistor M 5  is connected between this node and a voltage source. A predetermined voltage V bias  is applied to the gate of the PMOS transistor M 5  so that the PMOS transistor MS functions as a current source. The drain voltage of the PMOS transistor M 2  is output as the output voltage V out . That is, the second amplifier  12  adjusts the threshold voltage V th  by applying the drain voltage of its PMOS transistor M 2 . 
     Further, the gate and drain of an NMOS transistor M 6  are connected to an adjustment terminal ADJUST, and its source is grounded. The drain of an NMOS transistor M 7  is connected to the drain of the PMOS transistor M 1 , and the source of the NMOS transistor M 7  is grounded. The NMOS transistors M 6  and M 7  constitute an adjusting section  16  which adjusts the drain current of the PMOS transistor M 1  in response to the current or voltage externally applied to the adjustment terminal ADJUST. 
     Thus, the second amplifier  12  of the present embodiment employs PMOS transistors (M 1 , M 2 ) as input transistors and NMOS transistors (M 3 , M 4 ) as load transistors and provides the same effect as described in connection with the first embodiment. 
     Fourth Embodiment 
     The second amplifiers of the first to third embodiments are feedback differential-to-single-ended converter circuits which automatically adjust the offset of the first amplifier. A second amplifier of a fourth embodiment of the present invention, on the other hand, is a feedforward differential converter circuit functioning as a unity gain buffer for the first amplifier and does not provide automatic offset adjustment. 
       FIG. 5  is a block diagram showing a differential signal generator circuit of the present embodiment. Referring to  FIG. 5 , a first amplifier  11  compares the input signal V IN  with a threshold voltage V th  and outputs differential signals V +  and V − . A second amplifier  12  receives the input signal V IN  through a resistance  13  and also receives its own output signal as feedback, and outputs the threshold voltage V th . That is, the second amplifier  12  adjusts the threshold voltage V th  in response to the input signal V IN . One end of the resistance  13  is grounded through a capacitance  14 . The discriminator circuit ( 15 ) is a clock and data recovery (or CDR) circuit, etc., and determines, based on the average values of the differential signals V +  and V −  output from the first amplifier  11 , whether the input signal V IN  is at a logical high level or a logical low level. 
       FIG. 6  is a circuit diagram of the second amplifier  12  of the present embodiment. As shown, the second amplifier is a differential input, single-ended output amplifier. Referring to  FIG. 6 , NMOS transistors M 1  and M 2  (referred to as a “first transistor” and a “second transistor,” respectively, in the appended claims) form a differential pair. The input signal V IN  is input to the gate of the NMOS transistor M 1 . The drain and gate of the NMOS transistor M 2  are connected together. 
     Referring still to  FIG. 6 , PMOS transistors M 3  and M 4  (referred to as a “third transistor” and a “fourth transistor,” respectively, in the appended claims) form a current mirror. The PMOS transistor M 3  is connected between the drain of the NMOS transistor M 1  and a voltage source (or reference potential point), and the PMOS transistor M 4  is connected between the drain of the NMOS transistor M 2  and the voltage source. The sources of the NMOS transistors M 1  and M 2  are connected together at a node, and an NMOS transistor M 5  is connected between this node and ground potential. A predetermined voltage V bias  is applied to the gate of the NMOS transistor M 5  so that the NMOS transistor M 5  functions as a current source. The drain voltage of the NMOS transistor M 2  is output as the threshold voltage V th . That is, the second amplifier  12  adjusts the threshold voltage V th  by applying the drain voltage of its NMOS transistor M 2 . 
     Further, the gate and drain of an NMOS transistor M 6  are connected to an adjustment terminal ADJUST, and its source is grounded. The drain of an NMOS transistor M 7  is connected to the drain of the NMOS transistor M 1 , and the source of the NMOS transistor M 7  is grounded. The NMOS transistors M 6  and M 7  constitute an adjusting section  16  which adjusts the drain current of the NMOS transistor M 1  in response to the current or voltage externally applied to the adjustment terminal ADJUST. This allows for easy adjustment of the cross-point of the differential signals, as in the first embodiment. 
     Obviously many modifications and variations of the present invention are possible in the light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described. 
     The entire disclosure of a Japanese Patent Application No. 2007-143778, filed on May 30, 2007 including specification, claims, drawings and summary, on which the Convention priority of the present application is based, are incorporated herein by reference in its entirety.