Abstract:
An RF MOS transistor having improved AC output conductance and AC output capacitance includes parallel interdigitated source and drain regions separated by channel regions and overlying gates. Grounded tap regions contacting an underlying well are placed contiguous to source regions and reduce distributed backgate resistance, lower backgate channel modulation, and lower output conductance.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    The present invention is related to the design of MOS transistors and, in particular, to the design of MOS transistors operating in the RF frequency region.  
           [0002]    Current semiconductor processing technologies have enabled the reduction of sizes of transistors with critical dimensions below 0.25 μm. Critical dimensions are now approaching 0.18 μm and even more aggressive technologies are considering critical dimensions of 0.13 μm. The operating frequencies of the resulting integrated circuits have risen to such an extent that MOS (Metal-Oxide-Semiconductor) integrated circuits are being used for RF (Radio Frequency) applications.  
           [0003]    However, at high frequencies the transistors operate less efficiently in some applications. This is especially true when the MOS transistor is used in a receiving circuit, which is required to have high linearity and low-noise. The AC output conductance and the AC output capacitance of the transistor are adversely affected. The output conductance increases with frequency and the output capacitance becomes highly dependent upon the device&#39;s bias. An increase in output conductance results in reduced gain and bias dependency results in added distortion. Additionally, in a low-noise amplifier circuit, unintended and undesirable circuit feedback voltage may be induced from the back gate-to-source connection.  
           [0004]    Therefore, an MOS transistor for RF operations in which the shortcomings above are solved or substantially alleviated is desirable. The present invention provides for such an MOS transistor, which is highly suitable for operation with RF circuits.  
         BRIEF SUMMARY OF THE INVENTION  
         [0005]    The present invention provides for an RF MOS transistor having a plurality of elongated first source/drain regions, a plurality of elongated second source/drain regions that are parallel to and interdigitated with the elongated first source/drain regions in a semiconductor substrate, a plurality of elongated gate electrodes over the semiconductor substrate defining channel regions separating the elongated first source/drain regions from the elongated second source/drain regions; and a plurality of elongated tap regions in the semiconductor substrate parallel to and interdigitated with the elongated first and second source/drain regions. The elongated tap regions provide an electrical voltage reference for the channel regions and are arranged so that each elongated second source/drain region is abutted to an elongated tap region.  
           [0006]    The present invention further provides for an integrated circuit having a circuit block having input and output terminals each having AC signals at an RF frequency and, at least, one RF MOS transistor connected to the circuit block. The RF MOS transistor has a plurality of drain regions elongated and parallel in the semiconductor substrate of the integrated circuit, a plurality of source regions elongated in the semiconductor substrate parallel to and interdigitated with the drain regions, a plurality of elongated gate electrodes over the semiconductor substrate defining channel regions separating the elongated drain regions from the elongated source regions, and a plurality of elongated tap regions in the semiconductor substrate that are parallel to and interdigitated with the elongated drain and source regions. Drain regions are connected to each other in parallel by a drain terminal that is coupled to a first power supply. The source regions are connected to each other in parallel by a source terminal that is coupled to an RF ground; the gate electrodes are connected to each other in parallel to a gate terminal that is connected to the circuit block input terminal. The tap regions are connected to the source regions locally. The tap regions provide an electrical voltage reference for the channel regions and are arranged so that each elongated source region is contiguous to an elongated tap region so that backgate modulation of the channel regions is reduced. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]    [0007]FIG. 1A is a plan view for the layout of a conventional RF MOS transistor; FIG. 1B is a cross-sectional view of the RF MOS transistor of FIG. 1A; FIG. 1C is representation of a circuit schematic of the RF MOS transistor of FIG. 1A that shows the back-gate resistance between the well tap and the intrinsic transistor back-gate terminal;  
         [0008]    [0008]FIG. 2 is a block diagram of an exemplary RF circuit that uses RF MOS transistors;  
         [0009]    [0009]FIG. 3A is a plan view for the layout of an RF MOS transistor according to one embodiment of the present invention; FIG. 3B is a cross-sectional view of the RF MOS transistor of FIG. 3A;  
         [0010]    [0010]FIG. 4A is a comparison plot of measured data of AC output conductance versus the drain current I ds  at a fixed drain-to-source voltage V ds  for a conventional RF MOS transistor and an RF MOS transistor according to one embodiment of the present invention; FIG. 4B is a similar comparison plot of measured data of the output capacitance versus the drain current I ds  at a fixed drain-to-source voltage V ds ; FIG. 4C is another comparison plot of measured data of the transconductance g m  versus drain current I ds  at a fixed drain-to-source voltage V ds ; FIG. 4D is still another comparison plot of the feedback capacitance C fb  versus the drain current at a fixed drain-to-source voltage V ds ; and FIG. 4E is another comparison of input capacitance versus drain current. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0011]    [0011]FIGS. 1A and 1B illustrate a conventional RF NMOS transistor in a semiconductor substrate  10 . The transistor has a plurality of source regions  11  that are interdigitated with drain regions  12 . The source and drain regions  11 ,  12  are formed by N+-type regions formed in a P-type well  18  in the substrate  10 . Gate electrodes  13  lie over channel regions between the source and drain regions  11 ,  12  and are connected in parallel by a metal interconnect  14 . The source and drain regions  11 ,  12  are likewise connected in parallel respectively. The interconnects for these parallel connections are not shown in the drawings. Isolating the source and gate regions  11 ,  12  is an insulating oxide layer  15  in a trench surrounding the regions  11 ,  12 . A P+-type tap  16  rings the oxide layer  15  (and source and gate regions  11 ,  12 ) at the periphery of the transistor and provides an electrical contact to the P-well  18  in that the source and drain regions  11 ,  12  are located.  
         [0012]    [0012]FIG. 1C is a circuit element symbol of the RF NMOS transistor of FIGS. 1A and 1B. For ease of understanding, the same reference numerals are used for the terminals of the NMOS transistor circuit symbol and for the corresponding parts of the transistor in FIGS. 1A and 1B. The circuit symbol is discussed in greater detail below.  
         [0013]    A common application for RF MOS transistors is shown in FIG. 2. Low-Noise Amplifier circuits typically have a differential input pair with inductive series-series feedback inductors  23 A and  23 B, as shown in FIG. 2. An antenna  20 , represented by a voltage source and a resistor is connected to a block  21  that represents an impedance-matching network and balun. The particular circuitry for the block  21  is well known to circuit designers and beyond the scope of the present invention. The output signal from the block  21  is an RF signal. In one particular application the signal has a frequency greater than 2 GHz and varies in amplitude from approximately 1 μV to 1V peak-to-peak. It should be understood that the DC component of the voltage, or bias voltage, on the terminals of the RF MOS transistors  22 A and  22 B exist but are not discussed in any detail since it is the RF signals, i.e., the AC components, that create the problems addressed by the present invention. The AC input signals are received by the gate electrodes of a differential pair of RF MOS transistors  22 A and  22 B, such as described with respect to FIGS. 1A and 1B. The source of the RF MOS transistors  22 A,  22 B are connected respectively to the inductors  23 A and  23 B, that are both connected to ground through a common inductor  25 . The drains of the RF MOS transistors  22 A,  22 B are connected to the amplifier circuit output terminals, that are also connected to a positive supply voltage terminal at V DD  through a matched pair of inductors  24 A and  24 B respectively. A capacitor  26  having a selected capacitance to tune the output circuit is also connected to the positive supply voltage terminal.  
         [0014]    As shown, the backgates, or P-type well in which the transistor channel regions are located, of the RF NMOS transistors  22 A and  22 B are conventionally tied to ground. Such connections ensure that the threshold voltage V T  of the transistors is fixed so that the transistors operate consistently with the input gate voltages V gs . For example, in many RF applications of the MOS transistor, such is in the present exemplary application, the transconductance (g m =I ds /V gs ) from the AC gate voltage to the AC drain-source current is used. If the threshold voltage is allowed to move, then the signal voltage V Gs  does not accurately control the source-drain current, I D , of the transistor.  
         [0015]    Such a problem does arise in the conventional RF MOS transistors. For the RF signals, an undesirable voltage V BS  appear between the backgate and the source of each transistor  22 A and  22 B, as represented in FIG. 1C by the resistor symbol. The V BS  voltage appears due to the distributed resistance in the P-well  18  between the grounded tap  16  (See FIGS. 1B and 1C) and the channel region of the transistor. This backgate voltage V BS  undesirably modulates the transistor&#39;s channel region and the source-drain current I D  through the resistive back-gate terminal, as symbolically illustrated in FIGS. 1B and 1C. The unintended and undesired results are: 1) increased RF output conductance that lowers the gain (Gain˜g m /G out ); 2) nonlinear output capacitance that increases the intermodulation distortion under high input signal conditions; 3) backgate modulation of the transistor channel region by the feedback network; and 4) susceptibility of the transistors to within-substrate interference at low frequencies and at RF from other elements of the integrated circuit.  
         [0016]    The present invention provides for an RF MOS transistor that avoids or substantially solves many of these problems. As shown in FIGS. 3A and 3B, the MOS transistor according to one embodiment of the present invention has its source regions  31  split into two parts and an active area tap  37  to the underlying P-well  38  is inserted between the source regions  31 . The result is that each portion of the MOS transistor has a source region  31  on either side of a drain region  32  and gate electrodes  33  over the channel regions between the source and drain regions  31  and  32 . As in the case of the conventional RF MOS transistor described previously, the different regions of the MOS transistor are all connected in parallel. The gate electrodes  33  are connected in parallel to a metal interconnect  34  and the source and drain regions  31  and  32  are respectively connected in parallel by metal interconnects (not shown). An isolating oxide layer  35  surrounds the source and drain regions  31 ,  32  and gate electrodes  33  in a shallow trench. Outside of and surrounding the oxide layer  35  is a grounded P+tap  36  that contacts the P-well  38 . The P-well  38  is also grounded by the active area taps  37 .  
         [0017]    Due to the close location of the taps  37  to the channel regions of the transistor, the distributed backgate resistance is lowered. When the MOS transistor is used in a common-source mode configuration, such as in an RF amplifier, this lowered resistance results in a lower backgate channel modulation. Additionally, the lowered resistance from the backgate channel region to common-source results in lower output conductance for the transistor. The lower output conductance creates a more ideal AC performance at radio and microwave frequencies for the MOS transistor.  
         [0018]    Measured data illustrated in FIGS.  4 A- 4 D show the marked performance improvement of the MOS transistor according to the present invention versus that of a conventional MOS transistor. A 0.18 μm process was used to manufacture both MOS transistors; operation is at radio frequencies.  
         [0019]    [0019]FIG. 4A plots the AC output conductance versus the drain current I ds , at a fixed drain-to-source voltage V ds =1V for a conventional MOS transistor (indicated by “o” data points) and the present invention&#39;s MOS transistor (indicated by “+” data points). The AC frequency is at 3 GHz. As shown, the present invention indicates an improved output conductance at 2 mA from 1.1 mS to 0.6 mS. This reduction in output conductance improves the gain of the MOS transistors at RF frequencies. FIG. 4B shows the output capacitance versus the drain current I ds  at the fixed drain-to-source voltage V ds =1V for a conventional MOS transistor (indicated by “o” data points) and the present invention&#39;s MOS transistor (indicated by “+” data points). The AC frequency is at 3 GHz. With the present invention, the output capacitance variation with the drain current is significantly reduced from 225% to 38%. This more linear output capacitance with respect to Ids decreases the intermodulation distortion for high frequency input signals. FIG. 4C shows the transconductance g m  versus drain current I ds  at the fixed drain-to-source voltage V ds =1V for a conventional MOS transistor (indicated by “o” data points) and the present invention&#39;s MOS transistor (indicated by “+” data points). The AC frequency is at 3 GHz. As shown in the plot, the transconductance of both transistors are the same. Finally, FIG. 4D shows the feedback capacitance C fb  versus the drain current at the fixed drain-to-source voltage V ds =1V. Again, the conventional MOS transistor is indicated by “o” data points and the present invention&#39;s MOS transistor indicated by “+” data points. At 3 GHz frequency, the feedback capacitances of both transistors are the same.  
         [0020]    It should be noted that with these improvements, i.e., a significantly lower output conductance and variation in output capacitance, and no difference in the transconductance and the feedback capacitance, the RF MOS transistor, according to the present invention, has a small undesired increase in input capacitance. As shown in FIG. 4E, C in  is about 10% higher than that of the conventional MOS transistor at 3 GHz, which is the result of improving the reduction of the backgate resistance.  
         [0021]    Nonetheless, with the MOS transistor of the present invention, a circuit that more nearly approaches an ideal Low-Noise Amplifier circuit is achieved. The undesirable modulation of the channel through the back-gate is nearly eliminated by reducing the backgate resistance and the susceptibility of the MOS transistors to interference at low and RF frequencies generated within the integrated circuit is greatly reduced.  
         [0022]    Therefore, while the description above provides a full and complete disclosure of the preferred embodiments of the present invention, various modifications, alternate constructions, and equivalents will be obvious to those with skill in the art. For example, it should be evident that though the RF MOS transistors were described in terms of N-type MOS technology, P-type MOS technology could be used in certain circumstances. Thus, the scope of the present invention is limited solely by the metes and bounds of the appended claims.