Abstract:
This invention discloses a system and method for dynamically managing voltage and frequency in an integrated circuit (IC), comprising a plurality of ring oscillators for generating a plurality of continuous pulses with frequencies reflecting the process parameter, operating voltage and temperature effects in the IC, a period generator for generating at least one gating period with a predetermined duration, a plurality of counters coupling to the plurality of ring oscillators as well as the period generator for counting the number of the continuous pulses in the gating period, at least one selector for selecting a predetermined number counted by the plurality of counters, and at least one voltage-and-frequency adjustment circuitry for adjusting one or more operating voltages or one or more clock frequencies in the IC based on the predetermined number selected by the selector, wherein the IC operating voltage or clock frequency correlates with the ring oscillator frequencies.

Description:
BACKGROUND 
       [0001]    The present invention relates generally to integrated circuit designs, and more particularly, to a system and method for dynamically managing power and frequency in an integrated circuit. 
         [0002]    Battery-powered electronics systems continue to demand greater performance while strictly limiting the power consumption by device electronics, and particularly by their processors which consume the most power in the systems. Such battery-powered systems include laptop computers, personal digital assistants (PDAs), cell phones, and personal music and/or video players. 
         [0003]    The performance of a processor is determined by the frequency of operation and the number of operations that can be completed on average per processor clock cycle. A dynamic power consumed in a CMOS transistor resulting from the switching of a load capacitance, C L , through a voltage, V dd , at a clock frequency, f, is 
         [0000]    
       
         
           
             P 
             = 
             
               
                 1 
                 2 
               
                
               
                 
                   C 
                   L 
                 
                 · 
                 
                   V 
                   dd 
                   2 
                 
                 · 
                 
                   f 
                   . 
                 
               
             
           
         
       
     
         [0000]    Then dynamic power consumed in a chip is the sum of the power consumed by all its switching nodes. It can be modeled as the power of switching the average switching capacitance of the system, C SW , through the voltage, V dd , 
         [0000]    
       
         
           
             
               
                 
                   P 
                   = 
                   
                     
                       1 
                       2 
                     
                      
                     
                       
                         C 
                         SW 
                       
                       · 
                       
                         V 
                         dd 
                         2 
                       
                       · 
                       f 
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
         [0004]    Examination of Equation (1) shows that if a slight voltage dependence of the switching capacitance is ignored, the dynamic power consumption of a system is quadratically more sensitive to power-supply voltage than is the clock frequency. While clock frequency determines a system&#39;s performance, voltage is much more sensitive to power efficiency. When voltage supply to an integrated circuit is lowered, its operating frequency will be lowered as well. So in order to maintain a performance level, a certain clock frequency is required, then the system seeks a minimum voltage to maintain that clock frequency. 
         [0005]    In some cases, different applications may have difference performance requirements. Using laptop computers as an example, the computational requirements can be considered to fall into one of three categories: compute-intensive, low-speed, and idle. Compute-intensive and short-latency tasks (e.g., video decompression, speech recognition, complex spreadsheet operations, etc.) utilize the full throughput of the processor. Low speed and long-latency tasks (e.g., text entry, address book browsing, playing music, etc.) only require a fraction of the full processor throughput to adequately run. Executing these tasks faster than the desired throughput rate has no discernible benefit. In addition, there are system idle periods because single-user systems are often not actively computing. A key design objective for the processor systems in these applications is to provide the highest possible peak throughput for the compute-intensive tasks while maximizing the battery life for the remaining low speed and idle periods. 
         [0006]    A common power-saving technique is to reduce the clock frequency during non-compute-intensive activity. This reduces power, but does not affect the total energy consumed per task, since energy consumption is independent of clock frequency to a first order approximation. Intuitively, executing a task slower only takes longer time, and total energy consumption is still the same. Conversely, reducing the voltage of the processor improves its energy efficiency, but compromises its peak throughput. If, however, both clock frequency and supply voltage are dynamically varied in response to computational load demands, then the energy consumed per task can be reduced for the low computational periods, while retaining peak throughput when required. When a majority of the computation does not require maximum throughput, then the average energy consumption can be significantly reduced, thereby increasing the computation that can be done with the limited energy supply of a battery. 
         [0007]    A prior art dynamic voltage and frequency management (DVFM) system employs dynamic frequency and voltage scaling separately. The dynamic frequency scaling module monitors activity levels of main logic circuits, and scales up the frequency when the circuit activity is high, and scales down the frequency when the circuit activity is low. After the frequency is determined, the separate dynamic voltage scaling module scales the supply voltage, i.e., increasing, decreasing or keeping the present supply voltage, based on delay information of the main logic circuits. There are drawbacks of this kind of DVFM system, such as its circuit is very complicated due to separate dynamic frequency and voltage scaling modules. It also cannot determine the lowest frequency the circuit can operate given a certain supply voltage. 
         [0008]    As such, what is desired is a DVFM system that are easy to implement and can control voltage and frequency with greater flexibility. 
       SUMMARY 
       [0009]    This invention discloses a system and method for dynamically managing voltage and frequency in an integrated circuit (IC), comprising a plurality of ring oscillators for generating a plurality of continuous pulses with frequencies reflecting process parameters, operating voltage and temperature (PVT) effects in the IC, at least one period generator for generating at least one gating period with a predetermined duration, a plurality of counters coupling to the plurality of ring oscillators as well as the period generator for counting the number of the continuous pulses in the gating period, at least one selector for selecting a value from a plurality of numbers counted by the plurality of counters, and at least one voltage-and-frequency adjustment circuitry for adjusting operating voltage or clock frequency in the IC based on the counted value selected by the selector. 
         [0010]    The construction and method of operation of the invention, however, together with additional objectives and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a block diagram illustrating a dynamic voltage and frequency management system according to one embodiment of the present invention. 
           [0012]      FIG. 2  is a waveform diagram illustrating a voltage quantifying scheme by using a counter. 
           [0013]      FIGS. 3A and 3B  are block diagrams illustrating a close-loop and open-loop voltage-and-frequency adjustment circuitries, respectively. 
           [0014]      FIGS. 4A and 4B  illustrates an open-loop index table for voltage and frequency controls, respectively. 
       
    
    
     DESCRIPTION 
       [0015]    The present invention discloses a system and method for dynamically managing voltage and frequency in integrated circuits (ICs). 
         [0016]    The invention and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. Descriptions of well known components and processing techniques are omitted so as not to unnecessarily obscure the invention in detail. It should be understood, however, that the detailed description and the specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only and not by way of limitation. Various substitutions, modifications, additions and/or rearrangements within the spirit and/or scope of the underlying inventive concept will become apparent to those skilled in the art from this detailed description. 
         [0017]      FIG. 1  is a block diagram illustrating a dynamic voltage and frequency management (DVFM) system  100  for an IC according to one embodiment of the present invention. The DVFM system  100  comprises a plurality of ring oscillators  110 [ 0 : n ], a period generator  120 , a plurality of counters  130 [ 0 : n ], a selector  140 , a close-loop voltage-and-frequency adjustment circuitry  150  and an open-loop voltage-and-frequency adjustment circuitry  160 . Outputs of the ring oscillators  110 [ 0 : n ] are connected to the inputs of the corresponding counter  130 [ 0 : n ]. The output of the period generator  120  feed to all the counters  130 [ 0 : n ]. All the counter  130 [ 0 : n ]&#39;s outputs, count[ 0 : n ], are connected to the selector  140 &#39;s inputs. A selector  140 &#39;s output is connected to the close-loop voltage-and-frequency adjustment circuitry  150  and an open-loop voltage-and-frequency adjustment circuitry  160  if the system employs both of them. In some cases, only one voltage-and-frequency adjustment circuitry, either close-loop  150  or open-loop  160 , is used. 
         [0018]    The ring oscillators  110 [ 0 : n ] are designed to emulate the effect of process parameters, operating voltage and temperature (PVT) of critical paths in the IC. Process parameters across a wafer as well as across a die may vary, placing multiple ring oscillators across a die tracks such variations. In a slow corner the ring oscillator placed there will all oscillate at a slower frequency than a normal frequency. When the operating voltage increases, the ring oscillator frequency will also increase. Temperature affects the ring oscillator through altering device parameters, a net effect is when temperatures increase, and the ring oscillator frequency decreases. 
         [0019]    The period generator  120  produces a pulse of predetermined pulse width or period, which determines a length of time during which the counter  130  counts the number of pulses the ring oscillator  110  generates. The longer the pulse width of the period generator  120 , the finer granulation the DVFM system can emulate the effect of the PVT variations. The predetermined pulse width is programmable by modifying a denominator (N). 
         [0020]      FIG. 2  is a waveform diagram illustrating a parameter quantifying scheme by using the counters  130 [ 0 : n ]. The counter  130  has two inputs, one is continuous pulses  210 , and the other is a single gating period  220 . At a rising edge of the gating period  220 , the counter  130  starts counting the number of continuous pulses  210 , and at a falling edge of the gating period  220 , the counter  110  stops counting. Then a total number of the continuous pulses that passes the gating period  220  is obtained and serves as an output  230  of the counter  130 . If the gating period  220  is fixed, than the counter output  230  is proportional to the frequency of the continuous pulse  210 . On the other hand, if the frequency of the continuous pulse  210  is fixed, then the counter output  230  is proportional to a length of the gating period  220 . 
         [0021]    Referring back to  FIG. 1 , according to one embodiment of the present invention, the continuous pulse  210  is an output of the ring oscillator  110 [ n ], which correlates with the effect of the PVT. The gating period  220  is an output of the period generator  120 . Then the counter  130  quantifies the PVT effects on the die. 
         [0022]    Referring to  FIG. 1 , the selector  140  is used to select a smallest number from its inputs, count[ 0 : n ]. In another case, the selector  140  can choose a particular counter-and-ring-oscillator path which is considered as most critical to the circuit performance. An output of the selector  140  sends a signal S to the voltage-and-frequency adjustment circuitry  150  for determining a lowest operating voltage given a frequency or a highest operating frequency given to a voltage to achieve power a saving purpose for the IC. 
         [0023]      FIG. 3A  is block diagram illustrating a close-loop voltage-and-frequency adjustment circuitry  150 . Signal S serves as an input to both close-loop comparators  310  and  330 , which base on programmable high-and-low watermarks to translate signal S into operating voltage and clock frequency control signals, respectively. 
         [0024]    Referring to  FIG. 3A , a voltage controller  320  takes the operating voltage control signal as an input and updates the operating voltage of the corresponding power domain continuously. Supposing the IC requires operating at a certain frequency, and the DVFM system has been previously characterized in worst case condition for this frequency that a voltage high water mark is M, and a voltage low water mark is N. If the IC operates at a low temperature or the IC has better process parameters, and as a result, the signal S can be a value larger than M, which means at current clock frequency, the operating voltage of the IC can still be lowered. Lower operating voltage reduces the ring oscillator  110 [ 0 : n ]&#39;s frequency, then counter  130 [ 0 : n ]&#39;s outputs and selector  140 &#39;s output, i.e., the signal S, will all be lowered, until it becomes less than M. In such way, for every given frequency, the DVFM system can determine a lowest operating voltage. But if the signal S is a value smaller than N, it means the IC operates at a very worse condition (e.g. Voltage is too low). In this case, the operating voltage has to rise to maintain correct functionality. 
         [0025]    Referring to  FIG. 3A , similarly, a frequency controller  340  takes the clock frequency control signal as an input and updates the clock frequency of the corresponding circuit continuously. Supposing the IC requires operating at a certain voltage, and the DVFM has previously characterized in worst case condition for this operating voltage that a frequency high water mark is P, and a frequency low water mark is Q. If the IC operates at a low temperature or the IC has better process parameters, and as a result, the signal S can be a value larger than P, which means at current operating voltage, there are still rooms to raise the clock frequency, and the frequency controller  340  raises the clock frequency accordingly. Higher clock frequency increases the temperature of the corresponding circuit, thus the ring oscillator  110  [ 0 : n ]&#39;s frequency is reduced as well, then the counter  130  [ 0 : n ]&#39;s outputs and selector  140 &#39;s output, i.e. the signal S, will all be lowered, until it becomes less than P. In such way, for every given operating voltage, the DVFM system can determine a highest clock frequency. But if the signal S is smaller than Q, it means the IC operates in a very worse condition (e.g. Temperature is too high). In this case, the frequency has to lower to maintain correct functionality. 
         [0026]      FIG. 3B  is a block diagram illustrating an open-loop voltage-and-frequency adjustment circuitry  160 . Signal S serves as an input to both open-loop index tables  350  and  370 , which is based on a programmable voltage and frequency index tables to translate signal S into operating voltage and clock frequency control signals, respectively. A voltage controller  360  takes the operating voltage control signal to change an operating voltage to a targeted value. Similarly, a frequency controller  380  takes the clock frequency control signal to change a clock frequency to a targeted value. 
         [0027]      FIGS. 4A and 4B  illustrates an open-loop index table for voltage and frequency controls, respectively. Referring to  FIG. 4A , an open-loop index table  405  stores two columns of data, ring OSC count number in column  410  and its corresponding voltage value in column  420 . From a ring OSC count number in columns  410 , a voltage value can be determined from a corresponding row in column  420 . Referring to  FIG. 4B , similarly, an open-loop index table  425  stores two columns of data, ring OSC count number in column  430  and its corresponding frequency in column  440 . From a ring OSC count number in column  430 , a frequency can be determined from a corresponding row in column  440 . 
         [0028]    Referring to  FIG. 3B  and  FIG. 4A , supposing the IC requires to operate at a certain performance level, and after it is set, the signal S will be used to be compared with the ring OSC count values stored in column  410 . If the IC operates at a low temperature or the IC has better process parameters, and as a result, the signal S is number A, which is higher than the ring&#39;s OSC count number R and less than the ring OSC count number R+1, then the operating voltage of the IC can be lowered and set to the voltage value R stored in column  420 . In such way, for every given frequency, the DVFM system can determine a lowest operating voltage. 
         [0029]    Referring to  FIG. 3B  and  FIG. 4A , similarly, supposing the IC requires operating at a certain performance level, and after it is set, the signal S will be used to be compared with the ring&#39;s OSC count values stored in column  430 . If the IC operates at a low temperature or the IC has better process parameters, and as a result, the signal S is number A, which is higher than the ring&#39;s OSC count number R and less than the ring OSC count number R+1. Then it means at current operating voltage, there are still rooms to raise the clock frequency, and the frequency controller  380  raises the clock frequency according to the frequency value R stored in column  440 . In such way, for every given operating voltage, the DVFM system can determine a highest clock frequency. 
         [0030]    The above illustration provides many different embodiments or embodiments for implementing different features of the invention. Specific embodiments of components and processes are described to help clarify the invention. These are, of course, merely embodiments and are not intended to limit the invention from that described in the claims. 
         [0031]    Although the invention is illustrated and described herein as embodied in one or more specific examples, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention, as set forth in the following claims.