Abstract:
Provided is a successive approximation register analog-to-digital converter (SAR ADC) including a digital-to-analog converter (DAC) generating and outputting first and second level voltages based on first and second analog input signals and a reference voltage signal; a comparator comparing the first and second level voltages and outputting a comparison signal according to a comparison result; and an SAR logic generating a digital signal based on the comparison signal, wherein the DAC includes: first and second input switches controlling reception of the first and second analog input signals, respectively; a first discharge switch connected electrically to the first input switch, the first discharge switch discharging leakage current according to an operation of the first input switch; and a second discharge switch connected electrically to the second input switch, the second discharge switch discharging leakage current according to an operation of the second input switch.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 of Korean Patent Application No. 10-2013-0087535, filed on Jul. 24, 2013, the entire contents of which are hereby incorporated by reference. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    The present invention disclosed herein relates to an analog-to-digital converter (ADC), and more particularly, to a successive approximation register ADC and method of operating a built-in self-test (BIST) device for testing the converter. 
         [0003]    An analog-to-digital converter (ADC) receives an analog input voltage and converts the voltage into a digital signal. The digital signal may be transmitted to other devices. A successive approximation register (SAR) ADC has a structure in which a comparator is repetitively used. Since the SAR ADC does not have an analog circuit such as a multiplying digital ADC and a sample and hold S/H circuit, it has a simple structure. Thus, it occupies a narrower area and consumes less power, as compared to other ADCs. Also, the SAR ADC is easily applied to a low-voltage circuit. 
         [0004]    The SAR ADC may receive output signals from sensors and convert them into digital signals. General sensors have a single-voltage output. Thus, the SAR ADC that converts the signals output from the sensors into digital signals needs to have a single-ended input structure. The SAR ADC includes an SAR logic, a comparator, and a digital-to-analog converter (DAC). 
         [0005]    A differential pre-amplifier and a latch may be used as a comparator for comparing the output of the DAC. In this case, the SAR ADC performs a conversion operation by comparing level voltages that are generated based on a digital bit and analog input voltage sampled on a capacitor. 
         [0006]    When an output range of a sensor having a single voltage as an output is within a range of a supply voltage Vdd, the voltage of a node connected to the top plate of a capacitor may be higher than the supply voltage Vdd. In this case, due to the malfunction of switches connected to the node having a voltage higher than the supply voltage Vdd, charges stored in the capacitor may be lost and the reliability of the SAR ADC may decrease. 
       SUMMARY OF THE INVENTION 
       [0007]    The present invention provides a successive approximation register analog-to-digital converter (ADC) and method of operating a built-in self-test device (BIST) for testing the converter that have enhanced reliability. 
         [0008]    Embodiments of the present invention provide successive approximation register analog-to-digital converters (SAR ADCs) including a digital-to-analog converter (DAC) generating and outputting first and second level voltages based on first and second analog input signals and a reference voltage signal; a comparator comparing the first and second level voltages and outputting a comparison signal according to a comparison result; and an SAR logic generating a digital signal based on the comparison signal, wherein the DAC includes: first and second input switches controlling reception of the first and second analog input signals, respectively; a first discharge switch connected electrically to the first input switch, the first discharge switch discharging leakage current according to an operation of the first input switch; and a second discharge switch connected electrically to the second input switch, the second discharge switch discharging leakage current according to an operation of the second input switch. 
         [0009]    In other embodiments of the present invention, methods of operating a built-in self-test (BIST) device for testing a successive approximation register analog-to-digital converter (SAR ADC) including storing first and second output codes in response to first and second input voltages; outputting a gain error based on a calculation result of a difference between the stored first and second output codes and a first normal code according to the second input voltage; storing third and fourth output codes in response to the second input voltage and the third input voltage; outputting an offset error based on a calculation result of the stored third output code and the first normal code; and outputting an integral non-linearity (INL) error based on a calculation result of a difference between the stored third and fourth output codes and a second normal code according to the third input voltage, wherein the SAR ADC receives a signal corresponding to the offset error from the BIST device and outputs an offset-corrected digital signal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The accompanying drawings are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present invention and, together with the description, serve to explain principles of the present invention. In the drawings: 
           [0011]      FIG. 1  is a block diagram of a successive approximation register analog-to-digital converter (SAR ADC) according to an embodiment of the present invention; 
           [0012]      FIG. 2  is a circuit diagram of a digital-to-analog converter (DAC) shown in  FIG. 1 ; 
           [0013]      FIG. 3  is a graph showing an integral non-linearity (INL) measurement of the SAR ADC; 
           [0014]      FIG. 4  is an example showing the operative characteristics of the SAR ADC; 
           [0015]      FIG. 5  is a flow chart showing a test operation on a gain error according to a built-in self-test (BIST) algorithm of the present invention; 
           [0016]      FIG. 6  is a flow chart showing a test operation on an offset error according to the built-in self-test (BIST) algorithm of the present invention; 
           [0017]      FIG. 7  is a flow chart showing a test operation on an INL error according to the built-in self-test (BIST) algorithm of the present invention; and 
           [0018]      FIG. 8  is a circuit diagram of a DAC according to another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0019]    In order to prescribe the present invention in detail so that a person skilled in the art may easily practice the technical spirits of the present invention, embodiments of the present invention are described below with reference to the accompanying drawings. The same components are denoted by using the same reference numerals. Like components are denoted by using similar reference numerals. A successive approximation register analog-to-digital converter (SAR ADC) according to the present invention to be described below and operations to be performed by using the SAR ADC are merely described as examples, and many variations and alterations may be made within the scope of the technical spirit of the present invention. 
         [0020]      FIG. 1  is a block diagram of a successive approximation register analog-to-digital converter (SAR ADC) according to an embodiment of the present invention. Referring to  FIG. 1 , an SAR ADC  10  includes a clock generator  100 , a comparator  200 , an SAR logic  300 , and a digital-to-analog converter (DAC)  400 . 
         [0021]    The clock generator  100  may generate a sampling clock CLKs and a conversion clocks CLK. The sampling clock CLKs and the conversion clock CLKc are delivered to the DAC  400  and the conversion clock CLKc is delivered to the comparator  200 , the SAR logic  300 , and the DAC  400 . In the embodiment, the sampling clock CLKs and the conversion clock CLKc may be reversed clocks. As an example, the DAC  400  may sample an input voltage Vin in response to the sampling clock CLKs. Also, the DAC  400  may generate first and second voltage levels Vn 1  and Vn 2  in response to the conversion clock CLKc. 
         [0022]    The comparator  200  compares the generated first and second level voltages Vn 1  and Vn 2 . Specifically, the comparator  200  includes a differential pre-amplifier  210  and a latch  220 . The differential pre-amplifier  210  receives the first and second level voltages Vn 1  and Vn 2  from the DAC  400  and compares the received first and second level voltages Vn 1  and Vn 2 . The differential pre-amplifier  210  amplifies the comparison result and delivers the amplified result to the latch  200 . In the embodiment, the differential pre-amplifier  210  may have any one of an NMOS input and a PMOS input. 
         [0023]    The latch  220  may store any one of “data 0” or “data 1” based on the comparison result amplified from the differential pre-amplifier  210 . For example, if the first level voltage Vn 1  is higher the second level voltage Vn 2 , the latch  220  stores the “data 1”. If the first level voltage Vn 1  is lower than the second level voltage Vn 2 , the latch  220  stores the “data 0”. 
         [0024]    The SAR logic  300  may determine a digital bit based on the data stored in the latch  220 , in response to the conversion clock CLKc. For example, the SAR ADC  10  may receive and convert an analog input Vin into a 3-bit digital signal. In a first conversion operation, all capacitors (shown in  FIG. 2 ) are connected to a common mode voltage Vcm by a decoding logic included in the DAC  400  and, the digital signals of the SAR logic  300  are reset to logic low. The comparator  200  determines most significant bit (MSB) and stores MSB determined from the latch  220 . 
         [0025]    The SAR logic  300  determines MSB based on the data stored in the latch  220 , in response to the conversion clock CLKc. If the “data 1” is stored in the latch  220 , the SAR logic  300  determines the MST as logic high. If the “data 0” is stored in the latch  220 , the SAR logic  300  determines the MSB as logic low. 
         [0026]    The SAR logic  300  determines the MSB and then delivers the determined MSB to the decoding logic included in the DAC  400 . The SAR logic  300  may determine least significant bit (LSB) through the repetition of the above-described operations. 
         [0027]    The DAC  400  receives the analog input voltage Vin, a reference voltage Vref, and a digital signal Dout from the SAR logic  300 . The DAC  400  may output the first and second level voltages Vn 1  and Vn 2  based on the received voltages and digital signal Dout. In the embodiment, the analog input voltage Vin may implemented as a first analog input voltage Vin_a (shown  FIG. 2 ) and a second analog input voltage Vin_b (shown in  FIG. 2 ) and applied to the DAC  400 . Also, the reference voltage Vref may be implemented as first and second reference voltages Vrefp and Vrefn. The first reference voltage Vrefp may be ½ times the supply voltage Vdd and the second reference voltage Vrefn may be 0 V. 
         [0028]    The DAC  400  samples the first and second analog input voltages Vin_a and Vin_b in response to the sampling clock CLKs. The DAC  400  may generate the first and second level voltages Vn 1  and Vn 2  in response to the conversion clock CLKc. Also, the level voltage is used for determining the voltage level of the analog input voltage Vin and is a value that is obtained by properly distributing the reference voltage Vref based on the digital resolution of the ADC. In the embodiment, the DAC  400  may be a capacitive DAC that operates based on charge redistribution. 
         [0029]    In the embodiment, the SAR ADC  10  has a single-ended input structure and the analog input voltage Vin applied to the DAC  400  may have a voltage level from 0 V to the supply voltage VDD. Also, the voltage level of the reference voltage Vref may generally have a level of the supply voltage VDD. As an example, if the voltage level of the supply voltage VDD according to the analog input voltage is 5 V, the voltage level of the reference voltage Vref also becomes 5 V. 
         [0030]    However, as an example, a battery attached to a vehicle may vary in the voltage level of the battery depending on an external condition and a drive operation. For example, if the level of the supply voltage VDD applied from the battery to the DAC is lower than the normal supply voltage VDD of the analog input voltage Vin, the operation of the DAC may have a problem. 
         [0031]    Thus, in the SAR ADC  10  according to the embodiment of the present invention is applied, the reference voltage Vref that is ½ times the supply voltage VDD is applied to the DAC  400 . The DAC  400  may receive the reference voltage Vref set as ½ times the supply voltage VDD to be able to stably perform the turn-on operation of a switch. Related descriptions are provided in detail through  FIG. 2 . 
         [0032]      FIG. 2  is a circuit diagram of the DAC shown in  FIG. 1 . Referring to  FIG. 2 , the DAC  400  includes a first conversion unit  410 , a second conversion unit  420 , and a decoding logic  430 . The analog input voltage Vin may be implemented as first and second analog input voltages Vin_a and Vin_b. As an example, the first analog input voltage Vin_a may be implemented as an input voltage having a level of the supply voltage VDD and the second analog input voltage Vin_b may be implemented as the common mode voltage Vcm. 
         [0033]    Also, for simplicity, the operation of the DAC  400  is described based on the process of determining MSB. 
         [0034]    It is assumed that the top plate of first and second capacitor arrays  411  and  421  indicates a surface where the first and second capacitor arrays  411  and  421  are connected to nodes from which the first and second level voltages Vn 1  and Vn 2  are output. It is assumed that the bottom plate of first and second capacitor arrays  411  and  421  indicates a surface of the third and fourth capacitor arrays  411  and  421  that is connected to first and third switch arrays  412  and  422 . 
         [0035]    In the embodiment, the digital logic  430  may generate a first control signal Q 1  in response to the sampling clock CLKs. Also, the digital logic  430  may generate a second control signal Q 2  in response to the conversion clock CLKc. 
         [0036]    The first conversion unit  410  generates the first level voltage Vn 1 . Specifically, the first conversion unit  410  includes the first capacitor array  411 , the first switch array  412 , a second switch array  413 , and a common mode switch Scm, a first input switch Sin_a, and a first discharge switch SA. 
         [0037]    The first capacitor array  411  includes a plurality of capacitors C 11  to C 1   n . The number of the capacitors C 11  to C 1   n  may be determined depending on the digital resolution of the SAR ADC  10 . For example, when the SAR ADC  10  has a 10-bit digital resolution, the first capacitor array  411  includes ten capacitors. The ten capacitors have different capacitances, respectively. The first conversion unit  410  may generate the first level voltage Vn 1  based on charge redistribution. 
         [0038]    The first switch array  412  includes a plurality of switches Q 11  to Q 1   n . In response to the first control signal Q 1 , the switches Q 11  to Q 1   n  may operate so that the first analog input voltage Vin_a is supplied to the bottom plate of the first capacitor array  411 . Specifically, the switches Q 11  to Q 1   n  operate so that the first analog input voltage Vin_a may be supplied, when the first control signal Q 1  is transited to a high level. Also, the switches Q 11  to Q 1   n  operate so that the first analog input voltage Vin_a is not supplied to the first capacitor array  411 , when the first control signal Q 1  is transited to a low level. 
         [0039]    The second switch array  413  includes a plurality of switches S 11  to S 1   n . In response to the second control signal Q 2 , the switches S 11  to S 1   n  may operate so that any one of the first reference voltage Vrefp and the second reference voltage Vrefn to the bottom plate of the first capacitor array  141 . 
         [0040]    As an example, the MSB of the digital signal Dout received when determining MSB would be logic high. In response to the conversion clock CLKc, the decoding logic  430  may control the first switch S 11  so that the first reference voltage Vrefp is supplied to the bottom plate of the capacitor C 11 . Generally, the decoding logic  430  may control the other switches S 12  to S 1   n  so that the common mode voltage Vcm is supplied to the bottom plate of the remaining capacitors C 12  to C 1   n  other than the capacitor C 11 . 
         [0041]    However, the first and second conversion units  410  and  420  of the present invention do not include a node for applying the common mode voltage Vcm. Instead, the DAC  400  according to the embodiment of the present invention applies the same first or second reference voltage Vrefp or Vrefn to both the first and second conversion units  410  and  420  for the implementation of the common mode voltage Vcm. Thus, a voltage having the effect of the common mode voltage Vcm may be applied to the bottom plate of the remaining capacitors C 12  to C 1   n  other then the capacitor C 11 . 
         [0042]    In response to the first control signal Q 1 , a first common mode switch Scm 1  may be connected so that the common mode voltage Vcm is supplied to the top plate of the first capacitor array  411 . In the embodiment, the common mode voltage Vcm may be ½ times the supply voltage VDD. 
         [0043]    The first discharge switch SA may prevent a leakage current from flowing on the first capacitor array  411 , namely, through a first node T 1 . In the embodiment, the first input switch Sin_a and the first discharge switch SA may be implemented as a CMOS transistor. 
         [0044]    Specifically, the turn-off operation of an NMOS transistor according to the first input switch Sin_a may be controlled by applying 0 V. However, the turn-off operation of a PMOS transistor according to the first input switch Sin_a may be adjusted by a level of the supply voltage VDD and the first analog input voltage Vin_a. In the turn-off operation of the first input switch Sin_a, the level of the supply voltage VDD controlling the operation of the first input switch Sin_a becomes lower than that of the first analog input voltage Vin_a according to an external condition and a drive operation and thus a leakage current may flow through the first node and the bottom plate of the first capacitor array  411 . 
         [0045]    The first discharge switch SA according to the present invention may discharge the leakage current flowing through the first node T 1  from the first input switch Sin_a, externally, namely, through a common mode voltage Vcm terminal. Specifically, the first input switch Sin_a and the first discharge switch SA may operate complementarily. If the turn-off operation of the first input switch Sin_a is completely performed, a leakage current may flow through the first node T 1 . The leakage current may be not applied to the first capacitor array  411  through the first node T 1  but discharged to the common mode voltage Vcm terminal through the first discharge switch SA. 
         [0046]    In the embodiment, the common mode voltage Vcm may be set as ½ times the supply voltage VDD. If the first input switch Sin_a is turned off, a voltage of VDD/ 2  may be applied to the first node T 1  in response to the common mode voltage Vcm applied through the first discharge switch SA. Also, in the embodiment, the first reference voltage Vrefp may be set as ½ times the supply voltage VDD. 
         [0047]    The second conversion unit  420  generates the second level voltage Vn 1 . Specifically, the second conversion unit  420  includes the second capacitor array  421 , the third switch array  422 , a fourth switch array  423 , a second common mode switch Scm 2 , a second input switch Sin_b, and a second discharge switch SB. 
         [0048]    The operation of the second conversion unit  420  is similar to that of the first conversion unit  410  and outputs the second level voltage Vn 2 . When compared to the first conversion unit  420 , the second conversion unit  420  may operate as a differential structure. Thus, the operation of the second conversion unit  420  is not described because it may be understood with reference to that of the first conversion unit  410 . 
         [0049]    The decoding logic  430  may receive the digital signal Dout from the SAR logic  300 . Also, the decoding logic  430  may receive the sampling clock CLKs and the conversion clock CLKc. The decoding logic  430  generates the first and second control signals Q 1  and Q 2  for controlling the first and second conversion units  410  and  420 , in response to the sampling clock CLKs and the conversion clock CLKc. 
         [0050]    As described above, the DAC  400  may sample the first and second analog input voltages Vin_a and Vin_b on the first and second capacitor arrays  411  and  421  respectively, in response to the first control signal Q 1 . The first and second conversion units  410  and  420  generate the first and second level voltages Vn 1  and Vn 2  based on the first and second analog input voltages Vin_a and Vin_b. The SAR logic  300  (See  FIG. 1 ) may determine a digital bit based on the difference between the generated first and second level voltages Vn 1  and Vn 2 . The SAR ADC  10  (See  FIG. 1 ) may convert the analog input voltage Vin into the digital signal Dout based on the repetition of these operations and output and output the digital signal. 
         [0051]      FIGS. 3 and 4  are graphs showing integral non-linearity (INL) measurement of the SAR ADC and the characteristics of a code according to an analog input voltage. As an example, it is described that a 10-bit code is output from the SAR ADC  10  (See  FIG. 1 ). Referring to  FIG. 3 , the horizontal axis is the output code of the SAR ADC  10  and the vertical axis shows the INL according to an output code. As an example, the output code of the SAR ADC  10  may be 10-bit based  1024  codes. The INL has a minimum at code  256  and zero at code  512 . Also, it may be seen that the INL measurement graph shown in  FIG. 3  has bilateral symmetry at the code  512 . 
         [0052]    Referring to  FIG. 4 , the horizontal axis represents the analog input voltage Vin applied to the DAC  400  (See  FIG. 1 ) and the vertical axis represents the output of the code. The SAR ADC  10  may output a code having a linear ideal curve, in response to the analog input voltage Vin. However, due to an offset error, a gain error, and the INL, a real curve may not match the ideal curve. 
         [0053]    A built-in self-test (BIST) device may analyze the digital signal Dout output from the SAR ADC  10  (See  FIG. 1 ) and monitor the offset error, the gain error, and an INL value. The operation of the BIST device is described in detail through  FIG. 5 . 
         [0054]      FIGS. 5 to 7  are flow charts showing the algorithms of the BIST device according to embodiments of the present invention. Referring to  FIGS. 3 to 7 , the performance of the SAR ADC  10  (See  FIG. 1 ) may be monitored according to the gain error G, the offset error O and the INL result that are measured from the BIST device. When the above-described three errors do not exist, codes may be detected in the shape of the ideal curve shown in  FIG. 4 . However, when the above-described three errors occur, a curve having an error may be detected through a comparison with the ideal curve. 
         [0055]    Referring to  FIG. 5 , in steps S 110  and S 120 , the BIST device may store a first output code Z 1 , in response to a compensation code C and the first input voltage Vin 1 , in step S 110 . Also, the BIST device may store a second output code Z 2  in response to the compensation code and the second input voltage Vin 2 , in step S 120 . The BIST device may detect the gain error G in response to the calculation result of the first and second output codes Z 1  and Z 2 . 
         [0056]    Specifically, the gain error G may be found through the difference between two codes that are output according to values. The values are ½ times the supply voltage VDD and the analog input voltage Vin of 0 V. As an example, the first input voltage Vin 1  may be 0 V, and the second input voltage Vin 2  may be ½ times the supply voltage VDD. For example, in the case of the 10-bit based ideal curve, the code output according to the first input voltage Vin 1  may be 0 and the code output according to the second input voltage Vin 2  may be 512. 
         [0057]    However, based on an external condition according to the process of manufacturing the SAR ADC, a minus code may be output in response to the first input voltage Vin 1 . In other words, the code 0 may be output according to the first input voltage Vin 1  and the code  512  may be output according to the second input voltage Vin 2  and thus it is not possible to obtain an exact gain error G result. Thus, in response to when the minus code is output, the compensation code C may be set to code 10 as an example. 
         [0058]    In third step S 130 , the BIST device may compare a measurement of the grain error G with a preset reference error G_th based on the first and second output codes Z 1  and Z 2 . 
         [0000]      Gain error  G =|( Z 2− Z 1)− I 1|×2  &lt;Equation 1&gt;
 
         [0059]    Referring to Equation 1, the gain error G may be obtained by subtracting the first output code Z 1  from the second output code Z 2 , subtract a first normal code I 1  from the value obtained through the subtraction and then taking two times ×2 the value obtained through the last subtraction. As an example, the first normal code I 1  may be a code output in response to the second input voltage Vin, based on the ideal curve (See  FIG. 4 ). In the case of a 10-bit based ideal curve, the first normal code I 1  may be 512. Also, the reason for the square ×2 is that output codes have bilateral symmetry at the first normal code I 1  as shown in  FIG. 4 . Thus, it is possible to detect the whole gain error G by detecting a left or right gain error and taking two times X 2 the detected error. 
         [0060]    Also, in fourth step S 140 , if the measured gain error G is greater than the preset reference error G_th (if YES), the BIST device makes an alarm relative to the gain error G. The BIST device ends the monitoring operation if the measured gain error G is less than the preset reference error G_th (if NO). 
         [0061]    Referring to  FIG. 6 , in first step S 210 , the BIST device may store a third output code Z 3  in response to the second input voltage Vin 2 . The BIST device may measure the offset error O in response to a calculation result according to the third output code Z 3 . 
         [0062]    In second step S 220 , the BIST device may compare a measurement of the offset error O with a preset reference error O_th based on the third output code Z 3 . 
         [0000]      Offset error  O=|Z 3− I 1|  &lt;Equation 2&gt;
 
         [0063]    Referring to Equation 2, the third output code Z 3  may be an output code obtained in response to the second input voltage Vin 2 . The first normal code I 1  may be a code output in response to the second input voltage Vin, based on the ideal curve. For example, in the case of the 10-bit based ideal curve, the first normal code I 1  may be 512. The BIST device may measure the offset error O by subtracting the first normal code I 1  from the third output code Z 3 . 
         [0064]    In third step S 230 , if the measured offset error O is greater than the preset reference error O_th (if YES), the BIST device makes an alarm relative to the offset error O. The BIST device ends the monitoring operation if the measured offset error O is less than the preset reference error O_th. 
         [0065]    Also, in the embodiment, the SAR ADC  10  according to the present invention receives the measured offset error O from the BIST device. The SAR ADC  10  may output an offset-corrected digital signal based on the received offset error O. 
         [0066]    Referring to  FIG. 7 , in first step S 310 , the IBST device may store a fourth output code Z 4  in response to a third input voltage Vin 3 . The BIST device may measure the INL in response to calculation results according to the third and fourth output codes Z 3  and Z 4 . As shown in  FIGS. 3 and 4 , the BIST device according to the present invention measures the INL according to a minimum Min, based on that the difference between the minimum Min and a maximum of the INL has symmetry within a certain range. As an example, the third input voltage Vin 3  may be set to ¼ times the supply voltage VDD for measuring the minimum Min of the INL. 
         [0067]    In second step S 320 , the BIST device may compare a measurement of an INL error I with a preset reference error I_th, based on the third and fourth output codes Z 3  and Z 4 . 
         [0000]      INL error  I =|( Z 3− Z 4)− I 2|
 
         [0068]    Referring to Equation 3, the INL error I may be obtained by subtracting the fourth output code Z 4  from the third output code Z 3  and then subtracting a second normal code I 2  from the value obtained through the subtraction. As an example, the second normal code I 2  may be a code output in response to the third input voltage Vin 3 , based on the ideal curve (See  FIG. 4 ). In the case of the 10-bit based ideal curve, the second normal code I 2  may be 256. 
         [0069]    In third step S 330 , if the measured ILN error I is greater than the preset reference error I_th (if YES), the BIST device makes an alarm relative to the INL error I. The BIST device ends the monitoring operations if the measured INL error I is less than the preset reference error I_th (if No). 
         [0070]    As described above, the BIST device according to the present invention may monitor the offset error O, the gain error G, and the INL error I, based on the digital signal output from the SAR ADC  10 . The SAR ADC  10  may output error-corrected digital signals, in response to information on errors detected from the BIST device. 
         [0071]      FIG. 8  is a circuit diagram of a DAC according to another embodiment of the present invention. Referring to  FIG. 8 , the DAC  500  includes a first conversion unit  510 , a second conversion unit  520 , and a decoding logic  530 . The DAC  500  has a structure in which the third input voltage Vin 3  required for measuring the INL error I described with respect to  FIG. 5 , namely ¼ times the supply voltage VDD may be used as the input voltage Vin. In other words, the DAC  500  according to the present invention may generate, as the input voltage Vin, 0 V or ½ times the supply voltage VDD but not ¼ times the supply voltage VDD. Thus, the DAC  500  may generate, through the distribution of capacitors, an input voltage that is ¼ times the supply voltage VDD. As an example, the input voltage Vin may have a voltage level from 0 V to the supply voltage VDD. 
         [0072]    Also, since the digital signal output process of the DAC  400  shown in  FIG. 2  is the same as that of the DAC  500 , related descriptions are omitted.  FIG. 8  describes how to implement an input voltage that is ¼ times the supply voltage VDD, for measuring the INL error I. 
         [0073]    The first conversion unit  510  includes first and second capacitor units  511  and  512 , first and second switch units  513  and  514 , a first input switch Sc 1 , a first discharge switch Sc 2 , and a first distribution switch Sc 3 . The second conversion unit  520  includes third and fourth capacitor units  521  and  522 , third and fourth switch units  523  and  524 , a fourth input switch Sd 1 , a fifth discharge switch Sd 2 , and a sixth distribution switch Sd 3 . 
         [0074]    For the INL measurement of the BIST device, the bottom plate of the first and third capacitor units  511  and  521  may be connected to the third and sixth distribution switches Sc 3  and Sd 3  in response to the high level of a first control signal Q. Also, the bottom plate of the second and fourth capacitor units  512  and  522  may be connected to the second and fourth discharge switches Sc 2  and Sd 2  in response to the high level of the first control signal Q. 
         [0075]    As described above, the first and second conversion units  510  and  520  may generate, through the distribution of capacitors, an input voltage that is ¼ times the supply voltage VDD. Also, the decoding logic  530  may generate first and second control signals Q 1  and Q 2  to be able to overall control the operations of the first and second conversion units  510  and  520 . 
         [0076]    The SAR ADC according to embodiments of the present invention may stably operate even under fluctuation in an internal supply voltage according to an external condition. Also, the SAR ADC may monitor ADC performance according to the BIST algorithm to be able to exactly determine whether there is an analog-to-digital conversion 
         [0077]    Hitherto, the embodiments are disclosed in the drawings and specification. While specific terms were used, they were not used to limit the meaning or the scope of the present invention described in Claims, but merely used to explain the present invention. Accordingly, a person having ordinary skill in the art will understand from the above that various modifications and other equivalent embodiments are also possible. Hence, the real protective scope of the present invention shall be determined by the technical scope of the accompanying claims.