Abstract:
A method to fabricate an interconnect structure is provided. First, an inter-metal dielectric layer is formed on a substrate. Then the inter-metal dielectric layer is etched to form a trench, and a barrier layer is formed on the trench. Afterwards, a metal layer is formed to fill the trench over the barrier layer. Then chemical mechanical polishing (CMP) is performed to remove the barrier layer and the metal layer on the inter-metal dielectric layer. Next, an adhesion layer is formed to cover the metal layer and the inter-metal dielectric layer. Finally, a sealing layer is formed to cover the adhesion layer.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates in general to a process for manufacturing an interconnect structure. In particular, the present invention relates to advance formation of an adhesion layer having superior adhesion characteristics on a metal layer, then formation of a sealing layer for anti-diffusion of ions of the metal layer. Therefore, the adhesion between the sealing layer and the metal layer of the interconnect structure will be improved to avoid the problems of electro-migration.  
           [0003]    2. Description of the Related Art  
           [0004]    In ultra large-scale integrated (ULSI) circuit manufacturing, semiconductor devices are fabricated on a substrate or a silicon wafer. After the formation of the devices, metal lines for interconnection are defined using a metallization. As the integration of integrated circuits increases, manufacturing with high yield and highly reliable metal interconnect lines is hard to achieve. A method of fabricating a metal-damascene structure is to etch trenches for metal interconnect lines and then fill the trenches with metal material. In addition, chemical mechanical polishing (“CMP” hereinafter) is used to polish the metal material. The method offers a better way to fabricate a submicron VLSI interconnection with high performance and high reliability.  
           [0005]    In the following description, a conventional method for fabricating a damascene structure on a substrate is explained with reference to FIGS. 1A to  1 D.  
           [0006]    First, referring to FIG. 1A, a substrate  100  is provided and a metal interconnect line  110  is fabricated in the substrate  100 . Next, a sealing layer  120  is formed covering the metal interconnect line  110 . Then, an inter-metal dielectric (IMD) layer  120  is formed covering the sealing layer  120 . The sealing layer  120  can be silicon nitride (SiN) or silicon carbide (SiC) The sealing layer  120  is provided for sealing the metal interconnect line  110  and for avoiding the ions of the metal interconnect line  110  diffusing to other parts of the semiconductor device, causing a short circuit of the semiconductor device. Next, referring to FIG. 1B, the IMD layer  130  is defined by the damascene to form a dual damascene structure  140  extending through the IMD layer  130  and the sealing layer  120  to the metal interconnect line  110 .  
           [0007]    Then, referring to FIG. 1C, a barrier layer  150  is formed on the sidewalls and the bottom of the dual damascene structure  140  and the IMD layer  130  by CVD or PVD. Afterwards, a metal layer  160  is formed on the dual damascene structure  140  on the barrier layer  150 . Finally, referring to FIG. 1D, CMP is performed to remove the metal layer  160  and the barrier layer  150  on the IMD layer  130  outside the dual damascene structure  140 .  
           [0008]    However, the requirement of adhesion between the copper metal layer and the sealing layer and the requirement of diffusion of the copper from the metal layer to the IMD layer are different. Therefore, a single sealing cannot meet the above requirements. For example, if the conventional sealing layer is SiN or SiC, but the conventional sealing layer is unable to adhere to the metal layer efficiently. Hence, electro-migration of the metal layer is generated, degrading the reliability of the semiconductor device.  
           [0009]    Moreover, while CMP is performed, some metal oxide will be generated on the surface of the metal line  160 . For example, if the metal is copper, the copper oxidizes, producing copper oxide (Cu 2 O). The oxide will increase the resistance of the metal line and cause the surface of the metal layer to bulge. Thus, adhesion between the sealing layer and the metal line will be decreased. Furthermore, the increased resistance of the metal line will generate more heat during operation of the semiconductor device. Moreover, when the adhesion between the sealing layer and the metal line deteriorates, the electro migration of the metal line will be degraded, which will negatively influence the performance of the semiconductor device.  
         SUMMARY OF THE INVENTION  
         [0010]    The object of the present invention is to provide a method for interconnect structure manufacture, which can satisfy both the requirement for adhesion between the copper metal layer and the sealing layer and that for the diffusion of the copper from the metal layer to the IMD layer. The method of the present invention forms an adhesion layer, which adheres to the metal layer efficiently. The adhesion layer maybe silicon oxynitride (SiON), silicon containing oxygen, nitrogen and hydrogen (SiONH), silicon containing nitrogen and hydrogen (SiNH), silicon containing carbon and nitrogen (SICN) or silicon containing carbon and hydrogen (SiCH). The method according to the present invention then forms a sealing layer on the adhesion layer, which allows the sealing layer to avoid metal ions diffusing from the metal layer. The sealing layer maybe silicon nitride (SiN) or silicon carbide (SiC).  
           [0011]    To achieve the above-mentioned object, the present invention provides a method to fabricate an interconnect structure, comprising the following steps.  
           [0012]    First, an inter-metal dielectric layer is formed on a substrate. Then the inter-metal dielectric layer is etched to form a trench. A barrier layer is formed on the trench. Afterwards, a metal layer is formed to fill the trench over the barrier layer. Then chemical mechanical polishing (CMP) is performed to remove the barrier layer and the metal layer on the inter-metal dielectric layer. After the CMP, an adhesion layer is formed on the metal layer. Finally, a sealing layer is formed to cover the adhesion layer. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]    The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings, given by way of illustration only and thus not intended to be limitative of the present invention.  
         [0014]    FIGS.  1 A- 1 D are section views illustrating a conventional method of manufacturing an interconnect structure.  
         [0015]    FIGS.  2 A- 2 J are section views illustrating a method of manufacturing an interconnect structure according to the embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0016]    A method of fabricating a dual damascene structure on a substrate is described herein with reference to FIGS. 2A to  2 J.  
         [0017]    First, referring to FIG. 2A, a substrate  200  is provided for the present embodiment. Then, an inter-metal dielectric (IMD) layer  210  is formed on the substrate. The inter-metal dielectric layer  210  is composed of single layer or multi-layer low k dielectric material, wherein the k is dielectric constant. Next, referring to FIG. 2B, the inter-metal dielectric layer  210  is etched by lithography to form the trenches  220 A and  220 B. In the present embodiment, the trenches  220 A and  220 B are formed by anisotropic etching, and the depths of the trenches  220 A and  220 B are between about 2000 to 6000 angstroms.  
         [0018]    Referring to FIG. 2C, a barrier layer  230  is formed on the sidewalls and the bottom of the trenches  220 A and  220 B. Then the metal layer  240  is disposed on the trench  220 A and  220 B on the barrier layer  230 . The metal layer  240  may be copper, aluminum, tungsten, or others. In this embodiment, the metal layer  240  is a copper layer.  
         [0019]    Referring to FIG. 2D, CMP is performed to remove the metal layer  240  and the barrier layer  230  from the inter-metal dielectric layer  210 . However, during CMP and after, the copper oxide (Cu 2 O) is generated on the remained metal layer  240  in the trenches  220 A and  220 B because of wetness. Moreover, the copper oxide (Cu 2 O) will cause the surface of the metal layer to bulge. Therefore, the adhesion between the sealing layer  260 , which is formed later, and the metal layer  240  is deteriorated. Hence, the reliability of the semiconductor is decreased.  
         [0020]    A reduction is performed to solve this problem. The reduction provides a reduction gas to the surface of the metal layer  240 . Therefore, the Cu 2 O is reduced to Cu by free radicals. In the present invention, the reduction gas may be ammonia (NH 3 ), hydrogen (H 2 ), or silane (SiH 4 ). Alternately, the reduction gas may be a mixture of ammonia (NH3) and hydrogen (H2), or a mixture of silane (SiH4) and hydrogen (H2). Preferably, the silane is used as the reduction gas. The reduction is under the following conditions: flow rate of the reduction is between about 20 to 400 sccm; the pressure of the reduction is between about 0.01 to 10 torr; and the temperature of the reduction is between about 180 to 620° C. Therefore, the metal oxide is removed and the surface of the metal layer is planarized.  
         [0021]    Afterwards, referring to FIG. 2E, an adhesion layer  260  is formed covering the metal layer  240  and the inter-metal dielectric layer  210  by plasma enhancement chemical vapor deposition (PECVD). The adhesion layer  260  may be silicon oxynitride (SiON), silicon containing oxygen, nitrogenand hydrogen (SiONH), silicon containing nitrogen and hydrogen (SiNH), silicon containing carbon and nitrogen (SiCN) or silicon containing carbon and hydrogen (SiCH), and the thickness of the adhesion layer  260  is between about 200 to 500 angstroms.  
         [0022]    Next, a sealing layer  270  is formed covering on the surface of the adhesion layer  260 . The sealing layer  270  may be silicon nitride (SiN) or silicon carbide (SiC), and the thickness of the sealing layer  270  is between about 200 to 850 angstroms.  
         [0023]    In the present invention, the reliability of the semiconductor device will be improved by providing the adhesion layer  260  and the sealing layer  270 , since the characteristics of the molecular structures of the sealing layer  270  and the adhesion layer  260  are different. As mentioned above, the adhesion layer  260  is silicon oxynitride (SiON), silicon containing oxygen, nitrogenand hydrogen (SiONH), silicon containing nitrogen and hydrogen (SiNH), silicon containing carbon and nitrogen (SICN) or silicon containing carbon and hydrogen (SiCH). Therefore, the molecular structures of the adhesion layer  260  containing such material have the necessary oxygen, hydrogen or nitrogen elements to combine with copper atoms. For this reason, a firmed structure such as Si—O—Cu forms at the interface between the adhesion layer  260  and the metal layer  240 . Therefore, the adhesion between the adhesion layer  260  and the metal layer  240  is improved. In addition, the chemical characteristic of the sealing layer  270  is very stable. While the sealing layer  270  is formed on the adhesion layer  260 , it is effective to avoid the copper ions diffusing to the inter-metal dielectric layer  280 , which is formed in the following steps, by providing the sealing layer  270 .  
         [0024]    Referring to FIG. 2F, an inter-metal dielectric layer  280  is formed on the conductive sealing layer  270 , wherein the inter-metal dielectric layer  280  is composed of single layer or multi-layer low k dielectric materials.  
         [0025]    Next, referring to the FIG. 2G, the IMD layer  280  is defined by the damascene to form a trench  290 B and a dual damascene structure  290 A extending through the IMD layer  280 , the adhesion layer  260  and the sealing layer  270  to the metal layer  240 .  
         [0026]    Then, referring to FIG. 2H, a barrier layer  300  is formed on the IMD layer  280  and the sidewalls and the bottom of the dual damascene structure  290 A and the trench  290 B by CVD or PVD. Afterwards, a metal layer  310  is formed on the dual damascene structure  290 A and the trench  290 B on the barrier layer  300 . The metal layer  310  may be copper, aluminum, or tungsten, etc. In this present embodiment, the metal layer  310  is a copper layer.  
         [0027]    Afterwards, referring to FIG. 2I, after the metal layer  310  is formed, CMP is performed to remove the metal layer  310  and the barrier layer  300  on the IMD layer  280 . As mentioned above, during CMP and after, copper oxide (Cu 2 O) is generated on the remaining metal layer  310 .  
         [0028]    Thus, a reduction is performed. The reduction provides a reduction gas to the surface of the metal layer  310 . Therefore, the Cu 2 O is reduced to Cu by free radicals. In the present invention, the reduction gas may be ammonia (NH 3 ), hydrogen (H 2 ), or silane (SiH 4 ). Alternately, the reduction gas may be a mixture of ammonia (NH3) or hydrogen (H 2 ), or a mixture of silane (SiH 4 ) and hydrogen (H 2 ). Preferably, the reduction gas is silane (SiH 4 ). The reduction is under the following conditions: flow rate of the reduction is between about 20 to 400 sccm; the pressure of the reduction is between about 0.01 to 10 torr; and the temperature of the reduction is between about 180 to 620° C.  
         [0029]    Afterwards, referring to FIG. 2J, an adhesion layer  320  is formed covering the metal layer  310  and the inter-metal dielectric layer  280  by plasma enhancement chemical vapor deposition (PECVD). The adhesion layer  320  may be silicon oxynitride (SiON), silicon containing oxygen, nitrogenand hydrogen (SiONH), silicon containing nitrogen and hydrogen (SiNH), silicon containing carbon and nitrogen (SiCN) or silicon containing carbon and hydrogen (SiCH), and the thickness of the adhesion layer  260  is between about 200 to 500 angstroms.  
         [0030]    Next, a sealing layer  330  is formed covering the surface of the adhesion layer  320 . The sealing layer  330  may be silicon nitride (SiN) or silicon carbide (SiC), and the thickness of the sealing layer  330  is between about 200 to 850 angstroms.  
         [0031]    In the present invention, the functions of the sealing layer  330  and the adhesion layer  320  are the same as those of the adhesion layer  260  and the sealing layer  270  to improve the reliability of the semiconductor device, since the characteristics of the molecular structures of the sealing layer  330  and the adhesion layer  320  are different. As mentioned above, the adhesion layer  320  is silicon oxynitride (SiON), silicon containing oxygen, nitrogenand hydrogen (SiONH), silicon containing nitrogen and hydrogen (SiNH), silicon containing carbon and nitrogen (SICN) or silicon containing carbon and hydrogen (SiCH). Therefore, the molecular structures of the adhesion layer  320  containing such material have the necessary oxygen, hydrogen or nitrogen elements to combine with copper atoms. For this reason, a firmed structure such as Si—O—Cu forms at the interface between the adhesion layer  320  and the metal layer  310 . Therefore, the adhesion between the adhesion layer  320  and the metal layer  310  is improved. In addition, the chemical characteristic of the sealing layer  330  is very stable. While the sealing layer  330  is formed on the adhesion layer  320 , it is effective to avoid the copper ions diffusing to other undesired place by providing the sealing layer  330 .  
         [0032]    According to the method of the present invention, an adhesion layer and a sealing layer are provided to satisfy both the requirements for adhesion between the metal layer and the adhesion layer and that for the metal ions to diffuse from the metal layer to the IMD layer. Therefore, the present invention reduces the electro-migration of copper and the improves adhesion between the sealing layer and the metal layer. Thus, the reliability of the semiconductor device is improved effectively.  
         [0033]    The foregoing description of the preferred embodiments of this invention has been presented for purposes of illustration and description. Obvious modifications or variations are possible in light of the above teaching. The embodiments were chosen and described to provide the best illustration of the principles of this invention and its practical application to thereby enable those skilled in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the present invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally, and equitably entitled.