Abstract:
This document discusses, among other things, apparatus having at least one CMOS transistor overlying a substrate; and at least one finned bipolar transistor overlying the substrate and methods for making the apparatus.

Description:
RELATED APPLICATION INFORMATION 
       [0001]    This application is a divisional application of U.S. patent application Ser. No. 11/837,972, filed on Aug. 13, 2007. U.S. patent application Ser. No. 11/837,972 is hereby incorporated by reference herein. 
     
    
     TECHNICAL FIELD 
       [0002]    The various embodiments described herein relate generally to transistor technology and more particularly to apparatus and method for making transistors. 
       BACKGROUND 
       [0003]    Bipolar transistors are widely used in semiconductor devices. In some electronic circuit applications it is desirable to utilize bipolar transistors and CMOS devices. 
         [0004]    Although it has been well known for a long time that reducing the size of electronic components is desirable, the practical means of doing so are not easily determined and do not yield predictable results. 
         [0005]    In the semiconductor field, the desire to continually reduce the size of semiconductor devices has not been a progression of minor steps aimed at reducing size of various aspects of a semiconductor but has required substantial changes in the basic structure as well as in the manner of making the structure. 
         [0006]    For a number of reasons that include reduction of semiconductor size, field effect transistors fabricated with CMOS technology have become standard for memory circuits where a large number of semiconductor devices are packed onto an integrated circuit chip. Use of CMOS technology has generally allowed a reduction of semiconductor device size from that achieved using bipolar transistor devices. 
         [0007]    There are a number of circuit applications where increasingly large drive currents at ever increasing frequencies are to be handled. In such applications the current handling capacity of bipolar transistors is desirable although their size is a drawback. Additionally, the bipolar transistors may not be the best solution to all of the operational constraints of a particular circuit. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]      FIG. 1  shows, in perspective, a bipolar transistor in accordance with at least one embodiment of the invention; 
           [0009]      FIG. 2A-2D  are sectional detail views of manufacturing intermediates of the bipolar transistor of  FIG. 1  at various stages in the manufacturing process, taken along section line  2 - 2 ′ of  FIG. 1 ; 
           [0010]      FIGS. 3A-3D  are sectional detail views of manufacturing intermediates of the bipolar transistor of  FIG. 1  at various stages in the manufacturing process, taken along section line  3 - 3 ′ of  FIG. 1 , manufactured using the process of  FIG. 5 ; 
           [0011]      FIGS. 4A and 4B  are sectional views of another embodiment of the manufacturing intermediate of the bipolar transistor that was illustrated in  FIGS. 2B and 3B , manufactured using the process of  FIG. 6 ; 
           [0012]      FIG. 5  is a flow diagram of embodiments of some of the process steps in the manufacture of finned bipolar and FinFET transistors on the same substrate; 
           [0013]      FIG. 6  is a flow diagram of embodiments of some of the process steps in the manufacture of finned bipolar and FinFET transistors on the same substrate; 
           [0014]      FIG. 7  is a flow diagram of embodiments of some of the process steps in the manufacture of finned bipolar and FinFET transistors on the same substrate; and 
           [0015]      FIGS. 8A-8B  and  9 A- 9 B are sectional views of another embodiment of the manufacturing intermediate of the bipolar transistor that was illustrated in  FIGS. 2B and 3B , manufactured using the process of  FIG. 7 . 
       
    
    
     DETAILED DESCRIPTION 
       [0016]    In order to obtain the favorable operating characteristics provided by bipolar transistors and CMOS devices, there are situations where the use of bipolar transistors and CMOS transistors is desired in a single circuit. For reasons which shall be more apparent in the discussion below, manufacturing integrated circuits with both bipolar devices and CMOS devices on the same chip requires solutions which are more than a simple combining of manufacturing steps used in the manufacture of CMOS and bipolar transistors. 
         [0017]    Bipolar transistors in BiCMOS circuits are generally formed as vertical bipolar transistors. Reduction of the size of such devices is often achieved by vertical scaling with steep and narrow base doping profiles. Some integrated BiCMOS structures have used SiGe-bipolar transistors. Improvements of device speed in such devices is achieved by reduction of base width. But planar integration in such devices is often achieved at the cost of greatly reduced performance levels because the semiconductor feature sizes available have been too large using vertical bipolar transistors and planar CMOS integration. 
         [0018]    The manufacturing processes for bipolar transistors and CMOS devices are fundamentally different. For that reason, realization of circuits having both bipolar and CMOS devices using the exercise of ordinary skill could be addressed by forming the bipolar and CMOS devices on separate chips. But the difficulties in interconnecting such hybrid circuits lead to reduced performance levels because of the physical sizes of the devices and the circuitry for interconnecting them. 
         [0019]    In order to deal with these difficulties, various bipolar and CMOS technology solutions have been proposed. To date, attempts at providing BiCMOS circuits on a single chip have been very complex, at least in part, because of the unpredictability of the manufacturing process steps if BiCMOS and bipolar manufacturing operations are combined. Those integration efforts have generally been aimed at forming the bipolar devices as vertically-stacked regions typical of most bipolar devices. 
         [0020]    As processes evolved to make CMOS devices increasingly smaller, the size constraints of such scaling efforts exceeded what could be accomplished using conventional photolithography techniques. To address this need, FinFET devices were conceived to allow manufacture of CMOS devices several orders of magnitude smaller than could be achieved using planar CMOS device manufacturing processes. 
         [0021]    Forming hybrid circuits on single wafer substrates including both FinFET CMOS devices and finned bipolar transistors is possible using modifications of fin forming techniques previously used to form FinFET devices. Embodiments of the present subject matter allow both FinFET and finned bipolar devices to be formed on a single chip substrate. Using embodiments of our modified manufacturing processes, both FinFET and finned bipolar transistors of exceedingly small size can be produced in hybrid integrated circuits formed on a single chip. 
         [0022]    In  FIG. 1 , a perspective view is shown of some embodiments of a finned bipolar transistor  100  of a hybrid integrated circuit, which in some embodiments, may combine at least one bipolar transistor and at least one finFET CMOS transistor. In some other embodiments, the circuit may comprise at least one finned bipolar transistor with no CMOS devices. In some embodiments, the finned bipolar transistor  100  may be part of a memory-element-select device for a phase-change memory module since such a device allows operation of small memory cell elements with a useful switching current. Phase-change materials may be programmed between a first structural state where the material is generally more amorphous (less ordered) and a second structural state where the material is generally more crystalline (more ordered). The less ordered state generally has a higher resistivity that the more ordered state. Examples of phase-change materials include chalcogenide materials comprising at least one chalcogen element. An example of a chalcogenide phase-change material is Ge 2 Sb 2 Te 5 . 
         [0023]    In some other embodiments, a junction of the finned bipolar transistor may connected as a band-gap voltage reference for use in a CMOS circuit. 
         [0024]    In accordance with some embodiments, at least one finned bipolar transistor  100  overlies and is supported by a buried oxide layer  120  of a silicon wafer substrate  110 . Buried oxide layer  120  is above and supported by remaining silicon layers  121 . The fin structure  126  of bipolar transistor  100  is quite similar to that of the fin of a FinFET CMOS device. Rather than having source/drain regions, fin  126  has collector/emitter regions  122  and  124  positioned adjacent its opposite ends. Fin  126  overlies and is supported by the surface of buried oxide layer  120  of the wafer substrate  110 . 
         [0025]    In finned bipolar transistor  100 , the collector and emitter regions  122  and  124  are located on the fin  126  and are generally analogous to source/drain regions for FinFETs although their doping levels are different, as discussed below. Collector and emitter regions  122  and  124  are appropriately doped regions of fin  126 , with the doping ions and concentrations determined in part by whether the bipolar transistor  100  is to be constructed in an npn or configuration or whether it is to have a pnp configuration. The discussion herein is of npn bipolar transistors and NMOS FinFETs. PMOS FinFETs and pnp bipolar transistors are achieved in a corresponding manner. 
         [0026]    A base region  128  is located between the collector and emitter regions  122  and  124  of fin structure  126 . Base region  128  is not fully visible in  FIG. 1 , but it can be seen in the more detailed view in  FIG. 2D . Because base region  128  is in conductive contact with fin  126 , it is distinguishable from the gate of a FinFET which is electrically insulated from its fin and its conductive channel. 
         [0027]    As shown in  FIG. 1 , a contact line  130  overlies the surface of the substrate  110  and is in electrical conductive contact with the base region  128  of fin  126 . Contact line  130  is a conductive line that, in some embodiments, is formed of polysilicon. In some embodiments, contact line  130  is metallic or is a metal. In an embodiment, the material is selected from a group of conductors consisting of polysilicon, gold, copper, and aluminum and alloys thereof. 
         [0028]    Also shown in  FIG. 1  are collector and emitter contact landing pads  132  and  134  that are adjacent to and in electrical contact with the respective collector and emitter regions  122  and  124  of fin structure  126 . Landing areas  132  and  134  are used to connect the electrodes of transistor  100  to other areas of integrated circuit  100  using vias and metallization layers in a BEOL (back end of line) connection process. The vias and metallization layers are not shown in  FIG. 1 . 
         [0029]    In  FIG. 1 , bipolar transistor  100  is not drawn to scale and the relative sizes of its various parts are not necessarily in the same relative size relationships that are depicted. In some embodiments, the width of the fin  126  is about 20 nm and its height is about 60-80 nm. 
         [0030]    In some embodiments, multiple finned transistors  100  are formed on the same substrate  110 . In some embodiments, the finned bipolar transistors  100  are contemporaneously formed on the same substrate  110  as at least one FinFET transistor.  FIGS. 2A-2D  and  3 A- 3 D are cross-sectional detail views of several manufacturing intermediate embodiments in the manufacture of finned bipolar transistor  100  of  FIG. 1 .  FIGS. 4A and 4B  are views of an alternative manufacturing intermediate embodiment of  FIGS. 2B and 3B  respectively. Those views are taken along the longitudinal axis of fin  126  and along the longitudinal axis of contact line  130  respectively.  FIGS. 2A-2D  and  3 A- 3 D also illustrate some aspects of some process actions carried out in the course of the manufacturing process shown in the process flow diagram of  FIG. 5 . 
         [0031]    As shown in  FIGS. 2A and 3A , the structure of a single finned transistor  100  is shown at an intermediate point  520  in the manufacturing process of  FIG. 5 , after formation of the fin  126  and formation of the base stack that will later become the base region of fin  126 . 
         [0032]      FIG. 5  is a process flow diagram for some embodiments of a manufacturing process for the manufacture of finned bipolar transistors. In some embodiments, the process for manufacturing bipolar transistors produces bipolar transistors contemporaneously with FinFET transistors. For each process operation in  FIG. 5 , a description is provided in separate columns of what that process operation provides for the finned bipolar (FinBIP) transistor and the FinFET CMOS transistor. 
         [0033]    In some embodiments, the manufacturing process begins at block  501  with providing a wafer  110  which includes a prepared wafer surface which has a silicon region overlying a buried oxide layer  120  which is supported by a silicon substrate  120 . The wafer surface silicon region is lightly doped in a planar collector implant operation  502 , as shown in  FIG. 5 , to form planar collector implant regions of the wafer surface where the fins  126  of the bipolar transistors  100  will be formed in subsequent operations. 
         [0034]    The collector implant doping process  502  will result in a lightly-doped collector region  122  in the fin structure  126  of finished bipolar transistor  100 . If both bipolar and CMOS devices are being contemporaneously formed on the same wafer  120 , the same implantation operation  502  which provides the lightly doped collector  122  for the bipolar device may also be used, in some embodiments, to provide well doping in the CMOS FinFET devices being contemporaneously formed on the same substrate. 
         [0035]    Fins  126  for both finned bipolar transistors  100  and for FinFETs are produced by a photolithography and selective etching process  503 . In some embodiments, process  503  commences with the deposition of a hardmask material which is resistant to aggressive etch chemistries such as plasma etching. In further action  503 , a series of lithography processes to form fin structure  126  are performed using fin forming operations corresponding to those that are followed for manufacturing FinFET devices. The lithography processes include selectively etching, in block  503 , the wafer surface to form an elongated fin  126  with a collector region  122  including a portion of the collector implant previously formed. 
         [0036]    The same hardmask and photolithography processes  503  used to form the bipolar fins  126  can be performed on the areas of the chip where FinFET devices are to be formed to provide a FinFET fin. Thus the fin structures  126  for finned bipolar devices and those for contemporaneously formed FinFETS use the same process  503  that is utilized for forming fins in FinFET devices. 
         [0037]    In a further operation  505  through  507 , in some embodiments, a sacrificial dielectric layer  136  is applied to provide an etchstop during a later etching operation  507 . Base and gate lithography  506  and anisotropic etching processes  507  are contemporaneously performed next on the bipolar finned transistor and FinFETs. These operations form a polysilicon sacrificial base deposit  138  between a pair of oxide sidewall spacers  140 . Sacrificial base deposit  138  will later be replaced by base electrode material in a further operation  521 . The operations that form the bipolar transistor base region also contemporaneously form a gate electrode in FinFETs formed on the same substrate. Sidewall oxide spacers  140  provide spacing between the emitter/collector regions  122  and  124  and the base region  128 . 
         [0038]    Bipolar transistor base region  128 , analogous to the gate of a FinFET structure, is formed intermediate the ends of the fin  126 . The results of the base forming operations contemporaneously carried out to form base region  128  for the finned bipolar transistor  100  are shown in  FIG. 2A . Gate regions for FinFET transistors formed on the same substrate  110 . 
         [0039]    In some embodiments, extension implants are formed for the FinFET transistors in a further process operation  509 . Extension implant regions are not added to the bipolar finned transistors. Nitride spacers  142  are then formed in operation  510  and lithography operations  511  and implant operations  512  are performed to form the bipolar emitter and collector areas  122  and  124 . In  FIG. 2B , doping  242  is applied in operation  512 , as shown in the process flow diagram of  FIG. 5 , for forming an emitter region  124  between the base region and an end of the fin  126 . In some embodiments, the same doping is applied for forming a collector region  122  between the base region and the other end of the fin. 
         [0040]    To achieve a doping gradient for the base collector junction, the collector region  126  is more heavily doped than a lightly doped collector region  123  and other doped regions. In some embodiments, a resist mask  144  was applied to the surface above the emitter region  124 , as shown in  FIG. 2B . The mask  144  blocks a portion of the doping implant to reduce the dose received below the resist mask  144 . The FinFET source and drain regions are formed in a contemporaneous operation performed on FinFET transistors on the same substrate. 
         [0041]    The arrows  242  in  FIG. 2B  signify the application of doping operations  516  to form emitter and collector regions. The arrows  242  also show that in some embodiments, the doping operations are carried out with the doping applied substantially perpendicular to the surface of substrate  110 . 
         [0042]      FIG. 4  is a view of an embodiment of a manufacturing intermediate of a FinBIP formed using an alternative doping process to the one shown and discussed relative to  FIG. 2B .  FIG. 6  is a step-by-step outline of further embodiments of the manufacturing process as it applies to the formation of the bipolar and FinFET transistors shown in  FIG. 4 . Specifically, the process embodiments of  FIG. 6  are similar to those shown in  FIG. 5 . In operations  611  and  612  the resist mask of operations  511  and  512  is not used. Instead, the implant beam is tilted away from the vertical so that the lightly doped collector area falls into the shadow of the sacrificial “gate structure” formed at operations  604  through  607 . The shadow prevents the full implant from being delivered to the lightly doped collector area and allows creation of a base-collector doping gradient which will be fine tuned in operation  616  when the tilted base implant is delivered. 
         [0043]    In  FIG. 4 , the doping  442  is applied in the operation at  612  of  FIG. 6 , at an angle the perpendicular across the entire region where the finned transistor is being formed. In this alternative embodiment, no resist mask is needed to create a doping distribution. Because base implant material  138  and sidewalls  140  extend upwardly from the fin  126 , the base implant stack shields the fin  126  adjacent the base region to provide the desired doping gradient to form a lightly doped collector region  123  of collector  122  adjacent the base implant. 
         [0044]    Following the injection of the collector and emitter doping following a process  512  or  612  as illustrated in either  FIG. 2B  or  FIG. 4 , a layer of BSG  246  is formed and then treated by a CMP operation  513  to complete the formation of the manufacturing intermediate structure illustrated in  FIG. 2B . In some embodiments, the upper surface of the BSG layer  246  is flush with the base sacrificial region  138  and serves as an etch block to allow a selective etching in operation  514  of just the sacrificial material  138  in the “gate stack” region that will become base region  128  of the bipolar transistor and the gate of the FinFET. 
         [0045]    In the base etching operation  514 , the base region  128  is etched down to the oxide layer  136  on fin  126  and to the spacer regions  140  lining the base region cavity. Following this etching, the width of the base region to be formed is adjusted in operation  515  by depositing inner spacers  142  in the bipolar base region  128 . The spacer material contemporaneously formed in the FinFET gate regions are removed again from the FinFET devices. 
         [0046]    In  FIG. 2C , arrows  248  are shown to signify the tilted base implant doping operation  516 . The base implant doping is applied at an angle to the perpendicular to reduce the doping load in the lightly doped collector region  123  to fine tune the desired base-collector doping level gradient. 
         [0047]    In process block  518  the sacrificial dielectric layer is etched away. A gate dielectric deposition process  518  The gate dielectric is needed to provide an insulated gate in CMOS transistors and is also contemporaneously and temporarily applied to the bipolar transistor. It is removed from the finned bipolar transistor  100  after a lithographic process is applied to expose the base areas of the bipolar transistors, as well as the collector and emitter electrodes, while the gate regions of the CMOS remain protected from that etching process by a patterned etch blocking layer. 
         [0048]    After the lithography and etch processes  519  and  520  for removal of the dielectric oxide layer  138  in the base region of the bipolar transistors, a deposition process  521  is performed to deposit a base electrode conductor  250  formed of polysilicon or other metals as illustrated in  FIG. 2D . That region is directly connected to the base region of the fin. In the contemporaneously formed FinFETs similarly formed regions to provide an insulated gate electrode for the FinFET transistors. 
         [0049]    In a further operation  522 , CMP planarization is then performed to make a smooth surface for the wafer with the implanted base electrode region and the emitter and collector region exposed for connection in a suitable back-end-of-line (BEOL) interconnection process  523 , to connect the transistor electrodes to the conductive interconnection layers (not shown). 
         [0050]      FIG. 7  is a step-by step outline of further embodiments of the manufacturing process as it as it applies to the formation of the bipolar and FinFET transistors. In this process the BiCMOS structure is formed without forming and replacing a sacrificial gate structure as was illustrated in the processes shown in  FIGS. 5 and 6  and discussed above. The intermediate structures created as the process of  FIG. 7  are carried out are illustrated in  FIGS. 8A and 8B  and  FIGS. 9A and 9B . 
         [0051]    The process in  FIG. 7  commences at  701  with preparation of the wafer surface. In the process at block  702  a base implant doping is applied in the area of the wafer where the bipolar transistor base will be formed. In that same operation  702 , well doping for contemporaneously formed FinFET CMOS devices may also be implanted 
         [0052]    In operation  703  fins  826  for the bipolar and FinFET transistors are contemporaneously formed by etching and lithography operations analogous to those of blocks  503  and  603  of  FIGS. 5 and 6 . A conductive layer of a material such as CoSi is applied to the fin  826  in the bipolar region in operation  704  to serve as an etchstop for the etching process to be carried out in block  707 . In the FinFet device regions, the conducting layer needs to be removed in CMOS areas. If the CoSi material is used for the deposited conducting layer, silicidation is avoided in CMOS areas by suitable masking, for example. 
         [0053]    In operations  705 - 707  a gate stack and hardmask is applied to the bipolar and finFET devices, gate lithography is performed to define a base electrode  828  for the bipolar devices and to define gates for the FinFETs and in etching step  707 , the base and gate electrodes are etched to the conductive layer. The conductive layer is removed in operation  708 . 
         [0054]    In the operations at block  709  and  710 , sidewall  840  and oxide spacers are formed to space the emitter/collector  832  and  834  and base regions  828  of the bipolar transistors and extensions for the FETs. 
         [0055]    In operations  711  and  712  collector implants are formed. In operation  711 , the doping implant  811 , shown in  FIG. 8B , is oriented substantially vertical to the surface of the wafer to apply light collector doping. This implant  811  makes only a negligible contribution to the S/D/doping of the FinFET. In some embodiments, in block  712   a , a tilted implant operation  812  is performed with the lightly doped collector region shadowed from application of the implant. In some other embodiments, in block  712   b , a resist mask, not shown in  FIG. 8B , is used to protect the lightly doped collector area from a vertical implant which is also applied to the S/D regions of the FinFET CMOS. 
         [0056]    The accompanying drawings that form a part hereof show by way of illustration, and not of limitation, specific embodiments in which the subject matter may be practiced. The embodiments illustrated are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed herein. Other embodiments may be utilized and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of this disclosure. This Detailed Description, therefore, is not to be taken in a limiting sense, and the scope of various embodiments is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled. 
         [0057]    Although specific embodiments have been illustrated and described herein, it should be appreciated that any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. This disclosure is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the above description. 
         [0058]    The Abstract of the Disclosure is provided to comply with 37 C.F.R. §1.72(b), requiring an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.