Abstract:
A method and apparatus for digital-to-analog conversion utilizing randomized dynamic element matching for the attenuation of harmonic distortion during the conversion process due to non-ideal circuit behavior is presented. The present invention introduces a new DEM approach that results in a simplified DAC architecture relative to previous DACs, while preserving optimal spurious-free dynamic range (SFDR). The particular topology utilized involves the use of a bank of DAC-elements, preferably 1-bit DAC elements, the outputs of which are summed to yield a single multiple-level DAC. During each conversion cycle, random selection is used to determine the addresses of the DAC-elements used in order to “scramble” the DAC noise arising from each individual 1-bit DAC.

Description:
TECHNICAL FIELD 
     The present invention is related to the field of solid-state electronic circuits, and more particularly to the field of digital-to-analog converters employing randomized dynamic element matching techniques. 
     BACKGROUND OF THE INVENTION 
     Digital-to-analog converters (DACs) operate to convert signals representing values in the digital domain to the same values represented in the analog domain, and are therefore ideally linear devices. However, the non-ideal circuit behavior of practical DACs introduces non-linearities that cause harmonic distortion and limit the achievable spurious-free dynamic range (SFDR). 
     The continued growth in wireless technology has spawned an increased demand for large-scale integration digital-to-analog conversion techniques. For example, a technique frequently used in wireless communication products is direct digital synthesis (DDS). In DDS, analog signals, such as carrier tones, are synthesized using mostly digital circuitry. The front-end digital-to-analog converter (DAC) used to convert the input digital signal into an analog waveform limits the efficiency in many DDS systems. In particular, the production of harmonic distortion during the conversion places an upper boundary on the SFDR of the entire system. 
     In order to attenuate or eliminate harmonic distortion resulting from non-ideal circuit behavior in various multi-bit DACs, dynamic element matching (DEM) techniques have been successfully applied. Rather than using special fabrication processes or laser trimmed components to improve performance, non-ideal circuit behavior is accepted as inevitable, and signal-processing techniques are applied to mitigate the negative effects on DAC linearity. 
     An example of a popular multi-bit DAC architecture involves the use of a plurality of nominally identical current sources whose outputs are summed to yield a composite DAC. During monolithic integration of high-accuracy current sources for volume production of solid-state circuits, however, the problem arises that, due to current source manufacturing variations, individual current sources vary in the current they deliver. These current source manufacturing variations can largely be compensated for by the use of a current divider and by switching the currents of a plurality of current sources to three current paths in a “rotating” manner by means of a cyclic shift register, with the first and second current paths being fed half the current of the third path. By cascading a plurality of such current dividers, a high-accuracy monolithic integrated DAC can be implemented. The binary signal is caused to “rotate” by means of a cyclic shift register, and the “rotating” signal drives a set of switches to turn the individual current sources on or off In order to utilize this “rotation” method, the frequency of the shift signal for the shift register must be at least (2 n −1) times higher than the frequency of the sampling signal at whose pulse repetition rate the binary signals occur. However, use of such a shift signal is not always feasible, e.g. an oscillator operational at a correspondingly stable frequency is too expensive for a specific application. In addition, the frequency of the shift signal often lies in ranges that necessitate particularly careful design of, and specific manufacturing processes for, the integrated circuit. 
     Another approach applied in monolithic integration involves the input signal being applied to a conventional DAC, and first. processed so that its value is uncorrelated with that of the unprocessed input signal. Adding a digital random number to the input digital signal can effect this processing. The digital random number is then converted into analog form by a second DAC. An analog subtraction circuit then subtracts the analog version of the processed sum. The difference is the analog counterpart to the original digital input signal. 
     The present invention proposes the use of a new DEM technique suitable for applications requiring low-distortion DACs, such as DDS. It is demonstrated that harmonic distortion is eliminated, i.e., the DAC noise is white, and thus an optimal SFDR is achieved. These results are achieved by utilizing a topology that incorporates a bank of, preferably 1-bit, DACs, the outputs of which are summed together to yield a single multi-bit DAC. The DAC noise arising from mismatches between the individual 1-bit DACs is “scrambled” by randomly selecting one of the appropriate codes for each digital input value. A digital encoder is exploited to carry out the scrambling process, the ultimate effect being modulation of the DAC noise without modulation of the signal component of the DAC output. 
     SUMMARY OF THE PRESENT INVENTION 
     A digital-to-analog converter used in converting digital input signals to analog output signals using a bank of, preferably 1-bit, DACs, or “unit DAC elements” (UDEs) as follows. A multi-bit digital signal is received by an encoder, which translates the received signal into multiple one-bit binary signals. Each binary signal is received by a UDE that converts the binary signal to analog. The encoder implements a randomization algorithm that identifies the UDEs to be selected during each conversion cycle. The UDE analog output paths are connected through a summing node to generate the final analog output corresponding to the original digital input signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 demonstrates the topology of an N-level version of the proposed digital-to-analog converter (DAC); 
     FIG. 2 demonstrates the topology of an 8-level, 3-bit version of the proposed digital-to-analog converter (DAC); 
     FIG. 3 provides a demonstration of the simulated power spectral density (PSD) relative to N 2  of a particular signal of the digital-to-analog converter (DAC) operating with a 3-bit dithered sinusoidal input, wherein: 
     FIG.  3 ( a ) provides the output y[n] of an ideal digital-to-analog converter (DAC) with no static mismatch errors; 
     FIG.  3 ( b ) provides the output y[n] of a non-ideal digital-to-analog converter (DAC) without dynamic element matching; 
     FIG.  3 ( c ) provides the difference between the input and output signals y[n]−x[n] of a non-ideal digital-to-analog converter (DAC) without dynamic element matching; 
     FIG.  3 ( d ) provides the output y[n] of a non-ideal digital-to-analog converter (DAC) using the dynamic element matching provided by the present invention; 
     FIG.  3 ( e ) provides the difference between the input and output signals y[n]−x[n] of a non-ideal digital-to-analog converter (DAC) using the dynamic element matching provided by the present invention; and 
     FIG.  3 ( f ) demonstrates the noise of the digital-to-analog converter using the dynamic element matching provided by the present invention. 
    
    
     DETAILED DESCRIPTION 
     The present invention relates to a digital-to-analog conversion method employing randomized element shuffling and apparatus incorporating it therein, and may be tailored to a variety of applications. The following description is presented to enable one of ordinary skill in the art to make and use the invention and to incorporate it in the context of particular applications. Various modifications, as well as a variety of uses indifferent applications will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to a wide range of embodiments. Thus, the present invention is not intended to be limited to the embodiments presented, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. 
     An example of a generic N-level DAC topology of the present invention is shown in FIG. 1, wherein a N-level digital input signal x[n] is provided. The particular nature of the N-level digital input signal x[n] may vary from application to application and may, for example, represent an audio signal. The N-level digital input signal x[n]  100  is applied to an encoder  102 , preferably a stochastic barrel shifting encoder (SBSE). The encoder  102  coverts the N-level digital input signal x[n]  100  into N−2 one-base unit codes  104  (e.g. bits in the case of binary codes) that are fed into the N−2 DACs. FIG. 1 specifically demonstrates the case of a binary N-level digital input signal x[n]  100 , where the DAC elements are preferably Unit DAC elements (UDEs)  106 . Although the binary case is shown in FIG. 1, it is important to note that other digital-to-analog converter types may be used depending on the numerical base of the input signal. The fragmented analog signal output  108  is processed into an analog output summing node  110 , resulting in the final analog output  112 . 
     The N-level digital input signal x[n]  100 , is in the form of a sequence of unsigned integers such that x[n]&lt;N. As shown in FIG. 1 by the lines emerging from the encoder  102 , each input sample is mapped onto N−2 output bits, x 0 [n] . . . x N−2 [n]  104 , such that            ∑     i   =   0       N   -   2                         x   i          [   n   ]         =       x        [   n   ]       ·                            
     Each UDE  106  operates according to            y   r          [   n   ]       =     [             1   +     e     h   r         ,                 x   r          [   n   ]       =   1     ;               e     l   r                   x   r          [   n   ]       =   0     ;                                    
     where y r [n] denotes the analog output of the r th  UDE  106 , and e h     r    and e l     r    are errors in the analog output levels. The errors are assumed to be time-invariant, but otherwise arbitrary, and are referred to as static mismatch errors. The r th  UDE  106  is selected whenever x r [n]=1. 
     With non-zero static mismatch errors, the output y[n] of the multi-bit DAC can be written in the form: 
     
       
         
           y[n]=αx[n]+β+e[n], 
         
       
     
     where α is a constant gain, β is a DC offset, and e[n] is zero-mean DAC noise. The purpose of the encoder  102  is to dynamically select the UDEs  106  such that e[n] is white and uncorrelated with the input. To accomplish this purpose, the present invention utilizes a method that processes a random offset integer, provided by a random number generator, to select the appropriate UDEs  106  during each conversion cycle. For purposes of FIG. 1, the random number generator is assumed to be contained within the encoder  102 , though depending on the specific embodiment this may or may not be the case. The encoder  102  associates the x[n] elements  104  with UDEs  106  (which may take the more general form of digital-to-analog converter elements (DACE)) as follows, 
     
       
           UDE   o[n]   , UDE   (o[n]+1)%(N−1)   , . . . , UDE   (o[n]+x[n]−1)%(N−1) , 
       
     
     where % denotes the “modulo” operator and o[n] is a random integer offset from the set {0, 1, . . . , N−2}. It is important that possible values of o[n] are equi-probable, i.e.,          P        {       o        [   n   ]       =   i     }       =     1     N   -   2                              
     for all i, and the value of o[n] is statistically independent, or approximately statistically independent, of previous values. As shown in FIG. 1, the number of UDEs  106  utilized for a particular input signal x[n]  100  of N-levels is N−1, addressed {0, 1, . . . , N−2}. A series of UDEs  106 , beginning with an address {0, 1, . . . , N−2} are used to perform the digital-to-analog conversion. Because the UDEs  106  are non-ideal, each generates a particular output error pattern. Randomizing the sequence of UDEs  106  by randomly selecting the address of the first UDE  106  causes the particular output error pattern of each individual UDE  106  to be averaged with the particular output error pattern of the other individual UDEs  106  in order to produce a random, white noise error pattern rather than an error pattern of spurs as results from the individual UDEs  106 . 
     The block diagram in FIG. 2 demonstrates the use of the randomized dynamic element matching technique of the present invention for an 8-level DAC embodiment, i.e., x[n]ε {0, 1, . . . , 7}. Thus, a total of the number of UDEs necessary is N−1=7, addressed {0, 1, . . . , 6}. 
     The simulated performance of the example DAC is presented in graphical form in FIG.  3 . Each portion of the figure shows the simulated power spectral density (PSD) relative to N 2  of a particular signal of the DAC operating with a 3-bit, 8-level dithered sinusoidal input. More specifically, FIG.  3 ( a ) provides the output y[n] of an ideal digital-to-analog converter (DAC) with no static mismatch errors. FIG.  3 ( b ) provides the output y[n] of a non-ideal digital-to-analog converter (DAC) without dynamic element matching. FIG.  3 ( c ) provides the difference between the input and output signals y[n]−x[n] of a non-ideal digital-to-analog converter (DAC) without dynamic element matching. FIG.  3 ( d ) provides the output y[n] of a non-ideal digital-to-analog converter (DAC) using the dynamic element matching provided by the present invention. FIG.  3 ( e ) provides the difference between the input and output signals y[n]-x[n] of a non-ideal digital-to-analog converter (DAC) using the dynamic element matching provided by the present invention. More specifically, FIG.  3 ( e ) shows the signal. 
     
       
         
           e[n]=y[n]−αx[n]−β, 
         
       
     
     where        α   =     1   +       1   N            ∑     i   =   0       N   -   1                         (       e     h   i       -     e     l   i         )                   and                   β   =       ∑     i   =   0       N   -   1                       e     l   i                                
     FIG.  3 ( f ) demonstrates the noise of the digital-to-analog converter using the dynamic element matching provided by the present invention. 
     In these simulations, the static mismatch errors were chosen within +/−5% of the nominal LSB value of the DAC. Rather severe harmonic distortion results from the static mismatch errors in the absence of DEM, as evidenced by the numerous spurs distributed across the spectrum of FIGS.  3 ( b ) and  3 ( c ), resulting in a SFDR of less than 40 dB. This harmonic distortion is largely eliminated by the present invention, as evidenced by the data of FIGS.  3 ( d ),  3 ( e ), and  3 ( f ). With regard to the simulation of FIG. 3, the PSDs were each estimated by averaging 32 length 2 17  periodograms. The input was generated by adding dither to a high-resolution sinusoid, and quantizing to a 3-bit value. The dither was a white noise sequence with a triangular probability density function supported on (−1, 1), so that the quantization error was modeled as white noise. It is important to note that the white noise of the DAC does not depend on the statistical properties of the input, and that a dithered sinusoid was used as a non-limiting example only.