Abstract:
An accurate and simple benchmarking method for multiple processor systems. Instead of a central timer as used in the prior art, a counter is implemented in each processor that counts the processor&#39;s clock cycles. The counter may be read after the processor&#39;s completes a benchmark task. This eliminates the timing skew common in the prior art.

Description:
CLAIM TO PRIORITY OF PROVISIONAL APPLICATION 
       [0001]    This application claims priority under 35 U.S.C. 119(e) (1) to U.S. Provisional Application No. 60/60/941,357 filed Jun. 1, 2007. 
     
    
     TECHNICAL FIELD OF THE INVENTION 
       [0002]    The technical field of this invention is performance benchmarking of multiprocessor video codec&#39;s employed in image transmission systems such as video conferencing and in video compression. 
       BACKGROUND OF THE INVENTION 
       [0003]    Image data compression often employs a spatial to frequency transform of blocks of image data known as macroblocks. A Discrete Cosine Transform (DCT) is typically used for this spatial to frequency transform. Most images have more information in the low frequency bands than in the high frequency bands. It is typical to arrange and encode such data in frequency order from low frequency to high frequency. Generally such an arrangement of data will produce a highest frequency with significant data that is lower than the highest possible encoded frequency. This permits the data for frequencies higher than the highest frequency with significant data to be coded via an end-of-block code. Such an end-of-block code implies all remaining higher frequency data is insignificant. This technique saves coding the bits that might have been devoted to the higher frequency data. 
         [0004]    Video encoding standards typically permit two types of motion vector predictions. In inter-frame prediction, data is compared with data from the corresponding location of another frame. In intra-frame prediction, data is compared with data from another location in the same frame. 
         [0005]    As coding algorithms increase in complexity paired with the increase in screen resolution, multiple processing elements may be employed. These may be a combination of one or more digital signal processors, a general purpose processor and dedicated hardware processing blocks designed to implement specific algorithms. To optimize system performance, it is necessary to accurately benchmark the individual processing elements. 
         [0006]    One approach to benchmark the performance of these devices is to implement a chip timer in each processor. The timers generate individual interrupts that are read by one of the processors to determine processing time. The following problems exist with this approach: 
         [0007]    a) The timer must be read right before enabling each of the processors, and then individual enables have to be written to the processors to be started. Since this is a serial process, errors will be introduced. 
         [0008]    b) Multiple processors may complete their tasks at different times, but very close to each other. If two processors complete at the same time then the processor which is responding to the interrupts responds to them one at a time and so until it finishes servicing the first interrupt it cannot read the timer and find out when the second CPU has finished. This results in skewing the interrupt, precludes the accurate measurement of completion times. 
         [0009]    c) The approach of using interrupt service routines to measure execution times of individual processors is not scaleable, as the more processors we add the more we are likely to see the skew in measuring results. Further since these specialized processors have limited memory, they send interrupts once per macroblock or once per two macroblocks. The interrupt rate at high definition video resolutions results in a high interrupt rate of 121,500 interrupts per second, resulting in an excessive processor overhead. 
       SUMMARY OF THE INVENTION 
       [0010]    Instead of implementing a timer to measure processor throughput, this invention implements a benchmark counter in each processor. Since all processing elements run synchronous to corresponding clocks, measuring co-processor performance really amounts to just counting the number of clock ticks consumed by the processor. A start command resets the benchmark counter, which then starts incrementing with every subsequent clock tick. The benchmark counter stops incrementing when it sees an end command. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0011]    These and other aspects of this invention are illustrated in the drawings, in which: 
           [0012]      FIG. 1  illustrates the organization of a typical digital signal processor to which this invention is applicable (prior art); 
           [0013]      FIG. 2  illustrates details of a very long instruction word digital signal processor core suitable for use in  FIG. 1  (prior art); 
           [0014]      FIG. 3  illustrates the pipeline stages of the very long instruction word digital signal processor core illustrated in  FIG. 2  (prior art); 
           [0015]      FIG. 4  illustrates the instruction syntax of the very long instruction word digital signal processor core illustrated in  FIG. 2  (prior art); 
           [0016]      FIG. 5  illustrates an overview of the video encoding process (prior art); 
           [0017]      FIG. 6  illustrates an overview of the video decoding process (prior art); and 
           [0018]      FIG. 7  illustrates the process of this invention in benchmark mode. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0019]      FIG. 1  illustrates the organization of a typical digital signal processor system  100  to which this invention is applicable. Digital signal processor system  100  includes central processing unit core  110 . Central processing unit core  110  includes the data processing portion of digital signal processor system  100 . Central processing unit core  110  could be constructed as known in the art and would typically includes a register file, an integer arithmetic logic unit, an integer multiplier and program flow control units. An example of an appropriate central processing unit core is described below in conjunction with  FIGS. 2 to 4 . 
         [0020]    Digital signal processor system  100  includes a number of cache memories.  FIG. 1  illustrates a pair of first level caches. Level one instruction cache (L 1 I)  121  stores instructions used by central processing unit core  110 . Central processing unit core  110  first attempts to access any instruction from level one instruction cache  121 . Level one data cache (L 1 D)  123  stores data used by central processing unit core  110 . Central processing unit core  110  first attempts to access any required data from level one data cache  123 . The two level one caches are backed by a level two unified cache (L 2 )  130 . In the event of a cache miss to level one instruction cache  121  or to level one data cache  123 , the requested instruction or data is sought from level two unified cache  130 . If the requested instruction or data is stored in level two unified cache  130 , then it is supplied to the requesting level one cache for supply to central processing unit core  110 . As is known in the art, the requested instruction or data may be simultaneously supplied to both the requesting cache and central processing unit core  110  to speed use. 
         [0021]    Level two unified cache  130  is further coupled to higher level memory systems. Digital signal processor system  100  may be a part of a multiprocessor system. The other processors of the multiprocessor system are coupled to level two unified cache  130  via a transfer request bus  141  and a data transfer bus  143 . A direct memory access unit  150  provides the connection of digital signal processor system  100  to external memory  161  and external peripherals  169 . 
         [0022]      FIG. 2  is a block diagram illustrating details of a digital signal processor integrated circuit  200  suitable but not essential for use in this invention. The digital signal processor integrated circuit  200  includes central processing unit  1 , which is a 32-bit eight-way VLIW pipelined processor. Central processing unit  1  is coupled to level  1  instruction cache  121  included in digital signal processor integrated circuit  200 . Digital signal processor integrated circuit  200  also includes level one data cache  123 . Digital signal processor integrated circuit  200  also includes peripherals  4  to  9 . These peripherals preferably include an external memory interface (EMIF)  4  and a direct memory access (DMA) controller  5 . External memory interface (EMIF)  4  preferably supports access to supports synchronous and asynchronous SRAM and synchronous DRAM. Direct memory access (DMA) controller  5  preferably provides 2-channel auto-boot loading direct memory access. These peripherals include power-down logic  6 . Power-down logic  6  preferably can halt central processing unit activity, peripheral activity and phase lock loop (PLL) clock synchronization activity to reduce power consumption. These peripherals also include host ports  7 , serial ports  8  and programmable timers  9 . 
         [0023]    Central processing unit  1  has a 32-bit, byte addressable address space. Internal memory on the same integrated circuit is preferably organized in a data space including level one data cache  123  and a program space including level one instruction cache  121 . When off-chip memory is used, preferably these two spaces are unified into a single memory space via the external memory interface (EMIF)  4 . 
         [0024]    Level one data cache  123  may be internally accessed by central processing unit  1  via two internal ports  3   a  and  3   b . Each internal port  3   a  and  3   b  preferably has 32 bits of data and a 32-bit byte address reach. Level one instruction cache  121  may be internally accessed by central processing unit  1  via a single port  2   a . Port  2   a  of level one instruction cache  121  preferably has an instruction-fetch width of 256 bits and a 30-bit word (four bytes) address, equivalent to a 32-bit byte address. 
         [0025]    Central processing unit  1  includes program fetch unit  10 , instruction dispatch unit  11 , instruction decode unit  12  and two data paths  20  and  30 . First data path  20  includes four functional units designated L 1  unit  22 , S 1  unit  23 , M 1  unit  24  and D 1  unit  25  and 16 32-bit A registers forming register file  21 . Second data path  30  likewise includes four functional units designated L 2  unit  32 , S 2  unit  33 , M 2  unit  34  and D 2  unit  35  and 16 32-bit B registers forming register file  31 . The functional units of each data path access the corresponding register file for their operands. There are two cross paths  27  and  37  permitting access to one register in the opposite register file each pipeline stage. Central processing unit  1  includes control registers  13 , control logic  14  and test logic  15 , emulation logic  16  and interrupt logic  17 . 
         [0026]    Program fetch unit  10 , instruction dispatch unit  11  and instruction decode unit  12  recall instructions from level one instruction cache  121  and deliver up to eight 32-bit instructions to the functional units every instruction cycle. Processing occurs in each of the two data paths  20  and  30 . As previously described above each data path has four corresponding functional units (L, S, M and D) and a corresponding register file containing 16 32-bit registers. Each functional unit is controlled by a 32-bit instruction. The data paths are further described below. A control register file  13  provides the means to configure and control various processor operations. 
         [0027]      FIG. 3  illustrates the pipeline stages  300  of digital signal processor core  110 . These pipeline stages are divided into three groups: fetch group  310 ; decode group  320 ; and execute group  330 . All instructions in the instruction set flow through the fetch, decode and execute stages of the pipeline. Fetch group  310  has four phases for all instructions and decode group  320  has two phases for all instructions. Execute group  330  requires a varying number of phases depending on the type of instruction. 
         [0028]    The fetch phases of the fetch group  310  are: Program address generate phase  311  (PG); Program address send phase  312  (PS); Program access ready wait stage  313  (PW); and Program fetch packet receive stage  314  (PR). Digital signal processor core  110  uses a fetch packet (FP) of eight instructions. All eight of the instructions proceed through fetch group  310  together. During PG phase  311 , the program address is generated in program fetch unit  10 . During PS phase  312 , this program address is sent to memory. During PW phase  313 , the memory read occurs. Finally during PR phase  314 , the fetch packet is received at CPU  1 . 
         [0029]    The decode phases of decode group  320  are: Instruction dispatch (DP)  321 ; and Instruction decode (DC)  322 . During the DP phase  321 , the fetch packets are split into execute packets. Execute packets consist of one or more instructions which are coded to execute in parallel. During DP phase  322 , the instructions in an execute packet are assigned to the appropriate functional units. Also during DC phase  322 , the source registers, destination registers and associated paths are decoded for the execution of the instructions in the respective functional units. 
         [0030]    The execute phases of the execute group  330  are: Execute  1  (E 1 )  331 ; Execute  2  (E 2 )  332 ; Execute  3  (E 3 )  333 ; Execute  4  (E 4 )  334 ; and Execute  5  (E 5 )  335 . Different types of instructions require different numbers of these phases to complete. These phases of the pipeline play an important role in understanding the device state at CPU cycle boundaries. 
         [0031]    During E 1  phase  331 , the conditions for the instructions are evaluated and operands are read for all instruction types. For load and store instructions, address generation is performed and address modifications are written to a register file. For branch instructions, branch fetch packet in PG phase  311  is affected. For all single-cycle instructions, the results are written to a register file. All single-cycle instructions complete during the E 1  phase  331 . 
         [0032]    During the E 2  phase  332 , for load instructions, the address is sent to memory. For store instructions, the address and data are sent to memory. Single-cycle instructions that saturate results set the SAT bit in the control status register (CSR) if saturation occurs. For single cycle 16×16 multiply instructions, the results are written to a register file. For M unit non-multiply instructions, the results are written to a register file. All ordinary multiply unit instructions complete during E 2  phase  322 . 
         [0033]    During E 3  phase  333 , data memory accesses are performed. Any multiply instruction that saturates results sets the SAT bit in the control status register (CSR) if saturation occurs. Store instructions complete during the E 3  phase  333 . 
         [0034]    During E 4  phase  334 , for load instructions, data is brought to the CPU boundary. For multiply extensions instructions, the results are written to a register file. Multiply extension instructions complete during the E 4  phase  334 . 
         [0035]    During E 5  phase  335 , load instructions write data into a register. Load instructions complete during the E 5  phase  335 . 
         [0036]      FIG. 4  illustrates an example of the instruction coding of instructions used by digital signal processor core  110 . Each instruction consists of 32 bits and controls the operation of one of the eight functional units. The bit fields are defined as follows. The creg field (bits 29 to 31) is the conditional register field. These bits identify whether the instruction is conditional and identify the predicate register. The z bit (bit 28) indicates whether the predication is based upon zero or not zero in the predicate register. If z=1, the test is for equality with zero. If z=0, the test is for nonzero. The case of creg=0 and z=0 is treated as always true to allow unconditional instruction execution. The creg field is encoded in the instruction opcode as shown in Table 1. 
         [0000]    
       
         
               
               
               
               
             
               
               
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
             
             
               
                   
                   
               
               
                   
                 Conditional 
                 creg 
                 z 
               
             
          
           
               
                   
                 Register 
                 31 
                 30 
                 29 
                 28 
               
               
                   
                   
               
               
                   
                 Unconditional 
                 0 
                 0 
                 0 
                 0 
               
               
                   
                 Reserved 
                 0 
                 0 
                 0 
                 1 
               
               
                   
                 B0 
                 0 
                 0 
                 1 
                 z 
               
               
                   
                 B1 
                 0 
                 1 
                 0 
                 z 
               
               
                   
                 B2 
                 0 
                 1 
                 1 
                 z 
               
               
                   
                 A1 
                 1 
                 0 
                 0 
                 z 
               
               
                   
                 A2 
                 1 
                 0 
                 1 
                 z 
               
               
                   
                 A0 
                 1 
                 1 
                 0 
                 z 
               
               
                   
                 Reserved 
                 1 
                 1 
                 1 
                 x 
               
               
                   
                   
               
               
                   
                 Note 
               
               
                   
                 that “z” in the z bit column refers to the zero/not zero comparison selection noted above and “x” is a don&#39;t care state. This coding can only specify a subset of the 32 registers in each register file as predicate registers. This selection was made to preserve bits in the instruction coding. 
               
             
          
         
       
     
         [0037]    The dst field (bits 23 to 27) specifies one of the 32 registers in the corresponding register file as the destination of the instruction results. 
         [0038]    The scr 2  field (bits 18 to 22) specifies one of the 32 registers in the corresponding register file as the second source operand. 
         [0039]    The scr 1 /cst field (bits 13 to 17) has several meanings depending on the instruction opcode field (bits 3 to 12). The first meaning specifies one of the 32 registers of the corresponding register file as the first operand. The second meaning is a 5-bit immediate constant. Depending on the instruction type, this is treated as an unsigned integer and zero extended to 32 bits or is treated as a signed integer and sign extended to 32 bits. Lastly, this field can specify one of the 32 registers in the opposite register file if the instruction invokes one of the register file cross paths  27  or  37 . 
         [0040]    The opcode field (bits 3 to 12) specifies the type of instruction and designates appropriate instruction options. A detailed explanation of this field is beyond the scope of this invention except for the instruction options detailed below. 
         [0041]    The s bit (bit 1) designates the data path  20  or  30 . If s=0, then data path  20  is selected. This limits the functional unit to L 1  unit  22 , S 1  unit  23 , M 1  unit  24  and D 1  unit  25  and the corresponding register file A  21 . Similarly, s=1 selects data path  20  limiting the functional unit to L  2  unit  32 , S 2  unit  33 , M 2  unit  34  and D 2  unit  35  and the corresponding register file B  31 . 
         [0042]    The p bit (bit 0) marks the execute packets. The p-bit determines whether the instruction executes in parallel with the following instruction. The p-bits are scanned from lower to higher address. If p=1 for the current instruction, then the next instruction executes in parallel with the current instruction. If p=0 for the current instruction, then the next instruction executes in the cycle after the current instruction. All instructions executing in parallel constitute an execute packet. An execute packet can contain up to eight instructions. Each instruction in an execute packet must use a different functional unit. 
         [0043]      FIG. 5  illustrates the encoding process  500  of video encoding. Many video encoding standards use similar processes such as represented in  FIG. 5 . Encoding process  500  begins with the n th frame F n    501 . Frequency transform block  502  transforms a macroblock of the pixel data into the spatial frequency domain. This typically involves a discrete cosine transform (DCT). This frequency domain data is quantized in quantization block  503 . This quantization typically takes into account the range of data values for the current macroblock. Thus differing macroblocks may have differing quantizations. In accordance with the H.264 standard, in the base profile the macroblock data may be arbitrarily reordered via reorder block  504 . As will be explained below, this reordering is reversed upon decoding. Other video encoding standards and the H.264 main profile transmit data for the macroblocks in strict raster scan order. The quantized data is encoded by entropy encoding block  505 . Entropy encoding employs fewer bits to encode more frequently used symbols and more bits to encode less frequency used symbols. This process reduces the amount of encoded that must be transmitted and/or stored. The resulting entropy encoded data is the encoded data stream. Video encoding standards typically permit two types of predictions. In inter-frame prediction, data is compared with data from the corresponding location of another frame. In intra-frame prediction, data is compared with data from another location in the same frame. 
         [0044]    For inter prediction, data from n- 1  th frame F n-1    510  and data from the current frame F n    501  supply motion estimation block  511 . Motion estimation block  511  determines the positions and motion vectors of moving objects within the picture. This motion data is supplied to motion compensation block  512  along with data from frame F n-1    510 . The resulting motion compensated frame data is selected by switch  513  for application to subtraction unit  506 . Subtraction unit  506  subtracts the inter prediction data from switch  513  from the input frame data from current frame F n    501 . Thus frequency transform block  502 , quantization block  503 , reorder block  504  and entropy encoding block  505  encode the differential data rather than the original frame data. Assuming there is relatively little change from frame to frame, this differential data has a smaller magnitude than the raw frame data. Thus this can be expressed in fewer bits contributing to data compression. This is true even if motion estimation block  511  and motion compensation block  512  find no moving objects to code. If the current frame F n  and the prior frame F n-1  are identical, the subtraction unit  506  will produce a string of zeros for data. This data string can be encoded using few bits. 
         [0045]    The second type of prediction is intra prediction. Intra prediction predicts a macroblock of the current frame from another macroblock of that frame. Inverse quantization block  520  receives the quantized data from quantization block  503  and substantially recovers the original frequency domain data. Inverse frequency transform block  521  transforms the frequency domain data from inverse quantization block  520  back to the spatial domain. This spatial domain data supplies one input of addition unit  522 , whose function will be further described. Encoding process  500  includes choose intra predication unit  514  to determine whether to implement intra prediction. Choose intra prediction unit  514  receives data from current frame F n    501  and the output of addition unit  522 . Choose intra prediction unit  514  signals intra prediction intra predication unit  515 , which also receives the output of addition unit  522 . Switch  513  selects the intra prediction output for application to the subtraction input of subtraction units  506  and an addition input of addition unit  522 . Intra prediction is based upon the recovered data from inverse quantization block  520  and inverse frequency transform block  521  in order to better match the processing at decoding. If the encoding used the original frame, there might be drift between these processes resulting in growing errors. 
         [0046]    Video encoders typically periodically transmit unpredicted frames. In such an event the predicted frame is all 0&#39;s. Subtraction unit  506  thus produces data corresponding to the current frame F n    501  data. Periodic unpredicted or I frames limit any drift between the transmitter coding and the receive decoding. In a video movie a scene change may produce such a large change between adjacent frames that differential coding provides little advantage. Video coding standards typically signal whether a frame is a predicted frame and the type of prediction in the transmitted data stream. 
         [0047]    Encoding process  500  includes reconstruction of the frame based upon this recovered data. The output of addition unit  522  supplies deblock filter  523 . Deblock filter  523  smoothes artifacts created by the block and macroblock nature of the encoding process. The result is reconstructed frame F′ n    524 . As shown schematically in  FIG. 5 , this reconstructed frame F′ n    524  becomes the next reference frame F n-1    510 . 
         [0048]      FIG. 6  illustrates the corresponding decoding process  600 . Entropy decode unit  601  receives the encoded data stream. Entropy decode unit  601  recovers the symbols from the entropy encoding of entropy encoding unit  505 . Reorder unit  602  assembles the macroblocks in raster scan order reversing the reordering of reorder unit  504 . Inverse quantization block  603  receives the quantized data from reorder unit  602  and substantially recovers the original frequency domain data. Inverse frequency transform block  604  transforms the frequency domain data from inverse quantization block  603  back to the spatial domain. This spatial domain data supplies one input of addition unit  605 . The other input of addition input  605  comes from switch  609 . In inter mode switch  609  selects the output of motion compensation unit  607 . Motion compensation unit  607  receives the reference frame F′ n-1    606  and applies the motion compensation computed by motion compensation unit  512  and transmitted in the encoded data stream. 
         [0049]    Switch  609  may also select intra prediction. The intra prediction is signaled in the encoded data stream. If this is selected, intra prediction unit  608  forms the predicted data from the output of adder  605  and then applies the intra prediction computed by intra prediction block  515  of the encoding process  500 . Addition unit  605  recovers the predicted frame. As previously discussed in conjunction with encoding, it is possible to transmit an unpredicted or I frame. If the data stream signals that a received frame is an I frame, then the predicted frame supplied to addition unit  605  is all 0&#39;s. 
         [0050]    The output of addition unit  605  supplies the input of deblock filter  610 . Deblock filter  610  smoothes artifacts created by the block and macroblock nature of the encoding process. The result is reconstructed frame F′ n    611 . As shown schematically in  FIG. 6 , this reconstructed frame F′ n    611  becomes the next reference frame F n    606 . 
         [0051]    The deblocking filtering of deblock filter  523  and deblock  610  must be the same. This enables the decoding process to accurately reflect the input frame F n    501  without error drift. The H.264 standard has a specific, very detailed decision matrix and corresponding filter operations for this process. The standard deblock filtering is applied to every macroblock in raster scan order. This deblock filtering smoothes artifacts created by the block and macroblock nature of the encoding. The filtered macroblock is used as the reference frame in predicted frames in both encoding and decoding. The encoding and decoding apply the identical processing to the reconstructed frame to reduce the residual error after prediction. 
         [0052]    As coding algorithms increase in complexity and screen resolutions increase, multiple processing elements may be employed in encoding and decoding. These multiple processors may be a combination of one or more digital signal processors, a general purpose processor and dedicated hardware processing blocks designed to implement specific algorithms. To optimize system performance, it is necessary to accurately benchmark the individual processing elements. 
         [0053]    Making each individual processor is responsible for its own benchmarking, removes the need for an interrupt service routine and the general purpose processor is relieved from the task of trimming each processor. Instead of implementing a timer, it is sufficient to implement a benchmark counter in each of the processors. Since all processors are synchronous with corresponding clocks, measuring processor performance may be accomplished by counting the number of clock ticks used by the processor. A start command resets the benchmark counter. The benchmark counter increments with every subsequent clock-tick and stops upon a stop command. After the stop command the processor is in a halted state until another enable or start command is detected. The benchmark counter may then be read to determine the number of clock ticks. 
         [0054]      FIG. 7  illustrates the process of this invention in benchmark mode. Each processor is loaded with appropriate software for the benchmark. This will generally be an example of software of the type that will be used in the operating system. As stated above, each processor of the multiprocessor system has a special benchmark counter for benchmarking. Each processor will be halted before beginning the process. This will generally be an emulation halt. At block  701  the data processor determines if a start command has been received. If not (No at block  701 ), then the processors loops back to block  701  to await a start command. 
         [0055]    If a start command is received (Yes at block  701 ), then block  702  resets the benchmark counter. Block  703  then begins the data processor and enables counting by the benchmark counter. 
         [0056]    Block  704  determines if a stop command is received. If not (No at block  704 ), then the processors loops back to block  704 . The data processor continues to run and the benchmark counter continues to increment on each clock tick. 
         [0057]    If stop command is received (Yes at block  704 ), then block  705  stops the data processor and thus counting by the benchmark counter. In the preferred embodiment, this is an emulation halt. The benchmark counter may then be read in block  706 . The count in the benchmark counter and the correspond clock frequency of the data process indicate the amount of processing employed between the start command and the end command. A particular one of the processors in the multiprocessor system, such as a single general purpose data processor, can poll benchmark counters of other data processors. This particular processor then possesses the information for benchmarking the multiprocessor system. 
         [0058]    As an alternative, the data processor may be programmed to generate an interrupt upon detecting the end command. This interrupt command alerts the benchmarking data processor to the completion of the benchmarking program.