Abstract:
A self-aligned via between interconnect layers in an integrated circuit, and a process for forming such a via which allows a less precise masking alignment to be used to fabricate an integrated circuit with increased packing density.

Description:
This application is a continuation of application Ser. No. 08/341,800, filed Nov. 18, 1994, abandoned which is a division of application Ser. No. 08/201,437, filed Feb. 24, 1994, now U.S. Pat. No. 5,471,094. 
    
    
     FIELD OF THE INVENTION 
     This invention relates to a self-aligned via between interconnect layers in an integrated circuit and to a process for forming such a via. 
     BACKGROUND OF THE INVENTION 
     In the fabrication of semiconductor memory devices and other types of integrated circuits, two or more conductive layers known as interconnect layers are commonly deposited. These interconnect layers are separated, for example, by one or more dielectric layers. Various methods may be used to make electrical connections between these interconnect layers. One such method includes (a) forming a first dielectric layer, (b) depositing a first interconnect layer (“Poly 1”), (c) masking and etching Poly 1 to form conductive leads, (d) depositing a second dielectric layer, (e) masking and etching the second dielectric layer to form a “via” (a small opening) completely through the second dielectric layer to a Poly 1 conductive lead, and (f) depositing a second interconnect layer (“Poly 2”) in and over the via so that electrical contact between Poly 1 and Poly 2 is made through a “plug” of conductive material which fills the via. One of the difficulties in using this method is that it is necessary to compensate for possible misalignment of the via mask. For example, a misalignment of the via mask may shift the via sideways so that the via is not formed entirely over the Poly 1 conductor. Instead, the via may overlap onto the first dielectric layer alongside a Poly 1 conductor, exposing the first dielectric layer during the via etch step, and allowing a groove to be etched in the first dielectric layer during the via etch step. The groove may cause microcracking or thinning of the Poly 2 conductor when it is deposited in and over the via to contact the Poly 1 conductor. This can be avoided by widening the Poly 1 conductor at the via location so that even a misaligned via will not overlap onto the first dielectric layer. However, locally widening the Poly 1 conductor conflicts with the goal of reducing the size of the integrated circuit and increasing its packing density. 
     It is desirable to decrease the memory cell size in fabricating semiconductor memory devices such as random access memory chips, in order to increase the packing density. A major factor limiting further increases in packing density is the alignment tolerance of the via mask used in forming a via between Poly 1 and Poly 2. 
     SUMMARY OF THE INVENTION 
     In accordance with the present invention, a process is provided for forming a self-aligned via between interconnect layers on an integrated circuit chip. This self-aligned feature permits a less precise masking alignment to be used in forming such a via, without the disadvantage of locally widening the Poly 1 conductor at the via location as in the prior art process described above. In the present invention, the smaller linewidth of the Poly 1 conductor at the via location makes it possible to fabricate an integrated circuit with greater packing density, reduced die size, and improved yield. 
     In one embodiment, the process of the present invention includes (a) depositing a first conductive layer overlying one surface of a semiconductor substrate, (b) forming a first dielectric layer directly upon the first conductive layer, (c) masking and etching the first dielectric layer to form a via, (d) forming a conductive plug within the via, (e) masking and etching the conductive plug, the first dielectric layer, and the first conductive layer to form an interconnect structure, (f) depositing a second dielectric layer overlying the substrate and the interconnect structure, (g) etching the second dielectric layer to expose the upper surface of the conductive plug, and (h) forming a second interconnect layer overlying the second dielectric layer so that an electrical connection is formed between the first and second interconnect layers. The resulting structure will have a conductive plug formed within the self-aligned via, with one edge of the conductive plug normally being aligned with one edge of the first interconnect layer, and the other edge of the conductive plug either lying above the first interconnect layer or aligned with the other edge of the first interconnect layer. If the via mask is perfectly aligned, both edges of the conductive plug will be aligned with the edges of the first interconnect layer. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIGS. 1 a  through  1   g  illustrate one process for making a novel self-aligned via in accordance with this invention. 
     FIG. 2 shows a cross-sectional perspective view of one embodiment of a self-aligned via in accordance with this invention. 
     FIG. 3 shows a cross-sectional perspective view of a second embodiment of a self-aligned via in accordance with this invention. 
     FIGS. 4 and 5 show a schematic diagram and a layout of an SRAM memory cell fabricated by using self-aligned vias in accordance with this invention. 
    
    
     DETAILED DESCRIPTION 
     In FIG. 1 a , a first conductive layer  20  of any suitable conductive material is deposited overlying one or more other layers on a wafer. Typically, the first conductive layer  20  is formed on a dielectric layer  19  overlying a semiconductor substrate  18  (usually, but not necessarily silicon). For simplicity and clarity, the semiconductor substrate  18  and the dielectric layer  19  are omitted from FIG. 1 b  through  1   g . but it should be understood that elements  18  and  19  are present throughout the described process. The first conductive layer  20  will be formed into a first layer of interconnects at a later step in the process of this invention. In one embodiment, the first conductive layer  20  is formed of polysilicon (polycrystalline silicon) about 2,000 to 3,000 angstroms thick by CVD deposition of silane (SiH 4 ) at a temperature of about 610° C. This polysilicon layer is either formed doped in a standard, well-known manner or is doped by a standard process such as diffusion or ion implantation. A first dielectric layer  22  of silicon dioxide about 3,000 angstroms thick is then formed on layer  20  by thermal oxidation of the polysilicon first conductive layer  20  at a temperature of approximately 410° C. 
     The first dielectric layer  22  is then masked and typically dry etched in a well-known manner to form a via  24 , as shown in FIG. 1 b.    
     In FIG. 1 c , the via  24  is filled with a plug  26  of any suitable conductive material. In one embodiment, the plug  26  is formed of doped polysilicon. Alternatively, plug  26  can be formed of undoped polysilicon, in which case the undoped plug will become doped from outdiffusion of dopant from the first polysilicon conductive layer  20  or from a subsequently formed second polysilicon layer. Alternatively, the plug  26  may be formed of tungsten silicide. The plug  26  may be formed either by selective deposition or by blanket deposition and etchback in a well-known manner. In one embodiment, the plug  26  is about 3,000 angstroms thick. 
     A mask, typically of photoresist  28 , is then used to define the conductive lead pattern to be formed from the first conductive layer  20 . FIG. 1d shows a cross-sectional view of the resist  28  where it passes over the plug  26 . The offset “t” between the resist  28  and the plug  26  is caused by misalignment of the via mask which reflects the inherent inability to exactly align any mask in its desired position on a wafer. The process used to fabricate a semiconductor device must always reflect the tolerances for the alignment on the wafer of the masks used to fabricate the device. 
     The portions of the first dielectric layer  22 , the plug  26 , and the first conductive layer  20  which are not protected by the resist are then etched to form (after removal of the resist) an interconnect structure (FIG. 1 e ). In this etching step, the first conductive layer  20  is etched to form a first interconnect layer. FIG. 1 e  shows a cross-sectional view of a conductive lead  20   a  which is part of the first interconnect layer. In one embodiment, the unprotected portions of a first dielectric layer  22  of silicon dioxide, a plug  26  of polysilicon, and a first conductive layer  20  of polysilicon are etched in a two-step process. In the first step, a well-known dry etch process is used to anisotropically etch the unprotected portions of the first dielectric layer  22  and of the plug  26 . For example, if the plug  26  is polysilicon, a chlorine or a bromine plasma etch may be used. Alternatively, if the plug  26  is tungsten silicide, a fluorine plasma etch may be used. If a composite tungsten silicide-polysilicon plug is used, a fluorine plasma etch is used, followed by either a chlorine or bromine plasma etch. In the second step, a dry etch process is used to anisotropically etch the unprotected portion of the first conductive layer  20 . Typically, a fluorine plasma is used to initiate the etch, a mixture of chlorine and bromine plasma is used to etch the bulk of the polysilicon, and bromine plasma (which is highly selective and preferentially etches polysilicon 50 to 100 times faster than it etches silicon dioxide) is used in the final overetch step to remove the residual polysilicon. 
     Due to the misalignment of the via mask, the left edge of plug  26  is etched away so that the plug is narrower than the conductive lead  20   a , leaving a small pocket  22   a  of the first dielectric layer  22  next to the plug. In contrast with the prior art, misalignment of the via mask does not cause any significant harmful effect as long as the etching step does not remove so much of the plug  26  that the plug  26  is no longer an effective conductor between the first interconnect layer and a second interconnect layer to be formed in a later step. This is a unique feature of this invention, permitting the use of a less precise via mask alignment than would normally be required. 
     In FIG. 1 f , a second dielectric layer  30  is then deposited to a selected thickness. In one embodiment, the second dielectric layer  30  is formed of silicon dioxide about 1,000 to 1,500 angstroms thick by plasma enhanced CVD. A sacrificial layer  32  of a material such as photoresist or spin-on-glass is formed on the wafer to protect the portion of the second dielectric layer  30  over the active regions of the underlying semiconductor substrate  18  and dielectric layer  19  (FIG. 1 a ) while allowing the portion of the second dielectric layer  30  which is directly above the plug  26  to be etched away to expose the top surface of the plug  26 . As shown in FIG. 1 g , the remainder of the photoresist sacrificial layer  32  is then typically stripped in a dry etch process using oxygen plasma followed by sulfuric peroxide. Alternatively, if spin-on-glass is used as a sacrificial layer, it may either be left on the wafer or removed by using hydrogen fluoride. 
     In one embodiment, the polysilicon conductive lead  20   a  forms the gate of an MOS transistor. The thickness of both the plug  26  and the sacrificial layer  32  are therefore selected so that the sacrificial layer will be thinner over the plug than over the source and drain regions. Thus, the portion of the sacrificial layer  32  and of the second dielectric layer  30  which is directly above the plug  26  may be masked and etched (for example, by using a dry plasma etch) to expose the top surface of the plug, while the sacrificial layer  32  protects the second dielectric layer  30  over the source and drain regions. Alternatively, well-known chemical mechanical polishing (“CMP”) may be used to expose the top surface of the plug  26 , thus avoiding the need for a sacrificial layer (although the sacrificial layer may still be used). In this embodiment, it may be desirable not to form the plug  26  directly above the gate of an MOS device if the plug would be sufficiently close to the source or drain contact to cause shorting. 
     FIG. 2 shows a cross-sectional view of one embodiment of a self-aligned via and plug in accordance with this invention. In this view, the small pocket  22   a  of the first dielectric layer  22  next to the plug  26  has been removed to more clearly show the structure of the conductive lead  20   a  (which is part of the first interconnect layer) and of the plug  26 . 
     FIG. 3 shows a partial cross-sectional view of a second embodiment of a self-aligned via and plug in accordance with this invention. This view shows the substrate  34  and a dielectric layer  36  which is formed overlying the substrate before the self-aligned via and plug are formed. This view also shows one or more intervening layers  37  (typically including an additional dielectric layer) which are formed overlying the second dielectric layer  30  prior to the formation of a second interconnect layer. In this view, a second conductive lead  38  (which is part of a second interconnect layer formed in a manner well known in the art) contacts the top surface of the plug  26 , so that an electrical connection is formed between the first and second interconnect layers. (FIG. 3 is intended to show only the manner in which the second conductive lead  38  contacts the top of the plug  26 . For clarity, only those portions of the second conductive lead  38  and the intervening layers  37  are shown which are adjacent to the plug  26 , with the remaining portions stripped away.) 
     FIGS. 4 and 5 show a schematic diagram and a layout of a poly-load SRAM memory cell fabricated by using self-aligned vias according to one embodiment of this invention. The memory cell, which is well known in the art, includes NMOS access transistors Q 3  and Q 4 , NMOS driver transistors Q 1 . and Q 2 , and high-valued load resistors R 1 , and R 2 . As shown in FIG. 5, the gates  40   a-   40   d  of transistors Q 1- Q 4  are formed in the first polysilicon layer (“Poly 1”), which is heavily doped. NMOS transistors Q 1 , and Q 3  share a common drain  42   a , and NMOS transistors Q 2  and Q 4  share a common drain  42   b . The load resistors R 1 , and R 2  (not shown in FIG. 5) are formed in a lightly doped portion of the second polysilicon layer (“Poly 2”). The remainder of the Poly 2 layer is implanted with a much higher dopant concentration and patterned to form a low resistance interconnect layer which includes conductive leads  44   a  and  44   b  (FIG.  5 ). 
     FIG. 5 illustrates the use of self-aligned vias in the above described SRAM memory cell in accordance with this invention. The connection between the Poly 1 gate  40   c  of transistor Q 1 . and the common drain  42   b  of transistors Q 2  and Q 4  is made through the self-aligned via  46   a , the Poly 2 conductive lead  44   b , and the self-aligned via  46   d . The connection between the Poly 1 gate  40   d  of transistor Q 2  and the common drain  42   a  of transistors Q 1 , and Q 3  is made through the self-aligned via  46   c , the Poly 2 conductive lead  44   a , and the self-aligned via  46   b . The drain  42   a  of transistor Q 3  and the drain  42   b  of transistor Q 4  are connected to Poly 2 resistors R 1 , and R 2  (not shown) through buried contacts  48   a  and  48   b . Finally, the common source of transistors Q 1 , and Q 2  is contacted through buried contact V ss.    
     Significant advantages are achieved by using self-aligned vias in SRAM memory cells according to the present invention. For example, in the embodiment of FIGS. 4 and 5, it is possible to reduce the device area by approximately 10% compared to the prior art, resulting in a 7% increase in yield. 
     This invention has been described using polysilicon for the conductive interconnect layers. However, other suitable materials, such as polycides, silicides, or metals (such as aluminum, titanium, tungsten or combinations thereof) may be used to form one or more of the interconnect layers, depending on the processing temperatures and other requirements of the particular process. The drawings are illustrative of one embodiment, and are not intended to be limiting; for example, the plug  26  may be round or another shape (referring to a cross-sectional top view of the plug), rather than rectangular as shown in FIG.  2 . Further, other suitable semiconductors such as gallium arsenide may be used as substrates. It should be understood that this invention, although advantageous for memory cells and particularly SRAM memory cells, is not limited to the use of self-aligned vias in semiconductor memory devices, but may be used to form electrical connections between interconnect layers in virtually any integrated circuit. 
     Other embodiments of the invention will be apparent to persons skilled in the art upon considering this specification or practicing the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the full scope of the invention being indicated by the following claims.