Abstract:
A semiconductor structure and a method for forming the same. The structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a gate dielectric region, and (iv) a gate electrode region, (v) a plurality of interconnect layers on the gate electrode region, and (vi) first and second spaces. The gate dielectric region is disposed between and in direct physical contact with the channel region and the gate electrode region. The gate electrode region is disposed between and in direct physical contact with the gate dielectric region and the interconnect layers. The first and second spaces are in direct physical contact with the gate electrode region. The first space is disposed between the first source/drain region and the gate electrode region. The second space is disposed between the second source/drain region and the gate electrode region.

Description:
FIELD OF THE INVENTION 
   The present invention relates generally to semiconductor transistors and more particularly to semiconductor transistors having high-K gate dielectric layers, metal gate electrode regions, and low fringing capacitances. 
   BACKGROUND OF THE INVENTION 
   In a typical transistor with a high-K gate dielectric layer and a metal gate electrode region, the fringing capacitances between the gate electrode region and the source/drain regions of the transistor detrimentally affect the operation of the transistor. Therefore, there is a need for a structure (and a method for forming the same) in which the fringing capacitances are lower than those of the prior art. 
   SUMMARY OF THE INVENTION 
   The present invention provides a semiconductor structure fabrication method, comprising providing a semiconductor structure which includes (i) a semiconductor substrate which includes a channel region, (ii) a first source/drain region on the semiconductor substrate, (iii) a second source/drain region on the semiconductor substrate, wherein the channel region is disposed between the first and second source/drain regions, (iv) a gate dielectric region which includes a first gate dielectric portion, a second gate dielectric portion, and a third gate dielectric portion, wherein the third gate dielectric portion of the gate dielectric region is in direct physical contact with the channel region, wherein the gate dielectric region comprises a first dielectric material having a first dielectric constant, and wherein the first dielectric constant is greater than 4, (v) a gate electrode region, wherein the first gate dielectric portion of the gate dielectric region is disposed between and in direct physical contact with the channel region and the gate electrode region, and wherein the gate electrode region comprises an electrically conductive material, (vi) a first converting portion, wherein the first gate dielectric portion of the gate dielectric region is disposed between and in direct physical contact with the first converting portion and the gate electrode region, and (vii) a second converting portion, wherein the second gate dielectric portion of the gate dielectric region is disposed between and in direct physical contact with the second converting portion and the gate electrode region, and wherein the first and second converting portions comprise a converting material; causing the converting material of the first converting portion to chemically react with the first dielectric material of the first gate dielectric portion of the gate dielectric region resulting in a first spacer dielectric region; and causing the converting material of the second converting portion to chemically react with the first dielectric material of the second gate dielectric portion of the gate dielectric region resulting in a second spacer dielectric region, wherein the first and second spacer dielectric regions comprise a second dielectric material having a second dielectric constant, and wherein the second dielectric constant is lower than the first dielectric constant]. 
   The present invention provides a transistor (and a method for forming the same) in which the fringing capacitances are lower than those of the prior art. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIGS. 1A-1Q  show cross-section views used to illustrate a fabrication process of a semiconductor structure, in accordance with embodiments of the present invention. 
       FIGS. 2A-2K  show cross-section views used to illustrate a fabrication process of another semiconductor structure, in accordance with embodiments of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIGS. 1A-1Q  show cross-section views used to illustrate a fabrication process of a semiconductor structure  100 , in accordance with embodiments of the present invention. More specifically, with reference to  FIG. 1A , the fabrication process of the semiconductor structure  100  can start with a silicon substrate  110 . 
   Next, in one embodiment, a temporary gate dielectric layer  112  is formed on top of the silicon substrate  110 . The temporary gate dielectric layer  112  can comprise silicon dioxide. The temporary gate dielectric layer  112  can be formed by thermally oxidizing the top surface  110 ′ of the silicon substrate  110  resulting in the temporary gate dielectric layer  112 . 
   Next, in one embodiment, a temporary gate electrode layer  120  is formed on top of the temporary gate dielectric layer  112 . The temporary gate electrode layer  120  can comprise poly-silicon. The temporary gate electrode layer  120  can be formed by CVD (Chemical Vapor Deposition) of poly-silicon on top of the temporary gate dielectric layer  112 . 
   Next, in one embodiment, a cap layer  125  is formed on top of the temporary gate electrode layer  120 . The cap layer  125  can comprise silicon dioxide. The cap layer  125  can be formed by CVD of silicon dioxide on top of the temporary gate electrode layer  120 . 
   Next, in one embodiment, the cap layer  125  and the temporary gate electrode layer  120  are patterned resulting in the cap region  125  and the temporary gate electrode region  120  of  FIG. 1B . More specifically, the cap layer  125  and the temporary gate electrode layer  120  can be patterned using conventional lithographic and etching processes. 
   Next, with reference to  FIG. 1C , in one embodiment, extension regions  114   a  and  114   b  are formed in the silicon substrate  110 . More specifically, the extension regions  114   a  and  114   b  can be formed by a conventional ion implantation process. 
   Next, with reference to  FIG. 1D , in one embodiment, spacer regions  130   a  and  130   b  are formed on the side walls of the temporary gate electrode region  120 . The spacer regions  130   a  and  130   b  can comprise silicon nitride. The spacer regions  130   a  and  130   b  can be formed by (i) depositing a silicon nitride layer (not shown) on top of the structure  100  of  FIG. 1C  and then (ii) anisotropically etching the silicon nitride layer in a vertical direction defined by an arrow  135  (direction  135 ) until the top surface  110 ′ of the temporary gate electrode region  110  is exposed to the surrounding ambient resulting in the spacer regions  130   a  and  130   b . The direction  135  is perpendicular to the top surface  110 ′ of the silicon substrate  110  and points from the temporary gate dielectric layer  112  toward the silicon substrate  110 . 
   Next, with reference to  FIG. 1E , in one embodiment, source/drain regions  116   a  and  116   b  are formed in the silicon substrate  110 . More specifically, the source/drain regions  116   a  and  116   b  can be formed by a conventional ion implantation process. 
   Next, with reference to  FIG. 1F , in one embodiment, silicide regions  140   a  and  140   b  are formed on the source/drain regions  116   a  and  116   b , respectively. The silicide regions  140   a  and  140   b  can be formed by (i) depositing a metal layer (not shown) on top of the structure  100  of  FIG. 1E , then (ii) heating the structure  100  resulting in the metal chemically reacting with silicon of the source/drain regions  116   a  and  116   b , and then (iii) removing unreacted metal resulting in the silicide regions  140   a  and  140   b . In one embodiment, the silicide region  140   a  comprises nickel silicide. 
   Next, with reference to  FIG. 1G , in one embodiment, a dielectric layer  150  and a BPSG (boro-phospho-silicate glass) layer  160  are formed on top of the structure  100  of  FIG. 1F . In general, the material of the dielectric layer  150  is the same as the material of the spacer regions  130   a  and  130   b  (i.e., silicon nitride). The dielectric layer  150  and the BPSG layer  160  can be formed by (i) depositing silicon nitride on top of the structure  100  of  FIG. 1F  resulting in the dielectric layer  150  and then (ii) depositing BPSG on top of the dielectric layer  150  resulting in the BPSG layer  160 . 
   Next, in one embodiment, a CMP (Chemical Mechanical Polishing) process is performed on top of the structure  100  of  FIG. 1G  until the top surface  122  of the temporary gate electrode region  120  is exposed to the surrounding ambient resulting in the structure  100  of  FIG. 1H . After the CMP process is performed, what remain of the BPSG layer  160  are BPSG regions  160   a  and  160   b , and what remain of the dielectric layer  150  are dielectric regions  150   a  and  150   b.    
   Next, with reference to  FIG. 1H , in one embodiment, the temporary gate electrode region  120  is removed resulting in a trench  124  of  FIG. 1I . The temporary gate electrode region  120  can be removed by a wet etching process. 
   Next, with reference to  FIG. 1I , in one embodiment, a portion  112 ′ of the temporary gate dielectric region  112  is removed resulting in the top surface  110 ′ of the silicon substrate  110  being exposed to the surrounding ambient, as shown in  FIG. 1J . The portion  112 ′ can be removed by a wet etching process. 
   Next, with reference to  FIG. 1K , in one embodiment, a gate dielectric layer  170  and an electrically conductive layer  180  are formed on top of the structure  100  of  FIG. 1J . The gate dielectric layer  170  can comprise a high-K dielectric material, wherein K is a dielectric constant and K is greater than 4. For example, the gate dielectric layer  170  comprises hafnium silicon oxynitride (Hf x Si y O z N w ). The electrically conductive layer  180  can comprise a metal such as tantalum nitride (TaN). The gate dielectric layer  170  and the electrically conductive layer  180  can be formed by (i) CVD or ALD (Atomic Layer Deposition) of the Hf x Si y O z N w  on top of the structure  100  of  FIG. 1J  resulting in the gate dielectric layer  170  and then (ii) CVD or ALD of tantalum nitride on top of the gate dielectric layer  170  such that the trench  124  is completely filled with tantalum nitride resulting in the electrically conductive layer  180 . 
   Next, in one embodiment, a CMP process is performed on top of the structure  100  of  FIG. 1K  until the top surface  165  of the BPSG regions  160   a  and  160   b  are exposed to the surrounding ambient resulting in the structure  100  of  FIG. 1L . After the CMP process is performed, what remain of the gate dielectric layer  170  and the electrically conductive layer  180  are the gate dielectric region  170  and the gate electrode region  180 , respectively. 
   Next, with reference to  FIG. 1L , in one embodiment, portions  130   a ′ and  130   b ′ of the spacer regions  130   a  and  130   b , respectively, and portions  150   a ′ and  150   b ′ of the dielectric regions  150   a  and  150   b , respectively, are removed resulting in trenches  155   a  and  155   b  of  FIG. 1M . After the removal of the portions  130   a ′,  130   b ′,  150   a ′, and  150   b ′ is performed, what remain of the spacer region  130   a  and the dielectric region  150   a  can be collectively referred to as a dielectric region  130   a + 150   a , and what remain of the spacer region  130   b  and the silicon nitride region  150   b  can be collectively referred to as a dielectric region  130   b + 150   b.    
   Next, with reference to  FIG. 1N , in one embodiment, a titanium layer  190  is formed on top of the structure  100  of  FIG. 1M  such that the trenches  155   a  and  155   b  are completely filled with titanium. The titanium layer  190  can be formed by ALD of titanium on top of the structure  100  of  FIG. 1M . 
   Next, in one embodiment, the structure  100  is annealed at a temperature around 400-600° C. resulting in titanium of the layer  190  chemically reacting with Hf x Si y O z N w  of the gate dielectric region  170  resulting in the dielectric regions  195   a  and  195   b  of  FIG. 1O  which comprise titanium hafnium silicon oxynitride (Ti v Hf x Si y O z N w ) Ti v Hf x Si y O z N w  is a low-K dielectric material. After the annealing of the structure  100  is performed, what remains of the gate dielectric region  170  is the gate dielectric region  170 ′, and unreacted titanium of the layer  190  can be referred to as the titanium layer  190 ′. 
   In the embodiments described above, the material of the gate dielectric layer  170  ( FIG. 1K ) is Hf x Si y O z N w  and the material of the layer  190  is titanium. In general, the material of the gate dielectric layer  170  and the material of the layer  190  can be selected such that (i) the material of the gate dielectric layer  170  is a high-K dielectric material (K&gt;4) and (ii) at a high temperature (e.g., around 400-600°), the material of the gate dielectric layer  170  and the material of the layer  190  chemically react with each other resulting in a low-K dielectric material (K&lt;4). 
   Next, with reference to  FIG. 1O , in one embodiment, the titanium layer  190 ′ is removed resulting in the structure  100  of  FIG. 1P . The titanium layer  190 ′ can be removed by a selective wet etching process. 
   With reference to  FIG. 1P , the structure  100  shows a transistor having the gate electrode region  180 , the gate dielectric region  170 ′, the source/drain regions  116   a  and  116   b  and the channel  115 . The dielectric regions  195   a  and  195   b  can be referred to as spacer dielectric regions  195   a  and  195   b.    
   Next, in one embodiment, interconnect layers (not shown) are formed on top of the structure  100  to provide electrical access to the transistor of  FIG. 1P . 
   It should be noted that the fringing capacitance between the gate electrode region  180  and the source/drain region  116   a  depends on the dielectric constants of the materials of the dielectric regions disposed between the gate electrode region  180  and the source/drain region  116   a . Similarly, the fringing capacitance between the gate electrode region  180  and the source/drain region  116   b  depends on the dielectric constants of the materials of the dielectric regions disposed between the gate electrode region  180  and the source/drain region  116   b . In general, it is desirable to reduce dielectric constants of these dielectric regions so as to reduce the fringing capacitances. 
   With reference to  FIGS. 1N and 1O , as described above, Hf x Si y O z N w  of the gate dielectric region  170  is converted to Ti v Hf x Si y O z N w  of the dielectric regions  195   a  and  195   b  which has a lower dielectric constant than Hf x Si y O z N w  of the gate dielectric region  170 . As a result, the fringing capacitances between the gate electrode region  180  and the source/drain regions  116   a  and  160   b  are reduced. 
   In the embodiments described above, the interconnect layers are formed on top of the structure  100  to provide electrical access to the transistor of  FIG. 1P . Alternatively, with reference to  FIG. 1P , before the interconnect layers are formed on top of the structure  100 , the dielectric regions  195   a  and  195   b  are removed resulting in trenches  195   a ′ and  195   b ′ of  FIG. 1Q . More specifically, the dielectric regions  195   a  and  195   b  can be removed by a wet etching process. 
   Next, in one embodiment, the interconnect layers (not shown) are formed on top of the structure  100  of  FIG. 1Q  to provide electrical access to the transistor of  FIG. 1Q  such that the trenches  195   a ′ and  195   b ′ are not completely filled by solid material. As a result, the trenches  195   a ′ and  195   b ′ can still contain some spaces (not shown) that contain gases, vapors, and/or vacuum. In one embodiment, these spaces are in direct physical contact with the gate electrode region  180 . These spaces can be in direct physical contact with the gate dielectric region  170 ′. 
   It should be noted that after the interconnect layers are formed, the dielectric constants of the materials that fill the trenches  195   a ′ and  195   b ′ (dielectric solid materials, gases, vapors, and/or vacuum) are lower than that of Ti v Hf x Si y O z N w  of the dielectric regions  195   a  and  195   b  of  FIG. 1P . Therefore, fringing capacitances between the gate electrode region  180  and the source/drain regions  116   a  and  116   b  are further reduced. 
     FIGS. 2A-2K  show cross-section views used to illustrate a fabrication process of a semiconductor structure  200 , in accordance with embodiments of the present invention. More specifically, with reference to  FIG. 2A , the fabrication process of the semiconductor structure  200  can start with the structure  200  of  FIG. 2A . The structure  200  of  FIG. 2A  is similar to the structure  100  of  FIG. 1F . The formation of the structure  200  is similar to the formation of the structure  100  of  FIG. 1F . 
   Next, in one embodiment, the spacer regions  130   a  and  130   b  are removed. More specifically, the spacer regions  130   a  and  130   b  can be removed by a wet etching process. 
   Next, with reference to  FIG. 2B , in one embodiment, a dielectric layer  250  and a titanium layer  260  are formed in turn. The dielectric layer  250  can comprise silicon dioxide. The dielectric layer  250  and the titanium layer  260  can be formed using conventional processes. 
   Next, in one embodiment, an anisotropic etching process is performed in the direction  135  until the top surface  252  of the dielectric layer  250  is exposed to the surrounding ambient resulting in the structure  200  of  FIG. 2C . After the anisotropic etching process is performed, what remain of the titanium layer  260  are titanium regions  260   a  and  260   b  on side walls of the temporary gate electrode region  120 . 
   Next, with reference to  FIG. 2D , in one embodiment, a dielectric layer  270  and a BPSG layer  275  are formed on top of the structure  200  of  FIG. 2C . More specifically, the dielectric layer  270  and the BPSG layer  275  can be formed by (i) depositing silicon nitride on top of the structure  200  of  FIG. 2C  resulting in the dielectric layer  270  and then (ii) depositing BPSG on top of the dielectric layer  270  resulting in the BPSG layer  275 . 
   Next, in one embodiment, a CMP process is performed on top of the structure  200  of  FIG. 2D  until the top surface  122  of the temporary gate electrode region  120  is exposed to the surrounding ambient resulting in the structure  200  of  FIG. 2E . After the CMP process is performed, what remain of the dielectric layer  270  are dielectric regions  270   a  and  270   b , and what remain of the BPSG layer  275  are BPSG regions  275   a  and  275   b.    
   Next, with reference to  FIG. 2E , in one embodiment, the temporary gate electrode region  120  is removed resulting in a trench  224  of  FIG. 2F . More specifically, the temporary gate electrode region  120  can be removed by a wet etching process. 
   Next, with reference to  FIG. 2F , in one embodiment, silicon dioxide on side walls and bottom walls of the trench  224  are removed such that the top surface  110 ′ of the substrate  110  and side walls of the titanium regions  260   a  and  260   b  are exposed to the surrounding ambient resulting in the structure  200  of  FIG. 2G . 
   Next, with reference to  FIG. 2H , in one embodiment, a gate dielectric layer  280  and an electrically conductive layer  285  are formed on top of the structure  200  of  FIG. 2G . The gate dielectric layer  280  can comprise Hf x Si y O z N w . The electrically conductive layer  285  can comprise tantalum nitride. The gate dielectric layer  280  and the electrically conductive layer  280  can be formed by (i) CVD or ALD of the Hf x Si y O z N w  on top of the structure  200  of  FIG. 2G  resulting in the gate dielectric layer  280  and then (ii) CVD or ALD of tantalum nitride on top of the gate dielectric layer  280  such that the trench  224  is completely filled with tantalum nitride resulting in the electrically conductive layer  285 . 
   Next, in one embodiment, a CMP process is performed on top of the structure  200  of  FIG. 2H  until the top surface  275 ′ of the BPSG regions  275   a  and  275   b  is exposed to the surrounding ambient resulting in the structure  200  of  FIG. 2I . After the CMP process is performed, what remains of the gate dielectric layer  280  is the gate dielectric region  280 , and what remains of the electrically conductive layer  285  is the electrically conductive region  285 . 
   Next, in one embodiment, the structure  200  is annealed at a temperature around 400-600° C. resulting in titanium of the regions  260   a  and  260   b  chemically reacting with Hf x Si y O z N w  of the gate dielectric region  280  resulting in the dielectric regions  295   a  and  295   b  of  FIG. 2J  which comprise Ti v Hf x Si y O z N w . Ti v Hf x Si y O z N w  is a low-K dielectric material. After the annealing of the structure  200  is performed, what remains of the gate dielectric region  280  is the gate dielectric region  280 ′. 
   In the embodiments described above, the material of the gate dielectric layer  280  ( FIG. 2H ) is Hf x Si y O z N w  and the material of the layer  260  ( FIG. 2B ) is titanium. In general, the material of the gate dielectric layer  280  and the material of the layer  260  can be selected such that (i) the material of the gate dielectric layer  280  is a high-K dielectric material (K&gt;4) and (ii) at a high temperature (e.g., around 400-600°), the material of the gate dielectric layer  280  and the material of the layer  260  chemically react with each other resulting in a low-K dielectric material (K&lt;4). 
   With reference to  FIG. 2J , the structure  200  shows a transistor having the gate electrode region  285 , the gate dielectric region  280 ′, the source/drain regions  116   a  and  116   b  and the channel  115 . The dielectric regions  295   a  and  295   b  can be referred to as spacer dielectric regions  295   a  and  295   b.    
   Next, in one embodiment, interconnect layers (not shown) are formed on top of the structure  200  to provide electrical access to the transistor of  FIG. 2J . 
   With reference to  FIGS. 2I and 2J , as described above, Hf x Si y O z N w  of the gate dielectric region  280  is converted to Ti v Hf x Si y O z N w  of the dielectric regions  295   a  and  295   b  which has a lower dielectric constant than Hf x Si y O z N w  of the gate dielectric region  280 . As a result, the fringing capacitances between the gate electrode region  285  and the source/drain regions  116   a  and  160   b  are reduced. 
   In the embodiments described above, the interconnect layers are formed on top of the structure  200  to provide electrical access to the transistor of  FIG. 2J . Alternatively, with reference to  FIG. 2J , before the interconnect layers are formed on top of the structure  200 , the dielectric regions  295   a  and  295   b  are removed resulting in trenches  295   a ′ and  295   b ′ of  FIG. 2K . More specifically, the dielectric regions  295   a  and  295   b  can be removed by a wet etching process. 
   Next, in one embodiment, the interconnect layers (not shown) are formed on top of the structure  200  of  FIG. 2K  to provide electrical access to the transistor of  FIG. 2K  such that the trenches  295   a ′ and  295   b ′ are not completely filled by solid material. As a result, the trenches  295   a ′ and  295   b ′ can still contain some spaces (not shown) that contain gases, vapors and/or vacuum. In one embodiment, these spaces are in direct physical contact with the gate electrode region  285 . These spaces can be in direct physical contact with the gate dielectric region  280 ′. 
   It should be noted that after the interconnect layers are formed, the dielectric constants of the materials that fill the trenches  295   a ′ and  295   b ′ (dielectric solid materials, gases, vapors, and/or vacuum) are lower than that of Ti v Hf x Si y O z N w  of the dielectric regions  295   a  and  295   b  of  FIG. 2J . Therefore, fringing capacitances between the gate electrode region  285  and the source/drain regions  116   a  and  116   b  are further reduced. 
   In the embodiments described above, the layer  190  ( FIG. 1N ) and the layer  260  ( FIG. 2B ) comprise Ti. Alternatively, each of the layers  190  and  260  can comprise Zirconium (Zr) or hafnium (Hf). 
   While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.