Abstract:
An apparatus for converting an analog signal to a digital signal comprising a first analog to digital converter for generating a first digital value from an analog value. A second analog to digital converter for generating a second digital value from the analog value. Logic for determining a correction factor for the second digital value based on a difference between the first digital value and the second digital value, wherein the logic updates the correction factor.

Description:
RELATED APPLICATIONS 
   This application claims priority to provisional U.S. application 61/086,266, filed Aug. 5, 2008, which is hereby incorporated by reference for all purposes. 

   FIELD OF THE INVENTION 
   The invention relates to analog to digital converters, and more particularly to nonlinear compensation in analog to digital converters that improves accuracy. 
   BACKGROUND OF THE INVENTION 
   Lower power and higher speed analog to digital converters can be obtained by using lower accuracy analog components. The accuracy can be recovered by digitally post-processing the output of the analog to digital converter. This invention describes a method to identify and correct for the nonlinearities and mismatches in the analog components. 
   SUMMARY OF THE INVENTION 
   In accordance with the present invention, an apparatus and method for nonlinear compensation in analog to digital converters are provided, which increased the accuracy of high speed analog to digital converters. 
   In accordance with an exemplary embodiment of the present invention, an apparatus for converting an analog signal to a digital signal is provided. The apparatus includes a first analog to digital converter for generating a first digital value from an analog value, such as a high accuracy digital value that is generated over a first time period. A second analog to digital converter generates a second digital value from the analog value, such as a lower accuracy digital value that is generated in less time than the first time period. Logic determines a correction factor for the second digital value based on a difference between the first digital value and the second digital value, wherein the logic updates the correction factor each time a new analog value is processed. 
   Those skilled in the art will further appreciate the advantages and superior features of the invention together with other important aspects thereof on reading the detailed description that follows in conjunction with the drawings. 

   
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       FIG. 1  is a diagram of a system for an adaptive analog to digital converter in accordance with an exemplary embodiment of the present invention; 
       FIG. 2  is a diagram of a system for an adaptive analog to digital converter in accordance with an exemplary embodiment of the present invention; 
       FIG. 3  is a diagram of a system for an four stage pipelined adaptive core in accordance with an exemplary embodiment of the present invention; 
       FIG. 4  is a diagram of a system of a four stage analog to digital converter with a polynomial nonlinear adaptive filter in accordance with an exemplary embodiment of the present invention; 
       FIG. 5  is a diagram of a system of a four stage analog to digital converter with a look-up table based nonlinear filter in accordance with an exemplary embodiment of the present invention; 
       FIG. 6  is a diagram of a system of a four stage analog to digital converter with a hybrid look-up table and adaptive nonlinear filter in accordance with an exemplary embodiment of the present invention; 
       FIG. 7  is a diagram of a system of a four stage analog to digital converter with a hybrid thermometer code correction and adaptive nonlinear filter in accordance with an exemplary embodiment of the present invention; and 
       FIG. 8  is a diagram of a system of a three stage analog to digital converter with adaptive hybrid thermometer code correction and vectorizer to implement the nonlinear adaptive filter in accordance with an exemplary embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
   In the description that follows, like parts are marked throughout the specification and drawings with the same reference numerals, respectively. The drawing figures might not be to scale and certain components can be shown in generalized or schematic form and identified by commercial designations in the interest of clarity and conciseness. 
     FIG. 1  is a diagram of a system  100  for an adaptive analog to digital converter in accordance with an exemplary embodiment of the present invention. System  100  uses an adaptive core to compensate for manufacturing variances in and non-linearity of the circuit components of system  100  to generate more accurate analog to digital conversion values. 
   System  100  can be implemented in hardware or a suitable combination of software and hardware, such as one or more discrete circuit components such as transistors and capacitors operating in conjunction with a digital signal processor, a field programmable gate array, an application specific integrated circuit or other suitable components. System  100  includes reference analog to digital converter  102 , which is a high accuracy analog to digital converter that operates at a first conversion speed. System  100  also includes adaptive core  104 , which includes a lower accuracy analog to digital converter stage that operates at a second conversion speed that is faster than the conversion speed of reference analog to digital converter  102 . The faster speed of adaptive core is obtained using lower cost and lower power components, but results in inaccurate analog to digital conversion processing. In order to improve the accuracy of adaptive core  104 , it is necessary to determine the error created by adaptive core  104  and to compensate for that error. 
   In order to compensate for the inaccuracy of the faster analog to digital conversion stage of the adaptive core, subtractor  106  is used to generate an error signal that is fed back to adaptive core  104 . Adaptive core  104  includes iterative logic that compensates the output of the high speed but inaccurate analog to digital converter of adaptive core  104  to yield an accurate conversion value that compensates for variances in and non-linearity of the analog to digital converter of adaptive core  104 . Because reference analog to digital converter  102  operates at a slower conversion rate than adaptive core  104 , the error signal is only valid at predetermined times, and the subtractor  106  or other suitable components of adaptive core  104  include buffers to store the converted analog signal from adaptive core  104  that corresponds to the converted analog signal from reference analog to digital converter  102 . Adaptive logic of adaptive core  104  is used to determine the errors generated by the components of adaptive core  104 , and to correct the generated digital codes to compensate for these errors. 
     FIG. 2  is a diagram of a system  200  for an adaptive analog to digital converter in accordance with an exemplary embodiment of the present invention. System  200  uses an adaptive core to compensate for manufacturing variances in and non-linearity of the circuit components of system  200  to generate more accurate analog to digital conversion values. 
   System  200  can be implemented in hardware or a suitable combination of software and hardware, such as one or more discrete circuit components such as transistors and capacitors operating in conjunction with a digital signal processor, a field programmable gate array, an application specific integrated circuit or other suitable components. System  200  includes reference digital to analog converter  202 , which is a high accuracy digital to analog converter that operates at a first conversion speed. System  200  also includes adaptive core  204 , which includes a lower accuracy analog to digital converter stage that operates at a second conversion speed that is faster than the conversion speed of reference digital to analog converter  202 . The faster speed of adaptive core is obtained using lower cost and lower power components, but results in inaccurate analog to digital conversion processing. In order to improve the accuracy of adaptive core  204 , it is necessary to determine the error created by adaptive core  204  and to compensate for that error. 
   In order to compensate for the inaccuracy of the faster analog to digital conversion stage of the adaptive core, subtractor  206  is used to generate an error signal that is fed back to adaptive core  204 . Adaptive core  204  includes iterative logic that compensates the output of the high speed but inaccurate analog to digital converter of adaptive core  204  to yield an accurate conversion value that compensates for variances in and non-linearity of the analog to digital converter of adaptive core  204 . Because reference digital to analog converter operates at a slower conversion rate than adaptive core  204 , the error signal is only valid at predetermined times, and the subtractor  206  or other suitable components of adaptive core  204  include buffers to store the converted analog signal from adaptive core  204  that corresponds to the converted analog signal from reference digital to analog converter  202 . Adaptive logic of adaptive core  204  is used to determine the errors generated by the components of adaptive core  204 , and to correct the generated digital codes to compensate for these errors. 
     FIG. 3  is a diagram of a stage of the analog to digital converter. An exemplary 4-bits per stage architecture is shown with 4 stages, but any number of bits or stages can also or alternatively be resolved. System  300  includes the lower resolution analog to digital converter  302 , which generates thermometer codes based on the voltage input. 
   In this exemplary embodiment, reference 4-bit analog to digital converter  302  may generate the following 14 digital thermometer codes, which represent the associated analog voltage input for an input voltage that can vary from −1.0 volts to 1.0 volts: 
                                                             Thermometer   Digital   Analog Output           code   Code   Of DAC       Input voltage   Generated by   Generated by   Generated by       range   302   312   306                                &lt;−13/14   00000000000000   −7   −1.0       −13/14 to −11/14   000000000000001   −6   −12/14       −11/14 to −9/14    000000000000011   −5   −10/14       −9/14 to −7/14   000000000000111   −4    −8/14       −7/14 to −5/14   000000000001111   −3    −6/14       −5/14 to −3/14   000000000011111   −2    −4/14       −3/14 to −1/14   000000000111111   −1    −2/14       −1/14 to 1/14    000000001111111   0   0        1/14 to 3/14   000000011111111   1      2/14       3/14 to 5/14   000000111111111   2      4/14       5/14 to 7/14   000001111111111   3      6/14       7/14 to 9/14   000011111111111   4      8/14        9/14 to 11/14   000111111111111   5     10/14       11/14 to 13/14   011111111111111   6     12/14         &gt;13/14   111111111111111   7     1.0                    
Randomizer  304  receives the thermometer codes and randomly reorders them. The randomizer may be disabled or bypassed. When bypassed, the thermometer code is used by the summing decode  312  to generate a digital code D representing the associated voltage range for that stage of the analog to digital converter. Alternatively, the output of the randomizer  304  is processed by a summing decode  312  to generate the digital code D. Digital to analog converter  306  generates an analog value based on the randomized thermometer code generated by analog to digital converter  302  and  304 . The analog value is designed to nominally be at the center of the input voltage range that corresponds to the thermometer code. For example, the analog outputs that are generated for the corresponding thermometer codes are shown in the above table. The digital to analog converter  306  in this exemplary embodiment is comprised of 14 unit elements. Exemplary unit elements can include unit capacitors, unit current cells or other suitable components. In this exemplary embodiment, unit capacitors are used. Each unit capacitor in the digital to analog converter  306  has a weight of exactly 1/14 in this exemplary embodiment. The digital to analog converter  306  generates an analog value based on the thermometer code by performing a weighted summation of the unit elements. A thermometer code of ‘0’ corresponds to a weight of −1 and a thermometer code of ‘1’ corresponds to a weight of 1 for the corresponding unit capacitor.
 
   The output of the digital to analog converter  306  is subtracted from the voltage input by the subtractor  308 , and the difference value is amplified by amplifier  310 . The output of the amplifier  310  is then processed by a subsequent stage when higher accuracy is desired. Thus, when high accuracy is required, each stage is used to generate an amplified analog voltage that is processed by subsequent stages to generate additional digital data representing the analog voltage input. 
   The analog to digital converter of the adaptive cores does not result in high accuracy conversion of the analog voltage input or the subsequent re-conversion of the thermometer code to an analog value. For example, due to capacitance value variations in the digital to analog converter or amplifier non-linearity, the output voltage for a stage might not equal the desired value. This would result in inaccurate conversion in subsequent stages. A number of different processes can be used to correct for the above errors, as described below. 
     FIG. 4  is a diagram of a system  400  of a four stage analog to digital converter with an adaptive filter in accordance with an exemplary embodiment of the present invention. Although four stages are shown, any suitable number of stages can be used to provide the desired analog to digital conversion accuracy. 
   System  400  uses a vectorizer  410  that receives the outputs D 1  through D 4  of the four stages ( 402 ,  404 ,  406 ,  408 ) and generates the higher order powers and cross products of those digital outputs. A nonlinear adaptive filter  412  applies a weighted combination or summation of the outputs produced by each stage, their higher order powers and cross products. 
   In one exemplary embodiment, a four stage analog to digital converter with outputs D 1 , D 2 , D 3 , and D 4  can utilize a vectorizer  412  that generates the following regressors: 
   2 nd  Order 
   D 1   2 , D 2   2 , D 3   2 , D 4   2 , D 2 ·D 3 , D 2 ·D 4 , D 3 ·D 4  . . . , 
   3 rd  Order 
   D 1   3 , D 2   3 , D 3   3 , D 4   3 , D 2   2 ·D 3 , D 2 ·D 3   2 , D 2 ·D 4   2 , D 3 ·D 4   2 , D 3   2 ·D 4 , D 2 ·D 3 ·D 4  . . . , 
   and 4 th  and higher orders powers and cross products. However, the total number of cross products can be reduced by selecting the cross products that have the greatest affect on the output, and by excluding the other cross products that have a negligible effect. The selection of cross products can be performed by running a number of conversion samples using all cross products during a design phase, and selecting the cross products that are found to have the greatest effect on the output. An additional advantage obtained by reducing the number of cross products is an increase in stability. The resulting set of efficient cross products (or regressors) for one exemplary four stage analog to digital converter is:
 
D 2   3 , D 3   3 , D 4   3 , D 2   2 ·D 3 , D 2 ·D 3   2 , D 3 ·D 4   2 , D 3   2 ·D 4  
 
which can be used to achieve up to 12-bit accuracy. Similar embodiments can be used for less or more stages, or when higher accuracy is desired.
 
   The regressors u k  are assigned to the cross products of the vectorizer  410  in accordance with the following relationships: 
   
     
       
             
             
             
           
         
             
                 
                 
             
             
                 
               Regressor 
               Definition 
             
             
                 
                 
             
           
           
             
                 
               u 1   
               D 1   
             
             
                 
               u 2   
               D 2   
             
             
                 
               u 3   
               D 3   
             
             
                 
               u 4   
               D 4   
             
             
                 
               u 5   
               D 2   3   
             
             
                 
               u 6   
               D 3   3   
             
             
                 
               u 7   
               D 4   3   
             
             
                 
               u 8   
               D 2   2  · D 3   
             
             
                 
               u 9   
               D 2  · D 3   2   
             
             
                 
               u 10   
               D 3  · D 4   2   
             
             
                 
               u 11   
               D 3   2  · D 4   
             
             
                 
                 
             
           
        
       
     
   
   Each regressor is weighted by a coefficient W k  and summed by the nonlinear filter  412  to generate the output x 1  given by 
   
     
       
         
           
             x 
             1 
           
           = 
           
             
               ∑ 
               
                 k 
                 = 
                 1 
               
               11 
             
             ⁢ 
             
               
                 W 
                 k 
               
               · 
               
                 u 
                 k 
               
             
           
         
       
     
   
   An error signal (e=y−x 1 ) is generated by the difference between the high speed and inaccurate analog to digital converter stages (x 1 ) and the low speed and accurate reference input (y) by the subtractor  414 . The coefficients W k  of the nonlinear adaptive filter  412  can be updated using the equation:
 
 W   k   (t+1)   =W   k   (t)   +μ*e   (t)   *u   k   (t)  for k=1, 2, . . . 11
 
where
 
   the estimation error e=y−x 1 , 
   y=the output from the low speed and accurate analog to digital converter, 
   x 1 =the digital estimate, 
   W k  is adapted such as to minimize the error, and 
   μ k  is a user determined step size which can be positive or negative. 
     FIG. 5  is a diagram of a system  500  of a four stage analog to digital converter  502 ,  504 ,  508 ,  510  with a look-up table based nonlinear filter in accordance with an exemplary embodiment of the present invention. Although four stages are shown, any suitable number of stages can be used to provide the desired analog to digital conversion accuracy. The randomizers in each stage are disabled in this exemplary embodiment. 
   System  500  includes look-up tables  510 ,  512 ,  514 ,  516  based on outputs D 1:4  from each stage as well as look-up tables based on the cross products of the outputs  518 ,  520 . The outputs of the table lookups are summed together. 
   The contents of the look-up tables L k    510 ,  512 ,  514 ,  516  include the higher-order powers and sums-of-powers of the outputs of the k th  stage. The contents of look-up tables L jk  include the cross-products and sums-of-cross-products of the j th  stage  518  and the k th  stage  520 . The output of the nonlinear filter  522  is given by the sum of the outputs of the look-up tables as described by the equation
 
 x   1   =L   1 ( D   1 )+ L   2 ( D   2 )+ L   3 ( D   3 )+ L   4 ( D   4 )+ L   23 ( D   2   ,D   3 )+ L   34 ( D   3   ,D   4 )
 
The nonlinear filter  522  corrects for nonlinearities in the digital to analog converters and amplifier nonlinearities in each stage.
 
   The error values generated by the difference  524  between the low speed accurate reference value y and the high speed inaccurate analog to digital conversion output x 1  are used to update the look-up tables in accordance with the equations
 
 L   k   (t+1) ( D   k   (t) )= L   k   (t) ( D   k   (t) )+μ* e   (t)  for k=1, 2, 3, 4
 
and
 
 L   jk   (t+1) ( D   j   (t)   ,D   k   (t) )= L   jk   (t) ( D   j   (t)   ,D   k   (t) )+μ* e   (t)  for ( j,k )=(2,3),(3,4)
 
   In this manner, look-up tables can be updated based on a user defined step size μ which can be positive or negative and the error signals to provide a high speed analog to digital converter that has an output that is corrected to compensate for nonlinearity and variance of circuit components. 
     FIG. 6  is a diagram of a system  600  of a four stage analog to digital converter  602 ,  604 , 606 ,  608  with a hybrid look-up table and adaptive filter in accordance with an exemplary embodiment of the present invention. Although four stages are shown, any suitable number of stages can be used to provide the desired analog to digital conversion accuracy. 
   A hybrid approach can be adapted that utilizes a combination of look-up tables and an adaptive nonlinear filter, as shown in system  600 . This hybrid approach can be used to avoid the need for look-up tables for cross products, which may tend to be larger in size. Table L 1    610  stores the nonlinear functions of D 1 . Similarly, Table L 2    612  includes the sum of all relevant linear and higher-order powers and sums thereof of the second stage output D 2 . Vectorizer  614  generates all other higher order powers and cross products. In one exemplary embodiment of a four stage analog to digital converter with outputs D 1 , D 2 , D 3 , and D 4 , vectorizer  614  can generate the following regressors: 
   2 nd  Order 
   D 3   2 , D 4   2 , D 2 ·D 3 , D 2 ·D 4 , D 3 ·D 4  . . . , 
   3 rd  Order 
   D 3   3 , D 4   3 , D 2   2 ·D 3 , D 2 ·D 3   2 , D 2 ·D 4   2 , D 3 ·D 4   2 , D 3   2 ·D 4 , D 2 ·D 3 ·D 4  . . . , 
   and other 4 th  and higher orders. However, the total number of cross products can be reduced by selecting key cross products with greatest affect on the output, as previously described. Also, stability can be improved as the number of cross products is reduced. Similar embodiments can be done for less or more stages. In one exemplary embodiment, the resulting set of high efficiency products for a four-stage analog to digital converter can be:
 
D 3   3 , D 4   3 , D 2   2 ·D 3 , D 2 ·D 3   2 , D 3 ·D 4   2 , D 3   2 ·D 4 .
 
Other suitable combinations of regressors can be also be used, and can also be selected for use with less or more stages. In this exemplary embodiment, each cross product (or regressor) is assigned a coefficient W k . The regressors u k  are assigned to the outputs of the vectorizer  614  in accordance with the following relationships:
 
                                           Regressor   Definition                           u 3     D 3             u 4     D 4             u 5     D 3   3             u 6     D 4   3             u 7     D 2   2  · D 3             u 8     D 2  · D 3   2             u 9     D 3  · D 4   2             u 10     D 3   2  · D 4                          
Each cross product is assigned a coefficient W k . The regressors are weighted and summed to create the output x 1  given by
 
   
     
       
         
           
             x 
             1 
           
           = 
           
             
               
                 L 
                 1 
               
               ⁡ 
               
                 ( 
                 
                   D 
                   1 
                 
                 ) 
               
             
             + 
             
               
                 L 
                 2 
               
               ⁡ 
               
                 ( 
                 
                   D 
                   2 
                 
                 ) 
               
             
             + 
             
               
                 ∑ 
                 
                   k 
                   = 
                   3 
                 
                 10 
               
               ⁢ 
               
                 
                   u 
                   k 
                 
                 ⁢ 
                 
                   w 
                   k 
                 
               
             
           
         
       
     
   
   An error signal e is generated by the difference between the high speed and inaccurate analog to digital converter stages x 1  and the low speed and accurate reference y by subtractor  618 , which generates e=y−x 1 . The error signal is used to adapt the Table look-ups L 1  and L 2  as follows
 
 L   1   (t+1) ( D   1   (t) )= L   1   (t) ( D   1   (t) )+μ* e   (t)  
 
 L   2   (t+1) ( D   2   (t) )= L   2   (t) ( D   2   (t) )+μ* e   (t)  
 
   The coefficients W k  of the nonlinear adaptive filter  616  can be updated using the equation:
 
 W   k   (t+1)   =W   k   (t)   +μ*e   (t)   *u   k   (t)  for k=3, 4, . . . 10
 
where μ k  is a user defined step size that can be positive or negative.
 
     FIG. 7  is a diagram of a system  700  of a four stage  702 ,  704 ,  706 ,  708  analog to digital converter with adaptive hybrid thermometer code correction  710  and  712  and vectorizer  714  to implement the nonlinear adaptive filter  716  in accordance with an exemplary embodiment of the present invention. Although four stages are shown, any suitable number of stages can be used to provide the desired analog to digital conversion accuracy. 
   System  700  uses a randomized thermometer code in each stage that distributes the thermometer code values so as to prevent over-reliance on a small group of unit capacitors of the digital to analog converter. For example, the 4-b thermometer code [0001] can be randomized as either [0010], [0100] or [1000], so as to ensure that effect on the analog voltages generated by the digital to analog converter caused by variances in the values of capacitors of the digital to analog converter are randomly distributed. More importantly, the digital estimates of the unit capacitors can be estimated independent of input amplitude statistics. Once the unit capacitors in the digital to analog converter of a stage are estimated, the digital output of the digital to analog converter in a stage can be accurately represented by 
             ∑     k   =   1     N     ⁢       T   k     ⁢     C   k             
where the T k  are the N thermometer codes and the C k  are the estimates of the N unit capacitances. This exemplary embodiment can be used to reproduce the effects of variations in the capacitor values in the operation of the digital to analog converter.
 
   In one exemplary embodiment of a four stage analog to digital converter with outputs D 1 , D 2 , D 3 , and D 4 , vectorizer  714  can generate the following regressors: 
   2 nd  Order 
   D 2   2 , D 3   2 , D 4   2 , D 2 ·D 3 , D 2 ·D 4 , D 3 ·D 4  . . . , 
   3 rd  Order 
   D 2   3 , D 3   3 , D 4   3 , D 2   2 ·D 3 , D 2 ·D 3   2 , D 2 ·D 4   2 , D 3 ·D 4   2 , D 3   2 ·D 4 , D 2 ·D 3 ·D 4  . . . , 
   and other 4 th  and higher orders. However, the total number of cross products can be reduced by selecting key cross products with greatest affect on the output, as previously described. Also, stability can be improved as the number of cross products is reduced. Other exemplary embodiments can also be used for less or more stages. In one exemplary embodiment, the set of high efficiency products for a four stage analog to digital converter can be:
 
D 2   3 , D 3   3 , D 4   3 , D 2   2 ·D 3 , D 2 ·D 3   2 , D 3 ·D 4   2 , D 3   2 ·D 4 .
 
   In this exemplary embodiment, the regressors u k  can be assigned to the outputs of vectorizer  714  in accordance with the following relationships: 
                                           Regressor   Definition                           u 3     D 3             u 4     D 4             u 5     D 2   3             u 6     D 3   3             u 7     D 4   3             u 8     D 2   2  · D 3             u 9     D 2  · D 3   2             u 10     D 3  · D 4   2             u 11     D 3   2  · D 4                          
Other exemplary embodiments can provided for less or more stages. Each cross product is assigned a coefficient W k . The products are weighted and summed by the nonlinear filter  716  to create the output x 1  given by
 
   
     
       
         
           
             x 
             1 
           
           = 
           
             
               
                 ∑ 
                 
                   k 
                   = 
                   1 
                 
                 N 
               
               ⁢ 
               
                 
                   T 
                   
                     1 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     k 
                   
                 
                 ⁢ 
                 
                   C 
                   
                     1 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     k 
                   
                 
               
             
             + 
             
               
                 ∑ 
                 
                   k 
                   = 
                   1 
                 
                 N 
               
               ⁢ 
               
                 
                   T 
                   
                     2 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     k 
                   
                 
                 ⁢ 
                 
                   C 
                   
                     2 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     k 
                   
                 
               
             
             + 
             
               
                 ∑ 
                 
                   k 
                   = 
                   3 
                 
                 11 
               
               ⁢ 
               
                 
                   u 
                   k 
                 
                 ⁢ 
                 
                   w 
                   k 
                 
               
             
           
         
       
     
   
   The error signal of system  700  is processed according to the equation e=y−x 1 . The coefficients W k  of the nonlinear adaptive filter  716  can be updated using the equation:
 
 W   k   (t+1)   =W   k   (t)   +μ*e   (t)   *u   k   (t)  for k=3, 4, . . . 11
 
The digital estimates of the unit capacitors C 1k  and C 2k  used in adaptive hybrid thermometer code correction  710  and  712  can be updated using the equations
 
 C   1k   (t+1)   =C   1k   (t)   +μ*e   (t)   *T   1k   (t)  for k=1, . . . N
 
 C   2k   (t+1)   =C   2k   (t)   +μ*e   (t)   *T   2k   (t)  for k=1, . . . N
 
Where μ is a user defined step size that can be positive or negative.
 
     FIG. 8  is a diagram of a system  800  of a three stage  802 ,  804 ,  806  analog to digital converter with adaptive hybrid thermometer code correction  810  and  812  and vectorizer  814  to implement the nonlinear adaptive filter  816  in accordance with an exemplary embodiment of the present invention. Although three stages are shown, any suitable number of stages can be used to provide the desired analog to digital conversion accuracy. 
   System  800  uses a randomized thermometer code in each stage that distributes the thermometer code values so as to prevent over-reliance on a small group of unit capacitors of the digital to analog converter. For example, the 4-b thermometer code [0001] can be randomized as either [0010], [0100] or [1000], so as to ensure that effect on the analog voltages generated by the digital to analog converter caused by variances in the values of capacitors of the digital to analog converter are randomly distributed. In addition, the digital estimates of the unit capacitors can be estimated independently of input amplitude statistics. Once the unit capacitors in the digital to analog converter of a stage are estimated, the digital output of the digital to analog converter in a stage can be accurately represented by 
             ∑     k   =   1     N     ⁢       T   k     ⁢     C   k             
where the T k  are the N thermometer codes and the C k  are the estimates of the N unit capacitances. This representation can be used to reproduce the effects of variations in the capacitor values in the operation of the digital to analog converter.
 
   In one exemplary embodiment of a three stage analog to digital converter with outputs D 1 , D 2 , and D 3 , vectorizer  814  can generates the following regressors: 
   2 nd  Order 
   D 2   2 , D 3   2 , D 2 ·D 3 , . . . , 
   3 rd  Order 
   D 2   3 , D 3   3 , D 2   2 ·D 2 ·D 3   2 , . . . , 
   and other 4 th  and higher orders. However, the total number of cross products can be reduced by selecting key cross products with greatest affect on the output, as previously described. Also, stability can be improved as the number of cross products is reduced. Similar embodiments can be done for less or more stages. In one exemplary embodiment, the resulting set of high efficiency products can be:
 
D 2   3 , D 3   3 , D 2   2 ·D 3 .
 
In this exemplary embodiment, the regressors u k  are assigned to the outputs of vectorizer  714  in accordance with the following relationships:
 
                                           Regressor   Definition                           u 3     D 3             u 4     D 2   3             u 5     D 3   3             u 6     D 2   2  · D 3                          
Other suitable embodiments can be used for less or more stages. Each cross product is assigned a coefficient W k . The products can be weighted and summed by nonlinear filter  816  to create the output x 1  given by
 
   
     
       
         
           
             x 
             1 
           
           = 
           
             
               
                 ∑ 
                 
                   k 
                   = 
                   1 
                 
                 N 
               
               ⁢ 
               
                 
                   T 
                   
                     1 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     k 
                   
                 
                 ⁢ 
                 
                   C 
                   
                     1 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     k 
                   
                 
               
             
             + 
             
               
                 ∑ 
                 
                   k 
                   = 
                   1 
                 
                 N 
               
               ⁢ 
               
                 
                   T 
                   
                     2 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     k 
                   
                 
                 ⁢ 
                 
                   C 
                   
                     2 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     k 
                   
                 
               
             
             + 
             
               
                 ∑ 
                 
                   k 
                   = 
                   3 
                 
                 11 
               
               ⁢ 
               
                 
                   u 
                   k 
                 
                 ⁢ 
                 
                   w 
                   k 
                 
               
             
           
         
       
     
   
   The error signal of system  800  is processed according to the equation e=y−x 1 . The coefficients W k  of nonlinear adaptive filter  816  can be updated using the equation:
 
 W   k   (t+1)   =W   k   (t)   +μ*e   (t)   *u   k   (t)  for k=1, . . . 11
 
The digital estimates of the unit capacitors C 1k  and C 2k  in adaptive hybrid thermometer code correction  810  and  812  can be updated using the equations
 
 C   1k   (t+1)   =C   1k   (t)   +μ*e   (t)   *T   1k   (t)  for k=1, . . . N
 
 C   2k   (t+1)   =C   2k   (t)   +μ*e   (t)   *T   2k   (t)  for k=1, . . . N
 
Where μ is a user defined step size that can be positive or negative.
 
   While certain exemplary embodiments have been described in detail and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention. It will thus be recognized to those skilled in the art that various modifications may be made to the illustrated and other embodiments of the invention described above, without departing from the broad inventive scope thereof. It will be understood, therefore, that the invention is not limited to the particular embodiments or arrangements disclosed, but is rather intended to cover any changes, adaptations or modifications which are within the scope and the spirit of the invention defined by the appended claims.