Abstract:
A significant reduction of the amplitude of the transient response is obtained by keeping a low dropout regulator circuit in a closed loop condition. This is achieved by manipulation of the reference voltage level when an open loop condition arises due to a falling input voltage. In this case, the reference voltage level is tracked with the input voltage level, keeping the output voltage regulated. As a consequence, the power pass element of the regulator is not forced into the linear region (in the case of a MOSFET) or deep saturation (in the case of a bipolar transistor).

Description:
TECHNICAL FIELD 
       [0001]    The present invention relates to voltage regulator circuits. 
       BACKGROUND 
       [0002]    Voltage regulators such as low dropout (LDO) voltage regulators are widely used devices in electronic systems. Such circuits are usually applied in the voltage supply chain to provide a precise and time-stable supply voltage to the supplied system. There exist strong requirements on the electrical characteristics of regulator circuits. The main task for the voltage regulator is to keep the output voltage (VOUT) regulated at a nominal voltage level. This must be assured in both steady state and transient conditions. If the voltage VOUT goes out of regulation, this can lead to malfunction or even destruction of the supplied system. If the input voltage VIN of the LDO regulator changes over a wide range with a high slew rate, the output voltage VOUT can show different transient response products—for example, overshoots, undershoots. The amplitude of such transient response products depends on the regulator dynamic characteristics. This behavior is usually called the line transient response. It is beneficial to improve the operating characteristic because this will increase the overall regulator capability of keeping the output voltage VOUT constant. 
         [0003]    LDO voltage regulators are usually built as feedback regulation systems. The circuit senses an error between the output voltage VOUT and a reference voltage (VREF), and after sufficient multiplication of the error the circuit drives a power pass (transistor) element with an amplified signal. From principle there is always some error between the VOUT and VREF, but because of high gain, the impact on the output voltage VOUT is negligible. Usually the precision of the output voltage VOUT level is impacted much more by an offset of the error amplifier and by the precision of the voltage reference. In steady state, when a supply voltage (VIN) level and the load current (ILOAD) are fixed, the regulator is able to provide a stable output voltage VOUT level. The situation is more problematic when VIN and/or ILOAD are changing, in particular when the change is very fast (for example, due to a transient condition). The LDO regulator as a real electronic circuit has a characteristic response time given by the charge stored inside the system and by the mobility of the charge carriers. For this reason the system is not able to react in an infinitely short time. This is represented as the line/load transient response of the LDO which can be seen on the VOUT waveform as under/over shoots around the nominal VOUT level. The amplitude of the transient response depends on the amplitude of the VIN, the ILOAD stimuli and the slew rate. Small and slow changes may generate relatively small VOUT transients; fast changes with high amplitude may generate relatively large VOUT transients (which may exceed safe limits). 
         [0004]    The LDO regulator is known to operate in two conditions depending on the VIN level. If the VIN level is sufficiently in excess of the nominal VOUT voltage, the LDO regulator operates to regulate VOUT at a constant level. If the VIN level drops close to or even below the nominal VOUT voltage, however, the LDO regulator is not able to provide a constant VOUT level and the output voltage drops down. The first condition is referred to in the art as “closed loop” and the second condition is referred to as “open loop.” In the open loop condition, the LDO regulator is not operating as a voltage regulator, per se, but rather behaves like a switch with some characteristic resistance causing some minimum dropout voltage VDROP=VIN−VOUT=ILOAD*RDSON (wherein RDSON is the on-resistance of the drive transistor). The transition between the closed loop condition and the open loop condition is represented by a significant change of operating points inside the LDO circuitry. If the change between the modes is due, for example, to an extreme and very fast VIN change, the circuit will accommodate this change over a short time period and the consequence of this effect is an extreme transient response overshoot and/or undershoot on the output voltage. 
         [0005]    The dropout condition itself is not problematic for the LDO regulator, but the transition from the dropout (open loop) to the closed loop condition is. The transition is usually forced by a rising transition of the VIN level. The regulator has to react in a fast way to recover the VOUT regulation. Because there are significant charges stored inside the circuit, it is not possible to recover the regulation in an infinitely short time. The result of this can be a severe overshoot on the regulator output. There is a need in the art to improve significantly this response. 
         [0006]    Reference is now made to  FIG. 1  showing a conventional voltage regulator circuit  10  of the low drop out (LDO) type. The circuit  10  is of a known configuration including a bandgap voltage reference V 1  generator, a LDO OPAMP I 1 , a power pass (P-channel MOSFET transistor) element M 1 , a feedback network (RX and R 2 ), and an output storage capacitor COUT. The circuit  10  operates to provide a constant VOUT level, independent of the input voltage VIN level which can usually change over a wide range. The circuit represents a feedback system, driven by an error voltage VERR=VFB−VREF (where VFB is the feedback voltage provided by the resistive divider RX and R 2 ). The error voltage VERR is amplified by the OPAMP M 1  and a resulting driving voltage (VGATE) is applied to the gate of the power MOSFET M 1 . If the error voltage VERR is low, the output voltage VOUT is close to the nominal level and the feedback loop is closed. This condition is achieved when VIN is sufficiently high with respect to the nominal VOUT level and ILOAD. In this condition the operating point of the circuit nodes is set to a normal level and it changes only slightly depending on external conditions (for example, ILOAD, VIN and temperature). However, if the input voltage VIN drops too much such that the LDO regulator is not able to keep the output voltage VOUT constant, the feedback loop goes into the open loop (dropout) condition. Because the error voltage VERR in this case rises too high, the OPAMP I 1  generates the voltage VGATE to try to open the power MOSFET as much as possible by overdriving its VGS (gate to source voltage). The VDROP level depends on the RDSON of the power MOSFET and the load current in accordance with the following equation: 
         [0000]        V DROP= RDSON*I LOAD  (1)
 
         [0007]    Furthermore, in the dropout condition different nodes of the OPAMP internal structure are pushed into a saturation state. If a fast rising VIN transition subsequently occurs in this condition, forcing the structure from the open loop to the closed loop condition, the circuit structure can have difficulty in discharging the power MOSFET VGS and recovering the normal regulating state of the OPAMP. This is usually accompanied by overshoot on the output voltage VOUT. 
       SUMMARY 
       [0008]    A voltage regulator can work in two different operating modes: closed loop and open loop. Usually the regulator is designed to operate in the closed loop condition, keeping the output voltage regulated. In many applications, however, this condition is not always maintained and the regulator can pass from closed loop to the open loop condition when the supply voltage drops close to or below the LDO output regulated voltage. In this condition, the power MOSFET is fully turned on and the regulator loses all rejection performance. This is represented by significant operating point changes inside the regulator circuit. Because there are components inside the circuit storing significant charge (i.e., the power MOSFET is fully turned on with maximum allowed VGS), it is not possible to make this change in a short time. As a consequence the standard voltage regulator generates significant over/undershoots (spikes) during the transition from closed loop to open loop and vice versa. 
         [0009]    Embodiments disclosed herein reduce significantly such spikes by keeping the regulator always in the closed loop condition. This is accomplished by altering the reference voltage of the regulator when the supply level is falling so as to cause the output voltage to drop below the nominal level. In this condition, the reference level tracks with the falling supply level. As a consequence, the minimum difference between supply and the output voltage (the dropout voltage) is not given by the power pass element characteristic but is instead an internally predefined difference between the supply level and the reference level. This difference can be made load current dependent for achieving characteristic similar to a standard voltage regulator. 
         [0010]    The drawbacks of the prior art are addressed by reducing the line transient response of the LDO regulator. This accomplished by manipulation of the reference voltage VREF level when the device is in dropout condition. The manipulation is done with the goal of keeping the regulation loop inside the closed loop condition. If the closed loop condition is maintained the changes of the potentials are reduced and it is not necessary to move significant charge inside the circuit during the input voltage VIN transitions. 
         [0011]    To improve the line regulation transient response, but also to maintain the standard dropout characteristic of the LDO regulator, the VREF manipulation is driven by both VIN and ILOAD. In particular, in the dropout condition the VREF level is tracked with the VIN level whereas the voltage difference between VIN and VOUT (VDROP) is ILOAD dependent. In normal closed loop condition the VREF level is kept constant, independent of any external variable. 
         [0012]    If the input voltage VIN drops, forcing the regulator into the dropout condition, the VREF level is forced down to maintain the regulation. So, the VREF is tracked with the VIN level when necessary. The voltage difference between VIN and VREF level defines the VDROP, because if the regulation is maintained, the VREF is equal to VOUT. 
         [0013]    For achieving a dropout characteristic similar to the standard LDO regulator, where the power MOSFET behaves like a resistor, the voltage difference between VIN and VREF is made load current dependent. 
         [0014]    Generally speaking, the solution herein allows for a significant reduction of the amplitude of the transient response by keeping the LDO circuits in the closed loop condition. This is achieved by manipulation of the VREF level when an open loop condition due to falling input voltage VIN should occur. In this case, the VREF level is tracked with the VIN level, keeping the output voltage VOUT regulated. As a consequence, the power pass element is not forced into the linear region (in the case of a MOSFET) or deep saturation (in the case of a bipolar transistor). 
         [0015]    In an embodiment, a voltage regulator circuit comprises: an input node configured to receive an input voltage; a power transistor having a conduction path coupled between the input node and an output node; an amplifier having an output driving a control terminal of the power transistor and a first input coupled to the output node to form a regulator feedback loop, said amplifier further having a second input; and a voltage generator supplied by the input voltage and configured to generate a variable reference voltage applied to the second input of the amplifier, said variable reference voltage varying correspondingly with changes in the input voltage. 
         [0016]    In an embodiment, a voltage regulator circuit comprises: an input node configured to receive an input voltage; a power transistor having a conduction path coupled between the input node and an output node; a current sensing circuit configured to sense current flowing in the conduction path of the power transistor and generate a sense current; an amplifier having an output driving a control terminal of the power transistor and a first input coupled to the output node to form a regulator feedback loop, said amplifier further having a second input; and a voltage generator supplied by the input voltage and configured to generate a variable reference voltage applied to the second input of the amplifier in response to said input voltage and the sense current. 
         [0017]    In an embodiment, a method for operating a voltage regulator circuit comprises: determining an error between a feedback voltage and a reference voltage; driving a control terminal of a power transistor with a control voltage derived from the determined error to generate an output voltage, wherein said feedback voltage is derived from the output voltage; supplying an input voltage to the power transistor; and generating said reference voltage to vary correspondingly with changes in the input voltage. 
         [0018]    In an embodiment, a method for operating a voltage regulator circuit comprises: determining an error between a feedback voltage and a reference voltage; driving a control terminal of a power transistor with a control voltage derived from the determined error to generate an output voltage, wherein said feedback voltage is derived from the output voltage; sensing a current flowing through the power transistor; and varying the reference voltage in response to change in the sensed current. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0019]    For a better understanding, preferred embodiments thereof are now described, purely by way of non-limiting example, with reference to the attached drawings, wherein: 
           [0020]      FIG. 1  is a circuit diagram for a conventional voltage regulator circuit of the low drop out (LDO) type; 
           [0021]      FIG. 2  is a circuit diagram for a voltage regulator circuit of the LDO type with a dropout control loop; 
           [0022]      FIG. 3  illustrates the dropout voltage dependence on the load current for the circuits of  FIGS. 1 and 2 ; 
           [0023]      FIG. 4  illustrates a comparison between the line transient responses of the circuit of  FIGS. 1 and 2 ; 
           [0024]      FIG. 5  illustrates VOUT behavior during the VIN rising transient (from dropout to regulation) for different values of the RX resistor in the circuit of  FIG. 2 ; 
           [0025]      FIG. 6  plots the amplitude of the VOUT overshoot different values of the RX resistor in the circuit of  FIG. 2 ; 
           [0026]      FIG. 7  is a circuit diagram for a voltage regulator circuit of the LDO type with a dropout control loop; and 
           [0027]      FIG. 8  is a circuit diagram for a voltage regulator circuit of the LDO type with a dropout control loop. 
       
    
    
     DETAILED DESCRIPTION 
       [0028]    Reference is now made to  FIG. 2  showing a voltage regulator circuit  20  of the LDO type with a dropout control loop  22 . The circuit  20  includes a reference voltage VREF generator, an OPAMP I 2  and a power pass (transistor) element M 4 . The reference voltage VREF generator is formed by current source I 1 , transistor M 1 , transistor M 2 , zener diode D 1  and resistor RX. Transistor M 1  is in a diode-connected configuration in series with current source I 1 . Transistor M 2  is connected to transistor M 1  in a current mirroring configuration and further connected at its drain to zener diode Z 1  and the inverting input of the OPAMP (i.e., the source-drain or conduction path of transistor M 2  is coupled to the non-inverting input of the OPAMP I 1 ). To sense the LDO output current (IOUT), MOSFET M 3  which is a scaled copy of transistor M 4  is used (transistor M 3  comprising a gate and drain connected to the gate and drain of the power MOSFET M 4 ; the scaling ratio of M 4 :M 3  may, for example, comprise 1000:1). The source of transistor M 4  is connected to receive the input voltage VIN with the drain out transistor M 4  coupled to the output node (i.e., the source-drain or conduction path of transistor M 4  is coupled between the input node and output node). The source of transistor M 3  is connected to the source terminals of transistors M 1  and M 2  and the drain of transistor M 3  is coupled to output node (i.e., the source-drain or conduction path of transistor M 3  is coupled between an intermediate node at the source terminals of transistors M 1  and M 2  and the output node). The transistor M 3  accordingly generates a sense current ICOPY at the intermediate node according to the current IPOWER flowing through the transistor M 4 . The resistor RX is connected between VIN and the intermediate node at the source terminals of transistors M 1  and M 2 . The drains of transistors M 3  and M 4  are connected to the output terminal and to the non-inverting input of the OPAMP I 2  to form the feedback loop for regulation. 
         [0029]    The LDO regulator  20  operates in two distinct conditions: a closed loop (regulation) condition and an open loop (dropout) condition. In the closed loop condition, the input voltage VIN is sufficiently high to guarantee a regulated output voltage VOUT. In the open loop condition, the input voltage VIN is lower than a certain limit and the LDO circuit  20  is not able to keep the output voltage VOUT at the nominal level. This circuit state represents the dropout condition, where the VOUT is tracked with the VIN. The difference between VIN and VOUT is referred to as the dropout voltage VDROP. More specifically: 
         [0000]        V DROP&gt; I OUT* RDSON   M4   (2)
 
         [0000]    This condition is a prerequisite for proper operation of circuit  20  and the production of an effective line transient response improvement. 
         [0030]    The circuit  20  exhibits a difference in comparison to the circuit  10  of the prior art because the voltage VDROP is defined by the reference generator instead of the power MOSFET RDSON. The VDROP for circuit  20  can be expressed as: 
         [0000]        V DROP= V DROP M2   +VX   (3)
 
         [0000]    wherein VX is the voltage drop across resistor RX and VDROP M2  is the voltage drop across the transistor M 2  representing the minimum VDS (voltage drain to source) of transistor M 2  and is given by equation: 
         [0000]        V DROP M2   =I 2 *RDSON   M2   (4)
 
         [0031]    To make the dropout characteristic of circuit  20  similar to that of a standard LDO circuit like that shown in  FIG. 1 , the resistor RX is used in cooperation with the copy MOSFET M 3  to form the dropout control loop  22 . Because the current IX flowing through resistor RX changes with the IOUT current, the VX voltage will also follow the same trend: 
         [0000]        VX=RX *( I COPY+ I 1+ I 2)  (5)
 
         [0000]    wherein the current I 1  is the current though transistor M 1  (i.e., the current of current source I 1 ) and the current I 2  is the current through transistor M 2 . 
         [0032]    At significant load currents the contribution of the I 1  and I 2  currents can be neglected. Then: 
         [0000]        VX=RX*I COPY  (6)
 
         [0000]    wherein the current ICOPY is the current through the copy transistor M 3 . 
         [0033]    Combining above equations produces: 
         [0000]        V DROP=( RX*I COPY)+( I 2 *RDSON   M2 )  (7)
 
         [0034]    It will accordingly be noted from this equation that the voltage VDROP is a linear function of the ICOPY current. But for the overall LDO regulator, the VDROP dependence on the IPOWER current has a higher importance. It is not linear because the ratio between IPOWER and ICOPY is not linear, caused by a voltage drop on resistor RX. At low IPOWER currents the function is close to linear but at higher currents a square root content significantly impacts the ratio. This function is graphically shown in  FIG. 3  which illustrates the dropout voltage dependence on the load current. The functions for both the prior art circuit  10  and the circuit  20  of  FIG. 2  are shown for comparison purposes in  FIG. 3 . For the circuit  10 , the dependence is linear because of the resistive nature of the power MOSFET channel in the linear region. In the circuit  20  of  FIG. 2 , however, the dropout curve is not given by the power MOSFET electrical characteristic, but is instead given by the control loop  22  influencing the reference voltage VREF level. The dropout characteristic of the circuit  20  exhibits a square root content because of the serial combination of the VGS of transistor M 3  and the voltage VX. Because the feedback loop in circuit  20  is not interrupted in the dropout condition, the VOUT=VREF equality is maintained. For avoiding of the power MOSFET deep VGS overdrive, the dropout voltage of the circuit  20  is higher in comparison to the circuit  10  of  FIG. 1 . 
         [0035]    The voltage VDROP defined by the VREF generator is set to be higher than the voltage VDROP defined by the power MOSFET M 4  (equation 2). This assures that when VIN drops (forcing the LDO into the dropout condition) the OPAMP stays in the normal operating point for regulating the output voltage VOUT. When the input voltage VIN increase transition subsequently occurs, the OPAMP has no difficulty to keep the output voltage VOUT regulated without any significant overshoot. A comparison between the line transient responses of the circuit  10  of  FIG. 1  and the circuit  20  of  FIG. 2  is shown in  FIG. 4 , where VIN, VOUT and VGS (gate-to-source voltage of the power MOSFET) waveforms are plotted. 
         [0036]    The input voltage VIN transient is chosen to drive the voltage regulator from open loop to closed loop condition. In the circuit  10  of  FIG. 1 , the VOUT response is represented by a large overshoot over the nominal regulated level. For the circuit  20  of  FIG. 2 , however, the overshoot amplitude is relatively small. From the waveforms of  FIG. 4 , the behavior of the power MOSFET VGS is evident. In the circuit  10  of  FIG. 1 , the power MOSFET is forced into the linear region with a high VGS overdrive. However, in the circuit  20  of  FIG. 2 , the power MOSFET is kept in the saturation region without the VGS overdrive. 
         [0037]    At time 10 ms it will be noted that a fast input voltage VIN rising transient occurs. The reaction of the circuit  10  of  FIG. 1  presents a severe overshoot on the output voltage VOUT because before the transient event the LDO regulator was in the open loop condition with VGS charged to almost 3.5V. The reaction of the circuit  20  of  FIG. 2 , however, presents a substantially smaller VOUT overshoot because the VGS before the event was kept at value below 1V and the OPAMP closed loop operating condition was maintained. 
         [0038]    Reference is now made to  FIG. 5  showing the VOUT behavior during the VIN rising transient (from dropout to regulation) for different values of the RX resistor. It will be noted that relatively higher values of resistance for the resistor RX give lower amplitudes of the VOUT overshoot. The amplitude of the VOUT overshoot is analyzed in the plot on  FIG. 6 . The dependence can be approximated by a 1/x function. An optimal resistance value for the resistor RX can be selected by the circuit designer as a tradeoff between the VOUT overshoot and the VDROP voltage. 
         [0039]    Reference is now made to  FIG. 7  showing a voltage regulator circuit  30  of the LDO type with a dropout control loop  32 . The circuit  30  includes a reference voltage VREF generator, an OPAMP I 1  and a power pass (transistor) element M 5 . The reference voltage VREF generator is formed by transistor M 1 , transistor M 2 , transistor M 3 , transistor Q 1 , transistor Q 2  and resistors R 2 -R 6 . Transistor M 2  is in a diode-connected configuration in series with transistor Q 2 . Transistor M 1  is connected to transistor M 2  in a current mirroring configuration and is further connected to transistor Q 1 . Transistors Q 1  and Q 2  share a common base electrode connection to a resistive voltage divider formed by resistors R 2  and R 3 . The emitter of transistor Q 1  is coupled to a reference voltage node (GND) through series connected resistors R 4  and R 5 . The emitter of transistor Q 2  is connected the series connection node between resistors R 4  and R 5 . The transistor M 3  has a gate connection to the series connection node between transistors M 1  and Q 1 . A drain of transistor M 3  is connected to the resistive voltage divider formed by resistors R 2  and R 3 . A resistor RX is coupled between the input voltage VIN and the source of transistor M 3 . 
         [0040]    To sense the LDO output current (IOUT), MOSFET M 4  which is a copy of transistor M 5  is used (transistor M 4  comprising a gate and drain connected to the gate and drain of the power MOSFET M 5 ; the scaling ratio of M 5 :M 4  may, for example, comprise 1000:1). The source of transistor M 5  is connected to receive the input voltage VIN. The source of transistor M 4  is connected to the source terminal of transistor M 3  at resistor RX. The drains of transistors M 3  and M 4  are connected to the output terminal and to the non-inverting input of the OPAMPL I 1  to form the feedback loop for regulation. The resistor R 6  is coupled between the drain of transistor M 3  and the inverting input of the OPAMP I 1 . 
         [0041]    The circuit components Q 1 , Q 2 , M 1 , M 2 , M 3 , R 4 , R 5 , R 2 , R 3  and RX form a bandgap reference voltage generator have a circuit configuration and operation that is well known to those skilled in the art. The resistor R 6  and shunt capacitor CBP form a low pass filter circuit which helps to reduce possible glitches, improve supply voltage rejection and reduce noise. The remainder of the circuit  30  corresponds to the circuit  20  of  FIG. 2 . The function of resistor RX together with the copy MOSFET M 4  (forming the dropout control loop  32 ) is the same as with loop  22  in the circuit  20  of  FIG. 2 . The bandgap reference voltage generator is equipped with a feedback network formed by the resistive voltage divider R 2  and R 3  that guarantees natural bandgap voltage multiplication to the required VREF level. Also in this circuit  30  the VOUT=VREF equality is always maintained by the regulation loop formed by OPAMP I 1  and the power MOSFET M 5 . 
         [0042]    In order to achieve the expected line transient response in the circuit  30 , it is necessary to design the bandgap generator to have a fast line transient response. The circuit designer must take in account the fact that the bandgap generator can pass to open loop condition when VIN is not sufficient to guarantee regulation of the reference voltage VREF. In this dropout condition the VGS of the bandgap pass element M 3  is overdriven to a maximum possible value. But guaranteeing a fast recovery of the bandgap reference is much easier than guaranteeing a fast recovery for the OPAMP I 1  and the large power MOSFET M 5 . This is because the charge stored in relatively smaller bandgap reference components is much less than the charge stored in the OPAMP I 1  and the power MOSFET M 5 . For this reason, the main feedback loop has to be always kept in regulation as was described above in connection with the circuit  20  of  FIG. 2 . For the circuit  30 , the electrical characteristics shown in  FIG. 3 ,  FIG. 4 ,  FIG. 5  and  FIG. 6  relative to the circuit of  FIG. 2  are equally valid. 
         [0043]    Reference is now made to  FIG. 8  showing a voltage regulator circuit  40  of the LDO type with a dropout control loop  42 . The circuit  40  includes a reference voltage VREF generator, an OPAMP I 2  and a power pass (transistor) element M 3 . The reference voltage VREF generator is formed by transistor M 1 , OPAMP I 1  and resistors R 2 -R 3 . A bandgap reference voltage generator provides a bandgap voltage VBG. The reference voltage VREF is not provided directly from the bandgap voltage generator V 1  (compare to  FIG. 7 ), but rather is provided using a voltage multiplier circuit formed by OPAMP I 1 , MOSFET M 1  and resistors RX, R 2  and R 3 . The bandgap voltage is applied to a non-inverting input of the OPAMP I 1 . Transistor M 1  has a gate terminal coupled to the output of the OPAMP I 1 . A resistive voltage divider formed by resistors R 2 /R 3  is coupled between the drain of transistor M 1  and a reference voltage node (GND). A series connection node between resistors R 2  and R 3  is coupled to the inverting input of the OPAMP 
         [0044]    To sense the LDO output current (IOUT), MOSFET M 2  which is a copy of transistor M 3  is used (transistor M 2  comprising a gate and drain connected to the gate and drain of the power MOSFET M 3 ; the scaling ratio of M 3 :M 2  may, for example, comprise 1000:1). The source of transistor M 3  is connected to receive the input voltage VIN. The source of transistor M 2  is connected to the source terminal of transistor M 1  at resistor RX. The drains of transistors M 2  and M 3  are connected to the output terminal and to the non-inverting input of the OPAMPL I 2  to form the feedback loop for regulation. The resistor R 4  is coupled between the drain of transistor M 1  and the inverting input of the OPAMP I 2 . The resistor R 4  and shunt capacitor CBP form a low pass filter circuit which helps to reduce possible glitches, improve supply voltage rejection and reduce noise. 
         [0045]    The feedback loop of the LDO regulator is formed by OPAMP I 2  and MOSFETs M 2 , M 3  in the same configuration as with the circuits  20  and  30 . The purpose of the VREF voltage multiplier circuit is to amplify the bandgap voltage VBG to the required reference voltage VREF level equal to the nominal VOUT level. The resistor RX functions in cooperation with the MOSFET M 2  to form the dropout control loop  42  (like loops  22  and  32 ) which protects the feedback regulation loop (OPAMP I 2  and MOSFET M 3 ) from the open loop condition. 
         [0046]    An excess drop of the input voltage VIN forces the LDO regulator into the dropout condition, but the reference voltage VREF will correspondingly drop sufficiently down to a level which will keep the main feedback loop in the regulation. In this operating condition, the VREF multiplier loop (OPAMP I 1 , MOSFET M 1  and feedback divider R 2 , R 3 ) transitions into the open loop condition. But because the size of components and corresponding charge stored is much smaller compared to the main feedback loop, the recovery from the open loop to closed loop condition is much faster. Possible glitches during the operation are filtered by the RC filter formed by resistor R 4  and capacitor CBP. For the circuit  40 , the electrical characteristics shown in  FIG. 3 ,  FIG. 4 ,  FIG. 5  and  FIG. 6  relative to the circuit of  FIG. 2  are equally valid. 
         [0047]    Although the regulator circuits are illustrated and described in connection with a MOSFET implementation, it will be understood that the disclosure is equally applicable to regulator circuits implemented in bipolar technology. Furthermore, the polarity of the transistor devices is by way of example only, it being understood that the circuits could alternatively be implemented with opposite polarity devices. 
         [0048]    The foregoing description has provided by way of exemplary and non-limiting examples a full and informative description of the exemplary embodiment of this invention. However, various modifications and adaptations may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims. However, all such and similar modifications of the teachings of this invention will still fall within the scope of this invention as defined in the appended claims.