Abstract:
High speed data transmission schemes often use differential lines to reduce the effect of noise on the data signal. Unfortunately, the signal propagation on the positive and negative lines may be different, which leads to a signal skew problem. This document describes a novel way of compensating for differential line skew in data transmission lines.

Description:
RELATED APPLICATIONS  
       [0001]     This application claims priority under 35 U.S.C. §119(e) to provisional application No. 60/507,606 filed on Sep. 30, 2003 titled “Adaptive Per-Pair Skew Compensation Method for Extended Reach Differential Transmission.” 
     
    
     FIELD  
       [0002]     The invention relates to data transmission, and, more specifically, to skew between differential transmission lines, which may be shielded or unshielded.  
       BACKGROUND  
       [0003]     Differential transmission lines are used in high-speed data communication in order to reduce the effect of electrical interference on the signal. A differential transmission line usually consists of a pair of wires, one positive and one negative. Ideally the signal propagation in the positive and negative wires is the same with respect to the shield or ground. This results in a signal pulse that has a minimum dispersion (growth in width).  
         [0004]      FIG. 1  shows graphs of voltage vs. time for the positive and negative signals  102 ,  104 . The positive signal  102  has a signal peak at time t=t p . The negative signal  104  has a signal peak at time t=t n . In this case, t p =t n . A differential signal  108  that results from the two signals running through a subtracter  106  has a small dispersion and large voltage peak.  
         [0005]      FIG. 2  is similar to that shown in  FIG. 1 , except that the positive and negative signals  202 ,  204  have a skew with respect to each other. In this case, t p  does not equal t n . The differential signal  208 , as seen as the output of the subtracter  206 , has a larger dispersion and lower peak voltage compared to that shown in  FIG. 1 . One skilled in the art will quickly recognize that the differential signal  108  in  FIG. 1  is much more desirable than the differential signal  208  in  FIG. 2  for reliable high-speed data communication. With long cable lengths (20 meters for example) and high data transmission rates (1.5 GHz for example), skew becomes a major issue.  
         [0006]     Thus, there is a need for differential pair signal de-skewing in data communication systems.  
       SUMMARY  
       [0007]     This document describes a method and apparatus to remove skew from a signal with one or more delay blocks. 
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0008]      FIG. 1  shows graphs of voltage vs. time for positive and negative transmission signals.  
         [0009]      FIG. 2  shows graphs of voltage vs. time for skewed positive and negative transmission signals.  
         [0010]      FIG. 3  shows an example of a de-skew arrangement.  
         [0011]      FIG. 4  shows a layout of a de-skewing receiver.  
         [0012]      FIG. 5  shows a layout of a de-skewing receiver with additional control elements.  
         [0013]      FIG. 6  shows an example of the internal components of a delay block. 
     
    
     DESCRIPTION  
       [0014]     Cables that are used for differential data communication, both shielded and unshielded, may have differences in the positive and negative wires that cause skew between the positive and negative signals. As discussed above, this type of skew is undesirable for reliable high speed communication. By introducing actively controlled delay elements to the differential receiver, the skew can be reduced or eliminated before a signal is converted to data, thereby maximizing the signal integrity of the system. This novel approach treats the positive and negative signals as two different entities, instead of a single lumped differential signal.  
         [0015]     Shielded cable usually provide a grounding sheath that provides a voltage reference for the positive and negative signals. Unshielded cables do not provide the sheath and rely on the earth ground for the voltage reference. For the purposes of this application, it may be advantageous to consider skew as relative to a triggering clock edge at the signal source transceiver.  
         [0016]      FIG. 3  shows an example of a de-skew arrangement. Positive and negative signals  302 ,  304  are fed into a de-skew module  306 . In this case, the skew is t n -t p . The module senses the skew in the signal pair and delays the propagation of one or both of the signals  302 ,  304  in order to remove the skew from the signal pair. The de-skewed signals are then fed into the subtracter  308 . The resulting differential signal  308  has a small dispersion and large voltage peak.  
         [0017]      FIG. 4  shows a layout of a de-skewing receiver. Positive and negative transmission lines  402 ,  404  carry the respective positive and negative signals. The positive signal enters the positive delay block  406 . The negative signal enters the negative delay block  408 . The delay blocks  406 ,  408  delay their corresponding signals such that the signal skew in minimized. The signals leave the delay blocks  406 ,  408  and enter the subtracter  410 . The output of the subtracter  410  is the analog differential signal. The analog differential signal is fed into both the slicer  412  and the error subtracter  414 . The slicer  412  converts the analog differential signal into the digital data stream noted as data(n). The analog differential signal is subtracted from an analog signal that represents the digital data stream at the error subtracter  414 . The digital output of the error subtracter  414  is noted as error(n). Error(n) represents the difference between the measured analog differential signal and the desired signal. Both the error(n) and data(n) streams are fed into the delay control blocks  416 . The delay control blocks  416  control the delay behavior of the positive and negative delay blocks  406 ,  408 . The delay control blocks  416  comprise two different block as shown, but, in reality, may comprise a single control block  416  that controls both delay blocks  406 ,  408 . The delay control blocks  416  may also be referred to as an adaptive algorithm block.  
         [0018]     The slicer  412  as shown has two output levels. For systems that use pulse amplitude modulation (PAM) to carry more bits of data per pulse, an analog to digital (A/D) converter may be used in place of the slicer  412 . An A/D converter may be constructed using a slicer for each level of PAM in the differential signal. The slicer  412  may need a D/A converter to send an analog representation of the data stream to the error subtracter  414 .  
         [0019]     For a simple example of the slicer  412  operation, consider the following. If a system has two level PAM at 0 and 1 V and the output of the subtracter  410  is 1 V, then the error is 0 V. If, on the other hand, the output of the subtracter  410  is 0.9 V, then the error is 0.1 V. In the second case, the delay control block  416  would alter the delay coefficients of the delay blocks  406 ,  408  in such a way as to minimize the delay. The delay control block  416  may use an integrator to determine appropriate coefficients for the delay blocks  406 ,  408 . Iterative algorithms for determining appropriate coefficients are well known ( Adaptive Signal Processing  by Bernard Widrow and Samuel Stearns, Prentice-Hall, New Jersey, 1985 pages 99-114).  
         [0020]      FIG. 5  shows a layout of a de-skewing receiver with additional control elements. The layout shown is similar to that shown in  FIG. 4  with the addition of a miscellaneous control block  418 . The control block  418  receives the error(n) and data(n) streams and outputs a signal to the subtracter  410 . The control block  418  may include any additional elements deemed necessary by the designer, such as an equalizer or echo canceller.  
         [0021]      FIG. 6  shows an example of the internal components of a delay block. The delay block  606  may be either the positive or negative delay blocks  406 ,  408  shown in  FIGS. 5, 6 . The delay block includes one or more delay cells  608  that each have a controllable propagation delay. The propagation delay is controlled by the delay control block  416 . The delay of each individual delay cell should be less than one baud. Of course, the overall delay of the delay block  606  may be more than one baud.  
         [0022]     A raw signal  602  enters the delay block  606  and goes into the first delay cell  608 . The first delay cell delays the signal propagation by a certain amount, which may also be zero. The signal may propagate through each successive delay cell  608  before heading to the summer  610 . The summer  610  adds the partial signals from all of the delay cells  608  to create the delayed signal  604 . Each delay cell has an associated coefficient. For example, the first delay cell  608 , delay cell zero, has a coefficient of A(0). The next delay cell has a coefficient of A(1), etc. The coefficients range between 0 and 1. The coefficients may be digital or analog. If they are digital, their values are converted to analog before being multiplied by the cell delay value.  
         [0023]     Each delay cell  608  has an associated cell delay value between 0 and _baud. Cell delay values may be different for each cell. For example, consider the case where each delay cell  608  has an ever decreasing cell delay value: delay(0)=_baud, delay(1)=_baud, delay (2)=⅛ baud, etc. The cell delay value is multiplied by the corresponding coefficient. The result is summed at the summer  610  with all of the other multiplied results. The output of the summer is the delayed signal  604 . Ideally, the sum of all of the coefficients equals 1.  
         [0024]     The true delay should be determined by simulation. High precision systems would need finer delay control, therefore less than _baud delay. The true range/resolution of the delay block  606  may depend on: (1) system required precision (this would be determined by simulations optimizing BER vs. delay_cell delay, which may be part of the process of implementation), and (2) length of cable (longer cables generally give more skew and would require more delay cells). The fact that both the positive and negative signals are delayed is advantageous since only half of the total delay is needed on either side (worst case is minimum delay on+ and max on −, or vise versa).  
         [0025]     The delay control block  416  stores and uses delay coefficients to control the propagation delay of each delay cell  608 . Thus, for m+1 delay blocks, coefficients A(0), A(1), A(2), . . . , A(m) are used. The corresponding z-transform is f(A(0)+A(1)z −1 +A(2)z −2 + . . . +A(m)z −m ). Thus, the differential output of the subtracter  410  would be f positive -f negative .  
         [0026]     The delay coefficients are updated by the delay control block  416  relative to the system clock. The coefficients may be updated every clock cycle or every n clock cycles, where n is an integer. The number of delay cells necessary for a given system depends on the range and resolution of the desired added delay. The delay introduced by all of the delay cells  408  in a delay block  606  should be greater than the worst cast delay that may be required. Use of a system simulator will aid the designer in determining the appropriate number of delay cells  408 .  
         [0027]     The amount of delay that each delay cell  408  may relative to a fixed value or not, depending on the desired outcome. For example, a delay tied to the system clock, a flip flop, or a given delay may be considered to be based on a fixed delay. A delay tied to an analog delay that varies with respect to currect, for example, may be considered to be based on a variable delay.