Abstract:
A blocking section is inserted between the control section and the fuse section of a fuse control logic circuit. The blocking section comprises switching means which block the flow of DC current during a power-up sequence and thus avoids the collapse of the power supply voltage with the attending potential for incorrect addressing and improper function and timing options. The insertion of the blocking section further eliminates indeterminate logic states when fusible means are not fully blown thus assuring correct voltage levels at the output of the circuit.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The invention relates to an address matching circuit for redundancy cell repair in DRAM memories, and more particularly to such a circuit which is without a DC path at power up and one which has a better margin when the fuse in the circuit is only partially blown. 
   2. Description of the Related Art 
   Referring now to  FIG. 1   a  a conventional fuse control logic circuit  10  is shown. Power-up signal PU is the input to control section  12  and couples to the gate of PMOS transistor P 2 . Transistors P 1  and P 2  are coupled in parallel between a power supply V CC  and a common node P 2 D. The fuse section  14  with fuse I 1  is coupled between P 2 D and the return terminal of power supply V CC  (ground in  FIG. 1   a ). The common node P 2 D couples to the gates of PMOS transistor P 3  and NMOS transistor N 1  of driver section  16 . Transistors P 3  and N 1  are coupled in series between V CC  and the return terminal of power supply V CC  (ground). The junction between transistors P 3  and N 1  is the output terminal OUT of driver section  16 . The output terminal OUT also feeds back to the gate of PMOS transistor P 1 . 
   The problem with the related art of  FIG. 1   a  is that it has a DC path when PU=0 (logical “0”), which is the power-up state. This will introduce potential problems such as excessive current drain if there are many of these circuits, especially when the driving capability of the power supply is not enough. An additional problem is that the related art circuit has a smaller margin for normal function if fuse I 1  is not perfectly blown because transistor P 2  represents a large resistor for a small DC current. Common node P 2 D will then be at some intermediate voltage level depending on the resistance of fuse I 1 . As a result the circuit may malfunction because the voltage at common node P 2 D is not high enough. Additionally, there may be DC current flowing through transistors P 3 /N 1 . This is a serious problem for low power memories which may be out-of-spec then. 
   The related art circuit  11  of  FIG. 1   b  is structurally similar to circuit  10  of  FIG. 1   a  but uses NMOS transistors. Fuse section Block  14  is coupled between power supply V CC  and node N 2 D. Block  22 , coupled between node N 2 D and ground comprises transistors N 21  and N 22 . The first input of Block  22  receives power-up signal PU-bar, which is the inverted signal of PU of circuit  10 , Block  12 . Block  26 , showing a generic inverter INV, is coupled between node N 2 D and the second input to Block  22 . The description for  FIG. 1   a  above applies equally to circuit  11  of  FIG. 1   b.    
     FIG. 2  is a graph of the input signal and the voltage levels of a good power supply or regulator during power-up of the circuit of  FIG. 1 . Curve  21  depicts the external V DD  supply ramping up, Curve  22  depicts the power-up signal PU ramping up briefly to Point A, dropping to “0” level, and then rising at Point B to join Curve  21 . Curve  23  depicts the internal V CC  supply ramping up smoothly. 
     FIG. 3  is a graph of the input signal and voltage levels of a bad power supply or regulator of the circuit of  FIG. 1 . Curves  31  and  32  are identical to Curves  21  and  22  of  FIG. 2 . Internal V CC  Curve  33 , however, ramps up only to about Point A, then continues almost horizontally to Point C and then rises. The section from near Point A to Point C represents an excessive current draw caused by DC paths in the P 2 /I 1  path in other circuits without blown fuses. This delay in the rise of the internal V CC  supply causes problems when the blown-fuse initialization time is not long enough, because then common node P 2 D cannot set up properly at startup and its voltage level is at an indeterminate state. An improper address may be output or an improper function/timing option may be selected. Conversely, if the initialization time is lengthened it affects other circuits which use the power-up signal PU and V CC  for initialization. Lastly, in blown fuse circuits a DC current path can be introduced in the P 3 /N 1  transistor path because P 2 D is neither at “0” nor at “1”. 
   An improved circuit and method are clearly needed to overcome these problems of the related art. The circuits and method described hereinafter and illustrated in  FIGS. 4   a ,  4   b ,  5   a ,  5   b , and  6  completely eliminates these problems. 
   U.S. Pat. No. 6,292,422 (Pitts) discloses a system and method for storing data values by implementation of electrical fuse chains which enables the programming and use of electrical fuses and includes read and write protection. U.S. Pat. No. 6,073,258 (Wheater) teaches the use of fuse elements responsible for soft-fusing redundant memory elements into the memory array. Soft-fusing is defined to mean that the fuse elements may be set and reset via an electronic signal. 
   It should be noted that none of the above-cited examples of the related art address the above described problems. 
   SUMMARY OF THE INVENTION 
   It is an object of at least one embodiment of the present invention to provide circuits and a method which block any DC paths on power-up and therefore eliminate a potential collapse of the power supply voltage. 
   It is another object of the present invention to prevent the fuse control logic circuit from entering into an indeterminate state by providing a circuit which is more tolerant of a residual fuse resistance, thereby allowing normal function when the fusible means is not fully destroyed. 
   It is yet another object of the present invention is to prevent an indeterminate and improper address at the output of the circuit. 
   It is still another object of the present invention is to prevent the selection of an improper function or timing option. 
   It is a further object of the present invention to provide a fuse control logic circuit for a fail address matching circuit for redundancy cell repair in a memory. 
   It is yet a further object of the present invention to provide a fuse control logic circuit for use in certain functions on a die per customer request. 
   It is still a further object of the present invention is to provide a fuse control logic circuit for timing options such as to adjust timing parameters. 
   These and other objects have been achieved by inserting a blocking section between the control section and the fuse section, where the blocking section comprises switching means which block the flow of DC current during a power-up sequence and thus avoids the collapse of the power supply voltage with attending serious side effects. The insertion of the blocking section further assures proper voltage levels at the output of the circuit. 
   These objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of the preferred embodiments. 
   In the following, first and second conductivity types are opposite conductivity types, such as N and P types. Each embodiment includes its complement as well. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIGS. 1   a  and  1   b  are circuit diagrams of the prior art. 
       FIG. 2  is a view of the input signal and voltage levels of a good power supply or regulator of the circuit of  FIG. 1 . 
       FIG. 3  is a view of the input signal and voltage levels of a bad power supply or regulator of the circuit of  FIG. 1 . 
       FIGS. 4   a  and  4   b  are block diagrams of a first and second preferred embodiment of the present invention. 
       FIGS. 5   a  and  5   b  are circuit diagrams of a first and second preferred embodiment of the present invention. 
       FIG. 6  is a block diagram of the preferred method of the present invention. 
   

   Use of the same reference number in different figures indicates similar or like elements. 
   DESCRIPTION OF THE PREFERRED EMBODIMENT 
   Referring now to  FIG. 4   a , we begin a description of a first preferred embodiment of the present invention.  FIG. 4   a  is a block diagram of fuse control logic circuit  40  comprising control section  12 , a blocking section  13  coupled to common node P 2 D of control section  12 , a fuse section  14  coupled to blocking section  13 , and a driver section  16  coupled to common node P 2 D. Control section  12  and blocking section  13  share a first input with power-up signal PU applied. The output terminal OUT of driver section  16  feeds back to a second input of control section  12 . 
   Referring now to  FIG. 5   a  we describe in detail fuse control logic circuit  40 . First input receives a power-up signal PU which has a logical “0” or “1”. Control section  12  comprises switching means which are coupled at one end to common node P 2 D. Control section  12  controls the state of fuse control logic circuit  40  as a function of the first input. Blocking section  13 , comprising switching means, blocks DC paths in the control section when the power-up signal PU is at a logical “0”. Fuse section  14  comprises fusible means and controls the voltage level at the output terminal S of blocking section  13 . Driver section  16 , coupled to the common node P 2 D, has an output terminal OUT. Driver section  16  serves as a signal powering means and is illustrated here, by way of example, as a CMOS inverter. Output terminal OUT is coupled to a second input of control section  12 . When power-up signal PU is at logical “1”, output terminal OUT produces a logical “1” signal when the fusible means of fuse section  14  is not blown, and a logical “0” signal when the fusible means is blown. 
   Control section  12  has a first input, receiving power-up signal PU, a second input and a common node P 2 D. The first input is coupled to the control gate of first switching means P 2 , the second input is coupled to the control gate of second switching means P 1 . First terminals of switching means P 1 , P 2  are coupled to the positive terminal of a power supply V CC , while the second terminals of second switching means P 1 , P 2  are tied to common node P 2 D. Switching means P 1  and P 2  are shown as PMOS transistors by way of illustration. 
   Blocking section  13  comprises a third switching means N 12  having a first terminal and a second terminal S, and a control gate. The first terminal of third switching means N 12  is coupled to common node P 2 D, and the control gate of N 12  is coupled to the first input of control section  12 . The function of blocking section  13  is to block DC paths in control section  12  during a power-up sequence when power-up signal PU is inactive (logical “0”). Switching means N 12  is shown as an NMOS transistor by way of illustration and of opposite conductivity to P 1 , P 2 . When power-up signal PU is active (logical “1”=near V CC ), blocking section  13  insures that common node P 2 D is at or near ground level (because NMOS transistor N 12  is conducting) when fusible means I 1  is good, thus providing a logical “1” at output terminal OUT. When the power-up signal PU is inactive (logical “0”) PMOS transistor P 2  is conducting. This forces node P 2 D to near V CC  and the output terminal OUT to a logical “0” (near GND), whether fusible means I 1  is good (not blown) or blown. 
   Fuse section  14  comprises fusible means I 1 , where one end of that fusible means I 1  is coupled to the second terminal S of third switching means N 12 . The other end of fusible means I 1  is coupled to the return terminal of the power supply (typically ground GND). Fuse section  14  controls the voltage level at second terminal S of third switching means N 12 . 
   Driver section  16  comprises a fourth and a fifth switching means P 3 , N 1 , coupled in series between the positive terminal of the power supply V CC  and the return terminal of that power supply (typically ground GND). The control gates of the fourth and the fifth switching means are coupled to common node P 2 D of the control section  12 . The junction of the fourth and fifth switching means is coupled to output terminal OUT, and also to the control gate of the second switching means P 1 , thereby latching up fuse control logic circuit  40 . When power-up signal PU is at logical “1”, CMOS driver section  16  provides a logical “1” (near V CC ) signal at output terminal OUT when fusible means I 1  is not blown and a logical “0” signal (near ground) when it is blown or not fully blown. Fourth and fifth switching means P 3 , N 1  illustrate a typical inverter in CMOS technology but may be replaced by some other suitable inverter means. 
   The present invention provides a circuit which is more tolerant of a residual fuse resistance when the fusible means I 1  is not fully blown, i.e. it has some resistance instead of presenting an open circuit. This is because the width-to-length ratio (W/L) of P 1  can be much larger than the W/L of P 2  and is not critical in the present invention. The ratio is typically 10:1, but may range, depending on the design, from 20:1 to 5:1. When the ratio is 10:1 the tolerance of the residual resistance is about one tenth of the prior art for normal function. In the present invention, the W/L of P 1  is key since it must be large enough to overcome leakage current when the fuse is not blown properly. In the prior art, the W/L of P 1  and P 2  is important; in particular the W/L of P 2  must be small for a small DC current during the power-up period. In the present invention, the W/L of N 12  must be larger than the W/L of P 1  and is typically 5:1 but may range, depending on the design, from 10:1 to 2:1. 
   In a second preferred embodiment the NMOS and PMOS transistors are interchanged. This requires that the blocks of  FIG. 4   a  are rearranged as illustrated by circuit  41  in  FIG. 4   b  and that the polarity of the power-up signal PU of  FIG. 4   a  be inverted as is obvious to those skilled in the art. Still referring to  FIG. 4   b , the block diagram of fuse control logic circuit  41  comprises control section  22 , a blocking section  23  coupled to common node N 2 D of control section  22 , a fuse section  14  coupled to blocking section  23 , and a driver section  26  coupled to common node N 2 D. Control section  22  and blocking section  23  share a first input power-up signal PU-bar (NOT PU). The output terminal OUT-bar (=NOT OUT) of driver section  26  feeds back to a second input of control section  22 . Note that the function of Blocks  22  and  12 ,  23  and  13 ,  26  and  16  of  FIGS. 4   b  and  4   a , respectively, are the same. Note also that negative logic is used in the second preferred embodiment, so that:
         a signal is active when it is near ground potential (=logical “1”);   a signal is inactive when it is near V CC  (=logical “0”).       

   We now refer to  FIG. 5   b  for an explanation of the fuse control logic circuit  41  of the second preferred embodiment of the present invention. Control section  22  comprises switching means which are coupled at one end to common node N 2 D. Control section  22  controls the state of fuse control logic circuit  41  as a function of the first input. Blocking section  23 , comprising switching means, blocks DC paths in the control section when the power-up signal is at a logical “1”. Fuse section  14  comprises fusible means and controls the voltage level at the output terminal S of blocking section  23 . Driver section  26 , coupled to the common node N 2 D, has an output terminal OUT-bar. Driver section  26  serves as a signal powering means and is illustrated here, by way of example, as inverter INV. Output terminal OUT-bar is coupled to a second input of control section  22 . When power-up signal PU-bar is at logical “1”, output terminal OUT-bar produces a logical “1” signal when the fusible means of fuss section  14  is not blown, and a logical “0” signal when the fusible means is blown or not fully blown. The detailed explanation of fuse control logic circuit  41  is obvious to those skilled in the art by referring to circuit  40  of  FIG. 5   a  and reviewing the explanation of control section  12 , blocking section  13 , and fuse section  14 . 
   Still referring to  FIG. 5   b , control section  22  has a first input receiving power-up signal PU-bar, a second input and a common node N 2 D. The first input is coupled to the control gate of first switching means N 22 , the second input is coupled to the control gate of second switching means N 21 . First terminals of switching means N 21 , N 22  are coupled to the return terminal of a power supply (typically ground GND), while the second terminals of N 21  and N 22  are tied to common node N 2 D. N 21  and N 22  are shown as NMOS transistors by way of illustration. 
   Blocking section  23  comprises a third switching means P 22  having a first terminal and a second terminal S, and a control gate. The first terminal of third switching means P 22  is coupled to common node N 2 D, and the control gate of P 22  is coupled to the first input of control section  22 . The function of blocking section  23  is to block DC paths in control section  22  during a power-up sequence when power-up signal PU-bar is inactive (logical “0”). Switching means P 22  is shown as an PMOS transistor by way of illustration and of opposite conductivity type to N 21 , N 22 . When power-up signal PU-bar is active (logical “1”=near ground), blocking section  23  insures that common node N 2 D is pulled up to or near V CC , when fusible means I 1  is good, thus providing a logical “1” (near ground) at output terminal OUT-bar. When the power-up signal PU-bar is inactive (logical “0”=near V CC ) PMOS transistor P 22  is off, but NMOS transistor N 22  is conducting, thus pulling node N 2 D to ground. Thus the output terminal OUT-bar is set to a logical “0” (near V CC ), whether fusible means I 1  is good (not blown) or blown. However, when PU-bar is active and when fusible means I 1  is not fully blown then terminal OUT is forced to logical “0”. 
   Fuse section  14  comprises fusible means I 1 , where one end of that fusible means I 1  is coupled to the second terminal S of third switching means P 22 . The other end of fusible means I 1  is coupled to the positive terminal of the power supply V CC . Fuse section  14  controls the voltage level at second terminal S of third switching means P 22 . 
   Driver section  26  comprises an inverter INV, whose input is coupled to node N 2 D and whose output is coupled to output terminal OUT-bar and the control gate of the second switching means N 21 , thereby latching up fuse control logic circuit  41 . When first input, receiving power-up signal PU-bar, is at logical “1”, i.e. low, inverter INV provides a logical “1” signal, i.e. low, at output terminal OUT-bar when fusible means I 1  is not blown and a logical “0” signal, i.e. high, when it is blown or not fully blown, as already mentioned earlier. 
   In the second preferred embodiment the W/L ratios for N 21 , N 22  are the same as those of P 1 , P 2  of the first preferred embodiment. However, the W/L of P 22  versus N 21  of the second preferred embodiment ranges from 20:1 to 4:1. 
   Referring now to the block diagram of  FIG. 6  we describe the preferred method of the present invention:
     BLOCK  1  provides a control section with an input, having logic level signals, which controls the state of a fuse control logic circuit.   BLOCK  2  couples a blocking section to a common node of the control section, and an input of the blocking section to the input of the control section, where the blocking section blocks DC paths in the control section when the power-up signal is at a logical “0”.   BLOCK  3  couples a fuse section having fusible means, between the blocking section and a power supply terminal.   BLOCK  4  couples a driver section to the common node of the control section, where, when the power-up signal is at a logical “1”, the driver section produces a logical “1” signal at its output terminal when the fusible means is not blown, and a logical “0” signal when the fusible means is blown.   BLOCK  5  couples back the output of the output terminal to the control section to provide latching up of the fuse control logic circuit.   

   One application of the present invention is when a memory has a bad cell then its address is stored using the fuse control logic circuit. Because the fusible means I 1  is then blown the output terminal OUT=logical “0”. Conversely, when a memory does not have a bad cell in a certain address then the associated fusible means I 1  is not blown and the output terminal OUT=logical “1”. The operation is as follows:
         When applied to a memory chip, the corresponding fail address of the chip is known after the chip probe test. Then using a laser to blow fuses of a set of fuse control logic circuits, the corresponding fail address will be recorded in the set of fuse control logic circuits. E.g., if the failing address is A 3 =0, A 2 =1, A 1 =1, A 0 =0, four fuse control logic circuits are involved. The fuses corresponding to A 3  and A 0  will be blown and will generate the corresponding fail address logic output from the set of 4 fuse control logic circuits. During chip operation, the external address will be compared to the output of the sets of fuse control logic circuits. If the address matches, the redundant cells will substitute for the cells of the corresponding failed address.
 
This circuit can also be used to advantage for certain functions, e.g., on a die per customer request or for timing options, such as adjustment of timing parameters.
       

   While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.