Abstract:
An electronic circuit for performing logic operations is provided. The electronic circuit comprises a logic gate having at least two binary inputs adapted to receive corresponding input binary digits; an output for outputting an output signal; signal transmission means between said input and said output; a logic circuit coupled to said transmission means and having an input capacitance, and capacitance decoupling means between said logic circuit and said transmission means for decoupling the input capacitance of said logic circuit from said transmission means.

Description:
CROSS REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims the benefit of U.S. provisional application Ser. No. 60/657,391, filed Mar. 2, 2005 the disclosure of which is incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     The present invention relates to electronic circuits, and in particular to electronic circuits for performing logic operations.  
         [0003]     Logic circuits have a wide variety of uses and may be configured to perform arithmetical operations. A basic full adder circuit can be described by the following two equations: 
 
Sum=A⊕B⊕C in    (Eq. 1) 
 
Cout=AB+BC in +AC in    (Eq. 2) 
 
         [0004]     A full adder cell or block can be illustrated in the form shown in  FIG. 1 . The full adder cell  1  has first and second inputs  3 ,  5  for receiving the numbers (A, B) to be summed, a carry input  7 , a carry output  9  and a sum output  11 . Typically each input and output is a single bit. In order to perform higher order addition, a number of full adders are connected together in a series with the carry output of one adder being connected to the carry input of another adder. An example of a four-bit adder circuit is shown in  FIG. 2  and comprises four full adder cells  2 ,  4 ,  6  and  8 . The main concerns in designing a full adder circuit are the speed and area of the circuit. In the four-bit full adder shown in  FIG. 2 , the maximum propagation delay can be described by: 
 
4bit_delay=t H +4×t carry +t Sum    (Eq. 3) 
 
 where t H  describes the delay through the circuit that implements (Eq. 4) logic: 
 
H={overscore (A)}B+A{overscore (B)}=A⊕B  (Eq.4) 
 
 Using (Eq.4), (Eq.1) and (Eq.2) are rewritten as: 
 
Sum=H⊕C in    (Eq. 5) 
 
Cout={overscore (H)}A+HC in    (Eq. 6) 
 
 t carry  describes the delay from C in  to C out  of a full adder cell, and t Sum  describes the delay through the circuit that implements Eq. 5. The reason that the H-equation logic is added is to minimize the number of input lines that effect the propagation of C in  to C out . 
 
         [0005]      FIG. 3  shows a typical standard cell implementation of a full adder which implements equations 4, 5 and 6. The adder circuit comprises a first (or input) XOR gate  15  for determining the value of H (equation 3), an inverter  17  at the output of the XOR gate  15  for deriving the value {overscore (H)} for use in equation 6, a first transmission gate  19 , a carry propagate circuit  21  (transmission means) between the carry input and carry output  7 ,  9 , and a summing circuit  31  comprising a second XOR gate for implementing equation 5. The carry propagate circuit  21  comprises a second transmission gate  23  and a buffer  25  comprising a pair of serially arranged inverters  27 ,  29 .  
         [0006]     The first input  20  of the first transmission gate  19  is connected to the first input  3  of the adder circuit and the other complementary inputs  22 ,  24  (NMOS gate and PMOS gate) are connected to receive the values {overscore (H)} and H respectively. The output  26  of the first transmission gate  19  is connected to the carry propagate circuit  21  and implements the first term of equation 6. The first input  28  of the second transmission gate  23  is connected to the C input  7  of the carry propagate circuit and the complementary inputs  30 ,  32  are connected to receive the values of H and {overscore (H)}, respectively. The output  34  of the second transmission gate outputs the value HC IN  which is the second term of equation 6.  
         [0007]     One of the inputs  36  of the second (or summing) XOR gate  31  is connected to the output of the first XOR gate  15  for receiving the value H and the second input  38  of the second XOR gate is connected to the input  7  of the carry propagate circuit  21  for receiving the value C IN .  
         [0008]     The components of the full adder circuit shown in  FIG. 3  that are responsible for the propagation delay of equation 3 are as follows. t H  is the delay through the input XOR gate  15 , t SUM  is the delay through the output XOR gate  31 , and t CARRY  is the delay from C IN  to C OUT  (for bit  0  this might be from the first input  3  (A) to C OUT ). It is apparent from equation 3 that the propagation delay from C IN  to C OUT  in a multiple cell adder is more heavily weighted than other parts of the equation, and this delay plays a pivotal role in determining the total delay through the adder chain.  
         [0009]     In a typical standard cell implementation, when H=1, the C IN  signal is loaded by the gate capacitance of the second XOR gate  31 , which is equal to, at the very least, the input capacitance of an inverter comprising an N-type and P-type gate capacitance; the N-type and P-type gate capacitance of the second transmission gate  23 , the two drain to gate capacitances of the first transmission gate  19  and the input capacitance of the buffer cell  25 . In addition, there is a propagation delay through the output buffer cell, which comprises two inverters  27 ,  29  in series.  
         [0010]     It would be desirable to reduce the propagation delay in the carry propagate circuit.  
       SUMMARY OF THE INVENTION  
       [0011]     The present invention in one embodiment involves the provision of an electronic circuit comprising: a logic gate having at least two binary inputs adapted to receive corresponding input binary digits; an output for outputting an output signal; signal transmission means between said input and said output; a logic circuit coupled to said transmission means and having an input capacitance, and capacitance decoupling means between said logic circuit and said transmission means for decoupling the input capacitance of said logic circuit from said transmission means.  
         [0012]     According to another aspect of the present invention, there is provided an electronic circuit comprising first and second signal generating means, each having an input and an output, circuit means between the output of said first signal generating means and the input of said second signal generating means, and a circuit, for example a logic circuit coupled to the input of said first signal generating means.  
         [0013]     According to yet another aspect of the present invention, there is provided an electronic circuit comprising first and second inputs and first and second outputs, first transmission means between said first input and said first output and second transmission means between said second input and said second output, a circuit having first and second inputs, wherein the first input is coupled to the first transmission means and the second input is coupled to the second transmission means.  
         [0014]     According to a further aspect of the present invention, there is provided an electronic circuit comprising first and second transmission means having a respective input and a respective output and a differential buffer having a first input coupled to the output of said first transmission means and a second input coupled to the output of said second transmission means.  
         [0015]     According to yet a further aspect of the present invention, there is provided an adder circuit comprising first and second inputs for receiving signals to be added together, circuit means for determining the sum of said signals and first and second carry propagate circuits each having an input and an output, and wherein said first carry propagate circuit is adapted to determine a carry-out signal from a carry-in signal and the second carry propagate circuit is adapted to determine a carry-out signal from an inverted carry-in signal.  
         [0016]     According to yet a further aspect of the present invention, there is provided an electronic circuit comprising an input circuit having at least one input for receiving a signal, a transmission means having an input and output, the input circuit being connected to said transmission means, a further circuit coupled to the transmission means, and capacitive reduction or decoupling means connected between said transmission means and said further circuit means for reducing the capacitive load on the input of said transmission means.  
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0017]     Examples of embodiments of the present invention will now be described with reference to the drawings, in which:  
         [0018]      FIG. 1  shows a schematic block diagram of a full adder circuit;  
         [0019]      FIG. 2  shows a block diagram of a full adder comprising multiple cells;  
         [0020]      FIG. 3  shows an example of a full adder circuit;  
         [0021]      FIG. 4  shows an example of a full adder circuit according to an embodiment of the present invention;  
         [0022]      FIG. 5  shows an example of a full adder circuit according to another embodiment of the present invention;  
         [0023]      FIG. 6  shows an example of a full adder circuit according to another embodiment of the present invention;  
         [0024]      FIG. 7  shows an example of a full adder circuit according to another embodiment of the present invention;  
         [0025]      FIG. 8  shows an example of an electronic circuit according to another embodiment of the present invention; and  
         [0026]      FIG. 9  shows an example of an electronic circuit according to another embodiment of the present invention. 
     
    
       [0027]     It should be understood that the drawings are not necessarily to scale and that the embodiments are sometimes illustrated by graphic symbols, phantom lines, diagrammatic representations and fragmentary views. In certain instances, details which are not necessary for an understanding of the present invention or which render other details difficult to perceive may have been omitted. It should be understood, of course, that the invention is not necessarily limited to the particular embodiments illustrated herein. Like numbers utilized throughout the various Figures designate like or similar parts.  
       DETAILED DESCRIPTION  
       [0028]     Before describing the present invention, it will be understood that variations of the present invention may is not limited to the specific examples described herein.  
         [0029]      FIG. 4  shows an example of a full adder circuit according to a first embodiment of the present invention.  
         [0030]     The circuit  101  comprises first and second inputs  103 ,  105  for receiving bits to be summed and each being connected to the respective inputs of an input XOR gate  115  for generating a value “H”. The first inverter  117  is connected to the output of the input XOR gate  115  for generating a value {overscore (H)}, and the values {overscore (H)} and H are applied to the complementary inputs of a first transmission gate  119 . The other input terminal  120  of the first transmission gate  119  is arranged to receive the inverse of the signal received at the first input  103 . Although {overscore (A)} may be generated by a separate inverter  110 , the value {overscore (A)} is also generated by the XOR gate  115  and therefore a separate inverter is not required.  
         [0031]     The adder  101  has a carry propagate circuit  121  having an input  107  for receiving a carry bit, C IN , and an output  109  for outputting a carry bit, C OUT . The propagate circuit  121  comprises a first inverter  151 , a transmission gate  123  and a second inverter  153 . The output  126  of the first transmission gate  119  is connected to the carry propagate circuit between the transmission gate  123  and the second inverter  153 .  
         [0032]     The adder  101  includes a second XOR gate  131  for generating a sum from the values of H and C IN  (equation 5) and a buffer circuit  155  connected between the carry propagate circuit  121  and the summing XOR gate  131 .  
         [0033]     The buffer circuit  155  has a first input  157  connected to the input of the first inverter  151  and a second input  159  connected to the output of the first inverter. The buffer circuit  155  comprises first and second FET&#39;s  161 ,  163  and third and a fourth FET&#39;s  165 ,  167 . The first and third FET&#39;s  161 ,  165  are both NMOS-type FETS whereas the second and fourth FET&#39;s  163 ,  167  are both PMOS-type FETS. The sources of the first and third FET&#39;s are connected to ground and their drains are connected to the sources of the second and fourth FET&#39;s, respectively. The drains of the second and fourth FET&#39;s are connected to a voltage rail  169 . The gate of the first FET  161  is connected to the input of the first inverter  151  of the carry propagate circuit and the gate of the third FET  165  is connected to the output of the first inverter  151 . The gate of the second FET  163  is cross-coupled to the drain of the second FET  165  and the gate of the fourth FET  167  is cross-coupled to the drain of the first FET  161 . The drains of the first and third FET&#39;s  161 ,  165  provide inverted and non-inverted buffered carry-in signals C BUF  and C BUF , respectively and are used as inputs to the XOR gate  131 , which will be described in more detail below.  
         [0034]     A typical XOR gate comprises a pair of AND gates each having an inverter on one of their inputs and an OR gate connected to their outputs. As an inverter and the input to an AND gate typically comprise two FET&#39;s each when implemented in CMOS, each input to an XOR gate is effectively coupled to four gate capacitances.  
         [0035]     The purpose of the buffer circuit  155  is to effectively reduce the capacitance at the input of the carry propagate circuit. The buffer circuit effectively decouples the input capacitance of the summing circuit  131  from the input  107  of the carry propagate circuit.  
         [0036]     In the embodiment shown in  FIG. 4 , the input capacitance of the carry propagate circuit essentially corresponds to the gate capacitance of the first NMOS FET  161  and the two-gate capacitances of the FET&#39;s of the first inverter  151 . This is a substantial reduction in the input capacitance of the circuit shown in  FIG. 3 . It is to be noted that the gate capacitance of the first FET  161  can be reduced by using a relatively small FET. Also, as the FET can be implemented in NMOS, the gate capacitance can be significantly reduced over a PMOS FET, in which the gate area (and therefore capacitance) is typically 3 times larger. The “input” capacitance of the carry propagate circuit at the output of the first inverter  151  is provided by the gate capacitance of the third NMOS FET  165  of the buffer circuit, the gate capacitances of the NMOS and PMOS FET&#39;s of the transmission gate  123 , the gate to drain capacitances of the transmission gate  119  and the input capacitance of the second inverter  153 .  
         [0037]     Partially coupling the summing XOR circuit  131  at the input of the first inverter  151  causes the capacitive loading of the carry propagate circuit to be shared more evenly between the inverters, each of which drives an inverted input signal from its output. The presence of two inverters ensures that the parity of the carry propagate signal is maintained between the input and output of the carry propagate circuit  121 .  
         [0038]     The differential buffer circuit  155  operates as follows. When the input of the carry propagate circuit is high (i.e. 1), the gate of the first FET  161  is high connecting the drain of the first FET to ground, and generating {overscore (C)} BUFF . At the same time, the output of the first inverter and therefore the gate of the third FET  165  is low, turning the third FET off. The gate of the fourth FET  167  (PMOS) is pulled low, turning on the FET and connecting its source to the voltage rail  169  so that C BUF  is high. This signal drives the gate of the second FET  163  (PMOS) high, thereby turning the second FET  163  off, to ensure that its source is pulled low by the first FET  161 . In this way, the differential buffer circuit  155  generates inverted and non-inverted signals in which the voltage of the high signal corresponds to the voltage on the voltage rail  169  and the low signal essentially corresponds to ground.  
         [0039]     When the carry input signal is low (i.e. 0), the first FET  161  is switched off, the third FET  165  is switched on, thereby connecting the gate of the second FET  163  to ground, and turning on the second FET  163 , so that {overscore (C)} BUF  is high (i.e. 1) and is equal to the voltage of the voltage rail  169 . This signal drives the gate of the fourth FET  167  low turning off the fourth FET  167 , so that C BUF  is low (i.e. 0) and corresponds to ground.  
         [0040]     In this embodiment, the XOR gate  131  comprises first and second AND gates  171 ,  173 , an inverter  175  at the input of the second AND gate  173  and an OR gate  177  to which the outputs of the AND gates are connected. Although a conventional XOR gate would normally have an inverter at the first input  172  of the first AND gate  171 , the differential buffer circuit  155  allows this inverter to be omitted as the circuit provides the inverted carry-in signal C BUF . It is to be noted that {overscore (H)} is also available at the output of the inverter  117  connected to the output of the input XOR gate  115 , and this signal could be provided at the input of the second AND gate  173 , allowing inverter  175  to be eliminated.  
         [0041]     The presence of the first inverter  151  in the propagate carry circuit changes the polarity of the carry input signal which is available to the succeeding portion of the circuit (including the transmission gate  123 ) which determines C OUT  using equation 6. As the polarity of this signal is reversed by the second inverter  153 , the carry signal at the input of the second inverter  153  is given by the equation: {overscore (C)}={overscore (C)} IN H+{overscore (AH)} and C OUT  at the output of the second inverter is given by the equation: C OUT ={double overscore ({overscore (C)}H+{double overscore (AH)}. Therefore, the value H and {overscore (C)} are applied to the transmission gate  123  and {overscore (AH)} are applied to the first transmission gate  119  to generate {overscore (C)} at the input of the second inverter  153 , and the second inverter then generates C OUT .  
         [0042]     Thus, in comparison to the circuit of  FIG. 3 , in the embodiment of  FIG. 4 , an inverter replaces the output buffer and a second inverter is placed at the input to maintain signal polarity. To decrease the amount of load on the C IN  to C OUT  signal path the differential buffer cell  155  is inserted between the carry input  107  and the sum XOR gate  131 . This differential buffer  155  connects to the input C IN  using the gate input of a minimum size NMOS gate, and attaches to the inverted version of C IN  using a similar minimum size NMOS gate.  
         [0043]     By using the differential buffer, the overall capacitance on the carry line can be reduced, and the load per inverter in the chain can be shared more evenly. By reducing the load on C IN  and sharing the load more evenly, a higher propagation speed can be achieved.  
         [0044]     As mentioned above, although  FIG. 4  shows an inverter  110  to generate {overscore (A)}, the inverter is not in practice required as {overscore (A)} is generated within the XOR gate that generates H. The differential buffer  155  creates both {overscore (C)} BUF  and C BUFF , which means that an inverter (or two) can be removed from the sum XOR gate. The cost of this new implementation over the standard circuit is at most two transistors for an unbuffered (slower—more load on C IN )-adder.  
         [0045]     The embodiment of  FIG. 4  is suitable for voltage scaling applications because all nodes including the transmission gates realize the full voltage swing. If voltage scaling is not important to the application, or if the application supports multiple on-chip voltage levels so that this circuit can be kept in a range where it works efficiently, then one or more of the transmission gates may be replaced by a pass transistor, for example an NMOS pass transistor. An example of this implementation is shown in  FIG. 5 . The embodiment of  FIG. 5  is similar to that shown in  FIG. 4  and like parts are designated by the same reference numerals (However, the XOR gates have been omitted for simplicity, although they would, of course, be present in the actual implementation). The main difference between the circuit of  FIG. 5  and that of  FIG. 4  is that in  FIG. 5 , the transmission gates  119 ,  123  have been replaced by pass gates  150 ,  160 . Replacing the transmission gate  123  in the carry propagate circuit  121  with a pass gate reduces the delay through the circuit by removing a PMOS drain-source (DS) capacitance, and a PMOS gate capacitance associated with the PMOS FET of the transmission gate. At the input of the second inverter  153 , the voltage level will be reduced to V DD -V THN . This will only be an issue if the voltage rail is too low and the input voltage to the inverter does not reach a high enough level to cause it to switch. As long as a sufficient voltage margin is maintained, this circuit should operate quickly and efficiently. In a variation of the embodiment of  FIG. 5 , either one of the first and second pass gates  150 ,  160  can be replaced by a transmission gate.  
         [0046]     In another embodiment of the propagate circuit, the carry-out output inverter (e.g. inverter  153 ) can be omitted thereby removing the propagation delay caused by the output inverter and further increasing the speed of propagation through the circuit. In this implementation, as each carry propagate circuit contains only one inverter, the polarity of the carry signal will be inverted once per circuit and therefore returned to the original polarity after propagating through two adjacent adder circuits. An example of this implementation is shown in  FIG. 6 .  
         [0047]     Referring to  FIG. 6 , an adder circuit comprises two full adders  201 ,  203 , (EVEN and ODD) each of which is similar to that shown in  FIG. 5  and like parts are designated by the same reference numerals. The difference between the first full adder circuit  201  and that shown in  FIG. 5 , is that the output inverter  153  has been omitted. In this embodiment, since the carry-out (C OUT ) determining circuit of the EVEN adder  201  receives {overscore (C IN )} after the inverter  151 , the input signals to the pass gate  150  are {overscore (A)} and {overscore (H)}. Although the circuit shows the inclusion of an inverter  110  to generate {overscore (A)}, since {overscore (A)} is available from the input XOR gate (shown in  FIG. 4 , not in  FIG. 6 ), the additional inverter is not required in practice.  
         [0048]     The input to the second full adder  203  is {overscore (C OUT )} which is subsequently inverted by the inverter  151  of the second adder  203 . Therefore, the carry signal which is input to the carry-out determining circuit of the second adder  203  has the original polarity of C IN  applied to the input of the first adder  201  and therefore the input signals to the pass gate  150  of the second circuit is A and {overscore (H)} (rather than {double overscore (A)} and {double overscore (H)}, for the first circuit).  
         [0049]     A differential buffer cell  155  is connected across the inverter  151  of the carry propagate circuit of each full adder  201 ,  203  to reduce the capacitive loading at the input of the carry propagate circuit of each adder  201 ,  203 , caused by the input capacitance of each summing XOR gate (shown in  FIG. 4 , not in  FIG. 6 ). Each differential buffer circuit generates both an inverted and a non-inverted carry-in signal (i.e. C 0   BUF , C 0   BUF  for the first adder and C 1   BUF  and C 1   BUF  for the second adder  203 ) which can be applied to the inputs of the XOR gate associated with each adder.  
         [0050]     By removing the output inverter and dividing the circuit into odd and even bits, a gate delay is saved. The actual implementation will not save the complete gate delay due to the inverter because the single inverter that remains is required to drive a modestly larger load as there is no additional inverter with which to share the load. However, the reduction in delay caused by the omission of the output inverter is significant. As an optional but preferable feature, the last full adder in the chain is arranged such that C OUT  drives either a small load or C OUT  is buffered.  
         [0051]     In another embodiment of the present invention, the carry propagate circuit is split into two carry propagate lines so that the capacitive loading on each line can be further reduced. Each line may include a single inverter and the input of one line may be an inverted carry signal and the input of the other line may be a non-inverted carry signal. A differential buffer may be connected between the lines and the summing XOR gate to decouple the input of the carry propagate circuit from the capacitive loading of the XOR gate. One of the inputs to the differential buffer circuit may be connected to the input of one of the carry propagate lines and the other input of the differential buffer may be connected to the input of the other carry propagate line. The single inverter on each line may be implemented by a differential buffer circuit which can be arranged to reduce the capacitive loading on each line in comparison to a conventional double inverter-type buffer.  
         [0052]     An example of an embodiment of a carry propagate circuit having two propagate lines is shown in  FIG. 7 .  
         [0053]     Referring to  FIG. 7 , a full adder circuit  301  comprises first and second carry propagate lines  351 ,  353  each having an input  355 ,  357  and an output  359 ,  361 . Each line includes a circuit for determining the value of the carry-out signal. The first line  351  is connected to pass gate  350  for generating {overscore (AH)} and also includes pass gate  360  for generating C IN H. The second line  352   353  is connected to pass gate  352  for generating {overscore (AH)} or {overscore (AH)}and also includes pass gate  362  for generating {overscore (C IN )}H or {overscore (C IN H)}.  
         [0054]     A differential buffer circuit  365  is connected between the carry inputs  355 ,  357  and a summing XOR gate (not shown) and has a first input  367  connected to the first carry input  355  and a second input  369  connected to the second carry input  357 . Advantageously, connecting a single input of the differential buffer to each carry propagate line effectively reduces the capacitive loading of the differential buffer on the carry propagate lines in comparison with the embodiment of  FIG. 4 , for example, since each line is connected to only one gate capacitance of an NMOS FET rather than two NMOS FET gate capacitances.  
         [0055]     A second differential buffer circuit  381  is connected to each carry propagate line and may be connected in a manner which preserves the polarity of the carry signal in the upper and lower outputs  359 ,  361 . The second differential buffer circuit is similar to that between the carry input lines and the summing XOR gate and fuictions in a similar manner, as described above. In particular, the differential buffer comprises first and second FET&#39;s  383 ,  385  in which the drain of the first FET is connected to the source of the second FET  385 . The differential buffer circuit also comprises third and fourth FET&#39;s  387 ,  389  in which the drain of the third FET  387  is connected to the source of the fourth FET  389 . The gates of the first and third FET&#39;s (which are preferably NMOS FET&#39;s) are connected to the inverse carry and non-inverted carry lines  357 ,  355 , respectively and the gates of the second and fourth FET&#39;s (which are preferably PMOS FETS) are cross-coupled to the drains of the third and first FET&#39;s, respectively.  
         [0056]     The reduction in capacitive loading of each carry propagate line provided by this circuit significantly increases the speed of the circuit, and the circuit exhibits good noise immunity due to its differential nature.  
         [0057]     In an alternative embodiment, the differential buffer at the output of the circuit of  FIG. 7  may be replaced by one or more inverters in each line. At least one of these inverters is preferably connected differentially, cross-coupled, between the carry propagate lines to preserve timing between the carry propagate lines and reduce the risk of a race condition between Cin and {overscore (Cin)}. However, one of the benefits of a differential buffer at the output of the propagate lines is the reduced capacitance since each line is loaded by the gate capacitance of an NMOS FET which is smaller than the input capacitance of a buffer which is typically provided by the gate capacitances of both an NMOS and PMOS FET.  
         [0058]     In another embodiment, one or more pass gates of the embodiment of  FIG. 7  may be replaced by a transmission gate.  
         [0059]      FIGS. 8 and 9  each show another embodiment of the present invention. The embodiments of  FIGS. 8 and 9  are similar to that shown in  FIG. 4 , and like parts are designated by the same reference numerals. The main difference between the embodiment shown in  FIG. 8  and that shown in  FIG. 4  is that in  FIG. 8 , the differential buffer connected to the input  107  of the carry propagate line has been replaced by an alternative embodiment of a capacitive reduction or decoupling means to reduce the capacitive loading on the carry propagate input resulting from the input capacitance of a logic circuit (e.g. summing XOR gate) to which it is connected. In this embodiment, the capacitive decoupling means comprises a transistor  161 , for example an FET, e.g. NMOS or PMOS having a source, drain and gate, in which the gate is connected to the carry propagate input  107 . The capacitive decoupling or reduction circuit further comprises a resistive load  164  coupled between the transistor  161  and the voltage rail  169 . If the transistor  161  comprises an FET, either the drain or source may be connected to the resistive load  164 . The other of the drain and the source of an FET implemented transistor  161  is connected to ground. In this embodiment, the capacitive decoupling circuit outputs {overscore (C BUF  )} at the junction between the transistor  161  and the resistive load  164  for input to a logic circuit. In another embodiment, the control input (e.g. gate) of the transistor  161  can be connected to the output of the first inverter  151 , in which case the capacitive decoupling circuit would output C BUF  to be input to a logic circuit connected thereto.  
         [0060]     The resistor or resistive load  164  can be implemented by any suitable means such as n-type or a p-type transistor. In another embodiment, the resistive load may comprise a device that can be implemented as a resistor such as a bipolar device, a length of poly (e.g. poly silicon) or any other device.  
         [0061]     Referring to the embodiment shown in  FIG. 9 , the main difference between this embodiment and that shown in  FIG. 8  is that the first inverter  151  has been removed from the carry propagate circuit, in which the case output of the carry propagate circuit is {overscore (C)} OUT .  
         [0062]     Any of the full adder circuits disclosed herein may be used to implement a full adder of any size.  
         [0063]     In other embodiments, the various transistors used to implement the full adder circuit (or other circuit), may be of any other suitable type, for example bipolar. NMOS and PMOS FETS disclosed herein are illustrative examples only and any FET of either type disclosed herein may be replaced by any other type, as desired. Furthermore, any references herein to a source of an FET may be replaced by a reference to a drain, and vice versa.  
         [0064]     The principles of reducing the capacitive loading and load sharing provided by various aspects of the present invention may be applied to other circuits for increasing the speed of transmitting a (digital) signal.  
         [0065]     Thus, there has been shown and described several embodiments of a novel invention. As is evident from the foregoing description, certain aspects of the present invention are not limited by the particular details of the examples illustrated herein, and it is therefore contemplated that other modifications and applications, or equivalents thereof, will occur to those skilled in the art. The terms “having” and “including” and similar terms as used in the foregoing specification are used in the sense of “optional” or “may include” and not as “required”. Many changes, modifications, variations and other uses and applications of the present construction will, however, become apparent to those skilled in the art after considering the specification and the accompanying drawings. All such changes, modifications, variations and other uses and applications which do not depart from the spirit and scope of the invention are deemed to be covered by the invention which is limited only by the claims which follow.