Abstract:
An FPCA includes a scheme for peripheral routing that provides symmetrical routing across its entire area including the periphery by incorporating peripheral routing lines of equal length that are symmetrically deflected orthogonally. The symmetrical peripheral routing lines are connected to switch boxes and connection boxes at the periphery for maintaining constant routing channel width.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    This invention relates to a Field Programmable Gate Array (FPGA) incorporating peripheral routing with symmetrical edge termination at the boundaries. The invention also relates to a method for incorporating symmetrical edge termination at FPGA chip boundaries.  
           [0003]    2. Description of the Related Art  
           [0004]    FPGAs are programmable devices containing an array of programmable logic blocks connectable by programmable routing resources. IO pads at the chip periphery can interact with the core logic. The FPGA can be programmed to implement a wide range of circuits providing a large variety of designs. The efficiency of the implementation in terms of area and speed depends not only on the FPGA architecture, but also largely on effectiveness of the physical layout and interconnections. Automated software tools, known as automated Place &amp; Route, define the connectivity provided by programmable interconnections. The automated Place &amp; Route is a complex activity. An FPGA architecture that facilitates this activity can have a very considerably influence the quality of the output produced. A good architecture exploitable by the software is ideal. Symmetric architectures aid in the development of efficient software algorithms.  
           [0005]    The problem of maintaining of symmetry is acute in the regions neighboring the chip periphery. The worst affected is the routing architecture. The Xilinx Virtex device attempts to correct this problem by reflecting back the lines hitting the edge [ 12 ] as shown in FIG. 1. This approach successfully maintains constant channel width in the FPGA. But at the same time two other changes occur:  
           [0006]    1. A new switching module [ 11 ] is required to be defined at the periphery.  
           [0007]    2. The segments no longer adhere to the properties demonstrated in the core.  
           [0008]    A peripheral routing channel [ 13 ] is also introduced that is different from the core channel. These changes present new architectural components to be modeled by the software. These requirements introduce considerable complexities in the software algorithm resulting in inefficiencies and delays.  
           [0009]    The XC 4000 architecture is relatively simple with a connection box interfacing the terminating core routing channel to the peripheral segments. Moreover, the XC 4000 routing employs single length line segments.  
         BRIEF SUMMARY OF THE INVENTION  
         [0010]    An embodiment of this invention overcomes these drawbacks and provide an FPGA device that maintains symmetry in the interconnection routing even at the periphery. The FPGA establishes predictable and uniform routing delays and reduces the schematic and layout design time of the FPGA owing to the virtue of a uniform tile.  
           [0011]    An embodiment of the invention provides a scheme for peripheral routing that provides symmetrical routing across its entire area including the periphery by incorporating peripheral routing lines of equal length that are symmetrically deflected orthogonally. The symmetrical peripheral routing lines are connected to switch boxes and connection boxes at the periphery for maintaining constant routing channel width.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]    The objects and advantages of the invention will become more apparent in reference to the following description and the accompanying drawings, wherein:  
         [0013]    [0013]FIG. 1 shows peripheral routing according to the prior art.  
         [0014]    [0014]FIG. 2 shows vertical edge section of an FPGA according to the prior art  
         [0015]    [0015]FIG. 3 shows an embodiment peripheral routing according to the present invention.  
         [0016]    [0016]FIG. 4 shows a second embodiment of peripheral routing according to the present invention.  
         [0017]    [0017]FIG. 5 shows a third embodiment of peripheral routing according to the present invention 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0018]    A basic FPGA architecture comprising PLBs (Programmable Logic Blocks), switch boxes, and connection boxes has been described in the present embodiment. However it will be apparent to a person of ordinary skill in the art that the description is applicable to more complex architectures as well.  
         [0019]    [0019]FIG. 2 illustrates a vertical edge section of an FPGA. The FPGA includes an array of PLBs  21 , conductive routing segments  22 , core architecture switch boxes  22   a,  peripheral switch boxes  23   a,  core architecture connection boxes  22   b,  peripheral connection boxes  23   b,  and input/output (IO) pads  24  connected to each other to realize a programmable device. The segments [ 22 ] are staggered in the peripheral channel  13  for increased routing flexibility. Segments  22  start and finish at switch boxes [ 22   a,    23   a ]. Line segments spanning more than one PLB tend to cause asymmetry in the channel close to the periphery. As it will become apparent, this asymmetry is directly proportional to the composition of the channel. The segment length of the segments  22  constituting the channel chiefly contributes to the irregularities seen at the edge. The segment length in the present embodiment is kept at four quad lines (segments spanning four PLB faces), which doesn&#39;t necessarily imply spanning of four PLBs. The PLB sides traversed may be of the same PLB. As the segments approach the edge, they tend to extend beyond the last PLB. For instance, a quad line emerging from a switch box adjacent to the last PLB would tend to finish at a switch box  4  PLB sides away. Due to non-existence of such a PLB the line would end abruptly or would have to be done away with. This would lead to an unbalanced architecture.  
         [0020]    The present invention maintains architectural symmetry by orthogonal deflection of the segment lines to produce orthogonally deflected segments  23 . The lines  23  are symmetrically deflected in the two possible orthogonal directions opposite to each other. In the embodiment shown in FIG. 3, each of the peripheral switch boxes  23   a  includes a west side  23   a W at which two segments  23  are connected, respectively. The segments exit the west side  23   a W of the switch box  23   a  in a westerly direction for a small distance and then are deflected orthogonally in opposite directions: one segment  23  being deflected to the north and the other being deflected to the south.  
         [0021]    In the embodiment of FIG. 4, each peripheral switch box  23   a  still is connected to two segments  23  extending in opposite directions. However, in FIG. 4, the two segments  23  exit from the north and south sides of the switch box  23   a,  respectively.  
         [0022]    The line segments retain their property of spanning four PLBs. As shown in FIG. 3 and FIG. 4 in the preferred embodiment, one IO pad [ 24 ] is associated per PLB tile. The implementation exploits the concept of virtual depth by visualizing IO pad [ 24 ] and the PLBs along the edge as PLBs in a virtual array extending beyond the edge. For example, a track originating from a switch box adjoining the PLB on the west edge and turning northwards may be virtually re-constructed by unfolding the bent line westward. The IOs and the abutting PLBs facing the IOs are then visualized as logic blocks extending beyond the edge.  
         [0023]    The switch box and connection box topologies can be retained from the core after inserting some lines in the channel induced at the periphery so as to maintain constant channel width. As shown in FIG. 4 side ( 23   a W) of a switch box at the periphery has its side facing the chip edge removed, but this does not have any adverse impact on its topology. A minor change in the connection box topology of the IO pads interfacing with the so-formed peripheral routing might arise due to differences between the PLB &amp; IO ports tapping the channel. However, the entire structure is a highly symmetrical, closed, well-knit peripheral routing framework.  
         [0024]    A common requirement is to have a peripheral channel  13  wider than the core routing channel  25 . FIGS. 3 and 4 delineate two of the many possible schemes to widen the peripheral channel in accordance with the invention. In FIG. 3, the side of each of the switch boxes  23   a  facing the edge is utilized to induce a supplementary channel [ 23   b ]. In FIG. 4, the bent segments are not terminated at a switch box. A 3-sided switch box [ 23   a ] accommodates the extra lines in two of its three sides. One of its sides [ 23   a E] acts as a receptor of lines ending from the channel [ 22 ], similar to that shown in FIG. 3, but not shown in FIG. 4 for simplicity. Connection boxes  23   b  for IO pad and PLB interface are inserted between the peripheral switch boxes [ 23   a].    
         [0025]    Another embodiment illustrated in FIG. 5 accomplishes the object of the invention by merging lines  23  deflected from adjacent core channels  25   a,    25   b.  The lines are merged in a manner to retain their common segment length of four, although other common segment lengths could be employed. In FIG. 5, a quad line is redefined as a segment spanning four PLBs, and not PLB sides as stated in earlier embodiments. An auxiliary channel  25   c  is also introduced with properties similar to the one in FIG. 4.  
         [0026]    As will be appreciated by those skilled in the art, the proposed peripheral routing scheme results in a highly symmetric, easy to build architecture with low complexity in all domains. Many more embodiments are possible in the light and spirit of the present invention. For example, line segments of lengths other than four in a channel can be handled effectively in other possible embodiments. A line segment can be redefined to suit a particular architecture with the re-characterization altering the PLBs spanned by a segment at the periphery.  
         [0027]    All of the above U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety.  
         [0028]    From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.