Abstract:
Methods for isotropically etching a monocrystalline silicon wafer. An example method includes applying a layer of material at least one of onto a first side or into a first side of the monocrystalline silicon wafer and isotropically etching a non-linear pit into the monocrystalline silicon wafer using an anisotropic etchant. The applied layer of material has a faster etch rate than the monocrystalline silicon wafer.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    Etchants that are chemical bases such as Potassium Hydroxide (KOH), Sodium Hydroxide (NaOH), Ethylene-Diamine-Pyrocatechol (EDP), and Tetra-Methyl Ammonium Hydroxide (TMAH) etch the (100) planes of monocrystalline silicon faster than other crystal planes. These etchants etch the (111) planes the slowest. Therefore, these etchants will preferentially etch in the &lt;100&gt; crystallographic direction. The etch rate in the &lt;111&gt; direction is much slower: 20 to 400 times slower (depending on the etchant, concentration and temperature) than in the &lt;100&gt; direction. Employing one of these etchants to etch a masked wafer, patterned with square or rectangular features, will result in the formation of an etch pit with a V-shaped cross section. For this reason these chemicals are called anisotropic etchants. See  FIGS. 1A-D . 
         [0002]    The motivation shown in the prior art is to use isotropic etchants to isotropically etch and to use anisotropic etchants to anisotropically etch. 
       SUMMARY OF THE INVENTION 
       [0003]    The present invention provides a method for isotropically etching a monocrystalline silicon wafer. An example method includes applying a layer of material at least one of onto a first side or into a first side of the monocrystalline silicon wafer and isotropically etching a non-linear pit into the monocrystalline silicon wafer using an anisotropic etchant. The applied layer of material has a faster etch rate than the monocrystalline silicon wafer. 
         [0004]    In one aspect of the invention, the applied layer of material includes polysilicon, amorphous silicon, or a fast etching material. 
         [0005]    In another aspect of the invention, an etch accelerant is applied to the anisotropic etchant. The shape of the etch can be controlled by varying the concentration of etch accelerant during etching. 
         [0006]    In still another aspect of the invention, the pit includes a width and depth dimensions that are controlled according to at least one of the applied materials or the composition of the anisotropic etchant. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]    Preferred and alternative embodiments of the present invention are described in detail below with reference to the following drawings: 
           [0008]      FIGS. 1A-D  illustrate a conventional anisotropic etching process; and 
           [0009]      FIGS. 2-5  illustrate a number of embodiments showing isotropic etching performed using anisotropic etchants. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0010]      FIGS. 2A-2D  illustrates steps in performing an isotropic etch using anisotropic etchants. A monocrystalline silicon wafer  60  has a layer  62  of polysilicon or amorphous silicon deposited on a surface. A hard mask layer  64  is applied over the polysilicon or amorphous silicon layer  62 . As shown in  FIG. 2B , the hard mask layer  64  is patterned and etched according to a predefined pattern in order to expose a predefined section of the polysilicon or amorphous silicon layer  62 . 
         [0011]    As shown in  FIG. 2C , an anisotropic wet etchant such as hydroxide etchants (e.g., NaOH, KOH) are applied to the surface of the hard mask layer  64  and the polysilicon or amorphous silicon layer  62 , thus causing isotropic etching of the polysilicon or amorphous silicon layer  62  and the crystalline silicon wafer  60 . The anisotropic etchant etches the polysilicon or amorphous silicon layer  62  faster laterally than the monocrystalline silicon wafer  60 . This is because each polysilicon crystal has the slow etching (111) planes randomly oriented with respect to neighboring silicon crystals. Because the (111) planes are randomly oriented they will not impede the lateral etch rate. An amorphous silicon layer  62  lacks the slow etching (111) plane entirely. Thus, a circular shaped pit  70  is produced thereby performing some undercutting of the hard mask layer  64  and producing essentially an isotropic etch pattern. The hard mask layer  64  is then removed. ( FIG. 2D ). The hard mask layer  64  is patterned and removed using standard photolithography techniques. 
         [0012]    The width and depth of the etched circular pit  70  can be controlled by varying the ratio of the width of the hard mask opening to the thickness of the polysilicon or amorphous silicon layer  62 . 
         [0013]    In another embodiment of the present invention, the polysilicon or amorphous silicon layer  62  has been stressed during deposition on to the monocrystalline silicon wafer  60 . Stressing is preformed by controlling deposition rate and temperature. Tensile stress increases the reactivity of the silicon. Stress levels varying from 100 to 1000 Megapascals (MPa) can be easily obtained. 
         [0014]      FIGS. 3A-D  shows an alternate process for isotropically etching using an anisotropic etchant. A layer of fast etching material  106  is deposited on a monocrystalline silicon wafer  104 . The etch rate of the fast etching material can be as low as less than a μm/minute or as high as 400 μm/minute. A hard mask layer  108  is applied over the deposited fast etching layer  106  and is then partially removed in order to expose the desired portion of the fast etching layer  106  similar to  FIG. 2B . Next, an anisotropic etchant is applied to the fast etching layer  106  to etch the fast etching layer  106  and the monocrystalline silicon wafer  104  in an isotropic manner, thereby undercutting the hard mask layer  108 . The hard mask layer  108  is then removed to fully expose the etched circular pit. Example fast etching materials include silicon dioxide (SiO 2 ), Ti, and Al. The ratio of the fast etching material etch rate to the silicon etch rate can vary from being as low as 1.1:1 to as high as 400:1. 
         [0015]      FIGS. 4A-D  show a wafer having a monocrystalline silicon wafer  124  with deposited fast-etching layer  126  similar to that as shown in  FIGS. 3A-D . However, as shown in  FIG. 4C , the layer of fast-etching material  126  and the monocrystalline silicon wafer  124  are etched by a solution that contains an anisotropic etchant and a etch accelerant that will increase the etch rate of the fast etching material. The etch accelerant increases the etch rate ratio of the fast etching material layer  126  and the silicon wafer  124 . The result is a pattern ( FIGS. 4C  and D) whereby the sidewall pattern is S-shaped with heavy undercutting of the fast etching material layer  126  under a hard mask layer  128 . The type of geometry that can be accomplished can vary a great deal depending upon the concentration of the etch accelerant and the variation of this concentration during the etching process. Possible etch accelerants include hydrogen peroxide (H 2 O 2 ) and potassium fluoride (KF). 
         [0016]    While the preferred embodiment of the invention has been illustrated and described, as noted above, many changes can be made without departing from the spirit and scope of the invention. Accordingly, the scope of the invention is not limited by the disclosure of the preferred embodiment. Instead, the invention should be determined entirely by reference to the claims that follow.