Abstract:
A shield cap and a semiconductor package including a shield cap provide protection for passive components mounted on a substrate of a semiconductor package. The shield cap provides a means for manufacturing a semiconductor package that includes a semiconductor die and passive components without encapsulating the passive components within the encapsulation protecting the semiconductor die. The shield cap provides electromagnetic shielding and physical protection for the passive components and may provide thermal conduction from a semiconductor die by contacting the semiconductor die. The shield cap may be perforated to permit air circulation through the shield cap for providing improved thermal performance or may be a solid metal shield, providing improved electromagnetic shielding.

Description:
FIELD OF THE INVENTION 
     The present invention relates generally to integrated circuit packaging and more specifically, to semiconductor packaging methods and assemblies for packaging integrated circuit dies along with passive elements. 
     BACKGROUND OF THE INVENTION 
     Semiconductor packages are fabricated in various structures, but all of the structures generally include an encapsulation around a semiconductor die that includes integrated electronic circuits. The encapsulation provides protection from external environments. A substrate, such as a lead frame, a printed circuit board (PCB), a circuit film, a circuit tape, or a similar structure is included for interconnecting various input/output signals to and from the semiconductor die. 
     Among the differing types of semiconductor packages, there are semiconductor packages including passive components, such as resistors R, capacitors C, inductors L, and other passive components mounted within the semiconductor package. One such semiconductor package for a self-contained system has the passive components mounted on a surface of a substrate described above, such as the resistors, the capacitors, and the inductors. Another semiconductor package includes passive components and semiconductor dies mounted to one face of a substrate, and solder balls fused to the other face of the substrate. This second type of semiconductor package is used to reduce the size of the semiconductor package where otherwise a large area would be required if the semiconductor dies and the passive components were mounted on the same face of the substrate. 
     As the semiconductor packages are included within mobile modules and radio frequency (RF) devices such as cellular phones and Personal Digital Assistants (PDAs), the semiconductor packages are required to have excellent thermal properties to provide product reliability. However, since the above-described prior art semiconductor packages have passive components encapsulated along with the semiconductor dies, they have poor heat dissipation characteristics. 
     Therefore, it would be desirable to provide a semiconductor package including passive components that has improved heat dissipation characteristics. 
     SUMMARY OF THE INVENTION 
     The above stated objectives are achieved in a shield cap and semiconductor package including a shield cap whereby a semiconductor die is packaged in conjunction with passive elements. The semiconductor package assemblies include at least one passive component, a substrate with a central cavity for mounting a semiconductor die and a shield cap attached to the bottom surface of the substrate for covering and protecting the passive components. The substrate includes multiple electrically conductive patterns formed on the top surface and bottom surface and the electrically conductive patterns on the bottom surface include mounting pads for mounting the passive components. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a sectional view of a semiconductor package including passive components and a shield cap in accordance with one embodiment of the present invention; 
     FIG. 2 illustrates a perspective view of the shield cap of FIG. 1; 
     FIG. 3 illustrate a sectional view of a semiconductor package including passive components and a shield cap in accordance with another embodiment of the present invention; and 
     FIG. 4 illustrates a perspective view of the shield cap of FIG.  3 . 
    
    
     The invention, as well as a preferred mode of use and advantages thereof, will best be understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings, wherein like reference numerals indicate like parts throughout. 
     DETAILED DESCRIPTION 
     Referring to FIG. 1, a sectional view of a semiconductor package  100  including passive components  10  in accordance with one embodiment of the present invention is illustrated. Semiconductor package  100  includes a semiconductor die  1 , a substrate  3  including a cavity  38  for placing the semiconductor die  1  within, a plurality of solder balls  7  each for conducting an electrical signal between semiconductor die  1  and the outside of substrate  3 , a plurality of passive components  10  mounted to a second conductive layer  33  of substrate  3 , an encapsulant  5  encapsulating semiconductor die  1  and covering cavity  38  for protecting exposed circuit patterns, and a shield cap  20  for protecting passive components  10 . 
     Semiconductor die  1  is fabricated by forming a pure SiO 2  crystal extracted from sand and cut to form a wafer, and forming an integrated circuit on one face thereof. The semiconductor die  1  is in general square or rectangular, with a plurality of bond pads  1   a  formed on the face of the integrated circuit for connection of electrical signals to and from the integrated circuit. Bond pads  1   a  are arranged on one line on the periphery or a central part of the semiconductor die  1 . Bond pads  1   a  are connected to a plurality of bond fingers  32   a  of a first conductive layer  32  on substrate  3  for interconnecting the electrical signals of semiconductor die  1 . 
     Semiconductor die  1  is mounted in cavity  38 , which is formed in a central part of substrate  3 . Substrate  3  includes first conductive layer  32  and second conductive layer  33  for connection of electrical signals through bond pads  1   a  on the semiconductor die  1 . First conductive layer  32  and second layer  33  are formed on opposite side of a dielectric layer  34 . First conductive layer  32  and second conductive layer  33  are electrically connected to each other by a plurality of conductive vias  36 . 
     After semiconductor die  1  is placed in cavity  38 , a plurality of wires  9  are bonded between bond pads  1   a  of the semiconductor die  1  and bond fingers  32   a  of the substrate  3  to electrically connect semiconductor die  1  and substrate  3 . Wires  9  may be any conductive material such as aluminum (Al), gold (Au), copper (Cu) or an equivalent. While bonding wires  9  to bond pads  1   a  and bond fingers  32   a , each end of the wires are exposed to a momentary high temperature, generated by an over-voltage applied to melt the ends, welding wires  9  onto bond pads  1   a  and bond fingers  32   a.    
     After wires  9  are bonded, semiconductor die  1  is encapsulated. Semiconductor die  1  is encapsulated to protect semiconductor die  1  against external environments. Bond fingers  32   a  and wires  9  are also subject to oxidation and impact breakage if substrate  3  and wires  9  are exposed to the exterior. Therefore, wires  9  and bond fingers  32   a  are also encapsulated. Epoxy Mold Compound (EMC) is a preferred encapsulant for forming encapsulation  5 . The EMC is molded in a metal mold with pressure and heat. Recently powder epoxy and paste epoxy are used, which directly coated on the assembly and fixed via pressure and/or heat. Solder balls  7  are attached to surfaces except the central encapsulated part of the substrate  3 . Solder balls  7  provide external electrical connections for semiconductor package  100 . Electrical signals reach semiconductor die  1  and passive components  10  via first and second conductive layer  32  and  33  of substrate  3  from solder balls  7  provided on the exterior of semiconductor package  100 . Solder balls  7  are fused to a plurality of lands  32   b  of first conductive layer  32 . 
     As described above, passive components  10  are mounted to second conductive layer  33 , which opposes first conductive layer  32 . As passive components  10  are mounted within semiconductor package  100 , the semiconductor package becomes a stand-alone processing system. Shield cap  20  is attached to the face of substrate  3  to which passive components  10  are mounted. A perspective view of the shield cap  20  is illustrated in FIG.  2 . 
     Referring now to both FIG.  1  and FIG. 2 shield cap  20  is rectangular or square and of a size substantially equal to the outline of the semiconductor package. Shield cap  20  includes a vertical wall  21  on each side. Vertical wall  21  contacts substrate  3  forming a space within for accommodating passive components  10 . Shield cap  20  include a base panel  23  in a lower part thereof for covering the passive components  10 , and a heat dissipation portion  24  projecting from a central part of base panel  23 . Heat dissipation portion  24  is of an area similar to do the area of semiconductor die  1 . The material of the shield cap  20  may be any metal material such as aluminum, copper or an equivalent. 
     Heat dissipation portion  24  has a height great sufficient to provide contact with semiconductor die  1  when shield cap  20  is attached to the bottom of substrate  3 . Base panel  23  includes a plurality of holes  22  formed through shield cap  20 . The shape of the holes  22  is not limited by the illustration and may be any shape. 
     Shield cap  20  is attached to the bottom of the substrate  3  and covers passive components  10 . When the top surface of the heat dissipation part  24  is brought into surface to surface contact with the bottom of the semiconductor die  1 , a space is formed between the bottom of substrate  3  and base panel  23  of the shield cap  20 . Prior to mounting of shield cap  20 , passive components  10  are disposed in this space. Therefore, the passive components  10  are protected not by encapsulant  5  but are protected by shield cap  20  covering passive components  10 . 
     Shield cap  20  serves to not only protect passive components  10 , but also provides heat dissipation. Shield cap  20  is attached to the semiconductor die  1  and substrate  3  for effective heat dissipation from semiconductor die  1  and the passive components  10 . 
     Further, malfunction of the passive components  10  caused by external electromagnetic waves can be eliminated, as base panel  23  of shield cap  20  shields passive components  10  from external electromagnetic waves. 
     Referring now FIG. 3, a semiconductor package  200  in accordance with an alternative embodiment of the invention is depicted. Semiconductor package  200  is similar to semiconductor package  100  of FIG. 1, but includes a different shield cap  20 ′ as shown. Referring additionally to FIG. 4, shield cap  20 ′ as shown in FIG. 3 and 4 has no holes, improving electromagnetic shielding around passive components  10 . 
     Since the semiconductor packages of the present invention have passive components mounted to a second conductive layer of a substrate, the total area of the semiconductor package can be reduced and more passive components may be mounted therein. Additionally, the shield cap of the present invention provides physical protection of the passive components, shielding from external electromagnetic waves, and heat dissipation from the semiconductor die and the passive components to the exterior. 
     This disclosure provides exemplary embodiments of the present invention. The scope of the present invention is not limited by these exemplary embodiments. Numerous variations, whether explicitly provided for by the specification or implied by the specification, such as variations in structure, dimension, type of material and manufacturing process may be implemented by one of skill in the art in view of this disclosure.