Abstract:
Methods and apparatuses for providing a dummy load in a power converter are disclosed. The power converter has a primary winding and a secondary winding isolated from each other. The secondary winding can de-energize to provide an output voltage at an output node for powering a load. The winding voltage at across the secondary winding is sensed to provide a non-switching time, which is checked if it exceeds a predetermined reference time. The output voltage is compared with a predetermined safe voltage. A discharge current is provided as a dummy load to drain from the output node and to lower the output voltage if the on-switching time exceeds the predetermined reference time and the output voltage exceeds the predetermined safe voltage.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims priority to and the benefit of U.S. provisional application Ser. No. 62/007,476 filed on Jun. 4, 2014, which is incorporated by reference in its entirety. 
     
    
     BACKGROUND 
       [0002]    The present disclosure relates generally to power supplies, and more particularly to apparatuses and control methods for providing dummy loads to power supplies under primary-side control. 
         [0003]    The battery run time, the duration when a portable device is operable under the power supplied by its own batteries, means a lot to users. A short battery run time troubles user in non-operable device or frequently charging. To make battery run time longer, the capacity of the batteries in portable devices becomes larger. Aside effect of the batteries with larger capacity is a longer charging time which is required for a battery charger to charge the batteries to a full condition. Some manufactories of battery chargers have developed methods for quickly charging batteries, so users need not wait so long to fully charge their portable devices. 
         [0004]    A common methodology of quickly charging batteries is to increase the output voltage supplied by a battery charger. For example, a USB port of a charger has an output rating voltage about 5V, but that charger, if equipped with the ability of quickly charging, might boost its output voltage up to between 9V and 12V to charge a portable device. Nevertheless, a portable device that is to be charged by a 9V input voltage must be specially designed to sustain a so-high charge voltage. Otherwise, that portable device could be over stressed and suffer damage. 
         [0005]    To be backward compatible with old-version portable devices that are unable to sustain a high-charge voltage, the output voltage of a battery charger with the ability of quickly charging must lower its output voltage down to its output rating voltage quickly after a portable device is removed, so that the charger won&#39;t damage any of old-version portable devices that does not support quickly charging and is next connected to the output port of the charger. 
         [0006]    Demonstrated in  FIG. 1  is a conventional charger  100  with the ability of quickly charging, for charging the load  104 . The charger  100  has an isolation topology, with a primary side and a secondary side isolated from each other by a transformer. Voltages at the primary side substantially reference to input ground GND IN , while voltages at the secondary side to output ground GND OUT . As illustrated in  FIG. 1 , a power controller  108  in the primary side turns ON and OFF a power switch  106  so as to control the current through a primary winding PRM. When power switch  106  is turned ON, the current through the primary winding PRM increases and the transformer energizes; when it is turned OFF, the transformer de-energizes and the secondary winding SEC outputs a current to build output voltage V OUT . The auxiliary winding AUX, the secondary winding SEC, and voltage divider  110  cooperate to provide information in association with the output voltage V OUT , and power controller  108  accordingly provides pulse-width-modulation (PWM) signal S DRV  to control power switch  106 . This type of control is commonly referred to as primary side control (PSR), which detects output voltage V OUT  by way of the induced voltage of a transformer, rather than through a photo-coupler. The charge  100  includes a dummy load R DUM , which is capable of lowering the output voltage V OUT  down to a safe level when the load  104  is removed or becomes a light load. 
         [0007]    The presence of the dummy load R DUM  causes disadvantages in view of power conversion, because it constantly consumes electric power no matter the load  104  exists or not. Therefore, the dummy load R DUM  is not suitable for advanced chargers, especially for those seeking a higher power conversion rate. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]    Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following drawings. In the drawings, like reference numerals refer to like parts throughout the various figures unless otherwise specified. These drawings are not necessarily drawn to scale. Likewise, the relative sizes of elements illustrated by the drawings may differ from the relative sizes depicted. 
           [0009]    The invention can be more fully understood by the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0010]      FIG. 1  shows a conventional charger with the ability of quickly charging; 
           [0011]      FIG. 2  shows a charger in accordance with embodiments of the invention; 
           [0012]      FIG. 3  shows a control method suitable for use in the dummy-load control unit of  FIG. 2 ; 
           [0013]      FIG. 4  exemplifies the dummy-load control unit in  FIG. 2 ; 
           [0014]      FIG. 5  demonstrates the waveforms of the PWM signal S DRV , the winding voltage V SEC , and the comparison result S NO-SWT ; 
           [0015]      FIG. 6  shows, from top to bottom, the waveforms of the comparison result S NO-SWT  the timeout signal S DIS-1 , and the timeout signal S DIS-2 ; 
           [0016]      FIG. 7  demonstrates another dummy-load control unit  202   a  according to embodiments of the invention; 
           [0017]      FIG. 8  shows another charger according to embodiments of the invention; and 
           [0018]      FIG. 9  exemplifies the dummy-load control unit in  FIG. 8 . 
       
    
    
     DETAILED DESCRIPTION 
       [0019]      FIG. 2  shows a charger  200  in accordance with embodiments of the invention. The charge  200  in  FIG. 2  has a detection resistor R DET , a discharge resistor R DIS , and a dummy-load control unit  202 , but lacks the dummy load R DUM  in  FIG. 1 . If the dummy-load control unit  202  determines the load  104  is a light load or no load, it internally provides a dummy load to discharge the output node OUT, preventing the output voltage V OUT  from over-high. The output rating voltage of the charger  200  is 5V, meaning that the output voltage V OUT  is regulated to be 5V when the load  104  is a light load or a no load. When the dummy-load control unit  202  determines the load  104  is heavier than a light load, it stops providing the dummy load, so that the power conversion rate is kept high. 
         [0020]    The dummy-load control unit  202  detects winding voltage V SEC  via the detection resistor R DET . The dynamic signal of the winding voltage V SEC  carries load information based on which the dummy-load control unit  202  determines whether the load  104  is a normal load, a light load or a no load. In this specification, a normal load means the load  104  is heavier than a predetermined value, and a light load or no load means the load  104  is lighter than the predetermined value. In case that the dummy-load control unit  202  deems the load  104  normal, it makes its discharge charge node DIS a high-impedance input node, substantially no current flowing through the discharge resistor R DIS  to keep power conversion rate high. If the dummy-load control unit  202  deems the load  104  being a light load or no load, and the output voltage V OUT  is over-high, then the dummy-load control unit  202  provides a discharge path from the discharge node DIS to output ground GND OUT . This discharge path conducts a discharge current to discharge the output node OUT and to quickly lower the output voltage V OUT  down to a safe level. Therefore, if the load  104  is replaced by another load, the output voltage V OUT  always starts at the safe level at most and causes no harm to the load. 
         [0021]      FIG. 3  shows a control method  300  suitable for use in the dummy-load control unit  202  of  FIG. 2 . In step  302 , dummy-load control unit  202  senses the winding voltage V SEC  via the detection resistor R DET . Step  304  determines a non-switching time T NO-SWT  when the power switch in the primary side is not switched to change its condition based on the winding voltage V SEC . For example, the non-switching time T NO-SWT  could be the duration when the winding voltage V SEC  continues not to go across a reference voltage V REF . Step  306  decides whether the non-switching time T NO-SWT  exceeds a predetermined reference time T OUT-1 . A positive answer of step  306  likely could mean the load  104  is a light load or no load at this moment, so step  308  follows, providing a discharge current I DIS-1  to discharge the output node OUT. Step  310  further determines whether the non-switching time T NO-SWT  exceeds another predetermined reference time T OUT-2  longer than the predetermined reference time T OUT-1  and whether the output voltage V OUT  is over-high, e.g. exceeding a predetermined safe level V SAFE . If each of the inquiries in step  310  has a positive answer, it seems like that quickly charging just completes or ends, and step  314  follows to provide another discharge current I DIS-2  which, larger than the discharge current I DIS-1 , discharges the output node OUT via the discharge resistor R DIS . If any of the answers in steps  310  and  306  is negative, step  304  follows. 
         [0022]      FIG. 4  exemplifies the dummy-load control unit  202 . A Zener diode  240  limits the highest and lowest voltages at the detection node DET. In  FIG. 4 , the detection voltage V DET  at the detection node DET is kept substantially above 0V. A comparator  220  compares the detection voltage V DET  with a reference voltage V REF , which is 4V in  FIG. 4  for instance. In another embodiment of the invention, the reference voltage V REF  is not a constant, but in association with the output voltage V OUT  instead, and equal to 0.8*V OUT  for example. If the winding voltage V SEC  exceeds 0V, the detection voltage V DET  could be substantially the same with the winding voltage V SEC  The comparator  220  outputs a comparison result S NO-SWT . 
         [0023]    Timeout detector  222  mainly detects a duration when the comparison result S NO-SWT  does not change its logic value, and this duration is deemed as a non-switching time T NO-SWT . In one embodiment, if the non-switching time T NO-SWT  is longer than the predetermined reference time T OUT-1 , the timeout detector  222  outputs “1” in logic; otherwise, it outputs “0”. In another embodiment, the timeout detector  222  acts as a debounce circuit and has its output “1” only if the comparison result S NO-SWT  lasts to be “1” in logic for the predetermined reference time T OUT-1 . The output of the timeout detector  222 , while having “1” in logic, sets the SR flip flop  226  and resets the counter  224 , which then starts to count from number “0”. The comparison result S NO-SWT  is also fed to the clock input of the counter  224 , which calculates how many times the comparison result S N0-SWT  turns to be “1” from “0”. When the calculation result of the counter  224  exceeds a certain number, 32 as shown in  FIG. 4  for example, the SR flip flop  226  is reset. A timeout signal S DIS-1  at the non-inverted output Q of the SR flip flop  226 , while in logic “1”, makes the switch  236  a short circuit, so a constant current source  234  generates discharge current I DIS-1  to drain charges from power node VCC, equivalently discharging the output node OUT of  FIG. 2 . 
         [0024]    A debounce circuit  228 , coupled to the non-inverted output Q of the SR flip flop  226 , has a timeout signal S DIS-2  at its own output “1” in logic only if timeout signal S DIS-1  lasts to be “1” for at least a predetermined time duration T OUT-DIF . Otherwise, the timeout signal S DIS-2  remains “0” in logic. An And gate  232  and a comparator  230  together control a switch  238 . When the output voltage V OUT  at power node VCC exceeds a predetermined safe voltage V SAFE  which is 5.8V in  FIG. 4  for example, and when the timeout signal S DIS-2  is “1”, the switch  238  is switched ON, providing a discharge path for discharging the output node OUT in  FIG. 2 . It is equivalent to say that the non-switching time T NO-SWT  must exceed the summation of the predetermined time duration T OUT-DIF  and the predetermined reference time T OUT-1  to make the timeout signal S DIS-2  “1”, where this summation is referred to as another predetermined reference time T OUT-2 . 
         [0025]      FIG. 5  demonstrates the waveforms of the PWM signal S DRV , the winding voltage V SEC  and the comparison result S NO-SWT . One period of time when power switch  106  is ON is referred to as an ON time T ON , and in the opposite one period of time when it is OFF is called an OFF time T OFF . One ON time T ON  and one OFF time T OFF , adjacent to each other, are called a cycle time T CYC . During an OFF time T OFF  after the secondary winding SEC completes de-energizing, the winding voltage V SEC  starts oscillating due to an LC tank in the primary side and this oscillation dampens over time because power steadily dissipates during oscillation. The comparison result S NO-SWT  is generated by comparing the winding voltage V SEC  with 4V as shown in  FIG. 5 , and defines a non-switching time T NO-SWT . Also demonstrated in  FIG. 5  is a much longer non-switching time T NO-SWT , which starts at the moment when the magnitude of the oscillating winding voltage V SEC  is less than 4V. 
         [0026]      FIG. 6  shows, from top to bottom, the waveforms of the comparison result S NO-SWT  the timeout signal S DIS-1 , and the timeout signal S DIS-2 . As the comparison result S NO-SWT  changes quickly within the time period from moment t 0  to moment t 1 , each non-switching time T NO-SWT  within this time period is too short, and therefore both timeout signals S DIS-1  and S DIS-2  remain “0” in logic. After moment t 1 , the non-switching time T NO-SWT  constantly increases as long as the comparison result S NO-SWT  is kept to be “1”. As demonstrated in  FIG. 6 , the non-switching time T NO-SWT  is deemed to be the duration when the comparison result S NO-SWT  continues staying at “1”. When the non-switching time T NO-SWT  is longer than the predetermined reference time T OUT-1 , the timeout signal S DIS-1  turns to “1” in logic; and when it is further longer than the predetermined reference time T OUT-2 , the timeout signal S DIS-2  also turns to “1” in logic. Starting from moment t 2 , the comparison result S NO-SWT  remains unchanged no more, possibly because PWM signal S DRV  toggles and another cycle time T CYC  starts. 
         [0027]    Because of the counter  224 , the timeout signal S DIS-1  is reset to be “0” at moment t 3  when the comparison result S NO-SWT  has generated 32 pulses in view of its waveform. It is derivable from  FIG. 4  that a timeout signal S DIS-1  with “0” in logic also makes the timeout signal S DIS-2  “0”. Please note that, once the discharge current I DIS-1  in  FIG. 4  starts discharging output node OUT, the discharging will last at least for a certain period of time before it is stopped, and this certain period of time (a discharge time) is 32 clock pulses defined by the comparison result S NO-SWT . 
         [0028]    In order to let dummy-load control unit  202  operate properly, it would be better to make the power controller  108  output PWM signal S DRV  with requirements under corresponding specific conditions, thereby the power controller  108  hand-shaking with dummy-load control unit  202 . In the embodiment shown in  FIG. 2 , PWM signal S DRV  has a first minimum cycle time T CYC-MIN-NORMAL  which is 1/(20 kHz) for example, if the power controller  108  determines the load  104  is a light load or no load, and the output voltage V OUT  is well regulated at about the output rating voltage, 5V. In another case that the power controller  108  determines the present load  104  is a light load or no load, and the output voltage V OUT  is a high charging voltage exceeding the predetermined safe voltage V SAFE , which is 5.8V, then PWM signal S DRV  has a second minimum cycle time T CYC-MIN-QH  which is 1/(1 kHz) for example. The embodiment in  FIG. 2  is better to have the predetermined reference time T OUT-1  less than the first minimum cycle time T CYC-MIN-NORMAL  and the predetermined reference time T OUT-2  between the first minimum cycle time T CYC-MIN-NORMAL  and the second minimum cycle time T CYC-MIN-QH . 
         [0029]    The dummy-load control unit  202  in  FIG. 2  could know how heavy or light the load  104  is by sensing the length of the non-switching time T NI-SWT  rather than by directly sensing the current through the load  104 . 
         [0030]    Once a non-switching time T NO-SWT  has exceeded the predetermined reference time T OUT-1 , it can be expected by the dummy-load control unit  202  that the load  104  is presently a light load or no load. In response, the dummy-load control unit  202  conducts the discharge current I DIS-1  to slightly discharge output node OUT, so as to prevent output voltage V OUT  from further increasing and running away from the output rating voltage (5V). This output voltage run-away could result from RSC that need to periodically energize the transformer in order to sense output voltage V OUT  from the primary side. 
         [0031]    Once a non-switching time T NO-SWT  is very long and exceeds the predetermined reference time T OUT-2  the dummy-load control unit  202  can reasonably assume not only that the load  104  was quickly charged under a high charging voltage, but also the load  104  has become a light load or no load possibly, probably because the charging to the load  104  has completed or the load  104  is removed. Since a light load or no load requires a high charging voltage no more, the output voltage V OUT  at output node OUT should return to its output rating voltage (5V) as soon as possible, not to cause overvoltage damage or stress to another load that is next connected for charging. Accordingly, when a non-switching time T NO-SWT  exceeds the predetermined reference time T OUT-2  the discharge current I DIS-2  larger than the discharge current I DIS-1 , is provided to quickly pull down the output voltage V OUT , unit the output voltage V OUT  is below the predetermined safe voltage V SAFE . 
         [0032]    When the load  104  is normal, heavier than a light load, the cycle time of the PWM signal S DRV  should be less than the first minimum cycle time T CYC-MIN-NORMAL  or preferably less than the predetermined reference time T OUT-1 . Therefore, when the load is normal, both the discharge currents I DIS-1  and I DIS-2  are stopped from discharging the output node OUT, and the dummy-load control unit  202  contribute only ignorable power consumption to the whole power system, causing substantially no harm to power conversion efficiency. 
         [0033]    The discharge currents I DIS-1  and I DIS-2  drain current from power node VCC and discharge node DIS respectively, but this invention is not limited to.  FIG. 7  demonstrates another dummy-load control unit  202   a  according to embodiments of the invention, where both the charge currents I DIS-1  and I DIS-2  drain current from discharge node DIS to output ground GND OUT . 
         [0034]      FIG. 8  shows another charger  400  according to embodiments of the invention. The common devices or the similar devices between  FIG. 8  and  FIG. 2  could be comprehensible by the aforementioned teaching so their details are omitted herein for brevity.  FIG. 9  exemplifies the dummy-load control unit  402  in  FIG. 8 , where the discharge current I DIS-2 , if exists, flows from output node OUT, via power node VCC, switch  238 , discharge node DIS, discharge resistor R DIS , and to output ground GND OUT . The dummy-load control unit  402  in  FIGS. 8 and 9  is beneficial in that the discharge node DIS therein need not support or sustain the high charging voltage possibly occurring at output node OUT. In other words, the circuitry for the discharge node DIS in  FIGS. 8 and 9  could be simpler and cheaper than that for the discharge node DIS in  FIGS. 2 and 4 . 
         [0035]    While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.