Abstract:
A semiconductor device can include wiring lines on a substrate and an interlayer insulating structure, between ones of the wiring lines. The wiring lines can include a pore-containing layer that includes a plurality of pores extending away from a surface of the substrate, wherein ones of the pores have respective volumes that increase with a distance from the substrate until reaching an air gap layer above the pore-containing layer and beneath uppermost surfaces of the wiring lines.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2013-0044320, filed on Apr. 22, 2013, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference. 
       BACKGROUND 
       [0002]    The inventive concept relates to the field of semiconductor devices and in particular, to interconnection structures in semiconductor devices. 
         [0003]    Some examples of semiconductor devices include a memory device for storing data, a logic device for processing data, and a hybrid device capable of performing various memory storage and data processing functions. 
         [0004]    Semiconductor devices may operate at high speed and/or relatively low voltage. To provide desired operating characteristics, a semiconductor device may have a highly integrated density, that is, may have increased elements per area. However, an increase in the integration density may lead to a decrease in the reliability of the semiconductor device. For example, in a Back-End-Of-Line (BEOL) step, copper (Cu) lines of a semiconductor device may be formed, however as the pitch of the interconnection lines decreases, the semiconductor device may suffer from an RC delay problem. To overcome this problem, a low-k dielectric material has been used as an inter-media dielectric (IMD). For example, an IMD structure having an air gap has been used. When the air gap is formed, however, various problems may arise. For example, if the interconnection lines have a large pitch, they may collapse. Otherwise, an insulating material may be absent, and thus, the device may suffer from low reliability. 
       SUMMARY 
       [0005]    According to example embodiments of the inventive concepts, a semiconductor device can include wiring lines on a substrate and an interlayer insulating structure, between ones of the wiring lines. The wiring lines can include a pore-containing layer that includes a plurality of pores extending away from a surface of the substrate, wherein ones of the pores have respective volumes that increase with a distance from the substrate until reaching an air gap layer above the pore-containing layer and beneath uppermost surfaces of the wiring lines. 
         [0006]    In some embodiments according to the inventive concept, a semiconductor device can include wiring lines on a substrate and an interlayer insulating structure between ones of the wiring lines. A cover layer can cover the wiring lines and the interlayer insulating structure, wherein the interlayer insulating structure includes a non-porous layer without pores, a pore-containing layer with pores, and an air gap sequentially provided on the substrate, wherein respective volumes of the pores in the pore-containing layer increase monotonically with increased distance from a surface of the substrate. 
         [0007]    In some embodiments according to the inventive concept, the cover layer can be a silicon oxycarbide based material. In some embodiments according to the inventive concept, the wiring lines can be tungsten or copper. In some embodiments according to the inventive concept, the device can further include a barrier layer between the substrate and at least one of the wiring lines and between the interlayer insulating structure and the at least one wiring line. 
         [0008]    In some embodiments according to the inventive concept, at least one wiring line can be tungsten, and the barrier layer can be a metal barrier layer. In some embodiments according to the inventive concept, the metal barrier layer can be at least one of tantalum, tantalum nitride, ruthenium, cobalt, manganese, titanium, titanium nitride, tungsten nitride, nickel, nickel boron, or any combination thereof. 
         [0009]    In some embodiments according to the inventive concept, the at least one wiring line can be copper, and the barrier layer can be a multi-layered structure including a metal barrier layer and a seed layer on the metal barrier layer. In some embodiments according to the inventive concept, the device can also include an etch stop layer between the substrate and the interlayer insulating structure. In some embodiments according to the inventive concept, the etch stop layer can be silicon carbon nitride. 
         [0010]    In some embodiments according to the inventive concept, a method of fabricating a semiconductor device can be provided by depositing an interlayer insulating layer on a substrate while monotonically increasing an amount of porogen gas applied to the interlayer insulating layer from about 0% to about 100% of a source material. An interconnection line can be formed to penetrate the interlayer insulating layer. A cover layer can be formed on the interconnection line and the interlayer insulating layer and porogen can be removed from the interlayer insulating layer to form an interlayer insulating structure including a non-porous layer without pores, a pore-containing layer with pores, and an air gap sequentially provided on the substrate. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings. The accompanying drawings represent non-limiting, example embodiments as described herein. 
           [0012]      FIG. 1  is a sectional view illustrating a semiconductor device according to some embodiments of the inventive concept. 
           [0013]      FIGS. 2 through 8  are sectional views illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept. 
           [0014]      FIG. 9  is a schematic block diagram illustrating an example of memory systems including a semiconductor device according to some embodiments of the inventive concept. 
           [0015]      FIG. 10  is a schematic block diagram illustrating an example of memory cards including a semiconductor device according to some embodiments of the inventive concept. 
           [0016]      FIG. 11  is a schematic block diagram illustrating an example of information processing systems including a semiconductor device according to some embodiments of the inventive concept. 
       
    
    
     DETAILED DESCRIPTION 
       [0017]    Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown. Example embodiments of the inventive concepts may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of some embodiments to those of ordinary skill in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like reference numerals in the drawings denote like elements. 
         [0018]    It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items. Other words used to describe the relationship between elements or layers should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” “on” versus “directly on”). 
         [0019]    It will be understood that, although the terms “first”, “second”, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of example embodiments. 
         [0020]    Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated  90  degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. 
         [0021]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising”, “includes” and/or “including,” if used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof. 
         [0022]    Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments of the inventive concepts belong. It will be further understood that terms, such as those defined in commonly-used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
         [0023]      FIG. 1  is a sectional view illustrating a semiconductor device according to example embodiments of the inventive concept. 
         [0024]    Referring to  FIG. 1 , a semiconductor device may include a substrate  110 , an etch stop layer  120 , an interlayer insulating structure  130   a,  a barrier layer  140 , a wiring pattern  150   a,  and a cover layer  160 . 
         [0025]    The substrate  110  may be a semiconductor wafer, such as a silicon (Si) wafer, a germanium (Ge) wafer, or a silicon-germanium (SiGe) wafer. Other wafers may also be used. Integrated circuits including transistors and/or memory cells may be provided between the substrate  110  and the interlayer insulating structure  130   a  or on the substrate  110 . 
         [0026]    The etch stop layer  120  may be interposed between the substrate  110  and the interlayer insulating structure  130   a.  The etch stop layer  120  may include a material having an etch selectivity with respect to the material comprising the interlayer insulating structure  130   a  that is sufficient to enable the formation of the structure shown in  FIG. 1  using an etch chemistry. For example, the etch stop layer  120  may include silicon carbon nitride (SiCN). Due to the presence of the etch stop layer  120 , it is possible to suppress an increase in etching uniformity of the substrate  110 , in a process of forming the wiring patterns  150   a.    
         [0027]    The interlayer insulating structure  130   a  may include a non-porous layer  130   np  without a pore, a pore-containing layer  130   pp  with pores  131   p,  and an air gap  130   ag . In example embodiments, the non-porous layer  130   np , the pore-containing layer  130   pp , and the air gap  130   ag  may be sequentially disposed on the substrate  110 . Further, the pores  131   p  may be formed to have volumes that increase with the distance from a surface of the substrate  110  on which the interlayer insulation structure  130   a  is formed. In some embodiments according to the inventive concept, the volumes of the pores  131   p  may increase monotonically as the distance from the substrate  110  increases. In some embodiments according to the inventive concept, the term “increasing monotonically” can refer to embodiments where the volumes of the pores  131   p  increase (without decreasing) with the distance from the surface of the substrate  110 . For example, “increasing monotonically” can describe an embodiment where the volumes of the pores  131   p  increase with the distance from the substrate  110  surface and do not decrease, as the distance from the substrate  110  surface increases. Furthermore, the term “increasing monotonically” can include embodiments where the volumes of the pores  131   p  increase through some portions of the structure  130   a  as the distance increases and remains the same through other portions of the structure  130   a  as the distance increases, but the volumes do not decrease as the distance increases. Here, the pores  131   p  and/or the air gap  130   ag  may be voids such that all liquid and/or solids are absent from inside the pores  131   p.  For example, the pores  131   p  and/or the air gap  130   ag  may be empty spaces. In some embodiments according to the inventive concept, the material that surrounds the pores  131   p  is absent from inside the volumes that define the pores. The non-porous layer  130   np  and the pore-containing layer  130   pp  may include a low-k material. For example, the non-porous layer  130   np  and the pore-containing layer  130   pp  may include silicon carbide (SiC). 
         [0028]    In some embodiments according to the inventive concept, the pores  131   p  can be formed at any higher density in the structure as the distance from the surface of the substrate  110  increases. For example, in some embodiments according to the inventive concept, as the distance from the surface of the substrate  110  increases, the volumes of the pores  131   p  can also increase so that less of the interlayer insulating structure  130   a  is available so that the pores  131   p  consume a greater volume of the structure  130   a  as the distance increases. 
         [0029]    The wiring pattern  150   a  may include tungsten (W) or copper (Cu). The wiring pattern  150   a  may be electrically connected to the transistors and/or the memory cells. The barrier layer  140  may be interposed between the substrate  110  and the wiring pattern  150   a  and between the interlayer insulating structure  130   a  and the wiring pattern  150   a.  The barrier layer  140  may prevent metallic elements in the wiring pattern  150   a  from being diffused into the substrate  110  and/or the interlayer insulating structure  130   a.  This wiring pattern  150   a  includes wiring lines that are spread apart from one another. The interlayer insulate structure  130   a  is located between ones of the wiring lines. 
         [0030]    In the case where the wiring pattern  150   a  contains tungsten, the barrier layer  140  may be a metal barrier layer. For example, the barrier layer  140  may include at least one selected from the group consisting of tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), cobalt (Co), manganese (Mn), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), nickel (Ni), nickel boron (NiB), and any combination thereof. 
         [0031]    In the case where the wiring pattern  150   a  contains copper, the barrier layer  140  may be a multi-layered structure including a metal barrier layer and a seed layer on the metal barrier layer. The seed layer may include copper. 
         [0032]    The cover layer  160  may be provided to cover the wiring pattern  150   a  and the interlayer insulating structure  130   a.  The cover layer  160  may include at least one of silicon oxycarbide (SiOC) based materials. The cover layer  160  may be formed to have a thickness ranging from about 10 Å to about 30 Å. During a process for forming the interlayer insulating structure  130   a,  polymeric pore generator (porogen) may be evaporated to form the nano-volume or small volume pores. In some embodiments, the cover layer  160  may be formed to have pores allowing the evaporated porogens to be exhausted to the atmosphere. 
         [0033]    An interconnection line structure may be additionally provided on the cover layer  160 . In example embodiments, the additional interconnection line structure may be configured to be similar to the interlayer insulating structure  130   a  and the wiring pattern  150   a.    
         [0034]    In some embodiments, the interlayer insulating structure  130   a  can include a predetermined thickness pore-free non-porous layer  130   np , a predetermined thickness pore-containing layer  130   pp , including pores  131   p  of monotonically-increasing volume with increasing distance from the substrate  110 , and a predetermined thickness air gap  130   ag  that are sequentially provided on the substrate  110 . Owing to this structure of the interlayer insulating structure  130   a,  it is possible to reduce the likelihood that the wiring pattern  150   a  may collapse during formation. Further, by using the interlayer insulating structure, it is possible to reduce a problem of RC delay. 
         [0035]      FIGS. 2 through 8  are sectional views illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept. 
         [0036]    Referring to  FIG. 2 , the etch stop layer  120  may be formed on the substrate  110 , and then, an interlayer insulating layer  130  may be formed on the etch stop layer  120 . The interlayer insulating layer  130  may include the non-porous layer  130   np , a porogen-containing layer  130   p,  and a porogen layer  130   ap  that are sequentially formed on the substrate  110 . 
         [0037]    The substrate  110  may be a semiconductor wafer, such as a silicon (Si) wafer, a germanium (Ge) wafer, or a silicon-germanium (SiGe) wafer. Integrated circuits including transistors and/or memory cells may be provided between the substrate  110  and the interlayer insulating structure  130   a  or on the substrate  110 . 
         [0038]    The etch stop layer  120  may be formed to include a material having an etch selectivity with respect to the interlayer insulating layer  130 . For example, the etch stop layer  120  may include silicon carbon nitride. The etch stop layer  120  may make it possible to suppress an increase in etching uniformity of the substrate  110 , in a subsequent process of forming the wiring patterns  150   a  (of  FIG. 1 ). 
         [0039]    The interlayer insulating  130  may be formed by providing a source material including a silicon source and a porogen gas. For example, the silicon source includes silane-based materials or methyl silane based materials. The interlayer insulating layer  130  may be formed by monotonically or linearly increasing an amount of porogen gas, for example, from 0% to 100% of the source material during the deposition of the interlayer insulating layer  130 . As a result, the interlayer insulating layer  130  may be formed to include the non-porous layer  130   np , the porogen-containing layer  130   p  including porogen portions  129   p,  and the porogen layer  130   ap  made of porogen. The porogen portions  129   p  in the porogen-containing layer  130   p  may be formed to have volumes that monotonically or linearly increase with increasing distance from the substrate  110 . The non-porous layer  130   np  and the porogen-containing layer  130   p  may be formed of a low-k material. For example, the non-porous layer  130   np  and the porogen-containing layer  130   p  may be formed of silicon carbide. The porogen gas may include at least one of hydrocarbon (CxHy) based materials, where x+y=1. In some embodiments, the interlayer insulating layer  130  may be formed using a chemical vapor deposition method. 
         [0040]    Referring to  FIG. 3 , an opening  135  may be formed through the interlayer insulating layer  130  to expose a portion of the substrate  110 . The formation of the opening  135  may include forming a hardmask pattern on the interlayer insulating layer  130 , and then, sequentially etching the interlayer insulating layer  130  and the etch stop layer  120  using the hardmask pattern as an etch mask. Thereafter, the hardmask pattern may be removed. 
         [0041]    Referring to  FIG. 4 , the barrier layer  140  may be formed to cover conformally the resulting structure provided with the opening  135 . The barrier layer  140  may be a metal barrier layer. The metal barrier layer may include at least one selected from the group consisting of tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), cobalt (Co), manganese (Mn), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), nickel (Ni), nickel boron (NiB), and any combination thereof. In addition, the barrier layer  140  may be a multi-layered structure including a metal barrier layer and a seed layer on the metal barrier layer. The seed layer may include copper. 
         [0042]    Referring to  FIG. 5 , a wiring layer  150  may be formed on the resulting structure provided with the barrier layer  140 . The wiring layer  150  may include tungsten or copper. The barrier layer  140  may reduce diffusion of metallic elements in the wiring layer  150  into the substrate  110  and/or the interlayer insulating layer  130 . 
         [0043]    In embodiments where the wiring layer  150  contains tungsten, the barrier layer  140  may be a metal barrier layer. The metal barrier layer may include at least one selected from the group consisting of tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), cobalt (Co), manganese (Mn), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), nickel (Ni), nickel boron (NiB), and any combination thereof. In the case where the wiring layer  150  contains tungsten, the wiring layer  150  may be formed by a physical vapor deposition (PVD) or chemical vapor deposition method. 
         [0044]    In embodiments where the wiring layer  150  contains copper, the barrier layer  140  may be a multi-layered structure including a metal barrier layer and a seed layer on the metal barrier layer. In embodiments where the wiring layer  150  contains copper, the wiring layer  150  may be formed by an electroplating method. 
         [0045]    Referring to  FIG. 6 , the wiring layer  150  may be planarized to expose the interlayer insulating layer  130 . Accordingly, the wiring pattern  150   a  having an exposed top surface may be formed. The wiring pattern  150   a  may be electrically connected to the transistors and/or the memory cells. 
         [0046]    Referring to  FIG. 7 , the cover layer  160  may be formed to cover the wiring pattern  150   a  and the interlayer insulating layer  130 . The cover layer  160  may be formed of at least one of silicon oxycarbide based materials. The cover layer  160  may be formed to have a thickness ranging from about  10 A to about  30 A. During a subsequent process for forming the interlayer insulating structure  130   a  (of  FIG. 1 ), porogens may be evaporated from the porogen portions  129   p  and the porogen layer  130   ap . In some embodiments, the cover layer  160  may be formed to have pores allowing the evaporated porogens to be exhausted to the exterior atmosphere. 
         [0047]    Referring to  FIG. 8 , the interlayer insulating layer  130  may be cured, thereby forming the interlayer insulating structure  130   a  including the non-porous layer  130   np , the pore-containing layer  130   pp  with the pores  131   p,  and the air gap  130   ag.    
         [0048]    The curing of the interlayer insulating layer  130  may include a high temperature UV process, which may be performed to irradiate ultraviolet (UV) rays to the interlayer insulating layer  130  at a temperature of  400 ° C. or higher. By performing the high temperature UV process, the porogen layer  130   ap  and the porogen portions  129   p  in the porogen-containing layer  130   p  may be evaporated, and the evaporated porogen may be exhausted to the exterior atmosphere through the pores of the cover layer  160 . 
         [0049]    As a result, the interlayer insulating structure  130   a  may be formed to have a pore density (in terms of volumes of respective pores  131   p ) increasing from bottom to top along a sidewall of the wiring pattern  150   a.    
         [0050]    An interconnection line structure may be additionally formed on the cover layer  160 . In example embodiments, the additional interconnection line structure may be configured to be similar to the interlayer insulating structure  130   a  and the wiring pattern  150   a.    
         [0051]    According to the above method, the semiconductor device may be fabricated to include the interlayer insulating structure  130   a  including the pore-free non-porous layer  130   np , the pore-containing layer  130   pp  (having pores  131   p  with volumes that monotonically or linearly increase with increasing distance from the substrate  110 ), and the air gap  130   ag . Owing to this structure of the interlayer insulating structure  130   a,  it is possible to prevent the wiring pattern  150   a  from falling. Further, by using the interlayer insulating structure  130   a,  it is possible to reduce a problem of RC delay. 
         [0052]      FIG. 9  is a block diagram illustrating an example of a memory system including the semiconductor devices according to some embodiments of the inventive concept. 
         [0053]    Referring to  FIG. 9 , a memory system  1100  can be applied to a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a memory card and/or any device that can transmit and/or receive data in a wireless communication environment. 
         [0054]    The memory system  1100  includes a controller  1110 , an input/output device  1120 , a memory  1130 , an interface  1140  and a bus  1150 . The memory  1130  and the interface  1140  communicate with each other through the bus  1150 . 
         [0055]    The controller  1110  includes at least one microprocessor, at least one digital signal processor, at least one micro controller or other processor devices similar to the microprocessor, the digital signal processor and the micro controller. The memory  1130  may be used to store instructions executed by the controller  1110 . The input/output device  1120  can receive data or signals from external to the system  1100  or transmit data or signals from the system  1100 . For example, the input/output device  1120  may include a keyboard, a keypad and/or a display. 
         [0056]    The memory  1130  includes at least one of the semiconductor devices according to some embodiments of the inventive concepts. The memory  1130  may further include a different kind of memory, a randomly accessible volatile memory device and various kinds of memories. 
         [0057]    The interface  1140  transmits data to a communication network or receives data from a communication network. 
         [0058]      FIG. 10  is a schematic block diagram illustrating an example of a memory card including at least one of the semiconductor devices according to some embodiments of the inventive concept. 
         [0059]    Referring to  FIG. 10 , the memory card  1200  for supporting a storage capability of a large capacity may be configured to include a semiconductor memory device  1210 , which may be the semiconductor device according to some embodiments of the inventive concept. The memory card  1200  includes a memory controller  1220  controlling data exchange between a host and the semiconductor memory device  1210 . 
         [0060]    A static random access memory (SRAM)  1221  is used as an operational memory of a central processing unit (CPU)  1222 . A host interface  1223  includes data exchange protocols of a host to be connected to the memory card  1200 . An error correction coding block  1224  detects and corrects errors included in data readout from the semiconductor memory device  1210  which may be a multi-bit memory device. A memory interface  1225  interfaces with the semiconductor memory device  1210  including the semiconductor device according to some embodiments of the inventive concept. The CPU  1222  performs control operations for exchanging data of the memory controller  1220 . It will be understood that other components can also be provided in the memory card  1200 , such as a ROM for storing code data for interfacing with the host. 
         [0061]    According to the afore-described example embodiments of the inventive concept, a semiconductor device, a memory card, or a memory system can be provided to have high integration. The example embodiments are applicable to a memory system such as solid state drive (SSD), thereby providing a memory system with high integration. 
         [0062]      FIG. 11  is a schematic block diagram illustrating an example of an information processing system  1300  including at least one of the semiconductor devices according to some embodiments of the inventive concept. 
         [0063]    Referring to  FIG. 11 , the information processing system  1300  may be realized using a memory system  1310  including at least one of the semiconductor devices according to some embodiments of the inventive concepts. For instance, the information processing system  1300  may be or be used to realize a mobile device and/or a desktop computer. In some embodiments, the information processing system  1300  may further include a modem  1320 , a central processing unit (CPU)  1330 , a random access memory (RAM)  1340 , and a user interface  1350 , which are electrically connected to a system bus  1360 , in addition to the memory system  1310 . The memory system  1310  may include a memory device  1311  and a memory controller  1312 . In some embodiments, the memory system  1310  may be configured substantially identical to the memory system described with reference to  FIG. 9 . Data processed by the CPU  1330  and/or input from the outside (e.g., external to the system  1300 ) may be stored in the memory system  1310 . In some embodiments, the memory system  1310  may be used as a portion of a solid state drive (SSD), and in this case, the information processing system  1300  may stably and reliably store a large amount of data in the memory system  1310 . It will be understood that other components may also be included in the system  1300 , such as an application chipset, a camera image sensor, a camera image signal processor (ISP), an input/output device, or the like. 
         [0064]    Furthermore, a semiconductor device according to the inventive concept or a memory system comprising the same may be packaged in various kinds of ways. For instance, the semiconductor device or the memory system may be employed in a Package on Package (PoP), Ball Grid Array (BGA), Chip Scale Package (CSP), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB) package, Ceramic Dual In-line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flat Pack (TQFP), Small Outline Integrated Circuit (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline Package (TSOP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), or Wafer-level Processed Stack Package (WSP). Also, any such package in which a semiconductor memory device according to the inventive concept is incorporated may additionally incorporate at least one semiconductor device (e.g., a controller and/or a logic device) that controls the semiconductor device. 
         [0065]    While some embodiments of the inventive concepts have been particularly shown and described, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit and scope of the attached claims.