Abstract:
A system, method, and apparatus for controlling tri-state drivers are presented herein. During scan testing, a decoder controls the tri-state drivers and prevents more than one tri-state driver from driving a shared resource, regardless of the test patterns shifted into the scan chain. During functional mode, the tri-state drivers are driven by functional enables.

Description:
RELATED APPLICATIONS  
       [0001]     This continuation application claims priority to Non-Provisional application for U.S. patent Ser. No. 10/608,336, “Control of Tristate Buses During Scan Test” by Kodihalli, et al, filed Jun. 27, 2003, issued as U.S. Pat. No. ______ which claims the benefit of Provisional Application for U.S. Patent, Ser. No; 60/443,769, “Control of Tristate Buses During Scan-Test—A Strategy” by Kodihalli, et. al., filed Jan. 30, 2003. Each of the foregoing applications are incorporated herein by reference, in their entirety for all purposes. 
     
    
     FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT  
       [0002]     [Not Applicable] 
       MICROFICHE/COPYRIGHT REFERENCE  
       [0003]     [Not Applicable] 
       BACKGROUND OF THE INVENTION  
       [0004]     Due to the increasing numbers of transistors that are incorporated on integrated circuits, exhaustive testing of integrated circuits is practically impossible. Rather, digital circuits are usually tested by applying a variety of test signals to the system and monitoring the output signals produced in response.  
         [0005]     Adding to this technique, digital circuits have also been designed with memory stages which can be operated in one of two modes—a first mode where the memory stages operate primarily as designed, and a second mode where the memory stages are connected in series to form one or more extended shift registers, otherwise known as scan chains. During the second mode, bit patterns, known as test vectors, are shifted or scanned into the scan chains. The logic system is returned to its first mode configuration and permitted to operate for one clock. The logic system is then returned to the second mode and the results extracted from the logic system (again by scanning) are analyzed to determine the operability of the stages and interconnections of the logic system. This testing technique is usually referred to as “scan testing”.  
         [0006]     Fault coverage measures the degree to which test vectors are capable of uncovering potential defects and faults. It is a goal of scan testing to achieve a high degree of fault coverage in a reasonable amount of time. Accordingly, there are a number of tools which generate a combination of test patterns which achieve a requisite degree of fault coverage in short amount of time.  
         [0007]     Many of the digital circuits tested include tristate buses, which can be used by two or more entities. Competing requests for use by the two or more entities result in a resource contention. Use of test patterns which cause resource contention on tristate buses result in erroneous error reporting. Accordingly, automatic test pattern generators remove test patterns which cause resource contention on tristate buses and replace the test patterns with other test patterns which achieve the same fault coverage and avoid the resource contention. Nevertheless, some fault coverage is still lost.  
         [0008]     Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art through comparison of such systems with embodiments presented in the remainder of the present application with reference to the drawings.  
       BRIEF SUMMARY OF THE INVENTION  
       [0009]     Described herein are system(s), method(s), and apparatus for controlling tristate buses during scan testing.  
         [0010]     In one embodiment, there is presented a method for testing a circuit. The method comprises inputting a test pattern into the circuit; disabling all but one of a plurality of clients accessing a shared resource, while inputting the test pattern; and capturing a response.  
         [0011]     In another embodiment, there is presented a circuit for performing a function. The circuit comprises a shared resource, a plurality of clients, and a testing circuit. The plurality of clients are connected to the shared resource. The testing circuit disables all but one of the clients while inputting a test pattern into the circuit.  
         [0012]     In another embodiment, there is presented a circuit for accessing a shared resource. The circuit comprises a driver and a logic circuit. The driver drives the share resource. The logic circuit disables the driver during a testing mode.  
         [0013]     In another embodiment, there is presented a circuit for accessing a shared resource. The circuit comprises a driver and a logic circuit. The driver drives the share resource. The logic circuit is operably connected to the driver, and operable to disable the driver during a testing mode.  
         [0014]     These and other advantages and novel features of the present invention, as well as details of illustrated embodiments thereof, will be more fully understood from the following description and drawings.  
     
    
     BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS  
       [0015]      FIG. 1  is a block diagram describing a system for testing a circuit in accordance with an embodiment of the present invention; 
         FIG. 2  is a flow diagram for testing a circuit in accordance with an embodiment of the present invention;          
         [0017]      FIG. 3  is a block diagram of a circuit for testing a device under test in accordance with an embodiment of the present invention; and  
         [0018]      FIG. 4  is a logic diagram of a decoder for disabling tristate driver in accordance with an embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0019]     Referring now to  FIG. 1 , there is illustrated a circuit  100  in accordance with an embodiment of the present invention. The circuit  100  comprises a functional portion  105 , also known as a sea of logic, and additional testing hardware. The circuit  100  can be implemented in a number of ways, such as an integrated circuit on a chip or a printed circuit on a printed circuit board.  
         [0020]     The circuit  100  can operate in either a functional mode or a scan mode. The functional mode is the primary function of operation for the circuit  100 . The functional portion  105  is the portion of the circuit that performs the primary functions. For example, the circuit  100  can be incorporated into an end product. In general, the functional portion  105  is the portion of the circuit  100  that performs the chip functions after incorporation into the end product. The circuit  100  also includes additional elements that are used for testing functions.  
         [0021]     The scan mode is a testing mode to verify proper operation of the functional portion  105 . During the scan mode, state devices, such as flip-flops, are connected in series to form one or more extended shift registers, otherwise known as scan chains  110 . During the second mode, bit patterns, known as test vectors, are shifted or scanned into the scan chains  110 . After scanning the test vectors into the scan chains  110 , the functional portion  105  of the circuit  100  operates as though in the functional mode for one cycle. After the cycle, the contents of the scan chain  110  are extracted. The foregoing can be repeated any number of times.  
         [0022]     The circuit  100  also includes shared resources  115 , such as a bus, that can be used by two or more entities. Each of the entities accesses the bus through a tri-state driver  120 . The tri-state drivers  120  can operate in one of three states—a high impedance state, a high state, and a low state. When a tri-state driver  120  is in the high impedance state, the tri-state driver  120  does not attempt to set the shared resource  115  into any state. When the tri-state drivers  120  are in either the high state or the low state, the tri-state drivers  120  attempt to drive the shared resource into the high or low state.  
         [0023]     A resource contention occurs when two or more tri-state drivers  120  attempt to drive the shared resource  115 . Serious damage to the circuit  100  can occur when two or more tri-state drivers  120  attempt to drive the shared resource  115  to two different states. Another problem occurs when none of the tri-state drivers  120  attempt to drive the share resource  115 . The foregoing can cause the shared resource  120  to enter a floating state. The foregoing problems are alleviated during the functional mode by an arbiter that prevents resource contentions.  
         [0024]     During testing mode, the test patterns that are scanned into the scan chain  110  can potentially cause resource contentions with the shared resource  115 . To prevent resource contentions, a decoder  125  and logic circuits  130  are connected to each of the tri-state drivers  120  that can potentially drive a shared resource  115 .  
         [0025]     The scan mode is indicated by the assertion of the scan_mode signal. The decoder  125  receives the scan_mode signal, and upon receiving the scan mode signal, the decoder disables (e.g., sets to a high impedance state) all but one of the tri-state drivers  120 . As noted above, during the scan mode, test patterns are serially shifted through the scan chain  110 . The shifting is indicated by assertion of the scan_enable signal. While the bits are shifted through the scan chain  110 , the decoder  125  disables all of the tri-state drivers  120 , except for one default driver  120 α. The foregoing prevents resource contention.  
         [0026]     After the serial bit shift, the functional portion  105  operates as though in the functional mode for one clock cycle. During the one clock cycle, the decoder  125  disables each of the tri-state drivers  120  except one. The one tri-state driver  120  that is not disabled is controllable by controllable input signals. For example, in one embodiment, the selected state driver  120  can be a function of the test pattern. Additionally, the selected state driver  120  can be selected by receiving the controllable input signals from the scan chain  110 .  
         [0027]     During the functional mode, the decoder  125  does not disable any of the tri-state drivers  120 . The tri-state drivers  120  are controlled by functional enable signals  130  from the functional portion  105  of the circuit  100 . The tri-state drivers  120  are controlled by logic circuits  135  that are connected thereto. The logic circuits  135  receive a signal from the decoder  125  and functional enable signals  130  from the functional portions  105  of the circuit  100 . During the functional mode, the decoder  125  transmits signals to the logic circuits  135  that cause the output of the logic circuits  135  to be determined by the functional enables  130 .  
         [0028]     Referring now to  FIG. 2 , there is illustrated a flow diagram for testing a circuit in accordance with an embodiment of the present invention. At  205 , a determination is made whether the circuit  100  is operating in the scan mode or functional mode. As noted above, the mode of operation may be indicated by assertion of the scan_mode signal. If the circuit  100  is not operating in scan mode, the circuit is operating in the functional mode. Accordingly, at  240 , the tri-state drivers  120  are controlled by functional enables  130 . The decoder  125  can allow the tri-state drivers  120  to be controlled by the functional enables  130  by either not transmitting -any signal, or alternatively, transmitting a signal to the logic circuits  135 , such that the output of the logic circuit  135  is determined by the functional enables  130 .  
         [0029]     If at  205 , the circuit  100  is in the scan mode, all of the tri-state drivers  120  except for a default tri-state driver  120 α for a shared resource  115  are disabled ( 210 ) during scan shifting ( 215 ) . The decode  125  disables the tri-state drivers  120  transmitting of a signal to the logic circuits  130  controlling each of the tri-state drivers  120  except the default tri-state driver  120 α, causing the tri-state drivers  120  to be disabled. As noted above, the scan shifting is indicated by assertion of the scan_enable signal.  
         [0030]     At  220 , after the scan shift, a tri-state driver  120  is selected based on the controllable inputs. The selected tri-state driver  120  can be a function of the test pattern shifted into the scan chain  110 . As well, the controllable inputs can be received from the scan chain  110 , itself.  
         [0031]     At  230 , each of the tri-state drivers  120  except for the selected tri-state driver  120  are disabled while data is captured ( 235 ) . After the data is captured during  235 ,  205 - 240  are repeated.  
         [0032]     Referring now to  FIG. 3 , there is illustrated a block diagram describing a system for testing a circuit in accordance with an embodiment of the present invention. The circuit  300 . The circuit  300  also includes a bus  315  that is shared by two or more entities. Each of the entities accesses the bus through a tri-state driver  320 . A resource contention may occur when two or more tri-state drivers  320  attempt to drive the bus  315 . Serious damage to the circuit  300  can occur when two or more tri-state drivers  320  attempt to drive the bus  315  to two different states. Another problem may occur when none of the tri-state drivers  120  attempt to drive the bus  315 . The foregoing can cause the bus  315  to enter a floating state. An arbiter that prevents resource contentions may alleviate the foregoing problems during the functional mode.  
         [0033]     During testing mode, the test patterns that are scanned into the scan chain  310  can potentially cause resource contentions with the bus  315 . To prevent resource contentions, a decoder  325  and AND gates  335  are connected to each of the tri-state drivers  320  that can potentially drive the bus  315 .  
         [0034]     The scan mode is indicated by the assertion of the scan_mode signal. The decoder  325  receives the scan_mode signal, and upon receiving the scan mode signal, the decoder disables (e.g., sets to a high impedance state) all but one of the tri-state drivers  320 . As noted above, during the scan mode, test patterns are serially shifted through the scan chain  310 . The shifting is indicated by assertion of the scan_enable signal. While the bits are shifted through the scan chain  310 , the decoder  325  disables all of the tri-state drivers  320 , except for one default driver  320   d . The foregoing prevents resource contention.  
         [0035]     After the serial bit shift, the circuit  300  operates as though in the functional mode for one clock cycle. During the one clock cycle, the decoder  325  disables each of the tri-state drivers  320  except one. The one tri-state driver  320  that is not disabled is controllable by controllable input signals from two particular flip-flops  322  in the scan chain  310 .  
         [0036]     The tri-state drivers  320  are controlled by functional enable signals  335 . The tri-state drivers  320  are connected to AND gates  335 . The AND gates  335  receive a signal from the decoder  325  and functional enable signals  330 . The decoder  325  disables a particular tri-state driver  325  by transmitting a logical “0” to the AND gate  335  connected to the tri-state driver  320 .  
         [0037]     During the functional mode, the decoder  325  transmits a logical “1” to each of the AND gates  335  connected to the tri-state drivers  320 . The logical “1&#39;s” transmitted by the decoder  325  cause the output of the AND gates  335  to be determined by the functional enables  330 .  
         [0038]     Additionally, in one embodiment, the decoder  325  can also include an IDDQ_enable signal that causes all of the drivers except the default driver  320   d  to be disabled.  
         [0039]     The decoder  325  can be implemented in a number of different ways. For example, the decoder  325  can be implemented by programmable hardware that executes instructions from a memory. Storage of the instructions in the memory physically, chemically, and/or electromagnetically alters the memory.  
         [0040]     In an exemplary case, the plurality of instructions can include the follow instructions:  
                                                                                       If (iddq_enable) OUT0 = 1;       else If(scan_test_mode) {                If(scan_enable)   {   OUT0 = 1; (DRIVER0 active)                   OUT1 = 0; (DRIVER1 inactive)                   OUT2 = 0; (DRIVER2 inactive)                   OUT3 = 0; (DRIVER3 inactive)                }                else Active output is selected by S1, S2;                else OUT0, OUT1, OUT2, OUT3 = ‘1’;   (Functional enables               will decide the               active driver)                      
 
         [0041]     Alternatively, the decoder  325  can be implemented as logic. In an exemplary case, the logic design of the decoder  325  can adhere to the following truth table describing the input/output behavior:  
                                                           Scan_Mode   Scan_enable   S1   S2   O0   O1   O2   O3                   0   X   X   X   1   1   1   1       1   0   0   0   1   0   0   0       1   0   0   1   0   1   0   0       1   0   1   0   0   0   1   0       1   0   1   1   0   0   0   1       1   1   X   X   1   0   0   0                  
 
         [0042]     Referring now to  FIG. 4 , there is illustrated an exemplary logic design for a decoder  325  in accordance with an embodiment of the present invention. The decoder  325  receives inputs S 1 , S 2 , scan_enable, and scan_mode. Inputs S 1  and S 2  are received by a 2:4 demultiplexer  405 . The demultiplexer  405  has four outputs  410  that are controlled by the inputs S 1  and S 2 . If S 1 , S 2 =0, output  410 ( 0 ) is set. If S 1 =0, S 2 =1, output  410  ( 1 ) is set. If S 1 =1, S 2 =0, output  410 ( 2 ) is set and if S 1 =1, and S 2 =1, output  410 ( 3 ) is set.  
         [0043]     The outputs  410 , except  410 ( 0 ) are each received by a age of AND gates  415 . The AND gates  415  receive the inverse scan_enable signal. When the scan_enable signal is set, the output of the AND gates  415  is 0. The output of the AND gates  415  are received by OR gates  420 . The output of the OR gates  420 ( 0 ),  420 ( 1 ),  420 ( 2 ), and  420 ( 3 ), are O 0 , O 1 , O 2 , and O 3 . The OR gates  420  also receive the inverse of scan_mode signal.  
         [0044]     Accordingly, when the scan_mode signal is not set, each of the outputs O 0 , O 1 , O 2 , and O 3  are “1”. When the scan_enable signal is set, and the scan_enable signal is set, the outputs O 0 , O 1 , O 2 , and O 3  are 1,0,0, and 0 respectively, where O 0  is associated with the default tri-state driver. When the scan_mode signal is set, and the scan_enable signal is not set, the outputs O 0 , O 1 , O 2 , and O 3  are determined by the outputs  410  of the multiplexer. As noted above, the outputs  410  of the multiplexer are determined by S 1  and S 2 .  
         [0045]     While the invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt particular situations or materials to the teachings of the intention without departing from its scope. Therefore, the invention is noted limited to the particular embodiment(s) disclosed, but that the invention will include all embodiments falling within the scope of the claims.