Abstract:
According to an aspect of the present invention, there is provided an output circuit including a first output unit supplying a first voltage, a second output unit supplying a second voltage, a switching unit selectively outputting, to an output end, the first voltage from the first output unit and the second voltage from the second output unit, a detection unit detecting a voltage of the output end, and a control unit controlling one of the first voltage and the second voltage on the basis of the voltage detected by the detection unit.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2006-346502, filed Dec. 22, 2006, the entire contents of which are incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an output circuit and liquid crystal display device. 
     2. Description of the Related Art 
     In a liquid crystal driving device, it is necessary to ensure the convergence of a constant-voltage output with respect to a voltage fluctuation caused by an external factor acting on a liquid crystal panel. Conventionally, therefore, the voltage is rapidly converged to a constant voltage by decreasing the resistance by increasing the size of a switch of a binary output circuit for outputting the constant voltage. In this case, however, the size of the liquid crystal driving device increases because the switch size of the binary output circuit increases. 
     Note that a flat panel display device in which a plurality of pixels are arranged in a matrix and a method of driving the display device are disclosed in Japanese Patent No. 3677100. 
     BRIEF SUMMARY OF THE INVENTION 
     According to an aspect of the present invention, there is provided an output circuit comprising: a first output unit supplying a first voltage; a second output unit supplying a second voltage; a switching unit selectively outputting, to an output end, the first voltage from the first output unit and the second voltage from the second output unit; a detection unit detecting a voltage of the output end; and a control unit controlling one of the first voltage and the second voltage on the basis of the voltage detected by the detection unit. 
     According to another aspect of the present invention, there is provided a liquid crystal display device comprising: a liquid crystal panel having a display element to form a pixel at each of intersections of a plurality of scanning lines running along a horizontal scanning direction, and a plurality of signal lines running along a vertical scanning direction; a gate driver driving each of said plurality of scanning lines; and a source driver driving each of said plurality of signal lines by an image signal voltage, the source driver comprising a common voltage generator applying a common voltage to a common electrode of the display element, and the common voltage generator comprising a first output unit supplying a first voltage to the common electrode of the display element; a second output unit supplying a second voltage to the common electrode of the display element, a switching unit selectively outputting, to the common electrode of the display element, the first voltage from the first output unit and the second voltage from the second output unit; a detection unit detecting the common voltage of the display element; and a control unit controlling one of the first voltage and the second voltage on the basis of the common voltage detected by the detection unit. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING 
         FIG. 1  is a block diagram showing the arrangement of a binary output circuit according to the first embodiment of the present invention; 
         FIG. 2  is a block diagram showing the arrangement of a liquid crystal display device to which a binary output circuit according to the second embodiment of the present invention is applied; 
         FIG. 3  is a view showing the arrangement of a common voltage generator according to the second embodiment of the present invention; 
         FIG. 4  is a view showing a practical arrangement of the common voltage generator according to the second embodiment of the present invention; 
         FIG. 5  is a view showing the arrangement of a common voltage generator according to a conventional example as a comparative example of the second embodiment of the present invention; 
         FIG. 6  is a block diagram showing the arrangement of a binary output circuit according to the third embodiment of the present invention; 
         FIG. 7  is a block diagram showing the arrangement of a binary output circuit according to the fourth embodiment of the present invention; 
         FIG. 8  shows a verification result of the convergence property of the constant voltage output verified by using the binary output circuit shown in  FIG. 4 ; 
         FIG. 9  shows the convergence property of the constant voltage output of the differential amplifier  120 ′ in the binary output circuit shown in  FIG. 4 ; and 
         FIG. 10  is a diagram in which the convergence properties of the constant voltage output shown in  FIGS. 8 and 9  are compared with each other. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Embodiments will be explained below with reference to the accompanying drawing. 
       FIG. 1  is a block diagram showing the arrangement of a binary output circuit according to the first embodiment of the present invention. Referring to  FIG. 1 , switches SW 1  and SW 2  are respectively connected to output circuits  11  and  12 . The output circuits  11  and  12  respectively include detection circuits  21  and  22 . Switches SW 1  and SW 2  are connected to each other. A control circuit  100  is connected to switches SW 1  and SW 2  and detection circuits  21  and  22 . Switches SW 1  and SW 2  and detection circuits  21  and  22  are connected to an output terminal P, and connected to a circuit as a voltage supply object. 
     Voltage source circuits (not shown) supply V 1  and V 2  representing binary values to the output circuits  11  and  12 , respectively. When outputting V 1  from the output terminal P, the control circuit  100  closes switch SW 1  and opens switch S 2 , thereby enabling the detection circuit  21 . When outputting V 2  from the output terminal P, the control circuit  100  opens switch SW 1  and closes switch SW 2 , thereby enabling the detection circuit  22  and disabling the detection circuit  21 . 
     The detection circuits  21  and  22  detect the voltage of the output terminal P. If an external factor changes the voltage of the output terminal P to, e.g., (V 1 +ΔV) while V 1  is output from the output terminal P, the detection circuit  21  detects this voltage (V 1 +ΔV), and drives the output circuit  11  on the basis of a difference ΔV from V 1  so that the voltage of the output terminal P rapidly converges to V 1 . That is, the output circuit  11  is driven to output {V 1 −G(ΔV)} so that the voltage of the output terminal P rapidly converges to V 1 . Here, G(ΔV) is a function which has an inherent value for each output circuit. More specifically, for example, in a case where G(ΔV) is a linear function, when a voltage higher than V 1  (ΔV&gt;0) is detected at the output terminal P, the output circuit outputs a voltage lower than V 1 . Thereby, the voltage of the output terminal P rapidly converges to V 1 . Conversely, for example, when a voltage lower than V 1  (ΔV&lt;0) is detected at the output terminal P, the output circuit outputs a voltage higher than V 1 . Thereby, the voltage of the output terminal P rapidly converges to V 1 . 
     Similarly, if the voltage of the output terminal P changes from V 2  while V 2  is output to the output terminal P, the detection circuit  22  detects a voltage (V 2 +ΔV), and drives the output circuit  12  on the basis of a difference ΔV from V 2  so that the voltage of the output terminal P rapidly converges to V 2 . 
     The above control can also be performed to switch, e.g., the state in which the V 1  is output from the output terminal P to the state in which V 2  is output. In this case, the voltage of the output terminal P is kept at V 1  when the output from the output terminal P is switched from V 1  to V 2 . Therefore, the detection circuit  22  detects voltage V 1 , and drives the output circuit  12  on the basis of a difference V 1 −V 2  from V 2  so that the voltage of the output terminal P rapidly converges to V 2 . That is, the output circuit  12  is driven to output {V 1 −G(V 1 −V 2 )} so that the voltage of the output terminal P rapidly converges to V 2 . Here, G(V 1 −V 2 ) is a function which has an inherent value for each output circuit. More specifically, for example, in a case where G(V 1 −N 2 ) is a linear function, when a voltage higher than V 2  (V 1 −V 2 &gt;0) is detected at the output terminal P, the output circuit outputs a voltage lower than V 2 . Thereby, the voltage of the output terminal P rapidly converges to V 2 . Conversely, for example, when a voltage lower than V 2  (V 1 −V 2 &lt;0) is detected at the output terminal P, the output circuit outputs a voltage higher than V 2 . Thereby, the voltage of the output terminal P rapidly converges to V 1 . Note that analog switches or inverters may also be used as switches SW 1  and SW 2 . It is also possible to use a combination of analog switches, a combination of resistors, or a combination of analog switches and resistors as the detection circuits  22  and  21 . 
     By contrast, the conventional binary output circuits outputs V 1  (or V 2 ) even if the voltage of the output terminal P changes from V 1  (or V 2 ) while V 1  (or V 2 ) is output to the output terminal P, unlike the case shown in  FIG. 1 . This makes it impossible to control the voltage of the output terminal P to rapidly converge to V 1  (or V 2 ). In the arrangement of this embodiment, however, the voltage of the output terminal P can be controlled to rapidly converge to V 1  (or V 2 ) as described above. 
       FIG. 2  is a block diagram showing the arrangement of a liquid crystal display device to which a binary output circuit according to the second embodiment of the present invention is applied. In the liquid crystal display device, the binary output circuit having a schematic arrangement described in the first embodiment is applied to a common voltage generator  1 . 
     Referring to  FIG. 2 , the liquid crystal display device comprises a liquid crystal panel  2 , source driver  204 , and gate driver  203 . In  FIG. 2 , the source driver  204  comprises the common voltage generator  1 , display RAM  3 , latch circuit  4 , Glay Scale generator (G/S generator)  5 , decoder circuit  6 , gradation output circuit  7 , and control circuit  100 . The common voltage generator  1  is a binary output circuit, and connected to the liquid crystal panel  2 . 
     In the liquid crystal panel  2 , scanning lines G 1  to Gm run along the horizontal scanning direction, and signal lines S 1  to Sn run along the vertical scanning direction. Thin-film transistors  201  are formed at the intersections of the signal lines S 1  to Sn and scanning lines G 1  to Gm. The transistors  201  have sources (S) connected to the signal lines S 1  to Sn, and gates (G) connected to the scanning lines G 1  to Gm. Capacitors  202  are connected to the drains (D) of the transistors  201  connected to the scanning lines G 1  to Gm. The capacitors  202  are connected together for each of the signal lines S 1  to Sn. Each capacitor  202  functions as a display element capacitance. A common electrode of the capacitor  202  is connected to the common voltage generator  1 . 
     The control circuit  100  controls the common voltage generator  1 , display RAM  3 , latch circuit  4 , Glay Scale generator  5 , and gate driver  203 . 
     The display RAM  3  has a memory area capable of storing image data corresponding to the display screen. The latch circuit  4  latches the image data read from the display RAM  3 . The latch circuit  4  outputs the latched image data to the decoder circuit  6 . The decoder circuit  6  selects a gradation voltage corresponding to the image data, and outputs the gradation voltage to the signal lines S 1  to Sn via the gradation output circuit  7 . The gate driver  203  switches the scanning lines G 1  to Gm under the control of the control circuit  100 . 
       FIG. 3  is a view showing the arrangement of the common voltage generator  1  shown in  FIG. 2 . The common voltage generator  1  shown in  FIG. 3  generates a binary output by operating analog switches ASW 1  and ASW 2  connected to voltage source circuits  110  and  120  for outputting constant voltages Va and Vb, respectively. 
     Referring to  FIG. 3 , switches ASW 1  and ASW 2  are respectively connected to the voltage source circuits (Va)  110  and (Vb)  120 . Switches ASW 1  and ASW 2  respectively have resistors Ron 1  and Ron 2 . The voltage source circuits (Va)  110  and (Vb)  120  respectively include detection circuits  111  and  121 . 
     Switches ASW 1  and ASW 2  are connected to each other. A series circuit of analog switches ASW 3  and ASW 4  is connected in parallel with switch ASW 1 . Switches ASW 3  and ASW 4  respectively have resistors Ron 3  and Ron 4 . A series circuit of analog switches ASW 5  and ASW 6  is connected in parallel with switch ASW 2 . Switches ASW 5  and ASW 6  respectively have resistors Ron 5  and Ron 6 . 
     The detection circuit  111  is connected to the connection node of switches ASW 3  and ASW 4 , and the detection circuit  121  is connected to the connection node of switches ASW 5  and ASW 6 . The control circuit  100  is connected to switches ASW 1  to ASW 6  and detection circuits  111  and  121 . The common voltage generator  1  is connected to voltage holding capacitors  112  and  122  and the liquid crystal panel  2  as a voltage supply object shown in  FIG. 2 . 
       FIG. 4  is a view showing a practical arrangement of the common voltage generator  1  shown in  FIG. 3 . The same reference numbers as in  FIG. 3  denote the same parts in  FIG. 4 . Referring to  FIG. 4 , a differential amplifier  110 ′ implements the voltage source circuit (Va)  110  and detection circuit  111  shown in  FIG. 3 , and a differential amplifier  120 ′ implements the voltage source circuit (Vb)  120  and detection circuit  121  shown in  FIG. 3 . 
     The operation of the common voltage generator  1  according to the second embodiment will be explained below with reference to  FIG. 3 . First, switches ASW 1 , ASW 3 , ASW 4 , and ASW 5  are ON, and switches ASW 2  and ASW 6  are OFF. As a consequence, voltage Va is applied to the capacitor  202 . In this state, the potentials of nodes N 1 ′, N 3 ′, and N 4 ′ are
 
VN1′=VN3′=VN4′=Va.
 
     If an external factor applies ΔV to a voltage Vp applied to the capacitor  202 , the potential of node N 4 ′ rises to (Va+ΔV). By contrast, the potential of node N 3 ′ is maintained at Va. That is,
 
 VN 3′= Va,VN 4′= Va+ΔV.  
 
     In this state, the ratio of resistor Ron 3  of switch ASW 3  to resistor Ron 4  of switch ASW 4  determines the potential of a node N 6 ′ positioned in the detection circuit  111 . That is,
 
 VN 6′= VN 1′+Δ V ×{Ron3/(Ron3+Ron4)}.
 
Accordingly, a voltage Vd to be supplied to the detection circuit  111  can be varied by changing the ratio of Ron 3  to Ron 4 . The voltage source circuit  110  is operated on the basis of a difference voltage Vd−Va between the detected voltages Vd and Va so that VN 4 ′ rapidly converges to Va. That is, the voltage source circuit  110  is operated to output {Va−G(Va−Vd)} so that the voltage of the VN 4 ′ rapidly converges to Va. Here, G(Va−Vd) is a function which has an inherent value for each voltage source circuit. More specifically, for example, in a case where G(Va−Vd) is a linear function, when a voltage higher than Va (Va−Vd&gt;0) is detected at the node VN 4 ′, the voltage source circuit outputs a voltage lower than Va. Thereby, the voltage of the node VN 4 ′ rapidly converges to Va. Conversely, for example, when a voltage lower than Va (Va−Vd&lt;0) is detected at the node VN 4 ′, the voltage source circuit outputs a voltage higher than V 1 . Thereby, the voltage of the node VN 4 ′ rapidly converges to Va. As described above, it is possible by actively operating the voltage source circuit  110  to converge the voltage of the capacitor  202  to constant voltage Va faster than a time constant obtained with resistor Ron 1  of switch ASW 1  and capacitance C 2  of the capacitor  202 .
 
     The above control can also be performed to switch, e.g., the state in which Va is supplied to the capacitor  202  to the state in which Vb is supplied. In this case, voltage Va is initially applied to the capacitor  202  because switches ASW 1 , ASW 3 , ASW 4 , and ASW 5  are ON and switches ASW 2  and ASW 6  are OFF. Then, switches ASW 2 , ASW 5 , ASW 6 , and ASW 3  are ON and switches ASW 1  and ASW 4  are OFF in order to switch the voltage from Va to Vb. 
     Assume that when the above operation is performed an external factor applies ΔV to voltage Va applied to the capacitor  202  and the potential of node N 4 ′ changes to (Va+ΔV). The ratio of resistor Ron 5  of switch ASW 5  to resistor Ron 6  of switch ASW 6  determines the potential of a node N 7 ′ positioned in the detection circuit  121 , and voltage Vd to be supplied to the detection circuit  121  is variable. The voltage source circuit  120  is operated on the basis of a difference voltage Vd−Vb between detected voltages Vd and Vb such that VN 4 ′ rapidly converges to Vb. That is, the voltage source circuit  120  is operated to output {Vb−G(Vd−Vb)} so that the voltage of the VN 4 ′ rapidly converges to Vb. Here, G(Vd−Vb) is a function which has an inherent value for each voltage source circuit. More specifically, for example, in a case where G(Vd−Vb) is a linear function, when a voltage higher than Vb (Vd−Vb&gt;0) is detected at the node VN 4 ′, the voltage source circuit outputs a voltage lower than Vb. Thereby, the voltage of the node VN 4 ′ rapidly converges to Vb. Conversely, for example, when a voltage lower than Vb (Vd−Vb&lt;0) is detected at the node VN 4 ′, the voltage source circuit outputs a voltage higher than Vb. Thereby, the voltage of the node VN 4 ′ rapidly converges to Vb. As described above, it is possible by actively operating the voltage source circuit  120  to converge the voltage on the common electrode side of the capacitor  202  to constant voltage Vb faster than a time constant obtained with resistor Ron 2  of switch ASW 2  and capacitance C 2  of the capacitor  202 . 
       FIG. 5  is a view showing the arrangement of a common voltage generator according to a conventional example as a comparative example of the second embodiment. This common voltage generator shown in  FIG. 5  generates a binary output by operating switches ASW 1  and ASW 2  connected to voltage source circuits  110  and  120  for outputting constant voltages Va and Vb, respectively. 
     The same reference numbers as in  FIG. 3  denote the same parts in  FIG. 5 . Referring to  FIG. 5 , switches ASW 1  and ASW 2  are respectively connected to the voltage source circuits (Va)  110  and (Vb)  120 . Switches ASW 1  and ASW 2  respectively have resistors Ron 1  and Ron 2 . The voltage source circuits (Va)  110  and (Vb)  120  respectively include detection circuits  111  and  121 . Switches ASW 1  and ASW 2  are connected to each other. 
     A control circuit  100  is connected to switches ASW 1  and ASW 2  and detection circuits  111  and  121 . This common voltage generator is connected to voltage holding capacitors  112  and  122  and a liquid crystal panel  2  as a voltage supply object. 
     The operation of the common voltage generator according to the conventional example will be explained below with reference to  FIG. 5 . Initially, switch ASW 1  is ON, and switch ASW 2  is OFF. As a consequence, voltage Va is applied to a capacitor  202 . In this state, the potentials of nodes N 1 , N 3 , and N 4  are
 
VN1=VN3=VN4=Va.
 
     If an external factor applies ΔV to a voltage Vp applied to the capacitor  202 , the potential of node N 4  rises to Va+ΔV. On the other hand, the potential of node N 3  is maintained at Va. That is,
 
 VN 3= Va,VN 4= Va+ΔV.  
 
     In this state, a time constant obtained by on-resistance component Ron 1  and capacitance C 2  of switch ASW 1  determines a period required for the potential of node N 4  to converge to original voltage Va. To ensure sufficient convergence, therefore, the on-resistance must be suppressed by increasing the switch size. 
     By contrast, in the common voltage generator according to the embodiment of the present invention described above, switches ASW 3  to ASW 6  are added to the circuit that generates the binary output voltage by switching the two voltage source circuits  110  and  120 . If a voltage fluctuation caused by an external factor changes the potential of the liquid crystal panel, therefore, the voltage source circuits are positively operated by actively varying the voltage amplitude input to the detection system. These makes it possible to downsize the common voltage generator without increasing the size of switches ASW 1  and ASW 2 , and increase the convergence of the constant-voltage output with respect to the fluctuation in binary output voltage caused by an external factor. 
       FIG. 6  is a block diagram showing the arrangement of a binary output circuit according to the third embodiment of the present invention. This binary output circuit is applied to the common voltage generator  1  shown in  FIG. 2 . The same reference numbers as in  FIG. 3  denote the same parts in  FIG. 6 . Referring to  FIG. 6 , resistors R 1  and R 2  are used instead of the switches ASW 3  and ASW 5 , thereby simply configuring the binary output circuit. Note that a resistor may be used instead of one of the switches ASW 3  and ASW 5 . 
       FIG. 7  is a block diagram showing the arrangement of a binary output circuit according to the fourth embodiment of the present invention. This binary output circuit is applied to the common voltage generator  1  shown in  FIG. 2 . The same reference numbers as in  FIG. 3  denote the same parts in  FIG. 7 . 
     Referring to  FIG. 7 , resistors R 1  and R 2  may be used instead of the switches ASW 3  and ASW 5 , a series circuit of a resistor R 3  and an analog switch ASW 4 ′ may be used instead of the switch ASW 4 , and a series circuit of a resistor R 4  and an analog switch ASW 6 ′ may be used instead of the switch ASW 6 . Note the above configuration may be used instead of one of the series circuit of switches ASW 3  and ASW 4  and the series circuit of switches ASW 5  and ASW 6 . Alternatively, the switches ASW 3  and ASW 5  may be used while the series circuit of the resistor R 3  and the analog switch ASW 4 ′ and the series circuit of the resistor R 4  and the analog switch ASW 6 ′ are used. 
       FIG. 8  shows a verification result of the convergence property of the constant voltage output verified by using the binary output circuit shown in  FIG. 4 . In  FIG. 8 , the horizontal axis indicates time (s), and the vertical axis indicates voltage of N 4 ′, which is the measurement point. The differential amplifiers  110 ′ and  120 ′ output constant voltage Va (2.0 V) and Vb (1.9 V), respectively.  FIG. 8  shows the convergence property of the constant voltage output of the differential amplifiers  110 ′ in the binary output circuit shown in  FIG. 4  with the resistance ratio of the switch ASW 3  to the switch ASW 4  changed. In  FIG. 8 , the ratio of the resistance of the resistor Ron 3  of the switch ASW 3  to that of the resistor Ron 4  of the switch ASW 4  is set to 2:10, 2:2, and 2:1.  FIG. 8  shows a case where voltage supplied to the capacitor is changed from Vb to Va. 
     In  FIG. 4 , while the differential amplifier  120 ′ outputs Vb, the control circuit  100  outputs an output voltage control signal, resulting in a state where the switches ASW 1 , ASW 3 , ASW 4 , and ASW 5  are ON, and the switches ASW 2  and ASW 6  are OFF. Thereby, Va is applied to the capacitor  202 . In this case, the convergence times up to (Va−10) mV are as shown in  FIG. 8 . When Ron 3 :Ron 4  is 2:10, the convergence time is 2.06 μs, 2:2, 1.86 μs, and 2:1, 1.79 μs. As stated above, as the resistance Ron 4  of the switch ASW 4  decreases with respect to the resistance Ron 3  of the switch ASW 3 , the convergence property improves. 
       FIG. 9  shows the convergence property of the constant voltage output of the differential amplifier  120 ′ in the binary output circuit shown in  FIG. 4 . In  FIG. 9 , the horizontal axis indicates time (s), and the vertical axis indicates voltage of N 4 ′, which is the measurement point. In  FIG. 9 , the ratio of the resistance of the resistor Ron 5  of the switch ASW 5  to that of the resistor Ron 6  of the switch ASW 6  (Ron 5 :Ron 6 ) is set to 2:10, 2:2, and 2:1.  FIG. 9  shows a case where voltage supplied to the capacitor  202  is changed from Va to Vb. 
     In  FIG. 9 , while the differential amplifier  110 ′ outputs Va, the control circuit  100  outputs an output voltage control signal, resulting in a state where the switches ASW 2 , ASW 5 , ASW 6 , and ASW 3  are ON, and the switches ASW 1  and ASW 4  are OFF. Thereby, Vb is applied to the capacitor  202 . In this case, the convergence times down to (Vb+10) mV are as shown in  FIG. 9 . When Ron 5 :Ron 6  is 2:10, the convergence time is 2.03 μs, 2:2, 1.84 μs, and 2:1, 1.78 μs. As stated above, as the resistance Ron 6  of the switch ASW 6  decreases with respect to the resistance Ron 5  of the switch ASW 5 , the convergence property improves. 
       FIG. 10  is a diagram in which the convergence properties of the constant voltage output shown in  FIGS. 8 and 9  are compared with each other. In  FIG. 10 , the horizontal axis indicates the resistance ratio Ron 3 /Ron 4  and the resistance ratio Ron 5 /Ron 6 , and the vertical axis indicates the convergence time (TR) up to (Va−10) mV and the convergence time (TF) down to (Vb+10) mV. As shown in  FIG. 10 , as the resistance ratios increase, both of the convergence times TR and TF decrease, thereby improving the convergence properties. 
     Note that the convergence property of the constant voltage output can be improved by changing not only the resistance ratio in the configuration shown in  FIG. 4  but the resistance ratio in another configuration. 
     As described above, the embodiment can provide an output circuit and liquid crystal display device capable of increasing the operating speed. 
     Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.