Abstract:
An invention is provided for a fuse state sensing circuit that senses the state of a fuse, which is coupled between a ground rail and a fuse state sensing node. The fuse state sensing node indicates a state of the fuse when rail voltage is provided to the fuse state sensing circuit. In addition, a capacitive element is included that is coupled to the fuse state sensing node. The capacitive element is capable of providing a first amount of current to the fuse state sensing node when an initial voltage is supplied to the rail voltage. The capacitive element is further configured to stop supplying the first amount of current upon reaching a threshold voltage of the capacitive element. The fuse state sensing circuit further includes a keeper latch circuit that is coupled to the fuse state sensing node in parallel with the capacitive element. The keeper latch circuit is capable of latching the state of the fuse state sensing node. In addition, the keeper latch circuit stops supplying current to the fuse state sensing node when a predetermined rail voltage is reached if the fuse is intact. Also, when a predetermined rail voltage is reached and the fuse is blown, the keeper latch circuit continues to supply current to the fuse state sensing node.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates generally to fuse enabled redundancy memory, and more particularly to zero power fuse sensing circuitry for redundancy applications in computer memories. 
     2. Description of the Related Art 
     Currently, semiconductor devices are becoming faster and highly integrated with the development of refining techniques, including semiconductor memory devices. However, if one memory cell of a memory device is defective, the entire memory device may no longer operate properly. Moreover, with the higher integration of semiconductor memory devices, the frequency of defects in memory cells is further increased. Such defective memory cells deteriorate the functionality of the memory device, and have become one of the main factors that lower the yield of semiconductor memory devices. 
     To address this issue, redundancy systems have been developed that improve yield by replacing defective cells with redundant cells. FIG. 1 is a block diagram showing prior art redundancy system  100  for replacing defective memory cells with redundant memory cells. The redundancy system  100  includes a master fuse  102  connected to a fuse box  104 , which controls access to redundant memory  106 . The redundancy system  100  drives spare redundancy memory cell blocks arranged in columns and rows, and selects a redundant memory cell in the redundancy memory  106  to replace the defective cell. Generally, when a defective cell is addressed, a fuse in the fuse box  104 , which is connected to the defective column and/or row, is cut such that a redundant column and/or row within the redundancy memory  106  is selected instead of the defective column and/or row. 
     To avoid unnecessary power consumption, the redundancy system  100  includes a master fuse  102 , which controls power flow to the fuse box  104 . When the redundant memory cells within redundant memory  106  are not in use, the master fuse  102  remains intact and prevents current flow to the fuse box  104 . In this manner, the fuses in the fuse box  104  do not bum power when none of the memory cells within the redundant memory  106  are in use. Conversely, when the redundant memory cells within redundant memory  106  are needed to replace defective memory cells, the master fuse  102  is cut to allow current flow to the fuse box  104 . However, when the master fuse  102  is cut, current is provided to all the fuses in the fuse box  104 . As a result, fuses not being used to redirect memory addresses begin to bum power. 
     FIG. 2 is a schematic diagram showing a prior art fuse state sensing circuit  200 . The prior art fuse state sensing circuit  200  includes an enable transistor  202  having a gate coupled to an enable signal  204 , a first terminal coupled to V DD , and a second terminal coupled to a fuse  206 . The second terminal is also coupled to a buffer  208 , which provides an output signal  210  for the fuse state sensing circuit  200 . 
     The enable signal  204  is utilized to indicate whether the fuses in the fuse box are being used, and as such, whether current should be provided to the fuse state sensing circuit  200 . In particular, when the master fuse is blown, the enable signal  204  provides a low signal to the enable transistor  202 , thus turning on the enable transistor  202  and allowing current to flow from the first terminal to the second terminal. This current flows to ground when the fuse  206  is intact, and as a result the buffer outputs a high on the output signal  210 . When the fuse  206  is blown indicating the corresponding redundant memory is in use, node  212  remains high and the buffer  208  outputs a low on the output signal  210 . 
     Unfortunately, the prior art fuse state sensing circuit  200  burns power when the fuse  106  is intact. Hence, the prior art fuse state sensing circuit  200  burns power when the corresponding redundant memory is not in use. As a result, when the master fuse is blown, all intact fuses in the corresponding fuse box burn power, which can create problems in low power applications. 
     In view of the foregoing, there is a need for low power fuse sensing circuitry. The fuse sensing circuitry should not burn power when the corresponding redundant memory blocks are not in use. Moreover, the fuse sensing circuitry should avoid using a master fuse, which burns additional power. 
     SUMMARY OF THE INVENTION 
     Broadly speaking, the present invention fills these needs by providing a zero power fuse sensing circuit for use in redundant memory applications. In one embodiment, a fuse state sensing circuit is disclosed that senses the state of a fuse, which is coupled between ground rail and a fuse state sensing node. The fuse state sensing node indicates a state of the fuse when rail voltage is provided to the fuse state sensing circuit. In addition, a capacitive element is included that is coupled to the fuse state sensing node. The capacitive element is capable of providing a first amount of current to the fuse state sensing node when an initial voltage is supplied to the rail voltage. The capacitive element is further configured to stop supplying the first amount of current upon reaching a threshold voltage of the capacitive element. The fuse state sensing circuit further includes a keeper latch circuit that is coupled to the fuse state sensing node in parallel with the capacitive element. The keeper latch circuit is capable of latching the state of the fuse state sensing node. In addition, the keeper latch circuit stops supplying current to the fuse state sensing node when the rail voltage is reached if the fuse is intact. Also, when the rail voltage reaches a predetermined voltage and the fuse is blown, the keeper latch circuit continues to supply current to the fuse state sensing node. 
     A further fuse state sensing circuit is disclosed in further embodiment of the present invention. This embodiment includes a fuse that is coupled between ground rail and a fuse state sensing node. The fuse state sensing node indicates a state of the fuse when rail voltage is provided to the fuse state sensing circuit. In addition, a capacitive element is included that is coupled to the fuse state sensing node. The capacitive element is capable of providing a first amount of current to the fuse state sensing node when an initial voltage is supplied to the rail voltage. The capacitive element is further configured to stop supplying the first amount of current upon reaching a threshold voltage of the capacitive element. The fuse state sensing circuit also includes a pull up circuit that is coupled to the fuse state sensing node in parallel with the capacitive element. The pull up circuit stops supplying current to the fuse state sensing node when the rail voltage reaches a predetermined value if the fuse is intact. In addition, as above, the pull up circuit continues to supply current to the fuse state sensing node when the rail voltage is reached and the fuse is blown. 
     In yet a further embodiment of the present invention, a method for sensing a fuse state for a redundancy application is disclosed. An initial voltage is supplied to the rail voltage of the circuit. Also, an initial current is provided to a fuse state sensing node utilizing a capacitive element. As above, the capacitive element ceases to provide current to the fuse state sensing node upon reaching a predetermined voltage threshold. Additional current is supplied to the fuse state sensing node when the fuse is blown utilizing a pull up circuit and a keeper latch circuit. However, when the fuse is intact, the pull up circuit and a keeper latch circuit stop supplying current to the fuse state sensing node. 
     Advantageously, using the embodiments of the present invention, intact fuses within the fuse box do not burn power. By controlling current flow, embodiments of the present invention prevent current flow across intact fuses during normal memory operation. Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention, together with further advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawings in which: 
     FIG. 1 is a block diagram showing prior art redundancy system for replacing defective memory cells with redundant memory cells; 
     FIG. 2 is a schematic diagram showing a prior art fuse state sensing circuit; 
     FIG. 3 is a block diagram showing redundant memory system, in accordance with an embodiment of the present invention; 
     FIG. 4 is a schematic diagram showing a fuse state sensing circuit, in accordance with an embodiment of the present invention; 
     FIG. 5 is a schematic diagram showing a detailed view of inverter having a skewed trip point, in accordance with an embodiment of the present invention; and 
     FIG. 6 is a flowchart showing a method for sensing a fuse state in a redundant memory application, in accordance with an embodiment of the present invention; 
     FIG. 7A is a block diagram showing an exemplary simplified memory generator graphical user interface (GUI) front end view; and 
     FIG. 7B is a block diagram showing an exemplary memory generator backend. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     An invention is disclosed for a zero power fuse sensing circuit for redundancy applications in memories. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some or all of these specific details. In other instances, well known process steps have not been described in detail in order not to unnecessarily obscure the present invention. 
     FIGS. 1 and 2 have been described in terms of the prior art. FIG. 3 is a block diagram showing redundant memory system  300 , in accordance with an embodiment of the present invention. The redundant memory system  300  includes a fuse box  302 , which is in electrical communication with a redundant memory  304 . The redundant memory system  300  provides redundant memory management with low power requirements for redundant memory applications. 
     The redundant memory system  300  provides a fuse box  302  that includes a plurality of fuses for controlling access to memory cells within the redundant memory  304 . In use, the fuses indicate where the faulty memory address are and where the new data is located. The fuses are blown to indicate that redundant memory is being used and to program the new addresses. Advantageously, using the embodiments of the present invention, intact fuses within the fuse box  302  do not burn power. By controlling current flow, embodiments of the present invention prevent current flow across intact fuses during normal memory operation. 
     FIG. 4 is a schematic diagram showing a fuse state sensing circuit  400 , in accordance with an embodiment of the present invention. The fuse state sensing circuit  400  includes a fuse  402  coupled to ground and a fuse state sensing node  404 , which indicates the state of the fuse  402 . The fuse state sensing node  404  is coupled to a capacitive element  406 , a pull up circuit  408 , and a keeper latch circuit  410 . Broadly speaking, the fuse sensing circuit  400  senses the state of the fuse  402  and latches that state. Thereafter, the fuse sensing circuit  400  does not burn power. Hence, each fuse in the fuse box includes the fuse sensing circuitry  400  to self sense. 
     Generally speaking, the capacitive element provides an initial current to the fuse state sensing node  404  until reaching a threshold voltage of the capacitive element, at which point the capacitive element ceases to provide current. Both the pull up circuit  408  and the keeper latch circuit  410  provide current to the fuse state sensing node  404  when the fuse  402  is blown, and cease providing current to the fuse state sensing node when the fuse  402  is intact. In addition, the keeper latch circuit  410  latches the state of the fuse state sensing node. 
     More particularly, when the fuse  402  is not blown, the fuse  402  functions as a short to ground. As a result, the fuse state sensing node  404 , which is coupled to the fuse  402 , is held low. This low state on the fuse state sensing node  404  is also provided to the keeper latch circuit  410 , which is comprised of a p-channel transistor  424  and inverter  422 . As shown in FIG. 4, the p-channel transistor  424  includes a first terminal coupled to V DD , a second terminal coupled to the fuse state sensing node  404 , and a gate coupled to the output of the inverter  422 . 
     The fuse state sensing node  404  determines whether transistor  424  is on or off. Specifically, when the fuse state sensing node  404  is low, the inverter  422  places a high on node  426 , thus turning off transistor  424 . When transistor  424  is off, current does not flow across the terminals of transistor  424 , and thus current is not provided to the fuse state sensing node  404  from transistor  424 . As a result, current does not flow from transistor  424  to ground across the fuse  402  when fuse  402  is intact. 
     In addition, the pull up circuit  408  does not provide current to the fuse state sensing node  404  when the fuse  402  is intact. Specifically, when the fuse  402  is intact, the fuse state sensing node  404  is grounded. As a result, p-channel transistor  416 , which has a first terminal coupled to V DD , a second terminal coupled to node  419 , and a gate coupled to the fuse state sensing node  404 , turns on at power up when V DD  reaches V T . When transistor  416  turns on, current is allowed to flow from V DD  across transistor  416 , thus bringing node  419  high. As a result, p-channel transistor  420 , which includes a gate coupled to node  419 , a first terminal coupled to V DD , and a second terminal coupled the fuse state sensing node  404 , turns off, thus preventing current flow from transistor  420 . 
     Returning to the fuse state sensing node  404 , when V DD  reaches V T  the inverter  422  places a high on node  426 , which turns off transistor  424 . Node  426  being high causes inverter  428  to place a low on node  434 . Node  434  being low causes inverter  430  to place a high on node  436 . Finally, node  436  being high causes inverter  432  to place a low on output node  412 . Hence, a low is sensed on the fuse sensing circuit  400  when the fuse  402  is intact. Moreover, current is not allowed to flow into the fuse state sensing node  404  when the fuse  402  is intact, thus preventing unnecessary power consumption across the fuse  402 . 
     When the fuse  402  is blown, indicating the corresponding redundant memory cell is being used, the operation of the fuse sensing circuitry  400  changes. Specifically, during power up when the fuse  402  is blown, the fuse state sensing node  404  is floating because the ground connection is severed. However, when power is first applied to the fuse sensing circuit  400 , the fuse state sensing node  404  is at ground because current is not yet present in the system. Because of the isolating inverters  428 ,  430 , and  432 , the fuse state sensing node  404  should be high when the fuse  402  is blown in order for the output node  412  will be high and indicate the fuse  402  is blown. 
     Accordingly, when the fuse  402  is blown, the fuse sensing circuit pulls the floating fuse state sensing node  404  high. In particular, during power up the capacitive element  406  and the pull up circuit  408  provide initial current into the fuse state sensing node  404 , which allows the pull up circuit  408  and the keeper latch circuit  410  to pull the fuse state sensing node  404  fully high. As noted previously, the fuse sensing circuit  400  does not burn power once the state of the fuse  402  has been determined. To achieve this property, current cannot flow across the fuse  402  when it is intact. As described previously, both the pull up circuit  408  and the keeper latch circuit  410  turn off current to the fuse state sensing node  404 , and consequently to the fuse  402 , when the fuse  402  is intact. In a similar manner, the capacitive element  406  also does not provide current to the fuse state sensing node  404  once the state of the fuse  402  has been determined. 
     In particular, the capacitive element  406  is not a static pull up transistor because a static pull up transistor would always allow current to flow to the fuse state sensing node  404 , and thus allow the fuse  402  to burn power when intact. The capacitive element  406  always stops current flow through itself when a predefined threshold voltage is reached. In the exemplary embodiment of the FIG. 4, the capacitive element is a capacitive configured transistor  414 , however, it should be noted that any type of capacitor can be utilized as a capacitive element. Larger capacitors allow more current into the fuse state sensing node  404 , however larger capacitors also require more area to implement. The capacitive configured transistor  414  has its source and drain terminals coupled together. In this manner, the gate-to-drain capacitance of capacitive configured transistor  414  can be used to provide limited current to the fuse state sensing node  404 . In particular, as V DD  begins to rise during power up, a coupling occurs across the capacitive configured transistor  414  and the fuse state sensing node  404 . This coupling capacitance causes the fuse state sensing node  404  to begin following the V DD  as it rises. Since fuse  402  is blown, the fuse state sensing node  404  is not pulled to ground and thus rises with V DD . 
     When the fuse state sensing node  404  rises, p-channel transistor  416  turns off because its gate is coupled to the fuse state sensing node  404 . This prevents current from flowing across transistor  416  to node  419 , which stays low. In addition, grounded gate n-channel leakage transistor  418  further ensures node  419  remains low when the fuse  402  is blown. Currently, transistors leak even at zero volts because of the increasingly reduced transistor sizes. That is, the source and drain are very small resulting in leakage across them. Hence, leakage transistor  418  is utilized to hold node  419  low when V DD  is powering up. Holding node  419  low turns on transistor  420 , which provides current to the fuse state sensing node  404  to pull it high. 
     As mentioned previously, on power up all nodes are initially at ground. Hence, both nodes  404  and  426  begin at ground during power up. Then, because of the inverter  422  and transistor  424 , which ever node becomes high first causes the other node to be low. Consequently, embodiments of the present invention skew the trip point of inverter  422  such that it favors a low on node  426 , as explained in greater detail next with reference to FIG.  5 . 
     FIG. 5 is a schematic diagram showing a detailed view of inverter  422  having a skewed trip point, in accordance with an embodiment of the present invention. The inverter  422  includes a p-channel transistor  500  having a first terminal coupled to V DD , a second terminal coupled to node  426 , and a gate coupled to node  404 . In addition, inverter  422  includes an n-channel transistor  502  having a first terminal coupled to node  426 , a second terminal coupled to ground, and a gate coupled to node  404 . 
     To skew inverter  422 , the width of the n-channel transistor  502  is selected to be higher than the width of the p-channel transistor  500 . For example, when the width of the p-channel transistor  500  is “×” the width of the n-channel transistor  502  can be selected to be “36×.” Hence, the n-channel transistor  502  dominates the inverter  422 . As a result, as soon as node  404  reaches V Tn , the n-channel transistor  502  grounds node  426 . Consequently, a low on node  426  turns on transistor  424 , which provides additional current to node  404  to make node  404  high. 
     Thus, there are three mechanisms utilized in the embodiments of the present invention to bring node  404  high when the fuse  402  is blown, namely, the capacitive element  406 , the pull up circuit  408 , and the keeper latch circuit  410 . Each of these mechanisms can bring node  404  high to indicate that the fuse  402  is blown. Moreover, since the fuse  402  is blown, power is not burned when node  404  is made high. 
     As mentioned above, the inverter  422  favors a low on node  426  and a high on node  404 . However, the grounded intact fuse  402  can overcome the inverter&#39;s  422  skewed configuration. That is, when the fuse state sensing node  404  is grounded via fuse  402 , the n-channel transistor  502  turns off. This allows the p-channel transistor  500  to begin providing current to node  426 , regardless of the size of the p-channel transistor  500 , to off turn transistor  424 . 
     FIG. 6 is a flowchart showing a method  600  for sensing a fuse state in a redundant memory application, in accordance with an embodiment of the present invention. In an initial operation  602 , preprocess operations are performed. Preprocess operations can include testing memory to determine the location of faulty cells, determining which fuses to cut to implement the redundant memory, and other preprocess operations that will be apparent to those skilled in the art after a careful reading of the present disclosure. 
     In operation  604 , an initial voltage is supplied to the rail voltage and an initial current is supplied to the fuse state sensing node. During power up the capacitive element provides an initial current into the fuse state sensing node. As noted previously, the fuse sensing circuit does not burn power once the state of the fuse has been determined. To achieve this property, current cannot flow across the fuse when it is intact. Advantageously, the capacitive element also does not provide current to the fuse state sensing node once the state of the fuse has been determined. 
     In particular, the capacitive element is not a static pull up transistor because a static pull up transistor would always allow current to flow to the fuse state sensing node, and thus allow the fuse to burn power when intact. The capacitive element always stops current flow through itself when a predefined threshold voltage is reached. For example, the capacitive element can be a capacitive configured transistor or any other type of capacitor. When using the capacitive configured transistor, the source and drain terminals are coupled together. In this manner, the gate-to-drain capacitance of capacitive configured transistor can be used to provide limited current to the fuse state sensing node. In particular, as V DD  begins to rise during power up, a coupling occurs across the capacitive configured transistor and the fuse state sensing node. This coupling capacitance causes the fuse state sensing node to begin following the V DD  as it rises. 
     A decision is then made as to whether the fuse is blown, in operation  606 . When the fuse is intact it grounds the fuse state sensing node, thus bringing the fuse state sensing node low regardless of the current applied to it. However, when the fuse is blown, the fuse state sensing node floats, and as a result will begin to rise when the capacitive elements provides current to the fuse state sensing node. Depending on whether the fuse state sensing node begins to rise or remains grounded, the fuse sensing circuitry can determine whether the fuse is blown. If the fuse is not blown, the method  600  branches to operation  608 . Otherwise, the method branches to operation  614 . 
     In operation  608 , the fuse state sensing node is grounded via the fuse. As stated above, the intact fuse can overcome all attempts to raise the fuse state sensing node high. Thus, when the fuse is present, the fuse state sensing node will be grounded, thus turning off current providing transistors of the pull up circuit and keeper latch circuit, as explained subsequently. 
     In operation  610 , the fuse sensing circuitry ceases to provide current to the fuse state sensing node. As mentioned above, when the fuse state sensing node is low, current providing transistors of the pull up circuit and keeper latch circuit are turned off. In this manner, current is not allowed to flow to ground across the fuse. As a result, power is not burned using the fuse sensing circuitry of the embodiments of the present invention. 
     When the fuse is blown, additional current is supplied to the fuse state sensing node, in operation  614 . As mentioned above, there are three mechanisms utilized in the embodiments of the present invention to bring the fuse state sensing node high when the fuse is blown, namely, the capacitive element, the pull up circuit, and the keeper latch circuit. The capacitive element provides an initial amount of current to the fuse state sensing node, which raises the fuse state sensing node. When this occurs, the pull up circuitry and the keeper latch circuitry take over and provide additional current to the floating fuse state sensing node. In addition, the keeper latch circuit latches the state of the fuse state sensing node in operation  616 . Since the fuse is not present to ground the fuse state sensing node, current does not flow across the fuse. As a result, power is not burned when the fuse is blown. 
     Post process operations are performed in operation  612 . Post process operations can include redirecting memory addresses to new redundant memory, and other post process operations that will be apparent to those skilled in the art after a careful reading of the present disclosure. Advantageously, power is not burned using the fuse sensing circuitry of the embodiments of the present invention, regardless of whether the fuse is cut or intact. 
     In one embodiment, optimum placement and utilization of the techniques of the present invention is implemented utilizing a generator. The generator should be generally understood to include one or more generators, each generator can be specifically optimized for a particular task. Such tasks or sub-tasks, for example, can include generating a fuse box  302  (e.g., as shown in FIG. 3) to be used with a memory device. 
     FIG. 7A is a block diagram showing an exemplary simplified memory generator graphical user interface (GUI) front end  700 , in accordance with an embodiment of the present invention. The exemplary memory generator GUI  700  illustrates one view utilized for entering parameters into fields  702  to define a particular memory application. Broadly speaking, the memory generator checks the validity of the entered data and executes appropriate generators to define the memory application. After receiving data utilizing the GUI front end view  700 , a memory generator of the embodiments of the present invention processes the data utilizing a memory generator backend, as described next with reference to FIG.  7 B. 
     FIG. 7B is a block diagram showing an exemplary memory generator backend  750 , in accordance with an embodiment of the present invention. The memory generator backend  750  comprises an XPAR process  752 , a tiling engine  754 , a Bifilator process  756 , a CDLGEN process  764 , and a cell library  766 . Generally speaking, these processes function together to generate a LEF model  758 , a GDSII model  760 , and a SPICE model  762  for the particular memory application. The LEF model  758  comprises place and route information, which is utilized by routers to manufacture integrated circuits. The GDSII model  760  comprises mask layouts and is utilized by semiconductor foundries. The SPICE model  762  includes circuit interconnection definitions, operational properties, and schematic diagrams of the memory application. Thus, the designer can use the SPICE model of the application for cross verification. 
     As mentioned above, the exemplary memory generator backend  750  processes the data received via the GUI front end  700 . More specifically, the XPAR process  752  encapsulates the rules needed to utilize particular cell layouts stored in the cell library. These rules, along with the parameter data for the memory application are then provided to the tiling engine  754  for optimization and cell placement. By separating the functions of the XPAR process  752  from those of the tiling engine  754 , individual rules can be altered for specific applications without altering the functions and placement algorithms utilized in the timing engine  754 . 
     The Bifilator process  756  generates an interface around a particular device or memory array. Generally, on a RAM there may exist over one thousand routing points for interfacing with the RAM. As a result, the entire routing configuration may change when a user changes the placement of the RAM, requiring intense reconfiguration. To address this issue, the Bifilator process  756  builds an interface around the RAM, which the user can use to interface with the RAM without configuring each routing point. 
     The present invention may be implemented using any type of integrated circuit logic, state machines, or software driven computer-implemented operations. By way of example, a hardware description language (HDL) based design and synthesis program may be used to design the silicon-level circuitry necessary to appropriately perform the data and control operations in accordance with one embodiment of the present invention. 
     The invention may employ various computer-implemented operations involving data stored in computer systems. These operations are those requiring physical manipulation of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. Further, the manipulations performed are often referred to in terms, such as producing, identifying, determining, or comparing. 
     Any of the operations described herein that form part of the invention are useful machine operations. The invention also relates to a device or an apparatus for performing these operations. The apparatus may be specially constructed for the required purposes, or it may be a general purpose computer selectively activated or configured by a computer program stored in the computer. In particular, various general purpose machines may be used with computer programs written in accordance with the teachings herein, or it may be more convenient to construct a more specialized apparatus to perform the required operations. Although the foregoing invention has been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.