Abstract:
A decoupling circuit for decoupling conduction lines from each other, the circuit including at least one pass gate element having conduction terminals connected to the conduction lines and having at least one control terminal. The decoupling circuit includes at least one protection circuit inserted between the control terminal and at least one of the conduction lines, and including at least one protection transistor connected to the control terminal and to the at least one conduction line, and configured to take in a disturbing signal passing through the pass gate element (N 1 ) to properly decouple the conduction lines from each other on the occurrence of a disturbing condition.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a circuit for decoupling conduction lines from each other. More specifically, the invention relates to a circuit for decoupling conduction lines from each other, which circuit includes at least one pass gate element having conduction terminals connected to the conduction lines and having at least one control terminal.  
           [0003]    2. Description of the Art  
           [0004]    As it is well known, two conduction lines of an electronic circuit are normally connected together through a decoupling circuit  10  as shown in FIG. 1 that comprises essentially a pass gate element.  
           [0005]    In particular, the decoupling circuit  10  includes a pass gate decoupling transistor operative to connect the lines to each other allowing a signal to go through when in the ‘on’ state. It is operative to isolate the lines from each other and prevent the signal from going through when in the ‘off’ state.  
           [0006]    As shown schematically in FIG. 1, first L 1  and second L 2  conduction lines are connected to each other through a pass gate decoupling circuit  10 , essentially comprising a decoupling transistor N 1 .  
           [0007]    The decoupling transistor N 1  has its conduction terminals respectively connected to said conduction lines L 1  and L 2 , and has a control or gate terminal connected to an input inverter I 1 . The decoupling transistor N 1  may be a pass gate MOS transistor of the N or the P type, for example.  
           [0008]    It should be noted that, for example when enhancement transistors are used, the decoupling condition of the conduction lines L 1  and L 2  (transistor ‘off’) is obtained by equalizing the gate terminal voltage and the bulk terminal voltage.  
           [0009]    In this way, so long as the voltage signals presented on the two conduction lines L 1  and L 2  connected to the conduction terminals are above a ground reference level GND for an N-type decoupling transistor N 1 , or below a supply level Vdd for a P-type decoupling transistor, as it is usually happens the case in most circuits, the decoupling transistor N 1  will actually be ‘off’ and the conduction lines L 1 , L 2  properly decoupled.  
           [0010]    On the other hand, if the voltage signals at the conduction terminals lie outside the above ranges, i.e., are below the ground reference level GND for an N-type decoupling transistor N 1 , or above the supply level Vdd for a P-type decoupling transistor, the decoupling transistor N 1  might fail to go ‘off’, and the conduction lines L 1 , L 2  might become improperly coupled.  
           [0011]    Such abnormal operating condition are commonly known as disturbed conditions, and the voltage or current signals that originate them will be referred to as disturbing signals hereinafter.  
           [0012]    In particular, in the instance of an enhancement decoupling transistor N 1  of the N type, having its bulk terminal and gate terminal connected to a ground reference GND and, accordingly, being in a closed channel condition, the decoupling transistor N 1  is turned off when the voltages at the conduction terminals are positive voltages.  
           [0013]    In the event of one of the conduction terminals, e.g., the drain terminal, being at a lower voltage than the ground reference voltage GND, the voltage Vgs between the further conduction terminal, e.g., the source terminal, and the gate terminal might exceed the threshold voltage of the transistor, so that the latter shows out to be inexpediently on.  
           [0014]    Thus, under the conditions outlined hereinabove, a decoupling transistor N 1  of the N type is ineffective for the purpose of isolating the two conduction lines L 1  and L 2  from each other, and would rather allow an objectionable signal through.  
           [0015]    This is congruously true for a P-type transistor, whenever the voltage at one of its conduction, source or drain terminals, is higher than the supply reference Vdd used here for biasing its bulk and gate terminals.  
           [0016]    The particular instance of an N-type pass gate transistor will be considered hereinafter, it being understood that the same considerations are also true for a P-type transistor, where the terms are consistently substituted with their duals (transistor Nch⇄transistor Pch, reference GND⇄reference Vdd, higher than⇄lower than, etc.), as it is obvious to a skilled person in the art.  
           [0017]    The aforementioned disturbing signals appear in various operating condition of electronic circuits, as exemplified here below:  
           [0018]    1) Inside a generic electronic circuit:  
           [0019]    a. when two internal circuit nodes have different internal ground references (Vcc), because of resistances internal of the electronic circuit; and  
           [0020]    b. when a floating node is driven by capacitive effect.  
           [0021]    2) In an I/O interface circuit on nodes that are connected to pads external of the electronic circuit:  
           [0022]    a. when voltage undershoots or overshoots occur because of inductive effects; and  
           [0023]    b. when outside of the I/O interface circuit a signal below the ground reference (or likewise, above the supply reference Vdd) is.  
           [0024]    Electrostatic discharges (ESD) will not further be taken into account because the circuitry is assumed to incorporate adequate ESD protection structures.  
           [0025]    The underlying technical problem addressed by the disclosed embodiments of this invention is to provide satisfactory isolation between conduction lines that are interconnected by a pass gate element, despite the presence of a disturbing signal on the lines, so as to avoid the malfunction condition of prior circuits.  
         SUMMARY OF THE INVENTION  
         [0026]    The principle on which the embodiments of this invention stand is the one of connecting, in a circuit for decoupling conduction lines that are interconnected through a pass gate element, a protection circuit suitable to avoid the propagation of a disturbing signal over the lines, so as to provide the right turn-off condition for the pass gate element, meaning the right isolation condition of the conduction lines.  
           [0027]    Based on the above principle, the technical problem is solved by a decoupling circuit for decoupling conduction lines from each other, the circuit having at least pass one gate element with conduction terminals connected to the conduction lines and at least one control terminal; and at least one protection circuit inserted between the control terminal and the at least one conduction line, the protection circuit including at least one protection transistor connected to the control terminal and to the at least one of the conduction lines and configured to take in any disturbing signal passing through the pass gate element to properly decouple the conduction lines from each other on the occurrence of a disturbing condition resulting from the disturbing signal.  
           [0028]    In accordance with another aspect of the invention, a decoupling circuit is provided that has a decoupling transistor with first and second conduction terminals connected to first and second conduction lines, and a control terminal coupled to an inverter, and a protection circuit coupled to the inverter and the second conduction line, the protection circuit including a pull-up transistor having a first terminal coupled to a voltage source and a second terminal coupled to the second conduction line via a second decoupling transistor, and a control terminal coupled to the inverter, the second decoupling transistor having a first terminal coupled to the second terminal of the pull up transistor, a second terminal coupled to the second conduction line, and a control terminal coupled to the inverter.  
           [0029]    In accordance with yet another aspect of the present invention, a decoupling circuit is provided that includes a decoupling transistor having first and second conduction terminals coupled to first and second conduction lines, respectively, a control terminal coupled to the output of an inverter, and a protection circuit comprising a protection transistor having a first conduction terminal coupled to the first conduction line, a second conduction terminal coupled to the output of the inverter, and a control terminal coupled to a ground reference potential.  
           [0030]    In accordance with yet a further aspect of the present invention, a decoupling circuit is provided that includes a decoupling transistor having first and second conduction terminals coupled to first and second conduction lines, respectively, and a control terminal coupled to the output of an inverter, and further including a first protection circuit coupled between the second conduction line and the decoupling transistor and further coupled to the output of the inverter, and a second protection circuit coupled to the first conduction line and to the output of the inverter, the first and second protection circuits configured as described above. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0031]    The features and advantages of a decoupling circuit according to the invention will be apparent from the following description of embodiments thereof, given by way of nonlimitative examples with reference to the accompanying drawings, wherein:  
         [0032]    [0032]FIG. 1 schematically shows a conduction line decoupling circuit according to the prior art;  
         [0033]    [0033]FIG. 2 schematically shows a first embodiment of a conduction line decoupling circuit according to the invention;  
         [0034]    [0034]FIG. 3 schematically shows a second embodiment of a conduction line decoupling circuit according to the invention; and  
         [0035]    [0035]FIG. 4 schematically shows a third embodiment of a conduction line decoupling circuit according to the invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0036]    Shown in FIG. 2 of the drawings is a first embodiment of a decoupling circuit  1  for decoupling conduction lines L 1  and L 2  from each other, according to the invention. Advantageously in this invention, this decoupling circuit incorporates a protection circuit, generally shown at  2  in schematic form.  
         [0037]    The decoupling circuit  1  basically comprises, and in a similar way as the aforementioned prior art, a decoupling transistor N 1  connected between a first L 1  and a second L 2  conduction lines.  
         [0038]    In particular, the decoupling transistor N 1  has its conduction terminals respectively connected to said conduction lines L 1  and L 2 , and has a gate or control terminal G 1  connected to an input inverter I 1 . The decoupling transistor N 1  may be a pass gate transistor of the N type, for example.  
         [0039]    Advantageously in this invention, a protection circuit  2  is connected between the gate terminal G 1  of the decoupling transistor N 1  and at least one conduction line, in particular the second conduction line L 2 , and is connected to said input inverter I 1 .  
         [0040]    In particular, the protection circuit  2  comprises a first protection transistor P 2 , being connected between a supply voltage reference Vdd and an internal conduction line L 3  and having its gate terminal connected to the gate terminal G 1  of the decoupling transistor N 1 .  
         [0041]    The protection circuit  2  further comprises a second protection transistor N 2  having its conduction terminals connected to said second conduction line L 2  and to said internal conduction line L 3 , and having a gate terminal connected to the gate terminal G 1  of the decoupling transistor N 1 .  
         [0042]    The first protection transistor P 2  is a PMOS transistor, whereas the second protection transistor N 2  is an NMOS transistor. Thus, the protection circuit  2  has the MOS transistor P 2  in a pull-up configuration and the MOS transistor N 2  in a pass-gate configuration.  
         [0043]    The operation of the decoupling circuit  1  incorporating the protection circuit  2  of this invention will now be described.  
         [0044]    When the output of the input inverter I 1  is grounded, the internal conduction line L 3  is held high by the first protection transistor P 2 , and any disturbing current going through the decoupling transistor N 1  would be bypassed from the supply voltage reference Vdd by the first protection transistor P 2  rather than going directly through the second conduction line L 2 .  
         [0045]    The protection circuit  2  is effective in that a disturbing current can be picked up by the PMOS transistor, harmlessly to this transistor, or as far as the current at stake does not affect the supply voltage Vdd to any significant extent.  
         [0046]    This holds true if the disturbing current is temporary, or is not too large, this condition being dependent on the characteristics of the circuitry connected to the conduction lines L 1  and L 2 .  
         [0047]    Briefly, the protection circuit  2  will take in a disturbing signal passing through the decoupling transistor N 1  and prevent it from propagating to the second conduction line L 2 .  
         [0048]    Alternatively, a disturbing signal, especially a voltage signal, could be avoided by driving the gate terminal of the decoupling transistor N 1  with a voltage below the voltage level present at the bulk terminal (and equal to the ground reference GND), such that it approaches or equals the disturbing voltage. However, this driving voltage is not generally available in conventional integrated circuits because it falls outside standard ranges of supply voltages.  
         [0049]    [0049]FIG. 3 shows a second embodiment of a decoupling circuit  1  incorporating a protection circuit  3  according to the invention.  
         [0050]    Advantageously in this invention, the protection circuit  3  is connected between the gate terminal G 1  of the decoupling transistor N 1  and at least one conduction line, in particular the first conduction line L 1 .  
         [0051]    The protection circuit  3  comprises a protection transistor N 3  having its conduction terminals connected to the gate terminal G 1  of the decoupling transistor N 1  and to said first conduction line L 1 , and having its gate terminal connected to a ground reference GND.  
         [0052]    The protection transistor N 3  has its source terminal connected to the first conduction line L 1 , where a disturbing signal (especially a voltage signal) would appear, and has its drain terminal connected to the gate terminal G 1  of the decoupling transistor N 1 .  
         [0053]    Advantageously in this invention, the protection transistor N 3  is a native NMOS transistor.  
         [0054]    The operation of the decoupling circuit  1  incorporating the protection circuit  3  of this invention will now be described.  
         [0055]    The protection circuit  3  holds the decoupling transistor N 1  in the ‘off’ state by driving the voltage to its gate terminal G 1  with a lower voltage than the ground reference GND. However, the protection circuit  3  does not require other voltage levels than the ground reference GND, and utilizes the disturbance-causing voltages as useful signals to drive the gate terminal G 1  of the decoupling transistor N 1 .  
         [0056]    Advantageously in this invention, the protection transistor N 3  is of the native type, having a lower threshold voltage than the decoupling transistor N 1 .  
         [0057]    The protection transistor N 3 , when in the ‘on’ state, connects the gate terminal G 1  of the decoupling transistor N 1  to the first conduction line L 1 .  
         [0058]    In normal conditions, i.e., with the voltage on the first conduction line L 1  higher than the ground reference value GND, the protection transistor N 3  would be ‘off’ and the decoupling transistor N 1  driven directly from the input inverter I 1 .  
         [0059]    As the voltage on the first conduction line L 1  drops below the ground reference value GND, the protection transistor N 3 , having its gate terminal grounded, tends to enter the ‘on’ state because its gate-source voltage Vgs 3  increases as the voltage on the first conduction line L 1  decreases.  
         [0060]    When the protection transistor N 3  turns on, the current flowing through it tends to depress the voltage at the gate terminal G 1  of the decoupling transistor N 1 .  
         [0061]    Thus, the voltage at the gate terminal G 1  follows the source terminal voltage, maintaining the gate-source voltage Vgs 1  of the decoupling transistor N 1  constant.  
         [0062]    By having a lower threshold voltage Vth 3  than a threshold voltage Vth 1  of the decoupling transistor N 1 , the protection transistor N 3  turns on before the gate-source voltage Vgs 1  exceeds the threshold voltage Vth 1  of the decoupling transistor N 1 .  
         [0063]    Thus, the decoupling transistor N 1  is held ‘off’ and prevents a disturbing signal to pass on to the conduction lines L 1  and L 2 .  
         [0064]    [0064]FIG. 4 shows a third embodiment of a decoupling circuit  1  incorporating a protection circuit  4  according to the invention.  
         [0065]    Advantageously in this invention, the protection circuit  4  has a first portion  42 , which is connected between the gate terminal G 1  of the decoupling transistor N 1  and at least one conduction line, in particular the second line L 2 , and connected to said input inverter I 1 . The protection circuit also has a second portion  43  connected between the gate terminal G 1  of the decoupling transistor N 1  and at least another conduction line, in particular the first line L 1 .  
         [0066]    Similar as in the first embodiment, the first portion  42  comprises a first protection transistor P 2 , which is inserted between a supply voltage reference Vdd and an internal conduction line L 3 , and has its gate terminal connected to the gate terminal G 1  of the decoupling transistor N 1 .  
         [0067]    The first portion  42  further comprises a second protection transistor N 2  having its conduction terminals connected to said second conduction line L 2  and said internal conduction line L 3 , and having a gate terminal connected to the gate terminal G 1  of the decoupling transistor N 1 .  
         [0068]    Similar as in the second embodiment, moreover, the second portion  43  comprises a protection transistor N 3  having its conduction terminals connected to the gate terminal G 1  and to said first conduction line L 1 , and having its gate terminal connected to a ground reference GND.  
         [0069]    Advantageously in this invention, the second protection transistor N 2  in the first portion  42  has a threshold voltage value equal to the value of the threshold voltage Vth 1  of the decoupling transistor N 1 .  
         [0070]    In this case, with the protection transistor N 3  of the second portion  43  turned on, the gate-source voltage Vgs 1  of the decoupling transistor N 1  is held almost constant and close to the value of the transistor threshold voltage Vth 1 .  
         [0071]    Accordingly, the decoupling transistor N 1  is highly resistive rather than truly ‘off’, and the current flowing through the first protection transistor P 1  in the first portion  42  is much smaller than the current through the protection circuit  2  of FIG. 2.  
         [0072]    Finally, it should be noted that disturbing signals, specifically voltage signals, are natively limited by the junction diode of the decoupling transistor N 1  being forward biased and preventing a disturbing voltage from exceeding the junction built-in voltage by any significant amount.  
         [0073]    Summarizing, this decoupling circuit prevents possible disturbing signals produced by voltages lying out of the normal supply and ground reference ranges from causing pass gate elements to be turned on to whose nodes, connected to conduction lines, the out-of-range voltages are applied.  
         [0074]    From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims and the equivalents thereof.