Abstract:
Tri-state devices having exclusive gate output control include a tri-state device having first and second inputs and a tri-state output, a normally-off transistor connected in series between the tri-state output and a first reference potential (e.g., VCC or VSS) and an exclusive gate (e.g., NOR, OR) having first and second inputs coupled to the first and second inputs of said tri-state device, respectively, and an output electrically coupled to a control electrode of said normally-off transistor so that the tri-state output becomes electrically connected through the normally-off transistor to the first reference potential whenever the first and second inputs of said tri-state device are at different logic potentials. However, the normally-off transistor is maintained in a nonconductive state to reduce power consumption whenever the output of the tri-state device is switched to VCC or VSS.

Description:
FIELD OF THE INVENTION 
     The present invention relates to integrated circuit devices, and more particularly to tri-state devices and methods of operating same. 
     BACKGROUND OF THE INVENTION 
     Tri-state devices are used in a large number of applications which require the establishment of a high-impedance output state in addition to &#34;high&#34; and &#34;low&#34; logic states. However, under certain conditions the occurrence of a high impedance state can cause circuits which are coupled to the output of the tri-state device to become unstable. As will be understood by those skilled in the art, FIG. 1 illustrates a prior art tri-state device. Here, if the two inputs A and B have identical logic levels, then the output &#34;Y&#34; of the tri-state device will switch to a logic &#34;low&#34; level (e.g., VSS) or a logic &#34;high&#34; level (e.g., VCC) depending on the value of the logic level. In particular, if the inputs A and B are all at the logic &#34;low&#34; levels, then logic &#34;high&#34; levels are generated at the outputs of inverters IG1 and IG2. When this occurs, PMOS transistors MP1 and MP2 are turned off and NMOS transistors MN1 and MN2 are turned on and pull the output Y to VSS (e.g., logic &#34;0&#34;). In contrast, if the inputs A and B are all at logic &#34;high&#34; levels, the output Y is switched to VCC (e.g., logic &#34;1&#34;). 
     But, if the logic levels of the inputs A and B are different (i.e., A=0 &amp; B=1 or A=1 &amp; B=0), the output Y of the tri-state device enters a floating state. For example, if the input A=0 and the input B=1, then inputs A and B are inverted to logic &#34;high&#34; and &#34;low&#34; levels, respectively, via the inverters IG1 and IG2. In response, PMOS transistor MP1 and NMOS transistor MN1 are turned on and PMOS transistor MP2 and NMOS transistor MN2 are turned off. Thus, the output Y of the tri-state device become electrically disconnected from both VCC and VSS and enters a high impedance state. This is also true for the case where A=1 and B=0. The operation of the tri-state device of FIG. 1 is summarized by Table 1. The notation &#34;Z&#34; denotes a high impedance state. 
     
                       TABLE 1______________________________________Node     Case 1  Case 2      Case 3                              Case 4______________________________________A        0       0           1     1B        0       1           0     1Y        0       Z           Z     1INA      L       Float       Float H______________________________________ 
    
     Thus, if two inputs of the tri-state circuit as shown in FIG. 1 have different logic levels, the output signal line INA will be allowed to float. In this case, if the value of a load capacitor CL cannot sufficiently drive the fan-out of the following stage of a circuit, malfunction of the circuit may occur. In order to prevent such a malfunction, the occurrence of the floating signal line INA is prevented by adding a pull-up resistor (or a pull-down resistor) as shown in FIG. 2. 
     Referring now to the tri-state device of FIG. 2, if the two inputs A and B have different logic levels (e.g., A=0, &amp; B=1, or A=1 &amp; B=0), the output Y will enter a floating state, but the output signal line INA will be pulled to VCC by the pull-up resistor PR. Thus, the likelihood of an unstable condition is reduced. However, if the inputs A and B are at the logic &#34;low&#34; levels, the PMOS transistors MP1 and MP2 are turned off and the NMOS transistors MN1 and MN2 are turned on. Thus, the output Y of the tri-state device switches to a logic &#34;low&#34; state. When this occurs, the power supply voltage VCC will become connected to VSS via the pull-up resistor PR and the NMOS transistors MN1 and MN2. Unfortunately, this forms a continuous current path (&#34;i path&#34;) from VCC to VSS which can be excessive. The same is true even if a pull-down resistor is used instead of the pull-up resistor PR because if inputs A and B are set at the logic &#34;high&#34; level, the PMOS transistors MP1 and MP2 will turn on and provide current to the pull-down resistor (not shown). 
     The operation of the tri-state circuit using the pull-up resistor PR can be explained by the following Table 2, and the operation of the tri-state circuit using the pull-down resistor can be explained by the following Table 3. 
     
                       TABLE 2______________________________________Node       Case 1  Case 2     Case 3                               Case 4______________________________________A          0       0          1     1B          0       1          0     1Y          0       Z          Z     1INA        VSS     VCC        VCC   VCCCurrent path      Yes     No         No    No______________________________________ 
    
     
                       TABLE 3______________________________________Node       Case 1  Case 2     Case 3                               Case 4______________________________________A          0       0          1     1B          0       1          0     1Y          0       Z          Z     1INA        VSS     VSS        VSS   VCCCurrent path      No      No         No    Yes______________________________________ 
    
     Therefore, when a pull-up or pull-down resistor is used to prevent the floating state of the tri-state device, there remains the problem of excessive power consumption due to the unnecessary current path as described above. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide a tri-state device which is capable of generating stable output signal lines. 
     It is another object of the present invention to provide a tri-state device which has reduced power requirements. 
     These and other objects, advantages and features of the present invention are provided by a tri-state device which has an exclusive gate output control circuit. The exclusive gate output control circuit eliminates the potentially unstable floating state condition and the high current requirements associated with prior art tri-state devices. In particular, the present invention includes a tri-state device having first and second inputs and a tri-state output &#34;Y&#34;, a normally-off transistor connected in series between the tri-state output and a first reference potential (e.g., VCC or VSS) and an exclusive gate (e.g., XNOR, XOR) having first and second inputs. The inputs of the exclusive gate are coupled to the first and second inputs of the tri-state device, respectively. In addition, the output of the exclusive gate is electrically coupled to a gate electrode of the normally-off transistor so that the tri-state output becomes electrically connected through the normally-off transistor to the first reference potential whenever the first and second inputs of the tri-state device are at different logic potentials. 
     However, the normally-off transistor is maintained in a nonconductive state to reduce power consumption whenever the output Y of the tri-state device is switched to VCC or VSS. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is an electrical schematic of a first tri-state device according to the prior art. 
     FIG. 2 is an electrical schematic of a second tri-state device according to the prior art. 
     FIG. 3 is an electrical schematic of a tri-state device according to a first embodiment of the present invention. 
     FIG. 4 is an electrical schematic of a tri-state device according to a second embodiment of the present invention. 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
     The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. 
     Referring now to FIG. 3, a tri-state device according to a first embodiment of the present invention is illustrated. According to this embodiment, first and second NMOS transistors MN1 and MN2 are electrically connected in series between an output Y of the tri-state device and VSS (e.g., GND) and first and second PMOS transistors MP1 and MP2 are electrically connected in series between the output Y and the power supply potential (i.e., VCC). First and second inverters IG1 and IG2 are also provided in series between the gate electrodes of the NMOS and PMOS transistors and the inputs A and B, as illustrated. As will be understood by those skilled in the art, whenever inputs A and B are both switched to logic 1 potentials, the output Y of the tri-state device will be pulled up to VCC. Alternatively, whenever inputs A and B are both switched to logic 0 potentials, the output Y will be pulled down to VSS. However, according to the present invention, a two-input exclusive OR (XOR) gate is preferably connected between nodes N1 and N2, as illustrated, and a gate electrode of a normally-off NMOS pull-down transistor (PMN). Alternatively, a two-input exclusive NOR (XNOR) gate and a PMOS pull-down transistor (not shown) can be used in place of the illustrated XOR gate and NMOS transistor. Thus, the output signal line INA will also be pulled down to VSS whenever the inputs A and B are at different logic potentials because a logic 1 output will be generated by the XOR gate to turn on the NMOS pulled-down transistor PMN. But, because the output of the XOR gate remains at a logic 0 potential whenever the inputs A and B are the same, the NMOS pull-down transistor PMN will remain nonconductive when the inputs A and B are the same. Thus, any high current path between VCC and VSS is eliminated even when the PMOS transistors MP1 and MP2 are turned on. 
     In particular, referring now to FIG. 3 and Table 4, the operation of the tri-state device according to the first embodiment of the present invention will now be more fully described. Here, if the two inputs A and B have different logic levels (e.g., A=0 &amp; B=1 or A=1 &amp; B=0), the pull-down transistor PMN will turn on, thereby eliminating any floating state at the output Y. That is, if A=0 and B=1, these signals are inverted to the logic &#34;high&#34; and &#34;low&#34; levels via the inverters IG1 and IG2, respectively. In response, PMOS transistor MP1 and NMOS transistor MN1 are turned on and the PMOS transistor MP2 and NMOS transistor MN2 are turned off. The output Y of the tri-state device then enters the high impedance state &#34;Z&#34;. However, since the exclusive OR gate (XOR) is connected to the first and second input nodes N1 and N2, the XOR gate outputs a logic &#34;high&#34; signal to the gate of the pull-down transistor PMN. Once the pull-down transistor PMN turns on, the output signal line INA is pulled to VSS. Thus, the high impedance state of the tri-state device is converted to a logic &#34;low&#34; state. This is also true for the case where A=1 and B=0. 
     However, if these two inputs A and B are logic &#34;high&#34;, the PMOS transistors will turn on and pull output Y to a logic 1 potential, the NMOS transistors MN1 and MN2 will turn off and the output of the XOR gate will be set at a logic 0 potential to turn the pull-down transistor PMN off. This isolates the output signal line INA from VSS and eliminates any direct current path between VCC and VSS. 
     
                       TABLE 4______________________________________Node       Case 1  Case 2     Case 3                               Case 4______________________________________A          0       0          1     1B          0       1          0     1Y          0       Z          Z     1INA        VSS     VSS        VSS   VCCCurrent path      No      No         No    No______________________________________ 
    
     Referring now to FIG. 4, a tri-state device according to a second embodiment of the present invention is illustrated. According to this second embodiment, first and second NMOS transistors MN1 and MN2 are electrically connected in series between an output Y of the tri-state device and VSS (e.g., GND) and first and second PMOS transistors MP1 and MP2 are electrically connected in series between the output Y and the power supply potential (i.e., VCC). First and second inverters IG1 and IG2 are also provided in series between the gate electrodes of the NMOS and PMOS transistors and the inputs A and B, as illustrated. As will be understood by those skilled in the art, whenever inputs A and B are both switched to logic 1 potentials, the output Y of the tri-state device will be pulled up to VCC. Alternatively, whenever inputs A and B are both switched to logic 0 potentials, the output Y will be pulled down to VSS. However, according to the present invention, a two-input exclusive NOR (XNOR) gate is preferably connected between nodes N1 and N2, as illustrated, and a gate electrode of a normally-off PMOS pull-up transistor (PMP). Alternatively, a two-input exclusive OR (XOR) gate and an NMOS pull-up transistor (not shown) can be used in place of the illustrated XNOR gate and PMOS transistor. Thus, the output signal line INA will also be pulled up to VCC whenever the inputs A and B are at different logic potentials because a logic 0 output will be generated by the XNOR gate to turn on the PMOS pull-up transistor PMP. But, because the output of the XNOR gate remains at a logic 1 potential whenever the inputs A and B are the same, the PMOS pull-up transistor PMP will remain nonconductive when the inputs A and B are the same. Thus, any high current path between VCC and VSS is eliminated even when the NMOS transistors MN1 and MN2 are turned on. 
     In particular, referring now to FIG. 4 and Table 5, the operation of the tri-state device according to the second embodiment of the present invention will now be more fully described. Here, if the two inputs A and B have different logic levels (e.g., A=0 &amp; B=1 or A=1 &amp; B=0), the PMOS pull-up transistor PMP will turn on, thereby eliminating any floating state at the output Y. That is, if A=0 and B=1, these signals are inverted to the logic &#34;high&#34; and &#34;low&#34; levels via the inverters IG1 and IG2, respectively. In response, PMOS transistor MP1 and NMOS transistor MN1 are turned on and the PMOS transistor MP2 and NMOS transistor MN2 are turned off. 
     The output Y of the tri-state device then enters the high impedance state. 
     However, since the exclusive NOR gate (XNOR) is connected to the first and second input nodes N1 and N2, the XNOR gate outputs a logic &#34;low&#34; signal to the gate of the PMOS pull-up transistor PMP. Once the pull-up transistor PMP turns on, the output signal line INA is pulled to VCC. Thus, the high impedance state of the tri-state device is converted to a logic &#34;high&#34; state. This is also true for the case where A=1 and B=0. 
     However, if these two inputs A and B are logic &#34;high&#34;, the PMOS transistors will turn on and pull output Y to a logic 1 potential, the NMOS transistors MN1 and MN2 will turn off and the output of the XNOR gate will be set at a logic 1 potential to turn the pull-up transistor PMP off. This isolates the output signal line INA from VCC and eliminates any direct current path between VCC and VSS. 
     
                       TABLE 4______________________________________Node       Case 1  Case 2     Case 3                               Case 4______________________________________A          0       0          1     1B          0       1          0     1Y          0       Z          Z     1INA        VSS     VCC        VCC   VCCCurrent path      No      No         No    No______________________________________ 
    
     As described above with reference to FIGS. 3 and 4, it is possible to remove the floating state of the output signal line INA and to isolate the current path by using the combinational circuit, e.g. the exclusive OR gate XOR and NMOS pull-down transistor PMN or the exclusive NOR gate XNOR and PMOS pull-up transistor PMP (or exclusive NOR gate and PMOS pull-down transistor or the exclusive OR gate and NMOS pull-up transistor). This enables a remarkable reduction in the total power consumption of the device. Therefore, the circuit for stabilizing the output of the tri-state circuit according to the present invention can stabilize the operation of the tri-state circuit by preventing the floating state and can isolate the unnecessary current path thereby reducing power consumption. 
     In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.