Abstract:
A level shift driver circuit comprises a level shift circuit and a driver circuit. The driver circuit comprises a first and a second P-type transistors and a first and a second N-type transistors coupled in series. When a first input signal of the level shift circuit is at an operative voltage, the level shift circuit turns off the second N-type transistor. A control terminal of the first N-type transistor receives the operative voltage to avoid a gate-induced drain leakage current of the second N-type transistor. When the first input signal is at a system base voltage, the level shift circuit turns off the first P-type transistor. A control terminal of the second P-type transistor receives the operative voltage to avoid a gate-induced drain leakage current of the first P-type transistor.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This non-provisional application claims priority of U.S. provisional application U.S. 62/022,166, filed on Jul. 8, 2014, included herein by reference in its entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a level shift driver circuit, and more particularly, a level shift driver circuit capable of reducing gate-induced drain leakage current. 
     2. Description of the Prior Art 
     When the level shift driver circuit is used to control high voltage output, the large voltage difference between gate and drain of an output transistor may cause a gate-induced drain leakage current (GIDL) on the output transistor. The current leakage not only causes greater power consumption but also requires greater area for the high voltage supply circuit to provide such high driving current. 
     To solve the GIDL current, U.S. Pat. No. 7,646,653 discloses a driver circuit  100  to reduce the GIDL current as shown in  FIG. 1 . The driver circuit  100  comprises a PXID driver circuit  110 , a MWL signal generating circuit  120  and an output driver circuit  130 .  FIG. 2  shows the timing diagram of the driver  100 . 
     When the driver circuit  100  is in a standby mode, the signal PXID outputted by the PXID driver circuit  110  will be an operative voltage VDD and the MWL signal generating circuit  120  will output the signal MWL of a driving voltage VPP, where the driving voltage VPP is higher than the operative voltage VDD. Since the N-type transistor N 1 A is turned on and the P-type transistor P 1 A is turned off, the voltage level of the output terminal OUT of the driver circuit  100  will be pulled down to the ground voltage VSS. In other words, with the aid of the PXID circuit  110 , the voltage difference between the terminals of the P-type transistor P 1 A may be reduced, which results in the reduction of GIDL current when the driver circuit  100  is in the standby mode of operation. 
     However, when the driver circuit  100  is activated, the signal PXID outputted by the PXID driver circuit  110  will be at the driving voltage VPP and the MWL signal generating circuit  120  will output the signal MWL of the ground voltage VSS if the address bit of the driver circuit  100  is selected. Therefore, the voltage level of the output terminal OUT of the driver circuit  100  will be pulled up to the driving voltage VPP by the P-type transistor P 1 A. However, since the gate of the N-type transistor N 1 A is at the ground voltage VSS and the drain of the N-type transistor N 1 A is at the driving voltage VPP, a significant GIDL current may be induced by the great voltage difference on the gate and drain of the N-type transistor N 1 A. 
     Namely, the driver circuit  100  taught in U.S. Pat. No. 7,646,653 can only reduce the GIDL current in the standby mode of the driver circuit  100  but cannot reduce the GIDL current in the activated mode of the driver circuit  100 . Consequently, how to reduce the GIDL current in both modes has become a critical issue to be solved. 
     SUMMARY OF THE INVENTION 
     One embodiment of the present invention discloses a level shift driver circuit. The level shift driver circuit comprises a level shift circuit and a driver circuit. The level shift circuit comprises a first system voltage terminal for receiving a driving voltage, a second system voltage terminal for receiving a system base voltage, a first input terminal for receiving a first input signal, a second input terminal for receiving a second input signal, and a first output terminal. The second input signal is an inverse signal of the first input signal. The first driver circuit comprises a first P-type transistor, a second P-type transistor, a first N-type transistor, and a second N-type transistor. The first P-type transistor has a first terminal coupled to the first system voltage terminal, a second terminal, and a control terminal coupled to the first output terminal. The second P-type transistor has a first terminal coupled to the second terminal of the first P-type transistor, a second terminal, and a control terminal. The first N-type transistor has a first terminal coupled to the second terminal of the second P-type transistor, a second terminal, and a control terminal for receiving an operational high voltage. The second N-type transistor has a first terminal coupled to the second terminal of the first N-type transistor, a second terminal coupled to the second system voltage terminal, and a control terminal coupled to the first output terminal. When the first input signal is at the operational high voltage, a voltage level of the first output terminal is at the system base voltage. When the first input signal is at the system base voltage, the voltage level of the first output terminal is at the driving voltage. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a driver circuit according to a prior art. 
         FIG. 2  shows the timing diagram of the driver circuit in  FIG. 1 . 
         FIG. 3  shows a level shift driver circuit according to one embodiment of the present invention. 
         FIG. 4  shows the timing diagram of the level shift driver circuit in  FIG. 3 . 
         FIG. 5  shows a level shift driver circuit according to another embodiment of the present invention. 
         FIG. 6  shows a level shift driver circuit according to another embodiment of the present invention. 
         FIG. 7  shows a level shift driver circuit according to another embodiment of the present invention. 
         FIG. 8  shows the timing diagram of the level shift driver circuit in  FIG. 7 . 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 3  shows a level shift driver circuit  200  according to one embodiment of the present invention. The level shift driver circuit  200  comprises a level shift circuit  210  and a driver circuit  220 . 
     The level shift circuit  210  comprises a first system voltage terminal SI 1 , a second system voltage terminal SI 2 , a first input terminal IN, a second input terminal ZIN and a first output terminal O 1 . The first system voltage terminal SI 1  can receive a driving voltage VPP. In some embodiments of the present invention, the level shift driver circuit  200  may further comprise a voltage pumping circuit for generating the driving voltage VPP. In some other embodiments of the present invention, the driving voltage VPP can be generated by an external circuit. The second system voltage terminal SI 2  can receive a system base voltage VSS. In some embodiments of the present invention the system base voltage VSS can be lower than the driving voltage VPP and can be the ground voltage of a system comprising the level shift driver circuit  200 . The first input terminal IN can receive a first input signal S IN . The second input terminal ZIN can receive a second input signal S ZIN . In some embodiments of the present invention, the second input signal S ZIN  is an inverse signal of the first input signal S IN . 
     In some embodiments of the present invention, the driver circuit  220  comprises a P-type transistor P 2 A, a P-type transistor P 2 B, an N-type transistor N 2 A and an N-type transistor N 2 B. The P-type transistor P 2 A has a first terminal coupled to the first system voltage terminal SI 1 , a second terminal D p2A , and a control terminal G p2A  coupled to the first output terminal O 1 . The P-type transistor P 2 B has a first terminal coupled to the second terminal D p2A  of the P-type transistor P 2 A, a second terminal D p2B , and a control terminal G p2B . The N-type transistor N 2 A has a first terminal DN 2 A coupled to the second terminal Dp 2 B of the P-type transistor P 2 B, a second terminal, and a control terminal G N2A  for receiving an operative voltage VDD. The N-type transistor N 2 B has a first terminal D N2B  coupled to the second terminal of the N-type transistor N 2 A, a second terminal coupled to the second system voltage terminal SI 2 , and a control terminal G N2B  coupled to the first output terminal O 1 . In some embodiments of the preset invention, the driving voltage VPP is greater than the operative voltage VDD, for example, but not limited to, the driving voltage VPP can be 2 to 3 times the operative voltage VDD. In  FIG. 3 , the second terminal D P2B  of the P-type transistor P 2 B is also used as the driver output terminal OUT of the level shift driver circuit  200 . 
     In some embodiments of the present invention, the level shift circuit  210  comprises a P-type transistor P 2 C, a P-type transistor P 2 D, an N-type transistor N 2 C, and an N-type transistor N 2 D. The P-type transistor P 2 C has a first terminal coupled to the first system voltage terminal SI 1 , a second terminal coupled to the first output terminal O 1 , and a control terminal. The P-type transistor P 2 D has a first terminal coupled to the first system voltage terminal SI 1 , a second terminal coupled to the control terminal of the P-type transistor P 2 C, and a control terminal coupled to the first output terminal O 1 . The N-type transistor N 2 C has a first terminal coupled to the first output terminal O 1 , a second terminal coupled to the second system voltage terminal SI 2 , and a control terminal coupled to the first input terminal IN. The N-type transistor N 2 D has a first terminal coupled to the second terminal of the P-type transistor P 2 D, a second terminal coupled to the second system voltage terminal SI 2 , and a control terminal coupled to the second input terminal ZIN. However, the level shift circuit  210  is not limited to the structure shown in  FIG. 3 , different kinds of level shift circuits may also be used to switch the voltage level of the first output terminal O 1  according to the first input signal S IN  and the second input signal S ZIN  as long as a voltage level of the first output terminal O 1  is at the system base voltage VSS when the first input signal S IN  is at the operative voltage VDD, and the voltage level of the first output terminal O 1  is at the driving voltage VPP when the first input signal S IN  is at the system base voltage VSS. 
       FIG. 4  shows a timing diagram of the level shift driver  200  according to one embodiment of the present invention. In  FIG. 4 , during the period of T 1 , the first input signal S IN  is at the operative voltage VDD, the second input signal S ZIN  is at the system base voltage VSS. Therefore, the N-type transistor N 2 C is turned on and the voltage level of the first output terminal O 1  is at the system base voltage VSS. The P-type transistor P 2 A is turned on. In  FIG. 4 , the control terminal G P2B  of the P-type transistor P 2 B can receive the operative voltage VDD. Since the driving voltage VPP is higher than the operative voltage VDD, the P-type transistor P 2 B is also turned on and the voltage level of the driver output terminal OUT is pulled up to the driving voltage VPP. In addition, the N-type transistor N 2 B is turned off. Since the voltage level of the control terminal G N2A  of the N-type transistor N 2 A is at the operative voltage VDD, the voltage level of the control terminal G N2A  of the N-type transistor N 2 A may be higher than the voltage level of the second terminal of the N-type transistor N 2 A, that is the first terminal D N2B  of the N-type transistor N 2 B, due to the previous operations. Thus, the N-type transistor N 2 A may be turned on in the beginning of the period of T 1 . However, the N-type transistor N 2 A will finally be turned off in the end of period of T 1  when the voltage level of the first terminal D N2B  of the N-type transistor N 2 B is pulled up to the operative voltage VDD minus the threshold voltage V thN2A  of the N-type transistor N 2 A, namely VDD−V thN2A , by the P-type transistors P 2 A and P 2 B. Consequently, the voltage difference between the control terminal G N2A  and the first terminal D N2A  of the N-type transistor N 2 A is equal to VPP−VDD, which is less than VPP—VSS as in the prior art. Namely, the GIDL current caused on the N-type transistor N 2 A is reduced. In addition, the voltage difference between the control terminal G N2B  and the first terminal D N2B  of the N-type transistor N 2 B is equal to VDD−V thN2A −VSS, which is also less than VPP−VSS. Therefore, both GIDL currents on the N-type transistors N 2 A and N 2 B are reduced significantly when the level shift driver circuit  200  is in an activated mode, that is, when the voltage level of the driver output terminal OUT is at the driving voltage VPP. 
     In  FIG. 4 , during the period of T 2 , the first input signal S IN  is at the system base voltage VSS, the second input signal S ZIN  is at the operative voltage VDD. Therefore, the N-type transistor N 2 D is turned on and the P-type transistor P 2 C is also turned on so the voltage level of the first output terminal O 1  is pulled up to the driving voltage VPP. The N-type transistor N 2 B is turned on and the N-type transistor N 2 A is also turned on. The voltage level of the driver terminal OUT is pulled down to the system base voltage VSS. The P-type transistor P 2 A is turned off. Since the voltage level of the first terminal of the P-type transistor P 2 B, or the second terminal D P2A  of the P-type transistor P 2 A, may still at the driving voltage VPP according to the operation in the period of T 1 . Thus, the P-type transistor P 2 B may be turned on in the beginning of the period of T 2 . However, the P-type transistor P 2 B will finally be turned off when the voltage level of the first terminal of the P-type transistor P 2 B, or the second terminal D P2A  of the P-type transistor P 2 A, is pulled down to VDD+V thp2B  by the N-type transistors N 2 A and N 2 B, where V thp2B  denotes for the threshold voltage of the P-type transistor P 2 B. Consequently, the voltage difference between the control terminal G P2A  and the second terminal D P2A  of the P-type transistor P 2 A is equal to VPP−(VDD+V thp2B ), which is less than VPP−VSS, so the GIDL current caused on the P-type transistor P 2 A is reduced. In addition, the voltage difference between the control terminal G P2B  and the second terminal D P2B  of the P-type transistor P 2 B is equal to VDD−VSS, which is also less than VPP−VSS. Namely, both GIDL currents on the P-type transistors P 2 A and P 2 B are reduced significantly when the level shift driver circuit  200  is in a standby mode, that is, when the voltage level of the driver output terminal OUT is at the system base voltage VSS. 
     In another embodiment of the present invention, the control terminal G P2B  of the P-type transistor P 2 B can be coupled to the second input terminal S ZIN . In this case, during the period of T 1 , the P-type transistor P 2 B can be fully turned on since the second input signal S ZIN  is at the system base voltage VSS. Also, during the period of T 2 , the second input signal S ZIN  is at the operative voltage VDD so the operations of the P-type transistor P 2 B is the same as the aforesaid operations. 
     Consequently, the level shift driver circuit  200  is able to reduce the GIDL currents on the P-type transistors P 2 A and P 2 B during the period of T 2 , that is, the standby mode of the level shift driver circuit  200 . Also, the driver circuit  200  is able to reduce the GIDL currents on the N-type transistors N 2 A and N 2 B during the period of T 1 , that is, the activated mode of the level shift driver circuit  200 . 
     In some embodiments of the present invention, widths of the P-type transistor P 2 A and the P-type transistor P 2 B can be greater than widths of the P-type transistor P 2 C and the P-type transistor P 2 D because the level shift circuit  210  is used to output control signals and does not require large driving current while the driver circuit  220  is used to output larger driving current with high voltage for the system loads. Similarly, widths of the N-type transistor N 2 A and the N-type transistor N 2 B can be greater than widths of the N-type transistor N 2 C and the N-type transistor N 2 D. 
     Furthermore, lengths of the P-type transistor P 2 A and the P-type transistor P 2 B can be shorter than lengths of the P-type transistor P 2 C and the P-type transistor P 2 D so that the circuit area can be reduced. Similarly, lengths of the N-type transistor N 2 A and the N-type transistor N 2 B can be shorter than lengths of the N-type transistor N 2 C and the N-type transistor N 2 D. 
       FIG. 5  shows a level shift driver circuit  400  according to another embodiment of the present invention. The level shift driver circuit  400  is similar to the level shift driver circuit  200 . The difference between the level shift driver circuit  200  and  400  is that the level shift driver circuit  400  comprises the driver circuit  220 , a level shift circuit  410  and a driver circuit  430 . The level shift circuit  410  is very similar to the level shift circuit  210 , but the only difference between these two is that the level shift circuit  410  further comprises a second output terminal O 2  coupled to the second terminal of the P-type transistor P 2 D. The driver circuit  430  comprises a P-type transistor P 4 E, and an N-type transistor N 4 E. 
     The P-type transistor P 4 E has a first terminal coupled to the first system voltage terminal VPP, a second terminal, and a control terminal coupled to the second output terminal O 2 . The N-type transistor N 4 E has a first terminal coupled to the second terminal of the P-type transistor P 4 E, a second terminal coupled to the second system voltage terminal VSS, and a control terminal coupled to the second output terminal O 2 . The second terminal of the P-type transistor P 4 E can be used as a driver output terminal ZOUT of the level shift driver circuit  400 . 
     Since the structure of the driver circuit  430  and the driver circuit  220  are similar but with inverse input signals, the driver circuit  430  can be operated as a complemented counterpart of the driver circuit  220 . Namely, when the voltage level of the driver output terminal OUT is at the driving voltage VPP, the voltage level of the driver output terminal ZOUT will be at the system base voltage VSS, and when the voltage level of the driver output terminal OUT is at the system base voltage VSS, the voltage level of the driver output terminal ZOUT will be at the driving voltage VPP. 
     However, when the voltage level of the output terminal O 2  is at the driving voltage VPP and the voltage level of the driver output terminal ZOUT is at the system base voltage VSS, the P-type transistor P 4 E can suffer a big GIDL current due to the great voltage difference between the control terminal and the second terminal of the P-type transistor P 4 E. Similarly, when the voltage level of the output terminal O 2  is at the system base voltage VSS and the voltage level of the driver output terminal ZOUT is at the driving voltage VPP, the N-type transistor N 4 E can suffer a big GIDL current due to the great voltage difference between the control terminal and the first terminal of the N-type transistor N 4 E. 
     The GIDL currents occur on the driver circuit  430  can also be reduced by using the similar structure of the driver circuit  220 .  FIG. 6  shows a level shift driver circuit  500  according to another embodiment of the present invention. The level shift driver circuit  500  is similar to the level shift driver circuit  400 . The difference between the level shift driver circuit  500  and  400  is that the level shift driver circuit  500  comprises a driver circuit  530 , instead of the driver circuit  430 . The driver circuit  530  comprises a P-type transistor P 5 E, a P-type transistor P 5 F, an N-type transistor N 5 E, and an N-type transistor N 5 F. 
     The P-type transistor P 5 E has a first terminal coupled to the first system voltage terminal SI 1 , a second terminal, and a control terminal coupled to the second output terminal O 2 . The P-type transistor P 5 F has a first terminal coupled to the second terminal of the P-type transistor P 5 E, a second terminal, and a control terminal coupled to the first input terminal S IN  or for receiving the operative voltage VDD. The N-type transistor N 5 E has a first terminal coupled to the second terminal of the P-type transistor P 5 F, a second terminal, and a control terminal for receiving the operative voltage VDD. The N-type transistor N 5 F has a first terminal coupled to the second terminal of the N-type transistor N 5 E, a second terminal coupled to the second system voltage terminal SI 2 , and a control terminal coupled to the second output terminal O 2 . 
     Since the structure of the driver circuit  530  and the driver circuit  220  are the same but with inverse input signals, the P-type transistor P 5 E, the P-type transistor P 5 F, the N-type transistor N 5 E, and the N-type transistor N 5 F can be operated as a complemented counterpart of the P-type transistor P 2 A, the P-type transistor P 2 B, the N-type transistor N 2 A, and the N-type transistor N 2 B respectively. 
     Furthermore, since the driver circuit  530  has the same structure as the driver circuit  220 , the driver circuit  530  can be operated with the same principle as the driver circuit  220  and the GIDL currents on the driver circuit  530  can be reduced significantly. 
       FIG. 7  shows a level shift driver circuit  600  according to another embodiment of the present invention. The level shift driver circuit  600  is similar to the level shift driver circuit  200 . The difference between the level shift driver circuit  200  and  600  is that the level shift driver circuit  600  comprises a driver circuit  620 . The driver circuit  620  is similar to the driver circuit  220 , but the driver circuit  620  further comprises P-type transistors P 6 A, P 6 B, and P 6 C. The P-type transistors P 6 A and P 6 B can be corresponding to the P-type transistors P 2 A and P 2 B in the driver circuit  220  while the P-type transistor P 6 C is coupled in series between the P-type transistor P 6 A and P 6 B. 
     In some embodiments of the present invention, the voltage levels V P6C  of a control terminal of the P-type transistor P 6 C is between the driving voltage VPP and the voltage level of the control terminal of the P-type transistor P 6 B. For example, if the driving voltage VPP is three times the operative voltage VDD and the voltage level of the control terminal of the P-type transistor P 6 B is at the operative voltage VDD, then the voltage level V P6C  can be two times the operational voltage VDD (i.e. V P6C =2XVDD). 
       FIG. 8  shows a timing diagram of the level shift driver  600  according to one embodiment of the present invention. In  FIG. 8 , during the period of T 1 , the first input signal S IN  is at the operative voltage VDD, the second input signal S ZIN  is at the system base voltage VSS. Therefore, the voltage level of the first output terminal O 1  is at the system base voltage VSS. The P-type transistor P 6 A is turned on. Since the driving voltage VPP is three times the operative voltage VDD, the P-type transistor P 6 B and the P-type transistor P 6 C are also turned on and the voltage level of the driver output terminal OUT is pulled up to the driving voltage VPP. 
     During the period of T 2 , the first input signal S IN  is at the system base voltage VSS, the second input signal S ZIN  is at the operative voltage VDD. Therefore, the voltage level of the first output terminal O 1  is pulled up to the driving voltage VPP. The P-type transistor P 6 A is turned off. The N-type transistors are turned on so the driver output terminal OUT is at the system base voltage VSS. Since the voltage level of the first terminals of the P-type transistor P 6 C and P 6 B (the second terminals D P6A  and D P6C  of the P-type transistors P 6 A and P 6 C), may still at the driving voltage VPP according to the operation in the period of T 1 , the P-type transistors P 6 B and P 6 C may be turned on in the beginning of the period of T 2 . However, the P-type transistor P 6 C will finally be turned off when the voltage level of the first terminal of the P-type transistor P 6 C (the second terminal D P6A  of the P-type transistor P 6 A) is pulled down to 2VDD+V thP6C  by the N-type transistors of the driver circuit  620 , where V thP6C  denotes for the threshold voltage of the P-type transistor P 6 C. Also, the P-type transistor P 6 B will finally be turned off when the voltage level of the first terminal of the P-type transistor P 6 B (the second terminal D P6C  of the P-type transistor P 6 C) is pulled down to VDD+V thP6B  by the N-type transistors of the driver circuit  620 . 
     Consequently, the voltage difference between the control terminal G P6A  and the second terminal D P6A  of the P-type transistor P 6 A is equal to VPP−(2VDD+V thP6C ), which is even less than the voltage difference between the control terminal G P2A  and the second terminal D P2A  of the P-type transistor P 2 A as in the driver circuit  220 . Therefore, the GIDL current caused on the P-type transistor P 6 A is further reduced. Similarly, the GIDL currents caused on the P-type transistor P 6 C and the P-type transistor P 6 B can also be further reduced due to the intermediate voltage supplied to the control terminal of the P-type transistor P 6 C. 
     In some embodiments of the present invention, the control terminal of the P-type transistor P 6 B and the control terminal of the P-type transistor P 6 C can also receive the system base voltage VSS during the period of T 1  in  FIG. 7 . In this case, the P-type transistors P 6 B and P 6 C can be fully turned on when the level shift circuit  600  is activated. 
     In some embodiments of the present invention, the driver circuit  600  can comprise N-type transistors N 6 A N 6 B, and N 6 C. The N-type transistors N 6 A and N 6 B can be corresponding to the N-type transistors N 2 A and N 2 B while the N-type transistor N 6 C is coupled in series between the P-type transistor P 6 B and the N-type transistor N 6 A. 
     In some embodiments of the present invention, the voltage levels V N6C  of a control terminal of the N-type transistor N 6 C is between the driving voltage VPP and the operative voltage VDD. For example, if the driving voltage VPP is three times the operative voltage VDD, then the voltage level V N6C  can be two times the operational voltage VDD (i.e. V N6C =2XVDD). 
     In  FIG. 8 , during the period of T 1 , the voltage level of the first output terminal O 1  is at the system base voltage VSS. The N-type transistor NEB is turned off. Since the voltage level of the second terminals of the N-type transistors NEA and NEC may still at the system base voltage VSS according to the previous operations, the N-type transistors N 6 B and NEC may be turned on in the beginning of the period of T 1 . However, the N-type transistor N 6 A will finally be turned off when the voltage level of the second terminal of the N-type transistor N 6 A (the first terminal D N6B  of the N-type transistor N 6 B) is pulled up to VDD−V thN6A  by the P-type transistors of the driver circuit  620 . Also, the N-type transistor NEC will finally be turned off when the voltage level of the second terminal of the N-type transistor NEC (the first terminal D N6A  of the N-type transistor NEA) is pulled up to 2VDD−V thN6C  by the P-type transistors of the driver circuit  620 , where V thN6C  denotes for the threshold voltage of the N-type transistor NEC. 
     Consequently, the voltage difference between the control terminal G N6A  and the first terminal D N6A  of the N-type transistor NEA is equal to 2VDD−V thN6C −VDD, namely VDD−V thN6C , which is even less than the voltage difference between the control terminal G N2A  and the first terminal D N2A  of the N-type transistor N 2 A as in the driver circuit  220 . Therefore, the GIDL current caused on the N-type transistor N 2 A is further reduced. Similarly, the GIDL currents caused on the N-type transistor NEB can also be further reduced due to the intermediate voltage supplied to the control terminal of the N-type transistor NEC. 
     During the period of T 2 , the voltage level of the first output terminal O 1  is pulled up to the driving voltage VPP. The N-type transistors NEA, NEB, and NEC are turned on so the voltage level of the driver output terminal OUT is at the system base voltage VSS. 
     Consequently, the level shift driver circuit  600  is able to reduce the GIDL currents on the P-type transistors PEA, P 6 B and PEC during the period of T 2 , that is, the standby mode of the level shift driver circuit  600 . Also, the driver circuit  600  is able to reduce the GIDL currents on the N-type transistors NEA, NEB, and NEC during the period of T 1 , that is, the activated mode of the level shift driver circuit  600 . 
     Although in  FIG. 7 , the driver circuit  620  only comprises three P-type transistors and three N-type transistors, it is not to limit the present invention. In other embodiments of the present invention, the driver circuit  620  can also comprise other numbers of P-type transistors and N-type transistors according to the system needs. 
     In summary, according to the shift level driver circuits provided by the embodiments of the present invention, the GIDL currents on the transistors of the driver circuit can be reduced both when the level shift driver circuit is in the activated mode or the standby mode and the power consumption can be reduced. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.