Abstract:
A control circuit is described in which a single input terminal receives digital control signals and analog control signals. A circuit coupled to the single input provides a first output to indicate that a signal at said single input terminal is a digital signal and a second output indicates that a signal at said single input terminal is an analog signal.

Description:
RELATED APPLICATIONS  
       [0001]     This application claims priority of U.S. Provisional Patent Application Ser. No. 60/613,737 filed Sep. 27, 2004 and is a continuation of U.S. patent application Ser. No. 10/985,784 filed Nov. 10, 2004. 
     
    
     FIELD OF THE INVENTION  
       [0002]     The invention pertains to a circuit arrangement that is responsive to analog and digital signals received at a common terminal, in general, and to a control arrangement for a brushless direct current motor, in particular.  
       SUMMARY OF THE INVENTION  
       [0003]     A control circuit is described in which a single input terminal receives digital control signals and analog control signals. A circuit coupled to the single input provides a first output to indicate that a signal at said single input terminal is a digital signal and a second output indicates that a signal at said single input terminal is an analog signal.  
         [0004]     In accordance with the principles of the invention, a monolithic brushless DC motor controller is provided that contains all of the required functions for implementing fan speed control. The motor controller contains a pulse width modulator (PWM) consisting of a fixed frequency oscillator, comparator and a latch for speed control, commutation logic for proper drive sequencing, on-chip power MOSFETs for direct motor drive, cycle-by-cycle current limiting, programmable fault timer with time delayed restart, and a power down low current mode.  
         [0005]     In accordance with one aspect of the invention a control circuit has a single input terminal for receiving digital signals and analog control signals. The digital signals being in a first digital state when below a first level, and being in a second digital state when above a second level. The analog signals are within a range that is greater than said first level and less than said second level. The control circuit includes a comparator circuit coupled to the single input terminal for providing a first output when the level at the single input terminal is below said first level or when the level at the single input terminal is above the second level. The comparator circuit provides a second output when the level at the single input terminal is between the first level and the second level. The first output indicates that a signal at the single input terminal is a digital signal and the second output indicates that a signal at the single input terminal is an analog signal.  
         [0006]     In accordance with one aspect of the invention the comparator circuit comprises a first comparator operable to determine if the level at the single input terminal is below the first level and a second comparator operable to determine if the level at the single input terminal is above the second level.  
         [0007]     A logic element coupled to the first comparator and to the second comparator provides an output indicative of whether the signal at the single input terminal is a digital signal or an analog signal.  
         [0008]     In a method of operating a control circuit in accordance with the invention, signals are received at a single input terminal that may be digital signals and analog control signals. The method includes the steps of determining whether the level of a signal at the single input terminal is below a first level and determining whether the level of the signal at the single input terminal is above the second level. Steps of providing a first output if the level is below the first level or if the level is above the second level; and providing a second output if the level is between the first level and the second level; whereby the first output indicates that a signal at the single input terminal is a digital signal and the second output indicates that a signal at the single input terminal is an analog signal.  
         [0009]     A control circuit in accordance with the principles of the invention has a single input terminal for receiving digital signals and analog control signals. The digital signals are in a first digital state when below a first level, and are in a second digital state when above a second level. The analog signals are within a range that is greater than the first level and less than the second level. A comparator circuit coupled to the single input terminal provides a first output when the level at the single input terminal is below the first level or when the level at the single input terminal is above the second level. The comparator circuit provides a second output when the level at the single input terminal is between the first level and the second level. An oscillator provides a pulse waveform at a first output and a saw tooth waveform at a second output. A pulse width modulated comparator has a first input coupled to the single input terminal and a second input coupled to the oscillator second output and has an output. A circuit is coupled to the comparator, the oscillator first output and to the pulse width modulated comparator output. The circuit is operable to generate pulse width modulated control signals in response to digital input signals at the single input terminal and in response to analog input signals at the single input terminal.  
         [0010]     In accordance with the principles of the invention the comparator circuit comprises a first comparator operable to determine if the level at the single input terminal is below the first level; and a second comparator operable to determine if the level at the single input terminal is above the second level.  
         [0011]     In the illustrative embodiment of the invention a logic element is coupled to the first comparator and to the second comparator to provide an output indicative of whether the signal at the single input terminal is a digital signal or an analog signal.  
         [0012]     Still further in accordance with the principles of the invention, a method of providing control signals, comprises: providing a single input terminal and receiving digital signals at the input terminal. The digital signals are in a first digital state when below a first level, and are in a second digital state when above a second level. The method includes receiving analog signals at the input terminal. The analog signals are within a range that is greater than the first level and less than the second level. The method includes comparing signal levels at the input terminal to the first and the second levels; providing a first output when the level at the input terminal is below the first level or when the level at the input terminal is above the second level; providing a second output when the level at the input terminal is between the first level and the second level; and generating pulse width modulated control signals in response to digital input signals at the single input terminal and in response to analog input signals at the single input terminal.  
         [0013]     In the illustrative embodiment of the invention, the method includes providing an oscillator. The oscillator provides a pulse waveform at a first output and as saw tooth waveform at a second output. The method further includes providing a pulse width modulated comparator having a first input coupled to the single input terminal and a second input coupled to the oscillator second output and having an output; and providing a circuit coupled to the comparator, said oscillator first output and to said pulse width modulated comparator output to generate said pulse width modulated control signals when an analog signal is at said single input terminal.  
         [0014]     In the illustrative embodiment of the invention the method includes providing a latch operable in conjunction with the oscillator and said pulse width comparator to generate the pulse width modulated control signals.  
         [0015]     A motor controller for a brushless direct current motor in accordance with the principles of the invention includes an input terminal for receiving an analog control signal and a digital control signal; and a control circuit coupled to the single input terminal. The control circuit is responsive to digital input signals and analog input signals at the single input terminal to provide pulse width modulated control signals. A motor drive circuit is controlled by the control circuit and is coupleable to a brushless direct current motor for energizing the motor.  
         [0016]     In accordance with the principles of the invention the motor controller is formed on a single integrated circuit.  
         [0017]     In the illustrative embodiment of the invention the motor drive circuit comprises MOSFETs.  
         [0018]     In accordance with yet another aspect of the invention a current comparator is coupled to the motor drive circuit for effecting pulse width modulation control signals on a cycle-by-cycle basis. 
     
    
     BRIEF DESCRIPTION OF THE DRAWING  
       [0019]     The invention will be better understood from a reading of the following detailed description of the drawing in which like reference designators are used to identify like elements in the various drawing figures, and in which;  
         [0020]      FIG. 1  is a representation of a device in accordance with the principles of the invention:  
         [0021]      FIG. 2  illustrates the device of  FIG. 1  connected to a cooling fan;  
         [0022]      FIG. 3  is a detailed block diagram of the device of  FIG. 1 ;  
         [0023]      FIG. 4  illustrates input waveforms to the device of  FIG. 1 ; and  
         [0024]      FIGS. 5 and 6  illustrates detailed waveforms. 
     
    
     DETAILED DESCRIPTION  
       [0025]     The illustrative embodiment of the invention is a monolithic brushless DC motor controller  100  that provides functions for implementing fan speed control. As shown in  FIG. 1 , the invention may be implemented in one configuration as an eight pin package.  
         [0026]     Controller  100  may be provided in SOP-8 and MSOP-8 surface mount packages. In other embodiments of the invention controller  100  may be integrated onto the same silicon as the device being cooled by fan  200 .  
         [0027]     Turning now to  FIG. 2 , controller  100  for speed control of motor  200  includes a pulse width modulator logic or PWM circuit  101 , commutation logic for proper drive sequencing  103 , direct motor drive  105 , current limiter  107 , and a programmable fault timer with time delayed restart and a power down low current mode block  109 .  
         [0028]     Controller  100 , fully integrated on a single chip  102  contains all required functions for implementing fan speed control. As shown in  FIG. 3 , pulse width modulator (PWM)  101  comprising a fixed frequency oscillator  301 , comparator  303 , and a latch  305  along with associated gates for motor speed control of motor  200 . Controller  100  also includes commutation logic  103  for proper drive sequencing, on-chip power MOSFETs  313 ,  315  for direct motor drive, cycle-by-cycle current limiting circuit  317 , and a circuit block  319  providing a programmable fault timer with time delayed restart, and a power down low current mode.  
         [0029]     Motor  200  includes rotor  201  and stator windings  203 ,  205 . A rotator position sensor  207  is provided with motor  200 . In a typical motor fan arrangement, a Hall effect device sensor is utilized is utilized as sensor  207 . Motor  200  includes connections  01 ,  02 , a sensor output HALL and power connections.  
         [0030]     Controller  100  utilizes pulse width modulation to provide an energy efficient means for controlling the motor speed of fan motor  200  by varying the average applied voltage to each stator winding  203 ,  205  during the commutation sequence.  
         [0031]     PWM circuit  101  as noted above includes oscillator  301 , comparator  303 , and latch  305 . Oscillator  301  provides both pulse and saw tooth outputs. PWM circuit  101  is responsive to either an analog or a digital signal on the same input terminal PWM Input.  
         [0032]      FIG. 4  illustrates the analog input signal range  401  and a digital input signal range  405  that PWM logic  101  is responsive to in the illustrative embodiment are shown.  
         [0033]     PWM circuit  101  includes a sub-circuit comprising level comparators  331 ,  333  and a NOR gate  348  that is used to determine whether the control signal at terminal PWM Input is a digital control signal. If the control signal is not digital, it is assumed to be analog.  
         [0034]     Comparator  331  has an input coupled to terminal PWM Input and compares the voltage at PWM Input against a reference that corresponds to the minimum logic high level. In this embodiment, the minimum logic high voltage level is 2.5 volts. Comparator  331  generates a logic 1 or high output if the voltage at PWM Input exceeds 2.5 volts.  
         [0035]     Comparator  333  has an input coupled to terminal PWM Input and compares the voltage at PWM Input against a reference that corresponds to the maximum logic low level. In this embodiment, the maximum logic low voltage level is 0.5 volts. Comparator  333  generates a logic 1 or high output if the voltage at PWM Input is less than 0.5 volts.  
         [0036]     Nor gate  348  provides a logic 0 or low output if either comparator  331  or comparator  333  indicates that the control signal is digital and provides a logic 1 or high output if neither comparator  331  or  333  indicates that the control signal is a digital signal. Operation of gates  341 - 348  is as follows: AND gate  341  has one input coupled to the square wave output of oscillator  301  and its other input coupled to the output of gate  348 . Gate  341  blocks pulses from Oscillator  301  if a digital signal is present at PWM Input.  
         [0037]     This prevents Oscillator  301  from initiating operation of Motor Drive circuit  316  via latch  305  when a digital signal is present at PWM Input.  
         [0038]     AND gate  342  has one input coupled to the output of PWM comparator  303  and its other input coupled to the output of gate  348 . Gate  342  blocks the PWM comparator output pulses if a digital signal is present at PWM Input. This prevents PWM comparator  303  from terminating operation of Motor Drive circuit  316  via latch  305  when a digital signal is present at PWM Input.  
         [0039]     Gate  343  is used to block signals to latch  305  reset input R during the time that current limiter  317  detects that the motor current exceeds a predetermined limit. This prevents PWM comparator  303  from terminating energization of motor drive circuit  316 .  
         [0040]     Gate  344  allows the pulse output from Oscillator  301  to reset latch  305  if there is no current limiting and no analog input control signal.  
         [0041]     Gate  347  is used to lockout the indication that a digital control signal at input PWM Input is in a high state during the time that current limiter circuit  317  detects that the drive current limit is exceeded.  
         [0042]     Gate  346  is utilized to reset latch  305  to initiate on-time of motor drive circuit  316 . Gate  347  sets latch  305  to terminate the on-time of motor drive circuit  316 .  
         [0043]     Operation of PWM circuit  101  in response to analog input control signals may be better understood by referring to the waveforms of  FIG. 5 . Waveform  501  is the saw tooth output waveform of Oscillator  301 . Waveform  503  is the Analog signal control at PWM Input. Waveform  505  is the output of current limit circuit  317 . Waveform  507  is the reset input R of PWM latch  305 . Waveform  509  is the output Q′ of PWM latch  305 .  
         [0044]     Analog signal input control is accomplished with Oscillator  301  initiating Motor Drive conduction and the PWM Comparator  303  terminating it. As the voltage of saw tooth output waveform  501  falls from its peak level  504  to valley level  506  (2.0 V to 1.0 V, respectively), a pulse  511  is simultaneously generated at the oscillator output  507  to reset PWM Latch  305 , thereby causing the output Q′ to attain a high level allowing conduction of a Motor Drive MOSFET  313 ,  315 . PWM Comparator  303  terminates conduction when saw tooth waveform  501  rises above the voltage level of the analog control waveform  503  applied to PWM Input. Thus, the conduction duty cycle or average voltage applied to a stator winding  203 ,  205  of fan motor  200  is directly controlled by the analog voltage at PWM Input. The conduction duty cycle increases from 0% to 100% as illustrated by waveform  509  as PWM Input voltage increases from 1.0 V to 2.0 V, respectively.  
         [0045]     Operation of PWM logic  101  in response to digital control signals at PWM Input may be better understood by referring to the waveforms of  FIG. 6 . Waveform  603  is a representative waveform of an input digital signal control at PWM Input. Waveform  505  is the output of current limit comparator  317 . Waveform  507  is the reset input R of PWM latch  305 . Waveform  509  is the output Q′ of PWM latch  305 .  
         [0046]     Digital control is accomplished by applying a digital signal of the desired conduction duty cycle to the PWM Input. As shown in  FIG. 4 , the low VIL and high VIH states for the digital input encompass the internal saw tooth peak and valley levels. In the illustrative embodiment, saw tooth levels are chosen such that a maximum 0.5 V low state and a minimum 2.5 V high state digital signal is utilized. These levels are easily achievable by 3.0 V logic circuitry.  
         [0047]     Latch  305  when reset, initiates conduction of a Motor Drive MOSFET  313 ,  315 . Latch  305  when set, terminates conduction of Motor Drive MOSFETs  313 ,  315 . Thus, the conduction duty cycle is directly controlled by the signal duty cycle present at the PWM Input as long as the signal magnitude is above and below the window detector thresholds provided by comparators  331 ,  333 .  
         [0048]     Commutation logic  103  includes a rotor position decoder coupled to HALL input to monitor which in turn is connectable to Hall sensor  207 . Rotor position decoder provides proper sequencing of the Phase 1, φ1, and Phase 2, φ2 drive outputs. Hall input is designed to interface directly with an open collector type Hall Effect switch. An internal pull-up is provided to minimize to number of external components. The Commutation Logic provides an output signal for monitoring the motor speed at output Tach.  
         [0049]     Direct motor drive is accomplished by providing two on-chip open drain N-channel MOSFETs  313 ,  315 , each having a high breakdown voltage. The respective MOSFET  313 ,  315  drains are pinned out to output terminals φ1, φ2 for direct connection to motor windings  203 ,  205 . Zener and series diodes  314 ,  314   a  are connected from each respective MOSFET drain to gate to protect the MOSFETs  313 ,  315  from excessive inductive voltage spikes.  
         [0050]     Current limit comparator  317  monitors the voltage drop that appears across a sense resistor  318 . If motor  201  becomes overloaded or stalls, the threshold level of current limit circuit  317  will be exceeded causing PWM Latch  305  to set. This terminates conduction of the Motor Drive MOSFETs  313 ,  315  on an oscillator cycle-by-cycle basis.  
         [0051]     The Fault Timer  109  is controlled by the value of the external capacitor  110 . A current source included in fault timer  109  is used to charge capacitor  110 .  
         [0052]     The Fault Time mode is initiated when the current limit circuit  317  is activated. If an over current situation persists for an extended time period, the Fault Timer will gradually discharge the external timing capacitor to a voltage level that will cause the motor to stop and then initiate a restart sequence.  
         [0053]     The Power Down mode is initiated by clamping external capacitor  110  to a voltage of 100 mV or less. The drain current for the entirety of integrated circuit  102  will be reduced to less than 10 uA.  
         [0054]     Controller  100  advantageously provides the following features:  
         [0055]     Interfaces directly with aSC7512 thermal controller;  
         [0056]     Analog and digital PWM control signal compatibility;  
         [0057]     Motor fault timeout with auto start retry;  
         [0058]     Fan tachometer output for closed loop speed control;  
         [0059]     Latching PWM for enhanced noise immunity;  
         [0060]     Cycle-by-cycle current limit protection;  
         [0061]     On-chip 500 mA motor drivers;  
         [0062]     Low current power down mode;  
         [0063]     Minimum number of external components; and  
         [0064]     8-lead SOIC or MSOP package  
         [0065]     Controller  100  has many applications, including:  
         [0066]     Personal and notebook computers fans;  
         [0067]     Workstation and mainframe fans;  
         [0068]     LAN server blowers;  
         [0069]     Industrial control system fans;  
         [0070]     Telcom system fans;  
         [0071]     Instrumentation test and measurement fans; and  
         [0072]     Card rack fans.  
         [0073]     The invention has been described in conjunction with a specific illustrative embodiment. It will be understood by those skilled in the art that various changes, substitutions and modifications may be made without departing from the spirit or scope of the invention. It is intended that all such changes, substitutions and modifications be included in the scope of the invention. It is not intended that the invention be limited to the illustrative embodiment shown and described herein. It is intended that the invention be limited only by the claims appended hereto, giving the claims the broadest possible scope and coverage permitted under the law.