Abstract:
An interference tolerant capacitive touch sensor readout circuit having improved power and area efficiency is disclosed. Interference rejection for the capacitive touch sensing system is realized by transferring charge between a capacitive touch sensor and the readout circuit at frequencies outside bands where a level of interference is unacceptable. Improved power and area efficient come from the simplicity of the readout circuit which comprises a switched-capacitor integrator, a comparator, a digital accumulator and number of switches for driving a touch sensor and a capacitive feedback loop. The readout circuit is capable of interfacing with both self and mutual capacitance sensor to achieve compatibility with a larger collection of sensors and provides additional sensing and diagnostic functionalities.

Description:
REFERENCE TO RELATED APPLICATION 
       [0001]    The present U.S. Utility patent application claims priority pursuant to 35 U.S.C. §119(e) to the following U.S. Provisional Patent Application which is hereby incorporated herein by reference in its entirety and made part of the present U.S. Utility patent application for all purposes: 
         [0002]    1. U.S. Provisional Application Ser. No. 61/739,774 entitled “Capacitive Touch Sensing System With Interference Rejection,” (Attorney Docket No. BP31483) filed Dec. 20, 2012, pending. 
     
    
     BACKGROUND OF THE INVENTION 
       [0003]    1. Technical Field of the Invention 
         [0004]    This technology described herein relates generally to capacitive touch sensors and more particularly to circuits used to support capacitive touch sensors. 
         [0005]    2. Description of Related Art 
         [0006]    Various methods exist for detecting user interactions with a touch screen. Many of these utilize sensors whose electrical properties change when touched. Capacitive touch screens employ capacitive sensors for touch detection. Touching the screen in a specific area changes the amount of capacitance at that location which the system detects and after processing extracts as a user input. 
         [0007]    Generally, capacitive touch sensors are capacitors with loosely confined electric fields purposely projected in ways that make their capacitance sensitive to touch. As a finger approaches a capacitive touch sensor, it intersects with the projected electric field lines causing the sensor capacitance to change. The amount of capacitance change depends on the quantity of field lines crossed. Therefore, the closer a finger is to a touch sensor the greater the changes in the sensor capacitance. 
         [0008]    Usually, touch sensing is performed using either self or mutual capacitance sensors. In self-capacitance, the capacitive sensor is formed between a relatively small conductive layer and the much bigger sensor ground plane. In mutual capacitance, the capacitive sensor is formed between two conductive layers typically similar in size and neither assigned to any fixed voltages. Unlike self-capacitive sensors where only one electrode is accessible (i.e., available to make connection to other circuit elements), in mutual capacitive sensors both electrodes are accessible. 
         [0009]    Often, touch sensing systems are designed to interface with either self or mutual capacitive sensors. Systems having the capability to sense both mutual and self-capacitance are less prominent as they often incur significant power and area overheads. 
         [0010]    Another challenge in capacitive touch sensing is interference rejection. Capacitive touch sensors pick up both touch signals and additive interference. The frequency content of the two might overlap or can be too close to each other for direct filtering to be practical. Typically, capacitive touch sensing systems employ amplitude modulation to up-convert touch signals to a frequency band where they can be easily separated from interference using frequency selective filtering to achieve relatively error free touch detection. 
         [0011]      FIG. 1  provides an example capacitive touch sensor circuit  100  with interference rejection. Touch sensor  103  receives a generated analog carrier signal (sine wave) to up-convert touch input signals generated when sensor  103  is touched. Specifically, waveform generator  101  generates a digital waveform which is then converted to analog by digital-to-analog converter (DAC)  102 . The carrier frequency is selected such that the up-converted touch signal falls in a frequency range with low interference levels. The up-converted touch signals along with interference feed into trans-impedance amplifier  104  and subsequently pass through analog-to-digital converter (ADC)  105 . The digital signals are demodulated at  106  using the digital carrier signal from waveform generator  101  and are fed into digital low pass filter (digital LPF)  107  for frequency selective filtering to remove interference. Data results (Data&lt;N-1:0&gt;) representing sensor capacitance values are output from the digital LPF and undergo further signal processing steps (not shown) to extract touch events. Although good interference rejection is achieved with such systems, dedicated digital-to-analog and analog-to-digital converters in addition to non-trivial digital signal processing blocks are required. These requirements increase the complexity of such systems making them less suitable for applications where low power and small area are necessary. Therefore, a need exists to provide a capacitive touch sensor having good interference rejection for low power and small area applications. Although there are many power and area efficient ways to sense capacitance, these schemes are usually inaccurate when interferers are present. 
         [0012]    Disadvantages of conventional approaches will be evident to one skilled in the art when presented in the disclosure that follows. 
       BRIEF SUMMARY OF THE INVENTION 
       [0013]    The technology described herein is directed to a method and apparatus that are further described in the following Brief Description of the Drawings and the Detailed Description of the Invention. Other features and advantages will become apparent from the following detailed description made with reference to the accompanying drawings. 
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S) 
       [0014]      FIG. 1  illustrates prior art circuitry for a capacitive touch sensor; 
         [0015]      FIG. 2  illustrates a circuit layout for one embodiment of a mutual capacitive touch sensor; 
         [0016]      FIG. 3  illustrates a timing diagram for the  FIG. 2  embodiment of the mutual capacitive touch sensor; 
         [0017]      FIG. 4  illustrates an interference transfer function for one embodiment of the technology described herein; 
         [0018]      FIG. 5  illustrates a circuit layout for one embodiment of the self-capacitive touch sensor; 
         [0019]      FIG. 6  illustrates a timing diagram for the  FIG. 5  embodiment of the self-capacitive touch sensor; and 
         [0020]      FIG. 7  illustrates steps for capacitive touch sensing of one embodiment of the technology described herein. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0021]    A switched capacitor is an electronic circuit element used for discrete time signal processing. It works by moving charges into and out of capacitors when switches are opened and closed. Usually, non-overlapping signals are used to control the switches, so that not all switches are closed simultaneously. The operations of switched capacitor circuits can be described mathematically using difference equations with corresponding frequency domain transfer functions. One or more of the following embodiments will include circuits using switched capacitance circuits. 
         [0022]      FIG. 2  illustrates one embodiment of a circuit  200  for capturing mutual capacitive touch sensor  202  inputs with interference rejection in accordance with the technology described herein. In particular, a circuit layout is shown that accomplishes capacitive touch sensing and interference rejection using a minimal amount of circuitry and digital logic. Capacitive touch sensor  202  including at least variable capacitor Cl is connected as the input capacitor to switched-capacitor integrator  204 . Charge transfer between sensor  202  and switched-capacitor integrator  204  occurs every clock period during a conversion cycle (i.e., multiple clock periods) and alternates in phase between positive (P) and negative (N) from one clock period to another. In the positive phase, driver (driving signal generator)  201  using, for example, a square wave causes voltage at the positive terminal of capacitive touch sensor  202  to change by Vref while capacitor C 2  is connected across the inverting and output terminals of operational amplifier  203 , thereby forcing charge to flow from capacitive touch sensor  202  into capacitor C 2 . To affect the voltage change, driver  201  first closes switch S 2  and opens switch S 1  during Φ 1 , then opens switch S 2  and closes switch S 1  during Φ 2 . Capacitor C 2  is connected across operational amplifier  203  by closing switches S 4  and S 5  during Φ 2 . During Φ 1  switches S 4  and S 5  are open, and to maintain virtual ground at the inverting input of operational amplifier  203 , switch S 3  is always closed during Φ 1 . The remaining switched-capacitor integrator  204  switches S 6  and S 7  are always open in the positive phase because capacitor C 3  is used only in the negative phase. Each time a charge transfer occurs in the positive phase, the voltage across capacitor C 2  increases (i.e., more positive) which in turn causes switched-capacitor integrator  204  output voltage to drop towards the negative supply. Over the duration of a conversion cycle, as charge transfers occur repeatedly, switched-capacitor integrator  204  output voltage will ramp-down towards the negative supply during the positive phase. 
         [0023]    Relative to the positive phase, charge transfer happens in the reverse direction during the negative phase. Here, driver  201  cause voltage at the positive terminal of capacitive touch sensor  202  to change by −Vref while capacitor C 3  is connected across the inverting and output terminals of operational amplifier  203 , thereby forcing charge to flow from capacitor C 3  into capacitive touch sensor  202 . To affect the voltage change, driver  201  first closes switch S 1  and opens switch S 2  during Φ 1 , then opens switch S 1  and closes switch S 2  during Φ 2 . Capacitor C 3  is connected across operational amplifier  203  by closing switches S 6  and S 7  during Φ 2 . During Φ 1  switches S 6  and S 7  are open, and to maintain virtual ground at the inverting input of operational amplifier  203 , switch S 3  is always closed during Φ 1 . The remaining switched-capacitor integrator  204  switches S 4  and S 5  are always open in the negative phase because capacitor C 2  is used only in the positive phase. Each time a charge transfer occurs in the negative phase, the voltage across capacitor C 3  decreases (i.e., more negative) which in turn causes switched-capacitor integrator  204  output voltage to jump-up towards the positive supply. Over the duration of a conversion cycle, as charge transfers occur repeatedly, switched-capacitor integrator  204  output voltage will ramp-up toward the positive supply during the negative phase. 
         [0024]    Comparator  205  is used to determine whether charge (absolute value) held in capacitors C 2  or C 3  has exceeded a predetermined threshold. In operation, it outputs logic 1 if switched-capacitor integrator  204  output voltage at the end of Φ 2  is greater than a reference level, and logic 0 otherwise. In the positive phase when enough charge is accumulated (in the positive direction) on C 2 , switched-capacitor integrator  204  output voltage drops below comparator  205  reference voltage level causing comparator  205  to output logic 1. When this happens, feedback-DAC  208  subtracts a fixed amount of charge from capacitor C 2  and consequently brings the voltage at switched-capacitor integrator  204  output above comparator  205  reference voltage level causing the comparator output to return to logic 0. From this point on, the charge on C 2  will continue to accumulate (in the positive direction) until the next time comparator  205  output is logic 1. Feedback-DAC  208  performs charge subtraction by forcing a voltage change equal to −Vref at the positive terminal of capacitor C 4  while capacitor C 2  is connected. This operation is realized by first closing switch S 9  and opening switch S 8  during Φ 1  and then opening switch S 9  and closing switch S 8  during Φ 2 . When no charge transfer is performed, switch S 9  is always open and switch S 8  is always closed. 
         [0025]    In the negative phase when enough charge is accumulated (in the negative direction) on C 3 , switched-capacitor integrator  204  output voltage jumps above comparator  205  reference voltage level causing comparator  205  to output logic 0. When this happens feedback-DAC  208  adds a fixed amount of charge to capacitor C 3  and consequently brings the voltage at switched-capacitor integrator  204  output below comparator  205  reference voltage level causing the comparator output to return to logic 1. From this point on, the charge on C 3  will continue to accumulate (in the negative direction) until the next time comparator  205  output is logic 0. Feedback-DAC  208  performs charge addition by forcing a voltage change equal to Vref at the positive terminal of capacitor C 4  while capacitor C 3  is connected. This operation is realized by first closing switch S 8  and opening switch S 9  during Φ 1  and then opening switch S 8  and closing switch S 9  during Φ 2 . When no charge transfer is performed, switch S 9  is always open and switch S 8  is always closed. 
         [0026]    Whenever charge is subtracted from capacitor C 2  or added to capacitor C 3  using the feedback-DAC  208 , the accumulator  207  increments by one to keep track the total amount of charge moved by feedback-DAC  208 . Digital logic  206  ensures a logic 1 is presented at accumulator  207  input whenever feedback-DAC  208  moves charge. At the end of every conversion cycle, accumulator  207  output is the digital equivalent of the average capacitance presented by sensor  202  during that conversion cycle. The exact sensor  202  capacitance value is calculated as the actual accumulator output at the end of the conversion cycle divided by the accumulator output that would result had it been incrementing every clock period during the entire conversion cycle, multiplied by the capacitance value of the feedback-DAC  208  capacitor C 4 . After the completion of each conversion cycle and before starting the next one, accumulator  207  and switched-capacitor integrator  204  are always reset. Resetting switched-capacitor integrator  204  comprises closing switches S 3 -S 7  simultaneously to remove charges stored on capacitors C 2  and C 3 . 
         [0027]      FIG. 3  illustrates an example timing diagram  300  associated with  FIG. 2  circuit  200 . Timing diagram  300  includes various timing cycles including clock  301 , mode  302  and phase  303 . Starting with clock cycle  1 , “converting period” includes a series of alternating positive (P) and negative (N) cycles during which charge transfer between sensor  202  and switched-capacitor integrator  204  occur. The cycles continue to transfer charge between sensor  202  and switched-capacitor integrator  204  until the capacitance conversion (converting cycle) is completed and the mode is changed to clear (reset (RST)) charge held by switched-capacitor integrator  204  capacitors and set accumulator  207  output to logic 0. The non-overlapping clock phases Φ 1  and Φ 2  use in circuit  200  are derived from clock  301 , where Φ 1  is in phase with clock  301  and Φ 2  is 180° out of phase with clock  301 . 
         [0028]      FIG. 4  illustrates an example interference transfer function associated with  FIG. 2  and  FIG. 3 . A pass-band is located around the driving signal frequency (0.5 Hz normalized). In the stop-band, the notch-envelope near DC rolls off towards negative infinity and settles to a finite value near clock  301  frequency (1 Hz normalized). The pass-band width, stop-band attenuation, and notch spacing depend on the total number of clock cycles  301  used for conversion which determines the system impulse response length and therefore the scaling of the interference transfer function in the frequency domain. Any interferer located outside of the pass-band is attenuated to the extent given by the transfer function. Interference inside the pass-band may also be mitigated by moving the pass-band away from the interfering frequency once in-band interference is detected. 
         [0029]    While not shown, circuit  200 , in one embodiment, is operated in a similar manner to sense in-band interference levels (peak baseline interference). However, different than normal operation, the touch sensor capacitor  202  is not driven (i.e., the output of driver  201  is connected to ground or Vref). The interference pass-band depends both on clock  301  frequency and the pattern with which phase cycle  303  changes between positive (P) and negative (N). While in  FIG. 3  phase  303  alternates between P and N every clock cycle, other patterns are considered within the scope of the technology described herein. 
         [0030]      FIG. 5  illustrates an alternative embodiment circuit layout  500  for a self-capacitive touch sensor. The circuit layout accomplishes self-capacitive touch sensing and interference rejection using a minimal amount of circuitry and digital logic. In particular, a circuit layout is shown that includes driver circuit  501  using, for example, a square wave with modified timing (as compared to  FIG. 2 ) for reference switch S 1  and grounded switch S 2 . Driver circuit  501  is connected to self-capacitive touch sensor  502  including at least grounded variable capacitor C 1 . Charge transfer between self-capacitive touch sensor  502  and switched-capacitor integrator  505  passes through added switch S 10  ( 503 ). Self-capacitive touch sensor  502  is connected as the input capacitor to switched-capacitor integrator  505 . Charge transfer between self-capacitive touch sensor  502  and switched-capacitor integrator  505  occur every clock period during a conversion cycle (i.e., multiple clock periods) and alternates in phase between positive (P) and negative (N) from one clock period to another. 
         [0031]    In the positive phase, switching of switches S 1  and S 10  cause voltage on the positive terminal of self-capacitive touch sensor  502  to change by −Vref/2 while capacitor C 2  is connected across the inverting and output terminals of operational amplifier  504 , thereby forcing charge to flow from self-capacitive touch sensor  502  into capacitor C 2 . To affect the voltage change, first switch S 1  is closed and switch S 10  is opened during Φ 1  forcing voltage across self-capacitive touch sensor  502  to be Vref, then switch S 1  is opened and S 10  is closed during Φ 2  forcing voltage across self-capacitive touch sensor  502  to settle towards Vref/2 (the voltage at the non-inverting input of operational amplifier  504 ). Capacitor C 2  is connected across operational amplifier  504  by closing switches S 4  and S 5  during Φ 2 . During Φ 1  switches S 4  and S 5  are open, and to maintain virtual ground at the inverting input of amplifier  504 , switch S 3  is always closed during Φ 1 . The remaining switched-capacitor integrator  505  switches S 6  and S 7  are always open in the positive phase because capacitor C 3  is used only in the negative phase. Each time a charge transfer occurs, the voltage across capacitor C 2  increases (i.e., more positive) which in turn causes switched-capacitor integrator  505  output voltage to drop towards the negative supply. Over the duration of a conversion cycle, as charge transfers occur repeatedly, switched-capacitor integrator  505  output voltage will ramp-down towards the negative supply during the positive phase. 
         [0032]    Relative to the positive phase, charge transfer happens in the reverse direction during the negative phase. Here, switching of switches S 2  and S 10  cause voltage at the positive terminal of self-capacitive touch sensor  502  to change by Vref/2 while capacitor C 3  is connected across the inverting and output terminals of operational amplifier  504 , thereby forcing charge to flow from capacitor C 3  into self-capacitive touch sensor  502 . To affect the voltage change, first switch S 2  is closed and S 10  is opened during Φ 1  forcing the voltage across self-capacitive touch sensor  502  to 0, then switch S 2  is open and switch S 10  is closed during Φ 2  forcing the voltage across self-capacitive touch sensor  502  to settle towards Vref/2 (the voltage at the non-inverting input of amplifier  504 ). Capacitor C 3  is connected across operational amplifier  504  by closing switches S 6  and S 7  during Φ 2 . During Φ 1  switches S 6  and S 7  are open, and to maintain virtual ground at the inverting input of amplifier  504 , switch S 3  is always closed during Φ 1 . The remaining switched-capacitor integrator  505  switches S 4  and S 5  are always open in the negative phase because capacitor C 2  is used only in the positive phase. Each time a charge transfer occurs, the voltage across capacitor C 3  decreases (i.e., more negative) which in turn causes switched-capacitor integrator  505  output voltage to jump-up towards the positive supply. Over the duration of a conversion cycle, as charge transfers occur repeatedly, switched-capacitor integrator  505  output voltage will ramp-up toward the positive supply during the negative phase. 
         [0033]    Comparator  506  is used to determine whether charge held in capacitors C 2  or C 3  has exceeded a predetermined threshold. In operation, comparator  506  outputs logic 1 if switched-capacitor integrator  505  output voltage at the end of Φ 2  is greater than a reference level, and logic 0 otherwise. During the positive phase when enough charge is accumulated (in the positive direction) on C 2 , switched-capacitor integrator  505  output voltage drops below comparator  506  reference voltage level causing comparator  506  to output logic 1. When this happens feedback-DAC  509  subtracts a fixed amount of charge from capacitor C 2  and consequently brings the voltage at switched-capacitor integrator  505  output above comparator  506  reference voltage level causing comparator output to return to logic 0. From this point on, the charge on C 2  will continue to accumulate (in the positive direction) until the next time comparator  506  output is logic 1. Feedback-DAC  509  performs charge subtraction by forcing a voltage change equal to −Vref at the positive terminal of capacitor C 4  while capacitor C 2  is connected. This operation is realized by first closing switch S 9  and opening switch S 8  during Φ 1  and then opening switch S 9  and closing switch S 8  during Φ 2 . When no charge transfer is performed, switch S 9  is always open and switch S 8  is always closed. 
         [0034]    In the negative phase when enough charge is accumulated (in the negative direction) on C 3 , switched-capacitor integrator  505  output voltage jumps above comparator  506  reference voltage level causing comparator  506  to output logic 0. When this happens, feedback-DAC  509  adds a fixed amount of charge to capacitor C 3  and consequently brings the voltage at switched-capacitor integrator  505  output below comparator  506  reference level causing the comparator output to return to logic 1. From this point on, the charge on C 3  will continue to accumulate (in the negative direction) until the next time comparator  506  output is logic 0. Feedback-DAC  509  performs charge addition by forcing a voltage change equal to Vref at the positive terminal of capacitor C 4  while capacitor C 3  is connected. This operation is realized by first closing switch S 8  and opening switch S 9  during Φ 1  and then opening switch S 8  and closing switch S 9  during Φ 2 . When no charge transfer is performed, switch S 9  is always open and switch S 8  is always closed. 
         [0035]    Whenever charge is subtracted from capacitor C 2  or added to capacitor C 3  using the feedback-DAC  509 , the accumulator  508  increments by one to keep track the total amount of charge moved by feedback-DAC  509 . Digital logic  507  ensures a logic 1 is presented at accumulator  509  input whenever feedback-DAC  509  moves charge. At the end of every conversion cycle, accumulator  508  output is the digital equivalent of the average capacitance presented by self-capacitive touch sensor  502  during that conversion cycle. The exact self-capacitive touch sensor  502  capacitance value is calculated as the actual accumulator output at the end of the conversion cycle divide by the accumulator output that would result had it been incrementing every clock period during the entire conversion cycle, multiplied by the capacitance value of the feedback-DAC  509  capacitor C 4 . After the completion of each conversion cycle and before starting the next one, accumulator  508  and switched-capacitor integrator  505  are always reset. Resetting switched-capacitor integrator  505  involves closing switches S 3 -S 7  simultaneously to remove charges stored on capacitors C 2  and C 3 . 
         [0036]      FIG. 6  illustrates an example timing diagram  600  associated with  FIG. 5  circuit  500 . Timing diagram  600  includes various timing cycles including clock  601 , mode  602  and phase  603 . Starting with clock cycle  1 , “converting period” includes a series of alternating positive (P) and negative (N) cycles during which charge transfer between self-capacitive touch sensor  502  and switched-capacitor integrator  505  occur. The cycles continue to transfer charge between self-capacitive touch sensor  502  and switched-capacitor integrator  505  until capacitance conversion (converting cycle) is completed and the mode is changed to clear (reset(RST)) charge held by switched-capacitor integrator  505  capacitors and set accumulator  508  output to logic 0. The non-overlapping clock phases Φ 1  and Φ 2  use in circuit  500  are derived from clock  601 , where Φ 1  is in phase with clock  601  and Φ 2  is 180° out of phase with clock  601 . 
         [0037]    While not shown, circuit  500  may be operated in a similar manner to sense in-band interference levels (peak baseline interference). However, different than normal operation, the self-capacitive touch sensor capacitor  502  is not driven (i.e., the output of driver  501  is connected to ground or Vref). The interference pass-band depends both on clock  601  frequency and the pattern with which phase cycle  603  changes between positive (P) and negative (N). While in  FIG. 6  phase  603  alternates between P and N every clock cycle, other patterns are considered within the scope of the technology described herein. 
         [0038]    Circuit  200  provided in  FIG. 2  can be made to interface with self-cap sensors by changing the operation of switches S 1  and S 2 , and adding switch S 10  as show in  FIG. 5 . To use this circuit with mutual cap sensors, added switch S 10  can be held as “always on”, and revert the operation of switches S 1  and S 2  to those shown in  FIG. 2  and  FIG. 3 . 
         [0039]      FIG. 7  illustrates an embodiment of the technology described within which functions to perform a series of steps to provide improved interference rejection for capacitive touch sensors. In step  701 , an in-band interference level is detected by first operating a capacitive touch sensor without a driving signal. In step  702 , if the interference level is higher than a maximum acceptable, a different pass-band is selected  703  by changing the system clock frequency (tuning) or altering the phase cycle pattern of  303  and  603 . Steps  701 ,  702 , and  703  are repeated until the in-band interference level is sufficiently low. This is possible assuming the interference doesn&#39;t continuously jam the entire operating frequency range of the sensor circuit. While steps  701 - 703  assist in avoiding in-band interference, they can be eliminated if a quality low-interference pass-band is known. 
         [0040]    In step  704 , the tuned driving signal is used to drive the capacitive touch sensor during a conversion cycle. The driving signal may operate at one fixed or multiple time-multiplexed frequencies to achieve a sufficiently low in-band interference level. In step  705 , two capacitors of switched-capacitor integrator alternately store charge transferred from the capacitive touch sensor (depending on direction of current flow). In step  706 , if charge stored on at least one of the capacitors of the switched-capacitor integrator exceeds a predetermined threshold, remove a fixed amount using a feedback loop and increment the accumulator. Steps  704 - 706  are repeated  707  until the conversion cycle is completed. In step  708 , a digital representation of the total capacitive touch sensor charge is captured from the accumulator output. In step  709 , the capacitors of the switched-capacitor integrator and accumulator are reset in preparation for the next conversion cycle. In step  710 , if the interference profile is static, then the next conversion cycle begins in step  704 . On the other hand, if the interference profile is highly dynamic, the next conversion cycle begins in step  701 . 
         [0041]    Current embodiments result in improved power efficiency in capacitive touch sensing circuits over the prior art while providing interference rejection. Furthermore, implementation of both self and mutual cap sensing can be achieved with negligible overhead. Being able to sense both self and mutual capacitance makes the touch controller compatible with a larger collection of sensors. Additionally, for mutual capacitive sensing applications, this capability allows the touch controller to capture more information from a touch panel which can be used to provide more functionality or perform diagnostics. Lastly, removing dedicated convertors and digital signal processing circuit elements from prior art capacitive sensor circuits reduces required chip (integrated circuit die) real estate costs and space. 
         [0042]    While various embodiments have been provided directed to touch sensor applications, detection of capacitive changes for applications unrelated to touch sensing are considered within the scope of the technology described herein. In addition, the technology described herein can be used for high resolution, low bandwidth analog-to-digital convertors. 
         [0043]    As may be used herein, the terms “substantially” and “approximately” provides an industry-accepted tolerance for its corresponding term and/or relativity between items. Such an industry-accepted tolerance ranges from less than one percent to fifty percent and corresponds to, but is not limited to, component values, integrated circuit process variations, temperature variations, rise and fall times, and/or thermal noise. Such relativity between items ranges from a difference of a few percent to magnitude differences. As may also be used herein, the term(s) “operably coupled to”, “coupled to”, and/or “coupling” includes direct coupling between items and/or indirect coupling between items via an intervening item (e.g., an item includes, but is not limited to, a component, an element, a circuit, and/or a module) where, for indirect coupling, the intervening item does not modify the information of a signal but may adjust its current level, voltage level, and/or power level. As may further be used herein, inferred coupling (i.e., where one element is coupled to another element by inference) includes direct and indirect coupling between two items in the same manner as “coupled to”. As may even further be used herein, the term “operable to” or “operably coupled to” indicates that an item includes one or more of power connections, input(s), output(s), etc., to perform, when activated, one or more its corresponding functions and may further include inferred coupling to one or more other items. As may still further be used herein, the term “associated with”, includes direct and/or indirect coupling of separate items and/or one item being embedded within another item. As may be used herein, the term “compares favorably”, indicates that a comparison between two or more items, signals, etc., provides a desired relationship. 
         [0044]    The technology as described herein has been described above with the aid of method steps illustrating the performance of specified functions and relationships thereof. The boundaries and sequence of these functional building blocks and method steps have been arbitrarily defined herein for convenience of description. Alternate boundaries and sequences can be defined so long as the specified functions and relationships are appropriately performed. Any such alternate boundaries or sequences are thus within the scope and spirit of the claimed invention. Further, the boundaries of these functional building blocks have been arbitrarily defined for convenience of description. Alternate boundaries could be defined as long as the certain significant functions are appropriately performed. Similarly, flow diagram blocks may also have been arbitrarily defined herein to illustrate certain significant functionality. To the extent used, the flow diagram block boundaries and sequence could have been defined otherwise and still perform the certain significant functionality. Such alternate definitions of both functional building blocks and flow diagram blocks and sequences are thus within the scope and spirit of the claimed invention. One of average skill in the art will also recognize that the functional building blocks, and other illustrative blocks, modules and components herein, can be implemented as illustrated or by discrete components, application specific integrated circuits, processors executing appropriate software and the like or any combination thereof. 
         [0045]    The technology as described herein may have also been described, at least in part, in terms of one or more embodiments. An embodiment of the technology as described herein is used herein to illustrate an aspect thereof, a feature thereof, a concept thereof, and/or an example thereof. A physical embodiment of an apparatus, an article of manufacture, a machine, and/or of a process that embodies the technology described herein may include one or more of the aspects, features, concepts, examples, etc. described with reference to one or more of the embodiments discussed herein. Further, from figure to figure, the embodiments may incorporate the same or similarly named functions, steps, modules, etc. that may use the same or different reference numbers and, as such, the functions, steps, modules, etc. may be the same or similar functions, steps, modules, etc. or different ones. 
         [0046]    Unless specifically stated to the contrary, signals to, from, and/or between elements in a figure of any of the figures presented herein may be analog or digital, continuous time or discrete time, and single-ended or differential. For instance, if a signal path is shown as a single-ended path, it also represents a differential signal path. Similarly, if a signal path is shown as a differential path, it also represents a single-ended signal path. While one or more particular architectures are described herein, other architectures can likewise be implemented that use one or more data buses not expressly shown, direct connectivity between elements, and/or indirect coupling between other elements as recognized by one of average skill in the art. 
         [0047]    While particular combinations of various functions and features of the technology as described herein have been expressly described herein, other combinations of these features and functions are likewise possible. The technology as described herein is not limited by the particular examples disclosed herein and expressly incorporates these other combinations.