Abstract:
Method and apparatus for interfacing a circuit, such as a microcircuit, with an IC. The circuit is formed on a thick film dielectric structure supported by a substrate having a cut out to receive the IC. A ground plane is formed on the substrate. The thick film dielectric structure abuts the cut out with an area having at least two projections forming at least one recess, the edge of the recess having a conductive layer in electrical communication with the ground plane. A conductive pad on top of the dielectric structure is in electrical communication with the conductive layer in the recess. A ground connection on the IC is connected to the conductive pad thereby grounding the IC.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    Microwaves are electromagnetic energy waves with very short wavelengths, typically ranging from a millimeter to  30  centimeters peak to peak. In high-speed communications systems, microwaves are used as carrier signals for sending information from point A to point B. Information carried by microwaves is transmitted, received and processed by microwave circuits.  
           [0002]    Packaging of RF and microwave microcircuits has traditionally been very expensive. The packaging requirements are extremely demanding—very high electrical isolation and excellent signal integrity through gigahertz frequencies are required. Additionally, IC power densities can be very high. KQ dielectric materials from HERAESUS has found favor among designers of microcircuits because of its ability to provide such high electrical isolation while using more forgiving thick film processes.  
           [0003]    One are in which the use of KQ has caused problems is the inability to create certain useful via structures. A typical layer of KQ is about  5  mils ({fraction (5/1000)} th  of an inch) thick. It is difficult to constructing vias through 5 mils of KQ that terminate on, but not pierce, a ground plane on top of a substrate. Another problem is that, to obtain a desired 50 ohm impedance in the signal path, the width of each via should be between 30 and 40 mils. An additional 20 mils of space is desirable to provide sufficient signal isolation. In the context of interconnecting an IC, this results in a rather large pitch. Accordingly, an interconnection scheme is needed that maximizes available real estate on the substrate.  
           [0004]    The present inventors have recognized a need for method and apparatus for replicating the functionality of vias while maximizing the use of space on a substrate.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0005]    An understanding of the present invention can be gained from the following detailed description of the invention, taken in conjunction with the accompanying drawings of which:  
         [0006]    [0006]FIG. 1 is a conceptual diagram of a partially completed IC connection structure in accordance with the present invention.  
         [0007]    [0007]FIG. 2 is a conceptual diagram of a partially completed IC connection structure in accordance with the present invention.  
         [0008]    [0008]FIG. 3 is a conceptual diagram of an IC connection structure in accordance with the present invention.  
         [0009]    [0009]FIG. 4 is a conceptual diagram of a circuit board in accordance with the present invention.  
         [0010]    [0010]FIG. 5 is an image of a circuit board formed in accordance with teachings of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0011]    Reference will now be made in detail to the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout.  
         [0012]    [0012]FIG. 1 is a conceptual diagram of a partially completed IC connection structure  10   a  in accordance with the present invention. It will be appreciated by those of ordinary skill in the relevant arts that the IC connection structure  10   a , as illustrated in FIGS. 1 through 5 and the method of formation thereof as described hereinafter, is intended to be generally representative of such structures and that any given system may differ significantly from that shown in FIG. 1, particularly in the details of construction and operation of such system. More to the point, the structure illustrated in FIGS. 1 through 4 have been simplified to aid in explanation. For example, only a small portion of a typical IC connection structure constructed in accordance with the present invention is illustrated. Those of ordinary skill in the art will recognize that the exact configuration of any given IC connection structure will depend heavily upon the IC used along with the layout of other circuits in the system. As such, the IC connection structure  1  On is to be regarded as illustrative and exemplary and not limiting as regards the invention described herein or the claims attached hereto.  
         [0013]    The present invention provides methods and apparatus for the integration of an IC into a circuit, such as a microcircuit, formed on a layer of dielectric. Looking at FIG. 1, an IC connection structure  10   a  is supported by a substrate  12  upon which a ground plane  14  has been formed. The ground plane  14  is preferably formed of gold, but other materials known to those of ordinary skill in the art may be suitable. A dielectric layer  16  is formed on the substrate  14 . The dielectric layer  16  may be a single layer or it may be built up with multiple layers. The dielectric layer supports at least one conductive trace (not shown) associated with a circuit to which an IC will be connected. The circuit may be a microcircuit.  
         [0014]    In perhaps the preferred embodiment, the dielectric layer  16  is formed from a thick film paste that is applied and subsequently cured. Examples of suitable thick film dielectric materials that may be deposited as a paste and subsequently cured include the KQ 150 and KQ 115 thick film dielectrics from Heraeus and the 4141 A/D thick film compositions from DuPont. These materials are primarily formulations of borosilicate glass containing small amounts of aluminum and magnesium. These products are applied as a paste, typically through a screen or stencil, and subsequently cured by the application of heat. They may be shaped at the time of application, before curing, or after curing by well known techniques (e.g., laser etching). These process are all described by the associated data sheets from the respective manufacturers. While the end result of using any of these products is essentially the same (a shaped region of controlled thickness and having a dielectric constant K of about 3.9) they have various ancillary differences that may be of interest to the designer. These include a change of color when cured, and an upward shift in softening temperature after an initial cure to facilitate structural stability during subsequent processing steps that require the re-application of heat to produce curing or processing of materials applied in those subsequent processing steps.  
         [0015]    In the case of the present invention, the dielectric layer  16  is formed with an area  18 , referred to herein as the connection area  18 , of projections and recesses surrounding the desired location of the IC. Ideally, the connection area  18  is formed as a corrugated pattern, however, those of ordinary skill in the art will recognize that the shape, pitch and placement of the connection area  18  will vary depending on the configuration of the IC to be used and the process used to form the connection area  18 . It is to be noted that while the term corrugated has been used to describe the shape of the connection area  18 , the resulting projections and recesses need neither be parallel nor uniform. Further, the shape of the projections and recesses need not be a triangular pattern as shown in FIG. 1, but can be of any shape, such as square, circular or even irregular.  
         [0016]    During curing, KQ material shrinks, mostly contracting on an upper surface  16   a , to form an approximately 45-degree slope from the upper surface  16   a  to a lower surface  16   b . After curing a layer of conductive material, such as gold, is deposited upon the slope between the upper and lower surfaces  16   a  and  16   b  on at least on the exposed edge of the area  18  of the dielectric  16 . This, in essence, extends the ground plane  14  onto the area  18 .  
         [0017]    A portion of the dielectric layer  16  and substrate  12  is removed, using, for example, laser etching technology. In perhaps the preferred embodiment, a cut is made across the middle of the connection area  18 , for example at dotted line  20 . How much, if any of the dielectric layer  16  is cut may depend on a variety of factors, including the pitch of the connection in the IC used and the geometry of the connection area  18 .  
         [0018]    [0018]FIG. 2 is a conceptual diagram of a partially completed IC connection structure  10   b  in accordance with the present invention. In the example shown in FIG. 2, the removed portion  25  of the dielectric layer  16  and substrate  12  corresponds in shape to the IC being used. This does not need be the case. In fact the portion removed may be of any shape selected by the circuit designer, so long as the IC can be mounted within the removed portion  25 . In the example shown in FIG. 2, the cut forms discrete via-like ground connections,  24   a ,  24   b , and  24   c  in the recesses of the connection area  18 . Each ground connection  24   n  is isolated by flat non-conducting portions  22   n.    
         [0019]    It is preferable, but not necessary that the remaining portions of the connection area  18  have a length corresponding to the length of the side of the IC which will abut the connection area  18 . As is known to those of ordinary skill in the art, with high frequency signals, shorter signal paths reduce signal degradation. Accordingly, it may be preferable that the removed portion  25  be dimensioned 1 mil or less larger than the dimensions of the IC to be used.  
         [0020]    [0020]FIG. 3 is a conceptual diagram of an IC connection structure in accordance with the present invention. Ground connection pads  26   a - 26   c  and signal connection pads  28   a - 28   c  are shown in FIG. 3. The ground connection pads  26   n  are in electrical connection with the ground connections  24   n  and may be formed of gold pads. Signal connection pads  28   a  through  28   c  are also shown. The signal connection pads  28   n  are connected to transmission lines  30   a  though  30   c . Note that while rectangular connection pads  26   n  and  28   n  are portrayed, the pads can be of any shape chosen by the designer and may be simple extensions of the transmission lines  30   n . The exact number of ground connection pads  26   n  and signal connection pads  28   n  will be determined by the desired number and type of connections between the IC to be used and the circuit to which the IC is to be connected.  
         [0021]    The transmission lines  30   n , may be of a variety of geometries. In perhaps the preferred embodiment, the transmission lines  30   n  are microstrips. The microstrips may be subsequently transitioned into a quasi-grounded coplanar waveguide (not shown). Microstrips are an open type of transmission line, other such open transmission lines include: coplanar waveguide, and coupled microstrip. Open transmission line may be transitioned to other geometries including: stripline, quasi-coaxial, and coupled stripline. It may also be preferable for the signal connections  28   n  to directly interface with such other transmission line structures, including a quasi-coaxial transmission line.  
         [0022]    A quasi-coaxial transmission line uses an upper layer of KQ dielectric printed over the transmission line. The KQ dielectric is surrounded by a printed metal ground plane providing a completely surrounded structure. The metal ground plane might be grounded by using aspects of the present invention. For high frequency or high-speed digital signals, it may be beneficial for the transmission line  12  to exhibit a 50 ohm impedance.  
         [0023]    [0023]FIG. 4 is a conceptual diagram of a circuit board  100  in accordance with the present invention. An IC  50  is mounted on a pedestal  52 . An optional spacer  54  is shown that raises the top of the IC  50  to the height of the dielectric  16 . By raising the top of the IC  50  to the height of the dielectric  16 , the distances between connection points on the IC  50  and the dielectric  16  are minimized resulting in improved signals there between. The IC  50 , pedestal  52  and spacer  54  are mounted to the substrate  14 . Connection pads  56   n  on the IC are connected to connection pads  26   n  and  28   n  on the dielectric  16 . The connections can be formed using any suitable technology, such as wire bonding.  
         [0024]    [0024]FIG. 5 is an image of a circuit board  102  formed in accordance with teachings of the present invention. FIG. 5 is a plan view of the circuit board  102 . The cut out portion  125  is surrounded by six visible ground connection pads  110   a  through  110   f . Corresponding ground connections  112   a  through  112   f  are also visible. As is apparent in FIG. 5, while the ground connections have been described as being corrugated or triangular in shape, their actual shape will vary depending on many factors, including the accuracy of the formation process. Thus while some ground connections are triangular (such as  112   f ), other may be more rounded (such as  112   b ) or even irregular (such as  112   e ).  
         [0025]    Although a few variations of the preferred embodiment of the present invention have been shown and described, it would be appreciated by those skilled in the art that changes may be made to the described invention without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.