Abstract:
A method for manufacturing an injection-enhanced insulated-gate bipolar transistor, comprising the following steps: an n-type substrate ( 12 ) is provided; a p-type doped layer ( 14 ) is formed on the n-type substrate ( 12 ); a hard layer ( 20 ) is formed on the p-type doped layer ( 14 ); a groove ( 40 ) extending to the n-type substrate ( 12 ) is formed by etching on the p-type doped layer ( 14 ); an n-type doped layer ( 50 ) is formed on the sidewalls and bottom of the groove ( 40 ); the hard layer ( 20 ) is removed; p-type impurities of the p-type doped layer ( 14 ) and n-type impurities of the n-type doped layer ( 50 ) are driven in together, where the p-type impurities are diffused to form a p-type base region ( 60 ), and the n-type impurities are diffused to form an n-type buffer layer ( 70 ); a gated oxide dielectric layer ( 80 ) is formed on the surface of the groove ( 40 ); and, a polysilicon layer ( 90 ) is deposited in the groove having formed therein the gate oxide dielectric layer ( 80 ). In the method for manufacturing the injection-enhanced insulated-gate bipolar transistor, the p-type doped layer ( 14 ) and the n-type doped layer ( 50 ) are driven in together to form the p-type base region ( 60 ) and the n-type buffer layer ( 70 ), as only one drive-in process is required, production cycle is shortened in comparison with a conventional method for manufacturing the injection-enhanced insulated-gate bipolar transistor.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to a technical field of semiconductor manufacture, and more particularly, relates to a method of manufacturing an injection-enhanced Insulated Gate Bipolar Transistor. 
       BACKGROUND OF THE INVENTION 
       [0002]    Currently, in an injection-enhanced insulated gate bipolar transistor (IGBT), the buffer layer is formed by generally implanting an N-type dopant, and then a drive-in is performed, a body implantation is performed, then a drive-in is performed again, such that a time period of the drive-in for forming the buffer layer is longer than a time period of the drive-in for forming the body, which results in that a junction depth of the N-type dopant to be deeper than a junction depth of the body. Therefore, when such IGBT manufacturing method is adopted, it requires an additional drive-in to the buffer layer before performing a drive-in to the body, the N-type dopant is distributed and diffused by virtue of a long time period of drive-in, causing the junction depth of the N-type dopant to be deeper than the junction depth of the body, an N+ is formed beneath the body, such that an enhanced injection can be achieved. However, the method of manufacturing the injection-enhanced IGBT requires additionally adding a drive-in process, the production cycle thereof is long. 
       SUMMARY OF THE INVENTION 
       [0003]    Therefore, it is necessary to provide a method of manufacturing an injection-enhanced IGBT which has a shorter production cycle. 
         [0004]    A method of manufacturing an injection-enhanced IGBT includes steps as follow: providing an N-type substrate; forming a P-type doped layer on the N-type substrate; forming a hard layer on the P-type doped layer; etching the hard layer to form a hard layer having a trench pattern; etching the P-type doped layer to form a trench extending into the N-type substrate; forming an N-type doped layer on a sidewall and a bottom of the trench; removing the hard layer having the trench pattern; performing a drive-in to the P-type dopant of the P-type doped layer and the N-type dopant of the N-type doped layer together, the P-type dopant forms a P-type base region by diffusing, and the N-type dopant forms an N-type buffer layer by diffusing; forming a gate oxide dielectric layer on a surface of the trench; and depositing a polysilicon layer in the trench on which the gate oxide dielectric layer is formed. 
         [0005]    According to one embodiment, the P-type doped layer is formed by ion implantation or diffusion. 
         [0006]    According to one embodiment, a concentration of P-type dopant in the P-type doped layer is from 1×10 12 /cm 3  to 1×10 20 /cm 3 . 
         [0007]    According to one embodiment, in the forming the N-type doped layer on the sidewall and the bottom of the trench, the hard layer is adopted as a mask, the N-type doped layer is formed by diffusion technology. 
         [0008]    According to one embodiment, a concentration of N-type dopant in the N-type doped layer is from 1×10 12 /cm 3  to 1×10 20 /cm 3 . 
         [0009]    According to one embodiment, in the performing a drive-in to the P-type dopant of the P-type doped layer and the N-type dopant of the N-type doped layer together, a temperature of the drive-in is from 1100° C. to 1280° C. 
         [0010]    According to one embodiment, in the performing a drive-in to the P-type dopant of the P-type doped layer and the N-type dopant of the N-type doped layer together, a time period of the drive-in is from 20 min to 500 min. 
         [0011]    According to one embodiment, the forming the gate oxide dielectric layer on the surface of the trench comprises: oxidizing the surface of the trench to form a sacrificial oxide layer; removing the sacrificial oxide layer by etching; oxidizing the surface of the trench to form the gate oxide dielectric layer. 
         [0012]    According to one embodiment, the hard layer is made of silicon oxide or silicon nitride. 
         [0013]    A method of manufacturing an injection-enhanced IGBT includes steps as follow: providing an N-type substrate; forming a hard layer on the N-type doped layer; etching the hard layer to form a hard layer having a trench pattern; etching the N-type doped layer to form a trench; forming an N-type doped layer on a sidewall and a bottom of the trench; removing the hard layer having the trench pattern; forming a mask layer in the trench, the mask layer filling the trench; forming a P-type doped layer on a surface of the N-type substrate which forms the trench; removing the mask layer; performing a drive-in to the P-type dopant of the P-type doped layer and the N-type dopant of the N-type doped layer together, the P-type dopant forming a P-type base region by diffusing, and the N-type dopant forming an N-type buffer layer by diffusing; forming a gate oxide dielectric layer on a surface of the trench; and depositing a polysilicon layer in the trench on which the gate oxide dielectric layer is formed. 
         [0014]    In above described injection-enhanced IGBT, the P-type dopant of the P-type doped layer and the N-type dopant of the N-type doped layer are driven-in together to form a P-type base region and an N-type buffer layer, only one drive-in process is required, the production cycle is shortened in comparison with a conventional method of manufacturing injection-enhanced IGBT. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]      FIG. 1  is a flow chart of a method of manufacturing an injection-enhanced IGBT according to one embodiment; 
           [0016]      FIGS. 2  though  11  are schematic views of the structures corresponding to the process shown in  FIG. 1 ; 
           [0017]      FIG. 12  is a flow chart of a method of manufacturing an injection-enhanced IGBT according to another embodiment; and 
           [0018]      FIG. 13  is a flow chart of a method of manufacturing an injection-enhanced IGBT according to yet another embodiment. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0019]    For the purpose of better understanding the above objects, features and advantages, embodiments of the present invention will be described in detail hereinafter in conjunction with the drawings. To facilitate the sufficient understanding of the invention, many details are set forth in the following description. However, the present invention may be implemented in other manners than those described herein, and similar extensions may be made by those skilled in the art without deviating from the spirit of the present invention. Therefore, the present invention is not limited by the embodiments disclosed hereinafter. 
         [0020]    As shown in  FIG. 1 , a method of manufacturing an injection-enhanced IGBT according to one embodiment includes the following steps: 
         [0021]    S 110 , an N-type substrate is provided. 
         [0022]    Referring to  FIG. 2 , the specific resistance of the N-type substrate  12  is in a range of from about 0.01 Ω*cm to 200 Ω*cm. In practical application, the N-type substrate  12  having different specific resistances can be selected according to the IGBT product. The N-type substrate  12  can have a thickness in a range of from 100 μm to 1000 μm. 
         [0023]    S 115 , a P-type doped layer  14  is formed on the N-type substrate  12 . 
         [0024]    Referring to  FIG. 2 , a P-type doped layer  14  is formed by performing a P-type doping to the N-type substrate  12 . Specifically, the P-type doped layer  14  can be formed by diffusion or ion implantation. The forming method of the P-type doped layer  14  is not limited herein. When the P-type doped layer  14  is formed by ion implantation, the implanted ion can be boron (B), and an implantation concentration of the ions can be from 1×10 12 /cm 3  to 1×10 20 /cm 3 . The energy of the implantation ion can be from 20 KeV to 200 KeV. 
         [0025]    S 120 , a hard layer is formed on the P-type doped layer. 
         [0026]    Referring to  FIG. 3 , the hard layer  20  can be made of silicon oxide or silicon nitride. The thickness of the hard layer  20  can be in a range of 500 angstrom to 100000 angstrom. In practical application, the thickness of the hard layer  20  can be other values. The hard layer  20  covers the P-type doped layer  14 . When the hard layer  20  is made of silicon oxide, the hard layer  20  can be formed by methods such as lower pressure SiO 2  vapor deposition technology, furnace oxidation, rapid thermal annealing oxidation or in-situ vapor oxidation. When the hard layer  20  is made of silicon nitride, the hard layer  20  can be manufactured by chemical vapor deposition technology. 
         [0027]    S 130 , a hard layer having a trench pattern is formed by etching the hard layer. 
         [0028]    The hard layer having the trench pattern is formed by adopting photolithography and etching method to etch the hard layer. 
         [0029]    The specific steps of adopting a photo-etching method to etch the hard layer to form the hard layer having the trench pattern is: 
         [0030]    Referring to  FIG. 4 , a photoresist layer  30  is formed on the hard layer  20  first. And then, the photoresist layer  30  is placed beneath an exposure equipment, a photo-mask having the trench pattern on its surface is adopted to perform a photo-mask exposure, the trench pattern on the photo-mask is transferred to the photoresist layer  30 , and then developing solution is adopted to remove the photoresist on the exposure region, the photoresist layer  30  having the trench pattern is formed. Referring to  FIG. 5 , the photoresist layer  30  having the trench pattern is adopted as a mask, the hard layer  20  is etched to form the hard layer  20  having the trench pattern. 
         [0031]    The photoresist layer  30  can be formed by static drip or spin coating technology. 
         [0032]    S 140 , a trench is formed by etching the P-type doped layer, and the trench extends into the N-type substrate. 
         [0033]    Referring to  FIG. 6  and  FIG. 9 , in the embodiment, a depth of the trench  40  extends through the P-type doped layer  14 , and the depth of the trench  40  is deeper than a thickness of the P-body  60  which is formed by performing a drive-in to the P-type doped layer  14 . The depth of the trench  40  can be in a range of 0.5 μm to 15 μm. In practical application, one skilled in the art can select the depth of the trench  40  according to a specific condition. 
         [0034]    After etching the hard layer  20  to form the hard layer  20  having the trench pattern, and before forming the trench  40  on the P-type doped layer  12 , the photoresist layer  30  can be removed. The photoresist layer  30  can also be removed after forming trench  40  on the P-type doped layer  12 . The photoresist layer  30  can be removed by dry stripping or wet stripping technology. The dry stripping technology adopts plasma to bombard the photoresist to remove the photoresist layer  30 . The wet stripping technology adopts cleaning solution to remove the photoresist layer  30 . The cleaning solution adopted by the wet stripping technology can be a mixed liquid of sulfuric acid and oxidizing agent. In other embodiments, the cleaning solution of the wet stripping technology can be other mixture material. It should be noted that, one skilled in the art can selectively adopt the dry stripping technology or the wet stripping technology to remove the photoresist layer  30  according to a practical situation. 
         [0035]    S 150 , an N-type doped layer is formed on a sidewall and a bottom of the trench. 
         [0036]    Referring to  FIG. 7 , in the embodiment, the hard layer  20  having the trench pattern is adopted as a mask, and the N-type doped layer  50  is formed on the sidewall and the bottom of the trench  40  by a diffusion technology. 
         [0037]    The temperature of the diffusion technology is from 800° C. to 1250° C., the time period of the diffusion technology is from 10 min to 300 min, the diffusion source is an N-type dopant, such as B 2 O 3 , POCl 3  or PH 3 . In the embodiment, the diffusion source is POCl 3 . The concentration of the N-type dopant of the N-type doped layer  50  is from 1×10 12 /cm 3  to 1×10 20 /cm 3 . The category and concentration of dopant in the growth process can be controlled according to a specific requirement of the device. The N-type doped layer  50  has a thickness from 0.5 μm to 20 μm. 
         [0038]    S 160 , the hard layer  20  having the trench pattern is removed. When the hard layer  20  is an oxide, the hard layer  20  covering on the P-type doped layer  14  is removed by the plasma etching technology or by the buffer oxide etching technology, the structure after removing the hard layer  20  is shown as  FIG. 8 . The buffer oxide etching technology can adopt a mixed solution of hydrofluoric acid (49%), water and ammonium fluoride to rinse the hard layer  20 . In practical application, a removal rate of the hard layer  20  can be adjusted by adjusting concentrations of the hydrofluoric acid and the ammonium fluoride. 
         [0039]    When the hard layer  20  is nitride, the hard layer  20  can be removed by wet etching. 
         [0040]    S 170 , the P-type dopant of the P-type doped layer and the N-type dopant of the N-type doped layer are driven-in together, the P-type dopant forms a P-type base region by diffusing, and the N-type dopant forms an N-type buffer layer by diffusing. 
         [0041]    Referring to  FIG. 9 , the drive-in allows the implanted N-type dopant and the P-type dopant to penetrate the silicon crystal in the N-type substrate  12  and form a desired junction depth in the N-type substrate  12 , and form a P-type base region and an N-type buffer layer,. In the embodiment, the temperature of drive-in can be from 1100° C. to 1280° C., the time period of drive-in can be from 20 min to 500 min. In practical application, the temperature and time period of the drive-in can be adjusted according to a specific requirement of the device. 
         [0042]    S 180 , a gate oxide dielectric layer is formed on the surface of the trench. 
         [0043]    The operation for forming the gate oxide dielectric layer on the surface of the trench includes: 
         [0044]    First, a sacrificial oxide layer (not shown) is formed by oxidizing the surface of the trench  40 . Then, the sacrificial oxide layer is removed by etching. Subsequently, the surface of the trench  40  is oxidized to form a gate oxide dielectric layer  80 . The structure after forming a gate oxide dielectric layer  80  is shown as  FIG. 10 . 
         [0045]    Because many more defects are inevitably formed on the surface of the trench  40  when etching the trench, it affects the quality of the gate oxide dielectric layer  80 . Therefore, when the surface of the trench  40  is oxidized to form a sacrificial oxide layer first, and then the sacrificial oxide layer is etched to be removed, and then the gate oxide dielectric layer  80  is formed by oxidization, it facilitates to improve the oneness of the material and the homogeneity of the gate oxide dielectric layer  40 , and improving the quality of the gate oxide dielectric layer. 
         [0046]    The sacrificial oxide layer can be formed by a dry oxidization or a wet oxidization. 
         [0047]    The sacrificial oxide layer can be removed by a wet etching. 
         [0048]    The gate oxide dielectric layer  80  can be formed by a dry oxidization. The oxidizing method of the gate oxide dielectric layer  80  is not limited. For one skilled in the art, an appropriate oxidizing method of the gate oxide dielectric layer  80  can be selected according to a requirement of the quality of the gate oxide dielectric layer  80 . A thickness of the gate oxide dielectric layer  80  can be in a range from 100 angstrom to 5000 angstrom, for example, the thickness is 1000 angstrom. 
         [0049]    S 190 , a polysilicon layer is deposited in the trench on which the gate oxide dielectric layer is formed. 
         [0050]    The structure after depositing a polysilicon layer in the trench on which the gate oxide dielectric layer is formed and a back etching is shown as  FIG. 11 . The polysilicon layer can be formed by chemical vapor deposition, physical vapor deposition or other ways. In practical application, an appropriate deposition method can be selected according to a requirement. In the embodiment, the polysilicon layer  90  can adopt a dry etching to back etch the polysilicon layer, to remove the redundant deposition. 
         [0051]    A gate electrode is formed by performing subsequent processes to the polysilicon layer  90 . Subsequently, an emitting electrode and a collector electrode are formed by performing front processes, backgrind, back implantation, annealing, and back metallization and other steps to the device obtained by S 190 , an injection-enhanced IGBT is obtained. All technologies such as performing subsequent processes to the polysilicon layer  9  to form a gate electrode, front processes, backgrind, back implantation, annealing, and back metallization can adopt customary means in the technical field, and will not be limited hereby. 
         [0052]    Above described method of manufacturing an injection-enhanced IGBT is merely directed to an operation including: forming a P-type doped layer on the surface of the N-type substrate first; performing an etching to the trench subsequently; and then forming an N-type doped layer by diffusion technology; and then performing a drive-in to the P-type dopant of the P-type doped layer and the N-type dopant of the N-type doped layer together. It is possible that performing an etching to the N-type substrate to form the trench first, and then forming a P-type doped layer on the surface of the N-type substrate; and then forming an N-type doped layer by diffusion technology; and then performing a drive-in to the P-type dopant of the P-type doped layer and the N-type dopant of the N-type doped layer together. 
         [0053]    As shown in  FIG. 12 , a method of manufacturing an injection-enhanced IGBT according to another embodiment, includes the following steps: 
         [0054]    S 210 , an N-type substrate is provided. 
         [0055]    The N-type substrate provided in S 210  is same as the N-type substrate provided in S 110 . 
         [0056]    S 215 , a hard layer is formed on the N-type substrate. 
         [0057]    The hard layer in S 215  is same as the hard layer in S 120 . The technology for forming the hard layer in S 215  is same as the technology for forming the hard layer in S 120   
         [0058]    S 220 , a hard layer having a trench pattern is formed by etching the hard layer. 
         [0059]    The technology of etching the hard layer to form a hard layer having the trench pattern in S 220  is same as the technology of etching the hard layer to form a hard layer having the trench pattern in S 130 . 
         [0060]    S 225 , a trench is formed by etching the N-type substrate. 
         [0061]    The trench formed in S 225  is same as the trench formed in S 140 . 
         [0062]    S 230 , an N-type doped layer is formed on a sidewall and a bottom of the trench. 
         [0063]    In the embodiment, the hard layer having the trench pattern formed in step S 220  is adopted as a mask, and the N-type doped layer is formed on the sidewall and the bottom of the trench by diffusion technology. The diffusion technology in S 230  is same as the diffusion technology in S 150 . 
         [0064]    S 235 , the hard layer having the trench pattern is removed. 
         [0065]    The technology of removing the hard layer having the trench pattern in S 235  is same as the technology of removing the hard layer having the trench pattern in S 160 . 
         [0066]    S 240 , a mask layer is formed in the trench, and the mask layer fills the trench. 
         [0067]    In the embodiment, the mask layer can be made of photoresist. When the mask layer is made of photoresist, the photoresist layer can be formed by performing static drip or spin coating to the surface of the N-type substrate, the photoresist fills the trench, and the photoresist on the surface of the N-type substrate which forms no trench is removed, and the photoresist in the trench is reserved. 
         [0068]    S 250 , a P-type doped layer is formed on the surface of the N-type substrate which forms the trench. 
         [0069]    In the embodiment, the P-type doped layer is formed by ion implantation. The ion implantation technology is same as that in S 115 . 
         [0070]    S 260 , the mask layer is removed. 
         [0071]    When the mask layer is made of photoresist, the dry stripping technology and the wet stripping technology can be adopted to remove the mask layer. The dry stripping technology adopts plasma to bombard the photoresist to remove the mask layer. The wet stripping technology adopts cleaning solution to remove the mask layer  30 . The cleaning solution adopted by the wet stripping technology can be a mixed liquid of sulfuric acid and oxidizing agent. 
         [0072]    S 270 , the P-type dopant of the P-type doped layer and the N-type dopant of the N-type doped layer are driven-in together, the P-type dopant forms a P-type base region by diffusing, and the N-type dopant forms an N-type buffer layer by diffusing. 
         [0073]    The operation in S 270  is same as that in S 170 . 
         [0074]    S 280 , a gate oxide dielectric layer is formed on the surface of the trench. 
         [0075]    The operation in S 280  is same as that in S 180 . 
         [0076]    S 290 , a polysilicon layer is deposited in the trench on which the gate oxide dielectric layer is formed. 
         [0077]    The operation in S 290  is same as that in S 190 . A gate electrode is formed by performing subsequent processes to the polysilicon layer. Subsequently, an emitting electrode and a collector electrode are formed by performing front processes, backgrind, back implantation, annealing, and back metallization and so on to the device obtained by S 290 , an injection-enhanced IGBT is obtained. All technologies such as performing subsequent processes to the polysilicon layer to form a gate electrode, front processes, backgrind, back implantation, annealing, and back metallization can adopt customary means in the technical field, and will not be limited hereby. 
         [0078]    As shown in  FIG. 13 , a method of manufacturing an injection-enhanced IGBT according to another embodiment, includes the following steps: 
         [0079]    S 310 , an N-type substrate is provided. 
         [0080]    The N-type substrate provided in S 310  is same as the N-type substrate provided in S 110 . 
         [0081]    S 315 , a hard layer is formed on the N-type substrate. 
         [0082]    The hard layer in S 315  is same as the hard layer in S 120 . The technology for forming the hard layer in S 315  is same as the technology for forming the hard layer in S 120   
         [0083]    S 320 , a hard layer having a trench pattern is formed by etching the hard layer. 
         [0084]    The technology of etching the hard layer to form a hard layer having the trench pattern in S 320  is same as the technology of etching the hard layer to form a hard layer having the trench pattern in S 130 . 
         [0085]    S 325 , a trench is formed by etching the N-type substrate. 
         [0086]    The trench formed in S 325  is same as the trench formed in S 140 . 
         [0087]    S 330 , the hard layer having the trench pattern is removed. 
         [0088]    The technology of removing the hard layer having the trench pattern in S 330  is same as the technology of removing the hard layer having the trench pattern in S 160 . 
         [0089]    S 335 , a mask layer is formed in the trench, and the mask layer fills the trench. 
         [0090]    In the embodiment, the mask layer can be made of photoresist. When the mask layer is made of photoresist, the photoresist layer can be formed by performing static drip or spin coating to the surface of the N-type substrate, the photoresist fills the trench, and the photoresist on the surface of the N-type substrate which forms no trench is removed, and the photoresist in the trench is reserved. 
         [0091]    S 340 , a P-type doped layer is formed on the surface of the N-type substrate which forms the trench. 
         [0092]    In the embodiment, the P-type doped layer is formed by ion implantation. The ion implantation technology is same as that in S 115 . 
         [0093]    S 350 , the mask layer is removed. 
         [0094]    When the mask layer is made of photoresist, the dry stripping technology and the wet stripping technology can be adopted to remove the mask layer. The dry stripping technology adopts plasma to bombard the photoresist to remove the mask layer. The wet stripping technology adopts cleaning solution to remove the mask layer. The cleaning solution adopted by the wet stripping technology can be a mixed liquid of sulfuric acid and oxidizing agent. 
         [0095]    S 360 , an N-type doped layer is formed on a sidewall and a bottom of the trench. 
         [0096]    The N-type doped layer is formed on the sidewall and the bottom of the trench by diffusion technology. The diffusion technology in S 360  is same as the diffusion technology in S 150 . 
         [0097]    S 370 , the P-type dopant of the P-type doped layer and the N-type dopant of the N-type doped layer are driven-in together, the P-type dopant forms a P-type base region by diffusing, and the N-type dopant forms an N-type buffer layer by diffusing. 
         [0098]    The operation in S 370  is same as that in S 170 . 
         [0099]    S 380 , a gate oxide dielectric layer is formed on the surface of the trench. 
         [0100]    The operation in S 380  is same as that in S 180 . 
         [0101]    S 390 , a polysilicon layer is deposited in the trench on which the gate oxide dielectric layer is formed. 
         [0102]    The operation in S 390  is same as that in S 190 . A gate electrode is formed by performing subsequent processes to the polysilicon layer. Subsequently, an emitting electrode and a collector electrode are formed by performing front processes, backgrind, back implantation, annealing, and back metallization and so on to the device obtained by S 390 , an injection-enhanced IGBT is obtained. All technologies such as performing subsequent processes to the polysilicon layer to form a gate electrode, front processes, backgrind, back implantation, annealing, and back metallization can adopt customary means in the technical field, and will not be limited herein. 
         [0103]    In above described injection-enhanced IGBT, the P-type dopant of the P-type doped layer and the N-type dopant of the N-type doped layer are driven-in together to form a P-type base region, and an N-type buffer layer, only one drive-in process is required, the production cycle is shortened in comparison with a conventional method of manufacturing injection-enhanced IGBT. In the conventional method of manufacturing injection-enhanced IGBT, the implantation positions of the buffer layer and the body are the same, two drive-in processes are performed, causing the body to be diffused, and it is compensated by the P-type dopant and the N-type dopant, thus the resistance in the base region to be increased. In the method of manufacturing above described injection-enhanced IGBT, the implantation positions of the buffer layer and the doped layer are different, the P-type doped layer and the N-type doped layer are driven-in together, the P-type dopant and the N-type dopant are not required to compensate. 
         [0104]    The device manufactured by above described method of manufacturing an injection-enhanced IGBT can optimize the performance of the device, such as voltage drop saturation (VDSON). 
         [0105]    Although the invention is illustrated and described herein with reference to specific embodiments, the invention is not intended to be limited to the details shown. Rather, various modifications may be made in the details within the scope and range of equivalents of the claims and without departing from the invention.