Abstract:
One embodiment of the invention provides a method and a system for using phase shifter cutbacks to resolve conflicts between phase shifters during creation of a mask to be used in an optical lithography process for manufacturing an integrated circuit. The system works by locating a plurality of phase shifters, including a first phase shifter and a second phase shifter, on a phase shifting mask, and then identifying a conflict area wherein a conflict is likely to occur between the first phase shifter and the second phase shifter on the phase shifting mask. The system resolves this conflict by cutting back one or both of the first phase shifter and the second phase shifter, so that the first phase shifter and the second phase shifter do not interfere with each other in the conflict area.

Description:
RELATED APPLICATION 
     This application hereby claims priority under 35 U.S.C. §119 to U.S. Provisional Patent Application No. 60/288,738 filed May 4, 2001. 
     The subject matter of this application is related to the subject matter in a co-pending non-provisional application by the same inventor as the instant application and filed on the same day as the instant application entitled, “Method and Apparatus for Reducing Color Conflicts During Trim Generation for Phase Shifters,” having serial number TO BE ASSIGNED, and filing date TO BE ASSIGNED (Attorney Docket No. NMTC-0742). 
    
    
     BACKGROUND 
     1. Field of the Invention 
     The invention relates to the process of fabricating semiconductor chips. More specifically, the invention relates to a method and an apparatus for using phase shifter cutbacks to resolve conflicts between phase shifters during creation of a mask to be used in an optical lithography process for manufacturing an integrated circuit. 
     2. Related Art 
     Recent advances in integrated circuit technology have largely been accomplished by decreasing the feature size of circuit elements on a semiconductor chip. As the feature size of these circuit elements continues to decrease, circuit designers are forced to deal with problems that arise as a consequence of the optical lithography process that is typically used to manufacture integrated circuits. This optical lithography process generally begins with the formation of a photoresist layer on the surface of a semiconductor wafer. A mask composed of opaque regions, which are generally formed of chrome, and light-transmissive clear regions, which are generally formed of quartz, is then positioned over this photo resist layer coated wafer. (Note that the term “mask” as used in this specification is meant to include the term “retical.”) Light is then shone on the mask from a visible light source or an ultraviolet light source. 
     This light is generally reduced and focussed through an optical system that contains a number of lenses, filters and mirrors. The light passes through the clear regions of the mask and exposes the underlying photoresist layer. At the same time, the light is blocked by opaque regions of mask, leaving underlying portions of the photoresist layer unexposed. 
     The exposed photoresist layer is then developed, typically through chemical removal of the exposed/non-exposed regions of the photoresist layer. The end result is a semiconductor wafer with a photoresist layer having a desired pattern. This pattern can then be used for etching underlying regions of the wafer. 
     One problem in performing the optical lithography process arises from conflicts between phase shifters. Phase shifters are often incorporated into a mask in order to achieve line widths that are smaller than the wavelength of the light that is used to expose the photoresist layer through the mask. During phase shifting, destructive interference caused by two adjacent clear areas on a mask is used to create an unexposed area on the photoresist layer. This is accomplished by exploiting the fact that light passing through a mask&#39;s clear regions exhibits a wave characteristic having a phase that is a function of the distance the light travels through the mask material. By placing two clear areas adjacent to each other on the mask, one of thickness t 1  and the other of thickness t 2 , one can obtain a desired unexposed area on the underlying photoresist layer caused by interference. By varying the thickness t 1  and t 2  appropriately, the light exiting the material of thickness t 2  is 180 degrees out of phase with the light exiting the material of thickness t 1 . Phase shifting is described in more detail in U.S. Pat. No. 5,858,580, entitled “Phase Shifting Circuit Manufacture Method and Apparatus,” by inventors Yao-Ting Wang and Yagyensh C. Pati, filed Sep. 17, 1997 and issued Jan. 12, 1999, which is hereby incorporated by reference. 
     As can be seen in FIG. 1A, when two phase shifters are located in close proximity to each other, conflicts can arise. In FIG. 1A, a first phase shifter comprising a zero-degree phase region  102  and a 180-degree phase region  104  is used to produce a small line width in a gate region  103  of polysilicon line  101 . Similarly, a second phase shifter comprising a zero-degree phase region  114  and a 180-degree phase region  112  is used to produce a small line width in a gate region  113  of polysilicon line  111 . 
     Unfortunately, when the first phase shifter and the second phase shifter are located in close proximity to each other, conflicts can arise between them as is illustrated in FIG.  1 A. In existing systems, this can cause the system to halt with a phase conflict error. 
     What is needed is a method and an apparatus for resolving conflicts between phase shifters. 
     Another problem arises during the process of generating phase shifters and associated trim. A phase shifter located on a phase shifting mask will often be generated along with associated trim located on a second mask. During exposure of the second mask, this trim protects a region that is to be exposed by the phase shifter during exposure of the phase shifting mask. Unfortunately, design rules typically cause patches to be added to the shifter and to the associated trim and these patches can cause conflicts with other features on the masks. Note that in existing systems, phase shift regions cannot overlap with field polysilicon. 
     What is needed is a method and an apparatus for generating phase shifters and trim that satisfy design rules while minimizing conflicts with other mask features. 
     SUMMARY 
     One embodiment of the invention provides a system that uses phase shifter cutbacks to resolve conflicts between phase shifters during creation of a mask to be used in an optical lithography process for manufacturing an integrated circuit. The system works by locating a plurality of phase shifters, including a first phase shifter and a second phase shifter, on a phase shifting mask, and then identifying a conflict area wherein a conflict is likely to occur between the first phase shifter and the second phase shifter on the phase shifting mask. The system resolves this conflict by cutting back one or both of the first phase shifter and the second phase shifter, so that the first phase shifter and the second phase shifter do not interfere with each other in the conflict area. 
     In one embodiment of the invention, identifying the conflict area involves expanding the size of each shifter in the plurality of phase shifters, so that each shifter covers an area defined by a halo surrounding each shifter. The system then retrieves environment information for each shifter by examining the area covered by each expanded shifter. This enables the system to obtain inter-cell environment information, such as the location of inter-cell polysilicon features. The system uses this environment information not only to identify conflict areas between phase shifters but also to produce better shifter shapes. Finally, the system restores the size of each shifter. As a result of the above-described process, the system can produce better shifter shapes, which can improve yield and manufacturability. 
     In one embodiment of the present invention, the system uses a rule-based shape generation process known as “priority placement” to generate shapes for special cases. 
     In one embodiment of the invention, cutting back one or both of the first phase shifter and the second phase shifter involves reducing the size of the first phase shifter and/or the second phase shifter so that the first phase shifter and the second phase shifter do not interfere with each other in the conflict area. 
     In one embodiment of the invention, identifying the conflict area involves looking for conflicts between phase shifters located in different predefined cells, wherein no conflicts are assumed to exist between phase shifters within the same predefined cell. 
     In one embodiment of the invention, identifying the conflict area involves looking for conflicts between phase shifters located in the same predefined cell. 
     In one embodiment of the invention, resolving the conflict involves cutting back a shifter endcap extension for the first phase shifter and/or the second phase shifter. 
     In one embodiment of the invention, resolving the conflict involves unifying portions of the first phase shifter and the second phase shifter. 
     In one embodiment of the invention, the system additionally generates a third phase shifter within the phase shifting mask, wherein generating the third phase shifter involves ensuring that design rules are satisfied in defining dimensions for the third phase shifter. After this third phase shifter is generated, the system generates trim within a second mask to be used in conjunction with the phase shifting mask, by deriving the trim from the previously-defined dimensions of the third phase shifter while ensuring that design rules are satisfied. 
    
    
     BRIEF DESCRIPTION OF THE FIGURES 
     FIG. 1A illustrates two conflicting phase shifters. 
     FIG. 1B illustrates the use of cutbacks to resolve phase shifter conflicts. 
     FIG. 1C illustrates the use of cutbacks along with phase shifter unification to resolve phase shifter conflicts in accordance with an embodiment of the invention. 
     FIG. 2 illustrates another use of cutbacks to resolve a phase shifter conflict in accordance with an embodiment of the invention. 
     FIG. 3 is a flow chart illustrating the process of generating phase shifter cutbacks in accordance with an embodiment of the invention. 
     FIG. 4A is a flow chart illustrating the wafer fabrication process in accordance with an embodiment of the invention. 
     FIG. 4B is a flow chart illustrating the process of generating shifters and associated trim in accordance with an embodiment of the invention. 
     FIG. 5A illustrates patch generation to satisfy design rules. 
     FIG. 5B illustrates generation of a reduced shifter and associated trim to satisfy design rules in accordance with an embodiment of the invention. 
     FIG. 6A illustrates a shifter in close proximity to a wire in accordance with an embodiment of the invention. 
     FIG. 6B illustrates the use of shifter and trim patches to satisfy design rules. 
     FIG. 6C illustrates the generation of a reduced shifter and associated trim to satisfy design rules. 
     FIG. 7A illustrates a phase shifter in close proximity to a wire in accordance with an embodiment of the invention. 
     FIG. 7B illustrates the use of shifter and trim patches to satisfy design rules. 
     FIG. 7C illustrates the generation of a phase shifter in accordance with an embodiment of the invention. 
     FIG. 7D illustrates the generation of trim in accordance with an embodiment of the invention. 
     FIG. 8 is a flow chart illustrating the process of generating a phase shifter along with associated trim in accordance with an embodiment of the invention. 
     FIG. 9A illustrates a phase shifter with a non-Manhattan geometry in accordance with an embodiment of the invention. 
     FIG. 9B illustrates the use of a trim cutback to satisfy design rules in accordance with an embodiment of the invention. 
     FIG. 9C illustrates the use of trim and shifter extensions to satisfy design rules in accordance with an embodiment of the invention. 
    
    
     DETAILED DESCRIPTION 
     Using Cutbacks to Resolve Phase Shifter Conflicts 
     FIG. 1A illustrates two conflicting phase shifters in accordance with an embodiment of the invention. As was mentioned above, a first phase shifter comprising a zero-degree phase region  102  and a 180-degree phase region  104  is used to produce a small line width in a gate region  103  of a polysilicon line  101 . Similarly, a second phase shifter comprising a zero-degree phase region  114  and a 180-degree phase region  112  is used to produce a small line width in a gate region  113  of a polysilicon line  111 . Unfortunately, the first phase shifter and the second phase shifter are located in close proximity to each other, creating a conflict between them. 
     FIG. 1B illustrates the use of cutbacks to resolve phase shifter conflicts in accordance with an embodiment of the invention. Note in the first phase shifter, the zero-degree phase region  102  and the 180-degree phase region  104  have been cutback to remove the shifter endcap extension that extends past the endcap of the associated transistor. Similarly, in the second phase shifter, the zero-degree phase region  114  and the 180-degree phase region  112  have been cut back to remove the shifter endcap extension. Also note that these cutbacks are performed automatically by a computer application as opposed to being performed manually by a human being through a design editor. 
     FIG. 1C illustrates the use of cutbacks along with phase shifter unification to resolve phase shifter conflicts in accordance with an embodiment of the invention. In FIG. 1C, 180-degree phase region  104  is unified with 180-degree phase region  112 . This is possible because they can be unified with a shifter extension  116 , which has a width that is larger than a specified minimum shifter width. 
     FIG. 2 illustrates another use of cutbacks to resolve a phase shifter conflict in accordance with an embodiment of the invention. In this example, a first shifter  202  conflicts with a second shifter comprised of 180-degree phase region  204  and zero-degree phase region  206 . The second shifter also conflicts with a third phase shifter comprised of 180-degree phase region  208  and zero-degree phase region  207 . 
     In this case, the conflicts can be resolved by cutting back the endcap extensions for the second transistor and the third transistor, while cutting away a portion of the first shifter  202  to accommodate the remaining endcap associated with the second phase shifter. 
     Process of Generating Phase Shifter Cutbacks 
     FIG. 3 is a flow chart illustrating the process of generating phase shifter cutbacks in accordance with an embodiment of the invention. The system first locates phase shifters within a mask that is used to create the integrated circuit (step  302 ). Next, the system expands the size of each phase shifter to a new expanded size defined by a halo around the original phase shifter (step  306 ). The system subsequently retrieves environment information for each of the expanded phase shifters. This environment information is used to identify potential conflicts between phase shifters (step  308 ). Next, the system restores the phase shifters back to their original size (step  310 ). 
     Finally, the system performs cutbacks on phase shifters to resolve conflicts as is illustrated in FIGS. 1B, FIG.  1 C and FIG. 2 (step  312 ). This can be done by cutback both or only one of the phase shifters while ensuring that both the phase shifters are of sufficient size to operate on the gate of the associated transistor. 
     Note that by using the halo the problem area that needs to be considered can be limited, which improves performance of the system. Moreover, the system may be able to solve the problem by performing manipulations within the halo. 
     Also note that the present invention is not meant to be limited to the use of halos. Other techniques can be used to identify potential conflicts between phase shifters. For example, scan line techniques can be used, or techniques that extend projections from shifter corners. 
     Moreover, note that a phase shifter can generally be of many different sizes. However, an exemplary phase shifter can be 400 nanometers in width and 600-700 nanometers in length. Such a phase shifter can be used for example to cut a 180 nanometer wide polysilicon line down to a width of 100 nanometers. 
     Wafer Fabrication Process 
     FIG. 4A is a flow chart illustrating the wafer fabrication process in accordance with an embodiment of the invention. The system starts by applying the resist coating to the top surface of a wafer (step  402 ). Next, the system bakes the resist layer (step  404 ). The system then positions the first mask over the photoresist layer (step  406 ), and then exposes the photoresist layer through the first mask (step  408 ). Next, the system positions the second mask over the photoresist layer (step  410 ), and then exposes the photoresist layer through the second mask (step  412 ). The system then bakes the wafer again (step  414 ) before developing the photoresist layer (step  416 ). Next, either a chemical etching or ion implantation step takes place (step  418 ) before the photoresist layer is removed (step  420 ). Finally, a new layer of material can be added and the process can be repeated for the new layer (step  422 ). 
     Generating Phase Shifters and Associated Trim 
     FIG. 4B is a flow chart illustrating the process of generating shifters and associated trim in accordance with an embodiment of the invention. Note that the system can operate on a hierarchical design that is specified in a standard hierarchical format, such as GDSII stream format. In this type of format, a design is specified in terms of cells, within themselves can be specified in terms of sub-cells. 
     During operation, the system starts with an optional pre-processing step in which any number of pre-processing operations can take place (step  430 ). This is followed by a push diffusion step, which pushes diffusion onto associated polysilicon lines, even if the diffusion and polysilicon lines are defined within different cells (step  434 ). Next, the system identifies any gates that are formed between polysilicon and diffusion regions (step  436 ). Note that there may also be an additional step at this point to handle larger composite gates that contain more than a few transistors, such as an exclusive-OR gate. 
     Next, the system places shifters and associated trim on masks to form narrow polysilicon gates (step  438 ). At this point, the system performs intra-cell coloring to detect conflicts between phase shifters and other mask features (step  440 ). The system also performs inter-cell coloring to detect conflicts between cells (step  442 ). Note that these coloring operations can include performing corrective actions, such as generating cutbacks, to resolve the coloring problems. The system may also use priority placement to produce better shapes, which can improve yield and manufacturability. Priority placement uses rule-based shape generation to handle special cases. Finally, the system can perform a compression operation in order to reuse cells if possible (step  444 ). 
     FIG. 5A illustrates the use of patches to satisfy design rules. In this example, a shifter on a first mask contains a zero-degree phase region  502  and a 180-degree phase region  504 , which create a region of destructive interference to form a gate  509 . At the same time this phase shifter is being generated, the system also generates trim regions  506  and  508  on a second mask to protect the gate region that is to be exposed by the phase shifter in the first mask. 
     Unfortunately, zero-degree phase region  502  becomes narrower than a minimum width at location  501 . This causes the system to add a shifter patch  510  to increase zero-degree phase region  502  up to the minimum width. However, adding patch  510  can create coloring problems in adjacent features. 
     FIG. 5B illustrates generation of a reduced shifter and associated trim to satisfy design rules in accordance with an embodiment of the invention. In this example, instead of adding a patch, the size of zero-degree phase region  502  is reduced, and the associated trim region  506 , which is generated later, is also reduced. Note that this reduced shape satisfies design rules without creating coloring problems. 
     FIG. 6A illustrates a shifter in close proximity to a wire in accordance with an embodiment of the invention. Note that the separation between wire  601  and the phase shifter comprised of zero-degree phase region  602  and 180-degree phase region  604  violates a design rule. This can be remedied by adding shifter patch  611  and trim patch  610  as is illustrates in FIG.  6 B. However, adding these patches leads to potential coloring conflicts. 
     Some of these coloring conflicts can be avoided by stopping shifter  611  at wire  601 , and then subsequently generating trim patch  610  so that trim patch  610  is covered by shifter patch  611  (see FIG.  6 C). 
     FIG. 7A illustrates a shifter comprised of 180-degree phase region  702  and zero-degree clear region  704  in close proximity to a wire  701  in accordance with an embodiment of the invention. In order to satisfy design rules regarding minimum spacing between trim  703  and wire  701 , shifter patch  709  and trim patch  708  can be added to the shifter. However, these patches can lead to additional coloring conflicts with nearby features (see FIG.  7 B). 
     These coloring problems can be avoided by first generating the shifter as is illustrated in FIG. 7C, and then generating trim that is covered by the shifter and that satisfies the design rule that specifies a minimum spacing between trim  703  and wire  701  (see FIG.  7 D). 
     FIG. 8 is a flow chart illustrating the process of generating a shifter along with associated trim in accordance with an embodiment of the invention. The system starts by identifying features to be created using a phase shifter (step  802 ). Next, the system generates a phase shifter on a first mask while ensuring that design rules are satisfied (step  804 ). Note that these design rules can be applied within a cell (intra-cell) in the design, or between cells (inter-cell). 
     After the dimensions of the phase shifter are defined, the system generates associated trim on a second mask using the pre-specified dimensions of the phase shifter and at the same time ensuring that design rules are satisfied (step  806 ). 
     Note that these design rules can include rules to ensure that there exists a minimum spacing between trim and another wire in the integrated circuit, as well as rules to ensure that trim is covered by a phase shifter and to ensure that the phase shifter extends a minimum distance past the trim except where the trim is connected to a wire. 
     Note that the design rules can be satisfied by cutting and/or patching portions of the phase shifter and associated trim. The system may also patch features in a way that violates design rules, and may then cut these features so that design rules are satisfied. 
     Non-Manhattan Geometries 
     Although the present invention is discussed with reference to Manhattan layouts, it is not meant to be limited in this way. For example, FIG. 9A illustrates a phase shifter in a non-Manhattan layout in accordance with an embodiment of the invention. Within this non-Manhattan layout, FIG. 9B illustrates the use of a trim cutback to satisfy design rules in accordance with an embodiment of the invention. Alternatively, FIG. 9C illustrates the use of trim and shifter extensions to satisfy design rules in accordance with an embodiment of the invention. 
     Note the above-described techniques can be adapted for a variety of lithographic processes, including deep and extreme ultraviolet and X-ray lithographic processes. 
     The preceding description is presented to enable any person skilled in the art to make and use the invention, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the invention. Thus, the invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein. 
     The data structures and code described in this detailed description are typically stored on a computer-readable storage medium, which may be any device or medium that can store code and/or data for use by a computer system. This includes, but is not limited to, magnetic and optical storage devices such as disk drives, magnetic tape, CDs (compact discs) and DVDs (digital versatile discs or digital video discs), and computer instruction signals embodied in a transmission medium (with or without a carrier wave upon which the signals are modulated). For example, the transmission medium may include a communications network, such as the Internet. 
     The foregoing descriptions of embodiments of the invention have been presented for purposes of illustration and description only. They are not intended to be exhaustive or to limit the invention to the forms disclosed. Accordingly, many modifications and variations will be apparent to practitioners skilled in the art. 
     Additionally, the above disclosure is not intended to limit the invention. The scope of the invention is defined by the appended claims.