Abstract:
A method includes removing a portion of a substrate to define an isolation trench; forming a first dielectric layer on exposed surfaces of the substrate in the trench; forming a second dielectric layer on at least the first dielectric layer, the second dielectric layer containing a different dielectric material than the first dielectric layer; depositing a third dielectric layer to fill the trench; removing an upper portion of the third dielectric layer from the trench and leaving a lower portion covering a portion of the second dielectric layer; oxidizing the lower portion of the third dielectric layer after removing the upper portion; removing an exposed portion of the second dielectric layer from the trench, thereby exposing a portion of the first dielectric layer; and forming a fourth dielectric layer in the trench covering the exposed portion of the first dielectric layer.

Description:
RELATED APPLICATIONS  
       [0001]     This is a continuation in part application of U.S. patent application Ser. No. 10/878,805, filed Jun. 28, 2004, titled “ISOLATION TRENCHES FOR MEMORY DEVICES,” which application is commonly assigned, the entire contents of which are incorporated herein by reference. 
     
    
     TECHNICAL FIELD OF THE INVENTION  
       [0002]     The present invention relates generally to memory devices and in particular the present invention relates to isolation trenches for memory devices.  
       BACKGROUND OF THE INVENTION  
       [0003]     Memory devices are typically provided as internal storage areas in computers. The term memory identifies data storage that comes in the form of integrated circuit chips. In general, memory devices contain an array of memory cells for storing data, and row and column decoder circuits coupled to the array of memory cells for accessing the array of memory cells in response to an external address.  
         [0004]     One type of memory is a non-volatile memory known as flash memory. A flash memory is a type of EEPROM (electrically-erasable programmable read-only memory) that can be erased and reprogrammed in blocks. Many modern personal computers (PCs) have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in wireless electronic devices because it enables the manufacturer to support new communication protocols as they become standardized and to provide the ability to remotely upgrade the device for enhanced features.  
         [0005]     A typical flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating-gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed on an individual basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge on the floating gate.  
         [0006]     Memory devices are typically formed on semiconductor substrates using semiconductor fabrication methods. The array of memory cells is disposed on the substrate. Isolation trenches formed in the substrate within the array and filled with a dielectric, e.g., shallow trench isolation (STI), provide voltage isolation on the memory array by acting to prevent extraneous current flow through the substrate between the memory cells. The isolation trenches are often filled using a physical deposition process, e.g., with high-density plasma (HDP) oxides. However, the spacing requirements for flash memory arrays often require the isolation trenches to have relatively narrow widths, resulting in large aspect (or trench-depth-to-trench-width) ratios. The large aspect ratios often cause voids to form within the dielectric while filling these trenches using physical sputtering processes.  
         [0007]     Filling the trenches with spin-on-dielectrics (SODs) can reduce the formation of voids within the dielectric during filling. However, spin-on-dielectrics usually have to be cured (or annealed) after they are disposed within the trenches, e.g., using a steam-oxidation process that can result in unwanted oxidation of the substrate and of layers of the memory cells overlying the substrate. To protect against such oxidation, the trenches can be lined with a nitride liner prior to filling the trenches with a spin-on-dielectric. One problem with nitride liners is that they can store trapped charges that can adversely affect the reliability of the memory cells and thus the memory device.  
         [0008]     For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternatives to existing trench-fill methods.  
       SUMMARY  
       [0009]     The above-mentioned problems with filling isolation trenches and other problems are addressed by the present invention and will be understood by reading and studying the following specification.  
         [0010]     For one embodiment, the invention provides a method of forming a portion of an integrated circuit device contained on a semiconductor substrate. The method includes removing a portion of the substrate to define an isolation trench and forming a first dielectric layer on exposed surfaces of the substrate in the trench. Forming a second dielectric layer on at least the first dielectric layer, where the second dielectric layer contains a different dielectric material than the first dielectric layer is included in the method. The method includes depositing a third dielectric layer to fill the trench, removing an upper portion of the third dielectric layer from the trench and leaving a lower portion covering a portion of the second dielectric layer, and oxidizing the lower portion of the third dielectric layer after removing the upper portion. Removing an exposed portion of the second dielectric layer from the trench, thereby exposing a portion of the first dielectric layer is included in the method, as is forming a fourth dielectric layer in the trench covering the exposed portion of the first dielectric layer.  
         [0011]     For another embodiment, the invention provides a method of forming a portion of an integrated circuit device contained on a semiconductor substrate. The method includes removing a portion of the substrate to define an isolation trench and forming a first dielectric layer on exposed surfaces of the substrate in the trench. Forming a second dielectric layer on at least the first dielectric layer, where the second dielectric layer contains a different dielectric material than the first dielectric layer is included in the method. The method includes partially filling the trench with a silicon rich oxide material, oxidizing the silicon rich oxide material, causing surplus silicon of the silicon rich oxide material to form silicon oxide. Removing an exposed portion of the second dielectric layer from the trench, thereby exposing a portion of the first dielectric layer is included in the method, as is forming a third dielectric layer in the trench covering the exposed portion of the first dielectric layer.  
         [0012]     Further embodiments of the invention include methods and apparatus of varying scope.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]      FIG. 1  is a simplified block diagram of a memory system, according to an embodiment of the invention.  
         [0014]      FIGS. 2A-2H  are cross-sectional views of a portion of a memory device during various stages of fabrication, according to another embodiment of the invention.  
         [0015]      FIG. 3  is a cross-sectional view of a portion of a memory device during a stage of fabrication, according to yet another embodiment of the invention.  
         [0016]      FIGS. 4A-4E  are cross-sectional views of a portion of a memory device during various stages of fabrication, according to still another embodiment of the invention. 
     
    
     DETAILED DESCRIPTION  
       [0017]     In the following detailed description of the invention, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The term wafer or substrate used in the following description includes any base semiconductor structure. Both are to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of a silicon supported by a base semiconductor structure, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a wafer or substrate in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure, and terms wafer or substrate include the underlying layers containing such regions/junctions. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and equivalents thereof.  
         [0018]      FIG. 1  is a simplified block diagram of a memory system  100 , according to an embodiment of the invention. Memory system  100  includes an integrated circuit memory device  102 , such as a flash memory device, e.g., a NAND or NOR memory device, a DRAM, an SDRAM, etc., that includes an array of memory cells  104  and a region peripheral to memory array  104  that includes an address decoder  106 , row access circuitry  108 , column access circuitry  110 , control circuitry  112 , Input/Output (I/O) circuitry  114 , and an address buffer  116 . The row access circuitry  108  and column access circuitry  110  may include high-voltage circuitry, such as high-voltage pumps. Memory system  100  includes an external microprocessor  120 , or memory controller, electrically connected to memory device  102  for memory accessing as part of an electronic system. The memory device  102  receives control signals from the processor  120  over a control link  122 . The memory cells are used to store data that are accessed via a data (DQ) link  124 . Address signals are received via an address link  126  that are decoded at address decoder  106  to access the memory array  104 . Address buffer circuit  116  latches the address signals. The memory cells are accessed in response to the control signals and the address signals. It will be appreciated by those skilled in the art that additional circuitry and control signals can be provided, and that the memory device of  FIG. 1  has been simplified to help focus on the invention.  
         [0019]     The memory array  104  includes memory cells arranged in row and column fashion. For one embodiment, the memory cells are flash memory cells that include a floating-gate field-effect transistor capable of holding a charge. The cells may be grouped into blocks. Each of the cells within a block can be electrically programmed on an individual basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation.  
         [0020]     For one embodiment, memory array  104  is a NOR flash memory array. A control gate of each memory cell of a row of the array is connected to a word line, and a drain region of each memory cell of a column of the array is connected to a bit line. The memory array for NOR flash memory devices is accessed by row access circuitry, such as the row access circuitry  108  of memory device  102 , activating a row of floating gate memory cells by selecting the word line connected to their control gates. The row of selected memory cells then place their data values on the column bit lines by flowing a differing current, depending upon their programmed states, from a connected source line to the connected column bit lines.  
         [0021]     For another embodiment, memory array  104  is a NAND flash memory array also arranged such that the control gate of each memory cell of a row of the array is connected to a word line. However, each memory cell is not directly connected to a column bit line by its drain region. Instead, the memory cells of the array are arranged together in strings (often termed NAND strings), e.g., of 32 each, with the memory cells connected together in series, source to drain, between a source line and a column bit line. The memory array for NAND flash memory devices is then accessed by row access circuitry, such as the row access circuitry  108  of memory device  102 , activating a row of memory cells by selecting the word line connected to a control gate of a memory cell. In addition, the word lines connected to the control gates of unselected memory cells of each string are driven to operate the unselected memory cells of each string as pass transistors, so that they pass current in a manner that is unrestricted by their stored data values. Current then flows from the source line to the column bit line through each series connected string, restricted only by the selected memory cells of each string. This places the current-encoded data values of the row of selected memory cells on the column bit lines.  
         [0022]      FIGS. 2A-2H  are cross-sectional views of a portion of a memory device, such as a portion of the memory device  102 , during various stages of fabrication, according to another embodiment of the invention.  FIG. 2A  depicts the portion of the memory device after several processing steps have occurred. Formation of the structure depicted in  FIG. 2A  is well known and will not be detailed herein.  
         [0023]     In general, the structure of  FIG. 2A  is formed by forming a first dielectric layer  202  on a substrate  200 , e.g., of silicon or the like. For one embodiment, the first dielectric layer  202  is a gate dielectric layer (or tunnel dielectric layer), such as a tunnel oxide layer. A conductive layer  204 , e.g., a layer of doped polysilicon, is formed on the first dielectric layer  202 , and a hard mask layer  206  is formed on the conductive layer  204 . The mask layer  206  can be a second dielectric layer, such as a nitride layer, e.g., a silicon nitride (Si 3 N 4 ) layer.  
         [0024]     Trenches  210  are subsequently formed through the mask layer  206 , the conductive layer  204 , and the first dielectric layer  202  and extend into substrate  200 . This can be accomplished by patterning the mask layer  206  and etching. A third dielectric layer  212  may then be formed on portions of the substrate  200  exposed by the trenches  210  so as to line the portion of trenches  210  formed in substrate  200 .  
         [0025]     A fourth dielectric layer  220 , such as a nitride layer, e.g., a silicon nitride layer, is formed on the structure of  FIG. 2A  in  FIG. 2B , such as by blanket deposition, and acts as an oxidation barrier layer for one embodiment. Specifically, the fourth dielectric layer  220  is formed on an upper surface of mask layer  206  and on portions of the mask layer  206 , the conductive layer  204 , and the first dielectric layer  202  through which trenches  210  pass. The fourth dielectric layer  220  is also formed on the third dielectric layer  212 . In this way, the fourth dielectric layer  220  lines trenches  210 . For one embodiment, the third dielectric layer  212  acts to provide adhesion between substrate  200  and the fourth dielectric layer  220  and acts as a stress release layer for relieving stresses that would otherwise form between substrate  200  and the fourth dielectric layer  220 . For another embodiment, the third dielectric layer  212  is a pad oxide layer and can be a thermal oxide layer. For another embodiment, the third dielectric layer  212  is, for example, a layer of deposited silicon dioxide (SiO 2 ).  
         [0026]     A fifth dielectric layer  230  is deposited within each of the trenches  210  on the fourth dielectric layer  220  in  FIG. 2C  to either fill or partially fill trenches  210 . For one embodiment, the fifth dielectric layer  230  is spin-on dielectric (SOD) material, such as a spin-on glass, hydrogen silsesquioxane (HSQ), hexamethyldisiloxane, polysilazane, octamethyltrisiloxane, etc. The fifth dielectric layer  230  is then cured (or annealed), e.g., using a steam-oxidation process, if necessary. For one embodiment, the fourth dielectric layer  204  acts to prevent oxidation of the substrate  200  and the conductive layer  204  during curing.  
         [0027]     For one embodiment, the fifth dielectric layer  230  is formed as shown in  FIG. 3 . Each of the trenches  210  is partially filled with a silicon-rich oxide material  330 . The silicon-rich oxide material  330  is then oxidized, e.g., using a steam oxidation process, causing the surplus silicon to form silicon oxide that expands. The expansion of the silicon oxide acts to exert a compressive stress on adjacent silicon, which has been shown to improve carrier mobility and thus transistor gain control. For one embodiment, the expansion is achieved when the silicon-rich oxide material  330  has a molar ratio of silicon to oxygen within a range of about 1:1 to about 2:1. For another embodiment, the ratio may be adjusted, dependent upon on the steam and temperature conditions used for the steam oxidation, in order to obtain a desired degree of expansion or resulting compressive stress.  
         [0028]     In  FIG. 2D , a portion of the fifth dielectric layer  230  is removed, such as by etching in an etch-back process, so that an upper surface of the fifth dielectric layer  230  is recessed within the respective trenches  210 , e.g., below an upper surface of substrate  200 , exposing a portion of the fourth dielectric layer  220  lining each of trenches  210 . For embodiments where fifth dielectric layer  230  is a polysilazane-based SOD material, the etch-back process for removing the portion of the fifth dielectric layer  230  includes using a mixture of deionized water and ammonium hydroxide, at a temperature in the range from about 20° C. to about 90° C., preferably at about 55° C. For other embodiments where the fifth dielectric layer  230  is spin-on dielectric (SOD) material, e.g., polysilazane, the fifth dielectric layer  230  is cured, e.g., using the steam-oxidation process, after the removal of the portion of the fifth dielectric layer  230 , i.e., is performed for the structure of  FIG. 2D .  
         [0029]     A portion of the fourth dielectric layer  220  is selectively removed in  FIG. 2E , e.g., using a controlled wet etch, to a level of the upper surface of the fifth dielectric layer  230  such that a remaining portion of the fourth dielectric layer  220  is interposed between the fifth dielectric layer  230  and the third dielectric layer  212 . That is, the fourth dielectric layer  220  is removed from an upper surface of the mask layer  206 , and the exposed portion of the fourth dielectric layer  220  located within each of trenches  210  is removed. This exposes the upper surface of the mask layer  206 , the portions of the mask layer  206 , the conductive layer  204 , and the first dielectric layer  202  through which trenches  210  pass, and a portion of the third dielectric layer  212  lying between the upper surface of substrate  200  and the upper surface of the fifth dielectric layer. The remaining portions of the fourth dielectric layer  220  and the fifth dielectric layer  230  form a first dielectric plug  232  that fills a lower portion of trenches  210 , as shown in  FIG. 2E , having an upper surface that is recessed below the upper surface of the substrate  200 . For another embodiment, the fourth dielectric layer  220  is removed to a level of an upper surface of the oxidized silicon-rich oxide material  330  of  FIG. 3  to form a plug similar to first dielectric plug  232  (not shown in  FIG. 3 ).  
         [0030]     In  FIG. 2F , a sixth dielectric layer  240  is blanket deposited over the structure of  FIG. 2E  and fills an unfilled portion of each of trenches  210 . Specifically, the sixth dielectric layer  240  is deposited on the exposed upper surface of the mask layer  206 , on the exposed portions of the mask layer  206 , the conductive layer  204 , and the first dielectric layer  202  through which trenches  210  pass, on the portion of the third dielectric layer  212  lying between the upper surface of substrate  200  and the upper surface of the fifth dielectric layer, and on the first dielectric plug  232 . For one embodiment, the sixth dielectric layer  240  is of a high-density-plasma (HDP) dielectric material, such as a high-density-plasma (HDP) oxide. Note that the first dielectric plugs  232  reduce the remaining depths of trenches  210  and thus their aspect ratios for the deposition of the sixth dielectric layer  240 . The reduced aspect ratios of trenches  210  act to reduce the formation of voids when depositing the sixth dielectric layer  240  within the unfilled portions of trenches  210 . For another embodiment, in a similar fashion, the sixth dielectric layer  240  is formed over the structure of  FIG. 3  after the removal of the fourth dielectric layer  220  to the level of an upper surface of the oxidized silicon-rich oxide material  330  (not shown in  FIG. 3 ).  
         [0031]     A portion of the sixth dielectric layer  240  is removed from the structure of  FIG. 2F  in  FIG. 2G , e.g., using chemical mechanical polishing (CMP). That is, the sixth dielectric layer  240  is removed so that the upper surface of the mask layer  206  is exposed and so that an upper surface of the sixth dielectric layer  240  within each of trenches  210  is substantially flush with the upper surface of the mask layer  206 . Note that the portion of the sixth dielectric layer  240  within each of the trenches  210  forms a second dielectric plug  242  that passes through the mask layer  206 , the conductive layer  204 , the first conductive layer  202 , extends into the substrate  200 , and terminates at the first conductive plug  232 . The third dielectric layer  212  is interposed between the portion of the second dielectric plug  242  and the substrate  200  and the first dielectric plug  232  and the substrate  200 . Note that a structure similar to that of  FIG. 2H  may be formed from the structure of  FIG. 3  after the removal of the fourth dielectric layer  220  and the formation of sixth dielectric layer  240 , with the oxidized silicon-rich oxide material  330  replacing the fifth dielectric layer  230 .  
         [0032]     Note that the fourth dielectric layer  220  is located in the lower portion of each of trenches  210  and thus away from the layers disposed on the upper surface of substrate  200  that can be used to form memory cells. This acts to reduce problems associated with the fourth dielectric layer  220  storing trapped charges, especially when the fourth dielectric layer  220  is of nitride, that can adversely affect the reliability of the memory cells and thus the memory device.  
         [0033]     Mask  206  is subsequently removed to expose the conductive layer  204 . A seventh dielectric layer  250 , e.g., such as a layer of silicon oxide, a nitride, an oxynitride, an oxide-nitride-oxide (ONO) layer, etc., is then formed on the exposed conductive layer  204 . A conductive layer  260 , such as a doped polysilicon layer, a metal layer, e.g., refractory metal layer, a metal containing layer, e.g., a metal silicide layer, or the like, is formed on the seventh dielectric layer  250 , as shown in  FIG. 2H . The conductive layer  260  may include one or more conductive materials or conductive layers, a metal or metal containing layer disposed on a polysilicon layer, etc. For another embodiment, conductive layers  204  and  260  respectively form a floating gate and a control gate (or word line) of memory cells of a memory array, such as memory array  104  of  FIG. 1 , and the seventh dielectric layer  250  forms an intergate dielectric layer that separates the floating gate and the control gate. Source/drain regions are also formed in a portion of substrate  200  not shown in  FIG. 2G  as a part of the memory array. For one embodiment, conductive layer  204  is extended to improve the coupling of the floating gate. The trenches  210  filled with dielectric materials, as described above, act to prevent extraneous current flow through the substrate between the memory cells.  
         [0034]     The components located in the region peripheral to memory array  104  of  FIG. 1  (hereinafter the periphery) are also formed on the substrate  200 . For one embodiment the periphery may include address decoder  106 , row access circuitry  108 , column access circuitry  110 , control circuitry  112 , Input/Output (I/O) circuitry  114 , and address buffer  116  of memory device  102 , as shown in  FIG. 1 . For another embodiment, the row access circuitry  108  and column access circuitry  110  may include high-voltage circuitry, such as high-voltage pumps. For some embodiments, the periphery includes passive elements, such as capacitors, and active elements, such as transistors, e.g., field-effect transistors.  
         [0035]     For some embodiments, a memory array and a periphery are formed overlying the substrate  200 , as shown in  FIGS. 4A through 4E  at different stages of fabrication, according to another embodiment of the invention. The structure of  FIG. 4A , for one embodiment, is formed essentially as described for  FIGS. 2A-2B . That is, the first dielectric layer  202 , the conductive layer  204 , and the mask layer  206  are formed overlying substrate  200 ; trenches  210  are formed through the mask layer  206 , the conductive layer  204 , and the first dielectric layer  202  such that trenches  210  extend into substrate  200 ; the portion of trenches  210  extending into substrate  200  is lined with the third dielectric layer  212 ; and the fourth dielectric layer  220  is formed overlying the first dielectric layer  202 , the conductive layer  204 , the mask layer  206 , and the third dielectric layer  212 . For one embodiment, the trenches  210  in the periphery are deeper and/or wider than the trenches  210  in the array and thus have a larger volume than the trenches  210  in the array, as shown in  FIG. 4A .  
         [0036]     The fifth dielectric layer  230  is deposited overlying the structure of  FIG. 4A  in  FIG. 4B  so that dielectric material of the fifth dielectric layer  230  overfills trenches  210 . For the embodiment where the trenches  210  in the periphery have a larger volume than those in the array, more dielectric material is required to fill the trenches  210  of the periphery. Therefore, the trenches  210  of the array are filled more quickly than the trenches  210  of the periphery, and continued deposition of the dielectric material of the fifth dielectric layer  230  overfills the trenches  210  of the periphery. This, coupled with the fluid properties of the dielectric material, causes a step  410  to form in the fifth dielectric layer  230  between the array and the periphery, as shown in  FIG. 4B . In  FIG. 4C , a portion of the fifth dielectric layer  230  is removed, e.g., by CMP, so that step  410  is removed and an upper surface of the fifth dielectric layer  230  is substantially level, i.e., so that the upper surface of the fifth dielectric layer  230  in the periphery and the upper surface of the fifth dielectric layer  230  in the array are substantially co-planer. For one embodiment, the removal of the fifth dielectric layer  230  proceeds until an upper surface of the fifth dielectric layer  230  is substantially flush with an upper surface of the fourth dielectric layer  220 , as shown in  FIG. 4C . For another embodiment, the removal proceeds until the fifth dielectric layer  230  is substantially level and overlies the upper surface of the fourth dielectric layer  220  (not shown).  
         [0037]     In  FIG. 4D , the fifth dielectric layer  230  is recessed within the respective trenches  210 , e.g., using an etch-back process, as described above in conjunction with  FIG. 2D . Note further that leveling the fifth dielectric layer  230  prior to recessing the fifth dielectric layer  230  within the respective trenches  210  acts so that the fifth dielectric layer  230  is recessed to substantially the same level below the first dielectric layer  202  within the array and periphery trenches. Subsequently, for one embodiment, the process proceeds as described above for  FIGS. 2E-2H  to form the structure of  FIG. 4E . That is, a portion of the fourth dielectric layer  220  is selectively removed to a level of the upper surface of the fifth dielectric layer  230 ; the sixth dielectric layer  240  is formed to fill the remaining portion of the trenches  210 ; the hard mask layer  206  is removed; and the seventh dielectric layer  250  and the conductive layer  260  are formed overlying conductive layer  204 .  
         [0038]     In the array, the gate stacks comprising first dielectric layer  202 , the conductive layer  204 , the seventh dielectric layer  250 , and the conductive layer  260  each form a floating-gate transistor  275  that acts as a memory cell of the array. Each of the gate stacks comprising first dielectric layer  202 , the conductive layer  204 , the seventh dielectric layer  250 , and the conductive layer  260  in the periphery forms a field-effect transistor  280 . For some embodiments, the conductive layer  204  and the conductive layer  260  of each field-effect transistor  280  may be strapped (or shorted) together so that the shorted together conductive layers form the control gate of that field-effect transistor  280 . For another embodiment, the conductive layers  204  and  260  are not shorted together, and the conductive layer  204  forms the control gate of the field-effect transistors  280 . Note that field-effect transistors  280 , for one embodiment, form a portion of the logic of row access circuitry  108  and/or column access circuitry  110  of the memory device  102  of  FIG. 1  for accessing rows and columns of the memory array  104 .  
       CONCLUSION  
       [0039]     Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the invention will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the invention. It is manifestly intended that this invention be limited only by the following claims and equivalents thereof.