Abstract:
An electrical circuit for providing a temperature compensated feedback signal includes a first electrical component and a first amplifier. The first electrical component exhibits a first temperature variable impedance and is positioned in thermal contact with a first switch having a second temperature variable impedance. The first amplifier includes an input electrically coupled to the first switch and an output electrically coupled to an input of the first electrical component. The first amplifier amplifies the signal produced across the first switch when the first switch is conducting and the first electrical, component attenuates the amplified signal provided by the first amplifier as a function of a temperature of the first electrical component. The attenuated amplified signal is provided at an output of the first electrical component to provide a temperature compensated feedback signal.

Description:
TECHNICAL FIELD 
   The present invention is generally directed to a method and system for providing a feedback signal and, more specifically, to a method and system for providing a temperature compensated feedback signal. 
   BACKGROUND OF THE INVENTION 
   In a typical switching power supply that implements pulse width modulation (PWM), control loops have been implemented at an output of the supply and/or at a primary switch, for example, a field-effect transistor (FET). In general, inner-loop current feedback at the primary switch is desirable to provide stability and/or to detect overcurrent conditions. In a typical switching power supply, relatively expensive magnetic-field sensing hardware, such as a Hall-effect or magnetorestrictive sensor, or a very low-value power resistor, which is inserted in series with the switch, have been utilized to provide current feedback. When a resistor is utilized in series with the switch, the ramp voltage developed across the series resistor is then fed back to a control unit, which utilizes ramp slope information, along with an instantaneous output voltage, to control the modulation of a control signal applied to a control terminal of the switch. 
   Field-effect transistors (FETs) have been widely utilized as primary switches in switching power supplies. Various articles have proposed utilizing a saturation resistance, i.e., a drain-to-source resistance R DSon , of a FET to serve as a current sense resistor for the FET. However, the resistance of a typical conducting FET may vary over one-hundred percent over typical temperature operating ranges. As such, these temperature variable resistance changes may result in large errors in current feedback and, as a result, the current loop characteristics of a switching power supply implementing this technique are highly temperature sensitive. 
   Due to cost considerations, it would be desirable to develop a circuit for a switching power supply that measures a primary switch current economically and with enough accuracy to allow for adequate current loop control. What is needed is a technique for providing a temperature compensated feedback signal for a switching power supply. 
   SUMMARY OF THE INVENTION 
   An electrical circuit for providing a temperature compensated feedback signal includes a first electrical component and a first amplifier. The first electrical component exhibits a first temperature variable impedance. In operation, the first electrical component is positioned in thermal contact with a first switch having a second temperature variable impedance. The first amplifier includes an input electrically coupled to the first switch and an output electrically coupled to an input of the first electrical component. The first amplifier amplifies a signal produced across the first switch, when the first switch is conducting, and the first electrical component attenuates the amplified signal, provided by the first amplifier, as a function of the temperature of the first electrical component. The attenuated amplified signal is provided at an output of the first electrical component and acts as a temperature compensated feedback signal. The temperature compensated feedback signal may be utilized by an external control unit to determine whether an overcurrent condition exists and/or the circuit is unstable and, if so, take an appropriate action. 
   According to another embodiment of the present invention, a second amplifier, including an input electrically coupled to the output of the first electrical component, is provided. The second amplifier amplifies the attenuated amplified signal to provide the temperature compensated feedback signal at the output of the second amplifier. According to another aspect of the invention, a second switch, which is electrically coupled to the input of the first amplifier, is provided. The second switch couples the input of the first amplifier to ground, when the first switch is not conducting. The first electrical component may be a thermistor with a positive temperature coefficient that substantially matches a temperature coefficient of the first switch. Ideally, the temperature of the thermistor is within a +/−5 degrees Celsius of a temperature of the first switch. The first switch may be one of a field-effect transistor (FET) or an insulated-gate bipolar transistor (IGBT) and the first and second temperature variable impedances may be temperature variable resistances. 
   These and other features, advantages and objects of the present invention will be further understood and appreciated by those skilled in the art by reference to the following specification, claims and appended drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will now be described, by way of example, with reference to the accompanying drawings, in which: 
       FIG. 1  is an exemplary electrical block diagram of a control system for a switching power supply; 
       FIG. 2  is an electrical diagram of an electrical circuit for providing a temperature compensated feedback signal; 
       FIG. 3  is a graph depicting a temperature variable resistance curve of an exemplary thermistor; 
       FIG. 4  is a graph depicting an exemplary temperature variable resistance curve of an exemplary field-effect transistor (FET); 
       FIG. 5  is a graph depicting an exemplary maximally flat variable resistance curve for a FET; and 
       FIG. 6  is a graph depicting an exemplary normalized maximally flat variable resistance curve for a FET. 
   

   DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   As is described above, power switching supplies have been proposed that utilize a saturation resistance of a field-effect transistor (FET) to provide a feedback signal to a control unit for controlling the FET, which acts as a switch for a switching power supply. However, as also noted above, utilizing the FET saturation resistance to provide an indication of the current carried by the FET may result in large errors in a sensed feedback current, as a FET drain-to-source resistance R DSon  tends to be highly temperature dependent. As a general rule, it is not necessary for the FET current to be measured with extreme precision. Typically, a measurement accuracy of ten to twenty percent is sufficient for reliable loop control. As such, according to the present invention, a relatively accurate feedback signal is achieved by compensating for temperature effects on the FET drain-to-source resistance R DSon  to a sufficient degree. Accordingly, the added dissipation of a series current sense resistor is eliminated and, as a result, the resulting power conversion efficiency of the switching power supply is increased. 
   The circuit described herein can be implemented at approximately the same cost as that of a high-precision current sense resistor. In general, it is desirable that the electrical component, e.g., a thermistor, have a temperature variable impedance that is similar to that of the switching FET. Further, the electrical component should be selected to have a positive temperature coefficient curve with minimal curvature. It desirable for the electrical component to be positioned relatively close to a drain of the switching FET such that the temperature of the electrical component and the FET are approximately the same, e.g., within +/−5 degrees Celsius. 
   With reference to  FIG. 1 , a portion of a switching power supply  10  includes a control unit  104  and an electrical circuit  102 . The control unit  104  provides a control signal, through a series resistor R s  to a gate of a transistor Q 1 , e.g., a FET or an insulated-gate bipolar transistor (IGBT). A source of the transistor Q 1  is coupled to ground and a drain of the transistor Q 1  is coupled to one side of a primary of a transformer T 1 , whose other side is coupled to a positive terminal of a voltage supply +V. A first input of the electrical circuit  102  is coupled to the drain of the transistor Q 1  and a second input of the electrical circuit is coupled to an output of the control unit  104 . In this manner, the electrical circuit  102  can determine when the control unit  104  has applied a voltage V G  to a gate of the transistor Q 1 , to turn the transistor Q 1  on. The electrical circuit  102  provides feedback to an input of the control unit  104  such that the control unit  104  can determine the current through the transistor Q 1  and take an appropriate action. 
   As is better shown in  FIG. 2 , the circuit  102  is used to replace the traditional current sense resistor required for ground referenced inner-loop current feedback in a switching power supply. As mentioned above, this is desirable to increase the efficiency of the power supply and to eliminate additional internal heating that accompanies sense resistor losses. The circuit  102  samples the drain voltage, V D , of the transistor Q 1  during its on-time, isolates the sampled sawtooth signal V SD  and amplifies the signal V SD  to provide a signal V AO1 . The signal V AO1  is an amplified version of the voltage dropped across the temperature dependent FET. The signal V AO1  is then attenuated as a function of temperature by the resistive divider, i.e., electrical component RT and resistor R 1 , to compensate for increases in the FET Q 1  drain-to-source resistance R DSon  with temperature. The divided signal V C  is then amplified to produce an output signal V AO2 , which is essentially an amplified version of the voltage signal, which would be developed across a reasonably temperature independent FET. 
   The choice of using two amplification stages is desirable in order to drive the divider with a low-impedance source and present a low-impedance output for loop feedback control purposes. It is also desirable for the amplifiers to exhibit a reasonably wide bandwidth, e.g., 130 MHz, in order to provide substantial gain to low-amplitude input signals, while faithfully replicating relatively high-bandwidth signals. 
   Isolating the FET Q 1  saturation ramp voltage may be achieved using a NC7SZ66 high-speed analog transmission gate U 1 . The gate U 1  includes an internal transmission FET (between pins  1  and  2  of the device) that has a maximum drain-to-source resistance R DSon  of seven ohms and in this application is used to shunt the drain voltage signal of the FET Q 1 , through R 3 , to ground when the FET Q 1  is off and to pass the on-time ramp unattenuated to a positive input of amplifier U 2 A when the FET Q 1  is on. A low level at an SE input of the gate U 1  turns off the internal FET during the FET Q 1  on-time. This signal is generated by delaying the FET Q 1  gate drive signal, until turn-on is achieved, and inverting and logic level translating this signal to high-speed complementary metal-oxide semiconductor (HCMOS) logic levels. 
   The electrical component RT may be implemented as a thermistor, manufactured and made commercially available by Infineon (Part No. KTY23-6). The component RT is located adjacent a drain of the FET Q 1  in order that the resistance of the component RT vary in direct relationship with the drain-to-source resistance R DSon  of the FET Q 1 . The KTY23-6 has a positive temperature coefficient resistance curve that is only slightly curved. This substantially linear resistance curve, shown in  FIG. 3 , is adequate to provide compensation for the selected FET (in combination with the divider resistor R 1 ) due to the similar shape of resistance curve of the selected FET. 
   The resistance/temperature characteristics for the Infineon KTY23-6 are set forth below: 
           T   S     ≡       (           -   50               -   40               -   30               -   20               -   10             0           10           20           30           40           50           60           70           80           90           100           110           120           130           140           150         )     ⁢           ⁢     R   S       ≡         (         518           670           625           585           748           815           886           961           1040           1123           1209           1300           1394           1492           1594           1700           1810           1923           2041           2128           2235         )     ·   Ω     ⁢           ⁢     I   S         :=     0   ⁢           ⁢   …   ⁢           ⁢     (       rows   ⁢           ⁢     (     T   S     )       -   1     )           
 
As is shown in  FIG. 3 , a spline fit may be applied to approximate the resistance curve of the thermistor. In  FIG. 3 , the specification data is shown as circles and the solid line shows the spline fit.
 
   In general, it is desirable to select a FET that has a drain-to-source resistance R DSon  near nominal as indicated on a data sheet for the component. To determine whether the FET exhibits a nominal drain-to-source resistance the FET and thermistor may be mounted on a circuit board with a gate of the FET connected ta a voltage source to continuously turn-on the FET so that the FET can be evaluated. A drain of the FET is connected to a current source capable of supplying a saturation current to the FET, without exceeding the dissipation capability of the FET. A current probe is attached to measure drain current and a voltmeter is connected across the FET to measure a drain-to-source saturation voltage of the FET. An ohmmeter is connected across the terminals of the thermistor for monitoring its resistance and provides an indication of the temperature of the thermistor. The FET drain-to-source resistance R DSon  can then be determined with respect to the thermistor temperature. 
   As a general rule, it is sufficient to determine the FET drain-to-source resistance R DSon  at three temperatures in a desired temperature range and then, using a spline function, to create a curve through the three points (see  FIG. 4 ). The following provides an example of how to determine appropriate values for the components of the electrical circuit  102  of  FIG. 2 . Given an internal ambient operating temperature range, the FET drain-to-source resistance R DSon  may be determined at temperatures T 1 , T 2  and T 3  as defined below: 
   Given: 
   
       
       T Ambmin :=−40 
       T Ambmax :=125
         T   1     :=       T   Ambmin     +         T   Ambmax     -     T   Ambmin       6           
         T   2     :=       T   Ambmin     +         T   Ambmax     -     T   Ambmin       2           
         T   3     :=       T   Ambmax     -     (         T   Ambmax     -     T   Ambmin       6     )           
 
For this range, the temperatures at which to determine the FET drain-to-source resistance R DSon  and the corresponding thermistor resistances are given below in matrix form. 
         T   Amb     :=         (           T   1               T   2               T   3           )     ⁢           ⁢     T   Amb       =         (           -   12.5000             42.5000           97.5000         )     ⁢           ⁢       R   Th     ⁡     (     T   Amb     )         =       (         731.9292           1144.1481           1673.0464         )     ⁢   Ω             
 
     
  
   The circuit board is placed within an environmental chamber and the instrumentation leads described above are connected. The chamber is turned on and the chamber temperature is varied to sequentially achieve temperatures T 1 , T2 and T 3 , as indicated by the measured resistance of the thermistor. At each of these temperatures, the FET drain current I D  and saturation voltage V sat  are recorded. Results of some measurements using this procedure on a test circuit are given below, as are the resulting computed values of the FET drain-to-source resistance R DSon  (designated R DSonAT ) at the specific temperatures. 
         T   Amb     :=         (           T   1               T   2               T   3           )     ⁢           ⁢     I   D       =           (         20.09           19.66           19.18         )     ·   amp     ⁢           ⁢     V   sat       =       (         .0469           .0628           .0795         )     ·   volt             
         R   DSonAT     =         (             V     sat     0   ,   0           I     D     0   ,   0                       V     sat     1   ,   0           I     D     1   ,   0                       V     sat     2   ,   0           I     D     2   ,   0                 )     ⁢           ⁢     R   DSonAT       =       (         2.3345           3.1790           4.1449         )     ⁢   m   ⁢           ⁢   Ω           
         I   discrete     :=     0   ⁢           ⁢   …   ⁢           ⁢     (       rows   ⁡     (     T   Amb     )       -   1     )           
 
To approximate the FET drain-to-source resistance R DSon  characteristic, another spline fit may be performed as follows:
 
 J   Spline :=cspline( T   Amb   ,R   DSonAT )
 
 R   DSonA ( T ):=interp( J   Spline   ,T   Amb   ,R   DSonAT   , T )
 
 T   interp   :=T   Ambmin −5 ., T   Ambmax +5
 
   Assuming that the first amplifier U 2 A gain is unity, the circuit output voltage V C  is then given by the following: 
         V   C     =           V   SD     ·     (       R   1         R   1     +       R   Th     ⁡     (   T   )           )       ⁢           ⁢     V   AO1       =       V   SD     =     V   D             
         V   C     =       V   D     ·     (       R   1         R   1     +       R   Th     ⁡     (   T   )           )           
         V   C     =       I   D     ·       R   DSonA     ⁡     (   T   )       ·     (       R   1         R   1     +       R   Th     ⁡     (   T   )           )           
 
   As it is desirable for the output voltage V C  to be constant with temperature for each value of I D  over the temperature range, the right side of the following expression should be as nearly constant as possible. This expression represents the equivalent sense resistor value that would give an output V C  with I D  passing through it. 
           V   C       I   D       =         R   DSonA     ⁡     (   T   )       ·     (       R   1         R   1     +       R   Th     ⁡     (   T   )           )           
 
   It is desirable to choose the value of R 1  to give the most constant value of the expression with respect to changes in temperature T. Assuming the initial value for R 1  is chosen to be 500 Ohms and the maximally constant value is R DSonAC . 
           R   DSonAC     ⁡     (     T   ,     R   1       )       :=         R   DSonA     ⁡     (   T   )       ·     (       R   1         R   1     +       R   Th     ⁡     (   T   )           )           
         ɛ   ⁢     (     R   1     )       :=     ❘           i   ←   0                 for   ⁢           ⁢   Temp     ∈       T   Ambmin     -     5   ⁢           ⁢   …   ⁢           ⁢     T   Ambmax       +   5                 ❘             R     DSonAC   i       ←       R   DSonAC     ⁡     (     Temp   ,     R   1       )                   i   ←     i   +   1                           Err   Max     ←     max   ⁡     (     R   DSonAC     )                     Err   Min     ←     min   ⁡     (     R   DSonAC     )                   Δ   ←       Err   Max     -     Err   Min                   return   ⁡     (           Err   Max               Err   Min             Δ         )                   
 
   With the initial guess of R 1 :=500·Ω, the error terms are: 
           ɛ   ⁡     (     R   1     )       =       (         0.9673           0.9295           0.0379         )     ⁢           ⁢   m   ⁢           ⁢   Ω       ;         ɛ   (     R   1     )     2     =     0.0379   ⁢           ⁢   m   ⁢           ⁢   Ω           
 
The “Delta Error” is in vector element ‘2’. Optimizing the circuit yields the following (see  FIG. 5 ):
         Given
 
0 Ω=ε( R   1 ) 2   R   1 &gt;1 Ω
   R 1 :=Minerr(R 1 )R 1 =501.2418 Ω   R 1 :=R Nearest     —     1% (R 1 )   Thus, R 1 =499.0000 Ω
         R   DSonACavg     :=         ɛ   ⁡     (     R   1     )       1     +         ɛ   ⁡     (     R   1     )       2     2           
   R DSonACavg =0.9470 m Ω       

   Normalizing R DSonAC  to the range average value gives the following: 
           R   DSonACN     ⁡     (     T   ,     R   1       )       :=           R   DSonA     ⁡     (   T   )       ·     (       R   1         R   1     +       R   Th     ⁡     (   T   )           )         R   DSonACavg           
 
   The normalized graph of R DSonAC  (see  FIG. 6 ) is much less temperature dependent than the original R DSonA . Assuming the circuit provides an output voltage, V AO2 , at a specific peak drain current, I Dpk  at some temperature, say 25 degrees Celsius, for example, let V AO2req :=0.8·vol at I Dpk25 :=40·amp. It is then necessary to obtain the FET drain-to-source resistance R DSon  corresponding to a temperature of 25 degrees Celsius. But this is just R DSonA (25)=2.8914 m Ω. This corresponds to an amplifier output of: 
           V   AO2pk25     :=       I   Dpk25     ·       R   DSonA     ⁡     (   25   )       ·     (       R   1         R   1     +       R   Th     ⁡     (   25   )           )         ,       
 
or
         V AO2pk25 =38.5010 mV       

   Thus, it is necessary to increase the output voltage V AO2  by a gain factor of: 
         G   :=       V   AO2req       V   AO2         ,           ⁢       or   ⁢           ⁢   G     =     20.7787   .           
 
To distribute this gain equally over the two amplifier stages requires a stage gain of:
 
 G   stage   :=√{square root over (G)} , or  G   stage =4.5584
 
In the circuit, let:
 
 R   5 :=1000·Ω
 
The first amplifier gain is: 
         G   stage     =     1   +       R   4       R   5             
 
Thus,
 
 R   4   :=R   5 ·( G   stage −1), or  R   4 =3558.3655 Ω
 
Choosing the nearest 1% resistor value yields:
 
 R   4   :=R   Nearest     —     1% ( R   4 ), or  R   4 3570.0000 Ω
 
Then, 
           G   stage1     :=     1   +       R   4       R   5           ,           ⁢       or   ⁢           ⁢     G   stage1       =   4.5700         
 
This requires that the gain of stage two be: 
           G   stage2     :=     G     G   stage1         ,           ⁢       or   ⁢           ⁢     G   stage2       =   4.5468         
 
Choosing
 
 R   7 :=1000·Ω
 
gives:
 
 R   6   :=R   7 ·( G   stage2 −1), or  R   6 3546.7605 Ω
 
The nearest 1% resistor value is:
 
 R   6   :=R   Nearest     —     1% ( R   6 ), or  R   6 =3570.0000 Ω
 
The resulting cumulative gain is: 
           G   actual     :=       (     1   +       R   4       R   5         )     ·     (     1   +       R   6       R   7         )         ,           ⁢       or   ⁢           ⁢     G   actual       =   20.8849         
 
This results in an actual:
 
 V   AO2actual  of  V   AO2actual   :=G   actual   ·V   AO2pk25 , or
 
 V   AO2actual  =804.0890 mV.
 
   Accordingly, a method and system have been described herein that provides a temperature compensated feedback signal for a switching power supply. The method and system provide a more economical and efficient switch power supply that can advantageously be implemented within an automotive environment. 
   The above description is considered that of the preferred embodiments only. Modifications of the invention will occur to those skilled in the art and to those who make or use the invention. Therefore, it is understood that the embodiments shown in the drawings and described above are merely for illustrative purposes and not intended to limit the scope of the invention, which is defined by the following claims as interpreted according to the principles of patent law, including the doctrine of equivalents.