Abstract:
An improved multi-channel receiver for satellite broadcast applications or the like. In an exemplary embodiment, a primary AGC loop controls an analog sub-receiver adapted to simultaneously receive multiple signals. Multiple digital demodulators, coupled to the sub-receiver, demodulate the multiple received signals. Multiple secondary AGC loops, one for each received signal, compensate for variations in demodulated signal strengths caused by the primary AGC loop. A feed-forward AGC compensation technique generates scalar control values for scaling the demodulated signals before the demodulated signals are processed by the secondary AGC loops. This at least partially compensates for gain variations caused by the primary AGC, reducing received signal drop-outs before the secondary AGC loops can compensate for the gain variations. Because of systemic delays in the sub-receiver and the demodulators, the scalar control values are independently timed to be coincident with the variations in the demodulated signal strengths caused by the primary AGC loop.

Description:
TECHNICAL FIELD 
       [0001]    The present invention relates to digital data receivers, and, in particular, to multi-channel data receivers for use in satellite broadcast systems or the like. 
       BACKGROUND 
       [0002]    A typical satellite digital audio radio service (SDARS) system, such as that provided by XM Satellite Radio Inc. of Washington, D.C. or Sirius Satellite Radio Inc. of New York City, N.Y., uses two or more satellites with orbits that provide a usable signal over most of North America at all times. However, the signals from the satellites tend not to be received well in cities or anywhere a satellite receiver does not have an unobstructed view of at least one of the satellites. Thus, in cities and other areas where direct reception from a satellite is impossible or unlikely, the SDARS provider may have installed terrestrial repeaters that provide a digital audio data signal carrying the same digital audio data that the satellites are broadcasting. The use of redundant digital audio data channels minimizes service outages as the satellites orbit the earth or as a user moves about. To minimize interference and provide redundancy, the terrestrial repeater and each satellite transmits its digital audio data signal on a different channel, each channel having a different carrier frequency. Moreover, the modulation method used for the terrestrial channel (e.g., a carrier-orthogonal frequency division multiplexed (COFDM) modulation technique) is chosen for its resistance to fading caused by multipath interference and is more complicated than the modulation method used for the satellite channels (e.g., a time division multiplexed (TDM) modulation technique). 
         [0003]    A typical prior art SDARS receiver has multiple independent analog sub-receivers therein, one sub-receiver for each channel, and circuitry within the receiver selects which sub-receiver provides the best data signal for decoding. The radio frequency (RF) and intermediate frequency (IF) portions of the sub-receivers are analog, and each sub-receiver contains an analog-to-digital converter (ADC) that digitizes IF signals for further processing by various digital circuits. Because each analog sub-receiver consumes considerable power, an SDARS receiver having three or more sub-receivers operating simultaneously does not lend itself to portable or other low-power applications. In addition, having three or more separate sub-receivers makes the SDARS receiver physically larger than desired for certain applications. 
       SUMMARY 
       [0004]    In one embodiment, the present invention is a receiver comprising a gain section, a detector, a demodulator, a scalar, and a controller. The gain section generates, based on a gain control value, an output signal from one or more received signals. The detector generates an intensity value in response to the output signal. The demodulator, for each received signal, demodulates the output signal into a corresponding demodulated signal having an amplitude. The scalar, for each demodulated signal, scales the amplitude of the corresponding demodulated signal based on a corresponding scalar control value. The controller generates and adaptively changes the gain control value and each scalar control value based on changes in the intensity value. Further, the controller delays a change of at least one of the scalar control values based on at least one processing delay associated with generating the corresponding demodulated signal. 
         [0005]    In still another embodiment, the present invention includes the steps of: generating, based on a gain control value, an output signal from the one or more received signals; generating an intensity value in response to the output signal; demodulating, for each received signal, the output signal into a corresponding demodulated signal having an amplitude; scaling, for each demodulated signal, the amplitude of the corresponding demodulated signal based on a corresponding scalar control value; and generating and adaptively updating the gain control value and each scalar control value based on changes in the intensity value. A change of at least one scalar control value is delayed based on at least one processing delay associated with generating the corresponding demodulated signal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    The aspects, features, and advantages of the present invention will become more fully apparent from the following detailed description, the appended claims, and the accompanying drawings in which like reference numerals identify similar or identical elements. 
           [0007]      FIG. 1  is a simplified block diagram of a portion of an improved SDARS receiver with one analog sub-receiver, one primary and three secondary AGC loops, and a feed-forward AGC compensation technique according to the one exemplary embodiment of the present invention; and 
           [0008]      FIG. 2  is a simplified timing diagram demonstrating operation of the improved SDARS receiver in  FIG. 1 . 
       
    
    
     DETAILED DESCRIPTION 
       [0009]    For purposes of this description and unless explicitly stated otherwise, each numerical value and range should be interpreted as being approximate as if the word “about” or “approximately” preceded the value of the value or range. Further, reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments necessarily mutually exclusive of other embodiments. The same applies to the term “implementation.” 
         [0010]    Also for purposes of this description, the terms “couple,” “coupling,” “coupled,” “connect,” “connecting,” or “connected,” refer to any manner known in the art or later developed in which energy is allowed to be transferred between two or more elements and the interposition of one or more additional elements is contemplated, although not required. Conversely, the terms “directly coupled,” “directly connected,” etc., imply the absence of such additional elements. 
         [0011]    Signals and corresponding nodes, ports, inputs, or outputs may be referred to by the same name and are interchangeable for purposes here. 
         [0012]    Referring to  FIG. 1 , an exemplary embodiment of the invention is shown, in which a simplified block diagram of an SDARS receiver  100  having one sub-receiver  150  capable of simultaneously receiving a plurality of channels (RF signals) is diagrammed. The sub-receiver  150  comprises an analog RF/IF section  152  producing an amplified analog IF output signal at node  154 , the analog output signal having therein a combination of one or more IF signals based on the received signals, each IF signal with a different IF carrier frequency. The analog output signal is digitized by an analog-to-digital converter (ADC)  156  to produce a digitized output signal at node  158 . Included in the sub-receiver is a power detector  160 , preferably a root-mean-square (RMS) power detector, generating an intensity value at node  162 . It is understood that the power detector  160  may be of another design, such as a peak detector. While shown as responsive to the digitized output signal on node  158 , the detector  160  may instead receive the analog output signal on node  154  for generating the intensity value. Moreover, as is known in the art, the RF/IF section  152  may be a direct conversion sub-receiver, avoiding the need for an IF portion by amplifying and directly converting received RF signals to a base-band analog output signal at node  154 . Thus, the section  152  may be referred to generically as a gain section. 
         [0013]    The RF/IF section  152  is responsive to an AGC control value on node  164  to vary the gain of the RF/IF section  152 . As is appreciated by those skilled in the art, the gain in the RF/IF section  152  is adjusted in response to the AGC control value so that the RF/IF section  152  has the proper amount of gain to produce an analog IF output signal on node  154  that has an average amplitude near the middle of the dynamic range of ADC  156 . This avoids saturating the ADC  156  on peaks in the amplitude of the analog IF output signal on node  154  but leaves the analog signal with sufficient amplitude that the ADC  156  produces a digitized output signal (containing the one or more IF signals in digitized form) at node  158  having low distortion and a good signal-to-noise ratio. As will be discussed in more detail below, the AGC control value is produced by AGC processor  200  in response to the intensity value from detector  160 , thereby forming a primary AGC loop  120  for the sub-receiver  150 . Generally, the AGC processor  200 , in response to a change in the intensity value, changes the AGC control value to partially counteract the change in the amplitude of the digitized output signal on node  158 . For example, when a change in the intensity value indicates an increase in the power (thus, the amplitude) of the digitized output signal on node  158 , the AGC processor  200  changes the AGC control value in response to reduce the gain of the RF/IF section  152  and lessen the increase in the amplitude of the digitized output signal. Conversely, when a change in the intensity value indicates a decrease in the power (thus, the amplitude) of the digitized output signal on node  158 , the AGC processor  200  changes the AGC control value in response to increase the gain of the RF/IF section  152 . However, because the primary AGC loop  120  has a finite delay and a finite loop gain (and, as will be discussed in more detail below, because the AGC control value changes in discrete steps), the primary AGC loop  120  cannot completely counteract an amplitude change in digitized output signal. Moreover, a change in the AGC control value by the primary AGC loop  120  will appear as a corresponding change in the amplitude of at least one of the one or more IF signals in the analog IF output signal on node  154  and, thus, a change in the amplitude of the corresponding one or more digitized IF signals in the digitized output signal on node  158 . 
         [0014]    Coupled to the output node  158  are, in this example, three demodulators  170 ,  180 , and  190 . The demodulator  170 , in this example a digital down-converter for a COFDM-modulated signal, demodulates one channel (IF signal) in the digitized output signal on node  158  to produce a demodulated signal on node  171 . Similarly, demodulators  180  and  190 , in this example digital down-converters for TDM-modulated signals, produce demodulated signals on respective nodes  181  and  191 . It is understood that if a single RF signal is being received by the sub-receiver  150 , then instead of all three demodulators operating and consuming power, just the demodulator for that received signal is used and the other demodulators and associated circuitry (such as the corresponding secondary AGC loops) are disabled. Similarly, if two signals are being simultaneously received, then the two demodulators for those signals are used and the remaining demodulator and associated circuitry are disabled. 
         [0015]    The demodulated signals on nodes  171 ,  181 , and  191  are scaled (i.e., amplified or attenuated) by corresponding scalars  172 ,  182 , and  192  to produce corresponding scaled demodulated signals at nodes  173 ,  183 , and  193 , respectively, the amount of scaling being determined by corresponding scalar control values on nodes  174 ,  184 , and  194  from the AGC processor  200 . While the scalars  172 ,  182 , and  192  are shown as variable gain amplifiers, they may be multipliers or other circuits or algorithms designed to controllably increase or decrease the amplitude of the demodulated signals at nodes  171 ,  181 , and  191 . As will be discussed in greater detail below, the AGC processor  200  generates the scalar control values, in addition to the AGC control value, in response to the intensity value from detector  160 . The AGC processor responds to a change in the intensity value from detector  160  by generating corresponding changes in the AGC and scalar control values. Preferably, the amount of change in the gain of the RF/IF section  152  in response to the change in the AGC control value from the AGC processor is at least partially offset by a corresponding, but opposite, change in the scaling of the demodulated signals by the scalars  172 ,  182 , and  192 . Thus, the change in the scalar control values by AGC processor  200  is a feed-forward AGC technique to at least partially compensate for the effect the primary AGC loop has on the received signals. 
         [0016]    It is preferable that the AGC control value and scalar control values from the AGC processor  200  change in discrete steps (e.g., 3 dB, 5 dB, etc.) to reduce the frequency of changes to the AGC and scalar control values. Moreover, as known in the art, it is desirable that the AGC processor  200  implement a level of hysteresis in the generation of the AGC and scalar control values to further reduce the frequency of changes thereto and enhance stability within the primary AGC loop  120 . 
         [0017]    Coupled to each of the nodes  173 ,  183 , and  193  are secondary AGC loops  175 ,  185 , and  195  comprising corresponding scalars  176 ,  186 , and  196 , and corresponding power detectors  177 ,  187 , and  197 . As is well understood in the art, the secondary AGC loops  175 ,  185 , and  195  serve to further regulate the amplitude of the corresponding scaled demodulated signals on nodes  173 ,  183 , and  193  for further processing by corresponding decoders  178 ,  188 , and  198 . However, the secondary AGC loops  175 ,  185 , and  195  take a finite amount of time to equalize an amplitude change, during which time the output signals therefrom may be too low (“drop-out”) for one or more of the decoders  178 ,  188 , and  198  to process correctly. 
         [0018]    As is known in the art, a digital demodulator takes time to demodulate a signal, the amount of time being dependent on the complexity of the demodulator. In this embodiment, a change in the amplitude of the digitized signal on node  158  propagates through the demodulators  170 ,  180 , and  190 , resulting in an amplitude change in at least one of the demodulated signals appearing on respective output nodes  171 ,  181 , and  191  after the delay from the respective demodulator. Because COFDM modulation is more complex than TDM modulation, the demodulator  170  is typically more complicated and has a longer latency than demodulators  180  and  190 , both having substantially the same latency. Moreover, it is understood that some demodulator designs are adaptive and the amount of latency in an adaptive demodulator may vary depending on the amount of processing needed to demodulate a signal. Thus, it may be necessary to keep track of the latency of each demodulator, the importance of which is discussed in more detail below. 
         [0019]    As stated above, there is a delay between a change in the AGC control value and a change in the amplitude of the digitized output signal at node  158 . This delay is in addition to the demodulator latency. Taken together, the delay between a change in the AGC control value to the RF/IF portion  152  and when that change results in a change in amplitude of a demodulated signal might be considerable and will vary based upon the latency of the demodulator being used. In particular, the delay from a change in the AGC control value to a corresponding change in the amplitude of the demodulated signal on node  173  may be tens of milliseconds longer than the delay of the corresponding change in the amplitude of the demodulated signal on node  183  or  193 . Since the changes in the scalar control values at least partially compensate for the amplitude changes in the corresponding demodulated signals, it is therefore desirable that each scalar  172 ,  182 , and  192  not change the amplitude of the demodulated signals until the changes in the amplitudes of the corresponding demodulated signals at the nodes  171 ,  181 , and  191  reach the input of the respective scalar. Put another way, the changes in the scalar control values should substantially coincide in time with the corresponding changes in amplitudes of the demodulated signals. In this embodiment, the desired delay is accomplished by the AGC processor  200  independently delaying the change in each scalar control value to substantially coincide with the corresponding change in the amplitude of the demodulated signals at the scalars  172 ,  182 , and  192 . The temporal alignment of the changes in the scalar control values with the changes in amplitude of the demodulated signals reduces “glitching,” i.e., the overshooting and undershooting of the amplitude of the scaled demodulated signals at nodes  173 ,  183 , and  193 , that the secondary AGC loops  175 ,  185 , and  195  then process. 
         [0020]    Preferably, the power detectors ( 160 ,  177 ,  187 , and  197 ), demodulators ( 170 ,  180 , and  190 ), scalars ( 172 ,  176 ,  182 ,  186 ,  192 , and  196 ), decoders ( 178 ,  188 , and  198 ) and AGC processor  200  are implemented in a digital signal processor, microprocessor, application-specific integrated circuit, or the like. In addition, it is desirable that the intensity value from detector  160  be stable before the AGC and scalar control values are calculated and applied to the RF/IF portion  152  and scalars  172 ,  182 , and  192 . As shown in  FIG. 2  and for this embodiment, during a first time sub-interval T 0  to T 1  of an AGC update interval, the intensity value stabilizes and is sampled at time T 0 . Then the AGC and the scalar control values are calculated by the AGC processor  200 . During the time interval from T 1  to T 0  of the subsequent AGC update interval, the AGC control value is applied to the RF/IF portion  152  at time T a , the scalar control value for scalars  182  and  192  then applied at time T b  (both demodulators  180  and  190  having the same latency in this example), and then the scalar control value for scalar  172  is applied at interval T c  (the latency of demodulator  170  being longer than the latency of the demodulators  180  and  190 ). It is understood that the time T b  may be different for the demodulators  180  and  190  if the demodulators have different latencies. 
         [0021]    As mentioned above, the latency of the demodulators  170 ,  180 , and  190  may vary over time. In this embodiment and as is well known in the art, the demodulators  170 ,  180 , and  190  are each of a conventional design and configurable. The configurability of the demodulators allows each demodulator to independently apply an amount of signal processing to the digitized signal on node  158  depending on a desired level of quality (e.g., error rate, signal-to-noise ratio, etc.) in each demodulator&#39;s output signal. Generally, the more signal processing that is done by a demodulator, the more latency the demodulator has. In this embodiment, the AGC processor  200  keeps track of the latency of the demodulators  170 ,  180 , and  190  by reading associated registers (not shown) that contain data indicative of the corresponding demodulator&#39;s latencies via exemplary data paths  131 - 133 . The AGC processor  200  then uses the data to calculate the times T b  and T c . It is understood, however, that one or more of the demodulators  170 ,  180 , and  190  may have a fixed latency, obviating the need for the associated data path  131 - 133  so long as the AGC processor  200  has the pertinent latency data stored therein. 
         [0022]    Operation of the receiver  100  is illustrated by the following example where steady COFDM and TDM signals (TDM1 and TDM2) are simultaneously received by the sub-receiver  150  and where the COFDM signal has the best signal-to-noise ratio but not the strongest signal. Because the COFDM and TDM signals are being simultaneously received, the digitized output signal on node  158  contains both the COFDM and the TDM1 and TDM2 signals added together but with different carrier frequencies. If the received COFDM, TDM1, and TDM2 signals are steady, then the intensity value at node  162  is steady and the AGC processor  200  supplies a certain steady AGC control value to the RF/IF section  152  and certain steady scalar control values to the scalars  172 ,  182 , and  192 . Should just the TDM1 signal suddenly increase in strength, the amplitude of the digitized output signal at node  158  increases (from the increased strength of the TDM1 signal, the COFDM and TDM2 signal strengths remaining unchanged), resulting in an increase in the intensity value at node  162 . If the intensity value increase is sufficient to overcome any hysteresis by the AGC processor  200 , then the AGC processor  200  changes (steps) the AGC control value to the RF/IF section  152  to reduce the gain of the RF/IF section  152 . The change in the AGC control value reduces (attenuates) the amplitude of the digitized output signal at node  158 , and, thus, the amplitudes of the COFDM, TDM1, and TDM2 signals in the digitized output signal are decreased equally. Further, the demodulated COFDM, TDM1, and TDM2 signals on nodes  171 ,  181 , and  191 , respectively, are also decreased equally. Because the signal strength of the COFDM signal has not changed and the gain of the RF/IF section has been reduced, the amplitude of the demodulated COFDM signal on node  171  (and that of demodulated TDM2 signal on node  191 )) is reduced by approximately the amount the gain of the RF/IF section  152  was reduced in response to the change in AGC control value. However, after primary AGC loop  120  stabilized, the amplitude of the demodulated TDM1 signal on node  181  is changed a lesser amount when compared to the amplitude of the demodulated TDM1 signal before the received TDM1 signal increased in strength. 
         [0023]    For this example and notwithstanding the smaller amplitude, the COFDM signal remains the better signal for utilization by the receiver  100  because it has a better signal-to-noise ratio than the TDM signals. However, if the amplitude of the demodulated COFDM signal is too low, then the COFDM decoder  178  might not correctly process the attenuated COFDM signal, degrading the performance of the receiver  100 , until the secondary AGC loop  175  catches up to compensate for the low-amplitude demodulated COFDM signal. Thus, the primary AGC loop  120  degrades the performance of the receiver  100  in this instance because the increase in TDM1 signal strength “dominates” the sub-receiver  150  to the detriment of the COFDM signal and the rest of the receiver  100 . 
         [0024]    To overcome the undesired attenuation of the COFDM signal by the action of the primary AGC loop  120 , the AGC processor  200  changes the scalar control values to at least partially compensate for the change in gain in the RF/IF section  152 . Since, in this embodiment, the AGC processor  200  does not know which signal, COFDM or TDM, has increased in strength, the processor  200 , after the appropriate delays, increases the scalar control values to all the scalars  172 ,  182 , and  192  to scale up (i.e., amplify) the demodulated signals on nodes  171 ,  181 , and  191  such that the amplitude of the scaled demodulated COFDM signal on node  173  (and, correspondingly, the scaled demodulated TDM2 signal on node  193 ) is about what it was before the received TDM1 signal increased in strength. Specifically and for this example, if the gain of the RF/IF section  152  is reduced by 6 dB in response to a change in the AGC control value, then the scalar control values to scalars  172 ,  182 , and  192  are increased by a factor of 2. Any small variation in amplitude of the scaled demodulated COFDM signal at node  173  is further reduced by the secondary AGC loop  175 . The delays in the changes to the scalar control values by the AGC controller  200  substantially time-aligns the scalar control value changes with the amplitude changes in the demodulated COFDM, TDM1, and TDM2 signals after having passed through the respective demodulators  170 ,  180 , and  190 . Advantageously, the time alignment of the increase in the scalar control value to scalar  172  keeps the amplitude of the COFDM signal from not being too low for a length of time sufficient to cause the COFDM decoder  170  to incorrectly decode the demodulated COFDM signal from the scalar  176 . Although the amplitude of the scaled demodulated TDM1 signal might be greater than desired, the secondary AGC loop  185  reduces the amplitude to a desired value. 
         [0025]    Although the present invention has been described in the context of an SDARS receiver, those skilled in the art will understand that the present invention can be implemented in the context of other types of multi-channel receivers, such as and without limitation, diversity receivers. 
         [0026]    Unless explicitly stated otherwise, each numerical value and range should be interpreted as being approximate as if the word “about” or “approximately” preceded the value of the value or range. 
         [0027]    It will be further understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain the nature of this invention may be made by those skilled in the art without departing from the scope of the invention as expressed in the following claims. 
         [0028]    The use of figure numbers and/or figure reference labels in the claims is intended to identify one or more possible embodiments of the claimed subject matter in order to facilitate the interpretation of the claims. Such use is not to be construed as necessarily limiting the scope of those claims to the embodiments shown in the corresponding figures. 
         [0029]    Although the elements in the following method claims, if any, are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence.