Abstract:
The present invention relates to a method of manufacturing a cloverleaf microgyroscope containing an integrated post comprising: attaching a post wafer to a resonator wafer, forming a bottom post from the post wafer being attached to the resonator wafer, preparing a base wafer with through-wafer interconnects, attaching the resonator wafer to the base wafer, wherein the bottom post fits into a post hole in the base wafer, forming a top post from the resonator wafer, wherein the bottom and top post are formed symmetrically around the same axis, and attaching a cap wafer on top of the base wafer.

Description:
BACKROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention refers to a cloverleaf microgyroscope and a method of manufacturing a cloverleaf microgyroscope that contains a single crystal silicon cloverleaf-shaped resonator and integrated post attached to the leaves with through-wafer interconnects. 
   2. Description of Related Art 
   U.S. Pat. No. 5,894,090 to Tang et al., which is incorporated herein by reference, discloses a micromachined symmetrical leaf structure having a plurality of symmetrically disposed leaves about a defined center. At least one micromachined spring is disposed symmetrically with respect to the symmetrical leaf structure and supporting the symmetrical leaf structure, a rim/base structure to which the spring is coupled. The rim/base structure includes a plurality of sensing and drive electrodes and a circuit electrically coupled to the electrodes included within the rim/base structure. The circuit provides drive signals to the drive electrodes to oscillate the symmetrical leaf structure and to receive a sensing signal from the sensing electrodes to detect response of the oscillating symmetrical leaf structure to physical phenomena exterior to the micromachined resonator. The micromachined resonator has a manually inserted post. It shows a lack of a silicon based vacuum encapsulation. A low yield is obtained during the separation. The manufacturing of the resonator involves high fabrication costs. It shows large vibration sensitivity and no clear path to electronic integration. 
   The known manufacturing processes make it very difficult to manufacture a microgyroscope. The central post is inserted by hand, the device has to be vacuum packaged in a custom package and there is no ability to integrate control electronics with the silicon structure. 
   Although electrical through-wafer vias have been used for many years for standard ICs, the use of deep (&gt;500 microns) vias with MEMS within a wafer-level vacuum package has not been attempted to our knowledge. In addition, standard pn junction techniques for electrical isolation are not satisfactory for the extremely high levels of isolation that must be achieved for MEMS devices. Also, standard poly fills of etched vias are not useful since the front side contacts (control electrodes for the MEMS device) must be perfectly smooth for the microgyro. This is needed to produce a high degree of reproducibility of the measured capacitance between the plates. The use of spray resist techniques allows us to perform lithography in high-aspect ratio holes, and thus create the desired structure. 
   What are needed are a cloverleaf microgyroscope and a process for manufacturing a cloverleaf microgyroscope with an integrated central post and electronics with the resonator and vacuum package at wafer-level with a single crystal silicon construction. 
   BRIEF SUMMARY OF THE INVENTION 
   This invention addresses the above needs. 
   One aspect of the present invention is a method of manufacturing a cloverleaf microgyroscope containing an integrated post comprising:
         a) attaching a post wafer to a resonator wafer,   b) forming a bottom post from the post wafer,   c) preparing a base wafer with through-wafer interconnects,   d) attaching the resonator wafer to the base wafer, wherein the bottom post fits into a post hole in the base wafer,   e) forming a top post from the resonator wafer, wherein the bottom and top post are formed symmetrically around the same axis, and   f) attaching a cap wafer on top of the base wafer.       

   Another aspect of the present invention is a cloverleaf microgyroscope manufactured by this method. 
   The construction of a microgyroscope has a single crystal silicon cloverleaf-shaped resonator and integrated post attached to the leaves. The microgyroscope device array is fabricated by bonding two separate substrates together using a gold/gold thermo compression technique; one contains the cloverleaf resonator structures fabricated from silicon-on-insulator (SOI) and bulk silicon substrates, and the other contains the support pillars and electrode metal. A fourth wafer containing an array of etched cavities and openings which allow the bonding of electrical wires from metal pads to the device wafer in a vacuum, thus hermetically sealing each individual microgyroscope. 
   This disclosure describes a new concept of using deep through-wafer vias combined with wafer-level vacuum packaging to produce all-Si microgyros with ball-grid array interconnects on the bottom wafer. High-aspect ratio lithography using spray-on resist and DRIE are utilized with conformal dielectric coatings and metal plating from the backside to form the through-wafer interconnects. For base wafer thicknesses of about 800 microns, the proposed lateral dimension of the vias is about 200 microns, which is consistent with the size of the gyro&#39;s control electrodes. 

   
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
     These and other features, aspects and advantages of the present invention will become better understood with reference to the following description, appended claims, and accompanying drawings where 
       FIG. 1   a  is a top plan view of the preferred starting material of a resonator SOI wafer A and  FIG. 1   b  is a cross-sectional view through wafer A of  FIG. 1   a  at line  1   b — 1   b  of the resonator SOI wafer A; 
       FIG. 2   a  is a top plan view of the preferred starting material of a resonator SOI wafer A and  FIG. 2   b  is a cross-sectional view through wafer A of  FIG. 2   a  at line  2   b — 2   b  of the resonator SOI wafer A; 
       FIG. 3   a  is a top plan view of the preferred starting material of a resonator SOI wafer B and  FIG. 3   b  is a cross-sectional view through wafer B of  FIG. 3   a  at line  3   b — 3   b  of the bottom-portion wafer B; 
       FIG. 4   a  is a cross-sectional view at line  3   b — 3   b  of the bond wafer B; 
       FIG. 4   b  is a cross-sectional view at line  2   b — 2   b  of bonded to wafer A; 
       FIG. 5   a  is a top plan view of the resonator SOI wafer A and a bottom post B′ and  FIG. 5   b  is a cross-sectional view through wafer A and bottom post B′ of  FIG. 5   a  at line  5   b — 5   b  of the resonator SOI wafer A and bottom post B′; 
       FIG. 6   a  is a top plan view of the resonator SOI wafer A and a bottom post B′ and  FIG. 6   b  is a cross-sectional view through wafer A and bottom post B′ of  FIG. 6   a  at line  6   b — 6   b  of the resonator SOI wafer A and bottom post B′ after several contacts are attached to it; 
       FIG. 7   a  is a top plan view of the preferred starting material of a base wafer C and  FIG. 7   b  is a cross-sectional view through wafer C of  FIG. 7   a  at line  7   b — 7   b  of the base wafer C; 
       FIG. 8   a  is a top plan view of the preferred starting material of the base wafer C and  FIG. 8   b  is a cross-sectional view through wafer C of  FIG. 8   a  at line  8   b — 8   b  of the base wafer C, after on both surfaces of base wafer C a silicon dioxide layer is grown; 
       FIG. 9   a  is a top plan view of the preferred starting material of the base wafer C and  FIG. 9   b  is a cross-sectional view through wafer C of  FIG. 9   a  at line  9   b — 9   b  of the base wafer C, after pillar fabrication; 
     FIG  10   a  is a top plan view of the preferred starting material of the base wafer C and  FIG. 10   b  is a cross-sectional view through wafer C of  FIG. 10   a  at line  10   b — 10   b  of the base wafer C, after on both surfaces of base wafer C a silicon dioxide layer is grown; 
       FIG. 11   a  is a top plan view of the preferred starting material of the base wafer C and  FIG. 11   b  is a cross-sectional view through wafer C of  FIG. 11   a  at line  11   b — 11   b  of the base wafer C after an ohmic contact. 
       FIG. 12   a  is a top plan view of the preferred starting material of the base wafer C and  FIG. 12   b  is a cross-sectional view through wafer C of  FIG. 12   a  at line  12   b — 12   b  of the base wafer C after front side metal deposition. 
       FIG. 13   a  is a bottom view of the preferred starting material of the base wafer C and  FIG. 13   b  is a cross-sectional view through wafer C of  FIG. 13   a  at line  13   b — 13   b  of the base wafer C after hole formation on the bottom of base wafer C; 
       FIG. 14   a  is a bottom view of the preferred starting material of the base wafer C and  FIG. 14   b  is a cross-sectional view through wafer C of  FIG. 14   a  at line  14   b — 14   b  of the base wafer C after dielectric layer deposition on the bottom of base wafer C; 
       FIG. 15   a  is a bottom view of the preferred starting material of the base wafer C and  FIG. 15   b  is a cross-sectional view through wafer C of  FIG. 15   a  at line  15   b — 15   b  of the base wafer C after Ti metal etch on the bottom of base wafer C; 
       FIG. 16   a  is a bottom view of the preferred starting material of the base wafer C and  FIG. 16   b  is a cross-sectional view through wafer C of  FIG. 16   a  at line  16   b — 16   b  of the base wafer C after hole metal plating on the bottom of base wafer C; 
       FIG. 17   a  is a bottom view of the preferred starting material of the base wafer C and  FIG. 17   b  is a cross-sectional view through wafer C of  FIG. 17   a  at line  17   b — 17   b  of the base wafer C after dielectric layer removal on the bottom of base wafer C; 
       FIG. 18   a  is a top plan view of the preferred starting material of the base wafer C and  FIG. 18   b  is a cross-sectional view through wafer C of  FIG. 18   a  at line  18   b — 18   b  of the base wafer C after front-side electrode and seal ring metal patterning and deposition on the base wafer C; 
       FIG. 19   a  is a top plan view of the preferred starting material of the base wafer C and  FIG. 19   b  is a cross-sectional view through wafer C of  FIG. 19   a  at line  19   b — 19   b  of the base wafer C after a post hole etch is carried out in the base wafer C; 
       FIG. 20   a  is a top plan view of the preferred starting material of the bottom surface of wafer A and  FIG. 20   b  is a cross-sectional view through the base wafer A, post B′, and base wafer C of  FIG. 20   a  at line  20   b — 20   b  of the base wafer A, post B′, and base wafer C; 
       FIG. 21   a  is a top plan view depicting post A′ and base wafer C and  FIG. 21   b  is a cross-sectional view through the base wafer A, post B′, and base wafer C of  FIG. 21   a  at line  21   b — 21   b  depicting post A′, post B′, and base wafer C after post formation; 
       FIG. 22   a  is a bottom view of the preferred starting material of a cap wafer D and  FIG. 22   b  is a cross-sectional view through the cap wafer D of  FIG. 22   a  at line  22   b — 22   b  of the cap wafer D; 
       FIG. 23   a  is a bottom view of the preferred starting material of a cap wafer D and  FIG. 23   b  is a cross-sectional view through the cap wafer D of  FIG. 23   a  at line  23   b — 23   b  of the cap wafer D after backside metallization; 
       FIG. 24   a  is a bottom view of the preferred starting material of a cap wafer D and  FIG. 24   b  is a cross-sectional view through the cap wafer D of  FIG. 24   a  at line  24   b — 24   b  of the cap wafer D after forming of backside cavity; 
       FIG. 25   a  is a top plan view of the preferred starting material of a cap wafer D and  FIG. 25   b  is a cross-sectional view through the cap wafer D and the base wafer C of  FIG. 25   a  at line  25   b — 25   b  of the cap wafer D bonded to the base wafer C. 
   

   DETAILED DESCRIPTION 
   The following disclosure provides the construction of a microgyroscope that has a single crystal silicon cloverleaf-shaped resonator and integrated post attached to the leaves. The microgyroscope device is fabricated by bonding two separate substrates together preferably using a gold/gold thermocompression technique; one contains the cloverleaf resonator structures fabricated from SOI and bulk silicon substrates, and the other contains the support pillars, electrode metal, and through-wafer interconnects. A fourth wafer containing an array of etched cavities is solder-bonded to the device wafer in a vacuum, thus hermetically sealing each individual microgyroscope. 
   The resonator wafer A, preferably a SOI wafer, is preferably prepared first. On a bulk silicon base  1  having a preferable thickness of ≦500 μm, which is optionally lightly-doped bulk silicon about 1e15 cm −3 , a silicon dioxide layer  2  having a preferable thickness of ≦2 μm is formed preferably by thermal oxidation at a temperature between 800° C. and 1000° C. On top of the silicon dioxide layer  2  a heavily doped silicon epi-layer, p-type, 1e19–1e20 cm −3    3  is provided having a preferable thickness of 10 μm to 20 μm, as shown in  FIGS. 1   a  and  1   b.    
   Then the cloverleaf petal and spring of the resonator wafer A is prepared. Parts of the heavily doped silicon epi-layer  3  are preferably removed by photoresist lithography, deep reactive ion etching (DRIE) and photoresist removal, as shown in  FIGS. 2   a  and  2   b . Photoresist lithography and DRIE are described in inter alia Veljko Milanovic et al. “Deep Reactive Ion Etching for Lateral Field Emission Devices”, IEEE Electron Device Letters, Vol. 21, No. 6, June 2000, which is incorporated herein by reference. 
   The process preferably comprises:
         1. The top silicon layer of the wafer is coated with a layer of photoresist.   2. Light from an illuminator is projected through a mask that contains the pattern to be created on the wafer. That light patterns that pass through the mask are projected onto the photoresist-coated layer.   3. The photoresist that is exposed to the light becomes soluble and is rinsed away, leaving miniature images of the mask pattern. It remains as an etch mask on the silicon surface of the wafer.   4. Regions unprotected by photoresist are etched preferably by gases utilizing Deep Reactive Ion Etching (DRIE). DRIE involves repeated exposure of a photoresist-masked silicon wafer to an etchant (usually SF 6 ) plasma in alternation with a passivant (usually C 4 F 8 ) plasma. So the etching process preferably cycles between etching and deposition steps several times to achieve a deep etching with a quite vertical profile. The etch rate, profile and selectivity to the mask are controlled by adjusting etch and passivation step efficiency or the time ratio of the two steps. Average etch rate is around 2.7 μm/min, and etching is terminated when the SiO 2  layer  2  is reached. The SiO 2  layer  2  serves as a stop layer.       

   5. After the DRIE process the photoresist is removed. Photoresist removal with solvents is a preferred process in the semiconductor manufacturing and is used extensively after any metal processing. Organic strippers may have any number of different components such as NMP, glycol ether, amine, and DMSO. 
   The process parameters for the photoresist lithography are preferably as follows:
         a) Resist Application:
           2.07 μm   AZI 1350J, 3500 RPM   100° C. Hotplate bake for 45 sec.   
           b) Resist Exposure:
           Photomask # C1   Time=7 sec.   Mask Offset=0.2 μm   
           c) Develop &amp; Bake:
           MF351:H 2 O, 1:5 for 60 sec   100C Hotplate Bake for 45 sec.   
               

   The bottom post wafer B is prepared next. On a bulk silicon base  1  having a preferable thickness of ≦500 μm, which is optionally lightly-doped bulk silicon layer (about 1e15 cm −3 )  2  a silicon dioxide layer, having a preferable thickness of ≦2 μm, is formed preferably by thermal oxidation between 800° C. and 1000° C. as shown in  FIGS. 3   a  and  3   b.    
   Wafer B is bonded to resonator wafer A. The bondage between heavily-doped silicon epi-layer  3  of the bottom portion of wafer A and the silicon dioxide layer  2  of the wafer B may be achieved by heating at a temperature from 800° C. to 1000° C., as diagrammatically shown in  FIGS. 4   a  and  4   b . In this process the SiO 2  layer  2  of wafer B is preferably bonded to the heavily doped silicon epi-layer,  3  of the SOI wafer A. The epi-layer  3  is preferably p-type, 1e19–1e20 cm −3 . 
   Then the bottom post B′ and rib pattern are prepared. The bulk silicon layer  1  and silicon dioxide layer  2  of the wafer B have been partially removed to yield a post B′ as shown in  FIGS. 5   a  and  5   b.    
   The process preferably comprises:
         1. Coating the top silicon layer  1  of the wafer B with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern to be created on the wafer B,   3. Washing the exposed regions of the photoresist layer and leaving an etch mask on the silicon surface of the wafer B.   4. Etching silicon layer  1  unprotected by photoresist by gases utilizing the deep reactive ion etch (DRIE).   5. Removing SiO 2  layer  2  of wafer B by CF 4 /O 2  plasma etch, and   6. Removing photoresist on the surface of the post B′.       

   Then ohmic contacts are formed. On the heavily doped silicon epi-layer  3  several contacts  4  are preferably formed by sputtering metal. The contacts  4  are preferably placed symmetrically around the post B′. The contacts  4  contain preferably Ti/Pd/Au, Ti/Pt/Au or mixtures thereof. The contacts  4  are prepared for example by photoresist lithography, wet etching the metal and removing the photoresist (photoresist spray lithography, metallization Ti/Pt/Au and metal lift-off), as shown in  FIGS. 6   a  and  6   b . Metal liftoff is a common means of creating narrow metal lines for metals. A metal liftoff process is preferably done in a spray system. The process of resist photoresist, spray lithography, metallization and metal lift-off is described for example, in inter alia, Andrea Via et al. “Metal Lift-off on InP HBTs Using Carbon Dioxide Snow Spray” (see: www1.boc.com/eco-snow/pdf/CS-MAX%202002.pdf.) 
   The process preferably comprises:
         1. Coating the heavily doped silicon epi-layer, p-type, 1e19–1e20 cm −3    3  of the wafer A by metallization with sputter metal (Ti/Pd/Au).   2. Coating metal (Ti/Pd/Au) on the layer  3  with a layer of photoresist,   3. Projecting light from an illuminator through a mask that contains the pattern, namely the places for the ohmic contacts  4  to be created, on the layer  3  of wafer A,   4. Washing the exposed regions of the photoresist layer and leaving an etch mask on the silicon surface of the wafer A, Removing the metal which is not covered by photoresist by wet etch,   5. Removing photoresist on the surface of the ohmic contacts  4 .       

   The process for photoresist spray lithography, metallization Ti/Pt/Au and metal lift-off preferably comprises:
         1. Coating layer  3  with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the places for the ohmic contacts Ti/Pt/Au  4  to be created, on the layer  3  of wafer A,   3. Washing the exposed regions of the photoresist layer and leaving an etch mask on the silicon surface of the wafer A, Removing the metal which is not covered by photoresist by wet etch,   4. Depositing Ti/Pt/Au  4  by spray lithography,   5. Removing Ti/Pt/Au  4  covering the photoresist by a metal lift-off process,   6. Stripping the remaining photoresist yielding a Ti/Pt/Au  4  pattern on the surface of wafer C.       

   Then a base wafer C is prepared. The preferred starting material  5  of the base wafer C has a preferable thickness of about ≦800 μm and preferably contains a moderately doped silicon substrate p-type, 1e 19 cm −3 , as shown in  FIGS. 7   a  and  7   b.    
   On both surfaces of the preferred starting material  5  of the base wafer C a silicon dioxide layer  2  of ≦0.3 μm-thick is grown by thermal oxidation at a temperature preferably of about 950° C., as shown in  FIGS. 8   a  and  8   b.    
   Then a pillar fabrication is carried out. From the preferred starting material  5  a thickness of preferably about 5 μm to 8 μm is removed by photoresist lithography, wet etch SiO 2  and photoresist removal, wet KOH etch of silicon and SiO 2  removal in order to obtain pillars PI, as shown in  FIGS. 9   a  and  9   b.    
   The process preferably comprises:
         1. Coating the top and bottom SiO 2  layer  2  of wafer C with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the places for the pillars PI to be created, on the top layer  2  of wafer C,   3. Washing the exposed regions of the photoresist layer and leaving an etch mask on the SiO 2  layer  2  of the wafer C,   4. Removing the SiO 2  layer  2 , which is not covered by photoresist, by CF 4 /O 2  plasma etch,   5. Removing 5–8 μm of moderate doped Si preferred starting material  5  by wet KOH etch to produce a cavity CA,   6. Removing remaining photoresist, and   7. Removing SiO 2  layer  2  on the pillars and on the bottom layer by CF 4 /O 2  plasma etch.       

   On both surfaces of the preferred starting material  5  of the base wafer C (with pillars PI) a SiO 2  layer of ≦2 μm thick is provided, preferably by thermal oxidation at a temperature of about 1050° C., as shown in  FIGS. 10   a  and  10   b.    
   An ohmic contact metal Al  6  and interconnect metal Ti/Al  7  may be attached to the preferred starting silicon material  5  of the base wafer C by photoresist spray lithography and metal deposition and liftoff, as shown in  FIGS. 11   a  and  11   b.    
   The process preferably comprises:
         1. Coating SiO 2  layer  2  with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the places for the ohmic contact Al  6  to be created on the layer  2  of wafer C,   3. Washing the exposed regions of the photoresist layer and leaving an etch mask on the SiO 2  layer  2  of the wafer C,   4. Removing the SiO 2  layer  2  by wet etch which is not covered by photoresist,   5. Depositing Al  6  by spray lithography,   6. Removing Al  6  covering the photoresist by a metal lift-off process,   7. Stripping the remaining photoresist yielding an Al  6  pattern on the surface of wafer C.       

   A layer of Ti/Pd/Au  8  was deposited preferably by Sputter Deposition of Ti/Pd/Au on the top surface, as shown in  FIGS. 12   a  and  12   b . Pd can be advantageously removed by wet etching. 
   The following process disclosed in  FIGS. 13 to 17  is a preferred process to prepare a preparing a base wafer with through-wafer interconnects as a part of a vacuum packaged integrated microgyro with thru-wafer interconnects. A hole formation was performed to produce holes  7 ′,  7 ″,  7 ′″, in the bottom of wafer C, as shown in  FIGS. 13   a  and  13   b.    
   The process preferably comprises:
         1. Coating the bottom SiO 2  layer  2  of wafer C with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the places for the holes  7  to be created, on the bottom layer  2  of wafer C,   3. Washing the exposed regions of the photoresist layer and leaving an etch mask on the SiO 2  layer  2  of the wafer C,   4. Removing the SiO 2  layer  2 , which is not covered by photoresist, by CF 4 /O 2  plasma etch,   5. Removing moderate doped Si preferred starting material  5  by Deep DRIE of Si to produce the holes  7 ,   6. Removing remaining photoresist       

   A Si 3 N 4  layer  9  is preferably provided on the bottom of base wafer C preferably by PECVD of Si 3 N 4  deposition, wherein a Si 3 N 4  layer  9 ≦1.0 μm thick is preferably provided, as shown in  FIGS. 14   a  and  14   b.    
   A dielectric layer and Titanium metal etch at the bottom of wafer C is performed. The horizontal layer of Si 3 N 4    9  in the holes  7 ″ and  7 ′″ on the bottom of the base wafer C is removed, as shown in  FIGS. 15   a  and  15   b.    
   The process preferably comprises:
         1. Coating the bottom Si 3 N 4    9  layer of wafer C with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the places for the holes  7  to be created, on the bottom layer  9  of wafer C,   3. Washing the exposed regions of the photoresist layer and leaving an etch mask on the Si 3 N 4    9  layer in the holes  7 ″ and  7 ′″ of the wafer C,   4. Removing the Si 3 N 4    9  layer in the holes  7 ″ and  7 ′″ which is not covered by photoresist, by CF 4 /O 2  plasma etch,   5. Ion Mill treatment of Ti metal layer to expose Pd metal of Ti/Pd/Au  8  for electroplating and   6. Removing remaining photoresist.       

   A hole metal plating is carried out at the bottom of wafer C. The holes  7  on the bottom of the base wafer C are electroplated by copper electroplating, as shown in  FIGS. 16   a  and  16   b.    
   The process preferably comprises:
         1. Coating the bottom Si 3 N 4    9  layer of wafer C with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the places for the holes  7  to be created, on the bottom layer  9  of wafer C,   3. Washing the exposed regions of the photoresist layer and leaving an etch mask on the Si 3 N 4    9  layer in the holes  7  of the wafer C,   4. Electroplating with copper  14  in the holes  7 , and   5. Removing remaining photoresist.       

   Si 3 N 4    9  layer on the bottom of the wafer C was then removed preferably by CF 4 /O 2  as shown in  FIGS. 17   a  and  17   b.    
   Seal ring metal Ti/Pd/Au  8   a , drive/sense electrodes Ti/Pd/Au  8   b  and wafer bonding metal Ti/Pt/Au  8   c  may be provided by photoresist lithography and metal deposition and liftoff, as shown in  FIGS. 18   a  and  18   b.    
   The process preferably comprises:
         1. Coating the top surface layer Ti/Pd/Au  8  layer of wafer C with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the places were Ti/Pd/Au  8  layer shall be removed on the top of wafer C,   3. Washing the exposed regions of the photoresist layer and leaving an etch mask on the Ti/Pd/Au  8  layer on the wafer C,   4. Wet etching of Ti/Pd/Au  8  and creating seal ring metal Ti/Pd/Au  8   a , drive/sense electrodes Ti/Pd/Au  8   b  and wafer bonding metal Ti/Pt/Au  8   c , and   5. Removing remaining photoresist.       

   As a next step a post hole etch  5 ′ is preferably carried out by photoresist lithography (spray on thick resist), CF 4 /O 2  plasma etch of silicon dioxide in the hole region, DRIE of silicon hole and photoresist removal as shown in  FIGS. 19   a  and  19   b.    
   The process preferably comprises:
         1. Coating the top surface of wafer C with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the place for the hole region on the top surface of wafer C,   3. Washing the exposed regions of the photoresist layer and leaving a mask on the top surface of the wafer C,   4. CF 4 /O 2  plasma etch of silicon dioxide in the hole region,   5. DRIE remove to create a silicon hole  5 ′, and   6. Stripping the remaining photoresist layer.       

   As a next step a bonding of resonator wafer A according to  FIG. 6   b  and to base wafer C according to  FIG. 19   b  is carried out preferably by an Au to Au thermocompression bond at a temperature of 300° C. to 400° C., as shown in  FIGS. 20   a  and  20   b . The bonding is carried out between the contacts  4  of resonator wafer A-B and the seal ring metal  8   a  of the base wafer C. Post B′ of resonator wafer A-B fits into the post hole  5 ′ of base wafer C. 
   The post fabrication on wafer A is preferably carried out by photoresist lithography (spray on thick resist), CF 4 /O 2  plasma etching of silicon dioxide, photoresist removal by dry etch. Thereby a post A′ and optional frame formation in the top layer A″ is obtained, as shown in  FIGS. 21   a  and  21   b.    
   The process preferably comprises:
         1. Coating the top surface of wafer A with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the place for the hole region on the top surface of wafer A,   3. Washing the exposed regions of the photoresist layer and leaving a mask on the top surface of the wafer A,   4. DRIE remove of silicon from wafer A,   5. CF 4 /O 2  plasma etch of silicon dioxide from wafer A, whereby a post A′ and optional frame formation in the top layer A″ is obtained, and   6. Stripping the remaining photoresist layer.       

   A cap wafer D is prepared with a preferred starting material of lightly doped bulk silicon  1  having a thickness of ≦800 μm and having on top and bottom a thin silicon dioxide layer  2 , as shown in  FIGS. 22   a  and  22   b.    
   A backside metallization is carried out by photoresist lithography and metal deposition and liftoff. Thereby Ti/Pt/Au  8  and solder metal  12  are attached, as shown in  FIGS. 23   a  and  23   b.    
   The process preferably comprises:
         1. Coating the bottom surface of cap wafer D with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the places for seal ring Ti/Pt/Au  8  and solder metal  12  to be attached, on the bottom surface of wafer cap wafer D,   3. Washing the exposed regions of the photoresist layer and leaving a mask on the top surface of the wafer D,   4. Depositing Ti/Pt/Au on the bottom surface of cap wafer D,   5. Depositing solder metal  12  on the bottom surface of cap wafer D,   6. Removing excess Ti/Pt/Au  8  and solder metal  12  covering the photoresist by a metal lift-off process,   7. Stripping remaining photoresist yielding a seal ring Ti/Pt/Au  8  and solder metal  12 .       

   Then backside cavity  13   a  is preferably formed on the cap wafer D by spraying thick photoresist on the backside, DRIE etch of SiO 2 , DRIE cavities and remove photoresist, as shown in  FIGS. 24   a  and  24   b.    
   The process preferably comprises: 
   
       
       
         
           1. Coating the bottom silicon dioxide layer  2  of the cap wafer D with a layer of photoresist, 
           2. Projecting light from an illuminator through a mask that contains the pattern to be created on bottom layer  2  of the cap wafer D, 
           3. Washing the exposed regions of the photoresist layer and leaving an etch mask on the bottom silicon dioxide layer  2  of the cap wafer E, 
           4. Removing SiO 2  layer  2  of wafer B by CF 4 /O 2  plasma etch, 
           5. Etching silicon layer  1  unprotected with photoresist by gases utilizing the deep reactive ion etch (DRIE) on the bottom of the cap wafer D, and 
           6. Removing photoresist from the bottom silicon dioxide layer  2  of the cap wafer D yielding two cavities  13 . 
         
       
     
  
   The cap wafer D is preferably bonded to the base wafer C. The cap wafer D is positioned on top of base wafer C. A solder bond is carried out at low temperature at about 200° C. between the solder metal  12  of the cap wafer D and the seal ring metal  8   a  of the base wafer C, as shown in  FIGS. 25   a  and  25   b.    
   The present invention can be used for cell phone applications where the gyros are mounted directly on a PC board. In addition, for high g applications, the changes in the stray capacitance that can occur if the wire bonded interconnects move can create false signals and noise. Finally, if vertical stacking of the Si microgyro with its ASIC is desirable for 3-D (but separate wafer) integration, ball-grid array interconnect techniques are necessary. 
   This invention is extremely important in the overall packaging concepts for I*Star inertial instruments. Different customers require different package and interconnect designs for use in their products. Automotive users still prefer to use wire bonding and plastic hybrid packages for many of their applications. However, other users such as wireless manufacturers or military users such as Raytheon will require even lower cost and more rugged packaging concepts. In general, the IC industry is moving toward ball-grid array technology for advanced packaging designs. 
   Finally, the manufacturing yield and vacuum lifetime may be improved with the present design since the solder on the capping wafer seal ring makes a vacuum seal to a completely planar metal seal ring on the base wafer. The previous design could produce undulations in the bottom seal ring due to the Ti/Al interconnects. 
   Although certain preferred embodiments of the present invention have been described above, these should not be construed as limiting the scope of the invention but as merely providing illustrations of some of the presently preferred embodiments of this invention. Those skilled in the art will appreciate the fact that both the order in which the described processes are carried out and the described process parameters may be varied if needed to suit local requirements.