Abstract:
The present invention is a method for manufacturing a semiconductor apparatus including a chip which is fabricated in large numbers on a wafer and has a plurality of information blocks. In the method, a unique information bit is written in a chip discrimination block of each chip  10  within a shot, which is a segmented region of the wafer, by a fixed pattern method. In addition, an information bit uniquely given to each shot within the wafer is written by a mask shift method. Further, an information bit uniquely given to each wafer is written in a wafer discrimination block of the chip  10  which is fabricated on the wafer by the mask shift method and mask combination method.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the foreign priority benefit under Title 35, United States Code, §119(a)-(d) of Japanese Patent Application No. 2007-243552, filed on Sep. 20, 2007, the contents of which are hereby incorporated by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a semiconductor apparatus and a method for manufacturing the semiconductor apparatus, which can easily verify a reliability of a written bit. 
         [0004]    2. Description of Related Art 
         [0005]    An RFID tag attached to an individual product to label the product is required to readably store a unique identifier for avoiding confusion with another RFID tag. Therefore, the identifier has been written in a semiconductor chip constituting the RFID tag using an electron beam direct writing apparatus (EB apparatus). In the method described above, since a bit is written by aligning an individual memory cell, a long time is required for writing one semiconductor chip, thereby, improvement of the productivity has been difficult. In addition, since the EB apparatus is expensive, reduction of the manufacturing cost has been difficult. 
         [0006]    In the meantime, a “method for manufacturing semiconductor apparatus” which is used for obtaining a semiconductor chip having a different random number for each wafer by using the following processes has been disclosed in Japanese Patent Laid-open Publication No. 2005-347597 (paragraphs [0011], [0020], FIG. 1 to FIG. 4). In the method, first, (1) combine a plurality of reticles having a random number and an error detection code; next, (2) in the reticle, a large number of contact holes larger than that of intersection points between bit-lines and word-lines are disposed in an area larger than the area where the bit-lines and word-lines are formed; then, a relative position between the bit-lines and word-lines is displaced for each wafer with reference to an alignment mark. As a result, the semiconductor chip having a different random number for each wafer is obtained. 
       SUMMARY OF THE INVENTION 
       [0007]    However, in the “method for manufacturing semiconductor apparatus” (Japanese Patent Laid-open Publication No. 2005-347597), as described in (1), if it is tried to prepare various kinds of random numbers only by combinations of the reticles, a large number of various kinds of reticles are required. Therefore, as described in (2), it is required to combine the method which displaces the relative position between the contact holes and intersection points of the bit-lines and word-lines. However, in the method (2), since the error detection code has a one-to-one correspondence with the random number, the method described above can not be combined to (1). 
         [0008]    The present invention has been developed considering the above problems. It is, therefore, an object of the present invention to provide a semiconductor apparatus and a method for manufacturing the semiconductor apparatus, which can easily verify a written bit. 
         [0009]    To solve the problems described above, the method for manufacturing a semiconductor apparatus according to the present invention provides a method which includes steps of: a chip discrimination block writing step for writing a first information bit which is uniquely given to each chip included in a shot in a first information block of the chip; a shot discrimination block writing step for writing a second information bit which is uniquely given to each shot in the wafer in a second information block of the chip; and a wafer discrimination block writing step for writing a third information bit which is uniquely given to each of the wafers in a third information block of the chip fabricated on the wafer. 
         [0010]    In regard to specific methods of the present invention other than the above, spirits of the technology will be described through, for example, “DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT”. 
         [0011]    According to the present invention, a semiconductor apparatus and a method for manufacturing the semiconductor apparatus, which can easily verify a written bit, can be provided. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]      FIG. 1  is an illustration for explaining a utilization example of a chip according to one embodiment of the present invention; 
           [0013]      FIG. 2  is a conceptual illustration showing a verification principle of a storing content in a chip according to the present invention; 
           [0014]      FIG. 3A  to  FIG. 3D  are illustrations for explaining a data structure and a memory structure to be stored in a chip; 
           [0015]      FIG. 4  is a block diagram of hardware of a chip showing units related to a read only memory; 
           [0016]      FIG. 5  is an illustration showing a layout of a memory; 
           [0017]      FIG. 6A  and  FIG. 6B  are illustrations for explaining a pattern formation example by a mask shift method in details; and 
           [0018]      FIG. 7  is a flowchart showing a verifying operation example of a memory in a chip  10 . 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0019]    Next, one embodiment of the present invention will be explained in details by referring to figures. 
         [0020]      FIG. 1  is an illustration for explaining a utilization example of a chip  10  according to one embodiment of the present invention. 
         [0021]    An RFID tag  11  includes a base film  13  made of dielectric material such as polyimide, a tag antenna  12  formed on the base film  13  by an electrically conductive film such as aluminum or copper, and the chip  10  connected to power supply points of the tag antenna  12 . The RFID tag  11  constituted as described above is called an inlet. In addition, the RFID tag  11  is a passive device which is activated by taking in an external electromagnetic energy. 
         [0022]    The chip  10  is a semiconductor apparatus for an RFID, and includes, for example, a non-volatile storage function, a signal transmission/reception function, a signal modulation/demodulation function, a power extraction function from a received signal, and an arithmetic control function. The chip  10  is typically a one-chip IC integrating the functions described above like a μ-chip (registered trademark) which is manufactured by the assignee of the present invention. 
         [0023]    It is noted that if simply written as “memory” in the explanation, the “memory” may mean a non-volatile storage area which is formed (written) during a semiconductor fabrication process of the chip  10 . 
         [0024]    A reader unit  20  includes a reader unit body  21  and a reader antenna  22  connected to the reader unit body  21 . 
         [0025]    The reader unit body  21  transmits a modulated questioning signal to the reader antenna  22  so that a power supply, a clock supply, and a command transmission can be implemented. The reader antenna  22  transforms the questioning signal into electromagnetic waves or electromagnetic fields to radiate the waves or fields in the air. 
         [0026]    In addition, the reader antenna  22  receives an answering signal radiated from the RFID tag  11  and transforms the signal into a high frequency current to transmit to the reader unit body  21 . The reader unit body  21  demodulates the high frequency current to take out data, and transmits the date to other units (not shown) and a display unit (not shown) for displaying a data list on the display unit. 
         [0027]    In the tag antenna  12  of the RFID tag  11 , a L-shaped slit is disposed to form a stub for impedance matching, and the chip  10  is connected to this area (stub side and opposite side of the stub across the slit) as the power supply points. With the configuration described above, a capacitance of the chip  10  is compensated by an inductance of the stub, and thereby, a side of the chip  10  and a side of the tag antenna  12  are impedance-matched. As a result, a signal loss of the transmission/reception can be reduced. In addition, the RFID tag  11  may use other devices having identical functions to those described above, for example, the chip  10  on which an antenna coil (not shown) is formed. 
         [0028]      FIG. 2  is a conceptual illustration showing a verification principle of a storing content in the chip  10  according to the present invention. 
         [0029]    A pattern of a non-volatile storage area of the chip  10  (see  FIG. 1 ) is formed by combination of a “mask shift method”, a “mask combination method” described later, and a “fixed pattern method”. It is noted that a unit for conducting verification, which will be described later, is expressed as a comparator unit P 20 . 
         [0030]    With respect to the “mask shift method”, a “verification pattern P 12  for formed pattern by mask shift method” is formed in the chip  10  (see  FIG. 1 ) as well as a “formed pattern P 11  by mask shift method”. The “verification pattern P 12  for formed pattern by mask shift method” is formed by a procedure identical to that of the “formed pattern P 11  by mask shift method”, and has the same pattern with the “formed pattern P 11  by mask shift method”. That is, if there is no error in each pattern (P 11 , P 12 ), the same data can be obtained from the both patterns (P 11 , P 12 ). 
         [0031]    If a part of data obtained from each of the patterns (P 11 , P 12 ) is not identical, it means that there is an error in one of the “formed pattern P 11  by mask shift method” and the “verification pattern P 12  for formed pattern by mask shift method”. Since a probability that the error is in the “formed pattern P 11  by mask shift method” is half, practically, the chip  10  corresponding to the error may be scrapped as a defective chip without checking which pattern (P 11 , P 12 ) contain the error. In addition, a probability to generate an error when a pattern is formed is extremely small. Therefore, in a single chip  10 , since a probability that a given portion in the “formed pattern P 11  by mask shift method” and a portion corresponding to the given portion in the “verification pattern P 12  for formed pattern by mask shift method” are both errors is expressed as a square value of the extremely small probability, practically, a undetected probability of the defective portion is negligible small. 
         [0032]    Specifically, identical data strings are read out from the “formed pattern P 11  by mask shift method” and the “verification pattern P 12  for formed pattern by mask shift method”, next, each of the read out data strings is compared each other, and the obtained comparison result is checked up. For example, address numbers of the two patterns (P 11 , P 12 ) are read out in ascending order, and each data of the data strings corresponding to the identical address number (that is, in read out order) is conducted XOR (exclusive OR) operation to calculate a data string. If values of the data string are composed of only “0” (zero), it means that the chip  10  of this verification is good, and if the data string contains a value “1”, it means that the chip  10  of this verification is a defective one. 
         [0033]      FIG. 3A  to  FIG. 3D  are illustrations for explaining a data structure and a memory structure to be stored in a chip; 
         [0034]    As shown in  FIG. 3A , a data string stored in the chip  10  includes, in ascending order of the address number, a chip header composed of a header and an extension, a service header composed of a class identifier and a service ID, an application data composed of a user data and a unique ID, an error detection circuit output result (EDC), an extension header composed of a header and an extension, and an ID verification data. 
         [0035]    The chip header indicates that the chip  10  is a predetermined type of RFID chip (for example, μ-chip (registered trademark)). The service header is determined by, for example, specifications of the chip  10 . The application data is composed of the user data defining a user of the chip  10  and the unique data identifying each chip  10 . The “error detection circuit output result” (EDC) is data generated from the chip header, the service header, and the application data for verifying the chip header, the service header, and the application data. The ID verification data is data for verification generated from data other than the ID verification data. 
         [0036]    As shown in  FIG. 3B , a memory block of the chip  10  includes, in ascending order of the address number and corresponding to the data string stored in the chip  10  shown in  FIG. 3A , a chip header block storing the chip header, a service header block storing the service header, a user data block storing the user data in the application data, a unique ID block storing the unique ID, an EDC block storing the “error detection circuit output result” (EDC), an extension header block storing the extension header, and an extension data block storing the ID verification data. 
         [0037]    The ID verification data to be stored in the extension data block includes (1) a chip header verification number, (2) a service header verification number, (3) a user data verification number, (4) a verification number of the mask combination method in a wafer discrimination block, (5) a chip discrimination block verification number, and (6) an extension header verification number. Each of these data described above is cross-checked with data, which is subjected to a predetermined processing, corresponding to each block, and as a result, the data stored in the each block can be verified whether the data is correct or not. 
         [0038]    The unique ID is a unique identifier for a combination of a same chip header, a same service header, and a same user data, and given to each chip  10 . 
         [0039]    As shown in  FIG. 3C , the unique ID block includes a wafer discrimination block which indicates a wafer from which the chip  10  is taken out, a shot discrimination block which indicates a shot with which the chip  10  is formed, and a chip discrimination block which indicates a location of the chip  10  in the shot. 
         [0040]    As shown in  FIG. 3D , the wafer discrimination block is composed of a memory formation area formed by the “mask combination method” and the memory formation area formed by the “mask shift method”. The shot discrimination block is composed of the memory formation area formed by the “mask shift method”. The chip discrimination block is composed of the memory formation area formed by the “fixed pattern method”. 
         [0041]    Alternately, the wafer discrimination block may be composed of the memory formation area formed by the “mask shift method” without using the “mask combination method”. 
         [0042]    It is noted that the “mask combination method” is a method for forming different memory patterns on the chip  10  by combining different masks (reticles). In the method, more masks are required for increasing the different memory patterns. 
         [0043]    The “mask shift method” is a method for obtaining different memory patterns by changing a relative position between the chip  10  (surface) and the mask by the pitch of a bit-line or a word-line (both not shown) of the memory as a unit. The “mask shift method” will be described later in details by referring to  FIG. 6A  and  FIG. 6B . 
         [0044]    The “fixed pattern method” is a method for forming a memory pattern by arranging an original master on which a pattern image is formed at slightly above a wafer or on the wafer for exposure. Since the pattern image is different in each portion corresponding to the chip  10 , the chip  10  which is obtained from an area formed by the “fixed pattern method” in the same wafer has a unique pattern in the wafer. 
         [0045]      FIG. 4  is a block diagram of hardware of a chip  10  showing units related to a read only memory. 
         [0046]    The chip  10  includes a power source circuit  31 , an arithmetic processing control circuit  32 , a memory circuit  40 , a memory content verification circuit  50 , an EDC generation circuit  34 , a verification circuit  33 , and a bit-length compression circuit  35 . 
         [0047]    The chip  10  is connected to the tag antenna  12  (see  FIG. 1 ) which is located outside the chip  10  through an antenna pad  36  disposed in the package of the chip  10 . When the chip  10  is tested without using the tag antenna  12 , the antenna pad  36  functions as a test pad, and a test equipment (not shown) is connected to the test pad (antenna pad  36 ) instead of the tag antenna  12 . Since the chip  10  according to the present embodiment has a memory verification mechanism, a memory test and a communication test can be concurrently conducted (partial overlapping of time of the both tests may be sufficient) by connecting the tag antenna  12  to the antenna pad  36 , and each test result of the memory test and the communication test can be obtained separately. Of course, the following processes may be taken. First, the memory test of the chip  10  is conducted by connecting a test equipment to the test pad (antenna pad  36 ), and subsequently the communication test is conducted by connecting the tag antenna  12  to the antenna pad  36 . 
         [0048]    The power source circuit  31  extracts an electric power and a clock from a high frequency current (questioning signal) transmitted from the tag antenna  12  to supply to each part of the chip  10 . The power source circuit  31  also has a modulation/demodulation function and transmits a data signal, which is input from the antenna pad  36 , to the arithmetic processing control circuit  32  after demodulating the data signal, and also transmits a data signal received from the arithmetic processing control circuit  32  to the outside through the antenna pad  36  after modulating the data signal. 
         [0049]    The arithmetic processing control circuit  32  is a microcomputer, and controls operations of each unit as well as conducts various kinds of processing in the chip  10 , and further, has a function to intermediate between the data transmission and data reception. 
         [0050]    The memory circuit  40  includes a fixed mask pattern  41  formed by the “fixed mask method”, a mask combination pattern  42  formed by the “mask combination method”, and a mask shift pattern  43  formed by the “mask shift method”. 
         [0051]    The memory content verification circuit  50  includes a fixed mask pattern verification pattern  51  formed by the “fixed mask method”, a mask combination pattern verification pattern  52  formed by the “mask combination method”, and a mask shift pattern verification pattern  53  formed by the “mask shift method”. 
         [0052]    If there is no error, the fixed mask pattern  41  is identical to the fixed mask pattern verification pattern  51 , the mask combination pattern  42  is identical to the mask combination pattern verification pattern  52 , and the mask shift pattern  43  is identical to the mask shift pattern verification pattern  53 . Therefore, if there is no error, patterns in the memory circuit  40  are identical to those in the memory content verification circuit  50 . 
         [0053]    The verification circuit  33  reads out data one by one (for example, by one-bit) in a predetermined order (for example, in ascending order of address number) from the memory circuit  40  and the memory content verification circuit  50  based on a control of the arithmetic processing control circuit  32  and conducts, for example, XOR operation to verify the identity of the both data, then, outputs the verification result to the arithmetic processing control circuit  32 . 
         [0054]    The EDC generation circuit  34  reads out data from the memory circuit  40  and generate an EDC to transmit to the verification circuit  33 . 
         [0055]    The verification circuit  33  compares the EDC generated by the EDC generation circuit  34  with an EDC which is read out from the memory circuit  40 , and transmits the verification result to the arithmetic processing control circuit  32 . 
         [0056]    The bit-length compression circuit  35  compresses data readout from the memory circuit  40  and transmits the compressed data to the arithmetic processing control circuit  32 . This is a process for compressing a redundancy of the mask shift pattern  43  since the mask shift pattern  43  especially has a redundant structure. Since on-chip data compression is adopted, a communication error probability of the communication through the tag antenna  12  can be reduced, and also, a communication load and a communication time can be reduced. Further, the read out data can be treated as a compact random number. 
         [0057]    The arithmetic processing control circuit  32  transmits the data (information), which is obtained as described above, outside the chip  10  through the power source circuit  31 . 
         [0058]    The arithmetic processing control circuit  32  also transmits the data outside the chip  10  by adding an error detection result received from the verification circuit  33 . However, when there is an inconsistency in the documented content of the “mask combination method” or the “mask shift method”, the arithmetic processing control circuit  32  transmits an occurrence of error of the memory content in the chip  10  outside the chip  10  by making a part or all of the verification result generated by the verification circuit  33  in a specific pattern (form) which is easily distinguished from other data. Through this, when the RFID tag  11  is read by the reader unit  20  (see  FIG. 11 ), an error in a reading operation by a wireless communication can be discriminated from a defect of the memory in the chip  10 . This is a big advantage for implementing a quality assurance of a product. 
         [0059]      FIG. 5  is an illustration showing a layout of a memory. 
         [0060]    In the illustration, each element on the left is a block in the memory body and each element on the right is a verification block for verifying the memory. 
         [0061]    The block on the left and the block on the right corresponding to the block on the left are fabricated with the same processes. 
         [0062]    Therefore, each block on the left and each block on the right have patterns which have one-to-one correspondence to each other. 
         [0063]      FIG. 6A  and  FIG. 6B  are illustrations for explaining a pattern formation example by a mask shift method in details. 
         [0064]    The illustrations show a writing example of a predetermined bit-string in the chip  10  which has a 16-bits (4-bits×4-bits) memory capacity. 
         [0065]    As shown in  FIG. 6A , a memory cell  61  and an alignment pattern  62  are formed in the chip  10 . 
         [0066]    In addition, as shown in  FIG. 6B , in a reticle  70 , a memory bit writing pattern  71  is bored and an alignment pattern  72  is formed. 
         [0067]    The memory cell  61  is written as follows. The reticle  70  is set slightly above the chip  10 . Decoders  63 ,  64  read a relative displacement between the alignment patterns  62  and  72 , while referring to a relative position between the alignment patterns  62  and  72 . A stepper receives the position information from a position detection circuit  65 . Then, a target memory cell  61  is exposed through the memory bit writing pattern  71 . 
         [0068]    In the present embodiment, a number of the memory bit writing pattern  71  is small, for example, one to several, and an area where the memory cell  61  is formed is made relatively large. Through this, an exposure light for the memory bit writing pattern  71  is used for exposing the memory cell  61  without wasting the light by leaking outside the target area. Therefore, a verification of a memory formation by the “mask shift method” can be conducted using, for example, the chip discrimination block verification number (see  FIG. 3B ). 
         [0069]    It is noted that in the feature described above, data becomes redundant. However, the data can be utilized with a compact form by using the data processed by the bit-length compression circuit  35  (see  FIG. 4 ). 
         [0070]    In addition, it is noted that in a “chip discrimination block writing process”, content of a memory is written by the “fixed pattern method”. Similarly, in a “shot discrimination block writing process”, content of a memory is written by the “mask shift method”. Also, in a “wafer discrimination block writing process”, content of a memory is written by the “mask shift method” (or by “mask shift method” and “fixed pattern method”). 
         [0071]      FIG. 7  is a flowchart showing a verifying operation example of a memory in a chip  10  (see  FIG. 1  and  FIG. 4  as appropriate). 
         [0072]    First, the power source circuit  31  receives electromagnetic waves through the tag antenna  12  (Step S 101 ). 
         [0073]    If there is no reception of the electromagnetic waves (Step S 102 : No), the step returns to Step S 101  and continuously receives the electromagnetic waves. 
         [0074]    If the electromagnetic waves are received (Step S 102 : Yes), the power source circuit  31  is activated (Step S 103 ) and an electric power and a clock are supplied to each unit in the chip  10 . 
         [0075]    Then, a whole chip  10  is activated (Step S 104 ). 
         [0076]    Subsequently, the arithmetic processing control circuit  32  receives a command through the power source circuit  31  (Step S 105 ). 
         [0077]    If there is no reception of the command (Step S 106 : No), the step returns to Step S 105  and continuously receives the command. 
         [0078]    If the command is received (Step S 106 : Yes), the arithmetic processing control circuit  32  resets (Step S 107 ) a built-in memory counter (not shown), and the memory counter starts operation (Step S 108 ). 
         [0079]    Next, the bit-length compression circuit  35 , the EDC generation circuit  34 , and the verification circuit  33  read out data of the memory (Step S 109 ). 
         [0080]    Then, the bit-length compression circuit  35  conducts a bit-length compression (Step S 110 ) of the data read out from the memory circuit  40  and transmits the compressed data to the arithmetic processing control circuit  32 . 
         [0081]    In addition, the EDC generation circuit  34  generates an EDC (Step S 111 ) by using data read out from the memory circuit  40 , and transmits the generated EDC to the verification circuit  33 . 
         [0082]    The verification circuit  33  conducts a data verification (Step S 112 ) based on the received EDC, and transmits data (verified data) showing the verification result to the arithmetic processing control circuit  32 . 
         [0083]    The arithmetic processing control circuit  32  transmits data, which is compressed by the bit-length compression circuit  35 , outside the chip  10  through the power source circuit  31  (Step S 113 ). 
         [0084]    The arithmetic processing control circuit  32  also transmits the EDC, which is generated by the EDC generation circuit  34 , outside the chip  10  through the power source circuit  31  (Step S 114 ). 
         [0085]    The arithmetic processing control circuit  32  further transmits the verified data, which is generated by the verification circuit  33 , outside the chip  10  through the power source circuit  31  (Step S 115 ). 
         [0086]    When a series of the processing is completed, the step returns to the first step and repeats the processing again. 
         [0087]    Other than the chip  10  for the FRID tag, the present embodiment described above is widely applicable for verifying whether a unique data stored in a device to be identified is correct or not, while discriminating a reason of an error from others, and for keeping a reliability of stored data to be high.