Abstract:
A switch circuit for switching between a first storage and a second storage. The switch circuit includes a switch, first and second control circuits, a switch control chip, and a processing chip. When the second control circuit transmits power from a power supply to the first storage, the first control circuit connects the power supply to the first storage, and connects the second control circuit to the processing chip the first storage regardless of the state of the switch. When the second control circuit transmits power from the power supply to the second storage, the first control circuit connects the power supply to the second storage, and connects the processing chip to the second storage regardless of the state of the switch.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure relates to a switch circuit. 
         [0003]    2. Description of Related Art 
         [0004]    Dual systems are used for protecting information stored in handheld devices. Users can store important information in one system, and store general information in the other system. Software is generally used to switch the handheld device between the two systems. However, there are security risks. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]    Many aspects of the present embodiments can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present embodiments. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views. 
           [0006]      FIG. 1  is a block diagram of an exemplary embodiment of a switch circuit. 
           [0007]      FIGS. 2-9  are circuit diagrams of the switch circuit of  FIG. 1 . 
       
    
    
     DETAILED DESCRIPTION 
       [0008]    The disclosure, including the accompanying drawings, is illustrated by way of example and not by way of limitation. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean at least one. 
         [0009]    Referring to  FIG. 1 , an exemplary embodiment of a switch circuit is shown. The switch circuit includes a switch  10 , a first control circuit  11 , a second control circuit  12 , a switch control chip  15 , and a processing chip  18 . 
         [0010]    The switch  10  is connected to the first control circuit  11  and the second control circuit  12 . The second control circuit  12  is further connected to a first storage  100 , a second storage  200 , and a power supply  16 . The second control circuit  12  either outputs power from the power supply  16  to the first storage  100  or outputs power from the power supply  16  to the second storage  200  according to the switch  10 . The second control circuit  12  is further connected to the switch control chip  15 . The switch control chip  15  is connected to the processing chip  18 . The switch control chip  15  is further connected to the first and second storages  100  and  200 . The second control circuit  12  further controls the switch control chip  15  according to the switch  10 . The switch control chip  15  allows transmitting of data between the processing chip  18  and the first storage  100  or between the processing chip  18  and the second storage  200 . In one embodiment, the power supply  16  is a power supply V3.3, which can provide 3.3 volts. 
         [0011]    Referring to  FIGS. 2-4 , the switch  10  is a single pole double throw switch. The first control circuit  11  includes an n-channel metal oxide semiconductor field effect transistor (MOSFET) Q 1 . The second control circuit  12  includes a first accessory circuit  120  and a second accessory circuit  122 . A pole  2  of the switch  10  is connected to a power supply VDD_RTC through a resistor R 1 . A first throw  1  of the switch  10  is connected to the first accessory circuit  120 . A second throw  3  of the switch  10  is connected to the second accessory circuit  122 . The pole  2  is further connected to a drain of the MOSFET Q 1 . A source of the MOSFET Q 1  is grounded. A gate of the MOSFET Q 1  is connected to the power supply V3.3 through a resistor R 2 . The gate of the MOSFET Q 1  is further grounded through a capacitor C 1 . 
         [0012]    When the pole  2  contacts the first throw  1 , the first accessory circuit  120  supplies power to the first storage  100 , and data can be transmitted between the processing chip  18  and the first storage  100 . When the pole  2  contacts the second throw  3 , the second accessory circuit  122  supplies power to the second storage  200 , and data can be transmitted between the processing chip  18  and the second storage  200 . 
         [0013]    Referring to  FIG. 3 , the first accessory circuit  120  includes n-channel MOSFETs Q 2 -Q 5  and a p-channel MOSFET Q 6 . The first throw  1  is grounded through a resistor R 3 . The first throw  1  is further connected to a gate of the MOSFET Q 2 . A source of the MOSFET Q 2  is grounded. A drain of the MOSFET Q 2  is connected to the power supply V3.3 through a resistor R 4 . The drain of the MOSFET Q 2  is connected to a drain of the MOSFET Q 3 . A source of the MOSFET Q 3  is grounded. A gate of the MOSFET Q 3  is grounded through a capacitor C 2 . The drain of the MOSFET Q 2  is connected to a gate of the MOSFET Q 4 . A source of the MOSFET Q 4  is grounded. A drain of the MOSFET Q 4  is connected to the power supply V3.3 through a resistor R 5 . The drain of the MOSFET Q 4  is grounded through a capacitor C 3 . The drain of the MOSFET Q 4  is further connected to a gate of the MOSFET Q 5 . A source of the MOSFET Q 5  is grounded. A drain of the MOSFET Q 5  is connected to the power supply V3.3 through resistors R 6  and R 7  connected in series. A node between the resistors R 6  and R 7  is connected to a gate of the MOSFET Q 6 . The node between the resistors R 6  and R 7  is further connected to a source of the MOSFET Q 6  through a capacitor C 4 . The power supply V3.3 is further grounded through a capacitor C 5 . A drain of the MOSFET Q 6  is grounded through capacitors C 6  and C 7  connected in parallel. The drain of the MOSFET Q 6  is further connected to power terminals VCC 0  and VCC 1  of the first storage  100  (shown in  FIG. 8 ) for outputting a first power signal HDD_PWR 1  to the first storage  100 . The gate of the MOSFET Q 3  is further connected to the drain of the MOSFET Q 6  through a resistor R 8 . 
         [0014]    Referring to  FIG. 4 , the second accessory circuit  122  includes an n-channel MOSFETs Q 7 -Q 10  and a p-channel MOSFET Q 11 . The second throw  3  of the switch  10  is grounded through a resistor R 9 . The second throw  3  is further connected to a gate of the MOSFET Q 7 . A source of the MOSFET Q 7  is grounded. A drain of the MOSFET Q 7  is connected to the power supply V3.3 through a resistor R 10 . The drain of the MOSFET Q 7  is further connected to a drain of the MOSFET Q 8 . A source of the MOSFET Q 8  is grounded. A gate of the MOSFET Q 8  is grounded through a capacitor C 8 . The drain of the MOSFET Q 7  is connected to a gate of the MOSFET Q 9 . A source of the MOSFET Q 9  is grounded. A drain of the MOSFET Q 9  is connected to the power supply V3.3 through a resistor R 11 . The drain of the MOSFET Q 9  is further grounded through a capacitor C 9 . The drain of the MOSFET Q 9  is further connected to a gate of the MOSFET Q 10 . A source of the MOSFET Q 10  is grounded. A drain of the MOSFET Q 10  is connected to the power supply V3.3 through resistors R 12  and R 13  connected in series. A node between the resistors R 12  and R 13  is connected to a gate of the MOSFET Q 11 . The node between the resistors R 12  and R 13  is further connected to a source of the MOSFET Q 11  through a capacitor C 10 . The power supply V3.3 is further grounded through a capacitor C 11 . A drain of the MOSFET Q 11  is grounded through capacitors C 12  and C 13  connected in parallel. The drain of the MOSFET Q 11  is connected to power terminals VCC 0  and VCC 1  of the second storage  200  (shown in  FIG. 9 ) for outputting a second power signal HDD_PWR 2  to the second storage  200 . The gate of the MOSFET Q 8  is further connected to the drain of the MOSFET Q 11  through a resistor R 14 . The drain of the MOSFET Q 11  is further grounded through resistors R 15  and R 16  connected in series. A node between the resistors R 15  and R 16  is for outputting a control signal SW. 
         [0015]    Referring to  FIGS. 5 to 7 , the switch control chip  15  includes a first control chip  150  and a second control chip  152 . A power terminal VCC of the first control chip  150  is connected to the power supply V3.3 through a resistor R 17 , and is grounded through a capacitor C 14 . A power terminal VCC of the second control chip  152  is connected to the power supply V3.3 through a resistor R 18 , and is grounded through a capacitor C 15 . Control terminals S of the first control chip  150  and the second control chip  152  are connected to the node between the resistors R 15  and R 16 , for receiving the control signal SW. Ground terminals GND 1  and GND 2  of the first control chip  150  and the second control chip  152  are grounded. An enable terminal OE# of the first control chip  150  is grounded through a resistor R 19 . An enable terminal OE# of the second control chip  152  is grounded through a resistor R 20 . 
         [0016]    Data terminals  1 A,  2 A,  3 A, and  4 A of the first control chip  150  are respectively connected to data terminals T 1 , T 2 , T 3 , and T 4  of the processing chip  18 . Data terminals  1 A,  2 A,  3 A, and  4 A of the second control chip  152  are respectively connected to data terminals T 5 , T 6 , T 7 , and T 8  of the processing chip  18 . Data terminals  1 B 1 ,  2 B 1 ,  3 B 1 , and  4 B 1  of the first control chip  150  are respectively connected to data terminals DQ 0 , DQ 1 , DQ 2 , and DQ 3  of the first storage  100 . Data terminals  1 B 1 ,  2 B 1 ,  3 B 1 , and  4 B 1  of the second control chip  152  are respectively connected to data terminals DQ 4 , DQ 5 , DQ 6 , and DQ 7  of the first storage  100 . Data terminals  1 B 2 ,  2 B 2 ,  3 B 2 , and  4 B 2  of the first control chip  150  are respectively connected to data terminals DQ 0 , DQ 1 , DQ 2 , and DQ 3  of the second storage  200 . Data terminals  1 B 2 ,  2 B 2 ,  3 B 2 , and  4 B 2  of the second control chip  152  are respectively connected to data terminals DQ 4 , DQ 5 , DQ 6 , and DQ 7  of the second storage  200 . The power terminals VCC 0  and VCC 1  of the first storage  100  are connected to the first accessory circuit  120  for receiving the first power signal HDD_PWR 1 . The power terminals VCC 0  and VCC 1  of the second storage  200  are connected to the second accessory circuit  122  for receiving the second power signal HDD_PWR 2 . Ground pins VSS 0  and VSS 1  of the first storage  100  and the second storage  200  are grounded. 
         [0017]    In the embodiment, a motherboard provides the power supply VDD_RTC and the power supply V3.3. The power supply VDD_RTC provides power all the time, and the power supply V3.3 provides power when the motherboard is powered on. 
         [0018]    When the pole  2  contacts the first throw  1 , the gate of the MOSFET Q 2  receives a high level signal. The MOSFET Q 2  is tuned on. During a period of 100 milliseconds after the power supply V3.3 provides power, the gate of the MOSFET Q 1  receives a low level signal. The MOSFET Q 1  is turned off. The MOSFET Q 2  remains turned on. The MOSFET Q 4  is turned off. The MOSFETs Q 5  and Q 6  are turned on. The first storage  100  is powered on. Meanwhile, the MOSFETs Q 7  and Q 11  are turned off. The second storage  200  is not powered on. In the embodiment, the resistor R 2  and the capacitor C 1  is an RC circuit. The 100 milliseconds are determined by parameters of the RC circuit. 
         [0019]    In addition, each of the control terminals S of the first control chip  150  and the second control chip  152  receives a low level signal. Moreover, each of the enable terminals OE# of the first control chip  150  and the second control chip  152  is grounded. At this time, the data terminals  1 A,  2 A,  3 A, and  4 A of the first control chip  150  are respectively connected to the data terminals  1 B 1 ,  2 B 1 ,  3 B 1 , and  4 B 1  of the first control chip  150 . The data terminals  1 A,  2 A,  3 A, and  4 A of the second control chip  152  are respectively connected to the data terminals  1 B 1 ,  2 B 1 ,  3 B 1 , and  4 B 1  of the second control chip  152 . As a result, the data terminals T 1 -T 8  of the processing chip  18  are respectively connected to the data terminals DQ 0 -DQ 7  of the first storage  100 . In other words, data can be transmitted between the first storage  100  and the processing chip  18 . 
         [0020]    Meanwhile, when the first storage  100  is powered on, the gate of the MOSFET Q 3  receives a high level signal. The MOSFET Q 3  is turned on. The gate of the MOSFET Q 4  receives a low level signal. In this condition, even if the pole  2  is connected to the second throw  3 , and the MOSFET Q 2  is turned off, the MOSFET Q 6  remains turned on. The first storage  100  is powered on. Furthermore, after the power supply V3.3 supplies power and after a 100 milliseconds delay, the gate of the MOSFET Q 1  receives a high level signal. The MOSFET Q 1  is turned on. In this condition, even if the pole  2  is connected to the second throw  3 , the control terminals S of the first control chip  150  and the second control chip  152  receive low level signals. In other words, data cannot be transmitted between the second storage  200  and the processing chip  18 . 
         [0021]    When the pole  2  contacts the second throw  3 , the gate of the MOSFET Q 7  receives a high level signal. The MOSFET Q 7  is turned on. During a period of 100 milliseconds after the power supply V3.3 provides power, the gate of the MOSFET Q 1  receives a low level signal. The MOSFET Q 1  is turned off. The MOSFET Q 9  is turned off. The MOSFET Q 10  is turned on. The MOSFET Q 11  is turned on. The second storage  200  is powered on. Meanwhile, the MOSFETs Q 2  and Q 6  are turned off. The first storage  100  is not powered on. 
         [0022]    In addition, each of the control terminals S of the first control chip  150  and the second control chip  152  receives a high level signal. Moreover, each of the enable terminals OE# of the first control chip  150  and the second control chip  152  is grounded. At this time, the data terminals  1 A,  2 A,  3 A, and  4 A of the first control chip  150  are respectively connected to the data terminals  1 B 2 ,  2 B 2 ,  3 B 2 , and  4 B 2  of the first control chip  150 . The data terminals  1 A,  2 A,  3 A, and  4 A of the second control chip  152  are respectively connected to the data terminals  1 B 2 ,  2 B 2 ,  3 B 2 , and  4 B 2  of the second control chip  152 . As a result, the data terminals T 1 -T 8  of the processing chip  18  are respectively connected to the data terminals DQ 0 -DQ 7  of the second storage  200 . In other words, data can be transmitted between the second storage  200  and the processing chip  18 . 
         [0023]    Meanwhile, when the second storage  100  is powered on, the gate of the MOSFET Q 8  receives a high level signal. The MOSFET Q 8  is turned on. The gate of the MOSFET Q 9  receives a low level signal. In this condition, even if the pole  2  is connected to the first throw  1 , and the MOSFET Q 7  is turned off, the MOSFET Q 11  remains turned on. The second storage  200  is powered on. Furthermore, after the power supply V3.3 supplies power and after a 100 milliseconds delay, the gate of the MOSFET Q 1  receives a high level signal. The MOSFET Q 1  is turned on. In this condition, even if the pole  2  is connected to the first throw  1 , the control terminals S of the first control chip  150  and the second control chip  152  receive high level signals. In other words, data cannot be transmitted between the first storage  100  and the processing chip  18 . 
         [0024]    The foregoing description of the exemplary embodiments of the disclosure has been presented only for the purposes of illustration and description and is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the above everything. The embodiments were chosen and described in order to explain the principles of the disclosure and their practical application so as to enable others of ordinary skill in the art to utilize the disclosure and various embodiments and with various modifications as are suited to the particular use contemplated. Alternative embodiments will become apparent to those of ordinary skills in the art to which the present disclosure pertains without departing from its spirit and scope. Accordingly, the scope of the present disclosure is defined by the appended claims rather than the foregoing description and the exemplary embodiments described therein.