Abstract:
A method and apparatus for post-fabrication adjustment of a delay locked loop leakage current is provided. The adjustment system includes a programmable current source that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor. The capacitor connects to a control voltage of the delay locked loop. The programmable current source includes at least one current source and switch to adjust the leakage current offset circuit. The programmable current source is selectively adjusted by a combinational logic circuit. Such control of the leakage current in the delay locked loop allows a designer to achieve a desired delay locked loop operating characteristic after fabrication of the adjustable delay locked loop.

Description:
BACKGROUND OF INVENTION 
     As the frequencies of modern computers continue to increase, the need to rapidly transmit data between chip interfaces also increases. To accurately receive data, a clock signal is often sent to help recover the data. The clock signal determines when the data should be sampled or latched by a receiver circuit. 
     The clock signal may transition at the beginning of the time the data is valid. The receiver circuit, however, may require that the clock signal transition during the middle of the time the data is valid. Also, the transmission of the clock signal may degrade as it travels from its transmission point. In both circumstances, a delay locked loop, or “DLL,” can regenerate a copy of the clock signal at a fixed phase shift with respect to the original clock signal. 
     FIG. 1 shows a section of a typical computer system component ( 100 ). Data ( 14 ) that is K bits wide is transmitted from circuit A ( 12 ) to circuit B ( 34 ) (also referred to as the “receiver circuit”). To aid in the recovery of the transmitted data, a clock signal ( 16 ) is also transmitted with the data ( 14 ). The circuits could also have a path to transmit data from circuit B ( 34 ) to circuit A ( 12 ) along with an additional clock (not shown). The clock signal ( 16 ) may transition from one state to another at the beginning of the data transmission. Circuit B ( 34 ) requires a clock signal temporally located some time after the beginning of the valid data. Furthermore, the clock signal ( 16 ) may have degraded during transmission. The DLL has the ability to regenerate the clock signal ( 16 ) to a valid state and to create a phase shifted version of the clock signal ( 16 ) to be used by other circuits. For example, the receiver circuit ( 34 ) may use the phase shifted version of the clock signal ( 16 ) as the receiver circuit&#39;s sampling signal. The receiver circuit&#39;s sampling signal determines when the input to the receiver circuit should be sampled. The performance of a DLL is critical, and the DLL must maintain a proper reference of time on the CPU, or generically, an integrated circuit. 
     FIG. 2 shows a block diagram of a typical DLL ( 200 ). Clock signal ( 201 ) is input to the DLL ( 200 ) to create a phased (i.e., delayed) output. Clock signal ( 201 ) is input to a voltage-controlled delay line ( 210 ) and to a phase detector ( 202 ). The phase detector ( 202 ) measures whether a phase difference between the clock signal ( 201 ) and an output signal, clk_out ( 217 ), of the voltage-controlled delay line ( 210 ) has the desired amount of delay. The phase detector ( 202 ) produces signals that control a charge pump ( 204 ). The phase detector ( 202 ) controls the charge pump ( 204 ) to increase or decrease its output current using up and down signals, U ( 203 ) and D ( 205 ). To ensure that the charge pump ( 204 ) maintains some nominal current output, the charge pump ( 204 ) is internally biased. The internal biasing of the charge pump ( 204 ) is dependent on bias signals, V BP  ( 209 ) and V BN  ( 211 ), generated from a bias generator ( 208 ) (discussed below). The up and down signals ( 203 ,  205 ) adjust the current output of the charge pump ( 204 ) with respect to the nominal current set by the bias signals ( 209 ,  211 ). 
     The charge pump ( 204 ) adds or removes charge from a capacitor C 1  ( 206 ), which in turn, changes a voltage potential at the input of the bias-generator ( 208 ). The capacitor ( 206 ) is connected between a power supply, V DD , and a control signal, V CTRL  ( 207 ). The bias-generator ( 208 ) produces the bias signals ( 209 ,  211 ) in response to the control signal ( 207 ), which, in turn, controls the delay of the voltage-controlled delay line ( 210 ) and maintains a nominal current output from the charge pump ( 204 ). 
     In FIG. 2, the voltage-controlled delay line ( 210 ) may be implemented using current starved elements. This means that the delays are controlled by modifying the amount of current available for charging and discharging capacitances. The linearity of a voltage controlled delay line&#39;s characteristics determines the stable range of frequencies over which the DLL ( 200 ) can operate. The output signal ( 217 ) of the voltage-controlled delay line ( 210 ) represents a phase delayed copy of clock signal ( 201 ) that is then used by other circuits. 
     Still referring to FIG. 2, the negative feedback created by the output signal ( 217 ) in the DLL ( 200 ) adjusts the delay through the voltage-controlled delay line ( 210 ). The phase detector ( 202 ) integrates the phase error that results between the clock signal ( 201 ) and the output signal ( 217 ). The voltage-controlled delay line ( 210 ) delays the output signal ( 217 ) by a fixed amount of time such that a desired delay between the clock signal ( 201 ) and the output signal ( 217 ) is maintained. 
     Accordingly, proper operation of the receiver circuit ( 34  in FIG. 1) depends on the DLL ( 200 ) maintaining a constant phase delay between the clock signal ( 201 ) and the output signal ( 217 ). 
     SUMMARY OF INVENTION 
     According to one aspect of the present invention, an integrated circuit including a clock path arranged to carry a clock signal; a power supply path arranged to receive power from a power supply; a delay locked loop operatively connected to the power supply path and the clock path, comprising a capacitor, responsive to a phase difference between the clock signal and a delayed clock signal, for storing a voltage potential; a leakage current offset circuit operatively connected to the capacitor where the leakage current offset circuit is arranged to adjust the voltage potential; a programmable current source connected to the leakage current offset circuit where the programmable current source comprises a first current source and a first switch arranged to control the leakage current offset circuit; and a combinational logic circuit operatively connected to the programmable current source where the combinational logic circuit is arranged to selectively adjust the programmable current source. 
     According to one aspect of the present invention, a method for post-fabrication treatment of a delay locked loop including generating a delayed clock signal; comparing the delayed clock signal to an input clock signal; generating a current dependent on the comparing; storing a voltage potential on a capacitor dependent on the current; adjusting a leakage current of the capacitor using a leakage current offset circuit responsive to a programmable current source where the programmable current source comprises a first current source and a first switch arranged to control the leakage current offset circuit; and selectively adjusting the programmable current source using a combinational logic circuit operatively connected to the programmable current source. 
     According to one aspect of the present invention, an integrated circuit including means for generating a delayed clock signal; means for comparing the delayed clock signal to an input clock signal; means for generating a current dependent on the means for comparing; means for storing a charge; means for storing a voltage potential on the means for storing the charge dependent on the means for generating the current; means for adjusting a leakage current of the means for storing the charge; and means for selectively adjusting the means for adjusting. 
     Other aspects and advantages of the invention will be apparent from the following description and the appended claims. 
    
    
     BRIEF DESCRIPTION OF DRAWINGS 
     FIG. 1 shows a typical computer system component. 
     FIG. 2 shows a block diagram of a prior art delay locked loop. 
     FIG. 3 shows a schematic diagram of a prior art phase detector. 
     FIG. 4 shows a schematic diagram of a prior art charge pump. 
     FIG. 5 shows a timing diagram for the phase detector shown in FIG.  3 . 
     FIG. 6 shows a block diagram of a delay locked loop with an adjustable leakage current offset circuit in accordance with an embodiment of the present invention. 
     FIG. 7 shows a block diagram of a delay locked loop with an adjustable leakage current offset circuit in accordance with an embodiment of the present invention. 
     FIG. 8 shows a schematic diagram of a programmable current source in accordance with an embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION 
     Exemplary embodiments of the invention will be described with reference to the accompanying drawings. Like items in the drawings are shown with the same reference numbers. 
     The present invention relates to an adjustment system for post-fabrication adjustment of a DLL ( 200  shown in FIG.  2 ). In FIG. 2, the DLL ( 200 ) determines the amount of delay of the voltage-controlled delay line ( 210 ) based on a voltage potential maintained by the capacitor ( 206 ). Charge may leak from the capacitor ( 206 ), which, in turn, changes the voltage potential on the capacitor ( 206 ). Accordingly, the delay of the voltage-controlled delay line ( 210 ) may drift. The adjustment system includes combinational logic that controls a leakage current offset circuit using an adjustment circuit that compensates for such a leakage current. Thus, the leakage current of the capacitor ( 206 ) may be offset so that the capacitor ( 206 ) maintains a constant voltage potential. 
     FIG. 3 shows a block diagram of a typical phase detector ( 300 ). The phase detector ( 300 ) is representative of the phase detector ( 202 ) shown in FIG.  2 . The phase detector ( 300 ) integrates the phase error that results between the clock signal ( 201 ) and the output signal ( 217 ). The clock signal ( 201 ) clocks a flip-flop ( 306 ) and the output signal ( 217 ) clocks a flip-flop ( 308 ). 
     When clock signal ( 201 ) transitions from a low state to a high state, flip-flop ( 306 ) transfers the high state created by the power supply V DD  ( 351 ) on an input of the flip-flop ( 306 ) to the up signal ( 203 ). When the output signal ( 217 ) transitions from a low state to a high state, flip-flop ( 308 ) transfers the high state created by the power supply V DD  ( 351 ) on an input of the flip-flop ( 308 ) to the down signal ( 205 ). When both the up and down signals ( 203 ,  205 ) are at a high state, the AND gate ( 303 ) outputs a high state on signal line ( 307 ). The high state on signal line ( 307 ) resets both flip-flop ( 306 ) and flip-flop ( 308 ). The up and down signals ( 203 ,  205 ) transition to a low state when the flip-flop ( 306 ) and flip-flop ( 308 ) are reset, respectively. 
     FIG. 4 shows a block diagram of a typical charge pump ( 400 ). The charge pump ( 400 ) is representative of the charge pump ( 204 ) shown in FIG.  2 . The charge pump ( 400 ) has two current sources ( 402 ,  408 ). The current source ( 402 ) provides a current based on the bias signal ( 209 ) (also shown in FIG.  2 ). The current source ( 408 ) provides a current based on the bias signal ( 211 ) (also shown in FIG.  2 ). The current source ( 402 ) is connected between the power supply V DD  ( 401 ) and the signal line ( 403 ). The current source ( 408 ) is connected between the power supply V SS  ( 407 ) and the signal line ( 405 ). 
     In FIG. 4, the up and down signals ( 203 ,  205 ) from the phase detector ( 300 ) shown in FIG. 3 determine whether switches ( 404 ,  406 ) are closed, respectively. When the up signal ( 203 ) is at a high state, the switch ( 404 ) is closed. The switch ( 404 ) is connected between signal ( 403 ) and the control signal ( 207 ). When closed, the switch ( 404 ) allows the current generated by the current source ( 402 ) to add charge to the capacitor ( 206  shown in FIG. 2) using the control signal ( 207 ). 
     When the down signal ( 205 ) is at a high state, the switch ( 406 ) is closed. The switch ( 406 ) is connected between signal ( 405 ) and the control signal ( 207 ). When closed, the switch ( 406 ) allows the current generated by the current source ( 408 ) to remove charge from the capacitor ( 206  shown in FIG. 2) using the control signal ( 207 ). 
     A short time period exists when both the up and down signals ( 203 ,  205 ) are at a high state. In FIG. 3, when both the up and down signals ( 203 ,  205 ) transition to a high state, the AND gate ( 303 ) resets the flip-flops ( 306 ,  308 ) by generating a high state on the signal line ( 307 ). A finite time duration is needed for the AND gate ( 303 ) and the flip-flops ( 306 ,  308 ) to respond to this change in state. In FIG. 4, both the switches ( 404 ,  406 ) are closed when both the up and down signals ( 203 ,  205 ) signals are high. During this time, a nominal amount of charge is added to the capacitor ( 206  shown in FIG.  2 ). Some or all of the current generated by the current source ( 402 ) is transferred to the V SS  power supply ( 407 ) through the current source ( 408 ). 
     FIG. 5 shows a timing diagram ( 500 ) for the phase detector ( 300 ) shown in FIG.  3 . The timing diagram ( 500 ) shows two clock cycles. The first clock cycle shows the output signal ( 217 ) lagging the clock signal ( 201 ) (i.e., they are out of phase). The second cycle shows the output signal ( 217 ) properly aligned with the clock signal ( 201 ). 
     In the first cycle, when the clock signal ( 201 ) transitions from a low state to a high state, the up signal ( 203 ) transitions from a low state to a high state. When the output signal ( 217 ) transitions from a low state to a high state, the down signal ( 205 ) transitions from a low state to a high state. Because both the up and down signals ( 203 ,  205 ) are at a high state, the AND gate ( 303  shown in FIG. 3) resets both flip-flops ( 306 ,  308  shown in FIG.  3 ). The up and down signals ( 203 ,  205 ) output a low state when the flip-flops ( 306 ,  308  shown in FIG. 3) are reset, respectively. 
     In the first cycle, the up signal ( 203 ) is at a high state for a longer duration than the down signal ( 205 ). Accordingly, the current source ( 402  shown in FIG. 4) adds charge to the capacitor ( 206  shown in FIG.  2 ). If the down signal ( 205 ) was at a high state for a longer duration than the up signal ( 203 ), the current source ( 408  shown in FIG. 4) would remove charge from the capacitor ( 206  shown in FIG.  2 ). The change in the voltage potential maintained by the capacitor ( 206  shown in FIG. 2) affects the delay of the voltage-controlled delay line ( 210  shown in FIG.  2 ). 
     In FIG. 5, in the second cycle, both the clock signal ( 201 ) and the output signal ( 217 ) transition from a low state to a high state at the same time. In other words, the clock signal ( 201 ) and the output signal ( 217 ) are in phase. Accordingly, both the up and down signals ( 203 ,  205 ) transition from a low state to a high state at the same time. Also, both the flip-flops ( 306 ,  308  shown in FIG. 3) are reset simultaneously. Because a finite time duration (i.e., t MIN ) is needed for the AND gate ( 303  shown in FIG. 3) and the flip-flops ( 306 ,  308  shown in FIG. 3) to respond to the change in state, both the up and down signals ( 203 ,  205 ) have a finite time duration for which they are high. A nominal amount of charge is added to the capacitor ( 206  shown in FIG. 2) to maintain the present voltage potential on the control signal ( 207  shown in FIG.  2 ). 
     In FIG. 5, the times during which the charge pump ( 400  shown in FIG. 4) may modify or maintain the charge on the capacitor ( 206  shown in FIG. 2) are indicated. When the clock signal ( 201 ) and the output signal ( 217 ) are aligned, the time duration that the charge pump ( 400  shown in FIG. 4) is active is relatively small (i.e., t MIN ). During the time the charge pump ( 400  shown in FIG. 4) is inactive (i.e., when both switches ( 404 ,  406 ) are open), the voltage potential on the capacitor ( 206  shown in FIG. 2) may drift due to leakage currents inherent with devices used to form the capacitor ( 206  shown in FIG.  2 ). A means to compensate for the drift is needed. 
     Semiconductor capacitors are typically parallel plate capacitors formed by connecting the source and drain of a transistor together to create one terminal of the capacitor. The other terminal of the capacitor is formed by the gate connection of the transistor. Tunneling through the gate creates a path for leakage current. 
     Leakage current causes the voltage potential originally stored on the capacitor to change. In a DLL, the capacitor (e.g.,  206  shown in FIG. 2) helps maintain the amount of delay produced by the voltage-controlled delay line ( 210  shown in FIG.  2 ). 
     In FIG. 2, the relatively long time durations between the charge pump ( 204 ) updating the charge stored (i.e., voltage potential stored) on the capacitor ( 206 ) may result in a drift in the expected amount of delay of the DLL ( 200 ). Although a designer may intend for an integrated circuit to have a particular value for the leakage current of the capacitor ( 206 ), actual values for these parameters are typically unknown until the integrated circuit has been fabricated (i.e., in a post-fabrication stage). 
     For example, a designer may intend for the delay drift of the DLL ( 200 ) to be within in a particular range. The leakage current of the capacitor ( 206 ) may be unintentionally affected by many factors in the fabrication process. Because the leakage current cannot be redesigned in the post-fabrication stage without considerable temporal and monetary expenditures, these fabrication factors may cause the DLL ( 200 ) to have a different delay drift range than the range it was designed to have and therefore may have poor performance. Accordingly, there is a need for a technique and design that facilitates increased post-fabrication control of leakage current in the capacitor ( 206 ) of the DLL ( 200 ). 
     FIG. 6 shows an exemplary adjustable DLL ( 600 ) in accordance with an embodiment of the present invention. The phase detector ( 202 ), capacitor ( 206 ), bias-generator ( 208 ) and voltage-controlled delay line ( 210 ) of the adjustable DLL ( 600 ) operate similar to those respective components described above with reference to FIG.  2 . 
     In FIG. 6, a leakage current offset circuit ( 604 ) is connected between the control signal ( 207 ) and a power supply V SS . As the capacitor ( 206 ) leaks current, the voltage potential on the control signal ( 207 ) has a tendency to drift toward the power supply V DD . The leakage current offset circuit ( 604 ) is arranged to pull the voltage potential on the control signal ( 207 ) toward a power supply V SS . For example, an n-channel transistor is used as the leakage current offset circuit ( 604 ). 
     One of ordinary skill in the art will understand that in other embodiments, the capacitor ( 206 ) may be connected between the control signal ( 207 ) and the power supply V SS . In this case, the leakage current offset circuit ( 604 ) is connected between the control signal ( 207 ) and the power supply V DD . A leakage current offset circuit ( 604 ) in this arrangement may be a p-channel transistor. 
     In FIG. 6, an adjustment circuit ( 654 ) is used to adjust the leakage current offset circuit ( 604 ) to compensate for the leakage current of the capacitor ( 206 ). A bias voltage potential V BIAS  ( 661 ), is used to control the amount of compensation applied to offset the leakage current. The bias voltage potential V BIAS  ( 661 ) may be adjusted to increase, decrease, turn off, or maintain the amount of leakage current compensation (i.e., leakage current offset) produced by the leakage current offset circuit ( 604 ). 
     In FIG. 6, a combinational logic circuit ( 652 ) controls the adjustment circuit ( 654 ) using multiple adjustment signals N ( 653 ). The values of the multiple adjustment signals N ( 653 ) are determined by the combinational logic circuit ( 652 ). The combinational logic circuit ( 652 ) may communicate through an interface (not shown) using M communication lines ( 651 ). Those with ordinary skill in the art will understand that the interface and M communication lines ( 651 ) may take a wide variety of forms. The communication may be defined by an industry standard. 
     The combinational logic circuit ( 652 ) generates the multiple adjustment signals N ( 653 ) in response to the signal values on the M communication lines ( 651 ). The combinational logic circuit ( 652 ) may have 2 m  input combinations. For example, M may equal four and N may equal six. Accordingly, sixteen combinations exist for values on the six adjustment signals N ( 653 ). 
     Those skilled in the art will understand that the adjustable DLL ( 600 ) may be analog, digital, or a combination of both types of circuits. 
     FIG. 7 shows an exemplary adjustable DLL ( 700 ) in accordance with an embodiment of the present invention. The phase detector ( 202 ), capacitor ( 206 ), bias-generator ( 208 ), voltage-controlled delay line ( 210 ), leakage current offset circuit ( 604 ), and adjustment circuit ( 654 ) of the adjustable DLL ( 700 ) operate similar to those respective components described above with reference to FIG.  6 . 
     In FIG. 7, a combinational logic circuit ( 762 ) controls the adjustment circuit ( 654 ) using multiple adjustment signals N ( 653 ). The values of the multiple adjustment signals N ( 653 ) are determined by the combinational logic circuit ( 762 ). The up and down signals ( 203 ,  205 ) from the phase detector ( 202 ) control the combinational logic circuit ( 762 ). 
     The combinational logic circuit ( 762 ) generates the multiple adjustment signals N ( 653 ) in response to the up and down signals ( 203 ,  205 ). In one or more embodiments, the combinational logic circuit ( 762 ) may use a state machine to generate the multiple adjustment signals N ( 653 ). In other embodiments, the combinational logic circuit ( 762 ) may be an analog circuit with an analog-to-digital converter to generate the multiple adjustment signals N ( 653 ). In other embodiments, the combinational logic circuit ( 762 ) and adjustment circuit ( 654 ) may be combined to perform a function similar to the charge pump ( 204 ) where this additional charge pump controls the leakage current offset circuit ( 604 ). 
     Those skilled in the art will understand that, the adjustable DLL ( 700 ) may be analog, digital, or a combination of both types of circuits. 
     FIG. 8 shows a programmable current source ( 800 ) in accordance with an embodiment of the present invention. The programmable current source can be representative of the adjustment circuit ( 654 ) shown in FIGS. 6 and 7. The programmable current source ( 800 ) includes multiple p-channel transistors ( 802 ,  806 ,  810 ) connected respectively to multiple current sources ( 822 ,  824 ,  826 ) arranged in parallel with each other. The current sources ( 822 ,  824 ,  826 ) connect to the power supply V DD  and the p-channel transistors ( 802 ,  806 ,  810 ), respectively. The p-channel transistors ( 802 ,  806 ,  810 ) have a common node on which the bias voltage potential V BIAS  ( 661 ) is supplied to the leakage current offset circuit ( 604  shown in FIG.  6  and FIG.  7 ). The programmable current source ( 800 ) also includes multiple n-channel transistors ( 804 ,  808 ,  812 ) connected respectively to multiple current sources ( 828 ,  830 ,  832 ) arranged in parallel with each other. The current sources ( 828 ,  830 ,  832 ) connect to the power supply V SS  and the n-channel transistors ( 804 ,  808 ,  812 ), respectively. The n-channel transistors ( 804 ,  808 ,  812 ) connect to the bias voltage potential V BIAS  ( 661 ). 
     Each transistor has a corresponding individual control signal that turns “on” or “off” the respective p-channel transistors ( 802 ,  806 ,  810 ) and respective n-channel transistors ( 804 ,  808 ,  812 ). The p-channel transistors ( 802 ,  806 ,  810 ) have control signals EN_P 0  ( 801 ), EN_P 1  ( 805 ), and EN_P N  ( 809 ) connected to their gates, respectively. The n-channel transistors ( 804 ,  808 ,  812 ) have control signals EN_N 0  ( 803 ), EN —N   1  ( 807 ), and EN_N N  ( 811 ) connected to their gates, respectively. A “low” voltage potential on any of the EN_P x  control signals ( 801 ,  805 ,  809 ), where “x” represents any index 0 through N, turns “on” the respective p-channel transistor ( 802 ,  806 ,  810 ). A “high” voltage potential on any of the EN_N X  control signals ( 803 ,  807 ,  811 ), where “x” represents any index 0 through N, turns “on” the respective n-channel transistor ( 804 ,  808 ,  812 ). 
     A p-channel transistor ( 802 ,  806 ,  810 ) that is “on” changes the bias voltage potential ( 661 ) toward power supply V DD . The change in the bias voltage potential ( 661 ) is caused by current flow provided by one or more of the current sources ( 822 ,  824 ,  826 ) onto the bias voltage potential ( 661 ). An n-channel transistor ( 804 ,  808 ,  812 ) that is “on” changes the bias voltage potential ( 661 ) toward power supply V SS . The change in the bias voltage potential ( 661 ) is caused by current flow provided by one or more of the current sources ( 828 ,  830 ,  832 ) away from the bias voltage potential V BIAS  ( 661 ). By selecting which p-channel transistors ( 802 ,  806 ,  810 ) and/or n-channel transistors ( 804 ,  808 ,  812 ) are “on,” a selected change in the bias voltage potential V BIAS  ( 661 ) may be achieved. 
     Those with ordinary skill in the art will understand that the current sources ( 822 ,  824 ,  826 ,  828 ,  830 ,  832 ) may be designed using transistors that operate in a saturated region. Furthermore, the p-channel transistors ( 802 ,  806 ,  810 ) and n-channel transistors ( 804 ,  808 ,  812 ) operate as switches to connect the current sources ( 822 ,  824 ,  826 ,  828 ,  830 ,  832 ) to ries the bias voltage potential V BIAS  ( 661 ). 
     Those with ordinary skill in the art will understand that the p-channel transistors ( 802 ,  806 ,  810 ) and n-channel transistors ( 804 ,  808 ,  812 ) may be turned “on” individually or as a group. Each current source ( 822 ,  824 ,  826 ,  828 ,  830 ,  832 ) may provide a fixed amount of current; although, the current provided by each current source ( 822 ,  824 ,  826 ,  828 ,  830 ,  832 ) may differ from the other current sources ( 822 ,  824 ,  826 ,  828 ,  830 ,  832 ). The current sources ( 822 ,  824 ,  826 ,  828 ,  830 ,  832 ) may be designed to provide a linear, exponential, or other function as the current sources ( 822 ,  824 ,  826 ,  828 ,  830 ,  832 ) are connected or disconnected from bias voltage potential V BIAS  ( 661 ). 
     The p-channel transistors ( 802 ,  806 ,  810 ) and n-channel transistors ( 804 ,  808 ,  812 ) may be used to add or subtract a fixed amount of current from the current on the bias voltage potential V BIAS  ( 661 ). The p-channel transistors ( 802 ,  806 ,  810 ) and n-channel transistors ( 804 ,  808 ,  812 ) control the operation of the programmable current source ( 800 ). The programmable current source includes a plurality of current sources with each current source operatively connected to a switch. The switch controls the current flow from the current source. 
     In FIG. 6, the combinational logic circuit ( 652 ) generates a binary control word that determines which n-channel transistors ( 804 ,  808 ,  812  shown in FIG. 8) and p-channel transistors ( 802 ,  806 ,  810  shown in FIG. 8) are “on” and which are “off” in the adjustment circuit ( 654 ). Depending on the signal values of the M communication lines ( 651 ) received by the combinational logic circuit ( 652 ), multiple adjustment signals N ( 653 ) that represent EN_N X  signals, ( 803 ,  807 ,  811  in FIG. 8) and EN_P X  signals ( 801 ,  805 ,  809  in FIG. 8) may turn “on” or turn “off” the p-channel transistors ( 802 ,  806 ,  810  shown in FIG. 8) and n-channel transistors ( 804 ,  808 ,  812  shown in FIG. 8) in the adjustment circuit ( 654 ). The bias voltage potential V BIAS  ( 661 ) of the adjustment circuit ( 654 ) adjusts the leakage current offset circuit ( 604 ) to compensate for the leakage current of the capacitor ( 206 ). 
     In FIG. 7, the combinational logic circuit ( 762 ) generates a binary control word that determines which n-channel transistors ( 804 ,  808 ,  812  shown in FIG. 8) and p-channel transistors ( 802 ,  806 ,  810  shown in FIG. 8) are “on” and which are “off” in the adjustment circuit ( 654 ). The multiple adjustment signals N ( 653 ) that represent EN_N X  signals ( 803 ,  807 ,  811  in FIG. 8) and EN_P X  signals ( 801 ,  805 ,  809  in FIG. 8) may turn “on” or turn “off” the p-channel transistors ( 802 ,  806 ,  810  shown in FIG. 8) and n-channel transistors ( 804 ,  808 ,  812  shown in FIG. 8) in the adjustment circuit ( 654 ). The bias voltage potential V BIAS  ( 661 ) of the adjustment circuit ( 654 ) adjusts the leakage current offset circuit ( 604 ) to compensate for the leakage current of the capacitor ( 206 ). 
     Advantages of the present invention may include one or more of the following. The adjustable DLL ( 600  in FIG. 6 and 700 in FIG.  7 ), after fabrication, may demonstrate undesirable operating characteristics that may not have been apparent from simulation. In one or more embodiments, because the adjustment circuit ( 654  shown in FIG.  6  and FIG. 7) may modify the operating characteristics of the adjustable DLL ( 600  in FIG. 6 and 700 in FIG.  7 ), the adjustable DLL ( 600  in FIG. 6 and 700 in FIG. 7) may be adjusted. 
     In one or more embodiments, because the adjustable DLL ( 600  in FIG. 6 and 700 in FIG. 7) may be fabricated with a means for compensating the leakage current of the capacitor ( 206  in FIG.  6  and in FIG.  7 ), fewer design iterations and higher confidence in the adjustable DLL ( 600  in FIG. 6 and 700 in FIG. 7) operating characteristics may be afforded. 
     In one or more embodiments, because an adjustment circuit ( 654  in FIG.  6  and FIG. 7) may modify the operating characteristics of the adjustable DLL ( 600  in FIG. 6 and 700 in FIG.  7 ), an investigation of the adjustable DLL&#39;s ( 600  in FIG. 6 and 700 in FIG. 7) response during operating conditions may be performed. 
     In one or more embodiments, a limited number of adjustable DLLs ( 600  in FIG. 6 and 700 in FIG. 7) may need to be tested to determine a desired adjustment that may be used for future, non-adjustable DLLs. 
     In one or more embodiments, a current source ( 822 ,  824 ,  826 ,  828 ,  830 ,  832 ) in programmable current source ( 800  in FIG. 8) may have a fixed current supply. A fixed current source may be easier to design and maintain at a fixed current supply. The programmable current source ( 800  in FIG. 8) may add, subtract, and/or redirect current from the current sources ( 822 ,  824 ,  826 ,  828 ,  830 ,  832 ) using digital control of switches. 
     While the invention has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be devised which do not depart from the scope of the invention as disclosed herein. Accordingly, the scope of the invention should be limited only by the attached claims.