Abstract:
A power multiplier system for an amplifier comprises a power multiplier control stage, an amplifier stage and a first switching stage connectable to the power multiplier control stage. The amplifier stage is connectable to the power multiplier control stage. The power multiplier system has a first output terminal and a second output terminal, the amplifier stage is connectable to the second output terminal for driving a load connectable between the first and second output terminals. The first switching stage is connectable to the first output terminal to apply a switchable DC voltage level to the first output terminal. 
     There is also disclosed a method of amplifying the power output of an amplifier system.

Description:
FIELD OF THE INVENTION 
   The present invention relates to a power multiplier system and method, and in particular such a system for use in Class D digital amplifiers. 
   BACKGROUND OF THE INVENTION 
   Currently, the typical maximum output power that can be derived from a conventional Class D digital amplifier is about 100 Watts to 200 Watts into a 4 Ohms load. There is a limitation on this maximum output power due to the semiconductors used in the amplifiers. It is desirable to keep the size of the integrated circuits used to make the amplifiers small to facilitate compact product design, but at the same time, there is also demand for higher output power, which is especially desirable for Class D digital amplifiers due to their high efficiency. 
   SUMMARY OF THE INVENTION 
   In general, the invention provides a power multiplier system and method in which the power of the system is increased by restricting the range of the signal applied to a pulse width modulator stage, applying the output of a first switching stage to an output terminal of the system and applying a switched potential to a further output of the system to create a substantially undistorted output signal. 
   According to a first aspect of the invention there is provided a power multiplier system for an amplifier comprising:
         a power multiplier control stage;   an amplifier stage; and   a first switching stage connectable to said power multiplier control stage; said amplifier stage being connectable to said power multiplier control stage; wherein said power multiplier system has a first output terminal and a second output terminal, said amplifier stage being connectable to said second output terminal for driving a load connectable between said first and second output terminals; and   wherein said first switching stage is connectable to said first output terminal to apply a switchable DC voltage level to said first output terminal.       

   According to a second aspect of the invention there is provided a method of amplifying power output from a digital amplifier system having a first output terminal and a second output terminal, the method comprising the steps of:
         applying an input signal to a power multiplier control stage;       

   producing one or more signals in said power multiplier control stage;
         controlling an amplifier stage using one or more of said one or more signals;   driving said second output terminal via said amplifier stage;   controlling a first switching stage using one or more signals from said power multiplier control stage; and   selecting in said first switching stage one or more switchable DC voltage levels from a plurality of voltage levels; and   applying said one or more selected voltage levels to said first output terminal for producing a substantially undistorted waveform across a load connectable between said first and second output terminals.       

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Preferred features of the invention will now be described, for the sake of illustration only, with reference to the following Figures in which: 
       FIG. 1  is a schematic block diagram of a conventional Class D digital amplifier configuration; 
       FIG. 2  is a schematic circuit diagram of an amplifier according to a preferred embodiment of the invention; 
       FIG. 3  is a waveform of an output signal at node  2  in the circuit of  FIG. 2 ; 
       FIG. 4  is a waveform of a signal at node  1  in the circuit of  FIG. 2 ; 
       FIG. 5  is a waveform of a signal present across the load in the circuit of  FIG. 2  and a waveform of a signal from a conventional bridge-tied load (BTL) amplifier; 
       FIG. 6  is a representation of the waveforms across the load, at node  2  and at node  1  in the circuit of  FIG. 2 ; 
       FIG. 7  is a schematic circuit diagram of an amplifier according to a further preferred embodiment of the invention; 
       FIG. 8  is a waveform of an output signal at node  2  in the circuit of  FIG. 7 ; 
       FIG. 9  is a waveform of a signal at node  1  in the circuit of  FIG. 7 ; 
       FIG. 10  is a representation of the waveforms across the load, at node  2  and at node  1  in the circuit of  FIG. 7 ; 
       FIG. 11  is a schematic circuit diagram of an amplifier according to another preferred embodiment of the invention; 
       FIG. 12  is a schematic representation of the pulse width modulated signal for DC modulated voltages from the pulse width modulator in the circuit of  FIG. 11 ; 
       FIG. 13  is a schematic circuit diagram of an amplifier according to another preferred embodiment of the invention; 
       FIG. 14  schematic representation of the pulse width modulated signal for DC modulated voltages from the pulse width modulator in the circuit of  FIG. 13 ; 
       FIG. 15  is a schematic circuit diagram of an amplifier according to yet another preferred embodiment of the invention; and 
       FIG. 16  is a schematic circuit diagram of a further preferred embodiment of the invention operating in analogue mode. 
   

   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     FIG. 1  shows a block diagram of a conventional Class D digital amplifier system driving a speaker load, in a single channel within a BTL configuration. 
   The system comprises a pulse width modulator integrated circuit  4 , a power stage driver integrated circuit  5 , and a MOSFET H-bridge stage  6  driving a load  7 . The digital audio input signal is fed to the pulse width modulator circuit  4  and the pulse width modulated signal output from the pulse width modulator circuit  4  is applied to the power stage driver  5 . The output of the power stage driver  5  drives the MOSFET H-bridge stage  6  which in turn drives the load  7 . 
   The peak amplitude of the digital input signal in the system of  FIG. 1  to produce the maximum undistorted output to the load  7  (V cc  volts peak-to-peak) may be denoted as A. In this configuration, the main limitation on the output power is due to the power handling capability of the power stage driver IC  5 . 
     FIG. 2  illustrates a system according to a first preferred embodiment of the invention and comprises a power multiplier control stage  10 , a switching stage  11 , a pulse width modulator stage  12 , a power driver stage  13 , two power MOSFETs M 1 , M 2 , an inductor L 1 , a capacitor C 1 , and a load  20 . The pulse width modulator stage  12 , the power driver stage  13 , and the two power MOSFETs M 1  and M 2  form an amplifier stage. 
   In the system of  FIG. 2 , the digital audio input signal  30  is applied to the power multiplier control stage  10  which multiplies the signal amplitude by, for example, 3 and checks the level of the signal. If the signal is below A, which is the peak amplitude of the digital input signal in a conventional Class D amplifier which will produce the maximum peak-to-peak undistorted output for a supply voltage V cc , the switching stage  11  which is preferably a multiway switch will select the voltage ½ V cc . 
   If the level of the signal exceeds A, the multiway switch  11  will switch to ground (GND) and a level A will be subtracted from the result of the input signal multiplied by 3. If the level exceeds 2 A, the switch  11  will select the voltage −½ V cc  and a level  2 A will be subtracted from the result of the signal multiplied by 3. In both cases, this result will be sent to the pulse width modulator stage  12  which is preferably a PWM processor IC. Thus the amplitude of the input to the PWM processor IC  12  is always kept below A so that no overflow will occur and the signal remains within the linear working range of the system. 
   The multiplied signal is applied to the pulse width modulator  12  to produce a train of width-modulated pulses which are then applied to the power driver stage  13 . 
   Similarly, for the negative peak of the input signal  30 , if the level of the signal exceeds −A or −2 A, the Multiway Switch  11  will switch to V cc  or 3/2 V cc  respectively. Also, −A or −2 A will be subtracted from the result of the signal multiplied by 3 and this result will be sent to the PWM processor IC  12 . 
   The power driver stage  13  drives the two MOSFETs M 1  and M 2  which are coupled in series across a power supply V cc . The junction of the two MOSFETs M 1  and M 2  is connected to a first end of the inductor L 1 . The output of L 1  is coupled to one side of the capacitor C 1  at a node  2  and also to one terminal of the load  20 . The other side of the capacitor C 1  is connected to ground. The digital outputs from the power multiplier control  10  are applied to the switching stage  11  which is also coupled to a range of voltage sources V cc , 3/2V cc , ½V cc , ground and −½V cc . 
   The switching stage  11  selects one of the voltage sources as determined by the power multiplier control unit  10  and the selected voltage level is applied to the second side of the load  20  at a node  1 . The inductor L 1  and the capacitor C 1  form a low pass filter. 
     FIG. 3  shows a plot of the signal at node  2  of the circuit of  FIG. 2  if a sinusoidal input signal of amplitude A is applied as the audio input signal  30 . 
     FIG. 4  shows a plot of the corresponding signal at Node  1 .  FIG. 5  shows a plot of the corresponding overall signal across the load  20  in the system of  FIG. 2  and a waveform of a signal from a conventional bridge-tied load (BTL) amplifier.  FIG. 6  shows the signal at node  1 , node  2  and across the load  20  in one plot using the system of  FIG. 2 . 
   As shown in  FIG. 5 , using the system of  FIG. 2 , a peak amplitude of 1.5V cc  is achieved as compared to a conventional system of the type shown in  FIG. 1  in which a peak amplitude of V cc  is achieved, using the same integrated circuits in both cases. In terms of power, by using the system of  FIG. 2 , the output power may be increased by, for example, 2.25 times the power from a conventional system of the type shown in  FIG. 1 , and this is shown in the calculations below. 
   
     
       
         
           
             
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   As the power multiplier control stage  10  may be implemented using a digital signal processor, the system of  FIG. 2  may be implemented readily by use of an appropriate algorithm. It may also be possible and desirable to include the power multiplier control stage  10  within the PWM processor  12  as this will reduce the number of integrated circuits required. 
   Although the input signal  30  has been described and illustrated as being a pure sine wave, any form of input signal may be used. 
   An alternative embodiment of a system according to a further preferred embodiment of the invention is shown in  FIG. 7 . The circuit of  FIG. 7  is identical to that shown in  FIG. 2  with the exception that the number of switched voltages has been reduced to 3, that is, to −½ V cc , ½ V cc  and 3/2 V cc . 
   In the embodiment of  FIG. 7 , the power multiplier control stage  10  multiplies the input signal by 5 and checks the level of the signal. If the signal is below A, the multiway switch  11  will select the voltage ½ V cc  to be applied to a first side of the load  20 . If the level of the signal exceeds A, the multiway switch  11  will switch to −½ V cc . At the same time, 2 A is subtracted from the result of the signal multiplied by 5 and this result will be sent to the PWM processor IC  12 . 
   Similarly, for the negative side, if the level exceeds −A, the multiway switch  11  will select the voltage 3/2 V cc  and −2 A will be subtracted from the result of the signal multiplied by 5 and this result will be sent to the PWM processor IC  12 . 
     FIG. 8  shows a plot of the signal at node  2  of the system of  FIG. 7  if a sinusoidal input signal of amplitude A is applied as the digital audio input signal  30 . 
     FIG. 9  shows a plot of the corresponding signal at Node  1  in the system of  FIG. 7  and  FIG. 10  shows the signal at node  1 , node  2  and across the load  20  of the system of  FIG. 7  in one plot. 
     FIG. 11  shows a further preferred embodiment of the present invention which differs from the embodiments of  FIGS. 2 and 7  in that the MOSFET drive involves a full bridge, whereas for the first described embodiment shown in  FIG. 2 , it can be seen that only half an H-Bridge is used. The embodiment of  FIG. 11  also has fewer steps of switching voltages, than the embodiment of  FIG. 2 . 
   In the system of  FIG. 11 , the digital input signal  30  is applied to the power multiplier control stage  10  where it is multiplied and sampled. As in the system of  FIG. 2 , the amplitude of the signal level is checked and adjusted as required to keep the level within the working range of the PWM processor  12 . The multiplied output signal is applied to the PWM processor  12 , the width modulated pulses from which are then applied to the input of the power driver stage  13 . The outputs from this stage  13 , as well as being applied to the MOSFETS M 1  and M 2 , are also applied to two further MOSFETs M 3  and M 4 . M 1  and M 2  are connected in series across the power supply V cc  to ground, the junction being taken to inductor L 1 , the second terminal of which is connected to a first terminal of capacitor C 1  and a first terminal of the load  20  at node  2 . The MOSFETs M 3  and M 4  are connected in series across the supply V cc  to ground. The junction between M 3  and M 4  is connected to a first terminal of an inductor L 2 , the second terminal of which is connected to capacitor C 2 . The other terminals of the capacitors C 1  and C 2  are connected to ground. The second terminal of L 2  is further connected to an input of the switching unit  14  at node  3 . The other voltage inputs to the switching unit  14  are −½ V cc  and 3/2V cc . The switching operation is controlled by the power multiplier stage  10 . 
   In the system of  FIG. 11 , the working principles are the same as the embodiment of  FIG. 2 , but in the configuration of  FIG. 11  the DC voltages of GND, ½ V cc  and V cc  are provided to Node  1  of the load to the side of the H-Bridge connected to the 3-way switch  14 . The DC voltages are applied through the 3-way switch  14  by controlling the width of the pulse width-modulated (PWM) signal applied from the power driver stage  13  to M 3  and M 4  through the low pass filter formed by L 2  and C 2 . The PWM signals for producing these DC voltages are shown in  FIG. 12 . 
   A further alternative preferred embodiment of the invention is shown in  FIG. 13 . In this embodiment, the input signal  30  is applied to the power multiplier control  10  the output of which is applied to the pulse width modulator  12 . The pulse width modulated pulses therefrom are applied to the power driver stage  13  and the outputs of this stage control MOSFETs M 1  and M 2  connected in series across the supply. The junction of the MOSFETs M 1  and M 2  is connected to the first terminal of an inductor L 1 , the second terminal of which is connected to a first terminal of a load  20  and a first terminal of a capacitor C 1  to form node  2 . The control outputs from the power multiplier control stage  10  are applied to a pulse width modulated signal generator stage  15  which provides outputs to drive a further pair of MOSFETs M 3  and M 4  which are connected in series between supplies 3/2V cc  and −½ V cc . The junction of the MOSFETs M 3  and M 4  is connected to a first terminal of an inductor L 2 , the second terminal of which is coupled to a first terminal of a capacitor C 2  and a second terminal of a load  20  to form node  1 . The second terminals of C 1  and C 2  are both connected to ground. 
   In the embodiment of  FIG. 13 , the switching among the DC voltages −½ Vcc, GND, ½ Vcc, Vcc and 3/2 Vcc to Node  1  are provided by a PWM Signal Generator  15  through the low pass filter formed by L 2  and C 2 , by controlling the width of the PWM signal, which is as shown below in  FIG. 14 . 
     FIG. 14  shows the pulse width modulated signals applied to M 3  and M 4  respectively the system of  FIG. 13  for the various switching voltages. 
   To obtain the switching voltage of −½V cc , the upper transistor M 3  is turned off and the lower transistor M 4  is turned on. 
   To obtain the ground condition, the upper transistor M 3  is turned on for ⅓ of the cycle whilst the lower transistor M 4  is turned off and then M 3  is turned off whilst M 4  is turned on for the remaining ⅔ of the cycle. 
   To obtain the switching voltage ½V cc , M 3  is switched on for half of the cycle whilst M 4  is switched off and then for the remaining half of the cycle M 3  is turned off whilst M 4  is turned on. 
   To obtain the switching voltage V cc , M 3  is turned on for ⅔ of the cycle whilst M 4  is turned off and M 4  is then turned on for the remaining ⅓ of the cycle whilst M 3  is turned off. 
   To obtain the switching voltage 3/2V cc , M 3  is turned on and M 4  is turned off for the duration of the cycle. 
   A further preferred embodiment of the invention is shown in  FIG. 15 . A Switching Mode Power Supply is used for switching among the DC voltages. As in the system of  FIG. 2 , the amplitude of the signal level is checked and adjusted as required to keep the level within the working range of the PWM processor  12 . The digital audio input signal  30  is applied to a power multiplier control stage  10  where it is multiplied and the multiplied output is then applied to the pulse width modulator stage  12 . The pulse width modulated pulses from the pulse width modulator stage  12  are applied to a power driver stage  13  which drives a pair of MOSFET transistors M 1  and M 2  connected in series across the supply. The junction of the MOSFET transistors M 1  and M 2  is connected to a first terminal of an inductor L 1  and the second terminal of the inductor L 1  is connected to a first terminal of a capacitor C 1  and a first terminal of a load  20  to form node  2 . 
   The switching outputs of the power multiplier control stage  10  are applied to a switching mode power supply  16  to switch the output voltages thereof between −½V cc , ground, ½V cc  and 3/2V cc . 
   The output voltages of the switching mode power supply  16  are applied to the second terminal of the load  20  to form node  1  and the second terminal of the capacitor C 1  is connected to ground. Further outputs voltages V 1 , V 2  and V 3  from the switching mode power supply  16  shown in  FIG. 15  are other voltages supplied to other devices within the equipment, for example, a microcontroller. 
   As the power multiplier control stage  10  may be implemented using a digital signal processor, the systems of  FIGS. 2 ,  7 ,  11 ,  13 , and  15  may be implemented readily by use of an appropriate conventional control algorithm. 
     FIG. 16  illustrates a further preferred embodiment of the present invention working in the analogue mode which is in contrast to the embodiments of  FIGS. 2 ,  7 ,  11 ,  13  and  15  which work in the digital mode. The system of  FIG. 16  includes a Class D analogue amplifier  23  having a first (positive) input and a second (negative) input, a switching stage  24 , a comparator stage  25 , a further interface stage  26 , a load  27  and a resistive potential divider network formed of resistors R 9  and R 10  having a division ratio equivalent to the inverse of the gain of the amplifier  23 . The comparator stage  25  and the further interface stage  26  form a power multiplier control stage. 
   In the system of  FIG. 16 , the analogue input signal  19  is applied to the negative input of the Class D analogue amplifier  23  which has a gain of Gv. The analogue input signal  19  is also applied to the comparator stage  25  wherein it is compared with a plurality of DC voltages obtained from a positive voltage supply Vref and a negative voltage supply −Vref. Within the comparator stage  25  a serially connected chain of six resistors R 1  to R 6  is connected between Vref and −Vref to provide the plurality of DC voltages. The junction of resistors R 3  and R 4  is connected to ground. Also within the comparator stage  25  are four comparators. The analogue input signal  19  is applied to one input of each comparator and the other input of each comparator is connected to a junction in the chain of resistors R 1  to R 6 , the junctions being between R 1  and R 2 , R 2  and R 3 , R 4  and R 5  and R 5  and R 6 . Preferably, resistors R 1  to R 6  are equal in resistive value. Thus the signal is compared with voltages ±⅓Vref and ±⅔Vref. 
   The outputs of the comparators are coupled to the further stage  26  which may comprise a control circuit to control The switching stage  24 . The outputs of the stage  26  are coupled to the switching stage  24 . 
   The output of the switching stage  24  is coupled to a first (positive) terminal of the load  27  and also to resistor R 9  of the potential divider formed by resistors R 9  and R 10 . The junction between R 9  and R 10  is coupled to a first (positive) terminal of the Class D analogue amplifier  23 . The other terminal of R 10  is connected to ground. The output of the second (negative) terminal of the load  27  is connected to the output of the Class D analogue amplifier  23 . 
   In the system of  FIG. 16 , the supply voltage to the Class D amplifier  23  need only be one third of the total output voltage swing. If, therefore, the total undistorted output voltage is ±Vcc, then Vref is chosen such that an input swing of ±Vref will give an undistorted output of ±Vcc. 
   If the positive excursion of the incoming signal  19  exceeds the level ⅓ Vref, then the comparator connected at the junction of R 2  and R 3  will give an output which, via the stage  26 , sets the switching stage  24  to give an output Vcc 1  which corresponds to ⅓Vcc. 
   If the positive excursion exceeds ⅔ Vref, then the comparator connected to the junction of R 1  and R 2  produces an output which sets the switching stage  24  to give an output of Vcc 2  which is equal to ⅔ Vcc. 
   If the negative excursion of the incoming signal  19  exceeds the level −⅓ Vref, then the comparator connected at the junction of R 4  and R 5  will give an output which the stage  26  will use to set the switching stage  24  to give an output of −Vcc 1  which corresponds to −⅓Vcc. 
   If the negative excursion exceeds −⅔ Vref, then the comparator connected to the junction of R 5  and R 6  produces an output which sets the switching stage  24  to give an output of −Vcc 2  which is equal to −2Vcc 1 . 
   The waveforms at the first (positive) and second (negative) terminals of the load  27  are also shown in  FIG. 16 . In the embodiment of  FIG. 16 , the Class D amplifier  23  can achieve a higher output power than the amplifier alone was designed to produce. As in the embodiments of  FIGS. 2 to 15 , it is possible to produce higher output power than conventional amplifier designs without increasing the voltage applied to the amplifier or to produce the same output power at a lower supply voltage. 
   As the junction between resistors R 9  and R 10  is connected to the positive terminal of the Class D analogue amplifier  23 , the signal level at this junction is subtracted from the input signal level so that the resulting level of the signal output from the amplifier  23  is within the linear working range of the amplifier  23 . 
   Various modifications to the embodiments of the present invention described above may be made. For example, other components and method steps can be added or substituted for those above. Thus, although the invention has been described above using particular embodiments, many variations are possible within the scope of the claims, as will be clear to the skilled reader, without departing from the spirit and scope of the invention.