Abstract:
A semiconductor memory device includes a controller, a plurality of substrates, and a plurality of stacked memories that are spaced apart and sequence on each of the substrates. Each of the stacked memories includes an interface chip that is connected to the respective substrate and a plurality of memory chips that are stacked on the interface chip. The controller is configured to control the stacked memories. The interface chips are configured to forward a command signal from the controller through each interface chip in the sequence of stacked memories that is intervening between the controller and a selected stacked memory to which the command signal is directed. The interface chips may forward the command signal from one end of the sequence of the stacked memories on one of the substrates to the selected stacked memory, and forward a response signal from the selected stacked memory through the remaining stacked memories in the sequence on the substrate back to the controller or through the same sequence of stacked memories that was taken by the command signal.

Description:
CROSS-REFERENCE TO RELATED PATENT APPLICATIONS 
       [0001]    This application claims the benefit of Korean Patent Application No. 10-2008-0025379, filed on Mar. 19, 2008, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. 
       FIELD OF THE INVENTION 
       [0002]    The present invention relates to semiconductor memory devices and, more particularly, to semiconductor memory devices having memory modules in which an interface chip and a plurality of memory chips are stacked. 
       BACKGROUND 
       [0003]    In an attempt to increase the performance and capacity of memory devices, a plurality of memory chips can be interconnected to form a memory module, such as a dynamic random access memory (DRAM), on a printed circuit board (PCB). 
         [0004]    Such memory modules may be classified into single in-line memory modules (SIMMs), in which a plurality of memory chips are connected to one surface of a PCB, and dual in-line memory modules (DIMMs), in which a plurality of memory chips are connected to both surfaces of a PCB. An FBDIMM (fully buffered DIMM) is one type of DIMM that has been developed to allow high-operating speed and large memory capacity using a packet protocol. The FBDIMM includes an interface chip for converting a packet type serial interface into a DRAM interface. The interface chip is a unit that transforms a high-speed packet received from a host, such as a microprocessor, into a memory command, and provides an interface between a received signal and a transmitted signal. In general, the interface chip is referred to as an advanced memory buffer (AMB) chip. 
         [0005]      FIG. 1  is a block diagram of a conventional semiconductor memory device  100  that is configured as a FBDIMM. Referring to  FIG. 1 , the semiconductor memory device  100  includes a controller  110 , a first memory module  120 , and a second memory module  130 . The first memory module  120  is connected to an interface chip, e.g., a first AMB chip AMB_ 1 , and a plurality of memory chips  121 ,  122 , . . . ,  128 . Similarly, the second memory module  130  is connected to a second AMB chip AMB_ 2  and a plurality of memory chips  131 ,  132 , . . . ,  138 . The controller  110  exchanges a signal, e.g., an address, a command, or data, with the first and second memory modules  120  and  130 . 
         [0006]    When the controller  110  transmits a signal related to the first memory module  120 , the first AMB chip AMB_ 1  receives the signal and transmits it to a corresponding memory chip of the first memory module  120 . If the controller  110  transmits a signal related to the second memory module  130 , the first AMB chip AMB_ 1  receives the signal and transmits it to the AMB chip AMB_ 2 . Then, the second AMB chip AMB_ 2  receives the signal and transmits it to a corresponding memory chip of the second memory module  130 . 
         [0007]    For example, in order to read data from the memory chip  123 , the controller  110  transmits a read command for reading the data from the memory chip  123  to the first AMB chip AMB_ 1 . The first AMB chip AMB_ 1  receives the read command and transmits it to the memory chip  123 , and the memory chip  123  performs a read operation. The data read through the read operation is transmitted to the controller  110  via the first AMB chip AMB_ 1 . In order to read data from the memory chip  136 , the controller  110  transmits a read command for reading the data from the memory chip  136  to the first AMB chip AMB_ 1 . Since the read command is not related to the first memory module  120 , the first AMB chip AMB_ 1  delivers the read command to the second AMB chip AMB_ 2 . Then, the second AMB chip AMB  2  receives the read command and transmits it to the memory chip  136 , and the memory chip  136  performs a read operation. The data read through the read operation is transmitted to the controller  110  via the first AMB chip AMB_ 1  and the second AMB chip AMB_ 2 . When a command or data is transmitted as described above, unidirectional signal transmission is performed between the controller  110  and the first AMB chip AMB_ 1  and between the first AMB chip AMB_ 1  and the second AMB chip AMB_ 2 , and bidirectional signal transmission is performed between the first AMB chip AMB_ 1  and the memory chips  121 , . . . ,  128  and between the second AMB chip AMB_ 2  and the memory chips  131 , . . . ,  138 . 
       SUMMARY 
       [0008]    Some embodiments of the present invention are directed to a semiconductor memory device having a plurality of stacked memory chips and which may be capable of reducing power consumption and/or shortening the length of a signal transmission path to the stacked memory chips. 
         [0009]    According to some embodiments of the present invention, a semiconductor memory device includes first through mth substrates, where m is a natural number greater than 1, and first through nth stacked memories that are spaced apart and connected to each of the first through mth substrates, where n is a natural number. Each of the first through nth stacked memories includes an interface chip that is connected the respective substrate and further includes a plurality of memory chips stacked on the interface chip. A kth one of the interface chips transmits a signal to a k+1th interface chip connected to the same substrate, where k is a natural number that is equal to or greater than 1 and is less than or equal to n−1. 
         [0010]    The semiconductor memory device can further include a controller that is configured to control the first through nth stacked memories connected to each of the first through mth substrates. The controller transmits a command signal, which is directed to the nth interface chip connected to the first substrate, to the first one of the interface chips connected to the first substrate and which relays the command signal to the nth interface chip connected to the first substrate, and the controller receives a response signal from the nth interface chip connected to the first substrate. 
         [0011]    The kth interface chip may forward the command signal to the k+1th interface chip using a first signaling mode. The controller may transmit the command signal to the first interface chip and receive the response signal from the nth interface chip using a second signaling mode that is different than the first signaling mode. The controller and stacked memories can thereby be configured so that power consumption in the first signaling mode is less than in the second signaling mode. 
         [0012]    The controller may transmit a command signal, which is directed to the first interface chip connected to an a+1th substrate, through the first interface chip connected to an ath substrate, where a is a natural number equal to or greater than 1 and less than or equal to m−1. The first interface chip connected to the ath substrate can respond to the command signal by transmitting the command signal to the first interface chip connected to the a+1th substrate. The nth interface chip connected to the ath substrate can receive a response signal from the nth interface chip connected to the a+1th substrate. 
         [0013]    According to some other embodiments of the present invention, a semiconductor memory device includes first through mth substrates, where m is a natural number greater than 1, and first through nth stacked memories that are spaced apart and connected to each of the first through mth substrates, where n is a natural number. Each of the first through nth stacked memories includes an interface chip that is connected to the respective substrate and further includes a plurality of memory chips stacked on the interface chip. A kth one of the interface chips exchanges a signal with a k+1th interface chip connected to the same substrate, where k is a natural number that is equal to or greater than 1 and is less than or equal to n−1. 
         [0014]    The semiconductor memory device can further include a controller that is configured to control the first through nth stacked memories connected to each of the first through mth substrates. The controller may exchange signals with the first interface chip connected to the first substrate to read data from one of the stacked memories on one of the substrates other than the first substrate. 
         [0015]    According to some other embodiments of the present invention, a semiconductor memory device includes a controller, a plurality of substrates, and a plurality of stacked memories that are spaced apart and sequence on each of the substrates. Each of the stacked memories includes an interface chip that is directly connected to the respective substrate and a plurality of memory chips that are stacked on the interface chip. The controller is configured to control the stacked memories. The interface chips are configured to forward a command signal from the controller through each interface chip in the sequence of stacked memories that is intervening between the controller and a selected stacked memory to which the command signal is directed. 
         [0016]    The interface chips can be further configured to forward the command signal from one end of the sequence of the stacked memories on one of the substrates to the selected stacked memory, and to forward a response signal from the selected stacked memory through the remaining stacked memories in the sequence on the substrate back to the controller. 
         [0017]    One of the interface chips at an end of the sequence of the stacked memories on a first substrate can be configured to forward the command signal to one of the interface chips at an end of the sequence of the stacked memories on a second substrate when the selected stacked memory is not on the first substrate. 
         [0018]    The stacked memories on a plurality of the substrates can be connected in a continuous sequence. The interface chips can be further configured to forward the command signal from one end of the sequence of the stacked memories to the selected stacked memory, and to forward a response signal from the selected stacked memory back to the controller along the same path through the same sequence of stacked memories that was taken by the command signal. 
         [0019]    The interface chips can be further configured to forward the command signal from one end of the sequence of the stacked memories to the selected stacked memory on the same substrate, and to forward a response signal from the selected stacked memory back to the controller along the same path through the same sequence of stacked memories that was taken by the command signal. 
         [0020]    According to some other embodiments of the present invention, a semiconductor memory device includes first through mth substrates, where m is a natural number; and first through nth stacked memories respectively include first through nth interface chips connected to each of the first through mth substrates. A plurality of memory chips are stacked on each of the first through nth interface chips in the vertical direction, where n is a natural number. A kth interface chip transmits a signal to a k+1th interface chip connected to the same substrate, where k is a natural number equal to or greater than 1 and less than or equal to n−1. 
         [0021]    The semiconductor memory device may further include a controller that is configured to control the first through nth stacked memories connected to each of the first through mth substrates. The controller may transmit a signal to the first interface chip connected to the first substrate and receive a signal from the nth interface chip connected to the first substrate. 
         [0022]    The first interface chip connected to an ath substrate may transmit a signal to the first interface chip connected to an a+1th substrate, where a is a natural number equal to or greater than 1 and less than or equal to m−1. The nth interface chip connected to the ath substrate may receive a signal from the nth interface chip connected to the a+1th substrate. 
         [0023]    According to some other embodiments of the present invention, a semiconductor memory device includes first through mth substrates, where m is a natural number; and first through nth stacked memories respectively including first through nth interface chips connected to each of the first through mth substrates. A plurality of memory chips are stacked on each of the first through nth interface chips in the vertical direction, where n is a natural number. A kth interface chip exchanges a signal with a k+1th interface chip connected to the same substrate, where k is a natural number equal to or greater than 1 and less than or equal to n−1. 
         [0024]    The semiconductor memory device may further include a controller that is configured to control the first through nth stacked memories connected to each of the first through mth substrates. The controller exchanges a signal with the first interface chip connected to the first substrate. 
         [0025]    The nth interface chip connected to an ath substrate may exchange a signal with the first interface chip connected to an a+1th substrate, where a is a natural number equal to or greater than 1 and less than or equal to m−1. 
         [0026]    The semiconductor memory device may further include a controller that is configured to control the first through nth stacked memories connected to each of the first through mth substrates. The controller exchanges a signal with an ith interface chip connected to the first substrate, where i is a natural number equal to or greater than 2 and less than or equal to n−1. 
         [0027]    The ith interface chip connected to an ath substrate may exchange a signal with the ith interface chip connected to an a+1th substrate, where a is a natural number equal to or greater than 1 and less than or equal to m−1. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0028]    The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate certain embodiments of the invention. In the drawings: 
           [0029]      FIG. 1  is a block diagram of a conventional semiconductor memory device having a fully buffered dual in-line memory module (FBDIMM); 
           [0030]      FIG. 2A  illustrates a memory module according to some embodiments of the present invention; 
           [0031]      FIG. 2B  illustrates a memory module according to other embodiments of the present invention; 
           [0032]      FIG. 3  is a block diagram of a semiconductor memory device according to some embodiments of the present invention; 
           [0033]      FIG. 4  is a block diagram of a semiconductor memory device according to other embodiments of the present invention; and 
           [0034]      FIG. 5  is a block diagram of a semiconductor memory device according to other embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0035]    The present invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, the thicknesses sizes of layers and regions are exaggerated for clarity. Like reference numerals in the drawings denote like elements. A semiconductor substrate described in the present specification denotes not only the semiconductor substrate itself, but also a structure in/on which the semiconductor substrate is formed by various processes. 
         [0036]    It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items and may be abbreviated as “/”. 
         [0037]    It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first region/layer could be termed a second region/layer, and, similarly, a second region/layer could be termed a first region/layer without departing from the teachings of the disclosure. 
         [0038]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” or “includes” and/or “including” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof. 
         [0039]    Embodiments of the present invention may be described with reference to cross-sectional illustrations, which are schematic illustrations of idealized embodiments of the present invention. As such, variations from the shapes of the illustrations, as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes that result from, e.g., manufacturing. For example, a region illustrated as a rectangle may have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and are not intended to limit the scope of the present invention. 
         [0040]    Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present application, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
         [0041]      FIG. 2A  illustrates a memory module  200  according to some embodiments of the present invention.  FIG. 2B  illustrates a memory module  250  according to other embodiments of the present invention. 
         [0042]    Referring to  FIG. 2A , the memory module  200  may include a substrate  210  and a stacked memory  230 . The substrate  210  may be a printed circuit board (PCB). The stacked memory  230  may include an interface chip IF and a plurality of memory chips ME_ 1 , ME_ 2 , ME_ 3 , and ME_ 4 . The interface chip IF is configured to transmit signals therefrom to selected ones of the memory chips ME_ 1 , ME_ 2 , ME_ 3 , and ME_ 4 , and to transmit signals that are received from the memory chips ME_ 1 , ME_ 2 , ME_ 3 , and ME_ 4  to other external circuitry (e.g., to a processor controller). When the memory module  200  is configured as a fully buffered dual in-line memory module (FBDIMM), the interface chip IF may be configured as an advanced memory buffer (AMB) chip. Each of the memory chips ME_ 1 , ME_ 2 , ME_ 3 , and ME_ 4  includes a memory core that includes a plurality of memory cells. For example, the memory chips ME_ 1 , ME_ 2 , ME_ 3 , and ME_ 4  may be configured as dynamic random access memory (DRAM). The interface chip IF may therefore include a memory core that includes of a plurality of memory cells. Accordingly, the interface chip IF can be configured to not only transmit and receive signals with the memory chips ME_ 1 , ME_ 2 , ME_ 3 , and ME_ 4 , but it can also store data in it&#39;s internal memory core. Hereinafter, an interface chip IF may or may not include the memory core. 
         [0043]    Although  FIG. 2A  illustrates that the four memory chips ME_ 1 , ME_ 2 , ME_ 3 , and ME_ 4  are stacked on the interface chip IF, it is to be understood that any number of memory chips can be stacked on the interface chip IF in accordance with various other embodiments. 
         [0044]    Referring to  FIG. 2B , the memory module  250  may include a substrate  260  and a stacked memory  280 . In contrast to the memory module  200  of  FIG. 2A , a plurality of memory chips ME_ 1  through ME_ 8  are stacked on opposite surfaces of the substrate  260  in the memory module  250  of  FIG. 2B . In detail, an interface chip IF is attached to one side of the substrate  260 , the memory chips ME_ 1 , ME_ 2 , ME_ 3 , and ME_ 4  are stacked on an opposite surface of the interface chip IF from the substrate  260 , and the memory chips ME_ 5 , ME_ 6 , ME_ 7 , and ME_ 8  are stacked on the opposite surface of the interface chip IF. Similarly, as described above with reference to  FIG. 2A , any number of memory chips can be stacked on the interface chip IF in accordance with various other embodiments. 
         [0045]      FIG. 3  is a block diagram of a semiconductor memory device  300  according to some embodiments of the present invention. Referring to  FIG. 3 , the semiconductor memory device  300  may include first through mth memory modules  310 _ 1 ,  310 _ 2 , . . .  310   —   m,  and a controller  350 . Each of the first through mth memory modules  310 _ 1 ,  310 _ 2 , . . . ,  310   —   m  may include a corresponding substrate from among first through mth substrates  330 _ 1 ,  330 _ 2 , . . . ,  330   —   m,  and corresponding n stacked memories from among first through nth stacked memories SME_ 11 , SME_ 12 , . . . , SME_mn. That is, the first memory module  310 _ 1  may include the first substrate  330 _ 1  and the first through nth stacked memories SME_ 11 , SME_ 12 , . . . , SME_ 1   n.  The mth memory module  310   —   m  may include the mth substrate  330   —   m  and the first through nth stacked memories SME_m 1 , SME_m 2 , . . . , SME_mn. Similarly, each of the other memory modules may also include a corresponding substrate and first through nth stacked memories. 
         [0046]    The first through nth stacked memories SME_ 11 , SME_ 12 , . . . , SME_mn included in the first through mth memory modules  310 _ 1 ,  310 _ 2 , . . . ,  310   —   m  may be realized as illustrated in  FIG. 2A  or  2 B. That is, although not shown, the first stacked memory SME_ 11  connected to the first substrate  330 _ 1  may include a first interface chip connected to the first substrate  330 _ 1 , and a plurality of memory chips stacked on the first interface chip in the vertical direction. Also, the nth stacked memory SME_ 1   n  connected to the first substrate  330 _ 1  may include an nth interface chip connected to the first substrate  330 _ 1 , and a plurality of memory chips stacked on the nth interface chip in the vertical direction. Similarly, the other stacked memories may include an interface chip and a plurality of memory chips. 
         [0047]    The controller  350  can exchange a signal, e.g., an address, a command, and/or data, with the first through mth memory modules  310 _ 1 ,  310 _ 2 , . . . ,  310   —   m.  That is, the controller  350  can control the first through nth stacked memories SME_ 11 , SME_ 12 , . . . , SME_mn connected to the respective substrates  330 _ 1  through  330   —   m  by exchanging the signal with the first through nth stacked memories SME_ 11 , SME_ 12 , . . . , SME_mn. 
         [0048]    The controller  350  transmits a signal to the interface chip of the first stacked memory SME_ 11  connected to the first substrate  330 _ 1 . If the signal is related to the first memory module  310 _ 1 , the interface chip of the first stacked memory SME_ 11  transmits the signal to the interface chip of the second stacked memory SME_ 12  connected to the first substrate  330 _ 1 . If the signal is related to the second memory module  310 _ 2 , the interface chip of the first stacked memory SME_ 11  does not transmit the signal to the interface chip of the second stacked memory SME_ 12 , but instead transmits it to the interface chip of the first stacked memory SME_ 21  connected to the second substrate  330 _ 2 . The interface chip of the nth stacked memory SME_ 1   n  connected to the first substrate  330 _ 1  transmits the signal to the controller  350 . 
         [0049]    For example, in order to read data from the second stacked memory SME_ 12  connected to the first substrate  330 _ 1 , the controller  350  transmits a read command for reading the data from the second stacked memory SME_ 12  to the interface chip of the first stacked memory SME_ 11  connected to the first substrate  330 _ 1 . The read command is related to the first memory module  310 _ 1 , and thus, the interface chip of the first stacked memory SME_ 11  does not transmit the read command to the interface chip of the first stacked memory SME_ 21  connected to the second substrate  330 _ 2 , but instead transmits it to the interface chip of the second stacked memory SME_ 12  connected to the first substrate  330 _ 1 . The interface chip of the second stacked memory SME_ 12  receives the read command and transmits it to a corresponding (addressed) memory chip among the stacked memory chips on the second stacked memory SME_ 12 , and the corresponding memory chip performs a read operation. The data read through the read operation is transmitted to the interface chip of the second stacked memory SME_ 12 , the interface chip of the second stacked memory SME_ 12  transmits the read data to the interface chip of the third stacked memory SME_ 13 , and then, the interface chip of the third stacked memory SME_ 13  transmits it to the interface chip of the fourth stacked memory SME_ 14 . Continuing the above exemplary operation, the read data is eventually transmitted to the interface chip of the nth stacked memory SME_ 1   n,  and then, the interface chip of the nth stacked memory SME_ 1   n  transmits it to the controller  350 . 
         [0050]    In order to read data from the nth stacked memory SME_mn connected to the mth substrate  330   —   m,  the controller  350  transmits a read command for reading the data from the nth stacked memory SME_mn to the interface chip of the first stacked memory SME_ 11  connected to the first substrate  330 _ 1 . Since the read command is related to the nth memory module  310   —   n,  the interface chip of the first stacked memory SME_ 11  does not transmit the read command to the interface chip of the second stacked memory SME_ 12  connected to the first substrate  330 _ 1 , but instead transmits it to the interface chip of the first stacked memory SME_ 21  connected to the second substrate  330 _ 2 . Likewise, the interface chip of the first stacked memory SME_ 21  transmits the read command to the interface chip of the first stacked memory SME_ 31  connected to the third substrate  330 _ 3 . Such forwarding operations are performed by subsequent exemplary numbered substrates to cause the read command to be transmitted to the interface chip of the first stacked memory SME_m 1  connected to the mth substrate  330   —   m.  The read command is related to the nth stacked memory SME_mn of the mth memory module  310   —   m,  and thus, the interface chip of the first stacked memory SME_m 1  transmits the read command to the interface chip of the second stacked memory SME_m 2  connected to the mth substrate  330   —   m.  Such signal forwarding operations are sequentially performed to cause the read command to be transmitted to the interface chip of the nth stacked memory SME_mn connected to the mth substrate  330   —   m.    
         [0051]    The interface chip of the nth stacked memory SME_mn receives the read command and transmits it to a corresponding (address) memory chip among the stacked memory chips on the nth stacked memory SME_mn, and the memory chip performs a read operation. The data read through the read operation is transmitted to the interface chip of the nth stacked memory SME_mn, and the interface chip of the nth stacked memory SME_mn transmits the read data to the interface chip of the nth stacked memory connected to the m−1th substrate. Then, the interface chip of the nth stacked memory connected to the m−1th substrate transmits the read data to the interface chip of the nth stacked memory connected to the m−2th substrate. Through the above operation, the read data is transmitted to the interface chip of the interface chip of the nth stacked memory SME_ 1   n  connected to the first substrate  330 _ 1 , and the interface chip of the nth stacked memory SME_ 1   n  transmits the read data to the controller  350 . 
         [0052]    Performing this exemplary signal transmission may reduce power consumption when transmitting a signal within the same memory module, and thereby reduce power consumption by the semiconductor memory device  300 . For example, assume that a first signaling mode is used when a signal is transmitted within the same memory module and a second signaling mode is used when a signal is exchanged between the controller  350  and a memory module or between memory modules. In this case, it may be possible to reduce power consumption in the semiconductor memory device  300  by setting power consumption in the first mode to be less than in the second mode. The first or second mode may be selected for use via a register setting. That is, the stacked memories may be manufactured to operate according to both the first and second modes, and the first or second mode may be selected for use via the register so that the selected mode can be used in conjunction with a port of each of the stacked memories. 
         [0053]    For example, it is assumed that a single signal is exchanged in the first signaling mode, and a pair of differential signals are transmitted in the second signaling mode. In this case, differential signals are exchanged between the controller  350  and the first memory module  310 _ 1  since the second mode is used therebetween. In sharp contrast, a single signal is transmitted between the interface chips of the first and second stacked memory SME_ 11  and SME_ 12  of the first memory module  310 _ 1  since the first signaling mode is used therebetween, which may thereby reduce the power consumption in the semiconductor memory device  300 . Likewise, the differential signals are exchanged between the controller  350  and the first memory module  310 _ 1  since the second signaling mode is used therebetween, and the single signal is exchanged between memory modules, e.g., the first memory module  310 _ 1  and the second memory module  310 _ 2 , since the first mode is used therebetween, which may thereby reduce power consumption in the semiconductor memory device  300 . 
         [0054]    As another example, it is assumed that the amplitude of a signal that is transmitted according to the first mode is smaller than that of a signal that is transmitted according to the second mode. In this case, the amplitude of a signal transmitted from the interface chip of the first stacked memory SME_ 11  of the first memory module  310 _ 1  to the interface chip of the second stacked memory SME_ 12  is smaller than that of a signal transmitted between the controller  350  and the first memory module  310 _ 1 , which may thereby reduce power consumption in the semiconductor memory device  300 . Similarly, the amplitude of a signal exchanged between memory modules, e.g., the first memory module  310 _ 1  and the second memory module  310 _ 2 , is smaller than that of a signal exchanged between the controller  350  and the first memory module  310 _ 1 , which may thereby reduce power consumption in the semiconductor memory device  300 . 
         [0055]    The interface chips and/or the controller  350  may be connected to one another in a daisy chain fashion. Also, the interface chips, e.g., the interface chips of the first stacked memory SME_ 11  and the second stacked memory SME_ 12 , may be connected to one another within the same module not only in a daisy chain configuration but also in a fly-by configuration. 
         [0056]      FIG. 4  is a block diagram of semiconductor memory device  400  according to other embodiments of the present invention. Referring to  FIGS. 3 and 4 , the semiconductor memory device  400  may include first through mth memory modules  410 _ 1 ,  410 _ 2 , . . . ,  410   —   m,  and a controller  450 . The first through mth memory modules  410 _ 1 ,  410 _ 2 , . . . ,  410   —   m  may be configured in a similar way to the first through mth memory modules  310 _ 1 ,  310 _ 2 , . . . ,  310   —   m  illustrated in  FIG. 3 . 
         [0057]    The controller  450  can exchange a signal, e.g., an address, a command, and/or data, with the first through mth memory modules  410 _ 1 ,  410 _ 2 , . . . ,  410   —   m.  That is, the controller  450  can control the first through nth stacked memories SME_ 11  through SMN_mn connected to substrates  430 _ 1  through  430   —   m  by exchanging the signal with the first through nth stacked memories SME_ 11  through SMN_mn. 
         [0058]    The controller  450  transmits a signal to an interface chip of the first stacked memory SME_ 11  connected to the first substrate  430 _ 1 . The interface chip of the first stacked memory SME_ 11  transmits the signal to an interface chip of the second stacked memory SME_ 12  connected to the first substrate  430 _ 1 . That is, the signal is transmitted to an interface chip of a stacked memory corresponding to the signal, and the signal output from the corresponding stacked memory is transmitted to the controller  450  via the same path through which the signal was transmitted. 
         [0059]    For example, in order to read data from the second stacked memory SME_ 12  connected to the first substrate  430 _ 1 , the controller  450  transmits a read command for reading the data from the second stacked memory SME_ 12  to the interface chip of the first stacked memory SME_ 11  connected to the first substrate  430 _ 1 . Since the read command is related to the second stacked memory SME  430 _ 2 , the interface chip of the first stacked memory SME_ 11  transmits the read command to the interface chip of the second stacked memory SME_ 12  connected to the first substrate  430 _ 1 . The interface chip of the second stacked memory SME_ 12  receives the read command and transmits it to a corresponding (addressed) memory chip from among stacked memory chips mounted thereon, and the memory chip performs a read operation. The data read through the read operation is transmitted to the interface chip of the second stacked memory SME_ 12 . The interface chip of the second stacked memory SME_ 12  transmits the read data to the interface chip of the first stacked memory SME_ 11 , and the interface chip of the first stacked memory SME_ 11  transmits it to the controller  450 . 
         [0060]    For example, in order to read data from the nth stacked memory SME_mn connected to the mth substrate  430   —   m,  the controller  450  transmits a read command for reading the data from the nth stacked memory SME_mn to the interface chip of the first stacked memory SME_ 11  connected to the first substrate  430 _ 1 . Since the read command is related to the nth stacked memory SME_mn, the interface chip of the first stacked memory SME_ 11  transmits the read command to the interface chip of the second stacked memory SME_ 12  connected to the first substrate  430 _ 1 . Likewise, the interface chip of the second stacked memory SME_ 12  transmits the read command to the interface chip of the third stacked memory SME_ 13 . Such forwarding operations are sequentially performed to cause the read command to be transmitted to an interface chip of the nth stacked memory SME_ 1   n  connected to the first substrate  430 _ 1 . The interface chip of the nth stacked memory SME_ 1   n  connected to the first substrate  430 _ 1  transmits the read command to an interface chip of the second substrate  430 _ 2  connected to the first stacked memory SME_ 21 . Such forwarding operations are sequentially performed to cause the read command to be transmitted to an interface chip of the nth stacked memory SME_mn connected to the mth substrate  430   —   m.    
         [0061]    The interface chip of the nth stacked memory SME_mn receives the read command and transmits it to a corresponding memory chip from among stacked memory chips mounted thereon, and the corresponding memory chip performs a read operation. The data read through the read operation is transmitted to the interface chip of the nth stacked memory SME_mn, the interface chip of the nth stacked memory SME_mn transmits the read data to an interface chip of the n−1th stacked memory connected to the mth substrate  430   —   m,  and then, the interface chip of the n−1th stacked memory connected to the mth substrate  430   —   m  transmits the read data to an interface chip of the n−2th stacked memory connected to the mth substrate  430   —   m.  Such forwarding operations are sequentially performed to cause the read data to be transmitted to the interface chip of the first stacked memory SME_ 11  connected to the first substrate  430 _ 1  via the same path in which the read command was received. Then, the interface chip of the first stacked memory SME_ 11  transmits the read data to the controller  450 . 
         [0062]      FIG. 5  is a block diagram of a semiconductor memory device  500  according to other embodiments of the present invention Referring to  FIGS. 3 through 5 , the semiconductor memory device  500  may include first through mth memory modules  510 _ 1 ,  510 _ 2 , . . . ,  510   —   m,  and a controller  550 . The first through mth memory module  510 _ 1 ,  510 _ 2 , . . . ,  510   —   m  may be configured in a similar way to the first through mth memory modules  310 _ 1 ,  310 _ 2 , . . . ,  310   —   m  illustrated in  FIG. 3 . 
         [0063]    The controller  550  can exchange a signal, such as an address, a command, and/or data, with the first through mth memory module  510 _ 1 ,  510 _ 2 , . . . ,  510   —   m.  That is, the controller  550  can control the first through nth stacked memories SME_ 11  through SME_mn that are respectively connected to substrates  530 _ 1  through  530   —   m  by exchanging the signal with the first through nth stacked memories SME_ 11  through SME_mn. 
         [0064]    The controller  550  exchanges a signal with an interface chip of the second stacked memory SME_ 12  connected to the first substrate  530 _ 1 . Although  FIG. 5  illustrates that the controller  550  directly exchanges a signal with the interface chip of the second stacked memory SME_ 12  connected to the first substrate  530 _ 1 , it is not limited thereto and may instead directly exchange a signal with an interface chip of a stacked memory other than the first stacked memory SME_ 11  or the nth stacked memory SME_ 1   n,  which is connected to the first substrate  530 _ 1 . 
         [0065]    If the signal is related to the first memory module  510 _ 1 , the interface chip of the second stacked memory SME_ 12  exchanges the signal with the interface chip of the first stacked memory SME_ 11  or the third stacked memory SME_ 13  connected to the first substrate  530 _ 1 . If the signal is related to the second memory module  510 _ 2 , the interface chip of the second stacked memory SME_ 12  exchanges the signal with an interface chip of the second stacked memory SME_ 22  connected to the second substrate  530 _ 2 . Although  FIG. 5  illustrates that the interface chip of the second stacked memory SME_ 12  directly exchanges a signal with the Interface chip of the second stacked memory SME_ 22  connected to the second substrate  530 _ 2 , it is not limited thereto and may instead directly exchange the signal with an interface chip of another stacked memory connected to the second substrate  530 _ 2 . 
         [0066]    For example, in order to read data from the third stacked memory SME_ 13  connected to the first substrate  530 _ 1 , the controller  550  transmits a read command for reading the data from the third stacked memory SME_ 13  to the interface chip of the second stacked memory SME_ 12  connected to the first substrate  530 _ 1 . Since the read command is related to the third stacked memory SME_ 13  of the first memory module  510 _ 1 , the interface chip of the second stacked memory SME_ 12  does not transmit the read command to the interface chip of the second stacked memory SME_ 22  connected to the second substrate  530 _ 2  but transmits it to the interface chip of the third stacked memory SME_ 13  connected to the first substrate  530 _ 1 . The interface chip of the third stacked memory SME_ 13  receives the read command and transmits it to a corresponding memory chip from among stacked memory chips, and the corresponding memory chip performs a read operation. The data read through the read operation is transmitted to the interface chip of the third stacked memory SME_ 13 , the interface chip of the third stacked memory SME_ 13  transmits the read data to the interface chip of the second stacked memory SME_ 12 , and then, the interface chip of the second stacked memory SME_ 12  transmits the read data to the controller  550 . 
         [0067]    For example, in order to read data from the nth stacked memory SME_mn connected to the mth substrate  530   —   m,  the controller  550  transmits a read command for reading the data from the nth stacked memory SME_mn to the interface chip of the first stacked memory SME_ 11  connected to the first substrate  530 _ 1 . Since the read command is related to the nth memory module  510   —   n,  the interface chip of the second stacked memory SME_ 12  does not transmit the read command to the interface chip of the first stacked memory SME_ 11  or the third stacked memory SME_ 13  connected to the first substrate  530 _ 1  but transmits the read command to the interface chip of the second stacked memory SME_ 22  connected to the second substrate  530 _ 2 . Likewise, the interface chip of the second stacked memory SME_ 22  transmits the read command to the interface chip of the second stacked memory SME_ 32  connected to the third substrate  530 _ 3 . Such  40  operations are sequentially performed to cause the read command to be transmitted to the interface chip of the second stacked memory SME_m 2  connected to the mth substrate  530   —   m.  Since the read command is related to the nth stacked memory SME_mn of the mth memory module  510   —   m,  the interface chip of the second stacked memory SME_m 2  does not transmit the read command to the interface chip of the first stacked memory SME_m 1  but transmits it to the interface chip of the third stacked memory SME_m 3 . Such porting operations are sequentially performed to cause the read command to be transmitted to the interface chip of the nth stacked memory SME_mn connected to the mth substrate  530   —   m.    
         [0068]    The interface chip of the nth stacked memory SME_mn receives the read command and transmits it to a corresponding memory chip from among the stacked memory chips, and the corresponding memory chip performs a read operation. The data read through the read operation is transmitted to the interface chip of the nth stacked memory SME_mn, the interface chip of the nth stacked memory SME_mn transmits the read data to the interface chip of the n−1th stacked memory connected to the mth substrate  430   —   m,  and then, the interface chip of the mth substrate  430   —   m  connected to the n−1th stacked memory transmits the read data to the interface chip of the n−2th stacked memory connected to the mth substrate  430   —   m.  Such forwarding operations are sequentially performed to cause the read data to be transmitted to the interface chip of the second stacked memory SME_m 2  connected to the mth substrate  530   —   m.  The interface chip of the second stacked memory SME_m 2  transmits the read data to the interface chip of the second stacked memory connected to the m−1th substrate, and the interface chip of the second stacked memory connected to the m−1th substrate transmits the read data to the interface chip of the second stacked memory connected to the m−2th substrate. Through these operations, the read data is transmitted to the interface chip of the second stacked memory SME_ 12  connected to the first substrate  530 _ 1 , and the interface chip of the second stacked memory SME_ 12  transmits the read data to the controller  550 . 
         [0069]    As illustrated in  FIGS. 3 ,  4 , and  5 , according to various embodiments of the present invention, it may be possible to reduce power consumption in the semiconductor memory devices  400  and  500  by reducing power consumption when transmitting a signal within the same memory module. That is, as described above, the exemplary first operational mode is used when a signal is exchanged within the same memory module, and the exemplary second operational mode is used when a signal is exchanged between the controller  450  (or  550 ) and a memory module or between memory modules, which may thereby reduce power consumption in the semiconductor memory device  400  (or  500 ). The first mode and the second mode may operate as described above. The interface chips and/or the controller  450  (or  550 ) may be connected to one another in a daisy chain configuration. 
         [0070]    The memory modules illustrated in  FIGS. 3 through 5  may be configured as FBDIMMs. In this case, a signal exchanged between a controller and a memory module or between memory modules may be subject to an FBDIMM protocol complying with one or more specifications from the Joint Electron Device Engineering Council (JEDEC). However, the various embodiments are not limited to of a signal within the same memory module subject to the FBDIMM protocol according to the JEDEC. 
         [0071]    Accordingly, various embodiments of a semiconductor memory device include a memory module in which a plurality of memory chips are stacked, and which are configured so as to potentially reduce not only power consumption when exchanging a signal within the memory module but also potentially reduce the length of a communication channel through which the signal is transmitted. 
         [0072]    While this invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.