Abstract:
Disclosure includes control methods and power controllers with load compensation adapted for a power supply powering a load. A disclosed power controller comprises a converter and a control circuit. The converter converts the load signal at a first node to output a load-compensation signal at a second node. The load signal corresponds to an output power provided from the power supply to the load, and the converter includes a low-pass filter coupled between the first and second nodes. The control circuit is coupled to an inductive device via a feedback node, for controlling the output power to make a cross voltage of the inductive device approach a target voltage, based on a feedback voltage at the feedback node. The higher the load-compensation signal the higher the target voltage.

Description:
BACKGROUND 
       [0001]    The present disclosure relates generally to switching-mode power supplies and control methods with regard to primary side control and load compensation. 
         [0002]    A power supply need provide a steady output voltage at an output power node to power a load. The regulation of the output voltage is commonly achieved by using detection devices, such as resistors and LT431, at a secondary side to detect the output voltage and then passing the detection result to the power controller at a primary side with the help of a photo coupler. This kind of control means is generally referred to as secondary side control. 
         [0003]    To eliminate the need of the detection devices at the secondary side and save the electric power there consumed, primary side control (PSC) is developed. PSC achieves the detection of the output voltage at the primary side, employing the theory of inductance coupling. 
         [0004]      FIG. 1  demonstrates switching-mode power supply  8  using PSC. Power supply  8  includes a flyback topology  10 , which uses a transformer with primary winding PRM, secondary winding SEC, and auxiliary winding AUX to isolate the primary side from the secondary side. As shown in  FIG. 1 , the primary and secondary sides have different grounds, isolated by the transformer. By switching power switch  15 , power controller  18  controls the energizing and de-energizing of the transformer. During a discharge time T DIS  when the transformer is de-energizing, secondary and auxiliary windings, SEC and AUX, discharge to charge output power node OUT and operation power node VCC, respectively. Because of inductance coupling, during discharge time T DIS , the cross voltage V SEC  across secondary winding SEC should be in certain proportion to the cross voltage V AUX  across auxiliary winding AUX. Power controller  18  detects cross voltage V AUX  via feedback node FB, and voltage-dividing resistors  13  and  14 , equivalently detecting cross voltage V SEC , which in a way is substantially equivalent to output voltage V OUT  at output power node OUT. Based on feedback voltage V FB  at feedback node FB, power controller  18  modifies compensation voltage V COM  at compensation node COM and accordingly controls the ON time, the OFF time, or the duty cycle of power switch  15 . Simply put, PSC monitors cross voltage V AUX  across auxiliary winding AUX to regulate output voltage V OUT . 
         [0005]    PSC might induce a phenomenon that the regulated output voltage V OUT  varies while load  20  is changed. It is because that parasitic resistance exists inevitably between output power node OUT and secondary winding SEC, such that output voltage V OUT  is somehow smaller than cross voltage V SEC  and the voltage difference there between increases along with the increase of output current I OUT . In other words, to make output voltage V OUT  substantially independent from output current I OUT , the target voltages that cross voltages V SEC  and V AUX  are controlled to approach shall increase as load  20  or output current I OUT  increases, such that the voltage difference between output power node OUT and secondary winding SEC is compensated. This kind of control concept for voltage regulation is generally referred to as load compensation. 
         [0006]    Load compensation introduces a positive feedback loop, which, if not well designed, might cause oscillation easily. According to load compensation, for a certain load  20 , the higher output current I OUT , the higher target voltages that cross voltages V SEC  and V AUX  are controlled to approach. Nevertheless, the higher target voltages also need further higher output current I OUT  to support, such that a positive feedback loop is formed. The oscillation that would company with a positive feedback loop should be avoided or damped, however, for good output voltage regulation. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]    The invention can be more fully understood by the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0008]      FIG. 1  demonstrates a switching-mode power supply using primary side control; 
           [0009]      FIG. 2  demonstrates a power controller adapted for replacing the power controller of the power supply in  FIG. 1  according to one embodiment of the invention; 
           [0010]      FIG. 3  demonstrates a peak detection circuit and a voltage-to-current converter; and 
           [0011]      FIG. 4  demonstrates the low-pass filter shown in  FIG. 2 ; and 
           [0012]      FIG. 5  shows waveforms of signals in  FIG. 2 . 
       
    
    
     DETAILED DESCRIPTION 
       [0013]    The following embodiments of the invention are used in but not limited to power supply  8  of  FIG. 1 . The invention is not limited to isolation structures, for example, the flyback topology exemplified in  FIG. 1 , and could be used in non-isolation structures, such as boosters. For instance, the invention might be embodied in a power controller, which detects cross voltage V AUX  of an auxiliary winding that inductively coupled to a primary winding coupled between an input voltage node and an output voltage node in a booster topology. 
         [0014]      FIG. 2  demonstrates power controller  30  adapted for being used in power controller  18  of power supply  8  of  FIG. 1  according to one embodiment of the invention. 
         [0015]    In one embodiment, circuit  34  determines the beginning of an ON time T ON , a period of time when power switch  15  is turned ON and performs a short circuit. For example, circuit  34  could detect the complete of de-energizing of the transformer and accordingly set SR register  32 , to turn on power switch  15 . 
         [0016]    Circuit  38  substantially determines the beginning of an OFF time T OFF , a period time when power switch  15  is turned OFF and performs an open circuit. For example, voltage divider  36  generates limiting voltage V COMI  at node COMI based on compensation voltage V COM  at compensation node COM. When current-sensing signal V CS  exceeds limiting voltage V COMI , circuit  38  resets SR register  32 , turning OFF power switch  15  and making it an open circuit. Accordingly, limiting voltage V COMI  substantially determines the peak voltage of current-sensing signal V CS . 
         [0017]    Peak detection circuit  42  provides peak signal V CS-P  representing the peak voltage of current-sensing signal V CS . As peak signal V CS-P  corresponds to the peak current flowing through primary winding PRM, it also corresponds to the output power currently output to load  20  from power supply  8 . 
         [0018]    At a moment within discharge time T DIS , a short-pulse of signal S SH  makes sample/hold circuit  40  sample feedback voltage V FB  at feedback node FB to hold and provide held voltage V FBIN  at node FBIN. The comparison result between held voltage V FBIN  and predetermined voltage V TAR0  determines the increase or decrease of compensation voltage V COM . When power supply  8  makes output voltage V OUT  a substantially constant, compensation voltage V COM  shall remain substantially unchanged over time, and held voltage V FBIN  shall be very close to, if not the same with, predetermined voltage V TAR0 . 
         [0019]    Converter  44  converts peak signal V CS-P  into load-compensation current I OffSet . Inside converter  44  are voltage-to-current converter  64  and low-pass filter  60 . Voltage-to-current converter  64  converts peak signal V CS-P  into corresponding current I OS . Low-pass filter  60  low passes current I OS  to generate load-compensation current I OffSet . Voltage-to-current converter  64  and low-pass filter  60  are exemplified and detailed later. 
         [0020]    Please refer to both  FIGS. 1 and 2 , where load-compensation current I OffSet  seems to be an offset current draining from feedback node FB to primary ground. As aforementioned, power controller  30  makes cross voltages V SEC  and V AUX  during discharge time T DIS  approach target voltages, respectively referred to as V SEC-TAR  and V AUX-TAR , where the ratio of target voltage V SEC-TAR  to target voltage V AUX-TAR  should equal to the turn ratio of secondary winding SEC to auxiliary winding AUX. During discharge time T DIS  and when output voltage V OUT  is substantially stabilized, the following equations should be complied. 
         [0000]        V   FB   =V   FBIN   =V   TAR0 ; 
         [0000]        V   FB   =V   AUX-TAR   *R   13 /( R   13   +R   14 )− I   OffSet   *R   13   *R   14 /( R   13   +R   14 );
 
         [0000]      and 
         [0000]        V   AUX-TAR   =I   OffSet   *R   14   +V   TAR0 *( R   13   +R   14 )/ R   13 ; 
         [0000]    where R 13  and R 14  represent resistances of resistors  13  and  14 , respectively. It can be derived from the last equation above that the higher load-compensation current I OffSet  the higher target voltage V AUX-TAR  and as a result, the higher target voltage V SEC-TAR . 
         [0021]    When output voltage V OUT  is substantially stabilized, power supply  8  provides a steady output power to load  20  and peak signal V CS-P  is about a constant. The higher peak signal V CS-P  means the higher output power. In the meantime, peak signal V CS-P  corresponds to both current I OS  and load-compensation current I OffSet , and the higher load-compensation current I OffSet  the higher target voltage V SEC-TAR . Accordingly, during the steady state when output voltage V OUT  is substantially stabilized, the higher output power the higher target voltage V SEC-TAR , achieving load compensation. 
         [0022]    Nevertheless, during a load transient when output voltage V OUT  has not been stabilized, peak signal V CS-P  might change dramatically, and low-pass filter  60  limits the variation rate of load-compensation current I OffSet . Once a signal that exists in a positive feedback loop is limited in view of it variation rate, the possibility of oscillation caused by the positive feedback loop is decreased or eliminated. Accordingly, with undue diligence in circuit design, low-pass filter  60  might depress or eliminate the oscillation caused by load compensation. 
         [0023]      FIG. 3  demonstrates peak detection circuit  42  and voltage-to-current converter  64  shown in  FIG. 2 . At the moment when power switch  15  is turned OFF, the switch in peak detection circuit  42  is turned OFF, such that peak signal V CS-P  stored on the capacitor substantially equals to the peak voltage of current-sensing signal V CS . Voltage-to-current converter  64  has an operational amplifier, a NMOS transistor, and a current mirror  63 , the operation of which can be well derived by persons skilled in the art and is not detailed herein for brevity. Voltage-to-current converter  64  provides current I OS  in proportion to peak signal V CS-P . 
         [0024]      FIG. 4  demonstrates low-pass filter  60  shown in  FIG. 2 . By periodically toggling signal V GATE  at gate node GATE, switched-capacitor low-pass filter  61  low passes the gate voltage at the control gate of NMOS  68  to provide another gate voltage at the control gate of NMOS  66 . In the long run when output voltage V OUT  is stabilized, the gate voltage of NMOS  66  should be equal to that of NMOS  68 , forming a current mirror. 
         [0025]    In the embodiment of  FIG. 2 , peak signal V CS-P  is used as an output power indicator corresponding to the output power that power supply  8  provides to load  20 , and load-compensation current I OffSet  is generated according to peak signal V CS-P . In other embodiments, compensation voltage V COM  or limiting voltage V COMI  could be an output power indicator to generate current I OS  and load-compensation current I OffSet . 
         [0026]    In an embodiment, converter  44  that converts peak signal V CS-P  to load-compensation current I OffSet  might have a LPF to first low pass peak signal V CS-P , outputting a filtered result V CS-LP , and a voltage-to-current converter to second convert the filtered result V CS-LP  into load-compensation current I OffSet . 
         [0027]    At the beginning of a startup period when, for example, a power supply is just connected to a grid outlet, the power controller of the power supply will deem the load as being heavy no matter what the load actually is, because the output voltage to the load starts from a value much lower than the required one. If load compensation starts at the startup period, load compensation will make target voltages V SEC-TAR  and V AUX-TAR  much higher during the startup period. The output voltage, as pulled by the much higher target voltage V SEC-TAR , might easily overshoots if the load is light or zero in real, and the stabilization of the output voltage might be adversely delayed. 
         [0028]    Comparator  70  and load-compensation controller  62  both in  FIG. 2  could solve the output voltage overshooting caused by load compensation. Basically speaking, during the startup period, comparator  70  and load-compensation controller  62  prohibit the execution of load compensation. Only if output voltage V OUT  is almost well built, or exceeds a certain level, then load compensation is executed softly, or little by little. 
         [0029]      FIG. 5  shows waveforms of signals in  FIG. 2 , corresponding, from top to bottom, held voltage V FBIN , signal S EN , ramp signal S SC , peak signal V CS-P , and load-compensation current I OffSet . Held voltage V FBIN  is the sampled result from feedback voltage V FB  during discharge time T DIS , substantially in proportion to output voltage V OUT  if load compensation is not introduced. Before time point t S , peak signal V CS-P  stays at its maximum because output voltage V OUT  is very low, held voltage V FBIN  goes up as output power node OUT is steadily charged. In the meantime, held voltage V FBIN  is lower than predetermined reference voltage V REF , such that signal S EN  output by comparator  70  is 0 in logic, ramp signal S SC  is 0V, load-compensation current I OffSet  is forced by load-compensation controller  62  to be 0A, and, as a result, no load compensation is introduced. 
         [0030]    At time point t S  when held voltage V FBIN  exceeds predetermined reference voltage V REF , comparator  70  turns its output to 1 in logic and ramp signal S SC  starts to rise, causing load-compensation current I OffSet  to increase slowly. In other words, load compensation is softly introduced and load-compensation current I OffSet  is softly or little by little built. At time point t E  when ramp signal S SC  reaches its highest value, load compensation is completely introduced and load-compensation current I OffSet  is controlled by peak signal V CS-P . The time period from time point t S  to time point t E  when load compensation is softly introduced is referred to as soft-compensation time T SC . 
         [0031]    It is shown in  FIG. 2  that load-compensation controller  62  influences load-compensation current I OffSet  with the help from voltage-to-current converter  64  and low-pass filter  60 . In another embodiment, load-compensation controller  62  might influence load-compensation current I Offset  directly without low-pass filter  60  therebetween. 
         [0032]    As shown in  FIG. 5 , predetermined reference voltage V REF  could be very close to, but smaller than predetermined voltage V TAR0 , which as shown in  FIG. 2  is used to compare with held voltage V FBIN . In another embodiment, predetermined reference voltage V REF  is equal to predetermined voltage V TAR0 . 
         [0033]    While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.