Abstract:
A background-calibrated comparator and a background-calibrated flash analog-to-digital converter are disclosed for using in mixed-signal integrated circuit design in particular on the high-speed analog-to-digital converter circuit. Without affecting the operation of the comparator, the disclosure is directed at reducing the unpredictable input offset voltage originated from the variation of process parameters and environmental factors. The background-calibrated comparator includes a random chopping comparator, a calibration processor, and a random sequence generator. The background-calibrated flash analog-to-digital converter (ADC) includes a background-calibrated comparator array together with a reference voltage generator, a thermometer code edge detector, and a set of digital encoders.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a background-calibrated comparator (BCC) and a background-calibrated flash analog-to-digital converter (ADC), which are used on design of mixed-signal integrated circuit, in particular on the high-speed analog-to-digital converter circuit. 
   2. Discussion of Related Art 
   U.S. Pat. No. 6,459,394B1 entitled “Multi-bank flash ADC array with uninterrupted operation during offset calibration and auto-zero” has disclosed a flash ADC array in which the comparators are separated into two groups. When one group of comparators is processing calibration, the other group of comparators can maintain the operation of the ADC. However, it will degrade the resolution of the ADC for half. Also, this method requires calibration in approximately every 400 ms, which means the entire resolution of the ADC will degrade periodically and the method thus can only be used in the intermittent system of reading a disk. 
   U.S. Pat. No. 6,084,538 entitled “Offset calibration of a flash ADC array” uses conventional means of capacitor storage to calibrate and expiate the offset voltage of a single comparator. To achieve the object of background-calibration, the calibration circuit takes turns to selectively calibrate each single comparator. The comparators need to be split from the signal path during calibration and be rejoined after the calibration is done. To the entire ADC, there exists a “bubble” in the output thermometer codes because there is always a comparator in calibration. The encoder in the downstream part thus requires special design to suppress the error caused by the bubble. This method causes great complexity and large amount of wires in the circuit, whereby the operation speed is restrained. 
   “Offset calibrating comparator array for 1.2-V, 6-bit, 4-Gsample/s flash ADCs using 0.13-μm CMOS technology” by H. Okada, Y. Hashimoto, K. Sakata, T. Tsukada, and K. Ishibashi, ESSCIRC 2003 Proceedings, September 2003, pp. 711–714 has disclosed a pre-calibration method, wherein the calibration circuit generates a triangle wave as an input signal before the circuit operation initiates. The value of the offset voltage of each comparator is determined by the conversion property of the ADC, whereby the reference voltage of each comparator is adjusted to expiate its offset. Since pre-calibration is adopted in this method, the calibration cannot be carried once the circuit operation initiates. 
   “A 2.5-V 12-b 54-Msample/s 0.25-mm CMOS ADC in 1-mm2 with mixed-signal chopping and calibration,” by H. van der Ploeg, G. Hoogzaad, H. A. H. Termeer, M. Vertregt, and R. L. J. Roovers, IEEE J. Solid-State Circuits, vol. 36, pp. 1859–1867, December 2001 has disclosed a two-step ADC with background calibration. In the paper, a random chopping method similar to that of the present invention is adopted to calibrate the residue amplifier. However, the object to be calibrated in this paper is an amplifier, the offset information is therefore easy to be obtained in the process of random chopping, unlike in the present invention, where the offset is hidden among big quantization noises and is difficult to be obtained since the object to be treated in the present invention is a comparator. 
   Additionally, the calibration loop in this paper employs the manner of periodical adjustment, which periodically detects if the accumulated output of the amplifier exceeds a predetermined threshold and adjusts the offset accordingly. However, compared with the present invention, the calibration method disclosed in this paper is not efficient enough because the offset cannot be instantly adjusted due to the periodical adjustment. 
   SUMMARY OF THE INVENTION 
   A background-calibrated comparator and a background-calibrated flash analog-to-digital converter are disclosed in the present invention. The former is composed of a random-chopping comparator and a calibration processor. The latter comprises a comparator array consisting of windowed background-calibrated comparators. The remainder parts of the background-calibrated flash analog-to-digital converter are similar to those of a standard analog-to-digital converter. 
   The calibration processor of the background-calibrated comparator utilizes accumulators and simple logics to obtain the polarity information of the comparator input offset voltage, according to the statistical characteristics of its output digital codes. Inside the comparator, there exists an offset-tuning mechanism, which is controlled by the calibration processor and can be used to calibrate the input offset voltage. The calibration process operates simultaneously to adjust the comparator input offset voltage close to zero and does not influence the normal function of comparison. As the calibration converges, due to the stochastic nature, the offset voltage fluctuation around zero instead of staying static. The fluctuation is referred as an input noise, which can be suppressed not to degrade the comparator performance by accurately estimating and selecting related parameters. 
   For a background-calibrated flash analog-to-digital converter that has N-bit resolution, the comparator array is composed of 2 N −1 windowed background-calibrated comparators. In each windowed background-calibrated comparator, the output of the random chopping comparator is processed by the thermometer code edge detector before it can be used as the input of the calibration processor. 
   The thermometer code edge detector detects the thermometer code generated from the random chopping comparators and produces 2 N  digital bits among which only the bit corresponding to the 0–1 edge of the thermometer code is 1. The output of the thermometer-code edge detector is the input of the calibration processor as well as the encoding bases of the output binary codes. 
   In the calibration loop, the thermometer-code edge detector plays a role to confine the input signal swing for a single comparator so that only when input signal falls in the vicinity of the corresponding reference voltage the background calibration is activated. This confinement is equivalent to a windowing effect, which can largely suppress the fluctuation noise and reduce the influence of non-uniform distributed input signal over the calibration performance. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a circuit diagram showing a random chopping comparator (RCC) according to a preferred embodiment of the present invention; 
       FIG. 2  is a complete block diagram showing a background-calibrated comparator (BCC) according to the preferred embodiment of the present invention; and 
       FIG. 3  is a circuit diagram showing a background-calibrated flash analog-to-digital converter (ADC) according to the preferred embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
   Now the preferred embodiments according to the present invention will be described with reference to the accompanying drawings. Since preferred embodiments are provided for the purpose that the ordinary skilled in the art are able to understand the present invention, they may be modified in various manners and the scope of the present invention is not limited by the preferred embodiments described later. Further, in the drawing, like reference numerals are used to identify the same or similar parts. 
   A background-calibrated comparator and a background-calibrated flash analog-to-digital converter are disclosed in the present invention; the former is composed of a random-chopping comparator and a calibration processor and the latter comprises a comparator array consisting of windowed background-calibrated comparators while the remainder parts of the background-calibrated flash analog-to-digital converter are similar to those of a standard analog-to-digital converter. 
     FIG. 1  shows a random chopping comparator (RCC) according to a preferred embodiment of the present invention, which comprises a comparator together with two choppers CHP 1  and CHP 2 . The input offset voltage V OS  of the comparator is unknown; however, the comparator has an internal mechanism for tuning the V OS , wherein the V OS  is compensated by being controlled by an external digital control signal T[k]. CHP 1  and CHP 2  both have two states: in the forward state, input signals are directly connected to the input terminals of the comparator and the digital signal outputted from the comparator serves as an output signal; in the reversed state, input signals are inversed and connected to the input terminals of the comparator and the digital signal outputted from the comparator is inversed and serves as an output signal. 
   CHP 1  and CHP 2  are both under the control of random sequence q[k], which is generated by an independent random sequence generator. The probability of generating a forward or a reversed signal is 50% and has nothing to do with the input signal of the comparator (“k” represents the discrete time index). Based on the operation principle of CHP 1  and CHP 2 , when q[k] is negative, the operation of the random chopping comparator is not affected but the polarity of its input offset voltage V OS  is reversed. 
   A correlated variable “U” is defined while the RCC is in operation. When the output of the comparator is “1” and q[k] is “forward”, “U” is “+1”; when the output of the comparator is “1” and q[k] is “reversed”, “U” is “−1”; and when the output of the comparator is “0”, “U” is “0”. According to the aspect of statistics, accumulation of “U” reflects the value of V OS  as shown in  FIG. 1 . When V OS  is positive, the accumulation tends to decrease; when V OS  is negative, the accumulation tends to increase. 
     FIG. 2  is a complete block diagram showing a background-calibrated comparator (BCC) according to the preferred embodiment of the present invention, wherein above the dotted line is a schematic view of a RCC, and below the dotted line is a calibration processor (CP) serving to automatically calibrate the input offset voltage of the comparator. The calibration processor comprises two accumulators ACC 1  and ACC 2  and a bilateral peak detector (BPD). ACC 1  accumulates the value of U[k] and outputs an accumulation result R[k]. According to the aforementioned description, the variation of R[k] reflects the value of V OS , whereby the polarity of V OS  can be estimated. The longer the accumulation time, the more the number of times of the accumulation and the higher the reliability are. 
   BPD is used to monitor R[k], wherein in the BPD exists a predetermined threshold N C ; whenever R[k] is higher than N C , BPD outputs the signal of S[k]=+1; whenever R[k] is lower than −N C , BPD outputs the signal of S[k]=−1. S[k] remains “0” in the other cases. Once S[k] is non-zero, ACC 1  will be reset to “0” synchronously, and the accumulation will restart. Therefore the non-zero S[k] can only remain for one clock cycle. The non-zero S[k] is sufficiently reliable to be used to determine the polarity of V OS . 
   ACC 2  functions to accumulate S[k], wherein the accumulation result T[k] of which is used for controlling the offset voltage of the comparator. Whenever T[k] adds 1, the offset voltage increases for a fixed small amount ΔV. V OS  can be expressed as V OS [k]=V OS [0]+T[k]×ΔV in any time, where V OS [0] is the inherent offset voltage of the comparator before the calibration loop initiates. 
   V OS  does not converge to a fixed value but fluctuates around “0”. The fluctuation can be referred as an input noise, which is related to N C  and V. The noise can be maintained in the range not to affect the performance of the comparator by estimating and selecting variables according to the random process theory. 
     FIG. 3  shows a background-calibrated flash analog-to-digital converter (ADC) with N-bit resolution according to the preferred embodiment of the present invention. The comparator array in  FIG. 3  comprises 2 N −1 windowed BCC, whose structure is a little different from that of the BCC in  FIG. 2 . The output signals of the RCC of the windowed BCC are first processed by a thermometer code edge detector (TCED), calibration processors then use the outputs of the TCED as input signals. 
   TCED consists of AND gates. The thermometer codes generated by the comparator array serve as the input of the TCED, which outputs 2 N  bits and only the bits corresponding to the 0–1 edge of the thermometer codes are “1” while the remainder bits are “0”. The TCED can detect the edge of the thermometer codes “1” and “0”, which is the basic component of a flash ADC. The combination of BCC and TCED enforces U to be non-zero only when the input signal is near the corresponding reference voltage of each comparator. This adjustment is equivalent to introducing a “windowing” effect to every BCC, which can greatly suppress the fluctuation noise and reduce the influence on the calibration performance caused by the inhomogeneous distribution of the input signals. 
   Although the foregoing description has been made with reference to the preferred embodiments, it is to be understood that changes and modifications of the present invention may be made by the ordinary skilled in the art without departing from the spirit and scope of the present invention and appended claims.