Abstract:
A signal processing circuit for optical encoder, including: a plurality of photodiodes for detecting light in different phase; IV conversion circuits for providing outputs by converting photo currents outputted from a current output terminal of each photodiode respectively into voltage signals; differential amplification circuits for amplifying difference between the output voltage signals corresponding to each photodiode; a DC signal detection circuit for detecting DC components of the photo currents; and a suppressing current generation circuit for supplying suppressing currents for suppressing the DC components to the current output terminals of the photodiodes in accordance with a value of the detected DC components.

Description:
[0001]    This application claims benefit of Japanese Patent Application No. 2006-252259 filed in Japan on Sep. 19, 2006, the contents of which are incorporated by this reference. 
       BACKGROUND OF THE INVENTION  
       [0002]    The present invention relates to a signal processing circuit for optical encoder for detecting movement information such as an amount and direction of movement or angular displacement. 
         [0003]    Among those having been developed as an optical encoder for detecting movement information such as an amount and direction of movement or angular displacement are: an optical path interrupting encoder in which a scale having slits at a certain interval thereon is moved so as to interrupt an optical path between a light source and a light receiving device so that light/dark of transmitted light is detected to obtain a position information; and a diffraction image projection encoder in which a light is radiated on a scale from a light source and a movement of light/dark of diffraction interference pattern by the reflected light is detected at a light receiving section to obtain a position information. 
         [0004]    As a prior-art example of such encoder, a general plane view and side view of a diffraction image projection encoder disclosed in Japanese Patent Application Laid-Open 2000-205819 are shown in  FIGS. 1A and 1B . What is denoted by  301  in  FIGS. 1A and 1B  is a light source. A light emitted from the light source  301  is radiated on a reflecting-type diffraction grating scale  302  where stripes of light/dark are alternately placed. The diffraction image projection encoder is constructed so that a specific portion of thus produced diffraction interference pattern is detected at an optical detector  304  disposed in parallel to the scale  302  with having a plurality of light receiving areas  303 . A photodiode for example is used for the light receiving area  303  as a means for detecting signal intensity. 
         [0005]    Referring to  FIGS. 1A and 1B : z 1  represents the distance between the light source  301  and the plane in which the diffraction grating on the scale  302  is formed; z 2 , distance between the plane in which the diffraction grating on the scale  302  is formed and the light receiving plane of the optical detector  304 ; p 1 , pitch of the diffraction grating on the scale  302 ; and p 2 , pitch of diffraction interference pattern on the light receiving plane of the optical detector  304 . It should be noted that, hereinafter, “pitch of diffraction grating on the scale” refers to a spatial period of pattern where optical characteristics formed on the scale  302  are modulated. Further, “pitch of diffraction interference pattern on the light receiving plane of the optical detector” refers to a spatial period of intensity distribution of diffraction interference pattern produced on the light receiving plane of the optical detector  304 . 
         [0006]    An operation of the diffraction image projection encoder constructed as the above will now be described. According to the diffraction theory of light, when a specific relationship between the above described distances z 1 , z 2  exists so as to satisfy the expression of (1), an intensity pattern similar to the diffraction grating pattern on the scale  302  is produced on the light receiving plane of the optical detector  304 . 
         [0000]      1/ z 1+1 /z 2=λ/ k ( p 1) 2    (1) 
         [0000]    where λ is the wavelength of light beam radiated from the light source  301 , and k is an integer. Given expression (1), pitch p 2  of the diffraction interference pattern in the light receiving plane is expressed as in the expression (2) using other constituent parameters. 
         [0000]        p 2 =p 1( z 1 +z 2)/ z 1   (2) 
         [0007]    When the scale  302  is displaced in the direction of pitch of the diffraction grating in relation to the light source  301 , the distribution intensity of the diffraction interference pattern is moved in the direction of displacement of the scale  302  with keeping the same spatial period. Accordingly, if a spatial period p 20  of the light receiving area  303  of the optical detector  304  is set to the same value as the diffraction interference pattern p 2  in the light receiving plane, a periodical signal intensity is obtained from the optical detector  304  every time when the scale  302  is moved by p 1  in the pitch direction. A displacement amount in the pitch direction of the scale  302  is thereby detected. In other words, an output signal that changes by a periodical intensity is obtained from the optical detector  304  every time when the scale  302  is displaced by 1 pitch in the direction of pitch of the diffraction grating. 
         [0008]      FIG. 2  shows a plan in the case where the light receiving plane of the optical detector  304  of the prior-art example is seen from the side of the scale  302 . In  FIG. 2 , what is denoted by  304  is the optical detector. On the optical detector  304 , there are four light receiving area groups, each consisting of a plurality (3 in the illustrated example) of light receiving areas  303  formed at an interval of p 20  which is expressed as p 20 =np 1 (z 1 +z 2 )/z 1  (n being a natural number). The plurality of light receiving areas of each of these groups alternate with the others in a manner shifted from one another by a spatial position shift δ p 20  of each group. It should be noted that the spatial position shift δ p 20  is set to an odd-number multiple of ¼ of the diffraction interference pattern p 2  in the light receiving plane. Each light receiving area of the 4-group construction is connected respectively through a wiring to output pads  305 A,  305 A′,  305 B, and  305 B′. 
         [0009]    An operation of the optical detector of the prior-art example having such construction will now be described. Referring to  FIG. 2 , since the spatial position shift of each light receiving area group is set to an odd-number multiple of (p 2 ×¼), signals with phase shifted by ¼ period from one another or A phase, B phase, inverted-A phase, and inverted-B phase of a so-called encoder signal are outputted from the respective pads  305 A,  305 A′,  305 B, and  305 B′. Since the signals of A phase and inverted-A phase, and of B phase and inverted-B phase respectively have an inverted phase relationship with each other, an encoder signal can be obtained by taking a difference signal between A phase and inverted-A phase, and a difference signal between B phase and inverted-B phase. 
       SUMMARY OF THE INVENTION  
       [0010]    In a first aspect of the invention, there is provided a signal processing circuit for optical encoder, including: a plurality of photodiodes for detecting light in different phase; IV conversion circuits for providing outputs by converting photo currents outputted from a current output terminal of each photodiode respectively into voltage signals; differential amplification circuits for amplifying difference between the output voltage signals corresponding to each photodiode; a DC signal detection circuit for detecting DC components of the photo currents; and a suppressing current generation circuit for supplying suppressing currents for suppressing the DC components to the current output terminals of the photodiodes in accordance with a value of the detected DC components. 
         [0011]    In a second aspect of the invention, the DC signal detection circuit in the signal processing circuit for optical encoder according to the first aspect receives as input the output voltage signals corresponding to each photodiode and outputs DC components of the photo currents as DC voltage signal, and the suppressing current generation circuit includes a DC signal monitoring circuit for monitoring the DC voltage signal, a VI conversion circuit for converting the DC voltage signal into a current value corresponding to result of the monitoring so as to output it as the suppressing current, and a current mirror circuit for copying the suppressing current and supplying it to the current output terminals of each photodiode. 
         [0012]    In a third aspect of the invention, the VI conversion circuit in the signal processing circuit for optical encoder according to the second aspect includes a gain regulating amplifier for regulating gain of the DC voltage signal in accordance with result of the monitoring, a resistor, an operational amplifier for applying the DC voltage signal regulated of gain to the resistor, and a transistor for controlling electric current flowing through the resistor. The gain-regulated DC voltage signal is converted into a current value so as to be outputted as the suppressing current. 
         [0013]    In a fourth aspect of the invention, the VI conversion circuit in the signal processing circuit for optical encoder according to the second aspect includes a variable resistor capable of changing resistance value thereof in accordance with result of the monitoring, an operational amplifier for applying the DC voltage signal to the variable resistor, and a transistor for controlling electric current flowing through the variable resistor. The DC voltage signal is converted into a current value corresponding to the resistance value of the variable resistor so as to be outputted as the suppressing current. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0014]      FIGS. 1A and 1B  are a plane view and side view showing construction of a prior-art diffraction image projection encoder. 
           [0015]      FIG. 2  is a plan where a light receiving surface of the optical detector in the diffraction image projection encoder shown in  FIGS. 1A and 1B  is seen from the side of the scale. 
           [0016]      FIG. 3  is a circuit diagram showing construction of a first embodiment of the signal processing circuit for optical encoder according to the invention. 
           [0017]      FIG. 4  is a circuit diagram showing construction of the signal processing circuit for optical encoder according to a second embodiment of the invention. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0018]    A description will now be given by way of the drawings with respect to some embodiments of the signal processing circuit for optical encoder according to the invention. 
       Embodiment 1  
       [0019]    A first embodiment of the signal processing circuit for optical encoder according to the invention will now be described.  FIG. 3  is a circuit diagram showing construction of the signal processing circuit for optical encoder according to the first embodiment. Referring to  FIG. 3 ,  101   a ,  101   a ′,  101   b , and  101   b ′ each are a photodiode for converting optical signal into an electric current signal, each cathode terminal of the photodiode group being connected to a power supply voltage VCC. Further, the anode terminals thereof are respectively connected to inverting input terminals of operational amplifiers  102   a ,  102   a ′,  102   b ,  102   b ′ of which the respective non-inverting input terminals are connected to a reference potential (ground potential). Resistors  103   a ,  103   a ′,  103   b , and  103   b ′ each having a resistance value R 1  are connected between the inverting input terminal and the output terminal of the operational amplifiers  102   a ,  102   a ′,  102   b , and  102   b′.    
         [0020]    An output of the operational amplifier  102   a  is connected to one terminal of a resistor  105   a  having a resistance value R 2  of which the other terminal is connected to an inverting input terminal of an operational amplifier  104   a . An output of the operational amplifier  102   a ′ is connected to one terminal of a resistor  105   a ′ having a resistance value R 2  of which the other terminal is connected to a non-inverting input terminal of the operational amplifier  104   a . It should be noted that a resistor  106 - 1   a  having a resistance value R 3  is connected between the inverting input terminal and the output terminal of the operational amplifier  104   a  while a resistor  106 - 2   a  having a resistance value R 3  is connected between the non-inverting input terminal and the reference potential (ground potential), and the output terminal of the operational amplifier  104   a  is connected to an encoder signal output terminal  107   a.    
         [0021]    Further, an output of the operational amplifier  102   b  is connected to one terminal of a resistor  105   b  having a resistance value R 2  of which the other terminal is connected to an inverting input terminal of an operational amplifier  104   b.  An output of the operational amplifier  102   b ′ is connected to one terminal of a resistor  105   b ′ having a resistance value R 2  of which the other terminal is connected to a non-inverting input terminal of the operational amplifier  104   b . It should be noted that a resistor  106 - 1   b  having a resistance value R 3  is connected between the inverting input terminal and the output terminal of the operational amplifier  104   b  while a resistor  106 - 2   b  having a resistance value R 3  is connected between the non-inverting input terminal and the reference potential (ground potential), and the output terminal of the operational amplifier  104   b  is connected to an encoder signal output terminal  107   b.    
         [0022]    Further, the outputs of the operational amplifiers  102   a ,  102   a ′,  102   b , and  102   b ′ are respectively connected to one terminal of resistors  109   a ,  109   a ′,  109   b , and  109   b ′ each having a resistance value R 4  of which the other terminal are connected to an inverting input terminal of an operational amplifier  108 . A non-inverting input terminal of the operational amplifier  108  is connected to a reference potential (ground potential), and a resister  110  having a resistance value R 4 /4 is connected between the inverting input terminal and the output terminal thereof. 
         [0023]    An output terminal of the operational amplifier  108  is connected to a DC signal monitoring circuit  111  and to a gain regulating amplifier  112 , and an output of the DC signal monitoring circuit  111  is transmitted as control signal to the gain regulating amplifier  112 . The DC signal monitoring circuit  111  is composed of a differential amplifier where DC voltage signal from the operational amplifier  108  is compared with a target reference DC voltage to generate a difference signal. Such difference signal is transmitted as control signal to the gain regulating amplifier  112 . An output of the gain regulating amplifier  112  is connected to a non-inverting input terminal of the operational amplifier  113 , and an inverting input terminal of the operational amplifier  113  is connected to one terminal of a resistor  114  having a resistance value R 5  of which the other terminal is connected to a reference potential (ground potential). An output of the operational amplifier  113  is connected to the gate terminal of a transistor  115  of which the source terminal is connected to the inverting input terminal of the operational amplifier  113 . 
         [0024]    The drain terminal of the transistor  115  is connected to an input terminal of a current mirror circuit  116 , and an output terminal of the current mirror circuit  116  is connected to an input terminal of a current mirror circuit  117  which has four output terminals. Each output terminal of the current mirror circuit  117  is respectively connected to the anode terminal of the photodiodes  101   a ,  101   a ′,  101   b , and  101   b′.    
         [0025]    The operational amplifier  102   a  and resistor  103   a , the operational amplifier  102   a ′ and resistor  103   a ′, the operational amplifier  102   b  and resistor  103   b , and the operational amplifier  102   b ′ and resistor  103   b ′ respectively constitute IV conversion circuits  118   a ,  118   a ′,  118   b , and  118   b ′ at which photo current signals outputted from photodiodes  101   a ,  101   a ′,  101   b , and  101   b ′ are respectively converted into voltage signals to be outputted. The operational amplifier  104   a , resistors  105   a ,  105   a ′,  106 - 1   a , and  106 - 2   a  constitute a differential amplification circuit  119   a  which obtains and amplifies the differential signal between the respective output voltage signals of the IV conversion circuits  118   a  and  118   a ′. The operational amplifier  104   b , and resistors  105   b ,  105   b ′,  106 - 1   b , and  106 - 2   b  constitute a differential amplification circuit  119   b  which obtains and amplifies the differential signal between the respective output voltage signals of the IV conversion circuits  118   b  and  118   b′.    
         [0026]    The operational amplifier  108 , resistors  109   a ,  109   a ′,  109   b , and  109   b ′, and resistor  110  constitute a DC signal detection circuit  119  which adds up the output voltage signals of the respective IV conversion circuits  118   a ,  118   a ′,  118   b , and  118   b ′ to detect DC component of the optical signals. The gain regulating amplifier  112 , operational amplifier  113 , resistor  114 , transistor  115 , and current mirror circuit  116  constitute a VI conversion circuit  120  which converts DC voltage signal into a current value and outputs it as a suppressing current. The DC signal monitoring circuit  111 , VI conversion circuit  120 , and current mirror circuit  117  constitute a suppressing current generation circuit  121  which supplies the suppressing current for suppressing the DC component to anode terminals that are the photo current output terminals of the photodiodes  101   a ,  101   a ′,  101   b , and  101   b ′ in accordance with the value of the DC component. 
         [0027]    An operation will now be described of thus constructed signal processing circuit for optical encoder according to the first embodiment. From the photodiodes  101   a ,  101   a ′,  101   b , and  101   b ′ in  FIG. 3 , photo currents are respectively detected with a shift in phase respectively of ½ period between the photodiodes  101   a  and  101   a ′, ½ period between the photodiodes  101   b  and  101   b ′, ¼ period between the photodiodes  101   a  and  101   b , and ¼ period between the photodiodes  101   a ′ and  1101   b ′. The photo currents respectively detected at each of the photodiodes, after subtraction of the suppressing current If produced by the suppressing current generation circuit  121 , is inputted respectively to the IV conversion circuits  118   a ,  118   a ′,  118   b , and  118   b ′ that correspond to each photodiode. 
         [0028]    Here, supposing Ia, Ia′, Ib, and Ib′ as AC current components of photo current generated by difference in light/dark of the lights incident respectively on the photodiodes  101   a ,  101   a ′,  101   b , and  101   b ′, and Idc as DC current component generated by dark current and the continuously incident light or in other words a background light, the voltage signals Va, Va′, Vb, and Vb′ outputted from each IV conversion circuit  118   a ,  118   a ′,  118   b , and  118   b ′ are respectively expressed by the expressions (3) to (6). 
         [0000]        Va=−R   1  ( Ia+Idc−If )   (3) 
         [0000]        Va′=−R   1 ( Ia′+Idc−If )   (4) 
         [0000]        Vb=−R   1 ( Ib+Idc−If )   (5) 
         [0000]        Vb′=−R   1 ( Ib′+Idc−If )   (6) 
         [0029]    Next, the voltage signals Va and Va′ outputted from the IV conversion circuits  118   a ,  118   a ′ are inputted to the differential amplification circuit  119   a , and the voltage signals Vb and Vb′ outputted from the IV conversion circuits  118   b ,  118   b ′ are similarly inputted to the differential amplification circuit  119   b  so that these are respectively differentiated and amplified. The signals operated and amplified at each of the differential amplification circuits  119   a ,  119   b  are respectively outputted to the encoder signal output terminals  107   a  and  107   b . The encoder signals VAout, VBout to be outputted to the respective encoder signal output terminals  107   a ,  107   b  are obtained by the following expressions (7), (8). 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         VAout 
                         = 
                         
                           
                             
                               R 
                               3 
                             
                             / 
                             
                               R 
                               2 
                             
                           
                           · 
                           
                             ( 
                             
                               
                                 Va 
                                 ′ 
                               
                               - 
                               Va 
                             
                             ) 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                         
                           
                             
                               R 
                               3 
                             
                             / 
                             
                               R 
                               2 
                             
                           
                           · 
                           
                             { 
                             
                               
                                 - 
                                 
                                   
                                     R 
                                     1 
                                   
                                    
                                   
                                     ( 
                                     
                                       
                                         Ia 
                                         ′ 
                                       
                                       + 
                                       Idc 
                                       - 
                                       If 
                                     
                                     ) 
                                   
                                 
                               
                               + 
                               
                                 
                                   R 
                                   1 
                                 
                                  
                                 
                                   ( 
                                   
                                     Ia 
                                     + 
                                     Idc 
                                     + 
                                     If 
                                   
                                   ) 
                                 
                               
                             
                             } 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                         
                           
                             R 
                             1 
                           
                            
                           
                             
                               
                                 R 
                                 3 
                               
                               / 
                               
                                 R 
                                 2 
                               
                             
                             · 
                             
                               ( 
                               
                                 Ia 
                                 - 
                                 
                                   Ia 
                                   ′ 
                                 
                               
                               ) 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
             
               
                 
                   
                     
                       
                         VBout 
                         = 
                         
                           
                             
                               R 
                               3 
                             
                             / 
                             
                               R 
                               2 
                             
                           
                           · 
                           
                             ( 
                             
                               
                                 Vb 
                                 ′ 
                               
                               - 
                               Vb 
                             
                             ) 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                         
                           
                             
                               R 
                               3 
                             
                             / 
                             
                               R 
                               2 
                             
                           
                           · 
                           
                             { 
                             
                               
                                 - 
                                 
                                   
                                     R 
                                     1 
                                   
                                    
                                   
                                     ( 
                                     
                                       
                                         Ib 
                                         ′ 
                                       
                                       + 
                                       Idc 
                                       - 
                                       If 
                                     
                                     ) 
                                   
                                 
                               
                               + 
                               
                                 
                                   R 
                                   1 
                                 
                                  
                                 
                                   ( 
                                   
                                     Ib 
                                     + 
                                     Idc 
                                     - 
                                     If 
                                   
                                   ) 
                                 
                               
                             
                             } 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                         
                           
                             R 
                             1 
                           
                            
                           
                             
                               
                                 R 
                                 3 
                               
                               / 
                               
                                 R 
                                 2 
                               
                             
                             · 
                             
                               ( 
                               
                                 Ib 
                                 - 
                                 
                                   Ib 
                                   ′ 
                                 
                               
                               ) 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where Ia=−Ia′, Ib=−Ib′, since Ia and Ia′, and Ib and Ib′ are the signals shifted in phase by ½ period from each other. The expressions (7), (8) thus become the following expressions (9), (10) so that encoder signals VAout and VBout having a phase difference of ¼ period are generated. 
         [0000]        VA out=2 R   1   R   3   /R   2   ·Ia    (9) 
         [0000]        VB out=2 R   1   R   3   /R   2   ·Ib    (10) 
         [0030]    Now, the output voltage signals Va, Va′, Vb, Vb′ of the IV conversion circuits  118   a ,  118   a ′,  118   b ,  118   b ′ are inputted to the DC signal detection circuit  119  so as to be operated. Since the DC signal detection circuit  119  is formed as a summing amplifier having an input resistance R 4  and feedback resistance R 4 /4, the following expression (11) where Vdc is output voltage is obtained from the expressions (3) to (6). 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         Vdc 
                         = 
                         
                           
                             
                               - 
                               
                                 ( 
                                 
                                   
                                     R 
                                     4 
                                   
                                   / 
                                   4 
                                 
                                 ) 
                               
                             
                             / 
                             
                               R 
                               4 
                             
                           
                           · 
                           
                             ( 
                             
                               Va 
                               + 
                               
                                 Va 
                                 ′ 
                               
                               + 
                               Vb 
                               + 
                               
                                 Vb 
                                 ′ 
                               
                             
                             ) 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                         
                           
                             
                               R 
                               1 
                             
                             / 
                             4 
                           
                           · 
                           
                             { 
                             
                               
                                 ( 
                                 
                                   Ia 
                                   + 
                                   
                                     Ia 
                                     ′ 
                                   
                                   + 
                                   Ib 
                                   + 
                                   
                                     Ib 
                                     ′ 
                                   
                                 
                                 ) 
                               
                               + 
                               
                                 4 
                                  
                                 
                                   ( 
                                   
                                     Idc 
                                     - 
                                     If 
                                   
                                   ) 
                                 
                               
                             
                             } 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   11 
                   ) 
                 
               
             
           
         
       
     
         [0031]    Here, of the AC components of each photo current, there is a shift in phase of ½ period from each other between  1   a  and  1   a ′, and between  1   b  and  1   b ′. Accordingly, the following expression (12) is obtained. 
         [0000]        Ia+Ia′+Ib+Ib′= 0   (12) 
       From (12), thus, (11) is expressed by the following expression (13) 
       [0032]        Vdc=R   1 ( Idc−If )   (13) 
         [0033]    As can be seen from the above expression (13), in consequence, the DC signal detection circuit  119  is to detect DC component of the signals flowing out from the photodiodes. 
         [0034]    Next, the DC voltage signal Vdc detected at the DC signal detection circuit  119  is inputted to the suppressing current generation circuit  121 . At the suppressing current generation circuit  121 , the DC voltage signal Vdc is inputted to the DC signal monitoring circuit  111  and to the gain regulating amplifier  112  of the VI conversion circuit  120  so that it is amplified by the gain regulating amplifier  112  under control of the DC signal monitoring circuit  111 . Supposing the gain as α and output voltage of the gain regulating amplifier  112  as VG, the output voltage VG of the gain regulating amplifier  112  is obtained by the following expression (14). 
         [0000]        VG=α Vdc=α R   1 ( Idc−If )   (14) 
         [0035]    The DC voltage signal multiplied by α is converted into the suppressing current If as shown in the following expression (15) by the VI conversion circuit  120 . 
         [0000]        If=VG/R   5   =α·R   1   /R   5 ·( Idc−If )   (15) 
         [0036]    Rearranging (15), the following expression (16) is obtained. 
         [0000]        If {α/( R   5   /R   1 +α)}· Idc    (16) 
         [0000]    where, especially when R1=R5 is put, the suppressing current If is represented by the following expression (17). 
         [0000]        If= α/(1+α)· Idc    (17) 
         [0037]    The suppressing current If, which is an output current of the VI conversion circuit  120 , is copied by the current mirror circuit  117 , and is supplied to the anode terminals of the photodiodes  101   a ,  101   a ′,  101   b , and  101   b ′ as an output of the suppressing current generation circuit  121 . From (3) to (6), and (17) of the above, thus, the voltage signals Va, Va′, Vb, and Vb′ outputted from the IV conversion circuits  118   a ,  118   a ′,  118   b , and  118   b ′ are respectively represented by the following expressions (18) to (21). 
         [0000]        Va=−R   1   Ia−R   1 /(1+α)· Idc    (18) 
         [0000]        Va′=−R   1   Ia′−R   1 /(1+α)· Idc    (19) 
         [0000]        Vb=−R   1   Ib−R   1 /(1+α)· Idc    (20) 
         [0000]        Vb′=−R   1   Ib′−R   1 /(1+α)· Idc    (21) 
         [0038]    Further, from (13) and (16), the DC voltage signal Vdc is obtained as in the following expression (22). 
         [0000]        Vdc=R   1 /(1+α)· Idc    (22) 
         [0039]    In the first embodiment as the above, the DC voltage signal Vdc, which is an output voltage of the DC signal detection circuit  119 , is monitored by comparing it with the reference DC voltage provided at the DC signal monitoring circuit  111 . If the DC voltage signal Vdc is greater than the reference voltage DC, i.e., the DC component of photo current is large, the gain α at the gain regulating amplifier  112  is made higher by control of the DC signal monitoring circuit  111  to increase the suppressing current If. If, on the other hand, the DC voltage signal Vdc is smaller, i.e., the DC component of photo current is small, the gain α of the gain regulating amplifier  112  is lowered to decrease the suppressing current If. In this manner, even when DC component of the photo current photoelectrically converted at the photodiode is large, distortion of the output voltage of the IV conversion circuit is avoided so that the IV conversion circuit can be operated in an optimum operation range. Accordingly, stable and accurate signal processing of optical encoder can be effected. 
       Embodiment 2  
       [0040]    A description will now be given by way of  FIG. 4  with respect to a second embodiment of the signal processing circuit for optical encoder according to the invention. The main differences from the first embodiment shown in  FIG. 3  will be described below with partially omitting a description of the common portions. First, construction of the signal processing circuit for optical encoder according to the second embodiment will be described. Referring to  FIG. 4 , what is denoted by  119  is a DC signal detection circuit identical to that of the first embodiment. An output of the DC signal detection circuit  119  is connected to an input of the DC signal monitoring circuit  111  and to an input of the VI conversion circuit  120 . A variable resistor constitutes a resistor  214  having one terminal connected to a reference potential (ground potential) and the other terminal to an inverting input terminal of the operational amplifier  113  and to a source terminal of transistor  115 , and resistance value R 5  of the variable resistor  214  is controlled by output signal of the DC signal monitoring circuit  111 . 
         [0041]    An operation of thus constructed second embodiment will now be described. Similarly to the first embodiment, the DC voltage signal Vdc detected at the DC signal detection circuit  119  is inputted to the suppressing current generation circuit  121 . At the suppressing current generation circuit  121 , the DC voltage signal Vdc is inputted to the DC signal monitoring circuit  111  and to the VI conversion circuit  120 . The DC voltage signal Vdc is then converted into the suppressing current If as in the following expression (23) by the VI conversion circuit  120  which has the variable resistor  214  where the resistance value R 5  is changed by control of the DC signal monitoring circuit  111 . 
         [0000]        If=Vdc/R   5   =R   1   /R   5 ·( Idc−If )   (23) 
         [0042]    Rearranging (23), the following expression (24) is obtained. 
         [0000]        If=R   1 /( R   5   +R   1 )· Idc    (24) 
         [0043]    The suppressing current If, which is an output current of the VI conversion circuit  120 , is copied by the current mirror circuit  117  and is supplied to the anode terminals of the photodiodes  101   a ,  101   a ′,  101   b , and  101   b ′ as output of the suppressing current generation circuit  121 . From (3) to (6), and (24) of the above, thus, the voltage signals Va, Va′, Vb, and Vb′ outputted from the IV conversion circuits  118   a ,  118   a ′,  118   b , and  118   b ′ are respectively represented by the following expressions (25) to (28). 
         [0000]        Va=−R   1   Ia−R   1   R   5 /( R   5   +R   1 )· Idc    (25) 
         [0000]        Va′=−R   1   Ia′−R   1   R   5 /( R   5   +R   1 )· Idc    (26) 
         [0000]        Vb=−R   1   Ib−R   1   R   5 /( R   5   +R   1 )· Idc    (27) 
         [0000]        Vb′=−R   1   Ib′−R   1   R   5 /( R   5   +R   1 )· Idc    (28) 
         [0044]    Further, from (13) and (24), the DC voltage signal Vdc is represented by the following expression (29). 
         [0000]        Vdc=R   1   R   5 /( R   5   +R   1 )· Idc    (29) 
         [0045]    In the second embodiment as the above, the DC voltage signal Vdc, which is an output voltage of the DC signal detection circuit  119 , is monitored by the DC signal monitoring circuit  111  similarly to the first embodiment. If the DC voltage signal Vdc is large, i.e., the DC component of photo current is large, the resistance value of the variable resistor  214  of the VI conversion circuit  120  is set to a smaller value under instruction from the DC signal monitoring circuit  111  to increase the suppressing current If. If, on the other hand, the DC voltage signal Vdc is small, i.e., the DC component of photo current is small, the resistance value of the variable resistor  214  is set to a larger value to decrease the suppressing current If. In this manner, even when DC component of the photo current photoelectrically converted at the photodiode is large, distortion of the output voltage of the IV conversion circuit is avoided so that the IV conversion circuit can be operated in an optimum operation range. Accordingly, a stable and accurate signal processing of optical encoder can be effected. 
         [0046]    As has been described by way of the above embodiments, according to the first and second aspects of the invention, DC component of photo currents is detected at the DC signal detection circuit, and, if the DC component of the photo currents is small, a suppressing current from the suppressing current generation circuit for suppressing DC component is made smaller, while the suppressing current for suppressing DC component is increased when DC component of the photo currents is large. Failure of the output voltage of the IV conversion circuit by the amount of photo currents is thereby avoided and the IV conversion circuit can be operated in an optimal operation range so that the signal processing for optical encoder can be effected in a stable manner. 
         [0047]    According to the third aspect, an output voltage of the DC signal detection circuit is monitored by the DC signal monitoring circuit, and, if the output voltage is small, i.e., DC component of the photo currents is small, the gain of the gain regulating amplifier is lowered to make the suppressing current smaller, while the gain of the gain regulating amplifier is made higher to increase the suppressing current when the DC component of the photo currents is large. Failure of the output voltage of the IV conversion circuit by the amount of photo currents is thereby avoided and the IV conversion circuit can be operated in an optimal operation range so that the signal processing for optical encoder can be effected in a stable manner. 
         [0048]    According to the fourth aspect, an output voltage of the DC signal detection circuit is monitored by the DC signal monitoring circuit, and, if the output voltage thereof is small, i.e., DC component of the photo currents is small, the resistance value of a variable resistor of VI amplifier is set to a higher level under an instruction from the DC signal monitoring circuit to make the suppressing current smaller, while the resistance value of the variable resistor is set to a lower value to increase the suppressing current when the output voltage is high, i.e., DC component of the photo currents is large. Failure of the output voltage of the IV conversion circuit by the amount of photo currents is thereby avoided and the IV conversion circuit can be operated in an optimal operation range so that the signal processing for optical encoder can be effected in a stable manner.