Abstract:
A driver with the arrangement of the travelling wave amplifier is disclosed. The driver provides n counts of cells each configuring the open collector arrangement and amplifying an input signal. The cells are arranged between an input interconnection and an output interconnection, and powered through the output interconnection. The power supply line to power the output interconnection is connected between m-th and (m+1)-th cells not through the output terminal of the output interconnection.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a driver for driving a semiconductor optical modulator. 
         [0003]    2. Related Background Art 
         [0004]    A traveling wave amplifier (hereafter denoted as “TWA”) has been well known in the field. A TWA generally provides a plurality of cells each connected in parallel between the input interconnection and the output interconnection and amplifying an input signal coming therein with an input delay time specific to the cell and output an amplified signal to the output terminal with an output delay time also specific to the cell. But the sum of the input delay time and the output delay time is common to respective cells; accordingly, the output signal may be kept in the waveform thereof. The cells are powered through the output interconnection. 
         [0005]    When an TWA is utilized in an optical communication, in particular, when an TWA drives an optical modulator types of an electro-absorption (hereafter denoted as “EA”) modulator or a Mach-Zehnder (hereafter denoted as “MZ”) modulator, a substantial amplitude of the output signal is required, which increases a driving current flowing in the driver. A TWA generally requires delay lines. When the driving current with the substantial amplitude flows in the delay lines, the delay lines are inevitable to be widened in dimensions thereof, which enlarges a size of the TWA. 
       SUMMARY OF THE INVENTION 
       [0006]    One aspect of the present application relates to a driver to modulate continuous light coming from an optical source. The driver includes an input interconnection to propagate an input signal, an output interconnection to propagate amplified signals, first to N-th cells each connected between the input interconnection and the output interconnection, and a power line to supply electrical power to the cells through the output interconnection. 
         [0007]    The input interconnection provides first to N-th input delay lines connected in series and each of the input delay lines has a delay time substantially equal to each other. The output interconnection also provides first to N-th output delay lines connected in series and each of the output delay lines has a delay time substantially equal to each other and equal to the delay time of the input delay line. The n-th cell, where n is an integer between 1 and N, is connected between the n-th input delay line and the n-th output delay line. A feature of the driver of an embodiment is that the power line is connected between the m-th output delay line and (m+1)-th output delay line, where m is an integer between 2 to N−2. 
         [0008]    Another aspect of the present application relates to a transmitting module that includes an optical source, an optical modulator, and a driver. The optical source that includes a semiconductor laser diode (hereafter denoted as “LD”) emits continuous light. The optical modulator modulates the continuous light by receiving a driving signal from the driver. The driver, which is configured with the TWA, includes an input interconnection, an output interconnection, first to N-th cells, and a power line. The input interconnection provides first to N-th input delay lines. The output interconnection provides first to N-th output delay lines. The n-th cell is connected between the n-th input delay line to receive an input signal and the n-th output delay line to output an amplified signal, where n is an integer between 1 and N. A feature of the transmitting module is that the power line is connected between the m-th output delay line and (m+1)-th output delay line, where m is an integer between 2 to N−2, to supply electrical power to the cells through the output interconnection. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    The foregoing and other purposes, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which: 
           [0010]      FIG. 1  is a functional block diagram of a optical transmitting module installing a driver according to an embodiment of the invention; 
           [0011]      FIG. 2  shows a circuit diagram of a driver according to an embodiment of the invention; 
           [0012]      FIG. 3  shows a circuit diagram of a cell implemented within the driver shown in  FIG. 2 ; 
           [0013]      FIG. 4  shows an equivalent circuit diagram of the cell viewed from the output interconnections; 
           [0014]      FIG. 5A  is a plan view of the cell and two delay elements shown in  FIG. 4 ; and,  FIG. 5B  shows a cross section taken along the line I-I appeared in  FIG. 5A ; 
           [0015]      FIG. 6  shows an equivalent circuit of the output interconnections,  13   a  and  13   b , each configured with a co-planar line; 
           [0016]      FIG. 7  is a circuit diagram of a driver according to a comparable embodiment of the invention; 
           [0017]      FIG. 8  shows a relation of the output DC current flowing into the driver against the output amplitude; 
           [0018]      FIG. 9A  shows a behavior of the transmission impedance of the delay line with respect to the width thereof; and  FIG. 9B  shows a length of the delay line to have the preset transmission impedance against the width thereof; 
           [0019]      FIG. 10  shows a circuit diagram of a driver modified from the driver shown in  FIG. 2 ; 
           [0020]      FIG. 11A  is a magnified plan view of the power line with a spiral inductor and the output interconnection connected to the power line; and  FIG. 11B  shows an equivalent circuit diagram of the layout shown in  FIG. 11A ; 
           [0021]      FIG. 12A  is a magnified plan view of the power line without a spiral inductor and the output interconnection connected to the power line; and  FIG. 12B  shows an equivalent circuit diagram of the layout shown in  FIG. 12A ; 
           [0022]      FIG. 13  shows an equivalent circuit diagram of the output interconnection combined with the equivalent circuit diagram of the power line with the spiral inductor shown in  FIG. 11B ; 
           [0023]      FIG. 14  shows an equivalent circuit diagram of the output interconnection combined with the power line without the spiral inductor; 
           [0024]      FIG. 15  shows a circuit diagram of a driver further modified from the driver shown in  FIG. 10 ; and 
           [0025]      FIG. 16  shows an equivalent circuit diagram of the output interconnection shown in  FIG. 15  combined with the power line without the spiral inductor. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0026]    Next, some preferred embodiments according to the present invention will be described as referring to drawings. In the description of the drawings, numerals or symbols same with or similar to each other will refer to the elements same with or similar to each other without overlapping explanations. 
         [0027]      FIG. 1  is a functional block diagram of an optical transmitting module implemented with a driver according to one embodiment of the present invention. The optical transmitting module  1 A shown in  FIG. 1  includes an optical source  3 , an optical modulator  5 , and a driver  10 . The optical source  3 , which may be a semiconductor-light-emitting device, typically, a semiconductor laser diode (hereafter denoted as “LD”), that emits light L 1  with a preset wavelength. The optical modulator  5 , which is optically coupled with the optical source  3 , modulates the continuous wave light L 1  to generate modulated light L 2 . The optical modulator  5  may be a type of EA or MZ. The modulated light L 2  includes signals of high frequency components exceeding 10 GHz, typically reaching 25 Gbps or 40 Gbps. The modulated light L 2  is guided to an external from the optical transmitting module  1 A. 
         [0028]    The driver  10 , which drives the optical modulator  5 , amplifies signals, S IN  and /S IN , provided in input terminals to output a driving signal S d  to the optical modulator  5 . The symbol slash “/” means that signal denoted by the symbol has a phase opposite to a signal denoted by a symbol without the slash. The optical modulator  5  modulates the continuous light L 1  by the driving signal S d . The driver  10  of the present embodiment has the arrangement of, what is called, the differential arrangement that processes two signals S IN  and /S IN  complementary to each other; however, the signal S IN  and the driving signal S d  may be a single phase signal. 
         [0029]      FIG. 2  shows a circuit diagram of the driver  10 . The driver  10 , which may have the configuration of the TWA includes a pair of input interconnections,  12   a  and  12   b , a pair of output interconnections,  13   a  and  13   b , a plurality of cells, A 1  to A N , where N is an integer greater than unity, where the driver  10  shown in  FIG. 2  has four (4) cells, input delay lines, DI 1  to DI N , output delay lines, DO 1  to DO N , and a pair of power lines,  14   a  and  14   b . These circuit elements described above are integrated on a semiconductor substrate, such as InP substrate. 
         [0030]    The input interconnections,  12   a  and  12   b , each transmits signals, S IN  and /S IN , and extends along one direction on the substrate. The input interconnections,  12   a  and  12   b , each has an input terminal,  12   c  and  12   d , in one end thereof. As illustrated in  FIG. 2 , the driver  10  may further provide a pre-amplifier  15  to amplify the signals, S IN  and /S IN , in the end of the input interconnections,  12   a  and  12   b . The input interconnections,  12   a  and  12   b , are connected to the ground GND through resistors,  16   a  and  16   b , in the other end thereof. 
         [0031]    The output interconnections,  13   a  and  13   b , each carries the amplified signals, S OUT  and /S OUT , and extends substantially in parallel to the input interconnections,  12   a  and  12   b , on the substrate. The output interconnections,  13   a  and  13   b , each provides the output terminal,  13   c  and  13   d , to output the amplified signals, S OUT  and /S OUT , in the end thereof. The output terminal  13   c  is connected with one electrode of the optical modulator  5  through a coupling capacitor  18   a , where the amplified signal S OUT  output from the output terminal  13   c  is provided to the optical modulator  5  as the driving signal S d . The other output terminal  13   d  provides the other amplified signal /S OUT  to the ground through another coupling capacitor  18   b  and a resistor  19 . The output interconnections,  13   a  and  13   b , in the other end thereof, are grounded through respective resistors,  17   a  and  17   b , and a capacitor  20  as illustrated in  FIG. 2 . 
         [0032]    Each of cells, A 1  to A N , amplifies the input signals, S IN  and /S IN , to generate the amplified signals, S OUT  and /S OUT . The cells, A 1  to A N , according to the present embodiment have the configuration of, what is called, the differential circuit, and are connected in parallel between the input interconnections,  12   a  and  12   b , and the output interconnections,  13   a  and  13   b . Specifically, each of cells, A 1  to A N , provides a pair of inputs connected to the input interconnections,  12   a  and  12   b , and a pair of outputs connected to the output interconnections,  13   a  and  13   b.    
         [0033]    The input delay lines, DI 1  to DI N , have the configuration of the transmission line having a specific delay time equal to each other. That is, one of the input interconnections  12   a  provides the input delay lines, DI 1  to DI N , in series from the input end in this order; while, the other input interconnection  12   b  also provides the input delay lines, DI 1  to DI N , in series from the input end in this order. 
         [0034]    Each of the input delay lines, DI n  (n=1 to N), includes two delay elements, Da and Db, connected in series each having a delay time substantially equal to each other; and a sum the delay times is the delay time of respective input delay lines DI n  (n=1 to N). Specifically, each of delay lines DI n  is coupled with an input of the cell A n  such that a node between the delay elements, Da and Db, is connected to the input of the cell A n . Accordingly, the first cell A 1  receives the signal output from the pre-amplifier  15  through the delay element Db, the second cell A 2  receives the signal through delay element Db twice and another delay element Da, the third cell A 3  receives the signal through the delay element Db three times and another delay element Da twice, and the fourth cell A 4  receives the signal through the delay element Db four times and another delay element Da three times. That is, a delay element Da in the m-th input delay line DI m  and another delay element Db in the (m+1)-th input delay line DI m+1  are put between the inputs of the cells, A m  and A m+1 . In other words, the (m+1)-th cell A m+1  receives the signals, S IN  and /S IN , output from the pre-amplifier  15  delayed by the delay elements, Da and Db, compared with the upstream cell A m . 
         [0035]    The output delay lines, DO 1  to DO N , have an arrangement similar to the input delay lines, DI 1  to DI N , described above. That is, the output delay lines, DO 1  to DO N , have delay times same to each other, and formed in respective output interconnections,  13   a  and  13   b . The delay time of the output delay lines, DO 1  to DO N , is substantially equal to that of the input delay lines, DI 1  to DI N . 
         [0036]    In the present embodiment, each of the output delay lines DO n  (n=1 to N) includes first and second elements, Da and Db, respectively. Two delay elements, Da and Db, have a delay time substantially same to each other; and a sum of the delay times is the delay time of respective output delay lines, DO 1  to DO N . The fourth cell A 4  output the amplified signals to the output terminals,  13   c  and  13   d , through the delay element Da in the fourth output delay lines DO 4 , the third cell A 3  outputs the amplified signals to the output terminals,  13   c  and  13   d , through the delay element Da twice and another delay element Db. The second cell A 2  outputs the amplified signals to the output terminals,  13   c  and  13   d , through the delay element Da three times and another delay element Db twice. The first cell A 1  outputs the amplified signal to the output terminals,  13   c  and  13   d , through the delay element Da four times and another delay element Db three times. That is, one delay element Da and one delay element Db are put between the outputs of the cells, A m  and A m+i , neighbor to each other. 
         [0037]    Further specifically, the signals, S IN  and /S IN , output from the pre-amplifier  15  and output from the output terminals,  13   c  and  13   d , after being amplified by the first cell A 1  are influenced by the delay element Da four times and another delay element Db four times; those amplified by the second cell A 2  are influenced by the delay element Da four times and another delay element Db four times; and those amplified by the third cell A 3  and those amplified by the fourth cell A 4  are influenced by the delay element Da four times and another delay element Db four times. Thus, assuming the cells, A 1  to A 4 , show a propagation delay time same to each other, the amplified signals, S OUT  and /S OUT , appeared in the output terminals,  13   c  and  13   d , are adequately recovered in the signal shape thereof even the paths are different from others. 
         [0038]    The power lines,  14   a  and  14   b , supply electrical power to respective cells, A 1  to A 4 , through the output interconnections,  13   a  and  13   b . The power lines,  14   a  and  14   b , couples with the output interconnections,  13   a  and  13   b , between the m-th output delay line DO m  and (m+1)-th output delay line DO m+1 . When the number of the cell A m  is even as the present embodiment shown in  FIG. 4 , where m is equal to 4, the power lines,  14   a  and  14   b , are preferably to be connected just in the midpoint of the cells, that is, between the second cell A 2  and the third cell A 3 . In a case where the driver provides the odd number of cells A m , the power lines,  14   a  and  14   b , are preferable connected to the output interconnections,  13   a  and  13   b , around a midpoint of the cells, A 1  to A N . For instance, the driver  10  includes five (5) cells, the power lines,  14   a  and  14   b , are preferably connected to a point between the second and third cells, A 2  and A 3 , or between the third and fourth cells, A 3  and A 4 . 
         [0039]    That is, assuming the driver  10  provides the N count of the cells, the power lines are preferably connected to the output interconnections,  13   a  and  13   b , between the (N/2)-th cell and the (N/2+1)-th cell. In particular, the driver  10  provides an odd number N of the cells, the power lines,  14   a  and  14   b , are preferably connected to the upstream or the downstream of the (INT(N/2)+1)-th cell, namely, between INT(N/2)-th and (INT(N/2)+1)-th cells, or between (INT(N/2)+1)-th and (INT(N/2)+2)-the cells, where “INT(N/2)” means that a maximum integer closest to a real number of N/2. Inductors,  21   a  and  21   b , are preferably provided in the power lines,  14   a  and  14   b , not to influence the transmission impedance of the output interconnections,  13   a  and  13   b , and/or the delay time of the output delay lines, connected to the power lines,  14   a  and  14   b.    
         [0040]      FIG. 3  shows an example of a circuit diagram of the cell A n .  FIG. 3  also shows the output delay lines DO n  including two delay elements, Da and Db. As shown in  FIG. 3 , the cell A n  includes a differential circuit of two transistors,  31   a  and  31   b , two cascade transistors,  32   a  and  32   b , and two emitter follower transistors,  33   a  and  33   b . The transistors,  33   a  and  33   b , as described above, constitute the emitter follower accompanied with the current sources,  34   a  and  34   b , namely, the collector grounded configuration, whose bases receive the signals, S IN  and /S IN , delayed by accumulative input delay lines. 
         [0041]    The transistors,  31   a  and  31   b , constitute the differential circuit accompanied with the current source  35  commonly connected to the emitter of the transistors,  31   a  and  31   b . The cascade transistors,  32   a  and  32   b , whose bases are biased by a constant voltage generated by dividing the power supply Vcc by two resistors,  36   a  and  36   b , which constitutes the base grounded configuration. That is, the emitters are connected to the collector of the differential circuit,  31   a  and  31   b , while, the collector thereof are connected to the output delay lines,  13   a  and  13   b , as an open collector configuration. 
         [0042]    The transmission impedance of the output interconnections,  13   a  and  13   b , may be determined by the delay elements, Da and Db, and the output capacitance of the cell A n , which is primarily given by the collector-base capacitance of the cascade transistors,  32   a  and  32   b .  FIG. 4  shows an equivalent circuit of the output interconnections,  13   a  and  13   b , and the cell A n . When the transistors in the cell A n  are integrally formed on a semiconductor substrate, the collector-base capacitance of such transistor inherently shows, for instance, about 20 fF. 
         [0043]    As shown in  FIGS. 5A and 5B , the output interconnections, DO 1  to DO N , preferably have an arrangement of, what is called, the micro-strip line, or the co-planar line with the ground pattern  52 , formed on the substrate  50 . In the case of the co-planar line with the ground pattern, the substrate  50  in the top surface  50   a  thereof provides an interconnection  13   a , or  13   b  with a preset width W, while the back surface  50   b  thereof provides a metal film  51  connected to a reference voltage, typically the ground. The top surface  50   a  further provides, in both sides of the interconnection  13   a , or  13   b , metal films  52  operating as the ground with a preset span against the interconnection  13   a , or  13   b .  FIG. 6  shows an equivalent circuit of the output interconnections,  13   a  and  13   b , each configured with a co-planar line. 
         [0044]    The transmission impedance Z of the output interconnections,  13   a  and  13   b , with the arrangement shown in  FIGS. 5A and 5B , is given by: 
         [0000]        Z ={( C   COP   +C   bc )/ L   COP } 1/2 ,  (1)
 
         [0000]    where C COP  is capacitance of the co-planar line, and L COP  is inductance of the co-planar line. The impedance Z depends on the base-collector capacitance C bc ; accordingly, in order to design the transmission impedance of the output interconnections,  13   a  and  13   b , accompanied with the cells A n , it is necessary to design the bare impedance of the output interconnections,  13   a  and  13   b , without any cells A n  to be greater than 50 and secure the inductance L COP  so as to close the transmission impedance to be equal to 50Ω. Generally, because the line inductance of an interconnection depends on the length and width of the interconnection, a substantial length of the transmission line is necessary to set the transmission impedance thereof to be equal to the preset range. 
         [0045]      FIG. 7  is a circuit diagram of a driver  100  according to a comparable embodiment of the invention. The driver  100  has an arrangement substantially same with those of the embodiment  10  shown in  FIG. 2  except for the power lines,  104   a  and  104   b , instead of the power lines,  14   a  and  14   b . That is, the power lines,  104   a  and  104   b , of the comparable embodiment shown in  FIG. 7  supply power to the output interconnections,  13   a  and  13   b , from the output terminals,  13   c  and  13   d . The inductors,  106   a  and  106   b , connected to the power supply are also provided in the power lines,  104   a  and  104   b.    
         [0046]    In the driver with the TWA arrangement, when the duty ratio of the output signal is 50%, the output amplitude V OUT  and the output DC current Ioutdc have a relation of: 
         [0000]        I outdc= V   OUT /( Z   OUT   //Z   L ),  (2)
 
         [0000]    where Z OUT  and Z L  are the output impedance of the driver and the impedance of the optical modulator, respectively. In equation (2), the symbol “//” means combined impedance of two elements putting this symbol therebetween that are connected in parallel to the others. 
         [0047]      FIG. 8  shows the relation denoted by equation (2), that is, the horizontal axis of  FIG. 8  corresponds to the output amplitude V OUT , the vertical axis corresponds to the output DC current Ioutdc, and the slope of the behavior is given by 1/(Z OUT /Z L ). The output amplitude V OUT  of about 2 to 3.5 V is generally required for the modulator with a type of the EA, while, a larger amplitude of about 3.5 to 9 V is required for an MZ modulator. For such amplitudes, the output DC current Ioutdc of 40 to 180 mA is necessary. 
         [0048]    In the driver  100  shown in  FIG. 7 , which has the power lines,  104   a  and  104   b , connected in the output terminals,  13   c  and  13   d , the output DC current Ioutdc supplied from the output terminals,  13   c  and  13   d , flow in the delay element Da. A portion of the DC current is divided into the cell A 4 , and a rest of the current flows into the next delay element Db. Iterating the division of the current into the cell A i  and the rest of the current flowing into the next delay element Db, the current finally flows into the cell A 1 . Accordingly, the output interconnections,  13   a  and  13   b , or the delay elements, Da and Db, in the output delay lines DO 4  closest to the output terminals,  13   c  and  13   d , are necessary to be formed wider to lower the series resistance thereof. However, widened patterns of the delay elements, Da and Db, are necessary to be formed longer to have the predetermined transmission impedance as described in  FIG. 6 . The driver  100  shown in  FIG. 7  or that  10  shown in  FIG. 2 , when they are integrally formed on a semiconductor substrate, generally has a feature that the interconnections and delay lines occupy a dominant area to have the predetermined impedance and the predetermined delay time. Under such a condition, the widened delay elements, Da and Db, close to the output terminals,  13   c  and  13   d , immediately brings a larger sized integrated circuit. 
         [0049]    The driver  10  shown in  FIG. 2  according to an embodiment of the invention, the power lines,  14   a  and  14   b , are extracted between the m-th cell A m  and the (m+1)-th cell A m+1 , where m is an integer greater than 1 but less than N−1, not the output terminals,  13   c  and  13   d . Accordingly, the driver  10  of the embodiment reduces the current flowing in the output terminals,  13   c  and  13   d , by at least (N−1)/N of the current Idcout. When the number of the cells is even, like the present embodiment where n is equal to four (4), the power lines,  14   a  to  14   b , are preferably connected between the second and third cells, A 2  and A 3 , then the current flowing in the output terminals,  13   c  and  13   d , is reduced to a half of the current when the power lines are connected to the output terminals,  13   c  and  13   d.    
         [0050]      FIG. 9A  shows a behavior of the transmission impedance of the output delay lines, DO 1  to DO N , with respect to the width thereof ignoring the base-collector capacitance Cbc inherently attributed to the output transistors,  32   a  and  32   b , of the cell A n . The horizontal scale is micron-meter (μm), while, that of the vertical axis is ohm (Ω). Moreover,  FIG. 9A  assumes that the substrate is made of InP with a thickness of 100 μm, output delay lines DO 1  to DO N , has a thickness of 3 μm and a gap to the ground patterns in both sides thereof is 40 μm. As shown in  FIG. 9A , the impedance thereof lowers as the width of the delay lines becomes wider. 
         [0051]    On the other hand,  FIG. 9B  shows a length of the delay lines, DO 1  to DO N , against the width thereof in order to have the transmission impedance of 50Ω. Horizontal axis shows the width of the delay lines, while, the vertical axis shows the length necessary to have the impedance of 50Ω.  FIG. 9B  takes into account the base-collector capacitance Cbc of the output transistors,  32   a  and  32   b , of the cell A n , which is assumed to be 20 fF. As shown in  FIG. 9B , the widened delay line requests a lengthened pattern to have the predetermined transmission impedance. 
         [0052]    A width of a transmission line is designed so as to have enough tolerance for the current flowing therein, namely, designed to have enhanced reliability against a magnitude of a current flowing therein. Reduced DC current like the embodiment of the present invention makes it possible to narrower the width of the delay line. Moreover, a narrowed transmission line makes it possible to shorten the transmission line to have the predetermined transmission impedance, which resultantly makes the circuit size smaller. In an example, narrowing the width from 20 μm to 10 μm, namely, a half of the original width, the length of the transmission line is able to be reduced from 240 μm to 140 μm, namely, about 40% downsizing. 
         [0053]    (First Modification) 
         [0054]      FIG. 10  shows a circuit diagram of a driver  10 A according to a modification of the aforementioned driver  10 . The driver  10 A has an arrangement substantially same with those of the aforementioned driver  10  shown in  FIG. 2  except for features described below. 
         [0055]    That is, the driver  10 A provides power lines,  14   a  and  14   b , accompanied with additional inductors,  23   a  and  23   b , connected in series to the inductors,  21   a  and  21   b . The former inductors,  23   a  and  23   b , are preferably a type of the spiral inductor with inductance of about 1 nH. The additional inductors,  23   a  and  23   b , are formed on the substrate made of, for instance, InP on which the other elements of the cells A i , the pre-amplifier  15  and delay elements, Da and Db, are integrally formed. 
         [0056]      FIG. 11A  is a plan view of a portion where the power line,  14   a  or  14   b , is coupled with the output interconnection  13   a  or  13   b , while,  FIG. 11B  shows an equivalent circuit of the power line  14   a  and the output interconnection  13   a .  FIG. 11A  includes, in addition to the spiral inductor  23   a  and the output interconnection  13   a , a bonding pad  36  to supply the electrical power on the output interconnection  13   a  and metal patterns  52  formed along the output interconnection  13   a  in both sides thereof. 
         [0057]    The equivalent circuit includes, in addition to the spiral inductor  23   a , parasitic capacitors, C 1  to C 3 . The capacitor C 1  is a stray capacitance attributed to a line put from the output interconnection  13   a  to the bonding pad  36 , the capacitor C 2  is a stray capacitance attributed to an aerial capacitor formed above the spiral inductor  23   a  and between the output interconnection  13   a  to the pad  36 . The capacitor C 3  is attributed to the pad  36  itself against the ground, or the back surface of the InP substrate. 
         [0058]      FIG. 12A  also shows a plan view of the portion of the power line  14   a  without any additional inductors, and  FIG. 12B  is an equivalent circuit of the layout shown in  FIG. 12A . The equivalent circuit of  FIG. 12B  includes parasitic capacitors, C 1  and C 3 .  FIG. 13  combines the equivalent circuit shown in  FIG. 11B  and those for the output delay lines, DO m  and DO m+1 , connected to the power line  14   a . External inductors,  21   a  and  21   b , where that latter is omitted in  FIG. 13 , and the spiral inductor  23   a  generally have large inductance to be regarded as an open-circuited in high frequencies compared with inductors attributed to the delay lines, DO m  and DO m+1 .  FIG. 14  is an equivalent circuit of the power line  14   a  and the output delay lines, DO m  and DO m+1 , to regard the external inductors,  23   a  and  21   a , in the open-circuited. The capacitor shown in  FIG. 14  has capacitance of 
         [0000]        C   4 =( C   1   +C   2   //C   3 ), and 
         [0000]        C   2   //C   3 =( C   2   ×C   3 )/( C   2   +C   3 ). 
         [0000]    That is, the power lines,  14   a  and  14   b , are grounded in high frequencies through a capacitor C 4  whose capacitance is given by the equation above. When the spiral inductor  23   a  is removed from the power line  14   a , the capacitor C 4  has not the capacitance of the capacitor C 2 , where C 4  becomes equal to C 1 +C 3 . 
         [0059]    In the layout shown in  FIG. 11A , because the capacitance of the capacitor C 3  attributed to the pad  36  becomes far greater than the capacitance C 2  for the overlay capacitor, namely, C 3 &gt;C 2 ; a condition of (C 1 +C 3 )&gt;(C 1 +C 2 //C 3 ) is satisfied. Then, the power lines,  14   a  and  14   b , shown in  FIG. 10  with additional inductors,  23   a  and  23   b , have smaller capacitance compared with the power line  14   a  shown in  FIG. 2  without any spiral inductors,  23   a  and  23   b . Thus, the power lines,  14   a  and  14   b , according to the modified embodiment shown in  FIG. 10  give less influence, such as a variation of the transmission impedance of the output interconnections,  13   a  and  13   b , and a fluctuation of the delay time of the delay lines, DO m  and DO m+1  compared with the arrangement without any additional inductors. 
         [0060]    (Second Modification) 
         [0061]      FIG. 15  shows a circuit diagram of a driver  10 B further modified from the aforementioned driver  10 A shown in  FIG. 10 . The driver  10 B provides arrangements substantially same with those of the driver  10 A except for points described below. 
         [0062]    That is, the driver  10 B further includes additional delay lines D OP  in the output interconnections,  13   a  and  13   b , to which the power lines,  14   a  and  14   b , are connected. The additional delay line D OP  has an arrangement similar to the output delay lines, DO 1  to DO N ; that is, the delay line D OP  includes two delay elements, Dc and Dd, each being attributed to a delay time substantially same to each other. A sum of delay times for the delay elements, Dc and Dd, becomes a delay time of the additional delay line D OP . The power lines,  14   a  and  14   b , are connected to a node between two delay elements, Dc and Dd. 
         [0063]      FIG. 16  shows an equivalent circuit of the power lines,  14   a  and  14   b , and the output interconnection,  13   a  and  13   b , in a portion connected to the power lines,  14   a  and  14   b . Comparing the equivalent circuit shown in  FIG. 16  with that shown in  FIG. 14 , two delay elements, Dc and Dd, with the type of the co-planar line, are put between the power lines,  14   a  and  14   b , inherently with the parasitic capacitor with the capacitance of C 4 =(C 1 +C 2 //C 3 ) and the output delay lines, DO 2  and DO 3 . Then, a new transmission line constituted by the additional delay elements, Dc and Dd, and the parasitic capacitance C 4  is formed so as to have the predetermined impedance. Thus, the influence of the power lines,  14   a  and  14   b , to the output interconnections,  13   a  and  13   b , such as variations of the characteristic impedance of the output interconnections,  13   a  and  13   b , and that of the delay times of the output delay lines, DO 2  and DO 3 , is effectively suppressed compared with those of the aforementioned shown in  FIG. 10 . 
         [0064]    The modified driver  10 B shown in  FIG. 15  provides still further delay element De between the input delay lines, DI 2  and DI 3 , in the input interconnections,  12   a  and  12   b . The delay element De is a type of the transmission line having predetermined transmission impedance of, for instance, 50Ω and a delay time substantially equal to the delay time of the delay lines D OP  in the output interconnections,  13   a  and  13   b . The delay element De in the input interconnections,  12   a  and  12   b , adjust the phases of the signal amplified by the cells provided in the downstream of this delay element De so as to match the phase of signals amplified by respective cells, A 1  to A N , at the output terminals,  13   c  and  13   d.    
         [0065]    Although the driver  10 B shown in  FIG. 15  provides additional inductors,  23   a  and  23   b , in the power lines,  14   a  and  14   b ; the driver  10 B may omit these additional inductors,  23   a  and  23   b . The parasitic capacitor C 4  shown in  FIG. 16  typically has capacitance of about 30 fF. In such a case, a length of the additional delay elements, Dc and Dd, putting the capacitor C 4  therebetween becomes about 300 μm to have the transmission impedance of 50Ω. On the other hand, a total length of the output interconnections,  13   a  and  13   b , reaches a few milli-meters to realize a substantial delay time between the cells. Accordingly, the additional delay elements, Dc to De, may be substantially ignorable in a viewpoint of the length of the interconnections. 
         [0066]    In the foregoing detailed description, the driver for an optical modulator of the present invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present invention. For instance, the driver of the embodiments may directly driver a semiconductor laser diode. Moreover, the driver may be used as an amplifier with the TWA not restricted to applications to drive optical devices. The present specification and figures are accordingly to be regarded as illustrative rather than restrictive.