Abstract:
Compact electronic modules, which may be used with implantable microstimulators and other medical and non-medical devices, and manufacture/assembly of such modules are described. Component and circuitry designs utilize unique redistribution techniques and attachment methods. A number of component designs and packaging configurations maximize the volume efficiency of electronic modules. Also included are improved processes and systems enabling the manufacture and assembly of such compact packages.

Description:
[0001]     The present application is a divisional of U.S. patent application Ser. No. 10/609,452, filed Jun. 27, 2003 and now allowed, which claims the benefit of U.S. Provisional Patent Application Ser. No. 60/392,475, filed Jun. 28, 2002. These applications are incorporated herein by reference in their entireties. 
     
    
     FIELD OF THE INVENTION  
       [0002]     The present invention generally relates to compact electronic modules and more particularly to component and circuitry designs utilizing redistribution techniques; attachment methods, and other packaging that maximizes the volume efficiency of electronic modules, and further relates to improved processes and systems enabling the manufacture and assembly of such compact packages.  
       BACKGROUND OF THE INVENTION  
       [0003]     Many devices can benefit from optimization of space required for electronic modules, which may allow miniaturization of the device itself and/or introduction or enlargement of other device components. Compact electronic modules are particularly useful for devices requiring volume efficiency, including medical devices and consumer electronics devices. For instance, optimization of the packaging of an electronic module in a transistor radio would allow the entire radio to be more compact. Alternatively or additionally, the freed-up space could be used by other components, such as a larger battery. As another example, the size of implantable medical devices is preferably minimized to reduce trauma, cosmetic, and other effects of a device located in the body. Optimization of the packaging of an electronic module in an implantable medical device would allow the device to be smaller and/or allow the device to accommodate additional and/or larger components.  
         [0004]     For example, implantable microstimulators known as Bion® devices are characterized by a small, cylindrical housing which contains electronic circuitry that produces electric currents between spaced electrodes. These microstimulators are implanted proximate to target tissue, and the currents produced by the electrodes stimulate the tissue to reduce symptoms or otherwise provide therapy for various disorders. A compact electronic module would allow a Bion device to be smaller and thus easier to implant and less noticeable and/or allow the device to accommodate additional and/or larger components, such as a larger rechargeable battery that would lengthen time between recharges.  
         [0005]     Radio-frequency powered and battery powered microstimulators are described in the art. See, for instance, U.S. Pat. No. 5,193,539 (“Implantable Microstimulator); U.S. Pat. No. 5,193,540 (“Structure and Method of Manufacture of an Implantable Microstimulator”); U.S. Pat. No. 5,312,439 (“Implantable Device Having an Electrolytic Storage Electrode”); U.S. Pat. No. 6,185,452 (“Battery-Powered Patient Implantable Device”); U.S. Pat. No. 6,164,284 and U.S. Pat. No. 6,208,894 (both titled “System of Implantable Device for Monitoring and/or Affecting Body Parameters”). The &#39;539, &#39;540, &#39;439, &#39;452, &#39;284, and &#39;894 patents are incorporated herein by reference in their entirety.  
         [0006]     Microstimulators to prevent and/or treat various disorders are taught, e.g., in U.S. Pat. No. 6,061,596 (“Method for Conditioning Pelvis Musculature Using an Implanted Microstimulator”); U.S. Pat. No. 6,051,017 (“Implantable Microstimulator and Systems Employing the Same”); U.S. Pat. No. 6,175,764 (“Implantable Microstimulator System for Producing Repeatable Patterns of Electrical Stimulation”); U.S. Pat. No. 6,181,965 (“Implantable Microstimulator System for Prevention of Disorders”); U.S. Pat. No. 6,185,455 (“Methods of Reducing the Incidence of Medical Complications Using Implantable Microstimulators”); and U.S. Pat. No. 6,214,032 (“System for Implanting a Microstimulator”). The techniques described in these additional patents, including power charging techniques, may also be used with the present inventions. The &#39;596, &#39;017, &#39;764, &#39;965, &#39;455, and &#39;032 patents are incorporated herein by reference in their entirety.  
         [0007]     A number of the above cited patents describe microstimulator designs and methods for manufacturing a microstimulator or portions of a microstimulator. Disclosed herein are improved designs and techniques for producing compact electronic modules for a microstimulator or other medical or non-medical device. In addition, the designs and methods disclosed allow such devices, to be manufactured more efficiently, more reliably, and/or more cost effectively.  
       BRIEF SUMMARY OF THE INVENTION  
       [0008]     The present inventions address the above and other needs by providing, inter alia, improved methods for creating compact electronic modules. For instance, a present invention provides component and circuitry designs utilizing a redistribution technique that differ from standard redistribution processes, results, and uses. The technique creates a redistribution surface on the bare integrated circuit (IC) that allows secondary components to be mounted above the IC and connected electrically to the IC through the redistribution surface. The redistribution surface includes mounting pads and other interconnection pads, some along the edge of the redistribution surface to allow simplified connection to a substrate. A further improvement provides electronic shielding within the redistribution surface.  
         [0009]     The mounting pads may be positioned via the redistribution surface to one side of the IC, while a portion of the IC and the substrate on which it is mounted are positioned between two halves of a ferrite core. The length and diameter of the ferrite core are thus maximized, while providing the IC and substrate space between the ferrite halves, as well as beyond the ferrite core.  
         [0010]     The halves of the ferrite core may further create a dumbbell shape, allowing the wire of the coil to be wound on the center, smaller-diameter portion of the core. The core shape facilitates winding, centering, and protecting the coil, while maximizing the volume of core material and diameter at the ends of the ferrite core. The dumbbell shape further facilitates the creation of a cylindrical device, which is uniquely suited to some uses, such as implantation into a body through a cannula, while also providing the above-stated results.  
         [0011]     Methods and means for manufacturing/assembling components into compact electronic modules is described herein. A carrier facilitates manufacturing, assembly, and testing of a small electronic device, and in particular, a small cylindrical device, which includes the compact electronic modules of the invention. For instance, the carrier ensures the coaxial assembly of various components of a cylindrical package. In addition, the carrier protects and eases handling of the device.  
         [0012]     Embodiments of the various inventions described herein may include some or all of the items mentioned above. Additional embodiments will be evident upon further review of the present disclosure. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]     The above and other aspects of the present inventions will be more apparent from the following more particular description thereof, presented in conjunction with the following drawings wherein:  
         [0014]      FIG. 1A  is a top view of a battery-powered Bion® device used to describe the inventions, showing exemplary dimensions for some components of the device;  
         [0015]      FIG. 1B  is a cross-sectional view taken along line  1 B- 1 B of  FIG. 1A ;  
         [0016]      FIG. 2A  is an exploded view of the main internal components of the device;  
         [0017]      FIG. 2B  is a circuit diagram of the interactions of the main components of  FIG. 2A ;  
         [0018]      FIG. 3  is a perspective top view of a substrate panel assembly;  
         [0019]      FIG. 4A  is a perspective top view of a substrate panel;  
         [0020]      FIG. 4B  is a perspective bottom view of the substrate panel of  FIG. 4A ;  
         [0021]      FIG. 5  is a perspective top view of portions of the panel shown in  FIG. 3  with an integrated circuit chip attached;  
         [0022]      FIG. 6A  is an exploded view of one embodiment of layers formed while making a unique redistributed surface on an integrated circuit;  
         [0023]      FIG. 6B  is a side view of an embodiment of a redistributed surface on an integrated circuit;  
         [0024]      FIG. 7A  is a perspective top view of the panel assembly shown in  FIG. 5  with capacitors and diodes attached;  
         [0025]      FIG. 7B  is an enlarged detail view of some of the components shown in  FIG. 7A ;  
         [0026]      FIG. 8A  is a perspective top view of the panel assembly shown in  FIG. 7A  with the top ferrite half attached;  
         [0027]      FIG. 8B  is an enlarged detail view of some of the components shown in  FIG. 8A  including wire bond electrical connections;  
         [0028]      FIG. 9A  is a isometric top view of a subassembly of the invention, including the wire bonds of  FIG. 8B  shown encapsulated with protective material;  
         [0029]      FIG. 9B  is a plan view of the subassembly shown in  FIG. 9A ;  
         [0030]      FIG. 10A  is a isometric bottom view of the subassembly shown in  FIG. 9A ;  
         [0031]      FIG. 10B  is a plan view of the subassembly shown in  FIG. 10A ;  
         [0032]      FIG. 11A  is a perspective view of the subassembly shown in  FIG. 9A  with a coil wound on the middle section of the ferrite core;  
         [0033]      FIG. 11B  is a cross-section view of the subassembly shown in  FIG. 11A  taken along line  11 B- 11 B;  
         [0034]      FIG. 11C  is a bottom plan view of the subassembly shown in  FIG. 11A  with the coil ends depicted;  
         [0035]      FIG. 12  is an enlarged detail perspective view of the subassembly shown in  FIG. 11C  placed in a soldering fixture;  
         [0036]      FIG. 13A  is an exploded view of a carrier used during assembly;  
         [0037]      FIG. 13B  is a top view of the top carrier plate of  FIG. 13A ;  
         [0038]      FIG. 13C  is a bottom view of the bottom carrier plate of  FIG. 13A ;  
         [0039]      FIG. 14  is a perspective view of a work-plate supporting the bottom carrier plate of  FIG. 13A , with the subassembly of  FIG. 11A  and a stimulating capacitor placed in the bottom carrier plate;  
         [0040]      FIG. 15  is a perspective view of a battery with connecting wires; and  
         [0041]      FIG. 16  is a perspective view of the subassembly of  FIGS. 11A-11C  with the battery of  FIG. 15  and the stimulating capacitor of  FIG. 14  attached.  
         [0042]     Corresponding reference characters indicate corresponding components throughout the several views of the drawings. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0043]     The following description is of the best mode presently contemplated for carrying out the inventions. This description is not to be taken in a limiting sense, but is merely for the purpose of describing the general principles of the inventions. The scope of the presently claimed invention should be determined with reference to the claims.  
         [0044]     As described above, the compact electronic modules and methods of manufacture as described and claimed may be used with numerous devices. Such modules and techniques are particularly useful in implantable medical devices, as an example, and as such will be described in conjunction with such an implantable medical device. However, as will be understood by those of skill in the art of electronic devices, such modules and methods may be used with other types of devices.  
         [0045]     The exemplary medical device that will be used herein to describe the systems and methods of the inventions is a small, implantable stimulator, and more particularly a battery-powered microstimulator known as a Bion® microstimulator. For purposes of the present disclosure, the battery-powered Bion microstimulator will be referred to as device  10  or microstimulator  10 .  
         [0046]     The exemplary device  10  has a substantially cylindrical shape (while other shapes are possible) and at least portions of it are hermetically sealed. It includes a processor and other electronic circuitry that allow it to generate stimulus pulses that are applied to a patient through electrodes in accordance with a program that may be stored, if necessary or desired, in programmable memory. The exemplary device  10  also includes a rechargeable battery. The battery is recharged, as required, from an external battery charging system.  
         [0047]      FIG. 1A  is a top view of device  10  depicting exemplary overall dimensions for a case  12  and some internal components. As seen in  FIG. 1A , the device  10  includes case  12 , electronic subassembly  14 , power source  16 , active/stimulating electrode  22 , and indifferent/reference electrode  24 . The diagram of  FIG. 1A  is useful as a simplified representation of the example device  10 , depicting just a few of the device components. A cross-section of the assembled device  10  is shown in  FIG. 1B . A better understanding of the designs, functions, interactions, and methods of manufacture of various components is provided in the details that follow.  
         [0048]     As mentioned above, the exemplary device used herein to describe the inventions is a substantially cylindrical medical device, microstimulator  10 . In this exemplary configuration, case  12  has an outer diameter D 1  of about 3.20 mm to about 3.30 mm. The inner diameter of the portion of case  12  enclosing electronic subassembly  14  is shown in  FIG. 1A  as D 2 . The inner diameter of the portion of case  12  enclosing battery  16  is shown as D 3 . Inner diameter D 2  is about 2.40 mm to about 2.54 mm, and inner diameter D 3  is about 2.92 mm to about 3.05 mm.  
         [0049]     The length of case  12  plus stimulating electrode  22  is shown in  FIG. 1A  as L 1 , and is about 27 mm. Length L 2  of case  12  without electrode  22  is about 24.5 mm. The portion of case  12  enclosing electronic subassembly  14  is shown in  FIG. 1A  as length L 3 , and has a value of about 13.00 mm. The portion of case  12  enclosing battery  16  is shown in  FIG. 1A  as length L 4 , which has a value of about 11.84 mm. Of course, these values can vary. For instance, L 1  will change as the type of stimulating electrode  22  changes. As mentioned earlier, the fact that the assemblies and methods described and claimed herein may be used with small devices is one of the advantages of the inventions, but it is in no way limiting. The methods and systems described and claimed may be used with a multitude of devices of varying size and shape. To facilitate understanding of these methods and systems, some components of device  10  and their manufacture/assembly are discussed in detail below.  
         [0050]     As shown in  FIG. 1A , device  10  includes a power source (e.g., a rechargeable battery  16 ) and an electronic subassembly  14 . Electronic subassembly  14  contains circuitry and other components for, e.g., stimulation, battery charging, telemetry, and production testing. Rechargeable battery  16  is a self-contained rechargeable battery, e.g., a lithium-ion battery, which powers device  10 . Battery  16  is recharged, as required, from an external battery charging system (not shown).  
         [0051]     Device  10  contains an inductive coil  18  (shown in  FIG. 1B ) for receiving power for battery charging and for telemetry. Coil  18  may also be utilized to implement additional functions, including voltage conversion/high voltage generation. In the present exemplary configuration, coil  18  has an exemplary cylindrical shape and is constructed from multiple turns of conductive wire wound around a two-piece, dumbbell-shaped ferrite core. Assembly of coil  18  and the two-piece ferrite core, and other electronic components, will be discussed in more detail presently.  
         [0052]     Some internal components  200  of device  10  are shown unassembled in  FIG. 2A , and their interactions once assembled are depicted in the circuit diagram of  FIG. 2B . These components  200  include stimulating capacitor  15 ; battery  16 ; substrate panel  202 ; integrated circuit (IC)  206 ; capacitors  208 A 1 ,  208 A 2 ,  208 B 1 , and  208 B 2 ; diodes  210 A and  210 B; ferrite halves  212 A and  212 B; and unwound conductive coil wire  216 . Assembly of these components is described below. Portions of the device and its manufacture/assembly are not detailed herein as they are not necessary for describing the inventions. Materials mentioned in the description of the manufacturing/assembly process are exemplary; other suitable materials may be used.  
         [0053]     As illustrated in  FIG. 3 , up to ten or more devices may be (but are not necessarily) batch processed for at least a portion of the manufacture/assembly process. Batch processing allows the assembly procedures and testing to be more efficient than assembling each unit individually.  FIG. 3  shows substrate panel assembly  202   n , which includes substrate panels  202 A,  202 B,  202 C, . . . through  202 J, which individual panels are sometimes referred to herein as panel  202  or substrate  202 . The contour of each panel  202  of substrate panel assembly  202   n  may be precut, with only small portions of the edges left attached to substrate panel assembly  202   n . The small portions that are left intact aid the alignment of other components and make future singularization of each panel  202  easier, even when other components have been assembled to panel assembly  202   n.    
         [0054]     Substrate panel assembly  202   n  is a single layer, double-sided, polyimide-copper circuit board, or other suitable flexible substrate design/material(s). As is common in the art, mounting pads and traces on the top and bottom of the panels (see  FIGS. 4A and 4B , respectively) are gold-plated copper or the like and are electrically connected by vias through the panel material. The pads and traces on the top of substrate panels  202  are solderable and wire bondable. The pads on the bottom of panels  202  are solderable.  
         [0055]     Substrate panel assembly  202   n  may be identified by a serial number printed on a portion of the assembly during manufacturing of the panel assembly  202   n , while each panel  202  of substrate panel assembly  202   n  may be uniquely serialized, e.g., using a laser beam. For instance, metal pads  203 C and  203 D (shown in  FIGS. 10B , and  11 C),which are used for test probing during several steps of the assembly process, may carry each unique panel serial number.  
         [0056]     As seen, e.g., in  FIGS. 1B, 5  and  10 A, the top and bottom of substrate panel assembly  202   n  are used to mount other components. As examples, an integrated circuit  206  is mounted to the top  204  of each substrate panel  202  and capacitor  208 B 1 ,  208 B 2  are mounted to the bottom  205  of each substrate panel. All the off-chip, or secondary, components are electrically connected to IC  206  through substrate  202  or through redistributed surface  720 , as described below.  
         [0057]     Integrated circuit (IC)  206  is a custom designed IC chip (ASIC). The IC wafer includes a multitude of these custom ICs  206 . The bare ICs  702  are made using standard IC manufacturing processes. Wafer-level processing reduces production costs by allowing manufacturing and testing of large numbers of ICs at one time. The IC wafer is then taken through a post-process called redistribution, which creates a redistributed surface  720 , an example of which is shown in  FIGS. 6A and 6B , and as described below: 
        a) Polyimide (or other suitable insulation) is deposited on the top face  207  of the bare IC  702 , if insulation is needed or desired.     b) Photosensitive material such as photoresist is deposited on top of the insulation.     c) The photosensitive material is exposed, e.g., through a mask, in only selected areas (i.e., where the insulation is to remain or is to be removed, depending on whether a “positive” or “negative” process is used), as in photochemical etching processes known in the art.     d) All of the photosensitive material and the portions of the insulation that are not needed are removed, e.g., with a chemical stripping solution. This leaves a first insulation layer  704  where needed, but allows the interconnect pads (aluminum or the like) on the top face  207  of the bare IC to remain exposed.     e) Optionally, a layer of conductive material (e.g., copper) is deposited as a grounding plane  706 . When used, grounding plane  706  is ideally positioned between two layers of bond material  705  and  707 , such as titanium tungsten. Photosensitive etching or the like is used to remove these materials from around each interconnect pad, leaving all but a ground pad isolated.     f) When grounding plane  706  is used, optional insulation layer  708 , of polyimide or the like, is applied (via photochemical etching or the like) to select areas, leaving exposed the interconnect pads.     g) A bond layer  709  of titanium tungsten or the like is deposited to aid the bonding of metal (e.g., copper) redistribution layer  710 , if needed or desired. Photosensitive etching or the like may be used at this point, or later, as described below.     h) A layer of copper or other conductive material is deposited. This conductive material (aided by the surrounding layers) creates the traces and mounting/interconnect/test pads, e.g., mounting pads  718  and interconnect pads  719 / 719 A, of the “redistribution” of redistribution layer  710  and redistribution surface  720  that allow, e.g., secondary components such as capacitors  208 A 1 / 208 A 2  and diodes  210 A/ 210 B to be assembled above IC  206 . This redistribution also simplifies interconnections between IC  206  and substrate  202 , as shown in  FIG. 12B . Photosensitive etching or the like may be used at this point, or later, as described below.     i) Titanium tungsten or other suitable bonding material is applied to redistribution layer  710  to create bond layer  711 , if needed or desired. Photosensitive etching or the like may be used at each layer  709 ,  710 , and  711  individually, or may be used for two or all three of these layers at a time. As such, the material of bond layers  709  and  711  may have the same pattern as redistribution layer  710 , or may cover more or less than the redistribution layer material (such as only where two metals overlap).     j) Insulation layer  714  of polyimide or the like is applied (via photochemical etching or the like) to select areas, leaving some conductive areas exposed, e.g., for mounting pads  718  on which secondary components such as capacitors  208 A 1 / 208 A 2  and diodes  210 A/ 210 B will be placed.     k) A conductive layer  715  of gold or other conductive material is applied (again, via photochemical etching or the like), if needed or desired, to conductive areas, e.g., mounting pads  718  on which secondary components such as capacitors  208 A 1 / 208 A 2  and diodes  210 A/ 210 B will be placed, so may thus be part of a surface layer  716 . Conductive layer  715  is preferably (but not necessarily) about 8-10 microns thick when complete, while the other layers of redistributed surface  720  are preferably about 4-5 microns when complete.         Depending on the above described options that are used, various “layers”, e.g., parts of redistribution layer  710 , insulation layer  714 , parts of conductive layer  715 , may form surface layer  716 .    
 
         [0070]     This redistribution process, the resulting redistributed surface  720 , and use thereof differ from standard redistribution processes, results, and uses. In standard use, redistribution is used to route connections from peripheral pads into a ball grid array or other area array pattern of “under bump metallurgy” balls that allows the chip to be, for instance, “flipped” onto a printed wire board or other substrate having matching interconnects. The unique redistribution process of the present invention forms a custom-designed layout resulting in a number of mounting pads  718  on which off-chip secondary components are directly mounted, as well as a number of test and interconnect pads  719 / 719 A, some of which are routed to the periphery of the IC.  
         [0071]     The resulting configuration of IC  206  (i.e., with redistributed surface  720 ), substrate  202 , and secondary, off-chip components has a number of advantages. Bare IC  702  includes all circuitry that would ordinarily be included or desired in the IC, with no added requirements or detrimental effect to the IC. For instance, bare IC  702  is not constrained by requiring mounting pads in particular positions on the bare IC top face  207  (and/or the packaging is not constrained by having surface mounted components positioned where most convenient for the IC design). The redistributed surface  720  on bare IC  702  contains substrate-like mounting pads  718  above the top face  207  of bare IC  702 , which accommodate secondary components that typically require large mounting pads for attachment. This redistributed surface  720  contains larger, more reliable traces than would traces in the IC, allowing more reliable routing to more conveniently placed, more durable, and larger mounting pads  718  than interconnection pads on the top face  207  of the “bare” IC  702 . Since the secondary components mounted on redistributed surface  720  would normally use significant substrate surface area, the size and complexity of substrate  202  is minimized, which in turn minimizes the size of the device containing substrate  202  (or frees up space for other components).  
         [0072]     Also, the number of connections between the IC and substrate is reduced or eliminated. Connections between off-chip components and the substrate are also reduced since off-chip components mounted to the redistributed surface  720  are thereby connected electrically to the IC, rather than being electrically connected by wire bonding through the substrate, as are components surface mounted to some “bare” ICs. Surface mounting components to the redistributed surface  720 , rather than directly to the “bare” IC is also more reliable. For instance, mechanical stress on solder joints between a “bare” IC and a traditionally surface mounted component, induced by a thermal mismatch between the IC and the component, is alleviated.  
         [0073]     Additionally, the ICs may be batch processed, as may placing components on the ICs, leading to increased efficiency, yield, and/or cost savings. In addition, this arrangement facilitates use of traditional, low-cost, reliable chip-and-wire technology for IC-to-substrate and secondary component-to-substrate connections.  
         [0074]     Furthermore, space above a bare IC  702  that would ordinarily be unused is occupied by components that would otherwise increase the size of the device. The added layers on bare IC top face  207  also provide a damping media for protection against the stresses and damages caused by assembly handling and component placement. The IC and substrate being of similar length also increases the mechanical strength of the subassembly, which, e.g., increases yield through production processing.  
         [0075]     The optional grounding plane  706  provides electronic shielding for sensitive components within IC  206 , when needed. Since the redistribution brings interconnected circuits and components into close proximity, noise signals and voltage levels from the secondary components may potentially affect circuits within IC  206 . Grounding plane  706 , connected to a grounding pad (but not connected to any other interconnect pads), provides an isolated and quiet environment for electronics in IC  206 .  
         [0076]     Insulation layer  714  may potentially be created after secondary component(s) are mounted to mounting pad(s)  718 . For instance, a non-conductive epoxy or the like may be used to encapsulate the bottom portion of a secondary component and surrounding areas where insulation is desired, such as on traces formed during creation of redistributed surface  720 .  
         [0077]     Using the top  204  of the substrate assembly  202   n  or each substrate panel  202 , a non-conductive adhesive such as non-conductive epoxy is applied to attach each integrated circuit  206  as shown in  FIG. 5 . After the ICs  206  are assembled to substrate panels  202 , each non-serialized IC  206  is uniquely identified by the serial number on substrates  202 , and can be tested and calibrated with calibration information saved together with the serial number. For instance, test pads  719 A (and/or pads  718 ,  719 ) may be used for testing at this point, as they may also have been used for testing of the ICs at wafer level. However, once the ICs are assembled to substrates, the calibration and test results may be saved with the respective serial numbers.  
         [0078]     Conductive epoxy or the like is used to attach off-chip components, e.g., capacitors  208 A 1 ,  208 A 2  and diodes  210 A,  210 B, to mounting pads  718  on the redistributed surface  720  of each IC  206 , as shown in  FIGS. 7A and 7B . As seen in  FIG. 8A  and in enlarged view in  FIG. 8B , conductive wires  214 , such as gold wires, electrically connect components (e.g., capacitors  208 B 1 ,  208 B 2 ) through the substrate to the IC. Wires  214  are attached to traces on the substrate top  204  and to pads  719  on the IC redistributed surface  720  via wire bonding. Similarly, wires  214 A, such as gold wires, connecting traces on substrate top  204  to diodes  210 A and  210 B (which are already electrically connected to IC  206  through mounting pads  718  and redistribution surface  720 ) are attached via wire bonding.  
         [0079]     Quality inspection and testing (e.g., using test pads  719 A) are typically performed at this point, as well as at other points in the manufacturing process. To protect wires  214 ,  214 A from damage that may occur during the assembly and handling, the wires may be encapsulated, e.g., with an epoxy (such as Hysol®, available from Loctite of Rocky Hill, Conn.) or other non-conductive material  217 , as shown in  FIGS. 9A and 9B .  
         [0080]     As seen, e.g., in  FIGS. 1B, 9A ,  1 A, and  11 B, ferrite half cylinders  212 A and  212 B “sandwich” a portion of panel  202  and a portion of associated integrated circuit  206 . This design maximizes the length of ferrite (or other suitable core material) half cylinders  212 A and  212 B and diameter of the resulting ferrite core and coil  18 , thus maximizing the magnetic inductance of the coil assembly. At the same time, since the ferrite halves “sandwich” IC  206  and substrate  202 , the length of the housing is less than if these components were arranged in series. The sandwich design protects the IC and substrate while increasing the mechanical strength of the assembly. In addition, positioning IC  206  and substrate  202  between the ferrite halves allows the size of the IC (and substrate) to be maximized without lengthening the electronic subassembly  14  (and thus the device). Furthermore, the length of IC  206  (and substrate  202 ) is not limited to the length of the ferrite core; IC  206  can extend nearly the full length of electronic subassembly  14 , allowing mounting of secondary components above IC  206  via redistributed surface  720 .  
         [0081]     By extending IC  206  through and beyond the ferrite core, it is possible to use a “one-chip” approach, thus avoiding the difficulties of processing two ICs. It is possible to use a two-IC approach, for instance, using flip-chip technology. However, using two chips potentially increases the number of interconnects, the size of the subassembly, and the difficulties of processing the subassembly. For instance, under-fill reinforcement may be difficult, while processing without under-fill reinforcement requires more placement accuracy, which may decrease efficiency, e.g., due to piece processing rather than batch processing.  
         [0082]     In addition, as can be seen in the figures, core halves  212 A and  212 B form a core having a “dumbbell” shape. This shape further increases coil inductance by maximizing the ferrite material and diameter at the ends of the ferrite core. In addition, the dumbbell shape aids in the winding of wire  216  into coil  18  by acting as a mandrel, by constraining the wire to fit in the middle section of the dumbbell shape, and by centering the winding along the ferrite core. The dumbbell shape also helps to protect the wire of coil  18  during subsequent assembly steps. In addition, having a dumbbell shaped core achieves these goals while also facilitating creation of a cylindrically shaped device, which is the most efficient shape for some uses. For instance, a cylindrically shaped microstimulator  10  is ideally suited for insertion into a body through a cannula.  
         [0083]     Non-conductive epoxy or other appropriate non-conductive adhesive is applied to bond top ferrite half  212 A to a portion of IC redistributed surface  720 , as shown in  FIGS. 8A, 9A , and  9 B. Similarly, non-conductive epoxy or the like is applied to bond bottom ferrite half  212 B to a portion of substrate bottom  205 , as shown in  FIGS. 10A and 10B . Alternatively, the coil may hold the ferrite halves in place, so no or little adhesive material need be used.  
         [0084]     Conductive adhesive such as conductive epoxy is applied to bond and electrically connect capacitors  208 B 1  and  208 B 2  to substrate mounting pads  730  ( FIG. 4B ) on the substrate bottom  205 , as shown in  FIGS. 10A and 10B . At this point in the assembly/manufacture process, partially assembled units  200 A are typically separated from panel assembly  202   n , e.g., by breaking away the pre-cut small portions made to contour the edge of each panel  202 . Of course, panels  202  may be separated from panel assembly  202   n  by any useful means and at any useful point in assembly/manufacture.  
         [0085]      FIGS. 9B and 10B  show pads  203 A,  203 B,  203 C, and  203 D protruding from one end of the ferrite “sandwich” arrangement. Pads  203 A and  203 B are used to connect stimulating capacitor  15 , as described below, and can also be used for testing. As described earlier, pads  203 C and  203 D carry the serial number and are also used for electrical test probing. (Connector pads  201 A,  201 B,  201 C, and  201 D ( FIGS. 10A and 10B ) may also be used for testing.) Also seen in  FIGS. 10A and 10B  is mark  221  (shown on capacitor  208 B, but it may be placed wherever practical) which aids in orientation and handling during manufacturing.  
         [0086]     The unwound coil wire  216 , made of 46 gauge insulated magnetic copper wire or other suitable conductive wire material, is wound on the middle section of the ferrite halves  212 A and  212 B (see  FIGS. 11A and 11B ). The coil wire  216  in a wound configuration is referred to as coil  18 , as shown, e.g, in  FIGS. 1B, 11A , and  11 B. Coil  18  may have, for instance, 156 turns in two layers, identified in  FIG. 11B  as coil layer  223 A and coil layer  223 B. One coil layer or more than two coil layers may instead be used, as may a different number of turns in the winding. The number of turns and layers, and other design elements of the coil assembly, depend on the requirements of the coil assembly, such as frequency, current, and voltage. As shown in  FIG. 11B  and discussed earlier, an exemplary “dumbbell” configuration is formed with the arrangement of the two core halves  212 A and  212 B in which the gap formed by the distances A and B is used to wind coil  216 . This configuration maximizes the size of the core and the coil (and IC  206  and substrate  202 , as described earlier) in the constrained space of case  12 , and aids in manufacturing.  
         [0087]     A soldering fixture  226 , shown in  FIG. 12 , may be used to assist in terminating the coil  18  ends  228 A and  228 B to pads  201 A and  201 B of panel  202  ( FIG. 11C ). Soldering coil ends  228 A and  228 B becomes more practical when the subassembly  200 B is isolated and secured using soldering fixture  226  or other suitable fixture. Subassembly  200 B is placed in fixture  226  with the bottom of panel  202  facing up, as identified by mark  221  or other orientation marker, and is held firmly in place, for instance, by handle  226 A which is tightened by bolt  226 B.  FIG. 12  shows subassembly  200 B securely loaded in soldering fixture  226 . The two coil ends  228 A and  228 B are soldered or similarly connected to pads  201 A and  201 B, respectively. Tinning of pads  201 C and  201 D may also be performed at this time, and subassembly  200 B may be baked prior to battery  16  attachment.  
         [0088]     A carrier  230 , such as shown in  FIG. 13A , can be used to facilitate further assembly processes by, for instance, aiding in concentric/coaxial alignment of components, serving as a dimensional control gauge, easing handling by effectively increasing the size of the device being handled, providing protection for sensitive components, allowing stacking of devices (e.g., within carriers during processing, baking, temperature cycling or other testing), and/or providing access for testing during various stages of assembly. Carrier  230  may be made of conductive or dissipative polyetherimide (such as Ultem®, available from GE Plastics of Pittsfield, Mass.), or other material to limit Electrical Static Discharge (ESD).  
         [0089]     Carrier  230  may comprise two plates: top plate  230 A ( FIGS. 13A and 13B ) and bottom plate  230 B ( FIGS. 13A and 13C ). Cavities  231 A,  231 B, and  231 C ( FIG. 13A ) securely hold the partially assembled device when plates  230 A and  230 B are bolted (or otherwise coupled) together. Top plate  230 A contains openings  232 A and  232 B and bottom plate  230 B contains openings  232 C and  232 D to allow access to the device components for assembly, testing, and inspection. Plates  230 A and  230 B are securely fastened, e.g., with bolts  234 A and  234 B that align with holes  233 A and  233 B ( FIG. 13A ). If desired, carrier  230  (or bottom plate  230 B) may be aligned and secured to a work plate  239  via holes  233 C and  233 D in carrier  230  and pins  237 A and  237 B on work plate  239  (see  FIG. 14 ), or other suitable method. Having the carrier  230  aligned and secured to a work plate  239  may further facilitate portions of the assembly process.  
         [0090]     Subassembly  200 B and stimulating capacitor  15  are placed in carrier bottom plate  230 B as shown in  FIG. 14 , then top plate  230 A is secured to bottom plate  230 B, e.g., with bolts  234 A and  234 B. Stimulating capacitor  15  may be a tantalum capacitor, for instance, in which case it would preferably include a gold-plated nickel ribbon attached via resistance welding or the like to a tantalum pin protruding from one end of capacitor  15 , as shown in  FIG. 2A . If, as another example, a ceramic capacitor  15  is used, a ribbon would not be needed. Instead, a wire of stainless steel, nickel, copper, solder coated copper, or the like, protruding from one end of capacitor  15  may simply be bent to one side for attachment to pad(s)  203 A/ 203 B.  
         [0091]     The type of stimulating capacitor  15  used may depend on the intended use of microstimulator  10 . For instance, a tantalum capacitor may have a capacitance of approximately 7 microfarads, while a ceramic capacitor may have a capacitance of approximately 3 microfarads. The capacitor best suited to the requirements of the device in a given setting may thus be chosen. In any case, stimulating capacitor  15  is preferably a right circular cylinder that fits snugly within case  12 .  
         [0092]     Through opening  232 A on top plate  230 A, testing at pads  203 A/ 203 B (which are electrically connected) may be accomplished, then solder, conductive epoxy, or other suitable conductive adhesive  229  is applied (or other suitable method is used) to bond the ribbon or wire (or the like) of stimulating capacitor  15  to pad  203 A and/or  203 B. A material such as UV or thermal curable non-conductive epoxy  229 A or the like may also be applied to reinforce the connection (see  FIG. 16 ). Optionally, one or a portion of one of pads  203 A/ 203 B is left exposed for further testing. At this point, as at various points throughout the manufacturing process, the assembly is tested and processed through burn-in, baking, and temperature cycling while in carrier  230 . For instance, opening  232 C may be used to test at pads  201 A,  201 B,  201 C, and/or  201 D. Openings  232 D may be used to test at pads  203 C and  203 D, and stimulating capacitor  15 .  
         [0093]     If battery  16  was not previously placed in the carrier, top carrier plate  230 A is removed, battery  16  is placed in cavity  231 C of bottom plate  230 B, and top plate  230 A is fastened back in place. Battery  16 , shown in  FIG. 15 , has a cathode (negative polarity) shell  70  and an anode (positive polarity) center pin  95  that protrudes, e.g., 0.25 mm from one end. Shell may be made of titanium, stainless steel, or other suitable cathodic material, while pin  95  may be made of platinum, molybdenum or other suitable anodic material. Two wires  68 A and  68 B made of nickel or the like are used for connecting battery  16  to electronic subassembly  14 . Wire  68 A is insulated (to prevent shorting) and laser welded or otherwise electrically connected to pin  95 , and wire or ribbon  68 B (insulated or not) is laser welded or otherwise electrically connected to the case of the battery.  
         [0094]     Battery  16  is placed into cavity  231 C so the long ends of wires  68 A and  68 B are pointing downwards (towards bottom plate  230 B and bottom  205  of panel  202 ). Using opening  232 B through top plate  230 A, UV curable non-conductive epoxy  219  or the like is applied to reinforce the connection of the wires to the battery, while leaving the long ends of the wires  68 A and  68 B free. Carrier  230  is turned over so the free ends of wires  68 A and  68 B are accessible via opening  232 C in bottom plate  230 B. The free ends of wires  68 A and  68 B are trimmed, if necessary, and bent towards substrate  202 . The free end of wire  68 A is soldered to substrate pad  201 D and the free end of wire  68 B is soldered to substrate pad  201 C. To complete subassembly  200 C, as shown in  FIG. 16 , additional non-conductive epoxy  219  or the like may be applied to further secure the connection of wire  68 A soldered to pad  201 D and wire  68 B soldered to pad  201 C.  
         [0095]     Once assembly  200 C is complete, components  200  are contained within, e.g., housing  12  consisting of two cylindrical shells  213  and  215 , as best seen in the cross sectional view of  FIG. 1B . A variety of materials and shapes may be used for the housing. Via electrical attachment to stimulating capacitor  15 , electrode  22  becomes the active or stimulating electrode. Shell  213  is electrically attached to the cathodic surface of battery  16 , and a portion thereof may be formed, coated, plated, or otherwise processed with suitable material(s) to become the indifferent electrode  24 , as shown in  FIG. 1B . The device may be further processed with one or more coatings, or other post-assembly processes.  
         [0096]     While the inventions herein disclosed have been described by means of specific embodiments and applications thereof, numerous modifications and variations could be made thereto by those skilled in the art without departing from the scope of the invention set forth in the claims. For instance, a number of the assembly/manufacturing procedures described may be performed in a different sequence than detailed herein. Some sequences were presented in an order most conducive to describing the general principles of the inventions, and should not be construed as limiting. Variations are within the scope of the inventions, as defined by the various claims.