Abstract:
A method for making semiconductor devices may include forming a phosphosilicate glass (PSG) layer on a semiconductor wafer, with the PSG layer having a phosphine residual surface portion. The method may further include exposing the phosphine residual surface portion to a reactant plasma to integrate at least some of the phosphine residual surface portion into the PSG layer. The method may additionally include forming a mask layer on the PSG layer after the exposing.

Description:
FIELD OF THE INVENTION 
     The present invention relates to the field of electronic devices and, more particularly, to semiconductor devices and related methods. 
     BACKGROUND OF THE INVENTION 
     Cleaning is performed during semiconductor processing to remove surface particles, contaminants, native or chemical oxides, etc. Wafer cleaning and surface preparation steps may be required throughout the fabrication process, and inadequate cleaning may result in significant losses in device yield. 
     Various approaches for semiconductor wafer cleaning may be used. One approach involves wet chemical cleaning, in which a chemical is applied to react with a contaminant and remove it from the wafer surface. Another approach involves a jet scrubber, which sprays very fine droplets of water or chemicals at a high velocity onto a wafer surface to scrub contaminants or other particles away from the surface of the wafer. 
     Despite the existence of such approaches, further enhancements in wafer cleaning may be desirable, such as for next generation devices with relatively small dimensions. 
     SUMMARY OF THE INVENTION 
     A method for making semiconductor devices may include forming a phosphosilicate glass (PSG) layer on a semiconductor wafer, with the PSG layer having a phosphine residual surface portion. The method may further include exposing the phosphine residual surface portion to a reactant plasma to integrate at least some of the phosphine residual surface portion into the PSG layer. The method may additionally include forming a mask layer on the PSG layer after the exposing. 
     More particularly, the reactant plasma may comprise oxygen. Furthermore, forming of the mask layer may be performed after the exposing without an intervening scrubbing operation. Forming the PSG layer may comprise a deposition at a first radio frequency (RF) power, and exposing the phosphine residual surface portion to the reactant plasma may be performed at a second RF power less than the first RF power. 
     In addition, forming the PSG layer and exposing the phosphine residual surface portion may be performed in an RF plasma chamber. By way of example, exposing of the phosphine residual surface portion may be performed at a pressure in a range of 3 to 5 Torr. Also by way of example, exposing of the phosphine residual surface portion may be performed at a temperature in a range of 300 to 500° C. Additionally, forming the dielectric layer and exposing the phosphine residual surface portion may be performed with an N 2 O flow rate in a range of 1000-1200 scc, for example. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic block diagram illustrating a semiconductor processing step for removing a phosphine residual surface portion from a phosphosilicate glass (PSG) layer in accordance with an example embodiment. 
         FIG. 2  is a flow diagram illustrating a method for making a semiconductor device including the phosphine residual surface portion removal step shown in  FIG. 1 . 
         FIG. 3  is a table illustrating example processing parameters for an implementation of the method of  FIG. 2 . 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout. 
     Referring initially to  FIG. 1 , during semiconductor wafer processing, a wafer  30  (e.g., silicon, silicon-germanium, etc.) may be held by a chuck  31  within a processing chamber  32  (e.g., a radio frequency (RF) plasma chamber). In the illustrated example, a phosphosilicate glass (PSG) insulating layer  33  is formed on the underlying wafer  30 . By way of example, dielectric insulating layers such as PSG (including borophosphosilicate glass or BPSG) may be deposited between metal or conducting layers in semiconductor devices. However, when depositing certain dielectric layers, a residual surface portion(s) or layer  34  may be left which requires removal or cleaning before subsequent steps may be adequately performed. For example, in the case of PSG deposition, phosphine gas (which is introduced into the processing chamber  32  via a showerhead  35 ) may be adsorbed on the upper surface of the PSG layer  33  leaving the phosphine residual layer  34 . Yet, the residual layer  34  may prove problematic in subsequent steps, such as a masking step, if not removed. That is, the masking material may be subject to “popping” or peeling off the PSG layer  33  as a result of the residual layer  34 . Applicant theorizes, without wishing to be bound thereto, that this is because the surface contamination prevents proper photoresist adhesion on the PSG layer  33 . 
     As a result, it may therefore be desirable to remove the residual layer  34  prior to proceeding with subsequent processing steps (e.g., mask layer deposition for layer patterning, etc). This would typically be done using a physical method such as a jet scrubber or chemical cleaning, as discussed above. However, both of these approaches may have certain drawbacks in the semiconductor fabrication process. For example, while a jet scrubber will lower the hit rate of the residual layer  34 , it typically will not remove all of the residual layer. Furthermore, both of these approaches may involve extra steps/cycle time, and therefore increased costs associated with the fabrication process. 
     Referring additionally to the flow diagram  40  of  FIG. 2 , in accordance with an example embodiment, another approach for removing the residual layer  34  is now described. Beginning at Block  41 , upon formation of the PSG layer  33  on the semiconductor wafer  30  (and, consequently, the residual layer  34 ), the phosphine residual surface portion(s) may be exposed to a reactant plasma to integrate the phosphine residual surface portion into the PSG layer, at Block  43 . 
     More particularly, a gas flow (e.g., an oxygen-based gas flow, such as N 2 O) may be introduced via the showerhead  35  along with RF energy to provide the reactant plasma. Generally speaking, the PSG layer  33  may involve a deposition at a first RF power (e.g. 300 w, while the exposure of the phosphine residual surface portion to the reactant plasma may be performed at a second RF power (e.g. 250 w) less than the first RF power. That is, the reactant plasma exposure may advantageously be performed at a reduced power level with respect to the PSG layer  33  deposition. 
     The Applicant theorizes that the N 2 O will fully react with the residual phosphine complex of the residual layer  34  and integrate it into the PSG layer  33 . This will not only provide a purging effect, but also removal of the residual phosphine gases. The unreacted gases are accordingly adsorbed into the surface of the wafer  30  to remove this contamination from PSG layer  33 , which would otherwise prevent proper adhesion of a masking or photoresist layer subsequently on the PSG layer, for example, at Block  44 . The method of  FIG. 2  concludes at Block  45 . Those of skill in the art will recognize that other steps may be performed both before and after the noted steps to form semiconductor devices, such as integrated circuits, for example. 
     The above-described approach may advantageously allow for the removal of the jet scrubber or chemical clean after passivation PSG deposition, while providing for little or no mask popping issues. That is, formation of the mask layer may be performed after the reactant plasma exposure without an intervening jet or chemical scrubbing operation. As a result, this may provide a significant savings in terms of wafer cost and cycle time. 
     Referring more particularly to the chart  50  of  FIG. 3 , example processing flow parameters are provided for an implementation of the above-described approach, which includes the introduction of a stable gas (1), PSG deposition (2), the N 2 O plasma clean (3), lifting (4) and pumping (5), as shown. Of course, it will be appreciated that subsequent device processing steps (including additional PSG or dielectric depositions and residual layer removal) may be performed to provide additional layers or regions depending upon the given semiconductor device to be fabricated. 
     In the illustrated example, exposing of the phosphine residual surface portion(s)  34  may be performed at a pressure in a range of 3 to 5 Torr, and more specifically about 4 Torr. Also by way of example, exposing of the phosphine residual surface portion(s)  34  may be performed at a temperature in a range of 300 to 500° C., and more particularly about 400° C. The PSG layer  33  deposition and exposure of the phosphine residual surface portion(s)  34  may be performed with an N 2 O flow rate in a range of 1000-1200 scc, and more particularly 1100 scc, for example. Other exemplary processing parameters are shown in the chart  50 , although it will be appreciated that different parameters may be used in different embodiments. 
     Using the example approach shown in  FIG. 3 , a semiconductor wafer fabrication test run was performed. As compared with a similar approach which utilized a jet scrubber, use of the reactant plasma removal instead of the jet scrubber shortened the total product cycle time by approximately two hours per lot. Over a 40-week implementation period with approximately 5000 lots processed, a total of approximately 10,000 lot hours were saved. This is due in part to no longer needing to transport the wafer  30  to a jet scrubber station after deposition of the PSG layer  33 . In terms of cost savings, it is estimated the savings from the above-described approach are approximately $0.60 (USD) per wafer, resulting in about $80,000 in total savings cost for the 40-week implementation. 
     The test run resulted in no noticeable occurrences of popping. Moreover, the example approach utilizes existing materials and may be performed in the same chamber  32  in which the PSG layer  33  deposition occurs. It was also determined that there was a negligible impact on existing inline qualification parameters. 
     Many modifications and other embodiments of the invention will come to the mind of one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is understood that the invention is not to be limited to the specific embodiments disclosed, and that modifications and embodiments are intended to be included within the scope of the appended claims.