Abstract:
A Universal Series Bus USB port detection and testing circuit, configured to detect the voltage output of a USB port of an electronic device, includes a voltage comparing circuit and an indicating circuit. The indicating circuit is connected to an output terminal of the voltage comparing circuit. The voltage comparing circuit compares the voltage output from the USB port against a reference voltage and output a signal whereby the indicating circuit indicates whether the voltage is within, or above, or below, the standard range.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure relates to a Universal Series Bus (USB) port detecting circuit, and more particularly to a USB port detecting circuit capable of detecting whether the voltage of a USB port is within a standard range. 
         [0003]    2. Description of Related Art 
         [0004]    Today, USB technology is broadly applied in series communication solutions. Before selling or using electronic devices having USB ports, the USB ports need to be tested. A conventional method for testing the USB ports is to use some conventional USB devices such as mice, keyboards, hard disk drives, etc., to directly connect with the USB ports, and so judge whether the USB ports are functioning properly or not. However, this method requires plugging and unplugging the devices to or from the USB ports separately and frequently, which is laborious. Furthermore, the conventional method is unable to detect whether the voltage of a USB port is within a certain, standard range. 
         [0005]    Therefore, there is room for improvement within the art. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    Many aspects of the embodiments can be better understood with references to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the embodiments. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views. 
           [0007]      FIG. 1  is a block diagram of a USB port detecting circuit according to an embodiment. 
           [0008]      FIG. 2  is a detailed view of the circuit of  FIG. 1 . 
           [0009]      FIG. 3  is a detailed view of the voltage comparing chip included in  FIG. 2 . 
       
    
    
     DETAILED DESCRIPTION 
       [0010]    The disclosure is illustrated by way of example and not by way of limitation. In the accompanying drawings, like references indicate similar elements. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean at least one. 
         [0011]    Referring to  FIG. 1 , an embodiment of a USB port detecting circuit is configured to test whether the voltage output of a USB port  10  of an electronic device (such as a computer) is within a standard range (e.g., 4.75V-5.25V). The USB port detecting circuit includes a voltage dividing circuit  20  connected to the USB port  10 , a voltage comparing circuit  30  connected to the voltage dividing circuit  20 , an indicating circuit  40  connected to the voltage comparing circuit  30 , and an electric load  50  connected to the USB port  10 . 
         [0012]    Referring to  FIG. 2 , the voltage dividing circuit  20  includes a first resistor R 1 , a second resistor R 2 , and a third resistor R 3  which are connected in series. A first terminal of the first resistor R 1  is connected to a positive terminal of the USB port  10 , and a second terminal of the first resistor R 1  is connected to a first node A. A first terminal of the second resistor R 2  is connected to the first node A. A second terminal of the second resistor R 2  is connected to a second node B. A first terminal of the third resistor R 3  is connected to the second node B. A second terminal of the third resistor R 3  is connected to the ground terminal of the USB port  10 . In one embodiment, the resistance of the first resistor R 1  is substantially equal to that of the third resistor R 3 . The resistance of the second resistor R 2  is three twenty-eighths ( 3/28) of the resistance of the first resistor R 1  or the second resistor R 3 . For instance, if the first resistor R 1  and the third resistor R 3  each had a resistance of 14KΩ (Kilohms), the resistance of the second resistor R 2  would be 1.5 KΩ (Kilohms). 
         [0013]    The voltage comparing circuit  30  includes a voltage comparing chip U 1 . In one embodiment, the voltage comparing chip U 1  is a TSM103 chip. The voltage comparing chip U 1  includes pins  1 - 8 . The pin  1  is connected to a third node C. The pin  2  is connected to the first node A. The pin  3  is connected to a first capacitor C 1 . The pin  4  is connected to the ground terminal of the USB port  10 . The pin  5  is connected to the second node B. The pin  6  is connected to the pin  3  and has the same voltage as the pin  3 . The pin  7  is connected to a fourth node D. The pin  8  is connected to the positive terminal of the USB port  10 . 
         [0014]    The indicating circuit  40  includes a first light emitting diode (LED) L 1 , a second LED L 2 , a third LED L 3 , a fourth LED L 4 , a first diode D 1 , and a second diode D 2 . An anode of the first LED L 1  is connected to the positive terminal of the USB port  10  via a ninth resistor R 9 . A cathode of the first LED L 1  is connected to the anodes of the first diode D 1  and the second diode D 2 . A cathode of the first diode D 1  is connected to the fourth node D 1 . A cathode of the second diode D 2  is connected to the third node C. An anode of the second LED L 2  is connected to the fourth node D. A cathode node of the second LED L 2  is connected to an anode of the fourth LED L 4  via a tenth resistor R 10 . An anode of the third LED L 3  is connected to the third node C. A cathode of the third LED L 3  is connected to the anode of the fourth LED L 4  via the tenth resistor R 10 . A cathode of the fourth LED L 4  is connected to the ground terminal of the USB port  10 . 
         [0015]    The electric load  50  includes a switch module S 1 , a fourth resistor R 4 , a fifth resistor R 5 , a sixth resistor R 6 , a seventh resistor R 7 , and an eighth resistor R 8 . The resistors R 4 -R 8  are connected in parallel and located between the positive terminal and the ground terminal of the USB port  10 . The switch module S 1  includes five switches, one of each switch connected to a resistors R 4 -R 8  respectively. The switches can be switched on or off to respectively increase or decrease the load connected to the USB port  10 . A second capacitor C 2  is connected to the positive and ground terminals of the USB port  10 . 
         [0016]    Referring to  FIG. 3 , the voltage comparing chip U 1  includes a first comparator OP 1  and a second comparator OP 2 . The positive input terminal of the first comparator OP 1  is connected to the pin  3  and coupled with a reference voltage Vref. The negative input terminal of the first comparator OP 1  is connected to the pin  2 . The output terminal of the first comparator OP 1  is connected to the pin  1 . The positive input terminal of the second comparator OP 2  is connected to the pin  5 . The negative input terminal of the second comparator OP 2  is connected to the pin  6 . The output terminal of the second comparator OP 2  is connected to the pin  7 . When a voltage on the positive terminal of the first comparator OP 1  (or the second comparator OP 2 ) exceeds the voltage on the negative terminal of the first comparator OP 1  (or the second comparator OP 2 ), the output terminal of the first comparator OP 1  (or the second comparator OP 2 ) is at a high level. Otherwise, the output terminal of the first comparator OP 1  (or the second comparator OP 2 ) is at a low level. The pin  8  is a Vcc+ pin (positive power pin), and the pin  4  is a Vcc− pin (negative power pin). In one embodiment, the Vref is 2.5 volts. 
         [0017]    When the voltage of the USB port  10  is within the standard range, e.g., the voltage of the USB port  10  is exactly 5 volts, the voltage of the first node A is substantially equal to 2.6 volts which is greater than the Vref at the positive input terminal of the first comparator OP 1 . The output terminal of the first comparator OP 1  outputs a low level voltage to the third node C via the pin  1 . The voltage of the second node B is substantially equal to 2.37 volts which is less than the Vref at the negative input terminal of the second comparator OP 2 . The output terminal of the second comparator OP 2  outputs a low level voltage to the fourth node D. The first LED L 1  is powered on and lights up. The second LED L 2 , the third LED L 3 , and the fourth LED L 4  receive no power. The indicating circuit  40  indicates that the voltage of the USB port  10  is within the standard range. 
         [0018]    When the voltage of the USB port  10  is greater than the standard range, e.g., the voltage at the USB port  10  is more than 5.25 volts, the voltage of the first node A is greater than the Vref at the positive input terminal of the first comparator OP 1 . The output terminal of the first comparator OP 1  outputs a low level signal to the third node C via the pin  1 . The voltage of the second node B is greater than the Vref at the negative input terminal of the second comparator OP 2 . The output terminal of the second comparator OP 2  outputs a high level signal to the fourth node D. The first LED L 1 , the second LED L 2 , and the fourth LED L 4  are powered on and light up. The third LED L 3  receives no power. The indicating circuit  40  indicates that the voltage of the USB port  10  is greater than the standard range. 
         [0019]    When the voltage of the USB port  10  is less than the standard range, e.g., the voltage of the USB port  10  is less than 4.75 volts, the voltage of the first node A is less than the Vref at the positive input terminal of the first comparator OP 1 . The output terminal of the first comparator OP 1  outputs a high level signal to the third node C via the pin  1 . The voltage of the second node B is less than the Vref at the negative input terminal of the second comparator OP 2 . The output terminal of the second comparator OP 2  outputs a low level signal to the fourth node D. The first LED L 1 , the third LED L 3 , and the fourth LED L 4  are powered on and light up. The second LED L 2  receives no power. The indicating circuit  40  indicates that the voltage of the USB port  10  is less than the standard range. 
         [0020]    In one embodiment, the voltage at the USB port  10  is divided by the voltage dividing circuit  20 . The divided voltage is sent to the voltage comparing circuit  30 . The voltage comparing circuit  30  compares the divided voltage with the Vref and outputs a high or a low level signal to the indicating circuit  40  according to the voltage level found. Then the indicating circuit  40  can indicate whether the voltage of the USB port  10  is within the standard range. 
         [0021]    While the present disclosure has been illustrated by the description of preferred embodiments thereof, and while the preferred embodiments have been described in considerable detail, it is not intended to restrict or in any way limit the scope of the appended claims to such details. Additional advantages and modifications within the spirit and scope of the present disclosure will readily appear to those skilled in the art. Therefore, the present disclosure is not limited to the specific details and illustrative examples shown and described.