Abstract:
Multiple DIMM circuits or instantiations are presented in a single module. In some embodiments, memory integrated circuits (preferably CSPs) and accompanying AMBs, or accompanying memory registers, are arranged in two ranks in two fields on each side of a flexible circuit. The flexible circuit has expansion contacts disposed along one side. The flexible circuit is disposed about a supporting substrate or board to place one complete DIMM circuit or instantiation on each side of the constructed module. In alternative but also preferred embodiments, the ICs on the side of the flexible circuit closest to the substrate are disposed, at least partially, in what are, in a preferred embodiment, windows, pockets, or cutaway areas in the substrate. Other embodiments may only populate one side of the flexible circuit or may only remove enough substrate material to reduce but not eliminate the entire substrate contribution to overall profile. The flexible circuit may exhibit one or two or more conductive layers, and may have changes in the layered structure or have split layers. Other embodiments may stagger or offset the ICs or include greater numbers of ICs.

Description:
RELATED APPLICATIONS 
   This application is a continuation-in-part of U.S. patent application Ser. No. 11/007,551, filed Dec. 8, 2004, which application is a continuation-in-part of U.S. patent application Ser. No. 10/934,027, filed Sep. 3, 2004. U.S. patent applications Ser. Nos. 10/934,027 and 11/007,551 are hereby incorporated by reference herein. 

   FIELD 
   The present invention relates to systems and methods for creating high density circuit modules. 
   BACKGROUND 
   The well-known DIMM (Dual In-line Memory Module) board has been used for years, in various forms, to provide memory expansion. A typical DIMM includes a conventional PCB (printed circuit board) with memory devices and supporting digital logic devices mounted on both sides. The DIMM is typically mounted in the host computer system by inserting a contact-bearing edge of the DIMM into a card edge connector. Systems that employ DIMMs provide, however, very limited profile space for such devices and conventional DIMM-based solutions have typically provided only a moderate amount of memory expansion. 
   As bus speeds have increased, fewer devices per channel can be reliably addressed with a DIMM-based solution. For example, 288 ICs or devices per channel may be addressed using the SDRAM-100 bus protocol with an unbuffered DIMM. Using the DDR-200 bus protocol, approximately 144 devices may be address per channel. With the DDR2-400 bus protocol, only 72 devices per channel may be addressed. This constraint has led to the development of the fully-buffered DIMM (FB-DIMM) with buffered C/A and data in which 288 devices per channel may be addressed. With the FB-DIMM, not only has capacity increased, pin count has declined to approximately 69 from the approximately 240 pins previously required. 
   The FB-DIMM circuit solution is expected to offer practical motherboard memory capacities of up to about 192 gigabytes with six channels and eight DIMMs per channel and two ranks per DIMM using one gigabyte DRAMs. This solution should also be adaptable to next generation technologies and should exhibit significant downward compatibility. 
   This great improvement has, however, come with some cost and will eventually be self-limiting. The basic principle of systems that employ FB-DIMM relies upon a point-to-point or serial addressing scheme rather than the parallel multi-drop interface that dictates non-buffered DIMM addressing. That is, one DIMM is in point-to-point relationship with the memory controller and each DIMM is in point-to-point relationship with adjacent DIMMs. Consequently, as bus speeds increase, the number of DIMMs on a bus will decline as the discontinuities caused by the chain of point to point connections from the controller to the “last” DIMM become magnified in effect as speeds increase. Consequently, methods to increase the capacity of a single DIMM find value in contemporary memory and computing systems. 
   There are several known methods to improve the limited capacity of a DIMM or other circuit board. In one strategy, for example, small circuit boards (daughter cards) are connected to the DIMM to provide extra mounting space. The additional connection may cause, however, flawed signal integrity for the data signals passing from the DIMM to the daughter card and the additional thickness of the daughter card(s) increases the profile of the DIMM. 
   Multiple die packages (MDP) are also used to increase DIMM capacity while preserving profile conformity. This scheme increases the capacity of the memory devices on the DIMM by including multiple semiconductor die in a single device package. The additional heat generated by the multiple die typically requires, however, additional cooling capabilities to operate at maximum operating speed. Further, the MDP scheme may exhibit increased costs because of increased yield loss from packaging together multiple die that are not fully pre-tested. 
   Stacked packages are yet another strategy used to increase circuit board capacity. This scheme increases capacity by stacking packaged integrated circuits to create a high-density circuit module for mounting on the circuit board. In some techniques, flexible conductors are used to selectively interconnect packaged integrated circuits. Staktek Group L.P. has developed numerous systems for aggregating CSP (chipscale packaged) devices in space saving topologies. The increased component height of some stacking techniques may alter, however, system requirements such as, for example, required cooling airflow or the minimum spacing around a circuit board on its host system. 
   Another trend to increase DIMM capacity is the use of larger capacity ICs such as, for example, 512 Mega-bit, 1 Giga-bit, and 2 Giga-bit or larger DRAM devices. The trend indicates that larger devices are forthcoming. Such larger devices may necessitate packages with larger dimensions until technological advances provide smaller feature sizes. For example, some high-capacity DRAM devices may be too big for a 30 mm DIMM. 
   Another problem associated with some such high-capacity is that their thickness may be greater than the specified thickness for many standard DIMM designs. For example, many JEDEC DIMM thickness specifications require a 1 mm package thickness to allow DIMMs with stacked devices to fit in specified dimensions with adequate airflow. Some new high-capacity devices may have a greater thickness than the specified 1 mm. Such thickness may lead to stacked DIMMs would exceed the maximum specified thickness. 
   What is needed, therefore, are methods to fit provide thin DIMM modules with high capacity. What is needed also needed are methods and structures for increasing the flexibility of FB-DIMMs. 
   SUMMARY 
   Multiple DIMM circuits or instantiations are combined in a single module to provide on a single module circuitry that is substantially the functional equivalent of two or more DIMMs but avoids some of the drawbacks associated with having two discrete DIMMs. In one embodiment, registered DIMM circuits are used. In another, FB-DIMM circuits are used. 
   In a preferred embodiment, integrated circuits (preferably memory CSPs) and accompanying AMBs are arranged in two ranks in two fields on each side of a flexible circuit. The flexible circuit has expansion contacts disposed along one side. The flexible circuit is disposed about a supporting substrate or board to place at least one FB-DIMM instantiation on each side of the constructed module. In alternative, but also preferred embodiments, the ICs on the side of the flexible circuit closest to the substrate are disposed, at least partially, in what are, in a preferred embodiment, windows, pockets, or cutaway areas in the substrate. Other embodiments may only populate one side of the flexible circuit or may only remove enough substrate material to reduce but not eliminate the entire substrate contribution to overall profile. Other embodiments may connect the constituent devices in a way that creates a FB-DIMM circuit or instantiation with the devices on the upper half of the module while another FB-DIMM instantiation is created with the devices on the lower half of the module. Other embodiments may, for example, combine selected circuitry from one side of the module (memory CSPs for example) with circuitry on the other side of the module (an AMB, for example) in creating one of plural FB-DIMM instantiations on a single module. Other embodiments employ stacks to provide multiple FB-DIMM circuits or instantiations on a low profile module. The flexible circuit may exhibit one or two or more conductive layers, and may have changes in the layered structure or have split layers. Other embodiments may stagger or offset the ICs or include greater numbers of ICs. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a depiction of a preferred embodiment of a module devised in accordance with the present invention. 
       FIG. 2  depicts a contact bearing first side of a flex circuit devised in accordance with a preferred embodiment of the present invention. 
       FIG. 3  depicts the second side of the exemplar populated flex circuit of  FIG. 2 . 
       FIG. 4  is a cross-sectional depiction through the devices as populated in an embodiment of the present invention. 
       FIG. 5  is an enlarged view of the area marked ‘A’ in  FIG. 4 . 
       FIG. 6  depicts a cross-sectional view of a module devised in accordance with an alternate preferred embodiment of the present invention. 
       FIG. 7  depicts the area near an end of a substrate in the embodiment shown in  FIG. 6 . 
       FIG. 8  depicts a cross-sectional view of a module assembly devised in accordance with a preferred embodiment of the present invention. 
       FIG. 9  is an enlarged view of a portion of one preferred embodiment. 
       FIG. 10  depicts one perspective of an exemplar module devised in accordance with a preferred embodiment of the present invention. 
       FIG. 11  is another depiction of the relationship between flex circuitry and a substrate  14  which has been patterned or windowed with cutaway areas. 
       FIG. 12  depicts a cross sectional view of an exemplar substrate employed in  FIG. 11  before being combined with populated flex circuits. 
       FIG. 13  depicts another embodiment of the invention having additional ICs. 
       FIG. 14  is a representation of impedance discontinuities in typical FB-DIMM systems. 
       FIG. 15  is a representation of impedance discontinuities in an embodiment of the present invention. 
       FIG. 16  depicts yet another embodiment of the present invention. 
       FIG. 17  presents another embodiment of the present invention. 
       FIG. 18  depicts a low profile embodiment of the present invention. 
       FIG. 19  depicts one side of a flex circuit used in constructing a module according to an alternative embodiment of the present invention. 
       FIG. 20  is a perspective view of a module according to an alternative embodiment of the present invention. 
       FIG. 21  is an exploded depiction of a flex circuit cross-section according to one embodiment of the present invention. 
       FIG. 22  depicts a clock transmission line topology connecting to DIMM registers according to one embodiment of the present invention. 
       FIG. 23  depicts a clock the depicted topology connecting to SDRAM devices according to one embodiment of the present invention. 
       FIG. 24  depicts one perspective of an exemplar module devised in accordance with another preferred embodiment of the present invention. 
       FIG. 25  is another depiction of the relationship between flex circuitry and a substrate which has been patterned or windowed with cutaway areas. 
       FIG. 26  depicts a cross sectional view of exemplar substrate employed in  FIG. 25  before being combined with populated flex circuits and as viewed along a line through windows of substrate. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1  depicts a preferred embodiment devised in accordance with the present invention. Module  10  is depicted in  FIG. 1  exhibiting ICs  18  and circuit  19 . 
     FIG. 2  depicts a first side  8  of flex circuit  12  (“flex”, “flex circuitry”, “flexible circuit”) used in constructing a module according to an embodiment of the present invention. Flex circuit  12  is preferably made from one or more conductive layers supported by one or more flexible substrate layers as further described with reference to later Figs. The construction of flex circuitry is known in the art. The entirety of the flex circuit  12  may be flexible or, as those of skill in the art will recognize, the flexible circuit structure  12  may be made flexible in certain areas to allow conformability to required shapes or bends, and rigid in other areas to provide rigid and planar mounting surfaces. Preferred flex circuit  12  has openings  17  for use in aligning flex circuit  12  to substrate  14  during assembly. 
   ICs  18  on flexible circuit  12  are, in this embodiment, chip-scale packaged memory devices of small scale. For purposes of this disclosure, the term chip-scale or “CSP” shall refer to integrated circuitry of any function with an array package providing connection to one or more die through contacts (often embodied as “bumps” or “balls” for example) distributed across a major surface of the package or die. CSP does not refer to leaded devices that provide connection to an integrated circuit within the package through leads emergent from at least one side of the periphery of the package such as, for example, a TSOP. 
   Embodiments of the present invention may be employed with leaded or CSP devices or other devices in both packaged and unpackaged forms but where the term CSP is used, the above definition for CSP should be adopted. Consequently, although CSP excludes leaded devices, references to CSP are to be broadly construed to include the large variety of array devices (and not to be limited to memory only) and whether die-sized or other size such as BGA and micro BGA as well as flip-chip. As those of skill will understand after appreciating this disclosure, some embodiments of the present invention may be devised to employ stacks of ICs each disposed where an IC  18  is indicated in the exemplar Figs. 
   Multiple integrated circuit die may be included in a package depicted as a single IC  18 . While in this embodiment memory ICs are used to provide a memory expansion board or module, and various embodiments may include a variety of integrated circuits and other components. Such variety may include microprocessors, FPGA&#39;s, RF transceiver circuitry, digital logic, as a list of non-limiting examples, or other circuits or systems which may benefit from a high-density circuit board or module capability. Circuit  19  depicted between ICs  18  may be a memory buffer, or controller (“register”) as are used in common DIMMs such as, for example, registered-DIMMs. In a preferred embodiment is the well known advanced memory buffer or “AMB”. 
   The depiction of  FIG. 2  shows flex circuit  12  as having first and second fields F 1  and F 2 . Each of fields F 1  and F 2  have at least one mounting contact array for CSPs such as the one depicted by reference  11 A. Contact arrays such as array  11  are disposed beneath ICs  18  and circuits  19 . An exemplar contact array  11 A is shown as is exemplar IC  18  to be mounted at contact array  11 A as depicted. The contact arrays  11 A that correspond to an IC plurality may be considered a contact array set. 
   Field F 1  of side  8  of flex circuit  12  is shown populated with first plurality of CSPs IC R1  and second plurality of CSPs IC R2  while second field F 2  of side  8  of flex circuit  12  is shown populated with first plurality of CSPs IC R1  and second plurality of CSPs IC R2 . Those of skill will recognize that the identified pluralities of CSPs are, when disposed in the configurations depicted, typically described as “ranks”. Between the ranks IC R2  of field F 1  and IC R2  of field F 2 , flex circuit  12  bears a plurality of module contacts allocated in this embodiment into two rows (C R1  and C R2 ) of module contacts  20 . When flex circuit  12  is folded as later depicted, side  8  depicted in  FIG. 2  is presented at the outside of module  10 . The opposing side  9  of flex circuit  12  is on the inside in several depicted configurations of module  10  and thus side  9  is closer to the substrate  14  about which flex circuit  12  is disposed than is side  8 . Other embodiments may have other numbers of ranks and combinations of plural CSPs connected to create the module of the present invention. 
     FIG. 3  shows side  9  of flex circuit  12  depicting the other side of the flex circuit shown in  FIG. 2 . Side  9  of flex circuit  12  is shown as being populated with multiple CSPs  18 . Side  9  includes fields F 1  and F 2  that each include at least one mounting contact array site for CSPs and, in the depicted case, include multiple contact arrays. Each of fields F 1  and F 2  include, in the depicted preferred embodiment, two pluralities of ICs identified in  FIG. 3  as IC R1  and IC R2 . Thus, each side of flex circuit  12  has, in a preferred embodiment, two fields F 1  and F 2  each of which fields includes two ranks of CSPs IC R1  and IC R2 . In later  FIG. 4 , it will be recognized that fields F 1  and F 2  will be disposed on different sides of substrate  14  in a completed module  10  when ICs  18  are identified according to the organizational identification depicted in  FIGS. 2 and 3  but those of skill will recognize that the groupings of ICs  18  shown in  FIGS. 2 and 3  are not dictated by the invention but are provided merely as an exemplar organizational strategy to assist in understanding the present invention. 
   Various discrete components such as termination resistors, bypass capacitors, and bias resistors, in addition to the buffers  19  shown on side  8  of flex circuit  12 , may be mounted on either or both of sides  8  and  9  of flex  12 . Such discrete components are not shown to simplify the drawing. Flex circuit  12  may also depicted with reference to its perimeter edges, two of which are typically long (PE long1  and PE long2 ) and two of which are typically shorter (PE short1  and PE short2 ) Other embodiments may employ flex circuits  12  that are not rectangular in shape and may be square in which case the perimeter edges would be of equal size or other convenient shape to adapt to manufacturing particulars. Other embodiments may also have fewer or greater numbers of ranks or pluralities of ICs in each field or on a side of a flex circuit. 
     FIG. 2  depicts an exemplar conductive trace  21  connecting row C R2  of module contacts  20  to ICs  18 . Those of skill will understand that there are many such traces in a typical embodiment. Traces  21  may also connect to vias that may transit to other conductive layers of flex  12  in certain embodiments having more than one conductive layer. In a preferred embodiment, vias connect ICs  18  on side  9  of flex  12  to module contacts  20 . An example via is shown as reference  23 . Traces  21  may make other connections between the ICs on either side of flex  12  and may traverse the rows of module contacts  20  to interconnect ICs. Together the various traces and vias make interconnections needed to convey data and control signals amongst the various ICs and buffer circuits. Those of skill will understand that the present invention may be implemented with only a single row of module contacts  20  and may, in other embodiments, be implemented as a module bearing ICs on only one side of flex circuit  12 . 
     FIG. 4  is a cross section view of a module  10  devised in accordance with a preferred embodiment of the present invention. Module  10  is populated with ICs  18  having top surfaces  18   T  and bottom surfaces  18   B . Substrate or support structure  14  has first and second perimeter edges  16 A and  16 B appearing in the depiction of  FIG. 4  as ends. Substrate or support structure  14  typically has first and second lateral sides S 1  and S 2 . Flex  12  is wrapped about perimeter edge  16 A of substrate  14 , which in the depicted embodiment, provides the basic shape of a common DIMM board form factor such as that defined by JEDEC standard MO-256. 
     FIG. 5  is an enlarged view of the area marked ‘A’ in  FIG. 4 . Edge  16 A of substrate  14  is shaped like a male side edge of an edge card connector. While a particular oval-like configuration is shown, edge  16 A may take on other shapes devised to mate with various connectors or sockets. The form and function of various edge card connectors are well know in the art. In many preferred embodiments, flex  12  is wrapped around edge  16 A of substrate  14  and may be laminated or adhesively connected to substrate  14  with adhesive  30 . The depicted adhesive  30  and flex  12  may vary in thickness and are not drawn to scale to simplify the drawing. The depicted substrate  14  has a thickness such that when assembled with the flex  12  and adhesive  30 , the thickness measured between module contacts  20  falls in the range specified for the mating connector. In some other embodiments, flex circuit  12  may be wrapped about perimeter edge  16 B or both perimeter edges  16 A and  16 B of substrate  14 . In other instances, multiple flex circuits may be employed or a single flex circuit may connect one or both sets of contacts  20  to the resident ICs. 
     FIG. 6  depicts a cross-sectional view of a module  10  devised in accordance with an alternate preferred embodiment of the present invention with the view taken along a line through two AMBs and selected ICs  18  from IC R1 . The module  10  depicted in  FIG. 6  differs from that shown in earlier embodiments in that rather than a single flex circuit  12 , the depicted exemplar module  10  employs two flex circuits  12 A and  12 B with  12 A being disposed on one lateral side S 1  of substrate  14  while flex circuit  12 B is employed on lateral side S 2  of substrate  14 . 
     FIG. 7  depicts the area near end  16 A of substrate  14  in the embodiment shown in  FIG. 6  that employs two flex circuits identified as  12 A and  12 B to implement a module in accordance with an alternate preferred embodiment of the present invention. Each of flex circuits  12 A and  12 B are populated with ICs  18  on one or both of their respective sides  8  and  9  and each of flex circuits  12 A and  12 B employ a buffer circuit  19  such as, for example, an advanced buffer circuit or AMB to implement, along with the resident CSPs, multiple FB-DIMM circuits mounted on a single module  10 . The area on side  9  of each of flex circuits  12 A and  12 B opposite the disposition of buffer circuit  19  disposed along side  8  of flex circuits  12 A and  12 B is, in the depicted module, filled with a conformal material  31  to provide support along the length of module  10  where structure is not provided by the bodies of circuits such as ICs  18  or buffers  19 . 
     FIG. 8  depicts a cross-sectional view of a module  10  devised with a substrate  14  that has cutaway areas into which ICs  18  are disposed to reduce the profile of module  10 . Corresponding ICs  18  from each of fields F 1  and F 2  pass through windows  250  in substrate  14  as shown in later Figs. in further detail and the inner ICs  18  are preferably attached to each other&#39;s upper surfaces  18   T  with a thermally conductive adhesive  30 . While in this embodiment, the depicted ICs are attached to flex circuit  12  in opposing pairs, fewer or greater numbers of ICs may be connected in other arrangements such as, for example, staggered or offset arrangements in which they may exhibit preferred thermal characteristics. In a preferred embodiment, ICs  18  will be CSPs and typically, memory CSPs. To simplify the drawing, discrete components such as resistors and capacitors typically found on embodiments of module  10  are not shown. 
   In this embodiment, flex circuit  12  has module contacts  20  positioned in a manner devised to fit in a circuit board card edge connector or socket and connect to corresponding contacts in the connector (not shown). While module contacts  20  are shown protruding from the surface of flex circuit  12 , other embodiments may have flush contacts or contacts below the surface level of flex  12 . Substrate  14  supports module contacts  20  from behind flex circuit  12  in a manner devised to provide the mechanical form required for insertion into a socket. In other embodiments, the thickness or shape of substrate  14  in the vicinity of perimeter edge  16 A may differ from that in the vicinity of perimeter edge  16 B. Substrate  14  in the depicted embodiment is preferably made of a metal such as aluminum or copper, as non-limiting examples, or where thermal management is less of an issue, materials such as FR4 (flame retardant type 4) epoxy laminate, PTFE (poly-tetra-fluoro-ethylene) or plastic. In another embodiment, advantageous features from multiple technologies may be combined with use of FR4 having a layer of copper on both sides to provide a substrate  14  devised from familiar materials which may provide heat conduction or a ground plane. 
     FIG. 9  is an enlarged view of a portion of one preferred embodiment showing lower IC  18   1  and upper IC  18   2  and substrate  14  having cutaway areas into which ICs  18  are disposed. In this embodiment, conductive layer  66  of flex circuit  12  contains conductive traces connecting module contacts  20  to BGA contacts  63  on ICs  18   1  and  18   2 . The number of layers may be devised in a manner to achieve the bend radius required in those embodiments that bend flex circuit  12  around edge  16 A or  16 B, for example. The number of layers in any particular portion of flex circuit  12  may also be devised to achieve the necessary connection density given a particular minimum trace width associated with the flex circuit technology used. Some flex circuits  12  may have three or four or more conductive layers. Such layers may be beneficial to route signals in a FB-DIMM which may have fewer DIMM input/output signals than a registered DIMM, but may have more interconnect traces required among devices on the DIMM, such as, for example, the C/A copy A and C/A copy B (command/address) signals produced by an FB-DIMM AMB. 
   In this embodiment, there are three layers of flex circuit  12  between the two depicted ICs  18   1  and  18   2 . Conductive layers  64  and  66  express conductive traces that connect to the ICs and may further connect to other discrete components (not shown). Preferably, the conductive layers are metal such as, for example, copper or alloy  110 . Vias such as the exemplar vias  23  connect the two conductive layers  64  and  66  and thereby enable connection between conductive layer  64  and module contacts  20 . In this preferred embodiment having a three-layer portion of flex circuit  12 , the two conductive layers  64  and  66  may be devised in a manner so that one of them has substantial area employed as a ground plane. The other layer may employ substantial area as a voltage reference plane. The use of plural conductive layers provides advantages and the creation of a distributed capacitance intended to reduce noise or bounce effects that can, particularly at higher frequencies, degrade signal integrity, as those of skill in the art will recognize. If more than two conductive layers are employed, additional conductive layers may be added with insulating layers separating conductive layers. Portions of flex circuit  12  may in some embodiments be rigid portions (rigid-flex). Construction of rigid-flex circuitry is known in the art. 
   With the construction of an embodiment such as that shown in  FIG. 9 , thermal energy will be urged to move between the respective ICs  18   1 . Thus, the ICs become a thermal mass sharing the thermal load. Flex circuit  12  may be particularly devised to operate as a heat spreader or sink adding to the thermal conduction out of ICs  18   1  and  18   2 . 
     FIG. 10  depicts one perspective of an exemplar module  10  devised in accordance with a preferred embodiment of the present invention. As those of skill will understand, the depiction of  FIG. 10  is simplified to show more clearly the principles of the invention but depicts fewer ICs  18  than would typically be presented in embodiments of the present invention. 
   The principles of the present invention may, however, be employed where only one IC  18  is resident on a side of a flex circuit  12  or where multiple ranks or pluralities of ICS are resident on a side of flex circuit  12 , or, as will be later shown, where multiple ICs  18  are disposed one atop the other to give a single module  10  materially greater. 
     FIG. 10  depicts a cross sectional view of an exemplar module showing a reduced number of ICs  18  to allow a clearer exposition of the principles of the present invention as illustrated by this depicted embodiment. The module shown in  FIG. 10  is formed with an exemplar flex circuit such as that depicted in  FIGS. 2 and 3 . The second side  9  of flex circuit  12  shown in  FIG. 3  is folded about substrate  14  shown in  FIG. 10  to place ICs  18  into the windows  250  arrayed along substrate  14 . This results in ICs of ranks IC R1  and IC R2  being disposed back to back within windows  250 . Preferably, a thermally conductive adhesive or glue is used on the upper sides of ICs  18  to encourage thermal energy flow as well as provide some mechanical advantages. Those of skill will recognize that in this embodiment, where  FIG. 10  depicts the first or, in this case, the outer side of the flex circuit once combined with substrate  14 , the flex circuit itself will have staggered mounting arrays  11 A on side  8  of flex circuit  12  relative to side  9  of flex circuit  12 . This is merely one relative arrangement between ICs  18  on respective sides of substrate  14 . 
   As shown in  FIG. 10 , ICs  18  which are on second side  9  (which in this depiction is the inner side with respect to the module  10 ) of populated flex circuit  12  are disposed in windows  250  so that the upper surfaces  18   T  of ICs  18  of row ICR 1  of F 1  are in close proximity with the upper surfaces  18   T  of ICs  18  of rank ICR 1  of F 2 . Thus, a first group of ICs (CSPs in the depiction) may be considered to be comprised of the ICs of IC R1  from both fields F 1  and F 2  while a second group of ICs may be considered to be comprised of the ICs of IC R2  from both fields F 1  and F 2 . The ICs  18  that are populated along side  9  of flex circuit  12  are positioned in the cutaway areas of the first and second lateral sides, respectively, of substrate  14 . In this case, the cutaway areas on each lateral side of substrate  14  are in spatial coincidence to create windows  250 . Those of skill will recognize that the depiction is not to scale but representative of the interrelationships between the elements and the arrangement results in a profile “P” for module  10  that is significantly smaller than it would have been without fitting ICs  18  along inner side  9  of flex circuit  12  into windows  250 . Profile P in this case is approximately the sum of the distances between the upper and lower surfaces of IC  18  plus 4× the diameter of the BGA contacts  63  plus 2× the thickness of flex circuit  12  in addition to any adhesive layers  30  employed to adhere one IC  18  to another. This profile dimension will vary depending upon whether BGA contacts  63  are disposed below the surface of flex circuit  12  to reach an appropriate conductive layer or contacts which typically are a part of flex circuit  12 . 
     FIG. 11  is another depiction of the relationship between flex circuitry and a substrate  14  which has been patterned or windowed with cutaway areas. The view of  FIG. 11  is taken along a line that would intersect the bodies of ICs  18 . In  FIG. 11 , two flex circuits  12 A and  12 B are shown populated along their respective sides  9  with ICs  18  (i.e., CSPs in the depiction). The ICs  18  along the inner side  9  of flex circuit  12 A are staggered relative to those that are along inner side  9  of flex circuit  12 B when module  10  is assembled and flex circuits  12 A and  12 B are combined with substrate  14 . This staggering may result in some construction benefits providing a mechanical “step” for ICs  18  as they are fitted into substrate  14  and may further provide some thermal advantages increasing the contact area between substrate  14  and the plurality of ICs  18 . Those of skill will recognize that flex circuits  12 A and  12 B even though depicted as being populated on only one side, may be populated on either or both sides  8  and  9  just as in those embodiments that employ a single flex circuit  12  may be populated one or both sides of flex circuit  12  and may have populated one or both fields or ranks within fields on one or both sides with CSPs or other circuits. 
     FIG. 12  depicts a cross sectional view of exemplar substrate  14  employed in  FIG. 11  before being combined with populated flex circuits  12 A and  12 B as viewed along a line through windows  250  of substrate  14 . As depicted in  FIG. 12 , a number of cutaway areas or pockets are delineated with dotted lines and identified with references  250 B 3  and  250 B 4 , respectively. Those areas identified as  250 B 3  correspond, in this example, to the pockets, sites, or cutaway areas on one side of substrate  14  into which ICs  18  from flex circuit  12 A will be disposed when substrate  14  and flex circuit  12 A are combined. Those pocket, sites, or cutaway areas identified as references  250 B 4  correspond to the sites into which ICs  18  from flex circuit  12 B will be disposed. 
   For purposes herein, the term window may refer to an opening all the way through substrate  14  across span “S” which corresponds to the width: or height dimension of packaged IC  18  or, it may also refer to that opening where cutaway areas on each of the two sides of substrate  14  overlap. 
   Where cutaway areas  250 B 3  and  250 B 4  overlap, there are, as depicted, windows all the way through substrate  14 . In some embodiments, cutaway areas  250 B 3  and  250 B 4  may not overlap or in other embodiments, there may be pockets or cutaway areas only on one side of substrate  14 . Those of skill will recognize that cutaway areas such as those identified with references  250 B 3  and  250 B 4  may be formed in a variety of ways depending on the material of substrate  14  and need not literally be “cut” away but may be formed by a variety of molding, milling and cutting processes as is understood by those in the field. 
     FIG. 13  depicts another embodiment of the invention having additional ICs  18 . In this embodiment, four flex level transitions  26  connect to four mounting portions  28  of flex circuits  12 A 1 ,  12 A 2 ,  12 B 1 , and  12 B 2 . In this embodiment, each mounting portion  28  has ICs  18  on both sides. Flex circuitry  12  may also be provided in this configuration by, for example, having a split flex with layers interconnected with vias. As those of skill will recognize, the possibilities for large capacity iterations of module  10  are magnified by such strategies and the same principles may be employed where the ICs  18  on one side of substrate  14  are staggered relative to those ICs  18  on the other side of substrate  14  or, substrates such as those shown in  FIG. 4  that have no cutaway areas may be employed. 
   Four flex circuits are employed in module  10  as depicted in  FIG. 13  and, although those embodiments that wrap flex circuit  12  about end  16 A of substrate  14  present manufacturing efficiencies, in some environments having flex circuitry separate from each other may be desirable. 
   In a typical FB-DIMM system employing multiple FB-DIMM circuits, the respective AMB&#39;s from one FB-DIMM circuit to another FB-DIMM circuit are separated by what can be conceived of as three impedance discontinuities as represented in the system depicted in  FIG. 14  as D 1 , D 2 , and D 3 .  FIG. 14  includes two modules  10  and includes a representation of the connection between the two modules. Discontinuity D 1  represents the impedance discontinuity effectuated by the connector—socket combination associated with the first module  10 F. Discontinuity D 2  represents the impedance perturbation effectuated by the connection between the connector-socket of first module  10 F and the connector-socket of second module  10 S while discontinuity D 3  represents the discontinuity effectuated by the connector-socket combination associated with the second module  10 S. The AMB is the new buffer technology particularly for server memory and typically includes a number of features including pass-through logic for reading and writing data and commands and internal serialization capability, a data bus interface, a deserialing and decode logic capability and clocking functions. The functioning of an AMB is the principal distinguishing hard feature of a FB-DIMM module. Those of skill will understand how to implement the connections between ICs  18  and AMB  19  in FB-DIMM circuits implemented by embodiments of the present invention and will recognize that the present invention provides advantages in capacity as well as reduced impedance discontinuity that can hinder larger implementations of FB-DIMM systems. Further, those of skill will recognize that various principles of the present invention can be employed to multiple FB-DIMM circuits on a single substrate or module. 
   In contrast to the system represented by  FIG. 14 ,  FIG. 15  is a schematic representation of the single impedance perturbation DX effectuated by the connection between a first AMB  19  of a first FB-DIMM “FB1” of a first module  10 F and a second AMB  19  of a second FB-DIMM “FB2” of the same first module  10 F. 
     FIG. 16  depicts another embodiment of the present invention in which a module  10  is devised using stacks to create a module  10  presenting two FB-DIMM circuits. Those of skill will appreciate that using stacks such as depicted stacks  40  owned by Staktek Group L.P. allows creating modules that have multiple FB-DIMM circuits on a single module. Stacks  40  are just one of several stack designs that may be employed with the present invention. Stacks  40  are devised with mandrels  42  and stack flex circuits  44  as described in U.S. patent application Ser. No. 10/453,398, filed Jun. 6, 2003 which is owned by Staktek Group L.P. and which is hereby incorporated by reference and stacks  40  and AMB  19  are mounted on flex circuit  12  which is disposed about substrate  14 . 
     FIG. 17  depicts use of stacks in an embodiment of the present invention that exhibits a low profile with use of stacks. Such an embodiment presents at least two FB-DIMM circuits at its contacts  20 . 
     FIG. 18  illustrates a low profile embodiment of the present invention. The depicted module  10  has at least two AMBs and associated circuitry such as ICs  18  which in the preferred mode and as illustrated are CSPs and needed support circuitry to create at least two FB-DIMM circuits or instantiations on a single module with a low profile. It should be understood that the second AMB in addition to the one literally shown can be disposed on either side of module  10  but preferably will be disposed closer to lateral side S 2  of substrate  14  than is the depicted AMB  19  but like AMB  19  will be disposed on side  8  of flex circuit  12 . In this embodiment, contacts  20  are along side  8  of flex circuit  12  and proximal to edge E of flex circuit  12 . The principal circuits that constitute the first FB-DIMM circuitry or instantiation (i.e., the CSPs and AMB) may be disposed in single rank file as shown. They may be allocated to first and second mounting fields of the first and second sides of flex circuit  12  as earlier described with reference to earlier FIGS. Those of skill will recognize that contacts  20  may appear on one or both sides of module  10  depending on the mechanical contact interface particulars of the application. 
   The present invention may be employed to advantage in a variety of applications and environment such as, for example, in computers such as servers and notebook computers by being placed in motherboard expansion slots to provide enhanced memory capacity while utilizing fewer sockets. The two high rank embodiments or the single rank high embodiments may both be employed to such advantage as those of skill will recognize after appreciating this specification. 
   One advantageous methodology for efficiently assembling a circuit module  10  such as described and depicted herein is as follows. In a preferred method of assembling a preferred module assembly  10 , flex circuit  12  is placed flat and both sides populated according to circuit board assembly techniques known in the art. Flex circuit  12  is then folded about end  16 A of substrate  14 . Flex  12  may be laminated or otherwise attached to substrate  14 . 
     FIG. 19  depicts a first side  8  of flex circuit  12  (“flex”, “flex circuitry”, “flexible circuit”) used in constructing a module according to an embodiment of the present invention. ICs  18  on flexible circuit  12  are, in this embodiment, chip-scale packaged memory devices of small scale. Circuit  19  depicted between ICs  18  may be a memory buffer or controller such as, for example, an AMB, but in this embodiment is a memory controller or register for a registered DIMM. This embodiment will preferably have further IC&#39;s  18  on an opposite side  9 , which is not depicted here. Flex circuit  12  is, in this embodiment, made from 4 conductive layers supported by flexible substrate layers as further described with reference to later Figs. The construction of flex circuitry is known in the art. 
   In this embodiment, flex circuit  12  is provided with holes  13 , which are devised to allow greater flexibility for bending flex circuit  12  to achieve a desired bend radius for curve  25  ( FIG. 20 ). Holes  13  (“holes”, “voids”, “partial voids”) preferably pass entirely through flex circuit  12 , but in other embodiments may be only partial holes or voids that may be expressed by one or more of the conductive layers of flex circuit  12 , and/or one or more of the flexible substrate layers of flex circuit  12 . Such partial voids may be devised to allow flexibility while still providing sufficient conductive material to allow the desired connections to contacts  20  and between the depicted ICs in field F 1  and field F 2 . 
   Holes  13  in this embodiment are spaced to allow traces  21  to pass between them at the level of conductive layers of flex  13 . While some preferred embodiments have a dielectric solder mask layer partially covering side  8 , traces  21  are depicted along side  8  for simplicity. Traces  21  may, of course, be at interior conductive layers of flex circuit  12 , as will be described further with regard to later referenced Figures. 
   In this embodiment, flex circuit  12  is further provided with holes  15 . Holes  15  are devised to allow flexibility for bending flex circuit  12  to achieve a desired bend radius for around edge  16 A or  16 B of substrate  14 , for example. Holes  15  may be expressed as voids or partial voids in the various conductive and non-conductive layers of flex circuit  12 . Further, a desired bend radius at the portions of flex circuit  12  provided with holes  13  or holes  15  may also be achieved by providing a portion of flex circuit  12  having fewer layers, as described above with reference to  FIG. 9 . 
   This embodiment of flex circuit  12  is also provided with mounting pads  191  along side  18  of flex circuit  12 . Such pads  191  are used for mounting components such as, for example, surface mount resistors  192 . 
     FIG. 20  is a perspective view of a module  10  according to an embodiment of the present invention. Depicted are holes  13  along curve  25 . Further, parts of holes  15  can be seen along the lower depicted edge of module  10 . Holes  13  may have an extent such that they are present along the entirety of curve  25 . Holes  15  may also be sized such that they span the entire bend around the edge of substrate  14 . Holes  13  and  15  may have a span greater than the length of their respective curves, or less that such length. For example, holes  13  and  15  may be sized such that they provide an adjusted bend radius for flex circuit  12  only in portions of the bend having a desired bend radius smaller that the radius possible with an unmodified flex circuit  12 . 
   When flex circuit  12  is folded as depicted, side  8  depicted in  FIG. 2  is presented at the outside of module  10 . The opposing side  9  of flex circuit  12  is on the inside in several depicted configurations of module  10  and thus side  9  is closer to the substrate  14  about which flex circuit  12  is disposed than is side  8 . 
   The depicted topology and arrangement of flexible circuitry may be used to advantage to create high capacity and thin-profile circuit modules. Such modules include, for example, registered DIMMS and FB-DIMMs. For example, a DIMM may be constructed having double device-mounting surface area for a given DIMM height. Such doubling may allow doubling of the number memory devices or enable larger devices that would not fit on traditional DIMMs. 
   For example, one preferred embodiment provides a 30 mm 4-GByte RDIMM using 512 Mbit parts. Another embodiment provides a 50 mm 8-GByte RDIMM using 1 Gbit parts. Yet another embodiment provides a 2-GByte SO-DIMM using 512 Mbit parts. DIMM modules may be provided having multiple instantiations of DIMM or FB-DIMM circuits, as further described herein. Also, DIMMs having the usual single instantiation of DIMM circuitry may be provided where the devices employed are too large to fit in the surface area provided by a typical industry DIMM module. Such high-capacity capability may be used to advantage to provide high capacity memory for computer systems having a limited number of motherboard DIMM slots. 
     FIG. 21  is an exploded depiction of a flex circuit  12  cross-section according to one embodiment of the present invention. The depicted flex circuit  12  has four conducive layers  2101 - 2104  and seven insulative layers  2105 - 2111 . The numbers of layers described are merely those of one preferred embodiment, and other numbers and layer arrangements may be used. 
   Top conductive layer  2101  and the other conductive layers are preferably made of a conductive metal such as, for example, copper or alloy  110 . In this arrangement, conductive layers  2101 ,  2102 , and  2104  express signal traces  2112  that make various connections on flex circuit  12 . These layers may also express conductive planes for ground, power, or reference voltage. For example, top conductive layer  2101  may also be provided with a flood, or plane, of to provide the VDD to ICs mounted to flex circuit  12 . 
   In this embodiment, inner conductive layer  2102  expresses traces connecting to and among the various devices mounted along the sides of flex circuit  12 . The function of any of the depicted conductive layers may, of course, be interchanged with others of the conductive layers. Inner conductive layer  2103  expresses a ground plane, which may be split to provide VDD return for pre-register address signals. Inner conductive layer  2103  may further express other planes and traces. In this embodiment, floods, or planes, at bottom conductive layer  2104  provides VREF and ground in addition to the depicted traces. 
   Insulative layers  2105  and  2111  are, in this embodiment, dielectric solder mask layers which may be deposited on the adjacent conductive layers. Insulative layers  2107  and  2109  are made of adhesive dielectric. Other embodiments may not have such adhesive dielectric layers. Insulative layers  2106 ,  2108 , and  2110  are preferably flexible dielectric substrate layers made of polyamide. Any other suitable flexible circuit substrate material may be used. 
     FIG. 22  depicts a clock transmission line topology connecting to DIMM registers according to one embodiment of the present invention. In this embodiment, four DIMM circuit instantiations are used on one module, one being on each of the four fields available on a flex circuit  12  such as, for example, the one in  FIG. 2 . The depicted transmission line topology shows the distribution of a clock input signal to each of four registers associated respectively with the four DIMM circuit instantiations. The transmission lines are expressed by the various conductive layers of the flex circuit, and may include vias passing between layers. 
   In this embodiment, clock and inverted clock signals CK and CK# enter the depicted topology from a phase-locked-loop (PLL) or delay-locked loop (DLL) output. Construction of PLLs and DLLs is known in the art. The PLL in this embodiment is preferably mounted along one side of flex circuit  12 , and the depicted topology routes clock signal CK to DIMM registers  2201  on the same side of flex circuit  12  as the PLL circuitry, as well as to DIMM registers  2201  on the opposing side. Transmission line TL 0  branches to two transmission lines TL 1 , which may be, in some embodiments, disposed at opposite sides of a substrate  14 . Each transmission line TL 1  branches into two TL 4  lines and a TL 2  line. Each transmission line TL 4  has a termination resistor R 1  or a bypass capacitor C 1 . Transmission line TL 2  branches into two TL 3  lines. A via through flex circuit  12  may be used at the branchpoint from TL 2  to TL 3 . Preferably, TL 2  is relatively short so as to place bypass capacitors C 1  relatively close to the branchpoint of TL 2  and TL 3 . 
     FIG. 23  depicts a clock the depicted topology connecting to SDRAM devices according to one embodiment of the present invention. The depicted transmission line topology routes clock signal CK to devices on both sides of flex circuit  12 . Transmission line TL 230  branches to a transmission line TL 231  terminated with a resistor R 231 , and two transmission lines TL 232 , which may be, in some embodiments, disposed at opposite sides of a substrate  14 . Each transmission line TL 232  branches into two TL 233  lines. A via through flex circuit  12  may be used at the branchpoint from TL 232  to TL 233 . 
     FIG. 24  depicts one perspective of an exemplar module  10  devised in accordance with another preferred embodiment of the present invention. As those of skill will understand, the depiction of  FIG. 24  is simplified to show more clearly the principles of the invention but depicts fewer ICs  18  than would typically be presented in embodiments of the present invention. The module shown in  FIG. 24  is formed similarly to that in  FIG. 10 , but has a thinner substrate  14 . 
     FIG. 25  is another depiction of the relationship between flex circuitry and a substrate  14  which has been patterned or windowed with cutaway areas. The view of  FIG. 25  is taken along a line that would intersect the bodies of ICs  18 . Assembly of the depicted arrangement is similar to that described with reference to  FIG. 11 . In this embodiment, however, substrate  14  does not have variations in thickness along different portions of module  10 . 
     FIG. 26  depicts a cross sectional view of exemplar substrate  14  employed in  FIG. 25  before being combined with populated flex circuits  12 A and  12 B as viewed along a line through windows  250  of substrate  14 . As depicted in  FIG. 26 , a number of cutaway areas or pockets are delineated with dotted lines and identified with references  250 B 3  and  250 B 4 , respectively. 
   Although the present invention has been described in detail, it will be apparent to those skilled in the art that many embodiments taking a variety of specific forms and reflecting changes, substitutions and alterations can be made without departing from the spirit and scope of the invention. Therefore, the described embodiments illustrate but do not restrict the scope of the claims.