Abstract:
A semiconductor integrated circuit, comprising: a first output driving part which outputs a data signal in sync with a reference clock signal; a second output driving part which outputs a data strobe signal prescribing a timing of said data signal; and a driving control part which separately controls driving ability of said first and second output driving parts.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
         [0001]    This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2001-278225, filed on Sep. 13, 2001, the entire contents of which are incorporated herein by reference.  
         BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates to a semiconductor integrated circuit and a memory system which output a data signal and a data strobe signal in sync with a reference clock signal.  
           [0004]    2. Related Background Art  
           [0005]    Recently, processors and memories have been used for various electric apparatuses. With speeding-up of processors and development of IT (Information Technology), a high speed memory has been required. According to the requirement, a memory such as a DDR SDRAM which transfers data at two fold frequency in sync with an external clock has been developed.  
           [0006]    In a conventional SDR SDRAM (Single Data Rate Synchronous DRAM), data has been transferred in sync with only rising edges of the clock. On the other hand, in DDR SDRAM (Double Data Rate Synchronous DRAM), data is transferred in sync with both of rising edges and falling edges of the clock. Because of this, the DDR SDRAM can obtain two fold of the transferring speed of the SDR SDRAM.  
           [0007]    However, the higher the data transferring speed becomes, the narrower a valid period of data (data window) becomes, and it becomes difficult to acquire data at a receiver side. Because of this, DDR SDRAM is newly provided with a data strobe signal (DQS), and the data is acquired based on this DQS at the receiver side.  
           [0008]    The DQS is a bi-directional signal in sync with the clock and used for both of data write and read. At the write time, the DQS and the write data DQ are received from an ASIC side to write them into the memory. Conversely, at the read time, the DQS is outputted from the memory, and the DQS and the DQ for the data read are received at the ASIC side.  
           [0009]    Thus, because the DQS is synchronized with the DQ, it is necessary to equalize a wiring length (trace length) of the DQS with that of the DQ.  
           [0010]    Here, the problem due to the high speeding-up is the timing for acquiring data at the read time. FIG. 7 is a diagram showing the timing for acquiring data at the write time and the read time, with regard to the bi-directional DQS prescribed by JEDEC-DDR.  
           [0011]    As shown in FIG. 7, although the data acquisition at the write and read times are carried out at both edges of the rising and falling edges of the DQS, the problem occurs at the read time.  
           [0012]    In the data acquisition at the write time, as shown in FIG. 7A, the clock edges of the DQS locate at the vicinity of center of the valid period of the write data signal DQ. Because of this, it is possible to surely acquire data at the rising edges of the DQS.  
           [0013]    On the other hand, as shown in FIG. 7B, in the read time when data is acquired at the controller side, both edges of the DQS and the changing points of the DQ are substantially the same timing. Because of this, as shown in FIG. 8, timing and phase of the DQS are staggered by using the DLL circuit and the PLL circuit at the controller side, and the timing has to be adjusted so that both edges of the DQS are located at the vicinity of an intermediate point of the valid period of data.  
           [0014]    However, as mentioned above, it is a burden for the controller side to provide the DLL circuit or the PLL circuit to the controller side. As a method of adjusting timing between the DQ and the DQS without providing the DLL circuit or the PLL circuit to the controller side, there is a method of adjusting wiring length between the memory and the controller. If the wiring length of the DQS is set to be longer than that of the DQ, the wiring delay time of the DQS becomes long in proportion to that of the DQ, and the DQS at the controller side can be set to the vicinity of the intermediate point of the valid period of data.  
           [0015]    However, by the difference such as arrangement of patterns and the amount of load, the capacitance load of the DQS may become larger than that of the DQ. In this case, the rising and falling waveforms of data dull, and it becomes difficult to enlarge margin of the valid period of data.  
           [0016]    [0016]FIG. 9 is a block diagram showing schematic configuration of a conventional memory system. The memory system of FIG. 9 has a controller  52  composing a memory  51  and an ASIC implemented on a print substrate. The memory  51  and the controller  52  sends and receives data via a transferring line  53  on the print substrate.  
           [0017]    The memory  51  has a storage part  50  for inputting/outputting a data signal QR based on external address signals Al-An and inputting/outputting the data strobe signal QRS in sync with a data signal QR, an I/O buffer  54   a  for inputting/outputting the data signal DQ relating to the data signal QR, an I/O buffer  54   b  for inputting/outputting the data strobe signal DQS relating to the data strobe signal QRS, and an address latch circuit  50  for controlling driving ability of the I/O buffer  54   a,    54   b  based on the external address signals A 1  and A 6 .  
           [0018]    Because the conventional address latch circuit shown in FIG. 9 does not separately adjust driver sizes of the I/O buffers  54   a  and  54   b,  it was impossible to perform fine adjustment of the DQ and the DQS in a simple method of extending trace length.  
           [0019]    Furthermore, in the conventional address latch circuit, the driving ability of the I/O buffers  54   a  and  54   b  has been set to be equal to each other. Because of this, if the amount of load of the transferring path of the DQ is not equal to that of the DQS, the signal waveform on the transferring path with a large amount of the load may dull.  
           [0020]    FIGS.  10 A- 10 B are a signal waveform diagram of the DQ and the DQS. FIG. 10A is a signal waveform diagram in the case of not being influenced by noise, and FIG. 10B is a signal waveform diagram in the case of being influenced by noise. Solid lines of these diagrams show the case where the waveform dulls, and dotted lines thereof show the case where the waveform does not dull.  
           [0021]    As evidenced by these diagrams, timing is staggered by with or without noise. If the waveform dulls, the signal changes gradually, and as a result, a timing when logic changes staggers. For example, in FIG. 10A, if the original time when logic of the signal changes is time×0, the time staggers to time×1 by dulling of the signal waveform. Similarly, when there is noise and the waveform also dulls, the time staggers to time×2.  
           [0022]    Thus, in the conventional memory system, the driving ability of the DQ and the DQS has not been separately controlled in the memory. Because of this, even if only the trace length is just extended, the waveform dulls by the change of the load, thereby complicating the timing adjustment. Accordingly, timing adjustment of the DQ and the DQS has to be performed by using the DLL circuit and the PLL circuit at the controller side, thereby complicating the inside configuration of the controller.  
         SUMMARY OF THE INVENTION  
         [0023]    A semiconductor integrated circuit according to an embodiment of the present invention, comprising:  
           [0024]    a first output driving part which outputs a data signal in sync with a reference clock signal;  
           [0025]    a second output driving part which outputs a data strobe signal prescribing a timing of said data signal; and  
           [0026]    a driving control part which separately controls driving ability of said first and second output driving parts.  
           [0027]    Furthermore, a memory system according to an embodiment of the present invention, comprising:  
           [0028]    a storage part which outputs a data signal corresponding to a designated address and a data strobe signal prescribing a timing of said data signal;  
           [0029]    a first output driving part which outputs said data signal in sync with a reference clock signal;  
           [0030]    a second output driving part which outputs said data strobe signal in sync with said data signal; and  
           [0031]    a driving control part which separately controls driving ability of said first and second output driving parts. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0032]    [0032]FIG. 1 is a diagram showing schematic configuration of an embodiment of a memory system according to the present invention.  
         [0033]    [0033]FIG. 2 is a block diagram showing internal configuration of the address latch circuit.  
         [0034]    [0034]FIG. 3 is a block diagram showing internal configuration of the I/O buffer.  
         [0035]    [0035]FIG. 4 is a block diagram showing internal configuration of the gate signal generating circuit.  
         [0036]    [0036]FIG. 5 is a logic diagram of the address signal and the output of the control signal generating circuit.  
         [0037]    [0037]FIG. 6 is a diagram showing the timing relationship of the data strobe signal (DQS) and the data signal (DQ) outputted from the I/O buffer.  
         [0038]    [0038]FIG. 7 is a diagram showing the timings for acquiring data at write time and read time, with regard to the bi-directional DQS prescribed by JEDEC DDR.  
         [0039]    [0039]FIG. 8 is a diagram describing an example of performing timing adjustment so that both edges of the DQS are located at the vicinity of the center of the data valid period.  
         [0040]    [0040]FIG. 9 is a block diagram showing schematic configuration of the conventional memory system.  
         [0041]    FIGS.  10 A- 10 B are signal waveform diagrams of the DQ and the DQS. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0042]    Hereinafter, a semiconductor integrated circuit and a memory system according to the present invention will be more specifically described with reference to drawings.  
         [0043]    [0043]FIG. 1 is a block diagram showing schematic configuration of an embodiment of a memory system according to the present invention. The memory system of FIG. 1 has a memory  1  and a controller  2  composing an ASIC. The memory  1  and the controller  2  send and receive data via transferring lines  3  formed on a print substrate.  
         [0044]    The controller  2  of FIG. 1 supplies the data signal DQ and the data strobe signal DQS to the memory  1  during the write time. On the other hand, the memory  1  supplies the DQ and the DQS to the ASIC during the read time.  
         [0045]    The memory  1  has a storage part  10  for inputting/outputting a data signal QR based on external address signals Al-An and inputting/outputting the data strobe signal QRS in sync with a data signal QR, an I/O buffer  11   a  for inputting/outputting the data signal DQ relating to the data signal QR, an I/O buffer  11   b  for inputting/outputting the data strobe signal DQS relating to the data strobe signal QRS, and an address latch circuit  12   a  for controlling driving ability of the I/O buffer  11   a  based on the external address signals A 1  and A 6 , and an address latch circuit  12   b  for controlling driving ability of the I/O buffer  11   b  based on the external address signals A 2  and A 5 .  
         [0046]    The storage part  10  is, for example, a core part of a DDR SDRAM (Double Data Rate Synchronous DRAM) and a peripheral circuit thereof.  
         [0047]    In the memory system of the present embodiment, compared with the conventional memory system shown in FIG. 9, address latch circuits  12   a  and  12   b  are provided corresponding to the I/O buffers  11   a  and  11   b,  respectively, and timings of the DQ and the DQS can be adjusted separately.  
         [0048]    [0048]FIG. 2 is a block diagram showing internal configuration of the address latch circuit  12   a.  The address latch circuit  12   a  of FIG. 2 has address receivers  21   a  and  21   b  for acquiring the external address signals A 1  and A 6 , flipflops  22   a,    22   b  and inverters  23   a - 23   d.    
         [0049]    The flipflops  22   a  and  22   b  latch logic value of the external address signals A 1  and A 6  by an EMR signal clocked in the case set to an extended mode. In the case except the extended mode, the flipflops  22   a  and  22   b  continues to hold logics of the latched A 1  and A 6 .  
         [0050]    The external address signals (A 1 , A 6 ) inputted to the address latch circuit  12   a  and the external address signals (A 2 , A 5 ) inputted to the address latch circuit  12   b  are used for address designation of the memory  1  at time except the extended mode. The memory  1  of the present embodiment controls driving ability of the I/O buffers by using a portion (A 1 , A 6 ) or (A 2 , A 5 ) of the external address signals used for memory access, in order to prevent increase of the number of terminals of the memory  1 .  
         [0051]    The flipflop  22   a  has a latch circuit  27  composing clocked inverters  24  and  25  and an inverter  26 , and a latch circuit  31  composing clocked inverters  28  and  29  and an inverter  30 .  
         [0052]    The latch circuit  27  acquires the external address signal A 1  when the clock signal EMR is in low level, and fixes and latches logic value of the external address signal Al when the clock signal EMR changes from low level to high level. The latch circuit  31  acquires the output of the latch circuit  27  when the clock signal EMR is in high level, and fixes and latches the logic value of the external address signal Al when the clock signal EMR changes from high level to low level.  
         [0053]    Similarly, the latch circuit  32  in the flipflop  22   b  acquires the external address signal A 6  when the clock signal EMR is in low level, and latches the logic value of the external address signal A 6  when the clock signal EMR changes from low level to high level. The latch circuit  33  acquires the output of the latch circuit  32  when the clock signal EMR is in high level, and fixes and latches the logic value of the external address signal A 6  when the clock signal EMR changes from high level to low level.  
         [0054]    Although FIG. 2 has shown the internal configuration of the address latch circuit  12   a,  the address latch circuit  12   b  has also the similar configuration as that of FIG. 2. The address latch circuit  12   b  is supplied with the external address signals A 2  and A 5 .  
         [0055]    As the detailed configuration is shown in FIG. 3, the I/O buffer  11   a  has a plurality of transistor groups  41   a - 41   d  each having a PMOS transistor and an NMOS transistor connected in series between a power supply terminal VDDQ and a ground terminal VSSQ, and a gate signal generating circuit  42  for generating gate signals PGTn 0 -PGTn 3  and NGTp 0 -NGTp 3  of each transistor group.  
         [0056]    A connection point of the PMOS transistor and the NMOS transistor in each of transistor groups  41   a - 41   d  is connected to the output terminal of the I/O buffer  11   a.  As shown in the detailed configuration of FIG. 4, the gate signal generating circuit  42  has NAND gates G 1 -G 6 , NOR gates G 7 -G 9  and inverters IV 1 -IV 19 .  
         [0057]    The outputs PGTn 0 -PGTn 3  and NGTp 0 -NGTp 3  of the gate signal generating circuit  42  are inputted to gate terminals of transistors in the transistor groups  41   a - 41   d,  respectively.  
         [0058]    [0058]FIG. 5 is a logic diagram of the address signals A 1  and A 6 , and the outputs PGTn 0 -PGTn 3  and NGTp 0 -NGTp 3  of the control signal generating circuit. As shown in FIG. 5, if the address signals A 1  and A 6  are in low level, three transistor groups  41   a,    41   b  and  41   c  in the I/O buffer  11   a  operates, and driving ability of the I/O buffer  11   a  becomes the state of “default”.  
         [0059]    If the address signal Al is in high level and the address signal A 6  is low level, four transistor groups  41   a,    41   b,    41   c  and  41   d  in the I/O buffer  11   a  operate, and driving ability of the I/O buffer  11   a  becomes the state of “strong”.  
         [0060]    If the address signal A 1  is in low level, and the address signal A 6  is in high level, two transistor groups  41   a  and  41   b  in the I/O buffer  11   a  operates. In this case, the driving ability of the I/O buffer  11   a  becomes the state of “weaker”.  
         [0061]    If the address signals A 1  and A 6  are in high level, only the transistor group  41   a  in the I/O buffer  11   a  operates, and the driving ability of the I/O buffer  11   a  becomes the state of “weakest”.  
         [0062]    Although FIGS. 4 and 5 has shown the internal configuration of the I/O buffer  11   a,  the I/O buffer  11   b  has also the same configuration.  
         [0063]    [0063]FIG. 6 is a diagram showing timing between the DQS and the DQ outputted from the I/O buffers  11   a  and  11   b  in the case of delaying the DQS signal by lengthening the trace length of the data strobe signal DQS in regard to the data signal DQ, and driving the DQS signal with the driving ability optimum to the trace length.  
         [0064]    As shown in FIG. 6, the memory  1  of the present embodiment outputs the DQ and the DQS with timing in which the logic of the DQS changes at the vicinity of the center of the valid period of the DQ.  
         [0065]    Because of this, even if phase adjustment of the DQ and the DQS is not performed, it is possible to surely acquire the DQ at the edge of the DQS in the controller  2 .  
         [0066]    In the above mentioned FIGS. 3 and 4, the internal configuration of the I/O buffer  11   a  has been described. However, the I/O buffer  11   b  has also the same configuration. It is possible to variably control the driving ability of the I/O buffer  11   b  by the external address signals A 2  and A 5 .  
         [0067]    Thus, according to the present embodiment, the driving ability of the I/O buffer  11   a  for outputting the DQ and the driving ability of the I/O buffer  11   b  for outputting the DQS are variably controlled separate from each other. Because of this, as a example, by extending the trace length, it is possible to easily output the DQ and the DQS at timing when the logic of the DQS changes at the vicinity of the center of the data valid period of the DQ. Accordingly, it is unnecessary to perform a complicated timing adjustment of the DQ and the DQS in the controller  2  for transferring data to the memory  1 , thereby simplifying the internal configuration of the controller  2 .  
         [0068]    Furthermore, according to the present embodiment, the driving ability of the I/O buffers  11   a  and  11   b  is set by using a potion of the external address signals for designating the addresses of the memory  1 . Because of this, a dedicated terminal for setting the driving ability is unnecessary.