Abstract:
A self-calibrating circuit of a high speed comparator, having a first negative phase logic switch, a second negative logic switch, a first positive phase logic switch, a second positive phase logic switch, a third negative phase logic switch, a fourth negative phase logic switch, a third positive phase logic switch, a fourth positive phase logic switch, a fifth positive phase logic switch, a first current source circuit, a second current source circuit and a control logic circuit. Using the first and the second current source circuits, a self-calibration can be performed while the high speed comparator is just turned on, so that the input offset voltage of the high speed comparator can be eliminated.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefit of Taiwan application Ser. No. 89127056, filed Dec. 18, 2000. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates in general to a comparator. More particularly, this invention relates to a comparator having the self-calibration function of eliminating the input offset voltage. 
     2. Description of the Related Art 
     In various kinds of analog/digital converters (ADC) such as flash ADC, interpolation ADC, pipeline ADC and two-step ADC, a high speed comparator is often required to fulfill the requirements of high speed operation of the digital circuit. 
     FIG. 1 shows a circuit diagram of a conventional comparator. In FIG. 1, a PMOS latchp 1   114 , a PMOS latchp 2   112 , an NMOS latchn 1   120  and an NMOS latchn 2   118  are a set of regeneration stage circuits in the comparator  128 . A PMOS resetp 1   116  and a PMOS resetp 2   110  are a set of reset circuits. An NMOS minm  122  and an NMOS minp  124  are a set of analog signal amplifiers, and an NMOS strb  126  is a switch determining whether the current of the whole comparator  128  is conducted. 
     In FIG. 1, when the low level latch signal is input from the latch terminal of the comparator  128 , the NMOS strb  126  is open, and the NMOS resetp 1   116  and the PMOS resetp 2   110  are conducted. Thus, the output terminals outp and outm are reset to a voltage of vdda. When a high level latch signal is input from the latch terminal of the comparator  128 , the NMOS strb  126  is conducted, and the NMOS resetp 1   116  and the PMOS resetp 2   110  are open. Therefore, the PMOS latchp 1   114 , the PMOS latchp 2   112 , the NMOS latchn 1   120  and the NMOS latchn 2   118  are regenerating. The input analog signal at the input terminal inp of the NMOS minp  124  is compared to the input analog signal at the input terminal inm of the NMOS minm  122  until the potential levels between the output terminals outp and outm are distinguished from each other. 
     If mismatch occurs to the NMOS minm  122  and the NMOS minp  124 , or to the PMOS latchp 1   114 , the PMOS latchp 2   112 , the NMOS latchn 1   120  and the NMOS latchn 2   118  of the regeneration circuit, a large input offset voltage is caused at the input terminals inp and inm. The accuracy of the comparator  128  is thus seriously affected. In the actual circuit design, one can increase the transistor size to reduce the degree of mismatch, however the fabrication cost is raised, the power consumption is increased, and the operation speed is reduced (since the parasitic capacitance is increased). 
     SUMMARY OF THE INVENTION 
     The invention provides a self-calibrating circuit of a high speed comparator. The self-calibrating circuit provides a self-calibration when the comparator is just turned on to eliminate the input offset voltage of the comparator. 
     The self-calibrating circuit of the high speed comparator is supplied with a power by a first and a second voltage source. The self-calibrating circuit comprises a latch control terminal, a first analog input terminal, a second analog input terminal, a first digital output terminal and a second digital terminal. The latch control terminal receives a latch signal, the first analog input terminal receives a first analog signal, the second analog input terminal receives a second analog signal. The first digital output terminal outputs a first digital signal, the second digital output terminal outputs a second digital signal. 
     The self-calibrating circuit further comprises first to fourth negative phase logic switches, first to fifth positive phase logic switches, a first and a second current source circuits, and a control logic circuit. The first negative phase logic switch comprises a power source terminal coupled to the first voltage source, a load terminal coupled to the first digital output terminal, and a control terminal coupled to the latch control terminal. The second negative phase logic switch comprises a power source terminal coupled to the first voltage source, a load terminal coupled to the first digital output terminal, and a control terminal coupled to the second digital output terminal. The first positive phase logic switch comprises a power source terminal coupled to the first digital output terminal, a control terminal coupled to the second digital output terminal, and a load terminal. The second positive phase logic switch comprises a power source terminal coupled to the load terminal of the first positive phase logic switch, a control terminal coupled to the first analog input terminal, and a load terminal. The third negative phase logic switch comprises a power source terminal coupled to the first voltage source, a load terminal coupled to the second digital output terminal, and a control terminal coupled to the latch control terminal. The fourth negative logic switch comprises a power source coupled to the first voltage source, a load terminal coupled to the second digital output terminal, and a control terminal coupled to the first digital output terminal. The third positive phase logic switch comprises a power source terminal coupled to the second digital output terminal, a control terminal coupled to first digital output terminal, and a load terminal. The fourth positive output terminal comprises a power source terminal coupled to the load terminal of the third positive phase logic terminal, a load terminal coupled to the load terminal of the second positive phase logic switch, and a control terminal coupled to the second analog input terminal. The fifth positive phase logic switch comprises a power source terminal coupled to the load terminal of the second positive phase logic switch, a load terminal coupled to the second voltage source, and a control terminal coupled to the latch control terminal. The first current source circuit comprises a power source terminal coupled to the first voltage source, a load terminal coupled to the load terminal of the first positive phase logic switch, and a control terminal. The second current source circuit comprises a power source terminal coupled to the first voltage source, a load terminal coupled to the load terminal of the third positive phase logic switch, and a control terminal. The control logic circuit comprises a calibration control terminal to receive a calibration signal, a latch signal input terminal, a first data output terminal, a second output terminal and a digital signal input terminal. The latch signal input terminal is coupled to the latch control terminal. The first data output terminal is coupled to the data control terminal of the first current source circuit. The second data output terminal is coupled to the data control terminal of the second current source circuit. The digital signal input terminal is coupled to the first digital output terminal. 
     Using the above self-calibrating circuit in a high speed comparator comprising the first current source circuit, the second current source circuit and the control logic circuit, a self-calibration is performed within a very short time after the high speed comparator is turned on. Therefore, the input offset voltage of the high speed comparator can be eliminated. 
     Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of a conventional comparator; 
     FIG. 2 shows a circuit diagram of a high speed comparator according to the invention; 
     FIG. 3A shows a circuit diagram of the high speed comparator in a self-calibration status according to the invention; and 
     FIG. 3B shows a circuit diagram of the high speed comparator in a normal operation condition according to the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 2, an embodiment of a high speed comparator according to the invention is illustrated. In FIG. 2, the voltage source vdda and the voltage source vssa provide power to the high speed comparator  228 . The high speed comparator  228  has a latch control terminal latch, an analog input terminal inm, an analog input terminal inp, a digital output terminal outp, and a digital output terminal outm. The lath control terminal latch receives a latch signal. The analog input terminals inm and inp receive different analog signals. The digital output terminals outp and outm output complementary digital signals. 
     The comparator  228  comprises a PMOS resetp 2   210 , a PMOS latchp 2   212 , an NMOS latchn 2   218 , an NMOS minm  222 , a PMOS resetp 1   216 , a PMOS latchp 1   214 , an NMOS latchn 1   220 , an NMOS minp  224 , an NMOS strb  226 , a current source circuit DAC_M  230 , and a current source circuit DAC_P  232 . The PMOS resetp 2   210  comprises a power source terminal (source region) coupled to the voltage source vdda, a load terminal (drain region) coupled to the digital output terminal outp, and a control terminal (gate) coupled to the latch control terminal latch. The PMOS latchp 2   212  comprises a power source terminal coupled to the voltage source vdda, a load terminal coupled to the digital output terminal outp, and a control terminal coupled to the digital output terminal outm. The NMOS latchn 2  comprises a power source terminal (drain region) coupled to the digital output terminal outp, a control terminal (gate) coupled to the digital output terminal outm, and a load terminal (source). The NMOS minm  222  comprises a power source terminal coupled to the load terminal of the NMOS latchn 2   218 . The NMOS minm  222  comprises a control terminal coupled to the analog input terminal inm. 
     The PMOS resetp 1   216  comprises a power source terminal coupled to the voltage source vdda, a load terminal coupled to the digital output terminal outm, and a control terminal coupled to the latch control terminal latch. The PMOS latchp 1   214  comprises a power source terminal coupled to the voltage source vdda, a load terminal coupled to the digital output terminal outm and a control terminal coupled to the digital output terminal outp. The NMOS latchn 1   220  comprises a control terminal coupled to the digital output terminal outp. The NMOS minp  224  comprises a power source terminal coupled to a load terminal of the NMOS latchn 1   220  and a control terminal coupled to the analog input terminal inp. 
     The NMOS strb  226  comprises a power source terminal coupled to a load terminal of the NMOS minm  222 , a load terminal coupled to the voltage source vssa, and a control terminal coupled to the latch control terminal latch. The current source circuit DAC_M  230  comprises a power source terminal coupled to the voltage source vdda, a load terminal coupled to a load terminal of the NMOS latchn 2   218 , and a data control terminal DIN[ 3 : 0 ] to receive a data. The current source circuit DAC_P  232  comprises a power source terminal coupled to the voltage source vdda, a load terminal coupled to the load terminal of the NMOS latchn 1   220 , and a data control terminal DIN[ 3 : 0 ] to receive a data. 
     In FIG. 2, to easily use the digital circuit to calibrate the input offset voltage, a current mode digital-to-analog current converter (current DAC, not shown in FIG. 2) is employed. The magnitude of current flowing into the high speed comparator  228  from the current source circuits DAC_M  230  and DAC_P  232  is controlled by the input data. The input offset voltages of the analog input terminals inm and inp of the high speed comparator  228  are thus varied. Meanwhile, the currents output from the current source circuits DAC_M  230  and DAC_P  232  are inversely proportional. That is, when current flowing from the current source circuit DAC_M  230  increases a certain amount, the current flowing from the current source circuit DAC_P  232  decreases the exact amount that the current source circuit DAC_M  230  increases. 
     Using the circuit as shown in FIG. 2 as an example, assuming that the voltage of the analog input terminal inp is higher than the voltage of the analog input terminal inm, the input data causes the current flowing from the current source circuit DAC_M  230  to increase. As a result, the voltages at the power source terminal and the control terminal of the NMOS minm  222  rise, that is, the analog input terminal inm is pulled up. In contrast, this input data causes the current flowing from the current source circuit DAC_P  232  to decrease. Consequently, the voltages of the power source terminal and the control terminal of the NMOS minp  224  are lowered, that is, the voltage of the analog input terminal inp is dropped. Thus, only by adjusting the data input to the current source circuits DAC_M  230  and DAC_P  232 , can the input offset voltages of the analog input terminals inm and inp be eliminated. 
     FIG. 3A is a block diagram of a self-calibrating circuit of a high speed comparator. The high speed comparator  302  is a simplified form of the high speed comparator as shown in FIG. 2. A control logic circuit  304  comprises a calibration terminal calibration to receive a calibration signal, a latch signal input terminal coupled to the latch control terminal of the high speed comparator  302 , a first data output terminal, a second data output terminal and a digital signal input terminal. The first data output terminal is coupled to the data control terminal DIN[ 3 : 0 ] of the current source circuit DAC_M 230  (as shown in FIG.  2 ). The second data output terminal is coupled to the data control terminal DIN[ 3 : 0 ] of the current DAC_P  232  (as shown in FIG.  2 ). The digital signal input terminal is coupled to the digital output terminal outp of the high speed comparator  302 . 
     In this embodiment, the comparator is designed to perform a self-calibration operation a short period of time after power on. The method of calibration is described as follows. 
     When the calibration control terminal of the control logic circuit  304  receives a calibration signal “H” from an external circuit, it indicates that the high speed comparator  302  is performing a self-calibration operation. Meanwhile, the analog input terminals inp and inm receive a reference voltage vref simultaneously. As the voltages of both the analog input terminals inp and inm are the same, the digital output terminal outp is “H” or “L” under the ideal condition (that is, the input offset bias voltage is zero). That is, digital output terminal outp is at a high or low voltage level with a probability of ½ for each one. Meanwhile, the data output from the first data output terminal of the control logic circuit  304  to the current source circuit DAC_M  230  is [1000] (a four-digital data is used as an example in this embodiment). The data output from the second data output terminal of the control logic circuit  304  to the current source circuit DAC_P  232  is also [1000]. It is shown that the currents flowing from the current source circuits DAC_M  230  and DAC_P  232  are the same. 
     If input offset voltage occurs to the analog input terminals inp and inm, and assuming the digital output terminal outp is “H”, the latch signal input terminal of the control logic circuit  304  continuously receives four latch signal clocks (the embodiment uses 4 clock time as an example), the signal output from the digital output terminal outp is “H”, and the data output from the second data output terminal causes an increase of current flowing from the current source circuit DAC_P  232  (referring to FIG.  2 ). Meanwhile, the current flowing from the first data output terminal of the control logic circuit  304  is decreased. Thus, the input offset voltage of the analog input terminal inp and inm is calibrated. By iterating the same procedure for a period of time, the digital output terminal outp of the high speed comparator  302  outputs an “L” signal. The data of the data control terminals DIN[ 3 : 0 ] of the current source circuits DAC_M  230  and DAC_P  232  are at a certain value, for example, the data of the data control terminal DIN[ 3 : 0 ] of the current source circuit DAC_M  230  is [1101]. After a period to time, for example, 1024 clock cycles, the calibration operation stops, and the calibration of the input offset voltage of the analog input terminals inp and inm is complete. 
     FIG. 3B illustrates the self-calibrating circuit of the high speed comparator under the normal operation condition. In FIG. 3B, when the calibration signal received by the calibrating control terminal from an external circuit is converted from “H” to “L”, the high speed comparator  312  is operated under a normal operation condition. The analog input terminals inp and inm of the high speed comparator  312  receive different analog signals to compare. The comparison result is output from the digital output terminal outp to a next circuit block (not shown). Meanwhile, the first and second data output terminals of the control logic circuit  314  output constant data to the current source circuits DAC_M  230  and DAC_P  232 , respectively. The latch signal input terminal of the control logic circuit  314  no longer receives the latch signal (equivalent to an open status), and the digital input terminal stops receiving the digital signal output from the digital output terminal outp. The control logic circuit  314  is in an idle status. 
     The invention provides a self-calibrating circuit of a high speed comparator. Two current source circuits and a control logic circuit are used. A self-calibrating step is performed after a short period of time after the high speed comparator is on. The input offset voltage of the high speed comparator is thus eliminated. 
     Other embodiments of the invention will appear to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples to be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.