Abstract:
A semiconductor device including at least one contact pad disposed on an edge thereof. The semiconductor device may also include a protective overcoat layer. The present invention also includes a method of fabricating the semiconductor device, including forming disconnected notches in a semiconductor wafer, redirecting circuit traces into each of the notches, and singulating the semiconductor wafer along the notches to form bond pads on the edges of the resultant semiconductor devices. A method of attaching the semiconductor device to a carrier substrate includes orienting the semiconductor device nonparallel to a carrier substrate and establishing at least one electrical connection between the semiconductor device and the carrier substrate.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a divisional of application Ser. No. 10/132,429, filed Apr. 25, 2002, pending, which is a continuation of application Ser. No. 09/660,782, filed Sep. 13, 2000, now U.S. Pat. No. 6,410,406, issued Jun. 25, 2002, which is a continuation of application Ser. No. 09/001,404, filed Dec. 31, 1997, now U.S. Pat. No. 6,235,551, issued May 22, 2001. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to vertically mountable, bare or minimally packaged semiconductor dice. In particular, this invention relates to semiconductor dice having bond pads on an edge thereof. More particularly, a preferred semiconductor device according to the present invention has all of its bond pads distributed along a single edge thereof. In use, upon vertical orientation and alignment of the semiconductor device upon a carrier substrate, an electrically conductive material establishes an electrical connection between each bond pad and a corresponding terminal of the carrier substrate. 
     2. State of the Art 
     The direct attachment of a semiconductor device to a circuit board is known in the art as chip-on-board technology. Semiconductor dice that are directly mountable to a circuit board typically include bond pads adjacent more than one edge thereof or in an area array over the active surface thereof. Methods for attaching dice directly to a circuit board include flip-chip technology and tape automated bonding. Typically, when such techniques are employed, a semiconductor device which includes bond pads on the active surface thereof is oriented over the circuit board and substantially parallel thereto so that an electrical connection will be established between the semiconductor device and the circuit board. After connecting such a semiconductor device to a circuit board, a protective coating may be applied over the semiconductor device. 
     However, the placement of a semiconductor device directly against a circuit board is somewhat undesirable in that, due to the parallel orientation of the semiconductor device relative to the circuit board, and the typical placement of the semiconductor device&#39;s active surface against the circuit board, the heat must pass through both the circuit board and the semiconductor device in order to transfer away from the semiconductor device. Thus, the transfer of heat away from the semiconductor device is relatively slow. The horizontal orientation of the semiconductor device also consumes a great deal of area or “real estate” on the circuit board. Moreover, chip-on-board attachments are typically permanent, making them somewhat undesirable from the standpoint that they are not readily user-upgradeable. 
     Vertical surface mount packages are also known in the art. When compared with traditional, horizontally mountable semiconductor packages and chip-on-board devices, many vertical surface mount packages have a superior ability to transfer heat away from the semiconductor device. Vertical surface mount packages also consume less area on a circuit board than a horizontally mounted package of the same size. Thus, many skilled individuals in the semiconductor industry are finding vertical surface mount packages more desirable than their traditional, horizontally mountable counterparts. 
     The following United States Patents disclose various exemplary vertical surface mount packages: U.S. Pat. No. Re. 34,794, issued to Warren M. Farnworth on Nov. 22, 1994; U.S. Pat. No. 5,444,304, issued to Kouija Hara and Jun Tanabe on Aug. 22, 1995; U.S. Pat. No. 5,450,289, issued to Yooung D. Kweon and Min C. An on Sep. 12, 1995; U.S. Pat. No. 5,451,815, issued to Norio Taniguchi et al. on Sep. 19, 1995; U.S. Pat. No. 5,592,019, issued to Tetsuya Ueda et al. on Jan. 7, 1997; and U.S. Pat. No. 5,635,760, issued to Toru Ishikawa on Jun. 3, 1997. 
     Many vertical surface mount packages are somewhat undesirable in that they include leads which operatively connect a semiconductor device to a circuit board. The leads of such vertical surface mount packages tend to increase the impedance and decrease the overall speed with which the semiconductor device conducts electrical signals. Moreover, the packaging of many such vertical surface mount packages adds to their undesirability. Typically, packaging requires multiple additional manufacturing steps, which translates into increased production costs. The packaging of many vertical surface mount packages also tends to consume a substantial amount of area on the circuit board. Moreover, many vertical surface mount packages are not user-upgradeable. 
     Some electronic devices have electrical contacts disposed on the edges thereof. Typically, such contacts are formed by drilling a hole through the substrate. The hole, or at least the perimeter thereof, is then filled with an electrically conductive material. Solders, molten metals and other electrically conductive materials are useful for filling the holes and forming the electrical contacts. When the substrate is separated into distinct boards or dice, the contacts are divided such that they are located on the edge of the distinct boards or dice. Such devices are illustrated and described in the following United States patents: U.S. Pat. No. 5,266,833 (the “&#39;833 patent”), issued to David F. Capps on Nov. 30, 1993; U.S. Pat. No. 5,471,368 (the “&#39;368 patent”), issued to Alan P. Downie et al. on Nov. 28, 1995; and U.S. Pat. No. 5,635,670 (the “&#39;670 patent”), issued to Kenji Kubota et al. on Jun. 3, 1997. 
     The &#39;833 patent also describes semiconductor dice having bond pads on the edges thereof. Such bond pads are formed by disposing a grid of “thin electrically conductive wires 14 formed of a suitable electrical conductive material, such as copper or gold, . . . in a semiconductor material during the growth of a semiconductor crystal 16.” (Col. 4, lines 32-36.) 
     In order to achieve appropriate bond pad placement, great consistency and accuracy are required in the orientation of the conductive wires during formation of the silicon ingot, singulation of the wafer, and fabrication of circuit traces on each semiconductor device. However, because the silicon is transferred after being sawed into wafers, it is somewhat difficult to maintain such consistency and accuracy in the placement of the wires. Further, such a method of forming edge-bound bond pads does not permit varying the bond pad placement on different wafers cut from the same ingot. U.S. Pat. No. 5,668,409 (the “&#39;409 patent”), issued to Stephen Joseph Gaul on Sep. 16, 1997, discloses a vertically mountable, bare semiconductor die which includes bond pads along the edge thereof. The &#39;409 patent discloses vertical mounting of that device to a circuit board by solder reflow techniques. However, that device is somewhat undesirable in that fabrication thereof requires several additional steps relative to the fabrication of typical chip-on-board semiconductor devices. The requirement of additional fabrication steps and the related requirement of additional fabrication materials increase the manufacturing cost of such semiconductor devices. Moreover, the disclosed use of solder reflow techniques to attach the semiconductor device of the &#39;409 patent to a circuit board prohibits users from readily upgrading or otherwise replacing that semiconductor device. 
     Thus, a vertically mountable bare semiconductor device is needed which has reduced impedance relative to devices in the prior art, has good thermal conductivity, consumes less area or “real estate” on a circuit board, and is user-upgradeable. A method of fabricating a semiconductor device with bond pads in select positions on the edges thereof with fewer steps is needed. A method of directly mounting an edge-bumped semiconductor device perpendicularly relative to a carrier substrate is also needed. 
     BRIEF SUMMARY OF THE INVENTION 
     The vertically mountable, edge-bumped semiconductor device of the present invention addresses each of the foregoing needs. 
     The semiconductor device of the present invention includes bond pads disposed on the edges thereof. More preferable, the bond pads are disposed on a single edge of the semiconductor device. Placement of the bond pads on an edge of the semiconductor device facilitates direct vertical mounting of the semiconductor device to a carrier substrate. Thus, when such a semiconductor device is mounted perpendicularly relative to a carrier substrate, packaging and leads are not necessary to establish an electrical connection between the bond pads and the corresponding terminals on the carrier substrate. The direct connection between the bond pads of the semiconductor device and carrier substrate terminals also imparts the semiconductor device of the present invention with low impedance. 
     A fabrication method according to the present invention includes creating notches in a semiconductor wafer in locations where bond pads are desired and redirecting a circuit trace into selected notches. A protective overcoat may also be formed over the active surfaces of the dice. The metalized notches may be filled with a solder ball, other metal member or other electrically conductive material. The wafer is singulated along each of the metalized notches to form bond pads on the edges of each resultant semiconductor device. 
     An alignment device, which attaches the semiconductor device to a carrier substrate, includes a body which defines at least one slot therein, into which a semiconductor device is insertable. The alignment device may also include a mechanism for biasing the semiconductor device against a carrier substrate. Preferably, each slot is wider at its top opening than at its bottom opening, which abuts the carrier substrate, in order to facilitate insertion of a semiconductor device therein. The mechanism for biasing establishes and maintains electrical contact between the bond pads of the semiconductor device and the corresponding contacts of the carrier substrate. 
     Other advantages of the present invention will become apparent through a consideration of the appended drawings and the ensuing description. 
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
     FIG. 1 a  is a perspective view of a first embodiment of a semiconductor device according to the present invention; 
     FIG. 1 b  is a cross-section taken along line  1   b — 1   b  of FIG. 1 a;    
     FIGS. 2 a  through  2   f  are cross-sectional views which illustrate a method of fabricating the semiconductor device of FIG. 1 a;    
     FIG. 3 is a perspective view of a singulated semiconductor wafer including bumped bond pads on the edges of the semiconductor dice thereof; 
     FIG. 4 a  is an assembly view of the semiconductor device of FIG. 1 a , an alignment device for orienting the semiconductor device relative to a carrier substrate, the carrier substrate, and a cover which may be disposed over the alignment device; 
     FIG. 4 b  is a cross-section of the alignment device, taken along line  4   b — 4   b  of FIG. 4 a , which illustrates an embodiment of attachment of the semiconductor device to a carrier substrate; and 
     FIG. 5 is a schematic representation of the semiconductor device in a computer. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIGS. 1 a  and  1   b  illustrate a semiconductor device  10  according to the present invention, which includes bond pads  12  disposed along a single edge  16  thereof. Thus, during the fabrication of semiconductor device  10 , bond pads  12  are redirected to edge  16 . Methods and mechanisms which are known to those of ordinary skill in the art are useful for manufacturing semiconductor device  10  and fabricating circuit traces which lead to bond pads  12 . Preferably, the fabrication steps which precede the formation of the circuit traces that lead to the bond pads are unchanged from their equivalent steps in the fabrication of prior art semiconductor dice. Thus, existing semiconductor designs are useful in the semiconductor device with little reconfiguration. 
     Semiconductor device  10  may include a standardized number of bond pads  12  which are laterally spaced from one another at a standardized pitch, and which may be positioned at a specific location relative to a center line  18  of the semiconductor device, or relative to any other landmark on the semiconductor device, such as a side thereof. Alternatively, the pitch and number of bond pads may be nonstandardized. The placement of bond pads  12  on edge  16  imparts semiconductor device  10  with reduced impedance as the bond pads are electrically connected to a carrier substrate (reference character  40  of FIG.  4 ), relative to many vertical surface mount packages and other packaged semiconductor devices in the prior art. 
     Preferably, each bond pad  12  includes a bump  14   a ,  14   b ,  14   c , etc. (collectively bumps  14 ), respectively, formed thereon. Bumps  14   a ,  14   b ,  14   c , etc. are preferably formed from gold, gold alloy, or a lead-based solder. 
     FIGS. 2 a  through  2   f  illustrate a first method of fabricating bond pads along the edge of semiconductor device  10 . With reference to FIG. 2 a , one or more disconnected notches  22  are formed in the active surface  21  of a semiconductor wafer  20 . Preferably, notches  22  are formed only in locations upon semiconductor wafer  20  where bond pad placement is desired. Notches  22  are preferably formed by masking and silicon etching techniques that are known in the art, including, without limitation, photolithographic and plasma etching processes. 
     Preferably, a first protective layer of silicon dioxide (SiO 2 )  23  is formed over active surface  21  of each semiconductor device  10  of semiconductor wafer  20  by techniques that are known in the art. The SiO 2  layer  23  is then selectively etched at locations where electrical connection to circuit traces (described below) is desired. 
     Referring now to FIG. 2 b , circuit traces  24  are repatterned along active surface  21  of each semiconductor device  10  and into each notch  22 . Preferably, circuit traces  24  are formed from aluminum, aluminum alloys, titanium tungsten (Ti:W) alloys, platinum, refractory metal suicides or other metals or metal alloys by sputtering techniques, which are known in the art. 
     As FIG. 2 c  illustrates, a second protective layer, or protective overcoat  26  is then formed over semiconductor wafer  20 . Preferably, protective overcoat  26  has a thickness of from about 5 microns to about 25 microns to impart strength and support to semiconductor device  10 . Protective overcoat  26  is preferably a layer of polyimide, acrylate, epoxy potting compound, acrylic, silicone, polyurethane, another resin, or another protective coating material. Preferably, protective overcoat  26  is formed on or applied to semiconductor device  10  by methods which are known in the art, including, but not limited to, spin coating, spraying, flow coating, brush coating, and known polyimide application techniques. 
     Turning now to FIG. 2 d , when protective overcoat  26  is formed from a material which is not readily removable from notches  22  following deposition and/or curing, a mask is employed to prevent the overcoat material from entering or curing in the notches. Thus, the protective overcoat forms a bond pad opening  28  around each notch  22 . Polyimide layers may be applied over the entire active surface  21  of semiconductor wafer  20 , removed from notches  22  by known photolithography methods to create bond pad openings  28  around each notch, then cured. 
     With reference to FIG. 2 e , each notch  22  may be filled with an electrically conductive material, which is referred to as a conductive bump  29 . Conductive bump  29  may be formed from solder (preferably a lead-based solder), gold, gold alloy or another electrically conductive material. Conductive bump  29  is formed by methods which are known in the art, including, without limitation, screen printing, stencil printing or pressure dispensing of solder pastes, solder reflow techniques, wave soldering, condensation soldering, infrared soldering, conductive soldering, and other solder processes. 
     Alternatively, protective overcoat  26  may be applied following the formation of conductive bumps  29  in each notch  22 . 
     FIGS. 2 f  and  3  depict a singulated semiconductor wafer  30 . Semiconductor wafer  30  is preferably singulated by sawing. During singulation of semiconductor wafer  30 , several semiconductor devices  10  and  10 ′ are formed, having adjacent edges  16  and  16 ′. Conductive bump  29  is also severed, forming bond pads  12  and  12 ′ on edges  16  and  16 ′, respectively. 
     Referring to FIGS. 4 a  and  4   b , an alignment device  42  supports one or more semiconductor devices  10  relative to a carrier substrate  40 . Alignment device  42  has one or more slots  44  formed completely therethrough (i.e., each slot opens to both the top and bottom surfaces of the alignment device). Preferably, each slot  44  tapers outward towards the top portion thereof, such that the top of the slot is the largest portion thereof. Thus, the taper facilitates the insertion of a semiconductor device  10  into slot  44 . Preferably, an electrically conductive material  46 , such as a z-axis elastomer or a solder joint, is positioned at the bottom of slot  44 , against carrier substrate  40 , to establish an electrical connection between each bond pad  12  of semiconductor device  10  and its respective terminal  41  on the carrier substrate  40 . 
     Preferably, the total side tolerance between semiconductor device  10  and slot  44  is about 10 mils to about 40 mils, such that the semiconductor device is readily insertable into and removable from the slot. Nevertheless, due to carrier substrate “real estate” consumption considerations, alignment device  42  should be, preferably, as narrow as possible. As a semiconductor device  10  is inserted into alignment device  42 , downward pressure on the semiconductor device against electrically conductive material  46  biases the semiconductor device relative to the electrically conductive material to establish an electrical connection between the bond pads  12  of the semiconductor device and their respective terminals  41 . Alternatively, each slot  44  may be adapted to receive a plurality of dice. 
     Alignment device  42  may also include a cover  48 , which encloses semiconductor device  10  disposed within slot  44 . Cover  48  may also be adapted to bias semiconductor device  10  against carrier substrate  40  to maintain the electrical connection between bond pads  12  and their respective terminals  41 . 
     Preferably, alignment device  42  is manufactured from a material with good thermal conductivity, including, without limitation, copper, aluminum, other metals, metal alloys, and ceramics. 
     FIG. 5 illustrates a computer  50  including a carrier substrate  52 . Alignment device  42  is attached to carrier substrate  52 . One or more semiconductor devices  10  are inserted into alignment device  42  and biased against electrically conductive material  46  in order to establish an electrical connection between the devices and the carrier substrate. Thus, with the attachment of a semiconductor device  10  to carrier substrate  52 , the semiconductor device is operatively incorporated into computer  50 . 
     The vertically mountable, edge-bumped semiconductor device of the present invention includes several advantageous features. The placement of bond pads on a single edge of the semiconductor device eliminates the need for leads between the bond pads and their respective terminals on a carrier substrate. Thus, the semiconductor device has reduced impedance relative to many devices in the prior art. The vertical orientation of the semiconductor device relative to a substrate imparts the semiconductor device with good thermal transferability and consumes relatively little area or “real estate” on the carrier substrate. The protective overcoat supports the semiconductor device and strengthens it as it is biased against a carrier substrate to establish an electrical contact between the semiconductor device and the carrier substrate. The fabrication method facilitates selection of the bond pad sites on a semiconductor device and may be performed in relatively few steps. 
     Although the foregoing description contains many specificities, these should not be construed as limiting the scope of the present invention, but merely as providing illustrations of selected presently preferred embodiments. Similarly, other embodiments of the invention may be devised which do not depart from the spirit or scope of the present invention. The scope of this invention is, therefore, indicated and limited only by the appended claims and their legal equivalents, rather than by the foregoing description. All additions, deletions and modifications to the invention as disclosed herein which fall within the meaning and scope of the claims are embraced within their scope.