Abstract:
A digital to analog converter includes a coarse resolution resistor circuit ( 11 ) coupled between a first voltage (Vin) and an intermediate voltage (V 0 ) to produce coarse resolution node voltages (V 0 , . . . V 240 ), and also includes a fine resolution resistor circuit ( 20 ) coupled between the intermediate voltage and a second voltage (GND). One of the coarse resolution node voltages is selected in response to a group of MSB bits of a digital input (D 0,1  . . . ) to produce a first output voltage (Vout 2 ), and one of the fine resolution node voltages is selected in response to group of LSB bits of the digital input to produce a second output voltage (Vout 1 ), the second output voltage (Vout 1 ) and the first output voltage (Vout 2 ) providing a differential analog output signal (Vout 1 −Vout 2 ). In one embodiment, the coarse resolution and fine resolution resistor circuits are string resistor circuits, and in another embodiment they are modified R-2R networks.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
   This application claims the benefit of prior filed U.S. provisional application Ser. No. 60/863,503 filed Oct. 30, 2006, entitled “DAC WITH REDUCED SWITCH COUNT AND A SMALL OUTPUT IMPEDANCE”, by Dimitar T. Trifonov and Jerry L. Doorenbos, and incorporated herein by reference. 

   BACKGROUND OF THE INVENTION 
   The present invention relates generally to string DACs (digital to analog converters), and more particularly to string DAC architectures having a reduced number of resistors and switches, reduced output impedance, and reduced output impedance range. 
   Typically, an N-bit resistor string DAC includes 2 N  resistors and from 2 N  or more switches, depending on the complexity of the decoder. Thus, a 10-bit string resistor DAC would include 1024 resistors and at least 1024 switches which require a large amount of integrated circuit area. A large amount of digital decode circuitry for controlling the large number of switches also is required. The integrated circuit chip area increases rapidly with the number of bits. Furthermore, the string resistor DAC speed is reduced by parasitic capacitances associated with the large number of switches. 
   There are various references that deal with ways to reduce the number of switches in a string DAC. A reference representative of the closest prior art is believed to be commonly owned U.S. Pat. No. 5,808,576 “Resistor-String Digital-to-Analog Converter” issued Sep. 15, 1998 to Chloupek et al. This patent discloses a digital to analog converter including a first array of resistors connected in series, a switch matrix coupled to the first array, a first variable resistor coupled to a first end of the first array of resistors, and a second variable resistor coupled to a second end of the first array of resistors. The first variable resistor and the second variable resistor have a combined resistance that has a fixed value. 
     FIG. 1  shows a typical 10-bit string DAC  1  including a resistor string  2  having 1024 series-connected identical resistors R 0 , 1  . . .  1023 , 1024 switches SW 0 , 1  . . .  1023 , and a digital decoder  4  which decodes the 10 digital inputs D 0 , 1  . . .  9 . Decoder  4  produces signals on control lines  5 - 0 , 1  . . .  1023  which are connected to control terminals of switches SW 0 , 1  . . .  1023  to select one of the 1024 node voltages on conductors  6 - 0 , 1 , 2  . . .  1023 . One terminal of each of switches SW 0 , 1  . . .  1023  is connected to one of conductors  6 - 0 , 1 , . . .  1023 , respectively, and the other terminal of each of switches SW 0 , 1  . . .  1023  is connected to conductor  7 , on which Vout is produced. Switches SW 0 , 1  . . .  1023  can be N-channel transistors, or they can be CMOS transmission gates, in which case each of the control lines  5 - 0 , 1  . . .  1023  includes two conductors conducting logical complement control signals to the N-channel transistor and the P-channel transistor, respectively, which comprise each transmission gate. 
   For use in conjunction with switched capacitor circuits, it is desirable that a DAC having a differential output signal present the same output impedance on both output conductors. The terminal to which Vin is applied and the terminal which in  FIG. 1  is illustrated as being a ground conductor can be differential input terminals of DAC  1 . For example, a differential input voltage Vin=Vin+−Vin− can be applied to DAC  1  wherein Vin+ is applied to the upper terminal of resistor R 1023  and input signal Vin− is applied to conductor  6 - 0 . 
   A drawback of string DAC  1  of  FIG. 1  is that it requires such large numbers of switches and series-connected string resistors, i.e., 1024 switches and 1024 resistive segments or string resistors. Furthermore, an undesirably large amount of digital decode circuitry is required. Therefore, the amount of required integrated circuit area is relatively large, resulting in high integrated circuit cost for string resistor DAC  1 . Another drawback of conventional string resistor DAC  1  is that it has a large magnitude output impedance, the value of which varies over a wide range with respect to the DAC input code D 0 , 1  . . .  9 . This is a serious problem in many applications, because that causes settling times of associated switched capacitor circuits to also be dependent on the DAC input code. 
   Thus, there is an unmet need for a string resistor DAC having a substantially reduced number of resistors and switches. 
   There also is an unmet need for a string resistor DAC having reduced output impedance. 
   There also is an unmet need for a string resistor DAC having a reduced output impedance range. 
   There also is an unmet need for a string resistor DAC in which the output impedance is relatively invariant with respect to the value of the digital input number. 
   There also is an unmet need for a string resistor DAC which provides relatively consistent settling times for voltages on sampling capacitors which sample the output of the string resistor DAC. 
   SUMMARY OF THE INVENTION 
   It is an object of the invention to provide a DAC which is based on a string resistor architecture and which requires only a substantially reduced number of resistors and switches compared to the closest prior art. 
   It is another object of the invention to provide a DAC which is based on a string resistor architecture and which has substantially reduced output impedance and also a substantially reduced output impedance range compared to the closest prior art. 
   It is another object of the invention to provide a string resistor DAC having a reduced output impedance range. 
   It is another object of the invention to provide a string resistor DAC in which the output impedance is relatively invariant with respect to the value of the digital input number. 
   It is another object of the invention to provide a string resistor DAC which provides relatively consistent settling times for voltages on sampling capacitors which sample the output of the string resistor DAC. 
   It is another object of the invention to provide a differential output string resistor DAC having relatively constant output impedance on both output conductors to provide relatively consistent settling times of switched capacitor circuits coupled to the output conductors. 
   Briefly described, and in accordance with one embodiment, the present invention provides a digital to analog converter which includes a coarse resolution resistor circuit ( 11 ) coupled between a first voltage (e.g., V 992 , V 240  or Vin−) and an intermediate voltage (V 0 ) to produce coarse resolution node voltages (V 0 , . . . V 240 ,V 992 ), and which also includes a fine resolution resistor circuit ( 20 ) coupled between the intermediate voltage and a second voltage (e.g., GND or Vin−). One of the coarse resolution node voltages is selected in response to a group of MSB bits of a digital input (D 0 , 1  . . . ) to produce a first output voltage (Vout 2 ), and one of the fine resolution node voltages is selected in response to group of LSB bits of the digital input to produce a second output voltage (Vout 1 ), the second output voltage (Vout 1 ) and the first output voltage (Vout 2 ) providing a differential analog output signal (Vout 1 −Vout 2 ). In one embodiment, the coarse resolution and fine resolution resistor circuits are string resistor circuits, and in another embodiment they are modified R-2R networks. 
   In one embodiment, the invention provides a n-bit digital to analog converter for converting a digital input number (D 0 ,  1  . . . (n−1)) to an analog output signal (Vout 1 −Vout  2 ), including a coarse resolution resistor circuit ( 11 ) coupled between a first input voltage (Vin/Vref) and an intermediate voltage (V 0 ) for producing a first number of coarse resolution node voltages (V 0 , . . . (V 240 )). Each coarse resolution node voltage is separated from an adjacent coarse resolution node voltage by a first input voltage increment equal to the difference between the first input voltage (Vin/Vref) and the intermediate voltage (V 0 ) divided by the first number minus 1. A first switching circuit ( 12 ) includes the first number of switches (SW 2 ) each having a first terminal coupled to a corresponding coarse resolution node voltage, respectively, and each having a second terminal coupled to a first output conductor ( 16 ). A coarse resolution decoder ( 14 ) for decoding a second number of most significant bits of the input number (D 0 ,  1  . . . (n−1)) produces switch selection signals applied to control terminals ( 15 - 0 ,  1  . . . ( 31  or  15 )) of the switches (SW 2 ) of the first switching circuit ( 12 ), respectively. A fine resolution resistor circuit ( 20 ) is coupled between the intermediate voltage (V 0 ) and a second input voltage (GND or Yin) for producing a third number of fine resolution node voltages (V 0 ,  1  . . . (V 15  or V 31 )), each fine resolution node voltage being separated from an adjacent fine resolution node voltage by a second voltage increment equal to the difference between the intermediate voltage (V 0 ) and the second input voltage (GND or Vin−) divided by the third number. A second switching circuit ( 20 ) includes the third number of switches (SW 1 ) each having a first terminal coupled to a corresponding fine resolution node voltage, respectively, and each having a second terminal coupled to a second output conductor ( 26 ). A fine resolution decoder ( 23 ) for decoding a fourth number of least significant bits of the input number (D  0 ,  1  . . . (n−1)) produces and applies switch selection signals to control terminals ( 24 - 0 ,  1  . . . ( 31  or  15 )) of the switches (SW 1 ) of the second switching circuit ( 21 ), respectively. An analog output signal (Vout 2  −Vout 1 ) is thereby produced between the second ( 26 ) and first ( 16 ) output conductors. In a described embodiment, the first number and the third number are equal. 
   In one embodiment, the coarse resolution resistor circuit ( 11 ) includes a first string resistor circuit including the first number minus 1 of resistors (R 2 - 1 , 2  . . .  31 ) connected in series between the first input voltage (Vin/Vref or V 240 ) and the intermediate voltage (V 0 ), and the fine resolution resistor circuit ( 20 ) includes a second string resistor circuit including the third number of resistors (R 1 - 0 , 1 , 2  . . .  31 ) connected in series between the intermediate voltage (V 0 ) and the second input voltage (GND or Vin−). 
   In one embodiment, the coarse resolution resistor circuit ( 30 - 2 A) includes a plurality of sequentially connected R-2R sections ( 53 , 52 , 51 , 50 ) all composed of identical resistive links each having a predetermined resistance (R). Each R-2R section includes a R section and a 2R section. The first number of coarse resolution node voltages are produced on various terminals of resistive links in the R sections of the coarse resolution resistor circuit ( 30 - 2 A). A first R section (R 41 ) and a first R-2R section ( 53 ) produce one of the coarse resolution node voltages, and successive adjacent R sections ( 52 , 51 , 50 ) each produce twice as many of the coarse resolution node voltages as the previous R section, respectively. In one embodiment, the fine resolution resistor circuit ( 30 - 2 B) includes a plurality of sequentially connected R-2R sections all composed of identical resistive links each having the predetermined resistance (R) and a termination circuit ( 57 ) including a R section (R 2 ). Each R-2R section of the fine resolution resistor circuit ( 30 - 2 B) includes a R section and a 2R section, wherein the R section (R 2 ) of the termination circuit ( 57 ) is composed of one resistive link, the third number of fine resolution voltage nodes are produced on various terminals of the resistive links in the fine resolution resistor circuit ( 30 - 2 B). The R section (R 2 ) of the termination circuit ( 57 ) produces one of the fine resolution node voltages. Each of the successive adjacent R sections ( 56 , 55 , 54 ) of the fine resolution resistor circuit ( 30 - 2 B) produces twice as many of the fine resolution node voltages as the previous R section, respectively. Each successive adjacent R section of the fine resolution resistor circuit ( 30 - 2 A) also can include additional resistive links arranged so as to cause the resistance of that R section to be equal to the predetermined resistance. 
   In some of the R-2R sections, none of the additional resistive links in any R section is connected directly to any of the fine resolution node voltages produced between the terminals of that R section. In some of the R-2R sections, one of the additional resistive links in a R section is connected to a fine resolution node voltage produced between the terminals of that R section. 
   In a described embodiment, the first voltage increment is equal to 2 n/2  times the second voltage increment. 
   In a described embodiment, the coarse resolution resistor circuit ( 11 ) is coupled between the first input voltage (V 240 ) and a higher magnitude reference voltage (Vin/vref) by means of a scaling resistance ( 30 - 1 ) to produce the first input voltage (V 240 ) as a precisely scaled version of the higher magnitude reference voltage. 
   In one embodiment, the invention provides a method for converting a digital input number (D 0 , 1  . . . (n−1)) to an analog output signal (Vout 1 −Vout 2 ), including coupling a coarse resolution resistor circuit ( 11 ) between a first input voltage (Vin/Vref or V 240  or V 992 ) and an intermediate voltage (V 0 ) to produce a first number of coarse resolution node voltages (V 0 , . . . (V 240  or V 992 )), each coarse resolution node voltage being separated from an adjacent coarse resolution node voltage by a first voltage increment equal to the difference between the first input voltage (Vin/Vref or V 240  or V 992 ) and the intermediate voltage (V 0 ) divided by the first number minus 1, and also coupling a fine resolution resistor circuit ( 20 ) between the intermediate voltage (V 0 ) and a second input voltage (GND or Vin−) for producing a second number of fine resolution node voltages (V 0 , 1  . . . (V 15  or V 31 )), each fine resolution node voltage being separated from an adjacent fine resolution node voltage by a second voltage increment equal to the difference between the intermediate voltage (V 0 ) and the second input voltage (GND or Vin−) divided by the second number and selecting one of the coarse resolution node voltages in response to a third number of most significant bits of the digital input number (D 0 , 1  . . . (n−1)) to produce a first output voltage (Vout 2 ) and selecting one of the fine resolution node voltages in response to a fourth number of least significant bits of the digital input number (D 0 , 1  . . . (n−1)) to produce a second output voltage (Vout 1 ), the second output voltage (Vout 1 ) and the first output voltage (Vout 2 ) providing the analog output signal (Vout 1 −Vout 2 ). In a described embodiment, the method includes setting the first voltage increment equal to 2 n/2  times the second voltage increment and setting the magnitude of the intermediate voltage (V 0 ) equal to the first voltage increment. 
   In a described embodiment, the invention provides a digital to analog converter for converting a digital input number (D 0 , 1  . . . (n−1)) to an analog output signal (Vout 1 −Vout 2 ), including a coarse resolution resistor circuit ( 11 ) coupled between a first input voltage (Vin/Vref or V 240  or Vin+) and an intermediate voltage (V 0 ) to produce a first number of coarse resolution node voltages (V 0 , . . . (V 240  or V 992 )), each coarse resolution node voltage being separated from an adjacent coarse resolution node voltage by a first voltage increment equal to the difference between the first input voltage (Vin/Vref or V 240  or Vin+) and the intermediate voltage (V 0 ) divided by the first number minus 1, a fine resolution resistor circuit ( 20 ) coupled between the intermediate voltage (V 0 ) and a second input voltage (GND or Vin−) for producing a second number of fine resolution node voltages (V 0 , 1  . . . (V 15  or V 31 )), each fine resolution node voltage being separated from an adjacent fine resolution node voltage by a second voltage increment equal to the difference between the intermediate voltage (V 0 ) and a second input voltage (GND or Vin−) divided by the second number, means ( 35 B) for selecting one of the coarse resolution node voltages in response to a third number of most significant bits of the digital input number (D 0 , 1  . . . (n−1)) to produce a first output voltage (Vout 2 ), and means ( 35 A) for selecting one of the fine resolution node voltages in response to a fourth number of least significant bits of the digital input number (D 0 , 1  . . . (n−1)) to produce a second output voltage (Vout 1 ), the second output voltage (Vout 1 ) and the first output voltage (Vout 2 ) providing a differential analog output signal (Vout 1 −Vout 2 ). 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic diagram of a conventional 10-bit string DAC. 
       FIG. 2  is a schematic diagram illustrating a DAC architecture of the present invention. 
       FIG. 3  is a schematic diagram of a preferred DAC architecture of the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 2  shows a 10-bit DAC that reduces the number of switches from the 1024 switches shown in  FIG. 1  to only 64 switches. 10-bit DAC  10 - 1  includes a 5-bit “coarse resolution” section  18 A, and also includes a 5-bit “fine resolution” section  18 B. Coarse resolution section  18 A includes a coarse resolution string resistor section  11 , a switch section  12 , and a 5-bit coarse resolution decoder  14  which decodes the 5 most significant bits D 5 , 6  . . .  9  of the 10-bit input word D 0 , 1 , 2  . . .  9 . Fine resolution section  18 B includes a fine resolution string resistor section  20 , a switch section  21 , and a fine resolution decoder  23  which decodes the 5 least significant bits D 0 , 1  . . .  4  of the 10-bit input word D 0 , 1 , 2  . . .  9 . 
   Coarse resolution string resistor section  11  includes 31 series-connected resistors R 2 - 1 , 2  . . .  31 , each of which has a resistance equal to 32×R. Note that fine resolution section  18 B functions as a 32nd resistor having the same resistance as each of the resistors in coarse resolution section  18 A. Resistor R 2 - 1  has its lower terminal connected to conductor  22 - 1  and its upper terminal connected by conductor  13 - 1  to the lower conductor of resistor R 2 - 2 . Conductors  13 - 2 , 3  . . .  30  are connected to the junctions between resistors R 2 - 2  and R 2 - 3 , between resistors R 2 - 3  and R 2 - 4 , and so on. Conductor  13 - 31  is connected to the upper terminal of resistor R 2 - 31  and also is connected to a voltage input terminal to which an input voltage Vin or a reference voltage Vref is applied. Node voltages V 0 , V 32 , V 64  . . . V 960 , and V 992  are produced on conductors  22 - 1 ,  13 - 1 ,  13 - 2  . . . ,  13 - 30 , and  13 - 31 , respectively. 
   Switch section  12  includes 32 switches SW 2 - 0 , 1  . . .  31 . The left and right terminals of switch SW 2 - 0  are connected to conductors  22 - 0  and  16 , respectively. The left terminals of switches SW 2 - 1 , 2  . . .  31  are connected to conductors  13 - 1 , 2  . . .  31 , respectively. The right terminals of switches SW 2 - 1 , 2  . . .  31  are connected to conductor  16 , on which an output signal Vout 2  is produced. 32 output control lines  15 - 0 , 1 , 2  . . .  31  from coarse resolution decoder  14  are connected to the control terminals of switches SW 2 - 0 , 1  . . .  31 , respectively. Switches SW 2 - 0 , 1  . . .  31  can be N-channel transistors, or they can be CMOS transmission gates, in which case each of the control lines  15 - 0 , 1  . . .  31  includes two conductors conducting logical complement control signals to the N-channel transistor and the P-channel transistor, respectively, which comprise each transmission gate. 
   Fine resolution string resistor section  20  includes 32 series-connected resistors R 1 - 1 , 2  . . .  32  each of which has a resistance equal to R. Resistor R 1 - 1  has its upper terminal connected to conductor  22 - 0  and its lower terminal connected by conductor  22 - 1  to the upper conductor of resistor R 1 - 2 . Conductors  22 - 1 , 2  . . .  31  are connected to the junctions between resistors R 1 - 1  and R 1 - 2 , between resistors R 1 - 2  and R 1 - 3 , and so on. The lower terminal of resistor R 1 - 32  is connected to ground. Node voltages V 0 , V 1 , V 2  . . . V 31  are produced on conductors  22 - 0 ,  22 - 1 ,  22 - 2  . . .  22 - 31 , respectively. 
   Switch section  21  includes 32 switches SW 1 - 0 , 1  . . .  31 . The left and right terminals of switch SW 1 - 0  are connected to conductors  22 - 0  and  26 , respectively. The left terminals of switches SW 1 - 0 , 1 , 2  . . .  31  are connected to conductors  22 - 0 , 1 , 2  . . .  31 , respectively. The right terminals of switches SW 1 - 0 , 1 , 2  . . .  31  are connected to conductor  26 , on which an output signal Vout 2  is produced. The 32 output control lines  24 - 0 , 1 , 2  . . .  31  from fine resolution decoder  23  are connected to the control terminals of switches SW 1 - 0 , 1  . . .  31 , respectively. The differential output voltage produced by DAC  10 - 1  is Vout 2 −Vout 1 . 
   Switches SW 1 - 0 , 1  . . .  31  can be N-channel transistors, or they can be CMOS transmission gates, in which case each of the control lines  24 - 0 , 1  . . .  31  includes two conductors conducting logical complement control signals to the N-channel transistor and the P-channel transistor, respectively, which comprise each transmission gate. 
   Coarse resolution decode circuit  14  is the MSB decoder, and receives the most significant digital input bits D 5 , 6  . . .  9 , and fine resolution decode circuit  23  is the LSB decoder, which receives the least significant digital input bits D 0 , 1  . . .  4 . Coarse resolution circuitry  18 A is referenced to either Vin or Vref on conductor  13 - 31 , and fine resolution circuitry  18 B is referenced to ground. (Alternatively, a differential input voltage Vin=Vin+−Vin− can be applied to DAC  10 - 1  wherein Vin+ is applied to conductor  13 - 31  and input signal Vin− is applied to the conductor, labeled as ground in the drawings, which is connected to the bottom terminal of resistor R 1 - 32 .) The input voltage on conductor  13 - 31  can be can be either a time-varying input signal Vin or a reference voltage Vref. DAC  10 - 1  can be used as a controllable voltage divider wherein the differential output signal Vout 2 −Vout 1  is proportional to Vin or Vref, depending on the value of the digital input word D 0 , 1 , 2  . . .  9 . Thus, DAC  10 - 1  can be used as a digitally controllable reference voltage source to scale down a fixed reference voltage supplied by another reference voltage circuit, or as a digitally controllable signal source to scale down a signal voltage. 
   It should be understood that fine resolution section  18 B is illustrated as being, in effect, a 32nd resistor which is connected in series with coarse resolution section  18 A, and although in  FIG. 2  fine resolution section  18 B is connected between the ground or lower differential input terminal of DAC  10 - 1  in the bottom of coarse resolution section  18 A, the relative positions of fine section  18 B and coarse resolution section  18 A could be reversed. (Note, however, that fine resolution section  18 B could actually be swapped with any one of the coarse resolution resistors R 2 - 1 , 2  . . .  31 .) 
   The coarse resolution voltage steps between the voltage nodes  13 - 1 ,  13 - 2  . . . etc. in the coarse resolution resistor string  11  are 32 times larger than the fine resolution voltage steps between the voltage nodes  22 - 1 ,  22 - 2  . . . etc. in fine resolution resistor string  20 . In operation, a selected number of voltage steps in fine resolution resistor string  20  (wherein the number of such voltage steps is determined by fine resolution decoder  23  in response to least significant bits D 0 , 1  . . .  4 ) is added to a selected number of voltage steps in coarse resolution resistor string  11  (wherein the number of such voltage steps is determined by a coarse resolution decoder  14  in response to the most significant bits D 5 , 6  . . .  9 ). For example, a particular selected number of 32-millivolt coarse voltage steps of coarse resistor string  11  may be added to another selected number of 1-millivolt fine voltage steps of fine resistor string  20  to provide a value of differential output voltage Vout 2 −Vout 1  with a resolution of 1 millivolt. 
   DAC  10 - 1  of  FIG. 2  has the advantage of greatly reducing both the number of switches and the amount of decode logic required and also greatly reduces the overall circuit complexity. DAC  10 - 1  of  FIG. 2  has only 2 (1+n/2)  switches and string resistors, although the coarse resolution resistors have much greater resistance than the fine resolution resistors. If the physical size of the coarse resolution resistors can be the same as the physical size of the fine resolution resistors, then the architecture of DAC  10 - 1  greatly reduces the amount of integrated circuit area. For a 10 bit DAC with the new architecture shown in  FIG. 2 , the number of switches is greatly reduced and the decode logic is simplified. 
   However, DAC  10 - 1  does not reduce the number of string resistors if it is necessary to construct each of the resistors in coarse resolution resistor string  11  by connecting 32 precisely matched resistors of resistance R in order to achieve very precise matching of all of the string resistors in DAC  10 - 1 . Often, it would be desirable to achieve the precise string resistor matching that is achieved by constructing each coarse resolution string resistor of resistance  32 R in coarse resistor string  11  from 32 identical, and therefore precisely matched, series-connected individual resistors of resistance R, and by constructing each fine resolution string resistor of resistance R in fine resistor string  20  from one individual resistor of resistance R. In this case, the total number of required resistors is not reduced. 
   Also, the output impedance of DAC  10 - 1  of  FIG. 2 , varies considerably with respect to the value of the digital input code D 0 , 1  . . .  9 . This makes it difficult to achieve acceptable, consistent settling times for the voltages on sampling capacitors of switched capacitor sampling circuits which sample the DAC output voltages Vout 1  and Vout 2 . 
   Nevertheless, in many cases, DAC  10 - 1  can be advantageously used in a switched capacitor circuit in which the differential voltage is transferred to switched capacitors, and then is transferred from there to another point in a system to be used for comparison, amplification, etc. 
     FIG. 3  shows an 8-bit implementation of a presently preferred embodiment of the invention. In  FIG. 3 , an 8-bit implementation of DAC  10 - 2  of the present invention includes three distinct resistor sections  30 - 1 ,  30 - 2 A and  30 - 2 B. DAC  10 - 2  includes a coarse resolution resistor section  30 - 2 A which provides coarse resolution node voltages V 0 , V 16 , V 32  . . . and so forth, up to V 240  (which are the exactly same coarse resolution node voltages that would be produced in an 8-bit implementation of string DAC  10 - 1  of  FIG. 2 ), to be provided to 16 corresponding CMOS transmission gate switches SW 2  in block  38  of coarse resolution decode and switch circuitry  35 B. DAC  10 - 2  also includes a fine resolution resistor section  30 - 2 B which provides fine resolution node voltages V 0 , B 1 , V 2  . . . and so forth, up to V 15 , to be provided to the 16 corresponding CMOS transmission gate switches SW 1  in block  43  of fine resolution decode and switch circuitry  35 A. 
   DAC  10 - 2  also includes an optional resistor section  30 - 1 , which can be constructed as a simple string resistor section including resistors R 80 , R 81  . . . R 96  and a composite resistor R 78  (which is composed of two parallel-connected resistors R 78 A and R 78 B) all connected in series between input conductor  46  and conductor  240 . An input voltage Vin or a reference voltage Vref can be applied to conductor  46 , and a node voltage V 240  is produced on conductor  240 . Resistor section  30 - 1  can be omitted, and Vin/Vref can be coupled directly to conductor  240  if Vin or Vref is the needed voltage. However, if Vin or Vref needs to be scaled down, resistor section  30 - 1  can be included along with resistor sections  30 - 2 A and  30 - 2 B to provide voltage division to achieve the desired value of V 240  on conductor  240 . It should be appreciated that the scaling down of a particular supply voltage or reference voltage to obtain a voltage on conductor  240  that is scaled down with respect to the full scale voltage of the DAC may be quite desirable. It also should be appreciated that the scaling resistor section indicated by reference  30 - 1  works especially well with coarse resolution resistor section  30 - 2 A and fine resolution resistor section  30 - 2 B to provide the voltage division because the resistances of coarse resolution resistor section  30 - 2 A and fine resolution resistor section  30 - 2 B are not a function of the digital input code. Thus, a further advantage of the structure shown in  FIG. 3  is that it not only provides a low, constant impedance independent of the digital input code, but also allows very convenient scaling of the voltage applied across the coarse and fine resistor sections down to a voltage that is scaled with respect to the full scale voltage of the DAC. (Of course, a resistor section similar to resistor section  30 - 1  also can be used in conjunction with DAC  10 - 1  of  FIG. 2 .) 
   Coarse resolution decode and switching circuit  35 B decodes the most significant four bits D 4 , 5  . . .  7  of eight-bit digital input word D 0 , 1  . . .  7  to couple Vout 1  to an appropriate one of the coarse resolution node voltages V 0 , V 16 , V 32 , V 48  . . . V 240  as shown in coarse resolution resistor section  30 - 2 A. Fine resolution decode and switching circuit  35 A decodes the least significant four bits D 0 , 1  . . .  3  of eight-bit digital input word D 0 , 1  . . .  7  to couple Vout 2  to an appropriate one of the fine resolution node voltages V 0 , 1 , 2  . . .  15  as shown in resistor section  30 - 2 B. Each of the coarse resolution voltage steps of an 8-bit string DAC must be equal to 16 times each of the fine resolution voltage steps. 
   All of the integrated circuit resistors shown in  FIG. 3  preferably are composed of identical resistors which are referred to herein as “resistive links”, all of which have a resistance R, so that all of the resistors and combinations of resistors in an integrated circuit have a very high degree of matching. 
   Coarse resolution resistor section  30 - 2 A and fine resolution resistor section  30 - 2 B in  FIG. 3  together form a modified R-2R network that provides all of the above mentioned node voltages needed to enable coarse resolution decode and switching circuit  35 B and fine resolution decode and switching circuit  35 A to produce the differential output signal Vout 1 −Vout 2  in response to the decoding of digital input code D 0 , 1  . . .  7  by coarse resolution decode logic  40  and fine resolution decode logic  44 , with a resolution of 1 LSB. 
   Coarse resolution section  30 - 2 A includes three R-2R sections  50 ,  51  and  52 , and also includes a fourth R-2R section  53  which includes resistors R 41  and R 37 ,R 38 . Each R-2R section includes an “R” portion and a “2R” portion. 
   R-2R section  50  includes resistors R 60 , R 63 , R 64 , R 65 , R 66 , R 67 , R 68 , R 71 , R 72 , R 76 , R 77 , R 73 , R 74 , and R 75  as its “R” portion (which has a resistance R), and also includes series-connected resistors R 58  and R 59  as its “2R” portion (which has a resistance 2×R). Similarly, R-2R section  51  includes resistors R 50 , R 53 , R 54 , R 55 , R 56 , and R 57  as its “R” portion and includes resistors R 48  and R 49  as its “2R” portion. R-2R section  52  includes resistors R 47  and R 45  as its “R” portion and resistors R 42  and R 43  as its “2R” section. 
   Resistor R 41  is the “R” portion of above mentioned R-2R section  53 , which also includes series-connected resistors R 37  and R 38  as its “2R” portion. 
   Fine resolution resistor section  30 - 2 B includes three R-2R sections  54 ,  55 , and  56 . R-2R section  54  includes resistors R 24 , R 28 , R 21 , R 25 , R 26 , R 27 , R 29 , R 30 , R 36 , R 33 , R 34 , R 35 , R 39 , and R 40  as its “R” portion (which has a resistance R), and also includes series-connected resistors R 20  and R 19  as its “2R” portion (which has a resistance 2×R). Similarly, R-2R section  55  includes resistors R 13 , R 14 , R 15 , R 16 , R 17 , and R 18  as its “R” portion and includes resistors R 9  and R 10  as its “2R” portion. R-2R section  56  includes resistors R 6  and R 8  as its “R” portion and resistors R 3  and R 4  as its “2R” section. Resistors R 2  and R 1  form the usual termination circuit of a R-2R network. 
   The “R” portion of R-2R section  50  includes resistor R 75  connected between node voltages V 240  and V 224 . Resistor R 74  is connected between V 224  and V 208 . Resistor R 73  is connected between V 208  and V 192 . Resistor R 77  is connected between V 192  and V 176 . Resistor R 72  is connected between V 240  and V 176 . Resistors R 76  and R 71  are connected in series between V 240  and V 176 . Resistor R 71  is composed of three resistors of resistance R connected in parallel. Similarly, resistor R 68  is connected between V 176  and V 160 . Resistor R 67  is connected between V 160  and V 144 . Resistor R 64  is connected between V 144  and V 128 . Resistor R 60  is connected between V 128  and V 112 . Resistor R 65  is connected between V 176  and V 112 . Resistors R 66  and R 63  are connected in series between V 176  and V 112 . Resistor R 63  is composed of three “resistive links”, each of resistance R, connected in parallel. 
   The “R” portion of R-2R section  51  includes resistor R 57  connected between V 112  and V 96 . Resistor R 56  is connected between V 96  and V 80 . Resistor R 54  is connected between V 80  and V 64 . Resistor R 50  is connected between V 64  and V 48 . Resistors R 55  and R 53  are connected in series between V 112  and V 48 . Resistor R 53  is composed of three resistive links of resistance R connected in parallel. 
   The “R” portion of R-2R section  52  includes resistors R 47  and R 45  connected in series between V 48  and V 16 . V 32  is produced at the Junction between resistors R 47  and R 45 . Resistors R 47  and R 45  each are composed of two resistive links of resistance R connected in parallel. 
   Similarly, the “R” portion of R-2R section  54  includes resistor R 40  connected between V 0  and V 1 . Resistor R 35  is connected between V 1  and V 2 . Resistor R 34  is connected between V 2  and V 3 . Resistor R 33  is connected between V 3  and V 4 . Resistor R 39  is connected between V 0  and V 4 . Resistors R 36  and R 30  are connected in series between V 0  and V 4 . Resistor R 30  is composed of three resistive links of resistance R connected in parallel. Similarly, resistor R 29  is connected between V 4  and V 5 . Resistor R 26  is connected between V 5  and V 6 . Resistor R 25  is connected between V 6  and V 7 . Resistor R 21  is connected between V 7  and V 8 . Resistor R 27  is connected between V 4  and V 8 . Resistors R 28  and R 24  are connected in series between V 4  and V 8 . Resistor R 24  is composed of three resistive links of resistance R connected in parallel. 
   The “R” portion of R-2R section  55  includes resistor R 18  connected between V 8  and V 9 . Resistor R 16  is connected between V 9  and V 10 . Resistor R 15  is connected between V 10  and V 11 . Resistor R 14  is connected between V 11  and V 12 . Resistors R 17  and R 13  are connected in series between V 8  and V 12 . Resistor R 13  is composed of three resistive links of resistance R connected in parallel. 
   The “R” portion of R-2R section  56  includes resistor R 8  and R 6  connected in series between V 12  and V 14 . V 13  is produced at the junction between resistors R 8  and R 6 . Resistors R 8  and R 6  each are composed of two resistive links of resistance R connected in parallel. 
   All of the resistors shown in  FIG. 3  preferably are identical, precisely matched resistive links of resistance R. 
   By way of definition, a coarse node voltage or a fine node voltage is considered to be “produced in” a R section of a R-2R section if the node voltage is produced either at the junction between the R and 2R sections of that R-2R section or if it is produced at any junction between resistive links of which the R section is composed. 
   DAC  10 - 2  of  FIG. 3  solves the above mentioned problem of the implementation of  FIG. 2  using “unitary” coarse resolution resistors of resistance 32R (rather than using coarse resolution resistors composed of 32 series-connected resistive links each of resistance R) and fine resolution resistors which each are a single resistive link of resistance R. 
     FIG. 3  achieves the reduction in the total number of required precisely matched resistors of resistance R (over the number required by the architecture of string DAC  10 - 1  of  FIG. 2 ) by using the described R-2R network or equivalent thereof including coarse resolution resistive network  30 - 2 A and fine resolution resistive network  30 - 2 B so as to provide all of the reduced number of coarse resolution node voltages V 0 , V 16 , V 32  . . . V 240  and fine resolution node voltages V 0 , V 1  . . . V 15  that are needed (which are the same coarse resolution node voltages and fine resolution node voltages that would be required in an 8-bit implementation of DAC  10 - 1  in  FIG. 2 ). 
   Also, the output impedance of 8-bit DAC  10 - 2  of  FIG. 3  is much lower than the output impedance of an 8-bit implementation of string DAC  10 - 1  of  FIG. 2 . The range of the output impedance of DAC  10 - 2  is within a reasonably low range of approximately 1R and 3R, which is substantially lower than for the architecture of Prior Art  FIG. 1 . It should be noted that in a typical string DAC, the output impedance obviously depends heavily on which node voltage conductor is coupled to the string DAC output, and varies between approximately 0 and (R×2 n )/4, where n is the resolution of the DAC. 
   Thus, DAC  10 - 2  of  FIG. 3  includes an R-2R resistor network instead of using conventional resistor strings, wherein the sections of the R-2R network are constructed of identical, and therefore precisely matched, integrated circuit resistors or resistive links of resistance R. The R-2R resistor network in  FIG. 3  is formed of a much smaller number of identical integrated, precisely matched integrated circuit resistive links of resistance R than has been achieved in the prior art. For example, an 8-bit DAC with a differential output voltage range from 0 to 255 millivolts and an LSB or resolution of 1 millivolt (in which case the reference voltage Vref would be 2.496 volts) can be realized in the architecture of  FIG. 3  using only 96 equal, precisely matched, inexpensive integrated circuit resistors. 
   The “R” sections are modified in order to obtain the number of node voltages required for the resolution determined by the number of bits of the digital input code D 0 , 1  . . .  7 . It should be appreciated that the “splitting” of the “R” sections to achieve needed number of node voltages can be accomplished in various ways. The particular way disclosed herein represents a compromise between the number of identical resistors of resistance R needed and the desired output impedance of the DAC. 
   Although a single ended output may be desirable for a stand alone DAC, in many cases a differential output is preferable, especially for a DAC embedded in a larger integrated circuit system. For example, if the DAC outputs must be sampled by means of switched capacitor circuitry, the differential output of  FIG. 3  is preferable because it provides better balanced charging and settling of the sampling capacitors of the switched capacitor circuitry. 
   To summarize, the new topology of  FIG. 2  greatly reduces the number of switches and simplifies the digital decode logic. The new topology of  FIG. 3  including the “R-2R” embodiment of the DAC solves the problem of high, widely varying output impedance. If the differential output voltage is sampled, the settling time for the sampling is minimal and does not vary significantly with the DAC input code. The topology of  FIG. 3  allows the entire DAC to be implemented with a relatively very small number of equal, precisely matched resistors, and additionally reduces the number of components and the amount of integrated circuit chip area. The use of the equal, precisely matched resistors reduces the DNL and INL (integral nonlinearity) errors of the DAC. 
   While the invention has been described with reference to several particular embodiments thereof, those skilled in the art will be able to make various modifications to the described embodiments of the invention without departing from its true spirit and scope. It is intended that all elements or steps which are insubstantially different from those recited in the claims but perform substantially the same functions, respectively, in substantially the same way to achieve the same result as what is claimed are within the scope of the invention. For example, although DAC  10 - 1  of  FIG. 2  and DAC  10 - 2  of  FIG. 3  show the same number of digital input bits applied to the coarse resolution sections and the fine resolution sections, it is not necessary that the same number of the digital input bits be applied to the coarse resolution and fine resolution sections. Furthermore, the embodiment of  FIG. 3  could be modified so as to use fine string resistors  20  of  FIG. 2  instead of R-2R network  30 - 2 B.