Abstract:
A method and system that can be used with signals read from a memory cell or other feature that varies in amplitude as a function of the data being read. The data read from the memory cell may be of the type that decreases in voltage when a ‘low’ is being read and that remains at a predetermined voltage when a ‘high’ is being read. The method and system may vary a reference to voltage used to judge whether the data is being read ‘low’ or ‘high’.

Description:
BACKGROUND 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a circuit for amplifying single-ended differential signals and a method of sensing bit line data carried within the amplified signal. 
         [0003]    2. Background Art 
         [0004]      FIG. 1  schematically illustrates a memory system where bit line data is read from one or more memory cells. The bit line data may be read by a sense amplifier as being high or low depending on whether a voltage of the bit line (BL) is higher or lower than a reference voltage (Vref). Pressure, voltage, and temperature (PVT) variations within the system can influence the voltage differential required to properly read data from the cells. One cell may output a lower voltage than another cell or one sense amplifier may receive a lower Vref than another cell. Since the Vref is fixed and commonly supplied to each sense amplifier, the value of Vref may be selected to correspond with the worst case PVT conditions. The worst case condition compensations can require the value of Vref to be selected in a manner that insures a sufficient voltage differential. A large voltage differential can increase the time it takes to read data from the cells. 
         [0005]      FIG. 2  graphically illustrates reading a single-ended differential signal used to carry the bit line data. A left portion of the illustration corresponds with reading a low value from a cell when BL is sufficiently less than Vref. A right portion of the illustration corresponds with reading a high value from a cell when BL is sufficiently greater than Vref. The sense amplifier is unable to properly read the data until a sufficient voltage differential is generated. As shown with respect to reading a low value, a particular period of time may have to transpire before the BL is sufficiently less than Vref. This period of time is directly proportional to the time it takes to read data from the cells. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    The present invention is pointed out with particularity in the appended claims. However, other features of the present invention will become more apparent and the present invention will be best understood by referring to the following detailed description in conjunction with the accompany drawings in which: 
           [0007]      FIG. 1  schematically illustrates a memory system where bit line data is read from one or more memory cells; 
           [0008]      FIG. 2  graphically illustrates reading a single-ended differential signal used to carry the bit line data; 
           [0009]      FIG. 3  schematically illustrates a system for reading bit line data in accordance with one non-limiting aspect of the present invention; 
           [0010]      FIG. 4  graphically illustrates reading the bit line data in accordance with one non-limiting aspect of the present invention; 
           [0011]      FIG. 5  schematically illustrates a circuit for reading data in accordance with one non-limiting aspect of the present invention; 
           [0012]      FIG. 6  illustrates reading a bit line ‘low’ value in accordance with one non-limiting aspect of the present invention; and 
           [0013]      FIG. 7  illustrates reading a bit line ‘high’ value in accordance with one non-limiting aspect of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0014]      FIG. 3  schematically illustrates a system for reading bit line data in accordance with one non-limiting aspect of the present invention. The system may be configured to read data from any number of memory cells. The data may be carried within bit line signals read from each of the cells. A sense amplifier may be associated with each of the bit line signals to sense whether the data carried within the associated signal is high or low. A common reference voltage (Vref) may be provided to facilitate sensing whether the data is high or low. Generally, the data is read high if a voltage of the bit line (BL) is sufficiently higher or than Vref and read low if the BL is sufficiently lower than Vref. 
         [0015]    A local voltage generator may be associated with each of the sense amplifiers. The generators may be configured in accordance with the present invention to generate a substitute reference voltage (Vrefo). The sense amplifiers may be configured to substitute the commonly generated Vref with the Vrefo when assessing whether the BL is high or low. This substitution can be beneficial since it allows a separate and independent reference voltage to be generated at each sense amplifier. The independent reference voltages can limit inconsistencies in the system that may result from the sense amplifiers experiencing pressure, voltage, and temperature (PVT) variations. 
         [0016]    The local voltage generators may be configured to vary Vrefo depending on whether a high or low value is being read from the cells. One non-limiting aspect of the present invention contemplates increasing Vrefo to a value greater than Vref if the bit line value is to be read low and allowing Vrefo to equal Vref if the bit line value is to be read high. This can be helpful in reducing the amount of time required for the sense amplifiers to sense a sufficient voltage difference between BL and Vrefo. 
         [0017]      FIG. 4  graphically illustrates reading the bit line data in accordance with one non-limiting aspect of the present invention. A left portion of the illustration corresponds with reading a low value—BL being less than Vrefo—and a right portion of the illustration corresponds with reading a high value—BL being greater than Vrefo. A reference numeral may be used to refer to the difference in voltage required by the sense amplifier to read the data. The testing cycle time generally is limited by the length of time take to generate this difference. 
         [0018]    The sense amplifier requires some a minimal difference between BL and Vrefo before a proper reading can occur. As such, the testing cycle time cannot be shorter than the time take to create the voltage difference required by the particular sensitivity of the sense amplifier being used. Instead of adjusting the sensitivity of the sense amplifier, the present invention is able to use the same sense amplifier and decrease the read time by varying Vrefo so that the desired voltage difference occurs sooner. 
         [0019]    As shown in  FIG. 4 , the present invention increases Vrefo when low values are being read in order to produce the necessary voltage difference prior to the arrangement shown in  FIG. 2 . The testing cycles in  FIGS. 2 and 4  are shown to correspond with the same total period of time for exemplary purpose and to demonstrate the earlier read sensitivity of the present invention. The present invention could easily decrease the cycle time by beginning subsequent read operations after the prior read operation completes. 
         [0020]      FIG. 5  schematically illustrates the system in accordance with one non-limiting aspect of the present invention. The schematic illustrates a circuit arrangement that may be used to supply the voltage used by the sense amplifiers. The circuit arrangement may be configured to provide Vrefo to the sense amplifiers in the manner described above, i.e., where the Vrefo is provided at a value above Vref during a low read and at a value equal to Vref during a high read. 
         [0021]    A source may be included for providing Vref. Another source may be included to provide a supply voltage (Vdd) used to pull Vrefo to a voltage level greater than Vref. A number of switches P 1 , P 2 , P 3 , P 5 , a capacitor P 4 , and inverter I 1  may be included to facilitate operating the system as described in the operational charts illustrated in  FIGS. 6 and 7 . 
         [0022]      FIG. 6  illustrates reading a bit line low value. An EN portion of the illustration indicates the state of EN as controlled by a controller (not shown). When EN is low, P 2  and P 3  are ‘on’ and intermediate node BL′ and Vrefo are pre-charged to Vref. When EN goes high, P 2  and P 3  turn ‘off’ and I 1  inverts the signal to cause EN′ to go low and turn ‘on’ P 5 . P 5  then pulls intermediate node Vddi up from Vref to Vdd. BL, which was pre-charged to Vdd, is pulled down when the cell begins to pull BL down with the low read value. P 4  allows intermediary node BL′ to remain at Vref until BL begins to pull low. Once BL′ goes low, BL′ is coupled down via capacitor P 4 . P 1  is turned ‘on’ and Vrefo is pulled to Vdd. Since Vdd is greater than Vref, Vrefo is pulled higher as the bit line goes lower. This increases the voltage differential in the manner described above. At the end of the read cycle, EN goes low to turn P 2  and P 3  turn ‘on’ and pull Vrefo and BL′ to Vref. 
         [0023]      FIG. 7  illustrates reading a bit line high value. A similar process occurs as with the process described above with respect to  FIG. 6  except the P 1  is not turned ‘on’ since BL remains high (at Vdd). Without Vdd to pull Vrefo to Vdd, Vrefo remains at Vref. At the end of the read cycle, EN goes low to turn P 2  and P 3  turn ‘on’ and pull Vrefo and BL′ to Vref. 
         [0024]    As required, detailed embodiments of the present invention are disclosed herein; however, it is to be understood that the disclosed embodiments are merely exemplary of the invention that may be embodied in various and alternative forms. The figures are not necessarily to scale, some features may be exaggerated or minimized to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for the claims and/or as a representative basis for teaching one skilled in the art to variously employ the present invention.