Abstract:
The invention relates to circuitry for protecting n-channel load driving devices from reverse voltage conditions and for inhibiting the flow of destructive currents through such devices under reverse voltage conditions. According to one embodiment of the invention, a circuit is provided for protecting an n-channel high side load driving device from negative battery and negative transient operating conditions.

Description:
FIELD OF THE INVENTION 
     The present invention relates generally to circuitry for protecting n-channel load driving devices from reverse voltage conditions, and more specifically to such circuitry for inhibiting the flow of destructive currents through such devices under reverse voltage conditions. 
     BACKGROUND OF THE INVENTION 
     Integrated circuits are often used for driving loads in a variety of applications including those in the automotive environment. Such automotive loads may include dashboard lights, fuel injectors, solenoids, motors and the like. To provide the maximum voltage across such loads, the loads or load driving circuitry are typically tied directly to the vehicle battery. 
     Integrated circuits that drive these automotive loads fall into two broad categories; low side drivers and high side drivers. Referring to FIG. 1, a prior art example of a low side driver circuit  10  is illustrated. Circuit  10  includes a load driving device  12 , illustrated in FIG. 1 as a metal-oxide-semiconductor field effect transistor (MOSFET), having a control input or gate receiving a gate drive signal GD, an output or source connected to ground potential or VSS, and a signal input or drain connected to one end of a load  14 . The opposite end of load  14  is connected to battery voltage V BAT . Within circuit  10 , load driving device  12  is responsive to the gate drive signal GD to conduct a load current I L  from V BAT  through load  14 , and through device  12  to ground potential VSS. 
     Referring to FIG. 2, a prior art example of a high side driver circuit  20  is illustrated. High side driver circuit  20  includes a load driving device  12 , illustrated in FIG. 2 as a MOSFET, including a control input or gate receiving a gate drive signal GD, a signal input or drain connected to battery voltage V BAT  and an output or source connected to one end of a load  14 . The opposite end of load  14  is connected to ground potential or VSS. In operation, load driving device  12  is responsive to the gate drive signal GD to conduct current from V BAT , from the drain to the source of device  12 , through load  14  and to ground potential VSS. 
     In either of these circuit configurations  10  or  20  shown in FIGS. 1 and 2, the load driving device  12  is typically an N-channel MOSFET having a low voltage drop from drain to source when activated. Within circuits  10  and  20  of FIGS. 1 and 2, the load driving device  12  is illustrated as a double diffusion metal-oxide-semiconductor, or DMOS, transistor wherein the structure of one known configuration of a DMOS transistor  12  is shown in cross section in FIG.  3 . Referring to FIG. 3, the N channel DMOS transistor  12  includes a substrate  30 , typically formed from a P- semiconductor material in which a n-type buried layer silicon material  32  is formed. A n-type epitaxial layer  34  is typically grown or otherwise deposited on top of the substrate  30  and buried layer  32  combination, and a p-type isolation region  36  is diffused or otherwise implanted about a portion of layer  34  and extends into substrate  30  to thereby define a n-type silicon pocket  34 ′. A p+ layer  38  is typically diffused or otherwise implanted into a portion of the isolation region  36  to thereby form a low resistance contact for metal layer  40  which is typically tied to ground potential or VSS. 
     Within n-type pocket  34 ′, a deep N+ (DN+) region  42  is diffused or otherwise implanted into n-type pocket  34 ′ and extends into the buried layer  32  to thereby form a low resistance path through pocket  34 ′ to the buried layer  32 . A n+ silicon layer is diffused or otherwise implanted into DN+ layer  42  to thereby form an ohmic contact to metal layer  46  which defines the drain of the n-channel MOSFET. A p-type silicon layer  50  is diffused or otherwise implanted into n-type pocket  34 ′ and a p+ silicon layer  54  is diffused or otherwise implanted into p-type layer  50  to thereby provide an ohmic contact to a metal layer  56  which defines the source of MOSFET  12 . A n+ silicon layer  52  is diffused or otherwise implanted into p-type layer  50  about p+ region  54  and an oxide gate  58  is grown or otherwise deposited over p-type layer  50  and overlapping n+ layer  52  and n-type pocket  34 ′. A polysilicon layer  60  is formed over gate oxide  58  and defines the gate of MOSFET  12 . An oxide layer  48 , typically silicon dioxide (SiO 2 ) or silicon nitride (SiN 3 ), is formed over the bare silicon regions to thereby protect device  12  and insulate the silicon layers from the metal layers  40 ,  46 ,  56  and polysilicon layer  60 . In the operation of MOSFET  12 , a suitable gate voltage GD applied to gate  60  which forms a n-type depletion layer near the surface of p-type region  50  between n+ region  52  and n-type pocket  34 ′ to thereby provide a current conduction path between drain  46  and source  56 , as is known in the art. 
     In the typical structure of the n-channel MOSFET  12  illustrated in FIG. 3, two current conduction paths are formed that are separate from the operation of the MOSFET  12  as just described. A first current conduction path is formed between p-type region  50  and n-type pocket  34 ′ and defines a so-called body diode between source  56  and drain  46  as illustrated by diode Z 1  in FIGS. 1 and 2, wherein diode Z 1  is operable to conduct a current I Z1  from source  56  to drain  46  under certain negative battery or negative transient operating conditions as will be described in greater detail hereinafter. A second current path is defined between isolation region  36  and n-type pocket  34 ′ and defines a second diode illustrated in FIGS. 1 and 2 as diode Z 2 , wherein diode Z 2  is operable to conduct a current I Z2  from VSS  40  to the drain  46  of MOSFET  12  under certain negative battery or negative transient operating conditions as will be described in greater detail hereinafter. 
     The automotive environment offers many challenges when driving loads directly from the battery, including a reverse battery condition (e.g. −13.5 volts) and negative transients due to inductive switching of loads elsewhere in the vehicle. When using a n-channel MOSFET device such as device  12 , diodes Z 1  and Z 2  are operable to conduct currents I Z1  and I Z2  respectively when this negative voltage is applied to the battery line. In the low side driver configuration illustrated in FIG. 1, the negative battery condition or other negative transients generally do not cause a catastrophic problem since the currents I Z1  and I Z2  flowing from VSS to V BAT  are limited by the internal impedance of load  14 . This current limiting function of load  14  is typically sufficient to protect MOSFET  12  from damage or destruction in the low side driver configuration of FIG.  1 . 
     In the high side driver configuration illustrated in FIG. 2, however, the drain of the MOSFET  12  is coupled directly to ground potential VSS via diode Z 2 , wherein the drain of MOSFET  12  is connected directly to V BAT . Thus, under negative battery conditions or other negative transients, while current I Z1  is limited by the internal impedance of load  14 , the current I Z2  is limited only by the impedance of diode Z 2  which is typically very small. With such little resistance from VSS to V BAT  through diode Z 2 , the value of I Z2  may accordingly become excessively large and potentially destructive. As a result of large I Z2  current values, MOSFET  12  may latch up, the bond wires to the integrated circuit may become fused open, electromigration of the metal layers in the vicinity of device  12  may occur, and/or heat generated by the conduction of I Z2  may become excessive and damage or otherwise destroy the silicon. In any event, allowing the substantially unlimited current I Z2  to flow under negative battery or negative transient conditions could result in catastrophic damage to MOSFET  12  and surrounding circuitry. 
     At least three techniques for addressing the foregoing problems associated with negative battery and negative transient conditions in a n-channel MOSFET are known. According to one known technique, MOSFET  12  may be physically separated from the control circuitry controlling device  12  so that device  12  does not share an isolation region  36  in common with that of the control circuit generating the gate drive signal GD. This technique eliminates diode Z 2  but requires partitioning MOSFET  12  and any control circuitry into separate integrated circuits which may be cost prohibitive. 
     According to a second known technique for addressing the above problem, a PNP bipolar transistor may be used to replace MOSFET  12  in the high side driver circuit  20  of FIG.  2 . This technique eliminates any current flow back to the V BAT  terminal under negative battery conditions, but is expensive at the integrated circuit level since the area required for a PNP transistor is much larger than that required by MOSFET  12  for the same performance. The PNP transistor also has a large base current that would be pulled from the V BAT  line under normal operating conditions, thereby resulting in undesirable power dissipation and large quiescent currents. 
     A third known technique for addressing the above problem is to use a blocking diode between V BAT  and the drain of MOSFET  12  to thereby block reverse current flow from the drain of MOSFET  12  to V BAT  under reverse battery or negative transient conditions. Such blocking diodes, however, typically consume substantial circuit or circuit board space when sized large enough to handle the reverse voltage conditions as well as the load currents present during normal battery conditions. Moreover, the blocking diode creates a voltage drop in series with the load  14  that undesirably dissipates power and reduces the voltage across the load  14 . 
     In an integrated circuit of the type illustrated in FIG. 3, the potential of isolation region  36  is preferably connected to the lowest potential on the integrated circuit in order to be effective as a device isolator on the circuit. Accordingly, isolation region  36  has been typically connected in the past to ground potential or VSS. Unfortunately, this common practice results in the potentially destructive flow of current I Z2  through diode z 2  under negative battery or negative transient operating conditions in the high side driver configuration  20  illustrated in FIG. 2 as just described. What is therefore needed is a technique for addressing the problems associated with diode Z 2  described hereinabove while also maintaining isolation region  36  at or near the lowest potential on the integrated circuit. By eliminating the potentially destructive current I Z2  and further providing for the connection of isolation region  36  to the lowest potential on the integrated circuit, such a technique would be ideally suited for applications wherein it would be desirable to form one or more MOSFETS  12  on the same integrated circuit as that of the control circuitry. 
     SUMMARY OF THE INVENTION 
     The foregoing shortcomings of the prior art are addressed by the present invention. In accordance with one aspect of the present invention, circuitry for protecting a load driving device from a reverse voltage condition comprises a current drive device fabricated within a n-type silicon region formed on a p-type silicon substrate and surrounded by a p-type isolation region extending into the substrate, the n-type silicon region defining a drain of the drive device, a first protection device connected between the isolation region and a reference node, and a second protection device connected between the isolation region and the drain of the drive device. The first protection device isolates the isolation region from the reference node and the second protection device couples the isolation region to the drain of the drive device when a first voltage defined at the drain of the drive device is negative with respect to a reference potential defined at the reference node. The first protection device couples the isolation region to the reference node and the second protection device isolates the isolation region from the drain of the drive device when the first voltage is positive with respect to the reference potential. 
     One object of the present invention is to provide an improved circuit technique for protecting a n-channel high side load driving device from negative battery and negative transient operating conditions. 
     These and other objects of the present invention will become more apparent from the following description of the preferred embodiment. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram illustrating a prior art low side driver circuit utilizing a n-channel load driving device. 
     FIG. 2 is a schematic diagram illustrating a prior art high side driver circuit utilizing a n-channel load driving device. 
     FIG. 3 is a cross-sectional diagram illustrating one known structure of a prior art n-channel load driving device of the type illustrated in FIGS. 1 and 2. 
     FIG. 4 is a schematic diagram of a high side driver circuit illustrating circuitry for eliminating destructive current flow in a n-channel load driving device under negative battery or negative transient conditions, in accordance with the present invention. 
     FIG. 5 is a detailed schematic illustrating one preferred embodiment of the circuitry of FIG. 4 for eliminating destructive current flow in a n-channel load driving device under negative battery or negative transient operating conditions, in accordance with the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     For the purposes of promoting an understanding of the principles of the invention, references will now be made to the embodiment illustrated in the drawings and specific language will be used to describe the same. It will nevertheless be understood that no limitation of the scope of the invention is thereby intended, such alterations and further modifications in the illustrated device, and such further application of the principles of the invention as illustrated therein being contemplated as would normally occur to one skilled in the art to which the invention relates. 
     Referring now to FIG. 4, a simplified schematic of a high side driver circuit  100  including circuitry for eliminating the flow of current from VSS to V BAT  under negative battery or negative transient conditions, in accordance with the present invention, is shown. High side driver circuit  100  includes a n-channel MOSFET device  12  connected between battery voltage V BAT  and a load  14 , wherein device  12 , load  14  and V BAT  are all connected as described with respect to FIG.  2  and wherein load  14  is connected to ground potential or VSS. Some of the various regions of device  12  (including diodes z 1  and z 2 ), as they relate to the integrated circuit structure of device  12  illustrated and described with respect to FIG. 3, are correspondingly numbered parenthetically in FIG. 5 for cross-reference. In any event, unlike circuit  12  of FIG. 2, the anode of diode Z 2  in circuit  100  is not connected to VSS directly but is rather switchable between V BAT  and VSS through low resistance paths illustrated symbolically by resistors Ra and Rb respectively. Specifically, the circuitry  102  of the present invention includes a switch  104  connected to the anode of Z 2 , wherein activation of the switch  104  is controlled by the voltage polarity of V BAT  with respect to VSS as shown schematically by signal line  106 . If V BAT  is negative with respect to VSS, switch  104  is connected to low resistance path Ra to thereby pull the anode of diode Z 2  (isolation region  36  of FIG. 3) near V BAT . If, on the other hand, V BAT  is positive with respect to VSS, switch  104  is connected to low resistance path Rb to thereby pull the anode of diode Z 2  (isolation region  36  of FIG. 3) to a potential near VSS. It is to be understood that V BAT  is, in one embodiment, representative of the battery voltage of an automotive battery (not shown), but may alternatively be any voltage supply. 
     Referring now to FIG. 5, one preferred embodiment of the high side driver circuit  100  of FIG. 4, in accordance with the present invention, is shown. Circuit  100  of FIG. 5 includes the n-channel load driving device  12  having a drain connected battery voltage V BAT , a gate responsive to a gate drive voltage GD to activate device  12  as described hereinabove and a source connected to one end of a load  14 . The opposite end of load  14  is connected to a reference potential VSS which is preferably at ground potential. It is to be understood, however, that VSS may be a potential other than ground potential. The n-channel load driving device  12  includes body diode Z 1  defined between the source and drain of device  12  as described with respect to FIG. 3, and further includes diode Z 2  defined between an isolation region (such as isolation region  36  of FIG. 3) and the drain of device  12  as also described with respect to FIG.  3 . Unlike FIG. 3, however, the isolation region of device  12  within circuit  100  is not directly connected to VSS but is rather connected via signal line  110  to the source of a n-channel transistor M 1 , the source of a n-channel transistor M 2  and one end of a resistor R 2 . The gate of M 1  is connected to one end of a resistor R 1 , the opposite end of which is connected to VSS. The drain of M 1  is connected to V BAT . M 1  includes a body diode, identical to body diode Z 1  of device  12 , having an anode connected to the source of M 1  and a cathode connected to the drain of M 1 . The drain of M 2  is connected to VSS, and transistor M 2  includes a body diode ZM 2 , identical to diode Z 1  of device  12 , having an anode connected to the source of M 2  and a cathode connected to the drain of M 2 . The gate of transistor M 2  is connected to one end of a resistor R 3  and the collector of a NPN transistor Q 1 . The opposite ends of R 2  and R 3  are both connected to the drain of a p-channel transistor M 3 , the source of which is connected to a voltage VCC. VCC is, in one embodiment, less than V BAT  wherein typical values for V BAT  may range between approximately −12 to −15 volts (reverse battery condition) and approximately +12 to +15 volts (normal battery condition), and VCC is typically in the range of 5 volts. The source of transistor M 3  is further connected to one end of a resistor R 5 , the opposite end of which is connected to the base of Q 1  and the emitter of a PNP transistor Q 3 . The gate of transistor M 3  is connected to one end of a resistor R 4 , the opposite end of which is connected to the base of transistor Q 3  and to VSS. The emitter of Q 1  is connected to the anode of a diode, the cathode of which is connected to one end of a resistor R 6 . In one embodiment, the anode of the diode is defined by the connection of a base and collector of a NPN transistor Q 2 , and the cathode is defined by the emitter of Q 2 . In any case, the opposite end of resistor R 6  is connected to V BAT    
     In the operation of circuit  100 , transistor M 2  is operable to pull the isolation region defining the anode of diode Z 2  near VSS when V BAT  is positive with respect to VSS, and transistor M 1  is operable under such conditions to isolate the anode of diode Z 2  from V BAT . When V BAT  is negative with respect to VSS, transistor M 1  is operable to pull the isolation region defining the anode of Z 2  near V BAT  while transistor M 2  is operable to isolate the isolation region defining the anode of Z 2  from VSS. 
     When circuit  100  is without power, isolation line  110  is held near VSS via the body diode ZM 2  of transistor M 2 . Under normal power up conditions, a positive V BAT  is applied followed by application of VCC. As VCC approaches a gate-to-source threshold voltage (Vgs) of transistor M 3 , M 3  will turn on supplying gate drive to transistor M 2  through resistor R 3 . Transistor M 2  is responsive to this gate drive signal to turn on and pull the isolation line  110  near VSS through the low impedance path of activated M 2 . 
     Transistors Q 1 , Q 2  and Q 3  are used to monitor the voltage on the drain of device  12  (V BAT ). With V BAT  at a positive potential, transistors Q 1  and Q 2  are turned off and transistor Q 3  is turned on, thereby sinking the current supplied through R 5  from VCC. With the base of Q 3  connected to VSS, the emitter of Q 3  and the base of Q 1  are held one base-emitter voltage (Vbe) above VSS. When V BAT  goes negative one Vbe below VSS, Q 1  and Q 2  are turned on thereby pulling gate drive away from transistor M 2 . Transistor M 2  accordingly turns off which removes the low impedance path from isolation line  110  to VSS and minimizes any current flow in diode Z 2 . Isolation line  110  is, under such conditions, pulled near V BAT  through body diode ZM 1 . As V BAT  continues decreasing and approaches a Vgs threshold voltage below the gate of transistor M 1 , M 1  turns on and pulls the isolation line  110  near V BAT  through a low impedance path defined through the activated M 1 . With isolation line  110  approximately at the same potential V BAT , no current flows through Z 2  or ZM 1 . Transistor M 1  is thereafter operable to regulate the isolation line  110  to near V BAT  as long as V BAT  is negative. 
     If V BAT  starts increasing towards zero, transistor M 1  keeps isolation line  110  near V BAT  until V BAT  is a Vgs threshold below VSS. Diode ZM 1  and Z 2  keep isolation line  110  near V BAT  under such conditions. As V BAT  returns to 1 diode drop, or one Vbe, below VSS, transistors Q 1  and Q 2  turn off and the gate drive supplied by transistor M 3  is thereby directed to the gate of transistor M 2 . As a result, transistor M 2  turns on and pulls isolation line  110  near VSS through the low impedance path defined therethrough. 
     If a reverse battery condition occurs with no VCC applied, transistor M 2  is turned off since transistor M 3  is not supplying gate drive thereto. In this case, isolation line  110  would be coupled to V BAT  through diodes ZM 1  and Z 2  until transistor M 2  is enabled as described above. 
     From the foregoing it should be appreciated that the present invention provides for the protection of a n-channel MOSFET under negative battery and/or negative transient operating conditions, particularly when connected in a high-side driver configuration, while avoiding the various drawbacks of the prior art protection circuits described in the BACKGROUND section. By eliminating the possibility of large current flow through diode z 2 , the present invention also allows one or more n-channel MOSFETs and control circuitry therefore to be fabricated on the same integrated circuit without risking catastrophic damage to any of the circuitry due to negative battery and/or negative transient operating conditions. Moreover, the present invention is effective in maintaining the potential of the isolation region defining the anode of diode Z 2  near the most negative potential on circuit  100  for optimal device isolation while establishing a high impedance between VSS and V BAT  under negative battery and/or negative transient operating conditions. 
     While the invention has been illustrated and described in detail in the foregoing drawings and description, the same is to be considered as illustrative and not restrictive in character, it being understood that only the preferred embodiment has been shown and described and that all changes and modifications that come within the spirit of the invention are desired to be protected.