Abstract:
A Dynamic Random Access Memory (DRAM) device includes a bus for distributing a boosted voltage V CCP  within the device. A conventional internal voltage regulator, ring oscillator, and charge pump help to boost the boosted voltage V CCP  on the bus when the voltage V CCP  falls below a preset minimum. During testing of the DRAM device, when the demand on the boosted voltage V CCP  can be four or more times as much as it is under normal operating conditions, an external current source drives current I CCP  into an unused bond pad, such as a no-connection (NC) or address signal bond pad. An NMOS transistor switch then connects this bond pad to the boosted voltage V CCP  bus when a pump circuit controlled by the ring oscillator activates the switch. As a result, the external current augments the efforts of the internal charge pump to boost the voltage V CCP  during testing, so there is no need to build the internal charge pump with oversized capacitors to handle the excessive V CCP  demand during testing.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS:  
       [0001]    This application is a continuation of application Ser. No. 09/873,823, filed Jun. 4, 2001, pending, which is a continuation of application Ser. No. 09/688,993, filed Oct. 16, 2000, now U.S. Pat. No. 6,285,600 B1, issued Sep. 4, 2001, which is a continuation of application Ser. No. 09/407,614, filed Sep. 28, 1999, now U.S. Pat. No. 6,134,152, issued Oct. 17, 2000, which is a divisional of application Ser. No. 09/038,667, filed Feb. 27, 1998, now U.S. Pat. No. 6,005,812, issued Dec. 21, 1999. 
     
    
     
       BACKGROUND OF THE INVENTION  
         [0002]    Technical Field: This invention relates in general to semiconductor memories, such as Dynamic Random Access Memories (DRAMs), and, more specifically, to devices and methods for supplying current to semiconductor memories from external sources to support boosted voltages, such as wordline voltages and isolation gate voltages, within such memories while they are tested.  
           [0003]    State of the Art: Dynamic Random Access Memories (DRAMs) typically include various circuitry that will only operate properly when supplied with a voltage (denoted “V CCP ”) that is “boosted” above the supply voltage (denoted “V CC ”). Such circuitry includes, for example, wordlines, which require a boosted voltage V CCP  to store a full V CC  level in a memory cell, and isolation gates, which require a boosted voltage V CCP  to pass a full V CC  level along a digit line.  
           [0004]    In order to supply the boosted voltage V CCP , DRAMs typically include an internal charge pump that generates the boosted voltage V CCP  on one or more capacitors. These capacitors are typically relatively large so they can supply sufficient current I CCP  to meet any demands that may be made on the charge pump by the DRAM circuitry.  
           [0005]    During DRAM compression-mode testing, the demand for current I CCP  from the charge pump may be many times the demand for current I CCP  during normal memory operations. This is because many more wordlines and isolation gates may be operated at the same time during compression-mode testing than during normal memory operations.  
           [0006]    Consequently, DRAM designers typically find it necessary to provide a DRAM with a charge pump having capacitors of sufficient size to meet the increased demand for current I CCP  experienced during compression-mode testing, despite the fact that much smaller capacitors would suffice for normal memory operations. As a result, DRAMs shipped to customers typically include charge pumps with capacitors many times the size required for even the most rigorous field applications. These over-sized capacitors unnecessarily occupy integrated circuit (IC) die “real estate,” and thus can either limit the functional circuitry that can be provided in a DRAM, or necessitate a larger die than is desirable for a DRAM.  
           [0007]    Therefore, there is a need in the art for a device and method for providing current I CCP  to a DRAM or other semiconductor memory during testing without having to use a charge pump with over-sized capacitors.  
         SUMMARY OF THE INVENTION  
         [0008]    A semiconductor device, such as a DRAM or other semiconductor memory, in accordance with this invention includes a conductor, such as a voltage bus, that distributes a boosted voltage (e.g., V CCP ) within the semiconductor device. Internal boosting circuitry, such as a voltage regulator, a ring oscillator, and a charge pump, boosts a voltage level on the conductor upon sensing that the voltage level has fallen below a minimum level, such as a preset minimum. A terminal of the semiconductor device, such as a bond pad, receives current from a current source external to the device, and a switching circuit conducts current received through the terminal to the conductor in response to the internal boosting circuitry sensing that the voltage level on the conductor has fallen below the minimum level. As a result, the external current augments the efforts of the internal boosting circuitry to boost the voltage level on the conductor, thereby providing the necessary support for the boosted voltage during times of peak demand, such as during testing, without the need to provide oversized capacitors, for example, in the internal boosting circuitry. The switching circuit itself may be based on one or more pump circuits controlling one or more NMOS transistor switches that conduct the external current to the conductor when activated.  
           [0009]    In other embodiments of this invention, the semiconductor device described above may be incorporated into an electronic device, or may be fabricated on the surface of a semiconductor substrate, such as a semiconductor wafer.  
           [0010]    In a further embodiment of this invention, a boosted voltage in a semiconductor device is supported by boosting the boosted voltage using an externally generated current when the boosted voltage falls below a minimum level. The boosted voltage may be boosted by, for example, sensing that the boosted voltage has fallen below the minimum level. A charge pump in the semiconductor device can then be driven to boost the boosted voltage above the minimum level, and a switching circuit in the semiconductor device can be driven to conduct the externally generated current to augment the boosting of the boosted voltage by the charge pump. 
       
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS  
       [0011]    [0011]FIG. 1 is a block diagram of a Dynamic Random Access Memory (DRAM) device in accordance with this invention;  
         [0012]    [0012]FIG. 2 is a schematic and block diagram of a switching circuit of the DRAM device of FIG. 1;  
         [0013]    [0013]FIG. 3 is a block diagram of an electronic system incorporating the DRAM of FIG. 1; and  
         [0014]    [0014]FIG. 4 is a diagram of a semiconductor wafer having a surface on which the DRAM of FIG. 1 is fabricated. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0015]    As shown in FIG. 1, a Dynamic Random Access Memory (DRAM) device  10  in accordance with this invention includes a boosted voltage V CCP  bus  12  for distributing the boosted voltage V CCP  within the DRAM device  10 . Although this invention will be described with reference to the DRAM device  10 , it will be understood by those having skill in the field of the invention that the invention includes a wide variety of semiconductor devices within its scope, and is not limited to DRAM devices.  
         [0016]    While the DRAM device  10  is operating, a conventional voltage regulator  14  senses the level of the boosted voltage V CCP  on the bus  12  and outputs an oscillator activation signal REGDIS* when the level of the boosted voltage V CCP  drops below a preset minimum. In response to the oscillator activation signal REGDIS*, a conventional ring oscillator  16  outputs a clock signal CLK that activates a conventional charge pump  18 . This causes the charge pump  18  to “boost” the level of the boosted voltage V CCP  above the preset minimum until it reaches a preset maximum, at which point the voltage regulator  14  deactivates the oscillator activation signal REGDIS*, causing the ring oscillator  16  to deactivate the clock signal CLK and thereby deactivating the charge pump  18 .  
         [0017]    During testing, in particular compression-mode testing, a test signal TEST deactivates an input buffer  20  through which signals entering a bond pad  22  normally pass during non-test mode operations of the DRAM device  10 , and enables a switching circuit  24 . The bond pad  22  may be any bond pad that is not needed during testing, such as an unused address signal pad or a no-connection (NC) pad. Once enabled, the switching circuit  24  operates in response to the clock signal CLK by passing current I CCP  from an external current source  26  attached to the bond pad  22  to the bus  12 , thereby boosting the boosted voltage V CCP  above its preset minimum.  
         [0018]    Thus, the switching circuit  24  supports the increased demand on the boosted voltage V CCP  during testing by providing the current I CCP  from an external source. This allows the capacitors (not shown) of the charge pump  18  to be sized for the lesser demand on the boosted voltage V CCP  experienced during normal memory operations rather than the increased demand experienced during test operations. As a result, less die “real estate” is used for the capacitors of the charge pump  18 , so the DRAM device  10  can be manufactured on a smaller integrated circuit (IC) die, or more functional circuitry can be provided in the DRAM device  10 .  
         [0019]    As shown in detail in FIG. 2, during testing, an active (i.e., high) test signal TEST enables the switching circuit  24  by causing an inverter  27  to output a low. Assuming, for the moment, a steady-state condition in which the clock signal CLK has not been activated by the ring oscillator  16  (FIG. 1), the low output by the inverter  27  causes a NOR gate  28  to output a high which, in turn, causes an inverter  30  to output a low and an inverter  32  to output a high. The high from the inverter  32  causes a NOR gate  34  to output a low which, when combined with the low from the inverter  30 , causes a NOR gate  36  to output a high. The low from the NOR gate  34  causes an inverter  38  to output a high which, in turn, causes another inverter  40  to output a low, and the high from the NOR gate  36  causes an inverter  42  to output a low which, in turn, causes yet another inverter  44  to output a high. The high from the inverter  44  causes a NOR gate  46  and a NOR gate  48  to both output a low. The low from the NOR gate  48  and the low from the inverter  40  cause a NOR gate  50  to output a high which, in turn, causes a NOR gate  52  to output a low.  
         [0020]    The lows output by the NOR gates  46  and  52  ground node “A” of capacitors  54  and  56 . Meanwhile, the high test signal TEST activates NMOS transistors  58  and  60 , thereby storing the supply voltage V CC , less the threshold voltage V T  of the transistors  58  and  60 , on node “B” of the capacitors  54  and  56 . Helper NMOS transistors  62  and  64  help to pull node “B” of the capacitors  54  and  56  up to V CC −V T .  
         [0021]    Once the clock signal CLK is activated by the ring oscillator  16  (FIG. 1), a rising edge of the clock signal CLK flips the output of the NOR gate  28  to a low, causing the inverter  30  to output a high and the inverter  32  to output a low. The high from the inverter  30  causes the NOR gate  36  to output a low which, when combined with the low from the inverter  32 , causes the NOR gate  34  to output a high. The low from the NOR gate  36  causes the inverter  42  to output a high and the inverter  44  to output a low, and the high from the NOR gate  34  causes the inverter  38  to output a low and the inverter  40  to output a high.  
         [0022]    The low from the inverter  44  causes the NOR gate  46  to begin to output a high pulse. This high pulse lasts until the high output of the inverter  40  causes the NOR gate  50  to output a low, causing the NOR gate  48  to output a high and thereby driving the output of the NOR gate  46  low again. The output of the NOR gate  52  remains low on the rising edge of the clock signal CLK.  
         [0023]    The high pulse from the NOR gate  46  raises node A of the capacitor  54  up to the supply voltage V CC  during the pulse, which “boosts” the voltage on node B of the capacitor  54  up to 2V CC −V T  (because V CC −V T  is already stored across the capacitor  54 ). This “boosted” voltage causes the NMOS transistors  58  and  62  to turn off, and turns on an NMOS transistor  66 , allowing the transistor  66  to pass the external current I CCP  through to the V CCP  bus  12 .  
         [0024]    A conventional clamp  68  keeps the voltage on node B of the capacitor  54  from exceeding V CC +4V T , but it can, of course, be constructed to limit the node to any desired maximum voltage. Also, the boosted voltage on node B of the capacitor  54  causes the transistor  64  to pass a full supply voltage V CC  level through to node B of the capacitor  56  for storage thereon.  
         [0025]    With the clock signal CLK still activated, a falling edge of the clock signal CLK flips the output of the NOR gate  28  to a high, causing the inverter  30  to output a low and the inverter  32  to output a high. The high from the inverter  32  causes the NOR gate  34  to output a low which, when combined with the low from the inverter  30 , causes the NOR gate  36  to output a high. The low from the NOR gate  34  causes the inverter  38  to output a high and the inverter  40  to output a low, and the high from the NOR gate  36  causes the inverter  42  to output a low and the inverter  44  to output a high.  
         [0026]    The low from the inverter  40  causes the NOR gate  52  to begin to output a high pulse. This high pulse lasts until the high output of the inverter  44  causes the NOR gate  48  to output a low, causing the NOR gate  50  to output a high and thereby driving the output of the NOR gate  52  low again. The output of the NOR gate  46  remains low on the falling edge of the clock signal CLK.  
         [0027]    The high pulse from the NOR gate  52  raises node A of the capacitor  56  up to the supply voltage V CC  during the pulse, which “boosts” the voltage on node B of the capacitor  56  up to 2V CC  (because V CC  is already stored across the capacitor  56 ). This “boosted” voltage causes the NMOS transistors  60  and  64  to turn off, and turns on an NMOS transistor  70 , allowing the transistor  70  to pass the external current I CCP  through to the V CCP  bus  12 .  
         [0028]    A conventional clamp  72  keeps the voltage on node B of the capacitor  56  from exceeding V CC +4V T , but it can, of course, be constructed to limit the node to any desired maximum voltage. Also, the boosted voltage on node B of the capacitor  56  causes the transistor  62  to pass a full supply voltage V CC  level through to node B of the capacitor  54  for storage thereon. As a result, subsequent operation of the switching circuit  24  periodically boosts node B of the capacitor  54  up to 2V CC , rather than 2V CC −V T  as described above, because a full V CC  level is now stored across the capacitor  54 .  
         [0029]    During normal operations of the DRAM device  10  (FIG. 1), the test signal TEST is low, which causes the inverter  27  to output a high, thereby turning on NMOS transistors  74  and  76 , and pulling node B of the capacitors  54  and  56  to ground through NMOS transistors  74 ,  76 ,  78 , and  80 . As a result, the NMOS transistors  66  and  70  are off, and the V CCP  bus  12  is isolated from the bond pad  22  (FIG. 1).  
         [0030]    It should be understood that, as a group, the inverters  27 ,  30 ,  32 ,  38 ,  40 ,  42 , and  44 , and the NOR gates  28 ,  34 ,  36 ,  46 ,  48 ,  50 , and  52 , may be referred to generally as “pump control circuitry.” It should also be understood that, as a group, the capacitor  54  and the NMOS transistor  58  may be referred to as a “pump circuit,” and that, as a group, the capacitor  56  and the NMOS transistor  60  may also be referred to as a “pump circuit.” Further, it should be understood that the NMOS transistors  66  and  70  may be referred to as “switches.” 
         [0031]    As shown in FIG. 3, an electronic system  82  includes an input device  84 , an output device  86 , a processor device  88 , and a memory device  90  incorporating the DRAM device  10  of FIG. 1. Of course, any one of the input, output, and processor devices  84 ,  86 , and  88  can also incorporate the DRAM device  10 .  
         [0032]    As shown in FIG. 4, the DRAM device  10  of FIG. 1 is fabricated on the surface of a semiconductor wafer  92 . However, the DRAM device  10  may also be manufactured on a wide variety of semiconductor substrates other than a semiconductor wafer including, for example, a Silicon on Sapphire (SOS) substrate, a Silicon on Glass (SOG) substrate, and a Silicon on Insulator (SOI) substrate.  
         [0033]    Although this invention has been described with reference to particular embodiments, the invention is not limited to these described embodiments. Rather, the invention is limited only by the appended claims, which include within their scope all equivalent devices and methods that operate according to the principles of the invention as described.