Abstract:
A data compression architecture includes a shift register with multiple shift register elements. A data input receives input data characters, and applies each received input data character to the shift register, such that the received input data character is stored in each shift register element of said shift register in turn. Logic circuitry is associated with each shift register element of the shift register, for detecting a match when the comparison circuitry determines that a sequence of two or more received input data characters is equal to a sequence stored in the shift register. A flush input receives a data flush input signal, and applies a received data flush input signal to the logic circuitry associated with each shift register element of the shift register, such that no match is detected by said logic circuitry when the data flush input signal is received.

Description:
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   BACKGROUND OF THE INVENTION 
   This invention relates to data compression, and in particular to a hardware architecture that can be used to achieve data compression in accordance with the Lempel-Ziv compression algorithm. 
   When transmitting data over a communications channel, or when storing data, it is often useful to be able to compress the data, in order to reduce the resources required to transmit or store the data. Data compression techniques rely on the fact that most useful data contains patterns, which can be exploited in order to reduce the amount of data required in order to represent the source data. For example, when the source data contains one or more repeated sequences of characters, each of these can be represented more efficiently by a particular code. Provided of course that the code contains fewer bits of data than the sequence of characters, this representation reduces the amount of data required to represent the source data. 
   One well known data compression algorithm is the Lempel-Ziv data compression algorithm, originally described in the paper “A Universal Algorithm for Sequential Data Compression”, Jacob Ziv and Abraham Lempel, IEEE Transactions on Information Theory, vol. IT-23, no. 3, May 1977, pages 337–343. In use of the Lempel-Ziv algorithm, a code dictionary is built up, based on the received data string. The received data can for example represent text made up of characters. Then, the available codes can be assigned to respective character strings, as they appear in the received text. 
   In practice, this is achieved by comparing received character strings with previously received character strings. More specifically, it is necessary to find the longest of the previously received character strings that can be matched with a newly received character string. The next character of the newly received character string is then combined with that longest of the previously received character strings to form a character string that can be represented by a new code. 
   It is known to provide a hardware apparatus for comparing received data with previously received character strings. 
   For example, U.S. Pat. No. 5,003,307 to Whiting et al discloses an apparatus comprising a shift register. A newly received character is input to a first stage of the shift register. At the same time, the newly received character is compared with the characters stored in the other stages of the shift register. Logic circuitry is used to identify stages in the shift register at which the newly received character matches the stored characters. This process continues until the string of newly received characters no longer matches the strings of previously received characters at any of the stages of the shift register. At that time, the new code is output. 
   However, this architecture has the disadvantage that, when a match occurs, the encoding process has to stop for one clock cycle while a new search is started. This reduces the speed at which data can be processed by the device. 
   Jung and Burleson, in the paper “Efficient VLSI for Lempel-Ziv Compression in Wireless Data Communication Networks”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 6, no. 3, September 1998 propose an alternative architecture. However, it is desirable to improve the speed of operation of a compression architecture. 
   BRIEF SUMMARY OF THE INVENTION 
   According to the present invention, there is provided a data compression architecture, including a shift register with multiple shift register elements. A data input receives input data characters, and applies each received input data character to the shift register, such that the received input data character is stored in each shift register element of said shift register in turn. Comparison circuitry is associated with each shift register element of the shift register, for comparing each received input data character with a respective input data character stored in said shift register element of the shift register. Logic circuitry is associated with each shift register element of the shift register, for detecting a match when the comparison circuitry determines that the received input data character is equal to the respective input data character stored in the shift register element of the shift register. A flush input receives a data flush input signal, and applies a received data flush input signal to the logic circuitry associated with each shift register element of the shift register, such that no match is detected by said logic circuitry when the data flush input signal is received. 
   According to the present invention, there is provided a data compression architecture, comprising a shift register, comprising multiple shift register elements. A data input receives input data characters, and applies each received input data character to the shift register, such that the received input data character is stored in each shift register element of the shift register in turn. Comparison circuitry is associated with each shift register element of the shift register, for comparing each received input data character with a respective input data character stored in the shift register element of the shift register. Logic circuitry is associated with each shift register element of the shift register, for detecting a match when the comparison circuitry determines that the received input data character is equal to the respective input data character stored in the shift register element of the shift register in two consecutive clock cycles, and for supplying a match output when the received input data character is equal to the respective input data character stored in the shift register element of the shift register in two consecutive clock cycles and when a match output criterion is met. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block schematic diagram of a shift register structure, forming part of a compression architecture in accordance with the present invention. 
       FIG. 2  is a block schematic diagram of a compression architecture in accordance with the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1  shows a shift register structure  10 , forming part of a compression architecture, for achieving data compression, according to the Lempel-Ziv algorithm, which is well known to the person skilled in the art, and will not be described in detail herein, except in so far as is necessary for an understanding of the present invention. 
   In the preferred embodiment of the invention, the compression architecture is implemented in a field-programmable gate array (FPGA). However, it will be appreciated that the architecture can be implemented in any form of device, as required. 
   The Lempel-Ziv algorithm operates by detecting when a sequence of received characters matches a sequence that has been previously received. The algorithm proceeds on a character-by-character basis. That is, when a first character is received, it may be found that the same character has been received on many previous occasions. When a second character is received, it may then be found that the sequence of the first and second characters was received on some fraction of those previous occasions. Further characters are then received, until the longest previously received sequence, matching that newly received sequence, is found. 
   In order to detect the matching of the sequences, a shift register structure is used, as shown in  FIG. 1 . As will be apparent from the following description,  FIG. 1  shows only three stages of the shift register, for ease of illustration and explanation. However, the shift register structure can contain any desired number of stages and, in a practical embodiment of the invention, the shift register structure can contain several hundreds or several thousands of stages. The data stored in the shift register structure in effect makes up a dictionary of received character strings. 
   A flip-flop  100  is connected to an input  102  of the circuit, and receives an input data word. Typically, the input data word is 8 bits long, and may for example represent a character in a text, although the algorithm can be used with data of many types. 
   During a following clock cycle, the input data word is clocked into the first stage of the shift register structure. In  FIG. 1 , and the following description, components of the first stage of the shift register structure are indicated by the suffix “a” appended to their reference numerals, components of the second stage of the shift register structure are indicated by the suffix “b” appended to their reference numerals, and components of the third stage of the shift register structure are indicated by the suffix “c” appended to their reference numerals. These stages all contain the same components, and operate in the same way. 
   Thus, in the clock cycle following its receipt, the input data word is clocked into the shift register element  104   a  of the first stage of the shift register structure. The shift register elements  104   b ,  104   c  are connected to the shift register element  104   a , such that, during subsequent clock cycles, the input data word is clocked into the shift register element  104   b , and then into the shift register element  104   c , and so on. 
   The output of the shift register element  104   a  is also connected to a first input of a match block  106   a . In the other stages of the shift register structure, the outputs of the shift register elements  104   b ,  104   c  etc are also connected to the respective first inputs of the match blocks  106   b ,  106   c . The output of the flip-flop  100  is connected to a second input of the match block  106   a , as well as to the second inputs of the other match blocks  106   b ,  106   c.    
   The match block  106   a  outputs a logical “1” when the value stored in the flip-flop  100  matches the value stored in the shift register element  104   a.    
   The output of the match block  106   a  is connected to a first input of a logical AND gate  108   a , the operation of which will be described in more detail below. 
   The circuit also includes a flush shift register, containing a respective one-bit flush shift register element  110   a ,  110   b ,  110   c , etc associated with each stage of the shift register structure. During operation of the circuit, it may be desirable to clear the dictionary of received character strings. For example, it is often the case that the most efficient compression of received data can be achieved by comparing the received data only with recently received data, rather than with data that was received less recently. More specifically, when the source of received data changes, it is usually desirable for the new data to be compressed without any reference to the previous set of data. 
   However, it is not desirable simply to clear the shift register elements  104   a ,  104   b ,  104   c  etc, because this would mean that a received string of 0&#39;s would appear to match the stored data. 
   An enable input  112  is connected to the input of the flush shift register element  110   a , and is clocked on subsequent cycles to the inputs of the flush shift register elements  110   b ,  110   c , etc. When the circuit is initialized, that is, when the first data word is input to the flip-flop  100  from the input  102 , a logical “1” is input at the enable input  112 , and this high level signal is loaded sequentially into each flush shift register element of the flush shift register on subsequent clock cycles. 
   A flush input  114  is connected, inverted, to the clear inputs of each of the flush shift register elements  110   a ,  110   b ,  110   c , etc. When it is desired to clear the dictionary, for example when data is first received from a new dataset, a logical “1” is input at the flush input  114 . All of the flush shift register elements  110   a ,  110   b ,  110   c  are then cleared within a single clock cycle. 
   Thus, the output of any one of the flush shift register elements  110   a ,  110   b ,  110   c  is high only when the logical “1”, input at the enable input  112 , has propagated sufficiently far along the flush shift register to reach that element, and only for so long as a logical “1” has not been input at the flush input  114 . 
   The output of the flush shift register element  110   a  is connected to a second input of the logical AND gate  108   a  mentioned above. The outputs of the flush shift register elements  110   b ,  110   c  etc in the other stages are connected to the second inputs of the corresponding logical AND gates  108   b ,  108   c  etc. 
   Thus, provided that the output of the flush shift register element  110   a  is high, the logical AND gate  108   a  outputs a high signal, whenever the match block  106   a  outputs a high signal. Thus, this arrangement allows the dictionary to be flushed in a single clock cycle, or even during continuous data input. 
   The output of the logical AND gate  108   a  is connected to a register  116   a . The output of the register  116   a  is connected to a further register  118   a . Any signal input to the register  116   a  is thus applied to the further register  118   a  in the subsequent clock cycle. 
   The outputs of the register  116   a  and the further register  118   a  are applied to first and second inputs respectively of a three-input logical AND gate  120   a . The output of the three-input logical AND gate  120   a  is then applied to a further register  122   a . The output of the further register  122   a  is applied to the first input of an OR gate  124   a.    
   The outputs of the further registers  122   a ,  122   b ,  122   c  etc in all of the stages of the circuit are then applied to respective inputs of a NOR gate  126 . 
   The output of the NOR gate  126  forms a DONE signal, which is applied to the second inputs of the OR gates  124   a ,  124   b ,  124   c  etc in all of the stages of the circuit. Then the outputs of the OR gates  124   a ,  124   b ,  124   c  etc are applied to the respective third inputs of the three-input logical AND gate  120   a.    
   In operation of the circuit, when the value stored in the flip-flop  100  matches the value stored in the shift register element  104   a , the match block  106   a  outputs a logical “1”. Assuming that the output of the flush shift register element  110   a  is high, the logical AND gate  108   a  outputs a high signal, and this high signal is clocked into the register  116   a . The high signal is then clocked into the register  118   a  during the next clock cycle. 
   The AND gate  120  therefore receives high signals on its first and second inputs when the register  116   a  produces a high output in two consecutive clock cycles. This occurs when a sequence of two consecutive values, received and stored in the flip-flop  100  during consecutive clock cycles, matches a sequence of two values stored in the shift register element  104   a  during those two clock cycles, given that the received data signals are being clocked through the shift register elements  104   a ,  104   b ,  104   c  . . . during consecutive clock cycles. 
   In that situation, then, if the signal on the third input of the AND gate  120   a , from the output of the OR gate  124   a , is also high, then the output of the AND gate  120   a  will be high, and the match register  122   a  will be set. 
   Thus, the match register  122   a  can be set only when a sequence of two or more of the received input data characters matches a sequence of the stored, previously received, data characters. 
   Since the output of the match register  122   a  is connected to one of the inputs of the OR gate  124   a , then, if the match register  122   a  was previously set, it will remain set during the subsequent clock cycle, if the AND gate  120  is receiving high signals on its first and second inputs. 
   Moreover, the match register  122   a  will be set, provided that the AND gate  120  is receiving high signals on its first and second inputs, when the DONE signal is high. 
   When one or more of the match registers  122   a ,  122   b ,  122   c  etc in the different stages is set, the DONE signal on the output of the NOR gate  126  is low. The DONE signal on the output of the NOR gate  126  only becomes high when none of the match registers  122   a ,  122   b ,  122   c  etc in the different stages is set. This occurs when a received sequence of two or more of the received input data characters, matching a sequence of the stored input data characters, comes to an end. 
     FIG. 2  is a block schematic diagram of a data compression architecture including the shift register structure  10 . More specifically, the shift register structure  10  of the data compression architecture receives input data, which is supplied to the flip-flop  100  as described above, an enable signal, which is applied to the enable input  112 , and a flush signal, which is applied to the flush input  114 . 
   In order to produce an output code in the form &lt;index, runlength&gt;, the data compression architecture also includes a run length counter  20  and an index generator  30 , each connected to the shift register structure  10 . The outputs of the run length counter  20  and the index generator  30  are then supplied to an encoder  40 , so that the encoder  40  can provide the output encoded data. 
   The run length counter  20  receives the DONE signal from the NOR gate  126 , and is used to count the number of consecutive matches between the received data and the stored data. Since the combination of the registers  116   a ,  118   a  means that a match is detected by the AND gate  120  only when two consecutive characters match, the run length counter is initialized to the value 2, and increases the count by 1 for each clock cycle in which a DONE signal is not received. When a DONE signal is then received, the counter value indicates the run length. 
   The index generator  30  operates using a unary to binary converter, taking as its input the vector formed by the outputs of the registers  122   a ,  122   b ,  122   c , etc. Typically, at the end of a run, only one of the registers  122   a ,  122   b ,  122   c , etc will be active, and so the required index value can easily be obtained as the index of the active register  122 . If two or more of the registers  122   a ,  122   b ,  122   c , etc are active, a priority encoder (not shown) can be used to select the required index value as the index of the active register  122  having the lowest index value. 
   The encoder  40  can then combine the outputs of the run length counter  20  and the index generator  30  to produce the required output encoded data. 
   As mentioned above, this structure produces output data efficiently in the form &lt;index, runlength&gt;. That is, the structure is efficient in the sense that it can be initialized on the fly, without needing to be halted before the next match can be detected. 
   As an alternative, the shift register structure can be adapted such that the compression architecture produces output data efficiently in the form &lt;index, runlength, last symbol&gt;. In order to produce this form of output data efficiently, the shift register structure needs to detect when any single input character matches a stored character, rather than only detecting two or more consecutive matches. 
   In order to detect a single input character matching a stored character, only one of the registers  116 ,  118  need be provided, with that register being connected to receive the signal from the AND gate  108 , and the output of that register then being applied to the AND gate  120 . 
   When the compression architecture is to produce output data in the form &lt;index, runlength, last symbol&gt;, it needs to include a last symbol generator, for detecting the last symbol, which is to form part of the encoded data output. The last symbol in this case is the last input to the shift register. 
   In an embodiment of the invention, the second register  118  can be dynamically switchable into and out of the circuit. Thus, when it is desired to produce output data in the form &lt;index, runlength, last symbol&gt;, the second register  118  can be switched out of the circuit, while, when it is desired to produce output data in the form &lt;index, runlength&gt;, the second register  118  can be switched into the circuit. 
   When the DONE signal has gone high, and the end of a matching character string has been detected, the encoded data is output. Thereafter, in the immediately following clock cycle, any match register  122   a ,  122   b ,  122   c  etc can be set, provided that the AND gate  120  is receiving high signals on its first and second inputs. 
   The data can therefore be continuously processed, without requiring the circuit to be stopped when the end of a matching character string is reached. 
   The shift register structure described above allows unlimited pipelining to be inserted, for example between the input  102  and the register  116 , as required to allow the architecture to operate at the required speed. 
   For example, there may be pipeline delays required to forward the last input to the output, when the structure produces data in the form &lt;index, runlength, last symbol&gt;. Similarly, pipeline delays may be required for the unary to binary circuit in the index generator  30 , and specifically the internal priority circuit, to operate at speed. Further, the run length counter  20  may be offset in time from the rest of the circuit. 
   The output (code word) of the circuit can be independently calculated from the main part of the circuit, and can therefore be infinitely pipelined. If the runlength exceeds an arbitrary maximum (e.g. 32), a DONE signal can be forced. If the counter is offset in timeslots from the main part of the circuit, an offset can be applied to the count value to flag an end of run. For example, if the counter starts 2 cycles after the main circuit, and the maximum run length is 32, then the end of run will be flagged when the count value is 30. 
   There is therefore described a circuit which allows high speed processing of received data in accordance with the Lempel-Ziv algorithm.