Abstract:
A domino logic circuit contained within an integrated circuit includes a dynamic logic circuit and an intermediate logic circuit. The intermediate logic circuit includes a pull-up transistor having a source terminal coupled to a source voltage line and an n-block transistor having a source terminal connected to a low ground voltage line.

Description:
CLAIM OF PRIORITY 
     This application is a continuation and claims priority under 35 USC §120 to U.S. patent application Ser. No. 09/846,519, now U.S. Pat. No. 6,498,514, filed on Apr. 30, 2001, the entire contents of which are hereby incorporated by reference. 
    
    
     TECHNICAL FIELD 
     This invention relates to domino circuits. 
     BACKGROUND 
     Traditional domino-CMOS logic circuits include ‘dynamic’ and ‘static’ logic blocks. The ‘dynamic’ blocks include n-channel gates which are first pre-charged and then perform logical functions during an evaluation phase. The output of the dynamic gates is input to a ‘static’ block, typically a CMOS inverter. To utilize the time dissipated by the CMOS inverter, the static block may be replaced by other static CMOS gates or by a block of pseudo-NMOS logic. Each replacement circuit has potential drawbacks in terms of the overall speed and power consumption of the domino-CMOS circuit. 
    
    
     DESCRIPTION OF DRAWINGS 
     FIG. 1 is a schematic representation of a first embodiment of a domino circuit. 
     FIG. 2 is a schematic representation of a traditional pseudo-NMOS gate and an enhanced pseudo-NMOS gate. 
     FIG. 3 is a schematic representation of a second embodiment of a domino circuit. 
    
    
     Like reference symbols in the various drawings indicate like elements. 
     DETAILED DESCRIPTION 
     As used herein, ‘N-block’ refers to a circuit which includes one or more n-channel transistors. 
     Referring to FIG. 1, circuit  100  includes a series of domino circuits  100 A- 100 N. Each domino circuit  100 A- 100 N includes an intermediate logic block  105 A- 105 N. One or more of the intermediate logic blocks,  105 A- 105 N, may be implemented as a CMOS circuit or a pseudo-NMOS circuit. In an embodiment, according to the invention, intermediate logic block  105 A includes enhanced pseudo-NMOS logic circuit  280 . 
     Each domino circuit  100 A- 100 N includes one or more dynamic logic gates, represented by N-Block  104 A- 104 N. N-Block  104 A- 104 N gates alternate between pre-charge and evaluation phases, according to signal CLK  106  and DELAYED CLK B-N, respectively. N-block  104 A- 104 N gates evaluate input  130 A- 130 N signals only during the respective evaluation phases of each domino circuit  100 A- 100 N. For example, consider the operation of domino circuit  100 A: in the pre-charge phase, CLK  106  is ‘0’, PUA turns on, pre-charging (‘pulling up’) the output  120 A to ‘1’. During the evaluation phase, CLK  106  goes to ‘1’, PUA is turned off, and the output  120 A is either discharged to ‘0’, or, left at ‘1’ depending on the evaluation of input  130 A signal by N-block  104 A. 
     Domino circuit  100 A- 100 N may also include n-channel transistor NUA-NUN, connected in series with the N-blocks  104 A- 104 N. In operation, transistor NUA-NUN is turned off during the pre-charge phase (CLK  106  at ‘0’), therefore reducing the power dissipation of the N-block  104 A- 104 N transistors. 
     Circuit  100  includes domino circuits  100 A- 100 N, where each domino circuit is connected to the succeeding domino circuit. The CLK  106  signal is connected a series of inverter pairs,  108 A- 108 N and  100 A- 100 N, to provide a DELAYED CLK B-N for the pre-charge and evaluation phases of each succeeding domino circuit  100 B- 100 N. For example, inverters  108 A and  110 A provides a sufficient time delay for domino circuit  100 A to evaluate and propagate signals to the input  130 B of dynamic N-Block  104 B before DELAYED CLK B begins the evaluation phase in domino circuit  100 B. 
     In an embodiment, according to the invention, intermediate logic block (ILB)  105 A is implemented as enhanced pseudo-NMOS logic circuit  280 . Circuit  280  includes inverter  204 , p-channel transistor P 0 , N-block  202 , input  120 A, output  130 B, Vcc and Vss 2 . The configuration of P 0  and N-block  202  is similar to the configuration of dynamic logic blocks  104 A- 104 N as discussed above, however, since the input of P 0  is connected to the output of inverter  204 , P 0  will be off during the pre-charge phase of N-block  104 A (when CLK  106  is ‘0’). By turning P 0  off during the pre-charge phase, the D.C. power consumption of circuit  280  is significantly reduced, that is, circuit  280  only dissipates D.C. power conditionally when N-Block  202  transistors are turned on and evaluating input  120 A. As shown, N-Block  202  includes transistors N 1  and N 2 , with both N 1  and N 2  connected at their gate terminals to input  120 A. This configuration of N-Block  202  is an example to help explain the operation of circuit  280 , other N-Block  202  gate configurations are possible, and other inputs to the N-Block  202  transistors are possible. 
     Referring to circuit  280 , during the pre-charge phase, CLK  106  is ‘0’, PUA is on and output  120 A is pulled-up to ‘1’. Since  120 A is connected to the input of N-Block  202  transistors of circuit  280 , N 1  and N 2  are turned on, pulling-down output  130 B to ‘0’. CLK  106  ‘0’ is input to inverter  204 , which outputs a ‘1’ to P 0 , turning P 0  off, which substantially blocks the D.C. current flow through N-Block  202  transistors during the pre-charge phase. In the evaluation phase, CLK  106  goes to ‘1’, turning off PUA, and allowing N-Block  104 A to evaluate INPUT  130 A signal. Output  120 A is either held at ‘1’, or pulled-down to ‘ 0 ’ by N-Block  104 A depending on the INPUT  130 A signal. The ‘1’ at CLK  106  is input to inverter  204 , which outputs a ‘0’ to P 0 , turning on P 0  so that P 0  is ready to pull-up output  130 B depending on the evaluation of input  120 A by N-Block  202  transistors. If  120 A stays at ‘1’ N-Block  202  transistors N 1  and N 2  stay on, therefore output  130 B remains pulled-down to ‘0’. If  120 A goes to ‘0’, N-block  202  transistors N 1  and N 2  turn off, allowing P 0  to pull-up the output  130 B to ‘1’. 
     As described above, the control signal for turning transistor P 0  off and on is derived from the inverted  204  CLK  106  signal. In an alternate embodiment, the control signal to P 0  could be generated from other control circuitry, as long as the control signal is derived with reference to the CLK  106  signal or the evaluation phases of N-Block  104 A. 
     Circuit  280  also includes a connection to Vcc, the source voltage, and connections to a “low-ground”, Vss 2 , which represents a voltage level below the common ground of the circuit, Vss. The benefit of providing Vss 2  to the source terminals of N-Block  202  can be explained with reference to operation of a traditional pseudo NMOS circuit. 
     Referring to FIG. 2, traditional pseudo-NMOS circuit  250 , which includes a connection to Vss at the source terminals of N-block  202 , is shown. Pseudo-NMOS circuits are referred to as ‘ratio-logic’, where the device sizes (the width to length ratio) of the p-channel transistor and the n-channel transistors are ‘sized’ for proper operation of the circuit. Referring to traditional pseudo-NMOS circuit  250 , the pull-up device PU 25  has to be significantly weaker (down-sized) than the pull-down network  202  in order for the pull-down network  202  to produce an output  254  logic ‘low’ that is sufficiently close to Vss. The down-sizing of pull-up device PU 25  increases the time required to pull-up the output  254  during a ‘low’-to-‘high’ transition and reduces the overall speed of circuit  250 . 
     In enhanced pseudo-NMOS logic circuit  280 , because the source terminals of the N-Block  202  transistors are connected to Vss 2 , an output  130 B ‘low’ is produced that is sufficiently close to Vss but without requiring a significant down-sizing of pull-up device P 0 . In both circuit  250  and  280 , when both the pull-up and pull-down networks are “ON”, they are effectively acting as two serially connected resistances between Vcc and Vss in circuit  250 , and between Vcc and Vss 2  in circuit  280 . As a result, using the same device sizes in circuit  250  and  280 , and with reference to common ground Vss, the voltage level produced at the output  130 B of circuit  280  at a logic ‘low’, is at a lower level than can be produced at output  254  of circuit  250 . 
     The lower voltage level for logic ‘LOW’ at output  130 B can be utilized in two different ways. First, dynamic logic gates, such as gates  104 A- 104 N (FIG. 1) have a small input-‘LOW’ dc-noise margin. If the output  130 B is connected to the input of another dynamic logic block, such as  104 B, the dc-noise level input to the dynamic gate  104 B is reduced. Second, if the voltage level for the output ‘low’  130 B is the same as that of the traditional pseudo-NMOS gate  250 , then the pull-up device PU 0  in  280  can be sized larger than the pull-up device PU 25  in  250 . This allows circuit  280  to produce faster output ‘low’-to-‘high’ transitions and an increase in the overall speed of circuit. 
     When utilizing a low ground Vss 2 , the source-to-bulk PN junctions of the N-block  202  devices are in forward bias. The operation of circuit  280  is achieved by providing the absolute value of Vss 2  as large as possible but without exceeding the source-to-bulk PN-junction&#39;s turn-on voltage of the N-Block  202  transistors being used. Using n-channel transistors made from silicon, which have a diode turn-on voltage of approximately 0.5V, Vss 2  can be provided as near as possible to −0.5V. However, providing Vss 2  as any voltage lower than Vss without exceeding the diode turn-on voltage will also improve the operation of circuit  280 . 
     Referring to FIG. 3, in another embodiment of circuit  100 , enhanced pseudo-Nmos circuit  380  is included in intermediate logic block (ILB)  105 A. Circuit  380  differs from circuit  280  (FIG. 1) by the addition of a Delay element  302 , CMOS NOR gate  304  and p-channel transistor P 1 . The additional circuit elements  302 ,  304  and P 1  reduce power consumption of the  380  circuit by shortening the evaluation period of N-Block  202  and therefore reducing the time for D.C. current to flow through the N-Block  202  transistors, as will be explained. 
     In operation, during the pre-charge phase, CLK  106  is ‘0’, inverter  204  outputs a ‘1’ to P 0 , turning P 0  off. P 0  outputs  308  the ‘1’ to Delay element  302 , after time Td, the ‘1’ is input  310  to NOR gate  304 , which outputs  306  a ‘0’ to P 1 , turning on P 1 . CLK  106  at ‘0’ also turns on PUA, PUA pulls-up output  120 A to ‘1’, which is input to N-Block  202 , turning on N 1  and N 2 , which pulls down output  130 B to ‘0’. Therefore, at the end of the pre-charge phase the inputs to NOR gate  304  are ‘1’ ( 310 ) and ‘0’ ( 130 B), and the NOR gate  304  output  306  is ‘0’, keeping P 1  on. During the evaluation phase, CLK  106  goes to ‘1’, turning on P 0 , and inputting  308  a ‘0’ to Delay element  302 . Now P 0  and P 1  are both on, and ready to pull-up output  130 B of N-Block  202 . N-Block  202  transistors can now evaluate input  120 A from the previous dynamic block  104 A. If N 1  and N 2  stay on, output  130 B stays at ‘0’, and after time Td, the ‘0’ from  308  is input  310  to NOR gate  304 , producing a ‘1’ at  306 , turning off P 1 , and substantially cutting off D.C. power dissipation in N-Block  202 . In the opposite case, input  120 A goes to ‘0’, turning off N 1  and N 2 , output  130 B is pulled up to ‘1’ by P 0  and P 1 , the ‘1’ at  130 B is input to NOR gate  304  causing NOR gate output  306  to stay at ‘0’, keeping P 1  on, which together with P 0 , continue to pull-up output  130 B to ‘1’. 
     The delay element  302  may be configured in any manner which provides a delay time, Td, which is at least as long as the worst-case evaluation time of N-Block  104 A plus the worst-case evaluation time of N-Block  202 . 
     The D.C. power consumption of circuit  280  and  380  could be further reduced by providing a pulsed CLK  106  signal, where the duration of CLK  106  signal for the evaluation phase (CLK  106  at ‘1’) is shorter than the duration of the CLK  106  signal for the pre-charge phase (CLK  106  at ‘0’). 
     Embodiments of the circuit may have one or more of the following advantages. Faster transition times and reduced power consumption by the dynamic gates of a pseudo-Nmos circuit. 
     A number of embodiments of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other embodiments are within the scope of the following claims.