Abstract:
A MOSFET can operate as a resistor by operating in the linear or ohmic region of the drain V-I characteristics. This region can be obtained by floating the gate of the MOSFET, when the dc current and the voltage drop are given. Multiple resistors can be duplicated (or mirrored) by sharing the same source and floating gate. The floating gate voltage can be simulated using a closed loop equivalent circuit. Alternatively, the gate voltage can also be derived from the given drain-to-source voltage and the given current in a feedback loop. With this adaptive MOSFET resistor, the minimum supply voltage can be as low as the sum of the BJT threshold and the complementary BJT saturation voltage, e.g. V CC ≧V BE +Vsat (e.g. 0.8+0.15&lt;1.0V). The threshold voltage Vt should be less than V BE .

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   This invention relates bipolar-junction transistor (BJT)/MOSFET integrated circuit, particularly to resistive means to bias a BJT with a MOSFET. 
   2. Brief Description of Related Art 
   In integrated circuits, a polycrystalline film or diffusion is often used to fabricate resistors. Such resistors are limited in range of resistance values and may occupy substantial areas. Although it is well-known that a MOSFET can operate as a resistor in its ohmic or “triode” region of its drain V-I characteristics, it is seldom used in practice, because the resistance value varies with the gate voltage. 
   In circuit applications, a resistor is used to determine the current flow across a voltage differential, for instance between the supply voltage and an electrode of a transistor. For a BJT common emitter amplifier as shown in  FIG. 1   a , once the dc collector current I C1  is chosen, the dc base current I B  must be 1/β times less. Normally, the value of beta varies over a wide range in any production line, and if I B  is fed from a positive power supply through a resistor R B  to the base of an NPN transistor, the resistance value must vary accordingly. Besides, the base resistance value may be too low to shunt the input signal Vin coupled to the base. If the collector is fed through an inductive load, there is no dc voltage drop the load and the minimum required V CC  is the sum of dc base-to-emitter voltage V BE  and the drop across the R B . 
   If the dc base current is supply from a current mirror as shown in  FIG. 1   b , the effective beta is reduced, and the input resistance is further reduced to shunt the input signal Vin. 
   In another instance as shown in  FIG. 1   c , it is desired to operate Q 1  at a specified collector current I C1 . Then the base current I B  should be equal I C1 /β. This base current can be derived from the reference base current of Q 3  through current mirrors Q 2 ,Q 2 ′, where Q 3  is fed from a current source with current mirror Q 4 , Q 4 ′. A current mirror usually has a master section e.g. Q 2 ′ and Q 4 ′ and a slave section e.g. Q 2  and Q 4 . The dc collector-to-emitter voltage of the master section with the base shorted to the collector must be equal to the turn-on voltage of the BJT, typically in the 0.7V-0.8 V range. The dc collector-to-emitter voltage of the slave section need not be as large, so long as the BJT operates in the active region typically &gt;0.1-0.2V. The dc supply voltage must at least allow enough headroom V CE4  (&lt;0.2V) for the current source Q 4 , the base-to-emitter voltage V BE3  (&gt;0.7V) of the reference BJT Q 3  and the base-to-emitter voltage V CE2′  (&gt;0.7) of the current mirror Q 2 ′ for a total of more than 1.5 V. For a standard battery, the rated voltage is 1.5 V new, and for a mercury cell, the voltage is only 1.3V new. For low voltage application, it is desirable to operate the circuit below 1.3V. Thus the circuit shown in  FIG. 1   c  needs at least a supply voltage V CC  higher than V CE4 (&gt;0.2V)+V BE3 (&gt;0.7V)+V CE2′ (&gt;0.7V)&gt;1.6V, which is not suitable for single battery low voltage operation. 
   SUMMARY OF THE INVENTION 
   It is proposed here to use an adaptive gate MOSFET to serve as an ohmic resistor by operating the MOSFET is the linear region of the drain characteristics. The proposed adaptive gate MOSFET is to achieve the following objects:
         to adapt to a wide range of resistance value for any specified current and voltage drop;   to require lower voltage drop than a current mirror, hence low supply voltage;   to mirror the resistance to more than one resistance values;   to float the gate of the MOSFET to adapt to the voltage across the resistor and the current through the resistor;   to reduce the area occupied by the resistors in an IC.       

   These objects are achieved by using a MOSFET operating in the ohmic region of the drain V-I characteristic to bias the base of a BJT. The gate voltage of the MOSFET is adaptable, so the MOSFET resistor feeds the correct amount of dc base current to yield a desired dc collector current over a wide range of current amplification factor β. The adaptive gate voltage can be obtained by deriving the gate voltage from a current regulator or simply floating the gate. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIGS. 1   a,b,c  show prior art means for biasing a BJT common-emitter amplifier. 
       FIG. 2   a  shows a MOSFET serving as a base biasing resistor for a pnp transistor;  FIG. 2   b  shows the operating point of the MOSFET resistor;  FIG. 2   c  shows a MOSFET resistor biasing a pnp current mirror for feeding a base current to an npn common emitter amplifier. 
       FIG. 3  shows a base current regulating circuit for deriving an adaptable gate voltage to the MOSFET resistor to bias the base of a BJT. 
       FIG. 4   a  shows a MOSFET resistor for biasing the base of a BJT differential pair;  FIG. 4   b  shows two MOSFET resistor for biasing two bases of a BJT differential pair. 
       FIG. 5   a  shows common source and common gate MOSFET resistor mirrors;  FIG. 5   b  shows channel stops for the structure of  FIG. 5   a.    
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Operation of the MOSFET Resistor: 
     FIG. 2   a  shows the use of a n-channel MOSFET Mn as a base resistor for biasing a pnp BJT Qp of a common emitter amplifier. The dc drain characteristic is shown in  FIG. 2   b . The current I D  of a MOSFET is given as:
 I D =kp(W/L)[(V GS −Vt) V DS −V DS   2 /2]  (1)  
where kp is a transconductance parameter, W/L is the width-to-length ratio of the gate, V GS  is the gate to source voltage, Vt is the threshold voltage and V DS  is drain-to-source voltage. When V DS  is less than (V GS −Vt), the MOSFET is operating in the ohmic region, and
 I C ≈kp(W/L)(V GS −Vt) V DS   (2)  
The ohmic resistance is:
 R DS =V DS /I C =1/[kp(V GS −Vt)]  (3)  
By adjusting V GS , a wide range of resistance values can be obtained, so long as V DS  is less than (V GS −Vt).
 
     FIG. 2   c  shows the use of Qp′ similar to the pnp amplifier shown in  FIG. 2   a  as the master section of a current mirror fed from the MOSFET resistor Mn. The slave section Qp mirrors the current through Mn to the master section Qp′. The gate voltage V G  is adjusted to flow in Mn a current equal to 1/β that of the desired I C  for Q 1 . As compared to  FIG. 1   c ,  FIG. 2   c  has one less V BE3 ˜0.7V headroom in Q 3  and the supply voltage can be as low as the sum of V BE1 +V CE2knee &lt;1V, where the voltage drop across Mn can be as low as the knee voltage of Q 2 . 
   Design of the Adaptive MOSFET Resistor: 
   Consider the pnp common emitter circuit  FIG. 2   a  with the base of Qp′ fed from a nMOS resistor Mn with a gate voltage V G . The operating point of Mn is shown in  FIG. 2   b . The supply voltage V CC   32  V BE +V B ). For common emitter npn amplifier Q 1  as shown in  FIG. 2   c , the base is preferably fed from a current source Qp operating in the active region (i.e. above the knee V knee  of the collector characteristic ˜0.15V). Thus the minimum supply voltage V CC =(V BE +V knee )=0.8+0.15=0.95V. When the current source Qp is mirrored from a master pnp Qp′, the operation of Qp′ is similar to that in  FIG. 2   a  with V B =0.15V. For the ohmic operation of the MOSFET resistor shown in  FIG. 2   a , the dc voltage across of the MOSFET should operate at a V DS  less than the knee voltage, i.e.
 
V B =(V CC −V BE .)&lt;(V G −Vt)  (4) 
 
or (V CC −V BE +Vt)&lt;V G   (5) 
 
 Since V CC &gt;V G   (6)
 
Combining (5) and (6) yields:
 
V BE &gt;Vt  (7) 
 
   For I B &gt;0, V B &gt;0, as shown in FIG.  2 . For The minimum V B  can be obtained from the following consideration: Since the base of the BJT is the signal input terminal of a common emitter amplifier, the base should preferably be fed from a high impedance current source as shown in  FIG. 2   c , instead of the low ohmic resistance of MOSFET to avoid shunting the signal. The minimum voltage across a current source Qp should be higher that the saturation voltage Vsat, typically ˜0.15V. Thus, the minimum supply voltage is:
 
V CC &gt;(V BE +Vsat)=0.8+0.15=0.95V 
 
The current source Qp is mirrored from the master BJT Qp′, which is fed from an adaptable MOSFET resistor Mn described above.
 
   The size of the MOSFET resistance can be calculated as follows:
 
I B =I C /β=I D =kp(W/L)(V CC −V G −Vt)(V CC −V B )  (8) 
 
W/L=(I C /β)/[kp(V CC −V G −V)(V CC −V B )]  (9) 
 
A medium value of gate voltage can be derived from Eq. (5),
 
V G =(V CC −V B )/2  (10) 
 
This medium V G  can allow a I C /β variation twice that of the medium value.
 
Derivation of the Gate Voltage:
 
   The gate voltage for the MOSFET resistor can be obtained as follows: The gate voltage can be derived with a regulator circuit as shown in FIG.  3 . Consider a complementary circuit of  FIG. 2   a , where a pMOS Mp′ is used to drive the base of an npn BJT Q 1 ′, which is identical to Q 1  in  FIGS. 1   a -c. The MOSFET Mp′ corresponding R B  in  FIG. 1   a  is connected between supply V CC  and the base of BJT Q 1 ′ corresponding to Q 1 . The collector of Q 1 ′ is connected to a current mirror Q 5 , Q 5 ′, which mirrors the collector current of Q 1 ′. The mirror current out of Q 5  is compared with the desired collector current for Q 1  as a reference current Iref from a current mirror Q 6 ,Q 6 ′. An error voltage V G  is developed and applied to the gate of Mp′. The feedback loop regulates the base current Q 1 ′ to yield the desired reference emitter current Iref. Then V G  is the adaptive gate voltage. 
   Floating Gate Operation: 
   When the voltage across the MOSFET resistor and the current are known, there is only one gate voltage for the MOSFET resistor to satisfy this condition. Thus, if the voltage across the MOSFET is given and the current is given, the gate automatically adjusts itself, even if it is floating. This feature can sometimes be utilized as illustrated in  FIGS. 4   a , 4   b . When the gate of the MOSFET is floating, and V DS  and I C  are given, then V GS  must assume a value to satisfy Eq. (3). Therefore, the resistance value is adaptive. 
   A circuit to demonstrate this floating gate resistor is shown in  FIG. 4   a . An npn differential pair Q 7 , Q 8  is fed from a current source Io. The base of Q 8  is fixed at dc voltage V Ref . For balanced operation, the dc base voltage of Q 7  must be equal to that of Q 8 , i.e. V Ref , and the dc base currents I B7  and I B8  must be equal to Io/2(1+β). Since the dc base current I B7  and the dc base voltage are known, the base of Q 6  can be fed from a floating gate MOSFET M 7  as a resistor. The floating gate of M 7  automatically assumes a resistance value for the appropriate base current for Q 7 . 
   This resistance can be duplicated (mirrored) in other resistors on the same chip. For instance in  FIG. 4   b , there is another differential pair Q 7 ′, Q 8 ′ similar to Q 7 , Q 8  in  FIG. 4   a , fed from a similar current source Io. The base biasing resistors can be duplicated by two MOSFET resistors M 7 ′, M 8 ′ identical to M 7 . If the current source is different from Io, say 2Io, In such a case, the resistance M 8 ′ feeding the base should be doubled. This can be done by doubling the W/L ratio of M 8 ′ as compared the W/L ratio of M 8 . For the differential pairs in  FIGS. 4   a ,  4   b , one more headroom for Q 9  than that in  FIG. 2   c  is required, i.e. V CE9 +1.0V&lt;1.2V. 
   If the values of the MOSFET resistors shown in  FIGS. 4   a , 4   c  are too low to shunt the input signals, the techniques shown in  FIG. 2   c  can be used. 
   To simulate the floating MOSFET, a dc gate voltage must be assigned to the floating gate. In a typical simulation program such as SPICE, the program does not run with the gate floating. The floating gate voltage can be derived from the regulated gate voltage derived from FIG.  3 . 
   Layout of the Floating Gate Resistor: 
   The floating gate MOSFETs such as M 7 , M 8 ′ can share a common source and a common floating gate, but different drains D 7 , D 7 ′, D 8 ′. A layout is shown in  FIG. 5   a . Such a layout can save area. To prevent cross-talks among the different floating gate MOSFETs, the different MOSFETs can be separated to each other by channel stops shown in dotted lines in  FIG. 5   b  as is well known in the IC art. The floating gate should be sealed in oxide and not connected to any parts of the circuit to prevent leakage. 
   In the foregoing descriptions of the current mirrors in  FIGS. 1   c ,  2   c ,  3 ,  4   a  and  4   b , it is implied that the currents in the master sections are the same as that in the slave sections. However, the currents in the master sections can be reduced by reducing the emitter sizes of the master sections as is well known in the current mirror art. Also, the BJT current mirrors in these circuits can be replaced with corresponding MOSFETs, i.e. pMOS for pnp BJTs and nMOS for npn BJTs. 
   While the preferred embodiments of the invention have been described, it will be apparent to those skilled in the art that various modifications can be made without departing the spirit of the present invention. Such modifications are all within the scope of the present invention.