Abstract:
Provided is a transmitter in a communications system including a plurality of digital to analog converters. Also included is a plurality of clocks, each being communicably coupled to a corresponding one of the digital to analog converters.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention generally relates to digital to analog conversion in a communications system transmitter.  
         [0003]     2. Background Art  
         [0004]     An increasingly popular standard in conventional communication systems is the Data Over Cable Service Interface Specification (DOCSIS). Communications systems that comply with these standards, particularly DOCSIS upstream standards, typically include transmitters that have a single digital to analog converter (DAC). Each of these transmitters, mainly used in upstream communication channels, typically includes a low-pass filter coupled to an output of its DAC and a power amplifier connected to an output of the anti-aliasing filter.  
         [0005]     The anti-aliasing filter is provided to minimize aliasing components in the output signals. The power amplifier is provided to achieve the DOCSIS recommended output power level of about 58 dBmV (decibel millivolts).  
         [0006]     An additional (Euro) DOCSIS requirement is the ability to achieve a DAC output signal frequency of roughly 65 megahertz (MHz). That is, in conventional upstream (Euro) DOCSIS based transmitters, a single DAC must be able to run at a sampling rate of at least 130 MHz according to general sampling theory (Nyquist Theorem).  
         [0007]     Significant challenges exist in using anti-aliasing filters and power amplifiers in the manner noted above. The greatest of these challenges is that the power amplifiers typically used are relatively large in size. At low DAC sampling rates, e.g. 130 MHz, an expensive anti-aliasing filter is required and this filter may also attenuate the desired output signal, therefore requiring even higher output power from the power amplifier to compensate for these losses. The large size power amplifier is responsible for the consumption of significant amounts of integrated circuit (IC) real estate, or one may need to use an external power amplifier to generate the required high output power.  
         [0008]     What is needed therefore is a method and system of converting digital signals to analog domain in a manner that minimizes aliasing components in the output signal. What is also needed is a method and system that can also achieve or exceed the output power requirements of standards, such as DOCSIS.  
       BRIEF SUMMARY OF THE INVENTION  
       [0009]     Consistent with the principles of the present invention as embodied and broadly described herein, the present invention includes a transmitter in a communications system, including a plurality of DACs. Also included is a plurality of clocks each being communicably coupled to a corresponding one of the DACs.  
         [0010]     The present invention provides a unique technique for running multiple time-interleaved DACs in a communications system transmitter to achieve  4 ×over-sampling. This over-sampling translates into enhanced DAC resolution and performance.  
         [0011]     An exemplary embodiment of the present invention, described below, facilitates the use of multiple 10-bit time-interleaved DACs. The time-interleaved aspect occurs in the sense that multiple DACs operate off separately and independently phased clocked signals.  
         [0012]     In the present invention, multiple 10-bit DACs can achieve the same resolution as the single 11-bit DAC. Thus, the approach of the present invention enables four time-interleaved 10-bit DACs to gain an additional 1-bit improvement in resolution over the individual DACs running separately and provide a savings in IC real estate.  
         [0013]     An important benefit of the present invention is virtual elimination of the need of anti-aliasing filters. That is, the present invention minimizes the production of aliasing components output from the DAC that fall within DOCSIS frequency bands of interest.  
         [0014]     For example, it is well understood by those of skill in the art that conventional DACs produce undesirable spurious tones close to the DAC&#39;s sampling frequency. In the exemplary case of a DAC running at 400 MHz and producing a signal having an output frequency of 50 MHz, spurious tones will be produced at 400 MHz (which is the clock frequency) minus 50 MHz (i.e., at 350 MHz) and at 400 MHz plus 50 MHz (i.e., at 450 MHz). There will also be tones at 750 MHz (800 MHz−50 MHz) and 850 MHz (800 MHz+50 MHz), and so on. In essence, undesirable spurious tones are produced at multiples of the DAC&#39;s sampling rate.  
         [0015]     These spurious tones fall directly within the operational bands of traditional cable television (TV) channels and create interference. The DOCSIS specification requires suppression of this interference, hence the use of the anti-aliasing filters, noted above. In the conventional systems, substantial anti-aliasing filtering is required in the upstream channels to ensure that these images, as well as any related harmonics, are sufficiently suppressed.  
         [0016]     An embodiment of the present invention substitutes four DACs for the single DAC (used in conventional implementations) running at a sampling rate of 525 MHz. In the present invention, the four DACs produce a sampling rate of 2.1 gigahertz (GHz). In this case of an embodiment of the present invention and a 50 MHz output frequency, the first spurious (aliasing) tone is produced at 2.05 GHz (2.1 GHz−50 MHz) and 2.15 GHz (2.1 GHz+50 MHz) instead of 350 and 450 MHz. Since the operational upper bandwidth of cable television channels only reaches about 1 GHz, the spurious tones produced in exemplary embodiments of the present invention, do not interfere with cable TV since they fall outside of the operation bandwidth.  
         [0017]     Further embodiments, features, and advantages of the present invention, as well as the structure and operation of the various embodiments of the present invention, are described in detail below with reference to the accompanying drawings.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]     The accompanying drawings, which are incorporated in and constitute part of the specification, illustrate embodiments of the invention and, together with the general description given above and the detailed description of the embodiment given below, serve to explain the principles of the present invention. In the drawings:  
         [0019]      FIG. 1  is a high level block diagram illustration of a digital to analog converter (DAC) system constructed in accordance with an embodiment of the present invention;  
         [0020]      FIG. 2  is a graphical illustration of exemplary timing signals used in the illustration of  FIG. 1 ; and  
         [0021]      FIG. 3  is an exemplary flowchart of a method of practicing an embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0022]     The following detailed description of the present invention refers to the accompanying drawings that illustrate exemplary embodiments consistent with this invention. Other embodiments are possible, and modifications may be made to the embodiments within the spirit and scope of the invention. Therefore, the detailed description is not meant to limit the invention. Rather, the scope of the invention is defined by the appended claims.  
         [0023]     It would be apparent to one of skill in the art that the present invention, as described below, may be implemented in many different embodiments of software, hardware, firmware, and/or the entities illustrated in the figures. Any actual software code with the specialized control of hardware to implement the present invention is not limiting of the present invention. Thus, the operational behavior of the present invention will be described with the understanding that modifications and variations of the embodiments are possible, given the level of detail presented herein.  
         [0024]      FIG. 1  is an illustration of an exemplary PowerDAC  100  constructed in accordance with an embodiment of the present invention. The PowerDAC  100  includes a quad time-interleaved DAC architecture for use in a modem, such as a cable modem, used in a transmitter. This transmitter can in turn be used in an upstream channel of a DOCSIS based communications system.  
         [0025]     In the exemplary embodiment of  FIG. 1 , four 10-bit DACS  102 ,  104 ,  106 , and  108  are used. The clock frequency of each of the DACs  102 - 108  is skewed by 90°, effectively providing a four-fold over-sampling data conversion system. Input data words data 0 -data 3  are provided as respective inputs to the four DACs  102 - 108 . The input data words data 0 -data 3  are generated by a digital interpolation filter (not shown).  
         [0026]     Although the DACs  102 - 108  are implemented as 10-bit DACs, the present invention is not limited to such an implementation. In the present invention, the combination of the four exemplary 10-bit DACs  102 - 108  provides an output resolution equivalent to the output of a single 11-bit DAC. That is, the effective sampling rate of four time-interleaved DACs, such as the DACs  102 - 108 , is four times higher than the sampling frequency of any one of the individual DACs.  
         [0027]     As an example, one conventional transmitter DAC implementation might require a single 11-bit DAC to run at 500 MHz. The cycle time for this conventional implementation would be two nano-seconds ( 1/500 MHz). In the PowerDAC system  100  of  FIG. 1 , the 10-bit DACs  102 - 108 , are 4×time-interleaved (i.e., having an update rate of 500 pico-seconds) to behave as the single 11-bit DAC in the exemplary conventional implementation. Running at 500 MHz, four time-interleaved DACs results in the single PowerDAC  100  having a 2 GHz sampling rate. Due to the higher sampling rate of the present quad interleaved configuration, DAC aliasing images no longer fall within the cable bands of interest (e.g., a &gt;860 MHz), as explained above.  
         [0028]     In  FIG. 1 , the DACs  102 - 108  are connected to a timing generation unit  109 . The timing generation unit  109  controls phasing of the input data words data 0 -data 3 , respectively input to each of the DACs  102 - 108 . The timing generation system  109  includes individual clock generators  110 ,  112 ,  114 ,  116  and  118 .  
         [0029]     The exemplary clock generating unit  110  provides clock phasing for an upstream clocking signal (usclk) provided as an output signal to control digital logic (not shown) external to the PowerDAC system  100 . Each of the remaining clock generators  112 - 118  is coupled to a respective one of the DACs  102 - 108 . The upstream clocking signal (usclk) provides a time-base for the DACs  102 - 108 .  
         [0030]     Each of the clock generators  110 - 118  includes a phase interpolator and a corresponding fixed divider circuit. The clock generator  110 , for example, includes a phase interpolator  120  coupled to a divider circuit  122 . The clock generators  112 - 118  shifts a phase of a respective one of input data words by a multiple of 90°.  
         [0031]     Each of the phase interpolators, such as the phase interpolator  120 , provides an individual phase offset for its corresponding divider circuit, such as the circuit  122 .  
         [0032]     In more specific terms, the exemplary phase interpolators, such as the phase interpolator  120  in the PowerDAC  100 , allow independent clock timing adjustments for each of the four DACs  102 - 108 . They also allow independent adjustments for the output clock signal (usclk). Each of the phase interpolators has a 6-bit control word, and hence allows a timing grid of 1/(64×F vco )) where F vco  is the output frequency of a variable controlled oscillator (not shown) within the PLL  124 .  
         [0033]     The exemplary divider  122  is implemented as a divide-by-2 DAC, although the present invention is not limited to this implementation. A divide-by-2 implementation was chosen because it makes it easier to generate four equally spaced clock phases for the DACS  102 - 108 . Timing and phasing of the clock generators are provided by a phase locked loop (PLL) device  124 .  
         [0034]     In particular, the PLL device  124  provides synchronization, multiplication and phasing stability between an input reference clock signal (refclk) and the signals input to the clock generators  110 - 118 . The PLL  124  receives inputs from an M-divider control word (mdiv_ctrl) and an N-divider control word (ndiv_ctrl). The control words provide programmability for certain timing components within the PLL  124 . A multiplexer  126 , in conjunction with a bank of multiplexers  128 , enables a user to selectively bypass operation of the PLL  124  if conditions so dictate.  
         [0035]     The control words (mdiv_ctrl and ndiv_ctrl) in conjunction with the input clock signal refclk, are used in accordance with known techniques, to control a frequency of a frequency word output from the PLL  124 . The clocking mechanism  109  shifts a phase of the input data words data 0 -data 3  respectively input to the DACs  102 - 108 .  
         [0036]     The conversion unit  100  also includes flip-flops  130 - 133 , which receive the data words data 0 -data 3 , respectively coupled across data paths to the DACs  102 - 108 . The flip-flops  130 - 133  provide a mechanism to interface and synchronize data being received from external circuit components, with operation of the PowerDAC  100 . Although the flip-flops shown in  FIG. 1  are implemented as D-flip-flops, the present invention is not limited to such an implementation.  
         [0037]     During operation, the exemplary PowerDAC unit  100  receives the data signals data 0 -data 3  as inputs. The data0 signal, for example, is clocked by a signal received from the clock generator  112 . The signal output from the clock generator  112  has a “0” degree phase shift, and is provided as an input clock to the DAC  102 . Similarly, the data1 input signal is clocked by a clocking signal output from the clock generator  114  to produce a 90° phase shifted signal. The 90° signal is provided as an input clock to the DAC  104 . The data2 and data3 input signals are clocked in a similar manner to respectively provide input signals having phases of 180° and 270° respectively. These phase shifted signal are then as inputs to the DAC  106  and DAC  108 , respectively.  
         [0038]     In this manner, the DACs  102 - 108  operate in a quad time-interleaved manner to convert the input data signals data 0 -data 3  from digital domain to analog domain. Outputs of the DACs  102 - 108  are then combined, forming a single analog differential analog output signal (output P and output N).  
         [0039]     The present invention is not limited to the use of multiple clock generators. That is in another embodiment, all of the DACs  102 - 108  can be run off of a single clock. Running multiple DACs off of a single clock generator would still provide the benefits of higher output power compared to a single DAC, as discussed above.  
         [0040]     Similarly, many other combinations of clock generators and DACs can be used. For example, to further optimize power and timing benefits, eight DACs could be run in groups of two off of four clock generators. Alternatively, the eight DACs could be run off of a single clock generator. The present invention is not limited to any particular number of DACs or any particular number of clock generators.  
         [0041]      FIG. 2  is a graphical illustration of an exemplary timing diagram  200  of timing associated with the data signals data 0 -data 3 . In  FIG. 2 , each of the input data signals data 0 -data 3  is captured in a manner equally spaced in time. For example, each of the input data signals data 0 -data 3  is captured on a falling edge of the input clock signal usclk, as shown.  
         [0042]     In  FIG. 2 , the DAC  102  captures data0 on a rising edge of the clock  110 , and the DAC  104  captures data1 on a rising edge of the clock  112 . The DACs  106  and  108  similarly correspondingly capture data2 and data3 on respective rising edges of the clocks  114  and  116 .  
         [0043]     In an exemplary scenario the DACs  102 - 108  can each be run for example, at 500 MHz. Although four DACs are used, the present invention is not limited to four DACs. However, in the exemplary embodiment of the PowerDAC unit  100  of  FIG. 1 , a full clock cycle is 2 nanoseconds, and thus adjacent DACs have a clock timing delay of 500 picoseconds.  
         [0044]     The outputs of the DACs  102 - 108  are summed together. Because the effective update rate is now 500 picoseconds and not 2 nanoseconds, as noted above, the first spurious tone will show up at about 2 GHz, rather than 500 MHz. In case of a clock signal delay mismatch (e.g., 600 picoseconds delay for one DAC) there will images showing up at 500 MHz, although initial simulations show that a result is still significantly better than having a single DAC operating at 500 MHz. This is apparent since individual DAC errors are averaged across the power of four DACs.  
         [0045]     Another advantage of the present invention is the overall upstream signal- to-noise ratio (SNR). At full power, the 10-bit DACs  102 - 108 , of the exemplary embodiment of  FIG. 1 , together will effectively provide the dynamic range and resolution of an 11-bit DAC (4×over-sampling).  
         [0046]      FIG. 3  is an exemplary flowchart of a method  300  of practicing an embodiment of the present invention. In  FIG. 3 , a plurality of phase shifted clock signals is produced in step  302 . In step  304 , each of a plurality of received digital signals is clocked with a corresponding one of the phase shifted clock signals. The clocked digital signals are then converted to analog domain in accordance with the respective phase shifts, as indicated in step  306 .  
       CONCLUSION  
       [0047]     The present invention provides a method and system for a quad time interleaved DAC architecture for use in a cable modem transmitter. By skewing the clock frequency of each of the DACs  102 - 108  by 90°, the four exemplary 10 bits DACs  102 - 108  effectively provide the processing resolution of a single 11 bit DAC. That is, the improved SNR, due to four fold over-sampling, enhances the DAC resolution by 1 bit.  
         [0048]     In the present invention, the total amount of output power is the result of a summation of power from the individual DACs in the DAC array. This is advantageous for the system performance and required real estate (chip area) compared to a single DAC system.  
         [0049]     Also, in the exemplary embodiment of  FIG. 1 , each of the four DACs is operating at a sampling frequency at 500 MHz, ultimately resulting in a 2 GHz powerDAC. Due to the higher sampling rate, DAC aliasing images no longer fall within operational cable bands, such as above 860 MHz.  
         [0050]     The open loop style implementation of the DACs  102 - 108  and other circuitry provides adequate system stability, easing board and package design. Higher output power is possible, as long as the DACs can support the higher current levels. Fully digital control of power on and power off ramp time constants help to reduce electromagnetic interference and increase power integrity.  
         [0051]     The present invention has been described above with the aid of functional building blocks illustrating the performance of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.  
         [0052]     The foregoing description of the specific embodiments will so fully reveal the general nature of the invention that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present invention. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.  
         [0053]     The breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.