Abstract:
The present invention provides a circuit for use in an ADPCM synthesizer for generating a function of a quantization step without the use of a look-up table. Illustratively, the function is represented in a piecewise linear fashion. This permits an ADPCM synthesizer to be implemented without the use of a memory storing a look-up table for the function so the area of the synthesizer chip can be reduced.

Description:
FIELD OF THE INVENTION 
     The present invention relates to an Adaptive Differential Pulse Code Modulation (ADPCM) synthesizer which does not require the use of a look-up table. 
     BACKGROUND OF THE INVENTION 
     In signal processing applications such as speech, data is compressed before it is stored and decompressed when it is retrieved. Such compression/decompression reduces the amount of memory required to store the data. One of the most common compression/decompression techniques is ADPCM. 
     When ADPCM is used, the analysis (compression) process is as follows: 
     1. Consider the discrete data samples, X 0 , X 1 , X 2 , . . . X N-1 . It should be noted that this data has maximum points. 
     2. Select an initial estimated value X 0  and an initial quantization step q ini  ; 
     3. From the original data value X 0  and the initial estimated data value X 0 , a quantization step size q 0  and compressed data value D 0  can be obtained as follows: 
     
         q.sub.0 =f.sub.1 (X.sub.0, X.sub.0, q.sub.ini) 
    
     
         D.sub.0 =f.sub.2 (X.sub.0, X.sub.0, q.sub.ini) 
    
     4. From the obtained values q 0 , D 0 , the next estimated value, 
     
         X.sub.1 =X.sub.0 +T(q.sub.0)+D.sub.0 
    
     is obtained, where T is a function of q (quantization step). The function T is usually an exponential function and, conventionally, a look-up table stored in a memory is used to implement this function. The function T(q) is illustrated in FIG. 1. 
     5. The values q n , D n , X n  can be calculated as follows: 
     
         q.sub.n =f.sub.1 (X.sub.n-1, X.sub.n-1, q.sub.n-1) 
    
     
         D.sub.n =f.sub.2 (X.sub.n-1, X.sub.n-1, q.sub.n-1) 
    
     
         X.sub.n =X.sub.n-1 +T(q.sub.n-1)*D.sub.n-1 
    
     6. In this way, the original data X 0 , X 1 , X 2 , . . . , X N-1  are transformed into estimated data X 0 , X 1 , X 2 , . . . , X N-1  and the encoded (compressed) data D 0 , D 1 , D 2 , . . . , D N-1  are also obtained. 
     Generally, when ADPCM is used, the above-described analysis process is carried out in software using a computer to generate the compressed data D 0 , D 1 , D 2 , . . . , D N-1 . 
     When ADPCM is used, the synthesis (decompression) process is as follows: 
     1. Select the same initial quantization step size value q ini  and estimated value X 0 . 
     2. From the compressed data D 0 , D 1 , . . . , D N , the next estimated value X 1 , X 2 , . . . and quantization step q 0 , q 1 , . . . can be calculated as follows: 
     
         X.sub.n+1 =X.sub.n +T(q.sub.n)*D.sub.n 
    
     
         q.sub.n+1 =f.sub.3 (q.sub.n, D.sub.n) 
    
     Using this formulation, the sequence of estimated values X 0 , X 1 , X 2 , . . . , X N  is regenerated from the compressed data. 
     FIG. 2 schematically illustrates a circuit 10 for performing the ADPCM synthesis process described above. In the circuit 10 of FIG. 2, the input is the compressed data D n . The compressed data D n  is received at the input 11. The circuit 12 receives the inputs D n , q n  at the inputs 13, 14 respectively. The output of the circuit 12 is q n+1  =f 3  (q n , D n ) which appears at the output 15. The output q n+1  is then processed by the unit delay 16 so that q n  is present at the input 13. The unit delay 16 also transmits the value q n  to a memory circuit 20 which stores a look-up table for the function T(q n ). FIG. 3 is an exemplary look-up table for the function T(q n ) and thus illustrates the values stored in the memory 20. The circuit 22 multiplies T(q n ) and D n  and outputs the product T(q n )*D n . The product T(q n )*D n  is one input to the summer 24. The other input is X n . The value X n  is generated by the unit delay 26. The output of the summer 24 is X n+1  which is equal to X n  +T(q n )*D n . The value X n+1  is fed back to the unit delay 26 whose output is X n . 
     The values contained in the look-up table stored in the memory 20 of FIG. 2 and explicitly set forth in FIG. 3 are illustrative only and are obtained according to the formula: 
     
         q.sub.n =integer part of q.sub.n-1 *1.1 
    
     where 
     q n  =16. 
     The memory 20 of FIG. 2 is shown in greater detail in FIG. 4. As shown in FIG. 4, the memory 20 has six input pins for the 63 steps q n  =0 to q n  =62 and twelve output pins for the output values T(q n ). Thus, the memory 20 requires 63×12=756 bits. This memory cannot be easily divided into smaller blocks and, thus, results in a significant increase in the chip size for the ADPCM synthesizer. 
     Accordingly, it is an object of the present invention to provide an ADPCM synthesizer which does not utilize a memory storing a look-up table to implement the function T(q n ). 
     SUMMARY OF THE INVENTION 
     To carry out this objective, the present invention provides a circuit which implements the function T(q n ) without use of a look-up table stored in a memory. 
     In accordance with the present invention, the function T(q n ) is represented in a circuit in a piecewise linear fashion. Illustratively, the input q n  has six bits q 5  q 4  q 3  q 2  q 1  q 0 . The basic output value is 1q 2  q 1  q 0  0. This basic output value is shifted a number of bits to the left to generate the final output T(q n ) depending on the value q 5  q 4  q 3 . For example, if q n  =8=001000, then the basic value=1q 2  q 1  q 0  0=10000=16. The number of shifts to the left is given by q 5  q 4  q 3  =001. Thus, the output value T(q n )=100000 =32 is obtained by shifting the basic value one place to the left. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 schematically illustrates the function T(q n ). 
     FIG. 2 schematically illustrates a prior art ADPCM synthesizer. 
     FIG. 3 illustrates values comprising a look-up table for the function T(q n ) stored in a memory in the synthesizer circuit of FIG. 2. 
     FIG. 4 illustrates a memory which stores the look-up table of FIG. 3. 
     FIG. 5 is a piecewise linear representation of the function T(q n ). 
     FIG. 6 is a circuit which implements a piecewise linear representation of the function T(q n ) in accordance with the present invention. 
     FIG. 7 is a table which relates inputs and outputs for the circuit of FIG. 6. 
     FIG. 8 is an ADPCM synthesizer which utilizes the circuit of FIG. 6. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     In accordance with the present invention, the exponential function T(q n ) is represented in a piecewise linear manner. A piecewise linear representation T&#39;(q n ) of an exponential function T(q n ) is illustrated in FIG. 5. Thus, the function T(q n ) illustrated in the look-up table of FIG. 3 is approximated by 
     
         T&#39;(0)=16 
    
     
         T&#39;(q.sub.n)=(16+(q.sub.n -8*(q.sub.n /8))*2)*2.sup.(q.sbsp.n.sup./8) 
    
     where 
     (q n  /8) is the integer part of q n  divided by eight. 
     For example, if 
     
         for q.sub.n =1, T&#39;(1)=(16+(1-8*0)*2)*2.sup.0 =18 
    
     
         for q.sub.n =8, T&#39;(8)=(16+(8-8*1)*2)*2.sup.1 =32 
    
     FIG. 6 is a circuit 50 for implementing the piecewise linear function T&#39;(q n ). The quantization step size q n  is illustratively represented by six bits, i.e., q n  =q 5  q 4  q 3  q 2  q 1  q 0 . The circuit 50 has two sets of inputs. The first set of inputs 52 receives the bits q 2  q 1  q 0 . The second set of inputs 54 receives the bits q 5  q 4  q 3 . The outputs 56 comprise twelve bit positions of the values T&#39;(q n ). To generate the outputs 56 from the inputs 52, 54, the circuit 50 comprises a plurality of processing elements in the form of MOS transistors 58. The input 52 above q 2  (i.e., the input 52&#39;) is set to logic &#34;1&#34; and the remainder of the inputs 52 (besides the inputs receiving q 2 , q 1 , q 0 ) are set to logic &#34;0&#34;. 
     In the circuit 50, the transistors 58 are arranged in three columns 62, 64, 66. The bit values q 3 , q 4 , q 5  are applied to the gates of the transistors in the columns 62, 64, 66, either directly or via corresponding inverters 63, 65, 67. The bit values q 0 , q 1 , q 2  are connected to the drain terminals of particular transistors in the column 66. The source terminals of the transistors in the column 66 are connected to the drain terminals of particular transistors in the column 64. The source terminals of the transistors in the column 64 are connected to the drain terminals of particular transistors in the column 62. The source terminals of the transistors in the column 62 are connected to corresponding outputs 56. 
     The circuit 50 operates as follows: 
     At the inputs 52, there are present the values 00000001q 2  q 1  q 0  0 which are obtained from the bits q 2  q 1  q 0  of the quantization step q n . The basic value 1q 2  q 1  q 0  0 is shifted to the left a particular number of places depending on the values q 5  q 4  q 3  as follows: 
     When q 5  =0, the output data is the same as the input data, i.e., 00000001q 2  q 1  q 0  0, when q 5  =1, the input data is shifted four places to the left so that the output data is 0001q 2  q 1  q 0  00000 
     When q 5  =0, and q 4  =0, the output data is unchanged from the input, i.e., 00000001 q   2  q 1  q 0  0 
     When q 5  =1, and q 4  =0, the input data is shifted four places to the left so the output data is 0001q 2  q 1  q 0  00000 
     When q 5  =0, and q 4  =1, the input data is shifted two places to the left so that the output data is 000001q 2  q 1  q 0  000 
     When q 5  =1, and q 4  =1, the input data is shifted six places to the left so that the output data is 01q 2  q 1  q 0  0000000 
     When q 3  is equal to 1, there is an additional shift of one place to the left. 
     FIG. 7 is a table which summarizes the relationship between q 5  q 4  q 3  and the output data. 
     FIG. 8 illustrates an ADPCM circuit 10&#39; in accordance with the present invention. In FIG. 7, the circuit 50 of FIG. 5 replaces the memory table 20 in the prior art ADPCM synthesizer of FIG. 2. This reduces the chip area in the ADPCM synthesizer. 
     Finally, the above described embodiments of the invention are intended to be illustrative only. Numerous alternative embodiments may be devised without departing from the spirit and scope of the following claims.