Abstract:
A semiconductor device cell is disclosed. The semiconductor device cell includes a transistor gate having a gating surface and a contacting surface and a source region contacted by a source contact. The semiconductor device cell further includes a drain region contacted by a drain contact, wherein the drain contact is not situated opposite the source contact with respect to the gating surface of the transistor gate. Additional semiconductor device cells in which the gate contact is closer to the source contact than to the drain contact are disclosed.

Description:
BACKGROUND 
     The semiconductor integrated circuit industry has experienced rapid growth in the past several decades. Technological advances in semiconductor materials and design have produced increasingly smaller and more complex circuits. These material and design advances have been made possible as the technologies related to processing and manufacturing have also undergone technical advances. In the course of semiconductor evolution, the number of interconnected devices per unit of area has increased as the size of the smallest component that can be reliably created has decreased. 
     However, as the size of the smallest component has decreased, numerous problems have increased. As features become closer, current leakage can become more noticeable, signals can crossover more easily, and power usage has become a significant concern. The semiconductor integrated circuit industry has produced numerous developments in effort to continue the process of scaling. One of these developments is the potential replacement or supplementation of the conventional MOS field effect transistor by the tunneling field effect transistor (TFET). 
     TFETs are promising devices that may enable further scaling of power supply voltage without substantially increasing off-state leakage currents due to its sub-60 mV/dec subthreshold swing. However, existing TFETs have not been satisfactory in every respect. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features of the figures are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIGS. 1A and 1B  present a top, schematic view and a cross-sectional diagram of a MOS transistor, respectively. 
         FIGS. 2A and 2B  present a top, schematic view of an N-type semiconductor device and a cross-sectional diagram of the N-type semiconductor device according to one embodiment. 
         FIGS. 3A and 3B  present a top, schematic view of a P-type semiconductor device and a cross-sectional diagram of the P-type semiconductor device according to another embodiment. 
         FIGS. 4A-C  depicts a number of basic configurations of the semiconductor device according to various embodiments. 
         FIGS. 5A-C  depicts top, schematic views of semiconductor device embodiments that include an inverter, a NAND gate, and a NOR gate. 
         FIG. 6  is a flowchart of a method for fabricating a tunneling field effect transistor according to an embodiment. 
     
    
    
     The various features disclosed in the drawings briefly described above will become more apparent to one of skill in the art upon reading the detailed description below. Where features depicted in the various figures are common between two or more figures, the same identifying numerals have been used for clarity of description. 
     DETAILED DESCRIPTION 
     It is to be understood that the following disclosure provides many different embodiments and examples for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact. Various features in the figures may be arbitrarily drawn in different scales for the sake of simplicity and clarity. 
       FIGS. 1A and 1B  depict a metal-oxide-semiconductor (MOS) field-effect transistor (FET)  100 . MOSFET  100  includes a substrate  102 , which in this example, is a silicon substrate. Oppositely charged dopants have been implanted to create a drain region  104  and a source region  106 . A transistor gate  108  is situated above a gate oxide  110 . MOSFET  100  further includes an insulating layer  112 , which in this example, is an inter-metal dielectric layer made of silicon oxide.  FIGS. 1A and 1B  both depict three contacts: source contact  120 , gate contact  122 , and drain contact  124 . Contacts  120 ,  122 , and  124  have been formed by etching holes through insulating layer  112 , and then filling the holes with a conductor, such as tungsten. Contacts  120 ,  122 , and  124  provide access by remote electrical signals and voltages to drain region  104 , source region  106 , and transistor gate  108 .  FIG. 1B  is a cross-sectional diagram largely along the reference line A in  FIG. 1A . However, as readily observed in  FIG. 1A , gate contact  122  is not positioned or arranged along reference line A. However, gate contact  122  is included in  FIG. 1B , for clarity and comparison purposes. 
       FIG. 2A  and  FIG. 2B  depict an exemplary embodiment that is an N-type tunneling FET (TFET).  FIG. 2A  shows a schematic, top view of a vertically arranged TFET  200 , while  FIG. 2B  is a cross-sectional diagram along  FIG. 2A &#39;s reference line B.  FIG. 2B  includes a substrate  202 . In this example, substrate  202  is a silicon substrate. However, in other embodiments, substrate  202  may be another suitable elementary semiconductor material, such as diamond or germanium; a suitable compound semiconductor, such as silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. TFET  200  further includes a drain region  204 , a source region  206 , and a transistor gate  208 . In the depicted embodiment, the source region  206  is formed at the top of a frustoconical protrusion, which protrudes out of the plane of substrate  202  and is made of the same material as substrate  202 . The frustoconical protrusion may be formed by subjecting substrate  202  to an etch process, with a hard masking layer on the surface of substrate  202 . By having a masking layer approximately the size of the top of the source region  206 , the frustoconical protrusion can be formed with sidewalls forming an angle with the planar surface of the substrate ranging from approximately 90 degrees to around 45 degrees. In such an embodiment, the masking layer that creates the protrusion is circular in shape. However, other masking layer shapes may be used in other embodiments. 
     N-type dopants such as phosphorous or arsenic may be implanted to create drain region  204 . In the depicted embodiment, a diffusion process has been applied to cause phosphorous dopants to rise up into the frustoconical protrusion. As depicted, the diffusion process is used to bring the dopants up above the lower edge of transistor gate  208 . P-type dopants may be implanted into the top of the frustoconical protrusion to create a frustoconical source region  206 . In this example, boron is implanted to form source region  206 , however other embodiments may use other P-type dopants as known to those of skill in the art. 
     Transistor gate  208  may be a conductive multilayered gate. As depicted, transistor gate  208  is a single, doped polysilicon layer. In other embodiments, transistor gate  208  may be a metal layer such as copper, or a combination of a metal layer and a polysilicon layer. In this example, transistor gate  208  includes a planar portion, which is parallel to the surface of substrate  202 , and a gating surface, which surrounds the frustoconical protrusion. The out-of-plane gating surface of transistor gate  208  overlaps the portion of the drain that is raised up within the frustoconical protrusion at the bottom and the source region at the top with a channel of intrinsic substrate material in between. A dielectric layer  210  has been deposited before the material that forms transistor gate  208 , so that dielectric layer  210  is in between the frustoconical protrusion and transistor gate  208 . In the depicted embodiment, dielectric layer  210  includes an oxide interfacial layer and a high dielectric constant (high-k) material layer made of HfO. In other embodiments, the interfacial layer may be another insulating material layer. In additional embodiments, dielectric layer  210  may be formed from many different materials, including NiO, TiO, HfO, ZrO, ZnO, WO 3 , Al 2 O 3 , TaO, MoO, and CuO, and high-k materials such as TiO 2 , Ta 2 O 5 , Y 2 O 3 , La 2 O 5 , and HfO 2 . 
     Additionally, a shallow trench isolation feature (STI)  214  is depicted as located underneath the planar portion of transistor gate  208 . STI  214  may be formed by etching a trench in substrate  214  and then filling the trench with an electrically insulating material. The embodiment depicted is an oxide STI  214 , situated directly below the planar portion of transistor gate  208 . Some embodiments may not include an STI  214 , or may not include STI  214  beneath the planar portion of transistor gate  208 . Positioning the STI  214  underneath the planar portion of transistor gate  208  may decrease the effective footprint of TFET  200  on the substrate. 
     An oxide layer  212  covers the surface of substrate  202  and electrically insulates the frustoconical protrusion and the transistor gate  208 . A portion of oxide  212  is situated between STI  214  and transistor gate  208 . In order to make electrical contact for operation and use, TFET  200  includes a drain contact  220 , a gate contact  222 , and a source contact  224 . These three contacts may be formed by first etching holes through oxide layer  212 , and then filling the holes with a conductive material. In the depicted embodiment, drain contact  220 , gate contact  222 , and source contact  224  are tungsten contacts. 
     As shown in  FIG. 2B , drain contact  220 , gate contact  222 , and source contact  224  are arranged in a co-linear arrangement, unlike the traditional MOSFET depicted in  FIG. 1A . Thus, unlike  FIGS. 1A and 1B ,  FIG. 2B  represents a reasonably accurate cross-section of  FIG. 2A  along reference line B. Thus, the embodiment depicted in  FIG. 2B  has drain contact  220 , gate contact  222 , and source contact  224  arranged along reference line B. 
       FIG. 3B  is a P-type embodiment of a TFET  300 . Many aspects of TFET  200  are shared with TFET  200 , and so much of the disclosure above is applicable here as well. Thus, TFET  300  includes a substrate  202 , a drain region  304 , a source region  306 , and a transistor gate  208 . While transistor gate  208  and substrate  202  may be substantially as described above, drain region  304  is a P-type drain region. In the depicted example, drain region  304  has been doped with boron, while other embodiments may include different P-type dopants. Analogously, N-type source region  306  contains phosphorous, but in other embodiments may include arsenic or other N-type dopants. 
     TFET  300  also includes a dielectric layer  210  between transistor gate  208  and the frustoconical protrusion and an STI  214  underneath the planar portion of transistor gate  208 . A drain contact  220 , a gate contact  222 , and a source contact  224  allow electrical signals and voltages to access the various features of TFET  300  through an oxide layer  212 . 
       FIGS. 4A-C  contain several schematic, top view diagrams of TFETs according to various embodiments that highlight some of the flexibility of layouts encompassed by the various embodiments. Referring to  FIG. 4A , TFET  402  is substantially similar to TFET  200  as depicted in  FIG. 2A . Thus, TFET  402  depicts drain contact  220 , source contact  224 , and gate contact  222  as being arranged in a substantially linear arrangement, along reference line D, with drain contact  220  and gate contact  222  as being on opposite sides of the gating surface of transistor gate  208  and source contact  224 . 
     Referring to  FIG. 4B , TFET  404  is an alternative embodiment of an N-type TFET like TFET  402 . However, the contacts of TFET  404  are arranged or laid out differently than those of TFET  402 . While source contact  224  and gate contact  222  are arranged co-linearly along reference line E 1 , but drain contact  220  does not lay on reference line E 1 . Instead, drain contact  220  and source contact  224  are arranged along reference line E 2  that is perpendicular to the reference line E 1 . Thus, a 90 degree angle can be visualized between drain contact  220 , source contact  224 , and gate contact  222 . 
     Referring to  FIG. 4C , TFET  406  is yet another alternative embodiment of an N-type TFET like TFET  402 . Similarly to TFET  404 , not all of contacts  220 ,  222 , and  224  are arranged co-linearly. As depicted, source contact  224  and gate contact  222  are arranged linearly along reference line F 1 , while drain contact  220  and source contact  224  are arranged along reference line F 2  that is perpendicular to the reference line F 1 . 
     Embodiments similar to but different from those depicted by TFETs  402 ,  404 , and  406  are within the scope of this disclosure. For instance, TFETs  402 ,  404 , and  406  may be P-type, rather than N-type, embodiments. Additionally, the angle that can be visualized by the arrangement of drain contact  220 , source contact  224  at the vertex, and gate contact  222  can be any angle. This may allow a circuit designer added flexibility when laying out a circuit design as the TFETs themselves can be angled as needed. Additionally, embodiments such as TFETs  402 ,  404 , and  406 , and others may be rotated to a desired orientation. 
     The embodiments of TFETs  402 ,  404 , and  406  may also be described in terms of the orientations of the generally rectangular drain region  204  and the generally rectangular transistor gate  208 . The orientation of each generally rectangular feature being determined by its longer side. In such terms, TFET  402  is a TFET in which the orientations of drain region  204  and transistor gate  208  are co-linear and transistor gate  208  significantly overlaps drain region  204 . And in these terms, TFETs  404  and  406  are TFETs in which drain region  204  and transistor gate  208  are oriented are a right angle to each other. Thus any embodiments in which drain region  204  and transistor gate  208  are oriented at any angle relative to each other, and have coaxial out-of-plane features (the raised portion of drain region  204  and the gating surface of gate  208 ) may be within the scope of this disclosure. 
       FIGS. 5A-C  depicts schematic, top views of three embodiments that incorporate a number of TFETs similar to TFETs  200  and  300 . For instance,  FIG. 5A  depicts a semiconductor device embodiment that is an inverter  500 . The depicted embodiment of inverter  500  includes two drain regions: N-type drain region  502 A and P-type drain region  502 B. Inverter  500  also includes two source regions: P-type source region  504 A and N-type source region  504 B. These source and drain regions are connected by a single transistor gate  506 , which has a single planar surface for contacting and two gating surfaces, each surrounding the frustoconical protrusions and overlapping the drain regions on the bottom and the source regions on the top as described above. It is understood that in between transistor gate  506  and the source and drain regions is a dielectric layer as explain above. 
     A plurality of leads is depicted as connected to the source contacts, the drain contacts, and the transistor gate contact. Leads  508 A and  508 B can be connected to a supply voltage or ground. In the depicted embodiment, lead  508 B is connected to V DD . Inverter  500  generates an output on lead  508 C that is the inversion of the input signal received on lead  508 D. Additionally, inverter  500  includes two wells: an N-type well surrounding P-type drain region  502 B, and a P-type well surrounding N-type drain region  502 A. While not depicted in this example, inverter  500  may also include an STI feature underneath the planar portion of shared transistor gate  506 , which aid in electrically isolating drain regions  502 A and  502 B from each other. 
       FIG. 5B  depicts a semiconductor device that is a NAND gate  510 . NAND gate  510  includes four TFETS: two P-type TFETs and two N-type TFETs. NAND gate  510  has three drain regions: P-type drain region  512 A is a shared drain region for two P-type TFETs, and two unshared N-type drain regions  512 B and  512 C. P-type drain region  512 A is in an N-type well, while N-type drain regions  512 B and  512 C are in a P-type well. A first shared transistor gate  516 A is connected to P-type drain region  512 A and N-type drain region  512 B and also to N-type source region  514 A and P-type source region  514 B. Similarly, a second shared transistor gate  516 B is connected to P-type drain region  512 A and N-type drain region  512 C and also to N-type source region  514 D and P-type source region  514 C. While not depicted, an STI feature may be located underneath one or both of the first and second shared transistor gates. 
     As depicted, NAND gate  510  also includes a number of leads. In operation, leads  518 A and  518 B are connected to a supply voltage, V DD , while  518 C is connected to ground. Leads  518 D and  518 E receive input signals for NAND gate  510 , which outputs to lead  518 F. Lead  518 F also connects source  514 C to drain  512 B, and lead  518 G connects drain  512 A to source  514 B. It should be noted that care must be taken to prevent any lead from shorting to another lead. This may be done by placement of the leads on a single layer or one multiple layers. Thus, four TFETs may be connected together to form a NAND gate. 
       FIG. 5C  depicts a semiconductor device that is a NOR gate  520 . Like NAND gate  510 , NOR gate  520  includes three drain regions: N-type drain region  522 A and two P-type drain regions  522 B and  522 C. N-type drain region  522 A is in a P-type well, while P-type drain regions  522 B and  522 C are in an N-type well. NOR gate  520  further includes four source regions, which are part of the four TFETs that form NOR  520 . Source regions  524 A and  524 D are both P-type source regions, while source regions  524 B and  524 C are both N-type source regions. A first shared transistor gate  526 A connects to drain  522 A and source  524 A on one side, and to  522 B and  524 B on the other. A second shared transistor gate  526 B is connected to source region  524 C and drain region  522 C on one side and source region  524 D and drain region  522 A on the other side. While not depicted, an STI feature may be located underneath one or both of the first and second shared transistor gates. 
     A number of leads is also depicted in NOR gate  520 . In operation, leads  528 A and  528 B are connected to ground, while  528 C is connected to a supply voltage, V DD . Leads  528 D and  528 E receive input signals for NOR gate  520 , which outputs to lead  528 F. Lead  528 F also connects source  524 C to drain  522 B. Additionally, lead  528 G connects drain  522 A to source  524 B. It should be noted that care must be taken to prevent any lead from shorting to another lead. This may be done by placement of the leads on a single layer or one multiple layers. Thus, four TFETs may be connected together to form a NOR gate. 
     In both NAND gate  510  and NOR gate  520 , the transistor gate contacts for transistor gates  516 A and  526 A are depicted as forming an angle with the other source and drain contacts that is greater than 90 degrees. In other embodiments, the transistor gate contact may be centered within the dimensions of the transistor gate such that a 90 degree angle is formed. In such embodiments, some of the leads, such as  518 G and  528 G, may be rerouted, or additional metal layers may be used to provide access to the drains, sources, and gates. 
       FIG. 6  is a flowchart of a method  600  for forming a FET in which a drain contact is closer to a source contact than a gate contact. Method  600  begins in step  602  when a protrusion is formed on a surface of a substrate. For example, a hard mask layer of SiN may be deposited on the surface of the substrate and etched to form a circle around 100 nm in diameter. Etching the underlying silicon substrate will form a frustoconical protrusion that may range from 50 to 100 nm in height. Method  600  continues in step  604  when dopants are implanted into a lower portion of the protrusion. In this example, this may be done by implanting the dopants adjacent to the frustoconical protrusion and using a rapid thermal annealing (RTA) process to diffuse and activate the dopants. The RTA can diffuse the dopants laterally, so they extend underneath the protrusion, and also vertically, so the dopants that form the drain region move upward into the protrusion. Thus, the drain region may extend from the surface of the substrate into the lower portion of the protrusion. In the example, the implanted dopants are phosphorous dopants, while in other embodiments, the dopants may be P-type dopants, such as boron, or other N-type dopants such as arsenic. 
     In step  606 , dopants are implanted into an upper portion of the protrusion to form the source region. In the example, boron is implanted into the top of the protrusion to create a P-type source region. The dopants are activated with a laser spike annealing process to create an abrupt source/channel interface. In embodiments where the drain region is a P-type drain region, the source region may be doped with N-type dopants. In step  608 , a source contact, a drain contact, and a gate contact are formed. The source contact allows an electrical connection to the made to the source region; the drain contact allows an electrical connection to be made to the drain region, and the gate contact allows an electrical connection to be made to the transistor gate. The contacts are formed so that the drain contact is closer to the source contact than to the gate contact. Some embodiments of method  600  produce a tunneling field-effect transistor that is vertically configured. 
     In the example, a mask with at least three openings is applied to an oxide layer covering the source and drain regions and the gate. After etching the wafer, the three holes are filled with electrically conductive tungsten to form the source, drain, and gate contacts. The contacts are formed to match the arrangement of the source region, the drain region, and the gate. The contacts in the example, like that of  FIG. 2A , are formed in a co-linear arrangement, such that the three contacts are in line with the drain contact on one side of the source contact, and the gate contact is opposite the drain contact. In other embodiments, the underlying FET structure may be such that the contacts are not formed in a co-linear arrangement, but in another arrangement. Such would be the case where the drain region and the planar surface of the transistor gate are oriented relative to each other at a 90 degree angle as described in connection with  FIGS. 4A and 4B  above. So one alternative embodiment includes the three contacts forming a right angle, with the source contact at the vertex of the angle. Other embodiments in which the drain contact is closer to the source contact than to the gate contact are within the scope of this disclosure. 
     The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the detailed description. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.