Abstract:
An apparatus, for use in a Reed-Solomon decoder, evaluates a polynomial P(X) iteratively, by substituting α - (N-j) for X in a jth iteration, to thereby provide a jth evaluation result P(α - (N-j)), wherein j is an integer ranging from 1 to N, N being a predetermined positive integer, and α is a primitive element in a finite field GF(2 m ). The apparatus comprises: a FIFO buffer having T registers, T being a predefined positive integer; a root input block for sequentially providing a first group of T elements in the finite field during the jth iteration; a multiplier for sequentially multiplying the contents of the FIFO buffer with the first group of T elements in the finite field provided from the root input block, to thereby provide a jth set of T evaluating terms during the jth iteration; a multiplexor for providing T initial evaluating terms to the FIFO buffer during an initialization and providing the jth set of T evaluating terms to the FIFO buffer during the jth iteration, to be stored therein; an addition block for determining a sum of the T evaluating terms of the jth set, to thereby provide a jth sum; and an output block for adding a 0th coefficient of the polynomial to the jth sum, to thereby provide the jth evaluation result during the jth iteration.

Description:
FIELD OF THE INVENTION 
     The present invention relates to an apparatus for correcting errors present in stored or transmitted data; and, more particularly, to an apparatus for evaluating an error evaluator polynomial, an error locator polynomial and a differential polynomial which are used in correcting errors in the data encoded by using a Reed-Solomon code. 
     DESCRIPTION OF THE PRIOR ART 
     Noises occurring during a process of transmitting, storing or retrieving data can in turn cause errors in the transmitted, stored or retrieved data. Accordingly, various encoding techniques, having the capability of rectifying such errors, for encoding the data to be transmitted or stored have been developed. 
     In such encoding techniques, a set of check bits is appended to a group of message or information bits to form a codeword. The check bits, which are determined by an encoder, are used to detect and correct the errors. In this regard, the encoder essentially treats the bits comprising the message bits as coefficients of a binary message polynomial and derives the check bits by multiplying the message polynomial i(X) with a code generating polynomial g(X) or dividing i(X) by g(X), to thereby provide ea codeword polynomial c(X). The code generating polynomial is selected to impart desired properties to a codeword upon which it operates so that the codeword will belong to a particular class of error-correcting binary group codes (see, e.g., S. Lin et al., &#34;Error Control Coding: Fundamentals and Applications&#34;, Prentice-Hall, 1983). 
     One class of error correcting codes is the well-known BCH (Bose-Chaudhuri-Hocquenghen) codes, which include the Reed-Solomon (&#34;RS&#34;) code. The mathematical basis of the RS code is explained in, e.g., the aforementioned reference by Lin et al. and also in Berlekamp, &#34;Algebraic Coding Theory&#34;, McGraw-Hill, 1968, which is further referred to in U.S. Pat. No. 4,162,480 issued to Berlekamp. 
     If roots of the generator polynomial g(X) of the RS code are 2T consecutive powers of α as in Eq. (1), T being a predetermined positive integer, as many as T errors can be corrected: ##EQU1## wherein α is a primitive element in a finite field GF(2 m ). 
     In the process of receiving or retrieving a transmitted or stored codeword, certain attendant noises may have been converted to an error pattern in the codeword. In order to deal with the error pattern imposed upon the RS code, a four step procedure is generally utilized. In discussing the error-correcting procedure, reference shall be made to a RS code consisting of codewords containing N M-bit symbols, N and M being positive integers, (of which K symbols are informational symbols and (N-K) symbols are check symbols, K being a positive integer smaller than N). In that case, c(X) becomes an (N-1)st order polynomial and 2T equals (N-K). As a first error correcting step, syndromes S 0 , S 1 , . . . , S 2T-1  are calculated from a received codeword polynomial r(X), i.e., an (N-1)st order polynomial representing the received codeword. The received codeword polynomial r(X) is represented as r N-1  X N-1  +r N-2  + . . . +r 1  X 1  +r 0 , wherein r j  is an (N-j)th symbol of a codeword. As a second step, using the syndromes, coefficients of an error locator polynomial σ(X) are calculated. In a third step, the error locator polynomial σ(X) is solved to obtain its roots, which represent the error locations in the received codewords. Specifically, if substituting a power of the primitive element, α -j , for a variable X in the error locator polynomial σ(X) results in 0 (i.e., α -j  becomes a root of σ(X)), it means that an error has occurred in r j , i.e., (N-j)th symbol of a codeword. 
     As a fourth step, error values are calculated by using the error locations and the syndromes. Mathematical expressions for the syndromes and the coefficients of the error locator polynomial are set forth in the afore-referenced U.S. Pat. No. 4,162,480 issued to Berlekamp. 
     The fourth step will be now explained in more detail. 
     First, an error evaluator polynomial Ω(X) may be obtained as follows: 
     
         Ω(X)=σ(X)S(X)                                  Eq. (2) 
    
     wherein S(X) is a syndrome polynomial whose coefficients are the syndromes. 
     After deriving the error evaluation polynomial Ω(X), an error value e j  may be calculated as ##EQU2## wherein σ&#39;(X) is the first derivative of the error locator polynomial σ(X); α -j  is the root of the error locator polynomial obtained in the third step; and the error value e j  corresponds to the (N-j)th symbol which is an error location obtained in the third step. 
     After finding the error values, the original codeword can be recovered by adding the error values to the corresponding symbols. 
     As explained above, polynomial evaluation is used in various stages of error correcting procedures, wherein the polynomial evaluation for α -j  refers to substitution of the finite field element α -j  for a variable X in a given polynomial p(X). First, the error locator polynomial σ(X) is evaluated in the third step to find error locations. In the fourth step, the error evaluator polynomial Ω(X) and the differential polynomial σ&#39;(X) are evaluated to determine error values. 
     The error evaluator polynomial Ω(X) may be represented as ##EQU3## Accordingly, evaluating Ω(X) for X=α -j  gives ##EQU4## wherein j is an integer ranging from 0 to N-1, and multiplications and additions are done on the finite field GF(2 m ). Evaluation results for other polynomials may be represented in a similar manner. 
     Referring to FIG. 1, there is shown an exemplary block diagram of a conventional polynomial evaluator 10 which is disclosed in a copending commonly owned application, U.S. Ser. No. 08/755,581, entitled &#34;Polynomial Evaluator for use in a Reed-Solomon Decoder&#34;. The evaluator 10 shown in FIG. 1 evaluates the error evaluator polynomial Ω(X) by implementing Eq. (5B) in case of T=8. 
     The polynomial evaluator 10 includes a multiplier 11 operating on the finite field GF(2 m ), a root input block 12, a multiplexor (&#34;MUX&#34;) 16, a register block 18, an addition block 13 and an output block 14. 
     At the polynomial evaluator 10, the calculation of Eq. (5B) is done iteratively from j=0 to N-1. An iteration may be preferably done in one system clock cycle. 
     Before starting the 0th iteration of the evaluation procedure for determining Ω(α 0 ), the registers included in the register block 18 are initialized with Ω i  &#39;s. To do this, each of the coefficients of the error evaluator polynomial (Ω 1  to Ω 8 ) is sequentially fed through the MUX 16 to the register block 18 one for one bit clock cycle. A selection signal SEL1 controls the MUX 16 to provide Ω i  on an input port 0 to the register block 18 for the initialization. A first coefficient Ω 1  is first fed to R 1  and stored therein for a bit clock cycle. The contents of R 1  are shifted to R 2  and stored therein for a next bit clock cycle, and then to R 3 , and so on. Finally, the output of R 8  is fed to the multiplier 11. In conclusion, a coefficient is stored in each of the registers sequentially for a bit clock cycle as it is shifted through the registers before it is fed to the multiplier 11. 
     After each of the registers is filled with a corresponding Ω i  (e.g., Ω 1  in R 8 , Ω 2  in R 7 , and so on), the 0th iteration for determining Ω(α 0 ) begins. 
     During the first bit clock of the 0th iteration, the multiplier 11 multiplies 1 with Ω 1 , provided thereto from R 8 . To do this, 1 is fed from the root input block 12 to the multiplier 11. (It should be rioted that, during the 2nd to Nth iterations, α -i  &#39;s, i being 1 to 8, are fed to the multiplier 11, to be multiplied to the corresponding evaluating terms provided from the register block 18.) The output of the multiplier 11, i.e., Ω 1  (or in other words, 1st evaluating term of the 0th set, the 0th set of evaluating terms referring to Ω i  α 0  &#39;s), is fed to the addition block 13 one per one bit clock cycle. 
     The addition block 13 includes a two input adder 13a and a register 13b, wherein the adder 13a operating on the finite field GF(2 m ) sequentially adds each of the evaluating terms provided from the multiplier 11 to the contents of the register 13b and the register 13b stores a 1st to 7th partial sum of the evaluating terms provided from the adder 13a and feeds the partial sum to the two input adder 13a, the Lth partial sum referring to sums of L evaluating terms, L being 1 to 7, in the course of sequential addition of Eq. (5B). 
     Specifically, upon receiving Ω 1  from the multiplier 11, the adder 13a adds it to the initial content, i.e., 0, of the register 13b. Then the 1st partial sum, Ω 1 , is fed back to the register 13b, to be stored therein, e.g., at the rising edge of the next bit clock. Ω 1  provided from the multiplier 11 is also fed to the register block 18, to thereby shift the contents of each register to right, e.g., on the rising edge of the second bit clock of the first iteration. The contents of the registers, during the second bit clock cycle, are given in Table 1. 
     
                       TABLE 1______________________________________R.sub.1 R.sub.2  R.sub.3                R.sub.4 R.sub.5                            R.sub.6                                   R.sub.7                                       R.sub.8______________________________________Ω.sub.1 Ω.sub.8          Ω.sub.7                Ω.sub.6                        Ω.sub.5                            Ω.sub.4                                   Ω.sub.3                                       Ω.sub.2______________________________________ 
    
     During the second bit clock of the 0th iteration, the multiplier 11 multiplies 1 with Ω 2  provided thereto from R 8 . The output of the multiplier 11, i.e., Ω 2  at this time, is fed to the adder 13a, wherein it is added to the contents of the register 13b, i.e., Ω 1 . Then the second partial sum, Ω 1  +Ω 2 , is fed back to the register 13b, to be stored therein. Ω 2  from the multiplier 11 is fed to the register block 18, to thereby shift contents of each register to right on the rising edge of the next bit clock cycle. Then, the contents of the registers are changed as given in Table 2. 
     
                       TABLE 2______________________________________R.sub.1 R.sub.2  R.sub.3                R.sub.4 R.sub.5                            R.sub.6                                   R.sub.7                                       R.sub.8______________________________________Ω.sub.2 Ω.sub.1          Ω.sub.8                Ω.sub.7                        Ω.sub.6                            Ω.sub.5                                   Ω.sub.4                                       Ω.sub.3______________________________________ 
    
     By repeating the above procedure for the remaining bit clock cycles of the 0th iteration, Ω 1  to Ω 8  is summed at the addition block 13. The addition block 13 finally provides an 8th partial sum, i.e., a sum of the 8 evaluating terms (Ω 1  α -j  +Ω 2  α -2j  + . . . Ω 8  α -8j , j=0 at this time) to the output block 14. The sum, i.e., Ω 1  +Ω 2  + . . . +Ω 8 , is fed to and stored in R 10  under the contorl of a signal RST --  SUM provided externally and then fed to an adder 14b wherein it is added to Ω 0 , to thereby provide the final evalaution result of the 0th iteration, i.e., 0th evaluation result Ω(α 0 ). RST --  SUM is a signal that notifies the time when an evaluation result is provided from the adder 13a. RST --  SUM may be a signal that goes to &#34;1&#34; at the end of each iteration (equivalently at the start of a next iteration). RST --  SUM also serves to initialize the register 13b with 0 for a next iteration. (Note that the content of register 13b should be 0 at the start of each iteration.) 
     The first iteration is similar to the 0th iteration except that α -i , instead of 1, is multiplied with an output from the register block 18, Ω i , one by one at the multiplier 11, to provide a first set of evaluating terms Ω i  α -i  &#39;s to the addition block 13 and back to the register block 18. Specifically, α -1  is multiplied with Ω 1  during the first bit clock cycle, α -2  with Ω 2  during the second bit clock cycle, and so on. By summing the first set of evaluating terms, Ω i  α -i  &#39;s, the first evaluation result Ω(α -1 ) is obtained at the end of the first iteration. By repeating the above procedure, Ω(α -j )&#39;s for j=0 to N-1 are obtained in N iterations. 
     The contents of the registers R 1  to R 8  and R 9  for each bit clock cycle of the 0th to 2nd iterations are shown in Table 3, wherein each row corresponds to each bit clock cycle. 
     
                       TABLE 3______________________________________iteration R.sub.1 R.sub.2 . . .                      R.sub.7                            R.sub.8                                  R.sub.9______________________________________0th   Ω.sub.8         Ω.sub.7                 . . .                      Ω.sub.2                            Ω.sub.1                                  0 Ω.sub.1         Ω.sub.8                      Ω.sub.3                            Ω.sub.2                                  Ω.sub.1 .       .            .     .     . .       .            .     .     . .       .            .     .     . Ω.sub.7         Ω.sub.6                      Ω.sub.1                            Ω.sub.8                                  Ω.sub.1 + . . .                                  + Ω.sub.71st   Ω.sub.8         Ω.sub.7                 . . .                      Ω.sub.2                            Ω.sub.1                                  0 Ω.sub.1 α.sup.-1         Ω.sub.8                      Ω.sub.3                            Ω.sub.2                                  Ω.sub.1 α.sup.-1 Ω.sub.2 α.sup.-2         Ω.sub.1 α.sup.-1                      Ω.sub.4                            Ω.sub.3                                  Ω.sub.1 α.sup.-1 +                                  Ω.sub.2 α.sup.-2 .       .            .     .     . .       .            .     .     . .       .            .     .     . Ω.sub.7 α.sup.-7         Ω.sub.6 α.sup.-6                      Ω.sub.1 α.sup.-1                            Ω.sub.8                                  Ω.sub.1 α.sup.-1 + . .                                  . +                                  Ω.sub.7 α.sup.-72nd   Ω.sup.8 α.sup.-8         Ω.sub.7 α.sup.-7                 . . .                      Ω.sub.2 α.sup.-2                            Ω.sub.1 α.sup.-1                                  0 Ω.sub.1 α.sup.-2         Ω.sub.8 α.sup.-8                      Ω.sub.3 α.sup.-3                            Ω.sub.2 α.sup.-2                                  Ω.sub.1 α.sup.-2 Ω.sub.2 α.sup.-4         Ω.sub.1 α.sup.-2                      Ω.sub.4 α.sup.-4                            Ω.sub.3 α.sup.-3                                  Ω.sub.1 α.sup.-2 +                                  Ω.sub.2 α.sup.-4 .       .            .     .     . .       .            .     .     . .       .            .     .     . Ω.sub.7 α.sup.-14         Ω.sub.6 α.sup.-12                      Ω.sub.1 α.sup.-2                            Ω.sub.8 α.sup.-8                                  Ω.sub.1 α.sup.-2 + . .                                  . +                                  Ω.sub.7 α.sup.-14______________________________________ 
    
     In accordance with the conventional polynomial evaluator explained above, the evaluation results are provided sequentially in the order of Ω(α 0 ), Ω(α -1 ), . . . , Ω(α - (N-1)), which in turn renders the error value e j  with a smaller j be provided first. However, the received symbol is provided in the order of r N-1  to r 0 . Therefore, to correct the errors in the codeword, the received symbol r j  should first be stored in a LIFO (Last In First Out) buffer and provided in a reversed order before it is added to a corresponding error value e j . 
     SUMMARY OF THE INVENTION 
     It is, therefore, a primary object of the present invention to provide a polynomial evaluator which provides evaluation results in such an order that the evaluation results used in determining an error value for a first received symbol be provided first. 
     In accordance with the present invention, there is provided an apparatus, for use in a Reed-Solomon decoder, for evaluating a polynomial P(X) iteratively, by substituting α - (N-j) for X in a jth iteration, to thereby provide a jth evaluation result P(α - (N-j)), wherein j is an integer ranging from 1 to N, N being a predetermined positive integer, and α is a primitive element in a finite field GF(2 m ), the apparatus comprising: 
     a FIFO buffer having T registers, T being a predefined positive integer; 
     updating means for sequentially multiplying the contents of the FIFO buffer with a first group of T elements in the finite field, to thereby provide a jth set of T evaluating terms during the jth iteration; 
     a multiplexor for providing T initial evaluating terms to the FIFO buffer during an initialization and providing the jth set of T evaluating terms to the FIFO buffer during the jth iteration, to be stored therein; 
     an addition block for determining a sum of the T evaluating terms of the jth set, to thereby provide a jth sum; and 
     an output block for adding a 0th coefficient of the polynomial to the jth sum, to thereby provide the jth evaluation result during the jth iteration. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments given in conjunction with the accompanying drawings, in which: 
     FIG. 1 shows a block diagram of a conventional polynomial evaluator; 
     FIG. 2 illustrates a block diagram of a first embodiment of the polynomial evaluator for evaluating an error evaluator polynomial in accordance with the present invention; 
     FIG. 3 presents a block diagram of a second embodiment of the polynomial evaluator for evaluating an error locator polynomial in accordance with the present invention; and 
     FIG. 4 provides a block diagram of a third embodiment of the polynomial evaluator for evaluating a differential polynomial in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 2, there is provided a block diagram of a first embodiment of the polynomial evaluator in accordance with the present invention, which evaluates the error evaluator polynomial Ω(X) according to ##EQU5## for j=N-1 to 0, wherein T is set to 8 for the purpose of illustration. 
     At the polynomial evaluator 20, the calculation of Eq. (5B) is done iteratively from j=N-1 to 0 in that order, which is one of the main differences from the conventional evaluator shown in FIG. 1. An iteration may be preferably done in one system clock cycle. 
     The polynomial evaluator 20 shown in FIG. 2 includes a multiplier 21 operating on the finite field GF(2 m ), a root input block 22, a multiplexor (&#34;MUX&#34;) 26, an addition block 23, an output block 24 and a register block 28, which directly correspond to those of the conventional evaluator shown in FIG. 1. It also includes a multiplier 25 operating on the finite field GF(2 m ) and a root input block 27 which is used in initializing the register block 28. 
     While the register block 18 shown in FIG. 1 is initialized with the coefficients of the evaluator polynomial Ω i  &#39;s, the register block 28 shown in FIG. 2 is initialized with initial evaluating values (Ω i  α -iN  &#39;s) with the help of the multiplier 25 and the root input block 27. 
     Before starting a first iteration of the evaluation procedure for determining Ω(α - (N-1)), the registers included in the register block 28 are initialized with Ω i  α -iN  &#39;s. To do this, each of the coefficients of the error evaluator polynomial Ω i  is multiplied to α -iN , to sequentially provide a set of 8 initial evaluating terms Ω i  α -iN  &#39;s to an input port 0 of the MUX 26. A selection signal SEL1 controls the MUX 26 to provide Ω i  α -iN  to the register block 28 for the initialization. A first initial evaluating term Ω 1  α -N  is first fed to R 1  and stored therein for a bit clock cycle. The content of R 1  is shifted to R 2  and stored therein for a next bit clock cycle, and then to R 3 , and so on. Finally, the output port of R 8  is connected to the multiplier 21. 
     After each of the registers is filled with a corresponding Ω i  α -iN  (e.g., Ω 1  α -N  in R 8 , Ω 2  α -2N  in R 7 , and so on), the first iteration for determining Ω(α - (N-1)) begins. 
     During the first bit clock of the first iteration, the multiplier 21 multiplies α 1  with Ω 1  α -N  provided thereto from R 8 . To do this, α 1  is fed from the root input block 22 to the multiplier 21. The output of the multiplier 21, i.e., Ω 1  α - ((N-1) (or in other words, 1st evaluating term of a first set, the Kth set of evaluating terms referring to Ω i  α - (N-K) &#39;s, K being 1 to N), is fed to the addition block 23 one per one bit clock cycle. Note that α i  (instead of α -i  as in the conventional evaluator) is multiplied to the evaluating terms provided from the register block 28, to update the evaluating terms. 
     The addition block 23 includes a two input adder 23a and a register 23b, wherein the adder 23a operating on the finite field GF(2 m ) sequentially adds each of the evaluating terms provided from the multiplier 21 to the contents of the register 23b, and the register 23b stores a 1st to 7th partial sum of the evaluating terms provided from the adder 23a and feeds the partial sum to the two input adder 23a, the Lth partial sum referring to sums of L evaluating terms included in a same set, L being 1 to 7, in the course of sequential addition of Eq. (5B). It also includes a multiplexor (&#34;MUX&#34;) 23c for selectively providing 0 or the output of the adder 23a to the register 23b under the control of RST --  SUM which is essentially identical to that shown in FIG. 1. RST --  SUM also serves to initialize the register 23b by rendering MUX to provide 0 to the register 23b at the start of each iteration. 
     Specifically, upon receiving Ω 1  α - (N-1) from the multiplier 21, the adder 23a adds it to the initial content, i.e., 0, of the register 23b. Then the 1st partial sum, Ω 1  α - (N-1), is fed back through the MUX 23c to the register 23b, to be stored therein, e.g., at the rising edge of the next bit clock. To do this, the MUX 23c provides the output of the adder 23a to the register 23b in response to RST --  SUM. Ω 1  α - (N-1) provided from the multiplier 21 is also fed to the register block 28, to thereby shift the contents of each register to right, e.g., at the rising edge of the second bit clock of the first iteration. The contents of the registers, during the second bit clock cycle, are given in Table 4. 
     
                       TABLE 4______________________________________R.sub.1  R.sub.2   R.sub.3 . . .  R.sub.7                                   R.sub.8______________________________________Ω.sub.1 α.sup.-(n-1)    Ω.sub.8 α.sup.-8N              Ω.sub.7 α.sup.-7N                      . . .  Ω.sub.3 α.sup.-3N                                   Ω.sub.2 α.sup.-2N______________________________________ 
    
     During the second bit clock cycle of the first iteration, the multiplier 21 multiplies α 2  to Ω 2  α -2N  provided thereto from R 8 . The output of the multiplier 21, i.e., Ω 2  α -2 (N-1) at this time, is fed to the adder 23a, wherein it is added to the contents of the register 23b, i.e., Ω 1  α - (N-1). Then the second partial sum, Ω 1  α - (N-1) +Ω 2  α -2 (N-1), is fed back through the MUX 23c to the register 23b, to be stored therein. Ω 2  α -2 (N-1) from the multiplier 21 is also fed to the register block 28, to thereby shift contents of each register to right at the rising edge of the next bit clock cycle. Then, the contents of the registers are changed as given in table 5. 
     
                       TABLE 5______________________________________R.sub.1  R.sub.2    R.sub.3 . . .  R.sub.7                                  R.sub.8______________________________________Ω.sub.2 α.sup.-2(n-1)  Ω.sub.1 α.sup.-(N-1)             Ω.sub.8 α.sup.-8N                     . . .  Ω.sub.4 α.sup.-4N                                  Ω.sub.3 α.sup.-3N______________________________________ 
    
     By repeating the above procedure for the remaining bit clock cycles of the first iteration, Ω 1  α - (N-1) to Ω 8  α -8 (N-1) is summed at the addition block 23. The adder 23a finally provides an 8th partial sum, i.e., a sum of the 8 evaluating terms (Ω 1  α - (N-1) +Ω 2  α -2 (N-1) + . . . +Ω 8  α -8 (N-1)) of the first set to the output block 24. The sum is fed to and stored in Ri 0  in response to RST --  SUM and then fed to an adder 24b wherein it is added to Ω 0 , to thereby provide the final result of the first iteration, i.e., the first evaluation result Ω(α - (N-1)). At the same time, the register 23b is initialized to 0 provided from the MUX 23c in response to RST --  SUM for a next iteration. 
     A second iteration is similar to the first iteration except that a second set of evaluating terms Ωα -i (N-2) &#39;s is provided from the multiplier 21 to the addition block 23 and back to the register block 28. Specifically, α 1  is multiplied with Ω 1  α - (N-1) during the first bit clock cycle, α 2  with Ω 2  α -2 (N-1) during the second bit clock cycle, and so on, to provide the second set of evaluating terms. By summing the second set of evaluating terms, Ω i  α -i (N-2) &#39;s, the second evaluation result Ω(α - (N-2)) is obtained at the end of the second iteration. By repeating the above procedure, Ω(α -j )&#39;s for j=N-1 to 0 are obtained in N iterations. 
     The contents of the registers R 1  to R 8  and R 9  for each bit clock cycle of the first to third iterations are shown in Table 6, wherein each row corresponds to each bit clock cycle. 
     
                                           TABLE 6__________________________________________________________________________itera-tion R.sub.1      R.sub.2           . . .                R.sub.8                      R.sub.9__________________________________________________________________________1st  Ω.sub.8 α.sup.-8N      Ω.sub.7 α.sup.-7N           . . .                Ω.sub.1 α.sup.-N                      0Ω.sub.1 α.sup.-(N-1)      Ω.sub.8 α.sup.-8N                Ω.sub.2 α.sup.-2N                      Ω.sub.1 α.sup.-(N-1).     .         .     ..     .         .     ..     .         .     .Ω.sub.7 α.sup.-7(N-1)      Ω.sub.6 α.sup.-6(N-1)                Ω.sub.8 α.sup.-8N                      Ω.sub.1 α.sup.-(N-1) +. . .                      +Ω.sub.7 α.sup.-7(N-1)2nd  Ω.sub.8 α.sup.-8(N-1)      Ω.sub.7 α.sup.-7(N-1)           . . .                Ω.sub.1 α.sup.-(N-1)                      0Ω.sub.1 α.sup.-(N-2)      Ω.sub.8 α.sup.-8(N-1)                Ω.sub.2 α.sup.-2(N-1)                      Ω.sub.1 α.sup.-(N-2)Ω.sub.2 α.sup.-2(N-2)      Ω.sub.1 α.sup.-(N-2)                Ω.sub.3 α.sup.-3(N-1)                      Ω.sub.1 α.sup.-(N-2)                      + Ω.sub.2 α.sup.-2(N-2).     .         .     ..     .         .     ..     .         .     .Ω.sub.7 α.sup.-7(N-2)      Ω.sub.6 α.sup.-6(N-2)                Ω.sub.8 α.sup.-8(N-1)                      Ω.sub.1 α.sup.-(N-2) +. . .                      +Ω.sub.7 α.sup.-7)N-2)3rd  Ω.sub.8 α.sup.-8(N-2)      Ω.sub.7 α.sup.-7(N-2)           . . .                Ω.sub.1 α.sup.-(N-2)                      0Ω.sub.1 α.sup.-(N-3)      Ω.sub.8 α.sup.-8(N-2)                Ω.sub.2 α.sup.-2(N-2)                      Ω.sub.1 α.sup.-(N-3)Ω.sub.2 α.sup.-2(N-3)      Ω.sub.1 α.sup.-(N-3)                Ω.sub.3 α.sup.-3(N-2)                      Ω.sub.1 α.sup.-(N-3)                      + Ω.sub.2 α.sup.-2(N-3).     .         .     ..     .         .     ..     .         .     .Ω.sub.7 α.sup.-7(N-3)      Ω.sub.6 α.sup.-6(N-3)                Ω.sub.8 α.sup.-8(N-2)                      Ω.sub.1 α.sup.-(N-3)+. . .                      +Ω.sub.7 α.sup.-7(N-3)__________________________________________________________________________ 
    
     Referring now to FIG. 3, there is provided a block diagram of another embodiment of the polynomial evaluator in accordance with the present invention, which evaluates the error locator polynomial σ(X). The structure and function of the evaluator 30 shown in FIG. 3 are essentially identical to those of the evaluator 20 except an additional error decision block 39. As the object of the evaluator 30 is to evaluate the error locator polynomial, the coefficients of the error locator polynomial aj are fed to a multiplier 35. By the same procedure explained with reference to FIG. 2, an output block 34 provides the evaluation result σ(α -j ), j=N-1 to 0 in that order, for each iteration. 
     At the error decision block 39, in case σ(α -j ) is 0, an error signal, which notifies that an error has occurred at a corresponding symbol r j  of a codeword, is generated. It should be noted that as the evaluation result for larger j is determined first, r j  with larger j is first examined for its error. 
     Referring to FIG. 4, there is provided a block diagram of a third embodiment of the polynomial evaluator in accordance with the present invention, which evaluates the differential polynomial σ&#39;(X), i.e., the first derivative of the error locator polynomial σ(X). 
     When the error locator polynomial is an 8th order polynomial represented as 
     
         σ(X)=σ.sub.0 +σ.sub.1 X+σ.sub.2 X.sup.2 +σ.sub.3 X.sup.3 σ.sub.4 X.sup.4 σ.sub.5 X.sup.5 +σ.sub.6 X.sup.6 σ.sub.7 X.sup.7 30 σ.sub.8 X.sup.8,Eq. (6) 
    
     the differential polynomial is given as 
     
         σ&#39;(X)=σ.sub.1 +2σ.sub.2 X.sup.1 +3σ.sub.3 X.sup.2 +4σ.sub.4 X.sup.3 +5σ.sub.5 X.sup.4 +6σ.sub.6 X.sup.5 +7σ.sub.7 X.sup.6 +8σ.sub.8 X.sup.7           Eq.(7A) 
    
     Since two identical numbers in the finite field yield 0, Eq. (7A) is further simplified as 
     
         σ(X)=σ.sub.1 +σ.sub.3 X.sup.2 +σ.sub.5 X.sup.4 +σ.sub.7 X.sup.6                                    Eq. (7B) 
    
     Accordingly, evaluating σ&#39; (X) for α -j  gives ##EQU6## The structure of the evaluator is modified to deal with Eq. (7C), which distinguishes the evaluator 40 from the evaluator 20. Specifically, as the evaluation result of the differential polynomial includes only even powers of α, the root input blocks 42 and 47 provides only even powers of α, i.e., (α 0 , α 2 , α 4 , α 6 ) and (α 0 , α -2N , α -4N , α -6N ); the register block 48 includes half as many registers as those of other evaluators shown in FIGS. 2 and 3; only coefficients of odd power terms, i.e., σ 1 , σ 3 , σ 5 , σ 7 , are provided to a multiplier 45 in the finite field GF(2 m ); and the output block 44 does not include an adder, for the 0th coefficient (σ 0 ) is not included in the evaluation result. Except these, overall operation of the evaluator is similar to the evaluator 20 shown in FIG. 2. The contents of the registers R 1  to R 5  for each bit clock cycle of first to third iterations are shown in Table 7, wherein each row may correspond to each bit clock cycle. 
     
                       TABLE 7______________________________________iter-ationR.sub.1  R.sub.2  R.sub.4                         R.sub.5______________________________________1st  Ω.sub.7 α.sup.-6N         Ω.sub.5 α.sup.-4N                  Ω.sub.1                         0Ω.sub.1         Ω.sub.7 α.sup.-6N                  Ω.sub.3 α.sup.-2N                         Ω.sub.1Ω.sub.3 α.sup.-2(N-1)         Ω.sub.1                  Ω.sub.5 α.sup.-4N                         Ω.sub.1 + Ω.sub.3 α.sup.-2                         (N-1)Ω.sub.5 α.sup.-4(N-1)         Ω.sub.3 α.sup.-2(N-1)                  Ω.sub.7 α.sup.-6N                         Ω.sub.1 + Ω.sub.3 α.sup.-2                         (N-1) + Ω.sub.5 α.sup.-4(N-1)2nd  Ω.sub.7 α.sup.-6(N-1)         Ω.sub.5 α.sup.-4(N-1)                  Ω.sub.1                         0Ω.sub.1         Ω.sub.7 α.sup.-6(N-1)                  Ω.sub.3 α.sup.-2(N-1)                         Ω.sub.1Ω.sub.3 α.sup.-2(N-2)         Ω.sub.1                  Ω.sub.5 α.sup.-4(N-1)                         Ω.sub.1 + Ω.sub.3 α.sup.-2                         (N-2)Ω.sub.5 α.sup.-4(N-2)         Ω.sub.3 α.sup.-2(N-2)                  Ω.sub.7 α.sup.-6(N-1)                         Ω.sub.1 + Ω.sub.3 α.sup.-2                         (N-2) + Ω.sub.5 α.sup.-4(N-2)3rd  Ω.sub.7 α.sup.-6(N-2)         Ω.sub.5 α.sup.-4(N-2)                  Ω.sub.1                         0Ω.sub.1         Ω.sub.7 α.sup.-6(N-2)                  Ω.sub.3 α.sup.-2(N-2)                         Ω.sub.1Ω.sub.3 α.sup.-2(N-3)         Ω.sub.1                  Ω.sub.5 α.sup.-4(N-2)                         Ω.sub.1 + Ω.sub.3 α.sup.-2                         (N-3)Ω.sub.5 α.sup.-4(N-3)         Ω.sub.3 α.sup.-2(N-3)                  Ω.sub.7 α.sup.-6(N-2)                         Ω.sub.1 + Ω.sub.3 α.sup.-2                         (N-3) + Ω.sub.5 α.sup.-4(N-3)______________________________________ 
    
     As explained above, the evaluator in accordance with the present invention provides the evaluation results in a reversed order compared with the conventional evaluator. 
     While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.