Abstract:
A method and apparatus detects a ground fault on a span-powered telecommunication wireline within a plurality of span-powered wireline segments, to respective ones of which DSL-Cs are coupled, so that a ground fault may be detected when power is delivered by the DSL-C over a respective wireline segment to a respective downstream functional RT. A respective DSL-C measures a first voltage across a first sense resistor representative of current flowing in a first portion of its wireline segment to the RT, and also measures a second voltage across a second sense resistor representative of current flowing in a second portion of the wireline segment from the RT. In response to a difference in the first and second voltages an output representative of a ground fault in that wireline segment is generated.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates in general to electrical power systems and subsystems of the type used for span-powering multiple telecommunication equipments, and is particularly directed to a new and improved ground fault detection and isolation scheme for use with multiple electrical loads (transceivers), that are connected by way of respectively different wireline links to a common power source installed at a facility such as a central office.  
       BACKGROUND OF THE INVENTION  
       [0002]     Local Exchange Carriers (LECs) within the telecommunication industry have implemented a variety of digital transmission systems to service their customers. As diagrammatically illustrated in  FIG. 1 , a typical digital transmission system may contain a first (network or central office site-associated) transceiver unit  10  that is coupled to a first (e.g., central office) end  21  of a single twisted pair of telephone wires (or span)  20 , and a second (remote site-associated) transceiver unit  30  coupled to a remote end  22  of the twisted pair  20 . Also, the central office transceiver unit  10  may be equipped to supply electrical power over twisted pair  20  to remote transceiver  30 .  
         [0003]     In such a ‘span-powered’ configuration, it is often desirable for multiple central office transceiver units to derive span power for their respective remote transceiver units from a common or shared electrical power source. When a system incorporates span-powering of multiple remote units from a common electrical power source, there is the possibility that any individually span-powered twisted pair telephone line may incur an insulation failure—resulting in an electrical current path to earth. This electrical current path to earth is known as a ‘ground fault’ and a person&#39;s body can serve as this path. A ground faulted telephone line can present a hazardous voltage condition to service personnel and can interrupt normal power source operation, which results in transceiver malfunction on all of the connected twisted pair telephone lines.  
         [0004]     Hazardous voltage, power source interruption and resulting multiple transceiver malfunction are unacceptable network conditions. If the particular twisted pair telephone line that is ground-faulted can be identified, then that particular line can be isolated from the power source and the remaining multiple span-powered twisted pair telephone lines and associated transceivers can continue normal operation and the hazardous voltage can be isolated.  
       SUMMARY OF THE INVENTION  
       [0005]     The present invention is directed to a methodology and subsystem architecture for detecting the occurrence of a ground fault in a multiple, span-powered telecommunication network and then identifying which particular span segment or twisted pair telephone line is ground faulted. For this purpose, the ground fault detection circuit may be installed within a respective Digital Subscriber Line—Central Office Terminal (DSL-C), so that a ground fault may be detected when power is delivered by the DSL-C to a respective downstream functional Remote Terminal (RT).  
         [0006]     By ‘ground fault’ is meant that one or both conductors of a span-powered twisted pair are connected to earth by a low or zero ohm impedance, which is capable of causing the DSL-C to supply electrical current in excess of normal load current. If this should happen without detecting and isolating the faulted twisted pair, the span power bus voltage would be reduced to a level such that the other RT units would not operate properly and cause data errors on the digital subscriber line. As will be detailed below, this problem is effectively obviated in accordance with the invention by using the ground fault detect circuit to identify and initiate disconnecting and isolating the particular faulted twisted pair. The disconnect and isolation circuitry for each individual span power bus segment is incorporated in the DSL-C units and interfaces with the ground fault detect circuit.  
         [0007]     In order to detect a ground faulted twisted pair line, there must be some way of detecting the flow of current in the earth/ground connection. Although this could be accomplished at the electrical power source simply by measuring or detecting current in the conductor that connects the electrical power source to earth, such a method does not identify which twisted pair line is ground faulted. Some method for detecting ground fault current and identifying which line is ground faulted is required. The underlying principle of operation of a ground fault current detector circuit which identifies the ground faulted twisted pair line in accordance with the present invention is illustrated in the reduced complexity schematic diagram of  FIG. 2 .  
         [0008]     As shown therein, V 1  is the electrical power source that corresponds to the span power bus  210  of a multi powered span network of  FIG. 3 , which corresponds to a span-powered HDSL2 telecommunication system in which the present invention may be employed. The system of  FIG. 3  includes an arbitrary plurality (two being shown to reduce the complexity of the drawing) of functional DSL-Cs  200 - 1 , . . . ,  200 -N. These units conduct DSL communications over, and receive their electrical power by way of, a span powered bus  210  from a common electrical power source  220 . In accordance with the invention, within each DSL-C, span power from source  220  is processed by a ground fault detection circuit  201 -i (to be described), prior to being delivered to a respective downstream functional RT  230 -i, which presents a capacitive input constant power load. The ground fault detection circuit  201 -i in a respective DSL-C unit  200 -i provides ground fault detection for the individual twisted pair.  
         [0009]     In the reduced complexity schematic of  FIG. 2 , resistors R 1 sense and R 2 sense are main parts in the ground fault detect circuit in the DSL-C, and resistor Rload corresponds to the RT  230 -i. Resistors R 1 fault and R 2 fault represent possible ground fault current paths. The resistors R 1 sense and R 2 sense are current sensing resistors such that the voltage magnitude across these resistors is directly proportional to the magnitude of the current through the resistors and is given in equations (1) and (2) as:
 
 VR 1sense= I 1 ×R 1sense  (1)
 
 VR 2sense= I 2 ×R 2sense  (2)
 
         [0010]     The magnitude of the ground fault current is determined by sensing and processing the magnitude of current in both of the current sensing resistors. The magnitude of the ground fault current Ifault is given in equation (3) by:
 
 I fault= I 1- I 2  (3)
 
         [0011]     Which particular twisted pair line is ground faulted can be identified by implementing the ground fault current detect circuit on each twisted pair line. In addition, circuitry is provided which performs the mathematical function of finding the difference between I 1  and I 2 , which is equal to Ifault. This is accomplished by finding the difference between two voltages that are directly proportional to currents I 1  and I 2 . In this case the two voltages must be ground-referenced and must be derived using only one ground-referenced bias power supply.  
         [0012]     Deriving a precision ground-referenced voltage using one bias supply (that is directly proportional to current I 1 ) is not straightforward because of the high common mode voltage present at R 1 sense. Derivation is accomplished in accordance with the present invention by a composite circuit, a first differential amplifier-based section of which produces a first output voltage Vo 1  across a resistor that is directly proportional to the current I 1  flowing in the sense resistor R 1 sense of the schematic of  FIG. 2 . As will be described this first output voltage Vo 1  has an offset voltage needed for a single bias supply design to maintain a first amplifier&#39;s output voltage at a non-zero value when the current I 1  is zero. A slope value of the transfer function for the first output voltage is chosen to yield a maximum output voltage value Vo 1  when I 1  is at a maximum value.  
         [0013]     A second differential amplifier-based section of the composite circuit produces a second output voltage V 02 , that is directly proportional to the current I 2  flowing in the sense resistor R 2  sense of the schematic of  FIG. 2 . As in the first section, an offset voltage is employed for a single bias supply design to keep the amplifier output voltage at a non-zero value when the current I 1  is zero. A slope value is chosen to yield a maximum output voltage value V 02  when the current I 2  is at a maximum value.  
         [0014]     Circuit resistor values are chosen so that the output voltages of the first and second circuit sections are equal when the currents I 1  and I 2  are equal. This is accomplished my making the slope and offset of the two output voltage transfer functions equal. When there is a mathematical difference in the two current sense circuit output voltages, then currents I 1  and I 2  are not equal, which indicates that ground fault current is flowing. A difference circuit is used to provide an output voltage Vo that is proportional to the mathematical difference in the two current sense circuit output voltages. The output of the difference circuit is the output of the ground fault detect circuit and moves either positive or negative, depending on whether the fault current is flowing in resistor R 1 fault or resistor R 2 fault. This output is coupled as an input to circuitry that is operative to isolate the faulted twisted pair telephone line in response to detection of a fault current. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]      FIG. 1  diagrammatically illustrates a typical (reduced complexity) digital transmission system;  
         [0016]      FIG. 2  is a reduced complexity schematic diagram of a span powered network showing faults across a load to ground;  
         [0017]      FIG. 3  diagrammatically illustrates the general architecture of a span-powered High bit rate Digital Subscriber Line—Second Generation (HDSL2) telecommunication system in which the present invention may be employed;  
         [0018]      FIG. 4  is a schematic diagram of a circuit that is operative to produce an output voltage across a resistor that is directly proportional to the current I 1  flowing in the sense resistor R 1 sense of the schematic of  FIG. 2 ;  
         [0019]      FIG. 5  is a schematic diagram of a circuit that will produce a voltage directly proportional to I 2  in the sense resistor R 2 sense of the schematic of  FIG. 2 ;  
         [0020]      FIG. 6  is a schematic diagram of a difference circuit that will provide an output voltage Vo proportional to the mathematical difference in the two current sense circuit output voltages of the circuits of  FIGS. 4 and 5 ; and  
         [0021]      FIG. 7  is a composite circuit diagram containing the circuit portions of  FIGS. 4, 5  and  6 . 
     
    
     DETAILED DESCRIPTION  
       [0022]     Before detailing the inventive scheme for isolating a ground fault within a multiple span powered system, wherein different electrical loads are connected by way of respective wireline segments to a common electrical power source, it should be observed that the invention resides primarily in a prescribed arrangement of conventional communication circuits and components, and control circuitry that controls the operations of such circuits and components. Consequently, in the drawings, the configuration of such circuits and components, and the manner in which they may be interfaced with various telecommunication circuits have, for the most part, been illustrated by readily understandable block diagrams, which show only those specific details that are pertinent to the present invention, so as not to obscure the disclosure with details which will be readily apparent to those skilled in the art having the benefit of the description herein. Thus, the block diagrams of the Figures are primarily intended to show the various components of the invention in convenient functional groupings, so that the present invention may be more readily understood.  
         [0023]     Attention is now directed to  FIG. 4  which is a schematic diagram of a circuit that is operative to produce an output voltage across a resistor that is directly proportional to the current I 1  flowing in the sense resistor R 1 sense, which corresponds to the sense resistor R 1 sense of the schematic of  FIG. 2 . More particularly,  FIG. 4  shows current flow path I 1  proceeding from a power source V 1 (+), which is referenced to ground, through a sense resistor R 1 sense to the load (RT). The return path from the load is through a sense resistor R 2 sense to V 1 (−). Coupled to either end of sense resistor R 1 sense are equal valued resistors R 2  and R 3  in respective legs of a current mirror circuit  100  comprised of bipolar transistors Q 2  and Q 3  and bipolar transistors Q 4  and Q 5 , as shown. A reference current for the current mirror circuit is supplied by a further current mirror circuit  110  containing transistors Q 6  and Q 7 , that have their emitters coupled to V 1 (−) via same valued resistors R 10  and R 12 . Transistor Q 7  has its collector path referenced through resistor R 11  to a supply V 2 . The collector of transistor Q 4  is coupled to V 1 (−) through resistor R 9  of like value to resistors R 10  and R 12 .  
         [0024]     The collector of current mirror transistor Q 4  and the emitter of current mirror transistor Q 6  are coupled through respective resistors R 8  and R 7  to the non-inverting (+) and inverting (−) inputs  121  and  122  of differential amplifier U 1 . Capacitors C 2  and C 3  couple opposite ends of resistor R 8  to ground, while a feedback capacitor C 1  is coupled between the output of amplifier U 1  and its inverting input. The output of amplifier U 1  is further coupled through resistor R 6  to the base of transistor Q 1 , which has its collector-emitter current flow path for a current I 3  coupled between current mirror  100  and resistor R 5  coupled to ground. A pull-up resistor R 4  is coupled to a reference voltage Vref from the emitter of transistor Q 1 . The emitter of transistor Q 1  provides an output voltage Vo 1  as follows.  
         [0025]     The current I 1  flows through resistor R 1 sense and generates a voltage V(R 1 sense) across resistor R 1 sense as set forth in equation (4):
 
 V ( R 1sense)= I 1 ×R 1sense  (4)
 
         [0026]     Summing the voltages around the loop that contains R 1 sense, resistors R 2  and R 3  and the base-emitter paths through transistors Q 2  and Q 3 , and recognizing that the two base-emitter voltages of transistors Q 2  and Q 3  mutually cancel produces equation (5) as:
 
 V ( R 1sense)+ V ( R 2)= V ( R 3)  (5)
 
         [0027]     Since transistors Q 2  and Q 3  form a current mirror, their emitter currents are equivalent and in this case are equal to I(R 2 ). The current I(R 3 ) is larger than the current I(R 2 ), because V(R 3 ) is greater than V(R 2 ). Since the emitter currents of transistors Q 2  and Q 3  are equivalent, a portion of the current I(R 3 ) must flow through the current flow path I 3  to transistor Q 1 . If current I 1  is zero, then V(R 3 ) is equal to V(R 2 ). If current I 1  is non-zero, then V(R 3 ) is the sum of V(R 1 sense) and V(R 2 ). The current I 3  creates a voltage drop in resistor R 3  that is equal to V(R 1 sense), so that V(R 3 ) will increase to equal V(R 1 sense)+V(R 2 ), such that
 
 I 3= V ( R 1sense)/ R 3  (6)
 
         [0028]     The current I 3  is directly proportional to V(R 1 sense), which is directly proportional to current I 1 . With transistor Q 1  conducting, the current I 3  flows through resistor R 5  and a DC offset is created by Vref and R 4  to create a voltage Vo 1  in accordance with the transfer function (7):
 
 Vo 1 =m×I 3 +b   (7)
 
 where
 
 m =( R 4× R 5)/( R 4 +R 5)  (8) and
 
 b=V ref×R5/( R 4+ R 5)  (9)
 
         [0029]     Substituting for the current I 3 , the overall translation of input current to output voltage Vo 1  may be defined in equation (10) as:
 
 Vo 1 =I 1 ×R 1sense/ R 3×( R 4 ×R 5)/( R 4+ R 5)+ V ref×R5/( R 4+ R 5)  (10)
 
         [0030]     This yields a voltage Vo 1  that is directly proportional to the input current I 1 . The offset voltage b is needed for a single bias supply design to maintain the amplifier output voltage at a non-zero value when current I 1  is zero. The value m in equation (11) is chosen to yield a maximum output voltage value Vo 1  when I 1  is at a maximum value.
 
 m=R 1sense/ R 3×( R 4× R 5)/( R 4+ R 5)  (11)
 
         [0031]     A circuit that will produce a voltage directly proportional to I 2  is shown in  FIG. 5 . In particular, proceeding from the right hand portion of the circuit shown in  FIG. 4 , respective resistors R 13  and R 14  are coupled between opposite ends of the sense resistor R 2 sense and the non-inverting (+) and inverting (−) inputs  131  and  132  of differential amplifier U 2 . The non-inverting (+) input  131  of amplifier U 2  is further coupled to Vref via resistor R 12  and a capacitor C 7 , while the output of amplifier U 2  is coupled through resistor R 15  and capacitor C 4  to the inverting (−) input  132  of amplifier U 2 . The output of amplifier U 2  produces the voltage V 02  that is proportional to the current I 2  through sense resistor R 2 sense.  
         [0032]     In particular the amplifier circuit of  FIG. 5  has the transfer function:
 
 Vo 2 =m×I 2 +b   (12)
        where     m=chosen constant gain term
 
 m=R 2sense×{ R 12/( R 12+ R 13)}×{( R 14+ R 15)/ R 14}  (13) and
    b=chosen minimum DC output voltage.        
 
         [0036]     This yields a voltage Vo 2  at the output of amplifier U 2  that is directly proportional to input current I 2 . The offset voltage b is needed for a single bias supply design to keep the amplifier output voltage at a non-zero value when current I 1  is zero. The value m is chosen to yield a maximum output voltage value V 02  when the current I 2  is at a maximum value.  
         [0037]     Circuit resistor values are chosen so that the output voltage of the upper and lower current sense circuits are equal when the currents I 1  and I 2  are equal. This is accomplished my making m and b of the two transfer functions equal. When there is a mathematical difference in the two current sense circuit output voltages, then currents I 1  and I 2  are not equal, which indicates that a ground fault current is flowing. A difference circuit that will provide an output voltage Vo that is proportional to the mathematical difference in the two current sense circuit output voltages is shown in  FIG. 6 .  
         [0038]     As shown therein input ports  141  and  142  are coupled to receive the voltages V 01  and V 02  produced by the circuits of  FIGS. 4 and 5 , respectively. What results is the composite schematic diagram shown in  FIG. 7 . With respect to the difference circuit of  FIG. 6 , input port  141  is coupled through resistor R 18  to the inverting (−) input  151  of differential amplifier U 3 , while input port  142  is coupled through resistor R 17  to the non-inverting (+) input  152  of differential amplifier U 3 . The non-inverting (+) input  142  of amplifier U 3  is further coupled to Vref via resistor R 16  and a capacitor C 5 , while the output of amplifier U 3  is coupled through resistor R 19  and capacitor C 6  to the inverting (−) input  151  of amplifier U 3 . The output of amplifier U 2  produces a voltage Vo that is proportional to the difference between its two input voltages V 01  and V 02  as follows.  
         [0039]     The differential amplifier circuit of  FIG. 6  has the function defined by
 
 Vo =( Vo 1 −Vo 2)×( R 19/ R 18)+ b   (14)
        where Vo 1  and V 02  are defined above, and     b=Vref        
 
         [0042]     Resistor values R 19  and R 18  are chosen based on the desired output voltage versus fault current amplitude, and b is chosen as an output DC level, to indicate no difference in input voltage, or no fault current flowing. The output of the difference circuit of FIG.  6  is the output of the ground fault detect circuit and moves either positive or negative, depending on whether the fault current is flowing in resistor R 1 fault or resistor R 2 fault. This output is coupled as an input to circuitry that is operative to isolate the faulted twisted pair telephone line in response to detection of a fault current.  
         [0043]     While we have shown and described an embodiment in accordance with the present invention, it is to be understood that the same is not limited thereto but is susceptible to numerous changes and modifications as known to a person skilled in the art, and we therefore do not wish to be limited to the details shown and described herein, but intend to cover all such changes and modifications as are obvious to one of ordinary skill in the art.