Abstract:
Methods for sensing, memory devices, and memory systems are disclosed. One such method for sensing includes charging bit lines of an all bit line architecture to a precharge voltage, selecting a word line, and performing a sense operation on the bit lines. After the sense operation on the memory cells of the first selected word line is complete, the precharge voltage is maintained on the bit lines while a second word line is selected.

Description:
RELATED APPLICATION 
       [0001]    This is a continuation of U.S. application Ser. No. 12/561,692, titled “SENSING FOR ALL BIT LINE ARCHITECTURE IN A MEMORY DEVICE” filed Sep. 17, 2009, (allowed) which is commonly assigned and incorporated herein by reference. 
     
    
     TECHNICAL FIELD 
       [0002]    The present invention relates generally to memory and in a particular embodiment the present invention relates to non-volatile memory. 
       BACKGROUND 
       [0003]    Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems. 
         [0004]    Non-volatile memory cells are read during a sense operation using sense circuitry (e.g., sense amplifiers). Bit lines are coupled to the sense circuitry that detects the state of a target memory cell by sensing voltage or current on a particular bit line. A typical sense operation includes precharging, to a particular voltage level (e.g., 0.5V), the bit lines coupled to memory cells selected to be read. 
         [0005]    During a typical sense operation of a memory block, alternate bit lines coupled to NAND strings of memory cells are read. In other words, an initial sense operation might read the odd bit lines of memory cells while a subsequent sense operation would read the even bit lines of memory cells. Using this alternate bit line procedure, no two adjacent bit lines are read simultaneously. The bit lines that are not being read are typically grounded to provide shielding between bit lines that are being read. This reduces the bit line-to-bit line coupling that can occur as a result of the voltage level on the bit lines changing between sensing. 
         [0006]    Since only alternate bit lines of memory cells are read during a sense operation, reading a memory block can take twice as long as reading all of the bit lines simultaneously. One way that has been proposed to decrease the read time of a non-volatile memory device is to read all of the bit lines substantially simultaneously (i.e., an all bit line read (ABL)) using a multi-step sense operation that can reduce the bit line-to-bit line coupling. This is accomplished by measuring the cell current on the bit line by estimating the residual charge remaining on a capacitor coupled to the bit line after a sampling time has elapsed. 
         [0007]      FIG. 1  illustrates a timing diagram of a typical prior art multi-step sense operation. This timing diagram shows three different  101 - 103  sense operations. 
         [0008]    The lower waveform  105  shows the sensing trigger signal that signals the beginning of each sense cycle. Each time the sense trigger signal goes from low to high, a new sense operation is performed. 
         [0009]    The middle waveform  107  shows the residual charge remaining TDC on the capacitor coupled to the bit line. It can be seen that as one sense operation ends, the capacitor discharges so that TDC starts to go to 0V until the next sense trigger signal causes the capacitor to recharge. 
         [0010]    The top waveform  109  shows the bit line voltage for a bit line being read. This waveform also shows the bit line-to-bit line coupling  110 ,  111  that occurs due to a change in voltage on adjacent bit lines. Before this bit line can be sensed by the sense amplifier, the bit line voltage has to recover to the bit line bias level. Waiting for this recovery period results in a read delay during which the sense amplifiers cannot perform a sense operation. 
         [0011]    For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art to decrease the read time of a memory device. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]      FIG. 1  shows a timing diagram of a typical prior art non-volatile memory sense operation. 
           [0013]      FIG. 2  shows a schematic diagram of one embodiment of series NAND strings of memory cells. 
           [0014]      FIG. 3  shows a schematic diagram of one embodiment of an all bit line sense circuit. 
           [0015]      FIG. 4  shows a timing diagram of one embodiment of sense circuit signals in accordance with the circuit of  FIG. 3  and the method of  FIG. 5 . 
           [0016]      FIG. 5  shows a flowchart of one embodiment of a method for sensing an all bit line architecture. 
           [0017]      FIG. 6  shows a block diagram of one embodiment of a memory system in accordance with the memory device of  FIG. 1 . 
       
    
    
     DETAILED DESCRIPTION 
       [0018]    In the following detailed description of the invention, reference is made to the accompanying drawings that form a part hereof and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and equivalents thereof. 
         [0019]      FIG. 2  illustrates a schematic diagram of a portion of a NAND architecture memory array  201  comprising series strings of non-volatile memory cells. While  FIG. 2  and the subsequent discussions refer to a NAND memory device, the present embodiments are not limited to such an architecture but can be used in other memory device architectures as well (e.g., NOR, AND). 
         [0020]    The memory array  201  is comprised of an array of non-volatile memory cells (e.g., floating gate) arranged in columns such as series strings  204 ,  205 . Each of the cells are coupled drain to source in each series string  204 ,  205 . An access line (e.g. word line) WL 0 -WL 31  that spans across multiple series strings  204 ,  205  is connected to the control gates of each memory cell in a row in order to bias the control gates of the memory cells in the row. The data lines (e.g., bit lines) BL 1 , BL 2  are eventually connected to sense circuits that detect the state of each cell by sensing voltage or current on a particular bit line. The sense circuits are shown and described subsequently with reference to  FIG. 3 . 
         [0021]    Each series string  204 ,  205  of memory cells is coupled to a source line  206  by a source select gate  216 ,  217  and to an individual bit line BL 1 , BL 2  by a drain select gate  212 ,  213 . The source select gates  216 ,  217  are controlled by a source select gate control line SG(S)  218  coupled to their control gates. The drain select gates  212 ,  213  are controlled by a drain select gate control line SG(D)  214 . 
         [0022]    Each memory cell can be programmed as a single level cell (SLC) or multiple level cell (MLC). Each cell&#39;s threshold voltage (V t ) is indicative of the data that is stored in the cell. For example, in an SLC, a V t  of 0.5V might indicate a programmed cell while a V t  of −0.5V might indicate an erased cell. The MLC can have multiple V t  voltage ranges that each indicate a different state. 
         [0023]      FIG. 3  illustrates a schematic diagram of one embodiment of an all bit line sense circuit  390 . In one embodiment, this circuit  390  is replicated for each bit line of a memory block or other grouping of memory cells. The sense circuit  390  is generally comprised of a sense amplifier  305 , a latch  301 , and a precharge circuit  300  comprising precharge transistors  303 ,  304 . Additional circuitry is included to enable and control these functions. The sense amplifier  305  is coupled to its respective bit line through a transistor  310  controlled by a bit line enable signal BLS. 
         [0024]    In operation, the sense amplifier  305  is initialized by a reset signal RST that pulls NODE A  321  to ground. A voltage clamp circuit, such as transistor  311 , is enabled with a bit line clamp signal BLCLAMP that controls the bit line voltage clamp transistor  311 . An isolation circuit, such as transistor  312 , is controlled by an enable signal EN 1 . After the reset, the isolation transistor  312  is enabled to connect the TDC node and the capacitance  313  to the precharge circuit  300 . 
         [0025]    The precharge circuit  300  precharges the bit line BL through the internal sense node  330  for a particular period of time. This brings the bit line to an optimal voltage, as described subsequently, for sensing the conduction of the selected memory cell. 
         [0026]    Once the bit line is precharged, a sensing phase begins where the sense node  330  is sensed by a discriminator circuit that includes two transistors  350 ,  351 . The sensing identifies those memory cells with conduction currents that are higher than a particular level. The two transistors  350 ,  351  in series serve as a pull-up for NODE A  321 . One transistor  350  is enabled by the SENSING signal going low and the second transistor  351  is enabled by the sense node  330  going low. High current memory cells cause the signal TDC to be close to 0V or at least unable for the bit line to be precharged sufficiently high to turn off the transistor  351 . For example, if a weak pull up is limited to a current of 500 nA, it will fail to pull up a memory cell with a conduction current of 700 nA. 
         [0027]    When the sense amplifier  305  senses a current on the bit line, the latch  301  changes state to a high state so that NODE A  321  goes high and NODE B  322  goes low. Since NODE B is coupled to transistor  360  of the precharge circuit  300 , a low on NODE B turns on the transistor  360  and current can then pass through this transistor to recharge the TDC node  330 . The bit line is thus maintained at the precharge voltage by the voltage clamp circuit  311  used in a cascade connection. When NODE A  321  is high and the isolation enable signal EN 1  is low, the isolation circuit  312  is disabled and the sense node  330  is blocked from the precharge circuit  300 . 
         [0028]    After the sensing operation, the prior art bit line is pulled to ground and the sensing operation would have to wait for the adjacent bit lines, that have been coupled down, to recover back to their precharge levels before starting another sense operation on the next row of memory cells. However, the bit lines of the present embodiments are maintained at their precharge levels between each of the sense operations such as in order to reduce the bit line-to-bit line coupling. This is accomplished, as described previously, by the change of state of the latch  301  turning on transistor  360  of the precharge circuit  300  such that the TDC node is pulled up to the supply voltage. 
         [0029]    The circuit of  FIG. 3  is for purposes of illustration only. Alternate embodiments can maintain the precharge voltage on bit lines between sense operations using different circuit elements that operate in a different manner. 
         [0030]      FIG. 4  illustrates a timing diagram of one embodiment of the above-described sense circuit signals in accordance with the circuit of  FIG. 3  and the sense method of  FIG. 5 . The lower waveform  406  shows that the SENSING signal goes low at the start of every sense operation. The middle waveform  407  shows that the TDC node is kept from discharging during each sense operation as is shown in the prior art TDC waveform. The upper waveform  408  shows that the bit line voltage is thus kept charged to the bit line bias level even during the transitions  401 ,  402  between sense operations. The same transition areas  110 ,  111  of  FIG. 1  of the prior art showed that these areas required a recovery period prior to a subsequent sense operation. The bit line waveform of  FIG. 4  illustrates that this recovery period is not necessary for the present embodiments. 
         [0031]      FIG. 5  illustrates a flowchart of one embodiment of a method for sensing an all bit line architecture. A sense operation is performed substantially simultaneously on all of the bit lines of a memory block or other grouping of bit lines as each word line is selected. Thus, when a particular word line is selected, a selected memory cell coupled to both the selected word line and a bit line is selected to be sensed. 
         [0032]    After a particular word line is selected  500 , the method begins with the precharging of the bit lines to be sensed. The bit lines are precharged to a particular precharge voltage  501 . The precharge voltage varies with the conduction current of the selected memory cell. For example, a 400-500 nA conduction current might use a precharge voltage of 0-0.1V. A conduction current below 400 nA might use a precharge voltage of 0.5V that is set by the bit line clamp transistor  311 . Thus, in one embodiment, a lower conduction current uses a higher precharge voltage. 
         [0033]    A sense operation is then performed  503  as described previously. In one embodiment, a current is sensed. An alternate embodiment can sense a voltage level. If current was sensed  505  on the selected bit line, the stored data is then determined  507 . The value of the stored data can be determined by the current or voltage level as compared to a reference current or voltage in order to determine the threshold voltage of the selected memory cell. In an SLC device, presence of a current on the bit line means the selected memory cell is programmed. In an MLC device, the memory cell can be programmed to one of a plurality of different states, each state being represented by a different range of threshold voltages. 
         [0034]    When the data from the sensed bit line has been determined  507  or current was not sensed  505  during the sense operation, the bit lines are kept charged between sense operations  509  on each word line. It is determined whether all of the memory cells of the selected word line, or other grouping of memory cells, has been sensed  510 . If all of the grouping of memory cells has been sensed  510 , the sense operation is complete  513  for that particular word line or memory page. 
         [0035]    If the last memory cell of the word line or other grouping of memory cells has not been sensed  510 , the method changes the read voltage to the next MLC voltage to be sensed  511 . In one embodiment, the read voltage is increased on the word line. The sense operation of  FIG. 5  is repeated for other selected word lines of a memory block or other grouping of memory cells as each word line is selected in turn. 
         [0036]      FIG. 6  illustrates a functional block diagram of a memory device  600 . The memory device  600  is coupled to an external controller  610 . The controller  610  may be a microprocessor or some other type of controlling circuitry. The memory device  600  and the controller  610  form part of a memory system  620 . The memory device  600  has been simplified to focus on features of the memory that are helpful in understanding the present invention. 
         [0037]    The memory device  600  includes an array  201  of non-volatile memory cells, such as the one illustrated previously in  FIG. 2 . The memory array  201  is arranged in banks of word line rows and bit line columns. In one embodiment, the columns of the memory array  201  are comprised of series strings of memory cells as illustrated in  FIG. 2 . As is well known in the art, the connections of the cells to the bit lines determines whether the array is a NAND architecture, an AND architecture, or a NOR architecture. 
         [0038]    Address buffer circuitry  640  is provided to latch address signals provided through the I/O circuitry  660 . Address signals are received and decoded by a row decoder  644  and a column decoder  646  to access the memory array  201 . It will be appreciated by those skilled in the art, with the benefit of the present description, that the number of address input connections depends on the density and architecture of the memory array  201 . That is, the number of addresses increases with both increased memory cell counts and increased bank and block counts. 
         [0039]    The memory device  600  reads data in the memory array  201  by sensing voltage or current changes in the memory array columns using sense circuitry  390  as illustrated in  FIG. 3  and described previously. The sense circuitry  390 , in one embodiment, is coupled to read and latch a row of data from the memory array  201 . Data input and output buffer circuitry  660  is included for bidirectional data communication as well as address communication over a plurality of data connections  662  with the controller  610 . Write circuitry  655  is provided to write data to the memory array. 
         [0040]    Memory control circuitry  670  decodes signals provided on control connections  672  from the external controller  610 . These signals are used to control the operations on the memory array  201 , including data read, data write (program), and erase operations. The memory control circuitry  670  may be a state machine, a sequencer, or some other type of control circuitry to generate the memory control signals. In one embodiment, the memory control circuitry  670  is configured to execute the embodiments of the sense method of the present disclosure. 
         [0041]    The flash memory device illustrated in  FIG. 6  has been simplified to facilitate a basic understanding of the features of the memory. A more detailed understanding of internal circuitry and functions of flash memories are known to those skilled in the art. 
       CONCLUSION 
       [0042]    The method and sense circuit of the present embodiments may be used to provide faster sensing in an all bit line architecture. Since the all bit line architecture does not ground alternate bit lines during the sense operation, the charging and subsequent discharging of the bit lines after a sense operation can couple down adjacent bit lines, causing a recovery period to occur prior to a subsequent sense operation. By maintaining the bit lines at the precharge voltage between each of the sense operations for a particular bit line, the adjacent bit lines are not coupled down and no recovery period is necessary.