Abstract:
A semiconductor device comprises a first bit line, a second bit line, a memory cell electrically coupled to the first bit line and the second bit line, a first amplification circuit configured to amplify a potential of the first bit line and a second amplification circuit configured to amplify a potential of the second bit line.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
         [0001]    This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-241478, filed Aug. 9, 2000, the entire contents of which are incorporated herein by reference.  
         BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates to a semiconductor memory device.  
           [0004]    2. Description of the Related Art  
           [0005]    [0005]FIG. 15 is a circuit diagram showing a conventional semiconductor memory device.  
           [0006]    As shown in FIG. 15, in the conventional memory device, a word line WL (WL 0  or WL 1 ) and two bit lines BL (BL 0  and BL 1 ) are independently connected to a memory cell (memory element).  
           [0007]    A data read circuit is connected between two bit lines BL 0  and BL 1 . A sense amplification circuit (sense AMP. circuit) of a differential amplification type for differential-amplifying potential difference between two bit lines BL 0  and BL 1  is used in the Data Read Circuit.  
           [0008]    An example of the memory cell is a SRAM cell. The SRAM cell includes, for example, two inverters that are connected to each other in a cross-coupled manner, that is, a latch circuit and two N-channel type MOSFETs that connect the latch circuit to the bit lines BL 0  and BL 1  in accordance with a potential of the word line WL. Thus, when the word line is activated, the bit lines BL 0  and BL 1  are electrically connected to the memory cell and a charge can be moved mutually in such a manner that from the bit lines BL 0  and BL 1  to the memory cell, or from the memory cell to the bit lines BL 0  and BL 1 . A drain of P-channel type MOSFETs whose gate receives a pre-charge signal and whose source receives a fixed electric potential is connected to the bit lines BL 0  and BL 1 . The P-channel type MOSFETs constitute a pre-charge circuit and used for pre-charge operation to be described later.  
           [0009]    The sense AMP, circuit includes the latch circuit. The N-channel type MOSFET that is connected to earthed electric potential in accordance with a sense AMP. enable signal (S/A enable signal) and a pair of the P-channel type MOSFETs that are connected to the bit lines BL 0  and BL 1  in accordance with the S/A enable signal are connected to the latch circuit. Accordingly, when the S/A enable signal is activated, the latch circuit is connected to the earthed electric potential and disconnected from the bit lines BL 0  and BL 1 . At the timing when the S/A enable signal is activated, a slight amount of potential difference at the relevant time between the bit lines BL 0  and BL 1  is detected and the latch circuit amplifies the potential difference to a potential difference of CMOS level.  
           [0010]    Next, operation of the conventional memory device will be described.  
           [0011]    [0011]FIG. 16 is an operation waveform chart showing operation of the conventional memory device.  
           [0012]    As shown in FIG. 16, in general, each electric potential of the bit lines BL 0  and BL 1  is set at a predetermined value (In FIG. 16, “HIGH” level is adopted.), before starting read/writing operation.  
           [0013]    In the read operation, when the word line WL is activated, the memory cell is connected to the bit lines BL 0  and BL 1 . Electric potential of one bit line declines gradually in accordance with data stored in the latch circuit and a potential of the other bit line maintains “HIGH” level. The potential difference between the bit lines BL 0  and BL 1  is amplified by the sense AMP. circuit and output. After that, the word line WL is deactivated and the memory cell is disconnected from the bit lines BL 0  and BL 1 . When a pre-charge signal comes to “LOW” level, each electric potential of bit lines BL 0  and BL 1  is changed to “HIGH” level by the pre-charge circuit. This process is called pre-charge.  
           [0014]    In the writing operation, the word line WL is activated and the memory cell is connected to the bit lines BL 0  and BL 1 . Furthermore, when a write enable signal is activated, the potential of one bit line is changed to “Low” level by a data write circuit and the potential of the other bit line maintains “HIGH” level. Accordingly, data is written in the memory cell. After that, the word line WL is deactivated and each potential of the bit lines BL 0  and BL 1  changes to “HIGH” level (pre-charge) in the same manner as the read operation.  
           [0015]    As described above, the pre-charge is necessary after the read/write operation and plenty of time is spend on the pre-charge, in fact. A great deal of time required for the pre-charge is particularly necessary when the pre-charge is carried out after writing data with the bit line driven to “LOW” level and the read operation is carried out immediately after the pre-charge.  
           [0016]    In this case, since the potential of the bit line drops to “low” level first and then changes to “HIGH” level, the voltage varies largely and accordingly plenty of transition time is required.  
           [0017]    Additionally, in the read operation, the sense AMP. circuit detects a very slight amount of potential difference between the bit lines BL 0  and BL 1 . Therefore, when the read operation is started in an imperfect pre-charge state, possibility of causing malfunction is increased. For this reason, the read operation must be waited until the electric potential of the bit lines completely comes to “HIGH” level.  
           [0018]    A cycle of a clock cannot be shortened less than time for a series of the above operation, that is, time required from the write operation to completion the pre-charge, or from the read operation to completion of the pre-charge. Thus, operation frequency of the conventional memory device is rate-limited.  
         BRIEF SUMMARY OF THE INVENTION  
         [0019]    A semiconductor device according to a first embodiment of the present invention comprises: a first bit line; a second bit line; a memory cell electrically coupled to the first bit line and the second bit line; a first amplification circuit configured to amplify a potential of the first bit line; and a second amplification circuit configured to amplify a potential of the second bit line, the second amplification circuit being inactive when the first amplification circuit is active and being active when the first amplification circuit is inactive, in read operation.  
           [0020]    A semiconductor device according to a second embodiment of the present invention comprises: a first bit line; a second bit line; a memory cell electrically coupled to the first bit line and the second bit line; a amplification circuit configured to amplify a potential of the first bit line and a potential of the second bit line; and a multiplexer which selects the first bit line or the second bit line and electrically couples a selected bit line to the amplification circuit.  
           [0021]    A semiconductor device according to a third embodiment of the present invention comprises: a first bit line; a second bit line; a memory cell electrically coupled to the first bit line and the second bit line; a first amplification circuit configured to amplify a potential of the first bit line; a second amplification circuit configured to amplify a potential of the second bit line; and a pre-charge circuit configured to pre-charge the first and second bit lines, the pre-charge circuit pre-charging the second bit line when the first amplification circuit is active, and pre-charging the first bit line when the second amplification circuit is active. 
       
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING  
       [0022]    The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently embodiments of the invention, and together with the general description given above and the detailed description of the embodiments given below, serve to explain the principles of the invention.  
         [0023]    [0023]FIG. 1 is a circuit diagram showing a semiconductor memory device according to a first embodiment of the present invention;  
         [0024]    [0024]FIG. 2 is an operation waveform chart showing an example of read operation in the semiconductor memory device according to the first embodiment of the present invention;  
         [0025]    [0025]FIG. 3 is a block diagram showing an example of a S/A, pre-charge control circuit included in the semiconductor memory device according to the first embodiment of the present invention;  
         [0026]    [0026]FIG. 4 is a circuit diagram showing a semiconductor memory device according to a second embodiment of the present invention;  
         [0027]    [0027]FIG. 5 is an operation waveform chart showing an example of read/writing operation in the semiconductor memory device according to the second embodiment of the present invention;  
         [0028]    [0028]FIG. 6 is a block diagram showing an example of a S/A, pre-charge control circuit included in the semiconductor memory device according to the second embodiment of the present invention;  
         [0029]    [0029]FIG. 7 is a circuit diagram showing the semiconductor memory device according to a third embodiment of the present invention;  
         [0030]    [0030]FIG. 8 is an operation waveform chart showing an example of read/writing operation in the semiconductor memory device according to the third embodiment of the present invention;  
         [0031]    [0031]FIG. 9 is an operation waveform chart showing an example of read operation in the semiconductor memory device according to the third embodiment of the present invention;  
         [0032]    [0032]FIG. 10 is an operation waveform chart showing an example of writing operation in the semiconductor memory device according to the third embodiment of the present invention;  
         [0033]    [0033]FIG. 11 is a block diagram showing an example of a S/A, pre-charge control circuit included in the semiconductor memory device according to the third embodiment of the present invention;  
         [0034]    [0034]FIG. 12 is a circuit diagram showing the semiconductor memory device according to a fourth embodiment of the present invention;  
         [0035]    [0035]FIG. 13 is an operation waveform chart showing an example of read operation in the semiconductor memory device according to the fourth embodiment of the present invention;  
         [0036]    [0036]FIG. 14 is a block diagram showing an example of a S/A, pre-charge control circuit included in the semiconductor memory device according to the fourth embodiment of the present invention;  
         [0037]    [0037]FIG. 15 is a circuit diagram showing a conventional memory device; and  
         [0038]    [0038]FIG. 16 is an operation waveform chart showing writing/read operation of the conventional memory device.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0039]    Hereinafter, embodiments of the present invention will be described referring to the accompanying drawings. For the description, the same constituting elements are indicated by the same reference symbols for all of the drawings.  
       First Embodiment  
       [0040]    [0040]FIG. 1 is a circuit diagram showing a semiconductor memory device according to a first embodiment of the present invention.  
         [0041]    As shown in FIG. 1, a memory cell MC 1  is connected to bit lines BL 0  and BL 1  and a memory cell MC 2  is connected to the bit lines BL 0  and BL 1 . An example of each of the memory cells MC 1  and MC 2  is a SRAM cell, however, the other memory cells can be used. The bit lines BL 0  and BL 1  are connected to a pre-charge circuit  1  and a data read circuit  2 .  
         [0042]    A pre-charge circuit  1  includes P-channel type MOSFETs (will be abbreviated to PMOS, hereinafter)  3 - 0  and  3 - 1 . The PMOS  3 - 0  supplies a pre-charge potential VPRE to the bit line BL 0  in response to a pre-charge signal PRE 0  and the PMOS  3 - 1  supplies the pre-charge potential VPRE to the bit line BL 1  in response to a pre-charge signal PRE 1 .  
         [0043]    The data read circuit  2  includes sense AMP. circuits S/A 0  and S/A 1 , and a multiplexer  4 . The sense AMP. circuit S/A 0  amplifies a potential of the bit line BL 0  and the sense AMP. circuit S/A 1  amplifies a potential of the bit line BL 1 . The circuits S/A 0  and S/A 1  respond to S/A enable signals S/AENB 0  and S/AENB 1 , respectively and are alternately activated.  
         [0044]    The multiplexer  4  responds to a multiplex control signal MUX and selects output of the circuits S/A 0  and S/A 1  alternately so as to output the selected output as read data OUTPUT.  
         [0045]    An example of configuration of the circuits S/A 0  and S/A 1  will be described below.  
         [0046]    An input/output node NO of the circuit S/A 0  is connected to the bit line BL 0  through a PMOS  5 - 0 . An input/output node N 1  of the circuit S/A 1  is connected to the bit line BL 1  through a PMOS  5 - 1 . The circuits S/A 0  and S/A 1  are connected to, for example, a ground potential Vs through a NMOS  6 - 0  and a NMOS  6 - 1 , respectively.  
         [0047]    The PMOS  5 - 0  responds to the signal S/AENB 0 . When the circuit S/A 0  is activated, the PMOS  5 - 0  disconnects the circuit S/A 0  from the bit line BL 0 . The NMOS  6 - 0  responds to the signal S/AENB 0 . When the circuit S/A 0  is activated, the NMOS  6 - 0  supplies the ground potential Vs to the circuit S/A 0 . The PMOS  5 - 1  responds to the signal S/AENB 1 . When the circuit S/A 1  is activated, the PMOS  5 - 1  disconnects the circuit S/A 1  from the bit line BL 1 . The NMOS  6 - 1  responds to the signal S/AENB 1 . When the circuit S/A 1  is activated, the NMOS  6 - 1  supplies the ground potential Vs to the circuit S/A 1 .  
         [0048]    The circuits S/A 0  and S/A 1  of the first embodiment are single end type sense amplifiers. The single end type sense amplifier compares the potential of the bit line (BL 0 , BL 1 ) with a reference potential (REF 0 , REF 1 ) and amplifies a potential difference the bit line and the reference potential, thereby amplifying the potential of the bit line.  
         [0049]    The input/output node NO of the circuit S/A 0  is connected to a first input of the multiplexer  4  through a non-inverting buffer circuit  7 - 0 . The input/output node N 1  of the circuit S/A 1  is connected to a second input of the multiplexer  4  through an inverting buffer circuit  7 - 1 .  
         [0050]    Next, read operation of the semiconductor memory device will be described.  
         [0051]    [0051]FIG. 2 is an operation waveform chart showing an example of read operation in the semiconductor memory device according to the first embodiment.  
         [0052]    In the example of the operation shown in FIG. 2, it is assumed that when data written in the memory cell is “0”, the potential of the bit line BL 0  is at “LOW” level and the potential of the bit line BL 1  is at “HIGH” level, and when the data is “1”, the potential of the bit line BL 0  is at “HIGH” level and the potential of the bit line BL 1  is at “LOW” level.  
         [0053]    As shown in FIG. 2, in the first cycle T 1 , the bit line BL 0  is read-accessed. At this time, the other bit line BL 1  is pre-charged. While the bit line BL 0  is read-accessed, the circuit S/A 0  is activated and data of the bit line BL 0  detected and amplified by the circuit S/A 0  is output from the multiplexer  4  as read data OUTPUT.  
         [0054]    In the next cycle T 2 , data is read by using the bit line BL 1  that has been pre-charged in the first cycle T 1 . Together with this operation, the bit line BL 0  that has been read in the first cycle T 1  is pre-charged. At this time, the circuit S/A 1  is activated and the data read on the bit line BL 1  is detected and amplified by the circuit S/A 1 . And then the data is output from the multiplexer  4  as read data OUTPUT.  
         [0055]    In a following third cycle T 3 , data is read by using the bit line BL 0  that has been pre-charged in the second cycle T 2 . Together with this operation, the bit line BL 1  that has been read in the second cycle T 2  is pre-charged. At this time, the circuit S/A 0  is activated and the data read on the bit line BL 0  is detected and amplified by the circuit S/A 0 . And then the data is output from the multiplexer  4  as read data OUTPUT.  
         [0056]    As described above, in the first embodiment, data read operation is carried out by activating the circuits S/A 0  and S/A 1  alternately at every cycle of a clock signal CLOCK.  
         [0057]    [0057]FIG. 3 is a block diagram showing an example of a S/A, pre-charge control circuit included in the semiconductor memory device according to the first embodiment.  
         [0058]    As shown in FIG. 3, the clock signal CLOCK is input to a frequency divider  11 . The frequency divider  11  of the first embodiment divides a cycle of the clock signal CLOCK into two cycles. A divided clock signal CLOCK&#39; is input to a first input ( 0 ) of a multiplexer  12 - 0  and a negative-phase clock signal /CLOCK&#39; is input to a first input ( 0 ) of a multiplexer  12 - 1 . To each second input ( 1 ) of the multiplexers  12 - 0  and  12 - 1 , electric potential having “HIGH” level is input. Each of the multiplexers  12 - 0  and  12 - 1  selects the first input ( 0 ) when a write enable signal WE is at “0” level (for example, “LOW” level). On the contrary, when the write enable signal WE is at “1” level (for example, “HIGH” level), multiplexers  12 - 0  and  12 - 1  select the second input ( 1 ) and output. Output from the multiplexers  12 - 0  and  12 - 1  are pre-charge signals PRE 0  and PRE 1 , respectively.  
         [0059]    A divided clock signal CLOCK&#39; is input to a first input ( 0 ) of a multiplexer  14 - 0  through a circuit  13 - 0  and a negative-phase clock signal /CLOCK&#39; is input to a first input ( 0 ) of a multiplexer  14 - 1  through a circuit  13 - 1 . The circuits  13 - 0  and  13 - 1  provide timing and a period of time to activate the circuits S/A 0  and S/A 1 , respectively. To the second input ( 1 ) of the multiplexers  14 - 0  and  14 - 1 , electric potential having “LOW” level is input. Each of the multiplexers  14 - 0  and  14 - 1  selects the first input ( 0 ) when the write enable signal WE is at “0” level (for example, “LOW” level). On the contrary, when the write enable signal WE is at “1” level (for example, “HIGH” level), each of the multiplexers  14 - 0  and  14 - 1  selects the second input ( 1 ) and outputs. Outputs from each of the multiplexers  14 - 0  and  14 - 1  are sense enable signals S/AENB 0  and S/AENB 1 , respectively.  
         [0060]    According to the first embodiment as described above, during a cycle of the clock signal CLOCK, data is read by using one bit line that has already been pre-charged and the other bit line is pre-charged. Therefore, it is not needed to wait for completion of pre-charging one bit line but the data can be read by using the other bit line in the next cycle. Accordingly, it is not needed to carry out both data read and pre-charge during a cycle of the clock signal CLOCK.  
         [0061]    Thus, as compared with a conventional way in that both data read and pre-charge are to be carried out during a cycle of the clock signal CLOCK, a cycle of the clock signal CLOCK can be curtailed.  
       Second Embodiment  
       [0062]    [0062]FIG. 4 is a circuit diagram showing a semiconductor memory device according to a second embodiment of the invention.  
         [0063]    As shown in FIG. 4, what the second embodiment differs from the first embodiment is to have a control circuit  21  that determines circuits S/A to be activated and the pre-charge circuit  1  to be activated in accordance with writing data INPUT.  
         [0064]    Next, read/writing operation of the device will be described.  
         [0065]    [0065]FIG. 5 is an operation waveform chart showing an example of read/writing operation in the memory device according to the second embodiment.  
         [0066]    As shown in FIG. 5, in the read operation, since the circuits S/A to be activated is changed at every cycle of the clock signal CLOCK in the same manner as one of the first embodiment, it is not needed to wait for completion of pre-charging one bit line but the operation can be started by using the other bit line.  
         [0067]    When the write operation is carried out, the circuits S/A to be activated in a following cycle is selected in accordance with write data. For example, when write data is “0”, electric potential of the bit line BL 0  is assumed to change to “LOW” level.  
         [0068]    When data “0” is written, the bit line BL 0  drops to “LOW” level, whereas the bit line BL 1  maintains “HIGH” level. Therefore, when operation to be carried out in a following cycle is read operation, the S/A 1  connected to the bit line BL 1  is controlled to be active.  
         [0069]    On the contrary, when data “1” is written, the bit line BL 1  drops to “LOW” level, whereas the bit line BL 0  maintains “HIGH” level. Therefore, when operation to be carried out in a following cycle is read operation, the circuit S/A 0  connected to the bit line BL 0  is controlled to be active.  
         [0070]    [0070]FIG. 6 is a block diagram showing an example of a S/A, pre-charge control circuit included in the semiconductor memory device according to the second embodiment.  
         [0071]    What the control circuit  21  shown in FIG. 6 differs from the control circuit shown in FIG. 3 is to find exclusive OR of the divided clock signal CLOCK&#39; and write data INPUT so as to control multiplexers  22 - 0 ,  22 - 1 ,  24 - 0  and  24 - 1  by using the exclusive OR. When output from the latch is at “0” level, each of the multiplexers  22 - 0 ,  22 - 1 ,  24 - 0  and  24 - 1  selects the first input ( 0 ) and when the output is at “1” level, each of the multiplexers selects the second input ( 1 ). Accordingly, the signals PRE 0  and S/AENB 0  can be switched to the signals PRE 1  and S/AENB 1  respectively, or the signals PRE 1  and S/AENB 1  can be switched to the signals PRE 0  and S/AENB 0  respectively, in accordance with the writing data INPUT. More specific explanation is as follows.  
         [0072]    Basic operation of the present embodiment is assumed that when the divided clock signal CLOCK&#39; is at “LOW” level, the bit line BL 0  is pre-charged.  
         [0073]    According to the basic operation, when data read operation is carried out in a following cycle, data is read by using the bit line BL 0 .  
         [0074]    Here, when the divided clock signal CLOCK&#39; is at “LOW” level, it is assumed that the written data is “0” (at “low” level). Then, the bit line BL 0  comes to “LOW” level and the bit line BL 1  comes to “HIGH” level. That is, on the contrary to the above basic operation, the bit line BL 1  is to be pre-charged.  
         [0075]    In this state, when data is read in a following cycle, data read operation by using the bit line BL 1  can be carried out rapidly because it is not necessary to wait for completion of pre-charge of the bit line BL 0 .  
         [0076]    In order to realize this operation, it is detected whether or not exclusive OR of an inverted signal/CLOCK&#39; to the divided clock signal CLOCK&#39; and write data INPUT, that is, whether or not logical level of the inverted signal/CLOCK&#39; and logical level of the writing data INPUT are consistent with each other.  
         [0077]    In this embodiment, when the two levels are consistent with each other, the bit line is pre-charged as in the same manner as the basic operation. Thus, switching the circuit S/A to be activated is not carried out.  
         [0078]    On the contrary, when the two levels are not consistent with each other, the opposite bit line to one in the basic operation is pre-charged. Therefore, the circuit S/A to be activated is to be switched.  
         [0079]    More specifically, in the inconsistent case, the signals PRE 0  and S/AENB 0  are switched to the signals PRE 1  and S/AENB 1 , respectively, or the signals PRE 1  and S/AENB 1  are switched to the signals PRE 0  and S/AENB 0 , respectively. Accordingly, in a following cycle, it is possible to read data by using the bit line which has been changed to “HIGH” level in accordance with the writing data INPUT.  
         [0080]    According to the second embodiment described above, it is possible to obtain the similar effect as the first embodiment.  
         [0081]    Furthermore, in data read operation following to the data writing, the S/A to be activated is switched in accordance with the writing data so that the data is read by using the bit line which was changed to “HIGH” level in the data writing. As a consequence, it is not necessary to wait for completion of pre-charging the bit line which changed to “LOW” level in the data writing but data can be read in a following cycle.  
         [0082]    Note that when data is written again after data writing, it is obvious that pre-charge is not necessary. Thus, data can be written in a following cycle.  
       Third Embodiment  
       [0083]    [0083]FIG. 7 is a circuit diagram showing a memory device according to a third embodiment of the present invention.  
         [0084]    The third embodiment is a modification of the second embodiment. In the third embodiment, the memory device behaves as a pseudo two-ports RAM capable of carrying out a plurality of read/writing operation in a cycle.  
         [0085]    As shown in FIG. 7, what the third embodiment differs from the second embodiment is to have a multiplexer  4 - 0  connected to a first port PORT 0  and a multiplexer  4 - 1  connected to a second port PORT 1 .  
         [0086]    Next, read/writing operation of the device will be described.  
         [0087]    [0087]FIG. 8 is an operation waveform chart showing an example of read/writing operation of the memory device according to the third embodiment.  
         [0088]    As shown in FIG. 8, data “0” has been written in a memory cell. The data “0” is read at the first port PORT 0  during the first half of a cycle T 1  and written at the second port PORT 1  during the latter half of the cycle T 1 . Furthermore, a case where the data is read at the first port PORT 0  during the first half of the following cycle T 2  is considered. In addition, when the written data is “0”, it is assumed that the potential of the bit line BL 0  changes to “LOW” level.  
         [0089]    It is adapted that the circuits S/A 0  is used in a first read operation during the first half of the cycle T 1 . And then, electric potential of the bit line BL 0  drops gradually, since the data “0” has been written in the bit line BL 0 . On the other hand, the potential of the bit line BL 1  is still pre-charged.  
         [0090]    In the following writing operation during the latter half of the cycle T 1 , the potential of the bit line BL 0  changes to “LOW” level and the potential of the bit line BL 1  is maintained at “HIGH” level.  
         [0091]    In the following read operation during the first half of the cycle T 2 , as is the case with the second embodiment, the circuit S/A 1 , which has already been pre-charged and is connected to the bit line BL 1 , is activated. In addition, the multiplexer  4 - 0  is controlled so that the output can be linked to the first port PORT 0 .  
         [0092]    As described above, data read and data writing are carried out independently during a cycle of the clock signal in the pseudo two-port RAM.  
         [0093]    Next, read operation will be described.  
         [0094]    [0094]FIG. 9 is an operation waveform chart showing an example of read operation in the semiconductor memory device according to the third embodiment. This example is assumed that data read is carried out successively.  
         [0095]    As shown in FIG. 9, data “0” is written in a memory cell. The data is read at the first port PORT 0  during the first half of a cycle T 1  and read at the second port PORT 1  during the latter half of the cycle. Furthermore, a case where the data is read at the first port PORT 0  during the first half of a following cycle T 2  is considered. In addition, when the written data is “0”, it is assumed that the potential of the bit line BL 0  changes to “LOW” level.  
         [0096]    During the first half of the cycle T 1 , data is read from the bit line BL 0  by using the circuit S/A 0 . At this time, the bit line BL 1  is still pre-charged.  
         [0097]    Next, during the latter half of the cycle T 1 , data is read from the bit line BL 1  by using the circuit S/A 1  and the bit line BL 0  is pre-charged.  
         [0098]    And then, during the first half of the cycle T 2 , data is read from the bit line BL 0  by using the circuit S/A 0  and the bit line BL 1  is pre-charged.  
         [0099]    As described above, data read is carried out twice during a cycle of the clock signal in the pseudo two-port RAM.  
         [0100]    Note that FIG. 10 is an operation waveform chart for assumption that the data write is carried out successively.  
         [0101]    As shown in FIG. 10, even when successive data are written, data write is carried out twice during a cycle of the clock signal.  
         [0102]    [0102]FIG. 11 is a block diagram showing an example of a S/A, pre-charge control circuit included in the semiconductor memory device according to the third embodiment.  
         [0103]    As shown in FIG. 11, what a control circuit  21 ′ differs from the control circuit  21  is that the circuit  21 ′ does not have the frequency divider  11 . In the third embodiment, the circuits S/A 0  and S/A 1  are activated by turns in the first half and the latter half of a cycle of the clock signal CLOCK. Thus, it is not necessary to divide the clock signal CLOCK.  
         [0104]    As described above, it is possible to apply the invention to the pseudo two-port RAM.  
       Fourth Embodiment  
       [0105]    [0105]FIG. 12 is a circuit diagram showing a memory device according to a fourth embodiment of the invention.  
         [0106]    As shown in FIG. 12, what the fourth embodiment differs from the second embodiment is that the circuit is adapted to a common sense AMP. circuit S/A 01  shared between the bit lines BL 0  and BL 1 .  
         [0107]    Read/writing operation of the device will be described below.  
         [0108]    [0108]FIG. 13 is an operation waveform chart showing an example of read/writing operation of the memory device according to the fourth embodiment of the invention. In this description, it is assumed that when data is “0”, the BL 0 =“LOW” or BL 1   32  “HIGH”, and when the data is “1”, the BL 0 =“HIGH” or the BL 1 =“LOW”, in the same manner as described above.  
         [0109]    As shown in FIG. 13, data read is carried out in a cycle T 1 .  
         [0110]    At this time, since the bit line BL 1  is in a pre-charge state, the bit line BL 0  is selected by using the multiplexer  4 - 0  (see. FIG. 12) and connected to the common sense AMP. circuit S/A 01 . Furthermore, as the bit line BL 0  is selected, the output S/AOUT 0  is selected by using the multiplexer  4 - 1  (see. FIG. 12) and adapted to output OUTPUT. In this example, as the bit line BL 0  is at “LOW” level, the output OUTPUT is data “0”.  
         [0111]    In a following cycle T 2 , data writing is carried out. In this example, data “0” is written.  
         [0112]    In a following cycle T 3 , data read is carried out. In the invention, it is basic that the bit lines BL 0  and BL 1  are selected by turns at every cycle as described above. According to this basic, as the bit line BL 0  was selected in the cycle T 1 , the bit line BL 1  was selected in the cycle T 2 . Thus, the bit line BL 0  is to be selected in this cycle T 3 . However, as described in the second embodiment, when operation in the previous cycle T 2  was data writing, it is determined which bit line to be selected, the BL 0  or the BL 1 , referring to the written data.  
         [0113]    In the previous cycle T 2 , data “0” was written. Therefore, the bit line BL 0  is “LOW” and the bit line BL 1  is “High”.  
         [0114]    As a consequence, in this cycle T 3 , the bit line BL 1  is selected by using the multiplexer  4 - 0  and connected to the common sense AMP. circuit S/A 01 . Furthermore, as the bit line BL 1  is selected, output S/A 0 UT 1  is selected by using the multiplexer  4 - 1  and adapted to output OUTPUT. In this example, as the bit line BL 1  is “LOW”, the output OUTPUT is data “1”. In addition, the bit line BL 0  is to be pre-charged during the cycle T 3 .  
         [0115]    Note that when data “1” is written in the previous cycle T 2 , the bit line BL 0  is “HIGH” and the bit line BL 1  is “LOW”. Thus, on the contrary to the above, the bit line BL 0  is selected by using the multiplexer  4 - 0  and connected to the common sense AMP. circuit S/A 01 . And then, output S/AOUT 0  is selected by using the multiplexer  4 - 1  and adapted to output OUTPUT.  
         [0116]    [0116]FIG. 14 shows an example of a S/A, pre-charge control circuit included in the semiconductor memory device according to the fourth embodiment of the invention.  
         [0117]    In the fourth embodiment as described above, data read can be carried out successively without waiting for pre-charge, and thus, operation frequency of the memory device can be improved.  
         [0118]    In addition, as the sense AMP. circuit is adapted to the common sense AMP. circuit in the fourth embodiment, the number of sense AMP. circuits can be reduced in comparison with the first to third embodiments, providing an advantage of high-integration or decreasing electric power consumption.  
         [0119]    Note that the common sense AMP. circuit described in the fourth embodiment can obviously be applied to the pseudo two-port RAM in the third embodiment.  
         [0120]    The invention has been described with the first to fourth embodiments. The invention is not limited to these embodiments but can also be modified variously without departing from the spirit and scope of the present invention.  
         [0121]    For example, in the pseudo two-port RAM according to the third embodiment, a sense AMP. circuit S/A to be activated is switched in accordance with the writing data as is the case with the second embodiment. However, it may be preferable that the sense AMP. circuits S/A to be activated are only switched by turns in the first and latter half of a cycle.  
         [0122]    Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.