Abstract:
In one embodiment, the invention provides a method for manufacturing an array of interferometric modulators. Each interferometric modulator comprises first and second optical layers which when the interferometric modulator is in an undriven state are spaced by a gap of one size, and when the interferometric modulator is in a driven state are spaced by a gap of another size, the size of the gap determining an optical response of the interferometric modulator. The method comprises fabricating interferometric modulators of a first type characterized by the size of the gap between its first and second optical layers when in the undriven state; fabricating interferometric modulators of a second type characterized by the size of the gap between its first and second optical layers when in the undriven state; and fabricating interferometric modulators of a third type characterized by the size of the gap between its first and second optical layers when in the undriven state, wherein fabricating the interferometric modulators of the first, second, and third types comprises using a sequence of deposition and patterning steps of not more than 9 masking steps to deposit and pattern layers of material on a substrate.

Description:
FIELD OF THE INVENTION 
     This invention relates generally to fabrication processes for interferometric modulator arrays and more specifically to methods for manufacturing an array of interferometric modulators. 
     BACKGROUND OF THE INVENTION 
     An interferometric modulator is a class of MEM (micro-electromechanical) systems devices which have been described and documented in a variety of patents including U.S. Pat. Nos. 5,835,255, 5,986,796, 6,040,937, 6,055,090, 6,574,033 (application Ser. No. 10/084,893) U.S. Pat. No. 6,680,792 (application Ser. No. 09/974,544) U.S. Pat. No. 6,867,896 (application Ser. No. 09/966,843) and U.S. Pat. No. 7,067,846 (application Ser. No. 10/878,282), and U.S. Patent Application Publication No 2003/0072070 (application Ser. No. 10/082,397), herein incorporated by reference. One of the key attributes of these devices is the fact that they are fabricated monolithically using semiconductor-like fabrication processes. Specifically, these devices are manufactured in a sequence of steps which combine film deposition, photolithography, and etching using a variety of techniques. Costs in manufacturing processes of this sort are driven in large part by the number of steps in the sequence. Thus, a reduction in the number of masking steps in the overall manufacturing process will help to reduce manufacturing costs. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A-F  illustrate a 9 mask step interferometric modulator fabrication process including a step for defining a black mask and steps for an additive sacrificial layer sub-process in accordance with one embodiment of the invention; 
         FIG. 2  illustrates a subtractive sacrificial layer sub-process in accordance with another embodiment of the invention; 
         FIG. 3  illustrates a subtractive sacrificial layer sub-process optimized using gray-scale lithography in accordance with another embodiment of the invention; 
         FIGS. 4A-C  illustrate a 4 mask interferometric modulator fabrication process without a black mask or multi-height sacrificial layer in accordance with another embodiment of the invention; 
         FIGS. 5A-B  illustrate a 3 mask interferometric modulator fabrication process without black mask or multi-height sacrificial layer in accordance with another embodiment of the invention; 
         FIG. 6  illustrates a 3 mask interferometric modulator fabrication process without a black mask or multi-height sacrificial layer in accordance with another embodiment of the invention; 
         FIG. 7  illustrates a technique for consolidating the formation of post holes and support posts in accordance with another embodiment of the invention; and 
         FIG. 8  illustrates an embodiment in which the support posts are eliminated and the mechanical film is self-supporting. 
         FIGS. 9A-D  illustrate a 6 mask fabrication process for building an interferometric modulator with concealed supports in accordance with another embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     In the following detailed description of embodiments of the invention, numerous specific details are set forth such as examples of specific materials, machines, and methods in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that these specific details need not be employed to practice the present invention. In other instances, well known materials, machines, or methods have not been described in detail in order to avoid unnecessarily obscuring the present invention. 
     U.S. Pat. No. 6,794,119 (application Ser. No. 10/074,562) herein incorporated by reference describes a prototypical fabrication sequence for building interferometric modulators. In general, interferometric modulator fabrication sequences and categories of sequences are notable for their simplicity and cost effectiveness. This is due in large part to the fact that all of the films are deposited using physical vapor deposition (PVD) techniques with sputtering being the preferred and least expensive of the approaches. The materials used are common throughout the liquid crystal display (LCD) industry. This is significant because this industry represents the most cost effective means for manufacturing large area arrays of devices and provides a prime infrastructure for use in building displays and other devices based on interferometric modulators or other MEM devices. This characteristic is described in U.S. Pat. No. 6,867,896 herein incorporated by reference. The materials may be etched using low-cost wet etching processes, or higher cost dry etching techniques depending on the demands of the display application and the need for dimensional control. Photolithography may be achieved using low-cost imaging tools or higher cost step and repeat machines, also dependent on the dimensional requirements of the application. The dimensional requirements are primarily dictated by the resolution of the display in display-centric applications. 
       FIGS. 1A-1F  illustrate one embodiment of an interferometric modulator fabrication sequence which utilizes 9 masking steps. Step  1  shows the deposition of a stack of films  100  on a substrate  102 . The stack  100  is used in the definition of a black mask. More detail on how a black mask may be incorporated into an interferometric modulator array is described in U.S. Pat. No. 6,741,377 (application Ser. No. 10/190,400) herein incorporated by reference. The stack  100  is nominally deposited by sputtering and is subsequently patterned in Step  2 . Patterning refers to a class of techniques which usually include a lithographic step, a development step, and a material etch step. These are well known in the art and described in detail in the aforementioned patents and patent applications. 
     In Step  3 , an insulator  106 , an optical film  108 , and a conductor  1010  are deposited also using sputtering and are of a thickness and composition which has been described in the aforementioned patents and patent applications. Examples of the insulator, optical film, and conductor include silicon dioxide, chrome, and aluminum respectively. The optical film  108  and the conductor  1010  have been subsequently patterned in Step  4 . 
     For interferometric modulator matrices that are to be multi-color displays, some mechanism must be provided for depositing and patterning sacrificial layers with multiple heights. The height of the sacrificial layer is what determines one of the color modes or states of the interferometric modulator during operation. Typical full-color displays require matrices capable of display in at least three colors, Red, Green, and Blue. 
       FIG. 1B  begins with Step  5  where the conductor  1010  has been further patterned to form the conductor rails. These rails are used to enhance the conductivity of the underlying chrome and thereby improve the performance of the overall display by reducing R/C time constants. In Step  6 , an insulating film or films  1012  has been deposited. Step  7  reveals where insulator film/s  1012  have been patterned to expose the optical film  108  as a lead  1014  for bonding at a later step. 
       FIG. 1C  reveals the deposition of a first sacrificial layer  1016  in Step  8  using sputtering and its subsequent patterning in Step  9 . Step  10  shows the deposition of a second sacrificial layer  1018  also using sputtering. 
       FIG. 1D  begins in Step  11  with the patterning of sacrificial layer  1018  followed by the deposition of a third sacrificial layer  1020  in Step  12 . In Step  13 , an etch step is performed, the goal of which is to define support post vias  1022 . This may be done using either wet or dry etching techniques as all of the previous etches may be accomplished. 
       FIG. 1E  reveals the definition of support posts  1024 . More detail on how this process can be accomplished is contained in U.S. Pat. No. 6,794,119 herein incorporated by reference. In one embodiment, a negative acting photosensitive material is spun onto the structure and is exposed through the post support vias through the backside of the wafer illustrated by incident light arrows  1026 . The post support vias are transparent to the light because the sacrificial layers are designed to be opaque. Thus the sacrificial layers act as a mask and save on an additional masking step. Step  14  shows support posts  1024  that are formed in each support post via  1022 . The support posts  1029  may be polymeric, though they could be of any photo-definable material or material matrix. Step  15  shows the definition of a planar cover material  1028  which is used to smooth the topology presented by conductor rails  1010 . This is accomplished using standard lithography. In Step  16  a mechanical film/s  1030  has been deposited. 
       FIG. 1F  begins with Step  17  where the mechanical layer  1030  has been patterned to form the interferometric modulator matrix Red, Green, and Blue columns which are distinguished by the different sacrificial layer heights,  1032 ,  1034 , and  1036 . Finally, in Step  18 , the sacrificial layer has been removed using one of a variety of etching techniques. The preferred technique uses XeF 2  gas to spontaneously etch the sacrificial material. More detail on this approach can be found in U.S. Pat. No. 6,794,119 herein incorporated by reference. 
     Steps  8 - 12  of the previous sequence represent the sacrificial layer subprocess, i.e. the sequence of steps whereby the sacrificial layer heights are defined and patterned. This is an additive approach.  FIG. 2  illustrates an alternative sacrificial layer sub-process that includes a subtractive approach. Referring to  FIG. 2 , substrate  200  is coated with a multilayer sacrificial stack which comprises two different materials which are both etchable using XeF 2 , but which are wet etched, or potentially dry etched, using different chemistries. Silicon and molybdenum are two candidates, though there are others, for both these substances can be etched using XeF 2  However, silicon can be wet etched by hot solutions of tetramethylammonium hydroxide (among other etchants) while molybdenum can be etched using solutions of phosphoric, acetic, and nitric acid. Step  1  shows the multilayer stack deposited on substrate  200 , with silicon layers  202  and  204  acting as an etch stop, and molybdenum layers  206 ,  208 , and  210  acting as the height definition layers. The first resist layer  212  has been defined in Step  2  and in Step  3 , the first patterning step has been accomplished using this layer with the pattern then transferred to the molybdenum layer  206 . The next resist layer  214  has also been defined in Step  3 . Step  4  shows the subsequent patterning step which involves a two stage etch step. Masked by resist layer  214 , the first stage molybdenum layer  208  is patterned using the appropriate etchant, and in the second stage, silicon etch stop layer  204  has been etched through. Finally, in Step  5 , molybdenum layer  210  has been etched by virtue of being masked by a resist layer  216 . Because of the existence of etch stop layers  202  and  204 , the etchant can be used to pattern the height definition layers without concerns about overetching. The material may be exposed for as long as possible to insure complete etching of the feature with fear of etching into the next height definition layer which would compromise the overall process. 
     The sub-process of  FIG. 2  requires three separate lithography steps. Using gray-scale lithography this may be reduced.  FIG. 3  illustrates a variation on this theme which exploits gray-scale lithography to reduce the number of masking steps to one. Referring to  FIG. 3  a multilayer etch stack  310  has been deposited on substrate  312  and is identical to the etch stack of  FIG. 2 . A gray-scale mask  300  which is like a normal lithographic mask except that regions on it may be defined to have variable levels of transmission as opposed to binary levels in traditional masks is positioned over the stack  310 . There are numerous ways of preparing such masks as is well known in the art. For this case, three regions have been defined with three different transmission levels shown with zero transmission at a region  302 , moderate transmission at a region  304 , and the highest at a region  306 . In Step  1  when a photoresist layer  308  over the stack  310  is exposed, a well-timed development stage will result in the photoresist below region  306  developing first. The developer stage is a standard part of patterning where photoresist or other photosensitive material, which has been exposed to light, is dissolved away in a chemical solution specially designed for this task. The consequence of the first development stage is that the mutilayer etch material under region  306  is exposed. In Step  2  the first etch step is accomplished which defines the first height. In Step  3 , after another developer stage, the material under region  304  is exposed and etched appropriately while the region under  306  is etched to the next level. Finally a solvent or other resist removal process is used to finish off the process. 
       FIGS. 4A-C ,  5 A-B, and  6 A-B illustrate reduced mask fabrication sequences. These sequences differ from the sequence of  FIGS. 1A-F  in that they do not contain a black mask, a conductor, or a conductor planarization layer. Certain applications and device designs may eliminate or reduce the need for a black mask. Other applications may not require the addition of a conductor or may have their conductivity sufficiently increased by the presence of a transparent conductor. 
       FIGS. 4A-C  illustrate a sequence that uses 4 mask steps. Beginning with Step  1  in  FIG. 4A , optical film/s  402  are deposited on a substrate  400 . The optical films may or may not include a transparent conductor  404 . In Step  2  these films are patterned and in Step  3  an insulating film or films  406  is/are deposited followed by the deposition of a sacrificial material  408  in Step  4 .  FIG. 4B  begins with Step  5  where post support vias  410  have been etched into the sacrificial spacer  408 . Spacer posts  412  are formed in Step  6  according to the processes described above, and a mechanical film  414  has been deposited in Step  7 . 
       FIG. 4C  starts in Step  8  where sacrificial layer  408  has been etched back, optional etch hole  410  has been formed, and insulator  406  has been etched subsequently in Step  9  to expose optical film  404  for later bonding. The sacrificial layer has been removed in Step  10 . 
       FIGS. 5A-B  illustrate a  3  mask step process. Starting with Step  1  in  FIG. 5A  a starter stack  502  has been deposited on substrate  500 . The starter stack  502  comprises optical/conductor films  504 , insulator  506 , and a sacrificial layer  508 . Step  2  shows the etching of the entire starter stack which constitutes the step consolidation that removes a mask step, and provides support post vias  510 . In Step  3 , the support posts  512  have been formed and a mechanical film  514  is deposited in Step  4 . 
       FIG. 5B  shows in Step  5  the etching of the mechanical film  512 , the sacrificial layer  508 , and etch hole  514 . Step  6  illustrates the etching of the insulator  506 . Finally the sacrificial layer is removed using XeF 2  in Step  7 . Steps  5  and  6  represent the consolidation of a mask step in this sequence since only one mask step is required to accomplish both. 
       FIG. 6A  illustrates a 2 mask step process. Referring to  FIG. 6A , in Step  1  a starter stack comprising a substrate  602 , optical/conductor films  604 , an insulator  606 , and a spacer  608  is patterned to form support post vias  610 . In Step  2 , the vias  610  are filled with a support post material  612 , and a mechanical film layer  614  is deposited in Step  3 . In Step  4 , the mechanical layer  614 , the spacer  608 , and the insulator  606  are etched to expose optical film layers  604  for subsequent bonding. Step  5  is a final step where the sacrificial layer  608  is removed. 
       FIG. 7  illustrates a further means for consolidating mask steps by combining the process for forming the support post vias with the formation of the support posts themselves. This approach relies on a technique which is known in the industry as lift-off. Basically this means that a pattern can be formed in a deposited material not by etching it after deposition, but by forming the pattern during the deposition. One way of achieving this is explained in  FIG. 7 . 
     In Step  1  of  FIG. 7 , a starter stack  702  has been deposited on a substrate  700  and a negative photoresist  704  has been has been spun on. While positive a photoresist may be used, negative resist has the property that a so-called “re-entrant” profile may be formed. A re-entrant profile is one in which the top of the resist is effectively undercut during development. Negative resist differs from positive resist in that exposed negative resist remains during the development process Mask  710  serves to block light  708  and prevent the exposure of the photoresist below. However diffractive effects actually cause some of the incident light to be redirected underneath the mask. This redirected light  706  produces a “lip”  712  and associated re-entrant profile during Step  2 , which shows in the resist after development. 
     The opening in the resist is used as a mask to define the support post via  714  when it is etched into the starter stack  700 . Step  3  illustrates a lift-off process for establishing the support posts which in this case are deposited using some form of physical vapor deposition (PVD) technique as opposed to being spun on and photopolymerized using topside or backside exposure. Because of the re-entrant profile, a distinct break is formed between the post material in the hole  718  and the excess post material on the surface of the photoresist  716 . Thus in Step  4 , the excess material is removed in a lift-off process which uses a liquid solvent to dissolve the remaining photoresist and remove all post material which resides on top of it. 
     In another embodiment, the fabrication process is further streamlined by the elimination of the support posts. This is shown in  FIG. 8  and involves the use of the mechanical film in a self-supporting role. Beginning in Step  1  a starter stack, comprising optical films  802  and sacrificial film  804 , is shown deposited on substrate  800 . By proper application of etching techniques, a via,  806 , is etched onto the stack which exhibits a sloped profile. That is to say, the sidewalls of the via have a profile which is opposite that of the re-entrant profile described in  FIG. 7 . Because of this, when mechanical film  808  is deposited as in Step  3 , the resulting film is conformal and covers the slopes of the via without any break. When the sacrificial film,  808 , is removed in step  4 , the mechanical film remains standing because it supports itself by being attached to the substrate. This technique may be utilized in all of the process sequences described within this patent application. Advanced interferometric modulator architectures such as those described in patent application Ser. No. 08/769,947 filed on Dec. 19, 1996, now abandoned (a divisional application of which is U.S. Pat. No. 6,680,792 herein incorporated by reference), may also be fabricated using extensions of the previously described process sequences. In this architecture the support structure for the movable mirror is defined separately and positioned in such a way as to be hidden from view. Such a design offers improvements in fill factor, and uniformity in performance. 
     Referring now to  FIGS. 9A-D  of the drawings, beginning with Step  1  in  FIG. 9 , optical films  900  and  902  have been deposited and subsequently patterned in Step  2 . Step  3  reveals the deposition of insulator film  904 , followed by the deposition of a sacrificial layer,  908 , and a mirror material,  906 . The mirror is shown after it has been patterned in Step  5 , and an additional sacrificial material,  910 , has been deposited in Step  6 . Step  7  illustrates how the supports and mechanical connections are formed. The patterning which occurs in this step is such that vias  912  etch until stopped by mirror  906 , while vias  914  are etched, in the same step, until stopped by insulator film  904  which may be an oxide layer. In this way, and as shown in Step  8 , polymer supports  916 , are formed using backside exposure techniques to expose the vias  914 . Step  9  reveals how a mechanical support layer  918 , is deposited and consequently forms a mechanical connection to mirror  906  at the junctions indicated by  920 . In Step  10 , etch holes  22  are formed, and the entire structure is released in Step  11  using a gas phase etchant. 
     The fabrication sequences above are meant to illustrate various methods for building interferometric modulator matrices using different mask counts. They are not meant to be limiting in any way in terms of materials used, steps consolidated, or order of steps.