Abstract:
For a multiphase interleaved voltage regulator, an offset cancellation circuit is applied for each phase separately. The current loop gain of each phase is thus increased to mitigate the beat-frequency oscillation in phase currents when the beat frequency is below the bandwidth of the low-pass filter in the offset cancellation circuit, without introducing additional instability issue that is the drawback of increasing current-sensing gain.

Description:
FIELD OF THE INVENTION 
     The present invention is related generally to a multiphase interleaved voltage regulator and, more particularly, to mitigation of beat-frequency oscillation of phase currents in a multiphase interleaved voltage regulator. 
     BACKGROUND OF THE INVENTION 
     References 
     
         
         [1] U.S. Pat. No. 6,683,441. 
         [2] U.S. Pat. No. 6,144,194. 
         [3] J. Sun, Q. Yang, M. Xu, F. C. Lee, “High-frequency dynamic current sharing analyses for multiphase buck VRs,” IEEE Trans. Power Electronics, vol. 22, no. 6, pp. 2424-2431, November 2007. 
         [4] C.-J. Chen, D. Chen, M. Lee, E. K.-L. Tseng, “Design and modeling of a novel high-gain peak current control scheme to achieve adaptive voltage positioning for DC power converters,” in Proc. IEEE Power Electronics Specialists Conference, 2008, pp. 3284-3290. 
         [5] U.S. Pat. No. 7,436,158. 
       
    
     The multiphase interleaved voltage regulator is a popular topology for point-of-load (PoL) applications [1-2]. However, when loading represents high-frequency dynamic changing, this topology suffers from the problem of beat-frequency oscillation in phase currents. This phenomenon is depicted in  FIG. 1 , taking a two-phase interleaved voltage regulator as an example. Under high-frequency variation of load current Iload, two phase currents IL 1  and IL 2  represent a beat-frequency oscillation. The beat frequency is the difference between the sampling frequency (switching frequency) ω sw  of the pulse-width modulator and the load changing frequency ω load , i.e.
 
ω beat =ω sw −ω load .  [Eq-1]
 
The oscillation causes large current amplitude which hurts efficiency and may even destroy the main semiconductor switches. For peak-current mode controlled voltage regulators, it is reported in [3] that increasing current sensing gain can reduce this problem. However, increasing current-sensing gain may leads to instability of the voltage regulator. Moreover, in some applications, adaptive voltage positioning (AVP) is required. In this case, the current-sensing gain is decided by the specification of loading if an optimal AVP design is required.
 
     Peak current-mode control (PCC) offers unique features of easy phase-current balancing and cycle-to-cycle current protection but suffers from the disadvantages of output voltage direct-current (DC) offset and poor line regulation when used to achieve AVP. The over-riding design consideration to achieve AVP is to have constant converter output impedance, and as a result of this design constraint, the low frequency voltage loop gain of a PCC regulator is inevitably low which leads to poor output-voltage DC error and line regulation [4]. In [5], an offset cancellation circuit is proposed to the low-gain current-mode control which is used in applications with AVP function. However, the circuit also suffers from the problem of beat-frequency oscillation at high-frequency dynamic load change. 
       FIG. 2  is a circuit diagram of a two-phase interleaved voltage regulator with PCC. The phase  1  includes switches S 1 , S 2  and an inductor L 1 , and the phase  2  includes switches S 3 , S 4  and an inductor L 2 . The switches S 2  and S 4  can be replaced by diodes if synchronous rectifying is not needed. IL 1  and IL 2  represent the phase currents of the phases  1  and  2 , respectively. Current sensors  10  and  12  have respective gains indicated by Ri, and Hv stands for the gain of a compensator  14  in the voltage-control loop. Pulse-width modulators  16  and  18  perform current mode control in response to current sense signals IS 1  and IS 2 , respectively, and a compensation signal Vc provided by the compensator  14 . For an n-phase interleaved voltage regulator, there would be the circuits of n phases connected in parallel between the input terminal  22  and output terminal  24  of the voltage regulator. 
       FIG. 3  is a circuit diagram of [5], which adds an offset cancellation circuit  26  for modifying the compensation signal Vc of an n-phase interleaved voltage regulator with PCC. In the offset cancellation circuit  26 , an adder  28  sums up all of the current sense signals IS 1 -ISn to obtain a total current sense signal Isum, a divider  30  divides the total current sense signal Isum by the number of the phases n to obtain an average current sense signal Iavg, an adder  32  subtracts the average current sense signal Iavg from the modified compensation signal V′c to obtain a difference signal LI, a low-pass filter  34  filters the difference signal LI to generate an offset signal LO, and an adder  36  adds the offset signal LO into the compensation signal Vc and subtracts a bias ID therefrom to generate the modified compensation signal V′c that replaces the original compensation signal Vc to be provided for the pulse-width modulators  16 - 38  of all the phases. For multiphase applications, the offset cancellation circuit  26  is applied once for all phases, and the low-pass filter  34  is used to eliminate the DC offset of the output voltage Vo. 
     Based on small-signal analysis, the offset cancellation circuit  26  offers boosting in loop gains below the bandwidth of the low-pass filter  34  [4]. It is reported in [3] that the higher loop gain in each phase&#39;s current loop at beat-frequency suppresses the beating oscillation. Therefore, since the offset cancellation circuit  26  results in boosted loop gain, it can be used for mitigation of beat-frequency oscillation in phase currents. However, in [5], based on the analysis below, it can not retain the advantage of mitigation of beat-frequency oscillation. 
     The model for analyzing beat-frequency oscillation in phase currents is shown in  FIG. 4  for peak-current mode, in which ZOC(ω load ) represents the closed-loop output impedance of the voltage regulator, Hv(ω load ) represents the transfer function of the compensator  14 , Fm represents the gain of the pulse-width modulator  16 , D represents the steady-state value of the duty cycle, G′id(ω beat ) represents the transfer function of the beat-frequency duty cycle of the power stage (i.e. the switches S 1 , S 2  and the inductor L 1 ) to the phase currents, He(ω beat ) represents the sample-and-hold effect of the current loop, block  40  is the ω beat  component of the phase  1 , and the beat-frequency oscillation has a susceptibility 
                             IL   ⁢           ⁢   1   ⁢     (     ω   beat     )         I   ⁢           ⁢     load   ⁡     (     ω   load     )           =       ⁢           Zoc   ⁡     (     ω   load     )       ·     Hv   ⁡     (     ω   load     )       ·   Fm   ·     ⅇ       j   ·   D   ·   2     ⁢   π       ·     G   ′       ⁢     id   ⁡     (     ω   beat     )           1   +       G   ′     ⁢       id   ⁡     (     ω   beat     )       ·   Ri   ·     He   ⁡     (     ω   beat     )       ·   Fm                         ≡       ⁢       G   ⁡     (       ω   load     ,     ω   beat       )         1   +       T   ′     ⁢     i   ⁡     (     ω   beat     )               ,                 [     Eq   ⁢     -     ⁢   2     ]               
where G(ω load , ω beat ) is the susceptibility without any current loop, and T′i(ω beat ) is the current loop gain of each phase. In  FIG. 3 , the offset cancellation circuit  26  sums up the current sense signals IS 1 -ISn of all the phases and therefore, due to the phase shift among the phase currents IL 1 -ILn, the sum of their beat-frequency components will be zero, and thereby the transfer function GF(ω) of the low-pass filter  34  does not appear in T′i(ω beat ). In other words, in the conventional approach, the offset cancellation circuit  26  brings no effect to beat-frequency oscillation of the phase currents.
 
     SUMMARY OF THE INVENTION 
     An object of the present invention is directed to mitigation of beat-frequency oscillation of phase currents in a multiphase interleaved voltage regulator. 
     According to the present invention, in a multiphase interleaved voltage regulator, an offset cancellation circuit is applied for each phase separately to increase the phase&#39;s current loop gain. Specifically, the offset cancellation circuit includes a low-pass filter, and when beat frequency is lower than the bandwidth of the low-pass filter, the beat-frequency oscillation of the phase currents is mitigated. Moreover, using this technique to mitigate the problem of beat-frequency oscillation does not introduce additional instability issue, which is the drawback of increasing current sensing gain. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other objects, features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a waveform diagram of a load current and corresponding phase currents in a conventional two-phase interleaved voltage regulator; 
         FIG. 2  is a circuit diagram of a two-phase interleaved voltage regulator with peak-current control; 
         FIG. 3  is a circuit diagram of an n-phase interleaved voltage regulator having an offset cancellation circuit; 
         FIG. 4  is a model for analyzing beat-frequency oscillation in phase currents of the circuit shown in  FIG. 2 ; 
         FIG. 5  is a circuit diagram of an embodiment according to the present invention; 
         FIG. 6  is the frequency response of the offset cancellation circuit shown in  FIG. 5 ; 
         FIG. 7  is a model for analyzing beat-frequency oscillation in phase currents of the circuit shown in  FIG. 5 ; 
         FIG. 8  is the calculation result of using the model of  FIG. 7  to analyze the beat-frequency oscillation in phase currents of the circuit shown in  FIG. 5 ; 
         FIG. 9  is the circuit simulation result of the beat-frequency oscillation alleviation in the present invention; and 
         FIG. 10  shows time-domain waveforms of phase currents in a two-phase interleaved voltage regulator when offset cancellation circuit is applied once for all phases and when offset cancellation circuit is applied to each phase separately. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     For the sake of easy comparison between the present invention and the conventional approach,  FIG. 5  provides an embodiment according to the present invention designed based on the same n-phase interleaved voltage regulator of  FIG. 3 , in which, however, offset cancellation circuit is applied to each phase separately. Likewise, this voltage regulator includes an input terminal  22  for receiving an input voltage VG, an output terminal  24  for providing a regulated output voltage Vo, and n phase circuits  42 - 44  connected in parallel between the input terminal  22  and the output terminal  24  for generating a plurality of phase-interleaved currents IL 1 -ILn. Specifically, each of the phase circuits  42 - 44  has an individual offset cancellation circuit to increase the current loop gain of the phase itself, for example, an offset cancellation circuit  46  for the phase circuit  42  and an offset cancellation circuit  48  for the phase circuit  44 . The same as that of  FIG. 3 , in this embodiment, a compensator  14  generates a compensation signal Vc proportional to the difference between the output voltage Vo and a reference voltage VID for all the phase circuits  42 - 44 , and each of the phase circuits  42 - 44  has a control circuit for current mode control. For example, the phase circuit  42  has a control circuit  50  that includes a pulse-width modulator  16  to generate a pulse-width modulation signal PWM 1  in response to the compensation signal Vc and the phase current IL 1  of the phase circuit  42 . The low-side switches S 2 -S( 2   n ) can be replaced by diodes if synchronous rectifying is not needed. In the phase circuit  42 , the compensation signal Vc is modified by the offset cancellation circuit  46  before it is provided to the pulse-width modulator  16 . In the offset cancellation circuit  46 , an adder  28  subtracts the current sense signal IS 1  representative of the phase current IL 1  from the modified compensation signal VC 1  to generate a difference signal LI 1 , a low-pass filter  34  filters the difference signal LI 1  to generate an offset signal LO 1 , and an adder  36  adds the offset signal LO 1  into the compensation signal Vc and subtracts a bias VID therefrom to generate the modified compensation signal VC 1 . In other words, the offset signal LO 1  is generated in response to the current sense signal IS 1  and the compensation signal Vc, and is injected into the pulse-width modulator  16 . Since the current sense signal IS 1  has the beat-frequency oscillation component, the offset signal LO 1  also has the beat-frequency oscillation component. Therefore, the offset signal LO 1  injected into the pulse-width modulator  16  will affect the phase current IL 1  in terms of beat-frequency oscillation. 
     A typical frequency response of the offset cancellation circuit  46  is shown in  FIG. 6 , in which ω LPF  is the bandwidth of the low-pass filter  34 . The gain of the offset cancellation circuit  46  is greater than one below ω LPF , and equal to one above ω LPF . Thus, the current loop gain of the phase circuit  42  increases below ω LPF  and thereby mitigates beat-frequency oscillation of the phase current IL 1 . Nevertheless, since there is no increase in the current-sensing gain Ri, the risk of instability can be eliminated. 
       FIG. 7  is a small-signal model similar to that of  FIG. 4 , which includes a transfer function GF(ω) of the low-pass filter  34 , and whose beat-frequency oscillation has the susceptibility 
                             IL   ⁢           ⁢   1   ⁢     (     ω   beat     )         I   ⁢           ⁢     load   ⁡     (     ω   load     )           =       ⁢               Zoc   ⁡     (     ω   load     )       ·     Hv   ⁡     (     ω   load     )       ·     GF   ⁡     (     ω   load     )       ·                 Fm   ·     ⅇ       j   ·   D   ·   2     ⁢   π       ·     G   ′       ⁢     id   ⁡     (     ω   beat     )                 1   +       G   ′     ⁢       id   ⁡     (     ω   beat     )       ·   Ri   ·     He   ⁡     (     ω   beat     )       ·   Fm   ·     GF   ⁡     (     ω   beat     )                             ≡       ⁢       G   ⁡     (       ω   load     ,     ω   beat       )         1   +       T   ′     ⁢     i   ⁡     (     ω   beat     )               ,                   ⁢   □                 [     Eq   ⁢     -     ⁢   3     ]               
wherein GF(ω load ) approximates one and GF(ω beat ) is greater than one. Comparing  FIG. 7  with  FIG. 4 , the main difference is the appearance of the GF(ω beat ) block in  FIG. 7 , which is the gain of the offset cancellation circuit  46  and increases the current loop gain T′i(ω beat ) of the phase current IL 1  thereby mitigating the beat-frequency oscillation of the phase current IL 1 .
 
     The calculation result of using the model of  FIG. 7  to analyze the beat-frequency oscillation in phase currents is shown in  FIG. 8 , in which curve  52  represents the susceptibility IL 1 (ω beat )/Iload(ω load ) to the beat-frequency oscillation in phase currents of the circuit shown in  FIG. 5 , and curve  54  represents the susceptibility without the offset cancellation circuit  46  for comparison. Because of the GF(ω beat ) shown in the model of  FIG. 7 , the susceptibility to the beat-frequency oscillation in phase currents is suppressed by the magnitude of GF(ω beat ) in low beat frequency, compared with the conventional peak-current mode control. For the conventional voltage regulator of  FIG. 3 , the offset cancellation circuit  26  takes the sum of all the phase currents IL 1 -ILn for modifying the compensation signal Vc. Since each phase current has a phase shift, the sum of the beating frequency components will be zero. Therefore, the transfer function GF(ω) of the offset cancellation circuit  26  will not appear in the current loop gain Ti(ω beat ) of each phase, and the advantage as in the present invention can not be obtained. 
     This consequence can be justified by circuit simulation.  FIG. 9  shows the simulation result of the beat-frequency oscillation alleviation in the present invention, which shows good match with the model. Time-domain waveforms are shown in  FIG. 10 , where the load current Iload=0-30 A, the load variation frequency f load =299.9 kHz, and the beat-frequency f beat =100 Hz, in which waveforms  56  and  58  represent the phase currents IL 1  and IL 2  under the conventional peak-current control mode ( FIG. 2 ), waveforms  60  and  62  represent the phase currents IL 1  and IL 2  when an single offset cancellation circuit ( FIG. 3 ) is added, and waveforms  64  and  66  represent the phase currents IL 1  and IL 2  when a separate offset cancellation circuit is provided for each phase ( FIG. 5 ). The waveforms show that the voltage regulator according to the present invention has less beat-frequency oscillation than the conventional one. 
     While the present invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and scope thereof as set forth in the appended claims.