Abstract:
A circuit is described which allows a scan latch to selectively pass inputs derived from either of two test outputs, e.g. scan test and built-in self-test data, but which does not apply an added delay to a data path when this is instead selected.

Description:
FIELD OF THE INVENTION 
     The present invention relates to a scan latch circuit useable where alternative testing methods are employed on an associated circuit, and to the combination of such a scan latch circuit with an associated circuit. 
     BACKGROUND OF THE INVENTION 
     Scan latches are known components of test circuitry for circuits, and especially complex circuits such as memories. Such scan lathes typically have a two-input multiplexer with a control input for selecting between those two inputs from the output of the multiplexer feeding to latch circuitry. The control input receives a two state signal called scan enable, so that when it is a logical 1 state the second input, the scan input is applied from the multiplexer output to the latch circuitry. When the scan enable input is at logical 0, the first input, the data input is provided by the multiplexer to the latch circuitry. 
     Where such scan latches are used with a built-in self-test (BIST) arrangement—so that both scan test and built-in self-test (BIST) can be used—it is conventional to connect an input multiplexer to the first input of the scan latch, the input multiplexer having a first input for data output from the memory, a second input for the built-in self-test data from the memory and a control input for selecting between the two inputs. 
     Such a scan latch circuit is disadvantageous in that an additional gate delay is built in to the memory data path. 
     It is accordingly an object of the present invention to overcome difficulties of the prior art. 
     SUMMARY OF THE INVENTION 
     According to a first aspect of the present invention there is provided a scan latch circuit for a circuit having a data output and first and second outputs for test information, the scan latch circuit comprising a scan latch having first and second inputs and a control input for selecting between said first and second inputs for input to latch circuitry of said scan latch, the circuit further having first and second select signal inputs for selecting first and second test modes in which a respective one of said first and second test information is passed to said latch circuitry, wherein said data output is connected directly to one of said first and second inputs of said scan latch, and wherein said first and second outputs and said first and second select signals are connected by further circuitry to said control and said other input of said scan latch. 
     Preferably said further circuitry comprises a two input multiplexer having one input connected to receive said first output, the other input of said two input multiplexer being connected to receive said second output, the select terminal of said multiplexer being connected to receive one of said first and second select signals. 
     Advantageously said first and second select signals are connected to the control input of said scan latch via an OR gate whereby said control input responds to the logical OR of said select signals. 
     According to a second aspect of the invention there is provided the combination of a scan latch circuit and a circuit having a data output and first and second outputs for test information, the scan latch circuit comprising a scan latch having first and second inputs and a control input for selecting between said first and second inputs for input to latch circuitry of said scan latch, the scan latch circuit further having first and second select signal inputs for selecting first and second test modes in which a respective one of said first and second test information is passed to said latch circuitry, wherein said data output is connected directly to one of said first and second inputs of said scan latch, and wherein said first and second outputs and said first and second select signals are connected by further circuitry to said control and said other input of said scan latch. 
     According to a third aspect of the invention there is provided the combination of a scan latch circuit and a memory having a data output and first and second outputs for test information, the scan latch circuit comprising a scan latch having first and second inputs and a control input for selecting between said first and second inputs for input to latch circuitry of said scan latch, the scan latch circuit further having first and second select signal inputs for selecting first and second test modes in which a respective one of said first and second test information is passed to said latch circuitry, wherein said data output is connected directly to one of said first and second inputs of said scan latch, and wherein said first and second outputs and said first and second select signals are connected by further circuitry to said control and said other input of said scan latch. 
     Preferably said further circuitry comprises a two input multiplexer having one input connected to receive said first output, the other input of said two input multiplexer being connected to receive said second output, the select terminal of said multiplexer being connected to receive one of said first and second select signals. 
     Advantageously said first and second select signals are connected to the control input of said scan latch via an OR gate whereby said control input responds to the logical OR of said select signals. 
     Conveniently said circuit comprise a memory. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     An embodiment of the present invention will now be described, by way of example only, with reference to the accompanying drawings in which: 
     FIG. 1 shows a schematic diagram of a conventional test circuit using a scan latch and; 
     FIG. 2 shows an embodiment of scan latch circuitry in accordance with the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In the various figures like reference numerals refer to like parts. 
     Referring to FIG. 1 the scan latch  1  consists of a two input multiplexer  2  having a first input  10  and a second input  11  and further having a control input  12 . The multiplexer output is connected to the input of latch circuitry  3 , here shown figuratively as a single flip flop. 
     An input multiplexer  4  has an output terminal connected to the first input  10  of the scan latch and further has two inputs D and BIST as well as a control input BE. The second input  11  of the scan latch is provided at an input terminal (SI) and the control input at an input terminal (SE). 
     The circuitry of FIG. 1 is connected to memory circuitry and has three modes of operation, a normal mode in which the memory is addressed in a conventional way to provide a data output connected to terminal D, a scan mode in which data are scanned through the memory and the output provided at the terminal (SI) and a third built-in self-test mode in which the configuration of the memory is set, together with external circuitry to cause the memory to cycle through all the possible states of the memory. 
     The operation of the scan latch circuitry of FIG. 1 will now be described: 
     In the normal mode, the input terminal (BE) (BIST enable) is set to zero and the input to terminal (SE) (scan enable) is likewise set at zero. 
     In this state the input multiplexer  4  connects the D input (memory data) to the first input terminal  10  of the scan latch and the multiplexer  2  of the scan latch connects the first input  10  to the latch circuitry  3 . 
     In the built-in self-test mode, signal (BE) is set to logical  1 , whereas signal (SE) is set to logical 0. Thus, the built-in self-test input (BIST) is connected by the input multiplexer  4  to the first input terminal  10  of the scan latch, the multiplexer  2  continuing to supply the first input  10  to the latch circuitry  3 . 
     Finally, in the scan mode, the scan enable signal (SE) is set to logical 1 and the second input  11  which receives the scan input from the memory is connected by the multiplexer  2  to the latch circuitry  3 . 
     It will be appreciated that with the scan enable signal at logical 1, it does not matter whether the signal (BE) is at logical 1 or logical 0. 
     As has previously been discussed, the circuitry shown in FIG. 1 is disadvantageous in that the data input D from the memory suffers undesirable delay. 
     Turning now to FIG. 2, the scan latch circuitry of the present invention connects the data input terminal D directly to the first input terminal  10  of the scan latch  1 . 
     The second input terminal  11  of the scan latch  1  is derived from the output of a two-input multiplexer  24 , the two inputs to the multiplexer being derived from the built-in self-test (BIST) and the scan input data signal (SI). The two-input multiplexer  24  is controlled by the scan enable signal (SE). 
     The control input  12  of the scan latch is provided by the output of the two input OR gate  25  whose inputs are provided by the BIST enable signal (BE) and the scan enable signal (SE). 
     In operation, when both the scan enable signal and the BIST enable signal (SE,BE) are at logical 0, control input  12  of the scan latch  1  is at logical 0 and the data input D of the memory is connected via the multiplexer  2  of the scan latch to the latch circuitry  3  of the scan latch. 
     If either or both signals SE and BE are at logical 1, a logical 1 output is provided by the OR gate  25  to the control input  12  of the scan latch so that the scan latch multiplexer  2  connects the second input  11  of the scan latch to the latch circuitry  3 . If the scan enable input (SE) is at logical 1, then the input multiplexer  24  connects the second input (SI) to the second input  11  of the scan latch and thus to the latch circuitry  3 . Only if the BIST enable signal (BE) is at logical 1 and the scan enable signal (SE) as at logic 0 is the BIST data signal BIST connected by the input multiplexer  24  to the second input  11  of the scan latch, and thus to the latch circuitry  3  of the scan latch. 
     It will be seen that this arrangement is advantageous in that the data input to the scan latch, which is critical path for normal operation, is not impeded by passage through a multiplexer or by gating circuitry. The arrangement is disadvantageous in that an additional gate  25  is required by comparison with the conventional circuit but it will be understood by those skilled in the art that for a conventional memory arrangement there will be a scan latch for each bit (e.g. 32 bits) of the memory and that the gate  25  is shared between all of the scan latches. 
     The invention has been described in the context of a memory having scan test and built-in self-test arrangements. It is however to be understood that the invention is applicable to any circuitry in an application which permits any alternative testing methodologies to be used.