Abstract:
A bus of a SoC (system on chip) includes a system arbiter for controlling not only a command arbiter but also a read information arbiter, a write data control circuit, a write complete notice arbiter and the like. A sequential table containing a series of system operations including activation processing and application processing and an operation clock information circuit or the like that becomes effective when a SoC bus region is divided by an operation clock frequency are utilized in assignment of priority of buses of the system arbiter. Thus, the information transfer efficiency of the whole system bus and the information transfer efficiency of every transfer originator can be improved.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    The present invention relates to an information processing apparatus having a contention control function for a SoC (System on Chip) system bus. 
         [0002]      FIG. 22  is a block diagram for schematically showing the architecture of a conventional information processing apparatus and  FIG. 23  is a timing chart for explaining its operation. 
         [0003]    As shown in  FIG. 22 , the conventional information processing apparatus has a system bus for connecting a plurality of transfer originator bus control units  1  through  3  (transfer originators A, B and C) for respectively sending transfer information and a plurality of transfer destination bus control units  4  and  5  (transfer destinations  1  and  2 ) for respectively receiving the transfer information to one another, and includes circuits (command buffers)  9  through  11  for storing precedent transfer information of the transfer originator bus control units  1  through  3 ; buses  6  through  8  for respectively connecting the transfer originator bus control units  1  through  3  to the command buffers  9  through  11 ; circuits (command arbiters)  13  and  14  for controlling contention of the transfer information between the transfer destination bus control units  4  and  5 ; a hierarchical bus  12  for connecting the command buffers  9  through  11  to the command arbiters  13  and  14 ; buses  21  and  22  for respectively connecting the command arbiters  13  and  14  to the transfer destination bus control units  4  and  5 ; circuits (read information arbiters)  50  through  52  for controlling the contention of read information; buses  37  through  39  for respectively connecting the read information arbiters  50  through  52  to the transfer originator bus control units  1  through  3 ; a hierarchical bus  40  for connecting the transfer destination bus control units  4  and  5  to the read information arbiters  50  through  52 ; circuits (decoders)  44  and  45  for identifying read information; and buses  48  and  49  for respectively connecting the decoders  44  and  45  to the transfer destination bus control units  4  and  5 . 
         [0004]    The operation of the information processing apparatus having the aforementioned architecture will now be described with reference to  FIG. 23 . 
         [0005]    In  FIG. 23 , the ordinate indicates the states of the transfer originators and the transfer destinations, a transfer originator slot corresponds to a three-stage buffer for storing precedent transfer information, and a transfer destination slot corresponds to a three-stage buffer for storing read data notice information. The abscissa indicates time, and each time duration among times T 1 , T 2 , T 3 , T 4 , T 5 , T 6  and T 7  corresponds to an information processing unit time. Also, the priority for the command arbiters  13  and  14  and the read information arbiters  50  through  52  is in the order of the transfer originator A, the transfer originator B and the transfer originator C. 
         [0006]    At the time T 1 , the transfer originator A issues two transfer information items to the transfer destination  1 , the transfer originator B issues two transfer information items to the transfer destination  1  and the transfer originator C issues two transfer information items to the transfer destination  1  and one transfer information item to the transfer destination  2 . 
         [0007]    In a period between the times T 1  and T 2 , since the transfer originator A has the highest priority according to the priority for the command arbiters  13  and  14 , the transfer information items are transferred in the order of the transfer originator A, the transfer originator B and the transfer originator C. Also, the transfer destination  1  issues read information notices to the respective transfer originators. 
         [0008]    At the time T 2 , the transfer originator A issues one transfer information item to the transfer destination  1 , the transfer originator B issues one transfer information item to the transfer destination  1 , and the transfer originator C issues one transfer information item to the transfer destination  1  and one transfer information item to the transfer destination  2 . 
         [0009]    In a period between the times T 2  and T 3 , since the transfer originator A has the highest priority in accordance with the priority for the command arbiters  13  and  14 , the transfer information items are transferred in the order of the transfer originator A, the transfer originator B and the transfer originator C. Also, the transfer destination  1  issues a read information notice to the transfer originator C. 
         [0010]    At the time T 3 , the transfer originator C alone issues one transfer information item to the transfer destination  2 . Also, the transfer destination  1  simultaneously issues a read information notice. 
         [0011]    In a period between the times T 4  and T 6 , read information notices issued by the respective transfer destinations are sent to the respective transfer originators in accordance with the priority for the read information arbiters  50  through  52 . 
         [0012]    In a conventional technique, a bus for supporting split transfer is employed in a bus system in which a plurality of modules are hierarchically connected through buses, but the contention control is performed independently in every bus of the transfer destinations as described above (see Japanese Laid-Open Patent Publication No. 2002-278923). 
       SUMMARY OF THE INVENTION 
       [0013]    In the conventional contention control performed on the basis of the transfer information described above, when the contention control is performed independently in every bus of the transfer destinations, it is disadvantageously impossible to guarantee the performance in consideration of the end of the transfer and to improve the transfer performance of the whole SoC system bus. 
         [0014]    In order to overcome the disadvantage, the information processing apparatus according to one aspect of the invention includes a system bus for connecting a plurality of transfer originator bus control units each for sending transfer information and a plurality of transfer destination bus control units each for receiving the transfer information to one another; a circuit provided correspondingly to every bus of the plurality of transfer originator bus control units for storing precedent transfer information; a hierarchical bus for connecting the plurality of transfer originator bus control units to the plurality of transfer destination bus control units; a circuit provided correspondingly to every bus of the plurality of transfer destination bus control units for performing contention control of the transfer information; and a circuit for controlling the circuit provided for performing the contention control. 
         [0015]    According to another aspect of the invention, the information processing apparatus includes a system bus for connecting a plurality of transfer originator bus control units each for sending transfer information and a plurality of transfer destination bus control units each for receiving the transfer information to one another; a circuit for performing contention control of write complete notice information, read data information and the transfer information between buses of the plurality of transfer originator bus control units and buses of the plurality of transfer destination bus control units; and a circuit for storing successive transfer information necessary for the contention control. 
         [0016]    According to the present invention, the efficiency of successive information transfer between transfer destination bus control units, the transfer efficiency of a whole SoC system bus and the information transfer efficiency of every transfer originator can be improved. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0017]      FIG. 1  is a block diagram for schematically showing the architecture of an information processing apparatus according to Embodiment 1 of the invention. 
           [0018]      FIG. 2  is a timing chart of the information processing apparatus of  FIG. 1 . 
           [0019]      FIG. 3  is a block diagram for schematically showing the architecture of an information processing apparatus according to Embodiment 2 of the invention. 
           [0020]      FIG. 4  is a timing chart of the information processing apparatus of  FIG. 3 . 
           [0021]      FIG. 5  is a timing chart described as a comparative example of  FIG. 4 . 
           [0022]      FIG. 6  is a block diagram for schematically showing the architecture of an information processing apparatus according to Embodiment 3 of the invention. 
           [0023]      FIG. 7  is a timing chart of the information processing apparatus of  FIG. 6 . 
           [0024]      FIG. 8  is a block diagram for schematically showing the architecture of an information processing apparatus according to Embodiment 4 of the invention. 
           [0025]      FIG. 9  is a timing chart of the information processing apparatus of  FIG. 8 . 
           [0026]      FIG. 10  is a timing chart described as a comparative example of  FIG. 9 . 
           [0027]      FIG. 11  is a block diagram for schematically showing the architecture of an information processing apparatus according to Embodiment 5 of the invention. 
           [0028]      FIG. 12  is a block diagram for schematically showing the architecture of an information processing apparatus according to Embodiment 6 of the invention. 
           [0029]      FIG. 13  is a timing chart of the information processing apparatus of  FIG. 12 . 
           [0030]      FIG. 14  is a timing chart described as a comparative example of  FIG. 13 . 
           [0031]      FIG. 15  is a block diagram for schematically showing the architecture of an information processing apparatus according to Embodiment 7 of the invention. 
           [0032]      FIG. 16  is a timing chart of the information processing apparatus of  FIG. 15 . 
           [0033]      FIG. 17  is a block diagram for schematically showing the architecture of an information processing apparatus according to Embodiment 8 of the invention. 
           [0034]      FIG. 18  is a timing chart of the information processing apparatus of  FIG. 17 . 
           [0035]      FIG. 19  is a timing chart described as a comparative example of  FIG. 18 . 
           [0036]      FIG. 20  is a block diagram for schematically showing the architecture of an information processing apparatus according to Embodiment 9 of the invention. 
           [0037]      FIG. 21  is a block diagram for schematically showing the architecture of an information processing apparatus according to Embodiment 10 of the invention. 
           [0038]      FIG. 22  is a block diagram for schematically showing the architecture of a conventional information processing apparatus. 
           [0039]      FIG. 23  is a timing chart of the information processing apparatus of  FIG. 22 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0040]    Information processing apparatuses according to referred embodiments of the invention will now be described with reference to the accompanying drawings. 
       Embodiment 1 
       [0041]      FIG. 1  is a block diagram for schematically showing the architecture of an information processing apparatus according to Embodiment 1 of the invention. 
         [0042]    As shown in  FIG. 1 , the information processing apparatus of this embodiment has a system bus for connecting a plurality of transfer originator bus control units  1  through  3  for respectively sending transfer information and a plurality of transfer destination bus control units  4  and  5  for respectively receiving the transfer information to one another, and includes circuits (command buffers)  9  through  11  for storing precedent transfer information of the transfer originator bus control units  1  through  3 ; buses  6  through  8  for respectively connecting the transfer originator bus control units  1  through  3  to the command buffers  9  through  11 ; circuits (command arbiters)  13  and  14  for controlling contention of the transfer information between the transfer destination bus control units  4  and  5 ; a hierarchical bus  12  for connecting the command buffers  9  through  11  to the command arbiters  13  and  14 ; a circuit (system arbiter)  15  for controlling the command arbiters  13  and  14 ; buses  16  through  18  for respectively connecting the command buffers  9  through  11  to the system arbiter  15 ; buses  19  and  20  for respectively connecting the command arbiters  13  and  14  to the system arbiter  15 ; buses  21  and  22  for respectively connecting the command arbiters  13  and  14  to the transfer destination bus control units  4  and  5 ; and a bus  23  for controlling the system arbiter  15  from the transfer originator bus control units  1  through  3 . 
         [0043]    The operation of the information processing apparatus having the aforementioned architecture will now be described with reference to  FIG. 2 . 
         [0044]    In  FIG. 2 , a transfer originator slot corresponds to a three-stage buffer for storing precedent transfer information and a transfer destination slot corresponds to a three-stage buffer for storing precedent write complete notice information and read data notice information. Also, it is assumed that the system arbiter  15  for controlling the command arbiters  13  and  14  from the transfer originators through the bus  23  is set by software for controlling contention on the basis of information of a slot storing precedent transfer information. Furthermore, it is assumed that the priority for the command arbiters  13  and  14  is in the order of the transfer originator A, the transfer originator B and the transfer originator C. 
         [0045]    At time T 1 , the transfer originator A issues two transfer information items to the transfer destination  1 , the transfer originator B issues two transfer information items to the transfer destination  1  and the transfer originator C issues two transfer information items to the transfer destination  1  and one transfer information item to the transfer destination  2 . The issue information of these transfer originators is transmitted to the system arbiter  15 , so that contention control for giving the highest priority to the transfer originator C having the largest number of issues can be transmitted from the system arbiter  15  to the command arbiter  13  of the transfer destination  1 . 
         [0046]    In a period between the times T 1  and T 2 , since the transfer originator C has the highest priority, the transfer information items are sent in the order of the transfer originator C, the transfer originator A and the transfer originator B. 
         [0047]    At the time T 2 , the transfer originator A issues one transfer information item to the transfer destination  1 , the transfer originator B issues one transfer information item to the transfer destination  1  and the transfer originator C issues one transfer information item to the transfer destination  1  and one transfer information item to the transfer destination  2 . The issue information of these transfer originators is transmitted to the system arbiter  15 , so that contention control for giving the highest priority to the transfer originator C having the largest number of issues can be transmitted from the system arbiter  15  to the command arbiter  13  of the transfer destination  1 . 
         [0048]    In a period between the times T 2  and T 3 , since the transfer originator C has the highest priority, the transfer information items are sent in the order of the transfer originator C, the transfer originator A and the transfer originator B. When the transfer from the transfer originator C to the transfer destination  1  is completed, the transfer to the transfer destination  2  is started. 
         [0049]    At the time T 3 , the transfer requested by all the transfer originators is completed. 
         [0050]    In this manner, the transfer from the transfer originator C to the transfer destination  2  is carried out at early timing, and therefore, the transfer efficiency of the system bus can be improved. 
       Embodiment 2 
       [0051]      FIG. 3  is a block diagram for schematically showing the architecture of an information processing apparatus according to Embodiment 2 of the invention. 
         [0052]    As shown in  FIG. 3 , the information processing apparatus of this embodiment has a system bus for connecting a plurality of transfer originator bus control units  1  through  3  for respectively sending transfer information and a plurality of transfer destination bus control units  4  and  5  for respectively receiving the transfer information to one another, and includes circuits (command buffers)  9  through  11  for storing precedent transfer information of the transfer originator bus control units  1  through  3 ; buses  6  through  8  for respectively connecting the transfer originator bus control units  1  through  3  and to command buffers  9  through  11 ; circuits (command arbiters)  13  and  14  for controlling contention of the transfer information between the transfer destination bus control units  4  and  5 ; a hierarchical bus  12  for connecting the command buffers  9  through  11  to the command arbiters  13  and  14 ; a circuit (system arbiter)  15  for controlling the command arbiters  13  and  14 ; buses  16  through  18  for respectively connecting the command buffers  9  through  11  to the system arbiter  15 ; buses  19  and  20  for respectively connecting the command arbiters  13  and  14  to the system arbiter  15 ; buses  21  and  22  for respectively connecting the command arbiters  13  and  14  to the transfer destination bus control units  4  and  5 ; a bus  23  for controlling the system arbiter  15  from the transfer originator bus control units  1  through  3 ; address decoders  24  through  26  for respective transfer originator buses; and buses  27  through  29  for respectively connecting the address decoders  24  through  26  to the system arbiter  15 . 
         [0053]    The operation of the information processing apparatus having the aforementioned architecture will now be described with reference to  FIG. 4 . 
         [0054]    In  FIG. 4 , a transfer originator slot corresponds to a three-stage buffer for storing precedent transfer information and a transfer destination slot corresponds to a three-stage buffer for storing precedent write complete notice information and read data notice information. Also, it is assumed that the system arbiter  15  for controlling the command arbiters  13  and  14  from the transfer originator control units  1  through  3  through the bus  23  is set by software for controlling contention on the basis of information of a slot storing precedent transfer information and for using address information of a command within the slot. Furthermore, it is assumed that the priority for the command arbiters  13  and  14  is in the order of the transfer originator A, the transfer originator B and the transfer originator C. 
         [0055]    At time T 1 , the transfer originator A issues two transfer information items to the transfer destination  1 , the transfer originator B issues three transfer information items to the transfer destination  1  and the transfer originator C issues two transfer information items to the transfer destination  1  and one transfer information item to the transfer destination  2 . The issue information and the address information of these transfer originators are transmitted to the system arbiter  15 , so that contention control for giving higher priority to the transfer originator B and the transfer originator C having the largest number of issues and for further giving the highest priority to the transfer originator C determined to have issued the transfer information to the different destinations based on the address information can be transmitted from the system arbiter  15  to the command arbiter  13  of the transfer destination  1 . 
         [0056]    In a period between the times T 1  and T 2 , since the transfer originator C has the highest priority, the transfer information items are sent in the order of the transfer originator C, the transfer originator B and the transfer originator A. 
         [0057]    At the time T 2 , the transfer originator A issues one transfer information item to the transfer destination  1 , the transfer originator B issues two transfer information items to the transfer destination  1  and the transfer originator C issues one transfer information item to the transfer destination  1  and one transfer information item to the transfer destination  2 . The issue information of these transfer originators is transmitted to the system arbiter  15 , so that contention control for giving the highest priority to the transfer originator C having the largest number of issues to the different transfer destinations can be transmitted from the system arbiter  15  to the command arbiter  13  of the transfer destination  1 . 
         [0058]    In a period between the times T 2  and T 3 , since the transfer originator C has the highest priority, the transfer information items are sent in the order of the transfer originator C, the transfer originator B and the transfer originator A. When the transfer from the transfer originator C to the transfer destination  1  is completed, the transfer to the transfer destination  2  is started. 
         [0059]      FIG. 5  is a timing chart obtained when the same transfer as that shown in  FIG. 4  is performed in the information processing apparatus of Embodiment 1 (shown in  FIG. 1 ). 
         [0060]    As is understood from comparison between  FIGS. 4 and 5 , the transfer from the transfer originator C to the transfer destination  2  can be carried out at early timing in Embodiment 2, and therefore, the transfer efficiency of the system bus can be improved while retaining the throughput of the whole system bus. 
       Embodiment 3 
       [0061]      FIG. 6  is a block diagram for schematically showing the architecture of an information processing apparatus according to Embodiment 3 of the invention. 
         [0062]    As shown in  FIG. 6 , the information processing apparatus of this embodiment has a system bus for connecting a plurality of transfer originator bus control units  1  through  3  for respectively sending transfer information and a plurality of transfer destination bus control units  4  and  5  for respectively receiving the transfer information to one another, and includes circuits (command buffers)  9  through  11  for storing precedent transfer information of the transfer originator bus control units  1  through  3 ; buses  6  through  8  for respectively connecting the transfer originator bus control units  1  through  3  to the command buffers  9  through  11 ; circuits (command arbiters)  13  and  14  for controlling contention of the transfer information between the transfer destination bus control units  4  and  5 ; a hierarchical bus  12  for connecting the command buffers  9  through  11  to the command arbiters  13  and  14 ; a circuit (system arbiter)  15  for controlling the command arbiters  13  and  14 ; buses  16  through  18  for respectively connecting the command buffers  9  through  11  to the system arbiter  15 ; buses  19  and  20  for respectively connecting the command arbiters  13  and  14  to the system arbiter  15 ; buses  21  and  22  for respectively connecting the command arbiters  13  and  14  to the transfer destination bus control units  4  and  5 ; a bus  23  for controlling the system arbiter  15  from the transfer originator bus control units  1  through  3 ; address decoders  24  through  26  for respective transfer originator buses; buses  27  through  29  for respectively connecting the address decoders  24  through  26  to the system arbiter  15 ; write data control circuits  30  and  31  for controlling issue of write data to the respective transfer destinations; and buses  32  and  33  for respectively connecting the write data control circuits  30  and  31  to the system arbiter  15 . 
         [0063]    The operation of the information processing apparatus having the aforementioned architecture will now be described with reference to  FIG. 7 . 
         [0064]    In  FIG. 7 , a transfer originator slot corresponds to a three-stage buffer for storing precedent transfer information and a transfer destination slot corresponds to a three-stage buffer for storing precedent write complete notice information and read data notice information. Also, it is assumed that the system arbiter  15  for controlling the command arbiters  13  and  14  from the transfer originator bus control units  1  through  3  through the bus  23  is set by software for controlling contention on the basis of information of a slot storing precedent transfer information and for using address information of a command within the slot. Furthermore, it is assumed that the priority for the command arbiters  13  and  14  is in the order of the transfer originator A, the transfer originator B and the transfer originator C. 
         [0065]    At time T 1 , the transfer originator A issues two transfer information items to the transfer destination  1 , the transfer originator B issues three transfer information items to the transfer destination  1  and the transfer originator C issues two transfer information items to the transfer destination  1  and one transfer information item to the transfer destination  2 . The issue information and the address information of these transfer originators are transmitted to the system arbiter  15 , so that contention control for giving higher priority to the transfer originator B and the transfer originator C having the largest number of issues and for further giving the highest priority to the transfer originator C determined to have issued the transfer information to the different transfer destinations based on the address information can be transmitted from the system arbiter  15  to the command arbiter  13  of the transfer destination  1 . 
         [0066]    In a period between the times T 1  and T 2 , since the transfer originator C has the highest priority, the transfer information items are sent in the order of the transfer originator C, the transfer originator B and the transfer originator A. The write data control circuit  30  lowers write data traffic of the transfer originators B and A so as to priorly process the write data of the transfer originator C having issued access requests to the different transfer destinations. Also, when the transfer from the transfer originator C to the transfer destination  1  is completed, the transfer to the transfer destination  2  is started. 
         [0067]    At the time T 2 , the transfer originator A issues one transfer information item to the transfer destination  1 , the transfer originator B issues two transfer information items to the transfer destination  1  and the transfer originator C has completed to issue transfer information items. The issue information and the address information of these transfer originators are transmitted to the system arbiter  15 , so that contention control for giving higher priority to the transfer originator B having the larger number of issues than the transfer originator A can be transmitted from the system arbiter  15  to the command arbiter  13  of the transfer destination  1 . 
         [0068]    In a period between the times T 2  and T 3 , since the transfer originator C has the highest priority, the transfer information items are sent in the order of the transfer originator C, the transfer originator B and the transfer originator A. Furthermore, when the numbers of access requests made by the transfer originators B and A are the same, the priority is the same, and hence, the transfer information items are transferred with the same write data traffic. 
         [0069]    At the time T 3 , since none of the transfer originators makes an access request, the contention control is not performed. 
         [0070]    In a period between the times T 3  and T 4 , the remaining write data transfer of the transfer originators B and A is issued, and the processing is completed. 
         [0071]    In this manner, the transfer from the transfer originator C to the transfer destination  2  can be carried out at early timing, and therefore, the transfer efficiency of the system bus can be improved while retaining the throughput of the whole system bus. 
       Embodiment 4 
       [0072]      FIG. 8  is a block diagram for schematically showing the architecture of an information processing apparatus according to Embodiment 4 of the invention. 
         [0073]    As shown in  FIG. 8 , the information processing apparatus of this embodiment has a system bus for connecting a plurality of transfer originator bus control units  1  through  3  for respectively sending transfer information and a plurality of transfer destination bus control units  4  and  5  for respectively receiving the transfer information to one another, and an access from a transfer originator to a transfer destination is processed in the same manner as in the conventional technique (shown in  FIG. 22 ). The information processing apparatus includes, for improving the transfer efficiency by changing a form of sending a notice from a transfer destination to a transfer originator, circuits (write complete notice arbiters)  34  through  36  provided correspondingly to respective buses of the transfer originator bus control units  1  through  3 ; buses  37  through  39  for respectively connecting the transfer originator bus control units  1  through  3  to the write complete notice arbiters  34  through  36 ; a hierarchical bus  40  for connecting the write complete notice arbiters  34  through  36  to the transfer destination bus control units  4  and  5 ; a circuit (system arbiter)  15  for controlling the write complete notice arbiters  34  through  36 ; buses  41  through  43  for respectively connecting the write complete notice arbiters  34  through  36  to the system arbiter  15 ; circuits (decoders)  44  and  45  for decoding write transfer complete identification information used in sending a write transfer complete notice to the transfer originator bus control units  1  through  3  from the transfer destination control units  4  and  5 ; buses  46  and  47  for respectively connecting the decoders  44  and  45  to the system arbiter  15 ; and buses  48  and  49  for respectively connecting the transfer destination bus control units  4  and  5  to the decoders  44  and  45 . 
         [0074]    The operation of the information processing apparatus having the aforementioned architecture will now be described with reference to  FIG. 9 . 
         [0075]    In  FIG. 9 , a transfer originator slot corresponds to a three-stage buffer for storing precedent transfer information and a transfer destination slot corresponds to a three-stage buffer for storing precedent write complete notice information and read data notice information. Also, it is assumed that the write complete notice arbiters  34  through  36  are set by software through the bus  23  to be controlled by the system arbiter  15  by using the write transfer complete identification information. Furthermore, it is assumed that the priority for the command arbiters  13  and  14  is in the order of the transfer originator A, the transfer originator B and the transfer originator C. 
         [0076]    At time T 1 , the transfer originator A issues two transfer information items to the transfer destination  1 , the transfer originator B issues two transfer information items to the transfer destination  1  and the transfer originator C issues two transfer information items to the transfer destination  1  and one transfer information item to the transfer destination  2 . The priority is determined by the command arbiters  13  and  14  with fixed priority through accesses from these transfer originators to the transfer destination  1 . 
         [0077]    In a period between the times T 1  and T 2 , since the transfer originator A has the highest priority, the transfer information items are sent in the order of the transfer originator A, the transfer originator B and the transfer originator C. Also, write complete notices from the transfer destination  1  are sent to the respective transfer originators. 
         [0078]    At the time T 2 , the transfer originator A issues one transfer information item to the transfer destination  1 , the transfer originator B issues one transfer information item to the transfer destination  1  and the transfer originator C issues one transfer information item to the transfer destination  1  and one transfer information item to the transfer destination  2 . The priority is determined by the command arbiters  13  and  14  in the same manner as described above. 
         [0079]    In a period between the times T 2  and T 3 , since the transfer originator A has the highest priority, the transfer information items are sent in the order of the transfer originator A, the transfer originator B and the transfer originator C. Also, write complete notices from the transfer destination  1  are sent to the respective transfer originators. 
         [0080]    At the time T 3 , although there is an access request from the transfer originator C to the transfer destination  2 , there is no contention because other transfer originators issue no access request. 
         [0081]    In a period between the times T 3  and T 4 , the access request from the transfer originator C to the transfer destination  2  is executed. Furthermore, although the transfer originator C issues an access request to the transfer destination  1 , the access request cannot be processed because a write complete notice has not been received. 
         [0082]    At the time T 4 , write complete notices are issued to all the transfer originators, and since the access request from the transfer originator C to the transfer destination  1  is waited, the system arbiter  15  controls the write complete notice arbiters so as to give the highest priority to the write complete notice to the transfer originator C. 
         [0083]    In a period between the times T 4  and T 5 , the write complete notices are executed in the order of the transfer originator C, the transfer originator A and the transfer originator B, and the transfer originator C issues one transfer information item to the transfer destination  1  after receiving the write complete notice from the transfer destination  2 . 
         [0084]    At the time T 5 , the access requests from all the transfer originators are completed. 
         [0085]    In a period between the times T 5  and T 6 , a write complete notice is sent from the transfer destination  1  to the transfer originator C. 
         [0086]      FIG. 10  is a timing chart obtained when the same transfer as that shown in  FIG. 9  is performed in the conventional information processing apparatus (shown in  FIG. 22 ). 
         [0087]    As is understood from comparison between  FIGS. 9 and 10 , the transfer from the transfer originator C to the transfer destination  2  can be carried out at early timing in Embodiment 4, and therefore, the transfer efficiency of the system bus can be improved while retaining the throughput of the whole system bus. 
       Embodiment 5 
       [0088]      FIG. 11  is a block diagram for schematically showing the architecture of an information processing apparatus of Embodiment 5 obtained by replacing the write complete notice arbiters  34  through  36  of Embodiment 4 (shown in  FIG. 8 ) with read information arbiters  50  through  52 . In Embodiment 5, the transfer efficiency of read transfer can be improved in the same manner as in the improvement of the transfer efficiency of write transfer of Embodiment 4. 
       Embodiment 6 
       [0089]      FIG. 12  is a block diagram for schematically showing the architecture of an information processing apparatus according to Embodiment 6 of the invention. 
         [0090]    As shown in  FIG. 12 , the information processing apparatus of this embodiment has a system bus for connecting a plurality of transfer originator bus control units  1  through  3  for respectively sending transfer information and a plurality of transfer destination bus control units  4  and  5  for respectively receiving the transfer information to one another, and includes, in addition to the components of Embodiment 2, a write transferring bus  53 , a read transferring bus  54 , a write transferring system arbiter  55 , a read transferring system arbiter  56 , and a bus  57  for connecting the write transferring system arbiter  55  to the read transferring system arbiter  56 . 
         [0091]    The operation of the information processing apparatus having the aforementioned architecture will now be described with reference to  FIG. 13 . 
         [0092]    In  FIG. 13 , a transfer originator slot corresponds to a three-stage buffer for storing precedent transfer information and a transfer destination slot corresponds to a three-stage buffer for storing precedent write complete notice information and read data notice information. Also, it is assumed that the system arbiter  55  for controlling the command arbiters  13  and  14  from the transfer originators through the bus  23  is set by software for controlling contention on the basis of information of a slot storing precedent transfer information, for using address information of a command within the slot and for using a dependent relationship between write transfer and read transfer. Furthermore, the priority for the command arbiters  13  and  14  is in the order of the transfer originator A, the transfer originator B and the transfer originator C. 
         [0093]    At time T 1 , the transfer originator A issues two transfer information items to the transfer destination  1 , the transfer originator B issues two transfer information items to the transfer destination  1  and the transfer originator C issues two exclusive transfer information items to the transfer destination  1  and one transfer information item to the transfer destination  2 . A dependent relationship between write transfer and read transfer is detected by the exclusive transfer information items issued by the transfer originator C, and the command arbiters  13  and  14  are controlled so that the processing of the transfer originator C can be successively performed by the write transferring system arbiter  55  and the read transferring system arbiter  56 . 
         [0094]    In a period between the times T 1  and T 2 , since the transfer originator A has the highest priority, the transfer information items are sent in the order of the transfer originator A, the transfer originator B and the transfer originator C. Also, write complete notices from the transfer destination  1  are sent to the respective transfer originators. 
         [0095]    At the time T 2 , the transfer originator A issues one transfer information item to the transfer destination  1 , the transfer originator B issues one transfer information item to the transfer destination  1  and the transfer originator C issues one transfer information item to the transfer destination  1  and one transfer information item to the transfer destination  2 . Since the successive processing should be performed because of the detected exclusive transfer information item of the transfer originator C, the priority is assigned by the command arbiters  13  and  14  in the order of the transfer originator C, the transfer originator A and the transfer originator B. 
         [0096]    In a period between the times T 2  and T 3 , the transfer is executed in accordance with the priority assigned at the time T 2 . 
         [0097]    At the time T 3 , although there is an access request from the transfer originator C to the transfer destination  2 , there is no contention because none of the other transfer originators issues an access request. 
         [0098]    In a period between the times T 3  and T 4 , the access request from the transfer originator C to the transfer destination  2  is executed. 
         [0099]    At the time T 4 , transfer complete notices are issued to all the transfer originators, and since the transfer originator C is waiting for the largest number of transfer complete notices, the system arbiters  55  and  56  control the transfer complete notice arbiters so as to send the transfer complete notice to the transfer originator C the most priorly. 
         [0100]    In a period between the times T 4  and T 5 , the transfer complete notices are sent in the order of the transfer originator C, the transfer originator A and the transfer originator B, and the transfer originator C issues one transfer information item to the transfer destination  1  after receiving the transfer complete notice from the transfer destination  2 . 
         [0101]    At the time T 5 , the access requests of all the transfer originators have been completed. 
         [0102]    In a period between the times T 5  and T 6 , a transfer complete notice from the transfer destination  1  is sent to the transfer originator C. 
         [0103]      FIG. 14  is a timing chart obtained when the same transfer as that shown in  FIG. 13  is performed in the information processing apparatus of Embodiment 4 (shown in  FIG. 8 ). 
         [0104]    As is understood from comparison between  FIGS. 13 and 14 , the exclusive transfer issued by the transfer originator C can be carried out without retrying in Embodiment 6, and therefore, the transfer efficiency of the system bus can be improved. 
       Embodiment 7 
       [0105]      FIG. 15  is a block diagram for schematically showing the architecture of an information processing apparatus according to Embodiment 7 of the invention. 
         [0106]    As shown in  FIG. 15 , the information processing apparatus of this embodiment has a system bus for connecting a plurality of transfer originator bus control units  1  through  3  for respectively sending transfer information and a plurality of transfer destination bus control units  4  and  5  for respectively receiving the transfer information to one another, and includes, in addition to the components of Embodiments 4 and 5, a circuit (sequential table)  58  for storing successive transfer information necessary for the contention control; buses  59  through  61  used for selecting and rewriting the sequential table  58  from the transfer originator bus control units  1  through  3 ; a system arbiter  62  for controlling all arbiters included in the SoC; a bus  63  for connecting the sequential table  58  to the system arbiter  62 ; buses  64  and  65  for respectively connecting the command arbiters  13  and  14  to the system arbiter  62 ; buses  66  and  67  for respectively connecting the write data control circuits  30  and  31  to the system arbiter  62 ; transfer complete notice arbiters  68  through  70  related to write complete notice and read information; and buses  71  through  73  for respectively connecting the transfer complete notice arbiters  68  through  70  to the system arbiter  62 . 
         [0107]    The operation of the information processing apparatus having the aforementioned architecture will now be described with reference to  FIG. 16 . 
         [0108]    In  FIG. 16 , a transfer originator slot corresponds to a three-stage buffer for storing precedent transfer information and a transfer destination slot corresponds to a three-stage buffer for storing precedent write complete notice information and read data notice information. Also, it is assumed that successive transfer information for executing transfer from a transfer originator is written in the sequential table  58 , that information of the sequential table  58  selected by a transfer originator is transmitted to the system arbiter  62  and that the command arbiters  13  and  14 , the write data control circuits  30  and  31  and the transfer complete notice arbiters  68  through  70  are controlled by the system arbiter  62 . 
         [0109]    At time T 1 , the transfer originator A issues two transfer information items to the transfer destination  1 , the transfer originator B issues two transfer information items to the transfer destination  1  and the transfer originator C issues two exclusive transfer information items to the transfer destination  1  and one transfer information item to the transfer destination  2 . Since the system arbiter  62  gives the highest priority to the transfer originator C in accordance with the sequential table  58 , one of the two transfer information items of the transfer originator C is sent to the transfer destination  1  with no contention latency. 
         [0110]    In a period between the times T 1  and T 2 , the system arbiter  62  executes the transfer in the order of the transfer originator A, the transfer originator B and the transfer originator C in accordance with the sequential table  58 , and transfer complete notices are also sent in accordance with the sequential table  58  with no contention latency. 
         [0111]    Also in a period between the times T 2  and T 5 , the command arbiters  13  and  14 , the write data control circuits  30  and  31  and the transfer complete notice arbiters  68  through  70  are controlled in a similar manner in accordance with the sequential table  58  selected by each transfer originator, so that the transfer can be controlled without grasping the states of the buses included in the SoC. 
         [0112]    As is understood from comparison between  FIGS. 16 and 9 , the transfer between a transfer originator and a transfer destination can be executed with no contention latency in Embodiment 7, and therefore, the transfer efficiency of the system bus can be improved. 
       Embodiment 8 
       [0113]      FIG. 17  is a block diagram for schematically showing the architecture of an information processing apparatus according to Embodiment 8 of the invention. 
         [0114]    As shown in  FIG. 17 , the information processing apparatus of this embodiment has a system bus for connecting a plurality of transfer originator bus control units  1  through  3  for respectively sending transfer information and a plurality of transfer destination bus control units  4  and  5  for respectively receiving the transfer information to one another, and includes, in addition to the components of Embodiment 7, a bus clock information circuit  74 ; a high-speed bus region  75  operated with a high-speed clock; buses  76  through  78  for respectively connecting the transport originator bus control units  1  through  3  to the high-speed bus region  75 ; an intermediate-speed bus region  79  operated with an intermediate-speed clock; a low-speed bus region  80  operated with a low-speed clock; a bus  81  for connecting the high-speed bus region  75  to the intermediate-speed bus region  79 ; a bus  82  for connecting the intermediate-speed bus region  79  to the low-speed bus region  80 ; a bus  83  for connecting the low-speed bus region  80  to the transfer destination bus control unit  4  (the transfer destination  1 ); and a bus  84  for connecting the high-speed bus region  75  to the transfer destination bus control unit  5  (the transfer destination  2 ). 
         [0115]    The operation of the information processing apparatus having the aforementioned architecture will now be described with reference to  FIG. 18 . 
         [0116]    In  FIG. 18 , a transfer originator slot corresponds to a three-stage buffer for storing precedent transfer information and a transfer destination slot corresponds to a three-stage buffer for storing precedent write complete notice information and read data notice information. Also, it is assumed that successive transfer information for executing transfer from a transfer originator is written in the sequential table  58 , that information of the sequential table  58  selected by a transfer originator is transmitted to the system arbiter  62  and that the command arbiters  13  and  14 , the write data control circuits  30  and  31  and the transfer complete notice arbiters  68  through  70  are controlled by the system arbiter  62 . Furthermore, it is assumed that the system arbiter  62  includes the bus clock information circuit  74  so as to use bus clock information for the contention control. 
         [0117]    In a period between times T 1  and T 3 , the transfer originator A issues three transfer information items to the transfer destination  1  and three transfer information items to the transfer destination  2 . The system arbiter  62  sends transfer information of the transfer originator A to the transfer destinations  1  and  2  in accordance with the sequential table  58 . 
         [0118]    In a period between times T 3  and T 5 , in the case where a plurality of transfer complete notices from the transfer destinations  1  and  2  are simultaneously issued, the priority for the transfer complete notices simultaneously issued is assigned on the basis of precedent issue transfer information and bus clock information by using information of a transfer destination to swiftly return a transfer complete notice and a transfer destination to slowly return a transfer complete notice. Accordingly, the transfer complete notice is priorly sent from the transfer destination  1  to slowly return the transfer complete notice. 
         [0119]      FIG. 19  is a timing chart obtained when the same transfer as that shown in  FIG. 18  is performed in the conventional information processing apparatus (shown in  FIG. 22 ). 
         [0120]    As is understood from comparison between the  FIGS. 18 and 19 , the priority is given to a transfer destination to slowly issue a transfer complete notice in Embodiment 8, and hence, the throughput of each transfer originator can be improved. 
       Embodiment 9 
       [0121]      FIG. 20  shows an information processing apparatus of this embodiment obtained by additionally providing, in the information processing apparatus of Embodiment 8, system arbiters  85  and  86  each including a bus clock information circuit the same as that included in the high-speed bus region  75  respectively in the intermediate-speed bus region  79  and the low-speed bus region  80 , and providing buses  87  and  88  for connecting the system arbiters  62 ,  85  and  86  of the respective bus regions to each other. 
         [0122]    According to this embodiment, the same effect as that of Embodiment 8 can be attained, and in addition, the transfer efficiency can be improved with all the high-speed bus region  75 , the intermediate-speed bus region  79  and the low-speed bus region  80 . 
       Embodiment 10 
       [0123]      FIG. 21  shows an information processing apparatus of this embodiment obtained by additionally providing, in the information processing apparatus of Embodiment 9, a transfer destination  91  corresponding to an external memory, a transfer destination  92  corresponding to an external communication processing unit and buses  89  and  90  for respectively connecting the whole system  93  of Embodiment 9 to the transfer destinations  91  and  92 . 
         [0124]    According to this embodiment, the same effect as that of Embodiment 9 can be attained, and the transfer efficiency of the SoC system bus including accesses to the outside of the SoC can be improved. 
         [0125]    As described so far, the information processing apparatus of this invention includes a system arbiter used for batch management of the contention control of a SoC bus, and therefore, the invention is useful for improving the transfer efficiency of the whole SoC bus and the transfer efficiency of every transfer originator.