Abstract:
Scan chain routing efficiency is improved in an integrated circuit (IC) such as an application specific integrated circuit (ASIC) by defining flip flop groupings prior to place and route. A flip flop grouping specifies the arrangement of multiple flip flops and the scan chain routing through those flip flops. The predetermined flip flop arrangement of the flip flop grouping then prevents undesirable flip flop placements during place and route. The flip flop grouping therefore minimizes the layout impacts of scan insertion while simplifying the place and route process. Different flip flop groupings can be used in a single IC design, and flip flop groupings can be combined with individual flip flops in the IC layout. A flip flop grouping can include control logic for the flip flops. Clock gating logic can be offloaded from the flip flops into the control logic to further improve layout efficiency.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The invention relates to programmable logic devices, and in particular a method and structure for increasing chip area efficiency and power savings in scan chain implementations.  
           [0003]    2. Brief Description of Prior Art  
           [0004]    Design for testability (DFT) is a key method for enhancing the testability of an IC, such as an application specific integrated circuit (ASIC). DFT typically involves replacing the flip flops in an ASIC with scan-testable flip flops, or “scan flops”. A scan flop is generally a flip flop having a multiplexed input, which allows the input of the flip flop to be switched between test data and actual data. The scan flops are daisy chained into a long shift register-like structure via their test inputs. This “scan chain” allows predetermined data strings to be shifted into the flip flops for testing purposes.  
           [0005]    The scan chain is typically defined by synthesis tools during the pre-layout stage of the ASIC design process. Therefore, when the resulting netlist is converted into a physical layout during a subsequent place and route operation, sequentially connected scan flops in the scan chain may actually be placed far apart from one another in the physical layout.  
           [0006]    For example, FIG. 1 shows a schematic diagram of a conventional ASIC  100  including scan flops  101 ,  102 ,  103 ,  104 ,  105 ,  106 ,  107 , and  108 , which are sequentially connected in a scan chain. Each of scan flops  101 - 108  includes clock input terminal CLK, a data input terminal D, a test enable terminal TE, a reset terminal R, a test input terminal TI, and an output terminal Q. Only the connections between the output terminal Q and test input terminal TI of consecutive scan flops in the scan chain are depicted for clarity. The scan chain formed by scan flops  101 - 108  allow test data Tin to be scanned into each of the flip flops, and allows test data Tout to be shifted out of each of the flip flops to test the functionality of ASIC  100 .  
           [0007]    The specific positions of scan flops  101 - 108  represent a place and route solution meeting the functional timing requirements of the ASIC. However, because the particular arrangement does not place the scan flops in their scan chain order, complex interconnect paths must be made to form the scan chain. Such convoluted interconnect layouts increase overall chip size and also can reduce chip speed. Also, the scan chain interconnects can interfere with, and therefore substantially complicate, the routing of other ASIC interconnects. In addition, since power-saving clock gating logic is incorporated into the ASIC design prior to place and route, the lengthy wires created by the scan chain can increase the effective load seen by the clock gating cells, thereby making it difficult to control clock insertion delay and skew.  
           [0008]    Scan chains can be reordered during place and route to reduce layout inefficiency. Such reordering undesirably increases the complexity of the place and route operation, and also increases the time required for place and route. In addition, the reordering of scan chains typically requires that additional buffer cells be added to the design to maintain proper device timing and load handling. When clock gating logic is added, the place and route scripts become even more complex, and many iterations are required to control clock insertion delay and clock skew.  
           [0009]    Accordingly, it is desirable to provide a structure and method for increasing scan chain efficiency while minimizing place and route complexity and improving control over clock skew.  
         SUMMARY OF THE INVENTION  
         [0010]    By grouping multiple flip flops into a predefined “flip flop grouping” that defines the physical arrangement of the flip flops and a scan chain path, the invention prevents the haphazard scan chain routing implemented by conventional IC design processes that merely define the scan chain path. Because the flip flop grouping specifies the physical arrangement of the flip flops (and any associated control logic), the elements of the flip flop grouping can be optimized for layout efficiency. Any number of flip flops can be incorporated into a flip flop grouping, and flip flop groupings can be combined with individual flip flops in an IC, based on design requirements and goals.  
           [0011]    According to an embodiment of the invention, the flip flop grouping can be specified as a single-entity (standard) cell within a cell library, which not only simplifies place and route operations, and also allows an efficient scan chain to be incorporated into the prelayout netlist by synthesis tools.  
           [0012]    According to an embodiment of the invention, a flip flop grouping can comprise standard scan flops with predefined scan chain interconnects. According to another embodiment of the invention, a flip flop grouping can include control logic to provide scan capability with or without clock gating. Such control logic can allow the flip flops in the flip flop grouping to be modified to minimize layout area consumption, improve performance, reduce setup time, and reduce power consumption. Furthermore, by incorporating the scan/clock gating logic for multiple flip flops into the control logic, layout area requirements for the flip flop grouping can be significantly reduced. According to an embodiment of the invention, clock skew for the flip flops in a flip flop grouping can be minimized by arranging the flip flops around the control logic so that the clock signal is evenly distributed to all the flip flops.  
           [0013]    The present invention will be more fully understood in view of the following description and drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]    [0014]FIG. 1 is a schematic diagram of an ASIC including a conventional scan chain layout.  
         [0015]    [0015]FIG. 2 is a schematic diagram of an IC including a scan module in accordance with an embodiment of the invention.  
         [0016]    [0016]FIG. 3 is a schematic diagram of a flip flop grouping, in accordance with an embodiment of the invention.  
         [0017]    [0017]FIG. 4 is a schematic diagram of a control logic circuit for a flip flop grouping, in accordance with an embodiment of the invention.  
         [0018]    [0018]FIG. 5 is a schematic diagram of a space-efficient flip flop for use in a flip flop grouping, in accordance with an embodiment of the invention. 
     
    
     DETAILED DESCRIPTION  
       [0019]    The invention provides enhanced IC layout efficiency by predefining a group of scan chained flip flops that are treated as a single unit during place and route, thereby minimizing the effects of scan chain routing inefficiency. FIG. 2 shows an IC  200  that includes a flip flop grouping  210  in accordance with an embodiment of the invention. Flip flop grouping  210  comprises a set of flip flops  211 ,  212 ,  213 ,  214 ,  215 ,  216 ,  217 , and  218 , and optional built-in control logic  219 . Flip flops  211 - 218  are daisy chained (as indicated by the dotted arrow) between an input scan terminal Sin 1  and an output scan terminal Sout 1  in a scan chain configuration (i.e., the data output and the test input of successive flip flops are connected). This “partial scan chain” can then be incorporated into the full scan chain for IC  200 . Note that while flip flop grouping  210  (and flip flop grouping  220 , described below) is depicted as an 8-bit flip flop grouping (i.e., including eight flip flops) for explanatory purposes, the invention can be used with any grouping of two or more flip flops.  
         [0020]    By specifying the physical arrangement of flip flops  211 - 218  in flip flop grouping  210 , the scan chain routing between those flip flops (and any associated control logic) can be optimized and maintained throughout the IC design process. Since flip flop grouping  210  is treated a single entity (i.e., the predefined arrangement of flip flops  211 - 218  is maintained), the optimized scan chain routing is retained over the course of place and route and into the final IC layout. Flip flop grouping  210  can be part of a full scan chain with other flip flop groupings such as flip flop grouping  220 , and/or other individual flip flops such as flip flop  201 , thereby allowing test data Tin to be loaded into all the flip flops of IC  200  (and allowing test data Tout to be read out from those same flip flops). Flip flop grouping  220  can comprise another instance (or instances) of flip flop grouping  210 , or can represent a different flip flop grouping (i.e., different arrangement, flip flop quantity, etc.). Individual flip flop  201  can comprise any type of flip flop that can be incorporated into a scan chain, including conventional scan flops such as scan flops  101 - 108 , described with respect to FIG. 1. For clarity, only the scan chain connections are depicted in FIG. 2. Note that a full scan chain can include any number and order of flip flop groupings and individual flip flops, as indicated by the dashed lines around flip flop grouping  220  and individual flip flop  201 . The specific combination and arrangement of flip flop groupings and individual flip flops will depend on the specific requirements of the ASIC design. Note further that flip flop groupings having different numbers of flip flops can be used in a single ASIC.  
         [0021]    Flip flop grouping  220  includes flip flops  221 ,  222 ,  223 ,  224 ,  225 ,  226 ,  227 , and  228 , and optional built in control logic  229 . Flip flops  221 - 228  are daisy chained between an input scan terminal Sin 2  and an output scan terminal Sout 2  to form a partial scan chain (indicated by the dotted arrow). By connecting scan output terminal Sout 1  of flip flop grouping  210  with scan input terminal Sin 2  of flip flop grouping  220 , a scan chain formed from flip flops  211 - 218  and  221 - 228  can be formed. The only routing required to form this scan chain is the connection between scan output terminal Sout 1  and scan input terminal Sin 2 . Accordingly, the resulting scan chain can be very space-efficient, using short wiring runs and minimal buffer insertions due to the layout optimization that can be implemented within flip flop groupings  210  and  220 . In this manner, long, efficient scan chains can be easily implemented in an IC. Note that while flip flops  221 - 228  are shown surrounding control logic  229  for explanatory purposes, the flip flops and control logic in a flip flop grouping can have any specified arrangement.  
         [0022]    According to various embodiments of the invention, flip flops  211 - 218  of flip flop grouping  210  can comprise standard scan flops or even non-scan flip flops that provide the desired scan capability via control logic  219 . However, layout efficiency can often be improved even more by optimizing the flip flops for group arrangement and operation. A standard scan flop cell (i.e., a standard scan flop in a cell library) typically includes integrated scan logic. A flip flop grouping made up of such standard scan cells could provide efficient scan routing, but it could also consume more die area than necessary due to redundancies in the scan logic for each cell. Accordingly, by centralizing control in control logic  219 , additional layout efficiency can be realized.  
         [0023]    For example, FIG. 3 shows an 8-bit flip flop grouping  300  according to an embodiment of the invention. Flip flop grouping  310  can be defined in a cell library so that it can be readily incorporated into an IC design. Flip flop grouping  310  includes flip flops  311 ,  312 ,  313 ,  314 ,  315 ,  316 ,  317 , and  318 , and control logic  319 . Each of flip flops  311 - 318  includes a clock terminal CLf, a data input terminal D, an input enable terminal ENf, a test enable terminal TEf, a master reset terminal MR, a slave reset terminal SR, a test input terminal TI, and an output terminal Q. The input terminal D of each of flip flops  311 - 318  is coupled to receive input data D 1 -D 8 , respectively. Note that according to other embodiments of the invention, flip flops  311 - 318  can include complementary inputs/outputs to improve switching speed and reduce the overall layout area of the flip flop. Note that by surrounding control logic  319  with flip flops  311 - 318 , connections between control logic  319  and flip flops  311 - 318  can be efficiently made, although various other arrangements are possible.  
         [0024]    Each of flip flops  311 - 318  is a scan flop, and therefore data is loaded from either data input terminal D or test input terminal TI at each local clock pulse C at clock terminal CLf. During normal operation, a data enable signal Db is asserted at input enable terminal ENf, so that regular (i.e., non-test) data is loaded from data input terminal D. During testing operations, a test enable signal Tb is asserted at test enable terminal TEf, so that test data is loaded from test input terminal TI. Master reset terminal MR and slave reset terminal SR reset master and slave latches, respectively, within the flip flop (for example, as described in detail below with respect to FIG. 5) in response to master reset signal M and slave reset signal S, respectively.  
         [0025]    Flip flops  311 - 318  are daisy chained to form a partial scan chain between a scan input terminal Sin and a scan output terminal Sout, with the output terminal Q being connected to the input terminal TI between successive flip flops. Test input terminal TI of flip flop  311  is connected to scan input terminal Sin, while output terminal Q of flip flop  318  is connected to scan output terminal Sout. Therefore, test data Tin can be scanned into the partial scan chain via scan input terminal Sin, while test data Tout can be read from scan output terminal Sout.  
         [0026]    The behavior of flip flops  311 - 318  during both normal and test operations is controlled by control logic  319 , which includes a clock input terminal CP, a data enable terminal EN, a test enable terminal TE, a reset terminal RN, a clock output terminal CLc, a data control terminal ENc, a test control terminal TEc, a master reset control terminal Mc, and a slave reset control terminal Sc. In response to a system clock signal CLOCK at a clock input terminal CP, control logic signal generates local clock signal C for each of flip flops  311 - 318 . During normal operation, a data control signal Dc is asserted at data enable terminal EN, control logic  319  asserts data enable signal Db so that data at the data input terminal D of each flip flop is loaded on every local clock pulse C. On the other hand, during test mode a test control signal Tc is asserted at test enable terminal TE, control logic  319  asserts test enable signal Tb so that test data can be loaded into and/or read out of the partial scan chain formed by flip flops  311 - 318 .  
         [0027]    Control logic  319  can also provide consolidated clock gating control for flip flops  311 - 319  so that such circuitry can be eliminated from each flip flop. For example, control logic  319  can disable local clock signal C at clock output terminal CLc when both data control signal Dc and test control signal Tc are deasserted, thereby preventing activity and minimizing power consumption in flip flops  311 - 318 . In this manner, a single clock gating circuit in control logic  319  can replace multiple clock gating circuits that would otherwise be added during the place and route step for each of flip flops  311 - 318 .  
         [0028]    Finally, the state of a reset signal RS at reset control terminal RN controls the states of master reset signal M and slave reset signal S. During non-reset operations, reset signal RS is deasserted, and control logic  319  deasserts master reset signal M and slave reset signal S. To perform a reset operation on the flip flops associated with control logic  319 , reset signal RS is asserted at reset terminal RN, and in response, control logic  319  asserts master reset signal M and slave reset signal S at master reset control terminal Mc and slave reset control terminal Sc, respectively. Note that while the reset operation of flip flops are described herein using a reset signal that includes discrete master and slave reset signals, according to various other embodiments of the invention, the invention can be applied to flip flops that are reset by a single reset signal.  
         [0029]    [0029]FIG. 4 shows a schematic diagram of a control logic circuit  419 , which represents an implementation of control logic  319  (described with respect to FIG. 3), according to an embodiment of the invention. Control logic circuit  419  includes a clock input terminal CP, a data enable terminal EN, a test enable terminal TE, a reset terminal RN, a clock output terminal CLc, a data control terminal ENc, a test control terminal TEc, a master reset control terminal Mc, and a slave reset control terminal Sc, which correspond to the similarly labeled terminals of control logic  319  in FIG. 3. Control logic circuit further includes a complementary clock output terminal /CLc, a complementary data control terminal /ENc, a complementary test control terminal /TEc, a clock gating circuit  410 , NOR gates  421  and  422 , NAND gates  431  and  432 , inverters  441 ,  442 ,  443 ,  444 , and  445 .  
         [0030]    Clock gating for any flip flops associated with control logic circuit  419  is provided by clock gating circuit  410 . Clock gating circuit  410  includes a data clock enable input Dclk that is connected to data enable terminal EN, a test clock enable input Tclk that is connected to test enable terminal TE, a clock pulse input CPin that is connected to clock input terminal CP, and a clock pulse output CPout that is connected to clock output terminal CLc. When data control signal Dc is asserted at data enable terminal EN or test control signal Tc is asserted at test enable terminal TE, clock gating circuit  410  uses a system clock signal CLOCK coupled to clock input terminal CP to provide a local clock signal CK to clock output terminal CLc. Note that while local clock signal CK will be described as tracking (i.e., directly following, with matching clock pulses) system clock signal CLOCK for explanatory purposes, according to other embodiments of the invention, local clock signal CK can follow system clock signal CLOCK but be inverted, or local clock signal CK can have a pattern that does not follow system clock signal CLOCK at all. Inverter  444  connected between clock pulse output CPout and complementary clock output terminal /CLc inverts local clock signal CK to provide a complementary local clock signal CK_NOT at complementary clock output terminal /CLc. When neither data control signal Dc nor test control signal Tc is asserted, clock gating circuit  410  holds clock pulse output CPout at a fixed level to halt the operation of any flip flops that are clocked by local clock signal CK and complementary local clock signal CK_NOT.  
         [0031]    The states of data control signal Dc and test control signal Tc at data enable EN and test enable terminal TE, respectively, also determine the behavior of the flip flops associated with control logic circuit  419 . Data enable terminal EN is connected to one input of NAND gate  431 , while inverter  441  connects test input terminal TE and the other input of NAND gate  431 . The output of NAND gate  431  is connected to one input of NOR gate  422 , while clock input terminal CP is connected to the other input of NOR gate  422 . The output of NOR gate  422  is connected to data control terminal ENc to provide data enable signal Db, while inverter  443  connects the output of NOR gate  422  with complementary data control terminal /ENc to provide complementary data enable signal Db_NOT.  
         [0032]    When data control signal Dc is deasserted, the output of NAND gate  431  is logic HIGH, which forces the output of NOR gate  422  to a logic LOW state, regardless of the state of test control signal Tc and system clock signal CLOCK. However, when data control signal Dc is asserted while test control signal Tc is deasserted, the output of NAND gate  431  becomes a logic LOW output. The output of NOR gate  422  therefore is driven by the state of system clock signal CLOCK, so that data enable signal Db is simply the inverse of system clock signal CLOCK and complementary data enable signal Db tracks system clock signal CLOCK. The functional behavior of a flip flop having master and slave latches could then be controlled by this data enable signal Db (and local clock signal CK) as described below with respect to FIG. 5.  
         [0033]    Meanwhile, the output of inverter  441  is also connected to an input of NOR gate  421 . Clock input terminal CP is connected to the other input of NOR gate  421 , and the output of inverter  441  is connected to test control terminal TEc to provide test enable signal Tb. Inverter  442  is connected between the output of NOR gate  421  and complementary test control terminal /TEc to provide complementary test enable signal Tb_NOT. Therefore, when test control signal Tc at test input terminal TE is deasserted, inverter  441  provides a logic HIGH signal to NOR gate  421 , which forces test enable signal Tb to a logic LOW state (and complementary test enable signal Tb_NOT to a logic HIGH state), regardless of the state of system clock signal CLOCK. However, when test control signal Tc is asserted, inverter  441  provides a logic LOW signal to NOR gate  421 , so that the output of NOR gate  421  is driven by the state of system clock signal CLOCK. Therefore, when test control signal Tc is asserted, test enable signal Tb is simply the inverse of system clock signal CLOCK, while complementary test enable signal Tb_NOT tracks system clock signal CLOCK. The functional behavior of a flip flop having master and slave latches could then be controlled by this test enable signal Tb (and local clock signal CK) as described below with respect to FIG. 5.  
         [0034]    The state of reset signal RS at reset terminal RN controls the state of master reset signal M at master reset control terminal Mc and the state of slave reset signal S at slave reset control terminal Sc. Reset signal RS is an active LOW signal, and is maintained in a logic HIGH state during non-reset operations. Inverter  445  connects reset terminal RN with slave reset control terminal Sc, so that a logic HIGH signal at reset terminal RN holds slave reset signal S at slave reset control terminal Sc at a logic LOW level. Then, when reset signal RS is asserted (to a logic LOW state since reset signal RS is active LOW), slave reset signal S is asserted (to a logic HIGH state).  
         [0035]    Meanwhile, the output of inverter  445  is also connected to an input of NAND gate  432 , which has its output connected to master reset control terminal Mc by inverter  446 . The other input of NAND gate  432  is coupled to receive system clock signal CLOCK. Therefore, while reset signal RS is deasserted (logic HIGH), the output of inverter  445  is at a logic LOW state, and the output of NAND gate  432  is maintained at a logic HIGH state, regardless of the state of system clock signal CLOCK. Inverter  446  then inverts the output of NAND gate  402 , so that master reset signal M, is held at a logic LOW level while reset signal RS is deasserted. When reset signal RS is asserted (logic LOW), the output of inverter  445  is shifted to a logic HIGH, so that the output of NAND gate  432  is the inverse of system clock signal CLOCK, and master reset signal M therefore tracks system clock signal CLOCK. Note that while the operation of control logic circuit  419  is described with respect to an active LOW reset signal, according to other embodiments of the invention, reset signal RS could be an active HIGH signal.  
         [0036]    [0036]FIG. 5 shows a space-saving and reduced setup time flip flop  500  for a predefined flip flop grouping in accordance with an embodiment of the invention. Flip flop  500  can be used for flip flops  311 - 318  described with respect to FIG. 3. Flip flop  500  includes a clock terminal CLf, a complementary clock terminal /CLf, a data input terminal D, a test input terminal TI, an input enable terminal ENf, a complementary input enable terminal /ENf, a test enable terminal TEf, a complementary test enable terminal /TEf, a master reset terminal MR, a slave reset terminal SR, inverters  511 ,  512 ,  513 ,  514 ,  515 , and  516 , a pass inverter  531 , complementary metal-oxide-semiconductor (CMOS) pass gates  521 ,  522 ,  523 , and  524 , pass n-type metal-oxide-semiconductor (NMOS) pass transistors  541  and  542 , and an output terminal Q. Clock terminal CLf, complementary clock terminal /CLf, data input terminal D, test input terminal TI, input enable terminal ENf, complementary input enable terminal /ENf, test enable terminal TEf, complementary test enable terminal /TEf, master reset terminal MR, and slave reset terminal SR are coupled to receive local clock signal CK, complementary local clock signal CK_NOT, regular (non-test) data Dn, test data Tn, data enable signal Db, complementary data enable signal Db_NOT, test enable signal Tb, complementary test enable signal Tb_NOT, master reset signal M, and slave reset signal S, respectively, which are described above with respect to FIG. 4.  
         [0037]    Data input terminal D is connected to the input of inverter  511 , while test input terminal TI is connected to the input of inverter  512 . The output of inverter  511  is connected to the input of CMOS pass gate  521 , which has its enable terminal connected to input enable terminal ENf and its complementary enable terminal connected to complementary input enable terminal /ENf. Therefore, while data enable signal Db is in a logic LOW state (and complementary data enable signal /Db is logic HIGH), CMOS pass gate  521  is turned off and does not pass the output of inverter  511 . When data enable signal Db switches to logic HIGH (and complementary data enable signal Db_NOT goes logic LOW), CMOS pass gate  521  is turned on and pass the output of inverter  511 . In a similar manner, the output of inverter  512  is connected to the input of CMOS pass gate  522 , which has its enable terminal connected to test enable terminal TEf and its complementary enable terminal /TEf. When test enable signal Tb is in a logic LOW state (and complementary test enable signal Tb_NOT is logic HIGH), CMOS pass gate  522  is turned off and does not pass the output of inverter  512 . When test enable signal Tb is switched to a logic HIGH state (and complementary test enable signal Tb_NOT goes to a logic LOW), CMOS pass gate  522  is turned on and pass the output of inverter  511 . In this manner, data input via data input terminal D is enabled by asserting data enable signal Db, while test data input via test input terminal TI is enabled by asserting test enable signal Tb.  
         [0038]    The input data is then passed to a master latch formed by inverters  513  and pass inverter  531 . The outputs of CMOS pass gates  521  and  522  are connected to the input of inverter  513 , which has its output connected to the input of pass inverter  531 . The output of pass inverter  531  is connected to the input of inverter  513  to complete the master latch. The enable terminal of pass inverter  531  is connected to clock terminal CLf, while the complementary enable terminal of pass inverter  531  is connected to complementary clock terminal /CLf. Therefore, pass inverter  531  is enabled during the logic HIGH pulses of local clock signal CK. As described previously with respect to FIG. 4, data enable signal Db and test enable signal Tb also follow local clock signal CK, but are asserted on negative clock pulses, so during the negative (logic LOW) portions of local clock signal CK, data from either inverter  511  or  512  is passed by CMOS pass gate  521  or  522 , respectively, to the input of inverter  513 . Then, when local clock signal CK switches to a logic HIGH state, CMOS pass gates  521  and  522  are turned off, isolating inverter  513  from both inverters  511  and  512 , while pass inverter  531  is turned on to latch the data into the master latch.  
         [0039]    CMOS pass gate  523  connects the master latch formed by inverters  513  and  531  to a slave latch formed by inverters  514  and  515  and CMOS pass gate  524 . The output of inverter  514  is connected to the input of inverter  515 , which in turn has its output connected to the input of CMOS pass gate  524 . The output of CMOS pass gate  524  is connected to the input of inverter  514  to complete the slave latch. CMOS pass gate  524  has its enable terminal connected to complementary clock terminal /CLf and its complementary enable terminal connected to clock terminal CLf. Meanwhile, the enable terminal of CMOS pass gate  523  is connected to clock terminal CLf, while the complementary enable terminal of CMOS pass gate  523  is connected to complementary clock terminal /CLf. Therefore, when local clock signal CK is in a logic HIGH state, CMOS pass gate  524  is off as CMOS pass gate  523  passes the data latched in the master latch to the input of inverter  514 . Then, when local clock signal CK switches to a logic LOW state, CMOS pass gate  523  turns off, isolating the slave latch from the master latch, and CMOS pass gate  524  turns on, latching the data into the slave latch. The output of inverter  514  is connected to the input of inverter  516 , which inverts the data stored in the slave latch and passes this data to output terminal Q, thereby providing the output data Qj from flip flop  500 .  
         [0040]    NMOS pass transistors  541  and  542  provide reset functionality to flip flop  500 . NMOS pass transistor  541  is connected between the input of pass inverter  531  and ground, with its control terminal connected to master reset terminal MR, while NMOS pass transistor  542  is connected between the input of inverter  514  and ground, with its control terminal connected to slave reset terminal SR. Therefore, when master reset signal M is asserted at master reset terminal, NMOS pass transistor  541  is turned on, and the input of pass inverter  531  is pulled to ground, thereby forcing the master latch to store a logic LOW. As described previously with respect to FIG. 4, when master reset signal M is asserted, slave reset signal is concurrently asserted, so NMOS pass transistor  542  is also turned on. This pulls the input of inverter  514  to ground, thereby forcing the slave latch to store a logic HIGH. In this manner, flip flop  500  can be reset, such that output terminal Q will provide a logic LOW output immediately after the reset operation. Note that according to other embodiments of the invention, flip flop  500  can be set/reset to provide logic HIGH/LOW outputs immediately after the set/reset operations).  
         [0041]    In this manner, the invention enables the implementation of layout-efficient scan chains that can minimize setup time while improving performance and reducing power consumption. The space-saving flip flop  500  shown in FIG. 5 and control logic circuit  419  shown in FIG. 4 allow a flip flop grouping such as flip flop grouping  310  shown in FIG. 3 to be implemented using only the metal- 1  and metal- 2  layers of an IC. This in turn can reduce congestion during place and route operations, as the metal- 3  layer can be freely used during place and route to provide the most efficient interconnect routing. The various embodiments of the structures and methods of this invention that are described above are illustrative only of the principles of this invention and are not intended to limit the scope of the invention to the particular embodiments described. Thus, the invention is limited only by the following claims and their embodiments.