Abstract:
A chip with I/O pads on the peripheries and a method making the chip is disclosed. The chip includes: a substrate; at least two metal layers, formed above the substrate, each metal layer forming a specific circuit, wherein two adjacent metal layers are separated by an inter-metal dielectric layer; and a passivation layer, formed on a top side of the chip. By changing the I/O pad from the top of the chip to the peripheries, the extra thickness of the packaged chip caused by wire bonding in the prior arts can be reduced.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to a chip with I/O pads and a method to manufacture it. More particularly, the present invention relates to a chip with I/O pads on the peripheries of the chip and a method to manufacture it. 
       BACKGROUND OF THE INVENTION 
       [0002]    With the development of Integrated Circuit (IC) manufacturing processes, new packaging methods have been invented and applied to a variety of IC products. For example, Fine-Pitch Ball Grid Array (FPBGA) technology is used for most logic ICs while Thin Small Outline Package (TSOP) remains the main stream of memory packages. To choose a proper packaging type for a IC product, a designer should take the application into consideration, i.e. numbers of I/O signals, frequency, operation temperature, space, cost, etc. 
         [0003]    However, popular packaging methods may not apply to special cases that may require particular geometry or physical requirement. For instance, a photo sensor or a capacitive fingerprint sensor IC needs to have the sensing area exposed for picking up light or electrical energy. Therefore, a commonly used packaging type would have a sealing material over only the non-sensing area, including the wire-bonded pads, and leave the sensing area exposed to the environment as shown in  FIG. 1 .  FIG. 1  shows a cross-sectional structure of a fingerprint sensor package. The fingerprint sensor package mainly includes a substrate  11 , a fingerprint sensing chip  12 , a number of bonding wires  13  and a sealing material  14 . An active surface  21  of the fingerprint sensing chip  12  has a sensing region  23  formed thereon. The back of the fingerprint sensing chip  12  is adhered to a top surface  11   a  of the substrate  11 . The fingerprint sensing chip  12  is electrically connected to the substrate  11  with the bonding wires  13 . The sealing material  14  is formed on the top surface  11   a  of the substrate  11  to seal the bonding wires  13  and the non-sensing portion of the fingerprint sensing chip  12 . The sensing region  23  must be exposed. There are several bumps  15  formed on a bottom surface  11   b  of the substrate  11  as signal connectors to receive power and to electrically communicate with external circuitry. 
         [0004]    It is clear from  FIG. 1  that a protrusion height H of sealing material  14 , including a height h of bonding wires  13  and that of bonding material for covering the wires, cannot be avoided. When portable devices, such as a smart phone or smart card, which carry the fingerprint sensing chip  12  become more compact and slim than ever, the protrusion height H is preferred to be eliminated so that the surface of portable devices can be perfectly flat. 
         [0005]    Flip Chip assembly is another popular packaging method whose package size is smaller than a traditional carrier-based package. However, for a contact image sensor or a capacitive fingerprint sensor IC which may require both a compact package and a flat contact surface, flip chip assembly may not suitable. A typical flip chip assembly is shown in  FIG. 2 . Attachment pads  2  of a chip  1  and contact pads  5  on a PCB  4  are electrically connected using solder balls  3 , and an electrically-insulating adhesive  6  is then underfilled to provide a stronger mechanical connection. A surface level difference H′ between the upper surface of the chip  1  and the upper surface of the PCB  4 , which is the sum of the height of the chip h 1  and that of the solder balls h 2 , makes a flat top surface of the package impossible. 
         [0006]    Besides the technologies mentioned above, another technology involves chip-scale packaging is disclosed by U.S. Pat. No. 8,736,080. U.S. Pat. No. 8,736,080 of ARNOLD et al. discloses a compact Integrated Circuit Assembly comprising: an integrated circuit, a substrate where the integrated circuit is disposed on, a conductive layer disposed in the signal trench and coupling to the integrated circuit signal pad, a bond wire configured to couple the conductive layer to an external pad. The substrate comprise at least one signal trench which proximate to an integrated circuit signal pad and extending to one edge of the substrate. The bond wire, the at least one signal trench and the conductive layer are formed below a surface plane of the integrated circuit. This method successfully reduces the height of the package, and also provides a flat top surface. However, the manufacture process, involving a deep etching step to form the trench and an additional metal plating step to form the conductive layer, requires more manufacture time and additional cost. 
         [0007]    Therefore, in order to solve the problem mentioned above, a chip with pads on the peripheries and a method to manufacture the chip is provided. The chip can be a fingerprint sensing chip, even a contact image sensor. 
       SUMMARY OF THE INVENTION 
       [0008]    This paragraph extracts and compiles some features of the present invention; other features will be disclosed in the follow-up paragraphs. It is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims. 
         [0009]    In order to settle the problems mentioned above, a chip with I/O pads on the peripheries is disclosed. The chip includes: a substrate; at least two metal layers formed above the substrate, each metal layer forming a specific circuit, wherein two adjacent metal layers are separated by an inter-metal dielectric layer; and a passivation layer, formed on a top side of the chip. a plurality of I/O pads are formed in at least one metal layer and on peripheries of the chip; a pad window is formed above the I/O pad or part of the I/O pad; a connecting space is formed at the pad window; a contact surface of the I/O pad is exposed through the pad window; a distance between the contact surface of the I/O pad and an external surface of the passivation layer is larger than a connecting depth. 
         [0010]    Preferably, the connecting depth is 3 μm or more. A side of the pad window extends to a saw street of a wafer where the chip is made before the chip was diced from the wafer. The chip is a fingerprint sensing IC (Integrated Circuit) and a sensing area is formed on a portion of the top side. 
         [0011]    According to another aspect of the present invention, a method to make a chip with I/O pads on the peripheries is disclosed. The method includes the steps of: providing a substrate; forming a lower metal layer above the substrate, which contains a specific circuit and a plurality of I/O pads; forming an inter-metal dielectric layer above the lower metal layer and a plurality of via openings therein; forming other metal layers, inter-metal dielectric layers and vias formed therein if needed; forming an upper metal layer above the last formed inter-metal dielectric layer, which contains a specific circuit; forming a passivation layer above the upper metal layer; deeply etching a plurality of pad windows to expose the I/O pads; and dicing the wafer along the saw streets of the wafer formed therein. Each metal layer forms a specific circuit. The I/O pads are formed on peripheries of the chip. A pad window is formed above the I/O pad or part of the I/O pad. A connecting space is formed at the pad window. A contact surface of the I/O pad is exposed through the pad window. A distance between a contact surface of the I/O pad and an external surface of the passivation layer is larger than a connecting depth. 
         [0012]    According to the present invention, another method to make a chip with I/O pads on the peripheries is disclosed. The method includes the steps of: providing a substrate; forming a lower metal layer above the substrate, which contains a specific circuit and a lower layer of each I/O pad; forming an inter-metal dielectric layer above the lower metal layer and a plurality of via openings therein; forming other metal layers, inter-metal dielectric layers and vias formed therein if needed; deeply etching a plurality of vias at the I/O pad locations; forming an upper metal layer above the last formed inter-metal dielectric layer, which contains a specific circuit; forming a passivation layer above the upper metal layer; etching a plurality of pad windows to expose the I/O pads; and dicing the wafer along the saw streets of the wafer formed therein. Each metal layer forms a specific circuit. The I/O pads are formed on peripheries of the chip. A pad window is formed above the I/O pad or part of the I/O pad. A connecting space is formed at the pad window. A contact surface of the I/O pad is exposed through the pad window. A distance between a contact surface of the I/O pad and an external surface of the passivation layer is larger than a connecting depth. The via at each I/O pad location forms a concave portion, and a portion of the upper metal layer formed at each pad location forms a stacked metal structure. The stacked metal structure electrically links the upper metal layer to the lower metal layer. The contact surface of the I/O pad is a top surface of the upper metal layer at the I/O pad location. 
         [0013]    By changing the I/O pad from the top of the chip to the peripheries of the chip and applying the conductive adhesive to electrically connect with external circuitry, the extra thickness of the packaged chip caused by wire bonding can be removed. And, a low-cost sensor chip assembly with a flat top surface can be achieved. It is a good solution for the problems mentioned above. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]      FIG. 1  shows a cross-sectional structure of a fingerprint sensor package using wire bounding method. 
           [0015]      FIG. 2  shows a cross-sectional structure of a flip chip package. 
           [0016]      FIG. 3  depicts a wafer with fingerprint sensing chips and saw streets formed thereon. 
           [0017]      FIG. 4  is a top view of one fingerprint sensing chip. 
           [0018]      FIG. 5  shows three cross sections of the I/O pad. 
           [0019]      FIG. 6  is a three dimensional view of the fingerprint sensing chip in a first embodiment. 
           [0020]      FIG. 7  is a perspective view of the I/O pad. 
           [0021]      FIG. 8  shows two I/O pads in adjacent fingerprint sensing chips cut along with the saw street. 
           [0022]      FIG. 9  is a three dimensional view of the fingerprint sensing chip in a second embodiment. 
           [0023]      FIG. 10  is a three dimensional view of the fingerprint sensing chip in a third embodiment. 
           [0024]      FIG. 11  is a flow chart of a method to making a chip of the first embodiment according to the present invention. 
           [0025]      FIG. 12  is a flow chart of a method to making a chip of the second embodiment according to the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0026]    The present invention will now be described more specifically with reference to the following embodiments. 
         [0027]    Please see  FIG. 3  to  FIG. 12 . Embodiments according to the present invention are described with reference thereto.  FIG. 3  depicts a wafer  100  and a number of fingerprint sensing chips  110  formed thereon. A saw street  120  is formed between two rows or columns of fingerprint sensing chips  110 . The saw street  120  is used to be cut out so that each fingerprint sensing chip  110  can be taken out. 
         [0028]    A top view of one fingerprint sensing chip  110  is shown in  FIG. 4 . The fingerprint sensing chip  110  has a sensing area  111 . The sensing area  111  is composed of an array of sensing units  1111 . Around the sensing area  111 , in peripheries of the fingerprint sensing chip  110 , there are a number of I/O pads  112 . Not like conventional fingerprint sensing chips, the I/O pads  112  are just formed at and aligned with the peripheries of the fingerprint sensing chip  110  according to the present invention. The I/O pads  112  are also located below the top surface of the fingerprint sensing chip  110  instead of being on the top surface of the fingerprint sensing chip  110 . For a better understanding of the structure of the I/O pads  112 , please refer to  FIG. 5 .  FIG. 5  shows three cross sections of the I/O pad  112  enclosed by a dashed frame on the right bottom of the fingerprint sensing chip  110  in  FIG. 4 . 
         [0029]    In  FIG. 5 , the three cross sections are obtained along an AA′ line, a BB′ line and a CC′ line, respectively. A three dimensional view around the I/O pad  112  of the fingerprint sensing chip  110  is shown in  FIG. 6 . It is obvious that the pad structure of the fingerprint sensing chip  110  comprises a substrate  100   a,  a lower metal layer  100   b,  an inter-metal dielectric layer  100   c,  an upper metal layer  100   d  and a passivation layer  100   e.  The passivation layer  100   e  is on the top side of the fingerprint sensing chip  110 . It should be noticed that one fingerprint sensing chip may have metal layers more than two layers around the I/O pads. The number of inter-metal dielectric layer will be increased accordingly (two adjacent metal layers are separated by one inter-metal dielectric layer). The structure of the fingerprint sensing chip  110  illustrated in the present embodiment is just for illustrative purpose. It is not to limit the applications of the present invention. According to the spirit of the present invention, there should be at least two metal layers. Each metal layer (the lower metal layer  100   b  or the upper metal layer  100   d ) forms a specific circuit. The lower metal layer  100   b  and the upper metal layer  100   d  may be interlinked in other portions of the fingerprint sensing chip  110  for signal transmission. 
         [0030]    In  FIG. 5  and  FIG. 6 , the two metal layers are not linked. It is clear from the cross sections along that AA′ line and the CC′ line that a portion of the lower metal layer  100   b  forms the I/O pad  112 . Please see  FIG. 7 . It is a perspective view of the I/O pad  112  enclosed in  FIG. 4 . The lower metal layer  100   b  has a number of traces  100   b ′. Each I/O pad  112  is just linked to one trace  100   b ′ and formed on peripheries of the fingerprint sensing chip  110 . A connecting space is formed above each I/O pad  112  at the pad window. Therefore, a portion of materials of the fingerprint sensing chip  110  above the I/O pad  112  are removed by etching a pad window above the I/O pad  112  or part of the I/O pad  112 . Namely, portions of the inter-metal dielectric layer  100   c  and the passivation layer  100   e  above the I/O pad  112  are removed. Thus, a distance D between a contact surface of the I/O pad  112  and an external surface of the passivation layer  100   e  (the topmost portion of the passivation layer  100   e ) exists. The distance D should be larger than a connecting depth. In practice, the connecting depth should be 3 μm or more. 
         [0031]    Please refer to  FIG. 8 .  FIG. 8  shows a three dimensional view of two I/O pads  112   a  and  112   b  in two adjacent fingerprint sensing chips  110   a  and  110   b,  respectively, and a saw street  120  thereinbetween. In order to form the I/O pads  112  that are exactly located at and aligned with the periphery of the fingerprint sensing chip  110 , according to the present invention, a side of the pad window should extend to the saw street  120  of the wafer  100  where the fingerprint sensing chip  110  is made before the it was diced from the wafer  100 . 
         [0032]    It is obvious that the I/O pad  112  forms a platform in the connecting space. Thus, the I/O pad  112  can allow a conductive adhesive to be applied thereon and filled fully or partially in the connecting space. The conductive adhesive can electrically connect the I/O pad  112  to a contact pad of an external circuit (not shown). Preferably, the conductive adhesive may be a silver paste. Also, the connection between the I/O pad  112  and the contact pad of external circuit may be achieved by a solder paste or metal plating. It is an innovative change of I/O pad design of a chip. If the electrical linkage method of wire bonding can be replaced by the conductive adhesive, the electrical linkages are all formed below the topmost surface of the chip. Thus, the thickness of the packaged chip can be reduced. 
         [0033]    In a second embodiment, the lower metal layer  100   b  and the upper metal layer  100   d  can be linked at the I/O pad  112 . Please see  FIG. 9 . The linkage is achieved by a stacked metal structure  100   bd , which is formed along with the upper metal layer, at the via opening above the I/O pad  112 . 
         [0034]    In a third embodiment, the fingerprint sensing chip  110  may have three metal layers around some I/O pads  112  and is shown in  FIG. 10 .  FIG. 10  is a perspective view of the I/O pad  112 . An additional metal layer  100   c ′ and an additional inter-metal dielectric layer  100   c ″ are formed between the inter-metal dielectric layer  100   c  and the upper metal layer  100   d.    
         [0035]    In a fourth embodiment, the connecting space is not requested to only form above the full I/O pad  112 . It can be formed on part of the I/O pad  112 . It means a portion of the I/O pad  112  may be buried below the inter-metal dielectric layer  100   c.  In another case, the connecting space can also extend beyond the I/O pad  112 , which means the connecting space is slightly larger than the I/O pad  112  in a top view. In practice, due to variation of physical condition for manufacturing the fingerprint sensing chip  110 , portions of the I/O pad  112  are really embedded between the substrate  100   a  and the inter-metal dielectric layer  100   c.    
         [0036]    For the description above, a method to make a chip with I/O pads on the peripheries can be obtained. Please refer to  FIG. 11 .  FIG. 11  is a flow chart of the method. The method has below steps. First, provide a substrate (S 01 ). Second, form a lower metal layer above the substrate, which contains a specific circuit and a number of I/O pads (S 02 ). Third, form an inter-metal dielectric layer above the lower metal layer and a number of via openings therein (S 03 ). Fourth, form other metal layers, inter-metal dielectric layers and vias formed therein if needed (S 04 ). Fifth, form an upper metal layer above the last formed inter-metal dielectric layer, which contains a specific circuit (S 05 ). Then, form a passivation layer above the upper metal layer (S 06 ). Next, deeply etch a number of pad windows to expose the I/O pads (S 07 ). Finally, dice the wafer along the saw streets of the wafer formed therein (S 08 ). It should be noticed that two adjacent metal layers are separated by an inter-metal dielectric layer. Meanwhile, at least one metal layer should have a number of traces. An I/O pad linked to one or more trace(s) is formed and a portion of the layer(s) above the I/O pad is removed. According to the present invention, each metal layer forming a specific circuit. The I/O pads are formed on peripheries of the chip. A pad window is formed above the I/O pad or part of the I/O pad. A connecting space is formed at the pad window. A contact surface of the I/O pad is exposed through the pad window. A distance between the contact surface of the I/O pad and an external surface of the passivation layer is larger than a connecting depth. The definition of the connecting depth is as that in the previous embodiment and not repeat here. 
         [0037]    Another method to make a chip with I/O pads on the peripheries can also be available. Steps of the method are shown in  FIG. 12 . It is slightly different from the previous method. The current method has below steps. First, provide a substrate (S 11 ). Second, form a lower metal layer above the substrate, which contains a specific circuit and a lower layer of each I/O pad (S 12 ). Third, form an inter-metal dielectric layer above the lower metal layer and a plurality of via openings therein (S 13 ). Fourth, form other metal layers, inter-metal dielectric layers and vias formed therein if needed (S 14 ). Fifth, deeply etch a number of vias at the I/O pad locations (S  15 ). Sixth, form an upper metal layer above the last formed inter-metal dielectric layer, which contains a specific circuit (S 16 ). Then, form a passivation layer above the upper metal layer (S 17 ). Next, etch a number of pad windows to expose the I/O pads (S 18 ). Finally, dice the wafer along the saw streets of the wafer formed therein (S 19 ). It should be noticed that two adjacent metal layers are separated by an inter-metal dielectric layer. Meanwhile, at least one metal layer should have a number of traces. An I/O pad linked to one or more trace(s) is formed and a portion of the layer(s) above the I/O pad is removed. According to the present invention, each metal layer forming a specific circuit. The I/O pads are formed on peripheries of the chip. A pad window is formed above the I/O pad or part of the I/O pad. A connecting space is formed at the pad window. A contact surface of the I/O pad is exposed through the pad window. A distance between the contact surface of the I/O pad and an external surface of the passivation layer is larger than a connecting depth. The definition of the connecting depth is as that in the previous embodiment and not repeat here. The via at each I/O pad location forms a concave portion, and a portion of the upper metal layer formed at each pad location forms a stacked metal structure. The stacked metal structure electrically links the upper metal layer to the lower metal layer. The contact surface of the I/O pad is a top surface of the upper metal layer at the I/O pad location. 
         [0038]    While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.