Abstract:
A voltage booster and regulator usable with Dickson-type charge pump device is specifically adapted to maintain efficiency with both high and low supply voltages. For high voltage supplies (e.g., 2.6 volts or more), the charge pump reduces overall power consumption resulting in a more efficient design. For low voltage applications (e.g., for supply voltages less than 2.6 volts), the charge pump uses a booster circuit to increase a clock input potential beyond the supply voltage available to a typical Dickson array. Further, the charge pump avoids inherent diode voltage drops in a typical Dickson array.

Description:
TECHNICAL FIELD 
   The present invention relates to a Dickson charge pump. More particularly, the invention relates to a Dickson charge pump operable at either high or low supply voltages. 
   BACKGROUND ART 
   Extensive use is currently made of nonvolatile digital data memory devices. Various consumer products, such as personal data assistants (PDAs), cellular telephones, and electronic notebooks require nonvolatile memory devices for storing information in a compact support of large capacity. 
   A shortcoming of nonvolatile memory devices is a high rate of power consumption associated with their operation. The rate of power consumption is obviously of major consequence to portable products such as those listed above since such devices are typically battery powered. 
   Most of the power expended to operate such memories goes to charge pump circuits, which are arranged to raise the voltage value above the supply level (usually the battery voltage level) for further supplying a part of the circuitry integrated in the memory device. This power expenditure is a result of high voltages needed to perform such basic operations as program and erase operations in nonvolatile memory devices. Where low voltage supply circuits are utilized, read operations as well as program and erase voltages are higher than the supply voltage. 
   Thus, providing charge pump circuits that utilize as small of a drain as possible on the power supply for their operation is of significant importance, and the present trend toward ever lower supply voltages for integrated circuits can only increases this importance. 
   With reference to  FIG. 1 , a circuit diagram of a typical four-stage Dickson charge pump device includes diodes D 1 -D 5  connected in series, with coupling capacitors C 1 -C 4  each being connected to a node between the diodes D 1 -D 5 . The Dickson charge pump circuit also includes an output capacitor C L . The output capacitor C L  is connected in parallel with an external load  103 . Input clock pulses CLK A  and CLK B  are of opposite phase with respect to each other. The clock pulses CLK A  and CLK B  are input to a clock driver  101 . The clock driver  101  is provided with a power supply voltage V DD  (not shown). An output phase of the clock pulses CLK A  and CLK B  is represented as φ 1  and φ 2  respectively. The clock pulse phase φ 1  is fed to the capacitors C 1  and C 3 , while the clock pulse phase φ 2  is fed to the capacitors C 2  and C 4 . 
   In a stable state, in which a constant current I out  flows out through the external load  103 , an input current to the charge pump device is a sum of a current from an input voltage V DD  and a current provided from the clock driver. These currents are as described below, disregarding charging or discharging currents to or from any stray circuit capacitance. During a clock period where φ 1  is “high” (i.e., logic “1”) and φ 2  is “low” (i.e., logic “0”), an average current of 2·(I out ) flows through each of a plurality of paths in directions depicted in the figure as solid line arrows. 
   During a subsequent clock period where φ 1  is “low” and φ 2  is “high,” an average current of 2·(I out ) flows through each of the plurality of paths in directions depicted in the figure as dashed line arrows. An average current of each of these aforementioned currents over a complete clock cycle is I out . An increased voltage from the charge pump device in the stable state is expressed by equation (1),
 
 V   out   =V   in   −V   d   +n ( V   φ′   −V   1   −V   d )  (1)
 
where V φ′  refers to an amplitude of a voltage at each of the connecting nodes induced through the coupling capacitor by a change in the clock pulse; V 1  denotes a voltage drop due to the output current I out ; V in  denotes the input voltage, which is usually set at V DD  in positive voltage boosting and at 0 volts in negative voltage boosting; V d  refers to a forward bias diode voltage; and n denotes a number of stages of pumping.
 
   Further, V 1  and V φ′  are expressed by the following equations 
                   V   1     =         I   out       f   ⁡     (       C   i     +     C   s       )         ≡       T   ·     I   out           C   i     +     C   s                   (   2   )                 V     ϕ   ′       =         V   ϕ     ·   C         C   i     +     C   s                 (   3   )               
where C i  represents a clock coupling capacitance of one of the capacitors C 1 -C 4 ; C s  is a stray capacitance at each of the connecting nodes; V φ  is an amplitude of the clock pulses; f is a frequency of the clock pulses; and T is a clock period of the clock pulses. Power efficiency, η, of the charge pump device is calculated, disregarding charging/discharging currents from/to the clock driver to/from the stray capacitors and assuming V in =V DD , by
 
   
     
       
         
           
             
               
                 η 
                 = 
                 
                   
                     
                       
                         V 
                         out 
                       
                       · 
                       
                         I 
                         out 
                       
                     
                     
                       
                         ( 
                         
                           n 
                           + 
                           1 
                         
                         ) 
                       
                       ⁢ 
                       
                         
                           V 
                           DD 
                         
                         · 
                         
                           I 
                           out 
                         
                       
                     
                   
                   ≡ 
                   
                     
                       V 
                       out 
                     
                     
                       
                         ( 
                         
                           n 
                           + 
                           1 
                         
                         ) 
                       
                       ⁢ 
                       
                         V 
                         DD 
                       
                     
                   
                 
               
             
             
               
                 ( 
                 4 
                 ) 
               
             
           
         
       
     
   
   Consequently, the charge pump device boosts the voltage by successively transferring electric charge to a next stage using a diode as a charge transfer device. However, an MOS transistor is easier than a PN junction diode to implement in a semiconductor integrated circuit due to fabrication compatibility within the manufacturing process. 
   Thus, MOS transistors, as indicated in  FIG. 1B , are used as the charge transfer devices in place of the diodes D 1 -D 5  of  FIG. 1A . Using MOS transistors, V d  in equation (1) is replaced with V th , where V th  represents a threshold voltage of the MOS transistor. 
     FIG. 2  shows a simple ring oscillator that can be used to drive either of the Dickson charge pump circuits shown in  FIGS. 1A and 1B . The ring oscillator is composed of a number of inverter elements  203   1 ,  203   2 , . . . ,  203   5  connected in series. An input NAND gate  201  provides a means for disabling the oscillator when a low voltage signal is presented at a first input of the NAND gate  201 , labeled “clk_en.” Each oscillator output produces signals, clk and  clk , which are stable (i.e., φ 1 =1, φ 2 =0) when a signal at clk_en is low. When enabled, the input NAND gate  201  inverts the signal from a second input of the NAND gate  201 . The signal is then propagated through the inverter elements  203   1 ,  203   2 , . . . ,  203   5  back to the second input of the NAND gate  201 . This process continues until the enable signal at clk_en goes back to low. The amount of time taken to propagate the signal back to the second input is determined by a delay of each of the inverter elements  203   1 ,  203   2 , . . . ,  203   5 . This inverter delay is dependent on the supply voltage V DD ; the supply voltage V DD  determines a maximum gate-source voltage that can be applied to transistors within each of the inverter elements  203   1 ,  203   2 , . . . ,  203   5 . The gate-source voltage determines a current drive for each of the inverter elements  203   1 ,  203   2 , . . . ,  203   5 , thus determining the propagation delay. A signal that is present at f 1  is provided to a first clock driver portion  204 , which is comprised of a NAND gate  205 , a first inverter  207   1  and a second inverter  207   2 , all connected in serial manner with each other. The first clock driver portion  204  produces an output “clk.” A signal at f 0  is provided to a second clock drive portion  208 , which is comprised of a NAND gate  209 , a first inverter  211   1  and a second inverter  211   2 , all connected in serial manner with each other. The second clock driver portion  208  produces an output “  clk .” The output signals clk and  clk  are 180° out of phase with respect to each other. 
   SUMMARY 
   An exemplary voltage booster and regulator usable with Dickson-type charge pump device is specifically adapted to maintain efficiency with both high and low supply voltages. For high voltage supplies (e.g., 2.6 volts or more), the charge pump reduces overall power consumption resulting in a more efficient design. For low voltage applications (e.g., for supply voltages less than 2.6 volts), the charge pump uses a booster circuit to increase a clock input potential beyond the supply voltage available to a typical Dickson array. Further, the charge pump avoids inherent diode voltage drops in a typical Dickson array. 
   In an exemplary embodiment, the charge pump apparatus comprises a plurality of switching devices, a voltage booster, and a voltage regulation device. The plurality of switching devices are configured to connect and disconnect one or more charge storage devices to a supply voltage source. The voltage booster contains the one or more charge storage devices and are configured, along with the plurality of switching devices, to provide a voltage output that is greater than both a threshold voltage of each of the plurality of switching devices and the supply voltage source. The voltage output is adapted to be coupled to an input of a charge pump circuit (e.g., a Dickson-type charge pump). The voltage regulation device is coupled to receive as an input the supply voltage source and is configured to be enabled if the supply voltage source is low and disabled if the supply voltage source is high. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1A  is a Dickson charge pump of the prior art. 
       FIG. 1B  is a cross-sectional view showing a charge pump device of the prior art implemented in a CMOS structure. 
       FIG. 2  is a simple ring oscillator circuit that can be used to drive a charge pump circuit. 
       FIG. 3  is an exemplary block diagram of a charge pump circuit of the present invention. 
       FIG. 4  is an exemplary regulated charge pump and booster circuit stage of the charge pump of  FIG. 3 . 
       FIG. 5A  is an exemplary driver circuit of the regulated charge pump and booster circuit stage of  FIG. 4 . 
       FIG. 5B  is a functional representation of the driver circuit of  FIG. 5A . 
       FIG. 6  is an exemplary pump stage of the charge pump circuit of  FIG. 3 . 
   

   DETAILED DESCRIPTION 
   The block diagram of  FIG. 3  provides an overview of various parts of the charge pump circuit  300  of the present invention. The charge pump circuit  300  includes an oscillator circuit  301 , a regulated charge pump and booster circuit  303 , and a plurality of pump stages  305   1 ,  305   2 . 
   The oscillator circuit  301  receives a enable signal pump_on, fed through an inverter, and a single output clk signal. Details of the oscillator  301  are not discussed as such circuits are well-known within the art. One exemplary oscillator circuit which may be used with the present invention is described in detail in U.S. patent application Ser. No. 10/995,458 filed Nov. 22, 2004 (claiming priority from French Patent Application, serial number 04/08931, filed Aug. 17, 2004), entitled “Oscillator Circuit for EEPROM High Voltage Generation,” and commonly assigned, along with this application, to Atmel Corporation, San Jose, Calif. 
   The regulated charge pump and booster circuit  303  receives, as an input, the clk signal from the oscillator  301 . A supply voltage, V DD , is connected to the regulated charge pump and booster circuit  303  at lv_fuse, and two clocked output signals, out and  out  provide a clock and inverted clock input to the plurality of pump stages  305   1 ,  305   2 . The two clocked output signals, out and  out  may or may not be boosted in amplitude depending on a potential of the input supply voltage V DD . Typically, if the supply voltage V DD  is less than approximately 2.6 volts, the potential of the output signals will be boosted. Details of the regulated charge pump and booster circuit  303  are described, infra, with reference to  FIGS. 4 ,  5 A, and  5 B. 
   The plurality of pump stages  305   1 ,  305   2  may be implemented as a typical Dickson-type pump stage as described with reference to the CMOS-based Dickson pump stage of  FIG. 1B . Although only two stages are shown, a skilled artisan will recognize that a higher output voltage and/or current may be obtained by combining numerous pump stages in parallel and/or series. 
   The regulated charge pump and booster circuit  303  is described in more detail in an exemplary embodiment of  FIG. 4 .  FIG. 4  includes clock inversion circuitry  401  and a plurality of driver circuits  403   1 ,  403   2 . The clock inversion circuitry  401  includes two parallel NAND-inverter-NAND-inverter series connected string, each string connected in parallel with the other. Outputs c 0  and c 2  of the clock inversion circuitry  401  are shown in the table on  FIG. 4  as complementary to each other for a given input (i.e., a “0” or “1”) assuming power is on (i.e., pwr_on=1). Each output c 0 , c 2  serves as an input for the plurality of driver circuits  403   1 ,  403   2 . 
   Each of the driver circuits  403   1 ,  403   2  is cross-coupled to the other. The driver circuits  403   1 ,  403   2  contain the predominant circuitry controlling both voltage regulation and booster circuitry. Exemplary voltage regulation and booster circuitry are each described in detail with reference to  FIGS. 5A and 5B . 
     FIG. 5A  includes details of a specific exemplary driver circuit  403 , usable as an output stage for each of the driver stages  403   i  of the regulated charge pump and booster circuit  303  of  FIG. 3 . A first and second large capacitor, C 1  and C 2 , store an input supply voltage, V DD . Charge stored in the second large capacitor C 2  is delivered to the Dickson pump stages  305   i  through the PMOS transistor P 1  via a clk_out tap. The clk_out tap is a boosted version of the supply voltage V DD . In a specific exemplary embodiment, the first large capacitor C 1  has a storage value of 4.5 picofarads and the second large capacitor C 2  has a storage value of 55 picofarads. Details for a generic exemplary booster circuit is given infra with reference to  FIG. 5B . 
     FIG. 5A  also includes a voltage regulator portion  501 . The voltage regulator portion  501  includes additional circuitry providing a feedback path preventing the output voltage at int_hv_out from exceeding an absolute maximum voltage rating for IC transistors. In this embodiment, the voltage regulator portion includes PMOS transistors P 2 , P 3 , and P 4  connected in series, gate coupled NMOS transistors N 1  and N 2 , a V DD  pass transistor P 5 , and a NAND gate I 1 . In a specific exemplary embodiment, the absolute maximum voltage rating for the IC transistors is 5.5 volts. 
   The functional representation of  FIG. 5B  provides a high-level explanation of the booster circuit portion of  FIG. 5A . In operations involving a low supply voltage: During a first clock phase, φ 1 , switches S 1 , S 3 , and S 5  are turned on (i.e., “closed”) while switches S 2  and S 4  are turned off (i.e., “open”). Switch S 5  pulls the output “low.” Concurrently, the capacitor C is charged to the supply voltage level, V DD . During a second clock phase, φ 2 , the switches S 1 , S 3 , and S 5  are turned off while switches S 2  and S 4  are turned on. The output voltage now rises to roughly twice the supply voltage, V DD . Therefore, the subsequent pump stages  305  see a voltage that alternates between 0 volts and 2·V DD , making the pump stage  305  more efficient as any diode voltage drops comprise a much smaller percentage of the total starting supply voltage. For example, assume a pump stage diode voltage drop is 0.7 volts. For a supply voltage of only 1.2 volts, the percentage efficiency due to potential lost across the diode is 
                 1.2   ⁢   V     -     0.7   ⁢   V         1.2   ⁢   V       ≅     42   ⁢     %   .             
However, by boosting the voltage prior to entering the pump stage, the percentage efficiency increases to
 
                 2.4   ⁢   V     -     0.7   ⁢   V         2.4   ⁢   V       ≅     71   ⁢     %   .             
Thus, the booster circuit portion produces a significant increase in efficiency.
 
   In operations involving a high supply voltage: Switches S 1  through S 5  are operated differently than in low voltage operation due to the regulating function of the circuit. The regulating circuit measures a voltage output by the circuit. As discussed supra with regard to  FIG. 5A , the regulation circuit of the exemplary embodiment includes PMOS transistors P 2 -P 5 , NMOS transistors N 1  and N 2 , and the NAND logic gate I 1 . Referring back again to  FIG. 5B  operated at a high voltage, during clock φ 1 , the switches S 1 , S 3 , and S 5  are turned on while S 2  and S 4  are switched off. The capacitor is again charged to a level of the potential V DD . The output voltage remains low due to switch S 5  being turned on. In the second clock phase, φ 2 , the switches S 1  and S 5  are turned off, S 2  remains turned off, S 3  remains turned on, and S 4  is switched on if the measured output voltage remains below approximately 2.6 volts. The main difference between this high voltage operation and the low voltage operation described supra is that the switch S 2  is constantly off and the switch S 3  is constantly on. Therefore, the output voltage is no longer boosted as in the low voltage operation but rather, the output voltage alternates between 0 volts and about 2.6 volts. Therefore, an input voltage to the subsequent Dickson charge pump stage is always either 0 volts or about 2.6 volts. Additionally, energy transferred to the charge pump stage is limited by a value of the capacitor C. Hence, a drawn supply current is limited, thereby making the pump stage well-behaved at higher voltages (e.g., consistent and well-known output voltages with a consistent pulse width). 
     FIG. 6  includes a plurality of pump stages  305   1 ,  305   2 , . . . ,  305   n  connected in series, with each pump stage  305   i  connected to both a clkout signal and a complementary (i.e., opposite phase)  clkout  signal from the regulated charge pump and booster circuit  303  ( FIG. 3 ). The V DD  pass transistor  601 , in this embodiment, is chosen to be an “nw” device (with a higher than normal threshold voltage, V t ) rather than an “nws” device to avoid current leak-back to the supply at low supply voltages. The “nw” device is a native (i.e., without threshold implant) high voltage n-channel transistor with a p-well. The “nw” transistor has a higher threshold voltage (approximately 0.22 volts) than the “nws” device and, thus, lower leakage. The “nws” device is a native high voltage n-channel transistor in substrate. The threshold voltage of the “nws” transistor is about —0.09 volts. A skilled artisan will recognize that the  “nws”  device may be substituted for the “nw” device with a minimal performance difference. 
   In the foregoing specification, the present invention has been described with reference to specific embodiments thereof. It will, however, be evident to a skilled artisan that various modifications and changes can be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. For example, skilled artisans will appreciate that although the booster and regulator circuits have been described in terms of specific circuitry and specific voltage levels, equivalent or similar circuits and voltages may be implemented without departing from the scope of the present invention presented herein. Further, individual devices such as the capacitor described in connection with the voltage booster circuitry may be any charge storage device such as a transistor connected to act as a charge storage mechanism, a series of plates coupled with an interleaved dielectric fabricated as part of an integrated circuit, or a comb capacitor fabricated by techniques well known in the semiconductor art. Other items are described in terms of MOS integrated circuit devices although a person of ordinary skill in the art will recognize that other fabrication techniques, such as bipolar or BiCMOS techniques, may readily be employed as well. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.