Abstract:
An electronic device which includes an electronic component having a substrate and a plurality of metal interconnection layers, the plurality of metal interconnection layers having a top surface. It further comprises a dielectric layer situated above said metal interconnection layers, a conductive layer situated above said dielectric layer, an inductor coil and a ground shield, the inductor coil being formed in the conductive layer and the ground shield being formed in a layer of said plurality of metal interconnection layers.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the priority benefit of European patent application number 09305907.9, filed on Sep. 29, 2009, entitled “ELECTRONIC CIRCUIT WITH AN INDUCTOR,” which is hereby incorporated by reference to the maximum extent allowable by law. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to packages for electronic components, particularly but not exclusively to semiconductor components incorporating inductive elements. 
         [0004]    2. Discussion of the Related Art 
         [0005]    Electronic circuits frequently employ inductors and it is useful to place them as close as possible to the actual circuits of which they form part. 
         [0006]    It is known to incorporate inductors into the packages of electronic devices. However there is severe price pressure on electronic devices so it is undesirable for such incorporation to increase the costs of the device. 
         [0007]    Inductors are, as a consequence of the electromagnetic field they produce, very sensitive to their environment. Thus their incorporation requires care and compromises are necessary. Because of the form of their electromagnetic field, planar inductors are particularly sensitive. 
         [0008]    Furthermore, the performance of an inductor is very sensitive to parasitic effects. Both the series resistance of the windings and capacitive coupling, between the inductor and ground and between the windings themselves, reduce the quality factor of the inductor. The quality factor is a measure of the losses incurred in the circuit including the inductor and is therefore of profound influence on overall circuit performance. 
         [0009]    These inductors may take the form of discrete surface mount components placed on a printed circuit board substrate (PCB) close to the element having the electronics. 
         [0010]    The use of discrete components can cause an added cost in terms of component purchase, processing costs and size. Using the PCB metal tracks overcomes the purchase and processing cost issues. However the relatively coarse tolerances of PCB processing mean that the inductor tolerances are quite large. 
         [0011]    It is also known to incorporate inductors into semiconductor dice, by using the patterned metal interconnection layers of the alternating patterned metal and insulating layers (commonly known as the ‘multilevel interconnect’). Because the windings lie in a plane, rather than being three-dimensional, these are known as planar inductors. Another possibility is to use metal tracks on the PCB to form the windings of the planar inductor. 
         [0012]    Planar inductors are often not placed directly facing active components in order to avoid interaction between the electromagnetic field of the inductor and the active component. This is particularly true when the active component is on silicon because the highly doped silicon substrate causes high losses in the inductor. 
         [0013]    In the case of PCB planar inductors, they may be placed outside the area of the die. Because the inductor is therefore distanced from the actual circuitry concerned, its overall series resistance is increased, thereby decreasing the inductor quality factor. 
         [0014]    The inductors constructed in the semiconductor process benefit from better tolerances but the metal of the multilevel interconnect are limited to a maximum thickness of around 3 μm. This means that the series resistances of the coil windings are high compared to discrete inductors and so their quality factors are correspondingly lower. 
         [0015]    Multilayer ceramic packages allow the incorporation of high quality inductors but these are more expensive and generally larger. 
         [0016]    It is therefore desirable to provide a means of incorporating higher performance inductors into electronic component packages without increasing the cost and size. 
       SUMMARY OF THE INVENTION 
       [0017]    Embodiments described herein address this need by providing an electronic device comprising:
       an electronic component having a substrate and a plurality of metal interconnection layers, said plurality of metal interconnection layers having a top surface;   a dielectric layer situated above said metal interconnection layers;   at least one conductive layer situated above said dielectric layer;   an inductor coil and a ground shield,       
 
         [0022]    wherein the inductor coil is formed in at least one of the conductive layers and the ground shield is formed a layer of the plurality of metal interconnection layers. 
         [0023]    According to an embodiment of the electronic device, said inductor coil is vertically above said ground coil and the plane of said inductor coil is substantially parallel to the plane of said ground shield. 
         [0024]    According to an embodiment of the electronic device, the shortest distance between the inductor coil and said ground shield is not less than 10 μm. According to an embodiment of the electronic device, the shortest distance between said inductor coil and said ground shield is not greater than 25 μm. 
         [0025]    According to an embodiment of the electronic device, the area occupied by said inductor coil is less than that occupied by said ground shield. 
         [0026]    According to an embodiment of the electronic device, said electronic component is a semiconductor die. 
         [0027]    According to an embodiment of the electronic device, said metal interconnection layers are arranged vertically above one another and said ground shield is formed in a metal interconnection layer close to said substrate. 
         [0028]    According to an embodiment of the electronic device, it further comprises a block of molding resin partially encapsulating said electronic component so that said top surface of said metal interconnection layers is left free. 
         [0029]    According to an embodiment of the electronic device, the block of molding resin has a top surface flush with said top surface of said metal interconnection layers. 
         [0030]    Also provided is an electronic equipment comprising an electronic component according to an embodiment. 
         [0031]    There is also provided a process of manufacturing the electronic device according to an embodiment, comprising the steps of:
       providing an electronic component having a plurality of metal interconnection layers in which is formed a ground shield;   placing a dielectric layer above said multilevel interconnect;   placing a conductive layer above said dielectric layer;   forming a pattern in said conductive layer,       
 
         [0036]    wherein the step of patterning the conductive layer forms an inductor coil which is vertically aligned to the ground shield. 
         [0037]    According to an embodiment of the process, the dielectric layer and the conductive layer are made using thin-film techniques. 
         [0038]    According to an embodiment of the process, it further comprises the step of partially encapsulating the electronic component in molding resin in a way that the top surface of the multilevel interconnect is left free. 
         [0039]    According to an embodiment of the process, it further comprises the step of forming a protection layer partially covering said conductive and dielectric layers. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0040]    The foregoing and other purposes, features, aspects and advantages of the invention will become apparent from the following detailed description of embodiments, given by way of illustration and not limitation with reference to the accompanying drawings. 
           [0041]      FIG. 1  represents a cross-section of an electronic component package according to an embodiment; 
           [0042]      FIG. 2  represents a plan view the electronic component package of  FIG. 1 ; 
           [0043]      FIG. 3  represents an assembly flow for manufacturing a package like that of  FIG. 1 ; and 
           [0044]      FIG. 4 . represents equipment incorporating an electronic component in a package according to an embodiment. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0045]    In the interests of clarity, same references designate same elements. 
         [0046]      FIG. 1  represents a cross-section view of an electronic component  1  according to an embodiment. A semiconductor die  10  is partially enclosed in a block of molding resin  11 . 
         [0047]    The semiconductor die  10  incorporates active circuitry (not shown) on a substrate  100  and a multilevel interconnect  110 , formed of alternating patterned metal layers  111  and insulating layers  112 . In one of the metal layers  111 , preferably close to the substrate  100 , there is an area of metal forming a ground shield  113 . The uppermost layer of the multilevel interconnect  110  is a passivation layer  114 . The distance between the ground shield  113  and the top of the passivation layer  114  may be as much as 9 μm when several metal layers are present. 
         [0048]    The purpose of the ground shield  113  is to reduce the interaction between the electromagnetic fields generated by components above the shield and the substrate  100  below. 
         [0049]    There are contact pads  115 , such as bond pads, arranged on the upper metal level of the multilayer interconnect  110 . The block of molding resin  11  is arranged enveloping the semiconductor die  10  so that the top surface of the multilayer interconnect  110  is left free and the top surface of the molding resin  11  is approximately flush with the top surface of multilayer interconnect  110 . 
         [0050]    Across the top of the multilayer interconnect  110  of the semiconductor die  10  and of the block of molding resin  11 , is placed a redistribution structure  12 . 
         [0051]    The redistribution structure  12  is composed of a series of layers. There is a first dielectric layer  120  which lies on the surface formed by the passivation layer  114  of the semiconductor die  10  and the block of molding resin  11 . 
         [0052]    Through the first dielectric layer  120 , pass conductive vias  121 . The conductive vias  121  connect the contact pads  114  of the semiconductor die  10  to a metal layer  122  arranged above the dielectric layer  120 . The metal layer  122  has formed in it solder pads  123  for connections to external circuitry (not shown) and windings  124  forming a planar inductor. 
         [0053]    There is protection layer  125 , made from a second dielectric layer, which covers the metal layer  122  except for openings over the solder pads  123 . 
         [0054]    In general, soldering is done on much larger features than those used on the semiconductor die so redistribution is used to connect the closely spaced bond pads  115  to the more widely spaced solder pads  123 . 
         [0055]    Onto the solder pads  123 , optional solder balls  13  may be placed. 
         [0056]    The first dielectric layer  120  is typically about 7 μm thick. The metal layer  122  is typically about 7 μm thick and the protection layer  124  is typically about 9 μm thick. 
         [0057]      FIG. 2  represents a plan view of the electronic component  1 , viewed from the side of the solder balls  13 . Of the elements described previously, only those requiring further detail will be further described. Metal tracks  126  may be used to connect the conductive vias  121  to the solder pads  123 . 
         [0058]    Advantageously, the windings of the planar inductor  124  are positioned vertically above the ground shield  113 . The ground shield  113  reduces the influence of the substrate  100  of the semiconductor die  10  by limiting the degree to which the electromagnetic field from the planar inductor  124  penetrates the substrate  100 , thereby reducing the losses suffered by the planar inductor  124 . 
         [0059]    It may be advantageous if the area occupied by the windings  124  is contained within that occupied by the ground shield  113 . However, surface area of the semiconductor die  10  is at a premium so it is not desirable to make the ground shield  113  any larger than necessary. 
         [0060]    The metal layer  122  of the redistribution structure  12  is around twice the thickness of that of the thickest metal layer  111  of the multilevel interconnect  110 . Therefore the series resistance of the windings of the planar inductor  124  is significantly reduced compared to that obtainable in windings formed in the thickest metal layer  111  of the semiconductor die  10 . Thus a much improved quality factor is obtained. 
         [0061]    The presence of the ground shield  113  allows the planar inductor  124  to be placed above the semiconductor die  10 , rather than to one side. Thus the overall series resistance is reduced relative to the situation where the planar inductor  124  is offset. 
         [0062]    Though the ground shield  113  is generally beneficial, it has certain effects on the characteristics of the planar inductor  124  which result in certain compromises being necessary. 
         [0063]    The ground shield  113  is seen by the planar inductor  124  as a capacitive coupling both to ground. This capacitive coupling reduces the quality factor of the planar inductor  124 . By increasing the distance between the ground shield  113  and the planar inductor  124 , this effect may be reduced, thereby improving the quality factor. With distances above 10 μm, the degradation due to capacitive coupling becomes acceptable. 
         [0064]    However the ground shield  113  has the effect of distorting the electromagnetic field of the planar inductor  124  in such a way that the electromagnetic field interacts less with other metal objects such as tracks on any PCB to which the electronic component  1  is connected. Therefore it is desirable to keep the ground shield  113  closer than these other metal objects. If the distance between the planar inductor  124  and the ground shield  113  is kept below 25 μm, the influence of the PCB can be neglected since it will be of the order of over 100 μm away. 
         [0065]    It would be possible to form the ground shield  113  by adding an extra metal and dielectric layer to the redistribution structure  12 . However this presents certain drawbacks. 
         [0066]    Firstly, the additional layers increase the cost noticeably. 
         [0067]    Secondly, the standard dielectric thickness is around 7 μm which, in certain cases, would place the planar inductor  124  closer to a ground shield made this way, as compared to a ground shield contained in the semiconductor dies  10 . Thus the performance of the planar inductor  124  would be degraded. 
         [0068]    The new dielectric layer would have to be much thicker, i.e. around 16 μm, in order to obtain the same distance between the ground shield  113  and the planar inductor  124  as that obtained with an embodiment. Such a thick dielectric layer would be even more expensive and would require wider vias thus making the routing density lower. Since many devices have large numbers of solder pad  123  and bond pads  114 , the routing density is an important factor in determining overall package size. 
         [0069]      FIG. 3  represents a simplified process for manufacturing an electronic component according to an embodiment. 
         [0070]    At step S 1 , a number of semiconductor dice  10  are placed on a support  30 , with the top surface of the multilevel interconnect  110  in contact with the support  30 . The support is constructed so as to hold the semiconductor dice  10  in place. A sticky surface which allows the semiconductor dice  10  to be easily removed is a possible technique for this purpose. 
         [0071]    At step S 2 , semiconductor dice  10  are enclosed in a block of molding resin  11  which covers in one block all the semiconductor dice  10 . The block of molding resin  11  does not cover the top surfaces of the multilevel interconnect  110  of the semiconductor dice  10 . The block of molding resin is hardened by curing. 
         [0072]    At step S 3 , the support  30  is removed and a redistribution structure  12  is formed across the top surfaces of the multilevel interconnects  110  of the semiconductor dice  10 . The redistribution structure  12  may be formed using thin-film techniques. With such techniques, it is possible to align accurately features in the redistribution structure  12  with features in the multilevel interconnect  110 . Thus it is possible to ensure that the planar inductor  124  is correctly aligned with of the ground shield  113 . 
         [0073]    In the case where a PCB substrate has been used for the redistribution, instead of the thin-film techniques, the accuracy of alignment necessary for the planar inductor  124  and ground shield  113  is difficult to obtain. 
         [0074]    At step S 4 , the individual electronic components  1  are separated and, where appropriate, solder balls  13  are attached to the solder pads  123 . The order of these two steps may be varied according the details of the manufacturing process. Sawing may be used for separating the individual electronic components  1 . 
         [0075]      FIG. 4  represents a cross-section view of a piece of electronic equipment  40  comprising an electronic component  1 , according to an embodiment, attached to a PCB  41 . The attachment method should provide for some of the connections to be conductive. For this some form of soldering may be used and this choice is within the scope of the skilled person. Around the outside of the piece of electronic equipment is a casing  42 . Certain plastics may be suitable for this purpose and the skilled person will be able to choose. 
         [0076]    The foregoing is given purely by way of example and is, in no way, intended to be limitative. Indeed, other variants are possible. 
         [0077]    For example, it may be possible to use techniques other than thin-film processing for making the redistribution structure  12 , as long as the alignment tolerances needed between the planar inductor  124  and the ground shield  113  are respected. 
         [0078]    For example, the planar inductor  124  has been shown with only one turn. It is possible to leave an area near the center of the ground shield  113  free. Through this area a connection to a conductive via  121  may be made which in turn can be connected to one end of the planar inductor  124 . The planar inductor so formed may then have more turns. 
         [0079]    For example, is may be possible to have more than one planar inductor  124  above a single ground shield  113 . 
         [0080]    For example, it may be possible to use other conductive materials than metal in the redistribution structure. 
         [0081]    Having thus described at least one illustrative embodiment of the invention, various alterations, modifications and improvements will readily occur to those skilled in the art. Such alterations, modifications and improvements are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The invention is limited only as defined in the following claims and the equivalent thereto.