Abstract:
Microstructure devices, methods of forming a microstructure device and a method of forming a MEMS device are described. According to one aspect, a microstructure device includes: a semiconductive substrate; a monolithic microstructure device feature coupled with the semiconductive substrate, and wherein at least a portion of the microstructure device feature is configured to move relative to the semiconductive substrate; and a conductive structure provided directly upon the microstructure device feature.

Description:
TECHNICAL FIELD  
         [0001]    The invention pertains to microstructure devices, methods of forming a microstructure device and a method of forming a MEMS device.  
         BACKGROUND OF THE INVENTION  
         [0002]    Advancements in the field of semiconductor processing have resulted in the development of micro-machining and micro-electromechanics. More specifically, micro-electromechanical systems (MEMS) have been fabricated using semiconductor processing techniques to form electrical and mechanical structures using a given substrate.  
           [0003]    For example, some micro-electromechanical systems devices include cantilevers or other microstages of silicon which may be configured to be electrostatically actuated for various applications. Such MEMS devices may be used in exemplary applications including gyroscopes, accelerometers, tunable RF capacitors, digital mirrors, etc.  
           [0004]    Exemplary MEMS devices including cantilever structures are described in Zhang and MacDonald,  A RIE Process For Submicron, Silicon Electromechanical Structures,  Cornell University (IOP Publishing Ltd. 1992), the teachings of which are incorporated herein by reference. A process is proposed in this publication for the formation of silicon cantilever beams with aluminum side electrodes for use as capacitor actuators. This prior art method is depicted herein as FIGS.  1 - 11 .  
           [0005]    Referring initially to FIG. 1, a silicon substrate  10 , a silicon dioxide (SiO 2 ) layer  12 , and photoresist  14  are depicted. Layer  12  is formed to a thickness of 150 nm and photoresist  14  is patterned as illustrated.  
           [0006]    Referring to FIG. 2, a mask defined by photoresist  14  shown in FIG. 1 is utilized to pattern silicon dioxide layer  12 .  
           [0007]    Referring to FIG. 3, plural trenches  16  are formed in substrate  10  utilizing reactive ion etching (RIE) according to the prior art process.  
           [0008]    Referring to FIG. 4, thermal oxidation next occurs resulting in insulative layer  12   a  covering sidewalls and lower surfaces of trenches.  
           [0009]    Referring to FIG. 5, contact windows  20  are opened over a surface of substrate  10  to enable desired electrical connection through insulative silicon dioxide layer  12   a  to substrate  10 .  
           [0010]    Referring to FIG. 6, an aluminum layer  22  is formed by physical vapor deposition (PVD) to a thickness of 400 nm. The sputtered aluminum layer  22  forms side electrodes  23  within trenches  16 .  
           [0011]    Referring to FIG. 7, photoresist  24  is formed upon the structure of FIG. 6 and is patterned to cover portions of aluminum layer  22  including side electrodes  23 .  
           [0012]    Referring to FIG. 8, portions of the aluminum layer  22  upon the bottom surfaces of trenches  16  are patterned as shown using photoresist  24 .  
           [0013]    Referring to FIG. 9, portions of silicon dioxide layer  12  within the bottoms of trenches  16  are patterned following patterning of aluminum layer  22 .  
           [0014]    Referring to FIG. 10, photoresist  24  of FIG. 9 is stripped from the structure.  
           [0015]    Referring to FIG. 11, a cantilever  26  is released by isotropically etching silicon substrate  10  utilizing a fluorinated plasma (i.e., SiF 6 ). Further details regarding the depicted prior art process are also described in U.S. Pat. No. 5,198,390, the teachings of which are incorporated herein by reference.  
           [0016]    Modifications to this aforementioned process have been proposed by M. T. A. Saif and Noel C. MacDonald, as described herein.  
           [0017]    In this modified process, the silicon release step described above with respect to FIG. 11 is performed prior to aluminum metallization. More specifically, the silicon is etched similar to FIG. 3 and plasma enhanced chemical vapor deposition PECVD or tetraethylorthosilicate (TEOS) deposition thereafter occurs. The resultant oxide is patterned, the silicon release etch is performed, and aluminum is deposited. This described process eliminates the need to pattern the metal or open contact holes.  
           [0018]    The conventional described processes have associated drawbacks. Initially, the reactive ion etching of silicon substrate  10  shown in FIG. 3 typically results in a rough or scalloped etch profile. The roughness is duplicated in subsequent oxide and aluminum layers formed upon the sidewalls of trenches  16 . Such roughness or scalloping compromises the functionality of the resultant device inasmuch as the area of the electrodes or capacitor plates is not well controlled. Further, such roughness or scalloping limits the scalability of the structure.  
           [0019]    Also, the single crystal reactive etching and metallization process of the prior art contains multiple oxide and aluminum deposition and etch steps resulting in increased complexity.  
           [0020]    In addition, the utilization of SF 6  plasma to release the silicon cantilever  26  attacks the aluminum side electrodes  23 . Although the aluminum is attacked weakly by this chemistry, such may lead to further undesirable non-uniformity of electrodes  23 .  
           [0021]    Accordingly, there exists a need to provide improved processing methodologies and structures which avoid the drawbacks associated with the prior art methodologies and devices.  
         SUMMARY OF THE INVENTION  
         [0022]    The invention pertains to microstructure devices, methods of forming a microstructure device and a method of forming a MEMS device.  
           [0023]    According to one aspect, the invention provides a microstructure device comprising: a semiconductive substrate; a monolithic microstructure device feature coupled with the semiconductive substrate, and wherein at least a portion of the microstructure device feature is configured to move relative to the semiconductive substrate; and a conductive structure provided directly upon at least a portion of the microstructure device feature.  
           [0024]    A second aspect of the invention provides a microstructure device comprising: a semiconductive substrate; a microstructure device feature coupled with the semiconductive substrate, and wherein at least a portion of the microstructure device feature is configured to move relative to the semiconductive substrate; and a titanium nitride structure coupled with at least a portion of the microstructure device feature.  
           [0025]    Another aspect of the invention provides a microstructure device comprising: a semiconductive substrate having a sidewall; a microstructure device feature having a sidewall adjacent to and spaced from the sidewall of the semiconductive substrate, and wherein at least a portion of the microstructure device feature is configured to move relative to the semiconductive substrate; and opposing conductive electrodes individually provided directly upon one of the sidewall of the semiconductive substrate and the sidewall of the microstructure device feature to form a capacitor.  
           [0026]    According to another aspect, a method of forming a microstructure device comprises: forming a monolithic microstructure device feature coupled with a semiconductive substrate; providing a conductive structure directly upon at least a portion of the microstructure device feature; and releasing the microstructure device feature from the semiconductive substrate.  
           [0027]    Another aspect provides a method of forming a microstructure device comprising: forming a microstructure device feature coupled with a semiconductive substrate; depositing a conductive structure upon at least a portion of the microstructure device feature using chemical vapor deposition; and releasing at least a portion of the microstructure device feature from the semiconductive substrate.  
           [0028]    According to an additional aspect, the invention provides a method of forming a microstructure device comprising: providing a semiconductive substrate; forming a microstructure device feature using the semiconductive substrate and comprising material of the semiconductive substrate; and providing a conductive structure directly upon at least a portion of the semiconductive material of the microstructure device feature; and releasing the microstructure device feature from the semiconductive substrate.  
           [0029]    Another aspect provides a method of forming a microstructure device comprising: forming a plurality of trenches within a semiconductive substrate to define a microstructure device feature, the semiconductive substrate and the microstructure device feature having opposing sidewalls; forming respective conductive structures directly upon respective portions of the opposing sidewalls of the semiconductive substrate and the microstructure device feature; and undercutting at least a portion of the microstructure device feature to release the portion of the microstructure device feature from the substrate to permit the portion of the microstructure to move relative to the substrate.  
           [0030]    Yet another aspect provides a method of forming a MEMS device comprising: providing a semiconductive substrate; forming plural trenches having bottom surfaces within the semiconductive substrate to define a MEMS device feature between the trenches, the semiconductive substrate and the microstructure device feature having opposing sidewalls; depositing a titanium nitride layer using chemical vapor deposition upon at least a portion of an upper surface of the semiconductive substrate, upon the opposing sidewalls of the semiconductive substrate and the microstructure device feature to form capacitor electrodes, and upon the bottom surfaces; removing the titanium nitride layer upon the bottom surfaces of the trenches; and undercutting at least a portion of the microstructure device feature to release the portion of the microstructure device feature from the substrate to permit the portion of the microstructure device feature to move relative to the substrate.  
           [0031]    Other devices and methods are also disclosed herein according to other aspects of the present invention. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0032]    FIGS.  1 - 11  depict sequential process steps of a conventional fabrication methodology.  
         [0033]    FIGS.  12 - 20  depict exemplary sequential process steps according to aspects of the present invention.  
         [0034]    [0034]FIG. 21 is a perspective view of an exemplary device embodying aspects of the present invention and fabricated according to the process of FIGS.  12 - 20 . 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0035]    Exemplary process steps of the present invention are illustrated in FIGS.  12 - 20  and are described with respect to the formation of microstructure devices. One example of a microstructure device  31  is depicted in FIG. 21 comprising a capacitor actuator of a micro-electromechanical systems (MEMS) device or a microsystems technology (MST) device. Microstructure devices include micromachined components or structures. The depicted microstructure device  31  comprising a MEMS or MST device is exemplary and the present invention may be utilized to fabricate other devices, including other microstructure devices.  
         [0036]    Referring to FIGS.  12 - 20 , an exemplary methodology for fabricating features of microstructure devices is illustrated in sequential process steps. Microstructure device feature refers to a micromachined component or structure of a microstructure device configured to move relative to a substrate. One example of a microstructure device feature is a microstage of substrate material comprising a cantilever, gear, valve, actuator, sensor or other structure of a MEMS device.  
         [0037]    Referring initially to FIG. 12, a microstructure device assembly  30  is depicted at an initial process step. Assembly  30  includes a substrate  40  comprising substrate material  41  utilized to form subsequent devices. An exemplary substrate  40  is a semiconductive substrate, such as monocrystalline silicon. The present invention encompasses other substrates, materials, and/or layers in addition to monocrystalline silicon, such as polycrystalline or amorphous silicon, silicon carbide, gallium arsenide, for example.  
         [0038]    Semiconductive substrate comprises any construction of semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials) including silicon on insulator (SOI) and bonded wafer configurations, for example. Substrate refers to any supporting structure, including, but not limited to, the semiconductive substrate described above.  
         [0039]    A layer of insulative material  42 , such as thermal silicon dioxide, is formed upon substrate  40  in the depicted embodiment. Further, photoresist material  44  is patterned upon insulative material  42  as illustrated to form a desired microstructure device feature in the subsequent process steps described below.  
         [0040]    Referring to FIG. 13, the silicon dioxide material  42  is patterned using photoresist material  44  of FIG. 12 forming a mask  43 . Photoresist material  44  has been stripped from assembly  30  in FIG. 13.  
         [0041]    Referring to FIG. 14, a plurality of trenches  46  are formed within substrate  40  as defined by mask  43 . Trenches  46  are formed within substrate  40  using reactive ion etching in one example. The depicted trenches  46  are deep trenches individually having a depth of approximately 5-50 microns and a width of approximately 0.25-5 microns. Individual trenches  46  include plural sidewalls  47  and a bottom surface  49 .  
         [0042]    Referring to FIG. 15, mask  43 , comprising the insulative material  42 , is etched from substrate  40  of assembly  30  following the formation of deep trenches  46 .  
         [0043]    Referring to FIG. 16, a layer of conductive material  48  is provided over substrate  40 . According to the described embodiment, conductive material  48  comprises titanium nitride (TiN). An exemplary CVD process of titanium nitride is performed at pressures of approximately 5-10 Torr, temperatures of approximately 680° C., and utilizing the following gases TiCl 4  at 350 sccm, NH 3  at 100 sccm and nitrogen at 1000 sccm.  
         [0044]    Other conductive materials, such as tungsten, tantelum nitride, or other refractory metals, may also be utilized. An exemplary tungsten deposition process is described in Takayuki Ohba,  Chemical - Vapor - Deposited Tungsten for Vertical Wiring,  pp. 46-52 (1995), incorporated herein by reference. Conductive material  48  is selected in accordance with aspects of the invention such that direct deposition of the material upon substrate material  41  will not result in an adverse reaction which compromises device fabrication or operation.  
         [0045]    According to embodiments wherein titanium nitride is utilized, the titanium nitride conductive material  48  is deposited in a single layer using chemical vapor deposition (CVD) with TiCl 4  as a precursor in the described exemplary process. Conductive material  48  is formed to a thickness of approximately 300 nm in accordance with the illustrative embodiment. Deposition of TiN provides a conformal coating of conductive material  48  having substantially smooth outwardly exposed surfaces even when deposited over a rough substrate, such as sidewalls  47  of individual trenches  46 .  
         [0046]    Referring to FIG. 17, a mask  50  of photoresist material  52  is formed upon conductive material  48  of assembly  30  as depicted. The photoresist is deposited and patterned to form the depicted mask  50  over substrate  40 .  
         [0047]    Referring to FIG. 18, conductive material  48  is patterned utilizing mask  50 . Such patterning removes conductive material  48  from bottom surfaces  49  and adjacent portions of sidewalls  47  of trenches  46 .  
         [0048]    Referring to FIG. 19, photoresist material  52  comprising mask  50  of FIG. 18 has been stripped from assembly  30  leaving remaining conductive material  48  outwardly exposed.  
         [0049]    Referring to FIG. 20, substrate material  41  of substrate  40  adjacent to lower portions of trenches  46  is next isotropically etched using conductive material  48  as a mask. A SF 6  plasma silicon release etch chemistry is utilized according to one processing methodology to etch substrate material  41 . Other etch chemistries are possible including XeF 2 , for example. The depicted process step releases and defines a microstructure device feature  54  of microstructure device  31 . Microstructure device feature  54  is intermediate trenches  46  as shown.  
         [0050]    Referring to FIG. 21, further details of assembly  30  comprising microstructure device  31  are illustrated. Microstructure device feature  54  is coupled with substrate  40  and forms a cantilevered extension from substrate  40  in the described exemplary embodiment. Microstructure device feature  54  comprises monolithic substrate material  41  which extends from substrate  40 . In the depicted arrangement, microstructure device feature  54  is coupled with substrate  40  at a first end  58  while a second end  60  is configured to move relative to substrate  40 . Conductive material  48  is formed directly upon the monolithic microstructure device feature  54  according to aspects of the invention.  
         [0051]    As shown, microstructure device feature  54  and substrate  40  have opposing sidewalls  47  adjacent to and spaced from one another. The depicted sidewalls  47  are arranged to face one another intermediate first end  58  and second end  60  of the exemplary microstructure device feature  54 . Conductive material  48  is provided directly upon an upper surface  56  and sidewalls  47  of microstructure device feature  54  and directly upon sidewalls  47  and an upper surface  61  of substrate  40 .  
         [0052]    Conductive material  48  upon sidewalls  47  of substrate  40  define conductive structures  62 . Conductive material  48  provided upon sidewalls  47  of microstructure device feature  54  provide conductive structures  64 . In the depicted arrangement, conductive structures  62 ,  64  form capacitor electrodes of plural capacitors  66 . In the described embodiment, conductive structures  62 ,  64  are provided directly upon sidewalls  47  comprising substrate material  41  of respective ones of microstructure device feature  54  and substrate  40 .  
         [0053]    In the depicted embodiment of microstructure device  31 , microstructure device feature  54  including conductive structures  64  is a capacitive actuator which may be actuated responsive to the application of biasing voltages to one or more of conductive structures  62 ,  64 . In particular, conductive structures  62 ,  64  are biased during operations to create electrostatic forces that result in movement of end  60  of microstructure device feature  54 . The microstructure device feature  54  may be referred to as a capacitive micro-electromechanical actuator  68 .  
         [0054]    Titanium nitride has been shown to deposit conformally on silicon using chemical vapor deposition even though sidewalls  47  comprising silicon in the described embodiment may exhibit a rough surface profile after trenches  46  are formed within substrate  40 . The resultant conductive structures  62 ,  64  upon sidewalls  47  result in a titanium nitride layer having lower surface roughness compared with the prior art processes wherein the roughness or scallops on the surface of the silicon is replicated in subsequent oxide and aluminum layers. Such roughness may degrade the performance of the resultant prior art devices.  
         [0055]    Accordingly, in embodiments wherein titanium nitride is utilized, opposing conductive structures  62 ,  64  of conductive material  48  have substantially smooth outwardly exposed surfaces. Provision of such surfaces is beneficial to improve controllability of conductive structures  62 ,  64  forming the capacitor electrodes and to improve the functionality of the resultant microstructure device  31  in accordance with the described embodiment.  
         [0056]    Titanium nitride is additionally more resistant than aluminum to attack if SF 6  plasma silicon release etch chemistry is utilized in processing of assembly  30  depicted in FIG. 20. Utilization of titanium nitride in accordance with aspects of the invention provides conductive structures  62 ,  64  which are more robust than prior art structures.  
         [0057]    Inasmuch as conductive structures  62 ,  64  upon substrate  40  are conductors, there is no need for aluminum deposition. Direct formation of conductive structures  62 ,  64  on substrate  40  in accordance with aspects of the invention reduces process complexity by eliminating oxide deposition and etch steps utilized in the prior art processes. In addition, there is no need to open contact windows through an intermediate insulating layer (e.g., layer  12   a  illustrated in FIG. 5 of the prior art process) inasmuch as conductive material  48  is deposited upon the upper surface  61  of substrate  40 . Further, the geometry of the resultant devices  31  of the invention is improved over the prior art devices S wherein the formation of additional oxide layers reduces lateral dimensions. In addition, processing according to the present invention eliminates the need for processing following the release step shown in FIG. 20 utilized in the Saif and MacDonald process described above.