Abstract:
A method for providing an interpolated output signal includes, in at least one aspect, receiving a plurality of phase signals applying each phase signal of the plurality of phase signals to switching elements of a first set of switching elements receiving a plurality of select signals, applying an asserted select signal to a first switching element of a second set of switching elements to provide a connection between a first switching element of the first set of switching elements and a first output terminal, and applying the asserted select signal to a second switching element of the second set of switching elements to provide a connection between a second switching element of the first set of switching elements and a second output terminal.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This disclosure claims the benefit of priority of U.S. application Ser. No. 11/006,189, filed on Dec. 6, 2004, issued on Jul. 24, 2012, as U.S. Pat. No. 8,228,110, and titled “LOW POWER, LOW VOLTAGE PHASE INTERPOLATOR,” the disclosure of which is hereby incorporated by reference in its entirety. 
     BACKGROUND 
     The following disclosure relates to electrical circuits and signal processing. 
     A phase interpolator is a circuit that can be used within an integrated circuit to adjust a phase of a signal (e.g., a clock signal). A phase interpolator can be used in a variety of applications. For example, a phase interpolator can be implemented within a receiver to adjust a phase of a sampling clock, or within a write precompensation circuit (e.g., of a hard disk drive system) to adjust a phase of a write clock. 
       FIG. 1  shows one example of a conventional phase interpolator  100 . Phase interpolator  100  includes a differential pair having a pair of differential inputs PH 1 , PH 1 Bar (complement of PH 1 ), PH 2 , PH 2 Bar (complement of PH 2 ), and differential outputs OUT 1 , OUT 1 Bar (complement of OUT 1 ). Phase interpolator  100  includes bias currents I 1 -I 2 , transistors M 1 -M 4 , and resistors R 1 -R 2 . In general, phase interpolator  100  provides a phase shift for a signal that is an interpolation between phase signals PH 1  and PH 2 . Phase interpolator  100  provides the phase shift based on bias currents I 1  and I 2 . For example, if bias current I 1  is turned off, then phase interpolator  100  provides an output signal OUT 1  having a phase that is substantially equal to that of phase signal PH 2 . And if bias currents I 1  and I 2  are substantially equal, then phase interpolator  100  provides an output signal OUT 1  having a phase that is substantially in between those of phase signals PH 1  and PH 2 . 
     As bias current I 1  or I 2  is changed, a common mode component of output signals OUT 1  and OUT 1 Bar varies, and phase interpolator  100  therefore requires a certain amount of time to settle in order to provide an output signal having an accurate phase shift. In addition, phase interpolator  100  may require a large buffer to drive each of phase signals PH 1 , PH 1 Bar, PH 2  and PH 2 Bar. Such buffers typically require a large power supply (e.g., greater than 1.5 Volts). A change in a bias condition (e.g., including a large power supply) can impact interpolator linearity. 
     SUMMARY 
     In general, in one aspect, this specification describes a phase interpolator that is operable to provide an interpolated output signal through an output node. The phase interpolator includes a first and second interpolator module, each having an output in communication with the output node. The first interpolator includes an input to receive a first plurality of input phase signals, and a selector to select one or more of the first plurality of input phase signals for interpolation at the output node of the phase interpolator. The second interpolator module includes an input to receive a second plurality of input phase signals, and a selector to select one or more of the second plurality of input phase signals for interpolation at the output node of the phase interpolator. Each of the selected ones of the first plurality of input signals and each of the selected ones of the second plurality of input signals are included in the interpolated output signal. 
     Particular implementations can include one or more of the following. The first interpolator module and the second interpolator module can each include one or more interpolator core cells. Each interpolator core cell can be operable to provide a single instance of a given input phase signal to the output node for interpolation. Each interpolator core cell can receive as inputs one or more select signals operable to select a given input phase signal to be provided to the output node. Each interpolator core cell can include only NMOS or PMOS transistors. The selector in the first interpolator module and the selector in the second interpolator module can be substantially in common. The phase interpolator can operate using a power supply that is less than 1.2 Volts. Each of the first plurality of input phase signals can have a different phase relative to other ones of the first plurality of input phase signals. Each of the second plurality of input phase signals can have a different phase relative to other ones of the second plurality of input phase signals. The first plurality of input phase signals, the second plurality of input phase signals, and the interpolated output signal can be differential signals. 
     The phase interpolator can further include a third interpolator module having an output in communication with each of the output of the first interpolator module and the output of the second interpolator module. The third interpolator module can include an input to receive a third plurality of input phase signals, and a selector to select one or more of the third plurality of input phase signals for interpolation at the output node of the phase interpolator. 
     In general, in another aspect, this specification describes a phase interpolator operable to provide an interpolated output signal through an output node. The phase interpolator includes a first and second interpolator module, each having an output in communication with the output node. The first interpolator includes a plurality of first switches to receive a corresponding first plurality of input phase signals, and a plurality of second switches in communication with corresponding ones of the first plurality of switches. Each of the plurality of second switches are operable to assert one or more of the first plurality of input phase signals for interpolation at the output node of the phase interpolator. The second interpolator module includes a plurality of third switches to receive a corresponding second plurality of input phase signals, and a plurality of fourth switches in communication with corresponding ones of the third switches. Each of the plurality of fourth switches are operable to assert one or more of the second plurality of input phase signals for interpolation at the output node of the phase interpolator. Each of the asserted ones of the first plurality of input signals and each of the asserted ones of the second plurality of input signals are included in the interpolated output signal. 
     Particular implementations can include one or more of the following. Each of the first, second, third and fourth transistors can comprise only NMOS or PMOS transistors. The interpolated output signal can be provided to a load. The load can be associated with one or more of a serial ATA (Advanced Technology Architecture) communication system, a read channel, a fiber channel, a wireless baseband communication system, an ethernet XAUI SERDES transceiver, a 1000 BaseTx network, a USB (Universal Serial Bus) 2.0 bus, or a PCI Express bus. 
     In general, in another aspect, this specification describes a disk drive system. The disk drive system includes a read channel configured to provide a data stream to be recorded onto a surface of a disk, and a write precompensation circuit operable to precompensate each data bit of the data stream. The write precompensation circuit includes a phase interpolator operable to provide a predetermined delay (through an output node) of a write clock to precompensate each data bit of the data stream. The phase interpolator includes a first and second interpolator module, each having an output in communication with the output node. The first interpolator includes an input to receive a first plurality of input phase signals, and a selector to select one or more of the first plurality of input phase signals for interpolation at the output node of the phase interpolator. The second interpolator module includes an input to receive a second plurality of input phase signals, and a selector to select one or more of the second plurality of input phase signals for interpolation at the output node of the phase interpolator. Each of the selected ones of the first plurality of input signals and each of the selected ones of the second plurality of input signals are included in the interpolated output signal. The disk drive system further includes a read/write head operable to write the precompensated data bits onto the surface of the disk. 
     Implementations can include one or more of the following advantages. A phase interpolator circuit is provided that consumes low power. In one implementation, the phase interpolator circuit operates based on a power supply that is substantially 1.2 Volts or lower. 
     In one implementation, a phase interpolator is provided that includes plural interpolator modules. Each interpolator module is designed so that only the output(s) of each interpolator module need be in communication with one another. To increase a resolution of the phase interpolator, additional interpolator modules can be added to the phase interpolator including coupling each additional interpolator module to the output(s) of the phase interpolator. Such a modular design reduces complexities in layout of a high resolution phase interpolator. In addition, a high resolution phase interpolator can be implemented within a smaller area of an integrated circuit chip relative to conventional phase interpolator designs. 
     The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description and drawings, and from the claims. 
    
    
     
       DESCRIPTION OF DRAWINGS 
         FIG. 1  is a schematic diagram of a conventional phase interpolator. 
         FIG. 2  is block diagram of a phase interpolator. 
         FIG. 3  is a timing diagram illustrating the input phase signals of the phase interpolator of  FIG. 2 . 
         FIG. 4  is a schematic diagram of an interpolator core cell within an interpolation module of  FIG. 2 . 
         FIG. 5  is a schematic block diagram of a hard disk drive system. 
     
    
    
     Like reference symbols in the various drawings indicate like elements. 
     DETAILED DESCRIPTION 
       FIG. 2  illustrates a block diagram of a phase interpolator  200 . In one implementation, phase interpolator  200  includes circuitry for generating differential output signals OUT, OUTBar (complement of OUT) having a phase that is shifted relative to those of one or more differential input phase signals (e.g., phase signals PH 1 -PH 8 ). Differential output signals OUT, OUTBar can be provided to a load  202 . Load  202  can be associated with a variety of applications. For example, example applications include a serial ATA (Advanced Technology Architecture) communication system, a read channel, a fiber channel, a wireless baseband communication system, an ethernet XAUI SERDES transceiver, a 1000 BaseTx network, a USB (Universal Serial Bus) 2.0 bus, a PCI Express bus, and so on. 
     Phase interpolator  200  includes multiple interpolator modules, and, specifically, in the implementation shown, two interpolator modules  202 ,  204  are included. Though two interpolation modules  202 ,  204  are illustrated in  FIG. 2  by way of example, phase interpolator  200  can contain additional interpolator modules. Each interpolator module contains one or more interpolator core cells (not shown) that are each operable to output a selected differential input phase signal for interpolation at outputs OUT, OUTBar, as discussed in greater detail below. 
     Interpolator module  202  receives as inputs differential phase signals (e.g., phase signals PH 1 , PH 3 , PH 5  and PH 7 ). Interpolator module  204  receives as inputs differential phase signals (e.g., phase signals PH 2 , PH 4 , PH 6  and PH 8 ).  FIG. 3  shows a timing diagram, for one implementation, of phase signals PH 1 -PH 8 . Though (8) phase signals are shown (e.g., phase signals PH 1 -PH 8 ), any number of phase signals can be interpolated through interpolator modules  202 ,  204 . For example, in one implementation (4) phase signals are interpolated through interpolator modules  202 ,  204 . As shown in  FIG. 3 , each phase signal PH 1 -PH 8  has a delay time of ΔT*(i+1) [i=0, 1, . . . , 0] with respect to phase signal PH 1 . In the example of  FIG. 3 , in which a cycle of phase signal PH 1  is T, the delay time ΔT is approximately equal to T/8 (e.g., 45°). Together, interpolator modules  202 ,  204  output differential output signals OUT, OUTBar that are an interpolation between any combination of phase signals PH 1 -PH 8 . 
     Each interpolator module  202 ,  204  is powered by a low voltage supply VDD. In one implementation, VDD is substantially equal to 1.2 Volts. Alternatively, VDD can be substantially lower than 1.2 Volts (e.g., 0.7-0.9 Volts). Unlike a conventional phase interpolator that may require a high voltage power supply, phase interpolator  200  does not require a large supply voltage in order to interpolate various phase signals. 
     Each interpolator module  202 ,  204  further receives as inputs one or more SELECT signals. Each SELECT signal is operable to select a given differential input phase signal (within a given interpolator core cell) for interpolation at outputs OUT, OUTBar, as discussed in greater detail below. 
       FIG. 4  illustrates one implementation of an interpolator core cell  400  within an interpolator module (e.g., interpolator module  202 ). Interpolator core cell  400  includes transistors M 7 -M 22 , voltage bias sources Vbias 1 , Vbias 2 , and a current source  402 . In one implementation, current source  402  provides a bias current to one or more transistors within interpolator core cell  400 . In one implementation, each of transistors M 7 -M 22  are NMOS transistors or PMOS transistors. 
     The source of transistors M 7 -M 14  is in communication with the drains of transistors M 15 -M 22 , respectively. The sources of transistors M 15 , M 22  are respectively in communication with voltage bias sources Vbias 1 , Vbias 2 . The sources of transistors M 18 -M 21  are in communication with a low-side power supply VSS (e.g., 0 Volts). The gates of transistors M 7 , M 14  are in communication with select signal SEL 1 . The gates of transistors M 8 , M 13  are in communication with select signal SEL 2 . The gates of transistors M 9 , M 11  are in communication with select signal SEL 3 . The gates of transistors M 10 , M 12  are in communication with select signal SEL 4 . The gates of transistors M 15 , M 20  are in communication with input phase signal PH 1 . The gates of transistors M 16 , M 21  are in communication with input phase signal PH 3 . The gates of transistors M 17 , M 21  are in communication with input phase signal PH 7 . The gates of transistors M 18 , M 22  are in communication with input phase signal PH 5 . Interpolator module  204  can include a similar interpolator core cell (not shown) having as inputs, in the example shown, input phase signals PH 2 , PH 4 , PH 6  and PH 8 . 
     In operation, interpolator core cell  400  is operable to output a selected differential input phase signal for interpolation at outputs OUT, OUTBar based on select signals SEL 1 -SEL 4 . For example, to provide differential input phase signals PH 1  (0°) and PH 5  (180°) at the outputs OUT, OUTBar, respectively, interpolator core cell  400  can operate as follows. A control circuit or a switching circuit (not shown) asserts select signal SEL 1 , and deasserts each of select signals SEL 2 -SEL 4 . A conventional control circuit (or selector) can be used to assert or deassert each select signal SEL 1 -SEL 4 . In response to the voltage level settings of select signals SEL 1 -SEL 4 , transistors M 7  and M 14  are enabled (e.g., turned on) and transistors M 8 -M 13  are each disabled (e.g., turned off). As phase signal PH 1  goes high (and phase signal PH 5  goes low), a high reference voltage appears at output OUT, and a low reference voltage appears at output OUTBar. As phase signal PH 1  goes low (and phase signal PH 5  goes high), a low reference voltage appears at output OUT, and a high reference voltage appears at output OUTBar. 
     As discussed above, interpolator modules  202 ,  204  can each include one or more interpolator core cells (e.g., interpolator core cell  400 ). In one implementation, each interpolator module  202 ,  204  of phase interpolator  200  includes (16) interpolator core cells that are each operable to output a given differential input phase signal for interpolation at outputs OUT, OUTBar. In this implementation, phase interpolator  200  can output a differential output signal OUT, OUTBar having a phase with a resolution (e.g., step size= 1/16 th ) between any two given input phase signals (e.g., input phase signals PH 1 -PH 8 ). For example, to provide an output signal OUT having a phase that is ( 1/16 th ) between input phase signals PH 1  and PH 2 , a control circuit (not shown) controls one of the (16) interpolator core cells of interpolator module  202  to provide a single instance of input phase signal PH 1  at output OUT 1 . The control circuit also controls all (16) interpolator core cells of interpolator module  204  to provide (16) instances of input phase signal PH 2  at output OUT 1 . 
     In general, each interpolator module  202 ,  204  can contain any number of interpolator core cells, and any number of phase input signals to provide various granularities of resolution for phase shifting a signal. 
     Phase interpolator  200  can be used with circuitry of a disk drive system  500 , as shown in  FIG. 5 . Disk drive system  500  includes a read/write head  502 , a write precompensation circuit  504 , and a read channel  506 . 
     In a write operation, a data stream to be recorded is provided by read channel  506  to write precompensation circuit  504 . Write precompensation circuit  504  precompensates each data bit of the data stream and provides precompensated data to read/write head  502 . In one implementation, phase interpolator  200  provide a predetermined delay (or phase shift) of a write clock to precompensate the data being sent to read/write head  502 . Read/write head  502  locates an appropriate sector of a disk (not shown) and writes the precompensated data onto the disk. 
     A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, one or more of transistors M 5 -M 22  can be PMOS transistors. Accordingly, other implementations are within the scope of the following claims.