Abstract:
In a shift switch circuit for replacing a data line, a transmission gate circuit connecting node N 2  corresponding to ith write data line to node N 4  corresponding to ith read data line is provided. An operation of the shift switch circuit can be confirmed according to whether or not an output corresponding to provided data input signal D&lt;i&gt; is observed as data output signal Q&lt;i&gt;. Preferably, a transmission gate connecting i+1th write data line to an output data line is further provided, in order to further ensure operation confirmation. When a fuse circuit is set to replace a data line, ratio of successful chip repairing will be higher.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a semiconductor memory device, and more specifically to a semiconductor memory device having a data line redundancy replacement circuit of a shifting type.  
         [0003]     2. Description of the Background Art  
         [0004]     A semiconductor memory device has redundancy memory cells in addition to normal memory cells. Yield is enhanced by replacing and repairing defective memory cell among normal memory cells with a redundancy memory cell.  
         [0005]     Recently, there has been a strong demand to increase bus width in order to improve data transfer rate. Accordingly, the number of data lines tends to be larger, correspondingly making the number of column address smaller. Particularly in a dynamic random access memory (DRAM) embedded along with a logic circuit on a semiconductor device to implement system-on-chip, a configuration has been changing from one with 32-bit bus width and 256-bit column address (adopted in a conventional memory) to, for example, one with 256-bit bus width and 16-bit column address.  
         [0006]     Conventionally, a defective chip has been repaired through replacement of a bit line by making a switch of a column address. When the number of columns is small, however, high repair ratio cannot be expected without preparing a relatively large number of redundancy memory cells. Therefore, in many cases, a redundancy memory cell and a redundancy data line connected thereto are prepared so as to replace a data line connected to a defective memory cell or a data line having a defect (hereinafter, referred to as a defective data line) with a redundancy data line.  
         [0007]      FIG. 13  is a block diagram showing a conventional example of a semiconductor memory device with a data line redundancy replacement configuration.  
         [0008]     Referring to  FIG. 13 , a conventional semiconductor memory device includes: a memory cell array  502 ; a row decoder  504  selecting a row in memory cell array  502 ; a read amplifier and write driver circuit  506  reading and writing data from/to memory cell array  502  through a data line; a fuse circuit  508  programming replacement information according to a position of a defective data line; a shift information latch circuit  510  outputting shift control signal SFT&lt;n:0&gt; upon receiving an output from fuse circuit  508 ; a data line shift circuit  512  determining a data line pair to be used from n+1 normal data line pairs and a redundancy data line pair according to shift control signal SFT&lt;n:0&gt;; and an input/output circuit  514  communicating data with the data line pair selected by data line shift circuit  512 .  
         [0009]     N+1 normal data line pairs and a redundancy data line pair read and write data from/to memory cell array  502 . Read amplifier and write driver circuit  506  includes a plurality of read amplifier and write driver units  516 .  
         [0010]     Input/output circuit  514  includes a plurality of input/output buffers  518  corresponding to data signals DQ&lt;0&gt;-DQ&lt;n&gt; respectively. Data line shift circuit  512  includes shift switches  512 . 0 - 512 . n  corresponding to the plurality of input/output buffers  518  respectively.  
         [0011]     The normal data line pair includes data lines IO, NIO. The redundancy data line pair includes data lines SIO, NSIO.  
         [0012]     The data line pair IO, NIO is connected to a memory cell through a sense amplifier circuit and a bit line in memory cell array  502 . A read amplifier contained in read amplifier and write driver unit  516  amplifies data of the data line pair to generate a signal DBRA&lt;n+1:0&gt;. A write buffer circuit contained in read amplifier and write driver unit  516  drives the data line pair upon receiving a write data signal provided by signal DBWA&lt;n+1:0&gt;.  
         [0013]     If a defect is found in a data line in the memory cell array, those shift switches  512 . 0 - 512 . n  which correspond to the defective data line are switched so that data in a next adjacent data line can be used. By shifting all the data lines positioned higher in bits than the defective data line, a redundancy data line can be used in place of the defective data line.  
         [0014]      FIG. 14  is a circuit diagram showing a configuration of ith shift switch  512 . i  in  FIG. 13 .  
         [0015]     Referring to  FIG. 14 , shift switch  512 . i  includes: an inverter  538  receiving and inverting shift control signal SFT&lt;i&gt;; a transmission gate circuit  544  activated in accordance with an output of inverter  538  and transmitting signal DBWB&lt;i&gt; as signal DBWA&lt;i&gt;; and a transmission gate circuit  546  activated in accordance with shift control signal SFT&lt;i&gt; and transmitting signal DBWB&lt;i&gt; as signal DBWA&lt;i+1&gt;. Transmission gate circuit  544  is activated when shift control signal SFT&lt;i&gt; is “0”, while transmission gate circuit  546  is activated when shift control signal SFT&lt;i&gt; is “1”.  
         [0016]     Shift switch  512 . i  further includes a transmission gate circuit  540  activated in accordance with an output of inverter  538  and transmitting signal DBRA&lt;i&gt; as signal DBRB&lt;i&gt;; and a transmission gate circuit  542  activated in accordance with shift control signal SFT&lt;i&gt; and transmitting signal DBRA&lt;i+1&gt; as signal DBRB&lt;i&gt;. Transmission gate circuit  540  is activated when shift control signal SFT&lt;i&gt; is “0”, while transmission gate circuit  542  is activated when shift control signal SFT&lt;i&gt; is “1”.  
         [0017]     When shift control signal SFT&lt;i&gt; in  FIG. 14  is “0”, “no shift” is indicated and signals DBWA&lt;i&gt;, DBRA&lt;i&gt; are selected. On the other hand, when shift control signal SFT&lt;i&gt; is “1”, “shift” is indicated and signals DBWA&lt;i+1&gt;, DBRA&lt;i+1&gt; are selected.  
         [0018]      FIG. 15  is a circuit diagram showing a configuration of transmission gate circuit  544  in  FIG. 14 .  
         [0019]     Referring to  FIG. 15 , transmission gate circuit  544  includes: an inverter  552  receiving and inverting a signal provided to node E; a P channel MOS transistor connected between nodes A and B and receiving an output of inverter  552  at a gate; and an N channel MOS transistor  556  connected between nodes A and B and having a gate connected to node E. Transmission gate circuit  544  connects node A and node B when node E is supplied with H level, while it disconnects node A from node B when node E is supplied with L level.  
         [0020]     Transmission gate circuits  546 ,  540 ,  542  are of the same configuration as transmission gate circuit  544 , and description thereof will not be repeated.  
         [0021]      FIG. 16  shows relation between a defective data line and shift control signal SFT&lt;n:0&gt; in  FIG. 13 .  
         [0022]     Referring to  FIGS. 13 and 16 , when shift control signal is “0” or “1”, “no shift” or “shift” is indicated respectively.  
         [0023]     At initial setting, fuse circuit  508  has not been programmed and shift control signals SFT&lt;0&gt;-SFT&lt;n&gt; are all “0”. Connection status of shift switches  512 . 0 - 512 . n  in  FIG. 13  at that time is shown. At initial setting, redundancy data line pair is not used.  
         [0024]     For example if a defect FA is present in n-1th data line pair of 0-nth data line pairs, fuse circuit  508  will be programmed in such a way that shift control signals SFT&lt;0&gt;-SFT&lt;n−2&gt; are set to be “0” and shift control signals SFT&lt;n−1&gt;, SFT&lt;n&gt; are set to be “1”.  
         [0025]     Then, at initial state as shown in  FIG. 13 , connection of two shift switches (shift switches  512 . n− 1,  512 . n ) among shift switches  512 . 0 - 512 . n  connected to 0-nth normal data line pairs is changed. Consequently, input/output buffer  518  inputting/outputting signal DQ&lt;n&gt; is connected to a redundancy data line pair and an input/output buffer inputting/outputting signal DQ&lt;n−1&gt; is connected to nth normal data line pair. N-1th data line pair having a defect FA is not connected to any input/output buffer  518 .  
         [0026]     In above-described configuration of a semiconductor memory device, if a defect is found in the inside of memory cell array  502  as defect FA, a defective chip can be repaired by means of data line shift circuit  512 . If a defect is found in a connection path between data line shift circuit  512  and input/output circuit  514  or in the inside of data line shift circuit  512 , however, repairing thereof is impossible.  
         [0027]     Operation confirmation is performed per data line pair. Therefore, even if a defect is found in wafer testing, it is not possible to distinguish whether the defect is present in a data line (in which case a portion of memory cell array area can be repaired) or inside data line shift circuit  512  and input/output circuit  514 . Thus, even though a defect is found inside data line shift circuit  512  as defect FB or in a connection portion of data line shift circuit  512  and input/output circuit  514  as defect FC, the defect cannot be determined as irreparable, and fuse circuit  508  will be programmed in order to repair the data line.  
         [0028]     In particular, when a defect is present in a path as defect FB, which is not usually used for initial setting, presence of a defect could be determined only after actually programming fuse circuit  508  in an attempt to repair the chip. Programming fuse circuit  508  in such a case will cause lowering of repair ratio (yield ratio before and after repairing). Since programming fuse circuit  508  for an irreparable chip is useless, it is desirable to detect that a chip is irreparable and not to program the fuse circuit when that is the case.  
         [0029]     Particularly when test period should be shortened for the purpose of cost reduction, next assembly process is often carried out without conducting a test at wafer stage after fuse circuit  508  is programmed for repairing. In such a case, if repair ratio is low, test yield after assembly will decrease, which is a problem in terms of cost.  
       SUMMARY OF THE INVENTION  
       [0030]     An object of the present invention is to provide a semiconductor memory device capable of detecting a repairable chip to selectively program a fuse circuit and thus having improved repair ratio and production efficiency.  
         [0031]     In summary, according to the present invention, a semiconductor memory device having a test mode and a normal mode as operation modes includes a memory cell array, a plurality of read data lines, a plurality of write data lines, a replacement control circuit and a data line shift circuit.  
         [0032]     The memory cell array is divided into a plurality of areas. The plurality of read data lines are provided corresponding to the plurality of areas respectively to communicate data. The plurality of write data lines are provided corresponding to the plurality of areas respectively to communicate data. The replacement control circuit holds replacement information in a non-volatile manner and outputs a shift control signal in accordance with the replacement information. The data line shift circuit selects a prescribed number of read data lines to be used from the plurality of read data lines, and a prescribed number of write data lines to be used from the plurality of write data lines.  
         [0033]     The data line shift circuit includes a first switch circuit connecting, in the normal mode, either one of first and second write data lines of the plurality of write data lines to a first input node in accordance with the shift control signal and connecting, in the test mode, a first write data line to the first input node; a second switch circuit connecting, in the normal mode, either one of first and second read data lines of the plurality of read data lines to a first output node in accordance with the shift control signal and connecting, in the test mode, a first read data line to the first output node; and a first data transmission circuit activated in the test mode and transmitting data of the first write data line to the first read data line.  
         [0034]     According to an other aspect of the present invention, a semiconductor memory device having a test mode and a normal mode as operation modes includes a memory cell array, a plurality of data lines, a replacement control circuit and a data line shift circuit.  
         [0035]     The memory cell array is divided into a plurality of areas. The plurality of data lines are provided corresponding to the plurality of areas respectively to communicate data. The replacement control circuit holds replacement information in a non-volatile manner and outputs a shift control signal according to the replacement information. The data line shift circuit selects a prescribed number of data lines to be used from the plurality of data lines.  
         [0036]     The data line shift circuit includes a first switch circuit connecting either one of first and second data lines of the plurality of data lines to a first node in accordance with the shift control signal in the normal mode, and connecting both of the first and second data lines to the first node in the test mode; and a data transmission circuit activated in the test mode and transmitting data of the first data line to the second data line.  
         [0037]     Therefore, the principal advantage of the present invention is that a path to transmit data to a memory cell array through a data line shift circuit can be confirmed and that a chip can be repaired efficiently.  
         [0038]     The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0039]      FIG. 1  is a schematic block diagram showing an overall configuration of a semiconductor memory device in a first embodiment of the present invention.  
         [0040]      FIG. 2  is a block diagram showing a configuration of DRAM core MCR shown in  FIG. 1 .  
         [0041]      FIG. 3  is a circuit diagram showing a configuration of ith shift switch circuit  22  included in data line shift circuit  12  in  FIG. 2  and corresponding input/output buffer  18 .  
         [0042]      FIG. 4  is a circuit diagram showing a configuration of transmission gate circuit  34  in  FIG. 3 .  
         [0043]      FIG. 5  is a diagram of operation waveforms illustrating a test operation of shift switch circuit  22  shown in  FIG. 3 .  
         [0044]      FIG. 6  is a circuit diagram showing a configuration of shift switch circuit  22   a  and input/output buffer  18   a  used in a second embodiment.  
         [0045]      FIG. 7  is a diagram of operation waveforms illustrating an operation in testing, of shift switch circuit  22   a  shown in  FIG. 6 .  
         [0046]      FIG. 8  is a circuit diagram showing a configuration of shift switch circuit  22   b  used in a third embodiment.  
         [0047]      FIG. 9  illustrates an operation of shift switch circuit  22   b  shown in  FIG. 8 .  
         [0048]      FIG. 10  shows a variation when data input and output are separate.  
         [0049]      FIG. 11  is a circuit diagram showing a configuration of shift switch circuit  22   d  and input/output buffer  18   d  used in a fourth embodiment.  
         [0050]      FIG. 12  is a diagram of operation waveforms illustrating an operation of the circuit shown in  FIG. 11 .  
         [0051]      FIG. 13  shows an example of a semiconductor memory device with a conventional data line redundancy replacement configuration.  
         [0052]      FIG. 14  is a circuit diagram showing a configuration of ith shift switch  512 . i  in  FIG. 13 .  
         [0053]      FIG. 15  is a circuit diagram showing a configuration of transmission gate circuit  544  in  FIG. 14 .  
         [0054]      FIG. 16  shows relation between a defective data line and shift control signal SFT&lt;n:0&gt; in  FIG. 13 . 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0055]     In the following, embodiments of the present invention will be described in detail with reference to the figures. It is noted that the same reference characters refer to the same or corresponding components in the figures.  
         [0056]     (First Embodiment)  
         [0057]      FIG. 1  is a schematic block diagram showing an overall configuration of a semiconductor memory device in a first embodiment of the present invention.  
         [0058]     Referring to  FIG. 1 , a semiconductor memory device  1  which is a logic-embedded DRAM includes a large scale logic LG communicating signal LPGA with the outside; a DRAM core MCR controlled by large scale logic LG and communicating data therewith; and a test interface circuit TIC which, in testing, instead of large scale logic LG, provides a control signal and input data to DRAM core MCR and receives read data output from the same.  
         [0059]     Test interface circuit TIC communicates test signal group TPG with the outside. Test signal group TPG includes input data D&lt;i&gt;, output data Q&lt;i&gt;, command signal COMMAND, address signal ADDRESS and the like.  
         [0060]     DRAM core is supplied with power supply potential VCC from terminal PST. DRAM core MCR can also be provided directly from the outside with test control signals, such as TMBUSCHK 1 , TMBUSCHK 2 , TMBUSCHKR and TMBUSCHKW, for a test described later.  
         [0061]      FIG. 2  is a block diagram showing a configuration of DRAM core MCR shown in  FIG. 1 .  
         [0062]     Referring to  FIG. 2 , DRAM core MCR includes: a memory cell array  2 ; a row decoder  4  selecting a row in memory cell array  2 ; a read amplifier and write driver circuit  6  reading and writing data from/to memory cell array  2  through a data line; a fuse circuit  8  programming replacement information according to a position of a defective data line; a shift information latch circuit  10  outputting shift control signal SFT&lt;n:0&gt; upon receiving an output of fuse circuit  8 ; a data line shift circuit  12  determining a data line pair to be used from n+1 normal data line pairs and a redundancy data pair in accordance with shift control signal SFT&lt;n:0&gt;; and an input/output circuit  14  communicating data with the data line pair selected by data line shift circuit  12 .  
         [0063]     N+1 pairs of normal data lines and a redundancy data line pair read and write data from/to memory cell array  2 . The memory cell array is divided into a plurality of areas, which are allocated to n+1 normal data line pairs and the redundancy data line pair respectively. Read amplifier and write driver circuit  6  includes a plurality of read amplifier and write driver units  16 .  
         [0064]     Input/output circuit  14  includes a plurality of input/output buffers  18  corresponding to data signals DQ&lt;0&gt;-DQ&lt;n&gt; respectively.  
         [0065]     The normal data line pair includes data lines IO, NIO. The redundancy data line pair includes data lines SIO, NSIO.  
         [0066]     The pair of data lines IO, NIO is connected to a memory cell through a sense amplifier circuit and a bit line in memory cell array  2 . A read amplifier contained in read amplifier and write driver unit  16  amplifies data of the data line pair to generate a signal DBRA&lt;n+1:0&gt;. A write buffer circuit contained in read amplifier and write driver unit  16  drives the data line pair upon receiving a write data signal provided by signal DBWA&lt;n+1:0&gt;.  
         [0067]      FIG. 3  is a circuit diagram showing a configuration of ith shift switch circuit  22  included in data line shift circuit  12  in  FIG. 2  and corresponding input/output buffer  18 .  
         [0068]     Referring to  FIG. 3 , input/output buffer  18  includes an AND circuit  48  outputting signal DBWB&lt;i&gt; upon receiving control signal WE and input data signal D&lt;i&gt;; and a tristate buffer circuit  50  outputting data output signal Q&lt;i&gt; when control signal OE is activated, upon receiving signal DBRB&lt;i&gt;.  
         [0069]     Shift switch circuit  22  includes an inverter  24  receiving and inverting test control signal TMBUSCHK 1  and outputting signal NTMBUSCHK; an AND circuit  26  outputting signal SFTE&lt;i&gt; upon receiving shift control signal SFT&lt;i&gt; and signal NTMBUSCHK; inverters  36 ,  38  receiving and inverting signal SFTE&lt;i&gt;; and an inverter  28  receiving and inverting test control signal TMBUSCHK 1 .  
         [0070]     Shift switch circuit  22  further includes a transmission gate  44  having node B connected to node N 1  provided with signal DBWB&lt;i&gt; and node A connected to node N 2  outputting signal DBWA&lt;i&gt;, and receiving an output of inverter  38  at node E; a transmission gate circuit  46  having node A connected to node N 3  outputting signal DBWA&lt;i+1&gt; and node B connected to node N 1 , and receiving signal SFTE&lt;i&gt; at node E; and a transmission gate circuit  34  having node A connected to node N 2  and node B connected to node N 4 , and receiving test control signal TMBUSCHK 1  at node E.  
         [0071]     Shift switch circuit  22  further includes a transmission gate circuit  30  having node A connected to node N 6  provided with signal DBRA&lt;i&gt; and node B connected to node N 4 , and receiving an output of inverter  28  at node E; a transmission gate circuit  32  having node A connected to node N 7  provided with signal DBRA&lt;i+1&gt; and node B connected to node N 5 , and receiving an output of inverter  28  at node E; a transmission gate circuit  40  having node A connected to node N 4  and node B connected to node N 8  outputting signal DBRB&lt;i&gt;, and receiving an output of inverter  36  at node E; and a transmission gate circuit  42  having node A connected to node N 5  and node B connected to node N 8 , and receiving signal SFTE&lt;i&gt; at node E.  
         [0072]      FIG. 4  is a circuit diagram showing a configuration of transmission gate circuit  34  in  FIG. 3 .  
         [0073]     Referring to  FIG. 4 , transmission gate circuit  34  includes an inverter  52  inverting a signal provided to node E; a P channel MOS transistor  54  connected between nodes A and B and receiving an output of inverter  52  at a gate; and an N channel MOS transistor  56  connected between nodes A and B and having a gate connected to node E.  
         [0074]     Transmission gate circuit  34  connects nodes A and B when node E is supplied with H level, while it disconnects node A from node B when node E is supplied with L level.  
         [0075]      FIG. 5  is a diagram of operation waveforms illustrating a test operation of shift switch circuit  22  shown in  FIG. 3 .  
         [0076]     Referring to  FIGS. 3 and 5 , an operation in a test mode is shown, in which test control signal TMBUSCHK 1  is set to H level after time t2, though until time t2 a normal operation is performed, that is, operation is in a normal mode.  
         [0077]     First, at time t0-t1, test control signal TMBUSCHK 1  is set to L level and a value “0” is given to shift control signal SFT&lt;i&gt;. Then AND circuit  26  outputs shift control signal SFT&lt;i&gt; as it is, so that signal SFTE&lt;i&gt; is “0”. Control signals WE, OE and data input signal D&lt;i&gt; are valid, and accordingly, data output signal Q&lt;i&gt; is output.  
         [0078]     At time t1-t2, shift control signal SFT&lt;i&gt; is set to “1”. AND circuit  26  then outputs shift control signal SFT&lt;i&gt; as it is, as signal SFTE&lt;i&gt;. Here again, control signals WE, OE and data input signal D&lt;i&gt; are valid, and accordingly, data output signal Q&lt;i&gt; is output.  
         [0079]     At time t2-t3, a test to determine whether data line shift circuit  12  and input/output circuit  14  function normally or not is conducted prior to programming fuse circuit  8  in  FIG. 2 .  
         [0080]     As test control signal TMBUSCHK 1  is set to H level after time t2, signal SFTE&lt;i&gt; is set to “0” regardless of a value of shift control signal SFT&lt;i&gt;. Signals WE 1 , OE 1  are both forcibly set to “1”. Here, when “1” is given as data input signal D&lt;i&gt;, this value is output as data output signal Q&lt;i&gt; via nodes N 1 , N 2 , N 4  and N 8 .  
         [0081]     When “0” is given as data input signal D&lt;i&gt; at time t3, this value is similarly output as data output signal Q&lt;i&gt; via nodes N 1 , N 2 , N 4  and N 8 .  
         [0082]     By confirming a match between input data signal D&lt;i&gt; and output data signal Q&lt;i&gt; after time t2, whether a data bus is defective or not can be examined.  
         [0083]     As described above, according to the first embodiment of the present invention, in a memory having data line redundancy replacement of a shifting type, a defect in a data bus between an input/output buffer and a shift switch can be detected, and the cost for testing and assembly can be reduced.  
         [0084]     (Second Embodiment)  
         [0085]     In a second embodiment, an example will be described, in which a write data line and a read data line are separate and each has a shift switch, while input/output of data from/to the outside is performed through a common input/output data bus.  
         [0086]      FIG. 6  is a circuit diagram showing a configuration of shift switch circuit  22   a  and input/output buffer  18   a  used in the second embodiment.  
         [0087]     Referring to  FIG. 6 , in a configuration of input/output buffer  18  shown in  FIG. 3 , input/output buffer  18   a  includes an AND circuit  66  instead of AND circuit  48  and a tristate buffer circuit  68  instead of tristate buffer circuit  50 .  
         [0088]     AND circuit  66  has one input connected to a node from/to which data signal DQ&lt;i&gt; is input/output, receives signal WE at other input, and outputs signal DBWB&lt;i&gt; to node N 1 .  
         [0089]     Tristate buffer circuit  68  is activated upon receiving signal OE and outputs signal DBRB&lt;i&gt; as data signal DQ&lt;i&gt;.  
         [0090]     Other configuration of input/output buffer  18   a  is the same as that of input/output buffer  18 , and description thereof will not be repeated.  
         [0091]     In a configuration of shift switch circuit  22  shown in  FIG. 3 , shift switch circuit  22   a  includes a data transmission circuit  60  instead of transmission gate circuit  34 .  
         [0092]     Data transmission circuit  60  includes a D flip-flop  62  taking in a signal transmitted to node N 2 , in response to clock signal CLK; and a clocked inverter  64  activated by test control signal TMBUSCHK 1  and receiving and inverting an output of D flip-flop  62 . An output from clocked inverter  64  is connected to node N 4 .  
         [0093]     In a normal operation, test control signal TMBUSCHK 1  is set to L level, clocked inverter  64  is inactivated, and transmission gate circuits  30 ,  32  are activated. Shift switch circuit  22   a  determines to which of nodes N 2 , N 3  signal DBWB&lt;i&gt; should be transmitted, in response to shift control signal SFT&lt;i&gt;.  
         [0094]     Similarly, which of signals DBRA&lt;i&gt; and DBRA&lt;i+1&gt; should be transmitted to node N 8  will also be determined in accordance with shift control signal SFT&lt;i&gt;.  
         [0095]     Next, a testing operation will be described.  
         [0096]      FIG. 7  is a diagram of operation waveforms illustrating an operation in testing, of shift switch circuit  22   a  shown in  FIG. 6 .  
         [0097]     Referring to  FIGS. 6 and 7 , first, control signal WE is activated to H level and an input D for testing is then given to an input/output node of input/output buffer  18   a . When clock signal CLK rises from L level to H level at time t1, a signal which has been transmitted as far as node N 2  is taken into D flip-flop  62 . The signal taken in and held is then transmitted to node N 4  by clocked inverter  64  and to node N 8  through transmission gate circuit  40 . When control signal OE is activated to H level at time t2, a test result signal Q is output to the input/output node of input/output buffer  18   a . Here, transmission gate circuits  44 ,  40  are in a conducting state and transmission gate circuits  46 ,  30 ,  32  and  42  are in a non-conducting state.  
         [0098]     Data is inverted between the input and the output by clocked inverter  64  so that write data of a shared bus connected to the input/output node of input/output buffer  18   a  will not remain when reading.  
         [0099]     As described above, inputting data from DQ&lt;i&gt; in synchronization with clock signal CLK, the data is once latched at the flip-flop, and the data inverted at next clock is output as signal DQ&lt;i&gt;. By confirming that the inverted data is provided as output data with respect to the input data, whether a data bus is defective or not can be examined.  
         [0100]     (Third Embodiment)  
         [0101]      FIG. 8  is a circuit diagram showing a configuration of shift switch circuit  22   b  used in a third embodiment.  
         [0102]     Referring to  FIG. 8 , in a configuration of shift switch circuit  22   a  shown in  FIG. 6 , shift switch circuit  22   b  includes NOR circuits  80 ,  82 , an inverter  76  and a transmission gate circuit  78  instead of inverter  24 , AND circuit  26  and transmission gate circuit  32 .  
         [0103]     NOR circuit  80  receives shift control signal SFT&lt;i&gt; and test control signal TMBUSCHK 2 . NOR circuit  82  outputs signal SFTE&lt;i&gt; upon receiving test control signal TMBUSCHK 1  and an output of NOR circuit  80 . Inverter  76  receives and inverts test control signal TMBUSCHK 2 . Transmission gate circuit  78  has node A connected to node N 7  and node B connected to node N 5 , and receives an output of inverter  76  at node E. Transmission gate circuit  78  is of the same configuration as transmission gate circuit  34  shown in  FIG. 4 , and description thereof will not be repeated.  
         [0104]      FIG. 9  shows a diagram illustrating an operation of shift switch circuit  22   b  shown in  FIG. 8 .  
         [0105]     Referring to  FIGS. 8 and 9 , in a normal operation, both test control signals TMBUSCHK 1  and TMBUSCHK 2  are at L level, clocked inverters  74 ,  64  are inactivated and transmission gate circuits  30 ,  78  are in a conducting state. Shift switch circuit  22   b , in accordance with signal SFTE&lt;i&gt;, makes a switch between DBWA&lt;i&gt; and DBWA&lt;i+1&gt;, that is, determines to which side signal DBWB&lt;i&gt; provided to node N 1  should be transmitted. Similarly, shift switch circuit  22   b , in accordance with shift control signal SFTE&lt;i&gt;, makes a switch between DBRA&lt;i&gt; and DBRA&lt;i+1&gt;, that is, determines which of signals DBRA&lt;i&gt; and DBRA&lt;i+1&gt; should be transmitted to node N 8 .  
         [0106]     When test control signal TMBUSCHK 1  is set to H level and test control signal TMBUSCHK 2  is set to L level, clocked inverter  64  is activated while clocked inverter  74  is inactivated.  
         [0107]     Transmission gate circuits  44 ,  40  are in a conducting state and transmission gate circuits  46 ,  42  are in a non-conducting state. D flip-flop  62 , in synchronization with a rising edge of clock signal CLK, outputs from output node B a signal provided to input node A Therefore, input signal D provided from the input/output node of input/output buffer  18   a  returns thereto via nodes N 1 , N 2 , N 4  and N 8  in accordance with output enable signal OE. Input/output timing is the same as in  FIG. 7 , and description thereof will not be repeated.  
         [0108]     On the other hand, when test control signal TMBUSCHK 2  is set to H level and test control signal TMBUSCHK 1  is set to L level, clocked inverter  74  is active while clocked inverter  64  is inactive. In addition, transmission gate circuits  44 ,  40  are in a non-conducting state and transmission gate circuits  46 ,  42  are in a conducting state. D flip-flop  72 , in synchronization with a rising edge of clock signal CLK, outputs from output node B a signal provided to input node A.  
         [0109]     Therefore, provided test signal is output from tristate buffer circuit  68  via nodes N 1 , N 3 , N 5  and N 8 .  
         [0110]     Thus, by conducting a test twice using two test modes, whether switch circuits on both &lt;i&gt; and &lt;i+1&gt; sides function normally or not can be checked.  
         [0111]     When data input and output are separate, similar effects will be obtained by simply adding a transmission gate circuit without using a flip-flop circuit, as shown in the first embodiment.  
         [0112]      FIG. 10  shows a variation when data input and output are separate.  
         [0113]     Referring to  FIG. 10 , in the configuration of shift switch circuit  22   b  shown in  FIG. 8 , a shift switch circuit  22   c  includes transmission gate circuits  84 ,  86  instead of data transmission circuits  60 ,  70 .  
         [0114]     Transmission gate circuit  84  has node A connected to node N 2  and node B connected to node N 4 , and receives signal TMBUSCHK 1  at node E. Transmission gate circuit  86  has node A connected to node N 3  and node B connected to node N 5 , and receives signal TMBUSCHK 2  at node E. Transmission gate circuits  84 ,  86  are of the same configuration as transmission gate circuit  34  shown in  FIG. 4 , and description thereof will not be repeated.  
         [0115]     (Fourth Embodiment)  
         [0116]      FIG. 11  is a circuit diagram showing a configuration of shift switch circuit  22   d  and input/output buffer  18   d  used in a fourth embodiment.  
         [0117]     Referring to  FIG. 11 , shift switch circuit  22   d  corresponds to number &lt;i&gt; data line, where i is an integer not smaller than 0 and not larger than n.  
         [0118]     Here, an example is shown, in which write bus and read bus toward memory array are configured as a common data bus and a shift switch is used both for read and write.  
         [0119]     Shift switch circuit  22   d  includes an inverter  102  receiving and inverting test control signal TMBUSCHK 1 ; an OR circuit  110  outputting signal SFTE 1  upon receiving test control signal TMBUSCHK 1  and shift control signal SFT&lt;i&gt;; and an NAND circuit  112  outputting signal SFTE 0  upon receiving shift control signal SFT&lt;i&gt; and an output of inverter  102 .  
         [0120]     Shift switch circuit  22   d  further includes: a transmission gate circuit  114  having node B connected to node N 11  and node A connected to node N 12 , and receiving signal SFTE 0  at node E; a transmission gate circuit  104  having node B connected to node N  12  and node A connected to node N  14 , and receiving an output of inverter  102  at node E; a transmission gate circuit  106  having node A connected to node N 17  and node B connected to node N 13 , and receiving an output of inverter  102  at node E; a transmission gate circuit  116  having node A connected to node N 13  and node B connected to node N 11 , and receiving signal SFTE 1  at node E; and a data transmission circuit  108  connected between node N 12  and node N 13 .  
         [0121]     Signal DBB&lt;i&gt; is input and output via node N 11 . Node N 14  receives signal DBA&lt;i&gt; from memory cell array. Signal DBA&lt;i+1&gt; is input and output from/to memory cell array via node N 17 .  
         [0122]     Data transmission circuit  108  includes: a transmission gate circuit  118  having node A connected to node N 12  and node B connected to node N 15 , and receiving signal TMBUSCHKW at node E; an inverter  122  having an input connected to node N 15  and an output connected to node N 16 ; an inverter  120  having an input connected to node N 16  and an output connected to node N 15 ; and a clocked inverter  124  having an input connected to node N 16  and an output connected to node N 13 , and activated in accordance with signal TMBUSCHKR.  
         [0123]     Input/output buffer  18   d  includes: an OR circuit  126  receiving control signal WE and signal TMBUSCHKW; a tristate buffer circuit  128  having an input connected to node N 10  and an output connected to node N 11 , and activated in accordance with an output of OR circuit  126 ; an OR circuit  130  receiving control signal OE and signal TMBUSCHKR; and a tristate buffer circuit  132  having an input connected to node N 11  and an output connected to node N 10 , and activated in accordance with an output of OR circuit  130 . Node N 10  is connected to a data bus commonly used for read and write, for communicating data between a memory core and an embedded logic.  
         [0124]      FIG. 12  is a diagram of operation waveforms illustrating an operation of the circuit shown in  FIG. 11 .  
         [0125]     Referring to  FIGS. 11 and 12 , in a normal state of use until time t3, signals TMBUSCHK 1 , TMBUSCHKR and TMBUSCHKW are all set to L level. Here, transmission gate circuits  104 ,  106  are in a conducting state, and transmission gate circuits  114 ,  116 , in accordance with shift control signal SFT&lt;i&gt;, make a switch between DBA&lt;i&gt; and DBA&lt;i+1&gt;, that is, determines to which side data should be transmitted. Here also, transmission gate circuit  118  and clocked inverter  124  are inactivated.  
         [0126]     As shown at t1-t2, write operation is performed when control signal WE is at H level and control signal OE is at L level. As also shown at t2-t3, read operation is performed when control signal WE is at L level and control signal OE is at H level.  
         [0127]     When signal TMBUSCHK 1  is set to H level at time t3, test mode is set and both shift control signals SFTE 0  and SFTE 1  attain to H level. In addition, transmission gate circuits  104 ,  106  are rendered non-conductive, and memory cell array side and nodes N 12 , N 13  are disconnected. When signal TMBUSCHKW is set to H level at time t4 while allowing signal TMBUSCHK 1  to be kept at H level, transmission gate circuit  118  is rendered conductive and write data is written into a latch circuit consisting of inverters  120 ,  122 . When signal TMBUSCHKW is set to L level, write data will be held at nodes N 15 , N 16 .  
         [0128]     When signal TMBUSCHKR is set to H level at time t5 while allowing signal TMBUSCHK 1  to be kept at H level, clocked inverter  124  is activated and inverted data of input data held at node N 16  is output to node N 11  via node N 13 . Data is then output as signal DQ&lt;i&gt; by input/output buffer  18   d.    
         [0129]     Through operations in a sequence as described above, whether a data bus including a shift switch circuit is defective or not can be examined.  
         [0130]     Thus, since a path to transmit data to a memory cell array through a data line shift circuit can be confirmed, successful replacement of a normal data line with a redundancy data line is more likely, which is effective in efficient production of a semiconductor memory device.  
         [0131]     Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.