Abstract:
Various embodiments of the present invention include methods and apparatus for receiving a radio frequency (RF) signal spectrum in a receiver; mixing the RF signal spectrum with a first local oscillator (LO) frequency to obtain a first downmixed signal; and converting the first downmixed signal to a first digital signal using an analog-to-digital converter (ADC) having an adjustable clock frequency selected to avoid interference with the first LO frequency. The adjustable clock frequency may be adjusted by a predetermined amount, by phase modulation, or in other manners.

Description:
TECHNICAL FIELD OF THE INVENTION  
       [0001]     The invention relates to integrated circuits, and more specifically to avoiding interference between different components within such circuits.  
       BACKGROUND  
       [0002]     Numerous integrated circuits (IC) are used for mixed signal purposes. That is, such circuits include both analog and digital components. Specifically, certain such mixed signal circuits include analog circuitry that operates at extremely high frequencies, for example, radio frequencies (RF), and digital circuitry that operates at baseband frequencies. Because of the presence of both analog and digital circuitry within such IC devices, there is a potential for interference between the analog and digital components.  
         [0003]     While various sources of such interference may exist, one particular source of interference may be interference caused by harmonics of baseband clock frequencies that interfere with RF frequencies within the IC device. Accordingly, a need exists to reduce or prevent such interference. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0004]      FIG. 1  is a block diagram of a receiver in accordance with one embodiment of the present invention.  
         [0005]      FIG. 2  is a graphical representation of a signal spectrum in accordance with one embodiment of the present invention.  
         [0006]      FIG. 3  is a graphical representation of a signal spectrum in accordance with another embodiment of the present invention.  
         [0007]      FIG. 4  is a block diagram of a portion of a system in accordance with one embodiment of the present invention. 
     
    
     SUMMARY OF THE INVENTION  
       [0008]     One aspect of the present invention includes a method of adjusting a clock frequency for a baseband component of a system to avoid interference with a RF signal, such as a signal channel or a local oscillator (LO) frequency used by a receiver of the system.  
         [0009]     Another aspect of the present invention includes a method of receiving a RF signal spectrum in a receiver; mixing the RF signal spectrum with a first LO frequency to obtain a first downmixed signal; and converting the first downmixed signal to a first digital signal using an analog-to-digital converter (ADC) having an adjustable clock frequency selected to avoid interference with the first LO frequency.  
         [0010]     In yet another aspect of the present invention, an apparatus is provided that includes a clock generator to generate a baseband clock frequency; and a controller coupled to the clock generator to adjust the baseband clock frequency to avoid interference with a RF frequency. Such an apparatus may be used in a system that includes a RF circuit to receive a satellite spectrum and to mix the satellite spectrum with a first LO frequency to obtain a first downconverted signal; and a first baseband circuit coupled to receive and to process the first downconverted signal, the first baseband circuit having at least one component to operate at the adjustable baseband clock frequency.  
       DETAILED DESCRIPTION  
       [0011]     Referring to  FIG. 1 , shown is a block diagram of a system in accordance with one embodiment of the present invention. As shown in  FIG. 1 , system  10  may be, for example, a receiver for use in a RF system such as a satellite receiver for use in a set-top box or other television tuner. While discussed primarily herein as used in such a satellite system, it is to be understood that other embodiments of the present invention may be used in connection with other RF systems, such as cellular telephones, radios, other communication systems and the like.  
         [0012]     As shown in  FIG. 1 , system  10  receives an incoming signal  20  at a low noise amplifier (LNA)  30 . The resulting amplified signal  35  may then be input into a mixer  40 , where the RF signal is mixed with a local oscillator (LO) frequency (f LO ) provided by LO circuitry  50 .  
         [0013]     The resulting downconverted signal  55  may be provided to baseband circuitry for further processing. For example, downconverted signal  55  may be sent to an analog-to-digital converter (ADC)  60  for conversion from an analog signal to a corresponding digital signal  65 . Digital signal  65  may then be provided to a digital signal processor (DSP)  70  for desired processing. In one embodiment, a wide-band ADC  60  may receive a coarsely tuned signal  55  and provide a digital output to DSP  70 , which may be a tunable digital filter that in turn outputs digital baseband signals  75 .  
         [0014]     While such a DSP may take various forms, in certain embodiments, such a digital signal processor may include various circuitry for tuning, filtering, and processing digital signals. For example, such circuitry may include clock and data recovery circuitry, digital tuning circuitry, digital filtering circuitry, and digital decoding circuitry, for example.  
         [0015]     The processed signals  75 , which may be digital baseband signals, may be provided to additional circuitry (either on the same integrated circuit (IC) or to different circuitry) for further processing. For example, as shown in  FIG. 1 , the digital baseband signals  75  and the clock frequency may be provided to an input/output (I/O) circuit  96 . Such an I/O circuit may be used to transfer both the digital data (output as data  98 ) and the clock frequency to other circuitry within a system. In various embodiments, different components may be included in such additional circuitry, including additional processing components, audio and video components and the like. In such manner, in certain embodiments, the clock frequency may be provided for use in other system components, in addition to the digital data.  
         [0016]     Alternately, in other embodiments DSP  70  may sufficiently process incoming signals for their intended purpose. In the embodiment shown in  FIG. 1 , all components may be housed within a single integrated circuit, although the scope of the present invention is not so limited. Further, while not shown in  FIG. 1 , in other embodiments multiple tuners may be present within a single IC. Such multiple tuners may each include the same RF and baseband circuitry shown in  FIG. 1 .  
         [0017]     As further shown in  FIG. 1 , a clock frequency (f CLK ) may be provided by a clock generator  80  and used as clock signals for baseband components, including ADC  60  and DSP  70  (or other such baseband circuits). While shown in  FIG. 1  as providing the same clock signal to both ADC  60  and DSP  70 , in other embodiments, different clock signals may be provided to these or other digital circuits.  
         [0018]     There is a potential for interference between a harmonic of such a baseband or digital clock frequency and RF frequencies used in a system. For example, a digital clock frequency of 100 megahertz (MHz) may generate a harmonic (e.g., a tenth harmonic) that interferes with a RF frequency (e.g., a one gigahertz (GHz) frequency). Such an RF frequency may be within a band of a received signal (e.g., a received signal channel), a LO frequency, or any other RF frequency used in or received by the system. Thus it may be desirable to adjust the digital clock frequency to avoid interference at RF frequencies. Accordingly, a clock controller  90  may be used to control clock generator  80  so as to avoid this interference. While frequency planning is understood in the field of RF design, what is different in the embodiment is the fact that in certain broadband RF applications no single clock selection will suffice to eliminate the interference problem for all channels. Thus the clock frequency may be dynamically adjusted to adjust harmonics away from the “current” desired channel or “current” LO frequencies.  
         [0019]     As shown in  FIG. 1 , clock controller  90  may receive the LO frequency output from LO circuitry  50  and the clock frequency output from clock generator  80 . Of course, in other embodiments, other RF frequencies may be provided to clock controller  90  for comparison to a digital clock frequency. Based on analysis of these frequencies it may be determined whether there is a potential for interference therebetween. If such interference is likely, clock controller  90  may provide control signals  95  to clock generator  80  to adjust the clock frequency accordingly to avoid interference.  
         [0020]     In one embodiment, clock controller  90  may include logic functionality to analyze an LO frequency used to downmix an incoming signal, and a baseband clock frequency to determine whether a potential exists for interference therebetween. For example, in one embodiment clock controller  90  may include a combination of hardware, software and/or firmware to analyze the incoming frequencies and determine whether any adjustment to the baseband clock frequency is desired.  
         [0021]     In various embodiments, it may be determined whether a harmonic of the clock frequency (or frequencies) is near a desired signal channel. In such embodiments, “near” means that the two frequencies are close enough in frequency that undesired interference may occur if the clock frequency is not adjusted. While what is considered to be near a given signal may vary in different embodiments, in certain embodiments, if the harmonics are within between approximately 40 MHz and 80 MHz of a signal channel (or its LO frequency), the clock frequency may be adjusted.  
         [0022]     In other embodiments, the clock frequency may be adjusted so that its harmonics are separated from a LO frequency by at least an amount equal to a crosstalk region. While the width of such a crosstalk region may vary, in certain embodiments such a crosstalk region may be between approximately 40-80 MHz wide, although the scope of the present invention is not so limited.  
         [0023]     In certain embodiments, adjusting the clock frequency may be effected using software (or a combination of software, firmware and hardware) that may be executed within a system, such as a receiver, cellular telephone, or the like. For example, in the embodiment of  FIG. 1 , such software may be implemented within clock controller  90 . Such embodiments may include an article in the form of a machine-accessible storage medium onto which there are stored instructions and data that form a software program to perform such methods of avoiding interference.  
         [0024]     Thus control signals  95  may be used to cause clock generator  80  to adjust its output, namely the clock frequency, f CLK . While clock generator  80  may take different forms in various embodiments, in one embodiment, clock generator  80  may include a crystal oscillator, such as a quartz crystal that generates a reference frequency. Such a reference frequency may then be processed, for example, by dividing the reference frequency and then passing the divided output to clock frequency generation circuitry, such as a phase lock loop (PLL), a voltage controlled oscillator (VCO), or other such circuitry. While shown in the embodiment of  FIG. 1  as generating a single clock frequency, it is to be understood that clock generator  80  may output multiple different baseband clock frequencies. Using feedback from control signals  95 , clock generator  80  may accordingly adjust its output clock frequency (or frequencies) to avoid interference with RF frequencies, such as one or more signal channels of a satellite receiver.  
         [0025]     In such manner, the clock frequency may be adjusted to move interfering tones away from, for example, a desired RF signal channel. Because digital clock frequencies exist at a much lower frequency than desired RF channel frequencies, by adjusting the digital clock frequency by a small amount, significant changes in harmonics of the clock frequency may be realized, thus avoiding interference at the desired RF signal frequency.  
         [0026]     Referring now to  FIG. 2 , shown is a graphical representation (not drawn to scale) of a signal spectrum in accordance with one embodiment of the present invention. As shown in  FIG. 2 , a digital clock frequency is present at f CLK . For purposes of illustration, it may be assumed that f CLK  is at 100 MHz. Further shown in  FIG. 2  is a RF frequency (f LO ) corresponding to a LO frequency to be used for tuning a desired signal channel of an RF spectrum, for example, a television channel in a satellite television receiver. For sake of illustration, assume that the LO frequency is at two GHz. Thus, the twentieth harmonic of the clock frequency (i.e., ωf CLK ) falls on the LO frequency (not shown precisely in  FIG. 2  for ease of illustration) and therefore may cause interference.  
         [0027]     Still referring to  FIG. 2 , if instead the clock frequency is adjusted by a small amount (i.e., a Δf), the harmonics of the adjusted clock frequency may be far enough away from the desired LO frequency such that no interference exists. For example, assume that Δf equals 2 MHz. Thus, at two times the clock frequency, a Δf of four MHz exists, and at the twentieth harmonic, a total change in frequency of 40 MHz exists (i.e., ωΔf). In such manner, interference may be avoided between the LO frequency and the harmonics of the clock frequency. The importance of this is that only small adjustments in the clock frequency may be used to avoid interference. In such manner, any costs associated with developing flexible digital logic (due the higher speed needed) and slightly larger tuning range needed for the PLL are reduced. Similarly, any cost to analog blocks that require the f CLK , such as ADCs and digital-to-analog converters (DACs) is minimal. The designer only has to add a few percentage points of margin to such designs.  
         [0028]     While the amount that a clock frequency may be shifted may vary in different embodiments, in certain embodiments a frequency shift of a small percentage may be sufficient to avoid interference at RF signal levels. Thus in various embodiments, a frequency shift between approximately 0.5% and 5% may be effected, and in particular embodiments, approximately a 2% frequency shift may be used.  
         [0029]     In other embodiments, instead of a fixed percentage change to a clock frequency, a continuous phase modulation (CPM) of the clock frequency may be implemented. For example, a slow but large modulation of a clock frequency may be effected to avoid interference at RF signal levels.  
         [0030]     Referring now to  FIG. 3 , shown is a signal spectrum in accordance with one embodiment of the present invention. As shown in  FIG. 3 , digital interference may create a tone in a desired signal channel at a frequency somewhere between 1 and 2 GHz. For example, shown in  FIG. 3  is an undesired noise having a value of −A dbm in a given desired signal channel having a bandwidth of 1.2 MHz. By performing CPM of the digital clock frequency that causes this noise, the noise energy may instead be spread out over a wider frequency range, thus lowering the signal level of the noise to an acceptable level.  
         [0031]     In certain embodiments, modulation of the clock frequency may be performed slowly. For example, for a clock frequency of 100 MHz, the modulation rate may be, for example, 100 kilohertz (KHz). However, the actual modulation of the clock frequency may be larger than a fixed adjustment to the clock frequency, as described above. For example, in certain embodiments a larger percentage of modulation may occur. As an example, for a digital clock frequency of 100 MHz, the clock frequency may be modulated by 5 or more MHz. In such manner, noise that may occur at a desired RF frequency may be spread out over a wider frequency range, such that the noise becomes insignificant.  
         [0032]     Referring now to  FIG. 4 , shown is a block diagram of a system in accordance with another embodiment of the present invention. As shown in  FIG. 4 , system  200  may be a portion of a receiver, for example, a satellite receiver or the like. Only a portion of such a receiver is shown for purposes of the discussion of  FIG. 4 . However, it is to be understood that additional components may be present within such a receiver.  
         [0033]     As shown in  FIG. 4 , an incoming downconverted analog signal  205  may be provided to an ADC  210  for digital conversion. The resulting digital signal  215  may be provided to a clock and data recovery unit (CDR)  220 . CDR  220  may be used to recover a clock from the incoming signal as well as to sample the data present in the signal with the recovered clock. Thus the output of CDR  220  may be an encoded digital data stream  225  that is provided to a decoder  230 . Decoder  230  may decode the encoded signals and provide a decoded digital output  235  to an input/output (I/O) circuit  250 . For example, in one embodiment, decoder  230  may be a Viterbi decoder, although the scope of the present invention is not so limited.  
         [0034]     As shown in  FIG. 4 , each of the digital circuits, including ADC  210 , CDR  220 , and decoder  230  are provided a digital clock frequency (f CLK ), generated from clock generator  240 . While shown for ease of illustration in  FIG. 4  as receiving the same clock frequency, it is to be understood that in other embodiments some or each digital circuit may receive its own clock frequency. Further shown in  FIG. 4  is a clock controller  245  which may be used to provide control signals to clock generator  240  to modify, modulate, and/or adjust the clock frequency to avoid RF interference as described herein.  
         [0035]     As further shown in  FIG. 4 , the decoded digital data  235  and the clock frequency may be provided to an I/O circuit  250 . Such an I/O circuit may be used to transfer both the digital data and the clock frequency to other circuitry within a system. In such manner, in certain embodiments, the variable rate clock frequency may be provided for use in other system components, in addition to the decoded data.  
         [0036]     However, it may instead be desired to provide a fixed rate of digital data out of system  200 . To effect such a fixed data rate while using variable clock frequencies within system  200 , a variable rate interpolator may be present within I/O circuit  250 , for example, to digitally resample the data to the desired output frequency (e.g., an original clock frequency of one or more baseband components).  
         [0037]     As discussed, adjustment to a baseband clock frequency may occur for various RF systems. For example, set-top box satellite receivers, including low intermediate-frequency (IF) architectures, and direct down conversion (DDC) architectures may utilize such clock frequency adjustments.  
         [0038]     Similarly, clock frequency adjustment may be used in a receiver that analog coarsely tunes signal channels. In such an embodiment, by fine tuning a coarsely tuned channel spectrum, the receiver does not mix the desired channel down to a fixed target IF frequency and then mix the desired channel to DC. Rather, such an implementation uses analog coarse tune circuitry to mix the desired channel down to a variable location within a frequency range around DC, and then digital conversion and digital filtering is performed directly on the coarsely tuned channel spectrum.  
         [0039]     Further, such adjustments may be made in multi-tuner environments. In such environments, multiple tuners may be present to tune multiple signal channels. For example, two or more such tuners may be present to tune multiple television channels received from a satellite source. Accordingly, multiple LO generation circuits may be present. Furthermore, multiple signal channels may be received and tuned. Thus, one or more digital baseband clock frequencies may be adjusted to avoid interference with the signal channels and/or LO frequencies used in tuning such signal channels. In such embodiments, clock controller circuitry may receive multiple RF frequencies, for example, multiple LO frequencies and use such frequencies to determine whether baseband clock frequency adjustment is needed, and if so, what adjusted clock frequency should be generated.  
         [0040]     While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.