Abstract:
A contactless control device for a press having a device for checking whether an abnormality detector normally operates or not. The device of this invention is constructed to operate when power is fed to the press or when the press is stopped at its top dead center. A self-check operation generates and applies a dummy pulse to the abnormality detector. The abnormality detector generates an error signal corresponding to the dummy signal if normal. Since no error signal is generated when the abnormality detector is abnormal, the press is not operated. Operation of the press is dependent on the error signal. Whether the abnormality detector is normal or not is indicated during a self-check operation.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a contactless press control device having a self check circuit. 
     2. Description of the Prior Art 
     Contactless control devices wherein the relay sequence circuit are replaced by integrated circuits have begun to be used lately as a press control device in order to improve the reliability of the press. 
     The prior art contactless control device comprises a control circuit to control the press operation and a fault detection circuit to detect and prevent misoperation of the press. 
     The present invention is directed to further improve the safety of the press operation by adding the function to judge whether or not the fault detection circuit is working. The present invention provides a contactless press control device which is able to discriminate whether or not the fault detecting circuit is functioning normally by applying a dummy signal at the time of power input and when the press has stopped at its top dead center. 
     According to the present invention, fault detection is performed automatically upon the input of press power and thus, input, fault of the contactless control device is detected before the press start-up. In addition, since fault detection is performed each time the press stops at its top dead center, fault of the control device can be detected before the press operation, making it possible to prevent misoperation of the press. Furthermore since the fault detection time is very short, there is no press operation delay after the press is stopped at its top dead center. 
     The present invention will now be described in detail with reference to the accompanying drawings in which the presently preferred embodiment of the invention is illustrated by way of example. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a preferred embodiment of the contactless press control device according to the present invention; 
     FIG. 2 is a circuit diagram showing the detail on a preferred embodiment of the self-check circuit of the contactless press control device according to the present invention; 
     FIG. 3 is a time chart for operation of the circuit in FIG. 2. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 is a block diagram of a preferred embodiment of the contactless press control device according to the present invention. 
     An input circuit 1 forms an input check signal Db and an input signal D 1  from a signal Da to be applied from the press (not shown), the input circuit applies the signal Db to an input check circuit 2, and also applies the signal D 1  to operation circuits 3 and 4. In addition, the input circuit 1 applies a check start signal Cs to a self-check circuit 10 when power is fed to the press or when the press has stopped at its top dead center. The input circuit 1 also applies a signal. The input check circuit 1 also applies signal I t  to circuits 3 and 4 (indicating to these circuits that check is underway) and also applies this signal to the self-check circuit 10. 
     The input check circuit 2 applies an error signal Er 1  to an emergency stop circuit 8 upon the detection of abnormality in the signal Da from the signal Db previously applied to the check circuit. 
     The operation circuits 3 and 4 are configured identically, and apply signals which signify a state of a specified operation point to a comparator 7 as comparison signals C 1  and C 2  respectively. Likewise, output circuits 5 and 6 are configured identically, and apply signals which signify a state of a specified operation point to the comparator 7 as comparison signals C 3  and C 4 . The operation circuits 3 and 4 form ON-OFF signals D 2  and D 3  for solenoids 12 and 13 which in turn control a clutch or brake from the applied signal D 1 , and apply said signals to the solenoids 12 and 13 through the output circuits 5 and 6. 
     The comparator 7 compares the signals C 1  and C 2   point by point, and the difference, if any, is detected as fault. Upon the detection of fault, the comparator 7 outputs an error signal Er 2  to the emergency stop circuit 8. 
     When the signals Er 1  and Er 2  are fed, or when a stop signal Se is fed externally via the input circuit 1, the emergency stop circuit applies an emergency stop signal St to the operation circuits 3 and 4, output circuits 5 and 6, and the self-check circuit 10, and further applies an error occurrence signal De to an indicator 9. Thereupon, the operation circuits 3 and 4, and the output circuits 5 and 6 become the emergency stop state, the press operation is stopped, and the indicator 9 gives fault indication. 
     In addition, Feedback signals F 3  and F 2  corresponding to the operations of the solenoids 12 and 13 are fed to the operation circuits 3 and 4. 
     As described above, the self-check circuit 10 of the contactless press control device checks the operations of the input check circuit 2 and the comparator 7. That is, the normalness of the circuit for detecting the abnormality of the input signal Da, and the circuit for detecting the abnormality of the operation circuits 3, 4 and the output circuits 5, 6 is determined. 
     FIG. 2 illustrates in detail a preferred embodiment of the self-check circuit of the contactless press control device according to the invention. In this figure, the part 8a is the part where emergency stop signals St 1  -St 3  are generated in the emergency stop circuit 8 (Refer to FIG. 1). Signals Er 1 , Er 2 , and Se are fed to a NAND circuit Nd 1 , Emergency stop signals St 2  and St 3  are fed to the operation circuits 3 and 4, and output circuits 5 and 6 respectively. 
     In this embodiment the operation is judged normal through the following actions. When power is fed to the press at the press start-up; and when the press stops at its top dead center, the fault detection condition is produced artificially by applying a dummy signal to the input check circuit 2 and the comparator 7, an error signal is output to the emergency stop circuit 8, an emergency stop signal is output, and the error indication is made by the indicator. The operation is judged abnormal when the error signal is not output, and error indication is not given accordingly. 
     When power is fed to the press, the signal Cs is fed from the input circuit 1 to the NAND circuit Nd 3  becomes &#34;0&#34; (FIG. 3(a)). As a result, the output signal Cr or the NAND circuit Nd 3  becomes &#34;1&#34; (FIG. 3(e)). This signal is fed to a reset input RE of a ring counter Rc, resetting the ring counter Rc. Then, as the signal Cs becomes &#34;1&#34;, (FIG. 3(a)) the signal It to be fed to the enable input EN of the ring counter Rc becomes &#34;1&#34; (FIG. 3(d)), and the ring counter Rc becomes operable. When the signal Cs becomes &#34;0&#34;, the signal Se is fed to the emergency stop circuit 8 from the input circuit 1, the emergency stop signal St 1  is inverted via an inverter In 6 , and the signal is fed to a clock input CK of the ring counter Rc as a signal St 1  &#39;. In FIG. 2, the gates Nd 1  and Nd 3  are depicted as OR-gates with inverted inputs, these being functionally identical to NAND gates. 
     The signal St 1  is delayed by a specified time t via a delay circuit Dy, inverted through an inverter In 4 , fed to the NAND circuit Nd 7 , and further inverted through an inverter In 5 . As a result, the signal St 1  is delayed by time t, and a signal Sd is formed. Signal Sd is fed to AND circuits Ad 1  -Ad 7  forming dummy signals Dm 1  -Dm 7 , and also to a NAND circuit Nd 2 . 
     Now, when the signal St 1  rises to &#34;1&#34;, the output of the terminal Q 0  of the ring counter Rc becomes &#34;1&#34; (FIG. 3(g)). That is, upon the first rise of the signal St 1  after the press power input, the ring counter Rc is initialized. 
     Then, upon the fall of the signal St 1 , the output of the terminal Q 0  falls, and the output of a terminal Q 1  rises to &#34;1&#34; (FIG. 3(h)). The signal Sd rises time t after the fall of the signal St 1 . As a result, the AND circuit Ad 1  becomes operatable, and a dummy signal Dm 1  becomes &#34;1&#34; (FIG. 3(h)). 
     When the input check circuit 2 and the comparator 7 are normal, the error signal Er 1  or Er 2  is generated, as a result of the dummy signal Dm 2  become &#34;1&#34; and fed to the emergency stop circuit 8, and the signal St 1  becomes &#34;1&#34;. Then, the dummy signal Dm 1  becomes &#34;0&#34; upon the fall of the signal Sd time t after the rise of the signal St 1 . On the other hand, the output of the terminal Q 1  falls to &#34;0&#34; upon the fall of the signal St 1 , and the output of the terminal Q 2  rises to &#34;1&#34;. 
     Thus, the ring counter Rc is driven upon the fall of the signal St 1 , and the output of terminals Q 1  -Q 7  become &#34;1&#34; sequentially. At the same time, as the signal Sd becomes &#34;1&#34;, dummy signals Dm 1  -Dm 7  are sequentially formed and fed to the input check circuit 2 and the comparator 7. 
     The output of the NAND circuit Nd 2  to which the signal Sd and the signal It are fed is inverted at an inverter In 7 , and a signal Ch is formed. This signal Ch indicates that the self-check circuit 10 is in operation. This signal Ch is also fed to the indicator 9, and indicates that the self-check is underway together with the signal De to be fed to the indicator 9. 
     When the ring counter is driven sequentially, dummy signals are all output, self-check completes, the output of a terminal Q 8  becomes &#34;1&#34; thereafter, and output signal of an inverter In 4  rises to &#34;1&#34;, a NAND circuit Nd 7  becomes operatable, an AND circuit Ad 8   operates, and a signal Cf is output to the input circuit 1 and the operation circuits 3 and 4. As a result, the signal It is cut off, and the self-check is terminated. 
     When the signal Cf is fed to the operation circuits 3 and 4, a signal D 1  is formed, and said circuits become operable. If the start condition is fulfilled, solenoids 12 and 13 operate, the press clutch operates, and the press is started. 
     Dummy signals Dm 1  -Dm 7  cause the input check circuit 2 or the comparator 7 to form error signals Er 1 , Er 2 . For example, the signal Dm 1  corresponds to the abnormality of the input signal Da, and signals Dm 2  -Dm 7  corresponds to the abnormality of operation circuits 3 and 4. Accordingly, in case abnormality has occurred in the input check circuit 2, the error signal Er 1  resulting from the signal Dm 1  is not formed and in case abnormality has occurred in the comparator 7, the error signal Er 2  resulting from the signals Dm 2  -Dm 7  is not formed. Thus, since no error signal is formed when fault has occurred at the input check circuit 2 or the comparator 7, no emergency stop signal St 1  is produced. In addition, since a signal De is not output from the emergency stop circuit 8 to the indicator 9, the indicator 9 does not give fault detection indication. On the other hand, since the signal St 1  is &#34;1&#34;, signal St 1  &#39; is &#34;0&#34;, (the signal St 1  which has passed through the inverter In 6  is labeled ST 1  &#39;) and the signal Sd is &#34;1&#34;. Accordingly, a signal Ch becomes &#34;1&#34;, and the indicator 9 indicates that the self-check circuit 10 is performing fault detection. 
     When the input check circuit 2 and the comparator 7 are normal, the signal Ch becomes &#34;1&#34; and &#34;0&#34; alternately, and the indication by the indicator 9 flashes accordingly. On the other hand, when fault has occurred at the input check circuit 2 or the comparator 7, the signal Ch stays &#34;1&#34;, and the indication at the indicator 9 is steady. 
     In this way, the occurrence of fault at the input check circuit 2 and the comparator 7 is clearly noticed. 
     As described above, fault detection by the self-check circuit 10 concerning the input check circuit 2 and the comparator 7 is performed at the time of press start-up, while the similar fault detection is performed with a signal Cs formed by the input circuit 1 when the press has stopped at its top dead center. When fault has occurred at the self-check circuit, no signal Cf is formed, therefore the operation circuit does not start the press.