Abstract:
LED drivers specially directed to LED matrix driver&#39;s ghost image prevention is disclosed. The LED driver receives an external input and decodes the input to produce a time multiplex timing on turning on an LED array. The LED driver inserts a dead time to the outputs and during this time the ghost image prevention circuit discharges the output stray capacitances to a predetermined level.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to LED drivers and, more particularly, to LED matrix driver ghost image prevention apparatus and method. 
     Light Emitting Diodes or LEDs are often used in visual applications that require time-multiplexing of numerous LEDs in the display. Time-multiplexing is a scheme that involves connecting the cathodes of multiple LEDs to each OUT pin of the LED driver. A time-multiplexed circuit is advantageous because it uses fewer LED drivers for a given amount of LEDs, which results in lower cost and smaller size. One major drawback to time-multiplexing is a side-effect called ghosting. The ghosting phenomenon is caused by stray board capacitance which can force time-multiplexed LEDs to flash when they should be off. 
     For the purpose of understanding how ghost-image is produced, an exemplary conventional time multiplex LED driver is presented as have been describe in MAXIM application note 411, titled “Eliminating Ghost-currents in Color-LED Display System using the MAX6972-MAX6975 LED Drivers”. Referring to  FIG. 1 , the multiplexing transistors (Q 1  and Q 2 ) are alternately turned on by the LED Driver IC while the constant current-sinking drive pins (OUT 1 -OUT 3 ) alternate control settings between the two phases. During Phase  1  ( FIG. 2 ), MUX 1  pin is low, Q 1  is turned on, and node A is pulled to the LED supply, VLED, thereby connecting LED 2 , LED 4 , and LED 6  anodes to the LED supply. Likewise, during Phase  2 , MUX 2  is low and Q 2  is turned on, connecting LED 1 , LED 3 , and LED 5  anodes to the LED supply. The MUX 1  and MUX 2  outputs turn on the PNP transistors by sinking base current through the resistors via their open-drain drivers. When MUX 1  and MUX 2  are off, the open-drain outputs are essentially open-circuit, allowing the base-emitter resistors to turn off the PNP transistors. Between each MUX 1  and MUX 2  phase, both Q 1  and Q 2  are off, which is shown as t EMUX  in  FIG. 2 . Faint ghost images from parasitic currents occur during the transition from MUX 1  to MUX 2  and vice versa. The effects are most pronounced when the LEDs on the multiplexed circuits are different colors (light wavelengths) and, hence, have significantly different voltage drops for a given current flow. Further referring to  FIG. 1 , assuming all odd numbered LED are green and even numbered LED are red, and assuming that 
     The voltage drops of LEDs are: 
     
         
         
           
             V RED =2V 
             V GREEN =3.1V
 
The supply voltage:
 
             +VLED=5V
 
At phase  1 , with Q 1  turned on, the anode of the red LEDs will be connected to the supply voltage, this will in turned charge the parasitic capacitor Cp 1  at node A to approximately 5V. With Outputs OUT 1 -OUT 3  active and assuming the voltage drop of the PNP transistor to be negligible, all LED cathodes will be pulled to a voltage approximately equal to:
 
5V− V   RED =3V  (eq. 1)
 
When phase  1  ends, the 3 output drivers will be off and MUX 1  will be inactive, disconnecting the anode of the LEDs from the supply voltage. Since there are no discharge paths for the parasitic capacitor the voltage at node A will remain close to the supply voltage. When phase  2  begins, MUX  2  will be low, Q 2  turn on, the anode of green LED is connected to 5V, and Outputs OUT 1 -OUT 3  are activated. The voltage at the cathodes of the all LEDs will then be approximately equal to:
 
5V− V   GREEN =1.9V  (eq. 2)
 
With all cathode voltage approximately equal to 1.8V, the anode of the red LED will need to discharge to
 
1.8V+ V   RED =3.8V  (eq. 3)
 
From 5V voltage at node A at the beginning of phase  2  node A will discharge to 3.8V through the red LED. This discharging produces a faint illumination or ghost image on one or more red LEDs.
 
           
         
       
    
     The ghost image can be eliminated by providing a discharge path for the parasitic capacitor Cp 1 -Cp 2  and providing time for the discharge to occur. This is accomplished by adding R 1  and R 2 , as shown in  FIG. 3 . However this method does not give solution to the stray capacitances Cp 3 -Cp 5  present on the OUT pins and the method presented also lowers the efficiency due to the current which are consumed by the additional resistor. Furthermore this technique is limited to only LED time multiplex circuit arrangement as discussed above. For LED time multiplexed circuit where every LED output drives both anodes and cathodes of LEDs, as shown in  FIG. 4 , this method may not suitable. In this LED driver architecture the driver outputs Z 1 -Z 3  function as a switch to connect the LEDs to the power supply or constant current supply. The main objective of the current invention is to provide the most effective prevention to LED ghost image without sacrificing efficiency. 
     SUMMARY OF THE INVENTION 
     The purpose of this invention is to provide a method and apparatus that prevents the occurrence of ghost images in LEDs, without the efficiency loss. 
     According to the present invention, a method of removing ghost-image currents occurring in an arrangement of a plurality of LEDs, comprises: 
     generating a dead time between the turning on of subsequent multiplexing transistors; and 
     discharging of parasitic capacitances to a pre-determined voltage level. 
     According to the present invention, the pre-determined voltage level is equal to half of the power supply voltage. 
     According to the present invention, the discharging step is performed at all anode and cathode nodes of the LEDs. 
     According to the present invention, an apparatus for removing the ghost-image currents occurring in an arrangement of a plurality of LEDs, comprises: 
     a multiplexing controller to generate signals to control the operation of the arrangement of a plurality of LEDs; 
     a plurality of multiplexing transistors to control the voltages applied to the anode and cathode terminals of the LEDs; 
     a plurality of discharging devices, each having a first terminal electrically coupled to the multiplexing controller, having a second terminal electrically coupled to a path that leads to the power supply, having a third terminal electrically coupled to a path that leads to ground, and having a fourth terminal electrically coupled to each one of the anode and cathode terminals of the LEDs. 
     According to the present invention, the discharging device further comprises: 
     a PMOS transistor, having its gate terminal electrically coupled to the multiplexing controller, having its drain terminal electrically coupled to a first terminal of a first resistor, and having its source terminal electrically coupled to the path that leads to the power supply, 
     a first resistor, having its first terminal electrically coupled to the drain terminal of the first NMOS and having its second terminal coupled to the anode and cathode terminals of the LEDs; 
     a second resistor, having its first terminal electrically coupled to the anode and cathode terminals of the LEDs and having its second terminal electrically coupled to a drain terminal of an NMOS transistor; 
     an NMOS transistor, having its source terminal electrically coupled to a path that leads to ground, having its drain terminal electrically coupled to the second terminal of the second resistor and having its gate terminal electrically coupled to the multiplexing controller. 
     According to the present invention, the discharging device further comprises at least one current driver operative disposed of between the output of the multiplexing controller and the gate terminals of the first and second NMOS transistors. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is showing an application circuit diagram of a Time-multiplex LED Driver system, according to the prior art. 
         FIG. 2  is a timing diagram illustrating the timing of the output that controls the PNP bipolar transistor, according to the prior art. 
         FIG. 3  is showing an application circuit diagram of a Time-multiplex LED Driver system implementing Ghost image prevention, according to the prior art. 
         FIG. 4  is showing a simplified circuit diagram of a Time-multiplex LED Driver system, according to the present invention. 
         FIG. 5  is showing a simplified circuit diagram of a Time-multiplex LED Driver system implementing Ghost image prevention, according to the present invention. 
         FIG. 6  is showing a basic block diagram of Ghost image prevention, according to the present invention. 
         FIG. 7  is showing one possible circuit of implementing the Ghost image prevention, according to the present invention. 
         FIG. 8  is a timing diagram showing the timing the operation of a Time-multiplex LED Driver system implementing Ghost image prevention, according to the present invention. 
         FIG. 9  is a timing diagram showing the expanded view of the dead-time. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     To solve the problem stated above, the present invention has been made and it is an object of the invention to provide solution in preventing the occurrence of ghost images in LED matrix drivers. 
     It is to be understood that the figures and description of the present invention may have been simplified to illustrate relevant elements for a clear understanding of the present invention. Those of ordinary skill in the art will recognize that other element may be required in order to implement the present invention. However, because such elements are well known in the art, discussions of such element were not provided. It is also to be understood that the drawing included herewith only provided diagrammatic representations of the preferred structure of the present invention. 
     Referring to  FIG. 5 , the first embodiment of an LED matrix driver  100 , capable of removing ghost-image currents, according to the present invention is presented. For the purpose of simplification, a 2 by 2 matrix system  105  is presented. The LED system can be an n by m LED matrix system where n is the number of LED columns and m is the number of rows. Referring to  FIG. 5 , external signals VIN  106  is inputted to the controller  101 , which will then be decoded. The decoded signal will provide the output to terminals Y 1 CNT and Y 2 CNT. The terminal Y 1 CNT is electrically coupled to the gate of the PMOS transistor  102 , while the source terminal of PMOS transistor  102  is electrically coupled directly to the supply voltage VCC and the drain terminal electrically coupled to output Z 1 . Controller  101  output terminal Y 2 CNT is electrically coupled to the gate of PMOS transistor  103  and its drain and source terminal electrically coupled to the output Z 2  and supply voltage VCC respectively. The output terminals Y 1 CNT and Y 2 CNT will alternately turn on the two PMOS transistor according to the decoded external input signal. During each transition between output terminals Y 1 CNT and Y 2 CNT, a dead time t DEAD  is inserted in order to prevent shoot through current. This is as illustrated in  FIG. 9 . During the dead time t DEAD , the controller  101  will send a high level pulse via output terminal GICNT. Output terminal GICNT is electrically coupled to the input of the ghost image prevention block, GIP  104 . This GICNT signal will serve as an enable signal to the ghost image prevention block, GIP  104 . The ghost image prevention block, GIP  104 &#39;s outputs connect to the LED system via outputs Z 1 , Z 2  and Z 3 , and this connection provide the path in order to discharge the stray capacitances CP 1 -CP 3  at the outputs Z 1 , Z 2  and Z 3 . 
     The controller  101  also provides the output terminals X 1 CNT, X 2 CNT and X 3 CNT. These outputs control SW 1 , SW 2  and SW 3  switches, respectively. The switch electrically connects the current sources I 1 , I 2  and I 3  to output Z 1 , Z 2  and Z 3  respectively. These signals produced by output terminals X 1 CNT, X 2 CNT and X 3 CNT may be PWM signals that will increase or decrease the average magnitude of the current sources I 1  to I 3  which controls the LED&#39;s brightness level. 
     Further referring to  FIG. 5  the outputs Z 1 , Z 2  and Z 3  connect to each other through the different LEDs, that is, Z 1  connects to anode of LED 1  and LED 2  then the cathode of LED 1  and LED 2  connects to Z 2  and Z 3  respectively. LED 3  and LED 4  anodes connect to Z 2  and its cathode to Z 1  and Z 3  respectively. The capacitors CP 1 , CP 2  and CP 3  represent the parasitic capacitance at every one of the output pins Z 1 -Z 3 . 
     An exemplary implementation of the ghost image prevention block, GIP  104  is as shown in  FIG. 6 .  FIG. 6  shows the basic block diagram of the ghost image prevention block GIP  104 . The ghost image prevention block GIP  104  consists of identical voltage generators  201 ,  202  and  203  that receive an enable signal from the controller via output terminal GICNT. When an enable signal is transmitted to the voltage generators  201 ,  202  and  203 , that enable signal will provide a constant voltage at a predetermined level. This action will then force the voltage at outputs Z 1 , Z 2  and Z 3  to the predetermined level which will cause the discharging/charging of the parasitic capacitances. 
       FIG. 7  shows one of a possible way of implementation of the voltage generator according to the present invention. The voltage generator can be of any apparatus that will force the LED output at a predetermined voltage level. Referring to the figure, output terminal GICNT connects to the input of an inverter INV 1  and its output connected to the input of inverter INV 2  and the gate of PMOS 1 . PMOS 1  serves as a transistor switch with its source connected to the power supply and its drain connecting to R 1  resistor. While, inverter INV 2  output terminal connects to the gate of NMOS 1 . NMOS 1  functions as a switch wherein its drain is connected to resistor R 2  and its source terminal connects to ground. The other terminals of R 1  and R 2  finally connects to the outputs Z 1 , Z 2  and Z 3 . Assuming R 1  and R 2  are of the same resistance value, ½ of the supply voltage will be generated at the outputs when the signal at the output terminal GICNT is at high level or VCC level. 
       FIG. 8  show a timing diagram according to the present invention. At time t 1  the gate of PMOS 1  is low resulting Z 1  output to be pulled approximately VCC voltage level which will then cause charging of the parasitic capacitor CP 1  to VCC level. During this time the signal at output terminal X 3 CNT is high, thus, connecting  11  to output Z 3 . With this condition current will flow from the power supply then to LED 2  and to GND via SW 3  and  11 . During t 1 , the voltage magnitude V Z3  generated at Z 3  output will be
 
 V   Z3   =VCC−Vf   (eq. 4)
 
where VCC is the power supply voltage and Vf is the voltage drop of the LED and is the needed voltage potential for the LED to turn on. When t 1  ends, signal at output terminal Y 1 CNT will be high while the signals at output terminals X 1 CNT, X 2 CNT and X 3 CNT will be low causing Z 1 -Z 3  to go to a HiZ or high-impedance condition. During HiZ condition, the voltage at Z 1  will remain at approximately equal to the power supply voltage because the stray capacitance CP 1  has no discharge path. The time for this HiZ condition is denoted by t D1  as shown in  FIG. 9 . t D1  is inserted to prevent miss operation during the turning off of the PMOS switches and the ghost image prevention block, GIP  104 . As can be seen in  FIG. 9  t D1  is also inserted at the end of GICNT signal. At the end of the first t D1 , the signal at the output terminal GICNT will change to high level will cause CP 1  to discharge to a predetermined level, for this case the LED outputs discharges to voltage half of the power supply. Z 2  will also discharge to half VCC level while Z 3  will charge up to half VCC level. Please note that Z 3  pin may also discharge when VCC−Vf is more than half of VCC. The charging/discharging action will cause all LED output to be at half VCC at the beginning of time t 2 . When t 2  starts PMOS 2  will be on and the signal at the output terminal X 3 CNT will be high causing current to flow through LED 4  which was the only LED expected to be on. The ghost images were suppressed due the fact that Z 1 -Z 3  is all at half of the VCC level, and voltage potential are not enough to turn on other LEDs.
 
     Having described the above embodiment of the invention, various alternations, modifications or improvement could be made by those skilled in the art. Such alternations, modifications or improvement are intended to be within the spirit and scope of this invention. The above description is by ways of example only, and is not intended as limiting. The invention is only limited as defined in the following claims.