Abstract:
Apparatus for loading boot code including a non-volatile memory for the storage of the boot code, a micro-control unit for the storage of a small boot code, a microprocessor, and a volatile memory; and wherein the microprocessor copies the boot code from the non-volatile memory into the volatile memory using the small boot code. A corresponding method is also disclosed.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to a method and apparatus for the loading of boot code for a microprocessor and refers particularly, though not exclusively, to a method and apparatus of loading boot code stored in NAND Flash memory. 
       BACKGROUND TO THE INVENTION 
       [0002]    Boot code is the first piece of code loaded and executed by a microprocessor. The boot code resides in a known location of memory and the microprocessor executes the boot code at the known location. Boot code is normally stored in non-volatile memory such as, for example, EPROM, ROM or NOR Flash as it can&#39;t be lost and needs to be present even after a power loss. 
         [0003]    Microprocessor systems also need volatile memory (such as, for example, RAM) to store variables and changeable data. As such, microprocessor systems have both volatile and non-volatile memory. 
         [0004]    A low-cost form of non-volatile Flash memory is available—NAND Flash. Although it is of very low cost, and is therefore attractive to equipment manufacturers, it has not been extensively used as it has a limited interface. It&#39;s contents cannot be addressed and read individually but must be read as a block. This prevents it from being used as non-volatile memory holding boot code that needs to be read and executed directly by the microprocessor. One method developed to overcome this is illustrated in  FIG. 1 . An external ASIC is used to maintain the microprocessor in the Reset state while it reads code from the NAND Flash. The ASIC copies the entire code into the RAM before releasing the Reset, thereby allowing the microprocessor to execute the code from the RAM. 
       SUMMARY OF THE INVENTION 
       [0005]    In accordance with a preferred aspect of the invention there is provided apparatus for loading boot code including a non-volatile memory for the storage of the boot code, a micro-control unit for the storage of a small boot code, a microprocessor, and a volatile memory; and wherein the microprocessor copies the boot code from the non-volatile memory into the volatile memory using the small boot code. 
         [0006]    Preferably, the small boot code is storable in a part of the volatile memory reserved for the boot code, and is for controlling the microprocessor to copy the boot code from the non-volatile memory into the volatile memory. 
         [0007]    The microprocessor may have a serial port and a Serial-to-RAM logic block. The micro-control unit may be for asserting a setup pin on power-on to enable the Serial-to-RAM logic block to receive a special code from the serial port. The Serial-to-RAM logic block may be for loading the small boot code from the micro-control unit into the volatile memory. 
         [0008]    Alternatively, the microprocessor may have a JTAG interface and data address and control pins. The micro-control unit may be for asserting a RESET pin to maintain the microprocessor in a RESET state to enable the micro-control unit to write the small boot code into the volatile memory. The RESET pin may be de-asserted to enable the microprocessor to operate normally under the control of the small boot code to copy the boot code from the non-volatile memory into the volatile memory. 
         [0009]    After the boot code is copied into the volatile memory the microprocessor may be operable normally under the control of the boot code. The non-volatile memory may be a NAND Flash memory, and the volatile memory may be RAM. 
         [0010]    In another preferred form, there is provided a method for loading boot code stored in a non-volatile memory, including activating a micro-control unit having a small boot code stored therein, and using a microprocessor to load the boot code from the non-volatile memory into a volatile memory using the small boot code. 
         [0011]    The small boot code may be stored in a part of the volatile memory reserved for the boot code, and the small boot code may control the microprocessor to copy the boot code from the non-volatile memory into the volatile memory. 
         [0012]    The microprocessor may have a serial port and a Serial-to-RAM logic block. The micro-control unit may assert a setup pin on power-on to enable the Serial-to-RAM logic block to receive a special code from the serial port. The Serial-to-RAM logic block may load the small boot code from the micro-control unit into the volatile memory. 
         [0013]    Alternatively, the microprocessor may have a JTAG interface and data address and control pins. The micro-control unit may assert a RESET pin to maintain the microprocessor in a RESET state to enable the micro-control unit to write the small boot code into the volatile memory. The RESET pin may be de-asserted to enable the microprocessor to operate normally under the control of the small boot code to copy the boot code from the non-volatile memory into the volatile memory. 
         [0014]    After the boot code is copied into the volatile memory the microprocessor may operate normally under the control of the boot code. 
         [0015]    There is also provided a computer when fitted with such apparatus as described above; and when used to perform the method as described above; and a computer useable medium comprising a computer program code that is configured to cause a processor to execute one or more functions as described above; and a computer system that comprises one or more means for performing corresponding one or more functions as described above. 
     
    
     
       DESCRIPTION OF THE DRAWINGS 
         [0016]    In order that the invention may be better understood and readily put into practical effect there shall now be described by way of non-limitative example only preferred embodiments of the present invention, the description being with reference to the accompanying illustrative drawings in which: 
           [0017]      FIG. 1  is a block diagram showing the present state of the art; 
           [0018]      FIG. 2  is a block diagram of a first embodiment incorporating the present invention at a first state; 
           [0019]      FIG. 3  is a block diagram of the first embodiment at a second state; 
           [0020]      FIG. 4  is a block diagram of the first embodiment at a third state; 
           [0021]      FIG. 5  is a flow chart for the method of the first embodiment; 
           [0022]      FIG. 6  is a block diagram of a second embodiment incorporating the present invention at a first state; 
           [0023]      FIG. 7  is a block diagram of the second embodiment at a second state; and 
           [0024]      FIG. 8  is a flow chart for the method of the second embodiment. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0025]    To first refer to  FIGS. 2 to 4 , there is shown NAND Flash memory  10 , a micro-control unit  12  having a small boot code  14  built-in and stored in its internal ROM, microprocessor  16 , and RAM  18 . 
         [0026]    The micro-control unit  12  is a relatively simple microprocessor such as an 8-bit microprocessor. As such, it would be relatively inexpensive. It may have a number of functions such as, for example, ten functions, and has a connector, preferably a serial port. 
         [0027]    The microprocessor  16  also has a serial port  20  and a Serial-to-RAM logic block  22 . When power is initially applied, a setup pin is applied. The Serial-to-RAM logic block  22  then starts, but only when the setup pin is applied. During the power-on stage, the micro-control unit  12  asserts the setup pin; and the Serial-to-RAM logic block  22  waits for a special code to be received from the serial port  20  to activate the next stage or mode. This special code may be, for example, ASCII “U”. When the special code is received, the Serial-to-RAM logic block  22  then waits for the small boot code data  14  to be sent by the micro-control unit  12 . When the data is sent, it is written into the RAM  18  by the Serial-to-RAM logic block  22 . The data is written in the RAM  18  in the location  24  reserved for boot code. 
         [0028]    The Serial-to-RAM logic block  22  is then disabled be de-asserting the setup pin. The microprocessor then runs as per normal. As the small boot code  14  is in the boot code location  24 , it is executed by the microprocessor  16  and the small boot code  14  has control of the microprocessor  16 . 
         [0029]    The small boot code  14  then copies data from the NAND Flash  10  to the RAM  18 . The data copied includes the operating system and application programs. Once copying is complete, control passes to the operating system. 
         [0030]    In  FIGS. 5 and 6  there is shown a variation. Here the same reference numerals are used for like components but with a prefix number of 2 indicating a second embodiment. Here, a JTAG interface  226  is used in the microprocessor  216 . The JTAG interface  226  has special pins on the integrated circuit that are daisy-chained to all other pins on the integrated circuit by the use of special logic. This allows an external device to shift data to all the pins of the integrated circuit and, at a given signal, latch the data onto the pins. It also allows the actual data on the integrated circuit pins to be read at the same time and to be shifted to an external device. The JTAG interface allows the external device to read data on all the integrated circuit pins and to write any data onto the same pins. 
         [0031]    As before, the micro-control unit  212  asserts the RESET pin to maintain the microprocessor  216  in the RESET state. Using the JTAG interface  226 , the microprocessor  216  then shifts data into the microprocessor  216  to control the microprocessor  216  pins. Using that method, the micro-control unit  212  writes the small boot code  214  into the RAM  218 . The RESET pin is then de-asserted and the microprocessor  216  executes normally with the small boot code  214  controlling the microprocessor  216 . The small boot code  214  then copies data from the NAND Flash  210  to the RAM  218 . The data copied includes the operating system and application programs. Once copying is complete, control passes to the operating system. 
         [0032]    In this way, the NAND Flash copying function can be performed with minimal additional system cost. Most embedded microprocessor systems have an external micro-control unit to perform such functions as power management and so forth. As the NAND Flash copying function is used only at booting, when most other functions for the micro-control unit are not required, it should not add additional processing burdens to the micro-control unit. As most micro-control units have ample data storage they should easily cope with the storage of the small boot code. 
         [0033]    Furthermore, most microprocessors have a Serial-to-RAM logic block for such functions as code development and code debugging; and most integrated circuits have a JTAG interface for production testing of the integrated circuit. 
         [0034]    Whilst there has been described in the foregoing description preferred embodiments of the present invention, it will be understood by those skilled in the technology that many variations or modifications in details of design, construction or operation may be made without departing from the present invention. 
         [0035]    The present invention extends to all features disclosed both individually and in all possible permutations and combinations.