Abstract:
A comparator circuit providing a hysteresis characteristic which does not change a hysteresis width even if a power supply voltage changes is disclosed. The comparator circuit comprises a differential amplifier including an input terminal, a reference terminal and an output terminal; an input voltage terminal to which an input voltage is applied; a reference voltage terminal to which a reference voltage is applied; at least one level shift means connected between said input voltage terminal and said input terminal, or between said reference voltage terminal and said reference terminal; a current source means connected to the output of said level shift means; and control means for controlling the current value of said current source means in accordance with the output level of said output terminal.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a comparator circuit, particularly to a comparator circuit providing the hysteresis characteristic which does not change the hysteresis width even if the power supply voltage changes. 
     2. Description of the Prior Art 
     In case of configurating a comparator circuit with an IC and giving the hysteresis characteristic to said comparator circuit, the hysteresis width is determined ordinarily with power supply voltage and resistance ratio. In addition, in the case of an integrated circuit which can set from outside the power supply current and bias current such as a low power integrated circuit, such hysteresis width is determined by said current or internal resistance. The power supply voltage is comparatively constant but in some cases changes considerably. 
     FIG. 1 shows the structure of existing ordinary comparator circuit. In FIG. 1, 10 is the high gain differential amplifier having the input terminal (positive side) 1, reference terminal 2 (negative side) and output terminal 3, and its input terminal 1 is connected to the input voltage terminal 4, while the reference terminal 2 to the reference voltage terminal 5. To the input voltage terminal 4, an input voltage V i  is applied while to the reference voltage terminal 5, the reference voltage V r  is applied. When V i  (1)&lt;V r  (2); where V i  (1) is an input voltage at the input terminal 1 and V r  (2) is the reference voltage at the reference terminal 2, the differential amplifier 10 outputs an output voltage V 0  of L (low) level to the output terminal 3, and when V i  (1)&gt;V r  (2), an output voltage V 0  of H (high) level. 
     The proportional operation area is distributed in the vicinity, where V i  (1)=V r  (2) but when the gain is high, such operation area is very narrow and V 0  is considered to change in the form of step when V i  (1)=V r  (2) as shown in FIG. 2. 
     When an output voltage V 0  is fed back to the input terminal 1 of such differential amplifier 10 via the resistor 12 (R f ), the hysteresis characteristic having the width W is obtained as shown in FIG. 2. In FIG. 1, the input voltage terminal 4 to which an input voltage V i  is applied has an input resistance R in  (R in  &lt;R f ) but it is omitted in the drawing. 
     In FIG. 1, if an output voltage V 0  becomes H (high) level, for example, an input voltage V i  (1) is boosted by such H level. Therefore, V 0  does not become L (low), because the relation V i  (1)&lt;V r  (2) is not established if an input voltage V i  (4) is not lowered by that as much as boosted or more. In addition, when an output voltage V 0  changes to H from L, an output voltage V 0  becomes H only when an input voltage V i  (1) is lowered by means of the feedback resistance 12 and resultingly V i  (4) becomes higher than that when the feedback resistance 12 is not used. 
     The hysteresis width W of the comparator circuit having such hysteresis characteristic is influenced by the power supply voltage V cc . Namely, the H level output voltage V 0  is determined by the power supply voltage V cc  and becomes small when the power supply voltage is lowered. Therefore, the circuit shown in FIG. 1 has a disadvantage that a value of input voltage V i  (4) which changes from H level to L or from L level to H and resultingly the hysteresis width W also changes. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a comparator circuit which does not allow the hysteresis width to change due to a change of power supply voltage. 
     It is another object of the present invention to provide a comparator circuit which is capable of sustaining a constant hysteresis width without requiring a change of constant of external elements even when the power supply voltage or power source current is changed in the range of several times of rated value. 
     These objects are attained, according to the present invention, by providing 
     a comparator circuit comprising: 
     a differential amplifier including an input terminal, 
     a reference terminal and an output terminal; 
     an input voltage terminal to which an input voltage is applied; 
     a reference voltage terminal to which a reference voltage is applied; 
     at least one level shift means connected between said input voltage terminal and said input terminal, or between said reference voltage terminal and said reference terminal; 
     a current source means connected to the output of said level shift means; 
     control means for controlling the current value of said current source means in accordance with the output level of said output terminal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows the structure of existing comparator circuit. 
     FIG. 2 shows the hysteresis characteristic of the circuit shown in FIG. 1. 
     FIG. 3 shows the structure of comparator circuit according to an embodiment of the present invention. 
     FIG. 4 is the structure of a comparator circuit according to the other embodiment of the present invention. 
     FIG. 5 is the structure of a comparator circuit according to another embodiment of the present invention. 
     FIG. 6 is an example of the practical circuit corresponding to an embodiment of FIG. 3. 
     FIG. 7 is another example of practical circuit corresponding to an embodiment of FIG. 3. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 3 shows the structure of a comparator circuit according to an embodiment of the present invention. In FIG. 3, the same portions as those in FIG. 1 are given the same numbering. In the circuit of FIG. 3, a level shift means 6 consisting of the base-emitter of transistor Q 1  is provided between the input terminal 1 and input voltage terminal 4 of differential amplifier 10, and a level shift means 7 consisting of the base-emitter of transistor Q 2  is provided between the reference terminal 2 and reference voltage terminal 5 of differential amplifier 10. V cc , V EE  are respectively the high and low voltage power supplies. 
     The emitter follower type transistors Q 1 , Q 2  are driven by a constant current by the current sources 8, 9 so that an input current can be ignored. These currents I 1 , I 2  are given by the following equations. 
     
         I.sub.1 ≈I.sub.s e.sup.q/KT·.spsp.V.sup.BE1 (1) 
    
     
         I.sub.2 ≈I.sub.s e.sup.q/KT·.spsp.V.sup.BE2 (2) 
    
     Here, I s  is the saturation current, q is the change of electron, k is the Boltzman&#39;s constant, T is the absolute temperature, V BE1 , V BE2  are the base emitter voltage of transistors Q 1 , Q 2 . 
     From the equations (1) and (2), 
     
         V.sub.BE1 =KT/q ln I.sub.1 /I.sub.s                        (3) 
    
     
         V.sub.BE2 =KT/q ln I.sub.2 /I.sub.s                        (4) 
    
     Therefore, 
     
         V.sub.BE2 -V.sub.BE1 =KT/q ln I.sub.2 /I.sub.1             (5) 
    
     From the above equation, when I 1  =I 2 , V BE1  =V BE2 , and when I 2  =2I 1 , V BE2  -V BE1  =(kT/q)ln 2≈20(mV). In the case of this circuit, the current source 9 is allowed, for example, to change and the relation I 2  =I 1  is obtained when an output voltage V 0  is L level or the relation I 2  =mI 1  (here m&gt;1) is obtained when it is H level. Thereby, when an output voltage V 0  =L level and V BE  which is the same as that in case I 2  =I 1  is added to the input voltage V i  and reference voltage V r . Therefore it becomes equal to zero, considering it from the differential amplifier 10, and an output voltage V 0  becomes H level when V i  &gt;V r . When an output voltage V 0  becomes H level, the current source 9 outputs mI 1   and V BE2  becomes large as is obvious from the equation (4) (increment is considered as ΔV). Namely, the reference voltage V r  is supposed to be lowered by ΔV when considered from the differential amplifier 10. Therefore, a voltage being input to the input terminal 1 of the differential amplifier 10 seems to be relatively increased. For this reason, when an output voltage V 0  returns to the L level, an input voltage V i  must be lowered by ΔV than the reference voltage V r  and thereby an output voltage V 0  indicates the hysteresis characteristic having the width of ΔV. Moreover, the width ΔV, as is obvious from the equation (5), depends on the physical constants such as k, T, q and a current ratio of I 2  /I 1 , but on the power supply voltage V CC . The hysteresis width thus obtained is not influenced by the power supply voltage fluctuation. In the case of integrated circuits, resistance values fluctuate considerably but a current ratio of the constant current source can be set accurately to the desired value. Resultingly, the hysteresis width can be adjusted accurately by changing such current ratio. 
     Since the hysteresis width is determined by a changed value m of current of the current source 9, when, m=10 (at this time, said width is about 60 mV), a large hysteresis width can be obtained. In addition, when the current source 8 in the input voltage V i  side is increased in the backward direction together with the current source 9, namely when I 2  is increased m times, the hysteresis width is doubled against to that while only one current source is used by changing I 1  to I/m. 
     In such a case where only the current source 9 is changed, the level shift means 6 and current source 8 can be omitted. However, in this case, an input voltage V i  is directly applied to the input terminal 1 (without level shift) and therefore when V i  &gt;V r  -V BE2 , an output voltage V o  turns to the H level from L level. 
     At any rate, the hysteresis characteristic can be obtained by controlling a constant current value of the current source 8 or 9. 
     FIG. 4 shows the structure of a comparator circuit according to another embodiment of the present invention. 
     In FIG. 4, as the level shift means 6, 7, diodes are used and others are the same as those in FIG. 3. 
     FIG. 5 shows the structure of a comparator circuit according to another embodiment of the present invention. 
     As shown in FIG. 4, when the level shift means 6, 7 are formed by inserting in series the diodes to the emitter of transistors Q 1 , Q 2 , amount of change in the forward voltage of diode is added. Therefore, the range of hysteresis width change due to a change of current value of the current source becomes wide. Namely, when values of constant current source are I 1 , I 2  for the L level output voltage V 0  and these are changed respectively to I 1  &#39;, I 2  &#39; for the H level output voltage V 0 , 
     
         ΔV=N(kT/q) ln (I.sub.2 /I.sub.1 ·I.sub.1 &#39;/I.sub.2 &#39;) 
    
     when the sum of the transistors and diodes used for level shifts is considered as N for both inputs. 
     A current value of the constant current source can be done easily, for example, by changing over the two current sources of I 1 , mI 1  prepared with the H and L levels of the output voltage V 0 . 
     FIG. 6 is an example of the practical circuit corresponding to an embodiment of FIG. 3. 
     In this figure, the transistors Q 101  to Q 103 , Q 3 , Q 4  and Q 7  correspond to said differential amplifier 10, and Q 1 , Q 2  are input transistors, while Q 6 , Q 8 , Q 11  are current source transistor and these respectively correspond to said level shift means 6, 7 and current sources 8, 9. 
     The transistors Q 104  to Q 106  controls the circuit for generating the bias current I 0 , while the transistors Q 5 , Q 9 , Q 10  controls the bias current of differential amplifier 10 with said current. In case the output voltage V 0  is L level in this case, the transistor Q 9  is OFF, and resultingly the bias current I 1  of transistor Q 1  is two times of I 0  and the bias current I 2  of transistor Q 2  is equal to I 0 . Therefore, V BE  of transistor Q 1  and V BE  of transistor Q 2  are in the following relation: 
     
         V.sub.BE1 -V.sub.BE2 ≈20 mV 
    
     In addition the base potentials V 1 , V 2  of transistors Q 3 , Q 4  are expressed as follows: 
     
         V.sub.1 =V.sub.i -V.sub.BE1 
    
     
         V.sub.2 =V.sub.r -V.sub.BE2 
    
     Therefore, a difference of these voltages V 1 , V 2  becomes as follows: ##EQU1## 
     When the input voltage V i  changes to H level from L level, the output V 0  changes to H level from L level at the point where V i  =V r  +20 mV. When the output voltage V 0  becomes H level, the transistor Q 9  turns ON and I 1  =I 2  =I 0 . Thus, V 1  -V 2  =V i  -V r . When V i  changes to L level from H level, V 0  becomes L level from H level at the point where V i  =V r . Thus, this circuit has the hysteresis width of ΔV=20 mV. 
     FIG. 7 shows another practical example. This circuit is different from FIG. 6 in such a point that the current source transistors Q 6 , Q 8  are omitted. In this circuit, the base current of transistors Q 3 , Q 4  in the next stage is used as the bias current of level shift means 6, 7 and therefore the hysteresis width ΔW becomes as follows: ##EQU2## 
     β is the current amplification coefficient of the NPN transistors Q 3 , Q 4 . When β changes within the range from 50 to 250, ΔW=120 to 160 mV, resulting in a large hysteresis width. Therefore, the circuit of FIG. 7 is a very effective circuit for a certain purpose. 
     As explained above, according to the present invention, a comparator circuit having the hysteresis characteristic of the accurate width which is not influenced by fluctuation of power source voltage is obtained by the method that the input voltage V i  and/or the reference voltage V r  is shifted by V BE  of transistor and said V BE  is changed in accordance with the output level of the comparator circuit. 
     While the invention has been shown and described with respect to the preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.