Abstract:
A comparator to provide an output voltage indicative of comparing an input voltage with a reference voltage, where the comparator has an asymmetric frequency response. With an asymmetric frequency response, the bandwidth of the input voltage may be greater than the bandwidth of the reference voltage. A comparator includes a differential pair of transistors coupled to a current mirror and biased by a current source, where in one embodiment, a capacitor shunts the sources of the differential pair. In a second embodiment, a capacitor couples the input voltage port to the gates of the current mirror transistors. In a third embodiment, the comparator utilizes both capacitors of the first and second embodiments.

Description:
FIELD 
       [0001]    The present invention relates to comparator circuits, and more particularly, to comparator circuits with asymmetric frequency response. 
       BACKGROUND 
       [0002]    A voltage comparator may be used to compare the value of an input voltage signal V IN  with a reference voltage V REF . In this context, the voltage comparator may be viewed as an amplifier to amplify the difference V REF −V IN  with high gain. Such voltage comparisons are often performed in analog-to-digital converters, peak detectors, zero-crossing detectors, and full-wave rectifiers. Some or all of these mentioned circuits may be utilized in a computer system. For example, consider the computer system illustrated in  FIG. 1 . Microprocessor die  102  comprises many sub-blocks, such as arithmetic logic unit (ALU)  104  and on-die cache  106 . Microprocessor  102  may also communicate to other levels of cache, such as off-die cache  108 . Higher memory hierarchy levels, such as system memory  110 , are accessed via host bus  112  and chipset  114 . In addition, other off-die functional units, such as graphics accelerator  116  and network interface controller (NIC)  118 , to name just a few, may communicate with microprocessor  102  via appropriate busses or ports. Power supply  120  provides a regulated voltage to microprocessor  102 , as well as perhaps other system components in  FIG. 1 . Voltage comparators, for example, may find application in power supply  120  as part of a full-wave rectifier, or may find application in NIC  118  as part of an analog-to-digital converter for signal communication over a physical link (not shown). 
         [0003]    A prior art voltage comparator is shown in  FIG. 2 . The voltage comparator of  FIG. 2  is seen to be a differential amplifier comprising differential pair  202  and  204 , current source  206 , and a current mirror (transistors  208  and  210 ). Two voltage gains may be defined for the differential amplifier of  FIG. 2 . Let A IN  denote the input voltage gain |v OUT /v IN | when V REF  is held constant, where v OUT  is the small-signal voltage component of V OUT  and v IN  is the small-signal voltage component of V IN . Let A REF  denote the reference voltage gain |v OUT /v REF | when V IN  is held constant, where v REF  is the small-signal voltage component of V REF . 
         [0004]    Prior art voltage comparators tend to have approximately equal 3 dB bandwidths for the two gains A IN  and A REF . A typical frequency response for the comparator of  FIG. 2  is shown in  FIG. 3 , where curves for the two voltage gains A REF  and A IN  are labeled as such. From  FIG. 3 , it is seen that the two 3 dB bandwidths are approximately equal to each other. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]      FIG. 1  is a simplified, high-level abstraction of a computer system. 
           [0006]      FIG. 2  is a prior art comparator at the circuit level. 
           [0007]      FIG. 3  shows a typical frequency response for the comparator of  FIG. 2 . 
           [0008]      FIG. 4  is an embodiment of the present invention. 
           [0009]      FIG. 5  is a high-frequency equivalent circuit for the input signal gain of the comparator of  FIG. 4 . 
           [0010]      FIG. 6  shows a typical frequency response for the comparator of  FIG. 4 . 
           [0011]      FIG. 7  is another embodiment of the present invention. 
           [0012]      FIG. 8  is a high-frequency equivalent circuit for the input signal gain of the comparator of  FIG. 7 . 
           [0013]      FIG. 9  shows a typical frequency response for the comparator of  FIG. 7 . 
           [0014]      FIG. 10  is another embodiment of the present invention that incorporates the features of both of the embodiment comparators of  FIGS. 4 and 7 . 
           [0015]      FIG. 11  is the dual of the comparator circuit of  FIG. 4 . 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0016]    In some applications for voltage comparators, the bandwidth of reference voltage signal V REF  may be significantly less that that of the input voltage signal V IN . In particular, voltage comparators may be used in a power supply noise monitor employing a maximum and minimum detector circuit. In this particular application, the reference voltage signal V REF  is a relatively low-frequency or DC signal and the input voltage signal V IN  is a relatively high-frequency signal. In such applications, it is not necessary for a voltage comparator to have equal 3 dB bandwidths for the reference voltage gain A REF  and the input voltage gain A IN . Embodiments of the present invention take advantage of this observation by trading off bandwidth for the reference voltage gain for an increase in bandwidth for the input voltage gain. As a result, embodiments of the present invention have an asymmetric frequency response, and may be termed asymmetric frequency response high-speed comparators. 
         [0017]    An embodiment of the present invention is provided in  FIG. 4 , showing a voltage comparator comprising differential pair  404  and  408 , current mirror  412 , current source  406 , and capacitor  420 . Voltage reference source  402  provides reference voltage V REF  at the gate of nMOSFET  404 . The gate of nMOSFET  408  is at the input voltage V IN . Current source  406  provides bias current to differential pair nMOSFETs  404  and  408 . The output voltage V OUT  may be considered to be taken at output port (node)  410 . Current mirror  412  provides bias current and a relatively large small-signal load impedance to nMOSFET  408 . Various current mirrors may be employed. In the particular embodiment of  FIG. 4 , current mirror  412  comprises pMOSFETs  414  and  416  connected as shown. Capacitor  420  is connected in parallel with current source  406 , providing a capacitive impedance path from node  422  to rail  424 . (Rail  424  may be ground, a substrate, or a power rail.) At high frequencies, capacitor  420  shunts node  422  to rail  424 . The two voltage gains A IN  and A REF  for the voltage comparator of  FIG. 4  are defined in similar fashion to those of  FIG. 2 . 
         [0018]    The load at output port  410  is represented by utilization circuit  418 . In general, utilization circuit  418  utilizes V OUT  to perform a useful function, such as, for example, a control function for voltage regulation or analog-to-digital conversion. Utilization circuit  418  may comprise a latch circuit to latch output voltage V OUT  at specific time instants controlled by clock signal φ. 
         [0019]    For the embodiment of  FIG. 4  at low frequency operation, ωC &lt;&lt;1/Z, where C is the capacitance of capacitor  420 , ω is the signal frequency of either V IN  or V REF , and Z is the small-signal impedance of current source  406 , the voltage comparator behaves similarly to the amplifier of  FIG. 2 . In particular, the circuits of  FIGS. 4 and 2  have identical DC voltage gains, and consequently the presence of capacitor  402  does not cause overshoot or undershoot in the frequency characteristics of the voltage gains A IN  and A REF  for the voltage comparator of  FIG. 2 . 
         [0020]    At high frequency operation, ωC &gt;&gt;1/Z, the voltage comparator of  FIG. 4  behaves very differently from that of  FIG. 2 . For the input voltage gain A IN , a high frequency equivalent circuit for the voltage comparator of  FIG. 4  is provided in  FIG. 5 , where corresponding transistors in  FIGS. 4 and 5  are labeled accordingly. The bias voltage V BIAS  is the gate and drain voltage of pMOSFET  414 . At high frequencies, V BIAS  may be considered constant because, as discussed earlier, V REF  is held constant when considering the voltage gain A IN , and capacitor  420  provides a high-frequency short circuit to rail  424 . 
         [0021]    The circuit of  FIG. 5  is seen to be a simple single-stage, common-source amplifier. At high frequency operation, device parasitic capacitance causes a reduction in voltage gain A IN  for both voltage comparators of  FIGS. 2 and 4 . However, because the capacitances due to transistors  404  and  414  do not play a role in the high frequency equivalent circuit of  FIG. 5 , the circuit of  FIG. 5  has less parasitic capacitance in the signal path of V IN  compared to the voltage comparator of  FIG. 2 . Consequently, the 3 db bandwidth for the input voltage gain A IN  of the voltage comparator of  FIG. 4  is larger than that of  FIG. 2  (assuming the same technology and device sizes are used for both circuits in  FIGS. 2 and 4 ). 
         [0022]      FIG. 6  provides typical voltage gain curves for the voltage comparator of  FIG. 4  compared to that of  FIG. 2 . In  FIG. 6 , the two voltage gain curves A REF  and A IN  for the voltage comparator of  FIG. 4  are solid curves and labeled as A REF  and A IN , respectively. The two voltage gain curves A REF  and A IN  for the voltage comparator of  FIG. 2  are dashed curves and labeled as A REF ′ and A IN ′ respectively. The curves in  FIG. 6  illustrate the tradeoff in 3 db bandwidth, where the presence of capacitor  420  increases the 3 db bandwidth of A IN  at the expense of decreasing the 3 db bandwidth of A REF . However, as discussed in the Background, for many applications there is no penalty in decreasing the 3 db bandwidth of A REF  because the bandwidth of the reference voltage signal is much less than the bandwidth of the input voltage signal. 
         [0023]    Another embodiment of the present invention at the circuit level is provided by  FIG. 7 , where for simplicity a utilization circuit and voltage reference source are not shown. In  FIG. 7 , capacitor  702  provides a capacitive impedance path from input port  704  to node  706 , where node  706  may be taken as the gates of current mirror transistors  708  and  710  or as the drain of pMOSFET  708 . For the input voltage gain A IN , a high frequency equivalent of the circuit of  FIG. 7  is shown in  FIG. 8 , where corresponding transistors in  FIGS. 8 and 7  are labeled accordingly. Resistor  802  in  FIG. 8  represents the high-frequency, small-signal output impedance of current source  714 . 
         [0024]    The circuit of  FIG. 8  is similar to an inverter amplifier. The small-signal DC gain for the circuit in  FIG. 8  is larger than the small-signal DC gain of the differential amplifier of  FIG. 2 . Accordingly, with proper sizing of capacitor  702 , the 3 db bandwidth for the voltage gain A IN  for the circuit of  FIG. 7  may be increased over that of  FIG. 2 . A similar tradeoff in A IN  and A REF  for the circuit of  FIG. 7  results as for the case with the circuit of  FIG. 4 . The curves for the voltage gains A IN  and A REF  of the circuit of  FIG. 7  are similar to that of  FIG. 6 , and also show that the presence of capacitor  702  allows an increase in A IN  to at the expense of a decrease in A REF . 
         [0025]      FIG. 9  shows in a general way the effect that an increasing capacitance of capacitor  702  has upon the input voltage gain A IN , where the arrow in  FIG. 9  indicates the correspondence between the gain curves and increasing capacitance. As seen in  FIG. 9 , increasing capacitance can lead to a high frequency voltage gain exceeding the DC gain, thereby causing an overshoot in the frequency characteristic of the voltage gain. Consequently, in a preferred embodiment, the capacitance of capacitor  702  should be sized properly to avoid overshoot. Depending upon the capacitance of capacitor  702 , anywhere between 0% and 100% of v IN  may be coupled to node  706 . Overshoot is prevented if this coupling is less than g m712 /2g m710 , where g m712  and g m710  are the small-signal transconductances of transistors  712  and  710 , respectively. If a flat frequency response is not important, then overshoot may be tolerated. 
         [0026]    In another embodiment, two capacitors,  1002  and  1004 , may be utilized as shown in  FIG. 10 , resulting in a further increase in input voltage gain A IN  at the expense of a further decrease in reference voltage gain A REF . The remarks on overshoot regarding the circuit of  FIG. 7  also apply to the circuit of  FIG. 10 . Various modifications may be made to the disclosed embodiments without departing from the scope of the invention as claimed below. For example, other embodiments dual to those disclosed above may be realized by replacing the nMOSFETs with pMOSFETs. An example of the dual to the voltage comparator of  FIG. 4  is shown in  FIG. 11 . Furthermore, it is to be understood in these letters patent that the phrase “A is connected to B” means that A and B are directly connected to each other by way of an interconnect, such as metal or polysilicon. This is to be distinguished from the phrase “A is coupled to B”, which means that the connection between A and B may not be direct. That is, there may be an active device or passive element between A and B. It is also to be understood in these letters patent that a “current source” may mean either a current source or a current sink.