Abstract:
Disclosed is a method for rapidly and precisely detecting phase by a level trigger method. A phase detector includes a false lock preventing section which includes multiple latches, a lock discriminating section and a reset section. An input signal is sequentially latched to a reference signal and multiple delay signals to generate first and second latch signals different in phase from the reference signal. First and second lock discriminating signals having information about phase of the reference signal and phases of the delay signals are generated by the first and second latch signals. A reset signal is generated by a NAND gate when first and second lock discriminating signals are received. The reset signal reverses the latch signals and lock discriminating signals. A phase difference between reference signal and delay signals is detected by receiving reversed lock discriminating signals. Phases are rapidly detected by using latches.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims priority from Korean Patent Application No. 2003-61102, filed on Sep. 2, 2003, the contents of which are incorporated herein by reference in their entirety.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a phase detector and a method of detecting phase. More particularly, the present invention relates to a method of detecting phase and a phase detector capable of rapidly detecting phase.  
         [0004]     2. Description of the Related Art  
         [0005]     A Delay Locked Loop (DLL) generates a plurality of delay signals from a plurality of delay elements. The delay signals should have a definite phase relationship with a reference signal so that the delay signals may have predetermined phase differences from the reference signal. However, the desired delay signals having the predetermined phase differences may not be generated due to time delay by various causes. Therefore, there is a need for a phase detector capable of having the desired phase differences between the reference signal and the delay signals. The phase detector compares phases of the delay signals with the phase of the reference signal to generate information concerning a delay time. As a result, the DLL including the phase detector varies the delay signals by the delay time to generate the desired delay signal. This condition is designated as locking.  
         [0006]     A conventional phase detector does not discriminate between t 1  and T (period)+t 1 . As a result, even though the delay signal should be locked at t 1 , the DLL may discriminate that the delay signals is locked at T+t 1 . In addition, the conventional phase detector detects the phase late. One prior art solution to the problem of the false locking is disclosed in U.S. Pat. No. 6,215,343, which proposes a delay locked loop to eliminate the false locking, which comprises a chain of at least two delay elements consisting of multiple flip-flops having an input and an output, a phase comparator having first and second inputs and an output for delivering a binary control signal, and a converter for converting the binary control signal into an analog control signal. In such a technique, initialization flip-flops and the chain of flip-flops are triggered by clock inputs so that the outputs of the flip-flops are changed. Therefore, in a chain of multiple flip-flops, speed delay in each of flip-flops is accumulated, thereby resulting in great delay in total operation speed between the initial input terminal and final output terminal.  
       SUMMARY OF THE INVENTION  
       [0007]     Accordingly, the present invention is provided to substantially obviate one or more problems due to limitations and disadvantages of the related art.  
         [0008]     It is a feature of the present invention to provide a method of detecting phase at improved speed and a phase detector, in which the phase difference can be detected more rapidly and accurately.  
         [0009]     In accordance with one aspect of the invention, a method of detecting phase latches in sequence an input signal to a reference signal and a plurality of delay signals different in phase from the reference signal, thereby generating a first and second latch signals. First and second lock discriminating signals are generated using the first and second latch signals. The first and second lock discriminating signals include information concerning the phase of the reference signal and the phases of the delay signals, respectively. A reset signal is generated using the first and second lock discriminating signals. The first and second latch signals and the first and second lock signals are reversed using the reset signal. The phase difference between the reference signal and the delay signals is detected using the reversed first and second lock discriminating signals.  
         [0010]     In accordance with another aspect of the invention, a method of detecting phase latches an input signal having high logic to a plurality of delay signals to generate first and second latch signals, wherein the delay signals have in sequence predetermined phase difference from the reference signal. The latch signals pass through D flip-flops to generate first and second lock discriminating signals having information concerning phases of the reference signal and the delay signals, respectively. A logical NAND operation is performed on the lock discriminating signals to generate a reset signal. The latch signals and the lock discriminating signals are reversed using the reset signal. The phase difference between the reference and the delay signals is detected using the reversed lock discriminating signals.  
         [0011]     In accordance with another aspect of the invention, a phase detector includes a false lock preventing section, a lock discriminating section and a reset section. The false lock preventing section latches in sequence an input signal to a reference signal and a plurality of delay signals different in phase from of the reference signal, thereby generating first and second latch signals. The lock discriminating section receives the first and second latch signals to generate a first and second lock discriminating signals, which include information concerning the phases of the reference signal and the delay signals respectively. The reset section receives the first and second lock discriminating signals to reverse the latch signals and the lock discriminating signals.  
         [0012]     In accordance with another aspect, a phase detector includes a false lock preventing section, a lock discriminating section and a reset section. The false lock preventing section latches an input signal having high logic to a plurality of delay signals, thereby generating first and second latch signals, wherein phases of the delay signals have predetermined difference from phase of the reference signal. The lock discriminating section allows the first and second latch signals to pass through D flip-flops so that first and second lock discriminating signals having information concerning the phases of the reference signal and the delay signals may be generated. The reset section receives the lock discriminating signals to perform a logical NAND operation on the lock discriminating signals so that a reset signal may be generated, wherein the reset signal reverses the latch signals and the lock discriminating signals.  
         [0013]     As described above, a method of detecting a phase and a phase detector rapidly detect the phases of the signals using the latches.  
         [0014]     In addition, the method of detecting the phase and the phase detector compare the phases of signals using the latches coupled in series, the phases thereof are exactly detected. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]     The foregoing and other features and advantages of the invention will be apparent from the more particular description of an embodiment of the invention, as illustrated in the accompanying drawing. The drawing is not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.  
         [0016]      FIG. 1  is a block diagram illustrating a phase detector according to an embodiment of the invention.  
         [0017]      FIG. 2  is a block diagram illustrating a lock discriminating section according to an embodiment of the invention.  
         [0018]      FIG. 3  is a schematic view illustrating the circuit of the phase detector according to an embodiment of the invention.  
         [0019]      FIG. 4  is a timing diagram illustrating detecting phase in a conventional phase detector.  
         [0020]      FIG. 5  is another timing diagram illustrating detecting phase in the conventional phase detector.  
         [0021]      FIG. 6  is a timing diagram illustrating operation of the phase detector according to an embodiment of the invention.  
         [0022]      FIG. 7  is a timing diagram illustrating operation of the phase detector according to an embodiment of the invention.  
         [0023]      FIG. 8  is a timing diagram illustrating operation of the phase detector according to an embodiment of the invention.  
         [0024]      FIG. 9  is a timing diagram illustrating operation of the phase detector according to an embodiment of the invention.  
         [0025]      FIG. 10  is a flow chart illustrating operation of the DLL using the phase detector of the invention.  
         [0026]      FIG. 11  is a timing diagram illustrating the improvement in speed of the phase detector according to the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0027]     Detailed illustrative embodiments of the present invention are described herein. However, specific structural and functional details disclosed herein are merely representative for purposes of describing exemplary embodiments of the present invention.  
         [0028]      FIG. 1  is a block diagram illustrating a phase detector according to an embodiment of the invention.  
         [0029]     Referring to  FIG. 1 , the phase detector of the invention includes a false lock preventing section  10 , a lock discriminating section  30  and a reset section  50 .  
         [0030]     The phase detector may be used for a Delay Locked Loop (DLL). The DLL has less jitter than a Phase Locked Loop (PLL) and is less sensitive to noise than the PLL.  
         [0031]     The false lock preventing section  10  latches in sequence an input signal to a reference signal ref and a plurality of delay signals, thereby generating a first latch signal Q 1  and a second latch signal Q 4  for preventing the false locking. The phases of the delay signals are different from the phase of the reference signal. The input signal has a high logic; that is, the input signal is logical “1”. The delay signals have predetermined phase differences in sequence from the reference signal. For the purpose of an illustrative example, the number N of the delay signals is chosen to be  4 . In this case, the delay signals include a first delay signal D 1 , a second delay signal D 2 , a third delay signal D 3  and a fourth delay signal D 4 . At this time, the first delay signal D 1  has T/4 phase difference from the reference signal, the second delay signal D 2  has T/2 phase difference from the reference signal, the third delay signal D 3  has 3 T/4 phase difference from the reference signal, and the fourth delay signal D 4  has T phase difference from the reference signal. The T indicates the period of the reference signal.  
         [0032]     The lock discriminating section  30  receives the first latch signal Q 1  and the second latch signal Q 4  to generate a first lock discriminating signal Q 5  and a second lock discriminating signal Q 6  so that it discriminates phases of the reference signal and the delay signals. In detail, the lock discriminating section  30  receives the first latch signal Q 1  and the second latch signal Q 4  and passes the signals Q 1  and Q 4  through a flip flop to generate the first lock discriminating signal Q 5  and the second lock discriminating signals Q 6 . In addition, the lock discriminating section  30  provides the generated first and second lock discriminating signals Q 5  and Q 6  to a reset section  50 .  
         [0033]     The reset section  50  receives the first and second lock determining signals Q 5  and Q 6  to generate a reset signal. Particularly, the reset section  50  passes the first and second lock discriminating signals through a NAND gate to generate the reset signal. The reset signal is transmitted to the false lock preventing section  10  and the lock discriminating section  30 .  
         [0034]     The phase detector of the invention further includes a comparing section (not shown) for comparing the first lock discriminating signal Q 5  with the second lock discriminating Q 6  signal to generate a comparison signal having information concerning the comparison result.  
         [0035]     The false lock preventing section  10  includes a first latch section  100  and a second latch section  120 .  
         [0036]     The first latch section  100  latches the input signal having a high logic to the reference signal, thereby generating the first latch signal Q 1 .  
         [0037]     The second latch section  120  latches in sequence the first latch signal Q 1  to the delay signals D 1 , D 2  and D 3 , thereby generating the second latch signal Q 4 . Particularly, the second latch section  120  shifts the first latch signal Q 1  in correspondence with the delay signals D 1  to D 3 .  
         [0038]     Because the phase detector of the invention latches the input signal to the delay signals for locking, the phase detector can perform rapidly the locking operation compared to a conventional phase detector.  
         [0039]      FIG. 2  is a block diagram illustrating the lock discriminating section  30  according to an embodiment of the invention.  
         [0040]     Referring to  FIG. 2 , the lock discriminating section  30  includes a first lock discriminator  200  and a second lock discriminator  220 .  
         [0041]     The first lock discriminator  200  receives the first latch signal Q 1  and passes the signal Q 1  through a first flip-flop to generate the first lock discriminating signal.  
         [0042]     The second lock discriminator  220  receives the second latch signal Q 4  and passes the signal Q 4  through a second flip-flop to generate the second lock discriminating signal Q 6 .  
         [0043]      FIG. 3  is a schematic view illustrating a circuit of the phase detector according to an embodiment of the invention.  
         [0044]     As shown in  FIG. 3 , the first latch section  100  includes two D latches. The D latches include a reset terminal and an output terminal. The D latches latch the input signal of high logic to the reference signal, thereby generating an output signal. Here, the output signals corresponding to the D latches are substantially identical to each other. Therefore, the first latch section  100  may generate an output signal Q 1  using a D latch, and transmit the output signal Q 1  to the second latch section  120  and the lock discriminating section  30 . On the other hand, load of the circuit of the invention is smaller when the first latch  100  employs the two D latches than when the first latch  100  employs one D latch.  
         [0045]     The second latch section  120  includes a plurality of latches. The latches are coupled in series. For example, the latches include a first latch, a second latch and a third latch. The input terminal of the first latch is coupled to the first latch section  100 . The output terminal of the first latch is coupled to the input terminal of the second latch. The output terminal of the second latch is coupled to the input terminal of the third latch. In addition, the first latch receives a first delay signal D 1 . The second latch receives a second delay signal D 2 . The third latch receives a third delay signal D 3 . The delay signals D 1  to D 3  have predetermined phase difference in sequence from the reference signal.  
         [0046]     The lock discriminating section  30  includes a first flip-flop and a second flip flop. The first flip-flop is coupled in parallel to the second flip-flop.  
         [0047]     The reset section  50  includes a NAND gate. The NAND gate is coupled to the first flip-flop and the second flip-flop.  
         [0048]     The first latch section  100  and the second latch section  120  of the invention employ the latches instead of a plurality of flip-flops. Therefore, the phase detector of the invention compares rapidly phases of the delay signals with phase of the reference signal compared to a conventional phase detector.  
         [0049]      FIG. 4  contains a timing diagram that illustrates operation of detecting a phase in the conventional phase detector, and  FIG. 5  contains another timing diagram that illustrates operation of detecting a phase in the conventional phase detector.  
         [0050]     Referring to  FIG. 4 , in case of locking, the delay signals have T/4 phase difference in sequence from the reference signal. However, the delay signals have delays by various cases, and so the first delay signal D 1 , the second delay signal D 2 , the third delay signal D 3  and the fourth delay signal D 4  as shown in,  FIG. 4  are generated. Hence, in the DLL, the delay signals ought to be locked. The first to third delay signals are locked when the fourth delay signal is locked. This is because the first to third delay signals are latched in sequence.  
         [0051]     Referring to  FIG. 5 , the first delay signal D 1  has T/4+t 1  phase difference from the reference signal. The second delay signal D 2  has T/2+t 2  phase difference from the reference signal. The third delay signal D 3  has 3 T/4+t 3  phase difference from the reference signal. The fourth delay signal D 4  has T+t 4  phase difference from the reference signal. Therefore, the T+t 4  phase difference ought to be compensated for locking. However, the DLL employing a conventional phase detector stops the compensating operation after compensating the fourth delay signal D 4  by t 4 . This is because the conventional phase detector does not discriminate between t 4  and T+t 4  so that the conventional phase detector determines incorrectly that the phase of the compensated fourth delay signal is substantially identical to that of the reference. This indicates false lock.  
         [0052]      FIG. 6  is a timing diagram illustrating operation of the phase detector according to an embodiment of the invention.  
         [0053]     As shown in  FIG. 6 , when the delay signals are locked with the reference signal, the first lock discriminating signal Q 5  is substantially identical to the second lock discriminating signal Q 6 . That is, when the first lock discriminating signal Q 5  is substantially identical to the second lock discriminating signal Q 6 , the delay signals are locked.  
         [0054]      FIG. 7  is a timing diagram illustrating operation of the phase detector according to an embodiment of the invention.  
         [0055]     As shown in  FIG. 7 , the delay time of the first delay signal D 1  is t 1 , and that of the second delay signal D 2  is t 2 . In addition, the delay time of the third delay signal D 3  is t 3 , and that of the fourth delay signal D 4  is t 4 .  
         [0056]     Now referring to  FIG. 3 , the first latch signal corresponds to a Q 1  signal in  FIG. 7 . When a delay signal has high logic, a D latch reads input data, whereas when the delay signal has low logic, the D latch keeps the read input data. The logic of reference signal is changed from low to high at T 4 . Because the input signal has high logic, the data of the input signal at T 4  is read. As a result, the Q 1  signal is generated.  
         [0057]     The second latch section  120  of the invention includes latches coupled in series to each other. The first latch receives the Q 1  signal and the first delay signal D 1 . Therefore, the data of the Q 1  signal is read at T 0 +t 1 , and so the first latch generates a Q 2  signal. The second latch receives the Q 2  signal and the second delay signal D 2 . Therefore, the data of the Q 2  signal is read at T 1 +t 2 , and so the second latch generates a Q 3  signal. The third latch receives the Q 3  signal and the third delay signal D 3 . Therefore, the Q 3  signal is read at T 4 +t 3 , and so the third latch generates the Q 4  signal.  
         [0058]     The first latch signal Q 1  is inputted into a first flip-flop of the lock discriminating section  30 , and the reference signal is provided to the first-flip flop as a clock. Therefore, the data of the first latch signal Q 1  is read at T 3 , and so the first lock discriminating signal Q 5  is generated from the first flip-flop. The Q 4  signal is inputted into the second flip-flop of the lock discriminating section  30 , and the fourth delay signal D 4  is provided to the second flip-flop as a clock. Therefore, the data of the Q 4  signal is read at T 3 +t 4 , and so the second lock discriminating signal Q 6  is generated.  
         [0059]     The first and second lock discriminating signals Q 5  and Q 6  are inputted into the NAND gate. As a result, the reset signal RS is generated from the NAND gate. When each of the first and second lock discriminating signals Q 5  and Q 6  is high logic, the logic of the reset signal RS is low. The reset signal resets the latches and the flip-flops. Hence, the Q 1  signal, the Q 2  signal, the Q 3  signal, the Q 4  signal, the first lock discriminating signal Q 5  and the second lock discriminating signal Q 6  are reversed as shown in  FIG. 7 . When the reversed first lock discriminating signal is compared with the reversed second lock discriminating signal, time difference corresponding to t 5  is generated. Therefore, the DLL changes delay time corresponding to the t 5 . Particularly, the delay time corresponding to the t 5  ought to be reduced.  
         [0060]      FIG. 8  is a timing diagram illustrating operation of the phase detector according to one embodiment of the invention.  
         [0061]     As shown in  FIG. 8 , the delay time of the first delay signal D 1  is reduced by t 1 . The delay time of the second delay signal D 2  is reduced by t 2 . The delay time of the third delay time is reduced by t 3 . The delay time of the fourth delay signal D 4  is reduced by t 4 .  
         [0062]     Now referring to  FIG. 3 , the first latch signal corresponds to a Q 1  signal in  FIG. 8 . The logic of the reference signal is converted from low into high. Because the input signal has high logic, the data of the input signal is read at T 4 . As a result, the Q 1  signal is generated. The first latch of the latch section  120  receives the Q 1  signal and the first delay signal D 1 . Therefore, the data of the Q 1  signal is read at T 0 −t 1 , and so the first latch generates a Q 2  signal. The second latch thereof receives the Q 2  signal and the second delay signal D 2 . Therefore, the data of the Q 2  signal is read at T 1 −t 2 , and so the second latch generates a Q 3  signal. The third latch thereof receives the Q 3  signal and the third delay signal D 3 . Therefore, the data of the Q 3  signal is read at T 2 −t 3 , and so the third latch generates a Q 4  signal.  
         [0063]     The first latch signal Q 1  is inputted into the first flip-flop of the lock discriminating section  30 , and the reference signal is provided to the first flip-flop as a clock. Therefore, the data of the first latch signal Q 1  is read. As a result, the first lock discriminating signal Q 5  is generated. The Q 4  signal is inputted into the second flip-flop of the lock discriminating section  30 , and the fourth delay signal D 4  is provided to the second flip-flop of the lock discriminating section  30  as clock. Therefore, the data of the Q 4  signal is read at T 3 −t 4 . As a result, the second lock discriminating signal Q 6  is generated.  
         [0064]     The first and second lock discriminating signals Q 5  and Q 6  are inputted into the NAND gate. As a result, the reset signal RS is generated. When each of the first and second lock discriminating signals Q 5  and Q 6  has high logic, the logic of the reset signal RS is low. The reset signal RS resets the latches and the flip-flops. Hence, the Q 1  signal, the Q 2  signal, the Q 3  signal, the Q 4  signal, the first lock discriminating signal Q 5  and the second lock discriminating signal Q 6  are reversed as shown in  FIG. 7 . When the reversed first lock discriminating signal is compared with the reversed second lock discriminating signal, time difference corresponding to t 5  is generated. Therefore, the DLL changes delay time corresponding to the t 5 . In detail, the delay time corresponding to t 5  ought to be augmented.  
         [0065]      FIG. 9  is a timing diagram illustrating operation of the phase detector according to an embodiment of the invention.  
         [0066]     As shown in  FIG. 9 , the delay time of the first delay signal D 1  is T/4+t 1 . The delay time of the second delay signal D 2  is 2 T/4+t 2 . The delay time of the third delay signal D 3  is 3 T/4+t 3 . The delay time of the fourth delay signal D 4  is T+t 4 .  
         [0067]     Now referring to  FIG. 3 , the first latch signal corresponds to a Q 1  signal in  FIG. 7 . The logic of the reference is converted from low into high at T 4 . Because the logic of the input signal is high, the data of the input signal is read at T 4 . As a result, the Q 1  signal is generated. The second latch section  120  of the invention includes latches coupled in series to each other. The first latch of the second latch section  120  receives the Q 1  signal and the first delay signal D 1 . Therefore, the data of the Q 1  signal is read at T 1 +t 1 , and so the first latch generates a Q 2  signal. The second latch of the second latch section  120  receives the Q 2  signal and the second delay signal D 2 . Therefore, the data of the Q 2  signal is read at T 3 +t 2 , and so the second latch generates a Q 3  signal. The third latch receives the Q 3  signal and the third delay signal D 3 . Hence, the Q 3  signal is read at T 7 +t 3 . As a result, the third latch generates a Q 4  signal.  
         [0068]     The first latch signal Q 1  is inputted into the first flip-flop of the lock discriminating section  30 , and the reference signal is provided to the first flip-flop as a clock. Therefore, the data of the first latch signal Q 1  is read. As a result, the first flip-flop generates the first lock discriminating signal Q 5 . The Q 4  signal is inputted into the second flip-flop. The fourth delay signal D 4  is provided to the second flip-flop as clock. Therefore, the data of the Q 4  signal is read at T 9 +t 4 . As a result, the second flip-flop generates the second lock discriminating signal Q 6 .  
         [0069]     The first and second lock discriminating signals Q 5  and Q 6  are inputted into the NAND gate. As a result, the reset signal RS is generated. When each of the first and second lock discriminating signals Q 5  and Q 6  has high logic, the logic of the reset signal RS is low. The reset signal RS resets the latches and the flip-flops. Hence, the Q 1  signal, the Q 2  signal, the Q 3  signal, the Q 4  signal, the first lock discriminating signal Q 5  and the second lock discriminating signal Q 6  are reversed as shown in  FIG. 7 . When the reversed first lock discriminating signal is compared with the reversed second lock discriminating signal, time difference corresponding to T+t 5  is generated. The phase detector of the invention discriminates between T+t 5  and t 5 . Therefore, the DLL employing the phase detector does not stop operation after reducing delay time by t 5 , and stop operation after reducing delay time by T+t 5 . Hence, the DLL employing the phase detector locks exactly without the false lock.  
         [0070]      FIG. 10  is a flow chart illustrating operation of the DLL using the phase detector of the invention.  
         [0071]     Referring to  FIG. 10 , in step S 100 , the input signal having high logic is provided. In step S 120 , the delay signals having predetermined phase difference in sequence from the reference is provided. In step S 140 , the input signal is latched to the delay signals so that the first and second latch signals are generated. In step S 160 , the first and second latch signals are passed through the flip-flops so that the first and second lock discriminating signals are generated. In step S 180 , when the first and second lock discriminating signals are reversed, it is determined whether or not the reversed first lock discriminating signal is substantially identical to the reversed second lock discriminating signal.  
         [0072]     In step S 200 , when the reversed first lock discriminating signal is substantially identical to the reversed second lock discriminating signal, operation of detecting the phase is finished. Whereas, when the reversed first lock discriminating signal is not identical to the reversed second lock discriminating signal, it is determined whether or not the delay time of the reversed first lock discriminating signal is larger than that of the reversed second lock discriminating signal.  
         [0073]     In step S 220 , when the delay time of the first lock discriminating signal is longer than that of the reversed second lock discriminating signal, the reset signal is provided. In step S 240 , the delay of the delay signals is reduced. In step S 260 , when the delay time of the first lock discriminating signal is shorter than that of the reversed second lock discriminating signal, the reset signal is provided. In step S 280 , the delay of the delay signals is increased. The changed delay signals are provided.  
         [0074]     Referring to  FIG. 11 , according to the phase detector of the present invention, it can be understood that improvement on speed may be accomplished by constructing the false lock protecting section  10  with latch substituted for flip-flop. Namely, at ½ level of a rising edge of clock signal CLK, a latch output signal LTQ passes almost ½ level of a rising edge thereof simultaneously with the clock signal CLK. However, a flip-flop output signal FFQ does not pass ½ level of a rising edge thereof.  
         [0075]     Accordingly, in a chain structure in which N of flip-flops connected are connected in serial to each other, each unit delay time of flip-flops is accumulated so that the total delay time is greatly increased, namely N times as large as unit delay time. So, in comparison with the chain of N flip-flops, the total operation speed may be greatly fast in the latch according to the present invention.  
         [0076]     While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the appended claims.