Abstract:
A stack structure of carrier boards embedded with semiconductor components and a method for fabricating the same are proposed. A first carrier board and a second carrier board, each of which having at least one through hole, are provided. A first protecting layer and a second protecting layer are formed on a surface of the first and second carrier boards respectively. At least one first semiconductor component and at least one second semiconductor component are disposed on the first and second protecting layers and accommodated in the first and second through holes respectively. A dielectric layer is laminated between the surfaces of the first and second carrier boards without the protecting layers formed thereon. Thus, a modularized package structure with reduced space waste is formed.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     This invention relates to stack structures of carrier boards embedded with semiconductor components and methods for fabricating the same, and more particularly, to a stack structure having the semiconductor components be embedded in the carrier boards and having the carrier boards be stacked on each other, and a method for fabricating the same.  
         [0003]     2. Description of Related Art  
         [0004]     With the development of electronic technologies, electronic devices are designed to have multiple functions and to be of high performance, so as to satisfy the requirements of high integration and miniaturization of semiconductor packages. A conventional semiconductor package is brought to the market in the form of a multi chip module (MCM). Such a package has a reduced package size and better electrical performances, and is becoming one of the main-streamed products in electronic industry. The package comprises a chip supporting member and at least two semiconductor chips, both of which are installed on the chip supporting member and are stacked on each other. Such a package has been disclosed in U.S. Pat. No. 6,798,049.  
         [0005]      FIG. 1  is a cross sectional view of a cavity-down ball grid array (CDBGA) disclosed in U.S. Pat. No. 6,798,049. The CDBGA forms an hole  101  on a circuit board  10  having a circuit layer  11 , and the circuit layer  11  on a surface of the circuit board  10  and having an electrical connection pad  11   a  and a solder wire pad  11   b,  and accommodating in the hole  101  two stacked semiconductor chips  121  and  122  electrically to each other via a soldering layer  13  (bounding layer). The semiconductor chip  122  is electrically connected via a conductive device  14  such as golden wire to the solder wire pad  11   b  of the circuit layer  11 . A package colloid  15  is formed in the hole  101  of the circuit board  10 , and covered on the semiconductor chips  121  and  122  and the conductive device  14 . An insulating protecting layer  16  is formed on the circuit layer  11  of the circuit board. A plurality of openings  16   a  are formed on the insulating protecting layer  16  for the electrical connection pads  11   a  to be exposed through. The conductive components  17  such as the solder balls are formed in the openings  16  of the insulating protecting layer  16 , so as to complete a package process.  
         [0006]     However, the stacked semiconductor chips  121  and  122  are electrically connected to the circuit layer  11  in a wire-bonding manner. Such the wire-bonding manner increases the height of the package due to the height of arc wires adopted by the wire-bonding manner. Therefore, the package has a big bulk and is contradictory to an objective of compactness. Moreover, the package has to adopt the soldering layer  13  to electrically connect the semiconductor chips  121  and  122 . That is, before the semiconductor chips  121  and  122  being transferred to a package factory for a package process, a stack connection process has to be performed on the semiconductor chips  121  and  122  in a chip factory. Therefore, the process to manufacture the package is quite complicated.  
         [0007]     Moreover, in order to have better electric and modularized functionalities, the package has to have more stacked layers, this complicating the circuit layer  11  and increasing a number of the solder wire pads  11   b  of the circuit layer  11 . In order to install more solder wire pads  11   b  in a limited or constant area, a circuit board for supporting the semiconductor chips  121  and  122  has to have a thin enough circuit layout. However, installing the thin circuit layout on the circuit board has less effect on the reduction of area of the circuit board. Moreover, only a finite number of semiconductor chips  121  and  122  can be stacked on the circuit board, so the package still does not have satisfied electric functionalities.  
         [0008]     Therefore, how to increase the density of the multiple-chip modularized package on a multi-layer circuit board and decrease the area occupied by the semiconductor components on the multi-layer circuit board, thereby decreasing the capacity of the semiconductor package, simplifying the semiconductor package process and reducing the manufacture cost, is becoming one of the most important issues in the art.  
       SUMMARY OF THE INVENTION  
       [0009]     In views of the above-mentioned problems of the prior art, it is a primary objective of the present invention to provide a stack structure of carrier boards embedded with semiconductor components and a method for fabricating the same for embedding semiconductor components into carrier boards to form a modularized structure.  
         [0010]     It is another objective of the present invention to provide a stack structure of carrier boards embedded with semiconductor components and a method for fabricating the same having a better combination alteration for in accordance with a number of the embedded semiconductor components.  
         [0011]     It is a further objective of the present invention to provide a stack structure of carrier boards embedded with semiconductor components and a method for fabricating the same taking the base usage of the space of the carrier boards to minimize the capacity of the modularized structure.  
         [0012]     It is still another objective of the present invention to provide a stack structure of carrier boards embedded with semiconductor components and a method for fabricating the same for simplifying a semiconductor process and reducing a manufacture cost.  
         [0013]     To achieve the above-mentioned and other objectives, a stack structure of carrier boards embedded with semiconductor components and a method for fabricating the same are provided according to the present invention. The method includes providing a first carrier board and a second carrier board, forming in each of the first and second carrier boards at least one through hole, forming on a surface of the first carrier board a first protecting layer for sealing the through hole of the first carrier board and forming on a surface of the second carrier board a second protecting layer for sealing the through hole of the second carrier board, accommodating a first semiconductor component and a second semiconductor component into the through holes of the first and second carrier boards respectively, the first and second semiconductor components being installed on the first and second protecting layers, laminating a dielectric layer between another surfaces of the first and second carrier boards, both of the another surfaces being surfaces without any protecting layer, to fill part of the dielectric layer in the through holes of the first and second carrier boards to fix the first and second semiconductor components to the through holes, and removing the first and second protecting layers, so as to form a package structure embedded with the first and second semiconductor components.  
         [0014]     Each of the first and second carrier boardscan be one selected from the group consisting of an insulating board and a circuit board having a circuit layout. Each of the first and second protecting layerscan be a tape.  
         [0015]     The method further includes forming on two surfaces of the package structure a first circuit build-up structure and a second circuit build-up structure, each of which comprises a dielectric layer, a circuit layer stacked on the dielectric layer, and a conductive structure formed in the dielectric layer for electrically connecting the circuit layer to the electrode pads of the first and second semiconductor components. The method further includes forming a plurality of electroplated through holes penetrating the package structure and the first and second circuit build-up structures, wherein the electroplated through holes electrically connect the first and second circuit build-up structures.  
         [0016]     According to the above-mentioned method, the stack structure of the present invention includes a first carrier board and a second carrier board, each of the carrier boards having at least one through hole; a first semiconductor component and a second semiconductor component installed in the through holes of the first and second carrier boards respectively; and a dielectric layer formed between the first and second carrier boards and filled in the through holes of the first and second carrier boards for fixing the first and second semiconductor components to the through holes.  
         [0017]     The stack structure further includes a first circuit build-up structure and a second circuit build-up structure formed on outermost surfaces of the first and second carrier boards, each of the first and second circuit build-up structures comprising a dielectric layer, a circuit layer stacked on the dielectric layer, and a conductive structure formed in the dielectric layer for electrically connecting the circuit layer to the electrode pads of the semiconductor components. The stack structure further includes a plurality of electroplated through holes penetrating the first and second carrier boards, the first and second circuit build-up structures and the dielectric layer, wherein the electroplated through holes electrically connect the circuit layers of the first and second circuit build-up structures.  
         [0018]     In contrast to the prior art, the present invention embeds the semiconductor components in the carrier boards, forming protecting layers on surfaces of the carrier boards and on active surfaces of the semiconductor components, and laminating a dielectric layer between another surfaces of the carrier boards, both of the another surfaces are surfaces without any protecting layer, so as to form a modularized structure, which takes the best usage of the space of the carrier boards and has a small capacity. Moreover, the modularized structure can have different combination and alteration in accordance with varieties of demands. Compared with the prior art, the stack structure of carrier boards embedded with semiconductor components and the method for fabricating the same has the capability to simplify a semiconductor package process and reduce the manufacture cost. Moreover, the present invention further forms on surfaces of the carrier boards the first and the second circuit build-up structure and a plurality of electroplated through holes for electrically connecting the first and second circuit build-up structures, so as to form a stack structure of carrier boards embedded with semiconductor components. The stack structure can be electrically connected to other conductive components or external electronic devices such as a printed circuit board. 
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0019]     The invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:  
         [0020]      FIG. 1  is a cross sectional view of a cavity-down ball grid array (CDBGA) disclosed in U.S. Pat. No. 6,798,049; and  
         [0021]      FIG. 2A  to  FIG. 2F  are six cross sectional views of a stack structure of carrier boards embedded with semiconductor components of the preferred embodiment according to the present invention. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0022]     The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparently understood by those in the art after reading the disclosure of this specification. The present invention can also be performed or applied by other different embodiments. The details of the specification may be on the basis of different points and applications, and numerous modifications and variations can be devised without departing from the spirit of the present invention.  
         [0023]      FIG. 2A  through  FIG. 2F  are used to illustrate collectively a stack structure of carrier boards embedded with semiconductor components and a method for fabricating the same.  
         [0024]     Please refer to  FIG. 2A . The method forms a first through hole  211   a  in a first carrier board  21   a,  a second though hole  211   b  in a second carrier board  21   b,  a first protecting layer  22   a  on a surface of the first carrier board  21   a  for sealing one end of the first through hole  211   a,  a second protecting layer  22   b  on a surface of the second carrier board  21   b  for sealing one end of the second through hole  211   b,  accommodating in the first through hole  211   a  and installing on the first protecting layer  22   a  a first semiconductor component  23   a,  and accommodating in the second through hole  211   b  and installing on the second protecting layer  22   b  a second semiconductor component  23   b.    
         [0025]     The first carrier board  21   a,  and the second carrier board  21   b  as well, is an insulating board or a circuit board having a circuit layout. The first protecting layer  22   a,  and the second protecting layer  22   b  as well, is a tape. The tape is used to adhere the first semiconductor component  23   a  (the second semiconductor component  23   b ) to the first through hole  211   a  of the first carrier board  21   a  (the second through hole  211   b  of the second carrier board  21   b ). The first semiconductor component  23   a  comprises an active surface  231   a  has a plurality of electrode pads  233   a,  an inactive surface  232   a  opposite to the active surface  231   a,  and is installed on the first protecting layer  22   a  with the active surface  231   a.  The first protecting layer  22   a  is used to protect the active surface  231   a  of the first semiconductor component  23   a  during a compression process, which will be described in the following paragraphs. The second semiconductor component  23   b  comprises an active surface  231   b  has a plurality of electrode pads  233   b,  an inactive surface  232   b  opposite to the active surface  231   b,  and is installed on the second protecting layer  22   b  with the active surface  231   b.  The second protecting layer  22   b  is used to protect the active surface  231   b  of the second semiconductor component  23   b  during the compression process.  
         [0026]     Please refer to  FIG. 2B . Another surface of the first carrier board  21   a  and another surface of the second carrier board  21   b,  both of the another surfaces being a surface without any protecting layers, are compressed toward directions indicated by two arrows to form a dielectric layer  24 , so as to form a structure shown in  FIG. 2C . In  FIG. 2C , part of the dielectric layer  24  is filled in the through holes  211   a  and  211   b,  and the first and second semiconductor components  23   a  and  23   b  are fixed to the through holes  211   a  and  211   b  respectively.  
         [0027]     Please refer to  FIG. 2D . Both of the first and second protecting layers  22   a  and  22   b  are removed, so as to form a package structure  2  embedded with the first and second semiconductor components  23   a  and  23   b.    
         [0028]     Please refer to  FIG. 2E . A first circuit build-up structure  25   a  and a second circuit build-up structure  25   b  are formed on two surfaces of the package structure  2  respectively. The first circuit build-up structure  25   a  comprises a dielectric layer  251   a,  a circuit layer  252   a  stacked on the dielectric layer  251   a,  and a conductive structure  253   a  formed in the dielectric layer  251   a  for the circuit layer  252   a  to be electrically connected to the electrode pads  233   a  of the first semiconductor component  23   a.  The second circuit build-up structure  25   b  comprises a dielectric layer  251   b,  a circuit layer  252   b  stacked on the dielectric layer  251   b,  and a conductive structure  253   b  formed in the dielectric layer  251   b  for the circuit layer  252   b  to be electrically connected to the electrode pads  233   b  of the second semiconductor component  23   b.  A plurality of electroplated through hole (PTH) 26  are formed to penetrate the package structure  2 , the first circuit build-up structure  25   a  and the second circuit build-up structure  25   b,  to electrically connect the circuit layers circuit layer  252   a  and  252   b.    
         [0029]     Moreover, it should be noted that the first circuit build-up structure  25   a,  and the second circuit build-up structure  25   b  as well, is allowed to comprise more than one layer, unlike that shown in figure, to satisfy the practical demands.  
         [0030]     Please refer to  FIG. 2F . A first solder mask layer  27   a  is formed on an outermost surface of the first circuit build-up structure  25   a,  and a second solder mask layer  27   b  is formed in an outermost surface of the second circuit build-up structure  25   b.    
         [0031]     According to the method described previously, a stack structure of carrier boards embedded with semiconductor components is shown in  FIG. 2C  and  FIG. 2D . The stack structure comprises a first carrier board  21   a  and a second carrier board  21   b.  Two through holes  211   a  and  211   b  are formed in the first and second carrier boards  21   a  and  21   b  respectively. The first semiconductor component  23   a  and the second semiconductor component  23   b  are accommodated in the through holes  211   a  and  211   b  of the first and second carrier boards  21   a  and  21   b  respectively. The first and second semiconductor components  23   a  and  23   b  have the active surfaces  231   a  and  231   b  having the electrode pads  233   a  and  233   b  respectively, and the inactive surfaces  232   a  and  232   b,  which are opposite to the active surfaces  231   a  and  231   b  respectively. The stack structure further comprises the dielectric layer  24 , which is laminated between the first carrier board  21   a  and the second carrier board  21   b  and filled in the through holes  211   a  and  211   b  of the first and second carrier boards  21   a  and  21   b  for fixing the first and second semiconductor components  23   a  and  23   b  to the through holes  211   a  and  211   b  respectively.  
         [0032]     The above-mentioned stack structure, as shown in  FIG. 2E , further comprises the first circuit build-up structure  25   a  and the second circuit build-up structure  25   b  formed on the outermost surfaces of the first and second carrier board  21   a  and  21   b  respectively. The first and second circuit build-up structure  25   a  and  25   b  comprises the dielectric layers  251   a  and  251   b,  the circuit layers  252   a  and  252   b  stacked on the dielectric layers  251   a  and  251   b  respectively, and the conductive structures  253   a  and  253   b  formed in the dielectric layers  251   a  and  251   b  respectively for the circuit layers  252   a  and  252   b  to be electrically connected to the electrode pads  233   a  and  233   b  of the first and second semiconductor components  23   a  and  23   b  respectively. The stack structure further comprises the electroplated through holes  26  penetrating the first and second carrier boards  21   a  and  21   b,  the first and second circuit build-up structures  25   a  and  25   b  and the dielectric layers  24 , and electrically connected to the circuit layers  252   a  and  252   b.    
         [0033]     Additionally, as shown in  FIG. 2F , the stack structure further comprises the first and second solder mask layers  27   a  and  27   b  formed on the outermost surfaces of the first and second circuit build-up structures  25   a  and  25   b.    
         [0034]     In contrast to the prior art, the present invention embeds a plurality of semiconductor components in the first and second carrier boards  21   a  and  21   b,  so as to increase a number of carrier boards on which the semiconductor components are installed, and increase the storage capacity. Moreover, the first and second semiconductor components  23   a  and  23   b  are pre-installed in the through holes  211   a  and  211   b  of the first and second carrier boards  21   a  and  21   b.  Further, the first and second protecting layers  22   a  and  22   b  are formed on the surfaces of the first and second carrier board  21   a  and  21   b  and the active surfaces of the first and second semiconductor component  23   a  and  23   b,  and the first carrier board  21   a  is stacked on the second carrier board  21   b,  so as to form a modularized structure, which takes the best usage of the space of the carrier boards and has a small capacity. Moreover, the modularized structure can have different combination and alteration in accordance with varieties of demands. Compared with the prior art, the stack structure of carrier boards embedded with semiconductor components and the method for fabricating the same has the capability to simplify a semiconductor package process and reduce the manufacture cost.  
         [0035]     The foregoing descriptions of the detailed embodiments are only illustrated to disclose the features and functions of the present invention and not restrictive of the scope of the present invention. It should be understood to those in the art that all modifications and variations according to the spirit and principle in the disclosure of the present invention should fall within the scope of the appended claims.