Abstract:
A switched- capacitor summer  400  includes an operational amplifier  206  having an input and an output, first and second parallel capacitors  307, 401 , first switching circuitry  308, 404  and second switching circuitry  402, 403 . First switching circuitry  308, 404  discharges first capacitor  307  during a first timing phase and couples second capacitor  401  between the input and the output of operational amplifier  306  during a first timing phase. Second switching circuitry  402, 403  couples a first capacitor  307  between the input and output of operational amplifier  306  during the second phase to transfer charge from capacitor C S  to capacitor  307  and charge up capacitor C H  during the second phase.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application for patent is related to the following applications for patent: 
     Pending U.S. patent application Ser. No. 09/904,649, filed Jul. 12, 2001 by inventor Yu Qing YANG, entitled “SWITCHED-CAPACITOR CIRCUITS AND METHODS WITH IMPROVED SETTLING TIME AND SYSTEMS USING THE SAME”; and 
     Pending U.S. patent application Preliminary Ser. No. 09/870,900 , filed May 30, 2001 by inventor Yu Qing YANG and entitled “SWITCHED-CAPACITOR SUMMER CIRCUITS AND METHODS AND SYSTEMS USING THE SAME”. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates in general to switched-capacitor techniques and in particular to switched-capacitor summer circuits and methods and systems using the same. 
     2. Description of the Related Art 
     Delta-sigma modulators are particularly useful in digital to analog and analog to digital converters (DACs and ADCs). Using oversampling, the delta-sigma modulator spreads the quantization noise power across the oversampling frequency band, which typically much greater than the input signal bandwidth. Additionally, the delta sigma modulator performs noise shaping by acting as a lowpass filter to the input signal and a highpass filter to the noise; most of the quantization noise power is thereby shifted out of the signal band. 
     The typical delta sigma modulator includes a summer summing the input signal with negative feedback, a linear filter, quantizer and a feedback loop with a digital to analog converter coupling the quantizer output and the inverting input of the summer. In a first order modulator, the linear filter comprises a single integrator stage while the filter in higher a order modulator comprises a cascade of a corresponding number of integrator stages. The quantizer can be either a one-bit or a multiple-bit quantizer. 
     In the case of a higher-order multiple-bit modulator with weighted feed-forward summation, the outputs of the integrator stages are passed to a summation circuit. This summation circuitry does not have a “memory.” In other words, this circuitry must be reset to zero after each summation operation, even though the integrator outputs typical only increment up or down in voltage by a small amount with each new sample. Consequently, the summation circuitry must handle relatively large voltage swings, especially when the integrator outputs approach their maximum values. Moreover, when the summation circuitry includes an operational amplifier, a large tail current is required to achieve a sufficiently large output slew rate. 
     SUMMARY OF THE INVENTION 
     The principles of the present invention and embodied in switched-capacitor summation techniques. According to one such embodiment, a switched-capacitor summer is disclosed which includes an operational amplifier having an input and an output, first and second parallel capacitors, and first switching circuitry. The first switching circuit discharges the first capacitor during a first timing phase and couples the first capacitor between the input and the output of operational amplifier during a second timing phase. The second switching circuit couples the second capacitor between the input and output of operational amplifier during the first phase to maintain a voltage at the operational amplifier output and charges the second capacitor during the second phase. 
     The principles of the present invention allow for the construction and operation of summation circuits which are faster and consume less power. In particular, according to the inventive concepts, hold up capacitors and associated switching circuitry are provided such that the summer output voltage can be maintained while the conventional feedback capacitors are reset after each summation operation. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
     FIG. 1A is a high level functional block diagram of an analog to digital converter suitable for illustrating the application of the inventive principles; 
     FIG. 1B is a high level functional block diagram of a digital radio demonstrating a use of the analog to digital converter of FIG. 1A; 
     FIG. 2 is a functional block diagram of an exemplary 5 th  order delta-sigma modulator suitable for use in circuits and systems such as the analog to digital converter shown in FIG. 1A; 
     FIG. 3A is an electrical schematic diagram of a conventional switched-capacitor summer circuit; 
     FIG. 3B is an electrical schematic diagram of a flash A/D converter suitable for use as the multi-bit quantizer of FIG. 3A; 
     FIGS. 3C and 3D are diagrams respectively illustrating the typical outputs from single-bit and multiple-bit quantizers; 
     FIG. 4A is an electrical schematic diagram of a first switched-capacitor summer according to the inventive principles; and 
     FIG. 4B is an electrical schematic diagram of a second switched-capacitor summer according to the inventive principles. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The principles of the present invention and their advantages are best understood by referring to the illustrated embodiment depicted in FIGS. 1-4B of the drawings, in which like numbers designate like parts. 
     FIG. 1A is a high level functional block diagram of a single-chip audio analog-to-digital (A/D)  100  suitable for practicing the principles of the present invention. A/D converter  100  is only one of a number of possible applications requiring switched-capacitor integrator and summer stages. Other examples include digital to analog converters (DACs) and Codecs. 
     A/D converter  100  includes two conversion paths for converting left and right channel analog audio data respectively received at left and right analog differential inputs AINL+/− and AINR+/−. The analog inputs are each passed through an input gain stage  101  and then to a 5th order delta-sigma modulator. 
     Each delta-sigma modulator is represented in FIG. 1 by a summer  102 , low-pass filter  104 , comparator (quantizer)  105  and DAC  106  in the feedback loop. The outputs from the delta-sigma modulators are passed through a decimation filter  107  and a high pass filter  108 . 
     The resulting left and right channel digital audio data are output through a single serial port SDOUT of serial output interface  109 , timed with serial clock SCLK and left-right clock LRCLK in accordance with the Digital Interface Format (DIF). The SCLK and LRCLK clocks can be generated externally and input to converter  100  or can be generated on-chip, along with the associated data, in response to a received master clock MCLK. 
     One possible application of A/D converter is in a digital radio  110 , such as that shown in FIG.  1 B. 
     Digital radio  110  includes an analog section or front-end  111  which receives radio frequency (RF) signals from an associated antenna  112 . Analog front-end  111  is preferably a conventional RF down-converter including a low noise amplifier (LNA)  113  for setting the system noise figure, a bandpass filter  114  and mixer  115  driven by an analog local oscillator  116 . The mixed-down analog signal is then converted into digital form by analog to digital converter  117 . 
     The digitized data output from A/D converter  117  is passed to digital processing section  118 . A pair of mixers  119   a,b  generate in-phase (I) and quadrature (Q) signals from a corresponding pair of clock phases from crystal oscillator  120 . The I and Q signals are next passed through bandpass filters  121   a  and  121   b  on to digital baseband processor  122 . The processed digital signal is then re-converted to analog (audio) form by D/A converter  123 . 
     A switched mode (Class D) audio power amplifier (APA)  124  is used to drive an external set of speakers or a headset. Preferably, at least some of the components of digital radio  110  are powered by a switched mode power supply (SMPS)  124   
     FIG. 2 is an exemplary 5th order delta-sigma modulator  200  comprising an input summer  201  and 5 integrator stages  202   a,e . Delta sigma modulator  200  is of a weighted feed-forward design in which the outputs of each of the integrator stages are passed through a gain stage (amplifier)  202   a,e  to summer  205 . The output from summer  205  is quantized by a multiple-bit quantizer  206  which provides the digital output signal. Additionally, the output from quantizer  206  is feedback to the inverting of summer  201  through digital to analog converter  207 . 
     FIG. 3A is an electrical schematic diagram of a conventional switched-capacitor fully-differential summing circuit  300 . During Phase 1 (φ1), input nodes A and A′, sampling nodes B and B′, and output nodes C and C′ are brought to the common mode voltage V CM  by switches  302   a,b ,  304   a,b  and  309   a,b , respectively. Additionally, integrator capacitors (C I )  307   a,b  are discharged by switches  308   a,b.    
     During Phase 2 (φ 2 ), the differential integrator outputs are sampled by switches  301  onto sampling capacitors (C S )  303   a,b . Switches  305   a,b  transfer the charge to the summing nodes of operational amplifier  306  and integrator capacitors C I . Operational amplifier  306  drives multi-bit quantizer  206 . 
     Multiple-bit quantizer  206 , could be for example, a Flash A/D converter such as shown in FIG.  3 B. Flash A/D converter  310  is based on a series of parallel opamp comparators  311  comparing the differential summer output against a set of voltages generated by a ladder of resistors  312  from a reference voltage. 
     As shown in FIGS. 3C and 3D, the advantage of a multiple-bit quantizer is its ability to more closely represent the analog input voltage. Specifically, FIG. 3C shows the feedback voltage at the negative input to input summer  201  from DAC  207  when a single-bit quantizer is used. In this case, the feedback voltage for a given sample is represented by one of only two levels. On the other hand, for a multiple-bit quantizer, as illustrated in FIG. 3D, the feedback voltage is represented by a corresponding multiple of possible voltage levels and hence more closely approximates the signal voltage. 
     Multiple-bit quantizer  206  presents a significantly large capacitive load at the output of summer  205 . The primary source of this capacitive loading is the capacitance of the input gate transistors of comparators  311 . Since the nodes of summer  300  are discharged (“reset”) during Phase 1, during Phase 2, summer  300  must drive this capacitive loading from zero voltages to the voltage level representing the current sample. 
     FIG. 4 is an electrical schematic of a switched-capacitor summer—gain stage  400  according to the present inventive teachings and suitable for use, in one application, as summer  205  in delta sigma modulator  200 . 
     For each of the differential feedback paths summer—gain stage  200 , a set of hold-up capacitors (C H )  401   a,b  are provided in parallel with integration capacitors C I . A switch  402   a,b  is associated with each capacitor C H  for selectively coupling one plate to the common mode voltage V CM  during Phase 2 while a switch  404   a,b  couples that plate with the corresponding opamp summing node during Phase 1. The opposing plates of capacitors C H  are coupled to the corresponding outputs of opamp  306 . The integration capacitors C I  are selectively coupled with the corresponding outputs of opamp  306  by switches  403   a,b  during Phase 2. 
     Summer  400  operates as follows. During Phase 1, switches  302   a,b  and  304   a,b  close to discharge sampling capacitors C S  as discussed above. Additionally, switches  308   a,b  and  404   a,b  close. In this configuration, integrator capacitors C I  are discharged. At the same time, hold-up capacitors C H  hold up the output nodes C and C′ at the voltage charged thereon during the last Phase 2 cycle. 
     On the next Phase 2 cycle, switches  404   a,b  disconnect the left side plates of hold-up capacitors C H  from the op am summing nodes while switches  402   a,b  connect those plates to the common mode voltage V CM . The right side plates of hold up capacitors C H  then charge to the output voltage. Hold-up capacitors C H  have now been charged in preparation to hold-up the output nodes C and C′ on the next Phase 1 cycle. At the same time, switches  305   a,b  and  403   a,b  close such that the charge on sampling capacitors C S  is transferred onto integrator capacitors C I . 
     Consequently, the hold-up capacitors C H  are able to maintain the opamp output nodes C and C′ at a non-zero voltage such that the voltage swing and driving current required of opamp  306  is substantially reduced. A substantial amount of power is saved and the circuit response is faster. Notwithstanding, since integrator capacitors C I  are reset during each Phase 1, “memory” caused by the accumulation of charge on integrator capacitors C I  is avoided. 
     It should be noted that hold-up capacitors C I  can be relatively small. A simplified summation circuit  400  according to the inventive concepts is depicted in FIG.  4 B. In this embodiment, the parasitic capacitance at the inputs to quantizer  206  are allowed to hold the previous output voltage during Phase 1. During Phase 2, switches  406  close and the voltage at the quantizer input swings from the Phase 1 voltage. Although the output of operational amplifier  306  must drive a large voltage swing, the quantizer input capacitance does not need to be charged across that large voltage swing. This still results in a substantial power savings over the conventional circuit of FIG.  3 A. 
     Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.