Abstract:
An apparatus for testing a semiconductor device is disclosed. According to the present invention, the apparatus includes a pair of input pins, a first conductive wire, a second conductive wire, a driver and a terminator. A device-under-test (DUT) is connected to one of the pair of input pins. The first conductive wire and the second conductive wire are connected in parallel between the pair of input pins. The driver is coupled to the first conductive wire via a third conductive wire, and the terminator is coupled to the second conductive wire via a fourth conductive wire.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     (a) Field of the Invention  
         [0002]     The invention relates to an apparatus and a method for testing a high-speed semiconductor device.  
         [0003]     (b) Description of the Prior Art  
         [0004]     Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) is a memory technique developed based upon SDRAM. Unlike SDRAM that is capable of only supporting one data operation during each clock period, DDR SDRAM has capability of executing two data operations during each clock period. Therefore, not only bandwidth of memory is doubled but also data transmission capacity is multiplied. For the aforesaid advantage, DDR SDRAM is extensively applied in computer system platforms including personal computers, workstations, servers, laptop computers, portable devices, computer networks, and communication products, and consequently stands as a mainstream product in memory techniques. Along with technique advancement, data rate of DDR SDRAM has increased from 200/266 MHz to 533/667 MHz, and can promisingly be further increased to 800 MHz/1.066 GHz. It is to be noted that frequency upgrading is also an arduous challenge for testing techniques.  
         [0005]     Referring to  FIG. 1  showing a test system  1  applied in DDR SDRAM, the test system  1  comprises a tester  10  that may be an Advantest  5592 / 5593  tester manufactured by Advantest Corporation and is mainly for generating test patterns. The tester  10  is divided into several stations, and has two stations  12  and  14  supposed an Advantest  5592 / 5593  tester is adopted. The stations  12  and  14  are connected to respective test fixtures  16  and  18  as shown in  FIG. 1 .  
         [0006]     Referring to  FIG. 2  showing a schematic view of the test fixture  16 , the test fixture  16  has a test head  20 , a common motherboard  22  and a socket board  24 . The test head  20  is devised with elements including a driver and a comparator therein for driving and comparing signals. The common motherboard  22  has a coaxial cable therein for connecting the common motherboard  22  to the socket board  24 . The socket board  24  has a socket board printed circuit board (PCB) and a socket connector for fastening an integrated circuit (IC). The device-under-test (DUT) is inserted to the socket board  24 . To simplify illustrations, only two DUTs  26 A and  26 B are shown in  FIG. 2 . In practical, supposed an Advantest  5592 / 5593  tester is used, a number of DUTs may be 64 or even 128. For that  FIG. 2  serves for illustration purposes only, the test head  20  is electrically coupled to the common motherboard  22 , and the common motherboard  22  is electrically coupled to the socket board  24 .  
         [0007]     Pins of each of the DUTs  26 A and  26 B are generally divided into input pins and input/output (I/O) pins. Referring to  FIG. 3  showing a circuit schematic diagram of a conventional test apparatus  3  applied to an input pin. The conventional test apparatus  3  applied to an input pin is disposed in the test fixture  16  shown in  FIG. 2 . The test apparatus  3  comprises a driver  30  connected to one input end of the DUT  26 A through a pin  32 A whereas another pin  32 B is connected to one input end of the DUT  26 B. In other words, the DUTs  26 A and  26 B are both driven and controlled by the driver  30 .  
         [0008]     It is to be noted that I/O end of DDR SDRAM are differentiated in 4-bit, 8-bit and 16-bit. Connection configuration in  FIG. 3  is suitable for testing 4-bit I/O and 8-bit I/O DDR SDRAM but not 16-bit I/O DDR SDRAM. For 16-bit applications, it is necessary that the pin  32 B be left floating as shown in  FIG. 4 . To be more precise, the driver  30  is merely capable of corresponding to one DUT  26 A. At this point, impedance of the floating pin  32 B is rather great that apparent reflection of signals transmitted by the driver  30  is produced to affect accuracy of test results. Reflection becomes even more severe as signal frequencies get greater.  
         [0009]     Referring to  FIG. 5  showing a circuit schematic diagram of a prior test apparatus  5  applied to an I/O end. The prior test apparatus  5  applied to an I/O end is disposed in the test fixture  16  in  FIG. 2 . The test apparatus  5  comprises a driver  50 , a switch  51 , a resistor  52 , a voltage terminal  53 , a comparator  54 , a switch  55 , a resistor  56  and a voltage terminal  57 . An input of the driver  50  is for receiving a test pattern PAT, and an output end thereof is connected to the DUT  26 A via an I/O pin  59 A. In other words, the driver  50  is for merely corresponding to one DUT  26 A. The switch  51 , the resistor  52  and the voltage terminal  53  are connected in series between a driver enable signal (/DRE) and ground. The comparator  54  is connected to the I/O pin  59 A. When data are read from the I/O pin  59 A, the comparator  54  determines whether the data are at logic high or logic low. The switch  55 , the resistor  56  and the voltage terminal  57  are connected in series between the comparator  54  and ground. Under a write mode, the switches  51  and  55  are turned off through control of an OUTL signal, and the enable signal /DRE is at logic low for enabling the driver  50 , such that the output end of the driver outputs the test pattern signal PAT, with the enable signal /DRE simultaneously disabling the switch  58 . Under a read mode, the switches  51  and  55  are turned on through control of an OUTL signal, and the enable signal /DRE is at logic high for disabling the driver  50  and enabling the switch  58 , such that the resistor  52  and the voltage terminal  53  are coupled to the I/O pin  59 A. The read data whether being logic high or logic low is determined by the comparator  54 . Likewise, the test apparatus applied to the DUT  26 B operates in an identical or similar method as that disclosed in  FIG. 5 . To be more accurate, the DUTs  26 A and  26 B cannot share a same driver. There are test fixtures especially tailored for 16-bit DDR SDRAM, and these test fixtures are often purchased by users commonly being memory manufacturers or test houses. However, a complete set of test fixtures is considered quite resource uneconomical for that each costs at least millions of dollars.  
       SUMMARY OF THE INVENTION  
       [0010]     It is therefore an object of the invention to provide an apparatus and a method for testing a semiconductor device, in that a little modification is made to a prior test apparatus and the modified apparatus can then be applied for testing 4-bit, 8-bit and 16-bit I/O semiconductor devices, thereby reducing investment costs of apparatuses and equipments for memory manufacturers and test houses.  
         [0011]     To accomplish the aforesaid object, the invention provides a semiconductor device test apparatus for testing a DUT. A test apparatus according to the invention comprises a pair of input pins, with a DUT coupled to one of the input pins; a first conductive wire coupled between the pair of input pins; a second conductive wire coupled between the pair of input pins; a driver coupled to the first conductive wire via a third conductive wire; and a terminator coupled to the second conductive wire via a fourth conductive wire.  
         [0012]     The invention also provides a semiconductor device test apparatus for testing a DUT. A test apparatus according to the invention comprises a first I/O pin and a second I/O pin, with a DUT coupled to the first I/O pin; a bus having a plurality of conductive wires, with one of the conductive wires coupled between the first I/O pin and the second I/O pin; a driver coupled to the first I/O pin when under an input mode; a first terminator coupled to the first I/O pin when under an output mode; a comparator coupled to the second I/O pin; and a second terminal coupled to the second I/O pin when under an output mode. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]      FIG. 1  shows a schematic view of a test system  1  applied for DDR SDRAM;  
         [0014]      FIG. 2  shows a schematic view of a test fixture in  FIG. 1 ;  
         [0015]      FIG. 3  shows a circuit schematic diagram of a conventional test apparatus applied to an input end;  
         [0016]      FIG. 4  shows a pin in  FIG. 3  being left floating;  
         [0017]      FIG. 5  shows circuit schematic diagram of a conventional test apparatus applied to an I/O end;  
         [0018]      FIG. 6  shows a circuit schematic diagram of a test apparatus according to the invention applied to an input end;  
         [0019]      FIG. 7  shows a circuit schematic diagram of a test apparatus according to the invention applied to an I/O end;  
         [0020]      FIG. 8  shows a circuit schematic diagram of a test apparatus according to the invention applied to an input end;  
         [0021]      FIG. 9  shows a schematic view illustrating connection configurations of the DUTs in  FIGS. 7 and 8 ; and  
         [0022]      FIG. 10  shows a schematic view illustrating one of the DUTs in  FIG. 9  being removed. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0023]     To better understand technical contents of the invention, detailed descriptions of preferred embodiments shall be given with the accompanying drawings below.  
         [0024]     Referring to  FIG. 6  showing a circuit schematic diagram of a test apparatus  6  according to the invention applied to an input end, the test apparatus  6  applied to an input end is disposed in the test fixture  16  in  FIG. 2 . The test apparatus  6  comprises a driver  60 , a resistor  63  and a voltage terminal  64 . An input end of the driver  60  is for receiving a test pattern signal PAT, and an output end thereof is connected to a conductive wire  62  via a conductive wire  61 , with a connecting point of the conductive wires  61  and  62  forming a node  620 . The voltage terminal  64  is connected in series between the resistor  63  and ground. The resistor  63  is connected to a conductive wire  66  via a conductive wire  65 , with a connecting point of the conductive wires  65  and  66  forming a node  660 . The conductive wires  62  and  66  are connected in parallel between input pins  67 A and  67 B. The conductive wire  62  is distinguished into sub conductive wires  621  and  622  respectively connected to the input pins  67 A and  67 B. The conductive wire  66  is distinguished into sub conductive wires  661  and  662  also respectively connected to the input pins  67 A and  67 B. The pin  67 A is connected to a certain input end of the DUT  26 A, and the pin  67 B is connected to a certain input end of the DUT  26 B. In other words, the DUTs  26 A and  26 B are both driven and controlled by the driver  60 .  
         [0025]     Thus, although output ends of DDR SDRAM are differentiated as 4-bit, 8-bit and 16-bit, the input pins  67 A and  67 B are respectively inserted into the DUTs  26 A and  26 B when utilized for 4-bit or 8-bit applications; and the input pin  67 A or  67 B is left floating and the DUT  26 B is removed as in  FIG. 6  when utilized for 16-bit applications. In  FIG. 7 , the conductive wires  62  and  66  are connected in parallel and the voltage terminal  64  is provided, and therefore by appropriately adjusting impedance of the conductive wires  61  an  65  to match the resistance of a resistor  63  with internal resistance R of the driver  60 , reflection can be significantly reduced by leaving the input pin  67 B floating. Preferably, when the sub conductive wires  621  and  622  have approximately equal lengths while the sub conductive wires  661  and  662  also have approximately equal lengths, propagation delay time may be the same to reduce reflection. Hence, it is preferable that the sub conductive wires  621 ,  622 ,  661  and  662  have approximately equal lengths.  
         [0026]     Referring to  FIG. 7  shows a circuit schematic diagram of a test apparatus  7  according to the invention applied to an I/O end, the test apparatus  7  applied to an I/O end is disposed in the test fixture  16  shown in  FIG. 2 . The test apparatus  7  comprises a driver  70 , a switch  71 , a resistor  72 , a voltage terminal  73 , a comparator  74 , a switch  75 , a resistor  76  and a voltage terminal  77 . An input of the driver  70  is for receiving a test pattern PAT, and an output end thereof is connected to the DUT  26 A via an I/O pin  79 A. The switch  71 , the resistor  72  and the voltage terminal  73  are connected in series between a driver enable signal (/DRE) and ground. The comparator  74  is connected to the I/O pin  79 B. The switch  75 , the resistor  76  and the voltage terminal  77  are connected in series between the comparator  74  and ground. A conductive wire  911  is connected between the I/O pins  79 A and  79 B. Under a write mode, the switches  71  and  75  are turned off through control of an OUTL signal, and the enable signal /DRE is at logic low for enabling the driver  75 , such that the output end of the driver  70  outputs a test pattern signal PAT, with the enable signal /DRE simultaneously disabling the switch  78 . Under a read mode, the switches  71  and  75  are turned on through control of an OUTL signal, and the enable signal /DRE is at logic high for disabling the driver  70  and enabling the switch  78 , such that the resistor  72  and the voltage terminal  73  are coupled to the I/O pin  79 A and the resistor  76  and the voltage terminal  77  are coupled to the I/O pin  79 B. The read data whether being logic high or logic low is determined by the comparator  74 . According to the invention, the driver,  70 , the switch  71 , the resistor  72  and the voltage terminal  73  are all devised near a side of the I/O pin  79 A; and the comparator  74 , the switch  75 , the resistor  76  and the voltage terminal  77  are devised near a side of the pin  79 B. In  FIG. 7 , the DUT  26 B is represented in dotted lines to indicate that the I/O pin  79 B is no connection.  
         [0027]     Referring to  FIG. 8  showing a circuit schematic diagram of a test apparatus  8  according to the invention applied to an I/O end, the test apparatus  8  applied to an I/O end is disposed in the test fixture  16  shown in  FIG. 2 . The test apparatus  8  comprises a driver  80 , a switch  81 , a resistor  82 , a voltage terminal  83 , a comparator  84 , a switch  85 , a resistor  86  and a voltage terminal  87 . An input of the driver  80  is for receiving a test pattern PAT, and an output end thereof is connected to the DUT  26 B via an I/O pin  89 B. The switch  81 , the resistor  82  and the voltage terminal  83  are connected in series between the driver enable signal /DRE and ground. The comparator  84  is connected to the I/O pin  89 A. The switch  85 , the resistor  86  and the voltage terminal  87  are connected in series between an input end of the comparator  84  and ground. A conductive wire  921  is connected between the I/O pins  89 A and  89 B. Under a write mode, the switches  81  and  85  are turned off through control of an OUTL signal, and the enable signal /DRE is at logic low for enabling the driver  80 , such that the output end of the driver  80  outputs a test pattern signal PAT, with the enable signal DRE simultaneously disabling the switch  88 . Under a read mode, the switches  81  and  85  are turned on through control of an OUTL signal, and enable signal /DRE is at logic high for disabling the driver  80  and enabling the switch  88 , such that the resistor  82  and the voltage terminal  83  are coupled to the I/O pin  89 A and the resistor  86  and the voltage terminal  87  are coupled to the I/O pin  89 B. The read data whether being logic high or logic low is determined by the comparator  84 . According to the invention, the driver  80 , the switch  81 , the resistor  82  and the voltage terminal  83  are devised near a side of the I/O pin  89 A; and the comparator  84 , the switch  85 , the resistor  86  and the voltage terminal  87  are devised near a side of the I/O pin  89 B. In  FIG. 8 , the DUT  26 B is represented in dotted lines to indicate that the I/O pin  89 A is no connection.  
         [0028]     Referring to  FIG. 9  showing connection configurations of the DUTs  26 A and  26 B in  FIGS. 7 and 8 , a bus  91  is connected between I/O pins D[ 0 : 7 ] of the DUT  26 A and I/O pins D[ 8 : 15 ] of the DUT  26 B, and a bus  92  is connected between I/O pins D[ 8 : 15 ] of the DUT  26 A and I/O pins D[ 0 : 7 ] of the DUT  26 B. To illustrate in detail, I/O pins D 0 , D 1 , D 2 , D 3 , D 4 , D 5 , D 6  and D 7  of the DUT  26 A are respectively connected to I/O pins D 8 , D 9 , D 10 , D 11 , D 12 , D 13 , D 14  and D 15  of the DUT  26 B, and I/O pins D 8 , D 9 , D 10 , D 11 , D 12 , D 13 , D 14  and D 15  of the DUT  26 A are respectively connected to D 0 , D 1 , D 2 , D 3 , D 4 , D 5 , D 6  and D 7  of the DUT  26 B. For instance, the conductive wire  911  in  FIG. 7  is among the bus  91  and the pin D 0  of the DUT  26 A is connected to the pin D 8  of the DUT  26 B. Supposed the DUTs  26 A and  26 B are 4-bit or 8-bit, D[ 8 : 15 ] are not connected and therefore the DUT  26 B is represented in dofted lines in  FIG. 7 . Referring to  FIG. 8 , the conductive wire  921  in  FIG. 8  is among the bus  92  and the pin D 8  of the DUT  26 A is connected to the pin D 0  of the DUT  26 B. Supposed the DUTs  26 A and  26 B are 4-bit or 8-bit, D[ 8 : 15 ] are not connected and therefore the DUT  26 A is represented in dotted lines in  FIG. 8 .  
         [0029]     Referring to  FIG. 10 , when the DUTs  26 A and  26 B are 16-bit, D[ 8 : 15 ] are not no-connection pins, it is necessary that either the DUTs  26 A or  26 B be removed.  FIG. 10  shows the DUT  26 B removed for illustration.  
         [0030]     From the aforesaid description of the invention, although output end of DDR SDRAM are differentiated in 4-bit, 8-bit and 16-bit, the I/O pins  79 A/ 89 A and  79 B/ 89 B can be respectively inserted to the DUTs  26 A and  26 B when utilized for 4-bit or 8-bit applications as shown in  FIG. 9 ; and either the I/O pin  79 A/ 89 A or  79 B/ 89 B is left floating and the DUT  26 B is removed when utilized for 16-bit applications.  
         [0031]     It is of course to be understood that the embodiments described herein are merely illustrative of the principles of the invention and that a wide variety of modifications thereto may be effected by persons skilled in the art without departing from the spirit and scope of the invention as set forth in the following claims.