Abstract:
A self-testable digital integrator comprises binary adding apparatus and storage apparatus. The adding apparatus and the storage apparatus are functionally interconnected such that the storage apparatus feeds digital words to the adding apparatus for addition thereof and the adding apparatus feeds resulting digital words to the storage apparatus for storage thereof to perform a digital integration operation. The digital integrator further comprises a first combinational network responsive to a first state of a test mode signal to feed an external input signal to the adding apparatus for integration thereof, and responsive to a second state of the test mode signal to feed to the adding apparatus a test pattern signal derived from selected bias of the digital words fed from the adding apparatus to the storage apparatus. The digital integrator also comprises a second combinational network responsive to the second state of the test mode signal to feed back a carry-out bit of the adding apparatus to a carry-in port of the adding apparatus for test result compaction. The digital integrator optionally comprises a third combinational network responsive to the second state of the test mode signal to feed a carry-out bit of the adding apparatus to the first combinational network, the first combinational network being responsive to the second state of the test mode signal and to the carry-out bit to modify the test pattern signal. The self-testable digital integrator is particularly useful as a component of a digital decimator used to decimate Double Integration Sigma Delta modulation signals.

Description:
FIELD OF THE INVENTION 
     This invention relates to self-testable digital integrators and to self-test methods for digital integrators. 
     BACKGROUND OF THE INVENTION 
     Digital integrated circuits constructed according to conventional Built In Self Test (BIST) architectures comprise dedicated test circuitry in addition to operational circuitry required to perform functions expected of the integrated circuits in their intended applications. The dedicated test circuitry normally includes test pattern generators for generating test patterns, test response compactors for compressing results of test pattern application to the operational circuitry, and multiplexors used to switch between normal operating configurations and test configurations. The dedicated test circuitry can add a substantial hardware overhead, and introduction of the multiplexors into signal paths used during normal operation of the integrated circuits can degrade normal operation of the integrated circuits. 
     Some functional blocks of integrated circuits are difficult to test even using BIST techniques. For example, digital integrators of digital decimators used to band limit Sigma Delta Modulation (SDM) signals are difficult to test because digital words applied to the decimators are limited to only two possible differential values. A test pattern comprising only such digital words must be very long to ensure that the probability of making internal faults of the digital integrator observable is high enough for practical applications. 
     SUMMARY OF THE INVENTION 
     This invention is intended to provide a self-testable digital integrator having a modest hardware overhead for test pattern generation and test response compaction. Preferred embodiments of the invention are intended to provide improved observability of potential faults. 
     Accordingly, one aspect of the invention provides a self-testable digital integrator comprising adding apparatus for performing binary addition of digital words and storage apparatus for storing digital words. The adding apparatus and the storage apparatus are functionally interconnected such that the storage apparatus feeds digital words to the adding apparatus for addition thereof and the adding apparatus feeds resulting digital words to the storage apparatus for storage thereof to perform a digital integration operation. The digital integrator further comprises a first combinational network which is responsive to a first state of a test mode signal to feed an external input signal to the adding apparatus for integration thereof, and responsive to a second state of the test mode signal to feed to the adding apparatus a test pattern signal derived from selected bits of the digital words fed from the adding apparatus to the storage apparatus. The digital integrator also comprises a second combinational network responsive to the second state of the test mode signal to feed back a carry-out bit of the adding apparatus to a carry-in port of the adding apparatus, and responsive to the first state of the test mode signal to block such feedback. 
     Thus, circuitry of the digital integrator which is used in normal operation of the digital integrator to perform the integration function is used in test mode to generate a test pattern signal for testing the digital integrator and to compact test results. Consequently, the hardware overhead required for test pattern generation and test response compaction is modest. 
     The self-testable digital integrator may further comprise a third combinational network responsive to the second state of the test mode signal to feed a carry-out bit of the adding apparatus to the first combinational network, the first combinational network being responsive to the second state of the test mode signal and to the carry-out bit to modify the test pattern signal. 
     Thus, test patterns including digital words other than the limited range of digital words available in normal operation of the digital integrator are available for test purposes, making more efficient testing possible. 
     This invention is also intended to provide methods for testing digital integrators which require a modest hardware overhead for test pattern generation and test response compaction. Preferred methods are intended to provide improved observability of potential faults. 
     Thus, another aspect of the invention provides a method for self-testing a digital integrator, the digital integrator comprising adding apparatus for performing binary addition of digital words and storage apparatus for storing digital words, the adding apparatus and the storage apparatus being functionally interconnected such that the storage apparatus feeds digital words to the adding apparatus for addition thereof and the adding apparatus feeds resulting digital words to the storage apparatus for storage thereof to perform a digital integration operation. The method comprises deriving a test pattern signal from selected bits of digital words fed from the adding apparatus to the storage apparatus while feeding back a carry-out bit of the adding apparatus to a carry-in port of the adding apparatus and feeding the test pattern signal to the adding apparatus. 
     The method may further comprise modifying the test pattern signal in response to a carry-out bit of the adding apparatus. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Embodiments of the invention are described below by way of example only. Reference is made to accompanying drawings in which: 
     FIG. 1 is a block schematic diagram of a conventional digital integrator for use in decimating a sigma-delta modulated signal; 
     FIG. 2 is a series of plots 2a-2f showing state coverage and transition coverage as a function of test pattern length for the conventional digital integrator of FIG. 1 and for digital integrators according to embodiments of the invention shown in FIGS. 3-6; 
     FIG. 3 is a block schematic diagram of a self-testable digital integrator according to an embodiment of the invention; 
     FIG. 4 is a block schematic diagram similar to FIG. 3 showing a first implementation for some of the functional blocks of FIG. 3; and 
     FIG. 5 is a block schematic diagram similar to FIG. 3 showing a second implementation for some of the functional blocks of FIG. 3. 
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
     FIG. 1 is a block schematic diagram of a conventional digital integrator 100 commonly used for decimation of sigma-delta modulated signals. The conventional digital integrator 100 comprises a chain of three n-bit binary adders 110, 120, 130, each connected to a corresponding n-bit register 112, 122, 132. A first input bus 140 feeds a first input port of the first adder 110. A first output bus 141 connects an output port of the first adder 110 to a first input port of the second adder 120, and a second output bus 142 connects an output port of the second adder 120 to a first input port of the third adder 130. The first output bus 141 is also connected to the first register 112, and a first feedback bus 143 is connected from the first register 112 to a second input port of the first adder 110. The second output bus 142 is also connected to the second register 122, and a second feedback bus 144 is connected from the second register 122 to a second input port of the second adder 120. A third output bus 145 connects an output port of the third adder 130 to the third register 132, and a third feedback bus 146 connects the third register 132 to a second input port of the third adder 130. Each of the buses 140-146 is n bits wide. 
     Where the digital integrator 100 is used for decimation of sigma-delta modulated signals, the n-bit words applied to the first input port of the first adder 110 by the input bus 140 are restricted to n-bit words corresponding to differential values +1 or -1. The n-bit word corresponding to +1 has a logical 11, in the least significant bit and a logical &#34;0&#34; in all remaining bits. The n-bit word corresponding to -1 has a logical &#34;1&#34; in all n bits. Consequently, appropriate inputs to the first input port of the first adder 110 are generally arranged by permanently connecting a least significant bit line 1400 of the input bus 140 to a source of a logical &#34;1&#34; and connecting all remaining bit lines 140 1  -140 n-1  of the input bus in parallel to an input line 148 supplying a variable signal for which a logical &#34;0&#34; corresponds to a +1 value and a logical &#34;1&#34; corresponds to a - 1 value. 
     In conventional testing of the digital integrator 100, an external test pattern generator 150 would apply a test stimulus pattern to the input line 140 via a multiplexor 152 and an external test result analyzer 154 would analyze a corresponding test result pattern obtained from the third output bus 145. The test pattern generator 150 and the test result analyzer 154 could be provided by test equipment external to the integrated circuit comprising the digital integrator 100 or, according to conventional BIST architectures, could be provided on the same integrated circuit as the digital integrator 100. Alternatively, functions of the test pattern generator 150 and test result analyzer 154 could be partitioned between off-chip and on-chip functional blocks. Those functions of the test pattern generator 150 and the test result analyzer 154 which are implemented on-chip constitute a test hardware overhead which adds to the area and cost of the digital integrator 100. 
     Because of the limited range of input signals that can be applied to the digital integrator 100 via the input bus 140 and the highly sequential nature of the digital integrator&#39;s operation, a very long test pattern is required to ensure that the probability that potential faults internal to the adders 110, 120, 130 are made observable in the test results is high enough for practical applications. For example, it can be shown that, if the adders 110, 120, 130 are implemented as ripple-carry full adders, the length of test patterns required to make certain internal faults observable is proportional to 2 n  where n is the number of bits in each digital word processed by the adders 110, 120, 130. As n is typically greater than 16 for digital integrators used for decimation of sigma-delta modulated signals, the test patterns required for adequate testing can be impractically long. 
     The observability of various malfunctions of the digital integrator 100 depends on the number of different bit sequences applied to each bit of each adder input port and on the relative frequencies with which they occur. Generally, the larger the number of different bit sequences which occur relatively frequently, the greater the number of faults that are likely to be observable in the test results. In other words, the test fault coverage for a given test length increases as the randomness of the test stimulation increases. 
     An overall measure of the randomness of test stimulation is the average entropy E given by: ##EQU1## where p ij  is the probability that a stimulus j is applied at the i th  bit of an n-bit word and S is the code space of possible stimuli for application at each bit of each n-bit word. Each bit slice of each adder 110, 120, 130 has three inputs--one bit from each of the two words to be added and one carry bit from an adjacent bit slice. Thus, according to a simple analysis, S consists of 2 3  =8 combinations, and the state coverage, defined by SC=E/3, gives a comparative measure of test coverage. In an analysis which considers potential delay and transition faults, S consists of 8×8=64 possible combinations of two-vector sequences applied to each input port of each adder 110, 120, 130, and the transition coverage, defined by TC=E/6, gives a comparative measure of test coverage. 
     A random test pattern in which the two possible differential input signals are equally probable was applied to the input bus 140 in a Monte Carlo simulation to calculate the state coverage SC and the transition coverage TC as a function test pattern length for each of the three adders 110, 120, 130 of the digital integrator 100. The value of n (i.e. the number of bits in each digital word) was set at 22. The resulting values of SC and TC are plotted as solid lines in FIGS. 2a-2f. 
     Further simulations showed that the following percentages of single potential &#34;stuck-at faults&#34; in the adders 110, 120, 130 could be detected using the conventional BIST method as described above on the digital integrator 100: 
     
         ______________________________________Number of Test Words            % of Faults Detected______________________________________  10             55 100             82 1000            9310000            96______________________________________ 
    
     The fault coverage saturated at approximately 96% after 3223 test words. 
     FIG. 3 is a block schematic diagram of a self-testable digital integrator 300 according to an embodiment of the invention. The digital integrator 300 comprises adding apparatus 310 for performing binary addition of n-bit digital words and storage apparatus 320 for storing n-bit digital words. The storage apparatus 320 feeds n-bit digital words to the adding apparatus 310 via a bus 330, and the adding apparatus adds those n-bit digital words and feeds resulting n-bit digital words to the storage apparatus 320 for storage via another bus 332. 
     The digital integrator 300 further comprises first, second and third combinational networks 340, 350, 360. The first combinational network 340 receives an external input signal on an input line 370, receives on a bus 371 selected bits of the n-bit words fed via bus 332 from the adding apparatus 310 to the storage apparatus 320, receives a test mode signal on a test mode line 373, and receives a test pattern modification signal on a test pattern modification line 374 and feeds an output signal comprising n-bit digital words to the adding apparatus 310 via an adder input bus 375. The second combinational network 350 receives the test mode signal on the test mode line 373, a carry-out signal on a carry-out line 376 and feeds a signal to a carry-in port of the adding apparatus 310 via a carry-in line 377. The third combinational network 360 receives the test mode signal on the test mode line 373 and the carry-out signal from the adding apparatus 310 on the carry-out line 376, and feeds the test pattern modification signal to the first combinational network 340 on the test pattern modification line 374. 
     The first combinational network 340 responds to a first state of the test mode signal by feeding the external input signal to the adding apparatus 310 in the form of n-bit words. The second combinational network 350 responds to the first state of the test mode signal by blocking passage of the carry-out signal to the carry-in port of the adding apparatus 310. The functional interconnection of the adding apparatus 310 and the storage apparatus 320 is such that the digital integrator 300 performs a digital integration of the external input signal when the test mode signal is in its first state. 
     The third combinational network 360 responds to a second state of the test mode signal by applying the carry-out signal to the first combinational network 340. The first combinational network 340 responds to the second state of the test mode signal by deriving a test pattern signal from the selected bits received via bus 371 and by combining the test pattern signal with the carry-out signal to derive a modified test pattern signal for application to the adding apparatus 310 in the form of n-bit words. The second combinational network 350 responds to the second state of the test mode signal by passing the carry-out signal to the carry-in port of the adding apparatus 310 for compaction of a test result signal resulting from application of the test pattern signal to the adding apparatus 310. 
     Thus, the digital integrator 300 provides normal digital integration suitable for decimation of a sigma-delta modulated signal when the test mode signal is in its first state, and provides self-testing with integral test pattern generation and test result compaction when the test mode signal is in its second state. 
     FIG. 4 is a schematic diagram showing particular implementations 310&#39;, 320&#39;, 340&#39;, 350&#39;, 360&#39; for the adding apparatus 310, the storage apparatus 320, and the combinational networks 340, 350, 360 in a digital integrator 300&#39;. (In FIG. 4, heavy lines indicate buses which are n bits wide.) 
     The adding apparatus 310&#39; comprises a chain of three n-bit binary adders 312, 314, 316, and the storage apparatus 320&#39; comprises three corresponding n-bit registers 322, 324, 326. The first adder 312 has a first input port fed by the first combinational network 340&#39; via the adder input bus 375, a second input port fed by its corresponding register 322 via bus 330&#39; and an output port feeding its corresponding register 322 via bus 332&#39;. The second adder 314 has a first input port fed by the output port of the first adder 312 via buses 330&#39; and 332&#39;, a second input port fed by its corresponding register 324 via bus 330&#39; and an output port feeding its corresponding register 324 via bus 332&#39;. The third adder 316 has a first input port fed by the output port of the second adder 314 via buses 330, and 332&#39;, a second input port fed by its corresponding register 326 via bus 330&#39; and an output port feeding its corresponding register 326 via bus 332&#39;. This interconnection of adders 312, 314, 316 and registers 322, 324, 326 is similar to that shown in FIG. 1 for the conventional digital integrator 100. 
     The third combinational network 360&#39; comprises an AND gate 362 which passes a carry-out bit from the third adder 316 to the first combinational network 340&#39; when the test mode signal is a logical &#34;1&#34; and applies a logical &#34;0&#34; to the first combinational network 340&#39; when the test mode signal is a logical &#34;0&#34;. 
     The first combinational network 340&#39; comprises first and second AND gates 341, 342, first and second exclusive-OR gates 343, 344 and an OR gate 345 connected as shown in FIG. 4. The first exclusive-OR gate 343 logically combines selected bits from the second and third registers 324, 326 to derive a pseudo-random signal for test pattern generation. The first and second AND gates 341, 342 and the OR gate 345 pass either the input signal on the input line 370 or the pseudo-random signal depending on the state of the test mode signal on the test mode line 373. The second exclusive-OR gate 344 modifies the signal passed by the AND and OR gates 341, 342, 345 when a logical &#34;1&#34; is present on the pattern modification line 374, and passes the signal without modification when a logical &#34;0&#34; is present on the pattern modification line 374. 
     The first combinational network 340&#39; further comprises an output port comprising n output terminals 348 0  -348 n-1  one of the terminals 348 0  supplies a bit permanently fixed at logical &#34;1&#34;. Terminals 348 p  for every prime number value of p less than n receive the signal which is selectively modified by the second exclusive-OR gate 344, and all other terminals 348 4 , 348 6 , 348 8 , 348 9 , etc. receive the unmodified signal directly from the OR gate 345. 
     Thus, when the test mode signal is a logical &#34;0&#34;, the first combinational network 340&#39; applies a logical &#34;1&#34; to output terminal 3480 and applies the signal received on the input line 340 to all other output terminals 348 1  -348 n-1 . The resulting signal is passed as a series of n-bit words to the first input of the first adder 312 via the adder input bus 375, each n-bit word having one of the two admissible differential values for sigma-delta modulated signals, and is digitally integrated, the result of the integration being available at the output port of the third adder 316. 
     When the test mode signal is a logical &#34;1&#34;, however, the first combinational network 340&#39; blocks the signal received on the input line 340 and derives a pseudo-random test pattern signal from selected bits received on bus 371&#39;. This pseudo-random test pattern signal is applied directly to some of the output terminals 348 1  -348 n-1 , while a test pattern signal which is selectively modified according to the value of the carry-out bit is applied to others of the output terminals 348 1  -348 n-1 . The resulting signal is passed as series of n-bit words to the first input of the first adder 312 via the adder input bus 375, some of the n-bit words differing from the two admissible differential values for sigma-delta modulated signals. 
     The second combinational network 350&#39; comprises an AND gate 352 which passes a carry-out bit from the third adder 316 to a carry-in port of the third adder 316 when the test mode signal is a logical &#34;1&#34; and applies a logical &#34;0&#34; to the carry-in port of the third adder 316 when the test mode signal is a logical &#34;0&#34;. Thus, the second combinational network 350&#39; does not affect the normal operation of the digital integrator 300&#39; when the test mode signal is a logical &#34;0&#34;, but causes test result compaction when the test mode signal is a logical &#34;1&#34;. 
     Consequently, the digital integrator 300&#39; generates its own test patterns and compacts its own test results for a modest hardware overhead comprising the seven gates of the first, second and third combinational networks 340&#39;, 350&#39;, 360&#39;. Moreover, the test patterns are not limited to the restricted signal space normally encountered in digital integrators used for decimation of sigma-delta modulated signals, and this wider range of test patterns potentially leads to faster identification of internal faults. 
     The state coverage SC and the transition coverage TC for the digital integrator 300&#39; implemented as shown in FIG. 4 were calculated as a function of test pattern length and are plotted as dashed lines in FIGS. 2a-2f. Comparison with the corresponding quantities for the conventional digital integrator 100 shows that both the state coverage SC and the transition coverage TC are significantly better for the digital integrator 300&#39; than for the conventional digital integrator 100 at each of the first, second and third adders 312, 314, 316. 
     Further simulations showed that the following percentages of single potential &#34;stuck-at faults&#34; in the adders 312, 314, 316 could be detected using the improved BIST method as described above on the digital integrator 100: 
     
         ______________________________________Number of Test Words            % of Faults Detected______________________________________  10              94 100             100 1000            10010000            100______________________________________ 
    
     The fault coverage reached 100% of testable faults after only 16 test words. Thus, the improved BIST method provides an increased fault coverage at a test length which is more than 200 times shorter than the test length required for fault coverage saturation using conventional BIST methods on the conventional digital integrator 100. 
     While the first combinational network 340&#39; is connected in series with the adding apparatus 310&#39;, it does not degrade the operating speed of the digital integrator 300&#39; when the first adder 312 is implemented as a ripple-carry full adder because the propagation delay of the input signal through gates 341, 344, 345 of the first combinational network 340&#39; is essentially the same as the propagation delay of the feedback signal from the first register 322 through three similar gates of the 0 th  bit slice of the ripple-carry full adder. 
     The implementation of the digital integrator 300&#39; shown in FIG. 4 can be modified without departing from the principles of the invention as claimed below. For example, the third combinational network 360&#39; could simply pass the test mode signal so that modification of the test pattern signal is determined only by the connections of the output terminals 348 1  -348 n-1  to the gates 344, 345 of the first combinational network 340&#39; without any dependence on a carry-out bit. The connections of the output terminals 348 1  -348 n-1  to the gates 344, 345 of the first combinational network 340&#39; could also be modified. 
     The following modifications were simulated for comparison purposes: 
     Designation Conditions 
     M--middle output terminal only connected to gate 344, no dependence of test pattern on carry-out bit. 
     Mc--middle output terminal only connected to gate 344, test pattern dependent on carry-out bit. 
     O--Even numbered output terminals (i.e. 348 2 , 348 4 , 348 6 , etc. ) connected to gate 344, no dependence of test pattern on carry-out bit. 
     Oc--Even numbered output terminals (i.e. 348 2 , 348 4 , 348 6 , etc. ) connected to gate 344, test pattern dependent on carry-out bit. 
     P--Output terminals corresponding to prime numbers (i.e. 348 1 , 348 2 , 348 3 , 348 5 , 348 7 , etc. ) connected to gate 344, no dependence of test pattern on carry-out bit. 
     Pc--Output terminals corresponding to prime numbers (i.e. 348 1 , 348 2 , 348 3 , 348 5 , 348 7 , etc.) connected to gate 344, test pattern dependent on carry-out bit. 
     F--Every fourth output terminal (i.e. 348 2 , 348 6 , 348 10 , etc.) connected to gate 344, no dependence of test pattern on carry-out bit. 
     Fc--Every fourth output terminal (i.e. 348 2 , 348 6 , 348 10 , etc.) connected to gate 344, test pattern dependent on carry-out bit. 
     The state coverages SC and transition coverages TC were calculated for each of these modifications, and the calculated values are plotted as a function of test pattern length in FIGS. 2a-2f. Comparison with the corresponding quantities for the conventional digital integrator 100 shows that both the state coverages SC and the transition coverages TC are significantly better than for the conventional digital integrator 100 in every case. 
     The single &#34;stuck-at fault&#34; coverage was also simulated for each of these modifications with the following results: 
     
         ______________________________________      Number of Test Words for 100%Designation      Fault Coverage______________________________________M          17Mc         46O          13Oc         16P          123Pc         16F          33Fc         21______________________________________ 
    
     Comparison with the corresponding quantities for the conventional digital integrator 100 shows a significant reduction in test length in every case. 
     Alternative implementations 310&#34;, 320&#34;, 340&#34; of the adding apparatus 310, the storage apparatus 320 and the first combinational network 340 of the digital integrator 300 based on custom data path design are shown in FIG. 5. In this case, the adding apparatus comprises a single n-bit binary adder 310&#34;, the storage apparatus 320&#34; comprises three n-bit registers 322, 324, 326, a write address decoder 327 and two read address decoders 328, 329, and the digital integrator 300&#34; further comprises a finite state machine 390 for controlling interconnections of the single adder 310, and the registers 322, 324, 326 via the buses 330&#34;, 332&#34; and the first combinational network 340&#34; to implement the desired integration function. 
     The storage apparatus 320&#34; is connected to an output port of the adder 310&#34; by bus 332&#34;. The write address decoder 327 writes output words supplied by the adder 310&#34; on bus 332&#34; to the registers 322, 324, 326 selected according to write address signals supplied by the finite state machine 390 on a first control bus 391. The first read address decoder 328 reads words from the registers 322, 324, 326 selected according to first read address signals supplied by the finite state machine 390 on a second control bus 392 for application to the first combinational network 340&#34; via bus 371&#34;. The second read address decoder 329 reads words from the registers 322, 324, 326 selected according to second read address signals supplied by the finite state machine 390 on a third control bus 393 for application to a first input port of the adder 310&#34; via the bus 330&#34;. Two bits of each output word fed by the adder 310, to the write address decoder 327 are also fed to the first combinational network 340&#34; on bus 371&#34;. 
     The first combinational network 340&#34; comprises an exclusive-OR gate 343, a first multiplexor 347, a word generator 348 and a second multiplexor 349. The exclusive-OR gate 343 combines the two bits taken from each output word of the adder 310&#34; to derive a test pattern signal. The first multiplexor 347 selects an external input signal received on input line 370 when the test mode signal on the test mode line 373 is a logical &#34;0&#34;, and selects the test pattern signal when the test mode signal is a logical &#34;1&#34;. The selected signal is applied to the word generator 348 which comprises an exclusive-OR gate 344 and n output terminals 348 0  -348 n-1 . The output terminal 348 0  corresponding to the least significant bit is permanently connected to a logical &#34;1&#34;. Some of the other terminals 348 1  -348 n-1  are connected directly to the output of the first multiplexor 347, and the remaining terminals 348 1  -348 n-1  are connected to the output of the first multiplexor 347 via the exclusive-OR gate 344. The exclusive-OR gate 344 is also connected to the third combinational network 360&#34; which applies a logical &#34;0&#34; to the exclusive-OR gate 344 when the test mode signal is a logical &#34;0&#34; and applies a carry-out bit of the adder 310&#34; to the exclusive-OR gate 344 when the test mode signal is a logical &#34;1&#34;. The resulting n-bit word is fed to the second multiplexor 349 which selects either that word or the word supplied by the first read address decoder 328 for application to a second input port of the adder 310&#34; via bus 375 according to a control signal received on a fourth control bus 394. 
     The second combinational network 350&#34; applies a carry-out bit of the adder 310&#34; received on line 376 to a carry-in port of the adder 310&#34; via line 377 when the test mode signal is a logical &#34;1&#34;, blocking such feedback when the test mode signal is a logical &#34;0&#34;. 
     The finite state machine 390 is programmed to perform the following sequence of instructions when the test mode signal is a logical &#34;0&#34;, where P1 designates the port connected to the first read address decoder 328, P2 designates the port connected to the second read address decoder 329, P3 designates the port connected to the write address decoder, R1 designates register 322, R2 designates register 324, R3 designates register 326, and W designates the word generator 348: 
     
         ______________________________________State     P3        P2        P1______________________________________S0:       R1: =     R1 +      W →                                  S1S1:       R2: =     R2 +      R1 →                                  S2S2:       R3: =     R3 +      R2 →                                  S0______________________________________ 
    
     These instructions provide a digital integration suitable for use in decimation of sigma-delta modulated signals. 
     When the test mode signal is a logical &#34;1&#34;, however, the first multiplexor 347 selects the internally generated test pattern signal for application to the word generator 348, and the word generator 348 modifies the test pattern signal in response to the carry-out bit supplied by the third combinational network 360&#34; to provide a suitably random test stimulus. The second combinational network 350&#34; also activates internal test result compaction when the test mode signal is a logical &#34;1&#34;. 
     The finite state machine 390 may be programmed to perform the same sequence of instructions in test mode as in normal operation mode. Some possible structural faults may not be detectable in this case as port P1 is never connected to register R3. However, as this connection is not required for normal operation of the digital integrator 300&#34;, a fault affecting this connection will not affect normal operation of the digital integrator 300&#34;. 
     However, if detection of all detectable structural faults is desired for improved system reliability, the finite state machine 390 can be made responsive to the test mode signal so as to execute the following set of instructions when the test mode signal is a logical &#34;1&#34;: 
     
         ______________________________________State     P3        P2        P1______________________________________S0:       R1: =     R1 +      W →                                  S1S1:       R2: =     R2 +      R1 →                                  S2S2:       R3: =     R3 +      R2 →                                  S3S3:       R1: =     R1 +      R1 →                                  S4S4:       R2: =     R1 +      R2 →                                  S5S5:       R3: =     R2 +      R3 →                                  S0______________________________________ 
    
     These and other modifications are within the scope of the invention as defined below.