Abstract:
The present invention provides a thin film transistor (TFT) manufacturing method and a TFT, a source electrode or drain electrode of the TFT is electrically connected to a data line directly during a forming process by providing a through hole in a surface above the data line of the TFT, so as to save the process cost. Further, the source electrode and drain electrode of the TFT are also manufactured with poly-silicon rather than metal material used in prior art, processing steps are simplified, thereby further saving the process cost.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     The present application represents a divisional application of U.S. patent application Ser. No. 13/376,970 entitled “Thin Film Transistor Manufacturing Method and Thin Film Transistor” filed Dec. 8, 2011, pending, which represents a National stage application of PCT/CN2011/080158 entitled “Thin Film Transistor Manufacturing Method and Thin Film Transistor” filed Sep. 26, 2011, pending. 
    
    
     TECHNICAL FIELD OF THE INVENTION 
     The present invention relates to a field of liquid crystal display (LCD) manufacture, and more particularly, to a thin film transistor (TFT) manufacturing method and a TFT. 
     BACKGROUND OF THE INVENTION 
     An organic light emitting diode (OLED) is concerned by people more and more. An OLED screen usually utilizes an amorphous silicon (a-Si) TFT for driving, however, an electron mobility of an a-Si TFT switch device is too low to satisfy a current driving scheme of the OLED screen. Accordingly, it is particularly important to change the a-Si into poly-silicon for lifting the electron mobility so as to improve electrical characteristics of the TFT switch device. 
     The current technique has shortcomings that the TFT is directly formed on a transparent substrate, therefore it is necessary to grow a multi-laminated structure thereon, in addition, it is also necessary to manufacture electrical connection structure between the TFT and external components, so that the working process is complicated, and the cost is higher. 
     SUMMARY OF THE INVENTION 
     In order to solve the technical problems above, the present invention provides a TFT manufacturing method and a TFT, by which the processing cost can be saved. 
     To solve the above problems, the present invention provides a TFT manufacturing method, which comprises steps of: providing a transparent substrate; forming a gate electrode and a data line on a surface of the transparent substrate; forming a first insulation layer covering the gate electrode and the data line on the surface of the transparent substrate; forming an amorphous semiconductor layer on a surface of the first insulation layer in an area corresponding to the gate electrode; forming a through hole on the surface of the first insulation layer in an area corresponding to the data line; forming a conductive layer, which covers the amorphous semiconductor layer and the through hole, on the surface of the first insulation layer; removing a portion of the conductive layer corresponding to the gate electrode to cut the conductive layer, thereby forming a source electrode and a drain electrode of the TFT; forming a second insulation layer, which covers the amorphous semiconductor layer, the through hole and the source electrode as well as the drain electrode, on the surface of the first insulation layer; and irradiating the amorphous semiconductor layer by laser to increase an ordering degree of a lattice arrangement of the amorphous semiconductor layer. 
     The present invention further provides a TFT, which comprises: a transparent substrate; a gate electrode and a data line, which are disposed on a surface of the transparent substrate; a first insulation layer, which covers the gate electrode and the data line; an amorphous semiconductor layer, which is disposed on a surface of the first insulation layer in an area corresponding to the gate electrode; a through hole, which is disposed in an area of the surface of the first insulation layer corresponding with the data line; a source electrode and a drain electrode, which are disposed at two ends of the amorphous semiconductor layer, and one of the source electrode and the drain electrode being connected to the data line via the through hole; and the second insulation layer, which is on the surface of the first insulation layer and covers the amorphous semiconductor layer, the through hole and the source electrode as well as the drain electrode. 
     The present invention further provides a TFT, which comprises: a transparent substrate; a gate electrode and a data line, which are disposed on a surface of the transparent substrate; a first insulation layer, which covers the gate electrode and the data line; an amorphous semiconductor layer, which is disposed on a surface of the first insulation layer in an area corresponding to the gate electrode, the amorphous semiconductor comprising a first amorphous semiconductor layer and a second amorphous semiconductor layer having the same conductive type and being laminated, the first amorphous semiconductor layer being attached with the first insulation layer, a conductivity of the second amorphous semiconductor layer being higher than that of the first amorphous semiconductor layer; a through hole, which is disposed in an area of the surface of the first insulation layer corresponding with the data line; a source electrode and a drain electrode, which are disposed at two ends of the amorphous semiconductor layer, and one of the source electrode and the drain electrode being connected to the data line via the through hole, the second amorphous semiconductor layer being attached with the source electrode and the drain electrode; and the second insulation layer, which is on the surface of the first insulation layer and covers the amorphous semiconductor layer, the through hole and the source electrode as well as the drain electrode, a portion of the second insulation layer between the source electrode and the drain electrode being hollowed. 
     An advantage of the present invention is that the source electrode or the drain electrode of the TFT is electrically connected with the data line directly during the forming process, so the processing cost is saved. Further, the source electrode and the drain electrode are also manufactured with poly-silicon rather than metal material used in the current technique, so that processing steps are simplified, and thereby further saving the processing cost. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a flow chart of steps of a method described in an embodiment of the present invention. 
         FIG. 2A  to  FIG. 2J  show schematic diagrams of processing of the method described in the embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Embodiments of the TFT manufacturing method and the TFT provided by the present invention will be described in detail by referring to the accompanying drawings. 
     In order to manifest objectives, features and advantages of the present invention, preferable embodiments will be described in detail in conjunction with the drawings accompanying with the specification. Amongst, each component in the embodiments is arranged for clearly describing the contents disclosed in the present invention but not used to limit the present invention. Furthermore, some reference numbers are replicated in different embodiments for the reason of simplifying the descriptions rather than implying correlation among the different embodiments. 
       FIG. 1  shows a flow chart of steps of a method described in an embodiment of the present invention, which comprises: step S 100 , providing a transparent substrate; step S 110 , forming a gate electrode of a TFT and a data line on a surface of the transparent substrate; step S 120 , forming a first insulation layer which covers the gate electrode and the data line on the surface of the transparent substrate; step S 130 , forming an amorphous semiconductor layer on a surface of the first insulation layer in an area corresponding to the gate electrode, wherein the amorphous semiconductor layer comprises a first amorphous semiconductor layer and a second amorphous semiconductor layer, the second amorphous semiconductor layer is laminated on the first amorphous semiconductor layer; step S 140 , forming a through hole in an area of the surface of the first insulation layer corresponding to the data line; step S 150 , forming a conductive layer which covers the amorphous semiconductor layer and the through hole on the surface of the first insulation layer; step S 160 , removing a portion of the conductive layer, a portion of the second amorphous semiconductor layer and a portion of the first amorphous semiconductor layer, which correspond to the gate electrode, to cut the conductive layer and the second amorphous semiconductor layer and to thin the first amorphous semiconductor layer, so as to form a source electrode and a drain electrode of the TFT; step S 170 , forming a second insulation layer, which covers the amorphous semiconductor layer, the through hole as well as the source electrode and the drain electrode, on the surface of the first insulation layer; step S 180 , removing a portion of the second insulation layer, which is located between the source electrode and the drain electrode; step S 190 , irradiating the amorphous semiconductor layer with laser to increase the ordering degree of the lattice arrangement of the amorphous semiconductor layer. 
       FIG. 2A  to  FIG. 2J  show schematic diagrams of processing of the method described in the embodiment of the present invention. 
     As shown in  FIG. 2A , with reference to step S 100 , the transparent  200  is provided. The material of the transparent substrate  200  may be any of the common materials including glass. 
     As shown in  FIG. 2B , with reference to step S 110 , a gate electrode  210  of a TFT and a data line  230  are formed on a surface of the transparent substrate  200 . The material of the gate electrode  210  and the data line  230  may be conductive material such as poly-silicon or metal. In the present embodiment, the gate electrode  210  and the date line  230  are manufactured at the same time in this step. Furthermore, in the following steps, the electrical connection between the data line  230  and a source electrode of the TFT or a drain electrode of the TFT is formed by integrating process at the same time when the TFT is formed, so as to reduce the processing steps. 
     As shown in  FIG. 2C , with reference to step S 120 , a first insulation layer  251 , which covers the gate electrode  210  and the data line  230 , is formed on the surface of the transparent substrate  200 . The material of the first insulation layer  251  may be silicon oxide, silicon nitride or other insulating materials. And the forming method of the first insulation layer  251  may be any common processing method such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). 
     As shown in  FIG. 2D , with reference to step S 130 , an amorphous semiconductor layer  270  is formed on a surface of the first insulation layer  251  in an area corresponding to the gate electrode  210 . The material of the amorphous semiconductor layer  270  may be amorphous silicon, or other common semiconductor materials such as Gallium arsenide or Silicon-germanium. The forming method of the amorphous semiconductor layer  270  may comprise: firstly, epitaxizing or depositing a continuous amorphous semiconductor material on the surface of the first insulation layer  251 , and then an amorphous semiconductor layer  270  as shown in  FIG. 2D  is formed by retaining a designated area through an photo etch process. A doping concentration of the amorphous semiconductor layer  270  can be adjusted by controlling a dopant dosage supplied in the epitaxy or deposition process. 
     Still with reference to  FIG. 2D , in the present embodiment, the amorphous semiconductor  270  further comprises a first amorphous semiconductor layer  271  and a second amorphous semiconductor layer  272 , which are laminated and are of the same conductive type. The first amorphous semiconductor layer  271  is attached to the first insulation layer  251 . The second amorphous semiconductor layer  272  is exposed in this step, and will be attached to the source electrode of the TFT and the drain electrode of the TFT in the subsequent step. The conductivity of the second amorphous layer  272  is higher than that of the first amorphous layer  271 , A high conductivity means a high doping concentration (for example, N-doped amorphous silicon with a high doping concentration), and the high doping concentration is advantageous to forming a good ohm contact with the source electrode and the drain electrode, while a semiconductor layer with a low doping concentration is easier to be controlled by the gate electrode of the TFT to change the conductive type thereof. So it is selected to divide the amorphous semiconductor  270  into the low doped first amorphous semiconductor layer  271  and the high doped second amorphous semiconductor layer  272  in the present embodiment. 
     As shown in  FIG. 2E , with reference to step S 140 , a through hole  231  is formed in an area of the surface of the first insulation layer  251  corresponding to the data line  230 . The step of forming the through hole  231  can be done by photo etch process. The function of the through hole  231  is forming an electrical connection between the data line  230  and the source electrode or drain electrode subsequently. 
     As shown in  FIG. 2F , with reference to step S 150 , a conductive layer  290 , which covers the amorphous semiconductor layer  270  and the through hole  231 , is formed on the surface of the first insulation layer  251 . The material of the conductive layer  290  may be one selected from indium tin oxide (ITO) and indium zinc oxide (IZO). The forming method, for example, may be spin-coating, spray-coating or the like. The conductive layer  290  covers the through hole  231 , and is attached to the data line  230  below the through hole  231 , so as to implement the electrical connection. 
     As shown in  FIG. 2G , with reference to step S 160 , a portion of the conductive layer  290 , a portion of the second amorphous semiconductor layer  272  and a portion of the first amorphous semiconductor layer  271 , which correspond to the gate electrode  210 , are removed to cut the conductive layer  290  and the second amorphous semiconductor layer  272 , and to thin the first amorphous conductive layer  271 , so as to form a source electrode  291  and a drain electrode  292  of the TFT. Amongst, a location of the source electrode  291  and a location of the drain electrode  292  may be exchanged. The processes of cutting the conductive layer  290  and the second amorphous semiconductor layer  272  and thinning the first amorphous semiconductor layer  271  may be implemented by utilizing photo etch process. Since the electrical connection between the conductive layer  290  and the data line  230  has been established in the previous step, therefore it is not necessary to manufacture an electrical connection structure between the source electrode  291 , which is formed in the present embodiment, and the data line  230  additionally. 
     As shown in  FIG. 2H , with reference to step S 170 , a second insulation layer  252 , which covers the amorphous semiconductor layer  270 , the through hole  231  as well as the source electrode  291  and the drain electrode  292 , is formed on the surface of the first insulation layer  251 . The material of the second insulation layer  252 , of which the function is protecting the covered amorphous semiconductor layer  270 , the through hole  231  as well as the source electrode  291  and drain electrode  292 , may be an arbitrary one of insulating materials including silicon oxide and silicon nitride. 
     As shown in  FIG. 2I , with reference to step S 180 , a portion of the second insulation layer  252 , which is located between the source electrode  291  and the drain electrode  292 , is removed. This step is used for forming a pixel electrode pattern. 
     As shown in  FIG. 2J , with reference to step S 190 , the amorphous semiconductor layer  270  is irradiated by laser to increase the ordering degree of the lattice arrangement of the amorphous semiconductor layer  270 . The amorphous semiconductor layer  270  is annealed under the irradiation of the laser, and transforms from an amorphous material to a polycrystalline material. The amorphous material may transforms into the polycrystalline material under a circumstance that the laser power is sufficiently high and the irradiation continues for a sufficiently long time. The ordering degree of the lattice of the polycrystalline material is better, so it has a higher carrier mobility, and therefore is able to improve the electrical performances of the TFT. Since the thickness of the second insulation layer  252  is usually less than that of the transparent substrate  200 , it is preferred that the laser enters from the side of the second insulation layer  252 , and the laser should have a wavelength that is able to penetrate the second insulation layer  252  and the conductive layer  290 . In a condition that the material of the second insulation layer  252  is silicon nitride or silicon oxide and the material of the conductive layer  290  is ITO or IZO, lasers of a visible light band and an infrared band are all transparent to these materials. 
     Still with reference to  FIG. 2J , the TFT obtained after the above steps are executed completely comprises a structure as described below: the transparent substrate  200 ; the gate electrode  210  and the data line  230 , which are disposed on a surface of the transparent substrate  200 ; the first insulation layer  251 , which covers the gate electrode  210  and the data line  230 ; the amorphous semiconductor layer  270 , which comprises the first amorphous semiconductor layer  271  and the second amorphous semiconductor layer  272 , and is provided on the surface of the first insulation layer  251  in the area corresponding to the gate electrode  210 ; the through hole  231 , which is provided in the area of the surface of the first insulation layer  251  corresponding to the data line  230 ; the source electrode  291  and the drain electrode  292 , which are provided at two ends of the amorphous semiconductor layer  270 , and one of which is connected to the data line  230  via the through hole  231 ; and the second insulation layer  252 , which is on the surface of the first insulation layer  251  and covers the amorphous semiconductor layer  270 , the through hole  231  as well as the source electrode  291  and the drain electrode  292 , and of which the portion between the source electrode  291  and the drain electrode  292  is hollowed. The thickness of the first amorphous semiconductor layer  271  of the portion between the source electrode  291  and the drain electrode  292  is less than that of the other portions of the first amorphous semiconductor layer  271 . 
     The above are only preferred embodiments of the present invention, it is noted that various modifications and alterations can be made by persons skilled in this art without departing from the principles of the present invention, and therefore those modifications and alterations should also be deemed to be in the protection range of the present invention.