Abstract:
A damascene MIM capacitor and a method of fabricating the MIM capacitor. The MIN capacitor includes a dielectric layer having top and bottom surfaces; a trench in the dielectric layer, the trench extending from the top surface to the bottom surface of the dielectric layer; a first plate of a MIM capacitor comprising a conformal conductive liner formed on all sidewalls and extending along a bottom of the trench, the bottom of the trench coplanar with the bottom surface of the dielectric layer; an insulating layer formed over a top surface of the conformal conductive liner; and a second plate of the MIM capacitor comprising a core conductor in direct physical contact with the insulating layer, the core conductor filling spaces in the trench not filled by the conformal conductive liner and the insulating layer. The method includes forming portions of the MIM capacitor simultaneously with damascene interconnection wires.

Description:
RELATED APPLICATIONS  
       [0001]     This application is a division of copending U.S. application Ser. No. 11/106,887 filed on Apr. 15, 2005. 
     
    
     FIELD OF THE INVENTION  
       [0002]     The present invention relates to the field of integrated circuits and integrated circuit fabrication; more specifically, it relates to metal-insulator-metal capacitor and a method of fabricating the metal-insulator-metal capacitor.  
       BACKGROUND OF THE INVENTION  
       [0003]     Metal-insulator-metal capacitors (MIM or MIM cap) are integrated into various integrated circuits for applications such as analog-logic, analog-to-digital, mixed signal and radio frequency circuits. Current methods of integration of MIMs into integrated circuits require multiple extra photolithographic and etching steps beyond those required for all other components of the integrated circuits thus adding considerable cost and time to the manufacture of integrated circuits incorporating MIMs.  
         [0004]     Thus, there is a need for a simple and inexpensive integration scheme for fabrication of integrated circuits utilizing MIMs.  
       SUMMARY OF THE INVENTION  
       [0005]     The present invention utilizes damascene and dual damascene technology to fabricate MIMs in wiring levels of integrated circuits. The MIMs are fabricated simultaneously with normal damascene and dual damascene wires and vias by adding a number of steps to a dual damascene process. The MIMs themselves are dual damascene structures.  
         [0006]     A first aspect of the present invention is a structure, comprising: a dielectric layer on a top surface of a semiconductor substrate, the dielectric layer having a top surface and a bottom surface; a trench in the dielectric layer, the trench extending from the top surface to the bottom surface of the dielectric layer; a first plate of a MIM capacitor comprising a conformal conductive liner having a top surface and a bottom surface, the bottom surface of the conformal conductive liner in direct physical contact with all sidewalls and extending along a bottom of the trench, the bottom of the trench coplanar with the bottom surface of the dielectric layer; a conformal insulating layer formed on a top surface of the conformal conductive liner; and a second plate of the MIM capacitor comprising a single layer of a core conductor in direct physical contact with the insulating layer, the core conductor filling spaces in the trench not filled by the conformal conductive liner and the insulating layer. 
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0007]     The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:  
         [0008]      FIGS. 1A through 1E  are cross-sectional drawings illustrating common steps for manufacture of MIM capacitor devices according to is according to the various embodiments of the present invention;  
         [0009]      FIGS. 2A through 2D  are cross-sectional drawings illustrating steps for manufacture of MIM capacitor devices according to a first and a second embodiment of the present invention;  
         [0010]      FIG. 2E  is a cross-sectional drawings illustrating steps for manufacture of MIM capacitor devices according to a third and a fourth embodiment of the present invention;  
         [0011]      FIGS. 3A through 3D  are cross-sectional drawings illustrating steps for manufacture of MIM capacitor devices according to a fifth and a sixth embodiment of the present invention;  
         [0012]      FIG. 3E  is a cross-sectional drawings illustrating steps for manufacture of MIM capacitor devices according to a seventh and an eighth embodiment of the present invention;  
         [0013]      FIG. 4  is a top view of a MIM capacitor according to the first, third, fifth and seventh embodiments of the present invention; and  
         [0014]      FIG. 5  is a top view of a MIM capacitor according to the second, fourth, sixth and eight embodiments of the present invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0015]     A damascene process is one in which wire trench or via openings are formed in a dielectric layer, an electrical conductor deposited on a top surface of the dielectric of sufficient thickness to fill the trenches and a chemical-mechanical-polish (CMP) process performed to remove excess conductor and make the surface of the conductor co-planer with the surface of the dielectric layer to form damascene wires (or damascene vias).  
         [0016]     A dual damascene process is one in which via openings are formed through the entire thickness of a dielectric layer followed by formation of trenches part of the way through the dielectric layer in any given cross-sectional view. All via openings are intersected by integral wire trenches above and by a wire trench below, but not all trenches need intersect a via opening. An electrical conductor is deposited on a top surface of the dielectric of sufficient thickness to fill the trenches and via opening and a CMP process performed to make the surface of the conductor in the trench co-planer with the surface the dielectric layer to form dual damascene wire and dual damascene wires having integral dual damascene vias. While vias often have square cross-sections when viewed from above, vias may be elongated to have rectangular cross sections when viewed from above and are then known as via bars. Therefore, a via with a square cross-section should be considered as a special case of a via bar.  
         [0017]     Unless otherwise noted, trenches, via openings, and other openings or patterns formed in the various layers of the present invention are formed by conventional photolithography by applying a photoresist layer, exposing the photoresist layer to electromagnetic radiation through a mask, developing a pattern in the exposed photoresist layer and etching the regions of exposed layer with either a wet or a dry etch. An example of a dry etch is a reactive ion etch (RIE).  
         [0018]      FIGS. 1A through 1E  are cross-sectional drawings illustrating common steps for manufacture of MIM capacitor devices according to is according to the various embodiments of the present invention. In  FIG. 1 , a semiconductor substrate  100  having top surface  105  is provided. Semiconductor substrate may include active devices such as transistor and diodes as well as passive devices such as resistors and one or more wiring levels for interconnecting the active and passive devices into integrated circuits. An interlevel dielectric layer  110  is formed on top surface  105  of substrate  100 . Conductors  115 A and  115 B formed in dielectric layer  110 . Top surfaces  120 A and  120 B respectively of conductors  115 A and  155 B are coplanar with a top surface  125  of dielectric layer  110 . In the present example, conductors  115 A and  115 B are damascene conductors. In one example, conductor  115 A and  115 B comprise copper and dielectric layer is a silicon based dielectric.  
         [0019]     In  FIG. 1B , a dielectric layer  130  is formed as on top surfaces  120 A and  120 B respectively of conductors  115 A and  115 B as well on a top surface  125  of dielectric layer  110 . Formed on a top surface  135  of dielectric layer  130  is an interlevel dielectric layer  140 . Dielectric layer  130  may comprise, for example, silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon carbide (SiC), silicon oxy nitride (SiON), silicon oxy carbide (SiOC), hydrogen doped silica glass (SiCOH), plasma-enhanced silicon nitride (PSiN x ) or NBLoK (SiC(N,H)). Dielectric layer  130  may be, for example, between about 5 nm and about 100 nm thick. In one example, dielectric layer  140  is a low K (dielectric constant) material, examples of which include but are not limited to hydrogen silsesquioxane polymer (HSQ), methyl silsesquioxane polymer (MSQ) and polyphenylene oligomer (SiO x (CH 3 ) y ). A low K dielectric material has a relative permittivity of about 4 or less. In a second example, dielectric layer  140  comprises SiO 2 . Dielectric layer  140  may be, for example, between about 50 nm and about 1,000 nm thick.  
         [0020]     In  FIG. 1C , formed in a first region  145 A of dielectric layer  140  is a trench  150 A and a via opening  155 A. Formed in a second region  160 A of dielectric layer  140  is a trench  165 A and a single via bar opening  170 A. Formed in a third region  145 B of dielectric layer  140  is a trench  150 B and a via opening  155 B. Formed in a fourth region  160 B of dielectric layer  140  is a trench  165 B and a multiple via bar openings  170 B. While three via bar opening  170 B are illustrated in  FIG. 1C , there may be any number of via bar openings, with two as a minimum number of via bar openings. Via openings  155 A and via bar opening  170 A extend to conductor  115 A and via opening  155 B and via bar openings  170 B extend down to conductor  115 B.  
         [0021]     In  FIG. 1D , a conformal conductive liner  175  is formed on all sidewalls of trenches  150 A,  165 A,  150 B and  165 B (see  FIG. 1C ), via openings  155 A and  155 B (see  FIG. 1C ) and via bar openings  170 A and  170 B (see  FIG. 1C ). Liner  175  is in direct electrical contact with conductors  115 A and  115 B. Then trenches  150 A,  165 A,  150 B and  165 B (see  FIG. 1C ), via openings  155 A and  155 B (see  FIG. 1C ) and via bar openings  170 A and  170 B (see  FIG. 1C ) are filled with a core conductor  180 . Liner  175  may act as a copper diffusion barrier. In one example, liner  175  comprises Ta, TaN, Ti, TiN, TiSiN, W, Ru or combinations thereof. In one example, liner  175  is between about 5 nm and about 100 nm thick. In one example, core conductor  180  is Cu, Al, AlCu or W.  
         [0022]     The processes used to fill regions  145 A,  145 B,  160 A and  160 B are damascene processes. A conformal layer of liner material is deposited, a layer of core material is formed (in the example of core conductor  180  being copper, a thin copper layer is evaporated or deposited and then a thicker layer of copper is electroplated) followed by a CMP to planarize dielectric layer  140 , liner  175  and core conductor  180  to a common surface  182 . The processes used and the structures formed in regions  145 A,  145 B,  160 A and  160 B are the same as used to form the conventional wires, vias and via bars in other regions (not shown) of dielectric layer  140  that are used to form circuits from devices contained in the substrate  100 .  
         [0023]     In  FIG. 1E , a hard mask layer  185  is formed and patterned to expose core conductor  180  in regions  160 A and  160 B but in no other regions of dielectric layer  140  including those regions in which the conventional wires described supra were simultaneously formed. Hard mask layer  185  may comprise a dielectric material, for example, silicon dioxide, silicon nitride, silicon carbide, silicon oxy nitride, silicon oxy carbide, hydrogen doped silica glass, plasma-enhanced silicon nitride or NBLoK. Dielectric layer  185  may be, for example, between about 5 nm and about 100 nm thick. It is possible for hard mask layer  185  to comprise a metal.  
         [0024]      FIGS. 2A through 2D  are cross-sectional drawings illustrating steps for manufacture of MIM capacitor devices according to a first and a second embodiment of the present invention. In  FIGS. 2A through 2D , a MIM capacitor according to the first embodiment of the present invention will be formed in region  160 A and a MIM capacitor according to the second embodiment of the present invention will be formed in region  160 B. In  FIG. 2A , all of core conductor  180  is removed from regions  160 A and  160 B (see  FIG. 1E ). In one example, an etchant comprising HNO 3 , HCl, H 2 SO 4 , HF or combinations thereof is used to wet etch the core conductor.  
         [0025]     In  FIG. 2B , a dielectric layer  190  is blanket deposited and it should be particularly noted that dielectric layer covers all surfaces of liner  175  in regions  160 A and  160 B. In one example dielectric layer  190  comprises silicon dioxide, silicon nitride, silicon carbide, silicon oxy nitride, silicon oxy carbide, hydrogen doped silica glass, plasma-enhanced silicon nitride, NBLoK, a high K (dielectric constant) material, examples of which include but are not limited metal oxides such as Ta 2 O 5 , BaTiO 3 , HfO 2 , ZrO 2 , Al 2 O 3 , or metal silicates such as HfSi x O y  or HfSi x O y N z  or combinations thereof. A high K dielectric material has a relative permittivity above 10. In one example, dielectric layer  190  is between about 2 nm and about 100 nm thick.  
         [0026]     In  FIG. 2C , a core conductor  195  is formed over dielectric layer  190 . In one example, core conductor  195  is copper formed evaporation or deposition of a thin layer of copper over dielectric layer  190  followed by electroplating a thicker layer of copper. In a second example, core conductor  195  is copper or another metal formed by physical vapor deposition (PVD), chemical vapor deposition (CVD) or electroless plating. In a third example, conductor  190  is same as one or all of the materials used to form the conventional wires, vias and via bars that are used to form circuits from devices contained in the substrate  100 . Core conductor  195  is thick enough to completely fill regions  160 A and  160 B.  
         [0027]     In  FIG. 2D , a CMP process is used to remove all excess core conductor  195 , dielectric layer  190  and dielectric layer  185  (see  FIG. 2C ) and form a common planer surface  183  with dielectric layer  140 .  
         [0028]     In  FIG. 2D  a first device  200 A comprises a MIM capacitor  205 A, a contact  210 A and conductor  115 A. A first plate of MIM capacitor  205 A comprises core conductor  195 . The insulator of MIM capacitor  205 A comprises dielectric layer  190 . A second plate of MIM capacitor  205 A comprises conductive liner  175 . Electrical connection between the second plate of MIM capacitor  205 A is via contact  210 A through conductor  115 A. It should be noted that contacts  210 A and  210 B are identical to dual damascene wires that are formed in dielectric layer  140  as interconnect wiring of the integrated chip.  
         [0029]     A second device  200 B comprises a MIM capacitor  205 B, a contact  210 B and conductor  115 B. A first plate of MIM capacitor  205 B comprises core conductor  195 . The insulator of MIM capacitor  205 B comprises dielectric layer  190 . A second plate of MIM capacitor  205 B comprises conductive liner  175 . Electrical connection between the second plate of MIM capacitor  205 B is via contact  210 B through conductor  115 B.  
         [0030]     The essential difference between MIM capacitor  205 A and  205 B is MIM capacitor  205 B has more dielectric area because of the use of crenulations  215  in the lower portion of the structure, that portion contacting conductor  115 B.  
         [0031]      FIG. 2E  is a cross-sectional drawings illustrating steps for manufacture of MIM capacitor devices according to a third and a fourth embodiment of the present invention. In  FIG. 2E , a first device  200 C comprises a MIM capacitor  205 C, a contact  210 C and conductor  115 A. A first plate of MIM capacitor  205 C comprises core conductor  195 . A second device  200 D comprises a MIM capacitor  205 D, a contact  210 D and conductor  115 B. A second plate of MIM capacitor  205 D comprises conductive liner  175 .  
         [0032]     In  FIG. 2E , an optional recess process is performed to recess core conductors  180  and  195  below surface  183 . This reduces the possibility of shorts between conductive liner  175  and core conductor  195 . In one example, the recess process is a wet etch using an etchant comprising HNO 3 , HCl, H 2 SO 4 , HF or combinations thereof. In a second example, the CMP process used to generate the structures of  FIG. 2D  are adjusted to cause dishing in at least core conductor  195  of MIM capacitors  205 C and  205 D. Dishing is phenomenon of CMP where large features do not polish straight across, but curve convexly or concavely in the same sense as concave and convex optical lenses are defined. In one example, the recess is between about 1 m and about 100 nm below top surface  183 .  
         [0033]      FIGS. 3A through 3D  are cross-sectional drawings illustrating steps for manufacture of MIM capacitor devices according to a fifth and a sixth embodiment of the present invention. In  FIGS. 3A through 3D , a MIM capacitor according to the fifth embodiment of the present invention will be formed in region  160 A and a MIM capacitor according to the sixth embodiment of the present invention will be formed in region  160 B.  FIGS. 3A through 3D  are similar to  FIGS. 2A through 2D  so only the differences will be described infra.  
         [0034]     In  FIG. 3A , an uppermost portion of core conductor  180  is removed from regions  160 A and  160 B (see  FIG. 1E ). In one example, an etchant comprising HNO 3 , HCl, H 2 SO 4 , HF or combinations thereof is used to wet etch the core conductor. Thus some core conductor  195  remains in direct and physical contact with liner  175  in regions  160 A and  160 B.  
         [0035]     In  FIG. 3B , dielectric layer  190  contacts remaining portions of conductor  180  in regions  160 A and  160 B.  
         [0036]     In  FIG. 3D  a first device  220 A comprises a MIM capacitor  225 A, a contact  230 A and conductor  115 A. A first plate of MIM capacitor  225 A comprises core conductor  195 . The insulator of MIM capacitor  225 A comprises dielectric layer  190 . A first portion of a second plate of MIM capacitor  225 A comprises conductive liner  175 . Remaining conductor  180  comprises a second portion of second plate of MIM capacitor  225 A. Electrical connection between the second plate of MIM capacitor  225 A is via contact  230 A through conductor  115 A.  
         [0037]     A second device  220 B comprises a MIM capacitor  225 B, a contact  230 B and conductor  115 B. A first portion of a second plate of MIM capacitor  225 B comprises conductive liner  175 . Remaining conductor  180  comprises a second portion of second plate of MIM capacitor  225 B. The insulator of MIM capacitor  225 B comprises dielectric layer  190 . A first plate of MIM capacitor  225 B comprises core conductor  195 . Electrical connection between the second plate of MIM capacitor  225 B is via contact  230 B through conductor  115 B.  
         [0038]     It should be noted that contacts  230 A and  230 B are identical to dual damascene wires that are formed in dielectric layer  140  as interconnect wiring of the integrated chip.  
         [0039]      FIG. 3E  is a cross-sectional drawings illustrating steps for manufacture of MIM capacitor devices according to a seventh and an eighth embodiment of the present invention. In  FIG. 3E , a first device  220 C comprises a MIM capacitor, a contact  230 C and conductor  115 A. A first plate of MIM capacitor  225 C comprises core conductor  195 . The insulator of MIM capacitor  225 C comprises dielectric layer  190 . A first portion of a second plate of MIM capacitor  225 C comprises conductive liner  175 . Remaining conductor  180  comprises a second portion of second plate of MIM capacitor  225 C.  
         [0040]     A second device  220 D comprises a MIM capacitor  225 B, a contact  230 D and conductor  115 B. A first plate of MIM capacitor  225 D comprises core conductor  195 . The insulator of MIM capacitor  225 D comprises dielectric layer  190 . A first portion of a second plate of MIM capacitor  225 D comprises conductive liner  175 . Remaining conductor  180  comprises a second portion of second plate of MIM capacitor  225 D. Electrical connection between the second plate of MIM capacitor  225 D is via contact  230 D through conductor  115 B.  
         [0041]     In  FIG. 3E , an optional recess process is performed to recess core conductors  180  and  195  below surface  183  as described supra in reference to  FIG. 2E . In one example, the recess is between about 1 nm and about 100 nm below top surface  183 .  
         [0042]      FIG. 4  is a top view of a MIM capacitor according to the first, third, fifth and seventh embodiments of the present invention. In  FIG. 4 , conductor  115 A extends under contact  210 A/ 230 A and completely under MIM capacitor  205 A/ 225 A providing electrical connection to the second plate of the capacitor formed from liner  175 . In  FIG. 4 , heavy dashed line  235 A defines an alternate shape for conductor  115 A, illustrating that conductor  115 A needs only to contact a portion of conductive liner  175 .  
         [0043]      FIG. 5  is a top view of a MIM capacitor according to the second, fourth, sixth and eighth embodiments of the present invention. In  FIG. 5 , conductor  115 A extends under contact  210 B/ 230 B and under MIM capacitor  205 B/ 225 B providing electrical connection to the second plate of the capacitor formed from liner  175  and conductor  180 . In  FIG. 5 , heavy dashed line  235 B defines an alternate shape for conductor  115 B, illustrating that conductor  115 B needs only to contact a portion of conductive liner  175 .  
         [0044]     While  FIG. 5  illustrates crenulations  215  as a row via bars, however crenulations  215  can be replaced with a row of square vias, a row of circular vias, an array of square vias, and array of circular vias, an array of via bars, rows and arrays of other vias having other geometric shapes and combinations thereof.  
         [0045]     Therefore, the present invention provides a simple and inexpensive integration scheme for fabrication of integrated circuits utilizing MIMs.  
         [0046]     The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.