Abstract:
A data processing apparatus adopting a pipeline processing system, includes an instruction memory which store instruction packets; and a processing unit configured to execute the instruction packets sequentially in a pipeline manner. The processing unit includes an instruction queue and a loop speed-up circuit. The instruction packets stored in the instruction queue are executed sequentially by the processing unit. The loop speed-up circuit stores the instruction packets read out from the instruction memory into the instruction queue sequentially, holds the instruction packet containing a loop start address for a loop process, and outputs the held instruction packet to the instruction queue, when a loop process end is detected and the loop process is not circulated for a predetermined number of times.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a data processing apparatus adopting a pipeline processing system, in which a plurality of processes are executed in parallel, and a data processing method used in the same.  
         [0003]     2. Description of the Related Art  
         [0004]     In order to speed up processing, a “pipeline processing system” has been adopted in a data processing apparatus to execute a plurality of instructions in parallel while shifting slightly in timing.  
         [0005]     In the pipeline processing, the processing speed itself for executing the instructions is not speeded up. However, the instructions are executed in parallel (in the pipeline processing, the execution step is generally referred to as a “stage”), which contributes an increase of the performance for each unit time. As a result, the processing speed can be improved. If a job is enough, a speed improvement ratio in the pipeline processing is equal with the number of stages.  
         [0006]     In general, the data processing apparatus reads an instruction packet for instructions to be executed from the instruction memory, and stores the read instruction packet in an instruction queue. Then, the instructions of the instruction packet are read out from the instruction queue and are executed. The operation to read the instruction packet from the instruction memory and to store them in the instruction queue previously is referred to as a “preceding read” 
         [0007]     In the data processing apparatus adopting a pipeline processing system, when an instruction group of a same process is repeated, that is, when loop processing is executed, the speed improvement ratio reduces sometimes.  
         [0008]     Next, the pipeline processing in a conventional data processing apparatus at a loop back will be described.  FIG. 1  shows a configuration of the conventional data processing apparatus. A processor  500  has an instruction queue  506 . The processor  500  reads an instruction packet from an instruction memory  600  into the instruction queue  506 . The processor  500  determines whether an instruction to be executed is a loop start instruction, that is, whether the loop start instruction has been issued. Also, the processor  500  determines whether the processing should be looped out from a loop, during the execution of the loop instruction.  
         [0009]      FIG. 2  shows an operation of the data processing apparatus at the loop back, that is, an operation when the processing returns to the head of the loop since the loop is not circulated for the predetermined number of times. Here, it is supposed that the processor  500  requires time for two stages to read the instruction packet from the instruction memory  600 . As shown in  FIG. 3 , in the loop processing, instructions from a first instruction (LT 1 ) to a last instruction (LL) are repeated for the predetermined number of times. In the example shown in  FIG. 3 , a loop end (LE) is detected in the instruction immediately before the last instruction (LL) of the loop. In response to the detection of the loop end, it is determined whether the loop has been repeated for the predetermined number of times. When it is determined that the loop has not repeated for the predetermined number of times, the processing returns to the first instruction after the execution of the last instruction of the loop, that is the loop back is carried out. When it is determined that the loop has been repeated for the predetermined number of times, the processing loops out after execution of the last instruction. In this case, the processor  500  executes the instructions in the order from LE to LL, LT 1 , LT 2 , . . . at the loop back.  
         [0010]     However, as shown in  FIG. 2 , the processor  500  has already started to read the instruction packet at the detection of the address of the loop end. Such an instruction packet should not be originally executed, which is read in a cycle in which the loop end is detected. That is, the instruction packet, which is read in the cycle at the detection of the loop end, is read from an invalid memory address. Therefore, in order to execute the instruction (LT 1 ) after the loop back, it is necessary for the processor  500  to read an instruction packet from the instruction memory  600  into the instruction queue  506 . In other word, the reading of the instruction packet for the loop processing is executed in the following cycle to the cycle in which the loop end is detected. Therefore, an unuseful cycle shown in  FIG. 2  by INVALID is generated between the last instruction of the loop processing and the first instruction of the loop processing. As a result, in the data processing apparatus adopting the pipeline processing system of the preceding read, a delay (latency) is generated at the loop back in the execution of the loop processing, which causes an obstruction of speeding up of the processing.  
         [0011]     Japanese Laid Open Patent Application (JP-A-Showa 63-314644) discloses a data processing apparatus for high-speed execution of a loop instruction as a first conventional example. In the first conventional example, when an additional data to a preceding instruction indicates to store an instruction group for a loop in a loop instruction queue, the instruction group for the loop is stored in a loop instruction queue.  
         [0012]     However, the first conventional example is aimed to speed up the execution of the loop instruction by reducing the read time of the instruction group for the loop and any consideration is not made to the latency at the loop back. In addition, the first conventional example stores all the instructions of the instruction group for the loop in the loop instruction queue for the high-speed execution of the loop. Therefore, the size of the hardware increases. Especially, in the processing of multi-loop, the amount of the data to be stored in the loop instruction queue becomes huge.  
         [0013]     Thus, the conventional data processing apparatus of the pipeline processing system cannot prevent the delay at the loop back of the loop processing.  
       SUMMARY OF THE INVENTION  
       [0014]     In an aspect of the present invention, a data processing apparatus adopting a pipeline processing system, includes an instruction memory which store instruction packets; and a processing unit configured to execute the instruction packets sequentially in a pipeline manner. The processing unit includes an instruction queue and a loop speed-up circuit. The instruction packets stored in the instruction queue are executed sequentially by the processing unit. The loop speed-up circuit stores the instruction packets read out from the instruction memory into the instruction queue sequentially, holds the instruction packet containing a loop start address for a loop process, and outputs the held instruction packet to the instruction queue, when a loop process end is detected and the loop process is not circulated for a predetermined number of times.  
         [0015]     Here, the loop speed-up circuit may include a loop instruction queue group; a loop queue flag configured to indicate whether the loop queue flag is valid or invalid; and a selector. The processing-unit determines whether the instruction packet to be executed is a loop start instruction for the loop process, copies the instruction packet containing the loop start address from the instruction queue into the loop instruction queue group when determining that the instruction packet to be executed is the loop start instruction, and sets the loop queue flag to a valid state.  
         [0016]     In this case, the processing unit may control the selector to select and output the instruction packet stored in the loop instruction queue group to the instruction queue, when the loop process end is detected and the loop process is not circulated for a predetermined number of times.  
         [0017]     Also, the processing unit may control the selector to select and output the instruction packet read from the instruction memory to the instruction queue, when the loop process end is not detected or the loop process is circulated for a predetermined number of times.  
         [0018]     Also, the processing unit may control the selector to select and output the instruction packet read from the instruction memory to the instruction queue, when the instruction packet to be executed is an instruction packet for looping out from the loop process.  
         [0019]     Also, the processing unit may set the loop queue flag to an invalid state, when the instruction packet to be executed is an instruction packet for looping out from the loop process or the loop process is circulated for a predetermined number of times. In this case, the processing unit may control the selector to select and output the instruction packet read from the instruction memory to the instruction queue, when the loop queue flag is in the invalid stage, and may control the selector to select and output the instruction packet stored in the loop instruction queue group to the instruction queue, when the loop process end is detected, the loop process is not circulated for a predetermined number of times, and the loop queue flag is in the valid stage.  
         [0020]     Also, the loop instruction queue group may include loop instruction queues of a number less by one than a number of stages necessary to read the instruction packet from the instruction memory into the instruction queue. In this case, the processing unit may control the selector to select and output the stored instruction packet from each of the loop instruction queues of the loop instruction queue group to the instruction queue sequentially.  
         [0021]     In another aspect of the present invention, a data processing method using a pipeline processing system, is achieved by reading instruction packets from an instruction memory into instruction queue through a selector sequentially; by determining whether the instruction packet to be executed is a loop start instruction for a loop process; by copying the instruction packet containing a loop start address from the instruction queue into the loop instruction queue when determining that the instruction packet to be executed is the loop start instruction; by setting the loop queue flag to a valid state; and by executing the instruction packets stored in the instruction queue sequentially.  
         [0022]     Here, the data processing method may be achieved by further determining whether the instruction packet to be executed is an instruction packet for looping out; by setting the loop queue flag to an invalid state, when determining that the instruction packet is the instruction packet for the looping out; and by carrying out the read of the instruction packet from the instruction memory into the instruction queue.  
         [0023]     Also, the data processing method may be achieved by further determining whether the loop process reaches a loop end, when determining that the instruction packet is not the instruction packet for the looping out; and by carrying out the read of the instruction packet from the instruction memory into the instruction queue, when determining that the loop process does not reach the loop end.  
         [0024]     Also, the data processing method may be achieved by further determining whether the loop process is circulated for a predetermined number of times by the loop start instruction, when determining that the loop process reaches the loop end; by setting the loop queue flag to the invalid state, when determining that the loop process is circulated for the predetermined number of times; and by carrying out the read of the instruction packet from the instruction memory into the instruction queue.  
         [0025]     Also, the data processing method may be achieved by further checking whether the loop queue flag is in the valid state, when determining that the loop process is circulated for the predetermined number of times; and by carrying out the read of the instruction packet from the instruction memory into the instruction queue, when determining the loop queue flag is not in the valid state.  
         [0026]     Also, the data processing method may be achieved by further reading the instruction packet stored into the loop instruction queue when determining that the loop queue flag is in the valid state.  
         [0027]     Also, the loop instruction queue group may include loop instruction queues of a number less by one than a number of stages necessary to read the instruction packet from the instruction memory into the instruction queue. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0028]      FIG. 1  is a block diagram showing a configuration of a conventional data processing apparatus;  
         [0029]      FIG. 2  is a sequence diagram showing an operation of the conventional data processing apparatus at a loop back;  
         [0030]      FIG. 3  is a diagram showing instructions from a first instruction (LT 1 ) to a last instruction (LL) to be repeated for loop processing;  
         [0031]      FIG. 4  is a block diagram showing a configuration of a data processing apparatus adopting a pipeline processing system according to a first embodiment of the present invention;  
         [0032]      FIG. 5  is a block diagram showing a configuration of the data processing apparatus in the first embodiment more in detail;  
         [0033]      FIG. 6  is a flowchart showing an operation of the data processing apparatus in the first embodiment;  
         [0034]      FIG. 7  is a sequence diagram showing an operation of the data processing apparatus in the first embodiment at a loop back;  
         [0035]      FIG. 8  is a block diagram showing a configuration of the data processing apparatus according to a second embodiment of the present invention; and  
         [0036]      FIG. 9  is a sequence diagram showing an operation of the data processing apparatus in the second embodiment at the loop back. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0037]     Hereinafter, a data processing apparatus of the present invention will be described with reference to the attached drawings.  
       First Embodiment  
       [0038]      FIG. 4  shows a configuration of the data processing apparatus adopting a pipeline processing system according to the first embodiment of the present invention. As shown in  FIG. 4 , the data processing apparatus in the first embodiment includes a processor  100  and an instruction memory  200 , which are connected through a bus. The processor  100  has a loop speed-up circuit  107 . The processor  100  reads an instruction packet into the instruction queue  106  from the instruction memory  200 . The processor  100  determines whether an instruction to be executed is a loop start instruction, that is, determines whether a loop instruction has been issued. Also, the processor  100  determines whether the processing should be looped out during the execution of the loop instruction.  
         [0039]      FIG. 5  shows a configuration of the data processing apparatus in the first embodiment more in detail. The processor  100  has an instruction queue  106  and the loop speed-up circuit  107 . The loop speed-up circuit  107  includes a loop instruction queue  1071 , a loop queue flag  1072  and a selector  1073 . The loop queue flag  1072  indicates whether the loop instruction queue  1071  is valid or not. The selector  1073  selects one of the instruction packet read from the instruction memory  200  and the instruction packet read from the loop instruction queue  1071  under the control by the processor  100 . When determining that the loop instruction has been issued, the processor  100  reads and stores the instruction packet containing a loop start address from the instruction queue  106  into the loop instruction queue  1071 .  
         [0040]     Next, an operation of the data processing apparatus in the first embodiment will be described below.  FIG. 6  is a flowchart showing the operation of the data processing apparatus in the first embodiment. In an initial state, the selector  1073  selects the instruction memory  200  and the loop queue flag  1072  indicates an invalid state.  
         [0041]     Until the loop instruction is issued, the processor  100  reads the instruction packets from the instruction memory  200  into the instruction queue  106 , and executes the instruction packet read in the instruction queue  106  sequentially (Step S 101 , S 102 /No, S 104 , S 105 /No, S 106 /No, and S 111 ).  
         [0042]     When determining that the loop instruction has not been issued (Step S 102 /No), the processor  100  executes the instruction packet read in the instruction queue  106 . On the other hand, when determining that a loop instruction has been issued (Step S 102 /Yes), the processor  100  reads and stores a first instruction packet for the loop processing from the instruction queue  106  into the loop instruction queue  1071 . At the same time, the processor  100  sets the loop queue flag  1072  to a valid state (Step S 103 ). Then, the processor  100  executes the instruction packet read in the instruction queue  106  (Step S 104 ). In this case, the processor  100  determines whether the instruction to be executed is an instruction for looping out or looping hop (Step S 105 ). When determining that the instruction is the instruction for looping out (Step S 105 /Yes), the processor  100  sets the loop queue flag  1072  to an invalid state (Step S 110 ).  
         [0043]     On the other hand, when determining that the instruction packet to be executed by the processor  100  is not the instruction of looping out (Step S 105 /No), the processor  100  determines whether the processing reached a loop end (Step S 106 ). When determining that the processing does not reach the loop end (Step S 106 /No), the processor  100  reads the instruction packet from the instruction memory  200  into the instruction queue  106  (Step S 111 ). When determining that the processing reaches the loop end (Step S 106 /Yes), the processor  100  determines whether the loop is circulated for the predetermined number of times by the loop instruction. Subsequently, when determining that the loop is circulated for the predetermined number of times (Step S 107 ), the processor  100  sets the loop queue flag  1072  to the invalid state (Step S 110 ). On the other hand, when determining that the loop is circulated for the predetermined number of times (Step S 107 /No), the processor  100  checks whether the loop queue flag  1072  is valid or not (Step S 108 ).  
         [0044]     When the loop queue flag  1072  is valid (Step S 108 /Yes), the processor  100  controls the selector  1073  to select the loop instruction queue  1071 , and then reads the instruction packet stored into the loop instruction queue  1061 , that is, the instruction packet containing the loop start address into the instruction queue  106  (Step S 109 ). After the first instruction packet is read into the instruction queue  106  from the loop instruction queue  1071 , the processor  100  controls the selector  1073  to select the instruction memory  200 . On the other hand, when the loop queue flag  1072  is invalid (Step S 108 /No), the processor  100  reads the instruction packet into the instruction queue  106  from the instruction memory  200  (step S 111 ).  
         [0045]     Thereafter, the processing returns to the step S 102 , and the same steps as the above-mentioned are repeated until the processing is ended.  
         [0046]     In the first embodiment, the processor  100  reads the instruction packet stored in the loop instruction queue  1071  into the instruction queue  106  in the following cycle to a cycle in which the loop end is detected. Therefore, it is possible to read the instruction packet earlier by one cycle, compared with a case of reading from the instruction memory  200  in the following cycle. As a result, the latency cannot be generated at the loop back.  
         [0047]      FIG. 7  shows an operation of the data processing apparatus in the first embodiment at a loop back. As shown in  FIG. 7 , IF 1  and IF 2  indicate that it takes time for two stages for the processor  100  to read the instruction packet from the instruction memory  200  into the instruction queue  106 . Also, DQ indicates a stage in which the instruction packet is allocated, and DE indicates a stage in which the processor  100  decodes the instruction. DP indicates a stage in which the processor  100  changes or updates a data pointer, and EX indicates a stage in which the processor  100  executes the instruction.  
         [0048]     The instruction packet is executed in the order from LE to LL, LT 1 , LT 2  . . . at the loop back. In this example, time for two stages is needed for reading the instruction packet. Therefore, the reading of the instruction packet different from the instruction packet to be read at the stage LT 1  has been started at the detection of the loop end. However, in the present invention, the processor  100  can read the instruction packet to be read at the stage LT 1  from the loop instruction queue  1071  at the detection of the loop end. Therefore, the correct instruction packet can be read for the stage LT 1  at the loop end without generating any latency.  
         [0049]     In case of execution of the loop instruction, the first instruction packet for the loop processing is copied from the instruction queue  106  into the loop instruction queue  107  in the following stage to the stage in which the stage EX of the instruction packet for the loop instruction is ended. Also, the loop queue flag  1072  is set to the valid state. Also, the detection of the loop end is carried out based on an instruction immediately previous to the last instruction for the loop processing by the processor  100 . Therefore, the processor  100  can read the first instruction packet for the loop processing from the loop instruction queue  106  in the following cycle to the cycle in which the loop end is detected.  
         [0050]     In this way, in the data processing apparatus in the first embodiment, the processing is executed by reading the instruction packet stored in the loop instruction queue at the loop back. As a result, the latency is never caused at the loop back.  
       Second Embodiment  
       [0051]     Next, the data processing apparatus according to the second embodiment of the present invention will be described below. In the first embodiment, it takes time for two stages for the processor  100  to read the instruction packet from the instruction memory  200  to the instruction queue  106 . In the second embodiment, a case will be described where it takes time for n stages to read the instruction packet from the instruction memory  200  to the instruction queue  106 .  
         [0052]      FIG. 8  shows a configuration of the data processing apparatus in the second embodiment of the present invention. The data processing apparatus has the same configuration as that of the first embodiment as whole. However, in the second embodiment, a processor  100  includes n- 1  loop instruction queues  1071  ( 10711  to  1071  (n- 1 )).  
         [0053]     Next, an operation of the data processing apparatus in the second embodiment will be described. An operation flow of the data processing apparatus in the second embodiment is almost same as that of the first embodiment. However, at the loop back, the processor  100  controls the selector  1073  to select the loop instruction queue  10711  such that an instruction packet LT 1  is read out and then controls the selector  1073  to select the loop instruction queue  10712 . Through this step, the processor  100  can read an instruction packet LT 2  from the loop instruction queue  10712  at the following cycle. Similarly, the processor  100  controls the selector  1073  to sequentially select the loop instruction queues  10711  to  1071 ( n - 1 ) for every stage such that the instruction packets are read out from the loop instruction queues  10711  to  1071 ( n - 1 ) sequentially. Thus, at the loop back, the instruction packets LT 1  as the first instruction packet for the loop processing to the instruction packet LT(n- 1 ) as the n- 1   th  instruction packet are read from not the instruction memory from  200  but the loop instruction queues  10711  to  1071 ( n - 1 ).  
         [0054]     In this way, the processor  100  can read the instruction packets into the instruction queue  106  without specifying a memory address of the instruction memory  200 . Therefore, the latency cannot be generated in the loop back.  
         [0055]     An operation of the data processing apparatus adopting the pipeline processing system in the second embodiment will be described below. In this example, the reading of the instruction packet from the instruction memory  200  needs the four stages of time.  FIG. 9  shows the operation of the data processing apparatus in the second embodiment at the loop back. As shown in  FIG. 9 , IF 1 , IF 2 , IF 3 , and IF 4  indicate that it takes four stages for the processor  100  to read the instruction packet to the instruction queue  106  from the instruction memory  200 . Also, DQ indicates a stage in which the processor  100  allocates the instruction packet, and DE indicates a stage in which the processor  100  decodes the instruction. DP indicates a stage in which the processor  100  changes or updates a data pointer, and EX indicates a stage in which the processor  100  executes the instruction.  
         [0056]     The instruction packet is executed in the order from LE to LL, LT 1 , LT 2 , LT 3 , LT 4 , . . . at the loop end. In this example, four stages of time are needed for reading. Therefore, the reading of the instruction packet different from the instruction packets to be read in LT 1 , LT 2  and LT 3  has been started at the detection of the loop end. However, in the present invention, the processor  100  can read the instruction packets to be read in LT 1 , LT 2  and LT 3  to the instruction queue  106  from the loop instruction queues  10711 ,  10712  and  10713 , respectively. As a result, the instruction packets in LT 1 , LT 2  and LT 3  can be read without generating the latency at the loop end.  
         [0057]     As mentioned above, the data processing apparatus in the second embodiment reads each of the n- 1  instruction packets that are stored in the loop instruction queues at the loop back and executes the read instruction packets. Therefore, the latency is never generated at the loop back.  
         [0058]     It should be noted that the above-mentioned embodiments are only one example of the present invention, and the present invention is not limited to these examples. For instance, each stage has had the same time length in the above-mentioned embodiments. However, the present invention can be applicable even if the time length is different in each stage. Thus, the present invention can be modified diversely.  
         [0059]     As described above, in the present invention, the data processing apparatus determines whether the instruction packet is a loop start instruction, at the execution of the instruction packet. If the executed instruction packet is the loop start instruction, the instruction packets of the predetermined number are stored in the loop instruction queues from the first instruction of the instruction group for the loop processing. Then, the instruction packets stored in the loop instruction queues are read in the instruction queue sequentially when the loop end is detected. In this way, it is not necessary to read the first instruction packet for the loop processing from the instruction memory at the loop back. Therefore, the latency cannot be generated at the loop back. Thus, according to the present invention, it is possible to provide the data processing apparatus of a pipeline system with no latency at the loop back.