Abstract:
A processor including a microarchitecture adapted for invalidating mapping of at least one logical address to at least one absolute address, includes: at least one translation lookaside buffer (TLB) and a plurality of copies thereof; logic for independent indexing of each copy of the TLB; a plurality of comparators, each comparator associated with a respective output of each TLB set output for each TLB port, wherein each of the comparators is adapted for identifying mappings for invalidation; and logic for invalidating each identified mapping. A method and a computer program product are provided.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    This invention relates to microprocessors that are used in large multi-processor systems, and particularly to microprocessors that implement a virtual memory system using translation lookaside buffers to negotiate between virtual addresses and absolute addresses. 
         [0002]    A number of microprocessors have designs that include at least one translation lookaside buffer (TLB). The TLB is used to associate (i.e., to map) virtual addresses used by processes with addresses of absolute pages resident in memory. Since there is a limited number of absolute pages, the pages are often reused and therefore subject to allocation, reallocation or deallocation as needed. Some microprocessors (or simply “processors”) implement an architecture that supports access key protection. That is, with access key protection, when an absolute page is allocated it is assigned a protection key. The key is saved in the TLB together with the translation mapping (the association between the virtual addresses and the absolute addresses). Sometimes, the absolute address is referred to as a “real address.” 
         [0003]    When access key protection is implemented, each software process requires an access key for accesses to absolute pages. Thus, when an absolute page is reallocated to a different process, the access key must be changed. This may be accomplished through a key changing instruction, such as a Set Storage Key Extended (SSKE) instruction. In order to be effective, the instruction must invalidate the old access keys for all mappings stored in any TLBs before the key update is performed. Although normal processing activities may have reduced copies of any mapping by the time the page is reallocated, it is important that the old access keys be removed or be invalidated. Accordingly, invalidation may be accomplished by broadcasting an Invalidate TLB Key (ITK) command from a master processor executing the SSKE instruction to all processors in the system (each having one or more TLBs) including the targeted absolute address from the process. The actual key changes cannot be completed by the master processor until all processors have completed the ITK. Additionally, these processors also cannot install new TLB mappings for the same address until the SSKE is completed by the master processor where new keys have been assigned. 
         [0004]    In large multiprocessor systems, the SSKE instruction is commonly issued. Long execution delays associated with the SSKE command can be detrimental as associated latency limits overall system performance. One of the component of such delay is the time taken by individual processor to finish its ITK operation. Thus, completing the ITK command quickly is essential to improving SSKE latency and thus improving system performance. 
         [0005]    In greater detail, a basic implementation involves searching the TLB at a rate of one index per cycle. A counter increments from  0  to the maximum TLB array index and all the mappings of a given index (i.e. sets) are compared against the ITK target each cycle. When a successful compare occurs, the appropriate index and set(s) must be invalidated by resetting the valid bit for the targeted key. The counter is stalled while the unset of the valid bit occurs and then continues to increment. The total latency for this implementation of ITK within each processor is highly dependent on the number of indices in the TLB (with some overhead for processing the command). On the other hand, a bigger TLB, which contains more rows or indices, is desired for better performance since that reduces TLB miss rate. The design point needs to be carefully balanced to obtain the best performance. 
         [0006]    Another implementation uses content-addressable memory (CAM) to compare the ITK absolute addresses to all absolute addresses in the TLB. This allows the ITK to complete very quickly by identifying in a single cycle all the TLB mappings that may need to be invalidated. However, the CAM structure consumes a large amount of power and area in the processor core. This is problematic as modern processors have increasing area and power constraints as well as increasing frequency targets. Often times, in order to contain one of these factors, the actual compare width of the CAM will be limited to a partial range, potentially leading to unnecessary invalidations due to completion of imprecise comparisons. These extra invalidations can lead to performance degradation. A solution that meets the frequency, power, and area requirements while decreasing ITK latency as much as possible is required. 
         [0007]    What are needed are techniques for improving performance of invalidation of TLB entries. 
       SUMMARY OF THE INVENTION 
       [0008]    A processor including a microarchitecture adapted for invalidating mapping of at least one logical address to at least one absolute address, includes: at least one translation lookaside buffer (TLB) and a plurality of copies thereof; logic for independent indexing of each copy of the TLB; a plurality of comparators, each comparator associated with a respective output of each TLB set output for each TLB port, wherein each of the comparators is adapted for identifying mappings for invalidation; and logic for invalidating each identified mapping. 
         [0009]    A method for invalidating mapping of at least one logical address to at least one absolute address, includes, for each translation lookaside buffer (TLB), of at least one TLB: initializing a plurality of counters according to a number of entries in the TLB; indexing arrays including absolute address information of the TLB; comparing each indexed TLB entry against a request for invalidation; and at least one of: unsetting at least one validation bit in the TLB; incrementing a counter including index information; identifying a set of TLB entries for invalidation and incrementally unsetting at least one validation bit for each TLB entry in the set. 
         [0010]    A computer program product stored on machine readable media and including machine executable instructions for invalidating mapping of at least one logical address to at least one absolute address, the product including instructions for each translation lookaside buffer (TLB) of at least one TLB: initializing a plurality of counters according to a number of entries in the TLB; indexing arrays including absolute address information of the TLB; comparing each index against a request for invalidation; and at least one of: unsetting at least one validation bit in the TLB; incrementing a counter including index information; identifying a set of TLB entries for invalidation and incrementally unsetting at least one validation bit for each TLB entry in the set. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    Referring now to the drawings wherein like elements are numbered alike in the several figures, wherein: 
           [0012]      FIG. 1  illustrates aspects of a microarchitecture implementing two copies of a translation lookaside buffer (TLB) with two read ports each; 
           [0013]      FIG. 2  illustrates relationships within logical copies of a TLB; 
           [0014]      FIG. 3  is a flow chart exemplifying control logic when there is one write port for each instance of a TLB array. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0015]    Disclosed herein are architecture, methods and apparatus for using multiple copies of a translation lookaside buffer (TLB). The multiple copies can be indexed independently, each with absolute address comparators, to quickly search for mappings that must be invalidated. This further provides for rapid invalidation of mappings, providing for subsequent generation of new access keys. 
         [0016]    To provide perspective, consider that most superscalar microprocessors include a load store unit (LSU) that has two access pipes. The two pipes together naturally include either two copies of the TLB or a single copy that allows two independent indices to be read (i.e., two read ports) to support two parallel accesses to the data cache. The absolute address comparators used for ITK make use of the full width of the absolute address. This helps to avoid invalidating entries that are not targeted by the ITK. The power and area used by the comparators (one per copy per mapping per cycle) is also much less than that used by a CAM (size proportional to the total number of mappings in the TLB). In such embodiments, the total ITK latency is generally less than the basic implementation of searching one index per cycle, and can cut the latency in a half in comparison to a typical design. 
         [0017]    In general, each address translation mapping stored inside the TLB includes a logical address tag, an absolute address, bits indicating validity of the mapping and the corresponding storage key, and other bits including the storage key. A logical TLB can be implemented by physically splitting the TLB into two physical arrays such that one provides a read from one index to get the mappings for comparison while another can contain the valid bits and virtual address bits for a write (invalidate) to another index. Alternatively, a logical TLB can provide a separate read and write port. Similary, these mappings can be duplicated in one or more physical arrays (N) each with one or more read ports (M), where each read port can be indexed independently. Additionally, multiple sets may be read simultaneously at each read port, where the number read corresponds to the set associativity (L) of the TLB. 
         [0018]      FIG. 1  illustrates aspects of an exemplary and non-limiting microarchitecture according to the teachings herein. In this example, the number of physical arrays (N) is two (2), the number of read ports (M) is one (1) and the number of sets being read (L) is two (2). In  FIG. 1 , a processor  1  includes two copies of the TLB (a first copy including items  10  and  16 , a second copy including items  11  and  17 ). Each copy of the TLB (the first TLB copy  10 / 16 , and the second TLB copy  11 / 17 ), include one read port and one write port. In this example, the TLB has 256 entries (Q) with two sets per entry. There are two (N*M=2) counters (an upper counter  5  and a lower counter  6 ), each of which increments through 128 indices (Q/(N*M)=256/2=128). There are also four comparators (N*M*L=2*1*2=4, labeled with reference numerals  8  and  9 ). Each comparator produces a hit signal. OR logic (reference numerals  12  and  13 ) is used to determine which of the hit signals is to be used to write the TLB. The hit signals activate a write mechanism  15  for an appropriate index (a lower counter  6  or an upper counter  5 ) and sets (whichever sets hit, if any). Since there is only one write port and both copies must be written at the same time, a hit from both the lower index and upper index in the same cycle (computed by the AND logic  14 ) will cause a write to the upper index and also cause the upper counter  5  to increment to 255 instead of 127. This dual hit case will increase the latency of ITK to be closer to 256 rather than 128, but is deemed to be a very rare occurrence in a typical system. 
         [0019]    Referring now to  FIG. 2 , this illustration shows aspects of an embodiment where N=2, M=1, and L=2. A first copy of the logical TLB  51  includes physical array A  52  and physical array B  53 . A second copy of the logical TLB  61 , also includes corresponding physical array A  62  and physical array B  63 . Each logical TLB ( 51  and  61 ) generally includes one read port ( 54  and  64 , respectively). Each logical TLB ( 51  and  61 ) also generally includes one write port ( 55  and  65 , respectively). 
         [0020]      FIG. 3  provides a flow chart with an exemplary control algorithm  35 . In this example, the algorithm  35  starts with initializing counters  20 . The algorithm  35  proceeds with indexing and reading TLB array instances that include absolute addresses  21 . Then, comparison of indices and sets is performed against an ITK comparand  22  which is an absolute page address. If there is no match, then index counters are incremented  24 . If the largest counter exceeds the number of TLB entries, then the ITK operation is ended  25 . If not, the algorithm resumes indexing and reading TLB array instances that include absolute addresses  21 . If there is one match, then the algorithm  35  unsets a valid bit in the matching TLB index/sets, and then index counters are incremented  24 . If there is more than one matching index, the algorithm  35  proceeds with unsetting a valid bit in the smallest index matching TLB sets  26 , incrementing the smallest index counter  27 . If the smallest counter exceeds the number of TLB entries, then the ITK operation is ended  25 . If the smallest counter does not exceed the number of TLB entries, then the algorithm  35  proceeds with indexing and reading TLB array instances using the smallest index counter  28 , and then comparing all sets of one index against the ITK comparand  29 . If there is no match from the comparing, then the algorithm  35  continues with incrementing the smallest index counter  27 . If there is one matching index, then the algorithm  35  proceeds with unsetting a valid bit matching in TLB index/sets  30 , and then continues with incrementing the smallest index counter  27 . 
         [0021]    Now with greater detail, consider that in this example, N=2 and M=1. In general, there are N*M*L comparators that determine if the N*M*L absolute addresses read each cycle from the TLB match a target of the ITK. Each of the N*M read ports accesses a subset of the TLB (which has Q indices) on consecutive cycles. Each read port will read at least Q/(N*M) indices such that the total ITK latency is about Q/(N*M) cycles. Whenever one or more of the N*M*L addresses match, the bit indicating validity is unset for those particular index and set combinations in all copies of the TLB. This is performed in parallel with continued reads to other indices. When the number of matches (P) exceeds a total number of simultaneous writes (R) that can be performed on the TLB arrays, the smallest number of simultaneous writes (R) indices are invalidated. The read port that began on the smallest index continues to increment to the largest index instead of stopping after Q/(N*M) indices. This ensures that the indices that could not be invalidated during the initial write of simultaneous write (R) indices are read again and invalidated. As mentioned earlier, in most systems, the mapping targeted by an ITK is usually not in a given TLB. It is also true that there is rarely more than one matching mapping in a TLB. Therefore, it is even less likely that more than R writes will be required in a given cycle (i.e. P&gt;R). On average, the latency of ITK using this method will be about Q/(N*M) cycles because P is usually less than R. 
         [0022]    Technical effects and benefits include a solution that meets the frequency, power, and area requirements while decreasing ITK latency. The solution provides for improving performance of access key issue. 
         [0023]    The flow diagrams depicted herein are just examples. There may be many variations to these diagrams or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order, or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention. 
         [0024]    As described above, the embodiments of the invention may be embodied in the form of computer-implemented processes and apparatuses for practicing those processes. Embodiments of the invention may also be embodied in the form of computer program code containing instructions embodied in tangible media, such as floppy diskettes, CD-ROMs, hard drives, or any other computer-readable storage medium, wherein, when the computer program code is loaded into and executed by a computer, the computer becomes an apparatus for practicing the invention. The present invention can also be embodied in the form of computer program code, for example, whether stored in a storage medium, loaded into and/or executed by a computer, or transmitted over some transmission medium, such as over electrical wiring or cabling, through fiber optics, or via electromagnetic radiation, wherein, when the computer program code is loaded into and executed by a computer, the computer becomes an apparatus for practicing the invention. When implemented on a general-purpose microprocessor, the computer program code segments configure the microprocessor to create specific logic circuits. 
         [0025]    While the invention has been described with reference to exemplary embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims. Moreover, the use of the terms first, second, etc. do not denote any order or importance, but rather the terms first, second, etc. are used to distinguish one element from another.