Abstract:
An apparatus comprising a first stage and a second stage. The first stage may have a first plurality of states connected by a first topology. The second stage may have a second plurality of states connected by a second topology. The second topology may be different from the first topology.

Description:
FIELD OF THE INVENTION 
     The present invention relates to binary data transmissions generally and, more particularly, to a hybrid state machine for frame synchronization in digital transmissions. 
     BACKGROUND OF THE INVENTION 
     Data may be serially transmitted one bit at a time along it, a data transmission path. The serial data can be transmitted in groups of bits called frames. The frames are delimited by synchronization codes that identify the beginning or the end of each frame. The synchronization codes must be identified in the data stream before the significance of the data contained in the frame can be determined. When a synchronization code is identified, a signal can be generated to synchronize a data recovery circuit to the contents of the frame. The synchronization of the data recovery circuit to the frame is frame synchronization. 
     The process of frame synchronization can be divided into an acquisition phase and a tracking phase. Each of the phases can be managed by a synchronization state machine. In the acquisition phase, the synchronization state machine moves to a next state each time a “hit” occurs (e.g., a synchronization code is identified). If a “no-hit” occurs (e.g., a synchronization code is expected but not identified), the synchronization state machine moves to a previous acquisition state if one exists. When a predetermined number of “hits” occur in a row, the data signal is considered acquired. The synchronization state machine can generate a signal indicating that the synchronization of the data signal is acquired. 
     With the synchronization of the data signal acquired, the frame synchronization process switches to the tracking phase. In the tracking phase, the synchronization state machine moves to a next tracking state each time a “no-hit” occurs. If a “hit” occurs, the synchronization state machine moves to a previous tracking state, if one exists. When a predetermined number of “no-hits” occur in a row, tracking of the data signal is considered lost. With the tracking of the data signal lost, the frame synchronization process switches back to the acquisition phase. The synchronization state machine can generate a signal indicating that lock has been lost. 
     Conventional synchronization state machines used for frame synchronization usually have identical topologies for the acquisition phase and the tracking phase. The topology of a synchronization state machine defines the connections between synchronization states. Since the topologies of both phases are identical, conventional synchronization state machines for frame synchronization have either long acquisition and tracking times or short acquisition and tracking times. A synchronization state machine with the smallest mean acquisition time (MAT) is said to have an optimistic acquisition stage. Conversely, a synchronization state machine with the longest MAT is said to have a pessimistic acquisition stage. A similar characterization can be made with respect to the tracking stage. Using the mean time to loose lock (MTLL) as a parameter, a synchronization state machine with the smallest MTLL is said to have a pessimistic tracking stage. A synchronization state machine with the longest MTLL is said to have an optimistic tracking stage. 
     Referring to FIG. 1, a state diagram illustrating a conventional synchronization state machine (SSM)  10  is shown. The synchronization state machine  10  has an acquisition stage  12  and a tracking stage  14 . The acquisition stage  12  has three states  16 ,  18  and  20 . When a “hit” occurs, the acquisition stages moves forward one state (e.g., the arrows marked P A ). When a “no-hit” occurs, the acquisition stage moves back to the first acquisition state  16  (e.g., the arrows marked Q A )). Each time a “no-hit” occurs, the acquisition process must start over. In order for the synchronization state machine  10  to consider the synchronization acquired, 3 “hits” must occur in a row (or a number equal to the number of states in the acquisition stage). The mean acquisition time of the acquisition stage  12  is the longest for a given number of states. The tracking stage  14  uses the same topology as the acquisition stage. When a “hit” occurs during tracking, the tracking phase moves backward to the first tracking state (e.g., the arrows marked P T ). When a “no-hit” occurs during tracking, the tracking stage moves forward one state (e.g., the arrows marked Q T ) Since a single “hit” will start the tracking sequence over, the tracking phase  14  has the longest mean time to lose lock for a given number of states. The synchronization state machine  10  has a pessimistic acquisition stage and an optimistic tracking stage. 
     Referring to FIG. 2, a state diagram illustrating a another conventional synchronization state machine  22  is shown. The synchronization state machine  22  has an acquisition stage  24  and a tracking stage  26 . The acquisition stage  24  has three states  28 ,  30  and  32 . When a “hit” occurs, the acquisition stage moves forward one state (e.g., the arrows marked P A ). When a “no-hit” occurs, the acquisition stage moves backward one state (e.g., the arrows marked Q A ) Since a “no-hit” only moves the acquisition stage  24  back one state, the acquisition stage  24  will have the shortest mean acquisition time for a given number of states. 
     The tracking stage  26  uses the same topology as the acquisition stage. When a “hit” occurs during tracking the tracking stage  26  moves backward one state. When a “no-hit” occurs, the tracking phase moves forward one state. Like the acquisition stage, the tracking stage will have the shortest mean time to lose lock. The synchronization state machine  22  has an optimistic acquisition stage and a pessimistic tracking stage. 
     Ever increasing data transmission rates require that data recovery circuits quickly acquire a lock on the data transmissions and track the transmissions without losing the lock for as long as possible. The synchronization state machine  10  and the synchronization state machine  22  cannot meet these requirements. While the synchronization state machine  10  can track a transmission for the longest period, the synchronization state machine  10  also requires the longest time to acquire a lock on the transmission. Conversely, the synchronization state machine  22  can acquire a lock on a transmission in the shortest time. However, the synchronization state machine  22  also loses the lock in the shortest time. A synchronization state machine is needed that can provide a short mean acquisition time and a long mean time to lose lock. 
     SUMMARY OF THE INVENTION 
     The present invention concerns an apparatus comprising a first stage and a second stage. The first stage may have a first plurality of states connected by a first topology. The second stage may have a second plurality of states connected by a second topology. The second topology may be different for the first topology. 
     The objects, features and advantages of the present invention include providing a hybrid state machine for frame synchronization that may (i) have two different topologies to define connections between synchronization states, (ii) use one topology to minimize means acquisition time and a second topology to maximize mean time to lose lock, and/or (iii) provide added flexibility in trading-off time to recover from a false lock and tracking time. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
     FIG. 1 is a state diagram illustrating a conventional synchronization state machine; 
     FIG. 2 is a state diagram illustrating another conventional synchronization state machine; 
     FIG. 3 is a state diagram illustrating a synchronization state machine according to a preferred embodiment of the present invention; 
     FIG. 4 is a block diagram illustrating the state machine of FIG. 3 in the context of a serial transmission receiver; 
     FIG. 5 is a graph illustrating mean acquisition times of a conventional state machine and the state machine of FIG. 3; and 
     FIG. 6 is a graph illustrating mean acquisition time as a function of normalized frequency deviation. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 3, a state diagram of a synchronization state machine (SSM)  100  is shown in accordance with a preferred embodiment of the present invention. The synchronization state machine  100  generally comprises an acquisition stage  102  and a tracking stage  104 . The acquisition stage  102  may have a plurality of acquisition states  106   a - 106   n . In one example, the acquisition stage  102  may have 3 acquisition states. However, the number of acquisition states may be determined to meet the design criteria of it a particular application. The state  106   a  may be an initial, or start-up, acquisition state. The synchronization state machine  100  generally waits for a “hit” (e.g., the detection of a synchronization code) or a “no-hit” (e.g., the failure to detect a synchronization code) to occur. When a “no-hit” occurs, the synchronization state machine  100  generally moves backward from a current acquisition state to a previous acquisition state (e.g., from a state  106   i  to a state  106   i−1 ) as indicated by the pathways  108   a - 108   n . When a “hit” occurs, the synchronization state machine  100  generally moves forward from the current acquisition state to a next acquisition state (e.g., from a state  106   i  to a state  106   i+1 ) as indicated by the pathways  110   a - 110 (n- 1 ). If a “hit” occurs when the synchronization state machine  100  is in the acquisition state  106   n , the synchronization state machine  100  generally moves to the tracking stage  104 . The synchronization state machine  100  may be configured, in one example, to generate a signal indicating that the tracking stage  104  has been entered. 
     The tracking stage  104  generally comprises a plurality of tracking states  112   a - 112   n . In one example, the tracking stage  104  may have 5 tracking states. However, the number of tracking states may be determined to meet the design criteria of a particular application. The tracking state  112   a  may be an initial tracking state of the tracking stage  104 . When the synchronization state machine  100  is in the acquisition state  106   n , a “hit” will generally move the synchronization state machine  100  into the initial tracking state  112   a . When a “no-hit” occurs during the tracking phase, the synchronization state machine  100  generally moves forward from a current tracking state to a next tracking state (e.g., from a state  112   i  to a state  112   i+1 ) as indicated by the pathways  114   a - 114 (n- 1 ). If a “no-hit” occurs when the synchronization state machine  100  is in the tracking state  112   n , the synchronization state machine  100  generally moves to the initial acquisition state  106   a  (e.g., the pathway  114   n ). The synchronization state machine  100  may be configured, in one example, to generate a signal that indicates that the tracking stage has been exited. When a “hit” occurs during the tracking phase, the synchronization state machine  100  generally moves from the current state to the initial tracking state (e.g., from a state  112   i  to the state  112   a ) as indicated by the pathways  116   a - 116   n.    
     The acquisition stage and the tracking stage generally have different topologies. By using a different topology (e.g., the connections between synchronization states) for each of the two synchronization phases, the state machine  100  generally provides a connection between states that may (i) minimize the mean acquisition time for a given number of acquisition states and (ii) maximize the mean time to lose lock for a given number of tracking states. The number of acquisition states may be chosen to optimize the acquisition of lock while minimizing the probability of false locks. The number of tracking states may be chosen to optimize the trade off between minimizing the time to recover from a false lock and maximizing the mean time to losing lock. The synchronization state machine  100  may be, in one example, a “hybrid” realization of a state machine for synchronization, in which the acquisition stage uses transitions between adjacent states and the tracking stage uses transitions between states and the initial tracking state. 
     The function performed by the state machine  100  may be implemented using a conventional general purpose digital computer programmed according to the teachings of the present specification, as will be apparent to those skilled in the relevant art (s). Appropriate software coding can readily be prepared by skilled programmers based on the teachings of the present disclosure, as will also be apparent to those skilled in the relevant art(s). 
     The present invention may also be implemented by the preparation of ASICs, FPGAs, or by interconnecting an appropriate network of conventional component circuits, as will be readily apparent to those skilled in the art(s). 
     The present invention thus may also include a computer product which may be a storage medium including instructions which can be used to program a computer to perform a process in accordance with the present invention. The storage medium can include, but is not limited to, any type of disk including floppy disk, optical disk, CD-ROM, and magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, Flash memory, magnetic or optical cards, or any type of media suitable for storing electronic instructions. 
     Referring to FIG. 4, a block diagram illustrating an application of the state machine  100  is shown. The state machine  100  is shown implemented as part of a serial data transmission receiver  118 . The state machine  100  may be configured, in one example, to generate a signal (e.g., ACQUIRED) in response to a detection signal (e.g., HIT) and a detection signal (e.g., NO-HIT). The signal ACQUIRED may indicate that the state machine  100  has entered the tracking stage as described in connection with FIG.  3 . 
     The receiver  118  may be connected to a transmitter  120  by a data transmission path  122 . The transmitter generally sends a serial data transmission  124  along the transmission path  122  to the receiver  118 . The serial data transmission  124  is generally dividing into frames. Each frame generally contains a synchronization code  126  and data  128 . 
     The receiver  118  may comprise a synchronization code detector  130  and a data recovery circuit  132 . The synchronization code detector  130  may be configured, in one example, to generate (i) the signal HIT in response to detecting the synchronization code  126  and (ii) the signal NO-HIT in response to not detecting the synchronization code  126 . 
     Noise on the transmission path  122  may make it difficult to detect the synchronization code  126 . The synchronization code detector  130  may be configured to compensate for noise by detecting the synchronization code  126  with less than a perfect match. For example, if the synchronization code  126  has  20  bits, the synchronization code detector  130  may be configured to generate the signal HIT in response to detecting 17 of the 20 bits. The 3 bit error would represent a noise tolerance of the synchronization code detector  130 . 
     The data recovery circuit  132  may be configured, in one example, to recover the data  128  from the serial data transmission  124  in response to the signal ACQUIRED. 
     Referring to FIG. 5, a chart comparing the theoretical mean acquisition time (MAT) of the synchronization state machine  100  and the conventional synchronization state machine  10  is shown. The chart plots mean acquisition time versus frequency offset, normalized with respect to symbol rate. The computations of the MATs are based on an acquisition stage with 3 states and a tolerance (e.g., the maximum number of hard decision decoded bits in error with respect to a unique word of length 20 bits) of 3 bits. Binary phase shift keying (BPSK) and additive white gaussian noise (AWGN) are assumed. 
     Referring to FIG. 6, a chart comparing the MATs of the synchronization state machine  100  and the synchronization state machine  10  as a function of frequency deviation, normalized to baud rate at E s /N o =OdB (2 bits/symbol), is shown. The same general assumptions apply as in connection with FIG.  4 . 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.