Abstract:
A method of manufacturing a metal oxide semiconductor is provided. The method includes forming an offset spacer and a disposable spacer around the offset spacer. Then, forming a plurality of epitaxial layers outside the disposable spacer and removing the disposable spacer. In addition, the method includes forming a plurality of source/drain extension areas in the substrate outside the offset spacer and the epitaxial layers. Because the source/drain extension areas are formed after the selective epitaxial growth process, the thermal of the selective epitaxial growth process does not damage the source/drain extension areas.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a method of manufacturing a metal oxide semiconductor transistor and a complementary metal oxide semiconductor transistor, an more particularly, to a method of manufacturing a metal oxide semiconductor transistor and a complementary metal oxide semiconductor transistor, which forms source/drain extension areas before forming epitaxial layers.  
         [0003]     2. Description of the Prior Art  
         [0004]     Since the sizes of semiconductor components get smaller and smaller, the processes of manufacturing the transistors have improved greatly in forming small size and high quality transistors.  
         [0005]     The method of manufacturing the prior transistor involves first forming a gate, and then a low thermal budget ion implanting process is used to form source and drain extension areas (also called lightly doped drain, LDD) in the silicon substrate and on the two sides of the gate. A spacer is formed besides the gate, and the gate and the spacer serve as a mask for another ion implanting process, so as to form the source/drain. A plurality of contact plugs are formed in order to electrically connect the gate, the source, and the drain of the transistor. The surfaces of the gate and source/drain are formed with silicide by the self-aligned suicide process to improve the Ohmic contact among the gate and the source/drain.  
         [0006]     However, the metal in the metal layer expands into the silicon substrate and consumes the silicon in the source/drain in the self-aligned silicide process. The original crystal lattice of the source/drain is damaged, and the PN junction between the source/drain and the silicon substrate is too narrow, so as to generate leakage. The components lose efficacy in the ultra shallow junction (USL).  
         [0007]     A better solution is utilizing the selective epitaxial growth (SEG) process to stand the source/drain high, so that the silicide and the silicon substrate don&#39;t contact directly, and the source/drain extension areas are maintained. But, the temperature of the SEG process is 690 to 790 centigrade, which causes the source/drain extension areas to be damaged. So, researching methods of manufacturing the source/drain extension areas and the epitaxial layers at the same time is important.  
       SUMMARY OF THE INVENTION  
       [0008]     The present invention relates to a method of manufacturing a MOS to solve the above-mentioned problems.  
         [0009]     The present invention provides a method of manufacturing a metal oxide semiconductor. It provides a substrate, and a gate is formed on the substrate. An offset spacer is formed around the gate, and a disposable spacer is formed around the offset spacer. Then, a plurality of epitaxial layers is formed outside the disposable spacer and on the two sides of the gate. And then, the disposable spacer is removed, and a plurality of source/drain extension areas are formed in the substrate outside the offset spacer and the epitaxial layers.  
         [0010]     The present invention provides a method of manufacturing a complementary metal oxide semiconductor transistor. A substrate is formed. A first gate, and a second gate are formed on the substrate. A first offset spacer is formed around the first gate, and a second offset spacer is formed around the second gate. A disposable spacer is formed around the second offset spacer. A plurality of epitaxial layers are formed on two sides of the second gate. The epitaxial layers are formed outside the disposable spacers. The disposable spacers are removed. And, a plurality of first source/drain extension areas are formed in the substrate and on two sides of the first gate. A plurality of second source/drain extension areas are formed in the substrate and on two sides of the second and second gate.  
         [0011]     The present invention provides a method of manufacturing a complementary metal oxide semiconductor transistor. A substrate is formed. A first gate, and a second gate are formed on the substrate. A first and second offset spacer is formed around the first and second gate. Next, a first and second disposable spacers are formed around the first and second offset spacers. A plurality of epitaxial layers are formed on two sides of the first and second gate. The epitaxial layers are formed outside the first and second disposable spacers. The first and second disposable spacers are removed. And, a plurality of first and second source/drain extension areas are formed in the substrate and on two sides of the first and second gates.  
         [0012]     The source/drain extension areas of the present invention are made after the SEG process, so the high temperature of the SEG process doesn&#39;t damage the source/drain extension areas. The transistor made by the present invention has an ultra shallow junction and the epitaxial layer. The silicide and the substrate of the present invention don&#39;t contact each other, and the source/drain extension areas can be maintained.  
         [0013]     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]     FIGS.  1  to  4  are schematic diagrams of a manufacturing method of a first embodiment in the present invention.  
         [0015]     FIGS.  5  to  8  are schematic diagrams of a manufacturing method of a second embodiment in the present invention.  
         [0016]     FIGS.  9  to  12  are schematic diagrams of a manufacturing method of a third embodiment in the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0017]     Please refer to FIGS.  1  to  4 . FIGS.  1  to  4  are schematic diagrams of a manufacturing method of a first embodiment in the present invention. A semiconductor wafer  100  has a substrate  102 , a gate, and a shallow trench isolation (STI)  111  around the gate  104 . The gate  104  includes a gate insulating layer  106 , a doped poly-silicon layer  108 , and a cap layer  110 .  
         [0018]     And then, a deposition process and an anisotropic etching process are performed to form an offset spacer  112  around the gate  104 . A nitride silicon layer (not shown) is deposited on the substrate  102  and the gate  104 . An anisotropic etching process is performed to form a disposable spacer  114  around the offset spacer  112 .  
         [0019]     Please refer to  FIG. 2 . An etching process is performed and the cap layer  110  of the gate  104  and the disposable spacer  114  serve as etching masks, so as to form recesses  202  in the substrate  102  of the two side of the gate  104 . And then, a selective epitaxial growth (SEG) process is performed to form epitaxial layers  204  in the recesses  202 . The epitaxial layers  204  are made from silicon, SiGe or SiC. Then, the disposable spacer  114  is removed. A light dopant ion implanting process and the laser anneal process are performed to form source/drain extension areas  304  in the substrate  102  of the two sides of the offset spacer  112  and the surface of the epitaxial layer  204 .  
         [0020]     Please refer to  FIG. 4 . A nitride silicon layer (not shown) is on the gate  104 , the offset spacer  112 , the epitaxial layer  204 , and the substrate  102 . An anisotropic etching process is performed to form a main spacer  302  around the offset spacer  112 . Then, the cap layer  110  and the main spacer  302  serve as the ion implanting mask, and an ion implanting process and a laser anneal process are performed, so as to form source/drain  402  in the epitaxial layer  204  outside the main spacer  302 . Furthermore, a self-aligned silicide process is performed to form silicide (not shown) on the gate  104 , and the source/drain  402 . The gate  104  and the source/drain  402  are complete the metal oxide semiconductor (MOS) transistor.  
         [0021]     The first embodiment is not limited to the above method of manufacturing the source/drain  402 . It also can add dopant in the SEG process, so that the epitaxial layer  204  having dopant can be the source/drain directly. In the other way, the epitaxial layer  204  still has no dopant in the SEG process, but an ion implanting process is performed to form the doped epitaxial layer  204  as source/drain before the disposable spacer  114  is removed. As this is well known in the art and thus omitted here.  
         [0022]     Please refer to FIGS.  5  to  8 . FIGS.  5  to  8  are schematic diagrams of a manufacturing method of a second embodiment in the present invention. A semiconductor wafer  500  has a substrate  502 . The substrate  502  has a doped well  503 . The doped well  503  is an N type well in the second embodiment. Gates  504 ,  506  are formed on the substrate  502 , and a STI  511  is around the gates  504 ,  506 , wherein the gate  506  is on the doped well  503 . The gates  504 ,  506  include gate insulating layers  508 ,  514 , doped poly-silicon layers  510 ,  516 , and cap layers  512 ,  518 .  
         [0023]     A nitride silicon deposition process and an anisotropic etching process are performed to form an offset spacer  520  around the gate  504 . And then, a deposition process and an anisotropic etching process are performed to form an offset spacer  522  around the gate  506 . The offset spacer  522  is not made from the nitride silicon, but made from dielectric material. A nitride silicon layer  526  is deposited on the substrate  502  and the gates  504 ,  506 . A pattern hard mask  528  (for example, a pattern photoresist layer) is formed on the nitride silicon layer  526 . The pattern hard mask  528  is on the gate  504  and partial substrate  502 . Next, an anisotropic etching process is performed on the nitride silicon layer  526 , and the pattern hard mask  528  is the etching mask, so as to form a disposable spacer  524  around the offset spacer  522  of the gate  526 . Subsequently, an etching process is performed and the pattern hard mask  528 , the cap layer  518  of the gate  506  and the disposable spacer  524  serve as etching masks, so as to form recesses  530  in the substrate  502  of the two side of the gate  506 . After the recesses  530  are formed, the pattern hard mask  528  is removed.  
         [0024]     Please refer to  FIG. 6 . And then, a selective epitaxial growth (SEG) process is performed to form epitaxial layers  602  in the recesses  530 . The epitaxial layers  602  are made from silicon, SiGe or SiC.  
         [0025]     Please refer to  FIG. 7 . An etching process is performed, and the nitride silicon layer  526 , the offset spacer  520 , and the disposable spacer  524  are removed. Next, a mask (for example, a pattern photoresist layer) (not shown) is utilized to cover the gate  506  and the partial substrate  502 . An ion implanting process and the laser anneal process are performed to form source/drain extension areas  702  in the substrate  502  of the two sides of the gate  502 . Next, the mask on the gate  506  is removed, and another mask (for example a photoresist layer) (not shown) is formed to cover the gate  504  and partial substrate  502 . An ion implanting process and a laser anneal process are performed to form source/drain extension areas  704  in the doped well  503  of the two sides of the gate  506 , and the surface of the epitaxial layers  602 . In the second embodiment, the source/drain extension areas  702  are N type LDDs, and the source/drain extension areas  704  are P type LDDs. Otherwise, the present invention isn&#39;t limited to the source/drain extension areas  702  being made firstly, and then forming the source/drain extension areas  704 . In other variations, the source/drain extension areas  704  are made firstly, and then forms the source/drain extension areas  702 .  
         [0026]     Please refer to  FIG. 8 . A nitride silicon layer (not shown) is on the substrate  502 . An anisotropic etching process is performed to form a sub offset spacer  802  around the gate  504 . A main spacer  804  is formed around the offset spacer  112  of the gate  506 . Next, a mask (for example, a pattern photoresist layer) (not shown) is utilized to cover the gate  506  and the partial substrate  502 . An ion implanting process and a laser anneal process are performed to form source/drain  806  in the substrate  502  outside the two sides of the offset spacer  802  of the gate  504 . Subsequently, the mask on the gate  506  is removed, and another mask (for example, a pattern photoresist layer) (not shown) is formed to cover the gate  504  and the partial substrate  502 . An ion implanting process and a laser anneal process are preformed to form source/drain  808  in the epitaxial layer  602  of the two sides of the main spacer  804  of the gate  506 . The present invention isn&#39;t limited to the source/drain  806  being made firstly, and then forming the source/drain  808 . In other variations, the source/drain  808  is made firstly, and then forms the source/drain  806 . Subsequently, a self-aligned silicide process is performed to silicide (not shown) on the gates  504 ,  506 , and the source/drain  806 ,  808 . The gates  504 ,  506 , and source/drain  806 ,  808  compose the complementary metal oxide semiconductor (CMOS) transistor.  
         [0027]     In the second embodiment, the present invention isn&#39;t limited to the above method of manufacturing the source/drain  808 . The present invention also can add dopant in the SEG process to form the epitaxial layer  602 , and the doped epitaxial layer  602  as source/drain. Otherwise, the epitaxial layer  602  still has no dopant when the SEG process is performed, and an ion implanting process is performed to form doped epitaxial layer  602  as source/drain before the disposable spacer  524  is removed. The PMOS having the epitaxial layer in a CMOS is illustrated by the above manufacture. The present invention also suited for the NMOS having the epitaxial layer in a CMOS.  
         [0028]     Please refer to FIGS.  9  to  12 . FIGS.  9  to  12  are schematic diagrams of a manufacturing method of a third embodiment in the present invention. As  FIG. 9  shows, a semiconductor wafer  900  has a substrate  902 . The substrate  902  has a doped well  903 . The doped well  903  is an N type well in the third embodiment. Gates  904 ,  906  are formed on the substrate  902 , and a STI  911  is around the gates  904 ,  906 , wherein the gate  906  is on the doped well  903 . The gates  904 ,  906  include gate insulating layers  908 ,  914 , doped poly-silicon layers  910 ,  916 , and cap layers  912 ,  918 .  
         [0029]     A deposition process and an anisotropic etching process are performed to form offset spacers  920 ,  922  around the gates  904 ,  906 . And then, a nitride silicon layer (not shown) is deposited on the substrate  902 , and the gates  904 ,  906 . And an anisotropic etching process is performed to form disposable spacers  924 ,  926  outside the offset spacers  920 ,  922  around the gates  904 ,  906 . Please notice, the offset spacers  920 ,  922  and the disposable spacers  924 ,  926  are made by the different etching selectivity materials. Next, a SEG process is performed to form epitaxial layers  1006 ,  1008  in the recesses  1002 ,  1004 . The epitaxial layers  1006 ,  1008  are made from silicon, SiGe or SiC.  
         [0030]     Please refer to  FIG. 11 . An etching process is performed, and the disposable spacers  924 ,  926  are removed. Next, a pattern photoresist layer (not shown) is formed on the gate  906  and the partial substrate  902 . An ion implanting process and the laser anneal process are performed to form source/drain extension areas  1102  in the substrate  902  outside the offset spacer  920  of the two sides of the gate  904 . Next, the above-mentioned photoresist layer is removed, and another pattern photoresist layer is formed to cover the gate  904  and partial substrate  902 . An ion implanting process and a laser anneal process are performed to form source/drain extension areas  1104  in the doped well  903  outside the offset spacer  922  of the two sides of the gate  906 , and the surface of the epitaxial layers  1008 . In the third embodiment, the source/drain extension areas  1102  are N type LDDs, and the source/drain extension areas  1104  are P type LDDs. The sequence of forming the source/drain extension areas  1102 ,  1104  can be exchanged.  
         [0031]     Please refer to  FIG. 12 . A nitride silicon layer (not shown) is on the substrate  902 . An anisotropic etching process is performed to form main spacers  1202 ,  1204 . Next, a pattern photoresist layer (not shown) is formed on the gate  906 , and the partial substrate  902 . An ion implanting process and a laser anneal process are performed to form source/drain  1206  in the epitaxial layers  1006  outside the two sides of the main spacer  1202  of the gate  904 . Subsequently, the above pattern photoresist layer is removed, and another pattern photoresist layer (not shown) is formed to cover the gate  904  and the partial substrate  902 . An ion implanting process and a laser anneal process are preformed to form source/drain  1208  in the epitaxial layer  1008  of the two sides of the main spacer  1204  of the gate  906 . Subsequently, a self-aligned silicide process is performed to silicide (not shown) on the gates  904 ,  906 , and the source/drain  1206 ,  1208 . The gates  904 ,  906 , and source/drain  1206 ,  1208  compose the CMOS transistor.  
         [0032]     In the third embodiment, the present invention isn&#39;t limited to the above method of manufacturing the source/drain  1206 ,  1208 . The present invention also can add dopant in the SEG process to form the epitaxial layers  1006 ,  1008 , and the doped epitaxial layers  1006 ,  1008  as source/drain. Otherwise, the epitaxial layer  1006 ,  1008  still have no dopant when the SEG process is performed, and an ion implanting process is performed to form doped epitaxial layers  1006 ,  1008  as source/drain before the disposable spacers  924 ,  926  is removed. The present invention is not limited to the above method of manufacturing the etched recesses of the PMOS and the NMOS at the same time, the hard mask can change by demand when the SEG process is performed, and the recesses and the epitaxial layer of the PMOS and the NMOS can individually manufacture.  
         [0033]     Please notice, in the above-mentioned embodiment, the materials of the substrate can be silicon, SOI, and/or compounds having Si, Ge, SiGe, and SiC. The gate insulating layer is made by materials having high-K, such as oxide, nitric oxide, nitride, silica, or hafnium silicates. The gate is not limited by the above poly-silicon, and it also can be made by dummy gate or any conductive material, such as metal. Besides, the disposable spacer, and the main spacer are made by OO, ON, OON, ONO, ONONO. The silicide is made by Ti, Co, Ni.  
         [0034]     The source/drain extension areas of the present invention are made after the SEG process, so the high temperature of the SEG process doesn&#39;t damage the source/drain extension areas. The transistor made by the present invention has an ultra shallow junction and the epitaxial layer. The silicide and the substrate of the present invention don&#39;t contact each other, and the source/drain extension areas can be maintained.  
         [0035]     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.