Abstract:
A field-effect transistor (FET) includes a plurality of semiconductor layers, a source electrode and a drain electrode contacting one of the semiconductor layers, a first dielectric layer on a portion of a top semiconductor surface between the source and drain electrodes, a first trench extending through the first dielectric layer and having a bottom located on a top surface or within one of the semiconductor layers, a second dielectric layer lining the first trench and covering a portion of the first dielectric layer, a third dielectric layer over the semiconductor layers, the first dielectric layer, and the second dielectric layer, a second trench extending through the third dielectric layer and having a bottom located in the first trench on the second dielectric layer and extending over a portion of the second dielectric, and a gate electrode filling the second trench.

Description:
STATEMENT REGARDING FEDERAL FUNDING 
     This invention was made under U.S. Government contract DE-AR-0000117. The U.S. Government has certain rights in this invention. 
    
    
     CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is related to U.S. patent application Ser. No. 13/456,039, filed Apr. 25, 2012 and U.S. patent application Ser. No. 14/041,667, filed Sep. 30, 2013, which are incorporated herein as though set forth in full. 
     TECHNICAL FIELD 
     This disclosure relates to III-Nitride field effect transistors (FETs) and in particular to insulated gates for FETs. 
     BACKGROUND 
     III-nitride transistors are promising for high-speed and high-power applications, such as power switches, which may be used for motor drivers and power supplies, among other applications. 
     Many of these applications require the transistor to operate in normally-off mode. Normally-off mode operation can be realized by a number of approaches, but typically at the penalty of higher on-resistance and lower output-current. 
     U.S. patent application Ser. No. 13/456,039, filed Apr. 25, 2012 describes a normally-off III-Nitride field-effect transistor and a method for making a normally-off FET. 
     U.S. patent application Ser. No. 14/041,667, filed Sep. 30, 2013 describes normally-off III-nitride transistors with high threshold-voltage and low on-resistance. 
     High-power applications with normally-off III-nitride transistors need an insulated gate to achieve low leakage current, and an effective passivation dielectric to achieve minimal trapping effects. 
     The best-suited gate insulator and the best-suited passivation dielectric are usually different materials, which may cause processing compatibility problems. For example, plasma-enhanced chemical vapor deposition (PECVD) SiN film is a known good passivation material, while metal organic chemical vapor deposition (MOCVD) AlN is a known good gate insulator material. 
     Unfortunately, the process of forming MOCVD AlN can degrade a PECVD SiN film that is already deposited on the semiconductor. 
     What is needed is a device structure and method of making the device that resolves this process incompatibility and that has a high breakdown voltage and low on resistance. The embodiments of the present disclosure answer these and other needs. 
     SUMMARY 
     In a first embodiment disclosed herein, a field-effect transistor (FET) comprises a plurality of semiconductor layers, a source electrode contacting at least one of the semiconductor layers, a drain electrode contacting at least one of the semiconductor layers, a first dielectric layer covering a portion of semiconductor top surface between the source electrode and the drain electrode, a first trench extending through the first dielectric layer and having a bottom located on a top surface of the semiconductor layers or within one of the semiconductor layers, a second dielectric layer lining the first trench and covering a portion of the first dielectric layer, a third dielectric layer over the semiconductor layers, the first dielectric layer, and the second dielectric layer, a second trench extending through the third dielectric layer and having a bottom located in the first trench on the surface of or within the second dielectric layer, and extending over a portion of the second dielectric on the first dielectric, and a gate electrode filling the second trench. 
     In another embodiment disclosed herein, a method of fabricating a field-effect transistor (FET) comprises forming a plurality of semiconductor layers, forming a source electrode contacting at least one of the semiconductor layers, forming a drain electrode contacting at least one of the semiconductor layers, forming a first dielectric layer covering a portion of semiconductor top surface between the source electrode and the drain electrode, forming a first trench extending through the first dielectric layer and having a bottom located on a top surface of the semiconductor layers or within one of the semiconductor layers, forming a second dielectric layer lining the first trench and covering a portion of the first dielectric layer, forming a third dielectric layer over the semiconductor layers, the first dielectric layer, and the second dielectric layer, forming a second trench extending through the third dielectric layer and having a bottom located in the first trench on the surface of or within the second dielectric layer, and extending over a portion of the second dielectric on the first dielectric, and forming a gate electrode filling the second trench. 
     These and other features and advantages will become further apparent from the detailed description and accompanying figures that follow. In the figures and description, numerals indicate the various features, like numerals referring to like features throughout both the drawings and the description. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a diagram of III-nitride field effect transistor in accordance with the present disclosure; 
         FIG. 2  shows a typical off-state current voltage (IV) characteristic of a FET in accordance with the present disclosure; 
         FIG. 3  shows a typical dynamic current voltage (IV) characteristic of a FET in accordance with the present disclosure; 
         FIG. 4  shows a diagram of another field effect transistor in accordance with the present disclosure; 
         FIG. 5  shows a diagram of yet another field effect transistor in accordance with the present disclosure; 
         FIG. 6  shows a diagram of still another field effect transistor in accordance with the present disclosure; and 
         FIG. 7  shows a diagram of a gate insulator stack in accordance with the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     In the following description, numerous specific details are set forth to clearly describe various specific embodiments disclosed herein. One skilled in the art, however, will understand that the presently claimed invention may be practiced without all of the specific details discussed below. In other instances, well known features have not been described so as not to obscure the invention. 
       FIG. 1  shows a diagram of III-nitride field effect transistor (FET) in accordance with the present disclosure. The FET has a buffer layer  14  formed on a substrate  12 . A channel layer  16  is formed on the buffer layer  14  and a barrier layer  18 , is formed on the channel layer  16 . 
     The substrate  12  material may be silicon (Si), silicon carbide (SiC), sapphire (Al 2 O 3 ), gallium nitride (GaN), or aluminum nitride (AlN). 
     The buffer layer  14  may be a stack of III-Nitride materials grown on the substrate  12  by chemical vapor deposition or molecular beam epitaxy. 
     The channel layer  16  may be a III-Nitride material, such as GaN, grown on the buffer layer  14  by chemical vapor deposition or molecular beam epitaxy. Typically the channel layer  16  is an undoped GaN layer with the thickness ranging from 5 nanometers to a few micrometers. 
     The barrier layer  18  may be 1-30 nanometers thick and may typically be only 5 nm thick. The barrier layer  18  may be AlGaN, with a 25% Al composition. 
     A source electrode  20  and a drain electrode  22  are in contact with the channel layer  16  and extend through the the barrier layer  18 . The source electrode  20  and drain electrode  22  are on opposite ends of the channel layer  16 . 
     A dielectric layer  30 , which may be 1 nm to 100 nm thick and is typically 10 nm thick, and which may be SiN, is deposited by metal organic chemical vapor deposition (MOCVD) on top of the AlGaN barrier layer  18 . In a preferred embodiment the dielectric layer  30  is deposited by MOCVD at a temperature higher than 600 degrees C., and typically at 900 degrees C. 
     The dielectric layer  30  is patterned to be on top of the AlGaN barrier layer  18  in a gate area for a distance of Ls 2 , Ls 1 , Lg, Ld 1  and Ld 2 , as shown in  FIG. 1 , between the source  20  and drain  22 . In the embodiment of  FIG. 1 , the dielectric layer  30  is not in contact with either the source  20  or the drain  22 . 
     A first gate trench  32  with a length of Lg, as shown in  FIG. 1 , is formed through the dielectric layer  30  and the barrier layer  18 . The bottom  38  of the gate trench  32  is located within the channel layer  16 , and extends below the barrier layer  18  and into the channel layer  16  by a vertical distance  36 . This vertical distance  36  is between an interface of the barrier layer  18  and channel layer  16  and the bottom  38  of the gate trench  32 , and is typically between 0 and 10 nanometers (nm). The vertical distance  36  needs to be equal or greater than 0 nm for normally-off operation, and needs to be as small as possible to in order to minimize the on-resistance. 
     A gate insulator  33  is formed in the gate trench  32  and over the dielectric layer  30 . As shown in  FIG. 7 , the gate insulator  33  may include a stack of: a layer of single-crystalline AlN  104  at the bottom of the gate trench  32 , which may be up to 2 nm thick and typically 1 nm thick; a layer of polycrystalline AlN  102  on the single crystalline AlN layer, which is 1 nm to 50 nm thick and typically 10 nm thick; and an insulating layer of SiN  100 , which may be 1 nm to 50 nm thick and typically 10 nm thick, formed on the polycrystalline AlN layer. 
     The single crystalline AlN  104  is preferably grown at a temperature greater than 600 C, and less than 1100 C. A preferred temperature for growing the single crystalline AlN  104  is 900 C. The poly crystalline AlN  102  is preferably grown at a temperature greater than 300 C, and less than 900 C, and a preferred temperature is 600 C. 
     The gate insulator  33  stack makes the FET a normally off FET. Under a positive gate bias the FET has a very low gate leakage, and a high-mobility electron channel is formed at the interface between the barrier layer  18  and the channel layer  16 . 
     The single-crystalline AlN layer  104  of the gate insulator stack  33  provides a high-quality interface for electron transport in the channel layer  16 . Furthermore, the single crystalline AlN layer  104  provides an energy barrier to prevent electron trapping into the polycrystalline AlN layer  102 . The thickness of the single crystalline AlN layer  104  is chosen to be thin enough, typically below 2 nm, to avoid accumulation of channel electrons in absence of a positive gate bias. 
     The SiN layer  100  serves as a blocking layer to leakage paths through grain boundaries of the polycrystalline AlN layer  102 . 
     The gate insulator  33  is formed in the trench  32  and over the dielectric layer  30 . The gate insulator  33  and the dielectric layer  30  are removed in regions beyond the gate area of Ls 2 , Ls 1 , Lg, Ld 1  and Ld 2 , as shown in  FIG. 1 . 
     A passivation dielectric  34 , which may be SiN and have a thickness of 10 nm to 500 nm with a typical thickness of 100 nm, is deposited by plasma-enhanced chemical vapor deposition (PECVD) over the barrier layer  18  between the source  20  and the drain  22 , over the gate insulator  33  in the trench  32 , and over the gate insulator  33  on the dielectric layer  30 . In a preferred embodiment the passivation dielectric  34  is deposited by PECVD at a temperature lower than 500 degrees C., and typically at 300 degrees C. 
     A second gate trench  40  is formed in passivation dielectric  34  by etching and may have a length of the sum of Lg, Ls 1  and Ld 1 , as shown in  FIG. 1 . The second gate trench  40  extends to the gate insulator  33  in the gate trench  32  and overlaps the gate insulator  33  on the dielectric layer  30  by a distance Ls 1  and Ld 1 , as shown in  FIG. 1 . The gate insulator  33  on the dielectric layer  30  for distance Ls 2  and Ld 2  on either side of Ls 1  and Ld 1 , as shown in  FIG. 1 , remains covered by the passivation layer  34 . 
     A gate electrode  24  is formed within the second gate trench  40  and may extend over the passivation layer  34  partially toward the source electrode  20  by a distance Ls 3 , as shown in  FIG. 1 , and partially toward the drain electrode  22  by a distance Ld 3 , as shown in  FIG. 1 , to form an integrated gate field-plate. The gate electrode  24  may be any suitable metal. 
     As shown in  FIG. 1 , two types of dielectric are in contact with the AlGaN barrier layer  18  in the gate to drain region. The two types of dielectric are: a dielectric layer  30 , which may be a SiN layer deposited by metal organic chemical vapor deposition (MOCVD), and a passivation dielectric layer  34 , which may be a SiN layer deposited by plasma-enhanced chemical vapor deposition (PECVD). 
     Dielectric layer  30  is deposited prior to the deposition of the gate insulator layer stack  33 . The dielectric layer  30  serves as a etch stop layer for the patterning of the gate insulator layer stack  33 , and dielectric layer  30  can survive subsequent high-temperature steps, such as the deposition of gate insulator layer stack  33  and the alloying of source  20  and drain  22  contacts. 
     Dielectric layer  34  serves the purpose of mitigating trapping behaviors. Dielectric layer  34  is deposited after the deposition of gate insulator layer stack  33 , to avoid the impact of high-temperature processing on the properties of dielectric layer  34 . 
       FIG. 2  shows a typical off-state current voltage (IV) characteristic of a FET in accordance with the present disclosure. As shown in  FIG. 2 , the off-state current is very low even at 600 volts, demonstrating the breakdown voltage is greater than 600 volts. 
       FIG. 3  shows a typical dynamic current voltage (IV) characteristic of a FET in accordance with the present disclosure, and the graph demonstrates that the on-resistance for a FET is only minimally degraded. 
       FIG. 4  shows a diagram of another field effect transistor in accordance with the present disclosure. The embodiment of  FIG. 4  is similar to the embodiment of  FIG. 1 . However, in the embodiment of  FIG. 4  the dielectric layer  30 , which may be 1 nm to 100 nm thick and is typically 10 nm thick, and which may be SiN, is deposited by metal organic chemical vapor deposition (MOCVD) on top of the AlGaN barrier layer  18  and extends from the source  20  to the drain  22 , as shown in  FIG. 4 , rather than just in the gate area as shown in  FIG. 1 . 
       FIG. 5  shows a diagram of yet another field effect transistor in accordance with the present disclosure. The embodiment of  FIG. 5  is similar to the embodiment of  FIG. 4 . However, in the embodiment of  FIG. 5  the gate insulator stack  33  extends from the source  20  to the drain  22 , as shown in  FIG. 5 , rather than just in the gate area as shown in  FIG. 4 . 
       FIG. 6  shows a diagram of still another field effect transistor in accordance with the present disclosure. The embodiment of  FIG. 6  is similar to the embodiment of  FIG. 1 . However, in the embodiment of  FIG. 6  the bottom  38  of the gate trench  32  is located within the barrier layer  18 , and does not extend below the barrier layer  18  into the channel layer  16 . The gate trench  32  may also be only to the top surface of the barrier layer  18 . Variations of the embodiment of  FIG. 6  may also include an embodiment where the dielectric layer  30  extends from the source  20  to the drain  22 , and another embodiment where both the dielectric layer  30  and the gate insulator stand extend from the source  20  to the drain  22 . 
     Having now described the invention in accordance with the requirements of the patent statutes, those skilled in this art will understand how to make changes and modifications to the present invention to meet their specific requirements or conditions. Such changes and modifications may be made without departing from the scope and spirit of the invention as disclosed herein. 
     The foregoing Detailed Description of exemplary and preferred embodiments is presented for purposes of illustration and disclosure in accordance with the requirements of the law. It is not intended to be exhaustive nor to limit the invention to the precise form(s) described, but only to enable others skilled in the art to understand how the invention may be suited for a particular use or implementation. The possibility of modifications and variations will be apparent to practitioners skilled in the art. No limitation is intended by the description of exemplary embodiments which may have included tolerances, feature dimensions, specific operating conditions, engineering specifications, or the like, and which may vary between implementations or with changes to the state of the art, and no limitation should be implied therefrom. Applicant has made this disclosure with respect to the current state of the art, but also contemplates advancements and that adaptations in the future may take into consideration of those advancements, namely in accordance with the then current state of the art. It is intended that the scope of the invention be defined by the Claims as written and equivalents as applicable. Reference to a claim element in the singular is not intended to mean “one and only one” unless explicitly so stated. Moreover, no element, component, nor method or process step in this disclosure is intended to be dedicated to the public regardless of whether the element, component, or step is explicitly recited in the Claims. No claim element herein is to be construed under the provisions of 35 U.S.C. Sec. 112, sixth paragraph, unless the element is expressly recited using the phrase “means for . . . ” and no method or process step herein is to be construed under those provisions unless the step, or steps, are expressly recited using the phrase “comprising the step(s) of . . . . ”