Abstract:
A design structure including design data describing a semiconductor structure. The semiconductor structure includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip is on top of and bonded to the second semiconductor chip. The first and second semiconductor chips include a first and a second electric nodes. The second semiconductor chip further includes a first comparing circuit. The semiconductor structure further includes a first coupling via electrically connecting the first electric node of the first semiconductor chip to the first comparing circuit of the second semiconductor chip. The first comparing circuit is capable of (i) receiving an input signal from the second electric node directly, (ii) receiving an input signal from the first electric node indirectly through the first coupling via, and (iii) asserting a first mismatch signal in response to the input signals from the first and second electric nodes being different.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application is a Continuation In Part of copending U.S. patent application Ser. No. 11/277,306, filed Mar. 23, 2006. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The invention is related to design structures, and more specifically to design structures for semiconductor structures with error detection and correction. 
       BACKGROUND OF THE INVENTION 
       [0003]    In the prior art, error detection and correction for semiconductor devices can be made by using identical semiconductor chips on a same printed wire board in which the identical semiconductor chips are connected together via the printed wires on the board. However the number of signals that can be compared (checked) is limited by the number of pins of the semiconductor chip. Therefore, there is a need for a semiconductor chip (and method for operating the same) in which the number of signals that can be compared is not limited by the number of the pins on the semiconductor chip. 
       SUMMARY OF THE INVENTION 
       [0004]    The present invention provides a semiconductor structure, comprising (a) a first semiconductor chip and a second semiconductor chip, wherein the first semiconductor chip is on top of and bonded to the second semiconductor chip, wherein the first semiconductor chip comprises a first electric node, wherein the second semiconductor chip comprises a second electric node, and wherein the second semiconductor chip further comprises a first comparing circuit; and (b) a first coupling via electrically connecting the first electric node of the first semiconductor chip to the first comparing circuit of the second semiconductor chip, wherein the first comparing circuit is capable of: (i) receiving an input signal from the first electric node indirectly through the first coupling via, (ii) receiving an input signal from the second electric node directly, and (iii) asserting a first mismatch signal in response to the input signals from the first and second electric nodes being different. 
         [0005]    The present invention also provides a semiconductor structure, comprising (a) a first semiconductor chip, a second semiconductor chip, and a first error checking layer, wherein the first error checking layer is sandwiched between and bonded to the first and second semiconductor chips, wherein the first semiconductor chip comprises a first electric node, wherein the second semiconductor chip comprises a second electric node, wherein the first error checking layer comprises a first comparing circuit; (b) a first coupling via electrically connecting the first electric node of the first semiconductor chip to the first comparing circuit of the first error checking layer; and (c) a second coupling via electrically connecting the second electric node of the second semiconductor chip to the first comparing circuit of the first error checking layer, wherein the first comparing circuit is capable of: (i) receiving an input signal from the first electric node indirectly through the first coupling via, (ii) receiving an input signal from the second electric node indirectly through the second coupling via, and (iii) asserting a first mismatch signal in response to the input signals from the first and second electric nodes being different. 
         [0006]    The present invention provides a semiconductor structure operation method, comprising providing a semiconductor structure which includes: (a) a first semiconductor chip and a second semiconductor chip, wherein the first semiconductor chip is on top of and bonded to the second semiconductor chip, wherein the first semiconductor chip comprises a first electric node, wherein the second semiconductor chip comprises a second electric node, and wherein the second semiconductor chip further comprises a first comparing circuit, and (b) a first coupling via electrically connecting the first electric node of the first semiconductor chip to the first comparing circuit of the second semiconductor chip; and using the first comparing circuit to: (a) receive an input from the second electric node directly, (b) receive an input from the first electric node indirectly through the first coupling via, and (c) assert a first mismatch signal in response to signals on the first and second electric nodes being different 
         [0007]    The present invention provides the structure (and method for operating the same) in which the number of signals that can be compared are not limited by the number of the pins on the semiconductor chip. 
         [0008]    The present invention provides a design structure for a semiconductor chip in which the number of signals that can be compared is not limited by the number of the pins on the semiconductor chip. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]      FIGS. 1A-1C  illustrate a first digital system, in accordance with embodiments of the present invention. 
           [0010]      FIG. 2  illustrates a cross section view of a second digital system, in accordance with embodiments of the present invention. 
           [0011]      FIGS. 3A-3B  illustrates a cross section view of a third digital system, in accordance with embodiments of the present invention. 
           [0012]      FIG. 4  illustrates a cross section view of the fourth digital system, in accordance with embodiments of the present invention. 
           [0013]      FIG. 5  is a flow diagram of a design process used in semiconductor design, manufacture, and/or test. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0014]      FIGS. 1A-1C  illustrate a first digital system  1000 , in accordance with embodiments of the present invention. In one embodiment, more specifically,  FIG. 1A  illustrates a cross section view of the first digital system  1000  comprising a first semiconductor chip  1000   a  and a second semiconductor chip  1000   b . The first semiconductor chip  1000   a  is on top and bonded to the second semiconductor chip  1000   b . Illustratively, the first semiconductor chip  1000   a  comprises a first error checking circuit  1010   a  and a first functional circuit  1020   a . Similarly, the second semiconductor chip  1000   b  comprises a second error checking circuit  1010   b  and a second functional circuit  1020   b . In one embodiment, components of the first error checking circuit  1010   a  are dispersed among components of the first functional circuit  1020   a . Similarly, components of the second error checking circuit  1010   b  are dispersed among components of the second functional circuit  1020   b . However, for simplicity, the first and second error checking circuits  1010   a  and  1010   b  are shown separate from the first and second functional circuits  1020   a  and  1020   b . In one embodiment, coupling vias  1030  are formed between the first and second error checking circuits  1010   a  and  1010   b  to transmit checking logic signals between the first and second error checking circuits  1010   a  and  1010   b.    
         [0015]      FIG. 1B  illustrates a first embodiment of the first and second error checking circuits  1010   a  and  1010   b  and the coupling vias  1030  of  FIG. 1A . In one embodiment, more specifically, the first error checking circuit  1010   a  comprises a first NAND circuit  1040   a , four exclusive-NOR circuits  1050   a ,  1060   a ,  1070   a  and  1080   a , two OR circuits  1100   a  and  1110   a , a first local error latch  1090   a , and a first master error latch  1120   a . Similarly, in one embodiment, the second error checking circuit  1010   b  comprises a second NAND circuit  1040   b , four exclusive-NOR circuits  1050   b ,  1060   b ,  1070   b  and  1080   b , two OR circuits  1100   b  and  1110   b , a second local error latch  1090   b  and a second master error latch  1120   b . The first and second error checking circuits  1010   a  and  1010   b  are used to identify any mismatch between any pair of four functional latches pairs  1053   a  and  1053   b ,  1063   a  and  1063   b ,  1073   a  and  1073   b ,  1083   a  and  1083   b . In one embodiment, the coupling vias  1030  comprise ten coupling vias  1051 ,  1052 ,  1061 ,  1062 ,  1071 ,  1072 ,  1081 ,  1082 ,  1111 , and  1112 . 
         [0016]    In one embodiment, the exclusive-NOR circuits  1050   a ,  1060   a ,  1070   a , and  1080   a  receive as inputs (i) from the functional latches  1053   a ,  1063   a ,  1073   a , and  1083   a  directly and (ii) from the functional latches  1053   b ,  1063   b ,  1073   b , and  1083   b  indirectly through the vias  1051 ,  1061 ,  1071 , and  1081 , respectively. Similarly, the exclusive-NOR circuits  1050   b ,  1060   b ,  1070   b , and  1080   b  receive as inputs (i) from the functional latches  1053   b ,  1063   b ,  1073   b , and  1083   b  directly and (ii) from the functional latches  1053   a ,  1063   a ,  1073   a , and  1083   a  indirectly through the vias  1052 ,  1062 ,  1072 , and  1082 , respectively. 
         [0017]    In one embodiment, outputs of the first and second NAND circuits  1040   a  and  1040   b  are connected to the first and second local error latches  1090   a  and  1090   b , respectively. 
         [0018]    In one embodiment, the OR circuits  1100   a  and  1100   b  have only 3 inputs, but it should be understood that there may be any number of inputs from any number of local error latches. In one embodiment, the OR-circuit  1110   a  receives as inputs (i) from the output of the OR-circuit  1100   a  directly and (ii) from the output of the OR-circuit  1100   b  indirectly through the via  1112 . Similarly, the OR-circuit  1110   b  receives as inputs (i) from the output of the OR-circuit  1100   b  directly and (ii) from the output of the OR-circuit  1100   a  indirectly through the via  1111 . 
         [0019]    In one embodiment, the first and the second functional circuits  1020   a  and  1020   b  ( FIG. 1A ) are functionally identical and are operated in lock step which means they are controlled by a same clock signal synchronously. As a result, the contents of the functional latch pairs  1053   a  and  1053   b ,  1063   a  and  1063   b ,  1073   a  and  1073   b ,  1083   a  and  1083   b  are supposed to be the same. If a mismatch in any of the four functional latch pairs occurs, then a 1 will be generated and sent to the first and second local error latches  1090   a  and  1090   b . The contents of the first and second local error latches  1090   a  and  1090   b  will be sent respectively to the first and second master error latches  1120   a  and  1120   b  to indicate the mismatch. 
         [0020]      FIG. 1C  illustrates a second embodiment of the first and second error checking circuits  1010   a  and  1010   b  and the coupling vias  1030  of  FIG. 1A . In one embodiment, more specifically, the first error checking circuit  1010   a  comprises a first NAND circuit  1130   a , two exclusive-NOR circuits  1140  and  1150 , three OR circuits  1160   a ,  1180   a  and  1190   a , a first local error latch  1070   a  and a first master error latch  1200   a . Similarly, in one embodiment, the second error checking circuit  1010   b  comprises a second NAND circuit  1130   b , two exclusive-NOR circuits  1210  and  1220 , three OR circuits  1160   b ,  1180   b  and  1190   b , a second local error latch  1070   b  and a second master error latch  1200   b . The first and second error checking circuits  1010   a  and  1010   b  are used to identify any mismatch between any pair of four functional latches pairs  1141   a  and  1141   b ,  1151   a  and  1151   b ,  1211   a  and  1211   b ,  1221   a  and  1221   b . In one embodiment, the coupling vias  1030  comprise eight coupling vias  1212 ,  1222 ,  1142 ,  1152 ,  1161 ,  1162 ,  1191 , and  1192 . 
         [0021]    In one embodiment, the exclusive-NOR circuits  1140  and  1150  receive as inputs (i) from the functional latches  1141   a  and  1151   a  directly and (ii) from the functional latches  1141   b  and  1151   b  indirectly through the vias  1142  and  1152 , respectively. Similarly, the exclusive-NOR circuits  1210  and  1220  receive as inputs (i) from the functional latches  1211   b  and  1221   b  directly and (ii) from the functional latches  1211   a  and  1221   a  indirectly through the vias  1212  and  1222 , respectively. 
         [0022]    In one embodiment, the OR circuit  1160   a  receives as inputs (i) from the output of the NAND circuit  1130   a  directly and (ii) from the output of the NAND circuit  1130   b  indirectly through the via  1162 . Similarly, the OR circuit  1160   b  receives as inputs (i) from the output of the NAND circuit  1130   b  directly and (ii) from the output of the NAND circuit  1130   a  indirectly through the via  1161 . In one embodiment, outputs of the OR circuits  1160   a  and  1160   b  are connected to the first and second local error latches  1170   a  and  1170   b , respectively. For simplicity, in  FIG. 1C , the OR circuits  1180   a  and  1180   b  have only 3 inputs, but it should be understood that there may be any number of inputs from any number of local error latches. The OR circuit  1190   a  receives as inputs (i) from the output of the OR circuit  1180   a  directly and (ii) from the output of the OR circuit  1180   b  indirectly through the via  1192 . Similarly, the OR circuit  1190   b  receives as inputs (i) from the output of the OR circuit  1180   b  directly and (ii) from the output of the OR circuit  1180   a  indirectly through the via  1191 . 
         [0023]    In one embodiment, the first and second functional circuits  1020   a  and  1020   b  ( FIG. 1A ) are functionally identical and are operated in lock step, which means they are controlled by a same clock signal synchronously. As a result, the contents of the functional latch pairs  1141   a  and  1141   b ,  1151   a  and  1151   b ,  1211   a  and  1211   b ,  1221   a  and  1221   b  are supposed to be the same. If a mismatch in any of the four functional latch pairs occurs, then a 1 will be generated and sent to the first or second local error latch  1170   a  or  1170   b . The contents of the first and second local error latches  1170   a  and  1170   b  will be sent respectively to the first and second master error latches  1200   a  and  1200   b  to indicate the mismatch. 
         [0024]      FIG. 2  illustrates a second digital system  2000 , in accordance with embodiments of the present invention. In one embodiment, more specifically,  FIG. 2  illustrates a cross section view of the second digital system  2000  which comprises a first semiconductor chip  2000   a , a second semiconductor chip  2000   b , and a third semiconductor chip  2000   c . The first semiconductor chip  2000   a  is on top and bonded to the second semiconductor chip  2000   b . The second semiconductor chip  2000   b  is on top and bonded to the third semiconductor chip  2000   c . Illustratively, the first semiconductor chip  2000   a  comprises a first error checking circuit  2010   a  and a first functional circuit  2020   a . Similarly, the second semiconductor chip  2000   b  comprises a second error checking circuit  2010   b  and a second functional circuit  2020   b . Similarly, the third semiconductor chip  2000   c  comprises a third error checking circuit  2010   c , and a third functional circuit  2020   c . In one embodiment, components of the first error checking circuit  2010   a  are dispersed among components of the first functional circuit  2020   a . Similarly, components of the second error checking circuit  2010   b  are dispersed among components of the second functional circuit  2020   b . Similarly, components of the third error checking circuit  2010   c  are dispersed among components of the third functional circuit  2020   c . However, for simplicity, the first, second and third error checking circuits  2010   a ,  2010   b , and  2010   c  are shown separate from the first, second and third functional circuits  2020   a ,  2020   b , and  2020   c . In one embodiment, coupling vias  2030  are formed between the first and second error checking circuits  2020   a  and  2020   b , coupling vias  2040  are formed between the second and third error checking circuits  2020   b  and  2020   c  to transmit checking logic signals among the first, second, and third error checking circuits  2010   a ,  2010   b , and  2010   c.    
         [0025]    In one embodiment, the first, second, and third error checking circuits  2010   a ,  2010   b , and  2010   c  of the second digital system  2000  have components similar to those of the first and second error checking circuits  1010   a  and  1010   b  of the first digital system  1000  ( FIG. 1A ). 
         [0026]    In one embodiment, the first, second, and third functional circuits  2020   a ,  2020   b , and  2010   c  are functionally identical and are operated in lock step which means they are controlled by a same clock signal synchronously. As a result, the contents of any three corresponding functional latches in the first, second and third functional circuits  2020   a ,  2020   b , and  2020   c  are supposed to be the same. If a mismatch in the three functional latches occurs, then a 1 will be generated and sent to the master error latches (not shown) on the first, second, and third error checking circuits  2010   a ,  2010   b , and  2010   c  to indicate the mismatch. In one embodiment, the second error checking circuit  2010   b  comprises a conventional voting logic (not shown), which generates an output equal to the majority content of the three functional latches. For example, if two of the three functional latches (not shown) contain a 1 and the third functional latch (not shown) contains a 0, then the conventional voting logic (not shown) will generate a 1, which is the majority content of the three latches. This value can then be used to correct the value in the miscomparing latch, allowing computation to proceed without further intervention. 
         [0027]      FIGS. 3A-3B  illustrates a third digital system  3000 , in accordance with embodiments of the present invention. In one embodiment, more specifically,  FIG. 3A  illustrates a cross section view of the third digital system  3000  which comprises a first semiconductor chip  3030   a , a second semiconductor chip  3030   b , and an error checking layer  3040  sandwiched between the first and second functional circuits  3030   a  and  3030   b . Illustratively, the error checking layer  3040  comprises all error-checking functions needed for error detection of the entire third digital system  3000 . In one embodiment, coupling vias  3010  are formed between the first semiconductor chip  3030   a  and the error checking layer  3040 , coupling vias  3020  are formed between the second semiconductor chip  3030   b  and the error checking layer  3040  to transmit checking logic signals from the first and second functional circuits  3031  and  3032  to the error checking circuit  3041 . 
         [0028]      FIG. 3B  illustrates a third embodiment of the first and second functional circuits  3030   a  and  3030   b , the error checking layer  3040 , and the coupling vias  3010  and  3020  of  FIG. 3A . In one embodiment, more specifically, the first semiconductor chip  3030   a  comprises four functional latches  3051   a ,  3061   a ,  3071   a , and  3081   a . Similarly, the second semiconductor chip  3030   b  comprises four functional latches  3051   b ,  3061   b ,  3071   b , and  3081   b . The error checking layer  3040  comprises a NAND circuit  3090 , four exclusive-NOR circuits  3050 ,  3060 ,  3070  and  3080 , an OR circuit  3100 , and a master error latch  3110 . The error checking layer  3040  is used to identify any mismatch between any pair of four functional latches pairs  3051   a  and  3051   b ,  3061   a  and  3061   b ,  3071   a  and  3071   b ,  3081   a  and  3081   b . In one embodiment, the coupling vias  3010  comprise four coupling vias  3053 ,  3063 ,  3073 , and  3083 , whereas the coupling vias  3020  comprise four coupling vias  3054 ,  3064 ,  3074 , and  3084 . 
         [0029]    In one embodiment, the exclusive-NOR circuits  3050 ,  3060 ,  3070 , and  3080  receive as inputs (i) from the functional latches  3051   a ,  3061   a ,  3071   a , and  3081   a  indirectly through the via  3053 ,  3063 ,  3073 , and  3083  and (ii) from the functional latches  3051   b ,  3061   b ,  3071   b , and  3081   b  indirectly through the via  3054 ,  3064 ,  3074 , and  3084 , respectively. The outputs of the exclusive-NOR circuits  3050 ,  3060 ,  3070 , and  3080  are the inputs of the NAND circuit  3090 . The OR circuit  3100  receives as inputs from many NAND circuits which are similar to the NAND circuit  3090 . The output of the OR circuit  3100  is connected to the master error latch  3110  whose output (not shown) is reported back to the first and second semiconductor chips  3030   a  and  3030   b , using coupling vias (not shown). 
         [0030]    In one embodiment, the first semiconductor chip  3030   a  and the second semiconductor chip  3030   b  are functionally identical and are operated in lock step which means they are controlled by a same clock signal synchronously. As a result, the contents of the functional latch pairs  3051   a  and  3051   b ,  3061   a  and  3061   b ,  3071   a  and  3071   b ,  3081   a  and  3082   b  are supposed to be the same. If a mismatch in any of the four functional latch pairs occurs, then a 1 will be generated and sent to the master error latch  3110  to indicate the mismatch. 
         [0031]      FIG. 4  illustrates a fourth digital system  4000 , in accordance with embodiments of the present invention. In one embodiment, more specifically,  FIG. 4  illustrates a cross section view of the fourth digital system  4000  which comprises a first semiconductor chip  4010   a , a second semiconductor chip  4010   b , a third semiconductor chip  4010   c , a first error checking layer  4020   a  sandwiched between the first and second functional circuits  4010   a  and  4010   b , and a second error checking layer  4020   b  sandwiched between the second and third functional circuits  4010   b  and  4010   c . Illustratively, the first and second checking logic layers  4020   a  and  4020   b  comprise all the error checking circuits needed for error detection of the entire fourth digital system  4000 . In one embodiment, coupling vias  4030 ,  4040  and  4050 ,  4060  are formed between the first semiconductor chip  4010   a  and the first error checking layer  4020   a , the first error checking layer  4020   a  and second semiconductor chip  4010   b , the second semiconductor chip  4010   b  and the second error checking layer  4020   b , the second error checking layer  4020   b  and third semiconductor chip  4010   c , respectively to transmit checking logic signals among the first, second, and third functional circuits  4010   a ,  4010   b , and  4010   c  and the first and second checking logic layer  4020   a , and  4020   b.    
         [0032]    In one embodiment, the first and second error checking logic layers  4020   a  and  4020   b  of the fourth digital system  4000  have components similar to those of the error checking layer  3040  of the third digital system  3000  ( FIG. 3A ). 
         [0033]    In one embodiment, the first, second, and third semiconductor chips  4010   a ,  4010   b , and  4010   c  are functionally identical and are operated in lock step which means they are controlled by a same clock signal synchronously. As a result, the contents of the corresponding functional latches in the first, second and third functional circuits  4011 ,  4012 , and  4013  are supposed to be the same. If a mismatch in any of the three functional latch triplet occurs, then a 1 will be generated and sent to the master error latches (not shown) in the first and the second error checking circuits  4020   a  and  4020   b  to indicate the mismatch. In one embodiment, the first error checking layer comprises a conventional voting logic (not shown), which generates an output equal to the majority content of the three functional latches. For example, if two of the three functional latches (not shown) contain a 1 and the third functional latch (not shown) contains a 0, then the conventional voting logic will generate a 1, which is the majority content of the three latches. 
         [0034]    In the embodiments described above, 2-way and 3-way redundancies for error checking and correction are shown and described. In general, N-way redundancies for error checking and correction can be done in a similar manner, wherein N is an integer greater than 2. In the higher redundancy cases, the voting method previously described is only one of several methods of error correction that could be implemented within the structures described here. 
         [0035]      FIG. 5  shows a block diagram of an exemplary design flow  900  used for example, in semiconductor IC logic design, simulation, test, layout, and manufacture. Design flow  900  includes processes and mechanisms for processing design structures or devices to generate logically or otherwise functionally equivalent representations of the design structures and/or devices described above and shown in  FIGS. 1A-1C ,  2 ,  3 A- 3 B, and  4 . The design structures processed and/or generated by design flow  900  may be encoded on machine-readable transmission or storage media to include data and/or instructions that when executed or otherwise processed on a data processing system generate a logically, structurally, mechanically, or otherwise functionally equivalent representation of hardware components, circuits, devices, or systems. Design flow  900  may vary depending on the type of representation being designed. For example, a design flow  900  for building an application specific IC (ASIC) may differ from a design flow  900  for designing a standard component or from a design flow  900  for instantiating the design into a programmable array, for example a programmable gate array (PGA) or a field programmable gate array (FPGA) offered by Altera® Inc. or Xilinx® Inc. 
         [0036]      FIG. 5  illustrates multiple such design structures including an input design structure  920  that is preferably processed by a design process  910 . In one embodiment, the design structure  920  comprises design data used in a design process and comprising information describing an embodiment of the invention with respect to the circuits as shown in  FIGS. 1A-1C ,  2 ,  3 A- 3 B, and  4 . The design data in the form of schematics or HDL, a hardware-description language (e.g., Verilog, VHDL, C, etc.) may be embodied on one or more machine readable media. For example, design structure  920  may be a text file, numerical data or a graphical representation of an embodiment of the invention as shown in  FIGS. 1A-1C ,  2 ,  3 A- 3 B, and  4 . Design structure  920  may be a logical simulation design structure generated and processed by design process  910  to produce a logically equivalent functional representation of a hardware device. Design structure  920  may also or alternatively comprise data and/or program instructions that when processed by design process  910 , generate a functional representation of the physical structure of a hardware device. Whether representing functional and/or structural design features, design structure  920  may be generated using electronic computer-aided design (ECAD) such as implemented by a core developer/designer. When encoded on a machine-readable data transmission, gate array, or storage medium, design structure  920  may be accessed and processed by one or more hardware and/or software modules within design process  910  to simulate or otherwise functionally represent an electronic component, circuit, electronic or logic module, apparatus, device, or system such as those shown in  FIGS. 1A-1C ,  2 ,  3 A- 3 B, and  4 . As such, design structure  920  may comprise files or other data structures including human and/or machine-readable source code, compiled structures, and computer-executable code structures that when processed by a design or simulation data processing system, functionally simulate or otherwise represent circuits or other levels of hardware logic design. Such data structures may include hardware-description language (HDL) design entities or other data structures conforming to and/or compatible with lower-level HDL design languages such as Verilog and VHDL, and/or higher level design languages such as C or C++. 
         [0037]    Design process  910  preferably employs and incorporates hardware and/or software modules for synthesizing, translating, or otherwise processing a design/simulation functional equivalent of the components, circuits, devices, or logic structures shown in  FIGS. 1A-1C ,  2 ,  3 A- 3 B, and  4  to generate a netlist  980  which may contain design structures such as design structure  920 . Netlist  980  may comprise, for example, compiled or otherwise processed data structures representing a list of wires, discrete components, logic gates, control circuits, I/O devices, models, etc. that describes the connections to other elements and circuits in an integrated circuit design. Netlist  980  may be synthesized using an iterative process in which netlist  980  is resynthesized one or more times depending on design specifications and parameters for the device. As with other design structure types described herein, netlist  980  may be recorded on a machine-readable data storage medium or programmed into a programmable gate array. The medium may be a non-volatile storage medium such as a magnetic or optical disk drive, a programmable gate array, a compact flash, or other flash memory. Additionally, or in the alternative, the medium may be a system or cache memory, buffer space, or electrically or optically conductive devices and materials on which data packets may be transmitted and intermediately stored via the Internet, or other networking suitable means. 
         [0038]    Design process  910  may include hardware and software modules for processing a variety of input data structure types including netlist  980 . Such data structure types may reside, for example, within library elements  930  and include a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.). The data structure types may further include design specifications  940 , characterization data  950 , verification data  960 , design rules  970 , and test data files  985  which may include input test patterns, output test results, and other testing information. Design process  910  may further include, for example, standard mechanical design processes such as stress analysis, thermal analysis, mechanical event simulation, process simulation for operations such as casting, molding, and die press forming, etc. One of ordinary skill in the art of mechanical design can appreciate the extent of possible mechanical design tools and applications used in design process  910  without deviating from the scope and spirit of the invention. Design process  910  may also include modules for performing standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc. 
         [0039]    Design process  910  employs and incorporates logic and physical design tools such as HDL compilers and simulation model build tools to process design structure  920  together with some or all of the depicted supporting data structures along with any additional mechanical design or data (if applicable), to generate a second design structure  990  comprising second design data embodied on a storage medium in a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design structures). In one embodiment, the second design data resides on a storage medium or programmable gate array in a data format used for the exchange of data of mechanical devices and structures (e.g. information stored in a IGES, DXF, Parasolid XT, JT, DRG, or any other suitable format for storing or rendering such mechanical design structures). Similar to design structure  920 , design structure  990  preferably comprises one or more files, data structures, or other computer-encoded data or instructions that reside on transmission or data storage media and that when processed by an ECAD system generate a logically or otherwise functionally equivalent form of one or more of the embodiments of the invention shown in  FIGS. 1A-1C ,  2 ,  3 A- 3 B, and  4 . In one embodiment, design structure  990  may comprise a compiled, executable HDL simulation model that functionally simulates the devices shown in  FIGS. 1A-1C ,  2 ,  3 A- 3 B, and  4 . 
         [0040]    Design structure  990  may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures). Design structure  990  may comprise information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a manufacturer or other designer/developer to produce a device or structure as described above and shown in  FIGS. 1A-1C ,  2 ,  3 A- 3 B, and  4 . Design structure  990  may then proceed to a stage  995  where, for example, design structure  990 : proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc. 
         [0041]    While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.