Abstract:
The present invention provides integrated circuit devices that include a semiconductor substrate having a semiconductor region of first conductivity type therein extending adjacent the surface of the substrate. The device further includes an electrically insulating layer with a contact hole in it that exposes the semiconductor region of first conductivity type on the surface of the semiconductor substrate. The device still further includes a poly-Si 1-x Ge x  conductive plug of first conductivity type that extends in the contact hole and is electrically connected to the semiconductor region of first conductivity type is provided. Related methods of fabricating integrated circuit devices are also provided.

Description:
RELATED APPLICATION 
   This application is a divisional application of U.S. patent application Ser. No. 10/012,116, filed on Nov. 13, 2001, now U.S. Pat. No. 6,828,616 and claims priority from Korean Application No. 2001-2171, filed Jan. 15, 2001, the disclosures of which are hereby incorporated herein by reference as if set forth in their entirety. 

   FIELD OF THE INVENTION 
   The present invention relates to semiconductor devices and methods of fabricating the same and, more particularly, to semiconductor devices that use doped conductive plugs as interconnects and methods of fabricating the same. 
   BACKGROUND OF THE INVENTION 
   As semiconductor devices continue to decrease in size, the elements that make up these devices, such as channel lengths, intervals between active areas, via holes, metal studs, contact sizes, and the widths of metal interconnection also decrease. Due to the miniaturization of semiconductor devices including capacitors, such as a dynamic random access memory (DRAM), methods for forming self aligned contacts (SACs) are being used due to lack of a misalignment margin in a photolithography process. For example, a buried contact pad and a direct contact pad may be formed between word lines of a DRAM using a method for forming a SAC, and a buried contact plug may be formed between bit lines of a DRAM using the same method for forming a SAC. Thus, the lower electrode of the capacitor may be formed so that it is in contact with the buried contact plug and connected to the impurity region within the active area through the buried contact pad and the buried contact plug. 
   Typically, the direct contact pad, the buried contact pad, and the buried contact plug are formed using a doped polycrystalline silicon layer. Doped polycrystalline silicon layers have superior filling ability and stability in the presence of heat which makes them a desirable material for the elements of a semiconductor device. Furthermore, the doped polycrystalline silicon layer has an advantage over other materials in that a contact resistance of the semiconductor device may be reduced due to activation of a dopant by a high temperature annealing process. However, the high temperature annealing process may have negative effects on other elements of the device. 
   For example, a buried contact pad and a direct contact pad that are in direct contact with an n +  type impurity region of a semiconductor substrate may be provided. If the buried contact pad is formed using a doped polycrystalline silicon layer and the annealing process is used to activate the dopant, impurities of the doped polycrystalline silicon layer may be diffused within the semiconductor substrate, thus possibly causing the electrical characteristics of a transistor to deteriorate. 
   By way of further example, a p +  type impurity region within the semiconductor device that is not in direct contact with metal interconnection on the semiconductor substrate may be provided in order to overcome an increased height difference between the impurity region and the metal interconnection. Instead, after a metal stud connected to the p +  type impurity region is formed, the metal stud is in contact with the metal interconnection instead of the p +  type impurity region. The metal stud may be formed during a middle step when the bit lines of the cell area are formed. 
   In this case, a titanium silicide (Ti-silicide) layer is typically formed on the lower portion or the upper portion of the metal stud as a barrier metal layer for an ohmic contact. A high temperature annealing process may be accompanied by a step of forming the buried contact plug using the doped polycrystalline silicon layer, a step of activating the polycrystalline silicon layer dopant, and a step of forming a dielectric layer forming the capacitor, which are performed after the metal stud is formed. Impurities of the p+ type impurity region, for example, boron, may be diffused into the Ti-silicide layer by this high temperature annealing process such that a titanium-boron compound is formed which may result in an increased contact resistance. 
   SUMMARY OF THE INVENTION 
   Embodiments of the present invention provide an integrated circuit device that include a semiconductor substrate having a semiconductor region of first conductivity type extending adjacent the surface of the substrate. The device further includes an electrically insulating layer with a contact hole therein that exposes the semiconductor region of first conductivity type on the surface of the semiconductor substrate. The device still further includes a poly-Si 1-x Ge x  conductive plug of first conductivity type that extends in the contact hole and is electrically connected to the semiconductor region of first conductivity type. 
   Further aspects of embodiments of the present invention include a germanium mole fraction x that is in a range between about 0.1 and about 0.5. Additional embodiments of the present invention include a germanium mole fraction x that is less than about 0.35 but greater than 0.1. In further embodiments of the present invention the germanium mole fraction x within the poly-Si 1-x Ge x  conductive is greater than about 0.25 and less than 0.35. In some embodiments of the present invention the poly-Si 1-x Ge x  conductive plug may be doped with impurities, for example, phosphorus (P), arsenic (As) and antimony (Sb). 
   In further embodiments of the present invention an integrated circuit memory device is provided that includes a semiconductor substrate. A memory cell access transistor adjacent the surface of the semiconductor substrate includes a word line on the surface and source and drain regions of first conductivity type in the semiconductor substrate. A first interlayer insulating layer is provided on the semiconductor substrate and has a first opening therein that extends opposite the source region. A first poly-Si 1-x Ge x  conductive plug of first conductivity type extends in the first opening and is electrically connected to the source region. An integrated circuit capacitor extends on the semiconductor substrate and has an electrode electrically connected to the first poly-Si 1-x Ge x  conductive plug. 
   In still further embodiments of the present invention the integrated circuit memory device may include a second interlayer insulating layer on the first interlayer insulating layer that has a second opening therein that extends opposite the first poly-Si 1-x Ge x  conductive plug. A second poly-Si 1-x Ge x  conductive plug of first conductivity type extends in the second opening and is electrically connected to the poly-Si 1-x Ge x  conductive plug. The germanium mole fraction x within the second poly-Si 1-x Ge x  conductive plug may be unequal to the germanium mole fraction x within the first poly-Si 1-x Ge x  conductive plug. 
   Further embodiments of the integrated circuit may further include an integrated circuit capacitor that extends on the second interlayer insulating layer and has a lower electrode electrically connected to the second poly-Si 1-x Ge x  conductive plug. The lower electrode may directly contact the second poly-Si 1-x Ge x  conductive plug. 
   Some additional embodiments of the present invention provide an integrated circuit device that includes a semiconductor substrate and an electrically insulating layer on the semiconductor substrate. The electrically insulating layer has a contact hole in it and a poly-Si 1-x Ge x  conductive plug of first conductivity type that extends into the contact hole is further included. 
   While the present invention is described above primarily with reference to devices, methods of fabricating the devices is also provided. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a cross-sectional view cut in a bit line direction illustrating semiconductor devices having doped polycrystalline silicon-germanium layers according to embodiments of the present invention; 
       FIG. 2  is a cross-sectional view cut in a gate line direction illustrating semiconductor devices having doped polycrystalline silicon-germanium layers according to embodiments of the present invention; 
       FIG. 3  is a graph illustrating dopant activation with respect to a germanium mole fraction of a doped polycrystalline silicon-germanium layer according to embodiments of the present invention; 
       FIG. 4  is a graph illustrating hole electron mobility with respect to a germanium mole fraction of a doped polycrystalline silicon-germanium layer according to embodiments of the present invention; 
       FIGS. 5A through 7A  are cross-sectional views cut in the bit line direction illustrating methods of fabricating semiconductor devices having doped polycrystalline silicon-germanium layers according to embodiments of the present invention; 
       FIGS. 5B through 7B  are cross-sectional views cut in the gate line direction illustrating a methods of fabricating semiconductor devices having doped polycrystalline silicon-germanium layers according to embodiments of the present invention; 
       FIG. 8  is a graph illustrating the resistance between a metal stud and a p +  type impurity region in a peripheral circuit area with respect to annealing temperature and time after forming doped polycrystalline silicon-germanium layers according to embodiments of the present invention; and 
       FIG. 9  is a graph illustrating resistance between a contact pad and an n type impurity region in a cell area with respect to annealing temperature and time after forming doped polycrystalline silicon-germanium layers according to embodiments of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The present invention now will be described more fully with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Like reference numerals refer to like elements throughout. 
   Embodiments of the present invention will now be described in detail below with reference to  FIGS. 1 through 9 , which illustrate various embodiments of the present invention and various processes of fabricating embodiments of the present invention. A semiconductor device is provided having a doped polycrystalline silicon-germanium layer. As described in detail below, a contact pad that contacts the impurity regions of the semiconductor substrate and a buried contact plug connecting the contact pad to the lower electrodes of the capacitor are both formed using the polycrystalline silicon-germanium layer doped with n-type impurities, thus allowing the activation of the dopant to be performed at a lower temperature relative to conventional devices. The present invention may also prevent property deterioration of the semiconductor device, such as increased resistance in parts of the device that are susceptible to heat. 
     FIG. 1  is a cross-sectional view cut in a bit line direction illustrating semiconductor devices having doped polycrystalline silicon-germanium layers according to embodiments of the present invention.  FIG. 2  is a cross-sectional view cut in a gate line direction illustrating semiconductor devices having doped polycrystalline silicon-germanium layers according to embodiments of the present invention. Thus, the bit line is not shown in  FIG. 1  and the gate line is not shown in  FIG. 2 . 
   Now referring to  FIGS. 1 and 2 , semiconductor devices according to embodiments of the present invention will now be described in detail. As seen in  FIG. 1 , a semiconductor substrate  100  is provided. An active area  102  is defined within the semiconductor substrate  100  by an isolation area  101 . The isolation area  101  is illustrated in  FIGS. 1 and 2  as a recess, but as will be understood by those having skill in the art, it may also be made using a local oxidation of silicon (LOCOS) method. In the active area  102 , there are impurity regions of predetermined conductivity types corresponding to a source and a drain region of a transistor (not shown). The transistor may be a p-channel or an n-channel transistor. If the transistor is a p-channel transistor, the impurity regions have a high concentration of p-type impurities. If, on the other hand, the transistor is an n-channel transistor, the impurity regions have a high concentration of n-type impurities. N-channel transistors are typically used in the cell area of dynamic random access memory (DRAM). 
   A plurality of gate lines  110  are provided on the surface of the semiconductor substrate  100  separated from each other. Each of the gate lines  110  are in a stack structure in which a gate capping layer  113  is on a gate conductive layer  112 , which is on a gate insulating layer  111 . A optional metal silicide layer (not shown) can be further disposed between the gate conductive layer  112  and the gate capping layer  113  for reducing resistance. Gate spacers  115  are provided on the sidewalls of the gate lines  110 . 
   As further illustrated in  FIGS. 1 and 2 , a conductive contact pad  120  and a first electrically insulating layer  131  are provided in the space between the gate spacers  115 . The contact pad  120  may be a buried contact pad or a direct contact pad. The buried contact pad is used for connecting the impurity regions of the semiconductor substrate  100  to a lower electrode of a capacitor. A direct contact pad is used for connecting the impurity regions of the semiconductor substrate  100  to a bit line. 
   The contact pad  120  includes a polycrystalline silicon-germanium layer doped with impurities of a predetermined conductivity type. The conductivity type of the doped impurities is typically the same as that of the impurity regions of the semiconductor substrate  100 . For example, the contact pad  120  connected to the impurity regions of the n-channel transistor may be formed using the polycrystalline silicon-germanium layer doped with the n-type impurities. The n-type impurities may be phosphorous (P), arsenic (As) or antimony (Sb). Polycrystalline silicon-germanium has a lower melting point than silicon, thus, deposition, crystallization, growth of grains, and activation of impurities are typically performed at relatively low temperatures. 
   Now referring to  FIG. 3 , a graph illustrating dopant activation with respect to a germanium mole fraction of doped polycrystalline silicon-germanium layers according to embodiments of the present invention will be discussed. The doped polycrystalline silicon-germanium layer measured in  FIG. 3 , of which the dopant is phosphorous (P), is annealed at a temperature of about 900° C. for about 40 minutes and has a thickness of about 0.3 μm. The injection concentration of the dopant is about 4×10 15  cm 2 , and the injection energy of the dopant is about 60 KeV. 
   As shown in  FIG. 3 , if the germanium mole fraction is less than 0.5, dopant activation of the doped polycrystalline silicon-germanium layer is enhanced about 12-40% compared with the conventional doped polycrystalline silicon layer. When the germanium mole fraction is about 0.35, the dopant activation typically reaches a maximum value of 40%. Therefore, the dopant can be sufficiently activated at a relatively low temperature by controlling the germanium mole fraction. 
   Referring to  FIG. 4 , a graph illustrating the hole electron mobility with respect to a germanium mole fraction of doped polycrystalline silicon-germanium layers according to embodiments of the present invention will now be discussed in detail. The doped polycrystalline silicon-germanium layer measured in  FIG. 4 , of which the dopant is phosphorous (P), is annealed at a temperature about 900° C. for about 40 minutes and has a thickness of about 0.3 μm. The injection concentration of the dopant is about 4×10 15  cm 2 , and the injection energy of the dopant is about 60 KeV. 
   As shown in  FIG. 4 , if the germanium mole fraction is less than 0.5, the hole electron mobility of the doped polycrystalline silicon-germanium layer measured by the hall measurement is about 20 cm 2 /V s . Preferably, when the germanium mole fraction is about 0.35, the hole electron mobility reaches the maximum value, 37 cm 2 /V s . 
   Referring again to  FIGS. 1 and 2 , a second electrically insulating layer  132  is provided on the contact pad  120  and the first electrically insulating layer  131 . A plurality of bit lines  150  are provided on the second electrically insulating layer  132  separated from each other. Each of the bit lines  150  is formed so that its lengthwise direction crosses that of the gate lines  110 . The bit lines  150  is formed as a stack structure in which a bit line conductive layer  152  is on a barrier metal layer  151  and the bit line conductive layer  152  is on a bit line capping layer  153 . An optional metal silicide layer (not shown) may be further provided between the bit line conductive layer  152  and the bit line capping layer  153  for reducing resistance. A plurality of bit line spacers  155  are provided on the sidewalls of the bit lines  150 . 
   A buried contact plug  140  is formed on the buried contact pad, which is the contact pad  120  connected to the lower electrode of the capacitor through a third electrically insulating layer  133  and the second electrically insulating layer  132  between the bit line spacers  155 . In other words, a buried contact plug  140  adjacent to another buried contact plug  140  is electrically separated by the second electrically insulating layer  132 , the third electrically insulating layer  133 , and the bit line spacers  155 . The buried contact plug  140  includes a conductive material, preferably a doped polycrystalline silicon-germanium layer. The conductivity type of the doped impurities is typically the same as that of the majority carrier within the impurity regions of the semiconductor substrate  100 . For example, in the case of the buried contact plug  140  connected to the impurity regions of the n-channel transistor, a polycrystalline silicon-germanium layer doped with the n-type impurities is used. The n-type impurities may be phosphorous (P), arsenic (As), or antimony (Sb). As described above, the polycrystalline silicon-germanium has a lower melting point than silicon, so deposition, crystallization, growth of grains, and activation of impurities are typically performed at a relatively low temperature. 
   Lower electrodes  161  of a capacitor  160  are provided on the buried contact plug  140 . The lower electrodes  161  of the capacitor  160  are separated by an insulating layer  170 . A barrier metal layer (not shown) may optionally be provided between the buried contact plug  140  and the lower electrode  161 . The lower electrode  161  of the capacitor  160  is connected to the impurity regions of the semiconductor substrate  100  through the buried contact plug  140  and the buried contact pad among the contact pad  120 . Upper electrodes  163  are provided on a dielectric layer  162 , and the dielectric layer is provided on the lower electrodes  161  of the capacitor  160 . 
     FIGS. 5A through 7A , and  5 B through  7 B are cross-sectional views illustrating methods for fabricating a semiconductor device having doped polycrystalline silicon-germanium layers according to embodiments of the present invention.  FIGS. 5A through 7A  are cross-sectional views cut in the bit line direction, and  FIGS. 5B through 7B  are cross-sectional views cut in the gate line direction. 
   Now referring to  FIGS. 5A and 5B , methods of fabricating a semiconductor device according to embodiments of the present invention will be discussed in detail. The isolation area  101  is formed within the semiconductor substrate  100  defining the active area  102 . The isolation area  101  is illustrated as a recess in the Figures, but as will be understood by those having skill in the art, it can be also made using a general LOCOS method. A plurality of gate lines  110  are formed on the surface of the semiconductor substrate  100 . The gate lines  110  are formed as stack structures in which the gate insulating layer  111 , the gate conductive layer  112 , and the gate capping layer  113  are sequentially deposited. An optional metal silicide layer (not shown) may be further formed between the gate conductive layer  112  and the gate capping layer  113  for reducing resistance. A plurality of gate spacers  115  are formed on the sidewalls of the gate lines  110 . The gate insulating layer  111  is formed using a silicon oxide layer, the gate conductive layer  112  is formed from a polycrystalline silicon layer, and the gate capping layer  113  and the gate spacers  115  are formed from a silicon nitride layer. Although the gate insulating layer  111 , the gate conductive layer  112 , the gate capping layer  113  and the gate spacers  115  are described as being formed of particular materials, the present invention should not be limited to this configuration. It will be understood that any material that would provide the same functionality may be used. 
   Impurity regions (not shown) are formed in the active area  102  by injecting either n-type or p-type impurity ions. For example, if the transistor is a p-channel transistor, the impurity regions have a high concentration of p-type impurities. Alternatively, if the transistor is an n-channel transistor, the impurity regions have a high concentration of n-type impurities. Typically, an n-channel transistor is used in the cell area of DRAM. These impurity regions define the source and drain regions of the transistor. 
   A first electrically insulating layer  131  is formed to cover the gate lines  110  and the gate spacers  115  on the surface of the semiconductor substrate  100 . The first electrically insulating layer  131  is formed from a material layer having a high etch selectivity with respect to the gate capping layer  113  and the gate spacers  115 . For example, if the gate capping layer  113  and the gate spacers  115  are formed from silicon nitride layer, then the first electrically insulating layer  131  can be formed from a silicon oxide layer. A portion of the first electrically insulating layer  131  is removed to form contact holes that expose a portion of the semiconductor substrate  100  by using a predetermined mask layer pattern and a high etch selectivity with respect to the gate capping layer  113  and the gate spacers  115 . A contact pad  120  is formed by depositing the doped polycrystalline silicon-germanium layer in the contact holes formed in the electrically insulating layer  131 . The doped polycrystalline silicon-germanium layer may be formed by a chemical vapor deposition (CVD) method. 
   The conductivity type of the doped impurities within the contact pad  120  formed from the polycrystalline silicon-germanium layer is preferably the same as that of the majority carrier within the impurity regions of the semiconductor substrate  100 . For example, the contact pad  120  connected to the impurity regions of the n-channel transistor is typically formed using the polycrystalline silicon-germanium layer doped with the n-type impurities. The n-type impurities may be, for example, phosphorous (P), arsenic (As), or antimony (Sb). As described above, since the polycrystalline silicon-germanium has a lower melting point than silicon, deposition, crystallization, growth of grains, and activation of impurities are typically performed at relatively low temperatures. The injected dopant is activated by annealing the implant. The annealing process includes a first annealing process performed at a temperature lower than about 750° C., and a rapid thermal process (RTP) performed at a temperature lower than about 900° C. 
   Now referring to  FIGS. 6A and 6B , a second electrically insulating layer  132  is formed on the contact pad  120  and the first electrically insulating layer  131 . A plurality of bit lines  150  are formed on the second electrically insulating layer  132  separated from each other. Each of the bit lines  150  is formed so that its lengthwise direction crosses that of the gate lines  110 , and is formed as a stack structure in which the barrier metal layer  151 , the bit line conductive layer  152 , and the bit line capping layer  153  are sequentially deposited. An optional metal silicide layer (not shown) can be further formed between the bit line conductive layer  152  and the bit line capping layer  153  to reduce the resistance. The bit line spacers  115  are formed on the sidewalls of the bit lines  150 . The barrier metal layer  151  is formed from a single layer or double layer of a titanium layer and a titanium nitride layer. The bit line conductive layer  152  is formed from a polycrystalline silicon-germanium layer and the bit line capping layer  153  and the bit line spacers  155  are formed from a silicon nitride layer. Although the layers are described as being formed of particular materials, the present invention should not be limited to these materials. It will be understood by those having skill in the art that other materials providing the same functionality could be substituted for the materials described above. 
   A third electrically insulating layer  133  is formed to cover a portion of the surface of the second electrically insulating layer  132 , the bit lines  150  and the bit line spacers  155 . The second electrically insulating layer  132  and the third electrically insulating layer  133  are formed from a material layer having a high etch selectivity with respect to the bit line capping layer  153  and the bit line spacers  155 . For example, if the bit line capping layer  153  and the bit line spacers  155  are formed from a silicon nitride layer, then the second electrically insulating layer  132  and the third electrically insulating layer  133  can be formed from a silicon oxide layer. Portions of the second electrically insulating layer  132  and the third electrically insulating layer  133  are removed to form contact holes exposing a portion of the surface of the contact pad  120  by using a predetermined mask layer pattern and a high etch selectivity with respect to the bit line capping layer  153  and the bit line spacers  155 . The contact pad  120  exposed here is the buried contact pad to be connected to the lower electrode of the capacitor. The buried contact plug  140 , i.e. poly-Si 1-x Ge x  conductive plug, is formed by depositing the doped polycrystalline silicon-germanium layer within the contact holes in the second and third electrically insulating layer  132  and  133 . The doped polycrystalline silicon-germanium layer may be formed by the CVD method. 
   The conductivity type of the impurities doped within the buried contact plug  140  formed from the polycrystalline silicon-germanium layer is preferably the same as that for the majority carrier within the impurity regions of the semiconductor substrate  100 . For example, the buried contact plug  140  connected to the contact pad  120  connected to the impurity regions of the n-channel transistor is formed using a doped polycrystalline silicon-germanium layer. The n-type impurities, for example, may be phosphorous (P), arsenic (As), or antimony (Sb). As described above, since the polycrystalline silicon-germanium has a lower melting point than silicon, deposition, crystallization, growth of grains, and activation of impurities are typically performed at relatively low temperatures. After the buried contact plug  140  is formed, the injected dopant is activated by annealing process. The annealing process includes a first annealing process performed at a temperature lower than 750° C., and an RTP performed at a temperature lower than 900° C. 
   Referring to  FIGS. 7A and 7B , an insulating layer  170  is formed on the whole surface of the structure of  FIGS. 6A and 6B . The insulating layer  170  is patterned to form contact holes that expose the surface of the buried contact plug  140 . A conductive layer is formed on the buried contact plug  140  and on the surface of the insulating layer  170 . A plurality of capacitor lower electrodes  161  separated using a general node separation method are formed on the conductive layer. A dielectric layer  162  is then formed on the capacitor lower electrodes  161 . Capacitor upper electrodes ( 163  of  FIGS. 1 and 2 ) are formed on the dielectric layer  162 . 
   Now referring to  FIG. 8 , a graph illustrating the resistance between a metal stud and p +  type impurity regions in a peripheral circuit area with respect to annealing temperature and time after forming a doped polycrystalline silicon-germanium layer will be discussed in detail. As used herein, “n + ” or “p + ” refer to regions that are defined by higher carrier concentrations than are present in adjacent or other regions of the same or another layer or substrate. As shown in  FIG. 8 , as a result of measuring a change in resistance between the metal stud and the p +  type impurity regions in the peripheral circuit area with respect to annealing temperature and time after forming the doped polycrystalline silicon-germanium layer, and as a result of a first annealing process at a temperature lower than about 750° C. for about 30 minutes after forming the doped polycrystalline silicon-germanium layer and the RTP at a temperature lower than about 900° C. for about 90 seconds, a desired resistance lower than about 2200 Ω/contact is obtained. 
   Now referring to  FIG. 9 , a graph illustrating the resistance between the contact pad and the n-type impurity regions in the cell area with respect to annealing temperature and time after forming the doped polycrystalline silicon-germanium will be discussed. As shown in  FIG. 9 , as a result of measuring a change in resistance per contact between the contact pad and the n-type impurity regions in the cell area with respect to annealing temperature and time after forming the contact pad of the doped polycrystalline silicon-germanium layer, and as a result of the first annealing process at a temperature lower than about 750° C. for about 30 minutes after forming the contact pad of the doped polycrystalline silicon-germanium layer and the RTP at a temperature lower than about 900° C. for about 90 seconds, a desired resistance lower than about 5800 Ω/contact may be obtained. 
   As described above, a semiconductor device is provided having doped polycrystalline silicon-germanium layers and a contact pad in contact with the impurity regions of the semiconductor substrate. A buried contact plug connecting the contact pad to the capacitor lower electrodes are formed using the polycrystalline silicon-germanium layer doped with the n-type impurities, so that the activation of a dopant can be performed at a relatively low temperature. Thus, it is possible to prevent property deterioration such as an increase in resistance in other parts of the device susceptible to heat budge, for example, increase in resistance between the metal stud and the p+ type impurity regions in the peripheral circuit area. 
   In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.