Abstract:
A method for making trench MOSFET with shallow trench structures with thick trench bottom is disclosed. The improved method resolves the problem of deterioration of breakdown voltage resulted by LOCOS having a bird&#39;s beak shape introduced in prior art, and at the same time, the inventive device has a lower Qgd and lower Rds.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    This invention relates generally to the cell configuration and fabrication process of Power MOSFET devices. More particularly, this invention relates to a novel and improved trench MOSFET cell structure, and improved process of fabricating a trench MOSFET with shallow trench structures. 
         [0003]    2. The Prior Arts 
         [0004]    In order to resolve restrict of high gate charge introduced in trench MOSFET of conventional configurations, shallow trench structure was disclosed by decreasing trench depth, please refer to  FIG. 1A  for an N-channel trench MOSFET of prior art. However, when etching the shallow trench during fabrication process, the trenched gate contact  109  into shallow trenched gate may penetrate through gate oxide and short to drain because the Cdpoly (trenched gate contact depth, as shown in  FIG. 1A ) is about 1.5 times deeper than Cdsi (trenched source-body contact depth into epitaxial layer, as shown in  FIG. 1A ) as the result of faster etching rate in doped poly than in silicon region. 
         [0005]    Another disadvantage of prior art is that, as illustrated in  FIG. 2  (the upper curve), to prevent the increase of Rds (Resistance between Drain and Source), a difference between Td (Trench Depth,  FIG. 1A ) and Pd (P body depth,  FIG. 1A ) must be kept larger than 0.4 μm, thus forming a large overlap region between gate and epitaxial layer, therefore greatly increasing Qgd (gate to drain charge,  FIG. 1A ). 
         [0006]    To further reduce Qgd, a trench MOSFET with thick bottom oxide of prior art (U.S. Pat. No. 5,126,807) was disclosed, as shown in  FIG. 1B . However, according to the prior art, the thick bottom oxide  129  is formed by LOCOS (Local Oxidation of Silicon underneath trench bottom) having a bird&#39;s beak region  131  with nitride layer  130  on the sidewalls, resulting in deterioration of breakdown voltage as result of weak corner oxide formed in trench bottom. 
         [0007]    Accordingly, it would be desirable to provide a novel trench MOSFET with shallow trench structure and improved fabrication process to maintain lower Rds, lower Qgd and higher breakdown voltage. 
       SUMMARY OF THE INVENTION 
       [0008]    It is therefore an object of the present invention to provide new and improved power MOSFET with shallow trench structure and fabrication process to resolve the problems mentioned above. 
         [0009]    One aspect of the present invention is that, an additional ion implantation region with the same conductivity doping type as epitaxial layer and higher concentration is formed wrapping the shallow trenched gate bottoms to achieve lower Rds. Please refer to  FIG. 2  again for two different simulated relationship of an N-channel trench MOSFET, from which we can see that, the Rds of said N-channel trench MOSFET is significantly reduced with introduction of As ion implantation underneath shallow trenched gate bottoms. In  FIG. 3 , the dashed line represents the concentration along channel region of said N-channel trench MOSFET, indicating that the concentration of said As ion implantation (n* area) of said N-channel trench MOSFET is heavier than that of the epitaxial layer. 
         [0010]    Another aspect of the present invention is that, shallow trenched gates are formed with thick bottom insulation layer, for example, with thick bottom oxide by oxidizing un-doped poly silicon (deposited at 650° C. or above) or amorphous silicon (deposited below 650° C.) on top of gate oxide at trench bottom. By employing this structure, the Qgd of the trench MOSFET can be further reduced without having degradation of breakdown voltage due to the bird&#39;s beak effect of the prior art. 
         [0011]    Another aspect of the present invention is that, in fabrication process, source-body contact trenches and gate contact trenches are defined by two different contact masks to avoid over-etching issue which happens when using single contact mask for source-body contact trenches and gate contact trenches, thus preventing the gate/drain shortage from happening. 
         [0012]    Another aspect of the present invention is that, in some preferred embodiment, when carrying out the ion implantation for said additional ion implantation region wrapping the shallow trenched gates bottoms, a hard mask is used to block said ion implantation in termination area to avoid degradation of breakdown voltage. 
         [0013]    Another aspect of the present invention is that, in some preferred embodiment, a guard ring ion implantation with dose less than body region ion implantation is added in termination area to further avoid the degradation of breakdown voltage. 
         [0014]    Briefly, in a preferred embodiment, as shown in  FIG. 4 , the present invention discloses a shallow trench MOSFET with trench bottom wrapped by additional heavier doping concentration than epitaxial layer. Said shallow trench MOSFET is formed on a heavily doped substrate of a first conductivity doping type onto which a lightly doped epitaxial layer of a same first conductivity doping type is grown. A plurality of shallow trenched gates and at least a wider shallow trenched gate for gate connection are formed within said epitaxial layer and filled with doped poly wherein padded by a first insulation layer, for example, gate oxide layer. Especially, oxide layer on trench bottom portion is thicker than that along trench sidewalls to further reduce Qgd. Around the bottom of each shallow trenched gate, a doped region of said first conductivity doping type is formed within said epitaxial layer, furthermore, said doped region has a heavier doping concentration than said epitaxial layer. Between every two adjacent shallow trenched gates, body regions of a second conductivity doping type are formed below source region heavily doped with said first conductivity doping type. Through a second insulation layer deposited over said epitaxial layer, trenched source-body contacts are formed by penetrating said source region and extending into said body region to connect said body region, said source region to source metal, while at least a trenched gate contact is formed extending into said wider shallow trenched gate to connect said wider shallow trenched gate to gate metal. Underneath the bottom of each said trenched source-body contact, a body contact region is formed heavily doped with said second conductivity doping type to further reduce contact resistance. At the same time, said gate metal is serving as metal field plate for termination area which is beyond body region and overlap the epitaxial layer surface ranging from 2 to 10 um. 
         [0015]    Briefly, in another preferred embodiment, as shown in  FIG. 5 , the invention discloses a shallow trench MOSFET similar to that in  FIG. 4  except that, in  FIG. 5 , the termination area has trench bottom ion implantation dopant region near the top surface, and the metal field plate is beyond body and overlap the epitaxial layer surface ranging from 2 to 10 um, which can alleviate the BV degradation caused by said trench bottom ion implantation on top surface of epitaxial layer in termination area. 
         [0016]    Briefly, in another preferred embodiment, as shown in  FIG. 6 , the invention discloses a shallow trench MOSFET similar to that in  FIG. 5  except that, the termination area in  FIG. 6  has a guard ring which is lightly doped with said second conductivity doping type between said body region and said trench bottom ion implantation dopant region underneath said metal field plate. 
         [0017]    This invention further comprises method for making trench MOSFET with shallow trench structures with thick trench bottom wherein the method further comprising: depositing a first insulation layer along the inner surface of shallow gate trenches and the top surface of said epitaxial layer; depositing a layer of un-doped poly or amorphous silicon onto said first insulation layer; depositing a layer of nitride onto said un-doped poly or amorphous silicon and carrying out nitride anisotropic etch to leave said nitride only on sidewalls of said shallow gate trenches; oxidizing said un-doped poly or amorphous silicon on bottom of said shallow gate trenches and the top surface of said epitaxial layer. In some preferred embodiment, the method further comprises method for making guard ring after the formation of said shallow trenched gates and before applying body mask for the formation of body region. In some preferred embodiment, the method further comprises method for making trench bottom ion implantation region only around the bottom of each shallow trenched gate by applying a hard mask before the formation of shallow trenches and removing after the trench bottom ion implantation. In some preferred embodiment, the method further comprises method for making trench bottom ion implantation region around the bottom of each shallow trenched gate and near the top surface of said epitaxial layer in termination area by applying a hard mask before the formation of shallow trenches and removing before the trench bottom ion implantation. 
         [0018]    These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment, which is illustrated in the various drawing figures. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0019]    The present invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein: 
           [0020]      FIG. 1A  is a side cross-sectional view of a trench MOSFET of prior art. 
           [0021]      FIG. 1B  is a side cross-sectional view of a trench MOSFET with thick trench bottom of prior art. 
           [0022]      FIG. 2  is a profile showing the dependence of Rds on difference between trench depth and P body depth in an N-channel MOSFET. The upper curve indicates the condition with no As implantation at the bottom of the trench, while the lower one indicates the condition with heavier As implantation around the bottom of the trench for an N-channel trench MOSFET. 
           [0023]      FIG. 3  is a profile illustrating the doping concentration distributed along channel region from silicon surface in an N-channel MOSFET. 
           [0024]      FIG. 4  is a side cross-sectional view of a shallow trench MOSFET of an embodiment according to the present invention. 
           [0025]      FIG. 5  is a side cross-sectional view of a shallow trench MOSFET of another embodiment according to the present invention. 
           [0026]      FIG. 6  is a side cross-sectional view of a shallow trench MOSFET of another embodiment according to the present invention. 
           [0027]      FIGS. 7A to 7H  are a serial of side cross sectional views for showing the processing steps for fabricating a shallow trench MOSFET as shown in  FIG. 4 . 
           [0028]      FIGS. 8A to 8B  are a serial of side cross sectional views for showing a few processing steps for fabricating a shallow trench MOSFET as shown in  FIG. 5 . 
           [0029]      FIG. 9  is a side cross sectional view for showing a few processing steps for fabricating a shallow trench MOSFET as shown in  FIG. 6 . 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0030]    Please refer to  FIG. 4  for a preferred embodiment of this invention where an N-channel trench MOSFET with shallow trench structures is formed on a heavily N+ doped substrate  200  onto which a lightly N doped epitaxial layer  201  is grown. A plurality of shallow trenched gates are formed within said epitaxial layer and filled with doped poly onto gate oxide  202  to form shallow trenched gates  210  and at least a wider shallow trenched gate  211  for gate connection. What should be noticed is that, oxide layer on the bottom of each of trenched gates  210  and  211  is thicker than that along the sidewalls. Around the bottom of each trenched gate  210  and  211 , an n* is formed with heavier concentration than said epitaxial layer. N+ source region  205  is formed near the top surface of P body region  204  between every two adjacent shallow trenched gates  210 . The shallow trench MOSFET further comprises: trenched source-body contact filled with tungsten plug  208  penetrating through an insulation layer  206 , said source region  205  and extending into said body region  204 ; trenched gate contact filled with tungsten plug  209  penetrating through said insulation layer  206  and extending into doped poly filled in said shallow trenched gate  211 ; p+ body contact region  207  underneath each trenched source-body contact. Source metal  212  is connected to said source region  205  and said body region  204  via said trenched source-body contact metal plug  208 , while gate metal  212 ′ is connected to said shallow trenched gate  211  via said trenched gate contact metal plug  209 , said gate metal also serves as field metal plate for termination area and overlap the epitaxial layer  201  surface ranging from 2 to 10 um. 
         [0031]      FIG. 5  shows another preferred embodiment of the present invention. Compared to  FIG. 4 , the termination area in  FIG. 5  has additional n* region  203 ′ next to body region  204  near the top surface of said epitaxial layer  201 . Said n* region  203 ′ is formed due to the ion implantation for trench bottom doping region  203 . 
         [0032]      FIG. 6  shows another preferred embodiment of the present invention. Compared to  FIG. 5 , the termination area in  FIG. 6  has a p− guard ring  214  between n* region  203 ′ and P body region  204  underneath field metal plate which also serving as gate metal  212 ′. 
         [0033]      FIGS. 7A to 7H  show a series of exemplary steps that are performed to form the inventive shallow trench MOSFET shown in  FIG. 4 . In  FIG. 7A , an N doped epitaxial layer  201  is grown on an N+ doped substrate  200 . A hard mask (oxide or oxide/nitride/oxide) is deposited onto said epitaxial layer  201 . Thereafter, a trench mask (not shown) is applied onto said hard mask for the formation of a plurality of shallow gate trenches  210   a  and at least a wider shallow gate trench  211   a  by a successively hard mask etching, photo-resist removing and dry silicon etching. After all the shallow trenches are opened to a certain depth, in  FIG. 7B , a sacrificial oxide (not shown) is grown and then removed to eliminate the plasma damage introduced during opening those shallow gate trenches. Then, a layer of screen oxide is grown for the followed As ion implantation to form n* region  203  underneath each of shallow gate trenches with doping concentration heavier than that of said epitaxial layer  201  to further reduce Rds. Next, in  FIG. 7C , after the screen oxide and the hard mask removal, gate oxide  202   a , a layer of un-doped poly or amorphous silicon  202   b  and nitride layer  202   c  are successively deposited along the front surface of epitaxial layer  201  and the inner surface of said shallow gate trenches  210   a  and  211   a . Then, nitride anisotropic etch is carried out to leave said nitride layer  202   c  only on the sidewalls of said shallow gate trenches  210   a  and  211   a.    
         [0034]    In  FIG. 7D , a step of oxidation is performed to oxidizing un-doped poly or amorphous silicon  202   b  only on shallow gate trench bottoms and the top surface of said epitaxial layer due to blocking by said nitride layer  202   c  on sidewalls of said shallow gate trenches. Thus, the gate oxide layer  202  with thick trench bottom is implemented. In  FIG. 7E , after removing said nitride layer  202   c , all trenches are filled with doped poly or combination of doped poly and non-doped poly and followed by poly CMP (Chemical Mechanical Polishing) or plasma etching back to form shallow trenched gates  210  and at least a wider shallow trenched gate  211  for gate connection on which a layer of silicide (not shown) are formed as alternative for low Rg (gate resistance). Then, after applying a body mask, an ion implantation of a second conductivity doping type is carried out to form P-body region  204 . After that, the oxide along the top surface of said epitaxial layer is etched back to 100˜400 Å. Then, the process continues by applying an N+ source mask, and carrying out an ion implantation of said first conductivity doping type and driving in (or no driving in as alternative for shallower source) for the formation of N+ source region  205  near the top surface of said P body region  204 . 
         [0035]    In  FIG. 7F , a second insulation layer  206 , for example, oxide layer, is deposited covering the top surface of said epitaxial layer  201  and said shallow trenched gates  210  and said at least a wider shallow trenched gate  211 . Then, by applying a source-body contact mask, a dry oxide etch and dry silicon etch through the second insulation layer and the N+ source region are carried out successively to form source-body contact trenches  208   a  into P− body region. In  FIG. 7G , after the removal of said source-body contact mask, a gate contact mask is applied and followed by a successively dry oxide etch and dry poly-silicon etch to form gate contact trench  209   a  extending into said at least a wider shallow trenched gate  211 . Then, above said second insulation layer  206 , a BF2 ion implantation is carried out to form p+ body contact region  207  underneath each source-body contact trench  208   a  and followed by RTA (Rapid Thermal Annealing) to active BF2. In  FIG. 7H , a barrier layer of Ti/TiN or Co/TiN or Ta/TiN are deposited along the inner surface of contact trenches and the top surface of said second insulation layer  206 , on which metal W is deposited to fill said contact trenches and then etched back to form trenched source-body contact metal plug  208  and trenched gate contact metal plug  209 . Then, Al alloys padded with a resistance-reduction layer Ti or Ti/TiN is deposited covering the top surface of said second insulation layer  206 , said trenched source-body contact metal plug  208  and said trenched gate contact metal plug  209  and then patterned by a metal mask to form source metal  212  and gate metal  212 ′. 
         [0036]      FIGS. 8A to 8B  show a few steps for showing the processing steps for fabricating shallow trench MOSFET in  FIG. 5 . In  FIG. 8A , an N doped epitaxial layer  201  is grown on an N+ doped substrate  200 . A hard mask (oxide or oxide/Nitride/oxide) is deposited onto said epitaxial layer  201 . Then, a trench mask (not shown) is applied onto said hard mask for the formation of a plurality of shallow gate trenches  210   a  and at least a wider shallow gate trench  211   a  by a successively hard mask etching, photo-resist removing and dry silicon etching. Thereafter, said hard mask is removed, which is different from process flow of structure in  FIG. 4 . Then, a sacrificial oxide (not shown) is grown and then removed to eliminate the plasma damage introduced during opening those shallow gate trenches. Then, a layer of screen oxide is grown for the followed As ion implantation to form n* region  203  underneath each shallow gate trenches and n* region  203 ′ on the top surface of epitaxial layer with doping concentration heavier than that of said epitaxial layer  201 . 
         [0037]    Next, in  FIG. 8B , after the screen oxide removal, the process flow is similar to that of structure in  FIG. 4  till the formation of metal pad layer. Said n* region  203 ′ is left in termination area due to hard mask removal before screen oxide grown. 
         [0038]      FIG. 9  shows a few steps for fabricating structure in  FIG. 6 . Compared to  FIG. 8B , after the formation of shallow trenched gates, a guard ring mask is applied to define guard ring and followed by a guard ring ion implantation for the formation of P− guard ring  214  between body region  204  and n* region  203 ′ before applying P− body mask. 
         [0039]    Although the present invention has been described in terms of the presently preferred embodiments, it is to be understood that such disclosure is not to be interpreted as limiting. Various alternations and modifications will no doubt become apparent to those skilled in the art after reading the above disclosure. Accordingly, it is intended that the appended claims be interpreted as covering all alternations and modifications as fall within the true spirit and scope of the invention.