Abstract:
An analog switch includes a MOSFET that serves as a switching transistor through which the signal received at an input terminal of the analog switch passes to an output terminal of the analog switch. A resistor is coupled to the gate of the switching transistor to prevent the discharge of gate capacitance when a control signal is activating the switching transistor in an ON state. A second MOSFET has its source and drain terminals coupled across the gate and substrate of the switching transistor. The second MOSFET is activated to an ON state to provide low-impedance driving of the switching transistor when the control signal is driving the switching transistor to an OFF state. The switching MOSFET and the second MOSFET may be NMOS devices in some embodiments, while in other embodiments, PMOS devices.

Description:
TECHNICAL FIELD  
         [0001]    The invention relates to analog switches, and in particular metal-oxide semiconductor (MOS) analog switches.  
         BACKGROUND  
         [0002]    Analog switches are fundamental building blocks in analog circuit design. An analog switch is turned ON and OFF by-low voltage control signal. When the analog switch is in the ON state, an analog electrical signal is conducted from an input terminal, through a transistor switch, to an output terminal. Analog switches have many applications, including low-voltage applications such as audio and video signal routing, gain selection, and many others, and high-voltage applications such as ultrasound imaging, digital subscriber loop applications, and many others.  
           [0003]    Today&#39;s analog switches typically employ metal-oxide semiconductor field-effect transistors (MOSFETs) as the transistor switch through which the electrical signal conducts. The MOSFET switch may be an n-channel device (NMOS transistor), a p-channel device (PMOS transistor), or a pair of NMOS and PMOS transistors which enables current to be conducted through the analog switch in either direction. NMOS transistors have a smaller die size than PMOS transistors. The smaller die size makes NMOS transistors less capacitive, and thus NMOS transistors enable faster switching speeds, which is necessary in many applications.  
           [0004]    A prior art analog switch  10 , shown in FIG. 1, includes an NMOS switch transistor N 1  with its drain connected to an input terminal IN, its source connected to an output terminal OUT, and its gate controlled by a control signal CNTL. When the control terminal CNTL is HIGH, switch transistor N 1  is turned ON, thus switching the signal received at the input terminal IN to the output terminal OUT.  
           [0005]    To achieve acceptable “flatness” (that is, a constant on-resistance) for AC applications when using an NMOS transistor, a large resistor R 1  is typically put in series with the switch transistor N 1  gate, as shown in FIG. 1. In the ON state, the series resistor R 1  prevents the discharge of the capacitive charge on the gate of the switching transistor N 1 , and thus holds the gate-to-source voltage Vgs of switch transistor N 1  constant even under large signal swing conditions.  
           [0006]    In many applications, the NMOS switching transistor N 1 &#39;s gate cannot be driven in the OFF state by high impedance, but instead must be driven by a low impedance to minimize the gate voltage swing, which follows the swing of the signal received at input terminal IN. Minimizing the gate voltage swing may be necessary, especially in high-voltage applications, to obtain high off-isolation and prevent the transistor switch from turning ON when it should not turn ON. To obtain the needed off-isolation, the prior art analog switch  10  in FIG. 1 includes a second NMOS transistor N 2 , which is activated when N 1  is not being activated. The gate of switching transistor N 1  is thus switched through N 2  to the negative supply V- when the switching transistor Ni is in the OFF state.  
           [0007]    The prior art analog switch design shown in FIG. 1 has drawbacks. First, because of the charge on the gate of switching transistor N 1 , the second transistor N 2  is expected to see drain-to-source voltages (Vds) of at least 1.5 times the total supply voltage. In high-voltage applications such as ultrasound probe switching where the total supply voltage may be 220 volts or even more, there may not be sufficient breakdown Vds headroom to accommodate the levels of Vds that could be seen at N 2 . Another drawback of the analog switch design of FIG. 1 is that the drain capacitance of N 2  loads the gate charge of N 1  causing signal induced Vgs modulation of N 1  that increases distortion.  
         SUMMARY  
         [0008]    The invention overcomes limitations in prior art analog switches. The analog switch includes a MOSFET that serves as a switching transistor through which the signal received at an input terminal of the analog switch passes to an output terminal of the analog switch. A resistor is coupled to the gate of the switching transistor to prevent the discharge of gate capacitance when a control signal is activating the switching transistor in an ON state. A second MOSFET has its source and drain terminals coupled across the gate and substrate of the switching transistor. The second MOSFET is activated to an ON state to provide low-impedance driving of the switching transistor when the control signal is driving the switching transistor to an OFF state. The switching MOSFET and the second MOSFET may be NMOS devices in some embodiments, while in other embodiments, PMOS devices.  
           [0009]    In various embodiments, the analog switch may include an additional switch that couples the substrate of the switching transistor and the source of the second MOSFET to either a negative supply voltage (in NMOS embodiments) or a positive supply (in PMOS embodiments) when the second MOSFET is activated to an ON state. The analog switch may also include yet another switch that drives the second MOSFET OFF when the control signal is activating the switching transistor in an ON state, and a switch that that drives the second MOSFET ON when the control signal is activating the switching transistor in an OFF state. Also, the analog switch may include a switch that couples the signal received at the input terminal to the substrate of the switching transistor when the switching transistor is being driven to an ON state.  
           [0010]    The invention offers one or more of the following advantages. Because the second MOSFET is connected between the gate and substrate of the switching transistor, and because of the charge stored on the switching transistor, the second MOSFET sees a relatively constant voltage regardless of the voltage swing. This means that the drain-to-source voltage (Vds) of the second MOSFET will never exceed the supply voltage, thus conserving breakdown Vds headroom which is especially important in high-voltage applications. Also, because the drain capacitance of the second MOSFET is parallel to the gate-channel capacitance of the switching transistor, there is no signal-induced gate drive modulation of the switching transistor. Therefore, distortion is minimized and linearity of the on-resistance for the switching transistor is not compromised.  
           [0011]    The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims. 
       
    
    
     DESCRIPTION OF DRAWINGS  
       [0012]    [0012]FIG. 1 is a schematic diagram of a prior art analog switch.  
         [0013]    [0013]FIG. 2 is a schematic diagram of an analog switch in accordance with the invention.  
         [0014]    [0014]FIGS. 3A and 3B are schematic diagrams of circuitry that may be added to the analog switch of FIG. 2.  
         [0015]    [0015]FIG. 4 is a schematic diagram of an alternative embodiment of an analog switch in accordance with the invention.  
     
    
     DETAILED DESCRIPTION  
       [0016]    An analog switch  20  in accordance with the invention, shown in FIG. 2, includes an NMOS switch transistor N 1  with its drain connected to an input terminal IN, its source connected to an output terminal OUT, and its gate controlled by a control signal CNTL. When control signal CNTL is HIGH, switch transistor N 1  is turned ON, thus switching the signal received at the input terminal IN to the output terminal OUT.  
         [0017]    A large resistor R 1  is in series with the switch transistor N 1  gate and the control signal CNTL, as was the case in the prior art switch  10  shown in FIG. 1. Thus, during the time that the control signal is HIGH, the series resistor R 1  prevents the discharge of the capacitive charge on the gate of the switch transistor N 1 , and thus holds the gate-to-source voltage Vgs of switch transistor N 1  constant even under large signal swing conditions.  
         [0018]    To obtain the necessary off-isolation when the switch transistor N 1  is in the OFF state, NMOS transistor N 2  in combination with NMOS transistor N 3  switches the gate of N 1  to the negative supply V − . The drain of N 2  is connected to the gate of switch transistor N 1 . The source of N 2  is connected to the substrate of switch N 1  and to the substrate of N 2 . N 2  is thus connected between the gate and substrate of N 1 , which offers benefits that will be described later. Owing to the functioning of PMOS transistor P 1  and NMOS transistor N 4 , whose operation will be described later, N 2  is ON when the control signal CNTL is LOW and N 1  OFF. N 3  has its drain connected to the source of N 2  and to the substrates of both N 2  and N 1 . N 3  receives at its gate the control signal CNTL after having been inverted by inverter I 1 , and thus N 3  switches the substrates of N 2  and N 1  to the negative supply V −  when the control signal CNTL is LOW. The connection of the N 1  substrate to the negative supply V −  reverse biases Ni.  
         [0019]    NMOS transistor N 4  serves to drive N 2  OFF when the control signal CNTL is HIGH and thus switch transistor N 1  is ON. PMOS transistor P 1  serves to drive N 2  ON when the control signal CNTL is LOW and thus switch transistor N 1  is OFF. NMOS transistor N 4  receives the control signal CNTL at its gate. The drain of N 4  is connected to both the gate of N 2  and to the drain of PMOS transistor P 1 . The source of N 4  is connected to the substrate of both N 1  and N 2 , as well as to the substrate of N 4 . The control signal CNTL being HIGH activates N 4  to the ON state and also turns P 1  OFF, which shorts the gate of N 2  to its source, thus ensuring that N 2  is OFF when the control signal CNTL is HIGH. PMOS transistor P 1  also receives the control signal CNTL, via buffer A 1 , at P 1 &#39;s gate. The source of P 1  is connected to positive supply voltage V + . The source of P 1  is also connected to P 1 &#39;s substrate. Thus, CNTL being LOW turns P 1  on, which turns N 2  OFF.  
         [0020]    Circuitry  22 , which includes NMOS transistors N 5  and N 6 , switches the substrate of switch transistor N 1  to the signal received at input terminal IN when N 1  is ON, and in so doing minimizes the body effect of N 1 . The drain of N 5  is connected to the drain of N 1 , the source of N 5  to the drain of N 6 , and the source of N 6  to the output terminal OUT. The substrates of N 5  and N 6  are common and connected to the substrate of N 1  and to the source and substrate of N 2 . N 5  and N 6  both receive the control signal CNTL at their gates. Therefore, both N 5  and N 6  are turned ON when the control signal CNTL is HIGH. The substrate of N 1  is therefore tied to the signal level received at N 1 &#39;s drain. This minimizes the body effect. It also should be noted that during the time the input signal at terminal IN is tied to the N 1  substrate, N 3  is OFF and thus the N 1  substrate is not also connected to the negative supply.  
         [0021]    When the switch  20  is ON, the substrate of N 1  is at the signal level due to the operation of circuitry  22 , which minimizes the body effect. Also when the switch  20  is ON, N 2  is OFF. Because N 2  is connected between the gate and substrate of N 1 , and because of the charge stored on the gate of N 1 , N 2  sees a relatively constant voltage regardless of the signal swing. This means that the Vds of N 2  will never exceed the supply voltage. This aspect of the invention thus conserves breakdown Vds headroom, which is especially important in high-voltage applications. Also, because the drain capacitance of N 2  is parallel to the gate-channel capacitance of N 1 , there is no signal-induced gate drive modulation of N 1 . Therefore, a design in accordance with the invention does not compromise the linearity of the on-resistance of the switch transistor Ni. When the switch  20  is OFF, N 2  and N 3  are ON. The impedance seen by the gate of switch transistor N 1  is the sum of the impedances of N 2  and N 3 . These two devices, that is, N 2  and N 3 , may be made as large as possible to achieve the required off-isolation.  
         [0022]    In some embodiments, the semiconductor manufacture process employed may limit by the level of gate-to-source voltage Vgs that N 1  can sustain. In these cases it may be necessary to ensure that the gate-to-source voltage Vgs of N 1  does not exceed a prescribed limit. To ensure this, a voltage clamp D 1  may be connected between the gate and drain (input terminal IN) of N 1 , as shown in FIG. 3A. The voltage clamp D 1  may alternatively be connected between the gate and source of N 1  (shown in FIG. 3A by dashed lines). Also, circuit  22  connects the N 1  substrate to the input terminal IN when N 1  is ON, yet another alternative is to connect the voltage clamp D 1  between the gate and substrate of N 1 , as shown in FIG. 3B. In the embodiments of FIG. 3A and 3B, the voltage clamp is a zener diode D 1 , although those skilled in the art will recognize that other configurations of voltage clamps may be used. Also, combination of one or more of the above may be used.  
         [0023]    [0023]FIG. 4 shows an alternative embodiment of the invention where the switch transistor is a PMOS transistor P 1  instead of the NMOS transistor N 1  in the FIG. 2 embodiment. Also, the NMOS transistors N 2 -N 6  of the FIG. 2 embodiment are replaced with PMOS transistors P 2 -P 6  in the FIG. 4 embodiment, and the PMOS transistor P 1  of FIG. 2 is replaced with the NMOS transistor N 1  of FIG. 4. The PMOS embodiment of FIG. 4 operates similarly to the NMOS embodiment of FIG. 2. PMOS transistor P 2  in combination with PMOS transistor P 3  switches the gate of P 1  to the positive supply V + . PMOS transistor P 4  serves to drive P 2  OFF when the control signal is LOW and thus P 1  is ON, while NMOS transistor N 1  serves to drive P 2  ON when the control signal is HIGH and thus switch transistor P 1  is OFF. PMOS transistors P 5  and P 6  switch the substrate of switch transistor P 1  to the signal received at the input terminal IN when P 1  is ON, and in so doing minimizes the body effect of P 1 . P 2  is connected between the gate and substrate of P 1 , and thus, because of the charge stored on the gate of P 1 , P 2  sees a relatively constant voltage regardless of the signal swing. Also, the drain capacitance of P 2  is parallel to the gate-channel capacitance of P 1 , and so there is no signal-induced gate drive modulation of P 1 . Therefore, as with the NMOS embodiment of FIG. 2, a PMOS embodiment of the type shown in FIG. 4 does not compromise the linearity of the on-resistance of the switch transistor P 1 .  
         [0024]    While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments were merely illustrative of and not restrictive on the broad invention, and that this invention not be limited to the specific constructions and arrangements shown and described, because various other modifications may occur to those of ordinary skill in the art. For example, in the switch  20  of FIG. 2, switch transistor N 1  could be eliminated and NMOS transistors N 5  and N 6  may then serve as the switch transistor. This is commonly done with double diffusion MOS (DMOS) embodiments of analog switches. In FIG. 2, circuitry other than the PMOS transistor P 1  and NMOS transistor N 4  could be used to turn ON NMOS transistor N 2 . Other circuitry may be used as circuitry  22  to switch the signal to the N 1  substrate.