Abstract:
Artifacts in a specific pattern due to a time difference in a VTDC driving scheme may be prevented. A display device includes: a display including a first pixel circuit, a second pixel circuit, and a pixel group having a first light emitting element, a second light emitting element, a third light emitting element and a fourth light emitting element arranged in a first direction; and a light emission driver generating a first sub-light-emission control signal for controlling emission of the first light emitting element and a second sub-light-emission control signal for controlling emission of the second light emitting element in a first subframe, and generating a third sub-light-emission control signal for controlling emission of the third light emitting element and a fourth sub-light-emission control signal for controlling emission of the fourth light emitting element in a second subframe.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority to and the benefit of Korean Patent Application No. 10-2013-0084034 filed in the Korean Intellectual Property Office on Jul. 17, 2013, the entire contents of which are incorporated herein by reference. 
     BACKGROUND 
     (a) Field 
     The present invention relates to a display device and a method of driving the same. 
     (b) Discussion of the Related Art 
     An organic light emitting diode (OLED) display, from among flat panel displays, displays images using OLEDs that generate light through recombination of electrons and holes, and has a high response speed, low power consumption, high light emission efficiency, high luminance, and a wide viewing angle. 
     A plurality of pixels emitting light in an OLED display includes OLEDs which generate light with predetermined luminance in response to a data current supplied from pixel circuits. 
     In general, each of RGB pixels in an OLED display panel is driven by a thin film transistor (TFT) circuit to emit light, and each pixel includes a plurality of transistors and capacitors. 
     A time division controlled (TDC) driving panel can concurrently drive two pixels using a single TFT driving circuit and thus transistor integration of the TDC driving panel is reduced to half the transistor integration of a conventional display panel, thus achieving high resolution. 
     To drive two pixels using a single driving circuit in the TDC driving panel, a horizontal TDC (HTDC) or vertical TDC (VTDC) driving circuit is shared. 
     However, in the case of HTDC driving, a conventional TDC driving panel generates color separation in a specific pattern, and in the case of VTDC, the conventional TDC generates artifacts having a specific pattern due to a time difference caused by interlaced operation. 
     The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art. 
     SUMMARY 
     The present invention has been made in an effort to provide a display device and a method of driving the same by preventing (or reducing) artifacts caused by a time difference in a specific pattern in a VTDC driving mode. 
     The technical problems solved by embodiments of the present invention are not limited to the above technical problems, and those skilled in the art may understand other technical problems from the following description. 
     According to an aspect of the present invention, a display device may include: a display having: a first pixel circuit; a second pixel circuit; and a pixel group having a first light emitting element, a second light emitting element, a third light emitting element and a fourth light emitting element arranged along a first direction, the first and third light emitting elements being coupled to the first pixel circuit and the second and fourth light emitting elements being coupled to the second pixel circuit; and a light emission driver configured to generate: a first sub-light-emission control signal for controlling emission of the first light emitting element during a first subframe, a second sub-light-emission control signal for controlling emission of the second light emitting element during the first subframe, a third sub-light-emission control signal for controlling emission of the third light emitting element during a second subframe, and a fourth sub-light-emission control signal for controlling emission of the fourth light emitting element during the second subframe. 
     A first data signal and a second data signal respectively corresponding to the first light emitting element and the second light emitting element may be respectively delivered to the first pixel circuit and the second pixel circuit during the first subframe, and a third data signal and a fourth data signal respectively corresponding to the third light emitting element and the fourth light emitting element may be respectively delivered to the first pixel circuit and the second pixel circuit during the second subframe. 
     The first pixel circuit may be coupled to a first scan line and a first initialization line, and the second pixel circuit may be coupled to a second scan line and a second initialization line, wherein a driving current flowing through the first pixel circuit according to the first data signal may be delivered to the first light emitting element according to the first sub-light-emission control signal, during the first subframe, and a driving current flowing through the second pixel circuit according to the second data signal may be delivered to the second light emitting element according to the second sub-light-emission control signal, during the first subframe, and wherein the first pixel circuit may receive the first data signal according to a first scan signal delivered through the first scan line, and the second pixel circuit may receive the second data signal according to a second scan signal delivered through the second scan line, during the first subframe. 
     The first pixel circuit may be coupled to a first scan line and a first initialization line, and the second pixel circuit may be coupled to a second scan line and a second initialization line, wherein a driving current flowing through the first pixel circuit according to the third data signal may be delivered to the third light emitting element according to the third sub-light-emission control signal, and driving current flowing through the second pixel circuit according to the fourth data signal may be delivered to the fourth light emitting element according to the fourth sub-light-emission control signal, during the second subframe, and wherein the first pixel circuit may receive the third data signal according to a first scan signal delivered through the first scan line, and the second pixel circuit may be receive the fourth data signal according to a second scan signal delivered through the second scan line, during the second subframe. 
     The first pixel circuit may include: a first transistor configured to be turned on by a first scan signal to apply a corresponding data voltage to a second electrode of a second transistor; the second transistor having a first electrode through which current flows corresponding to a voltage across a control electrode and the second electrode of the second transistor thereof, the second electrode being electrically coupled to a first power source; a fifth transistor configured to be turned on by the first sub-light-emission control signal to deliver a current to the first light emitting element; and a sixth transistor configured to be turned on by the third sub-light-emission control signal to deliver a current to the third light emitting element, and wherein the second pixel circuit includes: a seventh transistor configured to be turned on by a second scan signal to apply a corresponding data voltage to a second electrode of an eighth transistor; the eighth transistor having a first electrode through which current flows corresponding to a voltage across a control electrode and the second electrode of the eighth transistor thereof, the second electrode being electrically coupled to the first power source; an eleventh transistor configured to be turned on by the second sub-light-emission control signal to deliver a current to the second light emitting element; and a twelfth transistor configured to be turned on by the fourth sub-light-emission control signal to deliver a current to the fourth light emitting element, wherein the fifth transistor and the eleventh transistor may be turned on during the first subframe and the sixth transistor and the twelfth transistor may be turned on during the second subframe. 
     The first pixel circuit may further include a third transistor configured to be turned on in response to the first scan signal to diode-connect the second transistor, and the second pixel circuit may further include a ninth transistor configured to be turned on in response to the second scan signal to diode-connect the eighth transistor. 
     The first pixel circuit may further include a fourth transistor configured to be turned on by a first initialization signal to apply an initialization voltage to the control electrode of the second transistor, and the second pixel circuit may further include a tenth transistor configured to be turned on by a second initialization signal to apply an initialization voltage to the control electrode of the eighth transistor, wherein the first and third transistors are configured to be turned on by the first scan signal after the fourth transistor is turned on by the first initialization signal, and the seventh and ninth transistors are configured to be turned on by the second scan signal after the tenth transistor is turned on by the second initialization signal. 
     The first pixel circuit may further include a first capacitor coupled between the first power source and the control electrode of the second transistor, and the second pixel circuit may further include a second capacitor coupled between the first power source and the control electrode of the eighth transistor. 
     The first pixel circuit may further include a third capacitor coupled between a control electrode of the first transistor and a second electrode of the third transistor, and the second pixel circuit may further include a fourth capacitor coupled between a control electrode of the seventh transistor and a second electrode of the ninth transistor. 
     According to another aspect of the present invention, a method of driving a display device may include a display having a first pixel circuit, a second pixel circuit, and a pixel group having a first light emitting element, a second light emitting element, a third light emitting element, and a fourth light emitting element arranged along a first direction, the first and third light emitting elements being coupled to the first pixel circuit and the second and fourth light emitting elements being coupled to the second pixel circuit, and a light emission driver configured to generate a first sub-light-emission control signal for controlling emission of the first light emitting element and a second sub-light-emission control signal for controlling emission of the second light emitting element during a first subframe, and generating a third sub-light-emission control signal for controlling emission of the third light emitting element and a fourth sub-light-emission control signal for controlling emission of the fourth light emitting element during a second subframe, the method may include: delivering a first data signal and a second data signal respectively corresponding to the first light emitting element and the second light emitting element to the first pixel circuit and the second pixel circuit, respectively, during the first subframe; and delivering a driving current flowing through the first pixel circuit according to the first data signal to the first light emitting element according to the first sub-light-emission control signal, and delivering a driving current flowing through the second pixel circuit according to the second data signal to the second light emitting element according to the second sub-light-emission control signal during the first subframe. 
     The method may further include: delivering a driving current flowing through the first pixel circuit according to the third data signal to the third light emitting element according to the third sub-light-emission control signal, and delivering a driving current flowing through the second pixel circuit according to the fourth data signal to the fourth light emitting element according to the fourth sub-light-emission control signal, during the second subframe; and delivering the third data signal to the first pixel circuit according to a first scan signal delivered through the first scan line, and delivering the fourth data signal to the second pixel circuit according to a second scan signal delivered through the second scan line, during the second subframe. 
     The first pixel circuit may include: a first transistor configured to be turned on by a first scan signal to apply a corresponding data voltage to a second electrode of a second transistor; the second transistor having a first electrode through which current flows corresponding to a voltage across a control electrode and the second electrode of the second transistor thereof, the second electrode being electrically coupled to a first power source; a fifth transistor configured to be turned on by the first sub-light-emission control signal to deliver current to the first light emitting element; and a sixth transistor configured to be turned on by the third sub-light-emission control signal to deliver current to the third light emitting element, and wherein the second pixel circuit includes: a seventh transistor configured to be turned on by a second scan signal to apply a corresponding data voltage to a second electrode of an eighth transistor; the eighth transistor having a first electrode through which current flows corresponding to a voltage across a control electrode and the second electrode of the eighth transistor thereof, the second electrode being electrically coupled to the first power source; an eleventh transistor configured to be turned on by the second sub-light-emission control signal to deliver current to the second light emitting element; and a twelfth transistor configured to be turned on by the fourth sub-light-emission control signal to deliver current to the fourth light emitting element, wherein the method may include: turning on the fifth transistor and the eleventh transistor during the first subframe; and turning on the sixth transistor and the twelfth transistor during the second subframe. 
     The first pixel circuit may further include a third transistor configured to be turned on in response to the first scan signal to diode-connect the second transistor and a fourth transistor configured to be turned on by a first initialization signal to apply an initialization voltage to the control electrode of the second transistor, wherein the second pixel circuit further includes a ninth transistor configured to be turned on in response to the second scan signal to diode-connect the eighth transistor and a tenth transistor configured to be turned on by a second initialization signal to apply an initialization voltage to the control electrode of the eighth transistor, the method may further include: turning on the first and third transistors by the first scan signal after the fourth transistor is turned on by the first initialization signal; and turning on the seventh and ninth transistors by the second scan signal after the tenth transistor is turned on by the second initialization signal. 
     The first pixel circuit may further include a first capacitor coupled between the first power source and a control electrode of the second transistor, the method may further include: turning on the fourth transistor by the first initialization signal to apply an initialization voltage to the control electrode of the second transistor and maintaining a first voltage by the first capacitor. 
     The second pixel circuit may further include a second capacitor coupled between the first power source and a control electrode of the eighth transistor, the method may further include: turning on the tenth transistor by the second initialization signal to apply an initialization voltage to the control electrode of the eighth transistor and maintaining a second voltage by the second capacitor. 
     The display device and method of driving the same according to the embodiments of the present invention can prevent artifacts in a specific pattern due to a time difference in the VTDC driving scheme. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram showing a display device according to an example embodiment of the present invention. 
         FIG. 2  is a diagram showing an n-th row of a display device according to an example embodiment of the present invention. 
         FIG. 3  is a diagram showing a circuit of a pixel group according to an embodiment of the present invention. 
         FIG. 4A  is a timing diagram showing a driving time of a first subframe for explaining operation of the pixel group shown in  FIG. 3 . 
         FIG. 4B  is a timing diagram showing a driving time of a second subframe for explanation of operation of the pixel group shown in  FIG. 3 . 
     
    
    
     DETAILED DESCRIPTION 
     The embodiments of the present invention will be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the invention are shown. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. The drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification. 
     In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements. The terms “-er(or)”, “module”, “portion”, or “part” is used to signify a unit performing at least one function or operation. The unit can be realized in hardware, software, or in combination of both. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. Further, the use of “may” when describing embodiments of the present invention refers to “one or more embodiments of the present invention.” 
       FIG. 1  is a diagram showing a display device according to an example embodiment of the present invention. 
     Referring to  FIG. 1 , the display device according to the example embodiment of the present invention includes a signal controller  100 , a scan driver  200 , a data driver  300 , a light emission driver  400 , and a display  500 . 
     The signal controller  100  receives external video signals RGB and input control signals for controlling display of the video signals. The video signals RGB include luminance information of each pixel included in each pixel group PX. The luminance information includes data indicating the graylevel of the corresponding pixel from among a predetermined number of graylevels (for example, 1024=2 10 , 256=2 8 , or 64=2 6  graylevels). The input control signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a main clock signal MCLK. 
     The signal controller  100  processes the video signals RGB into signals adapted to operate the display  500  and the data driver  300  based on the video signal RGB and the input control signals, and generates emission control signals CONT 1 , a scan control signal CONT 2 , a data control signal CONT 3 , and a video data signal DAT. 
     The signal controller  100  divides each frame of the video signals RGB into first and second subframes, and determines a driving method of a plurality of pixel groups PX. 
     The signal controller  100  generates a plurality of emission control signals CONT 1  for respectively controlling emission periods and non-emission periods of the plurality of pixel groups PX, and provides the emission control signals CONT 1  to the light emission driver  400 . 
     The signal controller  100  divides the video signals RGB into frames according to the vertical synchronization signal Vsync, and segments each frame into first and second subframes. Video signals RGB to be written to the pixel groups in each subframe are divided for a plurality of scan lines Gi 1  to Gin and Gw 1  to Gwn according to the horizontal synchronization signal Hsync. The signal controller  100  converts the video signals RGB into image data signals DAT by processing the video signals RGB (for example, by performing gamma correction on the video signals RGB). 
     The signal controller  100  transfers the scan control signal CONT 2  to the scan driver  200 , and delivers the data control signal CONT 3  and image data signals DAT to the data driver  300 . 
     The scan driver  200  delivers a plurality of scan signals to a plurality of scan lines Gi 1  to Gin and Gw 1  to Gwn, respectively, formed corresponding to a plurality of pixel groups PX according to the scan control signal CONT 2 . 
     The data driver  300  delivers a plurality of data signals corresponding to the image data signals DAT to a plurality of data lines D 1  to Dm, respectively, according to the data control signal CONT 3 . 
     According to an embodiment, the data driver  300  delivers, through the plurality of data lines D 1  to Dm, a plurality of data signals for controlling degrees of light emission of pixels of the plurality of pixel groups PX, in synchronization with a time when a scan signal of a gate-on voltage corresponding to each subframe is supplied. The gate-on voltage corresponds to a level that turns on switching transistors Ms 1  and Ms 2  (see, for example,  FIG. 3 ). 
     The light emission driver  400  delivers a plurality of light emission signals to a plurality of main light emission control lines E 1  to En, respectively, and first to fourth sub-light-emission control lines EM_T 1 -EM_Tk, EM_U 1 -EM_Uk, EM_V 1 -EM_Vk, and EM_W 1 -EM_Wk, respectively, according to the light emission control signals CONT 1 . 
     The display  500  includes a plurality of data lines D 1  to Dm extending in a column direction, a plurality of scan lines Gi 1  to Gin and Gw 1  to Gwn extending in a row direction, main light emission control lines E 1  to En, first sub-light-emission control lines EM_T 1  to EM_Tk, second sub-light-emission control lines EM_U 1  to EM_Uk, third sub-light-emission control lines EM_V 1  to EM_Vk, fourth sub-light-emission control lines EM_W 1  to EM_Wk, and a plurality of pixel groups PX. 
     The plurality of pixel groups are respectively coupled to the plurality of data lines D 1  to Dm, the plurality of scan lines Gi 1  to Gin and Gw 1  to Gwn, the plurality of main light emission control lines E 1  to En, the first sub-light-emission control lines EM_T 1  to EM_Tk, the second sub-light-emission control lines EM_U 1  to EM_Uk, the third sub-light-emission control lines EM_V 1  to EM_Vk and the fourth sub-light-emission control lines EM_W 1  to EM_Wk. 
     Data voltages corresponding to the image data signals DAT are delivered to corresponding pixel groups PX through the plurality of data lines D 1  to Dm, and a plurality of scan signals for selecting a plurality of pixel circuits (e.g., PX 1  and PX 2  shown in  FIG. 2 ) of the pixel group PX coupled to each scan line is delivered through the plurality of scan lines Gi 1  to Gin and Gw 1  to Gwn. 
     A plurality of light emitting signals for controlling light emission of a plurality of light emitting elements OLED 11  to OLED  22  of the plurality of pixel groups PX is delivered to the plurality of pixel groups PX corresponding thereto through the plurality of main light emission control lines E 1  to En and the first to fourth sub-light-emission control lines EM_T 1  to EM_Tk, EM_U 1  to EM_Uk, EM_V 1  to EM_Vk and EM_W 1 , to EM_Wk. 
     Detailed configuration of the pixel groups PX will now be described with reference to  FIGS. 2 and 3 . 
       FIG. 2  is a diagram showing an n-th row of the display device according to the example embodiment of the present invention. 
       FIG. 3  is a diagram showing a circuit of a pixel group according to an embodiment of the present invention. 
     Referring to  FIG. 2 , each pixel group PX corresponding to an n-th row  510  including a plurality of pixel groups PX is coupled to n-th scan lines Gin and Gwn, an n-th main light emission control line En, n-th first sub-light-emission control line EM_Tk, an n-th second sub-light-emission control line EM_Uk, an n-th third sub-light-emission control line EM_Vk, an n-th fourth sub-light-emission control line EM_Wk, and an m-th data line Dm. 
     Referring to  FIG. 3 , the first sub-light-emission control line EM_Tk controls light emission of a first light emitting element OLED 11 , which emits light according to an image data signal DAT written in (or during) the first subframe, out of the two light emitting elements OLED 11  and OLED 12  coupled to a first pixel circuit PX 1 . 
     The second sub-light-emission control line EM_Uk controls light emission of a third light emitting element OLED 21 , which emits light according to the image data signal DAT written in the first subframe, out of the two light emitting elements OLED 21  and OLED 22  coupled to a second pixel circuit PX 2  included in the pixel group PX. 
     The third sub-light-emission control line EM_Vk controls light emission of a second light emitting element OLED 12 , which emits light according to an image data signal DAT written in the second subframe, out of the two light emitting elements OLED 11  and OLED 12  coupled to the first pixel circuit PX 1  included in the pixel group PX. 
     The fourth sub-light-emission control line EM_Wk controls light emission of a fourth light emitting element OLED 22 , which emits light according to the image data signal DAT written in (or during) the second subframe, out of the two light emitting elements OLED 21  and OLED 22  coupled to a second pixel circuit PX 2  included in the pixel group PX. 
     Referring to  FIG. 3 , the pixel group PX includes the first pixel circuit PX 1 , the second pixel circuit PX 2 , and the first, second, third, and fourth light emitting elements OLED 11 , OLED 12 , OLED 21 , and OLED 22 . 
     The first light emitting element OLED 11  and the third light emitting element OLED 12  share the first pixel circuit PX 1 , and the second light emitting element OLED 21  and the fourth light emitting element OLED 22  share the second pixel circuit PX 2 . 
     The first, second, third, and fourth light emitting elements are arranged in the order of the first light emitting element OLED 11 , the second light emitting element OLED 21 , the third light emitting element OLED 12 , and the fourth light emitting element OLED 22  in the column direction, from top to bottom. 
     Each light emitting element included in the pixel group PX may emit light having one of red R, green G, and blue B colors. 
     Driving voltages ELVDD and ELVSS for operating the pixel group PX are supplied to respective terminals of the pixel group PX between which each of the light emitting elements OLED 11 , OLED 12 , OLED 21 , and OLED 22  is serially coupled with one of the driving transistors Md 1  and Md 2 . 
     Referring to  FIG. 3 , the first pixel circuit PX 1  includes the switching transistor Ms 1 , the driving transistor Md 1 , a plurality of transistors M 11  to M 15 , capacitors C 11  and Cboost 1 , the first light emitting element OLED 11 , and the third light emitting element OLED 12 . 
     According to an embodiment of the present invention, the switching transistor Ms 1  includes a gate electrode coupled to the scan line Gwn- 1 , a source electrode coupled to the data line Dm, and a drain electrode coupled to the driving transistor Md 1 . The switching transistor Ms 1  is turned on by a scan signal applied to the scan line Gwn- 1  to deliver a data voltage applied to the data line Dm to the source electrode of the driving transistor Md 1 . 
     The driving transistor Md 1  includes a source electrode to which the data voltage is applied when the switching transistor Ms 1  is turned on, a gate electrode coupled to the first terminal of the capacitor C 11 , and a drain electrode coupled to the source electrode of the transistor M 14 . The second terminal of the capacitor C 11  is coupled to a voltage source generating the driving voltage ELVDD. 
     The transistor M 11  includes a gate electrode coupled to the scan line Gwn- 1 , a source electrode coupled to the gate electrode of the driving transistor Md 1 , and a drain electrode coupled to the drain electrode of the driving transistor Md 1 . The transistor M 11  is turned on by the scan signal applied to the scan line Gwn- 1  to diode-connect the driving transistor Md 1 . 
     The first terminal of the capacitor Cboost 1  is coupled to the scan line Gwn- 1  and the second terminal thereof is coupled to the source electrode of the transistor M 11 . 
     The transistor M 12  includes a gate electrode coupled to the scan line Gin- 1 , a source electrode coupled to a voltage source generating an initialization voltage Vint, and a drain electrode coupled to the gate electrode of the driving transistor Md 1 . 
     The transistor M 13  includes a gate electrode coupled to the main light emission control line En- 1 , a source electrode coupled to the voltage source generating the driving voltage ELVDD, and a drain electrode coupled to the source electrode of the driving transistor Md 1 . 
     The transistor M 14  includes a gate electrode coupled to the first sub-light-emission control line EM_Tk, a source electrode coupled to the drain electrode of the driving transistor Md 1 , and a drain electrode coupled to the anode of the first light emitting element OLED 11 . 
     The cathode of the first light emitting element OLED 11  is coupled to the voltage source generating the driving voltage ELVSS. The first light emitting element OLED 11  emits light according to a current flowing through the driving transistor Md 1  when the transistor M 14  is turned on by a light emitting signal delivered through the first sub-light-emission control line EM_Tk. 
     The transistor M 15  includes a gate electrode coupled to the third sub-light-emission control line EM_Vk, a source electrode coupled to the drain electrode of the driving transistor Md 1 , and a drain electrode coupled to the anode of the third light emitting element OLED 12 . 
     The cathode of the third light emitting element OLED 12  is coupled to the voltage source generating the driving voltage ELVSS. The third light emitting element OLED 12  emits light according to current flowing through the driving transistor Md 1  when the transistor M 15  is turned on by a light emitting signal delivered through the third sub-light-emission control line EM_Vk. 
     The transistor M 12  is turned on by an initialization signal having an enable level (i.e., enable signal), transmitted through the scan line Gin- 1 , and thus the initialization voltage Vint is applied to the gate electrode of the driving transistor Md 1  and the capacitor C 11  maintains a voltage ELVDD-VINT (i.e., a voltage difference of ELVDD and VINT). Subsequently, the switching transistor Ms 1  and the transistor M 11  are turned on by the enable signal transmitted through the scan line Gwn- 1 . 
     When the transistor M 11  is turned on, the driving transistor Md 1  enters a diode-connected state. Accordingly, the gate-source voltage of the driving transistor Md 1  corresponds to the threshold voltage of the driving transistor Md 1 . 
     When the switching transistor Ms 1  is turned on, the data voltage from the data line Dm is applied to the source electrode of the driving transistor Md 1 . If the data voltage from the data line Dm is Vdata and the threshold voltage of the driving transistor Md 1  is Vth (e.g., a negative voltage), the gate voltage of the driving transistor Md 1  corresponds to Vdata+Vth. 
     Subsequently, the transistor M 13  is turned on by the enable signal transmitted through the main light emission control line En- 1 . 
     The transistor M 14  is turned on by the enable signal transmitted through the first sub-light-emission control line EM_Tk, enabling the first light emitting element OLED 11  to emit light. 
     The transistor M 15  is turned on by the enable signal transmitted through the third sub-light-emission control line EM_Vk, enabling the third light emitting element OLED 12  to emit light. 
     Here, the gate-source voltage of the driving transistor Md 1  is represented by Equation 1.
 
 Vgs =( V data+ Vth )− ELVDD   [Equation 1]
 
     Here, Vgs denotes the gate-source voltage of the driving transistor Md 1 , Vth denotes the threshold voltage of the driving transistor Md 1 , and Vdata denotes the data voltage transmitted through the data line Dm. Current flows through the first light emitting element OLED 11  through the driving transistor Md 1  to emit light. 
     Current flowing through the first light emitting element OLED 11  and the third light emitting element OLED 12  is represented by Equation 2.
 
IOLED=β/2( Vgs−Vth )^2=β/2(( V data+ Vth−ELVDD )− Vth )^2=β/2(( V data− ELVDD )^2  [Equation 2]
 
     Here, IOLED denotes current flowing through the first light emitting element OLED 11  and the third light emitting element OLED 12 , and β denotes a constant. 
     The second pixel circuit PX 2  includes the switching transistor Ms 2 , the driving transistor Md 2 , a plurality of transistors M 21  to M 25 , capacitors C 21  and Cboost 2 , the second light emitting element OLED 21 , and the fourth light emitting element OLED 22 . 
     According to an embodiment of the present invention, the switching transistor Ms 2  includes a gate electrode coupled to the scan line Gwn, a source electrode coupled to the data line Dm, and a drain electrode coupled to the source electrode of the driving transistor Md 2 . The switching transistor Ms 2  is turned on by a scan signal applied to the scan line Gwn to deliver a data voltage applied to the data line Dm to the source electrode of the driving transistor Md 2 . 
     The driving transistor Md 2  includes a source electrode to which the data voltage is applied when the switching transistor Ms 2  is turned on, a gate electrode coupled to the first terminal of the capacitor C 21 , and a drain electrode coupled to the source electrode of the transistor M 24 . The second terminal of the capacitor C 21  is coupled to the voltage source generating the driving voltage ELVDD. 
     The transistor M 21  includes a gate electrode coupled to the scan line Gwn, a source electrode coupled to the gate electrode of the driving transistor Md 2 , and a drain electrode coupled to the drain electrode of the driving transistor Md 2 . The transistor M 21  is turned on by the scan signal applied to the scan line Gwn to diode-connect the driving transistor Md 2 . 
     The first terminal of the capacitor Cboost 2  is coupled to the scan line Gwn and the second terminal thereof is coupled to the source electrode of the transistor M 21 . 
     The transistor M 22  includes a gate electrode coupled to the scan line Gin, a source electrode coupled to the voltage source generating the initialization voltage Vint, and a drain electrode coupled to the gate electrode of the driving transistor Md 2 . 
     The transistor M 23  includes a gate electrode coupled to the main light emission control line En, a source electrode coupled to the voltage source generating the driving voltage ELVDD, and a drain electrode coupled to the source electrode of the driving transistor Md 2 . 
     The transistor M 24  includes a gate electrode coupled to the second sub-light-emission control line EM_Uk, a source electrode coupled to the drain electrode of the driving transistor Md 2 , and a drain electrode coupled to the anode of the second light emitting element OLED 21 . 
     The cathode of the second light emitting element OLED 21  is coupled to the voltage source generating the driving voltage ELVSS. The second light emitting element OLED 21  emits light according to current flowing through the driving transistor Md 2  when the transistor M 24  is turned on by a light emitting signal delivered through the second sub-light-emission control line EM_Uk. 
     The transistor M 25  includes a gate electrode coupled to the fourth sub-light-emission control line EM_Wk, a source electrode coupled to the drain electrode of the driving transistor Md 2 , and a drain electrode coupled to the anode of the fourth light emitting element OLED 22 . 
     The cathode of the fourth light emitting element OLED 22  is coupled to the voltage source generating the driving voltage ELVSS. The fourth light emitting element OLED 22  emits light according to current flowing through the driving transistor Md 2  when the transistor M 25  is turned on by a light emitting signal delivered through the fourth sub-light-emission control line EM_Wk. 
     The transistor M 22  is turned on by the enable signal transmitted through the scan line Gin, and thus the initialization voltage Vint is applied to the gate electrode of the driving transistor Md 2  and the capacitor C 21  maintains a voltage ELVDD-VINT. Subsequently, the switching transistor Ms 2  and the transistor M 21  are turned on by the enable signal transmitted through the scan line Gwn. 
     When the transistor M 21  is turned on, the driving transistor Md 2  enters a diode-connected state. Accordingly, the gate-source voltage of the driving transistor Md 2  corresponds to the threshold voltage of the driving transistor Md 2 . 
     When the switching transistor Ms 2  is turned on, the data voltage from the data line Dm is applied to the source electrode of the driving transistor Md 2 . If the data voltage from the data line Dm is Vdata and the threshold voltage of the driving transistor Md 2  is Vth (e.g., a negative voltage), the gate voltage of the driving transistor Md 2  corresponds to Vdata+Vth. 
     Subsequently, the transistor M 23  is turned on by the enable signal transmitted through the main light emission control line En. 
     The transistor M 24  is turned on by the enable signal transmitted through the second sub-light-emission control line EM_Uk, thus enabling the second light emitting element OLED 21  to emit light. 
     The transistor M 25  is turned on by the enable signal transmitted through the fourth sub-light-emission control line EM_Wk, thus enabling the fourth light emitting element OLED 22  to emit light. 
     Here, the gate-source voltage of the driving transistor Md 2  is represented by Equation 1, and current flowing through the second light emitting element OLED 21  and the fourth light emitting element OLED 22  is represented by Equation 2. 
     While  FIG. 3  shows the transistors Ms 1 , Ms 2 , Md 1 , Md 2 , M 11  to M 15 , and M 21  to M 25  as p-channel MOS transistors, any suitable transistors having functions similar to those of the p-channel MOS transistors may replace the p-channel MOS transistors. 
       FIG. 4A  is a timing diagram showing driving times of the first subframe for explaining operation of the pixel group shown in  FIG. 3 , and  FIG. 4B  is a timing diagram showing driving times of the second subframe. 
       FIG. 4A  shows the driving times for the first subframe only and  FIG. 4B  shows the driving times for the second subframe only, for better understanding and ease of description. According to an embodiment of the present invention, a plurality of pixel groups may have the same pixel structure, and the pixel group PX shown in  FIG. 3  may be applied to other OLED display devices. The reference numerals of the transistors shown in  FIG. 3  are applied to transistors in other pixel groups for better understanding and ease of description. 
     Referring to  FIGS. 4A and 4B , according to an embodiment of the present invention, a frame includes the first subframe  1 SF and the second subframe  2 SF. The first subframe  1 SF includes a plurality of scan periods T 1  to Tn and a plurality of light emitting periods L 1  to Ln, whereas the second subframe  2 SF includes a plurality of scan periods T 1 ′ to Tn′ and a plurality of light emitting periods M 1  to Mn. 
     The enable signal is applied to the scan line Gi 1  at the start point of the scan period T 1  of the first subframe  1 SF. Then, the transistor M 12  is turned on and thus the initialization voltage Vint is applied to the gate electrode of the driving transistor Md 1 , and the capacitor C 11  maintains the voltage ELVDD-Vint. 
     The enable signal is applied to the scan line Gi 2  at the start point of the scan period T 2 . Then, the transistor M 22  is turned on and thus the initialization voltage Vint is applied to the gate electrode of the driving transistor Md 2 , and the capacitor C 21  maintains the voltage ELVDD-Vint. 
     Subsequently, the enable signal is applied to the scan line Gw 1  at the start point of the scan period T 3 . Then, the switching transistor Ms 1  and the transistor M 11  are turned on. 
     When the transistor M 11  is turned on, the driving transistor Md 1  enters a diode-connected state. Accordingly, the gate-source voltage of the driving transistor Md 1  corresponds to the threshold voltage of the driving transistor Md 1 . 
     When the switching transistor Ms 1  is turned on, a data voltage from the data line D 1  is applied to the source electrode of the driving transistor Md 1 . 
     The enable signal is applied to the main light emission control line E 1  and the first sub-light-emission control line EM_T 1  at the start point of the light emitting period L 1 . The transistor M 13  is turned on by the enable signal applied through the light emission control line E 1 , and the transistor M 14  is turned on by the enable signal applied through the first sub-light-emission control line EM_T 1 . Accordingly, the first light emitting element OLED 11  emits light according to current flowing through the driving transistor Md 1  during the light emitting period L 1 . 
     Subsequently, the enable signal is applied to the scan line Gw 2  at the start point of the scan period T 4 . Then, the switching transistor Ms 2  and the transistor M 21  are turned on. 
     When the transistor M 21  is turned on, the driving transistor Md 2  enters a diode-connected state. Accordingly, the gate-source voltage of the driving transistor Md 2  corresponds to the threshold voltage of the driving transistor Md 2 . 
     When the switching transistor Ms 2  is turned on, the data voltage from the data line D 1  is applied to the source electrode of the driving transistor Md 2 . 
     The enable signal is applied to the main light emission control line E 2  and the second sub-light-emission control line EM_U 1  during the light emitting period L 2 . Then, the transistor M 23  is turned on by the enable signal applied through the main light emission control line E 2 , and the transistor M 24  is turned on by the enable signal applied through the second sub-light emission control line EM_U 1 . Accordingly, the second light emitting element OLED 21  emits light according to current flowing through the driving transistor Md 2  during the light emitting period L 1 . 
     A disable signal is applied to the second sub-light-emission control line EM_V 1  and the fourth sub-light-emission control line EM_W 1  in the first subframe  1 SF, and thus the transistor M 15  and the transistor M 25  are turned off in the first subframe  1 SF. 
     In this way, data signals corresponding to image data signals DAT are sequentially written to corresponding pixel groups PX through corresponding data lines from among the plurality of data lines D 1  to Dm in the plurality of scan periods T 1  to Tn. Light emitting elements corresponding to the data signals written during the plurality of light emitting periods L 1  to Ln sequentially emit light. 
     While  FIG. 4A  shows, according to an embodiments, that the enable signal is applied to the main light emission control line E 1  during the light emitting period L 1  and the enable signal is applied to the main light emission control line E 2  during the light emitting period L 2 , the present invention is not limited thereto, and the enable signal can be applied in the first subframe  1 SF. 
     Referring to  FIG. 4B , the enable signal is applied to the scan line Gi 1  at the start point of the scan period T 1 ′ of the second subframe  2 SF. Then, the transistor M 12  is turned on and thus the initialization voltage Vint is applied to the gate electrode of the driving transistor Md 1  and the capacitor C 11  maintains the voltage ELVDD-Vint. 
     The enable signal is applied to the scan line Gi 2  at the start point of the scan period T 2 ′. Then, the transistor M 22  is turned on and thus the initialization voltage Vint is applied to the gate electrode of the driving transistor Md 2  and the capacitor C 21  maintains the voltage ELVDD-Vint. 
     Subsequently, the enable signal is applied to the scan line Gw 1  at the start point of the scan period T 3 ′. Then, the switching transistor Ms 1  and the transistor M 11  are turned on. 
     When the transistor M 11  is turned on, the driving transistor Md 1  enters a diode-connected state. Accordingly, the gate-source voltage of the driving transistor Md 1  corresponds to the threshold voltage of the driving transistor Md 1 . 
     When the switching transistor Ms 1  is turned on, a data voltage from the data line D 1  is applied to the source electrode of the driving transistor Md 1 . 
     The enable signal is applied to the main light emission control line E 1  and the third sub-light-emission control line EM_V 1  at the start point of the light emitting period M 1 . Then, the transistor M 13  is turned on by the enable signal applied through the light emission control line E 1 , and the transistor M 15  is turned on by the enable signal applied through the third sub-light-emission control line EM_V 1 . Accordingly, the third light emitting element OLED 12  emits light according to a current flowing through the driving transistor Md 1  during the light emitting period M 1 . 
     Subsequently, the enable signal is applied to the scan line Gw 2  at the start point of the scan period T 4 ′. Then, the switching transistor Ms 2  and the transistor M 21  are turned on. When the transistor M 21  is turned on, the driving transistor Md 2  enters a diode-connected state. Accordingly, the gate-source voltage of the driving transistor Md 2  corresponds to the threshold voltage of the driving transistor Md 2 . When the switching transistor Ms 2  is turned on, the data voltage from the data line Dm is applied to the source electrode of the driving transistor Md 2 . 
     The enable signal is applied to the main light emission control line E 2  and the fourth sub-light-emission control line EM_W 1  during the light emitting period M 2 . Then, the transistor M 23  is turned on by the enable signal applied through the main light emission control line E 2 , and the transistor M 25  is turned on by the enable signal applied through the fourth sub-light emission control line EM_W 1 . Accordingly, the fourth light emitting element OLED 22  emits light according to current flowing through the driving transistor Md 2  during the light emitting period M 2 . 
     A disable signal is applied to the first sub-light-emission control line EM_T 1  and the third sub-light-emission control line EM_U 1  in the second subframe  2 SF, and thus the transistor M 14  and the transistor M 24  are turned off in the second subframe  2 SF. 
     In this way, data signals corresponding to image data signals DAT are sequentially written to corresponding pixel groups PX through corresponding data lines from among the plurality of data lines D 1  to Dm in the plurality of scan periods T 1 ′ to Tn′. Light emitting elements corresponding to the data signals written during the plurality of light emitting periods M 1  to Mn sequentially emit light. 
     While  FIG. 4B  shows that the enable signal is applied to the main light emission control line E 1  during the light emitting period M 1  and the enable signal is applied to the main light emission control line E 2  during the light emitting period M 2 , the present invention is not limited thereto, and the enable signal can be applied in the second subframe  1 SF. 
     TFTs of pixels have different threshold voltages Vth due to non-uniform manufacturing processes and thus different quantities (or amounts) of current are supplied to OLEDs. Accordingly, the OLEDs have different luminances. However, according to the embodiments of the present invention, a uniform quantity of current can be supplied to the first to fourth OLEDs even when the driving transistors Md 1  and Md 2  of each pixel group PX have different threshold voltages, as represented by Equation 2, because the influence of the threshold voltage difference can be reduced or eliminated. Accordingly, it is possible to control luminance non-uniformity according to positions of the pixels PX. 
     While this invention has been described in connection with what is presently considered to be practical example embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, to the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. 
     
       
         
               
             
               
               
               
             
           
               
                   
               
               
                 Description of Symbols 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 100: signal controller 
                 200: scan driver 
               
               
                   
                 300: data driver 
                 400: light emission driver 
               
               
                   
                 500: display 
                 PX: pixel group 
               
               
                   
                 PX1: first pixel circuit 
                 PX2: second pixel circuit