Abstract:
An electrical connectors with electrodeposited terminals that are grown in place by electroplating cavities formed in a series of resist layers. The resist layers are subsequently stripped away. The resulting terminal shape is defined by the shape of the cavity created in the resist layers. Complex terminal shapes are possible. The present conductive terminals are particularly useful for electrical interconnects and semiconductor packaging substrates.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application is a continuation of U.S. Ser. No. 15/062,137 (U.S. Pat. No. 9,761,520), filed Mar. 6, 2016 (Issued Sep. 12, 2017), entitled Electrodeposited Contact Terminal for Use as an Electrical Connector or Semiconductor Packaging Substrate, which claims the benefit of U.S. provisional application 62/134,936, filed Mar. 18, 2015, entitled Electrodeposited Contact Terminal for Use as an Electrical Connector or Semiconductor Packaging Substrate, the entire disclosure of which is hereby incorporated by reference. 
         [0002]    This application is a continuation-in-part of U.S. patent Ser. No. 14/408,039, filed Dec. 15, 2014, entitled HIGH SPEED CIRCUIT ASSEMBLY WITH INTEGRAL TERMINAL AND MATING BIAS LOADING ELECTRICAL CONNECTOR ASSEMBLY, which is a national stage application under 35 U.S.C. 371 of International Application No. PCT/US2013/30981, filed Mar. 13, 2013, which claims the benefit of U.S. Provisional Application No. 61/669,893, filed Jul. 10, 2012, the disclosure of which is hereby incorporated by reference. 
     
    
     TECHNICAL FIELD 
       [0003]    The present disclosure relates to electrical connectors with electrodeposited terminals that are grown in place by electroplating cavities formed in a series of resist layers. The resist layers are subsequently stripped away. Complex terminal shapes are possible because the resulting terminal shape is defined by the shape of the cavity created in the resist layers. The present electrical connectors are particularly useful for electrical interconnects and semiconductor packaging substrates. 
       BACKGROUND OF THE INVENTION 
       [0004]    Electrical interconnects and package substrates experience challenges as the feature sizes and line spacing are reduced to achieve further miniaturization and increased circuit density. The use of laser ablation has become increasingly used to create the via structures for fine line or fine pitch structures. The use of lasers allows localized structure creation, where the processed circuits are plated together to create via connections from one layer to another. As density increases, however, laser processed via structures can experience significant taper, carbon contamination, layer-to-layer shorting during the plating process due to registration issues, and high resistance interconnections that may be prone to result in reliability issues. The challenge of making fine line PCBs often relates to the difficulty in creating very small or blind and buried vias. 
         [0005]    The process used by current technology is based upon a dry film process, where a substrate of some sort has a copper layer as the base circuit layer onto which a dry film is applied. The dry film is then patterned with a laser to create the circuit patterns. The next copper layer is added and etched as appropriate, with the laser used to drill through the film to expose the previous copper layer so a via can be plated to join the circuit layers. This process is typically used for semiconductor package substrates and larger format circuit boards, such as used in a cell phone. For larger format circuit boards, the dry film technology is used to build fine line circuits on top of base circuit board made with conventional low density lamination techniques. 
         [0006]    In both cases, the package substrate and the larger format circuit board build up are very expensive compared to traditional low density laminate technology, and suffer from several limitations inherent to the process. For example, in the case where a low density laminate base is used as the starting point for subsequent high density layers are built up, the cost increases dramatically since the entire surface of the lower density base board must be processed with the build up process across the entire area, not just in the areas where the high density is required. 
         [0007]    Another limitation is the reliability of the via structures joining one circuit layer to another, which tend to be a barrel plated structures with the side walls of the via plated and in many cases must be filled with a via fill material to eliminate an air pocket which may separate during solder reflow temperatures. The vias require drilling through the dry film to expose the previous circuit layer in order to create the via that connects the circuit layers. The dry film is applied as a solid contiguous sheet where the material on that particular layer is restricted to that particular material across the entire layer in the build up less the areas ablated to create the via target for joining the previous and subsequent circuit layers. That is, the dry layer film is homogeneous across the entire layer. 
       BRIEF SUMMARY OF THE INVENTION 
       [0008]    The present disclosure relates electrical connectors with resist defined electrodeposited terminals. The terminal shape is defined by the shape of the cavity created in the resist layers, so complex terminal shapes are possible. The present electrical connectors are particularly useful for electrical interconnects and semiconductor packaging substrates. 
         [0009]    One embodiment is directed to a method of making an electrical connector with electrodeposited terminals. The method includes preparing a substrate with a plurality of openings corresponding to a desired arrangement of the electrodeposited terminals. A first resist layer is deposited on a first surface of the substrate with a plurality of first through holes aligned with the openings in the substrate. The first through holes are electroplated so that the holes and at least a portion of the openings in the substrate are substantially filled with a conductive material. A second resist layer is deposited on the first resist layer to create a plurality of second through holes having second cross-sectional shapes that at least partially overlap with the conductive material in the first through holes. The second cross-sectional shapes of the second through holes preferably extend beyond the first cross-sectional shapes. The second through holes are electroplated so the second through holes are substantially filled with a conductive material. The first and second resist layers are removed to expose electrodeposited terminals attached to the substrate. The electrodeposited terminals have neck portions corresponding to the first cross-sectional shapes of the first through holes and distal portions corresponding to the second cross-sectional shapes of the second through holes. The distal portions and at least a portion of the neck portions extend above the first surface of the substrate and the distal portions include cantilevered portions that extend beyond the neck portions. A dielectric material is optionally deposited on a second surface of the substrate with terminal openings aligned with proximal portions of the electrodeposited terminals. 
         [0010]    One embodiment includes positioning electrical terminals of a circuit member in the terminal openings in the substrate so the electrical terminals are electrically coupled with the proximal portions of the electrodeposited terminals. In another embodiment, the terminal openings are plated and the method includes plastically deforming at least one of the solder terminals on the BGA device or the plating in the terminal openings to electrically couple the solder terminals to the electrodeposited terminals. One embodiment includes positioning solder terminals on a BGA device in the terminal openings in the substrate and reflowing the solder terminals to electrically couple the solder terminals on the BGA device to the electrodeposited terminals. It is also possible to omit the dielectric material on the second surface of the substrate and directly couple a flexible circuit member to proximal portions of the electroplated terminals. 
         [0011]    In another embodiment a third resist layer is deposited on the second resist layer to create a plurality of third through holes having third cross-sectional shapes that at least partially overlap with the conductive material in the second through holes. The second and third through holes are preferably configured so the electrodeposited terminals have two cantilevered portions extending in different directions relative to the neck portion. The present method can also be used to create conductive extensions on proximal ends of the electrodeposited terminals that extend upward in the terminal openings. 
         [0012]    The present electrodeposited terminals may include undercuts that facilitates electrical and mechanical coupling with spring contact members. The distal ends of the electrodeposited flex the spring contact members to create a compression or snap-fit engagement. In one embodiment, protrusions on the spring contact members engage with the neck portions and are captured against the distal ends of the electrodeposited terminals. The spring contact members preferably include opposing beams with opposing protrusions that mechanically retain the electrical connector to the interconnect. The neck portions can optionally include features, such as a recess, to engage with the protrusions. 
         [0013]    The present disclosure is also directed to an electrical assembly that includes an electrical connector having a substrate with a plurality of electrodeposited terminals. The electrodeposited terminals include neck portions with a first cross-sectional shape and distal portions having a second cross-sectional shape larger than the first cross sectional shape. The distal portions and at least a portion of the neck portions extend above the first surface of the substrate and the distal portions include cantilevered portions that extend beyond the neck portions. A dielectric material is located on a second surface of the substrate with terminal openings aligned with proximal portions of the electrodeposited terminals. A first circuit member includes raised electrical terminals positioned in the terminal openings and electrically coupled to the proximal portions of the electrodeposited terminals. A second circuit member is electrically coupled to the distal ends of the electrodeposited terminals. 
         [0014]    In one embodiment, inside surfaces of the terminal openings are plated and the first circuit member comprises a BGA device with solder terminals electrically coupled with the plating in the terminal openings. In another embodiment, the distal portions of the electroplated terminals include two cantilevered portions that extend beyond the neck portions in different directions relative to the neck portion. The second circuit member is optionally an electrical interconnect having spring contact members located in openings. The spring contacts include protrusions that form a snap-fit engagement with the neck portions of the electrodeposited terminals. 
         [0015]    The present disclosure is also directed to a method of coupling a flexible circuit with the extensions on the electrodeposited terminals located along the second surface of the substrate. The extensions are positioned in openings in a flexible circuits and electrically couple with circuit traces in the flexible circuit. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING 
         [0016]      FIGS. 1A through 1G  illustrate various method of making an electrical connector with resist defined electroplated terminals in accordance with an embodiment of the present disclosure. 
           [0017]      FIGS. 2A and 2B  are side views of an electrical interconnect with electroplated terminals coupled to a BGA device in accordance with an embodiment of the present disclosure. 
           [0018]      FIG. 3  is a side view of an alternate electrical interconnect with electroplated terminals coupled to a BGA device in accordance with an embodiment of the present disclosure. 
           [0019]      FIGS. 4A and 4B  illustrate alternate neck portions for electroplated terminals in accordance with an embodiment of the present disclosure. 
           [0020]      FIGS. 5A through 5D  illustrate various electrical assemblies an electrical connector with resist defined electroplated terminals in accordance with an embodiment of the present disclosure. 
           [0021]      FIGS. 6A and 6B  illustrate an electrical connector with resist defined electroplated terminals coupled to a flexible circuit member in accordance with an embodiment of the present disclosure. 
           [0022]      FIG. 7  illustrate an alternate electrical connector with resist defined electroplated terminals coupled to a flexible circuit member in accordance with an embodiment of the present disclosure. 
           [0023]      FIG. 8  is a side view of an electrical interconnect with electroplated terminals and internal ground planes coupled to a BGA device in accordance with an embodiment of the present disclosure. 
           [0024]      FIG. 9  illustrates an alternate way to coupled electroplated terminals to contact members in accordance with an embodiment of the present disclosure. 
           [0025]      FIGS. 10A and 10B  illustrate alternate way to coupled electroplated terminals to contact members in accordance with an embodiment of the present disclosure. 
           [0026]      FIG. 11  is a cross sectional view of an electroplated terminal soldered to a circuit member in accordance with an embodiment of the present disclosure. 
           [0027]      FIG. 12  illustrates solder deposited on a distal end of an electroplated terminal in accordance with an embodiment of the present disclosure. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0028]      FIGS. 1A-1E  illustrate a method of making an electrical connector  50  with resist defined electroplated terminals  62  in accordance with an embodiment of the present disclosure. In the illustrated embodiment, temporary copper bus  52  is deposited on substrate  54 . Resist layer  56 A is deposited on the copper bus  52  with through holes  58 A into which the resist defined electroplated terminals will be formed. The copper bus  52  enhances bulk copper electro plating. In one embodiment, the copper bus  52  is subsequently removed with a differential etch process that leaves terminals  62  intact (see e.g.,  FIG. 1E ). 
         [0029]    As best illustrated in  FIGS. 1A through 1C , one or more resist layers  56 A,  56 B,  56 C (“ 56 ”) of an imageable or ablateable plating resist are deposited on the copper bus  52  with through holes or recesses  58 A,  58 B,  58 C (“ 58 ”) that define the shape of the electroplated terminals  62 . The through holes  58  can have the same or a different cross-sectional shape (see e.g.,  FIGS. 1G, 4A and 4B ). Any cross-sectional shape is possible, including round, square, triangular, irregular or random, and the like, and the cross-sectional shape can vary from layer-to-layers  56 . 
         [0030]    In the preferred embodiment, plating  60 A is deposited in through holes  58 A, before resist layer  56 B is deposited. Resist layer  56 B is then deposited, followed sequentially by plating  60 B, resist layer  56 C and plating  60 C. This sequential process minimizes the risk of plating defects, such as voids. In an alternate embodiment, multiple layers  56  can be deposited before the plating  60 . In the preferred embodiment, the resist  56  is a liquid material that is imaged to create the through holes  58 . One or more of the resist layers  56  are optionally planarized to create a very consistent dielectric thickness and planarity, as well as assist with preparing select surfaces for electro-less copper plating adhesion. 
         [0031]    In an alternate embodiment, layer  56 B is constructed from a different dielectric material, such as for example, a liquid crystal polymer. In one embodiment, the layer  56 B is a sheet of LCP with a series of through holes  58 B corresponding to the desired arrangement of the electrodeposited terminals. Resist layer  56 A is added and imaged to create the through holes  58 A, followed by a plating step to add electrical bus  52 . The remainder of the process is as discussed herein. When the resist layers  56 A,  56 C, and  56 D are removed, all that remains are the terminals  62  and the core layer  56 B. 
         [0032]    The present method permits the material between the resist layers  56  and within each layer to be varied. One aspect of the present process that differs from the traditional dry film build up process is the nature of the dielectric deposition in liquid form. The resist layers  56  can be applied by screen printing, stencil printing, jetting, flooding, spraying etc. The liquid material  56  flows and fills any recessed regions within a previous circuit landscape. During the development process, desired regions remain and the regions that are not desired are washed away with fine resolution of the transition regions within the landscape. Multiple depositions steps can be tack cured and imaged such that thicker sections of resist layers  56  can be developed and washed away in one or multiple strip operations. As a result, internal cavities or mass regions can be excavated and subsequently filled at the next dielectric layer with materials that have physical properties differing from the base resist layer  56 . In other words, the excavated regions can be filled or treated with materials that have a different dielectric constant, vary in conductive or mechanical or thermal properties to achieve a desired performance function not possible with a contiguous dry film technique. In basic terms, the present process not only provides the ability to alter the material set and associated properties in a given layer, but the material set can be altered at any given point within a given deposition or layer. 
         [0033]    As illustrated in  FIG. 1D , final resist layer  56 D is applied with through holes  58 D having cross-sectional shapes different than the cross-sectional shapes of at least the through holes  58 C. In the illustrated embodiment, the cross-sectional shapes of the through holes  58 D extends beyond entire cross-sectional shapes of the through holes  58 C, creating circumferential undercuts  68 . The through holes  58 D are then plated. 
         [0034]    Upon reaching the desired terminal formation some or all of the resist layers are stripped. In the embodiment of  FIG. 1E , the resist layers  56 A,  56 C and  56 D are removed to exposed the free standing electroplated terminals  62  is exposed. Layer  56 B acts as the core support for the terminals  62 . The temporary copper bus  52  and substrate  54  are also preferably removed. In the illustrated embodiment, the terminals  62  include a plurality of contact surfaces or facets  64 A,  64 B,  64 C (“ 64 ”) that can potentially electrically and mechanically couple with another circuit member. Neck portions  66  provide undercuts  68  that cannot be formed using dry film technology. An optional domed or radius edge  70  can be added to the terminal  62  either by plating or solder deposition. 
         [0035]    Multiple layers of resist  56  can be built up and a variety of terminal shapes can be created as a function of the resist thickness and the shape of the target opening where plating is deposited to the previous target layer while not depositing onto the resist. The terminals  62  can be a variety of shapes, such as for example, cylindrical or non-cylindrical, regular or irregular, symmetrical or asymmetrical, rectangular, curvilinear, and the like. For example, the neck portion  66  can optionally be formed with features, such as the recesses illustrated in  FIGS. 4A and 4B . The resist layers  56  also permit the creation of internal features, undercuts, or cavities that are difficult or typically not possible to make using conventional molding or machining techniques, referred to herein as a “non-moldable feature.” 
         [0036]    While a single terminal is shown in  FIG. 1E , fields of terminals  62  in mass quantities can be created simultaneously and mass plated with final finish as desired. For some applications such as with a semiconductor package, rigid or flex circuit that may benefit from a solder terminal either for final reflow or temporary connection, the terminal  62  can be constructed of solder. 
         [0037]    As illustrated in  FIG. 1F , dielectric layer  72  is be added to second surface  74  of the layer  56 B. In one embodiment, the dielectric layer  72  is a liquid crystal polymer material processed to create through holes  78 . Use of liquid crystal polymers in electrical connectors is disclosed in commonly assigned U.S. patent application Ser. No. 14/864,215, filed Sep. 24, 2015, entitled Fusion Bonded Liquid Crystal Polymer Circuit Structure, which is hereby incorporated by reference. 
         [0038]    The second surface  76  of the terminal  62  is exposed in recess  78  in the dielectric layer  72 . Sidewalls  80  of the recess  76  optionally include plating  82 . In one embodiment, optional conductive extension  84  is formed on the rear surface  76  of the terminal  62  using the resist/plating processes discussed herein. 
         [0039]    The dielectric layer  72  is optionally processed to enable electro-less or electrolytic copper plating to adhere to the sidewalls  80 , such as one or more of plasma treatment, permanganate, carbon treatment, impregnating copper nano-particles, and the like. Once the surfaces  80  are plated, a higher deposition rate electroplate copper can be applied to build up the thickness or area of copper as desired. Additional discussion of electro-less plating of the dielectric structure is disclosed in commonly assigned U.S. patent Ser. No. 14/238,638, filed Sep. 6, 2012, entitled DIRECT METALIZATION OF ELECTRICAL CIRCUIT STRUCTURES, the entire of disclosure of which is hereby incorporated by reference. 
         [0040]    Neck portion  66  of the terminal  62  has a first cross-sectional shape  86  and the distal portion  88  has a second cross-sectional shape  90  that is larger than the first cross-sectional shape  86 . The second cross-sectional shape  90  extends beyond all edges of the first cross-sectional shape  86  creating a circumferential undercut  68 . The undercut  68  may be uniform around the perimeter of the terminal  62 , or offset. 
         [0041]      FIG. 1G  illustrates some alternate electrical connector  500  with electrodeposited terminals  502 ,  504 ,  506  of various shapes in accordance with an embodiment of the present disclosure. The terminal  502  includes neck portion  510  and distal portion  512  configured with cantilevered portion  514  that extends beyond the perimeter of the neck portion  510 . The cross-sectional shapes of the neck portion  510  and distal portion  512  can be the same or different. For example, the neck portion  510  can be oval shaped, while the distal portion  512  is rectangular. 
         [0042]    Terminal  504  includes stepped structure where neck portion  520  has a first cross-sectional shape  522  and a second cross-sectional shape  524  larger than the first cross-sectional shape  522 . Distal portion  526  has a third cross-sectional shape  528  larger than both the first and second cross-sectional shapes  522 ,  524 . The cross-sectional shapes  522 ,  524 ,  528  can be the same or different. 
         [0043]    Terminal  506  includes neck portion  530 , intermediate cantilever portion  532 , and distal portion  534  cantilevered in a different direction. The cross-sectional shape  536  of the intermediate cantilevered portion  532  may be the same as the cross-sectional shape  538  of the distal portion  534 , just offset in different directions. Alternatively, the cross-sectional shapes  536 ,  538  may be different sizes or shapes. 
         [0044]    The present method permits fine contact-to-contact spacing (pitch) on the order of less than 1.0 mm pitch, and more preferably a pitch of less than about 0.7 millimeter, and most preferably a pitch of less than about 0.4 millimeter. The present high density terminals  62  can be configured as a low cost, high signal performance electrical interconnect assembly or socket, which has a low profile that is particularly useful for desktop and mobile PC applications. IC devices can be installed and uninstalled without the need to reflow solder. The solder-free electrical connection of the IC devices is environmentally friendly. In another embodiment, the high density circuit structure can also be a portion of a socket or semiconductor package. 
         [0045]      FIGS. 2A and 2B  illustrate an application of electrical connector  100  with resist defined electroplated terminals  102  in accordance with an embodiment of the present disclosure. Base core layer  104  is processes with multiple layers of plating resist which are imaged and developed or ablated to create the resultant terminals  102 , as discussed herein. Upper core  106  is processes to create a plated terminal openings  108  that are in proximity to the upper surface  110  of the terminals  102 . 
         [0046]    In one embodiment, the electrical connector  100  is mated with circuit member  112 . The circuit member  112  can be a semiconductor package, bare die, rigid, flexible or hybrid rigid flexible printed circuit is mated with the upper core  106 . In the illustrated embodiment, the circuit member  112  is a BGA device with solder terminals  114  positioned in the plated terminal openings  108 . 
         [0047]    The electrical connection between the solder balls  114  on the circuit member  112  and the terminals  102  can be created by reflow to create the mechanical and electrical connection. In another embodiment, the solder terminal  114  and/or the plated sidewalls  109  are plastically deformed during engagement to create electrical connection in a manner that does not require reflow of the solder terminals  114 . In some embodiments, a retention lid is used to maintain loading  111  of the solder terminals  114  in the terminal openings  108 . In an embodiment where the terminal openings  108  are not plated, the terminal openings  108  only provides locational positioning for the solder balls  114  and support while the solder balls  114  is reflowed and connects directly to the terminals  102 . This embodiment permits for “pin like” terminal  102  to be grown in position and connected to a desired circuit member, such as for example BOA device  112 . 
         [0048]    In another embodiment, the terminals  102  can be plated with nickel and gold to create an interface conducive to mating with a socket or connector, or the terminal  102  can be reflow soldered directly to another circuit. For example, domed end  116  can be solder that is reflowed to attach the electrical connector  100  directly to another circuit member, such as for example PCB  122 . 
         [0049]      FIG. 2B  is a sectional view of an alternate system for electrically coupling the terminals  102  in accordance with an embodiment of the present disclosure. In the illustrated embodiment, interconnect  120  couples the terminals  102  to second circuit member  122 , such as a PCB. Spring contact members  124  are then located within interconnect housing  126 . The spring contact members  124  include one or more beams  128  that are permitted to flex within the housing  126 . 
         [0050]    In the illustrated embodiment, protrusion  130  at distal ends of the beams  128  are configured to engage with the terminals  102 , causing the beams  128  to flex outward in direction  132 . The domed end  116  reduces the required insertion past the protrusions  130 . 
         [0051]    As best illustrated in  FIG. 2B , once the terminals  102  on the circuit member  100  are fully engaged with the interconnect  120 , the protrusions  130  are biased by the elastic properties of the beams  128  into engagement with neck portion  134  of the terminals  102  to create both a mechanical and electrical connection. In one embodiment, the beams  128  create bias force  136  to retain the circuit member  100  to the interconnect  120 . An external fixation mechanism may also be used to secure the circuit member  100  to the interconnect  120 . 
         [0052]      FIG. 3  illustrates an alternate circuit member  150  with extension  154  attached to proximal ends of terminals  152 . The extension  154  adds a connection point that facilitates electrical coupling with the solder terminals  114  on the BOA device  112 . The electrical connection that can be made by reflow of the solder terminals  114 , or compression or plastic deformation of the solder terminal  114 . Plated side walls  156  are optional. 
         [0053]      FIGS. 4A and 4B  illustrate variations in the resist defined electroplated terminals  152  illustrated in  FIG. 3 . In particular, neck portion  158  of the terminal  152  can include recesses  160 A,  160 B (“ 160 ”) configured to receive the protrusions  130  on the beams  128 . In one embodiment, the recesses  160  have a shape complementary with the protrusions  130  on the beams  128 . 
         [0054]      FIG. 5A-5D  illustrate various assemblies using electrical connectors with electroplated terminals in accordance with embodiments of the present disclosure. 
         [0055]      FIG. 5A  illustrates an electrical interconnector  200  configured to provide internal routing and contact distribution. Flip chip or die level terminals  202  are located on top surface and a plurality of electroplated terminals  204  extend above the bottom surface. The electroplated terminals  204  can be soldered to PCB  206  or can be electrically coupled using other techniques disclosed herein (see e.g.,  FIGS. 2A and 3 ). 
         [0056]      FIG. 5B  illustrates an electrical interconnect  220  with routing and circuitry extensions  222  electrically coupled to multiple discrete devices  224 ,  226 , such as for example, IC devices, packages, discrete components, connectors and probes, sensors, cameras, antennae, filters, and the like. In the illustrated embodiment, electroplated terminals  228  of the assembly  232  are electrically coupled to PCB  230 . 
         [0057]      FIG. 5C  illustrates the electroplated terminals  228  of the assembly  232  of  FIG. 5B  plugged into the socket or connector  234 , such as illustrated in  FIG. 3 . The structure of the electroplated terminals  228  permit the assembly  232  to be removed disconnected from the socket  234 . In the illustrated embodiment, the socket  234  is soldered to the PCB  236 . 
         [0058]      FIG. 5D  illustrates a variation of the electrical interconnect  220  with routing and circuitry extensions  222  of  FIG. 5B . Internal connector or socket  240  is electrically coupled to the electrical interconnect  220 . The discrete devices  224 ,  226  are then coupled to the socket  240 . 
         [0059]      FIGS. 6A and 6B  illustrate an electrical interconnect  300  with electroplated terminals  302  to create a flex-to-PCB connection in accordance with an embodiment of the present disclosure. The dielectric layer  72  of  FIG. 1F  is omitted or reduced in thickness so upper extensions  304  of the electroplated terminals  302  extend above the interconnect  300 . The upper extensions  304  are received in recesses  306  in flexible circuit  308  and electrically coupled with conductive traces  310 ,  312 . The lower ends  314  of the electroplated terminals  302  are soldered to PCB  316 . In an alternate embodiment, the electrical interconnect  300  can be used as a mating match to a board to board or mezzanine connector, a backplane, or a processor connector. 
         [0060]      FIG. 7  illustrates an alternate electrical interconnect  320  with electroplated terminals  322  to create a flex-to-PCB connection in accordance with an embodiment of the present disclosure. Proximal ends  324  of the terminals  322  are received in recesses  326  and electrically couple with circuit trace  330 . Upper extensions  325  of the electroplated terminals  322  are received in recesses  327  in flexible circuit  328  and electrically coupled with conductive trace  332 . The lower ends  334  of the electroplated terminals  322  are configured to snap-fit with circuit member  336 , such as illustrated in  FIGS. 2B, and 3 , permitting the assembly  338  to be removed from the circuit member  336 . In one embodiment, the flexible circuit  328  is constructed from a liquid crystal polymer material that when heated and/or pressure is applied will flow around the proximal ends  324  and upper extensions  325  of the electroplated terminals  322 . 
         [0061]      FIG. 8  illustrates an electrical interconnect  350  with electroplated terminals  352 A,  352 B,  352 C (“ 352 ”) with integral shielding in accordance with an embodiment of the present disclosure. The electrical interconnect  350  includes ground planes  354 A,  354 B (“ 354 ”) electrically coupled to plated sidewalls  356 A,  356 B,  356 C (“ 356 ”) of the terminal openings  358 A,  358 B,  358 C (“ 358 ”) that receive the solder terminals  360 A,  360 B,  360 C (“ 360 ”) on the circuit device  362 . In the illustrated embodiment, the circuit device  362  is a BOA device. 
         [0062]    In the illustrated embodiment, electroplated terminals  352 A and  352 C are electrically coupled to the ground planes  354 . Insulation  364  isolates the electroplated terminal  352 B from the ground planes  354  and the plated sidewalls  356 B, creating a coaxial structure. Alternate embodiments for creating style coaxial structures are disclosed in commonly assigned U.S. patent application Ser. No. 14/408,338 entitled SEMICONDUCTOR SOCKET WITH DIRECT SELECTIVE METALIZATION, FILED Mar. 14, 2013, which is hereby incorporated by reference. 
         [0063]    All of the plated sidewalls  356  are coupled to the ground planes  354 . The plated sidewalls  356 A,  356 C are electrically coupled to the solder terminals  360 A,  360 C, so that those solder terminals  360 A,  360 C are tied to ground. The plated sidewalls  356 B, however, are not coupled to the solder terminals  360 B. Rather, the solder terminal  360 B is isolated from the plated sidewalls  356 B by insulation  366 . The insulation  366  can be a dielectric material or simply air. The embodiment of  FIG. 8  can be used for a variety of applications, including IC device-to-PCB, PCB-to-PCB, flex-to-PCB, or cable-to-PCB interface. Alternate embodiments of the present connector/interconnect with electroplated terminals are disclosed in U.S. patent Ser. No. 14/408,039, entitled HIGH SPEED CIRCUIT ASSEMBLY WITH INTEGRAL TERMINAL AND MATING BIAS LOADING ELECTRICAL CONNECTOR ASSEMBLY, which is hereby incorporated by reference. 
         [0064]      FIG. 9  illustrates an embodiment for forming a snap-fit coupling with the electroplated terminals  378  in accordance with an embodiment of the present disclosure. Spring contact members  380  include a pair of opposing beams  382 A,  382 B that flex outward  384  as terminals  378  are brought into engagement in direction  386 . Distal portions  388  of the terminals  378  preferably have a circular cross sectional shape that facilitates engagement. 
         [0065]    The circuit member  376  is moved in the direction  386  until it engages with connector housing  390 . In one embodiment, space  392  between the connector housing  390  and the terminals  378  is slightly greater than radius of the distal portion  388  of the terminals  378  so the beams  382  are continually biases against the terminals  378 . In another embodiment, once the terminals  378  are in the space  392 , the beams  382  close to form a compressive engagement with the terminals  378 . 
         [0066]      FIGS. 10A and 10B  illustrate alternate engagement mechanisms between contact members  400 A,  400 B (“ 400 ”) and terminals  402  on first circuit member  404  in accordance with an embodiment of the present disclosure. Distal portions  406 A,  406 B (“ 406 ”) of the contacts members  400  are configured to engage with the terminals  402 . In the illustrated embodiment, openings  408 A,  408 B (“ 408 ”) have shapes complementary to neck portions  410  of the terminals  402 . In one embodiment, distal portion  406 B of contact member  400 B is formed from two discrete beams  414 A,  414 B that can flex outward during engagement with the terminals  402 . 
         [0067]    Bends  412  near the distal portions  406  permit the terminals  402  to slide into engagement along axis  416  that is generally perpendicular to primary axis  418  of the contact members  400 . Lateral or biasing loads can optionally be provided for low insertion force applications. An external mechanism can be used to maintain contact load  416  or engagement between the terminals  402  and the contact members  400  such that the terminals  402  are held by the contacts  400 . Other suitable engagement mechanisms are disclosed in U.S. Pat. No. 9,196,980 (Rathbum) and U.S. Pat. No. 9,093,767 (Rathburn), which are hereby incorporated by reference. 
         [0068]    In another embodiment, the terminals  402  are forced into engagement with the contact members  400  with a lateral or biasing load in a zero insertion force mechanism with an external feature maintaining contact load  416  against the contact members  400  in a normally open environment, or the mechanism releases pre-loaded contact members  400  such that they engage with the terminals  402  in a normally closed environment. The terminals  402  can be installed and engaged in an environment containing each of the loading mechanisms described (normal force snap retention, LIF, ZIF etc.). 
         [0069]      FIG. 11  illustrates an embodiment in which terminals  420  are soldered to PCB  422  in accordance with an embodiment of the present disclosure. Solder  424  wicks around the terminals  420  during reflow and engages with undercuts  426  to create an extremely strong joint. The present integral terminals  420  with undercuts  426  creates a joint much stronger than the conventional BGA solder ball 
         [0070]    BGA solder ball joints often require under fill to survive thermal or mechanical shock, not required in the illustrated embodiment because the integral terminals  420  provide a natural controlled height standoff  428 . The neck region  426  of the terminals  420  provides a natural level of compliance as the ductile copper can provide some level of decoupling between the terminal  420 , the circuit member  430  (such as an IC package) and the system board  422  to reduce the failure effects of thermal expansion coefficient disparities as well as mechanical stress of shock. 
         [0071]      FIG. 12  illustrates a solder deposit  450  on the terminals  452  in accordance with an embodiment of the present disclosure. In the illustrated embodiment, the terminals  452  are tin plated and are capped with solder  450  in a manner similar to methods used for copper pillar die attach which has become popular for high pin count area array devices as an alternative to flip chip or C4 attachment. The advantage of the present approach is that flip chip and C4 attachments are limited in pitch due to the potential for solder bridging of conventional solder balls as the spacing between them during reflow is reduced. 
         [0072]    Where a range of values is provided, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limit of that range and any other stated or intervening value in that stated range is encompassed within the embodiments of the disclosure. The upper and lower limits of these smaller ranges which may independently be included in the smaller ranges is also encompassed within the embodiments of the disclosure, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either both of those included limits are also included in the embodiments of the present disclosure. 
         [0073]    Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments of the present disclosure belong. Although any methods and materials similar or equivalent to those described herein can also be used in the practice or testing of the embodiments of the present disclosure, the preferred methods and materials are now described. All patents and publications mentioned herein, including those cited in the Background of the application, are hereby incorporated by reference to disclose and described the methods and/or materials in connection with which the publications are cited. 
         [0074]    The publications discussed herein are provided solely for their disclosure prior to the filing date of the present application. Nothing herein is to be construed as an admission that the present disclosure is not entitled to antedate such publication by virtue of prior invention. Further, the dates of publication provided may be different from the actual publication dates which may need to be independently confirmed. 
         [0075]    Other embodiments of the disclosure are possible. Although the description above contains much specificity, these should not be construed as limiting the scope of the disclosure, but as merely providing illustrations of some of the presently preferred embodiments of this disclosure. It is also contemplated that various combinations or sub-combinations of the specific features and aspects of the embodiments may be made and still fall within the scope of the present disclosure. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for one another in order to form varying modes of the disclosed embodiments of the disclosure. Thus, it is intended that the scope of the present disclosure herein disclosed should not be limited by the particular disclosed embodiments described above. 
         [0076]    Thus the scope of this disclosure should be determined by the appended claims and their legal equivalents. Therefore, it will be appreciated that the scope of the present disclosure fully encompasses other embodiments which may become obvious to those skilled in the art, and that the scope of the present disclosure is accordingly to be limited by nothing other than the appended claims, in which reference to an element in the singular is not intended to mean “one and only one” unless explicitly so stated, but rather “one or more.” All structural, chemical, and functional equivalents to the elements of the above-described preferred embodiment(s) that are known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the present claims. Moreover, it is not necessary for a device or method to address each and every problem sought to be solved by the present disclosure, for it to be encompassed by the present claims. Furthermore, no element, component, or method step in the present disclosure is intended to be dedicated to the public regardless of whether the element, component, or method step is explicitly recited in the claims.