Abstract:
A self-timed multiplier unit includes a multiplier and a clock generator. The multiplier has a first set of semiconductor circuits in a critical path. The clock generator has a second set of semiconductor circuits configured to control a clock period of said clock generator selected to set a clock period longer than the propagation delay through the critical path of the multiplier. The clock generator may include a delay circuit having a delay to set the clock period longer than the propagation delay through the critical path of said multiplier. The clock generator uses circuit with identical logical design including the same standard cells, the same logic design or the same floor plan. Close matching of these circuit causes the multiplier and the clock generator to experience the same PVT speed variations.

Description:
CLAIM OF PRIORITY 
       [0001]    This application claims priority under 35 U.S.C. 119(a) to German Patent Application No. 10 2011 108 576.2 filed Jul. 27, 2011. 
       TECHNICAL FIELD OF THE INVENTION 
       [0002]    The technical field of this invention is a self-timed multiplier unit. 
       BACKGROUND OF THE INVENTION 
       [0003]    A multiplier or multiplier may be realized using a parallel design to achieve good performance such as completing a multiplication operation in one or two cycles. Parallel multipliers need a large number of gates which increases production cost. A multiplier may be built using a serial design to reduce the gate count and cost. Serial multipliers are disclosed in German Patent Application Nos. 10 2007 014 808 and 10 2007 056 104. Multiplication is a basic and central data processing step in all kinds of data processing units and applications. There is a general motivation to improve multiplier units for faster operation and reduced complexity. Generally a tradeoff needs to be found between performance and cost. 
         [0004]    A multiplier is typically a part of a microcontroller, microprocessor or other digital unit. The multiplier is typically clocked with the system or main processor clock. For both serial and parallel multipliers the critical signal path delay of the combinatorial logic within the multiplier must be shorter than the clock period of the system clock under the worst PVT conditions. In the commonly used term PVT refers to variances in operational rate based upon fluctuation in the production process, known as production spread (P), varying voltage (V) and varying temperature (T). The electronic characteristics and parameters of the devices will vary slightly from one device to another based upon these factors. The worst PVT conditions are a weak production process, a low operating voltage and a high operating temperature. 
         [0005]    An electronic device is mostly not operated under these worst case PVT conditions. Thus the performance of the device is generally much higher than under these worst case PVT conditions. A multiplier may thus be implemented having its own clock independent of the system clock. The multiplier may run faster than the system clock and therefore even serial multiplication can be executed in one or two system clock cycles. Since the multiplier performance does not depend on the system clock frequency, the system can be clocked slower than a typical synchronous architecture while maintaining high multiplication performance. This may enable a significant reduction of the system level energy consumption in the multiplier. 
         [0006]    The multiplier local clock may be adapted to the critical path delay of the multiplier. In a synchronous digital design with a fixed clock rate, the clock must always as fast as the critical path of the multiplier under worst case PVT conditions. The electronic circuit is generally not operated under these worst case conditions. An adaptive clock may enable the multiplier to be operated faster. This will increase the average performance of the multiplier. However, the multiplier must be as fast as the system requires the respective results from the multiplier. In other words, the local clock of the multiplier must be fast enough (under all PVT conditions) to provide appropriate service to the rest of the system. For example, the multiplier may need one system clock cycle for one multiplication under typical PVT conditions while it may require two system clock cycles under worst case PVT conditions. Thus the system clock speed or the clock frequency of the multiplier has to be adjusted to the current PVT conditions. This required a generally cost and time consuming calibration process which may be required of every device. This calibration compensates for the production spread (P). The voltage (V) and temperature (T) have to be measured during operation of the device in order to properly adjust the clock frequency. 
       SUMMARY OF THE INVENTION 
       [0007]    This invention is a multiplier with improved performance under different environmental conditions. 
         [0008]    In one aspect of the invention the multiplier is a self-timed multiplier. The multiplier has a carry save adder for multiplying a first and a second operand and at least one register storing at least parts of the product of the multiplication. The carry save adder has a plurality of rows, each comprising a plurality of AND gates calculating a single bit product. The carry save adder has a plurality of adder cells adding results of the preceding row to a following row. The carry save adder has a critical path for calculating the product. The critical path is the signal path through the multiply or carry save adder having the maximum signal propagation delay. The multiplier further has an oscillator clocking the at least one register. The oscillator has a clock period that is longer than the propagation delay of the critical path of the multiplier. At least some of the logical gates of the oscillator, the carry save adder and the at least one register are uniform. This uniformity may mean that the respective logical gates are manufactured using the same standard cell. This uniformity may mean that the logical gates have the same semiconductor layout. 
         [0009]    The multiplier includes two adder stages including a carry save adder and a carry propagate adder. The carry propagate adder is coupled to the carry save adder and consists of a row of full adder cells adding the carry vector and the sum vector provided at the output row of the carry save adder. 
         [0010]    In another advantageous embodiment, only a single carry save adder stage is used for all summing operations. After performing all additions relating to the partial products of a multiplication, the carry save adder performs the final addition by adding the carry vector and the sum vector at the output row of the carry save adder. This aspect of the invention recognizes that it can be useful to use hardware having the same critical path. This configuration allows the same clock period to be used for all summing operations. This permits the multiply to be continuously clocked with a clock having a constant clock period a little bit longer than the critical path delay of the carry save adder. 
         [0011]    According to another aspect of the invention, the oscillator has at least one adder cell. The multiplier is configured to multiply a first operand and a second operand. The multiplier has plural adder cells configured as the carry save adder. The adder cells are arranged in rows and columns. Each row of adder cells is configured to add the product of a plurality of digits (single bits) of the first operand and a single bit of the second operand to the product of the digits of the first operand and another single bit of the second operand. The critical path of the multiply then passes through all rows of the multiplier such as through one adder cell of each row. The multiplier has a first number of rows. The oscillator advantageously has a second number of adder cells. The first number may be equal to twice the second number. The oscillator thus advantageously has half the number of adder cells as the number of rows in the multiplier. The oscillator has at least one storing element such as a flip-flop a latch. The oscillator is configured in a loop comprising the adder cell(s) and the at least one storing element. The oscillator produces the same edge of an output clock signal only after the signal has propagated twice through the adder cells of the loop. 
         [0012]    Advantageously this multiplier has a small gate count and provides high performance. This multiplier has a high frequency clock having a clock period that is independent of the system clock. The self-timed clock period is adapted to the critical path of the multiplier unit. This self-timed multiplier provides low leakage power consumption and high average performance. The performance of the multiplier is significantly higher than worst case PVT conditions would allow for a synchronous design. Not only does this self-timed multiplier provide a better performance when compared to typical synchronous designs but its reduces system energy consumption. 
         [0013]    The multiplier according to aspects of the invention is designed with the clock period of the oscillator slightly larger than the propagation delay of the critical path of the carry save adder. The clock period may be optimized so that it slightly exceeds the propagation delay of the critical path of the carry save adder. 
         [0014]    This propagation delay of the critical path of the carry save adder will change with changing PVT conditions. Voltage (V) and temperature (T) conditions will change due to changing operating conditions for the respective electronic device comprising the multiplier unit. The voltage and temperature may vary due to a weak power supply or different places of operation. 
         [0015]    Advantageously, no adaption of the self-timed oscillator is necessary. At least a part of the logical gates of the oscillator, the carry save adder and the at least one register are uniform with each other. Due to this uniformity, the operating characteristics of oscillator and the carry save adder and the register change in a similar way under varying PVT conditions. Preferably, the microstructure of the logical gates is similar due to the use of the same standard cell for the logical gates. Thus the environmental influences of voltage (V) and temperature (T) and variations in the production process (P) influence the operating parameters such as signal and delay times of the carry save adder, the register and the oscillator in a comparable way. 
         [0016]    In another aspect of the invention, the oscillator has the same uniform adder cell as the carry save adder. Advantageously, the adder is a full adder. According to another advantageous aspect, the oscillator includes the same uniform flip-flop as the register. While slight deviations in the layout of the logical gates might be harmless with respect to their PVT time behavior, a full adder can significantly influence the time dependent behavior of the carry save adder. This also applies to the register with respect to its flip-flops. It is advantageous if these basic logical gates of the carry save adder and the register are comparable with respect to their PVT characteristics as the basic logical gates of the oscillator. 
         [0017]    In order to increase the uniformity of the PVT time dependent behavior, it is advantageous to manufacture the uniform logical gates of the oscillator, the carry save adder and/or the at least one register using the same standard cell. Preferably, this standard cell is from a standard library. Advantageously, the uniform logical gates have not only the same standard cell but also the same semiconductor layout. Accordingly, the micro structure of the respective gates is nearly identical. This leads to a PVT behavior of the oscillator, the carry save adder and the register that is nearly identical. 
         [0018]    In an aspect of the invention, the logical gates of the oscillator and the logical gates of the carry save adder are arranged in a floor plan of the self-timed multiplier. Thus the signal delay time within the critical path part of the carry save adder is shorter than the signal delay time between the logical gates of the oscillator. Advantageously, this signal delay time ensures that the clock period of the oscillator is longer than a signal delay time along the critical path of the carry save adder. 
         [0019]    According to an embodiment of the invention, the logical gates of the oscillator are disposed at opposite sides with respect to the logical gates of the carry save adder. In this configuration, the conductive paths inside the oscillator are longer than the conductive paths inside the carry save adder. Consequently, the signal delay times inside the oscillator are higher when compared to the signal delay times inside the carry save adder. This ensures that the clock period of the oscillator is longer than the signal delay time along the critical path of the carry save adder. 
         [0020]    According to another aspect of the invention, the oscillator has at least an XOR, a first flip-flop and a second flip-flop. In the floor plan of the self-timed multiplier, the first flip-flop and the second flip-flop are disposed at opposite sides with respect to the logical gates of the carry save adder. The XOR-gate has a center region that is intermediate to the position of the first flip-flop and the second flip-flop. 
         [0021]    During a first cycle of the oscillator, while the output signal of the oscillator is high, the clock signal is routed from the first flip-flop to the XOR-gate. During a second cycle of the oscillator, while the output signal is low, the clock signal is routed from the second flip-flop to the XOR-gate. Because the XOR-gate is disposed in a center region that is intermediate to the position of the first flip-flop and the second flip-flop, the signal path delay for the clock signal that is routed from the first flip-flop to the XOR-gate is comparable to the signal path delay for the clock signal that is routed from the second flip-flop to the XOR-gate. Accordingly, the duty cycle of the clock signal is advantageously uniform. 
         [0022]    According to an embodiment of the invention, the oscillator is dedicated to a carry save adder having two rows. The oscillator has a first and a second flip-flop, a full adder and an XOR-gate. The inverted output of each flip-flop is coupled to its respective data input, while the sum and carry outputs of the full adder are coupled to the clock input of the respective first and second flip-flop. The output of the first and second flip-flop is coupled to a respective input of the XOR-gate. The output of the XOR-gate is coupled to the carry input of the full adder. The output of the XOR-gate also serves as an output of the oscillator. Advantageously, the layout of the dedicated oscillator has a behavior with respect to variations of temperature, power supply and/or process parameters that is comparable to the behavior of the critical path of a carry save adder having two rows. This is because the signal path in the oscillator for producing one clock cycle (one clock period) and the critical path of the carry save adder comprise the same type and same number of logical gates. 
         [0023]    According to further embodiments of the invention, the oscillator may be extended to a carry save adder having more than two rows. An oscillator for a carry save adder having 16 rows has 8 flip-flops coupled in the same way for the carry save adder having two rows. 
         [0024]    According to another embodiment of the invention, the multiplier for the carry save adder has two rows. This multiplier has an oscillator further comprising an additional second full adder and a first and a second AND gate. The second full adder is coupled in parallel to the first full adder with respect to its carry input terminal. The sum output of the first and second full adder is coupled to respective terminals of the first AND-gate while the carry output of the first and second full adder is coupled to respective terminals of the second AND gate. The output of the first AND-gate is coupled to the clock input of the first flip-flop and the output of the second AND-gate is coupled to the clock input of the second flip-flop. The criterion that the clock period has to be slightly longer than the critical path of the carry save adder is advantageously achieved using the two full adders. Variations in the production process (P) will lead to different delay times within the full adder. When using two full adders in this way, the slower one will be the pacemaker. 
         [0025]    According to another aspect, a dedicated oscillator for a multiplier has a carry save adder comprising two rows. The oscillator has a first and a second flip-flop, a full adder, a XOR-gate and an inverter, wherein the inverted output of each flip-flop is coupled to its respective data input. According to a first embodiment, the sum output of the full adder is coupled to the clock input of the first and second flip-flop. The sum output of the full adder that is coupled to the second flip-flop is coupled to an inverter and to the clock input of the second flip-flop. According to an alternative embodiment, the carry output of the full adder is coupled to the clock input of the first and second flip-flop. The carry output that is coupled to the first flip-flop is coupled to an inverter and to the clock input of the first flip-flop. In both embodiments the output of the first and second flip-flop is coupled to a respective input of the XOR-gate. The output of the XOR-gate is coupled to the carry input of the full adder. The output of the XOR-gate provides the clock output of the oscillator. Instead of using both the sum and carry outputs of the full adder, only one of them may be used. This is advantageous, if the respective delay times between the carry input and the sum output and the carry output are significantly different. The additional inverter has a delay time and thereby adds a further delay to the clock period. 
         [0026]    In another embodiment of the invention, a dedicated oscillator for a multiplier has a carry save adder having four rows. The dedicated oscillator includes in addition to the oscillator of the two aforementioned embodiments a second full adder. This second full adder is coupled with its carry input to the output of the XOR-gate. The carry output of the second full adder to the carry input of the first full adder. The second full adder provides a suitable extra delay time that is necessary due to the additional two rows of the carry save adder. This is because the signal in the oscillator generating one clock period and the signal propagating through the critical path of the carry save adder have to pass through the same type and same number of logical gates. 
         [0027]    According to another aspect of the invention a delay element is coupled between the output of the XOR-gate and the carry input of the full adder. This ensures that the clock period is slightly longer than the signal delay of the critical path of the carry save adder. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0028]    These and other aspects of this invention are illustrated in the drawings, in which: 
           [0029]      FIG. 1  is a simplified circuit diagram of a multiplier having a carry save adder having two rows; 
           [0030]      FIG. 2  is a simplified circuit diagram of an oscillator according to an embodiment of the invention; 
           [0031]      FIG. 3  is a diagram of signals inside the oscillator of the embodiment of  FIG. 2 ; 
           [0032]      FIGS. 4 and 5  are simplified circuit diagrams of an oscillator of further embodiments of the invention; 
           [0033]      FIG. 6  is a simplified circuit diagram of an oscillator of another embodiment of the invention; 
           [0034]      FIG. 7  is a simplified circuit diagram of a multiplier having a carry save adder having four rows; 
           [0035]      FIG. 8  is a simplified circuit diagram of an oscillator of another embodiment where the oscillator is dedicated to the multiplier as illustrated in  FIG. 7 ; 
           [0036]      FIG. 9  is a simplified floor plan for a carry save adder and oscillator of an embodiment of the invention; 
           [0037]      FIGS. 10 and 11  are schematic diagrams of power estimations for a multiplier of an embodiment of the invention; 
           [0038]      FIG. 12  is a simplified diagram of a multiplier with a carry save adder and a carry propagate adder; 
           [0039]      FIG. 13  is a simplified diagram of a multiplier with two carry save adder stages; and 
           [0040]      FIG. 14  is the multiplier of  FIG. 1  modified according to another embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0041]      FIG. 1  is a simplified circuit diagram of a multiplier  2  having a carry save adder CSA, a temporary sum register  4 , a temporary result register  6 , a temporary carry register  8  and an accumulating result shift register  10 . Each register  4 ,  6 ,  8 ,  10  has a plurality of flip-flops FF. The carry save adder CSA has a plurality of full adders FA in two rows for two bits X i  and X i+1  of a second operand. A further carry save adder comprising four rows is shown in  FIG. 7  will be described later. The two row carry save adder CSA in  FIG. 1  and the four row carry save adder CSA in  FIG. 7  are comparable in layout. 
         [0042]    Consider the example of a first operand of 4 bit depth with bits a 0  to a 3 . The bit values a 0  to a 3  are input to the respective AND-gates together with respective two bit values X i  and X i+1 . The output of the AND-gates supply the A input of the full adders FA. The lower bit parts of the full adder FA sums are stored in temporary result register  6 . The higher bit parts of the full adder FA sums are stored in temporary sum register  4 . The carry values from the full adders FA of the last row of carry save adder CSA are stored in temporary carry register  8 . To multiply operands having more than four bits, this operation of the carry save adder CSA is repeated iteratively. The accumulating result shift register  10  incorporates the lower bit results. This is indicated by the arrow pointing from the temporary result register  6  to the accumulating result shift register  10 . Further details for the carry save adder CSA and its operation are exemplarily known from German Patent Application No. 10 2007 014 808 filed on Mar. 28, 2007 and German Patent Application No. 10 2007 056 104 filed on Nov. 15, 2007 by the same applicant. 
         [0043]    According to an exemplary embodiment, the registers  4 ,  6 ,  8 ,  10  are clocked by clock signal CLK that is preferably generated by an oscillator according to an embodiment shown in one of  FIGS. 2 to 4 ,  6  or  8 . The respective oscillators are exemplarily dedicated to the two row type multiplier  2  shown in  FIG. 1 . 
         [0044]      FIG. 2  is an oscillator  12  comprising a full adder FA, a first flip-flop FF 1 , a second flip-flop FF 2 , an XOR-gate XOR and a delay element DEL. Oscillator  12  is enabled by setting input A of full adder FA to high. The second input B of full adder FA is constantly set to “0”.  FIG. 3  illustrates time dependent signals of selected terminals of the logic gates of the oscillator  12  illustrated in  FIG. 2 . 
         [0045]    When switching input A of full adder FA from low to high a delay time T FA-S  elapses before sum output S of full adder FA follows and also switches from low to high. Sum output S of full adder FA supplies input C 1  of flip-flop FF 1  which also changes from low to high. After expiration of a delay time T FFQ , which is the clock to Q delay time of flip-flop FF 1 , output Q 1  of flip-flop F 1  switches to high. The inverted output of flip-flop FF 1   Q   1  is coupled to data input D 1  of flip-flop FF 1 . Output Q 1  is coupled to one terminal of XOR-gate XOR. The other terminal of XOR-gate XOR is coupled to output Q 2  of second flip-flop FF 2 . After expiration of the delay time T XOR  of XOR-gate XOR, XOR-gate XOR switches clock signal CLK to high (see  FIG. 3 ). 
         [0046]    If the delay time the delay element DEL is zero, the clock signal CLK is equal to signal CIN. Signal CIN is coupled to carry in terminal CIN of full adder FA. Following a further delay time T FA-CO , the input to carry output delay of full adder FA, carry output COUT of full adder FA switches to high. Carry output COUT of full adder FA is coupled to clock input C 2  of second flip-flop F 2 . Clock input C 2  of second flip-flop FF 2  thus follows signal COUT. After expiration of the delay time T FFQ , the clock to Q delay time of the second flip-flop which is preferably equal to the clock to Q delay time of first flip-flop FF 1 , output Q 2  of second flip-flop FF 2  switches from low to high. Inverted output  Q   2  of second flip-flop FF 2  is coupled to the data input D 2  of second flip-flop FF 2 . Output Q 2  of second flip-flop FF 2  is coupled to the second terminal of XOR-gate XOR. Since the value at output Q 1  of first flip-flop FF 1  is still high, the output of XOR-gate XOR switches from high to low after expiration of delay time T XOR . Thus clock signal CLK switches from high to low and a first clock period CLKP has expired (see  FIG. 3 ). 
         [0047]    This signal routing is repeated for each clock cycle. At the beginning of a new clock cycle, clock signal CLK is coupled to carry input CIN of full adder FA via delay element DEL. Upon expiration of delay time T FA-S  sum output S of full adder FA switches from low to high. The signal routing proceeds as already explained. At the end, clock signal CLK again switches to high. 
         [0048]    A clock period CLKP is given by the following formula: 
         [0000]        CLKP= 2 T   FFQ   +T   FA-S   +T   FA-CO +2 T   XOR +2 T   DELAY    
         [0000]    where: T DELAY  is the delay time of delay element DEL. 
         [0049]    The propagation delay time of the critical path CPOM of a multiplier may be estimated by help of the formula: 
         [0000]    
       
      
       CPOM=T 
       FFQ 
       +T 
       FF-SETUP 
       +T 
       FA-S 
       +T 
       FA-CO  
      
     
         [0000]    where: T FFQ  is the delay time at a flip-flop for a signal that is routed from a clock input to the Q output; T FF-SETUP  is the setup time for a flip-flop; T FA-S  is the delay time in the full adder for a signal that is routed from the carry input CIN to the sum output S; and T FA-CO  is the delay time in a full adder for a signal that is coupled to carry input CIN and is routed to carry output COUT. 
         [0050]    For a typical flip-flop, 2T FFQ  is nearly equal to T FFQ  plus T FE-SETUP . This is because setup time T FF-SETUP  is nearly equal to the clock to Q delay T FFQ . The setup time is approximately the clock to Q delay T FFQ . Accordingly, the first summand 2T FFQ  of the formula for CLKP and the sum of the first two delay times T FFQ  and T FF-SETUP  in the formula for CPOM are nearly equal. Further, the second and third delay time in the formula for CLKP and the third and fourth delay time inside the formula for CPOM (T FA-S , T FA-CO ) are identical. Consequently, the clock period CLKP is greater than the critical path of the multiplier CPOM by the following delay time T SM  which is referred to as a safety margin. 
         [0000]        T   SM =2 T   XOR +2 T   DELAY    
         [0000]    Consequently, the oscillator  12  giving the clock signal CLK for the registers  4 ,  6 ,  8  and  10  of the multiplier  2  according to  FIG. 1  is slower than the signal delay time of the critical path of the multiplier  2 . The propagation delay of the critical path of the carry save adder CSA is lower or equal to the clock period of the oscillator  12  plus the delay time T SM  defining a safety margin. The logical gates of the oscillator  12  and the logical gates of the multiplier  2  are preferably manufactured with the same standard cell or have the same semiconductor layout. Thus the safety margin T SM  is preserved even if the PVT parameters change. 
         [0051]      FIGS. 4 and 5  are further embodiments of oscillator  12 . In  FIG. 4  sum output S of full adder FA supplies the clock inputs of flip-flops FF 1  and FF 2 . In  FIG. 5  carry output COUT of full adder FA supplies the clock inputs of flip-flops FF 1  and FF 2 . In both embodiments, one channel is inverted.  FIG. 4  illustrates inverter INV coupled to clock input C 2  of second flip-flop FF 2 .  FIG. 5  illustrates inverter INV coupled to clock input C 1  of first flip-flop FF 1 . The operation of the embodiments of  FIGS. 4 and 5  is very similar. 
         [0052]    In  FIG. 4 , inverter INV inverts the signal sum output S of full adder FA to clock input C 2  of second flip-flop FF 2 . The signal from sum output S of full adder FA to clock input C 1  of first flip-flop FF 1  is not inverted. Thus just one of flip-flops FF 1  and FF 2  receives a clock signal. Sum S and carry COUT output of full adder FA are opposite to each other and accordingly only one of the clock inputs of the flip-flops receives a clock signal. Thus if a first clock input is high the other clock input will be low. 
         [0053]    The embodiment is advantageous if the delay times between the carry input CIN an the sum output S designated T FA-S  and the delay time between the carry input CIN and the carry output COUT of the full adder FA designated T FA-CO  are significantly different. A suitable delay time should be selected. The additional inverter INV provides an extra delay time adding a further delay to the clock period. 
         [0054]    According to a further embodiment shown in  FIG. 6 , the oscillator  12  has a further full adder this including first full adder FA 1  and second full adder FA 2 . Oscillator  12  further includes a first AND gate AND 1  and a second AND gate AND 2 . As already shown in  FIG. 2 , data output Q 1  of first flip-flop FF 1  is coupled to the first terminal of the XOR-gate XOR and data output Q 2  of second flip-flop FF 2  is coupled to the second terminal of the XOR-gate XOR. Inverted output  Q   1  of first flip-flop FF 1  is coupled to data input D 1  of first flip-flop FF 1  and inverted output  Q   2  of second flip-flop FF 2  is coupled to data input D 2  of second flip-flop FF 2 . The output of the XOR-gate outputs clock signal CLK and is further coupled via the delay element DEL to carry inputs CIN of both first full adder FA 1  and second full adder FA 2 . 
         [0055]    Oscillator  12  is enabled by switching input A of first adder FA 1  and input A of second full adder FA 2  from low to high. Second input B of first full adder FA 1  and second full adder FA 2  remain at “0”, as illustrated in  FIG. 2 . Sum output S 1  of first full adder FA 1  is coupled to one terminal of first AND element AND 1 . Sum output S 2  of second full adder FA 2  is coupled to the other terminal of first AND element AND 1 . The output of first AND element AND 1  is coupled to clock input C 1  of first flip-flop FF 1 . 
         [0056]    Carry output COUT 1  of first full adder FA 1  is coupled to one terminal of second AND-gate AND 2 . Carry output COUT 2  of second full adder FA 2  is coupled to the other terminal of second AND-gate AND 2 . The output of second AND gate AND 2  is coupled to clock input C 2  of second flip-flop FF 2 . 
         [0057]    First and second AND-gates AND 1  and AND 2  are high if both inputs are high. The output of first AND gate AND 1  is high if both sum output S 1  of first full adder FA 1  and sum output S 2  of second full adder FA 2  are high. The same applies with respect to carry outputs COUT 1  and COUT 2  of first full adder FA 1  and second full adder FA 2 . 
         [0058]    First full adder FA 1  and second full adder FA 2  work synchronously. If the first full adder FA 1  and second full adder FA 2  are exactly identical and have the same internal delay times (T FA-S , T FA-CO ), the clock period is the clock period of the embodiment in  FIG. 2  with an added delay time due to the AND gates AND 1  and AND 2 . However, if the full-adders FA 1  and FA 2  having differing delay times, due to production spread or slight variations in the semiconductor production process, clock period CLK is dominated by the slower full-adder. This leads to a further safety margin with respect to the necessity that clock period CLK shall be slower than the critical path of the multiplier. 
         [0059]      FIG. 7  is a simplified circuit diagram of a multiplier  2  including a carry save adder CSA, a temporary sum register  4 , a temporary result register  6 , a temporary carry register  8  and an accumulating result shift register  10 . Each register  4 ,  6 ,  8 ,  10  has a plurality of flip-flops FF. Carry save adder CSA has a plurality of full adders FA in four rows for four bits X I , X I+1 , X I+2 , and X I+3  of a second operand. The first operand has a 4 bit depth with bits ranging from a 0  to a 3 . For operands having a higher bit depth, the operation is repeated iteratively. The operation of the registers  4 ,  6 ,  8 ,  10  is the same mentioned for the multiplier  2  illustrated in  FIG. 1 . 
         [0060]      FIG. 8  is further embodiment of an oscillator  12  corresponding to the embodiment of  FIG. 4  including two full adders FA 1  and FA 2 . Carry output COUT of first full adder FF 1  is coupled to carry input CIN of second full adder FA 2 . 
         [0061]    The clock period CLKP for the oscillator according to  FIG. 8  is given by the following formula: 
         [0000]        CLKP= 2 T   FFQ +4 T   FA-CO +2 T   XOR +2 T   DELAY    
         [0000]    This includes an extra time of 2T FA-CO  in comparison to the embodiment of  FIG. 2 . This extra time may be necessary since the critical path CPOM of a multiplier having four rows may be estimated by the formula: 
         [0000]        CPOM=T   FFQ   +T   FF-SETUP 4 T   FA-CO    
         [0000]    Assume the delay time for a signal from the carry input to the sum output T FA-S  of a full adder is comparable to the delay time of a signal from the carry input CIN to the sum output S T FA-CO  in a full adder. This includes an extra time of 2 T FA-CO  compared to the embodiment of  FIG. 2 . Thus the safety margin between the clock of the oscillator and the carry save adder remains constant at: 
         [0000]        T   SM =2 T   XOR +2 T   DELAY    
         [0000]    This principle permits the design of a suitable oscillator for a multiply unit having a carry save adder with an arbitrary number of rows. The number of rows of the multiply may be twice as high as the number of full adders. 
         [0062]      FIG. 9  is a simplified floor plan for a carry save adder and an oscillator. The oscillator has first and second flip-flops FF 1  and FF 2 , first and second full adders FA 1  and FA 2 , first and second AND gates AND 1  and AND 2  and XOR-gate XOR. As an example according to  FIG. 6  the oscillator may have no delay element DEL. Further flip-flops FF, full adders FA and AND gates AND are component parts of the carry save adder. 
         [0063]    This embodiment permits the signal routing delay times inside the oscillator and inside the carry save adder to be matched. To switch clock signal CLK (see also  FIG. 6 ) the signal from data output Q 1  of first flip flop FF 1  must be routed to one input of XOR-gate XOR. The same applies for signal routing between data output Q 2  of second flip flop FF 2  and the other input of XOR-gate XOR. 
         [0064]    By placing the two flip-flops FF 1  and FF 2  in the periphery of the carry save adder, the critical path of the oscillator including the signal routing delay times is longer than the delay time of the critical path in the carry save adder. The wiring length and therefore the signal delay due to signal propagation in the oscillator is always at least slightly greater than the maximum routing delay time of the multiply unit. 
         [0065]    XOR-gate XOR is disposed in a center area that is more or less in the middle between the two flip-flops FF 1  and FF 2 . This provides a uniform duty cycle of the oscillator. In the floor plan of  FIG. 9 , the length of the conductive path between data output Q 1  of first flip flop FF 1  and the input of XOR-gate XOR is more or less the same as the length of the conductive path between data output Q 2  of second flip flop FF 2  and the other input of XOR-gate XOR. The signal routing delay time will be comparable for the two conductive paths. 
         [0066]    During a first part of the clock cycle of the oscillator, if the output signal of the oscillator is “high”, the clock signal is routed from first flip-flop FF 1  to XOR-gate XOR. During a second part of the clock cycle of the oscillator, if the output signal is “low”, the clock signal is routed from the second flip-flop FF 2  to the XOR-gate XOR. Due to the arrangement of the XOR-gate in a center region of the carry save adder, the signal path delay for the clock signal that is routed from first flip-flop FF 1  to XOR-gate XOR is comparable to the signal path delay for the clock signal that is routed from second flip-flop FF 2  to XOR-gate XOR. Accordingly, the duty cycle of the clock signal is advantageously uniform. 
         [0067]      FIGS. 10 and 11  are exemplarily simulations of the energy consumption of a 32 bit multiplier according to the prior art and in comparison a 32 bit multiplier according to an embodiment of this invention. The potential for energy savings is visualized. The graphs show the power consumption in mW over time in μs. The respective areas illustrate the energy consumption. 
         [0068]    In the upper part of  FIG. 10  shows the energy consumption of a multiplier according to the prior art. In comparison, the lower part of  FIG. 10  illustrates the energy consumption of a multiplier according to an embodiment of this invention. As an example  FIG. 10  assumes a system frequency of 10 MHz.  FIG. 11  is a further example comparing the energy consumption of multiplier according to the prior art with a multiplier according to an embodiment of the invention.  FIG. 11  assumes a system frequency of 25 MHz. The upper part of  FIG. 11  shows the energy consumption of a multiplier according to the prior art, while the lower part of  FIG. 11  illustrates the energy consumption of a multiplier according to an embodiment of this invention. 
         [0069]    At a system speed of 10 MHz, the multiplier according to the prior art consumes 12 CPU cycles having a duration of 1.2 μs for the exemplary multiplication operation. The multiplier itself consumes 0.59 nWs during this operation. Further parts of the system consume 1.25 nWs. After the calculation, a quiescent energy consumption of 0.08 nWs is consumed until the end of 2 μs. This leads to a total energy consumption of 1.92 nWs. 
         [0070]    In contrast, a multiplier according to an embodiment of the invention consumes 1.06 nWs for the exemplary multiplication operation. This specific energy consumption is higher than for the multiplier according to the prior art. However, the multiplication operation is finished after 2 CPU cycles. The power consumption of the further parts of the system is accordingly only 2/12 of the aforementioned 1.25 nWs which is about 0.21 nWs. After the calculation, a quiescent energy consumption of 0.18 nWs is consumed until the end of 2 μs. This leads to a total energy consumption of 1.45 nWs. This is a total energy savings of about 24.5%. The multiplier according to an embodiment of this invention needs about 24.5% less energy for the same exemplary calculation operation in comparison to an multiplier according to the prior art. 
         [0071]      FIG. 11  illustrates the exemplary calculation at a system speed of 25 MHz.  FIG. 11  shows a total power savings of about 11.6%. A 32 bit multiplier according to the prior art consumes about 1.99 nWs during 2 μs. Since the overall system frequency is higher, the multiplier according to an embodiment of this invention requires 5 CPU cycles instead of 2 CPU cycles at a system frequency of 10 MHz. This leads to an energy consumption of 1.06 nWs for the multiplier and 0.52 nWs for the further part of the system. The energy consumption of the further parts of the system is significantly reduced because this embodiment of the invention requires 5 CPU cycles instead of 12 CPU cycles required by the multiplier of the prior art. The total energy consumption of the multiply operation according to this embodiment of the invention is 1.76 nWs during 2 μs. 
         [0072]      FIG. 12  shows a simplified diagram of a multiplier with two adder stages. This is a typical configuration of a multiplier  2 . The first stage is a carry save adder CSA 1  in accordance with the previously discussed embodiments of the invention. The second stage is a carry propagate stage CPA configured to sum the final temporary sum vector and the final temporary carry vector provided in registers  4  and  8  by carry save adder CSA 1 . Since carry propagate adder CPA has an entirely different architecture than carry save adder CSA 1 , the optimized clocking principles and oscillators shown  FIGS. 2 ,  4 ,  5 ,  6  and  8  according to the invention cannot be applied. The final summing performed in carry propagate adder CPA requires a different clock period. This disadvantage can be overcome if carry save adder CSA 1  is used for the last summing instead of carry propagate adder CPA. 
         [0073]      FIG. 13  illustrates how a carry save adder used for the normal operation can be reused for the final summing.  FIG. 12  shows two carry save adder stages CSA 1  and CSA 2 . Carry save adder stage CSA 2  is only illustrated to show the way in which carry save adder stage CSA 1  is be modified to perform the final summing step. The same hardware is used for carry save adder stage CSA 1  and CSA 2 . F carry save adder stage CSA 1  has the carry save adder configuration described with respect to the other embodiments of the invention. An optimized oscillator according to the aspects of the invention can be used. The second carry save adder stage CSA 2  sums the last temporary sum vector and the last temporary carry vector. The hardware for both configurations CSA 1  and CSA 2  is the same. It is a 16 by 16 bit carry save array. Since the same hardware is used for both operations, the critical paths are identical. The maximum propagation delays of the two carry save adder configurations CSA 1  and CSA 2  are therefore exactly equal. This means that the same optimized clock period can be used. 
         [0074]      FIG. 14  shows a simplified circuit diagram of modification of the multiplier shown in  FIG. 1 . The modifications reuse the same carry save array for all summing steps as illustrated in  FIG. 13 . There is an additional AND gate coupled to each full adder for the highest bit of each row. The other AND gates of each row have an additional input for a partial product enable signal en_pp. This signal is high during normal operation while the partial products are calculated. The oscillator and optimal clock period according to this invention is used for each cycle. There is an additional enable signal referred to as accumulator enable signal en_acc. This signal is always active when en_pp is active and additionally during the first cycle during which the final product (illustrated by CSA 2  in  FIG. 13 ) is formed. Signals en_acc and en_pp allow adding the two highest significant bits of the value held in accumulating result shift register  10 . The lower significant bits other than two highest significant bits of the accumulating result shift register  10  are loaded into the temporary sum register  4  before the carry save adder operation starts. This principle is applied to other embodiments using carry save adders with a different number of rows and columns. 
         [0075]    The carry save array shown in  FIG. 14  can be used for all summing operations required for determining the product of two operands and it allows to add a third operand from the accumulation register. Since the same hardware is used for all operations, the critical path is the same and the same optimized clock signal generated by the oscillators according to the invention can be used. 
         [0076]    In order to ensure the critical path as defined herein above, there are flip-flops FF added between the outputs of the AND gates and the inputs of the full adder cells FA. The flip-flops allow the partial products in the AND gates to be determined one cycle before the summing in the full adders FA is performed. This ensures that the critical path becomes independent of the partial product generation and corresponds always to a path comprising a flip-flop FF, a full adder FA another full adder FA and another flip-flip FF. This also applies to the AND gates used for gating the accumulator signals with enable signal en_acc and with partial product enable signal en_pp. 
         [0077]    The same modifications as shown in  FIG. 14  with respect to  FIG. 1  can be made for the embodiment shown in  FIG. 7 . 
         [0078]    Although the invention has been described hereinabove with reference to specific embodiments, it is not limited to these embodiments and no doubt further alternatives will occur to the skilled person that lie within the scope of the invention as claimed.