Abstract:
A circuit for controlling a lighting load may operate to minimize flicker in the lighting load and electromagnetic interference (EMI) noise generated on an AC voltage supply for the lighting load. The circuit comprises a bus-voltage-generating circuit for generating a bus voltage, a load regulation circuit having an inverter circuit, and a high speed control circuit characterized by a cutoff frequency much greater than a frequency of a voltage ripple on the bus voltage. The control circuit may comprise an error amplifier circuit configured to spread the frequency of operation of the inverter circuit at a set intensity level of the lighting load into a spread spectrum of frequencies to reduce the time average of peaks of the spectrum of frequencies and peak EMI levels. The circuit may also comprise a non-linear amplifier circuit amplifying a lamp-current-feedback signal representative of the magnitude of the load current through the lighting load.

Description:
CROSS REFERENCES TO RELATED APPLICATIONS 
     This application is a continuation of commonly—assigned U.S. Ser. No. 13/464,330, filed May 4, 2012 entitled DIMMABLE SCREW-IN COMPACT FLUORESCENT LAMP HAVING INTEGRAL ELECTRONIC BALLAST CIRCUIT which is a non-provisional application of U.S. Provisional Patent Application No. 61/484,481, filed May 10, 2011, entitled DIMMABLE SCREW-IN COMPACT FLUORESCENT LAMP HAVING INTEGRAL ELECTRONIC BALLAST CIRCUIT, the entire disclosure of which is hereby incorporated by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to electronic ballasts for gas discharge lamps, such as fluorescent lamps, and particularly, a dimmable screw-in compact fluorescent lamp having an integral electronic ballast circuit. 
     2. Description of the Related Art 
     In order to save energy, high-efficiency lighting loads, such as, for example, compact fluorescent lamps (CFLs) and light-emitting diode (LED) light sources, are being used in place of or as replacements for conventional incandescent or halogen lamps. High-efficiency light sources typically consume less power and provide longer operational lives as compared to incandescent and halogen lamps.  FIG. 1  is a simplified block diagram of a prior art lighting control system  10  having a screw-in compact fluorescent lamp  20 . The screw-in compact fluorescent lamp  20  comprises a fluorescent lamp tube  22 , which may be formed in a spiral (as shown in  FIG. 1 ). The screw-in compact fluorescent lamp  20  also comprises an enclosure  24  for housing a load regulation circuit  40  ( FIG. 2 ), e.g., an electronic ballast circuit, which is electrically coupled to the lamp tube  22  for illuminating the lamp tube. The screw-in compact fluorescent lamp  20  has a screw-in base  26  adapted to be coupled to a standard Edison socket. The lamp tube  22  of a typical prior art screw-in compact fluorescent lamp  20  is filled with a fill gas of 100% argon at a pressure of approximately 4 Torr. 
     The lighting control system  10  also comprises a “two-wire” dimmer switch  30 , which is coupled in series between an alternating-current (AC) power source  15  and the screw-in compact fluorescent lamp  20  for controlling the intensity of the lamp tube  22 . The dimmer switch  30  may be adapted to be mounted to a standard electrical wallbox and comprises a hot terminal H coupled to the AC power source  15  for receiving an AC mains line voltage V AC , and a dimmed-hot terminal DH coupled to the screw-in compact fluorescent lamp  20 . The dimmer switch  30  does not require a direct connection to the neutral side N of the AC power source  15 . Examples of prior art dimmer switches are described in greater detail is commonly-assigned U.S. Pat. No. 5,248,919, issued Sep. 29, 1993, entitled LIGHTING CONTROL DEVICE; U.S. Pat. No. 6,969,959, issued Nov. 29, 2005, entitled ELECTRONIC CONTROL SYSTEMS AND METHODS; and U.S. Pat. No. 7,687,940, issued Mar. 30, 2010, entitled DIMMER SWITCH FOR USE WITH LIGHTING CIRCUITS HAVING THREE-WAY SWITCHES, the entire disclosures of which are hereby incorporated by reference. 
     The dimmer switch  30  comprises a bidirectional semiconductor switch  32  coupled between the hot terminal H and the dimmed hot terminal DH for conducting a load current I LOAD  through the screw-in compact fluorescent lamp  20 . The bidirectional semiconductor switch  32  may comprise a single device, such as a triac, or a combination of devices, such as, two field-effect transistors (FETs) or insulated-gate bipolar junction transistors (IGBTs) coupled in anti-series connection. To control the amount of power delivered to the lamp tube  22 , the bidirectional semiconductor switch  32  is controlled to be conductive and non-conductive for portions of a half-cycle of the AC power source  15 , such that the bidirectional semiconductor switch is rendered conductive for a conduction time T ON  each half-cycle. The dimmer switch  30  may comprise a toggle actuator for turning the high-efficiency lamp tube  22  on and off and an intensity adjustment actuator for adjusting the intensity of the lamp tube  22  between a low-end intensity and a high-end intensity. 
     The dimmer switch  30  further comprises a control circuit  34  coupled in parallel with the bidirectional semiconductor switch  32  for conducting a control circuit I CNTL  through the screw-in compact fluorescent lamp  20 . The control circuit  34  is coupled to a control input of the bidirectional semiconductor switch  32  for rendering the bidirectional semiconductor switch conductive and non-conductive to generate a phase-control voltage V PC  using either the forward phase-control dimming technique or the reverse phase-control technique. Accordingly, the bidirectional semiconductor switch  32  is rendered conductive for the conduction time T CON  each half-cycle, thus setting a duty cycle DC PC  of the phase-control voltage V PC . The control circuit  34  may be operable to provide, for example, a constant gate drive to the bidirectional semiconductor switch  32 , such that the bidirectional semiconductor switch will remain conductive independent of the magnitude of the load current I LOAD  conducted through the bidirectional semiconductor switch and the screw-in compact fluorescent lamp  20 . An example of a two-wire dimmer switch having a constant gate drive control circuit is described in greater detail in commonly-assigned, co-pending U.S. patent application Ser. No. 12/952,920, filed Nov. 23, 2010, entitled TWO-WIRE DIMMER SWITCH FOR LOW-POWER LOADS, the entire disclosure of which is hereby incorporated by reference. 
     The screw-in base  26  of the compact fluorescent lamp  20  provides for only two electrical connections: a phase-control connection PC to the dimmer switch  30  for receiving the phase-control voltage V PC  and a neutral connection NC to the neutral side N of the AC power source  15 . The load regulation circuit  40  of the screw-in compact fluorescent lamp  20  is operable to adjust the intensity of the lamp tube  22  between the low-end intensity and the high-end intensity in response to the duty-cycle DC PC  of the phase-control signal V PC  (i.e., the conduction time of the bidirectional semiconductor switch  32  of the dimmer switch  30 ). 
     With forward phase-control dimming, the bidirectional semiconductor switch  32  is rendered conductive at some point within each AC line voltage half-cycle and remains conductive until approximately the next voltage zero-crossing, such that the bidirectional semiconductor switch is conductive for the conduction time each half-cycle. A zero-crossing is defined as the time at which the AC line voltage transitions from positive to negative polarity, or from negative to positive polarity, at the beginning of each half-cycle. Forward phase-control dimming is often used to control energy delivered to a resistive or inductive load, which may include, for example, an incandescent lamp or a magnetic low-voltage transformer. The bidirectional semiconductor switch of a forward phase-control dimmer switch is typically implemented as a thyristor, such as a triac or two silicon-controlled rectifiers (SCRs) coupled in anti-parallel connection, since a thyristor becomes non-conductive when the magnitude of the current conducted through the thyristor decreases to approximately zero amps. Thyristors are typically characterized by a rated latching current and a rated holding current, and comprise two main terminals and a control terminal. The current conducted through the main terminals of the thyristor must exceed the latching current for the thyristor to become fully conductive. In addition, the magnitude of the load current I LOAD  conducted through the main terminals of the thyristor must remain above the holding current for the thyristor to remain in full conduction. 
     The control circuits of many forward phase-control dimmers comprise analog control circuits (such as timing circuits) for controlling when the thyristor is rendered conductive each half-cycle of the AC power source. The analog control circuit typically comprises a potentiometer, which may be adjusted in response to a user input provided from, for example, a linear slider control or a rotary knob in order to control the amount of power delivered to the lighting load. The analog control circuit is typically coupled in parallel with the thyristor and conducts a small timing current through the lighting load when the thyristor is non-conductive. 
     With reverse phase-control dimming, the bidirectional semiconductor switch  32  is rendered conductive at the zero-crossing of the AC line voltage and rendered non-conductive at some point within each half-cycle of the AC line voltage, such that the bidirectional semiconductor switch is conductive for a conduction time each half-cycle. The bidirectional semiconductor switch of reverse phase-control dimmers typically comprises two field-effect transistors (FETs) in anti-serial connection, or the like. Accordingly, prior art reverse phase-control dimmer switches have required advanced control circuits (such as microprocessors) for controlling the operation of the FETs, and power supplies for powering the microprocessors. In order to properly charge, the power supply of such a two-wire dimmer switch must develop an amount of voltage across the power supply and must conduct a charging current from the AC power source through the electrical load, in many instances even when the lighting load is off. 
       FIG. 2  is a simplified block diagram of the load regulation circuit  40  of the prior art screw-in compact fluorescent lamp  20 . The load regulation circuit  40  comprises an electromagnetic interference (EMI) filter  50  for preventing noise generated by the load regulation circuit from being conducted on the AC mains wiring. A full-wave bridge rectifier  52  receives the phase-control voltage V PC  from the EMI filter  50  and generates a rectified voltage V RECT . The rectified voltage V RECT  is coupled to a bus capacitor C BUS  through a diode D 54  for generating a direct-current (DC) bus voltage V BUS  across the bus capacitor. The load regulation circuit  40  further comprises an inverter circuit  56  for generating a high-frequency square-wave voltage V SQ  from the rectified voltage V RECT , and a resonant tank circuit  58  for receiving the square-wave voltage V SQ  and producing a substantially sinusoidal high-frequency AC voltage V LAMP  (i.e., an arc voltage or lamp voltage), which is provided to the lamp tube  22 . The inverter circuit  56  adjusts the operating frequency f OP  of the square-wave voltage V SQ  in order to adjust the intensity of the lamp tube  22 . 
     The load regulation circuit  40  further comprises a phase-to-DC converter circuit  60  for receiving the rectified voltage V RECT  and generating a DC voltage V DC  that has a magnitude that is representative of the duty-cycle DC PC  of the phase-control signal V PC , and a lamp current sense circuit  62  that generates a lamp current control signal V ILAMP  representative of a magnitude of a lamp current I LAMP  conducted through the lamp tube  22 . A control circuit  64  is coupled to the inverter circuit  56  for adjusting an operating frequency f OP  of the square wave voltage V SQ  and thus the magnitude of the lamp current I LAMP  in response to the duty-cycle DC PC  of the phase-control signal V PC  and the magnitude of the lamp current I LAMP . The load regulation circuit  40  also comprises a power supply  66  that receives the bus voltage V BUS  and generates a DC voltage V CC  for powering the control circuit  64 . 
     Since the dimmer switch  30  is a two-wire dimmer switch, the compact fluorescent lamp  20  receives both power for energizing the lamp tube  22  and information for determining the target intensity of the lamp tube from the phase-control signal V PC . The phase-to-DC circuit  60  typically comprises a filter circuit for preventing voltage fluctuations in the AC mains line voltage V AC  of the AC power source  15  or noise on the AC mains line voltage V AC  from altering the magnitude of the DC voltage V DC  generated by the phase-to-DC converter circuit  60 . Therefore, there is typically a delay time period between a change in the duty-cycle DC PC  of the phase-control signal V PC  and a resulting change in the magnitude of the DC voltage V DC  generated by the phase-to-DC converter circuit  60 . If the intensity adjustment actuator of the dimmer switch  30  is controlled such that the target intensity is quickly reduced from the high-end intensity to the low-end intensity, the magnitude of the phase-control signal V PC  (and thus the amount of power available to the load regulation circuit  40 ) will quickly decrease while the control circuit  64  is still controlling the intensity of the lamp tube  22  to the high-end intensity (due to the delay time period). Accordingly, the bus capacitor C BUS  will quickly discharge, such that the control circuit  64  becomes unpowered and the lamp tube  22  is extinguished, which, of course, is undesirable. 
       FIGS. 3A and 3B  show example waveforms of the DC bus voltage V BUS  and the lamp current I LAMP , respectively. As shown in  FIG. 3A , the bus voltage V BUS  is characterized by some low-frequency voltage ripple having a frequency approximately equal to twice the frequency of the AC power source  15  (e.g., approximately 120 Hz). The control circuit  64  is typically characterized by a corner frequency of approximately 10-20 Hz, and thus controls the inverter circuit  56  to adjust the operating frequency f OP  of the square-wave voltage V SQ  at a relatively slow rate in response to the lamp current control signal V ILAMP . Since the corner frequency (i.e., approximately 10-20 Hz) is less than the frequency of the voltage ripple of the bus voltage V BUS  (i.e., approximately 120 Hz), the operating frequency f OP  of the square-wave voltage V SQ  (and thus the lamp current I LAMP ) is maintained relatively constant over short time intervals (e.g., during a single half-cycle T HC  of the AC power source  15 , i.e., approximately 8.33 msec). As a result, the lamp current I LAMP  has an envelope I ENV  that is characterized by the frequency of the voltage ripple of the bus voltage V BUS  (as shown in  FIG. 3B ). This fluctuation (or ripple) in the envelope I ENV  of the lamp current I LAMP  can cause undesirable flicker in the lamp tube  22 . 
     Accordingly, there is a need for a dimmable screw-in compact fluorescent lamp having an integral electronic ballast circuit that avoids the disadvantages of the prior art circuits. 
     SUMMARY OF THE INVENTION  
     According to an embodiment of the present invention, a circuit for controlling a lighting load may operate to minimize flicker in the lighting load and electromagnetic interference (EMI) noise generated on an AC voltage supply for the lighting load. The circuit comprises a bus-voltage-generating circuit configured to receive an input from the AC voltage supply and produce a DC bus voltage characterized by a low-frequency voltage ripple, and a load regulation circuit including an inverter circuit and an output filter circuit. The inverter circuit is configured to receive the DC bus voltage and generate a high-frequency inverter output signal, and the output filter circuit is configured to generate a load current conducted through the lighting load in response to the high-frequency inverter output signal. The inverter circuit is configured to receive a drive control signal and to control the high-frequency inverter output signal to adjust the magnitude of the load current conducted through the lighting load in response to the drive control signal. The circuit further comprises a control circuit configured to produce the drive control signal for the inverter circuit to control the high-frequency inverter output signal to adjust the magnitude of the load current conducted through the lighting load. The control circuit is configured to receive a first signal having a magnitude representative of a target intensity level of the lighting load and a second signal having a magnitude representative of an actual intensity level of the lighting load. The control circuit comprises an error amplifier circuit configured to compare the first and second signals to produce the drive control signal to cause the inverter circuit to control the high-frequency inverter output signal to illuminate the lighting load at the target intensity level. The error amplifier circuit is configured to operate in a frequency range and is responsive to the second signal at the frequency of the second signal thereby to cause the inverter circuit to control the high-frequency inverter output signal to reduce the effect of the low-frequency voltage ripple of the DC bus voltage on the magnitude of the load current. 
     The error amplifier circuit may be configured to spread the frequency of operation of the inverter circuit at a set intensity level of the lighting load into a spread spectrum of frequencies thereby to reduce the time average of peaks of the spectrum of frequecies and reduce peak EMI levels. 
     The circuit may further comprise a non-linear amplifier circuit configured to amplify the second signal by a first amount when the magnitude of the load current is below a current threshold, and by a second, smaller amount when the magnitude of the load current is above the current threshold, thereby increasing responsiveness of the control circuit to changes in lamp intensity levels at low lamp intensity levels. 
     The circuit may further comprise an artificial load circuit configured to be coupled to the AC voltage supply to ensure that adequate current is drawn from the AC voltage supply to enable a semiconductor switch of a dimmer circuit supplying the AC voltage supply to latch on and stay on. 
     Other features and advantages of the present invention will become apparent from the following description of the invention that refers to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention will now be described in greater detail in the following detailed description with reference to the drawings in which: 
         FIG. 1  is a simplified block diagram of a prior art lighting control system including a “two-wire” dimmer switch for controlling the amount of power delivered to a screw-in compact fluorescent lamp; 
         FIG. 2  is a simplified block diagram of the screw-in compact fluorescent lamp of the lighting control system of  FIG. 1 ; 
         FIG. 3A  shows an example waveform of a bus voltage of the screw-in compact fluorescent lamp of  FIG. 2 ; 
         FIG. 3B  shows an example waveform of a lamp current of the screw-in compact fluorescent lamp of  FIG. 2 ; 
         FIG. 4  is a side view of a dimmable screw-in compact fluorescent lamp according to an embodiment of the present invention; 
         FIG. 5  is a simplified schematic diagram of the screw-in compact fluorescent lamp of  FIG. 4 ; 
         FIG. 6  is a simplified schematic diagram of the electrical circuitry of the screw-in compact fluorescent lamp of  FIG. 4  showing a load regulation circuit and two power supplies in greater detail; 
         FIG. 7  is a simplified schematic diagram of an inverter circuit of the load regulation circuit and an over-voltage protection circuit of the screw-in compact fluorescent lamp of  FIG. 4 ; 
         FIG. 8  is a simplified schematic diagram of a control circuit of the screw-in compact fluorescent lamp of  FIG. 4 ; 
         FIG. 9  is an example plot of the magnitude of a lamp voltage with respect to the magnitude of a lamp current of the screw-in compact fluorescent lamp of  FIG. 4 ; 
         FIG. 10A  shows an example waveform of a bus voltage of the screw-in compact fluorescent lamp of  FIG. 4 ; and 
         FIG. 10B  shows an example waveform of a lamp current of the screw-in compact fluorescent lamp of  FIG. 4  according to the embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The foregoing summary, as well as the following detailed description of the preferred embodiments, is better understood when read in conjunction with the appended drawings. For the purposes of illustrating the invention, there is shown in the drawings an embodiment that is presently preferred, in which like numerals represent similar parts throughout the several views of the drawings, it being understood, however, that the invention is not limited to the specific methods and instrumentalities disclosed. 
       FIG. 4  is a side view of a dimmable screw-in compact fluorescent lamp  120  according to an embodiment of the present invention. The dimmable screw-in compact fluorescent lamp  120  comprises a light source, e.g., a fluorescent lamp tube  122 , which may be formed in a spiral (as shown in  FIG. 4 ), in two or more U-bends, or in any other suitable form. The lamp tube  122  may be filled with a fill-gas mixture having a fall-gas pressure of approximately 2 Torr and a fill-gas ratio of approximately 85:15 argon to neon. The dimmable screw-in compact fluorescent lamp  120  further comprises an enclosure  24  for housing a load regulation circuit  130  ( FIG. 5 ), e.g., an electronic ballast circuit, which is electrically coupled to the lamp tube  122  for illuminating the lamp tube. 
     The screw-in compact fluorescent lamp  120  has a screw-in base  126  adapted to be coupled to a standard Edison socket, such that the lamp is adapted to be coupled to a two-wire dimmer switch (such as the dimmer switch  30 ) via the phase-control connection PC of the screw-in base  126  and to the neutral side N of an AC power source via the neutral connection NC (as in the prior art lighting control system  100  shown in  FIG. 1 ). As defined herein, a “two-wire” dimmer switch or load control device does not require a direct connection to the neutral side N of the AC power source. In other words, all currents conducted by the two-wire dimmer switch must also be conducted through the load. A two-wire dimmer switch may have only two terminals (i.e., the hot terminal H and the dimmed hot terminal DH as shown in  FIG. 1 ). Alternatively, a two-wire dimmer switch could comprise a three-way dimmer switch that may be used in a three-way lighting system and has at least three load terminals, but does not require a neutral connection. In addition, a two-wire dimmer switch may comprise an additional connection that provides for communication with a remote control device (for remotely controlling the dimmer switch), but does not require the dimmer switch to be directly connected to neutral. 
       FIG. 5  is a simplified schematic diagram of a dimmable screw-in compact fluorescent lamp  120  according to the embodiment of the present invention. As previously mentioned, the screw-in base  126  provides for only two electrical connections: the phase-control connection PC to the dimmer switch for receiving the phase-control voltage V PC  and the neutral connection NC to the neutral side N of the AC power source. The load regulation circuit  130  of the screw-in compact fluorescent lamp  120  is operable to adjust the intensity of the lamp tube  122  to a target intensity L TRGT  (i.e., a desired intensity) in response to the duty-cycle DC PC  of the phase-control signal V PC . The target intensity L TRGT  may range between a low-end intensity L LE  (e.g., approximately 1%) and a high-end intensity L HE  (e.g., approximately 100%). 
     The screw-in compact fluorescent lamp  120  comprises a filter network  200  coupled to the phase-control connection PC and the neutral connection NC of the connector  126  for receiving the phase-control voltage V PC  from the dimmer switch  30 . The filter network  200  comprises an inductor L 201  (e.g., having an inductance of approximately 680 μH) and two capacitors C 202 , C 203  (e.g., having capacitances of approximately 33 nF). The filter network  200  operates to prevent noise generated by the load regulation circuit  130  from being conducted on the AC mains wiring. The filter network  200  couples the phase-control voltage V PC  to a voltage doubler circuit  205  (i.e., a bus-voltage-generating circuit), which generates a direct-current (DC) bus voltage V BUS  across two series connected bus capacitors C B1 , C B2 . The first bus capacitor C B1  conducts the load current I LOAD  through a diode D 206  (and the dimmer switch  30 ) to charge during the positive half-cycles, while the second bus capacitor C B2  conducts the load current I LOAD  through a diode D 208  to charge during the negative half-cycles. Accordingly, the peak magnitude of the bus voltage V BUS  is approximately twice the peak voltage of the AC mains line voltage V AC . A half-bus voltage V HB  is generated across the first bus capacitor C B1  and has a magnitude equal to approximately half of the bus voltage V BUS . 
     The load regulation circuit  130  (i.e., the electronic ballast circuit) includes a half-bridge inverter circuit  210  for converting the DC bus voltage V BUS  to a high-frequency square-wave voltage V SQ  having an operating frequency f OP . The load regulation circuit  130  further comprises an output filter circuit, e.g., a resonant tank circuit  220 , for filtering the square-wave voltage V SQ  to produce a substantially sinusoidal high-frequency AC voltage, which is coupled to the electrodes of the lamp tube  122 . A control circuit  230  is coupled to the inverter circuit  210  for providing a drive control signal V DR  to the inverter circuit  210  for adjusting the operating frequency f OP  of the square wave voltage V SQ  and thus the magnitude of a lamp current I LAMP  conducted through the lamp tube  122  in order to turn the lamp tube on and off and adjust the intensity of the lamp tube. 
     Alternatively, the screw-in compact fluorescent lamp  120  could comprise a different high-efficiency lighting load, such as, a dimmable screw-in LED light source having an LED light engine, and the load regulation circuit  130  could comprise an LED driver. An example of the LED driver  102  is described in greater detail in commonly-assigned, co-pending U.S. patent application Ser. No. 12/813,908, filed Jun. 11, 2009, entitled LOAD CONTROL DEVICE FOR A LIGHT□EMITTING DIODE LIGHT SOURCE, the entire disclosure of which is hereby incorporated by reference. 
     The screw-in compact fluorescent lamp  120  further comprises two power supplies: an inverter power supply  240  and a control power supply  250 . The inverter power supply  240  receives the half-bus voltage V HB  across the first bus capacitor C B1  and generates a direct-current (DC) inverter supply voltage V INV  (e.g., approximately 15 volts) for powering the control circuitry of the inverter circuit  210 . The control power supply  250  draws current from the resonant tank circuit  220  and generates a DC control supply voltage V CC  (e.g., approximately 12 volts) for powering the control circuit  230  while the inverter circuit  210  is generating the high-frequency square-wave voltage V SQ . When the screw-in compact fluorescent lamp  120  is first powered up, the inverter power supply  240  is operable to generate the inverter supply voltage V INV  before the control power supply  250  begins to produce the control supply voltage V CC . After the inverter power supply  240  is generating the inverter supply voltage V INV , the inverter circuit  210  is able to begin generating the high-frequency square-wave voltage V SQ , such that the control power supply  250  is able to draw current from the resonant tank circuit  220 . Accordingly, the control power supply  250  then produces the control supply voltage V CC  to power the control circuit  230 . 
     The screw-in compact fluorescent lamp  120  further comprises an over-voltage protection (OVP) circuit  260 , which provides an OVP control signal V OVP  to the inverter circuit  210  for protecting the lamp tube  122  and the load regulation circuit  130  during over-voltage conditions. A lamp current sense circuit  270  is coupled in series with the lamp tube  122  to conduct the lamp current I LAMP  and to generate a lamp current control signal V ILAMP  representative of a magnitude of the lamp current I LAMP . The screw-in compact fluorescent lamp  120  further comprises a rectifier circuit  280  (e.g., a full-wave rectifier diode bridge as shown in  FIG. 5 ), which has AC terminals coupled to receive the phase-control voltage V PC  from the filter network  200  and DC terminals for providing a rectified voltage V RECT . 
     The rectified voltage V RECT  is received by an artificial load circuit  290  for conducting an artificial load current I ART  through the dimmer switch  30  in addition to the load current I LOAD  conducted by the bus capacitors C B1 , C B2  when the bus capacitors are charging. If the dimmer switch  30  includes a triac for generating the phase-control voltage V PC , the artificial load circuit  290  is able to conduct enough current to ensure that the magnitude of the total current conducted through the triac of the dimmer switch exceeds the rated latching and holding currents of the triac. In addition, the artificial load circuit  290  may conduct a timing current if the dimmer switch  30  comprises a timing circuit and may conduct a charging current if the dimmer switch comprises a power supply, such that these currents need not be conducted through the load regulation circuit  130  and do not affect the intensity of the lamp tube  122 . 
     The artificial load circuit  290  comprises a current-passing switch, e.g., a FET Q 282 , coupled in series with a resistor R 284  (e.g., having a resistance of approximately 12.4Ω), where the series combination of the drain-source junction of the FET Q 282  and the resistor R 284  is coupled across the DC terminals of the rectifier circuit  280 . The gate of the FET Q 282  is coupled to the drain of the FET Q 282  through a resistor R 285  (e.g., having a resistance of approximately 1 MΩ), such that the FET Q 282  is rendered conductive and conducts the artificial load current I ART  when the magnitude of the rectified voltage V RECT  increases from approximately zero volts to exceed a turn-on threshold (e.g., approximately 4 volts). Accordingly, the FET Q 282  is rendered conductive, such that the artificial load circuit  290  conducts the artificial load current I ART  through the dimmer switch  30  after the triac is rendered conductive (if the dimmer switch is using the forward phase-control dimming technique), or shortly after the beginning of each half-cycle (if the dimmer switch is using the reverse phase-control dimming technique). The artificial load circuit  290  further comprises an NPN bipolar junction transistor Q 286  having a base-emitter junction coupled across the resistor R 284  and a collector coupled to the gate of the FET Q 282 . The transistor Q 286  controls the FET Q 282  in the linear region to provide over-current protection of the FET Q 282  when the voltage across the resistor R 284  exceeds the rated base-emitter voltage of the transistor Q 286  (e.g., approximately 0.7 volt). 
     The artificial load circuit  290  also comprises an NPN bipolar junction transistor Q 288  having a collector coupled to the gate of the FET Q 282 , and a zener diode Z 292 , having, for example, break-over voltage V BR  of approximately 13.2 volts. Three resistors R 294 , R 295 , R 296  are coupled in series between the DC terminals of the rectifier circuit  180  and have, for example, resistances of approximately 22 kΩ, 470 kΩ, and 150 kΩ, respectively. The zener diode Z 292  is coupled between the base of the transistor Q 288  and the junction of the resistors R 295 , R 296 . A capacitor C 298  is coupled across the resistor R 296  and has, for example, a capacitance of approximately 1000 pF. When the magnitude of the rectified voltage V RECT  exceeds a turn-off threshold (e.g., approximately 60 volts), the zener diode Z 292  conducts current into the base of the transistor Q 288 . Accordingly, the transistor Q 288  is rendered conductive and the FET Q 282  is rendered non-conductive, such that the artificial load circuit  290  stops conducting the artificial load current I ART . If the dimmer switch  30  is using the forward phase-control dimming technique, the capacitor C 298  provides some delay, such that the artificial load circuit  290  conducts the artificial load current I ART  for a period of time after the triac is rendered conductive. 
     The artificial load circuit  290  also provides a phase-control input control signal V PC-IN  to the control circuit  230 . Specifically, the artificial load circuit  290  comprises a PNP bipolar junction transistor Q 299  having a collector coupled to the control circuit  230  for providing the phase-control input control signal V PC-IN . The emitter-base junction of the transistor Q 299  is coupled across the resistor R 294 , such that the transistor Q 299  is rendered conductive shortly after the triac is rendered conductive (with forward phase-control dimming) or shortly after the beginning of each half-cycle (with reverse phase-control dimming). The control circuit  230  uses the phase-control input control signal V PC-IN  to determine the duty-cycle DC PC  of the phase-control voltage V PC  (i.e., the conduction time T CON  of the bidirectional semiconductor switch  32  of the dimmer switch  30 ). The control circuit  230  determines the present magnitude of the lamp current I LAMP  from the lamp current control signal V ILAMP  received from the lamp current sense circuit  270 . The control circuit  230  then adjusts the operating frequency f OP  of the square wave voltage V SQ  to control the magnitude of the lamp current I LAMP  to a desired level that is dependent upon the duty-cycle DC PC  of the phase-control voltage V PC  to thus control the intensity of the lamp tube  122  to the target intensity L TRGT . 
       FIG. 6  is a simplified schematic diagram of the electrical circuitry of the screw-in compact fluorescent lamp  120  showing the inverter circuit  210 , the resonant tank circuit  220 , the inverter power supply  240 , the control power supply  250 , and lamp current sense circuit  270  in greater detail. The inverter circuit  210  comprises first and second series-connected switching devices (e.g., FETs Q 212 , Q 214 ) and an inverter control circuit  216 , which may comprise, for example, an inverter control integrated circuit (IC) U 300  ( FIG. 5 ), such as part number FAN7532, manufactured by Fairchild Semiconductor Incorporated. The inverter control IC U 300  of the inverter control circuit  216  is powered by the inverter supply voltage V INV  and controls the FETs Q 212 , Q 214  in response to the drive control signal V DR  received from the control circuit  230  as will be described in greater detail below with reference to  FIG. 7 . The inverter control circuit  216  renders the FETs Q 212 , Q 214  conductive and non-conductive on a complementary basis (such that only one of the FETs is conducting at a time) using a constant duty cycle (e.g., approximately 50%). When the first FET Q 212  is conductive, the output of the inverter circuit  210  is pulled up towards the bus voltage V BUS . When the second FET Q 214  is conductive, the output of the inverter circuit  210  is pulled down towards circuit common. The magnitude of the lamp current I LAMP  conducted through the lamp tube  122  is controlled by adjusting the operating frequency f OP  of the high-frequency square wave voltage V SQ  generated by the inverter circuit  210 . 
     The resonant tank circuit  220  comprises a resonant inductor L 222  adapted to be coupled in series between the inverter circuit  210  and the lamp tube  122 , and a resonant capacitor C 224  adapted to be coupled in parallel with the lamp tube. For example, the inductor L 222  may have an inductance of approximately 1.4 mH, while the resonant capacitor C 224  may have a capacitance of approximately 1.2 nF, such that resonant tank circuit is characterized by a resonant frequency of approximately 110 kHz. The resonant tank circuit  220  further comprises a DC-blocking capacitor C 226  that has a capacitance of, for example, approximately 2.7 nF and operates to minimize the DC component of the lamp current I LAMP  conducted through the lamp tube  122 . 
     When the lamp tube  122  is not illuminated and the control circuit  230  receives a command to turn the lamp tube on (from the phase-control voltage V PC ), the control circuit first preheats filaments  228 A,  228 B of the lamp tube  122  and then attempts to strike the lamp tube. The load regulation circuit  130  may comprise, for example, two filament windings  229 A,  229 B that are magnetically coupled to the resonant inductor L 222  and electrically coupled to the respective filaments  228 A,  228 B for generating filament voltages for heating the filaments of the lamp tube  122  prior to striking the lamp. To preheat the filaments  228 A,  228 B, the inverter circuit  210  controls the operating frequency f OP  of the square wave voltage V SQ  to a preheat frequency f PH  (e.g., approximately 150 kHz) for a preheat time period T PH  (e.g., approximately 700 msec). An example of a ballast having a circuit for heating the filaments of a fluorescent lamp is described in greater detail in U.S. Pat. No. 7,586,268, issued Sep. 8, 2009, titled APPARATUS AND METHOD FOR CONTROLLING THE FILAMENT VOLTAGE IN AN ELECTRONIC DIMMING BALLAST, the entire disclosure of which is hereby incorporated by reference. 
     The inverter power supply  240  receives the half-bus voltage V HB  developed across the first bus capacitor C B1  and generates the inverter supply voltage V INV  across a storage capacitor C 242  (e.g., having a capacitance of approximately 1 μF). The inverter power supply  240  comprises a simple zener-regulated power supply having a zener diode Z 243 , which is coupled across the storage capacitor C 242  and may have, for example, a break-over voltage of approximately 13.2 volts. When the screw-in compact fluorescent lamp  120  is first powered up, the storage capacitor C 242  is able to charge by conducting a small trickle current from the AC power source  15  through a resistor R 244  (e.g., having a resistance of approximately 392 kΩ) until the inverter supply voltage V INV  is developed across the storage capacitor C 242 . After the magnitude of the inverter supply voltage V INV  exceeds the rated operating voltage of the inverter control IC U 300  of the inverter control circuit  216 , the inverter control IC begins to control the FETs Q 212 , Q 214  to be conductive and non-conductive to generate the square wave voltage V SQ . 
     The inverter power supply  240  further comprises a snubber capacitor C 245  that has, for example, a capacitance of approximately 470 pF and provides a path for charging the storage capacitor C 242  after the inverter control circuit  216  begins generating the square wave voltage V SQ . The snubber capacitor C 245  is coupled between junction of the two FETs Q 212 , Q 214  and the storage capacitor C 242  through a diode D 246  and a resistor R 246  (e.g., having a resistance of approximately 5.6Ω). The storage capacitor C 242  is able to charge when the first FET Q 212  is conductive (i.e., when the square-wave voltage V SQ  is being pulled high towards the bus voltage V BUS ). When the second FET Q 214  is conductive and the square-wave voltage V SQ  is being pulled low towards circuit common, the snubber capacitor C 245  is able to discharge through the second FET Q 214  and a diode D 248 . Accordingly, after the inverter control circuit  216  begins generating the square wave voltage V SQ , the inverter power supply  240  is operable to generate the inverter supply voltage V INV  by conducting current through the snubber capacitor C 245  rather than conducting current through the resistor R 244 , which would needlessly dissipate an excessive amount of power. 
     The control power supply  250  comprises a linear regulator, for example, an adjustable linear regulator U 252 , such as part number LM317L, manufactured by Fairchild Semiconductor Incorporated. The control power supply  250  comprises a winding  254  magnetically coupled to the resonant inductor L 222  of the resonant tank circuit  220  for generating an electromagnetically-coupled voltage, such that the linear regulator U 252  is able to draw current from the resonant tank circuit through a diode D 255  when the inverter control circuit  216  is generating the square-wave voltage V SQ . A capacitor C 256  is coupled across the input of the linear regulator U 252  and has, for example, a capacitance of approximately 0.1 μF. A first resistor R 258  is coupled between the output of the adjustable linear regulator U 252  and the adjustment pin of the linear regulator, while a second resistor R 259  is coupled between the adjustment pin and circuit common. For example, the first and second resistors R 258 , R 259  may have resistances of approximately 475Ω and 5.23 kΩ, respectively, such that the control supply voltage V CC  at the output of the linear regulator U 252  has a nominal magnitude of approximately 15 volts. 
       FIG. 7  is a simplified schematic diagram of the inverter circuit  210  and the OVP circuit  260 . As previously mentioned, the inverter control circuit  216  includes the inverter control IC U 300 , which is powered by the inverter supply voltage V INV . The inverter control IC U 300  is directly coupled to the gates of the FETs Q 212 , Q 214  for controlling the FETs to be conductive and non-conductive (via pins  16  and  13 ). The inverter control circuit  216  comprises a preheat-frequency-set resistor R PH , which is coupled to a preheat-frequency-set input (pin  7 ) of the inverter control IC U 300  for setting the preheat frequency f PH . The preheat-frequency-set resistor R PH  may have a resistance of, for example, approximately 27 kΩ, such that the preheat frequency f PH  is approximately 150 kHz. The inverter control circuit  216  also comprises a preheat-time-set capacitor C PH , which is coupled to a preheat-time-set input (pin  5 ) of the inverter control IC U 300  for setting the length of the preheat time period T PH . For example, the preheat-time-set capacitor C PH  may have a capacitance of approximately 0.33 μF, such that the preheat time period T PH  is approximately 700 msec. 
     During the preheat time period T PH , a voltage V RPH  generated across the preheat-frequency-set resistor R PH  (i.e., at pin  7 ) is maintained constant, while a voltage V CPH  generated across the preheat-time-set capacitor C PH  (i.e., at pin  5 ) increases in magnitude with respect to time from approximately zero volts. When the voltage V CPH  across the preheat-time-set capacitor C PH  exceeds a preheat voltage threshold V PH  at the end of the preheat time period T PH , the inverter control IC U 300  then controls the operating frequency f OP  to attempt to strike the lamp tube  122 . The voltage V RPH  across the preheat-frequency-set resistor R PH  and the voltage V CPH  across the preheat-time-set capacitor C PH  are also provided to the control circuit  230 , such that the control circuit is operable to properly control the inverter control IC U 300  during the preheat time period T PH  as will be described in greater detail below. 
     The inverter control circuit  216  comprises an operating-frequency-set resistor R T  coupled to an frequency-set-resistor input (pin  8 ) of the inverter control IC U 300  and an operating-frequency-set capacitor C T  coupled to a frequency-set-capacitor input (pin  6 ) for setting the operating frequency f OP  of the square-wave voltage V SQ  when the lamp tube  122  is illuminated (i.e., after the lamp tube has been struck). For example, the operating-frequency-set resistor R T  may have a resistance of approximately 30 kΩ and the operating-frequency-set capacitor C T  may have a capacitance of approximately 330 pF, such that a default operating frequency of the square-wave voltage V SQ  is approximately 110 kHz. 
     The inverter control circuit  216  further comprises an NPN bipolar junction transistor Q 310  having a collector-emitter junction coupled between the frequency-set-resistor input of the inverter control IC U 300  and circuit common through a resistor R 312  (e.g., having a resistance of approximately 10 kΩ). The base of the transistor Q 310  is coupled to receive the drive control signal V DR  from the control circuit  230 . The drive control signal V DR  has a DC magnitude that is representative of a target operating frequency f TRGT  to which the operating frequency f OP  should be controlled to control the intensity of the lamp tube  122  to the target intensity L TRGT . The transistor Q 310  is controlled to operate in the linear region, such that the transistor Q 310  provides a controllable impedance between the frequency-set-resistor input of the inverter control IC U 300  and circuit common in response to the DC magnitude of the drive control signal V DR . Accordingly, the control circuit  230  is operable to adjust the operating frequency f OP  of the square-wave voltage V SQ  by controlling the impedance provided by the transistor Q 310  and thus the current conducted through the frequency-set-resistor input of the inverter control IC U 300 . 
     The inverter control circuit  216  receives the OVP control signal V OVP  from the OVP circuit  260 . Specifically, the OVP control signal V OVP  is coupled to an open lamp protection (OLP) input (pin  10 ) of the inverter control IC U 300  through a resistor R 320  (e.g., having a resistance of approximately 10 kΩ), and is coupled to circuit common through a capacitor C 322  (e.g., having a capacitance of approximately 0.1 μF). The OVP circuit  260  comprises a voltage divider having resistors R 261 , R 262  for scaling the magnitude of the lamp voltage V LAMP  down to a magnitude that is appropriate to be received by the inverter control IC U 300 . For example, the resistors R 261 , R 262  may have resistances of approximately 1 MΩ and 25.5 kΩ, respectively. The junction of the resistors R 261 , R 262  is coupled to a capacitor C 264  (e.g., having a capacitance of approximately 0.1 μF) through a diode D 265 . The junction of the capacitor C 264  and the diode D 265  is coupled to the inverter control circuit  216  through a zener diode Z 266  for generating the OVP control signal V OVP , which is coupled to circuit common through a resistor R 268  (e.g., having a resistance of approximately 100 kΩ). For example, the zener diode Z 266  may have a break-over voltage of approximately 13.2 volts. 
     During normal operation, the voltage at the OLP input of the inverter control IC U 300  remains low (i.e., at approximately circuit common). However, in the event of an overvoltage condition across the lamp tube  122 , the zener diode Z 266  begins to conduct, such that the voltage at the OLP input of the inverter control IC U 300  increases in magnitude. When the magnitude of the voltage at the OLP input exceeds an OLP threshold voltage of the inverter control IC U 300  (e.g., approximately 2 volts), the inverter control IC disables the outputs (i.e., pins  13  and  16 ) such that the FETs Q 212 , Q 214  are rendered non-conductive and the lamp tube  122  is not illuminated until the control circuit  230  controls the inverter circuit  210  to attempt to restrike the lamp tube once again. 
       FIG. 8  is a simplified schematic diagram of the control circuit  230 . The control circuit  230  comprises a two-speed phase-to-DC converter circuit  400  for converting the phase-control input control signal V PC-IN  to a DC target voltage V TRGT  that is representative of the duty-cycle DC PC  of the phase-control voltage V PC  and thus the target intensity L TRGT  of the lamp tube  122 . The DC target voltage V TRGT  is amplified by a non-inverting amplifier circuit  420  to generate an amplified target voltage V A-TRGT , such that the magnitude of the amplified target voltage V A-TRGT  is within a correct range to be received by an error amplifier circuit  430 . For example, the DC target voltage V TRGT  may be in the range of approximately 1-4 volts, while the amplified target voltage V A-TRGT  is in the range of approximately 0.5-6.5 volts. A non-linear amplifier circuit  440  receives the lamp current control signal V ILAMP  from the lamp current sense circuit  270  and generates an amplified lamp current signal V A-ILAMP . The error amplifier circuit  430  receives the amplified target voltage V A-TRGT  and the amplified lamp current signal V T-ILAMP  and generates the drive control signal V DR  to adjust the operating frequency f OP  of the inverter circuit  210 , so as to minimize the error between the amplified target voltage V A-TRGT  and the amplified lamp current signal V T-ILAMP . 
     The phase-to-DC converter circuit  400  comprises a voltage divider having two resistors R 401 , R 402  for scaling down the phase-control input control signal V PC-IN . For example, the resistors R 401 , R 402  may have resistances of approximately 1 MΩ and 47 kΩ, respectively. Next, the phase-to-DC converter circuit  400  generates a switched voltage V S  that has a duty-cycle approximately equal to the duty cycle DC PC  of the phase-control input control signal V PC-IN . Specifically, the junction of the resistors R 401 , R 402  is coupled to the base of a first NPN bipolar junction transistor Q 404  that has a collector-emitter junction coupled between the control supply voltage V CC  and circuit common through a resistor R 405  (e.g., having a resistance of approximately 220 kΩ). The junction of the collector of the transistor Q 404  and the resistor R 405  is coupled to the base of a second NPN bipolar junction transistor Q 406  that has a collector-emitter junction coupled between the control supply voltage V CC  and circuit common through two resistors R 408 , R 409  (e.g., having resistances of approximately 40 kΩ and 1 kΩ, respectively). Accordingly, the switched voltage V S  is generated at the collector of the second transistor Q 406 . 
     When the magnitude of the phase-control input control signal V PC-IN  is approximately zero volts (i.e., when the bidirectional semiconductor switch  32  of the dimmer switch  30  is non-conductive), the first transistor Q 404  is rendered non-conductive, such that the second transistor Q 406  is rendered conductive and the switched voltage V S  is pulled low towards circuit common. When the magnitude of the phase-control input control signal V PC-IN  is greater than a phase-control threshold, e.g., approximately 15 volts (i.e., when the bidirectional semiconductor switch  32  of the dimmer switch  30  is conductive), the first transistor Q 404  is rendered conductive, such that the second transistor Q 406  is rendered non-conductive and the switched voltage V S  is pulled high towards control supply voltage V CC  through the resistors R 408 , R 409 . 
     A ramp voltage V R  is generated across a capacitor C 410  (e.g., having a capacitance of approximately 0.22 μF) in response to the square-wave voltage V S . When the second transistor Q 406  is non-conductive, the capacitor C 410  is able to charge towards the control supply voltage V CC  through the resistor R 408 , such that the magnitude of the ramp voltage V R  increases with respect to time while the switched voltage V S  is high. When the second transistor Q 406  is conductive, the capacitor C 410  is able to discharge through the resistor R 409 , such that the magnitude of the ramp voltage V R  decreases at a second rate that is much faster than the first rate at which the ramp voltage increases in magnitude. Accordingly, the ramp voltage V R  is generated across the capacitor C 410  and has a duty cycle equal to approximately the duty cycle of the phase-control input control signal V PC-IN . Next, the ramp voltage V R  is filtered by a first filter circuit, e.g., a resistor-capacitor (RC) circuit (including a resistor R 411  and a capacitor C 412 ), to generate a filtered voltage V F . For example, the resistor R 411  has a resistance of approximately 220 kΩ and the capacitor C 412  has a capacitance of approximately 0.22 μF, such that the first RC circuit has a time constant τ RC1  of approximately 48.4 msec. 
     The filtered voltage V F  from the first RC circuit is then filtered by a second RC circuit (having a resistor R 413  and a capacitor C 414 ) to generate the target voltage V TRGT . Two diodes D 416 , D 418  are coupled in anti-parallel connection across the resistor R 413 . For example, the resistor R 413  has a resistance of approximately 2.2 MΩ and the capacitor C 414  has a capacitance of approximately 0.22 μF, such that a time constant τ RC2  of the second RC circuit has a nominal value of approximately 484 msec (i.e., approximately 10 times slower than the first RC circuit). The magnitude of the target voltage V TRGT  is a function of the square of the conduction time T CON  of the bidirectional semiconductor switch  32  of the dimmer switch  30 , i.e., V TRGT =ƒ(T CON   2 ). Accordingly, the control circuit  230  is operable to adjust the intensity of the lamp tube  122  in response to the duty-cycle DC PC  of the phase-control voltage V PC  according to a “square-law” dimming curve. As a result, the control circuit  230  provides finer tuning of the intensity of the lamp tube  122  near the low-end intensity L LE , such that larger variations in the conduction time T CON  of the bidirectional semiconductor switch  32  result in smaller changes in the intensity of the lamp tube  122  near the low-end intensity L LE . 
     Voltage fluctuations in the AC mains line voltage V AC  of the AC power source  15  or noise on the AC mains line voltage V AC  can cause the duty-cycle DC PC  of the phase-control signal V PC  and the magnitude of the filtered voltage V F  to vary slightly. Therefore, the slow nominal value τ RC2-NOM  of the time constant τ RC2  of the second RC circuit provides enough filtering such that the target voltage V TRGT  is not responsive to changes in the filtered voltage V F  that are less than a predetermined threshold, e.g., approximately the forward voltage of the diodes D 416 , D 418 , i.e., a diode drop (e.g., approximately 0.7 volts). 
     However, changes in the target intensity L TRGT  at the dimmer switch  30  that result in the dimmer switch changing the duty cycle DC PC  of the phase-control signal V PC  cause the magnitude of the filtered voltage V F  to change by greater amounts and at faster rates than the voltage fluctuations and noise of the AC mains line voltage V AC . Therefore, when the magnitude of the filtered voltage V F  changes by more than the forward voltage of the diodes D 416 , D 418 , one of the diodes D 416 , D 418  will begin to conduct such that the magnitude of the target voltage V TRGT  across the capacitor C 414  changes quickly in response to changes in the target intensity L TRGT . Specifically, the first diode D 416  is operable to conduct current into the capacitor C 414  when the target intensity L TRGT  increases, such that the time constant τ RC2  has a fast value τ RC2-FAST  that is less than the nominal value τ RC2-NOM . In addition, the capacitor C 414  is operable to discharge through the diode D 418  with the fast value τ RC2-FAST  when the target intensity L TRGT  decreases. Accordingly, the two-speed phase-to-DC converter circuit  400  is able to filter out changes in the duty cycle DC PC  of the phase-control voltage V PC  due to voltage fluctuations and noise of the AC mains line voltage V AC  while still providing a fast response as a result of changes in the target intensity L TRGT . 
     Each of the diodes D 416 , D 418  stops conducting when the difference between the magnitudes of the target voltage V TRGT  and the filtered voltage V F  falls below approximately the forward voltage of the respective diode. After the diodes D 416 , D 418  stop conducting, the magnitude of the target intensity L TRGT  will slowly change to be equal to the magnitude of the filtered voltage V F  (according to the nominal time constant τ RC2-NOM ) until the magnitudes of the voltages are equal. This results in a slow fading of the intensity of the lamp tube  122  at the end of a change in the target intensity L TRG , which provides a pleasant, soft effect on a human eye that is observing the change in the intensity of the lamp tube. 
     The non-inverting amplifier circuit  420  comprises an operational amplifier (“op amp”) U 421 , such as, for example, part number LM2902PWR, manufactured by National Semiconductor Corporation. The target voltage V TRGT  is coupled to the non-inverting input of the op amp U 421 , while an offset voltage V OFF  is coupled to the inverting input of the op amp through a resistor R 422  (e.g., having a resistance of approximately 160 kΩ). The offset voltage V OFF  is generated by a voltage divider that is coupled between the control supply voltage V CC  and circuit common, and includes two resistors R 424 , R 425 . For example, the resistors R 424 , R 425  may have resistances of approximately 33 kΩ and 5 kΩ, respectively, such that the offset voltage V OFF  has a magnitude of approximately 2 volts. The output of the op amp U 421  is coupled the inverting input via the parallel combination of a resistor R 426  (e.g., having a resistance of approximately 150 kΩ) and a capacitor C 428  (e.g., having a capacitance of approximately 0.22 μF). The magnitude of the amplified target voltage V A-TRGT  ranges from approximately 0.5 to 6.5 volts as the magnitude of the target voltage V TRGT  ranges from approximately 1 to 4 volts. 
     The non-linear amplifier circuit  440  receives the lamp current control signal V ILAMP  from the lamp current sense circuit  270 , which is shown in  FIG. 6 . The lamp current control signal V ILAMP  is generated across the parallel combination of a resistor R 272  (e.g., having a resistance of approximately 4Ω) and a capacitor C 274  (e.g., having a capacitance of approximately 2.2 μF). During the negative half-cycles of the lamp current I LAMP , the lamp current is conducted through a diode D 276  and the parallel combination of the resistor R 272  and the capacitor C 274 . During the positive half-cycles of the lamp current I LAMP , the lamp current is conducted through a diode D 278  and is not conducted through the parallel combination of the resistor R 272  and the capacitor C 274 . Accordingly, the lamp current control signal V ILAMP  has a negative magnitude that is representative of the magnitude of the lamp current I LAMP  during the negative half-cycles of the lamp current. Since the resistor R 272  only conducts the lamp current I LAMP  every other half-cycle, the resistor R 272  dissipates half of the amount of power that would be dissipated if the resistor R 272  conducted the lamp current each half-cycle. 
     Referring back to  FIG. 8 , the non-linear amplifier circuit  440  comprises an op amp U 441  having a non-inverting input coupled to circuit common and an inverting input coupled to receive the lamp current control signal V ILAMP  through a resistor R 442  (e.g., having a resistance of approximately 1 kΩ). The output of the op amp U 441  is coupled to the inverting input through a resistor R 444  (e.g., having a resistance of approximately 68.1 kΩ). The non-linear amplifier circuit  440  further comprises a PNP bipolar junction transistor Q 445  and a resistor R 446  (e.g., having a resistance of approximately 27 kΩ). The series combination of the collector-emitter junction of the transistor Q 445  and the resistor R 446  is also coupled between the inverting input and the output of the op amp U 441 . A capacitor C 448  is coupled is parallel with the resistor R 446  and may have, for example, a capacitance of approximately 470 μF. 
     When the magnitude of the lamp current I LAMP  is less than a current threshold (e.g., approximately 100 mA), the magnitude of the amplified lamp current signal V A-ILAMP  is less than approximately the rated emitter-base voltage of the transistor Q 445 . At this time, only the resistor R 444  is coupled between the inverting input and the output of the op amp U 441 , such that the non-linear amplifier circuit  440  is characterized by a first gain α 1  (e.g., approximately −68). However, when the magnitude of the lamp current I LAMP  is greater than the current threshold, the transistor Q 445  is rendered conductive, such that the resistor R 446  is coupled in parallel with the resistor R 444  between the inverting input and the output of the op amp U 441 . Accordingly, above the current threshold, the non-linear amplifier circuit  440  is characterized by a second gain α 2  that has a smaller magnitude than the first gain α 1  (e.g., approximately −25). 
     The error amplifier circuit  430  comprises an op amp U 431  having a non-inverting input coupled to receive the amplified lamp current signal V A-ILAMP  and an inverting input coupled to receive the amplified target voltage V A-TRGT  through a resistor R 432  (e.g., having a resistance of approximately 30 kΩ). The error amplifier circuit  430  further comprises two capacitors C 434 , C 435  (e.g., each having a capacitance of approximately 4.7 nF) and a resistor R 436  (e.g., having a resistance of approximately 47 kΩ). The capacitor C 434  is coupled between the inverting input and the output of the op amp U 431 , while the series combination of the capacitor C 435  and the resistor R 436  is also coupled between the inverting input and the output of the op amp U 431 . The output of the op amp U 431  is coupled to circuit common through a resister divider having two resistors R 438 , R 439  (e.g., having resistances of 18.7 kΩ and 6.8 kΩ, respectively), where the drive control signal V DR  is produced at the junction of the resistors R 438 , R 439 . The error amplifier circuit  430  operates to adjust the operating frequency f OP  of the inverter circuit  210  so as to minimize the error (i.e., the difference) between the amplified lamp current signal V A-ILAMP  and the amplified target voltage V A-TRGT . For example, the error amplifier circuit  430  may be characterized by a cutoff frequency of greater than or equal to approximately 10 kHz (i.e., the control circuit  230  has a bandwidth greater than or equal to approximately 10 kHz). 
     As previously mentioned, the lamp tube  122  of the screw-in compact fluorescent lamp  120  of the embodiment of the present invention may be filled with the fill-gas mixture having a fill-gas pressure of approximately 2 Torr and a fill-gas ratio of approximately 85:15 argon to neon.  FIG. 9  is an example V-I curve  500  (i.e., the plot of the magnitude of the lamp voltage V LAMP  across the lamp tube  122  with respect to the magnitude of the lamp current I LAMP  conducted through the lamp tube) according to the embodiment of the present invention.  FIG. 9  also shows an example V-I curve  550  of the prior art screw-in compact fluorescent lamp  20  that has a fill gas of 100% argon at a pressure of approximately 4 Torr. 
     By combining the lamp tube  122  having the fill-gas mixture having a fill-gas ratio of approximately 85:15 argon to neon at a pressure of approximately 2 Torr and the error amplifier  430  having a cutoff frequency of approximately 10 kHz, the V-I curve  500  of the screw-in compact fluorescent lamp  120  of the embodiment of the present invention is much “flatter” than the V-I curve  550  of the prior art screw-in compact fluorescent lamp  20  as shown in  FIG. 9 . In other words, the magnitude of the lamp voltage V LAMP  does not changes as much with respect to the magnitude of the lamp current I LAMP  as in the prior art screw-in compact fluorescent lamp  20 . Therefore, the size of the components of the resonant tank circuit  220  may be smaller and the resonant tank circuit may operate more efficiently during normal operation. Since the filament windings  229 A,  229 B are magnetically coupled to the resonant inductor L 222 , the flatter V-I curve  500  of the screw-in compact fluorescent lamp  120  of the embodiment of the present invention provides for more favorable magnitudes of the filament voltages across the dimming range of the lamp tube  122 , particularly, near the near the low-end intensity L LE  when the magnitude of the lamp voltage V LAMP  begins to decrease as the magnitude of the lamp current I LAMP  decreases. 
       FIGS. 10A and 10B  show example waveforms of the DC bus voltage V BUS  and the lamp current I LAMP , respectively, of the screw-in compact fluorescent lamp  120  of the embodiment of the present invention. Since the cutoff frequency of the error amplifier circuit  430  (i.e., approximately 10 kHz) is much greater than the frequency of the voltage ripple of the bus voltage V BUS  (i.e., approximately 120 Hz), the control circuit  230  is able to adjust the operating frequency f OP  of the square-wave voltage V SQ  (and thus the lamp current I LAMP ) within a single half-cycle of the AC power source  15 . Therefore, the operating frequency f OP  changes in magnitude in response to the voltage ripple of the bus voltage V BUS  during each half-cycle and the lamp current I LAMP  has an envelope I ENV  that is relatively constant or flat (as shown in  FIG. 10B ). It has been observed that this high speed operation of the error amplifier circuit  430  reduces flickering in the lamp tube  122 , particularly when the lamp tube is cold and/or has just been started up. In addition, since the operating frequency f OP  of the inverter circuit  210  changes during each half-cycle even when the screw-in compact fluorescent lamp  120  is maintaining the target intensity L TRGT  of the lamp tube  122  constant, the compact fluorescent lamp does not generate EMI noise at specific frequencies, but spreads the frequency of the EMI noise out over a range, such that the peak magnitude of the noise is decreased. 
     Referring back to  FIG. 8 , the control circuit  230  further comprises a preheat adjustment circuit  450  that modifies the operation of the phase-to-DC converter circuit  400  while the load regulation circuit  130  is preheating the filaments  228 A,  228 B of the lamp tube  122  (i.e., during the preheat time period T PH ). The preheat adjustment circuit  450  comprises an op amp U 452  having a non-inverting input coupled to receive the voltage V RPH  across the preheat-frequency-set resistor R PH  of the inverter control circuit  216 , and an inverting input coupled to receive the voltage V CPH  across the preheat-time-set capacitor C PH . The output of the op amp U 452  is coupled to the capacitor C 410  of the phase-to-DC converter circuit  400  through a resistor R 454  (e.g., having a resistance of approximately 464 kΩ). As previously mentioned, while the inverter control IC U 300  is preheating the filaments  228 A,  228 B of the lamp tube  122 , the voltage V RPH  across the preheat-frequency-set resistor R PH  is maintained constant, while the voltage V CPH  across the preheat-time-set capacitor C PH  increases in magnitude with respect to time from approximately zero volts. During the preheat time period T PH , the op amp U 452  injects current into the capacitor C 410  of the phase-to-DC converter circuit  400 , such that the magnitude of the target voltage V TRGT  increases. Therefore, if the lamp tube  122  is being turned on to an intensity near the low-end intensity L LE , the magnitude of the lamp current I LAMP  will be large enough at the end of the preheat time period T PH  to ensure that the arc current is established in the lamp tube when the lamp tube is struck. After the arc current has been properly established in the lamp tube  122 , the op amp U 452  stops injecting current into the capacitor C 410  of the phase-to-DC converter circuit  400  and the intensity of the lamp tube is controlled in response to the target intensity L TRGT  determined from the duty-cycle DC PC  of the phase-control voltage V PC . 
     Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.