Abstract:
In a three-phase inverter configured driving circuit and method, three switch assemblies are connected in parallel between an input voltage and a reference voltage and switched to generate a three-phase AC voltage on the primary side of a three-phase transformer, so as to be transformed to a three-phase current from the secondary side of the transformer to provide for three loadings.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates generally to a driving circuit, and more particularly, to a driving circuit and method for three-phase cold cathode fluorescent lamps (CCFL).  
         BACKGROUND OF THE INVENTION  
         [0002]    CCFL has been widely used for the backlight of display, especially the liquid crystal display (LCD), due to its advantages of power saving, low power dissipation, decreased heat generation, long life time, small size, light weight, high illumination, high color rendering, and moderate lamp temperature after long-term used. Conventionally, it is sufficient of only one CCFL for a display, because of the small size of the display. As the progress in technology, however, the display becomes larger and therefore the amount of the CCFLs served as the light source has to be increased. Thus, there is a need for a driving circuit capable of driving several CCFLs.  
           [0003]    A driving circuit proposed by U.S. Pat. No. 6,396,722 issued to Lin comprises four MOS transistors and one transformer to be constituted a full-bridge circuit to drive CCFL. However, only one CCFL could be driven by this circuit, and several such individual full-bridge circuits are needed if several CCFLs to be driven. Further, due to the fact that MOS transistor and transformer are all costly elements, the more ones being used, the cost is higher.  
           [0004]    Therefore, it is desired a driving circuit capable of driving several CCFLs with a reduced cost.  
         SUMMARY OF THE INVENTION  
         [0005]    It is an object of the present invention to disclose a driving circuit and method that employs a three-phase inverter configuration for driving a plurality of CCFLs.  
           [0006]    It is another object of the present invention to propose a driving circuit and method capable of driving a plurality of CCFLs with reduced cost.  
           [0007]    In a driving circuit configured in a three-phase inverter, according to the present invention, it is comprised a first switch assembly including a first high-side switch connected between an input voltage and a first node, and a first low-side switch connected between the first node and a reference voltage, a second switch assembly including a second high-side switch connected between the input voltage and a second node, and a second low-side switch connected between the second node and reference voltage, a third switch assembly including a third high-side switch connected between the input voltage and a third node, and a third low-side switch connected between the third node and reference voltage, and a three-phase transformer with three terminals of its primary side connected to the three nodes, respectively, and three terminals of its secondary side connected to three loadings, respectively. The switches are switched to generate a first AC voltage between the first and second nodes, a second AC voltage between the second and third nodes, and a third AC voltage between the third and first nodes, respectively. The three AC voltages are further transformed to three AC currents by the three-phase transformer to provide for the three loadings, and each of them includes at least one CCFL to be driven by the AC current flowing therethrough.  
       
    
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0008]    These and other objects, features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings, in which:  
         [0009]    [0009]FIG. 1 shows a driving circuit configured in a three-phase inverter according to the present invention;  
         [0010]    [0010]FIG. 2 shows a timing diagram of the waveforms of the voltages between the nodes A and B, B and C, and C and A, respectively, of the circuit shown in FIG. 1;  
         [0011]    [0011]FIG. 3 shows a timing diagram of the waveforms of the currents flowing through three CCFLs of the circuit shown in FIG. 1;  
         [0012]    [0012]FIG. 4 shows another embodiment driving circuit according to the present invention;  
         [0013]    [0013]FIG. 5 shows a further embodiment driving circuit according to the present invention; and  
         [0014]    [0014]FIG. 6 shows an application of the driving circuit according to the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0015]    [0015]FIG. 1 shows a preferred embodiment of a driving circuit  10  configured in a three-phase inverter, which comprises a switch assembly  12  connected between an input voltage V in  and ground GND 1 , and including a high-side NMOS transistor  122  connected between the input voltage V in  and node A, and a low-side NMOS transistor  124  connected between the node A and ground GND 1 . Likewise, another switch assembly  14  is connected between the input voltage V in  and ground GND 1 , and includes a high-side NMOS transistor  142  connected between the input voltage V in  and node B, and a low-side NMOS transistor  144  connected between the node B and ground GND 1 , and a third switch assembly  16  is connected between the input voltage V in  and ground GND 1 , and includes a high-side NMOS transistor  162  connected between the input voltage V in  and node C, and a low-side NMOS transistor  164  connected between the node C and ground GND 1 . In addition, six diodes D 1 -D 6  are connected in parallel to the six NMOS transistors  122 - 164 , respectively, and a three-phase transformer  18  including two transformers TX 1  and TX 2  connected in series has its primary side connected to the nodes A, B and C, and its secondary side connected with three CCFLs  20 ,  22  and  24  between thereto and ground GND 2 . All the NMOS transistors  122 ,  124 ,  142 ,  144 ,  162 , and  164  are provided for switches each under the control of one of the signals S 1 , S 2 , S 3 , S 4 , S 5 , and S 6 .  
         [0016]    [0016]FIG. 2 shows waveforms  26 ,  28 , and  30  for the voltages V AB  between the nodes A and B, V BC  between the nodes B and C, as well as V CA  between the nodes C and A, respectively, of the circuit shown in FIG. 1, where the phases of these three AC voltages are displaced from each other by 120 degrees. In conjunction of referring to FIG. 1, in the operation of the circuit  10 , the transistors  122 ,  144 , and  162  are turned on to conduct currents I AB , I CB  and I CA  during the time period of 0 to t 1 , the transistors  122 ,  144 , and  164  are turned on to conduct currents I AB , I CB  and I AC  during the time period of t 1  to t 2 , the transistors  122 ,  142 , and  164  are turned on to conduct currents I AB , I BC  and I AC  during the time period of t 2  to t 3 , the transistors  124 ,  142 , and  164  are turned on to conduct currents I BA , I BC  and I AC  during the time period of t 3  to t 4 , the transistors  124 ,  142 , and  162  are turned on to conduct currents I BA , I BC  and I CA  during the time period of t 4  to t 5 , and the transistors  124 ,  144 , and  162  are turned on to conduct currents I BA , I CB  and I CA  during the time period of t 5  to t 6 . As such, the AC voltage V AB  between the nodes A and B, the AC voltage V BC  between the nodes B and C, and the AC voltage V CA  between the nodes C and A are transformed by the three-phase transformer  18  to AC currents I 1 , I 2  and I 3  to flow through the CCFLs  20 ,  22  and  24 , respectively. From one point of view, systematically, the three AC voltages V AB , V BC  and V CA  form a three-phase voltage, and the three AC currents I 1 , I 2  and I 3  form a three-phase current, since dependence is presented between the three phases.  
         [0017]    From FIG. 2, obviously, each time interval, for example from 0 to t 1 , equals to ⅙ cycle since from 0 to t 6  is a complete cycle, and thus, the voltage waveforms  26 ,  28  and  30  of this embodiment are displaced from each other by 120 degrees in phase. On the other hand, the waveforms  32 ,  34  and  36  shown in FIG. 3 represent the AC current waveforms I 1 , I 2 , and I 3  of the circuit  10  shown in FIG. 1. As in the afore-mentioned operation, the phases of the current waveforms  32 ,  34  and  36  are also displaced from each other by 120 degrees.  
         [0018]    A typical three-phase transformer is constituted by three transformers. However, decreasing of one transformer has no effect on the generation of the three-phase current according to the principle of the three-phase circuit. For the purpose of cost reduction, two transformers TX 1  and TX 2  are preferred to be connected in series to constitute the three-phase transformer  18 . For comparison, the driving circuit proposed by the &#39;722 patent needs three sets of substantially equivalent full-bridge driving circuits and as a result, twelve NMOS transistors and three transformers are needed. In contrast, there needs only six NMOS transistors as well as two transformers for the circuit  10  to drive three CCFLs, which is less than the conventional driving circuit by six NMOS transistors as well as one transformer, resulting in dramatic reduction of cost.  
         [0019]    [0019]FIG. 4 is a second embodiment of the present invention. The driving circuit  38  hereof is similar to the previous driving circuit  10 , except that the three-phase transformer  18  has a Δ-Δ configuration instead, i.e., the three-phase transformer  18  is constituted by three transformers TX 1 , TX 2  and TX 3  connected in Δ-Δ configuration. The connection  1804  at the primary side of the transformer TX 1  is connected to the terminal  1806  at the primary side of the transformer TX 2 , the other terminal  1808  at the primary side of the transformer TX 2  is connected to the terminal  1810  at the primary side of the transformer TX 3 , the other terminal  1812  at the primary side of the transformer TX 3  is connected to the connection  1802  at the primary side of the transformer TX 1 . While the connection  1816  at the secondary side of the transformer TX 1  is connected to the terminal  1818  at the secondary side of the transformer TX 2 , the other terminal  1820  at the secondary side of the transformer TX 2  is connected to the terminal  1822  at the secondary side of the transformer TX 3 , the other terminal  1824  at the secondary side of the transformer TX 3  is connected to the connection  1814  at the secondary side of the transformer TX 1 . Further, the connections  1802 ,  1806  and  1810  are connected to the nodes A, B and C, respectively, and the connections  1814 ,  1818  and  1822  are connected to the CCFLs  20 ,  22  and  24 , respectively. This manner, it is obtained the cost reduction of decreasing six NMOS transistors.  
         [0020]    [0020]FIG. 5 shows a third embodiment of the present invention. The driving circuit  40  is also similar to the circuit  38 , except that the three-phase transformer  18  has a Y-Y connection instead, i.e., the three-phase transformer  18  is constituted by three transformers TX 1 , TX 2  and TX 3  connected in Y-Y configuration. The terminals  1802 ,  1806  and  1810  at the primary sides of the transformers TX 1 , TX 2  and TX 3  are connected to the nodes A, B and C, respectively, and the other terminals  1804 ,  1808  and  1812  of them are connected to ground GND 3 . While the terminals  1814 ,  1818  and  1822  at the secondary sides of the transformers TX 1 , TX 2  and TX 3  are connected to the CCFLs  20 ,  22  and  24 , respectively, and the other terminals  1816 ,  1820  and  1824  are connected to ground GND 4 . It is also obtained in this circuit  40  with the cost reduction of decreasing six NMOS transistors, as for the driving circuit  38 .  
         [0021]    If more than three CCFLs are to be driven, the CCFLs  202 ,  222  and  242  of the circuits  10 ,  38  or  40  could be connected in parallel with other CCFLs, and FIG. 6 shows an exemplatory circuit  42  for such situations.  
         [0022]    While the present invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and scope thereof as set forth in the appended claims.