Abstract:
Method for manufacturing a semiconductor device. The method includes forming source and drain extension regions in an upper surface of a SiGe-based substrate. The source and drain extension regions contain an N type impurity. Reducing vacancy concentration in the source and drain extension regions to decrease diffusion of the N type impurity contained in the first source and drain extension regions.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   The present application is a continuation of U.S. application Ser. No. 10/605,108 filed Sep. 9, 2003, the disclosure of which is expressly incorporated by reference herein in its entirety. 

   BACKGROUND OF INVENTION 
   1. Field of the Invention 
   The invention relates to methods for manufacturing a semiconductor device with improved device performance and a device structure exhibiting the improved device performance, and more particularly to a method for manufacturing a SiGe-based device exhibiting reduced diffusion of an N type impurity. 
   2. Background of the Invention 
   The escalating requirements for ultra large scale integration semiconductor devices require ever increasing high performance and density of transistors. With scaling-down of a device dimension reaching limits, the trend has been to seek new materials and methods that enhance device performance. One of the most preferred methods is through mobility enhancement. 
   It is known that biaxial tensile strain applied to a channel region increases electron mobility in NFET devices. This can be achieved by building an NFET device, which is composed of a set of stacked films (e.g., silicon-SiGe-silicon) on a substrate. Starting from a silicon substrate, SiGe is grown on the silicon substrate. Buffered layers have typically been used to reduce threading dislocation defect density that can affect device leakage but still achieve enough relaxation through misfit dislocation formation. The SiGe film is relaxed so that it has a lattice constant larger than that of silicon. When the silicon is then deposited on the SiGe, it conforms to the larger lattice of the relaxed SiGe and undergoes biaxial tension. The channel is fully contained within this strained silicon and the electron mobility is enhanced. 
   The SiGe-based substrate, however, exhibits certain drawbacks, especially when NFET devices are formed thereon. To form an NFET device, an N type impurity (e.g., As or P) is ion-implanted onto the SiGe-based substrate to form active regions (e.g., source and drain regions). Here, the excessive amount of vacancies contained in the SiGe layer undesirably increases diffusion of the implanted N type impurity. This makes it more difficult to achieve consistent roll-off device characteristics. Therefore, there is a need for effective methodology for manufacturing a SiGe-based semiconductor device. 
   SUMMARY OF INVENTION 
   In an aspect of the invention, a method for manufacturing a semiconductor device is provided. The method includes the step of forming the source and drain extension regions in an upper surface of a SiGe-based substrate. The source and drain extension regions contain an N type impurity. Then, vacancy concentration in the source and drain extension regions is reduced in order to reduce diffusion of the N type impurity contained in the source and drain extension regions. The vacancy concentration is reduced by providing an interstitial element or a vacancy-trapping element in the source and drain extension. 
   In another aspect of the invention, a method is provided for reducing diffusion of an N type impurity in a SiGe-based substrate. Source and drain extension regions are in an upper surface of the SiGe-based substrate. An interstitial element or a vacancy-trapping element is ion-implanted into the source and drain extension regions to reduce vacancy concentration in the source and drain extension regions. 
   Yet another aspect of the invention is a semiconductor device having a SiGe-based substrate. A gate electrode is formed on the SiGe-based substrate with a gate oxide therebetween source and drain extension regions containing an N type impurity are formed in an upper surface of the SiGe substrate. A low vacancy region is formed corresponding to the source and drain extension regions and containing an interstitial element or a vacancy-trapping element. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
     The foregoing and other advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which: 
       FIGS. 1 to 7  depict sequential phases of the method according to an embodiment of the invention. 
   

   DETAILED DESCRIPTION 
   The invention provides a method that significantly reduces undesirable diffusion of the N type impurity in a SiGe-based substrate, thereby improving roll-off characteristics of devices. In an embodiment, the diffusion of N type impurity is reduced by reducing vacancies in source and drain extension regions. The vacancies are reduced by providing an interstitial element (e.g., Si or O) or a vacancy-trapping element (e.g., F, N, Xe, Ar, He, Kr or a noble gas element) to the source and drain extension regions. 
   Typically, the interstitial element creates an additional interstitial per every ion provided thereto, and the additional interstitials react with and annihilate excessive vacancies in the SiGe-based substrate. The vacancy-trapping element trap vacancies and form vacancy-based clusters. Since vacancies are either annihilated or trapped by the interstitial element or the vacancy-trapping element, vacancy concentration is reduced, thereby reducing diffusion of the N type impurity in the source and drain regions. 
     FIG. 1  shows a SiGe-base substrate comprising a SiGe layer  12  formed on a silicon substrate  10 . In an embodiment, the SiGe layer  12  is formed by multiple growing steps forming buffer layers on the silicon substrate  10  for a typical total thickness of approximately 200 Å to 20000 Å. The SiGe layer  12  is then relaxed. A Si cap layer  14  is formed on the SiGe layer  12  by growing on the SiGe layer  12  at a thickness of approximately 30 Å to 400 Å. The Si cap layer  14  is then strained biaxially in tension to match the underlying relaxed SiGe lattice. A gate oxide layer  16  is formed on the Si cap layer  14 . The SiGe-based substrate is divided into an NMOS region and a PMOS region, in which NMOS devices and PMOS devices are formed, respectively. 
     FIG. 2  shows a gate electrode  18  formed on the gate oxide layer  16 . Since the invention is directed to N type devices, a mask  22  is formed selectively on the PMOS region to protect the PMOS devices therein from subsequent processing steps.  FIG. 2  further shows optional sidewalls  20  formed on the side surfaces of the gate electrode  1  for protecting the gate electrode  18  from subsequent ion-implantation steps. 
     FIG. 3  shows only the NMOS region of  FIG. 2 , in which the N type impurity (e.g., As or P) is ion-implanted, as shown by arrows “A”, into the upper surface of the Si cap layer  14  to form source and drain extension regions  24  in the surface portions of the SiGe-based substrate. As shown therein, the ion-implantation is performed in a self-aligned manner by using the gate electrode  18  as a mask, at an implantation concentration of approximately 1×10 14  atoms/cm 2  to 1×10 16  atoms/cm 2  and at an implantation energy of approximately 0.3 KeV to 50 KeV. The concentration peak of the implanted N type impurity is formed at a depth of approximately 10 Å to 1000 Å from an upper surface of the Si cap layer. 
   As described above, diffusion of the N type impurity (e.g., As or P) is significantly and undesirably enhanced in the SiGe-based substrate because the vacancy-based mechanism is more pronounced therein. To solve this problem, as shown in  FIG. 4 , an interstitial element (e.g., Si or O) or a vacancy-trapping element (e.g., F, N, Xe, Ar, He, Kr or other noble gas elements) is ion-implanted onto the source and drain extension regions  24 , as shown by arrows “B”, to form low-vacancy regions  26  that substantially overlap the source and drain extension regions  24 . 
   Upon implantation, damage is caused in such a way that, upon annealing of the damage, the interstitials annihilate the excessive vacancies, thereby reducing the vacancy concentration in the extension regions  24 . Similarly, the implanted vacancy-trapping element traps the excessive vacancies and form vacancy-based clusters, and hence reduces the vacancy concentration in the source and drain extension regions  24 . Annealing at this stage is optional. 
   In an embodiment, the interstitial element or a vacancy-trapping element is ion-implanted at an implantation concentration of approximately 1×10 14  atoms/cm 2  to 1×10 16  atoms/cm 2  and at an implantation energy of approximately 0.3 KeV to 100 KeV. The concentration peak of the implanted interstitial element or the vacancy-trapping element is formed at a depth of approximately 5 Å to 2000 Å from an upper surface of the Si cap layer. Typically the implant profile of the interstitial element or vacancy-trapping element should fully contain the N type impurity profile. The concentration peak of the implanted interstitial element or vacancy-trapping element can be near the N type impurity peak so as to maximize the diffusion retardation. 
   It is not necessary to form the source and drain extension regions  24  prior to ion-implanting the interstitial element or a vacancy-trapping element. The low-vacancy region  26  may be formed prior to forming the source and drain extension regions  24 . Annealing can then be performed to activate the implanted impurity and elements at the same time so that the diffusion through the vacancy-mediated mechanism is controlled. Annealing can also be performed later in the processing steps (e.g., after source and drain formation) or after completion of the fabrication process. 
   After forming sidewall spacers  28 , as shown in  FIG. 5 , the N type impurity is ion-implanted into the SiGe-based substrate, as shown by arrows “C”, to form source and drain regions  30 , as shown in  FIG. 6 . The source and drain regions  30  overlap the source and drain extension regions  24 , respectively. The N type impurity is ion-implanted in the self-aligned manner by using the gate electrode  18  and the sidewall spacers  28  as a mask. In an embodiment, the source and drain regions  30  are formed by ion-implanting the N type impurity at an implantation concentration of approximately 1×10 14  atoms/cm 2  to 1×10 16  atoms/cm 2  and at an implantation energy of approximately 0.3 KeV to 50 KeV. 
     FIG. 7  shows an optional step of ion-implanting the interstitial element or a vacancy-trapping element (e.g., F, N, Xe, Ar, He, Kr or a noble gas element), as shown by arrows “D”, to form low-vacancy regions  32  of the SiGe-based substrate corresponding to the source and drain regions  30  for reducing the vacancy concentration in the SiGe-based substrate. In an embodiment, the low-vacancy regions  32  are formed by ion-implanting the interstitial element or vacancy-trapping element at an implantation concentration of approximately 1×10 14  atoms/cm 2  to 1×10 16  atoms/cm 2  and at an implantation energy of approximately 0.3 KeV to 100 KeV. This step, however, might not be necessary if the vacancy concentration in the SiGe-based substrate has been sufficiently reduced by the previous ion-implantation step shown in  FIG. 4 . Again, the peaks of the N type implants and interstitial elements or vacancy-trapping element in regions  30  and  32  can be aligned on the top of each other or shifted depending upon the diffusion control. 
   Annealing is performed to activate the implanted impurity and cure the implantation damage arising from implanting the interstitial element or a vacancy-trapping element and source and drain implants. In an embodiment, the annealing is performed at a temperature of approximately 700° C. to 1200° C. for approximately 1 second to 3 minutes. This covers the full range of possible anneals including spike, rapid thermal, and furnace anneals. 
   As explained above, the invention provides a method that significantly reduces undesirable diffusion of the N type impurity in a SiGe-based substrate. The diffusion of N type impurity is reduced by reducing vacancies in source and drain extension regions. The vacancies are reduced by providing an interstitial element or a vacancy-trapping element to the source and drain extension regions. The implanted interstitial element creates additional interstitials which react with and annihilate excessive vacancies in the SiGe-based substrate. The implanted vacancy-trapping element traps vacancies and forms vacancy-based clusters. Since vacancies are either annihilated or trapped by the interstitial element or the vacancy-trapping element, vacancy concentration is reduced and diffusion of the N type impurity is reduced in the source and drain regions, thereby improving roll-off characteristics of devices. 
   While the invention has been described in terms of embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims.