Abstract:
To provide a ferroelectric storage device which can read all the quantities of charge (polarization quantity: 2Pr) accumulated in a ferroelectric during a writing operation. In the present invention, a bit line is recharged, a charge quantity required for recharging is detected, and the quantity is read on a sub bit line, thereby achieving a stable reading operation.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to a nonvolatile memory and specifically concerns a reading operation of a semiconductor memory having a ferroelectric capacitor.  
         BACKGROUND OF THE INVENTION  
         [0002]    In recent years, nonvolatile memories having a function of retaining data until power is turned off have been realized by using ferroelectric materials such as PZT, which demonstrates hysteresis characteristics. Such ferroelectric materials are used for a memory cell, so that nonvolatile memories are achieved with simple configurations.  
           [0003]    Since FeRAM (Ferroelectric Random Access Memory) has nonvolatile characteristics and operates at high speed with low voltage, a number of manufacturers of memory chips have been interested in FeRAM. The operating speed of FeRAM is determined by polarization inversion time. The polarization inversion speed of a ferroelectric capacitor is determined by an area of the capacitor, a thickness of a ferroelectric thin film, applied voltage, and so on, and is normally expressed in nanosecounds [ns].  
           [0004]    [0004]FIG. 15 shows a hysteresis loop of a ferroelectric capacitor.  
           [0005]    A vertical axis indicates a quantity of charge induced on a surface of a ferroelectric by spontaneous polarization of the ferroelectric, that is, a polarization quantity [C]. A horizontal axis indicates voltage [V] applied to the ferroelectric capacitor.  
           [0006]    When positive voltage is applied to the ferroelectric in a state in which the ferroelectric capacitor has an inter-terminal voltage of 0 [volt] and polarization does not occur, a polarization quantity increases from S 0  to A of FIG. 15. The ferroelectric does not increase in polarization quantity at a certain voltage (electric field) or more. Namely, a polarization quantity reaches a maximum quantity at point A. The slope at this point is defined by the equation below. 
           
         Cs=dg/dV  
       
           [0007]    where Cs represents a parallel plate capacitance component. Thereafter, even when an inter-terminal voltage of the ferroelectric capacitor is set at 0, a polarization quantity does not change to 0 but remains at S 1 . At this moment, a quantity of held polarization is expressed by Pr [C]. This characteristic is used to realize a nonvolatile memory.  
           [0008]    [0008]FIG. 13 shows a ferroelectric momery including a typical memory cell of 1T1C (one transistor, one capacitor).  
           [0009]    Reference character WL denotes a word line, reference characters BL and XBL denote bit lines, and reference characters BLS and XBLS denote sub bit lines.  
           [0010]    Reference numeral  101  denotes a ferroelectric capacitor having one end connected to a cell plate line CP.  
           [0011]    Reference numeral  103  denotes a reference capacitor having one end connected to a reference capacitor plate line RCP.  
           [0012]    Reference numeral  102  denotes a ferroelectric capacitor selection transistor controlled by the word line WL.  
           [0013]    Reference numeral  104  denotes a reference capacitor selection transistor controlled by a reference capacitor selection line RWL (hereinafter, referred to as a RWL line).  
           [0014]    Reference numeral  112  denotes a sub bit line charge transistor serving as a sub bit charge circuit. The transistor is controlled by a pre-charge control signal PRE to pre-charge the sub bit lines BLS and XBLS to a level of power supply voltage Vdd.  
           [0015]    Reference numeral  111  denotes a transfer gate serving as a bit line charge circuit. The transfer gate is constituted by transistors M 1  and M 2  for connecting the bit lines BL and XBL and the sub bit lines BLS and XBLS, and is controlled by an SSW line.  
           [0016]    Reference numeral  113  denotes a sense amplifier which amplifies a potential difference between the bit lines BL and XBL and is controlled by a sense amplifier control signal SEN.  
           [0017]    Reference numeral  110  denotes a transistor which discharges the bit lines BL and XBL to a ground potential and is controlled by a bit line discharge control signal BLDIS (hereinafter, referred to as a BLDIS line).  
           [0018]    Reference numeral  120  denotes a bit line parasitic capacitance represented as parasitic capacities Cb of the bit lines BL and XBL.  
           [0019]    Reference numeral  121  denotes a sub bit line parasitic capacitance represented as parasitic capacities Cbls of the sub bit lines BLS and XBLS.  
           [0020]    Reference numeral  122  denotes a reading operation control section.  
           [0021]    The reading operation control section  122  is configured so as to have a timing chart of FIG. 14.  
           [0022]    Besides, in the present specification, an activating state will be represented as “H” level.  
           [0023]    At time t 0 , the BLSDIS line is inactivated to cause the bit lines BL and XBL to enter a floating state.  
           [0024]    At time t 1 , the SSW line is activated, and at time t 2 , the bit lines BL and XBL are pre-charged to the Vdd level. Further, the pre-charge control signal PRE is activated to stop the pre-charging of the bit lines BL and XBL.  
           [0025]    At time t 3 , when the word lines WL and RWL are activated at a Vpp level (potential higher than Vdd) and a memory cell is selected, the voltage Vdd is applied to the ferroelectric capacitor  101  and the reference capacitor  103 .  
           [0026]    The following equations approximately indicate a potential Vbl (H) of the bit line when the ferroelectric capacitor  101  stores “H” data, and a potential Vbl (L) of the bit line when the ferroelectric capacitor  101  stores “L” data, respectively. 
             Vbl ( H )= Vdd−{Vdd /( Cb/Cs+ 1)} 
             Vbl ( L )= Vdd−{Vdd /( Cb/Cs+ 1)+(2 Pr/Cs )/( Cb/Cs+ 1)} 
           [0027]    Moreover, the reference capacitor  103  is set such that the reference bit line XBLS has a potential Vxbl expressed by the equation below. 
             Vxbl=Vdd−{Vvp /( Cb/Cs+ 1)+(2 Pr/Cs )/( Cb/Cs+ 1)}/2  
           [0028]    Thus, BL=BLS and XBL=XBLS have a potential difference Vdif.  
                   Vdif   =     VXb1   -   Vb1                 =       Pr   /   Cs     /     (       Cb   /   Cs     +   1     )                     (   1   )                               
 
           [0029]    Subsequently, at time t 4 , the sense amplifier control signal SEN is activated to start the sense amplifier  113 , amplifying a bit line potential difference (|B−XBL|).  
           [0030]    Next, at time t 5 , the cell plate line CP is activated to rewrite “L” data in the ferroelectric capacitor  101 . At time t 6 , the cell plate line CP is inactivated so as to inactivate the sense amplifier control signal SEN. At time t 7 , the BLDIS line is activated to discharge the bit lines BL and XBL. After the bit lines BL and XBL are discharged to VSS, the word line WL is inactivated at time t 8 , and the pre-charge control signal PRE is inactivated at time t 9  to pre-charge the sub bit lines BLS and XBLS. The reading cycle is completed thus.  
         DISCLOSURE OF THE INVENTION  
         [0031]    Equation (1) demonstrates the characteristic of a reading potential which increases as the parasitic capacitance Cb decreases. However, in reality, the bit line brought into a floating state is reduced in potential and sufficient voltage is not applied to the ferroelectric capacitor  101  due to its quantity of polarization charge, so that it is not possible to read all the quantities of charge (polarization charge quantity: 2Pr) accumulated in a ferroelectric.  
           [0032]    Further, when the polarization charge quantity 2Pr is increased by providing a larger area of the ferroelectric capacitor  101  and a smaller thickness of the ferroelectric, the parasitic capacitance Cs also increases. Similarly as the above description, voltage applied to the ferroelectric capacitor  101  decreases, voltage (electric field) applied to the ferroelectric is reduced, so that a quantity of polarization charge during writing cannot be retrieved from the memory cell. It is needless to say that lower voltage applied to the ferroelectric during a low-voltage operation is a more serious problem.  
           [0033]    The present invention has an object to provide a ferroelectric storage device which can fundamentally solve the above-described problems and perform a reading operation with stability.  
           [0034]    The ferroelectric storage device of the present invention comprises reading means for detecting and reading a quantity of charge applied for charging a bit line in bit line charging circuits for charging the bit line connected to a selection transistor, the transistor being connected to a ferroelectric capacitor constituting a ferroelectric memory cell. According to this configuration, it is possible to perform the reading operation with stability as compared with prior art.  
           [0035]    A ferroelectric storage device of the present invention including a ferroelectric memory cell constituted by a selection transistor and a ferroelectric capacitor, the selection transistor having the drain or source connected to one terminal of the ferroelectric capacitor, a word line connected to the gate of the selection transistor, a bit line connected to a drain or source of the selection transistor, the drain or source not being connected to the ferroelectric capacitor, a cell plate line connected to the other terminal of the ferroelectric capacitor, and bit line charge circuits for charging the bit line, characterized by comprising reading means for performing reading by detecting a quantity of charge applied for charging the bit line in the bit line charge circuit after the word line is activated.  
           [0036]    According to this configuration, it is possible to recharge a bit line potential, which is reduced by a reading charge quantity of a ferroelectric during the reading operation. Namely, it is possible to apply voltage not depending upon a reading charge quantity to the ferroelectric capacitor and it is possible to apply the same voltage (electric field) as during the writing operation to the ferroelectric capacitor thus to read all the quantities of charge 2Pr stored in the ferroelectric, thereby improving a reading margin.  
           [0037]    In the ferroelectric storage device of the present invention, the reading means may include sub bit lines (BLS, XBLS) connected to the bit line charge circuit so as to supply charge for charging the bit line, a sub bit line charge circuit for pre-charging the sub bit lines (BLS, XBLS) to a first potential (Vp 1 ), and a sense amplifier for amplifying voltage of the sub bit lines.  
           [0038]    In the ferroelectric storage device of the present invention, the following configuration is also preferable: the reading means activates the sub bit line charge circuit, pre-charges the sub bit lines to the first potential (Vp 1 ) by activating the bit line charge circuit, pre-charges the bit lines to a second potential (Vp 2 ), inactivates the sub bit line charge circuit, activates the word line, selects a memory cell for reading, activates the sense amplifier to amplify voltage of the sub bit lines, and performs the reading operation.  
           [0039]    In the ferroelectric storage device of the present invention, the following configuration is also preferable: the reading means includes a second bit line charge circuit, and the reading means activates the sub bit line charge circuit, pre-charges the sub bit lines to the first potential and pre-charges the bit lines to the second potential (Vp 2 ) by activating the second bit line charge circuit, inactivates the sub bit line charge circuit and the second bit line charge circuit, activates the bit line charge circuit, activates the word line, selects a memory cell for reading, activates the sense amplifier to amplify voltage of the sub bit lines, and performs the reading operation.  
           [0040]    According to this configuration, the second bit line charge circuit is additionally provided, so that current consumption of the first potential (boosting potential) can be reduced, thereby achieving lower current consumption.  
           [0041]    In the ferroelectric storage device of the present invention, the following configuration is also preferable: the reading means includes the second bit line charge circuit, and the reading means pre-charges a potential of the sub bit lines to the first potential (Vp 1 ) in advance, pre-charges the bit line to the second potential (Vp 2 ) by activating the second bit line charge circuit, inactivates the sub bit line charge circuit and the second bit line charge circuit, activates the bit-line charge circuit, activates the word line, selects a memory cell for reading, activates the sense amplifier to amplify voltage of the sub bit lines, and performs the reading operation.  
           [0042]    According to this configuration, in a stand-by state, the sub bit lines are pre-charged to the first potential in advance, so that it is possible to shorten the pre-charging time of the sub bit lines during the reading operation, thereby increasing the speed. Further, current for charging and discharging the sub bit lines can be reduced, thereby achieving lower current consumption.  
           [0043]    In the ferroelectric storage device of the present invention, the following configuration is also preferable: the reading means pre-charges the sub bit lines to a fourth potential (Vp 4 ) by activating the sub bit line charge circuit, inactivates the sub bit line charge circuit, activates the word line and a cell plate, selects a memory cell for reading, activates the sense amplifier to amplify voltage of the sub bit lines, and performs the reading operation.  
           [0044]    In the ferroelectric storage device of the present invention, the bit line charge circuit of the reading means may be a MOS transistor having the source connected to the sub bit line, the drain connected to the bit line, and the gate connected to the third potential (Vp 3 ).  
           [0045]    In the ferroelectric storage device of the present invention, the following configuration is also preferable: the bit line charge circuit of the reading means is an NMOS transistor having the source connected to the sub bit line, the drain connected to the bit line, and the gate connected to the third potential (Vp 3 ), and the first potential (Vp 1 ) and the third potential (Vp 3 ) are equal to the activated potential of a word line selecting signal. According to this configuration, it is not necessary to provide another power supply circuit, resulting in a smaller chip.  
           [0046]    In the ferroelectric storage device of the present invention, the following configuration is also preferable: the bit line charge circuit is a PMOS transistor having the source connected to the sub bit line, the drain connected to the bit line, and the gate connected to the third potential (Vp 3 ), the second potential (Vp 2 ) is lower than a ground potential (Vss), and the fourth potential (Vp 4 ) is lower than the ground potential (Vss). According to this configuration, the necessity for pre-charging the bit lines is eliminated, thereby achieving lower current consumption at high speed.  
           [0047]    In the ferroelectric storage device of the present invention, the bit line charge circuit of the reading means may be a clamping circuit having a bit line potential (SSW) as input.  
           [0048]    In the ferroelectric storage device of the present invention, the following configuration is also preferable: the bit line charge circuit of the reading means is a clamping circuit having a bit line potential (SSW) as input, and the first potential (Vp 1 ) is equal to the activating potential of the word line selecting signal.  
           [0049]    In the ferroelectric storage device of the present invention, the following configuration is also preferable: the bit line charge circuit of the reading means is a clamping circuit having a bit line potential (SSW) as input, and the first potential (Vp 1 ) is lower than the ground potential (Vss).  
           [0050]    In the ferroelectric storage device of the present invention, the reading means may include a sub bit line load capacity on the sub bit lines (BLS, XBLS).  
           [0051]    According to this configuration, it is possible to optimize a reading voltage applied to the sub bit lines, thereby stabilizing a reading potential.  
           [0052]    In the ferroelectric storage device of the present invention, the reading means may be configured such that the sub bit line load capacity is a parasitic bit line capacity of an adjacent memory cell array. According to this configuration, it is not necessary to configure another capacity element, thereby reducing the area.  
           [0053]    In the ferroelectric storage device of the present invention, the reading means may include a ferroelectric deterioration detecting circuit which has a plurality of the sub bit line load capacities, detects deterioration of the ferroelectric, and controls a capacity connected to the sub bit line (BLS). According to this configuration, a capacity added to the sub bit line is controlled, thereby further stabilizing a reading potential.  
           [0054]    In the ferroelectric storage device of the present invention, the reading means may be selectively configured such that the sub bit line load capacities connected to a selection sub bit line (BLS) and a reference sub bit line (XBLS) are different. According to this configuration, it is possible to provide input of the sense amplifier with an offset and to perform screening of a memory cell having a small margin during inspection, thereby improving reliability.  
           [0055]    A reading method of the ferroelectric storage device of the present invention in which the ferroelectric memory cell is formed by the selection transistor and the ferroelectric capacitor, the bit line (BL) is connected to the ferroelectric capacitor via the selection transistor, the sub bit line (BLS) is connected to the bit line (BL) via a transfer gate, the sub bit line (BLS) being pre-charged by the sub bit line charge transistor, and state of the ferroelectric capacitor is read from the sub bit line (BLS) by the sense amplifier, is characterized by comrising the steps of discharging the bit line (BL) and the sub bit line (BLS) to the ground potential (Vss), pre-charging the sub bit line (BLS) to the first potential (Vp 1 ) level via the sub bit line charge transistor; pre-charging the bit line (BL) to the second potential (Vp 2 ) level via the transfer gate, turning on the selection transistor to select the ferroelectric capacitor to carry out charging from the sub bit line (BLS) to the bit line (BL), and reading a quantity of change in reduced potential of the sub bit line (BLS) via the sense amplifier by the charging operation.  
           [0056]    A reading method of the ferroelectric storage device according to another aspect of the present invention in which the ferroelectric memory cell is formed by the selection transistor and the ferroelectric capacitor, the bit line (BL) is connected to the ferroelectric capacitor via the selection transistor, the sub bit line (XBLS) is connected to the bit line (BL) via a transfer gate, the sub bit line (XBLS) being pre-charged by the sub bit line charge transistor, and the state of the ferroelectric capacitor is read from the sub bit line (XBLS) by the sense amplifier, is characterized by comprising the steps of discharging the bit line (BL) and the sub bit line (BLS) to the ground potential (Vss), pre-charging the sub bit line (BLS) to the first potential (Vp 1 ) level via the sub bit line charge transistor, pre-charging the bit line (BL) to the second potential (Vp 2 ) level via the bit line charge transistor, turning on the selection transistor to select the ferroelectric capacitor to carry out charging from the sub bit line (BLS) to the bit line (BL), and reading a quantity of change in reduced potential of the sub bit line. (BLS) via the sense amplifier by the charging operation.  
           [0057]    A reading method of the ferroelectric storage device according to another aspect of the present invention in which the ferroelectric memory cell is formed by the selection transistor and the ferroelectric capacitor, the bit line (BL) is connected to the ferroelectric capacitor via the selection transistor, the sub bit line (XBLS) is connected to the bit line (BL) via the transfer gate, the sub bit line (XBLS) being pre-charged by the sub bit line charge transistor, and the state of the ferroelectric capacitor is read from the sub bit line (XBLS) by the sense amplifier, is characterized by comprising the steps of discharging the bit line (BL) and the sub bit line (BLS) to the ground potential (Vss), pre-charging the sub bit line (BLS) to the fourth potential (Vp 4 ) via the sub bit line charge transistor, turning on the selection transistor to select the ferroelectric capacitor to carry out charging from the sub bit line (BLS) to the bit line (BL), and reading a quantity of change in reduced potential of the sub bit line (BLS) via the sense amplifier by the charging operation. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0058]    [0058]FIG. 1 is a structural diagram showing a ferroelectric storage device according to (Embodiment 1) of the present invention;  
         [0059]    [0059]FIG. 2 is a reading timing chart of (Embodiment 1);  
         [0060]    [0060]FIG. 3 is a hysteresis locus chart of (Embodiment 1);  
         [0061]    [0061]FIG. 4 is a structural diagram showing a ferroelectric storage device according to (Embodiment 2) of the present invention;  
         [0062]    [0062]FIG. 5 is a reading timing chart of (Embodiment 2);  
         [0063]    [0063]FIG. 6 is a structural diagram showing a ferroelectric storage device according to (Embodiment 3) of the present invention;  
         [0064]    [0064]FIG. 7 is a reading timing chart of (Embodiment 3);  
         [0065]    [0065]FIG. 8 is a structural diagram showing a ferroelectric storage device according to (Embodiment 4) of the present invention;  
         [0066]    [0066]FIG. 9 is a structural diagram showing a ferroelectric storage device according to (Embodiment 5) of the present invention;  
         [0067]    [0067]FIG. 10 is a structural diagram showing a ferroelectric storage device according to (Embodiment 6) of the present invention;  
         [0068]    [0068]FIG. 11 is a structural diagram showing a ferroelectric storage device according to (Embodiment 7) of the present invention;  
         [0069]    [0069]FIG. 12 is a structural diagram showing a ferroelectric storage device according to (Embodiment 8) of the present invention;  
         [0070]    [0070]FIG. 13 is a structural diagram showing a ferroelectric storage device including a conventional 1T1C-type memory cell;  
         [0071]    [0071]FIG. 14 is a timing chart showing a reading operation of the conventional example; and  
         [0072]    [0072]FIG. 15 is a hysteresis characteristic diagram showing a ferroelectric capacitor of the conventional example. 
     
    
     DESCRIPTION OF EMBODIMENTS  
       [0073]    Referring to FIGS.  1  to  12 , the following will discuss embodiments of the present invention.  
         [0074]    (Embodiment 1)  
         [0075]    FIGS.  1  to  3  show (Embodiment 1) of the present invention.  
         [0076]    [0076]FIG. 1 shows a ferroelectric storage device according to (Embodiment 1) of the present invention. Those members having the same operations as those of FIG. 13, which illustrates the conventional example, are indicated by the same reference numerals in the explanation below.  
         [0077]    In (Embodiment 1), the configuration of a control section  123  is different from the control section  122  of FIG. 13 illustrating the conventional example. The control section  123  of FIG. 1 is configured so as to control the device according to a timing chart of FIG. 2.  
         [0078]    Further, a ferroelectric memory cell  105  is formed by a selection transistor  102  and a ferroelectric capacitor  101 . A sub bit line charge transistor  112  is a P-type transistor as that of FIG. 13. In (Embodiment 1), the sub bit line charge transistor  112  is controlled by a pre-charge control signal PRE so as to pre-charge a sub bit line (selection sub bit line) BLS and a sub bit line (reference sub bit line) XBLS to a first potential (Vp 1 ) level.  
         [0079]    Bit line charging means for charging the bit line BL is constituted by a transfer gate (bit line charge circuit)  111  and a sub bit line charge transistor  112 .  
         [0080]    The control section  123  is configured to control the device as follows:  
         [0081]    At time t 00 , the bit lines BL and XBL and the sub bit lines BLS and XBLS are discharged to a ground potential Vss. At time t 00 , when a BLDIS line makes a transition to “L”, the pre-charge control signal PRE makes a transition to “L”, and an SSW line makes a transition to a third potential (Vp 3 ), the sub bit lines BLS and XBLS are pre-charged to the first potential (Vp 1 ) via the transistor  112 , and the bit lines BL and XBL are pre-charged to a second potential (Vp 2 ) via the transfer gate  111 .  
         [0082]    Besides, the condition that Vp 1 &gt;Vp 2  and Vp 2 +V T =Vp 3  is established, where V T  represents a threshold voltage of the transistor. Vp 1  is obtained by boosting power supply voltage Vdd by using a booster circuit.  
         [0083]    At time t 0 , when a ferroelectric capacitor is selected while the pre-charge control signal PRE is set at “H” level, the SSW line is set at “L” level, and the word line WL is set at the third potential (Vp 3 ), as shown in FIG. 3, the bit lines BL and XBL decrease by ΔVa and ΔVb according to charge quantities Qa and Qb stored in a memory cell.  
         [0084]    At time t 1 , the SSW line is set at the third potential (Vp 3 ). Now, transistors M 1  and M 2  have increased gate-to-source voltages by ΔVa and ΔVb as compared with the time of pre-charging the bit lines. Thus, charging from the sub bit lines BLS and XBLS to the bit lines BL and XBL is started.  
         [0085]    At this moment, hysteresis is positioned on A and B of FIG. 3 and moves to C in response to the charging. Charges dQa and dQb of FIG. 3 are read by the charging operation, thereby reading all the charges.  
         [0086]    Quantities of charge are expressed by (Qa+dQa) and (Qb+dQb), and charging is performed from a BLS pair (sub bit lines BLS and XBLS). The BLS pair is reduced in potential by the charging operation. The quantities of change are expressed by the equations below. 
         Δ Vas= ( Qa+dQa )/ Cbls    
         Δ Vbs= ( Qb+dQb )/ Cbls    
         [0087]    A reading potential difference is expressed by the equation below.  
               Δ                 V     =       (       Δ                 Vas     -     Δ                 Vbs       )     /   2                 =       (     Qa   -   Qb   +   dQa   -   dQb     )     /     (     2      xCbls     )                                   
 
         [0088]    In this case, in order to perform the charging operation, it is necessary to set the second and third potentials (Vp 2  and Vp 3 ) such that the transistor M 1  or M 2 , connected to a reference bit line, performs a saturating operation from time t 1  to time t 2 .  
         [0089]    A conventional reading potential difference is expressed by the equation below. 
         Δ Vo= ( Qa−Qb )/(2 XCb ) 
         [0090]    Thus, the reading potential difference can be improved from the conventional difference according to the equation below.  
             η   =     Δ                   V   /   Δ                   Vo                 =       Cb   /   Cbs          {     1   +       (     dQa   -   dQb     )     /     (     Qa   -   Qb     )         }                                   
 
         [0091]    Consequently, the reading operation can be stabilized.  
         [0092]    At time t 3 , a reading potential difference ΔV between the sub bit line BLS and the sub bit line XBLS is amplified by starting a sense amplifier  113 . At time t 4 , a cell plate line CP is set at “H” to rewrite “L” data via the selection transistor  102 .  
         [0093]    At time t 5 , the bit lines are discharged while the cell plate line CP, a sense amplifier control signal SEN, and the SSW line are set at “L” and the BLDIS line is set at “H”, and at time t 6 , the word lines WL and RWL are set at “L”. The reading operation is thus completed.  
         [0094]    (Embodiment 1) has a reading sequence in which after the bit lines are pre-charged, the SSW line is set at “L” level once at time t 0 , a ferroelectric capacity is selected while the word line WL is set at the third potential (Vp 3 ), and then, the SSW line is set at the third potential (Vp 3 ) again at time t 1 . It is possible to simultaneously make the transition of the word line WL to the third potential (Vp 3 ) and the transition of the SSW line to the third potential (Vp 3 ), and it is not necessary to make the transition of the SSW line once to “L” level, thereby increasing the speed.  
         [0095]    (Embodiment 2)  
         [0096]    [0096]FIGS. 4 and 5 show (Embodiment 2) of the present invention.  
         [0097]    [0097]FIG. 4 shows a ferroelectric storage device according to (Embodiment 2) of the present invention. Those members having the same operations as those of (Embodiment 1) are indicated by the same reference numerals in the explanation below.  
         [0098]    In (Embodiment 2), a bit line charge transistor  414  is added which is composed of a P-type transistor serving as a second bit line charge circuit, and the configuration of a control section  124  is different. The bit line charge transistor  414  for charging bit lines BL and XBL to a second potential (Vp 2 ) is controlled by a pre-charge control signal BLPRE.  
         [0099]    The control section  124  of FIG. 4 is configured so as to control the device according to a timing chart of FIG. 5.  
         [0100]    At time t 00 , the bit lines BL and XBL and sub bit lines BLS and XBLS are discharged to a ground potential Vss. From time t 00 , a BLDIS line is set at “L” and pre-charge control signals PRE and BLPRE are set at “L”. The sub bit lines BLS and XBLS are pre-charged to a first potential (Vp 1 ) and the bit lines BL and XBL are pre-charged to the second potential (Vp 2 ).  
         [0101]    Besides, the condition that Vp 1 &gt;Vp 2  and VP 2 +V T =Vp 3  is established, where V T  denotes a threshold voltage of a transistor.  
         [0102]    At time t 0 , a ferroelectric capacitor is selected while the pre-charge control signals PRE and BLPRE are set at “H” level and the word line WL is set at a third potential (Vp 3 ). The subsequent operations are similar to those of (Embodiment 1).  
         [0103]    In ordinary cases, the first potential (Vp 1 ) is power supply boosted by a boosting power supply and so on. Vp 1  can be supplied from an external power supply, so that power consumption can be reduced by loss of power conversion.  
         [0104]    Further, in (Embodiment 2) as well, it is possible to simultaneously make a transition of a word line WL to the third potential (Vp 3 ) level and a transition of an SSW line to the third potential (Vp 3 ), thereby increasing the speed.  
         [0105]    Furthermore, the following configuration is also applicable: the sub bit line is pre-charged to the first potential (Vp 1 ) in advance, the bit line is pre-charged to the second potential (Vp 2 ) by activating the bit line charge transistor  414 , the sub bit line charge circuit and the second bit line charge circuit are inactivated, the word line is activated after the bit line charge circuit is activated, a sense amplifier is activated to amplify voltage of the sub bit line after a memory cell for reading is selected, and the reading operation is performed.  
         [0106]    (Embodiment 3)  
         [0107]    [0107]FIGS. 6 and 7 show (Embodiment 3) of the present invention.  
         [0108]    [0108]FIG. 6 shows a ferroelectric storage device according to (Embodiment 3) of the present invention. Those members having the same operations as those of (Embodiment 1) are indicated by the same reference numerals in the explanation below.  
         [0109]    (Embodiment 3) is different from (Embodiment 1) in that a transfer gate  111  is constituted by P-type transistors and a transfer gate  112  is constituted by N-type transistors. Besides, the configuration of a control section  125  is different from that of (Embodiment 1).  
         [0110]    The transistor  112  is controlled by a pre-charge control signal PRE to charge sub bit lines BLS and XBLS to a fourth potential (Vp 4 ) level.  
         [0111]    The control section  125  of FIG. 6 is configured so as to control the device according to a timing chart of FIG. 7.  
         [0112]    At time t 00 , the bit lines BL and XBL and sub bit lines BLS and XBLS are discharged to a ground potential Vss.  
         [0113]    From time t 00 , a BLDIS line is set at “L”, the pre-charge control signal PRE is set at “H”, and the sub bit lines BLS and XBLS are pre-charged to a fourth potential (Vp 4 ) via the transistor  112 .  
         [0114]    At time t 0 , a ferroelectric capacitor is selected while the pre-charge control signal PRE is set at the fourth potential (Vp 4 ), a word line WL is set at a third potential (Vp 3 ) level, and cell plate lines CP and RCP are set at “H”. When the ferroelectric capacitor is selected, the bit lines BL and XBL increase by ΔVa and ΔVb according to charge quantities Qa and Qb (FIG. 3) stored in a memory cell.  
         [0115]    At time t 1 , when an SSW line is set at a Vss level, transistors M 1  and M 2  increase in Vgs by Va and ΔVb as compared with the pre-charging of the bit lines. Thus, charging from the sub bit lines BLS and XBLS to the bit lines BL and XBL is started.  
         [0116]    At this moment, hysteresis positioned on A and B (FIG. 3) moves to C in response to the charging. Charges dQa and dQb (FIG. 3) are further read by the charging operation, thereby reading all the charges.  
         [0117]    Charge quantities used for this charging are expressed by (Qa+dQa) and (Qb+dQb), and the charging is started from a BLS pair. This charging operation reduces a potential of the BLS pair.  
         [0118]    The quantities of change are expressed by the equations below. 
         Δ Vas= ( Qa+dQa )/ Cbls    
         Δ Vbs= ( Qb+dQb )/ Cbls    
         [0119]    A reading potential difference is expressed by the equation below.  
               Δ                 V     =       (       Δ                 Vas     -     Δ                 Vbs       )     /   2                 =       (     Qa   -   Qb   +   dQa   -   dQb     )     /     (     2      XCbls     )                                   
 
         [0120]    A conventional reading potential difference is expressed by the equation below. 
         Δ VQ= ( Qa−Qb )/(2 XCb )  
         [0121]    Comparing the reading potential difference and the conventional potential difference, it is found that the former difference can be improved as expressed by the equation below.  
             η   =     Δ                   V   /   Δ                   Vo                 =       Cb   /   Cbls          {     1   +       (     dQa   -   dQb     )     /     (     Qa   -   Qb     )         }                                   
 
         [0122]    Thus, the reading operation can be stabilized. At time t 3 , a reading potential difference ΔV appearing on the sub bit lines is amplified by starting a sense amplifier while a sense amplifier control signal SEN is set at “H”.  
         [0123]    After time t 3 , the bit lines BL and BLS are charged to a power supply voltage Vdd.  
         [0124]    At time t 4 , “H” data is rewritten while cell plate lines CP and RCP are set at “L”. At time t 5 , the bit lines are discharged while the sense amplifier control signal SEN is set at “L”, the SSW line is set at Vss, and a BLDIS line is set at “H”, and word lines WL and RWL are set at “L”. The reading operation is completed thus.  
         [0125]    In this configuration, since pre-charging of the bit lines is not necessary, the power consumption can be reduced by a charge quantity of Cb 1 *Vp 1  as compared with (Embodiment 1). Further, time for pre-charging the bit lines with large capacities is not necessary, thereby increasing the speed.  
         [0126]    Besides, the following configuration is also applicable: a bit-line charge circuit ( 111 ) is a clamping circuit having a bit line potential (SSW) as input, and a first potential (Vp 1 ) is set lower than a ground potential (Vss).  
         [0127]    (Embodiment 4)  
         [0128]    [0128]FIG. 8 shows a ferroelectric storage device according to (Embodiment 4) of the present invention. Those members having the same operations as those of (Embodiment 1) are indicated by the same reference numerals in the explanation below.  
         [0129]    In (Embodiment 4), a transfer gate  111  is constituted by N-type transistors M 1  and M 2  and clamping circuits composed of NAND gates  127  and  128  of CMOS. The configuration of a control section  126  is identical to the control section  123  (Embodiment 1) except for a level of SSW.  
         [0130]    A transistor  112  is controlled by a pre-charge control signal PRE and charges sub bit lines BLS and XBLS to a Vdd level.  
         [0131]    The reading operation sequence is the same as that of (Embodiment 1) but is different from (Embodiment 1) in that the activating level of the SSW line is not a second potential (Vp 2 ) but Vdd of a logic “H” level.  
         [0132]    In the reading operation of (Embodiment 1), time for charging the bit lines is long in time t 1  and time t 2  of FIG. 2 because the transistors M 1  and M 2  of FIG. 1 are operated by a source follower. In contrast, in (Embodiment 4), bit lines are charged by the clamping circuits, each having bit line potential as input, thereby increasing the speed.  
         [0133]    In the present embodiment, the clamping circuits are CMOS circuits of N-type MOS and P-type MOS. The formats of the clamping circuits are not limited and may be all NMOS circuits.  
         [0134]    Further, as to (Embodiment 3) as well, the clamping circuit may be used instead of the transfer gate  111 .  
         [0135]    (Embodiment 5)  
         [0136]    [0136]FIG. 9 shows a ferroelectric storage device according to (Embodiment 5) of the present invention. Those members having the same operations as those of (Embodiment 1) are indicated by the same reference numerals in the explanation below.  
         [0137]    In FIG. 9, a bit line load capacitor  922  is added to (Embodiment 1) and is composed of a gate oxidation film capacitor of NMOS. The configuration of a control section  129  is identical to that of the control section  123  of (Embodiment 1).  
         [0138]    In (Embodiment  1 ), the quantities of change in pit line potential in a reading operation are expressed by the equations below. 
         Δ Vas= ( Qa+dQa )/ Cbls    
         Δ Vbs= ( Qb+dQb )/ Cbls    
         [0139]    When ΔVas and ΔVbs are larger than (Vp 1 −Vp 2 ), it becomes difficult to perform desired amplification. Although any problems do not occur by sufficiently increasing a first potential (Vp 1 ), the potential is limited due to restriction on a process. In contrast, in (Embodiment 5), the above problem can be solved by providing the sub bit lines with a capacitive load, and a change in potential of the bit line can be controlled as expressed by the equations below.  
         Δ Vas= ( Qa+dQa )/( Cbls+Cbln )  
         Δ Vbs= ( Qb+dQb )/( Cbls+Cbln )  
         [0140]    And then, Cbln is preferably set so as to satisfy one of the following equations.  
         [0141]    ΔVas&lt;(Vp2−Vp1+sense amplifier input sensitivity)  
         [0142]    ΔVbs&lt;(Vp2−Vp1+sense amplifier input sensitivity)  
         [0143]    (Embodiment 6)  
         [0144]    [0144]FIG. 10 shows a ferroelectric storage device according to (Embodiment 6) of the present invention. Those members having the same operations as those of (Embodiment 1) are indicated by the same reference numerals in the explanation below.  
         [0145]    [0145]FIG. 10 is different from (Embodiment 1) in that the transfer gate  111  of FIG. 1 is replaced with a CMOS transfer gate  1011 , and sub bit lines BLS and. XBLS are selectively connected to an adjacent memory cell array  1016  via a similar transfer gate  1015 . The transfer gate  1015  is controlled by SSWB. A control section  130  is substantially identical in configuration to the control section  123  of (Embodiment 1), an XSSW line is always set at a third potential (Vp 3 ), an SSWB line is always set at “L” level, an XSSWB line is set at “L” level from time t 00  to time t 3  and is set at the third potential (Vp 3 ) in other times.  
         [0146]    With this configuration, a parasitic bit line capacity  1022  of the adjacent memory cell array can be used instead of the bit line load capacity  922  required in (Embodiment 5), thereby reducing the area.  
         [0147]    (Embodiment 7)  
         [0148]    [0148]FIG. 11 shows a ferroelectric storage device according to (Embodiment 7) of the present invention. Those members having the same operations as those of (Embodiment 5) are indicated by the same reference numerals in the explanation below.  
         [0149]    In FIG. 11, a sub bit line capacitive load  1122  composed of n capacities of Cbln 0  to Cblnn is provided instead of the bit line capacitive load  922  of FIG. 9, and a ferroelectric deterioration detecting circuit  1123  is provided. The ferroelectric deterioration detecting circuit  1123  monitors a ferroelectric memory cell  105  other than a selected memory cell  105  to measure deterioration of the ferroelectric capacitor  101  (a degree of deterioration of Pr in FIG. 3). A control section  131  is identical in configuration to the control section  123  of (Embodiment 1).  
         [0150]    In (Embodiment 5), capacitors are added to the sub bit lines for optimization of the reading operation. Since (Qa+dQa) and (Qb+dQb) are reduced by deterioration of the ferroelectric, a sub bit line capacitance which is optimally set in the initial state deviates, from an optimum value after deterioration of the ferroelectric. In order to solve the problem, the present embodiment is configured such that a sub bit line capacitors can be selectively applied in response to control signals CAP 0  to CAPn. The signals CAP 0  to CAPn are controlled by a ferroelectric deterioration judging circuit  1023 , which is additionally provided, to always set a sub bit line capacitance at an optimum value.  
         [0151]    (Embodiment 8)  
         [0152]    [0152]FIG. 12 shows a ferroelectric storage device according to (Embodiment 8) of the present invention. (Embodiment 8) is configured such that connections between the bit line capacitive loads and the sub bit lines BLS and XBLS of (Embodiment 7) are separately controlled. A control section  132  is identical in configuration to the control section  131  of (Embodiment 1).  
         [0153]    Reference numerals CAP 0  to CAPn denote capacitive load control lines for a sub bit line BLS, and reference numerals CAP 0 b to CAPnb denote capacitive load control lines for a sub bit line XBLS. A ferroelectric deterioration detecting circuit  1223  of (Embodiment 8) is configured so as to set CAPn and CAPnb when deterioration of the ferroelectric is detected and screening is carried out.  
         [0154]    During a test and so on of the ferroelectric storage device, when screening is carried out on a ferroelectric capacitor with a small reading margin, it is possible to add an offset to a reading potential by separately controlling CAP 0  to CAPn and CAP 0 b to CAPnb, thereby detecting a ferroelectric capacitor not reaching a desired operating margin.  
         [0155]    The above explanation specifically discussed the embodiments of the present invention. However, the present invention is not limited to the above embodiments. For example, although the ferroelectric storage device with a 1T1C configuration was discussed in the above example, the present invention is applicable to a ferroelectric storage device with a 2T2C configuration. In that case, the reference capacitor is replaced with a ferroelectric capacitor, complementary data is written in the two ferroelectric capacitors, the RWL line is commonly used with the word line WL, and RCP is commonly used with the cell plate line CP.  
         [0156]    As described above, according to the present invention, the maximum polarization charge stored in writing can be retrieved in the reading operation, thereby remarkably increasing a margin of the reading operation. Additionally, the operation can be performed with stability even at a low voltage.