Abstract:
A method and system performs automatic deskew tuning and alignment across high-speed, parallel interconnections in a high performance digital system to compensate for inter-bit skew. Rather than using a VDL, digital elements such as registers and multiplexers are used for performing the automatic deskew tuning and alignment procedure. The result is a simpler, more robust deskew system capable of operating over a wider range of input values with greater accuracy and over a broader range of temperatures. In addition, the method and apparatus performs a one to four unfolding of the signal on each interconnection. The system includes a deskew controller and a plurality deskew subsystems. The deskew controller computes the amount of delay needed to correct the skew on each interconnection and feeds a different (or appropriate) delay value to each deskew subsystem located at the receiving end of each interconnection.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     The subject matter of this application is related to the subject matter of U.S. Pat. No. 6,493,320, entitled “AUTOMATIC INITIALIZATION AND TUNING ACROSS A HIGH SPEED, PLESIOCHRONOUS, PARALLEL LINK” and is fully incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an automatic deskew system and method for use in high-speed, parallel interconnections for digital systems, including high performance microprocessor systems, memory systems, and input/output (“I/O”) systems. 
     2. Description of Background Art 
     As data communication speeds increase in high performance digital systems and as the length of signal lines, for example copper or optical cables or printed circuit board traces, connecting the components of such high performance digital systems increases, the skew of the data arrival time at the receiving end of each signal line for parallel interconnections becomes significant. The skew on each signal line results from differences in the characteristics and length of each cable, connector or printed circuits board trace. Moreover, the skew is aggravated by the high data transfer rates. 
     Conventional deskew circuits exist to solve the problem of inter-bit skew on high-speed, parallel interconnections; however, conventional deskew circuits typically make use of an analog, device called a variable delay line (“VDL”). A VDL adds an amount of delay to a one bit skewed data input so as to align such one bit data input with other data input bits on parallel signal lines. 
     Conventional VDLs have numerous problems. First, it is difficult and expensive to make a VDL that can operate over a wide range of inputs and with a high degree of accuracy. The wider the range of operation and the better the accuracy of the VDL, the greater the number of delay elements, typically buffers, required. These buffers occupy space and increase overall chip size and pin connections and are, therefore, expensive. 
     Second, it is difficult to create a VDL with linear behavior. Linearity in a VDL is a desirable characteristic. If, for example, a VDL produces a two microsecond delay for an input value of one and a four microsecond delay given input value two, the VDL should produce a six microsecond delay given an input value of three. If instead the VDL produced a ten microsecond delay given input value of three, then the wrong amount of delay would be added to the skewed input data line and misalignment among the parallel input data lines would result. 
     Third, VDLs are not temperature-stable. For example, a VDL operating in low temperature conditions may output a delay of two microseconds given a certain input and a delay of three microseconds given the same input if operating in high temperature conditions. Thus, if a conventional deskew circuit containing a VDL is placed in a temperature variable environment, the performance of the VDL is unreliable. As a result, an incorrect amount of delay gets added to the one bit skewed input, resulting in misalignment of signals on parallel lines. 
     In addition to adding delay to correct for skew on parallel data input lines, conventional deskew circuits may also perform the task of “unfolding”. Specifically, in the case of a one to four unfolding circuit, four consecutive bits of a data signal are converted to an output signal of four bits width, one bit per output and each output bit having a rate one fourth that of the input. A purpose for slowing the rate of the input and unfolding is to make the design of the core logic circuit in the digital system easier. Generally the core logic circuit in such a system is quite complicated, thus a slower operation frequency facilitates design. Conventional deskew circuits typically perform the tasks of adding delay and unfolding sequentially. 
     Given the foregoing, there is a need for an automatic deskew system for use in high-speed, parallel interconnections for digital systems that: (i) operates over a wide range of inputs with accuracy; (ii) is suitable in temperature-variable environments; and (iii) performs unfolding. 
     SUMMARY OF THE INVENTION 
     The present invention includes a system and method for performing automatic deskew tuning and alignment across high-speed, parallel interconnections in a high performance digital system to compensate for inter-bit skew. Rather than using a VDL, the present invention includes digital elements, such as registers and multiplexers, which result in a simpler, more robust system capable of operating over a wider range of input values with greater accuracy and over a broader range of temperatures. In addition, the present invention performs a one to four unfolding of the signal on each interconnection. 
     A system in accordance with the present invention may include a deskew controller and a plurality deskew subsystems. The deskew controller computes the amount of delay needed to correct the skew on each interconnection and feeds a different (or appropriate) delay value to each deskew subsystem located at the receiving end of each interconnection. 
     Each deskew subsystem includes a clock recovery subsystem, a retiming subsystem and two coarse deskew subsystems. The clock recovery subsystem corrects skew that is less than the period of time for the transmission of one bit of information on an interconnection (“one bit time” or “T”). 
     The retiming subsystem and the coarse deskew subsystem collectively correct for any remaining skew by adding delay in integer multiples of one bit time, T, from 0T to 7T. The retiming subsystem and the coarse deskew subsystems collectively perform a one to four unfolding of the input signal. 
     The final output of the automatic deskew system is a one to four unfolding of each data input signal line and an alignment of all data on parallel interconnections in the digital system. 
     The features and advantages described in the specification are not all inclusive and, in particular, many additional features and advantages will be apparent to one of ordinary skill in the art in view of the drawings, specification, and claims. Moreover, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes, and may not have been selected to delineate or circumscribe the inventive subject matter. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of an automatic deskew system in accordance with an embodiment of the present invention. 
     FIG. 2 illustrates a timing diagram for an automatic deskew system in accordance with the present invention. 
     FIG. 3 is a block diagram of a retiming/deskew subsystem in accordance with the present invention. 
     FIG. 4 is a schematic diagram of an embodiment of the retiming subsystem in accordance with the present invention. 
     FIG. 5 illustrates an input/output table for the multiplexer contained in an embodiment of the retiming subsystem. 
     FIG. 6 illustrates the timing diagrams for the retiming subsystem. 
     FIG. 7 is a schematic diagram of an embodiment of a coarse deskew subsystem in accordance with the present invention. 
     FIG. 8 illustrates an input/output table for the multiplexer contained in an embodiment of the coarse deskew subsystem. 
     FIG. 9 illustrates the timing diagram for the coarse deskew subsystem. 
     FIG. 10A is a block diagram of a deskew controller in accordance with an embodiment of the present invention. 
     FIG. 10B is a block diagram of a controller for computing delays between or among each parallel input interconnection. 
     FIG. 11 is a flow diagram illustrating one method of operation of the present invention for a single deskew subsystem. 
     FIG. 12 is a flow diagram illustrating one method of operation of the retiming subsystem. 
     FIG. 13 is a flow diagram illustrating one method of operation of the coarse deskew subsystem. 
     FIG. 14 is a flow diagram illustrating one method of operation of the deskew controller. 
     FIG. 15 is a flow diagram illustrating one method of operation of phase one of the deskew controller. 
     FIG. 16 is a flow diagram illustrating one method of operation of phase two of the deskew controller. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A preferred embodiment of the present invention is now described with reference to the figures where like reference numbers indicate identical or functionally similar elements. Also in the figures, the left most digits of each reference number corresponds to the figure in which the reference number is first used. The present invention relates to a system and a method for automatic deskew for use in high-speed, parallel interconnections for digital systems. 
     FIG. 1 is a block diagram of an automatic deskew system  100  for use in high-speed, parallel interconnections for digital systems in accordance with one embodiment of the present invention. The digital system may be, for example, a high performance microprocessor, memory system or router chip. 
     The automatic deskew system  100  includes a plurality of deskew subsystems  192  and  180 , and a deskew controller  135 . One deskew subsystem resides at the receiving end of each parallel interconnection. In accordance with the present invention, the automatic deskew system has at least two deskew subsystems, but the precise number of such deskew subsystems varies depending upon the number of parallel interconnections in the digital system. 
     A deskew subsystem has a single bit input  145   a  which receives a skewed signal and a four bit output  160   a - 160   d , and is coupled to the deskew controller  135 . The signal on input  145   a  carries one bit of information every one bit time, T. “One bit time” or “T” is defined as 1/N seconds where N is the number of bits of information transmitted on an interconnection in one second. The signals on the four bit output  160   a - 160   d  are corrected for skew and unfolded. In other words, each output is properly aligned with the other output signals and the rate of each output has been reduced by a factor of four relative to the input  145   a.    
     FIG. 2 illustrates the timing diagram of the input and output values of a deskew subsystem and the automatic deskew system as a whole. The timing diagram for the data arriving on input line  145   a  is shown in  200  and for the data arriving on input line  145   b  is shown in  210 . As shown in FIG. 2, the data  200  arriving on input line  145   b  is delayed by approximately 5T relative to the data  210  arriving on input line  145   a . The difference in arrival time represents the skew between input lines  145   a  and  145   b . The automatic deskew system  100  corrects for the skew so that  205   a - 205   d  is aligned with  215   a - 215   d  and unfolds the signals  200  and  210  on input lines  145   a  and  145   b , respectively, so that the rate of the output signals is decreased by four. 
     As illustrated in FIG. 1, the deskew subsystem  192 , includes a clock recovery subsystem  105 , and a retiming/deskew subsystem  110 . Similarly, the deskew subsystem  180  includes a clock recovery subsytem  190  and a retiming/deskew subsystem  191 . A clock recovery subsystem corrects for skew which is less than one bit time, e.g., 0.5T. The clock recovery subsystem is further described in U.S. Pat. No. 6,247,138, and which is hereby incorporated by reference. 
     FIG. 3 illustrates a block diagram of an embodiment of a retiming/deskew subsystem in accordance with the present invention. A retiming/deskew subsystem  110  includes a retiming subsystem  305  and two coarse deskew subsystems  310  and  315 . The retiming/deskew subsystem  110  is coupled to the clock recovery subsystem  105  and a deskew controller  135 . Based upon delay control values  320 ,  325  and  330  computed by the deskew controller  135 , the retiming/deskew subsystem provides an integer multiple of one bit time delay up to seven bit time delay, i.e., 0T, 1T, 2T, 3T, 4T, 5T, 6T or 7T, to input signals  345   a  and  345   b  so that the clock recovery subsystem  105  and the associated deskew subsystem  110  collectively correct for any skew on input line  145   a . The deskew subsystem  192  (FIG. 1) also performs a one to four unfolding of such signal at its outputs  160   a - 160   d.    
     The timing diagrams shown in  205   a - 205   d  and  215   a - 215   d  illustrate the outputs of the automatic deskew system, which outputs have corrected for skew on lines  145   a  and  145   b , respectively. 
     As illustrated in FIG. 3, a retiming subsystem  305  comprises two inputs  345   a  and  345   b , an add delay input for receiving the delay control value  320 , and two outputs  350   a  and  350   b . A coarse deskew subsystem  310  has one input  350   a , two delay control inputs for receiving delay control values (bits)  325  and  330 , and two outputs  355   a  and  355   b . Each output of the retiming subsystem  305  is coupled to an input of a coarse deskew subsystem. The retiming subsystem  305  delays the signal on inputs  345   a  and  345   b  by 0T or 1T, depending on the value of the add delay input  320 , and performs a one to two unfolding of the signal on inputs  345   a  and  345   b.    
     FIG. 4 illustrates an embodiment of the retiming subsystem  305 . As shown in FIG. 4, the retiming subsystem  305  includes registers  410 ,  415 ,  425  and  430  and a multiplexer  420 . The registers are coupled so that the outputs of such registers perform a one to two unfolding of the two inputs  345   a  and  345   b , with 0T or 1T delay. 
     FIG. 6 illustrates a timing diagram for the retiming subsystem  305 . Input signal  600  transmits one bit of information every one bit time, T, wherein the input signal  600  is received via line  145   a  (FIG.  1 ). The timing diagrams of the unfolded outputs of registers  410 ,  415  and  430  are shown in  635 ,  645  and  650 , respectively. The signals shown in  645  are delayed by two bit times, 2T, relative to the signal shown in  635 . 
     The multiplexer  420  shown in FIG. 4 has three inputs  455 ,  465  and  470 , an input for receiving the one bit add delay control  320 , and two outputs  350   a  and  350   b . The multiplexer  420  is coupled to the outputs of registers  410 ,  415  and  430 . As shown in FIGS. 4 and 5, based upon the value of the add delay control value  320 , which is received from and computed by the deskew controller  135  (FIG.  1 ), the multiplexer  420  selects two consecutive bits of the delayed and unfolded outputs from registers  410 ,  415 , and  430 . The only difference between the two possible outputs of the multiplexer  420  is a delay of 0T or 1T. In short, the retiming subsystem  305  is capable of delaying a signal by 0T or 1T, and performing a one to two unfold of the input signal. 
     FIG. 7 illustrates an embodiment of the coarse deskew subsystem  310 . The coarse deskew subsystem  310  includes registers  705 ,  710 ,  715 ,  720 ,  725  and  730  and a multiplexer  735 . The registers are coupled so that the outputs of such registers perform a one to two unfolding of input  350   a , with delay of 0T, 2T, 4T or 6T, depending on the delay control values  325  and  330  from deskew controller  135 . 
     FIG. 9 illustrates the timing diagram for the coarse deskew subsystem  310 . Input signal  900  delivers one bit of information every two bit time, 2T wherein the input signal  900  is received via line  350   a . The timing diagrams of the unfolded outputs of registers  705 ,  715 ,  720 ,  725  and  730  are shown in  915 ,  925 ,  930 ,  935  and  940  respectively. The signal shown in  935  is delayed by eight bit time, 8T, relative to signal  915  and four bit time, 4T, relative to signal  925 . Signal  940  is delayed by four bit time, 4T, relative to signal  930 . 
     The multiplexer  735  shown in FIG. 7 has five inputs  770 ,  780 ,  790 ,  785  and  795 , an input for receiving the two bit delay control values  325  and  330 , and two outputs  355   a  and  355   b . The multiplexer  735  is coupled to the outputs of registers  705 ,  715 ,  720 ,  725  and  730 . As shown in FIGS. 7 and 8, based upon the values of the delay control bits  325  and  330 , which are computed by the deskew controller  135 , the multiplexer  735  selects two consecutive bits of the unfolded output. The only difference among the four possible outputs of the multiplexer  735  is a delay of 0T, 2T, 4T or 6T. 
     In short, the retiming/deskew subsystem  110  (including the two coarse deskew subsystems  310  and  315  coupled to the output of the retiming subsystem  305 ) is capable of delaying an input signal by 0T, 1T, 2T, 3T, 4T, 5T, 6T or 7T, and performing a one to four unfold of the input signals  345   a  and  345   b , with each of the four output bits  355   a - 355   d  in alignment and having a transmission rate one-fourth that of the input signal  145   a.    
     Each retiming/deskew subsystem  110  and  191  is coupled to the deskew controller  135 . The deskew controller  135  computes a three bit delay value for each interconnection. As shown in CHART 1 below, the least significant bit (LSB) from deskew controller is fed as a retiming add-delay bit  320  into the retiming subsystem  305 , while the most significant two bits (MSB 1  and MSB 2 ) are fed as coarse deskew add-delay bits  325  and  330  into coarse deskew subsystems  310  and  315 . The amount of added delay based on the values of the bits MSB 1 , MSB 2  and LSB are shown in the third column of CHART 1 below. 
     
       
         
               
             
               
               
               
               
               
             
           
               
                 CHART 1 
               
             
             
               
                   
               
               
                 delay control from deskew controller 135 
               
             
          
           
               
                   
                 MSB1 
                 MSB2 
                 LSB 
                 amount of 
               
               
                   
                 (bit 325) 
                 (bit 330) 
                 (bit 320) 
                 added delay 
               
               
                   
                   
               
               
                   
                 0 
                 0 
                 0 
                 0 T 
               
               
                   
                 0 
                 0 
                 1 
                 1 T 
               
               
                   
                 0 
                 1 
                 0 
                 2 T 
               
               
                   
                 0 
                 1 
                 1 
                 3 T 
               
               
                   
                 1 
                 0 
                 0 
                 4 T 
               
               
                   
                 1 
                 0 
                 1 
                 5 T 
               
               
                   
                 1 
                 1 
                 0 
                 6 T 
               
               
                   
                 1 
                 1 
                 1 
                 7 T 
               
               
                   
                   
               
             
          
         
       
     
     These delay values  320 ,  325  and  330  are unique to each interconnection and permit the retiming/deskew subsystem  110  to compensate differing skew on each parallel interconnection so as to align the outputs on each parallel interconnection. 
     FIG. 10A illustrates a functional block diagram of the deskew controller  135 . The deskew controller  135  includes a selector  1000 , a controller  1035 , four detectors  1015 ,  1020 ,  1025  and  1030 , and a plurality of registers  1050  and  1055 , the number of registers depends upon the number of parallel interconnections. 
     The deskew controller  135  is enabled by an enable signal  1085  from any suitable control unit. One suitable control unit is disclosed in U.S. Pat. No. 6,439,320, entitled “Automatic Initialization and Tuning Across a High Speed, Plesiochronous, Parallel Link,” and which is hereby incorporated by reference. 
     A selector  1000  receives the outputs of the deskew subsystems  192  and  180  in the digital system. As illustrated in FIG. 10A, outputs  160   a - 160   d  of deskew subsystem  192  associated with input  145   a  and outputs  165   a - 165   d  of deskew subsystem  180  associated with input  145   b  feed into selector  1000 . The selector  1000  selects the outputs of one of the deskew subsystems based upon an input  1040  from the controller  1035 . 
     The outputs  1070   a - 1070   d  of the selector  1000  are received by a detector  1015  which detects for all “1” values and a detector  1020  which detects for all “0” values. 
     The outputs  1075   a  and  1075   b  of detectors  1015  and  1020 , respectively, are input into the controller  1035  so that the controller can compute the delay on the interconnection associated with the deskew subsystem selected. 
     Detectors  1025  and  1030  receive inputs directly from the outputs of each deskew subsystem, e.g.,  192  and  180 , in the digital system. Detector  1025  detects for all “1” values, and detector  1030  detects for all “0” values. The outputs  1080   a  and  1080   b  of detectors  1025  and  1030 , respectively, are input into the controller  1035  so that the controller  1035  can compute the delays between or among each parallel input interconnection  145   a  and  145   b  in the digital system. 
     The controller  1035 , based upon outputs  1075   a ,  1075   b ,  1080   a  and  1080   b  from detectors  1015 ,  1020 ,  1025 , and  1030 , respectively, determines the three bit delay value for each input interconnection needed to compensate for skew and to align the outputs on each parallel interconnection. These three bit delay values computed by the controller  1035  are fed into registers  1050  and  1055 , and the registers  1050  and  1055  are coupled to the deskew subsystems  192  and  180  respectively. In short, there is one three bit delay value for each register and one register for each interconnection. 
     More particularly, the least significant bit  1090   c  of the output register  1050  is coupled to the add delay input  320  of retiming subsytem  305  (FIG. 3) for input  145   a , while the higher two significant bits  1090   a  and  1090   b  of the output register  1050  are coupled to the delay control inputs  325  and  330  of the coarse deskew subsystems  310  and  315 , respectively, for input  145   a . Similarly, the least significant bit  1095   c  of the output register  1055  is coupled to the add delay input  320  of retiming subsytem  305  (FIG. 3) for input  145   b , while the higher two significant bits  1095   a  and  1095   b  of the output register  1055  are coupled to the_delay control inputs  325  and  330  of the coarse deskew subsystems  310  and  315 , respectively, for input  145   b.    
     FIG. 10B is a functional block diagram of the controller  1035  in the deskew controller  135  of FIG.  10 A. The controller  1035  is enabled by a signal  1085  received from any suitable control unit. As discussed above, one such control unit is disclosed in U.S. Pat. No. 6,439,320, titled “Automatic Initialization and Tuning Across a High Speed, Plesiochronous, Parallel Link,” and which is hereby incorporated by reference. 
     A phase state register  1087  triggers a “Phase  1  start” signal in order to start the phase one tuning  1410  (FIG. 14) in response to receiving the deskew enable signal  1085  from any suitable control unit. The phase state register  1087  also generates a control signal  1089  for indicating a phase one tuning  1410  or phase two tuning  1415  procedure to a select stage  1091 . The select stage  1091  outputs the control signal  1040  to the selector  1000  (FIG. 10A) for the following purpose. In the phase one tuning procedure  1410  (FIG.  15 ), the input lines are selected by line select register  1093   a  (FIG. 10B) by use of selector  1000  (FIG.  10 A). 
     In the phase two tuning procedure  1415  (FIG.  16 ), the input lines are selected by line select register  1093   b  (FIG.  10 B). The select stage  1091  switches the source of the select value for selector  1000  (FIG. 10A) from registers  1093   a  or  1093   b  based on the signal  1089  from the phase state register  1087 . 
     A phase  1  state register  1088   a  receives the Phase  1  start signal and generates control signals  1092  for input into a line select register  1093   a . The line selector  1094   a  associates a delay value from the phase one state register  1088   a  with an interconnection whose value is stored in line select register  1093   a . In a preferred embodiment, line selector  1094   a  is a multiplexer whose control values are the outputs of line select register  1093   a.    
     The phase  1  state register  1088   a  also determines the values of the two least significant bits for providing the delay control bits  320  and  330  (see FIG.  3  and CHART 1). The least significant bit corresponds with bit  320  and the next least significant bit corresponds with bit  330 . The phase  1  state register  1088   a  makes the above value determination based upon the input signals  1075   a  and  1075   b  from detectors  1015  and  1020 , respectively (see FIG.  10 A). 
     When the phase one tuning  1410  is complete, the phase  1  state register generates a “Phase  1  complete” signal for input into phase state register  1087 , and in response the phase state register generates a “Phase  2  start” signal for starting the phase two tuning  1415 . A phase  2  state register  1088   b  generates control signals  1098  for input into a line select register  1093   b . The line selector  1094   b  associates a delay value from the phase two state register  1088   b  with an interconnection whose value is stored in line select register  1093   b . In a preferred embodiment, line selector  1094   b  is a multiplexer whose control values are the outputs of line select register  1093   b.    
     The line select register  1093   b  permits a line selector  1094   b  to_select one of the outputs of the deskew subsytems based upon a “select” signal from the line select register  1093   b . In a preferred embodiment, the line selector  1094   b  is a multiplexer. 
     The phase  2  state register  1088   b  also determines the values of the most significant bit for providing the delay control value  325  (see FIG.  3  and CHART 1). The phase  2  state register  1088   b  makes the above value determination based on the input signals  1075   a  and  1075   b  from detectors  1015  and  1020 , respectively (see FIG. 10A) and from input signal  1080   a  and  1080   b  from detectors  1025  and  1030 , respectively (see FIG.  10 A). 
     When the phase two tuning  1415  is complete, the phase  2  state register  1088   b  generates a “Phase  2  complete” signal for input into phase state register  1087 , and in response the phase state register generates a “complete” signal that indicates the completion of the deskew tuning procedure in accordance with he present invention. The “complete” signal may be generated to any suitable control unit, as mentioned above. 
     FIG. 11 illustrates a flow diagram of one embodiment of a method for automatically correcting skew on signals propagating on parallel interconnections in accordance with the present invention. At the start  1105  of the operation, which occurs upon receipt by the controller  1035  of an enabling signal  1085 , the deskew controller  135  commences deskew tuning  1115 . 
     During deskew tuning, the deskew controller  135  computes the appropriate delay values for each interconnection to correct for skew on each of the parallel interconnections. Skipping briefly to FIG. 14, one can see that deskew tuning for each interconnection includes the steps of receiving a known deskew initializing pattern  1405  and performing phase one tuning  1410  and phase two tuning  1415 . In one embodiment, the deskew initializing pattern is 1111 1111 0000. 
     In essence, phase one tuning  1410  involves determining the amount of skew on each individual interconnection and aligning each of the four outputs of a deskew subsystem, and phase two tuning  1415  involves determining the amount of delay to add to each interconnection to correct for differing amounts of skew between or among the parallel interconnections in the digital system. In order to perform phase one tuning and phase two tuning, detectors  1015 ,  1020 ,  1025  and  1030  search for the known deskew initializing pattern. Based upon the amount of skew observed, the automatic deskew system  100  will frame bits of information on each interconnection (i.e., add delay to the signal on each interconnection) so all outputs are in alignment. 
     FIG. 15 illustrates a flow diagram of one embodiment of a method for phase one tuning  1410 . During phase one tuning, selector  1000  selects  1505  the outputs  160   a - 160   d  or  165   a - 165   d  of one of the interconnections  145   a  or  145   b , respectively, in the digital system. The deskew controller  135  then uses detector  1015  to determine whether the outputs  1070   a - 1070   d  of the selected input line have all “1” values  1510 . If the outputs  1070   a - 1070   d  do not have all “1” values, the controller  1035  keeps waiting  1510  for all “1” values from detector  1015 . If, however, the outputs  1070   a - 1070   d  of the selected line have all “1” values, the deskew controller  135  then determines  1515  using detector  1015  whether the outputs  1070   a - 1070   d  of the next bit of information transmitted over the selected interconnection have all “1” values. 
     If the outputs  1070   a - 1070   d  do, the controller  1035  keeps waiting for the “not all values are 1” condition. In other words, the controller  1035  keeps waiting until the output signal from detector  1015  disappears. If, however, the outputs  1070   a - 1070   d  do not have all “1” values, the deskew controller  135  determines  1520  using detector  1020  whether the outputs  1070   a - 1070   d  of the next bit of information transmitted over the selected interconnection have all “0” values. 
     If the outputs  1070   a - 1070   d  do not, the delay control value gets incremented  1525  by one (i.e., if the current delay value on the selected interconnection is 0T, then the current delay value becomes 1T, or, if the current delay value is 1T, then the current delay value becomes 2T, and so forth). The deskew controller  135  then repeats steps  1510 ,  1515  and  1520  for the delayed signal. If, however, the outputs  1070   a - 1070   d  do have all “0” values, the tuning for the selected interconnection is complete and the selector  1000  selects  1530  the next interconnection  1530  and repeats the procedures in  1510 ,  1515 ,  1520 ,  1525 ,  1530  and  1535  until there are no more interconnections  1535  in the digital system, at which point the phase one tuning is complete  1540 . 
     FIG. 16 illustrates the flow diagram of one embodiment of phase two tuning  1415 . At the start  1600  of the phase two tuning, the selector  100  selects  1602  the outputs  160   a - 160   d  or  165   a - 165   d  of interconnections  145   a  or  145   b , respectively. The deskew controller  135  uses detector  1025  to determine  1605  whether all outputs  160   a - 160   d  and  165   a - 165   d  of each deskew subsystem in the digital system have all “1” values. If all outputs  160   a - 160   d  and  165   a - 165   d  do not have all “1” values, the controller  1035  keeps waiting for all “1” detected from detector  1025  (as shown in step  1605 ). If, however, all outputs  160   a - 160   d  and  165   a - 165   d  of each deskew subsystem have all “1” values, the deskew controller  135  then determines  1610  using detector  1025  whether all outputs  160   a - 160   d  and  165   a - 165   d  of the next bit of information transmitted over the parallel interconnections have all “1” values. 
     If all outputs  160   a - 160   d  and  165   a - 165   d  do have all “1” values, the controller  1035  keeps waiting for a “not all values 1” condition. In other words, the controller  1035  keeps waiting until the output signal from detector  1025  disappears. If, however, all outputs  160   a - 160   d  and  165   a - 165   d  of each deskew subsystem do not have all “1” values, the deskew controller  135  then determines  1615  using detector  1030  whether all outputs  160   a - 160   d  and  165   a - 165   d  of the next bit of information transmitted over the parallel interconnections have all “0” values. 
     In step  1615 , if detector  1030  does not detect an “all zero” condition, then the controller  1035  looks at the outputs of detectors  1015  and  1020  (i.e., signal lines  1075   a  and  1075   b , respectively). In step  1620 , if a “0000” is detected by detector  1020 , then the most significant bit of the delay control three bits is set  1625  to “1”, which means that a 4T delay is added to the interconnection (e.g., a 0T delay value becomes a 4T delay value; a 1T delay value becomes a 5T delay value; a 2T delay value becomes a 6T delay value, a 3T delay value becomes a 7T delay value, and so forth). 
     If, in step  1620 , a “1111” is detected by detector  1015 , then the delay control is not changed since the interconnection (line) selected in step  1602  is already in alignment with the other parallel interconnections. The selector  1000  then selects  1630  the next interconnection, and steps  1605  to  1630  are repeated so as to align the next interconnection with all the other parallel interconnections. 
     If, in step  1615 , the detector  1030  detects all zeros (“0000 . . . 0”), then the phase two tuning is completed  1635 . 
     Returning to FIG. 11, one can see that after completion of the deskew tuning  1115 , the automatic deskew system  100  receives a one bit signal  1120  on input lines  145   a  and  145   b . The clock recovery subsystems  105  and  190  correct for any skew  1125  that is less than one bit time, T, on the parallel interconnections  145   a  and  145   b.    
     As shown in greater detail in FIG. 12, the retiming subsystem  305 : (i) adds delay  1210  to the signal of 0T or 1T, based upon the value of the one bit add delay  320  computed by the deskew controller  135 ; (ii) performs a one to two unfolding  1215  the signal; and (iii) selects  1220  two consecutive bits among the delayed and unfolded signal. 
     As shown in FIG. 13, the coarse deskew subsystem  110  and  191  then adds further delay  1310  to the signal received from the retiming subsystem  320  in the amount of 0T, 2T, 4T and 6T, based upon the value of the two bit delay control  325  and  330  computed by the deskew controller  135 . In addition, the coarse deskew controller  110  and  191  performs a one to two unfolding  1315  of the received signal and selects  1320  two consecutive bits among the delayed and unfolded signal. 
     Thus, the end result of the above method performed by the automatic deskew system is a four bit unfolding of the signal on each interconnection corrected for skew so that all outputs on all parallel interconnections in the digital system are in alignment and each output has a transmission rate one-fourth that of the corresponding input signal. 
     While the invention has been particularly shown and described with reference to a preferred embodiment and several alternate embodiments, it will be understood by persons skilled in the relevant art that various changes in form and details can be made therein without departing from the spirit and scope of the invention.