Abstract:
A method for dissipating heat on address electrode drive chips of plasma display panel (PDP) comprises the steps of connecting an external voltage pulse circuit to the address electrode drive chips for driving; enabling a control circuit to control a switching sequence of switches in both the external voltage pulse circuit and each address electrode drive chip; generating an external voltage level or zero volt in each address electrode drive chip and applying the same to each address electrode of the PDP; and totally transferring a switching loss in the switches of each address electrode drive chip during switching to the switches of the external voltage pulse circuit. The method can prevent heat caused by switches switching loss from accumulating on drive chips.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to plasma display panels (PDPs) and more particularly to an effective method for dissipating heat on address electrode drive chips of PDP.  
         BACKGROUND OF THE INVENTION  
         [0002]    A manufacturing process of a conventional alternating current discharge type plasma display panel (PDP)  10  is shown in FIG. 1. First, two different activation layers are formed on glass substrates  11  and  12  respectively. Then seal the peripheries of the glass substrates together. A mixed gas consisting of helium (He), neon (Ne), and xenon (Xe) (or argon (Ar)) having a predetermined mixing volume ratio is stored in a discharge space formed in between the glass substrates. A front plate  11  is defined as one that facing viewers. A plurality of parallel spaced transparent electrodes  111 , a plurality of parallel spaced bus electrodes  112 , a dielectric layer  113 , and a protective layer  114  are formed from the front plate  11  inwardly. From a corresponding rear plate  12  inwardly, a plurality of parallel spaced data electrodes  121 , a dielectric layer  124 , a plurality of parallel spaced ribs  122 , and a uniform phosphor layer  123  are formed. When a voltage is applied on electrodes  111 ,  112 , and  121 , dielectric layers  113  and  124  will discharge in discharge cell  13  formed by adjacent spaced ribs  122 . As a result, a ray having a desired color is emitted from phosphor layer  123 .  
           [0003]    Conventionally, in PDP  10  a plurality of parallel spaced transparent electrodes  111  are formed on inner surface of front plate  11  by sputtering and photolithography (or printing). Then a plurality of parallel spaced bus electrodes  112  are formed on the transparent electrodes  111  respectively by plating (or sputtering) and photolithography. The line impedance of the transparent electrodes  111  may be reduced by the provision of bus electrodes  112 . In the following description, two adjacent transparent electrodes  111  (including bus electrodes  112 ) on the front plate  11  are represented by X electrode and Y electrode respectively. A triple electrode is formed by X electrode, Y electrode and corresponding data electrode  121  on the rear plate  12 . When a voltage is applied on the triple electrode, dielectric layers  113  and  124  will discharge in discharge cell  13  formed by adjacent spaced ribs  122 . Hence, UV rays are emitted from the mixed gas stored therein. And in turn, phosphor layer  123  in discharge cell  13  is activated by the UV rays. As an end, a visible light is generated by red, green and blue phosphor layers, resulting in an image showing.  
           [0004]    Referring to FIG. 2, a cross-section and structure of a conventional alternating current type plasma display panel (PDP)  10  is shown. As shown, PDP  1  comprises an X electrode  2   1 , Y electrodes  3   1 - 3   1000 , address A electrodes  4   1 - 4   M , a display grid  5 , a barrier rib  6 , and Y electrode display lines  7   1 - 7   1000 . X electrode  2   1  and Y electrode  3   1 - 3   1000  are on the same horizontal level. Address electrodes  4   1 - 4   M  are perpendicular to X and Y electrodes respectively. Each of X and Y electrodes has its specific function. For example, X electrode  2   1  acts to write and maintain discharge. Y electrodes  3   1 - 3   1000  act to scan and maintain discharge. Address electrodes  4   1 - 4   M  act to address. By effecting a cooperation among above electrodes, it is possible to show an image on panel  1 .  
           [0005]    [0005]FIG. 3 is a schematic diagram of drive circuit of PDP  10 . The drive circuit comprises address electrode drive chips  5   1 - 5   5 , Y electrode drive chips  6   1 - 6   4 , a Y electrode drive circuit  7 , an X electrode drive circuit  8  and a control circuit  9 . Address electrode drive chips  5   1 - 5   5  receive control signal from control circuit  9  for driving address electrodes  4   1 - 4   M  in order to effect an addressing. Y electrode drive chips  6   1 - 6   4  receive control signal from control circuit  9  for driving individual display line of Y electrodes  3   1 - 3   1000  in order to scan and maintain discharge. Y electrode drive circuit  7  is controlled by control circuit  9  for controlling timing. Y electrode drive circuit  7  cooperates with Y electrode drive chips  6   1 - 6   4  for distinguishing scan/address cycle from discharge maintaining cycle. X electrode drive circuit  8  receives control signal from control circuit  9  for driving X electrode in order to effect a writing and a discharge maintaining of PDP. By effecting a control on address electrode drive chips  5   1 - 5   5 , Y electrode drive chips  6   1 - 6   4 , Y electrode drive circuit  7 , and X electrode drive circuit  8  and a cooperation among them, it is possible to drive the circuitry of panel  1  and show an image thereon.  
           [0006]    [0006]FIG. 4 is a circuit diagram of drive circuit of PDP. As shown, X electrode drive circuit  8  comprises a discharge maintaining circuit  81 , a writing circuit  82 , and an energy recovery circuit  83 . Circuit  82  acts to excite each display grid for emitting light and exciting particles. Discharge maintaining circuit  81  acts to cause each display grid having excited particles to emit light and accumulate particles to be excited in a next cycle. Energy recovery circuit  83  acts to reduce energy lost in circuit parasite elements for transferring energy stored in display grids to an external storage element. Thus the stored energy may be sent to display grids before a next cycle starts. With this, it is possible to recover more than 90% of energy consumed in circuit parasite element for future use. Y electrode drive circuit  7  comprises a scan circuit  71 , a discharge maintaining circuit  72 , and an energy recovery circuit  73 . Scan circuit  71  acts to write data to be displayed into panel sequentially during scanning cycle. Further, scan circuit  71  acts to divide Y electrode into selected display lines and unselected display lines so that address electrode may address correctly. Y electrode drive chip  6  cooperates with scan circuit  71  and discharge maintaining circuit  72  for sequentially activating respective circuits. Address electrode drive chip  5  acts to write data to be displayed into selected display lines on Y electrode through address electrode in order to update display data on address circuit.  
           [0007]    Address electrode drive chip  5  acts to provide an external voltage (Va) (or zero volt) to address electrode. Thus address electrode drive chip  5  must switch an internal switch (e.g., semiconductor circuit) in order to output such external voltage (Va) (or zero volt). In a typical address drive chip, there are at least 64 switches. When address electrode drive chip generates an external voltage (Va) (or zero volt) and output the same to PDP, such drive chip must sustain energy loss due to multiple switchings. Such loss mainly is switching loss in capacitive load caused by switching the switches. FIG. 5 is an equivalent circuit diagram of the address electrode drive chip. As shown, a first semiconductor circuit of switch is designated by S 1 . A second semiconductor circuit of switch is designated by S 2 . R 1  and R 2  are equivalent resistors of switches S 1  and S 2  respectively. Va is an external voltage source. C is capacitive load. In FIG. 6, switch S 1  is closed and switch S 2  is open. Hence, power consumed in resistor R 1  is P R1 =CVa 2 /2 and energy stored in capacitive load C is P C =CVa 2 /2. Further, in FIG. 7, switch S 1  is open and switch S 2  is closed. Hence, energy stored in capacitive load C (i.e., P C =CVa 2 /2) is fed to resistor R 2 . Thus the consumed energy in resistor R 2  is P R2 =CVa 2 /2 and switching loss in capacitive load C per discharge is P T =P R1 +P R1 =CVa 2 . For example, the switching loss is CVa 2 f if the discharge times per second is f. Moreover, a so-called “thousand-bird pattern” is formed on cells of PDP as shown in FIG. 8. At the instinct of switching in address electrode drive chip, address electrodes on PDP is about equivalent to the capacitive load on the drive chip. Hence, energy loss permissible in drive chip is CVa 2 f. Such loss in converted into heat in the drive chip. In the case that the discharge times per second f is extremely high, the energy loss in address electrode drive chip is increased accordingly. This may burn out the drive chip eventually. In response, an automatic power control (W-APC) is developed by PDP designers and manufacturers for solving above serious power consumption on address electrode drive chip while displaying “thousand-bird pattern”. The technique proposed by W-APC is to control the switch times of address electrode drive chip for reducing switching loss in drive chip and reducing power consumption of PDP accordingly. However, it may also degrade image quality shown on PDP (e.g., HDTV). Therefore, it is not practical.  
         SUMMARY OF THE INVENTION  
         [0008]    It is thus an object of the present invention to provide a method for dissipating heat on a plurality of address electrode drive chips of a plasma display panel (PDP). The method comprises the steps of: (a) connecting an external voltage pulse circuit to the address electrode drive chips for driving; (b) enabling a control circuit to control a switching sequence of a plurality of switches in both the external voltage pulse circuit and each of the address electrode drive chips; (c) generating an external voltage level or zero volt in each of the address electrode drive chips and applying the same to each of a plurality of address electrodes of the PDP; and (d) totally transferring a switching loss in the switches of each the address electrode drive chips during switching to the switches of the external voltage pulse circuit.  
           [0009]    In one aspect of the present invention, when an output voltage of each of the address electrode drive chips is the external voltage, in one timing cycle of the external voltage pulse circuit and each of the address electrode drive chips, comprising the steps of: (e) enabling the control circuit to switch the third switch of each of the address electrode drive chips to a closed state and the fourth switch thereof to an open state for preventing heat from generating because there is no switching loss in the third switch; (f) enabling the control circuit to switch the first switch to the closed state and forming a first current path by the external voltage, the first current path passing from the external voltage, the first switch, the third switch, the external capacitor, and the ground terminal to return to the external voltage, thereby totally transferring energy loss due to the switchings to the first switch; (g) enabling the control circuit to switch the first switch to the open state and the second switch to the closed state and forming a second current path by the external voltage, and the second current path passing from the ground terminal, the external capacitor, the third switch, and the second switch to return to the ground terminal wherein charges accumulated in the external capacitor due to charging by the external voltage is discharged to the ground terminal for reducing a voltage of the external capacitor to zero and totally transfers energy loss due to the switchings to the second switch; and (h) enabling the control circuit to switch the first, second, and third switches to the open state and the fourth switch to the closed state and forming a third current path by the external voltage, and the third current path passing from the ground terminal, the external capacitor, and the fourth switch to return to the ground terminal wherein there is no current on the third current path since the voltage on the external capacitor is zero in the step (g) and prevents heat from generating because there is no switching in both the third and fourth switches.  
           [0010]    In another aspect of the present invention, when the output voltage of each of the address electrode drive chips is zero, in the other timing cycle of the external voltage pulse circuit and each of the address electrode drive chips, comprising the steps of: (i) enabling the control circuit to switch the first and fourth switches to the closed state and the second and third switches to the open state and forming the third current path by the external voltage, and the third current path passing from the ground terminal, the external capacitor, and the fourth switch to return to the ground terminal wherein there is no output voltage since the voltage on the external capacitor is zero; (j) enabling the control circuit to switch the first switch to the open state and the second switch to the closed state and forming the third current path by the external voltage, and the third current path passing from the ground terminal, the external capacitor, the fourth switch, and the second switch to return to the ground terminal wherein there is no output voltage since the voltage on the external capacitor is zero; and (k) enabling the control circuit to switch the second switch to the open state and forming the third current path by the external voltage, and the third current path passing from the ground terminal, the external capacitor, the fourth switch, and the second switch to return to the ground terminal wherein there is no output voltage since the voltage on the external capacitor is zero.  
           [0011]    The above and other objects, features and advantages of the present invention will become apparent from the following detailed description taken with the accompanying drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]    [0012]FIG. 1 is a sectional view of a conventional alternating current type PDP;  
         [0013]    [0013]FIG. 2 is schematic diagram showing a structure of PDP in FIG. 1;  
         [0014]    [0014]FIG. 3 is schematic diagram of drive circuit of PDP in FIG. 1;  
         [0015]    [0015]FIG. 4 is a circuit diagram of drive circuit of PDP in FIG. 1;  
         [0016]    [0016]FIG. 5 schematically showing an equivalent circuit diagram of the address electrode drive chip;  
         [0017]    [0017]FIG. 6 is a circuit diagram showing switch S 1  closed and switch S 2  open of FIG. 5;  
         [0018]    [0018]FIG. 7 is a circuit diagram showing switch S 1  open and switch S 2  closed of FIG. 5;  
         [0019]    [0019]FIG. 8 is a top plan view of “thousand-bird pattern” formed on cells of PDP;  
         [0020]    [0020]FIG. 9 is a circuit diagram of an external voltage pulse circuit incorporated in a plurality of address electrode drive chips on plasma display panel according to the invention;  
         [0021]    [0021]FIG. 10 schematically shows an equivalent circuit diagram of address electrode drive chip of FIG. 9;  
         [0022]    [0022]FIG. 11 is a timing diagram of waveforms illustrating relationship of switches versus output voltage; and  
         [0023]    FIGS.  12  to  18  are circuit diagrams illustrating various on/off combinations of switches in operation. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0024]    [0024]FIG. 9 is a circuit diagram showing an external voltage pulse circuit  2  in parallel connection to a plurality of (three are shown) address electrode drive chips  121  of plasma display panel (PDP) according to the invention. With this configuration, it is possible to solve above overheating problem of address electrode drive chip when the discharge times is extremely high, prevent such drive chip from burning out, and maintain a good image quality. As shown, a control circuit (not shown) is utilized by the address electrode drive chips  121  to control a switching sequence of switches in both the external voltage pulse circuit  2  and address electrode drive chip  121 . Accordingly, an external voltage level (Va) (or zero volt) is generated in address electrode drive chip  121 . Such voltage is then applied to address electrodes of PDP. Hence, it is possible to totally transfer switching loss in switches of address electrode drive chip  121  during switching to switches of the external voltage pulse circuit  2 . This can prevent heat caused by above switching loss from accumulating on address electrode drive chip  121 . For illustrating the principles of the invention, FIG. 10 schematically shows an equivalent circuit diagram of an address electrode drive chip  121  driven by a single external voltage pulse circuit  2 . The operations and effect of FIG. 10 is as follows:  
         [0025]    [0025]FIG. 11 is a timing diagram of waveforms illustrating relationship of switches of the external voltage pulse circuit  2  and address electrode drive chip  121  versus output voltage Va of address electrode drive chip  121  of a preferred embodiment. In one cycle of five continuous output waveforms (e.g., S 1 , S 2 , S 3 , S 4  and V out ) following four steps are performed:  
         [0026]    (1) First referring to FIG. 12, a control circuit (not shown) is utilized to switch a third switch S 3  of address electrode drive chip  121  to a closed state and fourth switch S 4  of address electrode drive chip  121  to an open state for preventing heat from generating because there is no switching loss in third switch S 3 .  
         [0027]    (2) Then referring to FIG. 13, control circuit acts to switch a first switch S 1  to a closed state. At this time, a current path is formed by the external voltage Va, which is from external voltage Va and sequentially passes through the first switch S 1 , third switch S 3 , external capacitor  25  and ground terminal  26 , and returns back to the external voltage Va. As stated above, as “thousand-bird pattern” shown on PDP at the instinct of switching in address electrode drive chip  121 , address electrodes is about equivalent to the capacitive load on the drive chip. Such capacitive load is called external capacitor  25 . Voltage of external capacitor  25  is an external voltage applied on address electrode. At this cycle, energy loss due to switching switches is totally transferred to first switch S 1 . Hence, it is possible to prevent heat from generating because there is no switching loss in both third switch S 3  and fourth switch S 4  of address electrode drive chip  121 .  
         [0028]    (3) Then referring to FIG. 14, control circuit acts to switch a first switch S 1  to an open state and second switch S 2  to a closed state. At this time, a current path is formed by the external voltage Va, which is from ground terminal  26  and sequentially passes through external capacitor  25 , third switch S 3  and second switch S 2 , and returns back to ground terminal  26 . That is, charges accumulated in external capacitor  25  due to charging by external voltage Va are discharged to ground terminal  26 . Hence, voltage of external capacitor  25  is zero. At this cycle, energy loss due to switching switches is totally transferred to second switch S 2 . Hence, it is possible to prevent heat from generating because there is no switching loss in both third switch S 3  and fourth switch S 4  of address electrode drive chip  121 .  
         [0029]    (4) Finally referring to FIG. 15, control circuit acts to switch first switch S 1 , second switch S 2 , and third switch S 3  to an open state and fourth switch S 4  to a closed state. At this time, a current path is formed by external voltage Va, which is from ground terminal  26  and sequentially passes through external capacitor  25  and fourth switch S 4 , and returns back to ground terminal  26 . At this time, there is no current on the path since voltage on external capacitor  25  is zero in above step (3). Hence, it is possible to prevent heat from generating because there is no switching loss in both third switch S 3  and fourth switch S 4  of address electrode drive chip  121 .  
         [0030]    Referring to FIG. 11 again, in the embodiment in a next cycle of five continuous output waveforms (e.g., S 1 , S 2 , S 3 , S 4  and V out ) following three steps are performed:  
         [0031]    (1) First referring to FIG. 16, control circuit acts to switch a first switch S 1  and fourth switch S 4  to a closed state and second switch S 2  and third switch S 3  to an open state. At this time, a current path is formed by external voltage Va, which is from ground terminal  26  and sequentially passes through external capacitor  25  and fourth switch S 4 , and returns back to ground terminal  26 . At this time, there is no output voltage since voltage on external capacitor  25  is zero. Hence, it is possible to prevent heat from generating because there is no switching loss in fourth switch S 4  of address electrode drive chip  121 .  
         [0032]    (2) Then referring to FIG. 17, control circuit acts to switch first switch S 1  to an open state and second switch S 2  to a closed state. At this time, a current path same as that shown in FIG. 16 is formed by external voltage Va, which is from ground terminal  26  and sequentially passes through external capacitor  25  and fourth switch S 4 , and returns back to ground terminal  26 . At this time, there is no output voltage since voltage on external capacitor  25  is zero. Hence, it is possible to prevent heat from generating because there is no switching loss in fourth switch S 4  of address electrode drive chip  121 .  
         [0033]    (3) Finally referring to FIG. 18, control circuit acts to switch second switch S 2  to an open state. At this time, a current path same as that shown in FIG. 16 is formed by external voltage Va, which is from ground terminal  26  and sequentially passes through external capacitor  25  and fourth switch S 4 , and returns back to ground terminal  26 . At this time, there is no output voltage since voltage on external capacitor  25  is zero. Hence, it is possible to prevent heat from generating because there is no switching loss in fourth switch S 4  of address electrode drive chip  121 .  
         [0034]    In view of above, the invention utilizes a control circuit to control a switching sequence of switches in both the external voltage pulse circuit  2  and in address electrode drive chip  121 . Accordingly, power loss due to switching switches in address electrode drive chip  121  is totally transferred to switches in the external voltage pulse circuit  2 . Hence, it is possible to prevent heat caused by above switching loss in address electrode drive chip  121  from accumulating thereon by designing a simple economic effective circuitry. It is found that energy transferred from address electrode drive chip  121  to first and second switches S 1  and S 2  will accumulate thereon. Hence, first and second switches S 1  and S 2  will be overheated. The invention provides an additional heat dissipation pad on each of switches S 1  and S 2  for increasing heat dissipation capability thereof. This can effectively prevent switches S 1  and S 2 from burning due to overheating. While the invention has been described by means of specific embodiments, numerous modifications and variations could be made thereto by those skilled in the art without departing from the scope and spirit of the invention set forth in the claims.