Abstract:
The present invention provides an LOC package wherein the lead frame is in direct contact with the semiconductor device. The lead frame, which includes openings, is positioned directly on the semiconductor device. An adhesive material is applied in the opening in the lead frame. This adhesive material contacts both the lead frame and the semiconductor device. The lead frame is therefore securely held to the semiconductor device. Wires can then be bonded to contact pads on the semiconductor device and to the lead frame.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 of Korean Patent Application P2004-0019664 filed Mar. 23, 2004 and Korean Patent Application No. P2004-0093481 filed Nov. 16, 2004, the entire contents of which are hereby incorporated by reference.  
       FIELD OF THE INVENTION  
       [0002]     The present invention relates to packaging semiconductor devices and more particularly to packaging semiconductor devices using a lead frame.  
       BACKGROUND OF THE INVENTION  
       [0003]     There are a wide variety of packaging technologies that have been used for semiconductor devices. One of the widely used packaging technologies is termed Lead On Chip (LOC).  
         [0004]     In LOC packaging a lead frame is positioned near the semiconductor device and wires are then bonded to pads on the chip and to the lead frame. Generally the wires are bonded to pads on the chip and to the lead frame using ultrasonic wire bonding technology. After the lead frame is connected to the semiconductor device the entire assembly is encapsulated.  
         [0005]     In many LOC packages, the lead frame is connected to the chip with a layer of adhesive material. For example, see U.S. Patent Publication No. 2001/0016371. The layer of adhesive material between the lead frame and the chip creates various problems. For example, if pressure is applied to secure the adhesive material to the chip and to the frame, this can damage the semiconductor chip. Another potential problem is created by the fact that the layer of adhesive material separates the lead frame from the semiconductor chip. This separation can create a space into which packaging material can flow, causing potential failure sites.  
       SUMMARY OF THE PRESENT INVENTION  
       [0006]     The present invention provides an LOC package wherein the lead frame is in direct contact with the semiconductor device. The lead frame, which includes openings, is positioned directly on the semiconductor device. An adhesive material is applied in the opening in the lead frame. This adhesive material contacts both the lead frame and the semiconductor device. The lead frame is therefore securely held to the semiconductor device. Wires can then be bonded to contact pads on the semiconductor device and to the lead frame.  
         [0007]     In one embodiment of the invention, an ultra violet curable adhesive is used. After this adhesive material is applied, it is cured by the application of ultra violet light.  
         [0008]     The package can be assembled using a die that has a plurality of holes and the following procedure. First, semiconductor devices are placed in these holes. Next, lead frames are positioned on top of the semiconductor devices. An adhesive material is then applied, at least in the spaces between the leads in the lead frame. The adhesive material contacts both the lead frame and the surface of the semiconductor device. After the adhesive is cured it holds the lead frame securely to the semiconductor device. 
     
    
     BRIEF DESCRIPTION OF THE FIGURES  
       [0009]      FIG. 1A  shows a side view of a first embodiment of the invention.  
         [0010]      FIG. 1B  is a view taken along line I-I′ in  FIG. 1A .  
         [0011]      FIG. 1C  is a view of an alternate embodiment of the invention.  
         [0012]      FIG. 2  is a perspective view of a die that can be used to assemble the package.  
         [0013]      FIGS. 3A  to  3 D show how the device can be assembled.  
         [0014]      FIGS. 4A  to  4 H show more detail about the devices at various stages of the assembly process.  
         [0015]      FIG. 5A  is a top view of a first embodiment of the invention.  
         [0016]      FIG. 5B  is a more detailed top view.  
         [0017]      FIG. 6  is a top view of a second embodiment of the invention.  
         [0018]      FIGS. 7A, 7B  and  7 C are top views of two other embodiments of the invention.  
         [0019]      FIGS. 8A and 8B  are top views of still another embodiment of the present invention.  
         [0020]      FIGS. 9A and 9B  are top views of still another embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0021]     The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to convey the scope of the invention to those skilled in the art.  
         [0022]     It is noted that the figures are not drawn to scale. Rather, for simplicity and clarity of illustration, the dimensions of some of the elements are exaggerated for clarity. It is also noted that well-known structures and processes have not been described or illustrated to avoid obscuring the essence of the present invention.  
         [0023]      FIG. 1A  is a cross section view of a Lead-on-chip (LOC) semiconductor package that incorporates a first embodiment of the present invention.  FIG. 1B  is a cross section view taken along line I-I′ in  FIG. 1A .  
         [0024]     The LOC package shown in  FIGS. 1A and 1B  includes a semiconductor chip  21 , a lead frame  22 , and bonding wires  23 . The chip  21  has conventional bonding pads  21   a  and a conventional insulating layer L 1 . As is conventional, the insulating layer L 1  covers the surface of chip  21  except for the bonding pads  21   a . The insulating layer L 1  may be a passivation layer or a polyimide layer. The bonding wires  23  connect the bonding pads  21   a  (and thus the chip circuitry which is not shown in the drawings) to the lead frame  22 .  
         [0025]     The lead frame  22  includes inner leads  22   a , which extend toward the chip pads  21 . Adhesive material  24  mechanically connects and holds the inner leads  22   a  to the chip  21 . The adhesive  24  can extend over and around the lead frame elements as shown in  FIG. 1B , or the adhesive can be located only between the lead frame elements as shown in the alternate embodiment illustrated in  FIG. 1C .  
         [0026]     In the specific embodiments described herein, the adhesive  24  is a UV (that is UV light) curable adhesive such as the commercially available adhesive known as adhesive EW707 series marketed by Polysciences, Inc. of 400 Valley Road, Warrington, Pa. While the embodiments described herein use the particular adhesive named above, it should be understood that various other types of adhesive may also be used.  
         [0027]     It is specifically noted that the adhesive layer  24  binds the leads  22   a  to the chip  21 ; however, there is no adhesive under the lead frame  22 . That is, there is no adhesive between the leads  22   a  and the chip  21  and no space between the leads  22   a  and the chip  21 . Thus, the leads  22   a  and the lead frame  22  are in contact with the upper surface of the semiconductor chip  21 . Stated differently, there is no gap between the lead frame  22  and the chip  21 . The close proximity of the lead frame  22  to the chip  21  has a number of advantages including improved positional stability, reduced thickness of the package, and the elimination of a gap into which packaging material can flow. Furthermore the use of a UV curable adhesive eliminates damage due to thermal shock, which can result from the use of a heat curable adhesives.  
         [0028]     The specific embodiments illustrated in  FIGS. 1A, 1B  and IC related to semiconductor chips with center pads; however, the invention can be used with semiconductor chips having pads at various other locations on the chip.  
         [0029]     A particular technique for manufacturing the package shown in  FIGS. 1A, 1B  and  1 C will now be described. It should, however, be understood that various other manufacturing techniques may also be used.  
         [0030]      FIG. 2  shows a chip mounting jig  50 , which includes chip mounting groves  51  for receiving semiconductor chips. While the jig  50  has six holes for receiving chips, it should be understood that the number of holes in the jig is a matter of engineering choice and that the jig may include many more such holes. The jig  50  can, for example, be made from a conventional stainless steal (SUS) alloy.  
         [0031]      FIGS. 3A, 3B ,  3 C and  3 D show overall diagrams of steps in the process, and  FIGS. 4A  to  4 H show more detailed views of steps in the process.  FIG. 3D  shows more detail one of the chips and lead frames shown in  FIG. 3C . The area shown in  FIG. 3D  is indicated by the circle D in  FIG. 3C .  
         [0032]     The overall operation will first be explained with reference to  FIGS. 3A  to  3 D. First, semiconductor chips  21  are positioned in the chip mounting groves  51  of the jig  30 . This may be done by a conventional chip picking machine (not shown) which picks the chips from a chip tray (not shown) and moves them to the groves  51  in the jig  50 .  
         [0033]     Next, as illustrated in  FIG. 3B  (and in the more detailed  FIG. 3D ), a lead frame strip  60  is positioned on top of the jig  50 . The led frame strip  60  includes a plurality of lead frames  22 , as is conventional. The lead frame strip  60  is positioned so that the inner leads  22   a  are in a close relationship to the upper surface of the semiconductor chips  21 , that is, to the insulating layer L 1  shown in  FIGS. 1A, 1B  and IC.  
         [0034]     As indicated in  FIG. 3C , an UV adhesive  24  is applied onto the inner leads  22   a  and to the semiconductor chip  21  along a strip in the direction indicated by the arrow P in  FIG. 3C . The UV adhesive may surround the inner leads, as shown in  FIG. 1B , or the adhesive may be only positioned between the leads, as shown in the alternate embodiment illustrated in  FIG. 1C .  
         [0035]     A more detailed view of the various steps is illustrated in  FIGS. 4A  to  4 H. First, a wafer  10  is divided into chips  21 . The chips are placed in the jig  50  as illustrated in  FIG. 4B .  FIGS. 4C  to  4 H relate to the single chip area indicated by the circle  66  in  FIG. 4B .  FIG. 4C  illustrates the chip  21  in the jig  50 .  
         [0036]      FIG. 4D  shows the lead frame leads  22   a  positioned on top of the chip  21 . This is a more detailed illustration of what is shown in  FIG. 3B .  FIG. 4E  shows the adhesive  24  positioned on and around the leads  22   a , as illustrated in  FIG. 3C .  
         [0037]      FIG. 4F  illustrates UV radiation (illustrated by the arrows  19 ) being applied to the adhesive  245 .  FIG. 4G  illustrates the wires  23  connected to the chip pads and the lead frame. The wires are bonded in a conventional manner by a conventional wire bonding technique. Finally,  FIG. 4H  illustrates the chip encapsulated with material  26 . This encapsulation is performed in a conventional manner.  
         [0038]     An alternate embodiment of the invention includes an additional cure step, that is, a second, UV curing step. In one alternate embodiment, the second curing step is performed after the wire bonding step. This second curing step may prevent deformation of the inner leads  22   a  which can result from mechanical shock. The second curing step may also improve the bonding between the semiconductor chip  21  and the inner leads  22   a . The number of UV cure steps used, the intensity of the UV light and the duration of the UV cure steps are a function of the particular adhesive used. A sufficient amount of light must be used to adequately cure the particular adhesive selected for use in any particular application.  
         [0039]     Still another embodiment of the invention includes an oven cure step after the first UV cure step and before the wire bonding step. This oven cure step can be at a temperature that insures that the adhesive is completely cured. For example, the oven cure step may be an over cure at 170 degrees centigrade.  
         [0040]     It is noted that the wire bonding step may be performed in the same jig used to apply the lead frame, or the chips may be removed from the first jig prior to wire bonding and the wire bonding can be performed in a separate jig.  
         [0041]      FIG. 5A  is an overall top view of the lead frame  22  and the chip  21 .  FIG. 5A  illustrates the position of the adhesive  24  on the leads  22   a .  FIG. 5B  is a more detailed view of a portion of the lead frame  22  and the chip  21 , showing the leads  22   a , the chip pads  21   a  and the wires  33  connecting the chip pads  21   a  to the leads  22   a.    
         [0042]     An alternate embodiment of the invention is shown in  FIG. 6 .  FIG. 6  illustrates a lead frame  222 , chip pads  221   a , adhesive  224 , and wires  223  connecting the lead frame  222  to the chip pads  222 . The leads on lead frame  222  have two portions designated  222   a  and  222   c . In this alternate embodiment, the portion  222   a  is longer than in the previous embodiment in order to accommodate and make additional room for the adhesive strip  224 .  
         [0043]     Three additional embodiments of the invention are shown in  FIGS. 7A, 7B  and  7 C. The embodiment shown in  FIG. 7A  includes a lead frame  722  and two strips of UV curable adhesive  701  and  703 . The additional strips of UV adhesive  703  provides additional bonding. Strip  703  is positioned near the tips of the leads adjacent to the locations  702  to which wires are bonded. By positioning the adhesive near the ends of the leads, the chip is prevented from tilting. The additional strip of adhesive  703  can applied prior to the wire bonding step since strip  703  does not cover the sites  702  to which wires are later bonded. That is, the package shown in  FIG. 7A  can be fabricated in the following sequence of steps which occur after the lead frame has been placed over the chips: First adhesive  701  is applied and cured to bond the lead frame to the chips, then adhesive  703  is applied and cured to further bond the lead frame to the chips, and finally the wires are bonded to the lead frame and the chip. Alternatively, the adhesive strip  703  can be applied after the wires have been bonded to the lead frame and to the chip.  
         [0044]     Another embodiment of the invention is shown in  FIG. 7B . In the embodiment shown in  FIG. 7B , the UV curable adhesive strip  703 B covers the wire bonding sites on the lead frame. In this embodiment the fabrication sequence of steps after the lead frame is positioned on the chips is as follows: First adhesive  701  is applied and cured to hold the lead frame to the chip, next the wires are bonded to the chip and to the lead frame, and finally adhesive strip  703 B is applied and cured. In the embodiment shown in  FIG. 7B , the adhesive strip  703 B covers the sites to which the wires have been bonded, thereby providing additional support of the wires that extend from the lead frame to the chip pads.  
         [0045]     Another embodiment of the invention is shown in  FIG. 7C . In the embodiment shown in  FIG. 7C , the UV curable adhesive is applied at the locations indicated by the rectangles  711  to  714 ,  721 - 724 , and  731 - 734 . In this embodiment the fabrication sequence of steps after the lead frame is positioned on the chips is as follows: First adhesive is applied and cured in the four corner rectangles  711  to  714 . This holds the lead frame to the chip. Next the wires are bonded to the lead frames and to the chip. Finally, UV adhesive is applied and cured in the areas indicated by rectangles  721  to  724  and  731  to  734 . It is noted that rectangles  721  to  724  and  731  to  734  overlap the wire bonding sites on the lead frame. Thus, the UV adhesive at locations  721  to  724  and  731  to  734  help hold the wires in place. It is noted that parts and steps of the embodiments shown in  FIGS. 7A, 7B  and  7 C not specifically discussed above are identical to the corresponding elements and steps in the previously described embodiments.  
         [0046]     Still another embodiment of the invention is illustrated in  FIGS. 8A and 8B .  FIG. 8B  is an expanded view of the section designated by the circle  851  shown in  FIG. 8A . This embodiment includes a lead frame  822  that includes a protective tape  899  over the center portion of the lead frame  822 . As shown in  FIG. 8B , the protective tape  899  covers the end portions  924  of the leads on frame  822 . It is noted that the wires, such as wires  23  in  FIG. 1A , are bonded to the ends of the leads. Use of the protective tape as shown in  FIGS. 8A and 8B  prevents the lead ends from being contaminated when the UV adhesive is applied as previously described.  
         [0047]     Still another embodiment of the invention is illustrated in  FIGS. 9A and 9B . In the embodiment shown in  FIGS. 9A and 9B  a chip  921  is positioned on top of the lead frame  922  rather than under the lead frame, as in the previously described embodiments.  FIG. 9A  shows a lead frame  922  that has a central portion  951  on which an integrated circuit chip can be placed. The central portion  951  of the lead frame includes at least one hole.  
         [0048]      FIG. 9B  shows the chip  921  positioned on the lead frame  922 . As in the previous embodiments, the chip is in direct contact with the lead frame. Adhesive  924  is placed in the hole in the lead frame under the semiconductor chip. The adhesive contacts the lead frame and the semiconductor chip. Adhesive  924  holds the chip  921  to the lead frame  922 . Wires  923  connect pads on the chip  921  to the leads of the lead frame  922 .  
         [0049]     Thus in the embodiments shown in  FIGS. 9A and 9B , the leads are positioned directly on the bottom surface of said semiconductor chip. In contrast in the embodiments shown earlier, the leads are positioned directly on the top surface of said semiconductor chip.  
         [0050]     In still another embodiment of the invention a heat curable adhesive is used. With such an embodiment, sufficient heat is applied to cure the head curable adhesive. An adhesive need be selected which has a low enough cure temperature that the semiconductor chip is not damaged during the cure step.  
         [0051]     While the invention has been shown and described with respect to preferred embodiments thereof, it should be understood that various changes may be made in the described embodiments without departing from the spirit and scope of the invention. The scope of the invention is limited only by the appended claims.