Abstract:
A memory controller device coupled to a memory device equipment including a plurality of memory devices, includes a memory controller configured to instruct read-out of data in the memory device and a physical part configured to terminate a read-out signal for a certain period containing an arrival time of data read out from one memory device of the memory device equipment in accordance with a read-out instruction from the memory controller and excludes a part of a delay time from the read-out instruction until the data read-out of at least one other memory device.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority of Japanese Patent Application No. 2008-080013, filed on Mar. 26, 2008, the entire contents of which are incorporated herein by reference. 
     FIELD 
     The embodiments discussed herein are related to a memory controller device, a control method for a memory controller device and a data reception device. 
     BACKGROUND 
       FIG. 7  shows a memory system  101 . The memory system  101  has a memory controller device  102  and a memory device  103 . The memory controller device  102  has a memory controller  104  and a physical layer part  105  for receiving/transmitting data. The physical layer part  105  is provided with a data reception circuit  113 . 
     A plurality of SDRAM (Synchronous DRAM) (not shown) are mounted in the memory device  103 . A clock supply route to the plurality of SDRAMs in the memory device  103  is constructed by a daisy chain. The memory device  103  and the physical layer part  105  are connected to each other through a clock signal line CW. A clock CK is input through the clock signal line CW and the clock supply route to each of the plurality of SDRAMs. Furthermore, a read command output from the memory controller  104  is input to each of the plurality of SDRAMs through a command signal (not shown) and a command supply route (not shown). 
     The plurality of SDRAMs in the memory device  103  and the data reception circuit  113  are connected to one another through a strobe signal line SW and a data signal line DW. Data signals DQ output from the plurality of SDRAMs are input to the data reception circuit  113  through the data signal line DW. The data strobe signals DQS output from the plurality of SDRAM are input to the data reception circuit  113  through the strobe signal line SW. The reception data signal RD is output from the data reception circuit  113 , and input to the memory controller  104 . 
     An input terminal of the data reception circuit  113  is provided with a terminating resistor (not shown) whose ON/OFF may be controlled. The terminating resistor is used to reduce reflection of an input signal, thereby enhancing waveform quality. The terminating resistor is required to be set to an ON-state during a read period for which data are input from the memory device  103  to the data reception circuit  113 . 
     Furthermore, JP-A-2000-195263, JP-A-2007-115366 and JP-A-10-336008 disclose examples of other memory systems. 
     The time period from the output time of the read command from the memory controller device  102  to the input time of the data signal DQ and the data strobe signal DQS to the data reception circuit  113  is a round trip time. The round trip time contains a propagation delay time of the clock CK. The clock supply route to the plurality of SDRAMs in the memory device  103  is constructed by the daisy chain, and thus the length of the clock supply route is different for every SDRAM. Accordingly, a time lag occurs in the round trip time among the SDRAMs. To prevent signal line conflict, the period for which the terminating resistor is set to the ON-state is set to a period having a sufficiently larger margin than the actual read period. Accordingly, the occupation time of the signal line is lengthened, causing a drop in bus efficiency. 
     SUMMARY 
     According to an aspect of the invention, a memory controller device coupled to a memory device equipment including a plurality of memory devices, includes a memory controller configured to instruct read-out of data in the memory device and a physical part configured to terminate a read-out signal for a certain period containing an arrival time of data read out from one memory device of the memory device equipment in accordance with a read-out instruction from the memory controller but not a part of a delay time from the read-out instruction until the data read-out of at least one other memory device. 
     The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  illustrates a circuit diagram of a memory system  1 ; 
         FIG. 2  illustrates a detailed circuit diagram of a clock generating circuit  15 , a delay circuit  11   a  and a data reception circuit  13   a;    
         FIG. 3  illustrates a timing chart of the operation of the memory system  1 ; 
         FIG. 4  illustrates a timing chart showing a comparative operation; 
         FIG. 5  illustrates a circuit diagram of a data transmission/reception system  201 ; 
         FIG. 6  illustrates a circuit diagram of a memory system  301 ; and 
         FIG. 7  illustrates a circuit diagram of a conventional memory. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     An embodiment according to a memory system  1  will be described with reference to  FIGS. 1 to 4 . 
       FIG. 1  is a circuit diagram showing the memory system  1  according to this embodiment. The memory system  1  has a memory controller device  2  and a memory device  3 . The memory device  3  has SDRAM  6   a  to  6   h . The terminal CP  3  of the memory device  3  is connected to the terminal CP 2  of a memory controller device  2  through a clock signal line CW. The memory device  3  is a memory device based on DDR3 standard and a flyby architecture is adopted. In this architecture, SDRAMs  6   a  to  6   h  are connected to the terminal CP 3  in the daisy-chain connection style. A clock CK and a reversed-phase clock CKX are input to the terminal CP 3 . A data strobe signal DQSa and DQSXa are output from DRAM  6   a , and input to the terminal SP 3   a . A data signal DQa is output from SDRAM  6   a  and input to the terminal DP 3   a . The structure of SDRAMs  6   b  to  6   h  are the same as SDRAM  6   a , and thus the detailed description thereof is omitted. 
     The memory controller device  2  has a memory controller  4  and a physical layer part  5 . The physical layer part  5  is a circuit used for data transmission/reception to/from the memory controller  4  and the memory device  3 . The physical layer part  5  is provided with a clock generating circuit  15 , delay circuits  11   a  to  11   h , data reception circuits  13   a  to  13   h  and data reception circuits  14   a  to  14   h . A clock ITXCK is input from the memory controller  4  into the clock generating circuit  15 . A clock CK and a reversed-phase clock CKX output from the clock generating circuit  15  are input to the terminal CP 2 . An ODT control signal CSa and a delay control signal DSa are input to the delay circuit  11   a , and a second delay ODT control signal DCS 2   a  is output from the delay circuit  11   a . The second delay ODT control signal DCS 2   a  is input to the data reception circuits  13   a  and  14   a.    
     The terminal DP 2   a  is connected to the data reception circuit  13   a.  The terminal DP 2   a  is connected to the terminal DP 3   a  of the memory device  3  through a data signal line DWa. A data signal DQa is input from SDRAM  6   a  to the data reception circuit  13   a , and a reception data signal RDQa is output from the data reception circuit  13   a . The terminal SP 2   a  is connected to the data reception circuit  14   a . The terminal SP 2   a  is connected to the terminal SP 3   a  of the memory device  3  through a strobe signal line SWa. Data strobe signals DQSa and DQSXa are input from SDRAM  6   a  are input to the data reception circuit  14   a,  and a reception data strobe signal RDQSa is output from the data reception circuit  14   a.    
     The structure of the delay circuits  11   b  to  11   h  are the same as the delay circuit  11   a . The structure of the data reception circuits  13   b  to  13   h  are the same as the data reception circuit  13   a , and the structure of the data reception circuits  14   b  to  14   h  are the same as the data reception circuit  14   a . Accordingly, the detailed description thereof is omitted from the following description. The physical layer part  5  also has a circuit for transmitting the read command output from the memory controller  4 , etc. to the memory device  3 . The structure of the circuit is the same as the clock generating circuit  15 , and thus the detailed description thereof is omitted. 
       FIG. 2  shows a detailed internal circuit of the clock generating circuit  15 , the delay circuit  11   a  and the data reception circuit  13   a . The clock generating circuit  15  includes a latency part  25 , a flip flop  26  and a driver  27 . The latency part  25  of the clock generating circuit  15  includes two flip flops to which an internal clock X 2 CLK is input, and which are connected to each other in series at two stages. A clock ITXCK is input to the latency part  25 , and a clock RCK to which a predetermined latency is provided is output from the latency part  25 . The clock RCK and the internal clock X 2 CLK are input to the flip flop  26 . A clock CK and a reversed-phase clock CKX are output from the flip flop  26  through the driver  27 . The clock CK is input to the terminal CP 21 , and the reversed-phase clock CKX is input to the terminal CP 22 . 
     The delay circuit  11   a  has a latency part  17   a , a delay control signal operation circuit  16   a , a delay roughly adjusting part  21   a , a delay minutely adjusting part  24   a  and a dummy driver  18   a . The latency part  17   a  includes two-stage flip flops to which an internal clock X 2 CLK is input, and which are connected to each other in series. An ODT control signal CSa is input to the latency part  17   a , and a first ODT control signal RCSa to which a predetermined latency is provided is output from the latency part  17   a . A delay control signal DSa is input to the delay control signal operation circuit  16   a , and a delay amount signal DDa is output from the delay control signal operation circuit  16   a . The first ODT control signal RCSa, the delay amount signal DDA and the internal clock X 2 CLK are input to the delay roughly adjusting part  21   a , and a first delay ODT control signal DCS  1   a  is output from the delay roughly adjusting part  21   a . The delay minutely adjusting part  24   a  has a DLL circuit  22   a  and a flip flop  23   a . The internal clock X 2 CLK and the delay amount signal DDa are input to the DLL circuit  22   a , and a delay clock DCLKa is output from the DLL circuit  22   a . The first delay ODT control signal DCS 1   a  and the delay clock DCLKa are input to the flip flop  23   a . A second delay ODT control signal DCS 2   a  is output from the flip flop  23   a  through a dummy driver  18   a , and it is input to the data reception circuit  13   a.    
     The data reception circuit  13   a  has a driver cell  31   a , a receiver cell  32   a , terminating resistors ODT 1   a  and ODT 2   a  and switches SW 1   a  and SW 2   a.  Predetermined potential is supplied to the input terminal of the receiver cell  32   a  through the switch SW 1   a  and the terminating resistor ODT 1   a , and predetermined potential is also supplied to the input terminal of the receiver cell  32   a  through the switch SW 2   a  and the terminating resistor ODT 2   a . A data signal DQa is input to the input terminal of the receiver cell  32   a . A second delay ODT control signal DCS 2   a  is input to the switches SW 1   a  and SW 2   a . A reception data signal RDQa is output from the receiver cell  32   a , and input to the memory controller  4 . 
     Next, the operation of the memory system  1  according to the present invention will be described with reference to the timing chart of  FIG. 3 . First, the description will be made by applying this embodiment to a case where data are read out from SDRAM  6   a  of the memory device  3  ( FIG. 1 ). This case corresponds to a case where the round trip time is minimal. At a time t 1  of  FIG. 3 , the read command RCMD is output from a circuit (not shown) of the physical layer part  5 , and input to SDRAM  6   a  together with the clock CK. After a round trip time RTTa elapses from the time t 1 , the data strobe signal DQSa and the data signal DQa are input from SDRAM  6   a  to the physical layer part  5 . Here, the round trip time RTTa corresponds to the sum of the following three delay times: (1) a delay time of the clock CK in a clock route CPa ( FIG. 1 ) extending from the memory controller device  2  to SDRAM  6   a , (2) an internal delay time of SDRAM  6   a  during the time period from the input of the read command RCMD and the clock CK into SDRAM  6   a  until the read-out of the data strobe signal DQSa and the data signal DQa, and (3) a delay time of the data signal DQa at the data signal line DWa and a delay time of the data strobe signal DQSa at the strobe signal line SWa. 
     The operation in the delay circuit  11   a  will be described. The delay circuit  11   a  is a circuit for delaying the first ODT control signal RCSa in conformity with the round trip time RTTa. The delay control signal DSa is input from the memory controller  4  to the delay control signal operation circuit  16   a  in accordance with the output of the read command RCMD at the time t 1  of  FIG. 3 . The round trip time RTTa of SDRAM  6   a  is held in advance in the delay control signal operation circuit  16   a . The delay control signal operation circuit  16   a  outputs the delay amount signal DDa in accordance with the input delay control signal DSa. Here, the delay amount signal DDa is a signal for instructing the delay roughly adjusting part  21   a  and the delay minutely adjusting part  24   a  to provide the first ODT control signal RCSa with the delay amount corresponding to the round trip time RTTa. A simulation method may be adopted as a method of determining the round trip time RTTa in advance, for example. 
     The delay roughly adjusting part  21   a  is a rough adjustment circuit for adjusting a delay amount of a half cycle or more of the internal clock X 2 CLK. The delay roughly adjusting part  21   a  provides the delay corresponding to the delay amount signal DDa to the first ODT control signal RCSa, and outputs the delay result as the first delay ODT control signal DCS 1   a . The first delay ODT control signal DCS 1   a  is input to the delay minutely adjusting part  24   a.    
     The delay minutely adjusting part  24   a  is a minute adjustment circuit for adjusting a delay amount which is smaller than the half cycle of the internal clock X 2 CLK. The DLL circuit  22   a  provides the delay corresponding to the delay amount signal DDa to the internal clock X 2 CLK, and outputs it as the delay clock DCLKa. The flip flop  23   a  provides the delay corresponding to the delay clock DCLKa to the first delay ODT control signal DCS 1   a , and outputs it as the second delay ODT control signal DCS 2   a.    
     The delay time DTCSa corresponding to the round trip time RTTa is provided to the first ODT control signal RCSa by the delay roughly adjusting part  21   a  and the delay minutely adjusting part  24   a  as described above, thereby generating the second delay ODT control signal DCS 2   a  ( FIG. 3 , an arrow A 1 ). 
     The second delay ODT control signal DCS 2   a  is input to the switches SW 1   a  and SW 2   a  of the data reception circuit  13   a  through the dummy driver  18   a.  The switches SW 1   a  and SW 2   a  are set to a conduction state at a terminating term TTa for which the second delay ODT control signal DCS 2   a  is set to a high level. Accordingly, the terminating processing is carried out at the terminating term TTa at the data reception circuit  13   a.    
     Secondly, the following description will be made by applying this embodiment to a case where data are read out from SDRAM  6   h . This case corresponds to a case where the round trip time is maximum. At the time t 1  of  FIG. 3 , the read command RCMD is output from a circuit (not shown) of the physical layer part  5 , and input to SDRAM  6   h  together with the clock CK. In this case, after a round trip time RTTh elapses from the time t 1 , the data strobe signal DQSh and the data signal DQh are input from SDRAM  6   h  to the physical layer part  5 . Here, the round trip time RTTh corresponds to the following three delay times; (1) a delay time of the clock CK in the clock route CPh ( FIG. 1 ) extending from the memory controller device  2  to SDRAM  6   h , (2) an internal delay time in SDRAM  6   h , and (3) a delay time of the data signal DQh at the data signal line DWh and a delay time of the data strobe signal at the strobe signal line SWh. 
     Here, a round trip time difference RTD 2  occurs between the round trip times RTTa and RTTh. This is because the clock supply route to SDRAMs  6   a  to  6   h  is constructed by the daisy chain and thus a difference in route length exists between the clock routes CPa and CPh. The length of the clock route CPa is shortest, and the length of the clock route CPh is longest, so that the round trip time difference RTD 2  is the maximum value of the difference between SDRAMs in the round trip time. 
     The delay time DTCSh corresponding to the round trip time RTTh is provided to the first ODT control signal RCSh by the delay circuit  11   h , whereby the second delay ODT control signal DCS 2   h  is generated ( FIG. 3 , an arrow A 2 ). The process of generating the second delay ODT control signal DCS 2   h  is the same as the process of generating the second delay ODT control signal DCS 2   a  as described above, and thus the description thereof is omitted. The second delay ODT control signal DCS 2   h  is input to the data reception circuit  13   h . In the data reception circuit  13   h , the terminating processing is executed at the terminating period TTh for which the second delay ODT control signal DCS 2   h  is set to a high level. 
     As described above, the value of the terminating period TTa is set to a small value which is matched with the arrival period Ata of one SDRAM  6   a.  The value of the terminating term TTh is set to a small value which is matched with the arrival period ATh of one SDRAM  6   h . When data are read out from the SDRAM  6   a , the value of the delay time DTCSa is adjusted in accordance with the value of the round trip time RTTa so that the terminating period TTa contains the overall arrive period Ata. Furthermore, when data are read out from SDRAM  6   h,  the value of the delay time DTCSh is adjusted in accordance with the value of the round trip time RTTh so that the terminating period TTh contains the overall arrival period ATh. Accordingly, even when a round trip time difference RTD 2  exists, the ON/OFF timing of the terminating resistor may be set so that the terminating processing is executed within the period of the terminating periods TTa and TTb having small values. The adjusting operation of the delay time when data are read out from SDRAMs  6   b  to  6   g  is the same as described above, and thus the detailed description thereof is omitted. 
     The delay time DTCSa provided to the second delay ODT control signal DCS 2   a  is given with the clock CK set as a reference, and thus it is required to match the clock CK and the second delay ODT control signal DCS 2   a  in phase as much as possible. In the memory controller device  2  of this embodiment, the latency part  25  and the latency part  17   a  are designed to have the same circuit construction. Accordingly, the latency provided to the clock ITXCK by the latency part  25  is identical to the latency provided to the ODT control signal CSa by the latency part  17   a . The driver  27  and the dummy driver  18   a  are designed to have the same circuit construction. Accordingly, the delay amount provided to the clock CK by the driver  27  is identical to the delay amount provided to the second delay ODT control signal DCS 2   a  by the dummy driver  18   a . Accordingly, the clock CK and the second delay ODT control signal DCS 2   a  may be matched with each other in phase, so that the delay time DTCSa may be more accurately controlled. 
     For comparison, a description will be given of a case where, in the circuit of  FIG. 7 , the terminating period for which the terminating process is executed is set to a large value having a margin with respect to the arrival period for which data arrives from SDRAM.  FIG. 4  shows a timing chart.  FIG. 4  shows a case where the data signal DQ 1  having the minimum round trip time RTT 1  and the data strobe signal DQS 1  are input to the data reception circuit  113  and a case where the data signal DQ 2  having the maximum round trip time RTT 2  and the data strobe signal DQS 2  are input to the data reception circuit  113 . A round trip time difference RTD 1  exists between the start point of the arrival period AT 1  for which the data strobe signal DQS 1  is input and the start point of the arrival period AT 2  for which the data strobe signal DQS 2  is input. 
     The terminating period TT_A of the ODT control signal RCS_A is set so that the overall arrival period AT 1  and the overall arrival period AT 2  are contained in the terminating period TT_A. In other words, the terminating period TT_A is set to a large value having a margin so as to contain the overall period of the round trip time difference RTD 1  corresponding to the difference between the round trip times RTT 1  and RTT 2 . 
     Accordingly, even when the round trip time varies within the range between the round trip times RTT 1  and RTT 2 , the terminating process may certainly be executed during the data arrival periods AT 1  and AT 2 . However, during the terminating period TT_A of a large value having a margin, the data signal line DW and the strobe signal line SW are occupied and data transmission efficiency is decreased. 
     However, in the memory system  1  of this embodiment, as shown in  FIG. 3 , the terminating period TTh when the round trip time is maximum (when data are read out from SDRAM  6   h ) is set so as not to contain the overall round trip time RTTa. In other words, the terminating period TTh is set so that a part of the round trip time difference RTD 2  corresponding to the difference between the round trip times RTTa and RTTh is not contained in the terminating period TTh. Accordingly, the length of the terminating period TTh is set to a small value so that it contains the overall arrival period ATh, but does not contain a part of the arrival period Ata. 
     The terminating period TTa when the round trip time is minimum (when data are read out from SDRAM  6   a ) is set so as not to contain a part of the round trip time RTTh. Accordingly, the length of the terminating period TTa is set to a small value so that it contains the overall arrival period Ata, but does not contain a part of the arrival period ATh. 
     As described above, in the memory system  1  of this embodiment, the start point of each of the terminating periods TTa to TTh is adjusted in accordance with the value of each of the round trip times RTTa to RTTh, whereby each of the data arrival periods Ata to ATh may be certainly contained in each of the terminating periods TTa to TTh. Accordingly, the signal line is occupied during only the terminating periods TTa to TTh having a small value, so that the data transfer efficiency may be prevented from being lowered. 
     The present invention is not limited to the above embodiment, and various kinds of improvements and modifications may be made without departing from the subject matter of the present invention. 
     In this embodiment, the physical layer part  5  is provided with the delay control signal operation circuits  16   a  to  16   h . That is, the round trip time of each SDRAM is held in the physical layer part  5 . However, the present invention is not limited to this embodiment, and the round trip time may be held in parts other than the physical layer part  5 . For example, the round trip time of each SDRAM may be held in the memory controller  4 . In this case, each of the delay amount signals DDa to DDh are output from the delay control signal operation circuit provided to the memory controller  4 , and input to each of the delay circuits  11   a  to  11   h.    
     In this embodiment, the memory system  1  is described. However, the system to which the present invention is applied is not limited to the memory system. For example, the present invention may be applied to the data transmission/reception system  201  as shown in  FIG. 5 . The data transmission/reception system  201  has a data reception device  202  and a data transmitter  203 . The data reception device  202  has a controller  204  and a physical layer part  205 . The physical layer part  205  is provided with a data reception circuit  213 . Plural data transmission devices for transmitting data to the data reception device  202  are mounted in the data transmitter  203 . The data transmitter  203  and the physical layer part  205  are connected to each other through the clock signal line CW. The clock supply route to the plural data transmission devices in the data transmitter  203  is constructed by the daisy chain. A clock CK is input to each of the plural data transmission devices through the clock signal line CW and the clock supply route. Transmission data TD output from the data transmission device in the data transmitter  203  is input to the data reception circuit  213  through the data signal line DW. A terminating resistor (not shown) whose ON/OFF may be controlled is provided to the input terminal of the data reception circuit  213 . 
     Here, a difference between data transmission devices exists in the round trip time of the transmission data TD. However, the data transmission/reception system  201  has a function of adjusting the start point of the terminating period TT in accordance with the value of the round trip time as in the case of the memory system  1  according to this embodiment. Accordingly, even when a difference (lag) between data transmission devices exists in the round trip time, the terminating processing may certainly be executed within the arrival period of the transmission data TD. The detailed method of adjusting the start point of the terminating period is the same as the memory system  1  of this embodiment, and thus the description thereof is omitted. 
     Furthermore, in this embodiment, the memory system has one memory device. However, the present invention is not limited to this embodiment, and it may be provided with plural memory devices. For example, a memory system  301  as shown in  FIG. 6  may be used. The memory system  301  has a memory controller device  302  and memory devices  303  and  403 . The memory controller device  302  has a memory controller  304  and a physical layer part  305 . A clock generating circuit  315  of the physical layer part  305  and memory devices  403  and  404  are connected to each other through a common clock signal line CW 2 . The clock CK output from the clock generating circuit  315  is commonly input to the memory devices  303  and  403 . An ODT control signal CS 3  and a delay control signal DS 3  are input to a delay circuit  311 . The delay circuit  311  provides the delay time corresponding to the value of the round trip time to the ODT control signal CS 3 , and outputs it as a second delay ODT control signal DCS 3 . The second delay ODT control signal DCS 3  and the data signals DQ 3   a  to DQ 3   h  are input to the data reception circuit  313 . An ODT control signal CS 4  and a delay control signal DS 4  are input to the delay circuit  411 . The delay circuit  411  provides the ODT control signal CS 4  with the delay time corresponding to the value of the round trip time, and outputs it as a second delay ODT control signal DCS 4 . The second delay ODT control signal DCS 4  and the data signals DQ 4   a  to DQ 4   h  are input to the data reception circuit  413 . The detailed circuit construction and operation are the same as the memory system  1  according to this embodiment, and thus the description thereof is omitted. 
     Accordingly, the terminating process corresponding to the memory device  303  in the data reception circuit  313  and the terminating process corresponding to the memory device  403  in the data reception circuit  413  may be executed in parallel to each other. Accordingly, the reduction of the data transfer efficiency may be prevented in both the memory devices  303  and  403 . The number of the memory devices provided to the memory system is not limited to two, as three or more memory devices may be provided. 
     SDRAMs  6   a  to  6   h  are examples of the memory device, the memory device  3  is an example of the memory device equipment, the memory controller device  2  is an example of the memory controller device, the physical layer part  5  is an example of a physical part, the round trip times RTTa to RTTh are examples of the delay time, the delay circuits  11   a  to  11   h  are examples of a setting part, the ODT control signals CSa and CSh are examples of the control signal, the internal clock X 2 CLK is an example of a first clock, the delay roughly adjusting part  21   a  is an example of a first adjusting part, the delay minutely adjusting part  24   a  is an example of a second adjusting part, the data reception circuits  13   a  to  13   h  and the data reception circuits  14   a  to  14   h  are examples of a terminating part, and the latency part  17   a  and the dummy driver  18   a  are examples of a dummy clock circuit part. 
     All examples and conditional language recited herein are intended to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiments of the present inventions have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.