Abstract:
A method of manufacturing a semiconductor device includes the steps of: preparing a semiconductor substrate having first and second element forming regions, the first and second element forming regions divided by an element separating insulation film; forming a first gate insulation film on the semiconductor substrate; forming a predetermined film on the first gate insulation film; forming a protective film on the predetermined film in the first element forming region; forming a second gate insulation film in the second element forming region by deforming the predetermined film into an insulation film using the protective film as a mask; removing the protective film and the remaining predetermined film which is not deformed into the insulated film; and forming gate electrodes on the first and second gate insulation films which are exposed by removing the remaining predetermined film.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a method of manufacturing a semiconductor device, which in particular has transistors for different withstand voltages.  
         [0003]     2. Background Information  
         [0004]     With respect to a conventional semiconductor device having transistors for different withstand voltages (e.g. Japanese Laid Open Patent Application No. 2000-150665 (hereinafter to be referred to as Patent Reference 1), Japanese Laid Open Patent Application No. 2000-200836 (hereinafter to be referred to as Patent Reference 2) and Japanese Laid Open Patent Application No. 2000-164726 (hereinafter to be referred to as Patent Reference 3)), the transistors for different withstand voltages are formed on the same semiconductor substrate by normally using gate oxide films with different thicknesses.  FIG. 1  and  FIG. 2  show the manufacturing processes of a conventional semiconductor device having transistors for different withstand voltages.  
         [0005]     According to the conventional art, first, as shown in  FIG. 1A , element isolating insulation films  102  are formed using the STI (shallow trench isolation) method by which the upper part of a semiconductor substrate  101  is divided into active regions AR and field regions FR.  
         [0006]     Then, by conducting a thermal oxidation treatment on the surface of the semiconductor substrate  101 , a gate oxide film  103 A is formed on the entire surface of the semiconductor substrate  101 , as shown in  FIG. 1B . The gate oxide film  103 A is thinner than a gate oxide film for high withstand voltage.  
         [0007]     Next, a predetermined resist solution is spin-coated over the gate oxide film  103 A after which a known photolithography process is conducted to form a resist pattern R 101  only in a region on the side of high withstand voltage. Then, using the resist pattern R 101  as a mask, the gate oxide film  103 A in a region on the side of low withstand voltage is removed by a known etching method. Through such process, a gate oxide film  103   a  will remain only in the region on the high withstand voltage side, as shown in  FIG. 1C . The resist pattern R 101  on the remaining gate oxide film  103   a  is removed after the etching process is finished.  
         [0008]     Next, by conducting a thermal oxidation treatment on the entire surface of the semiconductor substrate  101 , a gate oxide film  104  with a thickness suited for low withstand voltage is formed on the entire surface, as shown in  FIG. 2A . By this arrangement, a gate oxide film  103 , which is a laminated product of the gate oxide film  103   a  and the gate oxide film  104 , will be formed in the region on the high withstand voltage side. Accordingly, the thickness of the gate oxide film  103 A ( FIG. 1B ) should be set so that the thickness of the laminated product of the gate oxide film  103   a  and the gate oxide film  104  is suited for high withstand voltage.  
         [0009]     Next, a polysilicon is deposited over the entire surface of the semiconductor substrate  101  on which the gate oxide film  103   a  and the gate oxide film  104  are formed, and then processed by a known photolithography process and etching process to have a gate pattern  107   a  formed on the gate oxide film  104  in the active region AR on the low withstand voltage side, and a gate pattern  107   b  formed on the gate oxide film  103  in the active region AR on the high withstand voltage side, as shown in  FIG. 2B .  
         [0010]     Through the above described processes, it is possible to manufacture a semiconductor device having a transistor for low withstand voltage and a transistor for high withstand voltage formed on the same substrate.  
         [0011]     However, according to the conventional art described above, since the gate oxide film  103 A is thin, it is a problem in that the element isolating insulation films  102  in the field regions FR, particularly in the vicinity of the active regions AR, may be removed to an extent more than necessary, which may result in producing dimples on the element isolating insulation films  102 .  FIG. 3A  shows an enlarged view of the field region FR at the process of etching the gate oxide film  103 A ( FIG. 1C ) on the low withstand voltage side.  
         [0012]     As shown in  FIG. 3A , a dimple  111   a  is formed at the border between the element isolating insulation film  102  and the active region AR, and when the thermal oxidation treatment for forming the gate oxide film  104  takes place in such a state, the gate oxide film  104  will end up having a dimpled surface (i.e. a dimple  101   b ,  FIG. 3B ) as it is formed along the dimple  101   a , as shown in  FIG. 3B .  
         [0013]     This dimple  101   b  can cause problems such as an unnecessary concentration of electric field in the dimple  101   b , the gate oxide film  104  at the dimple  101   b  not becoming an appropriate thickness, and so forth. These problems can become triggers for other problems such as deterioration of the withstand voltage of the gate oxide film  104 , etc.  
         [0014]     Furthermore, this dimple  101   b  can cause materials of the gate pattern  107  (i.e. a poly-silicon  107   c ,  FIG. 3B ) to unnecessarily remain in the dimple  101   b  at the time of forming the gate pattern  107 , as shown in  FIG. 3B , and this can cause a short circuit of the gate.  
         [0015]     In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved method of manufacturing a semiconductor device. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.  
       SUMMARY OF THE INVENTION  
       [0016]     It is therefore an object of the present invention to resolve the above-described problems, and to provide a method of manufacturing a semiconductor device which makes it possible to prevent withstand voltage deterioration of the gate insulation films, short circuits of the gates, and other possible problems.  
         [0017]     In accordance with an aspect of the present invention, a method of manufacturing a semiconductor device comprises the steps of: preparing a semiconductor substrate having first and second element forming regions, the first and second element forming regions divided by an element separating insulation film; forming a first gate insulation film on the semiconductor substrate; forming a predetermined film on the first gate insulation film; forming a protective film on the predetermined film in the first element forming region; forming a second gate insulation film in the second element forming region by deforming the predetermined film into an insulation film using the protective film as a mask; removing the protective film and the remaining predetermined film which is not deformed into the insulated film; and forming gate electrodes on the first and second gate insulation films which are exposed by removing the remaining predetermined film.  
         [0018]     These and other objects, features, aspects, and advantages of the present invention will become apparent to those skilled in the art from the following detailed description, which, taken in conjunction with the annexed drawings, discloses preferred embodiments of the present invention. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0019]     Referring now to the attached drawings which form a part of this original disclosure:  
         [0020]      FIG. 1A  to  FIG. 1C  are diagrams showing a conventional method of forming a semiconductor device having a transistor for low withstand voltage and a transistor for high withstand voltage formed on a single semiconductor substrate;  
         [0021]      FIG. 2A  to  FIG. 2C  are diagrams showing a conventional method of forming the semiconductor device having the transistor for low withstand voltage and the transistor for high withstand voltage formed on the single semiconductor substrate;  
         [0022]      FIG. 3A  and  FIG. 3B  are diagrams for explaining problems with respect to the semiconductor device having the transistor for low withstand voltage and the transistor for high withstand voltage formed on the single semiconductor substrate produced according to the conventional method shown in  FIGS. 1 and 2 ;  
         [0023]      FIG. 4  is a diagram showing the structure of a semiconductor device according to a first embodiment of the present invention;  
         [0024]      FIG. 5A  to  FIG. 5C  are diagrams showing processes of forming the semiconductor device according to the first embodiment of the present invention;  
         [0025]      FIG. 6A  to  FIG. 6C  are diagrams showing processes of forming the semiconductor device according to the first embodiment of the present invention;  
         [0026]      FIG. 7A  to  FIG. 7C  are diagrams showing processes of forming the semiconductor device according to the first embodiment of the present invention; and  
         [0027]      FIG. 8A  to  FIG. 8B  are diagrams showing processes of forming the semiconductor device according to the first embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0028]     A selected embodiment of the present invention will now be explained with reference to the drawings. It will be apparent to those skilled in the art from this disclosure that the following descriptions of this embodiment of the present invention are provided for illustration only and not for the purpose of limiting the invention as defined by the appended claims and their equivalents.  
         [0000]     Structure  
         [0029]      FIG. 4  is a diagram showing the structure of a semiconductor device  1  according to a first embodiment of the present invention. In the following, each process in manufacturing the semiconductor device  1  according to the manufacturing method of the present invention will be described based on a sectional structure of the semiconductor device  1  which includes a line linking low withstand voltage MOS (metal oxide semiconductor) transistors LVMOS and high withstand voltage MOS transistors HVMOS and which is vertical with a semiconductor substrate  11 .  
         [0030]     As shown in  FIG. 4 , the semiconductor device  1  has a structure in which active regions (also referred to as element forming regions) AR and field regions (also referred to as element isolating regions) FR are defined by having element isolating insulation films  12  formed on the semiconductor substrate  11 .  
         [0031]     On the surface of the semiconductor substrate  11  on the side where the low withstand voltage MOS transistors LVMOS are to be formed (hereinafter to be referred to as the low withstand voltage side), a gate oxide film  13   a  having a certain thickness (i.e. a first thickness) is formed. On the parts of the gate oxide film  13   a  in the active regions AR of the low withstand voltage side, gate electrodes  17  are formed. In each of these active regions AR, a pair of highly doped regions  18   p  or  18   n  are formed in a way sandwiching a region beneath the gate electrode  17 . In other words, each low withstand voltage MOS transistor LVMOS includes the gate oxide film  13   a  having the first thickness which is formed on the active region AR of the semiconductor substrate  11 , the gate electrode  17  formed on this gate oxide film  13   a , and a pair of highly doped regions  18   p  or  18   n  formed in the active region AR.  
         [0032]     On the other hand, on the surface of the semiconductor substrate  11  on the side where the high withstand voltage MOS transistors HVMOS are to be formed (hereinafter to be referred to as the high withstand voltage side), a gate oxide film  13   b  having a certain thickness (i.e. a second thickness) which is thicker than the first thickness is formed. On the parts of the gate oxide film  13   b  in the active regions AR of the high withstand voltage side, gate electrodes  17  are formed. In each of these active regions AR, a pair of highly doped regions  18   p  and  18   n  are formed in a way sandwiching a region beneath the gate electrode  17 . In other words, each high withstand voltage MOS transistor HVMOS includes the gate oxide film  13   b  having the second thickness being thicker than the first thickness which is formed on the active region AR of the semiconductor substrate  11 , the gate electrode  17  formed on this gate oxide film  13   b , and a pair of highly doped regions  18   p  or  18   n  formed in the active region AR.  
         [0033]     In the above structure, the semiconductor substrate  11  can be a P type silicon substrate, for instance. In this case, the element isolating insulation films  12  can be formed using, for instance, the STI method.  
         [0034]     In certain regions of the semiconductor substrate  11  where N type MOS transistors are formed, P well regions  19   p  are formed by implanting P type impurities into those regions. In this embodiment, as for the P type impurities, a P type ion such as a boron difluoride ion (BF 2   + ) can be used, for example. The dose amount of the P type ion can be around 2×10 15 /cm 2 .  
         [0035]     On the other hand, in certain regions of the semiconductor substrate  11  where P type MOS transistors are formed, N well regions  19   n  are formed by implanting N type impurities into those regions. In this embodiment, as for the N type impurities, an N type ion such as a phosphorous ion (P + ) can be used, for example. The dose amount of the N type ion can be around 2×10 15 /cm 2 .  
         [0036]     In certain region of the P well region  19   p  where channel is formed, P type impurities are diffused for the purpose of adjusting threshold value. In the following, those region will be referred to as threshold adjusting region  20   p . As for the P type impurities, a P type ion such as a boron difluoride ion (BF 2   + ) can be used, for example. The dose amount of the P type ion can be around 2×10 12 /cm 2 .  
         [0037]     On the other hand, in threshold adjusting region  20   n  of the N well region  19   n , N type impurities are diffused for the purpose of adjusting threshold value. As for the N type impurities, an N type ion such as a phosphorous ion (P + ) can be used, for example. The dose amount of the N type ion can be around 2×10 12 /cm 2 .  
         [0038]     On the active regions AR on the low withstand voltage side, the gate oxide film  13   a  having the first thickness is formed, as described above. As for this gate oxide film  13   a , for instance, a silicon oxide film (SiO x  film) can be used. In addition, it is also possible to use a silicon nitride film (SiN x  film), for example. The thickness of the gate oxide film  13   a , for instance, can be 7 nm (nanometer) provided that the withstand voltage of the low withstand voltage MOS transistor LVMOS is 3.3V, for example.  
         [0039]     On the gate oxide film  13   a , the gate electrodes  17  are formed, as described above. The gate electrode  17  can be a polysilicon film, for instance. This polysilicon film is made to be electrically conductive by having P type impurities doped thereto, for example. The thickness of the gate electrode  17  can be 200 to 300 nm, for instance.  
         [0040]     In each active region AR on the low withstand voltage side, a pair of highly doped regions  18   p  or  18   n  are formed in a way sandwiching a region beneath the gate electrode  17 , as described above. Here, when an N type MOS transistor is formed, the diffusion regions  18   p  or  18   n  should be formed by having P type impurities implanted into the corresponding regions. As for the P type impurities, a P type ion such as a boron difluoride ion (BF 2   + ) can be used, for example. The dose amount of the P type ion can be around 2×10 15 /cm 2 .  
         [0041]     On the other hand, when a P type MOS transistor is formed, the diffusion regions  18   p  or  18   n  should be formed by having N type impurities implanted into the corresponding regions. As for the N type impurities, an N type ion such as a phosphorous ion (P + ) can be used, for example. The dose amount of the N type ion can be around 2×10 15 /cm 2 .  
         [0042]     On the active regions AR on the high withstand voltage side, the gate oxide film  13   b  having the second thickness, which is thicker than the first thickness, is formed, as described above. As for this gate oxide film  13   b , for instance, a silicon oxide film (SiO x  film) can be used. Besides, it is also possible to use a silicon nitride film (SiN x  film), for example. The thickness of the gate oxide film  13   b , for instance, can be 50 nm provided that the withstand voltage of the high withstand voltage MOS transistor HVMOS is 20V, for example.  
         [0043]     On the gate oxide film  13   b , the gate electrodes  17  are formed, as described above. The gate electrode  17  can be a polysilicon film, for instance. This polysilicon film is made to have a electrically conductive by having P type impurities doped thereto, for example. The thickness of the gate electrode  17  can be 200 to 300 nm, for instance.  
         [0044]     In each active region AR on the high withstand voltage side, a pair of highly doped regions  18   p  or  18   n  are formed in a way sandwiching a region beneath the gate electrode  17 , as described above. Here, in case when an N type MOS transistor is formed, the diffusion regions  18   p  or  18   n  should be formed by having P type impurities implanted into the corresponding regions. As for the P type impurities, a P type ion such as a boron difluoride ion (BF 2   + ) can be used, for example. The dose amount of the P type ion can be around 2×10 15 /cm 2 .  
         [0045]     On the other hand, when a P type MOS transistor is formed, the diffusion regions  18   p  or  18   n  should be formed by having N type impurities implanted into the corresponding regions. As for the N type impurities, an N type ion such as a phosphorous ion (P + ) can be used, for example. The dose amount of the N type ion can be around 2×10 15 /cm 2 .  
         [0000]     Manufacturing Method  
         [0046]     Now a method of manufacturing the semiconductor device  1  according to the embodiment of the present invention will be described in detail with reference to the drawings. FIGS.  5  to  8  are diagrams showing processes of manufacturing the semiconductor device  1  according to the first embodiment of the present invention.  
         [0047]     In this manufacturing method, first, a semiconductor substrate  11  having P well regions  19   p  and N well regions  19   n  is prepared. In this embodiment, a P type silicon substrate is used for the semiconductor substrate  11 . The dose amount of the P well regions  19   p  is 2×10 15 /cm 2 , and the dose amount of the N well regions  19   n  is 2×10 15 /cm 2 .  
         [0048]     Next, as shown in  FIG. 5A , in order to divide the surface of the semiconductor substrate  11  into active regions AR and field regions FR, element isolating insulation regions  12  are formed in certain regions of the semiconductor substrate  11  using a known STI method.  
         [0049]     Next, using a known photolithography process, a resist pattern R 11  is formed over the certain regions of the semiconductor substrate  11  where N type MOS transistors are formed. Then, using the resist pattern R 11  as a mask, P type ions are implanted into the active regions AR, of the semiconductor substrate  11  where N type MOS transistors are formed, for the purpose of adjusting threshold values. Thereby, as shown in  FIG. 5B , threshold adjusting regions  20   p  are formed in the certain regions of the semiconductor substrate  11  where N type MOS transistors are formed. In this case, since the boundaries between the element isolating insulation films  12  and the threshold adjusting regions  20   p  are self-aligned, the resist pattern R 11  should be formed covering at least the P well regions  19   p . In addition, if boron difluoride ions (BF 2   + ) are applied as the P type ions in this process, for instance, boron difluoride ions are accelerated to about 5 KeV (kilo electron volt), and the dose amount of the P type ions can be around 1×10 12  to 3×10 2 /cm 2 . After the threshold adjusting regions  20   p  are formed, the resist pattern R 11  is removed.  
         [0050]     Next, over the certain regions of the semiconductor substrate  11  where P type MOS transistors are formed, a resist pattern R 12  is formed using a known photolithography process. Then, using the resist pattern R 12  as a mask, N type ions are implanted into the active region AR, of the semiconductor substrate  11  where P type MOS transistors are formed, for the purpose of adjusting threshold value. Thereby, as shown in  FIG. 5C , threshold adjusting regions  20   n  are formed in the certain regions of the semiconductor substrate  11  where P type MOS transistors are formed. In this case, since the boundaries between the element isolating insulation films  12  and the threshold adjusting regions  20   n  are self-aligned, the resist pattern R 12  should be formed covering at least the N well regions  19   n . In addition, if phosphorous ions (P + ) are applied to the N type ions in this process for instance, phosphorous ions are accelerated to about 50 KeV, and the dose amount of the N type ions can be around 1×10 12  to 3×10 12 /cm 2 . After the threshold adjusting regions  20   n  are formed, the resist pattern R 12  is removed.  
         [0051]     Next, by conducting a thermal oxidation treatment on the semiconductor substrate  11 , as shown in  FIG. 6A , a gate oxide film  13  having the first thickness (for instance, 5 nm) is formed over the whole upper surface of the semiconductor substrate  11 . Here, as for the conditions of thermal oxidation treatment, for instance, the temperature is set at 850° C. and the heating time is set to 40 minutes.  
         [0052]     Next, by depositing silicon (Si) over the surface of the semiconductor substrate  11  using the CVD (Chemical Vapor Deposition) method and so on, a polysilicon film  14  having a thickness of 20 nm, for instance, is formed on the gate oxide film  13 , as shown in  FIG. 6B . As for this polysilicon film  14 , it may be a film which includes impurities or a film which does not include impurities. That is, any film is applicable as long it is a film which can be changed into an insulation film by a certain method such as a thermal oxidization treatment and nitriding treatment. In this description, such a film is called a predetermined film.  
         [0053]     Next, by depositing silicon nitride (SiN) over the surface of the semiconductor substrate  11  using the CVD method and so on, a silicon nitride film  15  having a thickness of 50 to 200 nm, for instance, is formed on the polysilicon film  14 , as shown in  FIG. 6C .  
         [0054]     Next, using a known photolithography process, a resist pattern R 13  is formed in the active regions AR of the low withstand voltage side, as shown in  FIG. 7A .  
         [0055]     Next, in order to expose the polysilicon film  14  in the active regions AR of the high withstand voltage side and cover the polysilicon film  14  in the active regions AR of the low withstand voltage side with the remaining silicon nitride film  15   a , the silicon nitride film  15  is etched using the resist pattern R 13  as a mask. After the silicon nitride film  14  is etched, the resist pattern R 13  is removed. Accordingly, the structure as shown in  FIG. 7B  is obtained.  
         [0056]     Next, by conducting a thermal oxidation treatment on the semiconductor substrate  11 , the exposed part of the polysilicon film  14  is oxidized, as shown in  FIG. 7C . In other words, the exposed part of the polysilicon film  14 , i.e. a predetermined film, is changed into an insulation film by the thermal oxidation treatment. In this embodiment, the predetermined film is changed into a silicon oxide film. At this time, the silicon nitride film  15   a  functions as a protective film for preventing the polysilicon film  14  in the active region AR of the low withstand voltage side from being oxidized. By this arrangement, the thickness of the gate oxide films  13   b  in the active regions AR of the high withstand voltage side becomes the second thickness (e.g. 50 nm) which is thicker than the first thickness of the gate oxide films  13   a  in the active regions AR of the low withstand voltage side. As for the conditions of thermal oxidation treatment, for instance, the temperature is set at 850° C. and the heating time is set to 30 minutes. However, the present invention is not limited to these conditions, and it is possible to apply any conditions which enable only the exposed part of the polysilicon film  14  to be oxidized completely.  
         [0057]     Next, by etching the silicon nitride film  15   a  and the polysilicon film  14  under the conditions enabling silicon nitride and polysilicon to be etched selectively while making silicon oxide remain, the silicon nitride film  15   a  and the polysilicon film  14  are removed, as shown in  FIG. 8A . With respect to the conditions for etching the silicon nitride film  15   a , for instance, it is possible to apply a mixed gas including CHF 3  CF 4  and O 2  as an etching gas. In this case, the flow ratio of the mixed gas is set to about CHF 3 :CF 4 :O 2 =100:100:3. With respect to the conditions for etching the polysilicon  14 , for instance, it is possible to apply a mixed gas including Cl 2  HBr 3  and O 2  as an etching gas. In this case, the flow ratio of the mixed gas is set to about Cl 2 :HBr 3 :O 2 =100:10:2˜3.  
         [0058]     Next, by depositing silicon (Si) over the surface of the semiconductor substrate  11  using the CVD method and so on, a polysilicon film having a thickness of 200 to 300 nm, for instance, is formed on the gate oxide films  13   a  and  13   b . Then, by patterning the polysilicon film using a known photolithography process and etching process, gate electrodes  17  are formed on the gate oxide films  13   a  and  13   b , respectively, as shown in  FIG. 8B .  
         [0059]     Finally, a resist pattern is formed in the certain regions of the semiconductor substrate  11  where the P type MOS transistors are formed using a known photolithography process, and using the resist pattern as a mask, P type ions are implanted into the active regions AR in the certain regions of the semiconductor substrate  11  where N type MOS transistors are formed so that the dose amount of the implanted regions become around 2×10 15 /cm 2 . By this arrangement, highly doped regions  18   p  are formed in the active regions AR of the semiconductor substrate  11  where N type MOS transistors are formed, as shown in  FIG. 4 . Furthermore, a resist pattern is formed in the certain regions of the semiconductor substrate  11  where the N type MOS transistors are formed using a known photolithography process, and using the resist pattern as a mask, N type ions are implanted into the active regions AR of the semiconductor substrate  11  where P type MOS transistors are formed so that the dose amount of the implanted regions become around 2×10 15 /cm 2 . By this arrangement, highly doped regions  18   n  are formed in the active regions AR of the semiconductor substrate  11  where P type MOS transistors are formed, as shown in  FIG. 4 . At this time, since the gate electrodes  17  perform as masks, the highly doped regions  18   p  and  18   n  are formed at both sides of the regions beneath the gate electrodes  17 , respectively. By this arrangement, the semiconductor device  1  having the low withstand voltage MOS transistors LVMOS and high withstand voltage MOS transistors HVMOS formed on the same semiconductor substrate  11  can be achieved. In addition, an inter-layer insulation film, contact holes and metal wirings are formed in post processes. It is possible to apply known processes for forming them, and therefore detailed descriptions of those processes will be omitted.  
         [0060]     As described above, according to embodiment of the present invention, a semiconductor substrate ( 11 ) having a structure in which first element forming regions (AR) and second element forming regions (AR) are separated by an element isolating insulation film ( 12 ) is prepared. On this semiconductor substrate ( 11 ), a first gate insulation film ( 13 ) is formed, and then a predetermined film ( 14 ) is formed on the first gate insulation film ( 13 ). Then a protection film ( 15   a ) is formed on the predetermined film ( 14 ) over the first element forming regions (AR). While the protection film ( 15   a ) serves as a mask, the predetermined film ( 14 ) on the second element forming regions (AR) is transformed into an insulation film, as a result of which a second gate insulation film ( 13   b ) is formed on the second element forming regions (AR). Then the protective film ( 15   a ) and the predetermined film ( 14 ) are removed to have the first gate insulation film ( 13   a ) exposed at the first element forming regions (AR). Then gate electrodes  17  are formed on the exposed first gate insulation film ( 13   a ) and the second gate insulation film ( 13   b ), respectively.  
         [0061]     According to the present invention, by forming the predetermined layer ( 14 ) on the first gate insulation film ( 13 ) and then turning it into an insulation film at the high withstand voltage side, gate insulation films ( 13   a  and  13   b ) for the transistors on the low withstand voltage side and for the transistors on the high withstand voltage side can be formed, respectively. According to the present invention, it is not necessary to have a process of etching the first gate insulation film ( 13 ) in order to form the gate insulation film ( 13   a ) for the low withstand voltage transistors. Therefore, it is possible to prevent dimples from forming at the element isolating insulation films ( 12 ) in the vicinity of the element forming regions (AR). As a result, it is made possible to prevent withstand voltage deterioration of the gate insulation films, short circuits of the gates and other possible problems.  
         [0062]     In this embodiment, although a silicon oxide film is used for the gate insulation film  13 , the present invention is not limited to this condition. For instance, the gate insulation film  13  can be made of silicon nitride. In this case, the protection film over the polysilicon film  14  should be a silicon oxide film. Furthermore, the thermal oxidation treatment as described with reference to  FIG. 7 ( c ) can be replaced with a nitriding treatment. In addition, as for the conditions for removing the polysilicon film  14  which remained through the nitriding treatment and the silicon oxide film as the protection film, for instance, it is possible to use a mixed gas of CF4/CHF3 with a mixture rate 1:10 as the etching gas.  
         [0063]     While the preferred embodiment of the invention has been described using specific terms, such description is for illustrative purposes only, and it is to be understood that changes and variations may be made without departing from the spirit or the scope of the following claims.  
         [0064]     This application claims priority to Japanese Patent Application No. 2005-52298. The entire disclosures of Japanese Patent Application No. 2005-52298 is hereby incorporated herein by reference.  
         [0065]     While only selected embodiments have been chosen to illustrate the present invention, it will be apparent to those skilled in the art from this disclosure that various changes and modifications can be made herein without departing from the scope of the invention as defined in the appended claims. Furthermore, the foregoing descriptions of the embodiments according to the present invention are provided for illustration only, and not for the purpose of limiting the invention as defined by the appended claims and their equivalents. Thus, the scope of the invention is not limited to the disclosed embodiments.  
         [0066]     The term “configured” as used herein to describe a component, section or part of a device includes hardware and/or software that is constructed and/or programmed to carry out the desired function.  
         [0067]     Moreover, terms that are expressed as “means-plus function” in the claims should include any structure that can be utilized to carry out the function of that part of the present invention.  
         [0068]     The terms of degree such as “substantially,” “about,” and “approximately” as used herein mean a reasonable amount of deviation of the modified term such that the end result is not significantly changed. For example, these terms can be construed as including a deviation of at least ±5% of the modified term if this deviation would not negate the meaning of the word it modifies.