Abstract:
A tamper respondent system having: a physical volume containing an electronic device to be protected; an at least partially conductive surface proximate to the electronic device; and a tamper respondent sensor over the electronic device (the sensor comprising: a flexible, dielectric substrate; conductive traces on the substrate; a porous insulating layer having pores over the conductive traces; and adhesive within said pores of said porous insulating layer), wherein the adhesive is in contact with both the substrate and the at least partially conductive surface through the porous insulating layer.

Description:
FIELD OF THE INVENTION 
     This invention relates to a tamper respondent system, and more particularly, to a tamper respondent sensor adapted for use inside a device. 
     BACKGROUND OF THE INVENTION 
     Tamper respondent sensors are utilized in various applications, including the transport of sensitive information and protecting electronic devices. Typical sensors are in the form of envelopes and shallow boxes, the walls of which are formed by folding flexible sheets incorporating tamper detection features. Included in such sensors are layers of flexible material including a matrix of conductive or semi-conductive lines printed on thin insulating film. The matrix of lines forms a continuous conductor which is broken if attempts are made to penetrate the film. The circuit is monitored by opening the conductor at one point and measuring the resistance between the two ends of the circuit. The resistance changes if the circuit is broken, for example because of tampering. 
     Typically, the sensors are wrapped around the outside of the device to be protected. In many applications, however, the device to be protected is also required to have some form of external ruggedization around it. That is, many electronic devices have an external box or casing that provides strength for transportation or in use. Accordingly, some form of internal tamper respondent sensor is desired. 
     SUMMARY OF THE INVENTION 
     The present invention provides a tamper respondent system having: an electronic device to be protected; an at least partially conductive surface proximate to the electronic device; and a tamper respondent sensor over the electronic device (the sensor comprising: a flexible, dielectric substrate; conductive traces on the substrate; a porous insulating layer having pores over the conductive traces; an adhesive within said pores of said porous insulating layer), wherein the adhesive is in contact with both the substrate and the at least partially conductive surface through the porous insulating layer. 
     Preferably, the at least partially conductive surface is bonded to the tamper respondent sensor by the adhesive, the flexible, dielectric substrate is polyethyleneterephthalate (“PET”), the porous insulating layer comprises spun-bond polyester, and the adhesive comprises a combination of a pressure sensitive adhesive and epoxy. The electronic device includes a Personal Computer Memory Card International Association (“PCMCIA”) card or an electrical chassis or box. 
    
    
     
       DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a side cross-sectional view of a tamper respondent system according to an exemplary embodiment of the present invention. 
         FIG. 1B  is a perspective cut-away view of a tamper respondent system according to an exemplary embodiment of the present invention. 
         FIG. 2  is a side cross-sectional view of a portion of a tamper respondent system according to an exemplary embodiment of the present invention. 
         FIG. 3  is a top view of an exemplary sensor used in an exemplary embodiment of the present invention. 
         FIG. 4  is a side cross-sectional view of a portion of a tamper respondent system according to an exemplary embodiment of the present invention. 
         FIG. 5  is a side cross-sectional view of a tamper respondent system according to an exemplary embodiment of the present invention. 
         FIG. 6  is an isometric view of a chassis or enclosure with a tamper respondent system applied to each interior wall. 
         FIG. 7  is a cross-section view of a tamper respondent system as it would be applied to a chassis or enclosure. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to  FIGS. 1A and 1B  of the drawing, a tamper respondent system  10  will now be described. Tamper respondent system  10  includes a circuit board  14  having components  15  disposed thereon. Components  15  may be electronic devices, some or all of need protection or which contain information to be protected. Disposed on or around circuit board  14  and components  15  is tamper respondent sensor  13 . Disposed around tamper respondent sensor  13  is porous insulating layer  12 . Porous insulating layer  12  has pores, which are defined herein as openings extending from one side of the insulating layer to the other. A preferred material for porous insulating layer  12  is polyester, most preferably spun-bond polyester. Adhesive (not shown) is disposed within the pores of porous insulating layer  12  such that porous insulating layer  12  is securely attached to both an inside surface of outer reinforcing casing  11  and tamper respondent sensor  13 . Preferably, the adhesive is an epoxy on the side of porous insulating layer  12  adjacent the inside surface of outer reinforcing casing  11  and a pressure sensitive adhesive on the side of porous insulating layer  12  adjacent tamper respondent sensor  13 . Alternatively, a uniform adhesive of either PSA or epoxy is used. In any event, it is critical that the adhesive extend from the inside surface of outer reinforcing casing  11  to tamper respondent sensor  13  through the pores of porous insulating layer  12 . 
     In use, if there is any breach of reinforcing casing  11 , it will destroy or tear the porous insulating layer  12 , which is attached by the adhesive to the casing  11 , which in turn will tear or breach the tamper respondent sensor  13 , also by virtue of the adhesive. Such breach of the tamper respondent sensor  13  triggers an electrical state change that sends an appropriate signal to a monitor circuit (not shown). If this electrical state change occurs then it will erase or destroy any information contained in components  15 . 
       FIG. 2  specifically illustrates circuit board  14  in combination with tamper respondent sensor  13 . In one embodiment tamper, respondent sensor  13  is wrapped around circuit board  14  without a separate box or enclosure around circuit board  14 . If necessary in this embodiment, a filler may be used to form a surface over the circuit board to which tamper respondent sensor  13  adheres. Alternatively, a separate box or enclosure may first be disposed around circuit board  14 . 
     Circuit board contains certain components  15  to be protected. Components  15  may include wireless transmitters. A particular arrangement of exemplary components involves components that carry security sensitive information in an encryption module, access to the information stored in the module requiring use of a variable key, the nature of the key required being stored in a memory. As will be described, tamper respondent system  10  is arranged to detect attempts to tamper with or penetrate it. Components  15  thus also include an enclosure monitor circuit which, if tampering is detected, activates a protective action, such as, for example, an erase circuit to erase the information stored in the memory and encryption module. These components  15  are mounted on and interconnected by printed circuit board  14 , power being provided by, for example, a battery. 
     In an exemplary embodiment, tamper respondent sensor  13  is initially planar, as illustrated in  FIG. 3  of the drawings. Sensor  13  in one embodiment may include a matrix of regular or unpredictable patterned conductive or semi-conductive lines printed onto or otherwise attached to a clear or opaque thin, insulating film. In order to make the unpredictable pattern, the trace herein is manually drawn using computer-aided software packages such as PCB-PADS®, from Mentor Graphics, a printed circuit board layout software program. 
       FIG. 4  illustrates porous layer  12  disposed around tamper respondent sensor  13 . Preferred properties for porous layer  12  include that it in fact be porous, as defined above, and that it be insulating or at least non-conducting. It is important that porous layer  12  be non-conducting because, by virtue of its attachment to sensor  13  having conductive or semi-conductive tracks on the outer surface thereof, a short circuit with an outer casing  11  ( FIG. 5 ) would be produced if porous layer  12  were conductive. The preferred material for porous layer  12  is polyester, and most preferably spun-bond polyester. Other porous insulating layers may also be used, such as (without limitation) porous polyethylene, porous polypropylene, porous polytetrafluoroethylene (such as expanded polytetrafluoroethylene), porous polycarbonate. Virtually any non-conductive or insulating material may be used, provided it is porous. Preferably, porous layer  12  has a thickness sufficient to ensure electrical isolation between outer casing  11  and sensor  13 . 
       FIG. 5  illustrates porous layer  12  is attached to both outer casing  11  and sensor  13  by adhesive  21 . Adhesive  21  must penetrate the pores of porous layer  12 , such that porous layer  12  is securely attached to both the inner surface of outer casing  11  and sensor  13 . In this manner, any attempt to tamper with outer protective casing  11  necessarily results in a breach of porous layer  12  and thus of sensor  13 , triggering an electrical state change. Casing  11  can alternatively be a chassis, as depicted in  FIG. 6 , with sensor  13  including porous insulating layer  12  attached to the inner walls thereof, or other enclosure, as depicted in  FIG. 7 , where the sensor  13  and porous layer  12  are attached directly to a wall. 
     Using the porous layer of the present invention as described herein allows a tamper respondent sensor to be disposed inside a protective outer casing around a sensitive electronic device to achieve suitable performance, which was heretofore unachievable. Also, for applications that require tamper respondent protection that have limited space and would require the tamper respondent sensor to be in close proximity to the enclosure, the tamper respondent system of the present invention provides the ability for the sensor to be in very close proximity to the surface of the enclosure, ensures electrical isolation between the sensor and the enclosure, and enables the outer enclosure to be used as an integral part of the security solution. 
     While particular embodiments of the present invention have been illustrated and described herein, the present invention should not be limited to such illustrations and descriptions. It should be apparent that changes and modifications may be incorporated and embodied as part of the present invention within the scope of the following claims.