Abstract:
A method and apparatus is disclosed for independently displaying one of a plurality of images on a display and for superimposing the plurality of images onto one another to produce a composite image. One or more bit planes are selected to constitute a group (defined to be a &#34;surface&#34;), and one or more additional bit planes are selected to constitute another group. The number of groups corresponds to the number of images to be independently displayed. The priority of one group over the other is selected. This ensures that the image from the one group (surface) appears to be &#34;in front of&#34; the images from the other group (surface) on the display. In the case of a color terminal, the colors associated with each group are selected. A color map memory contains a plurality of brightness indices which determines image brightness. Associated with each index is one or more color indices. The bits associated with each pixel are used as an index to the color map memory by locating the corresponding color (or gray) indices. The associated brightness index is noted, and converted to an analog voltage for determination of image brightness. In response to the selection of the groups mentioned hereinabove, and the designation of priority among groups, the firmware recomputes the color map in the color map memory, that is, the color indices are set based upon the number of selected groups and the number of bit planes per group, and selected ones of the brightness indices are recomputed based on the designated priority among groups. Due to the ability of the present invention to select one or more bit planes to constitute a group, and due to the firmware&#39;s ability to recompute the color map, one or more images can be displayed on the CRT, either independently of one another, or superimposed upon one another to produce a composite image.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a graphics display terminal&#39;s capability to provide a fill-pattern inside a redrawn panel outline to produce a redrawn panel image, the redrawn panel outline being generated on a display subsequent to generation of an original panel image having said fill pattern present therein. 
     2. Description of the Prior Art 
     Some of the graphics display terminals of the prior art possessed a panel-fill capability, wherein a fill-pattern was designated and a closed-boundary image, or panel, was drawn on the display of the terminal, the fill-pattern filling the space inside the panel. However, these graphics display terminals of the prior art did not possess a zoom capability, wherein a portion of the displayed panel image is magnified in order that the fine details of the displayed panel image may be studied and/or modified as desired. With the advent of the zoom capability for graphics display terminals, the user could, for example, zoom in on a portion of a displayed panel image including the fill-pattern filling the space inside the panel. When this zoom operation is performed on the displayed panel image, the displayed panel image is erased, and it is redrawn on the screen as a redrawn panel image. The zoom capability of the terminal redraws the zoomed outline of the panel image on the terminal display, resulting in a magnified panel outline. The panel fill capability of the terminal should determine which area, on both sides of the magnified panel outline, represents the area inside the panel outline, and which area represents the area outside the panel outline. However, the panel fill capability of the prior art graphics display terminals could not determine which area, on both sides of a magnified panel outline, represented the area inside the panel, and which area represented the area outside the panel. Consequently, since it was not known which area represented the area inside the panel, it was not possible to fill the zoomed panel outline with the predesignated fill pattern. 
     In addition, the graphics display terminals of the prior art did not possess a capability whereby a multiple number of viewports could be displayed on the terminal display, portions of the originally displayed panel image being displayed inside each of the viewports. The portions of the originally displayed image were sometimes subjected to a zoom operation, the zoomed portions of the originally displayed panel image being displayed in their corresponding viewports. However, again, with the advent of the ability to display these multiple viewports, if the multiple viewport capability was used in conjunction with a filled panel representing the originally displayed image, the terminal was capable of redrawing the outline of the panel in the viewport, but, in the case of an expanded panel outline, the terminal&#39;s original panel-fill feature was not capable of determining which area represented the area inside the panel, and which area represented the area outside the panel. 
     SUMMARY OF THE INVENTION 
     It is therefore a primary object of the present invention to provide a panel-fill capability for a graphics display terminal which is capable of determining which area, on both sides of a magnified panel outline, represents the area inside the panel, and which area represents the area outside the panel. 
     It is another object of the present invention to provide a panel fill capability for a graphics display terminal wherein a panel, having a fill-pattern drawn therein, may undergo a zoom operation, the zoomed outline of the panel being redrawn on the terminal display as a result of the zoom capability of the terminal, the panel fill capability determining which area on both sides of the zoomed outline represents the area inside the panel and which area represents the area outside the panel, the panel fill capability filling the area inside the panel with the predesignated fill-pattern. 
     These and other objects of the present invention are accomplished by providing a system including a processor connected to a keyboard and a host computer for performing a zoom operation on the original panel image, inclusive of its fill pattern, resulting in a zoomed panel image. The zoom operation magnifies the outline of the original panel image only. Therefore, there is an area inside the magnified boundary which does not contain the designated fill pattern. The processor also performs a panel fill operation wherein the area inside the magnified outline of the original panel image is determined, the fill-pattern being supplied to said area inside the magnified outline of the original panel image to complete the fill-pattern of the zoomed panel image. In response to the completion of the performance of these two operations, the processor supplies instructions to a vector generator, the instructions including CRT-vector generating information related to the zoom function and to the panel-fill function performed by the processor. The vector generator, in response to the instructions from the processor, generates binary data for each pixel of the terminal display, the binary data being representative of the zoomed panel image completely filled with the designated fill pattern. The binary data is stored in a memory, and is sequentially read out from the memory, pixel by pixel, until an entire corresponding terminal display area is encompassed. The binary data for each pixel thus read out from memory is converted to an analog voltage for determination of the image brightness for each pixel on the terminal display. 
     Further scope of applicability of the present invention will become apparent from the description given hereinafter. However, it should be understood that the details of the description of the specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     A full understanding of the present invention will be obtained from the detailed description given hereinbelow and the accompanying drawings, which are given by way of illustration only, and thus are not limitative of the present invention, and wherein: 
     FIG. 1 illustrates a plurality of panels, each panel having a different fill pattern therein. 
     FIG. 2a represents a panel having a fill pattern disposed therein before the panel has undergone a zoom operation, the panel and the fill pattern being stored in a memory in the form of a series of instructions. 
     FIG. 2b represents a portion of the panel shown in FIG. 2a after undergoing a zoom operation, this figure illustrating the manner by which the present invention determines which area, on both sides of the magnified panel outline, is inside the panel and which area is outside the panel. 
     FIG. 3 represents a system block diagram of the graphics display terminal of the present invention. 
     FIG. 4 represents a further detail of the video display memory shown in FIG. 3. 
     FIG. 5 represents a further detail of the video timing and control circuit shown in FIG. 3. 
     FIGS. 6A, 6B, and 6C represent a further detail of the vector generator shown in FIG. 3. 
     FIG. 7 is a data structure diagram of the scanline and edge lists. 
     FIG. 8 is a panel data structure I glossary. 
     FIG. 9 illustrates the various combinations of panel edges which may be encountered and the way the algorithms deal with them. 
     FIG. 10 is a pair of flow diagrams which show the interaction between several of the firmware modules of the present invention. 
     FIG. 11 is a flow diagram which shows the interaction between others of the firmware modules of the present invention. 
     FIG. 12 is a flow diagram which shows the interaction between others of the firmware modules of the present invention. 
     FIG. 13 is a data structure diagram which illustrates the structure of the pattern number list. 
     FIG. 14 is another data structure diagram showing the relationship between the siding pointer list and the edge list. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A full appreciation of the present invention will be obtained by reference to FIGS. 1, 2a, and 2b of the drawings. Referring to FIG. 1, a plurality of panels 10 are shown. For example, a typical panel would be panel 10a shown in FIG. 1. Panel 10b is still another panel. A &#34;panel&#34; is defined as being a closed-boundaried image. In the example shown in FIG. 1, each of the panels are defined by an outline which represents a pentagon figure. Note that each of the panels shown in FIG. 1 encompasses a different fill pattern. For example, panel 10a encompasses a cross-hatching fill pattern 10a1. The panel 10b encompasses a double cross-hatch fill pattern 10b1. 
     Some of the graphics display terminals of the prior art were capable of predesignating a fill pattern, and of drawing a closed boundary on the CRT (cathode ray tube) display, the predesignated fill pattern being drawn or written within the closed boundaried image. However, with the advent of a zoom capability for graphics display terminals, a problem arose during the zoom function when performing a zoom operation on a closed panel having a fill pattern encompassed therein. When the zoom operation was performed on said panel, a magnified panel outline would appear on the CRT screen. The panel-fill capability of the prior art terminals could not determine which area, on both sides of the magnified panel outline, represented the area inside the panel and which area represented the area outside the panel. 
     Referring to FIGS. 2a and 2b, the method of the present invention for determining which area is inside the magnified panel outline and which area is outside the magnified panel outline is illustrated. Referring to FIG. 2a, a panel outline 12 is shown having a fill pattern 14 disposed inside the panel. A frame box 16 is shown encompassing a portion of the panel 12, for the purpose of subjecting said portion of said panel 12 to the zoom operation. A cross-hair cursor 16A inside the frame box 16 is indicative of the center of the box 16. In FIG. 2b, said portion of said panel is shown after undergoing the zoom operation. In FIG. 2b, a lower left pixel 18 is shown in the lower left hand corner of frame box 16. If it is known, for example, that this lower left pixel 18 is inside the panel outline 12, it is possible to determine whether any other pixel in the frame box 16 is inside or outside the panel outline 12. Still referring to FIG. 2b, assuming that it is known that the lower left pixel 18 is inside the panel outline 12, if one were to scan from left to right, bottom to top, starting with the lower left pixel 18, the area between pixel 18 and outline 2 must be inside the panel outline 12. After the outline 12 is crossed during the scan, the area between the outline 12 and the lower right pixel must be outside the panel outline. On the return from right to left of the frame box 16, the outline is crossed once again, such that the area between outline 12 and the left side of frame box 12 is designated as being inside the panel outline 12. This scan technique continues from left to right, return from right to left, scanning from bottom to top of frame box 16 until the point 20 is encountered. The area between point 20 and outline 12 is still designated as being inside the panel outline 12. Continuing along this scan line, once the panel outline is crossed, the area between one portion of outline 12 and the next subsequent portion of outline 12 is designated as being outside the panel outline. When the panel outline is again crossed, along this scan line, the area between the outline 12 and the next subsequent outline portion 12 is inside the panel. When the panel outline is again crossed, along this scan line, the area between outline 12 and the right portion of frame box 16 is designated as being outside the panel. The return from right to left, along this scan line, is accomplished in the same manner as hereinbefore described, until point 20 is again encountered. 
     The scan moves up one pixel width to the next pixel above point 20. When this occurs, the area between the left side of frame box 16 and the outline 12 is designated as being outside, not inside, the panel. Once point 20, on the left side of frame box 16, is encountered, and passed, during the scan from bottom to top of frame box 16, the inside-outside status of the panel changes, in this case, from an &#34;inside the panel&#34; status, to an &#34;outside the panel&#34; status. The scan from left to right and return, is accomplished, and the inside-outside status of the pixels along the scan line is determined in exactly the same manner as hereinbefore described, only the starting status at the left portion of frame box 16 is an &#34;outside the panel&#34; status. Scan lines appear in FIG. 2b, and above each of the scan lines, an &#34;i&#34; or an &#34;o&#34; appears, indicating whether the pixels along the scan line are &#34;inside the panel&#34; or &#34;outside the panel&#34;, respectively. 
     The text presented hereinabove assumed that the status of the lower left pixel 18 was known to be &#34;inside the panel&#34;. How this fact was initially determined is presented in the paragraphs to follow. 
     Referring to FIG. 2a, a filled panel is shown, having outline 12, and a fill pattern 14 disposed therein, the panel being disposed in a universal space U. A horizontal line 22 connects the lower left pixel 18, within frame box 16, to a left-most point outside the universal space U, such as--∞. Starting from the left most outline of the universal space U, and proceeding from left to right along the line 22, the area between the left-most outline of the universal space U and the outline 12 of the panel is considered to be outside the panel. When the outline 12 is first encountered and crossed, along line 22, the area between the first crossing 24 and the second crossing 26 of outline 12 is considered to be inside the panel. The area between the second 26 and a third 28 crossing is considered to be outside the panel. Therefore, the area between the third crossing 28 and pixel 18 is considered to be inside the panel outline 12. Consequently, pixel 18 must be inside the panel outline 12. 
     The above paragraphs have described, with reference to FIGS. 2a and 2b, that it is possible to perform a zoom operation on a filled panel image and to determine which area, on both sides of the panel outline, is considered to be inside the panel outline, and which area is considered to be outside the panel outline. 
     When the panel image undergoes the zoom operation, the outline of the panel is magnified by a certain factor. At this point, the areas inside the panel outline are determined. Then, the fill pattern is supplied to those areas which were designated as being inside the magnified panel outline. 
     A detailed description of the zoom capability mentioned hereinabove for the graphics display terminal of the present invention is provided in a co-pending application entitled &#34;True Zoom of a Displayed Image&#34; filed on Apr. 12, 1982, by the same inventor as the present application and was assigned a Ser. No. of 367,829 is hereby incorporated by reference. 
     Referring to FIG. 3, a system block diagram of the graphics display terminal of the present invention is illustrated. The keyboard 30, and the host computer 32 are connected to a processor 34. The processor 34 includes a microprocessor and a ROM connected thereto. The keyboard 30 and the host computer 32 are connected to the microprocessor. An Intel 8086 can be used to perform the function of the microprocessor. The firmware is stored in the ROM. The microprocessor is connected to a processor bus. A memory 36 is also connected to the processor bus and stores a series of bits therein, referred to as a surface information index, associated with another capability of the graphics display terminal of the present invention. This other capability of the graphics display terminal of the present invention, inclusive of the concept behind the surface information index, is discussed in another co-pending application entitled &#34;Method and Apparatus for Displaying Images&#34;, assigned to the same assignee as the present invention, this co-pending application having been filed in the name of Paula Mossaides on Apr. 12, 1982, and assigned a Ser. No. of 367,659, the disclosure of which is hereby incorporated by reference. 
     A video display memory 38 is connected to the processor bus and stores therein the pixel data which is ultimately used for controlling the image brightness during the raster scan. A vector generator 40 is connected to the processor bus and generates the pixel data in response to instructions from the microprocessor in the processor 34, the pixel data being stored in the video display memory 38. A video timing and control circuit 42 is also connected to the processor bus and coordinates the readout of the pixel data stored in the video display memory 38 with the generation of the horizontal and vertical sync signals, generated by a deflection circuit 44. The video display memory 38 is also connected to a color map memory 46, the color map memory 46 being connected to the CRT via a D-A converter 48. When the pixel data, for each pixel on the CRT, is read out from the video display memory 38 by the video timing and control circuit 42, it is used as an index (or address) to a table stored in the color map memory 46. A corresponding brightness index is located in the table, corresponding to the pixel data, for each pixel, located therein, and is converted to an analog voltage in the D-A converter 48. The analog voltage drives an electron gun and determines the brightness of the image displayed at that particular pixel. The detailed concepts behind the construction of the color map memory, and the associated brightness indices stored therein, are discussed in the copending application entitled &#34;Method and Apparatus for Displaying Images&#34;, filed on Apr. 12, 1982, and assigned a Ser. No. of 367,659, the disclosure of which has already been incorporated by reference hereinabove. 
     A further detail of the video display memory 38 is shown in FIG. 4 of the drawings of the present application. In FIG. 4, the video display memory 38 comprises a plurality of ALU control circuits 38a and a plurality of bit planes connected thereto. Each of the ALU control circuits are nothing more than a register capable of being set to a 1 or a 0 in response to a high or a low input signal, respectively. If a bit in an ALU register is set to 1, an output signal is developed therefrom. 
     The output terminals of the ALU control circuit 38a are connected to a corresponding plurality of bit planes. Each of the bit planes comprise a certain number of RAM/data logic circuits 38b, a RAM control circuit 38c, and a shift register 38d. In the example shown in FIG. 4, there are twenty (20) RAM/data logic circuits 38b in each bit plane. Each line on the CRT is subdivided into a plurality of groups of pixels, each group including twenty (20) pixels, corresponding to the twenty (20) RAM/data logic circuits 38b. Four bit planes are illustrated in the FIG. 3 circuit embodiment. 
     Each RAM control circuit 38c, associated with each bit plane, is connected, on one end, to a RAM/data logic circuit 38b. Each RAM control circuits 38c is connected, on the other end, to the video timing and control circuit 42 of FIG. 3 and is therefore responsive to the output signals generated therefrom. The outputs of each of the RAM/data logic circuits 38b in each bit plane are connected to a shift register 38d. In response to instructions from the video timing and control circuit 42, the RAM control circuits 38c read out the pixel data from their corresponding RAM/data logic circuits 38b, the pixel data being stored in their corresponding shift registers 38d. 
     Since there are four bit planes illustrated in the FIG. 3 circuit embodiment, there are four respective RAM control circuits 38c, four sets of RAM/data logic circuits 38b connected to the RAM control circuits 38c, each set including 20 RAM/data logic circuits, and four respective shift register circuits 38d connected to the output of the four respective sets of RAM/data logic circuits 38b. 
     The output of each of the shift registers 38d is connected to the color map memory 46 of FIG. 3. The output of the color map memory 46 is connected to a D-A converter 48, which is, in turn, connected to the electron guns of the cathode ray tube (CRT). Pixel data is supplied to each of the bit planes from the vector generator 40, of FIG. 3, which receives its information from the processor 34. Processor 34 receives its instructions from the keyboard 30 or the host computer 32. 
     The surface information index 50 shown in FIG. 4 is a combination of bits which are stored in memory 36 of FIG. 3. This combination of bits is created in response to actuation of certain keys on keyboard 30 wherein certain ones of the bit planes shown in FIG. 4 are selected to constitute a &#34;surface&#34;. A bit plane is selected as part of the &#34;surface&#34; in response to a binary digit &#34;1&#34; present in the corresponding digit position of the surface information index 50. In the example shown in FIG. 4, the first two bit planes are selected to constitute a &#34;surface&#34;, the last two bit planes not being selected to constitute the &#34;surface&#34;. Each &#34;surface&#34; is responsible for generating an image on the cathode ray tube. If two &#34;surfaces&#34; are selected, two images will be displayed on the CRT, each image capable of being displayed independently of one another or superimposed upon one another to create a composite image. The details surrounding the selection of the appropriate &#34;surfaces&#34;, and the generation of their images in response thereto, on the CRT, are discussed in the above-mentioned co-pending application entitled &#34;Method and Apparatus for Displaying Images&#34;, filed on Apr. 12, 1982, and assigned a Ser. No. of 367,659, the disclosure of which has already been incorporated by reference hereinabove. 
     The host computer 32, in the keyboard 30, send instructions to the processor 34 which describe the original panel image, having the fill pattern disposed therein. The processor stores these instructions and thereby the original filled panel image, in memory 36. The memory 36 represents the universal space &#34;U&#34; shown in FIG. 2a of the drawings, and the panel outline shown in FIG. 2a represents the instructions stored in memory 36. 
     In operation, and referring to FIG. 3. In response to instructions from the host computer, and in accordance with the firmware stored in the ROM of the processor 34, the processor 34 retrieves the instructions from memory 36 (which describe the panel image), and issues certain commands therefrom, which are directed to the vector generator 40. The vector generator 40, in response thereto, develops certain output signals representing digital data to be stored in the video display memory 38, this digital data, stored in the video display memory 38, constituting the pixel representation of the original filled panel image. Once this digital data is stored in the video display memory 38, the video timing and control circuit 42 develops certain output signals, which are directed to the RAM control circuit 38c, in FIG. 4, for reading the pixel data from the video display memory 38. The video timing and control circuit 42 coordinates the read-out of this pixel data from the video display memory 38 with the development of the horizontal and vertical sync signals from the deflection circuit 44. 
     Referring to FIG. 4, a further functional description of the operation of the present invention is described, particularly with reference to the construction of the video display memory 38 of FIG. 3. The digital data developed by the vector generator 40 is stored in the RAM/data logic circuits 38b. As discussed hereinabove, if the first two bit planes are designated as being a &#34;surface&#34;, an image is displayed on the CRT associated with these bit planes. If the last two bit planes are separately designated as constituting another &#34;surface&#34;, two images may be independently displayed on the CRT, or superimposed upon one another to produce a composite image. The details of the generation of these multiple images are discussed in the co-pending application mentioned hereinabove entitled &#34;Method and Apparatus for Displaying Images&#34;, filed on Apr. 12, 1982, and assigned a Ser. No. of 367,659, already incorporated by reference. 
     The video timing and control circuit 42 of FIG. 3 directs the RAM control circuit 38c to read the digital data (i.e., the pixel data) out from the corresponding RAM/data logic circuits 38b. The digital data from each bit plane is read therefrom, simultaneously, in parallel fashion and stored in its corresponding shift register 38d. In the example of FIG. 4, the digital data stored in the first two bit planes is read from the corresponding two sets of RAM/data logic circuits 38b, the digital data being stored in the corresponding two shift registers 38d. The digital data in the shift registers 38d is sequentially shifted out therefrom in serial fashion, and located as an index (i.e., an address) to a table stored in the color map memory 46. A brightness index is located in the color map memory 46, corresponding to the digital data shifted out from the corresponding two shift registers 38d, the brightness index determining the brightness of the image displayed on the CRT. The brightness index is converted into an analog voltage via the D-A converter 48, the analog voltage energizing electron guns for determining the brightness of the image displayed on the CRT at the particular pixel point. 
     The resultant image displayed on the CRT is the original filled panel image, for example, the picture of the panels shown in FIG. 1 of the drawings. 
     If, in response to an actuation of a &#34;zoom&#34; key on the keyboard 30, the operator desires to perform the zoom operation, a frame box (not shown in the drawings) will appear on the CRT screen. The frame box will be stored in memory 36 in the form of further instructions stored therein. These instructions originated from the keyboard 30 where the operator actuated the &#34;zoom&#34; key. The processor 34, in response to actuation of the &#34;zoom&#34; key on the keyboard 30, will retrieve the further instructions from memory 36, and, in response thereto, will instruct the vector generator 40 to generate the appropriate digital data for storage in the video display memory 38, for further generation of the frame box on the CRT. By operating the thumb wheels on the keyboard 30, the length and width dimensions of the frame box can be altered accordingly. By operating the thumb wheels to shorten the dimensions of the frame box, the processor 34, instructs the vector generator 40 to supply the appropriate digital data to the video display memory 38 for storage therein. This appropriate digital data now reflects the shortened frame box, along its length and width dimension thereof. 
     The digital data stored in the video display memory 38, which reflects the shortened frame box, along the length and width dimension thereof, is used as an index to a table stored in the color map memory 46. The table in the color map memory 46 includes a plurality of brightness indices which determine the brightness of the display on the CRT. The digital data from the video display memory 38 is used as the index to the table in the color map memory 46 to locate the corresponding brightness index. The brightness index is converted to an analog voltage via a D-A converter 48, the analog voltage determining the brightness of the displayed image on the CRT. The frame box will then appear on the CRT as part of the &#34;displayed image&#34;, in addition to the original filled panel image. 
     When the operator actuates the &#34;pan&#34; key on the keyboard 30, the length and width dimensions of the frame box are set. The frame box 16 shown in FIG. 2a will appear on the CRT screen. Actuation of the &#34;pan&#34; key on the keyboard will also position a cross-hair cursor 16a in the center of the frame box 16, thus resulting in the frame box 16 shown in FIG. 2a. The generation of the frame box 16 shown in FIG. 2a, along with its cross-hair cursor 16a, is accomplished in the same manner as described hereinbefore. The memory 36 stores the frame box 16 therein, in the universal space &#34;U&#34; (of FIG. 2a), in the form of instructions stored therein. The processor 34, in response to actuations of the keys on the keyboard 30, will retrieve these instructions from the memory 36, and will instruct the vector generator 40 to generate the appropriate digital data for storage in the video display memory 38 in response thereto. The digital data stored in the video display memory 38 is used as an index to a table in the color map memory 46, for further determination of the brightness indices corresponding thereto. As mentioned hereinbefore, the brightness indices determine the brightness of the image displayed on the CRT. The located brightness indices are converted to an analog voltage via a D-A converter 48, the analog voltage energizing one or more electron guns to generate the image on the CRT and to determine the brightness of said image. 
     In response to actuation of the &#34;view&#34; key on the keyboard 30, the filled panel image shown in the frame box 16 of FIG. 2a undergoes a zoom operation. The image is magnified by a particular factor, the magnified image being shown in FIG. 2b. Referring to FIG. 3 of the drawings, when the &#34;view&#34; key on the keyboard 30 is actuated, the firmware stored in the ROM of processor 34, associated with the terminals zoom capability, accomplishes the magnification of the image being input thereto from the host computer. The processor 34 instructs the vector generator 40 to develop the appropriate digital data for storage in the video display memory 38, this appropriate digital data stored therein representing the expanded outline 12 of the filled panel shown in FIG. 2a. Since the firmware accomplishes the magnification of the image prior to instructing the vector generator to develop the appropriate digital data for storage in the video display memory 38, the width of the lines, which comprise the expanded outline 12 is approximately equal to the width of the lines which comprise the outline of the filled panel image. FIG. 2b illustrates the expanded outline 12, which is represented by the digital data stored in the video display memory 38. As mentioned hereinabove, the panel outline 12 of FIG. 2a is expanded by virtue of the firmware stored in the processor 34, associated with the terminals zoom capability. This digital data, stored in the video display memory 38, is again used as an index to the table in the color map memory 46 for further determination of their associated brightness indices. These associated brightness indices are converted into an analog voltage via the D-A converter 48, the analog voltage determining the brightness of the image displayed on the CRT. 
     However, in addition, when the &#34;view&#34; key is actuated, the firmware stored in the processor 34, associated with the terminals &#34;panel-fill&#34; capability, is responsible for determining which areas, on both sides of the panel outline, are inside the panel, and for completing the fill-pattern in those areas which are inside the panel outline. The filled zoomed panel image shown in FIG. 2b of the drawings, is the result. Note that all of the internal areas are completely filled with their corresponding fill-patterns. This function is accomplished by the firmware in the ROM of processor 34, in conjunction with the circuitry shown in FIGS. 3 and 4 of the drawings, in the manner hereinbefore described in the above paragraphs with reference to FIGS. 2a and 2b, wherein the lower left pixel 18 in the frame box 16 of FIG. 2a is determined to be inside or outside the panel outline 12, and, knowing the status of this pixel, the zoomed outline in the frame box 16 in FIG. 2b is scanned by the firmware in the ROM of processor 34 from left to right, bottom to top, the inside/outside status changing when the image outline 12 is crossed during the scan. 
     Referring to FIG. 4, a further functional description of the operation of the video display memory 38 in the circuitry of FIG. 3 will be provided hereinbelow. 
     As stated in the above paragraphs, the processor 34 performs the function of expanding the outline of the panel image, determining which areas on both sides of the outline are inside or outside the outline, and completing the fill-pattern in those areas which are inside the panel outline prior to generation of instructions therefrom which are directed to the vector generator 40. The vector generator 40 generates the binary, digital data, the pixel data, for storage in the video display memory 38. 
     In FIG. 4, the video display memory 38 includes the RAM control circuits 38c, their associated RAM/data logic circuits 38b, and their corresponding shift registers 38d. The ALU control circuits 38a, shown in FIG. 4, energize one or more of the bit planes shown in FIG. 4, each bit plane comprising one shift register 38d, one set of twenty (20) RAM/data logic circuits 20b, and one RAM control circuit 38c. As shown in FIG. 4, the first two bit planes are enabled in response to the energization thereof by their corresponding ALU control circuits 38a. An ALU control circuit energizes its corresponding bit plane in response to a binary digit &#34;1&#34; present in the surface information index 50. This surface information index is discussed in the pending application entitled &#34;Method and Apparatus for Displaying Images,&#34;  already incorporated by reference hereinabove. 
     If the first two bit planes shown in FIG. 4 are enabled, the vector generator 40 will store binary data in each of these first two bit planes representative of the zoomed, filled panel image of FIG. 2b. Since the last two bit planes shown in FIG. 4 are not enabled, binary data will not be stored in these bit planes. The binary data, stored in the first two bit planes of FIG. 4, is stored in the corresponding sets of RAM/data logic circuits 38b. Once the binary data is stored therein, the video timing and control circuit 42 causes the RAM control circuit 38c, associated with these bit planes, to read the corresponding binary data therefrom in parallel fashion, for storage in their corresponding two shift registers 38d. The corresponding shift registers 38d, sequentially in serial fashion, shift the binary data out therefrom, the shifted data being used as an index to a table stored in the color map memory 46. For each shifted piece of binary data, shifted out from the shift register 38d, a corresponding brightness index is associated therewith. The corresponding brightness index is converted to an analog voltage via the D-A converter 48, the analog voltage energizing one or more electron guns and is responsible for generation of the brightness of the image at the pixel point on the CRT. A further detailed discussion of the construction and operation of the RAM/data logic circuits 38b is presented in the copending application mentioned hereinabove, entitled &#34;Method and Apparatus for Displaying Images&#34;, filed on Apr. 12, 1982, and assigned a Ser. No. of 367,659, already incorporated by reference. 
     The firmware, stored in the ROM of processor 34, is characterized by an algorithm. The algorithm includes two parts: the first part represents the zoom algorithm and the panel fill algorithm; the second part represents definitions of the undefined terms present in the algorithm of the first part. 
     Appendix A, attached hereto, provides the definitions of the undefined terms present in the algorithm of the first part. 
     Appendix B1 provides the zoom algorithm. 
     Appendix B2 provides the panel-fill algorithm. ##SPC1## ##SPC2## ##SPC3## ##SPC4## ##SPC5## ##SPC6## ##SPC7## ##SPC8## ##SPC9## ##SPC10## ##SPC11## ##SPC12## ##SPC13## 
     The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.