Abstract:
A magnetic random access memory with perpendicular magnetization comprising a selection transistor with a gate width, that is formed on a substrate and is electrically connected to a word line; a plurality of memory layers sequentially disposed above the substrate, wherein each of the plurality of the memory layers includes a plurality of magnetoresistive elements with perpendicular magnetization and wherein each of the plurality of the magnetoresistive elements comprises an element width and includes at least a pinned layer comprising a fixed magnetization, a free layer comprising a changeable magnetization, and a tunnel barrier layer residing between the pinned layer and the free layer; a plurality of conductor layers disposed alternately with the memory layers beginning with the memory layer positioned adjacent to the substrate, wherein each of the plurality of the conductor layers comprises a plurality of parallel bit lines intersecting the word line, and wherein the bit line is disposed adjacent to the free layer and is electrically connected with the magnetoresistive element; wherein the gate width is substantially larger than the element width, and wherein the magnetoresistive elements of the memory layer are electrically connected in parallel to the selection transistor.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This invention claims benefit of U.S. Provisional Patent Application No. 61/227,364 entitled “3D Magnetic Random Access Memory with High Speed Writing” filed Jul. 21, 2009, which is hereby incorporated by reference in its entirety. 
     
    
     FEDERALLY SPONSORED RESEARCH 
       [0002]    Not Applicable 
       SEQUENCE LISTING OR PROGRAM 
       [0003]    Not Applicable 
       FIELD OF THE INVENTION 
       [0004]    The present invention relates to a magnetic random access memory (MRAM) and, more specifically, to a perpendicular MRAM with high-speed writing that can be arranged in a three-dimensional architecture. 
       BACKGROUND OF THE INVENTION 
       [0005]    Magnetic random access memory (MRAM) is a new memory technology that will likely provide a superior performance over existing semiconductor memories including flash memory and may even replace hard disk drives in certain applications requiring a compact non-volatile memory device. In MRAM bit of data is represented by a magnetic configuration of a small volume of ferromagnetic material and its magnetic state that can be measured during a read-back operation. The MRAM typically includes a two-dimensional array of memory cells wherein each cell comprises one magnetic tunnel junction (MTJ) element that can store at least one bit of data, one selection transistor (T) and intersecting conductor lines (so-called 1T-1MTJ design). 
         [0006]    Conventional MTJ element represents a patterned thin film multilayer that includes at least a pinned magnetic layer and a free magnetic layer separated from each other by a thin tunnel barrier layer. The free layer has two stable orientations of magnetization that are parallel or anti-parallel to the fixed orientation of magnetization in the pinned layer. Resistance of the MTJ depends on the mutual orientation of the magnetizations in the free and pinned layers and can be effectively measured. A resistance difference between the parallel and anti-parallel states of the MTJ can exceed 600% at room temperature. 
         [0007]    The orientation of the magnetization in the free layer may be changed from parallel to anti-parallel or vice-versa by applying two orthogonal magnetic fields to the selected MTJ, by passing a spin-polarized current through the selected junction in a direction perpendicular to the junction plane, or by using a hybrid switching mechanism that assumes a simultaneous application of the external magnetic field and spin-polarized current to the selected MTJ. The hybrid switching mechanism looks the most attractive among all others since it can provide good cell selectivity in the array, relatively low switching current and high write speed. 
         [0008]      FIGS. 1A and 1B  show a schematic cross-sectional and top down views of MRAM cell  10  employing the hybrid switching mechanism according to a prior art disclosed in U.S. Pat. No. 7,006,375 (Covington). The cross-section was taken alone the line  1 A- 1 A shown in the  FIG. 1B . The memory cell  10  includes a semiconductor wafer  11  with a selection transistor  12 , MTJ element  21 , a word line  16  and a bit line  19  that are orthogonal to each other (1T-1MTJ design). The bit line  19  and the MTJ element  21  are connected in series to the source region  13  of the selection transistor  12 . The MTJ element  21  includes a pinned magnetic layer  22  with a fixed in-plane magnetization (shown by an arrow), a free magnetic layer  23  with a changeable in-plane magnetization (shown by arrows), a thin tunnel barrier layer  24  positioned between the free  23  and pinned  22  layers, and a pinning anti-ferromagnetic layer  25  exchange coupled with the pinned layer  22 . The MTJ element  21  has an elliptical shape with a major axis of the ellipse being oriented in parallel to the word line  19 . The easy magnetic axis of the pinned and free layers coincides with the major axis. The transistor  12  comprises a gate  15  of a width W=2F, where F is a width of the MTJ element  21 . The drain region  14  of the transistor  12  is connected to the ground line  18  through a contact plug  17 . 
         [0009]    To write a data to the MTJ element  21 , a bias electric current I B  is applied to the bit line  19 . The current I B  induces a magnetic bias field H B  that affects the free layer  23  along its hard magnetic axis. The field H B  forces the magnetization in the free layer  23  from its equilibrium state that is parallel to the major axis of the MTJ element  21 . By applying a voltage to the gate  15  through the word line  16  the selection transistor  12  can be turned on. The transistor  12  delivers a spin-polarized current I S  to the MTJ element  21 . The current I S  running through the element  21  produces a spin momentum transfer that together with the bias field H B  provides a reversal of magnetization in the free layer  23 . The orientation of magnetization in the free layer  23  is controlled by a direction of the spin-polarized current I S . Magnitude of the spin-polarized current I S  required to reverse the magnetization in the free layer  23  depends on the strength of the bias field H B  that tilts the orientation of magnetization in the free layers relatively its equilibrium state. The switching current I S  can be reduced more than twice by a relatively small bias magnetic field H B . 
         [0010]    The MTJ with in-plane magnetization requires a high magnitude of the switching current I S  even with applied magnetic bias field H B . Magnitude of the spin-polarized current I S  defines a write speed of the memory cell; the speed increases with the current. The spin-polarized current I S  of the cell  10  is limited by a saturation current of the transistor  12  that is proportional to a gate width W. The selection transistor  12  has the gate width W=2F, where F is a width of the elliptical MTJ element  21 . This gate width is incapable to deliver the required magnitude of the current I S . To overcome the above obstacles the gate width W of the transistor  12  needs to be substantially increased. However that will result in considerable increase of memory cell size and in MRAM density reduction. 
         [0011]    Majority of the current MRAM designs uses the free and pinned layers made of magnetic materials with in-plane anisotropy. The in-plane MRAM (i-MRAM) suffers from a large cell size, low thermal stability, poor scalability, necessity to use MTJ with a special elliptical shape, and from other issues, which substantially limit a possibility of i-MRAM application at technology nodes below 90 nm. 
         [0012]    MRAM with a perpendicular orientation of magnetization in the free and pinned layers (p-MRAM) does not suffer from the above problems since perpendicular magnetic materials have a high intrinsic crystalline anisotropy. The high anisotropy provides p-MRAM with the excellent thermal stability and scalability, and with a possibility to use junctions of any shape. Nevertheless the existing p-MRAM designs have a large cell size and require a high switching current. 
         [0013]    What is needed is a simple design of p-MRAM having high switching speed at low current, small cell size, high capacity and excellent scalability. 
       SUMMARY OF THE INVENTION 
       [0014]    The present invention provides a three-dimensional magnetic random access memory (3D-MRAM) with a perpendicular magnetization for high-speed writing. 
         [0015]    A magnetic random access memory according to an aspect of the present invention comprises a selection transistor comprising a gate width, the selection transistor is formed on a substrate and is electrically connected to a word line; a plurality of memory layers sequentially disposed above the substrate, wherein each of the plurality of the memory layers includes a plurality of magnetoresistive elements and wherein each of the plurality of the magnetoresistive elements comprises an element width and includes at least a pinned layer comprising a fixed magnetization oriented substantially perpendicular to a layer plane, a free layer comprising a changeable magnetization oriented substantially perpendicular to a layer plane in its equilibrium state, and a tunnel barrier layer residing between the pinned layer and the free layer; a plurality of conductor layers disposed alternately with the memory layers beginning with the memory layer positioned adjacent to the substrate, wherein each of the plurality of the conductor layers comprises a plurality of parallel bit lines intersecting the word line, and wherein the bit line is disposed adjacent to the free layer and is electrically connected with the magnetoresistive element; wherein the gate width is substantially larger than the element width, and wherein the magnetoresistive elements of the memory layer are electrically connected in parallel to the selection transistor. 
         [0016]    A method of writing to a magnetic random access memory according to another aspect of the present invention comprises: providing a selection transistor disposed on a substrate and comprising a gate width; a word line connected to the selection transistor; a plurality of memory layers disposed above the substrate and comprising a plurality of magnetoresistive elements, wherein each of the plurality of the magnetoresistive elements comprises an element width and includes at least: a pinned layer with a fixed magnetization oriented perpendicular to a layer plane, a free layer with a changeable magnetization oriented perpendicular to a layer plane in its equilibrium state, and tunnel barrier layer residing between the pinned and free layers; a plurality of conductor layers comprising pluralities of parallel bit lines intersecting the word line, wherein the adjacent conductor layers are spaced from each other by the memory layer; and wherein the magnetoresistive elements are electrically connected in parallel to the selection transistor and the gate width is substantially larger than the element width; driving a bias current pulse through the bit line in a proximity to but not through the magnetoresistive element and producing a bias magnetic field along a hard magnetic axis of both the pinned layer and the free layer; driving a spin-polarized current pulse through the magnetoresistive element along an easy axis of both the pinned layer and the free layer and producing a spin momentum transfer; whereby the magnetization in the free layer will be switched by a collective effect of the substantially superimposed pulses of the bias and spin-polarized currents. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]      FIG. 1A  illustrates a schematic cross-section view of MRAM cell with in-plane magnetization in free and pinned layers employing a hybrid write mechanism according to a prior art. 
           [0018]      FIG. 1B  is a schematic top-down view of a MRAM cell of  FIG. 1A . 
           [0019]      FIG. 2A  is a schematic cross-sectional view of perpendicular MRAM cell with a hybrid write mechanism according to an embodiment of the present invention. 
           [0020]      FIG. 2B  is a schematic top-down view of the perpendicular MRAM cell of  FIG. 2 . 
           [0021]      FIG. 3  is a schematic view of perpendicular MRAM cell with a bilayer structure of free and pinned layers according to another embodiment of the present invention. 
           [0022]      FIG. 4A  is a schematic top-down view of two adjacent MRAM cells according to yet another embodiment of the present invention. 
           [0023]      FIG. 4B  is schematic cross-sectional view of two adjacent MRAM cells of  FIG. 4A . 
           [0024]      FIG. 5  is a schematic cross-sectional view of a three dimensional perpendicular MRAM with two memory layers according to yet another embodiment of the present invention. 
           [0025]      FIG. 6  is a circuit diagram of a three dimensional MRAM cell with magnetoresistive elements of different memory layers connected in parallel with a selection transistor according to still another embodiment of the present invention. 
           [0026]      FIG. 7  is a circuit diagram of a three dimensional MRAM cell with overlaying magnetoresistive elements of different memory layers connected in series between each other and in parallel as series with a selection transistor according to still another embodiment of the present invention. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0027]    In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings that form a part hereof, and in which are shown be way of illustration specific embodiments in which the invention may be practiced. It is understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention. 
         [0028]    The leading digits of reference numbers appearing in the Figures generally corresponds to the Figure number in which that component is first introduced, such that the same reference number is used throughout to refer to an identical component which appears in multiple Figures. 
         [0029]      FIG. 2A  show schematic cross-sectional view of memory cell  20  according to an embodiment of the present invention. The cross-section is taken along line  2 A- 2 A that is shown in the  FIG. 2B . The memory cell  20  comprises a semiconductor substrate  11  with a selection transistor  12 , a MTJ (or magnetoresistive) element  21 , a word line  16  and a bit line  19 ; the lines  16  and  19  intersect each other. The MTJ element  21  comprises a pinned layer  22  with a fixed magnetization (shown by an arrow) oriented substantially perpendicular to a layer plane, a free layer  23  with a changeable magnetization (shown by two arrows) oriented substantially perpendicular to a layer plane in its equilibrium state, a tunnel barrier layer  24  sandwiched between the pinned  22  and free  23  layers, a seed layer  26  and a cap layer  27 . The free layer  23  has two stable orientations of magnetization in its equilibrium state: up or down. The MTJ element  21  is electrically connected to the bit line  19  and to the source region  13  of the transistor  12  through a contact plug  17 . The word line  16  is connected to the gate region  15  through an insulator layer (not shown). The memory cell  20  comprises two MTJ elements  21 - 1  and  21 - 2 , and two parallel bit lines  19 - 1  and  19 - 2 , wherein the MTJ element  21 - 1  is electrically connected to the line  19 - 1  and the MTJ element  21 - 2  is connected to the line  19 - 2 , both the MTJ elements are connected in parallel to the source  13  of the transistor  12  through the contact plug  17 . The transistor  12  has a footprint size similar to the size of the cell  20  (shown by a dash-dot line) and the gate width W=4F, where F is a diameter of the MTJ elements. The large gate width W provides the transistor  12  with a high saturation current, which is important for high-speed writing. 
         [0030]    The memory cell  20  has a 1T-2MTJ (one transistor-two MTJs) design. Number of the MTJ elements in the cell  20  can be any. Each MTJ element of the memory cell  20  has a unique combination of the bit and word lines that provides its selection in the MRAM array. For instance, to write data to the MTJ element  21 - 1  the bias current I B  needs to be run in the bit line  19 - 1  and the spin-polarized current I S  should run through the element in direction perpendicular to its plane. The spin-polarized current I S  is controlled by the word line  16  that intersects the bit line  19 - 1  in vicinity of the MTJ element  21 - 1 . Combined effect of the bias I B  and spin-polarized I S  currents will reverse the magnetization in the free layer  23  of the element  21 - 1 . 
         [0031]    In some embodiments of the present invention the MTJ element  21  has multilayer structure of the pinned  22  and free  23  layers. The  FIG. 3  illustrates a memory cell  30  according to another embodiment of the present with bilayer structure of the pinned  22  and free  23  layers. The free layer  23  comprises a storage layer  34  having a perpendicular anisotropy and a first coercivity, and a soft magnetic underlayer  32  having a second coercivity. The soft magnetic underlayer  32  is disposed between the tunnel barrier layer  24  and the storage layer  34  and is substantially magnetically coupled to the storage layer  34 . The coercivity of the storage layer  34  is significantly higher than the coercivity of the soft magnetic underlayer  32 . The pinned layer  22  comprises the reference layer  38  with a perpendicular anisotropy and a third coercivity, and a spin-polarizing layer  37  with a fourth coercivity. The coercivity of the reference layer  38  is substantially higher than the coercivity of the storage layer  34 . The spin-polarizing layer  37  is disposed between the tunnel barrier layer  24  and the reference layer  38  and is substantially magnetically coupled to the reference layer  38 . The soft magnetic underlayer  32  can be made of a soft magnetic material with perpendicular or in-plane crystalline anisotropy. However due to a strong magnetic coupling to the storage layer  34  the orientation of magnetization in the soft magnetic underlayer  32  maintains perpendicular to layer plane in its equilibrium state. 
         [0032]    Pulse of the bias current I B  running in the bit line  19  induces a bias magnetic field H B  that is applied to the free layer  23  along its hard axis lying in the layer plane. The field H B  tilts the magnetization M 32  in the soft magnetic underlayer  32  on the angle Θ 32  but does not change the orientation of magnetizations M 22  and M 34  in the pinned  22  and storage  34  layers, respectively. The angle Θ 32  depends on the bias current magnitude, on thickness and magnetic properties of the soft magnetic underlayer  32  and the storage layer  34 , and on the strength of the magnetic coupling between them. Tilting of the magnetization M 32  in the soft magnetic underlayer  32  provides a significant reduction of the magnitude of spin-polarized current pulse I S  that is required to the reverse the magnetization in the storage layer  34 . The spin-polarizing layer  37  offers a high spin polarization of the switching current that is also important for reduction of I S  magnitude. The material of the spin-polarizing layer can have perpendicular or in-plane anisotropy. The orientation of magnetization in the spin-polarized layer  37  does not change under the bias field H B  due to its strong magnetic coupling with the reference layer  38 . The magnetizations in the soft-magnetic underlayer  32  and in the spin-polarizing layer  37  are substantially collinear (parallel or anti-parallel) in the equilibrium state. That is important for providing a high output signal during read operation. The saturation current of the transistor  12  does not limit the magnitude of the spin-polarized current I S  since the transistor has a large gate width W. At the same time, the bias field H B  offers a significant reduction of the spin-polarized current I S  and an additional opportunity of the write speed increase. 
         [0033]      FIGS. 4A and 4B  illustrate two memory cells  40  according to yet another embodiment of the present invention wherein one of the cells is shown by a dash-dot line. The cells have a common ground line  18  connected to the common drain region  14  of two selection transistors  12 . Footprints of the selection transistor  12  and the memory cell  40  coincide. The cells  40  have 1T-4MTJ design with four MTJ elements  21 - 1 ,  21 - 2 ,  21 - 3  and  21 - 4 , and four parallel bit lines  19 - 1 ,  19 - 2 ,  19 - 3  and  19 - 4  connected to the appropriate elements. All MTJ elements of the memory cells  40  are connected in parallel with the source region  13  of the proper transistor  12  through the contact plug  17 . Selection of MTJ element in the MRAM array is provided by unique combination of bit and word lines intersecting at the MTJ location. The transistors  12  have a gate width W=8F and can deliver a considerable spin-polarized current to the MTJ elements  21  for high-speed writing. 
         [0034]      FIG. 4B  shows a schematic cross-sectional view of the cells  40  given in  FIG. 4A . The cross-section was taken along  4 B- 4 B line. Elements of the cells  40  have functions similar to those in  FIGS. 2A and 2B . Each of the cells  40  additionally includes a local conductor line  42 . The MTJ elements  21  each of the memory cells are electrically connected in parallel to the source region  13  of the proper transistor  12 . 
         [0035]      FIG. 5  shows a schematic cross sectional view of two cells  50  of three-dimensional MRAM according to yet another embodiment of the present invention. The cells  50  comprises two memory layers  54 - 1  and  54 - 2  that include a plurality of MTJ elements  21 , and two conductor layers disposed above the memory layers  54 - 1  and  54 - 2 . Each of the conductor layers comprises a plurality of parallel bit lines  19 . The bit lines  19  disposed in the different conductor layers are parallel to each other and intersect the word lines  16 . Selection of the MTJ in the 3D-MRAM is provided by a unique combination of the word line  16 , the bit line  19  and the memory layer. Elements of the cells  50  have functions similar to those in the  FIGS. 2A and 2B . The three-dimensional memory cell  50  provides a possibly of substantial MRAM density increase. The MTJ elements  19  of the same memory layer are connected in parallel to the source  13  of the proper selection transistor  12  through conductor studs  52 . In the memory cells  50  the overlaying MTJ elements  19  disposed in the different memory layers  54 - 1  and  54 - 2  can have parallel or in series connections between each other. 
         [0036]      FIG. 6  shows a circuit diagram of 3D-memory cell  60  according to still another embodiment of the present invention. The memory cell  60  has 1 T-2MTJ-2L design. It includes one selection transistor  12 , two MTJ elements  21  per memory layer and two memory layers  54 - 1  and  54 - 2 . The number of MTJ elements in the memory layer and the number of memory layers can be any. All MTJ elements  19  of the memory cell  60  are connected in parallel to the source of the selection transistor  12 . The word line  16  is connected to a word line circuitry  62 . The bit lines  19  are connected to the bit line circuitry  64 . The bit line circuitry can includes several bit line drivers with one driver per conductor layer. For instance, the lines  19 - 1 - 1  and  19 - 2 - 1  of the bottom conductor layer are connected to the bit line driver  64 - 1  and the bit lines  19 - 1 - 2  and  19 - 2 - 2  of the top conductor layer are connected to the bit line driver  64 - 2 . The number of the bit line drivers can be any. 
         [0037]      FIG. 7  shows a circuitry diagram of 3D-memory cell  70  according to still another embodiment of the present invention. The memory cell  70  has 1T-2MTJ-2L design but distinguishes from the cell  60  shown in the  FIG. 6  by electrical connection between the overlaying MTJ elements  19  of the different memory layers  54 - 1  and  54 - 2 . The MTJ elements  19  of the layers  54 - 1  and  54 - 2  are connected in series to each other to form columns of the MTJ elements. The columns of the MTJ elements are connected in parallel to the selection transistor  12 . 
         [0038]    There is wide latitude for the choice of materials and their thicknesses within the embodiments of the present invention. 
         [0039]    The pinned layer  22  has a thickness of about 10-100 nm and more specifically of about 25-50 nm and coercivity measured along its easy axis above 1000 Oe and more specifically of about 2000-5000 Oe. The layer  22  is made of magnetic material with perpendicular anisotropy such as Co, Fe or Ni-based alloys or their multilayers such as Co/Pt, Co/Pd, Co/Au, CoFe/Pt, Fe/Pt, Fe/Pd, Ni/Cu or similar. 
         [0040]    The free layer  23  has a thickness of about 1-30 nm and more specifically of about 5-15 nm and coercivity less than 1000 Oe and more specifically of about 100-300 Oe. The layer  23  is made of soft magnetic material with perpendicular anisotropy such as Co, Fe or Ni-based alloys or multilayers such as Co/Pt, Co/Pd, Co/Au, CoFe/Pt, Fe/Pt, Fe/Pd, Ni/Cu or similar. 
         [0041]    The tunnel barrier layer  24  has a thickness of about 0.5-25 nm and more specifically of about 0.5-1.5 nm. The tunnel barrier layer is made of MgO, Al 2 O 3 , Ta 2 O 5 , TiO 2 , Mg—MgO and similar materials or their based laminates. 
         [0042]    The seed  26  and cap  27  layers have a thickness of 1-100 nm and more specifically of about 5-25 nm. The layers are made of Ta, W, Ti, Cr, Ru, NiFe, NiFeCr, PtMn, IrMn or similar conductive materials or their based laminates. 
         [0043]    The conductor lines  18  and  19  are made of Cu, Al, Au, Ag, AlCu, Ta/Au/Ta, Cr/Cu/Cr and similar materials or their based laminates. 
         [0044]    The soft magnetic underlayer  32  is 0.5-5 nm thick and is made of a soft magnetic material with a substantial spin polarization and coercivity of about 1-200 Oe such as CoFe, CoFeB, NiFe, Co, Fe, CoPt, FePt, CoPtCu, FeCoPt and similar or their based laminates such as CoFe/Pt, CoFeB/P and similar. The material of the soft magnetic underlayer  74  can have either in-plane or perpendicular anisotropy. 
         [0045]    The storage layer  34  has a thickness of 5-25 nm and more specifically of about 8-15 nm; and coercivity less than 1000 Oe and more specifically of about 200-500 Oe. The storage layer  76  is made of magnetic material with a substantial perpendicular anisotropy such as Co, Fe or Ni-based alloys or multilayers such as Co/Pt, Co/Pd, Co/Au, CoFe/Pt, Fe/Pt, Fe/Pd, Ni/Cu or similar. 
         [0046]    The spin-polarizing layer  37  has a thickness of 0.5-5 nm and is made of a soft magnetic material with a coercivity of about 1-200 Oe and a substantial spin polarization such as CoFe, CoFeB, NiFe, Co, Fe, CoPt, FePt, CoPtCu, FeCoPt and similar or their based laminates such as CoFe/Pt, CoFeB/P and similar. The material of the spin-polarizing layer  37  can have either in-plane or perpendicular anisotropy. 
         [0047]    The reference layer  38  has a thickness of 10-100 nm and more specifically of about 20-50 nm; and coercivity above 1000 Oe and more specifically of about 2000-5000 Oe. The reference layer  38  is made of magnetic material with a substantial perpendicular anisotropy such as Co, Fe or Ni-based alloys or multilayers such as Co/Pt, Co/Pd, Co/Au, CoFe/Pt, Fe/Pt, Fe/Pd, Ni/Cu or similar. 
         [0048]    It is understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention should be, therefore, determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.