Abstract:
A system and method for interface translation between a system packet interface level 3 (SPI-3) defines an interface between a physical device (PHY device) and a link layer device, and a gigabit media independence interface (GMII) which defines an interface between a media access control (MAC) portion of a gigabit Ethernet and a physical device. The system includes a translation circuit for translating a GMII reception signal, received from a GMII interface device, into an SPI-3 reception signal synchronized with an SPI3 reference clock, and for translating an SPI-3 transmission signal, received from an SPI-3 interface device, into a GMII transmission signal synchronized with a GMII reference clock.

Description:
CLAIM OF PRIORITY  
       [0001]     This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. §119 from an application for SYSTEM AND METHOD FOR GIGABIT MEDIA INDEPENDENCE INTERFACE (GMII)-TO-SYSTEM PACKET INTERFACE LEVEL 3 (SPI-3) INTERFACE TRANSLATION, filed in the Korean Intellectual Property Office on 23 Dec. 2004 and there duly assigned Serial No. 2004-111488.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Technical Field  
         [0003]     The present invention relates to a system and method for gigabit media independence interface (GMII)-to-system packet interface level 3 (SPI-3) interface translation and, more particularly, to a system and method for interface translation between a system packet interface level 3 (SPI-3), which defines an interface between a physical device (PHY device) and a link layer device, and a gigabit media independence interface (GMII), which defines an interface between a media access control (MAC) portion of a gigabit Ethernet and a physical device.  
         [0004]     2. Description of the Related Art  
         [0005]     Various kinds of communication protocols and interfaces are defined in communication and network systems. Interface matching is needed to enable communication with different protocols and interfaces because different interfaces are defined for different layers.  
         [0006]     In particular, an SPI-3 interface mechanism defines a communication mechanism between a link layer device and a physical device (PHY device), and a gigabit media independent interface (GMII) mechanism defines an interface which connects a MAC portion and a physical device (PHY device) in a gigabit Ethernet. Accordingly, communication between a device with the SPI-3 interface mechanism and a device with the GMII interface mechanism requires matching of different protocols and interfaces.  
       SUMMARY OF THE INVENTION  
       [0007]     It is an object of the present invention to provide a system and method for GMII-to-SPI-3 interface translation capable of minimizing latency time due to MAC address assignment, initialization or the like by connecting a translation circuit between a GMII device and an SPI-3 device so as to directly translate between protocols and interfaces.  
         [0008]     According to one aspect of the present invention, there is provided a system for gigabit media independence interface (GMII)-to-system packet interface level 3 (SPI-3) interface translation, the system comprising a translation circuit for translating a GMII reception signal received from a GMII interface device into an SPI-3 reception signal synchronized to an SPI3 reference clock, and for translating an SPI-3 transmission signal received from an SPI-3 interface device into a GMII transmission signal synchronized to a GMII reference clock.  
         [0009]     The translation circuit preferably comprises: a first translation circuit for translating the GMII reception signal received from the GMII interface device into an SPI-3 reception signal synchronized to the SPI3 reference clock based on starting frame delimiter (SFD) pattern information in the GMII reception signal; and a second translation circuit for translating the SPI-3 transmission signal received from the SPI-3 interface device into a GMII transmission signal synchronized to the GMII reference clock by adding the SFD pattern information to the SPI-3 transmission signal.  
         [0010]     The first translation circuit preferably comprises: an SFD pattern detector for detecting the SFD pattern information from the GMII reception signal received from the GMII interface device; a first clock synchronizer for performing clock synchronization with the GMII reference clock and the SPI3 reference clock upon translating the GMII reception signal into the SPI-3 reception signal; and a first controller for translating the GMII reception signal into the SPI-3 reception signal according to the SPI3 reference clock from the first clock synchronizer when the SFD pattern information received from the SFD pattern detector matches pre-stored SFD pattern information.  
         [0011]     The GMII reception signal may be transmitted by the GMII interface device in synchronization with the GMII_RXC clock signal only when a GMII RX_DV (Data Valid) signal is high.  
         [0012]     The first controller preferably comprises: a comparator for comparing the SFD pattern information received from the SFD detector to the pre-stored SFD pattern information, and for generating a match signal when they match; a GMII receiving controller for synchronizing the GMII reception signal to the GMII reference clock in response to reception of the match signal from the comparator; and an SPI-3 receiving controller for translating the GMII reception signal synchronized by the GMII receiving controller into the SPI-3 reception signal according to the SPI3 reference clock.  
         [0013]     The second translation circuit preferably comprises: a second clock synchronizer for performing clock synchronization with the GMII reference clock and the SPI3 reference clock upon translating the SPI-3 transmission signal into the GMII transmission signal; SFD pattern information generator for generating preamble and SFD pattern information according to a reference clock signal from the second clock synchronizer; and a second controller for translating the generated preamble and SFD pattern information from the SFD pattern information generator and the SPI-3 transmission signal into the GMII transmission signal according to the GMII reference clock from the second clock synchronizer.  
         [0014]     The second controller preferably comprises: an SPI-3 transmission controller for synchronizing the SPI-3 transmission signal with an SPI3 reference clock; and a GMII transmission controller for translating the SPI-3 transmission signal synchronized by the SPI-3 transmission controller into the GMII transmission signal according to the GMII reference clock.  
         [0015]     According to another aspect of the present invention, there is provided a method for gigabit media independence interface (GMII)-to-system packet interface level 3 (SPI-3) interface translation, the method comprising translating a GMII reception signal received from a GMII interface device into an SPI-3 reception signal synchronized with an SPI3 reference clock based on SFD pattern information in the GMII reception signal.  
         [0016]     Translating the GMII reception signal received from the GMII interface device into the SPI-3 reception signal synchronized with the SPI3 reference clock preferably comprises: detecting the SFD pattern information from the GMII reception signal received from the GMII interface device; performing clock synchronization with a GMII reference clock and the SPI3 reference clock upon translating the GMII reception signal into the SPI-3 reception signal; and translating the GMII reception signal into the SPI-3 reception signal according to the SPI3 reference clock when the detected SFD pattern information matches pre-stored SFD pattern information.  
         [0017]     Translating the GMII reception signal into the SPI-3 reception signal according to the SPI3 reference clock preferably comprises: comparing the detected SFD pattern information to the pre-stored SFD pattern information and generating a match signal when they match; synchronizing the GMII reception signal with the GMII reference clock in response to receiving the match signal; and translating the GMII reception signal into the SPI-3 reception signal according to the SPI3 reference clock.  
         [0018]     According to another aspect of the present invention, there is provided a method for gigabit media independence interface (GMII)-to-system packet interface level 3 (SPI-3) interface translation, the method comprising translating an SPI-3 transmission signal received from an SPI-3 interface device into a GMII transmission signal synchronized with a GMII reference clock by adding SFD pattern information to the SPI-3 transmission signal.  
         [0019]     Translating the SPI-3 transmission signal transmitted by the SPI-3 interface device into the GMII transmission signal synchronized with the GMII reference clock by adding SFD pattern information to the SPI-3 transmission signal preferably comprises: performing clock synchronization with the GMII reference clock and an SPI3 reference clock; generating preamble and SFD pattern information according to the GMII reference clock; and translating the preamble and SFD pattern information and the SPI-3 transmission signal into the GMII transmission signal according to the GMII reference clock.  
         [0020]     Translating the preamble and SFD pattern information and the SPI-3 transmission signal into the GMII transmission signal according to the GMII reference clock preferably comprises: synchronizing the SPI-3 transmission signal with the SPI3 reference clock; and translating the SPI-3 transmission signal synchronized with the SPI3 reference clock into the GMII transmission signal according to the GMII reference clock. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0021]     A more complete appreciation of the invention, and many of the attendant advantages thereof, will be readily apparent as the same becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings in which like reference symbols indicate the same or similar components, wherein:  
         [0022]      FIG. 1  illustrates an example of a system for GMII-to-SPI-3 interface translation;  
         [0023]      FIG. 2  illustrates another example of a system for GMII-to-SPI-3 interface translation;  
         [0024]      FIG. 3  illustrates a schematic configuration of a system for GMII-to-SPI-3 interface translation according to the present invention;  
         [0025]      FIG. 4  illustrates a detailed configuration of the translation circuit of  FIG. 3 ;  
         [0026]      FIG. 5  illustrates an example of pin allocation in the translation circuit of  FIG. 3 ;  
         [0027]      FIG. 6  illustrates a detailed configuration of the RX controller of  FIG. 4 ;  
         [0028]      FIG. 7  illustrates a detailed configuration of the TX controller of  FIG. 4 ;  
         [0029]      FIG. 8  is a flowchart illustrating a GMII-to-SPI-3 interface translation process according to the present invention; and  
         [0030]      FIG. 9  is a flowchart illustrating an SPI-3-to-GMII interface translation process according to the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0031]      FIG. 1  illustrates an example of a system for GMII-to-SPI-3 interface translation.  
         [0032]     In  FIG. 1 , direct connection of an Ethernet switch  20  with a GMII interface to a network processor  10  with an SPI-3 interface cannot be made due to lack of interface and protocol matching.  
         [0033]     As a way of addressing this problem, a media access control (MAC)  30  is connected between the network processor  10  and the Ethernet switch  20  for translating between protocols and interfaces, and a processor  40  is connected to control the MAC  30 .  
         [0034]     The MAC  30  translates the protocols and the interfaces between the network processor  10  and the Ethernet switch  20  under the control of the processor  40 , enabling communication between the network processor  10  and the Ethernet switch  20 .  
         [0035]     In such a system, however, it is necessary for the processor  40  to be connected to the MAC  30  for controlling it, and for a MAC address to be assigned.  
         [0036]     Furthermore, the processor  40  should have a driver for initializing or driving the MAC  30 , which makes the overall system configuration complex.  
         [0037]      FIG. 2  illustrates another example of a system for GMII-to-SPI-3 interface translation.  
         [0038]     In  FIG. 2 , direct connection of the Ethernet switch  20  with a GMII interface to the network processor  10  with an SPI-3 interface cannot be made due to lack of interface and protocol matching.  
         [0039]     As a way of addressing this problem, a MAC  30  for translating between protocols and interfaces, and physical devices  40  and  50  interconnected via Ethernet ports, are connected between the network processor  10  and the Ethernet switch  20 , and first and second processors  60  and  70 , respectively, are connected to the MAC  30  and the Ethernet switch  20 , respectively, for controlling them.  
         [0040]     The MAC  30  translates the protocols and the interfaces between the network processor  10  and the Ethernet switch  20  under the control of the first processor  60 , enabling communication between the network processor  10  and the Ethernet switch  20 .  
         [0041]     Even in this system, however, it is necessary for the first and second processors  60  and  70  to be connected to the MAC  30  and the Ethernet switch  20 , respectively, for controlling them, and also for a MAC address to be assigned.  
         [0042]     Furthermore, as in the configuration of  FIG. 1 , the first processor  60  should have a driver for initializing or driving the MAC  30 , which makes the overall system configuration complex, and which also increases latency time.  
         [0043]     The present invention will now be described more fully with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.  
         [0044]      FIG. 3  illustrates a schematic configuration of a system for GMII-to-SPI-3 interface translation according to the present invention.  
         [0045]     As shown in  FIG. 3 , the GMII-to-SPI-3 interface translation system includes a network processor  100  with an SPI-3 interface, an Ethernet switch  200  with a GMII interface, a translation circuit  300  for translating interfaces and protocols between the network processor  100  and the Ethernet switch  200 , and a processor  400  for controlling the network processor  100  and the Ethernet switch  200 .  
         [0046]     The translation circuit  300  translates a GMII RX signal received from the Ethernet switch  200  into an SPI-3 RX signal for the SPI-3 interface and protocol, and transmits the SPI-3 RX signal to the network processor  100 . Conversely, the translation circuit  300  translates an SPI-3 TX signal received from the network processor  100  into a GMII TX signal for the GMII interface and protocol, and transmits the GMII TX signal to the Ethernet switch  200 .  
         [0047]      FIG. 4  illustrates a detailed configuration of the translation circuit of  FIG. 3 , and FIG.  5  illustrates an example of pin allocation in the translation circuit of  FIG. 3 .  
         [0048]     As shown in  FIG. 4 , the translation circuit  300  of the present invention includes a translator for translating the GMII RX signal into the SPI-3 RX signal, and a translator for translating the SPI-3 TX signal into the GMII TX signal.  
         [0049]     First, the translator for translating the GMII RX signal into the SPI-3 RX signal includes a first data latch  310   a,  a starting frame delimiter (SFD) detector  320 , an RX controller  330 , an RX FIFO storage unit  340 , a second data latch  310   b,  and a first clock synchronizer  350   a.    
         [0050]     The first data latch  310   a  latches GMII RXD (7:0) data in synchronization with a GMII_RXC clock signal while a GMII RX_DV (Data Valid) signal received from the Ethernet switch is high.  
         [0051]     The SFD detector  320  receives the latched data from the first data latch  310   a,  detects information in preamble and SFD fields of the latched data, and transmits bit stream information in the SFD field to the RX controller  330 .  
         [0052]     The RX controller  330  receives the bit stream information in the SFD field from the SFD detector  320 , compares the received bit stream information to pre-stored SFD bit stream information (10101011), and if they match, stores only actual data, excluding the preamble and SFD fields, in the RX FIFO storage unit  340 .  
         [0053]     After storing the actual data in the RX FIFO storage unit  340 , the RX controller  330  also determines the state of an SPI-3_RXEN_B signal, which is a FIFO status signal of SPI-3 received from the network processor  100 . If the SPI-3_RXEN_B signal is low, the RX controller  330  transmits an SPI3_RXSOP (Start Of Packet) signal and an SPI3_RXEOP (End Of Packet) signal to the network processor  100  in synchronization with an SPI3_REFCLK reference clock signal provided by the first clock synchronizer  350   a.    
         [0054]     After transmitting the SPI3_RXSOP signal, the RX controller  330  also translates the data stored in the RX FIFO storage unit  340  into SPI3_RXD (7:0) data synchronized with the SPI3_REFCLK reference clock signal, and transmits the SPI3_RXD (7:0) data to the network processor  100  via the second data latch  310   b.    
         [0055]     That is, after the SPI3_RXSOP signal synchronized with the SPI3_REFCLK reference clock signal is first transmitted, the SPI3_RXD (7:0) data is transmitted, and then the SPI3_RXEOP signal is transmitted.  
         [0056]     The second data latch  310   b  receives the SPI3_RXSOP signal and the SPI3_RXEOP signal from the RX controller  330 , and the SPI3_RXD (7:0) data from the RX FIFO storage unit  340 , and latches and transmits them to the network processor  100 .  
         [0057]     The first clock synchronizer  350   a  serves to provide the GMII_REFCLK and SPI3_REFCLK reference clocks to synchronize clocks depending on the interfaces upon translation of the GMII RX signal into the SPI-3 RX signal.  
         [0058]     Meanwhile, the translator for translating the SPI-3 TX signal into the GMII TX signal includes a third data latch  31   c,  a TX controller  360 , a TX FIFO storage unit  370 , a starting frame delimiter (SFD) generator  380 , a fourth data latch  310   d,  and a second clock synchronizer  350   b.    
         [0059]     The third data latch  310   c  latches SPI TXD (7:0) data, which is received from the network processor  100  with the SPI-3 TX signal, in synchronization with an SPI3_TXC clock signal, and then transmits the latched SPI TXD (7:0) data to the TX FIFO storage unit  370 .  
         [0060]     The TX controller  360  receives an SPI3_TXSOP signal and an SPI3_TXEOP signal from the network processor  100  when an SPI3_TXEN_B signal received via the third data latch  310   c  is low.  
         [0061]     Furthermore, in response to receiving the SPI3_TXSOP signal from the network processor  100 , the TX controller  360  stores the latched SPI TXD (7:0) data within the third data latch  310   c  in the TX FIFO storage unit  370 .  
         [0062]     In addition, when receiving a high GMII_TXEN signal from the Ethernet switch  200 , the TX controller  360  transmits a preamble and SFD pattern generation signal to the SFD generator  380  in synchronization with a GMII_REFCLK reference clock signal provided by the second clock synchronizer  350   b.    
         [0063]     The TX controller  360  also translates the SPI TXD (7:0) data stored in the TX FIFO storage unit  370  into GMII_TXD (7:0) data synchronized with the GMII_REFCLK reference clock signal, and transmits the GMII_TXD (7:0) data to the fourth data latch  310   d.    
         [0064]     The SFD generator  380  generates a preamble pattern (10101010) and an SFD pattern (10101011), and transmits the patterns to the fourth data latch  310   d  under the control of the TX controller  360 .  
         [0065]     The fourth data latch  310   d  latches the preamble 10101010 and the SFD pattern (10101011) information generated by the SFD generator  380 , and the GMII_TXD (7:0) data transmitted by the TX FIFO storage unit  370 , and transmits a GMII_TX signal to the Ethernet switch  200 . In the latter regard, the fourth data latch  310   d  transmits the preamble 10101010 and the SFD pattern (10101011) information, and then transmits the GMII_TXD (7:0) data.  
         [0066]     The second clock synchronizer  350   b  provides the GMII_REFCLK and the SPI3_REFCLK reference clocks to synchronize clocks depending on the interface upon translation of the SPI-3 TX signal into the GMII TX signal.  
         [0067]      FIG. 6  illustrates a detailed configuration of the RX controller of  FIG. 4 .  
         [0068]     As shown in  FIG. 6 , the RX controller  330  according to the present invention includes a GMII RX controller  331 , a comparator  332 , and an SPI-3 RX controller  333 .  
         [0069]     The GMII RX controller  331  latches the GMII RXD (7:0) data in the register in synchronization with the GMII_RXC clock signal while the GMII RX_DV (Data Valid) signal received from the Ethernet switch is high.  
         [0070]     The comparator  332  receives the bit stream information of the detected SFD field from the starting frame delimiter (SFD) detector  320 , and compares the bit stream information to the pre-stored SFD pattern (10101011). If the bit stream information of the received SFD field matches the pre-stored SFD pattern (10101011) information, the comparator  332  transmits a match signal to the GMII RX controller  331 .  
         [0071]     The GMII RX controller  331  receives the match signal from the comparator  332 , and stores only actual data, excluding the preamble field and the SFD field, in the RX FIFO storage unit  340 .  
         [0072]     The SPI-3 RX controller  333  also determines the state of an SPI-3_RXEN_B signal, which is a FIFO status signal of SPI-3 received from the network processor  100 . If the SPI-3_RXEN_B signal is low, the SPI-3 RX controller  333  transmits an SPI3_RXSOP (Start Of Packet) signal and an SPI3_RXEOP (End Of Packet) signal to the network processor  100  in synchronization with an SPI3_REFCLK reference clock signal.  
         [0073]     That is, after transmitting the SPI3_RXSOP signal, the SPI-3 RX controller  331  translates the stored data in the RX FIFO storage unit  340  into the SPI3_RXD (7:0) data synchronized with the SPI3_REFCLK reference clock signal, and transmits the SPI3_RXD (7:0) data to the network processor  100 .  
         [0074]     The SPI-3 RX controller  331  also transmits the SPI3_RXEOP signal to the network processor  100  when the RX FIFO storage unit  340  is empty due to data transmission completion.  
         [0075]      FIG. 7  illustrates a detailed configuration of the TX controller of  FIG. 4 .  
         [0076]     As shown in  FIG. 7 , the TX controller  360  according to the present invention includes an SPI-3 TX controller  361  and a GMII TX controller  362 .  
         [0077]     The SPI-3 TX controller  361  receives an SPI3_TXEN_B signal from the network processor  100  with the SPI-3 TX signal. When the SPI3_TXEN_B signal is low, the SPI-3 TX controller  361  further receives an SPI3_TXSOP signal and an SPI3_TXEOP signal from the network processor  100 .  
         [0078]     After receiving the SPI3_TXSOP signal, the SPI-3 TX controller  361  stores the latched SPI TXD (7:0) data within the third data latch  310   c  ( FIG. 4 ) in the TX FIFO storage unit  370 .  
         [0079]     When the GMII_TXEN signal transmitted to the Ethernet switch  200  is high, the GMII TX controller  362  transmits a preamble and SFD pattern generation signal to the SFD generator  380  in synchronization with the GMII_REFCLK reference clock signal.  
         [0080]     In response to receiving the preamble and SFD pattern generation signal, the SFD generator  380  generates and transmits a preamble pattern (10101010) and an SFD pattern (10101011) to the Ethernet switch  200 , and then transmits a translation completion signal to the GMII TX controller  362 .  
         [0081]     When receiving the translation completion signal from the SFD generator  380 , the GMII TX controller  362  translates the stored SPI TXD (7:0) data within the TX FIFO storage unit  370  into the GMII_TXD (7:0) data synchronized with the GMII_REFCLK reference clock signal, and transmits the GMII_TXD (7:0) data to the Ethernet switch  200 .  
         [0082]     Furthermore, when the TX FIFO storage unit  370  is empty due to data transmission completion, the GMII TX controller  362  transmits a low GMII_TXEN signal to the Ethernet switch  200  to indicate that subsequently transmitted data is invalid.  
         [0083]      FIG. 8  is a flowchart illustrating a GMII-to-SPI-3 interface translation process according to the present invention.  
         [0084]     As shown in  FIG. 8 , the GMII RXD (7:0) data synchronized with the GMII_RXC clock signal is latched in the register (S 10 ), and is then transmitted to the SFD detector  320  while the GMII RX_DV (Data Valid) signal from the Ethernet switch  200  with the GMII interface is high.  
         [0085]     Upon receipt of the GMII RXD (7:0) data, the SFD detector  320  detects SFD pattern information from the received GMII RXD (7:0) data (S 20 ), and transmits the SFD pattern information to the RX controller  330 .  
         [0086]     The RX controller  330  compares the SFD pattern information received from the SFD detector  320  to the pre-stored SFD pattern information (10101011), and determines whether the received SFD pattern information matches the pre-stored SFD pattern information (S 30 ).  
         [0087]     If the received SFD pattern information matches the pre-stored SFD pattern information, only actual data, excluding the preamble field and the SFD field in the GMII RXD (7:0) data, is stored in the RX FIFO storage unit  340  under the control of the RX controller  330  (S 40 ).  
         [0088]     If the received SFD pattern information does not match the pre-stored SFD pattern information, the RX controller  330  generates an error signal (S 50 ). In this case, the process returns to step S 10  where the GMII RXD (7:0) data synchronized with the GMII_RXC clock signal is latched in the register (S 10 ).  
         [0089]     Subsequently, if an SPI-3_RXEN_B signal, which is a FIFO status signal of SPI-3 received from the network processor  100 , is low, the RX controller  330  transmits an SPI3_RXSOP (Start Of Packet) signal to the network processor  100  in synchronization with the SPI3_REFCLK reference clock signal to indicate the initiation of data transmission (S 60 ).  
         [0090]     Under the control of the RX controller  330 , the stored data in the RX FIFO storage unit  340  is then translated into the SPI3_RXD (7:0) data synchronized with the SPI3_REFCLK reference clock signal, and is transmitted to the network processor  100  (S 70 ).  
         [0091]     The RX controller  330  then determines whether the RX FIFO storage unit  340  is empty due to data transmission completion (S 80 ).  
         [0092]     If the RX FIFO storage unit  340  is empty, the RX controller  330  transmits an SPI3_RXEOP (End Of Packet) signal to the network processor  100  to indicate the data transmission completion (S 90 ). If the RX FIFO storage unit  340  is not empty, the process returns to step S 70 .  
         [0093]      FIG. 9  is a flowchart illustrating an SPI-3-to-GMII interface translation process according to the present invention.  
         [0094]     As shown in  FIG. 9 , when the SPI3_TXEN_B signal received from the network processor  100  with the SPI-3 TX signal is low, the TX controller  360  receives from the network processor  100  an SPI3_TXSOP signal indicating data transmission initiation (S 10 ).  
         [0095]     Under the control of the TX controller  360 , the SPI_TXD (7:0) data transferred from the network processor  100  is latched in the latch  310   c  ( FIG. 4 ) in synchronization with the SPI3_TXC clock signal, and is then stored in the TX FIFO storage unit  370  (S 20 ).  
         [0096]     The TX controller  360  then receives the SPI3_TXEOP signal indicating data transmission completion from the network processor  100  (S 30 ).  
         [0097]     When a GMII_TXEN signal transmitted to the Ethernet switch  200  with the GMII interface is high, the TX controller  360  transmits a preamble and an SFD pattern generation signal, which is synchronized with the GMII_REFCLK reference clock signal, to the SFD generator  380  (S 40 ).  
         [0098]     In response to receiving the preamble and SFD pattern generation signal, the SFD generator  380  generates a preamble pattern (10101010) and an SFD pattern (10101011) (S 50 ), transmits the patterns to the Ethernet switch (S 60 ), and then transmits a translation completion signal to the TX controller  360 .  
         [0099]     Under the control of the TX controller  360 , which receives the translation completion signal from the SFD generator  380 , the stored SPI TXD (7:0) data in the TX FIFO storage unit  370  is translated into the GMII_TXD (7:0) data synchronized with the GMII_REFCLK reference clock signal, and is then transmitted to the Ethernet switch  200  (S 70 ).  
         [0100]     The TX controller  360  then determines whether the TX FIFO storage unit  370  is empty due to data transmission completion (S 80 ).  
         [0101]     If the TX FIFO storage unit  370  is found to be empty, the TX controller  360  transmits a low GMII_TXEN signal to the Ethernet switch  200  to indicate that subsequently transmitted data is invalid (S 90 ). If the TX FIFO storage unit  370  is found to be not empty, a return to step S 70  is executed.  
         [0102]     According to the present invention, a translation circuit is connected between the GMII device and the SPI-3 device to directly translate between the protocols and the interfaces. This minimizes latency time caused in prior systems by MAC address assignment, initialization, or the like, thereby resulting in more efficient interface translation.  
         [0103]     While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents.