Abstract:
A system and method providing, via a single output electrode of an integrated circuit having internal circuitry, a status signal having time multiplexed states indicative of a power on reset condition for external circuitry following enablement of operations of portions of the internal circuitry, and further indicative of subsequent operation statuses of the internal circuitry portions.

Description:
BACKGROUND 
     1. Field of the Invention 
     The present invention relates to power management circuits, and in particular, to power management circuits providing multiple power supply voltages along with control and status signals for providing power on reset control for other circuitry and status signals indicative of the readiness of the various power supply voltages. 
     2. Related Art 
     Many systems and applications, particularly those concerned with operating at voltages different from that of the main power source, rely on power management circuits to provide multiple stable and regulated voltages. For example, one common example of such a circuit may include multiple regulated voltage sources in the form of low dropout (LDO) voltage regulators and multiple voltage buck regulators. Following initial enablement of one or more of these power supply regulators, a power on reset signal is provided for initiating a system reset of other, e.g., external, circuitry following enablement and readiness of the power supply voltage sources. Additionally, depending upon the application, it is desirable to monitor the output voltages being provided for any fault conditions. This, however, can result in a packaging problem when a separate interface pin, e.g., integrated circuit pin, is required for each voltage source (e.g., one for enablement plus another for fault monitoring), in addition to the pin needed for the power on reset. This results in a larger package to accommodate all such pins, as well as signal routing issues for the various signals. 
     Referring to  FIG. 1 , conventional systems having a power on reset signal and a power good, or ready, status signal operate substantially as represented in the voltage diagrams. As the input voltage VIN increases, power on reset signals nPOR, POR are generated in accordance with their respective voltage thresholds. For example, in the case of a power on reset signal nPOR in which such signal is asserted low, the output signal follows the input voltage VIN until such time t 1  the threshold, e.g., 1.2 volt, is crossed, following which the power on reset signal nPOR is asserted (low). Following a predetermined delay interval t 1 -t 3 , the power on reset signal nPOR is de-asserted (high). In the case of a power on reset, signal POR is generally needed as a logical inversion of signal nPOR. Meanwhile, the power good, or ready, status signal is asserted at time t 2  when the output voltage VOUT has achieved the predetermined level, e.g., 90%. 
     SUMMARY 
     In accordance with the presently claimed invention, a system and method are provided for providing, via a single output electrode of an integrated circuit having internal circuitry, a status signal having time multiplexed states indicative of a power on reset condition for external circuitry following enablement of operations of portions of the internal circuitry, and further indicative of subsequent operation statuses of the internal circuitry portions. 
     In accordance with one embodiment of the presently claimed invention, an integrated circuit having internal circuitry for providing, via a single output electrode, a status signal having time multiplexed states indicative of a power on reset condition for external circuitry following enablement of operations of portions of the internal circuitry, and further indicative of subsequent operation statuses of the internal circuitry portions, including: 
     shorter delay circuitry responsive to a plurality of ready signals having states indicative of stabilized and non-stabilized states of operations of corresponding portions of the internal circuitry by providing, in accordance with a plurality of shorter time delays, a plurality of corresponding delayed ready signals; 
     longer delay circuitry responsive to the plurality of ready signals and a plurality of enable signals having states indicative of enabled and non-enabled states of operations of the corresponding portions of the internal circuitry by providing a plurality of corresponding logic signals indicative of the states of respective pairs of one of the plurality of enable signals and one of the plurality of ready signals, and, in accordance with a plurality of longer time delays, a plurality of corresponding delayed logic signals and a plurality of corresponding inverse delayed logic signals; and 
     encoding circuitry coupled to the shorter delay circuitry and the longer delay circuitry, and responsive to the plurality of enable signals, the plurality of ready signals, the plurality of logic signals, the plurality of delayed logic signals, and the plurality of inverse delayed logic signals by providing a status signal having time multiplexed states which are indicative of a power on reset condition for external circuitry following one or more of the enabled states of operations of the corresponding portions of the internal circuitry, and are further indicative of one or more of the stabilized states of operations of the corresponding portions of the internal circuitry, wherein
         the status signal is in a de-asserted state when each of the plurality of enable signal states is indicative of the non-enabled states of operations of corresponding portions of the internal circuitry,   the status signal transitions to and remains in an asserted state, during at least an interval substantially equal to one of the plurality of longer time delays, in response to a first one of the plurality of enable signal states becoming indicative of the enabled state of operation of a first corresponding portion of the internal circuitry, following which, in response to a first one of the plurality of ready signal states being indicative of the stabilized state of operation of the first corresponding portion of the internal circuitry, the status signal transitions to the de-asserted state,   during the enabled and stabilized states of operation of the first corresponding portion of the internal circuitry and following a second one of the plurality of enable signal states becoming indicative of the enabled state of operation of a second corresponding portion of the internal circuitry, the status signal remains in the de-asserted state during at least an interval substantially equal to one of the plurality of shorter time delays, following which,
           in response to a second one of the plurality of ready signal states being indicative of the stabilized state of operation of the second corresponding portion of the internal circuitry, the status signal remains in the de-asserted state, and   in response to the second one of the plurality of ready signal states being indicative of the non-stabilized state of operation of the second corresponding portion of the internal circuitry, the status signal transitions to the asserted state, and   
           the status signal transitions to and remains in the asserted state in response to the first and second ones of the plurality of enable signal states concurrently becoming indicative of the enabled states of operations of the first and second corresponding portions of the internal circuitry, following which and after the first one of the plurality of ready signal states becomes and remains indicative of the stabilized state of operation of the first corresponding portion of the internal circuitry during at least an interval substantially equal to one of the plurality of longer time delays, the status signal transitions to the de-asserted state, further following which, in response to one of the first and second ready signal states becoming indicative of the non-stabilized state of operation of one of the first and second corresponding portions of the internal circuitry, the status signal transitions to the asserted state.       

     In accordance with another embodiment of the presently claimed invention, an integrated circuit having internal circuitry for providing, via a single output electrode, a status signal having time multiplexed states indicative of a power on reset condition for external circuitry following enablement of operations of portions of the internal circuitry, and further indicative of subsequent operation statuses of the internal circuitry portions, including: 
     a plurality of enablement electrodes to convey a plurality of enable signals having states indicative of enabled and non-enabled states of operations of corresponding portions of the internal circuitry; 
     a plurality of readiness electrodes to convey a plurality of ready signals having states indicative of stabilized and non-stabilized states of operations of the corresponding portions of the internal circuitry; 
     an output electrode to convey a status signal having time multiplexed states which are indicative of a power on reset condition for external circuitry following one or more of the enabled states of operations of the corresponding portions of the internal circuitry, and are further indicative of one or more of the stabilized states of operations of the corresponding portions of the internal circuitry; 
     shorter delay circuitry coupled to the plurality of readiness electrodes and responsive to the plurality of ready signals by providing, in accordance with a plurality of shorter time delays, a plurality of corresponding delayed ready signals; 
     longer delay circuitry coupled to the plurality of enablement electrodes and the plurality of readiness electrodes, and responsive to the plurality of enable signals and the plurality of ready signals by providing a corresponding plurality of logic signals indicative of the states of respective pairs of one of the plurality of enable signals and one of the plurality of ready signals, and, in accordance with a plurality of longer time delays, a plurality of corresponding delayed logic signals and a plurality of corresponding inverse delayed logic signals; and 
     encoding circuitry coupled to the plurality of enablement electrodes, the plurality of readiness electrodes, the shorter delay circuitry, the longer delay circuitry, and the output electrode, and responsive to the plurality of enable signals, the plurality of ready signals, the plurality of logic signals, the plurality of delayed logic signals, and the plurality of inverse delayed logic signals by providing the status signal, wherein
         the status signal is in a de-asserted state when each of the plurality of enable signal states is indicative of the non-enabled states of operations of corresponding portions of the internal circuitry,   when one of the plurality of enable signal states becomes indicative of the enabled state of operation of a corresponding portion of the internal circuitry, the status signal transitions to and remains in an asserted state during at least an interval substantially equal to one of the plurality of longer time delays, and, if a corresponding one of the plurality of ready signal states has also become and remained indicative of the stabilized state of operation of the corresponding portion of the internal circuitry during at least another interval substantially equal to another of the plurality of longer time delays, the status signal transitions to a de-asserted state, following which the status signal state follows the corresponding one of the plurality of ready signal states,   when, after one of the plurality of enable signal states is indicative of the enabled state of operation of a corresponding portion of the internal circuitry and a corresponding one of the plurality of ready signal states has become indicative of the stabilized state of operation of the corresponding portion of the internal circuitry, another of the plurality of enable signal states becomes indicative of the enabled state of operation of another corresponding portion of the internal circuitry, the status signal remains in the de-asserted state during at least an interval substantially equal to one of the plurality of shorter time delays, following which the status signal remains in the de-asserted state so long as each one of the plurality of ready signal states remains indicative of the stabilized states of operation of the corresponding portions of the internal circuitry, and transitions to the asserted state otherwise, and   when, substantially concurrently, each one of the plurality of enable signal states becomes indicative of the enabled states of operation of the corresponding portions of the internal circuitry, the status signal transitions to and remains in the asserted state during at least an interval substantially equal to one of the plurality of longer time delays, following which the status signal transitions to the de-asserted state, further following which the status signal transitions to the asserted state in response to one of the plurality of ready signal states becoming indicative of the non-stabilized state of operation of the corresponding portion of the internal circuitry.       

     In accordance with still another embodiment of the presently claimed invention, a method for providing, via a single output electrode of an integrated circuit having internal circuitry, a status signal having time multiplexed states indicative of a power on reset condition for external circuitry following enablement of operations of portions of the internal circuitry, and further indicative of subsequent operation statuses of the internal circuitry portions, including: 
     receiving a plurality of ready signals having states indicative of stabilized and non-stabilized states of operations of corresponding portions of the internal circuitry, and in response thereto providing, in accordance with a plurality of shorter time delays, a plurality of corresponding delayed ready signals; 
     receiving the plurality of ready signals and a plurality of enable signals having states indicative of enabled and non-enabled states of operations of the corresponding portions of the internal circuitry, and in response thereto providing a plurality of corresponding logic signals indicative of the states of respective pairs of one of the plurality of enable signals and one of the plurality of ready signals, and, in accordance with a plurality of longer time delays, a plurality of corresponding delayed logic signals and a plurality of corresponding inverse delayed logic signals; and 
     receiving the plurality of enable signals, the plurality of ready signals, the plurality of logic signals, the plurality of delayed logic signals, and the plurality of inverse delayed logic signals, and in response thereto providing a status signal having time multiplexed states which are indicative of a power on reset condition for external circuitry following one or more of the enabled states of operations of the corresponding portions of the internal circuitry, and are further indicative of one or more of the stabilized states of operations of the corresponding portions of the internal circuitry, wherein
         the status signal is in a de-asserted state when each of the plurality of enable signal states is indicative of the non-enabled states of operations of corresponding portions of the internal circuitry,   the status signal transitions to and remains in an asserted state, during at least an interval substantially equal to one of the plurality of longer time delays, in response to a first one of the plurality of enable signal states becoming indicative of the enabled state of operation of a first corresponding portion of the internal circuitry, following which, in response to a first one of the plurality of ready signal states being indicative of the stabilized state of operation of the first corresponding portion of the internal circuitry, the status signal transitions to the de-asserted state,   during the enabled and stabilized states of operation of the first corresponding portion of the internal circuitry and following a second one of the plurality of enable signal states becoming indicative of the enabled state of operation of a second corresponding portion of the internal circuitry, the status signal remains in the de-asserted state during at least an interval substantially equal to one of the plurality of shorter time delays, following which,
           in response to a second one of the plurality of ready signal states being indicative of the stabilized state of operation of the second corresponding portion of the internal circuitry, the status signal remains in the de-asserted state, and   in response to the second one of the plurality of ready signal states being indicative of the non-stabilized state of operation of the second corresponding portion of the internal circuitry, the status signal transitions to the asserted state, and   
           the status signal transitions to and remains in the asserted state in response to the first and second ones of the plurality of enable signal states concurrently becoming indicative of the enabled states of operations of the first and second corresponding portions of the internal circuitry, following which and after the first one of the plurality of ready signal states becomes and remains indicative of the stabilized state of operation of the first corresponding portion of the internal circuitry during at least an interval substantially equal to one of the plurality of longer time delays, the status signal transitions to the de-asserted state, further following which, in response to one of the first and second ready signal states becoming indicative of the non-stabilized state of operation of one of the first and second corresponding portions of the internal circuitry, the status signal transitions to the asserted state.       

    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a voltage timing diagram for voltage signals in a conventional power management system. 
         FIG. 2  is a functional block diagram of a power management system in accordance with one embodiment of the presently claimed invention. 
         FIG. 3  is a functional block diagram of the power on reset and status signal control circuitry of the circuit of  FIG. 2 . 
         FIG. 4  is a signal timing diagram for operation of the circuit of  FIG. 2  in accordance with one embodiment of the presently claimed invention. 
         FIG. 5  is a signal timing diagram for operation of the circuit of  FIG. 2  in accordance with another embodiment of the presently claimed invention. 
         FIG. 6  is a table of the possible operating states of the circuitry of  FIG. 3 . 
         FIG. 7  is a signal timing diagram corresponding to the table of  FIG. 6 . 
     
    
    
     DETAILED DESCRIPTION 
     The following detailed description is of example embodiments of the presently claimed invention with references to the accompanying drawings. Such description is intended to be illustrative and not limiting with respect to the scope of the present invention. Such embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the subject invention, and it will be understood that other embodiments may be practiced with some variations without departing from the spirit or scope of the subject invention. 
     Throughout the present disclosure, absent a clear indication to the contrary from the context, it will be understood that individual circuit elements as described may be singular or plural in number. For example, the terms “circuit” and “circuitry” may include either a single component or a plurality of components, which are either active and/or passive and are connected or otherwise coupled together (e.g., as one or more integrated circuit chips) to provide the described function. Additionally, the term “signal” may refer to one or more currents, one or more voltages, or a data signal. Within the drawings, like or related elements will have like or related alpha, numeric or alphanumeric designators. Further, while the present invention has been discussed in the context of implementations using discrete electronic circuitry (preferably in the form of one or more integrated circuit chips), the functions of any part of such circuitry may alternatively be implemented using one or more appropriately programmed processors, depending upon the signal frequencies or data rates to be processed. 
     Referring to  FIG. 2 , a power management system  10  in accordance with one embodiment of the presently claimed invention is embodied as, or as part of, an integrated circuit IC containing power management control circuitry  12 , voltage regulator circuits  14   a ,  14   b , . . . ,  14   n , and power on reset and status circuitry  16 . Enablement signals  11   a ,  11   b , . . . ,  11   n  are provided to the power management control circuitry  12 , which, in turn, provides appropriate control signals  13   a ,  13   b , . . . ,  13   n  to the voltage regulators  14   a ,  14   b , . . . ,  14   n . Additionally, the power management control circuitry  12  is programmed and otherwise controlled by one or more control signals  11   p . The power management control circuitry  12  also provides one or more control signals  13   p  for the power on reset and status circuitry  16 , which also receives the enablement signals  11   a ,  11   b , . . . ,  11   n.    
     The voltage regulator circuits  14   a ,  14   b , . . . ,  14   n  provide respective ready status signals  15   r   1 ,  15   r   2 , . . . ,  15   rn  to the power on reset and status circuitry  16  to indicate when they have achieved the desired states of readiness, e.g., a predetermined percentage of the desired output voltage level for the output signal  15   v   1 ,  15   v   2 , . . . ,  15   vn . As discussed in more detail below, the power on reset and status circuitry  16 , based on the enablement signals  11   a ,  11   b , . . . ,  11   n  and ready signals  15   r   1 ,  15   r   2 , . . . ,  15   rn , provides the power on reset and status signal  17 . This signal  17  provides power on reset control for circuitry external to the power management unit  10 , as well as provide status information regarding the readiness of the various voltage regulators  14   a ,  14   b , . . . ,  14   n.    
     Throughout the following discussion, most signals are deemed asserted when in a logic 1 state, i.e., a higher voltage level, and de-asserted when in a logic 0 state, i.e., at a lower voltage level. However, the power on reset and status output signal  17  is a “negative” logic signal and is, therefore, considered asserted when in its logic 0 state and de-asserted when in its logic 1 state. 
     Referring to  FIG. 3 , a preferred embodiment of the power on reset and status circuitry  16  includes delay circuits  22  ( 22   a ,  22   b , . . . ),  24  ( 24   a ,  24   b , . . . ), and logic circuits  26 ,  28 ,  30 ,  32 ,  34 ,  36 , interconnected substantially as shown. As depicted here, and discussed in more detail below, this particular example includes delay circuitry and logic circuits for processing two enablement signals  11   a ,  11   b  and two ready signals  15   r   1 ,  15   r   2 . However, it will be readily understood by one of ordinary skill in the art that additional delay circuits and logic circuits can be added and interconnected in similar manner so as to accommodate the processing of additional enablement and ready signals. The delay circuits  22 ,  24  are preferably implemented using monostable multivibrator, or one-shot, circuits. In accordance with a preferred embodiment, the short delay circuits  22  provide delays of approximately 3 milliseconds and the long delay circuits  24  provide delays of approximately 50 milliseconds. However, each of the delays circuits  22 ,  24  can be programmed in accordance with control signals  13   p.    
     The state of the output signal  17  is regulated in accordance with the independent input signals  11   a ,  11   b ,  15   r   1 ,  15   r   2 , and the additional variable of time. In this example in which two voltage regulator circuits are used, thereby involving two enablement signals  11   a ,  11   b  and two corresponding ready signals  15   r   1 ,  15   r   2 , there are 16 possible “static” input conditions, some of which are not realistic conditions (e.g., where an enablement signal is de-asserted but its corresponding ready signal is asserted) and can thus be ignored. However, additional conditions can exist involving the spatial separation and/or overlapping conditional possibilities that can exist among the four independent input signals which can also influence the state of the output signal  17 . 
     Each of the delay circuits  22 ,  24 , operate in a similar manner as follows. When the input EN is a logic 0, the output Q is set at a logic 1, and when the input EN is a logic 1 the internal counter of the delay circuit  22 ,  24  is started. Upon the end of its count sequence (EOC), the output Q is set to logic 0, which disables the counter such that the output signal Q remains at a logic 0 until the input EN is reset back to a logic 0 state, whereupon the output signal Q is again set to a logic 1. 
     More specifically, the long delay counters  24  operate as follows. Upon power up of the circuit, whenever the enablement  11  and ready  15   r  signals are true (asserted), a long delay is initiated by the counters  24 . If either of the related enable  11  or ready  15   r  signals is de-asserted prior to the end of count EOC within the delay circuit  24 , the counter resets. The first counter that successfully achieves an uninterrupted end of count sequence sets the flip-flop  34  (via the OR logic gate  30   a ) and holds the output signals  31   c ,  31   e  at logic 1 levels until a system reset occurs, i.e., when all enablement signals  11   a ,  11   b  are de-asserted. 
     The short delay counters  22  provide two types of masking functions. The first masking function is in the form of a bypass delay and is used in the beginning when none of the long delay circuits  24  have achieved a complete end of count sequence and only one enablement signal  11  is asserted. For example, when the first enablement signal  11   a  is asserted, and with the state of signal  31   b  following the state of the first ready signal  15   r   1  by one gate delay, the state of signal  31   c  is the inversion of the state of the ready signal  15   r   1  (due to the actions of the long delays circuit  24   a , as discussed above, and logic gates  26   a ,  32   a , and  30   c ), and overlaps the first ready signal  15   r   1  such that signals  31   b  and  31   c  force the power on reset and status signal  17  to a logic 0 state (asserted) until the end of count sequence for the long delay circuit  24   a.    
     Additionally, the short delay circuits  22  provide a masking operation as follows. With just one set of the enablement  11  and ready  15   r  signals asserted, and the associated long delay end of count sequence completed, signals  31   c  and  31   e  are pulled up to a logic 1. Hence, only signals  31   b  and  31   d  can affect the state of the output signal  17 . For example, after the first enable signal  11   a  is asserted to a logic 1 state, indicating that the first voltage regulator  14   a  is powered on and stabilized, the second enablement signal  11   b  is asserted to a logic 1 state, thereby turning on the second regulator  14   b . It will take a finite amount of time (e.g., 1 millisecond) for its ready signal  15   r   2  to also become asserted. To prevent the output status signal  17  from again becoming asserted to a logic 0 state while awaiting the second voltage regulator  14   b  to become stabilized, a timing window (e.g., 3 milliseconds) holds the output signal  17  at its de-asserted logic 1 state. After this masking window times out, the output signal  17  follows the state of the second ready signal  15   r   2 , i.e., if the second ready signal  15   r   2  is asserted at a logic 1, the output status signal  17  remains de-asserted in a logic 1 state, and vice versa. 
     The output status signal  17  is further affected by the various enablement  11  and ready  15   r  signals as follows. When neither of the two voltage regulators  14   a ,  14   b  is enabled, their enablement signals  11   a ,  11   b  are de-asserted at logic 0 states. When one regulator is operating, i.e., after its enablement signal  11  has been asserted, the power on reset signal  17  is immediately asserted and remains in its logic 0 state for at least the duration of the long delay end of count sequence (e.g., 50 milliseconds). This signal  17  is de-asserted to its logic 1 state if and only if the corresponding ready signal  15   r  remains asserted continuously without any glitches for the duration of the long delay end of count sequence. Thereafter, the output status signal  17  follows the state of the corresponding ready signal  15   r.    
     When one voltage regulator is enabled and its output has become stabilized, i.e., its enablement  11  and ready  15   r  signals are asserted, and then a second regulator is enabled, as indicated by its corresponding enablement signal  11 , the output status signal  17  is not affected by the status of the second regulator and remains in its de-asserted logic 1 state between the time of the assertion of the second enablement signal  11  and the termination of the corresponding short delay end of count sequence. If the first ready signal remains asserted at the end of the short delay count sequence, the output status signal  17  responds to the states of both of the input ready signals  15   r   1 ,  15   r   2 , i.e., de-assertion of either ready signal  15   r   1 ,  15   r   2  will cause the power on reset signal  17  to become asserted (logic 0). 
     If both enablement signals  11   a ,  11   b  are asserted concurrently, the power on reset signal  17  becomes asserted (logic 0) and remain so until one of the ready signals  15   r   1 ,  15   r   2  is maintained at its asserted state (logic 1) without interruption for the duration of the long delay count sequence. Following this, the output signal  17  becomes de-asserted (logic 1). Thereafter, the output signal  17  responds to, i.e., follows, the de-assertion of either of the ready signals  15   r   1 ,  15   r   2 . 
     Referring to  FIG. 4 , with reference to the discussion above for operation with only one voltage regulator enabled, the timing and states of the enablement signal  11   a , ready signal  15   r   1  and output signal  17  would appear as shown. As discussed above, the delay interval TL between the rising edge of the ready signal  15   r   1  and rising edge of the output signal  17  is equal to the long delay end of count sequence. Time interval TD is the time interval associated with the stabilization of the output voltage of the voltage regulator, e.g., the time necessary to achieve the predetermined 90% voltage level. 
     Referring to  FIG. 5 , regarding the discussion above for operation with one regulator enabled and stabilized and second regulator becoming enabled, the corresponding enablement, ready and output signals would appear as shown. As discussed above, if the second ready signal is not asserted during the masking interval TS, as represented by the dashed line, or if it remains de-asserted, then the power on reset signal  17  becomes asserted as represented by the dashed line. 
     Referring to  FIGS. 6 and 7 , the logic operation and states for the power on reset and status signal  17  can be summarized as shown in the table and depicted as shown in the signal timing diagram. 
     Various other modifications and alternations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and the spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.