Abstract:
Disclosed is a method and circuit for variably controlling a delay line for a read data capture timing window. In one embodiment, the circuit includes a variably controlled delay circuit coupled to a FIFO. The variably controlled delay circuit receives an input strobe signal. The variably controlled delay circuit also receives a multibit control code. The variably controlled delay circuit transmits the input strobe signal after a time delay, wherein the time delay varies according to the multibit control code. The FIFO is coupled to the variably controlled delay circuit and receives the time delayed strobe signal therefrom. The FIFO receives an input data bit signal. The FIFO stores the input data bit signal in response to receiving the time delayed strobe signal.

Description:
BACKGROUND OF THE INVENTION 
     FIG. 1  illustrates a microprocessor  10  coupled to a memory device  12  via data bus  14 . Data bus  14  includes a plurality of conductive lines (not shown) for transmitting data bit signals and a strobe signal in parallel between memory device  12  and microprocessor  10 . As used herein, a memory device may include SRAMs, DRAMs, or other memory capable of storing digital data. 
   Microprocessor  10  includes a plurality of input/output (“I/O”) devices (not shown in  FIG. 1 ) coupled to respective conductive lines of data bus  14 . These I/O devices are capable of transmitting or receiving data bit signals.  FIG. 2  shows relevant components of I/O devices of microprocessor  10 . More particularly,  FIG. 2  shows a plurality of FIFOs  20 ( 0 ) through  20 ( n ) each one of which is contained in a respective I/O device.  FIG. 2  also shows a strobe buffer  22 . Lastly,  FIG. 2  shows a plurality of data buffers  24 ( 0 ) through  24 ( n ) each one of which is contained in a respective I/O device. 
   Data buffers  24 ( 0 ) through  24 ( n ) are coupled between respective data inputs of FIFOs  20 ( 0 ) through  20 ( n ) and respective conductive lines of data bus  14 . The output of strobe buffer  22  is coupled between a conductive line of data bus  14  and FIFOs  20 ( 0 ) through  20 ( n ). For purposes of definition, two devices (e.g., a buffer and a FIFO) may be coupled together directly by a conductor or data link, or indirectly via a third device. For example,  FIG. 2  show data buffers  24 ( 0 ) through  24 ( n ) coupled directly to data inputs of FIFOs  20 ( 0 ) through  20 ( n ), respectively. Further, although not shown, buffers  24 ( 0 ) through  24 ( n ) are coupled indirectly to respective data bus lines via output bumps of microprocessor  10  and conductive traces of a semiconductor packaging in which microprocessor is contained. 
   Data bus  14  transmits the strobe signal in parallel with data bit signals. The strobe signal is essentially a clock having a 50% duty cycle. Memory  12  transmits data at a double data rate (DDR). More particularly, I/O devices of memory  12  transmit a set of data bit signals D in ( 0 ) through D in (n) with each transition edge (i.e., a rising edge and falling edge) of the strobe signal. 
   Data bit signals D in ( 0 ) through D in (n) are received by data buffers  24 ( 0 ) through  24 ( n ) around the same time strobe buffer  22  receives the transition edges of the strobe signal. Buffers  22  and  24 ( 0 ) through  24 ( n ), when the enable signal provided thereto are asserted, transmit the strobe signal and data bit signals D in ( 0 ) through D in (n) to FIFOs  20 ( 0 ) through  20 ( n ). 
   FIFOs  20 ( 0 ) through  20 ( n ) capture or store data bit signals D in ( 0 ) through D in (n), respectively, upon the transition edges of the strobe signal provided thereto by strobe buffer  22 . FIFOs  20 ( 0 ) through  20 ( n ) store data bit signals D in ( 0 ) through D in (n), respectively, for subsequent processing by the core of microprocessor  10 . It is essential that that FIFOs  20 ( 0 ) through  20 ( n ) receive the transition edges of the strobe signal during a read data capture timing window. The read data capture timing window is a period of time when: (1) all data bit signals D in ( 0 ) through D in (n) are present at the inputs of FIFOs  20 ( 0 ) through  20 ( n ) with sufficient set-up time before FIFOs  20 ( 0 ) through  20 ( n ) receive transition edges of the strobe signal from buffer  22 , and; (2) all data bit signals D in ( 0 ) through D in (n) are present at the inputs of FIFOs  20 ( 0 ) through  20 ( n ) with sufficient hold time after FIFOs  20 ( 0 ) through  20 ( n ) receive the transition edges of the strobe signal from buffer  22 . If the transition edges of the strobe signal do not arrive at FIFOs  20 ( 0 ) through  20 ( n ) during the read capture timing window, false data will be stored in FIFOs  20 ( 0 ) through  20 ( n ). 
   Transmission of the strobe signal and data bit signals D in ( 0 ) through D in (n) between memory device  12  and FIFOs  20 ( 0 ) through  20 ( n ), are subject to unexpected delays. Because of relative delays in the transmission of the data bit signals D in ( 0 ) through D in (n) to the inputs of FIFOs  20 ( 0 ) through  20 ( n ), the read capture timing window may be substantially small. Additionally, because of unexpected delays, the transition edges of the strobe signal may arrive at FIFOs  20 ( 0 ) through  20 ( n ) with an unexpected delay relative to the read capture timing window. 
   A variety of factors induce transmission delay in the data bit and strobe signals. For example, the conductive line of bus  14  that transmits the strobe signal may be shorter or longer in length than one or more of the conductive lines of bus  14  that transmit the data bit signals. Another source of relative signal delay relates to variations in the process used to manufacture microprocessor  10 . Microprocessors are manufactured using complex equipment and processes. Variations in the equipment and processes may result in unexpected physical variations of the structure of, for example, the transistors in strobe buffer  22 . These physical variations in transistor structure may introduce unexpected delays in the strobe signal transmitted through strobe buffer  22 . 
   The unexpected delays described above are fixed. Delays in the strobe and data bit signals may vary. For example, delays in the strobe signal may vary during operation of the microprocessor due to changes in temperature of strobe buffer  22  or changes in the power supply voltage provided to strobe buffer  22 . Increases in operating temperature of strobe buffer  22  will typically increase delay in strobe signal transmission therethrough, and vice versa. An increase power supply voltage provided to strobe buffer  22  will typically decrease delay in strobe signal transmission therethrough, and vice versa. 
   As noted above, the transition edges of strobe signal and the data bit signals D in ( 0 ) through D in (n) are received by buffers of microprocessor  12  around the same point in time.  FIG. 3  is a timing diagram illustrating the data bit signal D in ( 0 ) and the strobe signal provided to inputs of FIFO  20 ( 0 ). Except for relative delays between data signals, inputs to the remaining FIFOs  20 ( 1 ) through  20 ( n ) are identical. Strobe buffer  22  is designed to delay transmission of the strobe signal by a fixed amount of time (e.g., 25% of the strobe signal&#39;s duty cycle) so that FIFOs  20 ( 0 ) through  20 ( n ) receive the transition edges (e.g., rising edge at time=t 1 ) within a read capture timing window thereof. 
     FIG. 3  illustrates the relative effects of unexpected delays on the strobe signal. In  FIG. 3 , unexpected delays may cause the transition edges of the strobe signal to move in time relative to data bit signal D in ( 0 ) in either the D positive  or D negative  directions by an undetermined magnitude. Unfortunately, if the magnitude of D positive  or D negative  is great enough, the transition edges of the strobe signal may fall outside the read capture timing window. 
   SUMMARY OF THE INVENTION 
   Disclosed is a method and circuit for variably controlling a delay line for read data capture timing window. In one embodiment, the circuit includes a variably controlled delay circuit coupled to a FIFO. The variably controlled delay circuit receives an input strobe signal. The variably controlled delay circuit also receives a multibit control code. The variably controlled delay circuit transmits the input strobe signal after a time delay, wherein the time delay varies according to the multibit control code. The FIFO is coupled to the variably controlled delay circuit and receives the time delayed strobe signal therefrom. The FIFO receives an input data bit signal. The FIFO stores the input data bit signal in response to receiving the time delayed strobe signal. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention may be better understood, and its numerous objects, features and advantages made apparent to those skilled in the art by referencing the accompanying drawings. The use of the same reference number throughout the figures designates a like or similar element. 
       FIG. 1  illustrates a microprocessor coupled to a memory device; 
       FIG. 2  illustrates relevant components of I/O devices of the microprocessor shown in  FIG. 1 ; 
       FIG. 3  illustrates relative effects of delays on the strobe signal received by the FIFOs of  FIG. 2 ; 
       FIG. 4  illustrates a microprocessor coupled to a memory device; 
       FIG. 5  shows relevant components of I/O devices of the microprocessor of  FIG. 4 ; 
       FIG. 6  illustrates relative effects of delays on the strobe signal received by the FIFOs of  FIG. 5 ; 
       FIG. 7  illustrates one embodiment of the variable delay circuit employed in  FIG. 5 ; 
       FIG. 8  illustrates one embodiment of one of the controllable delay circuits shown in  FIG. 7 ; 
       FIG. 9  illustrates one embodiment of a controllable delay circuit shown in  FIG. 8 ; 
       FIG. 10  illustrates another embodiment of the controllable delay circuit of  FIG. 8 ; 
       FIG. 11  illustrates another embodiment of one of the controllable delay circuits shown in  FIG. 7 . 
   

   While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. However, the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention as defined by the appended claims. 
   DETAILED DESCRIPTION 
   Computer systems, including computer servers, employ one or more microprocessors coupled to one or more memory devices, via a serial or parallel data bus. The present invention will be described with reference to a microprocessor coupled to a memory device via a parallel data bus, it being understood that the present invention should not be limited thereto. The term device includes circuits of transistors coupled together to perform an electronic function. 
     FIG. 4  is a block diagram illustrating a microprocessor  26  coupled to a memory device  30  via a data bus  32 . Microprocessor  26  employs the present invention. The present invention may find application in devices other than a microprocessor and should not be limited to use in a microprocessor. For example, the present invention may find application in memory  30 . 
   Data bus  32  includes a plurality of conductive lines (not shown) for transmitting data bit signals and a strobe signal in parallel between memory device  30  and microprocessor  26 . Microprocessor  26  includes a plurality of I/O devices (not shown in  FIG. 4 ) coupled to respective conductive lines of data bus  32 . These I/O devices are capable of transmitting or receiving data bit signals. 
     FIG. 5  shows relevant components of I/O devices of microprocessor  10 . More particularly,  FIG. 5  shows a plurality of FIFOs  34 ( 0 ) through  34 ( n ) each one of which is contained in a respective I/O device.  FIG. 5  shows a plurality of data buffers  36 ( 0 ) through  36 ( n ) each one of which is contained in a respective I/O device of microprocessor  26 .  FIG. 5  shows a strobe buffer  40 . Lastly,  FIG. 5  shows a variable control delay circuit  42 . 
   Data buffers  36 ( 0 ) through  36 ( n ) are coupled between respective data inputs of FIFOs  34 ( 0 ) through  34 ( n ) and respective conductive lines of data bus  32 . Although not shown, buffers  36 ( 0 ) through  36 ( n ) are coupled to respective data bus lines via output bumps of microprocessor  26  and conductive traces of a semiconductor packaging in which microprocessor  26  is contained. The output of strobe buffer  40  is coupled between a conductive line of data bus  14  and variable delay circuit  42 . The output of variable delay circuit  42  is coupled to FIFOs  34 ( 0 ) through  34 ( n ). 
   Data bus  32  transmits the strobe signal in parallel with data bit signals. In one embodiment, the strobe signal is essentially a clock signal having a 50% duty cycle. Memory  30  transmits data at DDR. The present invention, it is understood, should not be limited to use in a system employing a DDR data bus. 
   Data bit signals D in ( 0 ) through D in (n) are received by data buffers  36 ( 0 ) through  36 ( n ) around the same time strobe buffer  40  receives transition edges of the strobe signal. Buffers  36 ( 0 ) through  36 ( n ), when the enable signals provided thereto are asserted, transmit the strobe signals and data bit signals D in ( 0 ) through D in (n) to FIFOs  34 ( 0 ) through  34 ( n ). Buffer  40  transmits the strobe signal to variable delay circuit  42 . Variable delay circuit  42  transmits the strobe signal to FIFOs  34 ( 0 ) through  34 ( n ). 
   FIFOs  34 ( 0 ) through  34 ( n ) capture or store data bit signals D in ( 0 ) through D in (n), respectively, upon the transition edges of the strobe signal provided thereto by variable delay circuit  42 . It is essential that FIFOs  34 ( 0 ) through  34 ( n ) receive the transition edges of the strobe signal during the read capture timing window thereof. 
   The data bit signals D in ( 0 ) through D in (n) and/or the strobe signal may be subject to one or more of the unexpected fixed or variable delays mentioned above. Variable delay circuit  42  operates to offset the one or more unexpected fixed or variable delays of strobe signal transmission.  FIG. 6  is a timing diagram illustrating the data bit signal D in ( 0 ) and the strobe signal provided to inputs of FIFO  34 ( 0 ). Except for relative delays between data signals, inputs to the remaining FIFOs  34 ( 1 ) through  34 ( n ) are identical.  FIG. 6  shows the strobe signal after delayed transmission by variable delay circuit  42 . Variable delay circuit delays the strobe signal by a first delay time in response to receiving a first variable delay control code. Ideally, the strobe signal is delayed by variable delay circuit  42  so that its transition edges (e.g., the falling edge at time=t 2 ) fall within the read capture timing window of FIFOs  34 ( 1 ) through  34 ( n ). 
   With continuing reference to  FIGS. 5 and 6 , during operation, one or more variable delays may unexpectedly cause the transition edges of the strobe signal to drift in either the D positive  or D negative  directions by an undetermined magnitude. For example, the temperature of strobe buffer  40  may decrease or the magnitude of the power supply provided to buffer  40  may increase thereby causing the transition edges of the strobe signal to drift in the D negative  direction. This drift may cause the transition edges to fall outside the read capture timing window. In response to a decrease in temperature, an increase in the power supply voltage, or both, a second variable delay code may be generated. The variable delay circuit  42  receives the second variable delay code, and in response variable delay circuit  42  increases the delay of strobe signal transmission therethrough so that the transition edges of the strobe signal move in the D positive  direction. After further operation, the temperature of strobe buffer  40  may increase or the magnitude of the power supply provided to buffer  40  may decrease thereby causing the transition edges of the strobe signal to drift in the D positive  direction. This drift may cause the transition edges to again fall outside the read capture timing window. In response to an increase in temperature, a decrease in the power supply voltage, or both, a third variable delay code may be generated. The variable delay circuit  42  receives the third variable delay code, and in response variable delay circuit  42  decrease the delay of strobe signal transmission therethrough so that the transition edges of the strobe signal move in the D negative  direction. 
   A variable delay control code generator (not shown) is provided for generating an initial and subsequent variable control delay codes to variable delay circuit  42 . In one embodiment, the variable delay control code generator generates the initial variable delay control code in response to: an initial temperature of the variable delay control code generator, the microprocessor  26 , the strobe buffer  42 , and/or one or more of the data buffers  34 ( 0 ) through  34 ( n ); an initial magnitude of the power supply voltage provided to the variable delay circuit, the microprocessor  10 , the strobe buffer and/or one or more of the data buffers  34 ( 0 ) through  34 ( n ); unexpected variations in the transistors that form the variable delay control code generator, the microprocessor  26 , the strobe buffer  42 , and/or one or more of the data buffers  34 ( 0 ) through  34 ( n ); or other factors; or any combination of the foregoing factors. In one embodiment, the variable delay code generator generates the subsequent variable delay codes in response to: a change in temperature of the variable delay control code generator, the microprocessor  26 , the strobe buffer  42 , and/or one or more of the data buffers  34 ( 0 ) through  34 ( n ); a change in the magnitude of the power supply voltage provided to the variable delay circuit, the microprocessor  10 , the strobe buffer and/or one or more of the data buffers  34 ( 0 ) through  34 ( n ); or any combination of the foregoing factors. In one embodiment, the variable delay control code represents an average of a pull up control code and a pull down control code. The pull up and pull down control codes can be generated by circuits described in U.S. Pat. No. 6,060,907 which is incorporated herein by reference in its entirety. The average of pull up and pull down control codes can be generated by a circuit described in copending U.S. patent application Ser. No. 10/158,695 filed May 30, 2002, entitled Average Code Generation Circuit by Cong Khieu and Louise Gu, which is incorporated herein by reference in its entirety. 
   Variable delay circuit  42 , as noted above, operates to adjust strobe signal delay in accordance with the variable delay code provided thereto.  FIG. 7  illustrates in block diagram form, one embodiment of the variable delay circuit  42 . More particularly, variable delay circuit  42  of  FIG. 7  includes controllable delay circuits  44 ( 0 ) through  44 ( m ) coupled in series between strobe signal input and a strobe signal output. In operation, controllable delay circuit  44 ( 0 ) receives the strobe signal. Controllable delay circuits  44 ( 0 ) through  44 ( m ) receive control bits CB( 0 ) through CB(m), respectively, of the variable delay control code provided to variable delay circuit  42 . 
   In one embodiment, each controllable delay circuit  44 ( 0 ) through  44 ( m ) transmits the strobe signal provided at its input via a short transmission delay circuit or a long transmission delay circuit. The transmission delays of the two circuits are distinct from each other. The transmission circuit used to transmit the strobe signal in each of the delay circuits  44 ( 0 ) through  44 ( m ) depends on the control bit provided thereto. For example, controllable delay circuit  44 ( 0 ) transmits the strobe signal to controllable delay circuit  44 ( 1 ) via the short transmission delay circuit of controllable delay circuit  44 ( 0 ) if CB( 0 ) provided thereto is as a logical one. In contrast, if CB( 0 ) is provided to controllable delay circuit  44 ( 0 ) as a logical zero, then controllable delay circuit  44 ( 0 ) transmits the strobe signal via its long transmission delay circuit. Each of the controllable delay circuits  44 ( 0 ) through  44 ( m ) operates in a substantially similar manner. 
   The time delay of the short transmission delay circuits in the controllable delay circuits  44 ( 0 ) through  44 ( m ) may be equal to each other in one embodiment or different from each other in another embodiment. The time delay of the long transmission delay circuits of the controllable delay circuits  44 ( 0 ) through  44 ( m ) may be equal to each other in one embodiment or different from each other in another embodiment. 
     FIG. 8  illustrates one embodiment of one of the controllable delay circuits  44 ( x ) shown in  FIG. 7 . More particularly,  FIG. 8  shows an inverting gate  52 , a long transmission delay circuit  54 , a short transmission delay circuit  56 , a multiplexer  60 , and an inverting gate  62 . The long transmission delay circuit  54  has an input and an output between which a signal is transmitted. Signals are transmitted through long transmission delay circuit  54  with a time delay T long . Short transmission delay circuit includes an input and an output between which signals are transmitted with a time delay T short . T long  is greater than T short . 
   The outputs of the long and short transmission delay circuits  54  and  56 , respectively, are provided to inputs of multiplexer  60 . A selector input or a control input receives one of the bits CB(x) of the variable delay control code. In response to receiving CB(x), multiplexer  60  selects or multiplexes one of the inputs to its output, which in turn is provided to inverting gate  62 . Thus, controllable delay circuit  44  shown in  FIG. 8  has a variable delay between its input and output which depends upon the state of the control bit CB(x) provided thereto. 
     FIG. 9  illustrates one embodiment of a controllable delay circuit  44 ( x ) shown in  FIG. 8 . More particularly,  FIG. 9  shows that multiplexer  60  consists of a pair of n-channel field effect transistors (FETs)  64  and  66  and a pair of p-channel FETs  70  and  72 . The long transmission delay circuit  54  shown in  FIG. 9  includes a pair of inverter gates  74  and  76 , n-channel FET  80 , and p-channel FET  82 . It is noted that the inverse of control bit CB(x) is provided to the gates of n-channel FET  64  and p-channel FET  72 . The inverse of CB(x) may be provided by a separate inverter (not shown) contained within the controllable delay circuit  44 ( x ) shown in  FIG. 9 . As will be appreciated by one of ordinary skill in the art, the signal transmission delay of circuit  54 , will be longer than the signal delay transmission of circuit  56 . 
     FIG. 10  illustrates another embodiment of the controllable delay circuit  44 ( x ) of  FIG. 8 . The long transmission delay circuit  54  shown in  FIG. 10  includes inverter gates  84  and  86 , and capacitor  90 . The short transmission delay circuit  56  shown in  FIG. 10 , like the short transmission delay circuit  56  shown in  FIG. 9 , consists of only a conductor. As can be appreciated by one of ordinary skill in the art, the signal transmission delay associated with circuit  54  shown in  FIG. 10  will be substantially longer than the signal transmission delay of the conductor of circuit  56 . 
     FIG. 11  illustrates another embodiment of one of the controllable delay circuits  44 ( x ) shown in  FIG. 7 . More particularly, the controllable delay circuit  44 ( x ) shown in  FIG. 11  includes a pair of inverting gates  92  and  94 , an n-channel FET  96 , p-channel FET  100 , and a capacitor  102 . The gate of p-channel FET  100  receives one bit CB(x) of the multi-bit variable control code, while the gate of n-channel FET  96  receives the inverse of CB(x). 
   Although the present invention has been described in connection with several embodiments, the invention is not intended to be limited to the specific forms set forth herein. On the contrary, it is intended to cover such alternatives, modifications, and equivalents as can be reasonably included within the spirit and scope of the invention as defined by the appended claims.