Abstract:
A method for manufacturing printed wiring board including preparing an electronic component having first and second surfaces and electrode on the first surface, forming in an adhesive tape a mark, mounting based on the mark the component on the tape such that the second surface faces the adhesive of the tape, forming another mark on insulative substrate having first and second surfaces, forming in the substrate an opening larger than the component, mounting based on the marks the substrate on the tape such that the component is in the opening of the substrate, fixing the component to the substrate using resin, forming an insulation layer on the first surface of the substrate where the component is accommodated, removing the tape, forming in the layer an opening reaching the electrode, forming a conductive circuit on the layer, and forming in the opening of the layer a via connected to the electrode.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application claims the benefits of priority to U.S. Application No. 61/141,143, filed Dec. 29, 2008. The contents of that application are incorporated herein by reference in their entirety. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention is related to a printed wiring board with a built-in electronic component and its manufacturing method. As for the built-in electronic component, for example, active components such as IC chips made of semiconductor elements, or passive components such as resistors, capacitors or coils are listed. 
         [0004]    2. Discussion of the Background 
         [0005]    WO2007/107630, the content of which are incorporated herein by reference in their entirety, describes a method for mounting an IC chip on a support plate where an adhesive is applied, laminating resin insulation layers, and then removing the support plate. 
       SUMMARY OF THE INVENTION 
       [0006]    A method for manufacturing a printed wiring board according to one aspect of the present invention includes the following: preparing an electronic component having a first surface and a second surface opposite the first surface, and having a first electrode formed on the first surface; in adhesive tape, forming a first alignment mark for mounting the electronic component; based on the first alignment mark, mounting the electronic component on the adhesive tape in such a way that its second surface faces the adhesive side of the adhesive tape; forming a second alignment mark on an insulative substrate having a first surface and a second surface opposite the first surface; in the insulative substrate, forming an opening section larger than the external shape of the electronic component; based on the first and second alignment marks, mounting the insulative substrate on the adhesive side of the adhesive tape in such a way that the electronic component is accommodated in the opening section of the insulative substrate; fixing the electronic component to the insulative substrate using resin material; forming a first resin insulation layer on the first surface of the insulative substrate in which the electronic component is accommodated; removing the adhesive tape; in the first resin insulation layer, forming an opening that reaches the first electrode of the electronic component; forming a first conductive circuit on the first resin insulation layer; and in the opening of the first resin insulation layer, forming a via conductor that is connected to the first electrode of the electronic component. 
         [0007]    A method for manufacturing a printed wiring board according to another aspect of the present invention includes the following: preparing an electronic component having a first surface and a second surface opposite the first surface, and having a first electrode formed on the first surface; in an adhesive tape, forming a first alignment mark for mounting the electronic component; based on the first alignment mark, mounting the electronic component on the adhesive tape in such a way that its second surface faces the adhesive side of the adhesive tape; forming a second alignment mark on an insulative substrate having a first surface and a second surface opposite the first surface; in the insulative substrate, forming an opening section larger than the external shape of the electronic component; based on the first and second alignment marks, mounting the insulative substrate on the adhesive side of the adhesive tape in such a way that the electronic component is accommodated in the opening section of the insulative substrate; fixing the electronic component to the insulative substrate using resin material; removing the adhesive tape; forming a first resin insulation layer and a second resin insulation layer on the first and second surfaces respectively of the insulative substrate in which the electronic component is accommodated; in the first resin insulation layer, forming an opening that reaches the first electrode of the electronic component; forming a through-hole that penetrates the first and second resin insulation layers and the insulative substrate; and forming a first conductive circuit and a second conductive circuit on the first and second resin insulation layers respectively, while forming in the opening of the first resin insulation layer a via conductor that connects the first conductive circuit and the first electrode of the electronic component, and forming on the inner wall of the through-hole a through-hole conductor that connects the first and second conductive circuits. 
         [0008]    Also, a printed wiring board according to yet another aspect of the present invention includes a core substrate having a first surface and a second surface opposite the first surface, and an opening section larger than the outer diameter of an electronic component to be accommodated; an electronic component accommodated in the opening section, having a first surface and a second surface opposite the first surface, and having a first electrode formed on the first surface; a first resin insulation layer formed on the first surface of the core substrate; a first conductive circuit formed on the first resin insulation layer; and in the first resin insulation layer, a first via conductor which is formed in an opening reaching the first electrode of the electronic component, and which connects the first conductive circuit and the first electrode. The gaps between the electronic component and the inner walls of the opening section of the core substrate are filled with resin made up of resin material and resin ingredients drained from the first resin insulation layer. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein: 
           [0010]      FIG. 1  is a cross-sectional view schematically showing a printed wiring board according to an embodiment of the present invention; 
           [0011]      FIG. 2A  is a cross-sectional view showing a first step to mount a chip capacitor on an adhesive sheet; 
           [0012]      FIG. 2B  is a cross-sectional view showing a second step to mount a chip capacitor on the adhesive sheet; 
           [0013]      FIG. 2C  is a cross-sectional view showing a third step to mount a chip capacitor on the adhesive sheet; 
           [0014]      FIG. 2D  is a cross-sectional view showing a fourth step to mount a chip capacitor on the adhesive sheet; 
           [0015]      FIG. 3A  is a cross-sectional view showing a first step to form a core substrate; 
           [0016]      FIG. 3B  is a cross-sectional view showing a second step to form a core substrate; 
           [0017]      FIG. 3C  is a cross-sectional view showing a third step to form a core substrate; 
           [0018]      FIG. 3D  is a cross-sectional view showing a fourth step to form a core substrate; 
           [0019]      FIG. 4A  is a cross-sectional view showing a first step to fix a chip capacitor to the core substrate; 
           [0020]      FIG. 4B  is a cross-sectional view showing a second step to fix a chip capacitor to the core substrate; 
           [0021]      FIG. 4C  is a cross-sectional view showing a third step to fix a chip capacitor to the core substrate; 
           [0022]      FIG. 5A  is a cross-sectional view showing a first step to form resin insulation layers on the substrate shown in  FIG. 4C ; 
           [0023]      FIG. 5B  is a cross-sectional view showing a second step to form resin insulation layers on the substrate shown in  FIG. 4C ; 
           [0024]      FIG. 6  is a cross-sectional view showing a step to form through-holes and via holes in the substrate shown in  FIG. 5B ; 
           [0025]      FIG. 7A  is a cross-sectional view showing a step to form conductive patterns on the resin insulation layers; 
           [0026]      FIG. 7B  is a cross-sectional view showing a step to form conductive patterns on the resin insulation layers; 
           [0027]      FIG. 7C  is a cross-sectional view showing a step to form conductive patterns on the resin insulation layers; 
           [0028]      FIG. 8A  is a cross-sectional view showing another example (a first step) to form a resin insulation layer; 
           [0029]      FIG. 8B  is a cross-sectional view showing another example (a second step) to form a resin insulation layer; 
           [0030]      FIG. 8C  is a cross-sectional view showing another example (a third step) to form a resin insulation layer; 
           [0031]      FIG. 9A  is a cross-sectional view showing another example (a first step) to form conductive patterns on the resin insulation layers; and 
           [0032]      FIG. 9B  is a cross-sectional view showing another example (a second step) to form conductive patterns on the resin insulation layers; 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0033]    The embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals designate corresponding or identical elements throughout the various drawings. 
         [0034]    As shown in  FIG. 1 , printed wiring board  10  according to the present embodiment is mainly formed with core substrate  11 , chip capacitor  20 , resin insulation layers  131 ,  132  laminated respectively on both surfaces of core substrate  11  and chip capacitor  20 , and conductive patterns (conductive circuits)  113 ,  114  formed respectively on resin insulation layers  131 ,  132 . 
         [0035]    Core substrate  11  has rigid base material  100 , and on both main surfaces of rigid base material  100 , conductive patterns (conductive circuits)  111 ,  112  made of, for example, copper are formed. Conductive patterns  111 ,  112  are electrically connected to further upper-layer conductive patterns at their respective predetermined spots. As for rigid base material  100 , the following may be used: namely, glass cloth or the like with an approximate thickness of 0.1-1.0 mm impregnated with resin such as BT (bismaleimide triazine) resin or epoxy resin, which is then cured. 
         [0036]    In rigid base material  100 , opening section ( 100   a ) is formed, and chip capacitor  20  is arranged in opening section ( 100   a ). Gaps between chip capacitor  20  and rigid base material  100  are filled with filler resin ( 100   b ), which secures chip capacitor  20 . As such, chip capacitor  20  is built (embedded) in core substrate  11 . As for material for filler resin ( 100   b ), it is efficient to use material such as that having lower coefficients of elasticity and thermal expansion than at least those of the material forming rigid base material  100 . Specifically, for example, bismaleimide resin containing fumed silica and polytetrafluoroethylene (PTFE) as filler may be used. 
         [0037]    On both main surfaces of core substrate  11 , resin insulation layers  131 ,  132  are laminated. As for material forming resin insulation layers  131 ,  132 , for example, thermosetting resins such as epoxy resin, BT resin, polyimide resin, olefin resin or the like, or a composition of thermosetting resins and thermoplastic resins, may be used. 
         [0038]    Conductive patterns  113 ,  114  and terminals  21  of chip capacitor  20  are electrically connected by means of via conductors  121 ,  122 . Via conductors  121 ,  122  are filled vias made by filling via holes with copper plating or the like. 
         [0039]    Also, in printed wiring board  10 , through-holes  140  are formed. Conductive pattern  113  and conductive pattern  114  are electrically connected by means of through-hole conductors  141 . 
         [0040]    Printed wiring board  10  functions as an electronic device by electrically connecting conductive patterns  113 ,  114  to further upper-layer conductive patterns according to requirements, or by being mounted on a motherboard or the like through flip-chip connection or wire bonding. 
         [0041]    When manufacturing such printed wiring board  10 , first as shown in  FIG. 2A , rectangular jig plate  501  (a support plate) made of metal, for example, is prepared. Then, as shown in  FIG. 2B , alignment marks ( 501   a ) for determining positions are formed by making through-holes at four corners of jig plate  501  using, for example, a drill or the like. In the following, alignment marks ( 502   a ) are also formed in adhesive layer  502  made of, for example, a UV tape having adhesiveness on both sides. Then, as shown in  FIG. 2C , based on alignment marks ( 501   a ,  502   a ), adhesive layer  502  is laminated on one main surface of jig plate  501 . Accordingly, adhesive sheet  500  with an adhesive surface is formed. 
         [0042]    As for jig plate  501 , for example, a metal plate or a resin plate may be used. In addition, as for adhesive layer  502 , any type of adhesive material may be used. Also, adhesive layer  502  does not have to be formed on the entire main surface of jig plate  501 , but for example, adhesive layer  502  may be formed only in a partial region on the main surface. Furthermore, alignment marks ( 501   a ,  502   a ) may also be any type other than through-holes, as long as they can be recognized (for example, optically recognized) at the time of alignment. If the alignment marks are configured to be through-holes, then pins or the like may be inserted into such through-holes, and based on such pins, jig plate  501  and adhesive layer  502  may be laminated. 
         [0043]    Next, as shown in  FIG. 2D , by aligning based on alignment marks ( 501   a ), chip capacitor  20  is mounted on adhesive sheet  500 . In doing so, chip capacitor  20  is fixed to adhesive sheet  500 . 
         [0044]    Here, before describing the next step, a step conducted prior to the step, namely a step to manufacture core substrate  11 , is described. When manufacturing core substrate  11 , first, as shown in  FIG. 3A , for example, conductive films ( 111   a ,  112 ) made of copper, for example, are formed (for example, laminated) on both main surfaces of rigid base material  100  respectively. After that, by conducting, for example, a predetermined lithography process (preliminary treatment, laminating, exposing and developing, etching, removing the film, inner-layer inspection and so forth), conductive films ( 111   a ,  112   a ) are patterned. Accordingly, conductive patterns  111 ,  112  and alignment marks ( 112   b ) are formed as shown in  FIG. 3B , for example. 
         [0045]    In the following, based on alignment marks ( 112   b ), opening section ( 100   a ), into which chip capacitor  20  will be built, is formed (drilled) at the predetermined section of rigid base material  100  using a drill or the like as shown in  FIG. 3C , for example. Accordingly, core substrate  11  is obtained as shown in  FIG. 3D . 
         [0046]    In the next step, core substrate  11  shown in  FIG. 3D  is mounted on adhesive sheet  500  in such a way that chip capacitor  20  will be accommodated in opening section ( 100   a ). At that time, based on alignment marks ( 501   a ,  502   a ) and alignment marks ( 112   b ) of core substrate  11 , chip capacitor  20  is aligned so that it will be arranged in opening section ( 100   a ). In doing so, as shown in  FIG. 4A , core substrate  11 , as well as chip capacitor  20 , is adhered and fixed to adhesive sheet  500 . Since core substrate  11  and chip capacitor  20  are aligned based on alignment marks ( 501   a ,  502   a ), chip capacitor  20  may be accurately positioned inside opening section ( 100   a ) of core substrate  11 . 
         [0047]    Next, as shown in  FIG. 4B , by vacuum printing (applying in a vacuum condition) for example, gaps between chip capacitor  20  and the inner walls of core substrate  11  in opening section ( 100   a ) are filled with filler resin ( 100   b ). As for the material for filler resin ( 100   b ), for example bismaleimide resin is used which contains fumed silica and PTFE as filler. Any method is used for filling filler resin  100 ; for example, it may be injected using a dispenser. However, vacuum printing is preferred to suppress voids or the like. 
         [0048]    At that point, glass cloth or the like contained in core substrate  11  is preferred to protrude slightly from the wall surface of opening portion ( 100   a ). Under such a condition, adhesiveness between filler resin ( 100   b ) and core substrate  11  will be further enhanced. 
         [0049]    After that, filler resin ( 100   b ) is semi-cured or completely cured by curing (thermal treatment). In the following, as shown in  FIG. 4C , for example, adhesive sheet  500  is peeled and removed from core substrate  11  and chip capacitor  20 . 
         [0050]    The conditions for curing (thermal treatment) of filler resin ( 100   b ) are 150° C. for 60 minutes, for example. In addition, properties of filler resin ( 100   b ) after curing are preferred to be set as follows: namely, elastic modulus (by a DMA) of 0.5 GPa (−40° C.), 0.11 GPa (25° C.) and 0.05 GPa (150° C.); glass transition temperature Tg (by a TMA) of −70° C.; and coefficient of thermal expansion (CTE (X,Y) α ½) of 59/130 (ppm/° C.) 
         [0051]    In the following, each surface of conductive patterns  111 ,  112  is roughened. Then, on both surfaces of the resultant structure, thermosetting insulative resin films ( 131   a ,  132   a ) are arranged as shown in  FIG. 5A , for example, and thermopressed (laminated) using a vacuum laminator with thermopressing functions. Accordingly, resin insulation layers  131 ,  132  are formed as shown in  FIG. 5B . At that point, since chip capacitor  20  is fixed to core substrate  11  by filler resin ( 100   b ), thermosetting insulative resin films ( 131   a ,  132   a ) may be laminated all at once on both surfaces of core substrate  11 . During that time, since resin ingredients are drained out of thermosetting insulative resin films ( 131   a ,  132   a ), even if there are gaps between chip capacitor  20  and the inner walls of core substrate  11 , the gaps are completely filled by such resin ingredients. 
         [0052]    Other than the above method for forming resin insulation layers  131 ,  132  shown in  FIG. 4C  through  FIG. 5B , the following method may also be employed: namely, in a state with adhesive sheet  500  as shown in  FIG. 4B , thermosetting insulative resin film ( 132   a ) is laminated on the upper surfaces of core substrate  11  and chip capacitor  20 , and resin insulation layer  132  is formed accordingly (see  FIG. 8A ); and then, adhesive sheet  500  is removed (see  FIG. 8B ), core substrate  11  is inversed, thermosetting insulative resin film ( 131   a ) is laminated, and resin insulation layer  131  is formed accordingly (see  FIG. 8C ). 
         [0053]    When resin insulation layers  131 ,  132  are formed as above, chip capacitor  20  is fixed to core substrate  11  by filler resin ( 100   b ). Thus, the positional shift of chip capacitor  20  during the lamination process may decrease. Also, since gaps between chip capacitor  20  and the inner walls of core substrate  11  in opening section ( 100   a ) are filled with filler resin ( 100   b ), resin insulation layers  131 ,  132  may be formed with excellent flatness. Also, since filler resin ( 100   b ) is made from material with a low thermal expansion coefficient, the positional shift of chip capacitor  20  caused by the thermosetting and heat contraction of resin may decrease. In addition, cracks or migration induced by stresses caused by voids may be suppressed. 
         [0054]    In the following, after a predetermined preliminary treatment, as shown in  FIG. 6 , via holes ( 121   a ,  122   a ) reaching each terminal  21  of chip capacitor  20  are formed in resin insulation layers  131 ,  132  respectively by laser beaming, for example. In addition, through-holes  140  penetrating core substrate  11  and resin insulation layers  131 ,  132  are formed. Through-holes  140  are aligned based on conductive patterns  111 ,  112 , for example. 
         [0055]    Then, desmearing (removing smears) is conducted on the substrate shown in  FIG. 6  using oxygen plasma (or a drug solution containing permanganic acid or the like). After that, the substrate is immersed in an electroless copper plating solution under the conditions of, for example, solution temperature 34° C. and time 40 minutes. As a result, on the surfaces of resin insulation layers  131 ,  132 , on the inner surfaces of via holes ( 121   a ,  122   a ) and on the inner surfaces of through-holes  140 , electroless copper-plated film  700  is formed with a thickness in the range of 0.6-3.0 μm (see  FIG. 7A ). 
         [0056]    In the following, electrolytic plating is performed by immersing the resultant substrate in an electrolytic plating solution under the conditions of, for example, current density 1.0 A/Dm2, temperature 22±2° C. and time 120 minutes. Accordingly, as shown in  FIG. 7B , electrolytic copper-plated film ( 113   a ,  114   a ), via conductors  121 ,  122  and through-hole conductors  141  are formed. As so described, conductive layers  710  are formed which are made up of electroless plated film  700  and electrolytic copper-plated film ( 113   a ,  114   a ). 
         [0057]    In the following, as shown in  FIG. 7C , by conducting a predetermined lithography process (preliminary treatment, laminating, exposing and developing), etching resists  720 ,  721  are formed. After that, conductive layers  710  are etched. By doing so, conductive patterns  113 ,  114  are formed and printed wiring board  10  is obtained as shown in  FIG. 1 . 
         [0058]    The present invention is not limited to the above embodiment, but various modifications may be made within a scope that will not deviate from the gist of the present invention. 
         [0059]    For example, in the above embodiment, conductive patterns  113 ,  114  are formed by a so-called tenting method, but they may also be formed by a semi-additive method. Steps for forming conductive patterns  113 ,  114  by a semi-additive method will be described briefly. First, electroless copper plating is performed on the substrate shown in  FIG. 6  to form electroless copper-plated film  700  with a thickness of 0.6-3.0 μm on the surfaces of resin insulation layers  131 ,  132 , on the inner surfaces of via holes ( 121   a ,  122   a ) and on the inner surfaces of through-holes  140  (see  FIG. 7A ). Next, on both main surfaces of the substrate shown in  FIG. 7A , a dry-film photosensitive resist is laminated, and mask film is adhered on the photosensitive resist, which is then exposed and developed. Accordingly, plating resist layer  901  with openings only in areas corresponding to conductive pattern  113 , and plating resist layer  902  with openings only in areas corresponding to conductive pattern  114 , are formed (see  FIG. 9A ). 
         [0060]    In the following, electrolytic copper plating is performed on the resultant substrate. As a result, as shown in  FIG. 9B , electrolytic copper-plated films ( 113   a ,  114   a ), via conductors  121 ,  122  and through-hole conductors  141  are formed. Then, resist layers  901 ,  902  are removed and unnecessary portions of electroless copper-plated film  700  are etched away. By doing so, conductive patterns  113 ,  114  are formed and printed wiring board  10  is obtained as shown in  FIG. 1 . 
         [0061]    Also, using a well-known build-up method or the like, a required number of resin insulation layers and wiring layers (conductive patterns) are further laminated on printed wiring board  10  shown in  FIG. 1 , and a further multilayered printed wiring board may be manufactured. 
         [0062]    Also, adhesive layer  502  is formed on both surfaces of jig plate  501 , and printed wiring boards may be manufactured on both such surfaces at the same time. 
         [0063]    Also, after mounting core substrate  11  on adhesive sheet  500 , chip capacitor  20  may be mounted on adhesive sheet  500  to be arranged inside opening section ( 100   a ) of substrate  11 . 
         [0064]    Also, adhesive sheet  500  does not necessarily include jig plate (support plate)  501 ; adhesive  500  may be formed by using only a UV tape, polyimide tape or the like. 
         [0065]    Also, in the above embodiment, a step to form a resin insulation layer is conducted after adhesive sheet  500  is removed (see  FIG. 4C ). However, even before adhesive sheet  500  is removed (see  FIG. 4B ), it is of course possible to form a resin insulation layer on the main surface of the substrate to which adhesive sheet  500  is not adhered (for example, on the surface of the substrate shown in  FIG. 4B  where conductive pattern  112  is formed). 
         [0066]    Also, the present invention may be applied in the same manner as in the above embodiment to other printed wiring boards in which not only chip capacitor  20 , but also other electronic components are built, for example, passive components such as a resistor or a coil, or active components such as an IC chip made of a semiconductor element or the like. In addition, when the thickness of an electronic component is small compared with the thickness of core substrate  11 , filler resin ( 100   b ) may also be adhered to the surfaces other than the side surfaces of the electronic component (such as the top surface and the bottom surface) to enhance the fixing strength. 
         [0067]    In the above embodiment, resin insulation layers and the wiring layers (conductive patterns) are formed on both main surfaces of core substrate  11 . However, resin insulation layers and wiring layers may be formed only on one main surface. 
         [0068]    Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.