Abstract:
An integrated circuit package having external pins includes a function circuit, such as an address buffer, receiving an input voltage through one of the pins. If the input voltage exceeds a maximum rated voltage, the function circuit can be damaged by voltage over-stress. To provide a definitive indication that the function circuit may have been over-stressed, a diode and a fuse are connected in series between the function circuit&#39;s pin and ground. When the input voltage nears the maximum rated voltage, the diode biases and applies a voltage to the fuise. The fuse is selected so that when the input voltage exceeds the maximum rated voltage, the applied voltage blows the fuse. At a later time, the function circuit can be tested for over-stress by applying a voltage to the function circuit&#39;s pin which is sufficient to forward bias the diode. If no current flows after a sufficient biasing voltage is applied to the pin, it is a definitive indication that the function circuit may have been over-stressed.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation of U.S. patent application Ser. No. 08/637,209, filed Apr. 24, 1996, now abandoned. 
    
    
     TECHNICAL FIELD 
     This invention relates in general to integrated circuits, and in particular to providing an indication that an integrated circuit may have been over-stressed by receiving a voltage well in excess of its normal operating voltages. 
     BACKGROUND OF THE INVENTION 
     A conventional integrated circuit (IC) device 10 shown in FIG. 1 typically houses a variety of &#34;function&#34; circuits (not shown), such as data buffers and power circuits, each receiving an input voltage from external circuitry (not shown) through one of multiple external pins 12. In general, the input voltage applied to each of the external pins 12 must be supplied within a limited range of voltages between maximum positive and negative rated voltages referred to as &#34;over-stress&#34; voltages. Otherwise, if the input voltage applied to one of the external pins 12 exceeds a maximum over-stress voltage, the function circuits (not shown) connected to the pin 12 may be damaged by voltage over-stress caused by excessive current flow or excessive voltage differentials within the function circuits (not shown). A positive over-stress voltage of 7.0 volts and a negative over-stress voltage of -1.0 volts are normal for a typical IC device 10 powered by a supply voltage of 5.0 volts. 
     When a customer returns a &#34;defective&#34; IC device to a manufacturer, the manufacturer may find it necessary or desirable to determine whether the &#34;defect&#34; in the returned device is a true defect or the result of the voltage over-stress described above. If the &#34;defect&#34; is a true defect caused by the manufacturing process, the manufacturer knows to adjust the process appropriately to reduce or eliminate the defect. However, if the &#34;defect &#34; is the result of voltage over-stress, the manufacturer knows there is no need to adjust the manufacturing process. 
     At the present time, manufacturers can only make educated guesses about the cause of a &#34;defect&#34; in an IC device, because no practical and definitive method exists to determine that an IC device has been damaged by voltage over-stress. If a manufacturer guesses wrong and incorrectly attributes a true defect to voltage over-stress, the manufacturer may fail to adjust the manufacturing process appropriately. As a result, the manufacturer may continue to manufacture defective IC devices without knowing it. While this would obviously be a problem in any industry, it is a particularly acute problem in the highly competitive IC device industry, where a slight difference in manufacturing yield between different manufacturers can be very significant. Therefore, there is a need in the art for an inventive device for definitively indicating that an IC device may have been subjected to an over-stressing input voltage. 
     SUMMARY OF THE INVENTION 
     An inventive over-stress indicating circuit provides a definitive indication that an IC device may have been over-stressed by an excessive voltage received at a voltage node of the IC device. The indicating circuit is coupled to the voltage node and it changes state from a first state to a second state when the magnitude of a voltage it senses at the voltage node exceeds the magnitude of a threshold voltage. In its second state, the indicating circuit indicates that the magnitude of the voltage at the voltage node has exceeded the magnitude of the threshold voltage during operation of the IC device. As a result, the inventive indicating circuit provides a definitive indication that the IC device may have been subjected to a potentially over-stressing voltage. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is an isometric view of a typical prior art integrated circuit device. 
     FIG. 2 is a block diagram of an integrated circuit device according to the present invention. 
     FIG. 3 is a block diagram of a voltage drop circuit and a voltage sensing circuit used in the integrated circuit device of FIG. 2. 
     FIGS. 4A, 4B and 4C are schematics of alternative versions of the voltage drop circuit and voltage sensing circuit of FIG. 3. 
     FIG. 5 is block diagram of a computer system having a memory device including the integrated circuit device of FIG. 2. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     As shown in FIG. 2, an inventive IC device 20 includes a function circuit 22 and a voltage over-stress indicating circuit 24 both receiving an input voltage V IN  through an input terminal 26. In operation, the function circuit 22 responds to the input voltage V IN  by changing state as the input voltage V IN  exceeds a first transition voltage V TR1 , such as 0.7 volts, or falls below a second transition voltage V TR2  which may be the same as the first transition voltage V TR1 . The transition voltage V TR1  may, for example, be the threshold voltage of a MOSFET transistor in the function circuit 22. If the magnitude of the input voltage V IN  exceeds a positive over-stress voltage, such as 7.0 volts, or exceeds the magnitude of a negative over-stress voltage, such as -1.0 volts, the function circuit 22 may be damaged by voltage over-stress. The function circuit 22 may be any circuit which is susceptible to damage by voltage over-stress, including, for example, address buffers, data buffers and decoder circuits. Also, although the present invention will be described with respect to one flnction circuit connected to one input terminal, it will be understood that the present invention will also work with multiple flnction circuits connected to the same or multiple input terminals. 
     A wide variety of configurations are suitable for the IC device 20. In some configurations, the function circuit 22 and the voltage over-stress indicating circuit 24 are provided on the same die. In other configurations, the function circuit 22 and the indicating circuit 24 are provided on separate dies and possibly in separate packages. Some suitable configurations include a dual inline package (DIP), a leadless ceramic chip carrier (LCCC), a plastic quad flat package (PQFP), a pin grid array (PGA), a pad array carrier (PAC), a ball grid array (BGA), a single in-line package (SIP), a single in-line memory module (SIMM), a lead-on-substrate (LOS) multi-chip package, and a multi-chip module (MCM). Another configuration for the IC device 20 is to directly attach the die or dies containing the function circuit 22 and the indicating circuit 24 to an interconnect board using direct chip attachment (DCA) methods such as die and wire bonding, tape-automated bonding or flip-chip bonding. Also, it should be understood that the input terminal 26 may be any appropriate terminal, such as a pin, a pad, a tab or a ball. 
     The voltage over-stress indicating circuit 24 remains in a no-stress state when it receives the input voltage V IN  at less than the positive over-stress voltage. In its no-stress state, the indicating circuit 24 indicates that the input voltage V IN  has not over-stressed the function circuit 22. Preferably, the indicating circuit 24 provides this indication with a fuse or anti-fuse, as described below in reference to FIGS. 4A-C. However, any component suitable for providing the indication may be used, including an optical, electronic or radio frequency interconnect, or a visually perceptible change. 
     If the input voltage V IN  exceeds the positive over-stress voltage, the indicating circuit 24 changes state from its no-stress state to an over-stress state. Once the indicating circuit 24 enters its over-stress state, it remains there, even if the input voltage V IN  subsequently falls below the positive over-stress voltage. In its over-stress state, the indicating circuit 24 indicates that the input voltage V IN  has exceeded the positive over-stress voltage, thereby possibly over-stressing the function circuit 22. Again, preferably the indicating circuit 24 provides this indication with a fuse or anti-fuse, as described below in reference to FIGS. 4A-C, but any component suitable for providing the indication may be used. Also, in an alternative version described below in reference to FIG. 4C, the indicating circuit 24 also enters its over-stress state if the input voltage V IN  falls below a negative over-stress voltage and thus possibly over-stresses the function circuit 22. 
     The voltage over-stress indicating circuit 24 is shown in more detail in FIG. 3. The indicating circuit 24 includes a voltage drop circuit 30 receiving the input voltage V IN . The voltage drop circuit 30 isolates the input terminal 26 (FIG. 2) from a voltage sensing circuit 32 when the input voltage V IN  is less than a bias voltage V BIAS . When the input voltage V IN  exceeds the bias voltage V BIAS , the voltage drop circuit 30 outputs an output voltage V OUT  equal to the input voltage V IN  less the bias voltage V BIAS . A predetermined voltage V PRE  of the voltage sensing circuit 32 is selected so the sum of the bias voltage V BIAS  and the predetermined voltage V PRE  equals the positive over-stress voltage. Thus, when the input voltage V IN  exceeds the positive over-stress voltage, the output voltage V OUT  exceeds the predetermined voltage V PRE . As a result, the voltage sensing circuit 32 changes state from a no-stress state to an over-stress state. If the input voltage V IN  subsequently drops below the positive over-stress voltage and causes the output voltage V OUT  to drop below the predetermined voltage V PRE , the voltage sensing circuit 32 remains in its over-stress state. In its over-stress state, the voltage sensing circuit 32 indicates that the input voltage V IN  has exceeded the positive over-stress voltage, thereby possibly over-stressing the function circuit 22 (FIG. 2). Preferably, the voltage sensing circuit 32 makes this indication with a fuse or anti-fuse, as described below in reference to FIGS. 4A-C, but any component suitable for providing the indication may be used. 
     Also, in the alternative version described below in reference to FIG. 4C, the voltage sensing circuit 32 also enters its over-stress state if the input voltage V IN  falls below the negative over-stress voltage and thus possibly over-stresses the function circuit 22. In this alternative version, once the voltage sensing circuit 32 enters its over-stress state, it remains there, even if the input voltage V IN  subsequently rises above the negative over-stress voltage. 
     The voltage drop circuit 30 and voltage sensing circuit 32 are shown in more detail in FIGS. 4A-C. As shown in FIG. 4A, the voltage drop circuit 30 comprises multiple diodes 40 coupled in series. The diodes 40 are selected so they will all be forward biased when the input voltage V IN  exceeds the bias voltage V BIAS . Any suitable diodes will work for purposes of this invention, including diode-connected transistors. Also, the voltage sensing circuit 32 may be a fuse 42 selected to &#34;blow&#34; when the output voltage V OUT  from the diodes 40 exceeds the predetermined voltage V PRE  as a result of the input voltage V IN  exceeding the positive over-stress voltage. When the fuse 42 blows, it readily indicates that the input voltage V IN  has exceeded the positive over-stress voltage, because the fuse 42 will fail to conduct current even when an input voltage V IN  sufficient to bias the diodes 40 is applied to the input terminal 26 (FIG. 2). Any suitable fuse or fuse circuit can be used, including metal fuses, polycarbonate fuses, anti-fuses, nitride fuses and dielectride fuses. Also, it should be noted that the order of the series-connected diodes 40 and fuse 42 can be reversed, and that the fuse 42 can be placed in series between some of the diodes 40. 
     As shown in an alternative version in FIG. 4B, the voltage drop circuit 30 comprises diode-connected NMOS transistors 44, 46 and 48. The threshold voltages of the NMOS transistors 44 and 46 are selected so the NMOS transistors 44 and 46 will conduct when the input voltage V IN  exceeds the bias voltage V BIAS . Also, the threshold voltages of the NMOS transistors 46 and 48 are selected so the NMOS transistors 46 and 48 will conduct when a second input voltage V IN .sbsb.-- 2  from a second input terminal (not shown) exceeds a second bias voltage V BIAS .sbsb.-- 2 . As described below, by accommodating multiple input voltages, the alternative voltage drop circuit 30 of FIG. 4B allows the alternative voltage sensing circuit 32 of FIG. 4B to indicate that the input voltage V IN  has exceeded the positive over-stress voltage for the function circuit 22 (FIG. 2), or that the second input voltage V IN .sbsb.-- 2  has exceeded the positive over-stress voltage for a different function circuit (not shown). Of course, additional diode-connected NMOS transistors (not shown) can be added to the voltage drop circuit 30 so it will accommodate more than two input voltages. The embodiment shown in FIG. 4B also allows a single voltage sensing circuit 32 to indicate whether an over-stressing input voltage has been applied to one of several input terminals. 
     The voltage sensing circuit 32 of FIG. 4B comprises an anti-fuse 50 selected to &#34;burn through&#34; when the output voltage V OUT  from the NMOS transistor 46 exceeds the predetermined voltage V PRE  as a result of the input voltage V IN ,or the second input voltage V IN .sbsb.-- 2 , exceeding the positive over-stress voltage. When the anti-fuse 50 burns through, it readily indicates that the input voltage V IN  has exceeded the positive over-stress voltage for the function circuit 22 (FIG. 2), or that the second input voltage V IN .sbsb.-- 2  has exceeded the positive over-stress voltage for its function circuit (not shown), because the anti-fuse 50 will conduct current when an input voltage V IN  sufficient to cause the NMOS transistors 44 and 46 to conduct is applied to the input terminal 26 (FIG. 2), or when a second input voltage V IN .sbsb.-- 2  sufficient to cause the NMOS transistors 46 and 48 to conduct is applied. 
     As shown in another alternative version in FIG. 4C, the voltage drop circuit 30 comprises multiple diode-connected NMOS transistors 52 coupled in parallel with multiple diode-connected NMOS transistors 54. The threshold voltages of the NMOS transistors 52 are selected so they will conduct when the input voltage V IN  becomes more positive than the bias voltage V BIAS , and the threshold voltages of the NMOS transistors 54 are selected so they will conduct when the input voltage V IN  becomes more negative than a second bias voltage V BIAS .sbsb.-- 2 . The threshold voltages of the NMOS transistors 54 are also selected so the sum of the second bias voltage V BIAS .sbsb.-- 2  and the magnitude of the predetermined voltage V PRE  is equal to the negative over-stress voltage. As a result, when the input voltage V IN  drops below ground, it causes the NMOS transistors 54 to conduct before it possibly over-stresses the function circuit 22 (FIG. 2) as a result of dropping to less than the negative over-stress voltage. 
     The voltage sensing circuit 32 of FIG. 4C comprises a fuse 56 selected to &#34;blow&#34; when the output voltage V OUT  from the NMOS transistors 52 exceeds the predetermined voltage V PRE  as a result of the input voltage V IN  exceeding the positive over-stress voltage. The fuse 56 is also selected to blow when the output voltage V OUT  from the NMOS transistors 54 becomes more negative than -V PRE  as a result of the input voltage becoming more negative than the negative over-stress voltage. When the fuse 56 blows, it readily indicates that the input voltage V IN  has exceeded the positive or negative over-stress voltages, because the fuse 56 will fail to conduct current even when an input voltage V IN  sufficient to cause the NMOS transistors 52 or the NMOS transistors 54 to conduct is applied. Thus, by providing additional NMOS transistors 54 which conduct when the input voltage V IN  becomes sufficiently negative, the alternative voltage drop circuit 30 of FIG. 4C allows the voltage sensing circuit 32 of FIG. 4C to indicate when the input voltage V IN  has fallen to less than the negative over-stress voltage and has thereby possibly over-stressed the flnction circuit 22 (FIG. 2). Of course, a wide variety of circuits other than the NMOS transistors 52 and 54 will work as the voltage drop circuit 30 for this purpose, including avalanche and zener diodes. 
     The inventive IC device may be incorporated into a computer system 60 as shown in FIG. 5. The computer system 60 includes an input device 62, such as a keyboard, an output device 64, such as a display, and a processor 66 coupled to the input device 62 and the output device 64. The computer system 60 also includes a memory device 68 coupled to the processor 66 to receive address, data and control signals, and a memory controller 70 coupled to the memory device 68. 
     The memory device 68 includes an address buffer 72 receiving address signals, an address decoder 74 coupled to the address buffer 72, a memory array 76 coupled to the address decoder 74, an input/output gating circuit and sense amplifiers 78 coupled to the address decoder 74 and the memory array 76, and a data buffer 80 coupled to the input/output gating circuit and sense amplifiers 78 and receiving data voltages. The memory device 68 also includes a function circuit 82 as described above with respect to FIG. 2, and a voltage over-stress indicating circuit 84 as described above with respect to FIGS. 2, 3 and 4A-C. 
     Although the present invention has been described with reference to a preferred embodiment, the invention is not limited to this preferred embodiment. Rather, the invention is limited only by the appended claims, which include within their scope all equivalent devices or methods which operate according to the principles of the invention as described.