Abstract:
A half tone display method of a display panel which can prevent the generation of a pseudo outline and can improve a contrast and a display picture quality. In the driving operation to cause light emission of the display panel having a plurality of row electrodes arranged in the horizontal direction corresponding to display lines and a plurality of column electrodes which are arranged in the vertical direction which perpendicularly crosses the row electrodes and form discharge cells at crossing points, a unit display period is divided into a plurality of divided periods and a plurality of light emitting modes in which the orders of light emitting periods which are allocated to each of the divided periods are made different are switched and executed every discharge cell or every discharge cell block in which a plurality of adjacent discharge cells form one set.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a half tone display method of a display panel of a matrix display system such as plasma display panel (hereinafter, referred to as a PDP), liquid crystal display panel (LCD), or the like. 
     2. Description of Related Art 
     As one of display panels of the matrix display system, a PDP of an AC (alternating current discharge) type is known. 
     The AC type PDP has: a plurality of column electrodes (address electrodes); and a plurality of row electrode pairs which are arranged so as to perpendicularly cross the column electrodes and in which one scanning line is formed by one pair. Each row electrode pair and column electrode are coated with a dielectric material layer for a discharge space and have a structure such that a discharge cell corresponding to one pixel is formed by a crossing point of each row electrode pair and column electrode. 
     As one of methods of gradation displaying the display panel of the matrix display system, there is known a method (what is called a subframe method) whereby a display period of time of one frame (one field) is divided into N subframes (subfields) which are lit up for only the time corresponding to a weight of each bit digit of pixel data of N bits and a display is performed. 
     According to the subframe method, for example, in the case where the pixel data consists of six bits, the display period of one frame is divided into six subframes SF 0 , SF 1 , . . . , and SF 5 . In this instance, in the subframes SF 0  to SF 5 , for example, sustain discharge light emissions of 1 time, 2 times, 4 times, 8 times, 16 times, and 32 times are sequentially executed in this order. By executing one cycle of the light emission by the six subframes, a 64-gradation display for an image of one frame (one field) can be performed. Each subframe is constituted by: a resetting period of once initializing all of the discharge cells; an address period of selecting light-up cells and light-off cells by performing an address scan (data writing) based on the image data; and a sustain discharge period of sustaining a discharge light emitting state for only the light-up cells by supplying a discharge sustain pulse. The sustain discharge period of time is determined by the number of times of the sustain discharge light emission as mentioned above. 
     In the case that selective writing address method is employed as the address scanning scheme, at first all of the discharge cells are once reset-discharged and wall charges are formed in the resetting period and, after that, all of the cells are driven to the state of discharge light emission and initialization is performed by erasing the wall charges. Subsequently, in the address period of time, only the relevant discharge cells are selectively excited to cause the discharge light emission in accordance with the image data and the wall charges are formed. In this case, the discharge cells in which the wall charges are formed are selected as light-up cells and the discharge cells in which no wall charge is formed are selected as light-off cells. 
     In the case of using a selective erasing address method, at first all of the discharge cells are once reset-discharged in the resetting period of time and wall charges are formed and initialized. Subsequently, in the address period of time, the wall charges which were once formed are selectively erased and discharged in accordance with the image data, thereby erasing the wall charges. The discharge cells in which the wall charges were erased are selected as the light off cells and the discharge cells in which the wall charges remain as they are are selected as the light up cells. 
     According to the gradation display method, the light emitting order of the subframes SF 0  to SF 5  in one frame (one field) is fixed to a descending order from the longest light emitting period of time (the number of times of light emission) or an ascending order from the shortest light emitting period. 
     OBJECTS AND SUMMARY OF THE INVENTION 
     The invention is made to solve the above problems and it is an object of the invention to provide a half tone display method of a display panel which can prevent the generation of a flicker or a pseudo outline and can improve a contrast and a display picture quality. 
     According to the invention, there is provided a half tone display method of a display panel in which when light emission driving a display panel having a plurality of row electrodes arranged in the horizonal direction in correspondence with display lines and a plurality of column electrodes which are arranged in the vertical direction which crosses the row electrodes and form discharge cells at crossing points, a unit display period is divided into a plurality of divided periods and light emitting periods of the discharge cells which are executed in the respective divided periods are made different from each other, thereby performing a half tone display, wherein a plurality of light emitting modes in which the orders of the light emitting periods which are allocated to the divided periods are made different from each other are switched and executed every discharge cell or every discharge cell block in which a plurality of adjacent discharge cells constitute a set. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a diagram schematically showing the structure of a plasma display apparatus for driving a plasma display panel on the basis of a half tone display method according to the invention; 
     FIG. 2 is a diagram showing an example of an internal construction of a data converting circuit  3 ; 
     FIG. 3 is a diagram showing an example of first and second conversion tables in the data converting circuit  3 ; 
     FIG. 4 is a diagram showing an example of the first and second conversion tables in the data converting circuit  3 ; 
     FIG. 5 is a diagram showing the correspondence among each discharge cell on a PDP screen and light emitting modes A and B; 
     FIG. 6 is a diagram showing an example of a light emission driving format based on the half tone display method of the invention; 
     FIGS. 7A to  7 H are diagrams showing supply timings of drive pulses in one divided period based on the half tone display method of the invention; 
     FIGS. 8A to  8 H are diagrams showing supply timings of drive pulses in one divided period based on the half tone display method of the invention; 
     FIG. 9 is a diagram showing another example of an internal construction of the data converting circuit  3 ; 
     FIGS. 10A to  10 G are diagrams showing internal operation waveforms in the first field in a dither processing circuit  34 ; 
     FIGS. 11A to  11 G are diagrams showing internal operation waveforms in the second field in the dither processing circuit  34 ; 
     FIGS. 12A to  12 G are diagrams showing internal operation waveforms in the third field in the dither processing circuit  34 ; 
     FIGS. 13A to  13 G are diagrams showing internal operation waveforms in the fourth field in the dither processing circuit  34 ; 
     FIG. 14 is a diagram showing an arrangement of discharge cells G 11  to G nm  on the PDP screen; 
     FIGS. 15A to  15 D are diagrams showing conversion pixel data corresponding to the discharge cells G 11  to G 22 ; 
     FIG. 16 is a diagram showing an example of a light emission driving format based on the half tone display method of the invention; 
     FIG. 17 is a diagram showing an example of first and second conversion tables in the data converting circuit  3 ; 
     FIG. 18 is a diagram showing an example of the first and second conversion tables in the data converting circuit  3 ; 
     FIG. 19 is a diagram schematically showing the structure of the plasma display apparatus; 
     FIG. 20 is a diagram showing the correspondence between each pixel on the PDP screen and the light emitting modes A and B; 
     FIG. 21 is a diagram showing the correspondence between each discharge cell on the PDP screen and the light emitting modes A and B; 
     FIG. 22 is a diagram showing the correspondence between pixel blocks on the PDP screen and the light emitting modes A and B; 
     FIG. 23 is a diagram showing the correspondence between discharge cell blocks on the PDP screen and the light emitting modes A and B; 
     FIG. 24 is a diagram showing a transition of the correspondence between each discharge cell on the PDP screen and the light emitting modes A and B every field; 
     FIG. 25 is a diagram showing an example of a light emission driving format based on the half tone display method of the invention; 
     FIG. 26 is a diagram showing an example of the light emission driving format based on the half tone display method of the invention; 
     FIG. 27 is a diagram showing an example of the light emission driving format based on the half tone display method of the invention; 
     FIG. 28 is a diagram showing an example of the light emission driving format based on the half tone display method of the invention; 
     FIG. 29 is a diagram showing an example of the light emission driving format based on the half tone display method of the invention; 
     FIG. 30 is a diagram showing an example of the light emission driving format based on the half tone display method of the invention; 
     FIG. 31 is a diagram showing an example of the light emission driving format (in the case of four sustain discharge periods) based on the half tone display method of the invention; 
     FIGS. 32A to  32 C are diagrams showing a transition of the correspondence between each discharge cell on the PDP screen and the light emitting modes A to D every field; 
     FIG. 33 is a diagram showing an example of the light emission driving format (in case of four sustain discharge periods) based on the half tone display method of the invention; 
     FIGS. 34A and 34B are diagrams showing light emitting periods which are executed by each of the four discharge cells G 11  to G 22  constructing one pixel; 
     FIGS. 35A to  35 H are diagrams showing another example of supply timings of drive pulses in one divided period based on the half tone display method of the invention; 
     FIG. 36 is a diagram showing the correspondence between a discharge cell pair forming one pixel on the PDP screen and the light emitting modes A and B; 
     FIG. 37 is a diagram showing a light emission driving format to realize a half tone display by an error diffusion by using a supplying method of drive pulses according to the invention; 
     FIG. 38 is a diagram showing the relation between the light emitting state and a luminance of each of the discharge cells G 11  and G 12 ; 
     FIG. 39 is a diagram showing first and second conversion tables to execute the light emission driving by the driving format shown in FIG. 37; 
     FIG. 40 is a diagram showing the correspondence among the block comprising four discharge cells and the light emitting modes A to D; 
     FIG. 41 is a diagram showing a light emission driving format which is applied in case of regarding four discharge cells as one block; 
     FIGS. 42A to  42 H are diagrams showing supply timings of drive pulses in the fifth divided period in the light emission driving format shown in FIG. 41; 
     FIG. 43 is a diagram showing another example of an internal construction of the data converting circuit  3 ; 
     FIG. 44 is a diagram showing the first to fourth conversion tables which are used in a first data converting circuit  441 , a second data converting circuit  442 , a third data converting circuit  443 , and a fourth data converting circuit  444  in the data converting circuit  3  shown in FIG. 43; 
     FIG. 45 is a diagram showing γ characteristics A and B which are used in a γ characteristics correcting circuit; 
     FIG. 46 is a diagram showing a light emission driving format in each of an R discharge cell, a G discharge cell, and a B discharge cell; 
     FIG. 47 is a diagram showing another example of the first and second conversion tables in the data converting circuit  3 ; 
     FIG. 48 is a diagram showing another example of the first and second conversion tables in the data converting circuit  3 ; 
     FIG. 49 is a diagram showing an example of a light emission driving format based on the half tone display method of the invention; 
     FIG. 50 is a diagram showing the first and second conversion tables to execute the light emission driving by the driving format shown in FIG. 49; 
     FIG. 51 is a diagram showing the first and second conversion tables to execute the light emission driving by the driving format shown in FIG. 49; 
     FIG. 52 is a diagram showing an example of the light emission driving format based on the half tone display method of the invention; 
     FIG. 53 is a diagram showing the first and second conversion tables to execute the light emission driving by the driving format shown in FIG. 52; 
     FIG. 54 is a diagram showing the first and second conversion tables to execute the light emission driving by the driving format shown in FIG. 52; and 
     FIG. 55 is a diagram showing an example of a light emission driving format in each discharge cell corresponding to each of R, G, and B. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     An embodiment of the invention will now be described hereinbelow with reference to the drawings. 
     FIG. 1 is a diagram schematically showing the structure of a plasma display apparatus for driving a plasma display panel (hereinbelow, referred to as a PDP) as a self light emission display on the basis of a half tone display method according to the invention. 
     In FIG. 1, an A/D converter  1  samples a supplied analog video signal in response to a clock signal which is supplied from a panel drive control circuit  2 , converts into pixel data of N bits every pixel, and supplies the pixel data to a data converting circuit  3 . 
     FIG. 2 is a diagram showing an example of an internal construction of the data converting circuit  3  which is applied to a case where the number of bits of the pixel data is equal to 6 bits. 
     In FIG. 2, a first data converting circuit  31  converts the 6-bit pixel data (bit  6  to bit  1 ) which is sequentially supplied from the A/D converter  1  into conversion pixel data A of 6 bits (bit  6  to bit  1 ) in accordance with a first conversion table as shown in FIGS. 3 and 4 and supplies the data A to a selector  32 . A second data converting circuit  33  converts the pixel data into conversion pixel data B of 6 bits (bit  6  to bit  1 ) in accordance with a second conversion table as shown in FIGS. 3 and 4 and supplies the data B to the selector  32 . The selector  32  selects the conversion pixel data according to a selection signal supplied from the panel drive control circuit  2  from the conversion pixel data A and B and generates the selected data as conversion pixel data HD. For example, each time the pixel data is generated from the A/D converter  1 , a selection signal to alternately switch the selecting state is supplied from the panel drive control circuit  2 . 
     FIG. 5 is a diagram showing to which one of the conversion pixel data A and B the pixel data corresponding to each pixel on the screen has been converted in accordance with the selection switching operation. 
     In FIG. 5, the data converting circuit  3  first converts the pixel data corresponding to the pixel of the first row and the first column of the screen into the conversion pixel data A on the basis of the first conversion table and generates the data A as conversion pixel data HD. The data converting circuit  3 , subsequently, converts the pixel data corresponding to the pixel of the first row and the second column of the screen into the conversion pixel data B on the basis of the second conversion table and generates the data B as conversion pixel data HD. The data converting circuit  3  similarly sequentially converts the pixel data corresponding to the first row by alternately using the first and second conversion tables. The data converting circuit  3  subsequently converts the pixel data corresponding to the pixels of the second row and the first column into the conversion pixel data B on the basis of the second conversion table and generates the data B as conversion pixel data HD. The data converting circuit  3  further converts the pixel data corresponding to the pixels of the second row and the second column into the conversion pixel data A on the basis of the first conversion table and generates the data A as conversion pixel data HD. The data converting circuit  3  likewise sequentially converts each pixel data corresponding to the second row by alternately using the second and first conversion tables. 
     A memory  4  shown in FIG. 1 sequentially writes the conversion pixel data HD in accordance with writing signals which are supplied from the panel drive control circuit  2 . 
     Each time the writing operation of conversion pixel data HD 11  to HD nm  of one screen (n rows, m columns) in a PDP  10  is finished, the memory  4  sequentially reads out the data bits of the bit digit corresponding to the divided period in accordance with the display order of the divided periods in response to a read control signal which is supplied from the panel drive control circuit  2 . When pixel data bit groups comprising data bits of the same bit digit of a pixel data bit group of one screen (n rows, m columns) corresponding to each divided period (conversion pixel data HD 11  to HD nm  of one screen) are supplied to an address driver  6 , the memory  4  sequentially supplies them to the address driver  6  every row of the screen. 
     The address driver  6  generates pixel data pulses DP 1  to DP m  each having a voltage corresponding to a bit logic value of each of the pixel data bit groups of one row supplied from the memory  4  and supplies them to column electrodes D 1  to D m  of the PDP  10 , respectively. The address driver  6  further generates address pulses AP EV  and AP OD  (which will be explained later) and supplies them to the column electrodes D 1  to D m  of the PDP  10 , respectively. 
     In addition to the clock signal, conversion control signal, writing signal, and reading signal as mentioned above, the panel drive control circuit  2  generates a pixel data timing signal, a reset timing signal, a scan timing signal, a sustain timing signal, and an erasing timing signal synchronously with horizontal and vertical sync signals in the video signal, respectively. 
     In response to various timing signals supplied from the panel drive control circuit  2 , a first sustain driver  7  generates a reset pulse to initialize a residual charge amount, a scanning pulse to write the pixel data, a sustain pulse to maintain a discharge light emitting state, and an erasing pulse to stop the discharge light emission and supplies them to row electrodes X 1  to X n  of the PDP  10 . In response to various timing signals supplied from the panel drive control circuit  2 , a second sustain driver  8  generates a reset pulse to initialize a residual charge amount, a scanning pulse to write the pixel data, a sustain pulse to maintain a discharge light emitting state, and an erasing pulse to stop the discharge light emission and supplies them to row electrodes Y 1  to Y n  of the PDP  10 . 
     The PDP  10  forms the row electrodes corresponding to one row of the screen by a pair of row electrode X and row electrode Y. For example, the row electrode pair of the first row in the PDP  10  is the row electrodes X 1  and Y 1  and the row electrode pair of the n-th row is the row electrodes X n  and Y n . In the PDP  10 , one discharge cell is formed in a crossing portion of the row electrode pair and each column electrode. 
     When the scanning pulse Is supplied to any one of the row electrode pairs (X 1 , Y 1 ) to (X n , Y n ) while the pixel data pulse DP is supplied to each of the column electrodes of the PDP  10 , the wall charges corresponding to the pulse voltage of each of the pixel data pulses DP 1  to DP m  are formed in each discharge cell of the crossing portion of the row electrode pair and each of the column electrodes D 1  to D m . After that, when the sustain pulses are supplied to the row electrode pairs (X 1 , Y 1 ) to (X n , Y n ), only the discharge cells in which the wall charges are formed start to light up and maintain the light emitting state for only the time corresponding to the number of sustain pulses. On the sense of sight, the luminance is recognized by the light emission sustain period of time during which the light emitting state is maintained. 
     The driving operation of the PDP  10  which is executed by the plasma display apparatus as shown in FIG. 1 will now be described. 
     An example of the light emission driving such that the one frame (field) period which is required for image display is divided into subframes SF 0  to SF 5  for discharge light emitting the discharge cells for different light emitting periods of time and a half tone display of 64 gradations is executed will now be described. 
     In this instance, now assuming that the light emitting period in the subframe SF 0  is equal to “1”, the period of time of the light emission which is executed in each subframe is as follows. 
     SF 0 :1 
     SF 1 :2 
     SF 2 :4 
     SF 3 :8 
     SF 4 :16 
     SF 5 :32 
     FIG. 6 is a diagram showing an example of a light emission driving format indicative of the light emission driving state by each of the subframes SF 0  to SF 5 . 
     In the light emission driving format shown in FIG. 6, the one frame (field) period is divided into six divided periods comprising the first to sixth divided periods. In each divided period, further, each of a resetting operation R, an address operation AD, a first sustain discharging operation I 1 , a selective erasing operation S, and a second sustain discharging operation I 2 , which will be explained later, is executed. 
     FIGS. 7A to  7 H are diagrams showing supply timings of various drive pulses which are supplied to the electrodes of the PDP  10  in the divided periods of time of the former half portion in one frame (field) period, namely, in each of the first to third divided periods in FIG.  6 . 
     In FIGS. 7A to  7 H, first, the first sustain driver  7  and second sustain driver  8  simultaneously supply reset pulses RP X  and RP Y  to the row electrodes X and Y of the PDP  10 , form wall charges into the discharge cells in the PDP  10 , and perform an initialization (resetting operation R). 
     The address driver  6  supplies the data pulses DP 1  to DP m  corresponding to each row to the column electrodes D 1  to D m . For example, the data pulses DP 1  to DP m  corresponding to the first row are supplied to the column electrodes D 1  to D m . Subsequently, the data pulses DP 1  to DP m  corresponding to the second row are supplied to the column electrodes D 1  to D m . Further, the data pulses DP 1  to DP m  corresponding to the third row are supplied to the column electrodes D 1  to D m . The second sustain driver  8  sequentially supplies the scanning pulse SP to the row electrodes Y 1  to Y n  at the same timings as the supply timings of the data pulses DP. In this instance, the wall charges formed in the discharge cells of the crossing point of the “row” to which the scanning pulse SP was supplied and the “column” to which the pixel data pulse of a high voltage was supplied are selectively erased (address operation AD). By the address operation, a light-up discharge cell which is discharge excited in a sustain discharging operation, which will be explained later, and a light-off discharge cell in which the discharge light emission is not performed are obtained. 
     Subsequently, the first sustain driver  7  and second sustain driver  8  alternately supply sustain pulses IP X  and IP Y  to the row electrodes X and Y. In this instance, each time the sustain pulses IP X  and IP Y  are alternately supplied, the discharge cell in which the wall charges were formed, namely, the light-up discharge cell executes the light emission discharge by the address operation and maintains the light emission discharging state (first sustain discharging operation I 1 ). 
     A discharge sustain period t a  in the first sustain discharging operation differs in dependence on each divided period. 
     That is, 
     The discharge sustain period t a  in the first 
     
       
         divided period=1  (equation 1) 
       
     
     The discharge sustain period t a  in the second 
     
       
         divided period=4  (equation 2) 
       
     
     The discharge sustain period t a  in the third 
     
       
         divided period=16  (equation 3) 
       
     
     Subsequently, the address driver  6  supplies the address pulse AP OD  to each of the odd number designated column electrodes in the column electrodes D 1  to D m . At the same timings as the supply timings of the address pulse AP OD , the second sustain driver  8  supplies an erasing pulse EP to the odd number designated row electrodes Y 1 , Y 3 , Y 5 , Y 7 , . . . . In accordance with this operation, the wall charges of all of the discharge cells existing in the crossing portions of the odd number designated “column electrodes” and the odd number designated “row electrode pairs” are extinguished. The address driver  6  supplies the address pulse AP EV  to each of the even number designated column electrodes in the column electrodes D 1  to D m . At the same timings as the supply timings of the address pulse AP EV , the second sustain driver  8  supplies the erasing pulse EP to the even number designated row electrodes Y 2 , Y 4 , Y 6 , Y 8 , . . . . In accordance with this operation, the wall charges of all of the discharge cells existing in the crossing portions of the even number designated “column electrodes” and the even number designated “row electrode pairs” are extinguished (selective all erasing operation S). 
     That is, the wall charges formed in all of the discharge cells existing in the odd columns and odd rows and all of the discharge cells existing in the even columns and even rows are extinguished and those discharge cells become the light-off discharge cells. That is, by executing the selective all erasing operation, the discharge cells shown by “A” in FIG. 5 become the light-off discharge cells. In this instance, the wall charges remain in each of the discharge cells shown by “B” in FIG.  5 . 
     The first sustain driver  7  and second sustain driver  8  subsequently alternately supply the sustain pulses IP X  and IP Y  to the row electrodes X and Y of the PDP  10 . In this instance, each time the sustain pulses IP X  and IP Y  are alternately supplied, the light-up discharge cell in which the wall charges remain performs the light emission discharge and maintains the light emission discharging state (second sustain discharging operation I 2 ). The discharge sustain period in the second sustain discharging operation is the same as the discharge sustain period t a  in the first sustain discharging operation. 
     That is, by executing the second sustain discharging operation, each of the discharge cells shown by “B” in FIG. 5 subsequently executes the light emission discharge for the period of time of the discharge sustain period t a . That is, in the first to third divided periods, the light emitting period in each of the discharge cells shown by “B” in FIG. 5 is twice as long as the light emitting period of each of the discharge cells shown by “A” in FIG.  5 . 
     When the second sustain discharging operation is finished, the second sustain driver  8  supplies the erasing pulse EP to all of the row electrodes Y 1  to Y n . In accordance with this operation, the wall charges in all of the discharge cells existing in the crossing portions of the “column electrodes” and the even number designated “row electrode pairs” are extinguished and those discharge cells become the light-off discharge cells (all erasing operation). 
     In each of the first to third divided periods, therefore, each of the discharge cells shown by “A” in FIG. 5 is light emission driven by the light emitting pattern shown in the light emitting mode A in FIG.  6  and each of the discharge cells shown by “B” in FIG. 5 is light emission driven by the light emitting pattern shown in the light emitting mode B in FIG.  6 . 
     In the divided periods of the latter half portion in one frame, namely, in each of the fourth to sixth divided periods, various drive pulses are supplied to the electrodes of the PDP  10  as shown in FIGS. 8A to  8 H. 
     In FIGS. 8A to  8 H, first, the first sustain driver  7  and second sustain driver  8  simultaneously supply the reset pulses RP X  and RP Y  to the row electrodes X and Y of the PDP  10 , form the wall charges in each discharge cell in the PDP  10 , and perform the initialization (resetting operation R). 
     Subsequently, the address driver  6  supplies the data pulses DP 1  to DP m  corresponding to each row to the column electrodes D 1  to D m . For example, the data pulses DP 1  to DP m  corresponding to the first row are supplied to the column electrodes D 1  to D m . Subsequently, the data pulses DP 1  to DP m  corresponding to the second row are supplied to the column electrodes D 1  to D m . Further, the data pulses DP 1  to DP m  corresponding to the third row are supplied to the column electrodes D 1  to D m . The second sustain driver  8  sequentially supplies the scanning pulse SP to the row electrodes Y 1  to Y n  at the same timings as the supply timings of the data pulses DP. In this instance, the wall charges formed in the discharge cells of the crossing points of the “row” to which the scanning pulse SP was supplied and the “column” to which the pixel data pulse of a high voltage was supplied are selectively erased (address operation AD). By the address operation, a light-up discharge cell which is discharge excited in the sustain discharging operation, which will be explained later, and a light-off discharge cell in which the discharge light emission is not performed are obtained. 
     Subsequently, the first sustain driver  7  and second sustain driver  8  alternately supply the sustain pulses IP X  and IP Y  to the row electrodes X and Y. In this instance, each time the sustain pulses IP X  and IP Y  are alternately supplied, the discharge cell in which the wall charges were formed, namely, the light-up discharge cell executes the light emission discharge by the address operation and maintains the light emission discharging state (first sustain discharging operation I 1 ). 
     The discharge sustain period t a  in the first sustain discharging operation differs in dependence on each divided period. 
     That is, 
     The discharge sustain period t a  in the fourth 
     
       
         divided period=16  (equation 4) 
       
     
     The discharge sustain period t a  in the fifth 
     
       
         divided period=4  (equation 5) 
       
     
     The discharge sustain period t a  in the sixth 
     
       
         divided period=1  (equation 6) 
       
     
     Subsequently, the address driver  6  supplies the address pulse AP EV  to each of the even number designated column electrodes in the column electrodes DP 1  to D m . At the same timings as the supply timings of the address pulse AP EV , the second sustain driver  8  supplies the erasing pulse EP to the odd number designated row electrodes Y 1 , Y 3 , Y 5 , Y 7 , . . . . In accordance with this operation, the wall charges of all of the discharge cells existing in the crossing portions of the even number designated “column electrodes” and the odd number designated “row electrode pairs” are extinguished. The address driver  6  supplies the address pulse AP OD  to each of the odd number designated column electrodes in the column electrodes D 1  to D m . At the same timings as the supply timings of the address pulse AP OD , the second sustain driver  8  supplies the erasing pulse EP to the even number designated row electrodes Y 2 , Y 4 , Y 6 , Y 8 , . . . . In accordance with this operation, the wall charges of all of the discharge cells existing in the crossing portions of the odd number designated “column electrodes” and the even number designated “row electrode pairs” are extinguished (selective all erasing operation S). 
     That is, the wall charges formed in all of the discharge cells existing in the odd columns and even rows and all of the discharge cells existing in the even columns and odd rows are extinguished and those discharge cells become the light-off discharge cells. That is, by executing the selective all erasing operation, all of the discharge cells shown by “B” in FIG. 5 become the light-off discharge cells. In this instance, the wall charges remain in each of the discharge cells shown by “A” in FIG.  5 . 
     The first sustain driver  7  and second sustain driver  8  subsequently alternately supply the sustain pulses IP X  and IP Y  to the row electrodes X and Y of the PDP  10 . In this instance, each time the sustain pulses IP X  and IP Y  are alternately supplied, the discharge cell in which the wall charges remain performs the light emission discharge and maintains the light emission discharging state (second sustain discharging operation I 2 ). The discharge sustain period in the second sustain discharging operation is the same as the discharge sustain period t a  in the first sustain discharging operation. 
     That is, by executing the second sustain discharging operation, each of the discharge cells shown by “A” in FIG. 5 subsequently executes the light emission discharge for the period of time of the discharge sustain period t a . That is, in the fourth to sixth divided periods, the light emitting period in each of the discharge cells shown by “A” in FIG. 5 is twice as long as the light emitting period of each of the discharge cells shown by “B” in FIG.  5 . 
     When the second sustain discharging operation is finished, the second sustain driver  8  supplies the erasing pulse EP to all of the row electrodes Y 1  to Y n . In accordance with this operation, the wall charges in all of the discharge cells existing in the crossing portion of the “column electrodes” and the even number designated “row electrode pairs” are extinguished (all erasing operation). 
     In each of the fourth to sixth divided periods, therefore, each of the discharge cells shown by “A” in FIG. 5 is light emission driven by the light emitting pattern shown in the light emitting mode A in FIG.  6  and each of the discharge cells shown by “B” in FIG. 5 is light emission driven by the light emitting pattern shown in the light emitting mode B in FIG.  6 . 
     In the divided periods (first to third divided periods) of the former half portion in one frame period, by supplying the drive pulses as shown in FIGS. 7A to  7 H to the PDP  10 , and in the divided periods (fourth to sixth divided periods) of the latter half portion, by supplying the drive pulses as shown in FIGS. 8A to  8 H to the PDP  10 , the adjacent discharge cells can be light emitted by the different light emitting patterns. 
     For example, each of the discharge cells shown by “A” in FIG. 5 is light emission driven by the light emitting pattern by the light emitting mode A in FIG.  6 . Each of the discharge cells shown by “B” is light emission driven by the light emitting pattern by the light emitting mode B in FIG.  6 . 
     In this instance, in the light emitting pattern by the light emitting mode A, as shown in FIG. 6, the light emitting period which is executed for the first divided period is equal to “1” and it corresponds to the subframe SF 0 . In the light emitting mode A, the light emitting period which is executed for the second divided period is equal to “4” and it corresponds to the subframe SF 2 . In the light emitting mode A, the light emitting period which is executed for the third divided period is equal to “16” and it corresponds to the subframe SF 4 . In the light emitting mode A, the light emitting period which is executed for the fourth divided period is equal to “32” and it corresponds to the subframe SF 5 . In the light emitting mode A, the light emitting period which is executed for the fifth divided period is equal to “8” and it corresponds to the subframe SF 3 . In the light emitting mode A, the light emitting period which is executed for the sixth divided period is equal to “2” and it corresponds to the subframe SF 1 . 
     A logic value of each bit of the conversion pixel data converted by the first or second conversion table as shown in FIGS. 3 and 4 decides whether the light-up operation is executed in each of the first to sixth divided periods or not. 
     For example, when the logic value of bit  6  of the conversion pixel data is equal to “0”, the light emission in the first divided period shown in FIG. 6 is not executed in any one of the light emitting modes A and B. When the logic value of bit  6  of the conversion pixel data is equal to “1”, the light emission of the light emitting period “1” (SF 0 ) is performed in the light emitting mode A and the light emission of the light emitting period “2” (SF 1 ) is executed in the light emitting mode B. when the logic value of bit  5  of the conversion pixel data is equal to “0”, the light emission in the second divided period shown in FIG. 6 is not executed in the light emitting modes A and B. When the logic value of bit  5  of the conversion pixel data is equal to “1”, the light emission of the light emitting period “4” (SF 2 ) is performed in the light emitting mode A and the light emission of the light emitting period “8” (SF 3 ) is executed in the light emitting mode B. When the logic value of bit  4  of the conversion pixel data is equal to “0”, the light emission in the third divided period shown in FIG. 6 is not executed in the light emitting modes A and B. When the logic value of bit  4  of the conversion pixel data is equal to “1”, the light emission of the light emitting period “16” (SF 4 ) is performed in the light emitting mode A and the light emission of the light emitting period “32” (SF 5 ) is executed in the light emitting mode B. When the logic value of bit  3  of the conversion pixel data is equal to “0”, the light emission in the fourth divided period shown in FIG. 6 is not performed in both of the light emitting modes A and B. When the logic value of bit  3  of the conversion pixel data is equal to “1”, the light emission of the light emitting period “32” (SF 5 ) is performed in the light emitting mode A and the light emission of the light emitting period “16” (SF 4 ) is executed in the light emitting mode B. When the logic value of bit  2  of the conversion pixel data is equal to “0”, the light emission in the fifth divided period shown in FIG. 6 is not performed in both of the light emitting modes A and B. When the logic value of bit  2  of the conversion pixel data is equal to “1”, the light emission of the light emitting period “8” (SF 3 ) is performed in the light emitting mode A and the light emission of the light emitting period “4” (SF 2 ) is executed in the light emitting mode B. When the logic value of bit  1  of the conversion pixel data is equal to “0”, the light emission in the sixth divided period shown in FIG. 6 is not performed in both of the light emitting modes A and B. When the logic value of bit  1  of the conversion pixel data is equal to “1”, the light emission of the light emitting period “2” (SF 1 ) is performed in the light emitting mode A and the light emission of the light emitting period “1” (SF 0 ) is executed in the light emitting mode B. 
     In the light emitting mode A or B, the sum of the light emitting periods in the first to sixth divided periods corresponds to the luminance level. 
     For example, as shown in FIG. 3, when the pixel data “010001” corresponding to the half tone level “17” is converted by the first conversion table, 
     Conversion pixel data “101000” is obtained. When it is converted by the second conversion table, 
     Conversion pixel data “000101” is obtained. 
     In this instance, the light emission driving based on the light emitting mode A shown in FIG. 6 is performed for the conversion pixel data “101000” converted by the first conversion table. The light emission driving based on the light emitting mode B shown in FIG. 6 is executed for the conversion pixel data “000101” converted by the second conversion table. 
     The light emitting patterns which are executed in one frame period, therefore, are as follows. 
     
       
         
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
             
           
               
                   
                   
               
               
                   
                 1st 
                 2nd 
                 3rd 
                 4th 
                 5th 
                 6th 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                 Light emitting 
                 ON 
                 OFF 
                 ON 
                 OFF 
                 OFF 
                 OFF 
               
               
                 mode A 
                 (SFO) 
                   
                 (SF4) 
               
               
                 Light emitting 
                 OFF 
                 OFF 
                 OFF 
                 ON 
                 OFF 
                 ON 
               
               
                 mode B 
                   
                   
                 (SF4) 
                   
                   
                 (SF0) 
               
               
                   
               
             
          
         
       
     
     That is, although the light-up patterns which are executed for one frame period in both of the light emitting modes A and B are different, the sum of the light emitting periods which are executed for one frame period in each mode is equal to 
     
       
         SF 0 +SF 4 =“17”  (equation 7) 
       
     
     In each of the discharge cells shown by “A” in FIG.  5  and the discharge cells “B” adjacent to the discharge cells “A”, therefore, although the light emission corresponding to the same half tone luminance is executed, the light emitting patterns which are executed in one frame period are different. 
     According to the half tone display method, consequently, since the adjacent discharge cells perform the light emissions by the different light emitting patterns, the pseudo outline is reduced. 
     As shown in FIG. 6, all of the light emitting patterns in the light emitting mode A are 
     {SF 0 , SF 2 , SF 4 , SF 5 , SF 3 , SF 1 } and all of the light emitting patterns in the light emitting mode B are 
     {SF 1 , SF 3 , SF 5 , SF 4 , SF 2 , SF 0 } 
     That is, in the light emitting patterns in the light emitting mode A and the light emitting patterns in the light emitting mode B, the orders of executing the subframes SF are opposite. 
     Since the orders of the subframes which are executed in one frame period are opposite as for both of the light emitting patterns, the pseudo outline can be more effectively reduced. 
     In the embodiment, although the intermediate luminance gradations according to the number of bits of the pixel data are obtained, by adding a dither processing circuit to it, intermediate luminance gradations larger than the gradations corresponding to the number of bits of the pixel data can be falsely obtained. FIG. 9 is a diagram showing another construction of the data converting circuit  3  realized in consideration of the above point. 
     In the data converting circuit  3  shown in FIG. 9, a dither processing circuit  34  comprising a dither generating circuit  310 , an adder  320 , and an upper bit extracting circuit  330  is further added to the construction shown in FIG.  2 . 
     The internal operation of the data converting circuit  3  shown in FIG. 9 will now be described hereinbelow with reference to FIGS. 10A to  10 G to  14 . FIGS. 10A to  10 G and FIGS. 13A to  13 G are diagrams showing internal operation waveforms of the data converting circuit  3  in each of the four continuous field periods of the video signal. FIG. 14 is a diagram showing an arrangement of the discharge cells of the PDP  10 . 
     First, the pixel data generated from the A/D converter  1  in FIG. 1 is sequentially supplied to the adder  320 . In this instance, in the case where the video signal is based on the interlace scan, among the discharge cells of the PDP  10 , the pixel data corresponding to the discharge cells of the odd number designated rows is first supplied and, after that, the pixel data corresponding to the discharge cells of the even number designated rows is supplied. 
     For instance, in the first field shown in FIGS. 10A to  10 G, after pixel data D 11  to D 1m  corresponding to discharge cells G 11  to G 1m  of the first row in FIG. 14 were supplied, pixel data D 31  to D 3m  corresponding to discharge cells G 31  to G 3m  of the third row as the next odd row are supplied. Similarly, pixel data corresponding to the odd rows is sequentially supplied. When pixel data D n1  to D nm  corresponding to discharge cells G n1  to G nm  of the final odd row are supplied, the second field as shown in FIGS. 11A to  11 G is executed. In the second field, pixel data D 21  to D 2m  corresponding to discharge cells G 21  to G 2m  of the first even row are supplied. The pixel data corresponding to the even rows is sequentially supplied. When pixel data D (n-1)1  to D nm  corresponding to the first even row are supplied, the third field as shown in FIGS. 12A to  12 G is executed. In the third field, the pixel data corresponding to the odd rows is supplied in a manner similar to the first field. In the fourth field, the pixel data corresponding to the even rows is supplied in a manner similar to the second field. 
     The dither generating circuit  310  circulatively repetitively generates a dither coefficient a, a dither coefficient c, a dither coefficient b, and a dither coefficient d every clock signal CK 2  in the first field as shown in FIGS. 10A to  10 G and supplies them to the adder  320 . In the next second field and subsequent third field, the dither generating circuit  310  circulatively repetitively generates the dither coefficient d, dither coefficient b, dither coefficient c, and dither coefficient a as shown in FIGS. 11A to  11 G and FIGS. 12A to  12 G and supplies them to the adder  320 . The dither generating circuit  310  circulatively repetitively generates the dither coefficient a, dither coefficient c, dither coefficient b, and dither coefficient d every clock signal CK 2  in the fourth field as shown in FIGS. 13A to  13 G and supplies them to the adder  320 . 
     The dither generating circuit  310  repetitively executes the operations in the first to fourth fields as mentioned above. That is, when the dither coefficient generating operation in the fourth field is finished, the operation is again returned to the operation of the first field and the foregoing operations are repeated. 
     The adder  320  successively adds the dither coefficients as mentioned above to the pixel data which is sequentially supplied from the A/D converter  1  as shown in FIGS. 10A to  10 G and FIGS. 13A to  13 G and supplies resultant dither addition pixel data to the upper bit extracting circuit  330 . 
     That is, two different dither coefficients are added to one pixel data and two dither addition pixel data are newly formed. 
     The upper bit extracting circuit  330  extracts the data as much as upper M bits in the dither addition pixel data and supplies it as dither processing pixel data Z to each of the first data converting circuit  31  and second data converting circuit  33 . 
     The first data converting circuit  31  converts, for example, the 6-bit dither processing pixel data Z (bit  6  to bit  1 ) which is sequentially supplied from the upper bit extracting circuit  330  into conversion pixel data AZ of 6 bits (bit  6  to bit  1 ) in accordance with the first conversion table as shown in FIGS. 3 and 4 and supplies the data AZ to the selector  32 . The second data converting circuit  33  converts the dither processing pixel data Z into conversion pixel data BZ of 6 bits (bit  6  to bit  1 ) in accordance with the second conversion table as shown in FIGS. 3 and 4 and supplies the data BZ to the selector  32 . 
     The selector  32  selects the conversion pixel data according to a selection signal as shown in FIGS. 10A to  10 G and FIGS. 13A to  13 G supplied from the panel drive control circuit  2  from the conversion pixel data AZ and BZ and generates it. 
     For example, in the first field as shown in FIGS. 10A to  10 G, conversion pixel data AZ(D 11 +a) obtained by converting dither processing pixel data Z(D 11 +a) in accordance with the first conversion table is generated from the selector  32  and conversion pixel data BZ(D 11 +c) obtained by converting dither processing pixel data Z(D 11 +c) in accordance with the second conversion table is generated from the selector  32 . Subsequently, conversion pixel data BZ(D 12 +b) obtained by converting dither processing pixel data Z(D 12 +b) in accordance with the second conversion table and conversion pixel data AZ(D 12 +d) obtained by converting dither processing pixel data Z(D 12 +d) in accordance with the first conversion table are sequentially generated from the selector  32 . 
     By the operation of the first field as shown in FIGS. 10A to  10 G, for example, as shown in FIG. 15A, the light emission based on the conversion pixel data AZ(D 11 +a) in the discharge cell G 11  of the first row and the first column, the light emission based on the conversion pixel data BZ(D 12 +b) in the discharge cell G 12  of the first row and the second column, the light emission based on the conversion pixel data BZ(D 11 +c) in the discharge cell G 21  of the second row and the first column, and the light emission based on the conversion pixel data AZ(D 12 +d) in the discharge cell G 22  of the second row and the second column are executed, respectively. 
     Similarly, by the operation in each of the second to fourth fields as shown in FIGS. 11A to  11 G and FIGS. 13A to  13 G, the light emission based on each of the conversion pixel data as shown in FIGS. 15B to  15 D is executed. 
     That is, in the dither processing circuit  34  of the data converting circuit  3 , as shown in FIGS. 10A to  10 G and FIGS. 13A to  13 G, two dither processing pixel data corresponding to the even and odd rows is formed from the pixel data corresponding to one discharge cell. In the dither processing circuit  34 , further, by changing the dither coefficients to be added to the pixel data corresponding to each discharge cell every field, the reduction of pattern noises of the dither is realized. 
     In the embodiment shown in FIG. 6, one frame period is divided into six divided periods, the subframes SF 1  to SF 6  are allocated to the six divided periods, and the light emission driving is executed. The invention, however, is not limited to this construction. 
     For instance, it is also possible to divide one frame period into eight divided periods and to execute the light emission driving. 
     FIG. 16 is a diagram showing another example of the light emission driving format made in consideration of the above point. 
     In the light emission driving format shown in FIG. 16, various drive pulses are supplied to the PDP  10  at timings as shown in FIGS. 7A to  7 H in each of the first, fifth, sixth, and eighth divided periods. 
     The discharge sustain period t a  in each of the first and second sustain discharging operations as shown in FIGS. 7A to  7 H to be executed in each of the first, fifth, sixth, and eighth divided periods is as follows. 
     The discharge sustain period t a  in the first 
     
       
         divided period=8  (equation 8) 
       
     
     The discharge sustain period t a  in the fifth 
     
       
         divided period=4  (equation 9) 
       
     
     The discharge sustain period t a  in the sixth 
     
       
         divided period=1  (equation 10) 
       
     
     The discharge sustain period t a  in the eighth 
     
       
         divided period=8  (equation 11) 
       
     
     Various drive pulses are supplied to the PDP  10  at timings as shown in FIGS. 8A to  8 H in each of the second, third, fourth, and seventh divided periods. 
     The discharge sustain period t a  in each of the first and second sustain discharging operations as shown in FIGS. 8A to  8 H to be executed in each of the second, third, fourth, and seventh divided periods is as follows. 
     The discharge sustain period t a  in the second 
     
       
         divided period=8  (equation 12) 
       
     
     The discharge sustain period t a  in the third 
     
       
         divided period=1  (equation 13) 
       
     
     The discharge sustain period t a  in the fourth 
     
       
         divided period=4  (equation 14) 
       
     
     The discharge sustain period t a  in the seventh 
     
       
         divided period=8  (equation 15) 
       
     
     Further, the first data converting circuit  31  and second data converting circuit  33  in the data converting circuit  3  are changed to data converting circuits which can obtain the conversion pixel data A and B on the basis of the conversion tables as shown in FIGS. 17 and 18. 
     That is, in the embodiment shown in FIGS. 16 to  18 , each of the subframes SF 4  and SF 5  among the subframes SF 0  to SF 6  for performing the light emission driving is divided into two periods at the following light emitting period ratios. 
     SF 0 :1 
     SF 1 :2 
     SF 2 :4 
     SF 3 :8 
     SF 4 :16 
     SF 5 :32 
     They are distributed and executed in one frame period. 
     That is, SF 4  as a light emitting period “16” is divided into SF 4   a  and SF 4   b  in which the light emitting period is equal to “8”. In the light emission driving in the light emitting mode A, they are distributed to the fourth divided period and the eighth divided period as shown in FIG.  16  and are executed. Further, SF 5  as a light emitting period “32” is divided into SF 5   a  and SF 5   b  in which the light emitting period is equal to “16”. In the light emission driving in the light emitting mode A, they are distributed to the second divided period and the seventh divided period as shown in FIG.  16  and are executed. 
     The conversion of the pixel data as shown in FIGS. 3,  4 ,  17 , and  18  can be applied to not only the output pixel data from the A/D converter  1  as mentioned above or the pixel data after completion of the dither process by the dither processing circuit  34  as shown in FIG. 9 but also the pixel data after completion of another bit number reducing process (for example, error diffusing process). 
     In FIG. 1, although the embodiment has been described without considering the R (red) component, G (green) component, and B (blue) component in the video signal, a construction as shown in FIG. 19 is actually used in consideration of those color components. 
     In FIG. 19, an RGB divided circuit  70  respectively separates and extracts a video signal R corresponding to the R (red) component, a video signal G corresponding to the G (green) component, and a video signal B corresponding to the B (blue) component from the supplied video signal and transfers to A/D converters  1   a  to  1   c , respectively. 
     In this instance, each of the A/D converter  1   a , a data converting circuit  3   a , and a memory  4   a  is a circuit for performing the pixel data process as mentioned above to the video signal R of the R (red) component. Functions of the circuit blocks are the same as the A/D converter  1 , data converting circuit  3 , and memory  4  shown in FIG.  1 . Each of the A/D converter  1   b , a data converting circuit  3   b , and a memory  4   b  is a circuit for performing the pixel data process as mentioned above to the video signal G of the G (green) component. Functions of the circuit blocks are the same as the A/D converter  1 , data converting circuit  3 , and memory  4  shown in FIG.  1 . Similarly, each of the A/D converter  1   c , a data converting circuit  3   c , and a memory  4   c  is a circuit for performing the pixel data process as mentioned above to the video signal B of the B (blue) component. Functions of the circuit blocks are the same as the A/D converter  1 , data converting circuit  3 , and memory  4  shown in FIG.  1 . 
     With the above construction, the conversion pixel data corresponding to the R, G, and B components is supplied to the address driver  6 . 
     In this instance, as shown in FIG. 20, a pixel data pulse corresponding to the conversion pixel data of the R component is supplied to each of the column electrodes D 1 , D 4 , D 7 , . . . , and D (3m-2)  of the PDP  10 . A pixel data pulse corresponding to the conversion pixel data of the G component is supplied to each of the column electrodes D 2 , D 5 , D 8 , . . . , and D (3m-1) . Further, a pixel data pulse corresponding to the conversion pixel data of the B component is supplied to each of the column electrodes D 3 , D 6 , D 9 , . . . , and D (3m) . That is, one pixel is formed by three adjacent discharge cells formed in the crossing portions of one column electrode and a pair of row electrode pair. In the embodiment shown in FIG. 20, the light emitting modes A and B are executed in a zigzag manner on a pixel unit basis. 
     In this instance, as shown in FIG. 21, the light emitting modes A and B can be also executed in a zigzag manner on a discharge cell unit basis. 
     As shown in FIG. 22, a plurality of pixels are set to one block (block surrounded by a broken line) and the light emitting modes A and B can be also executed in a zigzag manner on a block unit basis. 
     As shown in FIG. 23, a plurality of discharge cells are set to one block (block surrounded by a broken line) and the light emitting modes A and B can be also executed in a zigzag manner on a block unit basis. 
     As shown in FIG. 24, the light emitting modes A and B can be also alternately executed every field or every frame. 
     Although the embodiment has been described with respect to the driving formats to execute the half tone display of  64  gradations in FIGS. 6 and 16, it can be also executed with regard to 128 gradations or 256 gradations. 
     Each of FIGS. 25 to  28  is a diagram showing a driving format to execute the half tone display of 256 gradations. Each of FIGS. 29 and 30 is a diagram showing a driving format to execute the half tone display of 128 gradations. 
     In the driving methods shown in FIGS. 7A to  7 H and FIGS. 8A to  8 H, two sustain discharge periods are provided in one divided period and two kinds of modes in the case of executing the discharge light emission in both of those periods and in the case of executing the discharge light emission in only one of the periods of time can be selectively executed every discharge cell, thereby realizing two light emitting patterns (light emitting modes A and B). 
     Like a light emission driving format shown in FIG. 31, however, four sustain discharge periods (the first sustain discharge period I 1  to the fourth sustain discharge period I 4 ) are provided in one divided period and four kinds of light emitting patterns can be also obtained. The first sustain discharge period I 1  to the fourth sustain discharge period I 4  are not always equal to the same period. 
     The light emission in the light emitting mode A based on the light emission driving format shown in FIG. 31 has the following light emitting patterns. 
     First divided period light up in only the first sustain discharge period (light emitting period “1”) 
     Second divided period:light up in only the first sustain discharge period (light emitting period “16”) 
     Third divided period:light up in each of the first to third sustain discharging periods (light emitting period “64”) 
     Fourth divided period:light up in each of the first to third sustain discharging periods (light emitting period “4”) 
     Fifth divided period:light up in each of the first and second sustain discharging periods (light emitting period “2”) 
     Sixth divided period:light up in each of the first and second sustain discharging periods (light emitting period “32”) 
     Seventh divided period:light up in all of the first to fourth sustain discharging periods (light emitting period “128”) 
     Eighth divided period:light up in all of the first to fourth sustain discharging periods (light emitting period “8”) 
     The light emission in the light emitting mode B in FIG. 31 has the following light emitting patterns. 
     First divided period:light up in each of the first and second sustain discharging periods (light emitting period “2”) 
     Second divided period:light up in each of the first and second sustain discharging periods (light emitting period “32”) 
     Third divided period:light up in all of the first to fourth sustain discharging periods (light emitting period “128”) 
     Fourth divided period:light up in all of the first to fourth sustain discharging periods (light emitting period “8”) 
     Fifth divided period:light up in only the first sustain discharge period (light emitting period “1”) 
     Sixth divided period:light up in only the first sustain discharge period (light emitting period “16”) 
     Seventh divided period:light up in each of the first to third sustain discharging periods (light emitting period “64”) 
     Eighth divided period:light up in each of the first to third sustain discharging periods (light emitting period “4”) 
     The light emission in the light emitting mode C in FIG. 31 has the following light emitting patterns. 
     First divided period:light up in each of the first to third sustain discharging periods (light emitting period “4”) 
     Second divided period:light up in each of the first to third sustain discharging periods (light emitting period “64”) 
     Third divided period:light up in only the first sustain discharge period (light emitting period “16”) 
     Fourth divided period:light up in only the first sustain discharge period (light emitting period “1”) 
     Fifth divided period:light up in all of the first to fourth sustain discharging periods (light emitting period “8”) 
     Sixth divided period:light up in all of the first to fourth sustain discharging periods (light emitting period “128”) 
     Seventh divided period:light up in each of the first and second sustain discharging periods (light emitting period “32”) 
     Eighth divided period light up in each of the first and second sustain discharging periods (light emitting period “2”) 
     The light emission in the light emitting mode D in FIG. 31 has the following light emitting patterns. 
     First divided period light up in all of the first to fourth sustain discharging periods (light emitting period “8”) 
     Second divided period:light up in all of the first to fourth sustain discharging periods (light emitting period “128”) 
     Third divided period:light up in each of the first and second sustain discharging periods (light emitting period “32”) 
     Fourth divided period:light up in each of the first and second sustain discharging periods (light emitting period “2”) 
     Fifth divided period:light up in each of the first to third sustain discharging periods (light emitting period “4”) 
     Sixth divided period:light up in each of the first to third sustain discharging periods (light emitting period “64”) 
     Seventh divided period:light up in only the first sustain discharge period (light emitting period “16”) 
     Eighth divided period:light up in only the first sustain discharge period (light emitting period “1”) 
     The four kinds of light emitting patterns in the light emitting modes A to D are selectively executed every pixels, every discharge cell, or every group consisting of a plurality of adjacent discharge cells as shown in, for example, FIG.  32 A. 
     The four kinds of light emitting patterns in the light emitting modes A to D can be also changed every field or every frame as shown in FIG. 32B or FIG.  32 C. 
     In case of constructing one pixel by four adjacent discharge cells, by executing the light emission driving in the light emitting modes A to D, the half tone display of 256 gradations can be performed in two divided periods in one frame period. 
     FIG. 33 is a diagram showing an example of a light emission driving format realized in consideration of the above point. FIGS. 34A and 34B are diagrams showing light emitting periods which are embodied in each of the four discharge cells constructing one pixel. 
     That is, in the case where each of the four discharge cells G 11 , G 12 , G 21 , and G 22  forming one pixel as shown in FIG. 34A performs the light emission in the light emitting modes A to D in accordance with the light emission driving format shown in FIG. 33, each discharge cell performs the light emission in the light emitting period as shown in FIG. 34B in each of the two divided periods. 
     In place of the driving methods shown in FIGS. 7A to  7 H and FIGS. 8A to  8 H, a driving method as shown in FIGS. 35A to  35 H can be also used. 
     In the driving method shown in FIGS. 35A to  35 H, although the resetting operation, address operation, and first sustain discharging operation are the same as those shown in FIGS. 7A to  7 H and FIGS. 8A to  8 H, the operation after the first sustain discharging operation differs. 
     That is, according to the driving method shown in FIGS. 35A to  35 H, when the first sustain discharging operation is finished, the second sustain driver  8  subsequently supplies the erasing pulse EP to all of the row electrodes Y 1  to Y n  and the wall charges of all of the discharge cells are once erased (all erasing operation). 
     Subsequently, the address driver  6  supplies the address pulse AP OD  to each of the odd number designated column electrodes among the column electrodes D 1  to D m . At the same timings as the supply timings of the address pulse AP OD , the second sustain driver  8  supplies a data writing pulse WP to the odd number designated row electrodes Y 1 , Y 3 , Y 5 , Y 7 , . . . . In accordance with this operation, the wall charges are again formed in all of the discharge cells existing in the crossing portions between the odd number designated “column electrodes” and the odd number designated “row electrode pairs”. The address driver  6  subsequently supplies the address pulse AP EV  to each of the even number designated column electrodes among the column electrodes D 1  to D m . At the same timings as the supply timing of the address pulse AP EV , the second sustain driver  8  supplies the data writing pulse WP to the even number designated row electrodes Y 2 , Y 4 , Y 6 , Y 8 , . . . . In accordance with this operation, the wall charges are again formed in all of the discharge cells existing in the crossing portions between the even number designated “column electrodes” and the even number designated “row electrode pairs” (selective writing operation). 
     The first sustain driver  7  and second sustain driver  8  subsequently alternately supply the sustain pulses IP X  and IP Y  to the row electrodes X and Y of the PDP  10 . In this instance, the discharge cell in which the wall charges remain executes the light emission discharge each time the sustain pulse IP X  and IP Y  are alternately supplied and maintains its light emission discharging state (second sustain discharging operation). 
     That is, by executing the second sustain discharging operation, only the discharge cell in which the wall charges were formed by the selective writing operation subsequently executes the light emission discharge for only the discharge sustain period t a . 
     In the half tone display method according to the invention as mentioned above, by enabling the mode in case of providing a plurality of sustain discharge periods in one divided period and executing the discharge light emission in the whole period of time and the mode in case of stopping the light emission in at least one sustain discharge period to be selectively executed every discharge cell (pixel), the pseudo outline can be reduced. 
     By using the above driving method, a gradation expression such that a plurality of discharge cells are regarded as one block such as dither or diffusion error can be realized. 
     For example, two discharge cells (for instance, G 11  and G 12 ) surrounded by a broken line in FIG. 36 are regarded as one block and the light emission driving is executed by a driving format as shown in FIG.  37 . In this instance, among the seven divided periods comprising the first to seventh divided periods shown in FIG. 37, the light emission driving in which two sustain discharge periods as shown in FIG. 6 are provided is performed in only the seventh divided period of the smallest weight of the light emitting period. According to the driving, each of the discharge cells G 11  and G 12  can have any one of states  1  to  4  as shown in FIG. 38 in the seventh divided period. Now, it is assumed that the luminance level which is visually sensed is an average light emitting period of all of the discharge cells existing in one block, according to the light emission by the state  2  of each of the discharge cells G 11  and G 12 , the luminance corresponding to the light emitting period “1” is obtained. According to the light emission by the state  4 , the luminance corresponding to the light emitting period “3” is derived. 
     That is, according to the above construction, even if the divided period to execute the light emission of the light emitting period “1” is not provided, the luminance level corresponding to each of the light emitting periods “1” and “3” can be obtained. The half tone display of 256 gradations, therefore, can be realized in the seven divided periods comprising the first to seventh divided periods as mentioned above. 
     The first and second conversion tables which are used in the first and second data converting circuits  31  and  33  in order to execute the light emission driving by the driving format as shown in FIG. 37 are as shown in FIG.  39 . In FIG. 39, it is assumed that bits  8  to  3  of the received pixel data become bits  7  to  2  of the conversion pixel data as they are. 
     In the embodiment shown in FIGS. 36 to  39 , the operation which is used in case of regarding two discharge cells as one block has been described. The invention can be also similarly applied, however, to a case of regarding four discharge cells as one block as shown by a broken line in FIG.  40 . 
     FIG. 41 is a diagram showing a light emission driving format which is applied to a case where four discharge cells are regarded as one block as mentioned above. 
     In FIG. 41, one frame period is divided into five divided periods comprising the first to fifth divided periods and the light emission driving as shown in FIGS. 42A to  42 H is executed in only the fifth divided period. That is, the light emission at the light emission luminance levels “1” to “16” corresponding to the average light emitting period of four discharge cells is executed in only the fifth divided period. 
     The half tone display of 256 gradations, therefore, can be performed in five divided periods comprising the first to fifth divided periods as mentioned above. 
     FIG. 43 is a diagram showing an internal construction of the data converting circuit  3  to execute the light emission driving by a driving format as shown in FIG.  41 . 
     In FIG. 43, a first data converting circuit  441 , a second data converting circuit  442 , a third data converting circuit  443 , and a fourth data converting circuit  444  convert the pixel data of 8 bits into 5-bit conversion pixel data A to D, respectively, in accordance with a conversion table as shown in FIG.  44 . In FIG. 44, it is assumed that bits  8  to  5  of the received pixel data become bits  5  to  2  of the conversion pixel data as they are. A selector  440  alternatively supplies any one of outputs from the first to fourth data converting circuits  441  to  444  to the memory  4  so as to obtain the conversion pixel data A to D in a format as shown in FIG. 40 for each discharge cell. 
     A γ correcting circuit having A characteristics shown by an alternate long and two short dashes line in FIG. 45 and a γ correcting circuit having B characteristics shown by a solid line in FIG. 45 can be also provided at the front stages of the first data converting circuit  31  and second data converting circuit  33  shown in FIG.  2 . According to the γ correction, by modulating the pixel data every discharge cell so as to obtain the opposite characteristics in the horizontal, vertical, and time directions, the pixel data is corrected so that the average luminance level in the time direction becomes the inherent level. According to the γ correction, a strong bright line (dark line) which is caused when the luminance level of the pixel data is shifted from “63” to “64” or from “127” to “128” can be reduced. 
     In the embodiment, although the same light emitting pattern is allocated to the pixel data corresponding to each of the R (red) component, G (green) component, and B (blue) component in the video signal, the light emitting period can be also changed every discharge cell corresponding to each color as shown in a driving format of FIG.  46 . 
     According to the driving method shown in FIG. 46, the light emission driving of the PDP can be executed at a proper balance in which differences of the light emitting sensitivities of the discharge cells to perform the light emission of R (red), G (green), and B (blue) were corrected. 
     As data conversion tables which are used in the first data converting circuit  31  and second data converting circuit  33  shown in FIG. 2, data conversion tables shown in FIGS. 47 and 48 can be also used besides the data conversion tables shown in FIGS. 3,  4 ,  16 , and  17 . 
     In the embodiment, after the resetting operation was certainly once performed in the head portion of each divided period, the operation is shifted to the address operation. Even if the resetting operation is not performed in a partial divided period in one frame (field) period, however, the normal light emission can be performed. 
     FIG. 49 is a diagram showing one example of a driving format made in consideration of the above point. FIGS. 50 and 51 are diagrams showing an example of data conversion tables which are used in each of the first data converting circuit  31  and second data converting circuit  33  when the driving of the PDP is executed by the driving format. 
     In FIG. 49, the 8-bit pixel data is converted into 6-bit data by the dither process or the like, a subframe (subfield) SF of a long light emitting period corresponding to each of upper two bits is divided into two subframes (subfields) (namely, SF 5 →SF 5   a  and SF 5   b ; further, SF 4 →SF 4   a  and SF 4   b ) as shown in FIG. 16, and the order of the subframes is exchanged every discharge cell. 
     In this instance, as shown in FIG. 49, no reset period is provided in each of the second and eighth divided periods shown in FIG.  49 . 
     That is, since the discharge cell which is selected as a light-on discharge cell in the address period of SF 5   a  or SF 5   b  is also certainly selected as a light-on discharge cell in SF 4   a  or SF 4   b , the wall charges remaining in SFf a  or SFf b  can be left as they are without resetting. 
     According to this construction, since the number of times of the resetting operation which is executed for one frame (field) period is reduced from 8 to 6, the contrast of the image can be improved. 
     When the 8-bit pixel data is converted to 6-bit data by the dither process or the like and the light emission driving is executed in eight divided periods as mentioned above by using the 6-bit data, a weight of each divided light emitting period can be also set so as to reduce the number of inversion bits which are caused due to a carry of the bits. 
     FIG. 52 is a diagram showing an example of a driving format made in consideration of the above point. FIGS. 53 and 54 are diagrams showing an example of data conversion tables which are used in each of the first and second data converting circuits  31  and  33  when the driving of the PDP is executed by the driving format. 
     In the light emission in the light emitting mode A, the period ratio of the light emission which is executed in each divided period is as follows. 
     First divided period:72 
     Second divided period:32 
     Third divided period:20 
     Fourth divided period:4 
     Fifth divided period:8 
     Sixth divided period:12 
     Seventh divided period:44 
     Eighth divided period:60 
     In the light emission in the light emitting mode B, the period ratio is as follows. 
     First divided period:60 
     Second divided period:44 
     Third divided period:12 
     Fourth divided period:8 
     Fifth divided period:4 
     Sixth divided period:20 
     Seventh divided period:32 
     Eighth divided period:72 
     In FIG. 46, although the operation example such that the light emitting periods are changed every discharge cell to perform the light emission of R, G, and B has been shown, it is also possible to combine a technique such that a plurality of different light emitting patterns are allocated every discharge cell or every plurality of adjacent discharge cells as shown in FIGS. 6,  16 , and  25  to  31  to the above operation example. 
     FIG. 55 is a diagram showing an example of a driving format made in consideration of the above point. 
     In FIG. 55, one frame (field) period is divided into eight divided periods comprising the first to eighth divided periods. In each divided period, the resetting operation R, address operation AD, and selective erasing operation S 1  to S 4  as mentioned above are executed. By the selective erasing operations S 1  to S 4 , the sustain discharging operation is divided into five operations as shown in FIG.  55 . 
     According to the driving format shown in FIG. 55, a control is made so that the ratio of the maximum light emission luminance for the discharge cells to perform the light emission of each of G (green), R (red), and B (blue) is as follows. 
     Discharge cell to perform the light emission of G (green):512 
     Discharge cell to perform the light emission of R (red):765 
     Discharge cell to perform the light emission of B (blue):1020 
     Further, as shown in FIG. 55, two different light emitting patterns (light emitting modes A and B) are allocated every discharge cell corresponding to each of G (green), R (red), and B (blue) and the light emission in the light emitting modes A and B is executed in the form shown in, for example, FIG. 20 mentioned above. 
     According to the invention as described in detail above, the display order of the divided periods (subfields) is exchanged every discharge cell or every discharge cell block in which a plurality of adjacent discharge cells are combined. 
     An effect such that the bright line or dark line (pseudo outline) which is caused at the time of a specific gradation change (when a flat image moves and its gradation level transverses a boundary of 2 n ) is apparently set off as bright and dark patterns on every other discharge cell or every other discharge cell block is improved. A flickering or a pseudo outline can be sufficiently suppressed.