Abstract:
The invention implements a Positive Emitter Coupled Logic (PECL) output using CMOS transistors that approximate the Motorola ECL characteristics into standard PECL termination schemes. By creating a PECL output using a switchable current source the PECL output can be integrated into a Low Voltage Differential Signaling (LVDS) structure. The invention allows the user to switch between PECL and LVDS outputs via control logic by enabling the specific circuit elements for each signaling technology. With this invention, the combination of two drivers on one IC device gives system designers the flexibility to use the same circuitry in two separate signaling schemes. Thus, the designers can select to use one output characteristics or the other for their designs.

Description:
BACKGROUND OF THE INVENTION 
     The invention generally relates to electronic devices, and more particularly to an output structure for PECL (Motorola Positive Emitter Coupled Logic)/LVDS (Low Voltage Differential Signaling) signaling methods. 
     In telecom and networking systems, signaling methods have been used to route signals from one device to another. In many high speed signaling methods, both PECL and LVDS point-to-point techniques have been used. PECL is a standard developed by Motorola, in which the output node voltages are Vdd−1 volts and Vdd−1.6 volts. On the other hand, LVDS is the EIA-644 standard, in which the output differential voltage swing is ±400 mV. Many designers and manufacturers of telecom and networking system products would like the flexibility to choose either PECL or LVDS signaling levels for their designs. However, due to the performance limitation on LVDS which requires very low capacitance on the output node, the output driver that implements the signaling methods is limited to only one characteristic, i.e., it would have to be either PECL or LVDS, but not both. Otherwise, neither would perform to the PECL/LVDS specifications. 
     Attempts have been made to combine two output drivers to separately implement PECL and LVDS. Typically, these two output drivers are connected in parallel, and a designer may choose to enable one of the drivers to implement one of PECL and LVDS for a particular design. However, this type of circuit has a number of disadvantages including large size, high cost and inflexibility, etc. 
     Therefore, there is a need for an output structure that uses the same circuitry to implement the two different signaling schemes on one IC device so as to give designers the flexibility in their designs. 
     SUMMARY OF THE INVENTION 
     The invention provides an output structure that uses the same circuitry to implement two different signaling methods, PECL and LVDS, on one IC device. This gives designers the flexibility in their designs. 
     According to an embodiment of the invention, an output circuit is provided and comprises a first output block having a first output port and a second output block having a second output port. The first and second output blocks are configurable to provide first output characteristics at the first and second output ports compatible with a first signaling method (e.g., the PECL standard), in response to first external control signals. The two output blocks also provide second output characteristics at the first and second output ports compatible with a second signaling method (e.g., the LVDS standard), in response to second external control signals. 
     According to this embodiment of the invention, the first and second output blocks re substantially identical to each other. Each output block includes a switchable current source that supplies a selected one of a plurality of predetermined currents at its output port, in response to selected external control signals. 
     With the present invention, the same circuitry is used and functions as two drivers on one IC device. It allows system designers to use the same circuitry in two separate signaling schemes. Thus, the designers can select to use one output characteristics or the other for their designs. 
     Other objects and attainments together with a fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention is explained in further detail, and by way of example, with reference to the accompanying drawings wherein: 
     FIG. 1 shows a universal PECL/LVDS output structure according to an embodiment of the invention that is configured to implement a PECL output; 
     FIG. 2 shows a universal PECL/LVDS output structure that is configured to implement a LVDS output, according to an embodiment of the invention; and 
     FIG. 3 shows an exemplary schematic diagram of each of the output blocks in FIGS.  1  and  2 . 
    
    
     Throughout the drawings, the same reference numerals indicate similar or corresponding features or functions. 
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 shows a universal PECL/LVDS output structure  10  according to an embodiment of the invention that is configured to implement a PECL output. In FIG. 1, output structure  10  is connected between control logic  20  and a standard PECL termination circuit  30 . Output structure  10  comprises a first output block  12  and a second output block  16 . Each of the two output blocks comprises a switchable current source that can supply 4 mA, 6 mA, 10 mA or 20 mA current. Control logic  20  allows a user to switch output structure  10  between PECL and LVDS signaling methods (via outputs VoutA and VoutB) by enabling specific circuit elements for each signaling technology. 
     In configuring output structure  10  to implement a PECL output, input signals from control logic  20  set one of the output blocks, e.g., block  12 , to a high state so that VoutA is Vdd-1 volts and the other block, e.g., block  16 , to a low state so that VoutB is Vdd-1.6 volts. The resulting outputs VoutA and VoutB are compatible with PECL voltage levels. When a block is in a high state, its inputs V10 mAPMOS, V6 mAPMOS and V4 mAPMOS are activated to enable three corresponding current sources, so that the block supplies a total current of 20 mA. When a block is in a low state, the input V6 mAPMOS is activated to enable a corresponding current source so that the block supplies a 6 mA current. The schematic diagram of each block is shown in FIG. 3, which will be described below in detail. 
     In this embodiment of the invention, the PECL output is implemented using CMOS transistors that approximate the Motorola ECL characteristics into a standard PECL termination circuit  30 . PECL termination circuit  30  includes two resistors  32  and  36  each having a resistance value of 50 ohms and being connected to a voltage of Vdd-2 volts. Resistors  32  and  36  can be the Thevenin equivalent resistances. By implementing a PECL output using a switchable current source, the PECL output can be integrated into a LVDS structure as will be described below. 
     FIG. 2 shows universal PECL/LVDS output structure  10  that is configured to implement a LVDS output, according to an embodiment of the invention. In FIG. 2, output structure  10  is connected between control logic  20  and a LVDS termination circuit  40 . Termination circuit  40  includes two resistors  42  and  46  connected together in series, each having a resistance value of 50 ohms. A capacitor  48  representing parasitic capacitance is connected in parallel to resistors  42  and  46 . 
     In configuring output structure  10  to implement a LVDS output, input signals from control logic  20  activates the V4 mAPMOS input of one of the blocks, e.g., block  12 , and the V4 mANMOS input of the other block, e.g., block  16 , so that block  12  pushes a 4 mA current and block  16  sinks a 4 mA current. The resulting differential voltage across resistors  42  and  46  between VoutA and VoutB has a ±400 mV. The LVDS standard has a minimum of 100 mV. 
     FIG. 3 shows an exemplary schematic diagram of each of output blocks  12  and  16 . In this circuit, the NMOS input (V4 mANMOS) and the PMOS inputs (V4 mAPMOS, V6 mAPMOS and V10 mAPMOS) are not activated at the same time. If the NMOS input V4 mANMOS is activated, a 4 mA current is generated at the output Vout. Similarly, if any of the PMOS inputs V4 mAPMOS, V6 mAPMOS and V10 mAPMOS is individually activated, the corresponding current (i.e., 4 mA, 6 mA or 10 mA) is generated at the output. If any combination of the PMOS inputs is activated, a current equal to the sum of the corresponding currents is generated at the output Vout. For example, if all of the three PMOS inputs are activated, a current equal to the sum of the corresponding currents (i.e., 4+6+10) or 20 mA is generated at the output Vout. 
     The detailed operation of the circuit in FIG. 3 is described next. If input V4 mANMOS is activated, a 400 μA current (i.e., 4 times the current generated by current source  13 ) flows through transistor MP 8 . This 400 μA is generated via a current mirror composed of transistors MP 7  and MP 8 , based on the ratio of the gate width of MP 8  (i.e., 20) and that of MP 7  (i.e., 5 ). This current is again multiplied by a factor of 10 and a resulting 4 mA current is generated at the output Vout via a current mirror composed of transistors MN 11 , MN 13 , and MN 0 -MN 3 . In a similar manner, this 4 mA is generated based on the ratio of the sum of the gate widths of transistors MN 13  and MN 0 -MN 3  (i.e., 10×5) and that of transistor MN 11  (i.e., 5). 
     On the other hand, a 100 μA current flows through transistor MP 6  and is generated by a current mirror composed of transistor MP 7  and MP 6 , based on the ratio of their gate widths (i.e., 5/5). If only input V4 mAPMOS is activated, a 200 μA current flows through transistor MN 5  and is generated by a current mirror composed of transistors MN 4  and MN 5 , based on the ratio of their gate widths (i.e., 10/5). This current is multiplied by a factor of 20 and a resulting 4 mA current is generated at the output Vout. This 4 mA current is generated by a current mirror composed of transistors MP 5  and MP 0 -MP 4 , based on the ratio of the gate width of MP 5  and the sum of the gate widths of MP 0 -MP 4  (i.e., 40×5/10). Similarly, if only input V6 mAPMOS is activated, a 300 μA current flows through transistor MN 8  and is generated by a current mirror composed of transistors MN 4  and MN 8 , based on the ratio of their gate widths (i.e., 15/5). This current is multiplied by a factor  20  in a similar manner and a resulting 6 mA current is generated at the output Vout. Likewise, if only input V10 mAPMOS is activated, a 1 mA current flows through MN 9  and is generated by a current mirror composed of transistors MN 4  and MN 9 , based on the ratio of their gate widths (i.e., 50/5). This current is also multiplied by 20 in a similar way and a resulting 20 mA current is generated at the output Vout. If all of the PMOS inputs are activated, a resulting current of 20 mA is generated at the output Vout. 
     Therefore, the present invention provides flexibility and allows the user to switch between PECL and LVDS by enabling specific circuit elements for each signaling technology. 
     While the invention has been described in conjunction with specific embodiments, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. For example, CMOS or Bipolar CMOS circuits may also be used to implement the present invention. Accordingly, it is intended to embrace all such alternatives, modifications and variations as fall within the spirit and scope of the appended claims.