Abstract:
A method of processing digital information prior to recording comprises converting input digital words into code words, each of the same period as the input digital word but containing a greater number of time slots than the number of bit locations in the digital word, providing a plurality of groups of code words and selecting the group from which a code word will be taken in any instance on the basis of the immediately preceding code word. The code words are defined such that there is a minimum spacing of three time slots between transitions and no transition is permitted in the last time slot. Two main groups of code words are provided which each have a transformed version. Apparatus for carrying out the method as described as is apparatus for decoding the encode words in replay.

Description:
BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The present invention relates to a method and apparatus for processing digital signals prior to recording. More particularly but not exclusively the digital signals represent television video signals. 
     A channel code which had a minimum separation of 11/2 bit cells and which also was capable of statistically controlling the low frequency components was described in our co-pending U.K. Application No. A-2,141,906. For each successive group of eight bits it is possible, theoretically, (at least on average) to identify just over 453 discrete combinations and this should make it possible to construct a blockcode with controlled low frequencies with a minimum transition separation of 11/2 bit cells. 
     An alternative proposal has been made which operates on a bit-by-bit basis. Consideration has been given to the realisation of this alternative proposal but there are a number of difficulties which stem from the combination of the necessary high speed, the look ahead and the modulo-three requirements of parts of the coder. 
     SUMMARY OF THE INVENTION 
     The present invention provides a method for processing digital information for recording comprising the steps of inputting a succession of input digital words each comprising a plurality of bit locations, generating a respective code word for each digital word with each code word being of the same duration as a digital word but having a number of time slots greater than the number of bit locations in an input word providing a plurality of groups of code words, and selecting for each digital word a code word from one of the plurality of groups on the basis of the immediately preceding code word used. 
     Preferably, in each code word there is a period of three time slots between adjacent transitions. It is also advantageous to use more than two groups of code words e.g. two main groups may be used with each main group having a transformed or &#34;opposite&#34; group. 
     An advantage of the method is that less read only memory is required whilst approaching close to the theoretical limit of just over 453 different combinations in each block of 8 cells. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In order that the present invention be more readily understood an embodiment thereof described by way of example with reference to the accompanying drawings, in which : 
     FIG. 1 shows the basis of a first code book for 4-bit words; 
     FIG. 2 shows the basis of a second code book for 4-bit words; 
     FIG. 3 shows the time of transitions for certain combinations in the first and second code books; 
     FIG. 4 shows the basis of a first code book for 8-bit words; 
     FIG. 5 shows the basis of a second code book for 8-bit words; 
     FIG. 6 shows in block diagram form an encoder which utilizes the first and second code books for 8-bit words; 
     FIG. 7 shows truth tables to assist understanding of the encoder shown in FIG. 6; 
     FIG. 8 shows in more detail one way in which a part of the encoder of FIG. 6 may be implemented and is accompanied by its truth table; 
     FIG. 9 shows in block diagram form a decoder for decoding the signal encoded by the encoder of FIG. 6; and 
     FIGS. 10A-10J are a print out of the complete first and second code books. 
    
    
     DETAILED DESCRIPTION 
     Before describing the invention in detail, it is considered helpful to explain some basic principles of the coding system being used. It is to be remembered that the techniques disclosed in our co-pending application identified above are still being used and attention is directed to that case for further details. Suffice to say that the present invention comprises a method of processing digital information for recording purposes. The processing is organised on a word-based arrangement and generates a code word for each input digital word to be recorded, the code word occupies the same time as the input digital word but has at least double the number of time slots with respect to the number of bit locations in an input digital word. In a code word, transitions are not permitted at specified locations. 
     For a minimum transition separation of three half cells, the number of different combinations which can be portrayed as the number of half-cells increases from 0 to 34 is shown in the following table: 
     
                                           TABLE 1__________________________________________________________________________0..1    6..13    12..129          18..1278                24..12664                       30..1254911..2    7..19    13..189          19..1873                25..18560                       31..1839162..3    8..28    14..277          20..2745                26..27201                       32..2695423..4    9..41    15..406          21..4023                27..39865                       33..3950334..6    10..60    16..595          22..5896                28..58425                       34..5789495..9    11..88    17..872          23..8641                29..85626                       etc.__________________________________________________________________________ 
    
     A way of preventing transitions from being less than three half-cells spacing between blocks would be to arrange that there were two half-cells without transitions between the end of one block and the start of the next. An eight bit data block, allowing for the two half-cells between blocks, would leave 14 half-cells for information which can provide 277 combinations. This is significantly less than the 453 combinations theoretically available on average, amounting to only 61%. If a 16 bit data block could be realised, providing 30 information slots and 125491 combinations, this would provide a number of combinations equivalent to 354 per eight bit data block. This is better but it is still far short of the 453 combinations theoretically available. 
     A much better coding strategy has been discovered and to illustrate the principle this will be described for a four bit-data block. This coding strategy uses two alternative Code Books `A` and `B` and the basis for each of these is shown in FIGS. 1 and 2 respectively. 
     In Code Book `A` there is a first range (A) in which transitions are barred in time slots 0 and 1 in the word being coded and also in the subsequent word. A `O` in a time slot indicates that a transition is not permitted, a `:` indicates that a transition is permissible providing no two transitions are closer than three half-cells. There are 13 combinations of patterns and for this first range (A) the subsequent word will also be coded on the basis of Book `A`. The second range `B` has word transitions barred in time slots 0,1,6,7 and there must be a transition in time slots 0 or 1 of the following word i.e. within the brackets. Note however that the choice of the two positions will be determined by the next 4-bit word. This second range (B) provides a further 6 combinations making 19 in all available for Code Book `A`. When the range `B` is used for one word the next word must be coded on the basis of Code Book `B` shown in FIG. 2. 
     Again there are two basic ranges `A` and `B` but in this case each is split into two giving sub-ranges A0, A1, B0 and B1. For A0 and B0 there is a defined transition at time slot 0 whereas for A1 and B1 it is at time slot 1. A0 and A1 give 9 and 6 combinations respectively and for these 15 cases the following word is coded on the basis of Code Book `A`. B0 and B1 give 4 and 3 combinations and for these 7 cases the following word is coded on the basis of Code Book `B`. The total number of combinations is therefore 22 for Code Book `B`. 
     For random data, Code Book (A) would be used on about 68% of occasions, Code Book (B) for the remainder, so the average number of combinations for every 4 bit-cells would be just under 20 or approximately 400 combinations in eight bit-cells - an efficiency of about 88% of the theoretical limit. 
     FIG. 3 shows the time of transitions for the 19 and 22 possible combinations in Code Books `A` and `B` respectively. 
     Since the number of available combinations exceeds the sixteen necessary to carry 4 bits of binary information it is possible to eliminate patterns having less desirable characteristics, for example the one having no transitions, and/or to allocate two different patterns to certain 4 bit combinations. This may be most usefully realised by replacing Code Book `A` by two alternatives Code Book `A` `same` and Code Book `A` `opposite`. For at least 13 of the 16 binary combinations the patterns stored in the alternative code books would be the same but for three combinations the patterns in the `same` and `opposite` sections could differ. For these combinations the patterns would be chosen on the basis that the direct component due to the pattern would be in the `same` or the `opposite` direction to the polarity existing immediately before some sensible reference time for example just prior to time slot `0`. 
     If a `1` be stored to indicate a transition and a `0` to indicate no transition then the parallel information from the Read Only Memory when serialised could cause a change of state of a divide by two counter to generate the signal to be recorded. 
     The same type of splitting of Code Book `B` into sections `same` and `opposite` would be used but in this case at least 10 patterns would appear unchanged in both sections whilst 6 patterns could differ. 
     If an odd number of transitions occurs in a word then the polarity at the reference time for the next word is reversed. 
     A total of six address bits for the ROM would be required and these consist of 4 for the binary date, one to select between Code Books `A` and `B` and one to select between `same` and `opposite`. 
     It might appear at first sight that nine output bits are required, eight to indicate the presence or absence of a transition in each of the 8 time slots and one to instruct the ROM which of the Code Books `A` and `B` to use for the next 4-bit word. 
     By means of three 2-input gates, two binary digits giving four states can be very easily used to produce the four possible patterns that can occur by three consecutive time slots; these possible patterns consist of no transition or a transition in the first, second or third time slot. It is also possible to use 5 bits to control transitions in 8 time slots. Transitions in time slots 0 and 1 can only occur when Code Book `B` is in use and must occur in one of these positions so a simple ROM output bit may be used to control which of these two time slots must contain the transition. 
     If there is spare output capacity in the ROM it would be worth considering that one bit should be used to indicate if a word results in an odd or an even number of transitions since this is required information for the control of the direct component. Spare output capacity could also be used to give a measure of the direct component being produced by each word but the sign of this must also take note of the polarity of the signal at the reference time. 
     Since there are many alternatives for the ROM system, which can even include direct generation of the signal to be recorded by the ROM (but probably in parallel form) it seems pointless giving ROM details and that transition patterns are all that is necessary to define the channel code. 
     So far the information has been on a 4-bit coder, obviously other sizes are possible and the one of particular interest is a coder for 8-bits. For such a coder FIGS. 4 and 5 show the basis of Code Books `A` and `B` which yield 406 and 466 combinations respectively. The average of these when weighted for frequency of occurrence is about 425 or about 94% of that theoretically achievable. 
     The reason that a higher efficiency is not achieved stems from the occasions when transitions in the 14 time slot are barred even when the next transition is in time 1 of the next word. 
     To save space in providing information for the look-up table and to make computation easier, the number of transitions in time slots 0-15 inclusive, the Code Book to use for the next word, and the time slots in which transitions occur, are combined in one 11 digit word. First digit (in the tens position) gives the number of transitions in time slots 0-15 inclusive. The second digit (units position) gives which Code Book is to be used for the following word O corresponds to A, 1 to B. 
     After the decimal point the first digit gives the address of the first transition, this never exceeds 8. The next pair and subsequent pairs of digits give addresses of the subsequent transitions but note that pairs 00 do not signify a transition. For example in Code Book `B` or `1` level 16 `same` the number is 50.003081114. ##STR1## 
     In this particular case although it is from the `same` the magnitude of the shift of direct component happens to be zero as can be calculated. If `B` level 16 `opposite` had been selected the number would have been 50.004071114 with transitions in the 0,4,7,11 and 14th time slots and the shift would have been -2 i.e. a shift of 2 in the opposite direction to the polarity existing just before the zero time slot. 
     The number of address bits for the ROM will total 10, 8 for the data, one for differentiating between Code Books `A` and `B8` and one `same` or `opposite`. As mentioned earlier 1 output bit will suffice for time slots 0 and 1, taken as a pair, and 2 bits for each of the triads 2--4, 5-7, 8-10, 11-13 and 14-16 making 11 bits in all; to refer to time slot 16 is incorrect but it can be used to control the selection between Code Books `A` or `B` to be used for the next 8-bit word. A total of 11 output bits is required and since 8-bit wide ROMs are common there could remain 5 bits surplus when two are used. 
     These 5 bits could be used and are sufficient to aid the evaluation of a running sum and to provide the important information whether the number of transitions in a word is odd or even and the sign and magnitude of the change. None of these bits is essential since the information may be derived from the transition information but this information may make it easier to achieve fast operation and simplify running sum computation. 
     It may be useful to note that the code with six transitions at time slots 0,3,6,9,12 and 15 is not used; this might be useful for synchronisation. The continuation 2, 5, 8, 11 and 14 is used for level 5 Code Book `A`. Another useful feature for synchronisation is that a transition in time slot 14 never preceeds any word in Code Book `B`. 
     The constraints used in the Code Books are that no transitions are less than 3 or more than 12 time slots apart with the exception that between transitions in adjacent words the maximum separation may occasionally be 15 time slots; the latest first transition is in time slot 9 and the earliest last transition is in time slot 10 ignoring the cases where a further transition is forced to occur in time slots 0 or 1 in the following word. 
     FIG. 6 shows the above described arrangement in more detail. An 8-bit input latch feeds the information word to be carried as an address for a 10×16 programmed ROM 62. Outputs D o  -D 10  of the ROM 62 are fed to six assemblies of latches 63-68 and are operated thereby in accordance with the truth tables shown in FIG. 7. 
     The assemblies of latches 68-68 transform the eleven outputs D o  -D 10  from ROM 62 into sixteen signals, fifteen of which are fed through a further block of latches 70 clocked a word frequency and into a parallel to series converter 71. The output of the converter 71 os fed through a divide-by-two circuit 72 and an output latch 73 which is clocked at bit rate e.g. sixteen times word rate. 
     The sixteenth signal from the assemblies of latches is used to indicate whether Code Book `A` or `B` should be used; if the sixteenth signal is a `O` Code Book `A` is used for the next word while if the signal is a `1` Code Book `B` is used. The sixteenth signal is fed through a latch 75 clocked at word frequency and the output of the latch 75 is fed as an input to latch assembly 63 and as an address bit to the ROM 62. 
     Outputs D 11  -D 14  of the ROM 62 are assembled in an accumulator 76 and the sixteenth output D 15  is added to or subtracted from the signal in the accumulator 76 after being fed through a latch 77 and a divide-by-two-circuit 78. The output of the accumulator is used as the tenth addressing input to the ROM 62. 
     As shown in FIG. 8, the accumulator 76 may be constructed from a modulo 256 counter circuit 76a which feeds an 8-bit latch 76b. PROM 62 contains 1024 words of 16 bits and is addressed chiefly by the 8 bit words (A 0  to A 7 ) containing the information to be carried. However, there are two further address bits A 8  and A 9 . It is convenient to consider that if A 8  is `zero` then Code Book `A` will be used whereas Code Book `B` will be used if A 8  is in the `one` state. For each of these code books some of the words output from the PROM will differ depending on the state A 9  ; the state of A 9  is controlled by the most significant bit of an accumulator which will be assumed to operate in module 256 Initially this should be set to represent a 128 state (127 would also be usable) but 128 will be assumed. If the state is in the range 128 to 255 inclusive then A 9  will be high and this selects `opposite`, if the state is in the range 0 to 127 inclusive `same` will be selected. 
     All the inputs to the parallel to serial converter 71 are in the `zero` state except for those where transitions are required; these are in a `one` state. Whenever a `one` state reaches the output of the parallel to serial converter 71 the divide-by-two circuit 72 changes state so causing the production of a transition. 
     Knowing the required transition patterns, the patterns of data D 0  to D 10  may be derived from consideration of the Truth Tables shown in FIG. 7. Note however that for `A` words the state of D 0  is irrelevant and that D 9  and D 10  are both `ones` when the following word is required to be from the `B` Code Book. 
     For the embodiment shown there remain 5 bits D 11  -D 15 , of the 16 output bits, that are not used for the information being carried. These may be used for evaluating the running-sum rapidly. The running sum is usually defined for NRZ as follows. At the initial start of data the running-sum is assumed to be zero. As each succeeding bit occurs the running-sum is incremented by one if the bit represents a `one` whilst it is decremented by one if the bit represents a `zero`. For NRZ after an even number of bits the running-sum must be even. With this method of running-sum calculation the running-sum at the end of the word only becomes available after the start of the last bit of the word. 
     With the 2/3 coder a choice needs to be made for the next word to be coded dependent on the running-sum which will exist at the end of the current word. The variation of the running-sum during a word can never be greater than the range ±8; the extreme values would only occur if no transitions occurred within a word. It is assumed when the running-sum is computed that a state is counted as ±1/2 per half bit-cell. For an even number of half bit-cells the possible sum variations during a word always have integer values. 
     For code-books which are practical there will always be at least one transition in a word preventing the extremes of the range being used so a four bit number, capable of representing the number range -8 to +7, will always be sufficient. It is convenient to represent zero variation by the binary number 0000 and to add decimal 16 to negative numbers. The modulo 16 numbers can be changed to the appropriate modulo 256 numbers by applying the D 11  input to the adder also to the higher significance inputs as shown in FIG. 8. 
     It is suggested that the running-sum variation during a word should be the one starting from the centre of half-cell `O` up to the same point on the following word and that it be assumed that the state prior to the start should be `one`. 
     Since the polarity of the signal immediately before the start of half-cell `O` will reverse each time a previous word has an odd number of transitions it is necessary to appropriately switch the accumulator from addition to subtraction. This is achieved by making D 15  a `one` in all cases where the number of transitions in a word is odd. At the end of that word the divide by two changes state so switching the accumulator from add to substract or vice versa at the appropriate times. 
     There are many requirements of the replay circuitry which are unconnected with the channel code used and these will not be considered and it will be assumed that, a transition causes a `1` state lasting one time slot, that clocks at twice the bit cell frequency and that word framing are available. 
     The important step is how to reduce a pattern of transitions which may be occurring at 16 different points per word into say 10 or 11 binary digits used for addressing a ROM of practical size. 
     There are two approaches of interest. One is based on auxilliary ROMs. Only 28 different combinations of valid transition patterns may occur in eight adjacent time slots; this number can be portrayed by 5 bits. A small read only memory with 256 address locations would be used for this purpose and the speed could be so high that the same ROM could be used twice per word rather than to use two identical ROMs. This method can incorporate the checking of the minimum separation of transitions of three time slots. Table 2 shows the relationship between the number of, adjacent time slots, possible patterns and the number of bits; in practice some limitations such as the first transition occurring no later than time slot 8 (ninth time slot) may be used to slightly decrease the number of possible patterns if this is high. It is desirable that at least one additional pattern be available so that faulty operation can be signalled when two transitions are apparently separated by less than three time slots. 
     
                       TABLE 2______________________________________No. of time slots      3     4     5   6   7   8   9   10  11  12No. of patterns      4     6     9   13  19  28  41  60  88  129No. of bits      2     3     4   4   5   5   6   6   7   7?______________________________________ 
    
     The alternative method which uses no auxilliary ROM is shown in FIG. 9. 
     Before describing FIG. 9 in detail it is necessary to recall that there is a time slot clock running at double the frequency of the word frame clock and also that in the code words there must be at least three time slots between adjacent transitions. This latter feature requires that a further clock signal be generated where frequency is 1/3 the time slot clock frequency. 
     Turning now to FIG. 9, incoming serialized code words are fed through a seris of latches 101, 102, 103 clocked at time slot frequency which together with EXCLUSIVE OR gates 106 and 107 form a data validation section. The output from gate 106 is fed through a series of latches 111-115 clock at 1/3 the time slot frequency while the output from the gate 107 is fed through another series of latches 121-125 also clocked at 1/3 the time slot frequency. The outputs from the latches 111-115 and 121-125 constitute ten inputs to an 11-input latch 130 which is clocked at word frame frequency. The eleventh input to the latch 130 is derived from a further latch 104 which is with the incoming serialized code words. Every three time slots the latches 111 and 121 capture the information derived from outputs A, B and C of the latches 101, 102, 103 and have the states 01, 10 and 11 for transitions at A, B and C respectively. If A, B and C all have no transition present these latches have the state 00. After a word, the information derived from 15 of the 16 time slots, time slots 0-14, appears at the output of latches 111-115 and 121-125 in coded form. The information for time slot 15 is captured by the latch 104. It will also have previously captured the presence of transitions at time slots 3, 6, 9 and 12 but these are ignored. The eleven input latch 130 operates once per word and transfers the data then present at its inputs to the address inputs of a ROM 131 which contains the data necessary to convert the coded data into the original digital words, i.e. the information relating to both code books `A` and `B`. At the same time the 8 data outputs from the ROM for the previous word are captured by the output latch 132. For this system it is necessary to check for invalid data where transitions occur at less than three time slots separation. If, during a word, A and C or B and C are simultaneously both `ls` the word is invalid. This may either be used as a `flag` on the word but a possible alternative or addition would be to clear the input latch to the ROM when the word is entering and to reserve one output state, for example all `ones`, which may need to be excluded from the normal signal range.