Abstract:
A technique for generating a carry, AND, OR, NAND, NOR, INVERTING logic and sum and carry: operation in a one or at most two device delay by employing negative differential resistance devices. Circuits implemented with this technique are not only extremely fast, but use a small number of active devices as well. This technique could be implemented in building circuits using any transistor Bipolar Transistors, Field Effect Transistors (FETs), High Electron Mobility Transistors (HEMTs), Hetero-junction Bipolar Transistors (HBTs), etc. The negative differential resistance characteristics of the resonant tunneling transistor can be exploited to increase the noise margin. Resonant tunneling devices have the added advantage of working at very high speeds, and could yield propagation delays less than 5ps.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This is a continuation in part of my prior application Ser. No. 452,167, filed Dec. 15, 1989. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to methods and apparatus for generating logic outputs corresponding to several inputs, and more specifically to methods and apparatus for generating CARRY,SUM, AND, OR, INVERTING, NAND and NOR logic outputs. 
     2. Description of the Prior Art 
     Quantum devices like resonant tunneling transistors (RTT) have some distinctive speed advantages over conventional transistors. As functional densities of devices increase, there is an increasing pressure to reduce the device sizes. Quantum effects pose a major problem in shrinking conventional devices. As the devices become smaller and smaller, quantum interference occurs naturally and cannot be avoided. Quantum devices like resonant tunneling transistors (RTT) in fact make use of the quantum effects to operate. The quantum effects however cause negative differential resistance (NDR) characteristics. In the past NDR devices have not been found to be suitable for digital applications. Thus, it is desirable to make use of NDR device for digital applications. It is further desirable to develop a structure which is suitable to microminiaturize the NDR device. 
     Regularity and simplicity are the major features desired for Ultra Large Scale Integration (ULSI). AND, OR, NAND, NOR, CARRY, SUM and INVERTING logical circuits are the basic cells in all circuit designs. The conventional logic elements or cells are not regular which makes autorouting and ULSI very difficult. 
     One of the desired features of logical circuits is fast speed without increasing the complexity. It is desired to achieve logic and fundamental arithmetic operations at a fast speed while reducing the complexity. 
     Simplicity and fast speed have special application on binary addition which is a basic operation performed by all Logic and Arithmetic Operation Units. 
     Let x i  and y i  be binary inputs of bit i, z i  is the sum of the bit i and c i  is the carry out of the bit i, then z i  and c i  can be defined as follows: 
     
         Z.sub.i = X.sub.i + Y.sub.i + C.sub.i-l 
    
     
         C.sub.i = X.sub.i Y.sub.i + X.sub.i C.sub.i-l + Y.sub.i C.sub.i-l 
    
     The above equations indicate that sum z i  of the ith bit depends on the i-lth bit carry out c i-l . If an adder has 64 bits and all C i  (i=0, 1, 2, . . . , 63) ripple through all 63 stages, the c 63  can be generated after 63 stages of delay which will slow the speed of the result of addition. Currently the carry look-ahead technique is the most common approach for achieving faster addition. In this strategy, the input carry bit of stage i is directly generated from the inputs of the preceding stages i-1, i-2, . . . ,i-m. An eight-bit carry look-ahead adder is shown in FIG 1. The carries can be expressed in terms of the propagate Pi=x i  - y i  and generate (g i  =·y i ) terms as 
     
         c.sub.i = g.sub.i + p.sub.i c.sub.i-l. 
    
     This can be solved recursively for the carries and, for example, in an eight bit adder the final carry out is: 
     
         C.sub.out = g.sub.7 + p.sub.7 g.sub.6 + p.sub.7 p.sub.6 g.sub.5 + p.sub.7 p.sub.6 g.sub.4 + p.sub.7 p.sub.6 p.sub.5 p.sub.4 g.sub.3 + p.sub.7 p.sub.6 p.sub.5 p.sub.4 p.sub.3 g.sub.2 + p.sub.7 p.sub.6 p.sub.5 p.sub.4 p.sub.3 p.sub.2 g.sub.1 + p.sub.7 p.sub.6 p.sub.5 p.sub.4 p.sub.3 p.sub.2 p.sub.1 g.sub.0 + p.sub.7 p.sub.6 p.sub.5 p.sub.4 p.sub.3 p.sub.2 p.sub.0 c.sub.in. 
    
     The complexity of the carry expressions increase as the number of look-ahead stages increases. This results in an increase in the fan-in requirements. The fan-in limitations thus limit the number of carry look-ahead stages to about m≦8. 
     To perform a 64-bit addition, eight such 8-bit carry look-ahead adders may be used as shown in FIG. 2. A carry look-ahead addition is performed on each group of eight adjacent bits, and the output carry bit of each group is transferred to the input of its left neighbor. There is thus a ripple carry propagation between groups. To reduce the carry propagation delay, carry look-ahead addition is implemented using tree circuits which may consist of either standard gates with limited fan-in and fan-out, or carry look-ahead modules with a limited number of terminals. Though the speed is marginally increased in such implementations, the number of active devices and the complexity of the circuit increases substantially. 
     The adder circuit described in U.S. Pat. No. 3,280,316 is designed using the conventional equations for the sum and carry. As a result the circuit is very complex (refer to FIG. 9 of the patent). The carry generation will require at least six device (resonant tunneling diode, RTD) delays. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an objective of the present invention to provide methods and apparatus which can effectively use the devices with Negative Differential Resistance characteristics for digital applications. 
     It is another objective of the present invention to provide methods and a structure of the apparatus which is suitable to microminiaturize for ULSI. 
     It is another objective of the present invention to provide methods and apparatus which can generate logic outputs including NAND, NOR, AND, OR, CARRY, SUM and INVERTING at extremely high speed with reduced complexity. 
     It is yet another objective of the present invention to provide methods and a structure of apparatus which are suitable to regularize logic circuits for autorouting for ULSI and fabrication. 
     The above features are achieved in the present invention by using controllable devices in active region. In response to a specific number of logical inputs, the same number of controllable devices are used. Each of the controllable device has a control terminal which receives one of the logical input and an output terminal which generates an output in response to the logical input at the control terminal. Each controllable device also has an I-V curve at the output terminal in response to variation of voltage at the input terminal. All the output terminals are parallely connected to a resistance device which determines a load line for all the controllable device. The connecting point (referred as common output terminal hereinafter) has different I-V curves in response to different input patterns at the input terminals. It is the combination of the I-V curves and the load line that determines a voltage level and hence logic level at the common output terminal. 
     This principle can be applied to resonant tunneling transistor, field effect transistor, bipolar junction transistor and to other negative resistance devices for generating CARRY, AND, OR, NAND, NOR, INVERT and SUM. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is block diagram of an eight bit carry look-ahead adder (prior art); 
     FIG. 2 is a 64 bit adder with 8 bit carry look-ahead (prior art); 
     FIG. 3(a) illustrates the Negative Differential Resistance characteristics; 
     FIG. 3(b) illustrates the I-V characteristics for conventional transistors; 
     FIG. 4(a) is the logic symbol of the circuit to produce complement of carry, NAND and NOR logic, which is concatenated with the inverting circuitry, to generate carry, AND and OR logic; 
     FIG. 4(b) is the schematic diagram of the circuit to produce complement of carry, NAND and NOR logic, which is concatenated with the inverting circuitry, to generate carry, AND and OR logic; 
     FIG. 5 shows the current-voltage characteristics with load lines L 1  for NAND, L for complemented carry out, and L 2  for NOR applications; 
     FIG. 6(a) is a logic symbol of the sum circuit; 
     FIG. 6(b) is the schematic diagram of the sum circuit which includes the sum stage; 
     FIG. 7 shows the V-I characteristics for the generation of complement of sum; 
     FIG. 8 is a circuit of an invertor 
     FIG. 9 shows the current-voltage characteristics of the invertor; 
     FIG. 10 is the conduction band diagram of resonant tunneling transistor used to obtain current-voltage characteristics of FIG. 11 through FIG. 18; 
     FIG. 11 is the I e  -V be  characteristics for the resonant tunneling transistor; 
     FIG. 12(a) is the logic symbol of the circuit to generate carry out, AND and OR logic in a single step, ie, without requiring the invertor stage; 
     FIG. 12(b) is the symbol for resonant tunneling transistor; 
     FIG. 12(c) is the schematic of the circuit to generate carry, AND and OR logic in a single device delay; 
     FIG. 13 shows the simulation results for I e  -V be  characteristics of three resonant tunneling transistors connected as in FIG. 12(c); 
     FIG. 14 is the schematic for generating sum in a single device delay; 
     FIG. 15 illustrates the Ie-Vbe characteristics for the schematic of FIG. 14; 
     FIG. 16 is the schematic diagram of a 64 bit adder using the proposed approach; 
     FIG. 17 is the circuit to produce the I-V characteristics shown in FIG. 18; 
     FIG. 18 shows the simulation results for I e  -V ce  characteristics for the resonant tunneling transistor with V cb  as parameter; 
     FIG. 19(a) is the schematic for generating complement of carry, NAND and NOR logic, using FETs; 
     FIG. 19(b) shows the I D  -V out  characteristics with FETs and the operating points; 
     FIG. 20(a) is the schematic for generating carry, AND and OR logic, using FETs; 
     FIG. 20(b) shows the I D  -V out  characteristics for the schematic of FIG. 20(a) and the operating points; 
     FIG. 21(a) is the schematic for generating complement of carry, NAND and NOR logic, using FETs and a depletion transistor for load; 
     FIG. 21(b) shows the V-I characteristics with depletion load; 
     FIG. 22(a) shows the schematic for generating complement of sum using FETs; 
     FIG. 22(b) shows the I D  -V out  characteristics for the schematic of FIG. 22(a) and the operating points; 
     FIG. 23(a) is a schematic for generating complement of sum using FETs and a depletion load; 
     FIG. 23(b) shows the I D  -V out  characteristics for the schematic of FIG. 23(a) and the operating points; 
     FIG. 24(a) is a schematic for generating Sum; and 
     FIG. 24(b) shows the I D  -V out  characteristics for the schematic of FIG. 24(a) and the operating points. 
     FIG. 25 shows the relationship between the input and output logic levels, the logic operation and operating point; and 
     FIG. 26 shows the relationship between the inputs, outputs and operating point to obtain the sum. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     FIG. 3 (a) is an I-V curve for a resonant tunneling transistor illustrating the negative differential resistance (NDR) characteristics. For a particular voltage range (v1 to v2 as in FIG. 3(a)), over which, as the voltage applied increases, the current decreases, the device is said to exhibit NDR. The non-linear I-V characteristics for bipolar junction transistors and field effect transistors are as shown in FIG. 3 (b). 
     Before discussing the details of CARRY logic output circuit, the definition of CARRY is defined. FIG. 25 shows the relationship between the input and output logic levels, the logic operation and the operating point on the I-V characteristics. In this table, x i  and y i  are the ith bits of the two operands X and Y, C in  is the input carry from the preceding (i-l)th stage, and C out  is the carry out for the addition of x i , y i  and C in . The carry c out  to be propagated to the next (i+l)th stage, is logical &#34;1&#34; only when two or three of the inputs are logic &#34;1&#34;s. This fact can be used to calculate the carry out of each stage without the conventional carry generation and propagation bits. The AND, OR, NAND, NOR and INVERTING logical outputs are self explanatory. 
     For devices with NDR characteristics, the present invention can identify and generate CARRY, AND, OR, NAND, and NOR with the same structure of the circuit. 
     When three transistors with negative differential resistance (NDR) characteristics are connected as in FIG. 4, the I-V characteristics at node A of FIG. 4 are as shown in FIG. 5. The curves, (a), (b), (c) or (d) of FIG. 5 are obtained depending on the inputs at the base of each transistor. When all the three inputs are &#34;1&#34;s, the curve (a) corresponding to the highest peak current is obtained. The curves with lower peak currents (b), (c), and (d) are obtained as the number of logical &#34;1&#34;s at the inputs reduce. The load resistance R c   L  in FIG. 4 is selected in such a manner that, when there are two or more logical &#34;1&#34;s at the inputs, i.e., when the carry condition is satisfied, the current through R c   L  is large, and the operating point is at the intersection of LOAD LINE L and curve (a) (when all the inputs to the devices are logic &#34;1&#34;), or between LOAD LINE and curve (b) (when two of the three inputs are logic &#34;1&#34;),in FIG. 5, and the output at node A of FIG. 5 (which is the voltage corresponding to the operating point on the X axis of FIG. 5) is at a lower potential V 0  (logical &#34;0&#34;). On the other hand, when the carry condition is not satisfied, the operating point is at the intersection of the LOAD LINE L and curve (c) or between LOAD LINE L and curve (d), (depending on whether the number of logic &#34;1&#34;s at the inputs are one or none respectively) and the output at node A is at a higher potential V 1  (logical &#34;1&#34;). Hence when a carry condition is satisfied, the potential at node A corresponds to logic &#34;0&#34;, and when the carry condition is not satisfied, node A corresponds to logic &#34;1&#34;. Thus a complement of carry is obtained at node A. T 4  and T 5  in FIG. 4 are for inverting the logic at A. 
     By selecting appropriate R c   L  in FIG. 4, LOAD LINEs L1 or L2 can be obtained as indicated in FIG. 5. The load line L1 selects the operating point at node A of FIG. 4 so that the voltage at node A corresponds to V 0  logic &#34;0&#34; only when all the three inputs are logic &#34;1&#34; (NAND operation). The load line L 2  selects the operating point at node A so that the voltage at A corresponds to V 1  logic &#34;1&#34; only when all the inputs are &#34;0&#34;s (NOR operation). FIG. 25 shows the output at node A for different input combinations, for NAND and NO logic. 
     By observing FIG. 5, it is found that the intersection points of the load line L with I-V curve (a) and I-V curve (b) are clustered together corresponding to the voltage V 0  and the intersection points of the load line L and I-V curve (c) and I-V curve (d) are clustered together corresponding to V 1 . Similarly, the intersection point of the load line L 1  with the I-V curve (a) corresponds to V 0  while the intersection of L 1  with I-V curves (b), (c) and (d) are clustered together corresponding to voltage V 1 . The intersection points of L2 with I-V curve (a),(b) and (c) are clustered together corresponding to voltage V 0 , while the intersection of L2 with I-V curve (d) corresponds to voltage V 1 . The load lines L, L 1  and L 2  thus differentiate the two logic levels at the output. By setting different load lines, the same structure can generate different logical outputs. The same principle applies to field effect transistors, bipolar junction transistors and to their variations exhibiting negative resistance. 
     To obtain the sum, five transistors with NDR are connected as in FIG. 6. The inputs of two of the transistors are connected to the complement of the carry out of the same stage, and each of the other input is connected to x i , y i  and c i-l  respectively. As illustrated in FIG. 26, the sum bit is logic &#34;1&#34; when three of the five inputs are logic &#34;1&#34;. FIG. 7 shows the I-V characteristics of the combination of the five input transistors. The load resistance R s   L  of FIG. 6 is so chosen so as to obtain the load line as in FIG. 7. When there are three &#34;1&#34;s at the input, the condition for sum is satisfied, and the operating point is at Q 1 . Q 1  corresponds to a lower potential, V OL  (logic &#34;0&#34;). Thus when condition for generation of sum is satisfied, logic &#34;0&#34; is obtained at node SB of FIG. 6. When condition for sum is not satisfied, the operating point corresponds to a voltage V OH  (logic &#34;1&#34;). Hence a complement of sum is obtained at node SB of FIG. 6. T 6  and T 7  in FIG. 6 are for inverting the logic at node SB as explained in the next paragraph. The sum is then obtained at the output. 
     Operation as an invertor with two NDR transistors can be achieved as shown in FIG. 8. The base of one of the NDR transistor T 1 , is connected to the input, and the base of the other transistor T 2  is connected permanently high. Curve (a), (b) in FIG. 9 is obtained depending on whether the input at the base of T 1  is logic &#34;1&#34; or &#34;0&#34; respectively. The load line ,of FIG. 9 is obtained by suitably selecting the load resistance R inv  of FIG. 8. When the input to T 1  is &#34;1&#34;, the I-V characteristics are given by curve (a) of FIG. 9. The operating point will be at Q a , and the current I c  is large. As a result, the output voltage (which is corresponding point on X axis in FIG. 9) is low, logic &#34;0&#34;. On the other hand, when the input to T 1  is &#34;0&#34;, the I-V characteristics are given by curve (b). The operating point is shifted to Q B , the current is small and the output voltage is high, logic &#34;1&#34;. 
     As mentioned above, the resonant tunneling transistor is one of the device which has negative differential resistance (NDR). The operation of the resonant tunneling transistor is based on the resonant tunneling of electrons through quantum wells between energy barriers of energy. 
     FIG. 10 shows the double barrier structure of the resonant tunneling transistor that is used as a model in FIG. 11 through FIG. 17 which will be discussed hereinafter. The total barrier height in this model is 0.28 eV. Because of this, the voltage levels in this design are low. A barrier height around 1 eV is achievable. As a result the voltage levels will increase to more favorable values, which will both improve noise margins and make the operation less critically dependent on the circuit and device parameters. 
     The double barrier structure could be incorporated in one of the terminals of any three terminal device to obtain resonant tunneling. The experimental results (I-V characteristics) obtained by incorporating the double barrier tunnel structure with a vertical field effect transistor (VFET), a planar metal semiconductor FET (MESFET), and other transistors based on resonant tunneling are similar to the ones illustrated in FIGS. 5,7,9,11,13 and 15 and discussed above. The voltage location and peak to valley ratio is controlled with the voltage at the control terminal. Similar characteristics have also been obtained for resonant tunneling hot electron transistors (RTHET). Thus, the same method of obtaining the carry out in a single stage delay also holds for the transistors which have double barrier structures incorporated. 
     The I e  -V be  and I e  -V ce  characteristics of resonant tunneling transistors can be used to generate logic outputs. By suitably choosing the parameters of the resonant tunneling transistor, it is shown that carry out, AND and OR logic can be generated in one stage delay, and the need for inversion can be eliminated. Resonant tunneling transistors can switch in less than a picosecond so that allowing for circuit parasitic, carry generation with this circuit should be possible in 3-5 ps. Even with a ripple carry, a 64 bit adder would then have a delay of 200-300 ps. In contrast, an ECL design of eight 8-bit carry look-ahead sections would take around 3400 ps (estimated on the basis of 200 ps delay per gate, with three gate delays in the first eight bits and two gate delays in the remaining seven sections). The transistor count in the carry chain is also reduced substantially from around 2500 to 192 with a corresponding decrease in power. 
     Based on the Ie-Vbe characteristics, more advanced logic circuit can be designed. Computed values of the emitter current (I e ) versus base-emitter voltage (V be ) characteristics of a resonant tunneling transistor with the conduction band diagram as in FIG. 10 are shown in FIG. 11. Curve (a) of FIG. 11 is obtained for V 1   cb  ≈ -0.08 V (logic &#34;1&#34;) and curve (b) is for V 0   cb  ≈ -0.2 V (logic &#34;0&#34;). 
     In the present invention, the resonant tunneling transistors are connected as shown in FIG. 12(c) in which all the bases connect to ground and the output is the Veb (the voltage at the emitter with respect to the base). The input signals x i  and y i  represent the ith bit of the operands X and Y, and c in  is the input carry from the preceding (i-l)th stage. It may be noted that a stage i generates a carry only when three or two of the input bits are &#34;1&#34;. Under these conditions, the curves (a) and (b) of FIG. 13 are obtained respectively. The load resistance R c   L  in FIG. 12(c) is chosen so as to obtain the load line Lcarry in FIG. 13. Thus, when a carry condition is satisfied, the operating point is Q 1  (when three inputs are &#34;1&#34;s) with three transistors conducting, or Q 2  (when two inputs are &#34;1&#34;s) with two transistors conducting. Q 1  and Q 2  represent the potential at node A in FIG. 12(c). The voltage corresponding to Q 1  and Q 2  is 0.075V (approximately), from FIG. 13. The potential at node A is V eb , from FIG. 12(c). From FIG. 13, V be  corresponding to Q 1  and Q 2  is 0.075V (approximately). Hence potential at node A is V eb  =-V be  =-0.75V=V cb   1  (logic &#34;1&#34; for the input to next stage, because the node A is connected to collector of next stage). 
     On the other hand, when the condition for carry is not satisfied, the operating point is at Q 3  (one input is logic &#34;1&#34;) or Q 4  (no inputs are logic &#34;1&#34;). The load current is smaller, and the operating points Q 3  and Q 4  correspond to the potential V be  =0.22V (approximately). From FIG. 12(c), the potential at node A is V e  b = -V be  = -0.22V =V 0   cb  (corresponding to logic &#34;0&#34; for the input to next stage) Thus an inversion of the output is not needed when the circuits are cascaded since the uninverted c out  is already produced at point A. The carry for the next stage is thus generated in one transistor delay. 
     When the three inputs (x i , y i , or c in ) in FIG. 12(c) are logic &#34;1&#34;, the AND logic output must be &#34;1&#34;, and the I-V characteristics corresponding to curve (a) of FIG. 13 is obtained. The load line &#34;L and  &#34; is so chosen so as to obtain the operating point P1 when all the inputs are logic&#34;1&#34;. Similarly when one or more of the inputs is logic&#34;0&#34;, the operating point is on curve (b), (c) or (d) respectively. The voltage V be  corresponding to P1 is approximately 0.08V. Hence the &#34;C out  &#34; in FIG. 12(c) corresponds to V eb  = -0.08V. This corresponds to logic &#34;1&#34;. The voltage corresponding to the operating points clustered together on curves (b), (c) or (d) is approximately 0.22V. Hence the voltage at &#34;Cout&#34; is -0.22V corresponding to logic&#34;0&#34;. Hence the AND logic operation is performed in a one device delay. 
     Similarly, only when all the inputs at x i , y i  and c in  are logic &#34;0&#34;, the OR logic is &#34;0&#34;. The load line &#34;Lor&#34; in FIG. 13 is chosen to obtain the operating point R1 on curve (d) when all the inputs are logic &#34;0&#34;. When one or more of the inputs is a logic&#34;1&#34;, the operating point is on curve (c), (b) or (a) respectively. The voltage V be  corresponding to R 1  is approximately 0.2V. Hence &#34;C out  &#34; in FIG. 12(c) corresponds to V eb  = -0.2V. This corresponds to logic&#34;0&#34;. The voltage V be  corresponding to operating points on curves (a),(b) or (c) is approximately 0.08V. Hence the voltage at &#34;Cout&#34; is -0.08V corresponding to logic&#34;1&#34;. Hence the OR logic is obtained in a one device delay. 
     FIG. 14 is the circuit diagram to generate the sum bit. FIG. 15 shows the I-V characteristics simulated for the schematic of FIG. 14. The five inputs in FIG. 14 include the two operand bits x i  and y i , the carry from the previous stage C i-l , and two complements of carry of the same stage. When three of these five inputs are either logic &#34;1&#34; or logic &#34;0&#34;, the sum bit generated will be logic&#34;1&#34; or logic&#34;0&#34; respectively. FIG. 26 illustrates FIG. 26 the condition when the sum bit will be generated. The load line &#34;L sum  &#34; in FIG. 15 is so chosen so as to obtain the operating point at S1 when three of the inputs are logic&#34;1&#34;. When three or more of the inputs are logic&#34;0&#34;, the operating point is on curve (b), (c) or (d) respectively. The voltage V be  corresponding to S1 is approximately 0.07V. Hence the &#34;Sum&#34; in FIG. 14 corresponds to V eb  =-0.07V. This corresponds to logic&#34;1&#34;. The voltage V be  corresponding to operating points on curve (b), (c) or (d) is approximately 0.22V. Hence the voltage 1 at &#34;Sum&#34; in FIG. 14 is -0.22V corresponding to logic&#34;0&#34;. Hence the sum bit is generated. 
     FIG. 16 shows how a carry generating unit of FIG. 4(b) can be connected with a sum generating unit of FIG. 6(b) or a carry generating unit of FIG. 12(c) can be connected to a sum generating unit of FIG. 14 to form a 64-bit ripple-carry adder. 
     I e  -V ce  characteristics of a resonant tunneling transistor are shown in FIG. 18 for various values of V cb . The peak shifts towards the right as V cb  increases. When all the three inputs are logic &#34;0&#34;, curve (a) in FIG. 18 is obtained; when two inputs are logic&#34;0&#34; and one input is logic&#34;1&#34;, curve (b) is obtained; when one input is logic&#34;0&#34; and two inputs are logic&#34;1&#34;, curve (c) is obtained; when all the three inputs are logic&#34;1&#34;, curve (d) is obtained. 
     When a resonant tunneling transistor is connected as shown in FIG. 17, with inputs connected to the base of the transistor, R L  in FIG. 17 can be chosen to obtain the load lines L NOR , L c , L NAND  of FIG. 18, corresponding to NOR, Complement Carry, and NAND logic at the output. The complement of carry obtained, may then be inverted by using the inverting principle illustrated in FIG. 8 and FIG. 9 and described previously, to obtain carry out. 
     The FETs can also be used to design circuits under the same principle. Three n channel FETs and one p channel FET are connected as shown in FIG. 19(a). The W/L ratios of these transistors can be suitably adjusted to obtain the characteristics as in FIG. 19(b). 
     The curves (a), (b), (c) and (d) in FIG. 19(b) are obtained according to as the number of logic &#34;1&#34; s at the inputs x i , y i , c in  are three, two, one and nil respectively. The p channel transistor functions as an active load. 
     When the number of logic &#34;1&#34; s at the inputs are two or three, the carry condition is satisfied. The operating point is at C 1  or C 2  in FIG. 19(b), and the potential at node P in FIG. 19(a) is at low potential corresponding to V OL  (logic 0). Thus, a complement of carry out is generated at node P in one transistor delay. The output at node P is then inverted to obtain the carry out. By suitably adjusting the p channel FET parameters, the I-V characteristics corresponding to &#34;PMOS(nand)&#34;, and &#34;PMOS(nor)&#34; can be obtained to generate nand and nor logic respectively. 
     When all the inputs in FIG. 19(a) are logic&#34;1&#34;, the I-V characteristics corresponding to curve (a) of FIG. 19(b) are obtained, and the operating point is at N1, corresponding to the voltage V OL , logic&#34;0&#34;. When one or more of the inputs are logic &#34;0&#34;, the operating point will be on the curve (b), (c) or (d) of FIG. 19(b) respectively, clustered around the voltage V OH , corresponding to logic&#34;1&#34;. Hence the NAND logic is achieved in a single device delay. 
     When all the inputs in FIG. 19(a) are logic&#34;0&#34;, the I-V characteristics corresponding to curve (d) of FIG. 19(b) are obtained, and the operating point is at M 1 , corresponding to the voltage V OH , logic&#34;1&#34;. When one or more of the inputs are logic &#34;1&#34;, the operating point will be on the curve (c), (b) or (a) of FIG. 19(b) respectively, clustered around the voltage V OL , corresponding to logic&#34;0&#34;. Hence the NOR logic is achieved in a single device delay. 
     Three p channel FETs and one n channel FET are connected as shown in FIG. 20(a). The W/L ratios of these transistors can be suitably adjusted to obtain the characteristics as in FIG. 20(b). 
     The curves (a), (b), (c) and (d) in FIG. 20(b) are obtained according to as the number of logic &#34;1&#34; s at the inputs x i , y i , c in  are three, two, one and nil respectively. The n channel transistor functions as an active load. 
     When the number of logic &#34;1&#34;s at the inputs are two or three, the carry condition is satisfied, and the operating point is at the intersection of the load line &#34;NMOS(carry)&#34; and curve(b) or curve(a) respectively, at C 1  or C 2  in FIG. 20(b), and the potential at node P in FIG. 20(a) is at high potential corresponding to V OH  (logic 1). Thus, a carry out is generated at node P in one transistor delay. By suitably adjusting the n channel FET parameters, the I-V characteristics corresponding to &#34;NMOS(AND)&#34;, and &#34;NMOS(OR)&#34; can be obtained to generate AND and OR logic respectively. 
     When all the inputs in FIG. 20(a) are logic&#34;1&#34;, the I-V characteristics corresponding to curve (a) of FIG. 20(b) are obtained, and the operating point is at A1, corresponding to the voltage V OH , logic&#34;1&#34;. When one or more of the inputs are logic &#34;0&#34;, the operating point will be on the curve (b), (c) or (d) of FIG. 20(b) respectively, clustered around the voltage V OL , corresponding to logic&#34;0&#34;. Hence the AND logic is achieved in a single device delay. 
     When all the inputs in FIG. 20(a) are logic&#34;0&#34;, the I-V characteristics corresponding to curve (d) of FIG. 20(b) are obtained, and the operating point is at 01, corresponding to the voltage V OL , logic&#34;0&#34;. When one or more of the inputs are logic &#34;1&#34;, the operating point will be on the curve (c), (b) or (a) of FIG. 20(b) respectively, clustered around the voltage V OH , corresponding to logic&#34;1&#34;. Hence the OR logic is achieved in a single device delay. 
     When four n channel FETs are connected as shown in FIG. 21(a). The W/L ratios of these transistors can be suitably adjusted to obtain the characteristics as in FIG. 21(b). The configuration of FIG. 21(a) is called the enhancement-depletion technology. The n channel field effect depletion transistor replaces the p channel FET of FIG. 19(a). The n channel FET functions as a depletion load. The technique of generation of complement of carry, NAND and NOR is similar to that explained earlier with the p channel FET as a load device. 
     FIG. 22(a) shows the circuit diagram to generate the complement of sum bit. Five n channel FETs and one p channel FET are connected as shown in FIG. 22(a). The five inputs at the gate of the n channel FETs include the two operand bits x i  and y i , the carry from the previous stage C i-l , and two complements of carry of the same stage. When three of these five inputs are either logic &#34;1&#34; or logic &#34;0&#34;, the sum bit generated will be logic&#34;1&#34; or logic&#34;0&#34; respectively. FIG. 26 illustrates the condition when the sum bit will be generated. The load line &#34;Lsum&#34; in FIG. 22(b) is so chosen so as to obtain the operating point at NS 1  in FIG. 22(b) when three of the inputs are logic&#34;1&#34;. When three or more of the inputs are logic&#34;0&#34;, the operating point is on curve (b), (c) or (d) of FIG. 22(b) respectively. The operating point NS 1  corresponds to logic&#34;0&#34;. The operating points on curve (b), (c) or (d) are clustered around logic&#34;1&#34;. Hence the complement of sum bit is generated. 
     The complement of sum bit is also generated by replacing the p channel FET in FIG. 22(a) with a n channel depletion transistor as shown in FIG. 23(a) to obtain the characteristics as in FIG. 23(b). 
     FIG. 24(a) shows the circuit diagram to generate the sum bit. Five p channel FETs and one n channel FET are connected as shown in FIG. 24(a). The five inputs at the gate of the p channel FETs include the two operand bits x i  and y i , the carry from the previous stage C i-l , and two complements of carry of the same stage. When three of these five inputs are either logic &#34;1&#34; or logic &#34;0&#34;, the sum bit generated will be logic&#34;1&#34; or logic&#34;0&#34; respectively. FIG. 26 illustrates the condition when the sum bit will be generated. The load line &#34;Lsum&#34; in FIG. 24(b) is so chosen so as to obtain the operating point at S1 in FIG. 24(b) when three of the inputs are logic&#34;1&#34;. When three or more of the inputs are logic&#34;0&#34;, the operating point is on curve (b), (c) or (d) of FIG. 24(b) respectively. The operating point S1 corresponds to logic&#34;1&#34;. The operating points on curve (b), (c) or (d) are clustered around logic&#34;0&#34;. Hence the sum bit is generated. 
     The FETs in FIGS. 19 through 24 can be replaced by bipolar transistors, and the active loads can be replaced by resistances to obtain similar results as with FETs. 
     The present invention has its unique advantage. In the future, the devices will be microminiaturized. The demand for microminiaturization will make the technology lean towards quantum devices which have negative differential resistance (NDR). The present invention uses the NDR characteristic of these devices for digital applications. 
     The characteristics of resonant tunneling transistors can be exploited to generate the carry for an adder in as few as three transistors. Other logic functions can also be realized. Because of the fast switching speed of these transistors, a carry can be generated in possibly as little as 3-5 ps. Using a ripple-carry, a 64 bit adder would then have a delay of 200-300 ps, which is an order of magnitude below that of an ECL design of eight 8-bit carry look-ahead sections. The transistor count is also an order of magnitude smaller and consequently the power would be considersections. The transistor count is also an order of magnitude smaller and consequently the power would be considerably decreased. The designs based on conventional devices are equally promising for reducing the complexity of the adders and multipliers, and increasing the computational speed.