Abstract:
Provided are a method, system and program for using multiple data structures to manage data in cache. A plurality of data structures each have entries identifying data from a first computer readable medium added to a second computer readable medium. A request is received for data in the first computer readable medium. A determination is made as to whether there is an entry for the requested data in one of the data structures. The requested data is retrieved from the first computer readable medium to store in the second computer readable medium in response to determining that there is no entry for the requested data in one of the data structures. One of the data structures is selected in response to determining that there is no entry for the requested data in one of the data structures and an entry for the retrieved data is added to the selected data structure.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a method, system, and program using multiple data structures to manage data in cache. 
         [0003]    2. Description of the Related Art 
         [0004]    A cache management system stores data maintained in storage device in a faster access media, such as a memory device, so that requests for the data from the storage can be serviced faster from the faster access cache memory. A cache management system may maintain a linked list having one entry for each data unit staged into cache from the storage. In the commonly used Least Recently Used (LRU) cache technique, if data in the cache is accessed, i.e., a cache “hit”, then the entry in the LRU list for the accessed data is moved to a Most Recently Used (MRU) end of the list. If the requested data is not in the cache, i.e., a cache miss, then the data in the cache whose entry is at the LRU end of the list may be removed (or destaged back to storage) and an entry for the new data staged into cache is added to the MRU end of the LRU list. With this LRU cache technique, data that is more frequently accessed is likely to remain in cache, while data less frequently accessed will more likely be removed from the LRU end of the list to make room in cache for newly accessed data. 
         [0005]    In an asynchronous computing environment where multiple threads or different processors in a multi-processor environment are accessing data from the same cache, the MRU entry is protected by a lock to serialize access to the MRU entry. This means that one or more threads must wait for the thread holding the lock on the MRU entry to complete their cache hit or miss operation. In multi-threaded environments there is a significant amount of contention for this lock because all cache hits and cache misses require access to this lock. Such contention is considered undesirable for high performance and high throughput environments such as virtual memory, databases, file systems, and storage controllers. 
         [0006]      FIG. 1  illustrates a clock data structure (or “clock”)  2  known in the prior art to manage data cached from a storage device. The clock  2  comprises a circular buffer. The clock includes a clock hand  4  that points between a head entry  6  and tail entry  8  of the clock  2 . Data from storage is added to the head entry  6 . The clock algorithm maintains a “page reference bit” for each clock  2  entry, or page. When data is first brought into the cache from storage, the page reference bit for the entry for that cached data is set to zero. When data in cache is accessed, the page reference bit for the accessed data is set to one. 
         [0007]    To replace data in cache with newly accessed data from storage, if the head entry  8  at the clock hand  4  has a page reference bit of zero, then the data corresponding to the head entry  8  is destaged from cache, and information on the new page is added to the head entry  6 . If the page reference bit for the current head entry  8  is one, then that page reference bit is reset to zero and the clock hand  4  moves forward through the clock  2  until finding a head entry  8  having a page reference bit of zero to replace. In virtual memory applications, the page reference bit can be changed by the hardware. 
         [0008]    One advantage of the clock cache technique is that there is no need to move a page to an MRU position for a cache hit such as the case with the LRU cache technique, which requires a lock and serialization to move the entry in the LRU list for accessed data to the MRU position. Furthermore, the hit ratio of the clock cache technique is usually comparable to that of the LRU cache method. For this reason, variants of the clock cache technique are used in many operating systems and application programs. However, a lock is still required for a cache miss when adding a page to the head entry  8  of the clock structure. Thus, both the LRU and clock cache techniques require lock contention when replacing data in cache. 
         [0009]    For these reasons, there is a need in the art to provide techniques for managing data in a cache. 
       SUMMARY 
       [0010]    Provided are a method, system and program for using multiple data structures to manage data in cache. A plurality of data structures each have entries identifying data from a first computer readable medium added to a second computer readable medium. A request is received for data in the first computer readable medium. A determination is made as to whether there is an entry for the requested data in one of the data structures. The requested data is retrieved from the first computer readable medium to store in the second computer readable medium in response to determining that there is no entry for the requested data in one of the data structures. One of the data structures is selected in response to determining that there is no entry for the requested data in one of the data structures and an entry for the retrieved data is added to the selected data structure. 
         [0011]    In a further embodiment, selecting one of the data structures comprises randomly selecting one of the data structures. 
         [0012]    In a further embodiment, a determination is made as whether the second computer readable medium has available space to store the retrieved requested data in response to determining that there is no entry for the requested data in one of the data structures. One entry is selected from one of the data structures in response to determining that the second computer readable medium does not have available space. The data for the selected entry is destaged from the second computer readable medium. 
         [0013]    In a further embodiment, selecting one entry from one of the data structures in response to determining that the second computer readable medium does not have available space comprises determining one of the data structures having an oldest entry, wherein the selected entry comprises the oldest entry in the determined data structure. 
         [0014]    In a further embodiment, selecting one entry from one of the data structures in response to determining that the second computer readable medium does not have available space comprises selecting a random subset of the data structures and selecting one data structure from the selected random subset whose oldest entry is no more recent than an oldest entry in any other data structure in the selected subset. 
         [0015]    In a further embodiment, the data structures comprise Least Recently Used (LRU) lists and wherein adding the entry for the retrieved data comprises adding the entry to a Most Recently Used (MRU) end of the selected LRU list. 
         [0016]    In a further embodiment, the data structures comprise clocks, wherein each clock has a head and tail entries adjacent to each other in the list, and wherein adding the entry for the retrieved data comprises adding the entry to the head entry of the selected clock. 
         [0017]    In a further embodiment, the entries in the clocks indicate whether the entry has been accessed. A determination is made as to whether the second computer readable medium has available space to store the retrieved requested data in response to determining that there is no entry for the requested data in one of the clocks. One of the clocks is selected and a determination is made of one entry in the clock that is indicated as having not been accessed. The data for the determined entry is destaged from the second computer readable medium. 
         [0018]    In a further embodiment, a plurality of data structures each have entries identifying data from a first computer readable medium added to a second computer readable medium. A request is received for data in the first computer readable medium and a determination is made as to whether there is an entry for the requested data in one of the data structures. The requested data is accessed from the second computer readable medium for the data request in response to determining that there is one entry for the requested data in one of the data structures. One of the data structures is selected in response to determining that there is one entry for the requested data in one of the data structures and the determined entry for the requested data is moved to the data structure selected in response to determining that there is one entry for the requested data. 
         [0019]    In a further embodiment, the data structure is selected randomly in response to determining that there is one entry for the requested data in one of the data structures. 
         [0020]    In a further embodiment, each data structure is a member of a set of data structure comprising one of: Least Recently Used (LRU) lists and clock data structures. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0021]      FIG. 1  illustrates a prior art clock data structure used for cache management. 
           [0022]      FIG. 2  illustrates an embodiment of a computing environment. 
           [0023]      FIG. 3  illustrates an embodiment of an index entry used to manage cache in the computing environment of  FIG. 2 . 
           [0024]      FIG. 4  illustrates an embodiment of operations to manage cache using the data structures of  FIGS. 2 and 3 . 
           [0025]      FIG. 5  illustrates an embodiment of components in a memory used to manage a cache. 
           [0026]      FIG. 6  illustrates an embodiment of an index entry used to manage cache with the memory of  FIG. 5 . 
           [0027]      FIG. 7  illustrates an embodiment of operations to manage cache using the data structures of  FIGS. 5 and 6   
       
    
    
     DETAILED DESCRIPTION 
       [0028]      FIG. 2  illustrates an embodiment of a computing environment. A system  12  includes one or more processors  14   a ,  14   b  . . .  14   n , where each processor  14   a ,  14   b  . . .  14   n  submits Input/Output (I/O) requests directed to storage locations in a storage  16 . A cache manager  18  handles the I/O requests and caches data requested by the processors  14   a ,  14   b  . . .  14   n  in one of multiple Least Recently Used (LRU) lists  20   a ,  20   b  . . .  20   n  stored in a memory  22 . The cache manager  18  uses the LRU lists  20   a ,  20   b  . . .  20   n  to manage data from the storage  16  cached in the memory  22  to determine when to stage and destage data form the storage  16  to optimize cache hits and minimize cache misses. Each LRU list  20   a ,  20   b  . . .  20   n  includes a Most Recently Used (MRU) end  24   a ,  24   b  . . .  24   n  and LRU end  26   a ,  26   b  . . .  26   n . Data accessed from the storage  16  identified in the LRU lists  20   a ,  20   b  . . .  20   n  is cached in the memory  22 . 
         [0029]    The cache manager  18  further maintains a cache index  28  that has information on data from the storage  6  maintained in the cache of the memory  22 . The cache index  28  indicates whether data from a particular address or location in the storage  16  is identified in an entry in one of the LRU lists  20   a ,  20   b  . . .  20   n . A storage address or location may comprise a track, block, page, or any other segment of data in the storage  16 . 
         [0030]    The storage  16  may comprise one or more storage devices, such as one or more disk drives, an array of storage devices, such as a Just a Bunch of Disks (JBOD), Direct Access Storage Device (DASD), Redundant Array of Independent Disks (RAID) array, virtualization device, tape storage, flash memory, etc. The memory  22  may comprise one or more memory devices that has higher throughput and faster access than the storage  16 . In alternative embodiments, the memory  22  and storage  16  may comprise any suitable computer readable media known in the art, such that one computer readable medium functions as a fast access cache to another computer readable medium to which the I/O requests are directed. The processors  14   a ,  14   b  . . .  14   n  may comprise separate microprocessor devices or separate processing cores implemented on one or more multi-core microprocessor devices. The cache manager  18  may be implemented as a computer program executed by one or more of the processors  14   a ,  14   b  . . .  14   n  or implemented in the memory  22  hardware. 
         [0031]    In one embodiment, the system  12  may comprise a storage controller receiving read and write requests to the storage  16  from multiple connected hosts. 
         [0032]      FIG. 3  illustrates an embodiment of a cache index entry  30  in the cache index  28 , which indicates a storage location  32 , such as a storage address; an LRU list  34  identifying the LRU list  10   a ,  10   b  . . .  10   n  having the entry for the cached storage location  32 ; and the entry  36  position in the indicated LRU list  34  for the cached storage location  32 . 
         [0033]    The cache index  28  may comprise a hash table whose entries are indexed based on a hash of the storage location  32 . Alternatively, the cache index  28  may be implemented in suitable index type data structures other than a hash table known in the art. 
         [0034]      FIG. 4  illustrates an embodiment of operations performed by the cache manager  18  to manage the caching of data from the storage  16  in the memory  22 . Upon receiving (at block  100 ) a request, e.g., read or write request, to access data in the storage  16 , the cache manager  18  processes (at block  102 ) the cache index  28  to determine whether the requested storage address is in one of the LRU lists  20   a ,  20   b  . . .  20   n . The storage location of data that is cached may comprise a block, track, page or other unit or segment of storage. If (at block  104 ) there is a cache index entry  30  ( FIG. 3 ) for the requested storage address, then the requested data is in cache, i.e., a “cache hit”. In such case, the cache manager  18  determines (at block  106 ) from the cache index  28  the LRU list  20   a ,  20   b  . . .  20   n  from field  34  and entry  36  in the list for the requested data. In one embodiment, the cache manager  18  may move the entry for the accessed data to the MRU end  24   a ,  24   b  . . .  24   n  of the current LRU list  20   a ,  20   b  . . .  20   n  in which the entry is included. In alternative embodiment, the cache manager  18  may select (at block  108 ), e.g., randomly select, one of the LRU lists  20   a ,  20   b  . . .  20   n  (which may or may not include the LRU list already including the determined entry) and move (at block  110 ) the determined entry for the requested data to the MRU end  24   a ,  24   b  . . .  24   n  of the selected LRU list  20   a ,  20   b  . . .  20   n.    
         [0035]    If (at block  104 ) there is no entry in the cache index  28  for the requested storage address, then the requested data is not in cache, i.e., a “cache miss”. In such case, if (at block  112 ) the cache memory  22  is not full, i.e., has space available for the requested data, then the cache manager  18  stages (at block  114 ) the requested data into the cache memory  22 . To create an LRU list entry for the data staged into the cache memory  22 , the cache manager  18  selects, e.g., randomly, (at block  116 ) one of the LRU lists  20   a ,  20   b  . . .  20   n  and adds (at block  118 ) the entry for the staged data to the MRU end  24   a ,  24   b  . . .  24   n  of the selected LRU list  20   a ,  20   b  . . .  20   n . An entry  30  ( FIG. 3 ) is also added (at block  120 ) to the cache index  28  including the storage address of the requested data and selected LRU list  20   a ,  20   b  . . .  20   n  to which the entry  30  is added. If (at block  112 ) the cache is full, i.e., does not have space available for the requested data, then data needs to be destaged. To destage data, the cache manager  18  selects (at block  124 ) one of the lists by processing a randomly selected subset of the lists to determine the list of the randomly selected subset having the oldest LRU  26   a ,  26   b  . . .  26   n  entry. The oldest entry can be determined by maintaining with each cache entry a timestamp that stores the time of last access for that entry. For instance, if there are n LRU lists, then the subset of randomly selected lists may comprise m lists. In one embodiment, the subset of lists, or m, may be two. The cache manager  18  then destages (at block  126 ) the data for the LRU entry  26   a  . . .  26   n  from the selected LRU list  20   a ,  20   b  . . .  20   n . Destaging the data removes the data from the memory  22  and applies any updates to the data to the storage  16 . After destaging the data, control proceeds to block  114 , to stage in the requested data. From block  110  or  120 , control proceeds to block  128  to return the requested data to the requesting processor  14   a ,  14   b  . . .  14   n.    
         [0036]    By randomly distributing entries among LRU lists, the described embodiments seek to increase the likelihood that concurrently accessed storage locations have entries in different LRU lists to avoid lock contention by the processors  14   a ,  14   b  . . .  14   n  requesting the data. For instance, if there are two concurrent requests to storage locations whose LRU entries are on different LRU lists, then there would be no delays due to lock contention and serialization that result when two requests require access to the MRU entry in the same LRU list. However, lock contention may still occur if two concurrent requests are for data whose entries are on the same list. Nonetheless, the described embodiments substantially reduce the likelihood of lock contention by randomly distributing most recently accessed entries across multiple LRU lists having separate locks for their MRU and LRU ends. 
         [0037]      FIG. 5  is an alternative embodiment, where instead of using LRU lists  20   a ,  20   b  . . .  20   n  ( FIG. 2 ), the cache manager  18  maintains clock data structures (or “clocks”)  150   a ,  150   b  . . .  150   n  in memory  152  to manage data from the storage  16  in the cache memory  152 . Each clock  150   a ,  150   b  . . .  150   n  includes a clock hand  154   a ,  154   b  . . .  154   n  providing a pointer to a location in the clock  150   a ,  150   b  . . .  150   n  between a tail entry  156   a ,  156   b  . . .  156   n  and ahead entry  158   a ,  158   b  . . .  158   n  of the clock  150   a ,  150   b  . . .  150   n . A cache index  160  provides an index of storage addresses to entries in one of the clocks. The cache index  160  may comprise a hash table or other suitable index data structure. 
         [0038]      FIG. 6  is an embodiment of an entry  170  in the cache index  160 , which indicates a storage location  172 , such as a storage address; a clock  174  identifying the clock  150   a ,  150   b  . . .  150   n  having an entry for the storage location  172 ; and the entry  176  in the indicated clock  174  for the storage location  172 . 
         [0039]      FIG. 7  illustrates an embodiment of operations performed by the cache manager  18  using clocks  150   a ,  150   b  . . .  150   n  to manage the cache memory  152 . Upon receiving a request (at block  200 ) for a storage address, the cache manager  18  processes (at block  202 ) the cache index  160  to determine whether the requested data is in one of the clocks  150   a ,  150   b  . . .  150   n . If (at block  204 ) there is a cache index entry  160  for the requested storage address, i.e., a “cache hit”, then the cache manager  18  determines (at block  206 ) from the cache index  160  the clock  150   a ,  150   b  . . .  150   n  and entry  176  ( FIG. 6 ) in the clock  150   a ,  150   b  . . .  150   n  for the requested data. The cache manager  18  then sets (at block  208 ) the entry bit for the determined entry to indicate the entry has been accessed (e.g., setting the page reference bit to “1”) and returns (at block  210 ) the requested data. If (at block  204 ) the cache index  160  does not include an entry for the requested storage address, i.e., a “cache miss”, and if (at block  212 ) the cache memory  152  is not full, i.e., does have space available for the requested data, then the cache manager  18  stages (at block  214 ) the requested data into the cache memory  152  and selects (at block  216 ) one of the clocks  150   a ,  150   b  . . .  150   n , which may be selected randomly. An entry  170  ( FIG. 6 ) for the staged data is added (at block  218 ) to the head entry  158   a ,  158   b  . . .  158   n  of the selected clock  150   a ,  150   b  . . .  150   n  and an entry is added (at block  220 ) to the cache index  170 . This cache index entry  170  includes the storage address  172  of the requested data, the selected clock  174  and the entry in the selected clock for the data staged into the memory  152 . From block  220 , control proceeds to block  210  to return the data. 
         [0040]    If (at block  212 ) the memory cache  152  is full, i.e., does not have space available for the requested data, then the cache manager  18  may select (at block  222 ) one of the clocks  150   a ,  150   b  . . .  150   n  by randomly selecting a subset of the clocks  150   a ,  150   b  . . .  150   n  to determine the largest clock, i.e., clock with the most entries  170 , of the randomly selected subset from which to remove an entry, which is the clock having the most entries. For each clock, a counter indicating the number of entries in it is maintained. The counter can be used to determine the largest clock, i.e., the one containing the most entries, amongst a set of clocks. Alternatively, the cache manager  18  may randomly select one of the clocks  150   a ,  150   b  . . .  150   n  to be updated with the entry for the data being staged into the memory  152  for the cache miss. 
         [0041]    If (at block  224 ) the head entry  158   a ,  158   b  . . .  158   n  at the clock hand  154   a ,  154   b  . . .  154   n  of the selected clock set  150   a ,  150   b  . . .  150   n  is indicated as having been accessed, i.e., the page reference bit for that entry is set to “1”, then the cache manager  18  sets (at block  226 ) the bit for the entry  170  to indicate that the storage address has not been accessed, e.g., “0”, and moves the clock hand  154   a ,  154   b  . . .  154   n  one entry forward so that the previous head entry  158   a ,  158   b  . . .  158   n  is now the tail entry  156   a ,  156   b  . . .  156   n  of the new clock hand position. After resetting the bit for the entry to indicate “not accessed”, e.g., “0”, (at block  226 ) control proceeds back to block  224  so that the clock hand  154   a ,  54   b  . . .  154   n  continues moving forward until reaching a head entry  158   a ,  158   b  . . .  158   n  whose access bit indicates the entry has not been accessed recently, e.g., the page reference bit is zero. 
         [0042]    If (at block  224 ) the head entry  158   a ,  158   b  . . .  158   n  at the clock hand  154   a ,  154   b  . . .  154   n  indicates the storage address in cache has not been accessed, e.g., the page reference bit is zero, then the cache manager  18  destages (at block  228 ) the data for the head entry  156   a ,  156   b  . . .  156   n  from the cache memory  152  to storage  16  if the data has been modified. If the data has not been modified, the data may be discarded. Control then proceeds to block  214  to stage in the requested data, add an entry for the requested data to one of the clocks  150   a ,  150   b  . . .  150   n , and return the requested data. 
         [0043]    By randomly distributing entries among clock data structures, the described embodiments seek to increase the likelihood that concurrently accessed storage locations have entries in different clocks to avoid lock contention by the processors  14   a ,  14   b  . . .  14   n  when there are cache misses. For instance, if there are two concurrent requests to storage locations whose clock entries are on different clocks, then there would be no delays due to lock contention and serialization if there is a cache miss because different clocks may be separately updated for the data staged into cache for the cache miss. The described embodiments substantially reduce the likelihood of lock contention by randomly distributing most recently accessed entries across multiple clocks having separate locks. Moreover, using multiple lists improves the system transfer throughput by avoiding locking delays. 
       Additional Embodiment Details 
       [0044]    The described operations may be implemented as a method, apparatus or article of manufacture using standard programming and/or engineering techniques to produce software, firmware, hardware, or any combination thereof. The described operations may be implemented as code maintained in a “computer readable medium”, where a processor may read and execute the code from the computer readable medium. A computer readable medium may comprise media such as magnetic storage medium (e.g., hard disk drives, floppy disks, tape, etc.), optical storage (CD-ROMs, DVDs, optical disks, etc.), volatile and non-volatile memory devices (e.g., EEPROMs, ROMs, PROMs, RAMs, DRAMs, SRAMs, Flash Memory, firmware, programmable logic, etc.), etc. The code implementing the described operations may further be implemented in hardware logic (e.g., an integrated circuit chip, Programmable Gate Array (PGA), Application Specific Integrated Circuit (ASIC), etc.). Still further, the code implementing the described operations may be implemented in “transmission signals”, where transmission signals may propagate through space or through a transmission media, such as an optical fiber, copper wire, etc. The transmission signals in which the code or logic is encoded may further comprise a wireless signal, satellite transmission, radio waves, infrared signals, Bluetooth, etc. The transmission signals in which the code or logic is encoded is capable of being transmitted by a transmitting station and received by a receiving station, where the code or logic encoded in the transmission signal may be decoded and stored in hardware or a computer readable medium at the receiving and transmitting stations or devices. An “article of manufacture” comprises computer readable medium, hardware logic, and/or transmission signals in which code may be implemented. A device in which the code implementing the described embodiments of operations is encoded may comprise a computer readable medium or hardware logic. Of course, those skilled in the art will recognize that many modifications may be made to this configuration without departing from the scope of the present invention, and that the article of manufacture may comprise suitable information bearing medium known in the art. 
         [0045]    In the described embodiments, the data structures used to store the entries for the data in the cache comprised LRU lists or clocks. In alternative embodiments, additional suitable data structures may be used to store entries of information to manage the data in the cache. Moreover, in the described embodiments, the data structures used to store the entries were of the same type, e.g., LRU lists, clocks. In an alternative embodiment, the multiple data structures used to store the cache entries may be of mixed types. 
         [0046]    The terms “an embodiment”, “embodiment”, “embodiments”, “the embodiment”, “the embodiments”, “one or more embodiments”, “some embodiments”, and “one embodiment” mean “one or more (but not all) embodiments of the present invention(s)” unless expressly specified otherwise. 
         [0047]    The terms “including”, “comprising”, “having” and variations thereof mean “including but not limited to”, unless expressly specified otherwise. 
         [0048]    The enumerated listing of items does not imply that any or all of the items are mutually exclusive, unless expressly specified otherwise. 
         [0049]    The terms “a”, “an” and “the” mean “one or more”, unless expressly specified otherwise. 
         [0050]    The variables “n” and “m” when used to represent a variable number of an element may indicate any number of instances of the element, and may indicate different integer numbers when used with different elements. 
         [0051]    Devices that are in communication with each other need not be in continuous communication with each other, unless expressly specified otherwise. In addition, devices that are in communication with each other may communicate directly or indirectly through one or more intermediaries. 
         [0052]    A description of an embodiment with several components in communication with each other does not imply that all such components are required. On the contrary a variety of optional components are described to illustrate the wide variety of possible embodiments of the present invention. 
         [0053]    Further, although process steps, method steps, algorithms or the like may be described in a sequential order, such processes, methods and algorithms may be configured to work in alternate orders. In other words, any sequence or order of steps that may be described does not necessarily indicate a requirement that the steps be performed in that order. The steps of processes described herein may be performed in any order practical. Further, some steps may be performed simultaneously. 
         [0054]    When a single device or article is described herein, it will be readily apparent that more than one device/article (whether or not they cooperate) may be used in place of a single device/article. Similarly, where more than one device or article is described herein (whether or not they cooperate), it will be readily apparent that a single device/article may be used in place of the more than one device or article or a different number of devices/articles may be used instead of the shown number of devices or programs. The functionality and/or the features of a device may be alternatively embodied by one or more other devices which are not explicitly described as having such functionality/features. Thus, other embodiments of the present invention need not include the device itself. 
         [0055]    The illustrated operations of  FIGS. 4 and 7  show certain events occurring in a certain order. In alternative embodiments, certain operations may be performed in a different order, modified or removed. Moreover, steps may be added to the above described logic and still conform to the described embodiments. Further, operations described herein may occur sequentially or certain operations may be processed in parallel. Yet further, operations may be performed by a single processing unit or by distributed processing units. 
         [0056]    The foregoing description of various embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto. The above specification, examples and data provide a complete description of the manufacture and use of the composition of the invention. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention resides in the claims hereinafter appended.