Abstract:
Solid state lighting devices grown on semi-polar facets and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state light device includes a light emitting diode with an N-type gallium nitride (“GaN”) material, a P-type GaN material spaced apart from the N-type GaN material, and an indium gallium nitride (“InGaN”)/GaN multi quantum well (“MQW”) active region directly between the N-type GaN material and the P-type GaN material. At least one of the N-type GaN, InGaN/GaN MQW, and P-type GaN materials is grown a semi-polar sidewall.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a divisional of U.S. application Ser. No. 12/720,440 filed Mar. 9, 2010, now U.S. Pat. No. 8,445,890, which is incorporated herein by reference in its entirety. 
    
    
     TECHNICAL FIELD 
     The present technology is directed generally to solid state lighting (SSL) devices grown on semi-polar facets and associated methods of manufacturing. 
     BACKGROUND 
     SSL devices generally use semiconductor light emitting diodes (LEDs), organic light-emitting diodes (“OLEDs”), and/or polymer light emitting diodes (“PLEDs”) as sources of illumination rather than electrical filaments, a plasma, or a gas.  FIG. 1  is a cross-sectional diagram of a portion of a conventional indium-gallium nitride (“InGaN”) LED  10 . As shown in  FIG. 1 , the LED  10  includes a substrate  12  (e.g., silicon carbide, sapphire, gallium nitride, or silicon), an N-type gallium nitride (GaN) material  14 , an InGaN/GaN multi quantum well (MQW)  16 , and a P-type GaN material  18  on one another in series. The LED  10  also includes a first contact  20  on the P-type GaN material  18  and a second contact  22  on the N-type GaN material  14 . 
     The GaN/InGaN materials  14 ,  16 , and  18  have a wurtzite crystal formation in which hexagonal rings of gallium (or indium) are stacked on top of hexagonal rings of nitrogen atoms. According to conventional techniques, the GaN/InGaN materials  14 ,  16  and  18  are typically grown along a direction generally perpendicular to the hexagonal rings of gallium (or indium) and nitrogen atoms. As discussed in more detail later, the growth direction of the GaN/InGaN materials  14 ,  16  and  18  may negatively impact the optical efficiency of the LED  10 . Accordingly, several improvements in the optical efficiency of LEDs may be desirable. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a cross-sectional view of a portion of an LED in accordance with the prior art. 
         FIGS. 2A-2F  are schematic perspective views of various crystal planes in a GaN/InGaN material in accordance with embodiments of the technology. 
         FIG. 3A  is a cross-sectional view of a portion of an SSL device in accordance with embodiments of the technology. 
         FIG. 3B  is a top view of a portion of the SSL device in  FIG. 3A  in accordance with embodiments of the technology. 
         FIG. 3C  is a top view of a portion of the SSL device in  FIG. 3A  in accordance with additional embodiments of the technology. 
         FIGS. 4A-4E  are perspective and cross-sectional views of a portion of a microelectronic substrate undergoing a process of forming the SSL device in  FIGS. 3A and 3C  in accordance with embodiments of the technology. 
         FIGS. 5A and 5B  are perspective views of a portion of a microelectronic substrate undergoing a process of forming the SSL device in  FIGS. 3A and 3C  in accordance with embodiments of the technology. 
     
    
    
     DETAILED DESCRIPTION 
     Various embodiments of SSL devices and associated methods of manufacturing are described below. The term “microelectronic substrate” is used throughout to include substrates upon which and/or in which SSL devices, microelectronic devices, micromechanical devices, data storage elements, read/write components, and other features are fabricated. The term “optical efficiency” is defined as a percentage of photon output per unit electron input. A person skilled in the relevant art will also understand that the technology may have additional embodiments, and that the technology may be practiced without several of the details of the embodiments described below with reference to  FIGS. 2A-5B . 
     In the following discussion, an LED having GaN/InGaN materials is used as an example of an SSL device in accordance with embodiments of the technology. Several embodiments of the SSL device may also include at least one of gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), gallium arsenide phosphide (GaAsP), aluminum gallium indium phosphide (AlGaInP), gallium(III) phosphide (GaP), zinc selenide (ZnSe), boron nitride (BN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum gallium indium nitride (AlGaInN), and/or other suitable semiconductor materials. The foregoing semiconductor materials may have generally similar or different crystal structures than GaN/InGaN materials. However, the following definition of polar, non-polar, and semi-polar planes may still apply. 
       FIGS. 2A-2F  are schematic perspective views of various crystal planes in a portion of a GaN/InGaN material. In  FIGS. 2A-2F , Ga (or Ga/In) and N atoms are schematically shown as large and small spheres, respectively. As shown in  FIGS. 2A-2F , the GaN/InGaN material has a wurtzite crystal structure with various lattice planes or facets as represented by corresponding Miller indices. A discussion of the Miller index can be found in the  Handbook of Semiconductor Silicon Technology  by William C. O&#39;Mara. 
     As used hereinafter, a “polar plane” generally refers to a crystal plane in a crystal structure that contains only one type of atoms. For example, as shown in  FIG. 2A , the polar plane denoted as the “c-plane” in the wurtzite crystal structure with a Miller index of (0001) contains only Ga atoms. Similarly, other polar planes in the wurtzite crystal structure may contain only N atoms and/or other suitable type of atoms. 
     As used hereinafter, a “non-polar plane” generally refers to a crystal plane in a crystal structure that is generally perpendicular to a polar plane (e.g., to the c-plane). For example,  FIG. 2B  shows a non-polar plane denoted as the “a-plane” in the wurtzite crystal structure with a Miller index of (11  2 0).  FIG. 2C  shows another non-polar plane denoted as the “m-plane” in the wurtzite crystal structure with a Miller index of (10  1 0). Both the a-plane and the m-plane are generally perpendicular to the c-plane shown in  FIG. 2A . 
     As used hereinafter, a “semi-polar plane” generally refers to a crystal plane in a crystal structure that is canted relative to a polar plane (e.g., to the c-plane) without being perpendicular to the polar plane. For example, as shown in  FIGS. 2D-2F , each of the semi-polar planes in the wurtzite crystal structure with Miller indices of (10  13 ), (10  1 1), and (11  2 2) form an angle with the c-plane shown in  FIG. 2A . The angle is greater than 0° but less than 90°. Even though only particular examples of crystal planes are illustrated in  FIGS. 2A-2F , each of the polar, non-polar, and semi-polar planes can also include other crystal planes not illustrated in  FIGS. 2A-2F . 
       FIG. 3A  is a cross-sectional view and  FIG. 3B  is a top view of a portion of an SSL device  100  in accordance with embodiments of the technology. Referring to  FIG. 3A , the SSL device  100  includes a microelectronic substrate  102  carrying an LED structure  104 . The microelectronic substrate  102  includes a first surface  102   a  proximate to the LED structure  104  and a second surface  102   b  opposite the first surface  102   a . Even though not shown in  FIG. 3A , other embodiments of the SSL device  100  can also include a buffer material, a mirror material, a support structure, interconnects, and/or other suitable mechanical/electrical components (not shown). 
     In the illustrated embodiment, the microelectronic substrate  102  includes an optional support material  103  on a substrate material  101 . In certain embodiments, the support material  103  and the substrate material  101  include the same composition (e.g., GaN). In other embodiments, the support material  103  and the substrate material  101  can include different materials. For example, the support material  103  can include a GaN material, and the substrate material  101  can include silicon (Si), silicon carbide (SiC), sapphire (Al 2 O 3 ), a combination of the foregoing materials and/or other suitable substrate materials. In further embodiments, the substrate material  101  may be omitted. 
     Referring to  FIGS. 3A and 3B  together, the LED structure  104  includes a plurality of foundations  106  ( FIG. 3A ) and a first semiconductor material  108  both on the first surface  102   a  of the microelectronic substrate  102 , a second semiconductor material  110  spaced laterally apart from the first semiconductor material  108 , and an active region  112  between the first and second semiconductor materials  108  and  110 . The LED structure  104  can also include a first contact  114  in the first semiconductor material  108  and a second contact  116  in the second semiconductor material  110 . 
     In the illustrated embodiment, the first and second semiconductor materials  108  and  110 , the active region  112 , the first contact  114 , and the second contact  116  form an LED surface  118  ( FIG. 3B ) that is generally planar and parallel to the first surface  102   a  of the microelectronic substrate  102 . In other embodiments, the LED surface  118  may be generally planar but slanted relative to the first surface  102   a  of the microelectronic substrate  102 . In further embodiments, the LED surface  118  may be non-planar. In yet further embodiments, the LED surface  118  may have other suitable configurations. 
     In the embodiment shown in  FIG. 3A , the foundations  106  individually include a generally cuboid shape extending along a direction with a Miller index of (10  1 1) relative to the support material  103 . In other embodiments, the foundations  106  can also have a quadrilateral frustum, cubic, pentagonal, parallelepiped, rhombohedron, and/or other suitable shapes. The foundations  106  may also extend along other desired directions relative to the support material  103 . In certain embodiments, the foundations  106  may include the same material as the microelectronic substrate  102 . In other embodiments, the foundations  106  may include a material different from the microelectronic substrate  102 . Suitable materials of the foundations  106  can include silicon oxide (SiO 2 ), silicon nitride (SiN), aluminum nitride (AlN), GaN, and/or other semiconductor materials. 
     Referring to  FIG. 3A , the first semiconductor material  108  and the second semiconductor material  110  can extend from the first surface  102   a  along a direction generally parallel to a polar axis (denoted as the c-axis). In the illustrated embodiment, the first semiconductor material  108  includes an N-type GaN material with a first portion  108   a  adjacent to a second portion  108   b , as indicated by a phantom line in  FIG. 3A . The first portion  108   a  extends between the LED surface  118  and the first surface  102   a  of the microelectronic substrate  102 . The second portion  108   b  is defined by the foundation  106 , the active region  112 , and the first portion  108   a . In other embodiments, the first and second portions  108   a  and  108   b  of the first semiconductor material  108  may have other relative positions and/or suitable configurations. 
     As shown in  FIG. 3A , the first semiconductor material  108  includes a semiconductor surface  109  and a plurality of sidewalls  120  (identified individually as a first sidewall  120   a  and a second sidewall  120   b  for illustration purposes) between the semiconductor surface  109  and the first surface  102   a  of the microelectronic substrate  102 . The sidewalls  120  can extend along semi-polar planes of the first semiconductor material  108 . For example, in the illustrated embodiment, the first sidewall  120   a  extends along a semi-polar plane with a Miller index of (10  1 1). The second sidewall  120   b  extends along another semi-polar plane with a Miller index of (11  2 2). In other embodiments, the sidewalls  120  can also extend along other suitable semi-polar planes of the first semiconductor material  108 . 
     The second semiconductor material  110  includes a P-type GaN material that extends between the LED surface  118  and the foundation  106 . As shown in  FIG. 3A , the second semiconductor material  110  can have a first sidewall  121   a  and a second sidewall  121   b . The first sidewall  121   a  can be generally parallel to the first sidewall  120   a  of the first semiconductor material  108 . The second sidewall  121   b  can be generally parallel to the c-axis. In other embodiments, the second semiconductor material  110  may have other suitable cross sections and/or configurations. 
     The active region  112  can be formed on a semi-polar plane of the first semiconductor material  108 . For example, as shown in  FIG. 3A , the active region  112  includes an InGaN material on the first semi-polar sidewall  120   a  with a Miller index of (10  1 1) and the second semi-polar sidewall  120   b  with a Miller index of (11  2 2) of the first semiconductor material  108 . As a result, the active region  112  can form an angle α of about 58° relative to the first surface  102   a  of the microelectronic substrate  102  (or an angle β of about 32° relative to the c-axis). In other embodiments, the active region  112  may also include other suitable LED materials on other suitable semi-polar planes of the first and/or second semiconductor materials  108  and  110 . 
     As shown  FIGS. 3A and 3B , the first and second contacts  114  and  116  can include a conductive material (e.g., copper, aluminum, gold, etc.) in a first slot  113   a  ( FIG. 3A ) and a second slot  113   b  ( FIG. 3A ) in the first and second semiconductor materials  108  and  110 , respectively. In the illustrated embodiment, the first and second contacts  114  and  116  have a length L and a height H approximately equal to those of the first and second semiconductor materials  108  and  110 , respectively. For example, the first contact  114  extends completely between the semiconductor surface  109  of the first semiconductor material  108  and the first surface  102   a  of the microelectronic substrate  102 . In other embodiments, the first and second contacts  114  and  116  can have other dimensions and/or configurations. 
     Even though the first semiconductor material  108 , the second semiconductor material  110 , and the active region  112  are shown in  FIGS. 3A and 3B  as being generally parallel to one another at the LED surface  118 , other embodiments of these components may have other shapes and/or configurations. For example,  FIG. 3C  is a top view of a portion of the SSL device  100  in  FIG. 3A  in accordance with additional embodiments of the technology. As shown in  FIG. 3C , the first semiconductor material  108 , the second semiconductor material  110 , the active region  112 , and the second contact  116  are generally concentric, and each individually has a hexagonal shape. The first contact  114  is located in a central region of the first semiconductor material  108 . In other embodiments, at least some of the foregoing components may have a circular, rectangular, trapezoidal, and/or other suitable shapes. 
     Several embodiments of the SSL device  100  may have an increased optical efficiency compared to conventional LEDs. According to conventional techniques, the active region of an LED is typically grown along the c-axis ( FIG. 3A ), i.e., on polar planes of one of the first and second semiconductor materials  108  and  110 . Without being bound by theory, it is believed that the GaN/InGaN materials grown along the c-axis are polarized with an induced internal electric field generally perpendicular to the direction of growth. It is also believed that the internal electric field can slant the energy bands of the active region and can spatially prevent some of the electrons in the N-type GaN material from recombining with holes in the P-type GaN material during operation. The low recombination rate can result in a low optical efficiency of the LED. As a result, by forming the active region  112  on a semi-polar plane of the first or second semiconductor material  108  or  110 , the induced internal electric field can be reduced. Thus, the recombination rate in the SSL device  100  may be increased to improve the optical efficiency of the SSL device  100 . 
     Several embodiments of the SSL device  100  may also have a reduced contact resistance and improved current spread through the active region  112  when compared to conventional LEDs. For example, as shown in  FIG. 3A , the first and second contacts  114  and  116  are in physical contact with the entire sidewalls substantially of the first and second semiconductor materials  108  and  110 , respectively. As a result, the contact area between the first (or second) contact  114  (or  116 ) and the first (or second) semiconductor material  108  (or  110 ) may be increased compared to the contact points shown in  FIG. 1 . The increased contact area can thus reduce the electric resistance between the first (or second) contact  114  (or  116 ) and the first (or second) semiconductor material  108  (or  110 ) and improve the current spread through the active region  112 . 
     Several embodiments of the SSL device  100  may further have improved light extraction efficiency when compared to conventional LEDs. As used hereinafter, the light extraction efficiency generally refers to a percentage of photons extracted from an SSL device per unit photon generated internally by the SSL device. Without being bound by theory, it is believed that the N-type and P-type GaN materials  14  and  18  ( FIG. 1 ) and the InGaN/GaN MQW  16  ( FIG. 1 ) of the LED  10  ( FIG. 1 ) have different indices of refraction, which may result in at least partially internal reflection. For example, when a light strikes the surface between the GaN materials  14  and  18  and InGaN/GaN MQW  16  at an angle greater than the critical angle defined by the indices of refraction, internal reflection occurs. Thus, at least a portion of the generated light may be trapped in the InGaN/GaN MQW  16  and fails to be extracted. It is believed that the canted active region  112  can enable more light to be extracted by increasing the critical angle of internal reflection. 
     Even though the first and second semiconductor materials  108  and  110  are described above as including an N-type GaN material and a P-type GaN material, respectively, in other embodiments the second semiconductor material  110  can include an N-type GaN material and the first semiconductor material  108  can include a P-type material. In further embodiments, at least one of the first and second semiconductor materials  108  and  110  can include other suitable cladding materials. 
       FIGS. 4A-4E  are perspective and cross-sectional views of a portion of a microelectronic substrate undergoing a process of forming the SSL device  100  in  FIGS. 3A and 3B  in accordance with embodiments of the technology. As shown in  FIGS. 4A and 4B , an optional initial stage of the process can include forming the support material  103  on the substrate material  101  of the microelectronic substrate  102 . In one embodiment, forming the support material  103  includes forming a GaN material with a thickness of, for example, one micron on the substrate material  101 . In other embodiments, the support material  103  may include a GaN material with other desired thicknesses and/or may include a different material. Techniques for forming the GaN material can include metal organic CVD (“MOCVD”), molecular beam epitaxy (“MBE”), liquid phase epitaxy (“LPE”), hydride vapor phase epitaxy (“HVPE”), and/or other suitable techniques. 
     The process can then include forming the foundations  106  on the microelectronic substrate  102 . In one embodiment, the foundations  106  include a plurality of silicon oxide (“SiO 2 ”) cuboid slabs spaced apart from one another by an open region  122 . In one embodiment, forming the plurality of SiO 2  slabs can include depositing a photoresist (not shown) on the microelectronic substrate  102 , patterning the photoresist to define the openings generally corresponding to the slabs, and depositing SiO 2  through the openings via chemical vapor deposition (“CVD”), atomic layer deposition (“ALD”), and/or other suitable techniques. In another embodiment, forming the plurality of SiO 2  slabs can include blanket depositing SiO 2  material on the first surface  102   a , patterning the deposited SiO 2  material with a photoresist (not shown), and removing portions of the SiO 2  material to form the foundations  106 . In further embodiments, the foundations  106  may be formed via other suitable techniques. 
     As shown in  FIGS. 4C and 4D , the process includes forming the first semiconductor material  108  on a portion of the foundations  106  and the first surface  102   a  of the microelectronic substrate  102 . In one embodiment, forming the first semiconductor material  108  includes depositing an N-type GaN material on the foundations  106  and the microelectronic substrate  102  via MOCVD, MBE, LPE, HVPE, and/or other suitable techniques. 
     Without being bound by theory, it is believed that by adjusting the operating conditions during deposition, the deposited first semiconductor material  108  may have desired crystal planes on its surface. For example, a first temperature (e.g., 1050° C.), a first pressure (e.g., 300 mbar), and a first growth time of 90 minutes can be used such that the N-type GaN material grows from the open regions  122  into the foundations  106  with a first triangular cross-section  111   a  having semi-polar planes with a Miller index of (11  2 2). Then, a second temperature (e.g., 1160° C.), a second pressure (200 mbar), and a second growth time (e.g., 60 minutes) can be used such that the N-type GaN material may grow laterally over the foundations  106  to have a second generally trapezoidal cross-section  111   b . In other examples, (a) the size, direction, material, and/or fill factor of the foundations  106 , (b) the ambient conditions at the deposition site, (c) the impurities in the support material  103 , and/or (d) other suitable operating conditions can be adjusted such that the first semiconductor material  108  can have other semi-polar planes at its surface. 
     As shown in  FIG. 4E , the process can include forming the LED structure  104  by forming the active region  112  and the second semiconductor material  110  in series on the semi-polar planes  120   a  and  120   b  of the first semiconductor material  108 . In the illustrated embodiment, the active region  112  includes an InGaN/GaN MQW deposited on the first semiconductor material  108 , and the second semiconductor material  110  includes a P-type GaN material (e.g., magnesium doped) deposited on the active region material. The active region  112  and second semiconductor material  110  can be deposited using MOCVD, MBE, LPE, HVPE, and/or other suitable techniques. In other embodiments, the process can also include forming a mirror layer (e.g., aluminum, not shown) and a support structure (e.g., a silicon and/or silicon oxide material, not shown) on the LED structure  104 . 
       FIGS. 5A and 5B  are perspective views of a portion of a microelectronic substrate  102  undergoing a process of forming the SSL device  100  in  FIGS. 3A and 3C  in accordance with embodiments of the technology. As shown in  FIG. 5A , the process can include blanket depositing a foundation material  130  on the first surface  102   a  of the microelectronic substrate  102  (shown in  FIG. 5A  with the optional support material  103 ). In one embodiment, the foundation material  130  can include SiO 2  deposited via CVD, ALD, and/or other suitable techniques. The foundation material  130  has a first surface  130   a  and a second surface  130   b  in direct contact with the optional support material  103  and/or the microelectronic substrate  102 . In other embodiments, the foundation material  130  can include Al 2 O 3  and/or other suitable materials. 
     The process can include patterning the foundation material  130  using photolithography and/or other suitable techniques and removing a portion of the foundation material  130  to form a plurality of apertures  132 . Two apertures  132  are shown in  FIG. 5A  for illustration purposes though any desired number of apertures  132  may be formed based on particular applications. In the illustrated embodiment, the apertures  132  are generally circular. In other embodiments, the apertures  132  may be polygonal, oval, and/or have other shapes. 
     As shown in  FIG. 5B , the process can include forming the first semiconductor material  108  on the foundation material  130 . Without being bound by theory, it is believed that by controlling the operating conditions during deposition, the formed first semiconductor material  108  may have six semi-polar sidewalls  120  between a semiconductor surface  134  and the first surface  130   a  of the foundation material  130 . The process can then include forming the active region  112  ( FIG. 4E ) and the second semiconductor material  110  ( FIG. 4E ) on the first semiconductor material  108  as discussed above with reference to  FIG. 4E . 
     From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the disclosure. Many of the elements of one embodiment may be combined with other embodiments in addition to or in lieu of the elements of the other embodiments. Accordingly, the disclosure is not limited except as by the appended claims.