Abstract:
A non-volatile memory storage device has a non-volatile memory, e.g., a flash memory, and a controller coupled to the non-volatile memory. The controller comprises a plurality of control circuits and an arbitration circuit. Each control circuit is configured to generate a request to update the chip-enable (CE) signals for non-volatile memory, and the arbitration circuit is configured to determine when the requests are acknowledged. The arbitration circuit generates acknowledge signals to the control circuits when all of the requests of the control circuits have been received by the arbitration circuit. The CE signals for non-volatile memory are updated when requests are acknowledged.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    (A) Field of the Invention 
         [0002]    The present invention relates to a memory storage device and method for operating the same. More specifically, the present invention relates to a non-volatile memory storage device and method for operating the same. 
         [0003]    (B) Description of Related Art 
         [0004]      FIG. 1  illustrates an 8-bit flash memory storage device  10  including a flash controller  11  and a flash memory  12 . The flash controller  11  has a flash control circuit  13  which can issue a chip-enable (CE) signal to access the flash memory  12 . An 8-bit flash data bus FD[ 7 : 0 ] is connected between the flash control circuit  13  and the flash memory  12 . 
         [0005]      FIG. 2  illustrates a 16-bit flash memory storage device  20  including a flash controller  21  and a flash memory  22 . The flash memory  22  has two flash memory chips  221  and  222 . The flash controller  21  has a flash control circuit  23  that can issue a CE signal to access the flash memory chips  221  and  222 . A 16-bit flash data bus FD[ 15 : 0 ] is connected between the flash control circuit  23  and the flash memory chips  221  and  222 . 
         [0006]      FIG. 3  illustrates a flash memory storage device  30 , which is popularly used in current flash memory storage devices or memory card devices, including a flash controller  31  and a flash memory  32 . The flash memory  32  has a plurality of flash memory chips  34 . The flash controller  31  has a flash control circuit  33  that can issue a plurality of CE signals (CE[ 0 ] to CE[ 15 ]) to access the flash memory chips  34  of the flash memory  32 . A 16-bit flash data bus FD[ 15 : 0 ] is connected between the flash control circuit  33  and the flash memory chips  34 . 
         [0007]    In order to increase the performance of memory storage devices, it is common to increase the number of data buses, resulting in a need for more flash control circuits. As shown in  FIG. 4 , a flash controller  41  of a flash memory storage device  40  needs 64-bit data bus in total. Four control circuits, i.e., Flash Control Circuit  0 , Flash Control Circuit  1 , Flash Control Circuit  2  and Flash Control Circuit  3 , are used, and each controls a 16-bit data bus. Flash Control Circuit  0  generates CE[ 15 : 0 ] to control the flash memory chips  42  at the first two rows, and FD[ 15 : 0 ] is the data bus between the Flash Control Circuit  0  and the flash memory chips  42 . Likewise, Flash Control Circuit  1  generates CE[ 31 : 16 ] to control the flash memory chips  42  at the third and fourth rows, and FD[ 31 : 16 ] is the data bus thereof. Flash Control Circuit  2  generates CE[ 47 : 32 ] to control the flash memory chips  42  at the fifth and sixth rows, and FD[ 47 : 32 ] is the data bus thereof. Flash Control Circuit  3  generates CE[ 63 : 48 ] to control the flash memory chips  42  at the seventh and eighth rows, and FD[ 63 : 48 ] is the data bus thereof. Accordingly, 64 CE pads are needed for the flash controller  41 . However, more CE chip pads would increase the package size and cost. 
         [0008]      FIG. 5  illustrates a timing diagram for the flash memory storage device  40  in  FIG. 4 . “U” indicates CE update timing, and the CE signals CE[ 0 ], CE[ 16 ], CE[ 32 ] and CE[ 48 ], corresponding to the timings “U” for Flash Control Circuit  0 , Flash Control Circuit  1 , Flash Control Circuit  2  and Flash Control Circuit  3 , are changed from “1” to “0” to access the first column of flash memory chips  42 , respectively. Then, CE[ 0 ], CE[ 16 ], CE[ 32 ], and CE[ 48 ] are changed from “0” to “1” after accessing the first column of flash memory chips  42 , respectively. 
         [0009]      FIG. 6  illustrates a timing diagram of the flash memory storage device  40  in which the operation of every two neighboring columns of flash memory chips are interleaved (so-called interleave-2), i.e., they do not operate at the same time. CE[ 0 ] and CE[ 1 ], CE[ 16 ] and CE[ 17 ], CE[ 32 ] and CE[ 33 ], CE[ 48 ] and CE[ 49 ] are interleaved, i.e., CE[ 0 ] and CE[ 1 ] will not be “0” at the same time, CE[ 16 ] and CE[ 17 ] will not be “0” at the same time, CE[ 32 ] and CE[ 33 ] will not be “0” at the same time, and CE[ 48 ] and CE[ 49 ] will not be “0” at the same time. But, CE signals of each flash control circuit work independently, e.g., CE[ 0 ] and CE[ 1 ] do not care CE[ 16 ], CE[ 17 ], CE[ 32 ], CE[ 33 ], CE[ 48 ], and CE[ 49 ]. In another embodiment, the operation of every four neighboring columns of flash memory chips are interleaved (so-called interleave-4). For instance, CE[ 0 ], CE[ 1 ], CE[ 2 ], and CE[ 3 ] are interleaved. 
         [0010]    The increase of performance for the flash memory storage devices may incur more power consumption. Peak power demand will grow dramatically when the flash control circuits execute flash commands at the same time. For instance, for the 8-bit memory storage device  10  shown in  FIG. 1 , the peak current is approximately 125 mA to 133 mA. For the 16-bit memory storage device  20  shown in  FIG. 2 , the peak current is approximately 230 mA to 239 mA. The memory storage devices  10  and  20  each have only one control circuit, and it can be seen that the peak current will increase tremendously as the number of control circuits increases. As shown in  FIG. 7 , when the Flash Control Circuit  0 , Flash Control Circuit  1 , Flash Control Circuit  2  and Flash Control Circuit  3  execute flash commands “60” and “D0” at the same time, a very high peak power consumption occurs at the end of “D0”. There is therefore a challenge to reduce the power consumption of the memory device with high performance. 
       SUMMARY OF THE INVENTION 
       [0011]    The present invention provides a non-volatile memory storage device and the operation method thereof to increase performance of the memory storage device and avoid high peak current when executing commands at the same time. 
         [0012]    According to the present invention, a non-volatile memory storage device has a non-volatile memory, e.g., a flash memory, and a controller coupled to the non-volatile memory. The controller comprises a plurality of control circuits and an arbitration circuit. Each control circuit is configured to generate a request to update the CE for the non-volatile memory, and the arbitration circuit configured to determine when the requests are acknowledged. The CE for non-volatile memory is updated when all of the requests are received and acknowledged by arbitration circuit. 
         [0013]    In brief, requests to update the CE for non-volatile memory are generated by the control circuits, and then the arbitration circuit determines when the requests are acknowledged. The CE for non-volatile memory will be updated when all of the requests are received and acknowledged. 
         [0014]    In an embodiment, the arbitration circuit generates acknowledge signals to the control circuits when all of the requests of the control circuits are received by the arbitration circuit. 
         [0015]    In another embodiment, the controller further comprises a command interleaving circuit to interleave timings of acknowledging the requests for the control circuits, so as to avoid peak current when executing commands. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]      FIGS. 1 to 4  illustrate known flash memory storage devices; 
           [0017]      FIGS. 5 to 7  illustrate known operation timing for flash memory storage devices; 
           [0018]      FIGS. 8 to 13  illustrate a memory storage device and the operation method thereof in accordance with an embodiment of the present invention; and 
           [0019]      FIGS. 14 to 15  illustrate a memory storage device and the operation method thereof in accordance with another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0020]    Embodiments of the present invention will now be described with reference to the accompanying drawings. A flash memory device is exemplified but not limited for non-volatile memory of the present invention below. 
         [0021]      FIG. 8  illustrates a 64-bit flash memory storage device  50  having a flash controller  51  and a flash memory  52 . The flash memory  52  is a memory array of flash memory chips  54 . The flash controller  51  includes Flash Control Circuit  0 , Flash Control Circuit  1 , Flash Control Circuit  2  and Flash Control Circuit  3 . Chip-enable signals CE[ 0 ], CE[ 1 ], . . . , CE[ 15 ] each control the flash memory chips  54  of the flash memory  52  in the same column. Flash data bus FD[ 15 : 0 ] is between the Flash Control Circuit  0  and the flash memory chips  54  of the first two rows. Flash data bus FD[ 31 : 16 ] is between the Flash Control Circuit  1  and the flash memory chips  54  of the third and fourth rows. Data bus FD[ 47 : 32 ] is between the Flash Control Circuit  2  and the flash memory chips  54  of the fifth and sixth rows. Data bus FD[ 63 : 48 ] is between the Flash Control Circuit  3  and the flash memory chips  54  of the seventh and eighth rows. 
         [0022]    In an embodiment, CE[ 15 : 0 ] transmitted to the flash memory chips  54  is determined by a CE arbitration circuit in the flash controller  51 . As shown in  FIG. 9 , in addition to Flash Control Circuit  0 , Flash Control Circuit  1 , Flash Control Circuit  2  and Flash Control Circuit  3 , the flash controller  51  further comprises a CE arbitration circuit  55 . Each flash control circuit transmits a CE_UPDATE_REQUEST signal to the CE arbitration circuit  55 , and the CE arbitration circuit  55  acknowledges receipt of the request signal by transmitting a CE_UPDATE_ACK signal to the flash control circuit. After receiving the CE_UPDATE_ACK signal, Flash Control Circuit  0 , Flash Control Circuit  1 , Flash Control Circuit  2  and Flash Control Circuit  3  transmit chip-enable signals ce_ 0  [ 15 : 0 ], ce_ 1  [ 15 : 0 ], ce_ 2  [ 15 : 0 ] and ce_ 3  [ 15 : 0 ] to the CE arbitration circuit  55 , respectively. Then, the CE arbitration circuit  55  transmits CE[ 15 : 0 ] to the flash memory chips  54 . 
         [0023]      FIG. 10  illustrates an embodiment of the timing diagram for the flash memory storage device  50 . Each of the flash control circuits may transmit CE_UPDATE_REQUEST signal denoted by “R” to the CE arbitration circuit, and the CE arbitration circuit will not send acknowledge signals CE_UPDATE_ACK denoted by “A” to the flash control circuits until all CE_UPDATE_REQUEST signals are received. The flash control circuits update chip-enable signals in the “U” to the arbitration circuit after receiving CE_UPDATE_ACK signals, thereby causing ce_ 0 [ 0 ], ce_ 1 [ 0 ], ce_ 2 [ 0 ] and ce_ 3 [ 0 ] to switch from “1” to “0” at the same time. In this embodiment, ce_ 0 [ 0 ], ce_ 1 [ 0 ], ce_ 2 [ 0 ], ce_ 3 [ 0 ], and CE[ 0 ] are changed from “1” to “0” at the same time. The CE_UPDATE_REQUEST signals from the flash control circuits may be transmitted to an AND gate to generate a CE_UPDATE_ACK signal as shown in  FIG. 11 . CE_UPDATE_ACK will be transmitted to the flash control circuits afterwards. 
         [0024]      FIG. 12  illustrates CE update procedures in accordance with the prior art and the present invention. For a prior art, in the flash control circuits, CE for flash memory chips will be updated directly from state A, then change to state B after CE signals are updated. According to the present invention, the flash control circuits transmit CE_UPDATE_REQUEST signals to the CE arbitration circuit when it needs to update CE, and CE for flash memory chips can be only updated until the CE arbitration circuit acknowledges CE_UPDATE_ACK signals to the flash control circuit. 
         [0025]      FIG. 13  illustrates a timing diagram for the flash memory storage device  50  in which every two neighboring columns of flash memory chips are interleaved (so-called interleave-2), i.e., they do not operate at the same time. Likewise, each of the flash control circuits may transmit CE_UPDATE_REQUEST signal denoted by “R” to the CE arbitration circuit, and the CE arbitration circuit will send acknowledge signals CE_UPDATE_ACK denoted by “A” to the flash control circuits until all CE_UPDATE_REQUEST signals are received. The flash control circuits change its chip-enable signals denoted by “U” after receiving CE_UPDATE_ACK signals. For ce_ 0 [ 0 ] and ce_ 0 [ 1 ], ce_ 1 [ 0 ] and ce_ 1 [ 1 ], ce_ 2 [ 0 ] and ce_ 2 [ 1 ], ce_ 3 [ 0 ] and ce_ 3 [ 3 ] corresponding to “U” of Flash Control Circuit  0 , Flash Control Circuit  1 , Flash Control Circuit  2  and Flash Control Circuit  3 , will not be “0” at the same time. CE[ 0 ] is logic AND from ce_ 0 [ 0 ], ce_ 1 [ 0 ], ce_ 2 [ 0 ], and ce_ 3 [ 0 ]. CE[ 1 ] is logic AND from ce_ 0 [ 1 ], ce_ 1 [ 1 ], ce_ 2 [ 1 ], and ce_ 3 [ 1 ]. CE[ 0 ] and CE[ 1 ] will not be “0” at the same time because flash control circuits update its CE signals simultaneously. 
         [0026]    The increase of performance for the flash memory storage devices may incur more power consumption. Peak power demand will rise dramatically when the flash control circuits execute flash commands at the same time. According to this invention, the command timings for flash control circuits are interleaved or differentiated to reduce peak current. In  FIG. 14 , at time “a”, all flash control circuits request to update CE, Flash Control Circuit  0  receives an acknowledge signal denoted by “A”; however, Flash Control Circuit  1  receives “A” with an interval of “WAIT_CNT” in comparison with Flash Control Circuit  0 . In other words, the generation of acknowledge signal “A” for Flash Control Circuit  1  is postponed with a time period of “WAIT_CNT.” Likewise, the generation of acknowledge signals “A” for Flash Control Circuit  2  and Flash Control Circuit  3  are postponed by the time period “WAIT_CNT” in sequence also. Accordingly, the acknowledge signals for Flash Control Circuit  0 , Flash Control Circuit  1 , Flash Control Circuit  2 , Flash Control Circuit  3  are generated at time “b”, “c”, “d” and “e”, respectively, i.e., the timings for acknowledgment for the control circuits are interleaved or differentiated. Therefore, the commands “60” and “D0” will not execute at the same time, thereby reducing the peak power consumption of memory storage device while executing commands. In  FIG. 9 , the flash controller  51  can also interleave the acknowledgement of receipt of the requests, thereby preventing commands from executing at the same time to overcome the current peak problem. In an embodiment, the CE arbitration circuit  55  may comprise a command interleaving circuit  56  to interleave the timings of acknowledging the requests. 
         [0027]      FIG. 15  illustrates another embodiment, a flash memory storage device  60  having a flash controller  61  and a flash memory  62 . The flash memory  62  includes a memory array of flash memory chips  64 . The flash controller  61  includes Flash Control Circuit  0 , Flash Control Circuit  1 , Flash Control Circuit  2 , Flash Control Circuit  3 , Flash Control Circuit  4 , Flash Control Circuit  5 , Flash Control Circuit  6 , and Flash Control Circuit  7 . Chip enable signals CE[ 0 ], CE[ 1 ], . . . , CE[ 15 ] each control the flash memory chips  64  of the flash memory  62  in the same column. Each flash control circuit has an 8-bit data bus. Flash Control Circuit  0  has data bus FD[ 7 : 0 ]; Flash Control Circuit  1  has data bus F[ 15 : 8 ]; Flash Control Circuit  2  has data bus F[ 23 : 16 ]; Flash Control Circuit  3  has data bus F[ 31 : 24 ]; Flash Control Circuit  4  has data bus F[ 39 : 32 ]; Flash Control Circuit  5  has data bus F[ 47 : 40 ]; Flash Control Circuit  6  has data bus F[ 55 : 48 ]; Flash Control Circuit  7  has data bus F[ 63 : 56 ]. The CE Arbitration Circuit  65  can coordinate CE signals of flash control circuits and interleave the timing of command issue to increase performance and avoid peak current concurrently. 
         [0028]    The above-described embodiments of the present invention are intended to be illustrative only. Numerous alternative embodiments may be devised by those skilled in the art without departing from the scope of the following claims.