Abstract:
A video encoding apparatus for encoding a video stream comprising: a reference frame cache configured to cache reference frame video data retrieved from a reference frame storage unit in external memory, the reference frame video data cached in the reference frame cache being derived from an individual frame of the video stream; a first source frame storage unit configured to store a first block of unencoded video data taken from a first source frame of the video stream; a second source frame storage unit configured to store a second block of unencoded video data taken from a second source frame of the video stream; a first video encoder configured to perform a first encoding operation to encode the first block of unencoded video data with reference to the reference frame video data cached in the reference frame cache; and a second video encoder configured to perform a second encoding operation to encode said second block of unencoded video data with reference to the reference frame video data cached in the reference frame cache, wherein the first video encoder and the second video encoder are configured to perform the first encoding operation and the second encoding operation in parallel with one another.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a video data processing apparatus, and in particular relates to encoding of video by such a video data processing apparatus. 
         [0003]    2. Description of the Prior Art 
         [0004]    Contemporary encoding standards, such as H.264, incorporate many advanced techniques to achieve a high degree of coding efficiency, for example multi-picture inter-picture prediction, intra-coding and various entropy encoding techniques. 
         [0005]    Nevertheless, despite the great advances in encoding efficiency that have been achieved, video system designers naturally continually strive to design video systems which operate at (or close to) the achievable limits of video quality and frame transmission rates. 
         [0006]    Although dramatic compression ratios may be achieved by contemporary video encoding standards, video systems for performing encoding must be able to handle the high bandwidths of video data that result from the output of the high resolution and frame rate video cameras that are currently available. Indeed, in such systems the volume of video data traffic is typically the dominant bandwidth on the system bus. A further critical constraint on the system bandwidth is the random access memory bandwidth. The DRAM (Dynamic Random Access Memory) storage units employed by contemporary video systems have a limited bandwidth for accessing their stored data. If the system design requires a higher bandwidth, then this may necessitate the inclusion of an additional DRAM device, which in certain space-limited systems (such as embedded video encoders) may not be viable. Hence it will be recognised that bandwidth at the system level is a critical parameter in such systems. 
         [0007]    Nevertheless, it is well known that consumers are hard taskmasters, continually demanding higher specifications and new features from contemporary video systems. For example, a slow motion capability on video cameras is a popular feature, yet the increased frame rate that this requires can be become a serious demand on the system bandwidth. A typical encoding pattern for video data comprises an initial intra-coded frame (“I-frame”) followed by a series of predicted pictures (“P-frames”) which are each predicted with reference to the previous frame. Since video data bandwidth increases approximately linearly with frame rate, there may be little capacity for an increase in frame rate in a video system which is already operating close to its full bandwidth capacity. 
         [0008]    Some papers which discuss implementations of H.264 encoding and decoding are: “Implementation of H.264 Encoder and Decoder on Personal Computers”, Y.-K. Chen, E. Q. Li, X. Zhou, and S. L. Ge, in Journal of Visual Communications and Image Representations, vol. 17, no. 2, pp. 509-532, April 2006; and “Parallel H.264 Decoding on an Embedded Multicore Processor”, Azevedo, A., Meenderinck, C., Juurlink, B., Terechko, A., Hoogerbrugge, J., Alvarez, M., and Ramirez, A., 2009 , In Proceedings of the  4 th international Conference on High Performance Embedded Architectures and Compilers.    
         [0009]    It would be desirable to provide an improved technique for performing video encoding which enables an increase in frame rate, without a proportional increase in the bandwidth required to handle the consequent video data. 
       SUMMARY OF THE INVENTION 
       [0010]    Viewed from a first aspect, the present invention provides a video encoding apparatus for encoding a video stream comprising: a reference frame cache configured to cache reference frame video data retrieved from a reference frame storage unit in external memory, said reference frame video data cached in said reference frame cache being derived from an individual frame of said video stream; a first source frame storage unit configured to store a first block of unencoded video data taken from a first source frame of said video stream; a second source frame storage unit configured to store a second block of unencoded video data taken from a second source frame of said video stream; a first video encoder configured to perform a first encoding operation to encode said first block of unencoded video data with reference to said reference frame video data cached in said reference frame cache; and a second video encoder configured to perform a second encoding operation to encode said second block of unencoded video data with reference to said reference frame video data cached in said reference frame cache, wherein said first video encoder and said second video encoder are configured to perform said first encoding operation and said second encoding operation in parallel with one another. 
         [0011]    Accordingly, the present invention provides a video encoding apparatus comprising a reference frame cache and two source frame storage units. The reference frame cache is configured to cache reference frame video data which is used for the above mentioned predictive techniques for encoding the video data stored in the first source frame storage unit and the second source frame storage unit. The video encoding apparatus further comprises two video encoders which encode blocks of unencoded video data stored in the first and second source frame storage units respectively. The encoding operations carried out by the first and second video encoders are performed in parallel with one another, both video encoders making reference to the same reference frame video data cached in the referenced frame cache. 
         [0012]    Consequently, because both video decoders perform their respective encoding operations with reference to the same cached reference frame video data, the bandwidth requirement for this arrangement is approximately half that which would be required for two video encoders operating in parallel, but independently. 
         [0013]    The inventors of the present invention realised that a bandwidth efficient video encoder could be provided, by performing parallel encoding on blocks of video data taken from two different source frames in the video stream, by performing those parallel encoding operations with reference to reference frame video data derived from the same individual frame of the video stream. It will be recognised the reduction in bandwidth achieved for a higher frame rate can only come at the expense of some quality, since one of the encoders will be performing its encoding operation with reference to more temporally remote reference frame video data, yet in some implementations, such as enabling a slow motion feature on a video camera, this trade off has been found to be acceptable. 
         [0014]    The video encoding apparatus may only comprise two video encoders operating in parallel, but according to one embodiment said video encoding apparatus further comprises at least one further source frame storage unit, each at least one further source frame storage unit configured to store at least one further block of unencoded video data taken from at least one further source frame of said video stream; and at least one further video encoder configured to perform at least one further encoding operation to encode said at least one further block of unencoded video data with reference to said reference frame video data cached in said reference frame cache, wherein said at least one further video encoder is configured to perform said at least one further encoding operation in parallel with said first encoding operation and said second encoding operation. 
         [0015]    Accordingly, at least one further source frame storage unit storing blocks of unencoded video data from at least one further source frame of the video stream is provided, along with at least one further video encoder configured to perform its encoding operation with reference to the same cached referenced frame video data being used by the first and second video encoders, and furthermore to perform its encoding in parallel with the first and second video encoder. In this way, a triple frame rate may be handled, for only a modest increase in the bandwidth requirement, since the same reference frame video data is used, and only the additional blocks of unencoded video data from the further source frame of the video stream need to be retrieved. Equally, even higher frame rates may be handled (4×, 5× etc.) if further video encoders are correspondingly added. 
         [0016]    The parallel video encoders may perform their encoding operations with reference to reference video data derived from only one individual frame of the video stream, but according to one embodiment at least one of said first video encoder and said second video encoder is configured to perform its respective encoding operation with reference to further reference frame video data cached in said reference frame cache and derived from at least one further individual reference frame. 
         [0017]    It is known in contemporary video encoding standards that encoding efficiencies may be gained by performing video encoding with reference to more than one video reference frame. Hence, either or both of the first and second video encoder may, in some embodiments perform their encoding also operations with reference to an additional reference frame, the reference frame video data from this additional reference frame also being cached in the reference frame cache. 
         [0018]    Similarly, in embodiments where three or more video encoders are provided, in some such embodiments said at least one further video encoder is configured to perform said at least one further encoding operation with reference to said further reference frame video data cached in said reference frame cache and derived from at least one further individual reference frame. In this way the further video encoders (third, fourth etc) may also contribute to the encoded efficiency by performing their encoding operations with reference to additional video reference frames. 
         [0019]    According to some embodiments, at least one of said first video encoder and said second video encoder is configured to perform mono-directional prediction encoding. Mono-directional prediction encoding comprises performing video encoding with reference to video reference frame data taken from a frame (or frames) which is in one direction (typically in advance of) with respect to the source frame being encoded. A source frame thus encoded is sometimes referred to as a P-frame (“predicted picture”). 
         [0020]    In some embodiments, at least one of said first video encoder and said second video encoder is configured to perform bi-directional prediction encoding. In such embodiments, the source frame being encoded is encoded with reference to reference frame video data taken from frames both in advance of and following the source frame. A frame of video data thus encoded is sometimes referred to, as a B-frame (“bi-predictive picture”). 
         [0021]    In some embodiments, one of said first video encoder and said second video encoder is configured to perform mono-directional encoding and the other of said first video encoder and said second video encoder is configured to perform bi-directional prediction encoding. In other words, one of the video encoders generates a P-frame, whilst the other generates a B-frame. 
         [0022]    Similarly, in embodiments where there is at least one further video encoder, this further video encoder may perform mono-directional or bi-directional prediction encoding. In one embodiment, said at least one further video encoder is configured to perform mono-directional predication encoding, whereas in another embodiment said at least one further video encoder is configured to perform bi-directional prediction encoding. 
         [0023]    In order to allow a continuous process of encoding a received video stream, it may be necessary to reconstruct a block of video data after it has been encoded, to provide reference data for further encoding operations. Hence, in one embodiment said first video encoder is further configured to perform a decoding operation on encoded video data resulting from said first encoding operation to generate a reconstructed block for storage in said reference frame storage unit in said external memory. Hence, the output of the first video encoder is reconstructed and thus provides the reference frame data stored in the external memory. 
         [0024]    The reference frame video data cached in the reference frame cache may be organised in a number of different ways, but in one embodiment said reference frame video data cached in said reference frame cache derived from said individual frame of said video stream comprises neighboring blocks spatially adjacent to said first and second block of unencoded video data. Caching a set of neighbouring blocks that are spatially adjacent to the first and second block of unencoded video data. This presents an advantageous selection of reference frame video data since not only is the reference frame video data more likely to be relevant to the first and second block of unencoded video data (since it is spatially close to those blocks), but also the reference frame cache is efficiently used since both the first and second block of unencoded video data are likely to find relevant reference frame data for their encodings. The first and second source frame storage unit may take a number of forms, but in some embodiments said first source frame storage unit and said second source frame storage unit are buffers. This presents an advantageous arrangement for handling streaming video data. Similarly, in some embodiments said at least one further source frame storage unit is a buffer. 
         [0025]    The video stream to be encoded may be stored in a variety of ways in the external memory, but in one embodiment said video stream is retrieved from a FIFO in said external memory. This also presents an advantageous arrangement for handling a stream of video data being provided to the external memory, for example from a video camera in recording mode. 
         [0026]    The video stream being encoded may derive from a range of different sources, but in embodiments, said video stream is generated in a slow motion recording mode. Slow motion recording is typically effected by recording video data at a higher frame rate than usual, for example at 120 FPS (frames per second) instead of 60 FPS, whilst later playing back the video stream at the usual frame rate (60 FPS in this example). If the video encoding apparatus were to attempt to encode this higher frame rate video data in its normal processing mode, the bandwidth requirement imposed on the system of which the video encoding apparatus forms part would rise significantly, and could well exceed the system capabilities. However, by the techniques of the present invention, a frame rate such as that which is required for a slow motion recording mode is achieved, without commensurately increasing the bandwidth requirement. 
         [0027]    In some embodiments, said first source frame of said video stream and said second source frame of said video stream are sequential in said video stream. 
         [0028]    Viewed from a second aspect the present invention provides a method of encoding a video stream comprising the steps of: retrieving reference frame video data from a reference frame storage unit in external memory; caching said reference frame video data in a reference frame cache, said reference frame video data cached in said reference frame cache being derived from an individual frame of said video stream; receiving a first block of unencoded video data taken from a first source frame of said video stream; storing said first block of unencoded video data in a first source frame storage unit; receiving a second block of unencoded video data taken from a second source frame of said video stream; storing said second block of unencoded video data in a second source frame storage unit; performing a first encoding operation to encode said first block of unencoded video data with reference to said reference frame video data cached in said reference frame cache; and performing a second encoding operation to encode said second block of unencoded video data with reference to said reference frame video data cached in said reference frame cache, wherein said first encoding operation and said second encoding operation are performed in parallel with one another. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0029]    The present invention will be described further, by way of example only, with reference to embodiments thereof as illustrated in the accompanying drawings, in which: 
           [0030]      FIG. 1  schematically illustrates a video system comprising a video camera, system memory and video encoder; 
           [0031]      FIG. 2  schematically illustrates in more detail some components of the video encoder shown in  FIG. 1 ; 
           [0032]      FIGS. 3A ,  3 B and  3 C schematically illustrate some encoding patterns of sequential P-frames; 
           [0033]      FIGS. 4A and 4B  schematically illustrate some encoding patterns of sequential frames including both P-frames and B-frames; and 
           [0034]      FIG. 5  schematically illustrates a series of steps taken in one embodiment. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0035]      FIG. 1  schematically illustrates a video system according to one embodiment. This video system  100  comprises video camera  105 , system memory  110 , system controller  115 , video encoder  120  and system bus  125 . It will be understood that video system  100  will typically comprise various other components, however these are not illustrated here for clarity purposes. In operation the user employs video camera  105  to capture video footage which is passed, in the form of a stream of video data, to system memory  110 , where it is received by FIFO  130 . FIFO  130  is able to temporarily store the video data generated by video camera  105  for a sufficient time period for the video data to be accessed and encoded by video encoder  120 . 
         [0036]    Video encoder  120 , system memory  110  and system controller  115  communicate via system bus  125 . In this embodiment system bus  125  is configured in accordance with the AMBA (Advanced Microcontroller Bus Architecture) specification developed by ARM Limited of Cambridge, UK. These components connect to the bus via interconnects configured in accordance with the Advanced eXtensible Interface (AXI) also of ARM Limited, Cambridge, UK. System controller  115  is configured to provide overall control of the video system  100 . 
         [0037]    Video encoder  120  comprises two video encoding engines (described in more detail with reference to  FIG. 2 ). Video encoder  120  also comprises reference frame cache  135 , first source frame buffer  140  and second source frame buffer  145 . The two video encoding engines of video encoder  120  are configured to perform their encoding operations in parallel, the first video encoding engine being configured to encode first source frame video data buffered in first source frame video buffer  140 , and the second video encoding engine being configured to encode video data buffered in second source frame buffer  145 . Notably, both video encoding engines perform their encoding operations with reference to the same video reference frame data cached in reference frame cache  135 . The video reference frame data cached in reference frame cache  135  is retrieved by video encoder  120 , via system bus  125 , from the reference frame storage  150  in system memory  110 . The video reference frame data stored in reference frame storage  150  is generated by video encoder  120  as part of its video encoding operations, some of the video data it encodes being reconstructed and passed back to system memory  110  for storage in reference frame storage  150 . This means that the encoding of unencoded video data in first source frame buffer  140  and second source frame buffer  145  is always performed with reference to previously encoded and reconstructed video data, ensuring that the subsequent process of decoding the encoded video is performed with reference to the same reference data used for its encoding. 
         [0038]    The video camera  105  further comprises slow motion button  155 , which switches video camera  105  into a slow motion recording mode, in which video footage recorded by the video camera  105  is generated such that when it is played back, the time progression of the recorded footage is slowed down, for example by a factor of two. In some embodiments slow motion button  155  is configured to put video camera  105  into one of a number of slow motion recording modes, each of which has a different slow down rate for the video footage it generates. 
         [0039]    When video camera  105  is operating in its normal recording mode, the transfer of unencoded video data from FIFO  130  to video encoder  120 , the transfer of reference frame video data from reference frame storage  150  to reference frame cache  135 , and the transfer of reconstructed video data from video encoder  120  to reference frame storage  150  place a considerable demand on the available bandwidth of system bus  125 . When video camera  105  is switched into slow motion recording mode by operating slow motion button  155 , the increased frame rate resulting from this slow motion operation could place an even greater burden on the bandwidth capacity of system bus  125  (since the bandwidth required increases approximately linearly with the frame rate), which could exceed the available capacity, or at least swamp the system bus  125  to such an extent that the overall performance of video system  100  would be significantly downgraded. 
         [0040]    However, system controller  115  is configured to identify when video camera  105  has been switched into slow motion recording mode, and to signal this fact to video encoder  120 . When video encoder  120  is notified that video camera  105  has switched to slow motion recording mode, it is configured to operate its two video encoding engines in parallel, each performing their respective encoding operations with reference to the same reference frame video data cached in reference frame cache  135 . In particular, when operating in this slow motion mode, the two video encoding engines in video encoder  120  are configured to each perform their encoding operations on separate frames of the video stream being generated by video camera  105 , where those frames are sequential frames to one another. The reference frame video data (with reference to which they perform their encoding operations) may in some embodiments be the frame which immediately precedes the two frames that the two encoding engines are currently processing, although other embodiments are also possible as will be described later with reference to  FIGS. 3 and 4 . 
         [0041]    More detail of the configuration of video encoder  120  is now given with reference to  FIG. 2 . First source frame buffer  140  and second source frame buffer  145  (see  FIG. 1 ) are illustrated in  FIG. 2  as embodied in DMA unit  200 . DMA  200  is connected to system bus  125  (not illustrated) and issues memory access requests onto the bus in order to retrieve blocks of unencoded video data from FIFO  130  and reference frame video data from reference frame storage  150 . The two video encoding engines in video encoder  120  share reference frame cache  135 . The first video encoding engine is comprised of motion compensator (MC)  205 A, motion estimator (ME)  210 A, forward discrete cosine transformer (FDCT)  215 A, quantizer (Q)  220 A and entropy encoder  225 A. Similarly, the second encoding engine comprises motion compensator (MC)  205 B, motion estimator (ME)  210 B, forward discrete cosine transformer (FDCT)  215 B, quantizer (Q)  220 B and entropy encoder  225 B. In addition, the first encoding engine further comprises dequantizer (dQ)  230 , inverse discrete cosine transformer (IDCT)  235  and deblocker (DBL)  240 . These additional components of the first video encoding engine are used to reconstruct the encoded video data generated by the first encoding engine for storage in reference frame storage  150  (via DMA  200 ). 
         [0042]    In one embodiment, when video camera  105  is operating in slow motion mode, the encoding of the sequence of frames in the generated video stream is performed as is illustrated in  FIG. 3A .  FIG. 3A  schematically illustrates the reference relationships between the sequence of frames. I 0  is an “Intra-coded” frame which does not require reference to another frame in order to be decoded, i.e. it is a fully specified image, much like a conventional static image file. The other illustrated frames, P 1 , P 2  etc are P-frames (“predicted”) which are encoded with reference to another (earlier) frame. The parallel operation of the two video encoding engines in video encoder  120  is illustrated in the example of  FIG. 3A  by the pairs of frames A, B, C etc. In other words, the first video encoding engine encodes frame P 2  with reference to frame I 0 , whilst the second video encoding engine encodes frame P 1  also with reference to frame I 0 . By sharing reference frame cache  135  and performing their respective encoding operations with reference to the same reference frame video data, the video encoding engines in video encoder  120  keep pace with the increased frame rate generated by video camera  105  in its slow motion mode, without significantly increasing the bandwidth demand placed by video encoder  120  on system bus  125 , since the same reference frame video data is used by both encoding engines. Note that subsequently the first video encoding engine encodes frame P 4  whilst the second video encoding engine encodes frame P 3 , both performing these encoding operations with reference to previously encoded frame P 2 . The first video encoding engine in video encoder  120  has the additional reconstruction components dQ  230 , IDCT  235  and DBL  240  to enable a reconstructed version of frame P 2  to be returned to reference frame storage  150 , such that it may be retrieved and stored in reference frame cache  135  when the video encoding engines are encoding frame P 3  and P 4 . It will be recognised that this technique for performing video encoding operations on a video stream with an increased frame rate will necessarily come at the price of a reduction in the video quality, for example (with reference to  FIG. 3A ) frame P 2  would be more accurately encoded if it were instead encoded with reference to the immediate preceding frame P 1 , however this would require the first encoding engine (encoding frame P 2 ) and the second encoding engine (encoding frame P 1 ) to perform their encoding operations with reference to two different reference frames (namely P 1  and I 0  respectively) which would significantly increase the bandwidth requirement demanded of system bus  125 . It has been found that the small reduction in quality can be an acceptable trade off, for example when encoding a video stream generated by video camera operating in slow motion mode. 
         [0043]    Returning to  FIG. 2 , note that an alternative configuration is also illustrated (shown by the dashed lines), wherein the video encoder  120  comprises a further video encoder. This further video encoder is configured like the second video encoder, and consequently comprises MC  205 C, ME  210 C, FDCT  215 C, Q  220 C and entropy encoder  225 C. Also, when this third video encoder is present, the DMA  200  comprises a further source buffer  245 . The presence of this third video encoding engine enables the video encoder  120  to perform video encoding on a video stream with three times the frame rate (as compared to twice the frame rate as illustrated in  FIG. 3A ). For the  FIG. 3B  example P-frames P 1 , P 2  and P 3  are encoded in parallel (label A) by the three encoding engines, with reference to a single reference frame Subsequently P-frames P 4 , P 5  and P 6  are encoded in parallel (label B) with reference to previously encoded P-frame P 3 . Note that when the set of frames A is being encoded P 3  will be encoded by the first video encoding engine, since this encoding engine has the additional reconstruction components and frame P 3  is used as the reference frame when the group of frames B (namely P 4 , P 5  and P 6 ) are encoded. 
         [0044]    It is also possible for the video encoding engines of video encoder  120  to perform their respective encoding operations with reference to more than one reference frame, as illustrated in  FIG. 3C . In this example the video encoder operates two encoding engines, as was the case in the example given in  FIG. 3A . Indeed the operation for the pair of frames A is identical to that illustrated with reference to  FIG. 3A . However, when reference frames P 3  and P 4  are encoded (B) each frame is encoded with reference to two preceding frames. Both frames P 3  and P 4  are encoded with reference to both I 0  and P 2 . The sharing of reference frames between the frames currently being encoded makes efficient use of reference frame cache  135  and allows for an increased frame rate to be handled, without significantly increasing the bandwidth requirement. 
         [0045]    The examples illustrated in  FIGS. 3A ,  3 B and  3 C only make use of P-frames, i.e. the video encoding engines of video encoder  120  are only performing mono-directional prediction encoding. In the examples illustrated in  FIGS. 4A and 4B  however, the video encoding engines of video encoder  120  also perform some bi-directional prediction encoding. In  FIG. 4A , the illustrated sequence of frames is PBBPBBP. Frame P 1  is a P-frame encoded with reference to at least one previous frame (not illustrated), whilst frames B 2  and B 3  are bi-directionally predicted frames each of which is predicted with reference to preceding frame P 1  and subsequent frame P 4 . This encoding pattern of course requires that the frames are not encoded in play back order, since both B 2  and B 3  need to refer to frame P 4  and similarly frames B 5  and B 6  need to refer to frame P 7 . For this reason the required encoding order for these frames will in fact be P 1 , P 4 , B 2 /B 3 , P 7 , B 5 /B 6  etc. The techniques of the present invention are applied in this example to the pair of frames B 2  and B 3  (and similarly B 5  and B 6 ), which are encoded in parallel to each other with reference to the same reference frames, namely P 1  and P 4  (or P 4  and P 7 ). 
         [0046]    A further variation is illustrated in  FIG. 4B  which shows the sequence of frames PBPBPBP. In this case the parallel encoding process may be carried out on B 2  and P 3  (pair A). However, this configuration presents an additional component of complexity, since B 2  makes reference to P 3 , which is encoded in parallel with B 2 . For this reason in such an example it is necessary to configure the parallel encoding engines to operate slightly offset from one another, specifically that the encoding of P 3  is performed sufficiently in advance of B 2 , such that the reconstructed video data from P 3  is available when the encoding of B 2  requires it. Although this configuration will hence require greater bandwidth, the benefit resulting in sharing reference frames may nevertheless outweigh this. 
         [0047]      FIG. 5  schematically illustrates a series of steps taking in one embodiment. At step  300 , reference frame video data is retrieved from a reference frame storage in system memory and at step  305  this reference frame video data is cached in the reference frame cache of the video encoder. The following steps are then performed in parallel with one another, namely steps  310  and  315 , where first and second source frame blocks are retrieved from the FIFO in memory and stored in their respective source buffers in the video encoder, and steps  320  and  325 , where these first and second source frame blocks are encoded by their respective encoding engines with reference to the same reference frame video data cached in the reference frame cache in the video encoder. The parallel steps recombine at the next step, step  330 , where it is determined if further reference frame video data is required to continue encoding. If it is not, then the flow returns to parallel steps  310  and  315  to retrieve further source frame blocks for encoding. However if further reference frame data is required, then the flow returns to step  300  and that reference frame video data is retrieved and then cached. 
         [0048]    Hence, according to the techniques of the present invention video encoding may be performed such that a higher frame rate may be handled, without significantly increasing the bandwidth required to pass the necessary video data around in the video system. 
         [0049]    Although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various changes and modifications can be effected therein by one skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims.