Abstract:
An apparatus for adjusting a first signal with respect to a second signal includes: (a) A first converter receiving the first signal and employing n first converting elements for digitally converting the first signal to at least one first signal element. (b) A second converter coupled with an output, receiving the second signal and employing n second converting elements for digitally converting the second signal to a second representative signal presented at the output. (c) An adjusting element coupled with each of selected of the first converting elements. Each adjusting element is coupled with the output and cooperates with the connected selected element to present a corrected signal element to the output. The output presents an aggregate output signal including contributions from the second representative signal and each corrected signal element. Adjusting is effected by altering at least one corrected first signal element presented to the output.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   The present application is related to U.S. patent application Ser. No. 11/502,822 entitled “APPARATUS AND METHOD FOR COMPENSATING CHANGE IN A TEMPERATURE ASSOCIATED WITH A HOST DEVICE,” filed Aug. 10, 2006, which is assigned to the current assignee hereof. 
   TECHNICAL FIELD 
   The invention relates generally to current generation and, more particularly, to generating a temperature dependent current with high accuracy. 
   BACKGROUND 
   To reduce temperature drift in an analog circuit, a temperature dependent bias current I(T) may be used. The bias current I(T) may be generated from a PTAT or Proportional To Absolute Temperature current digital-to-analog converter or DAC coupled to a CTAT or Complementary To Absolute Temperature current DAC. The CTAT current is subtracted from the PTAT current, or vice versa, to generate the desired bias current I(T). The resulting I(T) is injected into a sensitive node of the circuit to be compensated. 
   Accurate control of absolute value of bias current I(T) at 0 is desirable because it defines the accuracy of the voltage in the sensitive node of the circuit into which the correcting current is injected. This absolute value of bias current I(T) is limited by the matching and resolution of the network of trimmable current sources providing bias current I(T). Providing such a network of trimmable current sources generally require high chip areas and significant power consumption. 
   SUMMARY 
   An apparatus for adjusting a first signal with respect to a second signal includes: (a) A first converter receiving the first signal and employing n first converting elements for digitally converting the first signal to at least one first signal element. (b) A second converter coupled with an output, receiving the second signal and employing n second converting elements for digitally converting the second signal to a second representative signal presented at the output. (c) An adjusting element coupled with each of selected of the first converting elements. Each adjusting element is coupled with the output and cooperates with the coupled selected element to present a corrected signal element to the output. The output presents an aggregate output signal including contributions from the second representative signal and each corrected signal element. Adjusting is effected by altering at least one corrected first signal element presented to the output. 
   A method for adjusting a first electrical signal with respect to a second electrical signal; the method includes the steps of: (a) in no particular order: (1) providing a first converting unit configured for receiving the first electrical signal; the first converting unit having a plurality of n selectively switchable first binary converting elements; and (2) providing a second converting unit configured for receiving the second electrical signal; the second converting unit having a plurality of n selectively switchable second binary converting elements; the second converting unit being coupled with an output locus; (b) providing a respective adjusting element coupled with each of a respective selected element of a plurality of selected elements of the plurality of the n switchable first binary converting elements; each respective adjusting element being coupled with the output locus; (c) in no particular order: (1) operating the plurality of n selectively switchable first binary converting elements to effect digital conversion of the first electrical signal to at least one first representative signal element representing the first electrical signal; (2) operating the plurality of n selectively switchable second binary converting elements for effecting digital conversion of the second electrical signal to a second representative signal representing the second electrical signal; the second converting unit presenting the second representative signal to the output locus; and (3) operating each respective adjusting element in cooperation with the respective coupled selected element to present a respective corrected first representative signal element to the output locus; the output locus presenting an aggregate output signal including contributions from the second representative signal and each respective corrected first representative signal element presented to the output locus; and (d) effecting the adjusting by altering at least one corrected first representative signal element presented to the output locus. 
   It is, therefore, an object of the present invention to provide an apparatus and method for adjusting a first electrical signal with respect to a second electrical signal that can present high resolution for a resulting signal, such as a bias current I(T) for injection as a compensating current into a host device. 
   The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
       FIGS. 1 and 2  are a diagram illustrating examples of conventional circuit; 
       FIG. 3  is a graphical depicting the generation of a temperature dependent bias current for  FIGS. 1  and/or  2 ; 
       FIG. 4  is a diagram illustrating an example of a conventional temperature dependent bias current generator; 
       FIG. 5-7  are a diagrams of examples of circuits in accordance with a preferred embodiment of the present invention; 
   

   DETAILED DESCRIPTION 
   Refer now to the drawings wherein depicted elements are, for the sake of clarity, not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views. 
   Referring to  FIG. 1  of the drawings a conventional circuit  10  is shown. Circuit  10  includes an NMOS transistors M 1  and M 2 , PMOS transistors M 3  and M 4 , switches S 1  and S 2 , and current sources  12 ,  20 , and  22 . Transistors M 1  and M 2  are each coupled between the operational amplifier (not shown in  FIG. 1 ) and a current source  12  (which provides a current I b2 ). Transistor M 3  is coupled between a voltage source V S  and a line  16 , and transistor M 4  is coupled between voltage source V S  and a line  18 . A gating signal V g1  gates transistors M 1  and M 3 , while gating voltage V g2  gates transistors M 2  and M 4 . Switch S 1  selectively couples one of lines  16  and  18  with current source  20  to impose a zero current bias at a predetermined temperature (0 TC). Switch S 2  selectively couples one of lines  16  and  18  with current source  22 , where current source  22  is employed to inject a bias current I(T) into one of a sensitive drain in circuit  10  to reduce temperature drift in circuit  10 . Additionally, current source  22  is generally comprised of PTAT or Proportional To Absolute Temperature current source  30  (which provides current I PTAT ) and CTAT or Complementary To Absolute Temperature current source  32  (which provides a current I CTAT ). Preferably, currents I PTAT  and I CTAT  are subtracted from one another to present a resulting bias current I(T), which is shown in  FIG. 3 . 
   Turning to  FIG. 2 , a conventional bandgap reference circuit  40  is shown. Circuit  40  includes an amplifier  42 , resistors  50 ,  54 ,  57 , and  58 , and transistors  52  and  56 . Amplifier has input terminals  44  and  46  an output terminal  48 . Terminal  44  is coupled to resistor  50  (which receives reference voltage V REF ) and to a diode-connected transistor  52  (which is coupled to resistor  57 ). Terminal  46  is coupled to resistor  54  (which receives reference voltage V REF ) and to diode-connected transistor  56  (which is coupled to resistors  57  and  58 ). A bias current I(T) is injected into bandgap reference circuit  40  by PTAT current source  30  and CTAT current source  32 , where currents I PTAT  and I CTAT  are subtracted from one another to present a resulting bias current I(T) that is shown in  FIG. 3 . 
   Turning to  FIG. 4 , an example of current source  22  can be seen in greater detail. Current source  22  includes a PTAT slope adjusting unit  92 , a CTAT slope adjusting unit  94 , and a position adjusting unit  96 . PTAT slope adjusting unit  92  generally comprises a digital-to-analog converter or DAC having NMOS transistors N 1  through N 6  arranged to establish a series of switched current mirrors that cooperate to generate a binary weighted fraction of bias current I PTAT  with transistors N 2  through N 6  operating as current sources related with respective bit positions of a digital representation of current I PTAT  (2 4  through 2 0 , respectively) Transistors N 2  through N 6  are selectively engaged using switch network  93 , and transistors C 2  through C 6  are coupled to transistors N 2  through N 6 . CTAT slope adjusting unit  94  generally comprises a DAC having NMOS transistors N 7  through N 12  arranged to establish a series of switched current mirrors that cooperate to generate a binary weighted fraction of bias current I CTAT  with transistors N 8  through N 12  operating as current sources related with respective bit positions of a digital representation of current I CTAT  (2 4  through 2 0 , respectively) Transistors N 7  through N 12  are selectively engaged using switch network  95 , and transistors C 2  through C 6  are coupled to transistors N 2  through N 6 . Additionally, current mirroring for units  92  and  94  may be established in ratios RP and RC established by relative aspect (width/length) ratios among transistors N 2  through N 6  and N 7  through N 12 , respectively, and adding transistors C 2  through C 6  and transistors C 8  through C 12  are optional design features that is a common design practice. Moreover, in operation, the same respective switch control signals are applied to switch networks  93  and  95 . That is, the same respective switch control signal is applied to activate or deactivate switches having the same respective position in switch networks  93  and  95  together. 
   Position adjusting unit  96  also generally comprises a DAC. DAC includes PMOS transistors P 1  through P 8  and switch network  97 . Transistors P 1  and P 2  generally comprise current mirror  100 . Current mirror  100  performs the subtraction the PTAT current I PTAT  and CTAT current I CTAT . Position adjusting unit  96  senses the weighted algebraic sum of signals selected by closing switches from switch networks  93  and  95 . Transistors P 3  through P 8  establish a series of switched current mirrors that cooperate to generate a binary weighted fraction of subtraction of the PTAT current I PTAT  and the CTAT current I CTAT . Transistors P 3  through P 8  are selectively engaged using switch network  97 . 
   Ignoring transistors P 3  through P 8  for the moment and assuming that transistors P 1  and P 2  have the same aspect ration, the output current I(T) would be:
 
 I ( T )= I   PTAT ( T )·(2 ·S   2 +2 −1   ·S   3 +2 −2   ·S   4 +2 −3   ·S   5 +2 −4   ·S   6 )− I   CTAT ( T )·(2 0   ·S   8 +2 −1   ·S   9 +2 −2   ·S   10 +2 −3   ·S   11 +2 −4   ·S   12 ),  (1)
 
   where S 2 =S 8 ; S 3 =S 9 ; S 4 =S 10 ; S 5 =S 11 ; S 6 =S 12 . The coefficients S 2  through S 12  are Boolean values (“0” or “1”) depending on the switch state of each of respective switches of switch networks  93  and  95 . If the value of a coefficient S X  in Equation [1] is “1”, then switch S X  is closed (i.e., conducting) and the corresponding current segment contributes both a PTAT and a CTAT current to current I(T) (because S 2 =S 8 ; S 3 =S 9 ; S 4 =S 10 ; S 5 =S 11 ; S 6 =S 12 ). If the value of a coefficient S X  in Equation [1] is “0”, then switch S X  is open (i.e., nonconducting) and the corresponding current segment contributes no current to current I(T). A desired design goal is to force current I(T) to a zero value at a predetermined temperature T 0 . In Equation [1], this condition is true if the condition I PTAT (T 0 )=I CTAT (T 0 ) holds, as occurs for example at temperature T 0  in  FIG. 3 . The desired result may be achieved by individually trimming current source  30  and current source  32  in a package final test at temperature T 0 . 
   In a typical implementation, current source  30  may adjusted (e.g., by trimming) in such a way that I(T 0 )=0. Temperature dependent current generator  90  permits adjustment of contribution by PTAT current I PTAT  to current I(T) using position adjust unit  96 . The overall output current I(T) appearing is:
 
 I ( T )= I   PTAT ( T )· x   —   pos ·(2 0   ·S   2 +2 −1   ·S   3 +2 −2   ·S   4 +2 −3   ·S   5 +2 −4   ·S   6 )− I   CTAT ( T )·(2 0   ·S   8 +2 −1   ·S   9 +2 −2   ·S   10 +2 −3   +S   11 +2 −4   ·S   12 )  (2)
 
   where S 2 =S 8 ; S 3 =S 9 ; S 4 =S 10 ; S 5 =S 11 ; S 6 =S 12 ; and x_pos=(2 −2 +2 −1 ·S 14 +2 −2 ·S 15 +2 −3 ·S 16 +2 −4 ·S 17 +2 −6 ·S 19 ). Equation [2] illustrates that I(T 0 )=0 can be achieved even if I PTAT (T 0 )≠I CTAT (T 0 ) by properly selecting coefficients S 14  through S 19 . This selection of coefficients S 14  through S 19  may be effected during a “test at first temperature T 0 ” procedure. After the first test, a second test may be conducted at a significantly different temperature T 1  (e.g. nominal or expected operating temperature of the device being compensated. Given test results at two temperatures, an actual temperature drift may be estimated. By way of example and not by way of limitation, in a bandgap device temperature drift may be determined by tracking a reference output voltage. 
   Temperature drift may be compensated by choosing a binary weighted I(T) sum at the output of temperature dependent current generator  90  that is appropriate to shift the reference output voltage to a target value and injecting this I(T) into the core circuit of the device being compensated. This may be effected using temperature dependent generating circuit  90  by a unique value for the five data input bits at switched in switch networks  93  and  95 . In terms of Equation [2], coefficients S 2  through S 6  and S 8  through S 12  are chosen to adjust I(T 1 ) to the desired value. The second test described above may be independent from the first test, so there is no requirement for tracking of die identification or tracking previous test data. Test implementation is therefore relatively cheap and easy. In single ended architectures (e.g., bandgap devices), bias current I(T) is provided also with the opposite temperature coefficient. For differential architectures, such as operational amplifiers, one temperature coefficient (e.g. positive) for bias current I(T) is likely sufficient because the compensating bias current I(T) may be injected on either side of the differential path to correct both positive and negative residual temperature coefficients. 
   Temperature dependent current generator  90 , though, has shortcomings. PTAT and CTAT current sources  30  and  32  and transistors N 1  through N 12  are subject to mismatch variations during manufacture. This mismatch likelihood is not included in Equation [2]. A result of such mismatches is a reduction in absolute accuracy of bias current I(T). The variations can differ among any of transistors N 2  through N 6  and N 8  through N 12 , so that accuracy of the binary digital representation of bias current I(T) presented is code dependent (i.e., depends on values of coefficients S 2  through S 6  and S 8  through S 12 ). By way of example and not by way of limitation, transistor N 2  may have a V t  (threshold voltage) mismatch with respect to V t  of transistor N 1 . Such a mismatch can result in a drain current I D  having a mismatch current Ierr 2  between transistors N 1  and N 2 . This mismatch between transistors N 1  and N 2  may be expressed as:
 
 I   D ( N 2)= I   D ( N 1)·(1 +Ierr   2 )  (3)
 
   Mismatch current Ierr 2  can be positive or negative and strongly depends on technology and parameterization of transistors N 1  and N 2 . By way of further example and not by way of limitation, a similar condition may exist with respect to transistors N 7  and N 8 , which is as follows
 
 I   D ( N 8)= I   D ( N 7)·(1 +Ierr   8 )  (4)
 
   By way of still further example and not by way of limitation, transistor N 3  can have a mismatch voltage V t  with respect to transistor N 1  which can be just opposite to the mismatch with respect to transistors N 1  and N 2 . This may occur because statistical mismatch among transistors is uncorrelated as follows:
 
 I   D ( N 3)= I   D ( N 1)·(1 +Ierr   3 )  (5)
 
Mismatch current Ierr 3  can be positive or negative, and in a worst case Ierr 3 =−Ierr 2 . One skilled in the art of transistor circuit design may recognize that similar relations may hold for other transistors N 4 , N 5 , N 6 , and N 9  through N 12  with all errors uncorrelated. The corrected Equation [2] for I(T) would be:
 
 I ( T )= I   PTAT ( T )· x   —   pos ·(2 0   ·S   2 ·(1 +Ierr 2)+2 −1   ·S   3 ·(1 +Ierr 3)+2 −2   ·S   4 ·(1 +Ierr 4)+2 −3   ·S   5 ·(1 +Ierr 5)+2 −4   ·S   6 ·(1 +Ierr 6)) −I   CTAT ( T )·(2 0   ·S   8 ·(1 +Ierr 8)+2 −1   ·S   9 ·(1 +Ierr 9)+2 −2   ·S   10 ·(1 +Ierr 10)+2 −3   ·S   11 ·(1 +Ierr 11)+2 −4   ·S   12 ·(1 +Ierr 12))  (6)
 
Because all mismatches currents Ierr x  are uncorrelated, all of the mismatch coefficients may have different magnitudes and cannot be corrected simultaneously by one set of coefficients S 14  through S 19  in x_pos. That means the final value of bias current at temperature T 0 , I(T 0 ), is code-dependent (i.e. depends on the values of coefficients S 2  through S 6 /S 8  through S 12 ).
 
   Turning now to  FIG. 5 , a current generator  110  in accordance with a preferred embodiment of the present invention can be seen. Current generator  110  generally a PTAT slope adjusting unit  92 , a CTAT slope adjusting unit  94 , and a position adjusting unit  116 . As can be seen, unit  92  and  94  of  FIG. 5  have the same general structure as the units  92  and  94  of  FIG. 4 . Position adjusting unit  116 , though, is different from unit  96 . Unit  116  generally comprises position adjusting arrays  120 ,  122 ,  124 ,  126 , and  128 . Each of position adjusting arrays  120 ,  122 ,  124 ,  126 , and  128  adjusts a respective individual bit output of PTAT slope adjusting unit  92 . Each of the position adjusting arrays  120 ,  122 ,  124 ,  126 , and  128  corresponds to a switch in switch network  93 . However, details are illustrated only for position adjusting arrays  120 ,  122 , and  128  for the sake of simplicity 
   Position adjusting array  120  generally corresponds to the first switch of switch network  93 . Array  120  generally comprises a DAC having PMOS transistors P 11  through P 18  and switch network  130 . Transistors P 11  and P 12  establish a current mirror  121 . Current mirror  121  performs current mirroring of output from transistor N 2  through the first switch of switch network  93 . Position adjusting array  120  presents a representation of current contribution from transistor N 2  in a contributing current signal I OUT1 , and transistors P 13  through P 18  present current contributions representing the 2 4  through 2 −1  bit positions, respectively, of a digital representation of current contribution from transistor N 2 . 
   Position adjusting array  122  generally corresponds to the second switch of switch network  93 . Array  122  generally comprises a DAC having PMOS transistors P 21  through P 27  and switch network  132 . Transistors P 21  and P 22  establish a current mirror  123 . Current mirror  123  performs current mirroring of output from transistor N 3  through the second switch of switch network  93 . Position adjusting array  122  presents a representation of current contribution from transistor N 3  in a contributing current signal I OUT2 , and transistors P 23  through P 27  present a current contributions representing the 2 3  through 2 −1  bit positions, respectively, of a digital representation of current contribution from transistor N 3 . 
   Position adjusting array  124  presents a representation of current contribution from transistor N 4  in a contributing current signal. Position adjusting array  126  presents a representation of current contribution from transistor N 5  in a contributing current signal. Position adjusting arrays  124  and  126  are preferably configured similar to position arrays  120  and  122  providing an array of transistors, each of which may be employed for contributing a current contribution relating to a respective bit position of a digital representation from PTAT slope adjusting unit  93 . 
   Position adjusting array  128  generally corresponds to the last switch of switch network  93 , which is the shown as the fifth switch in the example of  FIG. 5 ; however, it should be noted that more or less than five can be employed. Array  128  generally comprises a DAC having PMOS transistors P 51 , through P 55 . Transistors P 51  and P 52  establish a current mirror  129 . Current mirror  129  performs current mirroring of output from transistor N 6  through the last switch of switch network  93 . Position adjusting array  128  presents a representation of current contribution from transistor N 6  in a contributing current signal I OUT5 , and transistor P 53  through P 55  presents current contribution representing the 2 1  through 2 −1  bit position of a digital representation of current contribution from transistor N 6 . 
   Provision of a plurality of position adjusting arrays  120  through  128  coupled to switch network  93  permits separate balancing of the current contribution of each individual PTAT-CTAT transistor pair N 2 -N 8 , N 3 -N 9 , N 4 -N 10 , N 5 -N 11 , and N 6 -N 12 . Resolution of the various position adjust arrays  120  through  128  can be reduced as the current of a respective transistor pair Nx-Ny decreases with larger x-y (e.g., current in transistor pair N 3 -N 9  is smaller than current in transistor pair N 2 -N 8 ). This is indicated by labeling position adjust array  120  as MSB or Most Significant Bit, labeling position adjust array  122  as MSB−1 or Most Significant Bit minus 1, labeling position adjust array  124  as MSB−1 or Most Significant Bit minus 2, labeling position adjust array  126  as MSB−3 or Most Significant Bit minus 3, and labeling position adjust array  128  as LSB or Least Significant Bit. Thus, the corrected Equation [2] for I(T) as applied to temperature dependent current generator  110  is as follows:
 
 I ( T )= I   PTAT ( T )·(2 0   ·S   2   ·x   —   pos   2 ·(1 +Ierr 2)+2 −1   ·S   3   ·x   —   pos   3 ·(1 +Ierr 3)+2 −2   ·S   4   ·x   —   pos   4 ·(1 +Ierr 4)+2 −3   ·S   5   ·x   —   pos   5 ·(1 +Ierr 5)+2 −4   ·S   6   x   —   pos   6 ·(1 +Ierr 6))− I   CTAT ( T )·(2 0   ·S   8 ·(1 +Ierr 8)+2 −1   ·S   9 ·(1 +Ierr 9)+2 −2   ·S   10 ·(1 +Ierr 10)+2 −3   ·S   11 ·(1 +Ierr 11)+2 −4   ·S   12 ·(1 +Ierr 12))  (7)
 
where S 2 =S 8 ; S 3 =S 9 ; S 4 =S 10 ; S 5 =S 11 ; S 6 =S 12 ; and x_pos z =(2 −2 +2 −1 ·SP z1 +2 −2 ·SP z2 +2 −3 ·SP z3 +2 −4 ·SP z4 +2 −5 ·SP z5 +2 −6 ·SP z6 ). SP zn  also indicates a Boolean coefficient for a switch coupled with a PMOS transistor PZN, such as a coefficient for switch S 13  coupled with PMOS transistor P 13  in position adjust array  122 . From Equation [7] one may observe that each individual mismatch current Ierrn can be compensated by an individual trimming network x_pos z . For determination of appropriate coefficients for each respective trimming network x_pos z  one may set all other switches S j , with j≠z, to a nonconducting state and sweep through all coefficient combinations SP iy  until the output value approaches desired value (e.g., a desired bandgap output). Additionally, a gate bias GATE BIAS may optionally be applied to the gates of transistors of unit  116 .
 
   Turning to  FIG. 6 , current generator  310  can be seen in greater detail. Current generator has a similar configuration to current generator  110 , but some there are some differences between unit  316  and  116 . Position adjusting unit  316  generally comprises adjusting arrays  320 ,  321 ,  322 ,  323 ,  324 ,  326 , and  328 . Gate bias voltages BIAS 1  and BIAS 2  are generally provided from separate or external voltage generators. Bias voltage BIAS 1  biases transistors P 13  through P 17  and P 23  through P 26 , and bias voltage BIAS 2  biases transistors P 18  through P 110 , P 27 , through P 29 , and P 53  through P 55 . Multiple externally generated gate voltages may be used to provide cascaded position adjusting DAC arrays with overlapping dynamic ranges. By way of example and not by way of limitation, in  FIG. 6 , smaller currents from position adjusting arrays based on voltage BIAS 2  are used to interpolate between current values generated by the position adjusting arrays based on voltage BIAS 1 . 
   Using different gate bias voltages BIAS 1  and BIAS 2  with transistors addressing overlapping bit contributions to output currents permits interpolation of contributing currents I(T) with overlapping dynamic range. As shown, transistors P 18  and P 27  of arrays  120  and  122  are replaced with arrays  312  and  323  so that transistors P 19 , P 110 , and P 111  in position adjustment array  321  overlap current contributions by transistors P 15 , P 16 , and P 17  in position adjustment array  320  and transistors P 28 , P 29 , and P 30  in position adjustment array  323  overlap current contributions by transistors P 24 , P 25 , and P 26  in position adjustment array  322 . Switch arrays  130  and  132  are also replaced by switch netword  330  and  332 , respectively. By providing different gate bias voltages BIAS 1  and BIAS 2  to position adjustment arrays  320 ,  321 ,  322 , and  323  interpolation may be effected regarding current contributions representing the 2 2  through 2 0  bit position of a digital representation of current contribution from transistors N 2  and N 3 . Moreover, details of construction relation to position adjustment arrays  324  and  326  are not illustrated in  FIG. 6 . However, arrays  324  and  326 , preferably, have similar constructions to arrays  320 / 321  and  322 / 323 . 
   Turning to  FIG. 7 , current generator  410  can be seen. Current generator  410  is similar to current generator  310 ; however, there are some differences between unit  316  and  416 . While the construction of switching networks  430 ,  432 , and  434  (and corresponding transistors) is largely the same as switching networks  330 ,  332 , and  334  (and corresponding transistors), respectively. Each of arrays  422  and  428  lacks a current mirror. Instead current mirror (comprised of transistors P 11  and P 12 ) is coupled to each switch in switch network  93 . 
   Having thus described the present invention by reference to certain of its preferred embodiments, it is noted that the embodiments disclosed are illustrative rather than limiting in nature and that a wide range of variations, modifications, changes, and substitutions are contemplated in the foregoing disclosure and, in some instances, some features of the present invention may be employed without a corresponding use of the other features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.