Abstract:
A new detection system that improves the detection signal-to-noise (SNR) ratio of a digital communication system suffering from intersymbol interference is described. The detection system utilizes the sample power contained in the intersymbol interference created by the dispersive nature of the communication channel. Significant SNR advantages over more commonly used decision-feedback equalizers (DFE) and linear equalizers are realized.

Description:
BACKGROUND 
     1. Field of the Invention 
     This invention relates to improving the signal-to-noise ratio of a digital communication system suffering from intersymbol interference. 
     2. Background 
     The dramatic increase in desktop computing power driven by intranet-based operations and the increased demand for time-sensitive delivery between users has spurred development of high speed Ethernet LANs. 100BASE-TX Ethernet, using existing Category 5 copper wire, and the newly developing 1000BASE-T Ethernet for Gigabit/s transfer of data over Category 5 copper wire require new techniques in high speed symbol processing. In addition, high speed processing of data is in demand for use with existing switching boards which may currently be required to process data at a rate of 1000 Mb/s per port. Gigabit per second transfer can be accomplished utilizing four twisted pairs and a 125 megasymbol/s transfer rate on each pair where each symbol represents two bits. 
     Physically, data is transferred using a set of voltages where each voltage represents one or more bits of data. Each voltage in the set is referred to as a symbol and the whole set of voltages is referred to as a symbol alphabet. 
     One system of transferring data at high rates is Non Return to Zero (NRZ) signaling. In NRZ, the symbol alphabet {A} is {-1, +1}. A logical &#34;1&#34; is transmitted as a positive voltage while a logical &#34;0&#34; is transmitted as a negative voltage. At 125 M symbols/s, the pulse width of each symbol (the positive or negative voltage) is 8 ns. 
     An alternative modulation method for high speed symbol transfer is MLT3 and involves a three level system. (See American National Standard Information system, Fibre Distributed Data Interface (FDDI)--Part: Token Ring Twisted Pair Physical Layer Medium Dependent (TP-PMD), ANSI X3.263:199X). The symbol alphabet for MLT3 is {A}={-1, 0, +1}. In MLT3 transmission, a logical 1 is transmitted by either a -1 or a +1 while a logic 0 is transmitted as a 0. A transmission of two consecutive logic &#34;1&#34;s does not require the system to pass through zero in the transition. A transmission of the logical sequence (&#34;1&#34;, &#34;0&#34;, &#34;1&#34;) would result in transmission of the symbols (+1, 0, -1) or (-1, 0, +1) depending on the symbols transmitted prior to this sequence. If the symbol transmitted immediately prior to the sequence was a +1, then the symbols (+1, 0, -1) are transmitted. If the symbol transmitted before this sequence was a -1, then the symbols (-1, 0, +1) are transmitted. If the symbol transmitted immediately before this sequence was a 0, then the first symbol of the sequence transmitted will be a +1 if the previous logical &#34;1&#34; was transmitted as a -1 and will be a -1 if the previous logical &#34;1&#34; was transmitted as a +1. 
     The detection system in the MLT3 standard, however, needs to distinguish between 3 levels, instead of two levels in a more typical two level system. The signal to noise ratio required to achieve a particular bit error rate is higher for MLT3 signaling than for two level systems. The advantage of the MLT3 system, however, is that the energy spectrum of the emitted radiation from the MLT3 system is concentrated at lower frequencies and therefore more easily meets FCC radiation emission standards for transmission over twisted pair cables. Other communication systems may use a symbol alphabet having more than two voltage levels in the physical layer in order to transmit multiple bits of data using each individual symbol. 
     A block diagram of a typical digital communication transmission system is illustrated in FIG. 1A. In FIG. 1A, the transmitted data is represented by the symbol sequence {a k  }. The transmitted symbols in the sequence {a k  } are members of the symbol alphabet {A}. In the case of two level NRZ signaling, the symbol alphabet {A} is given by {-1, +1}. The index k represents the time index for that symbol, i.e. at sample time k, the symbol being transmitted is given by a k . The channel response is represented by the channel function f(z). The signal, x k , is summed with the noise sample n k  to represent the random noise on the transmission line. The signal, suffering from both the channel distortion and the random noise, is input to the detector. 
     For the sake of simplicity, a baseband transmission system is assumed, although the techniques shown are easily extended to a passband transmission system. (See E. A. LEE AND D. G. MESSERCHMITT, DIGITAL COMMUNICATIONS (1988)) It is also assumed that the channel model includes the effect of transmit and receive filtering. In addition, the transmission channel is assumed to be linear in that two overlapping signals simply add as a linear superposition. Therefore, the channel function polynomial can be defined as 
     
         f(Z)=f.sub.0 +f.sub.1 Z.sup.-1 +f.sub.2 Z.sup.-2 + . . . +f.sub.N Z.sup.-N,(1) 
    
     where f 0 , . . . , f j , . . . , f N  are the polynomial coefficients representing the dispersed component of the (k-j)th symbol present in the a k  th symbol and N is a cut-off integer such that f j  for j&gt;N is negligible. The polynomial f(Z) represents the Z-transformation of the frequency response of the transmission channel. (Z -1  represents a one period delay) See A. V. OPPENHEIM &amp; R. W. SCHAFER, DISCRETE-TIME SIGNAL PROCESSING 1989. 
     The noiseless output of the channel at sample time k is then given by 
     
         x.sub.k =f.sub.0 *a.sub.k +f.sub.1 *a.sub.k-1 + . . . f.sub.N *a.sub.k-N,(2) 
    
     where, without loss of generality, fo can be assumed to be 1. Thus, the channel output signal at time k depends, not only on transmitted data at time k, but past values of the transmitted data. This effect is known as &#34;intersymbol interference&#34; (ISI). See LEE &amp; MESSERSCHMITT. 
     Intersymbol interference is a result of the dispersive nature of the communication channel. The IEEE LAN standards require that systems be capable of transmitting and receiving data through at least a 100 meter cable. FIG. 1C shows a transmission bit stream with the effects of dispersion. FIG. 1D shows the power spectrum of the dispersed pulse with frequency. In a 100 meter cable, the signal strength at the Nyquist frequency of 62.5 Mhz is reduced nearly 20 db at the receiving end of the cable. Given this dispersion, a single symbol may affect symbols throughout the wire. 
     The noise element of the signal is represented by the sequence {n k  }. Therefore, the noisy output of the channel is given by 
     
         y.sub.k =x.sub.k +n.sub.k,                                 (3) 
    
     where the noise samples {n k  } are assumed to be independent and identically distributed Gaussian random variables (see LEE &amp; MESSERSCHMITT) with variance equal to σ 2 . 
     Most state-of-the art communication systems use two types of detectors for combating the ISI described by equation (2). These two detectors, Linear Equalization and Decision Feedback Equalization, are shown in FIG. 1B. 
     A liner equalizer having m+1 multipliers is illustrated in FIG. 2. In FIG. 2, the symbol Y k  is inputted to a delay array 10 having delays (D 1  through D m ) which, at each stage, delay the symbol by one time period. A set of multipliers 20 having multipliers M 0  through M m  multiply each of the m+1 symbols in the array of delays D 1  through D m  by a corresponding coefficient C 0  through C m . The adder 30 adds together the outputs of multipliers M 0  -M m  to obtain the resulting signal 
     
         a.sub.k &#39;=C.sub.0 y.sub.k +C.sub.1 y.sub.k-1 + . . . +C.sub.m y.sub.k-m.(4) 
    
     The signal a k  &#39; from the linear equalizer is inputted to decider 40 which decides on the output symbol a k . The output symbol a k  is the symbol from the symbol alphabet {A} which best approximates the input signal a k  &#39;. 
     The multiplier coefficients, C 0  through C m , define a transfer function T given by 
     
         T=C.sub.0 +C.sub.1 Z.sup.-1 + . . . +C.sub.m Z.sup.-m.     (5) 
    
     The coefficients C 0  through C m  may be chosen by an intelligent algorithm in an adaptive chip in order optimize the functioning of the equalizer. A zero-forcing linear equalizer (ZFLE) has a transfer function T given by the inverse of the frequency response of the channel. A minimum mean squared error based linear equalizer (MMSE-LE) optimizes the mean squared error between the transmitted data and the detected data, and hence finds a compromise between the un-canceled ISI at the output terminal of the equalizer and the noise variance. 
     The primary disadvantage of a linear equalizer is that, while removing the ISI due to the channel, it also causes the noise to be enhanced. This is especially true in a channel like the twisted copper pair channel, where the frequency response of the channel has significant attenuation across the transmitted signal bandwidth. Hence, in twisted-pair channels (which are commonly used in applications such as 10/100/1000BASE-TX Ethernet and digital subscriber loops), the noise {n k  } may be enhanced by the linear equalizer detector, reducing noise immunity. 
     FIG. 3 illustrates a Decision Feedback Equalizer (DFE) with N ff  multipliers in the feed-forward filter and N fb  multipliers in the feedback filter. The input signal y k  is inputted to the feed-forward filter 100. The resulting signal is added with the resulting signal from the feed-back filter 200 in adder 300. The added signal is inputted to circuit 400 which determines the output a k  symbol of the equalizer. 
     In feed-forward filter 100, the input signal y k  is inputted to a feed-forward delay array having delays D 1   ff  through D ff-1   ff . Each delay delays the signal by one period so that the delay array 101 stores N ff  -1 past input signals. Each of the stored signals is multiplied by a corresponding coefficient C 0  through C Nff-1  by multipliers M 0   ff  through M nff-1   ff . The results of each of the multipliers M 0   ff  through M nff-1   ff  are added together in adder 103 so that the signal inputted to adder 300 on line 301 is given by 
     
         a.sub.k &#39;=C.sub.0 y.sub.k +C.sub.1 y.sub.k-1 + . . . +C.sub.Nff-1 y.sub.k-Nff+1.                                            (6) 
    
     The feed-back filter 200 inputs the output symbol a k  to a feed-back delay array 201 having delays D 0   fb  through D Nfb-1   fb . The feed-back delay array 201 stores N fb-1  past determined symbols, a k-Nfb+1  through a k-1 . The output symbols of the feed back delay array 201 are inputted to multipliers 202, M 0   fb  through M Nfb-1   fb  respectively. The resulting signals from multipliers 202 are added in adder 203 so that the input signal of adder 300 on line 302 is given by 
     
         a.sub.k &#34;=b.sub.0 a.sub.k-1 +b.sub.1 a.sub.k-2 +b.sub.Nfb-1 a.sub.k-Nfb+1.(7) 
    
     Adder 300 adds the input signal on line 301 with the negative of the input signal on line 302 to obtain a k  &#39;-a k  &#34; which is received by decider 400. Decider 400 decides on the output symbol a k . The output symbol a k  arrived at by decider 400 is the symbol in symbol alphabet {A} which most closely approximates the signal a k  &#39;-a k  &#34; at the input terminal of decider 400. 
     The DFE operates on the principle that if the past transmitted data is correctly detected, then the ISI effect of these past data symbols can be canceled from the current received signal prior to detection. For a zero-forcing DFE, the feed-forward finite impulse response filter (FF-FIR) transfer function is set to 1 (i.e., C 0  =1 and C 1  through C m  are 0), and the feedback FIR (FB-FIR) transfer function is given by [f(z)-1], f(z) being the channel function. 
     Since past detected data samples contain no noise, DFE does not suffer from noise enhancement. However, DFE suffers from error propagation. If one of the past detected symbols is incorrect, then the effects of that error propagate to more symbol decisions in the future. 
     In addition, the DFE has the disadvantage that the sample power contained in the dispersive power of the channel, and represented by the ISI coefficients, is discarded prior to detection of the current symbol and therefore wasted. More precisely, the system has information regarding the current transmitted data symbol in the prior received signals which DFE does not utilize. 
     Also, because the equalizer is a feedback equalizer, pipelining of the feedback filtering operation is not possible, unlike a linear equalizer whose operation can be pipelined. Yet another disadvantage of a DFE versus a linear equalizer is that a linear equalizer depends only on past input signals to the detector while a DFE depends on past output symbols. 
     SUMMARY OF THE INVENTION 
     In accordance with the invention, a new detector and new detection method is presented. The sequence detector estimates an entire sequence of transmitted data and makes use of most or all of the sample power in the ISI symbols. This leads to a significant improvement in the performance of the detector. The detector presented here applies equally well to the NRZ or MLT3 standards as well as any other standards that may be developed for transmitting symbols. 
     Many systems utilize analog signal processing techniques to remove the ISI from the system. According to this invention, a digital signal processor (DSP) is used The bulk of the noise element therefore comes from the error in the analog to digital converter. In that case, the noise element nk is added to the input signal x k  at the receiver end of the transmission wire. Digital processing has the advantage that digital chips require lower power and have greater stability than analog chips. 
     An algorithm, the Viterbi algorithm (See B. SKLAR, DIGITAL COMMUNICATIONS, FUNDAMENTALS AND APPLICATIONS (1988)), is used in the sequence detector to track the amount of ISI from previous symbols which appear in the signal currently being detected. A minimization procedure is utilized which calculates the most likely set of symbols which gives rise to the currently observed signal. 
     In another embodiment, the channel is linearly equalized to obtain a shortened impulse response, g(Z), of length L≦N. The reduced sequential detector performs sequence detection assuming that the overall equalized channel is given by g(Z). In yet another embodiment, linear equalization and DFE filtering are added to the detector system to simplify implementation. 
    
    
     DESCRIPTION OF THE FIGURES 
     FIG. 1A shows a typical digital communication system. 
     FIG. 1B shows the two common detection systems for combating ISI. 
     FIG. 1C shows dispersion across the transmission channel for one pulse. 
     FIG. 1D shows the pulse power as a function of frequency. 
     FIG. 2 shows a Linear Equalizer Implemented with an FIR Filter. 
     FIG. 3 shows a Decision Feedback Equalizer. 
     FIG. 4 shows a block diagram of the sequential detector for an example ISI channel. 
     FIG. 5 shows a trellis diagram for the example ISI channel of FIG. 4. 
     FIG. 6 shows a reduced sequential detector using a linear equalizer. 
     FIG. 7 shows a reduced sequential detector using linear equalization and Decision Feedback Sequence Equalization. 
     FIG. 8 shows a block diagram of a detector for ISI channel 1+g 1  z -1  +g 2  z -2 . 
     FIG. 9 shows a trellis diagram with N=1 appropriate for use with applications with three level signaling. 
     FIG. 10 shows a block diagram of a sequence equalizer with N=l and three level signaling. 
     FIG. 11 shows a trellis diagram for N=1 and 5 level signaling. 
     FIG. 12 shows a block diagram of a sequence equalizer with N=1 and five level signaling. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     In accordance with the present invention, FIG. 4 shows a block diagram of a sequence detector for the case {A}={-1, +1} and N=1, although the system is generalizable to larger alphabets and more ISI interference (A&gt;2 and N&gt;1). The detector includes a Branch Metric Generator, an Add-Compare-Select (ACS) unit, Traceback Circuitry, a Last-In-First-Out (LIFO) buffer, and a starting state determiner. 
     The ISI in the sequence equalizer displayed in FIG. 4 is caused by just one previously transmitted symbol. Thus, 
     
         y.sub.k =a.sub.k +f.sub.1 a.sub.k-1 +n.sub.k.              (8) 
    
     The sequence detector estimates the transmitted data sequence {a k  } from the sequence of received signals {y k  }. 
     The state of the detector, S k , is defined as the past data symbol estimates. In general, a system with a symbol alphabet having A symbols and which suffers intersymbol interference from N previous symbols will have A N  possible states. Each state corresponds to a possible transition path through the N previous symbols. For example, a system with two symbols, {A}={+1, -1}, and N=2 will have four possible sequence states of the system: symbol +1 at time k-2 and symbol +1 at time k-1; symbol +1 at time k-2 and symbol -1 at time k-1; symbol -1 at time k-2 and symbol +1 at time k-1; and symbol -1 at time k-2 and symbol -1 at time k-1. The sequence detector for the example shown in FIG. 4 has two states, +1 and -1, corresponding to the two symbols in the alphabet {A}. 
     The trellis diagram depicting the state transition from time (k-1) to time k for the example shown in FIG. 4 is shown in FIG. 5. A trellis diagram provides a graphical mechanism for predicting what the signal output would be for the channel in transitions from one state in time k-1 to another state at time k. From the trellis diagram in FIG. 5, a transition from state +1 at time k-1 to state +1 at time k would result in a predicted signal output (without noise) of 1+f 1 . A transition from state -1 at time k-1 to state -1 at time k would result in a predicted signal output of -1-f 1 . A transition from state -1 at time k-1 to state +1 at time k results in a predicted signal output of 1-f 1  and a transition from state +1 at time k-1 to state -1 at time k results in a predicted signal output of -1+f 1 . 
     In the detector shown in FIG. 4, the branch metric unit generates four distance metrics corresponding to the four branch labels in the trellis diagram of FIG. 5. In the preferred embodiments, the distance metrics are given by the Euclidean distances 
     
         M.sub.k (0)=[y.sub.k -1-f.sub.1 ].sup.2, 
    
     
         M.sub.k (1)=[y.sub.k +1-f.sub.1 ].sup.2,                   (9) 
    
     
         M.sub.k (2)=[y.sub.k -1+f.sub.1 ].sup.2, and 
    
     
         M.sub.k (3)=[y.sub.k +1+f.sub.1 ].sup.2. 
    
     Other metrics which represent the difference between the input symbol and the predicted input symbols assuming each of the possible state transitions may be used as the distance metrics. In general, there will be branch metric for transitions from any state S&#39; at time k-1 to state S at time k, A 2N  for a system with A symbols and N interfering symbols if all transitions are allowed. 
     The add-compare-select (ACS) circuit in FIG. 4 updates a state metric for each possible state of the system, denoted by p k  (+1) and p k  (-1) in this example, at each time step k. For a two symbol system as shown in FIG. 4, the state metrics are given by: 
     
         p.sub.k (+1)=min[p.sub.k-1 (+1)+M.sub.k (0), p.sub.k-1 (-1)+M.sub.k (2)] and 
    
     
         p.sub.k (-1)=min[p.sub.k-1 (+1)+M.sub.k (1), p.sub.k-1 (-1)+M.sub.k (3)].(10) 
    
     In general, the state metrics represent the accumulated distance metrics of past states along transition paths that minimize the accumulated distance metric. Therefore, the transition metric for state S at time period k, p k  (S), is the accumulated distance metric for previous states along a transition path which ends at state S at time period k, state S being one of the possible states of the system. At time k-1, the state of the system may be at any state S&#39; in the group of possible states of the system. Therefore, p k  (S) is the minimum one of p k-1  (S&#39;) plus the distance metric for transition from S&#39; to S. A mathematical proof that this technique results in the least detection error is given in the Appendix. 
     In the example of FIG. 4, the comparison results, d k  (+1) and d k  (-1) , are stored in the traceback circuit for each of the two states. The comparison results indicate the state at time period k-1 which results in the state metric p k  (S) for state S at time period k. In the two symbol, N=1 example of FIG. 4, if 
     
         p.sub.k-1 (+1)+M.sub.k (0)≦p.sub.k-1 (-1)+M.sub.k (2),(11) 
    
     then a &#34;+1&#34; data value is stored for time k in the memory allocated for state +1 in the traceback circuit, d k  (+1). Otherwise, a &#34;-1&#34; is stored for time k in the memory allocated for state +1 in the traceback circuit. Similar results are stored in the memory allocated for state -1 in the traceback circuit. In the more general case, d k  (S) points toward the state S&#39; at time k-1 from which results the lowest state metric for arriving at state S at time k. 
     When it is time for decoding, the traceback circuit traces back from the best possible current state (the state with the smallest state metric), and fetches the data from the traceback memory. If the traceback depth is 2*TB, then it is expected that a traceback of TB is performed every TB/2 sample times and the traceback circuit outputs TB/2 data symbols. (TB is an even integer). A greater traceback depth will result in less error in determining the final sequence of symbols at a cost of including more memory in the chip. Typical traceback depths are 8 or 16. 
     During the traceback procedure, the starting state determiner picks the starting state based on whichever state metric is less. The traceback circuit follows the sequence back through the stored comparison results. The earliest symbols which result in the earliest states, the earliest TB/2 symbols in the A=2 and N=1 examples, are written into the last-in-first-out buffer. In the preferred embodiments, the new comparison results are stored in the memory locations previously occupied by the outputted results. 
     The traceback circuit determines the optimum sequence of symbols based on the state metrics stored in the starting state determiner. The starting state determiner also initializes the traceback procedure by setting a starting sequence. 
     The LIFO circuitry simply time-reverses the data coming out of traceback memory because the traceback is performed from the current time to previous times. 
     Sequence Detection with Linear Equalization 
     When the channel ISI length N is large, or if the transmitted symbol alphabet size A is large, the above method of full sequence estimation becomes impractical at high symbol rates. Full sequence estimations require the implementation of A N  states in the detector. Accordingly, the preferred embodiment of the invention, as shown in FIG. 6, uses a linear equalizer to reduce the number of ISI symbols seen by the sequence detector. 
     In this example, assume that the channel input alphabet size is 2, i.e. A={-1, +1}, and that the reduced ISI length (as seen by the sequence detector) is L=1. As before, the technique is applicable to larger alphabets and may accommodate more than one interfering symbol in the reduced length. 
     The output of the linear equalizer with A=2 and L=1 is given by 
     
         r.sub.k =a.sub.k +g.sub.1 *a.sub.k-1 +h.sub.k,             (12) 
    
     where g 1  is the equalized ISI coefficient and h k  is the noise component of the output of the linear equalizer. The linear equalizer transfer function (in Z-transform notation, See A. V. OPPENHEIM AND R. W. SCHAFER, DISCRETE-TIME SIGNAL PROCESSING, (1989)) is given by 
     
         E(z)=(1+g.sub.1 z.sup.-1)/f(z).                            (13) 
    
     The coefficient g 1  is chosen to minimize the noise variance at the output of the equalizer. 
     In the preferred embodiment, the reduced sequence equalization is implemented adaptively. One architecture used for adaptive implementation is a linear equalizer implementing a transfer function C(Z)=1/f(Z) adaptively followed by a (1+g 1  z -1 ) filter. By implementing both equalizers adaptively, optimal performance can be achieved for any cable length. The linear equalizer C(Z) can be adaptively implemented by using the least mean squares (LMS) algorithm (See E. A. LEE AND D. G. MESSERCHMITT, DIGITAL COMMUNICATIONS (1988)) and a finite impulse response filter as shown in FIG. 2. 
     The coefficient g 1  is chosen adaptively in the sequence detector by observing the frequency response of the linear equalizer C(Z). From the linear equalizer, the channel frequency response is deduced and g.sub. is selected from a look-up table. In a particular implementation, two possible values of g 1  (0 and 1/2) are used. One of the two possible coefficients is chosen for g 1  by observing the two largest coefficients of the linear equalizer implementing C(Z). 
     The benefits of combining linear equalization with sequence detection include (a) reduced complexity in the sequence detector, especially for large N, and (b) reduced noise enhancement in the linear equalization. 
     In the example of the preferred embodiment described in FIG. 6, the number of states in the sequence estimator is reduced from 2 N  to 2. The reduced state sequence estimator can be implemented using the Viterbi algorithm described in the previous embodiment where f 1  is replaced by g 1  to match the linear equalizer and y k  is replaced by r k  in the metric computations of Equation 5. 
     Seguence Detection with Linear Equalization and Decision Feedback 
     FIG. 7 shows an embodiment of the reduced state sequence estimation which utilizes linear equalization and decision-feedback. In this embodiment, the linear equalizer equalizes the channel to a pre-determined ISI polynomial G(z) of length M&lt;N. In FIG. 7, M is assumed to be 2, G(z) is given by 
     
         G(z)=1+g.sub.1 z.sup.-1 +g.sub.2 z.sup.-2,                 (14) 
    
     and the linear equalizer transfer function is given by 
     
         E(z)=G(z)/f(z).                                            (15) 
    
     In general, the detection technique may be used for any combination of M and N such that M&lt;N. Although the technique may be implemented with any sized alphabet, the example shown in FIG. 8 is for A=2. In the preferred embodiment, the coefficients g1 and g2, again, are chosen adaptively. 
     To perform the sequence estimation using the Viterbi algorithm outlined above, the sequence detector must be implemented with four states (if the data symbols are binary valued). Instead, a reduced state sequence estimation using only two states is used as shown in FIG. 8. The branch metric computation in the trellis diagram now accounts for the intersymbol interference due to the symbol transmitted two sample times before. In the block diagram shown in FIG. 8, the branch metrics are given by 
     
         M.sub.k (0)=[r.sub.k -g.sub.2 d.sub.k-1 (+1)-1-g.sub.1 ].sup.2, 
    
     
         M.sub.k (1)=[r.sub.k -g.sub.2 d.sub.k-1 (+1)+1-g.sub.1 ].sup.2,(16) 
    
     
         M.sub.k (2)=[r.sub.k -g.sub.2 d.sub.k-1 (-1)-1+g.sub.1 ].sup.2, and 
    
     
         M.sub.k (3)=[r.sub.k -g.sub.2 d.sub.k-1 (-1)+1+g.sub.1 ].sup.2. 
    
     In this way, the ISI due to the transmitted symbol at time (k-2) is removed from the received sample r k  before the branch metric of the sequence detector that accounts for the ISI due to the transmitted symbol at time (k-1) is computed. After this calculation, the previously described calculation is performed to remove the ISI due to the (k-1)th transmitted symbol. 
     Application to 100Base-TX Fast Ethernet 
     An embodiment of this invention appropriate for application to 100Base-TX Fast Ethernet (See Institute of Electrical and Electronics Engineers, New York, IEEE Standard 802.3u-1995 CSMA/CD Access Method, Type 100Base-T (1995); American National Standard Information Systems, Fibre Distributed Data Interface (FDDI)--Part: Token ring twisted pair physical layer medium dependent (TP-PMD), ANSI X3.263:199X) involves three-level signaling. (i.e., the binary data is physically transmitted using the MLT3 modulation method). A mapping of a binary sequence into the three-level transmission is given by the following chart: 
     
         ______________________________________Binary 0     0      1   1   0    1   0    1    0   1   13-Level 0     0      1   1   0    -1  0    1    0   -1  -1______________________________________ 
    
     In the above mapping, it is clear that a transmission sequence of {-1, +1) (symbol -1 in time k-1 to symbol +1 in time k) is invalid, as are the sequences {+1, 0, +1} and {-1, 0, -1}. 
     A trellis diagram for a symbol alphabet of {-1, 0, +1} and N=1 which incorporates the above restrictions in allowed sequences is shown in FIG. 9. In FIG. 9, the channel function is given by 1+g 1  z -1 . 
     A block diagram of a sequence detector to equalize the ISI Channel with f(z)=1+f 1  z -1  is shown in FIG. 10. In FIG. 10, an input symbol y k  is received by the branch metric generator. The branch metric generator generates the seven branch metrics corresponding to the seven allowed transitions showed in the trellis diagram of FIG. 9. The branch metrics are input to an add-compare-select (ACS) circuit which calculates the state metrics P k  and the predicted results D k . The state metrics P k  are inputted to the starting point determiner and the predicted results D R  are inputted to the traceback circuit. 
     In this example, the seven branch metrics are given by: 
     
         M.sub.k (0)=[y.sub.k -1f-.sub.1 ].sup.2 ; 
    
     
         M.sub.k (1)=[y.sub.k -1].sup.2 ; 
    
     
         M.sub.k (2)=[y.sub.k -f.sub.1 ].sup.2 ; 
    
     
         M.sub.k (3)=[y.sub.k ].sup.2 ; 
    
     
         M.sub.k (4)=[y.sub.k +f.sub.1 ].sup.2 ; 
    
     
         M.sub.k (5)=[y.sub.k +1].sup.2 ; and 
    
     
         M.sub.k (6)=[y.sub.k +1+f.sub.1 ].sup.2.                   (17) 
    
     If sequence detector is combined with a linear equalizer as shown in FIG. 6, then the symbol input y k  to the sequence detector in FIG. 10 is replaced by the output of the linear equalizer, r k  =y k  +g 1  y k-1  as in Equation 12 (neglecting noise), and the sequence detector is matched to the linear equalizer by setting g 1  =f 1 . 
     The three state metrics calculated in the ACS are: 
     
         p.sub.k (+1)=min{p.sub.k-1 (+1)+M.sub.k (0), p.sub.k-1 (0)+M.sub.k (1)}; 
    
     
         p.sub.k (0)=min{p.sub.k-1 (+1)+M.sub.k (2), p.sub.k-1 (0)+M.sub.k (3), p.sub.k-1 (-1)+M.sub.k (4)}; and 
    
     
         p.sub.k (+1)=min{p.sub.k-1 (0)+M.sub.k (5), p.sub.k-1 (-1)+M.sub.k (6)}.(18) 
    
     The results of the ACS are given by: 
     
         D.sub.k (+1)={+1 if p.sub.k (+1)=p.sub.k-1 (+1)+M.sub.k (0) 
    
     
          {-1 if p.sub.k (+1)=p.sub.k-1 (0)+M.sub.k (1) 
    
     
         D.sub.k(0)={+1 if p.sub.k (0)=p.sub.k-1 (+1)+M.sub.k (2) 
    
     
          {0 if p.sub.k (0)=p.sub.k-1 (0)+M.sub.k (3)               (19) 
    
     
          {-1 if p.sub.k (0)=p.sub.k-1 (-1)+M.sub.k (4) 
    
     
         D.sub.k (-1)={-1 if p.sub.k (-1)=p.sub.k-1 (-1)+M.sub.k (6) 
    
     
          {0 if p.sub.k (-1)=p.sub.k-1 (0)+M.sub.k (5) 
    
     These states and state metrics are stored in the memory of the traceback circuit. 
     As described above, the traceback circuit traces back from the best possible current state (the state with the smallest state metric), and fetches the data from the traceback memory. The symbol having the lowest state metric is output to the LIFO which outputs the last input first because the earliest received input symbol is the symbol decided on last. 
     The sequence detector appropriate for 100Base-TX Fast Ethernet as described above may additionally be combined with a linear equalizer as described above with FIG. 6 or with a combination of linear equalizer and decision feedback as described above with FIG. 7. 
     Application to 1000Base-T Long Haul Copper 
     The modulation format chosen by the IEEE 802.3ab standards committee for Gigabit Ethernet over category 5 copper cabling utilizes 5-level NRZ signaling given by the symbol alphabet A={+2, +1, 0, -1, -2}. (See IEEE 802.3ab, Gigabit long haul copper physical layer standards committee, 1997). 
     A trellis diagram for this application is shown in FIG. 11 assuming N=1 and a channel function f(z)=1+f 1  z -1 . A block diagram of the sequence detector is shown in FIG. 12. In FIG. 12, the input signal y k  is received by the branch metric generator. The branch metric generator calculates the 25 branch metrics M k  for input into the ACS circuit. The ACS circuit calculates the five state metrics P k  and the five comparison decisions D k  for input into the starting point determiner and the traceback circuit, respectively. The traceback circuit, with input from the starting point determiner, outputs to the LIFO the best symbol sequence {a k  } for output. 
     Branch metrics for N=1 and f(z)=1+f 1  z -1 , as in this example, are given by: 
     
         ______________________________________M.sub.k (0) = [y.sub.k -2 - 2f.sub.1 ].sup.2              M.sub.k (13) = [y.sub.k + f.sub.1 ].sup.2M.sub.k (1) = [y.sub.k -2 - f.sub.1 ].sup.2              M.sub.k (14) = [y.sub.k + 2f.sub.1 ].sup.2M.sub.k (2) = [y.sub.k -2].sup.2              M.sub.k (15) = [y.sub.k + 1 - 2f.sub.1 ].sup.2M.sub.k (3) = [y.sub.k -2 + f.sub.1 ].sup.2              M.sub.k (16) = [y.sub.k + 1 - f.sub.1 ].sup.2M.sub.k (4) = [y.sub.k -2 + 2f.sub.1 ].sup.2              M.sub.k (17) = [y.sub.k + 1].sup.2M.sub.k (5) = [y.sub.k -1 - 2f.sub.1 ].sup.2              M.sub.k (18) = [y.sub.k + 1 + f.sub.1 ].sup.2M.sub.k (6) = [y.sub.k -1 - f.sub.1 ].sup.2              M.sub.k (19) = [y.sub.k + 1 + 2f.sub.1 ].sup.2M.sub.k (7) = [y.sub.k -1].sup.2              M.sub.k (20) = [y.sub.k + 2 - 2f.sub.1 ].sup.2M.sub.k (8) = [y.sub.k -1 +f.sub.1 ].sup.2              M.sub.k (21) = [y.sub.k + 2 - f.sub.1 ].sup.2M.sub.k (9) = [y.sub.k -1 +2f.sub.1 ].sup.2              M.sub.k (22) = [y.sub.k + 2].sup.2M.sub.k (10) = [y.sub.k -2f.sub.1 ].sup.2              M.sub.k (23) = [y.sub.k + 2 + f.sub.1 ].sup.2M.sub.k (11) = [y.sub.k -f.sub.1 ].sup.2              M.sub.k (24) = [y.sub.k + 2 + 2f.sub.1 ].sup.2______________________________________ 
    
     
         M.sub.k (12)=[y.sub.k ].sup.2.                             (20) 
    
     The state metrics as updated in the ACS are 
     
         p.sub.k (i)=min.sub.j={-2, -1, 0, 1, 2} {p.sub.k-1 (j)+M.sub.k (2+j+5i}; for i={2, 1, 0, -1, -2}.                                  (21) 
    
     The ACS results for each of the five states are given by 
     
         D.sub.k (i)=j if p.sub.k (+1)=p.sub.k-1 (j)+Mk(2+j+5i); for i={2, 1, 0, -1, -2}; j={2, 1, 0, -1, -2}.                                 (22) 
    
     The five state sequential equalizer described above can be used with linear equalization as described with FIG. 6. In that application, the input signal y k  is replaced by the output signal of the linear equalizer r k  =y k  +g 1  *a k-1 , as in Equation 12 above (neglecting noise). The channel function of the sequential equalizer is then given by f 1  =g 1  to match the linear equalization. In addition, decision feedback equalization may also be used as described with FIG. 8. 
     The above examples are illustrative only and in no way should they be construed as limiting the scope of the invention. As such, the scope of the invention is limited only by the following claims. ##EQU1##