Abstract:
A clock selection circuit for selecting between two clock sources. The clock selection circuit has two independent clock inputs, CLK 1  and CLK 2 , where no assumptions are made regarding frequency or phase relationship between the two clocks inputs. Two asynchronous inputs, START 1  and START 2  (both active high), are used to start and stop the clocks. As long as one clock is active, the START signal of the other clock will not have any effect. The invention includes interlock circuitry that ensures that at any given time only one clock is enabled to the output. Disabling the corresponding START signal disables the clock signal.

Description:
TECHNICAL FIELD OF THE INVENTION  
         [0001]    The present invention is generally directed to data processors, radio transceivers, and other circuits that can operate from different clock sources and, more specifically, to a glitchless clock selection circuit for selecting one of two clock sources to apply to a clocked circuit.  
         BACKGROUND OF THE INVENTION  
         [0002]    The speed, power, and complexity of integrated circuits (ICs), such as application specific integrated circuit (ASIC) chips, central processing unit (CPU) chips, digital signal processor (DSP) chips and the like, have greatly increased in recent years. These advancements have made possible the development of system-on-a-chip (SOC) devices, among other things. A SOC device integrates into a single chip all (or nearly all) of the components of a complex electronic system, such as a wireless receiver (i.e., cell phone, a television receiver, and the like). Advanced semiconductor process technologies allow these circuits to be fabricated as dense high performance integrated circuit.  
           [0003]    Power dissipation is an important constraint in such dense high performance integrated circuits. A combination of several power minimization techniques is used to keep the power dissipation of chips within bounds. One such technique involves adapting the clock frequency of a circuit to the performance requirement of the system. When higher system throughput is desired, the clock frequency is increased dynamically. The clock frequency is lowered when the throughput requirement is lower to reduce power dissipation of the circuit.  
           [0004]    Dynamic control of the system clock frequency may be achieved in two ways, namely:  
           [0005]    1) Continuously variable clock frequency: In this technique, the clock frequency of the system can be gradually changed to a new value without stopping the clock. This technique is used in conjunction with voltage scaling techniques and requires analog circuits; and  
           [0006]    2) Discretely variable clock frequency: In this technique, the system can operate at only a few predetermined clock frequencies. The transition to a new clock frequency is possible only in discrete steps. To avoid corruption of data stored in the system, the clock to the system must be stopped before the transition from a first clock source to a second clock source is made (i.e., the transition from one clock domain to another must be “glitchless”). An important advantage in using this technique is that the clocks may be switched using digital circuits.  
           [0007]    Therefore, there is a need in the art for an improved clock selection circuit for applying a selected one of two clock sources to a clock circuit, such as a data processor.  
         SUMMARY OF THE INVENTION  
         [0008]    This present invention provides a clock selection circuit for selecting between two clock sources. The clock selection circuit has two independent clock inputs, CLK 1  and CLK 2 . No assumption is made about the frequency or phase relationship between the two clocks inputs. Two asynchronous inputs, START 1  and START 2  (both active high), are used to start and stop the clocks. The global asynchronous reset signal, R (active high), is used at power-on and is essential for correct operation of the circuit. The CLKOUT signal is used as the clock to the system.  
           [0009]    After power-on reset, one out of the two clock signals may be switched on using the START 1  or START 2  signals. As long as one clock is active, the START signal of the other clock will not have any effect. The interlock circuitry ensures that at any given time only one clock is enabled to the output. Disabling the corresponding START signal disables the clock signals.  
           [0010]    Important advantages provided by a clock selection circuit according to the principles of the present invention are:  
           [0011]    1) Glitchless switching between two clock signals with arbitrary frequency and phase relationship;  
           [0012]    2) Interlocked clock switching—The clock selection circuit ensures that the CLKOUT output of one clock has completely stopped before switching to the another.  
           [0013]    3) Integral clock period operation—The number of clock pulses is always an integral multiple of the clock period. This eliminates partial (incomplete) clock pulses when switching from one clock source to the other clock source.  
           [0014]    To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide, for use with a clocked circuit, a clock selection circuit capable of receiving a first input clock signal and a second input clock signal and outputting to the clocked circuit a selected clock signal derived from one of the first and second input clock signals. According to an advantageous embodiment of the present invention, the clock selection circuit comprises: 1) a first clock control circuit that receives the first input clock signal and a first start signal, wherein the first start signal, when asserted, is capable of causing the first clock control circuit to output a first gated clock signal; 2) a second clock control circuit that receives the second input clock signal and a second start signal, wherein the second start signal, when asserted, is capable of causing the second clock control circuit to output a second gated clock signal; 3) a first interlock circuit that detects when the first clock control circuit begins outputting the first gated clock signal and, in response to the detection, that asserts a first disable signal capable of preventing the second clock control circuit from outputting the second gated clock signal; 4) a second interlock circuit that detects when the second clock control circuit begins outputting the second gated clock signal and, in response to the detection, that asserts a second disable signal capable of preventing the first clock control circuit from outputting the first gated clock signal; and 5) a first OR gate that receives the first and second gate clock signal and outputs the selected clock signal.  
           [0015]    The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.  
           [0016]    Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term “controller” means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]    For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, wherein like numbers designate like objects, and in which:  
         [0018]    [0018]FIG. 1 illustrates a block diagram of a digital processing system according to an exemplary embodiment of the present invention;  
         [0019]    [0019]FIG. 2 illustrates the clock selection circuit in FIG. 1 in greater detail according to an exemplary embodiment of the present invention;  
         [0020]    [0020]FIG. 3 illustrates in greater detail the interlock circuit in the exemplary clock selection circuit according to one embodiment of the present invention; and  
         [0021]    [0021]FIG. 4 is a timing diagram illustrating the operation of the clock selection circuit according to the exemplary embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0022]    [0022]FIGS. 1 through 4, discussed below, and the various embodiments used to describe the principles of the present invention in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the invention. Those skilled in the art will understand that the principles of the present invention may be implemented in any suitably arranged data processor or other circuit that uses a clock selection circuit for selecting one of two clock sources to apply to a clocked circuit.  
         [0023]    [0023]FIG. 1 illustrates a block diagram of digital processing system  100  according to one exemplary embodiment of the present invention. Digital processing system  100  comprises clock source  105 , clock source  110 , clock selection circuit  115 , and a digital processing component (i.e., DSP/CPU system  120 ). Clock source  110  comprises crystal oscillator  111  and phase-locked loop (PLL) frequency synthesizer  112 .  
         [0024]    Exemplary crystal oscillator  111  generates an output reference frequency signal in which the reference frequency of the output is determined by the mechanical properties of a piezoelectric crystal. Exemplary PLL frequency synthesizer  112  is coupled to the output of crystal oscillator  111  and generates the CLK1 clock signal, which has an operating frequency that is a multiple of the reference frequency provided by crystal oscillator  111 . The CLK 1  signal may represent a set of clock frequencies. Clock source  105  may be any type of clock signal generator, including an external source, and it generates the CLK 2  clock signal.  
         [0025]    Generally, speaking DSP/CPU system  120  may be any digital processing component designed for performing mathematical computations and may suitably be programable, meaning that digital processing component  120  may be used for manipulating different types of information, including sound, images, video, and the like. According to the present embodiment, DSP/CPU system  120  has varying operating frequencies and receives a CLKOUT signal from clock selection circuit  115 .  
         [0026]    Clock selection circuit  115  outputs either the CLK 1  clock signal or the CLK 2  signal as the CLKOUT signal, depending one the values of the START 1  and START 2  clock select signals. No assumptions are made about the frequency or phase relationship between the CLK 1  clock signal and the CLK 2  signal. The CLK 1  clock signal and the CLK 2  signal may be synchronous or asynchronous. Either of CLK 1  and CLK 2  signal may be faster, or CLK 1  an dCLK 2  may operate at the same speed. START 1  and START 2  are synchronous active high signals that enable the CLK 1  clock signal and the CLK 2  signal to be connected to the CLKOUT output. The global asynchronous reset signal, R, is an active high signal used at power-on.  
         [0027]    [0027]FIG. 2 illustrates clock selection circuit  115  in greater detail according to an exemplary embodiment of the present invention. Clock selection circuit  115  comprise clock control circuits  201 A and  201 B, interlock circuits  240 A and  240 B, and OR gate  250 . Clock control circuits  201 A and  201 B produce the gated clock output GCLK 1  and GCLK 2 , repsectively. Clock control circuit  201 A comprises inverter  205 A, AND gate  210 A, flip-flop  215 A, inverter  220 A, flip-flop  225 A, OR gate  230 A, and AND gate  235 A. Clock control circuit  201 B comprises inverter  205 B, AND gate  210 B, flip-flop  215 B, inverter  220 B, flip-flop  225 B, OR gate  230 B, and AND gate  235 B. FIG. 3 illustrates interlock circuit  240  in clock selection circuit  115  in greater detail according to an exemplary embodiment of the present invention. Interlock circuit  240  in FIG. 3, which is representative of interlock circuits  240 A and  240 B in FIG. 2, comprises flip-flop  310 , flip-flop  320 , flip-flop  330 , and OR gate  340 .  
         [0028]    All of flip-flops  215 A and  215 B, flip-flops  225 A and  225 B, and flip-flops  310 ,  320  and  330  are positive (rising) edge-triggered D-type flip-flops (FF). Flip-flop  215 A and flip-flops  310 ,  320 , and  330  in interlock circuit  240 A are connected directly to the CLK 1  clock signal and transfer data on the D input to the Q output when a rising edge occurs on the CLK 1  clock signal. Flip-flop  215 B and flip-flops  310 ,  320 , and  330  in interlock circuit  240 B are connected directly to the CLK 2  clock signal and transfer data on the D input to the Q output when a rising edge occurs on the CLK 2  clock signal. Flip-flop  225 A is connected to the CLK 1  clock signal through inverter  220 A and transfers data on the D input to the Q output when a falling edge occurs on the CLK 1  clock signal. Flip-flop  225 B is connected to the CLK 2  clock signal through inverter  220 B and transfers data on the D input to the Q output when a falling edge occurs on the CLK 2  clock signal.  
         [0029]    [0029]FIG. 4 is a timing diagram illustrating the operation of selected portions of clock selection circuit  115  according to an exemplary embodiment of the present invention. Initially, the reset (R) signal is Logic 1 (i.e., high). The reset (R) signal is an active high master reset that sets the Q outputs of all of flip-flops  215 A and  215 B, flip-flops  225 A and  225 B, and flip-flops  310 ,  320  and  330  to Logic 0 (i.e., low). When the Q outputs of these flip-flops are Logic 0, the A and B inputs to interlock circuits  240 A and  240 B are Logic 0 and the DISABLE 1  and DISABLE 2  outputs of interlock circuits  240 A and  240 B are also Logic 0. Also, when the Q outputs of these flip-flops are all Logic 0, OR gates  230 A and  230 B output Logic 0 values to AND gates  235 A and  235 B. This, in turn, sets the gated clock signals GCLK 1 and GCLK 2  to Logic 0 and CLKOUT also is held at Logic 0.  
         [0030]    This state continues after the reset (R) signal is set back to Logic 0 until either START 1  or START 2  is set to Logic 1. Since clock control circuits  201 A and  201 B operate in similar manners, the following text describes in detail the operation of clock control circuit  201 A. The corresponding description of clock control circuit  201 B is omitted to avoid redundancy.  
         [0031]    The clock pulses (CPs) of CLK 1  and CLK 2  are sequentially numbered (i.e., CP 1 , CP 2 , CP 3 , . . . ). Since DISABLE 1  is initially Logic 0, when the START 1  signal finally goes to Logic 1 prior to the rising edge of CP 1 , both inputs of AND gate  210 A are finally Logic 1, which sets the D input of flip-flop  215 A to Logic 1. On the rising edge of CP 1  (i.e., time T 1 ), the Q output of flip-flop  215 A goes to Logic 1. This sets the A input of interlock circuit  240 B (shown as  240 B-A in FIG. 4) to Logic 1. On the falling edge of CP 1  (i.e., time T 2 ), the Q output of flip-flop  225 A (shown as  225 A-Q in FIG. 4) goes to Logic 1.  
         [0032]    When the START 1  signal finally goes to Logic 0 prior to the rising edge of CP 5 , one of the inputs to AND gate  210 A goes to Logic 0, which sets the D input of flip-flop  215 A to Logic 0. On the rising edge of CP 5  (i.e., time T 3 ), the Q output of flip-flop  215 A goes to Logic 0. This sets the A input of interlock circuit  240 B (shown as  240 B-A in FIG. 4) to Logic 0. On the falling edge of CP 5  (i.e., time T 4 ), the Q output of flip-flop  225 A (shown as  225 A-Q in FIG. 4) goes to Logic 0.  
         [0033]    When the A input of interlock circuit  240 B goes to Logic 1 at time T 1 , the DISABLE 2  signal immediately goes to Logic 1. This immediately disables the START 2  input of clock control circuit  201 B, preventing the GCLK 2  clock from being exerted for as long as START 1  remains at Logic 1. The B input of interlock circuit  240 B (shown as  240 B-B in FIG. 4) is the logic OR of the Q output of flip-flop  215 A and the Q output of flip-flop  225 A. If either the Q output of flip-flop  215 A or the Q output of flip-flop  225 A is Logic 1, then B input of interlock circuit  240 B is also Logic 1. The rising edges of CP 1 , CP 2  and CP 3  propagate the Logic 1 at the B input of interlock circuit  240 B to hold the DISABLE 2  signal at Logic 1.  
         [0034]    When the Logic 1 on the A input of interlock circuit  240 B finally goes to Logic 0 at time T 3  (as a result of START 1  going to Logic 0 prior to CP 5 ), the DISABLE 2  signal output is unaffected because the other input to OR gate  340  is held at Logic 1 by the Q output of flip-flop  330 . After the B input of interlock circuit  240 B goes to Logic 0 at time T 4 , it takes another three rising edges of the CLK 2  clock to propagate the Logic 0 from the B input of interlock circuit  240 B to the Q output of flip-flop  330 . Only then does the DISABLE 2  signal go to Logic 0, thereby enabling the START 2  signal via AND gate  210 B. Thus, the DISABLE 2  signal is a fast turn-on, slow turn-off signal with respect to the START 1  signal. Similarly, the DISABLE 1  signal is a fast turn-on, slow turn-off signal with respect to the START 2  signal.  
         [0035]    As noted above, the B input of interlock circuit  240 B (shown as  240 B-B in FIG. 4), taken from the output of OR gate  230 A, is the logic OR of the Q output of flip-flop  215 A and the Q output of flip-flop  225 A. The output of OR gate  230 A also enables AND gate  235 A to pass the CLK 1  signal to the output of AND gate  235 A. Thus, if either the Q output of flip-flop  215 A or the Q output of flip-flop  225 A is Logic 1, then CLK 1  appears at GCLK 1 , the gated clock output of clock control circuit  201 A. Since the Q output of flip-flop  225 A only goes to Logic 0 on the falling edges of CLK 1  clock pulses, the GCLK 1  signal only goes low on the falling edges of CLK 1  clock pulses. Thus, clock pulses at GLK 1  are not cut short when START 1  goes to Logic 0.  
         [0036]    As noted above, the operation of clock control circuit  201 B is substantially identical to the operation of clock control circuit  201 A. Thus, it is unnecessary and redundant to explain in detail the operation of clock control circuit  201 B.  
         [0037]    Although the present invention has been described in detail, those skilled in the art should understand that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the invention in its broadest form.