Abstract:
A method of fabricating at least one damascene opening comprising the following steps. A structure having at least one exposed conductive structure is provided. A dielectric barrier layer over the structure and the at least one exposed conductive structure. A lower low-k dielectric layer is formed over the dielectric barrier layer. An upper low-k dielectric layer is formed over the lower low-k dielectric layer. An SRO etch stop layer is formed between the lower low-k dielectric layer and the upper low-k dielectric layer and/or an SRO hard mask layer is formed over the upper low-k dielectric layer. At least the upper and lower low-k dielectric layers are patterned to form the at least one damascene opening exposing at least a portion of the at least one conductive structure, wherein the at least one SRO layer has a high etch selectivity relative to the lower and upper low-k dielectric layers.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    Currently, silicon nitride (SiN) or silicon oxynitride (SiON) liners are chosen as the etch stop layer and as hard masks for fluorine (F)-doped and carbon (C)-doped low-k dielectrics like FSG, CORAL™, BLACK DIAMOND™, SiLK™, etc. in copper (Cu) single/dual damascene interconnect processes. However, it has been reported that using either SiN (having a dielectric constant of about 7.0) or SiON (having a dielectric constant of about 5.5) causes masking footing and via poisoning issues due to the interaction of photoresist with amine species. Further, the high dielectric constant (k) from SiN or SiON compensates the effect of introducing low-k material into semiconductor manufacturing and results in a high effective dielectric constant of intermetal dielectric (IMD) layers.  
           [0002]    U.S. Pat. No. 6,207,556 B1 to Hsu describes an silicon-rich oxide (SRO) layer  204  and low-k layers.  
           [0003]    U.S. Pat. No. 6,174,797 B1 to Bao et al. describes an SRO barrier layer  16 .  
           [0004]    U.S. Pat. No. 6,228,756 B1 to Lee describes a silicon-rich layer  114  for low-k layer  106 .  
           [0005]    U.S. Pat. No. 6,166,427 to Huang et al., U.S. Pat. No. 6,133,143 to Lin et al. and U.S. Pat. No. 5,976,984 to Chen et al. describe SRO layers in interconnect processes.  
         SUMMARY OF THE INVENTION  
         [0006]    Accordingly, it is an object of one or more embodiments of the present invention to provide an improved method of fabricating a damascene structure using an intermediate SRO etch stop layer and/or an uppermost SRO hard mask layer.  
           [0007]    Other objects will appear hereinafter.  
           [0008]    It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a structure having at least one exposed conductive structure is provided. A dielectric barrier layer over the structure and the at least one exposed conductive structure. A lower low-k dielectric layer is formed over the dielectric barrier layer. An upper low-k dielectric layer is formed over the lower low-k dielectric layer. An SRO etch stop layer is formed between the lower low-k dielectric layer and the upper low-k dielectric layer and/or an SRO hard mask layer is formed over the upper low-k dielectric layer. At least the upper and lower low-k dielectric layers are patterned to form the at least one damascene opening exposing at least a portion of the at least one conductive structure, wherein the at least one SRO layer has a high etch selectivity relative to the lower and upper low-k dielectric layers.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]    The features and advantages of the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or corresponding elements, regions and portions and in which:  
         [0010]    FIGS.  1  to  3  schematically illustrate in cross-sectional representation a preferred embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0011]    Initial Structure  
         [0012]    [0012]FIG. 1 illustrates a cross-sectional view of a structure  10  having exposed conductive structures  12  formed therein. Conductive structures  12  may be metal plugs or lines, for example, and may include respective metal barrier layers  14  as shown in the figures. Conductive structures  12  are preferably comprised of copper (Cu), aluminum (Al), tungsten (W) or gold (Au) and are more preferably comprised of copper.  
         [0013]    Structure  10  is preferably a silicon substrate and is understood to possibly include a semiconductor wafer or substrate, active and passive devices formed within the wafer, conductive layers and dielectric layers (e.g., inter-poly oxide (IPO), intermetal dielectric (IMD), etc.) formed over the wafer surface. The term “semiconductor structure” is meant to include devices formed within a semiconductor wafer and the layers overlying the wafer.  
         [0014]    A dielectric barrier layer  11  is formed over the structure  10  and conductive structures  12  to a thickness of preferably from about 200 to 700 Å and more preferably from about 300 to 500 Å. Dielectric barrier layer  11  is preferably comprised of SiN, SiON or SiC.  
         [0015]    A lower dielectric layer  16  is formed over dielectric barrier layer  11  to a thickness of preferably from about 1500 to 6000 Å and more preferably from about 2500 to 5000 Å. Lower dielectric layer  16  is generally an intermetal dielectric (IMD) layer.  
         [0016]    Lower dielectric layer  16  is preferably comprised of a low-k dielectric material such as: inorganic low-k dielectrics such as hydrogen silsesquioxane; fluorine (F)-doped or carbon (C)-doped low-k dielectric materials such as FSG, CORAL™ manufactured by NVLS; BLACK DIAMOND™ manufactured by AMAT; or SILK™ manufactured by Dow Chemical, or other organic low-k materials, for example.  
         [0017]    Formation of SRO Etch Stop Layer  18   
         [0018]    A silicon-rich (SRO) etch stop layer  18  is formed over the lower dielectric layer  16  to a thickness of preferably from about 200 to 1000 Å and more preferably from about 300 to 700 Å. SRO etch stop layer  18  will be used as an etch stop for the trench opening in a dual damascene interconnect (and not for the via opening etching).  
         [0019]    SRO etch stop layer  18  is preferably formed in an amine-free environment either:  
         [0020]    (1) by the reaction of TEOS with O2 using a plasma enhanced chemical vapor deposition (PE CVD) tool under the following conditions:  
         [0021]    TEOS gas flow: preferably from about 50 to 2000 mgm and more preferably from about 100 to 1500 mgm;  
         [0022]    O 2  gas flow: preferably from about 50 to 2000 sccm and more preferably from about 100 to 1500 sccm;  
         [0023]    He gas flow: preferably from about 100 to 5000 sccm and more preferably from about 500 to 3000 sccm;  
         [0024]    pressure: preferably from about 2 to 15 Torr and more preferably from about 4 to 7 Torr;  
         [0025]    temperature: preferably from about 300 to 450° C. and more preferably from about 350 to 400° C.;  
         [0026]    HF RF power; preferably from about 100 to 1200 W and more preferably from about 200 to 700 W; and  
         [0027]    LF RF power; preferably from about 50 to 1000 W and more preferably from about 70 to 500 W; or  
         [0028]    (2) by the reaction of SiH 4  with O 2  using a high density plasma chemical vapor deposition (HDP CVD) tool under the following conditions:  
         [0029]    SiH 4  gas flow: preferably from about 20 to 100 sccm and more preferably from about 30 to 50 sccm;  
         [0030]    O 2  gas flow: preferably from about 30 to 150 sccm and more preferably from about 40 to 80 sccm;  
         [0031]    SiH 4 :O 2  ratio: preferably from about 1:2 to 1:1 and more preferably about 1:1.5;  
         [0032]    pressure: preferably from about 2 to 7 mTorr and more preferably from about 3 to 6 mTorr;  
         [0033]    temperature: preferably from about 250 to 500° C. and more preferably from about 300 to 400° C.;  
         [0034]    LF RF power; preferably from about 2000 to 5000 W and more preferably from about 2500 to 4500 W; and  
         [0035]    bias RF power; preferably from about 0 to 2000 W and more preferably from about 0 to 1000 W.  
         [0036]    SRO etch stop layer  18  has a refractive index (RI) of preferably from about 1.52 to 1.75, a dielectric constant (k) of from about 4.0 to 4.2. The Si-rich properties of SRO etch stop layer  18  provide for a much higher film density and greater hardness than other low-k materials which results in a high etch selectivity between SRO etch stop layer  18  and other low-k materials such as lower low-k dielectric layer  16  and upper low-k dielectric layer  20  (see below).  
         [0037]    An upper dielectric layer  20  is formed over SRO etch stop layer  18  to a thickness of preferably from about 2000 to 8000 Å and more preferably from about 3000 to 6000 Å. Upper dielectric layer  20  is generally also an intermetal dielectric (IMD) layer.  
         [0038]    Upper dielectric layer  20  is preferably comprised of a low-k dielectric material such as: inorganic low-k dielectrics such as hydrogen silsesquioxane; fluorine (F)-doped or carbon (C)-doped low-k dielectric materials such as FSG, CORAL™ manufactured by NVLS; BLACK DIAMOND™ manufactured by AMAT; SiLK™ manufactured by Dow Chemical or organic low-k materials, for example.  
         [0039]    Formation of SRO Hard Mask Layer  22   
         [0040]    A silicon-rich (SRO) hard mask layer  22  is formed over the upper dielectric layer  20  to a thickness of preferably from about 200 to 1000 Å and more preferably from about 300 to 700 Å.  
         [0041]    SRO hard mask layer  22  is preferably formed in an amine-free environment by either:  
         [0042]    (1) the reaction of TEOS with O 2  using a plasma enhanced chemical vapor deposition (PE CVD) tool under the following conditions:  
         [0043]    TEOS gas flow: preferably from about 50 to 2000 mgm and more preferably from about 100 to 1500 mgm;  
         [0044]    O 2  gas flow: preferably from about 50 to 2000 sccm and more preferably from about 100 to 1500 sccm;  
         [0045]    He gas flow: preferably from about 100 to 5000 sccm and more preferably from about 500 to 3000 sccm;  
         [0046]    pressure: preferably from about 2 to 15 Torr and more preferably from about 4 to 7 Torr;  
         [0047]    temperature: preferably from about 300 to 450° C. and more preferably from about 350 to 400° C.;  
         [0048]    HF RF power; preferably from about 100 to 1200 W and more preferably from about 200 to 700 W; and  
         [0049]    LF RF power; preferably from about 50 to 1000 W and more preferably from about 70 to 500 W; or  
         [0050]    (2) the reaction of SiH 4  with O 2  using a high density plasma chemical vapor deposition (HDP CVD) tool under the following conditions:  
         [0051]    SiH 4  gas flow: preferably from about 20 to 100 sccm and more preferably from about 30 to 50 sccm;  
         [0052]    O 2  gas flow: preferably from about 30 to 150 sccm and more preferably from about 40 to 80 sccm;  
         [0053]    SiH 4 :O 2  ratio: preferably from about 1:2 to 1:1 and more preferably about 1:1.5;  
         [0054]    pressure: preferably from about 2 to 7 mTorr and more preferably from about 3 to 6 mTorr;  
         [0055]    temperature: preferably from about 250 to 400° C. and more preferably from about 300 to 350° C.;  
         [0056]    LF RF power; preferably from about 2000 to 5000 W; and more preferably from about 2500 to 4500 W; and  
         [0057]    bias RF power; preferably from about 0 to 2000 W; and more preferably from about 0 to 1200 W.  
         [0058]    SRO hard mask layer  22  has a refractive index (RI) of preferably from about 1.52 to 1.75, a dielectric constant (k) of from about 4.0 to 4.2. The Si-rich properties of SRO hard mask layer  22  provide for a much higher film density and greater hardness than other low-k materials which results in a high etch selectivity between SRO hard mask layer  22  and other low-k materials such as upper low-k dielectric layer  20 .  
         [0059]    It is noted that under the teachings of the present invention, (1) just an SRO etch stop layer  18  may be formed for dual damascene interconnect formation, (2) just an SRO hard mask layer  22  may be formed; or (3) both an SRO etch stop layer  18  and an SRO hard mask layer  22  may be formed for dual damascene interconnect formation as shown in the figures.  
         [0060]    Patterning of Upper and Lower Dielectric Layers  20 ,  16   
         [0061]    As shown in FIG. 2, the upper and lower dielectric layers  20 ,  16  are patterned to form for example, via openings  24 ,  25  and trench openings  26  (only partially shown in FIGS. 2 and 3) where via openings  24  and the respective trench openings  26  comprise dual damascene openings  28  (again, only partially shown in FIGS. 2 and 3). In the formation of dual damascene openings  28 , SRO etch stop layer  18  is used as an etch stop layer only in the formation of trench openings  26 .  
         [0062]    As shown in FIG. 2, the upper and lower dielectric layers  20 ,  16  may be patterned using patterned photoresist layer, for example.  
         [0063]    Dielectric barrier layer  11  is also patterned to expose at least a portion of conductive structures  12  as shown in FIG. 2.  
         [0064]    For example, central via opening  25  is formed through the upper and lower dielectric layers  20 ,  16 . If only via openings  25  were formed, then SRO etch stop layer  18  could be omitted, hence upper and lower dielectric layers  20 ,  16  could be a single dielectric layer with an overlying SRO hard mask layer  22 . Via openings  25  need not be formed central to other openings, such as dual damascene openings  28 , and may be the only opening formed, just as dual damascene openings  28  need not be formed distal to any central via opening  25  and may be the only openings formed.  
         [0065]    Formation of Planarized Dual Damascene Structures  36  and Via Structures  38   
         [0066]    As shown in FIG. 3, photoresist layer  30  is removed as necessary, and: planarized metal dual damascene structures  36  are formed within dual damascene openings  28 ; and a planarized via structure, or plug,  38  is formed within central via opening  25  by methods and processes known in the art. Barrier metal layers  32  may be first formed within the dual damascene openings  28  and barrier metal layer  34  may be first formed within the central via opening  25  as shown in FIG. 3.  
         [0067]    Planarized metal structures  36 ,  38  are preferably comprised of copper (Cu), aluminum (Al), tungsten (W) or gold (Au) and are more preferably comprised of copper.  
         [0068]    Advantages of the Invention  
         [0069]    The advantages of one or more embodiments of the present invention include:  
         [0070]    1) formation of damascene structures without masking footing or via poisoning issues;  
         [0071]    2) reduction of the effective dielectric constant (k) of intermetal dielectric (IMD) layers;  
         [0072]    3) the SRO layers  18 ,  22  block the moisture absorption by FSG or low-k dielectric films such as IMD layers;  
         [0073]    4) the SRO layers  18 ,  22  block outgassing from FSG or low-k dielectric films such as IMD layers; and  
         [0074]    5) the SRO layers  18 ,  22  establish a sufficiently high etch selectivity as to FSG or low-k dielectric films such as IMD layers.  
         [0075]    While particular embodiments of the present invention have been illustrated and described, it is not intended to limit the invention, except as defined by the following claims.