Abstract:
A DC-to-DC converter includes first and second transistors that are connected in series between a supply voltage and ground and that are driven by PWM pulses. A junction of the transistors is connected to an inductance that is connected in series to a load. A first timing module determines a first time difference between a first edge of a first signal at the junction and a first edge of a second signal at a control terminal of the first transistor. A second timing module determines a second time difference between a second edge of the first signal and a second edge of the second signal. The first and second edges of the second signal respectively correspond to first and second edges of one of the PWM pulses. A delay module delays the first and second edges of the second signal respectively based on the first and second time differences.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of U.S. Provisional Application No. 61/567,938, filed on Dec. 7, 2011. The disclosure of the above application is incorporated herein by reference in its entirety. 
     
    
     FIELD 
       [0002]    The present disclosure relates generally to DC-to-DC voltage converters and more particularly to dead-time control in DC-to-DC voltage converters. 
       BACKGROUND 
       [0003]    The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure. 
         [0004]    Referring now to  FIGS. 1A and 1B , a DC-to-DC converter (hereinafter converter)  100  is shown. In  FIG. 1A , the converter  100  includes a control module  102 , a dead time control module  103 , a high-side switch M HS , a low-side switch T LS , an inductor L, a capacitor C out , and a load  104 . The high-side switch T HS  and the low-side switch T LS  (collectively switches) are connected in series. The control module  102  generates PWM pulses that control on and off times of the switches. The dead time control module  103  controls dead times of the switches (explained below). The inductor L is connected to a junction of the switches and is connected in series with the capacitor C out  as shown. The load  104  is connected in parallel to the capacitor C out  as shown. The converter  100  receives an input voltage V dd  and outputs an output voltage V out  across the load  104 . 
         [0005]    In  FIG. 1B , an inductor current I L  increases when the high-side switch T HS  is turned on while the low-side switch  TLS  is turned off and decreases when the high-side switch T HS  is turned off while the low-side switch T LS  is turned on. A voltage V LX  at the junction of the switches varies with time t as shown in  FIG. 1B . A time interval between opening (i.e., turning off) one switch (e.g., the high-side switch T HS ) and closing (i.e., turning on) another switch (e.g., the low-side switch T LS ) is called a dead-time and is shown by dotted circles in  FIG. 1B . Body diodes D HS  and D SS , which are respectively integrated with the high-side switch T HS  and the low-side switch T LS , conduct during dead times causing power loss. Power loss also occurs due to reverse recovery. Power losses due to conduction of the body diodes and reverse recovery are pronounced at high switching frequencies of the PWM pulses and low output voltages (V out ) of the converter. The dead times therefore need to be minimized to reduce the power losses. 
         [0006]    Referring now to  FIGS. 2A-2C , different modes of operation of a converter and corresponding dead times are shown. For example, in  FIG. 2A , the converter operates in a Buck continuous conduction mode (CCM) with a heavy load, where the inductor current I L  is always positive. In  FIG. 2B , the converter operates in a Buck or Boost forced CCM with a light load, where the inductor current I L  can be positive and negative. In  FIG. 2C , the converter operates in a Boost CCM with a heavy load, where the inductor current I L  is always negative. In each mode, the dead times shown need to be minimized to reduce the power losses. 
       SUMMARY 
       [0007]    A DC-to-DC converter shown in  FIG. 5A  includes first and second transistors each driven by pulse-width modulated (PWM) pulses and each having first and second terminals and a control terminal. The first terminal of the first transistor is connected to a supply voltage, the second terminal of the first transistor and the first terminal of the second transistor are connected to a node, the second terminal of the second transistor is connected to ground, and the node is connected to an inductance that is connected in series to a load. A first timing module determines a first time difference between a first edge of a first signal at the node and a first edge of a second signal at the control terminal of the first transistor. The first edge of the second signal corresponds to a first edge of one of the PWM pulses. A second timing module determines a second time difference between a second edge of the first signal at the node and a second edge of the second signal at the control terminal of the first transistor. The second edge of the second signal corresponds to a second edge of the one of the PWM pulses. A delay module delays the first edge of the second signal at the control terminal of the first transistor based on the first time difference and delays the second edge of the second signal at the control terminal of the first transistor based on the second time difference. 
         [0008]    A DC-to-DC converter shown in  FIG. 5B  includes first and second transistors each driven by pulse-width modulated (PWM) pulses and each having first and second terminals and a control terminal. The first terminal of the first transistor is connected to a supply voltage, the second terminal of the first transistor and the first terminal of the second transistor are connected to a node, the second terminal of the second transistor is connected to ground, and the node is connected to an inductance that is connected in series to a load. A first timing module determines a first time difference between a first edge of a first signal at the node and a first edge of a second signal at the control terminal of the second transistor. The first edge of the second signal corresponds to a first edge of one of the PWM pulses. A second timing module determines a second time difference between a second edge of the first signal at the node and a second edge of the second signal at the control terminal of the second transistor. The second edge of the second signal corresponds to a second edge of the one of the PWM pulses. A delay module delays the first edge of the second signal at the control terminal of the second transistor based on the first time difference and delays the second edge of the second signal at the control terminal of the second transistor based on the second time difference. 
         [0009]    A DC-to-DC converter shown in  FIG. 5C  includes first and second transistors each driven by pulse-width modulated (PWM) pulses and each having first and second terminals and a control terminal. The first terminal of the first transistor is connected to a supply voltage, the second terminal of the first transistor and the first terminal of the second transistor are connected to a node, the second terminal of the second transistor is connected to ground, and the node is connected to an inductance that is connected in series to a load. A first timing module determines a first time difference between a first edge of a first signal at the node and a first edge of a second signal at the control terminal of the first transistor. The first edge of the second signal corresponds to a first edge of one of the PWM pulses. A second timing module determines a second time difference between a second edge of the first signal at the node and a second edge of the second signal at the control terminal of the first transistor. The second edge of the second signal corresponds to a second edge of the one of the PWM pulses. A third timing module determines a third time difference between the first edge of the first signal at the node and a first edge of a third signal at the control terminal of the second transistor. The first edge of the third signal corresponds to the first edge of the one of the PWM pulses. A first delay module delays the first edge of the second signal at the control terminal of the first transistor based on the first time difference and delays the second edge of the second signal at the control terminal of the first transistor based on the second time difference. A second delay module delays the first edge of the third signal at the control terminal of the second transistor based on the third time difference and does not delay a second edge of the third signal at the control terminal of the second transistor, wherein the second edge of the third signal corresponds to the second edge of the one of the PWM pulses. 
         [0010]    A DC-to-DC converter shown in  FIG. 5D  includes first and second transistors each driven by pulse-width modulated (PWM) pulses and each having first and second terminals and a control terminal. The first terminal of the first transistor is connected to a supply voltage, the second terminal of the first transistor and the first terminal of the second transistor are connected to a node, the second terminal of the second transistor is connected to ground, and the node is connected to an inductance that is connected in series to a load. A first timing module determines a first time difference between a first edge of a first signal at the node and a first edge of a second signal at the control terminal of the first transistor. The first edge of the second signal corresponds to a first edge of the one of the PWM pulses. A second timing module determines a second time difference between the first edge of the first signal at the node and a first edge of a third signal at the control terminal of the second transistor. The first edge of the third signal corresponds to the first edge of the one of the PWM pulses. A third timing module determines a third time difference between a second edge of the first signal at the node and a second edge of the third signal at the control terminal of the second transistor. The second edge of the third signal corresponds to a second edge of the one of the PWM pulses. A first delay module delays the first edge of the second signal at the control terminal of the first transistor based on the first time difference and does not delay a second edge of the second signal at the control terminal of the first transistor. The second edge of the second signal corresponds to the second edge of the one of the PWM pulses. A second delay module delays the first edge of the third signal at the control terminal of the second transistor based on the second time difference and delays the second edge of the third signal at the control terminal of the second transistor based on the third time difference. 
         [0011]    A DC-to-DC converter shown in  FIG. 4A  includes first and second transistors each driven by pulse-width modulated (PWM) pulses and each having first and second terminals and a control terminal. The first terminal of the first transistor is connected to a supply voltage, the second terminal of the first transistor and the first terminal of the second transistor are connected to a node, the second terminal of the second transistor is connected to ground, and the node is connected to an inductance that is connected in series to a load. A first timing module determines a first time difference between a first edge of a first signal at the node and a first edge of a second signal at the control terminal of the first transistor. The first edge of the second signal corresponds to a first edge of one of the PWM pulses. A second timing module determines a second time difference between a second edge of the first signal at the node and a second edge of the second signal at the control terminal of the first transistor. The second edge of the second signal corresponds to a second edge of the one of the PWM pulses. A third timing module determines a third time difference between the second edge of the first signal at the node and a first edge of a third signal at the control terminal of the second transistor. The first edge of the second signal corresponds to the second edge of the one of the PWM pulses. A fourth timing module determines a fourth time difference between the first edge of the first signal at the node and a second edge of the third signal at the control terminal of the second transistor. The second edge of the third signal corresponds to the first edge of the one of the PWM pulses. A first delay module delays the first edge of the second signal at the control terminal of the first transistor based on the first time difference and delays the second edge of the second signal at the control terminal of the first transistor based on the second time difference. A second delay module delays the first edge of the third signal at the control terminal of the second transistor based on the third time difference and delays the second edge of the third signal at the control terminal of the second transistor based on the fourth time difference. 
         [0012]    Further areas of applicability of the present disclosure will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the disclosure. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]    The present disclosure will become more fully understood from the detailed description and the accompanying drawings, wherein: 
           [0014]      FIG. 1A  is a schematic of a DC-to-DC converter according to the prior art; 
           [0015]      FIG. 1B  depicts graphs of an inductor current (I L ) and a voltage (V LX )at a junction of switches of the DC-to-DC converter as functions of time according to the prior art; 
           [0016]      FIG. 2A  depicts graphs of I L  and V LX  as functions of time for a DC-to-DC converter operating in a Buck continuous conduction mode (CCM) with a heavy load; 
           [0017]      FIG. 2B  depicts graphs of I L  and V LX  as functions of time for a DC-to-DC converter operating in a Buck or Boost forced continuous conduction mode (CCM) with a light load; 
           [0018]      FIG. 2C  depicts graphs of I L  and V LX  as functions of time for a DC-to-DC converter operating in a Boost continuous conduction mode (CCM) with a heavy load; 
           [0019]      FIG. 3A  is a schematic of a DC-to-DC converter that reduces dead times in Buck or Boost forced continuous conduction mode (CCM) with a light load; 
           [0020]      FIG. 3B  depicts graphs of I L  and V LX  as functions of time for the DC-to-DC converter of  FIG. 3A  operating in a Buck continuous conduction mode (CCM) with a heavy load; 
           [0021]      FIG. 3C  depicts graphs of I L  and V LX  as functions of time for the DC-to-DC converter of  FIG. 3A  operating in a Buck or Boost forced continuous conduction mode (CCM) with a light load; 
           [0022]      FIG. 3D  depicts graphs of I L  and V LX  as functions of time for the DC-to-DC converter of  FIG. 3A  operating in a Boost continuous conduction mode (CCM) with a heavy load; 
           [0023]      FIG. 4A  is a schematic of a DC-to-DC converter according to the present disclosure that reduces dead times in various modes including Buck CCM with a heavy load, Buck or Boost forced CCM with a light load, and Boost CCM with a heavy load; 
           [0024]      FIG. 4B  depicts graphs of I L  and V LX  as functions of time for the DC-to-DC converter of  FIG. 4A  operating in a Buck continuous conduction mode (CCM) with a heavy load; 
           [0025]      FIG. 4C  depicts graphs of I L  and V LX  as functions of time for the DC-to-DC converter of  FIG. 4A  operating in a Buck or Boost forced continuous conduction mode (CCM) with a light load; 
           [0026]      FIG. 4D  depicts graphs of I L  and V LX  as functions of time for the DC-to-DC converter of  FIG. 4A  operating in a Boost continuous conduction mode (CCM) with a heavy load; 
           [0027]      FIG. 5A  is a schematic of a DC-to-DC converter according to the present disclosure that reduces dead times in Boost CCM using two feedback loops for a high-side switch of the converter; 
           [0028]      FIG. 5B  is a schematic of a DC-to-DC converter according to the present disclosure that reduces dead times in Buck CCM using two feedback loops for a low-side switch of the converter; 
           [0029]      FIG. 5C  is a schematic of a DC-to-DC converter according to the present disclosure that reduces dead times in Boost mode using two feedback loops for a high-side side switch of the converter and one feedback loop for a low-side switch of the converter; 
           [0030]      FIG. 5D  is a schematic of a DC-to-DC converter according to the present disclosure that reduces dead times in Buck mode using one feedback loop for a high-side switch of the converter and two feedback loop for a low-side switch of the converter; 
           [0031]      FIG. 6A  is a schematic of the DC-to-DC converter of  FIG. 4A  further comprising gate sensors and common-mode feedback modules according to the present disclosure; and 
           [0032]      FIG. 6B  is a schematic of a charge pump used in the DC-to-DC converter of  FIG. 6A . 
       
    
    
     DETAILED DESCRIPTION 
       [0033]    The following description is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. As used herein, the phrase at least one of A, B, and C should be construed to mean a logical (A or B or C), using a non-exclusive logical or. It should be understood that steps within a method may be executed in different order without altering the principles of the present disclosure. 
         [0034]    As used herein, the term module may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC); an electronic circuit; a combinational logic circuit; a field programmable gate array (FPGA); a processor (shared, dedicated, or group) that executes code; other suitable components that provide the described functionality; or a combination of some or all of the above, such as in a system-on-chip. The term module may include memory (shared, dedicated, or group) that stores code executed by the processor. 
         [0035]    The term code, as used above, may include software, firmware, and/or microcode, and may refer to programs, routines, functions, classes, and/or objects. The term shared, as used above, means that some or all code from multiple modules may be executed using a single (shared) processor. In addition, some or all code from multiple modules may be stored by a single (shared) memory. The term group, as used above, means that some or all code from a single module may be executed using a group of processors or a group of execution engines. For example, multiple cores and/or multiple threads of a processor may be considered to be execution engines. In various implementations, execution engines may be grouped across a processor, across multiple processors, and across processors in multiple locations, such as multiple servers in a parallel processing arrangement. In addition, some or all code from a single module may be stored using a group of memories. 
         [0036]    The apparatuses and methods described herein may be implemented by one or more computer programs executed by one or more processors. The computer programs include processor-executable instructions that are stored on a non-transitory tangible computer readable medium. The computer programs may also include stored data. Non-limiting examples of the non-transitory tangible computer readable medium are nonvolatile memory, magnetic storage, and optical storage. 
         [0037]    The present disclosure relates to reducing dead times (i.e., conduction times of body diodes of high and low side drivers) of DC-to-DC converters. Specifically, the present disclosure relates to reducing the dead times in various modes of operation of the DC-to-DC converters irrespective of load conditions. For example, the dead times can be reduced according to the present disclosure in DC-to-DC converters operating in Buck continuous conduction mode (CCM) with a heavy load, Buck or Boost forced CCM with a light load, and Boost CCM with a heavy load. 
         [0038]    One way to reduce the dead times is to prevent the body diodes from conducting and turning on the high-side switch T HS  or the low-side switch T LS  before the respective body diodes can conduct. Accordingly, the load current I L  will flow through the high-side switch T HS  or the low-side switch T LS  instead of flowing through the respective body diodes. 
         [0039]    Referring now to  FIGS. 3A-3D , a DC-to-DC converter (hereinafter converter)  200  that reduces dead times in Buck or Boost forced CCM with a light load is shown. In  FIG. 3A , the converter  200  includes the high-side switch T HS , the low-side switch T LS , the inductor L, the capacitor C out , and the load  104 . The high-side switch T HS  and the low-side switch T LS  (collectively switches) are connected in series. The inductor L is connected to the junction of the switches and is connected in series with the capacitor C out  as shown. The load  104  is connected in parallel to the capacitor C out  as shown. The PWM pulses generated by the PWM module  102  (not shown) control the on and off times of the switches. The converter  200  receives the input voltage V dd  and outputs the output voltage V out  across the load  104 . 
         [0040]    To reduce the dead times, the converter  200  further includes a feedback loop for each switch. The feedback loops compare timings of gate and drain voltage transitions of the switches. The feedback loops delay the PWM pulses that are output to the gates of the switches based on the timings to reduce the dead times. 
         [0041]    The word transition as used herein means a rising edge or a falling edge of a signal (e.g., a PWM pulse, a voltage, or a current) when the signal begins to rise from a low value or fall from a high value, respectively. Accordingly, a gate turn-on transition for the high-side switch T HS  is a falling edge of a gate-to-source voltage of the high-side switch T HS  since the high-side switch T HS  is shown as a PMOS device. A gate turn-off transition for the high-side switch T HS  is a rising edge of the gate-to-source voltage of the high-side switch T HS  since the high-side switch T HS  is shown as a PMOS device. 
         [0042]    Conversely, a gate turn-on transition for the low-side switch T LS  is a rising edge of a gate-to-source voltage of the low-side switch T LS  since the low-side switch T LS  is shown as an NMOS device. A gate turn-off transition for the low-side switch T LS  is a falling edge of the gate-to-source voltage of the low-side switch T LS  since the low-side switch T LS  is shown as an NMOS device. Similarly, a falling V LX  transition is a falling edge of the voltage V LX , and a rising V LX  transition is a rising edge of the voltage V LX . 
         [0043]    The feedback loop for the high-side switch T HS  includes a timing module  202 , a charge pump  204 , a delay module  206 , and an inverting driver  208 . The feedback loop for the low-side switch T LS  includes a timing module  210 , a charge pump  212 , a delay module  214 , and an inverting driver  216 . 
         [0044]    The inputs of the delay modules  206  and  214  receive the PWM pulses from the PWM module  102 . The delay module  206  delays a rising edge of a PWM pulse (since T HS  is a PMOS device) based on an output voltage of the charge pump  204  and propagates a falling edge of a PWM pulse without delay. The inverting driver  208  inverts the output of the delay module  206  and outputs the inverted output of the delay module  206  to the gate of the high-side switch T HS . The delay module  214  delays a falling edge of a PWM pulse (since T LS  is an NMOS device) based on an output voltage of the charge pump  212  and propagates a rising edge of a PWM pulse without delay. The inverting driver  216  inverts the output of the delay module  214  and outputs the inverted output of the delay module  214  to the gate of the low-side switch T LS . 
         [0045]    In the feedback loop for the high-side switch T HS , the timing module  202  has an inverting input and a non-inverting input. The inverting input is connected to the gate of the high-side switch T HS  (since T HS  is a PMOS device). The non-inverting input is connected to the junction of the switches. Accordingly, the inverting input senses a falling edge of a gate voltage of the high-side switch T HS , and the non-inverting input senses a rising edge of a voltage V LX  at the junction of the switches. 
         [0046]    Suppose a falling transition of the gate voltage of the high-side switch T HS  occurs at time t 1 , and a rising transition of the voltage V LX  occurs at time t 2 . The timing module  202  has two outputs: out 1  and out 2 . If t 1  is before t 2 , the timing module  202  outputs a pulse having a pulse width (t 2 −t 1 ) on the output out 1 , and out 2  is low. Conversely, if t 2  is before t 1 , out 1  is low, and the timing module  202  outputs a pulse having a pulse width (t 1 −t 2 ) on the output out 2 . 
         [0047]    The charge pump  204  has two inputs that respectively receive the outputs out 1  and out 2  of the timing module  202 , and an output that outputs a voltage that increases or decreases based on the outputs out 1  and out 2  of the timing module  202 . For example, the output voltage of the charge pump  204  increases when the timing module  202  outputs a pulse on the output out 1  and decreases when the timing module  202  outputs a pulse on the output out 2 . The amount by which the output of the charge pump increases or decreases depends respectively on the pulse widths on the outputs out 1  and out 2 . 
         [0048]    The delay module  206  delays a rising edge of a PWM pulse. The amount of delay is based on the output of the charge pump  204 . For example, the delay increases or decreases based on whether the output of the charge pump  204  increases or decreases. Further, the amount by which the delay increases or decreases depends on the amount by which the output of the charge pump  204  increases or decreases. The inverting driver  208  inverts the output of the delay module  206  and outputs the inverted output of the delay module  206  to the gate of the high-side switch T HS . 
         [0049]    In the feedback loop for the low-side switch T LS , the non-inverting input of the timing module  210  is connected to the gate of the low-side switch T LS  (since T LS  is an NMOS device). The inverting input is connected to the junction of the switches. Accordingly, the non-inverting input senses a rising edge of a gate voltage of the low-side switch T LS , and the inverting input senses a falling edge of the voltage V LX  at the junction of the switches. 
         [0050]    Suppose a falling transition of the voltage V LX  occurs at time t 1 , and a rising transition of the gate voltage of the low-side switch T LS  occurs at time t 2 . The timing module  210  has two outputs: out 1  and out 2 . If t 2  is before t 1 , the timing module  210  outputs a pulse having a pulse width (t 1 −t 2 ) on the output out 1 , and out 2  is low. If t 1  is before t 2 , out 1  is low, and the timing module  210  outputs a pulse having a pulse width (t 2 −t 1 ) on the output out 2 . 
         [0051]    The charge pump  212  has two inputs that respectively receive the outputs out 1  and out 2  of the timing module  210 , and an output that outputs a voltage that increases or decreases based on the outputs out 1  and out 2  of the timing module  210 . For example, the output voltage of the charge pump  212  increases when the timing module  210  outputs a pulse on the output out 1  and decreases when the timing module  210  outputs a pulse on the output out 2 . The amount by which the output of the charge pump increases or decreases depends respectively on the pulse widths of the outputs out 1  and out 2 . 
         [0052]    The delay module  214  delays a falling edge of a PWM pulse. The amount of delay is based on the output of the charge pump  212 . For example, the delay increases or decreases based on whether the output of the charge pump  212  increases or decreases. Further, the amount by which the delay increases or decreases depends on the amount by which the output of the charge pump  212  increases or decreases. The inverting driver  216  inverts the output of the delay module  214  and outputs the inverted output of the delay module  214  to the gate of the low-side switch T LS . 
         [0053]    In use, when the high-side switch T HS  is off and the low-side switch T LS  is on, a rising edge of a PWM pulse is output to turn on the high-side switch T HS . The delay modules  206  and  214  receive the rising edge of the PWM pulse. The delay module  214  propagates the rising edge of the PWM pulse without delay. The inverting driver  216  outputs a falling edge to the gate of the low-side switch T LS , which turns off the low-side switch T LS . If the inductor current flows into the junction of the switches at that time, the voltage V LX  starts to increase. 
         [0054]    The timing module  202  senses a time difference between a time at which the voltage V LX  has risen and a time at which the gate-to-source voltage of the high-side switch T HS  transitions and begins to fall (i.e., the gate turn-on transition of the high-side switch T HS ). The delay module  206  delays the gate turn-on transition of the high-side switch T HS  based on the time difference to reduce this time difference, i.e., the dead time. 
         [0055]    Conversely, when the high-side switch T HS  is on and the low-side switch T LS  is off, a falling edge of a PWM pulse is output to turn off the high-side switch T HS . The delay modules  206  and  214  receive the falling edge of the PWM pulse. The delay module  206  propagates the falling edge of the PWM pulse without delay. The inverting driver  208  outputs a rising edge to the gate of the high-side switch T HS , which turns off the high-side switch T HS . If the inductor current flows out of the junction of the switches at that time, the voltage V LX  starts to decrease. 
         [0056]    The timing module  210  senses a time difference between a time at which the voltage V LX  has fallen and a time at which the gate-to-source voltage of the low-side switch T LS  transitions and begins to rise (i.e., the gate turn-on transition of the low-side switch T LS ). The delay module  214  delays the gate turn-on transition of the low-side switch T LS  based on the time difference to reduce this time difference, i.e., the dead time. 
         [0057]    The delays generated by the delay modules  206  and  214  adjust (reduce) the dead times as shown in  FIG. 3C . The delays, however, reduce the dead times only when the converter  200  operates in Buck or Boost CCM with a light load. The delays increase the dead times when the inductor current flows only out of the junction of the switches (i.e., when the converter  200  operates in Buck CCM with a heavy load) as shown in  FIG. 3B  and when the inductor current flows only into the junction of the switches (i.e., when the converter  200  operates in Boost CCM with a heavy load) as shown in  FIG. 3D . 
         [0058]    Referring now to  FIGS. 4A-4D , a converter  300  that reduces dead times in various modes is shown. The converter  300  reduces dead times irrespective of load conditions. For example, the converter  300  reduces dead times when operating in Buck CCM with a heavy load, Buck or Boost forced CCM with a light load, and Boost CCM with a heavy load. 
         [0059]    In  FIG. 4A , the converter  300  includes all of the components of the converter  200  shown in  FIG. 3A  except the delay modules  206  and  214 . The converter  300  further includes an additional feedback loop for the high-side switch T HS  comprising a timing module  306  and a charge pump  308  and an additional feedback loop for the low-side switch T LS  comprising a timing module  310  and a charge pump  312 . The converter  300  also includes a delay module  302  for the high-side switch T HS  and a delay module  304  for the low-side switch T LS . The inputs of the delay modules  302  and  304  receive the PWM pulses from the PWM module  102 . 
         [0060]    The delay module  302  delays a rising edge of a PWM pulse based on the output of the timing module  202  and the charge pump  204  and delays a falling edge of a PWM pulse based on an output of the timing module  306  and the charge pump  308 . The delay module  304  delays a falling edge of a PWM pulse based on the output of the timing module  210  and the charge pump  212  and delays a rising edge of a PWM pulse based on an output of the timing module  310  and the charge pump  312 . 
         [0061]    The connections and functions of the timing module  202 , the charge pump  204 , the timing module  210 , and the charge pump  212  are the same as in the converter  200 . The connections and functions of the timing module  306 , the charge pump  308 , the timing module  310 , and the charge pump  312  are as follows. 
         [0062]    In the feedback loop for the high-side switch T HS , the timing module  306  has an inverting input and a non-inverting input. The inverting input is connected to the junction of the switches, and the non-inverting input is connected to the gate of the high-side switch T HS . Accordingly, the inverting input senses a falling edge of the voltage V LX  at the junction of the switches, and the non-inverting input senses a rising edge of the gate voltage of the high-side switch T HS . 
         [0063]    Suppose a rising transition of the gate voltage of the high-side switch T HS  occurs at time t 1 , and a falling transition of the voltage V LX  occurs at time t 2 . The timing module  306  has two outputs: out 1  and out 2 . If t 1  is before t 2 , the timing module  306  outputs a pulse having a pulse width (t 2 −t 1 ) on the output out 1 , and out 2  is low. Conversely, if t 2  is before t 1 , out 1  is low, and the timing module  306  outputs a pulse having a pulse width (t 1 −t 2 ) on the output out 2 . 
         [0064]    The charge pump  308  has two inputs that respectively receive the outputs out 1  and out 2  of the timing module  306 , and an output that outputs a voltage that increases or decreases based on the outputs out 1  and out 2  of the timing module  306 . For example, the output voltage of the charge pump  308  increases when the timing module  306  outputs a pulse on the output out 1  and decreases when the timing module  306  outputs a pulse on the output out 2 . The amount by which the output of the charge pump increases or decreases depends respectively on the pulse widths on the outputs out 1  and out 2 . 
         [0065]    The delay module  302  delays a falling edge of a PWM pulse by an amount based on the output of the charge pump  308 . For example, the delay increases or decreases based on whether the output of the charge pump  308  increases or decreases. Further, the amount by which the delay increases or decreases depends on the amount by which the output of the charge pump  308  increases or decreases. The inverting driver  208  inverts the output of the delay module  302  and outputs the inverted output of the delay module  302  to the gate of the high-side switch T HS . 
         [0066]    In the feedback loop for the low-side switch T LS , the inverting input of the timing module  310  is connected to the gate of the low-side switch T LS , and the non-inverting input is connected to the junction of the switches. Accordingly, the inverting input senses a falling edge of the gate voltage of the low-side switch T LS , and the non-inverting input senses a rising edge of the voltage V D (at the junction of the switches. 
         [0067]    Suppose a falling transition of the gate voltage of the low-side switch T LS  occurs at time t 1  and a rising transition of the voltage V LX  occurs at time t 2 . The timing module  310  has two outputs: out 1  and out 2 . If t 1  is before t 2 , the timing module  310  outputs a pulse having a pulse width (t 2 −t 1 ) on the output out 1 , and out 2  is low. If t 2  is before t 1 , out 1  is low, and the timing module  310  outputs a pulse having a pulse width (t 1 −t 2 ) on the output out 2 . 
         [0068]    The charge pump  312  has two inputs that respectively receive the outputs out 1  and out 2  of the timing module  310 , and an output that outputs a voltage that increases or decreases based on the outputs out 11  and out 2  of the timing module  310 . For example, the output voltage of the charge pump  312  increases when the timing module  310  outputs a pulse on the output out 1  and decreases when the timing module  310  outputs a pulse on the output out 2 . The amount by which the output of the charge pump increases or decreases depends respectively on the pulse widths of the outputs out 1  and out 2 . 
         [0069]    The delay module  304  delays a rising edge of a PWM pulse by an amount based on the output of the charge pump  312 . For example, the delay increases or decreases based on whether the output of the charge pump  312  increases or decreases. Further, the amount by which the delay increases or decreases depends on the amount by which the output of the charge pump  312  increases or decreases. The inverting driver  216  inverts the output of the delay module  304  and outputs the inverted output of the delay module  304  to the gate of the low-side switch T LS . 
         [0070]    In use, when a rising edge of the PWM pulse is received, the delay module  302  delays the rising edge according to the feedback received from the timing module  202  and the charge pump  204 , and the delay module  304  delays the rising edge according to the feedback received from the timing module  310  and the charge pump  312 . When a falling edge of the PWM pulse is received, the delay module  302  delays the falling edge according to the feedback received from the timing module  306  and the charge pump  308 , and the delay module  304  delays the falling edge according to the feedback received from the timing module  210  and the charge pump  212 . 
         [0071]    For example, suppose that the high-side switch T HS  is off, the low-side switch T LS  is on, and the delay modules  302  and  304  receive a rising edge of the PWM pulse to turn on the high-side switch T HS . Suppose also that the inductor current I L  flows out of the junction of the switches at that time. Since the rising edge of the PWM pulse turns on the high-side switch T HS , the rising edge of the PWM pulse may be called a turn-on transition of the converter  300 . 
         [0072]    In the feedback loop of the high-side switch T HS , the gate-to-source voltage of the high-side switch T HS  falls before the voltage V LX  can rise. Accordingly, at the inputs of the timing module  202 , time t 1  at which the gate-to-source voltage of the high-side switch T HS  starts falling is before time t 2  at which the voltage V LX  starts rising. In other words, the gate turn-on transition of the high-side switch T HS  occurs earlier than a rising V LX  transition. The output out 1  of the timing module  202  outputs a pulse of pulse width (t 2 −t 1 ) at the output out 1 , and the output out 2  of the timing module  202  is low. The output voltage of the charge pump  204  increases proportionally to the pulse width (t 2 −t 1 ). The delay module  302  delays the rising edge of the PWM pulse proportionally to the increase in the output voltage of the charge pump  204 . The process continues until the output voltage of the charge pump  204  rails at V dd . The amount of delay continues to increase and reaches a maximum value when the output voltage of the charge pump  204  rails at V dd . At this point the feedback loop of the high-side switch T HS  is saturated. 
         [0073]    In the feedback loop of the low-side switch T LS , the gate-to-source voltage of the low-side switch T LS  is falling, and the voltage V D (is rising. Suppose that at the inputs of the timing module  310 , time t 1  at which the gate-to-source voltage of the high-side switch T HS  starts falling is later than time t 2  at which the voltage V LX  starts rising. In other words, the gate turn-off transition of the low-side switch T LS  occurs later than a rising V LX  transition. The output out 2  of the timing module  310  outputs a pulse of pulse width (t 1 −t 2 ) at the output out 2 , and the output out 1  of the timing module  310  is low. The output voltage of the charge pump  312  decreases proportionally to the pulse width (t 1 −t 2 ). The delay module  304  decreases the delay of the rising edge of the PWM pulse proportionally to the decrease in the output voltage of the charge pump  312 . Over several cycles (i.e., PWM pulses) the amount of delay continues to decrease until a time difference between the times t 1  and t 2  becomes nearly zero. 
         [0074]    At this point, the dead time during the turn-on transitions of the converter  300  is nearly zero when the inductor current I L  flows out of the junction of the switches at that time. In this manner, when the inductor current I L  flows out of the junction of the switches during the rising edges of the PWM pulses (i.e., during the turn on transitions of the converter  300 ), the feedback loop of the high-side switch T HS  saturates, and the feedback loop of the low-side switch T LS  adjusts (reduces) the dead time during the rising edges of the PWM pulse (i.e., during the turn-on transitions of the converter  300 ). 
         [0075]    Now suppose that the high-side switch T HS  is off, the low-side switch  TLS  is on, the delay modules  302  and  304  receive a rising edge of the PWM pulse to turn on the high-side switch T HS , and the inductor current I L  flows into the junction of the switches at that time. In the feedback loop of the low-side switch T LS , the gate-to-source voltage of the low-side switch  TLS  falls before the voltage V LX  can rise. Accordingly, at the inputs of the timing module  310 , time t 1  at which the gate-to-source voltage of the low-side switch T LS  starts falling is before time t 2  at which the voltage V LX  starts rising. In other words, the gate turn-off transition of the low-side switch T LS  occurs earlier than a rising V LX  transition. The output out 1  of the timing module  310  outputs a pulse of pulse width (t 2 −t 1 ) at the output out 1 , and the output out 2  of the timing module  310  is low. The output voltage of the charge pump  312  increases proportionally to the pulse width (t 241 ). The delay module  304  delays the rising edge of the PWM pulse proportionally to the increase in the output voltage of the charge pump  312 . The process continues until the output voltage of the charge pump  312  rails at V dd . The amount of delay continues to increase and reaches a maximum value when the output voltage of the charge pump  312  rails at V dd . At this point the feedback loop of the low-side switch  TLS  is saturated. 
         [0076]    In the feedback loop of the high-side switch T HS , the gate-to-source voltage of the high-side switch T HS  is falling, and the voltage V LX  is rising. Suppose that at the inputs of the timing module  202 , time t 1  at which the gate-to-source voltage of the high-side switch T HS  starts falling is later than time t 2  at which the voltage V LX  starts rising. In other words, the gate turn-on transition of the high-side switch T HS  occurs later than a rising V LX  transition. The output out 2  of the timing module  202  outputs a pulse of pulse width (t 1 −t 2 ) at the output out 2 , and the output out 1  of the timing module  202  is low. The output voltage of the charge pump  204  decreases proportionally to the pulse width (t 1 −t 2 ). The delay module  302  decreases the delay of the rising edge of the PWM pulse proportionally to the decrease in the output voltage of the charge pump  204 . Over several cycles (i.e., PWM pulses) the amount of delay continues to decrease until a time difference between the times t 1  and t 2  becomes nearly zero. 
         [0077]    At this point, the dead time during the turn-on transitions of the converter  300  is nearly zero when the inductor current I L  flows into the junction of the switches at that time. In this manner, when the inductor current I L  flows into the junction of the switches during the rising edges of the PWM pulse (i.e., during the turn-on transitions of the converter  300 ), the feedback loop of the low-side switch T LS  saturates, and the feedback loop of the high-side switch T HS  adjusts (reduces) the dead time during the rising edges of the PWM pulse (i.e., during the turn-on transitions of the converter  300 ). 
         [0078]    Similar analysis can be obtained during a turn-off transition of the converter  300  (i.e., when a falling edge of a PWM pulse is output to turn off the high-side switch T HS ). The delays generated by the delay modules  302  and  304  adjust (reduce) the dead times when the converter  300  operates in various modes irrespective of load conditions as shown in  FIGS. 4B-4D . 
         [0079]    In summary, the timing module  306  senses a time difference between a time at which the voltage V LX  transitions and begins to fall and a time at which the gate-to-source voltage of the high-side switch T HS  transitions and begins to rise (i.e., the gate turn-off transition of the high-side switch T HS ). The delay module  302  delays the gate turn-off transition of the high-side switch T HS  by delaying the falling edge of the PWM pulse based on the time difference to reduce this time difference, i.e., the dead time. 
         [0080]    The timing module  202  senses a time difference between a time at which the voltage V LX  transitions and begins to rise and a time at which the gate-to-source voltage of the high-side switch T HS  transitions and begins to fall (i.e., the gate turn-on transition of the high-side switch T HS ). The delay module  302  delays the gate turn-on transition of the high-side switch T HS  by delaying the rising edge of the PWM pulse based on the time difference to reduce this time difference, i.e., the dead time. 
         [0081]    The timing module  310  senses a time difference between a time at which the voltage V LX  transitions and begins to rise and a time at which the gate-to-source voltage of the low-side switch T LS  transitions and begins to fall (i.e., the gate turn-off transition of the low-side switch T LS ). The delay module  304  delays the gate turn-off transition of the low-side switch T LS  by delaying the rising edge of the PWM pulse based on the time difference to reduce this time difference, i.e., the dead time. 
         [0082]    The timing module  210  senses a time difference between a time at which the voltage V LX  transitions and begins to fall and a time at which the gate-to-source voltage of the low-side switch T LS  transitions and begins to rise (i.e., the gate turn-on transition of the low-side switch T LS ). The delay module  304  delays the gate turn-on transition of the low-side switch T LS  by delaying the falling edge of the PWM pulse based on the time difference to reduce this time difference, i.e., the dead time. 
         [0083]    Referring now to  FIGS. 5A-5D , additional converters that reduce dead times are shown. Each of the converters operates in a particular mode and reduces dead times in the particular mode using a plurality but not all of the feedback loops shown in  FIG. 4A . For example, in  FIG. 5A , a converter  400 - 1  operating in Boost CCM reduces dead times using only the delay module  302 , the timing module  306 , the charge pump  308 , the timing module  202 , and the charge pump  204 . In  FIG. 5B , a converter  400 - 2  operating in Buck CCM reduces dead times using only the delay module  304 , the timing module  310 , the charge pump  312 , the timing module  210 , and the charge pump  212 . In  FIG. 5C , a converter  400 - 3  operating in Boost mode reduces dead times using only the delay modules  302  and  304 , the timing module  306 , the charge pump  308 , the timing module  202 , the charge pump  204 , the timing module  210 , and the charge pump  212 . In  FIG. 5D , a converter  400 - 4  operating in Buck mode reduces dead times using only the delay modules  302  and  304 , the timing module  202 , the charge pump  204 , the timing module  310 , the charge pump  312 , the timing module  210 , and the charge pump  212 . 
         [0084]    Referring now to  FIGS. 6A and 6B , a converter  500  comprising a plurality of gate sensors and a plurality of common-mode feedback modules is shown. In  FIG. 6A , the converter  500  includes all of the components of the converter  300  shown in  FIG. 4A . The converter  500  further includes gate sensors  502  and  504  and common-mode feedback modules  506  and  508 . The gate sensors  502  and  504  trip at gate-to-source voltages between the plateau voltages and gate-to-source threshold voltages of the high-side switch T HS  and the low-side switch T LS , respectively. The common-mode feedback modules  506  and  508  prevent the charge pumps from railing to V dd . 
         [0085]    A plateau voltage is defined in practice as the gate-to-source voltage at which the transistor delivers a current substantially equal to the inductor current. The gate-to-source threshold voltage is a gate-to-source voltage at which the transistor turns on. 
         [0086]    The trip voltages of the gate sensors  502  and  504  may be adjusted between the plateau voltage and the gate-to-source threshold voltage based on the inductor current I L . For example, for light load, the trip voltage may be set closer to the gate-to-source threshold voltage, and for heavy load, the trip voltage may be set farther from the gate-to-source threshold voltage and closer to the plateau voltage. The adjustment of the trip voltages of the gate sensors  502  and  504  based on the inductor current I L  further compensates for variations in dead time as a function of load current. 
         [0087]    In  FIG. 6A , each of the common-mode feedback modules  506 ,  508  includes a circuit that functions as a charge-injecting common-mode voltage controller. These modules prevent the charge pumps from railing to V dd  or ground. 
         [0088]    In  FIG. 6B , an example of a charge pump  550  is shown. The charge pump  550  includes current sources  552  and  554  and switches  556  and  558 . The switches  556  and  558  of a charge pump (e.g., one of the charge pumps  308 ,  204 ,  312 , or  212 ) are respectively connected to the outputs out 1  and out 2  of a corresponding timing module (e.g., one of the timing modules  306 ,  202 ,  310 , or  210 ) to which the charge pump is connected. 
         [0089]    Throughout the present disclosure, the high-side switch T HS  is shown as a PMOS device, and the low-side switch T LS  is shown as an NMOS device for example only. Instead, the high-side switch T HS  can be an NMOS device, and the low-side switch T LS  can be a PMOS device. Accordingly, while polarities of various signals including PWM pulses, voltages, and currents are discussed throughout the disclosure according to examples shown, the polarities will be opposite if the high-side switch T HS  is an NMOS device, and the low-side switch T LS  is a PMOS device instead. 
         [0090]    The broad teachings of the disclosure can be implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, the specification, and the following claims.