Abstract:
A MOSFET device for RF applications that uses a trench gate in place of the lateral gate used in lateral MOSFET devices is described. The trench gate in the devices of the invention is provided with a single, short channel for high frequency gain. The device of the invention is also provided with an asymmetric oxide in the trench gate, as well as LDD regions that lower the gate-drain capacitance for improved RF performance. Such features allow these devices to maintain the advantages of the LDMOS structure (better linearity), thereby increasing the RF power gain. The trench gate LDMOS of the invention also reduces the hot carrier effects when compared to regular LDMOS devices by reducing the peak electric field and impact ionization. Thus, the devices of the invention will have a better breakdown capability.

Description:
FIELD OF THE INVENTION 
   The invention generally relates to methods for fabricating integrated circuits (ICs) and semiconductor devices and the resulting structures. More particularly, the invention relates to metal oxide semiconductor field effect transistor (MOSFET) devices and methods for making such devices. Even more particularly, the invention relates to trench gate laterally-diffused MOSFET devices and methods for making such devices. 
   BACKGROUND OF THE INVENTION 
   In IC fabrication, devices such as transistors may be formed on a semiconductor wafer or substrate, which is typically made of silicon. MOSFET devices are widely used in numerous electronic apparatus, including automotive electronics, disk drives and power supplies. Generally, these apparatus function as switches and are used to connect a power supply to a load. 
   One of the applications in which MOSFET devices have been used is for radio frequency (RF) applications. Such “RF” MOSFET devices generally utilize standard lateral transistors. See, for example, the lateral MOSFET device described in U.S. Pat. No. 5,949,104, as well as the device illustrate in  FIG. 1 . Such lateral MOSFET devices often have a diffused source that allows a backside contact for improved thermal and parasitic reductions. 
   Recent advances in lateral (or laterally-diffused) MOSFET (LDMOS) devices have improved the performance and cost characteristics of lateral MOSFET devices when compared to vertical MOSFET devices for RF power amplifiers in base stations applications. Such RF LDMOS devices have been particularly useful for wireless base station applications. The RF vertical (or vertically-diffused) VDMOS structure unfortunately suffers from certain limitations relative to the LDMOS such as high output capacitance (which decreases efficiency), decreased power gain, narrowing of the usable bandwidth, and source inductance that decreases the operating efficiency. 
   It has been proposed to use a trench gate in place of the lateral gate so often used in RF MOSFET devices. See, for example, U.S. Pat. No. 6,400,003. The proposed structure in that patent, unfortunately suffers from several setbacks. First, the trench gate has a dual diffused channel on both sides of the trench gate. Second, the drain region extends entirely around the body portion. 
   SUMMARY OF THE INVENTION 
   The invention provides a MOSFET device for RF applications that uses a trench gate in place of the lateral gate used in lateral MOSFET devices. The trench gate in the devices of the invention is provided with a single, short channel for high frequency gain. The device of the invention is also provided with an asymmetric oxide in the trench gate, as well as LDD regions that lower the gate-drain capacitance for improved RF performance. Such features allow these devices to maintain the advantages of the LDMOS structure (better linearity), thereby increasing the RF power gain. The trench gate LDMOS of the invention also reduces the hot carrier effects when compared to regular LDMOS devices by reducing the peak electric field and impact ionization. Thus, the devices of the invention will have a better breakdown capability. 
   The invention includes a MOSFET device comprising a trench gate structure containing an asymmetric insulating layer and a plurality of drift drain regions with a first drift region extending under the gate structure. The invention also includes a semiconductor device and an electronic apparatus containing such a MOSFET device. The invention further includes a RF MOSFET device comprising a trench gate structure containing a single channel and an asymmetric oxide layer and a plurality of drift drain regions with a first drift region extending under the gate structure. The invention still further includes a MOSFET device, comprising a trench gate structure containing an asymmetric insulating layer and a plurality of drift drain regions with a first drift region extending under the gate structure. 
   The inventions also includes a method for making a MOSFET device by providing a trench gate structure containing an asymmetric insulating layer and providing a plurality of drift drain regions with a first drift region extending under the gate structure. The invention further includes a method for making a making a MOSFET device by providing a substrate, providing a trench in the substrate, filling the trench with an insulating layer, providing a second trench in the insulating layer such that the second trench is not symmetric relative to the first trench, filling the second trench with a conductive material, and providing a plurality of dopant regions adjacent the trench with a first dopant region extending under the trench. The invention still further includes a method for making a making a MOSFET device by providing a substrate having an epitaxial upper surface, providing a trench in the upper surface, filling the trench with an oxide layer, providing a second trench in the oxide layer so that the second trench is not symmetric relative to the first trench, filling the second trench with a conductive material, and providing a plurality of dopant regions adjacent the trench and within the epitaxial layer, wherein the plurality of dopant regions contains a first dopant region extending under the trench and a second dopant region with a dopant concentration higher than the first dopant region. The invention also includes MOSFET devices made by such methods. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIGS. 1–6  are views of one aspect of the MOSFET devices and methods of making the MOSFET devices according to the invention, in which: 
       FIG. 1  illustrates a prior art MOSFET device; 
       FIG. 2  illustrates a MOSFET device in one aspect of the invention; 
       FIGS. 3–5  illustrate various configurations of the MOSFET device during its manufacture in one aspect of the invention; and 
       FIG. 6  illustrates a MOSFET device in another aspect of the invention. 
   

     FIGS. 1–6  presented in conjunction with this description are views of only particular—rather than complete—portions of the MOSFET devices and methods of making the MOSFET devices according to the invention. Together with the following description, the Figures demonstrate and explain the principles of the invention. 
   DETAILED DESCRIPTION OF THE INVENTION 
   The following description provides specific details in order to provide a thorough understanding of the invention. The skilled artisan, however, would understand that the invention can be practiced without employing these specific details. Indeed, the invention can be practiced by modifying the illustrated system and method and can be used in conjunction with apparatus and techniques conventionally used in the industry. For example, the MOSFET devices are described for RF applications, but could be used in non-RF applications such as switching. 
   As noted above, the invention generally comprises a structure that combines the benefits of the LDMOS structure (i.e., a low gate-to-drain capacitance and a good linearity) with the benefits of a short gate channel. Thus, any structure that combines theses feature can be employed in the invention. In one aspect of the invention, these benefits are combined by using a trench gate laterally-diffused MOSFET device as described below. By using this structure, the breakdown capabilities of conventional LDMOS structure can be improved. In addition, the carrier effects (i.e., injection) will be improved, and the peak electric field and impact ionization of the drain region will be reduced. 
   To achieve these benefits, the structure illustrated in the  FIG. 2  is used in the invention. In  FIG. 2 , the MOSFET device  5  comprises a semiconductor substrate  10 , typically of monocrystalline silicon (Si), with an epitaxial layer  60  formed thereon. In one aspect of the invention, the silicon substrate  10  can have a first conductivity type, such as B (boron), with a dopant concentration of about 2×10 19  atoms/cm 3 . In another aspect of the invention, the substrate can have a resistivity ranging from 0.005 to 0.01 ohm centimeter. A contact region  55  can be located on the “backside” of the substrate  10 . In one aspect of the invention, the contact region  55  is a metal contact. In one aspect of the invention, the depth of the epitaxial layer  60  can range from about 3 to about 9 microns and can have a first conductivity dopant concentration of about 1.2×10 15  atoms/cm 3 . In another aspect of the invention, the epitaxial layer can have a resistivity ranging from about 20 to about 30 ohm centimeters. 
   A gate structure  90  is located between source region  95  and drain region  100 . The gate structure  90  is separated from the source region  95  by a body region  40 . And the gate structure  90  is separated from the drain region  100  by a lightly doped drain (LDD) region  75 . 
   The gate structure  90  contains gate conductor  30 , as well as an insulating layer  80  surrounding that part of the gate conductor  30  in the trench  85 . The MOSFET device contains channel region  25  of a first conductivity type (p-type in one aspect of the invention) that is adjacent to the side of the insulating layer  80  of the gate structure  90  nearest the source region  95 . Because of this configuration of the gate in the trench  85 , the gate structure  90  is often referred to as a trench gate in which length of the gate is controlled by the depth of the trench  85 . In one aspect of the invention, the trench depth can range from about 0.5 to about 4.0 microns. In another aspect of the invention, the depth of the trench can be about 1 to about 2 microns. In yet another aspect of the invention, the trench depth can be about 1.5 microns. 
   With this configuration of the gate structure  90 , the thin insulating layer between the channel region  25  and the conducting layer  30  operates as a high-quality gate insulating layer. In addition, the insulating layer  80  (which in one aspect of the invention is asymmetric) can also reduce the gate to drain capacitance (C gd ). As well, the thick bottom oxide (with a thickness of about 1 kÅ to about 4 kÅ) can reduce the gate-to-drain overlap capacitance and thereby lower the gate charge. 
   By applying a positive gate voltage to device  5 , the channel region  25  can change the polarity from a first conductivity type to a second conductivity type. This polarity change—called inversion—permits the carriers to drift (e.g., flow) from the dopant region  70  to the lightly doped drain (LDD) region  75 . Thus, the channel region  25  can be modulated by a positive gate voltage. 
   Source region  95  comprises dopant region  35  and source electrode  15 . The dopant region  35  is typically of a first conductivity type with a concentration ranging from about 5×10 15  to about 1×10 19  atoms/cm 3 . In one aspect of the invention, the concentration of dopant region  35  is about 1×10 19  atoms/cm 3 . The source electrode  15  is located over dopant region  35  and overlaps body region  40 . The body region  40  is typically of a first conductivity type with a concentration greater than or equal to the concentration of the epitaxial layer  60 . In one aspect of the invention, the concentration of body region  40  is about 2.5×10 15  atoms/cm 3 . 
   As known in the art, source electrode  15  can be separated from the body region  40  by dopant region  70  of a second conductivity type. As well, the source electrode  15  can be separated from the gate structure  90  by a distance (a) that depends on the desired characteristics of the gate. Generally, this distance (a) can range from about 0.5 to about 1.5 microns. 
   The drain region  100  contains a drain electrode  20  overlying a portion of LDD region  75 . In one aspect of the invention, the drain electrode  20  is separated from the gate by a distance (b) depending on the desired drain-source breakdown voltage. In one aspect of the invention, this distance typically can be between about 3 to about 5 microns. In another aspect of the invention, the drain electrode is separated from gate by a distance of about 4 microns. The drain electrode  20  is also separated from the LDD region  75  by a dopant region  65 . In one aspect of the invention, the dopant region  65  is of a second conductivity type with a concentration of ranging from about 1×10 15  to 1×10 16  atoms/cm 3 . 
   The LDD region  75  contains a first drain drift region  45  of the MOS structure. The first drain drift region  45  is formed completely within the epitaxial layer  60 , with a part underlying the trench  85 . In one aspect of the invention, the first enhanced drain drift region  45  has second conductivity type when the epitaxial layer  60  has a first conductivity type. In one aspect of the invention, the first enhanced drain drift region  45  can have a dopant concentration ranging from about 1×10 11  to about 5×10 13  atoms/cm 3 . In another aspect of the invention, this dopant concentration is about 2×10 12  atoms/cm 3 . The first enhanced drain region  45  can have lateral dimensions ranging from about 0.5 to about 5.0 microns and vertical dimensions ranging from about 0.2 to about 0.5 microns 
   The LDD region  75  also contains a second enhanced drain drift region  50  that is adjacent to and contacting the first drain drift region  45 . The second drain drift region  50  is also formed completely within the epitaxial layer  60 . In one aspect of the invention, the second drain drift region  50  has second conductivity type when the epitaxial layer  60  has a first conductivity type. In one aspect of the invention, the second drain drift region can have a dopant concentration greater than the first drain drift region  45 . In one aspect of the invention, the dopant concentration can range from about 1×10 11  to about 1×10 14  atoms/cm 3 . In another aspect of the invention, this dopant concentration is about 1×10 3  atoms/cm 3 . The second drain region  50  can have lateral dimensions ranging from more than 0 to about 5 microns and vertical dimensions substantially similar to the first drain drift region  45 . 
   Using the two drain drift regions  45  and  50  in LDD region  75  allows one to increase the maximum drain drift current density of the device, as well as increase the drain-to-source breakdown voltage. Indeed, the effective electrical field in the LDD region  75  is strong enough to cause the avalanche effect of carrier multiplication at certain critical concentration of carriers. Thus, the critical carrier concentration can be related to the breakdown voltage in device  5 . In one aspect of the invention, three or more drift regions that are uniformly graded from a light dopant concentration to a heavier dopant concentration can be used as LDD region  75 . 
   In one aspect of the invention, the second drain drift region  50  has a concentration higher than the concentration of the first drain drift region  45 . This configuration can result in the redistribution of the critical electrical fields in the channel region  25  and can result in an increase of the drain-to-source breakdown voltage. The maximum current density in the source-drain channel of the device can also be increased when the total concentration in the drain drift region is increased. 
   Using the two drain drift regions  45  and  50  also allows the LDD region  75  to act as a non-linear resistor, especially when the applied voltage is varied. This non-linear behavior suggests the existence of a pinch-off point in the LDD region  75 . In other words, as the applied voltage is increase, the depletion region present in the LDD region  75  can expand and lead to a pinch-off point. 
   Configuring the LDD region  75  as indicated above can also be used to support efficient operation of device  5 . The dopant profile of the LDD region  75  can be controlled by having different sectors each with a different dopant concentration. The different doping concentrations can be configured to ensure that any breakdown does not occur near the upper surface of the device, but deeper within the LDD region  75  near the interface of the dopant region  65  and LDD region  75 . The ability to configure the LDD region  75  in this manner must be carefully balanced, of course, with the other operating parameters of the device such as C gd  and the drain to source capacitance (C ds ). 
   As noted above, the drift drain region  45  extends under the trench  85 . In one aspect of the invention, the dopant concentration of the region under the trench  85  should be higher than the concentration of the remainder of LDD region  75 . This region is an extension of LDD region  75  and helps create a current flow from the drain to the source. The concentration of this region should be tailored to the required drain-source breakdown voltage, as well as to not to substantially increase the gate to drain capacitance. 
   By using a trench gate, the devices of the invention are able to achieve several improvements over existing LDMOS devices. First, the devices of the invention have an improved RF power gain and efficiency due to the reduction of the C gd  resulting from the asymmetric insulating material in the trench and the shorter channel. Second, the devices of the invention are able to reduce the hot carrier effects by reducing the peak electric field. Third, the operating voltages of the devices of the invention can be increased above the capabilities of existing LDMOS devices. 
   The device illustrated in  FIG. 2  can be made by any process resulting in the depicted structure. In one aspect of the invention, the process described below and illustrated in  FIGS. 3–5  is used to make the structure depicted in  FIG. 2 . 
   Referring to  FIG. 3 , the process begins with substrate  10 . Any substrate known in the art can be used in the invention. Suitable substrates include silicon wafers, epitaxial Si layers, polysilicon layers, bonded wafers such as used in silicon-on-insulator (SOI) technologies, and/or amorphous silicon layers, all of which may be doped or undoped. If the substrate is undoped, it can then be doped with a first conductivity type dopant to the concentration noted above by any method known in the art. 
   Next, the backside contact region  55  is formed. In one aspect of the invention, the contact region  55  can be formed by a metallization process. Then, if the epitaxial layer  60  is not already present, it is formed on the substrate  10  by any process known in the art. If the epitaxial layer is not doped in situ, then the desired doping concentration can be formed using any known process. Next, the various dopant regions  35 ,  40 ,  45 ,  50 ,  65 , and  70  can be formed as known in the art. 
   As depicted in  FIG. 3 , trench  85  is then formed in the upper surface of the epitaxial layer  60 . The trench  85  can be formed by any suitable masking and etching process known in the art. For example, the etching process can begin by forming a mask (not shown) with an opening(s) where the trench(es) will be formed. The silicon in the trench is then removed by etching through the mask. The parameters of the etching process are controlled to preferably form round bottom corners, smooth and continuous sidewalls, flat and clean trench bottom surfaces, and trench depth, thereby maintaining the integrity of the device characteristics using the trenches. After forming the trenches, the mask is removed by any suitable process known in the art. 
   As depicted in  FIG. 4 , the trench  85  is then filled with the material for insulating layer  80 . This material for the insulating layer can be any high-quality insulating material known in the art, such as silicon nitride, silicon oxide, or silicon oxynitride. In one aspect of the invention, the insulating layer is silicon oxide (or “oxide”). In this aspect of the invention, an oxide layer is provided on the top surface of the epitaxial layer  60 , including the trench  85 . Any suitable method known in the art—including oxidation and deposition—yielding a high quality oxide layer can be used to provide this oxide layer. The portions of the oxide layer on the surface of the epitaxial layer  60  are then removed by any known process, leaving the oxide solely within the trench  85 . 
   Next, a second trench  105  is formed within the insulating layer  80 . This second trench can be formed in a manner substantially similar to the method used to form the first trench  85 , with a few modifications. The first modification is that the mask material and the etching chemical may be different to account for the difference between etching silicon and etching the material for the insulating layer  80 , e.g., oxide. The second modification is that the width of the mask openings for the second trench  105  will be smaller than the first trench  85 . 
   After the second trench  105  is formed, the conductive material  110  for the gate, source, and drain is deposited to fill and overflow the remaining portions of the second trench  105  as illustrated in  FIG. 5 . The conductive layer can be suitable material that can be used as a gate conductor, such as a metal, metal alloy, or polysilicon. In one aspect of the invention, the conductive layer is heavily doped polysilicon. The conductive layer can be deposited using any known deposition process, including chemical vapor deposition process. Optionally, the conductive layer  110  can be doped with any suitable dopant to the desired concentration, particularly when the conductive layer is polysilicon or when a silicide can be used to red e the resistance of the gate. Excess (and unneeded) portions of the conductive layer  110  are then removed using any conventional process to form the gate conductor  30 , the source electrode  15 , and the drain electrode  20 . In another aspect of the invention, additional deposition, masking, and etching steps can be used if the conductive material for the gate conductor, the source electrode, and the drain electrode will be different. 
   After the above processes are concluded, conventional processing can continue to finish the MOSFET device. As well, other processing needed to complete other parts of the semiconductor device can then be carried out, as known in the art. 
   In the aspect of the invention described above and illustrated in the Figures, the first conductivity type is a p-type dopant and the second conductivity type is an n-type dopant. In another aspect of the invention, the device can be configured with the first conductivity type being a n-type dopant and the second conductivity type dopant being a p-type dopant. 
   The devices of the invention can also be modified to contain more than a single gate. For example, as depicted in  FIG. 6 , the devices of the invention can contain two trench gates between the source and drain. In the aspect of the invention shown in  FIG. 6 , the device can contain one gate with a symmetric oxide and one gate with an asymmetric oxide. In another aspect of the invention, both gates can contain an asymmetric oxide. The device in  FIG. 6  is manufactured similar to the device depicted in  FIG. 2 , except that two trenches with two gate structures could be provided instead of a single trench. 
   Having described these aspects of the invention, it is understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are possible without departing from the spirit or scope thereof.