Abstract:
A nested transimpedance amplifier (TIA) circuit includes a zero-order TIA having an input and an output. A first operational amplifier (opamp) has an input that communicates with the output of the zero-order TIA and an output. A first feedback resistance has one end that communicates with the input of the zero-order TIA and an opposite end that communicates with the output of the first opamp. A first feedback capacitance has a first end that communicates with the input of the zero-order TIA and a second end that communicates with the output of the zero-order TIA. A capacitor has one end that communicates with the input of the zero-order TIA.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application is a continuation-in-part of U.S. patent application Ser. No. 10/072,843 filed on Feb. 6, 2002 now U.S. Pat. No. 6,762,644, which claims the benefit of U.S. Provisional Application No. 60/275,109, filed Mar. 13, 2001, both of which are hereby incorporated by reference in their entirety. 

   FIELD OF THE INVENTION 
   The present invention relates to transimpedance amplifiers, and more particularly to nested transimpedance amplifiers with an increased gain-bandwidth product. 
   BACKGROUND OF THE INVENTION 
   A transimpedance amplifier (TIA) is a well-known type of electronic circuit. Referring now to  FIG. 1 , a TIA  100  includes an operational amplifier (opamp)  105  having a gain parameter (−g m ). The opamp  105  is connected in parallel to a resistor (R f )  110 . The input to the TIA  100  is a current (Δi)  115 . The output of the TIA  100  is a voltage (Δv o )  120 . 
   Referring now to  FIG. 2 , the opamp  105  of the TIA  100  is replaced by a current source  205  and a transistor  210  having gain −g m . The TIA  100  in  FIGS. 1 and 2  is often referred to as a transconductance amplifier because it converts the input current Δi into the output voltage Δv o . 
   Referring now to  FIG. 3 , a TIA  300  converts an input voltage (Δv i )  305  into an output voltage (Δv o )  310 . The TIA  300  also includes a resistor  315  that is connected to a transistor  320 . The TIA  300  is typically used in applications that require relatively low bandwidth. 
   Referring now to  FIG. 4 , a TIA  400  converts an input voltage (Δv i )  405  into an output voltage (Δv o )  410 . The TIA  400  includes a second opamp  415 , which is connected in series to a parallel combination of a resistor (R f )  420  and an opamp  425 . The TIA  400  is typically used for applications having higher bandwidth requirements than the TIA  300 . 
   Ordinarily, the bandwidth of the TIA is limited to a fraction of a threshold frequency f T  of transistor(s) that are used in the opamp(s). In the case of a bipolar junction transistor (BJT) such as a gallium-arsenide (GaAs) transistor, the bandwidth of the TIA is approximately equal to 10%–20% of f T . For metal-oxide-semiconductor (MOS) transistor(s), the bandwidth of the TIA is typically a few percent (i.e., approximately 2%–6%) of f T . 
   Referring now to  FIG. 5 , a TIA  500  may be configured to operate differentially using two inputs of each opamp  502  and  504 . One input  505  acts as a reference, in a similar manner as ground or virtual ground in a standard configuration TIA. The input voltage Δv i  and the output voltage Δv o  are measured as voltage differences between a reference input  505  and a second input  510 . Feedback resistors  514  and  516  are connected across the inputs and the outputs of the opamp  504 . 
   Referring now to  FIG. 6 , one TIA application having a relatively high bandwidth requirement is that of an optical sensor. An optical sensor circuit  600  includes the opamp  105  and the resistor  110  of the TIA  100  that are coupled with a photodiode  605 . The output of the photodiode  605  is a current I photo    610 , which acts as an input to the TIA  100 . 
   Increasingly, applications require both high bandwidth and high gain. Examples include optical sensors, such as fiber optic receivers, and preamplifier writers for high-speed hard disk drives. Efforts to increase the gain-bandwidth product of TIAs have been made. For example, in U.S. Pat. No. 6,114,913, which are hereby incorporated by reference, a boost current is used to increase the gain-bandwidth product in the TIA. Cascading TIA stages is also used in U.S. Pat. Nos. 5,345,073 and 4,772,859, which are hereby incorporated by reference. 
   Other improvements to TIAs are the subject of other patents, such as U.S. Pat. Nos. 6,084,478; 6,057,738; 6,037,841; 5,646,573; 5,532,471; 5,382,920; 5,010,588; 4,914,402; 4,764,732; 4,724,315; 4,564,818; and 4,535,233, which are hereby incorporated by reference. However, improving the gain-bandwidth product of TIAs continues to be a challenge for circuit designers. 
   SUMMARY OF THE INVENTION 
   A nested transimpedance amplifier (TIA) circuit according to the present invention includes a zero-order TIA having an input and an output. A first operational amplifier (opamp) has an input that communicates with the output of the zero-order TIA and an output. A first feedback resistance has one end that communicates with the input of the zero-order TIA and an opposite end that communicates with the output of the first opamp. A first feedback capacitance has a first end that communicates with the input of the zero-order TIA and a second end that communicates with the output of the zero-order TIA. 
   In other features, a capacitor has one end that communicates with the input of the zero-order TIA. The zero order TIA includes a second opamp having an input and an output. A third opamp has an input that communicates with the output of the second opamp and an output. A second feedback resistance has one end that communicates with the input of the third opamp and an opposite end that communicates with the output of the third opamp. 
   In yet other features, a fourth opamp has an input and an output that communicates with the input of the second opamp. A fifth opamp has an input that communicates with the output of the first opamp and an output. A second feedback capacitance has a first end that communicates with the input of the fourth opamp and a second end that communicates with the output of the first opamp. A third feedback resistance has one end that communicates with the input of the fourth opamp and an opposite end that communicates with the output of the fifth opamp. 
   In still other features, at least one higher order circuit is connected to the nested TIA circuit and includes an n th  feedback resistance, an n th  opamp, an (n+1) th  opamp, and an n th  feedback capacitance. 
   In yet other features of the invention, a nested differential mode TIA circuit includes a zero-order differential mode TIA having first and second inputs and first and second outputs. A first differential mode opamp has first and second inputs that communicate with the first and second outputs of the zero-order differential mode TIA and first and second outputs. A first feedback resistance has one end that communicates with the first input of the zero-order differential mode TIA and an opposite end that communicates with the first output of the first differential mode opamp. A second feedback resistance has one end that communicates with the second input of the zero-order differential mode TIA and an opposite end that communicates with the second output of the first differential mode opamp. A first capacitance has a first end that communicates with the first input of the zero-order differential mode TIA and a second end that communicates with the first output of the zero-order differential mode TIA. A second capacitance has a first end that communicates with the second input of the zero-order differential mode TIA and a second end that communicates with the second output of the zero-order differential mode TIA. 
   In still other features, the zero order differential mode TIA includes a second differential mode opamp having first and second inputs and first and second outputs. A third differential mode opamp has first and second inputs that communicate with the first and second outputs of the second differential mode opamp and first and second outputs. A third feedback resistance has one end that communicates with the first input of the third differential mode opamp and an opposite end that communicates with the first output of the third differential mode opamp. A fourth feedback resistance has one end that communicates with the second input of the third differential mode opamp and an opposite end that communicates with the second output of the third differential mode opamp. 
   In still other features, at least one higher order circuit is connected to the nested TIA circuit and includes an n th  feedback resistance, an (n+1) th  feedback resistance, an n th  differential mode opamp and an n th  feedback capacitance. 
   Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein: 
       FIGS. 1 and 2  are basic circuit architectures for a current-to-voltage TIA according to the prior art; 
       FIGS. 3 and 4  are basic circuit architectures for a voltage-to-voltage TIA according to the prior art; 
       FIG. 5  is a basic circuit architecture for a differential configuration of a TIA according to the prior art; 
       FIG. 6  shows an optical sensor, including a photodiode coupled to a TIA, according to the prior art; 
       FIG. 7  is a first-order nested TIA according to the present invention; 
       FIG. 8  is a second-order nested TIA according to the present invention; 
       FIG. 9  is an nth-order nested TIA according to the present invention; 
       FIG. 10  is a first-order nested TIA in a differential configuration according to the present invention; 
       FIG. 11  is an nth-order nested TIA in a differential configuration according to the present invention; 
       FIG. 12  is a graph of exemplary gain-bandwidth characteristics for a TIA; 
       FIG. 13  is a graph of an exemplary gain-bandwidth characteristic for a first-order nested TIA; 
       FIG. 14  is a graph of an exemplary gain-bandwidth characteristic for a second-order nested TIA; 
       FIG. 15  is a first-order nested TIA with capacitive cancellation of input parasitic capacitance according to the present invention; 
       FIG. 16  is a second-order nested TIA with capacitive cancellation of input parasitic capacitance according to the present invention; 
       FIG. 17  is an nth-order nested TIA with capacitive cancellation of input parasitic capacitance according to the present invention; 
       FIG. 18  is a first-order nested TIA in a differential configuration with capacitive cancellation of input parasitic capacitance according to the present invention; 
       FIG. 19  is a second order nested TIA in a differential configuration with capacitive cancellation of input parasitic capacitance according to the present invention; 
       FIG. 20  illustrates the first order nested TIA of  FIG. 7  with additional feedback resistance; 
       FIG. 21  illustrates a second order nested TIA of  FIG. 8  with additional feedback resistance; 
       FIG. 22  illustrates the first order nested TIA of  FIG. 15  with additional feedback resistance; 
       FIG. 23  illustrates the first order nested TIA of  FIG. 7  with an additional input capacitance, feedback capacitance, and feedback resistance; 
       FIG. 24  illustrates the first order differential mode TIA of  FIG. 10  with an additional input capacitance, feedback capacitance, and feedback resistance; and 
       FIG. 25  illustrates an exemplary disk drive system including a preamplifier with a nested TIA according to the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   The following description of the preferred embodiment(s) is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. 
   The present invention addresses the need for increasing the gain-bandwidth product of TIAs. Improvements in the gain-bandwidth product are achievable by “nesting” a TIA within another TIA. In other words, additional circuit elements such as feedback resistors, capacitors and/or opamps are added on the input and/or output sides of the TIA. In  FIGS. 15–17 , capacitive cancellation of the input parasitic capacitance is provided. In  FIGS. 20–24 , additional feedback resistance is provided. In  FIGS. 23 and 24 , input and/or feedback capacitance is provided. 
   Referring now to  FIGS. 7 ,  8 , and  9 , a “nested” TIA is constructed by adding opamps, feedback resistors and/or capacitors to a zero-order TIA. In  FIGS. 10 and 11 , a nested TIA may also be constructed to operate in a differential mode. 
   Referring back to  FIG. 7 , a first-order nested TIA  700  is shown. Reference numbers from  FIG. 4  are used in  FIG. 7  to identify similar elements. The TIA  700  includes a conventional TIA  705  (also referred to herein as a “zero-order” TIA), an opamp  710 , and a feedback resistor  715 . The feedback resistor  715  may be a standard fixed-value resistor, a nonlinear variable resistor, or an MOS resistor. A capacitor  720  is also connected between an input of the TIA  700  and ground (or virtual ground). 
   By nesting the TIA in this manner, improvements in the gain-bandwidth product may be realized. For example, the first-order nested TIA  700  that uses MOS transistors may achieve a bandwidth that is 10%–20% of the threshold frequency f T . This range represents a bandwidth that is approximately five to ten times greater than the bandwidth of the corresponding zero-order TIA. 
   Referring now to  FIGS. 12 and 13 , graphs illustrating characteristic gain-bandwidth curves for a zero-order TIA and a first-order nested TIA, respectively, are shown. In general, a higher value of gain is associated with a lower value of bandwidth, and a lower value of gain is associated with a higher value of bandwidth. The gain A, defined as the output voltage Δv o  divided by the input voltage Δv i , is typically on the order of a few hundred or a few thousand (i.e., approximately 10 2 –10 3 ). A typical range of threshold frequency (f T ) values for a 0.13 μm CMOS process is 30 GHz–40 GHz. 
   In  FIG. 12 , three exemplary characteristic curves are shown. A high gain value yields a bandwidth value of approximately 1 GHz. A medium gain value increases the bandwidth to approximately 2 GHz. Other values of gain and bandwidth are possible. For example, a TIA may have a characteristic gain value that is higher than the maximum shown in  FIG. 12  and a bandwidth that is less than 1 GHz. A TIA may have a characteristic gain value that is lower than the minimum gain value shown in  FIG. 12  and a bandwidth that is greater than 2 GHz. As can be appreciated, the bandwidth varies as an inverse function of gain. This function may be referred to as the “spread”. The spread is greater for TIAs using MOS transistors than for TIAs using bipolar junction transistors (BJTs). Thus, the need to improve the TIA bandwidth performance is more pronounced with MOS transistors than with BJT transistors. 
   The exemplary bandwidth values shown in  FIG. 12  do not define upper and lower bandwidth bounds. In many practical applications, bandwidths on the order of 1 GHz or 2 GHz are too low. Many applications, such as an OC192 fiber optic receiver, require bandwidths on the order of 10 GHz. Preamplifiers for high-speed hard disk drives also typically require bandwidths that are on the order of several GHz. Referring now to  FIG. 13 , a first-order nested TIA at a typical gain value may have a bandwidth of approximately 10 GHz. 
   Referring now to  FIG. 8 , a second-order nested TIA  800  builds upon the first-order nested TIA  700 . Reference numbers from  FIGS. 4 and 7  are used in  FIG. 8  to identify similar elements. The second-order nested TIA  800  includes an opamp  805  at the input of the first-order nested TIA  700  and an opamp  810  at the output of the first-order nested TIA  700 . An additional feedback resistor  815  is also added across the input of the opamp  805  and the output of the opamp  810 . An exemplary gain-bandwidth curve that is produced using the second-order nested TIA  800  is shown in  FIG. 14 . For a typical gain value, a bandwidth of approximately 20 GHz may be achieved. 
   Referring now to  FIG. 9 , higher-order nested TIAs may be constructed by adding additional opamps and feedback resistors. Reference numbers from  FIGS. 4 ,  7  and  8  are used in  FIG. 9  to identify similar elements. For example, a third-order nested TIA  900  includes opamps  905  and  910  and feedback resistor  915 . It is possible to achieve higher values of either gain or bandwidth (or both) by repeating the technique of the present invention. However, the efficiency of the circuit decreases as additional nesting levels are added due to parasitic noise and increased power dissipation. In general, either the first-order nested TIA or the second-order nested TIA will usually provide sufficient performance. 
   Referring now to  FIG. 10 , a differential mode first-order nested TIA  1000  is shown. Reference numbers from  FIG. 5  are used in  FIG. 10  to identify similar elements. An opamp  1002  is connected to the outputs of the opamp  504 . Feedback resistors  1006  and  1008  are connected to inputs of the differential mode TIA  500  and to outputs of the opamp  1002 . The gain-bandwidth product of the TIA is increased. 
   Referring now to  FIG. 11 , a differential mode nth-order nested TIA  1100  is constructed in a manner that is similar to the nth-order nested TIA of  FIG. 9 . Reference numbers from  FIGS. 5 and 10  are used in  FIG. 11  to identify similar elements. Additional opamps  1104  and  1108  and feedback resistors  1112  and  1114  are connected in a similar manner. The gain-bandwidth characteristics for differential mode TIAs are substantially similar to the gain-bandwidth characteristics shown in  FIGS. 12–14 . 
   It is noted that the opamps used in the nested TIA may employ either bipolar junction transistors (BJTs), such as gallium-arsenide (GaAs) transistors, or metal-oxide-semiconductor (MOS) transistors, such as CMOS or BICMOS transistors. The preferred embodiments of the invention use MOS transistors due to practical considerations such as ease of manufacture and better power consumption characteristics. 
   Referring now to  FIG. 15 , the first order nested TIA  700  is shown with additional feedback capacitance C 1 , which substantially cancels effects of an input capacitance C P1  at the input of the opamp  415 . The feedback capacitance C 1  has a first end that communicates with an input of the opamp  415  and a second end that communicates with an output of the opamp  425 . 
   Referring now to  FIG. 16 , the second order nested TIA  800  of  FIG. 8  is shown with additional feedback capacitances C 1  and C 2 , which substantially cancel effects of input capacitances C P1  and C P2  at the inputs of opamps  415  and  805 , respectively. The feedback capacitance C 1  has a first end that communicates with an input of the opamp  415  and a second end that communicates with an output of the opamp  425 . The feedback capacitance C 2  has a first end that communicates with an input of the opamp  805  and a second end that communicates with an output of the opamp  710 . 
   Referring now to  FIG. 17 , the nth order nested TIA of  FIG. 9  is shown with additional feedback capacitances C 1 , C 2 , . . . , and C N , which substantially cancel effects of input capacitances C P1 , C P2 , . . . , and CP N  at the inputs of opamps  415 ,  805  and  905 , respectively. The feedback capacitance C 1  has a first end that communicates with an input of the opamp  415  and a second end that communicates with an output of the opamp  425 . The feedback capacitance C 2  has a first end that communicates with an input of the opamp  805  and a second end that communicates with an output of the opamp  710 . The feedback capacitance C N  has a first end that communicates with an input of the opamp  905  and a second end that communicates with an output of the opamp  810 . 
   Referring now to  FIG. 18 , the first order nested differential mode TIA  1000  is shown with additional feedback capacitors C 1A  and C 1B , which substantially cancel effects of input parasitic capacitances C P1  and C P2  at the inputs of the differential mode opamp  502 . The feedback capacitance C 1A  has a first end that communicates with an input of the differential mode opamp  502  and a second end that communicates with an output of the differential mode opamp  504 . In  FIG. 19 , additional capacitances C 2A  and C 2B  are added to a second order differential mode TIAs in a similar manner to offset parasitic capacitances C P2A  and C P2B . Higher order circuits use a similar approach. 
   Referring back to  FIG. 20 , the first order nested TIA of  FIG. 7  is shown with additional feedback resistance  2010 . The feedback resistance  2010  has a first end that communicates with an input of the opamp  710 . A second end of the resistance  2010  communicates with an output of the opamp  710 . 
   Referring now to  FIG. 21 , the second order nested TIA of  FIG. 8  is shown with additional feedback resistance  2110 . The feedback resistance  2110  has a first end that communicates with an input of the opamp  810 . A second end of the resistance  2110  communicates with an output of the opamp  810 . 
   Referring now to  FIG. 22 , the first order nested TIA of  FIG. 15  is shown with additional feedback resistance  2210 . The feedback resistance  2210  has a first end that communicates with an input of the opamp  710 . A second end of the resistance  2210  communicates with an output of the opamp  710 . 
   Referring now to  FIG. 23 , the first order nested TIA of  FIG. 7  is shown with input capacitance C IN , feedback capacitance C FB , and feedback resistance  2310 . The input capacitance C IN  has a first end that receives an input signal for the nested TIA  700  and a second end that communicates with an input of opamp  415 . The feedback capacitance C FB  has a first end that communicates with an input of opamp  415  and a second end that communicates with one end of resistance  715 . 
   The additional feedback resistances, input capacitances, and/or feedback capacitances can also be added to the differential mode nested TIA. Referring now to  FIG. 24 , the first order differential mode nested TIA of  FIG. 10  is shown with first and second input capacitances C IN1  and C IN2 , first and second feedback capacitances C FB1  and C FB2 , and feedback resistances  2410  and  2412 . The input capacitances C IN1  and C IN2  have first ends that receive input signals for the nested differential mode TIA and second ends that communicate with inputs of opamp  502 . The feedback capacitances C FB1  and C FB2  have first ends that communicate with inputs of opamp  502  and second ends that communicate with first ends of resistances  1006  and  1008 , respectively. First and second feedback resistances  2410  and  2412  have first ends that are connected to inputs and second ends that are connected to outputs of differential mode opamp  1002 . 
   As can be appreciated, the feedback capacitances ( FIGS. 15–19 ), feedback resistances ( FIGS. 20–24 ), and input and feedback capacitances ( FIGS. 23 and 24 ) can be used in any combination on first, second, . . . or n th  order nested TIA and/or differential mode TIA. 
   Referring now to  FIG. 25 , an exemplary disk drive system  2500  is shown to include a disk drive write circuit  2510  that writes to a disk drive  2514 . A disk drive read circuit  2516  includes a preamp circuit  2518  with a nested TIA or nested differential mode TIA identified at  2520 , which is implemented as described above. 
   Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the present invention can be implemented in a variety of forms. Therefore, while this invention has been described in connection with particular examples thereof, the true scope of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, the specification and the following claims.