Abstract:
Provided is a method of performing a parallel test on semiconductor devices, the method including coupling a power signal line to a set of at least two semiconductor devices through a switching device, performing at least one part of a parallel test on the set of semiconductor devices, and disconnecting a semiconductor device from the set in response to determining that the semiconductor device is defective as a result of the at least one part of the parallel test.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     This application claims the priority of Korean Patent Application No. 10-2005-0002460, filed on Jan. 11, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.  
         [0002]     1. Field of the Invention  
         [0003]     This application relates to an apparatus for and method of testing semiconductor devices, and more particularly, to a method of increasing the number of semiconductors that can be tested at a time by improving the structure of a performance board of a testing apparatus and performing a parallel test on the doubled semiconductor devices.  
         [0004]     2. Description of the Related Art  
         [0005]     Semiconductor devices are produced in wafer forms and are assembled into a semiconductor package after an electrical die sorting (EDS) test. The semiconductor devices are finally tested electrically before being distributed to users. In particular, as the capacity of semiconductor memory devices and the number of semiconductor memory device pins increase rapidly, it becomes increasingly important to enhance efficiency of an electrical test process.  
         [0006]     To enhance the efficiency of the electrical test, a tester for testing semiconductor memory devices has been developed, focusing on increasing speed and throughput, and shortening testing time of the tester. The testing time may be shortened using the following methods.  
         [0007]     A first method is to change a testing method and modify a test program to shorten test time. A second method is to increase the number of semiconductor memory devices tested at a time, i.e., the number of devices under test (DUTs), in a parallel test.  
         [0008]      FIG. 1  is a schematic perspective view of a conventional tester used to electrically test semiconductor devices. Referring to  FIG. 1 , a measuring unit needed to electrically test the semiconductor devices is included in a mainframe  22 . The function of the mainframe  22  is extended to a test head  24  through a signal cable  20 . A performance board  28  is mounted on top of the test head  24 . The performance board  28  includes driver signal lines, I/O signal lines, power signal lines, and ground signal lines formed in a printed circuit pattern. Since a pogo pin block  19  is formed at the center of the performance board  28 , the performance board  28  may be connected to a prober system or a handler and then used.  
         [0009]      FIG. 2  is a sectional view of the test head  24  and the performance board  28  of  FIG. 1 . Referring to  FIG. 2 , the test head  24  includes a driver channel, an I/O channel, and a voltage supply unit (VSU) channel. The driver channel, the I/O channel, and the VSU channel are connected to a printed circuit patterns (not shown) of the performance board  28  by signal lines  30 . The printed circuit patterns in the performance board  28  are connected to pogo pins  18 .  
         [0010]     In the EDS test, the pogo pins  18  are connected to a probe card of the prober system. In the final electrical test of a semiconductor package, a DUT board is connected into the pogo pins  18 .  
         [0011]      FIG. 3  illustrates signal lines connected from the test head  24  to a plurality of DUTs  40 . Referring to  FIG. 3 , the test head  24  includes a driver signal line  10 , an I/O signal line  12 , and a power signal line  14  of a VSU. The driver signal line  10  is connected to address pins A 0  through An of the DUTs  40  by a driver  11 , via the performance board  28  and an interface board  32 . The interface board  32  may be the probe card or the DUT board.  
         [0012]     The I/O signal lines  12  are connected to data pins DQ 0  through DQn of the DUTs  40  by the driver  11  and a comparator  13 , via the performance board  28  and the interface board  32 . The power signal lines  14  are connected to power pins V DD  of the DUTs  40  by the driver  11 , via a relay  16  of the performance board  28  and the interface board  32 .  
         [0013]     If it is determined that a DUT is defective as a result of a parallel electrical test, the relay  16  is turned off, thereby preventing DUTs adjacent to the defective DUT or the interface board  32 , such as the probe card, from being damaged.  
         [0014]      FIG. 4  is a block diagram for illustrating a connection state of the power signal line  14  in the performance board  28 . Referring to  FIG. 4 , in the parallel test, the power signal line  14  in the printed circuit pattern of the performance board  28  is connected to the power pin V DD  of each of the DUTs  40 . In the parallel electrical test, all of first through n th  relays  16 - 1  through  16 - n  are connected. However, if a second DUT is found defective in the parallel test, the second relay  16 - 2  is turned off, thereby preventing DUTs adjacent to the second DUT from being damaged or a needle of the interface board  32  of  FIG. 3  from melting.  
         [0015]     However, the method described above is a mechanism for testing a predetermined number of DUTs in a parallel electrical test process. To increase the number of DUTs, a new control method in terms of software and hardware is required.  
       SUMMARY  
       [0016]     Embodiments include a method of performing a parallel test on semiconductor devices including coupling a power signal line to a set of at least two semiconductor devices through a switching device, performing at least one part of a parallel test on the set of semiconductor devices, and disconnecting a semiconductor device from the set in response to determining that the semiconductor device is defective as a result of the at least one part of the parallel test.  
         [0017]     Further embodiments include an apparatus for testing semiconductor devices including a power signal line, switching devices, and connections for testing sets of semiconductor devices, each connection coupled to the power signal line through an associated switching device, and each such set of semiconductor devices including at least two semiconductor devices. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]     The above and other features and advantages of the invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:  
         [0019]      FIG. 1  is a perspective view of a conventional tester used to electrically test semiconductor devices;  
         [0020]      FIG. 2  is a sectional view of a test head and a performance board of  FIG. 1 ;  
         [0021]      FIG. 3  is a block diagram illustrating signal lines connected from the test head to a plurality of DUTs;  
         [0022]      FIG. 4  is a block diagram illustrating a connection state of a power signal line in the performance board;  
         [0023]      FIG. 5  is a block diagram of a tester used to electrically test semiconductor devices;  
         [0024]      FIG. 6  is a top view of a performance board of  FIG. 5 ;  
         [0025]      FIG. 7  illustrates power signal lines divided into two power signal lines in the performance board;  
         [0026]      FIG. 8  illustrates the divided power signal lines connected to switching devices in the performance board;  
         [0027]      FIG. 9  is a block diagram of a test system including signal lines connected from a test head to first and second DUTs having an increased testing capacity in a parallel test; and  
         [0028]      FIG. 10  is a flowchart illustrating a method of performing parallel tests on semiconductor devices. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0029]     Embodiments will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth therein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.  
         [0030]     For example, a tester, which will be described in the following embodiments, may be for testing semiconductor memory devices. Alternatively, the tester may be an LSI device tester, an analog tester, or a mixed signal tester. In addition, the structure of the tester may be slightly modified to accomodate a tester manufacturer.  
         [0031]      FIG. 5  is a block diagram of a tester  100  used to electrically test semiconductor devices. Referring to  FIG. 5 , the tester  100  includes a tester processor  110  in a workstation for controlling hardware components in the tester  100 . The hardware components may include a programmable power supply  112 , a DC parameter measurement unit  114 , an algorithmic pattern generator  116 , a timing generator  118 , a wave shape formatter  120 , and a pin test head  150 .  
         [0032]     The pin test head  150  includes a driver signal channel, an input/output (I/O) signal channel, and a power signal channel connected to a voltage supply unit (VSU). A performance board  200  is loaded onto the pin test head  150 . Using a test program running on the tester processor  110 , the tester  100  allows the hardware components in the tester  100  to communicate signals to and test electric functions of devices under test (DUTs)  400  connected to the tester  100  by an interface board  300 .  
         [0033]     The test program may consist of a DC test, an AC test, and a function test. The function test is to test functions of a semiconductor memory device under actual operating conditions. For example, an input pattern from the algorithmic pattern generator  116  of the tester  100  is written to the DUTs  400 , and an output pattern from the DUTs  400 , is read out and compared with an expected pattern using a comparator. A specific example of DUT  400  is a DRAM. The input pattern could simulate a write operation and the output pattern could simulate a read operation.  
         [0034]      FIG. 6  is a top view of the performance board  200  of  FIG. 5 . Referring to  FIG. 6 , the performance board  200  may be a printed circuit board (PCB)  163  in a multilayer substrate form. The performance board  200  includes printed circuit patterns used as a driver signal line, an I/O signal line, and a power signal line and a ground signal line connected to the VSU. A pogo pin block  164  is formed at the center of the performance board  200  such that the printed circuit patterns used as the driver signal line, the I/O signal line, and the power signal line and the ground signal line connected to the VSU are connected to the DUTs  400  by the interface board  300 .  
         [0035]     In an electrical die sorting (EDS) test conducted when semiconductor memory devices are in wafer forms, the interface board  300  is a probe card and a prober system is an automatic test robot. In a final electrical test conducted when the semiconductor memory devices are assembled into a semiconductor package, the interface board  300  is a DUT board and uses a handler as the automatic test robot.  
         [0036]      FIG. 7  illustrates a power signal line  162  divided into two power signal lines  166  in the performance board  200 . Referring to  FIG. 7 , the power signal line  162  can be divided into two separate power signal lines  166 . Accordingly, the number of DUTs  400  can be doubled in the parallel test. For example, if it is determined that one (DUT  1 ′) of DUT  1  and DUT  1 ′ is defective as a result of the parallel test, a relay  164 - 1  is not turned off. Thus, DUT  1  adjacent to DUT  1 ′ or a needle of the interface board  300  may be damaged. For example, if the interface board  300  is a probe card, a needle of the probe card may melt. However, if it is determined that both of DUT  1  and DUT  1 ′ are defective as a result of the parallel test, the tester  100  can turn off the relay  164 - 1  using its operating system.  
         [0037]      FIG. 8  illustrates the power signal lines  162  connected to switching devices in the performance board  200 . Referring to  FIG. 8 , to solve the problems mentioned in  FIG. 7 , switching devices, i.e., a plurality of relays ( 164 - 1   b ,  164 - 1   c ,  164 - 2   b ,  164 - 2   c  . . .  164 - nb ,  164 - nc ) are additionally connected to the power signal lines  162 , respectively. The relays ( 164 - 1   b ,  164 - 1   c ,  164 - 2   b ,  164 - 2   c  . . .  164 - nb ,  164 - nc ) may be in circuit module forms and may be loaded into the performance board  200 . The relays ( 164 - 1   b ,  164 - 1   c ,  164 - 2   b ,  164 - 2   c  . . .  164 - nb ,  164 - nc ) can be controlled, i.e., turned on or off, by signal lines, such as the driver signal lines and the I/O signal lines, which can be utilized using a command language of a test program in a test head.  
         [0038]     For example, in a type of memory tester manufactured by ADVANTEST, when a V IH  level signal is applied to an LCON node used as a driver signal line, the relays  164 - 1   b  and  164 - 1   c  are turned on. When the V IH  level signal is applied to a PD 1  node used as another driver signal line, the relay  164 - 1   b  is turned on while the relay  164 - 1   c  is turned off.  
         [0039]     Conversely, when a V IL  level signal is applied to the PD 1  node, the relay  164 - 1   b  is turned off while the relay  164 - 1   c  is turned on. Thus, even though the power signal line  162  connected to the VSU is divided into two power signal lines  166 , the power supply of the power signal lines  166  can be controlled using the described switching devices.  
         [0040]     As described above, the relays ( 164 - 1   b ,  164 - 1   c ,  164 - 2   b ,  164 - 2   c  . . .  164 - nb ,  164 - nc ) can be controlled by applying the V IH /V IL  level signal on a driver signal line. Likewise, the relays ( 164 - 1   b ,  164 - 1   c ,  164 - 2   b ,  164 - 2   c  . . .  164 - nb ,  164 - nc ) may be controlled by applying the V IH /V IL  level signal to the I/O signal line.  
         [0041]     If it is determined that both of the DUT 1  and the DUT 1 ′ connected to the power signal lines  166  of the VSU are defective, the tester  100  may turn off the relay  164 - 1  using its operating system, thereby cutting off power supplied to the DUT  1  and the DUT 1 ′.  
         [0042]      FIG. 9  is a block diagram of a test system including the power signal lines  166  connected from the test head  150  to first and second groups of DUTs  400 A and  400 B having two times the testing capacity in the parallel test. Referring to  FIG. 9 , the power signal line  162  in the performance board  200  is divided into two power signal lines  166  and relays  164 A and  164 B are additionally connected to the two power signal lines  166 . A driver signal line  152  and an I/O signal line  154  in the interface board  300  are also divided into two driver signal lines and two I/O signal lines, respectively. The two driver signal lines and the two I/O signal lines are respectively connected to the first and second groups of DUTs  400 A and  400 B, via the performance board  200  and an interface board  300 . Therefore, the tester  100  can electrically test the first and second groups of DUTs  400 A and  400 B simultaneously, which is twice the original testing capacity of the tester  100  in the parallel test.  
         [0043]      FIG. 10  is a flowchart illustrating a method of performing parallel tests on semiconductor devices. Referring to  FIG. 10 , the test system including modified hardware as described above is prepared (S 100 ). The hardware may be modified by dividing the power signal line  162  connected to the VSU in the performance board  200  into two power signal lines  166  and installing a circuit module including a relay in each of the two power signal lines  166 . In addition, the hardware may be modified by dividing the driver signal line in the interface board into two driver signal lines or the I/O signal line into two I/O signal lines.  
         [0044]     The modified test system starts to electrically test semiconductor devices in a parallel method (S 110 ). In the EDS test conducted when DUTs are in wafer, after the probe card is connected to the performance board  200 , the automatic test robot electrically tests doubled DUTs, using the prober system. In the final test conducted when the DUTs are assembled into a semiconductor package, after a DUT board is connected to the performance board  200 , the doubled DUTs are electrically tested using the handler as the automatic test robot. The electrical test is initiated by running a test program in the workstation of the tester  100 .  
         [0045]     The number of DUTs that the tester  100  can test at a time is determined by the number of driver channels, I/O channels, and VSUs in the tester  100  when a tester manufacturer designs the test equipment. However, as described above, the numbers of driver signal lines, I/O signal lines, and power signal lines are increased by modifying the performance board  200  and the interface board  300 . Hence, the tester  100  can electrically test DUTs more DUTs than the number of DUTs determined by the tester manufacturer.  
         [0046]     An open/short test is conducted in a test program (S 120 ). In the test program, it is evaluated whether the DUTs  400  connected to the two power signal lines  166  are defective (S 130 ). If it is identified that one of the DUTs  400  is defective, the tester  100  forces signals such as V IH /V IL  level signals on a driver signal line or an I/O signal line currently unused by the tester  100  running the test program. In this way, the tester  100  controls the relays installed in the two power signal lines  166  to cut off one of the two power signal lines  166 , which is input to the defective DUT  400  (S 140 ). The driver signal line and the I/O signal line used to control the relays installed in the two power signal lines  166  may be used for test items included in the parallel test as well as for controlling the relays while the relays are open during the parallel test.  
         [0047]     If it is determined that none of the DUTs  400  is defective as a result of the open/short test, a leakage test is conducted (S 150 ). After the leakage test is completed, it is determined again whether the DUTs  400  connected to the two power signal lines  166  are defective (S 160 ). If it is determined that one of the DUTs  400  is defective, the tester  100  applies signals such as V IH /V IL  level signals on a driver signal line or an I/O signal line currently unused by the tester  100  running the test program. In this way, the tester  100  controls the relays installed in the two power signal lines  166  to cut off one of the two power signal lines  166 , which is input to the defective DUT  400  (S 170 ). By controlling the relays the power signal lines  166  may be cut off once the entire test program is finished or whenever a test item is finished.  
         [0048]     If it is determined that none of the DUTs  400  is defective as a result of the leakage test (S 150 ), a function test (S 180 ) and bin sorting (S 190 ) routines may be performed. Then, the parallel electrical test is terminated.  
         [0049]     As described above, first, in a parallel test, the number of DUTs can be increased by dividing a power signal line in a performance board of a tester and more efficiently operating the divided power signal lines. Second, if one of DUTs connected to the divided power signal lines is defective, one of the power signal lines, which is input to the defective DUT, may be cut off by controlling a corresponding switching device. Thus, damage to DUTs adjacent to the defective DUT or a probe card may be prevented.  
         [0050]     While the invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.