Abstract:
A low-power, passive radio frequency identification and communication device communicable with a device reader is disclosed, comprising an RF front end for receiving from and transmitting to the device reader RF signals and extracting power and data from an RF signal generated by the device reader, a controller for receiving from and transmitting to the RF front end data, and a memory for receiving from and transmitting to the controller data. The memory is readable and writable by the controller and operable using first and second voltage supplies during read and write operations, respectively, the first and second voltage supplies being of different voltage supply levels.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This is a Continuation Application of PCT Application No. PCT/JP2004/018424, filed Dec. 3, 2004, which was published under PCT Article 21(2) in English.  
         [0002]     This application is based upon and claims the benefit of priority from prior Singapore Patent Application No. 200400496-6, filed Jan. 30, 2004, the entire contents of which are incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION  
       [0003]     1. Field of the Invention  
         [0004]     The invention relates generally to communication devices. In particular, it relates to a radio frequency (RF) identification and communication device.  
         [0005]     2. Description of the Related Art  
         [0006]     A contactless or RF identification and communication (RFID) device, embodied in the form of a tag, transponder or card, is commonly used in numerous applications for identifying an object. These applications include sentry control, access control, inventory control, live stock tracking, vehicle telemetry, and etc.  
         [0007]     For application efficacy, miniaturization of the RFID device is desirable since the device is typically tagged or attached to an object for identification of the object. A device reader identifies the device which bears identification information about the object through interrogation, which consists of contactless or RF-based communication between the device and the device reader. For achieving optimal miniaturization, passive devices are preferred than active devices, which are devices having internal power sources.  
         [0008]     A passive device generates power from RF signals transmitted by the device reader for one-off or instant usage. Because such generated power is limited and cannot be stored for subsequent usage, it is therefore critical that the design of such a passive device is directed at achieving low-power internal operations.  
         [0009]     To achieve low-power internal operations, passive devices are typically required to provide different operating voltage supplies with different voltage supply levels for powering different circuit blocks within these devices. Such passive devices are also typically required to provide different clock frequencies for operation of the different circuit blocks. General requirements for the passive devices include incorporating a read/write memory and communication capability with the device reader.  
         [0010]     A number of conventional proposals are directed at RFID devices but do not address the need to provide both different operating voltage supplies and clock frequencies required for low-power operations in RFID devices.  
         [0011]     In U.S. Pat. No. 6,104,290 to Naguleswaran, a contactless identification and communication system in which use of two oscillators in a transponder is proposed. The transponder operates at a higher speed during transmission operations for transmitting data to a device reader and at a lower speed during other operations. By doing this, power-saving operations are purportedly carried out. However, this proposal has a demerit of having two oscillators leading an enlargement of the device and an increase of a cost of the device.  
         [0012]     In U.S. Pat. No. 6,211,786 to Yang et al., a battery-free circuit for an RFID tag is proposed for low-frequency application, and in U.S. Pat. No. 6,147,605 to Vega et al., a circuit for an electrostatic RFID device is proposed. Neither of these proposals is directed at multiple voltage supplies-multiple clock frequencies operations for power saving in the respective RFID devices.  
         [0013]     There is therefore a need for a low-power, passive RFID device having different operating voltage supplies and clock frequencies for performing power-saving operations.  
       BRIEF SUMMARY OF THE INVENTION  
       [0014]     In accordance with one aspect of the invention, there is disclosed a radio frequency identification and communication device communicable with a device reader, comprising an RF front end for receiving from and transmitting to the device reader RF signals and extracting power and data from an RF signal generated by the device reader, a controller for receiving from and transmitting to the RF front end data, and a memory for receiving from and transmitting to the controller data. The memory is readable and writable by the controller and operable using first and second voltage supplies during read and write operations, respectively, the first and second voltage supplies being of different voltage supply levels.  
         [0015]     Additional objects and advantages of the present invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present invention.  
         [0016]     The objects and advantages of the present invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter. 
     
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING  
       [0017]     The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present invention and, together with the general description given above and the detailed description of the embodiments given below, serve to explain the principles of the present invention in which:  
         [0018]      FIG. 1  is a block diagram of an RFID device according to the embodiment of the invention;  
         [0019]      FIG. 2  is a schematic diagram of an RF front end block in the RFID device of  FIG. 1 ;  
         [0020]      FIGS. 3A and 3B  are timing diagrams illustrating encoded data decoded in a two-stage decoding process using a forward deduction scheme implemented in a digital block in the RFID device of  FIG. 1 ;  
         [0021]      FIGS. 4A and 4B  are flowcharts of an implementation the decoding process of  FIGS. 3A and 3B ; and  
         [0022]      FIG. 5  is a circuit diagram of a DC-DC converter in the RFID device of  FIG. 1 . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0023]     Embodiments of the invention are described hereinafter for addressing the need for a low-power, passive RFID device having different operating voltage supplies and clock frequencies for performing power-saving operations.  
         [0024]     A low-power, passive RFID device  100  according to an embodiment of the invention is described hereinafter with reference to FIGS.  1  to  5 . The RFID device  100  exemplifies one of many RFID devices typically used in conjunction with an RFID device reader to form an RFID system. Such an RFID system typically performs identification-based applications by firstly identifying the RFID devices in proximity through interrogation, which is a process consisting of the RFID reader broadcasting an interrogation signal and in response receiving signals from the RFID devices being interrogated bearing identification information relating to the object and other data.  
         [0025]     The overall architecture of the RFID device  100  is described hereinafter with reference to  FIG. 1 , which is a block diagram depicting circuit blocks of the RFID device  100 . Each circuit block is configured internally and vis-à-vis other blocks for passive, low-power operations and directed at facilitating optimal miniaturized implementation of the RFID device  100 . The RFID device  100  may then be implemented as a chip, tag, or card as known to those skilled in the art. An RF frequency of a range of 300 MHz to 3 GHz is used in the embodiment.  
         [0026]     In the RFID device  100 , an antenna  102  receives interrogation or downlink signals generated and broadcasted by a RFID device reader (not shown), which are delivered to power generation blocks  104 ,  106 ,  108  for generating the required operating power from a carrier, for example a 2.45-GHz carrier, in the interrogation or downlink signals. The power generation blocks  104 ,  106 ,  108  include a rectifier  104 , a regulator  106 , and a capacitor bank  108 .  
         [0027]     In a passive device such as the RFID device  100 , such blocks are critical to the operability of their host device because the generated operating power is supplied to all other circuit blocks in the RFID device  100 . The level of voltage is proportional to the distance between the RFID device  100  and the device reader so that a very high voltage is generated to destroy some blocks of the RFID device  100  if the distance is very short. The rectifier  104  provides a rectified voltage and the regulator  106  maintains the rectified voltage below safe operating limits so that a generated operating voltage Vdd is typically kept low (˜1V) to minimize power consumption within the RFID device  100 . The capacitor bank  108  provides temporary or short-term storage of the power generated by tapping the operating voltage Vdd. The operating voltage Vdd is used to power all circuit blocks, except a memory  110 , which operates with higher operating voltage supplies.  
         [0028]     A dc-dc converter  112  is connected to the output of the power generation blocks  104 ,  106 ,  108  for accepting the operating voltage Vdd and from that generates the higher operating voltage supplies for the memory  110  to perform memory operations. The dc-dc converter  112  outputs a higher voltage Vdd-h for read and write operations which through programming the voltage level is double- or triple-times that of the operating voltage Vdd, respectively. For the same reason, a logic translator  114  is also connected to the dc-dc converter  112  and used as an interface for bridging logic levels between other digital circuit blocks in the RFID device  100  and the memory  110 . The logic translator  114  converts the logic level of data received from the memory  110  from Vdd-h (=2×Vdd, for example) to Vdd during read operations, and of data transmitted to the memory  110  from Vdd to Vdd-h (=3×Vdd, for example) during write operations. This allows other circuit blocks to operate with the lowest available operating voltage supply, ie Vdd, instead of the highest operating voltage so that the overall power consumption of the RFID device  100  is minimized.  
         [0029]     A modem  116  is connected to the antenna  102  for demodulating downlink signals containing an incoming RF carrier with downlink data, hereinafter referred to as data 2   bb , and modulating the same incoming RF carrier with uplink data, hereinafter referred to as data 2   rf , into uplink signals. Preferably, communication protocol used includes OOK/ASK modulation and Manchester coding for downlink and uplink communication, whereas uplink communication is achieved by modulating the incoming RF carrier with data 2   rf  through backscattering technique, which involves reflecting the incoming carrier by changing impedance.  
         [0030]     A digital block  118  performs power management of the RFID device  100  and controls logic switching in order to minimize instantaneous power consumption of the RFID device  100 . A power management logic module (not shown) in the digital block  118  is responsible to power up only the necessary blocks for each stage for operations. The digital block  118  also performs and/or processes anti-collision logic, command control and interpretation, Manchester coding-decoding and memory control logic.  
         [0031]     The digital block  118  is connected to the dc-dc converter  112  for performing power management by controlling via a control signal nR_W, the on/off switching of the dc-dc convener  112  and voltage level of the higher voltage Vdd-h. The digital block  118  is also connected to the modem  116  for processing downlink and uplink data 2   bb  and data 2   rf , respectively, and controlling via a control signal Cont_mod, the on/off switching of the modem  116 , and the logic translator  114  for reading from and writing to the memory  110 . The digital block  118  is further connected to a clock generator  122  for controlling via a control signal Cont_clk, the generation of different clocks with different frequencies.  
         [0032]     Other circuit blocks in the RFID device  100  include a power-on-reset circuit  120  that generates reset pulses for the digital block  118  and the clock generator  122  under a wide range of voltage supply conditions, and a low-power current reference  124  that generates bias current in nA for the digital block  118  and clock generator  122 . The RFID device  100  also includes the clock generator  122 , which is a programmable low-power oscillator that generates MHz clocks f 1 , f 2 , and f 3 , for the digital block  118 , the memory  110  through the logic translator  114 , and the dc-dc converter  112 , respectively. During communication with the RFID device reader and the RFID device  100  accesses the memory  110  in read operations, the same clock frequency is supplied to the digital block  118  and dc-dc converter  112 , ie f 3 =f 1 , and no clock is required by the memory  110 , ie f 2 =0. During memory write operations, the same clock frequency is supplied to the digital block  112  and memory  110 , ie f 2 =f 1 , while a clock frequency at a fraction, for example quarter, of f 1  is supplied to dc-dc converter  112 , ie f 3 =f 1 /4. With this scheme, only one oscillator is required in the clock generator  122  for generating f 1  while other clock frequencies are dependent on f 1  and as a result the various circuit blocks are supplied with different clock frequencies during different situations such as the read and write operations performed on the memory  110 .  
         [0033]     With the programmable dc-dc converter  112  and logic translator  114 , the RFID device  100  is able to minimize power consumption while ensuring proper logic level between various circuit blocks operating under different operating voltage supplies. With the programmable clock generator  122 , the RFID device  100  is able to minimize power consumption and reduce component count while satisfying different clock requirements of different circuit blocks in the RFID device  100 .  
         [0034]     As shown in  FIG. 2 , an RF front end in the RFID device  100  consists of three major components, namely the rectifier  104 , a demodulator  204  and a modulator  208 . The demodulator  204  and modulator  208  forms the modem  116  and the rectifier  104  is implemented as a rectifying device  202 , which serves as a virtual battery to power up the RFID device  100  by rectifying the downlink signal. The demodulator  204  detects the envelope of an OOK modulated downlink signal for processing by baseband circuit blocks such as the digital block  118 . The modulator  208  modulates uplink CW waves by using the backscattering method.  
         [0035]     A conventional voltage doubler is adopted as a rectifier core of the rectifying device  202 , consisting of diodes D 1  and D 2  where the cathode of D 1  is connected to the anode of D 2  for providing the voltage doubler is employed as the rectifier core of the rectifying device  202 .  
         [0036]     The downlink signal is provided to the rectifying device  202  through a capacitor Cx at the inter-connection between D 1  and D 2  and a bypass-capacitor C 1  is connected to the output of the rectifier core to smooth out the voltage at the output to provide the operating voltage Vdd.  
         [0037]     The demodulator  204  is constructed by connecting the anode of a diode D 3  to the inter-connection between D 1  and D 2  thereby allowing the demodulator  204  to tap the downlink signal for detection. With proper selection of resistor R 2  and capacitor C 2  connected to the cathode of D 3 , R 2  and C 2  being in parallel, an RC time constant of the demodulator  204  is selected such that the demodulator  204  filters out the incoming RF carrier but traces the envelope of the OOK-based downlink signal. R 2  may be replaced with a current source (not shown) to drain the current at the inter-connection between D 3  and R 2  and C 2 . The current source is switched off to save current drawn at idling time.  
         [0038]     According to the embodiment, all diodes are implemented using MOS devices configured as diodes.  
         [0039]     The detected baseband signal is further converted into binary levels by a low-frequency comparator  206  with built-in hysteresis. An input terminal of the comparator  206  is connected to a reference voltage, ref (=Vdd/2, for example), which can be generated with a resistor divider and another input terminal of the comparator  206  is connected to the cathode of D 3 . A binary coded signal is obtained at an output terminal of the comparator  206 , which is provided as data signal data 2   bb.    
         [0040]     The modulator  208  consists of resistor R 1  and a switch Sw through which data 2   rf  to be transmitted to the RFID device reader in uplink signals is delivered, the switch Sw being connected in series with R 1  and the free end of the R 1  being connected to the cathode of D 3 . Backscattering is achieved by switching on/off of additional DC loading at R 1 .  
         [0041]     An off-chip printed dipole antenna is designed and used as the antenna  102  to match to the composite input impedance of the RF front end.  
         [0042]     With reference to  FIGS. 3A, 3B ,  4 A and  4 B, the Manchester decoding scheme implemented in the digital block  118  is described hereinafter.  
         [0043]     There are currently numerous conventional Manchester decoding schemes. Some of these conventional schemes involve the use of clock recovery circuits for synchronizing input data and clock. With the Manchester decoding scheme, hereinafter referred to simply as the decoding scheme, data may be decoded without a clock recovery circuit or signal-edge detection means.  
         [0044]     The decoding scheme comprises of a two-stage process, i.e. stage  1  for pulse-width synchronization and stage  2  for data decoding as shown in  FIGS. 3A and 3B , which are timing diagrams depicting examples of encoded data, and  FIGS. 4A and 4B , which are flowcharts exemplifying an implementation of stages  1  and  2 , respectively.  
         [0045]     In Stage  1 , synchronization bits in the encoded data are detected for providing references for low-pulse and high-pulse widths. In Stage  2 , such references are then used for decoding data bits in the encoded data to obtain decoded data, hereinafter being referred to as Data [0 . . . (DataSize-1)]. The DataSize value reflects the number of data bits in the decoded data, out of which the first four bits are used as synchronization bits in the example.  
         [0046]     In Stage  1 , which is shown in  FIG. 4A  and begins with a step  402  in which a sequence of data stream in data 2   bb  is processed, when encoded data in data 2   bb  is detected to transition from 1 to 0 in a step  404 , a counter Cntr, which is initialized to 0, is incremented in a next step  406 . Thereafter in a step  408  the counter value Cntr is compared with the integer value 2, where if there is a mismatch the counter value Cntr is again compared with the integer value 4 in a step  410 . If there is a match in the step  410  Stage  1  ends and Stage  2  begins and if there is a mismatch the process loops back to the step  404 .  
         [0047]     In the example the integer value of 4 is used in the step  410  because the number of synchronization bits are set at 4. Also the integer value of 2 is used in the step  408  because it is intended that low-pulse and high-pulse widths if the second synchronization bit is measured for providing the references.  
         [0048]     If there is a match in the step  408 , the process enters a step  412  where the low-pulse width A of the second synchronization bit, as shown in  FIG. 3A , is measured with respect to the system or internal clock of the RFID device  100 . In a next step  414  the measured pulse width is checked whether it remains low for an extended time as predefined in Max Width, which consists of maximum values, in which if it is true the measurement is regarded as corrupted and discarded in a step  416 , after which the process then loops back to the step  402  in which a next sequence of data steam in data 2   bb  is processed.  
         [0049]     If it is false in the step  414 , i.e., if the measured pulse width does not remain low for an extended time, the process enters a step  418  in which the encoded data in data 2   bb  is detected to transition from 0 to 1 the high-pulse width B of the second synchronization bit, as shown in  FIG. 3B , is measured with respect to the clock of the RFID device  100  in a next step  420 . This measurement is then checked in a step  422  and if the measured pulse width remains high for an extended time as predefined in Max Width it is discarded in a step  424 , after which the process looks back to the step  402  for processing the next sequence of data stream in data 2   bb . Otherwise the process loops back to the step  404 .  
         [0050]     In Stage  2 , which is shown in  FIG. 4B  and begins with a step  452 , initialization for Stage  2  occurs in a step  454  in which the decoded data Data [0 . . . (DataSize-1)] is set to the value 0 and a variable Sampling Mode is set to High Sample. DataSize is indicative of the number of bits in the decoded data. When the Sampling Mode is set to High Sample the process measures the high-pulse width of the encoded data bits and when the Sampling Mode is set to Low Sample the process measures the low-pulse width of the encoded data bits.  
         [0051]     In a step  456 , the counter value Cntr is compared with DataSize, and if the counter value Cntr is lower the process enters a next step  458 . Otherwise the process ends.  
         [0052]     In the step  458  Sampling Mode is checked if it is set to High Sample, and if there is a match the process in a step  460  measures the current high-pulse width C, which includes the high-pulse width of the current encoded data bit, starting at the low-to-high transition of the current encoded data bit and ending at the next high-to-low transition. This measurement is then compared with (B+(A/2)) in a step  462  and if C is greater than (B+(A/2)), the current encoded data bit is assigned a “1” in a step  464  and as shown in  FIGS. 3A and 3B . Then in a next step  466  Sampling Mode is set to Low Sample, following which the counter is incremented in a step  468 . The measurement is next tested against the respective maximum value in Max Width in a step  470 , which when exceeded by the measurement it is discarded in a step  472 , after which the process looks back to the step  402  for processing the next sequence of data stream in data 2   bb . If the maximum values are not exceeded the process loops back to the step  456 .  
         [0053]     If in the step  462  C is not greater than (B+(A/2)) the current encoded data bit is assigned a “0” in a step  472  and in a next step  468  Sampling Mode is set to High Sample. The process from thence continues with the counter increment step  468 .  
         [0054]     If in the step  458  there is no match in a step  476 , the process measures the current low-pulse width D, which includes the low-pulse width of the current encoded data bit, starting at the high-to-low transition of the current encoded data bit and ending at the next low-to-high transition. This measurement is then compared with (A+(A/2)) in a step  478  and if D is greater than (A+(A/2)), the current encoded data bit is assigned a “0” in a step  480 , and as shown in  FIGS. 3A and 3B . Then in a next step  482  Sampling Mode is set to High Sample, following which the counter is incremented in the step  468 . The measurement is next tested against the respective maximum value in Max Width in the step  470 , which when exceeded by the measurement it is discarded in the step  472 , after which the process looks back to the step  402  for processing the next sequence of data stream in data 2   bb . If the respective maximum value is not exceeded the process loops back to the step  456 .  
         [0055]     If in the step  478  D is not greater than (A+(A/2)) the current encoded data bit is assigned a “1” in a step  484  and in a next step  486  Sampling Mode is set to Low Sample. The process from thence continues with the counter increment step  468 .  
         [0056]     In the decoding scheme Stage  2  of the process performs decoding via a forward deduction technique which involves the measurement of either a low-pulse or high-pulse width starting at the transition of a current encoded data bit, therefore measuring at least the second-half of the bit interval of the current encoded data bit, for determining the next encoded data bit value using references of both low- and high-pulse widths measured during Stage  1 .  
         [0057]     The dc-dc converter  112  is described in further details with reference to  FIG. 5  for providing a method to prevent transient current surge in the RFID device  100 . As critical as it is for passive devices such as the RFID device  100  to perform low-power operations, it is also unacceptable if circuit blocks in the RFID device  100  consume large dynamic currents even though the overall average current consumed is low. This usually occurs when circuit blocks are turned-on during power-on and huge surge currents are used to charge internal nodes within these circuit blocks.  
         [0058]     In power management concepts, which usually involve turning on/off circuit blocks during actual operation to save power, this can be the factor that causes the device to malfunction because of large voltage supply dip.  
         [0059]     The dc-dc converter  112  consists of a current-clamp circuitry  502  and a charge-pump circuit  504 . The current-clamp circuitry  502  is placed between the output of the rectifier  104  to accept the rectified voltage (Vdd) and the charge-pump circuit  504 . The current-clamp circuitry  502  serves to control current flow during the operation of the charge-pump circuit  504 .  
         [0060]     As shown in  FIG. 5 , the current-clamp circuitry  502  employs two PMOS switches having their output terminals inter-connected, one PMOS being high on-resistance (R on )  506  and another PMOS being of low R on    508 . These switches are controlled by a logic module  510  and are switched off/on accordingly. When the memory  110  is not accessed, both these switches are turned off.  
         [0061]     The logic module  510  performs switching so that when the current clamp circuitry  502  starts operating, only the high-R on  PMOS  506  is tuned on. This limits the amount of current that can be drawn from the rectifier  104 . There is an internal counter (not shown) in the logic module  510  that starts counting for 32 clock cycles, after which the low-R on  PMOS  506  is turned on for normal operation (EOC=1).  
         [0062]     The advantages of RFID device  100  are manifold. The advantages associated with the RF front end are as follows:  
         [0063]     (i) The RF Front End is implemented using a low-cost standard CMOS process, which is compatible with the mainstream technology for baseband circuitries, and allows a fully integrated solution in single silicon chip. In conventional proposals, the RF front end is constructed from high performance external Schottky diodes and the baseband circuit is implemented in CMOS process. While Schottky diodes offer the best RF performance, these devices are not available in standard CMOS process. The hybrid approach suffers from high cost with bulky structure, which offsets the added value inherent in RFID technology and prevents RFID from mass scale deployment.  
         [0064]     (ii) Reduced cost and form factor by eliminating external components and the associated assembly expense.  
         [0065]     (iii) More reliable performance because: 1) IC technology provides better device matching than discrete devices. 2) Avoid assembly misalignment of critical RF parts.  
         [0066]     (iv) Potential for integrating on-chip antenna to form a total RFID solution.  
         [0067]     The advantages associated with the current clamp circuitry  502  are as follows:  
         [0068]     (i) Current clamping allows proper power management to be applied to these modules without worrying for high surge current during re-powering.  
         [0069]     (ii) Additional circuit is small, mainly two switches and some flip-flops (digital is small in current technology)  
         [0070]     (iii) No current is consumed from the logic block during normal operation (pure digital), as such no additional wastage of power  
         [0071]     (iv) Additional circuit acts as a clean supply cut off from the charge-pump when not in use.  
         [0072]     In the foregoing manner, a low-power, passive RFID device having different operating voltage supplies and clock frequencies for performing power-saving operations is disclosed. Although only a number of embodiments of the invention are disclosed, it becomes apparent to one skilled in the art in view of this disclosure that numerous changes and/or modification can be made without departing from the scope and spirit of the invention. For example the Manchester decoding scheme is applicable to all ranges of incoming data duty cycle. Also in the current clamping circuitry, the digital counter value is a variable depending on implementation. The digital logic can be implemented in many other ways, as long as the delay is achieved to turn on the strong transistor, ie the low-R on  PMOS.