Abstract:
Transimpedance amplifiers (TIAs) are typically used within optical receiver modules to amplify weak photocurrents received from the photodetector, in the form of photodiode, or a PIN diode. Since TIAs are used to amplify weak photocurrents, noise in the resultant amplification of the weak photocurrent is typically a problem. However, TIAs must not only provide low noise amplification of weak photocurrents, but must also operate when a much higher optical power is received by the photodetector and hence a much higher photocurrent is provided to an input port of the TIA. Of course, with the higher photocurrent received from the photodetector the TIA must also exhibit acceptable bit error rate performance as with the lower photocurrents. An elevated front end TIA (EFTIA) is thus provided that offers low noise performance while providing a wide dynamic range, which overcomes the deficiencies of the prior art.

Description:
FIELD OF THE INVENTION  
       [0001]     The invention relates to the field of amplifier circuits and more specifically to the field of current sources for realizing low noise and wide dynamic range in transimpedance amplifier circuits.  
       BACKGROUND OF THE INVENTION  
       [0002]     The ever increasing demands for high capacity communications systems has resulted in a wide spread deployment of optical fiber networks across the world. A fundamental component used in such systems receives pulses of light and converts these into electrical signals. The pulses of light in such systems comprise a bit stream of information. This fundamental component employed in the fiber optic networks is commonly known as an optical receiver module. Within the optical receiver, a photodetector is typically employed to receive the light pulses and an amplifying circuit is employed for amplifying photocurrent generated within the photodetector.  
         [0003]     Transimpedance amplifiers (TIAs) are typically used within optical receiver modules to amplify and transform weak photocurrents received from the photodetector, in the form of a photodiode or a PIN diode. The TIA amplifies and transforms the photocurrent into an output voltage that is further provided to other stages of the optical receiver module. Since TIAs are used to deal with both strong and weak photocurrents, noise in the resultant amplification and transformation to a voltage signal is typically a problem. Indeed, for those skilled in the art of the design of TIAs, it is well understood and appreciated that the noise introduced by the TIA, in many circumstances, limits the ability of the optical receiver module to faithfully reconstruct the intended stream of information. Furthermore, a relationship between the rate at which the receiver produces errors—often called the Bit Error Rate (BER), and the noise generated by the TIA can be shown. Thus, the optical receiver module needs to have low noise amplification performed on the weak photocurrents in order to facilitate optical transmission of information. This is especially true in circumstances where the distance that the optical signal must travel is long and results in weak optical pulses at the receiver. It is known to those skilled in the art that long transmission distances—the distance between a transmitter and a receiver—serves to attenuate the initial transmitted optical signal strength and places a greater burden upon the receiver module to avoid errors. Furthermore, it is also known that cost of an optical communication system is reduced if a signal is transmitted along a longer length of optical fiber or, in the alternative, if less optical power is transmitted. Thus, providing low noise amplification for the TIA is important in order to reduce the bit error rate (BER) of the received and amplified signal.  
         [0004]     However, TIAs must not only provide low noise amplification of weak photocurrents, but must also operate when a much higher optical power is received by the photodetector and hence a much higher photocurrent is provided to an input port of the TIA. Thus, the TIA must exhibit wide dynamic range operation so that it does not suffer from input photocurrent overload, where the output voltage from the TIA is no longer linearly proportional to the input photocurrent. For example, if a TIA is used with a short transmission length of optical fiber, then the optical signal power levels received by the photodetector and amplified accurately can be much higher than when the TIA operates with much longer transmission lengths. Of course, with the higher photocurrent received from the photodetector, the TIA must also exhibit acceptable BER performance as with the lower photocurrents.  
         [0005]     In practice, in order to achieve a wide dynamic range for TIA operation, some form of switching circuit is typically used, or in some cases, an AGC is utilized in order to vary the transimpedance gain of the TIA. In U.S. Pat. No. 6,218,905, entitled “Common-gate transimpedance amplifier with dynamically controlled input impedance,” an AGC is utilized in order to vary the gain of the TIA. In U.S. Pat. No. 6,297,701, entitled “Wide dynamic range transimpedance amplifier,” an AGC function is realized by a transistor switching network.  
         [0006]     The most commonly used photodiode detector is the PIN diode, were the anode is usually connected to the input of the TIA while the cathode is connected to the positive voltage rail. Depending upon the type of PIN diode used, the wavelength of operation and possibly the data rate, the amount of reverse voltage required to allow the PIN diode to operate within its full dynamic range—from maximum sensitivity to overload—can vary between 5V to 0.8V. The reverse bias voltage requirement often dictates the circuit architecture of the front end transimpedance stage, which provides the input bias voltage to the PIN diode. As a result, performance compromises between sensitivity and overload typically occur.  
         [0007]     If high optical sensitivity is required from the receiver, the TIA input bias voltage is required to be as low as possible (0.8V), which provides maximum reverse bias voltage, thus the PIN diode exhibits minimum detector capacitance. However, this design approach reduces the overload performance of the TIA. On the other hand, if a higher overload is required, a TIA requires a higher input bias voltage, which in turn reduces the PIN diode reverse bias voltage, increasing the detector capacitance and reducing the optical receiver&#39;s sensitivity. The issue is exacerbated if a further requirement is to provide a 3.3V single rail operation, which can often restrict the input bias voltage required to offer both high sensitivity and overload performance from the TIA.  
         [0008]     A need therefore exists to provide a high reverse bias voltage required by a PIN diode operating at 1300-1550 nm wavelength and 10 Gbit/s from a 3.3V single supply rail and to providing sufficient reverse bias voltage to allow full dynamic range to be achieved without significant compromise in sensitivity and overload performance of the TIA.  
         [0009]     It is therefore an object of the invention to provide a TIA that offers wide dynamic range operation without resulting in a significant compromise between sensitivity and overload performance. It is a further object of the invention to provide a current source for biasing of the TIA.  
       SUMMARY OF THE INVENTION  
       [0010]     In accordance with the invention there is provided a circuit comprising: a transimpedance amplifier (TIA) circuit comprising a TIA input port, a first supply voltage input port, a second supply voltage input port, and a first amplification stage; a first MOSFET current source for receiving a feedback signal and for providing a first current to the first amplification stage; and, a feedback circuit for providing the feedback signal to the first MOSFET current source; a dummy TIA stage for replicating DC characteristics of the TIA circuit and for providing a control signal to the feedback circuit; and, a bias circuit for providing a bias voltage within a predetermined range below a first potential of the first supply voltage input port to the TIA input port.  
         [0011]     In accordance with the invention there is provided a circuit comprising: a transimpedance amplifier (TIA) circuit comprising a TIA input port, a first supply voltage input port, a second supply voltage input port, and a first amplification stage; a first MOSFET current source for receiving a feedback signal and for providing a first current to the first amplification stage; and, a feedback circuit for providing the feedback signal to the first MOSFET current source; a dummy TIA stage for replicating DC characteristics of the TIA circuit and for providing a control signal to the feedback circuit; a bias circuit for providing a reverse bias voltage within a predetermined range below a first potential of the first supply voltage input port to the TIA input port; and, a PIN diode connected to the TIA input port, where the reverse bias voltage available to the PIN diode is between 2.0V and 1.5V.  
         [0012]     In accordance with the invention there is provided a circuit comprising: a transimpedance amplifier (TIA) circuit comprising a TIA input port, a first supply voltage input port, a second supply voltage input port, and a first amplification stage; a first MOSFET current source comprising a first MOSFET for operating in a triode region for and for receiving a feedback signal and for providing a first current to the first amplification stage, the first current being relatively insensitive to at least one of temperature, DC supply voltage, and first MOSFET manufacturing tolerances; a feedback circuit for providing the feedback signal to the first MOSFET current source; a dummy TIA stage for replicating DC characteristics of the TIA circuit and for providing a control signal to the feedback circuit; and, a bias circuit for providing a bias voltage between 1.5V and 2.0V to the TIA input port.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]     Exemplary embodiments of the invention will now be described in conjunction with the following drawings, in which:  
         [0014]      FIG. 1  illustrates a prior art common emitter transimpedance amplifier (TIA) that uses a fixed input port bias voltage;  
         [0015]      FIG. 2  illustrates an elevated front end TIA (EFTIA); and,  
         [0016]      FIG. 3  illustrates a triode region MOSFET current source in accordance with an embodiment of the invention for biasing of a TIA. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0017]      FIG. 1  illustrates a commonly used first stage transimpedance amplifier (TIA)  100  arranged in a common emitter configuration. A collector terminal of transistor Q 1   101  is connected in series with a load resistor R 2   102  to a first voltage input port  100   c , preferably at a positive supply voltage and an emitter terminal of the input transistor Q 1   101  is connected to a second voltage input port  100   d , which is at a potential below that of the first voltage input port  100   c  and is preferably connected to ground. A base terminal of the input transistor  101  is connected to receive current for amplification, such as photocurrent from a photodiode  107 , preferably in the form of a PIN diode  107  having its anode coupled to a TIA input port  100   a  and its cathode coupled to the first voltage input port  100   c . In this typical configuration, the base terminal of the input transistor Q 1   101  has a potential of one Vbe above ground and thus has an approximate potential of 0.8V. The collector terminal of the input transistor Q 1   101  is optionally connected to cascode transistors (not shown) or to a load resistor R 2   102 . Transistor Q 2   103  and resistor R 3   104  in combination with a feedback resistor R 1   105  provide an emitter follower circuit. The emitter of transistor Q 2   103  is used to provide a closed loop path in combination with a feedback resistor R 1   105  to form a shunt feedback circuit for shunting of an output signal of the TIA  100 . This shunt feedback circuit is used to set the gain of the TIA  100 . Transistor Q 3   106 , disposed in a diode configuration, is used to provide a DC level shift in the output signal provided from the TIA output port  100   b . This DC level shift facilitates the connection of the first stage TIA  100  to a subsequent signal processing stage (not shown) connected thereto.  
         [0018]     Connecting the emitter terminal of the input transistor Q 1   101  directly to ground allows for a maximum open loop gain to be provided by the first stage TIA  100 . This connection allows for the use of a high value feedback resistance R 1   105  and offers reduced input signal noise. Unfortunately, although the common emitter configuration shown in  FIG. 1  is often used to provide a low noise TIA  100 , this low noise performance is achieved at the expense of high overload performance. The base voltage of input transistor Q 1   101  determines the voltage drop across R 3   104 . Assuming that negligible base current is flowing in the input transistor Q 1   101 , the voltage drop across R 3   104  is approximately 0.8V, which is the Vbe of the input transistor Q 1   101 . Unfortunately, this voltage drop restricts the amount of voltage swing at the emitter terminal of output transistor Q 2   103  and thus restricts the amount of voltage swing at the TIA output port  100   b . Of course, reducing the value of the feedback resistor R 1   105  reduces the voltage swing at the output port  100   b , but the resulting decrease in gain results in increased output signal noise. In addition, a maximum reverse voltage for the PIN diode  107  of 2.5V is provided, for a positive supply voltage of 3.3V, which reduces the PIN diode  107  capacitance.  
         [0019]     An alternative approach to that shown in  FIG. 1  is to elevate the input bias voltage of the TIA input port above one Vbe, as is shown in  FIG. 2 .  FIG. 2  illustrates an elevated front end TIA (EFTIA)  200 . An EFTIA input port  200   a  is provided for receiving a current from a photodiode  207  having an anode terminal coupled thereto. An EFTIA output port  200   b  is provided for providing an amplified signal therefrom. A cathode of the PIN diode  207  is coupled to a first voltage input port  200   c  for receiving a positive supply voltage, preferably having a potential of 3.3V. A second voltage input port  200   d  is provided on the EFTIA  200  for receiving a voltage at preferably a ground potential.  
         [0020]     Transistors Q 1   201  and Q 3   203  form a first long tail pair having emitter terminals of transistors Q 1   201  and Q 3   203  connected to a collector terminal of transistor Q 4   204 , which forms a first current source having a first bias port  204   a  for controlling the current provided therefrom. Optionally, the collector terminal of Q 1   201  is connected to a cascode transistor (not shown) or as is shown in  FIG. 2 , in series with a load resistor R 2   212  and the first voltage input port  200   c . An emitter follower circuit is provided by transistor Q 2   202  and resistor R 3   213 , which provide a closed loop signal path to the EFTIA input port  200   a  using resistor R 1   211 . This closed loop signal path provides shunt feedback that is used in providing the gain for the EFTIA  200 . A bias voltage, Vpos-1.5V is provided by the second current source ( 12 )  205  and resistor R 4   214  connected to the base terminal of transistor Q 3   203 . Capacitor C 1   221  connected in parallel with the second current source  205  is used to provide an AC ground and to limit the amount of thermal noise generated by resistor R 4   214  disposed between the first voltage input port  200   c  and an output port of the second current source  205 . Load resistor R 2   212  is used to set a collector current for transistor Q 1   201 . To provide reduced EFTIA noise, the collector current of transistor Q 3   203  is preferably much greater than the collector current of transistor Q 1   201 , thus ensuring that the emitter terminal of transistor Q 3   203  provides low AC impedance. However, at high frequencies, the emitter of transistor Q 3   203  begins to appear as a high impedance path, therefore the shunt capacitance C 2   222 , disposed for connecting the emitter terminal of transistor Q 1   201  to the second voltage input port  200   c  provides a low impedance path for these high frequencies to ground, thus providing low noise and high open loop gain for the EFTIA  200 . By providing a bias voltage of Vpos-1.5V to the base terminal of transistor Q 3   203 , the base terminal of transistor Q 1   201  is approximately equal in potential to the base terminal voltage of transistor Q 3   203  and thus a reverse bias voltage of 1.5V is provided to the PIN diode  207 .  
         [0021]     Although the common emitter configuration TIA  100  shown in  FIG. 1  is often used to provide a low noise TIA  100 , this low noise operation is at the expense of high overload performance, since the voltage across resistor R 3   104  is determined by the base voltage of transistor Q 1   101  and is thus at a potential of only 0.8V-assuming of course that transistor Q 1   101  has negligible base current flowing therein. This unfortunately restricts the amount of voltage swing at the emitter terminal of transistor Q 2   103  and thus restricts the amount of voltage swing at the output port  100   b  of the common emitter TIA. Reducing the value of the feedback resistor R 1   105  reduces the voltage swing at the output port  100   b , but with the resulting decrease in amplifier gain, there is an increase in circuit noise. In addition, the potential difference developed across resistor R 2   102  divided by the thermal voltage (Vt) of transistor Q 1   101 , where Vt equals approximately 25 mV, determines the open loop gain of the common emitter TIA  200 . Unfortunately, the open loop gain is dependent upon the supply voltage variation of Vpos provided to the first voltage input port  100   c . Furthermore, with low voltages of operation where Vpos=3.3V, this issue is exacerbated.  
         [0022]     The EFTIA design shown in  FIG. 2  advantageously provides greater overload performance than the common emitter design shown in  FIG. 1 , since the voltage drop across resistor R 3   213  is determined by the base voltage of transistor Q 3   203  and is thus at a potential of Vpos-1.5V. In addition, the voltage across load resistor R 2   212  is no longer supply voltage (Vpos) dependant and thus a constant open loop gain is realized for the EFTIA  200 . The input port bias voltage  200   a  is maximized at 1.8V (Vpos-1.5V), since below this voltage the constant current source formed from transistor Q 4   204  saturates. As such, the available reverse voltage bias range provided for the PIN diode  207  from the two circuit techniques shown in  FIG. 1  and  FIG. 2  is 2.5V or 1.5V, respectively. If an EFTIA input port bias voltage is preferred above 0.8V but below 1.5V then the circuits shown in  FIG. 1  and  FIG. 2  are unable to provide this amount of reverse bias voltage.  
         [0023]      FIG. 3  illustrates an embodiment of the invention, an amplifier circuit architecture  300  that provides a 1.3V input port bias voltage for a long wavelength-1300 nm-1500 nm—PIN diode  307  for use with optical signals clocked at over 10 Gbit/s. This amplifier circuit architecture  300  is preferably fabricated using a BiCMOS process. As is illustrated in  FIG. 3 , the amplifier circuit architecture  300  is divided into three parts, an EFTIA Stage  301  (similar to that illustrated in  FIG. 2 ), a dummy EFTIA Stage  302  (similar to that illustrated in  FIG. 2 ) and a Feedback Control circuit  303 . The EFTIA stage  301  comprises first and second transistors Q 1   311  and Q 2   312 , which form a first long tail pair, with the emitter terminals of transistors Q 1   311  and Q 2   312  connected to the drain of MOSFET M 1   321 , which forms a first MOSFET current source for providing a first current therefrom. A first current source formed by transistor Q 4   314  and resistor R 5   335  is used to provide a third current, in the form of a preferably constant current, to the emitter follower provided by transistor Q 3   313  and resistor R 3   333 .  
         [0024]     Resistor R 3   333  is used to provide a constant voltage drop, which provides a DC level for an output voltage for use in connecting the EFTIA stage  301  output port  300   b  to a subsequent signal processing stage (not shown). Shunt feedback resistor R 4   334  is connected between the base terminal of transistor Q  1311  and the collector terminal of transistor Q 4   314 , which forms part of the first current source. Resistors R 1   331  and R 2   332  determine the collector current of transistor Q 1   311 , while capacitor C 3   343  is used to provide a ‘zero pole’ compensation and to aid closed loop stability of the EFTIA stage  301 . The collector current of transistor Q 1   311  is predetermined to be at a value that provides low noise performance, while the collector current of transistor Q 2   312  is arranged to provide a much higher collector current, as compared to the collector current of transistor Q 1   311 , to ensure that at low frequencies the emitter terminal of transistor Q 2   312  appears as a low impedance, which terminates at a base capacitance of capacitor C 4   344 , disposed between the base terminal of transistor Q 2   312  and the second voltage input port  300   d . At high frequencies, however, the emitter terminal of transistor Q 2   312  appears as a high impedance, therefore shunt capacitance C 1   341  provides a low impedance path for these high frequency signals to the second voltage input port, which is preferably coupled to ground. This arrangement thus provides low noise and high open loop gain for the EFTIA stage  301 . Transistor Q 5   315  disposed in a diode configuration is used to limit the Vce voltage of transistor Q 2   312  provided from the first voltage input port  300   c . Capacitors C 2   342  and C 5   345  are used to limit amplification noise in the EFTIA stage  301 .  
         [0025]     The bias voltage applied to the base terminal of transistor Q 2   312  is determined by resistor R 12   352  and a fourth current supplied from the second current source  323 , disposed in the EFTIA Dummy stage  302 . Preferably, the bias voltage has a potential of Vpos-1.3V. This provides a potential difference between Vpos and the base terminal of transistor Q 1   311  that results in a preferably constant 2V reverse bias voltage being provided to the PIN diode  307 . In the Dummy EFTIA stage  302 , a bias control port  300   d  is coupled to the base terminal of transistor Q 4   314  and to the base terminal of transistor Q 8   318 . Transistors Q 6   316  and Q 7   317  form a second long tail pair and have their emitter terminals coupled to the drain of MOSFET M 2   322 , which forms a second MOSFET current source and provides a second current. A third current source is formed by transistor Q 8   318  and resistor R 10   370 , and it is used to provide a fifth constant current for the emitter follower provided by transistor Q 10   329  and resistor R 8   338 . Resistor R 9   339  disposed between the collector terminal of transistor Q 8   318  and the base terminal of transistor Q 6   316  is used to form a feedback path within the Dummy EFTIA stage  302 . Resistors R 7   337  and R 6   336  are used to provide a predetermined voltage drop from the first voltage input port to the base terminal of transistor Q 10   329  and the collector terminal of transistor Q 6   316 . The bias control port  300   d  is used to set a third current provided by the first current source, including transistor Q 4   314 , and a fifth current provided by the third current source, including transistor Q 8   318 , in order to control the DC bias at the base terminals of transistors Q 1   311  and Q 6   316 , respectively.  
         [0026]     To provide a 2V reverse bias voltage for the PIN diode  307 , the first MOSFET current source formed by MOSFET M 1   321  preferably operates with 0.5V potential difference between its drain and source terminals (Vds=500 mV). This causes MOSFET M 1   321  to operate in the triode region of operation.  
         [0027]     If a fixed bias voltage is applied to the gate terminal of MOSFET M 1   321 , then the current at the drain terminal of MOSFET M 1   321  varies with the potential on the first supply voltage input port  300   c  (Vpos). This unfortunately alters the DC bias conditions of the input port  300   a  for the EFTIA stage  310 . To prevent this altering of the DC bias condition, the Dummy EFTIA stage preferably replicates the DC operating conditions of the EFTIA stage  301 .  
         [0028]     Within the Dummy EFTIA stage  302 , the transistor Q 5   315  disposed in a diode configuration, found in the EFTIA stage  301 , is optionally replaced with a resistor R 11   351 . The value of resistor R 11   351  is predetermined to provide a same voltage drop across its terminals as that realized by transistor Q 5   315 . Capacitor C 6   346  is used to provide amplification stability in the Dummy EFTIA stage  302  and to reduce noise therein. The voltage at the collector terminal of transistor Q 7   317  is applied to a positive input port  360   a  of an operational amplifier  360  disposed with the Feedback Control Circuit  303 . A proportional to absolute temperature (PTAT) current source is formed by transistor Q 9   319  and resistors R 23  through R 26   353  disposed in series between a transistor Q 9   319  emitter terminal and the second voltage input port  300   d . This PTAT current source is used to provide a same potential difference across resistors R 13  through R 22   354 , disposed in series between first voltage input port  300   c  and a negative input port  360   b  of operational amplifier  360 , as is provided across resistor R 11   351  disposed within the Dummy EFTIA stage  302 . This PTAT current source, however, provides approximately {fraction (1/10)} th  the current that flows through the collector terminal of transistor Q 7   317 , which has an approximately equal collector current to that of transistor Q 2   312 . Capacitor C 7   347  is used to limit thermal noise contributions of resistors R 13 -R 22   354 .  
         [0029]     The operational amplifier  360  output port  360   c  is connected to the gate terminal of MOSFET M 2   322  and MOSFET M 1   321  for providing a closed circuit loop. An output signal, in the form of a feedback signal, from the operational amplifier output port  360   c  is provided as a “master” signal, in the form of a fourth bias voltage, to the gate terminal of MOSFET M 2   322  and as a “slave” signal, in the form of a first bias voltage, to the gate terminal of MOSFET M 1   321 . This results in the current at the collector terminals of transistors Q 7   317  and Q 2   312  being determined by the PTAT current source formed by transistor Q 9   319  and is thus independent of first voltage input port  300   c  supply voltage (Vpos) variation and the triode region characteristic of MOSFETS M 1   321  and M 2   322 . A PTAT current source bias port  300   f  coupled to the base terminal of transistor Q 9   319  is provided for externally controlling the amount of current provided by the PTAT current source  319 .  
         [0030]     Optionally, a resistor is used within the circuit of  FIG. 3  to replace MOSFET M 1   321 , which provides the first current at the emitter terminals of transistors Q 1   311  and Q 2   312 . However, if this substitution is made then the bias voltage applied to transistor Q 2   312  is no longer independent of the first voltage input port  300   c  voltage fluctuations, which unfortunately results in the open loop gain of the EFTIA stage  301  varying in gain with variations in Vpos. Further optionally, the PTAT current source  319  formed by transistor Q 9   319  is designed to provide a constant controllable current in response to an external signal received at the PTAT current source bias port  300   f.    
         [0031]     Advantageously, by using the circuit illustrated in  FIG. 3 , an approximately 2V reverse bias voltage is provided for reverse biasing of the PIN diode  307 , while a constant open loop amplifier gain is provided thereto. This is advantageous over the circuit shown in  FIG. 1  since the input bias voltage is pre-determined to be at a potential of greater than Vbe, thus improving overload. The embodiment of the invention is also advantageous over that shown in  FIG. 2  because the EFTIA of  FIG. 2  only allows for a 1.5V reverse bias voltage to be provided to the PIN diode  307 . Having a larger reverse bias voltage provided to the PIN diode  307  advantageously allows for wide dynamic range operation of the TIA  300 .  
         [0032]     The embodiment of the invention advantageously provides a reverse bias voltage on the PIN diode and thus the PIN diode exhibits minimum—or reduced—detector capacitance. With minimal detector capacitance higher optical data rates are receivable by the PIN diode. The embodiment of the invention also allows for high overload performance since a higher input port bias voltage, than that which is attainable in the prior art, is provided thereto. Because of the higher PIN diode reverse bias voltage, the PIN diode capacitance is not increased and the PIN diode sensitivity is not decreased. Thus, the input port bias voltage provided by the embodiment of the invention offers both high sensitivity and overload performance when used with a PIN diode coupled thereto.  
         [0033]     Furthermore, the embodiment of the invention is formable using a BiCMOS process that allows for the integration of the amplifier circuit  300  into single die. This allows for the photodetector to be directly attached to the die and thus facilitates the formation of a compact receiver package.  
         [0034]     Numerous other embodiments may be envisaged without departing from the spirit or scope of the invention.