Abstract:
A method of manufacturing porous-Si capacitors for use in semiconductor memories is disclosed herein. The present invention includes a SOG layer as an etching mask to etch a polysilicon layer to form a porous-Si structure. The etching process is performed to etch a portion of the first conductive layer and to etch away the remaining HSG-Si. Next, the residure SOG layer is removed to define a porous-Si bottom storage. Utilizing the porous-Si structure, the present invention can be used to increase the surface area of the capacitor.

Description:
FIELD OF THE INVENTION 
     The present invention relates to semiconductor capacitors, and more specifically, to a method of making a porous-Si capacitor DRAM cell. 
     BACKGROUND OF THE INVENTION 
     Semiconductor Dynamic Random Access Memory (DRAM) devices have many memory cells. Indeed, a memory cell is provided for each bit stored by a DRAM device. Each memory cell typically consists of a storage capacitor and an access transistor. Either the source or drain of the access transistor is connected to one terminal of the capacitor. The other side of the transistor and the transistor gate electrode are connected to external connection lines called a bit line and a word line, respectively. The other terminal of the capacitor is connected to a reference voltage. The formation of a DRAM memory cell comprises the formation of a transistor, a capacitor and contacts to external circuits. The capacitor type that has been typically used in DRAM memory cells are planar capacitors, because they are relatively simple to manufacture. 
     In order to achieve high performance (i.e. high density) DRAM devices, the memory cells must be scaled down in size to the submicrometer range. As the capacity of DRAMs has increased, the sizes of the memory cells have steadily decreased. If planar capacitors are used, as the memory cells decrease in size, the area of the capacitors also decrease, resulting in a reduction of cell capacitance. For very small memory cells, planar capacitors become very difficult to use reliably. Specifically, as the size of the capacitor decreases, the capacitance of the capacitor also decreases and the amount of the charge capable of being stored by the capacitor similarly decreases. This results in the capacitor being very susceptible to α particle interference. Additionally, as the capacitance decreases, the charge held by storage capacitor must be refreshed often. A simple stacked capacitor can not provide sufficient capacitance, even with high dielectric Ta 2  O 5  as the capacitor insulator. 
     Prior art approaches to overcoming these problems have resulted in the development of the trench capacitor (see for example U.S. Pat. No. 5,374,580) and the stacked capacitor(see for example U.S. Pat. No. 5,021,357). The trench capacitor has the well known problem of &#34;gated diode leakage,&#34; which is the leakage of current resulting in the trench capacitor failing to hold a charge. Reducing the thickness of the dielectric also can improve the capacitance of the capacitor, but this approach is limited because of yield and reliability problems. 
     A new capacitor over bit line cell with a hemispherical grain (HSG-Si) polysilicon storage node has been developed (see &#34;Capacitor-Over-Bit-Line Cell with Hemispherical Grain Storage Node For 64 Mb Drams&#34;, M. Sakao et al., microelectronics research laboratories, NEC Corporation. &#34;A Capacitor-Over-Bit-Line Cell with a Hemispherical Grain Storage Node For 64 Mb Drams&#34;, IEDM Tech Dig., December 1990, pp 655-658). The HSG-Si is deposited by low pressure chemical vapor deposition method at the transition temperature from amorphous-Si to polycrystalline-Si. This memory cell provides large storage capacitance by increasing the effective surface area of a simple storage node and is manufactured by optical delineation. The HSG-Si storage node can be fabricated by addition of two process steps, i.e. HSG-Si deposition and a etchback. A HSG-Si electrode node has been proposed (see &#34;New Cylindrical Capacitor Using Hemispherical Grain Si For 256 Mb Drams&#34;, H. Watanabe et al., microelectronics research laboratories, NEC Corporation). After the electrode structure is formed, a native-oxide on the electrode surface is removed by a diluted HF solution. HSG-Si appeared on silicon surface by using seeding method as disclosed in the paper of H. Watanabe. 
     SUMMARY OF THE INVENTION 
     The present invention thus provides capacitors with an enlarged surface area. The formation of the porous-Si capacitor described herein includes many process steps that are well known in the art. 
     A first dielectric layer is formed on a substrate, the first dielectric layer can be formed by using suitable material such as borophosphosilicate glass (BPSG) or TEOS-oxide. Next, a second dielectric layer is deposited on the first dielectric layer to serve as an etching barrier for subsequent process. The second dielectric layer is formed of nitride. A contact hole is formed in the first dielectric layer and second dielectric layer by patterning and etching them. A first conductive layer is formed over and in the contact hole and on the second dielectric layer. The first conductive layer is chosen from doped polysilicon or in-situ doped polysilicon. A HemiSpherical Grains silicon (HSG-Si) layer is formed on the first conductive layer with a thickness about 500-1000 angstroms. A slightly etching is used to etch the HSG-Si layer to separate the Si islands. Then a spin on glass (SOG)layer is formed on the HSG-Si. A thermal curing treatment is performed in N 2  at 400° C. to reflow the SOG layer. Next, a dry etching is used to etch the SOG layer to expose the top of the HSG-Si. Residual SOG layer is left on the first conductive layer after the etching process. An etching process is performed by using the residual SOG layer as a mask to etch a portion of the first conductive layer and the HSG-Si. The HSG-Si is totally removed during this etching process. The present invention uses the high etching selectivity between SOG layer and polysilicon to create cavities in the first conductive layer. The residual SOG layer is removed by wet etching. A porous-Si capacitor bottom storage node is formed while the residual SOG layer is stripped. A dielectric film is deposited along the surface of the first conductive layers and the nitride layer. Finally, a second conductive layer is deposited over the dielectric film. The second conductive layer provides a top storage electrode. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein: 
     FIG. 1 is a cross section view of a semiconductor wafer illustrating the step of forming a gate structure on a semiconductor substrate; 
     FIG. 2 is a cross section view of a semiconductor wafer illustrating the step of forming a first dielectric layer and a second dielectric layer on the semiconductor substrate; 
     FIG. 3 is a cross section view of a semiconductor wafer illustrating the step of forming a first conductive layer on said second dielectric layer; 
     FIG. 4 is a cross section view of a semiconductor wafer illustrating the step of forming a HSG-Si layer on the second dielectric layer; 
     FIG. 5 is a cross section view of a semiconductor wafer illustrating the step of etching the HSG-Si layer to form HSG-Si islands and forming a SOG layer on said HSG-Si islands; 
     FIG. 6 is a cross section view of a semiconductor wafer illustrating the step of curing SOG layer; 
     FIG. 7 is a cross section view of a semiconductor wafer illustrating the step of etching the SOG layer; 
     FIG. 8 is a cross section view of a semiconductor wafer illustrating the step of etching a portion of the first conductive layer and the HSG-Si; 
     FIG. 9 is a cross section view of a semiconductor wafer illustrating the step of forming a thin dielectric film along the surface of the first conductive layer; 
     FIG. 10 is a cross section view of a semiconductor wafer illustrating the step of forming a second conductive layer; and 
     FIG. 11 is a three dimension drawing of a bottom storage node. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The formation of the porous-Si capacitor described herein includes many process steps that are well known in the art. For example, the processes of photolithography masking and etching are well known in the art and are used extensively herein without a delated discussion of this well known technology. 
     In addition, the present invention uses residual SOG layer as an etching mask to form a porous-Si capacitor structure. Further more, the high etching selectivity between SOG and polysilicon (the relative susceptibility is about 100 to 1) is used to form the porous-Si capacitor. 
     Referring to FIG. 1, a single crystal silicon substrate 2 with a &lt;100&gt; crystallographic orientation, is provided. A thick field oxide (FOX) region 4 is formed to provide isolation between devices on the substrate 2. The FOX region 4 is created in a conventional manner. For example, the FOX region 4 can be formed via photolithography and dry etching steps to etch a silicon nitride-silicon dioxide composition layer. After the photoresist is removed and wet cleaned, thermal oxidation in an oxygen-steam environment is used to grow the FOX region 4 to a thickness of about 3000-8000 angstroms. 
     Next, a silicon dioxide layer 6 is created on the top surface of the substrate 2 to serve as the gate oxide for subsequently formed Metal Oxide Silicon Field Effect Transistors (MOSFETs). In one embodiment, the silicon dioxide layer 6 is formed by using an oxygen ambient, at a temperature of about 800° to 1100° C. Alternatively, the oxide layer 6 may be formed using any suitable oxide chemical compositions and procedures. In this embodiment, the thickness of the silicon dioxide layer 6 is approximately 30-200 angstroms. 
     A doped first polysilicon layer 8 is then formed over the FOX region 4 and the silicon dioxide layer 6 using a Low Pressure Chemical Vapor Deposition (LPCVD) process. In this embodiment, the first polysilicon layer 8 has a thickness of about 500-2000 angstroms. A tungsten silicide layer 10 is formed on the first polysilicon layer 8. Next, standard photolithography and etching steps are used to form a gate structure 12 and a local interconnection 14. Subsequently, active regions 16 (i.e. the source and the drain) are formed by using well known processes to implant appropriate impurities in those regions. Then a metal layer is formed on the substrate 2, A patterning and an etching process is used to etching the metal layer to form a bit line 18. 
     Turning next to FIG. 2, a first dielectric layer 18 is formed on the gate structure 12, the local interconnection 14, the metal layer 18 and the substrate 2. The first dielectric layer 20 can be formed by using suitable material such as borophosphosilicate glass (BPSG) or TEOS-oxide. The thickness of the first dielectric layer 20 is about 3000-10000 angstroms. Next, a second dielectric layer 22 is deposited on the first dielectric layer to serve as an etching barrier for subsequent process. The second dielectric layer 22 is formed of nitride. The thickness of the second dielectric layer 22 is about 300-2000 angstroms. 
     As shown in FIG. 3, a contact hole 24 is formed in the first dielectric layer 20 and second dielectric layer 22 by patterning and etching them. A first conductive layer 26 is formed over and in the contact hole 24 and on the second dielectric layer 22. The first conductive layer 26 is preferably formed using conventional LPCVD processing. The thickness of the first conductive layer 26, as measured over the second dielectric layer 22, is optimally 1000-10000 angstroms. The first conductive layer 26 is preferably chosen from doped polysilicon or in-situ doped polysilicon. 
     Turning now to FIG. 4, subsequently, a HemiSpherical Grains silicon (HSG-Si) layer 28 is formed on the first conductive layer 26 with a thickness about 500-1000 angstroms. 
     Turning next to FIG. 5, an slighty etching is used to etch the HSG-Si layer 28 to separate Si islands. The etchant of this etching to separate the HSG-Si is chosen from the group of: HBr/Cl 2  /O 2 , Cl 2 , HBr/O 2 , BCl 3  /Cl 2 , SiCl 4  /Cl 2 , SF 6 , SF 6  /Br 2 , CCl 4  /Cl 2 , CH 3  F 3  /Cl 2 . Then a spin on glass (SOG)layer 30 is formed on the HSG-Si 28 to have a thickness about 300-2000 angstroms. As seen in FIG. 6, a thermal curing treatment is performed to reflow the SOG layer 30. The temperature of the thermal treatment is about 400° C. The advantage of the SOG layer 30 is that it provides a better topography of planarization. 
     Next, as seen in FIG. 7, a dry etching is used to etch the SOG layer 30 to expose the top of the HSG-Si 28. The etchant of the etching is selected from the group of CCl 2  F 2 , CF 4 , C 2  F 6 , C 3  F 8 . Residual SOG layer 30 is left on the first conductive layer 26 after the etching. 
     As shown in FIG. 8, an etching process is performed by using the residual SOG layer 30 as a mask to etch a portion of the first conductive layer 26 and the HSG-Si 28. Of course, the HSG-Si 28 is totally removed during this etching process. The present invention uses the high etching selectivity between SOG layer 30 and polysilicon 28, 26 to create cavities in the first conductive layer 26. Any suitable etchant can be used for this etching, such as C 2  F 6 , SF 6 , CF 4  +O 2 , CF 4  +Cl 2 , CF 4  +HBr, HBr/Cl 2  /O 2 , Cl 2 , HBr/O 2 , BCl 3  /Cl 2 , SiCl 4  /Cl 2 , SF 6 , SF 6  /Br 2 , CCl 4  /Cl 2 , or CH 3  F/Cl 2 . 
     Referring to FIG. 9, the residual SOG layer 30 is removed by wet etching. In preferred embodiment, BOE or diluted HF solution is used as an etchant. A porous-Si capacitor bottom storage node is formed while the residual SOG layer 30 is stripped. A photoresist is patterned on the first conductive layer 26. Then a dry etching is used to etch the first conductive layer 26 to the surface of the nitride layer 22 which acts as an etching barrier. A dielectric film 32 is deposited along the surface of the first conductive layers 26 and the nitride layer 22. The dielectric film 32 is preferably formed of either a double-film of nitride/oxide film, a triple-film of oxide/nitride/oxide, or any other high dielectric film such as tantalum oxide(Ta 2  O 5 ), BST, PZT, PLZT. Finally, as is shown in FIG. 10, a second conductive layer 34 is deposited using a conventional LPCVD process over the dielectric film 32. The second conductive layer 34 provides a top storage electrode and is formed of doped polysilicon, in-situ doped polysilicon, aluminum, copper, tungsten or titanium. Thus, a semiconductor capacitor is formed which comprises a second conductive layer 34 as its top storage electrode, a dielectric 32, and a first conductive layer 26 as the bottom storage electrode. FIG. 11 shows the three dimension drawing of the porous-Si bottom storage node. It can be seen, a plurality of micro-hole 36 are created in the first polysilicon layer 26. 
     The present invention thus provides capacitors with an enlarged surface area. The present invention uses the high etching selectivity between SOG and polysilicon to fabricate the capacitor. Moreover, the structure increases the surface area of the capacitor. Therefore the present invention increases the performance of the capacitor. 
     As will be understood by persons skilled in the art, the foregoing preferred embodiment of the present invention is illustrative of the present invention rather than limiting the present invention. Having described the invention in connection with a preferred embodiment, modification will now suggest itself to those skilled in the art. Thus, the invention is not to be limited to this embodiment, but rather the invention is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structures. 
     While the preferred embodiment of the invention has been illustrated and described, it will be appreciated that various changes can be made therein without departing from the spirit and scope of the invention.