Abstract:
Method for effecting edge bias correction of topography-induced linewidth variations which are encountered in printed or integrated circuits on substrates or semiconductor devices for electronic packages. The method modifies data for current levels which is predicated on prior level data and models, as to the manner in which topography will affect the resist and/or antireflective coating (ARC) thicknesses, so as to improve upon linewidth (LW) control and, in general, imparting improved processing windows. The method can be implemented in the form of computer-executable instructions which are embodied in one or more program modules stored on computer-usable media.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to methods for effecting edge bias correction of topography-induced linewidth variations which are encountered in printed or integrated circuits on substrates or semiconductor devices for electronic packages. 
     In essence, during the formation of printed or integrated circuits there may be encountered undesirable topography-induced linewidth (LW) variations in view of the aspect that prior patterning levels can conceivably create topography which causes (photo) resist and/or antireflective coating (ARC) thickness variations in the level which is being currently implemented. In effect, these variations and diverse thicknesses may lead to linewidth (LW) variations in the printed circuits due to thin film interference (TFI) effects. 
     2. Discussion of the Prior Art 
     Although the technology has addressed itself to deriving different solutions which are designed for effectuating the reducing of topography-induced linewidth (LW) variations, these concepts have not always proven themselves to be entirely practical or economical in their applications in attempts to optimize LW controls. 
     a) Thus, for instance, efforts have been expended to reduce topography-induced LW variations by attempting to reduce and/or eliminate the topography. This, theoretically would be ideal, but frequently is impractical or even impossible to physically implement with currently available technology. 
     b) Furthermore, certain processing enhancements may also be employed such as: 
     i) the use of thicker ARC&#39;s which reduce the thin film interference (TFI) but which cause more problems in implementing the etching. Consequently, there is encountered a tradeoff in etch variations for TFI reductions, which is of a somewhat impractical value in nature; 
     ii) employ top ARC&#39;s, which add process costs and complexity, limit material choices, but which may still provide some undue linewidth (LW) variations. 
     iii) implement thickness optimization; however, in the event that the topography is large enough, then it becomes difficult to optimize. Moreover, even with optimization of the thickness this may cause some undue linewidth (LW) variations. 
     The present invention, in essence, is intended to solve the problems that are encountered in the current state-of-the technology, wherein prior patterning levels in the formation of printed circuits can create topographies which cause resist and antireflective coating (ARC) thickness variations in current photoresist application levels; whereby, in turn, these thickness variations lead to undesirable linewidth (LW) variations due to encountered thin film interference (TFI) effects. 
     SUMMARY OF THE INVENTION 
     Accordingly, in order to clearly and unambiguously improve upon and possibly eliminate the limitations and drawbacks which are encountered in the current state-of-the technology, the invention modifies data for current levels which is predicated on prior level data and models, as to the manner in which topography will affect the resist and antireflective coating (ARC) thicknesses, so as to improve upon linewidth (LW) control and, in general, imparting improved processing windows. 
     Pursuant to the invention, the data for the current level design data is modified to compensate for the effects of prior level topography, whereby the data modification consists of shifting edges of shapes in the data set. The amount of the shift is determined according to width or area of underlying pattern regions, or according to underlying pattern density. 
     Furthermore, in accordance with the invention the method for improving upon linewidth control may be implemented as computer-executable instructions which may be embodied in a program module or module stored on computer-useable media. A suitable computer program or collection of programs may be employed to implement the method in a variety of programming structures in data forms predicated on the information contained in the present specification. 
     Accordingly, it is an object of the present invention to improve upon topography-induced variations in linewidth (LW) in the formation of printed circuits by the expedients of modifying data for current levels based upon prior level data and models, as to the manner in which topography will affect resist and ARC thicknesses. 
     Another object of the invention is to provide a novel method of improved linewidth control and improved processing windows by employing data modification for the current level predicated on prior level data and models of topography affecting resist and ARC thicknesses. 
     Yet another object of the present invention is to provide for a method for edge bias correction of topography-induced printed circuit linewidth variations through the intermediary of modifying current level design data to compensate for the effects caused by prior level interference (TFI) effects in view of the creation of a topography leading to resist and antireflective coating (ARC) thickness variations. 
     Still another object of the present invention resides in the provision of a computer program or a collection of programs adapted to implement the inventive method in the form of computer-executable instructions, which may be tangibly embodied in a program module or module stored on computer-useable media. 
    
    
     BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS 
     The foregoing and other objects of the invention may now be more readily ascertained from the following detailed description of preferred embodiments of the invention, taken in conjunction with the accompanying drawings; in which: 
     FIG. 1 illustrates a graphical representation of linewidth (LW) plotted versus topography width; 
     FIG. 2 illustrates a graphical representation of linewidth (LW) versus topography width as divided into a various regions along the topography of a surface provided with printed circuits; 
     FIG. 3 illustrates a graphical representation of edge correction versus topography width across various regions over the extent of the topography; 
     FIG. 4 illustrates a graphical representation of the nominal to actual thicknesses plotted versus distance from the edge of a step for experimentally determined data for ARC and resist thickness as a function of distance from the edge of the topography feature; 
     FIG. 5 illustrates a breakdown of the initial data set into regions of the topography based on the width of the underlying shape; 
     FIG. 6 illustrates a more specific embodiment of the topography divided into four Regions A through D; and 
     FIG. 7 illustrates a generally diagrammatic representation of a computer system for implementing the invention in the form of computer-executable instructions. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Basically, any even relatively slight changes in the resist or ARC thicknesses can resultingly cause significant variations or changes to take place in the linewidth (LW) of the printed circuitry due to thin film interference (TFI) effects. On a planar surface, it is possible to be able to optimize the resist and ARC thickness in order to minimize TFI-induced linewidth (LW) variations. However, when there is a topography present on the surface of the wafer, there will of necessity be encountered some local variations in the resist and/or ARC thicknesses. Even relatively shallow step heights in the topography are significant, inasmuch as the TFI quarter wave is relatively small; for instance approx. 37 nm for a 248 nm exposure and 29 nm for a 193 nm exposure, by way of example. The planarization of a resist or antireflective coating (ARC) film over a step in the surface readily leads to variations in the resist or ARC thicknesses. However, since these variations in thickness are systematic, it is potentially possible to predict their effects on linewidths (LW) and thus to be able to compensate for the effects of the topography. For example, as the resist coating which is being applied to the surface planarizes a step, the resist thickness will decrease over the extent of the step. This, in turn, will produce either a decrease or increase in the linewidth (LW) depending upon the relative location of the nominal thickness within the so called swing curve. Nevertheless, this change in the linewidth (LW) can be compensated for by appropriately changing the design data so as to achieve the desired control over the precision in the production thereof. 
     Referring now in detail to the invention, and with reference to the accompanying drawings; a first example of a method employing a one-time calibration of data in order to achieve the inventive bias correction of topography-induced linewidth (LW) variations of a printed circuit comprises essentially the following steps: 
     1. One time calibration: 
     a) Determine the effect of width of topography on resist and ARC thicknesses (through simulation or experimentally). This can conceivably be an equation relating resist (and/or ARC) thickness to width of the topography, or Table 1 (as set forth hereinbelow) containing width, ARC, and resist thickness values. Equations 1 and 2 as follows, each illustrate show experimentally determined empirical fits for AR3-ARC and UV110 resist as a function of step height, h, width, W, antireflective coating ARC, and resist RES; wherein: 
     
       
           ARC= ( ARC   nom   −h )+(1+ e   (−0.8×W0.55) )× h   Equation 1 
       
     
     
       
           RES= ( RES   nom   −h )+(1+(25× W   29 ) e   (−5.5×W0.3) )× h   Equation 2 
       
     
     b) Determine effect of resist and ARC thickness variations on LW (simulation or experimental data) (i.e. Table with resist thickness, ARC thickness, and LW as the columns). 
     c) Combine a) and b) in order to obtain a correlation of topography width and LW; i.e. Table with width of topography and LW as the columns, or a graphical plot, as shown in FIG. 1 of the drawings. 
     d) Define Regions  1  through  5  by creating “buckets” vs topography width such as topography width less than 7 um=Region  1 ; 7 um to 14 um=Region  2 ; etc., as illustrated in FIG. 2 of the drawings. 
     e) Assign an edge correction value to each region by comparing average LW in each region to the desired LW. For example, when observed LW in Region  1  (from parts c and d above) is 170 nm and desired LW is 160 nm, then a −5 nm per edge correction value is assigned to Region  1 . This is illustrated in the graphical plot of FIG.  3 . The value of the correction may not match the value of the error due to non-linearity. 
     2. Break initial data set into regions ( 1  to  5 ) based on width of the underlying shape. 
     3. Apply an edge correction to each shape based on the region ( 1  to  5 ) into which it falls. 
     An alternative exemplary method of determining the effect of width of topography resist and ARC thickness it may be also determined as follows: 
     1. One time calibration: 
     a) Determine effect of width of topography on resist and ARC thicknesses (simulation or experimental). This could be an equation relating resist and (ARC) thickness to the width of the topography, or the Table containing width, ARC and resist thickness values. Equations 1 and 2, as listed hereinabove, show experimentally determined empirical fits for AR3-ARC and UV110 resist as a function of step height h, and width W; etc. 
     b) Determine effect of distance from the edge of a step on resist and ARC thickness (simulation or experimental). This could be an equation relating resist and (ARC) thickness to distance from the edge of a step, or a table containing width, ARC and resist thickness values. FIG.  4  and Table 1 shows experimentally determined data for ARC and resist thickness as a function of distance from an edge of a topography feature; 
     c) Determine effect of resist and ARC thickness variations on LW (simulation or experimental data) (i.e. Table with resist thickness, ARC thickness and LW listed as the columns); 
     d) Combine a), b) and c) to obtain a correlation of topography width, distance from an edge and LW (i.e. look up Table with topography width along one axis, distance from an edge on the other axis, and the cells of the Table containing the predicted LW. 
     e) Define regions by creating so called “buckets” vs. topography width and vs. distance from an edge e.g. Topography width of less than 0.3 um=Region 1; any region less than 0.1 um from the edge of structure which is between 0.3 and 0.5 um wide=Region  2 ; 
     f) Assign an edge correction value to each region by comparing average LW in each region to the desired LW; 
     2. Break initial data set into regions based on width of underlying shape as represented in FIGS. 5 and 6. FIG. 5 shows a topographic feature ( 101 ), and a feature crossing over it ( 201 ). In FIG. 6 the topographic feature is divided into 4 regions. 
     3. Apply an edge correction to each shape based on the region it falls in. This is illustrated in FIG. 6 with the dashed or phantom lines representing the changes required to feature  201 . 
     It is also possible to provide alternatives to the foregoing for specific applications, such as follows: 
     It may be possible to account for CMP systematic variations (e.g. for large pads dish, then substrate film thicknesses will vary. Input substrate and/or resist/ARC thicknesses, determine predicated effect on LW, and corrections may be applied accordingly). 
     Account for etch effects (e.g. with RIE (reactive ion etch) lag the step height could change as a function of width. This data could be included in the correction tables). 
     Apply corrections to account for resist variation only (e.g. for a conformal ARC). 
     Apply corrections to account for ARC variation only. 
     Account for local pattern density of underlying level, to account for more global topography effects. (e.g. divide data into grids, determine pattern density of topography in a given grid, correlate pattern density to average resist/ARC thickness, and then apply corrections to tables). 
     Apply corrections based upon area of topography features (and possibly also with regard to width). 
     Apply corrections to account for reflective notching, e.g. at a distance of “x” from a topography edge apply an edge bias “y” to the current level for a length of “z”. This correction could be further refined to also be a function of the width or spacing of the topography features. (e.g. the slope at the edge of the topography could alter the location of reflected light, and the topography slope might be a function of width or spacing). 
     The following is the tabular representation as mentioned hereinabove: 
     
       
         
               
               
               
             
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 Distance 
                   
                   
               
               
                 From edge 
                 ARC D 
                 Resist D 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 2 
                 4.1 
                 12 
               
               
                 4 
                 3.0 
                 10 
               
               
                 6 
                 2 
                 8.8 
               
               
                 8 
                 1.4 
                 7.3 
               
               
                 10 
                 1.3 
                 5.8 
               
               
                 12 
                 1.25 
                 5.1 
               
               
                 14 
                 1.2 
                 3.2 
               
               
                 16 
                 1.15 
                 2.6 
               
               
                 18 
                 1.1 
                 1.8 
               
               
                 20 
                 1.05 
                 1 
               
               
                 22 
                 1 
                 0.4 
               
               
                 24 
                 0.9 
                 0.2 
               
               
                 26 
                 0.7 
                 0 
               
               
                 28 
                 0.5 
                 0 
               
               
                 30 
                 0.3 
                 0 
               
               
                 32 
                 0 
                 0 
               
               
                   
               
             
          
         
       
     
     Pursuant to a preferred embodiment, the invention can also be implemented as computer-executable instructions which when executed perform the steps of the method as described hereinabove. The instructions are tangibly embodied in a program module or modules stored on computer-usable media. 
     Referring to FIG. 7, this shows a high-level representation of a general purpose computer system for implementing the invention in the form of computer-executable instructions, such as might be realized by a variety of known and commercially available hardware and software elements. The system comprises a memory  700  including a ROM and RAM, processor  710  and user interface  711  comprising a video display  712 , keyboard  713  and mouse  714 , whereby the various operative elements may communicate via system bus  706 . The system may further be connected to a network  717  via a network medium  718  and network interface  715 . 
     A computer program or a collection of programs comprising computer-executable instructions for performing method steps according to the present invention may be stored and transported on computer-usable media such as diskette  701 , CD-ROM  702 , magnetic tape  703  and fixed disk  704 . 
     In order to perform the steps of the method, the instructions may be retrieved from the computer-usable media  701 - 704  using their respective drives  705 - 708  into memory  700  and executed by a processor  710 . The method discloses hereinabove may find specific implementations in a variety of programming structure and data forms, which are considered to be within the abilities of a programmer of ordinary skill in the art after having reviewed the specification. 
     From the foregoing it becomes readily apparent that the inventive methods for the edge bias correction of topography-induced linewidth (LW) variations are each of a simple nature and may be readily implemented without undue difficulty and with a high degree of precision and accuracy. 
     While the invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.