Abstract:
An apparatus for supplying a load current. The apparatus comprises a first differential amplifier producing a differential output signal and an output buffer comprising a first and a second parallel emitter follower transistors each producing a current responsive to the differential output signal. A second differential amplifier responsive to the differential output signal controls current mirror masters that in turn control current source mirrors. Current supplied by each of the current sources mirrors in cooperation with the current produced by each of the first and second transistors produce the load current.

Description:
This application claims the benefit of U.S. Provisional Patent Application No. 60/616,790 filed on Oct. 6, 2004. 

   FIELD OF THE INVENTION 
   The present invention relates generally to a hard disk drive data storage system, and more particularly to an output stage of a hard disk drive preamplifier operative with the hard disk drive storage system. 
   BACKGROUND OF THE INVENTION 
   Disk drives are a cost effective data storage system for use with a computer or other data processing devices. As shown in  FIG. 1 , a disk drive  10  comprises a magnetic recording medium, in the form of a disk or platter  12  having a hub  13  and a magnetic read/write transducer  14 , commonly referred to as a read/write head. The read/write head  14  is attached to, or formed integrally with, a suspension arm  15  suspended over the disk  12  and affixed to a rotary actuator arm  16 . A structural arm  18 , fixed to a platform  20  of the disk drive  10 , is pivotably connected to the actuator arm  16  at a pivot joint  22 . A voice coil motor  24  drives the actuator arm  16  to position the head  14  over a selected position on the disk  12 . 
   As the disk  12  is rotated by a spindle motor (not shown) at an operating speed, the moving air generated by the rotating disk, in conjunction with the physical features of the suspension arm  15 , lifts the read/write head  14  away from the platter  12 , allowing the head to glide or fly on a cushion of air slightly above a surface of the disk  12 . The flying height of the read/write head over the disk surface is typically less than a micron. 
   An arm electronics module  30  may include circuits that switch the head function between read and write operations and write drivers for supplying write current to the head  14  during write operations. The write current alters magnetic domains within the disk  12  to store data thereon. The arm electronics module  30  may also include a preamplifier electrically connected to the head  14  by flexible conductive leads  32 . During read operations the preamplifier amplifies the read signals produced by the head  14  to increase the read signal amplitude prior to recovering the data bits represented by the read signal. In the write mode the preamplifier scales up the relatively low voltage levels representing the data bits to be written to the disk to a voltage range between about +/−6V and +/−10V. The preamplifier also shapes the write signal waveform to optimize the data writing process. 
   The configuration and components of the electronics module  30  may vary according to the disk drive design, as will be understood by persons familiar with such technology. Although the module  30  may be mounted anywhere in the disk drive  10 , a location proximate the head  14  minimizes signal losses and induced noise in the head signals during a read operation. A preferred mounting location for the module  30  comprises a side surface of the structural arm  18  as shown in  FIG. 1 . 
   As shown in  FIG. 2 , the disk  12  comprises a substrate  50  and a thin film  52 , disposed thereover. During write operations current through a write head  14 A alters magnetic domains of ferromagnetic material in the thin film  52  for storing the data bits as magnetic transitions. During read operations a read head  14 B senses the magnetic transitions to determine the data bits stored on the disk  12 . 
   Data storage media of alternative data storage systems comprise a floppy magnetic disk, a magnetic tape and a magneto-optic disk (not shown in the Figures) cooperating with the head  14  to read and write data to the storage media. 
   The disk drive read head  14 B comprises either a magneto-resistive (MR) sensor or an inductive sensor. The former produces a higher magnitude output signal in response to the magnetic transitions, and thus the output signal exhibits a greater signal-to-noise ratio than an output signal produced by the inductive sensor. The MR sensor is thus preferred, especially when a higher areal data storage density in the disk drive  10  is desired. 
   A DC (direct current) bias voltage of about 0.04V to 0.2V is supplied by the preamplifier to the read head terminals  54 A and  54 B via the conductive leads  32  for biasing the read head  14 B. Magnetic domains in the thin film  52  passing under the read head  14 B alter a resistance of the magneto-resistive material, imposing an AC (alternating current) component on the DC bias voltage, wherein the AC component represents the read data bits. The AC component is detected in the preamplifier, but has a relatively small magnitude (e.g., several millivolts) with respect to the DC bias voltage. 
   The output signal from the read head  14 B, representing data bits read from the disk drive  10  and having an amplitude in a range of several millivolts, is input to a signal processing stage  102  followed by an output or converter stage  104 . Typically, both the signal processing stage  102  and the output stage  104  are elements of the preamplifier. The signal processing stage amplifies the signal and supplies the read head bias voltage. The output stage  104  scales up the head signal voltage to a peak voltage value in a range of several hundred millivolts, supplying the scaled-up signal to channel circuits of a channel chip  106  through an interconnect  108 . The channel chip  106  detects the read data bits from the voltage pulses, while applying error detection and correction processes to the read data bits. 
   Desktop computers typically derive their operating power from an AC power source such as a power grid, and can therefore supply continuously high current levels up to the current capacity of the computer power supply. Although it is advantageous to limit the current drawn (power dissipated) by a desktop computer to limit heat build-up within the computer, generally the current supplied to the computer components is not constrained by the ability of the power source to supply the demanded current. 
   In contrast to a desktop computer, minimizing power dissipation is a crucial design objective for mobile and portable computing devices and data processing systems, for stored music players and for other battery-powered devices that include a mass data storage system operative with a preamplifier. Early designs of mobile computing devices mimizied power dissipation by trading power consumption with operating speed. That is, the operating speed was limited to reduce current consumption and thus extend battery life. Given the continuing demand for higher operating speeds and data rates, such a trade-off is less desirable. 
     FIG. 3  illustrates a conventional prior art converter or output stage  104  for scaling up and buffering a differential input signal to drive the interconnect  108  to the channel chip  106 . The output stage  104  comprises a differential amplifier  110  (further comprising bipolar junction transistors Q 7  and Q 6 ) and an output buffer  112  (further comprising bipolar junction transistors Q 12  and Q 9  each connected as an emitter follower). 
   The bipolar junction transistors Q 6  and Q 7  form a differential amplifier with a degeneration resistor R 20  connected between an emitter E of the bipolar junction transistor Q 6  and an emitter E of the bipolar junction transistor Q 7 . The degeneration resistor linearizes the amplification and stabilizes the gain of the differential amplifier  110 . Collector load resistors R 17  and R 19  of Q 7  and Q 6 , respectively, are connected to a supply voltage VCC. Current sources  115  and  116  supply current to the respective transistors Q 7  and Q 6   
   The emitter followers Q 12  and Q 9  of the output buffer  112  operate with a fixed bias (6 mA each in one embodiment) supplied by respective current sources  117  and  118 . The emitter followers Q 12  and Q 9  operate as approximately unity gain class-A amplifiers, i.e., current flows in the output circuit of each transistor Q 12  and Q 9  at all times. The bipolar junction transistors Q 9  and Q 12  buffer the collector load resistors R 17  and R 19  of Q 7  and Q 6 , respectively, to drive the interconnect  108  from a low impedance source, thereby maintaining a wide operating bandwidth, typically up to about 700 MHz. 
   As is known in the art, in one embodiment the current sources  115 ,  116 ,  117  and  118  comprise scaled current mirrors implemented as matched area-ratioed bipolar junction transistors and scaled emitter resistors. For exemplary current sources, see the commonly owned patent application entitled, Current Mirrors Having Fast Turn-on Time, filed on May 27, 2005, and assigned application Ser. No. 11/140,269. 
   The combination of the high data rate and a length of the interconnect  108  between the output stage  104  and the channel chip  106  (typically about two inches) requires consideration of transmission line effects on the interconnect  108 . To reduce reflections between the converter stage  104  (conventionally disposed within the preamplifier) and the separate channel chip  106 , impedance matching elements Routp  130  and Routn  132  match the preamplifier output impedance to a characteristic impedance of the interconnect  108 . In one embodiment, the impedance matching elements Routp  130  and Routn  132  are disposed internal to the preamplifier and thus are elements of the output stage  104 , with the output terminals RDP and RDN connected to the interconnect  108 . 
   An impedance matching element (also referred to as a load element) Rterm  134  (having an impedance approximately equal to the characteristic impedance of the interconnect  108 ) is located at an input side of the channel chip  106  to reduce signal reflections from the channel chip input back through the interconnect  108 . In certain applications a characteristic impedance of the interconnect  108  is about 110 ohms and the value of the element Rterm  134  is about 110 ohms. 
   The output stage  104  operates as follows. The references to more or less current in the operating description are referenced to an idle input condition where VinP−VinN=0. A differential input signal provided on input terminals VinN and VinP from the signal processing stage  102  biases the base of each bipolar junction transistor Q 6  and Q 7 . For a positive input condition VinP−VinN&gt;0 applied to the differential amplifier  110 , the bipolar junction transistor Q 6  carries more current than in the idle condition (the transistor pulls up or its operating condition moves in a direction of a saturation condition). A voltage at the collector C of Q 6  moves toward ground and drives the base B of Q 12  toward ground. This condition causes Q 12  to carry less current. The input signal supplied to the base B of the bipolar junction transistor Q 7  causes it to carry less current than in the idle condition. A voltage at the collector C of Q 7  moves toward the supply voltage VCC and drives the base of Q 9  toward VCC. Q 9  thus carries more current than in the idle condition. Since the current supplied by each of the current sources  117  and  118  is fixed, the decreased current through Q 12  and the increased current through Q 9  causes the load current ILoad through Rterm  134  to increase. In response to these current conditions, the voltage at the terminal RDP moves in a positive direction and the voltage at the terminal RDN moves in a negative direction with respect to their idle conditions, producing a more positive voltage drop across Rterm  134 . 
   For a negative input condition VinP−VinN&lt;0, the state of the transistors Q 6  and Q 7  is reversed from the positive input condition. Thus the bipolar junction transistor Q 12  carries more current and Q 9  carries less current than when in their idle condition. The voltage at the terminal RDP moves in a negative direction (i.e., lower than the RDP voltage for the positive input condition) and the voltage at the terminal RDN moves in a positive direction (greater than the RDN voltage for the positive input condition), producing a voltage drop across Rterm  134  that is less positive or lower than for the positive input condition. 
   The bias current produced by the current sources  117  and  118  is fixed (i.e., independent of any signal amplitude variations in the output stage  104 ) and the net current flowing in the bipolar junction transistors Q 9  and Q 12  is therefore fixed. 
   From  FIG. 3  it can be seen that,
 
 i   Q9   =I 118+ILoad
 
 i   Q12   =I 117−ILoad
 
where i Q9  is the current through the bipolar junction transistor Q 9 , I 118  is the current supplied by current source  118 , i Q12  is the current through the bipolar junction transistor Q 12 , I 117  is the current supplied by current source  117  and ILoad is the current through the load resistor Rterm  134 .
 
   To maintain operation of the output stage  104  in a linear flow distortion) region and maintain a desired signal bandwidth, both Q 9  and Q 12  require a minimum or overhead current of Iovrhd. Therefore it is necessary that
 
 I 117≧Iovrhd+ILoad max   (1)
 
 I 118≧Iovrhd+ILoad max   (2)
 
where ILoad max is the maximum load current generated in response to a maximum peak-to-peak input signal for VinP and VinN. Sizing the constant current sources  117  and  118  to satisfy equations (1) and (2), as disclosed in the prior art, ensures that Q 9  and Q 12  have sufficient current flow to operate in the linear region over the full differential input signal range, which is 400 mVp-p according to one application of the output stage  104 . However, sizing both of the current sources  117  and  118  to always supply the maximum current required for all input conditions results in supplying more current than may be needed.
 
   According to industry conventions, it is desired that a total harmonic distortion (THD) introduced by the output stage  104  be less than about 0.5% for a 400 mVp-p output swing at the output terminals RDN and RDP. 
   When operating in a disk drive data storage system for desktop computer with unlimited current capacity, the current sources  117  and  118  are designed to supply a constant current of about 6 mA, an amount sufficient to satisfy the maximum input signal conditions and current overhead requirements discussed above and the THD requirement. 
   For a disk drive data storage system operative with a mobile or portable computing device, typically deriving its power from an on-board battery, it is desired to improve the power efficiency of the output stage  104  to conserve battery life. However, the THD requirements must be satisfied and proper output stage performance maintained. 
   BRIEF SUMMARY OF THE INVENTION 
   According to one embodiment, the present invention comprises an apparatus for supplying a load current to a load in response to a differential input signal comprising a first and a second input signal. The apparatus comprises an output buffer for producing a first current at a first load terminal and a second current at a second load terminal, wherein the first and the second currents are functionally related to the first input signal and the second input signal, and wherein the load is connected between the first and the second load terminals, a first current source connected to the first load terminal for supplying a variable third current as a function of the differential input signal and a second current source connected to the second load terminal for supplying a variable fourth current as a function of the differential input signal, wherein the first, second third and fourth currents cooperate to determine the load current. 
   According to another embodiment, the present invention comprises a method for supplying a load current responsive to a first and a second differential input signal. The method comprises receiving the first and the second differential input signals, producing a first and a second variable current functionally related to the first and the second differential input signals, producing a third and a fourth current functionally related to the first and the second differential input signals and wherein the first variable current and the third current cooperate at a first terminal and the second variable current and the fourth current cooperate at a second terminal to produce the load current between the first and the second terminals. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention can be more easily understood and the advantages and uses thereof more readily apparent when the following detailed description of the present invention is read in conjunction with the figures wherein: 
       FIG. 1  illustrates a prior art disk drive to which the teachings of the present invention can be applied. 
       FIG. 2  is a schematic diagram of a prior art head and related components of the disk drive of  FIG. 1 . 
       FIG. 3  is a schematic diagram of a prior art output stage for use with the disk drive of  FIG. 2 . 
       FIG. 4  is a schematic diagram of an output stage of the present invention 
       FIG. 5  is a graph illustrating certain performance characteristics of the output converter of  FIG. 4  compared with the output converter of  FIG. 3 . 
     In accordance with common practice, the various described device features are not drawn to scale, but are drawn to emphasize specific features relevant to the invention. Like reference characters denote like elements throughout the figures and text. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Before describing in detail the particular method and apparatus related to an output stage of a preamplifier for a disk drive system, it should be observed that the present invention resides primarily in a novel and non-obvious combination of elements and process steps. So as not to obscure the disclosure with details that will be readily apparent to those skilled in the art, certain conventional elements and steps have been presented with lesser detail, while the drawings and the specification describe in greater detail other elements and steps pertinent to understanding the invention. 
   The following embodiments are not intended to define limits as to the structure or method of the invention, but only to provide exemplary constructions. The embodiments are permissive rather than mandatory and illustrative rather than exhaustive. Use of the present invention is not limited to an output stage of a preamplifier for a disk drive storage system and can be used in applications other than those described herein. 
   Unlike the constant current sources  117  and  118  of the prior art that supply a fixed constant current, the emitter follower current sources of the present invention are controlled in response to the instantaneous differential input signal levels at the terminals VinP and VinN. Controlling the current sources permits a reduction in the current supplied to the emitter follower bipolar junction transistors Q 12  and Q 9  in response to the input differential signals, lowering power consumption while maintaining compliance with the 0.5% THD requirement. The output stage of the present invention provides improved power efficiency compared with the output stage  104  of  FIG. 3  and is thus beneficial for use with a portable or mobile computer or data processing device operating from a battery power supply. 
   An output stage  150  of the present invention illustrated in  FIG. 4  includes the differential amplifier  110 , an amplifier  154  (a current controlling amplifier for providing control of current sources within the output stage  150 ) and an output buffer  156 . The output stage  150  is illustrated as operative with the power supply rail voltage VCC and ground. Alternatively, the output stage is operative with a high (e.g., positive) and a low (e.g., negative) power supply rail voltage, wherein the low power supply rail voltage includes a negative voltage, a positive voltage less than the high power supply rail voltage and ground. 
   The amplifier  154  comprises PMOSFETS M 5  and M 7  and a degeneration resistor  177  connected between sources S thereof, each source S is further responsive to a respective current source  172  and  170 . A node V n  (a collector C of the bipolar junction transistor Q 6 ) is connected to a gate G of the PMOSFET M 5  and to a base B of the bipolar junction transistor Q 12 . A node V p  (a collector C of the bipolar junction transistor Q 7 ) is connected to a gate G of the PMOSFET M 7  and to a base B of the bipolar junction transistor Q 9 . 
   The output buffer  156  comprises the bipolar junction transistors Q 12  and Q 9  disposed in a parallel configuration relative to the output terminals RDP and RDN. The bipolar junction transistors Q 12  and Q 9  track the collector voltages (V p  and V n ) of bipolar junction transistors Q 6  and Q 7  respectively, driving the output terminals RDP and RDN. A combination of the amplifier  154  and the output buffer  156  is referred to herein as a composite amplifier. 
   The PMOSFETS M 5  and M 7  of the amplifier  154  control current through respective current mirror master NMOSFETS M 9  and M 8  for controlling respective current source mirror NMOSFETS M 10  and M 11 . Each of the mirror NMOSFETS M 10  and M 11  supply a controllable current for determining the load current of the converter stage  150 . 
   Impedance matching termination elements Routp  158  (connected between an emitter terminal E of the bipolar junction transistor Q 9  and the RDP output terminal) and Routn  160  (connected between an emitter terminal E of the bipolar junction transistor Q 12  and the RDN output terminal) match the output stage (of the preamplifier) output impedance to the characteristic impedance of the interconnect  108 . The impedance matching element Rterm  176  (having a resistance approximately equal to the characteristic impedance of the interconnect  108 ) reduces reflections at the channel chip end of the interconnect  108 . 
   A positive differential input signal (VinP−VinN≧0) applied to the VinP and VinN input terminals (connected to the base B of the bipolar junction transistors Q 7  and Q 6 , respectively) causes the bipolar junction transistor Q 6  to carry more current and the bipolar junction transistor Q 7  to carry less current compared with an idle input condition where VinP−VinN=0. The positive differential input signal causes a voltage at the node V n  to move toward ground and a voltage at the node V p  to move toward the positive supply voltage VCC (in one embodiment VCC is about 3.3 V). These voltage shifts are tracked by the bipolar junction transistors Q 12  and Q 9 , causing the output terminals RDN and RDP to follow the input signal changes as described below. 
   The upward voltage shift (toward the positive supply voltage) at the node V p  due to the positive differential input signal increases a voltage on a gate G of the PMOSFET M 7  toward the supply voltage VCC. The downward voltage shift (toward ground) at the node Vn decreases a voltage of a gate G of the PMOSFET M 5  toward ground. Thus in response to the positive differential input signal, a larger share of the current supplied by the current sources  170  and  172  is carried by the PMOSFET M 5  and a smaller share is carried by the PMOSFET M 7  (compared to the idle condition where VinP=VinN). 
   The current supplied by the current sources  170  and  172  is divided between the PMOSFETS M 7  and M 5  in response to their respective gate voltages (where the gate voltages are responsive to the node voltages V p  and V n ), the size or area of each of each channel of the PMOSFETS M 5  and M 7  and a value of the degeneration resistor  177 . 
   With the PMOSFET M 5  carrying a larger share of the current (i M5 ) a current through the current mirror master NMOSFET M 9  and a current i M10  through the current source mirror NMOSFET M 10  is greater than the idle current (the current associated with the input condition VinP=VinN). With the PMOSFET M 7  carrying a smaller share of the current (i M7 ) a current through the current mirror master NMOSFET M 8  and a current i M11  through the current source mirror NMOSFET M 11  is less than the current associated with the idle input condition. 
   In addition to controlling the amplifier  154 , the upward voltage shift at the node V p  in response to the positive differential input signal increases a voltage on the base B of the transistor Q 9  toward the power supply voltage. Transistor action causes a voltage on an emitter E of Q 9  to also increase. As a result, the transistor Q 9  pulls up and its collector current i Q9  increases. 
   The downward voltage shift at the node Vn responsive to the positive differential input signal decreases a voltage on a base B of the transistor Q 12  toward ground potential and a voltage on the emitter E also drops. As a result the transistor&#39;s collector current i Q12  falls (the transistor is pulling down). 
   At nodes  180  and  182  the combined effect of the increased current i Q9 , the decreased current i M11 , the decreased current i Q12  and the increased current i M10  increases current ILoad through the load element Rterm  176 , increasing the voltage drop across Rterm  176 . That is the voltage at RDP increases and the voltage at RDN decreases compared to ground potential or the voltage drop across Rterm  176  increases. Thus the positive differential input signal is reflected to the output terminals RDP and RDN. However, as discussed below, under certain operating conditions and for certain values of the degeneration resistor (Rdegen)  177 , i Q9  and i Q12  do change substantially in response to the input conditions (VinP−VinN&gt;0 and VinP−VinN&lt;0) thus a majority of the load current is supplied by the current sources M 11  and M 10 , that is, currents i M11  and i M10 . 
   Similarly, for a negative differential input signal VinP−VinN&lt;0, the voltage at the node Vp is driven toward ground and the voltage at the node Vn is driven toward the supply voltage VCC. In response, the amplifier  154  reduces the current i M5  through the PMOSFET M 5 , consequently reducing the current through the NMOSFETS M 9  and M 10  (i M10 ). The amplifier  154  also increases the current i M7  through the PMOSFET M 7 , thereby increasing the current through the NMOSFETS M 8  and M 11  (i M11 ) increases. 
   Further in response to the voltage at the nodes V p  and V n , the voltage at the base B and the emitter E of the transistor Q 12  increase and the voltage at the base B and the emitter E of the transistor Q 9  decrease. The transistor Q 12  pulls up (i Q12  increases) and the transistor Q 9  pulls down (i Q9  decreases). 
   At the nodes  180  and  182 , the combined effect of the decreased current i Q9 , the increased current i M11 , the increased current i Q12  and the decreased current i M10  causes the current ILoad through the load element Rterm  176  to reverse direction compared with the positive differential input signal. The current reversal through the load Rterm  176  reverses the voltage drop across Rterm  176 . 
   The output buffer  156  draws less current from the power supply than the prior art output buffer  112  of  FIG. 3  because the current through each of the current source mirror NMOSFETS M 10  and M 11  changes in response to the input signal. That is, when he current i M11  increases the current i M10  decreases, and vice versa. Whereas the current sources  117  and  118  of the prior art provide a fixed current to supply the current required by a maximum swing of the input signal voltage. 
   To further illustrate operation of the composite amplifier (i.e., the amplifier  154  and the output buffer  156 ) in more detail, a small signal analysis of the combined operation of the amplifier  154  and the output buffer  156  is presented below. 
   The small signal currents through M 5  (i M5 ), M 7  (i M7 ) and Rdegen  177  are give by: 
   
     
       
         
           
             
               
                 
                   i 
                   
                     M 
                     ⁢ 
                     
                         
                     
                     ⁢ 
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                 = 
                 
                   
                     
                       V 
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                     - 
                     
                       V 
                       N 
                     
                   
                   
                     
                       
                         1 
                         / 
                         gm 
                       
                       ⁢ 
                       
                           
                       
                       ⁢ 
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                     + 
                     Rdegen 
                     + 
                     
                       
                         1 
                         / 
                         gm 
                       
                       ⁢ 
                       
                           
                       
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                       7 
                     
                   
                 
               
             
             
               
                 ( 
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               and 
             
             
               
                   
               
             
           
           
             
               
                 
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                     ⁢ 
                     
                         
                     
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                         ⁢ 
                         
                             
                         
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                 ( 
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   The current mirror master M 9  and the current source mirror M 10  mirror and scale i M5  by 1/K (i.e., M 9 =K×M 10  W/L) and the current mirror master M 8  and current source mirror M 11  mirror and scale i M7  by 1/K (i.e., M 8 =K×M 11  W/L). 
   Now analyzing the output stage  156 , the current through the bipolar junction transistor Q 9  is 
                   i     Q   ⁢           ⁢   9       =       i     M   ⁢           ⁢   11       +         V   180     -     V   182         Routp   +   Rterm   +   Routn                 (   5   )               
and the current through Q 12  is
 
                     i     Q   ⁢           ⁢   12       =       i     M   ⁢           ⁢   10       -         V   180     -     V   182         Routp   +   Rterm   +   Routn           ,           (   6   )               
where V 180  and V 182  represent the voltage at the nodes  180  and  182 , respectively.
 
   Substituting for M 10  and i M11  from equations (3) and (4) into equations (5) and (6) after scaling by 1/K, 
   
     
       
         
           
             
               
                 
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   The intent of the output stage is to drive the nodes  180  and  182  to closely follow the changes in nodes V P  and V N . Thus the above equations are simplified by replacing (V 180 −V 182 ) with (V p −V n ) 
   
     
       
         
           
             
               
                 
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               and 
             
             
               
                   
               
             
           
           
             
               
                 
                   i 
                   
                     Q 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     12 
                   
                 
                 ≈ 
                 
                   
                     
                       1 
                       K 
                     
                     ⁢ 
                     
                       ( 
                       
                         
                           
                             V 
                             P 
                           
                           - 
                           
                             V 
                             N 
                           
                         
                         
                           
                             
                               1 
                               / 
                               gm 
                             
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             5 
                           
                           + 
                           Rdegen 
                           + 
                           
                             
                               1 
                               / 
                               gm 
                             
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             7 
                           
                         
                       
                       ) 
                     
                   
                   - 
                   
                     
                       
                         
                           V 
                           P 
                         
                         - 
                         
                           V 
                           N 
                         
                       
                       
                         Routp 
                         + 
                         Rterm 
                         + 
                         Routn 
                       
                     
                     . 
                   
                 
               
             
             
               
                 ( 
                 8 
                 ) 
               
             
           
         
       
     
   
   The amplifier  154  provides substantially all the small signal current to the load Rterm  176  (via the current mirror masters M 8  and M 9  and the current source mirrors M 11  and M 10 ) if i Q9  and i Q12  are zero. This condition is met when from equations (7) and (8),
 
 K (1/ gm 5+R deg en+1 /gm 7)=Routp+Rterm+Routn   (9).
 
   With the condition of equation (9) satisfied, the bipolar junction transistors Q 9  and Q 12  provide the dc bias current to the current source mirrors M 10  and M 11  and also provide current to correct for any mis-tracking between V P −V N  and V 180 −V 182 . 
   For a specific implementation of the converter stage  150  in a hard disk drive data storage system, the interconnect  108  is designed to exhibit a specific characteristic impedance to match the converter stage output and the channel chip input. The preamp output impedance (i.e., the output impedance of the converter stage  150 , which is conventionally the output stage of the preamplifier) and load termination resistor Rterm  176  are set approximately equal to that characteristic impedance value, that is,
 
Routp+Routn≈characteristic impedance of the interconnect 108≈Rterm   (10).
 
   The scale factor K in the equations above trades signal bandwidth for power conservation of the output stage  150 . Using simulations, the inventor has determined that in one embodiment a value of K≈¼ appropriately balances power consumption and bandwidth, i.e., a conventional 700 MHz bandwidth specification is satisfied. 
   Thus for K=¼ and knowing the size for each of the PMOSFETS M 5  and M 7  (the MOSFET size determines the transconductance values gm5 and gm7), a specific value for Rdegen can be determined. For K=¼ and substituting the results from equation (9) into equation (10), reduces equation (10) to
 
(1/ gm 5)+(1/ gm 7)+Rdegen=4×2(Rterm)=8×Rterm.   (11)
 
   The values for gm5 and gm7 can be determined from the fabrication technology employed to implement the amplifier  154 . Rterm depends on the characteristic impedance of the interconnect  108  and the signal bandwidth requirements of the target application. In one implementation, Rterm=110 ohms, 1/gm5 and 1/gm7 are each approximately 230 ohms. However, in this implementation the sum (1/gm5)+(1/gm7)+Rdegen was set to approximately 990 ohms (larger than the optimum value of 8×110 ohms=880 ohms) to improve output stage linearity over fabrication process comers. Therefore Rdegen=530 ohms for this implementation. 
   Increasing Rdegen above this value reduces the portion of the current through the NMOSFETS M 10  and M 11  that is controlled by the input signal. Reducing Rdegen below this value results in excessive variation of the current supplied by the current source mirror NMOSFETS M 10  and M 11 , which must be compensated by increasing the currents supplied by the bipolar junction transistors Q 9  and Q 12 . 
   If K is increased to a value closer to one, the bandwidth of the amplifier  154  increases at the expense of requiring more supply current, i.e., increasing power consumption for the output or converter stage  150 . Setting K less than ¼ reduces the bandwidth of amplifier  154  significantly due to the gate capacitance of the NMOSFETS M 10  and M 11  for the fabrication technology employed in one implementation. 
   To compare power consumption of the output stage of the present invention and the output stage of the prior art, the total supply current for amplifier  154  and the output buffer  156  is
 
Itotal 154+156 =2(1 +K )×Iidle   (12)
 
where Iidle is the current through the NMOSFETS M 10  or M 11  when VinP−VinN=0. The total supply current for the prior art output buffer  112  of  FIG. 3  is
 
Itotal 112 =2× I 117   (6)
 
where I 117  is the current supplied by the current source  117  in  FIG. 3 .
 
   Through simulations, the inventor has determined that I 117 =6 mA to satisfy the 0.5% THD specification when driving Rterm=110 ohms with a 400 mVp-p swing for the differential input signal. The converter stage  150  of the present invention satisfies the THD specification for Rterm=110 ohms and a 400 mVp-p input signal swing when Iidle=3 mA. Thus from equations (5) and (6), the converter stage  150  requires a total supply current of 7.5 mA compared with 12 mA required for the prior art output buffer  112 . 
   The output stage  150  of the present invention reduces the emitter current for each of the bipolar junction transistors Q 12  and Q 9  to about 3 mA each while meeting the 0.5% THD objective.  FIG. 5  compares the output spectrum of the prior art output stage  104  of  FIG. 3  with the composite amplifier output stage  150  of  FIG. 4 , when both are biased with 3 mA dc through each of the bipolar junction transistors Q 12  and Q 9  and for an input signal of 400 mV peak-to-peak at 30 MHz. The output stage  104  does not satisfy the 0.5% THD objective. The output stage  150  satisfies the objective by more than about 10 dB. 
   In other embodiments, one or more of the MOSFETS and bipolar junction transistors as described herein is replaced by an opposite polarity MOSFET or bipolar junction transistor, and a MOSFET can be replaced by a bipolar junction transistor and vice versa. The associated gate drive signals and power supply voltages are modified to accommodate the doping characteristics of the opposite polarity MOSFET or bipolar junction transistor, while providing the functionality of the present invention. Further, throughout the description of the present invention, the phrase “high” signal value means a “true” or an “asserted” state. Those skilled in the art recognize that other signal values can also be associated with a “true” or an “asserted” logic state with a corresponding change in the device responsive to the logic state. 
   While the present invention has been described with reference to preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalent elements may be substituted for the elements thereof without departing from the scope of the invention. The scope of the present invention further includes any combination of elements from the various embodiments set forth herein. In addition, modifications may be made to adapt a particular situation to the teachings of the present invention without departing from its essential scope. Therefore, it is intended that the invention not be limited to the particular embodiments disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.