Abstract:
The invention relates generally to a multi-chip package (MCP) memory device, and more particularly, but without limitation, to a MCP memory device having a reduced size. In one embodiment, the MCP memory device includes: a transfer memory chip; and a plurality of memory chips coupled to the transfer memory chip, each of the plurality of memory chips including an internal voltage generating circuit, the transfer memory chip configured to receive a plurality of command signals from outside the MCP memory device, the transfer memory chip further configured to output a plurality of control signals to the plurality of memory chips based on the plurality of command signals. Embodiments of the invention also relate to a method of controlling an internal voltage of the MCP memory device.

Description:
CROSS-REFERENCE TO RELATED PATENT APPLICATION 
       [0001]    This application claims the benefit of Korean Patent Application No. 10-2007-0114292, filed on Nov. 9, 2007, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. 
       SUMMARY OF THE INVENTION 
       [0002]    The invention relates generally to a multi-chip package (MCP) memory device, and more particularly, but without limitation, to a MCP memory device having a reduced size. Embodiments of the invention also relate to a method of controlling an internal voltage of the MCP memory device. 
         [0003]    According to an aspect of the invention, the MCP memory device includes: a transfer memory chip; and a plurality of memory chips coupled to the transfer memory chip, each of the plurality of memory chips including an internal voltage generating circuit, the transfer memory chip configured to receive a plurality of command signals from outside the MCP memory device, the transfer memory chip further configured to output a plurality of control signals to the plurality of memory chips based on the plurality of command signals. 
         [0004]    According to another aspect of the invention, the method includes: receiving a plurality of command signals in the transfer memory chip, the plurality of command signals originating outside the MCP memory device; outputting a plurality of control signals from the transfer memory chip to the plurality of memory chips based on the received plurality of command signals; in each of the plurality of memory chips, selecting a corresponding one of the plurality of control signals to produce a selected control signal; and in each of the plurality of memory chips, controlling a corresponding one of the plurality of memory chip voltages based on the selected control signal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]    The above and other features and advantages of the invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which: 
           [0006]      FIG. 1  is a cross-sectional view and schematic diagram of a multi-chip package (MCP) memory device according to an embodiment of the invention; 
           [0007]      FIG. 2  is a cross-sectional view and schematic diagram of a multi-chip package (MCP) memory device including circuit diagrams of the internal voltage generating circuits of  FIG. 1 ; and 
           [0008]      FIG. 3  is a flow diagram of a method for controlling an internal voltage of the multi-chip package (MCP) memory device, according to an embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0009]    Hereinafter, the invention will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. Like reference numerals in the drawings denote like elements. 
         [0010]      FIG. 1  is a cross-sectional view and schematic diagram of a multi-chip package (MCP) memory device  100  according to an embodiment of the present invention. Referring to  FIG. 1 , a MCP memory device  100  includes a transfer memory chip ME_T, a first memory chip ME_ 1  and a second memory chip ME_ 2 . The transfer memory chip ME_T transfers command signals received from outside the MCP memory device  100  to the first memory chip ME_ 1  and a second memory chip ME_ 2 . The transfer memory chip ME_T may also transfer data of the first memory chip ME_ 1  and/or the second memory chip ME_ 2  to outside the MCP memory device  100 . The transfer memory chip ME_T may be an interface chip mounted on a printed circuit board (PCB). 
         [0011]    The first memory chip ME_ 1  and the second memory chip ME_ 2  may be stacked on the transfer memory chip ME_T. That is, the first memory chip ME_ 1  may be mounted onto the transfer memory chip ME_T, and the second memory chip ME_ 2  may be mounted onto the first memory chip ME_ 1 . The memory chips ME_ 1  and ME_ 2  are configured to support data reads and writes. 
         [0012]    Operations of the multi-chip package memory  100  will now be described with reference to generating an internal voltage. 
         [0013]    The transfer memory chip ME_T is configured to receive signals from outside the MCP memory device  100 . Such signals may include commands CMD. Hereinafter, commands for the first memory chip ME_ 1  are referred to as CMD_ 1  and commands for the second memory chip ME_ 2  are referred to as CMD_ 2 . The transfer memory chip ME_T may include control circuits  110 _ 1  and  110 _ 2 . The control circuit  110 _ 1  outputs a first control signal CON_ 1  to control a first internal voltage (not shown in  FIG. 1 ) that is provided to the first memory chip ME_ 1 . In addition, the control circuit  110 _ 2  outputs a second control signal CON_ 2  to control a second internal voltage (not shown in  FIG. 1 ) that is provided to the second memory chip ME_ 2 . 
         [0014]    Although not shown in  FIG. 1 , each of the control circuits  110 _ 1  and  110 _ 2  may include a command decoder and a logic device. Each of the command decoders is configured to decode the received command (CMD_ 1  or CMD_ 2 ). Each of the logic devices output a control signal (CON_ 1  or CON_ 2 ) in response to the decoded command. 
         [0015]    The first control signal CON_ 1  or the second control signal CON_ 2  may be transferred from the transfer memory chip ME_T to the first memory chip ME_ 1  or the second memory chip ME_ 2  using a through one or more through silicon vias (TSVs). Each of the TSVs may be a through-hole via. 
         [0016]    The first memory chip ME_ 1  may include an internal voltage generating circuit  130 _ 1 , a multiplexer (mux) MUX_ 1 , and a chip identifier (CHIP_ID)  150 _ 1 . The mux MUX_ 1  transfers the first control signal CON_ 1  to the internal voltage generating circuit  130 _ 1  in response to the CHIP_ID  150 _ 1 . The internal voltage generating circuit  130 _ 1  generates and outputs the first internal voltage (not shown) that is provided to the first memory chip ME_ 1  in response to the first control signal CON_ 1 . 
         [0017]    The second memory chip ME_ 2  operates similarly to the first memory chip ME_ 1 . The second memory chip ME_ 2  may include an internal voltage generating circuit  130 _ 2 , a mux MUX_ 2 , and a CHIP_ID  150 _ 2 . The mux MUX_ 2  transfers the second control signal CON_ 2  to the internal voltage generating circuit  130 _ 2  in response to the CHIP_ID  150 _ 2 . The internal voltage generating circuit  130 _ 2  generates and outputs the second internal voltage (not shown) that is provided to the second memory chip ME_ 2  in response to the second control signal CON_ 2 . 
         [0018]    Variations to the MCP memory device illustrated in  FIG. 1  are possible. For instance, instead of a PCB, the MCP substrate could be or include, for example, ceramic, silicon, sapphire, or other suitable material. The ceramic, silicon, or sapphire substrate could include one or more layers of copper or other electrically-conductive traces, as needed for signal and power distribution. In alternative embodiments of the invention, more than two memory chips may be stacked onto the transfer memory chip ME_T. Moreover, in alternative embodiments, the first memory chip ME_ 1  and the second memory chip ME_ 2  may be mounted directly to the transfer memory chip ME_T. Furthermore, the first memory chip ME_ 1  and the second memory chip ME_ 2  could be mounted directly to the PCB or other substrate. 
         [0019]      FIG. 2  is a cross-sectional view and schematic diagram of a multi-chip package (MCP) memory device  200  including circuit diagrams for an embodiment of the internal voltage generating circuits  130 _ 1  and  130 _ 2  shown in  FIG. 1 . 
         [0020]    In  FIG. 2 , a control circuit  110 _ 1  of a transfer memory chip ME_T outputs a first control signal CON_ 1 , and a control circuit  110 _ 2  outputs a second control signal CON_ 2 . 
         [0021]    An internal voltage generating circuit  130 _ 1  of the first memory chip ME_ 1  may include a reference voltage generating unit  210 _ 1  and an internal voltage controlling unit  250 _ 1 . The reference voltage generating unit  210 _ 1  is configured to output a first reference voltage Vref_ 1  to the voltage controlling unit  250 _ 1 . The reference voltage generating unit  210 _ 1  generates the first reference voltage Vref_ 1  by dividing the potential difference between a power supply voltage VDD and a ground voltage. Accordingly, the reference voltage generating unit  210 _ 1  may include resistors R 1 , R 2 , and R 3  coupled in series between VDD and GND. In the illustrated embodiment, a fuse F 1  is also coupled in parallel with resistor R 1  so that the value of the first reference voltage Vref_ 1  can be adjusted according to the state of the fuse F 1 . 
         [0022]    The internal voltage controlling unit  250 _ 1  controls the voltage level of the first internal voltage VINTA_ 1  in response to the first reference voltage Vref_ 1 , the first control signal CON_ 1 , and a first internal voltage feedback signal VINTA_ 1 . The internal voltage controlling unit  250 _ 1  may include a comparator COMP_ 1 , a current sink unit  253 _ 1 , and an internal voltage generating unit  255 _ 1 . The comparator COMP_ 1  compares the first reference voltage Vref_ 1  and the first internal voltage feedback signal VINTA_ 1  and outputs a comparison signal. The current sink unit  253 _ 1  controls a driving voltage of the comparator COMP_ 1  in response to the first control signal CON_ 1 . The current sink unit  253 _ 1  may be a transistor (as shown). The driving voltage of the comparator COMP_ 1  can be controlled since a current flowing through the transistor is changed according to the voltage level of the first control signal CON_ 1 . The internal voltage generating unit  255 _ 1  generates and outputs the first internal voltage VINTA_ 1  in response to the comparison signal output from the comparator COMP_ 1 . 
         [0023]    The internal voltage generating circuit  130 _ 2  is substantially the same as the internal voltage generating circuit  130 _ 1 . The internal voltage generating circuit  130 _ 2  may include a reference voltage generating unit  210 _ 2  and an internal voltage controlling unit  250 _ 2 . The reference voltage generating unit  210 _ 2  outputs a second reference voltage Vref_ 2  to the internal voltage controlling unit  250 _ 2 . The reference voltage generating unit  210 _ 2  generates the second reference voltage Vref_ 2  by dividing a potential difference between the power supply voltage VDD and a ground voltage. The reference voltage generating unit  210 _ 2  may include multiple resistors R 4 , R 5 , and R 6  coupled in series between VDD and the ground voltage. In the illustrated embodiment, a fuse F 2  is coupled in parallel with resistor R 4  so that the value of the second reference voltage Vref_ 2  can be adjusted according to the state of the fuse F 2 . 
         [0024]    The internal voltage controlling unit  250 _ 2  controls the voltage level of the second internal voltage VINTA_ 2  in response to the second reference voltage Vref_ 2 , the second control signal CON_ 2  and a second internal voltage feedback signal VINTA_ 2 . The internal voltage controlling unit  250 _ 2  may include a comparator COMP_ 2 , a current sink unit  253 _ 2  and an internal voltage generating unit  255 _ 2 . The comparator COMP_ 2  compares the second reference voltage Vref_ 2  and the second internal voltage feedback signal VINTA_ 2  and outputs a comparison signal. The current sink unit  253 _ 2  controls driving voltage of the comparator COMP_ 2  in response to the second control signal CON_ 2 . The internal voltage generating unit  255 _ 2  generates and outputs the second internal voltage VINTA_ 2  in response to the comparison signal. 
         [0025]    The configuration illustrated in  FIG. 2  is an exemplary embodiment for controlling voltages output from the internal voltage generating circuits  130 _ 1  and  130 _ 2 . However, alternative configurations for the internal voltage generating circuits  130 _ 1  and  130 _ 2  are also possible. For instance, in one respect, other resistor and fuse configurations are possible to implement the voltage-divider function performed by the reference voltage generating units  210 _ 1  and  210 _ 2 . 
         [0026]      FIG. 3  is a flow diagram of a method for controlling an internal voltage of a multi-chip package (MCP) memory device, according to an embodiment of the invention. Although the method in  FIG. 3  is described below with reference to the MCP memory devices in  FIGS. 1 and 2 , the method could also be applied to other memory device configurations. 
         [0027]    Referring to  FIG. 3 , a transfer memory chip outputs 1 st  to n th  signals in response to received command signals (S 310 ). For instance, a transfer memory chip ME_T outputs a first control signal CON_ 1  and a second control signal CON_ 2  in response to received command signals CMD_ 1  and CMD_ 2 , respectively. 
         [0028]    Next, a k th  control signal is transferred to a k th  memory chip (S 320 ). For example, the mux MUX_ 1  of the first memory chip ME_ 1  selects and outputs the first control signal CON_ 1  to the internal voltage generating circuit  130 _ 1 . Likewise, the mux MUX_ 2  of the second memory chip ME_ 2  selects and outputs the second control signal CON_ 2  to the internal voltage generating circuit  130 _ 2 . 
         [0029]    Finally, an internal voltage provided to the kth memory chip is controlled by the kth control signal (S 330 ). For instance, the internal voltage generating circuit  130 _ 1  controls the first internal voltage VINTA_ 1  provided to the first memory chip ME_ 1  in response to the first control signal CON_ 1 . Similarly, the internal voltage generating circuit  130 _ 2  controls the second internal voltage VINTA_ 2  provided to the second memory chip ME_ 2  in response to the second control signal CON_ 2 . 
         [0030]    In one embodiment of step S 330 , the internal voltage generating circuit  130 _ 1  generates a first reference voltage Vref_ 1  to which the first internal voltage VINTA_ 1  of the first memory chip ME_ 1  is referenced, and controls the voltage level of the first internal voltage VINTA_ 1  in response to the first reference voltage Vref_ 1 , the first control signal CON_ 1  and a first internal voltage feedback signal VINTA_ 1 . In addition, the internal voltage generating circuit  130 _ 2  generates a second reference voltage Vref_ 2  to which the second internal voltage VINTA_ 2  of the second memory chip ME_ 2  is referenced, and controls the voltage level of the second internal voltage VINTA_ 2  in response to the second reference voltage Vref_ 2 , the second control signal CON_ 2  and a second internal voltage feedback signal VINTA_ 2 . 
         [0031]      FIGS. 1 and 2  describe a multi-chip package (MCP) memory device that includes a transfer memory chip ME_T and two memory chips (ME_ 1  and ME_ 2 ) stacked thereon. In alternative embodiments, the transfer memory chip ME_T can generate and output n control signals when n memory chips are stacked on the transfer memory chip ME_T, wherein n is a natural number as described above. 
         [0032]    A consequence of embodiments of the invention is that the size of memory chips in a MCP memory device can be reduced. More specifically, the size of the stacked memory chips can be reduced by building a part of an internal voltage generating circuit in a transfer memory chip rather than in each of the memory chips. This configuration also simplifies the manufacturing process for the memory chips and the MCP memory device. 
         [0033]    While the invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the following claims.