Abstract:
A pseudo differential circuit is a circuit system taking the advantages of both a CMOS circuit and a differential circuit. However, when process variability and the like are taken into account, a cross point of positive and negative outputs is not constant, thereby increasing a variation in duty of an output waveform. A semiconductor circuit according to the present invention includes: a first transistor being of a first conductivity type, coupled between a first power supply and an output terminal, and applied with an input signal; a second transistor being of a second conductivity type and coupled between a second power supply and the output terminal; a third transistor being of the second conductivity type and coupled between the first power supply and the output terminal; and a fourth transistor being of the first conductivity type and coupled between the second power supply and the output terminal.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to an output buffer, and more particularly, to an output buffer for compensating a deviation caused by process variability. 
         [0003]    2. Description of the Related Art 
         [0004]    An output buffer including a CMOS circuit is used for a semiconductor circuit.  FIG. 21  is a circuit diagram showing a generally-known output buffer. The output buffer shown in  FIG. 21  is a buffer for inverting and out putting a signal applied to an input terminal. When an intermediate potential VDD/2 between a power supply potential (VDD) and a ground potential (VSS) is input to the input terminal of the output buffer, it is preferable to output the potential VDD/2 from an output terminal thereof. A technology of stabilizing the potential at the output stage is described in, for example, JP 2006-245828 A. 
         [0005]    However, in an output buffer circuit  11  where a CMOS circuit is included as shown in  FIG. 21 , when a PMOS transistor and an NMOS transistor are formed, there exists process variability. As a result, when the characteristics of the respective transistors deviates from design values, an output voltage may deviate from VDD/2 even if the VDD/2 is input as an input voltage. Therefore, there is the case where the output buffer circuit  11  does not act as an output buffer which performs an accurate operation. 
         [0006]    The output buffer circuit  11  according to the conventional technology includes an input terminal  11  to which an input signal IN is input, an n-type MOS transistor MN 1  for generating an inverted logic of the input signal IN, a p-type MOS transistor MP 1  serving as a load for the MOS transistor MN 1 , and an output terminal  2  from which an output signal OUTB is output. 
         [0007]    The sizes of the MOS transistors MP 1  and MN 1  of the circuit as shown in  FIG. 21  are generally determined such that, as an operating point (point at which the middle of the amplitude of a signal output to the output terminal  2  relative to a voltage input to the input terminal  1  is equal to VDD/2), a voltage VOUTB output to the output terminal  2  becomes VDD/2 when a voltage VIN input to the input terminal  1  is VDD/2. 
         [0008]    However, a semiconductor circuit manufacturing process size has been reduced in recent years, so variations in current gain (β) value and threshold voltage (Vth) value in each of the n-type MOS transistor and the p-type MOS transistor are caused by the process variability as described above. Therefore, even when the semiconductor circuit is formed based on values obtained by theoretical calculation, there is a difference from expected transistor capability, so a predetermined circuit output is not obtained. 
         [0009]    Here, a variation in transistor capability being caused by the variability of the manufacturing process (process variability) is expressed as “n-type MOS transistor capability/p-type MOS transistor capability.” For example, when the process variability is “large/small,” a current gain βN and a threshold voltage VthN of the n-type MOS transistor and a current gain βP and a threshold voltage VthP of the p-type MOS transistor deviate from expected values. Therefore, the operating point of the voltage VOUTB decreases in the case where the voltage VIN is VDD/2. The operating waveforms at this time are shown in  FIGS. 22A and 22B . On the other hand, even when the process variability is “small/large,” the current gain PN and the threshold voltage VthN of the n-type MOS transistor and the current gain βP and the threshold voltage VthP of the p-type MOS transistor deviate from the expected values. Therefore, the operating point of the voltage VOUTB increases in the case where the voltage VIN is VDD/2. The operating waveforms at this time are shown in  FIGS. 23A and 23B . 
         [0010]    As described above, there is the case where the theoretical output corresponding to the input is not obtained in the conventional output buffer having the CMOS structure because of, for example, the process variability. 
       SUMMARY 
       [0011]    In one embodiment, a semiconductor circuit includes: a buffer configured to allow a first current to flow to a node, wherein the buffer comprises a first plurality of transistors configured to allow the first current to leak in response to product variability in transistor characteristics at an operating point; and a compensating circuit configured to enable a second current to flow to the node to compensate for the first current, wherein the compensating circuit comprises a second plurality of transistors generating the second current in response to product variability in transistor characteristics at the operating point. 
         [0012]    According to the semiconductor circuit of the above embodiments, an operating current deviation between the first transistor and the second transistor being caused by the variability of a manufacturing process is corrected by operating currents of the third transistor and the fourth transistor, so an operating point deviation of an output signal can be compensated. 
         [0013]    According to the semiconductor circuit of the above embodiments, a deviation of an output from an input being caused by process variability of the semiconductor circuit can be compensated. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]    In the accompanying drawings: 
           [0015]      FIG. 1  shows an example of a structure of a buffer circuit according to Embodiment 1 of the present invention; 
           [0016]      FIG. 2  shows examples of variations in respective MOS transistor capabilities which are caused by the variability of manufacturing process; 
           [0017]      FIGS. 3A and 3B  show examples of operating waveforms of the buffer circuit according to Embodiment 1 of the present invention; 
           [0018]      FIG. 4  shows an example of another structure of the buffer circuit according to Embodiment 1 of the present invention; 
           [0019]      FIG. 5  shows an example of a structure a subsequent-stage circuit of a buffer circuit according to a conventional technique; 
           [0020]      FIGS. 6A and 6B  show examples of operating waveforms of the circuit of  FIG. 5 ; 
           [0021]      FIG. 7  shows an example of a structure of a pseudo differential buffer circuit according to Embodiment 2 of the present invention; 
           [0022]      FIGS. 8A and 8B  show examples of operating waveforms of the pseudo differential buffer circuit according to Embodiment 2 of the present invention; 
           [0023]      FIG. 9  shows an example of a structure of a pseudo differential buffer circuit according to the conventional technique; 
           [0024]      FIGS. 10A and 10B  show examples of operating waveforms in the case where process variability on the pseudo differential buffer circuit according to the conventional technique corresponds to a “large/small” condition; 
           [0025]      FIGS. 11A and 11B  show results obtained by simulation of operating waveforms in the case where process variability on the pseudo differential buffer circuit according to the conventional technique corresponds to the “large/small” condition; 
           [0026]      FIGS. 12A and 12B  show examples of operating waveforms in the case where process variability on the pseudo differential buffer circuit according to the conventional technique corresponds to a “small/large” condition; 
           [0027]      FIG. 13  shows an example of a structure of a subsequent circuit of the pseudo differential circuit according to the conventional technique as shown in  FIG. 9 ; 
           [0028]      FIGS. 14A and 14B  show examples of operating waveforms of the circuit of  FIG. 13 ; 
           [0029]      FIG. 15  shows an example of another structure of the pseudo differential buffer circuit according to Embodiment 2 of the present invention; 
           [0030]      FIG. 16  shows an example of a structure of a pseudo differential buffer circuit according to Embodiment 3 of the present invention; 
           [0031]      FIG. 17  shows an example of another structure of the pseudo differential buffer circuit according to Embodiment 3 of the present invention; 
           [0032]      FIG. 18  shows an example of another structure of the pseudo differential buffer circuit according to Embodiment 3 of the present invention; 
           [0033]      FIG. 19  shows an example of another structure of the pseudo differential buffer circuit according to Embodiment 3 of the present invention; 
           [0034]      FIG. 20  shows an example of a structure of a pseudo differential buffer circuit according to another embodiment of the present invention; 
           [0035]      FIG. 21  shows an example of a structure of the buffer circuit according to the conventional technique; 
           [0036]      FIGS. 22A and 22B  show examples of operating waveforms in the case where process variability on the buffer circuit according to the conventional technique corresponds to the “large/small” condition; and 
           [0037]      FIGS. 23A and 23B  show examples of operating waveforms in the case where the process variability on the buffer circuit according to the conventional technique corresponds to the “small/large” condition. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Embodiment 1 of the Present Invention 
       [0038]    Hereinafter, a specific example of a semiconductor circuit according to Embodiment 1 of the present invention will be described in detail with reference to the attached drawings. In Embodiment 1, the present invention is applied to a buffer circuit (one side of pseudo differential buffer circuit). 
         [0039]      FIG. 1  shows an example of a structure of a buffer circuit according to Embodiment 1 of the present invention. Of reference symbols shown in  FIG. 1 , elements expressed by the same reference symbols as those shown in  FIG. 21  are identical or similar to elements shown in  FIG. 21 . Embodiment 1 is different from the conventional technique in that the buffer circuit further includes an n-type MOS transistor MN 3  and a p-type MOS transistor MP 3 . 
         [0040]    A buffer circuit  101  includes an input terminal  1  to which an input signal IN is input, an n-type MOS transistor MN 1  for generating an inverted logic of the input signal, a p-type MOS transistor MP 1  serving as a load for the MOS transistor MN 1 , and an output terminal  2  from which an output signal OUTB being the inverted logic of the input signal is output. The buffer circuit  101  further includes the n-type MOS transistor MN 3  and the p-type MOS transistor MP 3  which are used to compensate for a variation in rise time of the output signal OUTB. 
         [0041]    The MOS transistor MN 1  includes a gate coupled to the input terminal  1 , a drain coupled to the output terminal  2 , and a source coupled to a low-potential side power supply potential VSS. The MOS transistor MP 1  includes a gate coupled to the low-potential side power supply potential VSS, a drain coupled to the output terminal  2 , and a source coupled to a high-potential side power supply potential VDD. The MOS transistor MN 3  includes a source coupled to the output terminal  2  and a drain and a gate which are coupled to the high-potential side power supply potential VDD. The MOS transistor MP 3  includes a source coupled to the output terminal  2 , and a drain and a gate which are coupled to the low-potential side power supply potential VSS. Assume that a voltage input to the input terminal  1  is expressed by VIN and a voltage output to the output terminal  2  is expressed by VOUTB. 
         [0042]    Hereinafter, a method of determining transistor sizes of the semiconductor circuit according to Embodiment 1 of the present invention will be described. Assume that a gate width of an n-type MOS transistor is expressed by WMN 1 , a gate width of a p-type MOS transistor is expressed by WMP 1 , a gate length of the n-type MOS transistor is expressed by LMN 1 , a gate length of the p-type MOS transistor is expressed by LMP 1 , a product of a carrier mobility and a gate oxide film capacitance in the n-type MOS transistor is expressed by βN, a product of a carrier mobility and a gate oxide film capacitance in the p-type MOS transistor is expressed by βP, a gate-source voltage of the n-type MOS transistor is expressed by VGSMN 1 , a gate-source voltage of the p-type MOS transistor is expressed by VGSMP 1 , a threshold voltage of the n-type MOS transistor is expressed by VthN, and a threshold voltage of the p-type MOS transistor is expressed by VthP. In this case, a current Ip 1  flowing through the MOS transistor MP 1  and a current In 1  flowing through the MOS transistor MN 1  are obtained by the following expressions. 
         [0000]        In 1=( βN/ 2)×( WMN 1/ LMN 1)×( VGSMN 1 −VthN )̂2   Expression (1) 
         [0000]        Ip 1=( βP/ 2)×( WMP 1/ LMP 1)×( VGSMP 1− VthP )̂2   Expression (2) 
         [0043]    In order to adjust VOUTB to VDD/2 when VIN is equal to VDD/2, the sizes of the MOS transistors MN 1  and MP 1  are preferably determined such that In 1  is equal to Ip 1  in the condition (VIN=VDD/2 and VOUTB=VDD/2). 
         [0044]    Because VIN is equal to VDD/2, VGSMN 1  is equal to VDD/2. The gate of the MOS transistor MP 1  is coupled to the low-potential side power supply potential VSS, so VGSMP 1  is equal to VDD. 
         [0045]    Therefore, when the condition of “VGSMN 1 =VDD/2” and “VGSMP 1 =VDD” is added to Expressions (1) and (2), transistor size ratios (WMN 1 /LMN 1  and WMP 1 /LMP 1 ) can be determined. 
         [0046]    The semiconductor circuit according to Embodiment 1 of the present invention further includes the n-type-MOS transistor MN 3  and the p-type MOS transistor MP 3 . Therefore, transistor sizes are determined using the following expressions for a current In 3  flowing through the MOS transistor MN 3  and a current Ip 3  flowing through the MOS transistor MP 3 . 
         [0000]        In 3=( βN/ 2)×( WMN 3/ LMN 3)×( VGSMN 3− VthN )̂2   Expression (3) 
         [0000]        Ip 3=( βP/ 2)×( WMP 3/ LMP 3)×( VGSMP 3− VthP )̂2   Expression (4) 
         [0047]    In order to adjust VOUTB to VDD/2 when VIN is equal to VDD/2, in the case of the condition (VIN=VDD/2 and VOUTB=VDD/2), it is preferable to determine the sizes of the MOS transistors MN 1  and MP 1  such that In 3  is equal to Ip 3  and to determine the sizes of the MOS transistors MN 3  and MP 3  such that In 3  is equal to Ip 3 . 
         [0048]    Because VOUTB is equal to VDD/2 and the gate of the MOS transistor MN 3  is coupled to the high-potential side power supply potential VDD, VGSMN 3  is equal to VDD/2. The gate of the MOS transistor MP 3  is coupled to the low-potential side power supply potential VSS, so VGSMP 3  is equal to VDD/2. Therefore, when the condition of “VGSMN 3 =VDD/2” and “VGSMP 3 =VDD/2” is added to Expressions (3) and (4), size ratios WMN 3 /LMN 3  and WMP 3 /LMP 3  can be determined. 
         [0049]    When the transistors satisfying the size ratios are formed, the buffer circuit  101  is capable of outputting VDD/2 as VOUTB when VIN is equal to VDD/2. 
         [0050]    As described in the conventional technique, the semiconductor circuit manufacturing process becomes finer, so variations occur in β value and threshold voltage value in each of the n-type MOS transistor and the p-type MOS transistor.  FIG. 2  is a table showing examples of variations in values of βN, βP, VthN, and VthP which are caused by the variability of a transistor manufacturing process. Note that a negative sign of VthP is omitted. Hereinafter, transistor sizes, a voltage at an operating point, and the like are specifically obtained based on the values shown in the table. 
         [0051]    Specific numeral values of WMP 1  and WMP 3  are obtained in the case where the variability of the manufacturing process on each of the n-type MOS transistor and the p-type MOS transistor corresponds to a “middle” condition (that is, a condition in which there is no variability of the manufacturing process, hereinafter referred to as TYP condition) in the table shown in  FIG. 2  are obtained. Each of LMN 1 , LMP 1 , LMN 3 , and LMP 3  is set to 0.2 μm, WMN 1  is set to 10 μm, WMN 3  is set to 3.5 μm, and VDD is set to 1.5 V. The set values are substituted into Expressions (1), (2), (3), and (4). In this way, WMP 1  (=2.9 μm) and WMP 3  (=16.0 μm) can be obtained. 
         [0052]    Because the transistor size values as described above are obtained, when VIN is equal to VDD/2 in the TYP condition, VOUTB becomes equal to VDD/2. Therefore, an operating point of the output signal OUTB can be set to VDD/2 corresponding to the middle operating point. The transistor sizes of the semiconductor circuit are determined for a normal manufacturing process based on the TYP condition. 
         [0053]    Next, the case where the process variability on the n-type MOS transistor and the p-type MOS transistor is taken into account is considered. In general, the types of combined variability of the “n-type MOS transistor capability/p-type MOS transistor capability” include five types, “large/large”, “middle/middle”, “small/small”, “large/small”, and “small/large”. In this case, the types of “large/small” and “small/large” are considered. This is because the directions of variability of the n-type MOS transistor capability and the p-type MOS transistor capability are equal to each other in the types of “large/small” and “small/large”, thereby making the same behavior as that in the TYP condition (“middle/middle”). 
         [0054]    The case where the type of the process variability on the n-type MOS transistor and the p-type MOS transistor is “large/small” is considered. In this case, as is apparent from the table shown in  FIG. 2 , βN, βP, VthN, and VthP are 220e-6, 80e-6, 0.3 V, and 0.6 V, respectively. When In 1  is calculated based on the transistor sizes (each of LMN 1 , LMP 1 , LMN 3 , and LMP 3  is 0.2 μm, WMN 1  is 10 μm, WMP 1  is 2.9 μm, WMN 3  is 3.5 μm, and WMP 3  is 16.0 μm) prepared under the TYP condition in the case of VGSMN 1 =VIN=VDD/2=0.75 V, 1.1137 mA is obtained as In 1  from Expression (1). Similarly, when Ip 1  is calculated using Expression (2) in the case of VGSMP 1 =VDD=1.5 V, 0.47 mA is obtained as Ip 1 . When In 3  is calculated using Expression (3) in the case of VGSMN 3 =VDD/2=0.75 V, 0.389 mA is obtained as In 3 . When Ip 3  is calculated using Expression (4) in the case of VGSMP 3 =VDD/2=0.75 V, 0.072 mA is obtained as Ip 3 . 
         [0055]    As is apparent from  FIG. 1 , because of circuit coupling in Embodiment 1 of the present invention, a difference current between Ip 1  and In 1 , that is, 0.6437 mA (=1.1137 mA−0.47 mA) is adjusted by a difference current between Ip 3  and In 3 , that is, 0.317 mA (=0.389 mA−0.072 mA). Therefore, substantial Ip 1  is corrected up to 0.787 mA (=0.47 mA+0.317 mA). Thus, when VGSMN 1  (=VIN) in the case of In 1 =Ip 1 =0.787 mA is calculated using Expression (1), 0.678 V is obtained as VGSMN 1  (=VIN). 
         [0056]    In order to compare the present invention with the conventional technique, VGSMN 1  (=VIN) of the buffer circuit  11  according to the conventional technique as shown in  FIG. 21  in the case where the type of the process variability is “large/small” is calculated. In the case of the transistor sizes (each of LMN 1  and LMP 1  is 0.2 μm, WMN 1  is 10 μm, and WMP 1  is 2.9 μm), 0.59 V is obtained as VGSMN 1  using Expressions (1) and (2). Because VGSMN 1  is equal to VIN, VIN in the case where the type of the process variability is “large/small” is reduced by 0.16 V from 0.75 V, being VIN in the TYP condition. In other words, the operating point of VOUTB in the case where VIN is equal to 0.75 V (VDD/2) is 0.59 V. 
         [0057]    Therefore, in the case of the buffer circuit  11  according to the conventional technique as shown in  FIG. 21 , VGSMN 1  (=VIN) is equal to 0.590 V, so VGSMN 1  is shifted from VIN in the TYP condition by −0.16 V. In contrast, in the case of the semiconductor circuit according to Embodiment 1 of the present invention, VGSMN 1  (=VIN) is equal to 0.678 V, so the shift from VIN is reduced to approximately −0.07 V. Thus, the operating point of VOUTB is corrected for compensation. 
         [0058]    The case where the type of the process variability on the n-type MOS transistor and the p-type MOS transistor is “small/large” is considered. In this case, as is apparent from the table shown in  FIG. 2 , βN, βP, VthN, and VthP are 200e-6, 100e-6, 0.5 V, and 0.4 V, respectively. When In 1  is calculated based on the transistor sizes (each of LMN 1 , LMP 1 , LMN 3 , and LMP 3  is 0.2 μm, WMN 1  is 10 μm, WMP 1  is 2.9 μm, WMN 3  is 3.5 μm, and WMP 3  is 16.0 μm) prepared under the TYP condition in the case of VGSMN 1 =VIN=VDD/2=0.75 V, 0.313 mA is obtained as In 1  from Expression (1). Similarly, when Ip 1  is calculated using Expression (2) in the case of VGSMP 1 =VDD=1.5 V, 0.877 mA is obtained as Ip 1 . When In 3  is calculated using Expression (3) in the case of VGSMN 3 =VDD/2=0.75 V, 0.109 mA is obtained as In 3 . When Ip 3  is calculated using Expression (4) in the case of VGSMP 3 =VDD/2=0.75 V, 0.490 mA is obtained as Ip 3 . 
         [0059]    As is apparent from  FIG. 1 , because of circuit coupling in Embodiment 1 of the present invention, a difference current between Ip 1  and In 1 , that is, 0.564 mA (=0.877 mA−0.313 mA) is adjusted by a difference current between Ip 3  and In 3 , that is, 0.381 mA (=0.109 mA−0.490 mA). Therefore, substantial Ip 1  is corrected up to 0.496 mA (=0.877 mA−0.381 mA). Thus, when VGSMN 1  (=VIN) in the case of In 1 =Ip 1 =0.496 mA is calculated using Expression (1), 0.836 V is obtained as VGSMN 1  (=VIN). 
         [0060]    In order to compare the present invention with the conventional technique, VGSMN 1  (=VIN) of the buffer circuit  11  according to the conventional technique as shown in  FIG. 21  in the case where the type of the process variability is “small/large” is calculated. In the case of the transistor sizes (each of LMN 1  and LMP 1  is 0.2 μm, WMN 1  is 10 μm, and WMP 1  is 2.9 μm), 0.92 V is obtained as VGSMN 1  using Expressions (1) and (2). Because VGSMN 1  is equal to VIN, VIN in the case where the type of the process variability is “small/large” is increased by 0.17 V from 0.75 V, being VIN in the TYP condition. In other words, the operating point of VOUTB in the case where VIN is equal to 0.75 V (VDD/2) is 0.92 V. 
         [0061]    Therefore, in the case of the buffer circuit  11  according to the conventional technique as shown in  FIG. 21 , VGSMN 1  (=VIN) is equal to 0.92 V, so VGSMN 1  is shifted from VIN in the TYP condition by +0.17 V. In contrast, in the case of the semiconductor circuit according to Embodiment 1 of the present invention, VGSMN 1  (=VIN) is equal to 0.836 V, so the shift from VIN is reduced to approximately +0.086 V. Thus, the operating point of VOUTB is corrected for compensation. 
         [0062]    As is apparent from the above description, even when the type of the process variability is “large/small” or “small/large”, the operation (change in output to input) waveform of the buffer circuit according to the Embodiment 1 of the present invention is made as shown in  FIGS. 3A and 3B . Therefore, substantially the same operation as that of a normal buffer circuit is performed (operating points of the output signal OUTB are points A and B of  FIG. 3B ). 
         [0063]      FIG. 4  shows a buffer circuit  102  in which the input terminal  1  is coupled to the p-type MOS transistor MP 1  and the n-type MOS transistor MN 1  is coupled to serve as a load for the MOS transistor MP 1 . In this case, the logic of the output signal OUTB is merely inverted relative to the logic of the output signal of the buffer circuit  101 . The other operation and the like are the same, and thus the detailed description is omitted. 
         [0064]    As is apparent form the above description, the semiconductor circuit according to Embodiment 1 of the present invention has the following effects. In the case of the buffer circuit  11  according to the conventional technique as shown in  FIG. 21 , when the condition type of the process variability is varied to “large/small” or “small/large”, In 1 ≠Ip 1  is obtained under the condition of VIN=VDD/2. Therefore, the operating points of the output signal OUTB deviate. In contrast, in the case of the semiconductor circuit according to Embodiment 1 of the present invention, as shown in  FIG. 1 , the MOS transistors MP 3  and MN 3  are provided which are formed by the same manufacturing process as that of the MOS transistors MP 1  and MN 1  and coupled to power supply voltages reverse to each other. Therefore, the difference between Ip 1  and In 1  is adjusted by the operating currents In 3  and Ip 3  of the MOS transistors MN 3  and MP 3  to correct the operating points of the output signal OUTB for compensation. 
         [0065]    For example, when a normal CMOS inverter  21  (threshold voltage is VDD/2) shown in  FIG. 5  receives an output from the buffer circuit  11  according to the conventional technique, a problem occurs in that a predetermined duty value is not obtained as shown in operating waveforms of  FIGS. 6A and 6B . (For example, although a duty under the TYP condition is 50%, a duty of each of the waveforms of  FIGS. 6A and 6B  is equal to or larger than 50%.) When both a rising edge and a falling edge of an output signal of the inverter whose predetermined duty value deviates are to be used for clock signals, a problem occurs in that the margins of setup/hold times are not sufficiently ensured. Therefore, some measures including the addition of a duty correction circuit are required. However, according to the present invention, such a problem can be also solved because the operating points of the output signal OUTB of the buffer circuit  101  can be corrected for compensation. 
         [0066]    The semiconductor circuit according to the present invention is expected to be a circuit output stage serving as the buffer circuit. Note that the present invention is not limited to the circuit output stage and thus may be applied to a circuit input stage. This is because, when the semiconductor circuit according to the present invention is used for a preceding stage, there is an advantage that the reliability of a signal for a subsequent-stage circuit is improved. 
         [0067]    As in the case of the variability of the manufacturing process, the compensation capability of the semiconductor circuit is effective for a change in threshold voltage of a transistor being caused by a change in operating temperature of the circuit and for a variation in drive capability of the transistor being caused by a change in drain-source voltage due to a variation in power supply voltage. Therefore, variations in operating points which are caused by changes in temperature, power supply voltage, and manufacturing process can be compensated by the semiconductor circuit according to this embodiment. The above description is effective for Embodiment 2 and a subsequent embodiment. 
       Embodiment 2 of the Present Invention 
       [0068]    Hereinafter, a specific example of a semiconductor circuit according to Embodiment 2 of the present invention will be described in detail with reference to the attached drawings. In Embodiment 2, the present invention is applied to a pseudo differential buffer circuit in which two buffer circuits, each of being the buffer circuit according to Embodiment 1, are arranged in parallel. 
         [0069]      FIG. 7  shows an example of a structure of the semiconductor circuit according to Embodiment 2 of the present invention. Of reference symbols shown in  FIG. 7 , elements expressed by the same reference symbols as those shown in  FIG. 1  are identical or similar to elements shown in  FIG. 1 . Embodiment 2 is different from Embodiment 1 in that a circuit structure in which two buffer circuits, each of being the buffer circuit shown in  FIG. 1 , are coupled in parallel is employed. In this embodiment, the description will be focused on the point. 
         [0070]    A pseudo differential buffer circuit  103  includes the input terminal  1  to which the input signal IN is input, the n-type MOS transistor MN 1  for generating the inverted logic of the input signal, the p-type MOS transistor MP 1  serving as the load for the MOS transistor MN 1 , the output terminal  2  from which the output signal OUTB being the inverted logic of the input signal is output, and the n-type MOS transistor MN 3  and the p-type MOS transistor MP 3  which are used to compensate for a variation in rise time of the output signal OUTB (hereinafter, the circuit structure is referred to as circuit unit  111 ). The pseudo differential buffer circuit  103  further includes an input terminal  3  to which an input signal INB is input, an n-type MOS transistor MN 2  for generating a inverted logic of the input signal INB, a p-type MOS transistor MP 2  serving as a load for the MOS transistor MN 2 , an output terminal  4  from which an output signal OUT being the inverted logic of the input signal INB is output, and the n-type MOS transistor MN 4  and the p-type MOS transistor MP 4  which are used to compensate for a variation in rise time of the output signal OUT (hereinafter, the circuit structure is referred to as circuit unit  112 ). Note that the input signal IN and the input signal INB are differential signals whose logics are inverted relative to each other. Therefore, the output signal OUTB and the output signal OUT are also signals whose logics are inverted relative to each other. 
         [0071]    The MOS transistor MN 1  includes the gate coupled to the input terminal  1 , the drain coupled to the output terminal  2 , and the source coupled to the low-potential side power supply potential VSS. The MOS transistor MP 1  includes the gate coupled to the low-potential side power supply potential VSS, the drain coupled to the output terminal  2 , and the source coupled to the high-potential side power supply potential VDD. The MOS transistor MN 3  includes the source coupled to the output terminal  2 , and the drain and the gate which are coupled to the high-potential side power supply potential VDD. The MOS transistor MP 3  includes the source coupled to the output terminal  2 , and the drain and the gate which are coupled to the low-potential side power supply potential VSS. Assume that a voltage input to the input terminal  1  is expressed by VIN and a voltage output to the output terminal  2  is expressed by VOUTB. The MOS transistor MN 2  includes a gate coupled to the input terminal  3 , a drain coupled to the output terminal  4 , and a source coupled to the low-potential side power supply potential VSS. The MOS transistor MP 2  includes a gate coupled to the low-potential side power supply potential VSS, a drain coupled to the output terminal  4 , and a source coupled to the high-potential side power supply potential VDD. The MOS transistor MN 4  includes a source coupled to the output terminal  4 , and a drain and a gate which are coupled to the high-potential side power supply potential VDD. The MOS transistor MP 4  includes a source coupled to the output terminal  4 , and a drain and a gate which are coupled to the low-potential side power supply potential VSS. Assume that a voltage input to the input terminal  3  is expressed by VINB and a voltage output to the output terminal  4  is expressed by VOUT. 
         [0072]    Each of the circuit unit  111  and the circuit unit  112  which are included in the pseudo differential buffer circuit  103  has the same structure as that of the buffer circuit  101  according to Embodiment 1. Therefore, according to the circuit unit  111 , the difference between Ip 1  and In 1  is adjusted by the operating currents In 3  and Ip 3  of the MOS transistors MN 3  and MP 3  which are formed by the same manufacturing process as that of the MOS transistors MP 1  and MN 1  and coupled to power supply voltages reverse to each other, so the operating point deviation can be compensated. According to the circuit unit  112 , a difference between Ip 2  and In 2  is adjusted by operating currents In 4  and Ip 4  of the MOS transistors MN 4  and MP 4  which are formed by the same manufacturing process as that of the MOS transistors MP 2  and MN 2  and coupled to power supply voltages reverse to each other, so the operating point deviation can be compensated. 
         [0073]    The above description is the same as that for the buffer circuit  101  according to Embodiment 1 and thus the description using the expressions and the like is omitted. 
         [0074]    Deviation of points at which the output signals OUT and OUTB cross (cross point) are compensated to obtain operating waveforms shown in  FIGS. 8A and 8B . Therefore, even when the process variability occurs, the operating waveforms of the output signals OUT and OUTB in the pseudo differential buffer circuit  103  according to this embodiment are substantially identical to the operating waveforms in the normal pseudo differential buffer circuit (cross points of the output signals OUT and OUTB correspond to points C and D of  FIG. 8B ). 
         [0075]    In order to compare the present invention with the conventional technique, a pseudo differential buffer circuit  12  according to the conventional technique is shown in  FIG. 9 . In the pseudo differential buffer circuit  12 , two buffer circuits, each of being the buffer circuit  11  shown in  FIG. 21 , are coupled in parallel. According to the circuit shown in  FIG. 9 , the deviations of the operating points of the output signals OUT and OUTB which are caused by the process variability is not compensated. Therefore, the operating points of the output signals OUT and OUTB deviate (cross points deviate). The operating waveforms of the circuit are shown as follows. 
         [0076]      FIGS. 10A and 10B  show the operating waveforms in the case where the type of the process variability is “large/small”. As shown in  FIG. 10B , when each of VIN and VINB is equal to VDD/2, the cross points of VOUT and VOUTB (point-E and point-F in  FIG. 10B ) fall. Results obtained by waveform simulation on the circuit in the variability condition are shown as reference in  FIGS. 11A and 11B . Even in the case of simulation, it is apparent that the same results as those shown in  FIGS. 10A and 10B  are obtained. 
         [0077]      FIGS. 12A and 12B  show the operating waveforms in the case where the type of the process variability is “small/large”. As shown in  FIG. 12B , when each of VIN and VINB is equal to VDD/2, the cross points of VOUT and VOUTB (point-G and point-H in  FIG. 12B ) rise. 
         [0078]    The operation of the pseudo differential buffer circuit  12  according to the conventional technique is described above. According to the pseudo differential buffer circuit  103  in Embodiment 2 of the present invention, the operating waveforms as shown in  FIGS. 8A and 8B  are obtained, so the variations in cross points as shown in  FIG. 10B  (or  FIG. 12B ) can be suppressed. 
         [0079]    For example, when normal CMOS inverters  22  and  23  (threshold voltage is VDD/2) shown in  FIG. 13  receives an output from the buffer circuit  12  according to the conventional technique, a problem occurs in that a predetermined duty value is not obtained as shown in operating waveforms of  FIGS. 14A and 14B . (For example, although a duty in the TYP condition is 50%, a duty of each of the waveforms of  FIGS. 14A and 14B  is equal to or larger than 50%.) When both a rising edge and a falling edge of an output signal of each inverter whose predetermined duty value deviates are to be used for clock signals, a problem occurs in that the margins of setup/hold times are not sufficiently ensured. Therefore, some measures including the addition of a duty correction circuit are required. However, according to the present invention, such a problem can be also solved because the cross points of the output signals OUTB and OUT of the buffer circuit  103  can be corrected for compensation. 
         [0080]    As in the case of Embodiment 1 of the present invention, the compensation capability of the semiconductor circuit according to this embodiment is effective for a change in threshold voltage of a transistor being caused by a change in operating temperature of the circuit and for a variation in drive capability of the transistor being caused by a change in drain-source voltage due to a variation in power supply voltage or the like, as in the case of the variability of the manufacturing process. Therefore, variations in positive and negative cross points which are caused by changes in temperature, power supply voltage, and manufacturing process can be compensated by the semiconductor circuit according to this embodiment. 
         [0081]      FIG. 15  shows a pseudo differential buffer circuit  104 . In the pseudo differential buffer circuit  104 , the input terminal  1  is coupled to the p-type MOS transistor MP 1 , the n-type MOS transistor MN 1  is coupled to serve as the load for the MOS transistor MP 1 , the input terminal  3  is coupled to the p-type MOS transistor MP 2 , and the n-type MOS transistor MN 2  is coupled to serve as the load for the MOS transistor MP 2 . Note that other structures are identical to the structures as shown in  FIG. 7 . In this case, the logic of each of the output signals OUTB and OUT is inverted relative to the logic of corresponding one of the output signals of the pseudo differential buffer circuit  103  shown in  FIG. 7 . The operation and the effect are the same as described above and thus the detailed description thereof will be omitted. 
       Embodiment 3 of the Present Invention 
       [0082]    Hereinafter, a specific example of a semiconductor circuit according to Embodiment 3 of the present invention will be described in detail with reference to the attached drawings. In Embodiment 3, the present invention is applied to a buffer circuit or a pseudo differential buffer circuit as in the case of Embodiment 1 or 2 of the present invention. 
         [0083]      FIG. 16  shows an example of a structure of the semiconductor circuit according to Embodiment 3 of the present invention. In the semiconductor circuit according to this embodiment as shown in  FIG. 16 , a disable signal (DISABLE) is input to the gate of the MOS transistor MN 3  of the buffer circuit  101  of  FIG. 1  as described in Embodiment 1 of the present invention. An inverted signal of the disable signal is input to the gate of each of the MOS transistors MP 1  and MP 3  through an inverter. Here, it is assumed that the disable signal to be input is “1” in the case where the circuit is in an active state and “0” in the case where the circuit is in a non-active state. Thus, in this case, when the disable signal is “1”, the same operation as Embodiment 1 of the present invention is performed. When the disable signal is “0” , the gate of each of the MOS transistors MP 1 , MN 3 , and MP 3  is closed, so the buffer circuit  101  becomes the non-active state. Therefore, when a circuit non-active signal for a normal circuit, such as the disable signal is used, the buffer circuit according to Embodiment 1 of the present invention can be reduced in power.  FIG. 17  shows a circuit in which the disable signal as described above is-applied to the buffer circuit  102  of  FIG. 4  according to Embodiment 4 of the present invention.  FIGS. 18 and 19  show a circuit in which the disable signal as described above is applied to the pseudo differential buffer circuit  103  shown in  FIG. 7  and a circuit in which the disable signal is applied to the pseudo differential buffer circuit  104  shown in  FIG. 15 . According to the pseudo differential buffer circuits, the same power reduction effect as described above can be obtained. 
         [0084]    The present invention is not limited to the embodiments described above and thus appropriate modifications can be made without departing from the scope of the present invention. For example, as shown in  FIG. 20 , an n-type MOS transistor MN 5  may be coupled to the high-potential side power supply potential VDD (or low-potential side power supply potential VSS) of the circuit shown in  FIG. 1 . Thus, as in the case of Embodiment 3 of the present invention, the disable signal can be used to reduce the power of the circuit.