Abstract:
A method of forming a circuit board which includes generating laser light with a carbon dioxide laser and making a hole through an insulating substrate by irradiating the insulating substrate with the laser light. The hole includes a top opening in a top surface of the insulating substrate, a bottom opening in a bottom surface of the insulating substrate, and an inner wall extending from the top opening to the bottom opening along a thickness direction of the insulating substrate, the inner wall including a bulge which extends in a direction generally orthogonal to the thickness direction. A via hole is formed in the insulating substrate by providing metal in the hole such that the metal extends from the top opening to the bottom opening along the inner wall, and completely closes each of the top and bottom openings.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a divisional of U.S. Ser. No. 11/480,851, filed on Jul. 6, 2006, the contents of which are incorporated by reference herein in its entirety. U.S. Ser. No. 11/480,851 also claims priority to Japanese Patent Application No. 2005-199442, filed Jul. 7, 2005. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to a multilayer printed wiring board for mounting electronic components such as a capacitor, IC and the like on the surface layer thereof. 
     BACKGROUND ART 
     The recent portable electronic devices such as a mobile phone, digital camera, etc., use a multilayer printed wiring board having electronic components such as a capacitor, IC and the like mounted on the surface layer thereof. 
     More specifically, the electronic components to be mounted on such a wiring board are passive parts such as an IC chip, capacitor, resistor, inductor and the like, a liquid crystal device, a display device for digital indication, control devices such as keypad, switches and the like or external terminals such as a USB, earphone and the like. 
     Various conductor pads corresponding to electronic components are provided together on a printed circuit board, a solder body is formed on each of the conductor pads, and the electronic components are mounted on the solder bodies on the conductor pads. 
     A typical one of multilayer circuit boards on which the above electronic components are to be mounted is disclosed in the Japanese unexamined patent publication No. H10-13028. As disclosed in the above Japanese unexamined patent publication No. H10-13028, holes for viaholes are formed, by lasering, in an insulating rigid substrate having a conductor circuit formed on one side or either side thereof, viaholes are formed by filling a metal paste or a plating material in the holes to form an interlayer-connected circuit board, and two or more such circuit boards prepared as above are stacked sequentially or collectively to produce a multilayer printed wiring board. 
     In such a multilayer circuit board, two circuit boards are electrically connected to each other by connecting a viahole or a land of the viahole in one of the adjacent circuit boards to a conductor circuit or land of the other circuit board. 
     Also, the circuit boards are joined, at other areas thereof not contributing to electrical connection between them, to each other with an adhesive layer, prepreg or the like of a thermosetting resin, to thereby form a multilayer structure. 
     Normally, a solder resist layer to protect the conductor circuit is formed on the surface layer of the above multilayer circuit board or prevailing printed wiring board, a hole is formed in a part of the solder resist layer, and a corrosion-resistant layer of gold or nickel is formed on the surface, exposed in the hole, of the conductor circuit. A solder body such as a solder bump is formed on the surface, having the corrosion-resistant layer formed thereon, of the conductor circuit, and an electronic component such as a capacitor, IC or the like is mounted on the solder body formed on the conductor circuit surface. 
     BRIEF SUMMARY OF THE INVENTION 
     According to one embodiment of the present invention, there is provided a multilayer printed wiring board in which insulating layers and conductor layers are stacked alternately on each other and the conductor layers are electrically connected to each other through viaholes formed in the insulation layers, wherein each of the viaholes has at least a part thereof formed to bulge in a direction generally orthogonal to the direction of thickness of the insulating layer. 
     According to other embodiment of the present invention, there is also provided a multilayer printed wiring board in which one insulating substrate having a conductor circuit formed thereon has stacked on either side thereof at least one other insulating substrate having a conductor circuit formed thereon and the conductor circuit formed on the one insulating substrate and that on the other insulating substrate are electrically connected to each other through viaholes formed in the insulating substrates, wherein each of the viaholes has at least a part thereof formed to bulge in a direction generally orthogonal to the direction of thickness of the insulating layer. 
     According to still other embodiment of the present invention, there is also provided a multilayer printed wiring board in which insulating layers and conductor layers are stacked alternately on each other and the conductor layers are electrically connected to each other through viaholes formed in the insulating layers, wherein the insulating layers are at least three in number; the viaholes include a first group of viaholes and a second group of viaholes; the first group includes viaholes in a stack of two or more viaholes in which each viahole is formed to bulge in a direction generally orthogonal to the direction of thickness of the insulating layer; the second group includes viaholes formed to bulge in a direction generally orthogonal to the direction of thickness of the insulating layer; and the first and second groups of viaholes are disposed in positions opposite to each other. 
     In the above multilayer printed wiring boards according to the embodiments of the present invention, the insulating layer or insulating substrate may be about 100 μm or less in thickness. Otherwise, the insulating layer or substrate may be about 50 μm or less in thickness. 
     Also in the above multilayer printed wiring boards according to the embodiments of the present invention, the viaholes may be stacked on each other to form a multistage stacked vias. Also, the viaholes formed in the insulating substrates stacked on one side of one of the insulating substrates having the conductor layer formed thereon are taken as a first group of viaholes, while those formed in the insulating substrates stacked on the other side of the one insulating layer are taken as a second group of viaholes. 
     In the above printed wiring boards according to the embodiments of the present invention, the first viahole group may be stacked on the second viahole group in such geometry that they are opposite to each other. Also, the first viahole group may be stacked on the second viahole group in such geometry that it is shifted in relation to the second viahole group in a direction generally orthogonal to the direction of thickness of the insulating layer. 
     Also in the above multilayer printed wiring boards according to the embodiments of the present invention, the viaholes in the first or second group may be stacked on almost same straight lines, respectively. Otherwise, the viaholes may be stacked together in such geometry that they are shifted from each other in a direction generally orthogonal to the direction of thickness of the insulating layer. 
     Also in the above multilayer printed wiring boards according to the embodiments of the present invention, the viaholes included in either the first or second group may be positioned at two opposite apexes of an imaginary tetragonal lattice on the insulating substrate while the viaholes included in the other group may be positioned at other two opposite apexes of the imaginary tetragonal lattice on the insulating layer. 
     Also in the above multilayer printed wiring boards according to the embodiments of the present invention, the viaholes included in either the first or second group may be positioned at apexes of an imaginary tetragonal or triangular lattice on the insulating substrate while the viaholes included in the other group may be positioned at the center of the imaginary tetragonal or triangular lattice on the insulating layer. 
     Also in the above multilayer printed wiring boards according to the embodiments of the present invention, the viaholes included in either the first or second group may be positioned intensively in a predetermined area of the insulating substrate while the viaholes included in the other group may be positioned in a peripheral area surrounding the predetermined area of the insulating layer. 
     Also in the above multilayer printed wiring board according to the embodiments of the present invention, each of the viaholes may be formed to bulge so that the diameter of a largest bulged part is about 1.1 to 1.5 times larger than that of the hole in the top or bottom of the insulating layer. 
     Also in the above multilayer printed wiring boards according to the embodiments of the present invention, each of the viaholes may be formed by filling a plating material in a hole formed in the insulating layer or insulating substrate. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a schematic sectional view of a barrel-shaped viahole in the multilayer printed wiring board according to the present invention and  FIG. 1B  is a SEM picture showing the section of the printed wiring board having the barrel-shaped viahole formed therein. 
         FIG. 2  is a schematic sectional view of a basic shape of the multistage stacked vias in the multilayer printed wiring board according to the present invention. 
         FIGS. 3A and 3B  are schematic sectional views of variants of the multistage stacked vias. 
         FIG. 4  is a schematic sectional view of another basic shape of the multistage stacked vias in the multilayer printed wiring board according to the present invention. 
         FIGS. 5A to 5C  schematically illustrate examples of disposition in plane of viaholes included in a multistage stacked vias (disposition in the form of a tetragonal lattice). 
         FIG. 6  schematically illustrates another example of disposition in plane of viaholes included in a multistage stacked vias (disposition in the form of a triangular lattice). 
         FIG. 7  schematically illustrates another example of disposition in plane of viaholes included in a multistage stacked vias (disposition on straight lines). 
         FIGS. 8A and 8B  schematically illustrate other examples of disposition in plane of viaholes included in a multistage stacked vias (concentrated disposition and dispersed disposition). 
         FIGS. 9A to 9E  are schematic sectional views of a multilayer printed wiring board as an embodiment 1 of the present invention, showing some steps in the manufacturing process for the multilayer printed wiring board. 
         FIGS. 10A to 10E  are schematic sectional views of the multilayer printed wiring board as the embodiment 1 of the present invention, showing some other steps in the manufacturing process for the multilayer printed wiring board. 
         FIG. 11  is a schematic sectional view of the multilayer printed wiring board as the embodiment 1 of the present invention, showing another step in the manufacturing process for the multilayer printed wiring board. 
         FIGS. 12A and 12B  are schematic sectional views of the multilayer printed wiring board as the embodiment 1 of the present invention, showing further steps in the manufacturing process for the multilayer printed wiring board. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     The multilayer printed wiring board as an embodiment of the present invention is configured such that at least one viahole is formed in an insulating layer to electrically connect conductor layers formed on either side of the insulating layer to each other so that at least a part thereof bulges in a direction orthogonal to the direction of thickness of the insulating layer. 
     More specifically, on either side of one insulating substrate having at least one conductor circuit formed thereon, there is stacked at least one other insulating substrate having at least one conductor circuit formed thereon, the conductor circuit provided on the one insulating substrate and that provided on the other insulating substrate are electrically connected to each other through viaholes formed in the insulating substrates, respectively, and each of the viaholes is formed to have at least a part thereof bulged in a direction generally orthogonal to the direction of thickness of the insulating layer. 
     It is inferred that in the above embodiment of the present invention, since each viahole to electrically connect the conductor layers to each other is formed for at least a part thereof to bulge in a direction generally orthogonal to the direction of thickness of the insulating layer, it is not easily broken due to an external stress (such as an impact applied when the multilayer printed wiring board is dropped) and the conductor circuits can be prevented from being cracked, opened or otherwise influenced. As a result, the printed circuit board including the multilayer printed wiring board can maintain its reliability and drop-shock resistance. 
     Especially, the viaholes can be stacked together to form a multistage stacked vias structure. So, in case the printed circuit board is applied with an external stress and the insulating layers are warped outwardly, the insulating resin layers and conductor layers forming the multistage stacked vias are not easily separable from each other because the multistage stacked vias will bite in the insulating layers. 
     Also, the multistage stacked vias formed in the insulating layers will function as a stake to prevent the insulating layers from being easily warped. As a result, the printed circuit board can maintain its specified reliability and drop-shock resistance. 
     Also, since the multistage stacked vias is formed within the insulating layers, it will function as a stake to prevent the insulating layers from being easily be warped. Therefore, it is inferred that the substrates will be able to keep their flatness, so that the printed circuit board can maintain the reliability as provable by the reliability test such as a heat cycle test without any early cracking of the conductor circuits including the viaholes and insulating layers and any reduction in reliability of the printed circuit board. As a result, the printed circuit board can maintain its reliability. 
     It is inferred that especially, a printed circuit board can be formed by forming a conductor circuit on an insulating layer or substrate of about 100 μm or less in thickness to form a multilayer printed wiring board and stacking more than one such multilayer printed wiring boards together. In this case, the printed circuit board can maintain its flatness. 
     Also it is inferred that even in case the insulating layer or substrate is 50 μm or less in thickness, a similar effect can be assured. 
     Also, the multistage stacked vias (first and second viahole groups), formed in such geometry that the first and second viahole groups are opposite to each other, effectively prevents the insulating layers from easily being warped both outwardly and inwardly. That is, even if the insulating layers are going to be warped when applied with an external stress, the multistage stacked vias formed in the insulating layers will add to the resistance against both the outward and inward warp caused by the external stress. As a result, the printed circuit board can maintain its reliability and drop-shock resistance. 
     Also, since the multistage stacked vias are disposed opposite to each other, the insulating layers themselves will be improved in rigidity where the multistage stacked vias are provided. Therefore, it is possible to reduce the warping itself of the printed circuit board, and the flatness of the printed circuit board can be maintained and mounted components will not drop off the printed circuit board in the subsequent process (such as solder-resist forming step, solder layer forming step, electronic component mounting step, etc.). As a result, the printed circuit board can maintain its reliability and drop-shock resistance. 
     Especially, a printed circuit board can advantageously be formed by forming a conductor circuit on an insulating layer or substrate of about 100 μm or less in thickness and stacking more than one such an insulating layer or substrate together. 
     Further, a printed circuit board can advantageously be formed by forming a conductor circuit on an insulating layer or substrate of about 50 μm or less in thickness and stacking more than one such an insulating layer or substrate together. The printed circuit board can have a satisfactory reliability and drop-shock resistance. 
     Various embodiments of the multilayer printed wiring board according to the present invention will be described in detail below with reference to the accompanying drawings: 
     The insulating layer or substrate used in the multilayer printed wiring board according to the present invention should be a rigid substrate formed from one selected from among, for example, glass cloth-based epoxy resin, phenol resin, glass cloth-based bismaleimide triazine resin, glass cloth-based polyphenylene ether resin, aramid unwoven cloth-based epoxy resin, aramid unwoven cloth-based polyimide resin, etc. The substrate of such an insulating resin should desirably be about 100 μm or less in thickness. Also, the substrate of such an insulating resin may be about 50 μm or less in thickness. 
     A multilayer printed wiring board (a printed circuit board for mounting electrical components) is formed by stacking such insulating layers or substrates alternately on the surface of a circuit board, in which a conductor circuit is formed on one or both of the surfaces of the insulating layer or substrate, as the core of stacking. Also, the thickness of the multilayer printed circuit board itself can be reduced by reducing the thickness of all the insulating layers or substrates in such a printed circuit board to about 100 μm or less. 
     Also, in the embodiment of the present invention, both the conductor circuits formed on the insulating substrates and the viaholes (multistage stacked vias) included in the first and second groups should desirably be formed by plating. The reason for the above is that in case the conductor circuits and the viaholes included in the first and second groups are formed from the plated film, the connections between the viahole included in the first or second group and the conductor circuits with which the viahole is in contact at the top and bottom thereof, respectively, will not easily be separated and will not be displaced even with an external stress, if applied, so that the conductor circuits and insulating layer will not easily be cracked or broken, or the like. 
     The viahole is formed by electrolytic or electroless plating. The metal used for plating may be an element such as copper, nickel, iron, cobalt or the like, or an alloy based on any of the elements. 
     As shown in  FIGS. 1A and 1B , the viahole in the embodiment of the present invention should desirably be formed to bulge in a direction generally orthogonal to the direction of thickness of the insulating layer, that is, it should desirably be formed to have a so-called barrel shape of which the diameter of an intermediate part thereof between the top and bottom is larger than those of the top and bottom. The viahole having such a barrel shape is bulged for at least a part thereof, for example, at least a just intermediate part between the top and bottom, to be largest in diameter. 
     The viahole bulging should desirably be such that the diameter at the intermediate part of the viahole is about 1.1 to about 1.5 times larger than the opening diameter (minimum) at the top or bottom, that is to say, such that on the assumption that the diameter at the top or bottom is D, the diameter at the part having the largest bulge is about 1.1 D to about 1.5 D. 
     So long as the bulging is within the above-specified range, an electrically conductive material such as a plating material can easily be filled into the viahole-forming hole and also the insulating layer can assure an insulation gap between the adjacent viaholes. 
     The top of the viahole in the embodiment of the present invention should desirably have a diameter ranging from about 50 to about 250 μm. With the diameter being within the above range, a conductor layer can easily be filled in a viahole-forming hole, it can be well formed in a barrel shape (bulging in a direction orthogonal to the direction of thickness of the insulating layer) and a gap can be assured between the adjacent viaholes. 
     Also, the viahole diameter at the bottom (will be referred to as “via-bottom diameter” hereunder) may be at least about 10 μm. The reason for the above is that since the viahole is formed by plating, the via-bottom diameter should be at least about 10 μm for that plating, whereby the upper conductor layer (upper conductor circuit and viahole) and lower one can electrically be connected to each other. 
     In the embodiment of the present invention, the multistage stacked vias should preferably be formed for the bottoms of outer viaholes (upper viaholes) to be superposed on those of inner viaholes (lower viaholes) in the same position. That is, the viaholes in the first and second groups can be formed on almost same straight lines, respectively, as shown in  FIG. 2 . 
     Also, as long as the bottom of the upper viahole and that of the lower viahole overlap each other, forming the viahole into the barrel shape can assure the reliability and drop-shock resistance of the printed circuit board including the multilayer printed wiring board. Further, in the first or second group, the viaholes may be stacked together in respective positions shifted in a direction orthogonal to each other in the direction of thickness of the insulating layers and where the bottoms of the viaholes overlap at least partially each other. 
     For example, the viaholes in the first or second group may be stacked in respective positions where they are shifted about a half of their diameter from each other as shown in  FIG. 3A . Also, the viaholes in the first or second group may be stacked in respective positions where they are shifted nearly one viahole diameter from each other as shown in  FIG. 3B . 
     The functions assured by forming the viahole in the barrel shape (bulging a part of the viahole in a direction generally orthogonal to the direction of thickness of the insulating layer) can fully be performed also when the multilayer printed wiring board is used as usual. 
     Also, in the embodiment of the present invention, the first or second group of viaholes included in the multistage stacked vias should preferably be formed by providing at least two or more insulating substrates and stacking the viaholes formed in the insulating substrates together. That is, the first or second viahole group may be formed from three, four or more viaholes by stacking them together. 
     In the multistage stacked vias, the first and second viaholes groups may be equal in number of viahole layers to each other (e.g., three viahole layers in the first group and three viahole layers in the second group) or may be different in number of viahole layers from each other (e.g., two viahole layers in the first group and three viahole layers in the second group). Basically, the interlayer electrical connection and reliability of the printed circuit board can be assured by forming the first and second viahole groups in the multistage stacked vias in such geometry that they are opposite to each other. 
     In the embodiment of the present invention, the multistage stacked vias may be an electrically conductive layer. But it may also be an electrically nonconductive layer, that is, a so-called dummy conductor layer. In case the multistage stacked vias is formed from a dummy conductor layer, it will be assured that conductor layers other than the dummy layer (conductor layers formed around the dummy conductor layer or conductor layers electrically connected to each other by the viahole in the multistage stacked vias or the like) will maintain their reliability and drop-shock resistance. Also, the printed circuit board maintains its flatness. 
     Also in the embodiment of the present invention, the first and second viahole groups included in the multistage stacked vias should desirably be disposed in generally same positions (on almost same lines) within an area where the conductor circuit of each insulating substrate is formed as shown in  FIG. 2  or disposed in respective positions shifted from each other (dispersed disposition) as shown in  FIG. 3A  or  3 B. 
     By dispersing the first and second viahole groups uniformly in the entire area of the insulating substrates, for example, it is possible to assure a satisfactory resistance of the insulating substrates against a warp caused by an external stress. 
     Also, by concentrically disposing the first and second viahole groups mainly in the central portion of the insulating substrate which is likely to be most influenced by an external stress, it is possible to assure a satisfactory resistance of the insulating substrates against a warp of the insulating substrates caused by an external stress. 
     Also, the first and second viahole groups may be disposed not in the central portion of the insulating substrate but mainly in a peripheral area surrounding that central portion. Such a disposition of the first and second viahole groups permits to assure the satisfactory resistance of the insulating substrates against the warp. Also it is possible to assure a satisfactory flatness of the printed circuit board. 
     Further, mainly in the central portion of the insulating substrate, the first and second viahole groups may be disposed opposite to each other, while in the peripheral portion, the first and second viahole groups may be disposed in respective positions shifted from each other. 
     The multistage stacked vias are disposed in any of various patterns of disposition in plane, such as a tetragonal lattice (as in  FIGS. 5A to 5C ), triangular lattice (as in  FIG. 6 ) or straight line (as in  FIG. 7 ) in addition to the aforementioned patterns. 
     In the disposition in the tetragonal lattice pattern, the viaholes are disposed as follows. For example, the first and second viahole groups are disposed regularly in an imaginary tetragonal matrix as shown in  FIG. 5A . The first viahole groups are disposed in an imaginary matrix while the second viahole groups opposite to the first ones are disposed in an intermediate portion of the matrix, as shown in  FIG. 5B . Otherwise, the first and second viahole groups are disposed regularly in an imaginary zigzag matrix as shown in  FIG. 5C . 
     In the disposition in the triangular lattice pattern, for example, the first viahole groups are disposed in an imaginary triangular pattern while the second viahole groups opposite to the first ones are disposed near the center, or at the center of gravity, of the triangle, as shown in  FIG. 6 . 
     Also, the viaholes may be disposed on a straight line. For example, at least two first groups of viaholes are disposed on an imaginary straight line while a second viahole group opposite to the first viahole groups is disposed at the center of the straight line, as shown in  FIG. 7 . 
     Also, the multistage stacked vias may be formed in a combination of two or more of the above-mentioned patterns of viahole disposition. 
     Further, in the embodiment of the present invention, for example, the second viahole groups may be disposed opposite to each other in areas where no first viahole groups are disposed, which disposition pattern may be added to the above-mentioned ones. Namely, the first viahole groups may be disposed in a plane of matrix while the second viahole groups may be disposed in a matrix in areas where no first viahole groups are disposed. Alternatively, the first viahole groups may be disposed mainly in the central portion of a substrate while the second viahole groups may be disposed around the substrate (as in  FIG. 8A ). 
     Note that in  FIG. 5 to 8 , the first viahole groups are indicated with a small circle (∘) and the second viahole groups are indicated each with a crisscross (×) but the viahole groups (first groups, for example) may be displaced in other groups&#39; (second groups, for example) positions. The first and second viahole groups may be equal or different in diameter to or from each other. 
     There will be described in detail below one example of the method of producing a multilayer printed wiring board as one embodiment of the present invention. 
     (1) A starting material for producing the multilayer printed wiring board as the embodiment of the present invention may be a circuit board used as a basic unit for the multilayer printed wiring board and having attached a copper foil on one or either side of an insulating substrate thereof. 
     The insulating substrate is a rigid one selected from among, for example, glass cloth-based epoxy resin, glass cloth-based bismaleimide triazine resin, glass cloth-based polyphenylene ether resin, aramid unwoven cloth-based epoxy resin, aramid unwoven cloth-based polyimide resin, etc. The most desirable one is the glass cloth-based epoxy resin substrate. 
     The insulating substrate should desirably be about 100 μm or less in thickness. Also, the insulating substrate may be about 50 μm or less in thickness. 
     According to the present invention, a hole for forming a viahole may be formed by lasering in the circuit board by either a direct lasering method in which lasering is made to form a hole through a copper foil and insulating substrate at a time or a conformal method in which a copper foil is etched to remove a portion thereof corresponding to a viahole and then a hole is formed by lasering in the insulating substrate. 
     The copper foil attached over the insulating substrate should desirably be about 5 to about 20 μm in thickness. 
     The above range of the copper foil thickness assures that the end face of the copper foil in the position of a viahole will not be deformed when a hole for the viahole is formed in the insulating substrate, a conductor circuit having a predetermined shape can easily be formed and a circuit board pattern having fine line width can easily be formed by etching. 
     The copper foil may be adjusted in thickness by a half etching. In this case, the copper foil thickness may be larger than the above and the thickness of the etched copper foil is adjusted to within the above range. 
     Also, in case a double-side copper-clad laminate is used as the circuit board, the copper thickness may be within the above range but the copper foil may be different in thickness from one side to the other of the circuit board as long as the thickness is within that range, whereby it is possible to proceed with subsequent steps of the manufacturing process smoothly. 
     The circuit board should preferably be formed from a single- or double-sided copper-clad laminate produced by hot-pressing of a stack of a copper foil and a B-stage prepreg as an insulating substrate formed by impregnating epoxy resin into a glass cloth. 
     The reason for the above is that the wiring pattern and viaholes can accurately be positioned without displacement thereof in subsequent steps of the manufacturing process after the copper foil is etched. 
     (2) Next, holes for viaholes are formed by lasering in the insulating substrate. 
     In case a single-sided copper-clad laminate is used to form a circuit board, the surface of the insulating substrate opposite to the side where the copper foil is attached is irradiated with carbon dioxide laser to form a hole through the insulating substrate to the copper foil (or conductor circuit pattern). 
     In case a double-sided copper-clad laminate is used to form the circuit board, the surface of the insulating substrate opposite to the side where the copper foil is attached is irradiated with carbon dioxide laser to form a hole through both the copper foil and insulating substrate to the copper foil (or conductor circuit pattern) attached on the other side of the insulating substrate, or a hole smaller in diameter than the viahole is formed by etching in the one side of the copper foil attached on the insulating layer and then carbon dioxide laser is irradiated to the smaller hole to form a hole through the insulating substrate to the copper foil (or the conductor circuit pattern) attached on the other side of the insulating substrate. 
     The lasing is done with the use of a pulse oscillation type carbon dioxide lasering unit for the side wall of the viahole hole to bulge in a direction generally orthogonal to the direction of thickness of the insulating layer so that the diameter of a central portion of the side wall, whose bulging will be largest, is about 110 to about 150% of the diameter of the viahole-forming hole (smallest hole diameter). 
     The lasing may be made with, for example, a pulse energy of about 0.5 to about 100 mJ, pulse width of about 1 to about 100 μs, pulse interval of about 0.5 ms or more, frequency of about 2000 to about 3000 Hz, and 2 to 10 shots, and with a laser under these conditions within this range, the extent of bulging of the side walls of the hole can be adjusted. 
     The viahole-forming hole that can be formed under the above lasering conditions should preferably be about 50 to about 250 μm in diameter. With the hole diameter being within this range, it is possible to positively bulge the side wall of the hole and increase a high density of wiring. 
     (3) The above laminate may be subjected to desmearing in order to remove resin residues from on the side walls and bottom of the hole formed in step (2) above. 
     The desmearing may be made by wet processing with acid or oxidizing agent (e.g., chromic acid or permanganic acid) or dry processing such as oxygen plasma discharge, corona discharge, ultraviolet lasering, excimer lasering or the like. 
     Any one of the above desmearing methods is selected with consideration given to a possible amount of residual smear that can be determined based on the type and thickness of the insulating substrate, diameter of the viahole-forming hole, lasering conditions, etc. 
     By reducing the tact time from completion of the lasering until start of the desmearing (for example, to less than 1 hour from completion of the lasering) or by desmearing in any other way, it is possible to positively form the viahole in the barrel shape (bulging in a direction generally orthogonal to the direction of thickness of the insulating layer). 
     (4) Next, the surface of the copper foil on the desmeared insulating substrate is electrolytically plated with the copper foil being used as a plating lead to fill electrolytic copper into the hole to the full extent, to thereby form a viahole (filled via). 
     Note that after the electrolytic-copper plating, the electrolytic copper plate protuberant on the upper portion of the viahole in the insulating substrate may be removed and flattened by belt sanding, buffing, etching or the like as the case may be. 
     Also, after the copper foil is electroless-plated, it may be subjected to electrolytic plating. In this case, the copper foil may be electroless-plated with copper, nickel or silver. 
     (5) Next, an etching resist layer is formed over the electrolytic-copper coating on the insulating substrate in the step (4) above. The etching resist layer may be formed either by applying a resist liquid or by attaching a pre-formed film of the resist liquid. A mask having a circuit pattern pre-depicted thereon is mounted on the resist layer, an etching resist layer is formed by exposing and developing the resist layer, and the metal layer in an area other than the area where the etching resist layer is not formed is etched to form a conductor circuit pattern including a conductor circuit and land. 
     The etchant used in the above processing should desirably be at least one selected from among aqueous solutions of sulfuric acid-hydrogen peroxide, persulfate, cupric chloride and ferric chloride. 
     To easily form a fine conductor circuit pattern prior to forming a conductor circuit by etching the copper foil and electrolytic-copper coating, the electrolytic-copper coating may be pre-adjusted in thickness by etching the entire surface of the coating. 
     The land as a part of the conductor circuit should desirably be formed to have an inside diameter generally equal to the viahole diameter or to have an outside diameter larger than the viahole diameter, so that the land diameter will be within a range of about 75 to about 350 μm. The reason for the above is that with the land diameter being within the above range, the multistage stacked vias can perform its specified function even if the viaholes are displaced in relation to each other. 
     An insulating resin layer and copper foil are stacked on one side or either side of the circuit board formed through the above steps (1) to (5) and which functions as the core of stacking. Thus, the circuit board will include one or two more insulating resin layers. 
     A viahole and conductor circuit are formed on the stacked insulating resin layers through similar steps to the above steps (2) to (5), and with an insulating resin layer and copper foil being stacked on the conductor layer, steps similar to the above steps (2) to (5) can be repeated to form a printed wiring board including further layers. 
     In the aforementioned method, the insulating resin layers are stacked sequentially to form a multilayer insulating resin layer structure. However, two or more circuit boards each including one insulating resin layer may collectively be stacked and hot-pressed to form a multilayer printed wiring board. 
     In the multilayer printed wiring board formed as above, the viahole formed in each of the stacked circuit boards or insulating resin layers is formed for a part thereof at a half thickness of the insulating layer to be larger in diameter than parts thereof exposed at the top and bottom of the insulating layer, namely, the viahole is formed to have a barrel shape. The viaholes formed in at least one or more insulating resin layers including a circuit board as the core of stacking form together a first group while those formed in at least one or more other insulating resin layers stacked together oppositely to the insulating resin layers in which the viaholes in the first group are formed form together a second group. These first and second viahole groups form together a multistage stacked vias. 
     (6) Next, a solder resist layer is formed over the surface of each of the outermost circuit boards. In this case, a solder resist composition is coated over the outer surface of the circuit board, the coating is dried, a photo mask having depicted thereon a hole for a solder pad is mounted on the dried coating, and the solder resist is exposed and developed to form a solder pad hole in which there is exposed a conductive pad portion positioned just above the viahole in the conductor circuit. In this case, a dry film of a solder resist is attached over the solder resist coating, exposed and developed or irradiated with laser light to form the solder-pad hole. 
     A corrosion-resistant layer of nickel, gold or the like is formed on the solder pad exposed in an area where the photomask is not formed. When it is formed from nickel-gold, the nickel layer should desirably be about 1 to about 7 μm in thickness while the gold layer should desirably be about 0.01 to about 0.1 μm in thickness. The corrosion-resistant layer may be formed from a nickel-palladium-gold alloy, gold, copper or the like in addition to the nickel-gold. 
     After the corrosion-resistant layer is formed, the mask layer is peeled off. Thus, a printed wiring board is provided which includes the solder pad having the corrosion-resistant layer formed thereon and the solder pad having no such corrosion-resistant layer formed thereon. 
     (7) Solder is supplied from the hole in the solder resist layer formed in the above step (6) to the solder pad exposed just above the viahole, melted and solidified to form a solder bump, or a conductive ball or conductive pin is joined to the solder pad with the use of a conductive adhesive or solder layer to form a multilayer circuit board. 
     The solder and solder layer may be supplied by solder transfer or printing. 
     The solder transfer is such that a solder foil is attached to over a prepreg and etched with leaving only a portion corresponding to a hole to form a solder pattern and thus a solder carrier film, a flux is applied to the hole in the solder resist on the circuit board, then the solder carrier film is stacked for the solder pattern to touch the solder pad, and it is heated for transfer of the solder. 
     On the other hand, the solder printing is such that a printing mask (metallic one) having a hole formed therein in a position corresponding to a solder pad is placed on the circuit board and then a solder past is printed and heated. The solder use to form such a solder bump may be an Sn—Ag solder, Sn/In solder, Sn/Zn solder or Sn/Bi solder. 
     Example 1 
     (1) First, there is produced a circuit board as one unit included in a multilayer printed wiring board. The circuit board is the core of stacking a plurality of insulating layers which are to be stacked together. For producing such a circuit board, copper foils and a B-stage prepreg prepared by impregnating epoxy resin into a glass cloth are stacked together and hot-pressed to form a double-sided copper-clad laminate which is to be used as a starting material (as in  FIG. 9A ). 
     The prepreg or insulating substrate  12  is 60 μm in thickness and copper foils  14  are 12 μm in thickness. The copper foil  14  may be more than 12 μm in thickness. In this case, the copper foil  14  is adjusted by etching to have a thickness of 12 μm. 
     (2) The double-sided copper-clad laminate  10  including the copper foils  14  is irradiated with carbon dioxide laser to form a viahole-forming hole  16  through one of the copper foils  14  and insulating substrate  12  to the copper foil  14  on the other side of the insulating substrate  12 , and then the hole formed by the lasering is desmeared, within one hour after completion of the lasering, by chemical processing with permanganic acid (as in  FIG. 9B ). 
     Note that in this Example, the viahole-forming hole  16  is formed using a high-peak short-pulse oscillation type carbon dioxide lasering unit (by the Hitachi Via). A copper foil on a glass cloth-based epoxy resin substrate of 60 μm in thickness having a 12 μm-thick copper foil attached thereon is irradiated directly with a laser beam under the following conditions to form a hole  16  of 75 μm in diameter at a speed of 100 holes/sec. 
     
       
         
               
             
               
               
               
             
           
               
                   
               
               
                 (Laser conditions) 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 Pulse energy: 
                 0.5 to 100 mJ 
               
               
                   
                 Pulse width: 
                 1 to 100 μs 
               
               
                   
                 Pulse interval: 
                 0.5 ms or more 
               
               
                   
                 Number of shots: 
                 2 
               
               
                   
                 Oscillating frequency: 
                 2000 to 3000 Hz 
               
               
                   
                   
               
             
          
         
       
     
     The hole  16  thus formed under the above conditions has an inner wall formed as a barrel shape which bulges in a direction generally orthogonal to the direction of thickness of the insulating layer so that the diameter of a part of the hole  16  at a half thickness of the insulating layer is 1.2 times larger than that of parts thereof exposed at the top and bottom of the insulating layer. 
     (3) The surface of the copper foil  14  having the desmeared viahole-forming hole  16  formed therein is electrolytically plated with the copper foil  14  being taken as a plating lead and under the following electrolytic plating conditions to form an electrolytic copper plated film (as in  FIG. 9C ). 
     
       
         
               
             
               
               
               
               
             
               
             
               
               
               
               
             
               
               
               
             
           
               
                   
               
             
             
               
                 (Electrolytic plating solution) 
               
             
          
           
               
                   
                 Sulfuric acid: 
                 2.24 
                 mol/l 
               
               
                   
                 Copper sulfate: 
                 0.26 
                 mol/l 
               
               
                   
                 Additive A (reaction promoter): 
                 10.0 
                 ml/l 
               
               
                   
                 Additive B (reaction inhibitor): 
                 10.0 
                 ml/l 
               
             
          
           
               
                 (Electrolytic plating conditions) 
               
             
          
           
               
                   
                 Current density: 
                 1 
                 A/dm 2   
               
               
                   
                 Time: 
                 65 
                 min 
               
             
          
           
               
                   
                 Temperature: 
                 22 ± 2° C. 
               
               
                   
                   
               
             
          
         
       
     
     The electrolytic copper plating in the viahole-forming hole is promoted by the additive A while the electrolytic copper plated film mainly on the copper foil is inhibited by the additive B from being formed. Also, when the electrolytic copper is fully filled in the viahole-forming hole up to nearly the same level as the surface of the copper foil  14 , the additive B will adhere to the copper foil  14  to inhibit the electrolytic copper plated film from being formed as on the copper foil. 
     Thus, there is formed a viahole  20  having the electrolytic copper filled in the hole  16  so that the surface of the viahole  20  will be nearly flush with the copper foil surface. 
     Also, the conductor layer of the copper foil  14  and electrolytic copper plated film may be adjusted in thickness by etching. The thickness of the conductor layer may be adjusted in thickness by a physical method such as the sand-belt polishing or buffing. 
     (4) At either side of the circuit board formed as in the step (3) above, a dry film of a photoresist is formed to a thickness of 15 to 20 μm on the conductor layer of the copper foil  14  and electrolytic copper plated film. A mask having depicted thereon a conductor circuit including a viahole land is mounted on the resist film, and the resist film is exposed and developed to form an etching resist layer  22  (as in  FIG. 9D ). The copper foil  14  and electrolytic copper plated film exposed in a portion where the etching resist is not formed are dissolved and removed by etching with an etching solution of hydrogen peroxide liquid/sulfuric acid. 
     (5) Thereafter, the etching resist layer  22  is peeled using an alkaline solution to form a pattern  24  of a conductor circuit including a viahole land. Thus, there is formed a viahole  20  electrically connecting the conductor circuits on both the front and rear sides of the circuit board to each other to provide a circuit board in which the viahole  20  and a copper foil portion forming the conductor circuit  24  are flat (as in  FIG. 9E ). 
     (6) At the front and rear sides of the circuit board formed through the above steps (1) to (5), there are superposed a 60 μm-thick B-stage prepreg prepared by impregnating epoxy resin into a glass cloth and 12 μm-thick copper foils. The prepreg and copper foils are hot-pressed at a temperature of 80 to 250° C. and under a pressure of 1.0 to 5.0 kgf/cm 2  to stack 60 μm-thick insulating resin layers  26  and 12 μm-thick conductor layers  28  on the circuit board (as in  FIG. 10A ). 
     (7) Next, nearly as in the step (2) above, the circuit board is irradiated at either side thereof with carbon dioxide laser under the following conditions to form a 85 μm-diameter viahole-forming hole  30  through the insulating resin layer  26  and conductor layer  28  to the lower conductor circuit  24  at a speed of 100 holes/sec. Then, the hole formed by the lasering is desmeared by chemical processing with permanganic acid (as in  FIG. 10B ). 
     
       
         
               
             
               
               
               
             
           
               
                   
               
               
                 (Laser conditions) 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 Pulse energy: 
                 0.5 to 100 mJ 
               
               
                   
                 Pulse width: 
                 1 to 100 μs 
               
               
                   
                 Pulse interval: 
                 0.5 ms or more 
               
               
                   
                 Number of shots: 
                 2 
               
               
                   
                 Oscillating frequency: 
                 2000 to 3000 Hz 
               
               
                   
                   
               
             
          
         
       
     
     The hole  30  thus formed under the above conditions has an inner wall formed as a barrel shape which bulges in a direction generally orthogonal to the direction of thickness of the insulating layer so that the diameter of a part of the hole  30  at a half thickness of the insulating layer is 1.2 times larger than that of parts thereof exposed at the top and bottom of the insulating layer. 
     (8) Nearly as in the step (3) above, the conductor layer  28  at the side of the desmeared viahole-forming hole is electrolytically plated under the following electrolytic plating conditions to form an electrolytic copper plated film  32  (as in  FIG. 10C ): 
     
       
         
               
             
               
               
               
               
             
               
             
               
               
               
               
             
               
               
               
             
           
               
                   
               
             
             
               
                 (Electrolytic plating solution) 
               
             
          
           
               
                   
                 Sulfuric acid: 
                 2.24 
                 mol/l 
               
               
                   
                 Copper sulfate: 
                 0.26 
                 mol/l 
               
               
                   
                 Additive A (reaction promoter): 
                 10.0 
                 ml/l 
               
               
                   
                 Additive B (reaction inhibitor): 
                 10.0 
                 ml/l 
               
             
          
           
               
                 (Electrolytic plating conditions) 
               
             
          
           
               
                   
                 Current density: 
                 1 
                 A/dm 2   
               
               
                   
                 Time: 
                 65 
                 min 
               
             
          
           
               
                   
                 Temperature: 
                 22 ± 2° C. 
               
               
                   
                   
               
             
          
         
       
     
     Thus, a viahole  34  having an electrolytic copper  32  filled in the hole  30  is formed so that the surface of the viahole  34  will generally be flush with the copper foil surface. 
     (9) Nearly as in the step (4) above, a dry film of a photoresist is formed to a thickness of 15 to 20 μm on the electrolytic copper plated layer formed in the above step (8). A mask having depicted thereon a conductor circuit, land of the viahole  34 , etc. is mounted on the resist film, the circuit boards are positioned and the resist film is exposed and developed to form an etching resist layer  36  (as in  FIG. 10D ). 
     Thereafter, the copper plated film and copper foil corresponding to a portion where the etching resist is not formed are removed by etching with an etching solution of hydrogen peroxide liquid/sulfuric acid. 
     (10) Next, the etching resist layer  36  is peeled using an alkaline solution to form a conductor circuit  38  including the viahole  34  and land of the latter. Thus, there is formed a circuit board in which the viahole  34  electrically connecting both the front and rear sides of the circuit board to each other and a copper foil portion forming the conductor circuit  38  are flat (as in  FIG. 10E ). 
     Further, the above steps (6) to (10) are repeated to form one more insulating resin layer  40 , an electrolytic copper is filled by plating into a hole formed in the insulating resin layer  40  to form a viahole  42  and also a conductor circuit pattern  44  including a viahole land. Thus, there can be provided a multilayer printed wiring board in which two insulating layers and conductor circuits are formed on either side of the double-sided circuit board  10  (as in  FIG. 11 ). 
     More specifically, the multilayer printed wiring board includes five insulating layers and six conductor circuits. In this multilayer printed wiring board, each of the viaholes formed in the double-side circuit board and two insulating layers stacked on the upper side of the double-sided circuit board has a barrel-shaped inner wall bulged in a direction generally orthogonal to the direction of thickness of the insulating layer and of which the intermediate part, bulged largest, is 1.2 times larger in diameter than parts exposed at the top and bottom of the insulating layer. These viaholes form together a first group. The viaholes formed in the two insulating layers stacked on the lower side of the double-sided circuit board are also formed similarly to the viaholes in the first group, and form together a second group. These first and second viahole groups are disposed opposite to each other and stacked on almost same straight lines, respectively. 
     (11) A solder resist layer  46  is formed on the surface of each of two insulating layers on the outermost sides, respectively, of the circuit board formed in the step (10) above to form a solder resist layer  46 . 
     First, a film-shaped solder resist of 20 to 30 μm in thickness is attached on the insulating layer having the conductor circuit  38  formed thereon. Next, the insulating layer is dried at 70° C. for 20 min and then at 100° C. for 30 min, and then a 5 mm-thick soda lime glass substrate having depicted thereon, with a chrome layer, a circle pattern (mask pattern) for a hole in the solder resist is attached at the side thereof having the chrome layer closely to the solder resist layer  46 , exposed to ultraviolet rays of 1000 mJ/cm 2  and DMTG-developed. 
     Further, the above assembly is heated at 120° C. for 1 hour and then at 150° C. for 3 hours to form a 20 μm-thick solder resist layer  46  having a hole  48  (200 μm in diameter) corresponding to a pad (as in  FIG. 12A ). 
     Before the solder resist layer  46  is formed over the surface of the outermost insulating layer of the multilayer printed wiring board, a roughed-surface layer may be provided as necessary. 
     (12) Next, the circuit board having the solder resist layer  46  formed thereon is immersed in an electroless nickel plating solution containing 30 g/l of nickel chloride, 10 g/l of nickel chloride, 10 g/l of sodium hypophosphite and 10 g/l of sodium citrate and having a pH value of 5 for 20 min to form a 5 μm-thick nickel plated layer on the surface of the conductor circuit  38  exposed from the hole  48 . 
     Further, the circuit board is immersed in an electroless nickel plating solution containing 2 g/l of potassium gold cyanide, 75 g/l of ammonium chloride, 50 g/l of sodium citrate and 10 g/l of sodium hypophosphite at 93° C. for 23 sec to form a 0.03 μm-thick gold plated layer on the nickel plated layer, to thereby form a conductor pad  50  covered with a metal layer consisting of the nickel and gold plated layers. 
     (13) Then, with a metal mask being mounted on the solder resist layer  46 , a solder paste of Sn/Pb or Sn/Ag/Cu having a melting point T 2  of 183° C. is printed. The metal mask is removed from on the solder resist layer  46 , and then the solder paste is subjected to reflowing at a temperature of about 183° C. to provide a multilayer printed wiring board having a solder layer  52  formed on the conductor pad  50  exposed in the hole  48  (as in  FIG. 12B ). 
     Next, mainly electronic components such as a capacitor, resistor and the like are mounted in an area where the solder layer  52  is formed, and external terminals such as a key pad and the like are mounted in an area where the solder layer  52  is not formed. Thus, a multilayer printed wiring board is provided. 
     Example 2 
     A multilayer printed wiring board is produced generally similarly to the Example 1 except that each of the viaholes included in the first and second viahole groups formed in the insulating layers, respectively, stacked on the front and rear sides, respectively, of the double-sided copper-clad laminate are shifted about a half of the viahole diameter from each other as shown in  FIG. 3A . 
     Example 3 
     A multilayer printed wiring board is produced generally similarly to the Example 1 except that each of the viaholes included in the first viahole group formed in the insulating layer stacked on the upper side of the double-side copper-clad laminate and those included in the second viahole group formed in the insulating layer stacked on the lower side of the double-sided copper-clad laminate are shifted about a half of the viahole diameter from each other, as shown in  FIG. 3B . 
     Example 4 
     A multilayer printed wiring board is produced generally similarly to the Example 1 except that two insulating layers are stacked on the upper side of the double-sided copper-clad laminate while one insulating layer is stacked on the lower side of the double-sided copper-clad laminate so that four insulating layers and five conductor circuits are formed. 
     Example 5 
     A multilayer printed wiring board is produced generally similarly to the Example 2 except that two insulating layers are stacked on the upper side of the double-sided copper-clad laminate while one insulating layer is stacked on the lower side of the double-sided copper-clad laminate so that four insulating layers and five conductor circuits are formed. 
     Example 6 
     A multilayer printed wiring board is produced generally similarly to the Example 3 except that two insulating layers are stacked on the upper side of the double-sided copper-clad laminate while one insulating layer is stacked on the lower side of the double-sided copper-clad laminate so that four insulating layers and five conductor circuits are formed. 
     Example 7 
     A multilayer printed wiring board is produced generally similarly to the Example 1 except that the first viahole group formed in the insulating layers stacked on the double-sided copper-clad laminate and on the upper side of the latter is horizontally shifted generally a half of the viahole diameter from the second viahole group formed in the insulating layers stacked on the lower side of the double-sided copper-clad laminate, as shown in  FIG. 4 . 
     Example 8 
     A multilayer printed wiring board is produced generally similarly to the Example 7 except that two insulating layers are stacked on the upper side of the double-sided copper-clad laminate while one insulating layer is stacked on the lower side of the double-sided copper-clad laminate so that four insulating layers and five conductor circuits are formed. 
     Example 9 
     A multilayer printed wiring board is produced generally similarly to the Example 4 except that the viaholes are stacked together for those included in the first group to be positioned at two opposite apexes of an imaginary tetragonal lattice (lattice interval: 10 mm) on the insulating substrate and those included in the second group to be positioned at two other opposite apexes of the imaginary tetragonal lattice on the insulating substrate as shown in  FIG. 5A . 
     Example 10 
     A multilayer printed wiring board is produced generally similarly to the Example 4 except that the viaholes are stacked together for those included in the first group to be positioned at the respective apexes of an imaginary tetragonal lattice (lattice interval: 10 mm) on the insulating substrate and those included in the other group to be positioned at the center of the imaginary tetragonal lattice as shown in  FIG. 5B . 
     Example 11 
     A multilayer printed wiring board is produced generally similarly to the Example 4 except that the viaholes are stacked together for those included in the first group to be positioned at the respective apexes of an imaginary triangular lattice (lattice interval: 20 mm) on the insulating substrate and those included in the second group to be positioned at the center of the imaginary triangular lattice, as shown in  FIG. 6 . 
     Example 12 
     A multilayer printed wiring board is produced generally similarly to the Example 4 except that the viaholes included in the first group are positioned nearly at the center of the insulating substrate and concentrically disposed in an area of 40×40 mm and those included in the second group are positioned outside the central area of a peripheral area (40×40 mm) surrounding the central portion and inside an area of 70×100 mm, as shown in  FIG. 8A . 
     INDUSTRIAL APPLICABILITY 
     As having been described in the foregoing, even if the multilayer printed wiring board according to the present invention is dropped, the external stress and warp of the insulating layers due to an applied impact can be suppressed. So, the present invention can provide a multilayer printed wiring board of which the conductor circuits can be prevented from being cracked and opened, so that a printed circuit board including the multilayer printed wiring board can be prevented from being less reduced in reliability and drop-shock resistance.