Abstract:
A two-level two-terminal modular multilevel converter subsystem. The subsystem includes a first capacitor and a second capacitor. The modular multilevel converter subsystem is configured to selectively place the first capacitor in series with the second capacitor. The modular multilevel converter subsystem is also configured to selectively place the first capacitor in parallel with the second capacitor relative to first and second output terminals of the modular multilevel converter subsystem.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the benefit under 35 U.S.C. §119(e) of the earlier filing date of U.S. Provisional Patent Application No. 61/384,853 filed on Sep. 21, 2010. 
    
    
     BACKGROUND 
     This application discloses an invention which is related, generally and in various embodiments, to a two-terminal modular multilevel converter (M2LC) subsystem, and a M2LC system including a plurality of M2LC subsystems (cells). 
     Many papers have been published regarding the Modular Multilevel Converter (M2LC) topology.  FIGS. 1 and 2  illustrate different two-level configurations of a two-terminal M2LC cell. In many instances, the M2LC cells shown in  FIGS. 1 and 2  are packaged as a single three-level M2LC cell having two terminals as shown in  FIG. 3 . 
     As shown in  FIG. 1 , the M2LC cell includes two switching devices (Q 1  and Q 2 ), two diodes, a capacitor (C 1 ) and two terminals. With the configuration shown in  FIG. 1 , the two switching devices can be controlled such that one of two different potentials may be present across the two terminals of the M2LC cell. The two different potentials are (1) zero volts and (2) V C1  which is the voltage present on storage capacitor C 1 . If switching device Q 2  is turned on, zero volts are present between the two terminals of the M2LC cell. If switching device Q 1  is turned on, the voltage V C1  is present between the two terminals of the M2LC cell. It will be appreciated that in order to avoid short circuiting of the storage capacitor C 1  and the significant damage likely to result therefrom, switching device Q 1  should be off when switching device Q 2  is on, and switching device Q 2  should be off when switching device Q 1  is on. 
     Similarly, as shown in  FIG. 2 , the M2LC cell includes two switching devices (Q 3  and Q 4 ), two diodes, a capacitor (C 2 ) and two terminals. With the configuration shown in  FIG. 2 , the two switching devices can be controlled such that one of two different potentials may be present across the two terminals of the M2LC cell. The two different potentials are (1) zero volts and (2) V C2  which is the voltage present on storage capacitor C 2 . If switching device Q 3  is turned on, zero volts are present between the two terminals of the M2LC cell. If switching device Q 4  is turned on, the voltage V C2  is present between the two terminals of the M2LC cell. It will be appreciated that in order to avoid short circuiting of the storage capacitor C 2  and the significant damage likely to result therefrom, switching device Q 3  should be off when switching device Q 4  is on, and switching device Q 4  should be off when switching device Q 3  is on. 
     As shown in  FIG. 3 , the three-level M2LC cell includes four switching devices (Q 1 , Q 2 , Q 3  and Q 4 ), four diodes, two capacitors (C 1  and C 2 ) and two terminals. It will be appreciated that capacitors C 1  and C 2  are typically identical for this arrangement. With the configuration shown in  FIG. 3 , the four switching devices can be controlled such that one of three different potentials may be present across the two terminals of the M2LC cell. The three different potentials are (1) zero volts, (2) V C1  which is the voltage present on storage capacitor C 1  or V C2  which is the voltage present on storage capacitor C 2 , and (3) V C1 +V C2  which is the sum of the voltages present on storage capacitors C 1  and C 2 . Because the two storage capacitors C 1  and C 2  are typically sized the same, it will be appreciated that the voltages V C1  and V C2  are substantially identical, and the voltage V C1 +V C2  is substantially identical to either 2V C1  or 2V C2 . 
     For the M2LC cell of  FIG. 3 , if switching devices Q 2  and Q 3  are both turned on, zero volts are present between the two terminals of the M2LC cell. If switching devices Q 1  and Q 3  are both turned on, the voltage V C1  is present between the two terminals of the M2LC cell. If switching devices Q 2  and Q 4  are both turned on, the voltage V C2  is present between the two terminals of the M2LC cell. If switching devices Q 1  and Q 4  are both turned on, the voltage V C1 V C2  is present between the two terminals of the M2LC cell. It will be appreciated that the independent control of the two voltage states V C1  and V C2  allow for the balancing of the charges on capacitors C 1  and C 2 . It should also be apparent to those skilled in the art of this topology that the functionality of the M2LC cell of  FIG. 3  may be realized by connecting the two-level M2LC cells of  FIGS. 1 and 2  in series so that the emitter connection of the switching device Q 2  of the two-level M2LC cell of  FIG. 1  is connected to the collector connection of the switching device Q 3  of the two-level M2LC cell of  FIG. 2  if the switch functions applied to switching devices Q 1 , Q 2 , Q 3 , and Q 4  are identical. The advantage of the M2LC cell of  FIG. 3  is primarily packaging and minimization of control since it is possible for this M2LC cell to share a single controller (not shown) as opposed to two independent controllers required for each of the M2LC cells of  FIGS. 1 and 2 . 
     It will be appreciated that the M2LC topology possesses the advantages of the Cascaded H Bridge (CCH) topology in that it is modular and capable of high operational availability due to redundancy. Additionally, the M2LC topology can be applied in common bus configurations with and without the use of a multi-winding transformer. In contrast to M2LC, CCH requires the utilization of a multi-winding transformer which contains individual secondary windings which supply input energy to the cells. 
     However, unlike CCH, the M2LC cells (or subsystems) are not independently supplied from isolated voltage sources or secondary windings. For a given M2LC cell, the amount of energy output at one of the two terminals depends on the amount of energy input at the other one of the two terminals. 
     Multiple M2LC cells have previously been arranged in a traditional bridge configuration. For such configurations, the M2LC cells are arranged into two or more output phase modules, each output phase module includes a plurality of series-connected M2LC cells, and each output phase module is further arranged into a positive arm (or valve) and a negative arm (or valve), where each arm (or valve) is separated by an inductive filter. Each output phase module may be considered to be a pole. The outputs of the respective output phase modules may be utilized to power an alternating current load such as, for example, a motor. 
     Although the M2LC cell arrangements described hereinabove have proven to be useful, the arrangements are not necessarily optimal for all potential applications. Additionally, from a size and cost standpoint, utilizing two identical storage capacitors to realize the respective voltage states adds more size and cost to the M2LC cells than is necessary. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Various embodiments of the invention are described herein in by way of example in conjunction with the following figures, wherein like reference characters designate the same or similar elements. 
         FIG. 1  illustrates a two-level configuration of an M2LC cell having two terminals; 
         FIG. 2  illustrates another two-level configuration of an M2LC cell having two terminals; 
         FIG. 3  illustrates a three-level configuration of an M2LC cell having two terminals; 
         FIG. 4  illustrates various embodiments of a two-level configuration of an M2LC subsystem having two terminals; 
         FIG. 5  illustrates various embodiments of a three-level configuration of an M2LC subsystem having two terminals; and 
         FIG. 6  illustrates various embodiments of a M2LC system. 
     
    
    
     DETAILED DESCRIPTION 
     It is to be understood that at least some of the figures and descriptions of the invention have been simplified to illustrate elements that are relevant for a clear understanding of the invention, while eliminating, for purposes of clarity, other elements that those of ordinary skill in the art will appreciate may also comprise a portion of the invention. However, because such elements are well known in the art, and because they do not facilitate a better understanding of the invention, a description of such elements is not provided herein. 
       FIG. 4  illustrates various embodiments of a two-level configuration of an M2LC subsystem  10  having two terminals. The M2LC subsystem  10  includes three switching devices (Q 1 , Q 2  and Q 3 ), three diodes, two capacitors (C 1  and C 2 ) and two terminals. The switching devices Q 1 -Q 3  may be embodied as any suitable type of switching devices. For example, according to various embodiments, the switching devices Q 1 -Q 3  are embodied as insulated gate bipolar transistors. According to various embodiments, switching devices Q 1 -Q 3  can be configured with two dual insulated gate bipolar transistors such that the top of one pair and the bottom of the other pair are paralleled to form switching device Q 2 . Because switching device Q 2  conducts more average current than either switching device Q 1  or switching device Q 3 , this arrangement allows for “standard” insulated gate bipolar transistors to be utilized to safely handle the higher current associated with switching device Q 2 . 
     With the configuration shown in  FIG. 4 , the three switching devices Q 1 -Q 3  can be selectively controlled such that one of two different potentials may be present across the two terminals of the M2LC subsystem  10 . The two different potentials are (1) zero volts and (2) V C1  which is the voltage present on storage capacitor C 1  or V C2  which is the voltage present on storage capacitor C 2 . If switching device Q 2  is turned on (and switching devices Q 1  and Q 3  are off), zero volts are present between the two terminals of the M2LC subsystem  10 . Also, if switching device Q 2  is turned on, the storage capacitors C 1  and C 2  are physically connected in series (but not with respect to the two output terminals). If switching devices Q 1  and Q 3  are both turned on (and switching device Q 2  is off), the voltage present between the two terminals is the voltage V C1  or the voltage V C2 . The voltages V C1  and V C2  are or will quickly become equal since the storage capacitors C 1  and C 2  are connected in parallel with respect to the two output terminals. In contrast to the storage capacitors C 1  and C 2  of the M2LC cells of  FIGS. 1 and 2 , it will be appreciated that the output current of the M2LC subsystem  10  is shared substantially equally by the storage capacitors C 1  and C 2  of the M2LC subsystem  10  if switching devices Q 1  and Q 3  are on (and switching device Q 2  is off). According to various embodiments, capacitor C 1  is sized the same as the capacitor C 2 . 
       FIG. 5  illustrates various embodiments of a three-level configuration of an M2LC subsystem  20  having two terminals. The M2LC subsystem  20  includes four switching devices (Q 1 , Q 2 , Q 3  and Q 4 ), four diodes, two capacitors (C 1  and C 2 ) and two terminals. In contrast to the two equal size storage capacitors of the M2LC cell shown in  FIG. 3 , the respective sizes of the two capacitors C 1  and C 2  of M2LC subsystem  20  are not the same. Capacitor C 1  is a storage capacitor which conducts the fundamental output current of the m2LC subsystem  20  and capacitor C 2  is a charge/pump capacitor or so-called “flying” capacitor which operates at the switching frequency of the switching devices Q 1 -Q 4  and hence sees only harmonic currents associated with the switching frequency. Flying capacitor C 2  does not conduct the fundamental output current and can be much smaller and less expensive than storage capacitor C 1 . 
     The switching devices Q 1 -Q 4  may be embodied as any suitable type of switching devices. For example, according to various embodiments, the switching devices Q 1 -Q 4  are embodied as insulated gate bipolar transistors. The four switching devices can be selectively controlled such that one of three different potentials may be present across the two terminals of the M2LC subsystem  20 . The three different potentials are (1) zero volts, (2) V C1  which is the voltage present on capacitor C 1 , and (3) V C2  which is the voltage present on capacitor C 2 . The voltage V C1  is double the voltage V C2  (i.e., V C1 =2V C2 ). The M2LC subsystem  20  can produce the potential V C2  in two different ways and can be independently controlled to balance charges on the two capacitors C 1  and C 2 . 
     The switching devices Q 1 -Q 4  of M2LC subsystem  20  can be controlled so that the voltage present on storage capacitor C 1  is V C1 , which is double the voltage V C2  which can be present on flying capacitor C 2 . The voltage on flying capacitor C 2  is controlled so that each switching device sees no more than V C2 . Stated differently, the voltage on flying capacitor C 2  is controlled so that each switching device sees no more than one-half of V C1 . To accomplish this, storage capacitor C 2  is controlled to voltage value V C2 . The M2LC subsystem  20  is arranged such that switching device Q 1  is a complement of switching device Q 2 , and switching device Q 3  is a complement of switching device Q 4 . 
     If switching devices Q 2  and Q 4  are both turned on, zero volts are present between the two terminals of the M2LC subsystem  20 . If switching devices Q 3  and Q 4  are both turned on, the voltage present on the flying capacitor C 2  (V C2 ) is present between the two terminals of the M2LC subsystem  20 . If switching devices Q 1  and Q 2  are both turned on, the voltage V C1-C2 , which is equal to the difference between the voltage V C1  and the voltage V C2  (i.e., V C1-C2 ), is present between the two terminals of the M2LC subsystem  20 . Since the voltage V C1  is double the voltage V C2 , the difference between voltage V C1  and voltage V C2  is equal to voltage V C2 . If switching devices Q 1  and Q 3  are both turned on, the voltage V C1  is present between the two terminals of the M2LC subsystem  20 . Since the voltage V C1  is double the voltage V C2 , it may also be stated that the voltage 2V C2  is present between the two terminals of the M2LC subsystem  20  if switching devices Q 1  and Q 3  are both turned on. In this way, the output voltage characteristic of the M2LC subsystem  20  of  FIG. 5  is essentially identical to the output voltage characteristic of the M2LC cell of  FIG. 3  in that it produces three voltage levels (e.g., zero volts, “v” volts (V C2 ) or “2 v” volts (V C1 )) with two independent switching modes to produce “v” volts but it does so using a single storage capacitor C 1  which conducts the fundamental output current produced at the output terminals of the M2LC subsystem  20 . 
       FIG. 6  illustrates various embodiments of a M2LC system  30 . The M2LC system  30  is configured as a three-phase bridge and includes a plurality of M2LC subsystems  32 , where the M2LC subsystems  32  are arranged as three output phase modules and each individual M2LC subsystem  32  is embodied as either the M2LC subsystem  10  or the M2LC subsystem  20  described hereinabove with respect to  FIGS. 4 and 5 . Although eighteen M2LC subsystems  32  are shown in  FIG. 6 , it will be appreciated that the M2LC system  30  may include any number of M2LC subsystems  32 . Of course, according to other embodiments, the M2LC system  30  may be configured differently than shown in  FIG. 6 . For example, the M2LC system  30  may be configured as two output phase modules. 
     For the M2LC system  30  of  FIG. 6 , the plurality of M2LC subsystems  32  are arranged as output phase modules. Each output phase module is further arranged into a positive arm (or valve) and a negative arm (or valve), where each arm (or valve) is separated by an inductive filter. According to other embodiments, for a given output phase module, in lieu of an inductive filter being connected between the positive arm and the negative arm of a the output phase module, one or more inductors may be distributed amongst the M2LC subsystems  32  of the arms of the output phase modules. Each output phase module may be considered to be a pole. Additionally, although not shown in  FIG. 6  for purposes of clarity, it will be appreciated that each M2LC subsystem  32  also includes a local controller, and each local controller may be communicably connected to a higher level controller (e.g., a hub controller) of the M2LC system  30 . 
     Nothing in the above description is meant to limit the invention to any specific materials, geometry, or orientation of elements. Many part/orientation substitutions are contemplated within the scope of the invention and will be apparent to those skilled in the art. The embodiments described herein were presented by way of example only and should not be used to limit the scope of the invention. 
     Although the invention has been described in terms of particular embodiments in this application, one of ordinary skill in the art, in light of the teachings herein, can generate additional embodiments and modifications without departing from the spirit of, or exceeding the scope of, the claimed invention. Accordingly, it is understood that the drawings and the descriptions herein are proffered only to facilitate comprehension of the invention and should not be construed to limit the scope thereof.