Abstract:
A packaged integrated circuit device includes a substrate module, leads, an IC die having first and second sets of die contact pads, and an encapsulant. The substrate module has upper and lower sets of conductive contacts on its upper and lower surfaces, respectively. The upper set of conductive contacts is electrically connected to the lower set of conductive contacts. The first set of die contact pads is electrically connected to the upper set of conductive contacts. The second set of die contact pads is electrically connected to the leads. Certain embodiments are a multi-form packaged device having both leads and conductive balls supporting different types of external connections, such as BGA and QFN.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to integrated circuit (IC) packaging and, more particularly, to a multi-form IC package. 
     There are many conventional types of IC packages. Most conventional IC packages include at least (i) an IC die, (ii) a conductive interface for electrically connecting the die to other electronic components, such as, for example, a printed circuit board (PCB), and (iii) an encapsulant enclosing the die to protect the die and keep the die attached to the conductive interface. The conductive interface is either a lead frame or a substrate with conductive traces. 
     Conventional package types include, for example, dual in-line package (DIP), quad flat-pack (QFP), quad flat-pack no-lead (QFN), ball-grid array (BGA), and pin-grid array (PGA). The selection of a particular package type for a particular application depends on multiple factors. Some applications require a relatively large number of input/output (I/O) interconnects for the IC device. For some of those applications, increasing the density of I/O interconnects can increase the utility of a chip but at the expense of production cost. As used herein, the term “chip” refers to a packaged, singulated, IC device. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects, features, and advantages of the invention will become fully apparent from the following detailed description, the appended claims, and the accompanying drawings in which like reference numerals identify similar or identical elements. Note that elements in the figures are not drawn to scale. 
         FIG. 1  is a simplified top view of a substrate plate that comprises a two-dimensional array of substrate modules; 
         FIG. 2  is a simplified magnified cross-sectional side view of the substrate module of  FIG. 1 ; 
         FIG. 3  is a simplified bottom view of the substrate plate of  FIG. 1 ; 
         FIG. 4  is a simplified top view of an assemblage comprising the substrate plate of  FIG. 1  and a lead frame array, following the attachment of the lead frame array to the top of the substrate plate; 
         FIG. 5  is a simplified top view of the assemblage of  FIG. 4  following the attachment of IC dies to the corresponding substrate modules; 
         FIG. 6  is a simplified enlarged cross-sectional side view of the substrate module, the corresponding lead frame module, and one of the attached IC dies of  FIG. 5 ; 
         FIG. 7  is a simplified top view of the assemblage of  FIG. 5  following the electrical connection—using bond wires—of the IC dies to the corresponding lead frame modules; 
         FIG. 8  is a simplified enlarged cross-sectional side view of the substrate module, the corresponding lead frame module, one of the attached IC dies, and the corresponding bond wires of  FIG. 7 ; 
         FIG. 9  is a simplified top view of the assemblage of  FIG. 7  following encapsulation with an encapsulant; 
         FIG. 10  is a simplified enlarged cross-sectional side view of the substrate module, the corresponding lead frame module, one of the attached IC dies, the corresponding bond wires, and the corresponding encapsulant of  FIG. 9 ; 
         FIG. 11  is a simplified top view of the multi-form chip resulting from the singulation of the assemblage of  FIG. 9 ; 
         FIG. 12  is a simplified enlarged cross-sectional side view of the multi-form chip of  FIG. 11 ; and 
         FIG. 13  is a perspective bottom view of the multi-form chip of  FIG. 11 . 
     
    
    
     DETAILED DESCRIPTION 
     Detailed illustrative embodiments of the present invention are disclosed herein. However, specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments of the present invention. Embodiments of the present invention may be embodied in many alternative forms and should not be construed as limited to only the embodiments set forth herein. Further, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments of the invention. 
     As used herein, the singular forms “a,” “an,” and “the,” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It further will be understood that the terms “comprises,” “comprising,” “has,” “having,” “includes,” and/or “including” specify the presence of stated features, steps, or components, but do not preclude the presence or addition of one or more other features, steps, or components. It also should be noted that, in some alternative implementations, the functions/acts noted may occur out of the order noted in the figures. 
     In one embodiment, an IC die is packaged so that the conductive interface comprises both an array of contact pads on the bottom and leads on the side of the chip. One implementation may be considered a combination of a modified QFN and a BGA package. 
       FIGS. 1-13  illustrate steps in the assembly of an exemplary multi-form chip  121  of  FIGS. 11, 12, and 13 , in accordance with one embodiment of the invention. The assembly process includes lead frame stacking, die mounting, wire bonding, encapsulation, and singulation. 
       FIG. 1  is a simplified top view of a substrate plate  100 , which comprises a two-dimensional array of ten substrate modules  101 .  FIG. 2  is a simplified magnified cross-sectional side view of one of the substrate modules  101  of  FIG. 1  along the cut-line YY. The substrate module  101  of  FIG. 2  is representative of all of the substrate modules  101 .  FIG. 3  is a simplified bottom view of the substrate plate  100  of  FIG. 1 . Each substrate module  101  comprises corresponding substrate material  102 . The substrate plate  100  also comprises a substrate material periphery  104 . Substrate materials  102  and  104  may be, for example, an epoxy-based material. The substrate plate  100  may be, for example, a conventional substrate plate designed for assembling BGA packages. 
     The substrate module  101  comprises corresponding substrate material  102 . As shown in  FIGS. 1 and 2 , the substrate module  101  has a six-by-six array of thirty-six upper contact pads  103  on the top surface  106  of the substrate material  102 . As shown in  FIGS. 2 and 3 , the substrate module  101  has a corresponding six-by-six array of thirty-six lower contact pads  105  on the bottom surface  107  of the substrate material  102 . 
     The upper contact pads  103  are designed for the attachment of an IC die with conductive balls such as bonding balls or bonding bumps. The lower contact pads  105 , which are a particular type of bottom-side conductive connectors, are for attachment to a PCB, or other component, using conductive balls. The upper contact pads  103  are smaller both individually and collectively, as an array than the lower contact pads  105 . The pitch of the upper array is smaller than the pitch of the lower array. Interposed between the upper contact pads  103  and the lower contact pads  105  is a redistribution layer (RDL)  108 , which connects each upper contact pad  103  to a corresponding lower contact pad  105 . The redistribution layer  108  may comprise horizontal traces within and vertical vias through the substrate material  102 . Note that  FIG. 2 , like the other corresponding cross-sectional side views, does not show the traces and vias of the redistribution layer  108 . 
       FIG. 4  is a simplified top view of an assemblage  109  comprising the substrate plate  100  of  FIG. 1  and a lead frame array  110 , following the attachment of the lead frame array  110  to the top of the substrate plate  100 . The lead frame array  110  is similar to a QFN lead frame modified to eliminate die pads and tie bars. The lead frame array  110  comprises ten lead frame modules  111  corresponding to the ten substrate modules  101 . Each lead frame module  111  comprises four support bars  112 . Note that the support bars  112  of adjoining lead frame modules  111  are shared. 
     Each lead frame module  111  supports thirty-two lead fingers  113 , where each support bar  112  of each lead frame module  111  supports eight corresponding lead fingers  113 . 
       FIG. 5  is a simplified top view of the assemblage  109  of  FIG. 4  following the attachment of ten IC dies  114  to the corresponding ten substrate modules  101 .  FIG. 6  is a simplified enlarged cross-sectional side view of one of the substrate modules  101 , the corresponding lead frame module  111 , and the corresponding attached IC die  114  of  FIG. 5  along the cut-line YY. 
     The IC die  114  is electrically connected and attached to the upper contact pads  103  of the substrate module  101  using thirty-six corresponding conductive balls  117 . In addition to the conductive balls  117 , the IC die  114  may be additionally attached to the substrate module  101  using underfill (not shown) interposed between the IC die  114  and the substrate material  102  of the substrate module  101 . 
     The IC die  114  is a through-silicon-via (TSV) die having its active layer (not shown)—i.e., the layer with the active devices—at the die top  115 . The IC die  114  has vias (not shown) connecting the active layer at the die top  115  to the die-bottom contact pads (not shown) at the die bottom  116 . The die-bottom contact pads of the IC die  114  connect to the corresponding upper contact pads  103  with the corresponding conductive balls  117 . The IC die  114  additionally has bond pads (not shown) on the die top  115 , which may be used to electrically connect, e.g., with bond wires, the IC die  114  to the corresponding lead frame module  111 . 
       FIG. 7  is a simplified top view of the assemblage  109  of  FIG. 5  following the electrical connection using bond wires  118  of the IC dies  114  to the corresponding lead frame modules  111 . 
       FIG. 8  is a simplified enlarged cross-sectional side view of the substrate module  101 , the corresponding lead frame module  111 , the corresponding attached IC die  114 , and the corresponding bond wires  118  of  FIG. 7  along the cut-line YY. The bond pads on the die top  115  of the IC die  114  are electrically connected to corresponding lead fingers  113  using corresponding bond wires  118 . 
       FIG. 9  is a simplified top view of the assemblage  109  of  FIG. 7  following encapsulation with an encapsulant  119 .  FIG. 10  is a simplified enlarged cross-sectional side view of the substrate module  101 , the corresponding lead frame module  111 , the corresponding attached IC die  114 , the corresponding bond wires  118 , and the corresponding encapsulant  119  of  FIG. 9  along the cut-line YY. 
     Following encapsulation, the assemblage  109  undergoes a singulation, also called dicing, step in which the substrate modules  101  are singulated, i.e., separated from each other, by cutting along the cutting-lines  120 . The singulation may be accomplished using a laser (not shown) or a circular saw (not shown), in which case the cutting-lines  120  may be said to represent saw streets for the circular-saw cutting. The singulation involves removing the distal portions of (i) the lead fingers  113 —which leaves behind corresponding leads  113 , (ii) the encapsulant  119 , and (iii) the substrate material  102  of each substrate module  101  to end up with the corresponding multi-form chips  121 . 
       FIG. 11  is a simplified top view of one of the multi-form chips  121  resulting from the singulation of the corresponding substrate module  101  of the assemblage  109  of  FIG. 9 .  FIG. 12  is a simplified enlarged cross-sectional side view of the multi-form chip  121  of  FIG. 11 .  FIG. 13  is a perspective bottom view of the multi-form chip  121  of  FIG. 11 . The multi-form chip  121  is ready for attachment to a corresponding PCB using both the lower contact pads  105 —which may be connected to the PCB using conductive balls—and the leads  113 —which may be connected to the PCB using conductive bumps or soldering. The use of both the lower contact pads  105  and the leads  113  allows the multi-form chip  121  to have a higher density of input/output nodes than may be available by using only lower contact pads or only leads. 
     An embodiment of the invention has been described where a substrate module comprises a six-by-six array of upper contact pads, a corresponding six-by-six array of lower contact pads, and a redistribution layer interposed therebetween that connects each upper contact pad to the corresponding lower contact pad. The invention is not, however, so limited. Alternative implementations may have a different number of upper contact pads that may be arranged in any suitable manner. Alternative implementations may have a different number of lower contact pads that may be arranged in any suitable manner. Alternative implementations may have redistribution layers that may connect any number of upper contact pads to any number of lower contact pads in any suitable pattern. 
     An embodiment of the invention has been described where a substrate plate comprises substrate modules and a substrate material periphery. The invention is not, however, so limited. In some alternative embodiments, the substrate plate includes one or more substrate modules but does not include a substrate material periphery. 
     An embodiment of the invention has been described where the upper contact pads of the substrate module are individually smaller and have an array with a smaller pitch than the lower contact pads. The invention is not, however, so limited. In some alternative embodiments, the upper contact pads are the same size as, or larger than, the lower contact pads. In some alternative embodiments, the array of the upper contact pads has a pitch that is the same as or larger than that of the array of the lower contact pads. 
     An embodiment of the invention has been described where the upper contact pads of a substrate module are electrically connected to corresponding lower contact pads by a redistribution layer. The invention is not, however, so limited. In alternative embodiments, the upper contact pads are electrically connected to corresponding lower contact pads using vertical vias through the substrate material without an intervening redistribution layer. 
     An embodiment of the invention has been described where the lower contact pads are bond pads for ball-bond attachment. The invention is not, however, so limited. Alternative implementations of the substrate module may instead have other types of bottom-side conductive connectors such as, without limitation, (i) pins for a corresponding socket or (ii) openings for corresponding pins on a corresponding receptacle. 
     An embodiment of the invention has been described where the tops of the upper contact pads are flush with the top surface of the corresponding substrate material and the bottoms of the lower contact pads are flush with the bottom surface of the corresponding substrate material. The invention is not, however, so limited. Alternative implementations may have upper and/or lower contacts pads that are recessed within or extend out of the corresponding substrate material. 
     An embodiment of the invention has been described where the IC die is a TSV die that is electrically connected to the lower contact pads by die-bottom contact pads connected to upper contact pads of the substrate module with conductive balls. The invention is not, however, so limited. In some alternative embodiments, die-top bond pads at the top of the IC die are wire-bonded to upper contact pads of the substrate module—as well as to lead fingers of the corresponding lead frame. 
     An embodiment of the invention has been described where the active layer of the IC die is at the die top. The invention is not, however, so limited. In some alternative embodiments, the active layer of the IC die is at the die bottom, where the IC die is used as a flip-chip die. In these alternative embodiments, through-silicon vias are used to connect the active layer at the die bottom to the die-top contact pads of the IC die, which are used for wire bonding to the corresponding lead frame. 
     An embodiment of the invention has been described where the IC dies are connected and attached to the substrate plate after the lead frame array is attached to the substrate plate. The invention is not, however, so limited. In alternative embodiments, the IC dies are connected and attached to the substrate plate before the lead frame array is attached. 
     An embodiment of the invention has been described where a modified QFN lead frame is used to assemble the multi-form chips. The invention is not, however, so limited. In alternative embodiments, other types of lead frames are used. In one alternative embodiment, the lead frame used is a modified quad flat pack (QFP) lead frame that is modified to have no die pad or tie bars. The modified QFP lead frame comprises lead fingers supported by support bars and dam bars located proximally to the support bars. During encapsulation, the substrate module is encapsulated up to the dam bars, which leaves the distal portions of the lead fingers exposed and not encapsulated. During singulation, the support bars are removed and the dam bars are cut to electrically isolate the individual leads from each other. After singulation, the resultant multi-form chip has lower contact pads on the bottom surface and protruding leads on the sides. The protruding leads may be bent into, for example, gull-wing leads or j leads. If the protruding leads are bent into j leads, then the encapsulant may be provided with corresponding notches in which the j leads are recessed. 
     Embodiments of the invention have been described where the multi-form chips are square in a top view. The invention is now, however, so limited. In alternative embodiments, the multi-form chips have, in a top view, shapes other than a square. 
     Embodiments of the invention have been described where the mutli-form chips have leads on four sides of the chip. The invention is not, however, so limited. In alternative embodiments, the multi-form chips have leads on fewer or more than four sides. 
     Embodiments of the invention have been described where a multi-form chip includes one IC die. The invention is not, however, so limited. In some embodiments, the multi-form chip includes two or more IC dies, which may be, for example, stacked vertically or placed side by side. 
     It should be noted that—unless mutually exclusive—any of the above alternatives may be combined with any other alternative embodiments and/or the above-described embodiment. 
     It will be further understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain the nature of this invention may be made by those skilled in the art without departing from the scope of the invention as expressed in the following claims. 
     A lead frame is a collection of metal leads and possibly other elements (e.g., die paddles, power bars) that is used in semiconductor packaging for assembling one or more IC dies into a single packaged semiconductor device. Prior to assembly into a packaged device, a lead frame may have support structures (e.g., a rectangular metal frame) that keep those elements in place. During the assembly process, the support structures may be removed. As used herein, the term “lead frame” may be used to refer to the collection of elements before assembly or after assembly, regardless of the presence or absence of those support structures. 
     Reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments necessarily mutually exclusive of other embodiments. The same applies to the term “implementation.” 
     Unless explicitly stated otherwise, each numerical value and range should be interpreted as being approximate as if the word “about” or “approximately” preceded the value of the value or range. As used in this application, unless otherwise explicitly indicated, the term “connected” is intended to cover both direct and indirect connections between elements. 
     In this specification including any claims, the term “each” may be used to refer to one or more specified characteristics of a plurality of previously recited elements or steps. When used with the open-ended term “comprising,” the recitation of the term “each” does not exclude additional, unrecited elements or steps. Thus, it will be understood that an apparatus may have additional, unrecited elements and a method may have additional, unrecited steps, where the additional, unrecited elements or steps do not have the one or more specified characteristics. 
     Although the steps in the following method claims are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those steps, those steps are not necessarily intended to be limited to being implemented in that particular sequence.