Abstract:
A multi-ladder DAC includes first and second resistor ladders, with a switch-interconnect. The switch-interconnect includes a second set of switches connected between each node of the first ladder and the top and bottom tap points of the second ladder. All other second ladder tap points are part of a loop tied to the nodes above and below each resistor through a second set of switches. Because no current flows through the switches that tie the top and bottom second-ladder tap points to the nodes of the first ladder, avoiding IRswitch error, thereby improving DNL.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    Priority is claimed under 37 CFR 1.78 and 35 USC 119(e) to U.S. Provisional Application 62/270505 (Docket TI-76492PS), filed Dec. 21. 2015), which is incorporated by reference. &lt;&lt; PLL lock range extension over temperate using capacitor bank switching during PLL operation 
     
    
     BACKGROUND 
       [0002]    Technical Field. 
         [0003]    This Patent Disclosure relates generally to phase-locked loop systems. 
         [0004]    Related Art. 
         [0005]    A phase-locked loop (PLL) circuit establishes a frequency/phase control loop around a VCO (voltage, or current, controlled oscillator), providing a Vctrl control voltage to adjust VCO frequency/phase to lock the VCO output to the frequency/phase of an input signal, such as a reference frequency signal. 
         [0006]    CMOS-based VCO designs commonly use LC and Ring based VCOs. LC VCOs rely on a varactor to fine tune the Vctrl voltage, and commonly include a switching capacitor array/bank to extend the tuning range (extend Kvco gain). 
         [0007]    The frequency range within which a PLL circuit can provide a locked output varies with the operation temperature of the PLL circuit, so that a PLL circuit may be unable to remain locked when the operation temperature fluctuates outside a specified temperature range (junction temperature). Two approaches to increasing lock range are increasing varactor size, and increasing the dynamic range of the Vctrl voltage. Increasing varactor size increases Kvco, which leads to an increase in phase noise. Increasing Vctrl can be restricted by varactor stress (reliability) considerations. 
         [0008]    While this Background information references in particular an LC VCO, the Disclosure is more generally directed to VCOs with switched capacitor tuning. 
       BRIEF SUMMARY 
       [0009]    This Brief Summary is provided as a general introduction to the Disclosure provided by the Detailed Description and Drawings, summarizing aspects and features of the Disclosure. It is not a complete overview of the Disclosure, and should not be interpreted as identifying key elements or features of, or otherwise characterizing or delimiting the scope of, the disclosed invention. 
         [0010]    The Disclosure describes a methodology for PLL lock range extension over temperate using dynamic capacitor bank switching to dynamically adjust varactor set point during PLL operation. 
         [0011]    According to aspects of the Disclosure, the PLL includes a VCO with a variable capacitance (such as an LC VCO) including a switched capacitor bank and a varactor. The PLL provides lock range extension over temperature using dynamic capacitor bank switching to dynamically adjust varactor set point based on junction temperature. The varactor is responsive to the Vctrl control voltage to adjust a capacitance of the variable capacitance to control the phase of the PLL signal. Compensation circuitry dynamically adjusts varactor set point by dynamically switching the capacitor bank based in a junction temperature associated with the PLL circuitry, thereby extending PLL lock range over temperature. 
         [0012]    Other aspects and features of the invention claimed in this Patent Document will be apparent to those skilled in the art from the following Disclosure. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]    Notification of Color Drawings. This Application contains at least one drawing in color. Copies of this Provisional Patent Disclosure with color drawings will be provided by the Office upon request and payment of the necessary fee. 
           [0014]      FIG. 1A  illustrates an example embodiment of a PLL adapted for PLL lock range extension over temperate for a PLL with an LC VCO including a variable capacitance with a switched capacitor bank and a varactor, using dynamic capacitor bank switching to adjust varactor set point during PLL operation, when junction temperature exceeds pre-defined temperature thresholds, including adjustment during calibration to provide capacitor bank adjustment range (capacitor code bits/steps) for varactor set point adjustment during compensation/operation. 
           [0015]      FIG. 1B  illustrates an example variable capacitance circuit including a switched capacitor bank/array, and a varactor, the switched capacitor bank configured as a three-level capacitor bank, with UFC (ultra-fine capacitor code), FC (Fine capacitor code) and CC (Course capacitor code) banks or elements. 
           [0016]      FIG. 2  provides example plots illustrating the PLL lock range extension scheme based on dynamic capacitor bank switching for varactor set point adjustment (dynamic adjustment of varactor range). 
           [0017]      FIG. 3  provides an example plot illustrating the PLL lock range extension scheme, including dynamic varactor set point adjustment (with resulting transient), and including hysteresis. 
           [0018]      FIG. 4  illustrates a design example of the PLL lock range extension scheme, including introducing temperature zones into dynamic varactor set point. 
           [0019]      FIG. 5  illustrates a design example of the PLL lock range extension scheme, including introducing hysteresis into dynamic varactor set point adjustment. 
           [0020]      FIG. 6  illustrates, for the PLL lock range extension scheme, an effect of capacitor code step size on transient performance in dynamically adjusting varactor set point. 
       
    
    
     DETAILED DESCRIPTION 
       [0021]    This Description and the Drawings constitute a Disclosure for PLL lock range extension over temperate using dynamic capacitor bank switching, such as to dynamically adjust varactor set point during PLL operation, including describing example embodiments, and illustrating various technical features and advantages. 
         [0022]    The PLL lock range extension scheme can be used to extend the PLL lock range beyond that available based on varactor Kvco and dynamic range of Vctrl. Prior to running out of varactor voltage range, during PLL operation, a discrete (such as UFC) capacitor code change dynamically resets varactor set point voltage, extending the varactor tuning range in the direction of the varactor set point change. 
         [0023]    In brief overview a PLL including a VCO with a variable capacitance (such as an LC VCO) including a switched capacitor bank and a varactor, the PLL providing lock range extension over temperature using dynamic capacitor bank switching to dynamically adjust varactor set point based on junction temperature. The varactor is responsive to the Vctrl control voltage to adjust a capacitance of the variable capacitance to control the phase of the PLL signal. Compensation circuitry dynamically adjusts varactor set point by dynamically switching the capacitor bank based in a junction temperature associated with the PLL circuitry, thereby extending PLL lock range over temperature. 
         [0024]      FIG. 1A  illustrates an example embodiment of a PLL adapted for PLL lock range extension over temperate for a PLL with an LC VCO including a variable capacitance with a switched capacitor bank and a varactor, using capacitor bank switching to adjust varactor set point during PLL operation, when junction temperature exceeds pre-defined temperature thresholds, including adjustment during calibration to provide cap bank adjustment range (capacitor code bits/steps) for varactor set point adjustment during compensation/operation. 
         [0025]    An analog PLL receives a reference frequency input, and provides a Vctrl control voltage to a VCO, based on a feedback voltage FBK. The example VCO is an LC VCO including a variable capacitance and a inductor coil. 
         [0026]    The variable capacitance includes a varactor and a switched capacitor bank. The switched capacitor bank is used to provide a set point for the varactor. The varactor is controlled by the Vctrl control voltage. 
         [0027]    Control for the capacitor bank includes a calibration state machine, and according to this Disclosure a compensation state machine. Both receive as inputs junction temperature information based on monitoring on-chip junction temperature. 
         [0028]    The calibration state machine controls capacitor bank switching during a calibration routine, to configure the capacitor bank for a varactor set point. According to aspects of the Disclosure, the compensation state machine functions during PLL operation to adjust the varactor set point based on junction temperature (Tj) information. Specifically, when junction temperature exceeds pre-defined Tj thresholds, the compensation state machine introduces a digital (capacitor code) adjustment to the capacitor bank to adjust varactor set point in the direction of the capacitor code adjustment to the capacitor bank. 
         [0029]      FIG. 1B  illustrates an example variable capacitance circuit including a varactor and a switched capacitor bank/array. The example switched capacitor bank is configured as a three-level capacitor bank, with UFC (ultra-fine capacitor code), FC (Fine capacitor code) and CC (Course capacitor code) banks or elements. That is, the cells in capacitor bank are UFC, FC and CC, where UFC is the smallest tunable (discrete) capacitor in the capacitor bank. 
         [0030]    Referring also to  FIGS. 2 and 3 , according to aspects of the Disclosure, during PLL operation, varactor set point can be adjusted by the compensation state machine in response to changes in junction temperature by providing digitally controlled capacitor codes to control capacitor bank switching.  FIG. 2  illustrates, as a design example, both a 1-bit UFC change, and 4-bit UFC change. 
         [0031]    For this design example, the capacitor codes ΔUFC (or, ΔUFC and ΔFC) are used to for varactor set point adjustment, where capacitance step size (capacitor code adjustment) is a design choice, as described further below. Adjustment of varactor set point during PLL operation ensures that over temperature the varactor loop filter control voltage Vctrl is retained in its dynamic range, extending varactor tuning range in the direction of the varactor set point adjustment. 
         [0032]    According to other aspects of the Disclosure, during varactor set point calibration, the varactor set point can be adjusted by the calibration state machine to ensure sufficient varactor set point adjustment range (for example, ΔUFC or ΔUFC/ΔFC capacitor code bits) is available to the compensation state machine to provide varactor set point adjustment during PLL operation. That is, the calibration state machine can be configured such to ensure that, after calibration, the calibrated (initial) varactor set point (based on a digitally controlled capacitor code value of UFC/FC/CC input to the switched UFC/FC/CC capacitor bank) provides sufficient step size range (ΔFC and ΔUFC changes) in the each direction (increase or decrease). 
         [0033]    Referring also to  FIG. 4 , as a design example, varactor set point calibration by the calibration state machine, based on junction temperature monitoring, can be configured to take into account: (a) Initial locking junction temperature Tj_lock, and (b) Temp Zone in which the PLL system is designed for operation (such as cold zone/hot zone), where the zone definition is (firmware) programmable, for example lock Tj_lock&gt;0 Deg C. is hot-zone and Tj_lock&lt;0 is cold-zone. If the calibration state machine returns a calibration capacitor code that does not provide sufficient varactor set point adjustment range, then calibration can be run again to provide a calibration capacitor code that ensures a pre-defined varactor set point tuning range for the compensation state machine during PLL operation. For example, calibration can be run with a pre-defined Coarse capacitor code CC, resulting in a new calibration capacitor code (CC, FC, UFC) to enable ΔFC and ΔUFC changes to the varactor set point by the compensation state machine. 
         [0034]    That is, the LC VCO includes a variable capacitance with discrete capacitors that are digitally controlled (UFC, FC, CC). The varactor, controlled by Vctrl, is used to keep the PLL locked as temperature (or other factors) changes In order to keep the PLL locked as temperature drifts. During PLL operation, the compensation state machine enables a discrete UFC jump prior to running out of varactor voltage range, resetting the varactor set point voltage, and effectively allowing the varactor tuning range to be extended as the temperature increases/decreases. 
         [0035]    Varactor set point compensation is implemented by: (a) monitoring on-chip junction temperature, and (b) changing the capacitor codes that control the switched capacitor banks (UFD/FC/CC) when the temperature reaches a pre-defined threshold, to permit the compensation state machine to adjust varactor set point during PLL operation. 
         [0036]    During PLL operation, as described further below, the compensation state machine runs background temperature monitoring with hysteresis as follows: (a) for low to high, Zone  1  to Zone  2 , UFC transition takes place at 65° C., and (b) for high to low, Zone  2  to Zone  1 , UFC transition takes place at 0° C. 
         [0037]    Referring to  FIG. 4 , as a design example, at the time of varactor set point calibration, if the locking temperature is less than or equal to 0° C., then Zone  1  is selected, otherwise Zone  2  is selected. Tambient at time of locking is between −40° C. and 85° C. (105° C. Tjunction). 
         [0038]    As an alternative design example, varactor set point calibration by the calibration state machine can be configured for operation with an extra UFC bank UFC_Temp parked in the mid code during varactor set point calibration. The additional UFC bank ensures that there are UFC bits available to adjust varactor set point for frequency drift with temperature in both directions with the desired step size. As a design example: (a) UFC_Temp can be  16  capacitor code bits wide, and UFC_Core can be 8 capacitor code bits wide. During calibration, UFC_Temp is parked mid-code (8 bits on and 8 bits off), and UFC_Core is adjusted during calibration. For lock range extension, UFC_Temp is incremented/decremented in appropriate step-size at the desired temperature threshold, while UFC_Core is left un-changed at the calibration value. This design example obtains the desired calibration capacitor code in a single calibration run. 
         [0039]      FIG. 5  illustrates PLL lock range extension over temperate, including varactor set point adjustment, and including introducing hysteresis to reduce the number of varactor set point adjustments, and the associated transients, as illustrated in  FIG. 3 . Hysteresis points are programmable. As a design example, transition zones can be defined and implemented by the compensation state machine. Other transition zone factors can include limiting varactor set point adjustment to the transition slot between TX off and RX on. 
         [0040]    As a design example, the lock range extension scheme with hysteresis in  FIG. 5  illustrates an implementation with hysteresis transition points at 0 Deg and 60 Deg, i.e. the temperature thresholds where UFC bits are changed by the compensation state machine to adjust varactor set point during PLL operation. Specifically, going from cold-zone to hot-zone the UFC change takes place at 60 Deg C., while going from hot-zone to cold-zone UFC changes at 0 Deg C., providing hysteresis to the capacitor code change to reduce varactor set point adjustment transients. 
         [0041]    Referring to  FIGS. 3 and 6 , a discrete change in capacitance (as opposed to a continuous change in capacitance as occurs in the varactor) introduces transients (steady state phase change). Such transients can be counteracted by a number of design techniques. For example, avoiding changing capacitor codes, and therefore varactor set point, at any temperature (or equivalently based on any change in Vctrl), and instead, varactor set point adjustment is done at the Vctrl values where the loop gain is high, and the varactor still has some margin, and the PLL is not at the out of lock threshold. As another example, the smallest number of UFC bits can be used to extend the range only as needed in order to minimize transients. 
         [0042]    According to aspects of the Disclosure, a PLL adapted for PLL lock range extension over temperate, such as a PLL with an LC VCO, including a variable capacitance with a switched capacitor bank and a varactor, and including using capacitor bank switching to adjust varactor set point during PLL operation, when junction temperature exceeds pre-defined temperature thresholds. Discrete capacitor steps to adjust varactor set point allows for the reuse of the varactor at a new varactor set point based on monitoring of on-chip junction temperature through on-chip temperature sensor to allow change in capacitor code (ΔUFC and ΔFC) at desired temperature threshold. The PLL lock extension scheme based on adjustments to varactor set does not monitor Vctrl voltage (avoiding the associated noise penalty). Temperature thresholds for varactor set point adjustment, including hysteresis, are programmable, thus allowing lock range extension to take into account geographical considerations. As an example, the compensation state machine can be designed for 5 Deg/10 Deg/30 Deg extension in lock range over temperature, with programmable step size. Programmable hysteresis allows for the extended lock range to remain valid (PLL locking not disturbed) for extended duration of time, without introducing excessive transients. The scheme avoids overhead for higher Kvco (larger varactor), and loop filter capacitor size. The voltage range needed on the Vctrl node is reduced, thus relaxing the stress tolerance of devices, and the need of special higher Voltage LDOs to support higher Vctrl voltage. The scheme provides a design trade-off between step size and settling transient, and uses hysteresis to reduce transients due to dynamic varactor set point adjustment. 
         [0043]    The Disclosure provided by this Description and the Figures sets forth example embodiments and applications illustrating aspects and features of the invention, and does not limit the scope of the invention, which is defined by the claims. Known circuits, connections, functions and operations are not described in detail to avoid obscuring the principles and features of the invention. These example embodiments and applications, including example design considerations/choices/tradeoffs, can be used by ordinarily skilled artisans as a basis for modifications, substitutions and alternatives to construct other embodiments, including adaptations for other applications.