Abstract:
A dual antenna RFID tag which can perform both Near Field (NF) communication and Far Field (FF) communication using a single RF tag is presented. The RFID tag includes an antenna unit and a voltage rectification unit. The antenna unit can perform communications in either or both a first and a second bandwidth. The voltage rectification unit can rectify and boost one or more radio signals received through the antenna unit and generate one or more power voltage impulses corresponding to the radio signals respectively.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    The priority of Korean patent application No. 10-2008-0126593 filed Dec. 12, 2008, the disclosure of which is hereby incorporated in its entirety by reference, is claimed. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a RFID tag which can be used both for Near Field (NF) Radio Frequency Identification (RFID)-type communication and Far Field (FF) RFID-type communication, and more particularly, to a RFID tag which includes an additional antenna for NF RFID communication and FF RFID communication in a single RFID tag, thereby enabling both types of communications. 
         [0004]    2. Background of the Invention 
         [0005]    RFID is a technology for providing a contactless automatic identification method that an RFID tag is attached to an object for identification so as to automatically identify the object by using radio signals while carrying out communications with an RFID reader through transceive using the radio signals. The RFID technology can supplement the shortcomings of barcode and optical character recognition technologies which are conventional automatic identification technologies. 
         [0006]    Recently, the RFID tag is used in several applications, such as a logistic management system, a user certification system, an electronic money system, and a traffic system. 
         [0007]    For example, in the logistic management system, freight is classified or inventory control is performed by using Integrated Circuit (IC) tags in which data is recorded instead of delivery slips or tags. Further, in the user certification system, the entrance management is performed by using an IC card in which personal information is recorded. 
         [0008]    In general, non-volatile ferroelectric memory can be used for the RFID tag. 
         [0009]    Non-volatile ferroelectric memory, that is, Ferroelectric Random Access Memory (FeRAM) has been in the spotlight as a next-generation memory device as it has a data processing speed comparable to that of Dynamic Random Access Memory (DRAM) and retains its data even after when power is turned off. 
         [0010]    FeRAM devices have almost the same structure as that of to DRAMs. FeRAMs use ferroelectric capacitors as storage elements. FeRAMs exhibit a high residual polarization property and can retain data even though an applied electric field might be removed. 
         [0011]    RFID uses several frequency bands and has different characteristics according to the frequency bands. 
         [0012]    In general, when the RFID frequency band is low, the RFID device is likely to exhibit a slow recognition speed, operate in a short range, and is less influenced by extraneous environmental interference. On the other hand, when the RFID frequency band is high, the RFID device is likely to exhibit a fast recognition speed, operate in a longer range and is prone to extraneous interference from the environment. 
         [0013]    Conventional RFID tags are divided into an RFID tag used in a low frequency band and an RFID tag used in a high frequency band. That is, an RFID tag equipped with an antenna enabling communication in a low frequency band and an RFID tag equipped with an antenna enabling communication in a high frequency band separately exist. Accordingly, there is a problem in that different RFID tags should be used according to the particular purpose of use. 
       BRIEF SUMMARY OF THE INVENTION 
       [0014]    Various embodiments of the invention are directed to provide an RFID tag which includes an additional antenna for NF communication and FF communication in a single RFID tag, thereby enabling both types of communications. 
         [0015]    According to an embodiment of the present invention, an RFID tag comprises an antenna unit configured to perform communication in a first bandwidth and a second bandwidth, and a voltage rectification unit configured to rectify and boost one or more radio signal received through the antenna unit and configured to generate one or more power voltages corresponding to the radio signals respectively. 
         [0016]    According to another embodiment of the present invention, an RFID tag comprises an antenna unit comprising a first antenna configured to perform communication in a first bandwidth and a second antenna configured to perform communication in a second bandwidth, and a voltage rectification unit configured to rectify and boost one or more radio signals received through the antenna unit and configured to generate one or more power voltages corresponding to the respective radio signals. The voltage rectification unit comprises a clamping circuit unit configured to clamp and to output the one or more radio signals, and a rectification circuit unit configured to rectify the signals outputted from the clamping circuit unit and configured to generate a DC voltage. 
         [0017]    According to the present invention, an antenna enabling NF communications in a low frequency band and an antenna enabling FF communications in a high frequency band are included in a single RFID tag. Accordingly, there is an advantage in that both NF communication and FF communication can be performed using the single RFID tag. 
         [0018]    Further, there is an advantage in that the entire size of a RFID tag can be reduced by applying the ferroelectric capacitors of a high permittivity to the rectifier included in the voltage rectification unit. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0019]      FIG. 1  illustrates an overall configuration of an RFID tag according to the present invention; 
           [0020]      FIG. 2  is a detailed circuit diagram illustrating a voltage rectification unit and a summation unit according to a first embodiment of the present invention; 
           [0021]      FIGS. 3   a  to  3   d  are diagrams illustrating the operation of a first voltage rectifier according to the first embodiment of the present invention; 
           [0022]      FIGS. 4   a  to  4   d  are diagrams illustrating the operation of a second voltage rectifier according to the first embodiment of the present invention; 
           [0023]      FIG. 5  is a circuit diagram illustrating a modulation/demodulation unit according to the first embodiment of the present invention; 
           [0024]      FIG. 6  is a detailed circuit diagram illustrating a voltage rectification unit and a summation unit according to a second embodiment of the present invention; 
           [0025]      FIGS. 7   a  to  7   d  are diagrams illustrating the operation of a first voltage rectifier according to the second embodiment of the present invention; 
           [0026]      FIGS. 8   a  to  8   d  are diagrams illustrating the operation of a second voltage rectifier according to the second embodiment of the present invention; 
           [0027]      FIG. 9  is a circuit diagram illustrating a modulation/demodulation unit according to the second embodiment of the present invention; 
           [0028]      FIG. 10  is a detailed circuit diagram illustrating a voltage rectification unit and a summation unit according to a third embodiment of the present invention; 
           [0029]      FIGS. 11   a  to  11   d  are diagrams illustrating the operation of a first voltage rectifier according to the third embodiment of the present invention; 
           [0030]      FIGS. 12   a  to  12   d  are diagrams illustrating the operation of a second voltage rectifier according to the third embodiment of the present invention; 
           [0031]      FIG. 13  is a circuit diagram illustrating a modulation/demodulation unit according to the third embodiment of the present invention; 
           [0032]      FIG. 14  is a detailed circuit diagram illustrating a voltage rectification unit and a summation unit according to a fourth embodiment of the present invention; 
           [0033]      FIGS. 15   a  to  15   d  are diagrams illustrating the operation of a first voltage rectifier according to the fourth embodiment of the present invention; 
           [0034]      FIGS. 16   a  to  16   d  are diagrams illustrating the operation of a second voltage rectifier according to the fourth embodiment of the present invention; 
           [0035]      FIG. 17  is a circuit diagram illustrating a modulation/demodulation unit according to the fourth embodiment of the present invention; and 
           [0036]      FIG. 18  is a circuit diagram illustrating a driving unit and modulation/demodulation unit according to the present invention. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0037]    Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Reference numerals and symbols indicated in the drawings denote different elements. 
         [0038]      FIG. 1  illustrates an overall configuration of an RFID tag according to the present invention. 
         [0039]    Referring to  FIG. 1 , the RFID tag of the present invention includes an antenna unit  10 , an analog unit  100 , a digital unit  200 , and a memory unit  300 . 
         [0040]    The antenna unit  10  transceives data between an external reader or writer (not shown) and the RFID tag. The antenna unit  10  includes a first antenna  11  that performs communication in a first bandwidth and a second antenna  12  that performs communication in a second bandwidth. The first bandwidth can preferably be formed in a low frequency domain of 1 MHz or less, and the second bandwidth can preferably be formed in a high frequency domain of 100 MHz or more. The first antenna can be configured to perform NF communication, and the second antenna can be configured to perform FF communication. 
         [0041]    The analog unit  100  includes a voltage rectification unit  110 , a modulation/demodulation unit  120 , a summation unit  130 , a logical sum device  140 , a power-on reset unit  150 , a clock generation unit  160 , and a driving unit  170 . 
         [0042]    The voltage rectification unit  110  includes a first voltage rectifier  111  configured to amplify a radio signal received from the first antenna  11  and a second voltage rectifier  112  configured to amplify a radio signal received from the second antenna  12 . 
         [0043]    The first voltage rectifier  111  is configured to amplify a received radio signal and generate a power voltage VDD 1 . The power voltage VDD 1  is supplied to a first demodulator  1211  and a first modulator  1212  and the power voltage VDD 1  is used as a power voltage. 
         [0044]    The second voltage rectifier  112  is configured to amplify a received radio signal and generate a power voltage VDD 2 . The power voltage VDD 2  is supplied to a second demodulator  1221  and a second modulator  1222  and the power voltage VDD 2  is used as a power voltage. 
         [0045]    The summation unit  130  is configured to receive the power voltage VDD 1  and the power voltage VDD 2  to sum and to generate a power voltage VDD. That is, the summation unit  130  preferably generates the power voltage VDD in accordance to VDD=VDD 1 +VDD 2 . The power voltage VDD is supplied to the power-on reset unit  150 , the clock generation unit  160 , and the memory unit  300 . 
         [0046]    The modulation/demodulation unit  120  includes the first demodulator  1211  configured to demodulate a radio signal received from the first antenna  11 , the first modulator  1212  configured to modulate a transmission signal TX 1  transmitted from the digital unit  200  to the reader, the second demodulator  1221  configured to demodulate a radio signal received from the second antenna  12 , and the second modulator  1222  configured to modulate a transmission signal TX 2  transmitted from the digital unit  200  to the reader. 
         [0047]    The first demodulator  1211  demodulates a radio signal received from the first antenna  11 . That is, the first demodulator  1211  detects a reception signal RX 1 , which is an operation command signal, from the radio signal and outputs to the digital unit  200 . The second demodulator  1221  demodulates a radio signal received from the second antenna  12 . That is, the second demodulator  1221  detects a reception signal RX 2 , which is an operation command signal, from the radio signal and outputs to the digital unit  200 . 
         [0048]    The logical sum device  140  logically sums the reception signal RX 1  and the reception signal RX 2  and generate a reception signal RX. The reception signal RX is inputted to the digital unit  200 . The logical sum device  140  preferably refers to an OR gate. 
         [0049]    The power-on reset unit  150  detects the power voltage VDD, which is an output voltage of the voltage rectification unit  110 , and outputs a power-on reset signal POR for controlling a reset operation to the digital unit  200 . 
         [0050]    The clock generation unit  160  supplies the digital unit  200  with a clock CLK for controlling the operation of the digital unit  200  according to the power voltage VDD which is an output voltage of the voltage rectification unit  110 . 
         [0051]    The digital unit  200  receives the power voltage VDD, the power-on reset signal POR, the clock CLK, and the reception signal RX from the analog unit  100 , and analyzes the reception signal RX to generate a transmission signal TX for controlling and processing the RFID tag, and outputs to the analog unit  100 . 
         [0052]    The driving unit  170  operates the transmission signal TX received from the digital unit  200 . The driving unit  170  includes a first driver  171  and a second driver  172 . The first driver  171  operates a transmission signal TX 1  inputted to the first modulator  1212 , and the second driver  172  operates a transmission signal TX 2  inputted to the second modulator  1222 . 
         [0053]    The transmission signal TX 1  is modulated in the first modulator  1212  so that it can be transmitted in the first bandwidth, and the modulated signal is transmitted to the reader via the first antenna  11 . The transmission signal TX 2  is modulated in the second modulator  1222  so that it can be transmitted in the second bandwidth, and the modulated signal is transmitted to the reader via the second antenna  12 . 
         [0054]    Further, the digital unit  200  outputs an address ADD, input/output data I/O, a control signal CTR, and a clock CLK to the memory unit  300 . 
         [0055]    The memory unit  300  stores data processed by the digital unit. The memory unit  300  can be configured to read or write data using a non-volatile ferroelectric capacitor element. 
         [0056]      FIG. 2  is a detailed circuit diagram illustrating one preferred the voltage rectification unit  110  and the summation unit  130  according to a first preferred embodiment of the present invention. 
         [0057]    The voltage rectification unit  110  according to the present embodiment includes a first voltage rectifier  111  and a second voltage rectifier  112 . The first voltage rectifier  111  includes a plurality of capacitors CS 11  to CS 1 N, CP 11  to CP 1 N and a plurality of Schottky diodes D 11 A, D 11 B to D 1 NA, D 1 NB. The second voltage rectifier includes a plurality of capacitors CS 21  to CS 2 N, CP 21  to CP 2 N and a plurality of Schottky diodes D 21 A, D 21 B to D 2 NA, D 2 NB. 
         [0058]    The plurality of Schottky diodes D 11 A, D 11 B to D 1 NA, D 1 NB and the plurality of Schottky diodes D 21 A, D 21 B to D 2 NA, D 2 NB can be used as rectification components. The Schottky diode can include PN-type or NP-type diode. 
         [0059]    The first antenna  11  is configured to perform NF RFID communication carried out in accordance with Faraday&#39;s law of induction. The NF RFID communication is a communication method preferably using a low frequency domain of 1 MHz or less. The communication method operates at the distance of 50 cm or less. 
         [0060]    The second antenna  12  is configured to perform FF RFID communication carried out in accordance with the principle of electromagnetic energy. The FF RFID communication is a communication method using a high frequency domain of preferably 100 MHz or more. This communication method operates at the distance of 50 cm or more. 
         [0061]    Since the present invention receives the radio signals from the first antenna  11  and the second antenna  12 , it can transceive radio signals irrespective of the distance between an RF reader and an RF tag. 
         [0062]    The radio signals received through the first antenna  11  and the second antenna  12  are inputted to the voltage rectification unit  110 . In detail, the radio signal received from the first antenna  11  is rectified and boosted by the first voltage rectifier  111 , and the radio signal received from the second antenna  12  is rectified and boosted by the second voltage rectifier  112 . 
         [0063]    Referring to  FIG. 2 , the first voltage rectifier  111  preferably includes the plurality of capacitors CP 11  to CP 1 N, CS 11  to CS 1 N and the plurality of diodes D 11 A, D 11 B to D 1 NA, D 1 NB, and the second voltage rectifier  112  preferably includes the plurality of capacitors CP 21  to CP 2 N, CS 21  to CS 2 N and the plurality of diodes D 21 A, D 21 B to D 2 NA, D 2 NB. 
         [0064]      FIGS. 3   a  to  3   d  are diagrams illustrating the operation of the first voltage rectifier  111  according to the first embodiment of the present invention. 
         [0065]      FIG. 3   a  is a circuit diagram illustrating a portion ‘A’ of the first voltage rectifier  111  shown in  FIG. 2  or in  FIG. 5 .  FIG. 3   b  illustrates an input waveform of a radio signal received via the first antenna  11 .  FIG. 3   c  is a circuit diagram illustrating an Al partial circuit (hereinafter, ‘A 1  circuit’) shown in  FIG. 3   a,  and  FIG. 3   d  illustrates an output waveform of an A 2  partial circuit (hereinafter, ‘A 2  circuit’) shown in  FIG. 3   a.    
         [0066]    Referring to  FIG. 3   b,  an input radio signal Vin 1  has a sine wave varying in the range of −Vp 1  to Vp 1 . The input radio signal Vin 1  can be any waveform such as a sine wave, a triangle wave, a square wave, or a step wave. 
         [0067]    The input radio signal Vin 1  becomes an input to the A 1  circuit. In the A 1  circuit, current flows when the diode D 11 A is forward-biased while current does not flow when the diode D 11 A is reverse-biased. That is, only when the input radio signal has a negative voltage, the diode D 11 A is forward-biased, so that electric charges are accumulated in the capacitor CP 11 . As a result, voltage as much as −(−Vp 1 )=Vp 1  is applied to the capacitors CP 11 . Accordingly, it becomes Vcp 11 =Vp 1 . 
         [0068]    In  FIG. 3   a,  since it becomes Vin 1 +Vcp 11 =V 11 , the signal V 11  has a waveform which is obtained by shifting Vin 1  by Vcp 11  in parallel in the positive direction of the Y axis. As shown in  FIG. 3   c,  the output signal V 11  has a sine wave varying in the range of 0 to 2 Vp 1 . In this case, since the lowest peak voltage of the output signal V 11  is clamped to 0 V, the A 1  circuit operates as a clamping circuit. 
         [0069]    The signal V 11  becomes an input to the A 2  circuit. In the A 2  circuit, current flows when the diode D 11 B is forward-biased while current does not flow when the diode D 11 B is reverse-biased. That is, only when the input signal V 11  has a positive voltage, the diode D 11 B is forward-biased, so that electric charges are accumulated in the capacitor CS 11 . 
         [0070]    When the electric charges are accumulated such that a potential difference greater than a peak voltage 2 Vp 1  of the input signal V 11  is generated across the capacitor CS 11 , the electric charges of the capacitors CS 11  are not discharged because the diode D 11 B is reverse-biased. Accordingly, as shown in  FIG. 3   d,  a DC voltage having the magnitude of 2 Vp 1  is maintained substantially constant at node  11 . In this case, the output signal V 1  is rectified into a DC voltage having the highest peak voltage of the input signal V 11  such that the A 2  circuit operates as a rectification circuit. 
         [0071]    Thereafter, the above operation is repeatedly performed by the capacitors CP 12 , CS 22  and the diodes D 12 A, D 12 B. Since the voltage of the node  11  is 2 Vp, the DC voltage 2 Vp 1 +2 Vp 1 =4 Vp 1  is maintained substantially constant at a node  12 . 
         [0072]    As described above, as the rectification and boosting process is performed, the DC voltage ‘N*2 Vp 1 ’ is maintained substantially constant at node  1 N. Accordingly, the power voltage VDD 1  is generated while it becomes ‘VDD 1 =N*2 Vp 1 ’. 
         [0073]    Meanwhile, the present invention includes two antennas configured to receive different signals. Accordingly, the process of rectifying and boosting the radio signal received through the first antenna  11  can be identically applied to the case where the radio signal received through the second antenna  12  is rectified and boosted. 
         [0074]      FIGS. 4   a  to  4   d  are diagrams illustrating the operation of the second voltage rectifier  112  according to the first embodiment of the present invention. 
         [0075]      FIG. 4   a  is a circuit diagram illustrating a portion ‘B’ of the second voltage rectifier  112  shown in  FIG. 2  or in  FIG. 5 .  FIG. 4   b  illustrates an input waveform of the radio signal received through the second antenna  12 .  FIG. 4   c  illustrates an output waveform of a B 1  partial circuit (hereinafter, B 1  circuit) shown in  FIG. 4   a.    FIG. 4   d  illustrates an output waveform of a B 2  partial circuit (hereinafter, B 2  circuit) shown in  FIG. 4   a.    
         [0076]    Referring to  FIG. 4   b,  an input radio signal has a sine wave varying in the range of −Vp 2  to Vp 2 . The input radio signal can be waveform such as those including a sine wave, a triangle wave, a square wave, or a step wave. 
         [0077]    The input radio signal becomes an input to the B 1  circuit. In the B 1  circuit, current flows when the diode D 21 A is forward-biased while current does not flow when the diode D 21 A is reverse-biased. That is, only when the input radio signal has a negative voltage, the diode D 21 A is forward-biased, so that electric charges are accumulated in the capacitor CP 21 . As a result, voltage as much as −(−Vp 2 )=Vp 2  is applied to the capacitor CP 21 . Accordingly, it becomes Vcp 21 =Vp 2 . 
         [0078]    In  FIG. 4   a,  since it becomes Vin 2 +Vcp 21 =V 21 , the signal V 21  has a waveform which is obtained by shifting Vin 2  by Vcp 21  in parallel in the positive direction of the Y axis. As shown in  FIG. 4   c,  the output signal V 21  has a sine wave varying in the range of 0 to 2 Vp 2 . In this case, since the lowest peak voltage of the output signal V 21  is clamped to 0 V, the B 1  circuit operates as a clamping circuit. 
         [0079]    The signal V 21  becomes an input to the B 2  circuit. In the B 2  circuit, current flows when the diode D 21 B is forward-biased while current does not flow when the diode D 21 B is reverse-biased. That is, only when the input radio signal has a positive voltage, the diode D 21 B is forward-biased, so that electric charges are accumulated in the capacitor CS 21 . 
         [0080]    When the electric charges are accumulated in the capacitor CS 21  such that a potential difference greater than the peak voltage 2 Vp 2  of the input signal V 21  is applied across the capacitor CS 21 , the electric charges of the capacitor CS 21  is not discharged because the diode D 21 B is reverse-biased. Accordingly, as shown in  FIG. 4   d,  a DC voltage having the magnitude of 2 Vp 2  is maintained substantially constant at node  21 . In this case, the output signal V 2  is rectified into a DC voltage having the highest peak voltage of the input signal V 21  such that the B 2  circuit operates as a rectification circuit. 
         [0081]    Thereafter, the above operation is repeatedly performed by the capacitors CP 22 , CS 22  and the diodes D 22 A, D 22 B. Since the voltage at node  21  is 2 Vp 2 , the DC voltage 2 Vp 2 +2 Vp 2 =4 Vp 2  is maintained substantially constant at node  22 . 
         [0082]    As described above, as the rectification and boosting process is performed, a DC voltage N*2 Vp 2  is maintained substantially constant at node  2 N. Accordingly, the power voltage VDD 2  is generated and it becomes VDD 2 =N*2 Vp 2 . 
         [0083]    Referring back to  FIG. 2 , the power voltages VDD 1 , VDD 2  generated by the first voltage rectifier  111  and the second voltage rectifier  112  become an input to the summation unit  130 . The summation unit  130  is configured to perform an operation of adding the power voltages VDD 1  and VDD 2  which are input signals. As a result, a power voltage VDD which is obtained by adding the power voltage VDD 1  to the power voltage VDD 2  is generated and outputted to the power-on reset unit  150 , the clock generation unit  160 , and the memory unit  300 . The summation unit  130  can be implemented preferably using an op amplifier in various ways. 
         [0084]    The RFID tag of the present invention has two antennas coupled to each other in parallel. The cases where the two antennas receive radio signals can be classified into i) a case where only the first antenna  11  receives the radio signal, ii) a case where only the second antenna  12  receives the radio signal, and iii) a case where the first and second antennas simultaneously receive radio signals. 
         [0085]    In the case of i), the power voltage VDD 1  is generated from the radio signal received by the first antenna  11  through the above-described rectification and boosting operation, and it becomes VDD=VDD 1 . 
         [0086]    In the case of ii), the power voltage VDD 2  is generated from the radio signal received by the second antenna  12  through the above-described rectification and boosting operation, and it becomes VDD=VDD 2 . 
         [0087]    In the case of iii), since the first and second antennas  11  and  12  receive the radio signals simultaneously, the power voltages VDD 1  and VDD 2  are generated through the above-described rectification and boosting operation, and it becomes VDD=VDD 1 +VDD 2 . 
         [0088]      FIG. 5  is a circuit diagram illustrating the modulation/demodulation unit  120  according to the first embodiment of the present invention. 
         [0089]    Referring to  FIG. 5 , the radio signals received through the first antenna  11  and the second antenna  12  are respectively inputted to the first demodulator  1211  and the second demodulator  1221 . The first demodulator  1211  demodulates the radio signal received from the first antenna  11 , detects and outputs a reception signal RX 1 , which is an operation command signal, from the radio signal. The second demodulator  1221  demodulates the radio signal received from the second antenna  12 , detects and outputs a reception signal RX 2 , which is an operation command signal, from the radio signal. 
         [0090]    The logical sum device  140  is configured to logically sum the reception signal RX 1  and the reception signal RX 2  and generate a reception signal RX. The reception signal RX is inputted to the digital unit  200 . 
         [0091]    The logical sum device  140  can be implemented with an OR gate. That is, the logical sum device  140  outputs the reception signal RX of high level although any one of the reception signals RX 1  and RX 2  has a logic high level. 
         [0092]      FIG. 6  is a detailed circuit diagram illustrating the voltage rectification unit  110  and the summation unit  130  according to a second embodiment of the present invention. 
         [0093]    The voltage rectification unit  110  according to the present embodiment includes the first voltage rectifier  111  and the second voltage rectifier  112 . The first voltage rectifier  111  includes a plurality of ferroelectric capacitors FCS 11  to FCS 1 N, FCP 11  to FCP 1 N and a plurality of Schottky diodes D 11 A, D 11 B to D 1 NA, D 1 NB. The second voltage rectifier  112  includes a plurality of ferroelectric capacitors FCS 21  to FCS 2 N, FCP 21  to FCP 2 N and a plurality of Schottky diodes D 21 A, D 21 B to D 2 NA, D 2 NB. 
         [0094]    The plurality of Schottky diodes D 11 A, D 11 B to D 1 NA, D 1 NB and the plurality of Schottky diodes D 21 A, D 21 B to D 2 NA, D 2 NB are used as rectification components. The Schottky diodes can be implemented with PN-type or NP-type diodes. 
         [0095]    The first antenna  11  performs NF RFID communication carried out in accordance with Faraday&#39;s law of induction. The NF RFID communication is a communication method using a low frequency domain of 1 MHz or less. This communication method preferably operates at a distance of 50 cm or less. 
         [0096]    The second antenna  12  performs FF RFID communication carried out in accordance with the principle of electromagnetic energy. The FF RFID communication is a communication method using a high frequency domain of 100 MHz or more. The communication method preferably operates at a distance of 50 cm or more. 
         [0097]    According to the present invention, radio signals can be transceived irrespective of the distance between the RF reader and the RF tag because the radio signals are received from the first antenna  11  and the second antenna  12 . 
         [0098]    The radio signals received through the first antenna  11  and the second antenna  12  are inputted to the voltage rectification unit  110 . In detail, the radio signal received from the first antenna  11  is rectified and boosted by the first voltage rectifier  111 , and the radio signal received from the second antenna  12  is rectified and boosted by the second voltage rectifier  112 . 
         [0099]    Referring to  FIG. 6 , the first voltage rectifier  111  includes the plurality of ferroelectric capacitors FCP 11  to FCP 1 N, FCS 11  to FCS 1 N and the plurality of diodes D 11 A, D 11 B to D 1 NA, D 1 NB. The second voltage rectifier  112  includes the plurality of ferroelectric capacitors FCP 21  to FCP 2 N, FCS 21  to FCS 2 N and the plurality of diodes D 21 A, D 21 B to D 2 NA, D 2 NB. 
         [0100]      FIGS. 7   a  to  7   d  are diagrams illustrating the operation of the first voltage rectifier  111  according to the second embodiment of the present invention. 
         [0101]      FIG. 7   a  is a circuit diagram illustrating a portion ‘A’ of the first voltage rectifier  111  shown in  FIG. 6  or in  FIG. 9 .  FIG. 7   b  illustrates an input waveform of the radio signal received through the first antenna  11 .  FIG. 7   c  illustrates an output waveform of an A 1  partial circuit (hereinafter, A 1  circuit) shown in  FIG. 7   a.    FIG. 7   d  illustrates an output waveform of an A 2  partial circuit (hereinafter, A 2  circuit) shown in  FIG. 7   a.    
         [0102]    Referring to  FIG. 7   b,  an input radio signal Vin 1  has a sine wave varying in the range of −Vp 1  to Vp 1 . The input radio signal can be any waveform such as those including a sine wave, a triangle wave, a square wave, or a step wave. 
         [0103]    The input radio signal Vin 1  becomes an input to the A 1  circuit. In the A 1  circuit, current flows when the diode D 11 A is forward-biased while current does not flow when the diode D 11 A is reverse-biased. That is, only when the input radio signal has a negative voltage, the diode D 11 A is forward-biased such that electric charges are accumulated in the ferroelectric capacitor FCP 11 . As a result, voltage as much as −(−Vp 1 )=Vp 1  is applied to the ferroelectric capacitor FCP 11 . Accordingly, it becomes VFCP 11 =Vp 1 . 
         [0104]    In  FIG. 7   a,  since it becomes Vin 1 +VFCP 11 =V 11 , the signal V 11  has a waveform which is obtained by shifting Vin 1  by VFCP 11  in parallel in the positive direction of the Y axis. As shown in  FIG. 7   c,  the signal V 11  has a sine wave varying in the range of 0 to 2 Vp 1 . In this case, the A 1  circuit operates as a clamping circuit because the lowest peak voltage of the output signal V 11  is clamped to 0 V. 
         [0105]    The signal V 11  becomes an input to the A 2  circuit. In the A 2  circuit, current flows when the diode D 11 B is forward-biased while current does not flow when the diode D 11 B is reverse-biased. That is, only when the input signal V 11  has a positive voltage, the diode D 11 B is forward-biased such that electric charges are accumulated in the ferroelectric capacitor FCS 11 . 
         [0106]    When the electric charges are accumulated in the ferroelectric capacitor FCS 11  and a potential difference greater than the peak voltage 2 Vp 1  of the input signal V 11  is applied across the ferroelectric capacitor FCS 11 , the electric charges of the ferroelectric capacitor FCS 11  are not discharged because the diode D 11 B is reverse-biased. Accordingly, as shown in  FIG. 7   d,  a DC voltage having the magnitude of 2 Vp 1  is maintained substantially constant at node  11 . In this case, since the output signal V 1  is rectified into a DC voltage having the highest peak voltage of the input signal V 11 , the A 2  circuit operates as a rectification circuit. 
         [0107]    Thereafter, the above operation is repeatedly performed by the ferroelectric capacitors FCP 12 , FCS 12  and the diodes D 12 A, D 12 B. Since the voltage of the node  11  is 2 Vp, a DC voltage 2 Vp 1 +2 Vp 1 =4 Vp 1  is maintained substantially constant at node  12 . 
         [0108]    As described above, as the rectification and boosting process is performed, a DC voltage N*2 Vp 1  is maintained substantially constant at node  1 N. Accordingly, the power voltage VDD 1  is generated, and it becomes VDD 1 =N*2 Vp 1 . 
         [0109]    Meanwhile, the present invention includes two antennas configured to receive different signals. Accordingly, the process of rectifying and boosting a radio signal received through the first antenna can be identically applied to the case where a radio signal received through the second antenna  12  is rectified and boosted. 
         [0110]      FIGS. 8   a  to  8   d  are diagrams illustrating the operation of the second voltage rectifier  112  according to the second embodiment of the present invention. 
         [0111]      FIG. 8   a  is a circuit diagram illustrating a portion ‘B’ of the second voltage rectifier  112  shown in  FIG. 6  or in  FIG. 9 .  FIG. 8   b  illustrates an input waveform of the radio signal received through the second antenna  12 .  FIG. 8   c  illustrates an output waveform of a B 1  partial circuit (hereinafter, B 1  circuit) shown in  FIG. 8   a.    FIG. 8   d  illustrates the output waveform of a B 2  partial circuit (hereinafter, B 2  circuit) shown in  FIG. 8   a.    
         [0112]    Referring to  FIG. 8   b,  an input radio signal is a sine wave varying in the range of −Vp 2  to Vp 2 . The input radio signal can any type of waveform such as those including a sine wave, a triangle wave, a square wave, or a step wave. 
         [0113]    The input radio signal becomes an input to the B 1  circuit. In the B 1  circuit, current flows when the diode D 21 A is forward-biased while current does not flow when the diode D 21 A is reverse-biased. That is, only when the input radio signal has a negative voltage, the diode D 21 A is forward-biased, such that electric charges are accumulated in the ferroelectric capacitor FCP 21 . As a result, voltage as much as −(−Vp 2 )=Vp 2  is applied to the ferroelectric capacitor FCP 21 . Accordingly, it becomes VFCP 21 =Vp 2 . In  FIG. 8   a,  since , it becomes Vin 2 +VFCP 21 =V 21 , the output signal V 21  has a waveform which is obtained by shifting Vin 2  by VFCP 21  in parallel in the positive direction of the Y axis. As shown in  FIG. 8   c,  the output signal V 21  has a sine wave varying in the range of 0 to 2 Vp 2 . In this case, since the lowest peak voltage of the output signal V 21  is clamped to 0 V, the B 1  circuit operates as a clamping circuit. 
         [0114]    The output signal V 21  becomes an input to the B 2  circuit. In the B 2  circuit, current flows when the diode D 21 B is forward-biased while current does not flow when the diode D 21 B is reverse-biased. That is, only when the input radio signal has a positive voltage, the diode D 21 B is forward-biased, so that electric charges are accumulated in the ferroelectric capacitor FCS 21 . 
         [0115]    When the electric charges are accumulated in the ferroelectric capacitor FCS 21  and a potential difference greater than the peak voltage 2 Vp 2  of the input signal V 21  is applied across the ferroelectric capacitor FCS 21 , the electric charges of the ferroelectric capacitor FCS 21  are not discharged because the diode D 21 B is reverse-biased. Accordingly, as shown in  FIG. 8   d,  a DC voltage having the magnitude of 2 Vp 2  is maintained substantially constant at node  21 . In this case, the A 2  circuit operates as a rectification circuit because the output signal V 2  is rectified into a DC voltage having the highest peak voltage of the input signal V 21 . 
         [0116]    Thereafter, the above operation is repeatedly performed by the ferroelectric capacitors FCP 22 , FCS 22  and the diodes D 22 A, D 22 B. Since the voltage of the node  21  is 2 Vp 2 , a DC voltage 2 Vp 2 +2 Vp 2 =4 Vp 2  is maintained substantially constant at node  22 . 
         [0117]    As the rectification and boosting process is performed as described above, a DC voltage N*2 Vp 2  is maintained substantially constant at node  2 N. Accordingly, the power voltage VDD 2  is generated and it becomes VDD 2 =N*2 Vp 2 . 
         [0118]    Referring back to  FIG. 6 , the power voltages VDD 1  and VDD 2  generated by the first voltage rectifier  111  and the second voltage rectifier  112  become an input to the summation unit  130 . The summation unit  130  is configured to perform an operation of adding the power voltages VDD 1  and VDD 2  which are input signals. As a result, a power voltage VDD which is obtained by adding the power voltage VDD 1  to the power voltage VDD 2  is generated and outputted to the power-on reset unit  150 , the clock generation unit  160 , and the memory unit  300 . The summation unit  130  can be implemented with an op amplifier in various ways. 
         [0119]    The RFID tag of the present invention has two antennas coupled to each other in parallel. The cases where the two antennas receive radio signals can be classified into i) a case where only the first antenna  11  receives the radio signal, ii) a case where only the second antenna  12  receives the radio signal, and iii) a case where the first and second antennas receive the radio signals simultaneously. 
         [0120]    In the case of i), the power voltage VDD 1  is generated from the radio signal received by the first antenna  11  through the above-described rectification and boosting operation, and it becomes VDD=VDD 1 . 
         [0121]    In the case of ii), the power voltage VDD 2  is generated from the radio signal received by the second antenna  12  through the above-described rectification and boosting operation, and it becomes VDD=VDD 2 . 
         [0122]    In the case of iii), since the first and second antennas  11  and  12  receive the radio signals simultaneously, the power voltages VDD 1  and VDD 2  are generated through the above-described rectification and boosting operation, and it becomes VDD=VDD 1 +VDD 2 . 
         [0123]      FIG. 9  is a circuit diagram illustrating a modulation/demodulation unit  120  according to the second embodiment of the present invention. 
         [0124]    Referring to  FIG. 9 , the radio signals received through the first antenna  11  and the second antenna  12  are respectively inputted to the first demodulator  1211  and the second demodulator  1221 . The first demodulator  1211  demodulates the radio signal received from the first antenna  11 , detects and outputs a reception signal RX 1 , which is an operation command signal, from the radio signal. The second demodulator  1221  demodulates the radio signal received from the second antenna  12 , detects and outputs a reception signal RX 2 , which is an operation command signal, from the radio signal. 
         [0125]    The logical sum device  140  is configured to logically sum the reception signal RX 1  and the reception signal RX 2  and generate a reception signal RX. The reception signal RX is inputted to the digital unit  200 . 
         [0126]    The logical sum device  140  can be implemented with an OR gate. That is, the logical sum device  140  outputs the reception signal RX of high level although any one of the reception signals RX 1  and RX 2  has a logic high level. 
         [0127]      FIG. 10  is a detailed circuit diagram illustrating a voltage rectification unit and a summation unit according to a third embodiment of the present invention; 
         [0128]    The voltage rectification unit  110  according to the present embodiment includes a first voltage rectifier  111  and a second voltage rectifier  112 . The first voltage rectifier  111  includes a plurality of capacitors CS 11  to CS 1 N, CP 11  to CP 1 N and a plurality of NMOS transistors N 11 A, N 11 B to N 1 NA, N 1 NB. The second voltage rectifier  112  includes a plurality of capacitors CS 21  to CS 2 N, CP 21  to CP 2 N and a plurality of NMOS transistors N 21 A, N 21 B to N 2 NA, N 2 NB. 
         [0129]    The plurality of NMOS transistors N 11 A, N 11 B to N 1 NA, N 1 NB and the plurality of NMOS transistors N 21 A, N 21 B to N 2 NA, N 2 NB are used as rectification components. The NMOS transistors can be implemented using PN-type or NP-type NMOS transistors. 
         [0130]    The first antenna  11  performs NF RFID communication carried out in accordance with Faraday&#39;s law of induction. The NF RFID communication is a communication method using a low frequency domain of 1 MHz or less. This communication method preferably operates in the distance of 50 cm or less. 
         [0131]    The second antenna  12  performs FF RFID communication carried out in accordance with the principle of electromagnetic energy. The FF RFID communication is a communication method using a high frequency domain of 100 MHz or more. The communication method preferably operates in the distance of 50 cm or more. 
         [0132]    According to the present invention, radio signals can be transceived irrespective of the distance between the RF reader and the RF tag because the radio signals are received from the first antenna  11  and the second antenna  12 . 
         [0133]    The radio signals received through the first antenna  11  and the second antenna  12  are inputted to the voltage rectification unit  110 . In detail, the radio signal received from the first antenna  11  is rectified and boosted by the first voltage rectifier  111 , and the radio signal received from the second antenna  12  is rectified and boosted by the second voltage rectifier  112 . 
         [0134]    Referring to  FIG. 10 , the first voltage rectifier  111  includes the plurality of capacitors CP 11  to CP 1 N, CS 11  to CS 1 N and the plurality of NMOS transistors N 11 A, N 11 B to N 1 NA, N 1 NB. The second voltage rectifier  112  includes the plurality of capacitors CP 21  to CP 2 N, CS 21  to CS 2 N and the plurality of NMOS transistors N 21 A, N 21 B to N 2 NA, N 2 NB. 
         [0135]      FIGS. 11   a  to  11   d  are diagrams illustrating the operation of a first voltage rectifier  111  according to a third embodiment of the present invention. 
         [0136]      FIG. 11   a  is a circuit diagram illustrating a portion ‘A’ of the first voltage rectifier  111  shown in  FIG. 10  or in  FIG. 13 .  FIG. 11   b  illustrates an input waveform of the radio signal received through the first antenna  11 .  FIG. 11   c  illustrates an output waveform of an A 1  partial circuit (hereinafter, A 1  circuit) shown in  FIG. 11   a.    FIG. 11   d  illustrates an output waveform of an A 2  partial circuit (hereinafter, A 2  circuit) shown in  FIG. 11   a.    
         [0137]    Referring to  FIG. 11   b,  an input radio signal Vin 1  has a sine wave varying in the range of −Vp 1  to Vp 1 . The input radio signal can be any waveform such as those including a sine wave, but a triangle wave, a square wave, or a step wave. 
         [0138]    The input radio signal becomes an input to the A 1  circuit. In the A 1  circuit, current flows when a NMOS transistor N 11 A is turned on while current does not flow when the NMOS transistor N 11 A is turned off. That is, only when the input radio signal has a negative voltage, the NMOS transistor N 11 A is turned on such that electric charges are accumulated in a capacitor CP 11 . As a result, the voltage as much as −(−Vp 1 )=Vp 1  is applied to the capacitor CP 11 . Accordingly, it becomes VCP 11 =Vp 1 . 
         [0139]    In  FIG. 11   a,  since it becomes Vin 1 +VCP 11 =V 11 , the signal V 11  has a waveform which is obtained by shifting Vin 1  by VCP 11  in parallel in the positive direction of the Y axis. As shown in  FIG. 11   c,  the signal V 11  has a sine wave varying in the range of 0 to 2 Vp 1 . In this case, the A 1  circuit operates as a clamping circuit because the lowest peak voltage of the output signal V 11  is clamped to 0 V. 
         [0140]    The signal V 11  becomes an input to the A 2  circuit. In the A 2  circuit, current flows when a NMOS transistor N 11 B is turned on while current does not flow when the NMOS transistor N 11 B is turned off. That is, only when the input signal V 11  has a positive voltage, the NMOS transistor N 11 B is turned on such that electric charges are accumulated in a capacitor CS 11 . 
         [0141]    When the electric charges are accumulated in the capacitor CS 11  and a potential difference greater than the peak voltage 2 Vp 1  of the input signal V 11  is applied across the capacitor CS 11 , the electric charges of the ferroelectric capacitor FCS 11  are not discharged because the NMOS transistor N 11 B is turned off. Accordingly, as shown in  FIG. 11   d,  a DC voltage having the magnitude of 2 Vp 1  is maintained substantially constant at node  11 . In this case, since the output signal V 1  is rectified into a DC voltage having the highest peak voltage of the input signal V 11 , the A 2  circuit operates as a rectification circuit. 
         [0142]    Thereafter, the above operation is repeatedly performed by the capacitors CP 12 , CS 22  and the NMOS transistors N 12 A, N 12 B. Since the voltage of the node  11  is 2 Vp, a DC voltage 2 Vp 1 +2 Vp 1 =4 Vp 1  is maintained substantially constant node  12 . 
         [0143]    As described above, as the rectification and boosting process is performed, a DC voltage N*2 Vp 1  is maintained substantially constant at node  1 N. Accordingly, the power voltage VDD 1  is generated, and it becomes VDD 1 =N*2 Vp 1 . 
         [0144]    Meanwhile, the present invention includes two antennas configured to receive different signals. Accordingly, the process of rectifying and boosting a radio signal received through the first antenna  11  can be identically applied to the case where a radio signal received through the second antenna  12  is rectified and boosted. 
         [0145]      FIGS. 12   a  to  12   d  are diagrams illustrating the operation of the second voltage rectifier  112  according to the third embodiment of the present invention. 
         [0146]      FIG. 12   a  is a circuit diagram illustrating a portion ‘B’ of the second voltage rectifier  112  shown in  FIG. 10  or in  FIG. 13 .  FIG. 12   b  illustrates an input waveform of the radio signal received through the second antenna  12 .  FIG. 12   c  illustrates an output waveform of a B 1  partial circuit (hereinafter, B 1  circuit) shown in  FIG. 12   a.    FIG. 12   d  illustrates an output waveform of a B 2  partial circuit (hereinafter, B 2  circuit) shown in  FIG. 12   a.    
         [0147]    Referring to  FIG. 12   b,  an input radio signal Vin 1  has a sine wave varying in the range of −Vp 1  to Vp 1 . The input radio signal can be any waveform such as those including a sine wave, but a triangle wave, a square wave, or a step wave. 
         [0148]    The input radio signal becomes an input to the B 1  circuit. In the B 1  circuit, current flows when the NMOS transistor N 21 A is turned on while current does not flow when the NMOS transistor N 21 A is turned off. That is, only when the input radio signal has a negative voltage, the NMOS transistor N 21 A is turned on such that electric charges are accumulated in a capacitor CP 21 . As a result, voltage as much as −(−Vp 1 )=Vp 2  is applied to the capacitor CP 21 . Accordingly, it becomes VCP 21 =Vp 2 . 
         [0149]    In  FIG. 12   a,  since it becomes Vin 2 +VCP 21 =V 21 , the signal V 21  has a waveform which is obtained by shifting Vin 2  by VCP 21  in parallel in the positive direction of the Y axis. As shown in  FIG. 12   c,  the output signal V 21  has a sine wave varying in the range of 0 to 2 Vp 2 . In this case, the B 1  circuit operates as a clamping circuit because the lowest peak voltage of the output signal V 21  is clamped to 0 V. 
         [0150]    The signal V 21  becomes an input to the B 2  circuit. In the B 2  circuit, current flows when the NMOS transistor N 21 B is turned on while current does not flow when the NMOS transistor N 21 B is turned off. That is, only when the input radio signal has a positive voltage, the NMOS transistor N 21 B is turned on such that electric charges are accumulated in a capacitor CS 21 . 
         [0151]    When the electric charges are accumulated in the capacitor CS 21  and a potential difference greater than the peak voltage 2 Vp 2  of the input signal V 21  is applied across the capacitor CS 21 , the electric charges of the capacitor CS 21  are not discharged because the NMOS transistor N 21 B is turned off. Accordingly, as shown in  FIG. 12   d,  a DC voltage having the magnitude of 2 Vp 2  is maintained substantially constant at node  21 . In this case, since the output signal V 2  is rectified into a DC voltage having the highest peak voltage of the input signal V 21 , the B 2  circuit operates as a rectification circuit. 
         [0152]    Thereafter, the above operation is repeatedly performed by the capacitors CP 22 , CS 22  and the NMOS transistor N 22 A, N 22 B. Since the voltage of the node  21  is 2 Vp 2 , a DC voltage 2 Vp 2 +2 Vp 2 =4 Vp 2  is maintained substantially constant at node  22 . 
         [0153]    As described above, as the rectification and boosting process is performed, a DC voltage N*2 Vp 1  is maintained substantially constant at node  2 N. Accordingly, the power voltage VDD 2  is generated, and it becomes VDD 2 =N*2 Vp 2 . 
         [0154]    Referring back to  FIG. 10 , the power voltages VDD 1  and VDD 2  generated by the first voltage rectifier  111  and the second voltage rectifier  112  become an input to the summation unit  130 . The summation unit  130  is configured to perform an operation of adding the power voltages VDD 1  and VDD 2  which are input signals. As a result, a power voltage VDD which is obtained by adding the power voltage VDD 1  to the power voltage VDD 2  is generated and outputted to the power-on reset unit  150 , the clock generation unit  160 , and the memory unit  300 . The summation unit  130  can be implemented with an op amplifier in various ways. 
         [0155]    The RFID tag of the present invention has two antennas coupled to each other in parallel. The cases where the two antennas receive radio signals can be classified into i) a case where only the first antenna  11  receives the radio signal, ii) a case where only the second antenna  12  receives the radio signal, and iii) a case where the first and second antennas receive the radio signals simultaneously. 
         [0156]    In the case of i), the power voltage VDD 1  is generated from the radio signal received by the first antenna  11  through the above-described rectification and boosting operation, and it becomes VDD=VDD 1 . 
         [0157]    In the case of ii), the power voltage VDD 2  is generated from the radio signal received by the second antenna  12  through the above-described rectification and boosting operation, and it becomes VDD=VDD 2 . 
         [0158]    In the case of iii), since the first and second antennas  11  and  12  receive the radio signals simultaneously, the power voltages VDD 1  and VDD 2  are generated through the above-described rectification and boosting operation, and it becomes VDD=VDD 1 +VDD 2 . 
         [0159]      FIG. 13  is a circuit diagram illustrating a modulation/demodulation unit  120  according to the third embodiment of the present invention. 
         [0160]    Referring to  FIG. 13 , the radio signals received through the first antenna  11  and the second antenna  12  are respectively inputted to the first demodulator  1211  and the second demodulator  1221 . The first demodulator  1211  demodulates the radio signal received from the first antenna  11 , detects and outputs a reception signal RX 1 , which is an operation command signal, from the radio signal. The second demodulator  1221  demodulates the radio signal received from the second antenna  12 , detects and outputs a reception signal RX 2 , which is an operation command signal, from the radio signal. 
         [0161]    The logical sum device  140  is configured to logically sum the reception signal RX 1  and the reception signal RX 2  and generate a reception signal RX. The reception signal RX is inputted to the digital unit  200 . 
         [0162]    The logical sum device  140  can be implemented with an OR gate. That is, the logical sum device  140  outputs the reception signal RX of high level although any one of the reception signals RX 1  and RX 2  has a high level. 
         [0163]      FIG. 14  is a detailed circuit diagram illustrating a voltage rectification unit and a summation unit according to a third embodiment of the present invention; 
         [0164]    The voltage rectification unit  110  according to the present embodiment includes a first voltage rectifier  111  and a second voltage rectifier  112 . The first voltage rectifier  111  includes a plurality of ferroelectric capacitors FCS 11  to FCS 1 N, FCP 11  to FCP 1 N and a plurality of NMOS transistors N 11 A, N 11 B to N 1 NA, N 1 NB. The second voltage rectifier  112  includes a plurality of ferroelectric capacitors FCS 21  to FCS 2 N, FCP 21  to FCP 2 N and a plurality of NMOS transistors N 21 A, N 21 B to N 2 NA, N 2 NB. 
         [0165]    The plurality of NMOS transistors N 11 A, N 11 B to N 1 NA, N 1 NB and the plurality of NMOS transistors N 21 A, N 21 B to N 2 NA, N 2 NB are used as rectification components. The NMOS transistors can be implemented using PN-type or NP-type NMOS transistors. 
         [0166]    The first antenna  11  performs NF RFID communication carried out in accordance with Faraday&#39;s law of induction. The NF RFID communication is a communication method using a low frequency domain of 1 MHz or less. This communication method preferably operates in the distance of 50 cm or less. 
         [0167]    The second antenna  12  performs FF RFID communication carried out in accordance with the principle of electromagnetic energy. The FF RFID communication is a communication method using a high frequency domain of 100 MHz or more. The communication method preferably operates in the distance of 50 cm or more. 
         [0168]    According to the present invention, radio signals can be transceived irrespective of the distance between the RF reader and the RF tag because the radio signals are received from the first antenna  11  and the second antenna  12 . 
         [0169]    The radio signals received through the first antenna  11  and the second antenna  12  are inputted to the voltage rectification unit  110 . In detail, the radio signal received from the first antenna  11  is rectified and boosted by the first voltage rectifier  111 , and the radio signal received from the second antenna  12  is rectified and boosted by the second voltage rectifier  112 . 
         [0170]    Referring to  FIG. 14 , the first voltage rectifier  111  includes the plurality of ferroelectric capacitors FCP 11  to FCP 1 N, FCS 11  to FCS 1 N and the plurality of NMOS transistors N 11 A, N 11 B to N 1 NA, N 1 NB. The second voltage rectifier  112  includes the plurality of ferroelectric capacitors FCP 21  to FCP 2 N, FCS 21  to FCS 2 N and the plurality of NMOS transistors N 21 A, N 21 B to N 2 NA, N 2 NB. 
         [0171]      FIGS. 15   a  to  15   d  are diagrams illustrating the operation of the first voltage rectifier  111  according to the fourth embodiment of the present invention. 
         [0172]      FIG. 15   a  is a circuit diagram illustrating a portion ‘A’ of the first voltage rectifier  111  shown in  FIG. 14  or in  FIG. 17 .  FIG. 15   b  illustrates an input waveform of the radio signal received through the first antenna  11 .  FIG. 15   c  illustrates an output waveform of a A 1  partial circuit (hereinafter, A 1  circuit) shown in  FIG. 15   a.    FIG. 15   d  illustrates an output waveform of a A 2  partial circuit (hereinafter, A 2  circuit) shown in  FIG. 15   a.    
         [0173]    Referring to  FIG. 15   b,  an input radio signal has a sine wave varying in the range of −Vp 1  to Vp 1 . The input radio signal can be any waveform such as those including a sine wave, but a triangle wave, a square wave, or a step wave. 
         [0174]    The input radio signal becomes an input to the A 1  circuit. In the A 1  circuit, current flows when the NMOS transistor N 11 A is turned on while current does not flow when the NMOS transistor N 11 A is turned off. That is, only when the input radio signal has a negative voltage, the NMOS transistor N 11 A is turned on such that electric charges are accumulated in a ferroelectric capacitor FCP 11 . As a result, voltage as much as −(−Vp 1 )=Vp 1  is applied to the ferroelectric capacitor FCP 11 . Accordingly, it becomes VCP 11 =Vp 1 . 
         [0175]    In  FIG. 15   a,  since it becomes Vin 1 +VCP 11 =V 11 , the signal V 11  has a waveform which is obtained by shifting Vin 1  by VCP 11  in parallel in the positive direction of the Y axis. As shown in  FIG. 15   c,  the signal V 11  has a sine wave varying in the range of 0 to 2 Vp 1 . In this case, the A 1  circuit operates as a clamping circuit because the lowest peak voltage of the output signal V 11  is clamped to 0 V. 
         [0176]    The signal V 11  becomes an input to the A 2  circuit. In the A 2  circuit, current flows when the NMOS transistor N 11 B is turned on while current does not flow when the NMOS transistor N 11 B is turned off. That is, only when the input radio signal has a positive voltage, the NMOS transistor N 11 B is turned on such that electric charges are accumulated in a ferroelectric capacitor FCS 11 . 
         [0177]    When the electric charges are accumulated in the ferroelectric capacitor FCS 11  and a potential difference greater than the peak voltage 2 Vp 1  of the input signal V 11  is applied across the ferroelectric capacitor FCS 11 , the electric charges of the ferroelectric capacitor FCS 11  are not discharged because the NMOS transistor N 21 B is turned off. Accordingly, as shown in  FIG. 15   d,  a DC voltage having the magnitude of 2 Vp 1  is maintained substantially constant at node  11 . In this case, since the output signal V 1  is rectified into a DC voltage having the highest peak voltage of the input signal V 11 , the A 2  circuit operates as a rectification circuit. 
         [0178]    Thereafter, the above operation is repeatedly performed by the ferroelectric capacitor FCP 12 , FCS 12  and the NMOS transistor N 12 A, N 12 B. Since the voltage of the node  11  is 2 Vp 1 , a DC voltage 2 Vp 1 +2 Vp 1 =4 Vp 1  is maintained substantially constant at node  12 . 
         [0179]    As described above, as the rectification and boosting process is performed, a DC voltage N*2 Vp 1  is maintained substantially constant at node  1 N. Accordingly, the power voltage VDD 1  is generated, and it becomes VDD 1 =N*2 Vp 1 . 
         [0180]    Meanwhile, the present invention includes two antennas configured to receive different signals. Accordingly, the process of rectifying and boosting a radio signal received through the first antenna  11  can be identically applied to a case where a radio signal received through the second antenna  12  is rectified and boosted. 
         [0181]      FIGS. 16   a  to  16   d  are diagrams illustrating the operation of the second voltage rectifier  112  according to the fourth embodiment of the present invention. 
         [0182]      FIG. 16   a  is a circuit diagram illustrating a portion ‘B’ of the second voltage rectifier  112  shown in  FIG. 14  or in  FIG. 17 .  FIG. 16   b  illustrates an input waveform of the radio signal received through the second antenna  12 .  FIG. 16   c  illustrates an output waveform of a B 1  partial circuit (hereinafter referred to as a ‘B 1  circuit’) shown in  FIG. 16   a .  FIG. 16   d  illustrates the output waveform of a B 2  partial circuit (hereinafter referred to as a ‘B 2  circuit’) shown in  FIG. 16   a.    
         [0183]    Referring to  FIG. 16   b,  an input radio signal Vin 2  has a sine wave varying in the range of −Vp 2  to Vp 2 . The input radio signal may have any waveform such as those including a sine wave, but a triangle wave, a square wave, or a step wave. 
         [0184]    The input radio signal becomes an input to the B 1  circuit. In the B 1  circuit, current flows when a NMOS transistor N 21 A is turned on while current does not flow when the NMOS transistor N 21 A is turned off. That is, only when the input radio signal has a negative voltage, the NMOS transistor N 21 A is turned on such that electric charges are accumulated in a ferroelectric capacitor FCP 21 . As a result, the voltage as much as −(−Vp 2 )=Vp 2  is applied to ferroelectric capacitor FCP 21 . Accordingly, it becomes VFCP 21 =Vp 2 . 
         [0185]    In  FIG. 16   a,  since it becomes Vin 2 +VFCP 21 =V 21 , the signal V 21  has a waveform which is obtained by shifting Vin 2  by VFCP 21  in parallel in the positive direction of the Y axis. As shown in  FIG. 16   c,  the signal V 21  has a sine wave varying in the range of 0 to 2 Vp 2 . In this case, the B 1  circuit operates as a clamping circuit because the lowest peak voltage of the output signal V 21  is clamped to 0 V. 
         [0186]    The signal V 21  becomes an input to the B 2  circuit. In the B 2  circuit, current flows when a NMOS transistor N 21 B is turned on while current does not flow when the NMOS transistor N 21 B is turned off. That is, only when the input radio signal has a positive voltage, the NMOS transistor N 21 B is turned on such that electric charges are accumulated in a ferroelectric capacitor FCS 21 . 
         [0187]    When the electric charges are accumulated in the ferroelectric capacitor FCS 21  and a potential difference greater than the peak voltage 2 Vp 2  of the input signal V 21  is applied across ferroelectric capacitor FCS 21 , the electric charges of ferroelectric capacitor FCS 21  are not discharged because the NMOS transistor N 21 B is turned off. Accordingly, as shown in  FIG. 16   d,  a DC voltage having the magnitude of 2 Vp 2  is maintained substantially constant at node  21 . In this case, since the output signal V 2  is rectified into a DC voltage having the highest peak voltage of the input signal V 21 , the A 2  circuit operates as a rectification circuit. 
         [0188]    Thereafter, the above operation is repeatedly performed by the ferroelectric capacitor FCP 22 , FCS 22  and the NMOS transistors N 22 A, N 22 B. Since the voltage of the node  21  is 2 Vp 2 , a DC voltage 2 Vp 2 +2 Vp 2 =4 Vp 2  is maintained substantially constant at node  22 . 
         [0189]    As described above, as the rectification and boosting process is performed, a DC voltage N*2 Vp 2  is maintained substantially constant at node  2 N. Accordingly, the power voltage VDD 2  is generated, and it becomes VDD 2 =N*2 Vp 2 . 
         [0190]    Referring back to  FIG. 14 , the power voltages VDD 1  and VDD 2  generated by the first voltage rectifier  111  and the second voltage rectifier  112  become an input to the summation unit  130 . The summation unit  130  is configured to perform an operation of adding the power voltages VDD 1  and VDD 2  which are input signals. As a result, a power voltage VDD which is obtained by adding the power voltage VDD 1  to the power voltage VDD 2  is generated and outputted to the power-on reset unit  150 , the clock generation unit  160 , and the memory unit  300 . The summation unit  130  can be implemented with an op amplifier in various ways. 
         [0191]    The RFID tag of the present invention has two antennas coupled to each other in parallel. The cases where the two antennas receive radio signals can be classified into i) a case where only the first antenna  11  receives the radio signal, ii) a case where only the second antenna  12  receives the radio signal, and iii) a case where the first and second antennas receive the radio signals simultaneously. 
         [0192]    In the case of i), the power voltage VDD 1  is generated from the radio signal received by the first antenna  11  through the above-described rectification and boosting operation, and it becomes VDD=VDD 1 . 
         [0193]    In the case of ii), the power voltage VDD 2  is generated from the radio signal received by the second antenna  12  through the above-described rectification and boosting operation, and it becomes VDD=VDD 2 . 
         [0194]    In the case of iii), since the first and second antennas  11  and  12  receive the radio signals simultaneously, the power voltages VDD 1  and VDD 2  are generated through the above-described rectification and boosting operation, and it becomes VDD=VDD 1 +VDD 2 . 
         [0195]      FIG. 17  is a circuit diagram illustrating a modulation/demodulation unit  120  according to the fourth embodiment of the present invention. 
         [0196]    Referring to  FIG. 17 , the radio signals received through the first antenna  11  and the second antenna  12  are respectively inputted to the first demodulator  1211  and the second demodulator  1221 . The first demodulator  1211  demodulates the radio signal received from the first antenna  11 , detects and outputs a reception signal RX 1 , which is an operation command signal, from the radio signal. The second demodulator  1221  demodulates the radio signal received from the second antenna  12 , detects and outputs a reception signal RX 2 , which is an operation command signal, from the radio signal. 
         [0197]    The logical sum device  140  is configured to logically sum the reception signal RX 1  and the reception signal RX 2  and generate a reception signal RX. The reception signal RX is inputted to the digital unit  200 . 
         [0198]    The logical sum device  140  can be implemented with an OR gate. That is, the logical sum device  140  outputs the reception signal RX of high level although any one of the reception signals RX 1  and RX 2  has a high level. 
         [0199]      FIG. 18  is a circuit diagram of the driving unit  170  and the modulation/demodulation unit  120  according to the present invention. 
         [0200]    Referring to  FIG. 18 , the transmission signal TX outputted from the digital unit  200  is inputted to the driving unit  170 . The driving unit  170  includes the first driver  171  and the second driver  172 . The first driver  171  generates the first transmission signal TX 1  in response to the input transmission signal TX. The second driver  172  generates the second transmission signal TX 2  in response to the input transmission signal TX. 
         [0201]    The first transmission signal TX 1  is inputted to the first modulator  1212 , and then, is modulated into a radio signal having a frequency of a first bandwidth. The second transmission signal TX 2  is inputted to the second modulator  1222 , and then, is modulated into a radio signal having a frequency of a second bandwidth. The modulated signals are sent to a RFID reader through the first antenna  11  and the second antenna  12  respectively. 
         [0202]    The above embodiments of the present invention are illustrative and not limitative. Various alternatives and equivalents are possible. The invention is not limited by the type of deposition, etching polishing, and patterning steps describe herein. Nor is the invention limited to any specific type of semiconductor device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.