Abstract:
According to the present invention, there is provided an image decoding apparatus having: a table selection controller configured to output a syntax selection signal which selects one of a prefix level_prefix, a suffix level_suffix, and a TrailingOnes syntax; a variable-length code decoding device configured to receive a bit stream, the syntax selection signal, and a suffix length suffixLength, and, by using data contained in the bit stream and the suffix length suffixLength, simultaneously decode the prefix level_prefix and the suffix level_suffix and output the result if the syntax selection signal selects the prefix level_prefix and the suffix level_suffix, and decode the TrailingOnes syntax and output the result if the syntax selection signal selects the TrailingOnes syntax; a level formation device configured to receive the decoded prefix level_prefix, the decoded suffix level_suffix, and the decoded TrailingOnes syntax, and form and output a level; and a suffix length updating device configured to receive the decoded prefix level_prefix, the decoded suffix level_suffix, and the decoded TrailingOnes syntax, and update the suffix length suffixLength.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
       [0001]    This application is based upon and claims benefit of priority under 35 USC §119 from the Japanese Patent Application No. 2007-87822, filed on Mar. 29, 2007, the entire contents of which are incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    The present invention relates to an image decoding apparatus and decoding method and, more particularly, to an image decoding apparatus and decoding method suitable for decoding image data encoded by the H.264 format. 
         [0003]    The international standardized encoding methods such as MPEG-4 are known as motion image encoding techniques, and ITU-Rec. H.264 Advanced Video Coding ISO/ITE International Standard 14496-10 (MPEG-4 AVC) abbreviated as H.264 is known as a new encoding method. 
         [0004]    A variable-length code decoding device decodes a prefix level_prefix and suffix level_suffix by the following procedure. First, a table selection controller outputs a syntax selection signal so as to select a TrailingOnes syntax from the syntaxes level_prefix, level_suffix, and TrailingOnes. Accordingly, the variable-length code decoding device outputs the TrailingOnes syntax. 
         [0005]    Then, the table selection controller outputs a syntax selection signal so as to select the prefix level_prefix syntax. The variable-length code decoding device outputs the prefix level_prefix by using a predetermined table. 
         [0006]    A suffix level_suffix decoding determination device receives the decoded prefix level_prefix, and determines the presence/absence of the suffix level_suffix in accordance with the manual of H.264. The suffix level_suffix decoding determination device outputs the result to the table selection controller. 
         [0007]    On the basis of this result, if the suffix level_suffix exists, the table selection controller outputs a syntax selection signal so as to select the suffix level_suffix. On the basis of a suffix length suffixLength output from a device for updating the suffix length suffixLength, the variable-length code decoding device decodes the suffix length suffixLength by using a predetermined table. 
         [0008]    On the other hand, a level formation device calculates a level by using the syntaxes (TrailingOnes, prefix level_prefix, and suffix level_suffix) output from the variable-length code decoding device, and outputs the result to a suffix length (suffixLength) updating device. 
         [0009]    The suffix length (suffixLength) updating device updates the suffix length suffixLength by using the value of the level output from the level formation device, and prepares for decoding the next suffix level_suffix. 
         [0010]    When decoding the prefix level_prefix and suffix level_suffix by using the arrangement as described above, however, if the suffix level_suffix exists, the prefix level_prefix is first decoded, and then the suffix level_suffix is decoded by using the decoding result. That is, two cycles are required. This means that decoding of one residual data requires two cycles. 
         [0011]    The residual data occupies most of the encoded image data. If the number of decoding cycles of this residual data increases, therefore, the operational frequency necessary for the required decoding performance of the system must be raised. This unavoidably increases the power consumption. 
         [0012]    A reference disclosing the conventional image decoding technique is as follows. 
         [0013]    Japanese Patent Laid-Open No. 2006-157157 
       SUMMARY OF THE INVENTION 
       [0014]    According to one aspect of the invention, there is provided an image decoding apparatus comprising: a table selection controller configured to output a syntax selection signal which selects one of a prefix level_prefix, a suffix level_suffix, and a TrailingOnes syntax; a variable-length code decoding device configured to receive a bit stream, the syntax selection signal, and a suffix length suffixLength, and, by using data contained in the bit stream and the suffix length suffixLength, simultaneously decode the prefix level_prefix and the suffix level_suffix and output the result if the syntax selection signal selects the prefix level_prefix and the suffix level_suffix, and decode the TrailingOnes syntax and output the result if the syntax selection signal selects the TrailingOnes syntax; a level formation device configured to receive the decoded prefix level_prefix, the decoded suffix level_suffix, and the decoded TrailingOnes syntax, and form and output a level; and a suffix length updating device configured to receive the decoded prefix level_prefix, the decoded suffix level_suffix, and the decoded TrailingOnes syntax, and update the suffix length suffixLength. 
         [0015]    According to one aspect of the invention, there is provided a method of performing an image decoding process by using an image decoding apparatus including a table selection controller, a variable-length code decoding device, a level formation device, and a suffix length updating device, the method comprising: outputting a syntax selection signal which selects one of a prefix level_prefix, a suffix level_suffix, and a TrailingOnes syntax, by using the table selection controller; receiving a bit stream, the syntax selection signal, and a suffix length suffixLength, and, by using data contained in the bit stream and the suffix length suffixLength, simultaneously decoding the prefix level_prefix and the suffix level_suffix and outputting the result if the syntax selection signal selects the prefix level_prefix and the suffix level_suffix, and decoding the TrailingOnes syntax and outputs the result if the syntax selection signal selects the TrailingOnes syntax, by using the variable-length code decoding device; receiving the decoded prefix level_prefix, the decoded suffix level_suffix, and the decoded TrailingOnes syntax, and forming and outputting a level, by using the level formation device; and receiving the decoded prefix level_prefix, the decoded suffix level_suffix, and the decoded TrailingOnes syntax, and updating the suffix length suffixLength, by using the suffix length updating device. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]      FIG. 1  is a block diagram showing the arrangement of an image decoding apparatus according to an embodiment of the present invention; 
           [0017]      FIG. 2  is a circuit diagram showing the arrangement of a variable-length code decoding device in the image decoding apparatus; 
           [0018]      FIGS. 3 to 9  are views for explaining examples of tables to be used in the variable-length code decoding device when a suffix length suffixLength is 0 to 6; 
           [0019]      FIG. 10  is a flowchart showing the procedure of processing performed by a suffix length (suffixLength) updating device in the image decoding apparatus; 
           [0020]      FIG. 11  is a circuit diagram showing an example of the arrangement of the suffix length (suffixLength) updating device; 
           [0021]      FIG. 12  is a circuit diagram showing an example of the arrangement of a comparator A in the suffix length (suffixLength) updating device; 
           [0022]      FIGS. 13 to 16  are circuit diagrams showing examples of the arrangements of multiplexers A to D in the suffix length (suffixLength) updating device; and 
           [0023]      FIG. 17  is a block diagram showing the arrangement of an image decoding apparatus according to a comparative example. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0024]    An embodiment of the present invention will be explained below with reference to the accompanying drawings. 
         [0025]      FIG. 1  shows the arrangement of an image decoding apparatus according to the embodiment of the present invention. This apparatus comprises a FIFO (First In First Out) device  101 , variable-length code decoding device  102 , level formation device  103 , suffix length (suffixLength) updating device  104 , and table selection controller  105 . The operation of the apparatus will be described later. 
         [0026]    As shown in, e.g.,  FIG. 2 , the variable-length code decoding device  102  comprises prefix level_prefix/suffix level_suffix tables  201  to  207 , a TrailingOnes table  210 , and multiplexers  208   a ,  208   b ,  209   a , and  209   b.    
         [0027]    A bit stream is supplied to the prefix level_prefix/suffix level_suffix tables  201  to  207  and TrailingOnes table  210 . The tables  201  to  207  each supply the values of a prefix level_prefix and suffix level_suffix to the multiplexer  208   a , and each supply the corresponding code length to the multiplexer  208   b.    
         [0028]    The suffix length (suffixLength) updating device  104  supplies an updated value of the suffix length suffixLength to the multiplexers  208   a  and  208   b . The values of the prefix level_prefix and suffix level_suffix output from a corresponding one of the tables  201  to  207  are supplied to the multiplexer  209   a , and the code length output from the corresponding one of the tables  201  to  207  is supplied to the multiplexer  209   b.    
         [0029]    In this case, a syntax selection signal is supplied to the multiplexers  209   a  and  209   b  so as to select the prefix level_prefix and suffix level_suffix. The values of the prefix level_prefix and suffix level_suffix are output to the level formation device  103 , and the code length of the prefix level_prefix and suffix level_suffix is output to the FIFO device  101 . 
         [0030]    The prefix level_prefix/suffix level_suffix tables  201  to  207  respectively have arrangements as shown in  FIGS. 3 to 9  in accordance with values “0” to “6” of the suffix length suffixLength. 
         [0031]    For example, when the value of the suffix length suffixLength is “0”, as shown in  FIG. 3 , values corresponding to a bit position when a value “1” initially exists in the leading portion of the bit stream are allocated to the prefix level_prefix and suffix level_suffix. In this example, if “1” exists in the first bit position of the bit stream, the value of the prefix level_prefix is “0”, the value of the suffix level_suffix is “none”, and the code length is “1”. If “0” continues from the first to nth (n is an integer of 1 or more) bit positions and “1” exists in the (n+1)th bit position of the bit stream, the value of the prefix level_prefix is “n”, the value of the suffix level_suffix is “none”, and the code length is “n+1”. 
         [0032]    When the value of the suffix length suffixLength is “1”, as shown in  FIG. 4 , if “1” exists in the first bit position of the bit stream, the value of the prefix level_prefix is “0”, the value of the suffix level_suffix is “none”, and the code length is “1”. If “0” continues from the first to 13th bit positions and “1” exists in the 14th bit position of the bit stream, the value of the prefix level_prefix is “13”, the value of the suffix level_suffix is “none”, and the code length is “14”. If “0” continues from the first to 14th bit positions and “1” exists in the 15th bit position of the bit stream (the 16th value can be either 0 or 1), the value of the prefix level_prefix is “14”, the value of the suffix level_suffix is the same as that in the 15th bit position, and the code length is “16”. This similarly applies to the cases where the values of the suffix length suffixLength are “2” to “5”, so a repetitive explanation will be omitted. 
         [0033]    When the value of the suffix length suffixLength is “6”, for example, as shown in  FIG. 9 , if “0” continues from the first to 15th bit positions and “1” exists in the 16th bit position of the bit stream (the value in the 17th to 22nd bit positions can be either 0 or 1), the value of the prefix level_prefix is “15”, the value of the suffix level_suffix is the same as that in the 17th to 22nd bit positions, and the code length is “22”. 
         [0034]    The suffix length (suffixLength) updating device  104  receives the prefix level_prefix, suffix level_suffix, and TrailingOnes syntax, and updates the suffix length suffixLength. More specifically, the suffix length (suffixLength) updating device  104  maintains the current suffix length suffixLength or increments it by “1”. 
         [0035]    The procedure of the suffix length (suffixLength) updating device  104  will be explained below with reference to a flowchart shown in  FIG. 10 . 
         [0036]    In step S 10 , the suffix length (suffixLength) updating device  104  checks whether the suffix length suffixLength is less than 6. If the result is true (Yes), the process advances to step S 11 . If the result is false (No), the suffix length (suffixLength) updating device  104  maintains the current suffix length suffixLength and outputs it as an updated value. 
         [0037]    In step S 11 , the suffix length (suffixLength) updating device  104  checks whether the prefix level_prefix is less than 8. If the result is true, the process advances to step S 12 . If the result is false, the suffix length (suffixLength) updating device  104  increments the current suffix length suffixLength by “1”, and outputs the incremented value as an updated value. 
         [0038]    In step S 12 , the suffix length (suffixLength) updating device  104  checks whether the TrailingOnes syntax is input immediately after decoding and less than 3. The process advances to step S 13  if the result is true, and to step S 16  if the result is false. 
         [0039]    In step S 13 , the suffix length (suffixLength) updating device  104  checks whether the suffix length suffixLength is 0. The process advances to step S 14  if the result is true, and to step S 15  if the result is false. 
         [0040]    Also, in step S 16 , the suffix length (suffixLength) updating device  104  checks whether the suffix length suffixLength is 0. The process advances to step S 17  if the result is true, and advances to step S 18  if the result is false. 
         [0041]    In step S 14 , the suffix length (suffixLength) updating device  104  checks whether the prefix level_prefix is larger than 3. If the result is true, the suffix length (suffixLength) updating device  104  increments the current suffix length suffixLength by “1”, and outputs the incremented value. If the result is false, the suffix length (suffixLength) updating device  104  maintains and outputs the current suffix length suffixLength. 
         [0042]    In step S 15 , the suffix length (suffixLength) updating device  104  checks whether the prefix level_prefix is larger than 1. If the result is true, the suffix length (suffixLength) updating device  104  increments the current suffix length suffixLength by “1”, and outputs the incremented value. If the result is false, the suffix length (suffixLength) updating device  104  maintains and outputs the current suffix length suffixLength. 
         [0043]    In step S 17 , the suffix length (suffixLength) updating device  104  checks whether the prefix level_prefix is larger than 5. If the result is true, the suffix length (suffixLength) updating device  104  increments the current suffix length suffixLength by “1”, and outputs the incremented value. If the result is false, the suffix length (suffixLength) updating device  104  maintains and outputs the current suffix length suffixLength. 
         [0044]    In step S 18 , the suffix length (suffixLength) updating device  104  checks whether the prefix level_prefix is larger than 3. If the result is true, the suffix length (suffixLength) updating device  104  increments the current suffix length suffixLength by “1”, and outputs the incremented value. If the result is false, the suffix length (suffixLength) updating device  104  maintains and outputs the current suffix length suffixLength. 
         [0045]      FIG. 11  shows an example of a practical circuit configuration of the suffix length (suffixLength) updating device  104  that performs the processing as described above. The device  104  comprises comparators A  301 ,  302 ,  311 , and  312 , multiplexers A  303  and  313 , a multiplexer B  321 , a multiplexer C  322 , and a multiplexer D  323 . 
         [0046]    The comparators A  301 ,  302 ,  311 , and  312  each have, e.g., the same arrangement as that of a multiplexer  401  shown in  FIG. 12 . Each comparator compares the prefix level_prefix with a predetermined input value (e.g., “3” for the comparator A  301 ). Also, each comparator receives values “1” and “0”, and outputs “1” if the result is true, and “0” if the result is false. 
         [0047]    The multiplexers A  303  and  313  each have, e.g., the same arrangement as that of a multiplexer  402  shown in  FIG. 13 . Each multiplexer receives values “a” and “b” from the input stage, and checks whether the suffix length suffixLength is 0. The multiplexer outputs “a” if the result is true, and “b” if the result is false. 
         [0048]    The multiplexer B  321  has the same arrangement as that of a multiplexer  403  shown in  FIG. 14 . The multiplexer B  321  receives values “a” and “b” from the input stage, and checks whether the TrailingOnes syntax is input immediately after decoding and larger than 3. The multiplexer B  321  outputs “a” if the result is true, and “b” if the result is false. 
         [0049]    The multiplexer C  322  has, e.g., the same arrangement as that of a multiplexer  404  shown in  FIG. 15 . The multiplexer C  322  receives values “a” and “b” from the input stage, and checks whether the prefix level_prefix is less than 8. The multiplexer C  322  outputs “a” if the result is true, and “b” if the result is false. 
         [0050]    The multiplexer D  323  has, e.g., the same arrangement as that of a multiplexer  405  shown in  FIG. 16 . The multiplexer D  323  receives values “a” and “b” from the input stage, and checks whether the suffix length suffixLength is less than 6. The multiplexer D  323  outputs “a” if the result is true, and “b” if the result is false. 
         [0051]    The operation of the suffix length (suffixLength) updating device  104  having the above arrangement will be explained below with reference to  FIG. 11 . Note that the order of processes is partially different from that of the procedure shown in the flowchart of  FIG. 10  because the operational speed can be increased by performing the parallel processing of the comparators A  301 ,  302 ,  311 , and  312  and the multiplexers  303  and  313  as earlier as possible, but the obtained result remains the same. Note also that the practical circuit configurations shown in  FIGS. 11 and 12  to  16  are merely examples and can be variously modified when implementing the flowchart shown in  FIG. 10 . 
         [0052]    The comparator A  301  checks whether the prefix level_prefix is larger than 3, and outputs “1” if the result is true, and “0” if the result is false. Similarly, the comparator A  302  checks whether the prefix level_prefix is larger than 1, the comparator A  311  checks whether the prefix level_prefix is larger than 5, and the comparator A  312  checks whether the prefix level_prefix is larger than 3. Each comparator A outputs “1” if the result is true, and “0” if the result is false. 
         [0053]    If the suffix length suffixLength is 0 in the multiplexer A  303 , the multiplexer A  303  selectively outputs the output value from the comparator A  301  from the values output from the comparators A  301  and  302 . If the suffix length suffixLength is not 0, the multiplexer A  303  selectively outputs the output value from the comparator A  302 . 
         [0054]    Likewise, if the suffix length suffixLength is 0 in the multiplexer A  313 , the multiplexer A  313  selectively outputs the output value from the comparator A  311  from the values output from the comparators A  311  and  312 . If the suffix length suffixLength is not 0, the multiplexer A  313  selectively outputs the output value from the comparator A  312 . 
         [0055]    The multiplexer B  321  checks whether the TrailingOnes syntax is input immediately after decoding and larger than 3. The multiplexer B  321  selectively outputs the output value from the multiplexer A  303  if the result is true, and the output value from the multiplexer A  313  if the result is false. 
         [0056]    The multiplexer C  322  checks whether the prefix level_prefix is less than 8. The multiplexer C  322  selectively outputs the output value from the multiplexer B  321  if the result is true, and “1” if the result is false. 
         [0057]    The multiplexer D  323  checks whether the prefix level_prefix is less than 6. The multiplexer D  323  selectively outputs the output value from the multiplexer C  322  if the result is true, and “0” if the result is false. 
         [0058]    The operation of the image processing apparatus according to this embodiment having the above arrangement will be explained below with reference to  FIG. 1 . 
         [0059]    The table selection controller  105  outputs a syntax selection signal so as to select the TrailingOnes syntax among other syntaxes. The FIFO device  101  receives an externally input bit stream, and outputs the bit stream in the input order by using the code length supplied from the variable-length code decoding device  102  as an output unit. 
         [0060]    As shown in  FIG. 2 , the variable-length code decoding device  102  decodes the TrailingOnes syntax by using the TrailingOnes table  210 , outputs the TrailingOnes syntax via the multiplexer  209   a , and outputs the code length of the TrailingOnes syntax via the multiplexer  209   b . The TrailingOnes syntax is supplied to the level formation device  103  and suffix length (suffixLength) updating device  104 . The code length is output to the FIFO device  101 . 
         [0061]    The table selection controller  105  outputs a syntax selection signal so as to select the prefix level_prefix and suffix level_suffix syntaxes. 
         [0062]    The variable-length code decoding device  102  receives the leading portion of the bit stream output from the FIFO device  101 , the updated suffix length suffixLength from the suffix length (suffixLength) updating device  104 , and the syntax selection signal from the table selection controller  105 . As shown in  FIG. 2 , on the basis of a bit position where a value “1” exists for the first time in the leading portion of the bit stream, the variable-length code decoding device  102  simultaneously decodes the prefix level_prefix, the suffix level_suffix, and their code length by using the prefix level_prefix/suffix level_suffix tables  201  to  207 . 
         [0063]    In accordance with the value of the suffix length suffixLength, the variable-length code decoding device  102  selectively outputs the corresponding prefix level_prefix/suffix level_suffix by using the multiplexer  208   a . Also, in accordance with the value of the suffix length suffixLength, the variable-length code decoding device  102  selectively outputs the corresponding code length by using the multiplexer  208   b.    
         [0064]    The variable-length code decoding device  102  outputs the prefix level_prefix and suffix level_suffix via the multiplexer  209   a , and outputs their code length via the multiplexer  209   b.    
         [0065]    In this manner, the variable-length code decoding device  102  outputs the TrailingOnes syntax, prefix level_prefix, and suffix level_suffix to the level formation device  103  and suffix length (suffixLength) updating device  104 , and the code length to the FIFO device  101 . 
         [0066]    The FIFO device  101  updates the bit stream by using the input code length. 
         [0067]    The level formation device  103  forms a level by using the input prefix level_prefix, suffix level_suffix, and TrailingOnes syntaxes, and outputs the level. 
         [0068]    The suffix length (suffixLength) updating device  104  updates the suffix length suffixLength, in accordance with the flowchart shown in  FIG. 10  or by using the circuit configuration shown in  FIG. 11 , by using the input prefix level_prefix, suffix level_suffix, and TrailingOnes syntax. The suffix length (suffixLength) updating device  104  outputs the updated suffix length suffixLength to the variable-length code decoding device  102 . 
         [0069]    As described above, this embodiment can simultaneously decode the prefix level_prefix and suffix level_suffix in one cycle. 
         [0070]    Consequently, the number of cycles required for the syntax decoding process decreases. Even when decoding a high-resolution (HD) image or the like, therefore, the operational frequency can be set lower than that in the conventional apparatus. This makes it possible to reduce the power consumption. 
         [0071]      FIG. 17  shows the arrangement of an image decoding apparatus according to a comparative example. 
         [0072]    A table selection controller  505  outputs a syntax selection signal to a variable-length code decoding device  502  so as to select a TrailingOnes syntax from a prefix level_prefix, a suffix level_suffix, and the TrailingOnes syntax. Accordingly, the variable-length code decoding device  502  outputs the TrailingOnes syntax. 
         [0073]    The table selection controller  505  outputs a syntax selection signal so as to select the prefix level_prefix. The variable-length code decoding device  502  outputs the prefix level_prefix by using a predetermined table. 
         [0074]    When receiving the decoded prefix level_prefix, a suffix (level_suffix) decoding determination device  506  determines the presence/absence of the suffix level_suffix in accordance with the manual of H.264, and outputs the result to the table selection controller  505 . 
         [0075]    If the result indicates that the suffix level_suffix exists, the table selection controller  505  outputs a syntax selection signal so as to select the suffix level_suffix. On the basis of a suffix length suffixLength output from a suffix length (suffixLength) updating device  504 , the variable-length code decoding device  502  decodes the suffix length suffixLength by using a predetermined table. 
         [0076]    On the other hand, a level formation device  503  calculates a level by using the syntaxes (TrailingOnes, prefix level_prefix, and suffix level_suffix) output from the variable-length code decoding device  502 , and outputs the result to the suffix length (suffixLength) updating device  504 . 
         [0077]    The suffix length (suffixLength) updating device  504  updates the suffix length suffixLength by using the value of the level output from the level formation device  503 , and outputs the result to the variable-length code decoding device  502 . 
         [0078]    When decoding the prefix level_prefix and suffix level_suffix in the image decoding apparatus according to the comparative example as described above, if the suffix level_suffix exists, it is necessary to first decode the prefix level_prefix and then decode the suffix level_suffix by using the decoding result, so two cycles are necessary. That is, decoding of one residual data requires two cycles. This increases the number of cycles required for the decoding process, thereby increasing the operational frequency and hence the power consumption. 
         [0079]    By contrast, the above embodiment can simultaneously decode the prefix level_prefix and suffix level_suffix in one cycle. Consequently, the power consumption can be reduced because the operational frequency can be set lower than that in the comparative example. 
         [0080]    As described above, the image decoding apparatus and decoding method of the above embodiment can decode the residual data (the prefix level_prefix and suffix level_suffix) at high speed and reduce the power consumption. 
         [0081]    The above embodiment is merely an example and hence does not limit the present invention. Accordingly, the present invention can be variously modified within the technical scope of the invention.