Abstract:
Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage.

Description:
RELATED APPLICATIONS 
     This is a continuation of U.S. application Ser. No. 13/542,250, titled “VOLTAGE SWITCHING IN A MEMORY DEVICE” filed Jul. 5, 2012 (allowed), which is a continuation of U.S. application Ser. No. 12/775,131 of the same title, filed May 6, 2010 and issued as U.S. Pat. No. 8,217,705 on Jul. 10, 2012, both applications commonly assigned and incorporated entirely herein by reference. 
    
    
     TECHNICAL FIELD 
     The present embodiments relate generally to memory and a particular embodiment relates to voltage switching in a memory device. 
     BACKGROUND 
     Flash memory devices have developed into a popular source of non-volatile memory for a wide range of applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, flash drives, digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems. 
     A flash memory is a type of non-volatile memory that can be erased and reprogrammed in blocks instead of one byte at a time. A typical flash memory comprises a memory array that includes a large number of memory cells. Changes in threshold voltage of the memory cells, through programming of charge storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data value of each cell. The cells are typically grouped into blocks. Each of the cells within a block can be electrically programmed, such as by charging the charge storage structure. The data in a cell of this type is determined by the presence or absence of the charge in the charge storage structure. The charge can be removed from the charge storage structure by an erase operation. 
     Certain memory operations in a non-volatile memory device use high voltages (e.g., greater than a device supply voltage) on the control gates of the memory cells. For example, programming memory cells might use voltages in the range of 15V-20V. These voltages need to be switched from the high voltage sources (e.g., charge pumps) to the various circuits of the memory device that need the high voltages. 
     Two circuit architectures are typically used to perform the high voltage switching in non-volatile memory devices: local pump high voltage switches (LPHVSW) and self-boosting high voltage switches (SBHVSW). Both of these architectures have their respective drawbacks. 
     An LPHVSW architecture, illustrated in  FIG. 1 , uses a local boosting charge pump  100  to generate the control voltage of a high voltage MOS pass transistor  101 . In this architecture, SW out =SW in −V thSHV  when V g  is boosted to SW in , where SW out  and SW in  are the output and input voltages respectively, and V thSHV  is the threshold voltage of the MOS transistor  101 . In order to obtain SW out =SW in , a V g  that is greater than SW in  is used. 
     This circuit generally drives large, critical parasitic elements that are sensitive to layout configurations, high voltages applied to some circuit nodes, and a clock generator with a switching speed that is dependent on a clock frequency. These drawbacks of the LPHVSW architecture can limit the performance of high voltage multiplexers, such as the global word line driver of a memory array. 
     An SBHVSW architecture, illustrated in  FIG. 2 , uses a combination of a high voltage depletion-mode NMOS transistor  200 , with a threshold voltage that is less than 0V, and a high voltage PMOS transistor  201 . In the illustrated circuit, when enb=0V, then SW out =SW in . Thus, this circuit provides reduced operational voltages compared to the circuit of  FIG. 1 . However, the circuit of  FIG. 2  lacks bi-directionality and experiences a reverse leakage of current when used in an SBHVSW voltage multiplexer. 
     For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a voltage switch with improved performance. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a schematic diagram of a typical prior art local pump high voltage switch circuit. 
         FIG. 2  shows a schematic diagram of a typical prior art self-boosting high voltage switch circuit. 
         FIG. 3  shows a schematic diagram of one embodiment of a high voltage switch circuit. 
         FIG. 4  shows a block diagram of one embodiment of a portion of a memory device configured to incorporate the high voltage switch circuit of the embodiment of  FIG. 3 . 
         FIG. 5  shows a block diagram of one embodiment of a memory system configured to incorporate the high voltage switch circuit of the embodiment of  FIG. 3 . 
     
    
    
     DETAILED DESCRIPTION 
     In the following detailed description, reference is made to the accompanying drawings that form a part hereof and in which is shown, by way of illustration, specific embodiments. In the drawings, like numerals describe substantially similar components throughout the several views. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense. 
       FIG. 3  illustrates a schematic diagram of one embodiment of a high voltage switch circuit based on level shift circuits. The illustrated embodiment is comprised of two switch circuits  320 ,  321  coupled in series. These circuits provide the switching of the SW IN  voltage to the SW OUT  output. A first level shift circuit  310  is coupled to an input of a first switch circuit  320 . A second level shift circuit  311  is coupled to an output of a second switch circuit  321 . An enable signal circuit  390  is coupled to the level shift circuits  310 ,  311  to provide the different states (e.g., a logical high component and a logical low component) of the enable signal to the various circuit components. 
     The level shift circuits  310 ,  311  drive the gates of the transistors of their respective switch circuits  320 ,  321 . For example, the first level shift circuit  310  (e.g., input level shift circuit) generates the NSW IN  and the PSW IN  signals. The NSW IN  signal drives the n-channel transistor N IN    330  and the PSW IN  signal drives the control gates of the p-channel transistors  360  of the first switch circuit  320  (e.g., input switch circuit). The second level shift circuit  311  (e.g., output level shift circuit) generates the NSW OUT  and the PSW OUT  signals. The NSW OUT  signal drives the n-channel transistor N OUT    331  and the PSW OUT  signal drives the control gates of the p-channel transistors  361  of the second switch circuit  321  (e.g., output switch circuit). 
     The level shift circuits  310 ,  311  have the relatively low voltage (e.g., 3V) signal inputs of ENOUT and ENOUTb and output the relatively high voltage (e.g., 20V) of SW IN  and SW OUT . Each level shift circuit  310 ,  311  includes two groups of series connected p-channel transistors  305 - 308 . The input level shift circuit  310  includes SHP 1   305  and SHP 2   306  while the output level shift circuit  311  includes SHP 3   307  and SHP 4   308 . 
     Each switch circuit  320 ,  321  and each level shift circuit  310 ,  311  are shown with four series coupled p-channel transistors in each circuit. This is only one possible embodiment for these circuits. Since each circuit has to drop a relatively large voltage (e.g., 20V) across the circuit, the greater the quantity of transistors in each circuit, the lower the maximum drain-to-source voltage (V DS ) experienced by each transistor. 
     The illustrated embodiment assumes a 20V input voltage that is to be switched. Thus, with four transistors in each circuit  310 ,  311 ,  320 ,  321 , each transistor is expected to experience a maximum V DS  of 5V. Fewer transistors can be used in each circuit  310 ,  311 ,  320 ,  321  assuming the transistor can withstand a larger V DS . In the alternative, a greater number of transistors may be used in each circuit  310 ,  311 ,  320 ,  321  in order to use transistors having a lower maximum V DS . Typically, these types of p-channel transistors can be less expensive to manufacture since they require no additional processing for high voltage source/drain diffusions. 
     The substantially identical switch circuits  320 ,  321  and the substantially identical level shift circuits  310 ,  311  provide the bi-directionality to the high voltage switch circuit. Because of the inherent diodes of each circuit  310 ,  311 ,  320 ,  321  between series connections of transistor pairs, the second switch circuit  321  and the second level shift circuit  311  provide current flow in the opposite direction from the first switch circuit  320  and the first level shift circuit  310 . At least one set of diodes of the circuits  310 ,  311 ,  320 ,  321  will thus be forward biased in one of two possible polarity situations (e.g., SW IN &gt;SW OUT  or SW IN &lt;SW OUT ). Additionally, when the switch circuit is turned off, a blocking series of diodes are reverse biased to provide leakage protection regardless of the voltage polarity between SW IN  and SW OUT . 
     The control signal SW EN  that turns the switch on and off can be provided by control logic. In one embodiment, SW EN  is at a logic high at 3V and a logic low at 0V. 
     Two modes of operation of the high voltage switch circuit are described subsequently. In the first mode, the switch is turned on and the voltage at SW IN  is passed on to SW OUT . SW OUT  may start at 0V and eventually rise to approximately SW IN  (within inherent losses of the activated transistors) if the load is capacitive. In the second mode, the switch is turned off and the voltage at SW IN  is not passed on to SW OUT . In this mode, SW OUT  remains substantially at 0V. An SW IN  of 20V is used subsequently in describing the operation of the high voltage switch circuit. This voltage is for purposes of illustration only as any voltage can be used. 
     The subsequent discussion assumes that SW IN &gt;SW OUT . However, the bi-directional nature of the switch allows the opposite to also be true. 
     Referring to  FIG. 3 , the switch is turned on by the control logic setting SW EN  to a logic high. This signal is applied to the first inverter  301  that generates the ENOUTb control signal at a logic low and the second inverter  302  that generates ENOUT at a logic high. 
     The logic low ENOUTb signal is applied to control transistors N 1   350  and N 4   353 . The logic low ENOUTb turns these transistors  350 ,  353  off. Thus, the SHP 1  series of transistors  305  and the SHP 4  series of transistors  308  are turned on so that NSW OUT =SW OUT  and NSW IN =SW IN =20V, which turns on n-channel transistors N IN    330  and N OUT    331 . 
     The logic high ENOUT signal is applied to control transistors N 2   351  and N 3   352 . The logic high ENOUT turns these transistors  351 ,  352  on. Thus, the SHP 2  series of transistors  306  and the SHP 3  series of transistors  307  are turned off so that PSW IN =0V and PSW OUT =0V. PSW IN  and PSW OUT  being at 0V turns on the switch circuits  320 ,  321  respectively. Current I SWITCH  flows from SW IN  to SW OUT  and the diodes associated with the transistors of the first switch circuit  320  are reverse biased. The diodes associated with the transistors of the second switch circuit  321  are forward biased but do not conduct provided that I SWITCH ×RdsON&lt;V be  where RdsON is the on resistance of each of the series coupled transistors of the second switch circuit  321 . 
     The switch is turned off by the control logic setting SW EN  to a logic low. In this mode, the input voltage is not switched to the output so that, in the illustrated embodiment, SW IN =20V and SW OUT =0V. 
     A logic low SW EN  signal results in a logic high ENOUTb signal from the first inverter  301  and a logic low ENOUT signal from the second inverter  302 . The logic high ENOUTb signal turns on control transistors N 1   350  and N 4   353 . Thus, the SHP 1   305  and SHP 4   308  series transistors are turned off so that PSW IN =SW IN =20V and PSW OUT =SW OUT . Since control transistors N 1   350  and N 4   353  are turned on, both NSW IN  and NSW OUT  are at 0V so that transistors N IN    330  and N OUT    331  are turned off, the switch circuits  320 ,  321  are turned off, and current I SWITCH  is not flowing. 
     The diodes associated with the transistors of the first switch circuit  320  are reverse biased. The diodes associated with the transistors of the second switch circuit  321  are forward biased. In this condition, the voltage difference SW IN −SW OUT =20V−0V=20V is almost entirely dropped across only the transistors of the first switch circuit  320 . These transistors of the first switch circuit  320  should therefore have a maximum V DS  capability greater than SW IN /(transistor quantity) in order to stop a breakdown that would cause a current flow through the switch. 
     The quantity of transistors that can be used in each of the switch circuits  320 ,  321  and level shift circuits  310 ,  311  can be determined by maximum voltage drop (V max ) across all of the transistors of each circuit  310 ,  311 ,  320 ,  321  divided by the maximum voltage that each transistor in each circuit can withstand (V dsmax ). In other words, V max /V dsmax . Therefore, the greater the quantity of transistors in each circuit, the lower the voltage drop across each transistor of each circuit. In the illustrated embodiment, the maximum voltage that the switch is to handle is SW IN =20V. If it is assumed that each transistor can withstand 5V prior to breakdown, the quantity of series coupled transistors in each circuit  310 ,  311 ,  320 ,  321  may be four or more. The embodiment of  FIG. 3  shows each circuit  310 ,  311 ,  320 ,  321  having the same number of transistors. However, alternate embodiments that use different SW IN  voltages and/or different transistors having a different V ds  may use different quantities in each switch and level shift circuit. 
       FIG. 4  illustrates a block diagram of one embodiment of a portion of a memory device incorporating the high voltage switch circuit of the embodiment of  FIG. 3 . In one embodiment, the memory device includes a non-volatile memory array  400  such as flash memory. 
     In one embodiment, the memory array  400  is comprised of a NAND architecture array of floating gate memory cells. Alternate embodiments can use other types of memory architecture including NOR and AND. The memory array  400  is comprised of a plurality of access lines (e.g., local word lines) LWL&lt;n:0&gt; and data lines (e.g., bit lines) BL&lt;m:0&gt;. Each end of the series string of memory cells of the array  400  includes a select gate transistor. One end of the series string has a select gate drain transistor that is controlled by the select gate drain (SGD) line. The other end of the series string has a select gate source transistor that is controlled by the select gate source (SGS) line. 
     The SGD, SGS, and LWL&lt;n:0&gt; lines are driven by a string driver block  401  that drives the voltages for these signals. A memory block high voltage selector  420  controls the switching of high voltages to the string driver  401 . The memory block high voltage selector  420  can incorporate a plurality of the high voltage switch circuits of the present disclosure. 
     An array driver  403  can also be comprised of a plurality of the high voltage switch circuits of the present disclosure. This array driver  403  is responsible for switching high voltages to the select gate drain, select gate source, and word lines of the memory array. The array driver  403  incorporates a global select gate drain driver  430 , a global word line driver  431 , and a global select gate source driver  432 . The global select gate drain driver  430  drives all of the select gate drain lines of the memory array  400 . The global select gate source driver  432  drives all of the select gate source lines of the memory array  400 . The global word line driver  431  drives all of the global word lines of the memory array  400 . 
     A global source line (GSRC) driver  411  controls the voltages applied to the source line of the memory array  400 . A tub driver  410  controls the voltages applied to the semiconductor tub in which the memory array  400  is located. 
     High voltage regulators  423  regulate the unregulated high voltage from the charge pump generators  424 . The regulated voltages from the regulators  423  are input over a high voltage bus  406  to the array driver  403  to be switched by the plurality of high voltage switch circuits of the present disclosure. The unregulated charge pump generator  424  voltages are also transferred, over a high voltage bus  405 , to the high voltage switch circuits of the memory block high voltage selector  420  and to the global source line driver  411  and tub driver  410 . 
       FIG. 5  illustrates a functional block diagram of a memory device  500  that can incorporate the embodiment of  FIG. 4 . The memory device  500  is coupled to an external processor  510 . The processor  510  may be a microprocessor or some other type of controller. The memory device  500  and the processor  510  form part of a memory system  520 . 
     The memory device  500  includes an array  530  of non-volatile memory cells. The memory array  530  is arranged in banks of word line rows and bit line columns. In one embodiment, the columns of the memory array  530  are comprised of series strings of memory cells. As is well known in the art, the connections of the cells to the bit lines determines whether the array is a NAND architecture, an AND architecture, a NOR architecture, or some other type of architecture. 
     Address buffer circuitry  540  is provided to latch address signals provided through I/O circuitry  560 . Address signals are received and decoded by a row decoder  544  and a column decoder  546  to access the memory array  530 . It will be appreciated by those skilled in the art, with the benefit of the present description, that the number of address input connections depends on the density and architecture of the memory array  530 . That is, the number of addresses increases with both increased memory cell counts and increased bank and block counts. 
     The memory device  500  reads data in the memory array  530  by sensing voltage or current changes in the memory array columns using sense amplifier circuitry  550 . The sense amplifier circuitry  550 , in one embodiment, is coupled to read and latch a row of data from the memory array  530 . Data input and output buffer circuitry  560  is included for bidirectional data communication as well as the address communication over a plurality of data connections  562  with the controller  510 . Write circuitry  555  is provided to write data to the memory array. 
     Memory control circuitry  570  decodes signals provided on control connections  572  from the processor  510 . These signals are used to control the operations on the memory array  530 , including data read, data write (program), and erase operations. The memory control circuitry  570  may be a state machine, a sequencer, or some other type of controller to generate the memory control signals. In one embodiment, the memory control circuitry  570  is configured to execute methods for switching high voltages in the memory device by controlling the high voltage switch circuit discussed previously. 
     The flash memory device illustrated in  FIG. 5  has been simplified to facilitate a basic understanding of the features of the memory. A more detailed understanding of internal circuitry and functions of flash memories are known to those skilled in the art. 
     CONCLUSION 
     In summary, one or more embodiments of the high voltage switch circuit switch voltages greater than a supply voltage from charge pumps to the memory array of a memory device. Two switch circuits, each comprised of groups of series coupled transistors, are coupled in series to provide bidirectional operation while the inherent diodes from the series connections provide blockage of leakage current when the switch is off. An input level shift circuit coupled to the input switch circuit and an output level shift circuit coupled to the output switch circuit drive their respective switch circuits by shifting a relatively low voltage control signal to a relatively high voltage output signal. 
     Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the invention will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the invention. It is manifestly intended that this invention be limited only by the following claims and equivalents thereof.