Abstract:
A semiconductor apparatus may include: a buffer configured to store write request data input in response to a write request from a host; a memory device configured to store data evicted from the buffer; and a controller configured to control the buffer and the memory device to process the write request.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application claims priority of Korean Patent Application No. 10-2015-0062996, filed on May 6, 2015, which is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Field 
         [0003]    Exemplary embodiments of the present invention relate generally to semiconductor technology, and more particularly to a semiconductor apparatus and an operating method thereof to improve performance of a memory device having different set and reset times. 
         [0004]    2. Description of the Related Art 
         [0005]      FIG. 1  is a graph describing a phase change of a memory cell in a Phase Change Random Access Memory (PCRAM). 
         [0006]    The graph illustrates the power required for a set and a reset operation as a function of time for a memory cell of a PCRAM. A set operation changes the memory cell from a reset, high resistance state (reset state) to a set, low resistance state (set state) while a reset operation changes the memory cell from a set state to a reset state. 
         [0007]    As illustrated in  FIG. 1 , a set operation may require about eight times more time than a reset operation. 
         [0008]    Generally, in a memory device, data may be written in units of a predetermined number of memory cells. Hence, during a write operation, a set operation may be performed on some of the memory cells at the same time as a reset operation is performed on other cells. 
         [0009]    Thus, the time required for a write operation of a conventional memory device such as a PCRAM is dictated by the time required for the set operations to the memory cells, which may slow down the operation of a PCRAM. 
         [0010]    The same problem occurs in any other memory device in which the time required for a write operation changes significantly according to the bit value to be written to a memory cell. 
       SUMMARY 
       [0011]    Various embodiments may be directed to a semiconductor apparatus capable of improving an operation performance of a memory device included therein despite of different times between the set and reset operations of the memory device, and an operating method thereof. 
         [0012]    In an embodiment, a semiconductor apparatus may include: a buffer configured to store write request data input in response to a write request from a host; a memory device configured to store data evicted from the buffer; and a controller configured to control the buffer and the memory device to process the write request. 
         [0013]    In an embodiment, an operating method of a semiconductor apparatus including a memory device and first and second buffers may include: storing write request data input in response to a write request in the first buffer; reading from the memory device memory data at write request address input in response to the write request, and storing the memory data at write request address in the second buffer; performing a logic operation on the write request data stored in the first buffer and memory data stored in the second buffer; and updating the memory data at the write request address in the memory device with a result of the logic operation. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]      FIG. 1  is a graph for describing a phase change of a memory cell in a PCRAM. 
           [0015]      FIG. 2  is a block diagram of a semiconductor apparatus, according to an embodiment of the present invention. 
           [0016]      FIG. 3  is a flowchart illustrating an example of a write operation of a semiconductor apparatus, according to an embodiment of the present invention. 
           [0017]      FIG. 4  is a flowchart illustrating another example of a write operation of a semiconductor apparatus according to an embodiment of the present invention. 
           [0018]      FIG. 5  is a flowchart illustrating an example of a read operation of a memory device according to an embodiment of the present invention. 
           [0019]      FIGS. 6 to 8  are diagrams describing an example of a write operation of a semiconductor apparatus shown in  FIG. 3 . 
           [0020]      FIGS. 9 to 11  are diagrams describing another example of a write operation of a semiconductor apparatus shown in  FIG. 3 . 
       
    
    
     DETAILED DESCRIPTION 
       [0021]    Various embodiments will be described below with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention. 
         [0022]    Referring now to  FIG. 2  an example of a semiconductor apparatus  1000  is provided. The semiconductor apparatus  1000  may include a controller  100 , a buffer  200  and a memory device  300 . The controller  100  may control a write request provided from a host  1  to the memory device  300 . The buffer  200  may temporarily store data to be stored in the memory device  300  in response to the write request (hereinafter, also referred to as write request data). 
         [0023]    Although not illustrated, data stored in the buffer  200  and the memory device  300  may be related to each other through an address mapping table, in which buffer addresses of the buffer  200  may be respectively mapped to memory addresses of the memory device  300 . 
         [0024]    The memory device  300  may include an arbitrary memory device having the characteristic that a write operation time changes according to the logic level of the data to be stored in the memory device  300 . The PCRAM is an example of such a memory device. 
         [0025]    The memory device  300  may include a single memory module. The memory device  300  may include a storage device including a plurality of memory modules, such as a Solid State Disk (SSD). 
         [0026]    In an embodiment, the controller  100  the buffer  200 , and the memory device  300  may be included in one package. In another embodiment, the controller  100 , the buffer  200 , and the memory device  300  may be included in different packages. 
         [0027]    Examples of write and read operations performed by the controller  100  will be described below. 
         [0028]    The buffer  200  may include first and second buffers  210  and  220 . The buffer  200  may be implemented with a high-speed memory device such as DRAM or SRAM. However, the invention is not limited in this way and other types of buffer memory devices may be employed. 
         [0029]    The first buffer  210  may perform a similar role to a cache for the memory device  300 . Thus, write request data from the host  1  may be stored in the first buffer  210 , before the write request data may be stored in the memory device  300 . 
         [0030]    The second buffer  220  may serve to temporarily store data. 
         [0031]    In an embodiment, when the write request data may be first written to the first buffer  210  or updated in the first buffer  210  the second buffer  220  may temporarily store data which has been stored at an address may corresponding to the write request data (hereinafter, also referred to as a write request address) in the memory device  300 . 
         [0032]    In another embodiment, the second buffer  220  may temporarily store write request data before the write request data may be stored in the first buffer  210 . 
         [0033]    The storage space of the first buffer  210  may be set to be less than that of the memory device  300 . 
         [0034]    As the operation progresses, the first buffer  210  may run short of storage space. In this case, one or two or more data may be selected from the first buffer  210 , and evicted to the memory device  300 . 
         [0035]    As described above, in response to a write request, the second buffer  220  may temporarily store the current data at the write request address in the memory device  300 . 
         [0036]    In this case, the controller  100  may perform a logic operation to the data temporarily stored in the second buffer  220  and the write request data stored in the first buffer  210 . The data of the write request address of the memory device  300  may be updated with the logic operation result. 
         [0037]    Referring now to  FIG. 3  an example of a write operation of the semiconductor apparatus  1000  will be described. The write operation may be controlled by the controller  100 . Accordingly, when a write request is provided from the host  1 , the controller  100  may determine whether data at the write request address is stored in the first buffer  210  at step S 100 . 
         [0038]    When the data of the write request address is stored in the first buffer  210  (e.g., a buffer hit), the controller  100  may then update the data of the write request address stored in the first buffer  210  with the write request data at step S 110 . 
         [0039]    Then, the controller  100  may temporarily store the data at the write request address of the memory device  300  in the second buffer  220  at step S 120 . 
         [0040]    The controller  100  may then perform a logic operation to the write request data stored in the first buffer  210  and the data of the write request address stored in the second buffer  220  at step  130 . 
         [0041]    The controller  100  may then update the data of the write request address in the memory device  300  with the logic operation result at step S 140 . 
         [0042]    When the data of the write request address is not stored in the first buffer  210  (i.e., the buffer miss) as the determination result of step S 100 , the controller  100  may determine whether the first buffer  210  has an available space for the write request data at step S 210 . 
         [0043]    When the first buffer  210  has an available space for the write request data, the controller  100  may then write the write request data to the available space in the first buffer  210  at step S 110 . Then, the controller  100  may perform steps S 120  to S 140  as described above. 
         [0044]    When the first buffer  210  has no available space for the write request data as the determination result of step S 210 , the controller  100  selects data to be evicted from the first buffer  210  to the memory device  300  at step S 220 . 
         [0045]    The data to be evicted may include one or more data. Criteria for selecting the data to be evicted may be set in various manners. For example, the least recently used data in the first buffer  210  may be selected to be removed. 
         [0046]    At step S 230 , the controller  100  may then update the data in the memory device  300  with the data selected at step  220 . 
         [0047]    Then, the controller  100  may repeat steps S 210  to S 230  until the first buffer  210  has an available space for the write request data. 
         [0048]    In the embodiment of  FIG. 3 , the respective steps of a write operation are described as being performed in a sequential manner. However, it is noted that a part or all of the respective steps, such as for example operations performed by the controller  100  may be performed in parallel, i.e. simultaneously or in an overlapping manner. For example, steps S 110  and S 120  may be performed in parallel at the same time. 
         [0049]      FIG. 4  is a flowchart illustrating another example of a write operation. The write operation shown in  FIG. 4  is the same as the example of the write operation of  FIG. 3  except for the operation when the controller  100  may determine that the first buffer  210  has no available space for the write request data. 
         [0050]    Specifically, in the example of  FIG. 4 , when it is determined that the first buffer  210  has no available space for the write request data as the determination result of step S 210 , the controller  100  may then temporarily store the write request data in the second buffer  220  at step S 200 . 
         [0051]    Then, the controller  100  may perform steps S 220  and S 230  as described above with reference to  FIG. 3 . 
         [0052]    Then, the controller  100  may transfer the write request data stored in the second buffer  220  to the first buffer  240  at step S 240 , and may perform steps S 120  to S 140  as described above with reference to  FIG. 3 . 
         [0053]    In the example of  FIG. 3 , when the first buffer  210  has no available space for the write request data, the write operation is not completed until the first buffer  210  has an available space for the write request data. In the example of  FIG. 4  however, when the first buffer  210  has no available space for the write request data, the write request data may be temporarily stored in the second buffer  220  at step S 200 . At the time of step S 200 , the host  1  may determine that the write operation is completed and thus may perform another operation. Thus, the operation performance of the semiconductor apparatus may be further improved. 
         [0054]      FIG. 5  is a flowchart illustrating an example of a read operation of the memory device  300 . Accordingly, when a read request is provided from the host  1 , the controller  100  may determine whether data of an address may corresponding to the read request (hereinafter, also referred to as a read request address) is stored in the first buffer  210  at step S 300 . 
         [0055]    When the data of the read request address is stored in the first buffer  210  (i.e., a buffer hit), the controller  100  may read the data of the read request address from the first buffer  210  at step S 310 . 
         [0056]    When the data of the read request address is not stored in the first buffer  210  (i.e., the buffer miss) as the determination result of step S 300 , the controller  100  may read the data of the read request address from the memory device  300 , and temporarily store the read data in the second buffer  220  at step S 320 . 
         [0057]    Then, the controller  100  may determine whether the first buffer  210  has an available space for the read data at step S 210 . 
         [0058]    When the first buffer  210  has an available space for the read data, the controller  100  may then store the read data stored in the second buffer  220  into the first buffer  210  at step S 330 . 
         [0059]    When the first buffer  210  has no available space for the read data as the determination result of step S 210 , the controller  100  selects data to be evicted from the first buffer  210  to the memory device  300  at step S 220 , and may then update the data in the memory device  300  with the data selected at step S 230 . 
         [0060]    The controller  100  may then store the read data stored in the second buffer  220  into the first buffer  210  at step S 330 . 
         [0061]    So far, it has been described that steps S 210 , S 220 , and S 230  for securing an available space for the write request data and the read data in the first buffer  210  may be performed during the read and write operation. However, it is noted that these steps may be performed in an idle state where no requests are provided from the host  1 . 
         [0062]      FIGS. 6 to 8  are diagrams describing an example of a write operation of a semiconductor apparatus  1000  shown in  FIG. 3 , wherein the memory device  300  is assumed to be a PCRAM device. 
         [0063]    Furthermore, as an example, the read and write operations of the memory device  300  are shown as being performed by units of 8 bits. It is noted, however, that the invention is not limited in this way. 
         [0064]    In  FIGS. 6 to 11 , a set state of the memory device  300  is represented by a patterned box while a reset state is represented by a non-patterned box. Further, for example, the set state may correspond to a logical value of 1 and the reset state may correspond to a logical value of 0. 
         [0065]      FIG. 6  is a diagram nay corresponding to steps S 110  and S 120  of  FIG. 3 . For example, the controller  100  may update the data of the write request address stored in the first buffer  210  with the write request data “10011111” at step S 110 . 
         [0066]    At this time, suppose that 8 memory cells (i.e., the unit of the write operation the write request address in the memory device  300  have “set”, “set”, “reset”, “set”, “reset”, “reset”, “set”, and “reset” states, respectively, as illustrated in  FIG. 6 . The states may correspond to data “11010010”, and the controller  100  may temporarily store the data “11010010” at the write request address of the memory device  300  in the second buffer  220  at step S 120 . 
         [0067]    According to the prior art, the write request data “10011111” may be directly written to the memory cells having the states corresponding to data “11010010”, the reset operation for one cell and set operations for three cells must be performed as respectively marked as “R” and “S” in  FIG. 6 . Thus, the operation time is dictated by the time required for the set operations. 
         [0068]      FIG. 7  is a diagram corresponding to steps S 130  and S 140  of  FIG. 3 . The controller  110  may perform a bit-wise OR operation on the write request data “10011111” stored in the first buffer  210  and the data “11010010” of the write request address which may be stored in the second buffer  220  at step S 130 . Then, the controller  110  may update the data “11010010” of the write request address of the memory device  300  with the data “11011111” obtained through the bit-wise OR operation at step S 140 . 
         [0069]    As marked as “S” in  FIG. 7 , three set operations may be required to update the data “11010010” of the write request address of the memory device  300  with the data “11011111” at step S 140 , thereby reducing the reset operation when compared to the prior art described with reference to  FIG. 6 . That is, the data of the memory device  300  may be updated through the bit-wise OR operation on the data of the first and second buffers  210  and  220 . Thus only the set operations may be performed at step S 140 . 
         [0070]    Further, since the set operation of step S 140  may be performed after the write request is completed by updating the data of the write request address stored in the first buffer  210  with the write request data at step S 110 , the set operation of step S 140  has no influence on the write performance of the memory device  300  at step S 110 . 
         [0071]    As the result of the set operations of step S 140 , the memory device  300  has the states corresponding to data “11011111”. 
         [0072]      FIG. 8  is a diagram corresponding to step S 230  of  FIG. 3 . In  FIG. 8 , it is assumed that the data “10011111” of the first buffer  210  as exemplified in  FIGS. 6 and 7  may be selected to be evicted to the memory device  300 . 
         [0073]    As illustrated in  FIG. 8 , the controller  110  may evict the selected data “10011111” stored in the first buffer  210  to the memory device  300 , and may then update the data “11011111” of the memory device  300  with the selected data “10011111” at step S 230 . 
         [0074]    As marked as “R” in  FIG. 8 , a single reset operation is required for one cell of the memory device  300 . 
         [0075]    Since the set operations are already performed at step S 140 , there is no need to perform further set operations at step S 230 . 
         [0076]    Since no set operations need to be performed on the memory device  300  in order to secure an available space for the write request data in the first buffer  210  at step S 230 , it is possible to reduce the time required for securing the available space for the write request data at step S 230 . 
         [0077]      FIGS. 9 to 11  are diagrams describing another example of a write operation of a semiconductor apparatus shown in  FIG. 3 . In this example, the set state may correspond to a logical value of 0 and the reset state may correspond to a logical value of 1. 
         [0078]      FIG. 9  is a diagram is corresponding to steps S 110  and S 120  of  FIG. 3 . For example, the controller  100  may update the data of the write request address stored in the first buffer  210  with the write request data “10011111” at step S 110 . 
         [0079]    At this time, 8 memory cells (i.e., the unit of the write operation) of the write request address in the memory device  300  may have “set”, “set”, “reset”, “set”, “reset”, “reset”, “set”, and “reset” states, respectively, as illustrated in  FIG. 9 . The states may correspond to data “00101101”, and the controller  100  may temporarily store the data “11010010” at the write request address of the memory device  300  in the second buffer  220  at step S 120 . 
         [0080]    According to the prior art as described above, the write request data “10011111” may be directly written to the memory cells having the states corresponding to data “11010010”, and thus the reset operation for one cell and set operations for three cells must be performed as respectively marked as “R” and “S” in  FIG. 9 . Thus, the operation time dictated by the time required for the set operations. 
         [0081]      FIG. 10  is a diagram corresponding to steps S 130  and S 140  of  FIG. 3 . The controller  110  may perform a bit-wise AND operation on the write request data “10011111” stored in the first buffer  210  and the data “11010010” of the write request address which may be stored in the second buffer  220  at step S 130 . Then, the controller  110  may update the data “11010010” of the write request address of the memory device  300  with the data “00001001” obtained through the bit-wise AND operation at step S 140 . 
         [0082]    As marked as “S” in  FIG. 10 , two set operations may be required to update the data “11010010” of the write request address of the memory device  300  with the data “00001001” at step S 140 , thereby reducing the reset operation when compared to the prior art described with reference to  FIG. 9 . For example, the data of the memory device  300  may be updated through the bit-wise AND operation on the data of the first and second buffers  210  and  220 , and thus only the set operations may be performed at step S 140 . 
         [0083]    Further, since the set operations of step S 140  may be performed after the write request is completed by updating the data of the write request address stored in the first buffer  210  with the write request data at step S 110 , the set operations of step S 140  have no influence on the write performance of the memory device  300  at step S 110 . 
         [0084]    As the result of set operation of step S 140 , the memory device  300  has the states corresponding to data “00001001”. 
         [0085]      FIG. 11  is a diagram corresponding to step S 230  of  FIG. 3 . 
         [0086]    In  FIG. 11 , the data “10011111” of the first buffer  210  as exemplified in  FIGS. 9 and 10  may be selected to be evicted to the memory device  300 . 
         [0087]    As illustrated in  FIG. 11 , the controller  110  may evict the selected data “10011111” stored in the first buffer  210  to the memory device  300 , and may then update the data “00001001” of the memory device  300  with the selected data “10011111” at step S 230 . 
         [0088]    As marked as “R” in  FIG. 11 , four reset operations may be required for four cells of the memory device  300 . 
         [0089]    Since the set operations may be already performed at step S 140 , there is no need to perform further set operations at step S 230 . 
         [0090]    Since no set operations need to be performed on the memory device  300  in order to secure an available space for the write request data in the first buffer  210  at step S 230 , it is possible to reduce the time required for securing the available space for the write request data at step S 230 . 
         [0091]    The effect disclosed in  FIGS. 8 to 11  may be exhibited in the same manner at step S 230  in examples of  FIGS. 4 and 5 . 
         [0092]    According to the embodiments of the present invention, the semiconductor apparatus can improve the performance of a write operation by preferentially performing the write operation for a buffer. Furthermore, the semiconductor apparatus can improve the performance of the memory device by separating and performing the reset operation and the set operation requiring a relatively large amount of time. 
         [0093]    Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.