Abstract:
In one embodiment the present invention includes a method of fabricating a chip scale package (CSP). The method includes forming conductive bumps on a top side of a semiconductor wafer; mounting the top side of the semiconductor wafer on adhesive tape; sawing the semiconductor wafer a first time such that a wide sawing kerf is obtained; molding the semiconductor wafer with a molding compound; and sawing the semiconductor wafer a second time to obtain the CSPs. Such method has improved efficiency as compared to many existing methods of fabricating CSPs.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    Not applicable. 
       BACKGROUND 
       [0002]    The present invention relates to chip scale package (CSP) fabrication processes, and in particular, to CSP fabrication processes for flip chips. 
         [0003]    In some types of semiconductor chips, the conductive pads of the chip are connected via conductive wire leads to a lead frame, and the lead frame connects the wire leads to the pins on the semiconductor package. In contrast, other types of semiconductor chips are termed flip chips. In a flip chip, conductive balls or bumps are formed on the chip, and the chip is “flipped over” in the package to connect (via a substrate or other structure) to the conductive structures of the pins. Such a flip chip does not require a lead frame or wire leads, and may therefore be made smaller than a package having a lead frame. 
         [0004]    A typical process for fabricating a flip chip is as follows. First, semiconductor fabrication processes form the semiconductor structures on a semiconductor wafer. Second, conductive bumps or balls are formed on the top of the wafer. Third, the wafer is mounted on top of adhesive tape with the bumps on the side of the wafer opposite the tape. Fourth, the wafer is sawed into individual dies. Fifth, each individual die is flipped, mounted onto a substrate, and molded into a semiconductor package. 
         [0005]    A number of problems arise from the above-described typical flip chip fabrication process. One such problem arises during flip chip bonding. During flip chip bonding, it is difficult to inspect the device and it is easy to cause quality issues. In addition, the bonding process is relatively high in both machine usage and raw material usage, so it is desired to develop a more efficient process. 
         [0006]    Thus, there is a need for improved CSP fabrication processes. The present invention solves these and other problems by providing improved processes for flip chip fabrication. 
       SUMMARY 
       [0007]    Embodiments of the present invention improve upon the process of fabricating flip chips. In one embodiment, the present invention includes a method of fabricating a chip scale package (CSP). The method includes mounting the top side of the semiconductor wafer on adhesive tape; sawing the semiconductor wafer a first time such that a wide sawing kerf is obtained; molding the semiconductor wafer with a molding compound; and sawing the semiconductor wafer a second time to obtain the CSPs. 
         [0008]    In another embodiment, the present invention includes a CSP produced by the above method. 
         [0009]    The above method has improved efficiency as compared to many existing methods of fabricating CSPs. 
         [0010]    The following detailed description and accompanying drawings provide a better understanding of the nature and advantages of the present invention. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIGS. 1A ,  1 B and  1 C are perspective views of a chip scale package (CSP) according to an embodiment of the present invention. 
           [0012]      FIG. 1D  is a cross-sectional view of the CSP shown in  FIG. 1A . 
           [0013]      FIG. 2  is a perspective view semiconductor wafer according to an embodiment of the present invention. 
           [0014]      FIG. 3  is a perspective view of the wafer of  FIG. 2  mounted on adhesive tape according to an embodiment of the present invention. 
           [0015]      FIG. 4  is a perspective view of the mounted wafer of  FIG. 3  being sawed according to an embodiment of the present invention. 
           [0016]      FIG. 5  is a perspective view of the sawed, mounted wafer of  FIG. 4  having been covered in molding compound according to an embodiment of the present invention. 
           [0017]      FIG. 6  is a perspective view of the molded wafer of  FIG. 5  being sawed a second time according to an embodiment of the present invention. 
           [0018]      FIG. 7  is a block diagram of a method of fabricating a CSP according to an embodiment of the present invention. 
           [0019]      FIGS. 8A-8F  are cross-sectional views of a semiconductor wafer as resulting from various steps of the method of  FIG. 7  according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0020]    Described herein are techniques for CSP fabrication processes. In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of the present invention. It will be evident, however, to one skilled in the art that the present invention as defined by the claims may include some or all of the features in these examples alone or in combination with other features described below, and may further include obvious modifications and equivalents of the features and concepts described herein. 
         [0021]    The following description uses the terms “bump” and “conductive bump”. These terms are used interchangeably. Equivalent terms include “ball” and “conductive ball”. Such bumps may be formed using solder, gold, or other conductive materials. The term “conductive bump” is used to refer to all these and similar types of structures in flip chips. 
         [0022]    The following description describes various methods and processes. Although the particular method steps are discussed in a particular order, such discussion is mainly for clarity of presentation. It should be recognized that such order may be varied, and some steps may be performed in parallel. One step need only follow another step when the other step must be completed before the one step begins. 
         [0023]    Before giving the details of a method according to an embodiment of the present invention,  FIG. 1A  through  FIG. 6  are briefly discussed to provide visual context for the method. 
         [0024]      FIG. 1A  is a top perspective view of a chip scale package (CSP)  100  according to an embodiment of the present invention. The outer package  102  is molded around the interior structures of the chip (not shown). The interior structures of the chip may be formed according to semiconductor fabrication methods, and may also be referred to collectively as a die. 
         [0025]      FIG. 1B  is a bottom perspective view of the CSP  100  of  FIG. 1A . Conductive bumps  104  protrude outside the outer package  102 . The conductive bumps  104  connect the semiconductor structures of the die to external connections. 
         [0026]      FIG. 1C  is a bottom perspective view of the CSP  100  of  FIG. 1A  without the outer package  102 . The interior structures  106  of the chip may be seen, as well as the conductive bumps  104 . 
         [0027]      FIG. 1D  is a cross-sectional view of the CSP  100  of  FIG. 1A . This figure shows that the outer package  102  is molded around the interior structures  106  of the chip. The conductive bumps  104  protrude outside of the outer package  102 . 
         [0028]      FIG. 2  is a perspective view of a semiconductor wafer  110  according to an embodiment of the present invention. The conductive bumps  104  are formed on the top surface of the wafer  110 . The wafer  110  is fabricated as a collection of dies  106 . The dies  106  are spaced apart by a spacing width on the wafer  110 . Twenty-eight such dies  106  are shown in the wafer  110 . The number of dies  106  in a wafer may vary according to the size of the wafer, the size of the die, and the desired spacing width between dies. 
         [0029]      FIG. 3  is a perspective view of the wafer  110  of  FIG. 2  mounted on adhesive tape  112 . The wafer  110  has been flipped over such that its top surface contacts the adhesive tape  112 . 
         [0030]      FIG. 4  is a perspective view of the mounted wafer of  FIG. 3  being sawed by a blade  120 . The path of the blade  120  follows the spacing width between the dies. The groove cut by the blade  120  is referred to as a kerf. 
         [0031]      FIG. 5  is a perspective view of the sawed, mounted wafer of  FIG. 4  having been covered in molding compound  130 . The molding compound  130  covers the dies (not visible) and fills in the kerfs between the dies. 
         [0032]      FIG. 6  is a perspective view of the molded wafer of  FIG. 5  being sawed a second time by a blade  140 . The path of the blade  140  follows the kerfs between the dies cut by the blade  120  (see  FIG. 4 ) that were filled with molding compound (see  FIG. 5 ). After having been sawed this second time, the individual CSPs  100  result (see  FIGS. 1B and 1D ). 
         [0033]      FIG. 7  is a block diagram of a method  150  according to an embodiment of the present invention. Where appropriate, the method steps refer to the structures illustrated in the previous figures. 
         [0034]    In step  152 , the semiconductor structures on the wafer  110  are fabricated (see  FIG. 2 ). The conductive bumps  104  are also fabricated on the wafer  110 . The pitch of the bumps may be determined by the die pad layout. The pitch of the bumps may also consider the surface mount technology (SMT) capability because the bump pitch determines the package lead pitch as well. The CSP die pad layout may also consider the footprint of the printed circuit board. Accordingly, the conductive bumps may be formed in accordance with a footprint of a printed circuit board. The dies  106  are spaced apart by the spacing width. 
         [0035]    In step  154 , the wafer  110  is mounted on the adhesive tape  112  (see  FIG. 3 ). The wafer  110  is flipped over such that its top surface contacts the adhesive tape  112 . Alternatively, the adhesive tape  112  may be placed on top of the wafer  100 , and the resulting wafer/tape combination itself flipped over. The bumps  104  may contact the adhesive tape  112 , and may be caved in a certain depth to the adhesive tape  112 . Such depth may range between approximately 0.00 mm and 0.05 mm. The adhesive tape  112  may be a thick ultraviolet (UV) tape. 
         [0036]    In step  156 , the wafer  110  is sawed into the individual dies  106  (see  FIG. 4 ). The path sawed by the blade  120  follows the spacing width between the dies  106 . The blade  120  does not cut the adhesive tape  112 . The kerf is a wide sawing kerf, as further detailed below. 
         [0037]    In step  158 , the molding compound  130  is applied to the sawed wafer  110  (see  FIG. 5 ). The molding compound  130  covers the dies and fills in the kerfs between the dies. As the adhesive tape  112  has not been cut, the cut dies  106  are held in place by the adhesive tape  112 . The adhesive tape  112  and the wafer  110  may be placed in the mold chase at the same time. The molding compound  130  fills from the top of the mold chase and fills all the space from the bottom of the dies  106  to the bumps  104 . Because the bumps  104  are caved into the tape a certain depth, the bumps  104  will stand out of the compound between approximately 0.00 mm to 0.05 mm. During this stage, a fine filler size compound may be used. After the molding compound  130  has set sufficiently, the process continues to step  160 . 
         [0038]    In step  160 , the blade  140  saws the molded wafer resulting from step  158  (see  FIG. 6 ). The path of the blade  140  follows the kerfs between the dies that were cut by the blade  120  (see step  156 ) and that were filled with molding compound (see step  158 ). After having been sawed this second time, the individual CSPs  100  result (see  FIGS. 1B and 1D ). At this time, the adhesive tape  112  is cut a sufficient depth to ensure that the compound is fully cut. 
         [0039]    After the CSPs  100  have been sawed, a UV lamp cures the tape. Then the tape may be removed from the CSPs  100 , and the CSPs  100  may be integrated with other components or otherwise packaged to form a discrete chip. 
         [0040]    As mentioned above with regard to step  156 , the kerf is a wide sawing kerf. The kerf is a wide sawing kerf in order to provide a space for molding compound to flow and to allow better cutting quality after molding. One example wide kerf may range between approximately 0.3 mm and 0.5 mm. 
         [0041]    The spacing width of the wafer  110  (discussed above with reference to  FIG. 2 ) is wide enough to accommodate the wide sawing kerf. 
         [0042]      FIGS. 8A-8F  are cross-sectional views of the wafer  110  at various stages of the method  150  according to an embodiment of the present invention.  FIG. 8A  is a cross-sectional view showing a portion of the wafer  110  having been fabricated (see step  152  of  FIG. 7 ). The interior structures  106 , conductive bumps  104 , and the spacing width  170  can be seen. 
         [0043]      FIG. 8B  is a cross-sectional view of the wafer  110  with the adhesive tape  112  having been applied (see step  154  of  FIG. 7 ). 
         [0044]      FIG. 8C  is a cross-sectional view of the wafer  110  having been sawed (see step  156  of  FIG. 7 ). The kerf  172  can be seen. 
         [0045]      FIG. 8D  is a cross-sectional view of the wafer  110  with the molding compound  130  having been applied (see step  158  of  FIG. 7 ). 
         [0046]      FIG. 8E  is a cross-sectional view of the CSPs  100  resulting from the wafer having been sawed the second time (see step  160  of  FIG. 7 ). As shown, because the sawing kerf resulting from the first sawing is wider than a sawing kerf resulting from the second sawing, the individual die may be separated while leaving the molding compound in place to cover the top, bottom, and sidewall surfaces of the die. The adhesive tape  112  has been cut but has not yet been removed from each CSP  100 . 
         [0047]      FIG. 8F  is a cross-sectional view of the CSPs  100  with the adhesive tape having been removed (see step  160  of  FIG. 7 ). 
         [0048]    As can be seen from the above description, embodiments of the present invention improve upon flip chip fabrication processes. A lead frame is unnecessary in embodiments of the present invention. In addition, a flip chip bonder machine is also unnecessary in embodiments of the present invention. With the elimination of these two items, many quality issues that have happened during many existing flip chip bonding processes may be avoided. As a result, the embodiments of the present invention reduce cost, improve reliability, and improve manufacturing yield. 
         [0049]    The above description illustrates various embodiments of the present invention along with examples of how aspects of the present invention may be implemented. The above examples and embodiments should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the present invention as defined by the following claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations and equivalents will be evident to those skilled in the art and may be employed without departing from the spirit and scope of the invention as defined by the claims. The terms and expressions that have been employed here are used to describe the various embodiments and examples. These terms and expressions are not to be construed as excluding equivalents of the features shown and described, or portions thereof, it being recognized that various modifications are possible within the scope of the appended claims.