Abstract:
An integrated circuit includes a memory cell structure including a first cell and a second cell. The first cell includes a first storage structure and a first gate over a substrate. The first gate is over the first storage structure. The second cell includes a second storage structure and a second gate over the substrate. The second gate is over the second storage structure. The first gate is separated from the second gate. A first doped region is adjacent to the first cell and is coupled to a first source. A second doped region is configured within the substrate and adjacent to the second cell. The second doped region is coupled to a second source. At least one third doped region is between the first cell and the second cell, wherein the third doped region is floating.

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
     This application claims benefit of priority to U.S. Provisional Application 60/985,966, filed Nov. 6, 2007, U.S. Provisional Application 60/986,960 filed Nov. 9, 2007, U.S. Provisional Application 60/986,198, filed Nov. 7, 2007, and U.S. Provisional Application 60/986,479, filed Nov. 8, 2007, commonly assigned, which are incorporated in their entirety by reference for all purpose. This application is also related to concurrently filed U.S. patent application Ser. No. 12/264,886, commonly assigned and incorporated by reference herein for all purposes. 
    
    
     BACKGROUND OF THE INVENTION 
     This application relates to semiconductor structures and methods for forming and operating the semiconductor structures and more particularly to Flash cell structures, array structures and methods for operating the Flash array structures. 
     Non-volatile memory (“NVM”) refers to semiconductor memory which is able to continually store information even when the supply of electricity is removed from the device containing the NVM cell. NVM includes Mask Read-Only Memory (Mask ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), and Flash Memory. Non-volatile memory is extensively used in the semiconductor industry and is a class of memory developed to prevent loss of programmed data. Typically, non-volatile memory can be programmed, read and/or erased based on the device&#39;s end-use requirements, and the programmed data can be stored for a long period of time. 
       FIG. 1  is a cross-sectional view of a traditional EEPROM cell structure. In  FIG. 1 , select transistor  110  is adjacent to memory cell  120  to constitute a cell unit. Select transistor  110  has source  101  and common source  103  formed within substrate  100 . Gate oxide layer  111  and select gate  113  are formed over substrate  100 . Memory cell  120  has common source  103  and drain  105 . Tunneling oxide layer  121 , floating gate  122 , oxide layer  123 /nitride layer  124 /oxide layer  125  (ONO), and gate  126  are sequentially formed over substrate  100 . Select transistor  110  is configured to control the operations of memory cell  120 . 
     In a traditional channel hot electron programming method, select transistor  110  is turned on. Source  101  is ground. Drain  105  is coupled to a 4-5V power. 8-10V is applied to gate  126 , such that hot electrons are injected into floating gate  122 . 
     In a traditional source-side FN erasing method, select transistor  110  is turned on. Source  101  is coupled to a 5V power. Drain  105  is floating. −10V is applied to gate  126 , such that electrons are pulled into common source  103  from floating gate  122 . 
     In a traditional channel FN erasing method, source  101  is floating. Substrate  100  is coupled to a 6-8V power. Drain  105  is floating. −8V is applied to gate  126 , such that electrons are pulled into substrate  100  from floating gate  122 . 
     In a traditional read method, select transistor  110  is turned on. Source  101  is ground. Drain  105  is coupled to a 0.6V power. 5V is applied to gate  126  so as to determine the state of memory cell  120 . 
     In a traditional memory cell having a so-called SONOS (silicon-oxide-nitride-oxide-silicon) structure, the nitride layer serves as a charge storage layer (not shown). In a traditional channel hot electron programming method for SONOS cell, a select transistor is turned on. A source is ground. A drain is coupled to a 5V power. 10V is applied to a gate of the SONOS memory cell, such that hot electrons are injected into the charge storage layer. 
     In a traditional band-to-band erase method for SONOS cell, a select transistor is turned off. A source is floating. A substrate is grounded. A drain is coupled to a 5V power. −10V is applied to a gate of the SONOS memory cell, such that hot holes are injected into the charge storage layer and combine with trapped electrons. 
     In a traditional read method for SONOS cell, a select transistor is turned on. A source is grounded. The drain is coupled to a 0.6V power. 5V is applied to a gate of the SONOS memory cell so as to determine the state of the SONOS memory cell. 
     BRIEF SUMMARY OF THE INVENTION 
     According to an exemplary embodiment of the present invention, an integrated circuit includes a memory cell structure. The memory cell structure includes a first cell and a second cell. The first cell includes a first storage structure and a first gate over a substrate, the first gate being over the first storage structure. The second cell includes a second storage structure and a second gate over the substrate, the second gate being over the second storage structure, the first gate being separated from the second gate. A first doped region is adjacent to the first cell and is coupled to a first source. A second doped region is configured within the substrate and adjacent to the second cell. The second doped region is coupled to a second source. At least one third doped region is between the first cell and the second cell. The third doped region is floating. 
     According to another exemplary embodiment of the present invention, an integrated circuit includes a memory array. The memory array includes a plurality of series of cells. Each of the plurality of series of cells is disposed between a first isolation region and a second isolation region. Each of the plurality of series of cells includes a plurality of cell pairs. Each of the cell pairs includes a first cell including a first storage structure and a first gate over a substrate. The first gate is over the first storage structure. A second cell includes a second storage structure and a second gate over the substrate. The second gate is over the second storage structure. The first gate is separated from the second gate. A first doped region is adjacent to the first cell. A second doped region is adjacent to the second cell. At least one third doped region is between the first cell and the second cell and the third doped region is floating. A first bit line is coupled with the first doped region. The first bit line is shared with another series of cells next to one of the first and the second isolation regions. A second bit line is coupled with the second doped region. The second bit line is shared with another series of cells next to the other one of the first and the second isolation regions. 
     According to an exemplary embodiment of the present invention, an integrated circuit includes a memory array. The memory array includes a plurality of series of cells. Each of the plurality of series of cells is disposed between a first isolation region and a second isolation region. Each of the plurality of series of cells includes a plurality of cell pairs. Each of the cell pairs includes a first cell including a first storage structure and a first gate over a substrate. The first gate is over the first storage structure. A second cell includes a second storage structure and a second gate over the substrate. The second gate is over the second storage structure. The first gate is separated from the second gate. A first doped region is adjacent to the first cell, a second doped region is adjacent to the second cell; and at least one third doped region is between the first cell and the second cell. The third doped region is floating. A first bit line is coupled with the first doped region. A second bit line is coupled with the second doped region, wherein the first and second bit lines are not shared with other series of cells. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The foregoing summary, as well as the following detailed description of the invention, will be better understood when read in conjunction with the appended drawings. For the purpose of illustrating the invention, there are shown in the drawings embodiments which are presently preferred. It should be understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown. 
       In the drawings: 
         FIG. 1  is a cross-sectional view of a traditional EEPROM cell structure; 
         FIG. 2A  is a schematic cross-sectional view of two exemplary Flash memory cells; 
         FIG. 2B  is a schematic cross-sectional view of two exemplary Flash memory cells; 
         FIG. 2C  is a schematic drawing showing an exemplary method for programming one of the two exemplary memory cells; 
         FIG. 2D  is a schematic drawing showing an exemplary method for programming one of the two exemplary memory cells; 
         FIG. 2E  is a schematic drawing showing an exemplary biasing of two unselected exemplary memory cells; 
         FIG. 2F  is a schematic drawing showing an exemplary method for erasing at least one of two exemplary memory cells; 
         FIG. 2G  is a schematic drawing showing an exemplary method for erasing at least one of two exemplary memory cells; 
         FIG. 2H  is a schematic drawing showing an exemplary method for reading one of two exemplary memory cells; 
         FIG. 2I  is a schematic drawing showing an exemplary method for reading one of two exemplary memory cells; 
         FIG. 3A  is a schematic drawing showing a portion of an exemplary array structure; 
         FIG. 3B  is a schematic drawing showing an exemplary process for programming a cell of area  350  shown in  FIG. 3A ; 
         FIG. 3C  is a schematic drawing showing an exemplary process for erasing at least one cell of area  350  shown in  FIG. 3A ; 
         FIG. 3D  is a schematic drawing showing an exemplary method for erasing at least one cell of area  350  shown in  FIG. 3A ; 
         FIG. 4A  is a schematic drawing showing a portion of an exemplary array structure; 
         FIG. 4B  is a schematic drawing showing an exemplary process for programming a cell of area  450  shown in  FIG. 4A ; 
         FIG. 4C  is a schematic drawing showing an exemplary process for erasing at least one cell of area  450  shown in  FIG. 4A ; 
         FIG. 4D  is a schematic drawing showing an exemplary method for erasing at least one cell of area  450  shown in  FIG. 4A ; 
         FIG. 5A  is a schematic cross-sectional view of two exemplary Flash memory cells; 
         FIG. 5B  is a schematic cross-sectional view of two exemplary Flash memory cells; 
         FIG. 5C  is a schematic drawing showing an exemplary method for erasing at least one of the two exemplary memory cells; 
         FIG. 5D  is a schematic drawing showing an exemplary method for programming one of two exemplary memory cells; 
         FIG. 5E  is a schematic drawing showing an exemplary method for inhibiting programming disturbance of one of two exemplary memory cells; 
         FIG. 5F  is a schematic drawing showing an exemplary biasing of two unselected exemplary memory cells; 
         FIG. 5G  is a schematic drawing showing an exemplary method for reading one of two exemplary memory cells; 
         FIG. 5H  is a schematic drawing showing an exemplary method for erasing at least one of the two exemplary memory cells; 
         FIG. 5I  is a schematic drawing showing an exemplary method for programming one of two exemplary memory cells; 
         FIG. 5J  is a schematic drawing showing an exemplary method for inhibiting programming disturbance of one of two exemplary memory cells; 
         FIG. 5K  is a schematic drawing showing an exemplary method for reading one of two exemplary memory cells; 
         FIG. 6A  is a schematic drawing showing a portion of an exemplary array structure; 
         FIG. 6B  is a schematic drawing showing an exemplary method for erasing at least one cell of area  350   a  shown in  FIG. 6A ; 
         FIG. 6C  is a schematic drawing showing an exemplary method for erasing at least one cell of area  350   a  shown in  FIG. 6A ; 
         FIG. 6D  is a schematic drawing showing an exemplary process for programming a cell of area  350   a  shown in  FIG. 6A ; 
         FIG. 7A  is a schematic drawing showing a portion of an exemplary array structure; 
         FIG. 7B  is a schematic drawing showing an exemplary method for erasing at least one cell of area  450   a  shown in  FIG. 7A ; 
         FIG. 7C  is a schematic drawing showing an exemplary method for erasing at least one cell of area  450   a  shown in  FIG. 7A ; and 
         FIG. 7D  is a schematic drawing showing an exemplary process for programming a cell of area  450   a  shown in  FIG. 7A . 
     
    
    
     It is to be noted that the appended drawings illustrate merely some exemplary embodiments and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments. 
     DETAILED DESCRIPTION OF THE INVENTION 
     Reference will now be made in detail to the presently exemplary embodiments which are illustrated in the accompanying drawings. The same or similar reference numbers are used in the drawings and the description to refer to the same or like parts. It should be noted that the non-graph drawings are in greatly simplified form and are not to precise scale. In reference to the disclosure herein, for purposes of convenience and clarity only, directional terms, such as top, bottom, left, right, up, down, above, below, beneath, rear, and front, are used with respect to the accompanying drawings. Such directional terms used in conjunction with the following description of the drawings should not be construed to limit the scope of the invention in any manner not explicitly set forth in the appended claims. Although the disclosure herein refers to certain illustrated embodiments, it is to be understood that these embodiments are presented by way of example and not by way of limitation. 
     Memory cells and array structures in accordance with the present invention can overcome some operational issues. The cell and array structures include two neighboring cells. While operating one the cells, the other one is configured to serve as a select transistor. The two cells are coupled to a common floating doped region. With the common floating doped region, the length between the drain side of the one of the two cells to the source side of the other one of the two cells is increased. With the enhanced channel length, punchthrough occurred by operations such as programming and reading one of the cells can be desirably avoided. 
       FIG. 2A  is a schematic cross-sectional view of two exemplary Flash memory cells. According to  FIG. 2A , doped regions  201 ,  203 , and  205  are within a substrate  200 . Substrate  200  can be a silicon substrate, a III-V compound substrate, a silicon/germanium (SiGe) substrate, an epi-substrate, a silicon-on-insulator (SOI) substrate, a display substrate such as a liquid crystal display (LCD), a plasma display, an electro luminescence (EL) lamp display, or a light emitting diode (LED) substrate, for example. Doped regions  201 ,  203 , and  205  can be n-type or p-type doped regions. For n-type doped regions, doped regions  201 ,  203 , and  205  may include dopants such as arsenic, phosphorus and/or other group V element. For p-type doped regions, doped regions  201 ,  203 , and  205  may include dopants such as boron and/or other group III element. In some embodiments, doped regions  201 ,  203 , and  205  can be formed by, for example, an implantation process. 
     Referring again to  FIG. 2A , memory cells  210 , and  220  are over substrate  200 . Memory cell  210  can include tunneling barrier  211 , charge storage layer  213 , dielectric layer  215 , and conductive layer  217 . Memory cell  220  can include tunneling barrier  221 , charge storage layer  223 , dielectric layer  225 , and conductive layer  227 . Tunneling barriers  211  and  221 , charge storage layers  213  and  223 , dielectric layers  215  and  225 , and conductive layers  217  and  227  are over substrate  200 . In some embodiments, tunneling barriers  211  and  221  can be oxide barriers and/or formed by the same process. Charge storage layers  213  and  223  can be nitride layers and/or formed by the same process. Charge storage layers  213  and  223  can be configured to store charges such as electrons and/or holes. Dielectric layers  215  and  225  can be oxide layers and/or formed by the same process. Conductive layers  217  and  227  can be, for example, polysilicon layers, amorphous silicon layers, metal-containing layers, tungsten silicide layers, copper layers, aluminum layers or other conductive material layers. In some embodiments, conductive layers  217  and  227  can be formed by the same process. In some embodiments, tunneling barriers  211  and  221 , charge storage layers  213  and  223 , dielectric layers  215  and  225 , and conductive layers  217  and  227  can be formed by chemical vapor deposition (CVD) processes, ultra high vacuum chemical vapor deposition (UHVCVD) processes, atomic layer chemical vapor deposition (ALCVD) processes, metal organic chemical vapor deposition (MOCVD) processes or other CVD processes. 
       FIG. 2B  is a schematic cross-sectional view of two exemplary Flash memory cells. Memory cells  240  and  250  are over substrate  230 . Memory cell  240  can include barrier layer  244 , floating gate  242 , dielectric layers  241 ,  243 , and  245 , and conductive layer  247 . Memory cell  250  can include barrier layer  254 , floating gate  252 , dielectric layers  251 ,  253 , and  255 , and conductive layer  257 . In  FIG. 2B , substrate  230  is similar to substrate  200  described above in conjunction with  FIG. 2A . Doped regions  231 ,  233 , and  235  are similar to doped regions  201 ,  203 , and  205  respectively, described above in conjunction with  FIG. 2A . Dielectric layers  241 ,  243 ,  245 ,  251 ,  253 , and  255  are dielectric layers. In some embodiments, dielectric layers  241 ,  243 , and  245  are oxide/nitride/oxide (ONO). In some embodiments, dielectric layers  251 ,  253 , and  255  are oxide/nitride/oxide (ONO). In some embodiments, conductive layers  247  and  257  can be similar to the conductive layers  217  and  227 . Tunneling layers  244  and  254  are over substrate  230 . In some embodiments, tunneling layers  244  and  254  can be oxide layers. Floating gates  242  and  252  can be, for example, silicon layers such as polysilicon layers. Floating gates  242  and  252  are configured to store charges such as electrons and/or holes. In some embodiments, tunneling layers  244  and  254 , floating gates  242  and  252 , dielectric layers  241 ,  243 ,  245 ,  251 ,  253 , and  255  and conductive layers  247  and  257  can be formed by chemical vapor deposition (CVD) processes, ultra high vacuum chemical vapor deposition (UHVCVD) processes, atomic layer chemical vapor deposition (ALCVD) processes, metal organic chemical vapor deposition (MOCVD) processes or other CVD processes. 
       FIG. 2C  is a schematic drawing showing an exemplary method for programming one of the two exemplary memory cells. Referring to  FIG. 2C , voltage V 1  can be applied to doped region  201 , voltage V 2  can be applied to gate  217  of cell  210 , doped region  203  can be floating, voltage V 4  can be applied to gate  227  of cell  220 , and voltage V 5  can be applied to doped region  205 . In some embodiments, substrate  200  can be grounded. In some embodiments programming cell  220 , voltage V 5  can be higher than voltage V 1 . Voltage V 2  can be higher than a predetermined threshold voltage of cell  210 , such that voltage V 2  can turn on cell  210 . Voltage V 4  can be a programming voltage. In this configuration, voltage V 2  can turn on cell  210 . Charges such as electrons can flow from doped region  201  to doped region  205  through floating doped region  203 . Due to the applying of voltage V 4  at cell  220 , charges will be injected and trapped at right side region  223   a  of charge storage layer  223 . In some embodiments, the predetermined threshold voltage of cell  210  can be a voltage representing a “0” state of cell  210 . In some embodiments, the predetermined threshold voltage of cell  210  can be a voltage for turning on programmed cell  210 . For example, voltage V 1  can be substantially grounded, voltage V 2  can be about 12V, doped region  203  can be floating, voltage V 4  can be about 10 V, and voltage V 5  can be about 5V. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to achieve a desired programming process for either cell  210  or cell  220 . 
     In some embodiments, the programming process described above in conjunction with  FIG. 2C  can be repeated one or more times so as to form a multi-state to cells  210  and/or  220 . In other embodiments, cell  220  can be programmed once with some voltages higher than voltages V 4  and/or V 5 , such that the threshold voltage of the programmed cell  220  meets one level of several target voltages. Accordingly, cells  210  and/or  220  can be used for multi-level cells. 
       FIG. 2D  is a schematic drawing showing an exemplary method for programming one of the two exemplary memory cells. Referring to  FIG. 2D , voltage V 6  can be applied to doped region  231 , voltage V 7  can be applied to gate  247  of cell  240 , doped region  233  can be floating, voltage V 9  can be applied to gate  257  of cell  250 , and voltage V 10  can be applied to doped region  235 . In some embodiments, substrate  230  can be grounded. In some embodiments programming cell  250 , voltage V 10  can be higher than voltage V 6 . Voltage V 7  can be higher than a predetermined threshold voltage of cell  240 , such that voltage V 7  can turn on cell  240 . Voltage V 9  can be a programming voltage. In this configuration, voltage V 7  can turn on cell  240 . Charges such as electrons can flow from doped region  231  to doped region  235  through floating doped region  233 . Due to the applying of voltage V 9  at cell  250 , charges will be injected and trapped at floating gate  252 . In some embodiments, the predetermined threshold voltage of cell  240  can be a voltage representing a “0” state of cell  240 . In some embodiments, the predetermined threshold voltage of cell  240  can be a voltage for turning on programmed cell  240 . For example, voltage V 6  can be substantially grounded, voltage V 7  can be about 12V, doped region  233  can be floating, voltage V 9  can be about 10 V, and voltage V 10  can be about 5V. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to achieve a desired programming process for either cell  240  or cell  250 . 
     In some embodiments, the programming process described above in conjunction with  FIG. 2D  can be repeated one or more times so as to form a multi-state to cells  240  and/or  250 . In other embodiments, cell  250  can be programmed once with some voltages higher than voltages V 9  and/or V 10 , such that the threshold voltage of the programmed cell  250  meets one level of several target voltages. Accordingly, cells  240  and/or  250  can be used for multi-level cells. 
       FIG. 2E  is a schematic drawing showing an exemplary method for biasing two unselected exemplary memory cells. In some embodiments, cells  210 , and  220  can be unselected cells. To prevent undesirably programming disturbances and further suppress the punchthrough current between doped region  201  and doped region  205 , voltages V 2  and V 4  can be substantially grounded and/or a negative bias. In some embodiments, the negative bias applied to voltages V 2  and/or V 4  may desirably prevent programming disturb and punchthrough current. In some embodiments, voltage V 1  may be substantially grounded, doped region  203  may be floating, and/or voltage V 5  may be about 5V. With floating doped region  203 , the length between doped regions  201  and  205  is longer than the length between doped regions  203 , and  205 . The punch through effect between doped regions  201  and  205  can be desirably reduced. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably prevent programming disturb to cells  210  and/or cell  220 . 
       FIG. 2F  is a schematic drawing showing an exemplary method for erasing at least one of two exemplary memory cells. In some embodiments, cells  210  and/or  220  can be programmed and have charges, e.g., electrons, trapped in charge storage layers  213 , and  223 , respectively. In some embodiments erasing the stored charges in programmed cells  210  and/or  220 , substrate  200  may be substantially grounded, voltage V 1  can be about 5V, voltage V 2  can be −10V, doped region  203  can be floating, voltage V 4  can be −10V, and voltage V 5  can be 5V. Due to the voltage drop between voltages V 1  and V 2 , hot holes can be injected into charge storage layer  213  to combine with trapped electrons, such that cell  210  can be erased. Due to the voltage drop between voltages V 4  and V 5 , hot holes can be injected into charge storage layer  223  to combine with trapped electrons, such that cell  220  can be erased. The threshold voltage of cell  210  is, therefore, reduced. In some embodiments, this erasing method can be referred to as a band-to-band tunneling induced hot hole erasing method. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably erase cells  210  and/or  220 . 
       FIG. 2G  is a schematic drawing showing an exemplary method for erasing at least one of two exemplary memory cells. In some embodiments, cells  240  and/or  250  can be programmed and have charges, e.g., electrons, trapped in floating gates  242  and  252 , respectively. In some embodiments erasing the stored charges in programmed cells  240  and/or  250 , substrate  230  may be substantially grounded, voltage V 6  can be floating, voltage V 7  can be −20V, doped region  233  can be floating, voltage V 9  can be −20V, and voltage V 10  can be floating. Due to the voltage drop between voltages V 7 , V 9  and voltage of substrate  230 , electrons can be ejected from floating gates  242  and  252 , such that cells  240  and/or  250  can be erased. The threshold voltages of cells  240  and/or  250  are, therefore, reduced. In some embodiments, this erasing method can be referred to as a negative gate Fowler-Nordheim (−FN) erasing method. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably erase cells  240  and/or  250 . 
       FIG. 2H  is a schematic drawing showing an exemplary method for reading one of two exemplary memory cells. In some embodiments reading cell  220 , substrate  200  can be substantially grounded, voltage V 1  can be higher than voltage V 5 , voltage V 2  can be applied a voltage higher than a predetermined threshold voltage of cell  210 , such that voltage V 2  can turn on cell  210 . Voltage V 4  can be a sense voltage. In some embodiments, the sense voltage can be between a “0” state voltage and a “1” state voltage of cell  220 . In some embodiments having cell  220  being “1” state, voltage V 4  can turn on cell  220 . Electrons can flow from doped region  205  to doped region  201  through floating doped region  203 . In some embodiments having cell  220  being “0” state, voltage V 4  can not turn on cell  220 . Electrons thus may not substantially flow from doped region  205  to doped region  201 . In some embodiments reading cell  220 , voltage V 1  can be about 1.6V, voltage V 2  can be about 10V, doped region  203  can be floating, voltage V 4  can be between a “0” state voltage and a “1” state voltage of cell  220 , and voltage V 5  can be substantially grounded. 
     In some embodiments reading cell  210 , substrate  200  can be substantially grounded, voltage V 5  can be higher than voltage V 1 , voltage V 4  can be applied a voltage higher than a predetermined threshold voltage of cell  220 , such that voltage V 4  can turn on cell  220 . Voltage V 2  can be a sense voltage. In some embodiments, the sense voltage can be between a “0” state voltage and a “1” state voltage of cell  210 . In some embodiments, this read method can be referred to as a reverse read method. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably read cells  210  or  220 . 
       FIG. 2I  is a schematic drawing showing an exemplary method for reading one of two exemplary memory cells. In some embodiments reading cell  250 , substrate  200  can be substantially grounded, voltage V 10  can be higher than voltage V 6 , voltage V 7  can be applied a voltage higher than a predetermined threshold voltage of cell  240 , such that voltage V 7  can turn on cell  240 . Voltage V 9  can be a sense voltage. In some embodiments, the sense voltage can be between a “0” state voltage and a “1” state voltage of cell  250 . In some embodiments having cell  250  being “1” state, voltage V 9  can turn on cell  250 . Electrons can flow from doped region  231  to doped region  235  through floating doped region  233 . In some embodiments having cell  250  being “0” state, voltage V 9  can not turn on cell  250 . Electrons thus may not substantially flow from doped region  231  to doped region  235 . In some embodiments reading cell  250 , voltage V 6  can be substantially grounded, voltage V 7  can be about 8V, doped region  233  can be floating, voltage V 9  can be between a “0” state voltage and a “1” state voltage of cell  250 , and voltage V 10  can be about 0.6V. 
     In some embodiments reading cell  240 , substrate  200  can be substantially grounded, voltage V 6  can be higher than voltage V 10 , voltage V 9  can be applied a voltage higher than a predetermined threshold voltage of cell  250 , such that voltage V 9  can turn on cell  250 . Voltage V 7  can be a sense voltage. In some embodiments, the sense voltage can be between a “0” state voltage and a “1” state voltage of cell  240 . In some embodiments, this read method can be referred to as a forward read method. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably read cells  240  or  250 . 
       FIG. 3A  is a schematic drawing showing a portion of an exemplary array structure. In some embodiments, a memory array structure comprises a plurality of parallel series of cells and a plurality of bit lines substantially parallel to the plurality of parallel series of cells. In some embodiments, at least one isolation structure  310  is configured between the adjacent parallel series of cells. Each of the plurality of parallel series of cells can be configured between two of the plurality of bit lines. The plurality of parallel series of cells can comprise a 2m th  series of cells being configured between a 2m−1 th  series of cells and a 2 m+1 th  series of cells. The 2m th  series of cells can comprise 4n+1 th  doped regions coupled to 2m th +1 bit line that is also coupled to the 4n+1 th  doped regions of the 2m+1 th  series of cells, respectively. The 2m th  series of cells can comprise 4n+2 th  and 4n+4 th  doped regions which are floating (not coupled to any interconnect). The 2m th  series of cells can comprise 4n+3 th  doped regions coupled to 2m th  bit line that is also coupled to the 4n+3 th  doped regions of the 2m−1 th  series of cells, respectively, wherein m and n are integers. First word lines can be coupled to a plurality of the first cells of the plurality of parallel series of the cells. Second word lines can be coupled to a plurality of the second cells of the plurality of series of the cells, and so on. In some embodiments, the cells of array structure  300  can be cells  210 ,  220 ,  240 , and/or  250  described above in conjunction with  FIGS. 2A and 2B . 
     Referring again to  FIG. 3A , in some embodiments, array structure  300 , for example, can include parallel series of cells  301 - 307  and bit lines BL 1 -BL 8 . Series of cells  301 - 303  can include cells  3011 - 3018 ,  3021 - 3028 , and  3031 - 3038 , respectively. Series of cells  301 - 303  can include doped regions  3111 - 3119 ,  3121 - 3129 , and  3131 - 3139 , respectively. Word lines WL 1 -WL 8  can be configured substantially perpendicular to bit lines BL 1 -BL 8 . Word line WL 1  can be coupled to first cells of the parallel series of cells  301 - 307 . Word line WL 2  can be coupled to second cells of the parallel series of cells  301 - 307 . For series of cells  302 , doped regions  3121 ,  3125 , and  3129  can be coupled to doped regions  3131 ,  3135 , and  3139 , respectively. Doped regions  3123  and  3127  can be coupled to doped regions  3113 , and  3117 , respectively. Doped regions  3122 ,  3124 ,  3126 , and  3128  can be floating. 
     In some embodiments, bit lines BL 1 -BL 8  can be coupled to bit line transistors or switches BLT 1 -BLT 8 , respectively. In some embodiments, bit lines BL 1  and BL 5  can be coupled to a global bit line GBL 1  that is coupled to a voltage sources V 1 . Bit lines BL 2  and BL 6  can be coupled to a global bit line GBL 2  that is coupled to a voltage source V 12 . Bit lines BL 3  and BL 7  can be coupled to a global bit line GBL 3  that is coupled to a voltage source V 13 . Bit lines BL 4  and BL 8  can be coupled to a global bit line GBL 4  that is coupled to a voltage source V 14 . In some embodiments, bit line transistors BLT 1 -BLT 8  can be configured to control the applying of voltages V 11 -V 14  to bit lines BL 1 -BL 8 . 
       FIG. 3B  is a schematic drawing showing an exemplary process for programming a cell of area  350  shown in  FIG. 3A . In some embodiments programming cell  3053 , bit line transistors BLT 5  and BLT 6  (shown in  FIG. 3A ) can be turned on. Voltage V 12  coupled to doped region  3153  can be higher than voltage VII coupled to doped region  3155 . In some embodiments, bit lines BL 4  and/or BL 7  can be floating. A voltage applied to word line WL 4  can be higher than a predetermined threshold voltage of cell  3054 , such that the voltage of word line WL 4  can turn on cell  3054 . A voltage applied to word line WL 3  can be a programming voltage. In this configuration, the voltage of word line WL 4  can turn on cell  3054 . Charges such as electrons can flow from doped region  3155  to doped region  3153  through floating doped region  3154 . Due to the applying of the voltage of word line WL 3  at cell  3053 , charges will be injected and trapped at a charge storage layer or a floating gate of cell  3053 . In some embodiments, the predetermined threshold voltage of cell  3054  can be a voltage representing a “0” state of cell  3054 . In some embodiments, the predetermined threshold voltage of cell  3054  can be a voltage for turning on programmed cell  3054 . For example, bit line BL 5  can be substantially grounded, the voltage of word line WL 3  can be about 10V, doped region  3154  can be floating, the voltage of word line WL 4  can be about 12 V, and bit line BL 6  can be about 5V. In some embodiments, the programming method can be referred to as a channel hot electron programming methods. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to achieve a desired programming process for a cell of array structure  300 . 
     In some embodiments, the programming process described above in conjunction with  FIG. 3B  can be repeated one or more times so as to form a multi-state to a cell of array structure  300 . 
       FIG. 3C  is a schematic drawing showing an exemplary process for erasing at least one cell of area  350  shown in  FIG. 3A . For embodiments having structures of cells  210  and  220  described above in conjunction with  FIG. 2A , cells  3053  and/or  3054  can be programmed and have charges, e.g., electrons, trapped in charge storage layers. In some embodiments erasing the stored charges in programmed cells  3053  and/or  3054 , substrate of array structure  300  may be substantially grounded. Bit line transistors BLT 5  and BLT 6  (shown in  FIG. 3A ) can be turned on. Bit line BL 5  can be about 5V, a voltage of word line WL 3  can be about −10V, doped region  3154  can be floating, a voltage of word line WL 4  can be about −10V, and bit line BL 6  can be 5V. Due to the voltage drop between voltages of bit line BL 6  and word line WL 3 , hot holes can be injected into a charge storage layer of cell  3053  to combine with trapped electrons, such that cell  3053  can be erased. Due to the voltage drop between voltages of bit line BL 5  and word line WL 4 , hot holes can be injected into a charge storage layer of cell  3054  to combine with trapped electrons, such that cell  3054  can be erased. In some embodiments, this erasing method can be referred to as a band-to-band tunneling induced hot hole erasing method. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably erase cells  3053  and/or  3054 . 
     In some embodiments, other bit lines such as bit lines BL 4  and BL 7  can be about 5V, such that cells  3043 ,  3044 ,  3063 , and  3064  can be erased. With this configuration, a regional or block erasing can be desirably achieved. 
       FIG. 3D  is a schematic drawing showing an exemplary method for erasing at least one cell of area  350  shown in  FIG. 3A . For embodiments having structures cells  240  and  250  described above in conjunction with  FIG. 2B , cells  3053  and/or  3054  can be programmed and have charges, e.g., electrons, trapped in floating gates of cells  3053  and/or  3054 . In some embodiments erasing the stored charges in programmed cells  3053  and/or  3054 , the substrate of array structure  300  may be substantially grounded, bit line BL 5  can be floating, a voltage of word line WL 3  can be about −20V, doped region  3154  can be floating, a voltage of word line WL 4  can be about −20V, and bit line BL 6  can be floating. Due to the voltage drop between word lines WL 3 , WL 4  and the voltage of the substrate of array structure  300 , electrons can be ejected from floating gates, such that cells  3053  and/or  3054  can be erased. In some embodiments, this erasing method can be referred to as a negative gate Fowler-Nordheim (−FN) erasing method. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably erase cells  3053  and/or  3054 . 
     In some embodiments, other bit lines such as bit lines BL 4  and BL 7  can be floating, such that cells  3043 ,  3044 ,  3063 , and  3064  can be erased. With this configuration, a regional or block erasing can be desirably achieved. 
     In some embodiments reading cell  3053  having a structure similar to cell  220  described above in conjunction with  FIG. 2A , a voltage of the substrate of array structure  300  can be substantially grounded, a voltage of bit line BL 5  can be higher than a voltage of bit line BL 6 , word line WL 4  can be applied a voltage higher than a predetermined threshold voltage of cell  3054 , such that the voltage of word line WL 4  can turn on cell  3054 . A voltage of word line WL 3  can be a sense voltage. In some embodiments, the sense voltage can be between a “0” state voltage and a “1” state voltage of cell  3053 . In some embodiments having cell  3053  being “1” state, the voltage of word line WL 3  can turn on cell  3053 . Electrons can flow from doped region  3153  to doped region  3155  through floating doped region  3154 . In some embodiments having cell  3053  being “0” state, the voltage of word line WL 3  can not turn on cell  3053 . Electrons thus may not substantially flow from doped region  3153  to doped region  3155 . In some embodiments reading cell  3053 , the voltage of bit line BL 5  can be about 1.6V, the voltage of word line WL 4  can be about 10V, doped region  3154  can be floating, a voltage of word line WL 3  can be between a “0” state voltage and a “1” state voltage of cell  3053 , and a voltage of bit line BL 6  can be substantially grounded. 
     In some embodiments reading cell  3054 , the substrate of array structure  300  can be substantially grounded, a voltage of bit line BL 6  can be higher than a voltage of bit line BL 5 , a voltage of word line WL 3  can be applied a voltage higher than a predetermined threshold voltage of cell  3053 , such that the voltage of word line WL 3  can turn on cell  3053 . A voltage of word line WL 4  can be a sense voltage. In some embodiments, the sense voltage can be between a “0” state voltage and a “1” state voltage of cell  3054 . In some embodiments, this read method can be referred to as a reverse read method. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably read cells  3053  or  3054 . 
     In some embodiments reading cell  3053  having a structure similar to cell  250  described above in conjunction with  FIG. 2B , the substrate of array structure  300  can be substantially grounded, a voltage of bit line BL 6  can be higher than a voltage of bit line BL 5 , word line WL 4  can be applied a voltage higher than a predetermined threshold voltage of cell  3054 , such that the voltage of word line WL 4  can turn on cell  3054 . A voltage of word line WL 3  can be a sense voltage. In some embodiments, the sense voltage can be between a “0” state voltage and a “1” state voltage of cell  3053 . In some embodiments having cell  3053  being “1” state, the voltage of word line WL 3  can turn on cell  3053 . Electrons can flow from doped region  3155  to doped region  3153  through floating doped region  3154 . In some embodiments having cell  3053  being “0” state, the voltage of word line WL 3  can not turn on cell  3053 . Electrons thus may not substantially flow from doped region  3155  to doped region  3153 . In some embodiments reading cell  3053 , bit line BL 5  can be substantially grounded, the voltage of word line WL 4  can be about 8V, doped region  3154  can be floating, the voltage of word line WL 3  can be between a “0” state voltage and a “1” state voltage of cell  3053 , and bit line BL 6  can be about 0.6V. 
     In some embodiments reading cell  3054 , the substrate of array structure  300  can be substantially grounded, the voltage of bit line BL 5  can be higher than the voltage of bit line BL 6 , the voltage of word line WL 3  can be higher than a predetermined threshold voltage of cell  3053 , such that the voltage of word line WL 3  can turn on cell  3053 . The voltage of word line WL 4  can be a sense voltage. In some embodiments, the sense voltage can be between a “0” state voltage and a “1” state voltage of cell  3054 . In some embodiments, this read method can be referred to as a forward read method. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably read cells  3053  or  3054 . 
     Table I shows exemplary methods for operating cells  3053  and/or  3054  array structure  300  described above in conjunction with  FIG. 3A . 
     
       
         
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                   
                 TABLE I 
               
               
                   
                   
               
               
                   
                   
                   
                   
                   
                   
                   
                   
                   
                 Other 
               
               
                   
                 Cell 
                 WL3 
                 WL4 
                 BL4 
                 BL5 
                 BL6 
                 BL7 
                 Substrate 
                 (Unselected) WL 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                 Program (CHE) 
                 3053 
                 10 
                 V 
                 12 
                 V 
                 Floating 
                 0 
                 V 
                 5 
                 V 
                 Floating 
                 0 V 
                 0 V or −Vg 
               
               
                   
                 3054 
                 12 
                 V 
                 10 
                 V 
                 Floating 
                 5 
                 V 
                 0 
                 V 
                 Floating 
                 0 V 
                 0 V or −Vg 
               
               
                 Read (Reverse) 
                 3053 
                 5 
                 V 
                 10 
                 V 
                 Floating 
                 1.6 
                 V 
                 0 
                 V 
                 Floating 
                 0 V 
                 0 V or −Vg 
               
               
                   
                 3054 
                 10 
                 V 
                 5 
                 V 
                 Floating 
                 0 
                 V 
                 1.6 
                 V 
                 Floating 
                 0 V 
                 0 V or −Vg 
               
               
                 Read (Forward) 
                 3053 
                 5 
                 V 
                 8 
                 V 
                 Floating 
                 0 
                 V 
                 0.6 
                 V 
                 Floating 
                 0 V 
                 0 V or −Vg 
               
               
                   
                 3054 
                 8 
                 V 
                 5 
                 V 
                 Floating 
                 0.6 
                 V 
                 0 
                 V 
                 Floating 
                 0 V 
                 0 V or −Vg 
               
             
          
           
               
                 Erase (−FN) 
                 All 
                 −20 
                 V 
                 −20 
                 V 
                 Floating 
                 Floating 
                 Floating 
                 Floating 
                 0 V 
                 −20 V 
               
             
          
           
               
                 Erase (BTB) 
                 All 
                 −10 
                 V 
                 −10 
                 V 
                 5 V 
                 5 
                 V 
                 5 
                 V 
                 5 V 
                 0 V 
                 −10 V 
               
               
                   
               
             
          
         
       
     
     It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably operate cells  3053  or  3054 . 
       FIG. 4A  is a schematic drawing showing a portion of an exemplary array structure. In some embodiments, a memory array structure comprises a plurality of parallel series of cells and a plurality of bit lines substantially parallel to the plurality of series of cells. Each of the plurality of series of cells can be configured between two bit lines. Each of the plurality of parallel series of cells can include 4n+1 th , 4n+2 th , 4n+3 th  and 4n+4 th  doped regions. The 4n+1 th  doped regions can be coupled to first one of the two bit lines, the 4n+2 th  and 4n+4 th  doped region can be floating (e.g., not coupled to any interconnect), and the 4n+3 th  doped regions can be coupled to second one of the two bit lines, wherein n is an integer. In some embodiments, the series of cells can be configured between two isolation structures  410 . First word lines can be coupled to the first cells of the plurality of parallel series of the cells. Second word lines can be coupled to the second cells of the plurality of series of the cells, and so on. In some embodiments, the cells of array structure  400  can be cells  210 ,  220 ,  240 , and/or  250  described above in conjunction with  FIGS. 2A and 2B . 
     Referring again to  FIG. 4A , in some embodiments, array structure  400 , for example, can include parallel series of cells  401 - 404  and bit lines BL 1 -BL 8 . Series of cells  401  and  402  can include cells  4011 - 4018 , and  4021 - 4028 , respectively. Series of cells  401  and  402  can include doped regions  4111 - 4119 , and  4121 - 4129 , respectively. Word lines WL 1 -WL 8  can be configured substantially perpendicular to bit lines BL 1 -BL 8 . Word line WL 1  can be coupled to first cells of the parallel series of cells  401 - 404 . Word line WL 2  can be coupled to second cells of the parallel series of cells  401 - 404 . For series of cells  402 , doped regions  4121 ,  4125 , and  4129  can be coupled to bit line BL 4 . Doped regions  4123  and  4127  can be coupled to bit line BL 3 . Doped regions  4122 ,  4124 ,  4126 , and  4128  can be floating. 
     In some embodiments, bit lines BL 1 -BL 8  can be coupled to bit line transistor switches BLT 1 -BLT 8 , respectively. In some embodiments, bit lines BL 1  and BL 5  can be coupled to a global bit line GBL 1  that is coupled to a voltage source V 15 . Bit lines BL 2  and BL 6  can be coupled to a global bit line GBL 2  that is coupled to a voltage sources V 16 . Bit lines BL 3  and BL 7  can be coupled to a global bit line GBL 3  that is coupled to a voltage source V 17 . Bit lines BL 4  and BL 8  can be coupled to a global bit line GBL 4  that is coupled to a voltage source V 18 . In some embodiments, bit line transistors BLT 1 -BLT 8  can be configured to control the applying of voltages V 15 -V 18  to respective bit lines BL 1 -BL 8 . 
       FIG. 4B  is a schematic drawing showing an exemplary process for programming a cell of area  450  shown in  FIG. 4A . In some embodiments programming cell  4043 , bit line transistors BLT 7  and BLT 8  (shown in  FIG. 4A ) can be turned on. Voltage V 17  coupled to doped region  4143  can be higher than voltage V 18  coupled to doped region  4145 . In some embodiments, bit lines BL 5  and/or BL 6  can be floating. A voltage applied to word line WL 4  can be higher than a predetermined threshold voltage of cell  4044 , such that the voltage of word line WL 4  can turn on cell  4044 . A voltage applied to word line WL 3  can be a programming voltage. In this configuration, the voltage of word line WL 4  can turn on cell  4044 . Charges such as electrons can flow from doped region  4145  to doped region  4143  through floating doped region  4144 . Due to the applying of the voltage of word line WL 3  at cell  4043 , charges will be injected and trapped at a charge storage layer or a floating gate of cell  4043 . In some embodiments, the predetermined threshold voltage of cell  4044  can be a voltage representing a “0” state of cell  4044 . In some embodiments, the predetermined threshold voltage of cell  4044  can be a voltage for turning on programmed cell  4044 . For example, bit line BL 8  can be substantially grounded, the voltage of word line WL 3  can be about 10V, doped region  4144  can be floating, the voltage of word line WL 4  can be about 12V, and bit line BL 7  can be about 5V. In some embodiments, the programming method can be referred to as a channel hot electron programming methods. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to achieve a desired programming process for a cell of array structure  400 . 
     In some embodiments, the programming process described above in conjunction with  FIG. 4B  can be repeated one or more times so as to form a multi-state to a cell of array structure  400 . 
       FIG. 4C  is a schematic drawing showing an exemplary process for erasing at least one cell of area  450  shown in  FIG. 4A . For embodiments having structures of cells  210  and  220  described above in conjunction with  FIG. 2A , cells  4043  and/or  4044  can be programmed and have charges, e.g., electrons, trapped in charge storage layers. In some embodiments erasing the stored charges in programmed cells  4043  and/or  4044 , substrate of array structure  400  may be substantially grounded. Bit line transistors BLT 7  and BLT 8  (shown in  FIG. 4A ) can be turned on. Bit line BL 7  can be about 5V, a voltage of word line WL 3  can be about −10V, doped region  4144  can be floating, a voltage of word line WL 4  can be about −10V, and bit line BL 8  can be 5V. Due to the voltage drop between voltages of bit line BL 7  and word line WL 3 , hot holes can be injected into a charge storage layer of cell  4043  to combine with trapped electrons, such that cell  4043  can be erased. Due to the voltage drop between voltages of bit line BL 8  and word line WL 4 , hot holes can be injected into a charge storage layer of cell  4044  to combine with trapped electrons, such that cell  4044  can be erased. In some embodiments, this erasing method can be referred to as a band-to-band tunneling induced hot hole erasing method. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably erase cells  4043  and/or  4044 . 
     In some embodiments, other bit lines such as bit lines BL 5  and BL 6  can be about 5V, such that cells  4033 , and  4034  can be erased. With this configuration, a regional or block erasing can be desirably achieved. 
       FIG. 4D  is a schematic drawing showing an exemplary method for erasing at least one cell of area  450  shown in  FIG. 4A . For embodiments having structures of cells  240  and  250  described above in conjunction with  FIG. 2B , cells  4043  and/or  4044  can be programmed and have charges, e.g., electrons, trapped in floating gates of cells  4043  and/or  4044 . In some embodiments erasing the stored charges in programmed cells  4043  and/or  4044 , the substrate of array structure  400  may be substantially grounded, bit line BL 7  can be floating, a voltage of word line WL 3  can be about −20V, doped region  4144  can be floating, a voltage of word line WL 4  can be about −20V, and bit line BL 8  can be floating. Due to the voltage drop between word lines WL 3 , WL 4  and the voltage of the substrate of array structure  400 , electrons can be ejected from floating gates, such that cells  4043  and/or  4044  can be erased. In some embodiments, this erasing method can be referred to as a negative gate Fowler-Nordheim (−FN) erasing method. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably erase cells  4043  and/or  4044 . 
     In some embodiments, other bit lines such as bit lines BL 5  and BL 6  can be floating, such that cells  4033 , and  4034  can be erased. With this configuration, a regional or block erasing can be desirably achieved. 
     In some embodiments reading cell  4043  having a structure similar to cell  220  described above in conjunction with  FIG. 2A , a voltage of the substrate of array structure  400  can be substantially grounded, a voltage of bit line BL 8  can be higher than a voltage of bit line BL 7 , word line WL 4  can be applied a voltage higher than a predetermined threshold voltage of cell  4044 , such that the voltage of word line WL 4  can turn on cell  4044 . A voltage of word line WL 3  can be a sense voltage. In some embodiments, the sense voltage can be between a “0” state voltage and a “1” state voltage of cell  4043 . In some embodiments having cell  4043  being “1” state, the voltage of word line WL 3  can turn on cell  4043 . Electrons can flow from doped region  4143  to doped region  4145  through floating doped region  4144 . In some embodiments having cell  4043  being “0” state, the voltage of word line WL 3  can not turn on cell  4043 . Electrons thus may not substantially flow from doped region  4143  to doped region  4145 . In some embodiments reading cell  4043 , the voltage of bit line BL 8  can be about 1.6V, the voltage of word line WL 4  can be about 10V, doped region  4144  can be floating, a voltage of word line WL 3  can be between a “0” state voltage and a “1” state voltage of cell  4043 , and a voltage of bit line BL 7  can be substantially grounded. 
     In some embodiments reading cell  4044 , the substrate of array structure  400  can be substantially grounded, a voltage of bit line BL 7  can be higher than a voltage of bit line BL 8 , a voltage of word line WL 3  can be applied a voltage higher than a predetermined threshold voltage of cell  4043 , such that the voltage of word line WL 3  can turn on cell  4043 . A voltage of word line WL 4  can be a sense voltage. In some embodiments, the sense voltage can be between a “0” state voltage and a “1” state voltage of cell  4044 . In some embodiments, this read method can be referred to as a reverse read method. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably read cells  4043  or  4044 . 
     In some embodiments reading cell  4043  having a structure similar to cell  250  described above in conjunction with  FIG. 2B , the substrate of array structure  400  can be substantially grounded, a voltage of bit line BL 7  can be higher than a voltage of bit line BL 8 , word line WL 4  can be applied a voltage higher than a predetermined threshold voltage of cell  4044 , such that the voltage of word line WL 4  can turn on cell  4044 . A voltage of word line WL 3  can be a sense voltage. In some embodiments, the sense voltage can be between a “0” state voltage and a “1” state voltage of cell  4043 . In some embodiments having cell  4043  being “1” state, the voltage of word line WL 3  can turn on cell  4043 . Electrons can flow from doped region  4145  to doped region  4143  through floating doped region  4144 . In some embodiments having cell  4043  being “0” state, the voltage of word line WL 3  can not turn on cell  4043 . Electrons thus may not substantially flow from doped region  4145  to doped region  4143 . In some embodiments reading cell  4043 , bit line BL 8  can be substantially grounded, the voltage of word line WL 4  can be about 8V, doped region  4144  can be floating, the voltage of word line WL 3  can be between a “0” state voltage and a “1” state voltage of cell  4043 , and bit line BL 7  can be about 0.6V. 
     In some embodiments reading cell  4044 , the substrate of array structure  400  can be substantially grounded, the voltage of bit line BL 8  can be higher than the voltage of bit line BL 7 , the voltage of word line WL 3  can be higher than a predetermined threshold voltage of cell  4043 , such that the voltage of word line WL 3  can turn on cell  4043 . The voltage of word line WL 4  can be a sense voltage. In some embodiments, the sense voltage can be between a “0” state voltage and a “1” state voltage of cell  4044 . In some embodiments, this read method can be referred to as a forward read method. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably read cells  4043  or  4044 . 
     Table II shows exemplary methods for operating cells  4043  and/or  4044  array structure  400  described above in conjunction with  FIG. 4A . 
     
       
         
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                   
                 TABLE II 
               
               
                   
                   
               
               
                   
                   
                   
                   
                   
                   
                   
                   
                   
                 Other 
               
               
                   
                 Cell 
                 WL3 
                 WL4 
                 BL5 
                 BL6 
                 BL7 
                 BL8 
                 Substrate 
                 (Unselected) WL 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                 Program (CHE) 
                 4043 
                 10 
                 V 
                 12 
                 V 
                 Floating 
                 Floating 
                 5 
                 V 
                 0 
                 V 
                 0 V 
                 0 V or −Vg 
               
               
                   
                 4044 
                 12 
                 V 
                 10 
                 V 
                 Floating 
                 Floating 
                 0 
                 V 
                 5 
                 V 
                 0 V 
                 0 V or −Vg 
               
               
                 Read (Reverse) 
                 4043 
                 5 
                 V 
                 10 
                 V 
                 Floating 
                 Floating 
                 0 
                 V 
                 1.6 
                 V 
                 0 V 
                 0 V or −Vg 
               
               
                   
                 4044 
                 10 
                 V 
                 5 
                 V 
                 Floating 
                 Floating 
                 1.6 
                 V 
                 0 
                 V 
                 0 V 
                 0 V or −Vg 
               
               
                 Read (Forward) 
                 4043 
                 5 
                 V 
                 8 
                 V 
                 Floating 
                 Floating 
                 0.6 
                 V 
                 0 
                 V 
                 0 V 
                 0 V or −Vg 
               
               
                   
                 4044 
                 8 
                 V 
                 5 
                 V 
                 Floating 
                 Floating 
                 0 
                 V 
                 0.6 
                 V 
                 0 V 
                 0 V or −Vg 
               
             
          
           
               
                 Erase (−FN) 
                 All 
                 −20 
                 V 
                 −20 
                 V 
                 Floating 
                 Floating 
                 Floating 
                 Floating 
                 0 V 
                 −20 V 
               
             
          
           
               
                 Erase (BTB) 
                 All 
                 −10 
                 V 
                 −10 
                 V 
                 5 V 
                 5 V 
                 5 
                 V 
                 5 
                 V 
                 0 V 
                 −10 V 
               
               
                   
               
             
          
         
       
     
     It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably operate cells  4043  or  4044 . 
       FIG. 5A  is a schematic cross-sectional view of two exemplary Flash memory cells. According to  FIG. 5A , doped regions  201   a ,  203   a , and  205   a  are within a substrate  200   a . Substrate  200   a  can be a silicon substrate, a III-V compound substrate, a silicon/germanium (SiGe) substrate, an epi-substrate, a silicon-on-insulator (SOI) substrate, a display substrate such as a liquid crystal display (LCD), a plasma display, an electro luminescence (EL) lamp display, or a light emitting diode (LED) substrate, for example. Doped regions  201   a ,  203   a , and  205   a  can be n-type or p-type doped regions. For n-type doped regions, doped regions  201   a ,  203   a , and  205   a  may include dopants such as arsenic, phosphorus and/or other group V element. For p-type doped regions, doped regions  201   a ,  203   a , and  205   a  may include dopants such as boron and/or other group III element. In some embodiments, doped regions  201   a ,  203   a , and  205   a  can be formed by, for example, an implantation process. 
     Referring again to  FIG. 5A , memory cells  210   a  and  220   a  are over substrate  200   a . Memory cell  210   a  can include tunneling barrier  211   a , charge storage layer  213   a , dielectric layer  215   a , and conductive layer  217   a . Memory cell  220   a  can include tunneling barrier  221   a , charge storage layer  223   a , dielectric layer  225   a , and conductive layer  227   a . Tunneling barriers  211   a  and  221   a , charge storage layers  213   a  and  223   a , dielectric layers  215   a  and  225   a , and conductive layers  217   a  and  227   a  are over substrate  200   a . In some embodiments, tunneling barriers  211   a  and  221   a  can be oxide barriers and/or formed by the same process. Charge storage layers  213   a  and  223   a  can be nitride layers and/or formed by the same process. Charge storage layers  213   a  and  223   a  can be configured to store charges such as electrons and/or holes. Dielectric layers  215   a  and  225   a  can be oxide layers and/or formed by the same process. Conductive layers  217   a  and  227   a  can be, for example, polysilicon layers, amorphous silicon layers, metal-containing layers, tungsten silicide layers, copper layers, aluminum layers or other conductive material layers. In some embodiments, conductive layers  217   a  and  227   a  can be formed by the same process. In some embodiments, tunneling barriers  211   a  and  221   a , charge storage layers  213   a  and  223   a , dielectric layers  215   a  and  225   a , and conductive layers  217   a  and  227   a  can be formed by chemical vapor deposition (CVD) processes, ultra high vacuum chemical vapor deposition (UHVCVD) processes, atomic layer chemical vapor deposition (ALCVD) processes, metal organic chemical vapor deposition (MOCVD) processes or other CVD processes. 
       FIG. 5B  is a schematic cross-sectional view of two exemplary Flash memory cells. Memory cells  240   a  and  250   a  are over substrate  230   a . Memory cell  240   a  can include barrier layer  244   a , floating gate  242   a , dielectric layers  241   a ,  243   a , and  245   a , and conductive layer  247   a . Memory cell  250   a  can include barrier layer  254   a , floating gate  252   a , dielectric layers  251   a ,  253   a , and  255   a , and conductive layer  257   a . In  FIG. 5B , substrate  230   a  is similar to substrate  200   a  described above in conjunction with  FIG. 5A . Doped regions  231   a ,  233   a , and  235   a  are similar to doped regions  201   a ,  203   a , and  205   a , respectively, described above in conjunction with  FIG. 5A . Dielectric layers  241   a ,  243   a ,  245   a ,  251   a ,  253   a , and  255   a  are dielectric layers. In some embodiments, dielectric layers  241   a ,  243   a , and  245   a  are oxide/nitride/oxide (ONO). In some embodiments, dielectric layers  251   a ,  253   a , and  255   a  are oxide/nitride/oxide (ONO). In some embodiments, conductive layers  247   a  and  257   a  can be similar to the conductive layers  217   a  and  227   a , respectively. Tunneling layers  244   a  and  254   a  are over substrate  230   a . In some embodiments, tunneling layers  244   a , and  254   a  can be oxide layers. Floating gates  242   a  and  252   a  can be, for example, silicon layers such as polysilicon layers. Floating gates  242   a  and  252   a  are configured to store charges such as electrons and/or holes. In some embodiments, tunneling layers  244   a  and  254   a , floating gates  242   a  and  252   a , dielectric layers  241   a ,  243   a ,  245   a ,  251   a ,  253   a , and  255   a  and conductive layers  247   a  and  257   a  can be formed by chemical vapor deposition (CVD) processes, ultra high vacuum chemical vapor deposition (UHVCVD) processes, atomic layer chemical vapor deposition (ALCVD) processes, metal organic chemical vapor deposition (MOCVD) processes or other CVD processes. 
       FIG. 5C  is a schematic drawing showing an exemplary method for erasing at least one of the two exemplary memory cells. In some embodiments, cells  210   a  and/or  220   a  can be erased by injecting charges such as electrons from gates  217   a  and  227   a  into charge storage layers  213   a , and  223   a , respectively. In some embodiments erasing cells  210   a  and/or  220   a , substrate  200   a  may be substantially grounded, voltages V 1  and V 5  can be floating. Doped region  203   a  can be floating. A first negative voltage can be applied to gate  217   a . A second negative voltage can be applied to gate  227   a . In some embodiments, the first negative voltage can be substantially equal to the second negative voltage. In some embodiments, substrate  200   a  may be substantially grounded, voltages V 1  and V 5  can be floating, doped region  203   a  can be floating, and voltages V 2  and V 4  can be about −20V. Due to the voltage drop between gates  217   a ,  227   a  and substrate  200   a , electrons can be injected into charge storage layer  213   a ,  223   a , such that cells  210   a  and  220   a  can be erased. In some embodiments, this erasing method can be referred to as a negative gate Fowler-Nordheim (−FN) erasing method. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably erase cells  210   a  and/or  220   a.    
       FIG. 5D  is a schematic drawing showing an exemplary method for programming one of two exemplary memory cells. In some embodiments, cells  210   a  and/or  220   a  can be erased and have charges, e.g., electrons, trapped in charge storage layers  213   a , and  223   a , respectively. In some embodiments programming cell  210   a , substrate  200   a  may be substantially grounded, a positive voltage can be applied to doped region  201   a , a negative voltage can be applied to gate  217   a , doped region  203   a  can be floating, cell  220   a  can be configured to serve as a select transistor and be turned on, and doped region  205   a  can be substantially grounded. In some embodiments, the absolute value of the negative voltage applied to gate  217   a  can be substantially equal to the positive voltage of V 1 . After the programming, the threshold voltage of the programmed cell  210   a  is reduced. In some embodiments, substrate  200   a  can be substantially grounded, voltage V 1  can be about 5V, voltage V 2  can be about −5V, doped region  203   a  is floating, cell  220   a  can be turned on, and voltage V 5  can be substantially grounded. In some embodiments, this programming method can be referred to as a band-to-band tunneling induced hot hole programming method. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably program cells  210   a  and/or  220   a.    
     In some embodiments, the programming process described above in conjunction with  FIG. 5D  can be repeated one or more times so as to form a multi-state to cells  210   a  and/or  220   a . In other embodiments, cell  210   a  can be programmed once with some voltages higher than voltages V 1  and/or V 2 , such that the threshold voltage of the programmed cell  210   a  meets one level of several target voltages. Accordingly, cells  210   a  and/or  220   a  can be used for multi-level cells. 
       FIG. 5E  is a schematic drawing showing an exemplary method for inhibiting programming disturbance of one of two exemplary memory cells. In some embodiments, cells  210   a  and/or  220   a  can be erased and have charges, e.g., electrons, trapped in charge storage layers  213   a , and  223   a , respectively. In some embodiments programming cell (not shown) adjacent to cell  210   a , the programming step may disturb cell  210   a . In some embodiments, substrate  200   a  may be substantially grounded, a positive voltage can be applied to doped region  201   a , a negative voltage can be applied to gate  217   a , doped region  203   a  can be floating, cell  220   a  can be configured to serve as a select transistor and be turned on, and doped region  205   a  can be coupled to a positive voltage. Since cell  220   a  is turned on, the positive voltage of doped region  205   a  can be coupled to doped region  203   a . Due to the coupled voltage of doped region  203   a , hot holes injected from doped region  201   a  into charge storage layer  217   a  can be desirably reduced. In some embodiments, the absolute value of the negative voltage applied to gate  217   a  can be substantially equal to the positive voltage of V 1 . In some embodiments, substrate  200   a  can be substantially grounded, voltage V 1  can be about 5V, voltage V 2  can be about −5V, doped region  203   a  is floating, cell  220   a  can be turned on, and voltage V 5  can be about 3V. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably avoid programming disturbance to cells  210   a  and/or  220   a.    
       FIG. 5F  is a schematic drawing showing an exemplary method for two unselected exemplary memory cells. In some embodiments, cells  210   a  and  220   a  can be unselected cells. To desirably avoid programming disturbances, voltages V 2  and V 4  can be substantially grounded and/or a negative bias. In some embodiments, the negative bias applied to voltages V 2  and/or V 4  may desirably prevent programming disturbance. In some embodiments, voltages V 1  can be about 5V and V 5  may be substantially grounded, and doped region  203   a  may be floating. With floating doped region  203   a , the length between doped regions  201   a  and  205   a  is longer than the length between doped regions  203   a , and  205   a . The punchthrough effect between doped regions  201   a , and  205   a  can be desirably reduced. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably prevent programming disturbance to cells  210   a  and/or cell  220   a.    
       FIG. 5G  is a schematic drawing showing an exemplary method for reading one of two exemplary memory cells. In some embodiments reading cell  210   a , substrate  200   a  can be substantially grounded, voltage V 5  can be higher than voltage V 1 , voltage V 4  can be applied a voltage higher than a predetermined threshold voltage of cell  220   a , such that voltage V 4  can turn on cell  220   a . Voltage V 2  can be a sense voltage. In some embodiments, the sense voltage can be between a “0” state voltage and a “1” state voltage of cell  210   a . In some embodiments having cell  210   a  being “1” state, voltage V 2  can turn on cell  210   a . Electrons can flow from doped region  201   a  to doped region  205   a  through floating doped region  203   a . In some embodiments having cell  210   a  being “0” state, voltage V 2  can not turn on cell  210   a . Electrons thus may not substantially flow from doped region  201   a  to doped region  205   a . In some embodiments reading cell  210   a , voltage V 1  can be substantially grounded, voltage V 2  can be between a “0” state voltage and a “1” state voltage of cell  210   a , doped region  203   a  can be floating, voltage V 4  can turn on cell  220   a , and voltage V 5  can be about 1.6V. 
     In some embodiments reading cell  220   a , substrate  200   a  can be substantially grounded, voltage V 1  can be higher than voltage V 5 , voltage V 2  can be applied a voltage higher than a predetermined threshold voltage of cell  210   a , such that voltage V 2  can turn on cell  210   a . Voltage V 4  can be a sense voltage. In some embodiments, the sense voltage can be between a “0” state voltage and a “1” state voltage of cell  220   a . In some embodiments, this read method can be referred to as a reverse read method. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably read cells  210   a  or  220   a.    
       FIG. 5H  is a schematic drawing showing an exemplary method for erasing at least one of the two exemplary memory cells. In some embodiments, cells  240   a  and/or  250   a  can be erased by injecting charges such as electrons from substrate  230   a  to floating gates  242   a  and  252   a . In some embodiments erasing cells  240   a  and/or  250   a , substrate  230   a  may be substantially grounded, voltages V 6  and V 10  can be substantially grounded. Doped region  233   a  can be floating. A first positive voltage can be applied to gate  247   a . A second positive voltage can be applied to gate  257   a . In some embodiments, the first positive voltage can be substantially equal to the second positive voltage. In some embodiments, substrate  230   a  may be substantially grounded, voltages V 6  and V 10  can be substantially grounded, doped region  203   a  can be floating, and voltages V 7  and V 9  can be about 20V. Due to the voltage drop between gates  247   a ,  257   a  and substrate  230   a , electrons can be injected into floating gates  242   a ,  252   a , such that cells  240   a  and  250   a  can be erased. The threshold voltages of erased cells  240   a  and  250   a  are thus increased. In some embodiments, this erasing method can be referred to as a positive gate Fowler-Nordheim (+FN) erasing method. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably erase cells  240   a  and/or  250   a.    
       FIG. 5I  is a schematic drawing showing an exemplary method for programming one of two exemplary memory cells. In some embodiments, cells  240   a  and/or  250   a  can be erased and have charges, e.g., electrons, trapped in floating gates  242   a , and  252   a , respectively. In some embodiments programming cell  240   a , substrate  230   a  may be substantially grounded, a positive voltage can be applied to doped region  231   a , a negative voltage can be applied to gate  247   a , doped region  233   a  can be floating, cell  250   a  can serve as a select transistor and be turned on, and doped region  235   a  can be substantially grounded. In some embodiments, the absolute value of the negative voltage applied to gate  247   a  can be substantially equal to the positive voltage of V 6 . After the programming step, the threshold voltage of programmed cell  240   a  is reduced. In some embodiments, substrate  230   a  can be substantially grounded, voltage V 6  can be about 5V, voltage V 7  can be about −5V, doped region  203   a  is floating, cell  220   a  can be turned on, and voltage V 10  can be substantially grounded. In some embodiments, this programming method can be referred to as a band-to-band tunneling induced hot hole programming method. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably program cells  240   a  and/or  250   a.    
     In some embodiments, the programming process described above in conjunction with  FIG. 5I  can be repeated one or more times so as to form a multi-state to cells  240   a  and/or  250   a . In other embodiments, cell  240   a  can be programmed once with some voltages higher than voltages V 6  and/or V 7 , such that the threshold voltage of the programmed cell  240   a  meets one level of several target voltages. Accordingly, cells  240   a  and/or  250   a  can be used for multi-level cells. 
       FIG. 5J  is a schematic drawing showing an exemplary method for inhibiting programming disturbance of one of two exemplary memory cells. In some embodiments, cells  240   a  and/or  250   a  can be erased and have charges, e.g., electrons, trapped in floating gates  242   a , and  252   a , respectively. In some embodiments programming cell (not shown) adjacent to cell  240   a , the programming step may disturb cell  240   a . In some embodiments for desirably reducing programming disturbance, substrate  230   a  may be substantially grounded, a positive voltage can be applied to doped region  231   a , a negative voltage can be applied to gate  247   a , doped region  233   a  can be floating, cell  250   a  can be configured to serve as a select transistor and be turned on, and doped region  235   a  can be coupled to a positive voltage. Since cell  250   a  is turned on, the positive voltage of doped region  235   a  can be coupled to doped region  233   a . Due to the coupled voltage of doped region  233   a , hot holes injected from doped region  231   a  into floating gate  242   a  can be desirably reduced. In some embodiments, the absolute value of the negative voltage applied to gate  247   a  can be substantially equal to the positive voltage of V 6 . In some embodiments, substrate  230   a  can be substantially grounded, voltage V 6  can be about 5V, voltage V 7  can be about −5V, doped region  233   a  is floating, cell  240   a  can be turned on, and voltage V 10  can be about 3V. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably avoid programming disturbance to cells  240   a  and/or  250   a.    
       FIG. 5K  is a schematic drawing showing an exemplary method for reading one of two exemplary memory cells. In some embodiments reading cell  240   a , substrate  230   a  can be substantially grounded, voltage V 6  can be higher than voltage V 10 , voltage V 9  can be applied a voltage higher than a predetermined threshold voltage of cell  250   a , such that voltage V 9  can turn on cell  250   a . Voltage V 7  can be a sense voltage. In some embodiments, the sense voltage can be between a “0” state voltage and a “1” state voltage of cell  240   a . In some embodiments having cell  240   a  being “1” state, voltage V 7  can turn on cell  240   a . Electrons can flow from doped region  235   a  to doped region  231   a  through floating doped region  233   a . In some embodiments having cell  240   a  being “0” state, voltage V 7  can not turn on cell  240   a . Electrons thus may not substantially flow from doped region  235   a  to doped region  231   a . In some embodiments reading cell  240   a , voltage V 6  can be about 0.6V, voltage V 7  can be between a “0” state voltage and a “1” state voltage of cell  240   a , doped region  233   a  can be floating, voltage V 9  can turn on cell  250   a , and voltage V 10  can be substantially grounded. 
     In some embodiments reading cell  250   a , substrate  230   a  can be substantially grounded, voltage V 10  can be higher than voltage V 6 , voltage V 7  can be applied a voltage higher than a predetermined threshold voltage of cell  240   a , such that voltage V 7  can turn on cell  240   a . Voltage V 9  can be a sense voltage. In some embodiments, the sense voltage can be between a “0” state voltage and a “1” state voltage of cell  250   a . In some embodiments, this read method can be referred to as a forward read method. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably read cells  240   a  or  250   a.    
       FIG. 6A  is a schematic drawing showing a portion of an exemplary array structure. In some embodiments, a memory array structure comprises a plurality of parallel series of cells and a plurality of bit lines substantially parallel to the plurality of parallel series of cells. In some embodiments, at least one isolation structure  310   a  is configured between two adjacent parallel series of cells. Each of the plurality of parallel series of cells can be configured between two of the plurality of bit lines. The plurality of parallel series of cells can comprise a 2m th  series of cells being configured between a 2m−1 th  series of cells and a 2m+1 th  series of cells. The 2m th  series of cells can comprise 4n+1 th  doped regions coupled to 4n+1 th  doped regions of the 2m+1 th  series of cells, respectively. The 2m th  series of cells can comprise 4n+2 th  and 4n+4 th  doped regions which are floating. The 2m th  series of cells can comprise 4n+3 th  doped regions coupled to 4n+3 th  doped regions of the 2m−1 th  series of cells, respectively, wherein m and n are integers. First word lines can be coupled to a plurality of the first cells of the plurality of parallel series of the cells. Second word lines can be coupled to a plurality of the second cells of the plurality of series of the cells, and so on. In some embodiments, the cells of array structure  300   a  can be cells  210   a ,  220   a ,  240   a , and/or  250   a  described above in conjunction with  FIGS. 5A and 5B . 
     Referring again to  FIG. 6A , in some embodiments, array structure  300   a , for example, can include parallel series of cells  301   a - 307   a  and bit lines BL 1 -BL 8 . Series of cells  301   a - 303   a  can include cells  3011   a - 3018   a ,  3021   a - 3028   a , and  3031   a - 3038   a , respectively. Series of cells  301   a - 303   a  can include doped regions  3111   a - 3119   a ,  3121   a - 3129   a , and  3131   a - 3139   a , respectively. Word lines WL 1 -WL 8  can be configured substantially perpendicular to bit lines BL 1 -BL 8 . Word line WL 1  can be coupled to first cells of the parallel series of cells  301   a - 307   a . Word line WL 2  can be coupled to second cells of the parallel series of cells  301   a - 307   a . For series of cells  302   a , doped regions  3121   a ,  3125   a , and  3129   a  can be coupled to doped regions  3131   a ,  3135   a , and  3139   a , respectively. Doped regions  3123   a  and  3127   a  can be coupled to doped regions  3113   a  and  3117   a , respectively. Doped regions  3122   a ,  3124   a ,  3126   a , and  3128   a  can be floating. 
     In some embodiments, bit lines BL 1 -BL 8  can be coupled to bit line transistors BLT 1 -BLT 8 , respectively. In some embodiments, bit line transistors BLT  1  and BLT  5  can be coupled to a voltage V 11 . Bit line transistor BLT 2  and BLT 6  can be coupled to a voltage V 12 . Bit line transistors BLT 3  and BLT 7  can be coupled to a voltage V 13 . Bit line transistors BLT 4  and BLT 8  can be coupled to a voltage V 14 . In some embodiments, bit line transistors BLT 1 -BLT 8  can be configured to control the applying of voltages V 11 -V 14  to respective bit lines BL 1 -BL 8 . 
       FIG. 6B  is a schematic drawing showing an exemplary method for erasing at least one cell of area  350   a  shown in  FIG. 6A . For embodiments with cells  210   a  and  220   a  described above in conjunction with  FIG. 5A , cells  3053   a  and/or  3054   a  can be erased and have charges, e.g., electrons, trapped in charge storage layers of cells  3053   a  and/or  3054   a . In some embodiments erasing cells  3053   a  and/or  3054   a , the substrate of array structure  300   a  may be substantially grounded, bit line BL 5  can be floating, a voltage of word line WL 3  can be about −20V, doped region  3154   a  can be floating, a voltage of word line WL 4  can be about −20V, and bit line BL 6  can be floating. Due to the voltage drop between word lines WL 3 , WL 4  and the voltage of the substrate of array structure  300   a , electrons can be injected from gates of cells  3053   a  and  3054   a  into charge storage layers of cells  3053   a  and  3054   a , respectively. In some embodiments, this erasing method can be referred to as a negative gate Fowler-Nordheim (−FN) erasing method. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably erase cells  3053   a  and/or  3054   a.    
     In some embodiments, other bit lines such as bit lines BL 4  and BL 7  can be floating, such that cells  3043   a ,  3044   a ,  3063   a , and  3064   a  can be erased. With this configuration, a regional or block erasing can be desirably achieved. 
       FIG. 6C  is a schematic drawing showing an exemplary method for erasing at least one cell of area  350   a  shown in  FIG. 6A . For embodiments with cells  240   a  and  250   a  described above in conjunction with  FIG. 5B , cells  3053   a  and/or  3054   a  can be erased and have charges, e.g., electrons, trapped in floating gates of cells  3053   a  and/or  3054   a . In some embodiments erasing cells  3053   a  and/or  3054   a , the substrate of array structure  300   a  may be substantially grounded, bit line BL 5  can be grounded, a voltage of word line WL 3  can be about 20V, doped region  3154   a  can be floating, a voltage of word line WL 4  can be about 20V, and bit line BL 6  can be grounded. Due to the voltage drop between word lines WL 3 , WL 4  and the voltage of the substrate of array structure  300   a , electrons can be injected from the substrate of array structure  300   a  into floating gates of cells  3053   a  and  3054   a . In some embodiments, this erasing method can be referred to as a positive gate Fowler-Nordheim (+FN) erasing method. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably erase cells  3053   a  and/or  3054   a.    
     In some embodiments, other bit lines such as bit lines BL 4  and BL 7  can be grounded, such that cells  3043   a ,  3044   a ,  3063   a , and  3064   a  can be erased. With this configuration, a regional or block erasing can be desirably achieved. 
       FIG. 6D  is a schematic drawing showing an exemplary process for programming a cell of area  350   a  shown in  FIG. 6A . In some embodiments, cells  3053   a  and/or  3054   a  can be erased and have charges, e.g., electrons, trapped in charge storage layers or floating gates. In some embodiments programming cells  3053   a , the substrate of array structure  300   a  may be substantially grounded. Bit line transistors BLT 5  and BLT 6  (shown in  FIG. 6A ) can be turned on. Bit line BL 5  can be about 0V, a voltage of word line WL 3  can be about −5V, doped region  3154   a  can be floating, a voltage of word line WL 4  can be about 10V for turning on cell  3054   a , and bit line BL 6  can be 5V. Due to the voltage drop between voltages of bit line BL 6  and word line WL 3 , hot holes can be injected into a charge storage layer or floating gate of cell  3053   a  to recombine with trapped electrons, such that cell  3053  can be programmed. In some embodiments, this programming method can be referred to as a band-to-band tunneling hot holes induced programming method. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably erase cells  3053   a  and/or  3054   a.    
     In some embodiments desirably reducing programming disturbance to cell  3063   a , a voltage is applied to bit line BL 7 . The voltage of bit line BL 7  can be lower than the voltage of bit line BL 6 . In some embodiments, the voltage of bit line BL 7  is about 3V. 
     In some embodiments reading cell  3053   a  having a structure similar to cell  220   a  described above in conjunction with  FIG. 5A , a voltage of the substrate of array structure  300   a  can be substantially grounded, a voltage of bit line BL 5  can be higher than a voltage of bit line BL 6 , word line WL 4  can be applied a voltage higher than a predetermined threshold voltage of cell  3054   a , such that the voltage of word line WL 4  can turn on cell  3054   a . A voltage of word line WL 3  can be a sense voltage. In some embodiments, the sense voltage can be between a “0” state voltage and a “1” state voltage of cell  3053   a . In some embodiments having cell  3053   a  being “1” state, the voltage of word line WL 3  can turn on cell  3053   a . Electrons can flow from doped region  3153   a  to doped region  3155   a  through floating doped region  3154   a . In some embodiments having cell  3053   a  being “0” state, the voltage of word line WL 3  can not turn on cell  3053   a . Electrons thus may not substantially flow from doped region  3153   a  to doped region  3155   a . In some embodiments reading cell  3053   a , the voltage of bit line BL 5  can be about 1.6V, the voltage of word line WL 4  can be about 10V, doped region  3154   a  can be floating, a voltage of word line WL 3  can be between a “0” state voltage and a “1” state voltage of cell  3053   a , and a voltage of bit line BL 6  can be substantially grounded. 
     In some embodiments reading cell  3054   a , the substrate of array structure  300   a  can be substantially grounded, a voltage of bit line BL 6  can be higher than a voltage of bit line BL 5 , a voltage of word line WL 3  can be applied a voltage higher than a predetermined threshold voltage of cell  3053   a , such that the voltage of word line WL 3  can turn on cell  3053   a . A voltage of word line WL 4  can be a sense voltage. In some embodiments, the sense voltage can be between a “0” state voltage and a “1” state voltage of cell  3054   a . In some embodiments, this read method can be referred to as a reverse read method. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably read cells  3053   a  or  3054   a.    
     In some embodiments reading cell  3053   a  having a structure similar to cell  250   a  described above in conjunction with  FIG. 5B , the substrate of array structure  300   a  can be substantially grounded, a voltage of bit line BL 6  can be higher than a voltage of bit line BL 5 , word line WL 4  can be applied a voltage higher than a predetermined threshold voltage of cell  3054   a , such that the voltage of word line WL 4  can turn on cell  3054   a . A voltage of word line WL 3  can be a sense voltage. In some embodiments, the sense voltage can be between a “0” state voltage and a “1” state voltage of cell  3053   a . In some embodiments having cell  3053   a  being “1” state, the voltage of word line WL 3  can turn on cell  3053   a . Electrons can flow from doped region  3155   a  to doped region  3153   a  through floating doped region  3154   a . In some embodiments having cell  3053   a  being “0” state, the voltage of word line WL 3  can not turn on cell  3053   a . Electrons thus may not substantially flow from doped region  3155   a  to doped region  3153   a . In some embodiments reading cell  3053   a , bit line BL 5  can be substantially grounded, the voltage of word line WL 4  can be about 8V, doped region  3154   a  can be floating, the voltage of word line WL 3  can be between a “0” state voltage and a “1” state voltage of cell  3053   a , and bit line BL 6  can be about 0.6V. 
     In some embodiments reading cell  3054   a , the substrate of array structure  300   a  can be substantially grounded, the voltage of bit line BL 5  can be higher than the voltage of bit line BL 6 , the voltage of word line WL 3  can be higher than a predetermined threshold voltage of cell  3053   a , such that the voltage of word line WL 3  can turn on cell  3053   a . The voltage of word line WL 4  can be a sense voltage. In some embodiments, the sense voltage can be between a “0” state voltage and a “1” state voltage of cell  3054   a . In some embodiments, this read method can be referred to as a forward read method. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably read cells  3053   a  or  3054   a.    
     Table III shows exemplary methods for operating cells  3053   a  and/or  3054   a  array structure  300   a  described above in conjunction with  FIG. 6A . 
     
       
         
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                   
                 TABLE III 
               
               
                   
                   
               
               
                   
                   
                 Inhibit 
                   
                   
                   
                   
                   
                   
                   
                 Other 
               
               
                   
                 Cell 
                 cell 
                 WL3 
                 WL4 
                 BL4 
                 BL5 
                 BL6 
                 BL7 
                 Substrate 
                 unselected WL 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                 Program (BTB HH) 
                 3053a 
                 3063a 
                 −5 
                 V 
                 12 
                 V 
                 Floating 
                 0 
                 V 
                 5 
                 V 
                 3 V 
                 0 V 
                 0 V or −Vg 
               
               
                   
                 3054a 
                 3044a 
                 12 
                 V 
                 −5 
                 V 
                 3 V 
                 5 
                 V 
                 0 
                 V 
                 Floating 
                 0 V 
                 0 V or −Vg 
               
               
                 Read (Reverse) 
                 3053a 
                   
                 5 
                 V 
                 10 
                 V 
                 Floating 
                 1.6 
                 V 
                 0 
                 V 
                 Floating 
                 0 V 
                 0 V or −Vg 
               
               
                   
                 3054a 
                   
                 10 
                 V 
                 5 
                 V 
                 Floating 
                 0 
                 V 
                 1.6 
                 V 
                 Floating 
                 0 V 
                 0 V or −Vg 
               
               
                 Read (Forward) 
                 3053a 
                   
                 5 
                 V 
                 8 
                 V 
                 Floating 
                 0 
                 V 
                 0.6 
                 V 
                 Floating 
                 0 V 
                 0 V or −Vg 
               
               
                   
                 3054a 
                   
                 8 
                 V 
                 5 
                 V 
                 Floating 
                 0.6 
                 V 
                 0 
                 V 
                 Floating 
                 0 V 
                 0 V or −Vg 
               
             
          
           
               
                 Erase (−FN) 
                 All 
                   
                 −20 
                 V 
                 −20 
                 V 
                 Floating 
                 Floating 
                 Floating 
                 Floating 
                 0 V 
                 −20 V 
               
             
          
           
               
                 Erase (+FN) 
                 All 
                   
                 +20 
                 V 
                 +20 
                 V 
                 0 V 
                 0 
                 V 
                 0 
                 V 
                 0 V 
                 0 V 
                 +20 V 
               
               
                   
               
             
          
         
       
     
     It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably operate cells  3053   a  or  3054   a.    
       FIG. 7A  is a schematic drawing showing a portion of an exemplary array structure. In some embodiments, a memory array structure comprises a plurality of parallel series of cells and a plurality of bit lines substantially parallel to the plurality of series of cells. Each of the plurality of series of cells can be configured between two bit lines. Each of the plurality of parallel series of cells can include 4n+1 th , 4n+2 th , 4n+3 th , and 4n+4 th  doped regions. The 4n+1 th  doped regions can be coupled to first one of the two bit lines, the 4n+2 th , and 4n+4 th  doped region can be floating, and the 4n+3 th  doped regions can be coupled to second one of the two bit lines, wherein n is an integer. In some embodiments, each of the series of cells can be configured between two isolation structures  410 . First word lines can be coupled to the first cells of the plurality of parallel series of the cells. Secondword lines can be coupled to the second cells of the plurality of series of the cells. In some embodiments, the cells of array structure  400   a  can be cells  210   a ,  220   a ,  240   a , and/or  250   a  described above in conjunction with  FIGS. 5A and 5B . 
     Referring again to  FIG. 7A , in some embodiments, array structure  400   a , for example, can include parallel series of cells  401   a - 404   a  and bit lines BL 1 -BL 8 . Series of cells  401   a  and  402   a  can include cells  4011   a - 4018   a , and  4021   a - 4028   a , respectively. Series of cells  401   a  and  402   a  can include doped regions  4111   a - 4119   a , and  4121   a - 4129   a , respectively. Word lines WL 1 -WL 8  can be configured substantially perpendicular to bit lines BL 1 -BL 8 . Word line WL 1  can be coupled to first cells of the parallel series of cells  401   a - 404   a . Word line WL 2  can be coupled to second cells of the parallel series of cells  401   a - 404   a . For series of cells  402   a , doped regions  4121   a ,  4125   a , and  4129   a  can be coupled to bit line BL 4 . Doped regions  4123   a  and  4127   a  can be coupled to bit line BL 3 . Doped regions  4122   a ,  4124   a ,  4126   a , and  4128   a  can be floating. 
     In some embodiments, bit lines BL 1 -BL 8  can be coupled to bit line transistors BLT 1 -BLT 8 , respectively. In some embodiments, bit line transistors BLT 1  and BLT 5  can be coupled to a voltage V 15 . Bit line transistors BLT 2  and BLT 6  can be coupled to a voltage V 16 . Bit line transistors BLT 3  and BLT 7  can be coupled to a voltage V 17 . Bit line transistors BLT 4  and BLT 8  can be coupled to a voltage V 18 . In some embodiments, bit line transistors BLT 1 -BLT 8  can be configured to control the applying of voltages V 15 -V 18  to respective bit lines BL 1 -BL 8 . 
       FIG. 7B  is a schematic drawing showing an exemplary method for erasing at least one cell of area  450   a  shown in  FIG. 7A . For embodiments with cells  210   a  and  220   a  described above in conjunction with  FIG. 5A , cells  4043   a  and/or  4044   a  can be erased and have charges, e.g., electrons, trapped in charge storage layers of cells  4043   a  and/or  4044   a . In some embodiments erasing cells  4043   a  and/or  4044   a , the substrate of array structure  400   a  may be substantially grounded, bit line BL 7  can be floating, a voltage of word line WL 3  can be about −20V, doped region  4144   a  can be floating, a voltage of word line WL 4  can be about −20V, and bit line BL 8  can be floating. Due to the voltage drop between word lines WL 3 , WL 4  and the voltage of the substrate of array structure  400   a , electrons can be injected from gates of cells  4043   a  and  4044   a  into charge storage layers of cells  4043   a  and  4044   a , respectively. In some embodiments, this erasing method can be referred to as a −FN erasing method. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably erase cells  4043   a  and/or  4044   a.    
     In some embodiments, other bit lines such as bit lines BL 5  and BL 6  can be floating, such that cells  4033   a  and  4034   a  can be erased. With this configuration, a regional or block erasing can be desirably achieved. 
       FIG. 7C  is a schematic drawing showing an exemplary method for erasing at least one cell of area  450   a  shown in  FIG. 7A . For embodiments with cells  240   a  and  250   a  described above in conjunction with  FIG. 5B , cells  4043   a  and/or  4044   a  can be erased and have charges, e.g., electrons, trapped in floating gates of cells  4043   a  and/or  4044   a . In some embodiments erasing cells  4043   a  and/or  4044   a , the substrate of array structure  400   a  may be substantially grounded, bit line BL 7  can be grounded, a voltage of word line WL 3  can be about 20V, doped region  4144   a  can be floating, a voltage of word line WL 4  can be about 20V, and bit line BL 8  can be grounded. Due to the voltage drop between word lines WL 3 , WL 4  and the voltage of the substrate of array structure  400   a , electrons can be injected from the substrate of array structure  400  into floating gates of cells  4043   a  and  4044   a . In some embodiments, this erasing method can be referred to as a +FN erasing method. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably erase cells  4043   a  and/or  4044   a.    
     In some embodiments, other bit lines such as bit lines BL 5  and BL 6  can be grounded, such that cells  4033   a  and  4034   a  can be erased. With this configuration, a regional or block erasing can be desirably achieved. 
       FIG. 7D  is a schematic drawing showing an exemplary process for programming a cell of area  450   a  shown in  FIG. 7A . In some embodiments, cells  4043   a  and/or  4044   a  can be erased and have charges, e.g., electrons, trapped in charge storage layers or floating gates. In some embodiments programming cells  4043   a , the substrate of array structure  400   a  may be substantially grounded. Bit line transistors BLT 7  and BLT 8  (shown in  FIG. 7A ) can be turned on. Bit line BL 8  can be about 0V, a voltage of word line WL 3  can be about −5V, doped region  4144   a  can be floating, a voltage of word line WL 4  can be about 10V for turning on cell  4044   a , and bit line BL 7  can be 5V. Due to the voltage drop between voltages of bit line BL 7  and word line WL 3 , hot holes can be injected into a charge storage layer or floating gate of cell  4043   a  to recombine with trapped electrons, such that cell  4043   a  can be programmed. In some embodiments, this programming method can be referred to as a band-to-band tunneling induced hot hole programming method. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably erase cells  4043   a  and/or  4044   a.    
     In some embodiments reading cell  4043   a  having a structure similar to cell  220   a  described above in conjunction with  FIG. 5A , a voltage of the substrate of array structure  400   a  can be substantially grounded, a voltage of bit line BL 8  can be higher than a voltage of bit line BL 7 , word line WL 4  can be applied a voltage higher than a predetermined threshold voltage of cell  4044   a , such that the voltage of word line WL 4  can turn on cell  4044   a . A voltage of word line WL 3  can be a sense voltage. In some embodiments, the sense voltage can be between a “0” state voltage and a “1” state voltage of cell  4043   a . In some embodiments having cell  4043   a  being “1” state, the voltage of word line WL 3  can turn on cell  4043   a . Electrons can flow from doped region  4143   a  to doped region  4145   a  through floating doped region  4144   a . In some embodiments having cell  4043   a  being “0” state, the voltage of word line WL 3  can not turn on cell  4043   a . Electrons thus may not substantially flow from doped region  4143   a  to doped region  4145   a . In some embodiments reading cell  4043   a , the voltage of bit line BL 8  can be about 1.6V, the voltage of word line WL 4  can be about 10V, doped region  4144   a  can be floating, a voltage of word line WL 3  can be between a “0” state voltage and a “1” state voltage of cell  4043   a , and a voltage of bit line BL 7  can be substantially grounded. 
     In some embodiments reading cell  4044   a , the substrate of array structure  300   a  can be substantially grounded, a voltage of bit line BL 7  can be higher than a voltage of bit line BL 8 , a voltage of word line WL 3  can be applied a voltage higher than a predetermined threshold voltage of cell  4043   a , such that the voltage of word line WL 3  can turn on cell  4043   a . A voltage of word line WL 4  can be a sense voltage. In some embodiments, the sense voltage can be between a “0” state voltage and a “1” state voltage of cell  4044   a . In some embodiments, this read method can be referred to as a reverse read method. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably read cells  4043   a  or  4044   a.    
     In some embodiments reading cell  4043   a  having a structure similar to cell  250   a  described above in conjunction with  FIG. 5B , the substrate of array structure  400   a  can be substantially grounded, a voltage of bit line BL 7  can be higher than a voltage of bit line BL 8 , word line WL 4  can be applied a voltage higher than a predetermined threshold voltage of cell  4044   a , such that the voltage of word line WL 4  can turn on cell  4044   a . A voltage of word line WL 3  can be a sense voltage. In some embodiments, the sense voltage can be between a “0” state voltage and a “1” state voltage of cell  4043   a . In some embodiments having cell  4043   a  being “1” state, the voltage of word line WL 3  can turn on cell  4043   a . Electrons can flow from doped region  4145   a  to doped region  4143   a  through floating doped region  4144   a . In some embodiments having cell  4043   a  being “0” state, the voltage of word line WL 3  can not turn on cell  4043   a . Electrons thus may not substantially flow from doped region  4145   a  to doped region  4143   a . In some embodiments reading cell  4043   a , bit line BL 8  can be substantially grounded, the voltage of word line WL 4  can be about 8V, doped region  4144   a  can be floating, the voltage of word line WL 3  can be between a “0” state voltage and a “1” state voltage of cell  4043   a , and bit line BL 7  can be about 0.6V. 
     In some embodiments reading cell  4044   a , the substrate of array structure  400   a  can be substantially grounded, the voltage of bit line BL 8  can be higher than the voltage of bit line BL 7 , the voltage of word line WL 3  can be higher than a predetermined threshold voltage of cell  4043   a , such that the voltage of word line WL 3  can turn on cell  4043   a . The voltage of word line WL 4  can be a sense voltage. In some embodiments, the sense voltage can be between a “0” state voltage and a “1” state voltage of cell  4044   a . In some embodiments, this read method can be referred to as a forward read method. It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably read cells  4043   a  or  4044   a.    
     Table IV shows exemplary methods for operating cells  4043   a  and/or  4044   a  array structure  400   a  described above in conjunction with  FIG. 7A . 
     
       
         
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                   
                 TABLE IV 
               
               
                   
                   
               
               
                   
                 Cell 
                 WL3 
                 WL4 
                 BL5 
                 BL6 
                 BL7 
                 BL8 
                 Substrate 
                 Other unselected 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                 Program (BTB HH) 
                 3053a 
                 −5 
                 V 
                 12 
                 V 
                 Floating 
                 Floating 
                 5 
                 V 
                 0 
                 V 
                 0 V 
                 0 V or −Vg 
               
               
                   
                 3054a 
                 12 
                 V 
                 −5 
                 V 
                 Floating 
                 Floating 
                 0 
                 V 
                 5 
                 V 
                 0 V 
                 0 V or −Vg 
               
               
                 Read (Reverse) 
                 3053a 
                 5 
                 V 
                 10 
                 V 
                 Floating 
                 Floating 
                 0 
                 V 
                 1.6 
                 V 
                 0 V 
                 0 V or −Vg 
               
               
                   
                 3054a 
                 10 
                 V 
                 5 
                 V 
                 Floating 
                 Floating 
                 1.6 
                 V 
                 0 
                 V 
                 0 V 
                 0 V or −Vg 
               
               
                 Read (Forward) 
                 3053a 
                 5 
                 V 
                 8 
                 V 
                 Floating 
                 Floating 
                 0.6 
                 V 
                 0 
                 V 
                 0 V 
                 0 V or −Vg 
               
               
                   
                 3054a 
                 8 
                 V 
                 5 
                 V 
                 Floating 
                 Floating 
                 0 
                 V 
                 0.6 
                 V 
                 0 V 
                 0 V or −Vg 
               
             
          
           
               
                 Erase (−FN) 
                 All 
                 −20 
                 V 
                 −20 
                 V 
                 Floating 
                 Floating 
                 Floating 
                 Floating 
                 0 V 
                 −20 V 
               
             
          
           
               
                 Erase (+FN) 
                 All 
                 +20 
                 V 
                 +20 
                 V 
                 0 V 
                 0 V 
                 0 
                 V 
                 0 
                 V 
                 0 V 
                 +20 V 
               
               
                   
               
             
          
         
       
     
     It is noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can modify the voltages to desirably operate cells  4043   a  or  4044   a.    
     While foregoing is directed to some exemplary embodiments, other and further embodiments may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.