Abstract:
A scheme (e.g., one or more methods, circuits and/or architectures) for detecting the difference in frequencies between two periodic (e.g., clock) signals and/or for reliably assuring the frequency of an oscillating circuit (e.g., a voltage controlled oscillator [VCO], a phase locked loop [PLL] containing a VCO, etc.). The present invention is particularly useful for clock recovery in data communications devices and more particularly in asynchronous transfer mode (ATM) devices, such as SONET/SDH transmitters, receivers and/or transceivers.

Description:
This application claims the benefit of U.S. Provisional Application No. 60/066,152, filed Nov. 19, 1997, which is hereby incorporated by reference in its entirety. 

   FIELD OF THE INVENTION 
   The present invention concerns frequency difference detector circuits generally, and more particularly, a circuit, method and/or architecture for detecting the difference between two periodic signals. 
   BACKGROUND OF THE INVENTION 
   Referring to  FIG. 1 , a circuit (or phase locked loop (PLL))  10  is shown illustrating a conventional scheme for clock recovery. The circuit  10  generally comprises a frequency detector  12 , a phase detector  14 , a multiplexor  16 , a loop filter  18 , a voltage controlled oscillator (VCO)  20 , a frequency difference detector  21  and a buffer  22 . The PLL  10  uses the frequency detector  12  and the frequency different detector  21  to ensure that the frequency of a signal presented by the VCO  20  is within a predetermined frequency range relative to an external reference signal (e.g., REFCLK) presented to the frequency detector  12 . The frequency detector  12  generates pulses whose width is proportional to frequency difference of the incoming signals. The phase detector  14  ensures that the phase of the signal presented by the VCO  20  is aligned with an incoming data stream (e.g., DATA) presented to the phase detector  14 . The frequency difference detector generates a control signal (e.g., LINKFAULT) indicating the status of the VCO frequency to the PLL compared to an external device (not shown). The signal to the external device is typically sent through a dedicated output pin connected to the buffer  22 . 
   Referring to  FIG. 2 , a circuit  30  illustrating a conventional scheme for detecting the difference in frequencies between two clock signals is shown. The circuit  30  comprises a counter  32 , a counter  34  and a compare block (or circuit)  36 . The counter  32  counts the cycles of a reference clock signal (e.g., REFCLK). The counter  34  counts the cycles of a VCO clock signal (e.g., VCOCLK). The circuit  30  uses a signal START to initiate the VCO clock signal counter  34 . The signal START may be generated periodically (i.e., once every certain number of cycles) to provide a periodic timing reference. The counter  32  tracks the number of VCO clock signal cycles to generate a count signal (e.g., via VCO_COUNT). The counter  34  counts the number of reference clock signal cycles to generate a count signal (e.g., via REF_COUNT). The compare circuit  36  compares the signal VCO_COUNT with the signal REF_COUNT to determine whether or not the VCO is presenting (or generating) a clock signal having a frequency within a predetermined window (i.e., within predetermined upper and lower boundaries, or a predetermined frequency range, relative to the reference clock signal REFCLK). The compare circuit  36  indicates that the VCO clock signal frequency is not within the predetermined window by presenting an active control signal (e.g., OutOfLock). 
   The circuit  30  gives rise to a problem in that an Out-of-lock signal (OOL) may be inadvertently or prematurely deactivated when the PLL pulls its output signal within the allowable predetermined frequency window, only to be reasserted a very short time later (typically less than 100 msec but at least one range compare cycle later; in one example, at least 50 μsec.) The inadvertent or premature deactivation of the signal OOL typically occurs as a result of jitter or noise or an artifact of the frequency-centering process. The signal OOL may “glitch” which may make designing a circuit board very difficult, particularly when the signal OOL appears at an I/O pin. 
   SUMMARY OF THE INVENTION 
   The present invention concerns a scheme (e.g., one or more methods, circuits and/or architectures) for detecting the difference in frequencies between two periodic (e.g., clock) signals and/or for reliably assuring the frequency of an oscillating circuit (e.g., a voltage controlled oscillator [VCO], a phase locked loop [PLL] containing a VCO, etc.). The present invention is particularly useful for clock recovery in data communications devices and more particularly in asynchronous transfer mode (ATM) devices, such as SONET/SDH transmitters, receivers and/or transceivers. 
   The objects, features and advantages of the present invention include (i) providing a reliable method, circuit and/or architecture for detecting the difference in frequencies between two periodic signals, (ii) indicating the acceptability of an oscillating circuit frequency, and/or (iii) providing clock recovery in a data communications device. A further object of the present invention is to provide a data communications device such as a SONET/SDH transmitter, receiver or transceiver configured to conduct such a method, or including such a circuit or architecture. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
       FIG. 1  shows a diagram of a conventional PLL having an Out-of-lock signal-generating scheme based on a single predetermined acceptable frequency window; 
       FIG. 2  illustrates a diagram of a conventional clock recovery scheme that may be implemented in the PLL of  FIG. 1 ; 
       FIG. 3  illustrates a diagram of a first embodiment of a clock recovery scheme of the present invention suitable for use in a PLL such as that of  FIG. 1 ; 
       FIG. 4  illustrates a timing diagram of various waveforms generated by the circuit of  FIG. 3 ; 
     FIGS.  5 ( a ),  5 ( b ),  5 ( c ),  5 ( d ),  5 ( e ) and  5 ( f ) illustrate timing diagrams of signals presented and received from the compare/state machine circuitry of  FIG. 3 ; 
       FIG. 6  illustrates an exemplary state diagram for the state machine of  FIG. 3 ; 
       FIG. 7  illustrates a diagram of a second embodiment of the clock recovery scheme of the present invention, also suitable for use in a PLL such as that of  FIG. 1 , and 
       FIG. 8  is a detailed block diagram illustrating the embodiment of FIG.  3 . 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 3  illustrates a frequency difference detection circuit  100  in accordance with a preferred embodiments of the present invention. The circuit  100  generally comprises a counter  102 , a counter  104  and a compare/state machine  106 . The counter  102  generally comprises an input  108  configured to receive a reference clock signal (e.g., REFCLK) and an output  110  configured to present a reference count signal (e.g., REF_COUNT). The compare/state machine  106  comprises an input  112  that may receive the signal REF_COUNT, an output  114  that may present an Out-Of-Lock signal (e.g., OutOfLock), an output  116  that may present a signal to the counter  104  and an input  118  that may receive a signal from the counter  104 . The counter  104  generally comprises an input  120  that may receive a VCO clock signal (e.g., VCOCLK), an input  122  that may receive the signal (e.g., START) from the output  116  of the compare/state machine  106 , and an output  124  that may present a signal (e.g., VcoCount) to the input  118  of the compare/state machine  106 . The signal REF_COUNT and the signal VcoCount may be multi-bit signals (e.g., an n-bit signal). The circuit  100  generally assures that the signal OutOfLock is not deasserted prior to an output of the VCO being safely within an outer predetermined window of acceptability. The circuit  100  may minimize the inadvertent (or temporary) deassertion of the OutOfLock signal during frequency and/or phase correction due to noise or jitter. The circuit  100  may be used in any PLL, but may be particularly useful as a frequency difference detector in the PLL of FIG.  1 . 
   The compare/state machine  106  may include a state machine that provides hysteresis to the signal OutOfLock. The compare/state machine  106  may be configured to determine when the VCO/PLL clock signal is within either or both of at least two predetermined windows of acceptability. An outer window may primarily be an indicator of the VCO/PLL falling outside the range of acceptable frequencies (“out of lock”) and an inner window may primarily be an indicator of the VCO/PLL operating safely within the range of acceptable frequencies (“in lock”). In response to the state machine output(s), the compare circuit generates an out-of-lock control signal which indicates the VCO clock signal status as described above. 
   Referring to  FIG. 4 , a timing diagram of the various signals generated by the circuit  100  is shown. The signal REFCLK is shown generally as a periodic signal. The signal START has a transition  130  that begins the execution of the VCO counter  104 . The signal UPDATE has a transition  132  that generally indicates an update to the VCO frequency shall occur. The signal InnerBoundary has a transition  134  and a transition  136  that generally define the InnerBoundary of operating frequencies that are acceptable. The signal OuterBoundary has a transition  138  and a transition  140  that generally define the outer range of acceptable frequencies. 
     FIGS. 5   a ,  5   b ,  5   c ,  5 ( d ),  5 ( e ) and  5 ( f ) illustrate exemplary waveforms for signals received by and presented from the compare/state machine  106 . In FIGS.  5 ( a ),  5 ( b ) and  5 ( c ), the first signal Update represents a reference clock timing signal derived from the reference clock counter  102 . For example, the reference clock timing signal may be a decoded reference clock signal (e.g., one that exhibits a rising and falling transition once every predetermined number of cycles, such as every 2n cycles, every m·2 n  cycles, or every (m/p)2 n  cycles, where n is a number of at least 2, preferably from 5 to 20, and m and p are each independently a number from 1 to 9, preferably from 1 to 6). 
   The compare/state machine  106  may track a transition of the reference clock timing signal (e.g., the rising edge of Update) and generate an output signal in response thereto. The second and third signals (i.e., InnerBoundary and OuterBoundary, respectively) may represent the inner acceptable frequency window (indicating the VCO clock signal operating safely within the range of acceptable frequencies) and the outer acceptable frequency window (indicating the VCO clock signal falling outside the range of acceptable frequencies). In one example, the boundary signals may be decoded signals received from the VCO clock counter. The signal OutOfLock may represent the signal presented at output  114  which may be generated in response to the reference clock timing signal transition (e.g., Update). The signal OutOfLock may have a state that may depend on the states of the boundary signals. The compare/state machine  106  may generate the signal OutOfLock by conventional logic circuits (e.g., AND, NAND, OR, NOR, XOR, XNOR, etc.) in accordance with known practices and techniques. 
   In FIG.  5 ( a ), the rising (or triggering) edge of the signal UPDATE occurs outside the logic HIGH portion of both the signal, InnerBoundary and the signal OuterBoundary, indicating the VCO clock signal frequency is not within the range of acceptable frequencies. Consequently, the signal OutOfLock remains asserted (e.g., in an active HIGH binary logic state). 
   In FIG.  5 ( b ), the rising (or triggering) edge of the signal UPDATE occurs when the signal, InnerBoundary is at a logic LOW and the signal OuterBoundary is at a logic HIGH, also indicating the VCO clock signal frequency is not within the range of acceptable frequencies. Consequently, the signal OutOfLock remains asserted (e.g., in an active HIGH binary logic state). 
   In FIG.  5 ( c ), the rising (or triggering) edge of the signal UPDATE occurs when both the signal InnerBoundary and the signal OuterBoundary are at a logic HIGH, indicating that the VCO clock signal frequency is within the range of acceptable frequencies. Consequently, the signal OutOfLock may be deasserted (e.g., an active LOW binary logic state). 
   In FIG.  5 ( d ), the rising (or triggering) edge of the signal UPDATE occurs when both the signal InnerBoundary and the signal OuterBoundary are at a logic HIGH, indicating that the VCO clock signal frequency is inside the range of acceptable frequencies. Consequently, the signal OutOfLock generally remains deasserted (e.g., as an active LOW binary logic state) since the VCO clock signal frequency is inside the acceptable range. 
   In FIG.  5 ( e ), the rising (or triggering) edge of the signal UPDATE occurs when the signal InnerBoundary is at a logic LOW and the signal OuterBoundary is at a logic HIGH, indicating that the VCO clock signal frequency is in the intermediate range of frequencies. Consequently, the signal OutOfLock generally remains deasserted (e.g., in an active LOW binary logic state) since the VCO clock signal frequency may return to within the acceptable range. 
   In FIG.  5 ( f ), the rising (or triggering) edge of the signal UPDATE occurs when both the signal, InnerBoundary and the signal OuterBoundary are LOW, indicating that the VCO clock signal frequency is not within the range of acceptable frequencies. Consequently, the signal OutOfLock generally may be asserted since the VCO clock signal frequency may no longer be within the acceptable range. 
   The inner and outer acceptable frequency windows are selected and generated such that (i) the rising transitions of the inner acceptable frequency window signal generally occur after the rising transitions of the outer acceptable frequency window and (ii) the falling transitions of the inner acceptable frequency window signal generally occur before the falling transitions of the outer acceptable frequency window. One consequence of this configuration may be that the reference clock timing signal may trigger transitions between an active inner and outer acceptable frequency window signals (see, e.g., FIG.  5 ( c ), where both inner and outer acceptable frequency window signals are active HIGH binary logic state signals), which may not affect the state of the signal OutOfLock. Thus, the state diagram for the present state machine  106  may be represented by FIG.  6 . 
   In other words, once an “out-of-lock” state is asserted, a device containing the present invention may indicate the “out-of-lock” state until the frequency difference between the VCO clock and the reference clock is less than x ppm. After the “out-of-lock” state is deasserted, the signal OutOfLock may stay deasserted until the frequency difference between the VCO clock and the reference clock is greater than y ppm, where y&gt;x (preferably, y≧1.1x, more preferably, y≧1.5x, even more preferably, y≧2x, and most preferably, y≧2.5x). In one embodiment, x is about 500 ppm and y is about 1500 ppm (y≧3x) for a PLL receiving either a 6.48 MHZ or 19.44 MHZ reference clock signal. However, further examples of x and y may include those where x is from 20 to 5000 ppm, preferably from 50 to 3000 ppm, more preferably from 100 to 1000 ppm, and where y is from 50 to 10,000 ppm, preferably from 100 to 5000 ppm, more preferably from 200 to 3000 ppm. 
   One benefit of the circuit  100  may be the ability to minimize the likelihood of an inadvertent deassertion of the signal OutOfLock. The built-in hysteresis of the present compare/state machine  106  generally minimizes the probability of falsely deasserting an out-of lock state, only to reassert the true out-of-lock state a very short time later. As a result, the present invention may help to avoid unusual (or defective) start-up signal sequences in circuit boards containing a data communications device comprising the present clock recovery-based PLL. 
   Referring to  FIG. 7 , a circuit  100 ′ illustrates an alternate embodiment of the present invention. Comparing the circuit  100 ′ to the circuit  100 , in circuit  100 ′, the VCO clock counter is enabled (initiated) by the most significant bit of the reference clock counter output signal (e.g., RefMsb). At the same time, a signal RefMsb may replace the decoded reference clock counter output signal (e.g., the signal Update in FIGS.  5 ( a )-( c )), which may simplify the circuitry and minimize the effects of process variations which may be inherent in making the circuitry. Alternatively, the decoded reference clock counter output signal may be generated in response to the signal RefMsb. However, similar to the circuit  100 , the decoded reference clock counter output signal may be generated simply in response to the reference clock counter output (not shown in FIG.  6 ). 
   Referring to  FIG. 8 , a detailed block diagram illustrating the circuit  100  is shown. In one example, the circuit  106  may comprise a circuit  130  and a circuit  132 . The circuit  130  may have an input  140  that may receive the signal RefCount, an output  142  that may present the signal START, an input  144  that may receive the signal VcoCount, an output  146  that may present the signal VcoCount, an output  148  that may present the signal InnerBoundary, and an output  150  that may present the signal OuterBoundary. The circuit  132  may have an input  152  that may receive the signal OuterBoundary, an input  154  that may receive the signal InnerBoundary, an input  156  that may receive the signal VcoCount and an output  158  that may present the signal OutOfLock. The circuit  130  may be, in one implementation, a state machine. The circuit  132  may be a compare circuit. 
   While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.