Abstract:
In a delay failure test circuit, a delay failure test between two clock domains among a plurality of clock domains having different operation clock rates is performed. The delay failure test circuit inputs, to a first clock domain, a clock signal having only a launch edge for transferring data from the first clock domain to a second clock domain, and to input, to the second clock domain, a clock signal having only a capture edge for capturing the data.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2006-071333, filed on Mar. 15, 2006, the entire contents of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a delay failure test circuit that detects a delay failure between clock domains in a tested circuit such as large scale integration (LSI).  
         [0004]     2. Description of the Related Art  
         [0005]     Recently, it has become increasingly important in shipment tests of LSI to detect a delay failure in addition to a stuck-at failure. To improve a detection rate of the delay failure, it is important to detect the delay failure between clock domains.  
         [0006]     If a pattern for detecting a delay failure is generated in a conventional test pattern generating technology, first, a capture clock and a clock on the launch side are analyzed in a tested circuit. If the clocks on the launch side and the capture side are the same clocks, the test pattern can be easily generated. If the clocks on the launch side and the capture side are different, it is difficult to generate the test pattern because timing of the clocks must be considered.  
         [0007]      FIG. 1  is a circuit diagram of LSI including a conventional delay failure test circuit. In  FIG. 1 , LSI  1100  is a tested circuit that includes plural clock domains CD (CD 1  to CD 3  in the example shown in  FIG. 1 ) and a delay failure test circuit  1101  that detects delay failures of the clock domains CD (CD 1  to CD 3 ).  
         [0008]     The delay failure test circuit  1101  includes a clock source CLK, a reset input terminal R, and a scan mode input terminal SM. Frequency dividing circuits div 1  to div 3  and selectors  1111  to  1113  are also included for the clock domains CD 1  to CD 3 , respectively. As shown in  FIG. 1 , the same characters are added to input/output terminals and signals input/output to/from the input/output terminals.  
         [0009]     A clock signal CLK is input to each of the frequency dividing circuits div 1  to div 3  and to each of the selectors  1111  to  1113 . A reset signal R is inverted and input to each of the frequency dividing circuits div 1  to div 3 . A scan mode signal SM is input to each of the selectors  1111  to  1113 .  
         [0010]     Each of the frequency dividing circuits div 1  to div 3  divides the incoming clock signal CLK. As shown in  FIG. 2 , when the clock signal CLK is a reference clock signal, the clock signal CLK is divided into N frequency-divided clocks (N is a real number). For example, the frequency dividing circuit div 1  divides the clock signal CLK to generate ⅛ frequency and outputs a frequency-divided clock signal CLK 1  (=⅛ CLK).  
         [0011]     The frequency dividing circuit div 2  divides the clock signal CLK to generate ¼ frequency and outputs a frequency-divided clock signal CLK 2  (=¼ CLK). The frequency dividing circuit div 3  divides the clock signal CLK to generate ½ frequency and outputs a frequency-divided clock signal CLK 3  (=½ CLK).  
         [0012]     At the subsequent stage to the frequency dividing circuits div 1  to div 3 , the selectors  1111  to  1113  are connected respectively. The frequency-divided clock signals CLK 1  to CLK 3  are input from the frequency dividing circuits div 1  to div 3  at the preceding stage to the selectors  1111  to  1113 , respectively. The clock signal CLK is also input to each of the selectors  1111  to  1113 . Each of the selectors  1111  to  1113  selects an output clock signal based on the scan mode signal SM.  
         [0013]     Specifically, if the scan mode signal SM is input, each of the selectors  1111  to  1113  outputs the clock signal CLK. On the other hand, if the scan mode signal SM is not input, the selectors  1111  to  1113  outputs the frequency-divided clock signals CLK 1  to CLK 3  from the frequency dividing circuits div 1  to div 3  at the preceding stage, respectively.  
         [0014]     At the subsequent stage to the selectors  1111  to  1113 , the clock domains CD 1  to CD 3  are connected via clock buffers  1121  to  1123  respectively. In other words, the frequency-divided clock signals CLK 1  to CLK 3  output from the selectors  1111  to  1113  are input to the clock domains CD 1  to CD 3  via the clock buffers  1121  to  1123 , respectively.  
         [0015]     In such LSI  1100 , the following three types of data transfer are possible:  
         [0016]     (1) data transfer between the clock domains CD 1  and CD 2  (an arrow A of  FIG. 1 );  
         [0017]     (2) data transfer between the clock domains CD 2  and CD 3  (an arrow B of  FIG. 1 ); and  
         [0018]     (3) data transfer between the clock domains CD 1  and CD 3  (an arrow C of  FIG. 1 ).  
         [0019]     To detect a delay failure in the LSI  1100 , two edges, i.e., launch/capture edges must be put in a one-on-one relationship. The launch edge is a clock serving as timing of outputting data and the capture edge is a clock serving as timing of capturing the output data.  
         [0020]      FIG. 2  is a timing chart of the clock signal CLK and the frequency-divided clock signals CLK 1  to CLK 3  at the time of the failure detection of the LSI  1100 . With regard to the data transfer from the clock domain CD 3  to the clock domain CD 1 , the clock must be switched from the frequency-divided clock signal CLK 3  to the frequency-divided clock signal CLK 1  to achieve the data transfer.  
         [0021]     Specifically, until a clock of a second cycle (( 2 ) of CLK 1 ) is input for the frequency-divided clock signal CLK 1 , clocks of four cycles (( 1 ) to ( 4 ) of CLK 3 ) are input for the frequency-divided clock signal CLK 3 .  
         [0022]     That is, since four launch edges (( 1 ) to ( 4 ) of CLK 3 ) exist corresponding to one capture edge (( 2 ) of CLK 1 ) in this case, the launch edges and the capture edge are not put in the one-on-one corresponding relationship.  
         [0023]     Therefore, for example, a test pattern for detecting a delay failure cannot be generated if data launched at the clock (( 4 ) of CLK 3 ) of the fourth cycle of the frequency-divided clock signal CLK 3  are captured at the capture edge (( 2 ) of CLK 1 ) of the frequency-divided clock signal CLK 1  (“a” in  FIG. 2 ).  
         [0024]     On the other hand, with regard to the data transfer from the clock domain CD 1  to the clock domain CD 3 , the clock must be switched from the frequency-divided clock signal CLK 1  to the frequency-divided clock signal CLK 3  to achieve the data transfer.  
         [0025]     As is the case with the above description, capture edges (( 2 ) to ( 7 ) of CLK 3 ) are generated in the frequency-divided clock signal CLK 3  corresponding to the launch edge (( 1 ) of CLK 1 ) of the frequency-divided clock signal CLK 1 . Therefore, a delay failure cannot be detected at a position actually desired (e.g., “b” in  FIG. 2 ).  
         [0026]     To eliminate this problem, a delay failure test circuit is suggested which aligns rising edges of plural clock domains (e.g., Published Japanese Translation of PCT Application No. 2004-538466).  
         [0027]     However, according to the conventional technology of Published Japanese Translation of PCT Application No. 2004-538466, an influence of signal change among plural first pulses (e.g., an influence of a signal change between a first pulse of clkout( 1 ) and a first pulse of clkout( 0 ) or lastclkout) must be considered at the time of the generation of the test pattern. Therefore, since plural clocks are operated at the same time, all circuits become targets of the test and the generation of the test pattern becomes complicated.  
       SUMMARY OF THE INVENTION  
       [0028]     It is an object of the present invention to at least solve the above problems in the conventional technologies.  
         [0029]     With a delay failure test circuit according to one aspect of the present invention, a delay failure test between two clock domains among a plurality of clock domains having different operation clock rates is performed. The delay failure test circuit is configured to input, to a first clock domain, a clock signal having only a launch edge for transferring data from the first clock domain to a second clock domain, and to input, to the second clock domain, a clock signal having only a capture edge for capturing the data.  
         [0030]     With a delay failure test circuit according to another aspect of the present invention, a delay failure test within a clock domain among a plurality of clock domains having different operation clock rates is performed. The delay failure test circuit is configured to generate only a launch edge and a capture edge from an operation clock of the clock domain, to mask an operation clock of other clock domains, and to input, to the clock domain, a clock signal having the launch edge and the capture edge.  
         [0031]     The other objects, features, and advantages of the present invention are specifically set forth in or will become apparent from the following detailed description of the invention when read in conjunction with the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0032]      FIG. 1  is a circuit diagram of LSI including the conventional delay failure test circuit;  
         [0033]      FIG. 2  is a timing chart of the clock signal CLK and the frequency-divided clock signals CLK 1  to CLK 3  at the time of the failure detection of the LSI including the conventional delay failure test circuit;  
         [0034]      FIG. 3  is a circuit diagram of LSI including the delay failure test circuit according to the first embodiment of the present invention;  
         [0035]      FIG. 4  is a timing chart of operation waveforms of MODE 1;  
         [0036]      FIGS. 5A  to  5 C are timing charts of waveforms at the time of the verification of the switching in the operation of MODE 1;  
         [0037]      FIG. 6  is a timing chart of operation waveforms of MODE 2;  
         [0038]      FIGS. 7A  to  7 C are timing charts of waveforms at the time of the verification of the switching in the operation of MODE 2;  
         [0039]      FIGS. 8A  to  8 C are timing charts of waveforms at the time of the verification of the switching in the operation of MODE 3;  
         [0040]      FIG. 9  is a circuit diagram of LSI including the delay failure test circuit according to the second embodiment of the present invention;  
         [0041]      FIGS. 10A  to  10 C are timing charts of waveforms at the time of the verification of the switching in the operation of MODE 1;  
         [0042]      FIGS. 11A  to  11 C are timing charts of waveforms at the time of the verification of the switching in the operation of MODE 2; and  
         [0043]      FIGS. 12A  to  12 C are timing charts of waveforms at the time of the verification of the switching in the operation of MODE 3. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0044]     Exemplary embodiments of the present invention will be explained in detail below with reference to the accompanying drawings. In the embodiments, the same characters are added to input/output terminals and signals input/output to/from the input/output terminals. For example, in  FIG. 3 , CLK represents both a clock source and a clock signal from the clock source.  
         [0045]      FIG. 3  is a circuit diagram of LSI including a delay failure test circuit according to a first embodiment of the present invention. In  FIG. 3 , LSI  100  is a tested circuit that includes plural (in the example shown in  FIG. 3 , three) clock domains CD (CD 1  to CD 3 ) and a delay failure test circuit  101  that detects failures of the clock domains CD (CD 1  to CD 3 ).  
         [0046]     The delay failure test circuit  101  includes the clock source CLK, a reset input terminal R, and a scan mode input terminal SM, two launch input terminals L 1 , L 2 , two capture input terminals C 1 , C 2 , a test mode input terminal TM, a launch side decoder DEC 1 , a capture side decoder DEC 2 , and a control circuit  110 .  
         [0047]     The delay failure test circuit  101  also includes frequency dividing circuits div 1  to div 3 , selectors S 1  to S 3 , high-speed selection circuits  111  to  113 , an OR circuits  121  to  123 , and gate clock buffers GCB 1  to GCB 3  for the clock domains CD 1  to CD 3 , respectively.  
         [0048]     The clock signal CLK is input to each of the frequency dividing circuits div 1  to div 3  and to each of the selectors S 1  to S 3 . A reset signal R is inverted and input to each of the frequency dividing circuits div 1  to div 3 . A scan mode signal SM is input to each of the selectors S 1  to S 3 . A test mode signal TM is input to the control circuit  110 .  
         [0049]     Launch selection signals L 1 , L 2  from the two launch input terminals L 1 , L 2  are input to the launch side decoder DEC 1  and the control circuit  110 . Capture selection signals C 1 , C 2  from the two capture input terminals C 1 , C 2  are input to the capture side decoder DEC 2  and the control circuit  110 .  
         [0050]     Each of the frequency dividing circuits div 1  to div 3  divides the incoming clock signal CLK. As shown in  FIG. 3 , when the clock signal CLK is a reference clock signal, the clock signal CLK is divided into N frequency divided clocks (N is a real number).  
         [0051]     For example, the frequency dividing circuit div 1  divides the clock signal CLK to generate ⅛ frequency and outputs a frequency-divided clock signal CLK 1  (=⅛ CLK). The frequency dividing circuit div 2  divides the clock signal CLK to generate ¼ frequency and outputs a frequency-divided clock signal CLK 2  (=¼ CLK). The frequency dividing circuit div 3  divides the clock signal CLK to generate ½ frequency and outputs a frequency-divided clock signal CLK 3  (=½ CLK).  
         [0052]     The frequency dividing circuits div 1  to div 3  are connected to the selectors S 1  to S 3  at the subsequent stage, respectively. The frequency-divided clock signals CLK 1  to CLK 3  are input from the frequency dividing circuits div 1  to div 3  at the preceding stage to the selectors S 1  to S 3 , respectively. The clock signal CLK is also input to each of the selectors S 1  to S 3 .  
         [0053]     Each of the selectors S 1  to S 3  selects an output clock signal based on the scan mode signal SM. The frequency-divided clock signals output from the selectors S 1  to S 3  are input to the gate clock buffers GCB 1  to GCB 3 , respectively.  
         [0054]     Specifically, if the scan mode signal SM is input, each of the selectors S 1  to S 3  outputs the clock signal CLK. On the other hand, if the scan mode signal SM is not input, the selectors S 1  to S 3  outputs the frequency-divided clock signal CLK 1  to CLK 3  from the frequency dividing circuits div 1  to div 3  at the preceding stage, respectively.  
         [0055]     The launch side decoder DEC 1  selects a launch side clock. The input of the launch side decoder DEC 1  is connected to the launch input terminals L 1 , L 2 . The launch side decoder DEC 1  includes launch output terminals LO 1  to LO 3  that are provided for the clock domains CD 1  to CD 3  and are connected to the high-speed selection circuits  111  to  113 , respectively.  
         [0056]     The launch side decoder DEC 1  activates a single clock from the launch selection signals L 1 , L 2  input to the launch input terminals L 1 , L 2 . An operation mode table of the launch side decoder DEC 1  is as follows.  
                                                             TABLE 1                                       INPUT       OUTPUT                    L1   L2   LO1   LO2   LO3                       0   0   0   0   0           0   1   1   0   0           1   0   0   1   0           1   1   0   0   1                      
 
         [0057]     For example, if a delay failure is tested for data transfer from the clock domain CD 3  to the clock domain CD 2 , the clock of the clock domain CD 3 , i.e., the launch side (transfer source) is analyzed. To activate the frequency-divided clock signal CLK 3  that is the launch clock, the launch selection signals from the launch input terminals L 1 , L 2  are set such that the launch output terminal LO 3  becomes one (in table  1 , L 1 =1, L 2 =1).  
         [0058]     The capture side decoder DEC 2  selects a capture side clock. The input of the capture side decoder DEC 2  is connected to the capture input terminals C 1 , C 2 . The capture side decoder DEC 2  includes capture output terminals CO 1  to CO 3  that are provided for the clock domains CD 1  to CD 3  and are connected to the high-speed selection circuits  111  to  113 , respectively.  
         [0059]     The capture side decoder DEC 2  activates a single clock from the capture selection signals input to the capture input terminals C 1 , C 2 . An operation mode table of the capture side decoder DEC 2  is as follows.  
                                                             TABLE 2                                       INPUT       OUTPUT                    C1   C2   CO1   CO2   CO3                       0   0   0   0   0           0   1   1   0   0           1   0   0   1   0           1   1   0   0   1                      
 
         [0060]     For example, if a delay failure is tested for data transfer from the clock domain CD 3  to the clock domain CD 2 , the clock of the clock domain CD 2 , i.e., the capture side (transfer destination) is analyzed. To activate the frequency-divided clock signal CLK 2  that is the launch clock, the capture selection signals from the capture input terminals C 1 , C 2  are set such that the capture output terminal CO 2  becomes one (in table  2 , C 1 =1, C 2 =0).  
         [0061]     The control circuit  110  decodes the launch/capture clock from each selection signal from the launch input terminals L 1 , L 2  and the capture input terminals C 1 , C 2  to generate clock signals CK 1  to CK 3  and mask signals EN 1  to EN 3  necessary for the failure detection. The generated clock signals CK 1  to CK 3  are input to the high-speed selection circuits  111  to  113 , respectively. The mask signals EN 1  to EN 3  are input to the OR circuits  121  to  123 , respectively.  
         [0062]     The mask signals EN 1  to EN 3  are signals that mask the frequency-divided clock signals CLK 1  to CLK 3 , respectively. That is, the mask signals EN 1  to EN 3  are signals for masking such that a two-clock pulse is generated in respective clock domains CD 1  to CD 3 .  
         [0063]     Specifically, while the mask signals EN 1  to EN 3  are rising (H-state), the respective frequency-divided clock signals CLK 1  to CLK 3  are masked and the clocks are not generated. On the other hand, while the mask signals EN 1  to EN 3  are falling (L-state), the respective frequency-divided clock signals CLK 1  to CLK 3  are released from the masking and are activated. The following table  3  is an operation mode table of the control circuit  110 .  
                                                                                                                   INPUT       OUTPUT                    L1   L2   C1   C2   EN1, 2, 3   CK1, 2, 3                       0   0   0   0                        0   1   0   1   MODE 3           1   0   0   1   MODE 2           1   1   0   1   MODE 2           0   1   1   0   MODE 1           1   0   1   0   MODE 3           1   1   1   0   MODE 2           0   1   1   1   MODE 1           1   0   1   1   MODE 1           1   1   1   1   MODE 3                      
 
         [0064]     In the above operation mode table, a “MODE 1” is an operation mode when verifying a switching position from a clock domain of a relatively slow clock to a clock domain of a fast clock. As shown in  FIG. 3 , the verification is performed for the switching positions of the clock domain CD 1 →the clock domain CD 2 , the clock domain CD 2 →the clock domain CD 3 , and the clock domain CD 1 →the clock domain CD 3 .  
         [0065]     In the above operation mode table, a “MODE 2” is an operation mode when verifying a switching position from a clock domain of a relatively fast clock to a clock domain of a slow clock. As shown in  FIG. 3 , the verification is performed for the switching positions of the clock domain CD 3 →the clock domain CD 2 , the clock domain CD 2 →the clock in CD 1 , and the clock domain CD 3 →the clock domain CD 1 .  
         [0066]     In the above operation mode table, a “MODE 3” is an operation mode when verifying the same clock domain. As shown in  FIG. 3 , the verification is performed for the clock domain CD 1 →the clock domain CD 1 , the clock domain CD 2 →the clock domain CD 2 , and the clock domain CD 3 →the clock domain CD 3 . Details of MODE 1 to MODE 3 are described later.  
         [0067]     As shown in  FIG. 3 , the high-speed selection circuits  111  to  113  have flip-flops FF 1  to FF 3  and selectors SEL 1  to SEL 3 , respectively. The clock signals CK 1  to CK 3  are input to the flip-flops FF 1  to FF 3 , respectively. The inverting outputs of the flip-flops FF 1  to FF 3  are input to the selectors SEL 1  to SEL 3  and to FF 1  to FF 3 . The reset signal R is inverted and input to the flip-flops FF 1  to FF 3 .  
         [0068]     In this way, the flip-flops FF 1  to FF 3  are toggled by the clock signals CK 1  to CK 3  corresponding to the clock domain CD 1  to CD 3  and generate launch/capture switching signals. The generated launch/capture switching signals switch the launch edge/capture edge active signals LO 1  to LO 3 , CO 1  to CO 3  input to the selectors SEL 1  to SEL 3  at the subsequent stage.  
         [0069]     The selectors SEL 1  to SEL 3  switch the active signals LO 1  to LO 3  of the launch side decoder DEC 1  and the active signals CO 1  to CO 3  of the capture side decoder DEC 2 , respectively, based on the respective launch/capture switching signals from the flip-flops FF 1  to FF 3 . That is, the active signals output from the selectors SEL 1  to SEL 3  are mask signals for generating the clock with the launch/capture switching signals only for the clock domains that need the launch/capture.  
         [0070]     Specifically, to the selector SEL 1 , the active signal LO 1  is input from the launch side decoder DEC 1  and the active signal CO 1  is input from the capture side decoder DEC 2 . One of the input active signals is selected with the launch/capture switching signal from the flip-flop FF 1  and is output to the OR circuit  121  at the subsequent stage.  
         [0071]     For example, if the launch/capture switching signal is “1”, the active signal LO 1  is selected and output to the OR circuit  121 . On the other hand, if the launch/capture switching signal is “0”, the active signal CO 1  is selected and output to the OR circuit  121 .  
         [0072]     To the selector SEL 2 , the active signal LO 2  is input from the launch side decoder DEC 1  and the active signal CO 2  is input from the capture side decoder DEC 2 . One of the input active signals is selected with the launch/capture switching signal from the flip-flop FF 2  and is output to the OR circuit  122  at the subsequent stage.  
         [0073]     For example, if the launch/capture switching signal is “1”, the active signal LO 2  is selected and output to the OR circuit  122 . On the other hand, if the launch/capture switching signal is “0”, the active signal CO 2  is selected and output to the OR circuit  122 .  
         [0074]     To the selector SEL 3 , the active signal LO 3  is input from the launch side decoder DEC 1  and the active signal CO 3  is input from the capture side decoder DEC 2 . One of the input active signals is selected with the launch/capture switching signal from the flip-flop FF 3  and is output to the OR circuit  123  at the subsequent stage.  
         [0075]     For example, if the launch/capture switching signal is “1”, the active signal LO 3  is selected and output to the OR circuit  123 . On the other hand, if the launch/capture switching signal is “0”, the active signal CO 3  is selected and output to the OR circuit  123 .  
         [0076]     Since the clock is provided for each of the clock domains CD 1  to CD 3  at a high speed, the high-speed selection circuits  111  to  113  are difficult to dispose within the control circuit  110  because of the restrictions of the layout. Therefore, the switching to the launch side or the capture side can be performed at speed by embedding the high-speed selection circuits  111  to  113  at the outside of the control circuit  110 , especially, just before the gate clock buffers GCB 1  to GCB 3 .  
         [0077]     To the OR circuits  121  to  123 , the active signals selected by the selectors SEL 1  to SEL 3  are input and the mask signals EN 1  to EN 3  are input from the control circuit  110 . The mask signals EN 1  to EN 3  are output only to the clock domains CD that need the launch edge/capture edge.  
         [0078]     To the gate clock buffers GCB 1  to GCB 3 , the mask signals EN 1  to EN 3  are input from the OR circuits  121  to  123  and the frequency-divided clock signals CLK 1  to CLK 3  are input from the selectors S 1  to S 3 . The clock signals TCK  1  to TCK 3  masked by the mask signals EN 1  to EN 3  are output to the clock domains CD 1  to CD 3 , respectively.  
         [0000]     &lt;Operation of MODE 1&gt; 
         [0079]      FIG. 4  is a timing chart of operation waveforms of MODE 1. The clock signal CK 1  shown in  FIG. 4  is a signal formed by masking the frequency-divided clock signal CLK 1  with the mask signal EN 1 ; the clock signal CK 2  is a signal formed by masking the clock signal CLK 2  with the mask signal EN 2 ; and the clock signal CK 3  is a signal formed by masking the frequency-divided clock signal CLK 3  with the mask signal EN 3 .  
         [0080]     Assuming that edges aligned at the same timing are the launch edges LE (LE 1  to LE 3 ) in the clock signals CK 1  to CK 3 , the capture edges CE (CE 1  to CE 3 ) are the rising edges of the clocks of the next cycle.  
         [0081]      FIGS. 5A  to  5 C are timing charts of waveforms at the time of the verification of the switching in the operation of MODE 1.  FIG. 5A  is waveforms at the time of the verification of the switching from the clock domain CD 1  to the clock domain CD 2  (CD 1 →CD 2 ).  
         [0082]     When verifying this switching, the output terminal LO 1  of the launch side decoder DEC 1  is set to LO 1 =1, and the output terminal CO 2  of the capture side decoder DEC 2  is set to CO 2 =1. The clock signal CLK is input to the clock source CLK in this sate to trigger the start of the delay failure test. In this way, the waveforms of  FIG. 5A  can be acquired.  
         [0083]     That is, because of CO 1 =0, the clock signal TCK 1  of  FIG. 5A  is a clock signal formed by masking the capture side waveform of the clock signal CK 1  shown in  FIG. 4 .  
         [0084]     Because of LO 2 =0, the clock signal TCK 2  of  FIG. 5A  is a clock signal formed by masking the launch side waveform of the clock signal CK 2  shown in  FIG. 4 .  
         [0085]     Because of LO 3 =0 and CO 3 =0, the clock signal TCK 3  of  FIG. 5A  is a clock signal formed by masking the launch side and capture side waveforms of the clock signal CK 3  shown in  FIG. 4 .  
         [0086]     In this way, the launch edge LE 1  is generated in the clock signal TCK 1  that is captured into the clock domain CD 1 , which is the switching source; the capture edge CE 2  is generated in the clock signal TCK 2  that is captured into the clock domain CD 2 , which is the switching destination; and other clocks are hidden.  
         [0087]      FIG. 5B  is waveforms at the time of the verification of the switching from the clock domain CD 1  to the clock domain CD 3  (CD 1 →CD 3 ). When verifying this switching, the output terminal LO 1  of the launch side decoder DEC 1  is set to LO 1 =1, and the output terminal CO 3  of the capture side decoder DEC 2  is set to CO 3 =1. The clock signal CLK is input to the clock source CLK in this sate to trigger the start of the delay failure test. In this way, the waveforms of  FIG. 5B  can be acquired.  
         [0088]     That is, because of CO 1 =0, the clock signal TCK 1  of  FIG. 5B  is a clock signal formed by masking the capture side waveform of the clock signal CK 1  shown in  FIG. 4 .  
         [0089]     Because of LO 2 =0 and CO 2 =0, the clock signal TCK 2  of  FIG. 5B  is a clock signal formed by masking the launch side and capture side waveforms of the clock signal CK 2  shown in  FIG. 4 .  
         [0090]     Because of LO 3 =0, the clock signal TCK 3  of  FIG. 5B  is a clock signal formed by masking the launch side waveform of the clock signal CK 3  shown in  FIG. 4 .  
         [0091]     In this way, the launch edge LE 1  is generated in the clock signal TCK 1  that is captured into the clock domain CD 1 , which is the switching source; the capture edge CE 3  is generated in the clock signal TCK 3  that is captured into the clock domain CD 3 , which is the switching destination; and other clocks are hidden.  
         [0092]      FIG. 5C  is waveforms at the time of the verification of the switching from the clock domain CD 2  to the clock domain CD 3  (CD 2 →CD 3 ). When verifying this switching, the output terminal LO 2  of the launch side decoder DEC 1  is set to LO 2 =1, and the output terminal CO 3  of the capture side decoder DEC 2  is set to CO 3 =1. The clock signal CLK is input to the clock source CLK in this sate to trigger the start of the delay failure test. In this way, the waveforms of  FIG. 5C  can be acquired.  
         [0093]     That is, because of LO 1 =0 and CO 1 =0, the clock signal TCK 1  of  FIG. 5C  is a clock signal formed by masking the launch side and capture side waveforms of the clock signal CK 1  shown in  FIG. 4 .  
         [0094]     Because of CO 2 =0, the clock signal TCK 2  of  FIG. 5C  is a clock signal formed by masking the capture side waveform of the clock signal CK 2  shown in  FIG. 4 .  
         [0095]     Because of LO 3 =0, the clock signal TCK 3  of  FIG. 5C  is a clock signal formed by masking the launch side waveform of the clock signal CK 3  shown in  FIG. 4 .  
         [0096]     In this way, the launch edge LE 2  is generated in the clock signal TCK 2  that is captured into the clock domain CD 2 , which is the switching source; the capture edge CE 3  is generated in the clock signal TCK 3  that is captured into the clock domain CD 3 , which is the switching destination; and other clocks are hidden.  
         [0097]     In this way, when switching from a clock domain of a relatively slow clock to a clock domain of a fast clock in MODE 1, the launch edge is generated in the clock signal captured into the clock domain CD that is the switching source; the capture edge is generated in the clock signal captured into the clock domain CD that is the switching destination; and other clocks are hidden. Therefore, the combination of the launch edge LE and the capture edge CE necessary for the switching verification can be activated in a one-on-one relationship.  
         [0000]     &lt;Operation of MODE 2&gt; 
         [0098]      FIG. 6  is a timing chart of operation waveforms of MODE 2. The clock signal CK 1  shown in  FIG. 6  is a signal formed by masking the frequency-divided clock signal CLK 1  with the mask signal EN 1 ; the clock signal CK 2  is a signal formed by masking the frequency-divided clock signal CLK 2  with the mask signal EN 2 ; and the clock signal CK 3  is a signal formed by masking the frequency-divided clock signal CLK 3  with the mask signal EN 3 .  
         [0099]     Assuming that edges aligned at the same timing are the capture edges CE (CE 1  to CE 3 ) in the clock signals CK 1  to CK 3 , the launch edges LE (LE 1  to LE 3 ) are the rising edges of the clocks of the previous cycle.  
         [0100]      FIGS. 7A  to  7 C are timing charts of waveforms at the time of the verification of the switching in the operation of MODE 2.  FIG. 7A  is waveforms at the time of the verification of the switching from the clock domain CD 3  to the clock domain CD 1  (CD 3 →CD 1 ).  
         [0101]     When verifying this switching, the output terminal LO 3  of the launch side decoder DEC 1  is set to LO 3 =1, and the output terminal CO 1  of the capture side decoder DEC 2  is set to CO 1 =1. The clock signal CLK is input to the clock source CLK in this sate to trigger the start of the delay failure test. In this way, the waveforms of  FIG. 7A  can be acquired.  
         [0102]     That is, because of LO 1 =0, the clock signal TCK 1  of  FIG. 7A  is a clock signal formed by masking the launch side waveform of the clock signal CK 1  shown in  FIG. 6 .  
         [0103]     Because of LO 2 =0 and CO 2 =0, the clock signal TCK 2  of  FIG. 7A  is a clock signal formed by masking the launch side and capture side waveforms of the clock signal CK 2  shown in  FIG. 6 .  
         [0104]     Because of CO 3 =0, the clock signal TCK 3  of  FIG. 7A  is a clock signal formed by masking the capture side waveform of the clock signal CK 3  shown in  FIG. 6 .  
         [0105]     In this way, the launch edge LE 3  is generated in the clock signal TCK 3  that is captured into the clock domain CD 3 , which is the switching source; the capture edge CE 1  is generated in the clock signal TCK 1  that is captured into the clock domain CD 1 , which is the switching destination; and other clocks are hidden.  
         [0106]     In  FIGS. 7A  to  7 C,  FIG. 7B  is waveforms at the time of the verification of the switching from the clock domain CD 2  to the clock domain CD 1  (CD 2 →CD 1 ). When verifying this switching, the output terminal LO 2  of the launch side decoder DEC 1  is set to LO 2 =1, and the output terminal CO 1  of the capture side decoder DEC 2  is set to CO 1 =1. The clock signal CLK is input to the clock source CLK in this sate to trigger the start of the delay failure test. In this way, the waveforms of  FIG. 7B  can be acquired.  
         [0107]     That is, because of LO 1 =0, the clock signal TCK 1  of  FIG. 7B  is a clock signal formed by masking the launch side waveform of the clock signal CK 1  shown in  FIG. 6 .  
         [0108]     Because of CO 2 =0, the clock signal TCK 2  of  FIG. 7B  is a clock signal formed by masking the capture side waveform of the clock signal CK 2  shown in  FIG. 6 .  
         [0109]     Because of LO 3 =0 and CO 3 =0, the clock signal TCK 3  of  FIG. 5B  is a clock signal formed by masking the launch side and capture side waveforms of the clock signal CK 3  shown in  FIG. 6 .  
         [0110]     In this way, the launch edge LE 2  is generated in the clock signal TCK 2  that is captured into the clock domain CD 2 , which is the switching source; the capture edge CE 1  is generated in the clock signal TCK 1  that is captured into the clock domain CD 1 , which is the switching destination; and other clocks are hidden.  
         [0111]      FIG. 7C  is waveforms at the time of the verification of the switching from the clock domain CD 3  to the clock domain CD 2  (CD 3 →CD 2 ). When verifying this switching, the output terminal LO 3  of the launch side decoder DEC 1  is set to LO 3 =1, and the output terminal CO 2  of the capture side decoder DEC 2  is set to CO 2 =1. The clock signal CLK is input to the clock source CLK in this sate to trigger the start of the delay failure test. In this way, the waveforms of  FIG. 7C  can be acquired.  
         [0112]     That is, because of LO 1 =0 and CO 1 =0, the clock signal TCK 1  of  FIG. 7C  is a clock signal formed by masking the launch side and capture side waveforms of the clock signal CK 1  shown in  FIG. 6 .  
         [0113]     Because of LO 2 =0, the clock signal TCK 2  of  FIG. 7C  is a clock signal formed by masking the launch side waveform of the clock signal CK 2  shown in  FIG. 6 .  
         [0114]     Because of CO 3 =0, the clock signal TCK 3  of  FIG. 7C  is a clock signal formed by masking the capture side waveform of the clock signal CK 3  shown in  FIG. 6 .  
         [0115]     In this way, the launch edge LE 3  is generated in the clock signal TCK 3  that is captured into the clock domain CD 3 , which is the switching source; the capture edge CE 2  is generated in the clock signal TCK 2  that is captured into the clock domain CD 2 , which is the switching destination; and other clocks are hidden.  
         [0116]     In this way, when switching from a clock domain of a relatively fast clock to a clock domain of a slow clock in MODE 2, the launch edge LE is generated in the clock signal captured into the clock domain CD that is the switching source; the capture edge CE is generated in the clock signal captured into the clock domain CD that is the switching destination; and other clocks are hidden. Therefore, the combination of the launch edge LE and the capture edge CE necessary for the switching verification can be activated in a one-on-one relationship.  
         [0000]     &lt;Operation of MODE 3&gt; 
         [0117]     The operation waveforms of MODE 1 (see  FIG. 4 ) or the operation waveforms of MODE 2 (see  FIG. 6 ) may be used for the operation waveforms of MODE 3. In this description, the operation waveforms of MODE 2 shown in  FIG. 6  are used.  
         [0118]      FIGS. 8A  to  8 C are timing charts of waveforms at the time of the verification in the operation of MODE 3.  FIG. 8A  is waveforms at the time of the same-domain verification from the clock domain CD 3  to the clock domain CD 3  (CD 3 →CD 3 ).  
         [0119]     In the case of the same-domain verification, the output terminal LO 3  of the launch side decoder DEC 1  is set to LO 3 =1, and the output terminal CO 3  of the capture side decoder DEC 2  is set to CO 3 =1. The clock signal CLK is input to the clock source CLK in this sate to trigger the start of the delay failure test. In this way, the waveforms of  FIG. 8A  can be acquired.  
         [0120]     That is, because of LO 1 =0 and CO 1 =0, the clock signal TCK 1  of  FIG. 8A  is a clock signal formed by masking the launch side and capture side waveforms of the clock signal CK 1  shown in  FIG. 6 .  
         [0121]     Because of LO 2 =0 and CO 2 =0, the clock signal TCK 2  of  FIG. 8A  is a clock signal formed by masking the launch side and capture side waveforms of the clock signal CK 2  shown in  FIG. 6 .  
         [0122]     Because of LO 3 =1 and CO 3 =1, the clock signal TCK 3  of  FIG. 8A  is a clock signal formed without masking either the launch side or capture side waveforms of the clock signal CK 3  shown in  FIG. 6 .  
         [0123]     In this way, the launch edge LE 3  is generated in the clock signal TCK 3  that is captured into the clock domain CD 3 , which is the switching source; the capture edge CE 3  is generated in the clock signal TCK 3  that is captured into the clock domain CD 3 , which is the switching destination; and other clocks are hidden.  
         [0124]     In  FIGS. 8A  to  8 C,  FIG. 8B  is waveforms at the time of the verification of the switching from the clock domain CD 2  to the clock domain CD 2  (CD 2 →CD 2 ). When verifying this switching, the output terminal LO 2  of the launch side decoder DEC 1  is set to LO 2 =1, and the output terminal CO 2  of the capture side decoder DEC 2  is set to CO 2 =1. The clock signal CLK is input to the clock source CLK in this sate to trigger the start of the delay failure test. In this way, the waveforms of  FIG. 8B  can be acquired.  
         [0125]     That is, because of LO 1 =0 and CO 1 =0, the clock signal TCK 1  of  FIG. 8B  is a clock signal formed by masking the launch side and capture side waveforms of the clock signal CK 1  shown in  FIG. 6 .  
         [0126]     Because of LO 2 =1 and CO 2 =1, the clock signal TCK 2  of  FIG. 8B  is a clock signal formed without masking either the launch side or capture side waveforms of the clock signal CK 2  shown in  FIG. 6 .  
         [0127]     Because of LO 3 =0 and CO 3 =0, the clock signal TCK 3  of  FIG. 8B  is a clock signal formed by masking the launch side and capture side waveforms of the clock signal CK 3  shown in  FIG. 6 .  
         [0128]     In this way, the launch edge LE 2  is generated in the clock signal TCK 2  that is captured into the clock domain CD 2 , which is the switching source; the capture edge CE 2  is generated in the clock signal TCK 2  that is captured into the clock domain CD 2 , which is the switching destination; and other clocks are hidden.  
         [0129]      FIG. 8C  is waveforms at the time of the verification of the switching from the clock domain CD 1  to the clock domain CD 1  (CD 1 →CD 1 ). When verifying this switching, the output terminal LO 1  of the launch side decoder DEC 1  is set to LO 1 =1, and the output terminal CO 1  of the capture side decoder DEC 2  is set to CO 1 =1. The clock signal CLK is input to the clock source CLK in this sate to trigger the start of the delay failure test. In this way, the waveforms of  FIG. 8C  can be acquired.  
         [0130]     That is, because of LO 1 =1 and CO 1 =1, the clock signal TCK 1  of  FIG. 8C  is a clock signal formed without masking either the launch side or capture side waveforms of the clock signal CK 1  shown in  FIG. 6 .  
         [0131]     Because of LO 2 =0 and CO 2 =0, the clock signal TCK 2  of  FIG. 8C  is a clock signal formed by masking the launch side and capture side waveforms of the clock signal CK 2  shown in  FIG. 6 .  
         [0132]     Because of LO 3 =0 and CO 3 =0, the clock signal TCK 3  of  FIG. 8C  is a clock signal formed by masking the launch side and capture side waveforms of the clock signal CK 3  shown in  FIG. 6 .  
         [0133]     In this way, the launch edge LE 1  is generated in the clock signal TCK 1  that is captured into the clock domain CD 1 , which is the switching source; the capture edge CE 1  is generated in the clock signal TCK 1  that is captured into the clock domain CD 1 , which is the switching destination; and other clocks are hidden.  
         [0134]     In MODE 3, the launch edge LE and the capture edge CE are generated in the clock signals captured into the same clock domain CD and other clocks are hidden. Therefore, the combination of the launch edge LE and the capture edge CE necessary for the verification of the same clock domain can be activated in a one-on-one relationship. The launch edges LE or capture edges CE may be used, provided the timing is not affected.  
         [0135]     A second embodiment shows an example of applying a skewed load mode to the first embodiment. In the skewed load mode, when the delay failure test is performed, a clock signal for the scan shift is used as the launch edge.  
         [0136]      FIG. 9  is a circuit diagram of LSI including a delay failure test circuit according to the second embodiment. In  FIG. 9 , LSI  700  is a tested circuit that includes plural (in the example shown in  FIG. 9 , three) clock domains CD (CD 1  to CD 3 ) and a delay failure test circuit  701  that detects failures of the clock domains CD (CD 1  to CD 3 ).  
         [0137]     Since the delay failure test circuit  701  has the almost same circuit configuration as the delay failure test circuit  101  shown in the first embodiment, the same characters are added to the same components and the description thereof is omitted. Since various operations are the same as the contents shown in tables  1  to  3  described above, the description thereof is omitted.  
         [0138]     The control circuit  710  includes, in addition to each component of the control circuit  110  shown in  FIG. 3 , a skewed load input terminal SL and scan enable output terminals SE 1  to SE 3  which are provided for the clock domains CD 1  to CD 3 , respectively.  
         [0139]     In the skewed load mode, only for a scan flip-flop (not shown) within a clock domain CDi where a launch edge LEi (i=1 to 3) is input into, a scan enable signal SEi is changed in accordance with the launch edge LEi.  
         [0140]     A scan enable signal SEj input to the scan flip-flop (not shown) of another clock domain CDj (j≠i) always has a polarity that constrains the shift while the clock is at a high speed (e.g., 400 [GHz]).  
         [0141]     Specifically, the number of times of the scan shift is increased by one for the clock domain CDi where the launch edge LEi is input into. In this way, the last clock of the scan shift can be used as the launch edge LEi and the scan shift can be made in common with the launch.  
         [0142]     In this case, the last edge of the scan shift is made close to the capture edge. Hereinafter, the operations of MODE 1 to MODE 3 shown in table  3  in the second embodiment will be described.  
         [0000]     &lt;Operation of MODE 1&gt; 
         [0143]     The operation waveforms of MODE 1 are the same as the operation waveforms shown in  FIG. 4  and will not be described.  
         [0144]      FIGS. 10A  to  10 C are timing charts of waveforms at the time of the verification of the switching in the operation of MODE 1.  FIG. 10A  is waveforms at the time of the verification of the switching from the clock domain CD 1  to the clock domain CD 2  (CD 1 →CD 2 ).  
         [0145]     When verifying this switching, the output terminal LO 1  of the launch side decoder DEC 1  is set to LO 1 =1, and the output terminal CO 2  of the capture side decoder DEC 2  is set to CO 2 =1. The clock signal CLK is input to the clock source CLK in this sate at the time of the scan mode to trigger the start of the delay failure test. In this way, the waveforms shown in  FIG. 10A  can be acquired from the clock signals CK 1  to CK 3  shown in  FIG. 4 .  
         [0146]     That is, because of LO 1 =1 in  FIG. 10A , the scan enable signal SE 1  becomes the H-state. An edge defined by the last clock of the scan mode becomes the launch edge LE 1 , and the scan enable signal SE 1  is changed from the H-state to the L-state by detecting this launch edge LE 1 . Since the mask signal EN 1  is activated while the scan enable signal SE 1  is in the L-state, the clocks are masked except the launch edge LE 1  of the clock signal TCK 1 .  
         [0147]     Because of LO 2 =0 and LO 3 =0, the scan enable signals SE 2 , SE 3  become the L-state. Therefore, the launch edges LE 2 , LE 3  are not detected from the clock signals TCK 2 , TCK 3 . The mask process same as the first embodiment is performed for masking the capture edges CE.  
         [0148]     In this way, the launch edge LE 1  is generated in the clock signal CK 1  that is captured into the clock domain CD 1 , which is the switching source; the capture edge CE 2  is generated in the clock signal CK 2  that is captured into the clock domain CD 2 , which is the switching destination; and other clocks are hidden.  
         [0149]      FIG. 10B  is waveforms at the time of the verification of the switching from the clock domain CD 1  to the clock domain CD 3  (CD 1 →CD 3 ).  
         [0150]     When verifying this switching, the output terminal LO 1  of the launch side decoder DEC 1  is set to LO 1 =1, and the output terminal CO 3  of the capture side decoder DEC 2  is set to CO 3 =1. The clock signal CLK is input to the clock source CLK in this sate at the time of the scan mode to trigger the start of the delay failure test. In this way, the waveforms shown in  FIG. 10B  can be acquired from the clock signals CK 1  to CK 3  shown in  FIG. 4 .  
         [0151]     That is, because of LO 1 =1 in  FIG. 10B , the scan enable signal SE 1  becomes the H-state. An edge defined by the last clock of the scan mode becomes the launch edge LE 1 , and the scan enable signal SE 1  is changed from the H-state to the L-state by detecting this launch edge LE 1 . Since the mask signal EN 1  is activated while the scan enable signal SE 1  is in the L-state, the clocks are masked except the launch edge LE 1  of the clock signal TCK 1 .  
         [0152]     Because of LO 2 =0 and LO 3 =0, the scan enable signals SE 2 , SE 3  become the L-state. Therefore, the launch edges LE 2 , LE 3  are not detected from the clock signals TCK 2 , TCK 3 . The mask process same as the first embodiment is performed for masking the capture edges CE.  
         [0153]     In this way, the launch edge LE 1  is generated in the clock signal TCK 1  that is captured into the clock domain CD 1 , which is the switching source; the capture edge CE 3  is generated in the clock signal TCK 3  that is captured into the clock domain CD 3 , which is the switching destination; and other clocks are hidden.  
         [0154]      FIG. 10C  is waveforms at the time of the verification of the switching from the clock domain CD 2  to the clock domain CD 3  (CD 2 →CD 3 ).  
         [0155]     When verifying this switching, the output terminal LO 2  of the launch side decoder DEC 1  is set to LO 2 =1, and the output terminal CO 3  of the capture side decoder DEC 2  is set to CO 3 =1. The clock signal CLK is input to the clock source CLK in this sate at the time of the scan mode to trigger the start of the delay failure test. In this way, the waveforms shown in  FIG. 10C  can be acquired from the clock signals TCK 1  to TCK 3  shown in  FIG. 4 .  
         [0156]     That is, because of LO 2 =1 in  FIG. 10C , the scan enable signal SE 2  becomes the H-state. An edge defined by the last clock of the scan mode becomes the launch edge LE 1 , and the scan enable signal SE 2  is changed from the H-state to the L-state by detecting this launch edge LE 2 . Since the mask signal EN 2  is activated while the scan enable signal SE 2  is in the L-state, the clocks are masked except the launch edge LE 2  of the clock signal TCK 2 .  
         [0157]     Because of LO 1 =0 and LO 3 =0, the scan enable signals SE 1 , SE 3  become the L-state. Therefore, the launch edges LE 1 , LE 3  are not detected from the clock signals TCK 1 , TCK 3 . The mask process same as the first embodiment is performed for masking the capture edges CE.  
         [0158]     In this way, the launch edge LE 2  is generated in the clock signal TCK 2  that is captured into the clock domain CD 2 , which is the switching source; the capture edge CE 3  is generated in the clock signal TCK 3  that is captured into the clock domain CD 3 , which is the switching destination; and other clocks are hidden.  
         [0159]     In this way, when switching from a clock domain of a relatively slow clock to a clock domain of a fast clock in MODE 1, the launch edge is generated in the clock signal captured into the clock domain CD that is the switching source; the capture edge is generated in the clock signal captured into the clock domain CD that is the switching destination; and other clocks are hidden.  
         [0160]     Therefore, the combination of the launch edge LE and the capture edge CE necessary for the switching verification can be activated in a one-on-one relationship. Consequently, the skewed load mode can be applied to the failure detection without considerably changing the circuit configuration.  
         [0000]     &lt;Operation of MODE 2&gt; 
         [0161]     The operation waveforms of MODE 2 are the same as the operation waveforms shown in  FIG. 6  and will not be described.  
         [0162]      FIGS. 11A  to  11 C are timing charts of waveforms at the time of the verification of the switching in the operation of MODE 2.  FIG. 11A  is waveforms at the time of the verification of the switching from the clock domain CD 2  to the clock domain CD 1  (CD 2 →CD 1 ).  
         [0163]     When verifying this switching, the output terminal LO 2  of the launch side decoder DEC 1  is set to LO 2 =1, and the output terminal CO 1  of the capture side decoder DEC 2  is set to CO 1 =1. The clock signal CLK is input to the clock source CLK in this sate at the time of the scan mode to trigger the start of the delay failure test. In this way, the waveforms shown in  FIG. 11A  can be acquired from the clock signals TCK 1  to TCK 3  shown in  FIG. 6 .  
         [0164]     That is, because of LO 2 =1 in  FIG. 11A , the scan enable signal SE 2  becomes the H-state. An edge defined by the last clock of the scan mode becomes the launch edge LE 2 , and the scan enable signal SE 2  is changed from the H-state to the L-state by detecting this launch edge LE 2 . Since the mask signal EN 2  is activated while the scan enable signal SE 2  is in the L-state, the clocks are masked except the launch edge LE 2  of the clock signal TCK 2 .  
         [0165]     Because of LO 1 =0 and LO 3 =0, the scan enable signals SE 1 , SE 3  become the L-state. Therefore, the launch edges LE 1 , LE 3  are not detected from the clock signals TCK 1 , TCK 3 . The mask process same as the first embodiment is performed for masking the capture edges CE.  
         [0166]     In this way, the launch edge LE 2  is generated in the clock signal TCK 2  that is captured into the clock domain CD 2 , which is the switching source; the capture edge CE 1  is generated in the clock signal TCK 1  that is captured into the clock domain CD 1 , which is the switching destination; and other clocks are hidden.  
         [0167]      FIG. 11B  is waveforms at the time of the verification of the switching from the clock domain CD 3  to the clock domain CD 2  (CD 3 →CD 2 ).  
         [0168]     When verifying this switching, the output terminal LO 3  of the launch side decoder DEC 1  is set to LO 3 =1, and the output terminal CO 2  of the capture side decoder DEC 2  is set to CO 2 =1. The clock signal CLK is input to the clock source CLK in this sate at the time of the scan mode to trigger the start of the delay failure test. In this way, the waveforms shown in  FIG. 11B  can be acquired from the clock signals TCK 1  to TCK 3  shown in  FIG. 6 .  
         [0169]     That is, because of LO 3 =1 in  FIG. 11B , the scan enable signal SE 3  becomes the H-state. An edge defined by the last clock of the scan mode becomes the launch edge LE 3 , and the scan enable signal SE 3  is changed from the H-state to the L-state by detecting this launch edge LE 3 . Since the mask signal EN 3  is activated while the scan enable signal SE 3  is in the L-state, the clocks are masked except the launch edge LE 3  of the clock signal TCK 3 .  
         [0170]     Because of LO 2 =0 and LO 1 =0, the scan enable signals SE 1 , SE 2  become the L-state. Therefore, the launch edges LE 1 , LE 2  are not detected from the clock signals TCK 1 , TCK 2 . The mask process same as the first embodiment is performed for masking the capture edges CE.  
         [0171]     In this way, the launch edge LE 3  is generated in the clock signal TCK 3  that is captured into the clock domain CD 3 , which is the switching source; the capture edge CE 2  is generated in the clock signal TCK 2  that is captured into the clock domain CD 2 , which is the switching destination; and other clocks are hidden.  
         [0172]      FIG. 11C  is waveforms at the time of the verification of the switching from the clock domain CD 3  to the clock domain CD 1  (CD 3 →CD 1 ).  
         [0173]     When verifying this switching, the output terminal LO 3  of the launch side decoder DEC 1  is set to LO 3 =1, and the output terminal CO 1  of the capture side decoder DEC 2  is set to CO 1 =1. The clock signal CLK is input to the clock source CLK in this sate at the time of the scan mode to trigger the start of the delay failure test. In this way, the waveforms shown in  FIG. 11C  can be acquired from the clock signals TCK 1  to TCK 3  shown in  FIG. 6 .  
         [0174]     That is, because of LO 3 =1 shown in  FIG. 11C , the scan enable signal SE 3  becomes the H-state. An edge defined by the last clock of the scan mode becomes the launch edge LE 3 , and the scan enable signal SE 3  is changed from the H-state to the L-state by detecting this launch edge LE 3 . Since the mask signal EN 3  is activated while the scan enable signal SE 3  is in the L-state, the clocks are masked except the launch edge LE 3  of the clock signal TCK 3 .  
         [0175]     Because of LO 1 =0 and LO 2 =0, the scan enable signals SE 1 , SE 2  become the L-state. Therefore, the launch edges LE 1 , LE 2  are not detected from the clock signals TCK 1 , TCK 2 . The mask process same as the first embodiment is performed for masking the capture edges CE.  
         [0176]     In this way, the launch edge LE 3  is generated in the clock signal TCK 3  that is captured into the clock domain CD 3 , which is the switching source; the capture edge CE 1  is generated in the clock signal TCK 1  that is captured into the clock domain CD 1 , which is the switching destination; and other clocks are hidden.  
         [0177]     In this way, when switching from a clock domain of a relatively fast clock to a clock domain of a slow clock in MODE 2, the launch edge LE is generated in the clock signal captured into the clock domain CD that is the switching source; the capture edge CE is generated in the clock signal captured into the clock domain CD that is the switching destination; and other clocks are hidden.  
         [0178]     Therefore, the combination of the launch edge LE and the capture edge CE necessary for the switching verification can be activated in a one-on-one relationship. Consequently, the skewed load mode can be applied to the failure detection without considerably changing the circuit configuration.  
         [0000]     &lt;Operation of MODE 3&gt; 
         [0179]     The operation waveforms of MODE 3 are the same as the operation waveforms shown in  FIG. 6  and will not be described.  
         [0180]      FIGS. 12A  to  12 C are timing charts of waveforms at the time of the verification in the operation of MODE 3.  FIG. 12A  is waveforms at the time of the same-domain verification from the clock domain CD 3  to the clock domain CD 3  (CD 3 →CD 3 ).  
         [0181]     In the case of the same-domain verification, the output terminal LO 3  of the launch side decoder DEC 1  is set to LO 3 =1, and the output terminal CO 3  of the capture side decoder DEC 2  is set to CO 3 =1. The clock signal CLK is input to the clock source CLK in this sate at the time of the scan mode to trigger the start of the delay failure test. In this way, the waveforms shown in  FIG. 12A  can be acquired from the clock signals TCK 1  to TCK 3  shown in  FIG. 6 .  
         [0182]     That is, because of LO 3 =1 in  FIG. 12A , the scan enable signal SE 3  becomes the H-state. An edge defined by the last clock of the scan mode becomes the launch edge LE 3 , and the scan enable signal SE 3  is changed from the H-state to the L-state by detecting this launch edge LE 3 . Since the mask signal EN 3  is activated while the scan enable signal SE 3  is in the L-state, the clocks are masked except the launch edge LE 3  of the clock signal TCK 3 .  
         [0183]     Because of LO 1 =0 and LO 2 =0, the scan enable signals SE 1 , SE 2  become the L-state. Therefore, the launch edges LE 1 , LE 2  are not detected from the clock signals TCK 1 , TCK 2 . The mask process same as the first embodiment is performed for masking the capture edges CE.  
         [0184]     In this way, the launch edge LE 3  is generated in the clock signal TCK 3  that is captured into the clock domain CD 3 , which is the switching source; the capture edge CE 3  is generated in the clock signal TCK 3  that is captured into the clock domain CD 3 , which is the switching destination; and other clocks are hidden.  
         [0185]      FIG. 12B  is waveforms at the time of the same-domain verification from the clock domain CD 2  to the clock domain CD 2  (CD 2 →CD 2 ).  
         [0186]     In the case of the same-domain verification, the output terminal LO 2  of the launch side decoder DEC 1  is set to LO 2 =1, and the output terminal CO 2  of the capture side decoder DEC 2  is set to CO 2 =1. The clock signal CLK is input to the clock source CLK in this sate at the time of the scan mode to trigger the start of the delay failure test. In this way, the waveforms shown in  FIG. 12B  can be acquired from the clock signals TCK 1  to TCK 3  shown in  FIG. 6 .  
         [0187]     That is, because of LO 2 =1 in  FIG. 12B , the scan enable signal SE 2  becomes the H-state. An edge defined by the last clock of the scan mode becomes the launch edge LE 2 , and the scan enable signal SE 2  is changed from the H-state to the L-state by detecting this launch edge LE 2 . Since the mask signal EN 2  is activated while the scan enable signal SE 2  is in the L-state, the clocks are masked except the launch edge LE 2  of the clock signal TCK 2 .  
         [0188]     Because of L 1 =0 and LO 3 =0, the scan enable signals SE 1 , SE 3  become the L-state. Therefore, the launch edges LE 1 , LE 3  are not detected from the clock signals TCK 1 , TCK 3 . The mask process same as the first embodiment is performed for masking the capture edges CE.  
         [0189]     In this way, the launch edge LE 2  is generated in the clock signal TCK 2  that is captured into the clock domain CD 2 , which is the switching source; the capture edge CE 2  is generated in the clock signal TCK 2  that is captured into the clock domain CD 2 , which is the switching destination; and other clocks are hidden.  
         [0190]      FIG. 12C  is waveforms at the time of the same-domain verification from the clock domain CD 1  to the clock domain CD 1  (CD 1 →CD 1 ).  
         [0191]     In the case of the same-domain verification, the output terminal LO 1  of the launch side decoder DEC 1  is set to LO 1 =1, and the output terminal CO 1  of the capture side decoder DEC 2  is set to CO 1 =1. The clock signal CLK is input to the clock source CLK in this sate at the time of the scan mode to trigger the start of the delay failure test. In this way, the waveforms shown in  FIG. 12C  can be acquired from the clock signals TCK 1  to TCK 3  shown in  FIG. 6 .  
         [0192]     That is, because of LO 1 =1 in  FIG. 12C , the scan enable signal SE 1  becomes the H-state. An edge defined by the last clock of the scan mode becomes the launch edge LE 1 , and the scan enable signal SE 1  is changed from the H-state to the L-state by detecting this launch edge LE 1 . Since the mask signal EN 1  is activated while the scan enable signal SE 1  is in the L-state, the clocks are masked except the launch edge LE 1  of the clock signal TCK 1 .  
         [0193]     Because of LO 2 =0 and LO 3 =0, the scan enable signals SE 2 , SE 3  become the L-state. Therefore, the launch edges LE 2 , LE 3  are not detected from the clock signals TCK 2 , TCK 3 . The mask process same as the first embodiment is performed for masking the capture edges CE.  
         [0194]     In this way, the launch edge LE 1  is generated in the clock signal TCK 1  that is captured into the clock domain CD 1 , which is the switching source; the capture edge CE 1  is generated in the clock signal TCK 1  that is captured into the clock domain CD 1 , which is the switching destination; and other clocks are hidden.  
         [0195]     In MODE 3, the launch edge LE and the capture edge CE are generated in the clock signals captured into the same clock domain CD and other clocks are hidden.  
         [0196]     Therefore, the combination of the launch edge LE and the capture edge CE necessary for the verification of the same clock domain can be activated in a one-on-one relationship. Consequently, the skewed load mode can be applied to the failure detection without considerably changing the circuit configuration.  
         [0197]     As described above, the delay failure test circuit can generate the launch edge and the capture edge only for the clock domains CD that are the targets of the delay failure test by masking clocks of clock domains other than the clock domains that are the targets of the delay failure test. Therefore, the launch edge can be correlated one-on-one with the capture edge. The launch edges LE or capture edges CE may be used, provided the timing is not affected.  
         [0198]     In this way, the quality of LSI can be improved by facilitating the generation of the test pattern between the clock domains CD and improving the detection rate of the delay failure between the clock domains CD.  
         [0199]     The present invention can be achieved without changing the clock configuration of the tested circuit (LSI  100 ,  700 ). Therefore, the present invention is also useful for the automatic insertion of the delay failure test circuit with a tool.  
         [0200]     According to the embodiments described above, quality of LSI can be improved.  
         [0201]     Although the invention has been described with respect to a specific embodiment for a complete and clear disclosure, the appended claims are not to be thus limited but are to be construed as embodying all modifications and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.