Abstract:
A plasma damage protection circuit includes a word line driver circuit with plasma damage protection features. If, during manufacture, plasma-based processes cause charge to build up on the word lines, the charge passes from the word lines through at least the word line drivers to the semiconductor substrate. Another plasma-based protection circuit includes a device coupled to multiple word line drivers. If, during manufacture, plasma-based processes cause charge to build up on the word lines, the charge passes from the word lines through at least the device to the semiconductor substrate. Thus, these plasma-based protection circuits save space while protecting the integrated circuit from plasma process-based damage.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to integrated circuit devices, and more particularly to devices for protection of integrated circuits from plasma damage during manufacture. 
   2. Description of Related Art 
   The subject of protecting integrated circuits from plasma damage has received much attention from circuit designers interested in protecting device gates. In the manufacturing of integrated circuits, the processes include plasma treatments. For example, backend processing, such as metal etching, photoresist stripping, and deposition of dielectrics, involves plasma which induces charge on the structures being treated. The plasma-induced charge damages underlying structures in the device, including structures critical to device performance. For example, tunnel dielectrics used in flash memory and gate dielectrics are damaged by plasma-induced charge. Furthermore, the charge storage structures utilized in SONOS, N-bit memory (charge trapping memory cell that can trap 
   charge at different positions of the charge trapping structure), and PHINES are particularly susceptible to damage by plasma-based processes. 
   The plasma-induced charge may be either positive or negative, and different types of damage can occur based on the type of plasma-induced charge. 
   In prior art semiconductor memory integrated circuits, each word line driver  101  is combined with its own protection circuit distinct from the word line driver  101 , such as the CMOS transistor pair  102  shown in  FIG. 1 . The word line driver  101  provides different operation voltages to a word line  106  in the course of memory operations. The CMOS transistor pair  102 , including PMOS  103  and NMOS  105 , passes plasma-induced charge to the semiconductor substrate. The positive charge is passed through PMOS  103  and the negative charge is passed through NMOS  105 . Each word line of the word line driver has its own protection circuit, such as a CMOS transistor pair. However, this design occupies a great deal of chip space and reduces the circuit density. This plasma protection circuit design presents an obstacle to the continued miniaturization of integrated circuit dimensions. 
   SUMMARY OF THE INVENTION 
   In one aspect of the invention, an integrated circuit comprises a semiconductor substrate, a memory array coupled to the substrate, word lines coupled to the memory substrate, and word line drivers. Each word line driver is coupled to the semiconductor substrate and at least one word line. The manufacturing process involves plasma-based processes which cause charge build up on word lines. If, during manufacture, charge builds up on a word line, the charge passes from the word line through a word line driver to the semiconductor substrate. 
   In another aspect of the invention, an integrated circuit comprises a semiconductor substrate, a memory array coupled to the substrate, word lines coupled to the memory substrate, word line drivers, and a device coupled to the word line drivers. For example, the device is a transistor with a gate that floats during plasma-based process manufacturing. If, during manufacture, charge builds up on word lines, the charge passes from the word lines through the device to the semiconductor substrate. 
   In one aspect of the invention, an integrated circuit comprises a semiconductor substrate, a memory array coupled to the substrate, word lines coupled to the memory substrate, word line drivers, and a device coupled to the word line drivers. Each word line driver is coupled to the semiconductor substrate and at least one word line. If, during manufacture, charge builds up on the word line, the charge passes from the word line to the semiconductor substrate. The charge passes through the device and/or a word line driver. 
   Another aspect of the invention is a method for manufacturing an integrated circuit device. A semiconductor substrate is provided. A memory array coupled to the semiconductor substrate is formed. Word lines coupled to the memory array are formed. 
   Word line drivers coupled to the word lines are formed. If, during manufacture, charge builds up on the word lines, charge is passed from the word lines through at least the word line drivers to the semiconductor substrate. 
   Another aspect of the invention is a method for manufacturing an integrated circuit device. A semiconductor substrate is provided. A memory array coupled to the semiconductor substrate is formed. Word lines coupled to the memory array are formed. 
   Word line drivers coupled to the word lines are formed. A device coupled to the word line drivers is formed. If, during manufacture, charge builds up on the word lines, charge is passed from the word lines through at least the device to the semiconductor substrate. 
   Yet another aspect of the invention is a method for manufacturing an integrated circuit device. A semiconductor substrate is provided. A memory array coupled to the semiconductor substrate is formed. Word lines coupled to the memory array are formed. 
   Word line drivers coupled to the word lines are formed. A device coupled to the word line drivers is formed. If, during manufacture, charge builds up on the word lines, charge is passed from the word lines to the semiconductor substrate. Some of the charge passes through at least the device. Some of the charge passes through the word line drivers. 
   In some embodiments, each word line driver includes a device coupled to the semiconductor substrate and the word line, such as a transistor, through which the charge passes on the way from the word line to the semiconductor substrate. By using one of the transistors of the word line driver, space is saved on the integrated circuit. For example, in the course of regular operation, the transistor couples a supply voltage to the word line during a memory operation. The transistor is of a certain charge type and passes charge of the same charge type. For example, holes building up on a word line pass from the word line through at least a p-type transistor in the word line driver to the semiconductor substrate, and electrons building up on a word line pass from the word line through at least an n-type transistor in the word line driver to the semiconductor substrate. In one embodiment, the transistor is formed in a well coupled to the semiconductor substrate. A current carrying terminal of the transistor, such as a source or drain, is coupled to the word line. 
   In some embodiments, charge passes through both the word line drivers and a device coupled to the word line drivers. In one embodiment, charge of the same type passes through both the word line drivers and the device coupled to the word line drivers. This has the advantage of providing extra safety by providing alternative paths from the word lines to the substrate, while still consuming much less space on the integrated circuit. In another embodiment, charge of one type passes through the device and charge of another type passes through the word line drivers. This has the advantage of minimizing the size of the integrated circuit. For example, electrons building up on the word lines pass through at least the device to the semiconductor substrate, and holes building up on the word lines pass through at least the word line drivers to the semiconductor substrate. In another example, holes building up on the word lines pass through at least the device to the semiconductor substrate, and electrons building up on the word lines pass through at least the word line drivers to the semiconductor substrate. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same become better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein: 
       FIG. 1  is a schematic illustration of word line driver and protection CMOS transistor pair in the prior art. 
       FIG. 2  shows a simplified diagram of a word line driver circuit with a device that passes charge from the word line to the semiconductor substrate during manufacture. 
       FIG. 3  shows a cross-sectional view of part of the word line driver circuit of  FIG. 2 . 
       FIG. 4  shows a simplified diagram of multiple word line driver circuits coupled to a device that passes charge from multiple word lines to the semiconductor substrate. 
       FIG. 5  shows a cross-sectional view of part of the word line driver circuits and device of  FIG. 4 . 
       FIG. 6  shows a simplified diagram of multiple word line driver circuits each with a device that passes charge from the word line to the semiconductor substrate during manufacture. The multiple word line driver circuits are coupled to a device that passes charge from multiple word lines to the semiconductor substrate 
       FIG. 7  illustrates a simplified plan view of one embodiment of the integrated circuit with the improved plasma protection circuitry. 
       FIG. 8  shows a simplified block diagram of an integrated circuit embodiment with the improved plasma damage protection circuitry. 
   

   DETAILED DESCRIPTION 
   Reference will now be made in detail to the exemplary embodiments of the invention. It should be noted that the drawings are in simplified form and are not to precise scale. 
   Although the disclosure herein refers to certain illustrated embodiments, it is to be understood that these embodiments are presented by way of example and not by way of limitation. The intent of the following detailed description, although discussing exemplary embodiments, is to be construed to cover all modifications, alternatives, and equivalents of the embodiments as may fall within the spirit and scope of invention as defined by the appended claims. 
     FIG. 2  illustrates a circuit including word line driver  201 . The shown word line driver  201  includes two NMOS transistors  220  and  240  and a PMOS transistor  230 . One of the source/drain terminals  205  of the NMOS transistor  220  is coupled to ground reference  250  which acts as a reference supply voltage during memory operations. The other of the source/drain terminals  207  of the NMOS transistor  220  is coupled to the word line  209 . 
   The gate of the NMOS transistor  220  is coupled to the voltage NDIS  261  to turn on/off the NMOS transistor  220  during operation. The P well  211  of the NMOS transistor  220  is coupled to the voltage WLDRVSS  262  during operation. The N well  213  of the NMOS transistor  220  is coupled to the voltage AVX to prevent a PN junction effect during operation. 
   One of the source/drain terminals  215  of the PMOS transistor  230  is coupled to the word line  209 . The other of the source/drain terminals  217  of the PMOS transistor  230  is coupled to voltage GWL  264  for memory operations such as program, erase and read. The N well of the PMOS transistor  230  is coupled to the N well of the NMOS transistor  240  via line  221 . The gate of the PMOS transistor  230  is coupled to the voltage PP  265  to turn on/off the PMOS transistor  230  during memory operations. 
   One of the source/drain terminals  223  of the NMOS transistor  240  is coupled to one of the source/drain terminals  217  of PMOS transistor  230 . The other of the source/drain terminals  225  of the NMOS transistor  240  is coupled to the word line  209 . As stated above, the N well of the NMOS transistor  240  is coupled to the N well of the PMOS transistor  230  via line  221 . The P well of the NMOS transistor  240  is coupled to voltage WLDRVSS  262  during memory operations. The gate of the NMOS transistor  240  is coupled to the voltage NP  266  to turn on/off the NMOS transistor  240  during memory operations. 
   A transistor PMOS  103  is coupled to each word line driver, and passes positive plasma-induced charge to the semiconductor substrate. 
   During the manufacturing process, the voltage PP  265 , NDIS  261 , and NP  266  are floating, so that the gates for the NMOS transistor  220  and  240 , and PMOS transistor  230 , are floating. During the manufacturing process, plasma-induced charge is passed from the word lines to the semiconductor substrate. Negative charge is passed from the word line  209 , through NMOS transistor  220 , to semiconductor substrate. Because negative charge is passed through NMOS transistor  220  functioning as part of the word line driver circuit  201  during memory operations, rather than through a separate NMOS transistor  105  dedicated for plasma protection for each word line driver, a great deal of space is saved in the integrated circuit. Positive charges are passed from word line  209 , through PMOS transistor  103 , and to the semiconductor substrate. The semiconductor substrate is the ground reference  250  for the whole integrated circuit. Therefore, the integrated circuit with the word line driver circuit can be protected from plasma charge having both positive and negative polarities. 
   While carrying out memory operations such as read, erase, and program, the following voltages characterize the operation of the word line driver: 
   
     
       
             
             
             
             
           
             
             
             
             
             
           
         
             
                 
                 
             
             
                 
               Erase 
               Program 
               Read 
             
             
                 
                 
             
           
           
             
                 
             
           
        
         
             
                 
               GWL 
               −4 V 
               10 V 
               2.7 V 
             
             
                 
               AVX 
               VDD 
               10 V 
               2.7 V 
             
             
                 
               PP 
                0 V 
                0 V 
                 0 V 
             
             
                 
               NDIS 
               −4 V 
                0 V 
                 0 V 
             
             
                 
               NP 
               VDD 
               VDD 
               VDD 
             
             
                 
               WLDRVSS 
               −4 V 
                0 V 
                 0 V 
             
             
                 
               WL 
               −4 V 
               10 V 
               2.7 V 
             
             
                 
                 
             
           
        
       
     
   
   In the erase mode, NMOS transistor  220  is off because the gate bias NDIS=−4V. 
     FIG. 3  shows a cross sectional view of a portion of the circuitry of  FIG. 2 . One of the source/drain terminals  205  of the NMOS transistor  220  is coupled to ground reference  250  which acts as a reference supply voltage during memory operations. The other of the source/drain terminals  207  of the NMOS transistor  220  is coupled to the word line  209 . NMOS transistor  220  is formed in the p well  211  which in turn is formed in the N well  213  which in turn is formed in the p-type substrate acting as a ground  250 . During the manufacturing process, negative plasma-induced charge is passed from the word line  209 , through NMOS transistor  220 , and to the semiconductor substrate acting as a ground  250 . Negative plasma-induced charge on the word line  209  causes the voltage of the word line  209  to be lower than the voltage of the p well  211 . This turns on the p-n junction formed by terminal  207  and p well  211 . Then the voltage of the p well  211  is negative relative to terminal  205 . As a result, the n+ source/drain terminals  205  and  207  and the p well  211  conduct current via minority carrier injection, like a bipolar junction transistor in the active mode. 
     FIG. 4  illustrates a circuit including word line drivers  401  and  402  coupled to word lines  209  and  208  respectively. The circuitry of word line drivers  401  and  402  is similar to the circuitry of word line driver  201  of  FIG. 2 . However, in  FIG. 4 , word lines  209  and  208  are coupled to plasma protection NMOS transistors  105 A and  105 B, respectively. During the manufacturing process, negative plasma-induced charge is passed from the word line  209 , through NMOS transistor  105 A, and to the semiconductor substrate acting as a ground  250 . Similarly, negative plasma-induced charge is passed from the word line  208 , through NMOS transistor  105 B, and to the semiconductor substrate acting as a ground  250 . 
   In  FIG. 4 , multiple word line drivers, such as word line drivers  401  and  402 , are combined with a protection PMOS transistor  210 . One of the source/drain terminals  231  of PMOS  210  is coupled to the node  235  on the line  221 . The other of the source/drain terminals  233  of the PMOS transistor  210  is coupled to the semiconductor substrate acting as ground reference  250 . The gate of the PMOS transistor  210  is coupled to the N well of the PMOS transistor  210 , and voltage AVX 1  is supplied on the gate to turn off PMOS  210  during memory operations. 
   During the manufacturing process, the voltage AVX 1  is floating, so that the gate of protection PMOS transistor  210  is floating. Plasma-induced positive charges are passed from word line  209 ; through PMOS transistor  230 , the line  221 , and protection PMOS transistor  210 ; to the semiconductor substrate acting as ground reference  250 . Thus, positive charge is passed through PMOS transistor  230  functioning as part of the word line driver circuit  401  during memory operations, and through a PMOS transistor  210  which acts as a plasma protection circuit for multiple word lines. A great deal of space is saved in the integrated circuit in contrast with having a separate NMOS transistor (e.g.,  105 A,  105 B) for each word line driver for plasma protection. 
     FIG. 5  shows a cross-sectional view of a portion of the circuitry of  FIG. 4 . One of the source/drain terminals of the PMOS transistor  230  is coupled to the word line  209 . One of the source/drain terminals  231  of protection PMOS transistor  210  is coupled to the node  235 , which is coupled to the N-well of PMOS transistor  230 . The other of the source/drain terminals  233  of the PMOS transistor  210  is coupled to the semiconductor substrate acting as ground reference  250 . The gate of the PMOS transistor  210  is coupled to the N well of the PMOS transistor  210 . During the manufacturing process, the gate of protection PMOS transistor  210  is floating. Positive plasma-induced positive charges are passed from word line  209 ; through PMOS transistor  230 , the line  221 , and protection PMOS transistor  210 ; and to the semiconductor substrate acting as ground reference  250 . Positive plasma-induced charge on the word line  209  causes the voltage of the word line  209  to be higher than the voltage of the n well  232 . This turns on the p-n junction formed by p+ terminal  234  and n well  232 . As a result, the p+ terminal  234  and the n well  232  conduct current via diode action. The PMOS transistor  210  conducts hole current via minority carrier injection, similar to NMOS transistor  220  in  FIG. 3 . Positive plasma-induced charge on node  235  causes the voltage of the p+ terminal  231  to be higher than the voltage of then well  237 . This turns on the p-n junction formed by p+ terminal  231  and n well  237 . Then the voltage of the n well  237  is positive relative to p+ terminal  233 . As a result, the p+ source/drain terminals  231  and  233  and the n well  237  conduct current via minority carrier injection, like a bipolar junction transistor in the active mode. 
     FIG. 6  illustrates a circuit including word line drivers  601  and  602  coupled to word lines  209  and  208  respectively. The circuitry of word line drivers  601  and  602  is similar to the circuitry of word line driver  401  of  FIG. 4 . However, during the manufacturing process, negative plasma-induced charge is passed from the word line  209 , through NMOS transistor  220 , to the semiconductor substrate. Because negative charge is passed through NMOS transistor  220  functioning as part of the word line driver circuit  601  during memory operations, rather than through a separate NMOS transistor dedicated for plasma protection for each word line driver, a great deal of space is saved in the integrated circuit. Positive plasma-induced positive charges are passed from word line  209 ; through PMOS transistor  230 , the line  221 , and protection PMOS transistor  210 ; and to the semiconductor substrate acting as ground reference  250 . 
     FIG. 7  shows a plan view of a portion of the integrated circuit with a protection device  740  providing plasma protection to multiple word line drivers and multiple word lines. Multiple word lines such as word line  709  and  710  are arranged in parallel with each other. The multiple word lines are coupled to multiple word line driver circuits, such as word line drivers  701  and  702 . The multiple word line driver circuits are formed in a well  720 . Word line  709  is coupled to word line driver  701  and word line  710  is coupled to word line driver  702 . Plasma-induced charge of a first conductivity type is passed from the word lines  709  and  710 , through word line drivers  701  and  702  respectively, through conductive line  705 , and to the substrate. 
   Plasma protection device  740  is formed in a well  730 . The plasma protection device  740  is coupled to each of the word line drivers, including word line drivers  701  and  702 , via a deep doped region  711 , which acts as a well pick up. Plasma-induced charge of a second conductivity type is passed from the word lines  709  and  710 , through word line drivers  701  and  702  respectively, through deep doped region  711 , through plasma protection device  740 , and to the substrate. 
   During the manufacturing of the integrated circuit, the connections among the word lines  709  and  710 , the word line drivers  701  and  702 , the deep doped region  711 , the plasma protection device  740 , and the substrate are formed before the first metal connection layer. The integrated circuit is protected from plasma charge having either positive or negative polarity. 
     FIG. 8  is a simplified block diagram of an integrated circuit according to an embodiment of the present invention. The integrated circuit  850  includes a memory array  800  implemented using localized charge trapping memory cells, on a semiconductor substrate. The supply voltages  808  supply power to the integrated circuit  850 . Row decoder/word line drivers  801  are coupled to a plurality of word lines  802  arranged along rows in the memory array  800 . A column decoder  803  is coupled to a plurality of bit lines  804  arranged along columns in the memory array  800 . Addresses are supplied on bus  805  to column decoder  803  and row decoder/word line drivers  801 . Sense amplifiers and data-in structures in block  806  are coupled to the column decoder  803  via data bus  807 . Data is supplied via the data-in line  811  from input/output ports on the integrated circuit  850 , or from other data sources internal or external to the integrated circuit  850 , to the data-in structures in block  806 . Data is supplied via the data-out line  812  from the sense amplifiers in block  806  to input/output ports on the integrated circuit  850 , or to other data destinations internal or external to the integrated circuit  850 . Plasma damage protection circuitry  810  is coupled to the row decoder/word line drivers  801 . Biasing arrangement state machine  809  controls the biasing arrangements of the integrated circuit  850 . 
   While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.