Abstract:
A quantum well structure useful for semiconducting devices comprises two barrier regions and a thin epitaxially grown monocrystalline semiconductor material quantum well sandwiched between said barrier regions. Each barrier region consists essentially of alternate strain layers forming a superlattice, each of said layers being thinner than said quantum well. The layers are so thin that no defects are generated as a result of the release of stored strain energy.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to quantum well structures for semiconducting devices, the structures including a strain-layer superlattice, and to devices employing the superlattice for various applications including for metal oxide-semiconductor field effect transistors. 
     2. Description of the Related Art 
     Prior publications concerning superlattices and quantum well structures are listed as follows, and the disclosure of each of said prior publications is incorporated herein by reference: 
     1. L. Esaki and R. Tsu, IBM J. Res. and Dev. 14, 61 (1970). 
     2. R. Tsu and L. Esaki, Appl. Phys. Lett. 22, 562(1973); L.L. Chang, L. Esaki and R. Tsu, ibid 24 593(1974). 
     3. J.P. van der Ziel et al., IEEE Q.E. 22 1587(1986). 
     4. J.W. Matthews and A.E. Blakeslee, J. Crystal. Growth 32 265(1976). 
     5. G.C. Osbourn, J. Appl. Phys. 53, 1586(1982). 
     6. E.H. Poindexter &amp; P.J. Caplan, in &#34;Ins. Films on Semi.&#34; (Springer, Berlin 1981) p. 150. 
     7. E.H Nicollian and R. Tsu, U.S. Pat. No. 5,051,786, Sep. 24, 1991; R. Tsu, E.H. Nicollian, and A. Reisman, Appl. Phys. Lett. 55, 1897(1989). 
     8. Q.Y.Ye, R. Tsu and E.H. Nicollian, Phys. Rev. B44, 1806(1991). 
     9. R. People, IEEE Q.E. 22, 1696(1986). 
     10. D.G. Deepe et al., Appl. Phys. Lett. 51, 637(1987). 
     For a general review of quantum devices, see F. Capasso et al. IEEE, Transactions on Electron Devices 36, 2065(1989) and F. Sols et al., Appl. Phys. Lett. 54 350(1989), the disclosure of each being incorporated herein by reference. 
     Electronic industries have entered into a new domain of small devices dictated by quantum mechanical effects. Whenever the electron mean free path exceeds the physical dimensions, the wave nature of the electrons play a dominant role in the operations of these devices such as the now-famous superlattice (see publication 1 above) and quantum well structures (see 2 above). All these new devices involve electrons confined in a quantum well between two energy barriers. To date, the wells and barriers in general, utilize a lattice matched system such as the GaAs/GaAlAs superlattices, or a strain-layer system such as AlGaSb/GaSb heterojunction lasers (see 3 above). As long as the thickness of the strain-layer system is kept below certain values determined by the stored strain energy in those layers, a defect-free superlattice is possible for lattice mismatched systems (see 4 and 5 above). Since the backbone of the electronic industry is in silicon technology, the involvement of silicon is required in order for quantum devices to play an important role. It is well known that the importance of the metal oxide-semiconductor field effect transistor (MOSFET)owes its success to the low interface defect density of the a-SiO 2  (amorphous SiO 2 ) and Si interface (see 6 above). The problem is that once an amorphous layer is grown, it is impossible to grow subsequent silicon epitaxially. 
     Therefore it is not possible to realize quantum devices with the Si/a-SiO 2  system, except where microcrystalline Si is involved (see 7 and 8 above). This invention involves the creation of alternate layers of SiO 2  and Si, as a strain-layer superlattice, serving as energy barriers for confinement. This is possible provided the layer thickness is no more than a couple of mono-atomic layers. Specifically, we propose a structure consisting of a quantum well formed by silicon with energy barriers formed by monolayers of SiO 2  /Si strain-layer superlattice. This new scheme opens the door for a silicon based family of new quantum devices. 
     A superlattice consisting of Si and SiO 2  should be the ideal choice; however as SiO 2  grows thicker, strain due to the extremely high lattice mismatch dominates and resulting SiO 2  becomes amorphous, preventing the subsequent growth of epitaxial layers. Matthews and Blakeslee (4 above) showed that if the thickness of the strain layer is thin enough the stored energy, if released, is below the creation energy for defects such as dislocations, the strain layer is then PERFECT, and subsequent growth of the epitaxial layer can proceed. This idea is responsible for many injection lasers (see 10 above). 
     SUMMARY OF THE INVENTION 
     The invention provides a quantum well structure useful for semiconducting devices, said structure comprising two barrier regions and a thin epitaxially grown monocrystalline semiconductor material quantum well sandwiched between said barrier regions, each barrier region consisting essentially of alternate strain layers forming a superlattice, each of said layers being thinner than said quantum well and being so thin that no defects are generated as a result of the release of stored strain energy. 
     The invention further provides a metal oxide-semiconductor field effect transistor, comprising silicon having thereon a metal contact, the metal contact being separated from said silicon by an insulating layer, said insulating layer consisting essentially of alternate strain layers of SiO 2  and Si forming a superlattice, each of said layers being so thin that no defects are generated as a result of the release of stored strain energy. 
     Also provided in accordance with the invention is a barrier material for use in semiconductor devices including quantum well structures, said material consisting essentially of alternate strain layers of SiO 2  and Si forming a superlattice, each of said layers being so thin that no defects are generated as a result of release of stored strain energy. 
     According to a preferred embodiment of the invention there is provided a quantum well structure useful for semiconducting devices, said structure comprising two barrier regions and a thin epitaxially grown monocrystalline Si quantum well sandwiched between said barrier regions, each barrier region consisting essentially of alternate strain layers of SiO 2  and Si forming a superlattice, each of said layers being thinner than said quantum well and being so thin that no defects are generated as a result of the release of stored strain energy. 
     In another embodiment of the invention, there is provided a quantum well structure useful for semiconducting devices, said structure comprising two barrier regions and a thin monocrystalline quantum well sandwiched between said barrier regions, the quantum well consisting essentially of alternate strain layers forming a superlattice, each of said layers being so thin that no defects are generated as a result of the release of stored strain energy, each barrier region being thinner than said quantum well and consisting of an epitaxially grown monocrystalline semiconductor material. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic representation of a quantum well structure according to this invention. 
     FIG. 2a is a diagrammatical elevational representation of energy versus distance showing the barrier and well regions of a quantum well structure in accordance with this invention. 
     FIG. 2b is a diagrammatical plane representation of a top view of the layers which are represented in FIG. 2a. 
     FIG. 3 is a schematic illustration of a conventional MOSFET. 
     FIG. 4 is a schematic illustration of a metal-strain layer-superlattice field effect transistor (MSLSFET) of the present invention. 
     FIG. 5 is a schematic illustration of a metal oxide-strain layer-superlattice field effect transistor (MOSLSFET) of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In preferred embodiments of the invention a quantum well consists of mono-crystalline silicon epitaxially grown between two barrier sections. The barrier section consists of a region of alternate layers each at generally one to four monoatomic layers thick. The alternating layers are SiO 2  and Si. This structure exhibits all of the quantum confinement effects and is fully compatible with silicon technology. 
     The energy barriers (layers with higher energy bandgap serving as a blocking layer for the passage or penetration of electrons) of the quantum devices each consists of a strain-layer superlattice of (SiO 2  /Si)n. 
     While a couple of monolayers of SiO 2  on Si is not enough to serve as a barrier to silicon for quantum confinement, this invention proposes to build a region of alternating layers of Si/SiO 2  /Si/SiO 2  . . . , as a barrier for Si as shown in FIG. 1. 
     In FIG. 1, the silicon quantum wells with width W should have energies given by ##EQU1## and Si in-between SiO 2  has well width b, and should have energies 
     If b &gt; W, then E b1  &lt; E n , and the lower states in the quantum well E 1  and E 2  should be as distinct as any quantum well levels in III-V semiconductors. And since the thickness of SiO 2  is only a couple monolayers, the strain energy stored should be far below that which allows the generation of defects. The ideal quantum well with Si based technology is now possible! 
     Conventional epitaxial growth techniques such as VPE (vapor phase epitaxy) with the use of gaseous sources such as SiH 4 , MBE (molecular beam epitaxy), and CBE (chemical beam epitaxy) may be used to fabricate such structures. The latter two methods are preferred since this offers better control of the process. Ultra high vacuum should be used to avoid contaminants. 
     In a preferred embodiment of the present invention, the quantum well structure for semiconducting devices comprises: first and second barrier regions each consisting of alternate layers of SiO 2  /Si with thicknesses so thin that no defects can be generated as a result of the release of the stored strain energy. This thickness is generally in the range of 2 to 4 monolayers. A much thicker section of pure silicon is sandwiched between these barrier regions serving as quantum confinement of carriers. Note that the proposed barriers can also serve to confine the holes in the valence band. Doping either with modulation doping, i.e. only in the silicon layers in the barrier region or involving also the well region may be incorporated to form desired junction characteristics. Hydrogen may also be used to passively reduce the residual defects if found necessary. 
     The following applications for the structure of the invention are listed: 
     (1) momentum selection rule breakdown for pseudodirect optical transition for optoelectronic applications such as light emitting diodes and lasers, 
     (2) resonant tunneling devices and high frequency oscillators and amplifiers for high speed switching, 
     (3) electric field modulation of excitons involving the transitions of the confined electrons and hole states, 
     (4) modulation doping for high transverse mobility as interconnections for VLSI. 
     This invention, utilizing a SL-superlattice as barrier confinement, may be extended to include cases where the thickness is too great for a regular SL-superlattice. For example, in a GaP/GaAs system, the thickness of GaAs exceeds the Matthew&#39;s criterion. In such a case, we can use alternate layers of (GaP/GaAs)n/GaP... as the barrier with GaAs free from the limitations imposed by the Matthew&#39;s criterion. In short, we can now include a superlattice where only the barriers consist of a SL-superlattice. Obviously, the reverse situation also applies where only the barriers are made of pure GaP with the wells made of SL-superlattices. However, since the confined electron will spend more time in the well, the reverse structure is generally less desirable except in the case of quantum step. 
     The silicon MOSFET (FIG. 3) is probably the most important solid state electronic device. The oxide, amorphous SiO 2  is sandwiched between a metal contact and silicon. The lower the interface defect density between the amorphous SiO 2  and silicon, the faster is the switching speed. The replacement of the amorphous SiO 2  by a strain-layer superlattice of SiO 2  /Si/SiO 2  etc. described in this invention, can further reduce the interface density between the silicon and the insulator. To be more precise, as shown in FIG. 4, the amorphous SiO 2  serving as the insulating layer between the metal gate and the silicon is now replaced by this strain-layer superlattice 1 of SiO 2  /Si/SiO 2  /Si etc. Alternatively, as shown in FIG. 5, if the oxide thickness is t, we can have a layer of t/2 next to the silicon consisting of the superlattice 1 of SiO 2  /Si/SiO 2  . . . , and the top t/2 consisting of the usual amorphous SiO 2 . In this configuration, there will be defects at the interface between the amorphous SiO 2  /strain-layer superlattice. But now these defects are located away from the silicon. 
     Therefore, the MSLSFET and MOSLSFET embodiments of the present invention represent a much improved MOSFET! 
     In the present invention each layer of the alternating layers of the superlattice normally has a thickness of 1 to 4 monolayers. In some cases there are design reasons, such as to lower gate conductance, to use a wider layer, which can be up to 20 alternate layers with each of thickness 1 to 4 monolayers. 
     The number of alternating layers of the superlattice thus is variable depending on design considerations, and this number normally is up to tens of layers, but in some cases could be up to hundreds of layers. 
     EXAMPLE 1 
     FIG. 2a shows an enlarged section of FIG. 1 in terms of energy and distance, the so-called energy bandedge profile. As shown, the thicknesses of each layer in the barrier region of this example are 2 monoatomic layers The composites of SiO 2  /Si/SiO 2  /Si/SiO 2  serve as barriers. Electrons are then confined by the barriers inside the quantum well of pure silicon with thickness depending on applications, generally in the range of 2-20 nm. FIG. 2b is a schematic of the actual layers. 
     The following examples describe two typical processes of fabrication. 
     EXAMPLE 2 
     Silicon substrate is held at a constant temperature of deposition, in the 600° to 850° C. range. An electron-beam is used for the evaporation of Si and a molecular oxygen beam for oxidation. Since the residual oxygen needs to be pumped out before the next deposition of Si, a fairly large pumping system is required. It is preferable to resume the silicon deposition only after the base pressure of the chamber is again at the desired level in order to have proper control of the epitaxy growth. 
     EXAMPLE 3 
     The substrate temperature is kept at 650° C. for the Si deposition and raised to 850° C. for the oxidation cycle. 
     There might also be a need to incorporate an annealing cycle between each step of layer formation for the alternating layers, and all these procedures described here are well known techniques. Obviously in both cases, shutters and valves are needed to cycle the silicon and oxygen beams. 
     In this example, the composites of (SiO 2  /Si)n serve as energy barriers. Electrons are confined by the barriers inside the quantum well of pure monocrystalline Si of thickness depending on applications.