Abstract:
Briefly, techniques to couple differential amplifiers with a low RC time constant and provide minimal common mode voltage reduction.

Description:
FIELD 
   The subject matter disclosed herein generally relates to techniques to couple differential amplifiers. 
   DESCRIPTION OF RELATED ART 
     FIG. 1  depicts a prior art two stage differential amplifier. The RC time constant of this two stage differential amplifier is based on the resistances of RL 12  and RL 13  as well as the input capacitances of transistors Q 12  and Q 15 . The RC time constant limits the maximum speed of the prior art two stage differential amplifier. To lower this time constant, a well known emitter follower (not depicted) may be added to couple the differential amplifiers. However, by doing so the voltage across current source I 7  is lowered (e.g., by Vbe volts) and thereby may lower the voltage across current source I 7  to the point of not operating (e.g., lower the voltage at the emitter terminals of transistors Q 12  and Q 15  below a threshold operating voltage). 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  depicts a prior art two stage amplifier; 
       FIG. 2  depicts a receiver system in accordance with an embodiment of the present invention; 
       FIG. 3  depicts an amplifier in accordance with an embodiment of the present invention; 
       FIG. 4  depicts an implementation of a coupling device in accordance with an embodiment of the present invention; and 
       FIG. 5  depicts an implementation of an amplifier in accordance with an embodiment of the present invention. 
   

   Note that use of the same reference numbers in different figures indicates the same or like elements. 
   DETAILED DESCRIPTION 
     FIG. 2  depicts a receiver system  20  in accordance with an embodiment of the present invention. Receiver system  20  may include optical-to-electrical converter (O/E)  22 , amplifier  24 , re-timer system  25 , data processor  26 , bus  27 , and interface  28 . 
   O/E  22  may convert optical signals to electrical format. In some embodiments of receiver system  20 , O/E  22  may not be used and electrical format signals are received by amplifier  24 . Amplifier  24  may amplify an electrical format input signal. For example, amplifier  24  may receive a small input current and convert such current to a small output voltage (e.g., in the order of millivolts). Amplifier  24  may use some embodiments of the present invention. Re-timer system  25  may reduce jitter in the amplified electrical signals. 
   Data processor  26  may perform optical transport network (OTN) de-framing and de-wrapping in compliance for example with ITU-T G.709; and/or forward error correction (FEC) processing in compliance for example with ITU-T G.975; and/or media access control (MAC) processing in compliance for example with Ethernet. 
   Bus  27  may provide intercommunication between re-timer system  25  and/or data processor  26  and other devices such as a memory device (not depicted) and/or microprocessor (not depicted). Bus  27  may comply with one or more of the following standards: Ten Gigabit Attachment Unit Interface (XAUI) (described in IEEE 802.3, IEEE 802.3ae, and related standards), Serial Peripheral Interface (SPI), I 2 C, universal serial bus (USB), IEEE 1394, Gigabit Media Independent Interface (GMII) (described in IEEE 802.3, IEEE 802.3ae, and related standards), Peripheral Component Interconnect (PCI), ten bit interface (TBI), and/or a vendor specific multi-source agreement (MSA) protocol. 
   Interface  28  may provide intercommunication between data processor  26  and other devices such as a packet processor (not depicted) and/or a switch fabric (not depicted). Interface  28  may comply with similar communications standards as that of bus  27 . 
   In one implementation, components of system  20  may be implemented as any or a combination of: hardwired logic, software stored by a memory device and executed by a microprocessor, firmware, an application specific integrated circuit (ASIC), and/or a field programmable gate array (FPGA). In one implementation, components of system  20  may be implemented among the same integrated circuit. In another implementation, components of system  20  may be implemented among several integrated circuits that intercommunicate using, for example, a bus or conductive leads of a printed circuit board. 
     FIG. 3  depicts an amplifier  100  in accordance with an embodiment of the present invention. One implementation of amplifier  100  may include input signal source  102 , differential amplifier  104 A, differential amplifier  104 B, coupling device  106 A, and coupling device  106 B. In one implementation, differential amplifiers  104 A and  104 B have similar characteristics and may be implemented in a similar manner. In one implementation, coupling devices  106 A and  106 B may have similar characteristics and may be implemented in a similar manner. 
   Terminal Y 2  of differential amplifier  104 A may provide an input to coupling device  106 A whereas terminal Y 2 N of differential amplifier  104 A may provide an input to coupling device  106 B. Outputs of coupling devices  106 A and  106 B may be coupled to respective differential inputs Y 22  and Y 22 N of differential amplifier  104 B. Differential amplifier  104 B may provide a differential output to terminals Out 2  and Out 2 N. 
     FIG. 4  depicts one possible implementation of each of coupling devices  106 A and  106 B in accordance with an embodiment of the present invention. This implementation may include transistor Q 1 , current source I 1 , capacitance element C 0 , and resistive element R 1 . Transistor Q 1  may be implemented as a bipolar junction transistor (BJT). A collector terminal of transistor Q 1  may be coupled to a voltage source Vdd. A base terminal of transistor Q 1  may be coupled to receive an input signal. An emitter terminal of transistor Q 1  may be coupled to current source I 1 . Current source I 1  may be coupled between an emitter terminal of transistor Q 1  and voltage terminal Vee. Capacitance element C 0  and resistive element R 1  may couple respective emitter and base terminals of transistor Q 1  to an output terminal. 
     FIG. 5  depicts an implementation of an amplifier in accordance with an embodiment of the present invention. The amplifier of  FIG. 5  may include input signal source  102 , differential amplifier  104 A, differential amplifier  104 B, coupling device  106 A, and coupling device  106 B. Input signal source  102  may provide an input signal to differential amplifier  104 A. 
   One implementation of differential amplifier  104 A may include transistors Q 2  and Q 3 , current source I 2 , resistive element RL 1 , and resistive element RL 2 . Input signal source  102  may provide a differential input signal to terminals In 2  and In 2 N of respective transistors Q 2  and Q 3 . Transistors Q 2  and Q 3  may be implemented as bipolar junction transistors (BJT) having similar characteristics, although other transistors may be used. Collector terminals of transistors Q 2  and Q 3  may provide respective output terminals Y 2  and Y 2 N. Resistive elements RL 1  and RL 2  may couple collector terminals of transistors Q 2  and Q 3  to a DC voltage source, Vdd. A common mode voltage for the input signal provided to base terminals of transistors Q 2  and Q 3  may be the same as that at respective output terminals Y 2  and Y 2 N. Emitter terminals of transistors Q 2  and Q 3  may be coupled to current source I 2 . Terminal Y 2  of differential amplifier  104 A may provide an input to coupling device  106 A whereas terminal Y 2 N of differential amplifier  104 A may provide an input to coupling device  106 B. 
   Coupling devices  106 A and  106 B may couple nodes Y 2  and Y 2 N of differential amplifier  104 A to respective differential inputs Y 22  and Y 22 N of differential amplifier  104 B. Coupling devices  106 A and  106 B may be implemented as devices with similar characteristics. For example, coupling devices  106 A and  106 B may be implemented in a similar manner to the implementation shown in  FIG. 4 . However, one implementation of coupling device  106 A may include transistor Q 18 , current source  110 , resistive element R 8 , and capacitive element C 2 . One implementation of coupling device  106 B may include transistor Q 19 , current source I 11 , resistive element R 9 , and capacitive element C 1 . 
   Resistive element R 8  of coupling device  106 A may transfer low frequency components of signals from node Y 2  to node Y 22 . Resistive element R 9  of coupling device  106 B may transfer low frequency components of signals from node Y 2 N to node Y 22 N. Capacitance element C 2  may transfer high frequency components of signals from node Y 2  to node Y 22 . Capacitance element C 1  may transfer high frequency components of signals from node Y 2 N to node Y 22 N. In one implementation, common mode voltages at Y 2  and Y 2 N may match those at nodes Y 22  and Y 22 N. 
   One advantage of this implementation, but not a necessary feature, is that the RC time constant at output terminals of differential amplifier  104 A may be lower than at the base terminals of Q 12  and Q 15  of the prior art two stage differential amplifier of  FIG. 1 . One advantage of this implementation, but not a necessary feature, is that the switching speed of nodes Y 22  and Y 22 N may be faster than those of respective Q 12  and Q 15  of the prior art two stage differential amplifier of  FIG. 1 . 
   Differential amplifier  104 B may be implemented in a similar manner as differential amplifier  104 A. For example, one implementation of differential amplifier  104 B may include transistors Q 4  and Q 5 , current source I 3 , resistive element RL 3 , and resistive element RL 4 . Input node Y 22  may be provided to a base terminal of transistor Q 5  whereas input node Y 22 N may be provided to a base terminal of transistor Q 4 . Collector terminals of transistors Q 4  and Q 5  may provide respective output terminals Out 2  and Out 2 N. Resistive elements RL 3  and RL 4  may couple collector terminals of transistors Q 4  and Q 5  to a DC voltage source, Vdd. Emitter terminals of transistors Q 4  and Q 5  may be coupled to current source I 3 . 
   The following parameters are merely examples and in no way limit the scope of the invention. In one implementation, resistive elements RL 1 , RL 2 , RL 3 , and RL 4  may each have resistance values of 250 ohms. In one implementation, resistive elements R 8  and R 9  may each have resistance values of 1,000 ohms. In one implementation, capacitance elements C 1  and C 2  each may have capacitance values of 300 femtofarads. In one implementation, transistors Q 2 , Q 3 , Q 4 , and Q 5  may have similar transistor characteristics. In one implementation, transistors Q 18  and Q 19  may have similar transistor characteristics. In one implementation, current sources I 10  and I 11  may each provide a current of 0.5 mA. In one implementation, current sources I 2  and I 3  may each provide a current of 1 mA. In one implementation, Vdd may have a value of 1.8 volts. 
   The drawings and the forgoing description gave examples of the present invention. The scope of the present invention, however, is by no means limited by these specific examples. Numerous variations, whether explicitly given in the specification or not, such as differences in structure, dimension, and use of material, are possible. The scope of the invention is at least as broad as given by the following claims.