Abstract:
Prefetching data includes issuing a first request to prefetch data from a memory, receiving a response to the first request from the memory, obtaining a measure of latency between the first request and the response, and controlling issuance of a subsequent request to prefetch other data from the memory based on the measure.

Description:
BACKGROUND  
         [0001]    This invention relates to prefetching data for peripheral component interconnect devices.  
           [0002]    A common computer task is the fetching of data by a data-consuming device (such as a peripheral card) from a place where the data is stored (such as a memory). Typically the consuming device is not connected directly to the memory, but rather is connected indirectly to the memory through a bridge, a bus such as a peripheral component interconnect (PCI) bus, and a memory controller.  
           [0003]    In a simple case, when a consuming device needs data that is stored at a location in a region of the memory, the consuming device requests the data from the bridge, the bridge fetches the data through the bus and the memory controller, and the data is returned through the bus and the bridge to the consuming device. A delay (called latency) thus occurs between the time when the request is made and the time when the data arrives back at the consuming device.  
           [0004]    Often, a data-consuming device will make a series of requests for data from successive locations in a single region of memory. The cumulative latency associated with the successive requests imposes a significant performance loss on the computer system.  
           [0005]    In a common technique for reducing the latency loss, when a consuming device asks for data, the bridge fetches not only the requested data but also other data that is stored in the same memory region, based on the speculation that the consuming device may ask for the additional data in later requests. The fetching of data that has not yet been requested is called prefetching. If the consuming device requests the additional, prefetched data, the request can be served immediately from the bridge, eliminating much of the latency that would otherwise occur if requests had to be made to memory.  
           [0006]    Prefetching works well if just the right amount of data is prefetched. Prefetching more data than the consuming device will actually use (called overshoot) wastes communication bandwidth because the prefetched data will be thrown away, and can, in fact, increase latency due to increased contention for memory.  
           [0007]    On the other hand, if too little data is prefetched (called undershoot), the bridge will not be able to provide all the data the consuming device requests and thus the consuming device must incur the latency to access memory. When the bridge does not have the data requested by the consuming device, the bridge disconnects the PCI transaction and the consuming device must later retry the PCI transaction. This disconnect-retry cycle may repeat many times before the bridge gets the requested data from memory. Thus the consuming device polls the bridge by repeatedly retrying until the bridge has the necessary data. Because of the delay between the bridge receiving the data from memory and the consuming device retrying and finding the data, each disconnect adds latency due to polling overhead in addition to the latency for the bridge to acquire the data. Thus, it is important to minimize the number of disconnects for good performance.  
           [0008]    Unfortunately the bridge does not know in advance how much data the consuming device will be requesting. Therefore, it would be useful to provide a prefetching algorithm that, on one hand, minimizes the number of disconnects triggered by lack of data in the prefetching bridge and, on the other hand, minimizes overshoot that prefetches more data than is actually used.  
           [0009]    The two goals conflict, however, in that minimizing disconnects is achieved by aggressively prefetching plenty of data so that the consuming device never runs out, while minimizing overshoot is achieved by prefetching less data (zero data in the extreme case, which assures overshoot will never happen).  
           [0010]    The algorithm of the invention balances the two conflicting requirements. 
       
    
    
     DESCRIPTION OF DRAWINGS  
       [0011]    [0011]FIG. 1 is a block diagram of a processing system.  
         [0012]    [0012]FIG. 2 is a flowchart showing a process of prefetching data.  
         [0013]    [0013]FIGS. 3, 3A, and  3 B show registers.  
         [0014]    [0014]FIG. 4 is a flowchart showing a process of computing a latency estimate.  
         [0015]    [0015]FIG. 5 is a flowchart showing a process of determining when to launch a prefetch request.  
         [0016]    [0016]FIG. 6 is a graph showing timing of prefetching data. 
     
    
     DESCRIPTION  
       [0017]    Referring to FIG. 1, an example of a system  100  that may be used in prefetching data is shown. The system  100  includes a peripheral component interconnect (PCI) hub link  132  that connects a memory controller hub (MCH)  104  with an I/O hub or PCI bridge  134 , such as the Intel® 82806 PCI 64 Hub (P64H) or the Intel® P64H-2. The PCI bridge  134  supports I/O units  136 , such as sixty-four bit and thirty-two bit PCI slots or devices  136 . The PCI bridge  134  includes one or more buffers  138  that may store data prefetched from a memory  124  and stream size values, round-trip latencies, counters, and other similar data. Generally, the PCI bridge  134  associates a buffer  138  with each active PCI unit  136 .  
         [0018]    One of the PCI units  136  may signal the PCI bridge  134  that it desires data from the memory  124  starting at a particular memory address location. A PCI protocol used by the PCI unit  136  typically does not provide a way for the signaling PCI unit  136  to indicate to the PCI bridge  134  how much data the PCI unit  136  needs from the memory  124 . The PCI bridge  134  typically fetches an initial amount of data from the memory  124  smaller than the expected amount of data desired by the PCI unit  136 . If the PCI unit  136  needs more data, the PCI bridge  134  later fetches more data from the memory  124 .  
         [0019]    In a more detailed example, when the PCI unit  136  makes a request, the PCI bridge  134  responds either with the requested data or with a retry signal. In the former case, the PCI bridge  134  streams data to the PCI unit  136  until either the PCI bridge  134  runs out of available data or the PCI unit  136  acquires all the data it needs. If the PCI bridge  134  runs out of data, the PCI bridge  134  disconnects the PCI transaction, terminating the stream, and the PCI unit  136  must retry the transaction to acquire further data. Once the PCI unit  136  acquires all the data, it terminates streaming, leaving any further data that may have been fetched from memory in the PCI bridge  134 . If the PCI unit  136  receives a retry signal, the PCI unit  136  waits a few clocks and then makes another request.  
         [0020]    The PCI unit  136  may retry many times before the PCI bridge  134  is able to fetch data from the memory  124  and have data available to stream to the PCI unit  136 . The PCI bridge  134  attempts to prefetch data from memory to minimize the latency in acquiring all the data. The objective may be to maintain streaming, avoiding disconnects due to the PCI bridge  134  running out of data—called prefetch undershoot—and to avoid fetching more data than the PCI unit  136  needs—called prefetch undershoot.  
         [0021]    A variety of prefetch algorithms are possible. For example, the PCI bridge  134  may estimate how much data to fetch from the memory  124  for the requesting PCI unit  136 . Alternatively, the PCI bridge  134  may make a first request for data to the memory  124 , wait a number of clock cycles, and make another request for data to the memory  124  starting at a memory location following the last requested memory location in the first request for data. The PCI bridge  134  may continue and repeat this process any number of times, making a request for data, waiting a number of clock cycles, and making another request for data, until a certain amount of data has been prefetched from the memory  124 . The number of clock cycles may be chosen so that the PCI bridge  134  can continuously stream data fetched from the memory  124  to the requesting PCI unit  136  once the PCI bridge  134  starts to stream data to the requesting PCI unit  136 .  
         [0022]    Given a round-trip latency from the PCI bridge  134  to the memory  124  and back, overshoot may result if successive prefetch requests are launched from the PCI bridge  134  to the memory  124  too rapidly. On the other hand, if successive prefetch requests are launched too infrequently, the PCI bridge  134  may lose connectivity with the requesting PCI unit  136  (i.e., be unable to continuously stream data to the requesting PCI unit  136 ).  
         [0023]    With a process  140 , the PCI bridge  134  may dynamically determine when to launch successive prefetch requests to the memory  124  based on, e.g., an estimate of the round-trip latency from the PCI bridge  134  to the memory  124  and back. Additionally, with the process  140 , the PCI bridge  134  may dynamically determine the amount of data to request from the memory  124  in each successive prefetch request based on, e.g., previous amounts of data consumed by the requesting PCI unit  136 .  
         [0024]    Turning to other elements included in the system  100  before further discussing the process  140 , a chipset  102  such as the Intel® 840 chipset can provide interfaces between a computer&#39;s subsystems (or the subsystems associated with the device that includes the system  100 , such as a workstation or a server). The chipset  102  includes the MCH  104  such as the Intel® 82840 MCH and an input/output controller hub (ICH)  106  such as the Intel® 82801 ICH. The system  100  also includes a basic input/output system (BIOS)  108  which may or may not be included as part of the chipset  102 .  
         [0025]    Memory channels  122  connect the MCH  104  with the memory  124 . The memory  124  may include dynamic random access memory (DRAM) or memory repeater hub (MRH). Each memory channel  122  may be able to accommodate its own DRAMs or MRHs.  
         [0026]    A thirty-two bit PCI bus  110  connects the ICH  106  with PCI slots or devices  112  that may connect to thirty-two bit PCI devices or PCI add-ons. Buses  114  connect the ICH  106  with various I/O elements such as integrated drive electronics (IDE) controllers/drivers  116 , Universal Serial Bus (USB) ports  118 , compressors/decompressors (codecs)  120 , and other similar elements.  
         [0027]    A processor bus  126  connects the MCH  104  to a CPU  128  that may include one or more processors  130 , e.g., Intel® Pentium processors.  
         [0028]    Referring to FIG. 2, a prefetching process  200  illustrates an example of the process  140 . Such a prefetching process can be executed for each stream of data that the PCI bridge  134  may handle. In the prefetching process  200 , a stream size value is initialized  202  to a static value. The stream size value indicates the amount of data consumed by the requesting PCI unit  136  in the last series of PCI requests terminated by the PCI unit  136 , as opposed to those terminated by the PCI bridge  134  disconnecting. The stream size value also indicates the amount of data for the PCI bridge  134  to request in its next request for data from the memory  124 . Thus, the PCI bridge  134  can dynamically determine how much data to request from the memory  124  in successive requests for data based on at least one previous data transfer between the PCI bridge  134  and a PCI unit  136 . In this way, the prefetching process  200  may reduce overshoot while maintaining the ability to tolerate long latencies.  
         [0029]    The stream size value may be expressed in clock cycles, seconds, bits, bytes, or other similar size or time parameter. If the stream size value is expressed as a time parameter such as clock ticks, seconds, or any divisions or multiples thereof, the PCI bridge  134  requests data from the memory  124  for that length of time. If the stream size value is expressed as a size parameter such as bits, bytes, or any divisions or multiples thereof, the PCI bridge  134  requests that much data from the memory  124  over as much time as necessary. As noted above, the stream size value may change as the PCI bridge  134  completes requests (e.g., requests data from the memory  124  and receives the data back). In this way, the PCI bridge  134  can modify the aggressiveness of its data prefetching.  
         [0030]    The stream size value&#39;s initial static value can be any preprogrammed value: an arbitrary value, an empirical value, a calculated estimate stream size value, or other similar value. In the case of multiple request streams, each stream size value&#39;s initial static value may vary.  
         [0031]    For simplicity, only one stream size value is discussed with reference to the prefetching process  200  example; a stream size value may actually exist for each request stream supported by the PCI bridge  134 , in which case the PCI bridge  134  can modify the aggressiveness of its data prefetching on a per-request-stream basis. A request stream generally refers to sets of data sequentially requested at consecutive memory locations.  
         [0032]    The PCI bridge  134  makes  204  a prefetch request to the memory  124 . The prefetch request is for an amount of data equal in time or size to the stream size value. The data can include computer-executable instructions, a combination of data and instructions, or other similar data. The memory  124  can include memory such as main memory, virtual memory, random-access memory (RAM), read-only memory (ROM), or other similar storage location. The memory  124  can be included in any device capable of maintaining the memory  124  such as a desktop computer, a mobile computer, a server, a workstation, a personal digital assistant, a telephone, a pager, or other similar device. These and other elements that may be used in implementing the prefetching process  200  are described further below.  
         [0033]    The memory  124  responds  206  to the request by returning an amount of data. The PCI bridge  134  receives  208  the data and stores the data at the PCI bridge  134  (e.g., in the buffer  138 ) or at another storage location accessible by the PCI bridge  134 . From the buffer  138  or the other storage location, the PCI bridge  134  can transmit the data to the requesting PCI unit  136 .  
         [0034]    The PCI bridge  134  can then perform a latency estimate process  210  and/or a stream prediction process  212 . The PCI bridge  134  can use the latency estimate process  210  to help determine the timing of prefetch requests while using a static value for the size of each request. The PCI bridge  134  can use the stream prediction process  212  to determine the amount of data to prefetch in each prefetch request and send prefetch requests at regularly scheduled intervals. If the processes  210  and  212  are used together, the PCI bridge  134  can dynamically determine when to make prefetch requests and how much data to request in each request.  
         [0035]    The PCI bridge  134  need not implement both the latency estimate process  210  and the stream prediction process  212  as part of the prefetching process  200 . If the PCI bridge  134  does implement both processes  210  and  212 , the PCI bridge  134  may perform the latency estimate process  210  and the stream prediction process  212  concurrently or sequentially. Typically, the PCI bridge  134  would perform the latency estimate process  210  before the stream prediction process  212  because while both the latency estimate process  210  and the stream prediction process  212  consider data regarding a full request-response cycle (round-trip latency and amount of data requested, respectively), the stream prediction process  212  needs additional data regarding the actual amount of data requested.  
         [0036]    Turning to the latency estimate process  210  first, the PCI bridge  134  records  214  the round-trip latency for the request. That is, the PCI bridge  134  stores the amount of time in seconds, clock ticks, or other time measurement that lapsed between the time that the PCI bridge  134  made the request to the time that the PCI bridge  134  began to receive a response. The PCI bridge  134  may store the round-trip latency time in a memory location such as a cache, a register, a buffer, or other memory location.  
         [0037]    [0037]FIG. 3 shows an example of how the PCI bridge  134  may store successive round-trip latency times in a memory location  300  (e.g., the buffer  138 ). For simplicity in this example, the memory location  300  includes two registers  302  and  304 ; the memory location  300  could include any number (n) of registers (enough to store values for the previous n latencies). The registers  302  and  304  may form a shift register in that when the PCI bridge  134  stores a new round-trip latency at the memory location  300 , a previously stored value is lost (except for possibly the first n latencies where the registers  302  and  304  may be initialized as empty).  
         [0038]    For example, at a time t 1 , the PCI bridge  134  has made two requests for data and has stored the round-trip latency time for the first and the second requests in registers  302  and  304 , respectively. At a time t 2 , the PCI bridge  134  has made a third request for data and has stored the third round-trip latency time in the register  302 . At a time t 3 , the PCI bridge  134  has made a fourth request for data and has stored the fourth round-trip latency time in the register  304 . This storage pattern continues for subsequent requests for data.  
         [0039]    In another example, values may be stored at the memory location  300  so that the registers  302  and  304  function as a right-shift register (see FIG. 3A) or as a left-shift register (see FIG. 3B) where a new round-trip latency value is pushed into the memory location from the left or the right, respectively, thereby losing the right-most or left-most stored value, respectively, with each successive storage.  
         [0040]    Returning to the latency estimate process  210  of FIG. 2, after storing the round-trip latency for the request, the PCI bridge  134  computes  216  a latency estimate from the stored round-trip latencies, actual round-trip latencies from previous requests. The PCI bridge  134  can dynamically determine when to launch the next prefetch request based on the latency estimate.  
         [0041]    [0041]FIG. 4 shows examples of how the PCI bridge  134  may compute the latency estimate. In one example, the PCI bridge  134  may set  400  the latency estimate as the last recorded round-trip latency. In such a case, the PCI bridge  134  may use a minimal amount of storage space, e.g., one register, to store the round-trip latency for the most recent request for data.  
         [0042]    In another example, the PCI bridge  134  may compute  402  an average of the previous n recorded round-trip latencies, where n can equal any integer greater than zero. This average may be a straight average or it may be a weighted average. In the case of a weighted average, the PCI bridge  134  may give more weight in the average calculation to more recently observed round-trip latency values.  
         [0043]    The PCI bridge  134  may maintain a counter that the PCI bridge  134  increments with each made request for data to aid in calculating the average. (If the PCI bridge  134  is tracking multiple request streams, each request stream may have its own counter.)  
         [0044]    The resources used to compute the latency estimate may vary. In the example of FIG. 3 where two registers  302  and  304  are used to store round-trip latencies for the previous two requests, the PCI bridge  134  could compute a straight average using the registers  302  and  304  and a simple adder, e.g., a half-adder, a full-adder, or other similar mechanism that can add the values stored in the two registers  302  and  304 . Once an average is computed, the PCI bridge  134  can set  404  the latency estimate as the computed average.  
         [0045]    Returning again to the latency estimate process  210  of FIG. 2, after computing the latency estimate, the PCI bridge  134  determines  218  when to launch subsequent prefetch requests based on the latency estimate. The PCI bridge  134  may take different actions based on how the latency estimate compares with a nominal round-trip latency.  
         [0046]    [0046]FIG. 5 shows an example of the actions that the PCI bridge  134  may take in determining when to launch subsequent prefetch requests. The PCI bridge  134  may determine  500  whether the latency estimate is greater than a nominal latency. If the latency estimate is greater than the nominal latency, then the PCI bridge  134  plans  502  to launch subsequent requests a number of clock cycles earlier than they would be nominally launched. This number may be a fixed amount such as a whole number of clock cycles, or it may be a calculated number such as the latency estimate minus the nominal latency. The number used (fixed or calculated) may be the same for all cases of the latency estimate exceeding the nominal latency or the number may vary, e.g., vary depending on the amount of difference between the latency estimate and the nominal latency. Expediting subsequent prefetch requests may enable the PCI bridge  134  to gather more data on a prefetch basis, e.g., before the data is actually requested.  
         [0047]    If the latency estimate is less than the nominal latency, then the PCI bridge  134  plans  504  to delay launch of subsequent requests by a number of clock cycles. This number may be a fixed amount or a calculated number as described above (except that the calculated number, to be positive, would be the nominal latency minus the latency estimate). Delaying subsequent prefetch requests may prevent the PCI bridge  134  from making unnecessary prefetch requests.  
         [0048]    If the latency estimate equals the nominal latency, then the PCI bridge  134  may launch the subsequent request after a nominal period.  
         [0049]    Turning now to the stream prediction process  212 , the PCI bridge  134  compares  220  the stream size value with an amount of data that the PCI unit  136  consumed in the last series of PCI requests that was terminated by the PCI unit  136 . (If the stream size value is time-based rather than size-based, the PCI bridge  134  compares the time of the request with the stream size value.)  
         [0050]    Generally, the stream prediction process  212  includes a built-in hysteresis that prevents the PCI bridge  134  from being confused by temporary spikes in the submitted request size for a particular request stream. If the stream size value is smaller than the amount of data consumed in the actual request, then the size (or time) prediction was too small. Thus, the PCI bridge  134  increments  222  the stream size value by a fixed amount or by a dynamically determined amount. If the stream size value is larger than the amount of data consumed in the actual request, then the size (or time) prediction was too large, so the PCI bridge  134  decrements  224  the stream size value by a fixed amount or a dynamically determined amount. If the stream size value equals the amount of data consumed in the actual request, then the PCI bridge  134  maintains  226  the stream size value, i.e., requests that same amount of data in the next prefetch request involving that request stream. The PCI bridge  134  may consider the stream size value equal to the amount of data consumed in the actual request if the amount of data consumed in the actual request is within a certain range above and/or below the stream size value.  
         [0051]    The PCI bridge  134  may modify the stream prediction process  212  by adding logic to keep track of the average size of actual requests for the request stream (or for each request stream in the case of multiple request streams). If keeping track of the average actual request size, the PCI bridge  134  can support two modes of operation: aggressive prefetching (for large requests) and small prefetching (for small requests). If a request stream is predicted to make too small of a request, the PCI bridge  134  could use a small prefetch size, while for a request stream that has predominantly large request sizes, the PCI bridge  134  can use a more aggressive setting of prefetch sizes.  
         [0052]    The PCI bridge  134  may determine whether a request stream is small or large based on previous history of each particular PCI unit  136 . Alternatively, the PCI bridge  134  may be able to identify certain types or particular models of PCI units  136  and know that request sizes for the certain types or particular models are made in certain byte block sizes. Similarly, the BIOS  108  may program the PCI bridge  134  with data regarding the PCI units  136 .  
         [0053]    The prefetching process  200  is one implementation of a prefetching algorithm in accordance with the invention. The prefetching process  200  may be modified. For example, as mentioned above, the latency estimate process  210  and the stream prediction process  212  need not both be implemented as part of the prefetching process  200 .  
         [0054]    Referring to FIG. 6, a graph  600  indicates an example prefetching scenario using the prefetching process  200  of FIG. 2 in the system  100  of FIG. 1. In this example, at a time t 1  the PCI bridge  134  receives a request for data from one of the PCI devices  136  and the PCI bridge  134  requests data from the memory  124 . The amount of data that the PCI bridge  134  requests from the memory  124  may be calculated as explained above with reference to FIG. 2. After a latency period L 1 , the PCI bridge  134  begins to receive data back from the memory  124  at a time t 2 . Data begins to collect in the buffer  138  at time t 2 , as indicated by the positive slope of a first line segment  602 .  
         [0055]    At a time t 3 , the PCI bridge  134  begins to stream data to the PCI device  136  that requested the data. Data continues to return to the PCI bridge  134  from the memory  124 , as indicated by the positive slope of a second line segment  604 . Note that the slope of the second line segment  604  is less than the slope of the first line segment  602  because while the PCI bridge  134  continues to store data from the memory in the buffer  138  after time t 3 , the PCI bridge  134  is also streaming data from the buffer  138  to the requesting PCI device  136 .  
         [0056]    At a peak point  606 , the PCI bridge  134  has received the amount of data that it requested from the memory  124 . Thus, the slope of a third line segment  608  has a negative slope as the PCI bridge  134  continues to stream data to the requesting PCI device  136 .  
         [0057]    The PCI bridge  134  launches a prefetch request to the memory  124  at a time t 4  and, after a latency period L 2 , begins to receive data back from the memory  124  at a time t 5  and to store the prefetched data in the buffer  138 . Time t 4  is chosen, by estimating L 2  by the process described with FIG. 4, so that before the buffer  138  runs out of data at time t 5 , the PCI bridge  134  will have prefetched data from the memory  124  that the PCI bridge  134  can stream to the requesting PCI device  136 . In this example, the latency period L 2  is ideally timed (e.g., perfectly estimated) so that prefetched data reaches the PCI bridge  134  exactly at the time when the buffer  138  runs out of data fetched from the request launched to the memory  124  at time t 1 . In this way, the PCI bridge  134  can continuously stream data to the requesting PCI device  136  without losing connectivity with the requesting PCI device  136 .  
         [0058]    From time t 5  to a second peak point  610 , the PCI bridge  134  continues to stream data to the requesting PCI device  136  while the prefetched data collects in the buffer  138 , as evidenced by the positive slope of a fourth line segment  612 . At the second peak point  610 , the PCI bridge  134  has received all of the requested prefetch data, so the slope of a fifth line segment  614  has a negative slope.  
         [0059]    At a time t 6 , the requesting PCI device  136  terminates the transaction because the requesting PCI device  136  has received all of its currently desired data from the memory  124 . The PCI bridge  134  thus stops streaming data to the requesting PCI device  136  at time t 6 . The time between times t 3  and t 6  can be considered a burst connect period, the time in which the PCI bridge  134  may stream data to the requesting PCI device  136  and request multiple sets of data for the requesting PCI device  136  at consecutive memory addresses from the memory  124 .  
         [0060]    Not all of the data prefetched from the memory  124  and stored in the buffer  138  was streamed to the requesting PCI device  136  in this example, as indicated by the zero slope and positive y-axis location of a sixth line segment  616 . The amount of data remaining in the buffer  138  is the overshoot. The PCI bridge  134  may clear the buffer  138  of this data or it may retain the data in case the requesting PCI device  136  (or other PCI device  136 ) subsequently requests the data.  
         [0061]    At a lower level of detail, each request to the memory  124  by the PCI bridge  134  involves the initiation of a new data transfer using a Memory-Read-Multiple (MRM) operation. Note also that the PCI bridge  134  may identify actual data requests/transfers by using MRM commands.  
         [0062]    If the requesting PCI device  136  is disconnected from the PCI bridge  134  during the data transfer, e.g., during the burst connect period, and later retries the data transfer, the retry is still considered to be part of the original request. For example, for PCI traffic, contents of the buffer  138  may be invalidated when certain events occur, e.g., page boundary crossing, processor-initiated writes, etc. In order to avoid confusing the stream prediction process  212  if this invalidation occurs, the PCI bridge  134  can recognize an event that causes a buffer invalidation and keep track of request sizes across such invalidation events. In this way, the PCI bridge  134  can know how much data the requesting PCI device  136  desires and can begin to prefetch the data without having to wait for the requesting PCI device  136  to signal the PCI bridge  134  for data after the buffer invalidation.  
         [0063]    In another example, for Gigabit Ethernet traffic, requests to the PCI bridge  134  that would cross a 4K page boundary are typically broken into two consecutive requests (MRMs) by the requesting PCI device  136 . By keeping track of the amount of data consumed by a request stream at the time of a stream termination, as well as the memory address at which the termination occurred, the PCI bridge  134  can recognize when a larger request is broken into two by the requesting PCI device  136  and can avoid resetting the stream size value associated with that request stream.  
         [0064]    If the requesting PCI device  136  is disconnected, then the requesting PCI device  136  likely receives its requested data in a series of disconnected spurts of data rather than in one continuous stream of data. Receiving the data in spurts can have a detrimental impact on overall I/O performance, and using the latency estimate process  210  can help reduce these detrimental effects and improve overall I/O performance. With the latency estimate process  210 , the PCI bridge  134  may use a more aggressive prefetch algorithm that launches prefetch requests early enough to allow for the data to be returned by the memory  124  before a disconnect occurs. However, a more aggressive prefetch algorithm may lead to larger prefetch overshoots, which in turn may reduce overall I/O performance, so the latency estimate process  210  attempts to reduce the number of disconnects without making the prefetch algorithm too aggressive. Using the stream prediction process  212  may also improve overall I/O performance by reducing prefetch overshoot.  
         [0065]    The techniques described here are not limited to any particular hardware or software configuration; they may find applicability in any computing or processing environment. The techniques may be implemented in hardware, software, or a combination of the two. The techniques may be implemented in programs executing on programmable machines such as mobile or stationary computers, personal digital assistants, and similar devices that may each include a processor, a storage medium readable by the processor (including volatile and non-volatile memory and/or storage elements), at least one input device, and one or more output devices. Program code is applied to data entered using the input device to perform the functions described and to generate output data. The output data is applied to one or more output devices.  
         [0066]    Each program may be implemented in a high level procedural or object oriented programming language to communicate with a machine system. However, the programs can be implemented in assembly or machine language, if desired. In any case, the language may be a compiled or interpreted language.  
         [0067]    Each such program may be stored on a storage medium or device, e.g., compact disc read only memory (CD-ROM), hard disk, magnetic diskette, or similar medium or device, that is readable by a general or special purpose programmable machine for configuring and operating the machine when the storage medium or device is read by the computer to perform the procedures described in this document. The system may also be considered to be implemented as a machine-readable storage medium, configured with a program, where the storage medium so configured causes a machine to operate in a specific and predefined manner.  
         [0068]    Other embodiments are within the scope of the following claims.