Abstract:
A sequence generator employing a neural network having its output coupled to at least one plurality of delay elements. The delayed outputs are fed back to an input interconnection network, wherein they contribute to the next state transition through an appropriate combination of interconnections.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to sequence generators, and more specifically, to systems employing neural computation to develop sequences of output signal vectors. 
     Neural networks have been described by J. J. Hopfield in &#34;Neurons With Graded Response Have Collective Computational Properties Like Those of Two-state Neurons&#34;; Proc. Natl. Sci., USA Vol. 81, pp. 3088-3092, and by J. J. Hopfield and D. W. Tank in &#34;`Neural` Computation of Decisions in Optimization Problems&#34;, Biological Cybernetics, Vol. 52, (1985), pp. 141-152; as well as in U.S. patent application Ser. No. 693,479 now U.S. Pat. No. 4,660,166 filed on behalf of J. J. Hopfield on Jan. 2, 1985, and U.S. patent application Ser. No. 795,789 now U.S. Pat. No. 4,719,591 filed on behalf of J. J. Hopfield and D. W. Tank on Nov. 7, 1985. 
     Basically, a neural network is a highly parallel computational circuit comprising a plurality of amplifiers, with each of the amplifiers feeding back its output signal to itself and all of the other amplifiers through conductance T ij . The T ij  conductances (where T ij  denotes the conductance between the output of amplifier j and the input of amplifier i) and the associated connections can be thought of as comprising a feedback network which has one output signal set and two input signal sets. The output signal set is applied to the amplifier inputs, one of the input signal sets is derived from the amplifier outputs, and the other input signal set is responsive to input stimuli applied to the neural network. As shown in the prior art, one can explicitly specify the values of the T ij  conductances to achieve predetermined results, such as reaching different specified output states of the amplifier in response to different ranges of input stimuli. Also as described in the prior art, an input interconnection network may be interposed between the input stimuli and the second set of inputs of the feedback network. The input interconnection network permits manipulation of the expected input signals to corresponding signals that drive the feedback network and the amplifiers. 
     The neural network model described most extensively in the prior art is one with symmetric couplings, i.e., the connections between pairs of neurons satisfy the relationship T ij  =T ji . The dynamics of such a network is relatively simple. The system moves in the direction of reducing a global energy function of the circuit, E, to states that are local minima of E, and once a local minimum is reached, the circuit remains at the stable state until perturbed by a sufficiently large input signal that moves the circuit to a different local minimum. The local minima may be thought of as the stored &#34;memories&#34; that are characterized by the vectors M.sup.μ. An associative memory can be constructed with the Hopfield neural network by constructing the connection strengths T ij  in accordance with the outer product, or Hebb, rule, to wit, by assigning ##EQU1## for j≠i, and 0 otherwise. 
     A symmetric-coupling neural network thus does not provide temporal association. Asymmetric couplings, on the other hand, can generate sequential memories by adding weighted terms of the form M.sup.μ+1 M.sup.μ to the T terms in the feedback matrix. Each of these M.sup.μ+1 M.sup.μ terms is a projection of one &#34;memory&#34; to the next &#34;memory&#34;. The problem with this technique for generating sequences is that only sequences of limited length are achieved because the state of the network becomes progressively mixed among memories comprising the sequence when long or cyclic sequences are used. More specifically, the essential difficulty in generating sequences through modifications of the feedback matrix is that the network does not become stationary in any one memory before transition to the next memory begins. 
     It is an object of this invention to provide a structure that simply and efficiently permits the realization of any desired sequence developed by neural networks. 
     SUMMARY OF THE INVENTION 
     These and other objects of the invention are achieved with a neural network having its output coupled to at least one plurality of delay elements. The delayed outputs are fed back to an input interconnection network, wherein they contribute to the next state transition through an appropriate combination of interconnections. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 illustrates one embodiment of a sequence generator in accordance with the principles of my invention; and 
     FIG. 2 illustrates a second embodiment of a sequence generator in accordance with the principles of my invention. 
    
    
     DETAILED DESCRIPTION 
     With reference to FIG. 1, a sequence generator is realized with a neural network combined with a delay network and an input interconnection network. The neural network, as described in the prior art, comprises an amplifier network 10 feeding its output signal to, and receiving its input signals from, a feedback network 20. Delay/averaging network 30 is responsive to amplifier network 10, and input interconnection network 40 is responsive (through a gate network 50) to the output of delay/averaging network 30. Network 40 feeds its output signals to feedback network 20. 
     The sequence generation action can be seen when it is recalled that the equation of motion for the neural network (networks 10 and 20), as taught by the prior art, minimizes the energy function expressed by ##EQU2## where V i  and V j  are the output voltages of amplifiers i and j, respectively, in amplifier network 10; T ij  is the conductance within the feedback network that connects the output of amplifier j to the input of amplifier i; R i  is the resistance between the input of amplifier i and ground; g i   -1  (V) is the inverse of the transfer function of amplifier i; and I i  is the current input to feedback network 20 (from input interconnection network 40) leading to the input of amplifier i. When gate network 50 merely passes the signals from delay/averaging network 30 to interconnection network 40, a perusal of the FIG. 1 structure reveals that the last term in Equation (1), ##EQU3## which accounts for the circuit into the feedback network contributed by the interconnection network, may be replaced with ##EQU4## where ##EQU5## represents the delayed value of the j th  output, determined by averaging over the history of the j th  output with a normalized weighting function D(x). The delay time is given by the time constant τ D  associated with D(x). Two particular implementations of the delay/average function may be pure delay, and an exponentially decaying averaging delay. The first may be realized with pure delay means, D(t)=δ(t-τ D ), yielding delayed signals V j  (t)=V j  (t-τ D ). The second may be implemented with a simple resistor-capacitor network, for which case D(t)=(1/τ D )e -t/ τ.sbsp.D. The connection strengths Q ij  are constants that are chosen to cause the desired transitions between sequential states. In accordance with one approach, the Q ij  strengths can follow the relationship ##EQU6## where M j .sup.μ is the j th  output of network 10 (V j ) in the μ th  output vector, M i .sup.μ+1 is the i th  output of network 10 in the next (μ+1 th ) output vector, and m is the length of the sequence (i.e., the number of different M vectors created). To achieve a cyclic sequence, the summation of Equation (3) is performed in modulo m. In other words, M m+1  =M 1 . 
     Network 50 is able to disconnect the feedback path from delay/averaging network 30 to interconnection network 40 by action of the control port, causing the FIG. 1 circuit to settle to a quiescent state. Gate network 50 can also be endowed with the ability to add a &#34;kicker&#34; signal vector to the fed-back voltage, under control of an enabling signal at the control port which could drive the FIG. 1 circuit from one cyclic sequence to a second cyclic sequence; both of which are designed into the Q ij  interconnection values. 
     The output of the FIG. 1 circuit can be obtained from the output of amplifier network 10 or, alternatively, from the output of delay/averaging network 30. 
     The structure of delay/averaging network 30 can be quite simple. In FIG. 1 it is shown as a simple RC network, which produces a delay related to the RC time constant. To avoid diminution of the signal because of the series resistor in the RC network, and to insure a low output impedance to the delay network, the FIG. 1 delay/averaging network 30 includes an amplifier following the RC delay circuit. 
     Many changes in construction and widely differing embodiment would, no doubt, suggest themselves to those skilled in the art to which this invention pertains, which would not depart from the spirit and scope of this invention. For example, the FIG. 1 arrangement can generate sequences where each state is derived from the immediately previous state. FIG. 2 presents a somewhat more general realization for developing sequences where each successive state is a function of more than one previous state. In FIG. 2, neural network 60 is fed by a serially connected arrangement of interconnection networks (70,71, and 72 in FIG. 2). Each one of the interconnection networks of FIG. 2 is similar in structure to interconnection network 40 of FIG. 1, with the only difference being that another set of inputs is available for adding the current offered by a preceding interconnection network to the network&#39;s output current. Each of the above interconnection networks derives its inputs from another interconnection network and from the output of a different delay network in a set of delay networks (70,81, and 82 in FIG. 2) that are responsive to the output of neural network 60. 
     As can be appreciated from the analysis related to the FIG. 1 arrangement, on the FIG. 2 arrangement, each output state that is developed by neural network 60 is a function of N previous delayed outputs, that is, where N is the number of delay networks. 
     As another example of a variation in accordance with the principles of my invention, the gating network presented in FIG. 1 does not necessarily have to be interposed between the delay network and the interconnection network. Any location where controlled interference with the sequence generation process is possible is equally acceptable. Also, the simple delay network shown in FIG. 1 (the RC delay coupled with amplification) can easily be substituted with more elaborate delay means, including clocked delay means--such as CCDs. Also, when more than one delay network is realized, the delay between different networks need not necessarily be of equal value.