Abstract:
A package substrate is provided. The package substrate includes: a dielectric layer; a passive component embedded in the dielectric layer and contacting the dielectric layer; and a circuit layer embedded in the dielectric layer and having a first surface aligned with a second surface of the dielectric layer.

Description:
BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The present invention relates to a package substrate, and in particular relates to a package substrate with a passive component embedded therein and manufacturing methods thereof and a chip package having the package substrate. 
     Description of the Related Art 
     Along with the rapid development of semiconductor packaging technologies, different chip package types have been developed for semiconductor devices. To reduce the height of chip packages so as to meet the miniaturization or thinning requirements of products, semiconductor components are generally embedded in the cavities of package substrates so as to reduce the volume of the overall semiconductor devices. 
     In general, the package substrate uses a core layer to support chips thereon. However, the core layer is very expensive. Therefore, methods for lowering the manufacturing cost of chip packages are required. 
     BRIEF SUMMARY OF THE INVENTION 
     An embodiment of the invention provides a package substrate which includes: a dielectric layer; a passive component embedded in the dielectric layer and contacting the dielectric layer; and a circuit layer embedded in the dielectric layer and having a first surface aligned with a second surface of the dielectric layer. 
     An embodiment of the invention provides a chip package, which includes: a package substrate including: a dielectric layer; a passive component embedded in the dielectric layer and contacting the dielectric layer; a first circuit layer embedded in the dielectric layer and having a first surface aligned with a second surface of the dielectric layer; and a chip disposed on the package substrate and electrically connected to the first circuit layer and the passive component. 
     An embodiment of the invention provides a manufacturing method of a package substrate, which includes: forming a first circuit layer on a carrier; disposing a passive component on the carrier; forming a dielectric layer on the carrier to embed the passive component and the circuit layer in the dielectric layer; forming a second circuit layer on the dielectric layer; and removing the carrier. 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIGS. 1A-1I  are cross-sectional views showing the steps of forming a chip package in accordance with an embodiment of the present invention; 
         FIGS. 2A-2I  are cross-sectional views showing the steps of forming a chip package in accordance with an embodiment of the present invention; 
         FIGS. 3A-3I  are cross-sectional views showing the steps of forming a chip package in accordance with an embodiment of the present invention; and 
         FIGS. 4A-4I  are cross-sectional views showing the steps of forming a chip package in accordance with an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
     It should be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numbers and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Furthermore, descriptions of a first layer “on,” “overlying,” (and like descriptions) a second layer, include embodiments where the first and second layers are in direct contact and those where one or more layers are interposing the first and second layers. 
       FIGS. 1A-1I  are cross-sectional views showing the steps of forming a chip package in accordance with an embodiment of the present invention. As shown in  FIG. 1A , a carrier  110  is provided, and the carrier  110  has two opposite surfaces  112  and  114 . The carrier  110  includes resin, polytetrafluoroethene or other materials suitable for support of electronic components. 
     In one embodiment, conductive layers  122  and  124  are formed on the surfaces  112  and  114 , respectively. A circuit layer  130  is formed on the conductive layer  122  by, for example, performing an electroplating process, a photolithography process and an etching process. In one embodiment, a conductive layer  140  is formed on a portion of the circuit layer  130  whereon conductive vias will be formed in subsequent processes. The conductive layer  140  is formed by, for example, performing an electroplating process, a photolithography process and an etching process. The conductive layers  122  and  124 , the circuit layer  130  and the conductive layer  140  include copper or other suitable conductive materials. 
     As shown in  FIG. 1B , a first dielectric material layer  150  and an adhesive layer  160  are provided. The adhesive layer  160  is disposed on the first dielectric material layer  150 . The first dielectric material layer  150  has a cavity  152  exposing a portion of the adhesive layer  160 . The first dielectric material layer  150  includes resin or other suitable dielectric materials. The adhesive layer  160  includes epoxy or other suitable adhesive materials. 
     Thereafter, as shown in  FIG. 1C , a passive component  170  is disposed in the cavity  152  to be adhered on the adhesive layer  160 . The passive component  170  includes a capacitor, an inductor, a resistor or other suitable passive components. In one embodiment, the passive component  170  is a capacitor, and the passive component  170  has electrode pads  172  and  174  disposed at two opposite ends thereof, respectively. 
     Afterwards, as shown in  FIG. 1D , a second dielectric material layer  180  is formed on the conductive layer  122  and is adjacent to the circuit layer  130 . Specifically, the circuit layer  130  is embedded in the second dielectric material layer  180 . The second dielectric material layer  180  has the same material as the first dielectric material layer  150 . Then, a conductive layer  190 , the adhesive layer  160 , the first dielectric material layer  150  and the passive component  170  are stacked on the carrier  110 . The conductive layer  190  includes copper or other suitable conductive materials. 
     Thereafter, as shown in  FIG. 1E , a lamination process is performed to combine the first dielectric material layer  150  with the second dielectric material layer  180  so as to form a dielectric layer  210 . The dielectric layer  210  is, for example, an integral layer includes the same material as the first dielectric material layer  150  (or the second dielectric material layer  180 ). The dielectric layer  210  fills the gaps between the passive component  170 , the first dielectric material layer  150 , the second dielectric material layer  180 , the circuit layer  130  and the conductive layer  140  (as shown in  FIG. 1D ). 
     Therefore, the passive component  170 , the circuit layer  130  and the conductive layer  140  are embedded in the dielectric layer  210 . In one embodiment, the passive component  170 , the circuit layer  130  and the conductive layer  140  are in direct contact with the dielectric layer  210 . Since the dielectric layer  210  and the circuit layer  130  are both formed on a surface S of the conductive layer  122 , a surface  212  of the dielectric layer  210  is aligned with a surface  132  of the circuit layer  130 . The adhesive layer  160  is disposed on a surface  214  of the dielectric layer  210 , and the surface  214  is opposite to the surface  212 . Furthermore, the conductive layer  190  is adhered onto the adhesive layer  160 . 
     Afterwards, as shown in  FIGS. 1E and 1F , holes T 1  and T 2  are formed by, for example, a laser drilling process. The holes T 1  pass through the conductive layer  190 , the adhesive layer  160  and the dielectric layer  210 . The holes T 2  pass through the conductive layer  190  and the adhesive layer  160 . Then, a conductive layer (not shown) is formed on the conductive layer  190  by, for example, an electroplating process, and the conductive layer fills the holes T 1  and T 2  to form conductive vias V 1 , V 2  and V 3 . It should be noted that the aspect ratio of the holes T 1  is reduced by the conductive layer  140 , which helps the conductive layer to fill the holes T 1 . 
     Thereafter, the conductive layer  190  and the conductive layer formed thereon are patterned to form circuit layers  190   a  and  220  on the surface  214  of the dielectric layer  210 . The patterning process includes, for example, a photolithography process and an etching process. Each of the conductive vias V 1  passes through the circuit layer  190   a , the adhesive layer  160  and the dielectric layer  210  and is electrically connected to the circuit layers  190   a  and  220 , the conductive layer  140  and the circuit layer  130 . 
     The conductive via V 2  passes through the circuit layer  190   a  and the adhesive layer  160  and is electrically connected to the circuit layers  190   a  and  220  and the electrode pad  172  of the passive component  170 . The conductive via V 3  passes through the circuit layer  190   a  and the adhesive layer  160  and is electrically connected to the circuit layers  190   a  and  220  and the electrode pad  174  of the passive component  170 . 
     In some other embodiments (not shown), the manufacturing processes performed on the conductive layer  122  are also performed on the conductive layer  124  to form the same structure as that formed on the conductive layer  122 . Therefore, the carrier  110  may be used to fabricate (or support) two package substrates simultaneously. 
     Afterwards, as shown in  FIG. 1G , the carrier  110  and the conductive layer  124  are removed. Holes T 3  are formed to pass through the conductive layer  122 , the circuit layer  130  and the dielectric layer  210  by, for example, a laser drilling process. Then, a conductive layer  230  is formed on the conductive layer  122  by, for example, an electroplating process, and the conductive layer  230  fills the holes T 3  to form conductive vias V 4  and V 5 . As shown in  FIG. 1H , the conductive layers  122  and  230  are patterned to form circuit layers  122   a  and  230   a . In this step, a package substrate  100  is substantially formed. 
     As shown in  FIG. 1I , the package substrate  100  is flipped up. In one embodiment, a chip  240  is bonded onto the circuit layer  230   a  via conductive bumps  242  formed under the chip  240 . The chip  240  is electrically connected to the passive component  170  through the circuit layer  230   a  and the conductive vias V 4  and V 5 . The chip  240  is located on the surface  212  of the dielectric layer  210 . 
     A molding process is optionally performed to form an encapsulating layer  250  on the package substrate  100  and covering (or encapsulating) the chip  240 . The encapsulating layer  250  includes epoxy, acrylate, urethane acrylate or other suitable encapsulating materials. Solder balls (or conductive bumps)  260  are formed on the circuit layer  220 . The solder balls include tin or other suitable solder materials. In this step, a chip package  100 A of the present embodiment is substantially formed. 
     In the present embodiment, a lamination process is performed to embed the passive component  170  into the dielectric layer  210  so as to form the package substrate  100 , and therefore the package substrate  100  of the present embodiment does not need to use a core layer. Therefore, the present embodiment may reduce the manufacturing cost of package substrates and chip packages. 
       FIGS. 2A-2I  are cross-sectional views showing the steps of forming a chip package in accordance with an embodiment of the present invention. It should be noted that some of the elements of  FIGS. 2A-2I  are the same as or similar to those of  FIGS. 1A-1I , and therefore same or similar reference numbers are used to designate same or similar elements. A detailed description of elements that are the same or similar to those in  FIGS. 1A-1I  is not repeated herein. 
     As shown in  FIG. 2A , a carrier  110 , conductive layers  122  and  124 , a circuit layer  130  and a conductive layer  140  are provided. The conductive layer  122 , the circuit layer  130  and the conductive layer  140  are stacked on a surface  112  of the carrier  110  sequentially. The conductive layer  124  is disposed on a surface  114  of the carrier  110 . 
     Thereafter, as shown in  FIG. 2B , an adhesive layer  270  is formed on the conductive layer  122  by, for example, a printing process or a dispensing process. The adhesive layer  270  includes insulating materials, such as epoxy or other suitable adhesive materials. Afterwards, as shown in  FIG. 2C , a passive component  170  is disposed on the adhesive layer  270  to be adhered on the carrier  110 . In one embodiment, the passive component  170  has electrode pads  172  and  174  disposed at two opposite ends thereof, respectively. 
     As shown in  FIG. 2D , a conductive layer  190  and a dielectric material layer  280  are stacked on the carrier  110 . The dielectric material layer  280  has a cavity  282  facing the passive component  170 . The dielectric material layer  280  includes resin or other suitable dielectric materials. 
     As shown in  FIG. 2E , a lamination process is performed to melt the dielectric material layer  280  so as to form a dielectric layer  280   a . The dielectric layer  280   a  fills the gaps between the passive component  170 , the dielectric material layer  280 , the circuit layer  130 , the conductive layer  140  and the adhesive layer  270  (as shown in  FIG. 2D ). Therefore, the passive component  170 , the circuit layer  130 , the conductive layer  140  and the adhesive layer  270  are embedded in the dielectric layer  280   a.    
     In one embodiment, the passive component  170 , the circuit layer  130 , the conductive layer  140  and the adhesive layer  270  are in direct contact with the dielectric layer  280   a . Since the dielectric layer  280   a , the adhesive layer  270  and the circuit layer  130  are formed on a surface S of the conductive layer  122 , a surface  282   a  of the dielectric layer  280   a , a surface  272  of the adhesive layer  270  and a surface  132  of the circuit layer  130  are aligned with each other. Furthermore, the conductive layer  190  is pressed onto the dielectric layer  280   a.    
     Afterwards, as shown in  FIGS. 2E and 2F , holes T 1  and T 2  are formed by, for example, a laser drilling process. The holes T 1  and T 2  pass through the conductive layer  190  and the dielectric layer  280   a . Then, a conductive layer (not shown) is formed on the conductive layer  190  by, for example, an electroplating process, and the conductive layer fills the holes T 1  and T 2  to form conductive vias V 1 , V 2  and V 3 . 
     Thereafter, the conductive layer  190  and the conductive layer formed thereon are patterned to form circuit layers  190   a  and  220 . The patterning process includes, for example, a photolithography process and an etching process. Each of the conductive vias V 1  passes through the circuit layer  190   a  and the dielectric layer  280   a  and is electrically connected to the circuit layers  190   a  and  220 , the conductive layer  140  and the circuit layer  130 . 
     The conductive via V 2  passes through the circuit layer  190   a  and the dielectric layer  280   a  and is electrically connected to the circuit layers  190   a  and  220  and the electrode pad  172  of the passive component  170 . The conductive via V 3  passes through the circuit layer  190   a  and the dielectric layer  280   a  and is electrically connected to the circuit layers  190   a  and  220  and the electrode pad  174  of the passive component  170 . 
     Afterwards, as shown in  FIG. 2G , the carrier  110  and the conductive layer  124  are removed. Holes T 3  are formed to pass through the conductive layer  122 , the circuit layer  130  and the adhesive layer  270  by, for example, a laser drilling process. Then, a conductive layer  230  is formed on the conductive layer  122  by, for example, an electroplating process, and the conductive layer  230  fills the holes T 3  to form conductive vias V 4  and V 5 . As shown in  FIG. 2H , the conductive layers  122  and  230  are patterned to form circuit layers  122   a  and  230   a . In this step, a package substrate  200  is substantially formed. 
     As shown in  FIG. 2I , the package substrate  200  is flipped up. In one embodiment, a chip  240  is bonded onto the circuit layer  230   a  via conductive bumps  242  formed under the chip  240 . The chip  240  is electrically connected to the passive component  170  through the circuit layer  230   a  and the conductive vias V 4  and V 5 . A molding process is optionally performed to form an encapsulating layer  250  on the package substrate  200  and covering (or encapsulating) the chip  240 . Solder balls (or conductive bumps)  260  are formed on the circuit layer  220 . In this step, a chip package  200 A of the present embodiment is substantially formed. 
       FIGS. 3A-3I  are cross-sectional views showing the steps of forming a chip package in accordance with an embodiment of the present invention. It should be noted that some of the elements of  FIGS. 3A-3I  are the same as or similar to those of  FIGS. 1A-1I  and  FIGS. 2A-2I , and therefore same or similar reference numbers are used to designate same or similar elements. A detailed description of elements that are the same or similar to those in  FIGS. 1A-1I  and  FIGS. 2A-2I  is not repeated herein. 
     As shown in  FIG. 3A , a carrier  110 , conductive layer  122 , a circuit layer  130  and conductive pillars  310  are provided. The conductive layer  122 , the circuit layer  130  and the conductive pillars  310  are stacked on a surface  112  of the carrier  110  sequentially. The conductive pillars  310  are disposed on the circuit layer  130  and are configured to be conductive vias of a chip package subsequently formed. The conductive pillars  310  include copper or other suitable conductive materials. The conductive pillars  310  are formed by, for example, an electroplating process. 
     Thereafter, as shown in  FIG. 3B , an adhesive layer  270  is formed on the conductive layer  122  by, for example, a printing process or a dispensing process. The adhesive layer  270  includes epoxy or other suitable adhesive materials. Afterwards, as shown in  FIG. 3C , a passive component  170  is disposed on the adhesive layer  270  to be adhered on the carrier  110 . In one embodiment, the passive component  170  has electrode pads  172  and  174  disposed at two opposite ends thereof, respectively. 
     As shown in  FIG. 3D , a pre-molding process is performed to form a dielectric layer  320  on the conductive layer  122  (or the carrier  110 ) so as to cover the passive component  170 , the circuit layer  130  and the adhesive layer  270 . The dielectric layer  320  includes epoxy, acrylate, urethane acrylate or other suitable encapsulating materials. The passive component  170 , the circuit layer  130 , the conductive pillars  310  and the adhesive layer  270  are embedded in the dielectric layer  320 . In one embodiment, the passive component  170 , the circuit layer  130 , the conductive pillars  310  and the adhesive layer  270  are in direct contact with the dielectric layer  320 . 
     Since the dielectric layer  320 , the adhesive layer  270  and the circuit layer  130  are formed on a surface S of the conductive layer  122 , a surface  324  of the dielectric layer  320 , a surface  272  of the adhesive layer  270  and a surface  132  of the circuit layer  130  are aligned with each other. In one embodiment, the dielectric layer  320  covers top surfaces  312  of the conductive pillars  310 , and therefore a grinding process is performed to remove the portion of the dielectric layer  320  covering the top surfaces  312  so as to expose the top surfaces  312 . 
     As shown in  FIG. 3E , holes T 2  are formed to pass through the dielectric layer  320 . In one embodiment, an electroless plating process is performed to form a seed layer  330  on a surface  322  of the dielectric layer  320  and sidewalls of the holes T 2 . The seed layer  330  includes copper or other suitable conductive materials. Thereafter, a conductive layer  220  is formed on the seed layer  330  by, for example, an electroplating process. The conductive layer  220  fills the holes T 2  to form conductive vias V 2  and V 3 . 
     Afterwards, as shown in  FIGS. 3E and 3F , the seed layer  330  and the conductive layer  220  are patterned to form a circuit layer  220   a . The patterning process includes, for example, a photolithography process and an etching process. The circuit layer  220   a  is electrically connected to the conductive pillars  310 . 
     The conductive via V 2  passes through the dielectric layer  320  and is electrically connected to the circuit layer  220   a  and the electrode pad  172  of the passive component  170 . The conductive via V 3  passes through the dielectric layer  320  and is electrically connected to the circuit layer  220   a  and the electrode pad  174  of the passive component  170 . 
     Afterwards, as shown in  FIG. 3G , the carrier  110  is removed. Holes T 3  are formed to pass through the conductive layer  122 , the circuit layer  130  and the adhesive layer  270  by, for example, a laser drilling process. Then, a conductive layer  230  is formed on the conductive layer  122  by, for example, an electroplating process, and the conductive layer  230  fills the holes T 3  to form conductive vias V 4  and V 5 . As shown in  FIG. 3H , the conductive layers  122  and  230  are patterned to form circuit layers  122   a  and  230   a . In this step, a package substrate  300  is substantially formed. 
     As shown in  FIG. 3I , the package substrate  300  is flipped up. In one embodiment, a chip  240  is bonded onto the circuit layer  230   a  via conductive bumps  242  formed under the chip  240 . The chip  240  is electrically connected to the passive component  170  through the circuit layer  230   a  and the conductive vias V 4  and V 5 . 
     A molding process is optionally performed to form an encapsulating layer  250  on the package substrate  300  and covering (or encapsulating) the chip  240 . The encapsulating layer  250  includes epoxy, acrylate, urethane acrylate or other suitable encapsulating materials. In one embodiment, the encapsulating layer  250  and the dielectric layer  320  have the same material. Solder balls (or conductive bumps)  260  are formed on the circuit layer  220   a . In this step, a chip package  300 A of the present embodiment is substantially formed. 
     In the present embodiment, a pre-molding process is performed to embed the passive component  170  into the dielectric layer  320  so as to form the package substrate  300 , and therefore the package substrate  300  of the present embodiment does not need to use a core layer. Therefore, the present embodiment may reduce the manufacturing cost of package substrates and chip packages. 
       FIGS. 4A-4I  are cross-sectional views showing the steps of forming a chip package in accordance with an embodiment of the present invention. It should be noted that some of the elements of  FIGS. 4A-4I  are the same as or similar to those of  FIGS. 1A-1I ,  FIGS. 2A-2I  and  FIGS. 3A-3I , and therefore same or similar reference numbers are used to designate same or similar elements. A detailed description of elements that are the same or similar to those in  FIGS. 1A-1I ,  FIGS. 2A-2I  and  FIGS. 3A-3I  is not repeated herein. 
     As shown in  FIG. 4A , a carrier  110 , conductive layer  122 , a circuit layer  130  and conductive pillars  310  are provided. The conductive layer  122 , the circuit layer  130  and the conductive pillars  310  are stacked on a surface  112  of the carrier  110  sequentially. The conductive pillars  310  are disposed on the circuit layer  130  and are configured to be conductive vias of a chip package subsequently formed. The conductive pillars  310  include copper or other suitable conductive materials. The conductive pillars  310  are formed by, for example, an electroplating process. 
     Thereafter, as shown in  FIG. 4B , an adhesive layer  410  is formed on the circuit layer  130  by, for example, a printing process. The adhesive layer  410  includes a solder paste including tin (Sn) or other suitable conductive materials. 
     Afterwards, as shown in  FIG. 4C , a passive component  170  is disposed on the adhesive layer  410  to be adhered on the carrier  110  (or the circuit layer  130 ). In one embodiment, after disposing the passive component  170 , a reflow process is performed to help the adhesive layer  410  to adhere to the passive component  170  and the circuit layer  130 . In one embodiment, the passive component  170  has electrode pads  172  and  174  disposed at two opposite ends thereof, respectively. The electrode pads  172  and  174  are connected to the adhesive layer  410 , respectively. 
     As shown in  FIG. 4D , a pre-molding process is performed to form a dielectric layer  320  on the conductive layer  122  (or the carrier  110 ) so as to cover the passive component  170 , the circuit layer  130  and the adhesive layer  410 . The passive component  170 , the circuit layer  130 , the conductive pillars  310  and the adhesive layer  410  are embedded in the dielectric layer  320 . In one embodiment, the passive component  170 , the circuit layer  130 , the conductive pillars  310  and the adhesive layer  410  are in direct contact with the dielectric layer  320 . 
     In one embodiment, the dielectric layer  320  covers top surfaces  312  of the conductive pillars  310 , and therefore a grinding process is performed to remove the portion of the dielectric layer  320  covering the top surfaces  312  so as to expose the top surfaces  312 . 
     As shown in  FIG. 4E , holes T 2  are formed to pass through the dielectric layer  320 . In one embodiment, an electroless plating process is performed to form a seed layer  330  on a surface  322  of the dielectric layer  320  and sidewalls of the holes T 2 . The seed layer  330  includes copper or other suitable conductive materials. Thereafter, a conductive layer  220  is formed on the seed layer  330  by, for example, an electroplating process. The conductive layer  220  fills the holes T 2  to form conductive vias V 2  and V 3 . 
     Afterwards, as shown in  FIGS. 4E and 4F , the seed layer  330  and the conductive layer  220  are patterned to form a circuit layer  220   a . The patterning process includes, for example, a photolithography process and an etching process. The circuit layer  220   a  is electrically connected to the conductive pillars  310 . 
     The conductive via V 2  passes through the dielectric layer  320  and is electrically connected to the circuit layer  220   a  and the electrode pad  172  of the passive component  170 . The conductive via V 3  passes through the dielectric layer  320  and is electrically connected to the circuit layer  220   a  and the electrode pad  174  of the passive component  170 . 
     Afterwards, as shown in  FIG. 4G , the carrier  110  is removed. As shown in  FIG. 4H , the conductive layer  122  is patterned to form a circuit layer  122   a . In this step, a package substrate  400  is substantially formed. As shown in  FIG. 4I , the package substrate  400  is flipped up. In one embodiment, a chip  240  is bonded onto the circuit layer  230   a  via conductive bumps  242  formed under the chip  240 . The chip  240  is electrically connected to the passive component  170  through the circuit layer  230   a  and  122   a  and the adhesive layer  410 . 
     A molding process is optionally performed to form an encapsulating layer  250  on the package substrate  400  and covering (or encapsulating) the chip  240 . Solder balls (or conductive bumps)  260  are formed on the circuit layer  220   a . In this step, a chip package  400 A of the present embodiment is substantially formed. 
     In view of the foregoing, in the present invention, a lamination process or a pre-molding process is performed to embed a passive component into a dielectric layer so as to form a package substrate, and therefore the package substrate of the present invention does not need to use a core layer. Therefore, the present invention may reduce the manufacturing cost of package substrates and chip packages. 
     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.