Abstract:
The present invention discloses a delay locked loop including: a frequency doubler for increasing the output frequency from an input buffer for buffering a clock; a variable delay line for delaying the output from the frequency doubler; a divider for restoring the output frequency from the variable delay line to the frequency of the clock by dividing the output frequency; an output buffer for buffering the output from the divider; a replica for delaying the output from the variable delay line; a phase detector for detecting a phase difference between the output from the replica and the output from the frequency doubler; and a control circuit for determining a delay amount of the variable delay line according to the output from the phase detector.

Description:
[0001]     This application relies for priority upon Korean Patent Application No. 2004-0027087 filed on Apr. 20, 2004, the contents of which are herein incorporated by reference in their entirety.  
       BACKGROUND  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a delay locked loop (DLL), and more particularly to, a DLL which can remove a skew of a clock and an output data in a read operation of a double data rate synchronous DRAM (DDR SDRAM).  
         [0004]     2. Discussion of Related Art  
         [0005]     In general, a clock is used as a reference for adjusting an operational timing in a system or circuit, and also used to perform a faster operation without errors. When an external clock is used inside the system or circuit, a time delay (clock skew) occurs by inside circuits. A DLL compensates for the time delay, so that an internal clock can have the same phase as that of the external clock.  
         [0006]     The essential factors of the DLL include a small area, a small jitter and a fast locking time, which are performances required by a future semiconductor memory device characterized by a low voltage high speed operation. However, the conventional arts satisfy only part of the factors, or restrict the low voltage high speed operation.  
         [0007]     On the other hand, the DLL is less influenced by noises than a phase locked loop (PLL), and thus is widely employed for a synchronous semiconductor memory device such as a DDR SDRAM. Especially, a register controlled DLL has been generally used. The disadvantages of the conventional register controlled DLL will now be explained.  
         [0008]      FIG. 1  is a block diagram illustrating the conventional register controlled DLL.  
         [0009]     An input buffer  101  buffers external clocks CLK and /CLK. A variable delay line  102  delays the buffered external clocks CLK and /CLK. A replica  105  is modeled to have the same delay time as an access time (tAC) path. A phase detector  103  detects a phase difference between a reference clock ref_clk from the input buffer  101  and a feedback clock fb_clk from the replica  105 . A control circuit  104  determines a delay amount of the variable delay line  102  according to the output from the phase detector  103 . An output buffer  106  generates an internal clock iCLK by buffering the output from the variable delay line  102 .  
         [0010]     The operational range of the DLL is determined by the delay time of the variable delay line  102  and the delay time of the replica  105 . In general, the operational range of the DLL is prescribed by the spec. of the DDR SDRAM, and has the maximum period of 15 ns. Accordingly, the DLL cannot be normally operated in a test apparatus having a clock period over 30 ns in a wafer test. It is thus impossible to perform logic verification relating to the DLL or defect analysis in a wafer level. In addition, the DLL is not operated in the wafer level, and thus the tAC value is not adjusted, which results in a low yield in a package level.  
       SUMMARY OF THE INVENTION  
       [0011]     The present invention is directed to a delay locked loop which can perform a low frequency operation in a wafer level, by reducing a period of an external clock to a half in a chip through a frequency doubler and applying the external clock to inside circuits, and by restoring an output clock to an original frequency through a frequency divider in a preceding terminal of an output buffer.  
         [0012]     One aspect of the present invention is to provide a delay locked loop including: a frequency doubler for increasing the output frequency from an input buffer for buffering a clock; a variable delay line for delaying the output from the frequency doubler; a divider for restoring the output frequency from the variable delay line to the frequency of the clock by dividing the output frequency; an output buffer for buffering the output from the divider; a replica for delaying the output from the variable delay line; a phase detector for detecting a phase difference between the output from the replica and the output from the frequency doubler; and a control circuit for determining a delay amount of the variable delay line according to the output from the phase detector. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]     A more complete understanding of the present invention may be had by reference to the following description when taken in conjunction with the accompanying drawings in which:  
         [0014]      FIG. 1  is a block diagram illustrating a conventional DLL;  
         [0015]      FIG. 2  is a block diagram illustrating a DLL in accordance with a preferred embodiment of the present invention; and  
         [0016]      FIG. 3  is a detailed circuit diagram illustrating a trimming logic unit of  FIG. 2 . 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0017]     A delay locked loop (DLL) in accordance with a preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings and the description to refer to the same or like parts.  
         [0018]      FIG. 2  is a block diagram illustrating the DLL in accordance with the preferred embodiment of the present invention.  
         [0019]     An input buffer  201  buffers external clocks CLK and /CLK. In a test mode, a test mode signal TM_DLL has a high state, and thus a transmission gate  202  is turned on. In the other modes, the test mode signal TM_DLL maintains a low state, and thus a transmission gate  203  is turned on.  
         [0020]     The signal from the transmission gate  202  is increased to, for example, a double frequency by the frequency doubler  204 . The output from the frequency doubler  204  or the signal from the transmission gate  203  is transmitted to the variable delay line  205 . The variable delay line  205  delays the buffered external clocks CLK and /CLK or the buffered and frequency-doubled external clocks CLK and /CLK. The output from the variable delay line  205  is inputted to a replica  208  through a trimming logic unit  209 . The trimming logic unit  209  delays the output from the variable delay line  205  by a predetermined amount. The replica  208  is modeled to have the same delay time as a tAC path. A phase detector  206  detects a phase difference between a reference clock ref_clk from the frequency doubler  204  or the input buffer  201  and a feedback clock fb_clk from the replica  208 . A control circuit  207  determines a delay amount of the variable delay line  205  according to the output from the phase detector  206 .  
         [0021]     When the test mode signal TM_DLL has a high state, a transmission gate  210  is opened, and thus the output from the variable delay line  205  is reduced to, for example, a half by a frequency divider  212 . When the test mode signal TM_DLL has a low state, a transmission gate  211  is opened, and thus the output from the variable delay line  205  is transmitted to an output buffer  213  as it is. The output buffer  213  generates an internal clock iCLK by driving the output from the variable delay line  205  or the output from the frequency divider  212 .  
         [0022]     In accordance with the present invention, in order to guarantee locking of the DLL at a low frequency, the frequency of the input clock is increased to, for example, a double frequency by the frequency doubler  204 . The doubled frequency of the input clock is restored to an original frequency by the frequency divider  212 . Here, doubling and division of the frequency are executed when the test mode signal TM_DLL has a high level, namely in a wafer state, which does not influence real applications.  
         [0023]      FIG. 3  is a detailed circuit diagram illustrating the trimming logic unit of  FIG. 2 .  
         [0024]     The trimming logic unit includes a unit delay cell array  301 , a decoder  302  and a logic circuit  303 . The unit delay cell array  301  has a plurality of unit cells UDC 0  to UDC 8 . For example, the decoder  302  outputs eight decoded signals according to three input signals. The logic circuit  303  has a plurality of unit logic circuits  303   a  to  303   c.    
         [0025]     The unit logic circuits  303   a  to  303   c  have the same structure, and thus the structure and operation of the unit logic circuit  303   a  will now be explained.  
         [0026]     A fuse F 0  is coupled between a power terminal Vcc and a node N 0 . A capacitor C 0  is coupled between the node N 0  and a ground terminal. An inverter I 0  is coupled between the node N 0  and an output terminal S 0 . An NMOS transistor Q 0  operated according to a potential of the output terminal S 0  is coupled between the node N 0  and the ground terminal. When the fuse F 0  is cut, the output terminal S 0  has a high state. When the output terminal S 0  has a high state, the transistor Q 0  is turned on, and thus the node N 0  has a low state. Therefore, when the node N 0  has a low state, the output terminal S 0  is latched in a high state. When the fuse F 0  is coupled, charges are charged in the capacitor C 0 , the node N 0  has a high state, and thus the output terminal S 0  which is the output from the inverter I 0  has a low state.  
         [0027]     When each of the fuses F 0 , F 1  and F 2  of the unit logic circuits  303   a  to  303   c  is cut, a high level signal is outputted, and when each of the fuses F 0 , F 1  and F 2  is coupled, a low level signal is outputted.  
         [0028]     The decoder  302  decodes the three outputs S 0  to S 2  generated in the logic circuit  303 , and outputs eight decode signals D 0  to D 7 .  
         [0029]     The unit delay cells UDC 0  to UDC 8  of the delay cell array  301  have the same structure. The unit delay cells UDC 0  to UDC 8  are dependently coupled between an input terminal IN and an output terminal OUT. That is, the output from the unit delay cell UDC 1  becomes the input of the unit delay cell UDC 2 , and the output from the unit delay cell UDC 2  becomes the input of the unit delay cell UDC 3 . The output from the unit delay cell UDC 3  becomes the input of the unit delay cell UDC 4 , and the output from the unit delay cell UDC 4  becomes the input of the unit delay cell UDC 0 . The output from the unit delay cell UDC 0  becomes the input of the unit delay cell UDC 5 , and the output from the unit delay cell UDC 5  becomes the input of the unit delay cell UDC 6 . The output from the unit delay cell UDC 6  becomes the input of the unit delay cell UDC 7 , and the output from the unit delay cell UDC 7  becomes the input of the unit delay cell UDC 8 . The output from the unit delay cell UDC 8  becomes the final output from the delay cell array  301 .  
         [0030]     The unit delay cell UDC 0  includes three NAND gates. One input terminal of the NAND gate ND 1  is coupled to the input terminal IN, but the other input terminal thereof is coupled to the output terminal D 2  of the decoder  302 . One input terminal of the NAND gate ND 2  is coupled to the output terminal of the preceding unit delay cell UDC 4 , but the other input terminal thereof is coupled to the output terminal of the NAND gate ND 1 . The output from the NAND gate ND 2  is inputted to one input terminal of the NAND gate ND 3 . The other input terminal of the NAND gate ND 3  is coupled to the power terminal Vcc, and the output terminal thereof is coupled to the succeeding unit delay cell UDC 5 .  
         [0031]     Each of the unit delay cells UDC 0  to UDC 8  delays the signal (output from the variable delay line) inputted through the input terminal IN according to the decode signals D 0  to D 7  from the decoder  302 . Here, the delay amount is the same.  
         [0032]     The operation of the trimming logic unit will now be described in detail.  
         [0033]     The levels of the output terminals S 0  to S 2  are determined according to cutting or coupling of the fuses F 0  to F 2  of the unit logic circuits  303   a  to  303   c . The three outputs from the unit logic circuits  303   a  to  303   c  are inputted to the decoder  302 . The decoder  302  outputs the eight decode signals D 0  to D 7  according to the outputs from the unit logic circuits  303   a  to  303   c . If the number of the unit logic circuits of the logic circuit  303  is N, the number of the outputs from the decoder  302  is 2 N .  
         [0034]     In the initial state where the fuses F 0  to F 2  of the unit logic circuits  303   a  to  303   c  are not cut, one output D 0  from the decoder  302  has a high level, and the other outputs D 1  to D 7  have a low level. The output from the variable delay line  205  inputted to the input terminal IN is transmitted to the NAND gate ND 1  of the unit delay cell UDC 0 . Accordingly, the output from the variable delay line  205  sequentially passes through the unit delay cells UDC 0 , D 5  to D 8 , and is delayed for the delay time of the NAND gates ND 2  and ND 3  in each unit delay cell. That is, in the initial state where the fuses F 0  to F 2  of the unit logic circuits  303   a  to  303   c  are not cut, the output from the variable delay line  205  is delayed for a delay time corresponding to a half of the whole delay time of the unit delay cell array  301 . As a result, the tAC value can be freely adjusted.  
         [0035]     As discussed earlier, in accordance with the present invention, the DLL is normally operated in a wafer test device using a low frequency, so that various items of tests relating to the read operation of the DDR SDRAM can be verified in advance in a non-package state. Accordingly, the test time and cost can be reduced, and defect analysis of the chip can be easily performed. Moreover, AC parameters can be measured in the wafer level, and thus various AC parameters such as tAC or tDQSCK can be tuned by using the fuses, which results in a high package yield.  
         [0036]     Although the present invention has been described in connection with the embodiment of the present invention illustrated in the accompanying drawings, it is not limited thereto. It will be apparent to those skilled in the art that various substitutions, modifications and changes may be made thereto without departing from the scope and spirit of the invention.