Abstract:
This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a compressive diffusion barrier material. The barrier material preferably has a compressive stress of greater than 300 MPa. In a preferred dual damascene embodiment of this method, the vias are formed first in the dielectric material, then the planarizing material is deposited in the vias and on the dielectric material, and the barrier material is deposited on the planarizing material. The trenches are then formed lithographically in the imaging material, etched through the barrier material into the planarizing material, and the trench pattern is transferred to the dielectric material. During and following the course of these etch steps, the imaging, barrier and planarizing materials are removed. The resultant dual damascene structure may then be metallized. With this method, the problem of photoresist poisoning by the interlevel dielectric material is alleviated.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
   This application is a continuation-in-part of U.S. patent application Ser. No. 10/604,056 filed Jun. 24, 2003, now U.S. Pat. No. 7,030,031. 

   FIELD OF THE INVENTION 
   This invention relates generally to the manufacture of integrated circuit devices, and more specifically, to the manufacture of single and dual damascene interconnect structures in integrated circuit devices. 
   BACKGROUND OF THE INVENTION 
   Several basic methods for forming a dual damascene structure have been developed. These include the via-first approach, the line-first approach, and various hardmask schemes. All of these methods are fraught with problems. 
   With the via-first approach, the use of photoresist layers on dielectric layers often results in “poisoning” of the line imaging layer which is done after vias are fully or partially etched into the dielectric. This is the case even when bottom anti-reflective coatings are used to fill the vias temporarily, so as to provide a planar surface for the line imaging layer. The source of this poisoning is not clearly understood, but it is thought to be due to absorption and/or generation and liberation of amine compounds from the insulator, as a result of its finite permeability and the use of N 2  and H 2  process gases in the films below, as well as in the etching and stripping of patterns prior to applying the photoresist where the poisoning is observed. The poisoning problem appears to be much worse when the dielectric layer is a low-k insulator applied using chemical vapor deposition (CVD), as compared to silicate glass dielectric layers. This is thought to be a result of the increased permeability of low-k insulators, the use of N 2 O as a carrier gas in some deposition recipes, and the common use of reducing chemistries such as N 2  and H 2  for stripping prior lithographic patterns. 
   Attempts to solve the poisoning problems have been incomplete. One attempt is to use a resist material that is less sensitive to poisoning. However, such resist materials compromise imaging resolution and decrease lithographic process window. Another attempt is to modify the dielectric material so that it causes less poisoning. For example, in U.S. Pat. No. 6,147,009 to Grill et al., the use of N 2 O as an oxidizing carrier gas is avoided by using a siloxane-based precursor and He gas to make low-k SiCOH films, thereby eliminating a source of nitrogen in the as-deposited film. This may prevent poisoning of a first photoresist material on the blanket SiCOH film, but after the pattern is etched into the SiCOH film and the resist is stripped, amines may still be generated and may poison a subsequent photoresist patterning step such as would be required for dual damascene interconnects. In another example, U.S. Published application No. 2001/0036748 by Rutter, Jr. et al. describes a method to eliminate poisoning of photoresist by pretreating the low-k material with acidic compounds. However, such modifications may adversely affect the dielectric constant and other characteristics of the insulating materials. Also, certain underlying dielectric materials such as dielectric barrier caps on underlying Cu levels preferably contain nitrogen and hydrogen, and can be a source of poisoning that might not be easily remedied. Removing the nitrogen compromises the barrier properties, and removing the hydrogen raises the dielectric constant to unacceptable levels. 
   An example of a solution to line resist poisoning in a via-first dual-damascene approach is disclosed in K. Higashi et al., “A manufacturable Copper/Low-k SiOC/SiCN Process Technology for 90 nm-node High Performance eDRAM,” Proc. of IEEE 2002 IITC, June 2002, pp. 15-17. Their practical solution required modifying the resist itself, limiting the polish stop and etch stop (Cu barrier cap) layers to nitrogen-free films, and eliminating use of nitrogen in etch and dielectric deposition chemistries. Even when a spin-on glass (SOG) layer was added between the planarizing and imaging layers (presumably for resist budget during etch), poisoning still occurred through this SOG layer. 
   Another approach with partial success is to deposit a barrier material after via etch. In this approach, the via is lined with a very thin layer of a barrier material such as TEOS or silane SiO 2 , thereby encapsulating the poisoning source. The liner material must have excellent conformality. Since it is difficult to deposit materials in high-aspect ratio vias, this approach may not be extendable to future technologies. Defects in thin regions of this liner may allow poisoning gases to pass through, and even with low statistical occurrence may cause an unacceptable level of defective patterns in the line imaging layer. 
   Another approach that can successfully eliminate poisoning is through the application of multilayer hardmask films such as SiO 2 , Si 3 N 4 , and metal nitrides such as TaN. This concept was first described in U.S. Pat. No. 6,140,226 to Grill et al., and was used successfully by R. D. Goldblatt et al. (“A High Performance 0.13 μm Copper BEOL Technology with Low-k Dielectric,” Proceedings of the IEEE 2000 International Interconnect Technology Conference, pp. 261-263) to pattern SiLK™ low-k polyarylene ether dielectric. (SiLK™ is a registered trademark of the Dow Chemical Company.) These methods are more complex and can be difficult for RIE manufacturing, because the RIE must be able to etch the dielectric with high selectively to the hardmask materials. That in turn may constrain the conditions under which the RIE may operate, and hence may compromise the ability to achieve the desired patterning control in the dielectric film. In the case of non-silicon containing organic polymers such as SiLK™, this is not as difficult to achieve and may be the preferred approach. However, in the case of Si-containing dielectric materials such as SiCOH, it is difficult to obtain high etch selectivity to any common hardmask materials, including metal nitrides. It becomes necessary to modify the conventional RIE chemistries or thicken the hardmask layers to the point where SiCOH pattern integrity is lost. 
   The line-first approach suffers from the difficulty of printing vias inside lines, especially at small dimensions. The reason for this difficulty is that the via imaging layer must planarize above a variety of line trench patterns at different pattern densities, leading to variation in this imaging layer thickness in various structures. It becomes difficult or impossible to define a photolithographic dose and focus process window that can image simultaneously all vias in all line pattern situations. As the via becomes ever smaller in size, it becomes ever more difficult to expose and develop out a via image through the extra thickness of resist that fills in, and becomes planar over, the line structure. Moreover, resist poisoning may continue to be a problem with this approach, as the already-etched line trenches expose the low-k dielectric to the via imaging layer, allowing amines, if present, to escape and poison this imaging layer. 
   Photoresist poisoning is a problem well known in the industry. Others skilled in the art have been unsuccessful in attempts to produce a barrier layer which prevents poisoning but does not damage planarizing material during its deposition. Some have therefore abandoned the via-first method, and are typically using hardmask schemes to circumvent poisoning. For example, the methods described in U.S. Pat. No. 6,316,167 and U.S. Published application No. 2002/0012876 by Angelopoulos et al, the disclosures of which are incorporated herein by reference, use a vapor deposited layer (R:C:H:X) as a multifunctional layer: planarization layer, arc layer, and hardmask layer. The vapor deposited film (R:C:H:X) is said to be compatible with resist, and therefore does not cause poisoning. The vapor deposited layer (R:C:H:X) becomes a permanent film on the device, which necessitates the additional requirement that the layer must also be a low-k material if it is to be used in state of the art devices. It is believed to be ever more difficult to find a material that meets all these requirements. There is currently not a known strip process for this material that would be compatible with patterned low-k dielectrics. Care must be used when selecting films to meet all of these requirements. For example, it has been discovered that some R:C:H:X films prevent poisoning while others do not, depending on the exact nature of the film. 
   In general, circumventing the phenomenon of resist poisoning has placed significant constraints on other elements in the multilevel damascene integration, especially for low-k insulators, that were not the case in previous generations; these constraints are not desired and represent disadvantages. As in the Higashi et al. paper, limitations are placed on choices that do not result in poisoning for the Cu barrier cap, the interlevel dielectric material itself, the etching and stripping chemistries used, the need for caps over the interlevel dielectric, and the choice of the resist imaging layer material itself. It is desirable to decouple the imaging layer from these other integration elements in a manner that does not constrain the choices in those elements, and yet by definition will prevent poisoning. 
   Thus, there remains a need in the art for a method of forming a dual damascene structure which does not suffer from the problems of photoresist poisoning. 
   SUMMARY OF THE INVENTION 
   The problems described above are solved by using the method of this invention. In general, this invention involves a method for forming an etched pattern on a semiconductor substrate. The method comprises the steps of depositing a thin film on the substrate; depositing a layer of planarizing material on the thin film; depositing a layer of barrier material on the layer of planarizing material, wherein the layer of barrier material has a compressive stress of greater than 300 MPa; depositing at least one layer of imaging material on the layer of barrier material; forming at least one first pattern shape in the layers of imaging material, barrier material and planarizing material; removing the imaging material, either after or concurrently with forming the first pattern shape in the planarizing material; transferring the first pattern shape to the thin film; removing the barrier layer, either after or concurrently with transferring the first pattern shape to the thin film; and removing the planarizing material. 
   In a preferred embodiment, the invention involves a via-first method for forming a dual damascene interconnect structure on a semiconductor substrate comprising at least one patterned conductor. The method comprises the steps of: depositing a dielectric material on the substrate; forming at least one via in said dielectric material, such that at least one of the vias is positioned over the patterned conductor; depositing a layer of planarizing material on the dielectric material and in the via; depositing a layer of barrier material on the layer of planarizing material, wherein the layer of barrier material has a compressive stress of greater than 300 MPa; depositing at least one layer of imaging material on the layer of barrier material; forming at least one trench in the layers of imaging material, barrier material and planarizing material, such that at least one of the trenches is positioned over the via; removing the imaging material, either after or concurrently with forming the trench in the planarizing material; transferring the at least one trench to the dielectric material, such that at least one of the trenches is positioned over the via; removing the barrier material, either after or concurrently with transferring the at least one trench to the dielectric material; and removing the planarizing material. 
   In an alternative embodiment, the invention involves a line-first method for forming a dual damascene interconnect structure on a semiconductor substrate comprising at least one patterned conductor. The method comprises the steps of: depositing a dielectric material on the substrate; forming at least one trench in the dielectric material, such that at least one of the trenches is positioned over the patterned conductor; depositing a layer of planarizing material on the dielectric material and in the trench; depositing a layer of barrier material on the layer of planarizing material, wherein the layer of barrier material has a compressive stress of greater than 300 MPa; depositing at least one layer of imaging material on the layer of barrier material; forming at least one via in the layers of imaging material, barrier material and planarizing material, such that at least one of the vias is positioned over the trench and the patterned conductor; removing the imaging material, either after or concurrently with forming the via in the planarizing material; transferring the at least one via to the dielectric material, such that at least one of the vias is positioned over the trench and the patterned conductor; removing the barrier material, either after or concurrently with transferring the at least one via to the dielectric material; and removing the planarizing material. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features of the invention believed to be novel and the elements characteristic of the invention are set forth with particularity in the appended claims. The drawings are for illustration purposes only and are not drawn to scale. Furthermore, like numbers represent like features in the drawings. The invention itself, however, both as to organization and method of operation, may best be understood by reference to the detailed description which follows, taken in conjunction with the accompanying drawings, in which: 
       FIGS. 1-6  illustrate a preferred method of forming a dual damascene structure in accordance with the present invention. 
       FIG. 7  shows weighted defect densities for embedded contamination in each sample measured. 
   

   DETAILED DESCRIPTION 
   The invention will now be described by reference to the accompanying figures. In the figures, various aspects of the structures have been shown and schematically represented in a simplified manner to more clearly describe and illustrate the invention. For example, the figures are not intended to be to scale. In addition, the vertical cross-sections of some of the various aspects of the structures are illustrated as being rectangular in shape. Those skilled in the art will appreciate, however, that with practical structures these aspects will most likely incorporate more tapered features. Moreover, the invention is not limited to constructions of any particular shape. 
   The problem of poisoning described above is solved by depositing a planarizing film on a patterned wafer and then depositing a barrier layer, preferably a low temperature oxide (LTO) film, on top of the planarizing film. Conventional lithographic patterning is performed on top of the LTO film. This invention achieves an advantage by planarizing the wafer, and by using LTO deposition conditions such that no damage is caused to the underlying planarizing film, while still producing an effective film that acts as a diffusion barrier to poisoning. 
   This invention is based on using the combination of a planarizing layer followed by a barrier layer which prevents photoresist poisoning. The use of a planarizing layer circumvents filling an etched pattern such as a deep aspect ratio trench. The preferred planarizing layer has superior planarization performance as well as superior thermal stability compared to many typical resist or arc materials used conventionally to fill vias during dual damascene patterning. These lead to improved manufacturability of fine patterns, as well as the ability to deposit an LTO film at temperatures suitable to achieve good barrier properties. The barrier layer deposited on top of the planarizing layer should be chemically stable, mechanically sound, relatively defect free, should not damage the planarizing layer, and should act as a barrier to photoresist poisoning. 
   A preferred embodiment of the method of this invention is shown in  FIGS. 1-6 , which illustrate use of the invention in a via-first dual damascene approach. In  FIG. 1 , the starting point of the method is a semiconductor substrate  11  having patterned conductors  10  embedded therein. Conductors  10  may be formed of any suitable conducting material, but are preferably formed of copper. A cap layer  12  and an interlevel dielectric (ILD)  13  are deposited on substrate  11  and conductors  10 . The cap layer  12  may be formed of, for example, SiN x or SiCHN. The ILD  13  may be formed of any suitable dielectric material, but is preferably formed of a low-k material, i.e. a material having a dielectric constant less than 3.9, more preferably less than about 3.2. The low-k ILD  13  may be formed of, for example, SiOF (fluorosilicate glass, FSG, F-TEOS, etc.), SiCOH (organosilicate glass, OSG, carbon doped oxide, CDO, etc.) deposited by plasma enhanced chemical vapor deposition (PECVD), or any other suitable inorganic or organic low-k dielectric material. An optional cap  14  may be added above the low-k material  13 ; the cap  14  may be formed of a material such as silane or TEOS oxide, or SiC(N,H) low-k silicon carbide. Vias  15  are patterned using conventional patterning techniques, such as lithography and reactive ion etch (RIE)/strip. Poisoning is not generally encountered during patterning of via  15 , either because the low-k film  13  does not yet contain amines, or because the cap  14  acts as a suitable barrier. 
   Then a planarizing layer  16  is applied. Planarizing layer  16  should fill vias  15  without voids and provide good resistance toward line RIE. Planarizing layer  16  also should be thick enough so that there is a sufficient thickness after RIE to define the line pattern. In addition, the planarization performance of this material should be adequate to limit deviations in surface topography over areas of differing via pattern density, otherwise subsequent high resolution lithographic performance might be compromised due to depth of focus limitations. The thickness of planarizing layer  16  may be expressed as a function of the via height. Specifically, a thickness in the range of about one half the via height to twice that of the via height is preferable. In a preferred embodiment, planarizing layer  16  has a thickness in the range of about 200 nm to about 700 nm for a via size of about 140 nm and a via height of about 600 nm. In a particularly preferred embodiment, planarizing layer  16  has a thickness of about 450 nm, wherein the thickness is about 0.75 that of the via height. 
   The planarizing material  16  is preferably a material such as that used for the underlayer in U.S. application Ser. No. 09/256,034, the disclosure of which is incorporated herein by reference. Specifically, the planarizing material is preferably a poly(hydroxystyrene) (PHS) based system which is a blend of two PHS polymers, a crosslinking agent, and a thermal acid generator (TAG). The preferred PHS polymers are poly(4-hydroxystyrene) and 9-anthracenylmethylated PHS. The preferred crosslinking agent, is tetrahydro-1,3,4,6-tetrakis(methoxymethyl)-imidazo[4,5-d]imidazole-2,5-(1H,3H)-dione, also known as “Powderlink.”The preferred TAG is p-nitrobenzyl tosylate (pNBT). The ratio of the two PHS polymers poly(4-hydroxystyrene) and 9-anthracenylmethylated PHS is preferably 3:7 in this system, but may be adjusted between the ranges of 0:10 to 10:0 to deliver the desired optical properties. The system also comprises about 10 wt % (based on the total polymer weight) of the crosslinking agent and about 5 wt % (based on the total polymer weight) of the TAG. 
   Other materials that may be used as the planarizing material  16  include polyarylsulfones such as the BARL material, polyhydroxystyrene based derivatives, an example being a copolymer of polyhydroxystyrene and polyhydroxystyrene reacted with anthracenemethanol that contains a cross-linker, and acid catalyst (thermal acid generator), polyimides, polyethers, in particular polyarylene ethers, polyarylenesulfides, polycarbonates, epoxies, epoxyacrylates, polyarylenes such as polyphenylenes, polyarylenevinylenes such as polyphenylenevinylenes, polyvinylcarbazole, cyclicolefins, and polyesters. 
   The preferred PHS-based planarizing material is preferably baked at a temperature of about 200° C. to about 250° C., more preferably at about 225° C. 
   Next, diffusion barrier layer  17  is deposited. In one embodiment, barrier layer  17  is low-temperature silicon oxide (LTO) deposited by plasma-enhanced chemical vapor deposition (PECVD) at a temperature of about 100° C. to about 225° C., more preferably about 150° C., using silane and nitrous oxide as deposition sources. (Although N 2 O may be used, poisoning of subsequent imaging layers has been found not to result.) Alternatively, tetraethylorthosilicate (TEOS) and oxygen gas could be used. The thickness of barrier layer  17  is preferably between about 50 and 100 nm in order to act as an effective diffusion barrier. 
   Although LTO deposited by PECVD is preferred, other materials may be used for diffusion barrier layer  17 , so long as their deposition temperature is suitably low to avoid damaging the planarizing layer. For example, a metal or dielectric deposited by physical vapor deposition (sputtering or evaporation) or chemical vapor deposition may be used for diffusion barrier layer  17 . Suitable materials include silicon, silicon nitride, silicon carbide, titanium nitride, and tantalum nitride. The material for layer  17  should be dense enough to perform as a barrier, and layer  17  should be thin enough (e.g., in the case of a metal) to be optically transmissive for lithographic alignment. The diffusion barrier layer may be formed of any material which effectively blocks the diffusion of impurities from the underlying insulator into the photoresist material, such as alkaline impurities which may diffuse into the photoresist and prevent the acid catalysis reaction. It is believed that alkaline impurities such as amines diffuse into the resist and prevent the acid catalysis reaction, and that the LTO layer should act as a barrier to these amines. 
   In another embodiment, diffusion barrier layer  17  has a compressive stress of greater than 300 MPa, more preferably greater than 350 MPa. It has been found that LTO deposited at a lower temperature may be prone to cracking during subsequent processing steps at higher temperature, such as during the lithography rework cycle. These cracks may be transferred into ILD  13  during subsequent etch. By increasing the compressive stress of barrier layer  17  to greater than 300 MPa, such cracks can be prevented. 
   Compressive barrier layer  17  may be formed by any method which results in a compressive stress of greater than 300 MPa. When barrier layer  17  is LTO deposited by PECVD and planarizing layer  16  is the preferred PHS-based planarizing material, the wafer temperature should be no less than about 200° C. to maximize stress and no greater than about 225° C. to avoid decomposition of PHS-based planarizing layer  16 . In general, selection of optimal temperature is dependent on the temperature used to bake planarizing layer  16  prior to deposition of barrier layer  17 . The deposition temperature of barrier layer  17  should not be less than the bake temperature of planarizing layer  16 , and preferably is about 5° C. greater than the planarizing layer bake temperature. The time that the wafer is heated prior to exposure to deposition gases is preferably in the range of about 15-30 seconds, most preferably about 20 seconds. Although the gas used during wafer heat up prior to deposition may be chosen from among several gases such as nitrogen, helium, argon, or nitrous oxide without greatly affecting stress, the preferred ambient is nitrous oxide. The RF plasma power delivered per wafer in the PECVD reactor is preferably in the range of about 150 to 250 Watts, most preferably about 200 Watts. Silane flow per wafer in the reactor is preferably in the range of about 50 to 100 sccm, most preferably about 50 sccm, and nitrous oxide flow per wafer in the reactor is preferably about 2500 to 5000 sccm, most preferably about 4500 sccm. Although pressure and showerhead to wafer spacing do not greatly affect stress, recommended settings are about 1.5 to 3 Torr pressure, most preferably about 2 Torr, and about 400 to 500 mils spacing, most preferably about 450 mils. 
   Photoresist or imaging layer  19  is then deposited, exposed and developed, thereby forming trenches  20 , as shown in  FIG. 1 . An anti-reflective coating (ARC) layer  18  may be deposited prior to depositing imaging layer  19 . Using the patterned photoresist  19  as a mask, ARC  18  and barrier layer  17  are etched as shown in  FIG. 2 , resulting in trench openings  21 . Then planarizing film  16  is etched, thereby forming trench openings  22 , as shown in  FIG. 3 . During the time that planarizing layer  16  is etched, the imaging layer  19  and ARC layer  18  may be removed by concurrent etching, as layers  19 ,  18  and  16  are typically organic layers that etch with similar rates in many etch chemistries. The LTO layer  17  acts as a mask for the etching of planarizing layer  16 . The result is depicted in  FIG. 3 . In a preferred embodiment, a mixture of nitrogen and hydrogen may be used to concurrently etch the PHS-based planarizing layer  16 , imaging layer  19  and ARC layer  18 . 
   In  FIG. 4 , ILD  13  is etched using RIE chemistry, thereby forming trenches  22 . When ILD  13  is SiCOH, the preferred RIE chemistry is Ar/O 2 /CF 4 /CHF 3  and/or any other fluorocarbon such as CH 3 F, CH 2 F 2 , C 2 F 6 , C 4 F 8  and C 5 F 8 . During this RIE step, barrier layer  17  is completely removed, and planarizing layer  16  remains in the field and in the vias. In  FIG. 5 , planarizing layer  16  is selectively stripped, and cap layer  12  is removed from the bottom of the via  15 . When planarizing film  16  is the preferred PHS-based system described above, it may be stripped using, for example, N 2 /H 2 /O 2  chemistry or O 2 /CO chemistry or H 2  chemistry. Cap layer  12  may be removed using, for example, Ar/CF 4 /O 2  chemistry or Ar/CF 4 /CHF 3 /O 2  chemistry. 
   Finally,  FIG. 6  depicts the metallization of the dual damascene via/trench patterns, thereby forming lines  25  and via  26 . Metallization may be performed by, for example, depositing a thin refractory metal liner and Cu seed layer by physical vapor deposition (PVD), filling to excess with electroplated Cu, and then planarizing and removing the excess Cu and liner by chemical-mechanical polishing (CMP). During the CMP step, the cap layer  14  may be removed. In some embodiments layer  14  is not completely removed, but is reduced below its original thickness. In a preferred embodiment, layer  14  is completely removed by CMP. 
   EXAMPLE 1 
   The method herein described was successfully utilized in the production of a 90 nm ground rule integrated circuit chips, using the preferred PHS-based system described above as the planarizing layer  16  and LTO as the barrier layer  17 . The cap layer  12  above underlying Cu conductors  10  was SiCNH, and no post-treatments or covering layers were used so as to prevent amine formation from this layer. Some chips were fabricated with via resist strip etch chemistries that included N 2  and H 2 , with no cleaning step after this strip. This would tend to form amines after subsequent 225° C. bake of the planarizing layer. The absence of resist poisoning was verified through optical and SEM inspection and through electrical test data. It is known that certain structures on the chip are particularly sensitive to resist poisoning, such as isolated vias and the corners of via chain array test structures. All test structures were shown to be completely free of any resist poisoning effects. 
   With the method of this invention, photoresist poisoning is eliminated, and yet conventional lithographic photoresists may be used with no special additives or procedures. This method allows for a wide lithography process window, since the wafer is completely planarized. In other words, there is no need to print vias inside troughs, and no need to print over steps created by hardmasks. Moreover, this method uses conventional RIE gases. No metal hardmask is involved, thus the method is compatible with existing back-end-of-line (BEOL) RIE processes typically used in semiconductor production, and it does not involve new learning of RIE manufacturing techniques associated with metal hardmask. There is also no constraint on nitrogen content of underlying dielectric layers, including Cu barrier caps and the interlevel dielectric itself. The via-first method is inherently simpler for RIE as compared to the multiple hard mask method, because the via etch can be adjusted without affecting trench etch. Most importantly, this method is extendable to future technologies, as new materials are introduced with increased porosity and deceased physical linewidths. 
   In the embodiment described above, the method of this invention is illustrated in the context of a via-first dual damascene approach. The method, however, is equally applicable to other damascene techniques such as a line-first dual damascene approach. 
   EXAMPLE 2 
   The method used in Example 1 was repeated, except that the method used to deposit the LTO layer was modified to alter the stress of this layer and to provide a layer with lower defect density and satisfactory resistance to post deposition lithography rework steps. Specifically, after coating with the planarizing layer, five LTO deposition methods were compared, as follows. 
   For the first sample, the substrate was exposed to a thermal soak in N 2 O at 2500 sccm per wafer for 30 sec. at a temperature of 210° C. before deposition ambient was established. At 210° C., deposition conditions of silane and N 2 O flow, RF power, and pressure were established to provide an oxide layer with a compressive stress of 350 MPa. Silane and N 2 O flow, and RF power (13.56 MHz) were 37 sccm, 4500 sccm, and 200 Watts, respectively per wafer station and pressure was 2 Torr to achieve this compressive stress. 
   For the second sample, the substrate was exposed to a thermal soak in He at 2500 sccm per wafer for 30 sec. at a temperature of 215° C. before deposition ambient was established. At 215° C., deposition conditions of silane and N 2 O flow, RF power, and pressure were established to provide an oxide layer with a compressive stress of 350 MPa. Silane and N 2 O flow, and RF power (13.56 MHz) were 37 sccm, 4500 sccm, and 200 Watts, respectively per wafer station and pressure was 2 Torr to achieve this compressive stress. 
   For the third sample, the substrate was exposed to a thermal soak in He at 2500 sccm per wafer for 30 sec. at a temperature of 235° C. before deposition ambient was established. At 235° C., deposition conditions of silane and N 2 O flow, RF power, and pressure were established to provide an oxide layer with a compressive stress of 350 MPa. Silane and N 2 O flow, and RF power (13.56MHz) were 37 sccm, 4500 sccm, and 200 Watts, respectively per wafer station and pressure was 2 Torr to achieve this compressive stress. 
   For the fourth sample, the substrate was exposed to a thermal soak in He at 2500 sccm per wafer for 10 sec. at a temperature of 200° C. before deposition ambient was established. At 200° C., deposition conditions of silane and N 2 O flow, RF power, and pressure were established to provide an oxide layer with a compressive stress of 270 MPa. Silane and N 2 O flow, and RF power (13.56 MHz) were 75 sccm, 2500 sccm, and 225 Watts, respectively per wafer station and pressure was 2 Torr to achieve this compressive stress. 
   For the fifth sample, multiple substrates were exposed to a thermal soak in N 2 O at 4000 sccm per wafer for 23 sec. at a temperature of 200° C. before deposition ambient was established. At 200° C., deposition conditions of silane and N 2 O flow, RF power, and pressure were established to provide an oxide layer with a compressive stress of 260-330 MPa. Silane and N 2 O flow, and RF power (13.56 MHz) were 140 sccm, 4000 sccm, and 200 Watts, respectively per wafer station and pressure was 2 Torr to achieve this compressive stress. 
   Weighted defect densities for embedded contamination in each sample were measured, and the results are shown in  FIG. 7 . It can be seen that Samples  1 - 4  had lower defect densities than Sample  5 , and Sample  1  had even lower defect density than Samples  2 - 4 . Accordingly, with respect to at least Sample  5 , an oxide layer was thereby provided that could sustain the lithography rework cycle at temperature of 300° C. without causing cracking of the oxide and planarizing layers. Furthermore, using an N 2 O ambient for thermal soaking provided the lowest defect density as observed at subsequent inspection steps. 
   While the present invention has been particularly described in conjunction with a specific preferred embodiment and other alternative embodiments, it is evident that numerous alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. It is therefore intended that the appended claims embrace all such alternatives, modifications and variations as falling within the true scope and spirit of the present invention.