Abstract:
A FIFO memory has integrated error management to react to different errors according to the current state of operation of the input and output as well as internal conditions such as buffer memory status. The FIFO memory completes or aborts current operations according to state and leaves the FIFO memory in known condition following error handling. Thus, data sent to a host avoids data gaps or data overlaps because the FIFO memory leaves operations in a known state before reporting the error to a controller.

Description:
RELATED APPLICATION 
     This application claims priority to U.S. Provisional Application 60/823,210, entitled “COMMUNICATION BETWEEN TWO SIDES OF A FIFO,” filed Aug. 22, 2006, which is hereby incorporated by reference herein in its entirety. 
    
    
     BACKGROUND 
     A FIFO is a specialized dual port memory with an input and an output that operate asynchronously. That is, data can be input at one end of the FIFO at one pace and read from the other end at a different pace. A FIFO is often used when data is received in blocks at one data rate and processed at a steadier, slower rate. One such application is a disk drive interface. 
     The shift register in a FIFO and its supporting control circuitry may all experience failures, separately or in combination. When a failure or an intentional abort occurs, the FIFO may be left in an unknown state, that is, having an uncertain condition of the data being read, data in the transmit register, and data being sent to a host. This may result in duplication of data when data thought to have been lost is incorrectly re-sent. Such errors may also result in gaps when data thought to have been sent was actually lost. 
     SUMMARY 
     A FIFO with integral error management determines the type of error and the state of input and output activity to determine next steps in FIFO error recovery. The error recovery process ensures that error-free processes continue to completion before action is initiated to reset the FIFO and restart operation. A state machine, implemented in a variety of technologies, may be used to manage the error recovery process by determining activities that should be continued or aborted responsive to a particular error. In this way, the FIFO may manage part of the error recovery process before a controller is even notified of the failure. 
     By processing errors to a known conclusion, the controller working in conjunction with the FIFO can be certain of the state of data and recover without duplication or gaps in data transmission. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a simplified and representative block diagram of a disk drive coupled to a host; 
         FIG. 2  is a simplified and representative block diagram of FIFO memory portion of a disk drive; 
         FIG. 3  is a block diagram of a state machine for use in concurrent input/output control of the FIFO memory of  FIG. 2 ; 
         FIG. 4  is a flow chart illustrating a method of processing errors in a FIFO memory; 
         FIG. 5A  is a block diagram of a high definition television that may utilize a FIFO memory such as the FIFO memory of  FIG. 2 ; 
         FIG. 5B  is a block diagram of a vehicle that may utilize a FIFO memory such as the FIFO memory of  FIG. 2 ; 
         FIG. 5C  is a block diagram of a cellular phone that may utilize a FIFO memory such as the FIFO memory of  FIG. 2 ; 
         FIG. 5D  is a block diagram of a set top box that may utilize a FIFO memory such as the FIFO memory of  FIG. 2 ; 
         FIG. 5E  is a block diagram of a media player that may utilize a FIFO memory such as the FIFO memory of  FIG. 2 ; and 
         FIG. 5F  is a block diagram of a voice over IP device that may utilize a FIFO memory such as the FIFO memory of  FIG. 2 . 
     
    
    
     DETAILED DESCRIPTION 
     Although the following text sets forth a detailed description of numerous different embodiments, it should be understood that the legal scope of the description is defined by the words of the claims set forth at the end of this disclosure. The detailed description is to be construed as exemplary only and does not describe every possible embodiment since describing every possible embodiment would be impractical, if not impossible. Numerous alternative embodiments could be implemented, using either current technology or technology developed after the filing date of this patent, which would still fall within the scope of the claims. 
     It should also be understood that, unless a term is expressly defined in this patent using the sentence “As used herein, the teen ‘______’ is hereby defined to mean . . . ” or a similar sentence, there is no intent to limit the meaning of that term, either expressly or by implication, beyond its plain or ordinary meaning, and such term should not be interpreted to be limited in scope based on any statement made in any section of this patent (other than the language of the claims). To the extent that any term recited in the claims at the end of this patent is referred to in this patent in a manner consistent with a single meaning, that is done for sake of clarity only so as to not confuse the reader, and it is not intended that such claim teen by limited, by implication or otherwise, to that single meaning. Finally, unless a claim element is defined by reciting the word “means” and a function without the recital of any structure, it is not intended that the scope of any claim element be interpreted based on the application of 35 U.S.C. §112, sixth paragraph. 
       FIG. 1 , a simplified and representative block diagram of a disk drive  102  coupled to a host  104  is discussed and described. The disk drive  102  may be used for storing relatively large amounts of non-volatile data, meaning the data persists when power is removed from the drive. The disk drive may have fixed or removable media, for example, non-removable ceramic or metallic disks, or may have removable media, such as optical disks like CDs, DVDs, Blu-ray or others. Older and less common removable media include floppy disks of various kinds. While not technically a disk, i.e. rotating media, many kinds of solid state memory may also require buffering of the kind described below and associated with rotating media. The disk drive  102  may be connected to the host  104  by a peripheral bus, such as a serial Advanced Technology Attachment (SATA), Integrated Drive Electronics (IDE/PATA) bus, USB, IEEE 1394 (FireWire), small computer system interface (SCSI)/Ultra Wide SCSI, all known in the art or other wired or wireless communication links. The host  104  may be a computer, mobile computing devices such as personal digital assistants, cellular phones, media or MP3 players, televisions, set-top boxes, automotive dash board electronics, and the like. 
     A common characteristic of rotating media memory and some solid state memory is that the rate at which data arrives may not be compatible with the rate at which data is taken. For example, data read from rotating media may arrive in bursty chunks with pauses in between caused by head relocation. On the other side, data being transferred to a host may be optimally sent in a high-speed continuous stream. 
     The common solution to this kind of mismatch is a first-in first-out (FIFO) memory. Data on the input side is accepted and buffered at one rate and is streamed to the output continuously in the order it is received, that is, the first data received is the first data sent. 
     In the simplified version of the disk drive  102  of  FIG. 1 , showing data read components, the mass storage  106  may be rotating media or relatively slow solid state media. Data from the mass storage  106  may be processed by a signal processing unit  108 , particularly when the signal from the mass storage  106  is an analog signal. The signal processing unit  108  may amplify the analog signal, adjust for DC offset and convert the analog signal to a digital output. 
     The digital output may be presented to a FIFO  110 . The FIFO  110  allows data arriving at one rate from the signal processing unit  108  to be buffered and sent to the host  104  at a different rate. An exemplary FIFO in accordance with the current disclosure is discussed in more detail with regard to  FIG. 2 . 
     A controller  112  may manage operation of the disk drive  102 . The controller  112  may manage head movement, synchronize clock rates, manage control signaling with the host  104  and manage error recovery when a failure occurs in the signal processing unit  108  or FIFO  110 , among other tasks. 
     In operation, the disk drive  102  may receive a request for data at a certain disk location. The controller  112  may translate the disk location to a head location or track number. When signals begin to stream from the mass storage  106 , the signal processing unit  108  may translate analog signals to digital data. The digital data may be stored in the FIFO  110 , formatted according to a protocol associated with the data interface, and sent to the host  104 . 
       FIG. 2  is a simplified and exemplary block diagram of a FIFO  200 , such as the FIFO  110  of  FIG. 1 . While the embodiment of the FIFO  110  of  FIG. 1  is a disk drive, the FIFO  200  may be used in a multitude of applications including parallel to serial data converters or any application transferring data between devices that operate at different speeds or data rates. 
     A data input  201  may load data into a buffer memory  202 . A cyclic redundancy check (CRC) generator  204  may receive data over connection  206  while the same data is sent over connection  208  to multiplexer  211 . The output  212  of the multiplexer  211  couples data to a FIFO register  214 , or transmit buffer, used to hold transmit data. The FIFO register  214  may be a serial in—serial out shift register or may be a parallel in—serial out shift register, or another configuration known in the art. The FIFO register  214  is coupled to an output CRC checker  216  which may in turn be coupled to a frame CRC generator  218 . In some embodiments, a single CRC engine may be used to check the payload CRC and generate the frame CRC value. The frame CRC generator  218  may be coupled to a first input  228  of the multiplexer  224 . A header generator  220  may be coupled to a second input of the multiplexer  224 . Frame data may be output through a host connection  230 . 
     A state machine  232  may be used to manage operation of the components of the FIFO  200 , including error state management. A controller  234  may serve the same function as the controller  112  of  FIG. 1 . In other embodiments, the state machine  232 , or another embodiment performing the functions of the state machine  232 , may be incorporated in the controller  234 . For example, the state machine may be implemented in software, microcode, a programmable array, or the like. 
     In the configuration shown in  FIG. 2 , the controller  234  has a control signal  236  to the state machine  232  and an input  238  from the state machine  232 . Not shown in  FIG. 2 , for the sake of simplicity, are control signal and clock connections with the controller  234  and the state machine  232 . Obvious management functions such as data clocking signals, multiplexer ( 211  and  224 ) switching, and protocol management for the host connection  230 , to name a few, have not been shown, but are assumed. 
     In operation, data may be transferred from a mass storage element, for example, mass storage  106  of  FIG. 1 , to the buffer memory  202 . Data may be clocked in serially or byte-wise. While data is transferred from the buffer memory  202  to the mulitplexer  211 , the input CRC generator  204  may be calculating a CRC result to attach to the data payload being clocked into the FIFO register  214 . After the payload is complete, the mulitplexer  211  may be switched from input  208  to input  210  to allow addition of the CRC to the data payload. The data path  206  may be used to feed data to the input CRC generator  204  or all input data may be routed through the input CRC generator  204 . 
     When the FIFO register  214  is full, that is, has a frame of data including data payload and CRC, data may begin clocking out data. First the CRC calculated at the input CRC generator  204  may be checked at the output CRC checker  216 . If there is no error, a frame CRC may be generated over the entire frame. After setting up a host communication session, a header may be generated and sent over host connection  230  by selecting the input  226  of the mulitplexer  224 . After the header is sent, the data frame may be sent by selecting input  228  of the mulitplexer  224 . After receipt of the data frame, a confirmation may be returned. When successfully received at the host  104 , the confirmation may be an acknowledgement (ACK) message. If the frame is not received in good order the confirmation may be a no acknowledgement (NACK) message. Host connection and transmission errors are discussed in more detail below. After an ACK message, the FIFO  200  may notify the controller  234  that the send process has completed normally. In other embodiments the host protocol management may be managed by the controller  234 . 
     As discussed above, errors may occur at virtually any point in the process. For example, the buffer memory  202  may receive incomplete data or inaccurate data, e.g. data may be presented with a CRC or parity error detected in the buffer memory  202 . The input CRC generator  204  may receive incomplete data or may not match a buffer memory parity bit (if a 9-bit buffer memory is used, for example). A mulitplexer  211  error or clocking error may prevent the FIFO register  214  from receiving complete data, leaving a register bit (not depicted) in an unknown state. The output CRC checker  216  may discover an error, such as one caused by the previous condition. The frame CRC generator  218  may receive incomplete data and generate an error. 
     Errors between the disk drive  102  and the host  104  may include an inability to establish a connection over the host connection  230 . After establishing a connection, a no-acknowledge (NACK) received from the host may indicate data was not received in good order. Another host error may occur when a number of frames of data are sent before an acknowledgement is received for any of the frames sent. When no confirmation (either ACK or NACK) is received during an acknowledgement interval or if the number of unacknowledged frames exceeds a limit, an error may be generated, a so-called ACK-NACK timeout error. The state machine  232  may monitor all possible sources of errors or may monitor only key input and output points. 
       FIG. 3  illustrates the logical inputs and outputs from a state machine  302 , similar to state machine  232  of  FIG. 2 . As mentioned above, the state machine abstraction is used for the purpose of this disclosure, but implementation of the state machine function in combinational logic, software, firmware, microcode, etc. will be obvious to one of ordinary skill based on the disclosure provided herein. 
     The state machine  302  may have exemplary error inputs such as a control signal abort  304 , a buffer memory error  306 , a FIFO register error  308 , an output CRC error  310 , a frame CRC error  312 , a header error  314 , a no-acknowledge (NACK) error  316 , a retry exhausted error  318  (unacknowledged frames), and a connection denied error  320 . This representative set of error inputs does not cover every possible error, but is sufficient to illustrate the operation of the state machine  302 . 
     In addition to error inputs, several inputs may represent device state at any given moment. Exemplary state inputs shown are an input data active input  322 , an output data active input  324 , and a buffer memory empty input  326 . The input data active input  322  may indicate when the buffer memory  202  is active, either receiving data via input  201  or forwarding data via connection  208 . The output data active input  324  may indicate when data is present on the host connection  230 , that is, when data is passing through mulitplexer  224 . The buffer memory empty input  326  indicates that no more data is available in the buffer memory  202 . 
     The outputs from the state machine  302  may include an abort input activity signal  328  and a complete current frame output signal  330 . The abort input activity signal  328  may stop the loading of payload data from the buffer memory  202  to the FIFO register  214 . The complete current frame signal  330  may cause the current data in the FIFO register  214 , including frame CRC and header information to be sent via the host connection  230  and wait until a status is confirmed by the host  104 . The confirmation may be either an ACK or a NACK. An error flag  332  may be used to signal the controller  234  that processing has stopped and, in some embodiments, may indicate the type of error and the current state of operation. A normal completion flag  334  may be used to signal the controller  234  of a normal end of processing. 
     As depicted, all signal lines are shown as single pins for the convenience of illustration. The signals may be expressed over a serial interface, that is, having several bytes of data rather than a single edge sensitivity. Alternatively, the signals may be carried over a bus as data packets representing messages of different types. 
     In general, errors may be categorized by type. The first, an explicit abort  304  from the controller  234 , while not strictly an error, may be handled as an error. The second error type is buffer error  306  at the buffer memory  202 , for example, a parity error. The third error type occurs at the output of the FIFO register  214  and is typified by a CRC error at the output CRC checker  216 . The fourth error type occurs between the disk drive  102  and the host  104  and may be triggered by signals  316 ,  318 , and  320 . 
     When the first error type occurs, for example, when the control signal abort  304  goes active, the state machine  302  may examine the state of the FIFO  200  using input activity input  322  and output activity input  324 . The state of the buffer memory indicated by input  326  is not a factor when handling control signal aborts. The error handling response of the state machine  302  is shown in Table 1. 
     
       
         
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 Input 322 
                 Input 324 
                   
               
               
                 (Input 
                 (Output 
                   
               
               
                 activity) 
                 activity) 
                 Result for First Error Type (Abort) 
               
               
                   
               
             
             
               
                 Active 
                 Inactive 
                 Stop input queuing (set output 328), notify  
               
               
                   
                   
                 controller (set output 332) 
               
               
                 Active 
                 Active 
                 Stop input queuing (set output 328), complete  
               
               
                   
                   
                 output frame (set output 330), then notify  
               
               
                   
                   
                 controller (set output 332) 
               
               
                 Inactive 
                 Active 
                 Complete output frame (set output 330), then  
               
               
                   
                   
                 notify controller (set output 332) 
               
               
                 Inactive 
                 Inactive 
                 When all data sent, ignore abort signal and send a 
               
               
                   
                   
                 normal completion signal (set output 334) 
               
               
                   
               
             
          
         
       
     
     When an error of the second type occurs, for example, a CRC error at the buffer memory  202 , the state machine  302  may respond according to activity status as shown in Table 2. 
     
       
         
               
               
               
             
           
               
                 TABLE 2 
               
               
                   
               
               
                 Input 322 
                 Input 324 
                   
               
               
                 (Input 
                 (Output 
                   
               
               
                 activity) 
                 activity) 
                 Result for Second Error Type (Buffer memory) 
               
               
                   
               
             
             
               
                 Active 
                 Inactive 
                 Stop input queuing (set output 328), notify  
               
               
                   
                   
                 controller (set output 332) 
               
               
                 Active 
                 Active 
                 Stop input queuing (set output 328), complete  
               
               
                   
                   
                 output frame (set output 330), then notify  
               
               
                   
                   
                 controller (set output 332) 
               
               
                 Inactive 
                 Active/ 
                 N/A (if input is inactive, no data is left in buffer 
               
               
                   
                 Inactive 
                 memory, so no type 2 errors will occur) 
               
               
                   
               
             
          
         
       
     
     When an error of the third type occurs, for example, a CRC error at the output of the FIFO register/transmit buffer, the state machine  302  may respond according to activity status as shown in Table 3. This type of error occurs when the FIFO register output is at a natural stopping spot, i.e. at the end of a frame of data. This type of error is usually indicative of a serious hardware failure. 
     
       
         
               
               
               
             
           
               
                 TABLE 3 
               
               
                   
               
               
                 Input 322 
                 Input 324 
                 Result for Third Error Type 
               
               
                 (Input 
                 (Output 
                 (FIFO register output CRC 
               
               
                 activity)  
                 activity) 
                 error) 
               
               
                   
               
             
             
               
                 Active 
                 Inactive 
                 Stop input queuing (set output 328), notify  
               
               
                   
                   
                 controller (set output 332) 
               
               
                 Inactive 
                 Inactive 
                 Notify controller (set output 332) 
               
               
                   
               
             
          
         
       
     
     The fourth type of error, host communication errors, may take several forms. Table 4 shows the error response steps taken by the state machine  302  for the various kinds of host communication errors. When a host confirmation interval is exceeded, a so called ACK/NACK timeout, the FIFO  200  will be at a natural stopping spot on the output side. Similarly, a retry exhausted or no connection error will also occur when the output is at a natural stopping spot. In each of these cases, the only change will be in input status. 
     
       
         
               
               
               
               
             
           
               
                 TABLE 4 
               
               
                   
               
               
                 Input 
                 Input 
                   
                   
               
               
                 322 
                 324 
                   
                   
               
               
                 (Input 
                 (Output 
                   
                 Result for Fourth Error Type (Host 
               
               
                 activity) 
                 activity) 
                 Host error 
                 communication error) 
               
               
                   
               
             
             
               
                 Active 
                 Active 
                 No-acknowledge 
                 Stop input queuing (set output 328), 
               
               
                   
                   
                 (NACK) 
                 complete output frame (set output 
               
               
                   
                   
                   
                 330), then notify controller  
               
               
                   
                   
                   
                 (set output 332) 
               
               
                 Inactive 
                 Active 
                 No-acknowledge 
                 Complete output frame (set output 
               
               
                   
                   
                 NACK 
                 330), then notify controller  
               
               
                   
                   
                   
                 (set output 332) 
               
               
                 Active 
                 Inactive 
                 ACK/NAK 
                 Stop input queuing (set output 328), 
               
               
                   
                   
                 Timeout 
                 notify controller (set output 332) 
               
               
                 Inactive 
                 Inactive 
                 ACK/NAK 
                 Notify controller (set output 332) 
               
               
                   
                   
                 Timeout 
                   
               
               
                 Active 
                 Inactive 
                 Retry Exhausted 
                 Stop input queuing (set output 328), 
               
               
                   
                   
                   
                 notify controller (set output 332) 
               
               
                 Inactive 
                 Inactive 
                 Retry Exhausted 
                 Notify controller (set output 332) 
               
               
                 Active 
                 Inactive 
                 Connection 
                 Stop input queuing (set output 328), 
               
               
                   
                   
                 denied 
                 notify controller (set output 332) 
               
               
                 Inactive 
                 Inactive 
                 Connection 
                 Notify controller (set output 332) 
               
               
                   
                   
                 denied 
               
               
                   
               
             
          
         
       
     
       FIG. 4 , a method  400  of processing errors in a FIFO memory, such as FIFO memory  200 , is discussed and described. At block  402 , an error may be detected in the FIFO  200 . The error may be detected at an input buffer memory  202 , a transmit buffer register  214 , or between the FIFO  200  and a host  104 . 
     At block  404 , the buffer memory  202  may be checked to determine if data is being transferred from the buffer memory  202  to the transmit buffer register  214 . If the input is active, the ‘yes’ branch from block  404  may be taken to block  406 . At block  406  input activity may be stopped and processing continued at block  408 . 
     Processing continues at block  408 , when the input is not active and the ‘no’ branch from block  404  is followed, or after completion of activity at block  406 . At block  408 , the transmit buffer output  230  may be checked to see if data is being transferred to the host, such as host  104  of  FIG. 1 . If, at block  408 , the output is active, the ‘yes’ branch may be followed to block  410  and the frame in progress may be sent. After a confirmation message from the host, either an ACK or a NACK, processing may continue at block  412 . When the confirmation is an ACK, the current frame of data was successfully received at the host. When the confirmation is a NACK, the current frame of data was not successfully received at the host. In either case, the output has reached a natural stopping spot at the end of a frame of data and any activity at the input will have been suspended. 
     Block  412  may be entered via the ‘no’ branch from block  408  or after completion of activity at block  410 . At block  412 , a check may be made to determine if the error is an abort error and if the buffer memory is empty, meaning that the input is inactive and all data has been transferred to the transmit buffer register  214 . If so, the ‘yes’ branch from block  412  may be taken to block  414 . At block  414 , because the final data block will have been sent at block  410  and the FIFO memory  200  will have completed sending all data, the abort error signal may be ignored and a normal exit message may be sent. 
     When the two conditions of block  412  are not met, the ‘no’ branch from block  412  may be taken to block  416 , where an error message may be sent indicating the type of error and current state of the FIFO memory. 
     Because a FIFO memory  200  in accordance with the current disclosure will finish in a known state, a controller  234  associated with the FIFO memory  200  will be able to deal with error conditions confident of the state of data because such a FIFO memory  200  will complete or abort data activity predictably and to completion. The controller  234  can recover the error, if possible, and begin resending data from the exact point where the error occurred, without gaps or duplications, as in prior art FIFO memories. 
     Referring now to  FIGS. 5A-5F , various exemplary implementations of the present invention are shown. Referring now to  FIG. 5A , the present invention may be embodied in a high definition television (HDTV)  420 . The present invention may implement mass data storage  427 , supporting an HDTV signal processing and control block  422 , a WLAN interface  429  and memory  428 . HDTV  420  receives HDTV input signals in either a wired or wireless format and generates HDTV output signals for a display  426 . In some implementations, signal processing circuit and/or control circuit  422  and/or other circuits (not shown) of HDTV  420  may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other type of HDTV processing that may be required. 
     HDTV  420  may communicate with mass data storage  427  that stores data in a nonvolatile manner such as optical and/or magnetic storage devices. At least one mass storage device may have the configuration shown in  FIG. 1 . The mass storage device may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″. HDTV  420  may be connected to memory  428  such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. HDTV  420  also may support connections with a WLAN via a WLAN network interface  429 . 
     Referring now to  FIG. 5B , a control system of a vehicle  430  may include mass data storage  446 , as well as a WLAN interface  448 . In some implementations, the present invention implements a powertrain control system  432  that receives inputs from one or more sensors  436  such as temperature sensors, pressure sensors, rotational sensors, airflow sensors and/or any other suitable sensors and/or that generates one or more output control signals  438  such as engine operating parameters, transmission operating parameters, and/or other control signals. 
     The present invention may also be embodied in other control systems  440  of vehicle  430 . Control system  440  may likewise receive signals from input sensors  442  and/or output control signals to one or more output devices  444 . In some implementations, control system  440  may be part of an anti-lock braking system (ABS), a navigation system, a telematics system, a vehicle telematics system, a lane departure system, an adaptive cruise control system, a vehicle entertainment system such as a stereo, DVD, compact disc and the like. Still other implementations are contemplated. 
     Powertrain control system  432  may communicate with mass data storage  427  that stores data in a nonvolatile manner such as optical and/or magnetic storage devices. At least one mass storage device may have the configuration shown in  FIG. 1 . The mass storage device  446  may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″. Powertrain control system  432  may be connected to memory  447  such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. Powertrain control system  432  also may support connections with a WLAN via a WLAN network interface  448 . The control system  440  may also include mass data storage, memory and/or a WLAN interface (all not shown). 
     Referring now to  FIG. 5C , the present invention may be embodied in a cellular phone  450  that may include a cellular antenna  451 . The cellular phone  450  may include either or both signal processing and/or control circuits, which are generally identified in  FIG. 5C  at  452 , a WLAN interface and/or mass data storage  464  of the cellular phone  450 . In some implementations, cellular phone  450  includes a microphone  456 , an audio output  458  such as a speaker and/or audio output jack, a display  460  and/or an input device  462  such as a keypad, pointing device, voice actuation and/or other input device. Signal processing and/or control circuits  452  and/or other circuits (not shown) in cellular phone  450  may process data, perform coding and/or encryption, perform calculations, format data and/or perform other cellular phone functions. 
     Cellular phone  450  may communicate with mass data storage  464  that stores data in a nonvolatile manner such as optical and/or magnetic storage devices for example hard disk drives HDD and/or DVDs. At least one HDD and/or DVD may have the configuration shown in  FIG. 1 . The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″. Cellular phone  450  may be connected to memory  466  such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. Cellular phone  450  also may support connections with a WLAN via a WLAN network interface  468 . 
     Referring now to  FIG. 5D , the present invention may be embodied in a set top box  480 . The set top box  480  may include either or both signal processing and/or control circuits, which are generally identified in  FIG. 5D  at  484 , a WLAN interface and/or mass data storage  490  of the set top box  480 . Set top box  480  receives signals from a source such as a broadband source and outputs standard and/or high definition audio/video signals suitable for a display  488  such as a television and/or monitor and/or other video and/or audio output devices. Signal processing and/or control circuits  484  and/or other circuits (not shown) of the set top box  480  may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other set top box function. 
     Set top box  480  may communicate with mass data storage  490  that stores data in a nonvolatile manner. Mass data storage  490  may include optical and/or magnetic storage devices for example hard disk drives HDD and/or DVDs. At least one HDD and/or DVD may have the configuration shown in  FIG. 1 . The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″. Set top box  480  may be connected to memory  494  such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. Set top box  480  also may support connections with a WLAN via a WLAN network interface  496 . 
     Referring now to  FIG. 5E , the present invention may be embodied in a media player  500 . The media player  500  may include either or both signal processing and/or control circuits, which are generally identified in  FIG. 5E  at  504 , a WLAN interface and/or mass data storage  510  of the media player  500 . In some implementations, media player  500  includes a display  507  and/or a user input  508  such as a keypad, touchpad and the like. In some implementations, media player  500  may employ a graphical user interface (GUI) that typically employs menus, drop down menus, icons and/or a point-and-click interface via display  507  and/or user input  508 . Media player  500  further includes an audio output  509  such as a speaker and/or audio output jack. Signal processing and/or control circuits  504  and/or other circuits (not shown) of media player  500  may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other media player function. 
     Media player  500  may communicate with mass data storage  510  that stores data such as compressed audio and/or video content in a nonvolatile manner. In some implementations, the compressed audio files include files that are compliant with MP3 format or other suitable compressed audio and/or video formats. The mass data storage may include optical and/or magnetic storage devices for example hard disk drives HDD and/or DVDs. At least one HDD and/or DVD may have the configuration shown in  FIG. 1 . The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″. Media player  500  may be connected to memory  514  such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. Media player  500  also may support connections with a WLAN via a WLAN network interface  516 . Still other implementations in addition to those described above are contemplated. 
     Referring to  FIG. 5F , the present invention may be embodied in a Voice over Internet Protocol (VoIP) phone  550  that may include an antenna  518 . The VoIP phone  550  may include either or both signal processing and/or control circuits, which are generally identified in  FIG. 5F  at  504 , a wireless interface and/or mass data storage of the VoIP phone  550 . In some implementations, VoIP phone  550  includes, in part, a microphone  510 , an audio output  512  such as a speaker and/or audio output jack, a display monitor  514 , an input device  516  such as a keypad, pointing device, voice actuation and/or other input devices, and a Wireless Fidelity (Wi-Fi) communication module  508 . Signal processing and/or control circuits  504  and/or other circuits (not shown) in VoIP phone  550  may process data, perform coding and/or encryption, perform calculations, format data and/or perform other VoIP phone functions. 
     VoIP phone  550  may communicate with mass data storage  502  that stores data in a nonvolatile manner such as optical and/or magnetic storage devices, for example hard disk drives HDD and/or DVDs. At least one HDD and/or DVD may have the configuration shown in  FIG. 1 . The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″. VoIP phone  550  may be connected to memory  506 , which may be a RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. VoIP phone  550  is configured to establish communications link with a VoIP network (not shown) via Wi-Fi communication module  508 .