Abstract:
A high frequency generator including a frequency generator and a multiplier, the multiplier including a diode, which multiplies the output frequency of the frequency generator, and shuts off or reduces an output by suspending or suppressing the multiplying operation through the control of a bias voltage applied to the diode used in the multiplier. The system for cutting off the output by controlling the multiplier is very effective for simplifying the circuit structure and reliably turning off the output.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to a device for generating high frequency signals such as microwave or milliwave signals and particularly to a method of controlling an output of a high frequency generator, including miltiplier means, having diodes, within the output of the generator. 
     High frequency generators, generators used for obtaining predetermined frequency signals by multiplying the outputs from a high frequency oscillator comprising a frequency stabilizing circuit such as Phase Lock Loop (PLL), are known. The high frequency generating means is required to turn the output off for a while after the power switch is turned on, because an abnormal frequency may be generated up until the frequency stabilization reaches a steady state due to the operation of a frequency stabilizing circuit. 
     The output of a high frequency generating means is turned off by the following methods: first, an ON/OFF circuit, such as diode switch using a PIN diode or coaxial relay, is inserted into the output and second, an output is turned off through suspension of operation by changing the bias of an amplifier used in the output circuit. The former method has a disadvantage in that the circuit structure is complicated because an ON/OFF circuit is added and moreover signal loss therein is inevitable. The latter method cannot be applied in a device not having an amplifier. In both of these methods, the output is turned off in the output frequency stage and shielding must be taken into account in order to obtain a large attenuation of the output, resulting in an increase in the device cost. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide means having a simple circuit structure for reliably turning off an output by controlling a bias voltage applied to a mulitplying means, included in a high frequency generating means, comprising an oscillator and a multiplier. 
     Therefore, this invention provides a high frequency generator which is capable of attentuating and turning off the output by forming a multiplier means, connected to the output of an oscillator, having a diode and controlling the bias voltage applied to the diode. 
    
    
     BRIEF DESCRIPTION OF DRAWINGS 
     FIG. 1 is a block diagram of an embodiment of a high frequency generator of the invention; 
     FIG. 2 is a schematic diagram of the multiplier means 6 of FIG. 1; 
     FIG. 3 is a schematic diagram of a second embodiment of the multiplier means 6 of FIG. 1; 
     FIG. 4 is a waveform diagram of the input signal of the multiplier means and the output signal of a step recovery diode; 
     FIG. 5 (a) and (b) are schematic diagrams of the bias voltage controlling means 11 of FIG. 1; and 
     FIG. 6 is a graph of the bias voltage controlling characteristic of the multiplier means 6 of FIG. 1. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 is an embodiment of a high frequency generator of the invention. In FIG. 1, 1 is a voltage controlled oscillator (referred to hereinafter as a VCO). An output of the VCO 1 is applied to a harmonic mixer 2 and is compared with a reference frequency input signal from terminal 3. An error signal output of the harmonic mixer 2 is fed back to the VCO 1 through a loop filter 4, thus forming a phase lock loop (referred to hereinafter as a PLL). An output of the VCO 1 is applied to a multiplier means 6 via a circulator 5, forming an isolator, and is multiplied to provide a high frequency output to the output terminal 7. A monitoring circuit 8 monitors the synchronization of the PLL depending on the output of the loop filter 4. When the detected output of the monitoring circuit becomes OFF, a bias controlling means 11 generates a specified control voltage and the voltage is applied to the multiplier means 6. Thus, the high frequency output of the multiplier means 6 becomes OFF. 
     The PLL circuit comprising the VCO 1, harmonic mixer 2 and loop filter 4, is already known. The oscillation frequency f o  of the VCO 1 is controlled by a signal applied thereto via the loop filter 4. However, since the reference frequency input signal, f R  =f o  /n 1 , having a high frequency stability and generated by a crystal oscillator etc., is applied to the terminal 3, the harmonic mixer 2 compares the phases between the harmonic f o  which is n 1  times the reference frequency signal and an output signal f o  of the VCO 1 and generates an error signal output. The error signal output of the harmonic mixer 2 passes the loop filter 4 and is fed back to the VCO 1 as a high frequency control voltage. Accordingly, control is carried out in the PLL circuit so that the error signal output from the harmonic mixer 2 is close to zero, thereby stabilizing the oscillation frequency of the VCO 1. 
     An oscillation output signal of the VCO 1 is input to the multiplier means 6 via the circulator 5. The circulator 5 is provided to reduce the load effect on the multiplier means 6 When the input frequency f 0  is about 2 GHz, the multiplier means 6 uses a step recovery diode (referred to hereinafter as a SRD) as a semiconductor element and is capable of obtaining the multiplication steps n 2  =4, etc. 
     FIG. 2 is an example of a multiplier means using a step recovery diode. In the figure, 61 is an input terminal and the input signal, for example, f 0  =2 GHz is input thereto. A resonant circuit, 62 resonates with the input signal f 0 . An output of the resonant circuit 62 is supplied to the SRD 64 via a small driving inductance 63 which is equivalently formed by a lead wire. A bias voltage V c  is input to the SRD 64 via the decreasing connector circuit comprising a resistor 65, bypass capacitor 66 and resistor 67. The SRD 64 is provided within a waveguide 68 and a multiplier signal generated by the SRD 64, for example, 4f 0  =8 GHz can be extracted from the waveguide output 69. 
     The step recovery diode changes its equivalent capacitance depending on the bias condition. It has a very small static capacitance C VR  determined by the diode characteristic under a reverse bias condition and a large static capacitance C FWD  under a forward bias condition. Usually, C VR  =0.5 to 5 pF and C FWD  goes to infinity. In the circuit of FIG. 2, the SRD 64 can be alternately biased forward and reverse for each cycle of the input signal f 0  by providing an adequate bias voltage V c . When the SRD 64 is forward biased, energy is accumulated in the driving inductance 63, and when the SRD 64 is reverse biased and the static capacitance is switched from C FWD  to C VR , energy accumulated in the inductance is released. Thus a narrow high frequency pulse is generated across the SRD 64. 
     FIG. 4 shows waveforms of the input signal of multiplier means and the output of the step recovery diode. In the figure, (a) is the waveform of signal f 0  of the input terminal 61, which is almost a sine wave having an amplitude of e 1  and period of T 1 . On the other hand, (b) is the output waveform of the SRD 64 having the same period T 1  and is a sharp pulse. The sharp pulse waveform usually contains harmonics of higher orders and the multiplier means can extract the signal of desired order from the harmonics. In FIG. 2, the waveguide 68 equivalently forming a band-pass filter which resonates at the specified frequency band. For example, only the quadrupled harmonic 4f 0  =8 GHz is selected and extracted through the output terminal 69. In the circuit of FIG. 2, when a high frequency f 0  =2.0 GHz with a level of 20 dBm is input, an output of for example, a higher frequency 4f 0  and a level of, about 15 dBm, is obtained with the bias voltage V c  =0. 
     FIG. 3 is a second circuit structure of multiplier means utilizing a step recovery diode. The circuit is preferred for use in a plane circuit formed with a micro-strip line. In FIG. 3, the portions given the same reference numbers as those of FIG. 2 indicate the same element. 
     In the example of the circut shown in FIG. 3, an idler 70 comprising an LC series circuit having the specified resonant frequency is connected to bias supplying means. The idler 70 functions as a band-reject filter (BRF) and reduces the impedance of the specific frequency near the SRD 64. For example, the input signal f o  =2 GHz sent from the input terminal 61, is input to the SRD 64 and the harmonic signals are extracted and input to the idler 70. The idler 70 is composed of the LC circuits which respectively, resonate at the frequencies of 4 GHz and 6 GHz. The specific frequency signals are reflected and are again input to the SRD 64. Energy of the reflected signals is used for extraction of the specified multiplied frequency signal, for example 4f o  =8 GHz, improving efficiency of operation. 
     The high frequency signal, having passed the idler 70, is input to the resonator circuit 71 in order to extract only the specified multiplied frequency signal. The resonantor circuit 71 allows, for example, only the 4f o  signal=8 GHz to pass and provides the function of a band-pass filter. It functions as the waveguide 69 shown in FIG. 2. The signal obtained from the resonator circuit 71 is output to the output terminal 72. 
     In the high frequency generator shown in FIG. 1, the synchronization of the PLL circuit is monitored by the monitoring circuit 8. It does so by obtaining the synchronous detecting signal from a subtraction output by comparison of the control voltage and reference voltage signal utilizing, for example, that the control voltage is fed back to the VCO 1 via the loop filter 4 and is not in the specified voltage range during the synchronous condition. When a synchronous detecting signal is generated from the monitoring circuit 8, the bias control circuit 11 is controlled and thereby the bias voltage of the multiplier means is changed. FIG. 5 is a circuit diagram of a bias voltage control circuit. FIG. 5 (a) is an example a bias voltage control circuit using a transistor 111. The NPN transistor 111 is in a cut-off condition when an input signal is not applied from an input terminal 112 and therefore a positive voltage is generated at the output terminal 113 from the power source V s  via an resistor 114. When the synchronous detecting signal is applied to the terminal 112, the transistor 111 becomes conductive and its collector voltage becomes approximately 0 V and therefore the output terminal 113 is set to ground potential. Thus, the bias voltage of multiplier means 8 changes. 
     FIG. 5 (b ) is a bias voltage control circuit using a relay in place of a transistor. When there is no input at the terminal 112, the NPN transistor is in the cut-off condition, making the relay 116 inoperative. Therefore, the contact 117 closes and a positive voltage is generated at the output terminal 113 from the power source V s  via the voltage dividing circuit comprising the resistors 118 and 119. When the synchronous detecting signal is applied to the terminal 112, the transistor 115 becomes conductive, the relay 116 operates, the contact 117 opens and the terminal 113 is set to ground potential. 
     Meanwhile, an oscillation output is applied from the VCO 1 to the multiplier means 6 in addition to the bias voltage as explained previously. Therefore, when the bias voltage V c  becomes a higher level than the amplitude of oscillation output signal, the SRD 64 is in the conductive condition, switching between the static capacitances C FWD  and C VR  is no longer performed at the SRD 64, and the multiplication operation stops. In each circuit of FIG. 5, if a negative bias voltage output is obtained when the synchronous detecting signal is not applied and if the bias voltage level is higher than the oscillation amplitude, the SRD 64 is always in the cut-off condition. In the same way, switching between static capacitances C VR  and C FWD  is no longer carried out in the SRD 64 and the multiplication operation stops. The above embodiment is an example of using a step recovery diode as the semiconductor device used in the multiplier means 6, but application is not limited in the present invention only to a step recovery diode. That is, the multiplication efficiency in the multiplier means is changed, depending on the bias voltage, by using other types of diodes. 
     FIG. 6 is a graph of the output reduction characteristic where the bias voltage of the multiplier means is changed. The horizontal axis indicates the bias voltage V c , while the vertical axis indicates reduction of the output of the multiplier means resulting from changes in the bias voltage V c  with reference to Vc=0 (at 0 db). The bias voltage V c  around V c  =0 changes about +0.2 V and the output voltage of the multiplier means changes slightly. In the range of +1 V or more or -2.2 V or less, it has been confirmed that the output voltage of the multiplier means is zero or very small. 
     According to the invention, an output of a high frequency generator comprising generating means and multiplier means including a diode for mutiplying an output frequency of the generating means, can be kept off or the voltage reduced by suspending or suppressing the multiplying operation through the control of the bias voltage of the diode used in the multiplier means. 
     Therefore, according to the microwave generator of the invention, a high frequency output can be cut-off by controlling a generator using the multiplier means. Thus, the circuit structure can be simplified and a sufficiently large output attenuation can be realized by suspending the operation of the multiplier means. From this point of view, the invention is very effective in keeping the output of the device off. 
     In addition, explained in the above embodiment is only a method of controlling a microwave output with the synchronous detecting signal sent from the PLL, but the microwave generator of this invention is also capable of controlling an output signal with a control signal from an external circuit.