Abstract:
Subject matter disclosed herein relates to non-volatile flash memory, and more particularly to a method of reducing stress induced leakage current.

Description:
BACKGROUND 
       [0001]    1. Field: 
         [0002]    Subject matter disclosed herein relates to non-volatile flash memory. 
         [0003]    2. Information: 
         [0004]    Flash memories typically preserve stored information even in power-off conditions. In such memories, in order to change a logic state of a cell, e.g. a bit, an electric charge present in a floating gate of the cell may be changed by application of electric potentials to various portions of the cell. A “0” state typically corresponds to a negatively charged floating gate and a “1” state typically corresponds to a positively charged floating gate. As intended, a non-volatile memory may preserve stored information over time, but a reliability of such a memory may be limited by degenerative processes affecting a tunnel oxide of the memory during various programming and erasing cycles. As a cell is programmed and erased, electrons move to and from the floating gate through the tunnel oxide. Such electrons may create “traps” in the oxide (i.e., defects in the oxide in which electrons may be trapped). Traps created in the tunnel oxide are typically responsible for stress induced leakage current (SILC), which is a leakage current typically observed at relatively low electric fields. Trap density may increase with the number of program and erase cycles experienced by the tunnel oxide. Due to the presence of these traps, a programmed or erased floating gate may, show an enhanced charge loss and/or charge gain even under relatively low electric fields across the tunnel oxide commonly seen during normal conditions of storage and reading of the cell. Such low level charge loss and/or charge gain mechanisms, which may lead to information loss, are undesirable since flash memory devices are expected to be able to store information on the order of at least several years. 
         [0005]    A physical model underlying SILC includes a trap assisted tunnel (TAT) model. A current loss, depending on its direction, may either lead to a charge gain or a charge loss. A charge gain may correspond to information loss for a “1” state, whereas a charge loss may correspond to information loss for a “0” state. In either case, such a logic state determined by charge on a floating gate may be lost, possibly leading to a memory failure. For example, a failure of the “0” state may occur if enough electrons flow from the floating gate to a substrate to reduce a threshold voltage of the memory cell affected by SILC to below a value used to discriminate a “0” state from a “1” state. Such a failure may be called a retention failure. In another example, a failure of the “ 1 ” state may occur on an erased cell belonging to the same word-line of a read cell. Such a cell may suffer a parasitic gate stress, which can induce a tunnel current from the substrate to the floating gate, possibly leading to unwanted programming. Such a condition is called read disturb and may be particularly pronounced on cells affected by SILC. 
         [0006]    SILC is typically dependent on tunnel oxide thickness. SILC may strongly increase for tunnel oxide thicknesses below approximately 10 nm, for example. In addition, SILC strongly depends on the strength of an electric field applied to the tunnel oxide. Accordingly, SILC is a relatively important factor limiting the scaling of tunnel oxide thickness in flash memories. 
     
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
         [0007]    Non-limiting and non-exhaustive embodiments will be described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various figures unless otherwise specified. 
           [0008]      FIG. 1A  is a schematic view of memory cell, according to an embodiment. 
           [0009]      FIG. 1B  is an energy band profile showing a tunneling electron, according to an embodiment. 
           [0010]      FIG. 2  is a flow diagram of a process to reduce charge loss for a memory cell in a memory device, according to an embodiment. 
           [0011]      FIG. 3  is a schematic view of a voltage wave-form to generate dynamic polarization, according to an embodiment. 
           [0012]      FIG. 4A  shows energy band profiles for a memory cell in a “0” state including tunneling and trapped electrons, according to an embodiment. 
           [0013]      FIG. 4B  shows energy band profiles for a memory cell in a “1” state including tunneling and trapped electrons, according to an embodiment. 
           [0014]      FIG. 5  is a graph showing measured cumulative distribution of threshold voltages of a population of memory cell in a “1” state for various polarization duty cycles, according to an embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0015]    Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of claimed subject matter. Thus, the appearances of the phrase “in one embodiment” or “an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in one or more embodiments. 
         [0016]    In an embodiment, a memory cell, which may be in a “1” state or a “0” state, may comprise a portion of a non-volatile memory device. Information may be read from and/or written to a memory cell. If information does not flow to/from a memory cell, such a memory cell may store information, such as during a standby or power off mode. If such a memory cell is operated in a standby or power off mode, the memory cell may be subjected to stress induced leakage current (SILC). Such leakage current may transfer charge into or out of a floating gate of the memory cell, leading to possible loss of stored information in the memory cell. For example, information loss of the “1” state may correspond to an increased charge on the floating gate of the memory cell, whereas information loss of the “0” state may correspond to a decreased charge on the floating gate. In a particular embodiment, a dynamic polarization may be applied via a terminal, such as a control gate, of a memory cell to reduce SILC-induced charge loss. Such a memory cell may be in a “0” state while in a standby mode. Accordingly, such a dynamically polarized memory cell may have improved storage capability. A dynamic polarization, for example, may comprise a polarization having a magnitude that varies with time. Such a polarization may be generated by applying an electric field and/or one or more voltages in a time-varying manner. For example, a voltage having a square-wave form may be applied to a terminal of a memory cell to generate a polarization having a square-wave form. Such a polarization may modify energies of electric charges stored in the memory cell. Accordingly, such a polarization may affect charge migration in portions of the memory cell, as explained below. 
         [0017]      FIG. 1A  is a schematic view of a memory cell  100 , according to an embodiment. Such a memory cell may comprise a body or substrate  110 , such as silicon, that includes doped regions  120 ,  125 , and  130 . For example, doped regions  120  and  130  may comprise source/drain n-doped regions, whereas intervening region  125  may comprise a p-doped channel region. In a particular implementation, doped region  130  may comprise a drain region so that line  170  may act as a bitline to the memory cell, and line  160  may act as a source line. Line  165  may comprise a wordline and/or a control gate controlling a floating gate  140  so that floating gate  140  may be responsive at least in part to voltages applied to control gate  165 . An oxide layer  150  may be disposed between floating gate  140  and channel region  125 . 
         [0018]      FIG. 1B  is an energy band profile  180  showing an electron tunneling through traps  190 , according to an embodiment. A memory cell, such as memory cell  100  shown in  FIG. 1A , may experience an electric field polarity that favors electron tunneling through oxide  150  from substrate  110  to floating gate  140  of the memory cell  100 . It is noted that terms used herein such as favors, favorable, unfavorable, and so on refer to a statistical and probabilistic nature of electron tunneling. Accordingly, favorable implies statistically probable while unfavorable implies statistically improbable, for example. 
         [0019]    Returning to  FIG. 1B , such an energy band profile may result from a voltage difference between a substrate and a floating gate, for example, as will be further explained below. 
         [0020]      FIG. 2  is a flow diagram of a process  200  to reduce charge loss for a memory cell, such as memory cell  100  shown in  FIG. 1A , according to an embodiment. As discussed above, such a charge loss may correspond to a failure probability resulting from SILC of the “0” state of the memory cell. At block  210 , the device may be in a standby mode and memory cell  100  may be in either a “1” state or a “0” state. At block  220 , a first portion of dynamic polarization may be applied via a terminal of memory cell  100 . In a particular embodiment, such dynamic polarization may be applied via a control gate, such as line  165  controlling a floating gate  140 . The first portion of dynamic polarization may be applied by applying a first voltage to the control gate. The first voltage may comprise a constant positive voltage, though in one particular implementation the first voltage may vary. The first voltage may be applied to control gate  165  for a duration T on , after which a second portion of dynamic polarization may be applied via control gate  165 , as at block  230 . In one particular implementation, the second portion of dynamic polarization may be applied by applying a second voltage to the control gate. The second voltage may be smaller than the first voltage, and may be substantially zero volts, for example. The second voltage may be applied to control gate  165  for a duration T off . At block  240 , a determination may be made whether the device is still in standby mode. If not, as in the case where writing and/or reading operations may be applied to memory cell  100  for example, then process  200  may end. Otherwise, a portion of process  200  that includes blocks  220  through  240  may repeat cyclically. 
         [0021]      FIG. 3  is a schematic view of a voltage wave-form  300  for generating dynamic polarization, according to an embodiment. Such dynamic polarization may comprise a pulsed polarization to generate a pulsed electric field between a floating gate and a substrate of a memory cell, for example. Wave-form  300  may include a first voltage  330  having a duration T on  and a second voltage  360  having a duration T off . A portion of wave-form  300  occurring during T on  may be referred to as a T on  phase, whereas a portion of wave-form  300  occurring during T off  may be referred to as a T off phase. Such a waveform may be applied to a terminal, such as a control gate, of a memory cell in a “0” state to decrease a failure probability resulting from SILC. For example, first and second voltages described at blocks  220  and  230  in process  200  may correspond to first and second voltages  330  and  360  of wave-form  300 , respectively. Parameters of a particular memory cell may determine, at least in part, values for first and second voltages  330  and  360 . For example, such parameters may include a thickness of oxide  150  and other dimensions and/or materials of a memory cell. In a particular implementation, a first voltage may include voltages in the order of approximately 1.0 to 10.0 volts, and a second voltage may include voltages in the order of approximately −2.0 to 0.0 volts. Of course such voltages are merely examples, and first and second voltages may include other values as well. Accordingly, claimed subject matter is not limited to voltages mentioned in these examples. In another particular implementation, parameters of a particular memory cell may determine, at least in part, values for T on  and/or T off . For example, such parameters may include a thickness of oxide  150  and other dimensions and/or materials of a memory cell. T on  and/or T off  may include times in the order of approximately 0.1 to 1000 microseconds, for example. Of course such times are merely examples, and claimed subject matter is not so limited. In addition, although voltage wave-form  300  comprises a square-wave, other voltage wave-forms may be used to generate a dynamic polarization, such as a sinusoidal wave, a triangular wave, and a saw-tooth wave, just to name a few examples. 
         [0022]    In an embodiment, a decrease of a failure probability of a memory cell in a “0” state resulting from SILC may correspond to a reduction of an electric field through a tunnel oxide, such as oxide  150  shown in  FIG. 1A , during a T on  phase of an applied dynamic polarization. Such an electric field between a substrate and a floating gate through a tunnel oxide may normally exist in a memory cell as a result of a certain amount of charge placed in the floating gate in the course of storing information. For example, such different voltages may exist if the memory cell is in a “0” state. As a result, the voltage difference may result in. an electric field leading to an energy band profile, such as energy band profile  180  shown in  FIG. 1B , for example. Applying a dynamic polarization, as explained above, may counteract, e.g., reduce, such an already-existing electric field. Accordingly, a reduced net electric field may result in a decreased probability for electrons to tunnel through oxide layer  150 , for example. Decreasing a probability of tunneling may also decrease SILC, thus reducing the failure probability of a memory cell in a “0” state. Of course, such electric fields are merely examples, and claimed subject matter is not so limited. 
         [0023]    As described above, applying a dynamic polarization to a memory cell in a “0” state may reduce an electric field that results in decreased electron tunneling, thus decreasing SILC. Unfortunately, the same dynamic polarization that may decrease SILO for a memory cell in a “0” state may increase SILC for a memory cell in a “1” state. 
         [0024]    Such an increased SILC may result from the fact that a floating gate of a memory cell in a “1” state may be positively charged, so that the applied dynamic polarization may favor increased electron tunneling from a substrate into the floating gate. This may reduce an amount of positive charge on the floating gate, leading to possible information loss. In contrast, as described above, a floating gate of a memory cell in a “0” state may be negatively charged, so that the applied dynamic polarization may favor a decreased electron tunneling from a substrate into the floating gate, thereby maintaining the amount of negative charge on the floating gate leading to improved information storage. Because a dynamic polarization may have opposing effects on a memory cell in a “1” state versus a “0” state, such a dynamic polarization may be intermittently and/or periodically applied. For example, such a periodic application may include wave-form  300  that includes a T on  phase and a T off  phase. In an embodiment, values for T on  and T off  may be selected for a periodically applied dynamic polarization so that T on  is long enough to prevent electrons from tunneling into a substrate of a memory cell in a “0” state, while T off  is long enough to allow any electrons that may have become trapped in an oxide during T on  to tunnel back to a substrate of a memory cell in a “1” state, as explained below. 
         [0025]      FIG. 4A  shows energy band profiles for a memory cell in a “0” state including tunneling and trapped electrons, according to an embodiment. With no applied dynamic polarization, as during a T off  phase, electrons  420  making up a charge on a floating gate may tunnel to a substrate, via tunnel processes  405  and  415 . However, an applied dynamic polarization, as during a T on  phase, may prevent electrons  420  on the floating gate from tunneling to the substrate, due at least in part to a relatively small net electric field between the floating gate and the substrate. 
         [0026]    As shown in  FIG. 4A  for phase T off , electrons  420  may tunnel from a floating gate towards a substrate via tunnel processes  405  and  415 . During the course of tunneling across an oxide region, the electrons become trapped in an oxide trap  410 . A trapped electron  425  is shown residing in oxide trap  410 , for example. If T off  is relatively short compared to T on , a tunneling electron that is at least momentarily trapped in oxide trap  410  may not have enough time to tunnel from oxide trap  410  to the substrate, for example. In other words, oxide trap  410  may hold onto electrons trapped during their tunneling from the floating gate long enough during phase T off  to give these trapped electrons  425  an opportunity to tunnel back to the floating gate during a subsequent T on  phase. In such a case, the T off  phase may be short enough to prevent tunnel process  415 . Of course, such examples may be simplified in that tunneling processes of relatively large numbers of electrons may primarily be statistically determined. In any case, claimed subject matter is not limited to such examples. 
         [0027]    Returning to  FIG. 4A  for phase T on , trapped electrons  425  may now have an opportunity to tunnel from oxide trap  410  to the floating gate via tunnel process  435 , for example. Meanwhile, tunnel process  445  from the oxide trap  410  to the substrate may become unfavorable, so that substantially the electron  425  that tunneled out of the floating gate to oxide trap  410  during the previous T off  phase has a favorable chance to return to the floating gate via tunnel process  435  during the T on  phase, for example. 
         [0028]      FIG. 4B  shows energy band profiles for a memory cell in a “1” state including tunneling and trapped electrons, according to an embodiment. With an applied dynamic polarization, as during a T on  phase, electrons  475  on a substrate may tunnel to a floating gate, via tunnel processes  460  and  470 . If enough such tunneling electrons add to a charge on the floating gate, stored information may be lost. However, during a T off  phase electrons that tunneled during T on  and subsequently became trapped electrons  465  may now reverse direction and tunnel back to the substrate, for example. Such reverse-direction tunneling may be due at least in part to a relatively small net electric field between. the floating gate and the substrate. 
         [0029]    As shown in  FIG. 4B  for phase T on , electrons  475  may tunnel from a substrate towards a floating gate via tunnel processes  460  and  470 . During the course of tunneling across an oxide region, the electrons become trapped in an oxide trap  465 . A trapped electron  465  is shown residing in oxide trap  490 , for example. If is relatively short compared to T off , a tunneling electron that is at least momentarily trapped in oxide trap  490  may not have enough time to tunnel from oxide trap  490  to the floating gate, for example. In other words, oxide trap  490  may hold onto electrons trapped during their tunneling from the substrate long enough during phase T on  to give these trapped electrons  465  an opportunity to tunnel back to the substrate during a subsequent T off  phase. In such a case, the T on  phase may be short enough to prevent tunnel process  460 . Of course, such examples may be simplified in that tunneling processes of relatively large numbers of electrons may primarily be statistically determined. In any case, claimed subject matter is not limited to such examples. 
         [0030]    Returning to  FIG. 4B  for phase T off , trapped electrons  465  may now have an opportunity to tunnel from oxide trap  490  to the substrate via tunnel process  485 , for example. Meanwhile, a tunnel process from the oxide trap  490  to the floating gate may become relatively less favorable compared to the case for T on , so that a substantial number of electrons  465  that tunneled out of the substrate to oxide trap  490  during a previous T on  phase may return to the substrate via tunnel process  485  during the T off  phase. 
         [0031]    In an embodiment, a numerical evaluation may be performed in order to determine values for T on  and T off . Consider a case where a control gate voltage, V cg  is equal to V th -V t,UV , where V th  and V t,UV  are the programmed threshold voltage and the UV threshold voltage of a memory cell, respectively. As a consequence, an electric field through a tunnel oxide of the memory cell may be substantially zero, so that a SILC current may be negligible. Generally, in order to decrease a memory cell failure probability by a factor of ten, for example, a memory storage time is to be reduced by multiplying by a factor of 0.2. A relation between T on  and T off  may be obtained by considering such a factor along with the relation (T on +T off )*N=T standby , where N is the number of pulses of a square waveform, and T standby  is the time span for which the memory cell is operated in a standby mode. SILC may affect the memory cell during a total period during which a dynamic polarization is not applied, which may be expressed as T off *N. Setting the latter relation equal to 0.2* T standby  yields T off *N=0.2*T standby , Finally, combining the latter relation with (T on +T off )*N=T standby  yields the ratio T on /T off =4, which may indicate that T on  may be four times greater than T off  to reduce a SILC failure probability for the “0” state by a factor of ten. Of course, such an estimate of a relation between T on , T off , and a SILO failure probability is merely an example, and claimed subject matter is not so limited. 
         [0032]      FIG. 5  is a graph  500  showing measured cumulative distribution of threshold voltages of a population of memory cells in a “1” state for various polarization duty cycles, according to an embodiment. Curves  530  and  560 , for example, may represent a same stress time, which is the sum of all T on  pulses, so that the shorter the T on , the greater the number of pulses applied, for example. Regarding the horizontal axis, Vt is the threshold voltage of a population of memory cells, which may comprise a measure of charge on floating gates of the memory cells. Such a threshold voltage may be used to discriminate between “0” and “1” states of the memory cell. For example, Vt below a reference value may correspond to a “1” state whereas Vt above the reference value may correspond to a “0” state. Regarding the vertical axis, “% cells” indicates the percentage of memory cells having a threshold voltage below a particular Vt. For example, 99.5% of the cells have a threshold voltage below 3.5V for curve  560  in  FIG. 5 . Curve  560  represents the case for T on , always and T off= 0, so that a static polarization is applied to the memory cell. In this case, curve  560  demonstrates that a greater number of memory cells compared to those represented by curve  530  have an increased floating gate charge (higher Vt). A higher Vt for a memory cell in a “1” state may present an increased risk that such a memory cell may not be read as a “1” state, so that stored information may be lost. Accordingly, decreasing T on  relative to T off , at least for implementations presented in  FIG. 5 , may provide some benefit to extending memory storage times. Of course, such conditions are merely examples, and claimed subject matter is not so limited. 
         [0033]    In an embodiment, operating a memory device in a standby mode may include switching off a relatively large portion of memory device circuits, thereby reducing power consumption. To implement a dynamic polarization as described above, however, may involve additional power consumption to apply voltage pulses to word-lines of the memory device, for example. Such a memory device may comprise multiple blocks of memory cells. In one particular implementation, a dynamic polarization may be applied sequentially to individual word-lines within the multiple memory blocks. In such a case, values for a T on /T off  ratio may be fixed by the number of ward-lines to the memory cells. 
         [0034]    Such a constraint may result from word-lines that are to be biased by the dynamic polarization one by one. For example, 32 word-lines may result in T off =31*T on . In another particular implementation, a dynamic polarization may be applied block by block, so that substantially all word-lines for a block are biased by the dynamic polarization together. As a result, there need not be a constraining relation between T on  and T off  as in the case above. Of course, such biasing of portions of a memory device is merely an example, and claimed subject matter is not so limited. 
         [0035]    In one embodiment, a dynamic polarization may be applied via a body of a memory cell, such as substrate  110  shown in  FIG. 1A . In such a case, a wave-form, such as wave-form  300  shown in  FIG. 3 , may include a first voltage  330  having a duration T on  and a second voltage  360  that is negative having a duration T off . Such a waveform may be applied to a body of a memory cell in a “0” state during standby phase to decrease a failure probability resulting from SILO, as described above. 
         [0036]    While there has been illustrated and described what are presently considered to be example embodiments, it will be understood by those skilled in the art that various other modifications may be made, and equivalents may be substituted, without departing from claimed subject matter. Additionally, many modifications may be made to adapt a particular situation to the teachings of claimed subject matter without departing from the central concept described herein. Therefore, it is intended that claimed subject matter not be limited to the particular embodiments disclosed, but that such claimed subject matter may also include all embodiments falling within the scope of the appended claims, and equivalents thereof.