Abstract:
A method of manufacturing an electronic circuit component, comprises the steps of: (a) forming a first thin film circuit element on a surface of a circuit board made of an Si substrate; (b) forming a hole or trench from the surface of the circuit board through at least a portion of a thickness of the Si substrate by etching; (c) forming an insulating film covering a surface of the formed hole or trench; (d) adhering a dry film of photoresist to the surface of the circuit board, the dry film capping an opening of the hole or trench; (e) patterning the dry film; and (f) by using the patterned dry film as a mask, etching the insulating film. An electronic circuit component having through conductors and being less influenced by high temperature annealing can be manufactured.

Description:
CROSS REFERENCE TO RELATED APPLICATION  
         [0001]    This application is based on Japanese Patent Application No. 2002-124691, filed on Apr. 25, 2002, the entire contents of which are incorporated herein by reference.  
         BACKGROUND OF THE INVENTION  
         [0002]    A) Field of the Invention  
           [0003]    The present invention relates to a method of manufacturing an electronic circuit component and more particularly to a method of manufacturing an electronic circuit component having a conductor pattern buried in holes or trenches.  
           [0004]    An example of such an electronic circuit component is an interposer substrate. For example, when LSIs are mounted on a mother board of a computer, an interposer substrate is interposed between LSIs and the mother board in some cases. If an interposer substrate is formed by an Si substrate, the interposer substrate can be manufactured by utilizing manufacture techniques of semiconductor devices. When through conductors are formed through layers of IC, LSI, memory or the like, a multilevel circuit can be manufactured.  
           [0005]    B) Description of the Related Art  
           [0006]    A multi-chip module (MCM) board used with a main frame computer and the like has a plurality of LSls mounted thereon. Capacitors are often mounted on the MCM board in order to eliminate noises from the power supply voltages. Conventionally, a ceramic capacitor chip is mounted on an MCM board.  
           [0007]    Recent computers have a high clock frequency. If a ceramic capacitor chip is to be mounted, it becomes necessary to use lead wires. These lead wires have impedance components such as inductance L so that the high speed performance is degraded.  
           [0008]    In order to improve the high speed performance, an interposer substrate mounted with capacitors just under LSIs to be mounted is desired in order to shorten the wiring length. In order to reduce the opposing areas of capacitor electrodes and obtain a large capacitance, it is preferable to use dielectric material having a high dielectric constant as the material of the capacitor dielectric film.  
           [0009]    For example, barium strontium titanate (BST, (Ba, Sr)TiO 3 ) is used as the material of the capacitor dielectric film. In order to improve the capacitor characteristics, after the capacitor dielectric film is formed, BST is preferably annealed at about 700° C. in an oxidizing atmosphere such as air. The circuit board is required to be excellent in heat resistance in order to perform high temperature annealing in an oxidizing atmosphere.  
           [0010]    Although a ceramic substrate is excellent in heat resistance, it has some problem of scratches on a polished surface and poor smoothness of a substrate surface. When ceramic is baked, it shrinks and the volume is reduced. It is therefore difficult to precisely control a pitch between electrodes or pads.  
           [0011]    An interposer substrate made of an Si substrate can utilize the manufacture techniques of Si integrated circuit devices so that a high precision can be realized. A method of manufacturing a circuit board made of an Si substrate has not established as yet.  
         SUMMARY OF THE INVENTION  
         [0012]    An object of this invention is to provide a method of manufacturing an electronic circuit component capable of manufacturing a high precision circuit board.  
           [0013]    Another object of the invention is to provide a method of manufacturing an electronic circuit component not influenced by high temperature annealing.  
           [0014]    According to one aspect of the present invention, there is provided a method of manufacturing an electronic circuit component, comprising the steps of: (a) forming a first thin film circuit element on a surface of a circuit board made of an Si substrate; (b) forming a hole or trench from the surface of the circuit board through at least a portion of a thickness of the Si substrate by etching; (c) forming an insulating film covering a surface of the formed hole or trench; (d) adhering a dry film of photoresist to the surface of the circuit board, the dry film capping an opening of the hole or trench; (e) patterning the dry film; and (f) by using the patterned dry film as a mask, etching the insulating film.  
           [0015]    According to another aspect of the present invention, there is provided a method of manufacturing an electronic circuit component, comprising the steps of: (a) preparing a circuit board having a hole or trench extending from a surface of the circuit board to an inside of the circuit board; (b) adhering a dry film of photoresist to a surface of the circuit board, the dry film capping an opening of the hole or trench; (c) patterning the dry film; and (d) by using the patterned dry film as a mask, processing the circuit board.  
           [0016]    As above, a novel manufacture method for an electronic circuit component is provided.  
           [0017]    After thin film circuit elements are formed, through conductors are formed. Restrictions of a thermal process for forming thin film circuit elements can be relaxed. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]    [0018]FIGS. 1A to  1 O are schematic cross sectional views illustrating a method of manufacturing an electronic circuit component according to an embodiment of the invention.  
         [0019]    [0019]FIG. 2 is a schematic cross sectional view illustrating a method of manufacturing an electronic circuit component according to another embodiment of the invention.  
         [0020]    [0020]FIGS. 3A and 3B are schematic cross sectional views illustrating a method of manufacturing an electronic circuit component according to another embodiment of the invention.  
         [0021]    [0021]FIGS. 4A to  4 D are schematic cross sectional views illustrating a method of manufacturing an electronic circuit component according to another embodiment of the invention.  
         [0022]    [0022]FIGS. 5A to  5 C are schematic cross sectional views illustrating a method of manufacturing an electronic circuit component according to another embodiment of the invention.  
         [0023]    [0023]FIGS. 6A and 6B are a plan view and a cross sectional view showing the structure of a system-in-package.  
         [0024]    [0024]FIGS. 7A to  7 C are perspective views and a side view showing the structure of a multilevel circuit board. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0025]    Description will be made on the preferred embodiments of the invention, referring to the drawings. The embodiments have no limitative meaning.  
         [0026]    As shown in FIG. 1A, the top and bottom surfaces of an Si substrate  11  having a thickness of, e.g., about 600 μm are thermally oxidized to form silicon oxide films  12  and  12   b  having a thickness of about 1 μm. Although the silicon oxide film  12   b  on the bottom surface is not necessarily required, it is formed at the same time when the silicon oxide film  12  on the top surface is formed.  
         [0027]    On the silicon oxide film  12  on the top surface, a Pt film  13  having a thickness of, e.g., about 100 nm is deposited by sputtering or the like. Instead of the Pt film, a noble metal film which cannot be oxidized or does not lose conductivity even if it is oxidized, a conductive oxidized noble film or the like may be formed. Conductive films of different kinds may be laminated. An insulating film may be laminated as an adhesion layer between the silicon oxide film  12  and Pt film  13 .  
         [0028]    A photoresist layer is coated on the Pt film  13 , exposed and developed to form a photoresist pattern PR 1 . By using the photoresist pattern PR 1  as a mask, the exposed Pt film  13  is etched or milled to pattern the Pt film  13 . The photoresist pattern PR 1  is thereafter removed with a resist remover.  
         [0029]    As shown in FIG. 1B, a barium strontium titanate (BST) film  14  having a thickness of, e.g., about 100 nm is formed covering the Pt layer  13 . The BST layer can be formed by a zol-gel process or the like. Other dielectric films having a high dielectric constant may be used. A photoresist pattern PR 2  is formed on the BST film  14 . By using the photoresist pattern PR 2  as a mask, the BST film  14  is etched. The photoresist pattern PR 2  is thereafter removed.  
         [0030]    As shown in FIG. 1C, a Pt layer  15  having a thickness of, e.g., about 100 nm is formed over the substrate by sputtering. A photoresist pattern PR 3  is formed on the Pt layer  15 . By using the photoresist pattern PR 3  as a mask, the Pt layer  15  is etched or milled. The photoresist pattern PR 3  is thereafter removed.  
         [0031]    [0031]FIG. 1D shows the structure of a capacitor formed by the above-described processes. Although a plurality of capacitor structures are shown in FIG. 1D, these capacitor structures are contiguous to each other in the area not shown. The areas where the capacitor structures are not formed constitute openings through which through conductors are passed.  
         [0032]    As shown in FIG. 1E, covering the capacitor structures, a photosensitive polyimide layer  16  is coated to a thickness of, e.g., about 500 nm. The photosensitive polyimide layer  16  is exposed and developed to partially and selectively remove it.  
         [0033]    As shown in FIG. 1F, the insulating film of polyimide is therefore formed which has openings exposing the upper electrode  15  and lower electrode  13  of the capacitor and covers the other surface of the capacitor.  
         [0034]    As shown in FIG. 1G, a copper wiring layer  17  is formed covering the polyimide layer  16 . For example, the copper wiring layer is formed by depositing a Cr adhesion layer and a Cu seed layer by sputtering and plating a Cu layer thereon.  
         [0035]    As shown in FIG. 1H, a photoresist pattern PR 4  is formed on the copper wiring layer  17 . The photoresist pattern PR 4  has a wiring pattern to be connected to the upper electrode  15  and lower electrode  13  of the capacitor, other wiring patterns to be formed on the polyimide layer  16 , and if necessary, inductor element patterns. By using the photoresist pattern PR 4  as a mask, the copper wiring layer  17  is etched.  
         [0036]    As shown in FIG. 1H, a photosensitive polyimide layer  18  is coated covering the copper wiring pattern  17 . The photosensitive polyimide layer  18  is exposed and developed to partially and selectively remove it. The polyimide layer  18  is therefore formed which has openings exposing wiring contacts.  
         [0037]    As shown in FIG. 1J, covering the polyimide layer  18 , a photoresist layer is coated over the Si substrate  11 . The photoresist layer is exposed and developed to form a resist pattern PR 5  having openings in the areas where holes or trenches are formed. By using the photoresist pattern PR 5  as a mask, the silicon oxide layer  12  is patterned by wet etching or dry etching. Thereafter, holes or trenches  20  having a depth of about 150 μm is formed in the Si substrate  11  by performing anisotropic dry etching (reactive ion etching) for about 60 minutes by using, e.g., an inductive coupled plasma etching system. The photoresist pattern PR 5  is thereafter removed.  
         [0038]    As shown in FIG. 1K, the substrate is placed in a CVD system and a silicon oxide film  21  is deposited by CVD, the silicon oxide film  21  having a thickness of about 2 μm on the flat surface. Although the silicon oxide film in the hole or trench having a high aspect ratio becomes thinner at a deeper position, the whole inner wall is covered with the silicon oxide film.  
         [0039]    [0039]FIG. 1O shows a dry film of a three-layer structure. A photoresist layer PR is sandwiched between a pair of protective layers PT. One protective layer PT is peeled off. Then, the dry film is placed on the substrate surface with the exposed resist layer PR being directed downward. The dry film is pressed with a roller to adhere it to the substrate surface. The other protective layer is peeled off to expose the dry film.  
         [0040]    As shown in FIG. 1K, the dry film is exposed and developed to leave a dry film pattern  25  which caps the holes or trenches. Since the hole or trench formed by etching is capped with the dry film pattern  25 , it is possible to prevent foreign matters or patterning process residues from entering the hole or trench.  
         [0041]    As shown in FIG. 1L, the silicon oxide film  21  exposed by the dry film pattern  25  is etched and removed with, e.g., dilute hydrofluoric acid. Thereafter, the dry film pattern is swelled and removed. The dry film pattern  25  can be removed without being dropped in the hole or trench.  
         [0042]    As shown in FIG. 1M, a copper layer is formed over the surface of the substrate to bury the hole or trench with copper and cover the substrate surface. For example, the copper wiring layer is formed by depositing a Cr adhesion layer and a Cu seed layer by sputtering and plating a Cu layer thereon. CVD may be used instead of plating. An unnecessary portion of the copper layer is removed by etching with a photoresist pattern to thereby form a copper wiring pattern  29  having a vertical region.  
         [0043]    In the structure shown in FIG. 1M, a left wiring  29  is connected to the upper electrode of the capacitor and the middle wiring  29  is connected to the lower electrode of the capacitor. Both the wirings are formed through the electrodes of the capacitor so that the contact wiring length is very short. Since parasitic inductance can be reduced, a high speed operation of the capacitor can be enhanced. The right wiring  29  is disposed independently from the capacitor and constitutes a signal wiring line or the like.  
         [0044]    As shown in FIG. 1N, the Si substrate  11  is polished from the bottom surface thereof to expose the wiring  29 . The wiring  29  is a through wiring which passes through the Si substrate  11 . On the exposed Si surface, an insulating film layer  31  such as silicon oxide is formed and an opening exposing the wiring  29  is formed by etching with a resist pattern. On the exposed wiring  29 , a contact pad  35  is formed.  
         [0045]    With the above-described processes, a circuit board can be manufactured which has through conductors and a capacitor having a small parasitic inductance and connected to the through conductors. Wirings can also be formed at the same time. The wirings may have a multilevel wiring structure. A hole or trench through which the through conductor passes is formed by etching the Si substrate to a partial depth thereof so that a process time can be shortened.  
         [0046]    In the above-described embodiment, after the hole or trench is capped with a dry film, wet etching is performed at an atmospheric pressure. Alternatively, dry etching in a low pressure atmosphere may be performed.  
         [0047]    [0047]FIG. 2 shows a pattern of a dry film  25   d  used when dry etching is performed. The dry film  25   d  has an air path hole  26  above the hole or trench  20 . As a circuit board is placed in a vacuum chamber and the inner pressure is reduced, air in the hole or trench  20  is exhausted via the air path hole  26  to the external. An insulating layer on the surface of the circuit board is dry-etched by plasma etching or the like. Since the air path hole  26  can be formed finely, an insulating layer in the inner wall of the hole or trench is etched scarcely.  
         [0048]    In the above-described embodiments, a hole or trench is formed in the Si substrate to an intermediate depth thereof, and the Si substrate is polished from the bottom surface to expose the conductor formed in the hole or trench. A hole or trench may be formed in the Si substrate to the whole thickness thereof. The processes of this embodiment will be described in the following.  
         [0049]    Processes similar to the processes shown from FIG. 1A to FIG. 1I are preformed.  
         [0050]    As shown in FIG. 3A, in a process corresponding to the process shown in FIG. 1J, the Si substrate  11  is etched to the whole thickness thereof. In this case, the silicon oxide layer  12   b  formed on the bottom surface of the Si substrate can be used as an etching stopper. In place of the silicon oxide layer, a CVD silicon nitride layer may be formed beforehand as an etching stopper layer. A lamination of a silicon oxide layer and a silicon nitride layer or the like may be used as an etching stopper layer. Thereafter, processes corresponding to the processes shown in FIGS. 1K and 1L are performed.  
         [0051]    As shown in FIG. 3B, after a through conductor  29   t  is formed, an opening for exposing the through conductor  29   t  is formed through the etching stopper layer  12   b  on the bottom surface of Si substrate, and a pad is formed covering the exposed through conductor.  
         [0052]    In the embodiment shown in FIGS. 3A and 3B, an etching time is prolonged because the whole thickness of the Si Substrate is etched. However, it is easy to form thin film circuit elements on the bottom surface of the Si substrate. An embodiment of forming additional circuit elements will be described in the following.  
         [0053]    As shown in FIG. 4A, on the top surface of an Si substrate  11  formed with silicon oxide layers  12  and  12   b , thin film circuit elements TF 1  are formed, and on the bottom surface thereof, thin film circuit elements TF 2  are formed.  
         [0054]    As shown in FIG. 4B, by using a photoresist pattern PR 5  as a mask, holes or trenches are etched from the top surface of the Si substrate. In this etching, the insulating layer  12   b  on the bottom surface of the Si substrate functions as an etching stopper layer.  
         [0055]    As shown in FIG. 4C, through conductors  29   t  are formed.  
         [0056]    As shown in FIG. 4D, the etching stopper layer  12   b  is partially etched to expose the bottoms of the through conductors  29   t  and pads  35  are formed. With these processes, a circuit board can be formed which has thin film circuit elements on the top and bottom surfaces of the Si substrate.  
         [0057]    Methods of forming a circuit board has been described by using an Si substrate. A substrate other than an Si substrate may be used.  
         [0058]    [0058]FIGS. 5A to  5 C illustrate a method of forming a circuit board by using a glass substrate as an insulating substrate.  
         [0059]    As shown in FIG. 5A, thin film circuit elements  42  are formed on the surface of a glass substrate  41 . After a hole  43  is formed in the glass substrate  41  to a partial depth thereof, an insulating layer  44  of silicon oxide or the like is deposited over the whole surface of the glass substrate.  
         [0060]    As shown in FIG. 5B, a dry film is adhered to the glass substrate, exposed and developed to form a dry film pattern  25 . The holes  43  are capped with the dry film pattern  25 . The dry film pattern  25  is formed on the surface of the insulating layer  44  to be left unetched. In this state, etching is performed to selectively remove the insulating layer  44 .  
         [0061]    As shown in FIG. 5C, the dry film  25  is swelled and removed. Thereafter through conductors  29  and other wirings  32  are formed.  
         [0062]    Thereafter, the glass substrate  41  is polished from the bottom surface thereof to expose the bottoms of the through conductors  29 . Contact pads and the like are formed on the exposed bottoms of the through conductors  29  to complete a circuit board. As described above, a circuit board can be formed by using substrates made of a variety of materials.  
         [0063]    [0063]FIG. 6A is a plan view of a system-in-package structure wherein an interposer substrate  51  is stacked on a circuit board  50  and semiconductor integrated circuit devices are disposed on the interposer substrate  51 . The interposer substrate  51  is mounted on the circuit board  50  and circuit components  52 - 1  to  52 - 5  including a plurality of semiconductor elements are mounted on the interposer substrate  51 . Semiconductor elements may be an arithmetic and logical unit, a digital signal processor (DSP), a memory, a high frequency (RF) IC, an input/output (I/O) interface and the like. Another circuit component  53  is a SAW filter or the like.  
         [0064]    A wiring pattern is formed on the circuit board  50 , and the interposer substrate  51  containing capacitors and wiring patterns is interposed between the circuit board  50  and the semiconductor elements  52 - 1  to  52 - 5  and circuit component  53 .  
         [0065]    [0065]FIG. 6B is a schematic diagram showing a portion of wirings in the interposer substrate  51 . The interposer substrate  51  is disposed on the circuit board  50 , and circuit components  54  including a plurality of semiconductor elements IC 1  and IC 2  are disposed on the interposer substrate  51 . Formed in the interposer substrate  51  are through conductors PC supported by a support substrate S, vertical wirings WV connected to the through conductors PC, apacitor electrodes C 1  and C 2  connected to the vertical wirings WV, and local interconnects LI 1  and LI 2  connected to terminals of the semiconductor elements.  
         [0066]    A pitch of terminals of the semiconductor elements IC 1  and IC 2  is narrower than a pitch of terminals of the circuit board  50 . If the terminals of the semiconductor elements IC 1  and IC 2  are to be interconnected by wirings on the circuit board  50 , it is necessary to widen the wiring pitch. By utilizing the wirings in the interposer substrate  51 , the semiconductor elements IC 1  and IC 2  can be interconnected at a shorter wiring length without changing the wiring pitch or by suppressing the enlargement of the wiring pitch.  
         [0067]    [0067]FIGS. 7A and 7B are perspective views showing a lamination structure of a plurality of semiconductor element layers of the same type, and FIG. 7C is a side view showing a lamination structure of a plurality of semiconductor element layers of different types.  
         [0068]    [0068]FIG. 7A shows a lamination structure of a plurality of low integration semiconductor element layers. An IC multilevel circuit board can be formed by stacking a plurality of IC layers, or a memory multilevel circuit board can be formed by stacking a plurality of memory layers. With such a multilevel structure, the performance of the circuit board can be improved. In the example shown in FIG. 7A, a semiconductor circuit  60  such as an IC and a memory disposed on a chip  61  having through conductors  64  is connected to an underlying chip  62  via lead wires  63 , through conductors  64  and bumps  65 . The chip  62  is connected to an underlying layer (not shown) via through conductors  66  and bumps  67 .  
         [0069]    [0069]FIG. 7B shows a lamination structure of a plurality of high integration semiconductor element layers, in comparison with the lamination structure of a plurality of low integration semiconductor element layers shown in FIG. 7A. In this example shown in FIG. 7B, an LSI circuit  70  disposed on a chip  71  having through conductors  74  is connected to an underlying chip  72  via lead wires  73 , through conductors  74  and bumps  75 . The chip  72  is connected to an underlying layer (not shown) via through conductors  76  and bumps  77 .  
         [0070]    [0070]FIG. 7C shows a composite multilevel circuit board using semiconductor elements of different types, in comparison with the lamination structure of a plurality of semiconductor element layers of the same type shown in FIGS. 7A and 7B. In the example shown in FIG. 7C, semiconductor element layers  81 ,  82  and  83  made of ICs, memories, LSIs and the like are disposed on a mother board  80  and interconnected via bumps  84 ,  85  and  86 .  
         [0071]    The present invention has been described in connection with the preferred embodiments. The invention is not limited only to the above embodiments. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.