Abstract:
A current conveyor circuit with improved power supply noise immunity. Additional biasing circuitry causes the nominal biasing potential applied to the output circuit to be increased, thereby producing a corresponding increase in the magnitude of noise voltage needed to appear on the power supply before the output signal becomes affected.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to current conveyor circuits, and in particular, to current conveyor circuits operating at low voltages with high power supply noise. 
   2. Description of the Related Art 
   Referring to  FIG. 1 , a conventional gain-boosting circuit, often referred to as a current conveyor circuit, includes two transistors, P-type metal oxide semiconductor field effect transistors (P-MOSFETs) M 1 , M 2 , and three current sources I 1 , I 2 , I 3 , all interconnected substantially as shown. Referring to  FIGS. 1A and 1B , in accordance with well-known current source circuit design techniques, the upper current source I 1  can be implemented using a P-type MOSFET P 1  with a bias voltage Vbiasp applied at its gate electrode to generate its output current I 1 . Similarly, each of the lower current sources I 2 , I 3  can be implemented as an N-type MOSFET N 1  with an appropriate bias voltage Vbiasn applied at its gate electrode to generate its current output I 2 , I 3 . 
   In such a current conveyor circuit, an input current Iin is applied at the source electrode of transistor M 1 , which conveys such current to its drain electrode to be made available as the output current Iout. The circuit node at the source electrode of transistor M 1  provides a low impedance path for the input current Iin, while the drain electrode of transistor M 1  provides a high output impedance, thereby providing good isolation between the input (source electrode) and output (drain electrode). By including transistor M 2  with its connections as shown the input impedance path for the input current Iin is reduced even further. The high impedance node at the drain electrode of transistor M 2  (and gate electrode of transistor M 1 ) and the resultant negative feedback loop can be compensated by connecting a shunt capacitance C 1 , e.g., between such node and the lower power supply electrode VSS/GND. 
   A problem arises when such a circuit is used in a large system where a significant amount of noise can appear within the power supply, particularly within the power supply reference, or ground, connection. Often such power supply noise can be quite large in magnitude as compared to the power supply voltage VDD which is often very low (e.g., 1.6 volts). As is evident from the circuit connections, the voltage V 2  at the input electrode is one gate-to-source voltage VGS below the power supply voltage VDD, i.e., VDD-VGS. Accordingly, the voltage V 1  at the gate electrode of the output transistor M 1  is lower by one additional gate-to-source voltage VGS, i.e., VDD−2*VGS. 
   This makes the voltage across current source I 3  also equal to VDD−2*VGS. In an integrated circuit fabricated using a typical 0.18 micron process, the threshold voltage VT of the transistors M 1 , M 2  is approximately 0.45 volt, while the saturation voltage VDSAT of the transistors within a good region of operation is approximately 0.2 volt. With a supply voltage of 1.6 volt, this makes the voltage across current source I 3  equal to VDD−2*VGS=1.6−2*0.45=1.6−1.3=0.3 volt. 
   If this current source I 3  is a simple N-MOSFET current source (e.g., transistor N 1  in  FIG. 1B ) operating with a minimum saturation voltage VDSAT of 0.2 volt, then it is operating with a 0.1 volt margin. However, if the power supply noise, via the ground connection VSS/GND, exceeds this margin of 0.1 volt, the device forming this current source I 3  will fall out of saturation, thereby allowing the noise voltage to modulate the voltage V 1  at the gate electrode of the output transistor M 1 . As a result, the noise becomes coupled into the output current Iout. 
   SUMMARY OF THE INVENTION 
   In accordance with the presently claimed invention, a current conveyor circuit is provided with improved power supply noise immunity. Additional biasing circuitry causes the nominal biasing potential applied to the output circuit to be increased, thereby producing a corresponding increase in the magnitude of noise voltage needed to appear on the power supply before the output signal becomes affected. 
   In accordance with one embodiment of the presently claimed invention, a current conveyor circuit with improved power supply noise immunity includes first and second power supply electrodes and serial circuitries. First serial circuitry is coupled between the first and second power supply electrodes, and includes input and output electrodes, a first circuit electrode and at least a first transistor. Second serial circuitry is coupled between the first and second power supply electrodes and the input electrode, and includes a second circuit electrode and at least a second transistor. Third serial circuitry is coupled between the second power supply electrode and the first and second circuit electrodes, and includes at least a third transistor. 
   In accordance with another embodiment of the presently claimed invention, a current conveyor circuit with improved power supply noise immunity includes first and second power supply electrodes, input and output electrodes, first and second circuit electrodes, current source circuitries and metal oxide semiconductor field effect transistors (MOSFETs). First current source circuitry is coupled between the first power supply electrode and the input electrode as a source of a first reference current. Second current source circuitry is coupled between the second power supply electrode and the output electrode as a source of a second reference current which is substantially equal to the first reference current. Third current source circuitry is coupled between the second power supply electrode and the second circuit electrode as a source of a third reference current. Fourth current source circuitry is coupled between the second power supply electrode and the first circuit electrode as a source of a fourth reference current. A first MOSFET includes first drain, source and gate electrodes coupled to the output, input and first circuit electrodes, respectively. A second MOSFET includes second drain, source and gate electrodes coupled to the second circuit, first power supply and input electrodes, respectively. A third MOSFET includes third drain and gate electrodes coupled to the first circuit electrode and a third source electrode coupled to the second circuit electrode. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic diagram of a conventional current conveyor circuit. 
       FIGS. 1A and 1B  are circuit symbols for conventional implementations of current source circuits. 
       FIG. 2  is a schematic diagram of a current conveyor circuit in accordance with one embodiment of the presently claimed invention. 
   

   DETAILED DESCRIPTION 
   The following detailed description is of example embodiments of the presently claimed invention with references to the accompanying drawings. Such description is intended to be illustrative and not limiting with respect to the scope of the present invention. Such embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the subject invention, and it will be understood that other embodiments may be practiced with some variations without departing from the spirit or scope of the subject invention. 
   Throughout the present disclosure, absent a clear indication to the contrary from the context, it will be understood that individual circuit elements as described may be singular or plural in number. For example, the terms “circuit” and “circuitry” may include either a single component or a plurality of components, which are either active and/or passive and are connected or otherwise coupled together (e.g., as one or more integrated circuit chips) to provide the described function. Additionally, the term “signal” may refer to one or more currents, one or more voltages, or a data signal. Within the drawings, like or related elements will have like or related alpha, numeric or alphanumeric designators. 
   Referring to  FIG. 2 , a current conveyor circuit with improved power supply noise immunity in accordance with one embodiment of the presently claimed invention provides a modification to the conventional current conveyor circuit of  FIG. 1  by adding an additional current source I 4  and transistor M 3 , interconnected within the circuit substantially as shown. In this embodiment, the transistor M 3  is a P-type MOSFET which is diode-connected with its gate and drain electrodes connected together and to the gate electrode of the output transistor M 1 , and with its source electrode connected to the circuit node connecting the drain electrode of transistor M 2  and the upper electrode of current source I 3 . 
   In accordance with this embodiment of the presently claimed invention, transistor M 3  is operated at a current density which is one-fourth (0.25) of the current densities at which transistors M 1  and M 2  are operated. For example, in a preferred embodiment, currents I 1 , I 2  and I 3  are equal, i.e., I 1 =I 2 =I 3 =IREF, while current I 4  has a magnitude of one percent (1%) of the other currents, i.e., I 4 =0.01*IREF. Further, in such embodiment, transistors M 1  and M 2  have equal channel width-to-length ratios W/L with equal channel widths and lengths, while transistor M 3  has a width-to-length ratio W/L of four percent (4%) of transistors M 1  and M 2 , i.e., 0.04*W/L. As a result, transistor M 3  is operated at a current density of one-fourth (¼) of the current densities of transistors M 1  and M 2 . This causes the voltage V 3  across current source I 3  to now be equal to VDD-VGS-VDSAT, which is an improvement in noise immunity by a factor of VGS-VDSAT. 
   This can be demonstrated in accordance with well-known MOSFET circuit operating characteristics. As is well-known, drain currents ID 1  and ID 2  of transistors M 1  and M 3 , respectively, can be computed based upon the majority carrier mobility u, the gate capacitance per unit area Cox, the channel width W, channel length L, threshold voltage VT, transistor scaling factor N and the respective gate-to-source voltages VGS 1  (transistor M 1 ), VGS 2  (transistor M 3 ), as follows: 
   
     
       
         
           
             
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   Setting these currents equal to each other (id 1 =id 2 ) produces Equation 3, which can be simplified and reduced as follows, for a scaling factor of N=4: 
               Equation   ⁢           ⁢   3     :           ⁢           u   ·   Cox     2     ·       N   ·   W     L       ⁢       (       VGS   1     -   VT     )     2         =           u   ·   Cox     2     ·     W   L       ⁢       (       VGS   2     -   VT     )     2               N ( VGS   1   −VT ) 2 =( VGS   2   −VT ) 2   Equation 4   √{square root over (N)} ( VGS   1   −VT )=( VGS   2   −VT )  Equation 5   VGS   2   =√{square root over (N)} ( VGS   1   −VT )+VT  Equation 6   VGS   2   −VGS   1   =√{square root over (N)} ( VGS   1   −VT )+ VT−VGS   1   Equation 7   VGS   2   −VGS   1   =√{square root over (N)} ( VGS   1   −VT )−( VGS   1   −VT )  Equation 8   VGS   2   −VGS   1 =( √{square root over (N)} −1)( VGS   1   −VT )  Equation 9 Example: N= 4 , VGS   2   −VGS   1 =( VGS   1   −VT )=VDSAT 1   Equation 10 
   The output conductance of a MOSFET, i.e., at its drain electrode, typically has a value approximately equal to 100 times the inverse 1/GM of the transconductance GM of the device. However, when the device leaves saturation during its operation, the output impedance drops to approximately 1/GM, i.e., by a factor of 100, thereby significantly reducing the loop gain. Further, the output conductance of a MOSFET scales inversely with its output current, i.e., its drain current. 
   In this circuit embodiment, transistor M 3  is part of a negative feedback loop where a high impedance node appears at the drain electrode of transistor M 2 . As noted above, this can be compensated by the shunt capacitance C 1 . The impedance at the drain electrode of transistor M 3  will be approximately the inverse of its transconductance GM, and is very small compared to the output impedance of the current source I 3 , i.e., at the circuit node to which the source electrode of transistor M 3  is connected. However, the device providing the output current for the current source I 3  (e.g., transistor N 1  in  FIG. 1B ) is also typically quite small and operates with a very low current. Accordingly, its output impedance, while large as compared to the impedance of transistor M 3 , may nonetheless be relatively low. To compensate for this, an additional capacitance C 2  can be connected if necessary between the drain and source electrodes of transistor M 3 , and preferably have a value approximately equal to the gate-to-source capacitance CGS of the output transistor M 1  so as to avoid introducing a high frequency zero into the transfer function for the feedback loop. 
   When the current source I 4  leaves saturation during operation, e.g., due to power supply noise via circuit ground VSS/GND, the impedance seen in parallel with the output impedance of current source I 3  will be the inverse 1/GM of the transconductance GM of the device forming current source I 4  (e.g., transistor N 1  in  FIG. 1B ) in series with the impedance of this added capacitance C 2  (which at high frequency should be very low). 
   As a result, the inverse 1/GM of the transconductance GM of the device forming current source I 4  will be approximately 100 times as large as the inverse 1/GM of the transconductance GM of the device forming current source I 3 , and is approximately equal to the output conductance GDS (the inverse of the output resistance, i.e., the drain-to-source resistance RDS) of the device forming current source I 3 . Accordingly, the loop gain decreases only by a factor of 2, which is an improvement by a factor of 50. 
   Various other modifications and alternations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and the spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.