Abstract:
A three-dimensional systolic architecture for beamforming according to convolve signals from an array with sets of weighting coefficients using a one dimensional array of similar modules with finite impulse response filter elements with outputs directed into pipelining register stacks and propagated to the stack boundaries for summing in accumulator arrays and demultiplexing.

Description:
BACKGROUND AND SUMMARY OF THE INVENTION 
     Current sonar systems employ both time and space diversity to achieve a high level of operational performance. This, together with the complex geometry and relatively slow speed of sound propagation in the ocean, has imposed many constraints on the concomitant signal processing system. For example, low sonar operating frequencies and the use of wide-band processing have forced the use of broad-band beamforming. Further, ever-increasing numbers of hydrophonic elements are being used for high spectral resolution and the signal processing system must be capable of forming in parallel large numbers of independent beams in order to attain an adequate angular cover as well as giving the desired spectral resolution. In addition, for towed systems in particular, the geometry of the array may fluctuate. The general effect of these three observations is to impose an enormous computing load on the signal processing system. Some agencies have developed satellite-to-shore systems which can call on the number crunching power of super-computers like the Cray. In the general environment this is not possible, and hence parallel computers based on VSLI technology must be considered. If such systems are realisable, then there is the added advantage that the system can be carried on small platforms such as helicopters and diesel-electric submarines. 
     This invention indicates one possible architecture for implementing a limited class of passive broad-band beamformers. It is found that computing loads approaching hundreds of mega-flops can be achieved conceptually with a minimum of silicon area. It is also found that the systems can be made highly reliable by incorporating a limited form of self repair. 
     A paper by Speiser, J. M., Whitehouse, H. J. and Bromley, K. (1980). `Signal Processing Applications for Systolic Arrays`, Record of the 14th Asimolar Conference on Circuits, Systems and Computers, Pacific Grove, Calif., IEEE 80CH1625-3 addresses the general question but does not give a clear indication of the power of systolic arrays for particular tasks. In contrast, this paper is concerned with a specific design and implementation. 
     Reference may be had to the specification of Patent Application No. WO 84/04225, published under the provision of the Patent Cooperation Treaty, in which a self repair large scale integrated circuit is described, this application is assigned to the Commonwealth of Australia, having the same inventors as this application namely Marwood, W. and Clarke, A. P. 
     The invention deals generally with a form of distributed signal processing called a systolic array. The systolic array is a one, two or higher dimensional array of identical processors. In each processor, both the hardware and the executed program is identical. Each processor is connected to nearest neighbours, computes data, and then passes data on to its neighbours at all times in synchronism with a master clock. In physiology, the word `systole` is used for the heart contraction pumping blood. In the systolic array the system clock is the analogue of the heart. 
     In most sonar signal processing requirements, the basic operations can be written in a matrix form. When this is realised, it can be seen that each processor can consist of a cascaded sequence of processing blocks where each block is a systolic array executing a matrix operation. Hence the total implementation will consist almost entirely of systolic processing elements. Reference may be had to the papers of Whitehouse, H. J. and Speiser, J. M., `Sonar Applications of Systolic Array Technology`, presented at IEEE Eascon, Washington, D.C., Nov. 17-19, 1981, and Speiser, J. M. and Whitehouse, H. J., `Parallel Processing Algorithms and Architectures for Real-Time Signal Processing`, SPEE Vol. 298, Real-Time Signal Processing IV (1981) paper 298-03. 
     In conventional beamforming, the observation of some propagating, coherent wave in the ambient noise background of the ocean is enhanced by summing time-delayed and weighted hydrophone data. The weights are designed to achieve some specified side-lobe level from a particular array. 
     The output in a given direction θ is given ##EQU1## where x n  (t) is output from hydrophone n 
     w n  is a weight factor 
     and r n  (θ) is a time delay to be applied to the n th  hydrophone to steer in the direction θ. 
     In digital systems the x n  are sampled (usually at frequencies 5-10 times Nyquist) and samples from each hydrophone taken as near to the steered direction θ as possible. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In order, however, that the invention will be better understood, an embodiment of the invention will be described with reference to the accompanying drawings, in which 
     FIG. 1 shows a structural schematic of the beamformer which includes a linear concatenation of identical modules with sensor data input at the left boundary module and weighting coefficients input to the front boundary of each module and beam data output from the bottom face of each module. 
     FIG. 2 shows a functional schematic of two modules and details their interconnection. 
     FIG. 3 is a functional schematic of a systolic processing element which when connected in a three dimensional structure of the form of FIG. 2 implements the FIR filter and register stacks of each module. 
     FIG. 4 shows the logical interconnection of a two dimensional array of the systolic elements of FIG. 3 to implement one module. 
     FIG. 5 shows the modified matrix product required for the formation of a beam sample. 
     FIG. 6 indicates the data shift operation required at each array sample time. 
     FIG. 7 shows by way of explanation the block diagram of a finite impulse response filter implemental with the systolic elements of FIG. 3. 
     FIG. 8 shows for explanatory purposes, details of a third order finite impulse response (FIR) filter or convolution implementation, showing the cyclic completion behaviour of the systolic processing elements. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 shows a structural schematic of the object of this invention, which is an interpolation or adaptive beamformer. The figure shows that construction is achieved by concatenating a series of identical modules 1. Sensor data are input at the leftmost module and weighting coefficients are input to the front boundary of each module. Beam outputs are driven out from the bottom face of each module, one beam per module. 
     A block schematic of the beamformer is shown in FIG. 2 for the case of two beams. It is constructed by replicating modules designated by 2, 3, 4 and 5. The number of replications of the module determines the number of beams the beamformer can process. Module interconnection is demonstrated by the figure. Operation of the beamformer is described in terms of one module only. The FIR filter bank 2 is constructed from k linear systolic arrays of multiply/accumulate elements. Each systolic array implements an FIR filter. Each filter is associated with one particular sensor. 
     The number of FIR filters is determined by the number of sensors, and each sensor broadcasts its data to one systolic array per module. Weighting coefficients are entered serially into the boundary elements of each filter and recirculated. Filter outputs occur cyclically from each element in turn and are input to adjacent linear arrays of registers. These registers are interconnected orthogonally to form a pipelining register stack 3. Data is clocked through the structure synchronously, and the cyclic completion times of the k filters are in phase. This causes the outputs from the ith element of each of the k filters to be loaded synchronously into one column of the register stack 3 at each successive time period. These output samples are clocked through the register stack 3 to the accumulator bank 4 where the accumulated result is output after k clock periods. The skewing of the data present in the columns due to the cyclic behaviour of the filters cause the accumulator element outputs to be cyclic also. These outputs are input to a demultiplexer 5 to recover the correct beam time series. 
     The inputs are designated X 1 , X 2 , X 3  . . . X k  and these go to the FIR filter banks 2. The weights are indicated by r 1 ,1, r 1 ,2 . . . r 1 ,k, r 2 ,2 . . . r 2 ,k etc. 
     FIG. 3 shows a functional schematic of a systolic processing element which when connected in a three dimensional structure of the form of FIG. 2 implements the FIR filters 2 and register stacks 3 of the modules of FIGS. 1 and 2. It consists of a pipelining delay element 6 for the r coefficients and a storage delay element 7 for the x coefficients. These coefficients are multiplied in a multiplier element 8 and the result summed in an accumulator 9. At the completion of the formation of an inner product x·r in the accumulator it is loaded into a register stack element 10. 
     FIG. 4 shows the logical interconnection of a two dimensional array 11 of the systolic elements of FIG. 3 with an accumulator array 12 and demultiplexer 13 to implement one module of FIGS. 1 and 2. 
     The beamforming can be represented in matrix form as: 
     
         tr{X·S(θ)}=b.sub.θ (t) 
    
     where X is the data buffer at time t and S (θ) is a matrix that extracts data from X for summing. 
     Errors are possible due to sampling. Pridham, R. G., and Mucci, R. A., `A Novel Approach to Digital Beamforming` I. Acoust, Soc. Am., February 1978 pp 625-434 suggest interpolation as a means of reducing this error. For steering over p angles it is then possible to write a matrix equation ##EQU2## where r 1 , r 2 , . . . ,r k  are the k columns of S which are now occupied by interpolation coefficients, 
     
         x.sub.1, x.sub.2, . . . ,x.sub.k are the k rows of X 
    
     and   is an operation giving as the `inner product` the sum over n of the scalar product r n .x n   
     The formation of a single beam is considered ##EQU3## where s is the length of the data vector. 
     A modification to this architecture which removes the necessity to broadcast the input data involves the placement of delay elements in both SPE interconnection paths and also the input data path. 
     FIG. 5 shows a schematic of the formation of an interpolation beam sample from a data matrix. The beam sample is the trace of the product of the data matrix and a weight matrix. As is shown in the figure, the computation performed by the proposed architecture does not include off-diagonal elements. The computation efficiency is improved over a conventional matrix multiplication by a factor of (k-1), as only k elements are formed, compared to k 2  in the conventional product. The formation of the actual beam sample requires the addition of the k main diagonal elements. This involves k-1 additions. 
     To obtain the next beam sample, it is necessary to perform the data shift operation detailed in FIG. 6 before performing the modified matrix product. However, the structure of the systolic arrays which perform the convolutions make this data shift naturally. The architecture readily accepts adaptive processes such as the Frost algorithm. 
     In the case of an adaptive algorithm implementation, the coefficients are updated as often as is required. Computation of the new coefficients is performed externally to the systolic array. 
     FIGS. 7 and 8 show respectively how a finite impulse response filter 15 is implemented with the systolic element of FIG. 3, and how the cyclic completion behaviour of the systolic elements is arrived at. The cyclic completion of the SPE&#39;s is not resolved by a demultiplexer as would be necessary in a complete filter implementation. Instead, advantage is taken of the spare clock periods between the completion phase of each SPE to clock the data in the pipeline register stack to the accumulator where it is summed. 
     The claims defining the invention are as follows: