Abstract:
The described devices, systems and methods include an electro-static discharge clamp with a latch to prevent false triggering of an electro-static discharge protection circuit in response to fluctuations in a power supply rail.

Description:
[0001]    This application is a Divisional filing of U.S. patent application Ser. No. 12/913,060, filed Oct. 27, 2010, which claims the benefit of U.S. provisional patent application No. 61/256,742, filed Oct. 30, 2009, the disclosures of which are incorporated herein by reference in their entireties. 
     
    
     FIELD OF THE DISCLOSURE 
       [0002]    This application relates to electro-static discharge (ESD) protection circuits. The application further relates to preventing false triggering of an ESD protection circuit in response to fluctuations on the power supply. 
       BACKGROUND 
       [0003]    Power supply clamps are used for ESD protection in complementary metal oxide semiconductor (CMOS) circuits.  FIG. 1  depicts a common ESD protection circuit  10  for an integrated circuit consisting of a resistor-capacitor (RC) time constant network  12  composed of a resistor  14  and a capacitor  16 . The RC time constant network  12  is connected to an inverter  18 , which in turn drives a transistor array  20  to clamp the power supply to ground during the ESD event. The ESD protection circuit  10  is designed to stay on only long enough to dissipate the ESD pulse and then turn off again. The length of time that the ESD protection circuit  10  is on is controlled by the RC time constant connected to the inverter  18 . One notable feature of the ESD protection circuit  10  is that each time the integrated circuit is powered up, a current spike occurs while the clamp is on prior to the RC trigger timing out. For most applications, this short surge of current is purely incidental and is not detrimental to the functioning of the integrated circuit. 
         [0004]    However, the ESD protection circuit  10  may also turn on when voltage transients cause large enough swings on the supply rails. If these voltage transients are inherent to an application, for example with dc to dc buck converters, the transistor array  20  can stay on indefinitely, which draws down the power rail. Another scenario where the ESD protection circuit  10  may be problematic is when the power supply is current limited such that the power supply is drawn down when the transistor array  20  turns on momentarily at startup of the integrated circuit. When the RC time constant releases, the voltage suddenly spikes up. At this point, the clamp may turn on again and a recurring oscillation ensues. 
         [0005]    Thus, there is a need for a new ESD clamp circuit that is insensitive to the transients produced on the power rail of an integrated circuit. 
       SUMMARY OF THE DETAILED DESCRIPTION 
       [0006]    Embodiments in the detailed description relate to an ESD clamp with a latch to preventing false triggering of an ESD protection circuit in response to fluctuations in a power supply. As a first example, an ESD clamp includes a resistor coupled to a power supply node of an integrated circuit. A capacitor is coupled to the resistor to form a first node, wherein the capacitor is also coupled to a common node of the integrated circuit. A first p-type field effect transistor (PFET) includes a gate, a source coupled to the power supply node, and a drain coupled to the first node. An inverter includes an inverter input and an inverter output, wherein the inverter input is in communication with the first node and the inverter output is in communication with the gate of the first PFET. In addition, the ESD clamp includes an n-type field effect transistor (NFET) including a gate in communication with the inverter output, a drain coupled to the power supply node, and a source coupled to the common node. 
         [0007]    A second example of an electro-static discharge (ESD) clamp includes a resistor coupled to a power supply node of an integrated circuit and a capacitor coupled to the resistor to form a first node. The capacitor is further coupled to a common node of the integrated circuit. The ESD clamp also includes a first NFET including a gate, a source coupled to the first node, and a drain coupled to the power supply node. The ESD claim further includes a first inverter including a first inverter input and a first inverter output, wherein the first inverter input is in communication with the first node and a second inverter including a second inverter input and a second inverter output, wherein the second inverter input is coupled to the first inverter output to form a second node, and the second inverter output is coupled to the gate of the first NFET. The ESD clamp also includes a second NFET including a gate coupled to the second node, a drain coupled to the power supply node, and a source coupled to a common node. 
         [0008]    Yet another ESD clamp includes a resistor coupled to a power supply node and a first capacitor coupled to a common node and further coupled to the first resistor to form a first node. The ESD clamp also includes a first inverter including a first inverter input coupled to the first node, a first inverter output coupled to a second node, and a clear input, wherein the first inverter is configured to output a logic low level upon assertion of the clear input. The ESD clamp further includes a second inverter including a second inverter input coupled to the second node, and an inverter output coupled to the clear input of the first inverter and a first NFET including a gate coupled to the second node, a drain coupled to the power supply node, and a gate coupled to the common node. 
         [0009]    Those skilled in the art will appreciate the scope of the disclosure and realize additional aspects thereof after reading the following detailed description in association with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure. 
           [0011]      FIG. 1  depicts an ESD clamp. 
           [0012]      FIG. 2  depicts an example power clamp with a disablement latch. 
           [0013]      FIG. 3  depicts a transistor level power clamp with a disablement latch of  FIG. 2 . 
           [0014]      FIG. 4  depicts an example power clamp with disablement latch. 
           [0015]      FIG. 5  depicts a transistor level power clamp with a disablement latch of  FIG. 4 . 
           [0016]      FIG. 6  depicts a three inverter clamp with disablement circuit. 
           [0017]      FIG. 7  depicts a single inverter clamp with disablement circuit. 
           [0018]      FIG. 8  depicts an example power clamp having a NOR circuit with disablement circuit. 
           [0019]      FIG. 9  depicts an example power clamp having a NOR circuit with disablement circuit. 
       
    
    
     DETAILED DESCRIPTION 
       [0020]    The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the disclosure and illustrate the best mode of practicing the disclosure. Upon reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. 
         [0021]    The described devices, systems and methods relate to an ESD clamp with a latch to preventing false triggering of an ESD protection circuit in response to fluctuations in the power supply. As a first example, an ESD clamp includes a resistor coupled to a power supply node of an integrated circuit. A capacitor is coupled to the resistor to form a first node, wherein the capacitor is also coupled to a common node of the integrated circuit. A first PFET includes a gate, a source coupled to the power supply node, and a drain coupled to the first node. An inverter includes an inverter input and an inverter output, wherein the inverter input is in communication with the first node and the inverter output is in communication with the gate of the first PFET. In addition, the ESD clamp includes an NFET including a gate in communication with the inverter output, a drain coupled to the power supply node, and a source coupled to the common node. When the power supply node is powered up, the second PFET is turned on, which keeps the input of the inverter asserted. As a consequence, the output of the inverter is held at a logic low level, which prevents the NFET from sinking current from the power supply node during a power glitch. 
         [0022]      FIG. 2  depicts a power clamp with a disablement latch  22  having a first PFET configured as a dynamic resistor  24  coupled to a second PFET configured as a MOS capacitor  26 . The dynamic resistor  34  is coupled to the power supply node (V DD ) of an integrated circuit and the MOS capacitor  26  to form a resistor capacitor (RC) time constant circuit. The MOS capacitor  26  is further coupled to a common voltage (V SS ). In some embodiments the common voltage (V SS ) may be ground. 
         [0023]    A first inverter  28  includes an inverter input coupled to the junction of the dynamic resistor  24  and MOS capacitor  26 . The inverter output of the first inverter  28  is coupled to a gate of NFET  30 . The drain of the NFET  30  may be coupled to the power supply node (V DD ) of the integrated circuit. The source of the NFET  30  may be coupled to the common voltage (V SS ). The NFET  30  may be an array of transistors. 
         [0024]    The power clamp with the disablement latch  22  further includes a second inverter  32  coupled in series with a third inverter  34 , where the input of the second inverter  32  is coupled to the inverter output of the first inverter  28 . The inverter output of the third inverter  34  is coupled to the gate of the third PFET  36 . The drain of the third PFET  36  is coupled to the inverter input of the first inverter  28 . 
         [0025]    Functionally, when no power is applied to the power supply node (V DD ), the power clamp with the disablement latch  22  is in a power down mode, and all the nodes are nominally at a zero volt potential. Upon receipt of an ESD discharge, the MOS capacitor  26  holds the input of the first inverter  28  low while turning on the first inverter  28 . As a result, the first inverter  28  provides a turn-on voltage to the gate of the NFET  30 . In response to the voltage applied to the gate of the NFET  30 , the NFET  30  shunts the EDS current to ground. The third PFET  36  is turned off. The MOS capacitor  26  is charged up through the dynamic resistor  24 . After the turn-on voltage applied to the MOS capacitor  26  reaches the logic threshold level of the first inverter  28 , the first inverter  28  asserts a logic low output, which turns off the NFET  30  and turns on the third PFET  36 . 
         [0026]    Alternatively, when power is applied to the power supply node (V DD ), the MOS capacitor  26  is charged up through the dynamic resistor  24 . After the voltage applied to the MOS capacitor  26  reaches the logic threshold level of the first inverter  28 , the first inverter  28  asserts a logic low output, which turns off the NFET  30 . Likewise, the feedback of the output of the first inverter  28  to the third PFET  36  ensures that the input of the first inverter  28  remains pulled high in the event there is a glitch or some instability on the power supply node (V DD ). 
         [0027]      FIG. 3  depicts a transistor implementation of the power clamp with a disablement latch  22 . The first inverter  28  is composed of a fourth PFET  38  coupled to a second NFET  40 . The second inverter  32  includes a fifth PFET  42  coupled to a third NFET  44 . The third inverter  34  includes a sixth PFET  46  coupled to a fourth NFET  48 . 
         [0028]      FIGS. 4 and 5  depict an ESD clamp with disablement latch  50  which is similar to the ESD clamp with disablement latch  22  depicted in  FIGS. 2 and 3 . As shown in  FIG. 5 , the ESD clamp with disablement latch  50  removes the third inverter  34  and replaces the third PFET  36  with a fifth NFET  52 . The source of the fifth NFET  52  is coupled to the input of the first inverter  28 . The drain of the fifth NFET  52  is coupled to the power supply node (V DD ). 
         [0029]    Continuing with reference to  FIG. 4 , functionally, the ESD clamp with disablement latch  50  operates similarly to the ESD clamp with disablement latch  22  except that the second inverter  32  asserts a logic high signal on the gate of the fifth NFET  52 , which causes the fifth NFET  52  to go into saturation. When the fifth NFET  52  is in saturation, the output of the first inverter  28  is held low, which turns off the NFET  30 . 
         [0030]    Alternatively, when power is applied to the power supply node (V DD ), the MOS capacitor  26  is charged through the dynamic resistor  24 . After the voltage applied to the MOS capacitor  26  reaches the logic threshold level of the first inverter  28 , the first inverter  28  asserts a logic low output, which turns off the NFET  30 . Likewise, the feedback of the output of the first inverter  28  to the fifth NFET  52  ensures that the input to the first inverter  28  remains pulled high in the event there is a glitch or some instability on the power supply node (V DD ). 
         [0031]      FIG. 5  depicts a transistor level diagram of the ESD clamp with disablement latch  50 . 
         [0032]      FIG. 6  depicts a single inverter clamp with disablement circuit having a first resistor  56  coupled to the power supply node (V DD ) and a first capacitor  58 . The first capacitor  58  is coupled to the common node (V SS ), which may be ground. The input of a first inverter  60  is coupled to the first resistor  56  and first capacitor  58 . The output of the first inverter  62  is coupled to the input of a second inverter  62 . The output of the second inverter  62  is coupled to the input of an inverter with clear circuit  64 . 
         [0033]    The inverter with clear circuit  64  includes an inverter input  66 , and inverter output  68 , and a clear input  70 . The inverter with clear circuit  64  is configured to output a logic low level upon assertion of the clear input  70 . Otherwise, the inverter with clear circuit  64  operates as an inverter when the clear input  70  is deasserted. 
         [0034]    The inverter with clear circuit  64  includes a first PFET  72  coupled to a first NFET  74  to form the inverter input  66 . The drain of the first PFET  72  is coupled to the source of a second PFET  76 . The drain of the second PFET  76  is coupled to the drain of the first NFET  74  to form the inverter output  68 . The gate of the second PFET  76  and the gate of a second NFET  78  are coupled to form the clear input  70  of the inverter with clear circuit  64 . The drain of the second NFET  78  is also coupled to the inverter output  68 . 
         [0035]    Functionally, when the clear input  70  is deasserted to a logic level low, the inverter with clear circuit  64  functions as an inverter. The second PFET  76  is turned on and the second NFET  78  is turned off. 
         [0036]    However, when the clear input  70  is asserted to a logic level high, the inverter with clear circuit  64  outputs a logic level low on the inverter output  68  of the inverter with clear circuit  64 . The second PFET  76  is turned off and the second NFET  78  is turned on, which forces the inverter output to a logic level low. 
         [0037]    Continuing with the description of the three inverter clamp with disablement circuit  54 , the inverter output  68  is coupled to the first NFET  74  and an inverter input of the third inverter  80 . The output of the third inverter  80  is coupled to a second capacitor  82  and the clear input  70 . 
         [0038]    Operationally, when no power is applied to the power supply node (V DD ), the three inverter clamp with disablement circuit  54  is in a power down mode and all the nodes are nominal at a zero volt potential. Upon receipt of an ESD discharge, the first capacitor  58  holds the input of the first inverter  60  at a logic level low, which causes the second inverter  62  to assert a logic level high output. Likewise, the second capacitor  82  holds the clear input  70  at a logic level low, which enables the inverter with clear circuit  64  to assert a logic level high at the inverter output  68 . This, in turn, turns on the clamping array  84 . The logic level high at the inverter output  68  asserts the third inverter  80 , which reinforces the clear input  70  to be held low until the ESD energy is discharged through the clamping array  84 . 
         [0039]    Alternatively, when power is applied to the power supply node (V DD ), the first capacitor  58  reaches the logic threshold level of the first inverter  60 , which turns off the clamping array  84  and asserts a logic level low on the inverter input of the third inverter  80 . As a result, the clear input  70  of the inverter with clear circuit  64  is asserted to a logic level high, which reinforces the inverter output  68  to remain at the logic level low. 
         [0040]    As depicted in  FIG. 7 , the single inverter clamp with disablement circuit  86  is functionally the same as the three inverter clamp with disablement circuit  54  except the first inverter  60  and the second inverter  62  are removed. As a consequence, the inverter input  66  of the inverter with clear circuit  64  is directly coupled to the first capacitor  58  and first resistor  56 . 
         [0041]    The single inverter clamp with disablement circuit  86  is functionally equivalent to the inverter with clear circuit  64 . The inverter with clear circuit  88  includes a first PFET  90  and a first NFET  92  coupled to form the inverter input  66  and inverter output  68 . The second PFET  94  is coupled to the source of the first PFET  90 , which acts to disable the inverter output  68  when the clear input  70  is asserted. Similar to the second NFET  78  of the three inverter with disablement circuit  54 , a drain of a second NFET  96  is coupled to the inverter output  68 , which acts to pull down the inverter output  68  when the clear input  70  is asserted. 
         [0042]    As depicted in  FIG. 8 , the single inverter clamp with disablement circuit  86  depicted in  FIG. 7  may be replaced by a NOR circuit  100 . The first input of the NOR circuit  100  may be coupled to the first capacitor  58  and first resistor  56 . The output of the NOR circuit  100  may be coupled to the clamping array  84  and the input of the third inverter  80 . The output of the third inverter  80  is coupled to the second input of the NOR circuit  100  and to the second capacitor  82 . As before, the second capacitor  82  and transmission time of the third inverter  80  delays the output of the third inverter  80  to permit the clamping array  84  to stay on for a desired period of time. 
         [0043]    As depicted in  FIG. 9 , the inverter with clear circuit  64  depicted in  FIG. 6  may likewise be replaced with a NOR circuit  100 . Similar to above, the first resistor  56  and first capacitor  58  are coupled to the input of the first inverter  60 . The output of the first inverter  60  is coupled to the input of the second inverter  62 . The first inverter  60  and second inverter  62  provide a delay before the NOR circuit  100  detects a transient spike on the V DD . Otherwise, the circuit of  FIG. 9  functionally operates similar to the circuit of  FIG. 8 . 
         [0044]    Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.