Abstract:
A logical circuit receives first and second input signals in which a period of a first logic level partially overlaps, and outputs first and second output signals in which a period of the first logic level does not overlap. The logical circuit comprises a first unit which changes a phase of the first output signal from a second logic level to the first logic level when a change of the first input signal from the second logic level to the first logic level is detected. A second unit changes a phase of the second output signal from the first logic level to the second logic level when the second input signal is detected as being at the first logic level at a time of detection of the change of the first input signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     This is a Continuation Application, which claims the benefit of pending U.S. patent application Ser. No. 11/042,335 filed Jan. 26, 2005, which in turn is a Continuation Application of International Application No. PCT/JP2003/03030, filed on Mar. 13, 2003. The disclosure of the prior application is hereby incorporated herein in its entirety by reference. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a logical circuit which is carried on a semiconductor device and outputs the output signals in which the period of the logic level (H) does not overlap even when the logical circuit receives the input signals in which the period of the logic level (H) partially overlaps.  
         [0004]     2. Description of the Related Art  
         [0005]     As a logical circuit which outputs the signals in which the period of the logic level (H) does not overlap, the EX-OR (exclusive-or) circuit is well known.  
         [0006]     In a case of the EX-OR circuit, the output signal will be influenced by one of the input signals at the time of rising of the other of the input signals.  
         [0007]     This is a significant problem for a certain circuit, such as a DLL (delay-locked loop) circuit in which the timing of rising of the signals is important. In a semiconductor device carrying the circuit which operates at a high speed synchronized with the clock signal, a variation of phase in the clock signal may arise due to signal transmission delay or the like.  
         [0008]     When a logical circuit which outputs the signals in which the period of the logic level (H) does not overlap is added to the semiconductor device and used together in order to reduce such phase variation of the clock signal as much as possible, consideration must be taken on the conformity of the logical circuit with the circuit in which the timing of rising of the signals is important.  
         [0009]     For this reason, it is demanded to provide a logical circuit which outputs the signals in which the period of the logic level (H) does not overlap and can be used suitably with the circuit, such as the DLL circuit in which the timing of rising of the signals is important, in such a manner that rising of the signal is not affected but falling of the signal is affected.  
         [0010]      FIG. 1A  shows an example of the conventional logical circuit.  FIG. 1B  shows the signal waveform of the input signals A and B to the logical circuit of  FIG. 1A , and the output signals C and D from the logical circuit.  
         [0011]     The logical circuit of  FIG. 1A  is a general EX-OR circuit that outputs the signals in which the period of the logic level (H) does not overlap.  
         [0012]     The EX-OR circuit comprises the inverter  1 , the inverter  2 , the inverter  3 , the inverter  4 , the NOR gate  5 , and the NOR gate  6 .  
         [0013]     In the EX-OR circuit of  FIG. 1A , the input signal A is inputted to the inverter  1 , and the input signal B is inputted to the inverter  2 . The output of the inverter  1  is inputted to one input of the NOR gate  5  while it is inputted to the inverter  3 . The output of the inverter  2  is inputted to one input of the NOR gate  6  while it is inputted to the inverter  4 .  
         [0014]     The output of the inverter  3  is inputted to the other input of the NOR gate  6 . The output of the inverter  4  is inputted to the other input of the NOR gate  5 . The NOR gate  5  receives the outputs from the inverter  1  and the inverter  4  and outputs the output signal C, and the NOR gate  6  receives the outputs from the inverter  2  and the inverter  3  and outputs the output signal D.  
         [0015]     Consideration will now be taken to the case where the phase of the input signal A and the input signal B is shifted somewhat with reference to  FIG. 1B .  
         [0016]     The input signal A and the input signal B are, for example, the two clock signals which have different phases.  
         [0017]     To these input clock signals, the variation in the phase may arise due to transmission delay of the clock signals in the semiconductor device carrying the circuit which operates at the high speed synchronized with the clock signals.  
         [0018]     As shown in  FIG. 1B , when the input signal B is at the logic level (L) at the instant the input signal A has changed from the logic level (L) to the logic level (H) (the time of rising), the phase of the input signal A transfers to the phase the output signal C as it is.  
         [0019]     However, when the input signal B is at the logic level (H) at the time of rising of the input signal A, the output signal C still remains at the logic level (L).  
         [0020]     When the input signal B changes from the logic level (H) to the logic level (L), the phase of the input signal A transfers to the phase of the output signal C for the first time.  
         [0021]     That is, the time of rising of the input signal A will be delayed until the phase of the input signal B changes to the logic level (L), and then the output signal C will be outputted.  
         [0022]     In other words, the EX-OR circuit of  FIG. 1A  operates such that the portion in which the logic level (H) of the input signal A overlaps with the input signal B is deleted from the portion in which the phase is changed from the logic level (L) to the logic level (H), and the overlapping of the logic level (H) of the output signal is eliminated.  
         [0023]     However, when the method of the EX-OR circuit is applied to the circuit like the DLL circuit in which the timing of rising is important, the delay of the timing of rising is affected by the counterpart signal, and excessive delay time (loss) may arise, which will become the factor which worsens the underflow of the DLL circuit (which indicates the circuit performance with the delay minimum value).  
         [0024]     Moreover,  FIG. 2  is a diagram for explaining operation of the conventional logical circuit of  FIG. 1A  when the phase shift of the input signals occurs at intervals of the period of some cycles.  
         [0025]     As shown in  FIG. 2 , when a phase shift of the input signal B to the input signal A occurs at intervals of some cycles, rather than the case where the phase shift occurs for every cycle, the conventional logical circuit may also cause the deviation of the phase of the input signal A.  
       SUMMARY OF THE INVENTION  
       [0026]     An object of the present invention is to provide an improved logical circuit in which the above-described problems are eliminated.  
         [0027]     Another object of the present invention is to provide a logical circuit which outputs the signals in which the period of the logic level (H) does not overlap and can be suitably used with a DLL circuit or the like in which the timing of rising is important, such that rising of the signals is not affected but falling of the signals is affected,  
         [0028]     In order to achieve the above-mentioned objects, the present invention provides a logical circuit which receives first and second input signals in which a period of a first logic level partially overlaps, and outputs first and second output signals in which a period of the first logic level does not overlap, the logical circuit comprising: a first unit which changes a phase of the first output signal from a second logic level to the first logic level when a change of the first input signal from the second logic level to the first logic level is detected; and a second unit which changes a phase of the second output signal from the first logic level to the second logic level when the second input signal is detected as being at the first logic level at a time of detection of the change of the first input signal.  
         [0029]     As a logical circuit in which the period of the logic level (H) of the two output signals does not overlap, in the case of EX-OR circuit, the output signals will be influenced when one of the input signals is at the logic level (H) at a time of rising of the other input signal.  
         [0030]     In the logical circuit of the present invention, rising of the signals is not influenced by the phase of the counterpart input signal. Therefore, according to the logical circuit of the present invention, it is possible to output the output signals in which the period of the logic level (H) does not overlap, without being influenced by either of the input signals at the time of rising of the counterpart input signal.  
         [0031]     By applying the logical circuit of the present invention to the circuit like the DLL circuit in which the timing of rising of the signals is important, it is possible that outputting the signals in which the period of the logic level (H) does not overlap be guaranteed and excessive delay time be shortened, without being influenced due to fluctuation of the input signals at the time of rising of one of the input signals. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0032]     Other objects, features and advantages of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.  
         [0033]      FIG. 1A  is a circuit diagram showing the conventional logical circuit.  
         [0034]      FIG. 1B  is a waveform diagram showing the signal waveform of the input signals A and B to the logical circuit of  FIG. 1A , and the output signals C and D.  
         [0035]      FIG. 2  is a diagram for explaining operation of the logical circuit of  FIG. 1A .  
         [0036]      FIG. 3  is a circuit diagram showing the logical circuit in one embodiment of the invention.  
         [0037]      FIG. 4  is a block diagram showing an example of composition of the semiconductor device using the EX-OR circuit in which outputting the first and second signals in which the period of the logic level (H) does not overlap is needed.  
         [0038]      FIG. 5  is a circuit diagram showing an example of the circuit in  FIG. 4  in which the signals in which the period of the logic level (H) does not overlap are needed.  
         [0039]      FIG. 6A  is a waveform diagram showing the signal waveform of the input signals A and B to the logical circuit of  FIG. 3 , and the output signals C and D.  
         [0040]      FIG. 6B  is a diagram for explaining operation of the logical circuit of  FIG. 3  at the time of outputting the output signal C to the input signals A and B.  
         [0041]      FIG. 6C  is a diagram for explaining operation of the logical circuit of  FIG. 3  at the time of outputting the output signal D to the input signals A and B. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0042]     A description will now be given of the preferred embodiments of the invention with reference to the accompanying drawings.  
         [0043]      FIG. 3  shows the logical circuit in one embodiment of the present invention.  
         [0044]     In the logical circuit of  FIG. 3 , the circuit elements of the upper-side circuit block configured to output the output signal C and the circuit elements of the lower-side circuit block configured to output the output signal D are arranged symmetrically.  
         [0045]     The upper-side circuit block of the logical circuit of  FIG. 3  comprises the output unit  51 A which outputs the output signal C, the circuit-element group  52 A which transmits the input signal B, and the circuit-element group  53 A which controls the transmission line (path) of the circuit-element group  52 A based on the logic information of the input signal A and the counterpart input signal B.  
         [0046]     The circuit-element group  52 A and the circuit-element group  53 A function as a state holding unit which holds, when the phase of the input signal A and the phase of the input signal B are set to the logic level (H) simultaneously, the state of the input signal B immediately preceding the setting.  
         [0047]     Similarly, the lower-side circuit block of the logical circuit of  FIG. 3  comprises the output unit  51 B which outputs the output signal D, the circuit-element group  52 B which transmits the input signal A, and the circuit-element group  53 B which controls the transmission line (path) of the circuit-element group  52 B by using the logic information of the input signal B and the counterpart input signal A.  
         [0048]     The circuit-element group  52 B and the circuit-element group  53 B function as a state holding unit which holds, when the phase of the input signal A and the phase of the input signal B are set to the logic level (H) simultaneously, the state of the input signal A immediately preceding the setting.  
         [0049]     As mentioned above, the circuit elements of the upper-side circuit block and the circuit elements of the lower-side circuit block in the logical circuit of this embodiment are the same, and, for the sake of convenience of description, only the circuit elements of the upper-side circuit block will be explained in the following, and a description of the lower-side circuit block will be omitted.  
         [0050]     The circuit-element group  51 A comprises the inverter  21  to which the input signal A is inputted, and the NOR gate  22  to which the output of the inverter  21  and the output of the circuit-element group  52 A are inputted.  
         [0051]     The circuit-element group  53 A comprises the NAND gate  32  to which the input signal A and the input signal B are inputted, the transistor  33 , and the transistor  34 .  
         [0052]     The transistor  33  has the gate to which the output of the NAND gate  32  is inputted, and the source-drain path one end of which is connected with the power-supply voltage line and the other end of which is connected with the source-drain path of the transistor  28 .  
         [0053]     The transistor  34  has the gate to which the output of the NAND gate  32  is inputted, and the source-drain path one end of which is grounded and the other end of which is connected with the output of the circuit-element group  52 A.  
         [0054]     The circuit-element group  52 A comprises the inverter  23  to which the input signal B is inputted, the inverter  24  to which the output of the inverter  23  is inputted, the transistor  25 , the transistor  26 , the transistor  27 , the transistor  28 , the inverter  29 , the transistor  30 , and the transistor  31 .  
         [0055]     The transistor  25  and the transistor  26  have the respective source-drain paths which are connected with each other, one of the source-drain paths is connected to the output of the inverter  24 , and the other of the source-drain paths is connected to the input of the inverter  29 .  
         [0056]     The transistor  25  has the gate to which the output of the NAND gate  32  is inputted. The transistor  26  has the gate to which the output of the inverter  35  is inputted.  
         [0057]     Moreover, in the circuit-element group  52 A, the transistor  28  has the gate to which the output of the inverter  29  is inputted, and the source-drain path one end of which is connected with the source-drain path of the transistor  33 , and the other end of which is connected with the source-drain path of the transistor  27 .  
         [0058]     The transistor  27  has the gate to which the output of the inverter  29  is inputted, and the source-drain path one end of which is connected with the source-drain path of the transistor  36 , and the other end of which is connected with the source-drain path of the transistor  28 .  
         [0059]     Moreover, in the circuit-element group  52 A, the inverter  29  has the input which is connected with the source-drain path of the transistors  27  and  28 , and the output which is connected with the source-drain path of the transistors  30  and  31 .  
         [0060]     The transistor  30  and the transistor  31  have the respective source-drain paths which are connected with each other, one of the source-drain paths is connected to the output of the inverter  29 , and the other of the source-drain paths is connected to the source-drain path of the transistor  34 .  
         [0061]     The transistor  30  has the gate to which the output of the NAND gate  32  is inputted. The transistor  31  has the gate to which the output of the inverter  35  is inputted.  
         [0062]     Furthermore, the upper-side circuit block of the logical circuit of  FIG. 3  comprises the inverter  35  to which the output of the NAND gate  32  is inputted, and the transistor  36 . The transistor  36  has the gate where the output of the inverter  35  is inputted, and the source-drain path one end of which is connected with the source-drain path of the transistor  27 , and the other end of which is grounded.  
         [0063]     As mentioned above, the lower-side circuit block of the logical circuit of  FIG. 3  has the composition which is the same as the upper-side circuit block thereof. The lower-side circuit block comprises the output unit  51 B which outputs the output signal D, the circuit-element group  52 B which transmits the input signal A, and the circuit-element group  53 B which controls the transmission line (path) of the circuit-element group  52 B based on the logic information of the input signal B and the counterpart input signal A.  
         [0064]      FIG. 6A  shows the signal waveform of the input signals A and B to the logical circuit of  FIG. 3 , and the output signals C and D.  FIG. 6B  is a diagram for explaining operation of the logical circuit of  FIG. 3  at the time of outputting the output signal C responsive to the input signals A and B.  FIG. 6C  is a diagram for explaining operation of the logical circuit of  FIG. 3  at the time of outputting the output signal D responsive to the input signals A and B.  
         [0065]     In  FIG. 6B  and  FIG. 6C , t 1 , t 2 , t 3 , t 4 , and t 5  respectively indicate the instants which are the same as the corresponding timings of the input/output signals in the signal waveform of  FIG. 6A  which are designated by the same reference numerals. In  FIG. 6B , a, b, c, d, e, f, and g respectively indicate the nodes which are the same as the corresponding nodes in the upper-side circuit block of the logical circuit of  FIG. 3  which are designated by the same reference numerals.  
         [0066]     Moreover, in  FIG. 6C , h, i, j, k, l, m, and n respectively indicate the nodes which are the same as corresponding nodes in the lower-side circuit block of the logical circuit of  FIG. 3  which are designated by the same reference numerals.  
         [0067]     As is apparent from the signal waveform of  FIG. 6A , at the time of t 1 , the input signal A is at the logic level (L), and the input signal B is at the logic level (H).  
         [0068]     At the time of t 2 , the input signal A rises to the logic level (H), and both the phase of the input signal A and the phase of the input signal B are set to the logic level (H) simultaneously.  
         [0069]     At the time of t 3 , the input signal B falls to the logic level (L), and the input signal A still remains at the logic level (H).  
         [0070]     At the time of t 4 , the input signal A falls to the logic level (L), and the input signal B still remains at the logic level (L).  
         [0071]     At the time of t 5 , the input signal B rises to the logic level (H), and the input signal A still remains at the logic level (L).  
         [0072]     As shown in  FIG. 6A , when the phase of the input signal A is changed from the logic level (L) to the logic level (H) (at the time of t 2 ), the logical circuit of  FIG. 3  functions to transfer the phase of the input signal A to the phase of the output signal C as it is, even if the counterpart input signal B is still at the logic level (H).  
         [0073]     On the other hand, when the phase of the counterpart input signal B is changed from the logic level (H) to the logic level (L) (at the time of t 3 ), the output signal D is still at the logic level (L). And the phase of the input signal B is not transferred to the phase of the output signal D. The position of falling of the output signal relative to the input signal will be shifted.  
         [0074]     As mentioned above, in the EX-OR circuit of  FIG. 1A , rising of one input signal is influenced by the counterpart input signal and falling is not influenced. On the other hand, in the logical circuit of the present invention, rising is not influenced by the counterpart input signal, but falling is influenced by the state of the counterpart input signal.  
         [0075]     According to the logical circuit of the present invention, excessive delay time can be shortened without being influenced due to fluctuation of the input signals at the time of rising of one of the input signals. When it is applied to the circuit like the DLL circuit in which the timing of rising is important, the logical circuit of the invention is very useful because the two output signals in which the period of the logic level (H) does not overlap are outputted while rising of one of the input signals is not influenced by the counterpart input signal.  
         [0076]      FIG. 4  shows an example of composition of the semiconductor device using the EX-OR circuit, which incorporates the circuit which requires receiving the incoming signals in which the period of the logic level (H) does not overlap.  
         [0077]     As shown in  FIG. 4 , the semiconductor device of this embodiment comprises the DLL delay circuit group  61 , the DLL comparator and control circuits  62 , the EX-OR circuit  63 , and the circuit  64  which needs receiving the incoming signals in which the period of the logic level (H) does not overlap.  
         [0078]     A description of the circuit  64  which needs receiving the incoming signals in which the period of the logic level (H) does not overlap will be given later with reference to  FIG. 5 .  
         [0079]     In the semiconductor device of  FIG. 4 , the EX-OR circuit  63  has the circuit configuration that is the same as that of the logical circuit of  FIG. 1A , and it is inserted in the circuit configuration including the general DLL circuit.  
         [0080]      FIG. 5  shows an example of the circuit  64  which needs receiving the incoming signals in which the period of the logic level (H) does not overlap, for use in the semiconductor device of  FIG. 4 .  
         [0081]     The outputs of the circuit of  FIG. 5  are arranged in the wired-or connection. The circuit of  FIG. 5  comprises the inverter  71 , the inverter  72 , the transistor  73 , the transistor  74 , the transistor  75 , the transistor  76 , the inverter  77 , the inverter  78 , and the inverter  79 .  
         [0082]     The 0-degree clock signal is inputted to the gate of the transistor  73 , and inputted to the input of the inverter  71 . The signal which is set by the inversion of the output of the inverter  71  is inputted to the gate of the transistor  74 .  
         [0083]     The respective source-drain paths of the transistors  73  and  74  are connected with each other, and the data  1  for the 0-degree clock input is inputted to one of the source-drain paths, and it is transmitted to the output terminal of the circuit of  FIG. 5  via the other of the source-drain paths.  
         [0084]     The 180-degree clock signal is inputted to the gate of the transistor  75 , and inputted to the input of the inverter  72 . The signal which is set by the inversion of the output of the inverter  72  is inputted to the gate of the transistor  76 .  
         [0085]     The respective source-drain paths of the transistors  75  and  76  are connected with each other, and the data  2  for the 180-degree clock input is inputted to one of the source-drain paths, and it is transmitted to the output terminal of the circuit of  FIG. 5  via the other of the source-drain paths.  
         [0086]     In the circuit of  FIG. 5 , the data bus is divided into two: one for the 0-degree clock input, and the other for the 180-degree clock input.  
         [0087]     From the output terminal of the circuit of  FIG. 5 , the data are serially outputted in accordance with the 0-degree clock signal and the 180-degree clock signal.  
         [0088]     Namely, the circuit of  FIG. 5  is the parallel-serial conversion circuit which receives the data  1  for the 0-degree clock input and the data  2  for the 180-degree clock input in parallel, and outputs the data serially in accordance with the 0-degree clock signal and the 180-degree clock signal.  
         [0089]     In the circuit of  FIG. 5 , if the 0-degree clock signal and the 180-degree clock signal, which are provided to perform the output control, indicate the logic level (H) simultaneously, the data will collide depending on the state of the data.  
         [0090]     For this reason, it is necessary to secure that the logic level (H) of the signals does not overlap, and therefore, the EX-OR circuit  63  is inserted in the semiconductor device as shown in  FIG. 4 .  
         [0091]     However, in the conventional EX-OR circuit  63 , the transitional portion of the input clock signal from the logic level (L) to the logic level (H) is deleted in order to secure that the logic level (H) of the signals does not overlap, and even though the clock signals with the phases locked by the DLL circuit are outputted, the deletion of the transitional portion of the input clock signal by the EX-OR circuit  63  will cause the variation of the clock phase to arise.  
         [0092]     It is satisfactory if there is no overlapping of the period of the logic level (H) between the input clock signals before being inputted to the EX-OR circuit  63 . However, there are some influences, such as the fluctuation of the pulse width of the clock signals in the transmission path of the DLL delay circuit group  61 , and the fluctuation of the delay position. Hence, it is difficult to guarantee that the period of the logic level (H) in the input clock signals does not overlap at all.  
         [0093]     For this reason, the removal of the clock signal portion will occur in the EX-OR circuit  63 , and this will cause the variation of operation of the semiconductor device.  
         [0094]     To obviate the problem, by using the logical circuit of  FIG. 3  in the semiconductor device of  FIG. 4  instead of the EX-OR circuit  63 , it is possible that the removal of the transitional portion from the logic level (L) to the logic level (H) of the input signal does not occur, as shown in  FIG. 6A , which makes it possible to suppress the variation of operation.  
         [0095]     According to the logical circuit of the present invention, it is possible to output the output signals in which the period of the logic level (H) does not overlap, without being influenced by either of the input signals at the time of rising of the counterpart input signal.  
         [0096]     By applying the logical circuit of the present invention to the circuit like the DLL circuit in which the timing of rising of the signals is important, it is possible that outputting the signals in which the period of the logic level (H) does not overlap be guaranteed and excessive delay time be shortened, without being influenced due to fluctuation of the input signals at the time of rising of one of the input signals.  
         [0097]     Moreover, since the factor which worsens the underflow of the DLL circuit as in the conventional logical circuit does not arise, the logical circuit of the present invention is effective as a logical circuit which outputs the signals in which the period of the logic level (H) does not overlap.  
         [0098]     The present invention is not limited to the above-described embodiments, and variations and modifications may be made without departing from the scope of the present invention.