Abstract:
A bandpass delta sigma truncator that truncates multi-bit digital input signals to digital output signals ( 24 ) having a selected number of the most significant data bits of the digital input signals and a method of truncating multi-bit digital signals. The remaining least significant data bits ( 3 ) of the input signals are (a) time delayed ( 26 ) by a period of time equal to the time between successive input signals and multiplied by a number ( 30 ) related to the ratio of a selected frequency to the frequency of the input signals and the results of the multiplication are added ( 32 ) to signs extensions ( 11 ) of the input signals, and (b) time delayed by a period of time equal to twice the time between successive input signals and after inversion ( 28 ) are added ( 32 ) to the sign extensions of the input signals.

Description:
TECHNICAL FIELD  
       [0001]     The present invention relates, in general, to radio frequency transmission and, in particular, to a sigma delta truncator that reduces noise in radio frequency transmissions by bit reduction of multi-bit digital signals and to a method of truncating multi-bit digital signals to reduce noise.  
       BACKGROUND OF THE INVENTION  
       [0002]     In a typical wireless system such as WCDMA, the baseband signal processing must meet two main specifications: (1) the in-band Error Vector Magnitude (EVM), and (2) the out-of-band Adjacent Channel Leakage Ratio (ACLR) as well as other speicifcations. The limits imposed on both EVM and ACLR are stringent.  
         [0003]     For WCDMA applications, there is an in-band EVM specification for the transmitter and an out-of-band ACLR specification at 5 MHZ and 10 MHZ. Usually, there is strong filtering at 10 MHZ which helps in reducing the 10 MHZ ACLR specification, but 5 MHZ is so close to the signal band that the 5 MHZ ACLR specification is somewhat more difficult to meet. Because all of the blocks in the transmit chain have an effect on meeting the ACLR specification, the effect of each should be well below the specification for the overall specification of the system to be met.  
         [0004]     The ACLR specification at 5 MHZ determines the number of bits required in the digital-to-analog converter. For WCDMA applications, this number is usually nine or ten bits. The other specifications, namely EVR and the 10 MHZ ACLR) usually can be satisfied with six bits.  
       SUMMARY OF THE INVENTION  
       [0005]     The present invention is a bandpass delta sigma truncator that effectively truncates the signals so that six bit digital-to-analog converters can be used in the signal processing circuitry and the EVM and 5 MHZ and 10 MHZ ACLR specifications are satisfied. This bandpass delta sigma truncator includes input means for receiving a series of first multi-bit digital signals each having a number of data bits and a first number of sign bits. Also included in this bandpass delta sigma truncator are sign extending means for sign extending each of the first multi-bit digital signals to a second multi-bit digital signal having the same number of data bits as the number of data bits in the first multi-bit digital signals and a second number of sign bits. A bandpass delta sigma truncator, constructed in accordance with the present invention, further includes output means for supplying from a series of third multi-bit digital signals each individually associated with one of the second multi-bit digital signals and each having the same number of data bits as in an associated second multi-bit digital signal a series of fourth multi-bit digital signals each having a selected number of the most significant data bits of the third multi-bit digital signals and a series of fifth multi-bit digital signals each having the remaining number of the least significant data bits of the third multi-bit digital signals. Also included in this bandpass delta sigma truncator are means for delaying by a period of time equal to the time between successive first multi-bit digital signals each of the fifth multi-bit digital signals and delaying by a period of time equal to twice the time between successive first multi-bit digital signals each of the fifth multi-bit digital signals and inverting the fifth multi-bit digital signals that have been delayed by a period of time equal to twice the time between successive first multi-bit digital signals. Each of the fifth multi-bit digital signals delayed by a period of time equal to the time between successive first multi-bit digital signals is multiplied by a multiplier number related to the ratio of a selected frequency to the frequency of the first multi-bit digital signals to develop a series of sixth multi-bit digital signals having a number of data bits that is the product of the multiplier number and the number of data bits in the fifth multi-bit digital signals. A bandpass delta sigma truncator, constructed in accordance with the present invention, further includes summing means for adding to each second multi-bit digital signal a fifth multi-bit digital signal that has been delayed by a period of time equal to twice the time between successive first multi-bit digital signals and inverted and a sixth multi-bit digital signal to develop the series of third multi-bit digital signals.  
         [0006]     A method for truncating a multi-bit digital signal in accordance with the present invention includes the steps of providing a series of first multi-bit digital signals each having a number of data bits and a first number of sign bits and sign extending each of the first multi-bit digital signals to a second multi-bit digital signal having the same number of data bits as the number of data bits in the first multi-bit digital signals and a second number of sign bits. This method also includes the step of adding to each second multi-bit digital signal to develop a series of third multi-bit digital signals each individually associated with one of the second multi-bit digital signals and each having the same number of data bits as in an associated second multi-bit digital signal a multi-bit digital signal that has been developed from a selected number of the least significant bits of the third multi-bit digital signals and delayed by a period of time equal to twice the time between successive first multi-bit digital signals and inverted and a multi-bit digital signal that has been developed from the selected number of the least significant bits of the third multi-bit digital signals and delayed by a period of time equal to the time between successive first multi-bit digital signals and multiplied by a multiplier number related to the ratio of a selected frequency to the frequency of the first multi-bit digital signals. A series of fourth digital signals each having a selected number of the most significant data bits of the third multi-bit digital signals is developed from the third multi-bit digital signals. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]      FIG. 1  is a block diagram of a bandpass delta sigma truncator constructed in accordance with the present invention.  
         [0008]      FIG. 2  shows the noise level of data of signals directly truncated to six bits.  
         [0009]      FIG. 3  shows the noise level of data truncated to six bits by a bandpass delta sigma truncator constructed in accordance with the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0010]     Referring to  FIG. 1 , a bandpass delta sigma truncator, constructed in accordance with the present invention, includes input means for receiving a series of first multi-bit digital signals each having a number of data bits and a first number of sign bits. Such means are represented by an input terminal  20  connected, for example, to a baseband processor (not shown) from which the series of first multi-bit digital signals are supplied.  
         [0011]     The bandpass delta sigma truncator of the present invention also includes sign extending means for sign extending each of the first multi-bit digital signals to a second multi-bit digital signal having the same number of data bits as the number of data bits in the first multi-bit digital signals and a second number of sign bits. Such means can be a sign extender  22  of conventional construction and operation. As will become clear below, the sign extension function serves to detect overflow or underflow as the first multi-bit digital signals are modified in accordance with the present invention.  
         [0012]     The  FIG. 1  bandpass delta sigma truncator further includes output means for supplying from a series of third multi-bit digital signals each individually associated with one of the second multi-bit digital signals and each having the same number of data bits as in an associated second multi-bit digital signal a series of fourth multi-bit digital signals each having a selected number of the most significant data bits of the third multi-bit digital signals and a series of fifth multi-bit digital signals each having the remaining number of the least significant data bits of the third multi-bit digital signals. Such output means are represented by an output terminal  24  connected, for example, to a digital-to-analog converter (not shown) to which the fourth multi-bit digital signals are supplied. The manner in which the series of third multi-bit digital signals is developed is explained below.  
         [0013]     Also included in the  FIG. 1  bandpass delta sigma truncator are means for delaying by a period of time equal to the time between successive first multi-bit digital signals each of the fifth multi-bit digital signals and delaying by a period of time equal to twice the time between successive first multi-bit digital signals each of the fifth multi-bit digital signals and inverting the fifth multi-bit digital signals that have been delayed by a period of time equal to twice the time between successive first multi-bit digital signals. For the embodiment of the invention being described, such means include a digital delay circuit  26  for delaying by a period of time equal to the time between successive first multi-bit digital signals each of the fifth multi-bit digital signals and a digital delay and inverter circuit  28  for additionally delaying by a period of time equal to the time between successive first multi-bit digital signals each of the fifth multi-bit digital signals delayed by digital delay circuit  26  and inverting the additionally delayed fifth multi-bit digital signals. Digital delay circuit  26  and digital delay and inverter circuit  28  can be of conventional construction and operation.  
         [0014]     The  FIG. 1  bandpass delta sigma truncator further includes means for multiplying by a multiplier number related to the ratio of a selected frequency to the frequency of the first multi-bit digital signals each of the fifth multi-bit digital signals delayed by a period of time equal to the time between successive first multi-bit digital signals and developing a series of sixth multi-bit digital signals having a number of data bits that is the product of the multiplier number and the number of data bits in the fifth multi-bit digital signals. Specifically, each fifth multi-bit digital signal delayed by delay circuit  26  is multiplied by a multiplier  30  of conventional construction and operation.  
         [0015]     A bandpass delta sigma truncator, constructed in accordance with the present invention, further includes summing means for adding to each second multi-bit digital signal delivered by sign extender  22  a fifth multi-bit digital signal that has been delayed by a period of time equal to twice the time between successive first multi-bit digital signals and inverted and a sixth multi-bit digital signal to develop the series of third multi-bit digital signals. Such summing means can be a summing circuit  32  of conventional construction and operation.  
         [0016]     A bandpass delta sigma truncator, constructed in accordance with the present invention, preferably includes means between summing circuit  32  and output terminal  24  for determining whether the value of the output of the summing circuit, namely the third multi-bit digital signal, is either greater than a first value or less than a second value. Such means can be an overflow/underflow detector  32  of conventional construction and operation. Overflow/underflow detector  34  serves to prevent the delta sigma truncator from becoming unstable.  
         [0017]     As indicated above, for:  
         [0018]     (a) the 5 MHZ ACLR specification, a ten bit digital-to-analog converter is required in the signal processing circuitry;  
         [0019]     (b) the 10 MHZ ACLR specification, a six bit digital-to-analog converter can be used in the signal processing because the signals can be truncated at a lowpass filter located downstream from the delta sigma truncator; and  
         [0020]     (c) the EVM specification, a six bit digital-to-analog converter can be used in the signal processing.  
         [0021]     In the preferred signal processing circuitry, the digital-to-analog converter is a six bit unit. Simply dropping the four least significant bits of each input ten bit digital signal results in six bit resolution which is inadequate for the 5 MHZ ACLR specification that requires ten bit resolution.  
         [0022]     For a selected WCDMA application of a bandpass delta sigma truncator, constructed in accordance with the present invention:  
         [0023]     (a) each first multi-bit digital signal supplied to input terminal  20  is a ten bit digital signal having nine data bits and one sign bit,  
         [0024]     (b) each second multi-bit digital signal developed by sign extender  22  is an eleven bit digital signal having nine data bits and two sign bits,  
         [0025]     (c) each third multi-bit digital signal developed by summing circuit  32  is a nine bit digital signal having nine data bits,  
         [0026]     (d) each fourth multi-bit digital signal that is outputted from the bandpass delta sigma truncator is a six bit digital signal having six data bits,  
         [0027]     (e) each fifth multi-bit digital signal delivered to digital delay circuit  26  is a three bit digital signal having three data bits,  
         [0028]     (f) each sixth multi-bit digital signal developed by multiplier  30  is a four bit digital signal having four data bits,  
         [0029]     (g) the multiplier number of multiplier  30  is 1.75,  
         [0030]     (h) the selected frequency is 5 MHZ, and  
         [0031]     (i) the frequency of the first multi-bit digital signals is 30 MHZ.  
         [0032]     The multiplier number of 1.75 is derived as follows. For zero noise shaping at 5 MHZ and a sampling frequency of 60 MHZ  
           5   ⁢           ⁢   MHZ       60   ⁢           ⁢   MHZ       =       cos   ⁢           ⁢   30   ⁢   °       cos   ⁢           ⁢   360   ⁢   °           
         2   ⁢           ⁢   cos   ⁢           ⁢   30   ⁢   °     =       sqrt   ⁢           ⁢   3     =   1.73         
 
 1.73 is approximately 1.75. 
 
         [0033]     The 1.75 multiplication by multiplier  30  of the three bit digital signal delivered to the multiplier is accomplished by multiplying the three bit digital signal, subtracting the three bit digital signal, and dividing the result by four (bit shifting operation in digital operation):  
             8   ⁢     (     three   ⁢           ⁢   bit   ⁢           ⁢   digital   ⁢           ⁢   signal     )       -     (     three   ⁢           ⁢   bit   ⁢           ⁢   digital   ⁢           ⁢   signal     )       4     =       7   4     =   1.75         
 
         [0034]     Overflow/underflow detector  34  detects an overflow when the tenth bit of the output from summing circuit  32  becomes a “1” and overflow/underflow detector  34  detects an underflow when the eleventh bit of the output from summing circuit  32  becomes a “1”. When an overflow condition is detected, the nine data bits of the output from summing circuit  32  become “1”s and when an underflow condition is detected (i.e., a negative value), the nine data bits of the output from summing circuit  32  become “0”s. Although the data in the signals is destroyed when an overflow condition or an underflow condition is detected, because this occurs so infrequently, there is no meaningful adverse effect on the overall transmission of data.  
         [0035]      FIG. 2  shows the noise level data directly truncated to six bits. The noise level at 5 MHZ is much higher than the 5 MHZ ACLR specification.  
         [0036]      FIG. 3  shows the noise level of data truncated to six bits by a bandpass delta sigma truncator constructed in accordance with the present invention. The noise level at 5 MHZ is bottoms at approximately the 5 MHZ ACLR specification with a shift in the noise level to higher frequencies at which the noise can be removed by filters.  
         [0037]     Although illustrated and described herein with reference to an exemplary embodiment, the present invention, nevertheless, is not intended to be limited to the details shown and described. Rather, various modifications may be made to the exemplary embodiment within the scope and range of equivalents of the claims without departing from the invention.