Abstract:
A method is provided for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer. The method includes selecting a periodicity for the second wafer to be manufactured that matches the periodicity of the first wafer. The method further includes manufacturing the second wafer in accordance with the selected periodicity. The method also includes placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer. The method additionally includes stacking the first wafer onto the second wafer using a bonding material.

Description:
BACKGROUND 
     Technical Field 
     The present invention generally relates to semiconductor devices, and more particularly to heterogeneous integration using wafer-to-wafer stacking with die size adjustment. 
     Description of the Related Art 
     Sensors combined with integrated logic circuits are key components of intelligent systems. Such systems are characterized by real-time, high-bandwidth processing, requiring high interconnect density and close-proximity coupling between the sensor elements and the logic processing elements. Additionally, compact form factor and low power are highly desirable attributes for mobile applications. 
     Three-dimensional (3D) Wafer-to-Wafer stacking offers the potential for much higher interconnect densities than either conventional two-dimensional (2D) packaging or 3D chip-to-chip stacking. In particular, compared to chip-to-chip stacking, wafer-to-wafer stacking enables scaling down of the interconnect dimension and pitch through thinning down of the wafer, which allows preservation of the via aspect ratio. 
     However, sensors and logic processors are fabricated on different wafers using appropriately optimized technologies. Thus, the die sizes on the two wafers are unlikely to be equal, precluding wafer-to-wafer bonding. Hence, there is a need for heterogeneous circuit integration using wafer-to-wafer stacking for situations including, e.g., wafers with differently sized dies. 
     SUMMARY 
     According to an aspect of the present principles, a method is provided for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer. The method includes selecting a periodicity for the second wafer to be manufactured that matches the periodicity of the first wafer. The method further includes manufacturing the second wafer in accordance with the selected periodicity. The method also includes placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer. The method additionally includes stacking the first wafer onto the second wafer using a bonding material. 
     According to another aspect of the present principles, a non-transitory computer readable storage medium is provided. The non-transitory computer readable storage medium includes a computer readable program for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer. The computer readable program when executed on a computer causes the computer to perform a method. The method includes selecting a periodicity for the second wafer to be manufactured that matches the periodicity of the first wafer. The method further includes manufacturing the second wafer in accordance with the selected periodicity. The method also includes placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer. The method additionally includes stacking the first wafer onto the second wafer using a bonding material. 
     These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       The disclosure will provide details in the following description of preferred embodiments with reference to the following figures wherein: 
         FIG. 1  shows exemplary component wafers  100  to which the present principles can be applied, in accordance with an embodiment of the present principle; 
         FIG. 2  shows a flowchart for an initial part of a method for heterogeneous integration using wafer-to-wafer stacking with die size adjustment, in accordance with an embodiment of the present principles; 
         FIG. 3  graphically shows the second wafer at a process step where pattern density is deemed critical, in accordance with an embodiment of the present principles; 
         FIG. 4  graphically shows the second wafer at a process step where another printing/exposing step is performed such that the white space between the chips (dies) of the second wafer is filled with a pattern by a laser tool; 
         FIG. 5  shows a flowchart for a subsequent part of a method for heterogeneous integration using wafer-to-wafer stacking with die size adjustment, in accordance with an embodiment of the present principles; 
         FIG. 6  graphically shows the first wafer and the temporary carrier in preparation for bonding, in accordance with an embodiment of the present principles; 
         FIG. 7  graphically shows the thin first wafer, in accordance with an embodiment of the present principles; 
         FIG. 8  graphically shows the second wafer bonded to the thin first wafer using permanent adhesive, in accordance with an embodiment of the present principles; 
         FIG. 9  graphically shows the thin first wafer bonded to the second wafer, with the temporary carrier removed, in accordance with an embodiment of the present principles; 
         FIG. 10  shows a wafer-to-wafer bonding, in accordance with an embodiment of the present principles; 
         FIG. 11  shows a wafer-to-wafer bonding having a first die stacked on a second die, where the second die is an image sensor that receives backside illumination, in accordance with an embodiment of the present principles; 
         FIG. 12  shows a flowchart for a subsequent part of a method for heterogeneous integration using wafer-to-wafer stacking with die size adjustment, in accordance with an embodiment of the present principles; 
         FIG. 13  graphically shows the first wafer and the second wafer in preparation for bonding, in accordance with an embodiment of the present principles; 
         FIG. 14  graphically shows the thin first wafer, in accordance with an embodiment of the present principles; and 
         FIG. 15  shows a wafer-to-wafer bonding having a first die stacked on a second die, where the second die is an image sensor that receives backside illumination, in accordance with an embodiment of the present principles. 
     
    
    
     DETAILED DESCRIPTION 
     The present principles are directed to heterogeneous integration using wafer-to-wafer stacking with die size adjustment. 
     In an embodiment, the present principles use a single mask set to realize a wafer, where the chip periodicity (die-to-die pitch) can be selected at the time of manufacturing to enable heterogeneous wafer stacking. 
       FIG. 1  shows exemplary component wafers  100  to which the present principles can be applied, in accordance with an embodiment of the present principles. 
     The exemplary component wafers  100  include a first component wafer (hereinafter “first wafer”)  110  and a second component wafer (hereinafter “second wafer”)  120 . 
     The first wafer  110  is formed using a larger die than the second component wafer  120 . The first wafer is printed using a mask set  1 . 
     The second wafer  120  is formed using a smaller die than the first component wafer  110 . The second wafer is printed using a mask set  2 . 
     For the sake of illustration, the first wafer can be considered to be a logic wafer and the second wafer can be considered to be a sensor wafer. Of course, the first wafer and the second wafer can pertain to other types of circuits, while maintaining the spirit of the present principles. 
     In some of the FIGURES described herein, an arrow adjacent a wafer or a die indicates the orientation thereof, with the arrow pointing from the back of the item (corresponding to the arrow end) to the front of the item (corresponding to the arrow head). Moreover, various layers are depicted in some of the FIGURES described herein. It is to be appreciated that the thicknesses of these layers are shown at an arbitrary thicknesses for the sake of illustration and can thus vary depending upon the implementation. 
     Hereinafter,  FIG. 2  describes method steps for an initial part  201  of a method  200  for heterogeneous integration using wafer-to-wafer stacking with die size adjustment.  FIG. 5  describes method steps for a subsequent part  202  of method  200 , while  FIG. 6  describes method steps for another subsequent part  203  of method  200 . Either subsequent part  202  or subsequent part  203  is performed after initial part  201  in order to form a wafer-to-wafer bonding in accordance with the present principles. That is, subsequent part  202  corresponds to one way to complete the heterogeneous integration commenced by initial part  201 , while subsequent part  203  corresponds to another way to complete the heterogeneous integration commenced by initial part  201 . 
       FIG. 2  shows a flowchart for an initial part  201  of a method  200  for heterogeneous integration using wafer-to-wafer stacking with die size adjustment, in accordance with an embodiment of the present principles. 
     At step  210 , at the time of manufacturing of the second wafer  120 , select a periodicity for the second wafer  120  that is equal to the periodicity of the chip (of the first wafer  110 ) and print/process the second wafer  120 . Thus, the dies from the second wafer  120  are printed at the periodicity of the first wafer  110  using mask set  2 . 
       FIG. 3  graphically shows the second wafer  120  at a process step  210 A (corresponding to the processing performed at step  210  of method  200  of  FIG. 2 ) where pattern density is deemed critical, in accordance with an embodiment of the present principles. 
     At step  220 , at a time when the pattern density at a process step is deemed critical (e.g., as shown with respect to process step  210 A in  FIG. 3 ), perform another printing/exposing step with a laser tool that places a pattern  499  in the white space between the chips (dies) of the second wafer  120 . The pattern  499  is depicted using diagonal hatching in  FIG. 4 . In an embodiment, the pattern  499  can be used to meet pattern density requirements. 
       FIG. 4  graphically shows the second wafer  120  at a process step  220 A where another printing/exposing step is performed such that the white space between the chips (dies) of the second wafer  120  is filled with a pattern  499  by a laser tool. The pattern  499  is shown using diagonal hatching. 
       FIG. 5  shows a flowchart for a subsequent part  202  of a method  200  for heterogeneous integration using wafer-to-wafer stacking with die size adjustment, in accordance with an embodiment of the present principles. 
     At step  230 , stack wafers that have the same periodicity. Thus, given step  210  above, stack the first wafer  110  and the second wafer  120 . Thus, relative to a given “starting wafer”, one or more other wafers are stacked thereon that periodicity that match the periodicity of the starting wafer (but not the chip). 
     In an embodiment, step  230  includes steps  230 A- 230 D. 
     At step  230 A, bond the first wafer  110  face down onto a temporary carrier  601  using a temporary adhesive  602 .  FIG. 6  graphically shows the first wafer  110  and the temporary carrier  601  in preparation for bonding per step  230 A, in accordance with an embodiment of the present principles. The result of step  230 A is a thin first wafer  110 T (hereinafter interchangeably referred to as “first wafer” followed by the reference numeral  110 T to distinguish from the “non-thin” first wafer  110  from which the “thin” first wafer is formed at step  230 A). The first wafer is thinned using one or more known standard techniques such as mechanical grinding, chemical metal polishing, and wet and dry etching.  FIG. 7  graphically shows the thin first wafer  110 T resulting from step  230 A, in accordance with an embodiment of the present principles. 
     At step  230 B, flip and bond the second wafer  120  to the thin first wafer  110 T using permanent adhesive  802 .  FIG. 8  graphically shows the second wafer  120  bonded to the thin first wafer  110 T using permanent adhesive  802 , in accordance with an embodiment of the present principles. The term “permanent” in “permanent adhesive” is used to contrast the bonding at this step ( 230 B) versus the bonding of step  230 A which involved a “temporary adhesive”. Thus, any more resilient bonding than a temporary adhesive/bonding can be used as element  802  such as, for example, an oxide-to-oxide bonding, and so forth, as readily appreciated by one of ordinary skill in the art. 
     At step  230 C, remove the temporary carrier  601  (and also remove the temporary adhesive  602  used to bond the temporary carrier  601  to the first wafer  110 ).  FIG. 9  graphically shows the thin first wafer  110 T bonded to the second wafer  120  (using the permanent adhesive  802 ), with the temporary carrier  601  (and temporary adhesive  602 ) removed, in accordance with an embodiment of the present principles. 
       FIG. 10  shows a wafer-to-wafer bonding  1000 , in accordance with an embodiment of the present principles. The wafer-to-wafer bonding  1000  can be formed, e.g., subsequent to step  230 C (or subsequent to step  230 D). 
     Starting from a back side  1099  to a front side  1001 , the bonding  1000  includes: a second wafer  120  (e.g., image sensor), with its backside first (closest to backside  1099 ); a second wafer BEOL  1021 ; a backside oxide  1030 ; a thin first wafer  110 T (e.g., logic wafer) with its backside first (closest to backside  1099 ); a first wafer BEOL  1011 ; and a metal above Through-Silicon Via (TSV) layer  1040 . 
     In the bonding  1000 , a TSV  1070  is formed through the thin first wafer  110 T to contact the second wafer  120 . The metal above TSV layer  1040  and a pillar  1080  are added for external contact/connection. Metallization in the second wafer BEOL  1021 , the first wafer BEOL  1011 , and the metal above TSV layer  1040  is generally indicated by the reference numeral  1090 . 
     At step  230 D, flip, singulate, and package the wafer-to-wafer bonding. In this way, it is possible to realize a low form-factor. 
     In an embodiment, the wafer-to-wafer bonding can include a backside illuminated image sensor with ultrahigh interconnect density.  FIG. 11  shows a wafer-to-wafer bonding  1100  having a first die  1101  (from thin wafer  110 T) stacked on a second die  1102  (from second wafer  120 ), where the second die  1102  is an image sensor that receives backside illumination, in accordance with an embodiment of the present principles. Solder bumps  1177  are used to connect the stacked dies to packaging  1188  having external connections (not shown, see  FIG. 10  for an exemplary external connection configuration). 
       FIG. 12  shows a flowchart for a subsequent part  203  of a method  200  for heterogeneous integration using wafer-to-wafer stacking with die size adjustment, in accordance with an embodiment of the present principles. Subsequent part  203  can be performed in place of subsequent part  202  shown in  FIG. 5 . 
     At step  1230 , stack wafers that have the same periodicity. Thus, given step  210  above, stack the first wafer  110  and the second wafer  120 . Thus, relative to a given “starting wafer”, one or more other wafers are stacked thereon that periodicity that match the periodicity of the starting wafer (but not the chip). 
     In an embodiment, step  1230  includes steps  1230 A- 1230 C. 
     At step  1230 A, bond the first wafer  110  to the second wafer  120  in a face-to-face configuration with the first wafer  110  face down. In an embodiment, a copper-to-copper (Cu—Cu) bonding process is used.  FIG. 13  graphically shows the first wafer  110  and the second wafer  120  in preparation for bonding per step  230 A, in accordance with an embodiment of the present principles. 
     At step  1230 B, thin the first wafer  110  using the second wafer  120  as a handle. The result of step  1230 B is a “thin” first wafer  110 TT, relative to first wafer  110  prior to “thinning” per step  1230 B.  FIG. 14  graphically shows the thin first wafer  110 TT resulting from step  1230 B, in accordance with an embodiment of the present principles. 
     At step  1230 C, flip, singulate, and package the wafer-to-wafer bonding. In this way, it is possible to realize a low form-factor. 
     In an embodiment, the wafer-to-wafer bonding can include a backside illuminated image sensor with ultrahigh interconnect density.  FIG. 15  shows a wafer-to-wafer bonding  1500  having a first die  1501  (from thin wafer  110 TT) stacked on a second die  1502  (from second wafer  120 ), where the second die  1502  is an image sensor that receives backside illumination, in accordance with an embodiment of the present principles. Solder bumps  1577  are used to connect the stacked dies to packaging  1588  having external connections (not shown, see  FIG. 10  for an exemplary external connection configuration). 
     It is to be appreciated that while some of the FIGURES described herein mention and/or otherwise involve a particular type of bonding material, the present principles are not limited to solely such materials and, thus, other bonding materials can also be used in accordance with the teachings of the present principles, while maintaining the spirit of the present principles. 
     Moreover, it to be appreciated that while some of the FIGURES described herein mention and/or otherwise involve the use of a laser tool for patterning, the present principles are not limited to solely such patterning technique and, thus, any patterning technique can be used in accordance with the teachings of the present principles, while maintaining the spirit of the present principles. 
     A description will now be given regarding some of the many attendant advantages of the present principles. 
     The cost of the increased Silicon (Si) wafer area required for die-size adjustment is offset by the following significant advantages of wafer-to-wafer integration versus state-of-the-art techniques: volume production; high bandwidth; compact form factor; and lower power. 
     Regarding volume prediction, the sensor and processor chips are all bonded in parallel, in contrast to die-to-die bonding in which the bonding is done sequentially. Since wafer bonding means all chips are joined in parallel, a high process yield is essential to cost reduction. Accurate wafer-to-wafer alignment is also critical. 
     Regarding high bandwidth, micro-bump pitch is typically ˜50 um with a ˜20 um bump size. Wafer-to-wafer bonding enables much smaller interconnect size (˜1 um) and much higher density (pitch ˜2 um). This higher interconnect density allows direct coupling of a sensor to a processor underneath. 
     Regarding compact form factor, direct wafer-to-wafer bonding, in which one wafer is thinned, is much more compact than die-to-die bonding having a layer of micro-bumps in between. This is desirable for mobile applications. 
     Regarding lower power, shorter wire lengths result in lower power dissipation, which is also highly desirable for mobile applications. 
     The present invention may be a system, a method, and/or a computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention. 
     The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire. 
     Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device. 
     Computer readable program instructions for carrying out operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The computer readable program instructions may execute entirely on the user&#39;s computer, partly on the user&#39;s computer, as a stand-alone software package, partly on the user&#39;s computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user&#39;s computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention. 
     Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions. 
     These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks. 
     The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks. 
     The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions. 
     Reference in the specification to “one embodiment” or “an embodiment” of the present principles, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present principles. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment”, as well any other variations, appearing in various places throughout the specification are not necessarily all referring to the same embodiment. 
     It is to be appreciated that the use of any of the following “/”, “and/or”, and “at least one of”, for example, in the cases of “A/B”, “A and/or B” and “at least one of A and B”, is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C”, such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This may be extended, as readily apparent by one of ordinary skill in this and related arts, for as many items listed. 
     Having described preferred embodiments of a system and method (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.