Abstract:
A CMOS or bipolar based Ion Sensitive Field Effect Transistor (ISFET) comprising an ion sensitive recess for holding a liquid wherein the recess is formed at least partly on top of a gate of the transistor. There is also provided a method of manufacturing an I on Sensitive Field Effect Transistor (ISFET) utilizing CMOS processing steps, the method comprising forming an ion sensitive recess for holding a liquid at least partly on top of a gate of the transistor.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation of International Patent Application Number PCT/EP2011/057359 filed on 6 May 2011, the contents of which are herein incorporated by reference in their entirety. 
     
    
     TECHNICAL FIELD 
       [0002]    The present invention relates to an Ion Sensitive Field Effect Transistor (ISFET), and in particular to an ISFET manufactured utilizing CMOS or bipolar processing steps. 
       BACKGROUND 
       [0003]    Electronic devices and components have found numerous applications in measurement and monitoring of chemical or biological reactions such as detecting concentration, presence and activity of particular ions, enzymes, antibodies, antigens, hormones and gases. One such electronic device is referred to as an Ion Sensitive Field Effect Transistor, often denoted in the relevant literature as ISFET. This device facilitates the measurement, for example, of a hydrogen ion concentration (i.e. pH) in a solution. 
         [0004]      FIG. 1  is a schematic cross-section of a conventional ISFET. This device is similar to a MOSFET and comprises a semiconductor substrate  141 , a source  147  and a drain  145 . The source  147  is spaced from the drain  145  and both are located near the surface of substrate  141 . A channel region  152  is located between the source  147  and the drain  145  in the substrate  141 . Inter alia in the channel region  152 , the surface of the substrate  141  is covered by an insulator  101  and an ion sensitive thin layer or membrane  150  on top of the insulator  101 . When the ion sensitive membrane  150  is exposed to an ionic solution, the surface potential is changed to vary the conductance of the channel region  152 . By measuring the current between the source  147  and the drain  145 , information such as the ion concentration of a chemical or biological reaction can be derived. 
         [0005]    Another structure has been demonstrated which uses a MOSFET structure and connects a gate poly and an ion sensitive membrane by metal. When the surface potential of the membrane is changed due to the ion concentration or pH value of the solution, the gate voltage of the MOSFET is also changed. Information about chemical and biological reactions can then be extracted by monitoring the electric signal from the MOSFET. 
         [0006]    A conventional ISFET needs a micro-well or recess for the chemical solutions. In this conventional ISFET, the recess needs to be well connected to the channel area of the ISFET. Further, a discrete signal readout circuit is generally employed for analyzing the signal readout from the conventional ISFET. The discrete signal readout circuit is arranged separately (i.e. not on the same chip) and connected to the conventional ISFET. Normally a printed circuit board (PCB) or wiring is used for connecting the discrete read out circuit with the conventional ISFET. The inventors have appreciated that no techniques exist which combine a conventional ISFET with signal on chip (SOC) technology using a standard CMOS process. 
       BRIEF SUMMARY 
       [0007]    The present inventors have found that the above conventional technique may result in relatively high manufacturing costs and increased noise in the readout. 
         [0008]    It is an aim of certain embodiments of the present invention to provide an ISFET structure which improves signal readout performance and reduces manufacturing cost. 
         [0009]    According to one aspect of the present invention there is provided a CMOS or bipolar based Ion Sensitive Field Effect Transistor (ISFET) comprising an ion sensitive recess for holding a liquid wherein the recess is formed at least partly on top of a gate of the transistor. 
         [0010]    According to another aspect of the present invention there is provided a method of manufacturing an Ion Sensitive Field Effect Transistor (ISFET) utilizing CMOS or bipolar processing steps, the method comprising forming an ion sensitive recess for holding a liquid at least partly on top of a gate of the transistor. 
         [0011]    Preferably, the recess is formed directly on a surface of the gate. In some embodiments, a minimum contact area between the gate surface and the recess in a 0.35 μm CMOS technology is about 10 or 16 μm 2 . Alternatively, one or more additional layers may be arranged between the gate and the recess surface. The additional layer(s) may comprise a material which is selected from any of: titanium nitride (TiN), silicon oxide nitride (SiON), silicon oxide (SiO 2 ) or a metal. Such an additional layer may improve the performance of the ISFET. Alternatively, the recess may be arranged such that there are interlayer dielectric and intermetal dielectric between the recess and gate. 
         [0012]    The gate may consist of an insulator. Alternatively, the gate consists of an insulator and a poly gate on top of the insulator. 
         [0013]    In some embodiments, the present invention provides a new method for integrating the ISFET in a standard CMOS or bipolar process. These embodiments comprise: (1) building up a standard CMOS or bipolar device with inter-connect metal and inter-metal dielectric films on a semiconductor substrate; (2) patterning and etching away the dielectric above an area of the ISFET down to an insulator or a poly gate; and (3) depositing an ion sensitive membrane such as a silicon nitride film covering the insulator gate oxide or poly gate. A standard bipolar device can be used in the signal read out circuit of the ISFET. 
         [0014]    Advantageously, the integrated CMOS or bipolar process can be optimized such that the ISFET provides high performance ion detection. The CMOS or bipolar based ISFET according to embodiments of the invention enables the ion sensitive recess and signal readout circuit to be integrated within a single chip. Since the signal transmission and processing are performed on the same chip, these operations are relatively fast and produce less noise than the conventional ISFET. As a result, the signal readout or sensitivity of the ISFET is improved. The improvement in the signal readout or sensitivity of the ISFET is particularly noticeable if the ion sensitive recess is fabricated directly on top of the gate of the ISFET. The utilization of the standard CMOS process may also result in low manufacturing cost. Furthermore, the invention enables the ISFET fabrication in arrays. Therefore, the on-die analysis of a biological reaction and ion concentration becomes easier and cheaper. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]    Some embodiments of the invention will now be described by way of example only and with reference to the accompanying drawings, in which: 
           [0016]      FIG. 1  is a schematic cross-section of a conventional ISFET; 
           [0017]      FIG. 2  is a schematic cross section of an ISFET at one stage of the fabrication according to a first embodiment of the present invention; 
           [0018]      FIG. 3  is a schematic cross section of an ISFET at a second stage of the fabrication according to the first embodiment of the present invention; 
           [0019]      FIG. 4  is a schematic cross section of an ISFET at a third stage of the fabrication according to the first embodiment of the present invention; 
           [0020]      FIG. 5  is a schematic cross section of an ISFET at one stage of the fabrication according to a second embodiment of the present invention; 
           [0021]      FIG. 6  is a schematic cross section of an ISFET at a second stage of the fabrication according to the second embodiment of the present invention; 
           [0022]      FIG. 7  is a schematic cross section of an ISFET at a third stage of the fabrication according to the second embodiment of the present invention; 
           [0023]      FIG. 8   a  shows a top view of an ISFET according to the present invention; 
           [0024]      FIG. 8   b  shows an alternative top view; and 
           [0025]      FIG. 8   c  shows a further alternative top view. 
       
    
    
     DETAILED DESCRIPTION 
       [0026]      FIG. 2  is a schematic cross section of an ISFET at one stage of the fabrication according to a first embodiment of the present invention. A basic CMOS device is provided comprising a semiconductor substrate  141  having a source  147 , a drain  145  and a channel region  152  between the source  147  and the drain  145 . A gate consisting of an insulator  101  is located on top of the channel region  152 . In certain embodiments, the thickness of the insulator is not less than about 5 nm and is not more than about 150 nm. The thickness of the insulator is preferably about 50 nm or 55 nm. The device also comprises inter-layer dielectric (ILD)  111  covering the insulator  101  and the substrate  141 . Inter-metal dielectrics (IMD)  112 ,  113  are provided on top of the ILD  111 . Inter metals  131  and  131   a  are provided on top of the ILD  111  within IMD  112 . Inter metal  131  is connected with the source  147  by contact plug  121 , and inter metal  131   a  is connected with the drain  145  by contact plug  121   a.  Further inter metals  132 ,  132   a  and  133 ,  133   a  are located on top of IMDs  112  and  113 . Inter metals  131  and  132  are connected with one another by inter layer via  122 , and inter metals  131   a  and  132   a  are connected with one another by inter layer via  122   a.  Similarly, inter metal  132  and top inter metal  133  are connected by inter layer via  123 , and inter metal  132   a  and top inter metal  133   a  are connected by inter layer via  123   a.  A passivation layer  104  is provided on top of IMD  113 . 
         [0027]    In the CMOS device of  FIG. 2 , the source  147 , drain  145 , channel region  152  and insulator layer  101  are also parasitically fabricated at the same time with the CMOS process. It will be appreciated that, in the CMOS process, the insulator layer (gate oxide), poly gate, channel implant, source and drain can be fabricated using a standard process for a MOS device. This standard process can also be utilized to fabricate the ISFET. The device is connected with inter metals  131 ,  131   a,    132 ,  132   a,    133 ,  133   a  and contact plugs  121 ,  121   a,  inter layer vias  122 ,  122   a,    123 ,  123   a  for the electric monitoring. A volume  160  is defined over insulator  101  of the gate, over an area  103 . No metal connections are located in this volume  160 . This area  103  is therefore only covered by ILD  111 , IMDs  112  and  113  and passivation layer  104  during the standard CMOS manufacturing process. 
         [0028]      FIG. 3  is a schematic cross section of an ISFET at a second stage of the fabrication according to the first embodiment of the present invention. At this stage, the process includes opening a window or recess  107  by patterning the area  103  (as shown in  FIG. 1 ) over the gate and then by etching the dielectric layers (ILD  111 , IMDs  112 ,  113  of  FIG. 1 ) of the area  103 . The etching process may be performed by a dry etch technique, a wet etch technique or an optical window etch technique. The etching process stops on the insulator  101  of the gate. 
         [0029]    It will be appreciated that according to a variant the second stage of the fabrication may include the sequential steps of: etching the entire passivation layer  104  along with inter-layer metals  133 , and  133   a;  etching the entire IMD  133  with inter metals  132  and  132   a;  etching the area  103  down to the insulator  101  to open a recess  107  by the OPTO window etch technique. 
         [0030]      FIG. 4  is a schematic cross section of an ISFET at a third stage of the fabrication according to the first embodiment of the present invention. At this stage, an ion sensitive membrane or thin film  105  is deposited on at least a portion of the surface of the recess  107 . Preferably, the membrane  105  is deposited over the entire surface of the recess  107  and connects to at least a part of the surface of the insulator  101 . It will be appreciated that according to a variant the membrane  105  may only cover the insulator  101  rather than fully covering the whole recess  107 . The membrane  105  may comprise any one or more of a variety of different materials to facilitate sensitivity to particular ions. For example, silicon nitride or silicon oxynitride generally provides sensitivity to hydrogen ion concentration (pH). 
         [0031]    At a final stage, the CMOS device (or the entire CMOS wafer) can be further processed by removing the passivation at a pad area, which is subsequently used for wire bonding. It will be appreciated that this process can also be performed before the ISFET recess opening and membrane deposition. 
         [0032]      FIG. 5  is a schematic cross section of an ISFET at one stage of the fabrication according to a second embodiment of the present invention. All the features of the CMOS device of  FIG. 5  are similar to those of the CMOS device of  FIG. 2 , except that an additional poly gate  102  is provided on top of the insulator  101 . 
         [0033]      FIG. 6  is a schematic cross section of an ISFET at a second stage of the fabrication according to the second embodiment of the present invention. The fabrication steps for this embodiment are the same as those described in relation to  FIG. 3 , except that the etching of the dielectric area  103  (of  FIG. 5 ) is carried out down to the surface of the poly gate  102 . 
         [0034]      FIG. 7  is a schematic cross section of an ISFET at a third stage of the fabrication according to the second embodiment of the present invention. The fabrication steps for this embodiment are also the same as those described in relation to  FIG. 4 , except that the ion sensitive membrane  105  is deposited over the entire recess surface to connect it with the surface of the poly gate  102 . 
         [0035]      FIG. 8   a  shows a top view of an ISFET such as the ISFET of  FIG. 7 . Only the passivation layer  104  and the recess  107  are shown. In this embodiment, the recess  107  is fully surrounded by the passivation layer  104 , i.e. the recess  107  is surrounded by five sides of the ISFET (four laterally, and the bottom of the recess). 
         [0036]      FIG. 8   b  shows a top view of an ISFET arrangement having an array of ISFETs. In this arrangement, each ISFET of the array is the same as the ISFET of  FIG. 7 . Only the passivation layer  104  and the recess  107  are shown. In this embodiment, the recess  107  is fully surrounded by the passivation layer  104 , i.e. the recess  107  is surrounded by five sides of the ISFET (four laterally, and the bottom of the recess). 
         [0037]      FIG. 8   c  shows a further alternative top view of an ISFET arrangement having an array of ISFETs. Only the passivation layer  104  and the recess  107  are shown. In this embodiment, the structure/shape of the recess  107  is different from that shown in  FIG. 8   b . It will be appreciated that the structure/shape of the recess  107  is not limited to a regular structure/shape such as a rectangular or circular structure/shape. 
         [0038]    It will be noted that the first and second embodiments described above are directed to arrangements having the recess formed directly on the surface of the gate. It will be appreciated that alternatively the recess may be arranged such that it is not located directly on the surface of the gate. For example, the recess can be formed on the surface of IMD  112  so that IMD  112  and ILD  111  are between the recess and the gate. It may be also possible that the recess is formed such that the surface of the recess is located above inter metals  131 ,  131   a,    132  and  132   a  but below top inter metals  133  and  133   a.  In such an arrangement, there may be a further inter metal above inter metals  131 ,  131   a,    132  and  132   a  and below top inter metals  133  and  133   a,  and the recess is located above the further inter metal but below the top inter metals  133  and  133   a.    
         [0039]    It will be also noted that the foregoing description is generally directed to arrangements having a poly gate. It will be appreciated that the poly gate may comprise poly silicon or any other semiconductor materials. 
         [0040]    It will be also noted that the first and second embodiments described above are directed to ISFET arrangements which are manufactured using a CMOS manufacturing process. It will be appreciated that the ISFET arrangements can also be manufactured using standard bipolar processing steps. 
         [0041]    Although the invention has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the invention, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.