Abstract:
A logical circuit device has a MOS transistor having a source region, a drain region, a channel region defined between the source region and the drain region, and a gate electrode formed above the channel region, respectively formed on a semiconductor substrate. The amplitude of a voltage applied to the gate electrode necessary for making the channel region conductive is not level throughout the channel region in the width direction. Using such a logical circuit device, flip-flop circuits and storage circuits of a multivalued logic type can be realized.

Description:
This application is based on Japanese Patent Application No. 9-28128 filed on Feb. 12, 1997, the entire contents of which are incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     a) Field of the Invention 
     The present invention relates to semiconductor logical circuits, flip-flop circuits and storage circuits particularly of a multivalued logic type. 
     b) Description of the Related Art 
     Most of conventional semiconductor logical circuits, flip-flop circuits and storage circuits adopt a binary logic. For example, one memory cell of a static RAM of a binary logic type is constituted of six MOS transistors. A storage density of a memory can be increased by reducing an area of a semiconductor substrate occupied by one memory cell. 
     There is a limit, however, in reducing a memory cell area. It is effective for increasing a storage capacity without reducing a memory cell area to adopt a multivalued logic type. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide semiconductor logical circuits, flip-flop circuits and storage circuits of a multivalued logic type. 
     It is another object of the present invention to provide a storage circuit device capable of increasing a storage capacity without reducing one memory cell area. 
     According to one aspect of the present invention, there is provided a logical circuit device comprising a MOS transistor having a source region, a drain region, a channel region defined between the source region and the drain region, and a gate electrode formed above the channel region, respectively formed on a semiconductor substrate, wherein the amplitude of a voltage applied to the gate electrode necessary for making the channel region conductive is not level throughout the channel region in the width direction. 
     As the voltage applied to the gate electrode is gradually increased, current first flows through a partial region conductive at that voltage of the channel region. As the voltage applied to the gate electrode is further increased, the width of the partial region where current flows is broadened. Since current flows also through the new conductive portion, the increase factor of current becomes large. The input/output characteristics of the MOS transistor take therefore a gently sloped step shape or wave form. A logical circuit of a multilevel logic type can be formed by using a gentle slope portion of the input/output characteristics for each state of multivalued logic levels. 
     According to another aspect of the present invention, there is provided a flip-flop circuit device comprising: first and second inverter circuits each formed by a three-terminal semiconductor circuit device having one control terminal and two current terminals, current flowing through the two current terminals being controlled by an electric signal applied to the control terminal, and two graphs intersecting at least 5 points or more when the two graphs are superposed, one graph representing the input/output characteristics of the first inverter circuit and the other graph representing an inverse function of the input/output characteristics of the second inverter circuit; and first and second interconnections for inputting output signals from the first and second inverter circuits to the second and first inverter circuits respectively. 
     According to another aspect of the present invention, there is provided a storage circuit device comprising: first and second inverter circuits each formed by a three-terminal semiconductor circuit device having one control terminal and two current terminals, current flowing through the two current terminals being controlled by an electric signal applied to the control terminal, and two graphs intersecting at least 5 points or more when the two graphs are superposed, one graph representing the input/output characteristics of the first inverter circuit and the other graph representing an inverse function of the input/output characteristics of the second inverter circuit; first and second interconnections for inputting output signals from the first and second inverter circuits to the second and first inverter circuits respectively; a bit line to be applied with an electric signal corresponding to information to be stored; a switching element connected between the second interconnection and the bit line, a conductive state and a non-conductive state of the switching element being selected by an externally applied select signal; and a word line for supplying the select signal to the switching element. 
     If there are five cross points between the graph representing the input/output characteristics of the first inverter circuit and the graph representing the inverse function of the input/output characteristics of the second inverter circuit, three cross points among the five cross points can be used as stable states. A storage circuit of a three-valued logic type can be obtained by using each stable state for each of multivalued levels. 
     As described above, a semiconductor logical circuit of a multivalued logic type can be realized by forming two or more regions having different threshold values in the channel region of a MOS transistor. A storage circuit of a multivalued logic type can be realized by a combination of inverter circuits of a multivalued logic type. The storage density can be increased by using a storage circuit of a multivalued logic type. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1A is an equivalent circuit diagram of an inverter according to an embodiment of the invention, 
     FIG. 1B is a graph showing the input/output characteristics of a driver transistor of the inverter shown in FIG. 1A, and 
     FIG. 1C is a graph showing the input/output characteristics of the inverter shown in FIG.  1 A. 
     FIG. 2A is a plan view showing an example of the layout of the inverter shown in FIG. 1A, and 
     FIG. 2B is a cross sectional view taken along one-dot chain line B 2 —B 2  shown in FIG.  2 A. 
     FIG. 2C is a cross sectional view showing another example of the MOS transistor shown in FIG.  2 A. 
     FIG. 3A is a plan view showing another example of the layout of the inverter shown in FIG. 1A, and 
     FIG. 3B is a cross sectional view taken along one-dot chain line B 3 —B 3  shown in FIG.  3 A. 
     FIGS. 4A to  4 C and  5 A to  5 C are equivalent circuit diagrams of inverters according to other embodiments of the invention. 
     FIG. 6A is an equivalent circuit diagram of a memory cell according to an embodiment of the invention, and 
     FIG. 6B is a graph showing the characteristics of normal and inverse input/output functions of an inverter of the memory cell shown in FIG.  6 A. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1A shows an inverter circuit according to an embodiment of the invention. The inverter circuit of this embodiment is constituted of a serial circuit of n-channel MOS transistors Tr 1  and Tr 2 . Of this serial circuit, the MOS transistor Tr 1  is connected at one of its two current terminals to a power line V DD , and the MOS transistor Tr 2  is grounded at one of its two current terminals. The gate electrode of the MOS transistor Tr 1  is connected to the power line V DD . The MOS transistor Tr 1  operates as a load of the MOS transistor Tr 2 . A voltage V in  is applied to the gate electrode of the driver MOS transistor Tr 2 . A voltage V out  is output from an interconnection between the MOS transistors Tr 1  and Tr 2 . 
     FIG. 1B is a graph showing drain current of the MOS transistor Tr 1  as a function of gate voltage. As the gate voltage exceeds the threshold voltage V th , the drain current starts flowing, and as the gate voltage continues to rise, the drain current increases. A MOS transistor of a binary logic has no inflection point except extremely near at the threshold voltage V th , and as the gate voltage exceeds this single inflection point, the increase factor of the drain current gradually reduces. 
     In contrast, a MOS transistor of this embodiment shown in FIG. 1B has at least two inflection points r 1  and r 2  in addition to the inflection point extremely near at the threshold voltage V th . At least two bump portions therefore appear on the curve of the input/output characteristics shown in the graph of FIG.  2 A. In the drawings of this application, the circuit symbol for such a MOS transistor having the input/output characteristics with at least two bumps is indicated by two arrows added between the drain and source terminals. 
     FIG. 1C shows an example of the input/output characteristics of the inverter circuit shown in FIG.  1 A. The abscissa represents an input voltage V out , and the ordinate represents an output voltage V out , both in optional scale. Since the MOS transistor Tr 2  has two bump portions on the curve of its input/output characteristics, the input/output characteristics of the inverter circuit have corresponding two bumps forming a stepped curve. Therefore, the curve has three regions A 1 , A 2  and A 3  of gentle slope. This inverter circuit is a three-valued logic inverter circuit, with the regions A 1 , A 2  and A 3  corresponding values 0, 1, and 2. 
     Next, with reference to FIGS. 2A and 2B, an example of the structure of the driver MOS transistor Tr 2  shown in FIG. 1A will be described. 
     FIG. 2A is a plan view showing an example of the layout of the driver MOS transistor. On both sides of a gate electrode G 1 , a source region S 1  and a drain region D 1  are disposed. The source and drain regions S 1  and D 1  and a channel region therebetween are surrounded by a field oxide film. 
     FIG. 2B is a cross sectional view taken along one-dot chain line B 2 —B 2  shown in FIG. 2A. A field oxide film  2  is formed on the surface of a silicon substrate  1  and defines an active region. A gate oxide film  4  is formed above the channel region of the silicon substrate  1 , and a gate electrode  5  made of polysilicon is formed on the gate oxide film  4 . 
     An impurity doped region  3  for controlling the threshold voltage is formed in the surface layer of the channel region. This impurity doped region  3  is constituted of a region  3   a  at the central area of the channel region in the channel width direction (in the lateral direction in FIG. 2B) where the impurity concentration is high and regions  3   b  on both sides of the region  3   a  where the impurity concentration is low. This configuration can be obtained by performing heat treatment after impurities are implanted in the surface layer of the channel region. If the implanted impurities are boron (B) or the like, impurity atoms are absorbed in the field oxide film  2  during heat treatment so that the impurity concentration of the regions  3   b  near both ends of the impurity implanted region  3  lowers. 
     The threshold value at the high impurity concentration region  3   a  is different from that of the low impurity concentration regions  3   b . This MOS transistor is therefore expected to have the characteristics similar to the circuit connecting two MOS transistors having different threshold values in parallel. As the gate voltage rises to the threshold voltage V th  of one MOS transistor having a lower threshold value, current starts flowing through the channel region having the lower threshold value. As the gate voltage further rises and exceeds the threshold value of the other MOS transistor having a higher threshold value, current starts flowing also through the channel regions having the higher threshold value. As a result, the graph of the input/output characteristics has two bumps. 
     The MOS transistor shown in FIG. 2B has a channel region, the impurity concentration of which is higher near at the central portion in the width direction and lower on both sides of the central portion. If arsenic or phosphorus are used as an impurity, the impurity in the field oxide film moves into the silicon substrate during heat treatment. Therefore, the impurity concentration near at the central portion  3   a  is lower than that of both sides  3   b  of the central region  3   a . In this case, the graph of the input/output characteristics also has two bumps. 
     The impurity concentration of the channel region may be different from that shown in FIG.  2 B. If the impurity concentration of the channel region is not level throughout the channel region in the width direction, the graph of the input/output characteristics is expected to have bumps. 
     As shown in FIG. 2C, for example, one side portion  3 C of the channel region  3  may be higher concentration region and the other side portion  3   d  may be lower concentration region. The concentration distribution shown in FIG. 2C can be obtained by implanting impurities along an oblique direction using ion implantation. It is preferable that the concentration changes stepwise in order to obtain the graph of the input/output characteristics with obvious bumps. 
     Next, with reference to FIGS. 3A and 3B, another structure of the MOS transistor Tr 2  shown in FIG. 1A will be described. 
     FIG. 3A is a plan view showing the layout of the driver MOS transistor of this example. On both sides of a gate electrode G 2 , a source region S 2  and a drain region D 2  are disposed. A channel region between the source and drain regions S 2  and D 2  is constituted of a region CH 1  at generally the central area of the channel region in the channel width direction where the gate oxide film is thin and regions CH 2  on both sides of the region CH 1  where the gate oxide film is thick. The gate oxide film above the regions CH 2  is formed, for example, at the same time when selective oxidation is performed for forming the field oxide film. 
     FIG. 3B is a cross sectional view taken along one-dot chain line B 3 —B 3  shown in FIG. 3A. A field oxide film  12  is formed on the surface of a silicon substrate  11  and defines an active region. A portion of the field oxide film  12  near the boundary to the active region functions as thick gate oxide films  14   b . A thin gate oxide film  14   a  is formed at the area between the thick gate oxide films  14   b . On the thin and thick gate oxide films  14   a  and  14   b , a gate electrode  15  made of polysilicon is formed. 
     The threshold voltage of a MOS transistor changes with the thickness of the gate oxide film. The threshold value at the thin gate oxide film  14   a  is different from that at the thick gate oxide films  14   b . Therefore, the MOS transistor having the structure shown in FIGS. 3A and 3B also has the input/output characteristics with two bumps such as shown in FIG. 1B, similar to the MOS transistor shown in FIGS. 2A and 2B. In order to form clear and separate two bumps, it is preferable to set the total width of the thick gate oxide films  14   b  to about one fourth to five times of the width of the thin gate oxide film. 
     FIGS. 4A to  4 C show modifications of the inverter circuit shown in FIG.  1 A. The inverter circuit of FIG. 4A uses a p-channel MOS transistor Tr 3  in place of the MOS transistor Tr 1  shown in FIG.  1 A. The inverter circuit of FIG. 4B has two MOS transistors whose conductivity types are opposite to those shown in FIG.  1 A. The inverter circuit of FIG. 4C has two MOS transistors whose conductivity types are opposite to those shown in FIG.  4 A. Similar to the inverter circuit shown in FIG. 1A, the inverter circuits shown in FIGS. 4A to  4 C are expected to have the input/output characteristics with steps of gentle slope similar to the characteristics shown in FIG.  1 C. 
     FIGS. 5A to  5 C show other modifications of the inverter circuit shown in FIG.  1 A. In FIGS. 5A and 5B, n- and p-channel MOS transistors of a CMOS inverter use the load transistor and the transistor having the input/output characteristics shown in FIG.  1 B. Also in this case, similar to the inverter circuit shown in FIG. 1A, the CMOS inverter is expected to have the input/output characteristics with steps of gentle slope similar to the characteristics shown in FIG.  1 C. 
     The CMOS inverter shown in FIG. 5C uses the transistor having the input/output characteristics shown in FIG. 1B as its two MOS transistors. It is expected in this case that the input/output characteristics of the two MOS transistors are influenced each other to obtain the input/output characteristics with two or more steps of gentle slope. 
     Next, with reference to FIGS. 6A and 6B, the structure and operational basics of an SRAM memory cell using the embodiment inverter circuit will be described. 
     The inverter circuits INV 1  and INV 2  shown in FIG. 6A have the characteristics similar to those of the CMOS inverter circuit shown in FIG.  5 A. The inverter circuit INV 1  is formed of an n-channel driver transistor Tr 11  and a p-channel load transistor Tr 12 , whereas the inverter circuit INV 2  is formed of an n-channel driver transistor Tr 21  and a p-channel load transistor Tr 22 . 
     An output of the inverter circuit INV 1  is input via an interconnection LI 1  to the inverter circuit INV 2 , and an output of the inverter circuit INV 2  is input via an interconnection LI 2  to the inverter circuit INV 1 . An output terminal of the inverter circuit INV 1  is connected via a transfer transistor Tr 31  to a bit line BL, and an output terminal of the inverter circuit INV 2  is connected via a transfer transistor Tr 32  to an inverted bit line (−BL). The gate electrodes of the transfer transistors Tr 31  and Tr 32  are connected to a word line WL. 
     The memory cell shown in FIG. 6A was actually formed and the characteristics thereof were measured. The gate width of the driver transistors Tr 11  and Tr 21  was 0.6 μm, the gate width of the load transistors Tr 12  and Tr 22  was 0.2 μm, and the gate width of the transfer transistors Tr 31  and Tr 32  was 0.5 μm. 
     The process conditions of the driver transistors Tr 11  and Tr 21  will be described briefly in the following. B +  ions for forming a p-type well were implanted at an acceleration energy of 200 keV and a dose of 2×10 13  cm −2 , and B +  ions for cutting a channel were implanted at an acceleration energy of 80 keV and a dose of 2×10 12  cm −2 . After ions for channel cut were implanted, annealing was executed for 30 minutes at 950° C. 
     B +  ions for controlling a threshold value were implanted at an acceleration energy of 40 keV and a dose of 2×10 12  cm −2 . The oxidation temperature for forming the gate oxide film was 800° C., and the thickness of the gate oxide film was 4 nm. As +  ions for forming a lightly doped drain structure were implanted at an acceleration energy of 10 keV and a dose of 4×10 13  cm −2 , and As +  ions for forming source/drain regions were implanted at an acceleration energy of 40 keV and a dose of 6×10 15  cm −2 . Annealing for activation after ion implantation was executed for 10 seconds at 1000° C. 
     Next, the process conditions of the load transistors Tr 12  and Tr 22  will be described briefly in the following. P +  ions for forming an n-type well were implanted at an acceleration energy of 400 keV and a dose of 2×10 13  cm −2 , and P +  ions for cutting a channel were implanted at an acceleration energy of 200 keV and a dose of 4×10 12  cm −2 . After ions for channel cut were implanted, annealing was executed for 30 minutes at 950° C. 
     As +  ions for controlling a threshold value were implanted at an acceleration energy of 180 keV and a dose of 8×10 12  cm −2 . The oxidation temperature for forming the gate oxide film was 800° C., and the thickness of the gate oxide film was 4 nm. BF 2   +  ions for forming a lightly doped drain structure were implanted at an acceleration energy of 10 keV and a dose of 1×10 15  cm −2 , and BF 2   +  ions for forming source/drain regions were implanted at an acceleration energy of 20 keV and a dose of 2×10 15  cm −2 . Annealing for activation after ion implantation was executed for 10 seconds at 1000° C. 
     FIG. 6B shows the measurement results of the input/output characteristics of the memory cell shown in FIG. 6A manufactured under the above-described process conditions. A curve a shows the input/output characteristics of the inverter circuit INV 1 , and a curve b shows the inverse function of the input/output characteristics of the inverter circuit INV 2 . The abscissa and ordinate represent voltage in the unit of V. The supply voltage was 2 V. 
     Although the curve a does not clearly show two bumps, the negative slope thereof becomes gentle in the region of the input voltage in excess of about 0.6 V, which provides the characteristics similar to the graph of FIG.  1 C. The curve b shows the characteristics of the curve a with its abscissa and ordinate being interchanged. The curves a and b cross at five points. Of these five cross points, the points at opposite ends and a center are stable points. Namely, this memory cell has three stable states at the outputs of the inverter circuit INV 2  of about 0.45 V, 0.95 V and 1.95 V. This memory cell can therefore store three-valued logic information. 
     As above, even if the input/output characteristics of a MOS transistor and an inverter circuit constituting a memory cell do not show clear two bumps, the memory cell operates as a multi-valued logic type if the graph of the input/output characteristics of one inverter circuit and the graph of an inverse function of those of the other inverter circuit intersect at five or more points. 
     The memory cell circuit shown in FIG. 6A is the same as a usual SRAM memory cell circuit, and so the area of the substrate surface occupied by the memory cell is the same. As compared to a binary logic memory cell, this memory cell of a multi-valued logic type can provide a higher storage density. 
     Although five cross points of the curves a and b are shown in FIG. 6B, the number of cross points may be seven or more. By setting the input/output characteristics of inverter circuits so as to form five or more cross points, information of a multi-valued logic of three or more values can be stored in one memory cell. 
     Furthermore, although the memory cell shown in FIG. 5A uses inverter circuits shown in FIG. 5A, it may use other inverter circuits such as shown in FIG. 1A, FIGS. 4A to  4 C, and FIGS. 5B and 5C. 
     The present invention has been described in connection with the preferred embodiments. The invention is not limited only to the above embodiments. It is apparent that various modifications, improvements, combinations, and the like can be made by those skilled in the art.