Abstract:
To provide a semiconductor memory device capable of writing a checkerboard pattern for interference and investigation by three writings regardless of the magnitude of memory capacity by making a change of a simple circuit configuration free from the need of a data holding circuit and a voltage converting circuit large in circuit area in a memory array in which the order of arrangement of bits is reversedly arranged between data words adjacent in a row direction. A row decoder and a column decoder are respectively configured to enable operation switching to an all selection mode and an even/odd-based selection mode in addition to a single address selection mode of a memory array by a control signal from a control circuit.

Description:
RELATED APPLICATIONS 
       [0001]    This application claims priority under 35 U.S.C. §119 to Japanese Patent Application No. 2015-015374 filed on Jan. 29, 2015, the entire content of which is hereby incorporated by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a semiconductor memory device, and more specifically to a matrix selection mechanism of a memory array. 
         [0004]    2. Background Art 
         [0005]      FIG. 4  is a circuit diagram illustrating a memory array of a related art EEPROM. One address is comprised of a memory word composed of a plurality of bits. A memory cell is comprised of a floating gate  401  for holding data and a control gate  402  for selecting a bit, and holds information of one bit therein. Since the reading of data from a memory normally starts from the MSB, i.e., the most significant bit side of data, MSB data is stored in a memory cell close to a word selector from the MSB side needed to be read earliest. The LSB of a data word, i.e., the least significant bit of data is stored in the farthest memory cell. In the process of manufacturing a memory array using an EEPROM, a checkerboard pattern in which data bits to be stored of memory cells adjacent to each other are brought into an inverted state, is required to be written in order to examine that data interference does not occur between adjacent memory cells. 
         [0006]    As a method of writing a checkerboard pattern, there are a method of executing writing for each word, and a method of providing an even/odd-based selection function in each of row decoders of a memory array as proposed in a related art and writing bit-inverted data therein respectively. 
         [0007]    [Patent Document 1] 
         [0008]    Japanese Patent Publication No. Hei 4 (1992)-66080 
         [0009]    [Patent Document 2] 
         [0010]    Japanese Patent Application Laid-Open No. 2001-236795 
       SUMMARY OF THE INVENTION 
       [0011]    In the method of executing writing for each word, however, a test time also increases in proportion to memory capacity. 
         [0012]    Further, in a recent memory array, as illustrated in  FIG. 2 , memory words adjacent in a row direction are arranged to be inverted with a column direction as an axis, and memory words adjacent in the column direction are arranged to be inverted with the row direction as an axis. The advantage of the present arrangements resides in that since a source line connected to each memory word can be shared between adjacent memory words, the area necessary to wire each source line in the memory array can be reduced to one half. The advantage is a technique indispensable even for reducing a chip area. 
         [0013]    Since the memory words adjacent in the row direction are arranged in such a manner that the LSBs or MSBs are closest to each other in the memory array having adopted the present arrangements, it is not possible to write a checkerboard pattern only by the even/odd-based selection of each row decoder such as in the related art. 
         [0014]    As a means for solving the above, there is generally provided a configuration that as illustrated in  FIG. 3 , a data supply means is provided which performs the holding of data and the conversion of a writing voltage respectively for each memory cell corresponding to all words which configure one row in a memory array. 
         [0015]    This has the disadvantage that since a data holding circuit and a voltage converting circuit are additionally increased, and the amount of buses connecting these is also increased, a chip area increases and control also becomes complicated. 
         [0016]    The present invention has been made with the foregoing in view, and provides a semiconductor memory device capable of writing a checkerboard pattern without increasing a data supply means even in a memory array in which adjacent memories are reversedly disposed in word units for sharing of source lines, and additionally without allowing the time taken for writing to be proportional to memory capacity. 
         [0017]    In order to solve the above problems, a semiconductor memory device of the present invention is configured by the following elements. 
         [0018]    The semiconductor memory device is configured of a memory array which has a plurality of memory words each comprised of a plurality of memory cell groups and one word selector, and in which the memory words adjacent in a row direction are respectively reversibly disposed with a column direction as an axis, the memory words adjacent in the column direction are respectively reversibly disposed with the row direction as an axis, and the memory words are arranged in a matrix form; an address counter which holds an address for selecting a specific word in the memory array; a row decoder connected to the address counter and capable of performing functional switching to one-row selection, even row batch selection, odd row batch selection, and all row batch selection modes; a column decoder connected to the address counter and capable of performing functional switching to one-column selection, even column batch selection, odd column batch selection, and all column batch selection modes; and a control circuit which controls the functional switching of the column decoder and the row decoder. 
         [0019]    According to the semiconductor memory device of the present invention, since there is no need to provide a data holding circuit and a voltage converting circuit which greatly affect a chip area, it is possible to write a checkerboard pattern for interference and investigation by three writings regardless of the magnitude of memory capacity in a simple circuit configuration. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0020]      FIG. 1  is a block diagram illustrating a semiconductor memory device of the present invention; 
           [0021]      FIG. 2  is a circuit diagram illustrating an arrangement of a recent memory array to be an adaptive object of the present invention; 
           [0022]      FIG. 3  is a block diagram illustrating a related art semiconductor memory device; and 
           [0023]      FIG. 4  is a circuit diagram illustrating an arrangement of a related art memory array. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0024]    A preferred embodiment of the present invention will hereinafter be described with reference to the accompanying drawings. 
         [0025]      FIG. 1  is a block diagram illustrating a semiconductor memory device according to the present invention. 
         [0026]    A configuration of the semiconductor memory device will first be described. The semiconductor memory device is equipped with a memory array  100 , a data supply means  110 , a row decoder  130 , a column decoder  140 , an address counter  150 , a control circuit  160 , a bit line bus  111 , an even-numbered row selection signal bus  131 , an odd-numbered row selection signal bus  132 , an even-numbered column selection signal bus  141 , an odd-numbered column selection signal bus  142 , an address bus  151 , a column/row even-odd selection signal line  161 , and a memory array all selection signal line  162 . 
         [0027]    The memory array  100  is configured by arranging memory words each comprised of a word selector  102  and a memory word group  101  in a matrix form. The data supply means  110  holds a data word to be written equivalent to one word and converts data to be written into a writing voltage. The address counter  150  holds address data therein. The control circuit  160  controls both row and column decoders. 
         [0028]    The bit line bus  111  is comprised of a bit line equivalent to one word and connects the memory array  100  and the data supply means  110 . The even-numbered row selection signal bus  131  is a collection of signal lines for selecting even rows, of signal buses for connecting the memory array  100  and the row decoder  130  and selecting rows in the memory array  100 . The odd-numbered row selection signal bus  132  is a collection of signal lines for selecting odd rows, of signal buses for connecting the memory array  100  and the row decoder  130  and selecting rows in the memory array  100 . The even-numbered column selection signal bus  141  is a collection of signal lines for selecting even columns, of signal buses for connecting the memory array  100  and the column decoder  140  and selecting columns in the memory array  100 . The odd-numbered column selection signal bus  142  is a collection of signal lines for selecting odd columns, of signal buses for connecting the memory array  100  and the column decoder  140  and selecting columns in the memory array  100 . The address bus  151  connects the address counter  150 , the row decoder  130 , and the column decoder  140 . The column/row even-odd selection signal line  161  connects the control circuit  160 , the row decoder  130 , and the column decoder  140 . The memory array all selection signal line  162  connects the control circuit  160 , the row decoder  130 , and the column decoder  140 . 
         [0029]    In the arrangement of the respective memory words in the memory array  100 , the memory words adjacent to each other in a row direction are respectively inverted with a column direction as an axis, and the memory words adjacent to each other in the column direction are respectively inverted with the row direction as an axis. The wire sharing of source lines is performed as illustrated in  FIG. 2 . In the present embodiment, bit lines connected to all data words in the memory array  100  are common for every corresponding bit. If the MSB of the data word is taken for example, a common MSB bit line is connected to the MSBs of all the data words. 
         [0030]    The operation of the semiconductor memory device will next be described. Normal data writing will be described by taking, for example, a case where data writing is performed on an arbitrary (N row, M column) memory word. 
         [0031]    The control circuit  160  negates the memory array all selection signal line  162  and the column/row even-odd selection signal line  161  to switch the row decoder  130  and the column decoder  140  to a single address selection mode. In the single address selection mode, the row decoder  130  and the column decoder  140  respectively assert a single row selection signal line and a column selection signal line indicated by address data transmitted from the address bus  151 . Next, data for designating (N row, M column) in the memory array  100  is stored in the address counter  150 . The address data stored therein is supplied to the row decoder  130  and the column decoder  140  through the address bus  151 . The row decoder  130  asserts a row selection signal line indicative of the N row out of the even-numbered row selection signal bus  131  and the odd-numbered row selection signal bus  132  to bring all word selectors  102  and all memory cells arranged in the Nth row into a selected state. The column decoder  140  asserts a column selection signal line indicative of the M column out of the even-numbered column selection signal bus  141  and the odd-numbered column selection signal bus  142  and thereby supplies a writing voltage to all word selectors  102  arranged in the Mth column. Each word selector  102  in the memory array  100  supplies a writing voltage from a column address selection signal to the memory cell through an in-address bit selection signal line when it is only in the selected state. As a result, the memory word in which both row address and column address selection signals are brought into an asserted state exits by one word within the memory array  100 . The data converted to the writing voltage is supplied via the bit line bus  111  from the data supply means  110  to the memory cell equivalent to one word supplied with the writing voltage, so that the data writing is performed. 
         [0032]    A description will next be made of a case where a checkerboard pattern is written into the memory array  100 . 
         [0033]    The memory array all selection signal line  162  is asserted by the control circuit  160  to switch the row decoder  130  and the column decoder  140  to an all selection mode. In the all selection mode, all row address selection signals and all column address selection signals are asserted regardless of address data. The data supply means  110  stores therein patterns in which data of adjacent memory cells are inverted within the memory word, e.g., data (10101010) or data (01010101) where one word is comprised of 8 bits. When memory writing is carried out in this state, the same data as data stored in data latches are written into all memory words in the memory array  100 . 
         [0034]    Next, the memory array all selection signal line  162  is negated and the column/row even-odd selection signal line  161  is asserted to switch the row decoder  130  and the column decoder  140  to an even-odd selection mode. In the even-odd selection mode, the row decoder  130  asserts either the even-numbered row selection signal bus  131  or the odd-numbered row selection signal bus  132  on the basis of the address data from the address bus  151 . The column decoder  140  asserts either the even-numbered column selection signal bus  141  or the odd-numbered column selection signal bus  142  on the basis of the address data from the address bus  151 . 
         [0035]    Next, the address counter  150  stores therein data for designating (N row, M column) in the memory array  100 . The stored address data is supplied to the row decoder  130  and the column decoder  140  through the address bus  151 . The row decoder  130  asserts a row selection signal for selecting the N row, and all row selection signals of numbers equal in even/odd form on the basis of the address data. The column decoder  140  asserts a column selection signal for selecting the M column, and all column selection signals of numbers equal in even/odd form on the basis of the address data. As a result, the memory words equivalent to a quarter in the memory array  100 , which include the memory words of (N row, M column), are put in a selected state. 
         [0036]    Inverted patterns are stored in the data supply means  110  in terms of the time of all writing. For example, when data (10101010) is stored upon all writing where one word is constituted of 8 bits, data (01010101) is stored in the data supply means  110 . When memory writing is done in this state, patterns in which data of adjacent bits are inverted are written into the quarter in the memory array  100 , which includes the memory words of (N row, M column). 
         [0037]    Next, data for designating (N+1 row, M+1 column) in the memory array  100  is stored in the address counter  150 . The stored address data is supplied to the row decoder  130  and the column decoder  140  through the address bus  151 . When the row decoder  130  and the column decoder  140  execute data writing, the same data as (N row, M column) is written into the quarter in the memory array  100 , which includes memory words of (N+1 row, M+1 column). As a result, the checkerboard pattern is written into the memory array  100 . That is, if a writing time and a data transmission time are allowed three times, the checkerboard pattern can be written regardless of memory capacity. 
         [0038]    In the semiconductor memory device of the present embodiment, as described above, the writing of the checkerboard pattern has been realized by carrying out the one-quarter writing twice after one all writing. However, row addresses and column addresses respectively different in the first quarter writing and the second quarter writing may be designated, and the order of addresses designated upon the quarter writing does not matter. For example, when the address designated upon the first quarter writing is assumed to be (N row, M+1 column), (N+1 row, M column) is designated upon the second quarter writing. Further, in order to uniform the writing frequency to all memory cells, the same data is written into (N row, M column) and (N+1 row, M column) by the quarter writing, and data bit-inverted from the previously written data is written into (N row, M+1 column) and (N+1 row, M+1 column) by the quarter writing, thereby making it possible to realize the writing of the checkerboard pattern by the four writings in total. This method has an advantage that although the writing time is increased once, the number of writings can be made uniform within the memory array  100 . Further, the number of bits which configure the memory words can be configured in arbitrary numbers regardless of even and odd numbers.