Abstract:
An array of non-volatile memory cells in a semiconductor substrate of a first conductivity type. Each memory cell comprises first and second regions of a second conductivity type on a surface of the substrate, with a channel region therebetween. A word line overlies one portion of the channel region, is adjacent to the first region, and has little or no overlap with the first region. A floating gate overlies another portion of the channel region, and is adjacent to the first portion and the second region. A coupling gate overlies the floating gate. An erase gate overlies the second region. A bit line is connected to the first region. A negative charge pump circuit generates a negative voltage. A control circuit generates a plurality of control signals in response to receiving a command signal, and applies the negative voltage to the word line of unselected memory cells.

Description:
TECHNICAL FIELD 
       [0001]    The present invention relates to a non-volatile memory cell device and a method of operating same. More particularly, the present invention relates to such memory device in which a negative voltage is applied to the word line and selectively in combination with other terminals of the unselected memory cells during the operations of read, program or erase. 
       BACKGROUND OF THE INVENTION 
       [0002]    Non-volatile memory cells are well known in the art. One prior art non-volatile memory cell  10  is shown in  FIG. 1 . The memory cell  10  comprises a semiconductor substrate  12  of a first conductivity type, such as P type. The substrate  12  has a surface on which there is formed a first region  14  (also known as the source line SL) of a second conductivity type, such as N type. A second region  16  (also known as the drain line) also of N type is formed on the surface of the substrate  12 . Between the first region  14  and the second region  16  is a channel region  18 . A bit line BL  20  is connected to the second region  16 . A word line WL  22  is positioned above a first portion of the channel region  18  and is insulated therefrom. The word line  22  has little or no over lap with the second region  16 . A floating gate FG  24  is over another portion of the channel region  18 . The floating gate  24  is insulated therefrom, and is adjacent to the word line  22 . The floating gate  24  is also adjacent to the first region  14 . A coupling gate CG (also known as control gate)  26  is over the floating gate  24  and is insulated therefrom. An erase gate EG  28  is over the first region  14  and is adjacent to the floating gate  24  and the coupling gate  26  and is insulated therefrom. The erase gate  28  is also insulated from the first region  14 . The cell  10  is more particularly described in U.S. Pat. No. 7,868,375 whose disclosure is incorporated herein by reference in its entirety. 
         [0003]    Although U.S. Pat. No. 7,868,375 discloses the application of a negative voltage to the coupling gate  26  of the memory cell  10  during the erase operation, the reference does not disclose the benefit of applying a negative voltage to other gates during other operations such as read and program. 
         [0004]    Accordingly, one object of the present invention is the disclosure of a non-volatile memory cell device that applies a negative voltage to other gates or terminals during other operations. 
       SUMMARY OF THE INVENTION 
       [0005]    The present invention relates to a non-volatile memory device that has a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is in the semiconductor substrate arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. An erase gate overlies the second region and is insulated therefrom. A bit line is connected to the first region. A negative charge pump circuit generates a first negative voltage. A control circuit receives a command signal and generates a plurality of control signals, in response thereto and applies the first negative voltage to the word line of the unselected memory cells. 
         [0006]    The present invention also relates to a method of operating a non-volatile memory cell device of the foregoing type. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]      FIG. 1  is a cross-sectional view of a non-volatile memory cell of the prior art to which the method of the present invention can be applied. 
           [0008]      FIG. 2  is a block diagram of a non-volatile memory device of the present invention using the non-volatile memory cell of the prior art shown in  FIG. 1 . 
           [0009]      FIGS. 3A and 3B  are waveform diagrams of program/erase and read operations, respectively, for use in the memory device of the present invention. 
           [0010]      FIGS. 4A and 4B  are detailed circuit diagrams of a negative/positive word line decoder circuit and negative charge pump, respectively, for use in the memory device of the present invention. 
           [0011]      FIG. 5  is a detailed circuit diagram of a first negative/positive high voltage decoder circuit for use in the memory device of the present invention. 
           [0012]      FIG. 6  is a detailed circuit diagram of a second negative/positive high voltage decoder circuit for use in the memory device of the present invention. 
           [0013]      FIG. 7  is a detailed circuit diagram of a third negative/positive high voltage decoder circuit for use in the memory device of the present invention. 
           [0014]      FIG. 8  is a detailed circuit diagram of a negative voltage charge pump generator for use with the memory device of the present invention. 
           [0015]      FIG. 9  is a detailed circuit diagram of a negative high voltage regulation circuit for use in the memory device of the present invention. 
           [0016]      FIG. 10  is a detailed circuit diagram of a negative/positive pad circuit for use in the memory device of the present invention. 
           [0017]      FIGS. 11A and 11B  are cross sectional views showing a portion of a process flow of the prior art for use in making the memory device of the prior art. 
           [0018]      FIG. 11C  is a cross sectional view showing a portion of a process flow for making the memory device of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0019]    Referring to  FIG. 2  there is shown a block level diagram of a non-volatile memory device  50  of the present invention. In the embodiment shown in  FIG. 2 , the memory device  50  comprises two arrays  52 A and  52 B of non-volatile memory cells  10  of the type shown in  FIG. 1 , arranged in a plurality of rows and columns in a semiconductor substrate  12 . Adjacent to each array  52  of non-volatile memory cells  10  is a decoder (Xdecoder  54 A and  54 B, respectively), for receiving address signals to be decoded and supplied to the word lines  22  of selected and unselected memory cells  10 . Each of decoders  54  also has an associate negative charge pump included in a charge pump  56  to generate a negative voltage. A decoder (WSHDRHALFV, NCG)  80  placed in between the array  52 A and  52 B provides voltage levels for the control gate  26 , the sourceline  14 , and the erase gate  28  as shown in embodiments in  FIG. 5-7 . 
         [0020]    Each of the memory arrays  52  of the memory device  50  also has a plurality of sensors  58  associated therewith to receive the signals from the memory cells  10  from the array  52  and to generate output signals from the device  50 . The memory device  50  also has a logic circuit  60 . The logic circuit  60  receives commands such as program, erase or read issue by a host controller (not shown), external to the memory device  50  to cause the memory device  50  to execute the various commands. In response to the commands received, the logic circuit  50  generates control signals that control the operation and the timing of the charge pump circuits  56  and the decoding circuits  54 , and sense amplifier circuits  58 . The analog circuit  70  provides analog bias voltages and currents and timing for the device  50 . A high voltage (positive, negative) control circuit  90  provides regulated and time-sequenced positive and negative levels. A pad circuit  88  provides input buffers, IO buffers, Power pads (Vdd,Vss), Test pads, and ESD protection. 
         [0021]    In response to the read, erase or program command, the logic circuit  60  causes the various voltages to be supplied in a timely and least disturb manner to the various portions of both the selected memory cell  10  and the unselected memory cells  10 . 
         [0022]    For the selected and unselected memory cell  10 , the voltage and current applied are as follows. As used hereinafter, the following abbreviations are used: source line or first region  14  (SL), bit line  20  (BL), word line  22  (WL), coupling gate  26  (CG), erase gate  28  (EG). 
         [0000]    
       
         
               
             
               
               
               
               
               
               
             
           
               
                   
               
               
                 Read Command 
               
             
          
           
               
                 Memory Cell 
                 WL 
                 BL 
                 CG 
                 EG 
                 SL 
               
               
                   
               
               
                 Selected 
                   1.0-2.0 v 
                 0.6-2.0 v 
                 0.0-2.6 v 
                 0.0-2.6 v 
                 0.0 v 
               
               
                 Unselected 
                 −0.5-0.0 v 
                    0.0 v 
                 0.0-2.6 v 
                 0.0-2.6 v 
                 0.0 v 
               
               
                   
               
             
          
         
       
     
         [0000]    
       
         
               
             
               
               
               
               
               
               
             
           
               
                   
               
               
                 Erase Command 
               
             
          
           
               
                 Memory Cell 
                 WL 
                 BL 
                 CG 
                 EG 
                 SL 
               
               
                   
               
               
                 Selected 
                 −0.5-0.0 v 
                 0.0 v 
                    0.0 v 
                 11.5-12.0 v 
                 0.0 v 
               
               
                 Unselected 
                 −0.5-0.0 v 
                 0.0 v 
                 0.0-2.6 v 
                  0.0-2.6 v 
                 0.0 v 
               
               
                   
               
             
          
         
       
     
         [0023]    Alternatively, the erase command can be performed with the following voltages: 
         [0000]    
       
         
               
             
               
               
               
               
               
               
             
               
               
               
               
               
               
               
             
           
               
                   
               
               
                 Erase Command 
               
             
          
           
               
                 Memory Cell 
                 WL 
                 BL 
                 CG 
                 EG 
                 SL 
               
               
                   
               
             
          
           
               
                 Selected 
                 −0.5-0.0 v 
                 0.0 v 
                 −(5.0-9.0) 
                 v 
                 8.0-9.0 v 
                 0.0 v 
               
               
                 Unselected 
                 −0.5-0.0 v 
                 0.0 v 
                 0.0-2.6 
                 v 
                 0.0-2.6 v 
                 0.0 v 
               
               
                   
               
             
          
         
       
     
         [0024]    Alternatively, the erase operation can be performed with P substrate  12  being negative instead of 0v, e.g., Vsub=−6v, in this case, the voltage on the wordline WL  22  is =&lt;−4v (to prevent WL oxide breakdown). 
         [0000]    
       
         
               
             
               
               
               
               
               
               
             
           
               
                   
               
               
                 Program Command 
               
             
          
           
               
                 Memory 
                   
                   
                   
                   
                   
               
               
                 Cell 
                 WL 
                 BL 
                 CG 
                 EG 
                 SL 
               
               
                   
               
               
                 Selected 
                      1.0 v 
                 1 uA 
                 10.0-11.0 v 
                 4.5-5.0 v 
                 4.5-5.0 v 
               
               
                 Un- 
                 −0.5-0.0 v 
                 Vinh 
                  0.0-2.6 v 
                 0.0-2.6 v 
                 0.0-1.0 v 
               
               
                 selected 
                   
                 (1.6-3.0 v) 
               
               
                   
               
             
          
         
       
     
         [0025]    Alternatively, the program command can be performed with the following voltages and current: 
         [0000]    
       
         
               
             
               
               
               
               
               
               
             
           
               
                   
               
               
                 Program Command 
               
             
          
           
               
                 Memory Cell 
                 WL 
                 BL 
                 CG 
                 EG 
                 SL 
               
               
                   
               
               
                 Selected 
                      1.0 v 
                 1 uA 
                 8.0-9.0 v 
                 8.0-9.0 v 
                 4.5-5.0 v 
               
               
                 Unselected 
                 −0.5-0.0 v 
                 Vinh 
                 0.0-2.6 v 
                 0.0-2.6 v 
                 0.0-1.0 v 
               
               
                   
                   
                 (1.6-3.0 v) 
               
               
                   
               
             
          
         
       
     
         [0026]    Alternatively, the program operation can be performed with the P substrate Vsub  12  being negative instead of 0v, e.g., −1v to −5v, in this case, the voltage on the selected wordline WL  22  is such that (VWL−Vsub)˜=&lt;2v, i.e., Vwl˜=&lt;1v to −3v (to prevent WL oxide breakdown). 
         [0027]    Referring to  FIG. 3A  there is shown one example of a signal timing waveform for program and erase signals for positive/negative bias levels as described above for use in the memory device  50  of the present invention. Signals WL, BL, CG, EG, SL as corresponding respectively to terminals WL, BL, CG, EG, SL of the memory cell  10  are as described above. For programming, a signal WL  102  goes to high (e.g., ˜Vdd) first (such as to set control signal in the decoder circuit  80  to be described later) then start to settle down (to a bias voltage Vpwl). 
         [0028]    Then signal BL  104  and CG  106  goes high, e.g., ˜Vinh=˜Vdd and 10 to 11v respectively, and then EG and SL  110  goes high (e.g, ˜4.5v to 5v). Alternatively CG  106  goes high after EG  108  and SL  110  (as shown by the dotted line waveform). The signal WL  102  settles down to a voltage Vpwl, e.g, 1v, and the signal BL  104  settles down to a voltage Vdp, e.g., ˜0.5v as CG goes high. Unselected WLs goes down to negative, e.g., −0.5v, before or concurrent with selected WL  102  goes high. Unselected CGs, EGs, stays at value in standby, e.g, 0 to 2.6v. Unselected SLs stays at a value in standby, e.g., 0v or switches to a bias voltage, e.g., 1v, as CG  106  goes high (unselected SL switching to a bias level to prevent leakage current through unselected cells through the BLs). 
         [0029]    The signal BL  104  goes first high to Vinh (inhibit voltage) to prevent inadvertent program disturb due various signals are not settled yet during ramping to programming voltages. The timed sequence CG  106  vs. EG  108  and SL  110  are optimized to reduce disturb effect, e.g. whichever signal causes more disturb goes high last. The ramping down of programming pulses are reversed in order to minimize disturb (i.e., signal that goes up first now goes down last). The signals EG  108 , SL  110  goes down, then CG  106  goes down, then WL  102  and BL  104  goes down. In the embodiment of programming with the substrate P going negative, e.g., −1v, this negative switching is concurrent with the signal WL goes low or the CG or EG goes high. 
         [0030]    For erase, the signal WL  102  goes high, e.g, Vdd, (such as to set control signal in the decoder circuit  80  to be described later as embodiments in  FIG. 5-7 ) then goes low, e.g, 0v (or alternatively a negative such as −0.5v). At approximately same time as the WL  102  going low, the signal CG  106  goes negative, e.g, −6v to −9v, then the signal EG  108  goes high, e.g., 8 to 9v. The signals BL  104 , SL  110  stays at a value in standby, e.g., 0v. Alternatively the signal CG  106  goes negative after EG  108  goes high. Unselected WLs goes down to negative, e.g., −0.5v, before or concurrent with selected WL  102  going high. Unselected CGs, EGs, stay at value in standby, e.g, 0 to 2.6v. Unselected SLs stay at a value in standby, e.g., 0v. 
         [0031]    In the embodiment of erase with the substrate P going negative, e.g., −6v, this negative switching is concurrent with the signal WL goes low. This is to prevent stressing or breakdown of the WL gate oxide. 
         [0032]    The ramping down of erase pulses is approximately reversed in order (i.e., signal that goes up first now goes down last). The signals EG  108  goes to standby value, e.g., 0v, then CG  106  goes to standby value, e.g., 0v. 
         [0033]    Referring to  FIG. 3B  there is shown one example of a signal timing waveform for read signals for positive/negative bias levels as described above for use in the memory device  50  of the present invention. This read signal waveform goes with the program and erase signal waveform in  FIG. 3A  for complete non-volatile erase/program/read operation. For Read Normal waveform, the SL  110  is at standby value, e.g., 0v. The CG  106  is at standby value, e.g., 0v or 2.6v, or alternatively switching to a bias value in read, e.g. 2.6v (to help increase the memory cell current due to CG voltage coupling to FG potential in read condition). The EG  106  is at standby value, e.g., 0v or 2.6v, or alternatively switching to a bias value in read, e.g. 2.6v (to help increase the memory cell current due to EG voltage coupling to FG potential in read condition). The standby values are similar to those for program and erase condition. The WL  102  and BL  104  switch to bias level in read, e.g. 2.6v and 1.0v respectively to selected memory cells for reading. 
         [0034]    A Read Margin0 operation is performed after programming the whole array to detect weak programming cells. After programming, the cell current is at a very low value normally &lt;nano amperes (nA), this corresponds to reading out a ‘0’ digital value (no cell current). However some cells may marginally stay at a couple micro amperes (due to weak programming due to various reasons such as cell leakage, weak cell programming coupling ratio, process geometrical effect, etc. . . . ) and this can causing read ‘0’ to fail during the operating lifetime of the memory device  50 . A Read Margin° is used to screen out those weak cells. For Read Margin° waveform, the SL  110  is at standby value, e.g., 0v. The EG  106  is at standby value, e.g., 0v or 2.6v, or alternatively switching to a bias value in read, e.g. 2.6v as same in Read Normal condition. The WL  102  and BL  104  switch to bias level in read, e.g. 2.6v and 1.0v respectively to selected memory cells for reading as in Read Normal condition. The CG  106  is biased at a margin0 value (provided by same circuit means described in  FIG. 6-8  as for program or read condition) in read, e.g. 3v, to detect weak programmed cells. The CG voltage will couple into FG potential to amplify the weak programming effect, effectively increase the cell current, so the weak cells now read as a ‘1’ instead of a ‘0’ (effectively there is cell current instead of no cell current). 
         [0035]    A Read Margin1 operation is performed after erasing the whole array to detect weak erased cells. Negative CG now (provided by same circuit means described in  FIG. 6-8  as for erasing with negative voltage) is utilized to detect this condition. The SL  110  is at standby value, e.g., 0v. The EG  108  is at standby value, e.g., 0v or 2.6v, or alternatively switching to a bias value in read, e.g. 2.6v as same in Read Normal condition. The WL  102  and BL  104  switch to bias level in read, e.g. 2.6v and 1.0v respectively to selected memory cells for reading as in Read Normal condition. The CG  106  is biased at a margin1 value in read, e.g. −3v, to detect weak erased cells. The CG voltage will couple negatively into FG potential to amplify the weak erased effect, effectively decrease the cell current (less FG potential), so the weak erased cells now read as a ‘0’ instead of a ‘1’ (effectively there is no cell current instead of cell current). 
         [0036]    Referring to  FIG. 4A  there is shown one example of a circuit diagram of the Xdecoder  200  for use in the memory device  50  of the present invention. The Xdecoder circuit  200  provides the decoded address signals to be supplied to the word lines  22  of the selected and unselected memory cells  10 . The Xdecoder circuit  200  operates in the following manner. NAND gate  201  and INV  202  is used for decoding wordline (row) pre-decoded signal XPA-XPC (which is called memory sector (address) selection). Circuit  280  consists of a pre-driver and a driver. PMOS transistors  210  and  211  and NMOS transistor  212  are wordline pre-driver combined with pre-decoded XPZ&lt;0:7&gt;. Pre-decoded signals XPZ&lt;0:7) is used to select one row out of eight (by being =‘0’). PMOS transistor  213  and NMOS transistor  214  are wordline WL driver, used to drive a memory row that includes typically 2048 or 4096 cells in a row and hence needing big size transistor for wordline RC delay, i.e., large W/L ratio, W=transistor width and L=transistor length. The circuit  280  is repeated 8 times and NAND  201  and INV  202  is repeated one time for 8 rows per memory sector size. Typically the source of the transistor  214  is connected to a ground node (i.e., 0v) for de-selection condition, here it is connected to a node NWLLOW  240 . The source of the transistor  213  is connected to a node ZVDD  220 , which is equal to Vwlrd (read wordline voltage) in read operation, equal to Vpwl (programming wordline voltage in programming operation). For programming condition, for selected wordline, WL=ZVDD=Vpwl=1.0v for example, for unselected WLs=NWLLOW, which is equal to −0.5v. For erase condition, for selected wordline WL and un-selected WLS=NWLLOW=−0.5v in one embodiment. For read condition, for selected wordline, WL=ZVDD=Vwlrd=2v for example, for un-selected wordlines WLS=NWLLOW, which is equal to −0.5v in one embodiment. 
         [0037]    Referring to  FIG. 4B  there is shown one example of a circuit diagram of a negative charge pump generator  260  (which is part of the charge pump  56  that provides both negative and positive voltages) for generating a negative voltage to be supplied to the word lines  22 . The negative charge pump circuit  260  operates in the following manner. In a first time period, PMOS transistor  263  and NMOS transistor  266  are used to charge (+)  268  and (−) terminal  269  of a capacitor  265  to a positive bias voltage NBIAS  267  and a ground level (i.e., 0v) respectively. In a next time period after the first period, the transistor  266  is turned off and a NMOS transistor  264  is turned on to discharge the (+) terminal  268  of the capacitor  265  from a bias level  268  to ground level. At this time, the (−) terminal  269  of the capacitor  265  will be capacitively coupled to a negative level, e.g., −0.5v, depending on value of the capacitor  265  to the capacitive loading at the node NWLLOW  240 . By adjusting level of NBIAS  267  and the value of the capacitor  265 , the negative level is adjusted. For the embodiment of a semiconductor process using P substrate=0v (grounded) for forming the memory device  50 , e.g., single well CMOS (P-substrate for N type devices and a single N well for P type devices), the negative level is clamped at a P/N+ forward junction forward bias (˜−0.6v). As is well known, the memory device  50  can be made of a twin well P-sub CMOS process, in which two wells (P well and N well) are constructed in the substrate  12 . Since the substrate  12  is of P type conductivity, a first P well therein would be for N type devices (NMOS), and a second N type well would be for P type devices (PMOS). The negative voltage charge pump generator  260  and the wordline decoder  200  can be made in a triple well in the substrate  12 . This is done by a triple well CMOS process instead of the twin well P-sub CMOS process described earlier. In that event, the negative pump generator  260  and the wordline decoder  200  would be made in a third P type well (which is made in the second N type well, which is inside the substrate  12 ) and the second N type well. This third P type well can now be applied negative voltage which is advantageous in certain operating conditions. Although constructing the memory device  50  having a triple well is more process intensive, the benefit of having the pump generator  260  and the wordline decoder  200  in a triple well is that the negative voltage applied to the word line  22  can be more negative, for example −6.0v used for an erase embodiment, (i.e. not clamped by the P/N+ junction forward bias ˜−0.6v). In this case the third P type well voltage condition can be negative to avoid the P/N+ junction forward bias, e.g, −6.0v or −8.0v or −5.6v. In an embodiment the memory cell  10  can be formed in the third P type well. 
         [0038]    Referring to  FIG. 5  there is shown a first embodiment of a high voltage decoding circuit  300  for positive/negative level signals for use in the memory device  50  of Psub CMOS process of the present invention. A circuit  320  consisting of hv (high voltage, e.g. 12v) PMOS transistors  321  and  322  and hv NMOS transistor  323  and lv (low voltage, e.g., 3v) transistors  324  and  325  are used for decoding EG signal for erase/program/read operation. The transistor  322  (EG current limiter) is used to limit current in erase and/or program (to limit current sinking from the HV charge pump). A circuit  310  is a hv latch circuit used to enable the hv control for the sector (1 sector per 8 rows) selected, which is selected once a WL signal is asserted (˜Vdd) at the beginning of the erase or programming sequence as shown in  FIG. 3A . A circuit  350  consisting of native hv NMOS transistor  351 , inverter  352 , NAND  353 , a lv latch (consisting of inverter  354  and  355  and set lv NMOS transistors  356 ,  359 ,  358  and reset lv NMOS transistor  357 ) is used to disable the hv signal if the sector is bad sector (not to be used). A circuit  330  consisting of lv PMOS transistors  331  and  332  and hv PMOS transistor  333  is used to provide CG bias level in standby and read. The transistor  331  (its gate is at a bias level) acts as current limiter to CG terminal to limit current from bad CG terminal such as in standby condition. A circuit  340  consisting of hv PMOS transistors  341  and  342  is used to provide CG bias level in erase/program. The transistor  341  could act as current limiter to CG terminal in erase/program to limit current supplied from HV chargepump. A circuit  360  consisting of hv PMOS transistor  361 , hv native NMOS transistor  362 , lv NMOS transistors  363  and  364  is used to disable the CG. A circuit  370  consisting of hv PMOS transistor  371 , hv NMOS transistor  373  and lv NMOS transistor  372  is used to enable SL signal for erase/program/read condition. The lv NMOS transistor  372  is used to pulldown the SL to ground in read and erase and to a bias level, e.g. &lt;2v, in program. A circuit  380  is a negative decoding circuit for the CG signal. The circuit  360  uses PMOS transistor  361  as isolation transistor to isolate negative level (provided by the circuit  380  going into CG terminal of memory cell) from the NMOS transistor  362  for Psub CMOS process. The circuit  380  uses clocked negatively bootstrapped high voltage circuit scheme. The circuits  380  consists of PMOS transistors  381 ,  382 ,  385 - 391  and NOR  384  and inverter  384 . The NOR  384  and inverter  384  is used to enable a clocking signal into the PMOS transistors  386  and  388  which act as a capacitor to negatively pumping gate of the transistor  387 . The transistor  385  acts as a bootstrap transistor for the PMOS transistor  387  and the PMOS capacitors  386  and  388 . The transistors  381 / 390  and  382 / 391  serves to clamp the drain of the transistor  387  and the drain of the transistor  385  respectively at Vdd level. The transistor  389  serves as a buffer for negative level into CG. The sources of transistors  385  and  387  connect to a negative power supply VCGNEG  399 . 
         [0039]    Referring to  FIG. 6  there is shown second embodiment of a high voltage decoding circuit  400  for positive/negative level signals for use in the memory device  50  of Triple well CMOS process of the present invention. The circuits  310 - 350 ,  370  are same or similar as those of  FIG. 5 . A circuit  410  consisting of hv NMOS transistor  410  and lv NMOS transistors  412 - 414  is used for de-selecting the CGs to a low level, e.g., 0v. The hv transistor  410  serves as isolation transistor to isolate the negative level into CGs, hence its bulk VCGNEG also at a negative level. A circuit  420 , serves as a negative level shifter, is used to provide negative level for CGs. The circuit  420  consists of NAND  421 , inverter  422  as enabling entity and hv PMOS transistors  423  and  424  and hv NMOS transistors  425  and  426  as a cross-coupled negative latch and hv NMOS transistor  427  as a buffer. The sources of NMOS transistors  425 ,  426 ,  427  connect to a negative power supply VCGNEG. 
         [0040]    Referring to  FIG. 7  there is shown third embodiment of a high voltage decoding circuit  420  for positive/negative level signals for use in the memory device  50  of Psub CMOS process of the present invention. It used a diode decoding scheme for negative voltage. The circuits  310 - 370  are same or similar as those of  FIG. 5 . A circuit  510  consisting of hv PMOS transistor  512  is used to provide negative level into CGs. The transistor  512  is diode-connected, meaning gate-drain connected together, and its gate-drain is connected to a negative power supply VCGNEG. Its source is connected to CG. Hence as the negative power supply VCGNEG goes negative, the source of the transistor goes negative by an amount=VCG NEG−|Vtp|. 
         [0041]    Referring to  FIG. 8  there is shown a negative charge pump  600  that generates the negative voltages that are applied to the coupling gate  26  during the erase operation. A circuit  610  consists of PMOS transistors  612  and  613  and capacitors  611  and  614  constitutes a pump stage. The transistor  613  is the transfer transistor (transferring charge from one stage to next stage). The transistor  612  and the capacitor  611  serves as Vt-cancelling function for the transferring transistor  613 . The capacitor  614  is the pump capacitor (meaning provide pumping charge). A diode-connected PMOS transistor  620  connects to a power supply node to first pump stage. A diode connected PMOS transistor  640  serves to connect to an output charge pump node from last pump stage. PMOS transistors  650  and  652  serve to clamp or initialize internal pumped nodes. Various clock generation, phase driver, and biases are not shown. 
         [0042]    Referring to  FIG. 9  there is shown an embodiment of a negative high voltage regulation circuit  700  for use in the memory device  50  of the present invention. Capacitors  702  and  704  are used to divide the negative voltage from the negative power supply VCGNEG  399  into a voltage to be compared with a reference voltage VREF  708 , e.g. 1v. The VREF  708  is coupled to a terminal of a comparator  710 . A transistor  714  is used to initialize node  706  to a bias voltage, e.g., 2v. The node  706  is coupled to other terminal of the comparator  710 . As the negative supply VCGNEG  399  is pumped negative progressively from a level such as ground, the node  706  proportionally goes from a bias level, e.g. positive 2v, to progressively lower in a negative direction (by the ratio determined by values of the capacitors  702  and  704 ). Once the node  706  reaches a value equal to VREF  708 , the comparator  710  switches polarity. The output REGOUT  718  is then used to signal that the negative power supply VCGNMEG  399  has reached a desired level such as −9v used for CG in erase condition. 
         [0043]    Referring to  FIG. 10  there is shown an embodiment of a negative test pad circuit  800  for use in the memory device  50  in Psub CMOS process of the present invention. PMOS transistor  810  serves to isolate NMOS transistor  812  to a negative level to be transferred from internal to external pad or vice versa. The transistor  810  has its bulk connected to its drain for the purpose of isolation. The transistor  812  serves as ESD clamping. 
         [0044]    Referring to  FIGS. 11A and 11B  there are shown prior art embodiments of a process flow cross section  900  and  901  to produce memory cells having positive high voltage operation of the prior art. A memory cell includes layer  902  (Oxide,SIN),  904  (CG poly),  905  (ONO),  906  (FG poly),  908  (EG poly),  912  (SL diffusion layer),  910  (oxide between EG and SL),  914  (FG gate oxide),  916  (side nitride layer),  955  (WL poly). For process flow cross section  900 , peripheral HV device includes  982  (gate poly),  988  (channel region underneath the gate poly), LDD  980  (LDD implant). For this case the peripheral HV gate poly  982  is thick which can stop the LDD implant  980  from going into the channel region  988 . For process flow cross section  901 , which is applicable to advanced smaller geometry technology node, the memory cell includes thin WL poly  965  (thin compared to the thickness of the WL  955  shown in  FIG. 11A ), and peripheral HV device includes  984  (gate poly),  988  (substrate), LDD  980  (LDD implant). The gate poly  984  is significantly thinner than that of the gate poly  982 . In this case LDD implant  980  penetrates gate poly  984  into the channel region  988  which modulate the channel  988  electrically. This effect is undesirable. In this case additional masking and/or process layer step may be needed to stop LDD implant from penetrating into the channel. 
         [0045]    Referring to  FIG. 11C  there is shown an embodiments of a process flow for the production of memory cells  10  having negative voltage operation for use in the memory device  50  in the present invention. LDD implant  981  in this case is significantly lower energy due to the lower high voltage requirement, e.g. 9v vs. 11v for negative voltage operation. Hence in this case even with smaller geometry technology node, with thin gate poly  982  thickness, LDD implant does not penetrate into the channel  988 . This process flow hence is suitable for producing memory cell for use with negative voltage operation. 
         [0046]    The benefits of applying a negative voltage to the word line  22  of the unselected or selected memory cells  10  during the operations of read, erase and program are to allow the memory cell to be scaled down more effectively. During erase, negative voltage on wordline of selected memory cells allows overall erase voltage to be lowered thus allowing cell dimension to be smaller (sustaining less voltage across various inter-cell or inter-layer dimensional horizontal or vertical spacing, isolation, width, length, etc. . . . ). During program, negative voltage on wordline of unselected memory cells reduces leakage for un-selected memory cells leading to less disturb (for un-selected cells in same sector), more accurate programming current (for selected cells, less leakage interference) and less power consumption. For read, negative voltage on wordline of unselected memory cells leads to more accurate sensing due to less interference from leakage. It is also advantageous to combine negative wordline, negative coupling gate and negative P substrate for use in memory array operation resulting in lowered erase/program voltages and current, more effective erasing and programming, less cell disturb, and less cell leakage.