Abstract:
A circuitry of an IC is provided, including a pad, an internal circuit, and an ESD protection circuit. The pad transmits or receives a signal and is coupled to a first node. The internal circuit is coupled to the first node for processing the signal. The ESD protection circuit includes an ESD clamping circuit, a first current limiting and shunting unit and a second current limiting and shunting unit. The ESD clamping circuit is coupled to the first node, for clamping an ESD current flowing through the first node. The first current limiting and shunting unit is through the first node coupled to the pad, for limiting the ESD current and shunting part of the ESD current to a first voltage path. The second current limiting and shunting unit is coupled to the first current limiting and shunting unit, for limiting the ESD current and shunting part of the ESD current to a second voltage path.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The invention relates to an electrostatic discharge (ESD) protection circuit, and in particular relates to an ESD protection circuit using diffusion resistors and parasitic diodes of the diffusion resistors. 
         [0003]    2. Description of the Related Art 
         [0004]    For semiconductor manufacturing process development, dimensions of complementary metal-oxide-semiconductor transistor (CMOS) have reached sub-micron level to upgrade the performance of very large scale integrated (VLSI) circuits and computational speed. As dimensions shrinks, reliability and ESD tolerance of VLSI circuits decline significantly. 
         [0005]    ESD models include human-body model (HBM), machine model (MM), and charged-device model (CDM). All three generate instantaneous current of several amperes only for hundreds of or even several nanoseconds. 
         [0006]    Due to the size of the VLSI circuit shrinking to a micrometer or nanometer, the VLSI circuits are easily damaged by electrostatic discharge (ESD) when the electrostatic discharge current exorbitantly exceeds the internal circuit limit. If the circuit line width of the VLSI circuit is increased, the VLSI circuit can tolerate or endure a much bigger ESD current but the size of the VLSI circuit increases. Additionally, increasing circuits in one chip would increase the chip size. An alternative way to avoid ESD damage in VLSI circuits is to prevent electrostatic discharge current from flowing through the internal circuits, wherein, limiting the electrostatic discharge current from flowing through the internal circuits is the focus of this invention. 
       BRIEF SUMMARY OF THE INVENTION 
       [0007]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
         [0008]    An embodiment of a circuitry of an IC is provided, comprising a pad, an internal circuit, and an ESD protection circuit. The pad transmits or receives a signal and is coupled to a first node. The internal circuit is coupled to the first node for processing the signal. The ESD protection circuit includes an ESD clamping circuit, a first current limiting and shunting unit and a second current limiting and shunting unit. The ESD clamping circuit is coupled to the first node, for clamping an ESD current flowing through the first node. The first current limiting and shunting unit is through the first node coupled to the pad, for limiting the ESD current and shunting part of the ESD current to a first voltage path. The second current limiting and shunting unit is coupled to the first current limiting and shunting unit, for limiting the ESD current and shunting part of the ESD current to a second voltage path. 
         [0009]    Another embodiment of an ESD protection circuit for protecting an internal circuit from being damaged by an ESD current is provided. The ESD protection circuit comprises a first diffusion resistor and a second diffusion resistor. The first diffusion resistor is coupled to a pad and the internal circuit, for limiting the ESD current and shunting part of the ESD current to a first voltage path. The second diffusion resistor is coupled to the first diffusion resistor, for limiting the ESD current and shunting part of the ESD current to a second voltage path, wherein when the first diffusion resistor is N-type, the second diffusion resistor has a type different from the N-type, and when the first diffusion resistor is P-type, the second diffusion resistor has a type different from the P-type. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0011]      FIG. 1  is an ESD protection circuit; 
           [0012]      FIG. 2  is an ESD protection circuit according to an embodiment of the invention; 
           [0013]      FIG. 3  is an ESD protection circuit according to another embodiment of the invention; 
           [0014]      FIG. 4  is an ESD protection circuit according to another embodiment of the invention; 
           [0015]      FIG. 5  is an ESD protection circuit according to another embodiment of the invention; 
           [0016]      FIG. 6  is a specific MOS transistor according to another embodiment of the invention; 
           [0017]      FIG. 7  is a cross section along X-X′ line shown in  FIG. 6  when the transistor of  FIG. 6  is an NMOS transistor according to another embodiment of the invention; and 
           [0018]      FIG. 8  is a cross section along X-X′ line shown in  FIG. 6  when the transistor of  FIG. 6  is a PMOS transistor according to another embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0019]    The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
         [0020]      FIG. 1  is a diagram of a circuitry of an IC having an ESD protection circuit  100  which blocks ESD from an I/O pad  106  to an internal circuit  110 . The ESD protection  100  comprises a pull up (PU) ESD clamping circuit  102 , a pull down (PD) ESD clamping circuit  104 , and a resistor R 1 . The I/O pad  106  is coupled to a node  121  for receiving or transmitting a signal. The pull up ESD clamping circuit  102  is coupled between a first voltage path (Vdd) and the node  121  for clamping ESD signal under voltage level Vdd. The pull down ESD clamping circuit  104  is coupled between the node  121  and a second voltage path (Vss) for clamping the ESD signal above voltage level Vss. If the transmission gates Mn 1  and Mp 1  of the internal circuit  110  are not large enough to sustain the current flowing through drains thereof under ESD stress, damage at the transmission gates Mn 1  and Mp 1  may occur. The resistor R 1 , a current-limiting resistor, can reduce the ESD current to prevent damage of the internal circuit  110 . Due to resistor R 1 , the current through the transmission gates Mn 1  and Mp 1  is largely reduced and internal circuit damage is prevented. However, exorbitantly large resistor may degrade the signal bandwidth or distort the signal substantially. 
         [0021]      FIG. 2  shows another ESD protection circuit  200  implemented between an I/O pad  206  and an internal circuit  210  according to an embodiment of the invention. The ESD protection circuit  200  comprises a pull up ESD clamping circuit  202 , a pull down ESD clamping circuit  204 , and limiting and shunting units  232  and  233 . The I/O pad  206  is coupled to a node  221  for receiving or transmitting a signal. The pull up ESD clamping circuit  202  is the same as the pull up ESD clamping circuit  102  and the pull down ESD clamping circuit  204  is the same as the pull down ESD clamping circuit  104 . The first limiting and shunting units  232  is through the node  221  coupled to the I/O pad  206 , and limits the ESD current and shunting part of the ESD current from flowing into the internal circuit  210 ; for example, the ESD current can be shunted to the first voltage path (Vdd). The first current limiting and shunting unit  232  comprises a diffusion resistor R 2  for limiting the ESD current and a parasitic diode D 1  for shunting part of the ESD current to the first voltage path (Vdd), as shown in  FIG. 2 . The second limiting and shunting units  233  is coupled to the first current limiting and shunting unit  232  in serial, and limits the ESD current and shunts part of the ESD current from flowing into the internal circuit  210 ; for example, the ESD current can be shunted to the second voltage path (Vss). The second current limiting and shunting unit  233  comprises a diffusion resistor R 3  for limiting the ESD current and a parasitic diode D 2  for shunting part of the ESD current to the second voltage path (Vss), as shown in  FIG. 2 . The diffusion resistor R 2  and the diffusion resistor R 3  are preferred to have different type, e.g. the diffusion resistor R 2  is N-type and its N well is coupled to the voltage level VDD, and the diffusion resistor R 3  is P-type and its P well is coupled to the voltage level VSS. Because the parasitic diodes D 1  and D 2  of the diffusion resistors R 2  and R 3  can shunt the ESD current, the resistance sum of diffusion resistors R 2  and R 3  is smaller than the resistance of resistor R 1 . Therefore, signal bandwidth will not be exorbitantly degraded and the signal will not be exorbitantly distorted. Moreover, layout of the diffusion resistors R 2  and R 3  can be separately fine-tuned to match the size of the internal circuit  210 , and the internal ESD protection and layout area can thereby be optimized. 
         [0022]      FIG. 3  is an ESD protection circuit  300  according to another embodiment of the invention. The ESD protection circuit  300  comprises a pull up ESD clamping circuit  302 , a pull down ESD clamping circuit  304 , and current limiting and shunting units  332  and  333 . The ESD protection circuit  300  is similar to the ESD protection circuit  200 . The difference is that the current limiting and shunting units are connected in serial or parallel. The first current limiting and shunting unit  332  comprises a diffusion resistor R 4  for limiting the ESD current and a parasitic diode D 4  for shunting part of the ESD current to the first voltage path (Vdd). The second current limiting and shunting unit  333  comprises a diffusion resistor R 5  for limiting the ESD current and a parasitic diode D 5  for shunting part of the ESD current to the second voltage path (Vss), as shown in  FIG. 3 . 
         [0023]      FIG. 4  is an ESD protection circuit  400  according to another embodiment of the invention. The ESD protection circuit  400  comprises a pull up ESD clamping circuit  402 , a pull down ESD clamping circuit  404 , and current limiting and shunting units  432  and  433 . The ESD protection circuit  400  of  FIG. 4  is amended from the ESD protection circuit  200  of  FIG. 2 . The first current limiting and shunting unit  432  has similar functions to the resistor R 2  and the parasitic diode D 1 , and the second current limiting and shunting unit  433  also has similar functions to the resistor R 3  and the parasitic diode D 2 , as shown in  FIG. 2 . The first current limiting and shunting unit  432  is a specific NMOS transistor  441  and the drain terminal of the specific NMOS transistor  441  is configured to have increased impedance illustrated by resistor R 4  in  FIG. 4  to limit the ESD current. The second current limiting and shunting unit  433  is a specific PMOS transistor  442  and the drain terminal of the specific PMOS transistor  442  is configured to have increased impedance illustrated by resistor R 5  in  FIG. 4  to limit the ESD current. The specific NMOS and PMOS transistors are discussed later in  FIG. 6 . 
         [0024]      FIG. 5  is an ESD protection circuit  500  according to another embodiment of the invention. The ESD protection circuit  500  comprises a pull up ESD clamping circuit  502 , a pull down ESD clamping circuit  504 , and current limiting and shunting units  532  and  533 . The ESD protection circuit  500  of  FIG. 5  is amended from the ESD protection circuit  300  of  FIG. 3 . The first current limiting and shunting unit  532  has similar functions to the resistor R 4  and the parasitic diode D 4  and the second current limiting and shunting unit  533  also has similar functions to the resistor R 5  and the parasitic diode D 5 , as shown in  FIG. 3 . The first current limiting and shunting unit  532  is a specific NMOS transistor  541  and the drain terminal of the specific NMOS transistor  541  is configured to have increased impedance illustrated by resistor R 4  in  FIG. 5  to limit the ESD current. The second current limiting and shunting unit  533  is a specific PMOS transistor  542  and the drain terminal of the specific PMOS transistor  542  is configured to have increased impedance illustrated by resistor R 5  in  FIG. 5  to limit the ESD current. The specific NMOS and PMOS transistors are discussed later in  FIG. 6 . 
         [0025]      FIG. 6  is a specific MOS transistor  600  according to another embodiment of the invention. The MOS transistor  600  can be the current limiting and shunting units  432  and  433  of  FIG. 4 . The drain of the MOS transistor  600  comprises first contacts  601 , second contacts  602  and a silicide block area  603 . The silicide block area  603  is formed by masking silicide film during fabrication process or removing the silicide after the fabrication process. Since the silicide block area  603  has fewer or no conducting material, the resistance of the region increases. Using the current limiting and shunting unit  432  as an example, the contacts  601  are coupled to the first node  421 . The contacts  602  are coupled to the second node  422 . The silicide block area  603  is formed between the contacts  601  and  602  as the diffusion resistor R 4  of  FIG. 4 . Similarly, using the current limiting and shunting unit  433  as an example, the contacts  601  are coupled to the second node  422 . The contacts  602  are coupled to the third node  423 . The silicide block area  603  is formed between the contacts  601  and  602  as the diffusion resistor R 5  of  FIG. 4 . Similarly, The MOS transistor  600  can be the current limiting and shunting units  532  and  533  of  FIG. 5 . 
         [0026]      FIG. 7  is a cross section along X-X′ line shown in  FIG. 6  when the transistor of  FIG. 6  is an NMOS transistor according to another embodiment of the invention. As shown in  FIG. 7 , in this case, the transistor  600  is an NMOS transistor. A resistor  701  is generated by the silicide block area. The resistor  701  can be equivalent to the resistor R 2  of  FIG. 2  or the resistor R 4  of  FIG. 3 . A diode  702  is formed between N Well and p+ area. The diode  702  can be equivalent to the diode D 1  of  FIG. 2  or the diode D 4  of  FIG. 3 . 
         [0027]      FIG. 8  is a cross section along X-X′ line shown in  FIG. 6  when the transistor of  FIG. 6  is a PMOS transistor according to another embodiment of the invention. As shown in  FIG. 8 , in this case, the transistor  600  is a PMOS transistor. A resistor  801  is generated by the silicide block area. The resistor  801  can be equivalent to the resistor R 3  of  FIG. 2  or the resistor R 5  of  FIG. 3 . A diode  802  is formed between P Well and n+ area. The diode  802  can be equivalent to the diode D 2  of  FIG. 2  or the diode D 5  of  FIG. 3 . 
         [0028]    While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited to thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.