Abstract:
A method and apparatus for measuring an AC voltage. In one embodiment, the apparatus comprises an AC voltage monitor, comprising a solid state electrical isolation device, enabled to (i) generate at least a first voltage measurement of an AC power source, (ii) generate a serial data stream frame based on the at least a first voltage measurement, and (iii) transmit the serial data stream frame via the solid state electrical isolation device.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present invention is a continuation of co-pending U.S. patent application Ser. No. 12/381,809, filed Mar. 17, 2009, which claims benefit of U.S. provisional patent application Ser. No. 61/070,797, filed Mar. 26, 2008. Each of the aforementioned patent applications is herein incorporated in its entirety by reference. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    Embodiments of the present invention generally relate to a method and apparatus for measuring AC voltages. 
         [0004]    2. Description of the Related Art 
         [0005]    In today&#39;s quest for obtaining energy from renewable resources, solar power is becoming an increasingly desirable option. Photovoltaic (PV) modules utilized in solar power systems convert energy from sunlight received into direct current (DC). The PV modules cannot store the electrical energy they produce, so the energy must either be dispersed to an energy storage system, such as a battery or pumped hydroelectricity storage, or dispersed by a load. One option to use the energy produced is to employ one or more inverters to convert the DC current into an alternating current (AC) and couple the AC current to the commercial power grid. 
         [0006]    PV power inverters coupled to the commercial power grid must constantly monitor the voltage of the Utility Power (grid) at the inverter location to comply with relevant Underwriters Laboratories (UL) and Institute of Electrical and Electronic Engineers (IEEE) standards, in particular UL-1741 ed. 1 “Standard for Inverters, Converters, Controllers and Interconnection System Equipment for Use with Distributed Energy Resources”, May 1999, and IEEE 1547-2003 “IEEE Standard for Interconnecting Distributed Resources with Electric Power Systems”. Additionally, other devices that may be coupled to the grid, such as uninterruptable power supplies (UPS), must also monitor the grid power and comply with certain isolation standards. 
         [0007]    In monitoring the grid, each phase of the grid voltage must be monitored and measured separately. Traditionally, grid monitoring circuits utilize transformers to isolate and step-down the grid voltages before sampling the AC voltage on each phase of the grid. Such transformers are bulky, heavy, and expensive. Additionally, these transformers continuously consume power and may exhibit distortion problems. 
         [0008]    Therefore, there is a need for a method and apparatus to efficiently measure AC voltages. 
       SUMMARY OF THE INVENTION 
       [0009]    Embodiments of the present invention generally relate to a method and apparatus for measuring an AC voltage. In one embodiment, the apparatus comprises an AC voltage monitor, comprising a solid state electrical isolation device, enabled to (i) generate at least a first voltage measurement of an AC power source, (ii) generate a serial data stream frame based on the at least a first voltage measurement, and (iii) transmit the serial data stream frame via the solid state electrical isolation device. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments. 
           [0011]      FIG. 1  is a block diagram of an AC voltage monitor for providing isolated AC voltage monitoring in accordance with one or more embodiments of the present invention; 
           [0012]      FIG. 2  is a block diagram of a power supply circuit in accordance with one or more embodiments of the present invention; 
           [0013]      FIG. 3  depicts a block diagram of a scaling circuit, a microcontroller, and an optocoupler in accordance with one or more embodiments of the present invention; and 
           [0014]      FIG. 4  is a method  400  for isolated AC voltage monitoring in accordance with one or more embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0015]      FIG. 1  is a block diagram of an AC voltage monitor  102  for providing isolated AC voltage monitoring in accordance with one or more embodiments of the present invention. The AC voltage monitor  102  is coupled to a three-phase AC commercial power grid (“grid”) and to a device  112 , and comprises a power supply circuit  104 , a scaling circuit  106 , a microcontroller  108 , and an optocoupler  110  (i.e., a solid state isolation device). In some embodiments, the power supply circuit  104  may be a state of the art AC/DC converter (e.g., a diode bridge, capacitor and flyback converter). The device  112  may be any device requiring voltage measurements from an AC line, such as a UPS, inverter, micro-inverter, and the like. 
         [0016]    The power supply circuit  104  is coupled to each line of the grid, i.e., L 1 , L 2 , L 3 , and N; lines L 1 , L 2 , and L 3  carry a first, a second, and a third phase, respectively, of a three-phase AC voltage on the grid (“grid voltage”), and line N provides a neutral line. The power supply circuit  104  is additionally coupled, via two output terminals, to the microcontroller  108  and generates DC power from the grid voltage for powering the microcontroller  108 . 
         [0017]    In addition to the power supply circuit  104 , the scaling circuit  106  is also coupled to each line of the grid and to the microcontroller  108 . The scaling circuit  106  couples a scaled version of the grid voltage (“scaled grid voltage”) to the microcontroller  108 ; in some embodiments, such a scaled grid voltage comprises a reduction of the grid voltage by two orders of magnitude. The microcontroller  108  samples (i.e., measures) the voltage on each phase of the scaled grid voltage, as well as the scaled neutral line voltage, and generates a serial data stream comprising line-to-neutral voltage data representing each phase of the grid voltage (i.e., a digital representation of the three-phase AC grid voltage). The microcontroller  108  transmits the serial data stream through the optocoupler  110  to the device  112  in order to provide electrical isolation between the device  112  and the grid; in one or more other embodiments, an alternative solid state isolation device may be utilized in place of the optocoupler  110 . 
         [0018]    In alternative embodiments, the AC voltage monitor  102  may be coupled to an alternate three-phase AC voltage source or to a two-phase or single-phase AC voltage source. 
         [0019]      FIG. 2  is a block diagram of a power supply circuit  104  in accordance with one or more embodiments of the present invention. The power supply circuit  104  converts AC power from the grid to DC power for powering digital electronics of the microcontroller  108 . 
         [0020]    The power supply circuit  104  comprises capacitors  202 ,  204 ,  206 ,  220 ,  222 ,  224 , and  226 ; diodes  208 ,  210 ,  212 ,  214 ,  216 , and  218 ; resistors  228  and  230 ; and zener diode  232 . First terminals of the capacitors  202 ,  204 , and  206  are coupled to the lines L 1 , L 2 , and L 3 , respectively. Second terminals of the capacitors  202 ,  204 , and  206  are coupled to cathode terminals of the diodes  214 ,  216 , and  218 , respectively, and anode terminals of the diodes  208 ,  210 , and  212 , respectively. Cathode terminals of the diodes  208 ,  210 , and  212  are coupled to a first terminal of the capacitor  220  and a first terminal of a resistor R 1 . A second terminal of the resistor R 1  is coupled to a first terminal of the capacitor  224 , an anode terminal of the zener diode  232 , and an output terminal “VP” of the power supply circuit  104 . A second terminal of the capacitor  220  is coupled to a second terminal of the capacitor  224 , a first terminal of the capacitor  222 , a first terminal of the capacitor  226 , and the neutral line. A resistor R 2  is coupled across the second terminals of the capacitors  222  and  226 . The second terminal of the capacitor  226  is further coupled to an anode terminal of the zener diode  232  and an output terminal “VN” of the power supply circuit  104 . 
         [0021]    A high voltage/low frequency AC voltage from the grid is present across each of the capacitors  202 ,  204 , and  206 , resulting in a small amount of current through such capacitors and thereby limiting current flow in the circuit. The current flow through the capacitors  202 ,  204 , and  206  is rectified by the diodes  214 ,  216 ,  218 ,  208 ,  210 , and  212 , and charges capacitors  220  and  222  depending upon the phase of the grid voltage. Additionally, the capacitors  220  and  222  provide protection against any voltage surges from the grid by absorbing the additional energy passing through the capacitors  202 ,  204 , and  206 . Capacitors  220  and  222  generally are orders of magnitude greater than the capacitors  202 ,  204 , and  206 , but do not require being rated for high voltage. In some embodiments, the capacitors  220  and  222  may be on the order of  1  microfarad, while the capacitors  202 ,  204 , and  206  may be on the order of tens of microfarads. 
         [0022]    The rectified current is smoothed by the resistors  228 / 230  and the capacitors  224 / 226 , and subsequently stabilized by the zener diode  232 . The zener diode  232  sets the output voltage magnitude at the zener voltage for providing a low voltage DC supply to power the microcontroller  108 , for example on the order of 3-5 volts. In alternative embodiments, the zener diode  232  may be replaced by a different voltage reference to regulate the output voltage across VP and VN. 
         [0023]      FIG. 3  is a block diagram of a scaling circuit  106 , a microcontroller  108 , and an optocoupler  110  in accordance with one or more embodiments of the present invention. The scaling circuit  106  comprises resistors  322 ,  324 ,  326 ,  328 ,  330 , and  332 . The resistor pairs  322 / 324 ,  326 / 328 , and  330 / 332  are each coupled in series across lines L 1  and N, L 2  and N, L 3  and N, respectively, forming voltage dividers between each phase of the grid and the neutral line N. Resistance values may be selected such that each voltage divider is a high-ratio voltage divider, for example dividing each voltage by a factor of one hundred. In some embodiments, capacitors  334 ,  336 , and  338  are coupled across the resistors  332 ,  328 , and  324 , respectively, to provide low-pass filtering. 
         [0024]    The scaling circuit  106  provides a scaled version of the three-phase AC grid voltage (“scaled grid voltage”), i.e., a representative sample of the voltage on each phase and neutral line of the grid, to the microcontroller  108  for digitizing and processing. 
         [0025]    The microcontroller  108  may be a conventionally available microcontroller, such as a Programmable Intelligent Computer (PIC). The microcontroller  108  is comprised of a processor  302  coupled to a memory  304 , support circuits  310 , clock circuits  312 , universal asynchronous receiver-transmitter (UART)  314 , and analog-to-digital converter (ADC) bank  316 . The processor  302  may comprise one or more conventionally available microprocessors; additionally and/or alternatively, the processor  302  may include one or more application specific integrated circuits (ASICs). The support circuits  310  are well known circuits used to promote functionality of the processor  302 , such as but not limited to a cache, power supplies, clock circuits, buses, network cards, input/output (I/O) circuits, and the like. 
         [0026]    The memory  304  may comprise random access memory, read only memory, removable disk memory, flash memory, and various combinations of these types of memory. The memory  304  is sometimes referred to as main memory and may, in part, be used as cache memory or buffer memory. Additionally, the memory  304  may store various forms of application software and/or firmware, such as voltage monitoring firmware  308  for determining the line-to-neutral voltage data based on digitized samples of the grid voltage and determining framing information for the serial data stream. The clock circuits  312  support the microcontroller  108  by providing timing signals. UART  314  transmits the serial data stream to the device  112 . 
         [0027]    The microcontroller  108  samples (i.e., measures) and digitizes the scaled grid voltage via the ADC bank  316 . The ADC bank  316  is comprised of analog to digital converters ADC 1 , ADC 2 , ADC 3 , and ADC 4  for sampling and digitizing the scaled grid voltages from lines L 3 , L 2 , L 1 , and N, respectively. The line-to-neutral voltages (VL 1 N, VL 2 N, and VL 3 N) for each phase of the grid voltage are computed by subtracting the sampled neutral voltage from the sampled phase voltages: 
         [0000]      VL1N=VL1−VN   (1)
 
         [0000]      VL2N=VL2−VN   (2)
 
         [0000]      VL3N=VL3−VN   (3)
 
         [0028]    Where VL 1 , VL 2 , and VL 3 , are the voltage samples representing the voltages on lines L 1 , L 2 , and L 3 , respectively, and VN is the voltage sample representing the voltage on the neutral line. Generally, the voltages VL 1 , VL 2 , VL 3 , and VN are measured sequentially and the line-to-neutral voltages computed immediately thereafter, for example within a few microseconds, thereby allowing for a rapid refresh rate. 
         [0029]    For each set of line-to-neutral voltages computed, the processor  302  constructs a frame word for identifying a serial data stream frame comprising the line-to-neutral voltage data. In some embodiments, the frame word may be constructed utilizing a 4-bit frame counter (e.g., 0000, 0001, 0010), a 4-bit parity or cyclic redundancy check (CRC) code, and the like; in alternative embodiments, more or fewer bits may be utilized. The frame word may also be padded to a length that is identical to the length of the words for each of the computed line-to-neutral voltages. 
         [0030]    The line-to-neutral voltage data and the frame word are coupled to the UART  314  for transmission as a serial data stream frame; in some embodiments, the UART  314  may utilize settings such as one start bit, eight to ten data bits, one optional parity bit, and one stop bit for transmitting each word. Each frame of the serial data stream comprises data representing the computed line-to-neutral voltage for each phase of the grid, as well as the frame word to identify the frame within the serial data stream. For example, each serial data stream frame may be transmitted as a sequence of words “VL 1 N, VL 2 N, VL 3 N, frame word”. 
         [0031]    The UART  314  transmits the serial data stream frame to the device  112  via the optocoupler  110 , where the optocoupler  110  provides electrical isolation between the device  112  and the grid. In some embodiments, a resistor  340  may be coupled between the UART  314  and the optocoupler  110 . 
         [0032]    Upon receiving the transmitted serial data stream, the device  112  may utilize the line-to-neutral voltage data to determine various information pertaining to the grid voltage, such as line-to-line instantaneous voltages, line-to-line phase angles, line RMS voltages, zero crossing information, and the like. In some embodiments, framing criteria utilized by the device  112  for determining a valid in-frame condition may consist of four contiguous valid frame counter nibbles received. Out-of-frame criteria may consist of receiving two contiguous erroneous frame counter nibbles, or two contiguous parity or CRC errors. During out-of-frame periods, the device  112  discards the corresponding line-to-neutral voltage data received. 
         [0033]      FIG. 4  is a flow diagram of a method  400  for isolated AC voltage monitoring in accordance with one or more embodiments of the present invention. In some embodiments, such as the embodiment described below, an AC voltage monitor (e.g., the AC voltage monitor  102 ) is coupled to a multi-phase AC power source, for example a three-phase commercial power grid; alternatively, the AC voltage monitor may be coupled to a different three-phase AC power source or a two-phase or single-phase AC power source. The AC voltage monitor is further coupled to a device requiring isolated monitoring of the AC voltages from the AC power source. In some embodiments, the AC voltage monitor may comprise a power supply circuit, such as a state of the art AC/DC converter (e.g., a diode bridge, capacitor and flyback converter), for converting AC power from the AC power source to DC power for powering digital electronics of the AC voltage monitor. 
         [0034]    The method  400  begins at step  402  and proceeds to step  404 , where a microcontroller of the AC voltage monitor is initialized. At step  406 , the microcontroller samples (i.e., measures) the AC line voltage on each line of the AC power source via an ADC bank, such as ADC bank  316 . For example, for a three-phase AC power source, the voltage on each phase (i.e., lines L 1 , L 2 , and L 3 ) is sampled as well as the voltage on the neutral line (i.e., N). The resulting digitized samples provide an accurate representation of the actual voltage on each line (each phase and neutral line) of the AC power source. In some embodiments, the AC voltages from the AC power source may be scaled, for example by a voltage divider, and/or low-pass filtered prior to being sampled. 
         [0035]    The method  400  proceeds to step  408 . At step  408 , a line-to-neutral voltage is computed for each phase by subtracting the sampled neutral line voltage from each sampled phase voltage (i.e., the sampled voltages from L 1 , L 2 , and L 3 ). Generally, the voltages on each line of the AC power source are measured sequentially and the line-to-neutral voltages computed immediately thereafter, for example within a few microseconds, allowing for a rapid refresh rate. 
         [0036]    At step  410 , a frame word is constructed. In some embodiments, the frame word may be constructed utilizing a 4-bit frame counter (e.g., 0000, 0001, 0010), a 4-bit parity or cyclic redundancy check (CRC) code, and the like; in alternative embodiments, fewer or more bits may be utilized. Additionally, the frame word may be padded to a length that is identical to the length of the words for each of the computed line-to-neutral voltages. 
         [0037]    At step  412 , data representing the computed line-to-neutral voltages and the frame word is transmitted as a frame of a serial AC voltage stream, for example by a universal asynchronous receiver-transmitter (UART), to the device. The serial data stream frame is transmitted to the device via a solid state isolation device, such as an optocoupler, to provide isolation between the device and the AC power source. 
         [0038]    Upon receiving the transmitted serial data stream frame, the device may utilize the line-to-neutral voltage data to determine various information pertaining to the grid voltage, such as line-to-line instantaneous voltages, line-to-line phase angles, line RMS voltages, zero crossing information, and the like. In some embodiments, framing criteria utilized by the device for determining a valid in-frame condition may consist of four contiguous valid frame counter nibbles received. Out-of-frame criteria may consist of receiving two contiguous erroneous frame counter nibbles, or two contiguous parity/CRC errors. During out-of-frame periods, the device discards the corresponding line-to-neutral voltage data received. 
         [0039]    The method  400  proceeds to step  414 , where a determination is made whether another set of line-to-neutral voltages are to be computed and transmitted. If the result of such determination is yes, the method  400  returns to step  406 . If the result of the determination at step  414  is no, the method  400  proceeds to step  416  where it ends. 
         [0040]    While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.