Abstract:
A method and a fiber channel switch element for processing receive-modify-send (“RMS”) frames in a fiber channel network are provided. The method includes, determining if a received frame is a RMS frame; modifying the RMS frame without copying the RMS frame to a transmit buffer; and transmitting the modified frame. The RMS frame is modified in a receive buffer before being sent to the transmit buffer and a port state machine controls the receive buffer where RMS frames are modified. The switch element includes a port having a state machine that determines if a received frame needs to be modified before being transmitted, and if the frame is to be modified then such modification occurs in a receive buffer without being copied to a transmit buffer before such modification. A buffer select logic selects the appropriate buffer for modifying and transmitting frames from.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority under 35 USC Section 119(e), to the following provisional patent applications: 
     Ser. No. 60/487,876 filed on Jul. 16, 2003; 
     Ser. No. 60/487,887 filed on Jul. 16, 2003; 
     Ser. No. 60/487,875 filed on Jul. 16, 2003; 
     Ser. No. 60/490,747 filed on Jul. 29, 2003; 
     Ser. No. 60/487,667 filed on Jul. 16, 2003; 
     Ser. No. 60/487,665 filed on Jul. 16, 2003; 
     Ser. No. 60/492,346 filed on Aug. 4, 2003; and 
     Ser. No. 60/487,873 filed on Jul. 16, 2003. 
     The disclosures of the foregoing applications are incorporated herein by reference in their entirety. 
    
    
     BACKGROUND 
     1. Field of the Invention 
     The present invention relates to networks, and more particularly, to accelerating receive-modify-send frames in a fibre channel network. 
     2. Background of the Invention 
     Fibre channel is a set of American National Standard Institute (ANSI) standards, which provide a serial transmission protocol for storage and network protocols such as HIPPI, SCSI, IP, ATM and others. Fibre channel provides an input/output interface to meet the requirements of both channel and network users. 
     Fibre channel supports three different topologies: point-to-point, arbitrated loop and fibre channel fabric. The point-to-point topology attaches two devices directly. The arbitrated loop topology attaches devices in a loop. The fibre channel fabric topology attaches host systems directly to a fabric, which are then connected to multiple devices. The fibre channel fabric topology allows several media types to be interconnected. 
     Fibre channel is a closed system that relies on multiple ports to exchange information on attributes and characteristics to determine if the ports can operate together. If the ports can work together, they define the criteria under which they communicate. 
     Traditional fibre channel port implementations maintain frame buffers for transmit-side separate from the receive-side. This separation prevents contention during full-duplex operations, but induces unnecessary firmware overhead for “Receive-Modify-Send” fibre channel frames. 
       FIG. 2A  shows a conventional implementation of receive and transmit buffers in a fibre channel port  200  coupled to fibre channel network  206 . A Receive (“Rx”) Buffer  201  may be in use at the same time as a Transmit (“Tx”) Buffer  202  if FC Port  200  supports full-duplex data transfers. Separating the buffers for receive-side from transmit-side prevents contentions and/or race conditions. FC Port State Machine  205  implements the state machine requirements as per the Fibre Channel standard using control information  203  and  204 . For example, the FC Port State Machine  205  in an Arbitrated Loop environment would implement the Loop Port State Machine (LPSM), as per the FC-AL standard. 
       FIG. 2B  shows incoming frames  207  that are received in buffer  201 / 202 .  FIG. 2C  shows outgoing frame(s)  208  from transmit buffer  202 . 
       FIG. 2D  shows the process flow for frames that are received and then modified before transmission (“Receive-Modify-Send” frames also referred to as “RMS frames”). Frame  207 A is an RMS frame that is received by the Rx buffer  201 . Firmware detects if an RMS frame is received. Thereafter, the frame is copied ( 209 ) to Tx buffer  202 . The frame is modified in the Tx buffer  202  and then sent out as frame  210 . 
     The conventional techniques are cumbersome and slow because RMS frames have to be copied first and then modified in the Tx buffer. This requires extra firmware operation and slows the overall system. 
     Therefore, there is a need for a method and system to efficiently process RMS frames in FC networks. 
     SUMMARY OF THE INVENTION 
     In one aspect of the present invention, a method for processing receive-modify-send (“RMS”) frames in a fibre channel network is provided. The method includes, determining if a received frame is a RMS frame; modifying the RMS frame without copying the RMS frame to a transmit buffer; and transmitting the modified frame. The RMS frame is modified in a receive buffer before being sent to the transmit buffer and a port state machine controls the receive buffer where RMS frames are modified. 
     In another aspect of the present invention, a fibre channel switch element coupled to an arbitrated loop in a network is provided. The switch element includes a port having a state machine that determines if a received frame needs to be modified before being transmitted, and if the frame is to be modified then such modification occurs in a receive buffer without being copied to a transmit buffer before such modification. A buffer select logic selects the appropriate buffer for modifying and transmitting frames from. 
     In yet another aspect of the present invention, a fibre channel network is provided. The network includes, a fibre channel switch element including a port having a state machine that determines if a received frame needs to be modified before being transmitted, and if the frame is to be modified then such modification occurs in a receive buffer without being copied to a transmit buffer before such modification. 
     This brief summary has been provided so that the nature of the invention may be understood quickly. A more complete understanding of the invention can be obtained by reference to the following detailed description of the preferred embodiments thereof concerning the attached drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The foregoing features and other features of the present invention will now be described with reference to the drawings of a preferred embodiment. In the drawings, the same components have the same reference numerals. The illustrated embodiment is intended to illustrate, but not to limit the invention. The drawings include the following Figures: 
         FIG. 1  shows a block diagram of a storage area network; 
         FIGS. 2A-2D  show prior art configurations for processing frames; 
       FIGS.  3 A/ 3 B show block diagrams of a system for processing RMS frames, according to one aspect of the present invention; 
         FIG. 4  shows a block diagram of a switch element, according to one aspect of the present invention; 
         FIG. 5A and 5B  (jointly referred to as  FIG. 5 ) show a block diagram of a transmission protocol engine, according to one aspect of the present invention; and 
         FIGS. 6A and 6B  show block diagrams for a diagnostic module and a SES module, according to one aspect of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Definitions: 
     The following definitions are provided as they are typically (but not exclusively) used in the fibre channel environment, implementing the various adaptive aspects of the present invention. 
     “AL_PA”: Arbitrated loop physical address. 
     “FC-AL”: Fibre channel arbitrated loop process described in FC-AL standard incorporated herein by reference in its entirety. 
     “Fibre channel ANSI Standard”: The standard (incorporated herein by reference in its entirety) describes the physical interface, transmission and signaling protocol of a high performance serial link for support of other high level protocols associated with IPI, SCSI, IP, ATM and others. 
     “FC-1”: Fibre channel transmission protocol, which includes serial encoding, decoding and error control. 
     “FC-2”: Fibre channel signaling protocol that includes frame structure and byte sequences. 
     “FC-3”: Defines a set of fibre channel services that are common across plural ports of a node. 
     “FC-4”: Provides mapping between lower levels of fibre channel, IPI and SCSI command sets, HIPPI data framing, IP and other upper level protocols. 
     “LIP”: Loop initialization primitive. 
     “L_Port”: A port that contains Arbitrated Loop functions associated with the Arbitrated Loop topology. 
     “RMS” frames: Receive-Modify-Send frames 
     “SES”: SCSI Enclosure Services. 
     To facilitate an understanding of the preferred embodiment, the general architecture and operation of a fibre channel system will be described. The specific architecture and operation of the preferred embodiment will then be described with reference to the general architecture of the fibre channel system. 
       FIG. 1  is a block diagram of a fibre channel system  100  implementing the methods and systems in accordance with the adaptive aspects of the present invention. System  100  includes plural devices that are interconnected. Each device includes one or more ports, classified as node ports (N_Ports), fabric ports (F_Ports), and expansion ports (E_Ports). Node ports may be located in a node device, e.g. server  103 , disk array  105  and storage device  104 . Fabric ports are located in fabric devices such as switch  101  and  102 . Arbitrated loop  106  may be operationally coupled to switch  101  using arbitrated loop ports (FL_Ports). 
     The devices of  FIG. 1  are operationally coupled via “links” or “paths”. A path may be established between two N_ports, e.g. between server  103  and storage  104 . A packet-switched path may be established using multiple links, e.g. an N-Port in server  103  may establish a path with disk array  105  through switch  102 . 
       FIG. 4  is a block diagram of an 18-port ASIC FC element  400 A (also referred to as system  400 A) according to one aspect of the present invention. FC element  400 A provides various functionality in an FC-AL environment, including without limitation, FC element  400 A operates as a loop controller and loop switch using switch matrix  408 , in accordance with the FC-AL standard. 
     FC element  400 A of the present invention is presently implemented as a single CMOS ASIC, and for this reason the term “FC element” and ASIC are used interchangeably to refer to the preferred embodiments in this specification. Although  FIG. 4  shows 18 ports, the present invention is not limited to any particular number of ports. 
     System  400 A provides a set of port control functions, status indications, and statistics counters for monitoring the health of the loop and attached devices, diagnosing faults, and recovering from errors. 
     ASIC  400 A has 18 ports where 16 ports are shown as numeral  405  while a host port  404  and cascade port  404 A are shown separately for convenience only. These ports are generic to common Fibre Channel port types, for example, L_Ports. 
     For illustration purposes only, all ports are drawn on the same side of ASIC  400 A in  FIG. 4 . However, the ports may be located on any side of ASIC  400 A. This does not imply any difference in port or ASIC design. Actual physical layout of the ports will depend on the physical layout of the ASIC. 
     Each port has transmit and receive connections to switch matrix  408  and includes transmit protocol engine  407  and a serial/deserializer  406 . Frames enter/leave the link  405 A and SERDES  406  converts data into 10-bit parallel data to fibre channel characters. 
     Switch matrix  408  dynamically establishes a connection for loop traffic. Switch matrix  408  includes a global arbiter (hence switch matrix  408  is also referred to as SGA  408 ) that provides lower latency and improved diagnostic capabilities while maintaining full Fibre Channel Arbitrated Loop (FC-AL) compliance. 
     Switch matrix  408  provides a quasi-direct architecture in the form of a buffer-less Switch Matrix. Switch matrix  408  includes data multiplexers that provide a path to each port. 
     SGA  408  creates a direct loop connection between source and destination devices. This connection methodology avoids the delay associated with data having to pass from one disk drive member of the loop to the next until the data has completed traversing the loop. 
     System  400 A includes plural I2C (I2C standard compliant) interfaces  412 - 413  that allow system  400 A to couple to plural I2C ports each having a master and slave capability. Timer module  411  is used to monitor various timers (not shown) used by System  400 A. 
     System  400 A also includes a general-purpose input/output interface (“GPIO”)  415 . This allows information from system  400 A to be analyzed by any device that can use GPIO  415 . Control/Status information  419  can be sent or received through module  415 . 
     System  400 A also includes a SPI module  414  that is used for parallel to serial and serial to parallel transfer between processor  400  firmware and flash memory  421  in the standard Little Endian format. 
     System  400 A also includes a Universal Asynchronous Receiver/Transmitter (“UART”) interface  418  that converts serial data to parallel data (for example, from a peripheral device modem or data set) and vice-versa (data received from processor  400 ) complying industry standard requirements. 
     System  400 A can also process tachometer inputs (received from a fan, not shown) using module  417 . Processor  400  can read the tachometer input via a tachometer rate register and status register (not shown). 
     System  400 A provides pulse width modulator (“PWM”) outputs via module  416 . Processor  400  can program plural outputs. 
     System  400 A also includes two frame manager modules  402  and  403  that are similar in structure. Processor  400  can set both modules  402  and  403  into a data capture mode by using a control bit. Processor  400  can access runtime code from memory  420  and input/output instructions from read only memory  409 . 
     Port Management Interface (PMIF)  401  allows processor  400  access to various port level registers, SerDes modules  406  and TPE Management Interfaces  509  ( FIG. 5 ). PMIF  401  contains a set of global control and status registers, receive and transmit test buffers, and three Serial Control Interface (SCIF) controllers (not shown) for accessing SerDes  406  registers. 
     Module  402  (also referred to as the “diag module  402 ”) is a diagnostic module used to transfer diagnostic information between a FC-AL and the firmware of system  400 A. 
     Diag module  402  is functionally coupled to storage media (via ports  405 ) via dedicated paths outside switch matrix  408  so that its connection does not disrupt the overall loop. Diag module  402  is used for AL_PA capture during LIP propagation, drive(s) (coupled to ports  405 ) diagnostics and frame capture. 
     Module  403  (also referred to as “SES module  403 ”) complies with the SES standard and is functionally coupled to host port  404  and its output is routed through switch matrix  408 . SES module  403  is used for in-band management services using the standard SES protocol. 
     When not bypassed, modules  402  and  403  receive primitives, primitive sequences, and frames. Based on the received traffic and the requests from firmware, modules  402  and  403  maintain loop port state machine (LPSM) ( 615 ,  FIG. 6B ) in the correct state per the FC-AL standard specification, and also maintains the current fill word. 
     Based on a current LPSM  615  state (OPEN or OPENED State), modules  402  and  403  receive frames, pass the frame onto a buffer, and alert firmware that a frame has been received. Module  402  and  403  follow FC-AL buffer to buffer credit requirements. 
     Firmware may request modules  402  and  403  to automatically append SOF and EOF to the outgoing frame, and to automatically calculate the outgoing frame&#39;s CRC using CRC generator  612 . Modules  402  and  403  can receive any class of frames and firmware may request to send either fibre channel Class  2  or Class  3  frames. 
       FIGS. 6A and 6B  show block diagrams for module  402  and  403 . It is noteworthy that the structure in  FIGS. 6A and 6B  can be used for both modules  402  and  403 .  FIG. 6B  is the internal data path of a FC port  601  coupled to modules  402 / 403 . 
     Modules  402  and  403  interface with processor  400  via an interface  606 . Incoming frames to modules  402  and  403  are received from port  601  (which could be any of the ports  404 ,  404 A and  405 ) and stored in frame buffer  607 . Outgoing frames are also stored in frame buffer  607 . Modules  402  and  403  have a receive side memory buffer based on “first-in, first-out” principle, RX_FIFO (“FIFO”)  603  and TX_FIFO transmit side FIFO  604  interfacing with FIFO  605 . A receive side FIFO  603  signals to firmware when incoming frame(s) are received. A transmit side FIFO  604  signals to hardware when outgoing frames(s) are ready for transmission. A frame buffer  607  is used to stage outgoing frames and to store incoming frames. Modules  602  and  602 A are used to manage frame traffic from port  601  to buffers  603  and  604 , respectively. 
     Modules  402  and  403  use various general-purpose registers  608  for managing control, status and timing information. 
     Based on the AL_PA, modules  402  and  403  monitor received frames and if a frame is received for a particular module ( 402  or  403 ), it will pass the frame onto a receive buffer and alert the firmware that a frame has been received via a receive side FIFO  603 . Modules  402  and  403  follow the FC-AL buffer-to-buffer credit requirements using module  616 . Modules  402  and  403  transmit primitives and frames based on FC-AL rules. On request, modules  402  and  403  may automatically generate SOF and EOF during frame transmission (using module  613 ). On request, modules  402  and  403  may also automatically calculate the Cyclic Redundancy Code (CRC) during frame transmission, using module  612 . 
     Overall transmission control is performed by module  611  that receives data, SOF, EOF and CRC. A word assembler module  609  is used to assemble incoming words, and a fill word module  610  receives data “words” before sending it to module  611  for transmission. Transmit buffer control is performed by module  614 . 
       FIG. 3A  shows a system that can be used in modules  402  and  403  for processing RMS frames. For incoming-only frames and outgoing-only frames (i.e., the frames that don&#39;t need modification), the buffers are still separated to avoid contention during full-duplex operations as shown in  FIG. 2A . However, for RMS frames the prior art dual buffer scheme is modified as depicted by buffer scheme  300  in  FIG. 3A . 
       FIG. 3A  shows a set of buffers  301  that are controlled by state machine  205 . RMS frames ( 303 ,  FIG. 3B ) are received from network  206  and processed in buffers  301 . RMS frames  303  are not copied to TX buffers  202  before modification. After the frames are modified in buffers  301 , the frames are sent to Tx buffer  202  for transmission. Buffer select logic  302  controls selection of buffers based upon the type of frame, i.e., RMS or non-RMS frames. 
     The buffer scheme of  FIG. 3A  allows firmware to accelerate processing of RMS, as follows: 
     Firmware first detects if a Receive-Modify-Send frame has arrived. Viewing incoming frame headers performs this operation. If the incoming frames are RMS type, then system  400 A firmware modifies the frame in-place at Rx buffer  301 , without copying the frame to another buffer (Tx  202 ); and after the frames are modified, the frames are transmitted. 
       FIG. 3B  shows a block diagram for RMS frame flow, according to one aspect of the present invention. Incoming RMS frame  303  is modified in buffer  301  and is then moved to Tx buffer  202 . Buffer select module  302  then transmits the modified frame  304  to network  206 . 
       FIG. 5  shows a block diagram of the transmission protocol engine (“TPE”)  407 . TPE  407  maintains plural counters/registers to interact with drives coupled to ports  405 . Each TPE  407  interacts with processor  400  via port manager interface  401 . 
     Each Fibre Channel port of system  400 A includes a TPE module for interfacing with SerDes  406 . TPE  407  handles most of the FC- 1  layer (transmission protocol) functions, including  10 B receive character alignment,  8 B/ 10 B encode/decode, 32-bit receive word synchronization, and elasticity buffer management for word re-timing and TX/RX frequency compensation. 
     SerDes modules  406  handle the FC- 1  serialization and de-serialization functions. Each SerDes  406  port consists of an independent transmit and receive node. 
     TPE  407  has a receive module  500  (that operates in the Rx clock domain  503 ) and a transmit module  501 . Data  502  is received from SERDES  406  and decoded by decoding module  504 . A parity generator module  505  generates parity data. SGA interface  508  allows TPE to communicate with switch  514  or switch matrix  408 . Interface  508  (via multiplexer  507 ) receives information from a receiver module  506  that receives decoded data from decode module  504  and parity data from module  505 . 
     Management interface module  509  interfaces with processor  400 . Transmit module  501  includes a parity checker  511 , a transmitter  510  and an encoder  512  that encodes 8-bit data into 10-bit data. 10-bit transmit data is sent to SERDES  406  via multiplexer  513 . 
     In one aspect of the present invention, extra processing is not required because the frame is not copied from an Rx buffer to a Tx buffer. 
     Although the present invention has been described with reference to specific embodiments, these embodiments are illustrative only and not limiting. Many other applications and embodiments of the present invention will be apparent in light of this disclosure and the following claims.