Abstract:
A method of and an electronic apparatus for determining real-time data latency are disclosed. The method may include creating a plurality of outgoing data packets having an outgoing time stamp, a group identifier and validation information. The outgoing data packets may be transmitted onto a network. A plurality of incoming data packets may be received over the network. The incoming data packets may be validated. For each of the incoming data packets that is valid, a round-trip time delay for the incoming data packet may be calculated, and statistics for the incoming data packets may be updated based on the round-trip time delay and the group identifier included in the incoming data packet. The method may be implemented on an electronic apparatus.

Description:
RELATED APPLICATION 
     Related subject matter is disclosed in U.S. patent application Ser. No. 09/591,080 filed on Jun. 9, 2000, entitled Method of Determining Time Delay for Round-Trip Transmission of Data and Electronic Apparatus Therefor assigned to the same assignee hereby incorporated by reference. 
    
    
     FIELD OF THE INVENTION 
     This invention relates, in-general, to data transmission, and more particularly, to methods of determining real-time data latency and apparatuses therefor. 
     BACKGROUND OF THE INVENTION 
     A user accessing a computer server across a computer network must transmit data across the computer network from the user&#39;s computer to the computer server and must also receive data across the computer network from the computer server to the user&#39;s computer. Therefore, the user requires fast data transmission rates across the computer network and requires, in particular, fast round-trip data transmission across the computer network. However, as computer networks continuously grow in size and complexity, the data transmission rates associated with the larger and more complex computer networks may decrease. Accordingly, a need exists for a method of determining real-time data latency and an apparatus therefor. 
     SUMMARY OF THE INVENTION 
     In accordance with the principles of the invention, a method of determining real-time data latency can include transmitting a first plurality of data packets, each having a first packet group identification (PGID) and a time stamp, receiving a set of data packets, identifying PGIDs in the set of data packets, identifying time stamps in the set of data packets, using the time stamps to determine time delays for the set of data packets, comparing the time delays of the set of data packets having the first PGID to a first minimum time delay, comparing the time delays of the set of data packets having the first PGID to a first maximum time delay, summing a number of data packets in the set of data packets having the first PGID as a first total count, and summing the time delays of the set of data packets having the first PGID as a first total time delay. 
     Further, in accordance with the principles of the invention; an electronic apparatus for determining real-time data latency can include a data packet reception portion, a data packet signature verification portion coupled to the data packet reception portion, a data packet validity verification portion coupled to the data packet reception portion, a data packet packet group identification (PGID) identification portion coupled to the data packet reception portion, a statistic array retrieval portion coupled to the data packet signature verification portion, the data packet validity verification portion, and the data packet PGID identification portion, a time delay determination and statistics portion coupled to the statistic array retrieval portion and the data packet reception portion, and a statistic array storage portion coupled to the time delay determination and statistics portion and the data packet PGID identification portion. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The invention will be better understood from a reading of the following detailed description, taken in conjunction with the accompanying drawing figures in which: 
     FIG. 1 illustrates a block diagram of an electronic apparatus for determining real-time data latency in accordance with an embodiment of the invention; 
     FIG. 2 illustrates a flow chart for a method of determining real-time data latency in accordance with an embodiment of the invention; 
     FIGS. 3 through 6 illustrate flow charts of detailed portions of the method of FIG. 2 in accordance with an embodiment of the invention; and 
     FIG. 7 illustrates a graph of the statistics generated by the method of FIG. 2 in accordance with an embodiment of the invention. 
    
    
     For simplicity and clarity of illustration, the same reference numerals in different figures denote the same elements, and descriptions and details of well-known features and techniques are omitted to avoid unnecessarily obscuring the invention. 
     Furthermore, the terms first, second, third, fourth, and the like in the description and in the claims, if any, are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. However, it is understood that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein. It is further understood that the terms so used are interchangeable under appropriate circumstances. 
     DETAILED DESCRIPTION 
     FIG. 1 illustrates a block diagram of a portion of an electronic apparatus  100  for determining real-time data latency. Apparatus  100  includes a data packet reception portion  110 , a data packet signature verification portion  120 , a data packet validity verification portion  130 , a data packet Packet Group IDentification (PGID) identification portion  140 , a statistic array retrieval portion  150 , a time delay determination and statistics portion  160 , a statistic array storage portion  170 , and a memory portion  180 . Data packet reception portion  110  is coupled to data packet signature verification portion  120 , data packet validity verification portion  130 , data packet PGID identification portion  140 , and time delay determination and statistics portion  160 . Statistic array retrieval portion  150  is coupled to data packet signature verification portion  120 , data packet validity verification portion  130 , data packet PGID identification portion  140 , time delay determination and statistics portion  160 , and memory portion  180 . Statistic array storage portion  170  is coupled to time delay determination and statistics portion  160  and memory portion  180 . In the preferred embodiment, memory portion  180  is a Dynamic Random Access Memory (DRAM). Also in the preferred embodiment, data packet reception portion  110 , data packet signature verification portion  120 , data packet validity verification portion  130 , data packet PGID identification portion  140 , statistic array retrieval portion  150 , time delay determination and statistics portion  160 , and statistic array storage portion  170  are located within a Field Programmable Gate Array (FPGA), as indicated by a dashed line  190  in FIG.  1 . 
     A general description of the operation of apparatus  100  is as follows. Data packet reception portion  110  receives incoming data packets from a computer network. Data packet signature verification portion  120  verifies signatures in the received data packets. Data packet validity verification portion  130  verifies a validity of the received data packets. Data packet PGID identification portion  140  identifies PGIDs in the received data packets. Statistic array retrieval portion  150  retrieves statistics stored in memory portion  180 . Time delay determination and statistics portion  160  determines time delays for the received data packets, compares the time delays to the stored statistics, and, if necessary, updates the statistics. Statistic array storage portion  170  stores the updated statistics in memory portion  180 . A more detailed description of the operation of apparatus  100  is described with reference to the subsequent drawing figures. 
     FIG. 2 illustrates a flow chart for a method  200  of determining real-time data latency. At a step  205  of method  200 , data packets are created by a first electronic apparatus. Each data packet has a time stamp indicating a time when the data packet is transmitted from or out of the first electronic apparatus. Each data packet also includes a signature located at a signature offset within the data packet. The signature offset is the same for all data packets. As an example, the signature can be a unique string of 32 bits indicating that the data packet was transmitted from the first electronic apparatus. Each data packet has a size that is within a predetermined range. In the preferred embodiment for Ethernet networks, the minimum size for any data packet is 64 Bytes, and the maximum size for any data packet is 1518 Bytes. The data packets can have other sizes for non-Ethernet networks. 
     The data packets are grouped into one or more sets. Each data packet within a particular group or set has a PGID that is unique to that particular group and is different from the PGIDs of other data packets in other groups. The PGID can be a user-defined unique string of 16 bits. As an example, the PGIDs can represent different Internet Protocol (IP) addresses, different IP priorities, different data packet sizes, or different protocol mixes. The PGID within each data packet is located at a PGID offset within the data packet. The PGID offset is the same for all data packets. The PGID offset can be larger than or smaller than the signature offset. Each data packet within a particular group having a particular PGID can have different sizes. As an example, the different sizes may be the result of the data packets having different data patterns. 
     At a step  210  of method  200 , the first electronic apparatus transmits the data packets out of the first electronic apparatus during a first time period. The data packets are sent to a second electronic apparatus, which receives the data packets. This second electronic apparatus takes portions of the data packets and inserts them into new data packets. As an example, the time stamps of the data packets are inserted into the new data packets. The second electronic apparatus transmits the new data packets back to the first electronic apparatus. Step  210  can be performed continuously during all of the subsequent steps of method  200 . 
     Next, the first electronic apparatus receives these new data packets during a second time period, which is different from the first time period of step  205 . However, this second time period may overlap the first time period. At a step  215  of method  200 , the first electronic apparatus receives a single one of the new data packets. As an example, data packet reception portion  110  of apparatus  100  in FIG. 1 can perform step.  215  in FIG.  2 . 
     At a step  220  of method  200  in FIG. 2, the first electronic apparatus verifies or checks the signature in the received data packet of step  215 . Subsequently, at a step  225  of method  200 , the first electronic apparatus verifies or checks the validity of the received data packet of step  215 . The sequence of steps  220  and  225  can be reversed. Details of steps  220  and  225  are provided hereinafter with respect to FIG.  3  and FIG. 4, respectively. As an example, data packet signature verification portion  120  of apparatus  100  in FIG. 1 can perform step  220  in FIG. 2, and data packet validity verification portion  130  of apparatus  100  in FIG. 1 can perform step  225  of FIG.  2 . 
     At a step  230  in method  200 , the first electronic apparatus identifies a PGID in the received data packet of step  215 . The PGID in the received data packet is located at the same PGID offset as used previously in step  205 . The sequence of steps  220 ,  225 , and  230  may be altered or reversed. As an example, data packet PGID identification portion  140  of apparatus  100  in FIG. 1 can perform step  230  in FIG.  2 . 
     Next, at a step  235  in method  200 , the first electronic apparatus identifies a time stamp in the received data packet of step  215 . Time stamps in the received data packet originates from a time stamp in one of the transmitted data packets of steps  205  and  210 . In other words, the time stamp of the received data packet indicates the time at which the source or original data packet was transmitted from the first electronic apparatus at step  210 . As an example, time delay determination and statistics portion  160  of apparatus  100  in FIG. 1 can perform step  235  in FIG.  2 . 
     At a step  240  of method  200 , the first electronic apparatus uses the time stamp of the received data packet of step  215  to determine a time delay or latency for the received data packet. In particular, the first electronic apparatus subtracts the time indicated by the time stamp from the time at which the data packet was received by the first electronic apparatus in step  215 . This time delay represents a round-trip time delay for the data packet. As an example, time delay determination and statistics portion  160  of apparatus  100  in FIG. 1 can perform step  240  of FIG.  2 . 
     At a step  245  of method  200 , the first electronic apparatus updates a set of statistics with the time delay and other statistics from the received data packet. In particular, the first electronic apparatus updates a particular set of statistics for the PGID contained in the received data packet. The details of step  245  are explained hereinafter with respect to FIGS. 5 and 6. As an example, statistic array retrieval portion  150 , time delay determination and statistics portion  160 , and statistic array storage portion  170  of apparatus  100  in FIG. 1 can be used to perform step  245  of FIG.  2 . 
     Next, steps  215 ,  220 ,  225 ,  230 ,  235 ,  240 , and  245  can be repeated numerous times. Additional data packets having the same PGID as the first received data packet can be received, and the set of statistics for the same PGID can be successively updated. Other data packets having a PGID different from that of the first received data packet can be received, and another set of statistics for this different PGID can be successively updated. For a particular received data packet, step  215  can be performed while performing steps  220 ,  225 ,  230 , and  235  and before receiving a subsequent data packet. Also for a particular received data packet, steps  240  and  245  can be performed after terminating step  215  and can be performed before or while receiving the next data packet. 
     After repeating steps  215 ,  220 ,  225 ,  230 ,  235 ,  240 , and  245  for a predetermined period of time, a step  250  of method  200  is performed. At step  250 , the first electronic apparatus displays the statistics for the received data packets. Steps  215 ,  220 ,  225 ,  230 ,  235 ,  240 , and  245  can be repeated or performed continuously while performing step  250 . 
     As an example of different statistical displays of step  250  in method  200 , FIG. 7 illustrates a graph of instantaneous latency determined by method  200  in FIG.  2 . The graph in FIG. 7 has an X-axis or horizontal axis representing the different PGIDs of the received data packets. The graph also has a Y-axis or vertical axis representing a magnitude of the time delay or latency in the round-trip transmission of the data packets. The graph in FIG. 7 illustrates four different PGIDs, each having a minimum time delay, an average time delay, and a maximum time delay over a specific instance in time. 
     FIG. 3 illustrates a flow chart of a detailed portion of method  200  in FIG.  2 . In particular, FIG. 3 illustrates additional details of step  220  in FIG.  2 . At a step  321  in FIG. 3, the first electronic apparatus identifies a signature in the received data packet of step  215  in FIG.  2 . The signature in the received data packet is located at a signature offset within the received data packets. This signature offset is the same offset as the signature offset used in step  205  of FIG.  2 . At a step  322  of FIG. 3, the first electronic apparatus compares the signature of the received data packet to the signature of the created and transmitted data packets in steps  205  and  210  of FIG.  2 . At a step  323  of FIG. 3, the first electronic apparatus rejects the received data packet if its signature fails to match the signature of the transmitted data packets. If a received data packet is rejected during step  323 , the rejected data packet is immediately discarded and is not processed any further in method  200 . Accordingly, after rejecting a received data packet during step  323 , method  200  continues by receiving another data packet during step  215  of FIG.  2 . 
     FIG. 4 illustrates a flow chart of a different detailed portion of method  200  in FIG.  2 . In particular, FIG. 4 illustrates additional details of step  225  of FIG.  2 . At a step  421  of FIG. 4, the first electronic apparatus checks a Cyclic Redundancy Check (CRC) value of the received data packet. To perform step  421 , the first electronic apparatus calculates a CRC value for the received data packet, and identifies a CRC value in the received data packet. Then, the first electronic apparatus compares the calculated CRC value to the CRC value in the received data packet. At a step  422  of FIG. 4, the first electronic apparatus rejects the received data packet if its CRC value is incorrect. An incorrect CRC value indicates an invalid data packet. If a received data packet is rejected during step  422 , the rejected data packet is immediately discarded and is not processed any further in method  200 . Accordingly, after rejecting a received data packet during step  422 , method  200  continues by receiving another data packet during step  215  of FIG.  2 . 
     If the received data packet is not rejected during step  422  of FIG. 4, step  225  continues by performing a step  423  in FIG.  4 . At step  423 , the first electronic apparatus calculates the size of the received data packet and compares the calculated size to a predetermined range of sizes. At a step  424 , the first electronic apparatus rejects the received data packet if its calculated size is outside of the predetermined range described earlier with respect to step  205  in FIG. 2. A size outside of the predetermined range of sizes indicates an invalid data packet. If a received data packet is rejected during step  424 , the rejected data packet is immediately discarded and is not processed any further in method  200 . Accordingly, after rejecting a received data packet during step  424 , method  200  continues by receiving another data packet during step  215  of FIG.  2 . 
     FIG. 5 illustrates a flow chart of an additional detailed portion of method  200  in FIG.  2 . In particular, FIG. 5 illustrates additional details of step  245  in FIG.  2 . At a step  541  in FIG. 5, the first electronic apparatus retrieves a set of stored statistics, for the PGID contained in the received data packet of step  215  in FIG.  2 . As an example, the set of stored statistics can be retrieved from memory portion  180  in FIG.  1 . The set of stored statistics can include a minimum time delay, a maximum time delay, a total number of received data packets having the PGID, a total time delay for all of the received data packets having the PGID, and a total number of bytes or byte count for all of the received data packets having the PGID. The set of stored statistics reflects the statistics for only those received data packets having the same PGID. 
     The PGID of the received data packet is used to perform step  541 . For example, the set of statistics is retrieved from a first array located at a first memory address in a memory portion. The first memory address in the memory portion is identified by the PGID of the received data packet. 
     Next, at a step  542  in FIG. 5, the first electronic apparatus compares the time delay determined during step  240  of FIG. 2 to time delays in the set of stored statistics retrieved during step  541 . Additional details of step  542  are explained hereinafter with respect to FIG.  6 . Then, at a step  543  in FIG. 5, the first electronic apparatus increases by one the total count or number of received data packets in the set of statistics. At a step  544 , the first electronic apparatus adds the time delay determined during step  240  of FIG. 2 to the total time delay in the set of statistics. At a step  545  of FIG. 5, the first electronic apparatus calculates the number of bytes in the received data packet and adds this number to the total number of bytes or byte count in the set of statistics. The sequence of steps  542 ,  543 ,  544 , and  545  can be altered or reversed. 
     Next, at a step  546 , the first electronic apparatus stores the updated set of statistics. The PGID of the received data packet is used to perform step  546 . For example, the set of statistics is stored back into the first array located at the first memory address in the memory portion. The first memory address in the memory portion is identified by the PGID of the received data packet. 
     The first electronic apparatus uses the updated set of statistics to perform step  250  in FIG.  2 . For example, to display or graph the minimum time delay for a PGID, the first electronic apparatus displays or graphs the minimum time delay stored in the updated set of statistics for the PGID. As an additional example, to display or graph the maximum time delay for a PGID, the first electronic apparatus displays or graphs the maximum time delay stored in the updated set of statistics for the PGID. Furthermore, to display or graph the average time delay for a PGID, the first electronic apparatus divides the first total time delay in the set of statistics by the first total count in the set of statistics. 
     FIG. 6 illustrates a flow chart of additional details for step  542  of FIG.  5 . At a step  641  in FIG. 6, the first electronic apparatus compares the calculated time delay for the received data packet to a minimum time delay in the retrieved set of statistics of step  541  in FIG.  5 . At a step  642  of FIG. 6, the first electronic apparatus replaces the minimum time delay in the retrieved set of statistics with the-calculated time delay for the received data packet if the calculated time delay is less than the minimum time delay in the retrieved set of statistics. At a step  643  of FIG. 6, the first electronic apparatus compares the time delay of the received data packet to a maximum time delay in the retrieved set of statistics of step  541  in FIG.  5 . At a step  644  of FIG. 6, the first electronic apparatus replaces the maximum time delay in the retrieved set of statistics with the calculated time delay for the received data packet if the calculated time delay is greater than the maximum time delay in the retrieved set of statistics. The calculated time delay is preferably not stored individually in the memory portion unless the calculated time delay is a maximum or minimum time delay for the particular PGID. 
     Therefore, an improved method of determining real-time data latency and an apparatus therefor is provided to overcome the disadvantages of the prior art. The method enables the detection of an increase or decrease in the time delay for the round-trip transmission of data across a computer network. 
     Although the invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes may be made without departing from the spirit or scope of the invention. For instance, the numerous details set forth herein such as, for example, the specific sequence of steps are provided to facilitate the understanding of the invention and are not provided to limit the scope of the invention. Furthermore, the method described herein is not limited to the round-trip transmission of data between two electronic devices. Instead, the method can be modified and applied to the round-trip or non-round-trip transmission of data between three or more electronic devices. Accordingly, the disclosure of embodiments of the invention is intended to be illustrative of the scope of the invention and is not intended to be limiting. It is intended that the scope of the invention shall be limited only to the extent required by the appended claims.