Abstract:
Circuits and methods for driving gates lines of a flat panel display, wherein gate driver circuit architectures provide compact designs that enable smaller chip sizes for gate driver ICs. In one aspect, a semiconductor integrated gate driver IC comprises a plurality of gate driver circuits, wherein each gate driver circuit drives a corresponding gate line of a display, and a level shifter circuit, for generating a precharge control signal for the gate driver circuits. Each gate driver circuit comprises a line decoder for decoding a gate line control signal and generating a decoded gate line control signal and a precharge circuit for precharging a gate driver turn-on voltage in response to the precharge control signal before activating the gate line. During a driving phase, the precharged gate driver turn-on voltage is discharged when the gate line is activated in response to the decoded gate line control signal, whereas the precharged gate driver turn-on voltage is maintained when the gate line is not activated in response to the decoded gate line control signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims priority to Korean Patent Application No. 2003-63939, filed Sep. 16, 2003, in the Korean Intellectual Property Office.  
       TECHNICAL FIELD OF THE INVENTION  
       [0002]     The present invention relates generally to circuits and methods for driving flat panel displays (e.g., a liquid crystal display (LCD)) and, in particular, to gate driver circuits and methods for driving gates lines of flat panels displays, wherein gate driver circuit architectures provide compact designs that enable smaller chip sizes for gate driver ICs.  
       BACKGROUND  
       [0003]     Various types of flat panel displays such as liquid crystal displays (LCDs), plasma display panels (PDPs), electroluminescence display panels, LED display panels, etc., have been developed to replace traditional cathode ray tube (CRT) displays. Such flat panel displays are suitable for devices and applications requiring small dimension, light weight and low power consumption. For example, LCDs can be operated using a large scale integration (LSI) driver since LCDs can be driven by a low-voltage power supply and have low power consumption. Accordingly, LCDs have been widely implemented for laptop computers, pocket computers, automobiles, and color televisions, etc. The light weight, smaller dimension, and lower power consumption features of LCD devices render such display devices suitable for use with, e.g., portable, handheld devices.  
         [0004]     In general, the signals that are used for driving flat panel displays are voltage or current signals that are either proportional or inversely proportional to the desired brightness of pixels of the display. The driving signals are generated from driving devices/apparatus (which include semiconductor integrated circuits (ICs)) disposed adjacent to the display panel. Depending on the display type, the driving signals will operate to change the panel electrically or optically.  
         [0005]      FIG. 1  is a schematic diagram that illustrates a conventional display system. The display system ( 100 ) comprises a display panel ( 110 ) (e.g., LCD) and a plurality of components for driving/controlling the display panel ( 110 ) including, e.g., a controller ( 120 ), a gate driver IC ( 130 ) and a source driver IC ( 140 ). The display panel ( 110 ) comprises a plurality of data lines (DL 1 ˜DLn) that are connected to the source driver IC ( 140 ) and a plurality of gate lines (GL 1 ˜GLn) that are connected to the gate driver IC ( 130 ). The display panel ( 110 ) comprises a plurality of pixels arrayed in a matrix of rows and columns, wherein the pixels in a given row are commonly connected to a gate line (GL 1 ) and wherein the pixels in a given column are commonly connected to a data line (DL 1 ). The display panel ( 110 ) displays an image in response to source signals output to the data lines (DL 1 ˜DLn) from the source driver IC ( 140 ) and gate driver control signals output to the gate lines (GL 1 ˜GLn) from the gate driver IC ( 130 ).  
         [0006]     More specifically, the controller ( 120 ) receives as input a plurality of driving data signals and driving control signals that are output from an image supply source (e.g., a main board of a computer). The driving data signals comprise R, G, B data for forming an image on the display ( 110 ). The driving control signals comprise vertical synchronous signals (Vsynch), horizontal synchronous signals (Hsync), a data enable signal (DE) and a clock signal (Clk). The controller ( 120 ) outputs to the source driver IC ( 140 ) a plurality of data signals R′, G′ and B′ (driving data), which correspond to the input R, G, B data, and a source control signal (SC) (driving control signal). The controller ( 120 ) outputs a gate control signal (SG) to control the gate driver IC ( 130 ).  
         [0007]     The gate driver IC ( 130 ) receives as input a plurality of DC voltages including VDD (logic power supply voltage), V SS  (logic ground voltage), V GH  (gate driver turn-on voltage), V GOFF  (gate driver turn-off voltage) and V COM  (common electrode voltage). The gate driver IC ( 130 ) outputs gate driver controls signals (having logic levels of V GH  or V GOFF ) to the gate lines (GL 1 ˜GLn) to drive selected gate lines. The source driver IC ( 140 ) determines source signals to be output to the data lines (DL 1 ˜DLn) in response to the data signals (R′, G′, B′) and the source control signal (SC).  
         [0008]     The controller ( 120 ) controls the timing for which data and control signals are output from the source driver IC ( 140 ) and gate driver IC ( 130 ). For example, in one mode of operation, the controller ( 120 ) generates the control signals SC and SG such that the gate driver IC ( 130 ) transmits a gate driver output signal V GH  to each gate line (GL 1 ˜GLn) in a consecutive manner and data voltage is selectively applied to each pixel in an activated row one by one in order. In another mode of operation, the pixels can be charged by sequentially scanning pixels in a first column and thereafter scanning pixels in a next column.  
         [0009]     Assuming the display panel ( 110 ) is a TFT-LCD, the display panel ( 110 ) would include a thin-film transistor (TFT) board comprising a plurality of pixel units arranged in matrix form. As shown in  FIG. 1 , each pixel unit comprises a TFT ( 150 ), a liquid crystal capacitor ( 151 ), which is connected between a drain electrode of the TFT ( 150 ) and a common electrode (V COM ), and a thin-film storage capacitor ( 152 ), which is connected in parallel with the liquid crystal capacitor ( 151 ). The storage capacitor ( 152 ) stores an electric charge so that an image on the display is maintained during a non-selected period. The liquid crystal capacitor ( 151 ) is formed by a common electrode (V COM ) of a color filter plate, a pixel electrode of the TFT ( 150 ) and liquid crystal material therebetween. A source electrode of the TFT ( 150 ) is connected to a data line (DL 1 ) and a gate electrode of the TFT ( 150 ) is connected to a gate line (GL 1 ). The TFT ( 150 ) acts as a switch that applies a source voltage on the data line (DL 1 ) to the pixel electrode when a gate driver signal of V GH  on the gate line (GL 1 ) is applied to the gate of the TFT ( 150 ).  
         [0010]      FIG. 2  is a block diagram that schematically illustrates a gate driver IC having a conventional architecture, which can be implemented in the system of  FIG. 1  for driving a flat panel display such as a TFT-LCD. In general, as depicted in  FIG. 2 , a conventional gate driver ( 200 ) comprises a row driver selecting unit ( 210 ), a line decoder ( 220 ), voltage level shifter circuits ( 230 ) and buffers (drivers) ( 240 ). The row driver selecting unit ( 210 ) generates a gate line control signal, G[m: 0 ] in response to a driver control signal (STV) that specifies one of a plurality of gate lines (GL 1 ˜GLn) to be selected. The line decoder ( 220 ) comprises a plurality of line decoders ( 220 - 1 ˜ 220 - n ), each associated with one of the gate lines (GL 1 ˜GLn). Each line decoder ( 220 - 1 ˜ 220 - n ) decodes the gate line control signal G[m: 0 ] and generates a corresponding decoded gate line control signal (GD[ 1 ]˜GD[n]).  
         [0011]     The voltage level shifter circuits ( 230 ) comprise a plurality of separate level shifter circuits ( 230 - 1 ˜ 230 - n ), each associated with one of the gate lines (GL 1 ˜GLn). Each level shifter circuit ( 230 - 1 ˜ 230 - n ) receives a corresponding decoded gate line control signal (GD[ 1 ]˜GD[n]) output from a corresponding line decoder ( 220 - 1 ˜ 220 - n ). DC voltages, V GH  and V GOFF  are applied to each level shifter circuit ( 230 - 1 ˜ 230 - n ), wherein V GH  is a predetermined gate driver turn-on voltage (e.g., +15v) and V GOFF  is a predetermined gate driver turn-off voltage (e.g., −8v). Each level shifter ( 230 - 1 ˜ 230 - n ) changes the voltage level of a corresponding decoded gate line control signal (GD[ 1 ]˜GD[n]) from V DD  to V GH  or from V SS  to V GOFF . The buffers ( 240 ) comprise a plurality of buffers (drivers) ( 240 - 1 ˜ 240 - n )) that are connected to the output of corresponding level shifters ( 230 - 1 ˜ 230 - n ), for driving corresponding gate lines (GL 1 ˜GLn) via corresponding gate driver output signals (G 1 ˜Gn). Details regarding operation of a level shifter circuit and buffer are described below with reference to  FIG. 3 .  
         [0012]      FIG. 3  is a circuit diagram illustrating a conventional level shifter circuit and output buffer, which can be implemented in the gate driver circuit of  FIG. 2 . For purposes of illustration,  FIG. 3  depicts circuit architectures of a voltage level shifter ( 230 - i ) and corresponding buffer (driver) ( 240 - i ), which can be implemented for each of the level shifters ( 230 - 1 ˜ 230 - n ) and buffers ( 240 - 1 ˜ 240 - n ) shown in  FIG. 2 . The level shifter ( 230 - i ) comprises a plurality of NMOS transistors (NT 1 ˜NT 6 ) and a plurality of PMOS transistors (PT 1 -PT 6 ) operatively connected as shown. The level shifter ( 230 - i ) receives as input the decoded gate line control signal GD[i] output from a corresponding line decoder ( 220 - i ). In the illustrative embodiment, the decoded gate line control signal GD[i] comprises GD[i] (which is V DD  or V SS ) and its complement GDB[i]. The level shifter ( 230 - i ) also receives as input DC voltages V GH  and V GOFF . The buffer ( 240 - i ) comprises two inverters, a first inverter comprising PMOS transistor (PT 7 ) and NMOS transistor (NT 7 ), and a second inverter comprising PMOS transistor (PT 8 ) and NMOS transistor (NT 8 ).  
         [0013]      FIG. 4  is a waveform diagram illustrating operation of the circuit of  FIG. 3 . More specifically,  FIG. 4  illustrates the gate driver voltage (Gi) that is output to gate line (GLi) based on the logic level of the decoded gate line control signal (GD[i]/GDB[i]). As shown in  FIG. 4 , when the logic level of GD[i]=V DD  and the logic level of GDB[i]=V SS , the gate line voltage GLi=V GH  (e.g., +15v) to activate (turn-on) the gate line. When the logic level of GD[i]=V SS  and the logic level of GDB[i]=V DD , the gate line voltage GLi=V GOFF  (e.g., −8v) to deactivate (turn-off) the gate line.  
         [0014]     Although the operation of the level shifter and buffer circuit of  FIG. 3  is known and readily understood by those of ordinary skill in the art, a brief description will be provided. Assume GD[i]=V DD  and GDB[i]=V SS . A logic “1” is applied to the gate of NT 1  and a logic “0” is applied to the gate of NT 2 . As such, NT 1  is turned on and NT 2  is turned off, causing node N 1  to be pulled down to logic “0” and node N 2  is floating. With node N 1  at logic “0”, PMOS transistors PT 2 , PT 3  and PT 5  will be turned on, which causes V GH  to be applied to the gates of transistors NT 3  and NT 6  to turn on such transistors.  
         [0015]     When designing display panel systems (such as shown in  FIG. 1 ), it is highly desirable to provide architectures that reduce the size of such systems, especially when such systems are implemented for small, handheld portable devices (e.g., PDAs, etc.). One way in which the size of such display systems can be reduced is by reducing the size of the IC chips that are used to drive the display panel. The architecture of the conventional gate driver circuit as described above ( FIGS. 2 and 3 ) is disadvantageous in this regard because the level-shifter circuits ( 230 ) occupy a significant amount of space, which results in an increase of the chip size of the gate driver IC. Indeed, as shown in  FIG. 2 , the conventional gate driver circuit comprises n voltage level shifters ( 230 - 1 ˜ 230 - n ), and as shown in  FIG. 3 , each voltage level shifter ( 230 - 1 ˜ 230 - n ) comprises 12 high-voltage transistors—six (6) PMOS and six (6) NMOS transistors, each of which are constructed to be significantly large due to the wide voltage range (e.g., V GH =+15v and V GOFF =−8V). As the range of level shifting becomes wider, the size of such transistors must be increased for proper operation. In the conventional architecture described above, the level shifter circuits ( 230 - 1 ˜ 230 - n ) occupy approximately 50% of the total chip size of the gate driver IC.  
       SUMMARY OF THE INVENTION  
       [0016]     Exemplary embodiments of the present invention include circuits and methods for driving flat panel displays (e.g., a liquid crystal display (LCD)) and, in particular, to gate driver circuits and methods for driving gates lines of a display panel. Exemplary gate driver circuit architectures according to the present invention provide compact designs that enable smaller chip sizes for gate driver ICs.  
         [0017]     In one exemplary embodiment of the present invention, a semiconductor integrated gate driver circuit for driving gate lines of a display is provided. The gate driver IC comprises a plurality of gate driver circuits, wherein each gate driver circuit drives a corresponding gate line of the display, and a level shifter circuit, for generating a precharge control signal for the gate driver circuits. Each gate driver circuit comprises a line decoder for decoding a gate line control signal and generating a decoded gate line control signal and a precharge circuit for precharging a gate driver turn-on voltage in response to the precharge control signal before activating the gate line. During a driving phase, the precharged gate driver turn-on voltage is discharged when the gate line is activated in response to the decoded gate line control signal, whereas the precharged gate driver turn-on voltage is maintained when the gate line is not activated in response to the decoded gate line control signal.  
         [0018]     In another exemplary embodiment of the invention, each precharge circuit comprises four transistors and two capacitors, wherein a first capacitor stores the precharged gate driver turn-on voltage and wherein a second capacitor stores a precharged gate driver turn-off voltage.  
         [0019]     In another exemplary embodiment of the invention, each precharge circuit comprises four transistors and two latch circuits, wherein a first latch circuit stores the precharged gate driver turn-on voltage and wherein a second latch circuit stores a precharged gate driver turn-off voltage.  
         [0020]     Advantageously, gate driver circuits according to exemplary embodiments of the invention utilize precharging circuits in lieu of the level shifter circuits used in the conventional gate driver circuit, such as described above with reference to  FIGS. 2 and 3 , which enable more compact gate driver designs resulting in smaller IC driver chips.  
         [0021]     These and other exemplary embodiments, aspects, features and advantages of the present invention will be described and become apparent from the following detailed description of exemplary embodiments, which is to be read in connection with the accompanying drawings.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0022]      FIG. 1  is a schematic diagram that illustrates a conventional display system.  
         [0023]      FIG. 2  is a schematic diagram that illustrates a conventional gate driver circuit.  
         [0024]      FIG. 3  is a circuit diagram that illustrates a conventional voltage level shifting and buffer circuit, which is implemented in the conventional gate driver circuit of  FIG. 2 .  
         [0025]      FIG. 4  is a waveform diagram illustrating the operation of the circuit of  FIG. 3 .  
         [0026]      FIG. 5  is a schematic diagram that illustrates a gate driver circuit according to an exemplary embodiment of the present invention.  
         [0027]      FIG. 6  is a circuit diagram that illustrates a voltage level shifter circuit for generating precharge control signals, according to an exemplary embodiment of the present invention.  
         [0028]      FIG. 7  is a circuit diagram that illustrates a precharge circuit and buffer circuit according to an exemplary embodiment of the present invention, which can be implemented in the gate driver circuit of  FIG. 5 .  
         [0029]      FIG. 8  is an exemplary timing diagram that illustrates a mode of operation of the circuit of  FIG. 7 .  
         [0030]      FIG. 9  is a circuit diagram that illustrates a precharge circuit and buffer circuit according to another exemplary embodiment of the present invention, which can be implemented in the gate driver circuit of  FIG. 5 .  
     
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS  
       [0031]      FIG. 5  is a block diagram that schematically illustrates a gate driver circuit ( 300 ) according to an exemplary embodiment of the invention. In one exemplary embodiment, the gate driver circuit ( 300 ) can be implemented in the system ( 100 ) of  FIG. 1  for driving a flat panel display such as an LCD. In general, as depicted in  FIG. 5 , the gate driver ( 300 ) comprises a level shifter ( 320 ), a line decoder ( 322 ), precharge circuits ( 310 ) and buffers (drivers) ( 330 ). As explained below, the architecture of the gate driver circuit ( 300 ) provides a compact design (as compared to the conventional gate driver of  FIG. 2 , for example) such that the gate driver ( 300 ) can be implemented on a smaller gate driver IC chip.  
         [0032]     The level shifter ( 320 ) receives as input DC voltages of V GH  (a predetermined gate driver turn-on voltage of e.g., +15v) and V GOFF  (a predetermined gate driver turn-off voltage of e.g., −8v), as well as a precharge control signal (PREC) of logic level V DD  or V SS . The level shifter ( 320 ) outputs a level-shifted precharge control signal (PRECH/PRECHB), where PRECH=V GH  and PRECHB=V GOFF , or where PRECH=V GOFF  and PRECHB=V GH , depending on the logic level of the input precharge control signal (PREC). The level-shifted precharge control signal (PRECH/PRECHB) is commonly input to each of a plurality of precharge circuits ( 310 - 1 ˜ 310 - n ) (or generally,  310 - i ). An exemplary embodiment of the level shifter circuit ( 320 ) and method of operation thereof, will be explained below with reference to the exemplary embodiment depicted in  FIG. 6 .  
         [0033]     The line decoder ( 322 ) decodes a gate line control signal G[m: 0 ] and generates a plurality of decoded gate line control signals (GDB[ 1 ]˜GDB[n]) (or generally, GDB[i]), which are output to corresponding precharge circuits ( 310 - 1 ˜ 310 - n ). In one exemplary embodiment, the line decoder ( 322 ) comprises a plurality of separate line decoders each associated with a corresponding one of the gate lines (GL 1 ˜GLn) (or generally, GLi), such as shown in  FIG. 2 . Each decoded gate line control signal (GDB[i]) will have a logic level of V DD  (logic power supply voltage) or V SS  (logic ground voltage), depending on which gate line (GL 1 ˜GLn) is to be selected as indicated by the gate line control signal G[m: 0 ].  
         [0034]     Each precharge circuit ( 310 - 1 ˜ 310 - n ) receives as input the level-shifted precharge control signal (PRECH/PRECHB) and a corresponding decoded gate line control signal GDB[i] during precharging and driving phases of operation of the gate driver ( 300 ). The buffers ( 330 ) include a plurality of buffers (drivers) ( 330 - 1 ˜ 330 - n ) (or generally,  330 - i ), each of which being connected to the output of a corresponding one of the precharge circuits ( 310 - 1 ˜ 310 - n ), for driving corresponding gate lines (GL 1 ˜GLn) using a respective gate driver output signal (G 1 ˜Gn) (or generally, Gi), based on the output of the precharge circuits ( 310 - 1 ˜ 310 - n ).  
         [0035]     In general, during a precharging phase, each precharge circuit ( 310 - 1 ˜ 310 - n ) operates by precharging a gate driver turn-on voltage (V GH ) in response to the precharge control signal (PRECH/PRECHB) before a corresponding gate line (GLi) is activated. The precharged turn-on voltage (V GH ) that is generated by each precharge circuit ( 310 - 1 ˜ 310 - n ) during the precharge phase is output to corresponding buffers ( 320 - 1 ˜ 320 - n ), which generate gate driver output signals (G 1 ˜Gn) having a voltage level of V GOFF . Accordingly, a precharging phase results in all gate lines (GL 1 ˜GLn) being initialized to V GOFF .  
         [0036]     Subsequently, during a driving phase, if a gate line (GLi) is selected in response to a corresponding decoded gate line control signal (GDB[i]), the corresponding precharge circuit ( 310 - i ) operates to discharge the precharged gate driver turn-on voltage (V GH ), which results in the corresponding buffer ( 320 - i ) driving the gate line (GLi) with a gate driver output signal Gi=V GH  On the other hand, if the gate line (GLi) is not selected in response to the corresponding decoded gate line control signal (GDB[i]), the corresponding precharge circuit ( 310 - i ) operates to maintain the precharged gate driver turn-on voltage (V GH ), which results in the corresponding buffer ( 320 - i ) driving the gate line (GLi) with a gate driver output signal Gi=V GOFF  (i.e., the initialization voltage V GOFF  is maintained on the gate line (GLi)). Details regarding operation of the precharge circuits ( 310 ) and buffers ( 330 ) will be explained below with reference to the exemplary embodiments  7 ,  8  and  9 , for example.  
         [0037]      FIG. 6  is a circuit diagram illustrating a level shifter circuit for generating a level-shifted precharge control signal (PRECH/PRECHB) according to an exemplary embodiment of the invention. In particular,  FIG. 6  depicts one exemplary embodiment of the level shifter ( 320 ) shown in  FIG. 5 . The level shifter ( 320 ) comprises a level shifter ( 324 ) and a buffer (driver) ( 325 ). The level shifter ( 324 ) is similar in circuit architecture and operation of the level shifter ( 230 - i ) depicted in  FIG. 3 . However, the level shifter ( 324 ) receives as input the precharge control signal (PREC/PRECB), where PREC and PRECB are at complementary logic levels (V DD , V SS ), and then level-shifts the precharge control signal to generate either V GH  or V GOFF  at Node N 3 , depending on the logic levels of PREC and PRECB. The voltage of Node N 3  is input to the buffer ( 325 ), which outputs a level-shifted precharge control signal (PRECH/PRECHB). The buffer ( 325 ) comprises two inverters and is similar in circuit architecture and function of the buffer ( 240 - i ) shown in  FIG. 3 . However, in the buffer ( 325 ) of  FIG. 6 , an output terminal is connected to node N 4  (i.e., the output of the first inverter formed by transistors PT 7  and NT 7 ) for outputting the complementary precharge control signal (PRECHB).  
         [0038]     In general, the level shifter ( 320 ) operates as follows. When the logic level of the precharge control signal (PREC) is V DD  and the logic level of the complementary precharge control signal (PRECB) is V SS , the level-shifted precharge control signal (PRECH) and complementary precharge control signal (PRECHB) are at logic levels V GH  (e.g., +15v) and V GOFF  (e.g., −8 v), respectively. On the other hand, when the logic level of the precharge control signal (PREC) is V SS  and the logic level of the complementary precharge control signal (PRECB) is V DD , the level-shifted precharge control signal (PRECH) and complementary precharge control signal (PRECHB) are at logic levels V GOFF  and V GH , respectively. The operation of the level shifter ( 320 ) of  FIG. 6  is similar to that of the circuit shown in  FIG. 3  and a detailed discussion thereof will not be repeated.  
         [0039]      FIG. 7  is a circuit diagram illustrating a precharge circuit ( 310 - i ) and output buffer ( 330 - i ) according to an exemplary embodiment of the invention. In particular,  FIG. 7  illustrates one exemplary circuit architecture according to the invention, which can be implemented for each of the precharge circuits ( 310 - 1 ˜ 310 - n ) and corresponding buffers ( 330 - 1 ˜ 330 - n ) shown in  FIG. 5 . The precharge circuit ( 310 - i ) comprises four transistors ( 312 ,  314 ,  316 , and  318 ), two storage devices ( 313  and  319 ) and an output Node B. In the exemplary embodiment, the storage devices ( 313  and  319 ) comprise capacitors (C 1  and C 2 ). The buffer ( 330 - i ) comprises an inverter comprised of PMOS transistor MP 3  and NMOS transistor MN 3 . The output Node B of the precharge circuit ( 310 - i ) is connected to the input of the buffer ( 330 - i ) The precharge circuit ( 310 - i ) and buffer ( 330 - i ) generally operate as follows. The precharge circuit ( 310 - i ) receives as input the level-shifted precharge control signal (PRECH) and complementary precharge control signal (PRECHB) at the gate terminals of NMOS transistor ( 314 ) and PMOS transistor ( 312 ), respectively. As noted above, the level-shifted precharge control signal (PRECH/PRECHB) is commonly applied to all precharge circuits ( 310 - 1 ˜ 310 - n ). The precharge circuit ( 310 - i ) also receives as input a corresponding decoded gate line control signal GDB[i] from the line decoder ( 322 ) ( FIG. 5 ), which is input to the gate terminal of PMOS transistor ( 318 ).  
         [0040]     During a precharging phase, the precharge circuit ( 310 - i ) charges Node B to V GH  in response to the precharge control signal (PRECH/PRECHB), which results in the gate line (GLi) being initialized to V GOFF . In particular, since the output Node B is precharged to logic level V GH , the logic level at Node C is V GOFF , and the gate driver output signal Gi=V GOFF  to initialize the gate line (GLi) to V GOFF . As noted above, the precharging phase results in all gate lines (GL 1 ˜GLn) being initialized to V GOFF .  
         [0041]     Subsequently, during a driving phase, if the gate line (GLi) is selected in response to the decoded gate line control signal (GDB[i]) input to the gate of transistor ( 318 ), the precharge circuit ( 310 - i ) operates to discharge the precharged gate driver turn-on voltage V GH  at Node B to V GOFF , which causes the voltage at Node C to become V GH . As a result, the gate line (GLi) is driven with a gate driver output signal Gi=V GH . On the other hand, if the gate line (GLi) is not selected in response to the decoded gate line control signal (GDB[i]), the precharge circuit ( 310 - i ) operates to maintain the precharged gate driver turn-on voltage V GH  at Node B, which results in maintaining the voltage level V GOFF  at Node C. As a result, the gate driver output signal Gi=V GOFF  is applied to the gate line (GLi) (i.e., the initialization voltage V GOFF  is maintained on the gate line (GLi)).  
         [0042]     A more detailed description of an exemplary method of operation of the precharge circuit ( 310 - i ) and buffer ( 330 - i ) will now be provided with reference to the circuit diagrams of  FIGS. 5 and 7  and the timing diagram illustrated in  FIG. 8 . In the timing diagram of  FIG. 8 , it is assumed that the gate lines (GL 1 ˜GLn) are sequentially activated starting with gate line GL 1 . In  FIG. 8 , time periods T1 denote precharging phases and time periods T2 denote driving phases. A precharging phase is performed to initialize the gate lines (GL 1 ˜GLn) to V GOFF , prior to a driving phase in which a selected gate line (GLi) is activated.  
         [0043]     A precharging phase is commenced by inputting a precharge control signal of PREC=V DD  and PRECB=V SS  to the level shifter ( 320 ). In response, as described above, the level shifter ( 320 ) outputs a level-shifted precharge control signal of PRECH=V GH  and PRECHB=V GOFF , which is commonly input to each of the precharge circuits ( 310 - 1 ˜ 310 - n ). Moreover, during precharge, all decoded gate line control signals (GDB[ 1 ]˜GDB[n]) are set at logic level V DD .  
         [0044]     Referring to  FIG. 7 , during a precharge phase, the precharge control signal PRECHB=V GOFF  is input to the gate of PMOS transistor ( 312 ), the precharge control signal PRECH=V GH  is input to the gate of NMOS transistor ( 314 ) and the decoded gate line control signal GDB[i]=V DD  is input to the gate terminal of PMOS transistor ( 318 ). As a result, PMOS transistor ( 312 ) and NMOS transistor ( 314 ) are both turned ON and the PMOS transistor ( 318 ) and NMOS transistor ( 316 ) are both turned OFF. Consequently, the voltage at Node B is precharged to V GH  and the voltage at Node A is precharged to V GOFF . Since Node B is precharged to V GH , transistor MN 3  is turned ON and transistor MP 3  is turned OFF, which results in Node C being pulled-down to V GOFF . Therefore, a gate driver signal Gi=V GOFF  is applied to the gate line (GLi). As noted above, during precharge, all precharge circuits generate a precharge voltage of V GH  at Node B so that all gate lines (GL 1 ˜GLn) are initialized to V GOFF .  
         [0045]     After a precharging phase, a driving phase (T2) is commenced in which a gate line (GLi) is activated. In the exemplary embodiment of  FIG. 8 , it is assumed that gate line GL 1  is initially selected. As shown in  FIG. 8 , a driving phase is commenced by inputting a precharge control signal of PREC=V SS  and PRECB=V DD  to the level shifter ( 320 ). In response, as described above, the level shifter ( 320 ) outputs a level-shifted precharge control signal of PRECH=V GOFF  and PRECHB=V GH , which is commonly input to each of the precharge circuits ( 310 - 1 ˜ 310 - n ). Moreover, during a driving phase for gate line GL 1 , the decoded gate line control signal (GDB[ 1 ]) is set to logic level V SS , while the decoded gate line control signals (GDB[ 2 ]˜GDB[n]) for the other gate lines are maintained at logic level V DD . As a result, a gate driver output signal of G 1 =V GH  is applied to gate line GL 1 .  
         [0046]     More specifically, referring to  FIG. 7 , assume that the precharge circuit ( 310 - i ) and buffer ( 330 - i ) are the precharge circuit ( 310 - 1 ) and buffer ( 330 - 1 ) for gate line GL 1 . During a driving phase for gate line GL 1 , the precharge control signal PRECHB=V GH  is input to the gate of PMOS transistor ( 312 ), the precharge control signal PRECH=V GOFF  is input to the gate of NMOS transistor ( 314 ) and the decoded gate line control signal GDB[ 1 ]=V SS  is input to the gate terminal of PMOS transistor ( 318 ). As a result, PMOS transistor ( 312 ) and NMOS transistor ( 314 ) are both turned OFF and the PMOS transistor ( 318 ) is turned ON, which causes Node A to be charged from V GOFF  to V DD . With Node A charged to V DD , NMOS transistor ( 316 ) is turned ON, which causes Node B to be discharged (pulled-down) to V GOFF . Further, since Node B is discharged to V GOFF , transistor MN 3  is turned OFF and transistor MP 3  is turned ON, which results in Node C being pulled-up to V GH . Therefore, a gate driver signal G 1 =V GH  is applied on gate line GL 1  to drive the gate line.  
         [0047]     Furthermore, during the driving phase of gate line GL 1 , although the level-shifted precharge control signals PRECHB=V GH  and PRECH=V GOFF  are applied to the precharge circuits ( 310 - 2 ˜ 3   10 - n ) of gate lines (GL 2 ˜GLn), the decoded gate line control signals (GDB[ 2 ]˜GDB[n]) are maintained at logic level V DD , which causes the gate driver output signals (G 2 ˜Gn) to remain at V GOFF .  
         [0048]     More specifically, referring to  FIG. 7 , assume by way of example that the precharge circuit ( 310 - i ) and buffer ( 330 - i ) are the precharge circuit ( 310 - 2 ) and buffer ( 330 - 2 ) for gate line GL 2 . During the driving phase for gate line GL 1  (as described above), the precharge control signal PRECHB=V GH  is input to the gate of PMOS transistor ( 312 ), the precharge control signal PRECH=V GOFF  is input to the gate of NMOS transistor ( 314 ) and the decoded gate line control signal GDB[ 2 ]=V DD  is input to the gate terminal of PMOS transistor ( 318 ). As a result, PMOS transistor ( 312 ) and NMOS transistor ( 314 ) are both turned OFF and the PMOS transistor ( 318 ) is turned OFF. Since PMOS transistor ( 318 ) is OFF, the voltage at Node A is maintained at the precharged voltage V GOFF  by the storage device ( 319 ). Since Node A is at V GOFF , the NMOS transistor ( 316 ) is turned OFF, which causes Node B to be maintained at the precharged voltage V GH  by the storage device ( 313 ). Further, since Node B is at V GH , the gate driver output signal G 2  on gate line GL 2  is maintained at V GOFF .  
         [0049]     After each driving phase (T2) for a given gate line (GLi), a precharge phase (T1) is performed to initialize all gate lines to V GOFF . For example, referring to  FIG. 8 , after the driving phase for gate line GL 1 , another precharge phase is performed, wherein GDB[ 1 ] is transitioned to logic level V DD . In addition, the precharge control signal PREC=V DD  is input to the level shifter ( 320 ) to generate a level-shifted precharge control signal of PRECH=V GH  and PRECHB=V GOFF , which is commonly input to all precharge circuits ( 310 - 1 ˜ 310 - n ) to generate the precharged voltage V GH  at Node B, and initialize the gate lines (GL 1 ˜GLn) to V GOFF , in the same manner as discussed above. As depicted in  FIG. 8 , a driving phase for gate line GL 2  is commenced by transitioning GDB[ 2 ] to logic level V SS  and generating a level-shifted precharge control signal of PRECH=V GOFF  and PRECHB=V GH . The precharging and driving phase are sequentially repeated as discussed above to sequentially activate the gate lines (GL 1 ˜GLn).  
         [0050]     It is to be appreciated that the architecture of the gate driver circuit of  FIG. 5  provides various advantages over the architecture of the conventional gate driver circuit of  FIG. 2 . For instance, the implementation of a single level shifter circuit ( 320 ) and the precharge circuits ( 310 - 1 ˜ 310 - n ) in the exemplary gate driver architecture of  FIG. 5  provides about a 50% reduction in the size of the gate driver IC chip as compared to the conventional gate driver circuit of  FIG. 2 . Indeed, the conventional gate driver circuit of  FIG. 2  comprises a plurality of level shifters ( 230 - 1 ˜ 230 - n ), each of which consisting of  12  transistors (as shown in  FIG. 3 ). In contrast, in the exemplary embodiment of  FIG. 7 , each precharge circuit ( 310 - 1 ˜ 310 - n ) includes only 4 transistors and two capacitors. Accordingly, the precharge circuits ( 310 ) in  FIG. 5  occupy a significantly less amount of silicon area as compared to the level shifter circuits ( 230 ) in  FIG. 2 , thereby resulting in a smaller IC gate driver chip.  
         [0051]      FIG. 9  is a circuit diagram illustrating a precharge circuit and output buffer according to another exemplary embodiment of the invention. The circuit ( 500 ) comprises a precharge circuit ( 310 - i ′) and buffer ( 330 - i ). The circuit ( 500 ) is similar in function and architecture as that of the circuit ( 400 ) of  FIG. 7 . However, the precharge circuit ( 310 - i ′) in  FIG. 9  comprises latch circuits ( 313   a  and  319   a ) as storage devices, as compared to the precharge circuit ( 310 - i ) of  FIG. 7  in which the storage devices ( 313  and  319 ) are capacitors (C 1  and C 2 ).  
         [0052]     The circuit ( 500 ) of  FIG. 9  operates in a similar manner as the circuit ( 400 ) of  FIG. 7 . In particular, during a precharging phase, the precharge control signal PRECHB=V GOFF  is input to the gate of PMOS transistor ( 312 ), the precharge control signal PRECH=V GH  is input to the gate of NMOS transistor ( 314 ) and the decoded gate line control signal GDB[i]=V DD  is input to the gate terminal of PMOS transistor ( 318 ). As a result, PMOS transistor ( 312 ) and NMOS transistor ( 314 ) are both turned ON and the PMOS transistor ( 318 ) and NMOS transistor ( 316 ) are both turned OFF. Consequently, since PMOS transistor ( 312 ) is ON, the voltage at Node B is brought to V GH , and the output of the inverter (INV 1 ) of the latch circuit ( 313   a ) is V GOFF , which causes PMOS transistor MP 4  to turn ON and maintain the voltage of V GH  at Node B. Further, since NMOS transistor ( 314 ) is ON, the voltage at Node A is brought to V GOFF , and the output of the inverter (INV 2 ) of the latch circuit ( 319   a ) is V DD , which causes NMOS transistor MN 4  to turn ON and maintain the voltage of V GOFF  at Node A. Further, since Node B is precharged to V GH , the transistor MN 3  is turned ON and MP 3  is turned OFF, which results in a gate driver signal Gi=V GOFF  being output to gate line GLi.  
         [0053]     During a driving phase, assume GDB[i] is set to V SS  for selecting the gate line GLi. The precharge control signal PRECHB=V GH  is input to the gate of PMOS transistor ( 312 ), the precharge control signal PRECH=V GOFF  is input to the gate of NMOS transistor ( 314 ) and the decoded gate line control signal GDB[i]=V SS  is input to the gate terminal of PMOS transistor ( 318 ). As a result, PMOS transistor ( 312 ) and NMOS transistor ( 314 ) are both turned OFF and the PMOS transistor ( 318 ) is turned ON, which causes Node A to be charged from V GOFF  to V DD . With Node A charged to V DD , the output of the inverter (INV 2 ) of the latch ( 319   a ) is V GOFF , which causes MN 4  to turn OFF and, therefore, Node A is maintained at V DD . With Node A maintained at V DD , the NMOS transistor ( 316 ) is turned ON, which causes Node B to be discharged (pulled-down) to V GOFF . Further, since Node B is discharged to V GOFF , the transistor MN 3  is turned OFF and MP 3  is turned ON, which results in a gate driver signal Gi=V GH  being output on gate line GLi.  
         [0054]     Furthermore, during a driving phase, assume that GDB[i] is maintained at logic level V DD  (another gate line is being driven). The precharge control signal PRECHB=V GH  is input to the gate of PMOS transistor ( 312 ), the precharge control signal PRECH=V GOFF  is input to the gate of NMOS transistor ( 314 ) and the decoded gate line control signal GDB[i]=V DD  is input to the gate terminal of PMOS transistor ( 318 ). As a result, PMOS transistor ( 312 ) and NMOS transistor ( 314 ) are both turned OFF and the PMOS transistor ( 318 ) is turned OFF. Since Node A is precharged to V DD , the transistor MN 4  of the latch circuit ( 319   a ) is ON, which causes Node A to be maintained at the precharged voltage V GOFF . Since Node A is at V GOFF , the NMOS transistor ( 316 ) is turned OFF, which causes Node B to be maintained at the precharged voltage V GH  by the storage device ( 313   a ). Indeed, the transistor MP 4  of the latch circuit ( 313   a ) stays ON, which causes Node B to be maintained at V GH . Since Node B is at V GH , the gate driver output signal (Gi) on gate line GLi is maintained at V GOFF .  
         [0055]     It is to be appreciated that the exemplary circuit architecture of the precharge circuit ( 310 - i ′) in  FIG. 9  occupies less silicon area as compared to the level shifter circuit ( 230 - i ) of  FIG. 3 . Accordingly, the use of the precharge circuit architecture in  FIG. 9  for the precharge circuits ( 310 ) in  FIG. 5 , as compared to the use of the level shifter circuit ( 230 - i ) in  FIG. 3 , would result in a smaller IC gate driver chip.  
         [0056]     Although illustrative embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to the precise system and method embodiments described herein, and that various other changes and modifications may be affected therein by one skilled in the art without departing form the scope or spirit of the invention. All such changes and modifications are intended to be included within the scope of the invention as defined by the appended claims.