Abstract:
A circuit with bi-directional signal transmission, including a first signal source, for generating a first signal comprising one bit per clock cycle during a first plurality of clock cycles, a second signal source, for generating a second signal including one bit per clock cycle during a second plurality of clock cycles, a first buffer, coupled with the first signal source, that outputs the first signal when the first buffer is enabled, a second buffer, coupled with the second signal source, that outputs the second signal when the second buffer is enabled, and a plurality of logical gates, coupled with the first signal source, the second signal source, the first buffer and the second buffer, that control enablement of the first buffer and the second buffer, such that (i) at any given clock cycle at least one of the first buffer and the second buffer is disabled, and (ii) when the first buffer and said the buffer are both disabled, subsequent generation of a ‘0’ bit in the first signal or the second signal causes enablement of the first buffer or the second buffer, respectively.

Description:
CROSS REFERENCES TO RELATED APPLICATIONS 
       [0001]    This application is a continuation-in-part of assignee&#39;s pending application U.S. Ser. No. 12/008,501, now U.S. Pat. No. 7,574,549, filed on Jan. 11, 2008, entitled BRIDGE DESIGN FOR SD AND MMC DATA BUSES. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The field of the present invention is bi-directional electrical data signal lines. 
       BACKGROUND OF THE INVENTION 
       [0003]    The SD card and multi-media card (MMC) standards use bi-directional bus lines. Specifically, the four data lines D 0 -D 3  and the CMD lines are bi-directional, and the CLK line for a clock is uni-directional. 
         [0004]    Conventionally, signal direction cannot be resolved by monitoring a simple condition. Instead, signal direction is determined by content of bus transactions; i.e., content of messages transferred over a bus. 
         [0005]    The SD card and MMC standards also define voltage levels for signals. An SD card, for example, should operate in the 2.7V-3.6V range. 
         [0006]    Some advanced silicon processes do not support voltages higher than 1.8V. For such processes, support of SD and MMC requires use of external level shifters, which boost voltages at a terminal. For a bi-directional bus connecting terminals A and B, a level shifter drives terminal A to 3V when terminal B is at 1.8V, for enabling a data signal to travel from A to B. Similarly, a level shifter drives terminal B to 3V when terminal A is at 1.8V, for enabling a data signal to travel from B to A. Thus level shifters require knowledge of signal direction in order to operate properly. 
         [0007]    Conventional implementations of level shifting include an additional pin for each bus signal, to determine signal direction. Such an implementation is present in the Level Translator, Model SN74AVCA406 SMC/xD, manufactured and distributed by Texas Instruments, Inc. of Dallas, Tex. Integrated circuits that interface with such level shifters must support directional signals, in addition to the standard SD and MMC signals. 
         [0008]    Support of directional signals causes large overhead and cost, for both the level shifter and the integrated circuit that interfaces with it. This is one of the drawbacks of bi-directional data buses. 
         [0009]    Devices that require bridges between SD devices, such as a bridge between an SD host and an SD slave, also encounter the problem of determining signal direction. Moreover, often the SD signals being bridged do not have directional signals associated therewith, and thus their direction is unknown. 
         [0010]    It would thus be of advantage to have circuitry and logic for determining signal direction in a bi-directional SD or MMC bus, without requiring external direction signals and without requiring decoding of exact content of bus transactions. 
       SUMMARY OF THE DESCRIPTION 
       [0011]    Aspects of the present invention relate to circuitry for bi-directional SD and MMC buses, which overcomes drawbacks of conventional circuitry by determining bus direction without use of external directions signals, and without decoding exact content of bus transactions. Further aspects of the present invention relate to a SIM interface, to monitor bus direction between a SIM card and a controller. 
         [0012]    In one embodiment, the present invention employs two data buffers, a first buffer that drives signals in a data bus in a direction from a terminal A to a terminal B, and a second buffer that drives signals in the opposite direction. The buffers may be in an enabled or disabled state. When a buffer is enabled, it drives the signal direction. 
         [0013]    Special logic is introduced to determine when to enable and disable each of the buffers, based on logical processing of sampled bits at terminals A and B. 
         [0014]    There is thus provided in accordance with an embodiment of the present invention a circuit with bi-directional signal transmission, including a first signal source, for generating a first signal comprising one bit per clock cycle during a first plurality of clock cycles, a second signal source, for generating a second signal including one bit per clock cycle during a second plurality of clock cycles, a first buffer, coupled with the first signal source, that outputs the first signal when the first buffer is enabled, a second buffer, coupled with the second signal source, that outputs the second signal when the second buffer is enabled, and a plurality of logical gates, coupled with the first signal source, the second signal source, the first buffer and the second buffer, that control enablement of the first buffer and the second buffer, such that (i) at any given clock cycle at least one of the first buffer and the second buffer is disabled, and (ii) when the first buffer and said the buffer are both disabled, subsequent generation of a ‘0’ bit in the first signal or the second signal causes enablement of the first buffer or the second buffer, respectively. 
         [0015]    There is additionally provided in accordance with an embodiment of the present invention a circuit with bi-directional signal transmission, including a first signal source, for generating a first signal including one bit per clock cycle during a first plurality of clock cycles, a second signal source, for generating a second signal including one bit per clock cycle during a second plurality of clock cycles, a first buffer, coupled with the first signal source, that outputs the first signal when the first buffer is enabled, a second buffer, coupled with the second signal source, that outputs the second signal when the second buffer is enabled, a plurality of logical gates, coupled with the first signal source, the second signal source, the first buffer and the second buffer, that control enablement of the first buffer and the second buffer, such that there is less than a one clock cycle delay in transmitting the first signal via the first buffer during the first plurality of clock cycles, and in transmitting the second signal via the second buffer during the second plurality of clock cycles. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]    The present invention will be more fully understood and appreciated from the following detailed description, taken in conjunction with the drawings in which: 
           [0017]      FIG. 1  is a simplified diagram of an electrical circuit that determines bus direction in bi-directional SD and MMC signal lines, in accordance with a first embodiment of the present invention; 
           [0018]      FIG. 2  is a simplified diagram of an electrical circuit that determines bus direction in bi-directional SD and MMC signal lines, in accordance with a second embodiment of the present invention; 
           [0019]      FIG. 3  is a simplified flowchart of a method for determining bus direction in bi-directional SD and MMC signal lines, in accordance with a first embodiment of the present invention; 
           [0020]      FIG. 4  is a simplified flowchart of a method for determining bus direction in bi-directional SD and MMC signal lines, in accordance with a second embodiment of the present invention; 
           [0021]      FIG. 5  is a sample simulation of the method of  FIG. 3 , in accordance with an embodiment of the present invention; and 
           [0022]      FIG. 6  is a simplified diagram of an electrical circuit that determines bus direction in multiplexed directional SD and MMC signal lines, in accordance with an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0023]    Aspects of the present invention relate to a bi-directional data bus that connects a terminal A with a terminal B. The data bus may be an SD or MMC bridge, wherein terminal A is generally connected to a host device and terminal B is connected to a slave device. Unlike conventional SD and MMC bridges, the bridges of the present invention are capable of determining signal direction without the need for external directional signals, and without the need for decoding exact content of messages being transmitted over the bridge. 
         [0024]    Reference is made to  FIG. 1 , which is a simplified diagram of an electrical circuit  100  that determines bus direction in bi-directional SD and MMC signal lines, in accordance with an embodiment of the present invention. Circuit  100  connects two terminals, A and B, and carries signals in both directions; i.e., from A to B, and from B to A. 
         [0025]    Generally, one terminal connects to an SD host and the other terminal connects to an SD slave. In such case, there are multiple bi-directional data lines D 0 -D 3  and CMD. The data lines D 0 -D 3  are synchronized so that they change their signal directions simultaneously. 
         [0026]    The voltages at terminals A and B may be the same, or may be different. To accommodate different voltages at the terminals, circuit  100  includes two level-shifter buffers,  110  and  115 , which drive signals from A to B and from B to A, respectively. Level shifting generates voltage drops across the buffers in order to drive the signal direction. Each buffer may enabled or disabled. When buffer  110  is enabled, signal data is transmitted from A to B, and when buffer  115  is enabled, signal data is transmitted from B to A. Buffers  110  and  115  are tri-state buffers, which hold their outputs at high impedance when disabled, and block transfer of signal data. Tri-state buffers thus have three outputs; namely, ‘0’, ‘1’ and ‘Z’. 
         [0027]    Circuit  100  also includes four data flip flop (DFF) modules; namely, module  120  designated DFF_A, module  125  designated DFF_B, module  130  designated DFF_EnAB, and module  135  designated DFF_EnBA. Each DFF module has an input value, an output value and a clock value. Each DFF module delays the input by one clock count; i.e., the DFF module captures the input signal at the moment of a rising clock edge, when the clock goes high, and subsequent input changes do not influence the output until the next rising clock edge. 
         [0028]    Modules  130  and  135  are used to enable buffers  110  and  115 , respectively. Specifically, when DFF_EnAB.out=0, buffer  110  is enabled, and when DFF_EnAB.out=1, buffer  110  is disabled. Similarly, when DFF_EnBA.out=0, buffer  115  is enabled, and when DFF_EnBA.out=1, buffer  115  is disabled. 
         [0029]    Circuit  100  also includes respective by-pass lines  140  and  145 , so that previous signal values A and B, denoted A_Delayed and B_Delayed, respectively, are accessible, together with current signal values A and B. 
         [0030]    Circuit  100  includes four logical processing units,  150 ,  155 ,  160  and  165 . Processing unit  150  is a NAND gate with inputs A and A_Delayed; processing unit  155  is a NAND gate with inputs B and B_Delayed; processing unit  160  is an AND gate with input !DFF_EnBA.out in addition to the output coming from processing unit  150  into processing unit  160 ; and processing unit  165  is an AND gate with input !DFF_EnAB.out in addition to the output coming from processing unit  155  into processing unit  165 . 
         [0031]    Circuit  100  includes two pull-up resistors,  170  and  175 , which pull the circuit bus up to logical 1 when both sides of the SD or MMC link are not driving signals. It is noted that there is a 2-clock delay for the SD host in circuit  100 , since the signal from A→B is delayed one clock count by DFF module  120 , and the signal from B→A is also delayed one clock count by DFF module  125 . 
         [0032]    Reference is made to  FIG. 2 , which is a simplified diagram of an alternative electrical circuit  200  that determines bus direction in bi-directional SD and MMC signal lines, in accordance with an embodiment of the present invention. It is noted that there is practically no delay for the SD host in circuit  200 . Specifically, DFF module  220  samples the state of the line at a rising edge of the clock SD_CLK, at which time the signal is stable regardless of whether it is driven by A or by B. The signal is delayed by another half clock at DFF module  230 , and presented to processing units  250  and  260  at the falling edge of the clock SD_CLK. As such, the signal presented to processing units  250  and  260  is synchronized with signal changes. 
         [0033]    Processing unit  250  is a NAND gate with inputs from side A and from the delayed signal from DFF module  230 . Processing unit  255  is a NAND gate with inputs from side B and from the delayed signal from DFF module  230 . Processing units  260  and  265  are AND gates that respectively control enablement and disablement of buffers  120  and  215 . 
         [0034]    The logic provides an enable to buffer  210  on side A or to buffer  215  on side B, but never to both. The side that presents a ‘0’ level signal first triggers the logic to open its buffer. If the side A logical level turns to ‘0’, then the logic enables the buffer from A         B. When the buffer from A         B is opened, the signal on side B also switches to ‘0’, but since the enable logic for A         B is already active, it blocks the logic for enabling buffer B         A. The logic remains active until two level ‘1’ bits are received. At that point, the logic blocks the A         B buffer, and the logic is then open to receive a ‘0’ state from either side. 
         [0035]    Circuit  200  is of advantage for implementations where host controllers cannot tolerate a delay in receiving an ACK acknowledgement from the slave. Specifically, in some embodiments, after sending a command, the host controller waits for an ACK acknowledgement from the slave. In other embodiments, the host controller waits no longer that a specified maximum tolerance time for the ACK. Circuit  200  ensures that there is no delay. In distinction, the two clock delay inherent with circuit  100  may be more than the host controller can tolerate. 
         [0036]    Reference is made to  FIG. 3 , which is a simplified flowchart of a method for determining bus direction in bi-directional SD and MMC signal lines, in accordance with a first embodiment of the present invention. 
         [0037]    The rationale for the logic illustrated in  FIG. 3  is based on three characteristics of SD and MMC buses; namely:
       1. The SD and MMC bus D 0 -D 3  and CMD lines have pull-up resistors  170  and  175  connected thereto, which pull the bus up to logical 1 when both sides of the SD or MMC link are not driving signals.   2. Each SD and MMC transaction on the D 0 -D 3  and CMD lines begins with a start bit of logical 0 and ends with a stop bit of logical 1.   3. Since the SD and MMC buses include direction transition, the side driving a signal stops driving a bus  2  clock cycles before the opposite side starts driving the bus.       
 
         [0041]    The logic of  FIG. 3  begins at step  305  where both buffers are set to their disabled states. At step  310  the A and B signal values are initialized to logical 0. Steps  315  and  320  are iterative steps that save previous A and B signal values and sample new values. 
         [0042]    As seen at steps  325 - 350 , when one side of circuit  100 , terminal A or terminal B, is sampled to have a logical 0 input, circuit  100  enables the buffer in the direction from that side to the opposite side, and locks the buffer in the enabled state. 
         [0043]    As seen at steps  355 - 375 , circuit  100  disables the enabled buffer when two consecutive logical 1 bits are detected. The event of detecting two consecutive logical 1 bits may represent an end of transaction, or may be part of a transaction. In the former case, both buffers are disabled, and circuit  100  is ready to detect a next transaction, and switch direction as required. In the latter case, the SD or MMC bus remains in its correct logical level due to the pull-up resistors. Since the previous bit was a logical 1, no delay in bus signal stabilization is incurred, due to device and bus capacitance. 
         [0044]    In order to avoid potential problems with transient conditions and synchronization to the SD_CLK signal, an embodiment of the present invention includes a sampling mechanism that delays transfer of bits from one direction to the other direction by a single clock, as indicated at steps  320 ,  335 ,  350 ,  370  and  375  of  FIG. 3 . Such delays are implemented by DFF modules  120 ,  125 ,  130  and  135  of  FIG. 1 , and do not affect proper operation of the SD or MMC bus, since transaction starts are determined by start bits, and not based on exact timing. Internally in a transaction, the delay is fixed and thus no change to transaction content occurs. 
         [0045]    The logic of  FIG. 3  applies to all bi-directional signals in an SD or MMC bus. However, since the D 0 -D 3  data lines change direction simultaneously, it is only necessary to apply the logic of  FIG. 3  to one of these data lines. The buffer enable/disable signals derived for the one data line suffices to control the buffers for the other three data lines. It is noted that even though the data lines may drive different signals, each data communication, from A to B or from B to A, starts with a ‘0’ bit and ends with two consecutive ‘1’ bits. 
         [0046]    Reference is made to  FIG. 4 , which is a simplified flowchart of a method for determining bus direction in bi-directional SD and MMC signal lines, in accordance with a second embodiment of the present invention. At step  405 , both buffers A         B and B         A are disabled. At step  410 , A, B LINE_DELAYED are initialized to zero. At step  415 , A and B are sampled during one clock cycle, which begins a processing loop. The processing loop has three primary branches; a first branch at steps  420 - 440 , which is entered when the A         B buffer is enabled, a second branch at steps  445 - 465 , which is entered when the B         A buffer is enabled, and a third branch at steps  470 - 485 , which is entered when both the A         B buffer and the B         A buffer are disabled. 
         [0047]    In the first branch the A         B buffer is enabled. If the current and previous signal values for A are logical ‘1’s, as determined at steps  425  and  430 , then the A         B buffer is disabled at step  435 . The value of LINE_DELAYED is set to the current A signal value at step  440 , and processing returns to step  415 . 
         [0048]    In the second branch the B         A buffer is enabled. If the current and previous signal values for B are logical ‘1’s, as determined at steps  450  and  455 , then the B         A buffer is disabled at step  460 . The value of LINE_DELAYED is set to the current B signal value at step  465 , and processing returns to step  415 . 
         [0049]    In the third branch the A         B buffer and the B         A buffer are both disabled. If the current A signal value is logical ‘0’, as determined at step  470 , then the A         B buffer is enabled at step  475  and processing returns to step  415 . Otherwise, if the current B signal value is ‘0’, as determined at step  480 , then the B         A buffer is enabled at step  485 , and processing returns to step  415 . If neither the current A signal nor the current B signal is logical ‘0’, then both buffers remain disabled. 
         [0050]    Reference is made to the Verilog pseudo-code presented hereinbelow, which summarizes one cycle of the logic for enabling and disabling buffers  110  and  115  in circuit  100  of  FIG. 1 . Logical processing units  150  and  160  are used to evaluate the Boolean expression !(A &amp; A_Delayed) &amp; !DFF_EnBA.out, and logical processing units  155  and  165  are used to evaluate the Boolean expression !(B &amp; B_Delayed) &amp; !DFF_EnAB.out. 
         [0000]    
       
         
               
               
             
           
               
                   
                   
               
             
             
               
                   
                 DFF_A.in = A 
               
               
                   
                 DFF_A.clk = SD_CLK 
               
               
                   
                 A_Delayed = DFF_A.out 
               
               
                   
                 DFF_B.in = B 
               
               
                   
                 DFF_B.clk = SD_CLK 
               
               
                   
                 B_Delayed = DFF_B.out 
               
               
                   
                 BufferAtoB.in = A_Delayed 
               
               
                   
                 B = BufferAtoB.out 
               
               
                   
                 BufferBtoA.in = B_Delayed 
               
               
                   
                 A = BufferBtoA.out 
               
               
                   
                 DFF_EnAB.in = ! (A &amp; A_Delayed) &amp; !DFF_EnBA.out 
               
               
                   
                 DFF_EnAB.clk = SD_CLK 
               
               
                   
                 BufferAtoB.enable = DFF_EnAB.out 
               
               
                   
                 DFF_EnBA.in = ! (B &amp; B_Delayed) &amp; !DFF_EnAB.out 
               
               
                   
                 DFF_EnBA.clk = SD_CLK 
               
               
                   
                 BufferBtoA.enable = DFF_EnBA.out 
               
               
                   
                   
               
             
          
         
       
     
         [0051]    Reference is made to the Verilog pseudo-code presented hereinbelow, which summarizes one cycle of the logic for enabling and disabling buffers  210  and  215  in circuit  200  of  FIG. 2 . Logical processing units  250  and  260  are used to evaluate the Boolean expression !(A &amp; DFF2_A.out) &amp; !Logic_EnBA, and logical processing units  255  and  265  are used to evaluate the Boolean expression !(B &amp; DFF2_A.out) &amp; !Logic_EnAB. 
         [0000]    
       
         
               
               
             
           
               
                   
                   
               
             
             
               
                   
                 DFF_A.in = A 
               
               
                   
                 DFF_A.clk = SD_CLK 
               
               
                   
                 DFF2_A.in = DFF_A.out 
               
               
                   
                 DFF2_A.clk = !SD_CLK 
               
               
                   
                 BufferAtoB.in = A 
               
               
                   
                 BufferBtoA.in = B 
               
               
                   
                 A = BufferBtoA.out 
               
               
                   
                 B = BufferAtoB.out 
               
               
                   
                 BufferAtoB.enable = ! (A &amp; DFF2_A.out) &amp; !Logic_EnBA 
               
               
                   
                 BufferBtoA.enable = ! (B &amp; DFF2_A.out) &amp; !Logic_EnAB 
               
               
                   
                   
               
             
          
         
       
     
         [0052]    Reference is made to  FIG. 5 , which is a sample simulation of the method of  FIG. 3  for A and B signals  0010101110111  and  0010111 , in accordance with an embodiment of the present invention. Each column in  FIG. 5  represents one clock cycle. As may be seen in  FIG. 5 , the signal direction goes from A to B, and Out A is a one clock delay of A, for bits  0010101  and for bits  01 . During the time Out A is used, the buffer from A to B is locked (represented by logical 1), and the buffer from B to A is unlocked (represented by logical 0). Signal direction goes from B to A, and Out B is a one clock delay of B, for bits  00101 . During the time Out B is used, the buffer from B to A is locked, and the buffer from A to B is unlocked. 
         [0053]    It will be appreciated by those skilled in the art that although detection of two logical 1 bits triggers circuit  100  to disable the enabled buffer, as indicated in  FIGS. 3-5 , detection of three or more logical 1 bits may be used instead to trigger the disabling. 
         [0054]    It will further be appreciated by those skilled in the art that circuit  100  may be used as a component of a more complex circuit that selectively connects terminal A with two terminals, B and C, or more than two terminals. To this end, reference is now made to  FIG. 6 , which is a simplified diagram of an electrical circuit  500  that determines bus direction in multiplexed directional SD and MMC signal lines, in accordance with an embodiment of the present invention. Generally, terminal A is connected to a host device, and terminals B and C are connected to slave devices. 
         [0055]    As shown in  FIG. 6 , circuit  500  includes two sub-circuits, each similar in operation to circuit  100 . The elements of one of the sub-circuits are labeled with numerals  510 - 575 , and the corresponding elements of the other sub-circuit are labeled with numerals  610 - 675 . Each of the sub-circuits is bi-directional, with one direction enabled and the other direction disabled, at any moment. 
         [0056]    Circuit  500  includes a B/C_SELECT signal line  600 , for selecting terminal B or terminal C. B/C_SELECT line  600  originates from a controller for the host device connected to terminal A. 
         [0057]    In distinction from logical processing unit  160  of circuit  100 , logical processing units  560  and  660  have four input lines. For each logical processing unit, two of its input lines carry signals from the sub-circuit in which the processing unit is located, one signal for examining two previous bits in the enabled direction and the other signal for examining a bit in the disabled direction. One of its input lines carries a signal from the other sub-circuit, for examining a bit in the disabled direction; and one of its input lines carries a signal from B/C_SELECT line  500 . Terminals A, B and C may have the same voltage levels, or different voltage levels. 
         [0058]    The sub-circuits of circuit  500  shown in  FIG. 6  correspond to the circuit  100  of  FIG. 1 . It will be appreciated by those skilled in the art that the alternative circuit  200  of  FIG. 2  may be used instead for the sub-circuits of circuit  700 , resulting in an alternate embodiment of circuitry for connecting terminal A with terminals B and C using bi-directional circuits. 
         [0059]    In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made to the specific exemplary embodiments without departing from the broader spirit and scope of the invention as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.