Abstract:
The present invention discloses a forward converter with secondary side post-regulation and zero voltage switching, where the primary side power loop may adopt a single or a dual transistor structure, driven by a primary side driving circuit with a constant duty ratio so that the voltage waveform across the secondary side power winding has a constant pulse width; the secondary side power loop uses a controllable switch, a magnetic amplifier (MA) or an N channel metal oxide semiconductor field transistor (NMOS), to blank the leading edge of the voltage waveform across the secondary side power winding, regulate the output voltage, and achieve zero voltage switching of primary side switch transistors.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention generally relates to a forward converter, and more particularly to a forward converter with secondary side post-regulation and zero voltage switching, achieving zero voltage switching of primary side switch transistors while post-regulating the output voltage at the secondary side. 
       DESCRIPTION OF THE RELATED ART 
       [0002]      FIGS. 1 and 2  respectively depict conventional main frames of a single and a dual transistor forward converter having primary side pre-regulation and self-driven synchronous rectifiers, wherein a secondary side error amplification circuit not shown therein detects a sample of an output voltage and compares the sample voltage with a reference voltage to generate an error signal optically coupled to a primary side control circuit and converted into Pulse Width Modulation (PWM) driving signals of primary side switch transistors for regulating the output voltage. 
         [0003]    If the conventional forward converter operates in Continuous Conduction Mode (CCM), the output voltage V out  is expressible as 
         [0000]    
       
         
           
             
               
                 V 
                 out 
               
               = 
               
                 
                   
                     N 
                     s 
                   
                   
                     N 
                     p 
                   
                 
                  
                 
                   D 
                   pri 
                 
                  
                 
                   V 
                   in 
                 
               
             
             , 
           
         
       
     
         [0000]    wherein V in  is the input voltage, D pri  is the variable primary duty ratio of primary side switch transistors, N p  is the turns number of the primary side power winding, and N s  is the turns number of the secondary side power winding. When V out  is lower than its predetermined value, D pri  is increased to appreciate V out ; when V out  is higher than its predetermined value, D pri  is decreased to depreciate V out . Consequently, modulating D pri  can straightforwardly regulate V out . Although very facile, the abovementioned primary side pre-regulation can not achieve zero-voltage switching of primary side switch transistors and suffers from higher switching losses. 
         [0004]    Both the transformer T 1  in  FIG. 1  and the transformer T 2  in  FIG. 2  include a primary side power winding N p  connecting to a primary side power loop, a secondary side power winding N s  connecting to a secondary side power loop, and a secondary side driving winding N d  inducing driving signals of secondary side self-driven synchronous rectifiers. Since N p  itself in  FIG. 1  is inapplicable to reset the core of T 1  but N p  itself in  FIG. 2  is applicable to reset the core of T 2 , the single transistor structure needs a primary side reset winding N r  but the dual transistor structure needs no primary side reset winding N r . In general, the turns number of N r  may be fewer than, equal to, or more than that of N p , respectively causing the maximum drain-source voltage of the primary side switch transistor in the single transistor structure to be higher than, equal to, or lower than 2V in . In contrast, the maximum drain-source voltage of primary side switch transistors in the dual transistor structure identically equals V in . The black dots juxtaposed on certain winding terminals indicate reference polarities for various winding voltages. The dotted and the un-dotted terminal are respectively defined as the positive and the negative terminal of the reference polarity. If the actual polarity coincides with the reference polarity, the winding voltage is positive. Otherwise, it is negative. Because an actual transformer must draw a magnetization current from an external circuit to build up a flux linkage in its core magnetic circuit for inducing various winding voltages, such an electromagnetic conversion process can be electrically modeled as a suppositional magnetization inductor L m  in parallel with the primary side power winding N p . The increasing of the magnetization current represents the magnetization of the transformer core magnetic circuit, and the decreasing of the magnetization current represents the demagnetization of the transformer core magnetic circuit. 
         [0005]    The primary side power loop in  FIG. 1  comprises an input voltage terminal V i , a primary ground terminal V ri , an input filter capacitor C i  having a positive and a negative terminal, a primary side reset winding N r , a reset diode D 1  having an anode and a cathode, a parallel connection of a suppositional magnetization inductor L m  and a primary side power winding N p , as well as a N channel Metal Oxide Semiconductor Field Effect Transistor (NMOSFET) Q 1  having a gate, a drain, a source, and a drain-source capacitor C 1 . Herein, both V i  and V ri  connect to an external DC input voltage source V in ; a positive and a negative terminal of C i  respectively connect to V i  and V ri ; the un-dotted and the dotted terminal of N r  respectively connect to V i  and the cathode of D 1 ; the anode of D 1  connects to V ri ; the dotted and the un-dotted terminal of N p  respectively connect to V i  and the drain of Q 1 ; the source of a connects to V ri ; the gate of Q 1  connects to the primary side PWM driving circuit not shown therein; as well as L m  and C 1  can constitute a series resonance circuit. 
         [0006]    The primary side power loop in  FIG. 2  comprises an input voltage terminal V i , a primary ground terminal V ri , an input filter capacitor C i  having a positive and a negative terminal, a first D 1  and a second reset diode D 2  both having an anode and a cathode, a parallel connection of a suppositional magnetization inductor L m  and a primary side power winding N p , as well as a first Q 1  and a second NMOSFET Q 2  both having a gate, a drain, a source, and a drain-source capacitor C 1 =C 2 . Herein, both V i  and V ri  connect to an external DC input voltage source V in ; a positive and a negative terminal of C i  respectively connect to V i  and V ri ; a cathode and an anode of D 1  respectively connect to the source of Q 1  and V ri ; a cathode and an anode of D 2  respectively connect to V i  and the drain of Q 2 ; the drain of Q 1  connects to V i ; the dotted and the un-dotted terminal of N p  respectively connect to the source of Q 1  and the drain of Q 2 ; the source of Q 2  connects to V ri ; the gates of Q 1  and Q 2  both connect to the primary side PWM driving circuit not shown therein; as well as L m , C 1 , and C 2  can constitute a series resonance circuit. 
         [0007]    Each of the secondary side power loops in  FIGS. 1 and 2  comprises a secondary side driving winding N d , a secondary side power winding N s , a forward SR f  and a freewheeling synchronous rectifier SR w  both having a gate, a drain, and a source, a forward gate resistor R 1 , a forward gate-source resistor R 2 , a freewheeling gate-source resistor R 3 , a freewheeling gate resistor R 4  all having a first and a second terminal, an output power inductor L o  having a first and a second terminal, an output filter capacitor C o  having a positive and a negative terminal, an output voltage terminal V o , as well as a secondary ground terminal V ro . Herein, the dotted and the un-dotted terminal of N d  respectively connect to the first terminal of R 1  and the first terminal of R 4 ; the second terminal of R 1  and the second terminal of R 4  respectively connect to the gate of SR f  and the gate of SR w ; the first and the second terminal of R 2  respectively connect to the gate and the source of SR f ; the first and the second terminal of R 3  respectively connect to the gate and the source of SR w ; the dotted and the un-dotted terminal of N s  respectively connect to the drain of SR w  and the drain of SR f ; the sources of SR f  and SR w  both connect to V ro ; the first and the second terminal of L o  respectively connect to the drain of SR w  and V o ; the positive and the negative terminal of C o  respectively connect to V o  and V ro ; the increasing of the output power inductor current represents the storing of energy to the inductor core magnetic circuit, and the decreasing of the output power inductor current represents the releasing of energy from the inductor core magnetic circuit. 
         [0008]    The operating principle of the single transistor structure can be easily inferred from that of the dual transistor structure, thus only the latter is explicitly described hereinafter.  FIG. 3  depicts crucial waveforms of  FIG. 2  during a switching period, wherein v p   GS (t) and v p   DS (t) are respectively the gate-source voltage and the drain-source voltage, referring to different source potential, of Q 1  and Q 2 ; v L     m   (t) is the voltage across L m ; i L     m   (t) is the current through L m ; v f   GS (t) and v w   GS (t) are respectively the gate-source voltages, referring to same source potentials, of SR f  and SR w ; i L     o   (t) is the current through L o ; V in  is the input voltage; V out  is the output voltage; I out  is the output current; as well as 
         [0000]    
       
         
           
             n 
             = 
             
               
                 N 
                 p 
               
               
                 N 
                 s 
               
             
           
         
       
     
         [0000]    is the turns ratio of the primary to the secondary side power winding. 
         [0009]    During the interval of t 0 ≦t&lt;t 1 , v p   GS (t) is high; the channels of Q 1  and Q 2  are both on; v p   DS (t)=0; both D 1  and D 2  are off due to reverse biases; v L     m   (t)=V in −2v p   DS (t)=V in ; L m  is clamped to V in  and magnetized by i L     m   (t) flowing through the channel of Q 2 , C i , and the channel of Q 1 ; i L     m   (t) is increasing linearly with a positive slope 
         [0000]    
       
         
           
             
               
                 
                    
                   
                     
                       i 
                       
                         L 
                         m 
                       
                     
                      
                     
                       ( 
                       t 
                       ) 
                     
                   
                 
                 
                    
                   t 
                 
               
               = 
               
                 
                   V 
                   in 
                 
                 
                   L 
                   m 
                 
               
             
             ; 
           
         
       
     
         [0000]    the induced voltage across N d  makes v f   GS (t)&gt;0 and v w   GS (t)&lt;0 the channel of SR f  is on and the channel of SR w  is off; i L     o   (t) flows through C o , the channel of SR f , and N s  to magnetize L o ; as well as i L     o   (t) is increasing linearly with a positive slope 
         [0000]    
       
         
           
             
               
                  
                 
                   
                     i 
                     
                       L 
                       o 
                     
                   
                    
                   
                     ( 
                     t 
                     ) 
                   
                 
               
               
                  
                 t 
               
             
             = 
             
               
                 1 
                 
                   L 
                   o 
                 
               
                
               
                 
                   ( 
                   
                     
                       
                         V 
                         in 
                       
                       n 
                     
                     - 
                     
                       V 
                       out 
                     
                   
                   ) 
                 
                 . 
               
             
           
         
       
     
         [0010]    During the interval of t 1 ≦t&lt;t 2 , v p   GS (t) is low; the channels of Q 1  and Q 2  are both off; 
         [0000]    
       
         
           
             
               0 
               ≤ 
               
                 
                   v 
                   p 
                   DS 
                 
                  
                 
                   ( 
                   t 
                   ) 
                 
               
               &lt; 
               
                 
                   V 
                   in 
                 
                 2 
               
             
             ; 
           
         
       
     
         [0000]    both D 1  and D 2  are off due to reverse biases; v L     m   (t)=V in −2v p   DS (t)&gt;0; L m  is magnetized by i L     m   (t) flowing through C 2 , C i , and C 1 ; the induced voltage across N d  makes v f   GS (t)&gt;0 and v w   GS (t)&lt;0; the channel of SR f  is on and the channel of SR w  is off; i L     o   (t) flows through C o , the channel of SR f , and N s  to magnetize L o ; both C 1  and C 2  are charged by a reflected output current 
         [0000]    
       
         
           
             
               
                 I 
                 out 
               
               n 
             
             ; 
           
         
       
     
         [0000]    as well as v p   DS (t) is increasing linearly with a positive slope 
         [0000]    
       
         
           
             
               
                  
                 
                   
                     v 
                     p 
                     DS 
                   
                    
                   
                     ( 
                     t 
                     ) 
                   
                 
               
               
                  
                 t 
               
             
             = 
             
               
                 
                   I 
                   out 
                 
                 
                   nC 
                   1 
                 
               
               . 
             
           
         
       
     
         [0011]    During the interval of t 2 ≦t&lt;t 3 , v p   GS (t) is low; the channels of Q 1  and Q 2  are both off; 
         [0000]    
       
         
           
             
               
                 
                   V 
                   in 
                 
                 2 
               
               ≤ 
               
                 
                   v 
                   p 
                   DS 
                 
                  
                 
                   ( 
                   t 
                   ) 
                 
               
               &lt; 
               
                 V 
                 in 
               
             
             ; 
           
         
       
     
         [0000]    both D 1  and D 2  are off due to reverse biases; v Lm (t)=V in −2v p   DS (t)&lt;0; L m  is demagnetized by i L     m   (t) flowing through C 2 , C i , and C 1 ; the induced voltage across N d  makes v f   GS (t)&lt;0 and v w   GS (t)&gt;0; the channel of SR f  is off and the channel of SR w  is on; i L     o   (t) flows through C o  and the channel of SR w  to demagnetize L o ; i L     o   (t) is decreasing linearly with a negative slope 
         [0000]    
       
         
           
             
               
                 
                    
                   
                     
                       i 
                       
                         L 
                         o 
                       
                     
                      
                     
                       ( 
                       t 
                       ) 
                     
                   
                 
                 
                    
                   t 
                 
               
               = 
               
                 - 
                 
                   
                     V 
                     out 
                   
                   
                     L 
                     o 
                   
                 
               
             
             ; 
             
               N 
               p 
             
           
         
       
     
         [0000]    resembles an open circuit conducting no reflected output current; as well as L m , C 1 , and C 2  constitute a series resonance circuit to increase v p   DS (t) and slightly decrease i L     m   (t). 
         [0012]    During the interval of t 3 ≦t&lt;t 4 , v p   GS (t) is low; the channels of Q 1  and Q 2  are both off; v p   DS (t)=V in ; both D 1  and D 2  are on due to forward biases; v L     m   (t)=V in −2v p   DS (t)=−V in ; L m  is clamped to −V in  and demagnetized by i L     m   (t) flowing through D 2 , C i , and D 1 ; i L     m   (t) is decreasing linearly with a negative slope 
         [0000]    
       
         
           
             
               
                 
                    
                   
                     
                       i 
                       
                         L 
                         m 
                       
                     
                      
                     
                       ( 
                       t 
                       ) 
                     
                   
                 
                 
                    
                   t 
                 
               
               = 
               
                 - 
                 
                   
                     V 
                     in 
                   
                   
                     L 
                     m 
                   
                 
               
             
             ; 
           
         
       
     
         [0000]    the induced voltage across N d  makes v f   GS (t)&lt;0 and v w   GS (t)&gt;0; the channel of SR f  is off and the channel of SR w  is on; i L     o   (t) flows through C o  and the channel of SR w  to demagnetize L o ; as well as i L     o   (t) is decreasing linearly with a negative slope 
         [0000]    
       
         
           
             
               
                  
                 
                   
                     i 
                     
                       L 
                       o 
                     
                   
                    
                   
                     ( 
                     t 
                     ) 
                   
                 
               
               
                  
                 t 
               
             
             = 
             
               - 
               
                 
                   
                     V 
                     out 
                   
                   
                     L 
                     o 
                   
                 
                 . 
               
             
           
         
       
     
         [0013]    During the interval of t 4 ≦t&lt;t 5 , v p   GS (t) is low; the channels of Q 1  and Q 2  are both off; 
         [0000]    
       
         
           
             
               
                 
                   V 
                   in 
                 
                 2 
               
               &lt; 
               
                 
                   v 
                   p 
                   DS 
                 
                  
                 
                   ( 
                   t 
                   ) 
                 
               
               ≤ 
               
                 V 
                 in 
               
             
             ; 
           
         
       
     
         [0000]    both D 1  and D 2  are off due to reverse biases; v L     m   (t)=V in −2v p   DS (t)&lt;0; L m  has been demagnetized completely; i L     m   (t)≈0; the induced voltage across N d  makes v f   GS (t)&lt;0 and v w   GS (t)&gt;0; the channel of SR f  is off and the channel of SR w  is on; i L     o   (t) flows through C o  and the channel of SR w  to demagnetize L o ; i L     o   (t) is decreasing linearly with a negative slope 
         [0000]    
       
         
           
             
               
                 
                    
                   
                     
                       i 
                       
                         L 
                         o 
                       
                     
                      
                     
                       ( 
                       t 
                       ) 
                     
                   
                 
                 
                    
                   t 
                 
               
               = 
               
                 - 
                 
                   
                     V 
                     out 
                   
                   
                     L 
                     o 
                   
                 
               
             
             ; 
             
               N 
               p 
             
           
         
       
     
         [0000]    resembles an open circuit conducting no reflected output current; as well as L m , C 1 , and C 2  constitute a series resonance circuit to decrease v p   DS (t) and slightly increase i L     m   (t). 
         [0014]    During the interval of t 5 ≦t&lt;t 0 , v p   GS (t) is low; the channels of Q 1  and Q 2  are both off; 
         [0000]    
       
         
           
             
               
                 
                   v 
                   p 
                   DS 
                 
                  
                 
                   ( 
                   t 
                   ) 
                 
               
               = 
               
                 
                   V 
                   in 
                 
                 2 
               
             
             ; 
           
         
       
     
         [0000]    both D 1  and D 2  are off due to reverse biases; v L     m   (t)=V in −2v p   DS (t)=0; L m  has been demagnetized completely; i L     m   (t)≈0; the induced voltage across N d  makes v f   GS (t)=0 and v w   GS (t)=0; the channels of SR f  and SR w  are both off; the continuous inductor current i L     o   (t) forces the body diodes of SR f  and SR w  to turn on; i L     o   (t) flows through C o  and (1) the body diode of SR f  and N s  or (2) the body diode of SR w  to demagnetize L o ; i L     o   (t) is decreasing linearly with a negative slope 
         [0000]    
       
         
           
             
               
                 
                    
                   
                     
                       i 
                       
                         L 
                         o 
                       
                     
                      
                     
                       ( 
                       t 
                       ) 
                     
                   
                 
                 
                    
                   t 
                 
               
               = 
               
                 - 
                 
                   
                     V 
                     out 
                   
                   
                     L 
                     o 
                   
                 
               
             
             ; 
           
         
       
     
         [0000]    as well as v L     m   (t) is clamped to 0 and v p   DS (t) is clamped to 
         [0000]    
       
         
           
             
               V 
               in 
             
             2 
           
         
       
     
         [0000]    because the body diodes of SR f  and SR w  are both turned on. 
         [0015]    Since 
         [0000]    
       
         
           
             
               
                 v 
                 p 
                 DS 
               
                
               
                 ( 
                 
                   t 
                   
                     0 
                     ′ 
                   
                   - 
                 
                 ) 
               
             
             = 
             
               
                 V 
                 in 
               
               2 
             
           
         
       
     
         [0000]    is a higher positive voltage as well as both Q 1  and Q 2  are switched on again at t=t 0· to discharge v p   DS (t 0· )=0, the conventional forward converters with primary side pre-regulation can not achieve the zero voltage switching of the primary side switch transistors and suffer from higher switching losses. 
       SUMMARY OF THE INVENTION 
       [0016]    The present invention is directed to a forward converter with secondary side post-regulation and zero voltage switching, wherein a primary side power loop may be but not confined to a single or a dual transistor structure having primary side switch transistors driven by a primary side driving circuit with a constant duty ratio so as to make the voltage waveform across the secondary side power winding have a fixed pulse width; the secondary side power loop uses a controllable switch, which may be but not confined to a Magnetic Amplifier (MA) or a NMOSFET, to blank the leading edge of the voltage waveform across the secondary side power winding; post-regulate the output voltage; and achieve zero voltage switching of primary side switch transistors. 
         [0017]    The secondary side power loop comprises a secondary side driving winding, a secondary side power winding, a forward and a freewheeling synchronous rectifier both having a gate, a drain, and a source, a controllable switch having a control, a first channel, and a second channel terminal, a forward gate resistor, a forward gate-source resistor, a freewheeling gate-source resistor and a freewheeling gate resistor both depending on the topology, an output power inductor having a first and a second terminal, an output filter capacitor having a positive and a negative terminal, an output voltage terminal, as well as a secondary ground terminal. Herein, the dotted and the un-dotted terminal of the secondary side power winding respectively connect to the first channel terminal of the controllable switch and the drain of the forward synchronous rectifier; the second channel terminal of the controllable switch connects to the drain of the freewheeling synchronous rectifier; the sources of the forward and the freewheeling synchronous rectifier both connect to the secondary ground terminal; the first and the second terminal of the output power inductor respectively connect to the drain of the freewheeling synchronous rectifier and the output voltage terminal; as well as the positive and the negative terminal of the output filter capacitor respectively connect to the output voltage and the secondary ground terminal. 
         [0018]    The forward synchronous rectifier is driven by the secondary side driving winding; 
         [0019]    the controllable switch is driven by the secondary side PWM control circuit. The freewheeling synchronous rectifier may be driven by the secondary side PWM control circuit or the secondary side driving winding. If the freewheeling synchronous rectifier is driven by the secondary side PWM control circuit, the dotted terminal of the secondary side driving winding connects to the gate of the forward synchronous rectifier through the forward gate resistor; the un-dotted terminal of the secondary side driving winding connects to the secondary ground terminal; as well as the forward gate-source resistor connects to the gate and the source of the forward synchronous rectifier. If the freewheeling synchronous rectifier is driven by the secondary side driving winding, the dotted terminal of the secondary side driving winding connects to the gate of the forward synchronous rectifier through the forward gate resistor; the un-dotted terminal of the secondary side driving winding connects to the gate of the freewheeling synchronous rectifier through the freewheeling gate resistor, the forward gate-source resistor connects to the gate and the source of the forward synchronous rectifier, as well as the freewheeling gate-source resistor connects to the gate and the source of the freewheeling synchronous rectifier. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0020]      FIGS. 1 and 2  respectively depict conventional main frames of a single and a dual transistor forward converter. 
           [0021]      FIG. 3  depicts crucial waveforms of  FIG. 2  during a switching period. 
           [0022]      FIGS. 4 and 5  respectively depict main frames of a first and a second embodiment based on the present invention. 
           [0023]      FIG. 6  depicts crucial waveforms of  FIG. 5  during a switching period. 
           [0024]      FIGS. 7 and 8  respectively depict main frames of a third and a fourth embodiment based on the present invention. 
           [0025]      FIG. 9  depicts crucial waveforms of  FIG. 8  during a switching period. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0026]    The advantages, features, objectives, and technologies of the present invention will become more apparent from the following description in conjunction with the accompanying drawings, wherein certain embodiments of the present invention are set forth by way of illustration and examples. 
         [0027]      FIGS. 4 ,  5 ,  7 , and  8  respectively depict main frames of a first, a second, a third and, a fourth embodiment based on the present invention. A secondary side error amplification circuit not shown therein detects a sample of the output voltage and compares the sample voltage with a reference voltage to generate an error signal fed back to a secondary side PWM control circuit not shown therein and converted into a PWM driving signal of a secondary side controllable switch for regulating the output voltage. 
         [0028]    If D* pri  is a constant primary duty ratio of primary side switch transistors, the output voltage V out  is expressible as 
         [0000]    
       
         
           
             
               
                 V 
                 out 
               
               = 
               
                 
                   
                     N 
                     s 
                   
                   
                     N 
                     p 
                   
                 
                  
                 
                   D 
                   sec 
                 
                  
                 
                   V 
                   in 
                 
               
             
             , 
           
         
       
     
         [0000]    wherein V in  is the input voltage; N p  is the turns number of the primary side power winding; N s  is the turns number of the secondary side power winding; and D sec ≦D* pri  is a variable secondary duty ratio of a secondary side controllable switch. A variable leading edge blanking time T blank  is expressible as T blank =(D* pri −D sec )T s , wherein T s  is a switching period. When V out  is lower than its predetermined value, D sec  is increased or T blank  is decreased to appreciate V out ; when V out  is higher than its predetermined value, D sec  is decreased or T blank  is increased to depreciate V out . Hence, it can regulate V out  to modulate D sec  or T blank . Besides, the abovementioned secondary side post-regulation can also achieve zero voltage switching of primary side switch transistors to further reduce switching losses. 
         [0029]    Because primary side power loops in  FIGS. 4 and 7  as well as in  FIGS. 5 and 8  are respectively identical to those in  FIG. 1  and in  FIG. 2 , their structural characteristics will not be reiterated in what follows. However, here are some of the remarkable differences between prior arts and the present invention. Distinguishable from the primary side switch transistors in  FIGS. 1 and 2  driven with a variable duty ratio, those in  FIGS. 4 ,  5 ,  7 , and  8  are driven with a constant duty ratio. In prior arts, the error signal generated from comparing the sample voltage with a reference voltage is optically coupled to a primary side PWM control circuit needing an optocoupler circuit. In the present invention, it is fed back to a secondary side PWM control circuit needing no optocoupler circuit. 
         [0030]    Each of secondary side power loops in  FIGS. 4 ,  5 ,  7 , and  8  comprises a secondary side driving winding N d , a secondary side power winding N s , a forward SR f  and a freewheeling synchronous rectifier SR w  both having a gate, a drain, and a source, a controllable switch SW having a control, a first channel, and a second channel terminal, a forward gate resistor R 1 , a forward gate-source resistor R 2 , a freewheeling gate-source resistor R 3  and a freewheeling gate resistor R 4  depending on the topology, an output power inductor L o  having a first and a second terminal, an output filter capacitor C o  having a positive and a negative terminal, an output voltage terminal V o , as well as a secondary ground terminal V ro . Herein, the dotted and the un-dotted terminal of N s  respectively connect to the first channel terminal of SW and the drain of SR f ; the second channel terminal of SW connects to the drain of SR w ; the sources of SR f  and SR w  both connect to V ro ; a first and a second terminal of L o  respectively connect to the drain of SR w  and V o ; as well as a positive and a negative terminal of C o  respectively connect to V o  and V ro . 
         [0031]    SR f  is driven by N d ; SW is driven by the secondary side PWM control circuit. SR w  may be driven by the secondary side PWM control circuit, a topology depicted in  FIGS. 4 and 5 , or by N d , a topology depicted in  FIGS. 7 and 8 . If SR w  is driven by the secondary side PWM control circuit, the dotted terminal of N d  connects to the gate of SR f  through R 1 , the un-dotted terminal of N d  connects to V ro , as well as R 2  connects to the gate and the source of SR f . If SR w  is driven by N d , the dotted terminal of N d  connects to the gate of SR f  through R 1 , the un-dotted terminal of N d  connects to the gate of SR w  through R 4 , as well as R 2  and R 3  respectively connect to the gate and the source of SR f  and SR w . 
         [0032]    In general, SW can be embodied with a MA or a NMOSFET. For the convenience of description, SW is assumed an NMOSFET with a gate, a drain, and a source respectively corresponding to the control, the first channel, and the second terminal. Being the counterpart of the description for embodiments with a NMOSFET, the description for embodiments with a MA can be omitted without loss of generality. 
         [0033]      FIG. 6  depicts crucial waveforms of  FIG. 5  during a switching period, wherein SR w  is driven by the secondary side PWM control circuit. 
         [0034]    During the interval of t 0 ≦t&lt;t 1 , v p   GS (t) is high; the channels of Q 1  and Q 2  are both on; v p   DS (t)=0; both D 1  and D 2  are off due to reverse biases; v L     m   (t)=V in −2v p   DS (t)=V in ; L m  is clamped to V in  and magnetized by i L     m   (t) flowing through the channel of Q 2 , C i , and the channel of Q 1 ; i L     m   (t) is increasing linearly with a positive slope 
         [0000]    
       
         
           
             
               
                 
                    
                   
                     
                       i 
                       
                         L 
                         m 
                       
                     
                      
                     
                       ( 
                       t 
                       ) 
                     
                   
                 
                 
                    
                   t 
                 
               
               = 
               
                 
                   V 
                   in 
                 
                 
                   L 
                   m 
                 
               
             
             ; 
           
         
       
     
         [0000]    the induced voltage across N d  makes v f   GS (t)&gt;0; the channel of SR f  is on. According to v sw   GS (t) and v w   GS (t) provided by the secondary side PWM control circuit, this interval can be further subdivided into three subintervals:
 
During the subinterval of t 0 ≦t&lt;t 01 , SW switches off its channel to blank the leading edge of the voltage waveform across N s ; SR w  switches on its channel to reduce the conduction loss of its body diode; i L     o   (t) flows through C o  and the channel of SR w  to demagnetize L o ; as well as i L     o   (t) is decreasing linearly with a negative slope
 
         [0000]    
       
         
           
             
               
                  
                 
                   
                     i 
                     
                       L 
                       o 
                     
                   
                    
                   
                     ( 
                     t 
                     ) 
                   
                 
               
               
                  
                 t 
               
             
             = 
             
               - 
               
                 
                   
                     V 
                     out 
                   
                   
                     L 
                     o 
                   
                 
                 . 
               
             
           
         
       
     
         [0000]    During the subinterval of t 01 ≦t&lt;t 02 , SW switches off its channel to blank the leading edge of the voltage waveform across N s ; SR w  switches off its channel to avoid a cross conduction between SW and SR w  at t=t 02 ; (t) flows through C o  and the body diode of SR w  to demagnetize L o ; as well as i L     o   (t) is decreasing linearly with a negative slope 
         [0000]    
       
         
           
             
               
                  
                 
                   
                     i 
                     
                       L 
                       o 
                     
                   
                    
                   
                     ( 
                     t 
                     ) 
                   
                 
               
               
                  
                 t 
               
             
             = 
             
               - 
               
                 
                   
                     V 
                     out 
                   
                   
                     L 
                     o 
                   
                 
                 . 
               
             
           
         
       
     
         [0000]    During the subinterval of t 02 ≦t&lt;t 1 , SW switches on its channel and SR w  switches off its channel; i L     o   (t) flows through C o , the channel of SR f , N s , and the channel of SW to magnetize L o ; as well as i L     o   (t) is increasing linearly with a positive slope 
         [0000]    
       
         
           
             
               
                  
                 
                   
                     i 
                     
                       L 
                       o 
                     
                   
                    
                   
                     ( 
                     t 
                     ) 
                   
                 
               
               
                  
                 t 
               
             
             = 
             
               
                 1 
                 
                   L 
                   o 
                 
               
                
               
                 
                   ( 
                   
                     
                       
                         V 
                         in 
                       
                       n 
                     
                     - 
                     
                       V 
                       out 
                     
                   
                   ) 
                 
                 . 
               
             
           
         
       
     
         [0000]    As depicted in  FIG. 6 , the variable leading edge blanking time T blank  is also expressible as T blank =t 02 −t 0  and modulated via t 02  to regulate the output voltage V out . 
         [0035]    During the interval of t 1 ≦t&lt;t 2 , v p   GS (t) is low; the channels of Q 1  and Q 2  are both off; 
         [0000]    
       
         
           
             
               0 
               ≤ 
               
                 
                   v 
                   p 
                   DS 
                 
                  
                 
                   ( 
                   t 
                   ) 
                 
               
               &lt; 
               
                 
                   V 
                   in 
                 
                 2 
               
             
             ; 
           
         
       
     
         [0000]    both D 1  and D 2  are off due to reverse biases; v L     m   (t)=V in −2v p   DS (t)&gt;0; L m  is magnetized by i L     m   (t) flowing through C 2 , C i , and C 1 ; the induced voltage across N d  makes v f   GS (t)&gt;0; the channel of SR f  is on; the secondary side PWM control circuit switches on the channel of SW and switches off the channel of SR w ; i L     o   (t) flows through C o , the channel of SR f , N s , and the channel of SW to magnetize L o ; both C 1  and C 2  are charged by a reflected output current 
         [0000]    
       
         
           
             
               
                 I 
                 out 
               
               n 
             
             ; 
           
         
       
     
         [0000]    and v p   DS (t) is increasing linearly with a positive slope 
         [0000]    
       
         
           
             
               
                  
                 
                   
                     v 
                     p 
                     DS 
                   
                    
                   
                     ( 
                     t 
                     ) 
                   
                 
               
               
                  
                 t 
               
             
             = 
             
               
                 
                   I 
                   out 
                 
                 
                   nC 
                   1 
                 
               
               . 
             
           
         
       
     
         [0036]    During the interval of t 2 ≦t&lt;t 3 , v p   GS (t) is low; the channels of Q 1  and Q 2  are both off; 
         [0000]    
       
         
           
             
               
                 
                   V 
                   in 
                 
                 2 
               
               ≤ 
               
                 
                   v 
                   p 
                   DS 
                 
                  
                 
                   ( 
                   t 
                   ) 
                 
               
               &lt; 
               
                 V 
                 in 
               
             
             ; 
           
         
       
     
         [0000]    both D 1  and D 2  are off due to reverse biases; v Lm (t)=V in 2v p   DS (t)&lt;0; L m  is demagnetized by i L     m   (t) flowing through C 2 , C i , and C 1 ; the induced voltage across N d  makes v f   GS (t)&lt;0; the channel of SR f  is off; N p  resembles an open circuit conducting no reflected output current; L m , C 1 , and C 2  constitute a series resonance circuit to increase v p   DS (t) and slightly decrease i L     m   (t); the secondary side PWM control circuit switches off the channel of SW and switches on the channel of SR w ; i L     o   (t) flows through C o  and the channel of SR w  to demagnetize L o ; as well as i L     o   (t) is decreasing linearly with a negative slope 
         [0000]    
       
         
           
             
               
                  
                 
                   
                     i 
                     
                       L 
                       o 
                     
                   
                    
                   
                     ( 
                     t 
                     ) 
                   
                 
               
               
                  
                 t 
               
             
             = 
             
               - 
               
                 
                   
                     V 
                     out 
                   
                   
                     L 
                     o 
                   
                 
                 . 
               
             
           
         
       
     
         [0037]    During the interval of t 3 ≦t&lt;t 4 , v p   GS (t) is low; the channels of Q 1  and Q 2  are both off; v p   DS (t)=V in ; both D 1  and D 2  are on due to forward biases; v L     m   (t)=V in −2v p   DS (t)=−V in ; L m  is clamped to −V in  and demagnetized by i L     m   (t) flowing through D 2 , C i , and D 1 ; i L     m   (t) is decreasing linearly with a negative slope 
         [0000]    
       
         
           
             
               
                 
                    
                   
                     
                       i 
                       
                         L 
                         m 
                       
                     
                      
                     
                       ( 
                       t 
                       ) 
                     
                   
                 
                 
                    
                   t 
                 
               
               = 
               
                 - 
                 
                   
                     V 
                     in 
                   
                   
                     L 
                     m 
                   
                 
               
             
             ; 
           
         
       
     
         [0000]    the induced voltage across N d  makes v f   GS (t)&lt;0; the channel of SR f  is off; the secondary side PWM control circuit switches off the channel of SW and switches on the channel of SR w ; i L     o   (t) flows through C o  and the channel of SR w  to demagnetize L o ; as well as i L     o   (t) is decreasing linearly with a negative slope 
         [0000]    
       
         
           
             
               
                  
                 
                   
                     i 
                     
                       L 
                       o 
                     
                   
                    
                   
                     ( 
                     t 
                     ) 
                   
                 
               
               
                  
                 t 
               
             
             = 
             
               - 
               
                 
                   
                     V 
                     out 
                   
                   
                     L 
                     o 
                   
                 
                 . 
               
             
           
         
       
     
         [0038]    During the interval of t 4 ≦t&lt;t 5 , v p   GS (t) is low; the channels of Q 1  and Q 2  are both off; 
         [0000]    
       
         
           
             
               
                 
                   V 
                   in 
                 
                 2 
               
               &lt; 
               
                 
                   v 
                   p 
                   DS 
                 
                  
                 
                   ( 
                   t 
                   ) 
                 
               
               ≤ 
               
                 V 
                 in 
               
             
             ; 
           
         
       
     
         [0000]    both D 1  and D 2  are off due to reverse biases; v L     m   (t)=V in −2v p   DS (t)&lt;0; L m  has been demagnetized completely; i L     m   (t)≈0; the induced voltage across N d  makes v f   GS (t)&lt;0; the channel of SR f  is off; the secondary side PWM control circuit switches off the channel of SW and switches on the channel of SR w ; i L     o   (t) flows through C o  and the channel of SR w  to demagnetize L o ; i L     o   (t) is decreasing linearly with a negative slope 
         [0000]    
       
         
           
             
               
                 
                    
                   
                     
                       i 
                       
                         L 
                         o 
                       
                     
                      
                     
                       ( 
                       t 
                       ) 
                     
                   
                 
                 
                    
                   t 
                 
               
               = 
               
                 - 
                 
                   
                     V 
                     out 
                   
                   
                     L 
                     o 
                   
                 
               
             
             ; 
             
               N 
               p 
             
           
         
       
     
         [0000]    resembles an open circuit conducting no reflected output current; as well as L m , C 1 , and C 2  constitute a series resonance circuit to decrease v p   DS (t) and slightly increase i L     m   (t). 
         [0039]    During the interval of t 5 ≦t&lt;t 0 , v p   GS (t) is low; the channels of Q 1  and Q 2  are both off; 
         [0000]    
       
         
           
             
               0 
               &lt; 
               
                 
                   v 
                   p 
                   DS 
                 
                  
                 
                   ( 
                   t 
                   ) 
                 
               
               ≤ 
               
                 
                   V 
                   in 
                 
                 2 
               
             
             ; 
           
         
       
     
         [0000]    both D 1  and D 2  are off due to reverse biases; v L     m   (t)=V in −2v p   DS (t)&gt;0; L m  has been demagnetized completely; i L     m   (t)≈0; the induced voltage across N d  makes v f   GS (t)&gt;0; the channel of SR f  is on; the secondary side PWM control circuit switches off the channel of SW and switches on the channel of SR w ; i L     o   (t) flows through C o  and the channel of SR w  to demagnetize L o ; i L     o   (t) is decreasing linearly with a negative slope 
         [0000]    
       
         
           
             
               
                 
                    
                   
                     
                       i 
                       
                         L 
                         o 
                       
                     
                      
                     
                       ( 
                       t 
                       ) 
                     
                   
                 
                 
                    
                   t 
                 
               
               = 
               
                 - 
                 
                   
                     V 
                     out 
                   
                   
                     L 
                     o 
                   
                 
               
             
             ; 
             
               N 
               p 
             
           
         
       
     
         [0000]    resembles an open circuit conducting no reflected output current; as well as L m , C 1 , and C 2  constitute a series resonance circuit to decrease v p   DS (t) and slightly increase i L     m   (t). 
         [0040]    Since v p   DS (t 0·   − )=0 as well as both Q 1  and Q 2  are switched on again at t=t 0· to discharge v p   DS (t 0· )=0 , the first and the second embodiment of the present invention can properly achieve zero voltage switching of primary side switch transistors to reduce switching losses. 
         [0041]      FIG. 9  depicts crucial waveforms of  FIG. 8  during a switching period, wherein SR w  is driven by N d . 
         [0042]    During the interval of t 0 ≦t&lt;t 1 , v p   GS (t) is high; the channels of Q 1  and Q 2  are both on; v p   DS (t)=0; both D 1  and D 2  are off due to reverse biases; v L     m   (t)=V in −2v p   DS (t)=V in ; L m  is clamped to V in  and magnetized by i L     m   (t) flowing through the channel of Q 2 , C i , and the channel of Q 1 ; i L     m   (t) is increasing linearly with a positive slope 
         [0000]    
       
         
           
             
               
                 
                    
                   
                     
                       i 
                       
                         L 
                         m 
                       
                     
                      
                     
                       ( 
                       t 
                       ) 
                     
                   
                 
                 
                    
                   t 
                 
               
               = 
               
                 
                   V 
                   in 
                 
                 
                   L 
                   m 
                 
               
             
             ; 
           
         
       
     
         [0000]    the induced voltage across N d  makes v f   GS (t)&gt;0 and v w   GS (t)&lt;0 ; the channel of SR f  is on and the channel of SR w  is off. According to v sw   GS (t) provided by the secondary side PWM control circuit, this interval can be further subdivided into two subintervals:
 
During the subinterval of t 0 ≦t&lt;t 02 , SW switches off its channel to blank the leading edge of the voltage waveform across N s ; i L     o   (t) flows through C o  and the body diode of SR w  to demagnetize L o ; as well as i L     o   (t) is decreasing linearly with a negative slope
 
         [0000]    
       
         
           
             
               
                  
                 
                   
                     i 
                     
                       L 
                       o 
                     
                   
                    
                   
                     ( 
                     t 
                     ) 
                   
                 
               
               
                  
                 t 
               
             
             = 
             
               - 
               
                 
                   
                     V 
                     out 
                   
                   
                     L 
                     o 
                   
                 
                 . 
               
             
           
         
       
     
         [0000]    During the subinterval of t 02 ≦t&lt;t 1 , SW switches on its channel; i L     o   (t) flows through C o , the channel of SR f , N s , and the channel of SW to magnetize L o ; as well as i L     o   (t) is increasing linearly with a positive slope 
         [0000]    
       
         
           
             
               
                  
                 
                   
                     i 
                     
                       L 
                       o 
                     
                   
                    
                   
                     ( 
                     t 
                     ) 
                   
                 
               
               
                  
                 t 
               
             
             = 
             
               
                 1 
                 
                   L 
                   o 
                 
               
                
               
                 
                   ( 
                   
                     
                       
                         V 
                         in 
                       
                       n 
                     
                     - 
                     
                       V 
                       out 
                     
                   
                   ) 
                 
                 . 
               
             
           
         
       
     
         [0043]    During the interval of t 1 ≦t&lt;t 2 , v p   GS (t) switches off the channels of Q 1  and Q 2 ; 
         [0000]    
       
         
           
             
               0 
               ≤ 
               
                 
                   v 
                   p 
                   DS 
                 
                  
                 
                   ( 
                   t 
                   ) 
                 
               
               &lt; 
               
                 
                   V 
                   in 
                 
                 2 
               
             
             ; 
           
         
       
     
         [0000]    both D 1  and D 2  are off due to reverse biases; v L     m   (t)=V in −2v p   DS (t)&gt;0; L m  is magnetized by i L     m   (t) flowing through C 2 , C i , and C 1 ; the induced voltage across N d  makes v f   GS (t)&gt;0 and v w   GS (t)&lt;0; the channel of SR f  is on and the channel of SR w  is off; the secondary side PWM control circuit switches on the channel of SW; i L     o   (t) flows through C o , the channel of SR f , N s , and the channel of SW to magnetize L o ; both C 1  and C 2  are charged by a reflected output current 
         [0000]    
       
         
           
             
               
                 I 
                 out 
               
               n 
             
             ; 
           
         
       
     
         [0000]    as well as v p   DS (t) is increasing linearly with a positive slope 
         [0000]    
       
         
           
             
               
                  
                 
                   
                     v 
                     p 
                     DS 
                   
                    
                   
                     ( 
                     t 
                     ) 
                   
                 
               
               
                  
                 t 
               
             
             = 
             
               
                 
                   I 
                   out 
                 
                 
                   nC 
                   1 
                 
               
               . 
             
           
         
       
     
         [0044]    During the interval of t 2 ≦t&lt;t   3 , v p   GS (t) is low; the channels of Q 1  and Q 2  are both off; 
         [0000]    
       
         
           
             
               
                 
                   V 
                   in 
                 
                 2 
               
               ≤ 
               
                 
                   v 
                   p 
                   DS 
                 
                  
                 
                   ( 
                   t 
                   ) 
                 
               
               &lt; 
               
                 V 
                 in 
               
             
             ; 
           
         
       
     
         [0000]    both D 1  and D 2  are off due to reverse biases; v Lm (t)=V in −2v p   DS (t)&lt;0; L m  is demagnetized by i L     m   (t) flowing through C 2 , C i , and C 1 ; the induced voltage across N d  makes v f   GS (t)&lt;0 and v w   GS (t)&gt;0; the channel of SR f  is off and the channel of SR w  is on; the secondary side PWM control circuit switches off the channel of SW; i L     o   (t) flows through C o  and the channel of SR w  to demagnetize L o ; i L     o   (t) is decreasing linearly with a negative slope 
         [0000]    
       
         
           
             
               
                 
                    
                   
                     
                       i 
                       
                         L 
                         o 
                       
                     
                      
                     
                       ( 
                       t 
                       ) 
                     
                   
                 
                 
                    
                   t 
                 
               
               = 
               
                 - 
                 
                   
                     V 
                     out 
                   
                   
                     L 
                     o 
                   
                 
               
             
             ; 
             
               N 
               p 
             
           
         
       
     
         [0000]    resembles an open circuit conducting no reflected output current; as well as L m , C 1  , and C 2  constitute a series resonance circuit to increase v p   DS (t) and slightly decrease i L     m   (t). 
         [0045]    During the interval of t 3 ≦t&lt;t 4 , v p   GS (t) is low; the channels of Q 1  and Q 2  are both off; v p   DS (t)=V in ; both D 1  and D 2  are on due to forward biases; v L     m   (t)=V in −2v p   DS (t)=−V in ; L m  is clamped to −V in  and demagnetized by i L     m   (t) flowing through D 2 , C i , and D 1 ; i L     m   (t) is decreasing linearly with a negative slope 
         [0000]    
       
         
           
             
               
                 
                    
                   
                     
                       i 
                       
                         L 
                         m 
                       
                     
                      
                     
                       ( 
                       t 
                       ) 
                     
                   
                 
                 
                    
                   t 
                 
               
               = 
               
                 - 
                 
                   
                     V 
                     in 
                   
                   
                     L 
                     m 
                   
                 
               
             
             ; 
           
         
       
     
         [0000]    the induced voltage across N d  makes v f   GS (t)&lt;0 and v w   GS (t)&gt;0; the channel of SR f  is off and the channel of SR w is on; the secondary side PWM control circuit switches off the channel of SW; i L     o   (t) flows through C o  and the channel of SR w  to demagnetize L o ; as well as i L     o   (t) is decreasing linearly with a negative slope 
         [0000]    
       
         
           
             
               
                  
                 
                   
                     i 
                     
                       L 
                       o 
                     
                   
                    
                   
                     ( 
                     t 
                     ) 
                   
                 
               
               
                  
                 t 
               
             
             = 
             
               - 
               
                 
                   
                     V 
                     out 
                   
                   
                     L 
                     o 
                   
                 
                 . 
               
             
           
         
       
     
         [0046]    During the interval of t 4 ≦t&lt;t 5 , v p   GS (t) is low; the channels of Q 1  and Q 2  are both off; 
         [0000]    
       
         
           
             
               
                 
                   V 
                   in 
                 
                 2 
               
               &lt; 
               
                 
                   v 
                   p 
                   DS 
                 
                  
                 
                   ( 
                   t 
                   ) 
                 
               
               ≤ 
               
                 V 
                 in 
               
             
             ; 
           
         
       
     
         [0000]    both D 1  and D 2  are off due to reverse biases; v L     m   (t)=V in −2v p   DS (t)&lt;0; L m  has been demagnetized completely; i L     m   (t)≈0; the induced voltage across N d  makes v f   GS (t)&lt;0 and v w   GS (t)&gt;0; the channel of SR f  is off and the channel of SR w  is on; the secondary side PWM control circuit switches off the channel of SW; i L     o   (t) flows through C o  and the channel of SR w  to demagnetize L o ; i L     o   (t) is decreasing linearly with a negative slope 
         [0000]    
       
         
           
             
               
                 
                    
                   
                     
                       i 
                       
                         L 
                         o 
                       
                     
                      
                     
                       ( 
                       t 
                       ) 
                     
                   
                 
                 
                    
                   t 
                 
               
               = 
               
                 - 
                 
                   
                     V 
                     out 
                   
                   
                     L 
                     o 
                   
                 
               
             
             ; 
             
               N 
               p 
             
           
         
       
     
         [0000]    resembles an open circuit conducting no reflected output current; as well as L m , C 1 , and C 2  constitute a series resonance circuit to decrease v p   DS (t) and slightly increase i L     m   (t). 
         [0047]    During the interval of t 5 ≦t&lt;t 0 , v p   GS (t) is low; the channels of Q 1  and Q 2  are both off; 
         [0000]    
       
         
           
             
               0 
               &lt; 
               
                 
                   v 
                   p 
                   DS 
                 
                  
                 
                   ( 
                   t 
                   ) 
                 
               
               ≤ 
               
                 
                   V 
                   in 
                 
                 2 
               
             
             ; 
           
         
       
     
         [0000]    both D 1  and D 2  are off due to reverse biases; v L     m   (t)=V in −2v p   DS (t)&gt;0; L m  has been demagnetized completely; i L     m   (t)≈0; the induced voltage across N d  makes v f   GS (t)&gt;0 and v w   GS (t)&lt;0; the channel of SR f  is on and the channel of SR w  is off; the secondary side PWM control circuit switches off the channel of SW; i L     o   (t) flows through C o  and the body diode of SR w  to demagnetize L o ; i L     o   (t) is decreasing linearly with a negative slope 
         [0000]    
       
         
           
             
               
                 
                    
                   
                     
                       i 
                       
                         L 
                         o 
                       
                     
                      
                     
                       ( 
                       t 
                       ) 
                     
                   
                 
                 
                    
                   t 
                 
               
               = 
               
                 - 
                 
                   
                     V 
                     out 
                   
                   
                     L 
                     o 
                   
                 
               
             
             ; 
             
               N 
               p 
             
           
         
       
     
         [0000]    resembles an open circuit conducting no reflected output current; as well as L m , C 1 , and C 2  constitute a series resonance circuit to decrease v p   DS (t) and slightly increase i L     m   (t). 
         [0048]    Since v p   DS (t 0·   −) =0 as well as both Q 1  and Q 2  are switched on again at t=t 0· to discharge v p   DS (t 0· )=0, the third and the fourth embodiment of the present invention can properly achieve zero voltage switching of primary side switch transistors to reduce switching losses. 
         [0049]    From the foregoing description, it is obvious there exists a causal relationship between secondary side post-regulation of the output voltage and zero voltage switching of primary side switch transistors. During the interval of t 5 ≦t&lt;t 0· , the secondary side controllable switch still remains off so that N p  resembles an open circuit conducting no reflected output current as well as L m , C 1 , and C 2  continue the series resonance depreciating v p   DS (t) to nil. This is the central idea of zero-voltage switching greatly differentiating the present invention from prior arts. 
         [0050]    It should be noted the location of N p , as shown in  FIGS. 4 and 7 , is interchangeable with that of Q 1  as long as the driving signal refers to the source of Q 1 . In retrospect, the primary side pre-regulation modulates D* pri  to regulate V out , thus different output voltages cannot directly correspond to the same duty ratio of the same primary side switch transistors; the secondary side post-regulation modulates D sec  to regulate V out , thus different output voltages can directly correspond to different duty ratios of different secondary side controllable switches. Therefore, the secondary side post-regulation, in addition to zero-voltage switching of primary side switch transistors, is more suitable for simultaneously regulating a multitude of different output voltages than the primary side pre-regulation. 
         [0051]    While the present invention is susceptible to alternative forms and various modifications, specific examples thereof have been shown in the drawings and described in detail. Not limited to the particular forms disclosed herein, the present invention covers all the alternatives, equivalents, and modifications falling within the scope and spirit of the appended claims.