Abstract:
A horizontal deflection circuit output stage includes a trace capacitor for developing a trace voltage. A retrace capacitance is coupled to a deflection winding to form a retrace resonant circuit with the deflection winding, during a retrace interval of a deflection cycle. A rectifier for rectifying a retrace pulse voltage developed in the retrace capacitance. A switching transistor is coupled to the inductance and to the trace capacitor for applying the rectified retrace pulse voltage to the inductance to generate a current in the inductance. The inductance current is coupled to the trace capacitor, during the trace interval, to provide for linearity correction. The rectifier is coupled to the switching transistor for producing a rectified control signal at a control terminal of the switching transistor to cause a change of state in the switching transistor, during the retrace interval.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]    This is a non-provisional application which claims the benefit of provisional application serial No. 60/311,508, filed Aug. 10, 2001. 
     
    
     
       BACKGROUND OF THE INVENTION  
         [0002]    The invention relates to a a linearity corrected deflection apparatus of a cathode ray tube (CRT).  
           [0003]    A horizontal or line deflection circuit produces a horizontal deflection current in a horizontal deflection winding that is mounted on a neck of a CRT. Line deflection circuits are subject to asymmetrical horizontal linearity errors caused by losses in the horizontal deflection winding and the trace switch.  
           [0004]    Typically, a CRT having a reduced length or depth is formed with an increased deflection angle. A CRT with a deflection angle greater than 110° requires a large amount of inside and outside pincushion distortion correction. A large amount of these distortion corrections require extensive amplitude and frequency modulation of the deflection current at a vertical rate. All these increased modulations of the deflection current increase horizontal linearity distortion.  
           [0005]    An active linearity correction circuit is described in U.S. Pat. No. 4,634,938, in the name of Haferl, entitled, Linearity Corrected Deflection Circuit (The Haferl Patent). In the Haferl Patent, the S-shaping or trace capacitor acquires an additional charge during trace to obtain an increased deflection current during the second half of trace. This additional charge is taken out of the trace capacitor during retrace to avoid a DC component in the deflection current. In the Haferl Patent, an inductor is responsive to a deflection retrace pulse voltage for supplying a correction current to the trace capacitor, during the trace interval.  
         SUMMARY OF THE INVENTION  
         [0006]    A deflection apparatus with raster distortion correction, embodying an inventive feature, includes a deflection winding. A retrace, first capacitance is coupled to the deflection winding to form a retrace resonant circuit with the deflection winding, during a retrace interval. A trace, second capacitor is coupled to the deflection winding to form a trace resonant circuit with the deflection winding, during a trace interval. A source of a synchronizing signal at a frequency related to a first deflection frequency is provided. A first switching semiconductor is responsive to the synchronizing signal and coupled to the deflection winding and to the retrace first capacitance to generate a first retrace pulse voltage in the retrace, first capacitance, during the retrace interval, and a deflection current in the deflection winding. A charge holding, third capacitance is provided. A sampling switching semiconductor is responsive to the first retrace pulse voltage and coupled to the third capacitance for sampling the first retrace pulse voltage and for developing a sampled voltage from a charge stored in the third capacitance. The sampled voltage is indicative of a magnitude of the first retrace pulse voltage. A first inductance is coupled to the third capacitance for applying the sampled voltage to the first inductance, during the trace interval, to generate a current in the first inductance. The first inductance current is coupled to the trace, second capacitor for varying, in accordance with the first inductance current, a trace voltage in the second capacitor to provide raster distortion correction.  
           [0007]    Using the charge holding third capacitor provides design flexibility for obtaining the desirable waveform of the correction current. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]    [0008]FIG. 1 illustrates a schematic diagram of a deflection circuit, embodying an inventive feature;  
         [0009]    [0009]FIG. 2 illustrates a schematic diagram of a deflection circuit, embodying another inventive feature; and  
         [0010]    [0010]FIGS. 3 a ,  3   b  and  3   c  illustrate waveforms useful for explaining the operation of deflection circuit of FIG. 2.  
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0011]    [0011]FIG. 1 illustrates a schematic diagram of a deflection circuit  100 , embodying an inventive feature. Deflection circuit  100  operates at a horizontal frequency of, for example 2×fH and a period of one-half H. The term fH denotes the horizontal frequency in a television standard such as 15,625 KHz. Similarly, the term H denotes the horizontal period in the television standard.  
         [0012]    Deflection circuit  100  includes a primary winding W 1  coupled to a source of a constant value supply voltage B+. Winding W 1  of a conventional flyback transformer T is also coupled to a horizontal output or switching transistor Q 1  controlled by a horizontal drive signal  50  having approximately 50% duty cycle. An emitter voltage of transistor Q 1  is at a common conductor potential, or ground. A retrace capacitor C 1  is coupled to a terminal  51  and in parallel with transistor Q 1 .  
         [0013]    A junction terminal  51  of winding W 1  and a collector of transistor Q 1  is coupled to a retrace capacitor C 2 . A terminal  52  of retrace capacitor C 2  is coupled to a retrace capacitor C 3 . A damper diode D 1  is coupled in parallel with capacitor C 2 . A damper diode D 2  is coupled in parallel with capacitor C 3 . Junction terminal  52  is coupled to an East-West modulation inductor Lew. Inductor Lew has a terminal  53  that is coupled to a collector of an East-West modulation transistor Qew and to a filter capacitor Cew to form a conventional diode modulator that provides outside pincushion distortion correction.  
         [0014]    Transistor Qew is controlled in a conventional manner by a vertical rate parabolic manner East-West modulation signal E/W-DRIVE having a period V. The term V denotes the vertical period in the television standard, such as 20 millisecond. A feedback resistor transistor Rew is coupled between the collector and base of transistor Qew to provide operation in class A mode of operation. A vertical rate parabolic manner modulation voltage Vm is developed at terminal  53 , in a conventional manner. A conventional S-shaping capacitor Cs is coupled between terminal  52  and a terminal  54 . A deflection winding Ly is coupled between terminals  51  and  54 .  
         [0015]    A linearity correction arrangement  120 , embodying an inventive feature, includes circuit elements shown inside a box drawn in a broken line that provides linearity correction. With the exception of the operation of linearity correction arrangement  120 , deflection circuit  100  produces a deflection current Iy in winding Ly in a conventional manner and operates as a conventional diode modulator.  
         [0016]    At the beginning of horizontal retrace, transistor Q 1  becomes non-conductive and produces a retrace pulse voltage in capacitor C 2 . Because of the modulation produces by transistor Qew, retrace voltage VC 2  in capacitor C 2  has a peak amplitude, during horizontal retrace, that varies in a vertical rate parabolic manner. Thereby, amplitude modulation of a deflection current Iy in winding Ly is provided at a vertical rate. During horizontal trace, the voltage at terminal  51  is close to zero volts because either both diodes D 1  and D 2  are conductive or transistor Q 1  is conductive.  
         [0017]    A sampling diode D 3 , embodying an inventive feature, is coupled between terminal  51  of capacitor C 2  and a terminal  60  of a capacitor C 4 . Capacitor C 4  is coupled in series with a capacitor C 5  between terminals  51  and  52 . The arrangement of diode D 3  and capacitors C 4  and C 5  forms a sample-and-hold circuit.  
         [0018]    In carrying out an inventive feature, retrace voltage VC 2  is sampled via diode D 3  for generating a rectified or sampled voltage VC 4 C 5  in charge holding capacitors C 4  and C 5 . Rectified or sampled voltage VC 4 C 5  is equal to the peak value of voltage VC 2  and is proportional to the peak amplitude of deflection current Iy in winding Ly in each horizontal period. The peak value of voltage VC 4 C 5  varies in a vertical rate parabolic manner and tracks the peak amplitude variations of deflection current Iy. Sampled voltage VC 4 C 5  is applied via terminal  60  to a linearity correction inductor L 1 .  
         [0019]    Voltage VC 4 C 5  generates a linearity correction current IL 1  in inductor L 1 , during retrace and during trace. The charged stored in capacitors C 4  and C 5  and voltage VC 4 C 5  decrease gradually, during horizontal trace. A magnitude of current IL 1  is determined by the charged stored in capacitors C 4  and C 5 .  
         [0020]    The charge stored in capacitors C 4  and C 5  is determined by the values of capacitors C 2 , C 4  and C 5 . For a given value of inductor L 1 , the charge stored in capacitors C 4  and C 5  mainly depends on the ratio of the values of capacitors C 4  and C 2 . The effect of capacitor C 5  is small, because capacitor C 5  is a relatively large capacitor and develops a relatively low voltage. Thus, advantageously, the magnitude of current IL 1  can be selected by selecting the ratio of the values of capacitors C 4  and C 2 .  
         [0021]    A terminal  61  of inductor L 1  is coupled to an anode of a diode D 5 . Diode D 5  is coupled in series with a metal oxide semiconductor (MOS) transistor Q 2 . A portion of voltage VC 4 C 5 , developed in capacitor C 5 , drives a gate of transistor Q 2  via a gate resistor R 1  to produce a gate voltage VG. A voltage limiting zener diode D 4  is coupled to the gate of transistor Q 2 .  
         [0022]    During horizontal retrace, voltage VG turns on transistor Q 2  and causes diode D 5  to become conductive. After the center of retrace, inductor L 1  begins discharging capacitor C 5 . Consequently, the gate capacitance, not shown, of transistor Q 2  is discharged via a gate resistor R 1 , causing gate voltage VG of transistor Q 2  to decrease until transistor Q 2  is turned off.  
         [0023]    During horizontal trace, current IL 1  flows in an inductor L 2  as a current IL 2 . Current IL 2  flows also in a capacitor C 7  and capacitor Cs for increasing voltage VCS. An increase in voltage VCS, during trace, corrects linearity errors, in a well known manner. The peak amplitude of voltage VCS at a given portion of horizontal trace varies in a vertical rate parabolic manner, during vertical trace, and, advantageously, closely tracks the variation in the peak amplitude of deflection current iy.  
         [0024]    A direct current (DC) blocking capacitor C 7  is coupled in series with inductor L 2 , between terminals  54  and  61 . Capacitor C 7  prevents current IL 2  from containing any DC current component. Any DC current component in current IL 2  would have produced an undesirable centering offset or shift.  
         [0025]    During trace, current IL 2  flows in the direction shown by the arrow and charges capacitor C 7 . Therefore, a voltage VC 7  is developed from current IL 2  in capacitor C 7  in the polarity shown.  
         [0026]    On the other hand, during retrace, transistor Q 2  and diode D 5  are turned on, as explained before. Thereby, inductor L 2 , capacitor C 7  and capacitor Cs form a resonant circuit that produces a half cycle of resonant current IL 2 . The half cycle of resonant current IL 2  varies in a sinusoidal manner in a negative polarity, opposite to that shown by the arrow. Negative current IL 2  discharges capacitor C 7  to decrease voltage VC 7 . Voltage VC 7  reaches zero volts at the negative peak of current IL 2  and becomes negative at the end of the sinusoidal half cycle in current IL 2 . Consequently, the arrangement formed by capacitor C 7 , inductor L 2 , diode D 5  and transistor Q 2  prevents any undesirable build-up of excessive DC voltage component in voltage VC 7 .  
         [0027]    The resonance frequency of the resonant circuit formed by inductor L 2 , capacitor C 7  and capacitor Cs, during retrace, can be, preferably, the same as or higher than the retrace resonance frequency. Preferably, the resonance frequency of the resonant circuit formed by inductor L 2 , capacitor C 7  and capacitor Cs should not be selected too high since the dissipation increases with frequency. A capacitor C 8  and a resistor R 2  that are coupled in series between terminals  54  and  61  prevent ringing caused by diode D 5 .  
         [0028]    During start-up, it may be desirable to produce horizontal drive signal  50  at a frequency that is higher than the frequency, during normal operation. Thereby, soft start can be provided in transistor Q 1 . The higher frequency of signal  50  can undesirably result in an excessive DC current in a DC current path from voltage B+ to ground formed by Diode D 3 , inductor L 1 , diode D 5 , transistor Q 2 , inductor Lew and transistor Qew. It can be desirable to prevent the formation of the DC current path from voltage B+ to ground via diode D 3 , inductor L 1 , diode D 5 , transistor Q 2 , inductor Lew and transistor Qew.  
         [0029]    [0029]FIG. 2 illustrates a schematic diagram of a deflection circuit  100 ′, embodying another inventive feature, for preventing any DC current, during start-up. Deflection circuit  100 ′ depicts an alternating current (AC) —coupled version of deflection circuit  100  of FIG. 1. FIGS. 3 a ,  3   b  and  3   c  illustrate waveforms useful for explaining the operation of deflection circuit  100 ′ of FIG. 2. Similar symbols and numerals in FIGS. 1, 2 and  3   a - 3   d  indicate similar items or functions.  
         [0030]    In deflection circuit  100 ′ of FIG. 2, retrace voltage VC 2 ′ is AC-coupled via a capacitor C 10  and sampled via diode D 3 ′ for developing a sampled voltage VC 4 C 5 ′ of FIG. 3 b  in a charge holding capacitor C 4 ′ of FIG. 2 that is analogous to series coupled capacitors C 4  and C 5  of FIG. 1. Capacitor C 10  of FIG. 2 prevents the formation of a DC current path from voltage B+ to ground via inductor L 1 ′. Except for the AC coupling formed by capacitor  10 , deflection circuit  100 ′ operates similarly to deflection circuit  100  of FIG. 1.  
         [0031]    The amount of linearity correction is selected by the values of capacitors C 2 ′, C 10  and C 4 ′ of FIG. 2. Capacitor C 6  couples a portion of voltage VC 4 C 5 ′ to the gate of transistor Q 2 ′ for turning on transistor Q 2 ′, during retrace, as explained before. Resistor R 1 ′ is coupled in series with a diode D 7  between terminal  51 ′ and the gate of transistor Q 2 ′ for discharging a gate capacitance, not shown, of transistor Q 2 ′, at the end of retrace and for maintaining it discharged, throughout trace. Consequently, transistor Q 2 ′ is non-conductive, throughout trace.  
         [0032]    During trace, a positive portion  72  of current IL 2 ′ of FIG. 3 a  charges capacitor C 7 ′ of FIG. 2. Therefore, a sum of voltages VC 7 ′ and VCS′ increases. Consequently, at the end of trace, a voltage V 2 ′ of FIG. 3 c  across the series arrangement of diode D 5 ′ and transistor Q 2 ′ is higher than at the beginning of trace. Because of discharging capacitor C 4 ′, voltage VC 4 C 5 ′ of FIG. 3 b  decreases gradually, during horizontal trace. Therefore, advantageously, the waveform of current IL 2 ′ of FIG. 3 a  is closer to the ideal waveform than if voltage VC 4 C 5 ′ were present only during horizontal retrace.  
         [0033]    During retrace, a resonant portion  71  of current IL 2 ′, produced by a resonant circuit that includes capacitor C 7 ′ and inductor L 2 ′, forms a half cycle sinusoidal waveform of current IL 2 ′ having a negative polarity, for reversing the polarity of voltage VC 7 ′ of FIG. 2. Consequently, the DC voltage component of voltage VC 7 ′ is advantageously eliminated.