Abstract:
An electrostatic discharge (ESD) protection circuit for protecting one or more devices in an electronic circuit from an ESD current which enters the electronic circuit through one or more input/output pins, the protection circuit comprising: a voltage clamp circuit connectable to the or each pin, for diverting the ESD current from the or each device; and a current sensor circuit connected between the input/output pins and the voltage clamp circuit and connected to the one or more devices, the current sensor circuit for sensing the ESD current and for switching off the or each device when the sensed current exceeds a threshold value, wherein when a current flows in the current mirror circuits above a threshold value the device is caused to switch off.

Description:
FIELD OF THE INVENTION 
       [0001]    This invention relates to an electrostatic discharge protection circuit, to an equipment including such a circuit and to a method of manufacturing such a circuit. 
       BACKGROUND OF THE INVENTION 
       [0002]    An electrostatic discharge (ESD) is a sudden unwanted current that can flow between two objects at different electrical potentials and as a result cause damage to electronic equipment that constitutes one or other of the two objects. ESD is a serious issue in solid-state electronics and can cause immediate permanent damage to a circuit or can result in less obvious forms of degradation that may affect the long-term reliability and performance of the circuit. As a result, there are many methods, systems and circuits for preventing an ESD event. The ESD prevention can form part of the circuit or device or can constitute an external protection component located within the circuit layout. 
         [0003]    In order to determine the susceptibility of an electronic circuit to an ESD event, there are a number of ESD test models which exist and which specify the nature of an ESD event. The models are defined by various standards and the most common models include the human body model (HBM), the gun stress model (GSM) and the machine model (MM). 
         [0004]    The gun or machine model ESD event as specified in International Electronics Commission (IEC), standard 61000-4-2 and Joint Election Device Engineering Course JESD22-A115A respectively, deal with situations where the ESD injected current may be high. The table below shows the situation for contact discharge and air discharge and sets out a level to which the equipment specification should comply and required test voltage associated with each level. The standard ESD gun test current waveform is shown in  FIG. 1 . 
         [0000]    
       
         
               
               
               
               
               
             
               
               
               
               
               
             
           
               
                   
                   
               
               
                   
                 1a - Contact discharge 
                   
                 1b - Air discharge 
                   
               
             
          
           
               
                   
                   
                 Test voltage 
                   
                 Test voltage 
               
               
                   
                 Level 
                 kV 
                 Level 
                 kV 
               
               
                   
                   
               
               
                   
                 1 
                 2 
                 1 
                 2 
               
               
                   
                 2 
                 4 
                 2 
                 4 
               
               
                   
                 3 
                 6 
                 3 
                 8 
               
               
                   
                 4 
                 8 
                 4 
                 2 
               
               
                   
                 x 1)   
                 Special 
                 x 1)   
                 Special 
               
               
                   
                   
               
               
                   
                   1) “x” is an open level. The level has to be specified in the dedicated equipment specification. From IEC 61000-4-2 if higher voltages than those shown are specified, special test equipment may be needed. 
               
             
          
         
       
     
         [0005]    Standard prior art protection circuits protect integrated circuits (IC) by means of voltage clamps combined with diodes or PNP transistors connected to the input and output (I/O) pins. These protection circuits divert the current that is being injected during an ESD event by essentially clamping the IC pin voltage at a level that is sufficient to avoid circuit destruction. However, when large sized power transistors, with low ohmic routing, connect to an input/output (I/O) pin, an ESD event can cause a fast voltage transient (high dV/dt event) which results in either the base or gate of the power transistor being pulled up through a parasitic base collector or drain gate capacitance, allowing the power transistor to switch on. Even though the pin voltage is clamped and stays below the transistor breakdown voltage, the power transistor current resulting from this could easily result in device destruction if the ESD injected current is sufficiently high, such as might be experienced during an ESD gun or machine model event. 
         [0006]      FIG. 2  shows an example of a prior art drawing showing a bipolar transistor ESD protection circuit which includes three input/output (I/O) pins  200 ,  202 ,  204 ; three diodes  206 ,  208 ,  210  and a voltage clamp  212 . 
         [0007]    US2006/0043490A1 discloses a system and method for the protection of a transistor from electrostatic discharge current associated with an ESD event. This is achieved by implementing an ESD detector circuit which is separate from the main clamp circuit and which detects an ESD event by detecting a high dV/dt event using an RC time constant and capacitive coupling. However, it is necessary to optimise the RC time constant for a particular ESD model event and in the case where inductive loads are switched, the ESD detect circuit can be triggered during normal operation. 
       SUMMARY OF THE INVENTION 
       [0008]    The present invention provides an electrostatic discharge protection circuit, equipment including such a circuit and method of manufacturing such a circuit as described in the accompanying claims. 
         [0009]    Specific embodiments of the invention are set forth in the dependent claims. 
         [0010]    These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    Further details, aspects and embodiments of the invention will be described, by way of example only, with reference to the drawings. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. 
           [0012]      FIG. 1  schematically shows an example of an ESD current waveform associated with the table, in accordance with the prior art. 
           [0013]      FIG. 2  is a circuit diagram of a prior art ESD circuit. 
           [0014]      FIG. 3  schematically shows an example of an embodiment of an ESD protection circuit. 
           [0015]      FIG. 4  schematically shows an example of an embodiment of a cross-section of the PNP mirror of  FIG. 3 . 
           [0016]      FIG. 5  schematically shows an example of an embodiment of the top side view of the PNP mirror  FIGS. 3 and 4 . 
           [0017]      FIG. 6  schematically shows an example of an embodiment of an automobile including an ESD protection circuit. 
           [0018]      FIG. 7  schematically shows an example of an embodiment of a mobile phone including an ESD protection circuit. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0019]    Referring to  FIG. 3  an example of protecting integrated circuitry, for example protecting a high-voltage output transistor switch from drawing current during a high current ESD event, is shown. The device protected could be an amplifier, such as a bipolar or MOS. Similarly, the device could include a cascade of transistors. However the ESD protection circuitry may be used for other types of devices and for other types of ESD events. The circuit described and illustrated in  FIG. 3  includes a centralised clamp  300  which is connected to the cathode (or base) of one or more large isolation diodes or a transistor such as a parasitic transistor  302 ,  304  and  306  with their anodes (or emitters) connected to the circuit I/O pins  308 ,  310  and  312  respectively. The circuit further comprises one or more lateral bipolar transistors  314 ,  316  and  318  which form current mirrors  320 ,  322  and  324  with the respective large isolation diodes which form current sensor circuits. From a fabrication point of view each of the lateral bipolar transistors may be formed in a single well by drawing stripes in the proximity of the isolation diodes stripes. These stripes may form the collector of the so formed lateral bipolar transistors and are used as ESD current sense elements that are connected to the output transistor&#39;s ( 326 ) gate or base pull down circuitry ( 330 ). The gate or base pull down circuit effectively constitutes a control circuit for the device or devices. This will be described in greater details with respect to  FIGS. 4 and 5 . The value of the mirror ratio can be determined by the length of the stripes mentioned earlier, as will be described in greater detail with respect to  FIG. 5 . 
         [0020]    During a positive ESD event on one or more pins, the isolation diodes  302 ,  304  and  306  and the centralised clamp  300  will divert the main ESD current. The current mirrors  320 ,  322  and  324  sense the ESD current and switch on the pull down circuitry, thereby avoiding capacitive pull-up of the output transistor&#39;s ( 326 ) gate or base and switching off the output transistor  326 . This effectively prevents the output transistor from switching on and self-destructing. The integrated circuit may also includes a gate driver  328  being part of the circuit that is active under normal operating conditions connected to the output transistor  326 . The output transistor  326  may be in the form of a MOSFET or any other appropriate type of device. The output transistor  326  may, as shown be connected to the pin to drive the voltage and/or current as the pin and thus to output signals. The protection circuitry and the device(s) to be protected may be included in a single integrated circuit, for example on multiple dies provided in a single package or on a single die. Although not shown in  FIG. 1 , the output transistor  326  may be connected, via gate driver  328  to a source of the signals to be outputted, such as a processor core or other suitable circuitry. 
         [0021]    The pull-down circuitry ( 330 ) will become active above a certain threshold value, for example an ESD current threshold value. As shown, the bipolar transistors  314 ,  316 ,  318 , are connected with a current output to the control input, e.g. in this example, the gate of the pull down transistor. A resistor  332  connects the current output to ground and forms a current to voltage converter. A diode is connected with a cathode to the gate and with an anode to ground. Thus, when the voltage diode is in reverse, the current will flow through the resistor  332 , and the voltage generated by the resistor  332  will cause the pull down resistor to pull down the gate of the output transistor  326 . The circuit properties may be designed or redesigned by varying the value of the resistor  332  and the mirror ratio of all or any of the PNP mirrors. For example, the circuit may be designed to pull down the output power transistors gate when the ESD injected current equals 10 Amps and to do nothing if the value of current is below this. Alternatively, the threshold may be 2 Amps for certain output transistor  326  or any other value depending on the circuit requirement. The gate pull down circuit could alternatively be in the form of a current mirror, a bipolar transistor, a cascade of amplifiers or any other device having a current input and current output. The gate pull down circuit may include a current to voltage (not shown per se) converter circuit for example a resistor. In an alternative, the current to voltage converter circuit may be separate from the gate pull down circuit. 
         [0022]    The PNP mirrors  320 ,  322  and  324  may be made by means of different components.  FIG. 4  shows an embodiment thereof. A cross-section of a PNP mirror is shown identifying the layout of the different materials in terms of N-type and P-type materials. The cross-section shows a first p-type substrate  400  on to which an N-type layer  402  is added. N-type sinkers  404  are masked on to the n-type layer and a layer of insulator  406  is applied. Highly doped P-type regions  408  are then applied. The figure also identifies the emitter (e), the base (b) and the collectors (c) of the so formed vertical and lateral bipolar transistors. 
         [0023]    Referring to  FIG. 5  a top view of the layout of the PNP mirror is illustrated. The collector (C) and emitters (stripes E) are made of p-type material as previously indicated. The base (B) is made of n-type material and surrounds the stripes (E). The island  500  is added to form the collector of lateral bipolar device. This results in the PNP mirror being relatively easily produced with a little change to the layout and without the need for process changes. The ratio of the lengths of the island to the stripes is used to define and determine the mirror ratio of the PNP mirrors. The island defining the proportion of current in the lateral bipolar transistor and the stripe defining the proportion of current in the large isolation diode. The mirror ratio may be associated with the threshold value, such that threshold value changes can be managed by designing the current mirror with a different ratio or changing the value of resistor  332  in  FIG. 3 . In order to change the mirror ratio the length of the island can be made larger or smaller. 
         [0024]    The ESD circuit can form part of an ESD system for example as shown in  FIG. 6  in an automobile. The automobile  600  includes an ESD system  602  including the ESD circuit  604  which are used to protect the engine  606  and electronics or other circuitry  608  in the car. Similarly in  FIG. 7  a mobile phone  700  includes an ESD system  702  including the ESD circuit according to the present invention  704  which is designed to protect the electronics and circuitry  706  in the mobile phone. 
         [0025]    In the foregoing specification, the invention has been described with reference to specific examples of embodiments of the invention. It will, however, be evident that various modifications and changes may be made therein without departing from the broader spirit and scope of the invention as set forth in the appended claims. For example, the connections in the circuit, system or device may be a type of connection suitable to transfer signals from or to the respective nodes, units or devices, for example via intermediate devices. Accordingly, unless implied or stated otherwise the connections may for example be direct connections or indirect connections. 
         [0026]    Also, the centralised clamp  300  may be located in different orientations than in a central orientation, for example the clamp  300  may be located closer to certain I/O pins than others. The clamp, whether centralised or not, may be in the form of a Zener diode, which may be connected to the base of all the bipolar transistors. The clamp may also be in the form of a diode string, a silicon controlled rectifier, a grounded gate NMOS (ggNMOS) or switches that fire when a fast voltage transient is detected. The semiconductor substrate described herein can be any semiconductor material or combinations of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, monocrystalline silicon, the like, and combinations of the above. 
         [0027]    Because the apparatus implementing the present invention is, for the most part, composed of electronic components and circuits known to those skilled in the art, circuit details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention. 
         [0028]    Although the invention has been described with respect to specific conductivity types or polarity of potentials, skilled artisans appreciated that conductivity types and polarities of potentials may be reversed. 
         [0029]    Moreover, the terms “up”, “down”, “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein. 
         [0030]    Some of the above embodiments, as applicable, may be implemented using a variety of different information processing systems. For example, although  FIG. 3  and the discussion thereof describes an exemplary ESD protection circuit architecture, this exemplary architecture is presented merely to provide a useful reference in discussing various aspects of the invention. Of course, the description of the architecture has been simplified for purposes of discussion, and it is just one of many different types of appropriate architectures that may be used in accordance with the invention. 
         [0031]    Thus, it is to be understood that the architectures depicted herein are merely exemplary, and that in fact many other architectures can be implemented which achieve the same functionality. In an abstract, but still definite sense, any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being “operably connected,” or “operably coupled,” to each other to achieve the desired functionality. 
         [0032]    Furthermore, those skilled in the art will recognize that boundaries between the functionality of the above described operations merely illustrative. The functionality of multiple operations may be combined into a single operation, and/or the functionality of a single operation may be distributed in additional operations. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments. 
         [0033]    However, other modifications, variations and alternatives are also possible. The specifications and drawings are, accordingly, to be regarded in an illustrative rather than in a restrictive sense. 
         [0034]    In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word ‘comprising’ does not exclude the presence of other elements or steps then those listed in a claim. Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an”. The same holds true for the use of definite articles. Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage.