Abstract:
A DCR detecting circuit is parallel connected to the inductor of a self-clocking PWM buck converter which performs a trigger control of a PWM signal by an output feedback, to detect the current signal on the inductor to provide a large enough ripple to be combined into the output feedback, so as to enhance the system stability, while remains the small output ripple, without additional power loss.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention is related generally to power supplies and, more particularly, to a self-clocking pulse width modulation (PWM) buck converter. 
       BACKGROUND OF THE INVENTION 
       [0002]    In a conventional constant on-time or hysteretic mode self-clocking PWM buck converter, the generation of the PWM signal relies on the output ripple to carry out a trigger control. In this control scheme, ripples that are too small will damage the loop stability while ones that are too large will bring the converter to operate over the specification of the converter. It is a trade-off choice to have a small output ripple and to remain the loop stability. 
         [0003]      FIG. 1  shows a conventional constant on-time PWM buck converter. To make it clearer, the equivalent serial resistances (ESR) of the inductor  12  and output capacitor  18  are shown as resistors  14  and  16 , respectively. A PWM controller  10  provides PWM signals to switch a high-side switch Q 1  and a low-side switch Q 2 . When the high-side switch Q 1  is on and the low-side switch Q 2  is off, the inductor current IL charges the output capacitor  18  and the output voltage VOUT increases. When the high-side switch Q 1  is off and the low-side switch Q 2  is on, the output capacitor  18  discharges and the output voltage VOUT decreases. Resistors  20  and  22  constitute a voltage divider to divide the output voltage VOUT to provide a feedback signal FB for the PWM controller  10 , so as to regulate the output voltage VOUT. Ideally, the ripple on the output voltage VOUT is preferred as small as possible. Accordingly, the output capacitor  18  is so designed to have small equivalent resistor  16 , for example, using a ceramic capacitor. However, a small output ripple results in a small ripple feedback signal FB, and since the PWM controller  10  uses the ripple of the feedback signal FB to trigger the PWM signal to switch the high-side switch Q 1  and the low-side switch Q 2 , a small ripple feedback signal FB will make the PWM signal easier to be interfered by noises and thus cause the system unstable.  FIG. 2  shows the waveforms of the feedback signal FB, the inductor current IL, and the output voltage VOUT when the equivalent resistor  16  is small. As shown, after the load changes, the system becomes unstable and the inductor current IL and the output voltage VOUT diverge. For the PWM controller  10  to trigger the PWM signal more precisely, the ripple of the feedback signal FB needs to be large enough, which is contrary to the need of small ripple for the output voltage VOUT. 
         [0004]    In order to stabilize a PWM buck converter and keep the output ripple small, a PWM buck converter is proposed as shown in  FIG. 3 , in which the output capacitor  18  has a small equivalent resistor  16 , and thus the feedback signal FB generated by the voltage divider composed of the resistors  20  and  22  has a too small ripple for the PWM controller  10  to have a good feedback control. However, a resistor  24  and a capacitor  26  is so configured to filter the voltage at the phase node P and couple it to the feedback signal FB to enlarge the ripple of the feedback signal FB. Unfortunately, when the high-side switch Q 1  is on, an additional current path is established from the high-side switch Q 1  through the resistors  24  and  22  to ground GND, which increases power loss and degrades the efficiency of the converter. 
       SUMMARY OF THE INVENTION 
       [0005]    One object of the present invention is to reduce the output ripple of a self-clocking PWM buck converter. 
         [0006]    Another object of the present invention is to enhance the stability of a self-clocking PWM buck converter. 
         [0007]    Still another object of the present invention is to prevent a self-clocking PWM buck converter from additional power loss. 
         [0008]    According to the present invention, a direct current resistor (DCR) detecting circuit is parallel connected to the inductor of a self-clocking PWM buck converter which performs a trigger control of a PWM signal by an output feedback, in order to detect the current signal on the inductor to provide a large enough ripple to combine into the output feedback. 
         [0009]    With the large enough ripple feedback provided by the DCR detecting circuit, it might remain the system stability together with the small output ripple, without additional power loss. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0010]      FIG. 1  shows a conventional constant on-time PWM buck converter; 
           [0011]      FIG. 2  is a waveform diagram to show the output signal variation when the converter of  FIG. 1  suffers a load change; 
           [0012]      FIG. 3  shows another conventional constant on-time PWM buck converter; 
           [0013]      FIG. 4  is a first embodiment according to the present invention; 
           [0014]      FIG. 5  is a second embodiment according to the present invention; 
           [0015]      FIG. 6  is a waveform diagram obtained by simulation by using the circuit of  FIG. 5 ; 
           [0016]      FIG. 7  is a third embodiment according to the present invention; and 
           [0017]      FIG. 8  is a waveform diagram obtained by simulation by using the circuit of  FIG. 7 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0018]      FIG. 4  is a first embodiment according to the present invention, in which the ESR of the output capacitor  18 , namely the equivalent resistor  16 , is designed so small that the ripple on the output voltage VOUT is small and thus the output voltage VOUT can be regarded as DC voltage. Resistors  20  and  22  constitute a voltage divider to divide the output voltage VOUT to generate a feedback signal FB 1  that can be also regarded as DC voltage. The resistor  14  denotes the ESR on the inductor path between the phase node P and the output terminal VOUT. An RC circuit including serially connected resistor  32  and capacitor  34  is parallel connected to the inductor  12 , to serve as a DCR detecting circuit, and thus the voltage across the capacitor  34  equals to the voltage across the ESR  14 , i.e., the product of the inductor current IL and the resistance of the ESR  14 . The voltage across the ESR  14  contains an AC component, which is amplified by an amplifier  36  and by a combiner  40 , combined into the feedback signal FB 1  buffered by a buffer  38 , so as to enlarge the ripple of the feedback signal FB 2  provided for the PWM controller  10 . Thereupon, the feedback signal FB 2  has a larger ripple to enhance the system stability, while the output voltage VOUT remains a rather small ripple. 
         [0019]      FIG. 5  is a second embodiment according to the present invention, in which a voltage follower  46  has its input to receive the feedback signal FB  1  provided by the divider resistors  20  and  22 , and an output terminal coupled to an output terminal of a transconductive amplifier  42  through a resistor  44  having a resistance R, and the transconductive amplifier  42  having a gain gm transforms the voltage across the capacitor  34  to a current flowing through the resistor  44  to generate a voltage to be combined into the feedback signal FB 1 . If the voltage across the capacitor  34  is VC 1 , then the feedback signal FB 2 =VC 1 ×gm×R+FB 1 , wherein the component (VC 1 ×gm×R) provides the ripple feedback that the system requires for stability.  FIG. 6  is a waveform diagram obtained by simulation by the circuit of  FIG. 5 . As shown, because the equivalent resistor  16  of the output capacitor  18  is very small, the output voltage VOUT has a very small ripple. However, the feedback signal FB 2  which has the enlarged ripple still has a ripple large enough to trigger the PWM signal effectively. When the load changes from light to heavy, the output voltage VOUT drops down and the inductor current IL jumps higher, while the feedback signal FB 2  still remains a stable ripple. When the heavy load changes back to the light load, the inductor current IL lowers down, and the output voltage VOUT raises up and releases excess charges so that the feedback signal FB 2  has a large wave ripple, but it returns to the original level quickly. 
         [0020]      FIG. 7  is a third embodiment according to the present invention, in which the AC signal across the capacitor  34  is directly coupled into the feedback signal FB 1  by a capacitor  48 , in order to provide enough ripple for system stability, while the output voltage VOUT still has rather small ripple. As shown in  FIG. 8 , when the load changes from light to heavy, the output voltage VOUT in this embodiment does not drop down significantly, but only lowers slightly and returns to the original level immediately. When the heavy load changes back to the light load, the inductor current IL returns to the original level, and the output voltage VOUT releases excess charges, causing a large ripple and the feedback signal FB 2  following accordingly, but the feedback signal FB 2  recovers to the original level immediately. 
         [0021]    As shown in the above embodiments, the DCR detecting circuit detects the current signal on the inductor to provide enough ripple feedback for system stability, together with the small output ripple, without additional power loss. 
         [0022]    While the present invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and scope thereof as set forth in the appended claims.