Abstract:
The invention describes a method for the selective dry etching of tantalum and tantalum nitride films. Tantalum nitride layers ( 30 ) are often used in semiconductor manufacturing. The semiconductor substrate is exposed to a reducing plasma chemistry which passivates any exposed copper ( 40 ). The tantalum or tantalum nitride films are selectively removed using an oxidizing plasma chemistry.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to a dry etching process for the selective removal of tantalum and tantalum nitride layers. The dry etch process used etches tantalum and tantalum nitride without significantly attacking copper layers and silicon oxide based dielectric layers.  
       BACKGROUND OF THE INVENTION  
       [0002]     The use of copper for forming the metal interconnect lines in integrated circuits is finding increasing usage due to the superior properties of copper compared to the widely used aluminum lines. One of the primary challenges in integrated circuit fabrication is reducing the RC time delay. An important component of the RC time delay is the resistance and the capacitance present in the metal lines that connect the various devices that comprise the integrated circuit. The resistivity of copper is 1.72×10 −6  Ohm-cm versus that of aluminum which is 2.82×10 −6  Ohm-cm. This reduced resistivity will reduce the RC delay associated with copper lines. In addition copper has superior resistance to electromigration and higher reliability when compared to commonly used aluminum alloys.  
         [0003]     In general integrated circuit metal lines are formed in dielectric layers. These dielectric layers typically comprise silicon oxide or contain silicon oxide. In a typical damascene process for forming an integrated circuit copper line a trench is first formed in a dielectric layer which is formed over a silicon substrate containing electronic devices such as transistors, diodes, etc. This is illustrated in  FIG. 1  where the dielectric layer  10  is formed over a silicon substrate. Using standard silicon processing technology a trench  20  is formed in the dielectric layer  10 . Because copper reacts with silicon oxide, it is necessary to confine it using a barrier layer. A commonly used barrier layer is tantalum nitride (Ta x N y ) which is formed on the dielectric layer before the formation of the copper layer. A Ta x N y  barrier layer  30 ,  35  is shown in  FIG. 1 . The Ta x N y  is formed in a blanket deposition resulting in region  35  which line the trench and region  30  which forms on the surface on the dielectric layer  10  outside the trench. Following the formation of the Ta x N y  barrier layer a thick layer of copper is formed. Using standard processing techniques such as chemical mechanical processing (CMP) the excess copper is removed leaving that portion of copper  40  which forms in the trench. To complete the process the portions of the barrier layer which are not cover by copper (i.e. regions  30  in  FIG. 1 ) must be removed. Using existing methods the selective removal of the Ta x N y  layer is a very difficult process. CMP processes are often used to remove the exposed Ta x N y  layer  30  but this often results in dishing of the exposed copper surface an erosion of the underlying dielectric layer  10 . Wet chemical etching of the exposed Ta x N y  layer is difficult because most of the chemical solutions which etch Ta x N y  will attack the underlying dielectric material and etch or damage the exposed copper surfaces. A method is therefore needed to selectively etch Ta x N y  layers without damaging the underlying dielectric layer and/or the exposed copper surface.  
       SUMMARY OF INVENTION  
       [0004]     Tantalum and tantalum nitride layers are often formed during integrated circuit formation. The instant invention recites a method to selectively etch tantalum nitride. The instant invention comprises exposing a semiconductor substrate comprising at least one tantalum layer and/or tantalum nitride layer to reducing plasma chemistry where this reducing chemistry passivates any exposed copper or dielectric layers exposed to the reducing chemistry. All or a portion of the tantalum and/or tantalum nitride layers can then be selectively removed by exposing the semiconductor substrate to an oxidizing plasma chemistry.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0005]     In the drawings:  
         [0006]      FIG. 1  is a cross section diagram illustrating a tantalum nitride barrier layer beneath a copper region.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0007]     A two step dry etch process is used to selectively etch Ta x N y  and/or Tantalum (Ta). The subscripts x and y in the chemical symbol for tantalum nitride (i.e. Ta x N y ) represent integer numbers that depend on the form of the tantalum nitride alloy. The etch process of the instant invention will selectively etch all forms of tantalum nitride alloys and well as tantalum metal. The process conditions are described in the following table:  
                                                                         Reducing   Oxidizing                Indices   Units   Step 1   Step 2                       Wafer   Celsius   &gt;60   &lt;100           Temperature           Pressure   milliTorr   500-900   500-900           N 2     Sccm   250-1000   0           NH 3     Sccm   1000-4000   0           O 2     Sccm   0   1000-5000           H 2     Sccm   0   0           C 2 F 4     Sccm   0   20-100           Power   Watts   700-1200   800-1800                      
 
         [0008]     As shown in above table, the first step of the process comprises a plasma process with nitrogen (N 2 ) and ammonium (NH 3 ) as the active gases. In addition to N 2  and NH 3  other gases, including carrier gases such as argon, can be present in the chamber without departing from the instant invention. In an embodiment of the instant invention the flow rates of N 2  and NH 3  are preferably 480 Sccm and 2200 Sccm respectively, the power 900 Watts, and the wafer temperature approximately 250° C. This step modifies the surfaces of the Ta x N y  and/or Ta layers by exposing the surfaces to a reducing plasma chemistry. In addition to modifying the surface of the Ta x N y  and/or Ta, the first step of the process passivates the copper surfaces exposed to the first step (e.g.  40  in  FIG. 1 ) thereby reducing the oxidation rate of the copper surface. Therefore the first step of the etch process simultaneously modifies the surface of the Ta x N y  and/or Ta layers and passivates the exposed copper surfaces reducing the oxidation rate of the copper surface.  
         [0009]     The second step of the process comprises a plasma process with oxygen (O 2 ) and tetrafluoroethylene (C 2 F 4 ) as the active gases. In addition to O 2  and C 2 F 4  other gases can be present in the chamber without departing from the instant invention. In an embodiment of the instant invention the flow rates of O 2  and C 2 F 4  are preferably 2900 Sccm and 60 Sccm respectively, the power 1200 Watts, and the wafer temperature approximately 60° C. This step uses an oxidizing plasma chemistry to remove the modified Ta x N y  and/or Ta layer without significantly attacking the dielectric layer. In addition the passivated copper surface from step one will be highly resistant to the oxidizing chemistry of the second step and therefore will not be significantly attacked during step two of the process. The two step etch process of the instant invention therefore results in a selective process for etching (or removing) Ta x N y  and/or Ta layers without attacking any underlying dielectric layers or exposed copper surfaces.  
         [0010]     The above described two step etch process can be performed in the same plasma chamber or may be performed in separate chambers. In addition to etching the Ta x N y  and/or Ta barrier layers in copper metallization process, the process of the instant invention can be used to etch Ta x N y  and/or Ta layers and films in any application.  
         [0011]     While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims any such modifications or embodiments.