Abstract:
An inverter for producing regulated AC voltage from an unregulated DC voltage source, such as a battery, employs two stepped voltage waveform generating means independently controlled in phase to produce waveform outputs that approach sine waves which are additively combined to produce an AC output voltage whose amplitude is sensed to produce a feedback signal for comparison with a reference voltage to produce an error signal that causes one stepped waveform generating means to so shift in phase relative to the other as to reduce the error. Each stepped voltage waveform generating means is capable of producing at least half the total desired AC output voltage, so that the DC voltage source may drop by as much as 50% and the desired AC output voltage can still be maintained by shifting the relative phase between the stepped waveforms.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to inverters, and more particularly to a system for efficiently supplying regulated AC voltage to a load from an unregulated source of DC voltage. 
     In many applications it is necessary to supply AC voltage to a load from a battery source, such as in portable electronic systems and in emergency power systems for hospitals and the like. Consequently, a preferred embodiment of the invention is directed to an inverter capable of efficiently supplying regulated AC voltage from a battery to a load over an extended period during which the output voltage of the battery may decrease 50%. However, in its broadest aspects, the invention may be employed with any source of DC voltage. 
     SUMMARY OF THE INVENTION 
     In accordance with the present invention, an unregulated DC source, such as a battery, is coupled to a load by two stepped waveform generating means, each generating means being capable of delivering half the voltage to the load. The generating means produce phase displaced stepped waveforms that approximate sine waves. Means are provided for additively combining the two stepped waveforms and for phase shifting one stepped waveform relative to the other for controlling their sum applied to the load. Sensing means responsive to the amplitude of the AC output voltage applied to the load produces a feedback signal that is compared with a reference signal to produce an error signal that is applied to means for so shifting the phase of one relative to the other of the two stepped waveform generating means as to reduce the error signal. 
     Each stepped waveform generating means is comprised of at least two output power bridges, each bridge having an output transformer and power switches for selectively connecting the ends of a primary winding of the transformer to positive and negative terminals of the DC source. The secondary windings of the two power bridge transformers are connected in series, and a step up ratio is so preselected for each transformer that when the voltages are selectively induced and additively combined across their series-connected secondary windings, a stepped waveform approximating a sine wave is produced across the load. 
     The novel features that are considered characteristic of this invention are set forth with particularity in the appended claims. The invention will best be understood from the following description when read in connection with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates two output power bridges for use in the present invention to produce a stepped voltage waveform from a DC source. 
     FIG. 2 illustrates a stepped voltage waveform and timing diagrams for the generation of the stepped voltage waveform by the two output power bridges of FIG. 1. 
     FIG. 3 is a circuit diagram of a preferred embodiment for an output power bridge. 
     FIG. 4 illustrates the manner in which two output power bridge sections are employed to additively combine out-of-phase stepped waveforms, and to control their phase to regulate power to the load. 
     FIG. 5 illustrates a preferred embodiment of the present invention. 
     FIG. 6 is a timing diagram useful in understanding the phase shift control implemented in the preferred embodiment of FIG. 5. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The basic concept of the present invention will first be described with reference to FIGS. 1 and 2. The circuit of FIG. 1 is a stepped  waveform generator comprised of output power bridges 10 and 11 connected to a battery 12 by power switches shown schematically as single-pole switches S1a, S1b, S2 and S3 and &#34;complementary&#34; single-pole switches S1a, S1b, S2 and S3. The term &#34;complementary&#34; implies that when one switch is open, such as switch S1a, the complementary switch S1a is closed, and vice versa. The switches S1a and S1b are employed to selectively connect one end of primary windings of transformers T1 and T2 to one terminal (+) of the battery, and switches S2 and S3 are employed to selectively connect the other end of the primary windings to the same terminal (+). Complementary switches S1a, S1b, S2 and S3 are employed to selectively connect the ends of the primary windings to the terminal of the battery of opposite polarity (-). 
     If the switches S1a, S1b, S2 and S3 are operated (closed) together, a voltage +V 1  is produced across the series connected secondary winding of the transformer T2. Operation of the switches S1a, S1b, S2 and S3 produces a voltage +V 2  across the transformer T1, and operation of the switches S1a, S1b, S2 and S3 produces a voltage +(V 1  +V 2 ) as shown in FIG. 2. If operation of each of the switches in the three combinations is reversed, the voltages produces are -V 1 , -V 2  and -(V 1  +V 2 ), and if all the possible combinations are selected in proper sequence, the result is a stepped waveform that approximates a sine wave. 
     Timing waveforms W, Y and Z are shown in FIG. 2 for operation of the switches S1a, S1b, S2 and S3. The following table explicitly sets forth the requisite conditions of all the switches for the stepped waveform. 
     
         ______________________________________VOLTAGE OUTPUT CLOSED SWITCHES______________________________________+V.sub.1       S1a      S1b      S2    S3--+V.sub.2       S1a      S1b      S2--  S3+(V.sub.1 + V.sub.2)          S1a      S1b      S2--  S3---V.sub.1       S1a----  S1b----  S2--  S3-V.sub.2       S1a----  S1b----  S2    S3---(V.sub.1 + V.sub.2)          S1a----  S1b----  S2    S3______________________________________ 
    
     Since switches S1a and S1b are operated together, a single control signal W operates both. When that signal is true (high) in the timing diagram of FIG. 2, both switches S1a and S1b are closed and their complementary switches S1a and S1b are open. When the control signal Y is also true, and the control signal Z is not, the transformer T1 is effectively removed from the circuit of FIG. 1, leaving only the voltage +V 1  induced across the secondary of the transformer T2. The turn ratios of the transformers T1 and T2 are 2.68X:1 and X:1, where X is a value selected for the particular value of voltage V 1  desired. When only W is true, switches S1a, S1b, S2 and S3 are closed to have both transformers active in the circuit. That yields the voltage +(V 1  +V 2 ). And when only W and Z are true, switches S1a, S1b and S3 are closed to effectively remove the transformer T2 from the circuit and provide a voltage output across the transformer T1 of a level +V 2 . All switches are reversed in state for the negative voltages -V 1 , -V 2  and -(V 1  +V 2 ), as noted hereinbefore. 
     It has been determined that odd harmonics up to the ninth are eliminated if the transformer turn ratios are 2.68X:1 and X:1 in producing the stepped waveform of FIG. 2. This provides highly efficient power inversion at low cost because only eight saturating switches (transistors, silicon controlled rectifiers, or the like) are required in conjunction with two transformers and a logic network for control of the power switches according to the foregoing table. The logic network may be economically manufactured as CMOS integrated circuits which require very low power. 
     Efficiency in power inversion arises from the elimination of the odd harmonics because harmonics must either be returned to the power supply or be wasted. In either case, the output stage of the amplifier must be overdesigned to handle both the desired fundamental and the undesired harmonics. These features are at odds with the obtainable efficiencies in classical linear amplifiers, classes A, B, etc. Thus, according to the present invention, a stepped waveform is obtained by additively combining switched voltage outputs for six discrete step levels such that only higher order (11, 13, . . . ) odd harmonics exist. An excellent sine wave output can be obtained by the addition of a harmonic filter to eliminate the eleventh and thirteenth harmonics. 
     It should be noted that although switched transformers have been illustrated in FIG. 1 as the preferred embodiment of the invention, switched output power amplifiers or other switched voltage translating means could be additively combined to produce the same stepped waveform. Consequently, the disclosure of switched transformers is by way of illustration only, and not by way of limitation. 
     FIG. 3 illustrates a preferred circuit for implementing an output power bridge (OPB) such as the one for the voltage ±V 2  of FIG. 2, namely the transformer T1 and switches S1a, S2, S1a and S2. The switches are comprised of NPN transistors Q 1  through Q 4  transformer coupled to signals W and Y. Three parallel diodes protect each transistor as shown. An OPB is provided for the voltage ±V 1  of FIG. 2 identical to the OPB of FIG. 3, except for the turn ratio of its output transformer T2. 
     There are several known methods of controlling the power output of an inverter that could be employed. One is to provide complete separation of the regulation and the inverter in the form of a series regulator used to maintain a constant RMS voltage at the output of the inverter. That technique requires placing a switching transistor between the battery and a storage capacitor, and operating the switch at a rate which will maintain the storage capacitor charged to a constant level. However, this requires switching the power source. Another technique which does not require switching the power source, and which is illustrated in FIG. 4, is phase shift control of two inverters operating with their outputs additively combined. 
     Referring now to FIG. 4, stepped wave control unit 20 is provided to drive the switching transistors of two output power bridges 21 and 22, each power bridge being of the configuration shown in FIG. 3 with transformer turn ratios as described with respect to FIG. 1 in order to produce the respective voltages -V 2  and ±V 1  for summing according to the timing waveforms of FIG. 2. A similar stepped wave control unit 23 drives the switching transistors of two output power bridges 24 and 25 to produce a stepped waveform 180° out of phase with that across output power bridges 21 and 22. Its phase is then controlled by a phase shifter 26 to control the output voltage as sensed across a load 27. The stepped wave control units are preferably implemented with digital counters responsive to clock pulses from a source 28. Phase shifting may then be easily carried out by inhibiting clock pulses to the unit 23 when a comparator 29 detects a difference between a feedback signal V FB  and a reference voltage V REF , thus shifting the phase of one stepped sinusoidal waveform relative to the other until their phase angle has been decreased from 180° to some smaller angle where the additively combined waveforms provide a voltage across the load 27 that produces a feedback signal via amplifier 30 and low pass filter 31 substantially equal to the reference. 
     In the case of a battery supplying the DC voltage, the regulated voltage to the load will quickly reach the desired level with a phase angle between 180° and 0° necessary for the condition of the battery. As the battery discharges, its voltage will tend to decrease, thus causing the phase angle to be further decreased toward 0°. If power to the load is turned off for some time, the battery will tend to regenerate itself. Consequently, upon turning the power back on, the voltage output to the load will be slightly higher than set by the reference voltage. To correct that, a second phase shifter 32 may be provided to inhibit clock pulses from the source 28 in response to the error voltage from the comparator 29 via an inverter 33. When the other stepped waveform is thus shifted in phase, the phase angle between the stepped waveforms will be increased to decrease the output voltage to the load. Once the error is reduced to zero, neither phase shifter will inhibit clock pulses so that the attained phase angle will be maintained until an error occurs again. To avoid overcorrecting by shifting phase too fast, each phase shifter may be implemented to inhibit only one clock pulse out of every few (for example four) cycles of the stepped waveforms while an error signal is present. In addition, a minimum error may be required before the phase shifter will begin inhibiting clock pulses by setting an inhibit control signal true only when the minimum error is present, as by a high gain saturating amplifier at the control input. This technique for correcting an error of either polarity is, of course, used with any unregulated DC voltage source for providing regulated AC voltage to a load. For the special case of a battery, however, it is possible to provide for correction of an error of only one polarity if, each time power is turned on to the load, the control units 20 and 23 are reset to a phase angle of 180°. Voltage to the load can then always be increased to the required phase angle for the condition of the battery at that time, and further increased as the battery is discharged until power to the load is turned off. That technique is employed in the exemplary embodiment of FIG. 5. 
     Referring now to FIG. 5, it is contemplated that stepped wave control logic units 40 and 50 be implemented with digital circuits comprised of CMOS counters and decoders. The counters count clock pulses from a source (not shown). Each counter counts twelve steps, six for a positive half sine wave cycle and six for a negative half sine wave cycle of the stepped output waveform, and then starts over again. A decoder responds to the counter and generates a switching pulse for each transistor as required by the timing diagram of FIG. 2. In that manner two stepped waveforms are generated each capable of delivering one half the total rated power of a load so when additively combined in the secondary windings of OPB transformers, the total rated power can be delivered to the load even through the battery source may vary over its useful life by 50%. 
     Initially, the two stepped waveforms generated will be 180° out of phase when the inverter is turned on by means (not shown) that initializes both counters at zero. A sense amplifier 60 drives a low pass filter 61 to produce a DC feedback signal V FB  that is proportional to the voltage supplied to the load. That feedback signal is compared with a reference voltage V REF  in a saturating differential amplifier 62. If the output voltage from the inverter is too low, the difference output from the amplifier 62 is positive at a predetermined logic level used in a phase shifter 70 to inhibit clock pulses, thus shifting the phase of the stepped waveform produced by a group of output power bridges 74 and 75 until the output waveform of that group of output power bridges additively combined with the output waveform of a group of output power bridges 76 and 77 reduces the error output signal from the comparator 62 to zero. Each OPB has a transformer with a turn of 0.5X:1, and the voltages ±V 1  and ±V 2  are generated by the respective groups of two and five OPBs operating in parallel by groups, but with the secondary windings of their transformers in series, as shown. A voltage transformer T3 has its primary winding in parallel with the load (not shown), or in series with the load when a current transformer is used. 
     In this exemplary embodiment, the phase shift increment Δφ is 7.5°, and the total phase shift nΔφ is equal to the number n of clock pulses inhibited. However, the increment may be selected to be any greater angle such as 15°, or some smaller angle such as 1° for finer control of the power output. Such finer control could be accomplished by using a higher frequency clock, inserting a frequency divider at the input of each stepped waveform control unit, and inhibiting clocks to the frequency divider at the input of the inverter to be phase controlled. 
     The phase shift rate of control selected for this exemplary embodiment is one half a clock period (7.5°) of clock pulses applied to a 12-step counter 41 for every four cycles of the stepped output waveform, as determined by a counter 71 which divides the output of the counter 41 by four. The output of the counter 71 is combined in an exclusive-OR circuit 72 with the clock pulses to drive a 12-step counter 51 of the stepped wave control unit 50. A decoder 52 decodes the 12 steps and operates the OPB groups 74 and 75 to generate a stepped waveform additively combined with the stepped waveform generated by the operation of the 12-step counter 41 and decoder 42 in direct response to clock pulses. 
     When power is first turned on, all counters are initially set to zero (by means not shown) while the counter 71 is set to binary 11 to produce a positive output. Consequently, the counters 41 and 51 will initially operate synchronously, thus producing stepped waveforms 180° out of phase owing to the polarity of the secondary windings of the OPB groups 74 and 75 vis-a-vis the polarity of the secondary windings in the OPB groups 76 and 77. The groups operating as two stepped waveform generators thus produce zero output when power is first turned on. An error signal from the comparator amplifier 62 enables the counter 71 to start counting cycles of the counter 41. Its output then goes to a low level. 
     When the output of the counter 41 goes low, as shown in FIG. 6, it will cause the exclusive-OR circuit 72 to inhibit one clock pulse otherwise applied to the counter 51 due to the inherent function of an &#34;exclusive-OR&#34; network, which is to transmit a high level signal from the clock source or the counter 71, but not both, as shown in FIG. 6. If a phase shift of 7.5° of the counter 51 is sufficient to correct the error, the counter 71 will be disabled before it counts four cycles of the counter 41. Its output will then remain low to prevent any further phase shift until another error signal occurs to enable it. It will then count through, and when its output goes high again (after counting four cycles of the counter 41 has been completed) the phase of the counter 51 is again shifted 7.5° by inhibiting another clock pulse transmitted by the exclusive-OR circuit. 
     It should be noted that in the one case (output of counter 71 high), pulses transmitted by the exclusive-OR circuit 72 are the negative going half cycles of the clock pulse waveform, and vice-versa. Consequently, with each transition of the output of the counter 71, there is a 7.5° shift in the phase of the counter 51. Therefore, if the error persists (as it will initially upon turning power on to the load) the counter 51 will be shifted 7.5° in phase relative to the counter 41 every four cycles of the counter 41 until the phase of the counter 51 has been shifted (delayed) enough to remove the error. 
     If the voltage applied to the groups of output power bridges is from a battery, the output voltage reached will tend to slowly degrade but will otherwise be quite stable and will not at any time significantly exceed the reference so that it never becomes necessary to shift the relative phase of the two counters 41 and 51 in the opposite direction. In other applications where the DC voltage source is subject to surges rather than a steady decline, a separate reference comparator and phase shifter may be provided to phase shift the counter 41 by inhibiting clock pulses in the same way to bring the output voltage back down to the reference, as described with reference to FIG. 4. 
     Assuming a battery for the source, as the DC voltage decreases, the error signal will come on again from time to time, causing the counter 71 to resume counting cycles of the counter 41, and in so doing resume inhibiting clock pulses transmitted by the &#34;exclusive-OR&#34; network 71, until a total phase shift of 180° has been introduced in the counter 51, putting the stepped waveforms generated by the two counters 41 and 51 (via decoders 42 and 52) in phase. That is the limit of control. 
     In some applications the power will be turned on and off. Each time the power is turned on, the counters 41 and 51 should be reset to zero. That is because most batteries have a tendency to regenerate themselves slightly when not in use, and the control system of this exemplary embodiment can approach the reference from only one side. But that is a purely arbitrary choice. The present invention is not limited to use with a battery or, as just noted, to approaching the reference from one direction. However, regardless of the nature of the DC voltage source, it is desirable to stop the counters 41 and 51 when their decoded outputs produce a zero voltage at the end of a positive half cycle so that the remnant flux in the cores of the OPB transformers is a minimum and of the opposite polarity for the next step to be generated. That is accomplished in the following manner. 
     Two JK flip-flops FF 1  and FF 2  are controlled by an ON-OFF switch 80. When the switch is set to the ON position, the flip-flop FF 1  is set with the next positive output from the counter 41 (i.e., at the beginning of a negative half cycle of the output of the counter 41 when the stepped waveform it controls first goes negative). That enables the decoder 42 to respond to the counter 41 which is running even while the switch 80 is in the OFF position shown. Setting the flip-flop FF 1  resets the counter 71. The flip-flop FF 2 , also controlled by the ON-OFF switch, is not set until the counter 51 completes a cycle. Counters 41 and 42 are synchronized when the switch 80 is turned to the ON position. Consequently, the flip-flop FF 2  controls a NAND gate 81 to transmit pulses from the clock source until it is set at the end of a cycle of the counter 51. At that time a NAND gate 82 is enabled to allow clock pulses to be applied to the counter 51 from the phase shifter 70. NAND gate 83 transmits pulses from either NAND gate 81 or 82. Regulation then proceeds as described hereinbefore. 
     When the ON-OFF switch 80 is returned to the OFF position, the flip-flop FF 1  is reset at the end of a positive half cycle of the counter 41. The flip-flop FF 2  is not reset until the counter 51 also completes a positive half cycle. The NAND gate 81 is then enabled to transmit clock pulses, while the decoder 52 is disabled. An &#34;exclusive-OR&#34; circuit 84 will, however, inhibit clock pulses at the NAND gate 81 until the counter 41 is phase shifted one half cycle, thus restoring the phase difference between the counters 41 and 51 to 180°. Once the phase difference of 180° is restored, the gate 81 transmits clock pulses to operate the counter 41 in synchronism (but 180° out of phase) with the counter 51. 
     Although particular embodiments of the invention have been described and illustrated herein, it is recognized that modifications and variations may readily occur to those skilled in the art. It is therefore intended that the claims be interpreted to cover such modifications and variations.