Abstract:
In accordance with an embodiment, a light emitting element driving circuit includes a comparator having an input connected to smoothing circuit and an output connected to a voltage-dividing circuit through a transistor. A drain-to-source resistance of the transistor is connected in parallel with a portion of the voltage dividing circuit. An output signal of the voltage dividing circuit is connected to another comparator that generates a drive transistor drive signal. The drive transistor is connected to one or more light emitting elements. In accordance with another embodiment, a reference voltage is generated in response to a rectified signal and compared with a sense voltage to generate a drive signal that is used to drive the drive transistor. Light is emitted from the one or more light emitting elements in response to the drive signal and the rectified voltage being greater than the forward voltage drops of the one or more light emitting elements.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the benefit of priority to Japanese Patent Application No. 2011-131441, filed Jun. 13, 2011, of which full contents are incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a light emitting element driving circuit. 
     2. Description of the Related Art 
     Lighting equipment using an LED (Light Emitting Diode) may use an LED driving circuit which drives an LED while improving the power factor (See Patent Document 1, for example). 
       FIG. 11  is a diagram illustrating a common configuration of an LED driving circuit. When an AC voltage Vac of a commercial power supply is supplied to a full-wave rectifying circuit  300 , the full-wave rectifying circuit  300  applies full-wave rectification to the AC voltage Vac for output. Resistors  310  and  320  divide the rectified voltage Vrec subjected to the full-wave rectification at the full-wave rectifying circuit  300  and outputs the result as a reference voltage Vref. The switching circuit  330  turns on the NMOS transistor  340  at predetermined intervals, and the switching circuit  330  turns off the NMOS transistor  340  when a voltage Vs according to the current flowing through an LED  350  becomes the reference voltage Vref. Since the reference voltage Vref and the rectified voltage Vrec are similar in an LED driving circuit  200 , the waveform of the current flowing through the LED  350  also becomes similar to the waveform of the rectified voltage Vrec. Therefore, the LED driving circuit  200  can drive the LED  350  while improving the power factor. 
     The amplitude of the AC voltage Vac of the commercial power supply may greatly vary within a range of, for example, 90 to 140V. In such a case, the level of the reference voltage Vref also varies greatly resulting with cases where the current flowing through the LED  350  vary significantly, and the brightness of the LED  350  largely deviates from the desired brightness. 
     SUMMARY OF THE INVENTION 
     An light emitting element driving circuit according to an aspect of the present invention, comprises: a rectifying circuit configured to output a rectified voltage obtained by providing rectification to an AC voltage; a voltage-dividing circuit configured to output as a reference voltage, a divided voltage obtained by dividing the rectified voltage; a transistor configured to increase a driving current of a light emitting element in accordance with the rectified voltage when turned on and to reduce the driving current of the light emitting element when turned off; a control circuit configured to bring the transistor to an on state or an off state at predetermined intervals and to bring the transistor to the other of the on state or the off state when a voltage according to a current flowing through the transistor increases and becomes the reference voltage; and a voltage-dividing ratio adjustment circuit configured to set a voltage-dividing ratio of the voltage dividing circuit as a first voltage-dividing ratio to reduce the reference voltage when an amplitude of the rectified voltage is larger than a predetermined amplitude and to set the voltage-dividing ratio as a second voltage-dividing ratio to increase the reference voltage when an amplitude of the rectified voltage is smaller than the predetermined amplitude. 
     Other features of the present invention will become apparent from descriptions of this specification and of the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For more thorough understanding of the present invention and advantages thereof, the following description should be read in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a diagram illustrating a configuration of an LED driving circuit  10  according to an embodiment of the present invention; 
         FIG. 2  is a diagram illustrating an example of waveforms of reference voltages Vref 1  and Vref 2 ; 
         FIG. 3  is a diagram illustrating a configuration of an oscillation circuit  90 ; 
         FIG. 4  is a diagram for explaining an operation of the LED driving circuit  10  when the amplitude of an AC voltage Vac is large; 
         FIG. 5  is a diagram for explaining the operation of the LED driving circuit  10  when the amplitude of the AC voltage Vac is small; 
         FIG. 6  is a diagram illustrating an example of a configuration of a control IC  51 ; 
         FIG. 7  is a diagram illustrating a configuration of an oscillation circuit  120 ; 
         FIG. 8  is a diagram illustrating a configuration of an oscillation circuit  140 ; 
         FIG. 9  is a diagram illustrating a configuration of an oscillation circuit  150 ; 
         FIG. 10  is a diagram for explaining an operation of the oscillation circuit  150 ; and 
         FIG. 11  is a diagram illustrating a configuration of a common LED driving circuit  200 . 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     At least the following details will become apparent from descriptions of this specification and of the accompanying drawings. 
     At least the following matters will become apparent from the description in the present specification and the drawings attached. 
       FIG. 1  is a diagram illustrating a configuration of the LED driving circuit  10  according to an embodiment of the present invention. The LED driving circuit  10  is, for example, a circuit which drives LEDs  30  to  39  on the basis of an AC voltage Vac of a commercial power supply whose amplitude fluctuates within the range of 90 to 140 V. The LED driving circuit  10  is configured to include a full-wave rectifying circuit  20 , a smoothing circuit  21 , a reference-voltage generation circuit  22 , LEDs  30  to  39 , an NMOS transistor  40 , an inductor  41 , a diode  42 , a resistor  43 , and a control IC (Integrated Circuit)  50 . 
     The full-wave rectifying circuit  20  provides full-wave rectification to the inputted AC voltage Vac and outputs rectified voltage Vrec. 
     The smoothing circuit  21  is a circuit for generating a DC voltage according to the amplitude of the rectified voltage Vrec and is configured to include resistors  60  and  61  and a capacitor  62 . The resistors  60  and  61  divide the rectified voltage Vrec, and the capacitor  62  smoothes voltage generated in the resistor  61 . Thus, DC voltage Vc 1  of a level according to the amplitude of the rectified voltage Vrec (AC voltage Vac) is generated at the capacitor  62 . 
     The reference-voltage generation circuit  22  is a circuit which generates a reference voltage Vref similar to the rectified voltage Vrec and is configured to include a voltage-dividing circuit  65 , an NMOS transistor  66 , and a capacitor  67 . The voltage-dividing circuit  65  includes resistors  70  to  72  connected in series. The rectified voltage Vrec is applied to the resistor  70  (first resistor), the resistor  71  (second resistor) is provided between the resistors  70  and  72 , and the resistor  72  (third resistor) is grounded. A source electrode of the NMOS transistor  66  (switch) is connected to one end of the resistor  71 , while a drain electrode is connected to the other end of the resistor  71 , and the capacitor  67  is connected to a gate electrode. 
     Thus, the reference voltage Vref generated at the node where the resistor  71  and the resistor  72  are connected is the voltage as represented by equation (1):
 
 V ref=( R 3/( R 1+( R 2// Rm )+ R 3))× V rec  (1)
 
     Here, resistance values of the resistors  70  to  72  are R 1  to R 3 , respectively, and resistance between the drain and the source of the NMOS transistor  66  is Rm. 
     The reference voltage Vref 1  when the NMOS transistor  66  is in the off state is as follows:
 
 V ref1=( R 3/( R 1 +R 2 +R 3))× V rec  (2)
 
     The resistance value Rm is designed to become sufficiently larger than the resistance value R 2  when the NMOS transistor  66  is in the off state. 
     On the other hand, the reference voltage Vref 2  is as follows when the NMOS transistor  66  is in the on state:
 
 V ref2=( R 3/( R 1+ R 3))× V rec  (3)
 
     The resistance value Rm is designed to become sufficiently smaller than the resistance value R 2  when the NMOS transistor  66  is in the on state. Here, a voltage-dividing ratio (R 3 :(R 1 +R 2 +R 3 )) of the voltage-dividing circuit  65  is set as voltage-dividing ratio A (first voltage-dividing ratio) when the NMOS transistor  66  is in the off state, while voltage-dividing ratio (R 3 :(R 1 +R 3 )) of the voltage-dividing circuit  65  is set as voltage-dividing ratio B (second voltage-dividing ratio) when the NMOS transistor  66  is in the on state. Factor (R 3 /(R 1 +R 2 +R 3 )) of equation (2) is set as the value of the voltage-dividing ratio A, while factor (R 3 /(R 1 +R 3 )) of equation (3) is set as the value of the voltage-dividing ratio B. Therefore, the value of the voltage-dividing ratio A is smaller than the value of the voltage-dividing ratio B. 
     As described above, the reference-voltage generation circuit  22  outputs reference voltage Vref whose level varies in accordance with the state of the NMOS transistor  66  and is similar to the rectified voltage Vrec. 
     The LEDs  30  to  39  are ten white LEDs connected in series, and rectified voltage Vrec is applied to the anode of the LED  30  and one end of the inductor  41  is connected to the cathode of the LED  39 . A forward voltage of each of the LEDs  30  to  39  is assumed to be 3 V, for example. 
     The NMOS transistor  40  controls increase/decrease of the driving current Is for driving the LEDs  30  to  39  along with the inductor  41  and the diode  42 . Specifically, when the NMOS transistor  40  is turned on when the level of the rectified voltage Vrec is higher than the sum (30 V) of all the forward voltages of the LEDs  30  to  39 , the driving current Is increases in accordance with the rectified voltage Vrec. Energy according to the current value of the driving current Is is accumulated in the inductor  41 . On the other hand, when the NMOS transistor  40  is turned off, the energy accumulated in the inductor  41  is emitted through the loop of the LEDs  30  to  39 , the inductor  41 , and the diode  42 , and the driving current Is drops. Even when the NMOS transistor  40  is turned on, the driving current Is does not flow when the level of the rectified voltage Vrec is lower than 30 V since all the LEDs  30  to  39  are in an off state. That is, the LEDs  30  to  39  emit light only when the level of the rectified voltage Vrec is higher than 30 V. 
     The resistor  43  is a resistor which detects a current value of the driving current Is when the NMOS transistor  40  is turned on and is provided between the source of the NMOS transistor  40  and the ground GND. The voltage generated at one end of the resistor  43  and of a level according to the current value of the driving current Is is set as detected voltage Vs. 
     The control IC  50  generates to the reference-voltage generation circuit  22  reference voltage Vref at a level according to the amplitude of the rectified voltage Vrec and controls switching of the NMOS transistor  40  on the basis of reference voltage Vref and detected voltage Vs. The control IC  50  is configured to include a power supply circuit  80 , a reference voltage circuit  81 , a comparator  82 , and a switching control circuit  83 . 
     The power supply circuit  80 , for example, generates power supply for operating each block in the control IC  50  when rectified voltage Vrec is inputted through the terminal not shown. 
     The reference voltage circuit  81  and the comparator  82  are charging/discharging circuits which charge/discharge the capacitor  67  in accordance with the level of voltage Vc 1  applied to the terminal DC, that is, amplitude of the rectified voltage Vrec. 
     The reference voltage circuit  81  (voltage generation circuit) generates voltage V 1  of a predetermined level VA. The predetermined level VA (first level) is a level equal to the level of the voltage Vc 1  obtained in the smoothing circuit  21  when the rectified voltage Vrec with a predetermined amplitude Vp is inputted to the smoothing circuit  21 . 
     Voltage Vc 1  is applied to an inverting input terminal of the comparator  82  through terminal DC, and voltage V 1  of the predetermined level VA is applied to a non-inverting input terminal. Thus, the comparator  82  charges the capacitor  67  through terminal SW when the level of the voltage Vc 1  is lower than the predetermined level VA, whereas the comparator  82  discharges the capacitor  67  when the level of the voltage Vc 1  is higher than the predetermined level VA. 
     For example, the level of voltage Vc 1  does not exceed the predetermined level VA when the rectified voltage Vrec smaller than predetermined amplitude Vp is continuously smoothed at the smoothing circuit  21 . In such a case, the capacitor  67  is continuously charged so that the level of the charging voltage Vc 2  of the capacitor  67  becomes higher than a predetermined level VB (second level) at which the NMOS transistor  66  is turned on. As a result, for example, reference voltage Vref 2  obtained by dividing the value of the rectified voltage Vrec with a larger voltage-dividing ratio B is outputted as the reference voltage Vref, as indicated by a solid line in  FIG. 2 . 
     On the other hand, for example, the level of voltage Vc 1  becomes higher than the predetermined level VA when the rectified voltage Vrec larger than the predetermined amplitude Vp is continuously smoothed at the smoothing circuit  21 . In such a case, the NMOS transistor  66  is turned off since the capacitor  67  is discharged. As a result, for example, reference voltage Vref 1  obtained by dividing the rectified voltage Vrec with a smaller voltage-dividing ratio A is outputted as the reference voltage Vref, as indicated by a one-dot-chain line in  FIG. 2 . 
     As described above, the control IC  50  adjusts the voltage-dividing ratio of the voltage dividing circuit  65  so that the reference voltage Vref drops when the AC voltage Vac with large amplitude is continuously inputted, while the reference voltage Vref increases when the AC voltage Vac with small amplitude is continuously inputted. Therefore, the level of the reference voltage Vref is suppressed from varying largely even when the amplitude of the AC voltage Vac largely fluctuates in the LED driving circuit  10 . 
     The reference voltage circuit  81 , the comparator  82 , the NMOS transistor  66 , and the capacitor  67  correspond to a voltage dividing ratio adjustment circuit which adjusts the voltage-dividing ratio of the voltage dividing circuit  65 . 
     The switching control circuit  83  (control circuit) is a circuit which controls switching of the NMOS transistor  40  so that the waveform of the driving current Is becomes similar to the waveform of the reference voltage Vref and is configured to include an oscillation circuit  90 , a comparator  91 , an SR flip-flop  92 , and a driving circuit  93 . 
     The oscillation circuit (OSC)  90  outputs an oscillation signal Vosc with a predetermined cycle, and the comparator  91  compares the reference voltage Vref inputted through terminal RIN with the detected voltage Vs inputted through terminal CS. The cycle of the oscillation signal Vosc is assumed to be approximately 100 kHz, for example, and to be sufficiently shorter than the cycle of the AC voltage Vac (50 Hz, for example). 
     Moreover, the oscillation circuit  90  is configured to include, for example, resistors  100  to  102 , NMOS transistors  103  to  105 , a PMOS transistor  106 , bias current sources  107  and  108 , a capacitor  109 , a comparator  110 , and an inverter  111  as illustrated in  FIG. 3 . 
     When the NMOS transistors  103  and  104  are turned on, they apply voltages VH and VL (&lt;VH) to the inverting input terminals of the comparator  110 . The NMOS transistor  105 , the PMOS transistor  106 , and the bias current sources  107  and  108  charge/discharge the capacitor  109  on the basis of an output of the comparator  110 . 
     First, when the oscillation signal Vosc being an output of the comparator  110  becomes high level (hereinafter referred to as H level), the NMOS transistor  104  is turned on, while the NMOS transistor  103  is turned off. Thus, voltage VL is applied to the inverting input terminal of the comparator  110 . Moreover, since the NMOS transistor  105  is turned on, the capacitor  109  is discharged by a current generated by the bias current source  108 . Then, when the charging voltage of the capacitor  109  (voltage of a non-inverting input terminal of the comparator  110 ) becomes lower than the voltage VL, the comparator  110  changes the oscillation signal Vosc to a low level (hereinafter referred to as L level). 
     Subsequently, when the oscillation signal Vosc becomes L level, the NMOS transistor  104  is turned off, and the NMOS transistor  103  turned on. Thus, the voltage VH is applied to the inverting input terminal of the comparator  110 . Moreover, since the PMOS transistor  106  is turned on, the capacitor  109  is charged by a current generated by the bias current source  107 . When the charging voltage of the capacitor  109  (voltage of the non-inverting input terminal of the comparator  110 ) becomes higher than voltage VH, the comparator  110  changes the oscillation signal Vosc to H level. By repeating such operations, the oscillation circuit  90  outputs the oscillation signal Vosc (clock signal) with a predetermined cycle. 
     The oscillation signal Vosc is inputted to the S input of the SR flip-flop  92 , and the comparison result of the comparator  91  is inputted to the R input. Thus, the Q output of the SR flip-flop  92  becomes H level at predetermined intervals when the oscillation signal Vosc becomes H level and the Q output becomes L level when the detected voltage Vs increases and becomes the reference voltage Vref. 
     The driving circuit  93  turns on the NMOS transistor  40  through a terminal OUT when the Q output of the SR flip-flow  92  becomes H level and turns off the NMOS transistor  40  when the Q output of the SR flip-flop  92  becomes L level. Therefore, the driving circuit  93  turns on the NMOS transistor  40  at predetermined intervals and turns off the NMOS transistor  40  when the detected voltage Vs according to a peak current of the driving current Is becomes the reference voltage Vref. As a result, the waveform of the driving current Is becomes similar to the waveform of the reference voltage Vref. 
     &lt;&lt;Operation of LED Driving Circuit  10  (Amplitude of Rectified Voltage Vrec&gt;Predetermined Amplitude Vp)&gt;&gt; 
     Here, with reference to  FIG. 4 , description will be given of an operation at the start of the LED driving circuit  10  when AC voltage Vac with large amplitude is inputted, that is, when rectified voltage Vrec with an amplitude larger than the predetermined amplitude Vp is generated. The capacitors  62  and  67  are assumed to be discharged and the voltage Vc 1  and the charging voltage Vc 2  are both assumed to be 0 V before the LED driving circuit  10  is started. Here, the time period since a rectified voltage Vrec with a predetermined amplitude Vp is applied to the smoothing circuit  21  until the level of voltage Vc 1  of the discharged capacitor  62  becomes the predetermined level VA is set as period TA, and that until the level of charging voltage Vc 2  of the discharged capacitor  67  becomes the predetermined level VB is set as period TB. It is also assumed that a current value of a source current of the comparator  82 , for example, is designed so that period TB (second period) is longer than period TA (first period) in the present embodiment. In  FIG. 4 , the waveform of the rectified voltage Vrec with a predetermined amplitude Vp and a rising waveform of the voltage Vc 1  when the rectified voltage Vrec with a predetermined amplitude Vp is applied are illustrated for the sake of convenience. 
     First, when the AC voltage Vac is inputted at time t 0 , rectified voltage Vrec according to AC voltage Vac is generated raising the voltage Vc 1  from 0 V. Here, since the level of voltage Vc 1  is lower than the predetermined level VA of voltage V 1 , the capacitor  67  is charged by the comparator  82 , and the charging voltage Vc 2  is also raised from 0 V. During this period, the NMOS transistor  66  is in the off state since the level of the charging voltage Vc 2  is lower than the predetermined level VB. Therefore, reference voltage Vref 1  is outputted as the reference voltage Vref. 
     The rectified voltage Vrec with amplitude larger than the predetermined amplitude Vp is applied to the smoothing circuit  21  at time t 0 . Thus, the voltage Vc 1  increases slightly faster than a case in which the rectified voltage Vrec with predetermined amplitude Vp is applied to the smoothing circuit  21  (waveform indicated by alternate long and short dashed line in  FIG. 4 ). Therefore, the level of voltage Vc 1  becomes the predetermined level VA at time t 1  earlier than time t 2  after period TA has elapsed since time t 0 . 
     The capacitor  67  is discharged at time t 1 , and thus charging voltage Vc 2  drops at time t 1  and thereafter. As described above, the level of charging voltage Vc 2  never exceeds the predetermined level VB when AC voltage Vac with large amplitude is inputted. Therefore, the reference voltage Vref 1  is constantly outputted as the reference voltage Vref. 
     &lt;&lt;Operation of LED Driving Circuit  10  (Amplitude of Rectified Voltage Vrec&lt;Predetermined Amplitude Vp)&gt;&gt; 
     Description will follow of an operation for starting the LED driving circuit  10  when AC voltage Vac with a small amplitude is inputted, that is, when rectified voltage Vrec with an amplitude smaller than the predetermined amplitude Vp is generated with reference to  FIG. 5 . Similar to  FIG. 4 ,  FIG. 5  also illustrates the waveform of the rectified voltage Vrec with predetermined amplitude Vp, and the rising waveform of voltage Vc 1  when the rectified voltage Vrec with predetermined amplitude Vp is applied for the sake of convenience. 
     First, when the AC voltage Vac is inputted at time t 10 , rectified voltage Vrec according to AC voltage Vac is generated raising the voltage Vc 1  from 0 V. Moreover, since the level of voltage Vc 1  is lower than the predetermined level VA of voltage V 1 , the charging voltage Vc 2  is also raised from 0 V. During this period, since the level of charging voltage Vc 2  is lower than predetermined level VB, reference voltage Vref 1  is outputted as the reference voltage Vref. 
     Subsequently, the voltage Vc 1  stops rising at time t 11  when the level of the voltage Vc 1  becomes level Vc obtained when the inputted rectified voltage Vrec was smoothed. At time t 11  and thereafter, the capacitor  67  is continuously charged since the level of voltage Vc 1  is lower than the level of voltage VA. Therefore, the level of charging voltage Vc 2  gradually increases. 
     At time t 12  after time period TB has elapsed since time t 10 , the level of charging voltage Vc 2  becomes the predetermined level VB. As a result, the NMOS transistor  66  is turned on to output reference voltage Vref 2  as the reference voltage Vref. Time t 13  in  FIG. 5  is the time after period TA has elapsed since time t 10 . Thus, time t 10  and time t 13  in  FIG. 5  correspond to time t 0  and time t 2  in  FIG. 4 , respectively. 
     As described above, when AC voltage Vac with small amplitude is inputted, the voltage-dividing ratio of the voltage dividing circuit  65  is adjusted so that the reference voltage Vref becomes high accordingly. On the other hand, as described with reference to  FIG. 4 , the voltage-dividing ratio of the voltage-dividing circuit  65  is adjusted so that the rise of the reference voltage Vref is suppressed when AC voltage Vac with large amplitude is inputted. Therefore, in the LED driving circuit  10 , the level of the reference voltage Vref can be suppressed from varying largely even when the amplitude of AC voltage Vac largely fluctuates. As a result, the LED driving circuit  10  can keep substantially constant the current value of the driving current Is of the LEDs  30  to  39  regardless of the amplitude of the AC voltage Vac. That is, the LED driving circuit  10  can make the LEDs  30  to  39  emit light at desired brightnesses. 
     Another Embodiment of the Control IC 
       FIG. 6  is a diagram illustrating another embodiment of the control IC. When comparing control IC  51  with the control IC  50  illustrated in  FIG. 1 , the two are similar except that an inverter  190  is provided in place of reference voltage circuit  81  and comparator  82 . Note that, similar blocks are designated with similar reference numerals in  FIGS. 1 and 6 . 
     The inverter  190  (charging/discharging circuit) outputs a signal at L level to the terminal SW when the level of voltage Vc 1  applied to the terminal DC is higher than the predetermined level VA and outputs a signal at H level to the terminal SW when the level of voltage Vc 1  is lower than the predetermined level VA. As described above, even when using an inverter  190  with the predetermined level VA as the threshold value, the capacitor  67  can be charged/discharged similar to the above-described comparator  82 . Therefore, even when control IC  51  is used instead of control IC  50  for the LED driving circuit  10 , the variation in the driving current Is, for example, can be suppressed similar to the case where the control IC  50  is used. 
     Another Embodiment of the Oscillation Circuit 
     Here, another embodiment of the oscillation circuit will be described with reference to  FIGS. 7 to 9 . In  FIGS. 7 to 9 , blocks similar to those in  FIG. 1  are designated with same reference numerals. Moreover, blocks such as the reference voltage generation circuit  22 , the comparator  82  and the like are omitted as appropriate in  FIGS. 7 to 9 . 
     &lt;&lt;Oscillation Circuit  120 &gt;&gt; 
       FIG. 7  is a diagram illustrating an example of an oscillation circuit  120  which controls to maintain constant the OFF time of the NMOS transistor  40 . The oscillation circuit  120  is provided in a control IC  55  and is configured to include a PMOS transistor  130 , a capacitor  131 , a bias current source  132 , a comparator  133 , an inverter  134 , and an SR flip-flop  92 . 
     When the oscillation signal Vosc of the comparator  133  becomes H level, for example, the Q output of the SR flip-flop  92  also becomes H level and the NMOS transistor  40  is turned on. At this time, since the PMOS transistor  130  is turned on, the level of the charging voltage of the capacitor  131  becomes the level of a bias voltage Vbi 1 . Then, when current Is increases and the voltage Vs becomes the reference voltage Vref, the SR flip-flop  92  is reset, and the Q output becomes H level. At this time, since the PMOS transistor  130  is turned off, the capacitor  131  is discharged by a current (constant current) of the bias current source  132 . And when the charging voltage of the capacitor  131  becomes lower than the bias voltage Vbi 2 , the comparator  133  changes the oscillation signal Vosc to H level again. Note that, time since the discharge of the capacitor  131  is started until when the level of the charging voltage becomes the level of the voltage Vbi 2 , that is, time since the NMOS transistor  40  is turned off until the NMOS transistor  40  is turned on is constant. Therefore, the OFF time of the NMOS transistor  40  is controlled to remain constant. On the other hand, the time while the NMOS transistor  40  is turned on varies in accordance with the level of the reference voltage Vref, for example. However, the time while the NMOS transistor  40  is turned on is determined in advance in accordance with the level of the reference voltage Vref. Thus, the driving circuit  93  switches the NMOS transistor  40  at intervals determined in advance, that is, at predetermined intervals in accordance with the level of the reference voltage Vref. 
     &lt;&lt;Oscillation Circuit  140 &gt;&gt; 
       FIG. 8  is a diagram illustrating an example of an oscillation circuit  140  which controls to maintain constant the ON time of the NMOS transistor  40 . The oscillation circuit  140  is provided in a control IC  56  and is configured to include a PMOS transistor  130 , a capacitor  131 , a bias current source  132 , a comparator  133 , and a SR flip-flop  92 . Here, voltage Vs is applied to the inverting input terminal of the comparator  91 , and reference voltage Vref is applied to the non-inverting input terminal of the comparator  91 . 
     In the oscillation circuit  140 , the oscillation signal Vosc from the comparator  133  is inputted to the R input reset) of the SR flip-flop  92 , and an output of the comparator  91  is inputted to the S input of the SR flip-flop  92 . And the Q output of the SR flip-flop  92  is applied to the gate of the PMOS transistor  130 . 
     First, when the NMOS transistor  40  is turned off, the current Is drops. When the voltage Vs drops to the reference voltage Vref, the Q output of the SR flip-flop  92  becomes H level to turn on the NMOS transistor  40 . Moreover, when the Q output of the SR flip-flop  92  becomes H level, the PROS transistor  130  is turned off, and thus, the discharge of the capacitor  131  is started. When the level of the charging voltage of the capacitor  131  becomes the level of the bias voltage Vbi 2 , the SR flip-flop  92  is reset so to turn off the NMOS transistor  40 . 
     The time since the discharge of the capacitor  131  had been started until the level of the charging voltage becomes the level of the voltage Vbi 2 , that is, time from the NMOS transistor  40  is turned on until the NMOS transistor  40  is turned off remains constant. Therefore, the ON time of the NMOS transistor  40  is controlled to remain constant. On the other hand, the time during which the NMOS transistor  40  is turned off changes, for example, in accordance with the level of the reference voltage Vref. However, the time during which the NMOS transistor  40  is turned off is predetermined in accordance with the level of the reference voltage Vref. Thus, the driving circuit  93  switches the NMOS transistor  40  at intervals determined in advance in accordance with the level of the reference voltage Vref, that is, at predetermined intervals. 
     &lt;&lt;Oscillation Circuit  150 &gt;&gt; 
       FIG. 9  is a diagram illustrating an example of a so-called pseudo-resonance oscillation circuit  150 . The oscillation circuit  150  is provided in a control IC  57  and is configured to include resistors  160  and  161 , a comparator  162 , an AND circuit  163 , an inverter  164 , and a diode  165 . And a transformer  170  is provided outside the control IC  57 . The transformer  170  includes a primary coil L 1  and a secondary coil L 2 , and the primary coil L 1  is insulated from the secondary coil L 2 . The primary coil L 1  is provided in place of the inductor  41  in  FIG. 1 , and the primary coil L 1  and the secondary coil L 2  are electromagnetically coupled with each other&#39;s polarities reversed (negative coupling). 
     Here, an operation of the oscillation circuit  150  in  FIG. 9  will be described with reference to the timing chart in  FIG. 10 . First, the NMOS transistor  40  is turned on when a driving signal Vdr outputted from the driving circuit  93  becomes H level at time t 50 . Thereafter, the SR flip-flop  92  is reset when the voltage Vs increases in accordance with an increase in current Is and becomes higher than the reference voltage Vref at time t 51 . As a result, the NMOS transistor  40  is turned off. Moreover, voltage Vtr of terminal TR to which the secondary coil L 2  is connected increases and exceeds voltage Vbi 3  when the NMOS transistor  40  is turned off since the primary coil L 1  and the secondary coil L 2  are electromagnetically coupled with each other&#39;s polarities reversed. Thereafter, the output of the comparator  162  and the oscillation signal Vosc which is an output of the AND circuit  163  become H level when energy accumulated in the secondary coil L 2  is emitted to lower voltage Vtr below voltage Vbi 3  at time t 52 . Thus, the NMOS transistor  40  is turned on again at time t 52 . As described above, the oscillation circuit  150  turns on the NMOS transistor  40  at predetermined intervals determined between time t 50  and time t 52 . 
     The LED driving circuit  10  of the present embodiment has been described above. When the amplitude of the rectified voltage Vrec is smaller than the predetermined amplitude Vp in the LED driving circuit  10 , the voltage obtained by dividing the value of the rectified voltage Vrec by the voltage-dividing ratio B with a large value becomes the reference voltage Vref. Moreover, when the amplitude of the rectified voltage Vrec is larger than the predetermined amplitude Vp, the voltage obtained by dividing the value of the rectified voltage Vrec by the voltage-dividing ratio A with a small value becomes the reference voltage Vref. Therefore, variation in the current value of the driving current Is of each of the LEDs  30  to  39  can be suppressed since the level of the reference voltage Vref does not vary largely even when the amplitude of the AC voltage Vac largely fluctuates. 
     Moreover, in the LED driving circuit  10 , it is not until time period TB longer than time period TA has elapsed since start that the NMOS transistor  66  is turned on. That is, reference voltage Vref 1  obtained by dividing the rectified voltage Vrec by the voltage-dividing ratio A is constantly outputted regardless of the amplitude of the AC voltage Vac at start. Therefore, a large current would not flow through the LEDs  30  to  39  realizing a so-called soft start function in the LED driving circuit  10 . 
     The capacitor  67  can be reliably discharged when the level of the voltage Vc 1  becomes the predetermined level VA by using the comparator  82 . 
     Moreover, for example, the number of elements can be reduced when configuring the capacitor  67  to charge/discharge using the inverter  190 . 
     The level of the reference voltage Vref having a shape similar to the rectified voltage Vrec can be varied with a simple configuration by adjusting the voltage-dividing ratio of the voltage-dividing circuit  65  to which the rectified voltage Vrec is applied. 
     In the LED driving circuit  10 , a non-insulating type circuit configuration was formed with the LEDs  30  to  39  connected to the inductor  41 , however, the configuration is not limited to such. An effect similar to the present embodiment can be achieved, for example, when a circuit (an insulated-type circuit) in which energy generated when switching the NMOS transistor  40  is supplied to the LED through the transducer (not shown). 
     A transmission gate or the like may be used instead of the NMOS transistor  66 , for example. 
     When the amplitude of the AC voltage Vac fluctuates within the range of, for example, 90 to 140 V the predetermined level VA may be set at a level higher than the level of the voltage Vc 1  when the amplitude of the rectified voltage Vrec becomes 140V. In such a case, a soft start is reliably realized similar to the case illustrated in  FIG. 5 . 
     The switching control circuit  83  switches the NMOS transistor  40  on the basis of an oscillation signal Vosc of the oscillation circuit  90  and the like, for example. 
     The above embodiments of the present invention are simply for facilitating the understanding of the present invention and are not in any way to be construed as limiting the present invention. The present invention may variously be changed or altered without departing from its spirit and encompass equivalents thereof. 
     Although a full-wave rectifying circuit is used in an embodiment of the present invention, a half-wave rectifying circuit may also be used.