Abstract:
Memory device systems, systems and methods are disclosed, such as those involving a plurality of stacked memory device dice and a logic die connected to each other through a plurality of conductors. The logic die serves, for example, as a memory interface device to a memory access device, such as a processor. The logic die can include a command register that allows selective operation in either of two modes. In a direct mode, conventional command signals as well as row and column address signals are applied to the logic die, and the logic die can essentially couple these signals directly to the memory device dice. In an indirect mode, a packet containing a command and a composite address are applied to the logic die, and the logic die can decode the command and composite address to apply conventional command signals as well as row and column address signals to the memory device dice.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is a continuation of U.S. patent application Ser. No. 12/166,871, filed Jul. 2, 2008. This application is incorporated by reference herein in its entirety and for all purposes. 
     
    
     TECHNICAL FIELD 
       [0002]    Embodiments of the invention relate to memory devices, and, more particularly, in one or more embodiments to a memory device that can be operated in either a direct mode, in which conventional memory control signals are coupled to the memory devices, or an indirect mode, in which command packets are coupled to the memory devices. 
       BACKGROUND OF THE INVENTION 
       [0003]    As memory devices of all types have evolved, continuous strides have been made in improving their performance in a variety of respects. For example, the storage capacity of memory devices has continued to increase at geometric proportions. This increased capacity, coupled with the geometrically higher operating speeds of electronic systems containing memory devices, has made high memory device bandwidth ever more critical. One application in which memory devices, such as dynamic random access memory (“DRAM”) devices, require a higher bandwidth is their use as system memory in computer systems. As the operating speed of processors has increased, processors are able to read and write data at correspondingly higher speeds. Yet conventional DRAM devices often do not have the bandwidth to read and write data at these higher speeds, thereby slowing the performance of conventional computer systems. This problem is exacerbated by the trend toward multi-core processors and multiple processor computer systems. It is currently estimated that computer systems operating as high-end servers are idle as many as 3 out of every 4 clock cycles because of the limited data bandwidth of system memory devices. In fact, the limited bandwidth of DRAM devices operating as system memory can reduce the performance of computer systems to as low as 10% of the performance of which they would otherwise be capable. 
         [0004]    Various attempts have been made to increase the data bandwidth of memory devices. For example, wider internal data buses have been used to transfer data to and from arrays with a higher bandwidth. However, doing so usually requires that write data be serialized and read data deserialized at the memory device interface. Another approach has been to simply scale up the size of memory devices or conversely shrink their feature sizes, but, for a variety of reasons, scaling has been incapable of keeping up with the geometric increase in the demand for higher data bandwidths. 
         [0005]    More recently, proposals have also been made to stack several integrated circuit memory devices in the same package, but doing so threatens to create a large number of other problems to be overcome. These problems can be solved to a large extent by connecting the stack of interconnected memory devices to a logic die on which the memory devices are stacked. The logic die can then serve as a high-speed interface to the memory devices. However, taking advantage of the increased capabilities of this arrangement is more easily achieved if memory command and address signals are placed in a packet and coupled to the logic die through a high-speed bus. Yet many computer and other systems are designed to interface with memory devices using conventional memory command signals and conventional row and column address signals. Advanced memory systems formed by stacking memory devices on a logic die would therefore be unusable with such systems. However, memory device manufacturers generally desire to standardize their product offerings to the greatest extent possible to lessen the number of different memory devices that are manufactured, marketed, etc. 
         [0006]    Therefore, a need exists for a method and system to allow advanced memory system formed by stacking interconnected memory device dice to be interfaced with systems by either using conventional memory commands and addresses or by using packets containing commands and addresses. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]      FIG. 1  is a block diagram of a computer system that includes a dual mode memory system according to an embodiment of the invention. 
           [0008]      FIG. 2  is a block diagram of a dual mode memory system according to an embodiment of the invention. 
           [0009]      FIG. 3  is a more detailed block diagram of a dual mode memory system according to an embodiment of the invention. 
           [0010]      FIG. 4  is a packet diagram showing the format of a downstream packet that can be coupled to the memory system of  FIG. 1 ,  2  or  3  or a memory system according to some other embodiment of the invention for the indirect operating mode. 
           [0011]      FIG. 5  is a chart showing how the commands in the first field of the downstream packet of  FIG. 4  are modified for the direct operating mode. 
           [0012]      FIG. 6  is a chart showing the commands in the downstream packet of 
           [0013]      FIG. 4  for the indirect operating mode. 
           [0014]      FIG. 7  is a packet diagram showing the format of an upstream packet that can be coupled from the memory system of  FIG. 1 ,  2  or  3  or a memory system according to some other embodiment of the invention. 
           [0015]      FIG. 8  is a chart showing the commands in the upstream packet of  FIG. 7  for the indirect operating mode. 
       
    
    
     DETAILED DESCRIPTION 
       [0016]    A computer system including a high-capacity, high bandwidth memory device  10  according to an embodiment of the invention is shown in  FIG. 1  connected to a processor  12  through a relatively narrow high-speed bus  14  that may be divided into downstream lanes and separate upstream lanes (not shown in  FIG. 1 ). The memory device  10  includes 4 DRAM die  20 ,  22 ,  24 ,  26 , which may be identical to each other, stacked on top of each other. Although the memory device  10  includes  4  DRAM die  20 ,  22 ,  24 ,  26 , other embodiments of the memory device use a greater or lesser number of DRAM die. The DRAM die  20 ,  22 ,  24 ,  26  are stacked with (e.g., on top of) a logic die  30 , which serves as the interface with the processor  12 . The logic die  30  can implement a variety of functions in the memory device  10 , such as to limit the number of functions that are be implemented in the DRAM die  20 ,  22 ,  24 ,  26 . For example, the logic die  30  may perform memory management functions, such as power management and refresh of memory cells in the DRAM die  20 ,  22 ,  24 ,  26 . In some embodiments, the logic die  30  may implement test and/or repair capabilities, and it may perform error checking and correcting (“ECC”) functions. 
         [0017]    The DRAM die  20 ,  22 ,  24 ,  26  are connected to each other and to the logic die  30  by a relatively wide bus  34 . The bus  34  may be implemented with through silicon vias (“TSVs”), which comprise a large number of conductors extending through the DRAM die  20 ,  22 ,  24 ,  26  at the same locations on the DRAM die and connect to respective conductors formed on the die  20 ,  22 ,  24 ,  26 . In one embodiment, each of the DRAM die  20 ,  22 ,  24 ,  26  are divided into 16 autonomous partitions, each of which may contain 2 or 4 independent memory banks. In such case, the partitions of each die  20 ,  22 ,  24 ,  26  that are stacked on top of each other may be independently accessed for read and write operations. Each set of 16 stacked partitions may be referred to as a “vault.” Thus, the memory device  10  may contain 16 vaults. 
         [0018]    As shown in  FIG. 2 , in one embodiment, the bus  34  may be divided into 16 36-bit bi-directional sub-buses  38   a - p , with each of the 16 36-bit sub-buses coupled to the 4 partitions in a respective vault. Each of these sub-buses couples  32  bits of a data and 4 ECC bits between the logic die  30  and the DRAM die  20 ,  22 ,  24 ,  26 . However, the number of stacked DRAM die  20 ,  22 ,  24 ,  26 , the number of partitions in each DRAM die, the number of banks in each partition, and the number of bits in each of the sub-buses  38   a - p  can vary as desired. The relatively narrow high-speed bus  14  connecting the processor  12  to the logic die may be divided into 4 16-bit downstream lanes  40   a - d  and 4 separate 16-bit upstream lanes  42   a - d . The 4 downstream lanes  40   a - d  may be connected to a single processor  12  as shown in  FIG. 1 , which may be a multi-core processor, to multiple processors (not shown), or to some other memory access device like a memory controller. The 4 downstream lanes  40   a - d  may operate independently of each other so that packets (in the indirect mode) or memory command, address, and data signals (in the direct mode) are coupled through the lanes  40   a - d  at different times and to the same or different vaults. 
         [0019]    As explained in greater detail below, one of the functions performed by the logic die  30  can be to serialize the read data bits coupled from the DRAM die  20 ,  22 ,  24 ,  26  into a serial stream of 16 serial data bits coupled through  16  parallel bits of each upstream lane  42   a - d  of the bus  14 . Similarly, the logic die  30  may perform the functions of deserializing  16  serial data bits coupled through one of the 16-bit downstream lanes  40   a - d  of the bus  14  to obtain 256 parallel data bits. The logic die  30  then couples these 256 bits through one of the 32-bit sub-buses  38   a - p  in a serial stream of 8 bits. However, other embodiments may use different numbers of lanes  40 ,  42  having different widths or different numbers of sub-buses  38   a - p  having different widths, and they may couple data bits having different structures. As will be appreciated by one skilled in the art, the stacking of multiple DRAM die results in a memory device having a very large capacity. Further, the use of a very wide bus connecting the DRAM die allows data to be coupled to and from the DRAM die with a very high bandwidth. 
         [0020]    A logic die  30  according to an embodiment of the invention is shown in  FIG. 3  connected to the processor  12  and the DRAM die  20 ,  22 ,  24 ,  26 . As shown in  FIG. 3 , each of the 4 downstream lanes  40   a - d  may be connected to a respective link interface  50   a - d . Each link interface  50   a - d  includes a deserializer  54  that converts each serial stream of 16 data bits on each of the 16-bit lanes  40   a - d  to 256 parallel bits. Insofar as there are 4 link interfaces  50   a - d , the link interfaces can together output  1024  output parallel bits. 
         [0021]    Each of the link interfaces  50   a - d  applies its 256 parallel bits to a respective downstream target  60   a - d , which decodes the command and address portions of the received packet (in the indirect mode) or the commands and addresses (in the direct mode) and buffers write data in the event a memory request is for a write operation. The downstream targets  60   a - d  output their respective commands, addresses and possibly write data to a switch  62 . The switch  62  contains 16 multiplexers  64  each of which direct the command, addresses and any write data from any of the downstream targets  60   a - d  to its respective vault of the DRAM die  20 ,  22 ,  24 ,  26 . Thus, each of the downstream targets  60   a - d  can access any of the 16 vaults in the DRAM die  20 ,  22 ,  24 ,  26 . The multiplexers  64  use the address in the received memory requests to determine if its respective vault is the target of a memory request. Each of the multiplexers  64  apply the memory request to a respective one of 16 vault controllers  70   a - p . 
         [0022]    Each vault controller  70   a - p  includes a respective memory controller  80 , each of which includes a write buffer  82 , a read buffer  84  and a command pipeline  86 . The commands and addresses in memory requests received from the switch  62  are loaded into the command pipeline  86 , which subsequently outputs the received commands and corresponding addresses. Any write data in the memory requests are stored in the write buffer  82 . The read buffer  84  may be used to store read data from the respective vault, as will be explained in greater detail below. The write data from the write buffer  82  are applied to a memory interface  88 . 
         [0023]    According to an embodiment of the invention, the commands and addresses from the command pipeline  86  are applied to a memory interface  88  through a command processing circuit, such as a command register  90 . The command register  90  can be a free running interface register. In the direct mode, the commands and addresses from the command pipeline are applied to the memory interface  88 . These commands and addressed may be applied to the memory interface  88  as they are received by the memory device  10 . In the indirect mode, the command register  90  creates the commands and addresses and sends it to the memory interface  88 . The command register  90  includes a sequencer (not shown) that transmits the commands and addresses to the memory interface in the proper order and at the proper times. 
         [0024]    The memory interface  88  couples the received command and address signals from the command register  90  to the DRAM die  20 ,  22 ,  24 ,  26  through a command/address bus  92 . The memory interface  88  also couples 32-bits of write data from the write buffer  82 . In some embodiments, the memory interface  88  may include an ECC system (not shown), which uses ECC techniques to check and correct the data read from the DRAM die  20 ,  22 ,  24 ,  26 . In such case, in addition to coupling write data to the DRAM die  20 ,  22 ,  24 ,  26 , the memory interface  88  couples 4 bits of ECC from the ECC system to the DRAM die  20 ,  22 ,  24 ,  26  through a 36-bit data bus  94 . 
         [0025]    Although write data are loaded into the write buffer  82  as 256 parallel bits, they are output from the buffer  82  in two sets, each set being 128 parallel bits. These 128 bits may then be further serialized by the ECC system (not shown) to 4 sets of 32-bit data, which are coupled through the data bus  94 . In the embodiment shown in  FIG. 3 , write data are coupled to the write buffer  82  in synchronism with a 500 MHz clock so the data are stored in the write buffer at 16 gigabytes (“GB”) per second. The write data are coupled from the write buffer  82  to the DRAM die  20 ,  22 ,  24 ,  26  using a 2 GHz clock so the data are output from the write buffer  82  at 8 GB/s. Therefore, as long as more than half of the memory requests are not write operations to the same vault, the write buffers  82  will be able to couple the write data to the DRAM die  20 ,  22 ,  24 ,  26  at least as fast as the data are coupled to the write buffer  82 . 
         [0026]    In the event a memory request is for a read operation, the command and address for the request are coupled to the DRAM die  20 ,  22 ,  24 ,  26  in the same manner as a write request, as explained above. In response to a read request, 32 bits of read data and 4 ECC bits are output from the DRAM die  20 ,  22 ,  24 ,  26  through the 36-bit data bus  94 . The ECC bits are passed to the ECC system (not shown), which uses the ECC bits to check and correct the read data before passing the read data on to the read buffer  84 . The ECC system also deserializes the 32 bits of read data into two sets of 128-bit read data. However, in some embodiments, the memory system does not include the ECC system. 
         [0027]    After 2 sets of 128-bit read data have been stored in the read buffer  84 , the read buffer transmits 256 bits to the switch  62 . The switch includes 4 output multiplexers  104  coupled to respective upstream masters  110   a - d . Each multiplexer  104  can couple 256 bits of parallel data from any one of the vault controllers  70   a - p  to its respective upstream master  110   a - d . The upstream masters  110   a - d  format the 256 bits of read data into packet data (in the indirect mode) and couple the packet to respective upstream link interfaces  114   a - d . In the direct mode, the read data are simply coupled to respective upstream link interfaces  114   a - d . Each of the link interfaces  114   a - d  include a respective serializer  120  that converts the incoming 256 bits to a serial stream of 16 bits on each bit of a respective one of the 16-bit upstream links  42   a - d.    
         [0028]    The format of a downstream packet  150  that can be coupled to the memory system of  FIG. 1 ,  2  or  3  or a memory system according to some other embodiment of the invention is shown in  FIG. 4 . The downstream packet  150  may be, as explained above, 32 bits wide, and it contains a first field  152 . In the indirect operating mode, the first field  152  includes a 4-bit command  156  (“Cmd  3 : 0 ”), and 28 bits of an upper address  158  (“UAddress”). The nature of the command  156  and upper address  158  will be described in connection with  FIG. 6 . 
         [0029]    As shown in  FIG. 5 , in the direct mode, the first field  152  of the downstream packet  150  may be modified to allow a memory access device to directly access the DRAM die  20 ,  22 ,  24 ,  26 . The first bit of the first field  152  may be a row address strobe (“RAS”) signal  160 , the second bit may be a column address strobe (“CAS”) signal  162  and the third bit may be a write enable (“WE”) signal  164 . The first field  152  also includes a 4-bit column address  166  and a 14-bit row address  168 . Finally, the first field  152  includes a four bit vault address  170 . The vault address  170  specifies which of the 16 vaults are being accessed. 
         [0030]    Returning to  FIG. 4 , the downstream packet  150  also contains a second field  180 , which may be used in the indirect operating mode. The second field  180  contains a first group of 8 bits  182  that include 3-bit command extension (“Cmd Ext”) and 5 bits of a lower address (“LAddress”). As subsequently explained, the Cmd Ext bits  182  are used to further define commands designated by the four command bits  156 . The next eight bits  184  of the second field  180  are reserved. The next eight bits  186  include 2 reserved bits (“RSV”) and 6 header error checking and correcting bits (“HCRC”), which allow errors in the first field  152  to be detected and possibly corrected. A final eight bits  188  of the second field  180  are tag bits (“Tag”) which uniquely identifies each memory request. As explained in greater detail below, these Tag bits  188  are included in upstream packets containing read data so that the memory request to which the read data corresponds can be identified, for example. Also, including these Tag bits  188  in an upstream packet for a write allows the writing of data to be acknowledged in an upstream packet, as will be subsequently explained. 
         [0031]    The downstream packet  150  also contains a third field  190 , which includes a mask bit  192  that specifies whether a write will be masked, and 31 bits of write data  196 . Following the third field  190  are one or more fields of write data  200 . A final field contains a set of error checking bits  210 , which may be cyclic redundancy check (“CRC”) bits, ECC bits or some other type of error checking bits. The error checking bits  210  correspond to the write data to allow the memory system to determine if there were any errors in the transmission of the write data. In the case where the error checking bits are ECC bits and the number of errors is not too great, the bits  210  may allow errors in the write data to be corrected. 
         [0032]    Potential commands corresponding to the 4 command bits  156  in the first field  152  are shown in  FIG. 6  for the indirect mode. For the direct mode, the memory commands are formed by combinations of the WE, CAD and RAS signals shown in  FIG. 5 . As shown in  FIG. 6 , Cmd “ 0000 ” is for a no operation (“NOP”) command, which does not cause the memory system  10  to perform any memory access. The command “ 0001 ” is decoded as a read command, with the number of bytes in the read being designated by the command extension bits  182 . The command “ 0100 ” is decoded as a write command, with the number of bytes being written again by the command extension bits  182 . Finally, the command “ 0101 ” is decoded as a masked write command, with the number of bytes also being written by the command extension bits  182 . The remaining commands in the Cmd bits  156  are reserved for implementing additional functions. 
         [0033]    With further reference to  FIG. 6 , the 28-bit upper address  158  and the 5-bit lower address in the bit group  182  specify the location in the memory system that is the subject of the memory request. The logic die  30  uses these address bits to route a memory request to the corresponding vault and the corresponding row and column address in that vault. As mentioned above, the command extension “Cmd Ext” in the group  182  specifies the number of bytes that are read or written for a read and write or a masked write. If the command  156  in the first field  152  was for a read, the command extensions “ 011 ” through “ 111 ” designate a read request of 8 through 128 bytes. The remaining command extensions are used for implementing additional functions. If the command  156  in the first field  152  was for a write, the command extensions “ 011 ” through “ 111 ” similarly designate a write request of 8 through 128 bytes. Finally, if the command  156  in the first field  152  was for a masked write, the command extensions “ 011 ” through “ 111 ” designate a masked write request of 8 through 128 bytes. The remaining command extensions are used for implementing additional functions. 
         [0034]    As also shown in  FIG. 6 , the 6 error checking bits “HCRC” in the group  186  detects whether the data in the first field  152  contains an error. The final 8-bit tag  188  uniquely identifies each memory request, as previously explained. 
         [0035]    The format of an upstream packet  250  is shown in  FIG. 7 . A first field  260  of the upstream packet  250  includes a 4-bit command (“Cmd 0 ”)  262 , and 2 error checking bits  264 . Next are 2 reserved bits  266  followed by the 8-bit tag  268  (“Tag 0 ”), which, as previously explained, corresponds to the tag in the downstream packet  150  to which the read data is responsive. The first field  260  also contains a second set of the above-described bits, namely a 4-bit command (“Cmd 1 ”)  272 , and 2 error checking bits  274 . These error checking bits  274 , along with the 2 error checking bits  264 , allow detection and possibly correction of errors in the 32 bits of the first field  260 . The first field  260  also contains 2 reserved bits  276 , and an 8-bit tag  278  (“Tag 1 ”). The upstream packet  250  normally does not include read data for two memory requests. However, the ability to include a second tag  278  and command  272 , etc. in the first field  260  allows a write request to be acknowledged in the same upstream packet  250  as an upstream packet containing read data and an associated tag. Following the first field  260  are one or more 32-bit fields  280  of read data and a 32-bit field  290  of error checking bits. These error checking bits allow a memory controller or other memory access device receiving the read data to check for and possibly correct any transmission errors in the read data. 
         [0036]    The commands corresponding to the Cmd bits  262 ,  272  in the upstream packet  250  are shown in  FIG. 8 . The 4-bit command “Cmd 0 ”  262  corresponds to a read if the upstream packet  250  is to contain read data. Again, the command “ 0000 ” is for a no operation “NOP” command. The next command “ 0001 ” is a naked command (“NAK”) that acknowledges a read memory request but indicates that the data could not be read because of an error. The command “ 0100 ” acknowledges a prior write request, and the command “ 0101 ” is a naked command that acknowledges a prior write request but indicates that the write data was in error. The commands “ 1011 ” through “ 1111 ” indicates the upstream packet  250  contains read data of 8, 16, 32, 64 or 128 bytes, respectively. The remaining commands of “Cmd 0 ” are reserved for implementing other features. 
         [0037]    The commands corresponding to the Cmdl bits  272  are also shown in  FIG. 8 . The command “ 0000 ” is again for a no operation “NOP” command, and the command “ 0001 ” is again a naked command (“NAK”) that acknowledges a read memory request but indicates that the data could not be read because of an error. The command “ 0100 ” acknowledges a prior write request, and the command “ 0101 ” is a naked command that acknowledges a prior write request but indicates that the write data was in error. The remaining commands of “Cmd 1 ” are reserved for implementing other features. 
         [0038]    From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. For example, although the embodiments of the invention are explained in the context of stacked DRAM die, it will be understood that the stacked die may be other types of memory device dice, such as flash memory device dice. Accordingly, the invention is not limited except as by the appended claims.