Abstract:
An RF amplifier with enhance power efficiency is disclosed. The RF amplifier traces the envelope of the input RF signal and varies the supply voltage to the final FET depending on the detected envelope through a linear power supply and a switching power supply superposed on the linear power supply. The linear power supply promptly responds the change of the envelope and gradually decreases the supply current as maintaining the supply voltage. The switching power supply takes over the supplement of the supply current to the final FET.

Description:
TECHNICAL FIELD 
     The present application relates to a radio frequency (RF) amplifier that enhances the power efficiency by implementing a switching power supply concurrently with a linear power supply. 
     BACKGROUND 
     One technique has been well known in the field to reduce the power dissipation, namely, to enhance the power efficiency, which is called as the envelope tracking technique where an RF amplifier adjusts or varies the power supply voltage depending on the envelope of an input RF signal. 
     SUMMARY 
     An aspect of the present invention relates to an amplifier that amplifies RF signals. The RF amplifier of the present invention includes a FET, a linear power supply, and a switching power supply. The FET, supplied with a supply voltage and a supply current, amplifies the input RF signals. The linear power supply provides, to the FET by receiving the source power supply, the supply voltage that traces an envelope of the input RF signals and a portion of the supply current. The switching power supply provides, to the FET by receiving the source power supply, a rest portion of the supply current. The portion of the supply current is preferably limited to the preset limit, while, the rest portion of the supply current provided from the switching power supply is an amount exceeding the preset limit. The switching power supply may be the step-up configuration and/or the step-down configuration. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention will now be described by way of example only and not in any limitative sense with reference to the accompanying drawings in which: 
         FIG. 1  shows a functional block diagram of an RF amplifier according to the first embodiment of the present invention; 
         FIG. 2  shows a circuit diagram of a final section, a linear power supply and a current detector implemented in the RF amplifier shown in  FIG. 1 ; 
         FIG. 3  shows a circuit diagram of a switching power supply with the step-up configuration implemented in the RF amplifier shown in  FIG. 1 ; 
         FIG. 4  shows a circuit diagram of another switching power supply also having the step-up configuration; 
         FIG. 5A  shows an example of an input RF signal RF IN , and  FIG. 5B  shows an envelope V ENV  of the input RF signal shown in  FIG. 5A ; 
         FIGS. 6A to 6C  show examples of the output voltage V L , the output current L L , and the power dissipation P L  of the linear power supply corresponding to the input RF signal RF IN  shown in  FIG. 5A ; 
         FIGS. 7A to 7C  show examples of the output voltage V SW  of the switching power supply, the drain level V drain  of the switching FET, the output current I SW  of the switching power supply, which is equivalent to the source current of the FET, and the power dissipation P FET  of the FET, which is substantially equal to the power dissipation of the switching power supply; 
         FIG. 8  shows a functional block diagram of an RF amplifier according to an example comparable to the embodiment of the present invention; 
         FIG. 9  shows a circuit of a switching power supply with the step-down configuration; 
         FIG. 10A  shows a behavior of the source level V source  of the FET driven by the gate driver,  FIG. 10B  shows the source current I source  output from the FET and the output current I SW  output from the inductor through the resistor, and  FIG. 10C  show power (I SW ×V SW ) provided from the switching power supply; 
         FIG. 11  shows a functional block diagram of an RF amplifier of the second embodiment of the present invention; 
         FIG. 12  is a circuit diagram of the switching power supply with the step-down configuration; and 
         FIG. 13  is a circuit diagram of still another switching power supply with the step-down configuration. 
     
    
    
     DETAILED DESCRIPTION 
     Next, some embodiments of the present invention will be described as referring to drawings. In the description of the drawings, numeral or symbols same with or similar to each other will refer to elements same with or similar to each other without duplicating explanations. 
     First Embodiment 
       FIG. 1  is a functional block diagram of an amplifier according to the first embodiment of the present invention. The amplifier  100  has the two-stage including a final section  10  and a front section  11 . Power supply of the amplifier  100  includes a switching power supply  12 , a linear power supply  14 , an envelope detector  16 , and a current detector  18  accompanied with a sensing resistor R S . A radio frequency (RF) signal RF IN  is input to the front section  11  and the envelope detector  16 . The final section  10  further amplifies an output of the front section  11  to be output as a signal RF OUT . 
     The envelope detector  16  detects an envelope of the RF input RF IN  to output an envelope signal V ENV . The linear power supply  14  generates a primary power V L  based on the envelope signal V ENV , and provides the primary power V L  to the final section  10  through the sensing resistor R S . The switching power supply  12 , which is supplied with the source power supply V CC . The switching power supply  12  is a type of, what is called, the step-up configuration, where an output voltage thereof is higher than an input voltage. In the present embodiment, the switching power supply  12  whose enhanced output V SW  is fed-back to the input, namely, the source power supply V CC  through a load, but the reference level thereof is coupled with the final section  10 . Thus, the switching power supply  12  may provide an additional current I SW  which is a sum of the current I CC  provided from the source power supply V CC  and a current I BACK  back to the source power supply V CC  from the step-up output V SW , to the final section  10  in addition to the load current I L  provided from the linear power supply  14 . 
     The current detector  18  measures a voltage drop caused by the load current I L , flowing in the sensing resistor R S , and controls the switching power supply  12  such that the load current I L  does not exceed a preset limit. That is, when the load current I L  is going to exceed the preset limit, the current detector  18  controls the switching power supply  12  to provide an additional current I SW . Then, the final section  10  is provided with a merged current, I L +I SW . 
     An amplifier with the envelope tracking function may enhance the power efficiency by varying the power supply provided to the final section  10  based on the envelope the input signal RF IN . A linear power supply  14  may follow the envelope of the input signal RF IN  but is inferior in an aspect of the power efficiency. On the other hand, a switching power supply inherently has superior power efficiency but unable to follow the envelope of the input signal. The amplifier  100  of the present embodiment, the linear power supply  14  primarily provides power to the final section  10  when the input signal RF IN  varies the envelope thereof promptly, while, the switching power supply  12  primarily provides the power to the final section  10  when the envelope of the input signal RF IN  varies moderately. Thus, the high efficiency in the power consumption may be consistent with the prompt response for the envelope of the input signal in the amplifier  100 . In a major application of the amplifier  100 , typically the application of the base station of the mobile telephone system, the envelope of the input signal RF IN  usually varies in moderate. 
       FIG. 2  shows exemplary circuits of the linear power supply  14 , the current detector  18 , and the final section  10  appearing in  FIG. 2 . The linear power supply  14  of the present embodiment provides a differential amplifier  20  and a buffer transistor  22 , which is an n-MOSFET. The linear power supply  14  of the present embodiment forms a voltage follower circuit that traces the non-inverting input of the differential amplifier  20  in the source of the transistor  22 . The transistor  22  operates as a current buffer to supply a large current I L  unable for the differential amplifier to output. 
     The current detector  18  includes two differential amplifiers,  24  and  26 , and four resistors, R 1  to R 4 . The first differential amplifier  24  amplifies a voltage signal generated in the sensing resistor R S  by the output current I L  of the liner power supply  14  flowing therein. Four resistors, R 1  to R 4 , determine the voltage gain of the first differential amplifier  24 . The second differential amplifier  26  compares the output of the first differential amplifier  24  with a reference V REF , and outputs a difference therebetween. That is, because the output of the first differential amplifier  24  corresponds to the current I L  flowing in the sensing resistor R S , the reference V REF  is equivalently equal to the preset limit current of the linear power supply  14 . The second amplifier  26  generates an excess amount of the supply current I L  from the preset limit as voltage signal V CTRL . 
     The final section  10  includes an FET type of the high electron mobility transistor (HEMT), capacitors, C 1  to C 3 , and a stub  29 . The HEMT of the present embodiment is, for instance, made of nitride semiconductor material such as gallium nitride (GaN) with a channel layer made of GaN formed on a substrate and a earner supply layer made of AlGaN provided on the channel layer. The FET  28  is grounded in the source thereof, receives in the gate thereof the input signal RF IN  amplified by the front section  11  through the coupling capacitor C 2 , and outputs the amplified signal RF OUT  from the drain thereof through another coupling capacitor C 3 . The drain of the FET  28  is also supplied with the power V D  through the bypassing capacitor C 1  and the stub  29 . 
       FIG. 3  shows a circuit diagram of the switching power supply  12 . As shown in  FIG. 3 , the switching power supply  12  of the embodiment has, what is called, the step-up configuration that includes an FET  30 , a gate driver  32 , a level shifter  34 , a pulse generator, exactly, a pulse width modulation (PWM) circuit  36 , differential amplifiers,  38  and  40 , a diode D 1 , a capacitor C 10 , an inductor L 1 , and a resistor R 10 . The FET  30  of the present embodiment is the type of the n-MOSFET, preferably, n-type power MOSFET. 
     The inductor L 1 , the FET  30  as a switching element, the diode D 1 , and the capacitor C 10  operate as the step-up switching circuit with the source power supply V CC  as the input, the cathode of the diode D 1 , namely, the non-inverting input of the differential amplifier  40  as the output V SW , and the output V D  as the reference. Specifically, when the FET  30  turns on by being driven by the gate driver, which sets the drain level of the FET substantially equal to the reference V D  and reversely biases the diode D 1 ; not only the current flows in the inductor L 1  and the FET  30  but the inductor L 1  stores energy. Subsequently, turning off the FET  30 , which shuts the current flowing in the inductor L 1  to release the energy stored therein, the output V SW  becomes the source power supply V CC  added with the energy stored in the inductor L 1 . Accordingly, the output V SW  exceeds the source power supply V CC . The capacitor C 10  is a smoothing capacitor for the output V SW . 
     The PWM circuit  36  generates a pulse signal with a variable duty ratio depending on the output of the first differential amplifier  38 . When the output of the first differential amplifier  38  becomes higher, the duty ratio of the pulse signal output from the PWM circuit increases, which enhances the output V SW . The level shifter  34  shifts the output of the PWM circuit  36  to levels adequate for driving the gate driver  32  and the FET  30 . 
     The differential amplifier  40  senses a difference between the output V SW  and the source power supply V CC , and feeds this difference back to the inverting input of the first differential amplifier  38  as a sensing signal V SENSE . The first differential amplifier  38  receives the control signal V CTRL  that corresponds to the excess amount of the output current I L  of the linear power supply  14  from the preset limit. Accordingly, the first differential amplifier  38  generates an output thereof such that the sensing signal V SENSE  becomes equal to the control signal V CTRL . Thus, the output V SW  of the switching power supply  12  is operated so as to become higher than the source power supply V CC  by the control signal V CTRL , V SW =V CC +V CTRL . 
     When the sensing signal V SENSE  lower than the control signal V CTRL , switching power supply  12  operates so as to increase the output V SW , which means that the current flowing in the transistor  30  increases. As described, the control signal V CTRL  corresponds to an excess amount of the output current I L  from the preset limit, accordingly, the switching power supply  12  compensates excess amount of the linear power supply  14 . The output current I L  of the linear power supply  14  does not exceed the present limit. 
     The switching power supply  12  thus described in  FIG. 3  has the type of, what is called, the asynchronous rectification; however, the switching power supply  12  may provide the type of the synchronous rectification. Also, the FET  30  may be a p-type FET, and/or other types of a switching element, such as a bipolar transistor and so on. 
       FIG. 4  shows another type of the step-up switching power supply  12 A having the type of the synchronous rectification. The switching power supply  12 A of  FIG. 4  provides, substituting for the diode D 1 , another n-MOSFET  44  driven by the high side circuit of the level shifter  34   a  and the gate driver  32   a . The other FET  30  is driven by the low side circuit of the level shifter  34   b  and the gate driver  32   b . Two FETs,  30  and,  44  alternately turn on/off. That is, when the FET  30  turns on to flow the current therein and store the energy in the inductor L 1 , the other FET  44  turns off to isolate the inductor L 1  from the output V SW . On the other hand, when the FET  30  is turned off, the other FET  44  is turned on to couple the inductor L 1  with the output V SW . In the synchronous switching power supply  12 A further provides a dead-time controller  46  put between the PWM circuit  36  and the level shifters,  34   a  and  34   b . The dead time controller  46  adjusts the pulse widths each provided to respective FETs,  30  and  44 , so as not to overlap, or not to turn on both FETs,  30  and  44 , at the same time. 
       FIGS. 5A and 5B  schematically illustrate the input signal RF IN  and the envelope V ENV  thereof, respectively. The input signal RF IN  has relatively small amplitude for the period T 1  until the instance t 1 , increases the amplitude thereof for the next period T 2  until the instance t 2 , further increases for the next period T 3  until t 3 , and recovers the initial amplitude for the next period T 4  until t 4 . The envelope V ENV  of the input signal RF IN  shown in  FIG. 5B , which corresponds to the amplitude of the input signal RF IN , becomes 1 V during the periods, T 1  and T 4 , 3 V during the period T 2 , and 5 V for the period T 3 , respectively. In an example shown in  FIG. 5A , the input signal RF IN  maintains the amplitude within respective periods. However, the input signal RF IN  is not restricted to those configurations; the input signal RF IN  may vary the amplitude during respective periods. 
       FIGS. 6A to 6C  schematically illustrate the output voltage V L , the output current I L , and the power P L  of the linear power supply  14 . The output voltage V L  substantially traces the envelope signal V ENV  shown in  FIG. 5B , assumes magnitudes thereof in respective periods, T 1  to T 4 , to be 10 V, 30 V, 50 V, and 10 V. An explanation below further assumes the source power supply V CC  to be 55 V. Because the linear power supply  14  promptly follows the envelope signal V ENV , the current output I L  thereof rapidly increases or decreases synchronous with the rising/falling of the output voltage V L . However, setting the preset limit of the output current of the linear power supply  14  to be relatively small, the switching power supply  12  may operate so as to compensate the excess amount of the output current I L , and the output current I L  gradually decreases to the preset limit. The output power, P L =V L ×I L , momently increases synchronous with the rising/falling of the envelope signal V ENV , but may maintain relatively small value. 
       FIGS. 7A to 7C  schematically show the drain voltage V drain , the source current I source , and the power consumption of the FET  30 , respectively. The source current I source  is substantially equal to the power consumption of the switching power supply  12 . As shown in  FIG. 7A , LOW level of the drain voltage V drain  is substantially equal to the reference level V D , namely, the output voltage of the linear power supply  14 ; that is, LOW level corresponds to the status where the FET  30  fully turns on and the drain level thereof becomes the source level which is equal to the output voltage V D  of the linear power supply  14 . While, HIGH level of the FET  30  exceeds the output V SW  because of tire energy stored in the inductor L 1  during the period the FET  30  turns on. For the periods, T 1  and T 4 , LOW level of the drain voltage V drain  is about 10 V, which is substantially equal to the output voltage of the linear power supply  14 , and the ratio of a period when the FET fully turns on (LOW) against the total period (HIGH+LOW), becomes a minimum, which means lowest energy be stored in the inductor L 1 . For the period T 2 , the low level of the drain voltage V drain  also becomes the output voltage of the linear power supply  14 , which is about 30 V, and the ratio above increases compared with that for the periods, T 1  and T 4 . For the period T 3 , the low level of the drain voltage V drain  further increases to about 50 V, which is also the output voltage V L  of the linear power supply  14 , and the ratio above becomes a maximum, which means the maximum energy be stored in the inductor L 1 . 
     As shown in  FIG. 7B , the source current I source  linearly increases for periods when the FET  30  turns on, where the slope of the linear increase depends on the inductance of the inductor L 1 . Because the period T 3  shows the maximum ratio of the period when the FET  30  tarns on against the total period, that is, the period T 3  shows a longest period when the FET  30  turns on, the final drain current becomes the maximum compared with those of other periods, T 1 , T 2 , and T 4 . The current output from the switching power supply  12  to the final section  10  corresponds to an average of the source current I source ; accordingly, the period T 3  provides a maximum current to the final section  10 ; while, the periods, T 1  and T 4 , provides a minimum current. 
     As shown in  FIG. 7C , because the switching power supply  12  is put between the source power supply V CC  and the output of the linear power supply  14 , the power consumption of the switching power supply  12 , which is equivalently equal to the power consumption P FET  of the FET  30 , is calculated by multiplying a voltage difference between the source power supply V CC  and the output V L  of the linear power supply  14  with a current flowing in the FET  30 . The current flowing in the FET  30  becomes the maximum for the period T 3  but the voltage difference becomes the minimum. Accordingly, the power consumption of the FET  30  may be kept small. Similarly, the periods, T 1  and T 4 , shows the maximum voltage difference, but the small current flowing in the FET  30 . Then the power consumption of the FET  30  is kept small. The period T 2  shows a moderate voltage difference and a moderate current flowing; accordingly, the power consumption of the FET  30  becomes a maximum. 
     Thus, the amplifier  100  of the present embodiment varies the supplying voltage V D  to the final section  10  depending on the envelope of the input RF signal RF IN . When the envelope rapidly varies, the linear power supply  14  promptly follows a change of the envelope, that is, the linear power supply  14  rapidly supplies the increased current to the final section  10 , and the switching power supply subsequently compensates a most portion of the increased current excessing the preset limit such that the linear power supply  14  reduces the output current I L . Thus, two power supplies,  12  and  14 , of the present embodiment, the linear power supply  14  provides the voltage V D , while, the switching power supply  12  provides a primary portion of the current I D . Moreover, the rapid transitions of the envelope of the input RF signal RF IN  may be followed by the linear power supply  14 . 
     Next, further enhancement of the efficiency of the amplifier according to a modification of the first embodiment will be described as comparing with a comparable example.  FIG. 8  is a functional block diagram of an amplifier according to a comparable example. The amplifier  110  includes a switching power supply  12   a  but the type of the step-down configuration. The switching power supply  12   a  converts the source power supply V CC  down to a voltage less than the source power supply V CC . The current detector  18  drives the switching power supply  12   a  such that the current I L  output from the linear power supply  14  does not exceed the preset limit. Other arrangements of the amplifier  110  are same with those of the first embodiment. Specifically, the switching power supply  12   a  of the comparable example generates the output current I SW  just equal to a portion of the output current I L  of the linear power supply  14  excessing from the preset limit under the condition that the output voltage of the switching power supply  12   a  equal to the supply voltage V D  for the final section  10 . 
       FIG. 9  shows a circuit of the switching power supply  12   a  with the step-down configuration implemented within the amplifier  110  of the comparable example. The step-down configuration of the switching power supply  12   a  includes a series circuit of the FET  30  and the diode D 1  between the source power supply V CC  and ground. When the FET  30  turns on the current flows therein from the source power supply V CC  to store the energy in the inductor L 1 . While, when the FET  30  turns off, the energy stored in the inductor L 1  is released not only to charge the capacitor C 10  but to be outputted as the current I SW . The resistor R 10  detects the magnitude of the output current I SW , and this magnitude is fed back to the differential amplifier  38  to be compared with the control signal V CTRL . Thus, the switching power supply  12   a  generates the output current I SW  corresponding to the excess amount of the output current I L  of the linear power supply  14  from the preset limit and the supply voltage V D . 
     The input signal RF IN , the envelope signal V ENV  thereof, the output voltage V L , the output current I L , and the output power P L  (=V L ×I L ) of the linear power supply  14  are those shown in figures from  FIG. 5A to 6C . 
       FIG. 10A  shows the waveform of the source level of the FET  30 ,  FIG. 10B  shows the source current I source  of the FET  30  and the output current I SW  of the switching power supply  12   a , and  FIG. 10C  shows the power consumption of the switching power supply  12   a , namely, V SW ×I SW . The source level V source  of the FET  30  shows a full swing between the source power supply V CC  and the ground. When the FET  30  fully turns on, namely, the HIGH source level, the source current linearly increases to respective maxima in the periods, T 1  to T 4 . In addition, the duty ratio of the driving waveform for the FET  30  becomes a maximum in the period T 3  and a minimum in the periods, T 1  and T 4 . The period T 2  shows an intermediate duty ratio. According to this driving signal, the switching power supply may provide the output current I SW  shown in  FIG. 10B  to the final section, and the output power supplied to the final section becomes that shown in  FIG. 10C . 
     The switching power supply  12   a  with the step-down configuration is put between the source power supply V CC  and the ground, while, the linear power supply  14  is also put between the source power supply V CC  and the ground. That is, the linear power supply  14  and the switching power supply  12   a  are put in parallel between the source power supply V CC  and the ground. In such an arrangement, the power consumption P SW  of the switching power supply  12   a  simply becomes a product of the output voltage V SW  and the output current I SW  thereof, which means that the power consumption increases as the output voltage V SW  increases. The switching power supply  12  of the invention is put between the source power supply V CC  and the output of the linear power supply  14 . In this arrangement, the power consumption of the switching power supply  12  may be suppressed to a voltage difference between the output voltage V L  of the linear power supply  14  and the source power supply V CC  multiplied with the output current I SW . The switching power supply  12  of the embodiment only provides a current while the linear power supply  14  provides only a voltage; accordingly, the amplifier  100  of the embodiment may save the power consumption, or enhance the power efficiency. 
     In an example, assuming the efficiency of the switching power supply  12   a  with the step-down configuration in the comparable example to be 95%, the switching power supply  12   a  shows the maximum power consumption when the supply voltage V D  becomes maximum. Further assuming a condition that the switching power supply  12   a  outputs the voltage 50 V and the current 4 A at the maximum, then the power consumption by the switching power supply  12   a  becomes 50V×4 A×(1−0.95)=10 W. 
     On the other hand, assuming the switching power supply with the step-up configuration of the embodiment to be 90%, which is inferior to that of the comparable example, the switching power supply  12   a , as schematically illustrating in  FIG. 7C , shows a maximum power loss when the supplied voltage V D  is moderate. Further assuming a condition that the supplied voltage of 25 V and the current 2 A, then the power loss or the power consumption by the switching power supply  12  becomes, 25V×2 A×(1−0.9)=5 W. The switching power supply with the synchronous rectification type  12 A shown in  FIG. 4  may further enhance the power efficiency to about 95%; then, the power consumption or the power loss by the switching power supply  12 A becomes only 2.5 W. 
     The switching power supply  12  of the present embodiment generates a voltage with respect to the output voltage V L  of the linear power supply  14 ; that is, the switching power supply  12  with the step-up configuration generates an output higher than the source power supply V CC  with respect to the voltage output V L  of the linear power supply  14  but provides a current I SW  additional to the output current I L  to the final section  10  of the amplifier  100 . Thus, the amplifier  100  may reduce the power consumption without degrading the response to the input envelope. 
     Second Embodiment 
       FIG. 11  shows a functional block diagram of an amplifier according to the second embodiment of the invention. The amplifier  102  implements, substituted for the switching power supply  12  with the step-up configuration, a switching power supply  12 B with the step-down configuration between the output of the linear amplifier  14  and the source power supply V CC . 
       FIG. 12  is a circuit diagram of the switching power supply  12 B with the step-down configuration. The step-down switching power supply  12 B shown in  FIG. 12  is the type of the asynchronous rectification having a diode D 1 . That is, the switching power supply  12 B includes a series circuit of an FET  30  and a diode D 1  between the source power supply V CC  and the output V D . Turning on the FET by the gate driver  32 , a current from the source power supply V CC  flows in the inductor L 1  and the resistor R 10  to the output V D . On the other hand, turning off the FET  30 , a circular circuit of the diode D 1 , the inductor L 1  and the resistor R 10  is isolated from the source power supply V CC  and the energy stored in the inductor L 1  during a period when the FET  30  turns on is released in this circular circuit. A rectification circuit of a diode D 2  and a capacitor C 11  generates a power supply for the gate driver  32 . Thus, the switching power supply  12 B generates a voltage V SW , with respect to the output of the linear power supply  14 , lower than the source power supply V CC , where a practical value of the voltage V SW  depends on the duty ratio of a signal to drive the FET  30 . 
     The differential amplifier  40  detects a voltage difference, V SW −V D =V SENSE , generated by the switching power supply  12 B, and feeds this difference V SENSE  back to the differential amplifier  38 . As already explained, the differential amplifier  38  receives the control signal V CTRL  that corresponds to the excess amount of the current I L  output from the linear amplifier  14  from the preset limit. The feedback loop of the switching power supply  12 B to the differential amplifier  38  operates such that the sensing signal V SENSE  becomes equal to the control signal V CTRL , that is, the output V SW  the switching power supply  12 B with respect to the output V D  becomes equal to the excess amount of the current I L  from the preset limit. Thus, the excess amount of the current I L  output from the linear amplifier  14  may be compensated by the switching power supply  12 B with the step-down configuration. 
       FIG. 13  shows a circuit of another example of the switching power supply  12 C that provides the arrangement of, what is called, the synchronous rectification. That is, the switching power supply  12 C provides, instead of the diode D 1 , another FET  31  driven by the low-side gate driver  32   b . Two FETs,  30  and  31 , are complimentarily driven but without any period when two FETs simultaneously turn on. That is, as already described, when the upper side FET  30  turns on and the lower side FET  31  turns off, the current not only flows in the inductor L 1  and the resistor R 10  to the output from the source power supply V CC  but stores energy in the inductor L 1 . On the other hand, when the upper side FET  30  turns off and the lower side FET  31  turns on, the energy stored in the inductor L 1  is released through the resistor R 10 ; thus, the current corresponding to the difference, V SW −V D , is provided to the output V D . 
     Setting the preset limit of the current I L  output from the linear power supply  14  to be relatively small, the switching power supply,  12  to  12 C, may provide the excess amount of the current provided to the final section  10 . However, the switching power supply,  12  to  12 C, may not follow prompt transitions of the envelope of the input RF signal RF IN . The linear power supply  14  may compensate this excess amount and the linear power supply  14  finally only provides the preset limit current. 
     Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.