Abstract:
A class-AB push-pull drive circuit comprises a P channel MOS transistor having a source connected with a DC power source, a drain connected with an output terminal and a control electrode coupled with an input terminal through a voltage-to-current converter and a current-to-voltage converter and an N channel MOS transistor having a source grounded, a drain connected with the output terminal and a control electrode coupled with the input terminal. Conversion characteristics of the converters are so set that a potential difference between the control electrodes of the transistors is kept constant independently of the voltage of an input signal. Thus, the rise and fall of voltage at the output terminal during the conducting state of respective transistors is decreased. In addition, a push-pull drive operation by the transistors can be achieved in accordance with the input signal.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a class-AB push-pull drive circuit used for an audio circuit and the like and more particularly to the expansion of an operating range of an output voltage thereof. 
     2. Description of the Prior Art 
     FIG. 3 is a circuit diagram showing a conventional push-pull drive circuit. As shown in FIG. 3, an input terminal 1 is connected to the gate of an N channel MOS transistor Q 10 . The source of the transistor Q 10  is grounded, and the drain thereof is connected to the gate of a P channel MOS transistor Q 1  and to the drain of a P channel MOS transistor Q 9  in which the gate and the drain are connected in common. The source of the transistor Q 9  is connected to the source of an N channel MOS transistor Q 8 . The drain of the transistor Q 8  is connected to the gate of an N channel MOS transistor Q 2  and to one end of a resistor R 3 . The and gate of trasistor Q 8  is connected to the other end of the resistor R 3 . The other end of the resistor R 3  is connected through a constant current source I 4  to the positive side of a DC power source 3. The negative side of the DC power source 3 is grounded. The source of the transistor Q 1  is connected to an output terminal 2, and the drain thereof is grounded. The source of the transistor Q 2  is connected to the output terminal 2, and the drain thereof is connected to the positive side of the DC power source 3. 
     If a gate-source voltage of the transistor Q 8  is designated by V GS8 , a gate-source voltage of the transistor Q 9  by V GS9 , drain currents of the transistors Q 8  and Q 9  by I B4 , a gate-source voltage of the transistor Q 2  by V GS2 , a drain current thereof by I D2 , a gate-source voltage of the transistor Q 1  by V GS1 , and a drain current thereof by I D1 , the following equations hold: ##EQU1## where β 8  is a constant determined by the configuration of the transistor Q 8 , β 9  is a constant determined by the configuration of the transistor Q 9 , β 2  is a constant determined by the configuration of the transistor Q 2 , β 1  is a constant determined by the configuration of the transistor Q 1 , V THON  is a threshold voltage of the N channel transistors, and V THOP  is a threshold voltage of the P channel transistors. 
     With respect to a potential difference between the gate of the transistor Q 2  and the gate of the transistor Q 3 , the following equation holds: 
     
         V.sub.GS2 +V.sub.GS1 =V.sub.GS8 +V.sub.GS9 -R.sub.3 I.sub.B4( 5) 
    
     where R 3  is a resistance value of the resistor R 3 , and I B4  is a bias current from the constant current source I 4 . 
     As is obvious from the equations (5), (1) and (2), the potential difference between the gates of the transistors Q 1  and Q 2  can be held constant by setting R 3  and I B4  appropriately. 
     When the equations (1), (2), (3) and (4) are substituted in the equation (5), the following equation holds: ##EQU2## where I B3  is a constant bias current supplied from a constant current source I 3 . The value on the right side of the equation (6) is constant independently of the drain currents I D1  and I D2  of the transistors Q 1  and Q 2  in an output stage. Accordingly, it can be expressed as follows: ##EQU3## 
     If the current which flows from the drain of the transistor Q 2  to the drain of the transistor Q 1 , while no load current is present in the output terminal 2, is designated by I idle , I idle  =I D1  =I D2  the following equation holds: ##EQU4## This current value can be held sufficiently small by increasing the resistance value R 3 . 
     When load is connected to the output terminal 2 and an outflow current I source  is present, the gate-source voltage V GS2  of the transistor Q 2  is increased. In such a case, because the voltage between the gates of the transistors Q 1  and Q 2  is constant as expressed by the equation (5), the gate-source voltage V GS1  of the transistor Q 1  is decreased and, as a result, the drain current I D1  of the transistor Q 1  is decreased. 
     In this state, if the drain current I D1  of the transistor Q 1  is disregarded, an increasable maximum voltage V 2max  of the output terminal 2 can be found by the following equations: ##EQU5## where E is a voltage value of the DC power source 3. 
     In a normal enhancement CMOS structure, V THON  is about 0.8V. For sufficient current flow in the transistor Q 2 , √2I source  /β 2  must be about 0.5 V. According to the equation (10), the increasable maximum voltage V 2max  of the output terminal 2 is less than the voltage value obtained by subtracting 1.3 V from the source voltage E. 
     When a load is connected to the output terminal 2 and an inflow current I sink  is present, the gate-source voltage V GS1  of the transistor Q 1  is increased. Also in this case, because the voltage between the gates of the transistors Q 2  and Q 1  is constant as expressed by the equation (5), the gate-source voltage V GS2  of the transistor Q 2  is decreased and, as a result, the drain current I D2  of the transistor Q 2  is decreased. 
     In this state, if the drain current I D2  of the transistor Q 2  is disregarded, an decreasable minimum voltage V 2min  of the output terminal 2 can be found by the following equations: ##EQU6## 
     In the normal enhancement CMOS structure, V THOP  is about 0.8 V. For sufficient current flow in the transistor Q 1 , √2I sink  /β 1  must be about 0.5 V. According to the equation (12), the decreasable minimum voltage V 2min  of the output terminal 2 is more than 1.3 V. 
     In the conventional class-AB push-pull drive circuit as constructed above, the attainable maximum and minimum output voltages from the output terminal 2 are (E-1.3)V and 1.3 V respectively, and therefore there has been a problem that the operating range of the output voltage is narrow. 
     SUMMARY OF THE INVENTION 
     According to the present invention, a class-AB push-pull drive circuit comprises first and second power terminals for applying different first and second power potentials, respectively. Input and output terminals are supplied with input and output signals, respectively, and a first transistor is provided, having one electrode connected to the output terminal, another electrode connected to the first power terminal, and a control electrode coupled to the input terminal and supplied with a the voltage corresponding to voltage of the input signal. Conduction of the first transistor is controlled in accordance with a potential difference between the control electrode thereof and the other electrode thereof. A second transistor opposite in polarity to the first transistor, having one electrode connected to the output terminal, and another electrode connected to the second power terminal. Conduction of the second transistor is controlled in accordance with a potential difference between a control electrode thereof and the other electrode thereof. A voltage-to-current converter is coupled to the input terminal for generating current corresponding to the voltage of the input signal, and a current-to-voltage converter is connected between an output of the voltage-to-current converter and the control electrode of the second transistor for converting the current into voltage to supply the voltage to the control electrode of the second transistor. Conversion characteristics of the voltage-to-current converter and the current-to-voltage converter are established so that a potential difference between the control electrodes of the first and second transistors is held constant independently of the voltage of the input signal. 
     The first and second transistors according to the present invention are opposite in polarity to each other. The conduction of the transistors is controlled in accordance with the potential difference between the control electrodes and the other electrodes, respectively. The respective other electrodes thereof are connected to the first and second power terminals. Therefore, the rise and fall of voltage at the output terminal during the respective conducting states of the first and second transistors is reduced. Furthermore, the conversion characteristics of the voltage-to-current converter and the current-to-voltage converter are established so that the potential difference between the control electrodes of the first and second transistors is held constant independently of the voltage of the input signal. Therefore a push-pull drive operation by the first and second transistors can be achieved in accordance with the input signal. 
     Accordingly, an object of the present invention is to provide a class-AB push-pull drive circuit having a wide operating range of an output voltage. 
     These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram showing one preferred embodiment of a class-AB push-pull drive circuit according to the present invention; 
     FIG. 2 is a circuit diagram showing another preferred embodiment of the class-AB push-pull drive circuit according to the present invention; and 
     FIG. 3 is a circuit diagram showing a conventional class-AB push-pull drive circuit. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 is a circuit diagram showing one preferred embodiment of a class-AB push-pull drive circuit according to the present invention. The class-AB push-pull drive circuit comprises a buffer circuit 11, a voltage-to-current converter 12 and a current-to-voltage converter 13. 
     The buffer circuit 11 is composed of an N channel MOS transistor Q 3 , a P channel MOS transistor Q 4  and a constant current source I 1 . The gate of the transistor Q 3  is connected to an input terminal 1, the source thereof is connected to the source of the transistor Q 4 , and the drain thereof is connected to the positive side of a DC power source 3. The gate and drain of the transistor Q 4  are grounded in common. The common gate and drain of the transistor Q 4  are connected to the gate of an N channel MOS transistor Q 11  and grounded through the constant current source I 1 . 
     The current-to-voltage converter 12 is composed of an N channel MOS transistor Q 5  and a resistor R 1 . The gate of the transistor Q 5  is connected to the source of the transistor Q 3  in the buffer circuit 11, and the source thereof is grounded through the resistor R 1 . 
     The current-to-voltage converter 13 is composed of P channel MOS transistors Q 6  and Q 7 , a constant current source I 2 , and a resistor R 2 . The source of the transistor Q 6  is connected to the positive side of the DC power source 3, and the drain thereof is connected to the gate of a P channel MOS transistor Q 12  and to one end of the resistor R 2 . The other end of the resistor R 2  is connected to the gate of the transistor Q 7  and to the drain of the transistor Q 5  in the voltage-to-current converter 12 and is grounded through a constant current source I 3 . The source of the transistor Q 7  is connected to the gate of the transistor Q 6  and to the positive side of the DC power source 3 through the constant current source I 2 , with the drain thereof grounded. 
     The drain of the transistor Q 11  is connected to an output terminal 2, and the source thereof is grounded. The drain of the transistor Q 12  is connected to the output terminal 2, and the source thereof is connected to the positive side of the DC power source 3. The negative side of the DC power source 3 is grounded. 
     In this preferred embodiment, the P channel transistor Q 12  is provided between the output terminal 2 and the DC power source 3 and the N channel transistor Q 11  is provided between the output terminal 2 and the ground as drive transistors in an output stage. The buffer circuit 11, the voltage-to-current converter 12 and the current-to-voltage converter 13 are provided so that a potential difference between the bases of the transistors Q 11  and Q 12  is held constant at all times independently of the input voltage of the input terminal 1. The buffer circuit 11 converts an input signal with high impedance into a signal with low impedance and supplies the gate of the transistor Q 11  with voltage corresponding to the input voltage of the input terminal 1. The current-to-voltage converter 12 generates current corresponding to the input voltage. This current is converted into voltage again by the current-to-voltage converter 13, which outputs such voltage that decreases (or increases) a gate-source voltage V GS12  of the transistor Q 12  correspondingly when the input voltage is increased (or decreased) and a gate-source voltage V GS11  of the transistor Q 11  is increased (or decreased). Thereby (V GS11  +V GS12 ) is held constant at all times, and the potential difference between the gates of the transistors Q 11  and Q 12  (i.e., E-(V GS11  +V GS12 )) is also held constant at all times. 
     If a gate-source voltage of the transistor Q 4  is designated by V GS4 , a drain current thereof by I B1  (a bias current from the constant current source I 1 ), the gate-source voltage of the transistor Q 11  by V GS11 , a drain current thereof by I D11 , a gate-source voltage of the transistor Q 5  by V GS5 , a drain current thereof by I D5 , a gate-source voltage of the transistor Q 7  by V GS7 , a drain current thereof by I B2  (a bias current from the constant current source I 2 ), a gate-source voltage of the transistor Q 6  by V GS6 , a drain current thereof by I D6 , the gate-source voltage of the transistor Q 12  by V GS12 , a drain current thereof by I D12 , a gate potential of the transistor Q 5  by V A , and a bias current from the constant current source I 3  by I B3 , the following equations hold: ##EQU7## where β 4  is a constant determined by the configuration of the transistor Q 4 , β 11  is a constant determined by the configuration of the transistor Q 11 , β 5  is a constant determined by the configuration of the transistor Q 5 , β 6  is a constant determined by the configuration of the transistor Q 6 , β 7  is a constant determined by the configuration of the transistor Q 7 , β 12  is a constant determined by the configuration of the transistor Q 12 , V THON  is a threshold voltage of the N channel transistors, and V THOP  is a threshold voltage of the P channel transistors. 
     From the equations (19) and (20), the following equations hold: ##EQU8## where R 1  and R 2  are resistance values of the resistors R 1  and R 2 , respectively. 
     Here, I D6  =I D5  +I B3 , and thereby the following equation is obtained from the equations (21) and (22): 
     
         V.sub.GS12 =V.sub.GS6 +V.sub.GS7 -(R.sub.2 /R.sub.1)·(V.sub.GS11 +V.sub.GS4 -V.sub.GS5)-R.sub.2 I.sub.B3                   (23) 
    
     On the other hand, the equations (13) to (18) are transformed into the following equations: ##EQU9## 
     Letting R 1  =R 2  for simplification, the equation (23) can be transformed into the following equation: 
     
         V.sub.GS11 +V.sub.GS12 =V.sub.GS6 +V.sub.GS7 -V.sub.GS4 +V.sub.GS5 -R.sub.2 I.sub.B3                                                  (30) 
    
     Since I B1  and I B2  are constant bias currents supplied from the constant current sources I 1  and I 2  respectively, V GS4  and V GS7  are constant from the equations (24) and (28). Assuming that the change of I D5  is small, V GS5  and V GS6  are approximately constant from the equations (26) and (27). By setting R 2  I B3  appropriately, (V GS11  +V GS12 ) can be held constant at all times. The potential difference between the gates of the transistors Q 11  and Q 12 , which is E-(V GS11  +V GS12 ), can be held constant at all times by holding (V GS11  +V GS12 ) constant. 
     When the equations (24) to (29) are substituted in the equation (17), the following equation holds: ##EQU10## Letting R 1  =R 2  for simplification as described above, the following equation holds: ##EQU11## Assuming that the change of I D5  is small as above-mentioned, ##EQU12## can be obtained because the value on the right side of the equation (33) is approximately constant. 
     If current which flows from the drain of the transistor Q 2  to the drain of the transistor Q 1 , while no load current is present in the output terminal 2, is designated by I idle , I idle  =I D11  =I D12  and the following equation holds from the equation (33): ##EQU13## This current value can be held sufficiently small by increasing R 2  I B3 . 
     When a load is connected to the output terminal 2 and an outflow current I source  is present, the gate-source voltage V GS12  of the transistor Q 12  is increased. In such a case, because the potential difference between the gates of the transistors Q 11  and Q 12  is approximately constant, as expressed by the equation (30), the gate-source voltage V GS11  of the transistor Q 11  is decreased and, as a result, the drain current I D11  of the transistor Q 11  is decreased. 
     In this state, an increasable maximum voltage V 2max  of the output terminal 2 can be expressed by the following equation: 
     
         V.sub.2max =E-V.sub.12SAT                                  (36) 
    
     where V 12SAT  is a saturation voltage of the transistor Q 12 . This saturation voltage V 12SAT  can be sufficiently small (e.g., 0.2 V or less). Hence, according to the drive circuit of this preferred embodiment, the voltage is operable up to a value much higher than the maximum voltage of the conventional circuit of FIG. 3 expressed by the equation (10). 
     When load is connected to the output terminal 2 and an inflow current I sink  is present, the gate-source voltage V GS11  of the transistor Q 11  is increased. In such a case, because the potential difference between the gates of the transistors Q 11  and Q 12  is approximately constant as expressed by the equation (30), the gate-source voltage V GS12  of the transistor Q 12  is decreased and, as a result, the drain current I D12  of the transistor Q 12  is decreased. 
     In this state, a decreasable minimum voltage V 2min  of the output terminal 2 can be expressed by the following equation: 
     
         V.sub.2min =V.sub.11SAT                                    (37) 
    
     where V 11SAT  is a saturation voltage of the transistor Q 11 . This saturation voltage V 11SAT  can be sufficiently small (e.g., 0.2 V or less). Hence, according to the drive circuit of this preferred embodiment, the voltage is operable to a value much lower than the minimum voltage of the conventional circuit of FIG. 3 expressed by the equation (12). 
     According to this preferred embodiment, the attainable maximum and minimum output voltages of the output terminal 2 are (E-0.2)V and 0.2 V respectively, and thus an advantage is that the operating range of the output voltage is sufficiently wide in comparison with the conventional circuit. 
     FIG. 2 is a circuit diagram showing another preferred embodiment of the class-AB push-pull drive circuit according to the present invention. In this preferred embodiment, the voltage-to-current converter 12 comprises resistors R 4  to R 6  and a current mirror circuit composed of N channel MOS transistors Q 21  and Q 22 . The gate and drain of the transistor Q 21  are connected in common, and the common junction is connected through the resistor R 6  to the source of the transistor Q 3  in the buffer circuit 11. The source of the transistor Q 21  is grounded through the resistor R 4 . The gate of the transistor Q 22  is connected to the gate of the transistor Q 21 , the drain thereof is connected to the common junction of the resistor R 2  and the gate of the transistor Q 7  in the current-to-voltage converter 13, and the source thereof is grounded through the resistor R 5 . Other structure of this preferred embodiment is similar to that of the circuit of FIG. 1. 
     In the circuit structure according to this preferred embodiment, the gate voltage of the transistor Q 22  is adapted to be decreased so that the transistor Q 22  connected to the current-to-voltage converter 13 can be operated on a lower power voltage in comparison with the transistor Q 5  in the circuit of FIG. 1. 
     In the above-mentioned preferred embodiments, conversion characteristics of the voltage-to-current converter 12 and the current-to-voltage converter 13 are established so that the increase (or decrease) in the input voltage causes the current in the voltage-to-current converter 12 to increase (or decrease) and accordingly the output voltage of the current-to-voltage converter 13 supplied with that current decreases (or increases) the gate-source voltage V GS12  of the transistor Q 12 . However, the conversion characteristics of the voltage-to-current converter 12 and the current-to-voltage converter 13 may be established so that the increase (or decrease) in the input voltage causes the current in the voltage-to-current converter 12 to decrease (or increase) and accordingly the output voltage of the current-to-voltage converter 13 supplied with that current decreases (or increases) the gate-source voltage V GS12  of the transistor Q 12 . 
     Furthermore, in the above-mentioned preferred embodiments, the drive circuit may be constituted so that, by reversing the potential E of the DC power source 3 and the ground potential, the respective transistors Q 3  to Q 7 , Q 11 , Q 12 , Q 21  and Q 22  are reversed in polarity of P and N channels. 
     Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation. The spirit and scope of the present invention should be limited only by the terms of the appended claims.