Abstract:
An amplitude equalizer includes a pair of serially connected unit amplitude equalizers, each having complementary delay distortion characteristics to flatten the overall delay distortion characteristic. The unit equalizers include amplifiers or attenuators, delay circuits, and/or phase shifters. The amplitude versus frequency characteristic of the overall equalizer can be varied by controlling one or more of the attenuator/amplifiers and phase shifters. The variation can be controlled by a feedback circuit.

Description:
The present invention relates to an amplitude equalizer for use in a signal transmission system. 
     Signal transmission systems require amplitude equalization in order to realize desired transmission characteristics. As an equalizer of this kind, the bridged-T attenuation equalizer (Reference is made to DATA TRANSMISSION, MacGraw-Hill, 1965, Chapter 15) is well known. In general, however, equalizers of this type produce more delay distortion the larger the equalizing quantity (deviation of amplitude-frequency characteristics) with the result that several more delay equalizers are needed for high-speed transmission systems than for level transmission systems. It has been almost impossible to construct a variable equalizer, although Bode&#39;s variable equalizers (Reference is made to &#34;On the Synthesis of the Two-Port Network in Bode&#39;s Variable Equalizer&#34;, IEEE TRANSACTIONS ON CIRCUIT THEORY, May 1971, pp 387-390) are commonly used. One shortcoming of equalizers of this type is that the equalizable amplitude range narrows as the ratio (fractional band) of signal bandwidths to be equalized versus signal center frequencies lowers. Furthermore, the generation of delay distortion has been unavoidable. 
     The object of this invention is to present an amplitude equalizer which is free from the shortcomings of conventional equalizers, and which is stable, versatile and easy to adjust. 
     According to the present invention, there is provided an amplitude equalizer having a first input terminal for an input signal of a prefixed amplitude distortion within a predetermined frequency region, and a first output terminal, the amplitude vs. frequency characteristics of said amplitude equalizer being such that an amplitude-equalized, distortion-eliminated output signal is provided at said first output terminal: wherein a first and a second unit amplitude equalizers respectively of a first and a second delay distortion characteristics are disposed in series between said first input terminal and said first output terminal; wherein said first unit amplitude equalizer has a first means having a second input terminal, a second and a third output terminals for branching an input signal applied thereto, a second means having a fourth output terminal and a third and a fourth input terminals for synthesizing signals incoming at said third and fourth input terminals, a third means disposed between said second output terminal and said third input terminal for amplifying or attenuating a signal incoming thereto, and a fourth and a fifth means disposed in series between said third output terminal and said fourth input terminal, said fourth and fifth means being for delaying and for phase shifting, respectively; wherein said second unit amplitude equalizer has a fifth input terminal, a sixth means having a fifth and a sixth output terminals for branching a signal incoming thereto, a seventh means having a seventh output terminal and a sixth and a seventh input terminals for synthesizing signals incoming at said sixth and seventh input terminals, an eight means for connecting said fifth output terminal and said sixth input terminal, a ninth and a tenth means disposed in series between said sixth output terminal and said seventh input terminal, said ninth and tenth means being respectively for phase shifting and attenuating or amplifying signals supplied thereto; wherein said first and second delay distortion characteristics being set to complementary values to flatten the overall delay distortion characteristics of said amplitude equalizer; and wherein at least one of attenuation or amplification factor of said third and eleventh means, the delay time at each said fourth and said with means, the phase shift at each said fifth and tenth means is changed to make said amplitude vs. frequency characteristics variable. 
    
    
     The present invention will be explained in detail by referring to the accompanying drawings, in which: 
     FIG. 1 shows a block diagram of one embodiment of the present invention; 
     FIG. 2 shows a block diagram of the equalizer shown in FIG. 1 with a modified circuit; 
     FIG. 3 shows amplitude vs. attenuation factor characteristics of the equalizer shown in FIG. 1; 
     FIGS. 4 and 5 show delay distortion vs. attenuation factor characteristics of the equalizer shown in FIG. 1; 
     FIGS. 6 and 7 show amplitude vs. phase shift quantity characteristics of the equalizer shown in FIG. 1; 
     FIG. 8 shows amplitude vs. delay time characteristics of the equalizer shown in FIG. 1; 
     FIG. 9 shows a block diagram of an example of the phase shift circuit employed in the embodiment of the present invention; 
     FIGS. 10 and 11 show block diagrams of further embodiments of the present invention; 
     FIG. 12 shows a block diagram of an example of the automatic phase shift circuit employed in the embodiments; 
     FIG. 13 shows a block diagram of an example of the control circuit employed in the embodiments; 
     FIG. 14 is a characteristic diagram of the circuit shown in FIG. 13; 
     FIGS. 15 through 18 show block diagrams of further embodiments of the present invention; 
     FIG. 19 is a block diagram of another example of the automatic phase shift circuit employed in the embodiments invention; and 
     FIG. 20 is a diagram of an example of the automatic phase shifter employed in the circuit shown in FIG. 19. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In FIG. 1, reference numerals 1 and 2 show the first and second unit equalizers each having different amplitude equalizing characteristics; 11, a signal branching circuit; 12, a signal combiner; 13, a delay circuit; and 15, an attenuation circuit. 
     Where the delay time in delay circuit 13, phase shift in phase shift circuit 14 and attenuation factor in attenuation circuit 15 are τ, φ and α, respectively, and where input signal E 1  supplied by input terminal 101 is βejωt, output signals A 1  and B 1  at branching circuit 11 having attenuation factor 1/β and attenuation circuit 15 are given by: 
     
         A.sub.1 =e.sup.jωt 
    
     
         B.sub.1 =α; e.sup.j{ω(t-τ)+φ} 
    
     Accordingly, output signal C 1  from the signal combiner 12 is given by: 
     
         C.sub.1 =A.sub.1 +B.sub.1 =e.sup.jωt {1+α·e.sup.-j(ωτ+φ)} 
    
     Transmission characteristics (transfer function) T 1  (ω) for the circuit lying between the input and output of the signal combiner 12, therefore, is given by: 
     
         T.sub.1 (ω)=1+α·e.sup.-j(ωτ+φ) 
    
     Where the transfer functions of the amplitude, phase and delay time of unit equalizer 1 are S 1  (ω), θ 1  (ω) and D 1  (ω) respectively, the following equation can be obtained: 
     
         T.sub.1 (ω)=S.sub.1 (ω)·e.sup.-jθ1(ω) ##EQU1## Next, transmission characteristics of unit equalizer 2 are obtained by the same methods, and where characteristic functions of the amplitude, phase and delay time are assumed to be S.sub.2 (ω), θ.sub.2 (ω) and D.sub.2 (ω) (provided circuits 13-15 have the same functions as those of unit equalizer 1 and the same delay time, phase shift quantity and attenuation factor are given to the respective signals), the following equations will be obtained: ##EQU2## The following relations are seen between S.sub.1 (ω) and S.sub.2 (ω), between θ.sub.1 (ω) and θ.sub.2 (ω) between D.sub.1 (ω) and D.sub.2 (ω): 
    
     
         S.sub.1 (ω)=S.sub.2 (ω) 
    
     
         θ.sub.1 (ω)+θ.sub.2 (ω)=-ωτ+φ ##EQU3## 
    
     As is apparent from the foregoing equations, amplitude vs. frequency characteristics can be equalized with absolutely no theoretical delay distortion only by combining unit equalizers 1 and 2 in FIG. 1. 
     FIG. 2 shows a block diagram of the equalizer modifying the circuit shown in FIG. 1. In FIG. 2, reference numeral 16 designates attenuation circuit. The exact same results as those of the construction in FIG. 1 will be obtained by giving the relations of α&#39;=1/α for the attenuation quantity α&#39; versus α of attenuation circuit 15. When α&lt;1, then α&#39;&gt;1. Accordingly, α&#39; will be an amplification factor and hence attenuation circuit 16 is changed to an amplifier circuit in this instance. 
     As with the relations in FIGS. 1 and 2, equalizers having the same characteristics as those of the equalizer shown in FIG. 1 can be obtained even if various types of the unit equalizers 1 and 2 are combined by selecting complementary attenuation or amplification factors of the first and last-stage unit equalizers so as not to generate delay distortion. 
     FIG. 3 shows the movement of S 1  (ω) (=S 2  (ω)) with the equalizer having the same construction as shown in FIG. 1, for the case when the value of the delay time τ is fixed and the value of α is to varied to 0.1, 0.4 and 0.7. In the figure, the equalizer has positive and negative linear characteristics in regions Z 1  and Z 2 , respectively, and has positive and negative course of the second, or higher order in regions Z 3  and Z 4 , respectively. 
     FIGS. 4 and 5 show the delay distortion D 1  (ω)/τ of equalizers 1 and 2 when α=0.1, 0.4 and 0.7. As {D 1  (ω)+D 2  (ω)}/τ in FIG. 5 shows, the delay distortion is flatted when equalizers 1 and 2 are combined, and the equalizer in FIG. 1 does not cause any delay distortion at all. 
     FIG. 6 shows the variation in S 1  (ω) when the phase shift quantity φ is varied while the attenuation factor, or amplification factor α, and delay time τ are kept constant. For example, by selecting the slant line region Z 5  (shown in the figure) as an equalizing bandwidth, characteristic a does not include equalizing characteristics of the linear distortion. By reducing the phase to -τ/2 and -3τ/4 relative to characteristic a, the positive linear amplitude distortion increases from characteristics b to c, while the negative linear amplitude distortion increases when the phase is reversed. In other words, this figure shows that equalizer 1, by continuously varying the phase, can vary the amplitude vs. frequency characteristics, including polarity, continuously for the linear distortion. 
     FIG. 7 shows amplitude vs. frequency characteristics S 1  (ω) for the attenuation factor, or amplification factor (α), and delay time (τ) kept constant and the phase difference φ varied to 0 and τ. In region Z 6 , characteristics d and e have the polarities of their linear distortion reversed, whereas in region Z 7  the polarities in the secondary and higher-order distortion are reversed. Therefore, when designing an amplitude equalizer as shown in FIGS. 1 and 2, it is not absolutely necessary to give continuously variable phase transition to the signal in phase shift circuit 14. By selecting the polarity in the linear distortion, or in the distortion of the second order and by using a simple phase switch for 0 and π only along with changing the amplitude ratio (attenuator factor, or amplification factor) α as shown in FIG. 3, a linear distortion equalizer including polarity, or an equalizer having distortion of the second, or higher, order can be obtained. 
     FIG. 8 shows amplitude vs. frequency characteristics, i.e., for the delay time τ varied to τ 2 , τ 1  and to τ 3  (τ 2  &lt;τ 1  &lt;τ 3 ) and the attenuation factor or amplification factor α and phase shift quantity φ kept constant. The linear distortion decreases as τ increases to τ 2 , τ 1 , and τ 3  when the slant line region Z 8  is selected as an equalizing bandwidth. 
     FIG. 9 is a block diagram of a more concrete circuit of phase shift circuit 14. Reference numerals 51 and 52 designate mixers; 55 and 56, phase shifters; 53 and 54 band-pass filters; and 57, a local frequency oscillator. When the phase shift values in phase shifters 55 and 56 are θ 1  and θ 2 , respectively, input signal fed to mixer 51 is V 1 , and output signals of phase shifters 55 and 56 are L 1  and L 2 , respectively. 
     
         V.sub.1 =A sin (ω.sub.1 t) 
    
     
         L.sub.1 =B sin (ω.sub.2 t+θ.sub.1) 
    
     
         L.sub.2 =B sin (ω.sub.2 t+θ.sub.2) 
    
     The following equation is obtained by mixing the input signal V 1   and the local oscillation L 1  in mixer 51: ##EQU4## For example, by selecting the first term (lower side band) in the above equation with band-pass filter 53 and by mixing with local signal L 2  : ##EQU5## Furthermore, by outputting the first term in the above equation by using band-pass filter 54, the difference in phase shift quantities (θ 2  -θ 1 ) in phase shifters 55 and 56 is given to signal V 1 . A fixed phase transition can be given to broadband signals by using circuit 14. 
     FIG. 10 is another application example of a block diagram of an amplitude equalizer according to the present invention. Reference numeral 3 denotes a unit equalizer; 17, an automatic phase shift circuit (will be discussed later); 18, an automatic gain control circuit (hereinafter referred to as AGC); and 19, a phase-shift control circuit. The circuit 19 detects amplitude vs. frequency characteristics of the input signal component (power spectrum) within signal bands and controls the phase shift quantity of automatic phase shift circuit 17. Nothing changes compared with the amplitude equalizer shown in FIG. 1 except for the automatic control of the phase shift quantity by automatic phase shift circuit 19. Consequently, the same theoretical analysis of the circuit shown in FIG. 1 applies to the equalizer shown in FIG. 10. Its characteristic functions of attenuation factor, or amplification factor, phase quantity and delay time are the same as those shown in FIGS. 3 through 8. 
     FIG. 11 is a block diagram of another example of an amplitude equalizer according to the present invention. Reference numeral 4 denotes a unit amplitude equalizer. The equalizer in FIG. 11 is inversely related to the attenuation factor or amplification factor of circuit 16 and the attenuation factor or amplification factor of circuit 15 in that their relations are expressed by an inverse number. This was the case with the equalizers in FIGS. 1 and 2. The same results as those of the equalizer in FIG. 10 were obtained. The same results as those in the equalizer shown in FIG. 1 can be obtained with other combinations using unit equalizers 3 and 4. 
     The equalizers in FIGS. 10 and 11 will be described further with regard to FIG. 6. It shows the movement of S 1  (ω) when the phase shift quantity φ is changed while the attenuation factor or amplification factor α and delay time τ remain constant. There will be no linear amplitude distortion for characteristic a in the figure when, for example, the slant line region Z 5  in FIG. 6 is selected as an equalizing bandwidth. When the phase is reduced from -π/2 to -3π/4, compared with characteristic a, the positive linear distortion increases from characteristics b to c. By inversely increasing the phase, the negative linear distortion increases. This shows that the amplitude vs. frequency characteristics can be varied continuously by the linear amplitude distortion, including the polarity, by continuously varying the phase. Therefore, by detecting the polarity and magnitude of the linear distortion of the amplitude vs. frequency characteristics generated on the transmission line (based on the distortion on the power spectrum of the receiving signal in control circuit 19), and by controlling the phase of phase shift circuit 17 in order to cancel this linear distortion, a negative feedback circuit can be structured and amplitude vs. frequency characteristics through the transmission line can be kept flat. 
     FIG. 12 shows a block diagram of a more concrete circuit of automatic phase shift circuit 17. Reference numerals 58 and 59 denote automatic phase shifters and F indicates a control signal from control circuit 19. The circuit is the same construction as phase shift circuit 14 in FIG. 9 except that the phase shift can be changed automatically by control circuit 19. When the phase shift in phase shifters 58 and 59 are θ 1  and θ 2 , the same analytic results as those for the circuit in FIG. 9 can be obtained. The phase shift quantity of input signal V 2  to mixer 51 will be the same. 
     FIG. 13 is a block diagram of a more concrete circuit of control circuit 19. Reference numerals 60 to 62 denote narrow band-pass filters having center frequencies (f 0  +f 1 ), (f o  -f 1 ) and f o  (f o  is the center frequency of the frequency band occupied by the signal and f 1  an appropriate frequency). Reference numerals 63 to 65 denote level detectors; and 66 and 67, differential amplifiers. FIG. 14 shows amplitude vs. frequency characteristics of filters 60 to 62. Differential amplifier 66 compares the output of level detectors 63 and 64, [signal components on both lower and higher frequency sides of f 0  ] takes out the difference between the two and outputs X according to the linear amplitude distortion and its polarity. Differential amplifier 67, on the other hand, compares the average output of level detectors 63 and 64 and the output of level detector 65 (signal components near f 0 ), and takes out the difference between the two. Then output Y is made according to the distortions and polarities of the second and higher orders. Filter 62, detector 65, resistors R 1  and R 3  and differential amplifier 67 are not needed when equalizing only the linear amplitude distortion, and differential amplifier 66 is not necessary when equalizing distortion of the second and higher orders. Output signals X and Y of differential amplifiers 66 and 67 respectively, are selectively supplied to the circuits to be controlled. 
     FIG. 15 is a block diagram of another example of the amplitude equalizer according to the present invention. Reference numeral 20 denotes a circuit for taking the sum or difference regarding signal synthesis; and 21 and 22, automatic attenuation circuits. The theoretical analysis of the equalizer in FIG. 15 is the same as that for the equalizer in FIG. 1. However, when there is no phase shift circuit, φ=0 or φ=π has to be present for the phase difference φ corresponding to the sum or difference of signals in combining circuit 20. The characteristic functions of attenuation factor, or amplification factor, and delay time are the same as the characteristic diagrams in FIGS. 3 to 5, 7 and 8. 
     FIG. 16 is a block diagram of still another example of the amplitude equalizer according to the present invention. The relations between the equalizers in FIGS. 16 and 15 are the same as those for the equalizers in FIGS. 1 and 2, and the same characteristics have been obtained by adjusting the attenuation factor or amplification factor. As with FIGS. 1 and 2, the same effects can be obtained by other combinations using unit equalizers 5 and 6. 
     The equalizers in FIGS. 15 and 16 are explained further in FIG. 7. It shows amplitude vs. frequency characteristics S 1  (ω) when the phase difference is changed to 0 and π while the attenuation factor, or amplification factor α, and delay time (τ) remain constant (equivalent in value by taking the sum of, or difference between the signals). In region Z 6  shown in FIG. 7, characteristics a and b have the polarities of their linear distortions reversed. In region Z 7 , the polarities of the second and higher order distortions are reversed. Therefore, if the distortion character of the amplitude vs. frequency characteristics generated in the transmission line can be determined in advance (e.g., the polarity of the linear distortion is positive), various amplitude equalizers can be designed. This is done by setting the delay time difference (τ) in the equalizers in FIGS. 15 and 16, and the sum or difference of signals in the synthesis circuit 20 as required. In other words, amplitude vs. frequency characteristics can be automatically maintained flat by detecting the linear amplitude distortion generated in the transmission lines of the equalizers in FIGS. 15 and 16 and reducing this distortion by controlling attenuation circuit 21 or 22. As a circuit in concrete terms for synthesizing circuit 20, a hybrid transformer, etc. can be used with a signal sum, while a differential amplifier, etc. can be used with a signal difference. 
     The same control circuit as shown in FIG. 13 can be used as control circuit 19. 
     FIG. 17 is a block diagram of another application example of the amplitude equalizer according to the present invention. Reference numeral 7 denotes a unit equalizer; and 23, an automatic phase shift circuit. The theoretical analysis of the equalizer in FIG. 17 is the same as that for the equalizer in FIG. 1. The only difference is that, in the construction, the phase shift quantity φ and attenuation factor or amplification factor α, are automatically controlled by control circuit 19. 
     FIG. 18 shows a block diagram of still another example of the amplitude equalizer according to the present invention. Reference numeral 8 denotes a unit equalizer. The relation between the equalizers in FIGS. 17 and 18 are the same as those for the equalizers shown in FIGS. 1 and 2. As with the equalizers in FIGS. 1 and 2, various equalizers can be constructed by changing combinations of unit equalizers 7 and 8. 
     The characteristic functions of the attenuation factor or amplification factor, phase quantity, and delay time of the amplitude equalizers in FIGS. 17 and 18 are the same as those in the characteristic diagrams in FIGS. 3 to 8. The equalizers shown in FIGS. 17 and 18 will be explained further in FIG. 7. It shows amplitude vs. frequency characteristics S 1  (ω) when the attenuation factor or amplification factor α, and delay time τ are constant and the phase difference is varied to 0 and π. In region Z 6  shown in FIG. 7, the polarities of the linear distortion for characteristics d and e are inverse, whereas in region Z 7 , the polarities of the distortion of the second, or higher, order are inverse. This means that, when designing an automatic equalizer as shown in FIGS. 17 and 18, continuous variable phase transition does not necessarily have to be given to the signal in phase shift circuit 23. An equalizer for linear distortion including polarity, or an equalizer for second or higher order distortions, can be obtained by selecting polarities of linear distortion, or of secondary, or higher order distortions. This is done by using a simple phase switch for 0 and π only, and by varying the amplitude ratio (attenuation factor or amplification factor) α as shown in FIG. 3. 
     FIG. 19 is a block diagram of a more concrete circuit for automatic phase shift circuit 23. Reference numeral 68 denotes the automatic phase shifter. When the phase shift of the automatic phase shifter is θ, input signal fed to mixer 51 is V 2 , output signal of the local oscillator 56 is L 3 , the output signal of the automatic phase shifter is L 4 , and where 
     
         V.sub.2 =A sin ω.sub.1 t 
    
     
         L.sub.3 =B sin ω.sub.2 t 
    
     
         L.sub.4 =B sin (ω.sub.2 t+θ) 
    
     the following equation is obtained: ##EQU6## by mixing input signal V 2  and local oscillation L 3  in mixer 51. For example, by selecting the first term (lower side band) in the above equation using filter 53 and by mixing it with local oscillation L 4  : ##EQU7## By taking out the first term in the above equation, the phase shift θ in automatic phase shifter 68 is given to signal V 2  as it is. A certain phase shift can be given to broadband signals by using circuit 23. 
     FIG. 20 is a more concrete circuit diagram for automatic phase shifter 68. Reference numeral 69 denotes a gate circuit for providing positive an inverse phases of an input signal; and 70, a NAND circuit. This phase shifter is a phase switch (0 and π) with a simple digital circuit. Assuming the oscillation output of local oscillator 56 to be L 3  ; control signal, F; and output signal, Z; a local oscillation, whose phase has changed by π only, will be obtained at the output Z when control signal F is a digital signal `0` or `1`. An automatic equalizer that can be used with linear distortions or secondary and higher order distortions can be obtained by varying θ to 0, π/2, π, and 3π/2. The circuit shown in FIG. 13 can be used with control circuit 19. 
     All the amplitude equalizers stated above are structured by combining unit equalizers 1 to 8. The foregoing explanations show that the unit equalizers 1 to 8 independently operate as an amplitude equalizer. Furthermore, an amplitude equalizer with a larger equalizing amplitude can be obtained by combining an n (n: positive integer) number of combinations consisting of two unit equalizers (i.e., unit equalizers in 2n number) aside from a unit equalizer, and an equalizer combining two unit equalizers. An equalizer capable of equalizing amplitude characteristics of linear distortions and secondary distortions at the same time can be obtained by using the circuit shown in FIG. 13 as a control circuit for an equalizer combining a plural number (2n) and by supplying output signals X and Y of differential amplifiers 66 and 67 to an equalizer that equalizes the characteristics of the linear and secondary order distortions. 
     The present invention permits a design of an amplitude equalizer that can have a specific frequency region and maximum equalizing amplitude by appropriately selecting the attenuation factor or amplification factor (α), phase shift quantity (Φ) and delay time (τ). This invention allows the addition of an automatic amplitude equalizer capable of automatically selecting the equalizing region and equalizing the characteristics as needed. Further, by combining unit equalizers and appropriately adjusting the attenuation factor or amplification factor, an amplitude equalizer with flat delay distortion characteristics, large equalizing amplitude and that can simultaneously equalize amplitude characteristics of linear and second or higher order distortions can be obtained.