Abstract:
An input buffer circuit incorporates variable hysteresis levels to protect against unintended changes of output state in response to glitches in the input signal. The circuit is used in connection with input signals that alternate between LO and HI input states with known minimum periods between alternations. The switching threshold hysteresis for reverting back to a prior output state is boosted during the period following an input signal transition, with the boosted hysteresis removed following a delay period that is no greater than the minimum period between successive input signal transitions. Numerous circuit designs may be used to implement the varying hysteresis levels.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to input buffer circuits for switching an output between HI and LO states when an input signal crosses a threshold level, with a hysteresis function added to prevent unintentional resetting switching of the circuit, and more particularly to Schmitt trigger circuits with a time-variant threshold level. 
     2. Description of the Related Art 
     A Schmitt trigger circuit functions as a level-detecting comparator with hysteresis. Its output changes from a LO to a HI state when an increasing input signal crosses an upper switching threshold Vhi, and reverts back to its initial state only when the input crosses a lower threshold level Vlo which is less than Vhi. The difference between the two threshold levels, Vhi-Vlo, is the hysteresis associated with the switch. Schmitt trigger circuits are commonly used on chip inputs to convert a signal with a very slow or sloppy transition into a signal with a sharp transition. They are described, for example, in Glasser et al., The Design and Analysis Circuits, Addison-Wesley Publishing Co., 1985, pages 281-282, and in Hodges et al., Analysis and Design of Digital Integrated Circuits, McGraw-Hill Book Co., 1983, pages 335-337. 
     A typical input-output voltage characteristic for a non-inverting Schmitt trigger circuit is illustrated in FIG. 1. The output follows a trace 2 when the input rises above the turn-on threshold Vhi, and then follows trace 4 as the input falls back below the turn-off voltage threshold Vlo. 
     A schematic diagram of a conventional non-inverting CMOS Schmitt trigger is given in FIG. 2. An input signal is applied at an input terminal 2, and is transmitted via an input N-channel field effect transistor (FET) N0pa (&#34;pa&#34; indicates &#34;prior art&#34;) to the switch circuit. An ENABLE terminal 4 provides a power conservation function by applying an ENABLE signal to the gates of input transistor N0pa and an ENABLE PMOS transistor P0pa. The source-drain circuit of transistor P0pa is connected between a positive voltage reference Vdd, typically 5 volts, and the input to the switch circuit. Transistor N0pa is turned on and transistor P0pa is turned off when a HI enable signal is applied at terminal 4, allowing the Schmitt trigger to function in the normal manner. A LO enable signal is applied during periods when the output from the Schmitt trigger is not used. It turns transistor N0pa off and transistor P0pa on, tying the Schmitt trigger input to Vdd and causing it to produce a HI output state regardless of the input signal. 
     The Schmitt trigger itself includes two P-channel FETs P1pa and P2pa, which have their source-drain current circuits connected in series with the source-drain current circuits of a pair of N-channel FETs N1pa and N2pa. The P-channel end of the series circuit is connected to Vdd, while the N-channel end of the circuit is connected to a lower voltage reference such as ground; the input signal is connected in common at node 6 to the gate control electrodes for each of the series-connected FETs. A third P-channel device P3pa has its source-drain circuit connected between ground and the junction 8 of the P1pa/P2pa current circuits, while a third N-channel device N3pa has its source-drain circuit connected between Vdd and the junction 10 of the current circuits for the N-channel devices N1pa and N2pa. The gate electrodes of P3pa and N3pa are connected together to an internal output line 12 at the junction of the current circuits for P2pa and N1pa, which in turn is connected through an inverter INV1 to an external output terminal 14. 
     In operation, assume that the input signal at terminal 2 is initially LO, and that the circuit has been enabled. The P-channel devices P1pa and P2pa will thus be ON, while the N-channel devices N1pa and N2pa will be OFF. This ties internal output line 12 to a HI state equal to Vdd, which in turn holds P3pa OFF and N3pa ON to set the node 10 HI (less a threshold voltage). The output at terminal 14 at this time is the inverted value of the signal at node 12, or LO. 
     Assume now that the input voltage at terminal 2 begins to rise. When the input voltage has become great enough, the N-channel devices N1pa and N2pa will become conductive, while the P-channel devices P1pa and P2pa will turn OFF. When it is conductive, FET N2pa connects node 10 to the ground reference, which in turn grounds the internal output line 12 through N1pa; the result is a HI inverted signal at output terminal 14. However, N2pa has to overcome the connection of Vdd to node 10 (through N3pa) before it can place node 10 in a LO state. The relative size scalings of N1pa, N2pa and N3pa are selected to set the threshold voltage level Vhi at which this transition to a HI output occurs. Conversely, once the trigger circuit output is HI, P3pa is held ON by virtue of its gate&#39;s ground connection through N1pa and N2pa, while P1pa and P2pa are held OFF. For the circuit output at terminal 14 to revert to a LO state when the input signal at terminal 2 falls, P1pa must become conductive enough to overcome the grounding effects of P3pa and set node 8 at a HI level that corresponds to Vdd. This is the point at which the circuit switches back to a LO output; the relative sizes of P1pa, P2pa and P3pa are selected so that the switching transition occurs at the threshold voltage level Vlo, thus providing the proper amount of hysteresis. 
     It is not necessary to have both hysteresis transistors P3pa and N3pa. There will still be a level of hysteresis if only one of these transistors is used, but it will be less than with both transistors present. Since the hysteresis level can be doubled using two transistors of the same size, whereas the size of a single transistor has to be substantially more than doubled to double its hysteresis effect, both transistors P3pa and N3pa are commonly employed. 
     In practice, the circuit does not switch abruptly from one output state to another at the instant Vhi or Vlo is traversed. Rather, a more gradual switching transition takes place, as indicated by the curvatures at either end of switching traces 2 and 4 in FIG. 1, and the non-vertical slope of the traces in between. Also, the actual switching points are sensitive to variations in the manufacturing process, the ambient temperature and the power supply voltage. Such variations impact both the hysteresis and the circuit&#39;s speed, as well as its absolute switching points. Thus, in a practical circuit Vhi and Vlo define the outer limits of the input voltage (the threshold window) beyond which the output state will definitely be either HI or LO. For example, with a Vdd of 5 volts and ground providing the voltage reference levels, typical values for Vhi and Vlo are 2.0 volts and 0.8 volts, whereas the actual designed threshold for switching HI might be 1.5 volts and the threshold for switching LO 1.3 volts. This leaves enough &#34;head room&#34; between the designed switching threshold levels and the outer permissible limits of Vhi and Vlo to allow for process, temperature and power supply variations. 
     The purpose of the hysteresis between the Vhi and Vlo switching threshold levels is to prevent the circuit from unintentionally switching its output state in response to noise or other signal defects. Such unintentional switching is illustrated in FIGS. 3a, 3b and 3c. FIG. 3a illustrates an input signal that begins rising from a LO to a HI state at time T1, and then begins returning to a LO state at time T2. The pulse&#39;s rising edge is shown as having a &#34;glitch&#34; 16, during which the signal level momentarily falls before resuming its rise, with another glitch 18 at the end of its falling edge when it rises back above its LO level. The latter glitch can result, for example, from signal undershoots due to transmission line effects from either the circuit board or the bond wires. 
     The desired output is shown in FIG. 3b, rising from a LO to a HI state at time T1 and then returning to LO at time T2. If, however, the input signal&#39;s rising edge initially rises above Vhi but then momentarily falls back below Vlo during the rising edge glitch 16, the buffer circuit will fail by producing an undesired LO output pulse 20, as illustrated in FIG. 3c. Similarly, if the falling edge glitch 18 arises above Vhi after the circuit has resumed a LO output, the circuit will fail by producing an undesired HI pulse 22 after the input pulse has terminated. The input signal is commonly a periodically alternating signal, such as a clock signal, in which the period between successive alternations is known. With such input signals, the circuit failures illustrated in FIG. 3c can reoccur at each alternation in the input signal. 
     One approach to overcoming this failure problem would be to simply increase the amount of hysteresis by making P3pa and N3pa larger. However, increasing the hysteresis can move the switching points out of the permissible Vhi-Vlo window under certain combinations of processing, temperature and power supply voltage variations. To leave adequate head room between the design switching levels and the window limits to allow for these factors, the amount of hysteresis that can be designed into the circuit is limited. 
     SUMMARY OF THE INVENTION 
     The present invention seeks to provide a new circuit and operating method for inhibiting unintentional switching of a Schmitt trigger circuit, without risk of operating beyond the window limits of Vhi or Vlo. The circuit is intended for use with an alternating input signal, such as a clock signal, that has a known minimum period between alternations. 
     These goals are accomplished with an input buffer circuit that switches from a LO to a HI output state when an input signal rises through LO and HI threshold levels that are separated by a hysteresis amount, and inhibits a reversion to the LO output state for a temporary delay period following the first switching transition, unless the input signal falls below a boosted LO threshold level that is less than the original LO threshold during this period. The delay period is no greater than the known minimum period between input signal alternations, and after it expires the original LO threshold level is restored. A similar operation is provided for a falling input signal, with the circuit switching from a HI to a LO output state when the input signal falls successively through the original HI and LO threshold levels, followed by a temporary period during which the HI threshold is boosted. Again, the boosted threshold level is removed after a delay period that is no greater than the known minimum period between signal alternations. Since the boosted thresholds are removed before the next input signal alternation can occur, they provide additional protection against unintentional switching during the interval between signal alternations. While the operational threshold levels that are in effect when the input alternations actually occur are held within the permissible threshold window, the boosted threshold levels can extend outside the window. 
     In this manner fixed threshold levels are established that are within the permissible window, but are temporarily overridden by the boosted threshold levels following an input transition. In a preferred embodiment, the boosted hysteresis level is provided by an additional MOS hysteresis transistor that is scaled larger than the normal hysteresis transistor, and thus provides a larger hysteresis. The original hysteresis transistors are connected in parallel with their respective boosted transistors, and a logic circuit interfaces between a delay circuit and the gates of the boosted transistors to hold the latter devices operational only during the delay periods. Multiple capacitors and inverters are preferably employed for the delay circuit to obtain symmetric delays for both rising and falling input signals. In another embodiment, a separate switch is placed in the source-drain circuit for each boosted hysteresis transistor. The switches are controlled by associated logic circuitry to disable the boosted hysteresis transistors after the desired delay period. 
     These and further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a voltage plot of a typical Schmitt trigger operation, described above; 
     FIG. 2 is a simplified schematic diagram of a prior Schmitt trigger circuit design, described above; 
     FIGS. 3a, 3b and 3c are respectively diagrams of an input voltage waveform, an idealized Schmitt trigger response and a Schmitt trigger response that has failed due to glitches in the input signal, described above; 
     FIG. 4 is a voltage diagram that illustrates the variable threshold scheme employed by the invention; 
     FIG. 5 is a schematic diagram showing one embodiment of the invention that can be used to prevent a Schmitt trigger from responding to unintentional glitches in the input signal; and 
     FIG. 6 is a schematic diagram of an improved embodiment of the invention that achieves a faster operation. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The basic approach taken by the invention to preventing unintentional changes of output state from a Schmitt trigger buffer circuit due to glitches in the input signal is illustrated in FIG. 4. An input signal 24 is shown with a periodic alternation between HI and LO states 26 and 28. Although the input signal 24 is shown as a square wave for simplification, in practice it would normally have noise and other distortions imposed upon it. 
     Schmitt trigger circuits are commonly used with input signals having a regular periodic variation between HI and LO states over time, such as clock signals. With such signals there is some ambiguity as to the actual pulse durations and intervals between pulses, due to variable process, temperature and power supply factors. However, the clock circuits are designed so that the pulse durations, the intervals between pulses and the overall signal periodicity will at least equal minimum specified durations over specified ranges of these variables. For example, a clock signal may be used in which the duration of each HI pulse is at least 28 nsec, the duration of each LO interval between pulses is at least 28 nsec, and the overall clock period between the beginning of one HI pulse and the beginning of the next HI pulse is at least 80 nsec. Thus, although the exact time characteristics of the clock signal would not normally be known in advance, it would be known that there will be an interval of at least 28 nsec between a rising signal edge and the next falling signal edge, and another interval of at least 28 nsec between the falling signal edge and the following rising edge. 
     The invention makes use of these known minimum signal time characteristics by substantially increasing the circuit&#39;s hysteresis during the period following a signal transition when it is known that another valid transition cannot occur, and then restoring the original smaller hysteresis level so that when the next valid signal transition does occur the circuit&#39;s hysteresis is within the acceptable window for switching thresholds. 
     In the upper portion of FIG. 4, the normal switching thresholds are indicated by Vhi and Vlo, with the normal hysteresis equal to Vhi-Vlo. The upper and lower switching threshold limits that define the permissible switching window are identified as Vwhi and Vwlo, respectively. When the rising edge 30 of the HI input pulse 26 is sensed, the lower threshold level Vlo is switched to a reduced level V&#39;lo. This results in a greater amount of hysteresis, indicated by shading in the figure, between the HI and LO threshold levels Vhi and V&#39;lo. To switch the output back to LO state, the input signal must now drop below V&#39;lo, which would require a considerably greater glitch than when the lower threshold was Vlo. The value of V&#39;lo is selected so that it is far enough below Vhi to prevent all normally expected glitches from triggering a change of output state. 
     The V&#39;lo threshold level is maintained for a period of time no greater than the minimum time before the arrival of the next valid falling input signal edge at the end of the HI pulse; this time period is indicated as T HImin  in the figure. At the end of this period the lower threshold level reverts to Vlo, and remains there until the following input signal edge at the end of the HI pulse arrives. Thus, a normal hysteresis level prevails for the active period during which valid switching can take place, depending upon the actual duration of the HI signal beyond its minimum period. This active switching period for the HI signal is identified in the figure as T HIA . When the HI pulse&#39;s falling edge 32 does arrive, the lower switching threshold remains at Vlo but the upper threshold increases to a higher level V&#39;hi, and remains at its boosted level for a period up to but no greater than the minimum duration for the LO input signal state T LOmin . During this period the boosted hysteresis prevents the circuit from unintentionally triggering to a HI output. The Vhi threshold level is restored at the end of this minimum period T LOmin , and continues in effect through the remainder of the active switching period T LOA  until the arrival of the rising edge 34 of the next HI pulse. 
     In this manner, unintentional triggering is inhibited for the majority of the circuit&#39;s operation, particularly during and immediately after the critical rising and falling pulse edges, and yet a normal hysteresis level prevails during all times when a valid input signal transition can be expected, thus enabling a rapid response to the transition. Either one or both of the boosted threshold levels V&#39;lo and Vhi can extend beyond the respective threshold window limits Vwlo and Vwhi, if desired. This is permissible because the window establishes the threshold limits for valid switching, and by definition no valid switching can occur during the boosted hysteresis periods. The system thus prevents unintentional changes of output state due to glitches in the input signal, and yet does not interfere with valid switching. 
     One circuit that can be used to implement this glitch protection function is shown in FIG. 5. This circuit builds upon the basic Schmitt trigger circuit of FIG. 2, and uses the same reference numerals to identify the same elements. In addition, a PMOS transistor P4 has it source-drain circuit connected between node 8 and NMOS switching transistor N5, while an additional NMOS transistor N4 has its source-drain circuit connected between node 10 and a switching PMOS transistor P5. P4 and N4 are scaled substantially larger than P3pa and N3pa to provide the boosted V&#39;hi and V&#39;lo hysteresis levels, respectively, with the gate of each device connected to the internal output line 12. They are switched into and out of the circuit by the switch transistors N5 and P5, which have their source-drain circuits connected between P4 and N4 to ground and Vdd, respectively. The gates of N5 and P5 are controlled by logic circuits that turn them on, allowing their associated boosted hysteresis transistors P4 and N4 to conduct during the boosted hysteresis periods T LOmin  and T HImin , respectively. At all other times the transistors N5 and P5 are off and prevent their hysteresis transistors P4 and N4 from conducting, thus rendering them inactive. 
     A second inverter INV2 at the output of INV1 provides an input signal for a timing circuit 36. With CMOS technology the timing circuit is conveniently implemented by an NMOS transistor that has its source and drain tied to ground to function as one plate of a capacitor, with its gate serving as the other plate and the gate insulation as the capacitor dielectric. When T HImin  is equal to T LOmin , a single delay circuit 36 can be used to provide equal periods for V&#39;lo and V&#39;hi; separate delay circuits would be used for each boosted hysteresis level if their durations were different. 
     A NOR gate at NOR1 is provided to control the gate of transistor N5, while a NAND gate NAND1 is provided to control the gate of P5. Each of these gates receives an input from internal output line 12, and another input from the timing circuit 36 that has been inverted by inverter INV3. At the beginning of a HI pulse, the signal on output line 12 goes LO and is applied to both of the logic gates. However, because of the delay associated with delay circuit 36, the other inputs to the logic gates remain HI. 
     While it offers effective protection against input glitches, the circuit of FIG. 5 is not optimum. Each device connected to the internal output line 12 adds a capacitive factor which, in the aggregate, can slow down the circuit&#39;s response to a change in the input signal. In the FIG. 5 circuit there are six such devices connected to the internal output line (P3pa, N3pa, P4, N4, NOR1 and NAND1). Also, taking the input to the delay circuit from the output terminal 14 makes the delay circuit vulnerable to capacitive effects from the output load, which if strong enough can change the delay period. It would be better to isolate the delay circuit from the output load. 
     An improved circuit is shown in FIG. 6 that addresses both of these problems. In this circuit, boosted hysteresis transistors P6 and N6 are connected with their source-drain circuits in parallel with the source-drain circuits of P3pa and N3pa, respectively. Control signals are applied to the gates of P6 and N6 to turn them ON during their respective boosted hysteresis periods, and to hold them OFF at other times. 
     Logic switching circuits for P6 and N6 include a NAND gate NA3D2 having its output connected to the gate of P6, and a NOR gate NOR2 having its output connected to the gate of N6. Each of these logic gates receives an input from an inverter INV4 that inverts the signal on internal output line 12. The delay circuit preferably consists of a pair of series-connected inverters INV5 and INV6, with charging capacitors C1 and C2 connected to their respective outputs. (Although a single inverter and capacitor could be used, two capacitors and two inverters are preferable so that symmetric delays are achieved for rising and falling input signals. Each inverter includes a pair of PMOS and NMOS transistors, which in practice are generally not precisely matched; a pair of inverters is used in the delay circuit to balance the P and N devices.) A third inverter INV7 is provided at the output of INV6 to sharpen the edges of the delay signal, which otherwise would rise and fall relatively slowly because of the capacitors. The output from INV7 is applied to the second inputs of the NAND2 and NOR2 gates. 
     In operation, a transition from a HI to a LO state on internal output line 12 produces HI inputs to NAND2 and NOR2 from INV4. The other input to these gates from INV7 was HI immediately before the input signal transition, and remains HI because of the delay circuit. As a result, NAND2 and NOR2 both produce LO outputs which set P6 ON and N6 OFF, reducing the lower threshold level to V&#39;lo. At the end of the delay period, the second input to both logic gates goes LO, causing NAND2 to change state and turn P6 OFF while leaving NOR2 in the same state holding N6 OFF. When the input signal thereafter falls back to a LO state, setting the internal output line 12 HI, the logic gates receive LO signals from both INV4 and INV7. This sets both NAND2 and NOR2 HI, holding P6 OFF and N6 ON and boosting the HI threshold level to V&#39;hi. After the delay period the output of NAND2 remains HI while the output of NOR2 goes LO, holding both P6 and N6 OFF and restoring the original hysteresis level Vhi-Vlo. 
     The FIG. 6 circuit thus functions in the manner illustrated in FIG. 4, and yet reduces the number of devices connected to the internal output line 12 by half compared to the FIG. 5 circuit. Furthermore, it avoids having to connect any logic or delay elements to the output terminal 14. 
     The absolute threshold and hysteresis levels that are achieved depend upon the device scalings. In one implementation of the FIG. 6 circuit Vhi was 1.5 volts, Vlo was 1.3 volts, V&#39;hi was 2.1 volts and V&#39;lo was 0.9 volts (all approximate). These threshold levels were achieved with C1 and C1 capacitances of 0.5 pf each and the following device scalings, in which the first and second digits respectively indicate the transistor widths and lengths in microns: 
     
         ______________________________________P0pa        3:1   N0pa         6:1P1pa        6:1.5 N1pa        18:1.5P2pa        6:1.5 N2pa        18:1.5P3pa      4.5:1.5 N3pa        (not used)P6pa       20:1.5 N6pa         6:1.5______________________________________ 
    
     The widths of each of the devices in the inverters and logic gates as 3 microns except for INV1 and INV4, for which the widths were 6 microns and 4.5 microns, respectively. 
     Although FIG. 6 represents the preferred embodiment, it is not absolutely necessary to use all of the hysteresis elements shown in this circuit. For example, consider that the base hysteresis level Vhi-Vlo is established by P3pa and N3pa. Even if N3pa were eliminated, P3pa would still establish a base hysteresis, although it would be half that established by P3pa and N3pa acting together (assuming the two transistors had equal scalings). While the original base hysteresis magnitude could be recaptured by scaling P3pa larger, the hysteresis level increases less than linearly with transistor size, and a much larger P3pa would be required. Since it becomes more difficult to control the circuit operation when the scalings of different transistors differ by significant amounts, dividing the base hysteresis function between the two transistors P3pa and N3pa is generally preferable. 
     A more extreme variation would be to eliminate both P3pa and N3pa. This would not significantly effect the boosted hysteresis levels because the parallel combination of P6 and P3pa is dominated by P6 when that device is ON, and similarly for the parallel combination N6 and N3pa. However, eliminating both of the base hysteresis transistors would eliminate all glitch protection during the intervals between the end of the delay period and the next input transition (T HIA  and T LOA  in FIG. 4). 
     An even more extreme variation would be to eliminate either P6 or N6, but not both, along with P3pa and N3pa. This would eliminate glitch protection except during the period T HImin  or T LOmin  of FIG. 4, but there may be circumstances in which it would be acceptable. 
     While particular embodiments of the invention have been shown and described, numerous variations and alternate embodiments will occur to those skilled in the art. Accordingly, it is intended that the invention be limited only in terms of the appended claims.