Abstract:
The present invention discloses an overcurrent detection device, which uses a first NOT gate and a second NOT gate to reverse the logic states of a first digital signal and a second digital signal which are digitalized audio signals in a class D power amplifier. Next, a CMOS transistor receives the reversed digital signals and drives a load. A comparing circuit detects the current of the load and compares the current with the reversed first and second digital signals. When the current of the load is too high, the comparing circuit respectively outputs a first electrical signal and a second electrical signal to a first logic gate and a second logic gate. Then, the logic gate outputs a signal to activate a protection circuit to prevent the entire circuit be damaged or burned out.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a detection device, particularly to an overcurrent detection device. 
   2. Description of the Related Art 
   With the prevalence of IC technology, CMOS (Complementary Metal Oxide Semiconductor) is also extensively used in various electronic elements, such as the Class-D audio power amplifier. The Class-D audio power amplifier is a high-efficiency amplifier outputting only two states (1 and 0) and usually used to drive a high-load speaker. As the Class-D audio power amplifier has very high energy conversion efficiency, it has been widely used in portable electronic products and can reduce the power consumption of portable electronic products. Thus, the standby time is prolonged, and the portability of electronic products is increased. 
   Refer to  FIG. 1  for a conventional overcurrent detection device. A common power amplifier uses a current detector to detect the load current. When the current is over a given value, a protection circuit is triggered. Such an architecture usually needs a comparator  10  and a detection resistor  12 . The comparator  10  receives the voltages at two terminals of the detection resistor  12  as the input signals and outputs a voltage signal to trigger a protection circuit. 
   In a class D power amplifier the audio signal is a digital signal and the conventional current detector can no longer be applied. Therefore the present invention proposes an overcurrent detection scheme, which achieves overcurrent detection by applying digitalized audio signal as control signal. Therefore, the present invention proposes an overcurrent detection device, which detects the overcurrent of the load through digitalized audio signal. 
   SUMMARY OF THE INVENTION 
   The primary objective of the present invention is to provide an overcurrent detection device, which can accurately detect the overcurrent of the load in real time via a digital circuit and digital signals. 
   Another objective of the present invention is to provide an overcurrent detection device, which detects the overcurrent of the load through digitalized audio signal. 
   To achieve the abovementioned objectives, the present invention proposes an overcurrent detection device, which comprises: a first NOT gate and a second NOT gate. The first NOT gate and the second NOT gate respectively receive a first digital signal and a second digital signal, digitalized audio signal, from the input terminals thereof and reverse the logic states of the first digital signal and the second digital signal. A CMOS (Complementary Metal Oxide Semiconductor) transistor is coupled to the output terminals of the first and second NOT gates to receive the reversed first and second digital signals and drives a load. The output terminals of the CMOS and NOT gates are coupled to a comparing circuit. The comparing circuit receives the reversed first and second digital signals from two terminals thereof, detects the current of the load, compares the detection result with the first and second digital signals and then selectively outputs a first electrical signal and a second electrical signal. A first logic gate and a second logic gate are coupled to the comparing circuit, respectively receive the first and second electrical signals and output a first signal and a second signal to a protection circuit. 
   Below, the preferred embodiments are to be described in detail in cooperation with the drawings to make easily understood the technical contents, characteristics and efficacies of the present invention. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a diagram schematically showing the circuit of a conventional overcurrent detection device; 
       FIG. 2  is a diagram schematically showing the circuit of an overcurrent detection device according to the present invention; 
       FIG. 3   a  is a diagram schematically showing a portion of the circuit of an overcurrent detection device according to the present invention; 
       FIG. 3   b  is a diagram schematically showing the signal waveforms at some nodes of the circuit of an overcurrent detection device according to the present invention; 
       FIG. 4   a  is a diagram schematically showing another portion of the circuit of an overcurrent detection device according to the present invention; and 
       FIG. 4   b  is a diagram schematically showing the signal waveforms at some other nodes of the circuit of an overcurrent detection device according to the present invention. 
   

   Like item numbers denote like items in the various drawings. 
   DETAILED DESCRIPTION OF THE INVENTION 
   Refer to  FIG. 2  a diagram schematically showing the circuit of an overcurrent detection device according to the present invention. The device of the present invention comprises: a first NOT gate  14  and a second NOT gate  16 , which respectively receive a first digital signal and a second digital signal from the input terminals thereof and reverse the logic states of the digital signals, wherein the digital signals may be identical or different in timing. 
   The output terminals of the first NOT gate  14  and the second NOT gate  16  are coupled to a CMOS (Complementary Metal Oxide Semiconductor) transistor  50 . The CMOS transistor  50  receives the reversed first digital signal and the reversed second digital signal and drives a load  22 . The CMOS transistor  50  includes: a PMOSFET  18  (P-channel Metal Oxide Semiconductor Field Effect Transistor) and an NMOSFET  20  (N-channel Metal Oxide Semiconductor Field Effect Transistor). The CMOS transistor  50  and the output terminals of the first NOT gate  14  and second NOT gate  16  are coupled to a comparing circuit  52 . Two terminals of the comparing circuit  52  respectively receive the reversed first digital signal and the reversed second digital signal. The comparing circuit  52  detects the current of the load  22  and compares the detection result with the first digital signal and the second digital signal received from the two terminals and then selectively outputs a first electrical signal and a second electrical signal. The comparing circuit  52  includes: a first comparing circuit  522  and a second comparing circuit  524 , which respectively generate the first electrical signal and the second electrical signal. The first comparing circuit  522  further comprises: a PMOSFET  24 , a first resistor  26 , a second resistor  28  and a comparator  36 . The second comparing circuit  524  further comprises: an NMOSFET  34 , a third resistor  30 , a fourth resistor  32  and a second comparator  38 . A first logic gate  54  is coupled the comparing circuit  52  to receive the first digital signal and the first electrical signal from the input terminal thereof and outputs a first signal from the output terminal thereof. A second logic gate  56  is coupled the comparing circuit  52  to receive the second digital signal and the second electrical signal from the input terminal thereof and outputs a second signal from the output terminal thereof. The first logic gate  54  may be a NOR gate  40 , and the second logic gate  56  may be an AND gate  42 . The negative input terminal of the first comparator  36  is coupled to the positive input terminal of the second comparator  38 . The drain of the PMOSFET  18  is coupled to the drain of the NMOSFET  20 . One side of the load  22  is coupled to the joint of the drain of the PMOSFET  18  and the drain of the NMOSFET  20 , and the same side of the load  22  is also coupled to the joint of the negative input terminal of the first comparator  36  and the positive terminal input terminal of the second comparator  38 . The other side of the load  22  is coupled to a reference voltage V REF . 
   Below, the detail of the abovementioned circuit is described. The source of the PMOSFET  18  is coupled to a DC voltage V DD , and the gate of the PMOSFET  18  is coupled to the output terminal of the first NOT gate  14 . The gate of the PMOSFET  18  is also coupled to the gate of another PMOSFET  24 . The source of the PMOSFET  24  is coupled to the DC voltage V DD , and the drain of the PMOSFET  24  is coupled to one side of the first resistor  26 . The other side of the first resistor  26  is coupled to the drain of the PMOSFET  18  via the second resistor  28 . The positive input terminal and negative input terminal of the first comparator  36  are respectively coupled to two sides of the second resistor  28 , and the positive input terminal of the first comparator  36  is coupled to a point between the first resistor  26  and the second resistor  28 . The output terminal of the first comparator  36  is coupled to one input terminal of the NOR gate  40 , and the input terminal of the NOR gate  40  also receives the first digital signal. The output terminal of the NOR gate  40  outputs the first signal. The source of the NMOSFET  20  is grounded, and the gate of the NMOSFET  20  is coupled to the output terminal of the second NOT gate  16 . The input terminal of the second NOT gate  16  receives the second digital signal. The gate of the NMOSFET  20  is also coupled to the gate of another NMOSFET  34 . The source of the NMOSFET  34  is grounded, and the drain of the NMOSFET  34  is coupled to one side of the fourth resistor  32 . The other side of the fourth resistor  32  is coupled to the drain of the NMOSFET  20  via the third resistor  30 . The positive input terminal and negative input terminal of the second comparator  38  are respectively coupled to two sides of the third resistor  30 , and the negative input terminal of the second comparator  38  is coupled to between the third resistor  30  and the fourth resistor  32 . The output terminal of the second comparator  38  is coupled to one input terminal of the AND gate  42 , and the input terminal of the AND gate  42  also receives the second digital signal. The output terminal of the AND gate  42  outputs the second signal. 
   When the PMOSFET  18  is turned on and when the load  22  is too small or short-circuited to the ground, an overcurrent occurs. In such a case, overcurrent detection is undertaken by the upper part of the circuit of the present invention. When the NMOSFET  20  is turned on and when the load  22  is too small or short-circuited to the DC voltage V DD , an overcurrent occurs. In such a case, overcurrent detection is undertaken by the lower part of the circuit of the present invention. As the digital signal can make only one MOSFET turned on, the present invention is suitable to be integrated with the circuit using CMOS transistors. 
   The operation of the upper part of the circuit of the present invention is to be independently described in detail below. Refer to  FIG. 3   a  and  FIG. 3   b . In  FIG. 3   a , one side of a load  46  is coupled to only the drain of the PMOSFET  18 , and the other side of the load  46  is coupled to a reference voltage V REF  (as ground).  FIG. 3   b  shows the waveforms of V 1p , V 2p , V 12p , V op  and V outp . Note the waveforms before the time T 1 . When V 1p  is a low-level digital signal, V 2p  is a high-level digital signal. At this time, the PMOSFET  18  and the PMOSFET  24  are not turned on; therefore, V 12p  is at V REF  voltage. At the same time, no voltage difference exists between two input terminals of the first comparator  36 . In other words, the threshold voltage of the first comparator  36  is not exceeded. Therefore, V op  is a high-level digital signal. V 1p  and V op  are respectively input to the input terminals of the NOR gate  40 , and the output V outp  of the NOR gate  40  is thus a low-level digital signal. Refer to the waveforms between the time T 1  and the time T 2 . When V 1p  is a high-level digital signal, V 2p  is a low-level digital signal. As the first NOT gate  14  delays outputting the signal slightly, the waveform slowly descends initially. At this time, the PMOSFET  18  and the PMOSFET  24  are both turned on, and the voltage V 12p  rises to a high level and maintains at the high level. For normal operation, the voltage difference between two input terminals of the first comparator  36  does not exceed the threshold voltage of the first comparator  36 . Therefore, V op  is also a high-level digital signal. Because of the input signals V op  and V 1p , the NOR gate  40  outputs a low-level digital signal V outp . However, when the current of the load  46  is too high or exceeds a critical value due to abnormal small value of load  46  or short circuit across load  46  or short circuit between V 12p  and any low voltage, the voltage V 12p  will decrease, as shown by the dotted line. At the same time, the voltage difference between two input terminals of the first comparator  36  exceeds the threshold voltage of the first comparator  36 . Therefore, V op  becomes a low-level digital signal. As the first comparator  36  also delays outputting the signal, the first comparator  36  takes a period of time to make V op  become a low-level digital signal shown by the dotted line. Because of the input signals V op  and V 1p , the output signal V outp  is a low-level digital signal. Refer to the waveforms after the time T 2 . When V 1p  descends to a low-level digital signal, V 2p  gradually rises to a high-level digital signal, and V 12p  is also gradually restored to a low-level digital signal. As the first comparator  36  delays outputting the signal, V op  takes a period of time to rise to a high-level digital signal. Because of the input signals V op  and V 1p , the NOR gate  40  outputs a positive pulse signal. The positive pulse signal is used to trigger a protection circuit to prevent the entire circuit from burnout. Thus the load current exceeds an overcurrent threshold, the positive pulse signal is sent out to trigger the protection circuit. 
   The operation of the lower part of the circuit of the present invention is also to be independently described in detail below. Refer to  FIG. 4   a  and  FIG. 4   b . In  FIG. 4   a , one side of a load  44  is coupled to only the drain of the NMOSFET  20 , and the other side of the load  44  is coupled to a voltage V REF  (as V DD ).  FIG. 4   b  shows the waveforms of V 1n , V 2n , V 12n , V on  and V outn . Note the waveforms before the time T 1 . When V 1n  is a high-level digital signal, V 2n  is a low-level digital signal. At this time, the NMOSFET  20  and the NMOSFET  34  are not turned on; therefore, V 12n  is at V REF  voltage. At the same time, no voltage difference exists between two input terminals of the second comparator  38 . In other words, the threshold voltage of the second comparator  38  is not exceeded. Therefore, V on  is a low-level digital signal. V 1n  and V on  are respectively input to the input terminals of the AND gate  42 , and the output V outn  of the AND gate  42  is thus a low-level digital signal. Refer to the waveforms between the time T 1  and the time T 2 . When V 1n  is a low-level digital signal, V 2n  is a high-level digital signal. As the second NOT gate  16  delays outputting the signal slightly, the waveform slowly rises initially. At this time, the NMOSFET  20  and the NMOSFET  34  are both turned on, and the voltage V 12n  descends to a low level and maintains at the low level. At the same time, the voltage difference between two input terminals of the second comparator  38  does not exceed the threshold voltage of the second comparator  38 . Therefore, V on  is also a low-level digital signal. Because of the input signals V on  and V 1n , the AND gate  42  outputs a low-level digital signal V outn . However, when the current of the load  44  is too high or exceeds a critical value due to abnormal small value of load  44  or short circuit across load  44  or short circuit between V 12n  and any high voltage, the voltage V 12n  will rise, as shown by the dotted line. At the same time, the voltage difference between two input terminals of the second comparator  38  exceeds the threshold voltage of the second comparator  38 . Therefore, V on  becomes a high-level digital signal. As the second comparator  38  also delays outputting the signal, the second comparator  38  takes a period of time to make V on  become a high-level digital signal shown by the dotted line. Because of the input signals V on  and V 1n , the output signal V outn  is a low-level digital signal. Refer to the waveforms after the time T 2 . When V 1n  rises to a high-level digital signal, V 2n  gradually descends to a low-level digital signal, and V 12n  is also gradually restored to a high-level digital signal. As the second comparator  38  delays outputting the signal, V on  takes a period of time to descend to a low-level digital signal. Because of the input signals V on  and V 1n , the AND gate  42  outputs a positive pulse signal. The positive pulse signal is used to trigger a protection circuit to prevent the entire circuit from burnout. Thus the load current exceeds an overcurrent threshold, the positive pulse signal is sent out to trigger the protection circuit. Note that there is a difference between the second comparator  38  and the first comparator  36 . When the voltage difference across the input terminals of the first comparator  36  exceeds the threshold of the first comparator  36 , the first comparator  36  outputs a low-level digital signal. However, when the voltage difference across the input terminals of the second comparator  38  exceeds the threshold of the second comparator  38 , the second comparator  38  outputs a high-level digital signal. 
   In conclusion, the present invention proposes an overcurrent detection device, which can accurately detect the overcurrent of the load in realtime via a digital circuit and digital signals, and which can integrate with CMOS to meet the trend of miniaturization and power efficiency. 
   The preferred embodiment described above is only to exemplify the present invention but not to limit the scope of the present invention. Therefore, any equivalent modification or variation according to the spirit or characteristics of the present invention is to be also included within the scope of the present invention.