Abstract:
A semiconductor apparatus includes: a through-silicon via (TSV) formed in a silicon substrate; a first insulating layer formed to surround side and bottom portions of the TSV such that the TSV is isolated from the silicon substrate; a first conductive layer interposed between the first insulating layer and the silicon substrate and formed outside the TSV to surround the TSV.

Description:
CROSS-REFERENCES TO RELATED APPLICATION 
       [0001]    The present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2012-0096994, filed on Sep. 3, 2012, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    Various embodiments relate to a semiconductor apparatus, and more particularly, to a semiconductor apparatus having through-silicon vias (TSVs) and a test method thereof. 
         [0004]    2. Related Art 
         [0005]    With the development of semiconductor memory technology, high integration and high performance have been required for packaging technology for a semiconductor integrated circuit apparatus. Thus, in order to replace a two-dimensional (2D) structure in which semiconductor chips having an integrated circuit implemented therein are two-dimensionally arranged over a printed circuit board (PCB) through a wire or bump, a variety of three-dimensional (3D) structures have been developed in which a plurality of semiconductor chips are vertically stacked. 
         [0006]    The 3D structure may be implemented through stack packaging technology. The stack package technology may be roughly divided into technology for packaging stacked semiconductor chips at a time and technology for stacking individually-packaged semiconductor chips. 
         [0007]    The semiconductor chips stacked in a vertical direction to a surface of the semiconductor chip are mounted on a substrate for a semiconductor package, while electrically coupled to each other through metallic wires or TSVs. 
         [0008]    When metallic wires are used in a stack package, performance may be reduced because electrical signals are exchanged through the metallic wires has long length. Since a large number of wires are used, electrical characteristics for example, a short between neighboring wires, may be degraded. Furthermore, since the semiconductor substrate may require an additional area to prevent the short between the neighboring wires, the entire size of the package may be increased. Since a gap for wire bonding between the semiconductor chips is required, the height of the package may be increased. 
         [0009]    On the other hand, a stack package using TSVs has a structure which couples semiconductor chips in a vertical direction so as to couple transistors or interconnections formed over a chip to the bottom of the chip. The stack package may reduce a distance between the upper and lower chips to thereby reduce a signal loss, than the stack package having the wire bonding structure. Thus, high-speed and low-power communication may be realized between the chips. In particular, when the TSV is electrically applied as a power line, an off-chip driver may be designed to have low power consumption. Thus, the duration of use for mobile electronic products may be increased to secure high marketability. 
         [0010]    Referring to  FIG. 1 , the semiconductor memory device includes a plurality of chips  10 _ 1 ,  10 _ 2 , and  10 _ 3  which are physically and electrically stacked using TSVs  20 . Each of the chips has a cell area and a peripheral circuit area for realizing the function of the semiconductor memory device. 
         [0011]    Among the plurality of chips, the chip  10 _ 1  positioned at the lowermost part is a master chip to buffer an external signal applied from an external controller, and the chips  10 _ 2  to  10   —   n  positioned over the master chip  10 - 1  are slave chips which are physically or electrically connected to the master chip  10 - 1  using the TSVs  20 . 
         [0012]    Referring to  FIGS. 2 and 3 , the TSV  20  is formed through a silicon substrate  30 , that is, each chip  10 - 1 ,  10 - 2 , or  10 - 3 . The silicon substrate  30  is a P-type silicon substrate having a low doping concentration or N-type silicon substrate having a low doping concentration. The TSV  20  is made of a conductive material including a metal such as copper (Cu). Furthermore, an insulating material  40  made of thin silicon oxide (SiO 2 ) is formed between the TSV  20  and the silicon substrate  30 . 
         [0013]    Thus, the TSV  20  and the peripheral structure thereof may form a MOS capacitor structure, which includes the TSV  20  made of a conductive material, the insulating material  40 , and the silicon substrate  30 . 
         [0014]    As such, the TSV  20  is provided to couple the plurality of chips  10 _ 1 ,  10 _ 2 , and  10   —   n  and is additionally formed in a completed semiconductor memory device. Thus, in order for the semiconductor memory device to perform an accurate operation and in order to develop the packaging technology for 3D structures, a test should be performed on the TSV. 
         [0015]    However, a TSV test is performed after packaging is completed. That is, a TSV has been tested in a state where a plurality of chips are stacked and completely packaged. Then, when a fail is discovered in the tested TSV, the failed TSV is replaced to a redundancy TSV. 
         [0016]    Therefore, a necessary number of redundancy TSVs should be prepared according to a TSV fail ratio. When fails of the TSV are larger than the prepared redundancy TSVs, the entire stack package should be discarded. Furthermore, when a fail is not discovered in the TSV, the prepared redundancy TSVs become useless. Thus, the fabrication cost inevitably increases due to the unnecessary redundancy TSVs. 
       SUMMARY 
       [0017]    In an embodiment, a semiconductor apparatus includes: a through-silicon via (TSV) formed in a semiconductor substrate; a first insulating layer formed to surround side and bottom portions of the TSV such that the TSV is isolated from the semiconductor substrate; a first conductive layer interposed between the first insulating layer and the semiconductor substrate and formed outside the TSV to surround the TSV. 
         [0018]    In an embodiment, a semiconductor apparatus includes: a semiconductor substrate; a through-silicon via (TSV) formed to be penetrated in a semiconductor substrate; a test conductive layer formed to surround a circumference of the TSV; an insulating layer formed between the TSV and the test conductive layer, wherein a fail of TSV is determined by a voltage between the TSV and the test conductive layer 
         [0019]    In an embodiment, a test method of a semiconductor apparatus includes the steps of: applying voltages to a bump electrically coupled to a through-silicon via (TSV) and a first conductive layer formed to surround the TSV, respectively; measuring a voltage between the bump and the first conductive layer; comparing the measured voltage to a preset reference voltage; and determining the TSV as a normal TSV in which no fail occurs, according a comparing result. 
         [0020]    In an embodiment, a test method of a semiconductor apparatus includes the steps of: forming a through-silicon via (TSV) in a semiconductor substrate; forming a test conductive layer to surround of a circumference of the TSV, with insulating from the TSV; applying a first voltage to the TSV; applying a second voltage being different from the first voltage to the test conductive layer; determining a fail of the TSV using to a voltage between the first voltage and the second voltage; and packaging a resultant of the semiconductor substrate. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0021]    Features, aspects, and embodiments are described in conjunction with the attached drawings, in which: 
           [0022]      FIG. 1  schematically illustrates the structure of a 3D semiconductor memory device in which a plurality of chips are stacked through a TSV; 
           [0023]      FIG. 2  is a plan view of a region “A” of  FIG. 1 ; 
           [0024]      FIG. 3  is a cross-sectional view of the region “A” of  FIG. 1 ; 
           [0025]      FIG. 4  illustrates a TSV structure according to an embodiment; 
           [0026]      FIG. 5  schematically illustrates a TSV test method according to a first embodiment; 
           [0027]      FIG. 6  is a flowchart illustrating the TSV test method according to the first embodiment; 
           [0028]      FIG. 7  schematically illustrates a TSV test method according to a second embodiment; 
           [0029]      FIG. 8  is a flowchart illustrating the TSV test method according to the second embodiment; 
           [0030]      FIG. 9  schematically illustrates a TSV test method according to a third embodiment; and 
           [0031]      FIG. 10  is a flowchart illustrating the TSV test method according to the third embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0032]    Hereinafter, a semiconductor apparatus having TSVs and a test method thereof according to the present invention will be described below with reference to the accompanying drawings through exemplary embodiments. 
         [0033]    Referring to  FIG. 4 , a vertical through-silicon via(TSV)  102  may be formed in a P-type or N-type silicon substrate  100  having a low doping concentration. The TSV  102  may be made of a conductive material, for example a metal such as Cu. 
         [0034]    Between the TSV  102  and the silicon substrate  100 , a first insulating layer  104  made of a high-k material (k is dielectric constant) may be formed. Thus, the TSV  102  and a peripheral structure represented by symbol “B” may form a MOS capacitor structure, which includes the TSV  102  made of a conductive material, the first insulating layer  104  made of an insulating material, and the silicon substrate  100 . 
         [0035]    Between the first insulating layer  104  and the silicon substrate  100 , a first conductive layer  110  may be formed. The first conductive layer  110  may be made of Ti/Cu, for example. The first conductive layer  110  may be provided as a test layer. The first conductive layer  110  may be configured to be withdrawn to the surface of the semiconductor substrate  100 , to be connected to a voltage terminal, for example a ground terminal. 
         [0036]    An ohmic contact layer  106  may be formed at the surface of the silicon substrate  100  around the TSV  102 . A second insulating layer  108  may be formed over the ohmic contact layer  106 . The ohmic contact layer  106  may be formed of a doping area and the doping type and concentration of the ohmic contact  106  may be properly adjusted according to the condition of the silicon substrate  100 . For example, when the silicon substrate  100  is a P-type silicon substrate having a low doping concentration, the ohmic contact layer  106  is formed with an N+ well having a high doping concentration. On the other hand, when the silicon substrate  100  is an N-type silicon substrate having a low doping concentration, the ohmic contact layer  106  is formed with a P+ well having a high doping concentration. 
         [0037]    A second conductive layer  112  may be formed on the TSV  102 , and a bump  114  may be formed on the second conductive layer  112 . For example, the second conductive layer  112  may be made of Ni, and the bump  114  may be made of SnAu. The bump  114  may be used as an outer connecting member. 
         [0038]    Furthermore, a grinding line  116  may indicate a grinding position of a rear surface of a wafer, which is set to expose the TSV  102 . Thus, after the TSV  102  corresponding to a final unit structure is formed in the silicon substrate  100 , a grinding process is performed on the rear surface of the wafer (the silicon substrate:  100 ) to the grinding line  116  so as to expose the TSV  102 . That is, the TSV  102  may include a structure which penetrates the silicon substrate  100 . Then, the wafer (the silicon substrate:  100 ) may be sawed to separate the wafer into individual chips. Two or more chips may be vertically stacked on a package substrate (not shown), using TSVs, the stacked chips are molded, and solder balls are mounted on the bottom surface of the package substrate. Then, the stack package process is completed. 
         [0039]    For example, a VDD voltage applied through the bump  114  may be supplied to the TSV  102  through the second conductive layer  112 . The first conductive layer  110  may receive a ground voltage (or VSS voltage). 
         [0040]    In this embodiment, the test for the TSV  102  may perform at a wafer level. The wafer level refers to the state of a wafer before the wafer is sawed to separate unit chips on the wafer into individual chips. Thus, it is possible to prevent the increase of fabrication cost caused by unnecessary redundancy TSVs. 
         [0041]    Now, the TSV test method according to the embodiment of is the present invention will be described in more detail. 
         [0042]    Referring to  FIG. 5 , a first voltage, for example, a VDD voltage may be applied to the bump  114  positioned over the TSV  102  and a second voltage, for example, a VSS voltage may be applied to the first conductive layer  110  surrounding the TSV  102 . Then, a voltage between the bump  114  and the first conductive layer  110  may be directly measured by a voltage measuring block  120 , and whether or not a fail occurred in the TSV  102  may be checked according to the measurement result. 
         [0043]    Referring to  FIG. 6 , the VDD voltage may be applied to the bump  114  and the VSS voltage may be applied to the first conductive layer  110  surrounding the TSV  102 , at step S 200 . 
         [0044]    The voltage between the bump  114  and the first conductive layer  110  may be directly measured by the voltage measuring block  120 , at step S 202 . 
         [0045]    The measured voltage may be compared to a preset reference voltage, at step S 204 . 
         [0046]    According to the comparison result of the step S 204 , whether or not the measured voltage deviates from the preset reference voltage may be determined at step S 206 . 
         [0047]    As the determination result, when the measured voltage does not deviate from the preset reference voltage, the procedure may proceed to step S 208  to determine the TSV  102  as a normal TSV in which no fail occurs. 
         [0048]    On the other hand, when the measured voltage deviates from the preset reference voltage, the procedure may proceed to step S 210  to determine the TSV  102  as a failed TSV. 
         [0049]    Then, whether or not the failed TSV can be repaired may be determined at step S 212 . 
         [0050]    As the determination result, when the failed TSV can be repaired, the procedure may proceed to step S 214  to repair the failed TSV using a redundancy TSV. 
         [0051]    Then, the repaired TSV may be used as a normal TSV at the step S 214 . 
         [0052]    When it is determined at the step S 212  that the failed TSV cannot be repaired, the procedure may proceed to step S 218  at which the failed TSV is classified as a final failed TSV and then discarded. 
         [0053]    Referring to  FIG. 7 , the first voltage, for example, the VDD voltage may be applied to the bump  114  positioned over the TSV  102 , and the second voltage, for example, the VSS voltage may be applied to the first conductive layer  110  surrounding the TSV  102 , as above. Then, a sense amplifier  118  may be used to measure the voltage between the bump  114  and the first conductive layer  110 , and whether or not a fail occurred in the TSV  102  is checked according to the measurement result. That is, the sense amplifier  118  may be connected between the bump  114  and the first conductive layer  110 . A voltage measuring block  120  may be connected to the sense amplifier  118 . 
         [0054]    Referring to  FIG. 8 , the VDD voltage may be applied to the bump  114  and the VSS voltage may be applied to the first conductive layer  110  surrounding the TSV  102 , at step S 300 . 
         [0055]    The voltage between the bump  114  and the first conductive layer  110  is measured by the sense amplifier  118 , at step S 302 . 
         [0056]    Whether or not the measured voltage falls within an output voltage range VOH/VOL may be determined at step S 304 . 
         [0057]    As the determination result of the step S 304 , when the measured voltage falls within the output voltage range, the procedure may proceed to step S 306  to determine the TSV  102  as a normal TSV in which no fail occurs. 
         [0058]    On the other hand, when the measured voltage deviates from the output voltage range, the procedure may proceed to step S 308  to determine the TSV  102  as a failed TSV. 
         [0059]    Whether or not the failed TSV can be repaired may determine at step S 310 . 
         [0060]    As the determination result, when the failed TSV can be repaired, the procedure may proceed to step S 312  to repair the failed TSV using a redundancy TSV. 
         [0061]    Then, the procedure may proceed to step S 314  to use the repaired TSV as a normal TSV. 
         [0062]    On the other hand, when the failed TSV cannot be repaired, the procedure may proceed to step S 316  at which the failed TSV is classified as a final failed TSV and then discarded. 
         [0063]    Referring to  FIG. 9 , the first voltage, for example, the VDD voltage is applied to the bump  114  positioned over the TSV  102 , and the second voltage, for example, the VSS voltage is applied to the first conductive layer  110  surrounding the TSV  102 , as above. Then, a parasitic capacitor may be generated between the TSV  102 . Capacitance of the MOS capacitor may be measured using the sense amplifier  118  and a capacitor measuring block  125 , and whether or not a fail occurred in the TSV  102  is checked according to the measurement result. The MOS capacitor includes the TSV  102 , the first insulating layer  104 , and the silicon substrate  100 . 
         [0064]    Referring to  FIG. 10 , the VDD voltage may be applied to the bump  114  and the VSS voltage may be applied to the conductive layer  110  positioned under the bump  114 , at step S 400 . 
         [0065]    The capacitance of the MOS capacitor including the TSV  102 , the first insulating layer  104 , and the silicon substrate  100  may be measured through the sense amplifier  118  and the capacitance measuring block  125  at step S 402 . 
         [0066]    The measured capacitance may be compared to preset reference capacitance at step  404 . 
         [0067]    According to the comparison result of the step S 404 , whether or not the measured capacitance falls within the preset reference capacitance range may be determined through the sense amplifier  120  at step S 406 . 
         [0068]    As the determination result, when the measured capacitance falls within the preset reference capacitance range, the procedure may proceed to step S 408  to determine the TSV  102  as a normal TSV in which no fail occurs. 
         [0069]    On the other hand, when the measured capacitance does not fall within the preset reference capacitance range, the procedure may proceed to step S 410  to determine the TSV  102  as a failed TSV. 
         [0070]    Then, whether or not the failed TSV can be repaired may be determined at step S 412 . 
         [0071]    As the determination result, when the failed TSV can be repaired, the procedure may proceed to step S 414  to repair the failed TSV using a redundancy TSV. 
         [0072]    Then, the procedure may proceed to step S 416  to use the repaired TSV as a normal TSV. 
         [0073]    On the other hand, when the failed TSV cannot be repaired, the procedure may proceed to step S 418  at which the failed TSV is classified as a final failed TSV and then discarded. 
         [0074]    According to the conventional test method, whether or not a fail occurred in a TSV is tested after packaging is completed. Therefore, when the number of redundancy TSVs for repairing failed TSVs is smaller than needed, the entire memory should be discarded, and a larger number of redundancy TSVs than needed should be provided to repair the failed TSVs. Thus, the entire fabrication cost inevitably increases. 
         [0075]    According to the embodiments of the present invention, however, whether or not a fail occurred in a TSV may be tested at the wafer level before packaging, in order to filter a TSV in which a fail such as open/short/leakage/void occurred. Then, as a repair process using a redundancy TSV is performed if necessary, the discard rate of the memory package may be lowered, and the fabrication cost may be reduced. 
         [0076]    While certain embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of example only. Accordingly, the semiconductor apparatus described herein should not be limited based on the described embodiments. Rather, the semiconductor apparatus described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.