Abstract:
Apparatus and methods for providing multi-mode clock signals are disclosed. In some embodiments, a multi-mode driver configured to receive a first clock signal, and to selectively output a different clock signal in response to one or more signals from a controller is provided. The driver can include an H-bridge circuit without substantial increases in the size of the design area. Advantageously, lower jitter and improved impedance matching can be accomplished.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation of U.S. patent application Ser. No. 12/606,142, filed Oct. 26, 2009, titled “APPARATUS AND METHOD FOR PROVIDING MULTI-MODE CLOCK SIGNALS,” the disclosure of which is hereby incorporated by reference herein. 
     
    
     BACKGROUND 
       [0002]    1. Field 
         [0003]    Embodiments of the invention relate to electronic devices, and more particularly, in one or more embodiments, to drivers for providing multi-mode clock signals for electronic devices. 
         [0004]    2. Description of the Related Technology 
         [0005]    Certain electronic systems use clock signals for various tasks. Each of these tasks may have individual specifications regarding the frequency and tolerances in logic thresholds. Some tasks may accommodate relaxed rise and fall times and be satisfied with approximate logic levels during operation, while others will require strict adherence to timing standards. Furthermore, some tasks employ different logic standards from other tasks. Examples of such different logic standards include low voltage differential signaling (LVDS), positive emitter-coupled logic (PECL), low-voltage positive emitter-coupled logic (LVPECL), and complementary metal-oxide-semiconductor (CMOS) logic. 
         [0006]    In many of these electronic systems, such different tasks may need to be synchronized with one another. Thus, such electronic systems may generate a single master clock, and employ internal circuit logic to produce multiple clock signals based on the master clock for each of the various needs. This scheme generally requires additional circuitry to generate each of the varied clock signals. 
         [0007]      FIG. 1  is a block diagram of an electronic system  100  in which multiple clock signals are produced for the operation of various components. The illustrated electronic system includes a master clock generator  101 , a clock generator/distributor  103 , and a plurality of components  105   a - 105   d . In some embodiments, the electronic system  100  may form at least part of, for example, a wireless transmission/reception base station or an optical transmission system. 
         [0008]    The master clock generator  101  generates a master clock signal CLK for the clock generator/distributor  103 . The clock generator/distributor  103  cleans up and modifies the master clock signal CLK to produce a plurality of clock signals CLK 1 -CLKn, and supplies the clock signals CLK 1 -CLKn to the components  105   a - 105   d  of the system. 
         [0009]    The clock signals CLK 1 -CLKn may be generally synchronized with the master clock signal CLK. However, one or more of the clock signals CLK 1 -CLKn may have a different frequency and/or voltage level from those of the master clock signal CLK, depending on the needs of the components  105   a - 105   d  that receive the clock signals CLK 1 -CLKn. Further, some of the clock signals CLK 1 -CLKn may have different frequencies and/or characteristics from one another, depending on the needs of the components  105   a -105 d.    
         [0010]    Referring to  FIGS. 2A-2C , various conventional configurations of a clock generator/distributor will be described as follows.  FIG. 2A  illustrates a clock generator/distributor  103   a . The illustrated clock generator/distributor  103   a  serves to generate and distribute clock signals CLK 1 -CLKn. The clock generator/distributor  103   a  may include a phase-locked loop (PLL)  203 , a plurality of clock dividers  201   a - 201   d , and a plurality of drivers  202   a - 202   d.    
         [0011]    The phase-locked-loop (PLL)  203  is configured to receive a master clock signal CLK. The PLL  203  serves to produce a refined clock signal CLK_B with reference to the master clock signal CLK, and provide the refined clock signal CLK_B to the clock dividers  201   a - 201   d . In certain embodiments, multiple phase-locked loop stages may be cascaded together within the clock generator/distributor  103   a  prior to providing a clock signal CLK_B to the dividers  201   a - 201   d . In some embodiments, a first PLL may have a narrow loop bandwidth providing initial jitter cleanup of the input reference signal. A second PLL may have a frequency multiplying and/or dividing PLL that converts the first stage output frequency to a selected frequency. A skilled artisan will thus appreciate that various configurations of PLL can be used for the PLL  203 . 
         [0012]    Each of the clock dividers  201   a - 201   d  serves to divide the refined clock signal CLK_B into a clock signal that has the same or a lower frequency. For example, if the refined clock signal CLK_B has a frequency f, the clock dividers  201   a - 201   d  can generate clock signals having a frequency of, for example, f, f/2, f/4, or f/8. The clock dividers  201   a - 201   d  may provide their divided clock signals to the drivers  202   a - 202   d.    
         [0013]    The drivers  202   a - 202   d  may buffer the divided clock signals, and may also modify the characteristics of the divided clock signals. The drivers  202   a - 202   d  provide the buffered and/or modified clock signals CLK 1 -CLKn to various electronic components. In the context of this document, the amplified and/or modified clock signals CLK 1 -CLKn may be referred to as “component clock signals.” 
         [0014]      FIG. 2B  illustrates another configuration for a clock generator/distributor  103   b . The illustrated clock generator/distributor  103   b  serves to divide and distribute clock signals. The clock generator/distributor  103   b  includes an amplifier  205 , a plurality of clock dividers  201   a - 201   d , and a plurality of drivers  202   a - 202   d.    
         [0015]    The amplifier  205  is configured to receive and amplify (i.e. level shift) a master clock signal CLK, and provides a resulting clock signal CLK_B to the clock dividers  201   a - 201   d . The configurations of the clock dividers  201   a - 201   d  and the drivers  202   a - 202   d  can be as described above in connection with  FIG. 2A . 
         [0016]      FIG. 2C  illustrates another configuration for a clock generator/distributor  103   c . The illustrated clock generator/distributor  103   c  serves to distribute and fan out clock signals having the same frequency. The clock generator/distributor  103   c  includes an amplifier  205  and a plurality of drivers  202   a - 202   d , but does not include clock dividers. The amplifier  205  is configured to receive and amplify a master clock signal CLK, and provides an amplified master clock signal CLK_B to the drivers  202   a - 202   d . Other details of the amplifier  205  and the drivers  202   a - 202   d  can be as described above in connection with  FIG. 2B . 
         [0017]    In some instances, a clock generator/distributor needs to provide different clock signals to various components of an electronic system. For example, the different clock signals may need to be in compliance with different logic standards that the components use. In such instances, one or more of the drivers of the clock generator/distributor may have different circuit configurations, each specified for a particular standard. 
         [0018]    However, in certain instances, one or more of the drivers of a clock generator/distributor may have the same configuration that can be configured to provide such different clock signals. For example, each of the drivers can have the same circuit that is configurable to provide different clock signals in response to control signals. Such a driver may be referred to as a “multi-mode driver” in the context of this document. 
         [0019]    Certain drivers for a clock generator/distributor are known to be configurable to provide clock signals complying with two or more of different logic standards, for example, low voltage differential signaling (LVDS), positive emitter-coupled logic (PECL), low-voltage positive emitter-coupled logic (LVPECL), and complementary metal-oxide-semiconductor (CMOS) logic. 
       SUMMARY 
       [0020]    In one embodiment, an electronic device comprises a multi-mode driver configured to receive a first clock signal and to output a second clock signal at least partly in response to the first clock signal. The device also may include a controller configured to provide one or more control signals to the multi-mode driver, wherein the multi-mode driver comprises a circuit that is configured to selectively output one of different clock signals in response to the one or more control signals provided by the controller. The different clock signals may comprise one or more of a clock signal having characteristics in compliance with low voltage differential signaling (LVDS), a clock signal having characteristics in compliance with positive emitter-coupled logic (PECL) standard, a clock signal having characteristics in compliance with low-voltage positive emitter-coupled logic (LVPECL) standard, or a clock signal having characteristics in compliance with complementary metal-oxide-semiconductor (CMOS) logic standard. The different clock signals further comprise a clock signal having characteristics in compliance with High-Speed Transceiver Logic (HSTL) standard. 
         [0021]    In another embodiment, an electronic device is disclosed comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The second transistor may be in series with a first resistor. The first transistor may be in parallel with the second transistor and first resistor in a first parallel circuit, the first parallel circuit further comprising an operational amplifier in connection with said first transistor. The eighth transistor may be in series with a second resistor and the seventh transistor may be in parallel with the second resistor and eighth transistor in a second parallel circuit. The third and fifth transistors may be in series, the fourth and sixth transistors may be in series, and the third and fifth transistors may be in parallel with the fourth and sixth transistors in a third parallel circuit. The first, second, and third parallel circuits may themselves be in series. 
         [0022]    In another embodiment, an apparatus is disclosed comprising a switching circuit having a first biasing node and a second biasing node. The switching circuit may be configured to receive at least one clock signal as an input and to generate an output signal as an output. The circuit may further comprise a first biasing circuit coupled to a first biasing node and to a first voltage reference, wherein the first biasing circuit is configured to operate in at least a first mode or a second mode. The apparatus may also comprise a second biasing circuit coupled to the second biasing node and to a second voltage reference, wherein the second biasing circuit is configured to operate in at least the first mode or the second mode. In the first mode, the first biasing circuit and the second biasing circuit are configured to provide a low resistance current path such that an output impedance as seen by a load coupled to the output signal matches an intended load resistance to within 30%. In the second mode, the first biasing circuit and the second biasing circuits are configured as current sources. 
         [0023]    In another embodiment, a method of biasing a switching circuit is disclosed, the method comprising providing a first selectable bias to a first biasing node of a switching circuit and providing a second selectable bias to a second biasing node of the switching circuit. The switching circuit may be configured to receive at least one clock signal as an input and to generate an output signal as an output. The method may also include selecting the first selectable bias and the second selectable bias to provide low resistance biases to the switching circuit for a first mode such that an output impedance as seen by a load coupled to the output signal matches an intended load resistance to within 30%. The method may further comprise selecting the first selectable bias and the second selectable bias to provide current source biases to the switching circuit for a second mode. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0024]    The embodiments will be better understood from the Detailed Description of Embodiments and from the appended drawings, which are meant to illustrate and not to limit the embodiments: 
           [0025]      FIG. 1  is a block diagram illustrating an environment in which clock signals are used. 
           [0026]      FIG. 2A  is a block diagram illustrating a conventional clock generation/distribution circuit. 
           [0027]      FIG. 2B  is a block diagram illustrating a conventional clock division/distribution circuit. 
           [0028]      FIG. 2C  is a circuit diagram illustrating a conventional clock distribution/fan-out circuit. 
           [0029]      FIG. 3  is a block diagram illustrating one example of a clock generation/distribution device and a component of an electronic system connected by a channel. 
           [0030]      FIG. 4  is a diagram comprising graphs illustrating the relationship between jitter and rise time in relation to noise from the component. 
           [0031]      FIG. 5  is a block diagram illustrating an electronic system including a clock generation/distribution device generating multi-mode clock signals according to some embodiments. 
           [0032]      FIG. 6  is a circuit diagram illustrating a driver circuit for a clock generation/distribution device generating multi-mode clock signals according to one embodiment. 
           [0033]      FIG. 7  is a circuit diagram illustrating a driver circuit for a clock generation/distribution device generating multi-mode clock signals according to another embodiment. 
           [0034]      FIGS. 8A and 8B  illustrate the operation of the driver circuit of  FIG. 7  in LVDS Mode or LVPECL. 
           [0035]      FIGS. 9A and 9B  illustrate the operation of the driver circuit of  FIG. 7  in HSTL Mode. 
           [0036]      FIG. 10A  is a circuit diagram illustrating a driver circuit for a clock generation/distribution device generating multi-mode clock signals according to yet another embodiment. 
           [0037]      FIG. 10B  is a circuit diagram illustrating a driver circuit for a clock generation/distribution device generating multi-mode clock signals according to yet another embodiment. 
           [0038]      FIG. 11  is a circuit diagram illustrating a driver circuit for a clock generation/distribution device generating multi-mode clock signals according to yet another embodiment. 
       
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
       [0039]    The following detailed description of certain embodiments presents various descriptions of specific embodiments of the invention. However, the invention can be embodied in a multitude of different ways as defined and covered by the claims. In this description, reference is made to the drawings where like reference numerals indicate identical or functionally similar elements. 
         [0040]    As components of electronic systems operate at high frequencies, it is necessary for multi-mode drivers to provide clock signals that minimize errors in high frequency operations of the components. One way of reducing errors is to minimize jitter in clock signals. Jitter generally refers to unfavorable dynamic changes in the edge location of a clock signal. For example, cycle-to-cycle jitter comprises changes in the edge location in each period. 
         [0041]    In addition to jitter, impedance matching becomes also important for high-frequency applications. Where the impedance between the clock generator/distributor  103  and the components  105   a - 105   d  is poorly matched, voltage signals will reflect from the load, resulting in unfavorable interference with the clock signal. 
         [0042]      FIG. 3  illustrates the impedance matching that needs to occur between a clock generator/distributor  103  and components  105   a - 105   d  (only  105   b  is shown for illustration purposes). With reference to only one of the components  105   b , a channel  401  carries a signal from a driver  202   b  of the clock generator/distributor  103  to the component  105   b . The termination R ext  of the component  105   b , as seen from the driver  202   b , may result in signal reflections back across the channel  401  to the line driver  202   b . Subsequent clock signals travelling from the driver  202   b  across the channel  401  may be distorted, thereby adversely affecting the operation of the component  105   b.    
         [0043]    In applications having poor impedance matching, clock signals from the driver  202   b  will be reflected back from the load R ext . In clocking applications, this can be especially troublesome because the reflections may change the rise and fall times of the clock signal. Thus, components dependent upon the fast rise and fall times of the clock signal can be adversely affected. 
         [0044]    Some logic standards, for example, LVDS, PECL, LVPECL, and CMOS logic, which can be provided by a multi-mode driver, are not always suitable for applications requiring low jitter. Therefore, there is a need for another standard that can minimize errors in high-frequency operations. 
         [0045]    In one embodiment, a multi-mode driver can be configured to provide a clock signal that can provide a relatively fast rise time to minimize jitter. Having a fast rise time is advantageous in that it provides less time for noise from the components&#39;  105   b  clock receiver to vary the proper timing of edge locations (i.e., the transitions from low to high, and vice versa, are displaced, at most, by a smaller amount). 
         [0046]    With reference to  FIG. 4 , clock generator/distributor  103  provides a clock signal Clki to the i th  component  105   c . Within the i th  component is a receiver  304 , which accepts the clock signal Clki and provides it to the component for use as signal  305 . Waveforms  301   a  and  301   b  show two different clock signals as seen internally from the component at  305 . Waveform  301   a  depicts the rise time for a typical clock signal with a shallow rise time. Waveform  301   b , in contrast, depicts a signal having a much faster rise time. Time is expressed along a horizontal axis and the illustrated waveforms have the same scale. 
         [0047]    Voltage noise  302  is from the receiver  304 . These fluctuations in voltage  302  can translate into noise displacements  303   a  in the clock signal. These displacements distort the clock signal, causing the minimum low voltage and the maximum peak values to be reached sooner or later than was intended. Under noisy conditions, a receiver  304  monitoring the signal would erroneously determine that the clock edge had occurred at this undesired time. This process repeats on every clock edge, typically with a random pattern of cycle-to-cycle jitter as a result of random noise. 
         [0048]    In contrast to the shallow rise time of graph  301   a , graph  301   b  has a much steeper ascent and descent at the end of each cycle. While noise displacements  303   b  have the same width as the noise displacements  303   a , there is less time for their distortion to influence the edge location of the clock signal. Accordingly, a more accurate signal results and the observed completion of the cycle more closely comports with the intended termination time. 
         [0049]    A multi-mode driver can be configured to provide a clock signal that can be compatible with High-Speed Transceiver Logic (HSTL) standard. In some instances, the clock signal can be a differential clock signal(s). In the context of this document, such a clock signal can be referred to as an “HSTL clock signal” or a “clock signal in HSTL mode.” Certain characteristics of an HSTL clock signal are shown in Table 1 below. In addition, the characteristics of clock signals according to other modes are also provided in Table 1. A skilled artisan will appreciate that the characteristics of the HSTL clock signal may not be identical to those of clock signals specified by a certain industry standard that is titled “HSTL standard.” 
         [0000]    
       
         
               
               
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 Parameter 
                 PECL 
                 LVPECL 
                 LVDS 
                 CMOS 
                 HSTL 
               
               
                   
               
             
             
               
                 V CC   
                 5 
                 3.3 
                 — 
                 5, 3.3, 1.8 
                 5, 3.3, 1.8 
               
               
                 V OH   
                 V CC  − 1.025 to 
                 V CC  − 1.025 to 
                 &lt;1.475 V 
                 V CC  − 0.1 
                 V CC  * 0.75 
               
               
                   
                 V CC  − 0.88 
                 VCC − 0.88 
               
               
                 V OL   
                 V CC  − 1.81 to 
                 V CC  − 1.81 to 
                 &gt;0.925 
                 0.1 
                 V CC  * 0.25 
               
               
                   
                 V CC  − 1.62 
                 V CC  − 1.62 
               
               
                 Differential 
                 800 mV 
                 800 mV 
                 250 mV-450 mV 
                 — 
                 V CC /2 
               
               
                 Output 
               
               
                 Voltage V PP   
               
               
                 Output 
                 V CC  − 1.3 
                 V CC  − 1.3 
                 1.25 
                 — 
                 V CC /2 
               
               
                 Common 
               
               
                 Mode 
               
               
                 Voltage V OS   
               
               
                   
               
             
          
         
       
     
         [0050]    As seen from Table 1, PECL and LVPECL are supply referenced and thus V OH  and V OL  are specified relative to V CC . PECL and LVPECL differ from one another in the level of supply voltage used. LVDS does not specify a supply voltage, but rather directly specifies the output common mode voltage V OS . V CC  refers to the source voltage used throughout the circuit. V OH  refers to the minimum voltage level that will comprise a logic high. V OL  is the maximum voltage level that will comprise a logic low. The Differential Output Voltage V PP  refers to the peak to peak voltage, i.e. the differential between V OH  and V OL . The Output Common Mode Voltage V OS  refers to the average voltage level of the two differential signals (i.e., (V OH −V OL )/2 for the implementation). 
         [0051]    Thus, such a multi-mode driver can provide an HSTL clock signal that can provide a fast rise time. Further, the multi-mode drivers can also be configured to match the output impedance of the driver to the impedance of the load during an HSTL mode. This matching reduces reflections, improving signal integrity and the rise/fall times in clocking applications. 
         [0052]    Referring to  FIG. 5 , in some embodiments, a clock generator/distributor  103  can include a PLL  203 , a plurality of clock dividers  201   a - 201   e , a plurality of drivers  202   a - 202   e , and a controller  501 . The details of the PLL and the clock dividers  201   a - 201   e  can be as described above in connection with  FIG. 2A . The controller  501  can control the operations of each of drivers  202   a - 202   e , including, but not limited to, satisfying the requirements of the respective components  105   a - 105   e.    
         [0053]    At least one of the drivers  202   a - 202   e  can have a circuit that can be configured to provide a HSTL mode clock signal as well as one or more of clock signals in compliance with LVDS, PECL, LVPECL, and CMOS logic levels. 
         [0054]    However, a multi-mode driver providing the HSTL mode in parallel with other modes, for example, in parallel with one or more of LVPECL, PECL, LVDS, and CMOS modes, can use significantly more chip area than devices without HSTL. Furthermore, the additional circuitry can increase the loading on the output nodes, adversely affecting the accuracy of clock signals. Similarly, placing additional resistors or large switching devices to permit HSTL mode can result in unwanted voltage drops or increased capacitance in the other modes. Further, to retain compatibility with LVPECL, and the DC coupling used with LVPECL and LVDS, it is desirable not to omit the previous modes when providing HSTL functionality in a single multi-mode driver. Thus, there is a need for a circuit for such a driver that can provide a HSTL mode in addition to other modes while minimizing the additional circuit area used. 
       Circuit For Multi-Mode Driver 
       [0055]    Referring to  FIG. 6 , one embodiment of a multi-mode driver circuit will be described below. The illustrated driver circuit  600  is configured to provide several modes of operation (LVPECL, LVDS, HSTL). The circuit  600  can be at least part of at least one of the drivers  201   a - 201   d  described above in connection with  FIGS. 2A to 2C  or at least one of the drivers  201   a - 201   e  described above in connection with  FIG. 5 . 
         [0056]    The illustrated driver circuit  600  includes first, third, fourth, fifth, sixth, and seventh transistors TR 1 , TR 3 , TR 4 , TR 5 , TR 6 , TR 7 , a first switch SW 1 , and a second switch SW 2 . The circuit  600  also includes a first and second resistors R 1 , R 2 , and a first and second switch resistors R a , R b . The circuit  600  further includes an operational amplifier OPAMP, a LVDS/LVPECL bias current source controller CM 1 , and first to sixth nodes N 1 -N 6 . 
         [0057]    In the illustrated embodiment, the first transistor TR 1  is a PMOS transistor. The first transistor TR 1  includes a source/drain coupled to a first voltage source V DD , a drain/source coupled to the second node N 2 , and a gate configured to receive an output signal from the operational amplifier OPAMP. A skilled artisan will appreciate that the first transistor TR 1  can alternatively be an NMOS transistor or other types of transistors, depending on the configuration of the circuit (and inputs to the OPAMP may need to be swapped). 
         [0058]    In the illustrated embodiment, the third transistor TR 3  is a PMOS transistor. The third transistor TR 3  includes a source/drain coupled to the second node N 2 , a drain/source coupled to the third node N 3 , and a gate configured to receive an inverted clock signal V clkb  from, for example, a clock divider  201   a - 201   e  ( FIG. 5 ). V clkb , may refer to a clock signal inverted from any of the clock signals CLK or CLK_B from  FIGS. 1 ,  2 A-C depending on the particular embodiment. A skilled artisan will appreciate that the third transistor TR 3  can be an NMOS transistor or other type of transistor, depending on the design of the circuit. 
         [0059]    In the illustrated embodiment, fourth transistor TR 4  is a PMOS transistor. The fourth transistor TR 4  includes a source/drain coupled to the second node N 2 , a drain/source coupled to the fifth node N 5 , and a gate configured to receive the clock signal V clk  from, for example, a clock divider ( FIG. 5 ). V clk  may refer to a clock signal inverted from any of the clock signals CLK or CLK_B from  FIGS. 1 ,  2 A-C depending on the particular embodiment. A skilled artisan will appreciate that the fourth transistor TR 4  can be an NMOS transistor or other type of transistor, depending on the design of the circuit. 
         [0060]    In the illustrated embodiment, the fifth transistor TR 5  is an NMOS transistor. The fifth transistor TR 5  includes a source/drain coupled to the third node N 3 , a drain/source coupled to the sixth node N 6 , and a gate configured to receive the inverted clock signal V clkb . A skilled artisan will appreciate that the fifth transistor TR 5  can be a PMOS transistor or other type of transistor, depending on the design of the circuit. 
         [0061]    In the illustrated embodiment, the sixth transistor TR 6  is an NMOS transistor. The sixth transistor TR 6  includes a source/drain coupled to the fifth node N 5 , a drain/source coupled to the sixth node N 6 , and a gate configured to receive the clock signal V clk . A skilled artisan will appreciate that the sixth transistor TR 6  can be a PMOS transistor or other type of transistor, depending on the design of the circuit. 
         [0062]    In the illustrated embodiment, the seventh transistor TR 7  is an NMOS transistor. The seventh transistor TR 7  includes a source/drain coupled to the sixth node N 6 , a drain/source coupled to the second voltage source V SS , and a gate configured to receive a control signal from the current source controller CM 1 . A skilled artisan will appreciate that the seventh transistor TR 7  can be a PMOS transistor or other type of transistor, depending on the design of the circuit. 
         [0063]    In the illustrated embodiment, the common-mode voltage controlling transistor is coupled to V DD  and the current source is coupled to V ss . Typically, current sources have high impedance characteristics. In an alternative embodiment one might consider exchanging the positions of current source CM 1  and op-amp OPAMP, such that the OPAMP is output to the gate of transistor TR 7  and the current source CM 1  is output to the gate of transistor TR 1 . One skilled in the art would readily recognize similar configuration variations that will achieve the same modes of operation. 
         [0064]    The first switch SW 1  includes a first terminal coupled to the first voltage source V DD , and a second terminal coupled to the switch resistor R a . The first switch SW 1  is configured to switch on or off at least partly in response to an HSTL enable signal from a controller, for example, the controller  501  of  FIG. 5 . Operation will be described later in connection with  FIGS. 8A-9B . 
         [0065]    The second switch SW 2  includes a first terminal coupled to switch resistor R b , and a second terminal coupled to the second voltage source V SS . The first switch SW 1  is configured to switch on or off at least partly in response to an HSTL enable signal from a controller, for example, the controller  501  of  FIG. 5 . Operation will be described later in connection with  FIGS. 8A-9B . 
         [0066]    The first resistor R 1  includes a first end coupled to the third node N 3  and a second end coupled to the fourth node N 4 . The second resistor R 2  includes a first end coupled to the fifth node N 5 , and a second end coupled to the fourth node N 4 . The third to sixth transistors TR 3 -TR 6  and the first and second resistors R 1 , R 2  together form a so-called “H-bridge circuit.” 
         [0067]    The first switch resistor R a  includes a first end coupled to SW 1  and a second end coupled to the second node N 2 . The second switch resistor R b  includes a first end coupled to the sixth node N 6  and a second end coupled to switch SW 2 . 
         [0068]    The operational amplifier OPAMP includes a non-inverting input coupled to the fourth node N 4 , and an inverting input configured to receive a reference signal from the controller. The operational amplifier OPAMP also includes an output coupled to the gate of the first transistor TR 1 . The operational amplifier OPAMP can be a common mode amplifier which senses the common mode level and sources current through the top of the H-bridge circuit  607 , using TR 1  for example, such that the voltage at the fourth node N 4  is about equal to a common mode reference voltage V cm     —     ref . The Operational Amplifier OPAMP can form part of a common mode feedback loop that establishes the common mode levels in a certain mode, such as LVPECL and LVDS modes. 
         [0069]    The LVDS/LVPECL bias current source control CM 1  is configured to receive a LVDS/LVPECL enable signal from the controller and to provide a control signal to the gate of the seventh transistor TR 7 . In some embodiments the current source control CM 1  may be a current mirror. In these embodiments, the current source control CM 1  serves to mirror a current through one active device by controlling the current in another active device of a circuit, keeping the output current relatively constant regardless of loading. In some programmable embodiments, the transistor TR 7  can sink about 3.5 mA to about 8 mA, for example, 3.5 mA through the bottom of the H-bridge circuit  607 . 3.5 mA may be typical for LVDS, whereas 8 mA may be typical for LVPECL Modes. Other applicable values will be readily determined by one of ordinary skill in the art. 
         [0070]    The third and fifth nodes N 3 , N 5  are connected to a channel  401  such that component clock signals are outputted therefrom to a component (for example, the components  105   a - 105   e  of  FIG. 5 ) via the channel  401 . On the component side, there is an external impedance denoted by R ext  in  FIG. 6 . A channel path  401   a  connecting the third node N 3  to the impedance R ext  is referred to as V outp , and a complementary path  401   b  from R ext  to the fifth node N 5  is referred to as V outn . Together, V outp  and V outn  comprise an output signal that can support multi-mode communication with the component (having impedance R ext ). 
         [0071]    In parallel with the component circuit are the first and second resistors R 1  and R 2 , which are electrically in series. The node N 4  between these resistors R 1 , R 2  serves to provide a V CM  common mode signal, and is coupled to the positive, non-inverting input of operational amplifier OPAMP as part of the feedback configuration. When the driver operates in HSTL mode, as will be described below, the common mode feedback loop is turned off, i.e., the first transistor TR 1  is turned off, and the current source control CM 1  connected to the seventh transistor TR 7  deactivates the seventh transistor TR 7 . 
         [0072]    Referring to  FIG. 7 , another embodiment of a multi-mode driver circuit will be described below. The driver circuit  700  is identical to the driver circuit  600  of  FIG. 6  except that the first and second switches SW 1 , SW 2  are replaced with second and eighth transistors TR 2 , TR 8 . The details of the components of the driver circuit  700 , other than those of the second and eight transistor TR 2 , TR 8 , can be as described above in connection with  FIG. 6 . 
         [0073]    The second transistor TR 2  includes a source/drain coupled to the first voltage source V DD , a drain/source coupled to the second node N 2 , and a gate configured to receive the inverted HSTL enable signal from a controller, for example, the controller  501  of  FIG. 5 . A skilled artisan will appreciate that the second transistor TR 2  can be an PMOS transistor or other types of transistors, depending on the design of the circuit. 
         [0074]    The eight transistor TR 8  includes a source/drain coupled to the sixth node N 6 , a drain/source coupled to the second voltage source Vss, and a gate configured to receive the HSTL enable signal from a controller, for example, the controller  501  of  FIG. 5 . A skilled artisan will appreciate that the second transistor TR 2  can be an PMOS transistor or other types of transistors, depending on the design of the circuit. 
         [0075]    A skilled artisan will recognize that the switches could be replaced with numerous alternatives, such as bipolar transistors or other types of field effect transistors, or any applicable switching device. 
       Operation of Multi-Mode Driver Circuit 
       [0076]    Referring now to  FIGS. 8A-9B  the operation of the driver circuit  700  of  FIG. 7  according to some embodiments will be described below. 
       LVDS or LVPECL Mode 
       [0077]      FIG. 8A  is a circuit diagram illustrating operation of the embodiment of  FIG. 7  in LVDS Mode for the state when the clock signal V clk  is high. In the illustrated LVDS mode, V cm     —     ref  can be set to, for example, about 1.25V. For LVPECL operation, V cm     —     ref  can be set to around 2.0V. During LVDS mode, the first transistor TR 1  is turned on. In addition, the LVDS/LVPECL enable signal is high (active high logic) during this mode, and thus the seventh transistor TR 7  is turned on to provide a current source. Transistors TR 2  and TR 8  are off. Accordingly, resistances Ra and Rb will be discussed later 
         [0078]    In  FIG. 8A , when the clock signal V ac  is high and the inverted clock signal V clkb , is low, the third transistor TR 3  and the sixth transistor TR 6  are on while the fourth transistor TR 4  and the fifth transistor TR 5  are off. Thus, a current I clkH  (through the load) flows from the first voltage source V DD  through the first transistor TR 1 , the third transistor TR 3 , the third node N 3 , the channel path V outp , the external impedance R ext , the complementary channel path V outn , the fifth node N 5 , the sixth transistor TR 6 , and the seventh transistor TR 7  to the second voltage source V ss . Because the combined resistance of the first and second resistors R 1 , R 2  is substantially greater than the impedance of the external impedance R ext , most of the current I clkH  flows through the external impedance R ext . 
         [0079]    Complementary to  FIG. 8A  in which V ac  was high,  FIG. 8B  is a circuit diagram illustrating operation of the embodiment of  FIG. 7  in LVDS Mode when V clk  is low and inverted clock signal V clkb  is high. V cm     —     ref  can again be set to, for example, about 1.25V to facilitate activation of the first transistor TR 1 . The LVDS/LVPECL enable signal is again high during this mode, and thus the seventh transistor TR 7  is turned on. 
         [0080]    In  FIG. 8B , because the clock signal V clk  is low and the inverted clock signal V clkb  is high, the third transistor TR 3  and the sixth transistor TR 6  are off while the fourth transistor TR 4  and the fifth transistor TR 5  are on. Thus, a current I clkL  flows from the first voltage source V DD  through the first transistor TR 1 , the fourth transistor TR 4 , the fifth node N 5 , the CHANNEL path via V outn , the external impedance R ext , the complementary channel path V outp , the third node N 3 , the fifth transistor TR 5 , and the seventh transistor TR 7  to the second voltage source V ss . 
         [0081]    For LVPECL operation, V cm     —     ref  can be set to about 2 volts. The operation will then be much the same as in  FIGS. 8A and 8B . 
         [0082]    HSTL Mode 
         [0083]      FIG. 9A  is a circuit diagram illustrating operation of the embodiment of  FIG. 7  in HSTL Mode when the clock signal V clk  is high. In the illustrated HSTL mode the output of the operational amplifier OPAMP is high, thereby turning off, the first transistor TR 1 . In some embodiments the output of the OPAMP may simply be of such a nature to render the effect of the first transistor negligible. During the HSTL mode, HSTL_EN is high, rendering the second and eighth transistors TR 2  and TR 8  active. LVDS/LVPECL ENABLE is low (active high), rendering the seventh transistor TR 7  inactive (open circuit). 
         [0084]    In  FIG. 9A , with the clock signal V clk  high and the inverted clock signal V clkb  low, the third transistor TR 3  and the sixth transistor TR 6  are on while the fourth transistor TR 4  and the fifth transistor TR 5  are off. Thus, a load current I clkH  flows from the first voltage source V DD  through the second transistor TR 2 , the resistor Ra, the third transistor TR 3 , the third node N 3 , the channel path V outp , the external impedance R ext , the complementary channel path V outn , the fifth node N 5 , the sixth transistor TR 6 , the resistor Rb, and the eighth transistor TR 7  to the second voltage source V ss . Because the combined resistance of the first and second resistors R 1 , R 2  is substantially greater than the impedance of the external impedance R ext , most of the current I clkH  flows through the external impedance R ext . Thus, a current through the first and second resistors R 1  and R 2  is negligible and ignored for this analysis. 
         [0085]      FIG. 9B  is a circuit diagram illustrating operation of the embodiment of  FIG. 7  in HSTL Mode with the clock signal V clk  low. In the illustrated HSTL mode, the first transistor TR 1  is turned off. In addition, HSTL_EN is high, rendering the second and eighth transistors TR 2  and TR 8  active. In contrast, LVDS/LVPECL ENABLE is low, rendering the seventh transistor TR 7  inactive. 
         [0086]    In  FIG. 9B , because the clock signal V clk  is low and the inverted clock signal V clkb  is high, the third transistor TR 3  and the sixth transistor TR 6  are off while the fourth transistor TR 4  and the fifth transistor TR 5  are on. Thus, a current I clkH  flows from the first voltage source V DD  through the second transistor TR 2 , resistor R a , the fourth transistor TR 4 , the fifth node N 5 , the channel path V outn , the external impedance R ext , the complementary channel path V outp , the third node N 3 , the fifth transistor TR 5 , resistor R b  and the eighth transistor TR 8  to the second voltage source V ss . 
         [0087]    In the illustrated embodiment, the second transistor TR 2  has a resistance RSW 1  when turned on. Each of the third and fourth transistors TR 3 , TR 4  has a resistance Rswp when turned on. In addition, each of the fifth and sixth transistors TR 5 , TR 6  has a resistance Rswn when turned on. The eighth transistor TR 8  has a resistance RSW 2  when turned on. 
         [0088]    Thus, in the HTSL mode described above, an output impedance provided by the driver circuit  600  can be represented as follows. 
         [0000]      RSW1+Ra+Rswp+Rswn+Rb+RSW2 
         [0089]    In some embodiments, by selecting the sizes of the third to sixth transistors TR 3 -TR 6  and the sizes of the switch resistors R a , R b , the impedance of the driver circuit  600  can be closely matched within about 80% to about 120% of the external impedance R ext , which is from about 90 ohms to about 110 ohms. 
       Alternative Configurations of Multi-Mode Driver Circuits 
       [0090]    One skilled in the art will recognize that multiple alternative configurations to the above described circuits are possible. For example, the resistors R a  and R b  of  FIGS. 6 ,  7 ,  8 A-B, or  9 A-B may be replaced with variable resistors (e.g., using a digital-to-analog converter (DAC). Such variable resistors can be adjusted to match the impedance of the driver with an external impedance during HSTL mode. 
         [0091]    In other embodiments, one or more of the transistor/resistor lines for receiving an HSTL mode enabling signal, for example, TR 2 /Ra and/or TR 8 /Rb of  FIGS. 6 ,  7 ,  8 A-B, or  9 A-B can be coupled in parallel to one or more additional transistor/resistor lines. In one embodiment, each of such additional transistor/resistor lines can include a transistor having substantially the same size as that of the second or eighth transistor TR 2  or TR 8 , and a resistor having substantially the same resistance as that of the first or second switch resistor Ra, Rb. In another embodiment, such additional transistor/resistor lines can include a transistor having a different size from that of the second or eighth transistor TR 2  or TR 8 , and a resistor having a different resistance from that of the first or second switch resistor Ra, Rb. Each of the transistors of the additional transistor/resistor lines can receive the same or different gate control signal for enabling HSTL mode, depending on the resistance desired by the operation. 
         [0092]      FIG. 10A  is a circuit diagram illustrating another embodiment of a circuit for a multi-mode driver. The configuration of the circuit of  FIG. 10A  is the same as that of the circuit of  FIG. 7  except that the resistors R a  and R b  are removed. The second transistor TR 2  and the eighth transistor TR 8  alone, in combination with the rest of the circuit, particularly resistors R 1  and R 2 , match the impedance of the driver with an external impedance during HSTL mode. 
         [0093]      FIG. 10B  is a circuit diagram illustrating yet another embodiment of a circuit for a multi-mode driver. The configuration of the circuit of  FIG. 10B  is the same as that of the circuit of  FIG. 7  except for the positions of resistors Ra, Rb. In the illustrated embodiment, the resistor R a  is coupled between V DD  and the second transistor TR 2 . The resistor R b  is coupled between Vss and the eight transistor TR 8 . These configurations can match the impedance of the driver with an external impedance during HSTL mode. 
       Circuit for Multi-Mode Driver for PECL, LVPECL, LVDS, HSTL and CMOS Modes 
       [0094]      FIG. 11  is a circuit diagram illustrating a modification of the embodiment of  FIG. 7  according to another embodiment. A multi-mode driver having the circuit of  FIG. 11  can also provide CMOS operation in addition to PECL, LVPECL, LVDS, and HSTL. In the illustrated circuit, a first CMOS transistor TR_CMOS 1  is coupled in parallel with the second transistor TR 2  and resistor Ra pair between nodes N 1  and N 2 . Similarly, a second CMOS transistor TR_CMOS 2  is coupled in parallel with the eighth transistor TR 8 , resistor Rb pair between a node N 6  and V SS . The first CMOS transistor TR_CMOS 1  receives an inverted CMOS_EN signal at its gate, while the second CMOS transistor TR_CMOS 2  receives CMOS_EN directly at its gate. By pulling HSTL_EN low and bringing CMOS_EN high, clock signals placed on the channel will be the ranges specified in Table 1 for CMOS. One skilled in the art will recognize that transistors TR_CMOS 1  and TR_CMOS 2  may be generalized to represent any switch. 
         [0095]    In other embodiments, each of the circuits shown in  FIGS. 6-10B  can also be provided with the first and second CMOS transistors, as described above with reference to  FIG. 11 . The operations of such circuits can be similar to that of the circuit of  FIG. 11 . 
         [0096]    The above embodiments can provide output frequencies in the range of, for example, less than 1 MHz to greater than 1 GHz. A skilled artisan will, however, appreciate that the embodiments are not limited to these frequency ranges. 
         [0097]    As used throughout this application, it will be understood that a current source refers to either a current source or a current sink. 
         [0098]    Devices employing the above described schemes can be implemented into various electronic devices. Examples of the electronic devices can include, but are not limited to, consumer electronic products, parts of the consumer electronic products, electronic test equipment, etc. Examples of the electronic devices can also include memory chips, memory modules, circuits of optical networks or other communication networks, and disk driver circuits. The consumer electronic products can include, but are not limited to, a mobile phone, a telephone, a television, a computer monitor, a computer, a hand-held computer, a personal digital assistant (PDA), a microwave, a refrigerator, a stereo system, a cassette recorder or player, a DVD player, a CD player, a VCR, an MP3 player, a radio, a camcorder, a camera, a digital camera, a portable memory chip, a washer, a dryer, a washer/dryer, a copier, a facsimile machine, a scanner, a multi functional peripheral device, a wrist watch, a clock, etc. Further, the electronic device can include unfinished products. 
         [0099]    Although this invention has been described in terms of certain embodiments, other embodiments that are apparent to those of ordinary skill in the art, including embodiments that do not provide all of the features and advantages set forth herein, are also within the scope of this invention. Moreover, the various embodiments described above can be combined to provide further embodiments. In addition, certain features shown in the context of one embodiment can be incorporated into other embodiments as well. Accordingly, the scope of the present invention is defined only by reference to the appended claims.