Abstract:
A semiconductor device includes at least first and second lower layer wirings provided on a surface of an insulator on a semiconductor substrate, a first interlayer film provided on the insulator to cover surfaces of the first and second lower layer wirings, first and second connection wirings which are provided on the first interlayer film and include first and second films contacting the first and second lower layer wirings respectively, and a plate electrode which is continuously provided on the second connection wiring and includes at least the first film.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This is a division of application Ser. No. 09/957,020, filed Sep. 21, 2001, now U.S. Pat. No. 6,515,365, which is incorporated herein by reference. 
    
    
     This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-287717, filed Sep. 21, 2000, the entire contents of which are incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor device having a ground plane and a manufacturing method thereof. More specifically, the present invention concerns a ground plane and a formation method thereof applied to semiconductor elements such as logic LSI (Large Scale Integrated circuit), memory LSI including DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory), and analog LSI comprising bipolar transistors. 
     2. Description of the Related Art 
     Generally, the multilayer wiring used for semiconductor elements is easily affected by a signal noise (crosstalk noise) due to mutual capacitance or mutual inductance between adjacent connections. In recent years, as interconnections become finer, the affect of this crosstalk noise increases and is becoming a cause of preventing fabrication of high-speed elements. Particularly in the field of LSI evaluation boards, crosstalk noise is becoming hindrance to evaluation of LSI&#39;s high performance. 
     An LSI evaluation board having damascene structure plate electrodes is proposed as a solution for decreasing the crosstalk noise. This board is provided with a metallic plate having ground potentials called a ground plane at least on or under the wiring. 
     There is an increasing demand for applying such a structure for decreasing the crosstalk noise in ordinary LSI chips. 
     FIGS. 9A and 9B provide examples of applying a ground plane used for conventional LSI evaluation boards to ordinary LSI chips. 
     In FIG. 9A, an insulator  102  is formed on an Si substrate  101 . On the surface of the insulator  102 , there are formed damascene-structure lower layer wirings  103 A and  103 B. The lower layer wirings  103 A and  103 B are made of liner metal  103   a  such as TaN and wiring metal  103   b  such as Cu, respectively. 
     An interlayer film  105  is formed via a barrier film  104  on the insulator  102  provided with the lower layer wirings  103 A and  103 B. On the interlayer film  105 , there are formed dual damascene structure connection wirings  106 A and  106 B. The connection wiring  106 A leads to the lower layer wiring  103 A. The connection wiring  106 B leads to the lower layer wiring  103 B. The connection wiring  106 A comprises a ViaPlug section  106 A- 1  and a wiring section  106 A- 2 . The connection wiring  106 B comprises a ViaPlug section  106 B- 1  and a ground plane  106 B- 2 . The connection wiring  106 A and  106 B are made of liner metal  106   a  such as TaN and plug metal  106   a  such as Cu, respectively. 
     An interlayer film  108  is formed via a barrier film  107  on the interlayer film  105  provided with the connection wirings  106 A and  106 B. On the interlayer film  108 , there is formed a dual damascene structure upper layer wiring  109  leading to the connection wiring  106 A. The upper layer wiring  109  comprises a ViaPlug section  109 A- 1  and a wiring section  109 A- 2 . The upper layer wiring  109  is formed of liner metal  109   a  such as TaN and wiring metal  109   b  such as Cu. 
     In this configuration, a ground potential is supplied to the ground plane  106 B- 2  via the lower layer wiring  103 B. This suppresses occurrence of crosstalk noise due to mutual capacitance or mutual inductance between adjacent wirings. 
     However, there arise various problems when a conventional multilayer wiring process is used to provide the above-mentioned configuration. For example, when the ground plane  106 B- 2  is formed by a formation process for dual damascene wiring which is being put to practical use, say, for Cu wiring, a phenomenon called “dishing” occurs. In this case, as shown in FIG. 9B, there is the problem that the inside of a pattern sinks largely. For example, when the CMP (Chemical Mechanical Polishing) method is used to flatten Cu, dishing occurs, which excessively scrapes the inside of a wide pattern such as the ground plane  106 B- 2 . This phenomenon is not only an obstacle to the ground potential, but also may adversely affect lithography and CMP when wiring is formed on a layer thereon. 
     As mentioned above, a prior art method can decrease crosstalk noise by forming the ground plane. This, however, has the drawback that dishing causes the inside of a pattern to sink largely when an attempt is made to provide the ground plane by means of a conventional formation process for dual damascene wiring. 
     BRIEF SUMMARY OF THE INVENTION 
     According to a first aspect of the present invention, there is provided a semiconductor device comprising at least first and second lower layer wirings provided on a surface of an insulator on a semiconductor substrate; a first interlayer film provided on the insulator to cover surfaces of the first and second lower layer wirings; first and second connection wirings which are provided on the first interlayer film and comprise first and second films contacting the first and second lower layer wirings respectively; and a plate electrode which is continuously provided on the second connection wiring and comprise the first film. 
     According to a second aspect of the present invention, there is provided a manufacturing method of a semiconductor device comprising forming at least first and second lower layer wirings on a surface of an insulator provided on a semiconductor substrate; forming a first interlayer film on the insulator to cover surfaces of the first and second lower layer wirings; forming first and second through-holes which reach the first and second lower layer wirings through the first interlayer film; forming a first film on a surface of the first interlayer film including insides of the first and second through-holes; forming a second film on the first film and completely filling the first and second through-holes; selectively removing the second film remaining on the first film except insides of the first and second through-holes; and patterning the first film and forming first and second connection wirings connected to the first and second lower layer wirings respectively and a plate electrode continuous with the second connection wiring. 
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING 
     FIG. 1 is a sectional view showing a configuration example of a semiconductor device according to a first embodiment of the present invention; 
     FIGS. 2A to  2 G are sectional views showing processes for a method of manufacturing the semiconductor device in FIG. 1; 
     FIG. 3 is a sectional view showing another configuration example of a semiconductor device according to the first embodiment of the present invention; 
     FIG. 4 is a sectional view showing a configuration example of a semiconductor device according to a second embodiment of the present invention; 
     FIGS. 5A to  5 G are sectional views showing processes for a method of manufacturing the semiconductor device in FIG. 4; 
     FIG. 6 is a sectional view showing an example of a third embodiment of the present invention applied to the semiconductor device in FIG. 1; 
     FIG. 7 is a sectional view showing an example of the third embodiment of the present invention applied to the semiconductor device in FIG. 3; 
     FIG. 8 is a sectional view showing an example of the third embodiment of the present invention applied to the semiconductor device in FIG. 4; and 
     FIGS. 9A and 9B are sectional views of a semiconductor device for explaining a prior art and problems thereof. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Embodiments of the present invention will be described in further detail with reference to the accompanying drawings. 
     (First Embodiment) 
     FIG. 1 shows a configuration example of a semiconductor device according to the first embodiment of the present invention. 
     In FIG. 1, an insulator  12  is formed on an Si substrate (semiconductor substrate)  11 . On the surface of the insulator  12 , there are formed damascene structure lower layer signal wires (first and second lower layer wirings)  13 A and  13 B. The lower layer signal wires  13 A and  13 B are made of liner metal  13   a  such as TaN and wiring metal  13   b  such as Cu, respectively. 
     The lower layer signal wire  13 A is electrically connected to an element section  31  formed on the surface of the Si substrate  11  by means of a contact  32 . 
     An interlayer insulator (first interlayer film)  14  is provided on the insulator  12  where the lower layer signal wires  13 A and  13 B are provided. On this interlayer insulator  14 , there are formed damascene structure connection wirings  15 A (first connection wiring) and  15 B (second connection wiring). The connection wirings  15 A leads to the lower layer signal wire  13 A. The connection wirings  15 B leads to the lower layer signal wire  13 B. On the interlayer insulator  14 , there is formed a ground plane (plate electrode)  15 C leading to the connection wiring  15 B. 
     The connection wiring  15 A and  15 B each have a ViaPlug configuration. This configuration comprises a liner metal  15   a  (first film) such as TaN and a plug metal  15   b  (second film) such as Cu or Ag having lower resistance than the liner metal  15   a . Further, the connection wiring  15 A and  15 B each include a barrier film  15   c  (third film) such as Al 2 O 3  for preventing oxidation and diffusion of the plug metal  15   b.    
     The ground plane  15 C is formed by using the liner metal  15   a  for configuring the connection wirings  15 A and  15 B. The ground plane  15 C contains the barrier film  15   c . Namely, this embodiment forms the ground plane  15 C integrally with the connection wiring  15 B by means of the liner metal  15   a  and the barrier film  15   c.    
     An interlayer insulator  16  (second interlayer film) is provided on the interlayer insulator  14  where the connection wirings  15 A and  15 B and the ground plane  15 C are provided. On this interlayer insulator  16 , there is formed a dual damascene structure upper layer signal wire  17  (first upper layer wiring) piercing the barrier film  15   c  and connecting to the connection wiring  15 A. The upper layer signal wire  17  includes a ViaPlug section  17 A and a wiring section  17 B. The upper layer signal wire  17  comprises a liner metal  17   a  such as TaN and a wiring metal  17   b  such as Cu. 
     In this configuration, the lower layer signal wire  13 A supplies a signal to the element section  31  via a contact  32 . The lower layer signal wire  13 B supplies a ground potential to the ground plane  15 C. This configuration suppresses occurrence of crosstalk noise due to mutual capacitance or mutual inductance between adjacent signal wires. 
     The following describes how to manufacture the semiconductor device having the above-mentioned configuration with reference to FIGS. 2A to  2 G. It should be noted that the element section  31  and the contact  32  are omitted from these figures. 
     As shown in FIG. 2A, the insulator  12  is deposited on the Si substrate  11 . A damascene wiring formation process is used to form the lower layer signal wires  13 A and  13 B on the surface. Thereafter, the interlayer insulator  14  is deposited on the entire surface. 
     Then, as shown in FIG. 2B, there are formed Viaholes  14   a  and  14   b  in the interlayer insulator  14  leading to the lower layer signal wires  13 A and  13 B, respectively. 
     Then, as shown in FIG. 2C, the liner metal  15   a  such as TaN is formed on the entire surface by using a CVD process, a sputtering process, or a plating process. On the liner metal  15   a , there is formed a plug metal  15   b  of, say, Cu or a material comprising Cu as a major component to completely fill in the Viaholes  14   a  and  14   b.    
     Here, the liner metal  15   a  is made of Ti, W, Ta, Nb, Al, Zr, V, Hf, Mo, Si, or their nitrides or oxides, or a material containing each as a major component. The plug metal  15   b  is made of Cu or Ag, or metal containing each as a major component and needs to be protected against oxidation and diffusion. The plug metal  15   b  can be made of W, Al, Au, or metal containing each as a major component. 
     Then, as shown in FIG. 2D, the liner metal  15   a  is used as a stopper to remove the plug metal  15   b  remaining on a region except Viaholes  14   a  and  14   b . When the CMP process is conducted under a condition which prevents the liner metal  15   a  from being removed, only the liner metal  15   a  remains on a region except ViaPlug. 
     Then, as shown in FIG. 2E, the barrier film  15   c  is formed on the entire surface for preventing oxidation and diffusion of the plug metal  15   b  exposed in the Viaholes  14   a  and  14   b.    
     Here, an insulator such as SiN or SiC is used for the barrier film  15   c . Alternatively, as shown in FIG. 3, it is also possible to use Ti, W, Ta, Nb, Al, Zr, V, Hf, Mo, Si, or a conductive material such as nitride containing each as a major component SiCN, SiON, SiOC, Poly Arylene, and BCB (benzocyclobutene) can be used for the barrier film  15   c.    
     Then, as shown in FIG. 2F, a PEP process, an RIE process, a CDE process, or a wet etching process is used to pattern the liner metal  15   a  and the barrier film  15   c  masked with a resist pattern  21 . There are formed the connection wirings  15 A and  15 B, and the ground plane  15 C. 
     After the ground plane  15 C is patterned, the resist pattern  21  is removed. As shown in FIG. 2G, the interlayer insulator  16  is deposited on the entire surface. 
     The dual damascene wiring formation process is used to form the upper layer signal wire  17  on the interlayer insulator  16 , providing the semiconductor device having the configuration as shown in FIG.  1 . 
     The above-mentioned processes makes it possible to easily form the ground plane  15 C for decreasing crosstalk noise which prevents fabrication of high-speed elements without substantially changing the existing multilayer wiring process. 
     As mentioned above, the ground plane formation can use the liner metal used for the ViaPlug formation. Namely, the ground place need not use a low-resistance material such as the signal wire. Accordingly, it is possible to form the ground plane by using the liner metal or the barrier metal. The ground plane can be easily formed without the need for a special apparatus or process or without causing a dishing condition. Accordingly, it is possible to easily prevent the ground plane from sinking largely without substantially changing the existing multilayer wiring process. 
     In addition, the ViaPlug formation process is used for forming the ground plane. Accordingly, processes can be simplified. It is possible to decrease the number of processes compared to a case where ViaPlug and the ground plane are formed independently. By using the ViaPlug formation process, it is possible to stably form the ground plane by minimizing irregularities such as dents. 
     (Second Embodiment) 
     FIG. 4 shows a configuration example of a semiconductor device according to the second embodiment of the present invention. Explained here is the semiconductor device using such metals as W, Al, Au, and the like which need not be protected against oxidation and diffusion. 
     In FIG. 4, an insulator  12  is formed on an Si substrate (semiconductor substrate)  11 . On the surface of the insulator  12 , there are formed damascene structure lower layer signal wires (first and second lower layer wirings)  13 A and  13 B. The lower layer signal wires  13 A and  13 B are made of liner metal  13   a  such as TaN and wiring metal  13   b  such as Cu, respectively. 
     The lower layer signal wire  13 A is electrically connected to an element section  31  formed on the surface of the Si substrate  11  by means of a contact  32 . 
     An interlayer insulator (first interlayer film)  14  is provided on the insulator  12  where the lower layer signal wires  13 A and  13 B are provided. On this interlayer insulator  14 , there are formed damascene structure connection wirings  15 A′ (first connection wiring) and  15 B′ (second connection wiring). The connection wirings  15 A′ leads to the lower layer signal wire  13 A. The connection wirings  15 B′ leads to the lower layer signal wire  13 B. On the interlayer insulator  14 , there is formed a ground plane (plate electrode)  15 C′ leading to the connection wiring  15 B′. 
     The connection wiring  15 A′ and  15 B′ each have a ViaPlug configuration. This configuration comprises the liner metal  15   a  (first film) such as TiN and a plug metal  15   b ′ (second film) such as W having lower resistance than the liner metal  15   a.    
     The ground plane  15 C′ is formed by using the liner metal  15   a  for configuring the connection wirings  15 A′ and  15 B′. Namely, this embodiment forms the ground plane  15 C′ integrally with the connection wiring  15 B′ by means of the liner metal  15   a.    
     The interlayer insulator  16  (second interlayer film) is provided on the interlayer insulator  14  where the connection wirings  15 A′ and  15 B′ and the ground plane  15 C′ are provided. On this interlayer insulator  16 , there is formed the dual damascene structure upper layer signal wire  17  (first upper layer wiring) connecting to the connection wiring  15 A′. The upper layer signal wire  17  includes the ViaPlug section  17 A and the wiring section  17 B. The upper layer signal wire  17  comprises the liner metal  17   a  such as TaN and the wiring metal  17   b  such as Cu. 
     In this configuration, the lower layer signal wire  13 A supplies a signal to the element section  31  via a contact  32 . The lower layer signal wire  13 B supplies a ground potential to the ground plane  15 C′. This configuration suppresses occurrence of crosstalk noise due to mutual capacitance or mutual inductance between adjacent signal wires. 
     The following describes how to manufacture the semiconductor device having the above-mentioned configuration with reference to FIGS. 5A to  5 G. It should be noted that the element section  31  and the contact  32  are omitted from these figures. 
     As shown in FIG. 5A, the insulator  12  is deposited on the Si substrate  11 . A damascene wiring formation process is used to form the lower layer signal wires  13 A and  13 B on the surface. Thereafter, the interlayer insulator  14  is deposited on the entire surface. 
     Then, as shown in FIG. 5B, there are formed Viaholes  14   a  and  14   b  in the interlayer insulator  14  leading to the lower layer signal wires  13 A and  13 B, respectively. Then, as shown in FIG. 5C, the liner metal  15   a  such as TiN is formed on the entire surface by using a CVD process, a sputtering process, or a plating process. On the liner metal  15   a , there is formed plug metal  15   b ′ of, say, tungsten (W) or a material comprising W as a major component to completely fill in the Viaholes  14   a  and  14   b.    
     Here, the liner metal  15   a  is made of Ti, W, Ta, Nb, Al, Zr, V, Hf, Mo, Si, their nitride or oxide, or a material containing each as a major component. The plug metal  15   b ′ is made of Al or Au, or metal containing each as a major component and needs not be protected against oxidation and diffusion in addition to W. Accordingly, no barrier film needs to be formed in the subsequent processes. 
     Then, as shown in FIG. 5D, the liner metal  15   a  is used as a stopper to remove the plug metal  15   b ′ remaining on a region except Viaholes  14   a  and  14   b . When the CMP process is conducted under conditions which prevent the liner metal  15   a  from being removed, only the liner metal  15   a  remains on a region except the ViaPlug. 
     As shown in FIG. 5F, the resist pattern  21  is formed on the entire surface. Then, a PEP process, an RIE process, a CDE process, or a wet etching process is used to pattern the liner metal  15   a  and the barrier film  15   c  masked with the resist pattern  21 . Thus, there are formed the connection wirings  15 A′ and  15 B′, and the ground plane  15 C′. 
     After the ground plane  15 C′ is patterned, the resist pattern  21  is removed as shown in FIG.  5 F. As shown in FIG. 5G, the interlayer insulator  16  is deposited on the entire surface. 
     The dual damascene wiring formation process is used to form the upper layer signal wire  17  on the interlayer insulator  16 , providing the semiconductor device having the configuration as shown in FIG.  4 . 
     Like the first embodiment, the above-mentioned processes make it possible to easily form the ground plane  15 C′ for decreasing crosstalk noise which prevents fabrication of high-speed elements without substantially changing the existing multilayer wiring process. 
     Besides, the second embodiment forms a ViaPlug by using the metal which need not be protected against oxidation and diffusion. Accordingly, it is possible to omit formation of the barrier film as described in the first embodiment. 
     Needless to say, the surface of the plug metal  15   b ′ can be protected by a barrier film such as SiN, SiC, SiCN, SiON, SiOC, Poly Arylene, and BCB (benzocyclobutene). 
     Even if a slight mask misalignment occurs in the ground plane, it is possible to maintain high process consistency between upper and lower signal wires. 
     The Plug metal  15   b ′ can be made of Cu or Ag, or metal containing each as a major component. 
     (Third Embodiment) 
     The above-mentioned first and second embodiments have explained the examples in which the lower layer signal wire  13 B supplies a ground potential to the ground planes  15 C and  15 C′. The present invention is not limited thereto. As shown in FIGS. 6 to  8 , it is also possible to supply a ground potential from an upper layer signal wire  17 ′ (second upper layer wiring). The upper layer signal wire  17 ′ can be formed concurrently with the formation of the upper layer signal wire  17  by means of similar processes. In any of these examples, it is possible to omit the lower layer signal wire  13 B, and the connection wirings  15 B and  15 B′. 
     As has been described above in detail, the above-described embodiments can provide a semiconductor device and a manufacturing method thereof capable of decreasing crosstalk noise and easily preventing a plate electrode from sinking largely due to dishing. 
     Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.