Abstract:
A battery voltage monitor circuit for monitoring a voltage of plural secondary batteries includes first and second logic circuit parts that select first and second secondary batteries from the plural secondary batteries according to first and second command signals supplied from an external device, first and second reference voltage generation parts that generate first and second reference voltages, first and second AD conversion parts that digitalize a voltage of both ends of the first and second secondary batteries into first and second digital signals by using the first and second reference voltages, first and second communication parts that transmit the first and second digital signals to the external device.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention generally relates to a battery voltage monitor circuit, such as a battery voltage monitor circuit for monitoring voltages of multiple secondary batteries connected in series. 
     2. Description of the Related Art 
     In recent years, a secondary battery (e.g., lithium ion battery) is used as a power source mounted on a vehicle such as an electric-powered bicycle or an automobile. The lithium ion battery is to be equipped with a monitor circuit for monitoring the voltage of the lithium ion battery. In a case of using a single battery pack having multiple lithium ion batteries connected in series, the monitor circuit accurately measures the voltage of each of the multiple lithium ion batteries and notifies the measurement result to an upper level device such as an external CPU (Central Processing Unit). 
     A protection apparatus and a condenser of a module battery having multiple secondary batteries connected in series according to a related art example (see, for example, Japanese Laid-Open Patent Publication No. 2001-177998) includes a first protection unit that detects a voltage between terminals of the secondary batteries and outputs a signal to stop the charging/discharging of the module battery in a case where the detected voltage of the terminals of the secondary batteries is beyond a predetermined range, and a second protection unit that detects a voltage between terminals of the module battery and outputs a signal to stop the charging/discharging of the module battery in a case where the detected voltage of the terminals of the module battery is beyond a predetermined range. 
     Although battery voltage monitor circuits that monitor the voltage of a battery pack are expected to have high reliability, the reliability of the battery voltage monitor circuits may be degraded by harsh environmental usage conditions (e.g., temperature, vibration) in a case where the battery pack is mounted on a vehicle. 
     As one method for improving reliability of the battery voltage monitor circuits under a harsh environmental usage conditions, there is a method of dualizing the battery voltage monitor circuit mounted on the battery pack. However, this dualizing method has a problem of doubling the cost of the battery voltage monitor circuit. 
     SUMMARY OF THE INVENTION 
     The present invention may provide a battery voltage monitor circuit that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art. 
     Features and advantages of the present invention will be set forth in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a battery voltage monitor circuit particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention. 
     To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, an embodiment of the present invention provides a battery voltage monitor circuit for monitoring a voltage of a plurality of secondary batteries, the battery voltage monitor circuit including: a first logic circuit part that selects a first secondary battery from the plural secondary batteries according to a first command signal supplied from an external device; a first reference voltage generation part that generates a first reference voltage; a first AD conversion part that digitalizes a voltage of both ends of the first secondary battery into a first digital signal by using the first reference voltage; a first communication part that transmits the first digital signal to the external device; a second logic part that selects a second secondary battery from the plural secondary batteries according to a second command signal supplied from the external device; a second reference voltage generation part that generates a second reference voltage; a second AD conversion part that digitalizes a voltage of both ends of the second secondary battery into a second digital signal by referring to the second reference voltage; and a second communication part that transmits the second digital signal to the external device. 
     Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram illustrating a configuration of a battery voltage monitor circuit according to an embodiment of the present invention; 
         FIG. 2  is a flowchart illustrating an operation performed by a battery voltage monitor circuit according to an embodiment of the present invention in a case where the battery voltage monitor circuit changes from a standby mode to an active mode according to an instruction from an external CPU; 
         FIG. 3  is a cross-sectional view of a batter voltage monitor circuit according to an embodiment of the present invention; and 
         FIG. 4  is a cross-sectional view of a batter voltage monitor circuit according to another embodiment of the present invention. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In the following, embodiments of the present invention will be described with reference to the accompanying drawings. 
     &lt;Circuit Configuration of Battery Voltage Monitor Circuit&gt; 
       FIG. 1  is a schematic diagram illustrating a configuration of a battery voltage monitor circuit  10  according to an embodiment of the present invention. In  FIG. 1 , the battery voltage monitor circuit  10  includes a semiconductor chip  11  and another semiconductor chip  12 . The semiconductor chip  11  and the semiconductor chip  12  are manufactured in separated processes. 
     The semiconductor chip  11  includes, a cell balance control part  21 , a level shift buffer part  22 , an AD converter (Analog/Digital Converter (ADC))  23 , a band gap reference voltage generation part (BGR)  24 , an oscillation part (OSC)  25 , a serial communication part  26 , a logic circuit part  27 , a switch  28 , and regulators  29 ,  30 ,  31 , and a multiplexer  32 . 
     The semiconductor chip  12  includes an AD converter  33 , a band gap reference voltage generation part  34 , an oscillation part  35 , a serial communication part  36 , a logic circuit part  37 , and a switch  38 . The AD converter  33  has the same circuit configuration as the AD converter  23 ; The band gap reference voltage generation part  34  has the same circuit configuration as the band gap reference voltage generation part  24 ; the oscillation part  35  has the same circuit configuration as the oscillation part  25 ; the serial communication part  36  has the same circuit configuration as the serial communication part  26 ; the logic circuit part  37  has the same circuit configuration as the logic circuit part  27 ; and the switch  38  has the same circuit configuration as the switch  28 . 
     The cell balance control part  21  switches on one of the n-channel MOS transistors M 1 -M 16  by outputting a high level signal to one of the external terminals CB 1  to CB 16  of the semiconductor chip  11  in accordance with control signals from the logic circuit part  27 ,  37 . In a case where one of the MOS transistors M 1  to M 16  is switched on, both ends of one of the battery cells Cell  1  to Cell  16  are connected by way of limiting resistors R 1  to R 16 , and the battery cells Cell  1  to Cell  16  are discharged. Thereby, a cell balancing process can be performed in which the voltage of each of the battery cells Cell  1  to Cell  16  becomes constant. 
     It is to be noted that each of the battery cells Cell  1  to Cell  16  connected in series is a lithium ion battery according to an embodiment of the present invention. Both ends of the battery cell Cell  1  are connected to corresponding external terminals V 0 , V 1  by way of a protection resistor, and both ends of the battery cell Cell  2  are connected to corresponding terminals V 1 , V 2 . Likewise, both ends of the subsequent battery cells are connected in the similar manner as described above. Lastly, both ends of the battery cells Cell  16  are connected to corresponding external terminals V 15 , V 16  by way of a protection resistor. 
     In a case where control signals from the logic circuit parts  27 ,  37  instruct selection of the battery cell Cell  1 , the level shift buffer part  22  outputs the voltage of the external terminal V 1  to the switches  28 ,  38  in a state where the voltage of the external terminal V 0  has shifted to ground level. In a case where control signals from the logic circuit parts  27 ,  37  instruct selection of the battery cell Cell  2 , the level shift buffer part  22  outputs the voltage of the external terminal V 2  to the switches  28 ,  38  in a state where the voltage of the external terminal V 1  has shifted to ground level. Likewise, in a case where control signals from the logic circuit parts  27 ,  37  instruct selection of the subsequent battery cells, the level shift buffer part  22  to outputs voltages in the similar manner as described above. Lastly, in a case where control signals from the logic circuit part  27 ,  37  instruct selection of the battery cell Cell  16 , the level shift buffer part  22  outputs the voltage of the external terminal V 16  to the switches  28 ,  38  in a state where the voltage of the external terminal V 15  has shifted to ground level. 
     The switch  28  supplies an output voltage of the level shift buffer part  22  to the AD converter  23  when a control signal from the logic circuit part  27  instructs that the battery voltage be measured (battery voltage measurement). The switch  28  supplies an output voltage of the multiplexer  32  to the AD converter  23  when a control signal from the logic circuit part  27  instructs temperature be measured or self-diagnosis be performed. The band gap reference voltage generation part  24  generates a reference voltage by using a band gap circuit and supplies the reference voltage to the AD converter  23 . The oscillation part  25  generates a clock and supplies the clock to the AD converter  23 , the serial communication part  26 , and the logic circuit part  27 . 
     The AD converter  23  digitalizes the output voltage of the level shift buffer part  22  (i.e. battery voltage) or the output voltage of the multiplexer  32  (temperature or test voltage) and supplies, the digitalized output voltage to the logic circuit part  27 . 
     The logic circuit part  27  is connected to an external device (e.g., external CPU (not illustrated)) interposed by external terminals SHDN, ALARM, TEST 1 , TEST 2 , and an isolation part  40 . The logic circuit part  27  interprets the control commands (command signals) supplied from the external CPU and supplies control signals to each part of the semiconductor chip  11  according to the interpretation of the command signals. Further, the logic circuit part  27  supplies chip selection signals (supplied from the external CPU (not illustrated)) to the external terminal CS 1  by way of the serial communication part  26 . The logic circuit part  27  supplies digital measured battery voltage signals (digital signals indicating measured battery voltage) from the AD converter  23  to the serial communication part  26  when measuring battery voltage. The logic circuit part  27  supplies digital measured temperature signals (digital signals indicating measured temperature) to the serial communication part  26  when measuring temperature. It is to be noted that the isolation part  40  performs level shift of signals communicated (transmitted/received) between the battery voltage monitor circuit  10  and the external CPU. 
     Further, the logic circuit part  27  includes a non-volatile memory  27   a  in which various reference values are recorded beforehand. The reference values include, for example, a reference voltage output from the band gap reference voltage generation part  24  during a normal state, a test voltage applied to the external terminal TC 4  by way of the isolation part  40  during self-diagnosis. The logic circuit part  27  determines whether the AD converter  23  or the band gap reference voltage generation part  24  is operating normally or whether there is a failure by comparing the reference voltage output from the band gap reference voltage generation part  24  or the test voltage applied to the external terminal TC 4  with respect to the reference values stored in the non-volatile memory  27   a  during self-diagnosis. In a case where there is a failure, an alarm signal is supplied from the external terminal ALARM to an external CPU. 
     The serial communication part  26  supplies the digital measured battery voltage signals or the digital measured temperature signals (which are supplied from the AD converter  23  by way of the logic circuit part  27 ) together with clock signals to an external CPU by way of external terminals SD 0 , SD 1 , CLK 1  and the isolation part  40 . It is to be noted that the serial communication part  26  outputs the above-described digital signals in a case where, for example, a high level chip selection signal is supplied from an external CPU by way of the external terminal CS 1 . 
     The regulator  29  generates a direct current voltage (e.g., 4.5 V) by using a voltage supplied from the battery cells Cell  1  to Cell  16  connected in series and supplies the generated direct current voltage to the band gap reference voltage generation part  24  of the semiconductor chip  11  and the band gap reference voltage generation part  34  of the semiconductor chip  12 . The regulator  30  generates a direct current voltage (e.g., 3.3 V) by using a direct current voltage of, for example, 4.5 V and supplies the generated direct current voltage from an external terminal TDVDD to external thermistors  41 ,  42 ,  43 . 
     The regulator  31  generates a direct current voltage (e.g., 3.3 V) by using a direct current voltage of, for example, 4.5 V and supplies the generated direct current voltage to the AD converter  23 , the oscillation part  25 , the serial communication part  26 , the logic circuit part  27 , the multiplexer  32 , the AD converter  33 , the oscillation part  35 , the serial communication part  36 , and the logic circuit part  37 . 
     The multiplexer  32  selects one of the output voltage of the thermistors  41 ,  42 ,  43  supplied from the external terminals TC 1 , TC 2 , TC 3 , the test voltage supplied from, for example, an external CPU to the external terminal TC 4 , and the voltage supplied from an externally attached multiplexer (not illustrated) to the external terminal TempIN, and supplies the selected voltage to the switches  28 ,  38 . 
     The switch  38  supplies an output voltage of the level shift buffer part  22  to the AD converter  33  when a control signal from the logic circuit part  37  instructs that the battery voltage be measured (battery voltage measurement). The switch  38  supplies an output voltage of the multiplexer  32  to the AD converter  33  when a control signal from the logic circuit part  37  instructs temperature be measured or self-diagnosis be performed. The band gap reference voltage generation part  34  generates a reference voltage by using a band gap circuit and supplies the reference voltage to the AD converter  33 . The oscillation part  35  generates a clock and supplies the clock to the AD converter  33 , the serial communication part  36 , and the logic circuit part  37 . 
     The AD converter  33  digitalizes the output voltage of the level shift buffer part  22  (i.e. battery voltage) or the output voltage of the multiplexer  32  (temperature or test voltage) and supplies the digitalized output voltage to the logic circuit part  37 . 
     The logic circuit part  37  is connected to an external CPU (not illustrated) interposed by external terminals SHDN, ALARM, TEST 1 , TEST 2 , and the isolation part  40 . The logic circuit part  37  interprets the control commands supplied from the external CPU and supplies control signals to each part of the semiconductor chip  12  according to the interpretation. Further, the logic circuit part  37  supplies chip selection signals (supplied from the external CPU (not illustrated)) to the external terminal CS 2  by way of the serial communication part  36 . The logic circuit part  37  supplies digital measured battery voltage signals (digital signals indicating measured battery voltage) from the AD converter  33  to the serial communication part  36  when measuring battery voltage. The logic circuit part  37  supplies digital measured temperature signals (digital signals indicating measured temperature) to the serial communication part  36  when measuring temperature. 
     Further, the logic circuit part  37  includes a non-volatile memory  37   a  in which various reference values are recorded beforehand. The reference values include, for example, a reference voltage output from the band gap reference voltage generation part  34  during a normal state, a test voltage applied to the external terminal TC 4  by way of the isolation part  40  during self-diagnosis. The logic circuit part  37  determines whether the AD converter  33  or the band gap reference voltage generation part  34  is operating normally or whether there is a failure by comparing the reference voltage output from the band gap reference voltage generation part  34  or the test voltage applied to the external terminal TC 4  with respect to the reference values stored in the non-volatile memory  37   a  during self-diagnosis. In a case where there is a failure, an alarm signal is supplied from the external terminal ALARM to an external CPU. 
     The serial communication part  36  supplies the digital measured battery voltage signals or the digital measured temperature signals (which are supplied from the AD converter  33  by way of the logic circuit part  37 ) together with clock signals to an external CPU by way of external terminals SD 0 , SD 1 , CLK 1  and the isolation part  40 . It is to be noted that the serial communication part  36  outputs the above-described digital signals in a case where, for example, a high level chip selection signal is supplied from an external CPU by way of the external terminal CS 2 . 
     &lt;Operation Mode of Battery Voltage Monitor Circuit&gt; 
     The battery voltage monitor circuit  10  activates the regulators  29  to  31  and goes into a standby mode when, for example, a high level signal is supplied from an external CPU to an external terminal SHDN. Then, when a high level chip selection signal is supplied to the external terminal CS 1  or the external terminal CS 2 , the battery voltage monitor circuit  10  becomes an active mode. Thereby, the battery voltage monitor circuit  10  performs voltage measurement by using the AD converter  23  or the AD converter  33  and outputs digital signals indicating the results of the voltage measurement by using the serial communication part  26  or the serial communication part  36 . Then, when a low level chip selection signal is supplied to the external terminal CS 1  or the external terminal CS 2 , the battery voltage monitor circuit  10  becomes a standby mode. Further, the battery voltage monitor circuit  10  stops (shuts down) all components including the regulators  29  to  31  when a low level signal is supplied to the external terminal SHDN. 
     &lt;Flowchart&gt; 
       FIG. 2  is a flowchart illustrating an operation performed by the battery voltage monitor circuit  10  according to an instruction from an external CPU in a case where the battery voltage monitor circuit  10  changes from a standby mode to an active mode. In Step S 1 , each of the logic circuit parts  27 ,  37  performs self-diagnosis according to an instruction from the external CPU. For example, the logic circuit parts  27 ,  37  determine whether the AD converters  23 ,  33  and/or the band gap reference voltage generation parts  24 ,  34  are operating normally by comparing the reference values stored in the non-volatile memory  27   a ,  37   a  with respect to, for example, the reference voltages output by the band gap reference voltage generation parts  24 ,  34  and/or the test voltage applied to the external terminal TC 4 . In a case where the logic circuit parts  27 ,  37  determine that the AD converters  23 ,  33  and/or the band gap reference voltage generation parts  24 ,  34  are not operating normally (failure), the external terminal ALARM supplies an alarm signal to the external CPU. 
     In Step S 2 , the external CPU determines whether the AD converter  23  and the band gap reference voltage generation part  24  of the semiconductor chip  11  are operating normally. In a case where the AD converter  23  and the band gap reference voltage generation part  24  of the semiconductor chip  11  are determined as operating normally (Yes in Step S 2 ), the battery voltage monitor circuit  10  is switched to an active mode by supplying a high level chip selection signal from the external CPU to only the external terminal CS 1 . Thereby, the battery voltage monitor circuit  10  outputs a digital measured battery voltage or a digital measured temperature by using the AD converter  23 , the band gap reference voltage generation part (BGR)  24 , the oscillation part (OSC)  25 , the serial communication part  26 , the logic circuit part  27 , and the switch  28 . 
     On the other hand, in a case where the AD converter  23  and the band gap reference voltage generation part  24  of the semiconductor chip  11  are determined as not operating normally (determined as failure) (No in Step S 2 ), the external CPU determines whether the AD converter  33  and the band gap reference voltage generation part  34  of the semiconductor chip  12  are operating normally in Step S 4 . In a case where the AD converter  33  and the band gap reference voltage generation part  34  of the semiconductor chip  12  are determined as operating normally (Yes in Step S 4 ), the battery voltage monitor circuit  10  is switched to an active mode by supplying a high level chip selection signal from the external CPU to only the external terminal CS 2 . Thereby, the battery voltage monitor circuit  10  outputs a digital measured battery voltage or a digital measured temperature by using the AD converter  33 , the band gap reference voltage generation part (BGR)  34 , the oscillation part (OSC)  35 , the serial communication part  36 , the logic circuit part  37 , and the switch  38 . 
     In a case where the AD converter  33  and the band gap reference voltage generation part  34  of the semiconductor chip  12  are determined as not operating normally (determined as failure) (No in Step S 4 ), the external CPU shuts down the battery voltage monitor circuit  10  by supplying a low level signal to the external terminal SHDN in Step S 6 . 
     In this embodiment, the cell balance control part  21  and the level shift buffer part  22  of the semiconductor chip  11  are high voltage resistant circuit whereas the AD converter  23 , the band gap reference voltage generation part (BGR)  24 , the oscillation part (OSC)  25 , the serial communication part  26 , the logic circuit part  27 , the switch  28 , and the regulators  29 ,  30 ,  31 , and the multiplexer  32  are low pressure resistant circuits. A high voltage resistant circuit has a large chip area and includes a small number of devices (e.g., approximately several hundreds of devices). A low voltage resistant circuit has a small chip area and includes a large number of devices (e.g., approximately several ten thousands of devices) compared to the high voltage resistant circuit. Therefore, the possibility of failure occurring in the low voltage resistant circuit is significantly higher than the possibility of failure occurring in the high voltage resistant circuit. 
     Therefore, in this embodiment, the battery voltage monitor circuit  10  is provided with the semiconductor chip  12  including the AD converter  33 , the band gap reference voltage generation part  34 , the oscillation part  35 , the serial communication part  36 , the logic circuit part  37 , and the switch  38  that have substantially the same configurations as those of the main components of the low voltage resistant circuit of the semiconductor chip  11  (i.e. the AD converter  23 , the band gap reference voltage generation part  24 , the oscillation part  25 , the serial communication part  26 , the logic circuit part  27 , and the switch part  28 ). Further, by providing a self-diagnosis function to the logic circuit parts  27 ,  37 , the semiconductor chip  12  can be used in a case where the logic circuit parts  27 ,  37  determines a failure occurring in the AD converter  23  or the band gap reference voltage generation part  24 . Thereby, reliability of the battery voltage monitor circuit  10  can be improved. Because the semiconductor chip  12  is inexpensive compared to the semiconductor chip  11 , cost of the battery voltage monitor circuit  10  can be kept at a low cost. 
     &lt;Cross Section of Battery Voltage Monitor Circuit&gt; 
       FIG. 3  is a cross-sectional view of the batter voltage monitor circuit according to an embodiment of the present invention. In  FIG. 3 , the semiconductor chip  11  is fixed onto a stage  51 . The semiconductor chip  12  is arranged (layered) on top of the semiconductor chip  11  and fixed to the semiconductor chip  11  by using an insulating adhesive agent. The external terminals of the semiconductor chips  11 ,  12  are connected to leads  53  with wires  52 . The stage  51 , the semiconductor chips  11 ,  12 , the wires  52 , and the leads  53  are encapsulated by an encapsulating material (e.g., encapsulating resin)  54  except for a portion of the leads  53 . 
     Alternatively, the semiconductor chip  11  and the semiconductor chip  12  may be formed on a same plane as illustrated in  FIG. 4  instead of being arranged one on top of the other. In  FIG. 4 , the semiconductor chip  11  is fixed onto a stage  61  and the semiconductor chip  12  is fixed onto a stage  62 . The external terminals of the semiconductor chips  11 ,  12  are connected to leads  64  with wires  63 . The external terminal(s) of the semiconductor chip  11  and the external terminal(s) of the semiconductor chip  12  are also connected to each other with wires  65 . The stages  61 ,  62 , the semiconductor chips  11 ,  12 , the wires  63 ,  65 , and the leads  64  are encapsulated by an encapsulating material (e.g., encapsulating resin)  66  except for a portion of the leads  64 . 
     The semiconductor chip  11  and the semiconductor chip  12  are separate chips. One reason that the semiconductor chip  11  and the semiconductor chip  12  are separate chips is because a leak current caused by failure (e.g., short-circuiting) of, for example, the AD converter  23  or the band gap reference voltage generation part  24  of the semiconductor chip  11  can be prevented from flowing to the semiconductor chip  12 . Thereby, the semiconductor chip  12  can be prevented from being affected by the failure occurring in the semiconductor chip  11 . 
     With the layered configuration of the semiconductors  11 ,  12  in  FIG. 3 , the stress applied to the semiconductor  11  and the stress applied to the semiconductor  12  can be substantially equal during the process of encapsulating the semiconductor chips  11 ,  12  with the encapsulating resin  54 . Because the stress applied to the semiconductor chips  11 ,  12  affects the characteristics of the circuit elements constituting the semiconductor chips  11 ,  12 , the characteristics of the AD converter  23  and the band gap reference voltage generation part  24  formed on the semiconductor chip  11  can be substantially the same as the characteristics of the AD converter  33  and the band gap reference voltage generation part  34  formed on the semiconductor chip  12 . In other words, even in a case where the AD converter  23  and the band gap reference voltage generation part  24  of the semiconductor chip  11  are switched to the AD converter  33  and the band gap reference voltage generation part  34  of the semiconductor chip  12 , there is hardly any change in the voltage measured with the battery voltage monitor circuit  10 . 
     Further, the present invention is not limited to these embodiments, but variations and modifications may be made without departing from the scope of the present invention. 
     The present application is based on Japanese Priority Application No. 2012-050374 filed on Mar. 7, 2012, with the Japanese Patent Office, the entire contents of which are hereby incorporated by reference.