Abstract:
This disclosure includes a method for securing a memory of an electronic system that includes initializing the memory, creating a security key, transmitting the security key to memory, storing the security key in the memory, transmitting the current security key and a new security key to the memory by the memory controller. If the current security key transmitted is the same as the security key stored in memory, then access to the memory is enabled and the current security key in the memory is replaced with the new security key. If the current security key transmitted is not the same as the security key stored in the memory, then access to the memory is disabled.

Description:
TECHNICAL FIELD 
     This disclosure relates to memory security. In particular, it relates to memory security for a removable memory. 
     BACKGROUND 
     A dynamic random access memory (DRAM) stores a bit of data on a capacitor in DRAM cells. The capacitors leak or pick up charge over time, and must be periodically refreshed for the DRAM to retain its data. Under normal operating conditions, the DRAM loses its data over a period of seconds after power has been removed from the DRAM. However, as the temperature of the DRAM decreases, the capacitors leak their charge at a slower rate. If the temperature is low enough, the DRAM may retain its data for minutes or hours after the DRAM has lost power. 
     The tendency of DRAM to retain its data at low temperatures after removal of power leaves it vulnerable to access by intruders. An intruder with physical access to a computer may bypass mechanisms that protect the computer against outside intrusion. A DIMM containing DRAM may be removed from the computer after the computer has powered down, transferred to another computer, and accessed for its data. This intrusion is a risk for any computer with DRAM, but especially so for a computer utilizing non-volatile storage encryption, as the DRAM could be accessed for the encryption keys to the storage that allow for continued access of the computer system. For example, a hard drive may be protected with an encryption algorithm that is enabled with an encryption key. However, if the hard drive was accessed in the last computer session, the encryption key may remain on the DRAM. The encryption key may be imaged and recovered by the intruder and the DRAM replaced into the original computer, without indication of hacking or access by the intruder. 
     SUMMARY 
     In an embodiment, a method for securing a memory of an electronic system includes initializing the memory and recognizing, by the memory, that initialization has occurred. A memory controller creates a current security key and transmits the current security key to the memory. The memory stores the current security key in the memory once. The memory may request that the memory controller retransmit of the current security key. The memory controller retransmits the current security key to the memory and transmits a new security key to the memory. If the current security key retransmitted by the memory controller is the same as the current security key stored in memory, then the memory enables access to the memory by the memory controller and replaces the current security key in the memory with the new security key. If the current security key retransmitted by the memory controller is not the same as the current security key stored in the memory, then the memory disables access to the memory by the memory controller. 
     In an embodiment, a memory includes a memory array and control logic. The control logic includes a register to store a first security key, an authentication event monitor to identify an authentication event, security key check logic, and signal decode logic. The security key check logic is configured to receive a second security key and compare the second security key received by the memory to the first security key stored on the register. The signal decode logic is configured to enable access to the memory when the second security key received by the memory and the first security key stored in the memory are the same, and disable access to the memory when the second security key received by the memory and the first security key stored in the memory are not the same. 
     In another embodiment, a method for securing a memory includes receiving initialization data by the memory and recognizing, by the memory, that initialization has occurred. The memory receives a first security key, stores the first security key in the first memory once, and receives a second security key and a third security key by the memory. If the second security key received is the same as the first security key stored in the memory, then the memory enables access to the memory and replaces the second security key in the memory with the third security key. If the second security key received is not the same as the first security key stored in the memory, then the memory disables access to the memory by control logic on the memory. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The drawings included in the present application are incorporated into, and form part of, the specification. They illustrate embodiments of the present invention and, along with the description, serve to explain the principles of the invention. The drawings are only illustrative of typical embodiments of the invention and do not limit the invention. 
         FIG. 1  is a flowchart of a memory security system, according to embodiments of the invention. 
         FIG. 2  is a diagram of an electronic system with a memory security mechanism, according to embodiments of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     According to the principles of the invention, a memory&#39;s contents may be secured against a physical intrusion through a remotely generated, synchronized, and periodically authenticated and replaced security key. The memory may be initialized and a memory controller located off a memory module may generate a security key. The security key may be stored on both the memory and the memory controller. During memory operation, the memory may periodically request that the memory controller provide its current security key to the memory. The memory controller transmits the current security key stored on the memory controller to the memory, as well as generates, stores, and sends a new security key to the memory. If the current security key sent to the memory matches the security key stored on the memory, the memory controller may continue to access the memory and the current security key stored on the memory is replaced with the new security key. If the current security key sent by the memory controller does not match the security key stored on the memory, the memory controller is blocked from accessing the memory. After a number of unsuccessful attempts to authenticate its security key, the memory controller may be blocked from accessing the memory until the contents of the memory are wiped and a new security key is generated and synchronized with the memory and memory controller. 
     Utilizing a unique security key that is synchronized between the memory controller and the memory may effectively tie the data contained on the memory to the electronic system containing the memory controller and on which the data is generated. By focusing the security key authentication at the memory controller level, the security key may be inaccessible to the user of the electronic system. The security key may be replaced at intervals to increase the difficulty of identifying data patterns leading to security key determination. If a valid user is locked out from using the memory due to the memory controller exceeding the attempt limit, the memory is not rendered useless, but must only be wiped of its data. 
     Method Structure 
       FIG. 1  is a flowchart of a memory security system, according to embodiments of the invention. The system initializes a memory, as in  101 . The memory may be any removable memory, such as a DRAM or SRAM. After the memory has been initialized and the memory recognizes that it has been initialized, a memory controller may generate a security key, as in  102 . A random security key generator on the memory controller may generate the security key and may be activated by an enable bit. The security key may be a word of any length, such as 128 bit, 196 bit, or 256 bit. Multiple security keys may be generated and synchronized for each rank on a DIMM, for a sub-array of a 3D DRAM, for each individual DIMM, and for multiple DIMM&#39;s. For example, one rank on a DIMM may be a secured rank requiring security key authentication, while another rank may be unsecured. Alternatively, a first DIMM may be synchronized with a first security key and a second DIMM may be synchronized with a second security key. 
     The security key may be stored in storage on the memory controller and memory, as in  103 . The memory controller may store the security key on a register outside scannable rings, so that no user can directly access the security key, including a valid user. After the memory controller transmits the security key to the memory, the memory may store the security key on a register, such as a multi-purpose register on memory control logic or a buffer chip. The security keys stored on the memory controller and the memory may be backed up for protection against soft errors or power loss, such as through latches or flash storage. 
     An authentication event monitor may monitor the memory and memory controller for signals that constitute an event requiring security authentication, as in  104 . An authentication event may include events such as refresh cycle, access interval, and power state change. For example, one authentication event may be a signal from an authentication event timer that is set to periodically require memory controller authentication; another authentication event may be a refresh signal, if the memory is a DRAM, or an access signal from a memory controller; another authentication event may be an exit command signal coming from the computer system to the memory when the computer system is coming out of a low power mode, such as sleep mode. 
     Once an authentication event occurs and is recognized by the authentication event monitor, the memory controller must authenticate itself to the memory by sending an authentication signal that includes its current security key, in order to continue accessing the memory, as in  105 . The authentication signal may also include a new security key that replaces the current security key once the current security key has been authenticated. The authentication signal may also include ECC to ensure proper transmission of the authentication signal. To generate a transmission of the current security key from the memory controller, the memory&#39;s control logic may send a request to the memory controller for the memory controller&#39;s current security key. Alternatively, the memory may be in a state where the security key is needed for operation, but where the memory does not communicate back to the memory controller to request a security key. If the current security key is not provided by the memory controller, security key check logic on the memory may block all further attempts by the memory controller to access the memory by temporarily disabling memory control functions, such as chip select and clock enable. These control functions may be controlled through the signal decode logic of a memory&#39;s control logic. 
     Once the memory controller sends the authentication signal, the current security key provided by the memory controller is compared with the security key stored on the memory, as in  106 . If the current security key sent by the memory controller matches the security key on the memory, the authentication is successful and the current security key on the memory is replaced with the new security key sent by the memory controller, to be used for the next authentication, as in  107 . The memory controller may continue to access the memory, as in  108 . If the current security key sent by the memory controller does not match the security key stored on the memory, the authentication is not successful, and the memory controller may not continue to access the memory until it presents the correct security key. 
     After an unsuccessful authentication attempt, the memory controller may continue to attempt to authenticate its security key until an authentication limit is exceeded, such as an access counter exceeding an access counter threshold, as in  109 . The access counter may return to a starter value when the security key sent by the memory controller is authenticated. The access counter for the number of memory controller attempts may be set sufficiently high to allow for soft errors that may occur during transmission of the current security key. When the access counter is exceeded, the memory controller may be disabled from accessing the memory, as in  110 , until the contents of the memory are wiped. Once the contents of the memory are wiped, as in  111 , the security key generation process may be started over again. 
     As an additional safeguard, a computer system having multiple DRAM modules may lock out all the DRAM in the computer system when it is detected that a DRAM has been locked out by the method discussed above or a DRAM module removed from the system. If one DRAM module is locked out, the locked out DRAM may send a signal that locks out the other DRAM modules. 
     Hardware Implementation 
       FIG. 2  is a diagram of an electronic system  200  with a memory security mechanism, according to embodiments of the invention. A security key generator  204  on a memory controller  202  generates a security key. The security key is stored in security key storage  205  on the memory controller  202  and written into a register  207  on control logic  206  of a memory  203 . A processor  201  may access a memory array  211  through the memory controller  202  until an authentication event monitor  208  indicates that an authentication event has occurred. While in  FIG. 2  the memory controller  202  and processor  201  are represented as different units, the memory controller  202  may also be part of the processor  201 . 
     Upon an authentication event, the control logic  206  of the memory  203  may send a request to the memory controller  202  to provide the memory controller&#39;s security key for authentication. The memory controller  202  must present the same security key that is stored in the register  207  of the memory  203  to continue to access the memory array  211 . Security key check logic  209  on the memory  203  may compare the security key provided by the memory controller  202  with the security key stored in the register  207 . If the security keys are the same, signal decode logic  210  may continue to allow the memory controller  202  to access the memory array  211 . If the security keys are not the same, the signal decode logic  210  may prevent the memory controller  202  from accessing the memory array  211  until the memory controller  202  presents the correct security key. After a number of unsuccessful attempts to authenticate the security key, the signal decode logic  210  may prevent the memory controller  202  from controlling select functions of the memory  203  until the memory array  211  is wiped and a new security key synchronized between the memory controller  202  and the memory  203 . If the signal decode logic  210  prevents the memory controller  202  from controlling select functions of the memory  203 , the control logic  206  may send a lockout signal to the signal decode logic  210  of other memories  203  so that the memory controller  202  is prevented from controlling select functions of their memory  203 . 
     Although the present invention has been described in terms of specific embodiments, it is anticipated that alterations and modifications thereof will become apparent to those skilled in the art. Therefore, it is intended that the following claims be interpreted as covering all such alterations and modifications as fall within the true spirit and scope of the invention.