Abstract:
A method of forming a resistive memory cell, e.g., CBRAM or ReRAM, includes forming a bottom electrode layer, forming an oxide region of an exposed area of the bottom electrode, removing a region of the bottom electrode layer proximate the oxide region to form a bottom electrode having a pointed tip or edge region. An electrically insulating mini-spacer region is formed adjacent the bottom electrode, and an electrolyte region and top electrode are formed over the bottom electrode and mini-spacer element(s) to define a memory element. The memory element defines a conductive filament/vacancy chain path from the bottom electrode pointed tip region to the top electrode via the electrolyte region. The mini-spacer elements decreases the effective area, or “confinement zone,” for the conductive filament/vacancy chain path, which may improve the device characteristics, and may provide an improvement over techniques that rely on enhanced electric field forces.

Description:
RELATED APPLICATIONS 
     This application is a continuation in part of co-pending U.S. application Ser. No. 14/184,331 (“the &#39;331 Non-Provisional Application”) filed on Feb. 19, 2014, and claims priority to U.S. Provisional Application No. 62/085,075 (“the &#39;075 Provisional application) filed on Nov. 26, 2014. This application also relates to U.S. non-provisional application U.S. Ser. No. 14/184,268 (“the &#39;268 Non-Provisional Application”). The entire contents of the &#39;331 Non-Provisional application, the &#39;075 Provisional application, and the &#39;268 Non-Provisional application are hereby incorporated by reference. 
    
    
     TECHNICAL FIELD 
     The present disclosure relates to resistive memory cells, e.g., conductive bridging random access memory (CBRAM) or resistive random-access memory (ReRAM) cells, having a reduced area for the formation of conductive paths (e.g., conductive filaments or vacancy chains), and including a spacer region for further reducing the conductive path area and/or enhancing the electric field. 
     BACKGROUND 
     Resistive memory cells, such as conductive bridging memory (CBRAM) and resistive RAM (ReRAM) cells are a new type of non-volatile memory cells that provide scaling and cost advantages over conventional Flash memory cells. A CBRAM is based on the physical re-location of ions within a solid electrolyte. A CBRAM memory cell can be made of two solid metal electrodes, one relatively inert (e.g., tungsten) the other electrochemically active (e.g., silver or copper), with a thin film of the electrolyte between them. The fundamental idea of a CBRAM cell is to create programmable conducting filaments, formed by either single or very few nanometer-scale ions across a normally non-conducting film through the application of a bias voltage across the non-conducting film. The non-conducting film is referred to as the electrolyte since it creates the filament through an oxidation/reduction process much like in a battery. In a ReRAM cell the conduction is through creation of a vacancy chain in an insulator. The creation of the filament/vacancy-chain creates an on-state (high conduction between the electrodes), while the dissolution of the filament/vacancy-chain is by applying a similar polarity with Joule heating current or an opposite polarity but at smaller currents to revert the electrolyte/insulator back to its nonconductive off-state. 
     A wide range of materials have been demonstrated for possible use in resistive memory cells, both for the electrolyte and the electrodes. One example is the Cu/SiOx based cell in which the Cu is the active metal-source electrode and the SiOx is the electrolyte. 
     One common problem facing resistive memory cells is the on-state retention, i.e., the ability of the conductive path (filament or vacancy chain) to be stable, especially at the elevated temperatures that the memory parts would typically be qualified to (85 C/125 C). 
       FIG. 1  shows a conventional CBRAM cell IA, having a top electrode  10  (e.g., copper) arranged over a bottom electrode  12  (e.g., tungsten), with the electrolyte or middle electrode  14  (e.g., Si02) arranged between the top and bottom electrodes. Conductive filaments  18  propagate from the bottom electrode  12  to the top electrode  10  through the electrolyte  14  when a bias voltage is applied to the cell IA. This structure has various potential limitations or drawbacks. For example, the effective cross-sectional area for filament formation, referred to herein as the effective filament formation area indicated as App, or alternatively the “confinement zone,” is relatively large and unconfined, making the filament formation area susceptible to extrinsic defects. Also, multi-filament root formation may be likely, due to a relatively large area, which may lead to weaker (less robust) filaments. In general, the larger the ratio between the diameter or width of the effective filament formation area App (indicated by “x”) to the filament propagation distance from the bottom electrode  12  to the top electrode  10  (in this case, the thickness of the electrolyte  14 , indicated by “y”), the greater the chance of multi-root filament formation. Further, a large electrolyte volume surrounds the filament, which provides diffusion paths for the filament and thus may provide poor retention. Thus, restricting the volume of the electrolyte material in which the conductive path forms may provide a more robust filament due to spatial confinement. The volume of the electrolyte material in which the conductive path forms may be restricted by reducing the area in contact between the bottom electrode  12  and the electrolyte  14 . 
     As used herein, “conductive path” refers a conductive filament (e.g., in a CBRAM cell), vacancy chain (e.g., in an oxygen vacancy based ReRAM cell), or any other type of conductive path for connecting the bottom and top electrodes of a non-volatile memory cell (typically through an electrolyte layer or region arranged between the bottom and top electrodes). 
     As used herein the “electrolyte layer” or “electrolyte region” refers to an electrolyte/insulator/memory layer or region between the bottom and top electrodes through which the conductive path propagates. 
       FIG. 2  shows certain principles of a CBRAM cell formation. Conductive paths  18  may form and grow laterally, or branch into multiple parallel paths. Further, locations of the conductive paths may change with each program/erase cycle. This may contribute to a marginal switching performance, variability, high-temp retention issues, and/or switching endurance. Restricting switching volume has been shown to benefit the operation. These principles apply to ReRAM and CBRAM cells. A key obstacle for adoption of these technologies is switching uniformity. 
       FIGS. 3A and 3B  show a schematic view and an electron microscope image of an example known bottom electrode configuration  1 B for a CBRAM cell (e.g., having a one transistor, one-resistive memory element (1T1R) architecture). In this example, the bottom electrode  12  is a cylindrical via, e.g., a tungsten-filled via with a Ti/TiN liner. The bottom electrode  12  may provide a relatively large effective filament formation area App, or confinement zone, of about 30,000 nm 2 , for example, which may lead to one or more of the problems or disadvantages discussed above. 
     SUMMARY 
     Some embodiments provide resistive memory cells, e.g., CBRAM or ReRAM cells, that focus the electric field more precisely than in known cells, which may provide more consistent filament formation, thus improving the consistency of programming voltage and cell predictability. For example, some embodiments provide methods for forming resistive memory cells (and formed memory cells/memory cell arrays) having a reduced area for the formation of conductive paths, which reduced conductive path area is defined by a path extending from a tip region (or regions) formed in the bottom electrode to a corresponding top electrode region, via an electrolyte region formed between the bottom electrode tip region and the top electrode. 
     Some embodiments include the feature of applying a thin spacer region, or “mini-spacer,” to the cell structure between the bottom electrode and the electrolyte layer, on the lateral side or sides of the bottom electrode structure. The spacer region may be formed from an electrically insulating material, e.g., a dielectric, or any other suitable material. The insulating spacer may thus decrease the available or possible area for filament formation between the bottom electrode and top electrode via the electrolyte region. In some embodiments, the effective cross-sectional area, or “confinement zone,” of the bottom electrode may be reduced in comparison to known resistive memory cells. For example, the confinement zone may be reduced to less than 1,000 nm 2 , less than 100 nm 2 , less than 10 nm 2 , or even less than 1 nm 2 . This may increase the restriction of filament formation to the tip of the bottom electrode, which may improve the device characteristics, and may provide an improvement over techniques that rely on enhanced electric field forces. 
     One embodiment provides a method of forming a resistive memory cell, including forming a bottom electrode layer on a substrate; oxidizing an exposed region of the bottom electrode layer to form an oxide region; removing a region of the bottom electrode layer proximate the oxide region, thereby forming a bottom electrode having a sidewall and a pointed tip region at a top of the sidewall adjacent the oxide region; depositing a spacer layer over at least the pointed tip region of the bottom electrode and the adjacent oxide region; removing a portion of the spacer layer such that a spacer region remains laterally adjacent the sidewall of the bottom electrode; and forming an electrolyte region and a top electrode over at least the spacer region, the pointed tip region of the bottom electrode, and the adjacent oxide region, such that the electrolyte region is arranged between the top electrode and the pointed tip region of the bottom electrode. 
     Another embodiment provides a method of forming an array of cells, including forming a bottom electrode layer on a substrate; oxidizing a plurality of exposed regions of the bottom electrode layer to form a plurality of oxide regions spaced apart from each other; removing regions of the bottom electrode layer between adjacent oxide regions, thereby forming a plurality of bottom electrodes, each bottom electrode having a sidewall and a respective oxide region at an upper side of the bottom electrode and at least one pointed tip region at a top of the sidewall adjacent the respective oxide region; depositing a spacer layer over the plurality of bottom electrodes and respective oxide regions; removing portions of the spacer layer such that a spacer region remains laterally adjacent the sidewall of each respective bottom electrode; forming an electrolyte layer and a top electrode layer over the plurality of bottom electrodes, spacer regions, and respective oxide regions; and removing portions of the electrolyte layer and a top electrode layer to form an electrolyte region and a top electrode on each bottom electrode and respective oxide region, thereby forming an array of cells, each cell including a respective bottom electrode, a respective oxide region, a respective electrolyte region, and a respective top electrode; wherein, for each cell: the respective electrolyte region is arranged between the pointed tip region of the respective bottom electrode and the respective top electrode, thereby providing a path for the formation of at least one conductive filament or vacancy chain from the pointed tip region of the respective bottom electrode to the respective top electrode through the respective electrolyte region; and the spacer region is located laterally between a portion of the bottom electrode sidewall below the tip region and a respective portion of the electrolyte region. 
     Another embodiment provides method of forming a resistive memory cell, including forming a bottom electrode layer on a substrate; oxidizing an exposed region of the bottom electrode layer to form an oxide region; removing a region of the bottom electrode layer proximate the oxide region, thereby forming a bottom electrode having a sidewall and a pointed tip region at a top of the sidewall adjacent the oxide region; depositing a spacer layer over at least the pointed tip region of the bottom electrode and the adjacent oxide region; removing a portion of the spacer layer such that a spacer region remains laterally adjacent the sidewall of the bottom electrode; and forming: (a) a first electrolyte region and first top electrode over a first portion of the pointed tip region of the bottom electrode and a corresponding first portion of the spacer region, such that the first electrolyte region is arranged between the first top electrode and the first portion of the pointed tip region of the bottom electrode to define a first memory element, and the first portion of the spacer region is located laterally between a first portion of the bottom electrode below the first portion of the pointed tip region and a respective portion of the first electrolyte region; and (b) a second electrolyte region and second top electrode over a second portion of the pointed tip region of the bottom electrode and a corresponding second portion of the spacer region, such that the second electrolyte region is arranged between the second top electrode and the second portion of the pointed tip region of the bottom electrode to define a second memory element, and the second portion of the spacer region is located laterally between a second portion of the bottom electrode below the second portion of the pointed tip region and a respective portion of second first electrolyte region. 
     Another embodiment provides a method of forming an array of memory elements, including forming a bottom electrode layer on a substrate; oxidizing a plurality of exposed regions of the bottom electrode layer to form a plurality of oxide regions spaced apart from each other; removing regions of the bottom electrode layer between adjacent oxide regions, thereby forming a plurality of bottom electrodes, each bottom electrode having a sidewall and a respective oxide region at an upper side of the bottom electrode and at least one pointed tip region at a top of the sidewall adjacent the respective oxide region; depositing a spacer layer over the plurality of bottom electrodes and respective oxide regions; removing portions of the spacer layer such that a spacer region remains laterally adjacent the sidewall of each respective bottom electrode; and for each bottom electrode, forming a pair of memory elements, each memory element defined by a respective region of the bottom electrode pointed tip, a respective top electrode, and an electrolyte region arranged therebetween, and a respective spacer region located laterally between a portion of the bottom electrode sidewall below the tip region and a respective portion of the electrolyte region. 
     Another embodiment provides an array of resistive memory structures, each including a bottom electrode formed on a substrate; an oxide region adjacent the bottom electrode; wherein the bottom electrode has a sidewall and a pointed tip region at a top of the sidewall proximate the oxide region; a dielectric spacer region laterally adjacent the bottom electrode sidewall; a first electrolyte region and first top electrode formed over a first portion of the pointed tip region of the bottom electrode and a corresponding first portion of the spacer region, with the first electrolyte region arranged between the first top electrode and the first portion of the pointed tip region of the bottom electrode to define a first memory element, and the first portion of the spacer region is located laterally between a first portion of the bottom electrode below the first portion of the pointed tip region and a respective portion of the first electrolyte region; and a second electrolyte region and second top electrode over a second portion of the pointed tip region of the bottom electrode and a corresponding second portion of the spacer region, with the second electrolyte region is arranged between the second top electrode and the second portion of the pointed tip region of the bottom electrode to define a second memory element, and the second portion of the spacer region is located laterally between a second portion of the bottom electrode below the second portion of the pointed tip region and a respective portion of second first electrolyte region. 
    
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
       Example embodiments are discussed below with reference to the drawings, in 
         FIG. 1  shows an example conventional CBRAM cell; 
         FIG. 2  shows certain principles of CBRAM cell formation; 
         FIGS. 3A and 3B  show a schematic view and an electron microscope image of an example known CBRAM cell configuration; 
         FIGS. 4A-4M  illustrate an example method for forming an array of resistive memory cells, e.g., CBRAM or ReRAM cells, according to one embodiment of the present invention; 
         FIG. 5A  illustrates a first example top electrode contact configuration, according to one embodiment; 
         FIG. 5B  illustrates a second example top electrode contact configuration, according to another embodiment; and 
         FIGS. 6A-6O  illustrate another example method for forming an array of resistive memory cells, e.g., CBRAM or ReRAM cells, according to one embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
       FIGS. 4A-4M  illustrate an example method for forming an array of resistive memory cells, e.g., an array of conductive bridging memory (CBRAM) and resistive RAM (ReRAM) cells, according to one embodiment. As shown in  FIG. 4A , a dielectric substrate  100  (e.g., Si02) is formed, using any suitable technique. Next, as shown in  FIG. 4B , a bottom electrode layer  102  and a hard mask layer  104  are deposited or formed over the dielectric substrate  100 . Bottom electrode layer  102  may comprise any suitable conductive material or materials, e.g., polysilicon, doped polysilicon, amorphous silicon, doped amorphous silicon, or any other suitable material, and may be deposited or formed in any suitable manner. Hard mask layer  104  may be formed from any suitable materials (e.g., silicon nitride) and may be deposited or formed in any suitable manner as known in the art. 
     Next, as shown in  FIG. 4C , the hard mask layer  104  is patterned, e.g., by forming and patterning a photoresist layer  106  over the hard mask layer  104 , using any suitable photolithography techniques. As shown, certain areas of the hard mask layer  104  are exposed through the patterned photoresist layer  106 . Next, as shown in  FIG. 4D , an etching process is performed to remove the photoresist layer  106  and portions of the hard mask layer  104  corresponding to the exposed areas shown in  FIG. 4C , thereby forming a patterned hard mask  104 A having an array of openings  105 . 
     The patterning and etching processes of  FIGS. 4C and 4D  may be selected such that openings  105  have any desired size and shape. For example, openings  105  may have a circular or oval shaped cross-section (in a plane parallel to the bottom electrode layer  102 ), thus providing cylindrical or elongated cylindrical openings  105 . As another example, openings  105  may have a rectangular or otherwise elongated cross-section (in a plane parallel to the bottom electrode layer  102 ), thus providing elongated trench-style openings  105 . Openings  105  may have any other suitable shapes and sizes. 
     Next, as shown in  FIG. 4E , an oxidation process is performed to oxidize areas of the bottom electrode layer  102  that are exposed through the openings  105  in patterned hard mask  104 A, thereby forming a number of spaced-apart oxide regions  110 . In some embodiments, each oxide region  110  may have a generally oval, rounded, curved, or otherwise non-orthogonal shape in a cross-section extending perpendicular to the bottom electrode layer  102  (i.e., the cross-section shown in  FIG. 4E ). 
     Next, as shown in  FIG. 4F , the hard mask  104 A is removed and the remaining bottom electrode layer  102  and oxide regions  110  are etched to form an array of spaced-apart bottom electrodes  102 A and corresponding oxide regions  110 . Alternatively, the hard mask  104 A may be removed during the etching of the bottom electrodes  102 A. The bottom electrode layer  102  and oxide regions  110  may be etched in any suitable manner, e.g., by applying and utilizing a patterned mask or photoresist above the stack, or by using the oxide regions  110  themselves as a mask (e.g., using an etch selective to the non-oxidized bottom electrode material). The etch may or may not be patterned to follow the pattern defined by openings  105  (and thus the pattern of oxide regions  110 ). Thus, bottom electrodes  102 A may have any shape and size, which may or may not correspond with the shapes and sizes of the openings  105  and oxide regions  110  prior to the etch process. For example, bottom electrodes  102 A may have a cylindrical or elongated cylindrical shape having a circular or oval shaped perimeter, or a rectangular prism shape have an elongated rectangular perimeter. 
     In addition, the lateral edges of the etch may be selected with respect to the lateral or outer perimeter edge or extent of each oxide region  110 . For example, with reference to  FIG. 4E , the lateral edges of the etch may align with the outer perimeter edge of each oxide region  110 , as indicated by dashed lines E 1 . Alternatively, the lateral edges of the etch may be aligned outside the outer perimeter edge of each oxide region  110 , as indicated by dashed lines E 2 , such that the post-etch bottom electrode  102 A has a region laterally outside the outer perimeter edge of the oxide region  110 . Alternatively, the lateral edges of the etch may be aligned inside the outer perimeter edge of each oxide region  110 , as indicated by dashed lines E 3 , such that the etch extends removes an outer portion of the oxide region  110 . 
     Returning to  FIG. 4F , each bottom electrode  102 A has a pointed tip region  114  adjacent the respective oxide region. The shape of the pointed tip region  114  may be at least partially defined by the oxide region  110 . For example, where the vertical cross-section of the oxide region  110  is oval shaped or otherwise curves downwardly toward the substrate  100 , the curved area toward the lateral perimeter of the oxide region  110  helps define the shape of the pointed tip region  114  of the bottom electrode  102 A. Thus, in the vertical plane, the pointed tip region  114  may define an angle of less than 90 degrees, as shown in  FIG. 4F . 
     The pointed tip region  114  may extend partially or fully around the lateral perimeter of the bottom electrode  102 A (e.g., a circular, oval, or rectangular perimeter). In some embodiments, the lateral perimeter of the bottom electrode  102 A defines a plurality of sides (e.g., a rectangular perimeter defining four sides), and the pointed tip region  114  extends along one, two, three, or more of the perimeter sides. 
     Next, as shown in  FIG. 4G , a spacer layer  116  is deposited over the array of bottom electrodes  102 A/oxide layers  110 . Spacer layer  116  may comprise any electrically insulating material, e.g., a dielectric such as SiO x  (e.g., SiO 2 ), GeS, CuS, TaO x , TiO 2 , Ge 2 Sb 2 Te 5 , GdO, HfO, CuO, Al 2 O 3 , or any other suitable dielectric material. Spacer layer  116  may be formed or deposited in any suitable manner known to one of ordinary skill in the art. 
     As shown in  FIG. 4H , spacer layer  116  may be partially etched, using any suitable etch process known to one of ordinary skill in the art, to define at least one remaining spacer region  118  adjacent each bottom electrode  102 A. The etch process may be selected or controlled such that the spacer region(s)  118  adjacent each bottom electrode  102 A extends fully or partially around the perimeter of the bottom electrode  102 A. Further, spacer layer  116  may be etched to define multiple spacer regions  118  at different locations around the perimeter of each bottom electrode  102 A. The example shown in  FIG. 4H  includes a pair of spacer regions  118 A and  118 B adjacent each bottom electrode  102 A. Further, the etch process may be selected or controlled such that each spacer region  118  extends only partially up the height of the adjacent edge of the bottom electrode  102 A, as shown in  FIG. 4H  and more clearly shown in example  FIG. 4M  (discussed below). 
     Next, as shown in  FIG. 4I , an electrolyte layer  120  and a top electrode layer  122  are formed over the array of bottom electrode  102 A and corresponding oxide regions  110 . Electrolyte layer  120  may comprise any suitable dielectric or memristive type material or materials, for example, SiO x  (e.g., SiO 2 ), GeS, CuS, TaO x , TiO 2 , Ge 2 Sb 2 Te 5 , GdO, HfO, CuO, Al 2 O 3 , or any other suitable material. Top electrode layer  122  may comprise any suitable conductive material or materials, e.g., Ag, Al, Cu, Ta, TaN, Ti, TiN, Al, W or any other suitable material, and may be deposited or formed in any suitable manner. 
     Next, as shown in  FIG. 4J , the stack is patterned, e.g., by forming and patterning a photomask  130  over the top electrode layer  122 , using any suitable photolithography techniques. As shown, certain areas of the top electrode layer  122  are exposed through the patterned photomask  130 . In the illustrated embodiment, the patterned photoresist layer  130  covers only a portion of each underlying bottom electrode  102 A/oxide region  110 . 
     Next, as shown in  FIG. 4K , an etching process is performed to remove exposed portions of the top electrode layer  122  and electrolyte layer  120 . In some embodiments, the etch may be selective with respect to the oxide region  110  such that the oxide region  110  and underlying bottom electrode  102 A are not removed, while exposing surfaces of the oxide region  110  and bottom electrode  102 A. As shown, the remaining portions of the top electrode layer  122  and electrolyte layer  120  define a respective top electrode  122 A and electrolyte region  120 A for each bottom electrode  102 A/oxide region  110  structure. Spacer regions  118  not covered by mask  130  may or may not be etched away, or may be partially etched away, depending on the particular type and extent of etching performed. In the illustrated example, each spacer region  118 A is partially etched away. 
     Next, as shown in  FIG. 4L , any remaining portions of the photomask  130  may be removed, leaving an array  138  of resistive memory cells  140 . Each cell  140  includes a bottom electrode  102 A having an oxide region  110  at an upper surface, a top electrode  122 A, and an electrolyte region  120 A arranged between the bottom electrode  102 A and top electrode  122 A. 
     A close-up of one cell  140  is shown in  FIG. 4M . As shown, the electrolyte region  120 A is arranged between the pointed tip region  114  of the bottom electrode  102 A and the top electrode  122 A, which provides a conductive path for the formation of conductive filament(s) or vacancy chain(s) from the pointed tip region  114  of the bottom electrode  102 A to the top electrode  122 A through the electrolyte region  120 A, said conductive path indicated by the illustrated dashed arrow CP. 
       FIG. 4M  also shows the dielectric spacer regions  118 B formed by the techniques discussed herein, arranged laterally between a sidewall of each bottom electrode  102 A and a respective laterally-outward portion of the electrolyte region  120 A. Thus, each spacer region  118 B may decrease the available or possible area for filament formation between the sidewall of the bottom electrode  102 A and the top electrode via the electrolyte (memory film), which may further restrict filament formation to the bottom electrode tip  114 . As shown, in some embodiment, each spacer region  118 B extends only partially up the height of the bottom electrode sidewall, such that a path from the bottom electrode tip  114  to the top electrode  122 A via the electrolyte  120 A is defined that is free of the spacer region  118 B. In some embodiments, the height of each spacer region  118 B is greater than 50% but less than 100% of the height of the adjacent edge of the bottom electrode  102 A. In particular embodiments, the height of each spacer region  118 B is greater than 75% but less than 100% of the height of the adjacent edge of the respective bottom electrode  102 A. Thus, the top of the remaining spacer region  118 B may be located below the pointed tip  114  of the bottom electrode  102 A. 
     Thus, the structure of cells  140 , including the pointed tip region  114  and dielectric spacer region  118 B, may define a relatively small, or confined, effective filament formation area A FF , or confinement zone. For example, the effective filament formation area A FF , measured in a plane generally perpendicular to the direction of filament propagation, may be less than 1,000 nm 2 . In some embodiments, the effective filament formation area A FF  is less than 100 nm 2 . In particular embodiments, the effective filament formation area A FF  is less than 10 nm 2 , or even less than 1 nm 2 . This reduced confinement zone may provide resistive memory cells (e.g., CBRAM or ReRAM cells) with more predictable and reliable filament formation, as compared with cells having a larger confinement zone. This may provide one or more of the following benefits: lower erase current, narrower distribution of low-resistance state (LRS), higher on/off ratio (HRS/LRS), and improved failure rates. 
     Top electrodes  122 A may be connected in or to any suitable circuitry using any suitable contact scheme. For example,  FIGS. 5A and 5B  illustrate two example schemes for contacting top electrodes  122 A. First, as shown in  FIG. 5A , top contacts  150  may be formed such that they contact an upper portion of each top electrode  122 A, above the respective bottom electrode  102 A/oxide region  110 . Second, as shown in  FIG. 5B , top contacts  150  may be formed such that they contact a lower portion of each top electrode  122 A at a location lateral to the respective bottom electrode  102 A/oxide region  110 . Top contacts  150  may be arranged in any other suitable manner with respect to top electrodes  122 A and other cell components. 
     In addition, it should be understood that each bottom electrode  102 A may be contacted (e.g., for connection to a wordline or bitline) in any suitable or conventional manner. For example, each bottom electrode  102 A may be contacted from above by dropping down a contact that is recessed or offset from the memory films. As another example, each bottom electrode  102 A may be contacted from below by depositing the bottom electrode layer  102  directly on a salicided active silicon region and then making contact to the active region at the end of a line of bits. 
       FIGS. 6A-6O  illustrate another example method for forming an array of resistive memory cells, e.g., an array of conductive bridging memory (CBRAM) and resistive RAM (ReRAM) cells, according to another embodiment. The method of  FIGS. 6A-6O  may be generally similar to the method of  FIGS. 4A-4M , but may include forming a pair of bottom electrode pointed tip region  114  in each cell, with a corresponding pair of mini-spacer regions  118 A and  118 B in each cell. 
     The steps shown in  FIGS. 6A-6G  may be similar or identical to the steps shown in  FIGS. 4A-4G  discussed above, to form a structure including a spacer layer  116  formed over an array of bottom electrodes  102 A/oxide regions  110 . After this point, the method may differ from that of  FIGS. 4A-4G , as discussed below. 
     As shown in  FIG. 6H , the spacer layer  116  may be partially etched, using any suitable etch process known to one of ordinary skill in the art, to define a pair of spaced-apart spacer regions  118 A and  118 B adjacent each bottom electrode  102 A. For example, the pair of spacer regions  118 A and  118 B may be located on opposite sides of each bottom electrode  102 A. The etch process may be selected or controlled such that each spacer region  118  extends only partially up the height of the adjacent edge of the bottom electrode  102 A, as shown in  FIG. 6H  and more clearly shown in example  FIG. 6M  (discussed below). 
     Next, as shown in  FIG. 6I , an electrolyte layer  120  and a top electrode layer  122  are formed over the array of bottom electrode  102 A and corresponding oxide regions  110 . Electrolyte layer  120  may comprise any suitable dielectric or memristive type material or materials, for example, SiO x  (e.g., SiO 2 ), GeS, CuS, TaO x , TiO 2 , Ge 2 Sb 2 Te 5 , GdO, HfO, CuO, Al 2 O 3 , or any other suitable material. Top electrode layer  122  may comprise any suitable conductive material or materials, e.g., Ag, Al, Cu, Ta, TaN, Ti, TiN, Al, W or any other suitable material, and may be deposited or formed in any suitable manner. 
     Next, as shown in  FIG. 6J , the stack is patterned, e.g., by forming and patterning a photomask  130  over the top electrode layer  122 , using any suitable photolithography techniques. As shown, photomask  130  may be patterned in a manner that defines a pair of photomask regions  130 A and  130 B separated by a gap  132  over each cell structure, with a central area of each cell structure being exposed through each gap  132 . Further, the pair of photomask regions  130 A and  130 B over each cell structure is separated from the adjacent pair of photomask regions  130 A and  130 B by a gap  133 . 
     Next, as shown in  FIG. 6K , an etching process is performed through gaps  132  and  133  to remove exposed portions of the top electrode layer  122  and underlying portions of electrolyte layer  120 . In some embodiments, the etch may be selective with respect to the oxide region  110  such that the oxide region  110  and underlying bottom electrode  102 A are not removed, while exposing surfaces of the oxide region  110  and bottom electrode  102 A. As shown, etching through gaps  133  removes portions of top electrode layer  122  and electrolyte layer  120  between adjacent bottom electrodes  102 A to separate adjacent cell structures from each other. In addition, etching through gaps  132  removes portions of top electrode layer  122  and electrolyte layer  120  over a central area of each oxide region  110 /bottom electrode  102 A, thereby defining, over each oxide region  110 /bottom electrode  102 A, a first top electrode  122 A and first electrolyte region  120 A physically separated from a second top electrode  122 B and second electrolyte region  120 B. As discussed below in more detail with respect to  FIG. 6M , the first top electrode  122 A is arranged to interact with a first region of the bottom electrode  102 A (via the first electrolyte region  120 A) to define a first memory element  140 A (indicated in  FIGS. 6L and 6M ), while the second top electrode  122 B is arranged to interact with a second region of the bottom electrode  102 A (via the second electrolyte region  120 B) to define a second memory element  140 B (indicated in  FIGS. 6L and 6M ). Thus, the etch process forms two distinct memory elements  140 A and  140 B for each bottom electrode  102 A. This may therefore double the density of memory cells as compared to a design in which a single memory element is formed per bottom electrode. 
     Next, as shown in  FIG. 6L , any remaining portions of the photomask  130  may be removed, leaving an array  138  of resistive memory cell structures  140 , in which each memory cell structure  140  defines a pair of memory elements  140 A and  140 B, as discussed above. 
     A close-up of one memory cell structure  140  is shown in  FIG. 6M . As shown, the memory cell structure  140  defines a pair of memory elements  140 A and  140 B. The first memory element  140 A is defined by a first top electrode  122 A, a first portion  114 A of the pointed tip region  114  of bottom electrode  102 A, and a first electrolyte region  120 A arranged therebetween. Similarly, the second memory element  140 B is defined by a second top electrode  122 B, a second portion  114 B of the pointed tip region  114  of bottom electrode  102 A, and a second electrolyte region  120 B arranged therebetween. In this embodiment, memory element  140 A is a mirror image of corresponding memory element  140 B. In other embodiments, memory element  140 A may have a different shape or structure than its corresponding memory element  140 B, e.g., by shifting the etch opening  132  (see  FIG. 6K  for reference) from the center of the respective underlying bottom electrode  102 A, or by forming an irregular-shaped etch opening  132 , for example. 
     The first memory element  140 A provides a first conductive path CP 1  for the formation of conductive filament(s) or vacancy chain(s) from the first pointed tip region  114 A of the bottom electrode  102 A to the top electrode  122 A through the electrolyte region  120 A. Similarly, the second memory element  140 B provides a second conductive path CP 2  for the formation of conductive filament(s) or vacancy chain(s) from the second pointed tip region  114 B of the bottom electrode  102 A to the top electrode  122 B through the electrolyte region  120 B. 
       FIG. 6M  also shows the dielectric spacer regions  118 A and  118 B formed by the techniques discussed herein, with dielectric spacer regions  118 A arranged laterally between a sidewall of bottom electrode  102 A and the laterally-outward first electrolyte region  120 A, and dielectric spacer regions  118 A arranged laterally between a sidewall of bottom electrode  102 A and the laterally-outward second electrolyte region  120 B. Thus, each spacer region  118  may decrease the available or possible area for filament formation between the bottom electrode  102 A and the respective top electrode  122 A,  122 B via the respective electrolyte (memory film)  120 A,  120 B, which may further restrict filament formation to the respective bottom electrode tip  114 . As shown, in some embodiment, each spacer region  118 A,  118 B extends only partially up the height of the adjacent bottom electrode sidewall, such that a path from the respective bottom electrode tip  114 A,  114 B to the respective top electrode  122 A,  122 B via the respective electrolyte  120 A,  120 B is defined that is free of the respective spacer region  118 A,  118 B. In some embodiments, the height of each spacer region  118 A,  118 B is greater than 50% but less than 100% of the height of the adjacent edge of the bottom electrode  102 A. In particular embodiments, the height of each spacer region  118 A,  118 B is greater than 75% but less than 100% of the height of the adjacent edge of the bottom electrode  102 A. Thus, the top of each spacer region  118 A,  118 B may be located below the respective pointed tip  114 A,  114 B of the bottom electrode  102 A. 
     Thus, the structure of each memory element  140 A and  140 B, including the respective pointed tip region  114 A or  114 B and corresponding mini-spacer region  118 A or  118 B, may define a relatively small, or confined, effective filament formation area A FF , or confinement zone. For example, the effective filament formation area A FF  for each memory element  140 A/ 140 B, measured in a plane generally perpendicular to the direction of filament propagation, may be less than 1,000 nm 2 . In some embodiments, each effective filament formation area A FF  is less than 100 nm 2 . In particular embodiments, each effective filament formation area A FF  is less than 10 nm 2 , or even less than 1 nm 2 . These reduced confinement zones may provide resistive memory cells (e.g., CBRAM or ReRAM cells) with more predictable and reliable filament formation, as compared with cells having a larger confinement zone. This may provide one or more of the following benefits: lower erase current, narrower distribution of low-resistance state (LRS), higher on/off ratio (HRS/LRS), and improved failure rates. 
     Top electrodes  122 A and  122 B may be connected in or to any suitable circuitry using any suitable contact scheme. For example, top contacts may be formed in contact with top electrodes  122 A and  122 B as shown in  FIGS. 6N and 6O . First, as shown in  FIG. 6N , a dielectric layer  144  may be deposited over the array of memory elements  140 A and  140 B. Then, as shown in  FIG. 6O , top contacts  150 A and  150 B may be formed in dielectric layer  144 , using any suitable techniques. As shown, each top contact  150 A contacts an upper portion of a top electrode  122 A, while each top contact  150 B contacts an upper portion of a top electrode  122 B. Top contacts  150  may be arranged in any other suitable manner with respect to top electrodes  122 A and  122 B and other cell components. 
     In addition, it should be understood that each bottom electrode  102 A may be contacted (e.g., for connection to a wordline or bitline) in any suitable or conventional manner. For example, each bottom electrode  102 A may be contacted from above by dropping down a contact that is recessed or offset from the memory films. As another example, each bottom electrode  102 A may be contacted from below by depositing the bottom electrode layer  102  directly on a salicided active silicon region and then making contact to the active region at the end of a line of bits. 
     Although the disclosed embodiments are described in detail in the present disclosure, it should be understood that various changes, substitutions and alterations can be made to the embodiments without departing from their spirit and scope.