Abstract:
A miniaturized system on a chip that incorporates a positive high voltage charge pump and a negative high voltage charge pump into one pump circuit and shares components. A voltage control apparatus in a semiconductor device may include at least one of the following: First and second input/output units capable of inputting or outputting voltage. A voltage booster that receives and boosts a voltage from one of the first and second input/output unit and outputs the boosted voltage from the other input/output unit. An output selector that receives the boosted voltage from the voltage booster and selects one of the positive or the negative voltage to output. An output controller that receives the boosted voltage from the voltage booster and controls and/or regulates the output voltage. An output unit that outputs the generated output voltage.

Description:
[0001]    The present application claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-2006-0119470 (filed on Nov. 30, 2006), which is hereby incorporated by reference in its entirety. 
       BACKGROUND 
       [0002]    A charge pump may output a positive high-voltage or a negative high-voltage that has a larger magnitude than a voltage supplied from a power supply. For example, a charge pump may be used in a back-bias voltage generator of a semiconductor device (e.g. DRAM or other similar semiconductor device). A charge pump may be used in a voltage generator which generates voltages for writing/erasing data in a cell of an EPROM, an EEPROM, a flash memory element, or other similar devices. A charge pump may be used in a DC-DC converter for components that require a voltage higher than a system voltage. 
         [0003]    Example  FIG. 1  is a circuit diagram illustrating a positive high-voltage charge pump. A positive high voltage charge pump circuit may include a power supply VDD, a diode unit  110 , a capacitor unit  120 , a clock unit  130 , and an output terminal VOUT  140 . Power supply VDD may be used as a power supply for generating a positive high voltage. 
         [0004]    Diode unit  110  may include diode D 11  connected to input power supply VDD in a forward direction. Diodes D 12 , D 13 , D 14  and D 15  may be serially and sequentially connected in a forward direction. 
         [0005]    Capacitor unit  120  may include capacitors C 11 , C 12 , C 13 , and C 14  arranged in parallel. Capacitors C 11 , C 12 , C 13 , and C 14  may each be to the outputs of diodes D 11 , D 12 , D 13 , and D 14 . A first clock signal CLK 1  in clock unit  130  may be connected to capacitors C 11  and C 13 . A second clock signal CLK 2  in clock unit  130  may be connected to capacitors C 12  and C 13 . For example, node N 11  may be connected to the output of diode D 11 , the input of diode D 12 , and one terminal of capacitor C 11 ; the other terminal of capacitor C 11  may be connected to first clock signal CLK 1 . Node N 12  may be connected to the output of diode D 12 , the input of diode D 13 , and one terminal of capacitor C 12 ; the other terminal of capacitor C 12  may be connected to second clock signal CLK 2 . Node N 13  may be connected to the output of diode D 13 , the input of diode D 14 , and one terminal of capacitor C 13 ; the other terminal of capacitor C 13  may be connected to first clock signal CLK 1 . Node N 14  may be connected to the output of diode D 14 , the input of diode D 15 , and one terminal of capacitor C 14 ; the other terminal of capacitor C 14  may be connected to second clock signal CLK 2 . The output terminal VOUT  140  may output a positive high voltage generated by a pump operation. 
         [0006]    Example  FIG. 2  illustrates a timing chart of first clock signal CLK 1  and second clock signal CLK 2 . First clock signal CLK 1  and second clock signal CLK 2  may be out of phase by 180°. 
         [0007]    For purposes of explanation and simplicity, it is assumed that threshold voltage Vth of the diodes D 11 , D 12 , D 13 , D 14 , and D 15  are the same; however one of ordinary skill in the art would appreciate that the threshold voltages may be different. As illustrated in the clock input diagram of example  FIG. 2 , VSS (e.g. a ground level voltage) may be input to one terminal of capacitor C 11  during time period T 1  of CLK 1 . Voltage VDD may be input into diode D 11  and voltage VDD−Vth may be output from diode D 11 ; in other words, the voltage output from diode D 11  may be reduced by threshold voltage Vth. Accordingly, the voltage at node N 11  may be VDD−Vth. The capacitance charged in capacitor C 11  during time period T 1  may be Q 1 =C 11 ×{(VDD−Vth)−VSS}. 
         [0008]    As illustrated in the clock input diagram of example  FIG. 2 , when CLK 1  is in time period T 2 , a voltage of VDD is input into the terminal of capacitor C 11  that is connected to CLK 1 . The capacitance of capacitor C 11  may remain constant. Accordingly, node N 11  will become 2VDD−Vth during time period T 2 . During time period T 2 , VSS (e.g. ground level voltage) may be input into the terminal of capacitor C 12  that is connected to CLK 2 . Diode D 12  may output to node N 12  a voltage of node N 11  minus Vth (i.e. 2VDD−2Vth). Accordingly, the capacitance charged in capacitor C 12  may be Q 2 =C 12 ×{(2VDD−2Vth)−VSS}. 
         [0009]    As illustrated in the clock input diagram of example  FIG. 2 , during time period T 3 , the voltage of VDD of CLK 2  is input into capacitor C 12 . During time period T 3 , since the capacitance charged in capacitor C 12  may be constant, node N 12  may be come VDD (voltage level of CLK 2  terminal of capacitor C 12 ) plus 2VDD−2Vth (voltage charge of capacitor C 12 ), which is 3VDD−2Vth. During time period T 3 , VSS (i.e. ground level voltage) from CLK 1  is input into capacitor C 13 . Accordingly, diode D 13  outputs the voltage of 3VDD−3Vth. Accordingly, the capacitance charged in capacitor C 13  may be Q 3 =C 13 ×{(3VDD−3Vth)−VSS}. 
         [0010]    When the clocks CLK 1 , CLK 2  are continuously input, output terminal VOUT  140  may output a voltage of 5VDD−5Vth. Therefore, the positive high voltage charge pump can generate a voltage higher than input voltage VDD. Example  FIG. 3  is a diagram of the positive high voltage charge pump simulation. 
         [0011]    Example  FIG. 4  is a circuit diagram illustrating a negative high voltage charge pump. A negative high voltage charge pump circuit may includes a power supply VSS, a diode unit  210 , a capacitor unit  220 , a clock unit  230 , and an output terminal VOUT  240 . Power supply VSS may used as the power supply to generate a negative high voltage. 
         [0012]    Diode unit  210  may include a diode D 21  connected to an input power supply VSS in a reverse direction. Diodes D 22 , D 23 , D 24  and D 25  may be serially and sequentially connected in a reverse direction. Capacitor unit  220  may include capacitors C 21 , C 22 , C 23 , and C 24  in parallel with each other. Each of capacitors C 21 , C 22 , C 23 , and C 24  may be connected to the inputs of diodes D 21 , D 22 , D 23 , and D 24  respectively. First clock signal CLK 1  in clock unit  230  may be connected to capacitor C 21  and capacitor C 23 . Second clock signal CLK 2  in clock unit  230  may be connected to capacitors C 22  and C 24 . For example, capacitor C 21  may have one terminal connected to node N 21  and another terminal connected to CLK 1 . Capacitor C 22  may have one terminal connected to node N 22  and another terminal connected to CLK 2 . Capacitor C 23  may have one terminal connected to N 23  and another terminal connected to CLK 1 . Capacitor C 24  may have one terminal connected to node N 24  and another terminal connected to CLK 2 . An example timing chart of first clock signal CLK 1  and second clock signal CLK 2  are illustrated in example  FIG. 2 . First clock signal CLK 1  and second clock signal CLK 2  may have a phase difference of 180°. 
         [0013]    Output terminal VOUT  240  may output a negative high voltage generated by a pump operation. The operation of a negative high voltage charge pump is generally opposite to the operation of a positive high voltage charge pump. For example, the connecting direction of the diodes and the input power supply are opposite. Example  FIG. 5  is an example diagram of a negative high voltage charge pump simulation. 
         [0014]    If a device requires both a positive charge pump and a negative charge pump, the device should include a charge pump circuit for each function. For example, a device may require a circuit that includes the positive charge pump circuit illustrate in example  FIG. 1  and the negative charge pump circuit illustrated in example  FIG. 2 . Having two different charge pump circuits may cause complications when miniaturizing a system on chip. Separate charge pumps circuits may each require a regulator for regulating a desired voltage level, which may cause complications when miniaturizing a system on a chip. 
         [0015]    A positive high voltage charge pump and a negative high voltage charge pump may be used as individual devices. Production flexibility may be limited as each device is specific to either positive charge pumping or negative charge pumping. Development costs may be unnecessarily spent, as each type of charge pump needs to be independently designed and verified. 
       SUMMARY 
       [0016]    Embodiments relate to a miniaturized system on a chip that incorporates a positive high voltage charge pump and a negative high voltage charge pump into one pump circuit and shares components. Embodiment relates to a voltage control apparatus in a semiconductor device which includes at least one of the following: First and second input/output units capable of inputting or outputting voltage. A voltage booster that receives and boosts a voltage from one of the first and second input/output unit and outputs the boosted voltage from the other input/output unit. An output selector that receives the boosted voltage from the voltage booster and selects one of the positive or the negative voltage to output. An output controller that receives the boosted voltage from the voltage booster and controls and/or regulates the output voltage. An output unit that outputs the generated output voltage. 
     
    
     
       DRAWINGS 
         [0017]    Example  FIG. 1  illustrates a circuit diagram of a positive high voltage charge pump. 
           [0018]    Example  FIG. 2  illustrates a clock input diagram. 
           [0019]    Example  FIG. 3  illustrates a positive high voltage charge pump simulation. 
           [0020]    Example  FIG. 4  illustrates a circuit diagram of a negative high voltage charge pump. 
           [0021]    Example  FIG. 5  illustrates a negative high voltage charge pump simulation. 
           [0022]    Example  FIG. 6A  illustrates a block diagram illustrating a voltage control apparatus, in accordance with embodiments. 
           [0023]    Example  FIG. 6B  illustrates a circuit diagram illustrating a voltage control apparatus, in accordance with embodiments. 
           [0024]    Example  FIG. 7  illustrates a circuit diagram of a pump switch, in accordance with embodiments. 
           [0025]    Example  FIG. 8  illustrates a result diagram of a positive high voltage simulation by a charge pump, in accordance with embodiments. 
           [0026]    Example  FIG. 9  illustrates a result diagram of a negative high voltage simulation by a charge pump, in accordance with embodiments. 
           [0027]    Example  FIG. 10  illustrates a circuit diagram of a regulator, in accordance with embodiments. 
           [0028]    Example  FIG. 11  illustrates a result diagram of a positive high voltage simulation by a charge pump and a regulator, in accordance with embodiments. 
           [0029]    Example  FIG. 12  illustrates a result diagram of a negative high voltage simulation by a charge pump and a regulator, in accordance with embodiments. 
       
    
    
     DESCRIPTION 
       [0030]    Example  FIG. 6A  illustrates a voltage control apparatus of a semiconductor device, according to embodiments. A first input/output unit  12  may receive a power supply VDD and may output a negative high voltage. A second input/output unit  11  may receive a power supply VSS and may output a positive high voltage. Voltage booster  20  may be electrically connected to first input/output unit  11  and second input/output unit  12 . Voltage booster  20  may receive a voltage input from one of first second input/output unit  11  and second input/output unit  12 . Voltage booster  20  may boost the input voltage and output the boosted voltage. 
         [0031]    Output selector  30  may receive a boosted voltage from voltage booster  20 . Output selector  30  may select one of a positive voltage or a negative voltage to output. Output controller  40  may receive a boosted voltage from voltage booster  20  and control and/or regulate the output voltage. Output unit  50  may output a generated output voltage. 
         [0032]    Example  FIG. 6B  illustrates a circuit of a voltage control apparatus of a semiconductor device, in accordance with embodiments. Input/output terminal VEE  320  in  FIG. 6B  may be represented by first input/output unit  12  in  FIG. 6A . Input/output terminal VPP  310  in  FIG. 6B  may be represented by second input/output unit  11  in  FIG. 6A . VOUT  330  in  FIG. 6B  may be represented by output unit  50  in  FIG. 6A . Diode unit  410 , clock unit  430 , capacitor unit  420  in  FIG. 6B  may be represented by voltage booster  20  in  FIG. 6A . Diode unit  410  may include a plurality of diodes D 31 , D 32 , D 33 , D 34 , and D 35 . Capacitor unit may include a plurality of capacitors C 31 , C 32 , C 33 , and C 34 . One of ordinary skill in the art would appreciate that any number of capacitors or diodes may be used in a capacitor unit or a diode unit. 
         [0033]    Pump switch  440  in  FIG. 6B  may be represented by output selector  30  in  FIG. 6A . Pump switch  440  may output a negative high voltage as VOUT  330  in a negative charge pump operation, in accordance with embodiments. Pump switch  440  may output a positive high voltage as VOUT  330  in a positive charge pump operation, in accordance with embodiments. 
         [0034]    VREF  340  (e.g. a reference voltage input unit) in  FIG. 6B  may be represented by output controller  40  in  FIG. 6A . A reference voltage may be input into VREF  340 . Regulator  450  and VOUT  330  may output the voltage input from input/output terminal  310  or input/output terminal  320 . 
         [0035]    Charge pump unit  500  in  FIG. 6B  may be represented by first input/output unit  11 , second input/output unit  12 , voltage booster  20 , and output selector  30  of  FIG. 6A . Regulator unit  510  of  FIG. 6B  may be represented by output controller  40  of  FIG. 6A . 
         [0036]    Charge pump unit  500  may include input/output terminal VEE  320 . VEE  320  may receive a voltage VDD during a positive charge pumping operation. VEE  320  may output a negative high voltage during a negative charge pumping operation. Input/output terminal VPP  310  may output a positive high voltage during positive charge pumping operation. Input/output terminal VPP  310  may receive a voltage VSS during a negative charge pumping operation. Charge pump unit  500  may include diode unit  410 , capacitor unit  420 , clock unit  430 , pump switch  440 , and output terminal VOUT  330 , in accordance with embodiments. Power supply VDD may be used as a power supply to generate a positive high voltage during positive charge pumping operation. 
         [0037]    Diode unit  410  may be used as a negative high voltage charge pump by being connected in the reverse direction as the direction used in a positive high voltage charge pump. For example, in embodiments, positive charge pumping may pump a positive voltage starting at VEE  320  and ending at VPP  310 , while negative charge pumping may pump a negative voltage starting at VPP  310  and ending at VEE  320 . Accordingly, in embodiments, diode unit  410  may be used for both a positive charge pump and a negative charge pump. In embodiments, using diode unit  410  in both a positive charge pump and a negative charge pump may be advantageous as it may reduce the number of components (and reduce manufacturing steps in making components), which may minimize costs. 
         [0038]    Capacitor unit  420  may be sequentially connected to each line between diodes of diode unit  410 . For example, capacitor C 31  may be connected to the input of diode D 31  and the output of diode D 32 . Capacitor C 32  may be connected to the input of diode D 32  and the output of capacitor D 33 . Capacitor D 33  may be connected to the input of diode D 33  and the output of diode D 34 . Capacitor C 34  may be connected to the input of diode D 34  and the output of capacitor D 35 . 
         [0039]    First clock signal CLK 1  and second clock signal CLK 2  in clock unit  430  may be are alternatively connected to capacitors of capacitor unit  420 . For example CLK 1  may be connected to capacitor C 32  and capacitor C 34 , while CLK 2  may be connected to capacitor C 31  and capacitor C 33 . A timing diagram for first clock signal CLK 1  and second clock signal CLK 2  are illustrated in example  FIG. 2 , according to embodiments. As illustrated in example  FIG. 2 , CLK 1  and CLK 2  have a phase difference of 180°. 
         [0040]    Pump switch  440  may receive a voltage from both input/output terminal VPP  310  and input/output terminal VEE  320 . Pump switch  440  may select which one of VPP  310  or VEE  320  to output to VOUT  330 , depending on the operation mode of the charge pump. For example, if the charge pump is operating as a positive charge pump, VOUT  330  will be connected to VPP  310  through pump switch  440 , while VEE will be disconnected from VOUT  330 . If the charge pump is operating as a negative charge pump, then VOUT  330  will be connected to VEE  320 , while VPP will be disconnected from VOUT  330 . Example  FIG. 7  illustrates an example circuit structure of pump switch  440 , in accordance with embodiments. 
         [0041]    Regulator unit  510  may include input terminal VREF  340 , which may receive a reference voltage signal. Regulator unit  510  may be coupled to VEE  320  and VPP  310 . Regulator  510  may be connected to VOUT  330 . 
         [0042]    For purposes of explanation and simplicity, it may be assumed that a threshold voltage Vth of diodes D 31 , D 32 , D 33 , D 34 , and D 35  are the same. However, one of ordinary skill in the art would appreciate that diodes D 31 , D 32 , D 33 , D 34 , and D 35  may have different threshold voltages Vth. 
         [0043]    Input voltage VDD may applied to VEE  320  in a positive charge pump operation. As illustrated in clock input diagram of example  FIG. 2 , VSS (i.e. a ground voltage level) may be input into one terminal of capacitor C 11  from CLK 1  during time period T 1 . During time period T 1 , diode D 35  may output a voltage of VDD−Vth (VDD in input into diode D 35  and dropped by threshold voltage Vth of diode D 35 ). Capacitor C 34  may be charged to a value of Q 1 =C 34 ×{(VDD−Vth)−VSS} from node N 34 . 
         [0044]    During time period T 2 , CLK 1  changes to input voltage VDD. Accordingly, the voltage at node N 34  becomes 2VDD−Vth, which is the voltage level across capacitor C 34  (that was charged in time period T 1 ) plus the voltage VDD at the bottom of capacitor C 34 . During time period T 2 , the bottom of capacitor C 33  is VSS (i.e. a ground voltage level) and the voltage 2VDD−2Vth (i.e. the output of diode D 34 , which is reduce by threshold voltage Vth) is input to the top of capacitor  33 . During time period T 2 , capacitor C 33  is charged to Q 2 =C 33 ×{(2VDD−2Vth)−VSS}. 
         [0045]    During time period T 3 , VDD from CLK 2  is input to the bottom of capacitor C 33 . Accordingly, the voltage at node N 33  becomes 3VDD−2Vth, which is input into diode D 33 . The output of diode D 33  is 3VDD−3Vth at node N 32 . Since during time period T 3 , the bottom of capacitor C 32  is VSS (i.e. ground) and the top of capacitor is 3VDD−3Vth, capacitor C 32  is charged to Q 3 =C 32 ×{(3VDD−3Vth)−VSS}. 
         [0046]    This operation continues through diode D 32  and diode D 31 , ultimately resulting in the output of diode D 31  having a voltage 5VDD−5Vth. Accordingly, a charge pump can effectively increase a voltage level using clock signals, diodes, and capacitor. One of ordinary skill would appreciate than any number of capacitor and diodes may be used, depending on the application. 
         [0047]    After a positive charge pumping operation, the positive high voltage VPP  310  and input voltage VEE  320  (i.e. VDD) are input into pump switch  440 . Example  FIG. 7  illustrates an example circuit for pump switch  440 . Positive high voltage VPP  310  may be applied to gates of PMOS transistor PMO  611  and NMOS transistor NM 2   612 , which would turn NMOS transistor NM 2   612  on and turn PMOS transistor PMO  611  off. VSS may be applied to node N 41  to turn off NMOS transistor NMO  620 , thus preventing VEE  320  from being connected to VOUT  330 . 
         [0048]    VEE  320  (i.e. the power supply voltage) may turn on NMOS transistor NM 1   617 , which will cause VSS to be applied to node N 44 , thus causing NMOS transistor NM 6   618  and NM 5   619  to be turned on. With NMOS transistor NM 5   619  turned on, positive high voltage from VPP  310  will be applied to VOUT  330 . 
         [0049]    Example  FIG. 8  illustrates an example result diagram of positive high voltage pumping simulation, in accordance with embodiments. 
         [0050]    As illustrated in example  FIG. 6B , VOUT  330  (e.g. applying a positive high voltage in a positive pumping operation) may be applied to regulator  450 , in accordance with embodiments. A reference voltage (e.g. 1.0V) may be applied to VREF  340  of regulator  450 . VPP  310  and VEE  320  may be applied to regulator  450 . 
         [0051]    As illustrated in example  FIG. 10 , VREF  340  may be applied to operational amplifier AMP  71 . Accordingly, the same voltage as VREF  340  may be generated at node N 51 . By resistor R 11  and resistor R 12  having the same resistance value, a voltage of 2VREF (i.e. 2 times VREF) may be generated at the node N 52 . A voltage of node N 51  may be applied to operational amplifier AMP 72 . 
         [0052]    During a positive charge pump operation, positive high voltage VPP  310  may be applied to inverter INV 71  (i.e. VSS may be applied to node N 58 , which is applied to the gate of NMOS transistor NM 71 ), thus turning transistor NM 71  off. VEE  320  (i.e. VDD during positive charge pumping operation) may be applied to the gate of the NMOS transistor NM 72 , thus turning transistor NM 72  on. By transistor NM 72  being turned on, the voltage of node N 55  may be applied to node N 56 , which is applied to an input of operational amplifier AMP 72 . 
         [0053]    A positive high voltage applied to VOUT  330  may be divided between resistors R 1 , R 12 , R 13 , R 14 , R 15 , and R 16 . Resisters R 15 , R 14 , R 13 , R 12 , and R 11  may have the same resistance value R, in accordance with embodiments. The resistance value of R 16  may be set in accordance with a desired output voltage, according to embodiments. 
         [0054]    For example, R 16  may be set to 8R to generating a positive high voltage 9V (e.g. when VREF is 1V). When the positive high voltage exceeds 9V, the voltage at node N 55  rises above 1.0V by division of resistances. If node N 55  rises above 1.0V, there will be a voltage difference between the node N 51  input and node N 56  inputs to operational amplifier AMP 72 , causing the voltage at node N 57  (i.e. output of operational amplifier AMP 72 ) to be lowered. The lowering of the voltage at node N 57  will turn on PMOS transistor PM 71 , which will cause voltage discharge, this lowering the voltage level of VOUT  330 . 
         [0055]    During positive high voltage operation, when voltage of VOUT  330  drop below 9V, the voltage value at node N 55  drops below 1.0V, causing the voltage at node N 57  to rise. When the voltage of node N 57  rises, PMOS transistor PM 71  is turned off, which raises the voltage level of VOUT  330  to be regulated at a target output voltage. Accordingly, using at least one feedback mechanism, regulator  510  can regulate the output of VOUT  330 , according to embodiments. Example  FIG. 11  is an example result diagram of a positive high voltage simulation by a charge pump and a regulator, according to embodiments. 
         [0056]    During a negative charge pumping operation, VSS is applied to the VPP  310 , in accordance with embodiments. A negative high voltage charge pumping operation is generally opposite from a positive high voltage charge pumping operation. A negative high charge pumped voltage VEE  320  and pre-pumped negative voltage VPP  310  (e.g. VSS) are input into pump switch  440 . As illustrated in example  FIG. 7 , VPP  310  (e.g. VSS) is applied to the gates of PMOS transistor PMO  611  and the NMOS transistor NM 2   612 , thus turning on PMOS transistor PMO  611  and turning off NMOS transistor NM 2   612 . Accordingly, VDD is applied to node N 41  to turn on the NMOS transistor NM 0   620  and output negative pumped high voltage VEE  320  to VOUT  330 . 
         [0057]    During a negative charge pumping operation, negative pumped high voltage VEE  320  turns off NMOS transistor NM 1   617 , in accordance with embodiments. VPP  310  (e.g. VSS) turns on PMOS transistor PM 3   616 , allowing VDD to be applied to node N 44 . By VDD being applied to node N 44 , NMOS transistor NM 6   618  is turned on to apply negative pumped high voltage VEE  320  to the node N 42 , which causes NMOS transistor NM 5   619  to be turned off, thus preventing VPP  310  from connecting to VOUT  330 . Example  FIG. 9  is an example result illustrating a negative pumped high voltage simulation, according to embodiments. 
         [0058]    In a negative charge pumping operation, VOUT  330  may output a negative pumped high voltage and may be applied to regulator  450 . An example reference voltage of 1.0V may be applied to VREF  340  in regulator  450 . As illustrated in example  FIG. 10 , VREF  340  may be applied to operational amplifier AMP  71 , resulting in the same voltage level as VREF  340  being generated at node N 51  by resistors R 11  and R 12  have the same resistance value. A voltage of 2VREF may be generated at node N 52 . The voltage of node N 51  may be applied to operational amplifier AMP 72 . 
         [0059]    During a negative charge pumping operation, VPP  310  (e.g. VSS) may be applied to inverter INV 71 , to cause NMOS transistor NM 71  to be turned on through node N 58 . The voltage of node N 53  may be applied to node N 56 , which is applied to operational amplifier AMP 72 . VEE  320 , which may be the negative pumped high voltage, may be applied to the gate of NMOS transistor NM 72  to turn it off. A negative pumped high voltage may be applied to VOUT  330  and may be divided between resistors R 11 , R 12 , R 13 , R 14 , R 15 , and R 16 . The resistance values of R 15 , R 14 , R 13 , R 12 , and R 1  may be the same (e.g. a value R). The resistance value of resistor R 16  may be set in accordance with a desired output voltage. 
         [0060]    For example, R 16  may set to 8R for generating the negative high voltage 9V. When the negative high voltage becomes less than −9V, the voltage at node N 53  may rise above 1.0V through resistance division. The voltage at node N 53  may be applied to operational amplifier AMP 72  through the NMOS transistor NM 71  (which is turned on in a negative charge pumping operation), thus lowering the voltage at node N 57 . Due to a voltage difference between node N 51  and node N 56 , the voltage at node N 57  changes, thus turning on PMOS transistor PM 71  to discharge VDD, which may boost VOUT  330  to 9V in a regulated fashion. 
         [0061]    During a negative charge pumping operation, if the voltage of VOUT  330  becomes greater than −9V, the voltage value at node N 53  applied to operational amplifier AMP 72  may become less than 1.0V. The lowering of voltage at node N 53  may cause a voltage difference between the inputs to operational amplifier AMP 72 , which may cause the voltage at node N 57  to rise. A rise of voltage at node N 57  may turn off PMOS transistor PM 71  and consequently drop the voltage at VOUT  330  to −9V. Through feedback, a regulator may cause VOUT to be consistently output at −9V (or another set target output voltage). Example  FIG. 12  illustrates a result diagram of a negative high voltage simulation by a charge pump and regulator, according to embodiments. 
         [0062]    A voltage control apparatus that implements both a positive high voltage charge pump and a negative high voltage charge pump may assist in scaling down a system on a chip, in accordance with embodiments. In embodiments, a single regulator may be used for both a positive high voltage charge pump and a negative high voltage charge pump, thus assisting in scaling down a system on a chip. Scaling down of a system on a chip, may reduce manufacturing costs, reduce development costs, improve productivity, and have other benefits, in accordance with embodiments. 
         [0063]    It will be obvious and apparent to those skilled in the art that various modifications and variations can be made in the embodiments disclosed. Thus, it is intended that the disclosed embodiments cover the obvious and apparent modifications and variations, provided that they are within the scope of the appended claims and their equivalents.