Abstract:
An object of the present invention is to provide an interconnect structure in which the current capacity of an interconnect pattern involving a large amount of current is increased without preventing miniaturization of signal lines and increasing film thickness. To accomplish this object, the present invention is configured as an interconnect structure including a resin layer; and interconnects formed on the resin layer, wherein the resin layer has a plurality of parallel grooves in an area in which the interconnects are formed, and the interconnects are formed of a plating film created on a resin layer front surface in the area, in which the interconnects are formed, and on inner wall surfaces of the plurality of grooves.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to an interconnect structure, printed circuit board, a semiconductor device, and a manufacturing method for the interconnect structure. 
         [0003]    2. Description of the Related Art 
         [0004]    An interconnect pattern formed on a semiconductor device or a printed circuit board needs to have a sectional area corresponding to the amount of current flowing through interconnects in order to prevent excessive heating of the interconnects during current conduction. 
         [0005]    For example, in a power device or a control device, an interconnect pattern for a power supply system involving a large amount of current needs to have a large sectional area. However, an increase in interconnect width is limited. 
         [0006]    A method for further increasing current capacity without increasing the interconnect width is to increase the thickness of the interconnects or to form a pattern by using a plurality of conductive layers in a multilayer board in parallel. 
         [0007]    However, the method of increasing the thickness of the interconnects has the disadvantages of needing much time to plate the interconnects and precluding miniaturization based on a reduction in interconnect intervals between signal lines through which a large current need not flow. 
         [0008]    The method of using a plurality of conductive layers in a multilayer circuit board in parallel is limited in an increase in the number of conductive layers. 
         [0009]    Japanese Patent Publication No. H10-32201 describes photolithography masks used to form interconnect patterns and including a mask in which all interconnect patterns are drawn as mask patterns and a mask in which only interconnect patterns for large current are drawn as mask patterns. These masks are used to form a thick interconnect pattern for a large amount of current, while forming a thin interconnect pattern for a small amount of current, thus allowing miniaturization. 
         [0010]    In Japanese Patent Publication No. 2007-165642, a groove is formed in an insulating resin on an interconnect layer and filled with conductive paste, and surfaces that are not in contact with the conductive paste are plated with copper. This increases the current capacity per unit width of pattern in one layer. 
       SUMMARY OF THE INVENTION 
     Problems to be Solved by the Invention 
       [0011]    An object of the present invention is to provide an interconnect structure in which the current capacity of an interconnect pattern involving a large amount of current is increased without preventing miniaturization of signal lines and increasing film thickness. 
         [0012]    To accomplish this object, an aspect of the present invention is configured as follows. 
         [0013]    (1) An interconnect structure including: 
         [0014]    a resin layer; and 
         [0015]    interconnects formed on the resin layer, wherein 
         [0016]    the resin layer has a plurality of parallel grooves in an area in which the interconnects are formed, and 
         [0017]    the interconnects are formed of a plating film created on a resin layer front surface in the area, in which the interconnects are formed, and on inner wall surfaces of the plurality of grooves. 
         [0018]    (2) A printed circuit board including the interconnect structure set forth in (1). 
         [0019]    (3) A semiconductor device including the interconnect structure set forth in (1). 
         [0020]    (4) The semiconductor device according to (3), wherein the interconnects constituting the interconnect structure are in direct contact with a front surface of a semiconductor chip. 
         [0021]    (5) A manufacturing method for an interconnect structure, the method including: 
         [0022]    a step of forming a plurality of parallel grooves in a front surface of a resin layer in an area in which interconnects are formed; and 
         [0023]    a step of forming a plating film on a resin layer front surface in an area in which the interconnects are formed and on inner wall surfaces of the plurality of grooves. 
         [0024]    The interconnect structure in the present invention enables a partial increase in current capacity of the interconnects without an increase in plating thickness of the interconnects. As a result, plating time needed to obtain the desired current capacity can be reduced, enhancing productivity. 
         [0025]    Compared to a case where a plating thickness is increased, a reduced plating thickness of the present invention precludes hindrance to the miniaturization of signal lines. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0026]      FIGS. 1A and 1B  are diagrams depicting an interconnect structure according to Embodiment 1 of the present invention,  FIG. 1A  is a sectional perspective view of the interconnect structure, and  FIG. 1B  is a sectional view of the interconnect structure prior to plating; 
           [0027]      FIGS. 2A and 2B  are diagrams comparing the interconnect structure in Embodiment 1 of the present invention with a conventional interconnect structure,  FIG. 2A  depicts an interconnect structure in Embodiment 1, and  FIG. 2B  depicts a conventional interconnect structure; 
           [0028]      FIGS. 3A to 3G  are diagrams each showing a part of a manufacturing process for an interconnect structure according to Embodiment 1 of the present invention, including steps until after grooves have been formed in a resin layer; 
           [0029]      FIGS. 3H to 3J  are diagrams each showing a part of the manufacturing process for an interconnect structure according to Embodiment 1 of the present invention, including steps in which openings and grooves formed in the resin layer are plated to form a plating film;  FIGS. 3K to 3N  are diagrams each showing a part of the manufacturing process for an interconnect structure according to Embodiment 1 of the present invention, including steps until after a solder resist film has been formed after forming vias and interconnects in the resin layer on interconnects; 
           [0030]      FIGS. 4A and 4B  are diagrams depicting an interconnect structure according to Embodiment 2 of the present invention,  FIG. 4A  is a sectional view of the interconnect structure, and  FIG. 4B  illustrates the interconnect structure prior to plating; and 
           [0031]      FIGS. 5A and 5B  are diagrams depicting an interconnect structure according to Embodiment 3 of the present invention,  FIG. 5A  is a sectional view of the interconnect structure, and  FIG. 5B  illustrates the interconnect structure prior to plating. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0032]    Embodiments of the present invention will be described below. The embodiments will be described below based on the drawings. However, the drawings are provided for description, and the present invention is not limited to the drawings. 
         [0033]      FIG. 1A  depicts a basic example of an interconnect structure in the present invention. 
         [0034]    The interconnect structure has a resin layer  1  and a plating film  3  constituting interconnects formed on the resin layer  1 . The resin layer  1  is formed on the core member  10  including conductive films  10   b  and  10   c  laminated on the respective opposite surfaces of a core plate  10   a.    
         [0035]      FIG. 1B  is a diagram depicting a section of the resin layer  1  on which the plating film  3  is not yet formed. The resin layer  1  has a plurality of parallel grooves  2  in an area in which the plating film  3  is formed. 
         [0036]    The plating film (interconnects)  3  is formed on inner wall surfaces  1   b  of the grooves  2  and on resin layer front surfaces  1   a  in the area where the interconnects are formed. 
         [0037]    Such an interconnect structure is obtained by forming the plurality of parallel grooves  2  in the resin layer front surface  1   a  in an area S of the resin layer  1  on the core member  10  where the interconnects are formed and forming the plating film  3  on the inner wall surfaces  1   b  of the grooves  2  and the resin layer front surfaces  1   a  as depicted in  FIG. 1B . 
         [0038]    In  FIG. 1B , the inner wall surfaces of the grooves refer to side surfaces and bottom surfaces (conductive film  10   b ) of the grooves. 
         [0039]    Wiring formed of the plating film  3  as depicted in  FIG. 1A  is hereinafter sometimes referred to as groove-shaped interconnects. 
         [0040]      FIGS. 2A and 2B  illustrate a comparison of an interconnect structure according to an embodiment of the present invention (see  FIG. 2A ) with an interconnect structure that is not the embodiment of the present invention (see  FIG. 2B ). 
         [0041]    In the interconnect structure depicted in  FIG. 2A , the plating film  3  is formed on side walls of the grooves  2  as well. 
         [0042]    In the conventional interconnect structure depicted in  FIG. 2B , the grooves  2  are not formed in the resin layer  1 , and the plating film  3  is formed only on the resin layer front surfaces  1   a  of the resin layer  1 . 
         [0043]    Wiring resistance is expressed by Equation (1). 
         [0000]    
       
         
           
             
               
                 
                   R 
                   = 
                   
                     p 
                     × 
                     
                       L 
                       A 
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
         [0000]    (R: resistance, ρ: resistivity of copper, L: interconnect length, A: interconnect sectional area) 
         [0044]    A comparison of the interconnect structure depicted in  FIG. 2A  with the interconnect structure depicted in  FIG. 2B  indicates that, compared to the interconnect structure depicted in  FIG. 2B , the interconnect structure depicted in  FIG. 2A  includes conductor portions formed of the plating film on the side surfaces of the grooves, with these conductor portions being enlarged with those of the interconnect structure depicted in  FIG. 2B . Therefore, the interconnect structure depicted in  FIG. 2A  has a larger interconnect sectional area A and a lower interconnect resistance R in Equation (1) than the interconnect structure depicted in  FIG. 2B . 
         [0045]    Current that can be passed through the interconnects are limited to the degree that the current is prevented from excessively elevating temperature. However, the interconnect structure in the embodiment of the present invention depicted in  FIG. 2A  has the lower interconnect resistance R, and thus, a reduced amount of heat is generated by the interconnects during current conduction. Consequently, a larger current can be passed through the interconnect structure. 
         [0046]    Now, an embodiment of the interconnect structure in the present invention will be described. 
       Embodiment 1 
       [0047]    The present embodiment relates to a printed circuit board having the interconnect structure according to the present invention. 
         [0048]    Steps for producing a printed circuit board having the interconnect structure depicted in  FIGS. 1A and 1B  will be described below based on  FIGS. 3A to 3N . 
         [0049]    (Step  1 ) See  FIG. 3A . 
         [0050]    The core member  10  is prepared which includes the conductive films  10   b  and  10   c  laminated on the respective opposite surfaces of the core plate  10   a.    
         [0051]    (Step  2 ) See  FIGS. 3B and 3C . 
         [0052]    An unwanted part of the conductive film  10   b  on one side of the core member  10  is melted and removed with a chemical to form conductive patterns  4   a,    4   b,  and  4   c  needed as interconnects. 
         [0053]      FIG. 3C  is a top view of the core member  10  depicted in  FIG. 3B . 
         [0054]    (Step  3 ) See  FIG. 3D . 
         [0055]    Resin is accumulated on the core member  10  with the conductive patterns  4   a,    4   b,  and  4   c  formed thereon, to form a resin layer  1 . 
         [0056]    (Step  4 ) See  FIGS. 3E to 3G . 
         [0057]    On the resin layer  1 , grooving is performed in which the plurality of grooves  2  for large-current interconnects is formed and drilling is further performed in which via openings  5  for signal lines are formed. In the present embodiment, four grooves  2  are formed. 
         [0058]    The drilling can be performed using a CO 2  laser or a THG laser. The grooving is preferably performed by excimer laser ablation. 
         [0059]    When the grooves  2  and the via openings  5  are formed by laser processing, the conductive patterns  4   a,    4   b,  and  4   c  are provided to control the depths of the grooves  2  and the via openings  5 . That is, if laser light has energy with a value equal to or smaller than a predetermined value, a conductive film forming the conductive patterns  4   a,    4   b,  and  4   c  acts as a barrier to stop formation of the grooves  2  and the via openings  5  directly before the depth of the conductive patterns  4   a,    4   b,  and  4   c  (upper side of the figures). 
         [0060]      FIG. 3F  is a top view of a laminated body including the core member  10  and the resin layer  1  depicted in  FIG. 3E .  FIG. 3G  is a sectional perspective view of the laminated body depicted in  FIG. 3F  and is taken along line A-A′in  FIG. 3F . 
         [0061]      FIG. 3G  illustrates that the conductive pattern  4   c  at the bottom surfaces of the grooves  2  formed in the resin layer  1  is exposed. 
         [0062]    (Step  5 ) See  FIGS. 3H to 3J . 
         [0063]    Seeding is performed on inner wall surfaces of the grooves  2 , peripheral portions of the grooves  2 , the via openings  5 , and peripheral portions thereof in the laminated body depicted in  FIG. 3E . Then, conductive films are formed by electroless plating, and vias  7  and interconnects  6  (interconnects  6   a,    6   b,    6   c,  and  6   d ) are formed by electroplating. 
         [0064]    The interconnects  6   a,    6   b,  and  6   c  are utilized as small-current conduction interconnects such as signal lines. 
         [0065]    The interconnect  6   d  is a groove-shaped interconnect and is utilized as a large-current conduction interconnect. 
         [0066]      FIG. 3I  is a top view of the laminated body depicted in  FIG. 3H . 
         [0067]      FIG. 3J  is a sectional perspective view of the laminated body depicted in  FIG. 31  and is taken along line A-A′ in  FIG. 3I . 
         [0068]    (Step  6 ) See  FIG. 3K . 
         [0069]    A resin layer  20  is formed on an upper surface of the laminated body depicted in  FIG. 3H . 
         [0070]    (Step  7 ) See  FIG. 3L . 
         [0071]    Via openings  8  are formed, by laser processing, in the resin layer  20  in the laminated body depicted in  FIG. 3K . 
         [0072]    (Step  8 ) See  FIG. 3M . 
         [0073]    Via openings  8  in the laminated body depicted in  FIG. 3K  and peripheral portions of the via openings  8  are plated to form vias  11  and interconnects  9 . 
         [0074]    (Step  9 ) See  FIG. 3N . 
         [0075]    A solder resist film  30  is formed which includes exposed portions (interconnects  9 ) serving as external connection pads. Thus, a printed circuit board is obtained. 
         [0076]    The printed circuit board in the present embodiment includes the interconnect structure in the present invention and thus enables a partial increase in current capacity of the interconnects without increasing plating thickness. As a result, plating time needed to obtain a desired current capacity can be reduced, enhancing productivity. Compared to a case where a plating thickness is increased, a reduced plating thickness of the present invention precludes hindrance to the miniaturization of signal lines. 
       Embodiment 2 
       [0077]    The present embodiment relates to a semiconductor device that includes a power device or a control device embedded therein and interconnects formed by plating and in which the plated interconnects include connection structures according to the present invention. 
         [0078]    The present embodiment will be described based on  FIG. 4A . 
         [0079]    Interconnects  42  are formed on a resin layer  41   a.    
         [0080]    Semiconductor chips  43   a  and  43   b  are secured onto the interconnects  42  via insulating materials and sealed with a resin layer  41   b.    
         [0081]    Interconnects  45  are formed on a front surface of the resin layer  41   b  by plating. 
         [0082]    On a front surface of the resin layer  41   b,  vias  44  are formed which connect electrode pads for the semiconductor chips  43   a  and  43   b  to the interconnects  45 . 
         [0083]    Vias  44  are also formed in the resin layer  41   b  to electrically connect the interconnects  42  and the interconnects  45  together. 
         [0084]    The interconnects  45  are embedded in a resin layer  41   c.  The vias  44  and a groove-shaped interconnect  47  are formed in the resin layer  41   c.    
         [0085]    Interconnects  48  are formed on a front surface of the resin layer  41   c  by plating. On a front surface of the resin layer  41   c,  a solder resist layer  50  is formed which has openings through each of which a part of the corresponding interconnect  48  is exposed. 
         [0086]    The groove-shaped interconnect can be formed executing a series of steps illustrated in  FIGS. 3D to 3J  on the resin layer  41   c.    
         [0087]    Steps of forming the groove-shaped interconnect will be described below. 
         [0088]    The interconnects  45  are formed on the surface of resin layer  41   b  sealing the semiconductor chips  43   a  and  43   b.    
         [0089]    The resin layer  41   c  is accumulated on the interconnects  45 . 
         [0090]    As depicted in  FIG. 4B , on the resin layer  41   c,  drilling is further performed in which via openings  5  for signal lines are formed and grooving is performed in which the plurality of grooves  2  for large-current interconnects are formed. 
         [0091]    The via openings  5 , peripheral portions of the via openings  5 , and inner wall surfaces and peripheral portions of the grooves  2  are plated to form the vias  44 , the interconnects  48 , and the groove-shaped interconnect  47 . 
         [0092]    The interconnects  48  produced as described above are utilized as small-current conduction interconnects such as signal lines. The groove-shaped interconnect  47  is utilized as a large-current conduction interconnect. 
         [0093]    The present embodiment produces effects similar to the effects of Embodiment 1 on a semiconductor device with interconnects formed by plating. 
       Embodiment 3 
       [0094]    The present embodiment relates to a semiconductor device that includes a power device or a control device embedded therein and interconnects formed by plating and in which the plated interconnects include connection structures according to the present invention. 
         [0095]    As depicted in  FIG. 5A , the semiconductor device in the present embodiment is structured such that the groove-shaped interconnect  47  is in direct contact with the semiconductor chip  43   a.    
         [0096]    To form such an interconnect structure, first, grooves  2  are formed which extend from a front surface of the resin layer  41   b  with semiconductor chips  43   a  and  43   b  sealed therein and which reach a front surface of the semiconductor chip  43   a,  and openings  5  are formed which also extend from the front surface of the resin layer  41   b  and which reach front surfaces of the interconnects  42 , as depicted in  FIG. 5B . 
         [0097]    Normally, Al pads, SiN, and the like are exposed from the front surfaces of the semiconductor chips  43   a.  If a CO 2  laser is used to form the grooves  2 , when the semiconductor chips are irradiated directly with CO 2  laser light, prevention of damages to the semiconductor chip  43   a  is difficult. 
         [0098]    However, since the etch rate of Al pads or SiN is lower and involves higher etch selectivity than the etch rate of resin, processing can be stopped at the front surfaces of the Al pads or SiN when an excimer laser is used for drilling that allows via openings to be formed and for grooving. Furthermore, ablation processing such as this has only a low thermal effect on the semiconductor chips. Thus, as a laser, an excimer laser is preferably used. 
         [0099]    After the grooves  2  and the via openings  5  depicted in  FIG. 5B  are formed, the via openings  5 , peripheral portions of the via openings  5 , inner wall surfaces and peripheral portions of the grooves  2  are plated to form the vias  44 , the interconnects  45 , and the groove-shaped interconnect  47 . 
         [0100]    Then, the resin layer  41   c  is accumulated on the vias  44  and the groove-shaped interconnect  47 . The vias  44  are formed in the resin layer  41   c,  and the interconnects  48  are formed on a front surface of the resin layer  41   c.    
         [0101]    Then, the solder resist layer  50  is formed which has openings through each of which a part of the corresponding interconnect layer is exposed on the surface of the resin layer  41   c.  Compared to Embodiment 2, Embodiment 3 eliminates the need to further increase interconnects in order to allow groove-shaped interconnects to be produced, enabling provision of a semiconductor device with a reduced number of layers.