Abstract:
A video data transfer control system allowing secure protection of video data from unauthorized copying is disclosed. A scrambling key used to scramble video data is stored in a key register and a new scrambling key is stored in a register. At the timing of a vertical sync signal of the video data, the scrambling key is changed to the new one. As a result, the scrambling key can be frequently changed while transferring the video data, achieving enhanced protection of the video data from unauthorized copying.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention related to video technologies on a computer such as a personal computer and in particular to a video data transfer control system and method allowing video data to be rendered on a display in overlaying fashion.  
           [0003]    2. Description of the Related Art  
           [0004]    There have been proposed video data transfer controllers having a scrambling/descrambling function to protect the video data from unauthorized copying. More specifically, video data is scrambled by a scrambler and the scrambled video data is transferred through a general-purpose bus The scrambled video data is descrambled by a descrambler and the original video data is output to a graphics device.  
           [0005]    For example, Japanese Patent Application Unexamined Publication No. 6-169307 discloses an encoding/decoding device that changes randomly or at regular intervals an encryption key for encrypting a scrambling key. The video data is scrambled using the scrambling key and the scrambling key is encrypted using the encryption key that changes randomly or at regular intervals. The scrambled video data is transferred through a data bus. The encrypted scrambling key is also transferred and decrypted to produce the scrambling key, which is used to descramble the scrambled video data.  
           [0006]    Japanese Patent Application Unexamined Publication No. 9-130733 discloses a data reproducing device that allows a scrambling key to be changed at the timing of transfer instruction of a series of scrambled data. More specifically, the scrambling key is generated by a random data generator when a drive controller has received a read-out instruction from a host computer. It should be noted that a series of data to be transferred to a decoder is stored in a memory of the host computer and thereby there is a time lag between data generation and data decoding. This means that the scrambling key cannot always be changed. Accordingly, the timing of changing the scrambling key is restricted to when a transfer instruction of the series of data is detected. As the result, a new scrambling key has been transferred to the decoder before the series of scrambled data is transferred to the decoder through the memory of the host computer.  
           [0007]    In the above prior arts, however, it is not sufficient to protect the video data from unauthorized copying. In the case of the encoding/decoding device disclosed in Japanese Patent Application Unexamined Publication No. 6-169307, when the encryption key has been known by a malicious user, it is easy to copy the video data. Even in the Case where the scrambling key itself is changed as disclosed in Japanese Patent Application Unexamined Publication No. 9-130733, the timing of changing the scrambling key is restricted to when a transfer instruction of the series of data is detected and Therefore it is not so difficult to descramble the scrambled video data.  
         SUMMARY OF THE INVENTION  
         [0008]    An object of the present invention is to provide a video data transfer control system and method allowing secure protection of video data from unauthorized copying.  
           [0009]    To achieve the above object, the inventor found that the scrambling key can be changed during transfer of video data at the timing of a vertical synchronizing signal of tho video data. Since the scrambling key can be frequently changed while transferring the video data to the graphics device through the general-purpose bus, the enhanced protection of the video data from unauthorized copying is achieved.  
           [0010]    According to an aspect of the present invention, a control system for transfer of scrambled video data through a data transfer line, includes: a vertical sync detector for detecting a vertical sync signal from the video data; a scrambling key update controller for updating a scrambling key to a new scrambling key as a current scrambling key at a vertical sync timing determined depending on the vertical sync signal; a scrambler for scrambling video data using the current scrambling key to produce scrambled video data, which is transferred to the data transfer line, and a descrambler for descrambling the scrambled video data received through the data transfer line based an the current scrambling key to produce original video data.  
           [0011]    According to another aspect of the present invention, a control system for transfer of scrambled video data through a data transfer line, includes: a scrambling key changer for changing a current scrambling key to a new scrambling key; a first key memory for storing the current scrambling key that is used to scramble video data; a second key memory for storing the new scrambling key received from the scrambling key changer; a vertical sync detector for detecting a vertical sync signal from the video data; a memory controller for replacing the current scrambling key stored in the first key memory with the new scrambling key stored in the second key memory as a current scrambling key at a timing determined depending on the vertical sync signal; a scrambler fro scrambling video data using the new scrambling key to produce scrambled video data, which is transferred through the data transfer line; and a descrambler for descrambling the scrambled video data received through the data transfer line based on the new scrambling key to produce original video data.  
           [0012]    The memory controller may control such that the first key memory stores the new scrambling key from the second key memory during vertical blanking determined depending on the vertical sync signal.  
           [0013]    The memory controller may notify the descrambler that the current scrambling key has been replaced with the new scrambling key in the first key memory.  
           [0014]    The control system preferably further includes: a random number generator for generating a random number; and a third key memory for storing a random key that is a random number generated by the random number generator when the memory controller replaces the current scrambling key with the new scrambling key, wherein the scrambler scrambles the video data using the current scrambling key and the random key and the descrambler descrambles the scrambled video data based on the current scrambling key and the random key.  
           [0015]    The descrambler may be notified that the new scrambling key has been stored as a current key scrambling key in the first key memory and a combination of the new scrambling key and the random key is used to scramble the video data.  
           [0016]    According to still another aspect of the present invention, a control method for transfer of scrambled video data through a data transfer line, includes the steps of: determining whether a current scrambling key is changed to a new scrambling key; when the current scrambling key is changed to a new scrambling key, determining whether a vertical blanking period is detected from the video data; when the vertical blanking period is detected, setting the new scrambling key as a current scrambling key during vertical blanking; scrambling video data using the new scrambling key to produce scrambled video data; transferring the scrambled video data through the data transfer line; and descrambling the scrambled video data received through the data transfer line based on the new scrambling key to produce original video data.  
           [0017]    The video data may comprise a plurality of frames of video data synchronizing to a vertical sync signal, wherein a frame of video data is scrambled using the new scrambling key during a frame period, and a frame of scrambled video data is descrambled based on the new scrambling key during a subsequent frame period.  
           [0018]    When a previous scrambling key is replaced with the new scrambling key during vertical blanking between a first frame period and a second frame period, update status information indicating occurrence of a scrambling key change may be created, wherein a first frame of scrambled video data is descrambled in the second frame period based on the previous scrambling key; and a second frame of scrambled video data is descrambled in a third frame period following the second frame period based on the new scrambling key. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0019]    [0019]FIG. 1 is a block diagram showing a video data transfer control system according to a first embodiment of the present invention;  
         [0020]    [0020]FIG. 2 is a flow chart showing a scrambling key updating operation employed in the video data transfer control system according to the first embodiment of the present invention.  
         [0021]    [0021]FIG. 3 is a timing chart showing an operation of the video data transfer control system according to the first embodiment; and  
         [0022]    [0022]FIG. 4 is a block diagram showing a video data transfer control system according to a second embodiment of the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0023]    Referring to FIG. 1 a video data transfer control system  1  according to a first embodiment of the present invention includes a video data sending device  10  which is connected to a general-purpose bus  26  through a general-purpose bus bridge  25 . A bus arbiter  24  is also connected to the general purpose bus  26 . A system memory  21  including a video data area  21 A, a graphics device  22 , and a program-controlled processor (here, CPU)  23  are connected to the bus arbiter  24 . The graphics device  22  has a frame buffer  27  connected thereto.  
         [0024]    The video data sending device  10  inputs video data and its vertical synchronizing signal, and scrambles the video data using a current scrambling, which may be updated at the vertical sync timing as described later. The scrambled video data is transferred to the video data area  21 A of the system memory  21  by the general-purpose bus bridge  25  using DMA (Direct Memory Access) function through the general-purpose bus  26 . The scrambled video data stored in the video data area  21 A is read out and descrambled by the CPU  23  based on the current scrambling key. The graphics device  22  stores the descrambled video data in units of a frame into the frame buffer  27  and performs graphics processing of the video data for overlay-displaying on the screen of a personal computer (not shown).  
         [0025]    The CPU  23  executes control programs for controlling the system  1 , including a descrambler program and a scrambling key changer program to implement a descrambler  23 A and a scrambling key changer  23 B. The descrambler  23 A descrambles the scrambled video data stored in the video data area  21 A of the system memory  21  based on the current scrambling key as described above. The scrambling key changer  23 B creates a new scrambling key while holding the current scrambling key and sends the new scrambling key to the video data sending device  10  through the bus arbiter  24 , the general-purpose bus  26 , and the general-purpose bus bridge  25 . The bus arbiter  24  arbitrates data transfer through the general-purpose bus  26 .  
         [0026]    The video data sending device  10  includes a key register  11  for storing a current scrambling key and a scrambler  12  for scrambling the input video data using the current scrambling key. The scrambler  12  may be composed of one or a combination of an exclusive-OR circuit, an adder and a subtracter.  
         [0027]    The scrambled video data is transferred to the general-purpose bus bridge  25  through a host interface  13 . A new scrambling key received from the CPU  23  through host interface  13  is stored in a register  14 . A scrambling key controller  15  controls the whole operation of the video data sending device  10 .  
         [0028]    The scrambling key controller  15  includes a vertical sync detector  15 A, a key update controller  15 B, and a notification section  15 C The vertical sync detector  15 A detects a vertical sync signal of the video data to output a vertical sync detection signal to the key update controller  15 B. When receiving the vertical sync detection signal, the key update controller  15 B instructs the key register  11  to replace the current scrambling key with the new scrambling key stored in the register  14  during vertical blanking. In other words, the new scrambling key is stored as a current scrambling key in the key register  11 .  
         [0029]    When the scrambling key has been updated, the notification section  15 C sends update status information to the CPU  23  to notify the descrambler  23 A that the current scrambling key of the scrambler  12  has been changed to the new one.  
         [0030]    The above arrangement of the system  1  allows frequent changes of scrambling keys during transfer of video data from the video data sending device  10  to the graphics device  22 . A scrambling key update operation will be described in detail with reference to FIG. 2.  
         [0031]    Referring to FIG. 2, it is determined whether the current scrambling key has been changed to a new one by the scrambling key changer  23 B t(step S 11 ). When it has been changed (Y in step S 11 ), a new scrambling key received frome the scrambling key changer  23 B through the host interface  13  is stored into the register  14 . (step S 12 ).  
         [0032]    Thereafter, the key update controller  15 B determines whether a vertical blanking period is detected based on the vertical sync detection signal received from the vertical sync detector  15 A (step S 13 ). When detected (Y in step S 13 ), the key update controller  15 B instructs the key register  11  to update the current scrambling key to the new scrambling key stored in the register  14  during the detected vertical blanking (step S 14 ).  
         [0033]    When the current scrambling key has been updated, the notification section  15 C creates update status information (step S 15 ) and sends it to the descrambler  23 A of the CPU  23  (step S 16 ). After the step S 16  or when the current scrambling key is not changed (N in step S 11 ), the scrambling key update routine is terminated.  
         [0034]    Next, an operation of the video data transfer control system  1  will be described with reference to FIG  3 .  
         [0035]    Referring to FIG. 3, at time TA 0 , it is assumed that a new scrambling key (here, an initial scrambling key RK 0 ) is set in the register  14  as shown in FIG. 3( d ).  
         [0036]    At a time TA 1  that is a vertical sync timing, the CPU  23  starts controlling the transfer of video data by setting a transfer start control status to high. Since the time TA 1  is included in a vertical blanking period, the key update controller  15 B stores the initial scrambling key RK 0  as a current scrambling key SK 0  into the key register  11  as shown in FIG. 3( e ).  
         [0037]    From the time TA 1 , the CPU  23  controls sequential DMA-transfer of the scrambled video data starting with a frame of video data FD 0  to the video data area  21 A of the system memory  21  via the general-purpose bus  26 .  
         [0038]    The scrambler  12  scrambles the frame of video data FD 0  using the current scrambling key SK 0  stored in the key register  11 . Accordingly, the scrambled video data FD 0  is output to the general-purpose bus  26  as shown in FIG. 3( b ).  
         [0039]    At a time TA 2  which is a subsequent vertical sync timing, the transfer of the scrambled video data FD 0  to the video data area  21 A has already been completed. In this example, the notification section  15 C of the scrambling key controller  15  creates update status information regarding the new scrambling key RK 0  and send it to the CPU  23 .  
         [0040]    At a time TA 3 , the descrambler  23 A of the CPU  23  starts descrambling the scrambled video data FD 0  using the new scrambling the key RK 0  that was sent to the video data sending device  10  and stored in the register  14  at the time TA 0  as shown in FIG. 3( g ). The descrambler  23 A is notified of the scrambling key change to the new scrambling key RK 0  by the update status information that was received from the scrambling key controller  15  at the time TA 2 . A delay time from TA 2  to TA 3  is caused by other software occupying the operating system on the CPU  23 .  
         [0041]    At a time TA 4 , the descrambler  23 A of the CPU  23  starts descrambling a subsequent frame of scrambled video data FD 1  using the scrambling key RK 0  that was sent to the video data sending device  10  and stored in the register  14  at the time TA 0  as shown in FIG. 3( g ). At the same time, the scrambling key changer  23 B sends a new scrambling key RK 1  to the video data sending device  10  and it is stored in the register  14  as shown in FIG. 3( d ).  
         [0042]    At a time TA 5  which is included in a vertical blanking period, the key update controller  15 B stores the new scrambling key RK 1  as a current scrambling key SK 1  into the key register  11  as shown in FIG. 3( e ). Here, a video data frame FD 3  and following ones are scrambled by the scrambler  12  using the current scrambling key SK 1 .  
         [0043]    At a time TA 6 , the transfer of the scrambled video data FD 0  to the video data area  21 A has already been completed. Accordingly, the notification section  15 C of the scrambling key controller  15  creates update status information indicating that the current scrambling key has been changed to the new scrambling key RK 1  and sends it to the CPU  23 .  
         [0044]    At a time TA 7 , the descrambler  23 A of the CPU  23  starts descrambling the scrambled video data FD 0  using the new scrambling key RK 1  that was sent to the video data sending device  10  and stored in the register  14  at the time TA 4  as shown in FIG. 3( g ). The descrambler  23 A is notified of the scrambling key change to the new scrambling key RK 1  by the update status information that was received from the scrambling key controller  15  at the time TA 6 .  
         [0045]    At a time TA 8 , the descrambler  23 A of the CPU  23  start descrambling a subsequent frame of scrambled video data FD 4  using the scrambling key RK 1  that was sent to the video data sending device  10  and stored in the register  14  at the time TA 4  as shown in FIG. 3( g ). At the same time, the scrambling key changer  23 B sends a new scrambling key RK 2  to the video data sending device  10  and stored in the register  14  as shown in FIG. 3( d ).  
         [0046]    At a time TA 9 , the key update controller  15 B stores the new scrambling key RK 2  as a current scrambling key SK 2  into the key register  11  as shown in FIG. 3( e ). Accordingly, a video data frame FD 6  and following ones are scrambled by the scrambler  12  using the current scrambling key SK 2 .  
         [0047]    It is assumed that the operating system is put under increased load after the time TA 8  and thereby, at time TA 9 , the descrambling of the scrambled video data FD 4  has not been completed. In this case, the video frame data FD 5  is discarded without processed and the processing of the video frame data FD 4  continues. Accordingly, the update status information changes at a time TA 10  and the descrambler  23 A starts descrambling the scrambled video frame data FD 6  using the new scrambling key RK 2 .  
         [0048]    As described above, according to the first embodiment of the present invention, a new scrambling key is previously stored in the register  14  and the current scrambling key stored in the key register  11  can be changed to the new one during vertical blanking based on a vertical sync signal of video data. Accordingly, even when transferring the video data, the scrambling key can be changed for each frame at the time of vertical blanking.  
         [0049]    In addition, the descrambler  23 A starts descrambling video frame data read out from the video data area  21 A of the system memory  21  by monitoring the update status information received from the scrambling key controller  15  of the video data sending device  10 . Accordingly, even when the CPU  23  is put under heavy load, causing video frame data to be discarded, a correct scrambling key can be identified, resulting in secure descrambling.  
         [0050]    The scrambling scheme employed in the video data sending device  10  is not restricted to that of the first embodiment. According to a second embodiment of the present invention, a combination of a random key and a scrambling key may be used to scramble input video data. A circuit of a video data sending device  10  in the second embodiment is shown in FIG. 4.  
         [0051]    Referring to FIG. 4, blocks similar to those previously described with reference to FIG. 1 are denoted by the same reference numerals and their descriptions are omitted. In the second embodiment, a random number generator  16  and a random key register  17  are added to the video data sending device  10  of the first embodiment.  
         [0052]    The random number generator  16  may include a prime number counter and the like. A random number generated by the random number generator  16  is stored as a random key in the random key register  17 . When the current scrambling key stored in the key register  11  is changed to a new scrambling key stored in the register  14 , the random key register  17  stores a random number generated by the random number generator  16 . The scrambler  12  uses the scrambling key stored n the key register  11  and the random key stored in the random key register  17  to scramble the video data, resulting in enhanced scrambling of video data.  
         [0053]    When the current scrambling key is changed, update status information including the random key stored in the random key register  17  may be sent to the descrambler  23 A on the CPU  23 . Accordingly, the descrambler  23 A can descramble the scrambled video data to output the original video data to the graphics device  22 .  
         [0054]    As described above, according to the second embodiment of the present invention, the current scrambling key stored in the key register  11  can be changed to a new one and a random key is latched from the random number generator  16  during vertical blanking based on a vertical sync signal of video data. A combination of the new scrambling key and the random number is used to scramble video data. Accordingly, even when transferring the video data, the combined scrambling key can be changed for each frame at the timing of vertical blanking, resulting in further enhanced scrambling.  
         [0055]    In addition, the descrambler  23 A starts descrambling video frame data read out from the video data area  21 A of the system memory  21  by monitoring the update status information including the random key received from the video data sending device  10 . Accordingly, even when the CPU  23  is put under heavy load, causing video frame data to be discarded, a correct scrambling key composed of the scrambling key and the random key can be identified, resulting in secure descrambling.