Abstract:
An output driver. The novel output driver includes a first circuit for receiving an input signal and in accordance therewith generating an output signal at an output node, a second circuit for applying a variable current to the output node, and a third circuit for controlling the magnitude of the variable current in accordance with the input signal. In an illustrative embodiment, the third circuit is adapted to generate a controlling current in accordance with the input signal, and the second circuit includes a current mirror adapted to receive the controlling current and output a scaled version of the controlling current to the output node.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of U.S. Provisional Application No. 60/529,335 filed Dec. 12, 2003, the disclosure of which is hereby incorporated by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to electronics. More specifically, the present invention relates to output drivers for digital circuits. 
     2. Description of the Related Art 
     Electronic circuits typically include several output drivers used to pass signals from one chip to another, or from one circuit board to another. An example of this is an M-bit analog to digital converter (ADC) driving an external circuit. In this case, a differential output driver is required for each bit (for a total of M differential output drivers), as well as additional output drivers for the saturation and “data valid” bits. Another example is a multi-channel deserializer or switch matrix where the number of differential output drivers could be greater than 100. 
     The objective of a digital output driver is to swing the output voltage from one defined level to another as rapidly as possible. Due to the capacitive load on the output driver, in order to make a fast transition between logic states, the output driver must sink or source a large current into the output transmission line in order to provide an output signal having logic high and logic low signals within their specified voltage ranges. The rising transition time (to go from logic low to logic high) of a typical output driver is relatively short. The falling transition time (to go from logic high to logic low), however, is usually much longer because the rate at which the load capacitance can discharge is set by the current sink. The larger the current sink is, the faster the trailing edge will go down. This is, of course, a tradeoff with power dissipation. The larger the current sink is, the more power the circuit will dissipate. 
     Digital output drivers must therefore provide adequate current sourcing and sinking capability in order to drive capacitive and resistive loads at the required speed. If differential outputs are required, then two current sources are needed for each driver. For circuits having several output drivers, considerable power is dissipated by the need to have several current sources providing drive and sink currents for the output drivers. 
     Hence, there is a need in the art for an improved output driver offering lower power consumption than prior art output drivers, which is operable at high speeds. 
     SUMMARY OF THE INVENTION 
     The need in the art is addressed by the output driver of the present invention. The novel output driver includes a first circuit for receiving an input signal and in accordance therewith generating an output signal at an output node, a second circuit for applying a variable current to the output node, and a third circuit for controlling the magnitude of the variable current in accordance with the input signal. In an illustrative embodiment, the third circuit is adapted to generate a controlling current in accordance with the input signal, and the second circuit includes a current mirror adapted to receive the controlling current and output a scaled version of the controlling current to the output node. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1   a  is a simplified schematic of a conventional single-ended output driver. 
         FIG. 1   b  is a graph of an example input waveform V IN  and a corresponding output waveform V OUT  for the conventional output driver of  FIG. 1   a.    
         FIG. 2  is a simplified schematic of a conventional differential output driver. 
         FIG. 3  is a simplified schematic of an illustrative embodiment of an output driver designed in accordance with the teachings of the present invention. 
         FIG. 4  is a simplified schematic of an alternate embodiment of an output driver designed in accordance with the teachings of the present invention. 
     
    
    
     DESCRIPTION OF THE INVENTION 
     Illustrative embodiments and exemplary applications will now be described with reference to the accompanying drawings to disclose the advantageous teachings of the present invention. 
     While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof and additional fields in which the present invention would be of significant utility. 
       FIG. 1   a  is a simplified schematic of a conventional single-ended output driver  10 . The output driver  10  includes a transistor Q 1  having a base adapted to receive an input signal V IN  from an input terminal  12 , a collector coupled to a voltage supply V CC , and an emitter coupled to a current source  14  of value I and to an output terminal  16 , which provides an output signal V OUT . The emitter of Q 1  is also coupled to a load capacitance C L  and load resistance R L . 
     The objectives of this circuit  10  are to swing the output voltage V OUT  from one defined level to another as rapidly as possible.  FIG. 1   b  is a graph of an example input waveform V IN  and a corresponding output waveform V OUT  for the output driver  10  of  FIG. 1   a . As can be seen in  FIG. 1   b , when the input V IN  goes from a low level to a high level, then the output V OUT  goes from a low level to a high level relatively rapidly (i.e. the circuit  10  has a fast rising transition time T R ). This is because the current to charge the load capacitance C L  is supplied by Q 1  and limited mostly by the base current drive. 
     On the other hand, when the input V IN  goes negative, from a high level to a low level, then the output V OUT  follows more slowly. This is because the rate at which C L  can discharge is set by the current sink, I. The larger the current sink I is, the faster the trailing edge will go down. The larger I is, however, the more power the circuit  10  will dissipate. 
     There is therefore a minimum value for the current source/sink required in order for the circuit to operate at the desired speed. Setting the value for the current I must satisfy two criteria. First, it must provide the desired output voltage swing between logic low and logic high. For example, assume the desired output swing is 0.4 V. Therefore, V OUT =IR L  or I=V OUT /R L . Next, I must satisfy the slew rate requirements as depicted by I=C L dV OUT /dt. For this example, let C L =1.0 pF, V OUT =0.4 V, and the desired maximum transition time ΔT=0.1 nanoseconds. Setting these two equations for I equal to each other results in: V OUT /R L =C L dV OUT /dt, or 0.4/R L =10 −12  (0.4/10 −10 ). Solving for R L  gives: R L =0.4×10 −10 /0.4×10 −10 =100Ω. Then, substituting back into the first equation, gives the result I=V OUT /R L =0.4/100=4 mA. 
       FIG. 1   a  shows a single ended output driver. If a differential output was required, then two current sources would be needed, one for each output. The prior art has attempted to reduce power in a differential output driver by devising a circuit that utilizes only one current sink to drive R L  and to discharge C L  by switching it from one output to the other, as required (or steered) by the input signal. 
       FIG. 2  is a simplified schematic of a conventional differential output driver  20 . The circuit  20  includes a differential pair Q 1  and Q 2 , having emitters connected in common to a current source  14 , bases coupled to differential input signals V IN  and −V IN , respectively, and collectors coupled to V CC  through resistors R 1  and R 2 , respectively. The collector of Q 1  is also coupled to the bases of transistors Q 3  and Q 4 , and the collector of Q 2  is also coupled to the bases of transistors Q 7  and Q 8 . The collectors of Q 3 , Q 4 , Q 7  and Q 8  are coupled to V CC . The emitter of Q 3  is connected to the anode of a diode D 1 , the cathode of which is connected to a current source  22  and to the base of a transistor Q 5 . The emitter of Q 4  is connected to a current source  24  and to the collector of a transistor Q 6 . The emitter of Q 7  is connected to a current source  28  and to the collector of Q 5 . The emitter of Q 8  is connected to the anode of a diode D 2 , the cathode of which is connected to a current source  30  and to the base of Q 6 . The emitters of Q 5  and Q 6  are connected in common to a current source  26 . The outputs of the driver  20 , at the collectors of Q 5  and Q 6 , are coupled to load capacitances C 1  and C 2 , respectively, and a load resistance R L  is connected between the collectors of Q 5  and Q 6 . 
     As can be seen in  FIG. 2 , six current sinks are required in a conventional differential output driver  20 . The current source  26  is the largest sink, because it provides the needed voltage drop across R L . The current source  26  also discharges the load capacitance and is switched from one output to the other as steered by V IN . If V IN  is more positive than −V IN , then Q 1  is on and Q 2  is off. Therefore, the emitter of Q 7  is at V CC −0.8 V. If, as an example, the resistance of R 1  multiplied by the current in current source  22  was equal to 1 V, then the emitter of Q 4  would be at V CC −1.8 V. Q 6  would be on because the base of Q 6  is equal to V CC −0.8 V−0.8 V, which equals 3.4 V if V CC =5 V. Q 5  would be off because the base of Q 5  would be equal to V CC −1 V−0.8 V−0.8 V=2.4 V. This is one volt more negative than the base of Q 6 . 
     Now, when V IN  goes more negative than −V IN , Q 5  will turn on because its base voltage will be higher than the base voltage at Q 6 . When Q 5  turns on, the current sink  26  will be routed to the emitter of Q 7 , allowing C 1  to discharge rapidly through the current sink  26 . In this way, the current sink  26  is shared between the two outputs as required to provide the sink current as the respective output is pulled low. In this prior art implementation, all six current sources are operational all the time and therefore they will all add to the power dissipated in the driver circuit. The present invention minimizes this power dissipation by implementing the current sources in a novel configuration, allowing them to be turned off or reduced in magnitude when not required. 
       FIG. 3  is a simplified schematic of an illustrative embodiment of an output driver  40  designed in accordance with the teachings of the present invention. The embodiment shown is a differential implementation. The invention, however, is not limited thereto. It may be applied to a single-ended implementation without departing from the scope of the present teachings. 
     The novel output driver  40  includes an input circuit  50  comprising a differential pair Q 1  and Q 2 , having emitters connected in common to a current source  42  of value I 1 , and bases coupled to differential inputs V IN  and −V IN , respectively. The outputs of Q 1  and Q 2  are coupled to a current controlling circuit  52 , including transistors Q 11  and Q 12 , and to an output circuit  54 , including transistors Q 13  and Q 14 . The collector of Q 1  is coupled to the base of Q 13 , and to the emitter of Q 11  through a resistor R 1 . The collector of Q 2  is coupled to the base of Q 14 , and to the emitter of Q 12  through a resistor R 2 . The emitter of Q 13  is connected to a first output node V OUT1  and to a load capacitance C 1 , and the emitter of Q 14  is connected to a second output node V OUT2  and to a load capacitance C 2 . A load resistance R L  is connected between V OUT1  and V OUT2 . 
     The current controlling circuit  52  is adapted to generate variable currents I 6  and I 7 , the values of which depend on the input signals. The current I 6  controls the current sink for the load capacitance C 2 , and the current I 7  controls the current sink for C 1 . When V IN  becomes more negative than −V IN , then C 2  needs a large current sink in order to discharge rapidly. C 1 , on the other hand, does not need a large current sink. The circuit  52  therefore outputs a large I 6  and a small I 7 . When V IN  becomes more positive than −V IN , then C 1  needs the large current sink, and the circuit  52  outputs a large I 7  and a small I 6 . In the illustrative embodiment, the current controlling circuit  52  includes transistors Q 11  and Q 12 . The bases of Q 11  and Q 12  are connected to a reference voltage V REF , and the collectors are connected to a current source  44  of value I 2  and a current source  46  of value I 3 , respectively. The currents I 2  and I 3  are slightly larger than I 1 , so I 2 =I 3 =I 1 +ΔI. (In this embodiment, I 2  is equal to I 3  for symmetry, but I 2  can differ from I 3  without departing from the scope of the present teachings.) The voltage at the emitter of Q 11  is labeled V 1 , and the voltage at the emitter of Q 12  is labeled V 2 . The collector of Q 11  is also connected to a first current mirror  56 , supplying the current mirror  56  with a current I 6 . The collector of Q 12  is also connected to a second current mirror  58 , supplying the current mirror  58  with a current I 7 . 
     The current mirror  58  includes transistors Q 15 , Q 16 , and Q 17 . The emitters of Q 15  and Q 17  are connected in common to a negative power Supply −V EE , and the bases of Q 15  and Q 17  are connected in common to the emitter of Q 16 . The collector of Q 15  is connected to V OUT1 , and the collector of Q 16  is connected to V CC . The collector of Q 17  is connected to the base of Q 16  and to the collector of Q 12 . The current I 4  at the collector of Q 15  is controlled by the current I 7  at the collector of Q 17 . 
     The current mirror  56  includes transistors Q 18 , Q 19 , and Q 20 . The emitters of Q 18  and Q 20  are connected in common to −V EE , and the bases of Q 18  and Q 20  are connected in common to the emitter of Q 19 . The collector of Q 18  is connected to V OUT2 , and the collector of Q 19  is connected to V CC . The collector of Q 20  is connected to the base of Q 19  and to the collector of Q 11 . The current I 5  at the collector of Q 18  is controlled by the current I 6  at the collector of Q 20 . 
     A description of the circuit&#39;s operation follows. Let R L  equal the output load and C 1  and C 2  are load-related capacitances. If the circuit  40  is in a steady state where V IN  is more positive than −V IN , then Q 1  is on and Q 2  is off. I 2  is slightly larger than I 1 , I 2 =I 1 +ΔI, therefore I 2  splits and its I 1  component flows through Q 1 . The residual current, ΔI, becomes I 6 . Due to the nature of current mirrors, I 5 =NI 6 , where N is some number depending on the characteristics of the transistors (Q 18 , Q 19 , Q 20 ) forming the current mirror. Let N=5, so I 5 =5 I 6 =5ΔI. Since Q 2  is off, Q 14  is conducting and its emitter voltage V OUT2  is approximately equal to V2−0.8 V. The emitter of Q 13  is at V OUT1 =V 1 −(I 1 R1)−0.8 V. V 1  and V 2  are equal and are set by cascode circuits Q 11  and Q 12  at the outputs of the current sources I 2  and I 3 . C 2  is therefore charged up to V2−0.8 V. 
     Now, when the input changes so that V IN  becomes more negative than −V IN , C 2  will need to discharge rapidly to a voltage equal to V 1 −(I 1 R2)−0.8 V. This is accomplished when Q 1  turns off and I 6  becomes equal to I 2 , which is equal to I 1 +ΔI. Now, I 5  will equal NI 6  or N(I 1 +ΔI), which will pull current from C 2 , thereby allowing it to reach its final state voltage more rapidly. 
     Thus, the current I 5  can be set with a small current, NΔI, to keep Q 14  and Q 18  on, but at a low current level. To maximize the circuit&#39;s switching speed, I 5  is then increased to N(I 1 +ΔI) to rapidly discharge C 2  when it is switched to the low state. Since the circuit is symmetrical, the other half works in the same manner. 
     The novel circuit  40  of the present invention therefore reduces power in an output driver by dynamically controlling the current sinks, turning them on or off (or reduced in magnitude) through the use of current mirrors controlled by the input signal. When a current source or sink is not needed, it is much reduced and therefore dissipating little power. The sink currents are controlled by much smaller currents due to the ability of a current mirror to scale (have current gain) the value of the mirrored currents. In this way, overall power consumption can be reduced over prior art implementations. 
     Depending on the value of N, there is a power reduction from the prior art of 14% for N=5 to almost 30% when N=50. While the prior art circuit as shown in  FIG. 2  has six fixed current sources, the driver  40  of the present invention has two fixed current sources, I 2  and I 3  (since I 1  will sink whichever one passes through the input Darlington pair and therefore does not dissipate any additional power), and two dynamic current sources that are in fact current mirrors ( 56  and  58 ). The collector currents for Q 19  and Q 16  are not considered in the calculations since they are the base currents of (Q 18 , Q 20 ) and (Q 15 , Q 17 ), respectively, and are very small compared to the other current sources (sinks). The current mirrors can be optimized to provide gain so that the controlling currents need not be large. Significant power reductions are realized for values of N greater than 5. 
       FIG. 4  is a simplified schematic of an alternate embodiment of an output driver  40 ′ designed in accordance with the teachings of the present invention. The circuit  40 ′ is similar to circuit  40  of  FIG. 3 , except the output circuit  54 ′ is modified to include Darlington pairs (Q 21 , Q 13 ) and (Q 22 , Q 14 ) to improve circuit drive and speed. The collector of Q 1  is now coupled to the base of Q 21 , the emitter of which is connected to the base of Q 13 . The emitter of Q 13  is coupled to V OUT1 . The collectors of Q 21  and Q 13  are coupled to V CC . The collector of Q 2  is now coupled to the base of Q 22 , the emitter of which is connected to the base of Q 14 . The emitter of Q 14  is coupled to V OUT2 . The collectors of Q 22  and Q 14  are coupled to V CC . 
     An additional output can also be added to each current mirror  56 ′ and  58 ′ to drive the transistors Q 22  and Q 21 , respectively. In the illustrative embodiment, current mirror  56 ′ further includes a transistor Q 24  having a base coupled to the emitter of Q 19 , an emitter coupled to −V EE , and a collector coupled to the emitter of Q 22 . Current mirror  58 ′ further includes a transistor Q 23  having a base coupled to the emitter of Q 16 , an emitter coupled to −V EE , and a collector coupled to the emitter of Q 21 . These additional outputs Q 23  and Q 24  are tailored to have a gain K in order to optimize the circuit&#39;s performance in both power and speed. Optimum values for K and N are selected depending on the particular technology used and current drive requirements. 
     The embodiment of  FIG. 4  shows yet another improvement. A resistor R 3  is added to the current controlling circuit  52 ′ between the emitters of Q 11  and Q 12 . This allows a trickle current (ΔI) to flow through R 3 , the direction of the trickle current being determined by whichever transistor (Q 1  or Q 2 ) is more on at the time (i.e. which base to emitter voltage V BE  is larger). This trickle current keeps the cascode transistors Q 11  and Q 12  always ‘on’ and therefore improves the switching speed of the circuit. For this example, let I 2  and I 3  both equal I 1 . When Q 1  is on and Q 2  is off, I 6 =ΔI. Therefore I 5 =NI 6  or I 5 =NΔI. I 7  is now equal to I 3 −ΔI. The rest of the circuit operates as described previously assuming the additional base to emitter voltage drop in the Darlington pair is properly considered. 
     Thus, the present invention has been described herein with reference to a particular embodiment for a particular application. Those having ordinary skill in the art and access to the present teachings will recognize additional modifications, applications and embodiments within the scope thereof. For example, while the illustrative embodiments have been described using NPN bipolar transistors, other process technologies may be used without departing from the scope of the present teachings. 
     It is therefore intended by the appended claims to cover any and all such applications, modifications and embodiments within the scope of the present invention. 
     Accordingly,