Abstract:
A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates generally to semiconductor package devices, semiconductor package structures, and fabrication methods thereof, and more particularly to a semiconductor package device with TSVs (Through Silicon Vias), a semiconductor package structure, and fabrication methods thereof. 
         [0003]    2. Description of Related Art 
         [0004]    Along with the development of electronic products and the requirement for high integration of semiconductor chips, TSV technique based on deep silicon etching has been proposed and disclosed in such as U.S. Pat. No. 5,270,261 and No.  5 , 202 , 754 . 
         [0005]    Referring to  FIGS. 2A to 2E , a conventional fabrication method of a semiconductor device with TSVs is shown. As shown in the drawings, a wafer  20  with a plurality of openings  201  formed on a first surface thereof is provided, wherein the openings  201  are filled with a metal material  21 , and solder pads  22  are formed on the metal material  21  and adhered to a carrier  24  through an adhesive material  23 . Then, the wafer  20  is thinned through a grinding process such that the metal material  21  can be exposed through a second surface of the wafer  20  opposed to the first surface with the solder pads  22 . Meanwhile, the adhesive material  23  and the carrier  24  are removed. Thereafter, semiconductor chips  30  are disposed on the second surface of the wafer  20  that exposes the metal material  21  so as to electrically connect the wafer  20 . Further, a plurality of solder bumps  31  is mounted on the solder pads  22  of the wafer  20  such that the semiconductor chips  30  can be electrically connected to external devices through the solder bumps  31 . 
         [0006]    During mounting of the solder bumps, the second surface of the wafer  20  with the semiconductor chips  30  faces downward and the first surface of the wafer  20  with the solder pads  22  faces upward so as to mount the solder bumps  31  on the solder pads  22 . However, since the semiconductor chips  30  have different thicknesses, the wafer  20  cannot be disposed in a flat manner, which can lead to position deviation of the solder bumps  31  during the solder bump process and difficulty in cutting of the wafer during a singulation process. 
         [0007]    Therefore, how to provide a semiconductor device with TSVs and a fabrication method thereof so as to overcome the above-described drawbacks has become urgent. 
       SUMMARY OF THE INVENTION 
       [0008]    According to the above drawbacks, an object of the present invention is to provide a semiconductor package device, a semiconductor package structure and fabrication methods thereof so as to improve flatness of the wafer during the solder bump process. 
         [0009]    Another object of the present invention is to provide a semiconductor package device, a semiconductor package structure and fabrication methods thereof so as to facilitate cutting of the wafer during a singulation process. 
         [0010]    A further object of the present invention is to provide a semiconductor package device, a semiconductor package structure and fabrication methods so as to prevent position deviation of the solder bumps. 
         [0011]    Still another object of the present invention is to provide a semiconductor package device, a semiconductor package structure and fabrication methods thereof so as to protect semiconductor chips. 
         [0012]    A further object of the present invention is to provide a semiconductor package device, a semiconductor package structure and fabrication methods thereof so as to improve the heat dissipating efficiency. 
         [0013]    In order to attain the above and other objects, the present invention provides fabrication method of a semiconductor package device, which comprises: providing a wafer having a plurality of silicon substrates, wherein each of the silicon substrates has a first surface and an opposed second surface and a plurality of TSVs; disposing a plurality of semiconductor chips on the first surfaces of the silicon substrates, wherein the semiconductor chips are electrically connected to the TSVs; forming an encapsulant on the first surfaces of the silicon substrates to encapsulate the semiconductor chips; forming a hard component on the encapsulant; and forming a plurality of conductive elements on the second surfaces of the silicon substrates to electrically connect the TSVs. The method further comprises performing a singulation process to the wafer. The hard component is made of one of a glass material, a thermosetting material and a metal material. 
         [0014]    Through the above-described fabrication method, a semiconductor package device is provided, which comprises: a silicon substrate having a first surface and an opposed second surface and a plurality of TSVs; a semiconductor chip disposed on the first surface of the silicon substrate and electrically connected to the TSVs; an encapsulant formed on the first surface of the silicon substrate to encapsulate the semiconductor chip; a hard component disposed on the encapsulant; and a plurality of conductive elements disposed on the second surface of the silicon substrate and electrically connected to the TSVs. 
         [0015]    The present invention further discloses a fabrication method of a semiconductor package structure, which comprises: providing a wafer having a plurality of silicon substrates, wherein each of the silicon substrates has a first surface and an opposed second surface and a plurality of TSVs; disposing a plurality of semiconductor chips on the first surfaces of the silicon substrates, wherein the semiconductor chips are electrically connected to the TSVs; forming an encapsulant on the first surfaces of the silicon substrates to encapsulate the semiconductor chips; forming a hard component on the encapsulant; forming a plurality of conductive elements on the second surfaces of the silicon substrates to electrically connect the TSVs; and disposing a carrier to the conductive elements such that the carrier can be electrically connected to the semiconductor chips through the conductive elements. 
         [0016]    Through the above-described fabrication method, a semiconductor package structure is provided, which comprises: a silicon substrate having a first surface and an opposed second surface and a plurality of TSVs; a semiconductor chip disposed on the first surface of the silicon substrate and electrically connected to the TSVs; an encapsulant formed on the first surface of the silicon substrate to encapsulate the semiconductor chip; a hard component disposed on the encapsulant; a plurality of conductive elements disposed on the second surface of the silicon substrate and electrically connected to the TSVs; and a carrier disposed to the conductive elements and electrically connected to the semiconductor chip through the conductive elements. 
         [0017]    Therefore, the present invention mainly involves providing a wafer having a plurality of silicon substrates, wherein each of the silicon substrates has a first surface and an opposed second surface and a plurality of TSVs filled with a conductive material; disposing a plurality of semiconductor chips on the first surfaces of the silicon substrates with the semiconductor chips electrically connected to the TSVs; forming an encapsulant on the first surfaces of the silicon substrates to encapsulate the semiconductor chips; forming a hard component on the encapsulant; forming a plurality of conductive elements on the second surfaces of the silicon substrates; and then performing a singulation process to the wafer so as to separate the silicon substrates from each other, thereby forming a plurality of semiconductor package devices with TSVs. Further, the semiconductor package devices can be respectively electrically connected to carriers such as substrates, circuit boards or lead frames through the conductive elements so as to form semiconductor package structures. Therein, the hard component is made of a glass material, a metal material or a thermosetting material. The hard component ensures flatness of the wafer during mounting of the conductive elements. The hard component also provides support to the wafer such that the wafer can be firmly placed on a singulation carrier during the singulation process, thereby facilitating cutting of the wafer. In addition, the hard component provides protection to the semiconductor chips disposed therebelow, and the hard component made of a metal material improves the heat dissipating efficiency of the semiconductor package device. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0018]      FIGS. 1A to 1D  are sectional views showing a semiconductor package device and a fabrication method thereof according to the present invention; 
           [0019]      FIG. 1E  is a sectional view showing a semiconductor package structure and a fabrication method thereof according to the present invention; and 
           [0020]      FIGS. 2A to 2E  are sectional views showing a conventional fabrication method of a semiconductor device formed with TSVs. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0021]    The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those skilled in the art after reading the disclosure of this specification. The present invention may also be implemented and applied according to other embodiments, and the details may be modified based on different views and applications without departing from the spirit of the invention. 
         [0022]      FIGS. 1A to 1D  are sectional views showing a semiconductor package device and a fabrication method thereof according to the present invention. 
         [0023]    As shown in  FIG. 1A , a wafer  10  having a plurality of silicon substrates  100  is provided. Each of the silicon substrates  100  has a first surface  101  and a second surface  102  opposed to the first surface  101 . A plurality of TSVs  103  is formed in each of the silicon substrates  100 , wherein the TSVs  103  are filled with a conductive material. That is, at least a through hole is formed on the second surface  102  of the silicon substrate  100 , a conductive material such as Cu or Ni/Au is filled in the through hole, and a grinding process is performed for thinning the first surface  101  of the silicon substrate  100  so as to expose the conductive material filled in the through hole, thus forming a TSV  103 . 
         [0024]    Subsequently, a plurality of semiconductor chips  11  is disposed on the first surfaces  101  of the silicon substrates  100  and electrically connected to the TSVs  103 . Therein, an underfill adhesive  111  is filled between the silicon substrates  100  and the semiconductor chips  11  so as to reduce relative deformation of the wafer  10  and the semiconductor chips  11 . 
         [0025]    As shown in  FIG. 1B , an encapsulant  12  is formed on the first surfaces  101  of the silicon substrates  100  so as to encapsulate the semiconductor chips  11 . 
         [0026]    Thereafter, a hard component  13  is formed on the encapsulant  12 , wherein the hard component  13  may be made of a glass material, a metal material such as copper, or a thermosetting material such as a polyimide resin, a BT (Bismaleimide Triazine) resin, FR-4 and so on. 
         [0027]    As shown in  FIG. 1C , a plurality of conductive elements  14  such as solder bumps is formed on the second surfaces  102  of the silicon substrates  100  and electrically connected to the TSVs  103 . Therein, during a solder bump process, the first surfaces  101  of the silicon substrates  100  with the hard component  13  face downward and the second surfaces  102  face upward so as to form the conductive elements  14  on the second surfaces  102 . As a result, the semiconductor chips  11  can be electrically connected to an external device through the TSVs  103  and the conductive elements  14 . Meanwhile, the hard component  13  ensures flatness of the wafer  10  during the solder bump process. 
         [0028]    As shown in  FIG. 1D , the wafer  10  is singulated to separate the silicon substrates  100  from each other, thereby forming a plurality of semiconductor package devices with TSVs  103 . During the singulation process, since the hard component  13  made of a glass material, a metal material or a thermosetting material provides support for the wafer  10 , the wafer  10  can be firmly placed on a carrier, thereby facilitating cutting of the wafer so as to form a plurality of semiconductor package devices. 
         [0029]    Further, the hard component  13  that is disposed above the semiconductor chips  11  provides protection to the semiconductor chips  11 . In addition, the hard component  13  made of a metal material improves the heat dissipating efficiency of the semiconductor package devices. 
         [0030]    Further referring to  FIGS. 1C to 1D , through the above-described fabrication method, a semiconductor package device is provided, which comprises: a silicon substrate  100  having a first surface  101 , an opposed second surface  102  and a plurality of TSVs  103 ; a semiconductor chip  11  disposed on the first surface  101  and electrically connected to the TSVs  103 ; an encapsulant  12  formed on the first surface  101  of the silicon substrate  100  to encapsulate the semiconductor chip  11 ; a hard component  13  disposed on the encapsulant  12 ; and a plurality of conductive elements  14  disposed on the second surface  102  of the silicon substrate  100  and electrically connected to the TSVs  103 . 
         [0031]    Referring to  FIG. 1E , a semiconductor package structure according to the present invention is shown. Same as the above-described method, a wafer having a plurality of silicon substrates  100  with TSVs  103  is provided, with the TSVs  103  filled with a conductive material, a plurality of semiconductor chips  11  is disposed on the silicon substrates  100  and electrically connected to the TSVs  103 , and an encapsulant  12  is formed on the silicon substrates  100  to encapsulate the semiconductor chips  11 , then, a hard component  13  is formed on the encapsulant  12  and a plurality of conductive elements  14  is formed. Thereafter, a singulation process is performed to separate the silicon substrates  100  from each other, thereby forming a plurality of semiconductor package devices. Further, a carrier  15  is disposed to such a semiconductor package device so as to electrically connect the semiconductor chip  11  through the conductive elements  14 , thereby forming a semiconductor package structure. The carrier  15  may be a substrate, a circuit board or a lead frame. 
         [0032]    Through the above-described method, a semiconductor package structure is provided, which comprises: a silicon substrate  100  having a first surface  101  and an opposed second surface  102  and a plurality of TSVs  103 ; a semiconductor chip  11  disposed on the first surface  101  and electrically connected to the TSVs  103 ; an encapsulant  12  formed on the first surface  101  of the silicon substrate  100  to encapsulate the semiconductor chip  11 ; a hard component  13  disposed on the encapsulant  12 ; a plurality of conductive elements  14  disposed on the second surface  102  of the silicon substrate  100  and electrically connected to the TSVs  103 ; and a carrier  15  disposed to the conductive elements  14  so as to electrically connect the semiconductor chip  11  through the conductive elements  14 . 
         [0033]    Therefore, the present invention mainly involves providing a wafer having a plurality of silicon substrates, wherein each of the silicon substrates has a first surface and an opposed second surface and a plurality of TSVs filled with a conductive material; disposing a plurality of semiconductor chips on the first surfaces of the silicon substrates with the semiconductor chips electrically connected to the TSVs; forming an encapsulant on the first surfaces of the silicon substrates to encapsulate the semiconductor chips; forming a hard component on the encapsulant; forming a plurality of conductive elements on the second surfaces of the silicon substrates; and then performing a singulation process to the wafer so as to separate the silicon substrates from each other, thereby forming a plurality of semiconductor package devices with TSVs. Further, the semiconductor package devices can be respectively electrically connected to carriers such as substrates, circuit boards or lead frames through the conductive elements so as to form semiconductor package structures. Therein, the hard component is made of a glass material, a metal material or a thermosetting material. The hard component ensures flatness of the wafer during mounting of the conductive elements. The hard component also provides support to the wafer such that the wafer can be firmly placed on a singulation carrier during the singulation process, thereby facilitating cutting of the wafer. In addition, the hard component provides protection to the semiconductor chips disposed therebelow, and the hard component made of a metal material improves the heat dissipating efficiency of the semiconductor package device. 
         [0034]    The above-described descriptions of the detailed embodiments are only to illustrate the preferred implementation according to the present invention, and it is not to limit the scope of the present invention, Accordingly, all modifications and variations completed by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims.