Abstract:
A method of fabricating a semiconductor device includes forming a passivation layer on a least one capping layer of the semiconductor device, and forming an encapsulant layer on the passivation layer. The method further includes patterning the encapsulant layer to expose a portion of the passivation layer and forming a final via opening in the passivation layer. A conductive material is deposited in the final via opening. The method further includes planarizing the conductive material until reaching a remaining portion of the encapsulant layer such that the conductive material is flush with the encapsulant layer and the passivation layer is preserved.

Description:
DOMESTIC PRIORITY 
       [0001]    This application is a division of application Ser. No. 14/202,067, entitled “SEMICONDUCTOR DEVICE INCLUDING PASSIVATION LAYER ENCAPSULANT”, filed on Mar. 10, 2014, which is a continuation-in-part of application Ser. No. 13/873,801, entitled “STRUCTURES AND METHODS TO REDUCE MAXIMUM CURRENT DENSITY IN A SOLDER BALL”, filed on Apr. 30, 2013, now Pat. No. 8,674,506, which is a division of application Ser. No. 12/640,752, entitled “STRUCTURES AND METHODS TO REDUCE MAXIMUM CURRENT DENSITY IN A SOLDER BALL”, filed on Dec. 17, 2009, now Pat. No. 8,446,006, and which the entire disclosures of all above-reference applications are hereby being incorporated by reference. 
     
    
     BACKGROUND 
       [0002]    Conventional far back-end-of-line (FBEOL) processes for fabricating smaller scaled semiconductor devices (e.g., 32 nm and 22 nm) use aluminum pads that support a controlled collapse chip connection (C4) element and the corresponding underbump metallurgy (UBM). As dimensions of features (e.g., pads, wires, interconnects, vias, etc.) continue to shrink to create smaller devices, the maximum allowable current density decreases rapidly due to element electromigration (EM) effects. This crowding of current associated with the C4 and the aluminum pad and/or via structures often results in EM void formation, which can lead to increased resistance that negatively affects the performance of the semiconductor device 
       SUMMARY 
       [0003]    According to at least one embodiment, a method of fabricating a semiconductor device includes forming a passivation layer on a least one capping layer of the semiconductor device, and forming an encapsulant layer on the passivation layer. The method further includes patterning the encapsulant layer to expose a portion of the passivation layer and forming a final via opening in the passivation layer. A conductive material is deposited in the final via opening. The method further includes planarizing the conductive material until reaching a remaining portion of the encapsulant layer such that the conductive material is flush with the encapsulant layer and the passivation layer is preserved. 
         [0004]    According to another embodiment, a method of fabricating a semiconductor device includes forming a passivation layer on a least one capping layer of the semiconductor device, and forming an encapsulant layer on the passivation layer. The method further includes patterning the encapsulant layer to expose a portion of the passivation layer and forming a final via opening in the passivation layer. A conductive material is deposited in the final via opening. The method further includes planarizing the conductive material until reaching a remaining portion of the encapsulant layer such that the conductive material is flush with the encapsulant layer and the passivation layer is preserved. 
         [0005]    According to another embodiment, a semiconductor device comprises a passivation layer formed on at least one capping layer of the semiconductor device. An encapsulant layer is formed on the passivation layer, and a final via opening is formed in the passivation layer. A conductive material is deposited in the final via opening. The conductive material is flush with an upper surface of the encapsulant layer. The passivation layer has at least one preserved surface that is disposed against the encapsulant layer. The at least one preserved surface excluding at least one etched deformity. 
         [0006]    Additional features are realized through the techniques of the present invention. Other embodiments are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the features, refer to the description and to the drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]    The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing features are apparent from the following detailed description taken in conjunction with the accompanying drawings in which: 
           [0008]      FIG. 1  is a cross-sectional view of a starting substrate including a film cap formed on contact pads disposed in a dielectric layer, and capping layers formed on an upper surface of the film cap; 
           [0009]      FIG. 2  illustrates the substrate of  FIG. 1  following a first etching process that forms terminal via openings in the capping layers to expose an upper surface of the film cap; 
           [0010]      FIG. 3  illustrates the substrate of  FIG. 2  after depositing a passivation layer on an upper surface of the capping layer and in the terminal via openings; 
           [0011]      FIG. 4  illustrates the substrate of  FIG. 3  after forming an encapsulant layer on an upper surface of the passivation layer; 
           [0012]      FIG. 5  illustrates the substrate of  FIG. 4  after patterning the encapsulant layer to expose a portion of the underlying passivation layer; 
           [0013]      FIG. 6  illustrates the substrate of  FIG. 5  following a second etching process that forms a first via opening in the passivation layer and that removes the passivation layer material from the terminal via openings; 
           [0014]      FIG. 7  illustrates the substrate of  FIG. 6  following a third etching process that etches through the film cap and stops on the contact pads; 
           [0015]      FIG. 8  illustrates the substrate of  FIG. 7  after depositing a conductive liner that conforms to an upper surface of the encapsulant layer and to the surfaces of the passivation layer, capping layers and contact pads defined by the final via opening and the terminal via openings, respectively; 
           [0016]      FIG. 9  illustrates the substrate of  FIG. 8  after depositing a conductive material that fills the final via opening and the terminal via openings, and that covers the uppers surfaces of the passivation layer and the encapsulant layer; and 
           [0017]      FIG. 10  illustrates the substrate of  FIG. 9  following a planarization process that planarizes the conductive material and stops on the encapsulant layer. 
       
    
    
     DETAILED DESCRIPTION 
       [0018]    With reference now to  FIG. 1 , a starting substrate  100  of is illustrated according to an exemplary embodiment. The starting substrate  100  includes a dielectric layer  102 , a film cap  104 , and one or more capping layers  106 . The dielectric layer  102  is formed from a dielectric material including, but not limited to, doped silicon carbide, silicon nitride, low-k materials, TEOS, FTEOS, etc. According to at least one exemplary embodiment, a contact pad  108  is disposed in dielectric layer  104 . The contact pad  108  is formed from any suitable conducting material including, but not limited to, copper, copper alloy, aluminum, etc. The contact pad  108  is formed in the dielectric layer  102  using one or more conventional semiconductor processing techniques, such as, for example, photolithography and reactive ion etch (RIE), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), and atomic layer deposition (ALD). According to at least one embodiment, an electrically conductive contact liner  109  is interposed between a respective contact pad  108  and the dielectric layer  102 . The contact liner  109  is formed from one or more materials including, but not limited to, tantalum nitride (TaN), cobalt (Co), cobalt manganese (CoMn), titanium (Ti), titanium tungsten (TiW) and ruthenium (Ru). Various methods for depositing the contact liner  109  may be used including, but not limited to, plasma sputtering, evaporation, ALD and CVD. 
         [0019]    The film cap  104  is formed on the dielectric layer  102  and contact pad  108 . In embodiments, the film cap  104  is composed of silicon nitride (SiN x ) or a well-known composition referred to as NBLoK (e.g., SiC(N,H), or SN x C y H z ) deposited using conventional processes such as CVD, PECVD, ALD, etc. The film cap  104  may have any desired thickness (e.g., depth). The invention is not limited to the exemplary materials and processes described herein, and other materials and/or processes may be used to form the film cap  104  within the scope of the invention. 
         [0020]    According to at least one exemplary embodiment, the capping layers  106  include a first capping layer  110  and a second capping layer  112 . The first capping layer  110  is formed on the film cap  104  and is formed from, for example, silicon oxide (SiO x ). It appreciated, however, that other oxide materials may be used to form the first capping layer  110 . The first capping layer  110  is deposited using various methods including, but not limited to, CVD, PECVD, ALD, etc. The first capping layer  110  has various thicknesses according to the desired application of the semiconductor device. 
         [0021]    The second capping layer  112  is formed on the first capping layer  110 , and is formed from, for example, SiN x . Accordingly, the first capping layer  110  is interposed between the film cap  104  and the second capping layer  112 . Although SiN x  is an exemplary material for forming the second capping layer  112 , it is appreciated that other nitride materials may be used. The second capping layer  112  is deposited using various methods including, but not limited to, CVD, PECVD, ALD, etc. The second capping layer  112  has various thicknesses according to the desired application of the semiconductor device. 
         [0022]    Referring to  FIG. 2 , one or more via openings  114  (e.g., terminal via openings) are formed in the first capping layer  110  and the second capping layer  112 . The via openings  114  may be formed using a RIE process, for example, that is selective to the material (e.g., nitride) of the film cap  104 . In this regard, the via openings  114  are etched through the first and second capping layers  110 ,  112  and stop on the film cap  104 . 
         [0023]    Turning to  FIG. 3 , a passivation layer  116  is formed on the second capping layer  112  and fills the via openings  114 . According to at least one embodiment, the passivation layer  116  is composed of photosensitive polyimide (PSPI) and is deposited using conventional processes such, for example, as spin coating. The passivation layer  116  may be cured (e.g., baked) in order to toughen the passivation layer  116  (i.e., the PSPI), as understood by those ordinarily skilled in the art. The passivation layer  116  may have any desired thickness (e.g., depth). The invention is not limited to the exemplary materials and processes described herein, and other materials and/or processes may be used to form the passivation layer  116  within the scope of the invention, such as curtain coatings of other polymer passivation materials. 
         [0024]    Referring now to  FIG. 4 , an encapsulant layer  118  is formed on an upper portion of the passivation layer  116 . The encapsulant layer  118  is formed from, for example, silicon nitride (SiN x ) and is deposited according to various deposition methods including, but not limited to, CVD, PECVD and ALD. The encapsulant layer  118  has a thickness of, for example, approximately 1000 angstroms (A), and is configured to protect the passivation layer  116  during one or more subsequent process (e.g., chemical mechanical planarization), as described in greater detail below. According to at least one exemplary embodiment, the thickness of the encapsulant layer  118  is greater than a thickness of the film cap  104 . 
         [0025]    Turning now to  FIG. 5 , the encapsulant layer  118  is patterned to form an opening  120  that exposes a portion of the underlying passivation layer  116 . According to an embodiment, a conventional lithograph and RIE technique is used to form the opening  120  when the encapsulant layer  118  is thick, e.g., approximately  1000  A or greater. 
         [0026]    According to another embodiment, a laser-masking ablation process is used to form the opening  120  when the encapsulant layer  118  is thin, e.g., approximately  500  A. In this regard, a patterned mask (not shown) formed from, for example, aluminum quartz, is interposed between a laser ablation tool and the encapsulant layer  118 . The mask is patterned according to a desired patterning (e.g., opening  120 ) to be formed in the encapsulant layer  118 . High energy pulses are generated by the laser ablation tools, and are delivered to the encapsulant layer  118  via the patterning of the mask. The pulsed energy heats and ablates the encapsulant layer  118 . Accordingly, the desired pattern is formed in the encapsulation layer  118 , thereby exposing the underlying passivation layer  116 . The energy pulses are generated at wavelength of, for example, 308 nanometers (nm) UV energy, and include a range of fluences from approximately 0.1 to approximately 2.0 joules per square centimeter. The pulses have a duration ranging, for example, from approximately 15 nanoseconds (ns) to approximately 25 ns. Although an exemplary wavelength of 308 nm is described above, it is appreciated that the wavelength of the UV pulses includes all wavelengths produced by an excimer laser (i.e., exciplex laser) without limitation. For example, the UV energy pulses may range from approximately 126 nm to approximately 351 nm. 
         [0027]    Turning to  FIG. 6 , a first via etching process is performed which forms at least one final via (FV) opening  122  in the passivation layer  116 . The first via etching process also removes the passivation layer  116  deposited in the via openings  114 . The first via etch process is selective to the cap film  104  and the encapsulant layer  118 . In this regard, a portion of the passivation layer  116  located beneath the encapsulant layer  118  is preserved (i.e., not etched) and a portion of the cap film  104  is exposed by a respective via opening  114 . The first via etching process may be performed according to either a conventional lithograph and subsequent RIE process, or a laser-masking ablation process similar to the processes discussed above. If laser ablation process is used and the encapsulant layer is thin, e.g., less than 1000 A then the buffer regions  123  are created such that the laser beam used to create the via by ablating the passivation material doesn&#39;t cause localized heating and subsequent damage of the thin encapsulant close to the via opening. According to one embodiment, opposing walls of the final via opening  122  formed according to the laser-masking ablation process have an angle being less than 90 degrees with respect to the at least one capping layer, and the opposing walls are uniform with respect to one another. 
         [0028]    According to at least one embodiment, opposing buffer regions  123  are formed in the passivation layer  116  as further illustrated in  FIG. 6 . The buffer regions  123  are formed, for example, by performing a laser-masking ablation process that uses a mask (e.g., an aluminum quartz mask). The mask (not shown) includes a pattern configured to form a desired FV opening (e.g., FV opening  122 ) in the passivation layer  116 . The mask may include a solid portion that covers a portion of the passivation layer  116  extending between respective patterned edges of the encapsulant layer  118  to the edge of the FV opening  122 . The covered portion, therefore, defines the formed buffer regions  123 . The buffer regions  123  may have a length ranging from, for example, approximately 2 nm to approximately 3 nm. 
         [0029]    Referring now to  FIG. 7 , a second via etching process is performed which removes the cap film  104  exposed by a respective via openings  104 . Accordingly, a portion of the underlying contact pad  108  is exposed. The second via etching process is performed, for example, using a RIE process that is selective to the passivation layer  112  and the capping layers  106 . The film cap  104  and the encapsulant layer  118  are simultaneously etched. However, the encapsulant layer has thickness that is greater than the thickness of the film cap  104 . In this regard, the film cap  104  is removed while the thickness of the encapsulant layer  118  remains with a reduced thickness. 
         [0030]    Turning to  FIG. 8 , an electrically conductive liner  124  is formed on the surfaces of the encapsulant layer  118  and passivation layer  116 . The conductive liner  124  also conforms to exposed surfaces of the capping layer  106  and the contact pads  108  defined by the FV opening  122  and the via openings  114 , respectively. The conductive liner  124  is formed from one or more materials including, but not limited to, tantalum nitride (TaN), cobalt (Co), cobalt manganese (CoMn), titanium (Ti), titanium tungsten (TiW) and ruthenium (Ru). Various methods for depositing the conductive liner  124  may be used including, but not limited to, plasma sputtering, evaporation, ALD and CVD. 
         [0031]    Referring to  FIG. 9 , a conductive material  126  is deposited on the conductive liner  124 . According to at least one embodiment, the conductive material  126  fills the via openings  114  and FV opening  122 , and covers the upper surfaces of the passivation layer  116  and encapsulant layer  118 . The conductive material  126  is formed using various processes including, for example, electroplating, and is annealed as understood by those ordinarily skilled in the art. According to one exemplary embodiment, the conductive material  126  is an electroplating material such as, for example, copper (Cu). It is appreciated, however, that the conductive material may comprise other conductive materials including, but not limited to, copper manganese (CuMn), gold (Au) and tin (Sn). 
         [0032]    Turning now to  FIG. 10 , excess conductive material  126  is planarized using a chemical planarization (CMP) process, for example. The encapsulant layer  118  acts as an etch stop (e.g., a CMP stop layer) that also protects the underlying passivation layer  116  from being recessed during the CMP process. That is, the CMP process stops on the encapsulant layer  118  such that the upper surface of the conductive material  126  is formed flush with the upper surface of the encapsulant layer  118 , while the underlying passivation layer  116  is unaffected and preserved. As further illustrated in  FIG. 10 , the passivation layer has a preserved surface  128  that is disposed against the encapsulant layer  118 . Since the encapsulant layer  118  protects the passivation layer  116  from the CMP process, the at least one preserved surface excludes at least one etched deformity which can result when being exposed to the CMP result. 
         [0033]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one more other features, integers, steps, operations, element components, and/or groups thereof. 
         [0034]    The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the inventive teachings and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated. 
         [0035]    There may be many variations to this diagram or the operations described therein without departing from the spirit of the invention. For instance, the operations may be performed in a differing order or operations may be added, deleted or modified. All of these variations are considered a part of the claimed invention. 
         [0036]    While various embodiments have been described, it will be understood that those skilled in the art, both now and in the future, may make various modifications which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.