Abstract:
A semiconductor device with a low-k material in close proximity thereto and its fabrication method. The device includes a gate electrode overlying a substrate. An electrically conductive plug is provided immediately adjacent to the gate electrode and making electrical contact to the device. A low-k dielectric material is disposed in the space between the gate electrode and the electrically conductive plug whereby reducing the parasitic capacitance. Thus, higher density of devices can be formed without decreasing operating speed.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The invention relates to semiconductor manufacturing, and more particularly to a semiconductor device with a low-k (low dielectric constant) material in close proximity thereto and a method of manufacturing the same.  
         [0003]     2. Description of the Related Art  
         [0004]     Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Today&#39;s wafer fabrication plants are routinely producing devices having 0.18 μm and even 0.15 μm feature sizes, and tomorrow&#39;s plants will soon be producing devices with even smaller geometries.  
         [0005]     However, various problems are caused as a result of the reduction in size of the elements. For example, the shortening of the channel length achieves the effect of lowering the channel resistance on the one hand but, on the other, gives rise to the problem that a short-channel effect is brought about. Further, as a result of the reduction in size of the elements, the ratios of the various parasitic components become relatively high. For example, in the case of a MOS transistor, the junction capacitance of the source/drain is brought to such a high ratio that it affects the operating speed.  
         [0006]     An unrecognized problem is the increase of the parasitic capacitance between the gate electrode and the adjacent conductive plug used to connect the transistor, which however, will become a bottleneck in ultra-miniaturization of devices according to the present inventors&#39; investigation. In addition, the parasitic capacitance between two adjacent contact plugs also increases because of their close proximity.  
         [0007]     Considerable work has been done to reduce the junction capacitance of the source/drain, but has not addressed the problems associated with the parasitic capacitance between the gate electrode and the conductive plug or of that between adjacent plugs. For example, in U.S. Pat. No. 6,383,883, a method is taught using double implantation to reduce the junction capacitance of the source/drain. In U.S. Pat. No. 6,198,142, a metal oxide semiconductor transistor with minimal junction capacitance is described. Still another method for reducing junction capacitance is taught in U.S. Pat. No. 6,570,217, in which a cavity is provided in the portion of the silicon substrate which lies beneath the channel region of the MOS transistor.  
         [0008]     The present inventors recognize the need for reducing the parasitic capacitance between the gate electrode and the contact plug and that between two adjacent contact plugs to accommodate the ultra-miniaturization of devices. This becomes exceptionally important as the RC (resistance X capacitance) delay becomes increasingly critical in ultra deep sub-micron devices with feature lengths of 0.13 μm or beyond.  
       SUMMARY OF THE INVENTION  
       [0009]     A broad object of the invention is to provide a semiconductor device having an ultra deep sub-micron feature length and its method of fabrication.  
         [0010]     Another object of the invention is to provide an ultra deep sub-micron device and its method of fabrication whereby scaling issues of the parasitic capacitance between the gate and the contact plug are addressed.  
         [0011]     A further object of the invention is to provide an ultra deep sub-micron device and its method of fabrication whereby scaling issues of the parasitic capacitance between two adjacent contact plugs are addressed.  
         [0012]     To achieve the above and other objects, a low-k dielectric material is disposed in close proximity to the semiconductor device. Specifically, the low-k dielectric material is disposed between the gate electrode and the conductive plug or between two closely spaced conductive plugs to reduce the parasitic capacitance. Although low-k dielectric is commonly used between interconnects to reduce the RC delay, using it at the above positions is never suggested. At the present time, the insulating material for the above positions is silicon oxide or related silicate glasses such as borophosphosilicate (BPSG) with k value between 3.9-4.2.  
         [0013]     According to an aspect of the invention, there is provided a semiconductor device including: a substrate; a device having a gate electrode overlying the substrate; an electrically conductive plug immediately adjacent to the gate electrode and making electrical contact to the device; and a low-k dielectric material disposed in the space between the gate electrode and the electrically conductive plug.  
         [0014]     According to another aspect of the invention, there is provided a semiconductor device including: a substrate; two closely spaced devices on the substrate, isolated with an isolation element therebetween; two adjacent electrically conductive plugs disposed between the two closely spaced devices and respectively making electrical contact to each device; and a low-k dielectric material disposed in the space between the two adjacent contact plugs.  
         [0015]     According to a further aspect of the invention, there is provided a method of manufacturing a semiconductor device, including the steps of: providing a device having a gate electrode overlying a substrate; forming a low-k dielectric layer in close proximity to the device; forming a contact opening adjacent to the gate electrode through the low-k dielectric layer; and forming an electrically conductive plug in the opening to make electrical contact to the device.  
         [0016]     According to a still further aspect of the invention, there is provided a method of manufacturing a semiconductor device, including the steps of: providing two closely spaced devices on a substrate, isolated with an isolation element therebetween; forming a low-k dielectric layer overlying the two closely spaced devices; and forming two adjacent electrically conductive plugs through the low-k dielectric layer between the two closely spaced devices to respectively make electrical contact to each of the devices.  
     
    
     DESCRIPTION OF THE DRAWINGS  
       [0017]     For a better understanding of the present invention, reference is made to a detailed description to be read in conjunction with the accompanying drawings, in which:  
         [0018]      FIG. 1  is a cross-section showing a semiconductor device according to the first embodiment of the invention, in which a low-k dielectric insulator is disposed between the gate electrode and the adjacent contact plug to reduce the parasitic capacitance; and  
         [0019]      FIG. 2  is a cross-section showing a semiconductor device according to the second embodiment of the invention, in which a low-k dielectric insulator is disposed between the two adjacent contact plugs to reduce the parasitic capacitance. 
     
    
     REFERENCE NUMERALS IN THE DRAWINGS  
       [0020]    
       
         
           
               100  substrate  
               110  shallow trench isolation  
               120 ,  120   a ,  120   b  MOS transistor  
               122  gate electrode  
               124  source/drain region  
               126  gate dielectric  
               128  spacer  
               130  buffer layer  
               140  low-k dielectric layer  
               150 ,  150   a ,  150   b  contact opening  
               160 ,  160   a ,  160   b  electrically conductive plug  
              d 1  spacing between gate  122  and plug  160   
              d 2  spacing between plug  160   a  and plug  160   b    
           
         
       
     
       DETAILED DESCRIPTION OF THE INVENTION  
       [0033]     In this specification, expressions such as “overlying the substrate”, “above the layer”, or “on the film” simply denote a relative positional relationship with respect to the surface of the base layer, regardless of the existence of intermediate layers. Accordingly, these expressions may indicate not only the direct contact of layers, but also, a non-contact state of one or more laminated layers. By use of the term “low dielectric constant” or “low k” herein, is meant a dielectric constant (k value) which is less than the dielectric constant of a conventional silicon oxide. Preferably, the dielectric constant of the low k is less than about 3.3 and more preferably less than about 2.8.  
         [heading-0034]     First Embodiment  
         [0035]     A preferred embodiment of the present invention is now described in detail with reference to  FIG. 1 .  
         [0036]      FIG. 1  is a schematic cross-section showing a semiconductor substrate  100  having a field effect MOS transistor  120  with a low-k dielectric layer  140  in close proximity thereto. The preferred substrate  100  is composed of P type single-crystal silicon with a &lt;100&gt; crystallographic orientation, and may contains defective semiconductor lattice in the channel region of the MOS transistor  120  to increase drive current. For example, a SiGe epitaxial layer may be grown for mobility enhancement.  
         [0037]     The MOS transistor  120  is formed in an active device area isolated by isolation elements such as the well-known shallow trench isolation (STI) structures  110  as shown. The MOS transistor includes a gate electrode  122  overlying the substrate with a gate dielectric  126  interposed therebetween, and a pair of source/drain regions  124  formed in the substrate oppositely adjacent to the gate electrode  126 . The gate electrode  122  preferably consists of doped polysilicon and refractory metal silicide, and insulating sidewall spacers  128  may be formed on the sidewalls of the gate electrode  122 . The process details for forming such a field effect transistor are well known and will not be described here; however, since the present invention is particularly advantageous for devices having ultra deep sub-micron feature lengths, preferred size features of the MOS transistor  120  will now be described. The height of the gate electrode  122  is preferably less than about 3,000 Å end more preferably less than about 2,500 Å. The width of the gate electrode  122  is preferably less than 0.1 μm. The effective thickness of the gate dielectric  126  is preferably equivalent to a conventional layer of silicon oxide having a thickness of about 25 Å or less. The gate dielectric  126  may be comprised of conventional silicon oxide or high-k dielectrics such as Y 2 O 3 , La 2 O 3 , Al 2 O 3 , ZnO 2 , HfO 2 , or combinations of silicon oxide and high-k dielectrics. The width the isolation element  110  is less than about 1500 Å 
         [0038]     Next, as a main feature and a key aspect of the present invention, a low-k dielectric layer  140  is formed in close proximity to the MOS transistor  120 . Preferably, the low-k dielectric layer is present within 200 nm, and more preferably 150 nm from the gate electrode  122  and the source/drain regions  124 . The use of low-k dielectric is not new in semiconductor manufacturing, but forming a low-k dielectric so close to a MOS transistor is never suggested. This low-k material  140  serves to reduce the parasitic capacitance between the gate electrode  122  and the adjacent conductive plug  160 , thereby reducing the RC delay and resulting in an improved performance of the MOS transistor. Accordingly, the low-k material  140  should at least substantially fill the space (&gt;70%) between the gate electrode  122  and the conductive plug  160 . Typically and preferably, the low-k dielectric layer  140  is blanketly deposited overlying the entire substrate surface including the MOS transistor  120  as a pre-metal dielectric (PMD), and then a through plug is formed down to the source/drain regions so as to be embedded in the low-k dielectric.  
         [0039]     The low-k material  140  can be a carbon-containing material or a carbon/oxygen-containing material. Suitable low-k materials include but are not limited to inorganic CVD (Chemical Vapor Deposition) materials such as fluorosilicate glass (FSG), Black Diamond (trade name, carbon-doped silica developed by Applied Materials); organic spin-on materials such as polyimide organic polymer, polyarylene ether organic polymer commonly known as PAE-2™ and FLARE™, parylene organic polymer and fluorinated analogs thereof; spin-on-glass (SOG) materials such as hydrogen silsesquioxane (HSQ), carbon bonded hydrocarbon silsesquioxane, and carbon bonded fluorocarbon silsesquioxane. For example, the FSG can be deposited by low pressure CVD using TEOS (tetraethyl-ortho-silicate) and by introducing a fluorine-containing dopant gas such as carbon tetrafluoride (CF 4 ). The low-k dielectric layer  140  is deposited to a thickness between about 3,000-12,000 Å and preferably has a planar upper surface.  
         [0040]     In a more preferred embodiment, a conformal buffer layer  130  is deposited lining the substrate surface and the MOS transistor  120  before forming the low-k dielectric layer  140 . The buffer layer is preferably a silicon/nitrogen-containing dielectric having a thickness between about 200-2000 Å. The buffer layer  130  serves several functions: (1) it provides a diffusion barrier against out-diffusion of the dopants that may be present in the low-k dielectric layer; (2) it improves adhesion between the underlying substrate and the low-k dielectric layer; and (3) it serves as an etch stop when etching the contact opening in the low-k dielectric layer. When serving as a diffusion barrier, the material is preferably chosen from SiOC, SiNC, or Si-rich oxide. When serving as an adhesion layer, the material is preferably chosen from SiOC, SiNC, SiC, or Si-rich oxide. When serving as an etch stop layer, the material is preferably chosen from SiON, SiN, or Si-rich oxide.  
         [0041]     Following the formation of the low-k dielectric layer  140 , contact openings  150  are defined down to the source/drain regions  124  on the substrate using known lithography technology and anisotropic etching methods. When etching the contact openings  150 , the buffer layer  130 , if any, can serve as an etch stop to avoid damage to the underlying device. Although the aspect ratio of the contact opening  130  can vary depending on the design rule, the present invention is particularly suitable for those not less than 5. Typically and preferably, the contact opening  150  has a width between about 100 and 1,000 Å.  
         [0042]     Subsequently, conductive plugs  160  are formed in the contact openings  150  to electrically connect to the source/drain regions  124  of the MOS transistor  120 . The conductive plugs  160  can be formed of electrically conductive materials including but not limited to metal, metal compound, metal alloy, doped polysilicon, polycides, although copper and copper alloys are particularly preferred. It can be formed by overfilling the contact opening and removing the conductive material outside of the contact opening by etch back or chemical mechanical polishing (CMP).  
         [0043]     For example, a conformal metal barrier layer (not shown) such as tantalum, titanium, tungsten, tantalum nitride, titanium nitride, or tungsten nitride is deposited overlying the substrate surface including the contact openings  150 , and then an electrically conductive material  160  is deposited on the barrier metal by chemical vapor deposition (CVD), physical vapor deposition (PVD), or electrochemical deposition (ECD) to substantially fill the contact openings  150 . Thereafter, the metal barrier layer and the conductive material  160  are etched back or polished by use of the CMP until the low-k dielectric layer  140  is exposed, thus forming the conductive plugs  160  embedded in the contact openings  150 . Alternatively, the above metal barrier layer can be replaced by a dielectric barrier (not shown) provided only on the sidewalls of the contact openings  150 . It can be formed by depositing a substantially conformal dielectric layer over the entire substrate surface followed by anisotropic etch back. Preferable materials for the dielectric barrier include silicon oxide, silicon nitride, carbon-doped silicon oxide, carbon-doped silicon nitride, carbon/nitride doped silicon oxide, silicon carbide, or combinations thereof.  
         [0044]     As shown in  FIG. 1 , the parasitic capacitance between the gate electrode  122  and the conductive plug  160  is substantially reduced by the low-k dielectric layer  140 . In future products having minimum feature sizes of 0.13 μm or even smaller, the spacing d 1  between the gate electrode  122  and the conductive plug  160  will also decrease to less than about 2,000 Å. Since the parasitic capacitance (Cp) varies inversely with spacing (d), when d decreases, the Cp increases. With the present invention, by reducing the dielectric constant (k) of the dielectric layer  140 , the spacing d 1  can be further reduced without increasing the parasitic capacitance. For example, if the dielectric constant k is reduced by 50% (e.g. k is reduced from 4 to 2), then the spacing d 1  can also be decreased by 50% without increasing Cp.  
         [heading-0045]     Second Embodiment  
         [0046]      FIG. 2  shows another embodiment of the invention, in which like numbers from the first described embodiment are utilized where appropriate. Two closely spaced field effect MOS transistors  120   a ,  120   b  are formed on a semiconductor substrate using known processes, isolated by a STI  110  therebetween. After a conformal buffer layer  130  (optional) and a blanket low-k dielectric layer  140  as in the first embodiment are formed, two contact openings  150   a ,  150   b  are defined through the low-k dielectric layer  140  between the two transistors to respectively expose one of the source/drain regions  124  of each transistor. Thereafter, electrically conductive materials are embedded in the contact openings  150   a ,  150   b , thereby forming two adjacent conductive plugs  160   a ,  160   b  to respectively make electrical contact to each of the MOS transistors  120   a , and  120   b.    
         [0047]     As shown in  FIG. 2 , the low-k dielectric material  140  reduces the parasitic capacitance between the two adjacent conductive plugs  160   a ,  160   b . In future products having minimum feature sizes of 0.13 μm or even smaller, the spacing d 2  between adjacent conductive plugs of closely spaced transistors will also decrease to less than about 2,000 Å. By forming a low-k dielectric material between the closely spaced conductive plugs, the spacing d 2  can be decreased without increasing the parasitic capacitance.  
         [0048]     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.