Abstract:
SRAM cell and method for fabricating the same, the SRAM cell including a first local interconnection connected between first terminals of the first access transistor, the first load transistor, and the first drive transistor, and gates of the second load transistor, and the second drive transistor electrically, and a second local interconnection connected between first terminals of the second access transistor, the second load transistor, and the second drive transistor, and gates of the first load transistor, and the first drive transistor electrically, thereby reducing an area of the SRAM cell.

Description:
[0001]    This application claims the benefit of the Korean Application No. P2002-23704 filed on Apr. 30, 2002, which is hereby incorporated by reference.  
         BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates to a semiconductor device, and more particularly, to an SRAM cell and a method for fabricating the same, which can reduce a cell size.  
           [0004]    2. Background of the Related Art  
           [0005]    In general, the SRAM (Static Random Access Memory) cell is provided with a flipflop circuit having two access transistors, two drive transistors, and two load transistors. FIG. 1 illustrates an equivalent circuit of a COMS type SRAM cell.  
           [0006]    Referring to FIG. 1, the COMS type SRAM cell has first, and second access transistors Q 1  and Q 2 , first and second driver transistors Q 3  and Q 4 , and first, and second load transistors Q 5  and Q 6 .  
           [0007]    That is, the SRAM cell is provided with first, and second inverters connected between a power source terminal and a ground terminal in parallel each having a PMOS transistor Q 5  or Q 6 , and an NMOS transistor Q 3  or Q 4 , and a first access transistor Q 1  and a second access transistor Q 2  each having a source (or a drain) connected to output terminals of the first, and second inverters.  
           [0008]    A drain (or source) of the first access transistor Q 1  and a drain (or source) of the second access transistor Q 2  are connected to a first bitline BL and a second bitline /BL, respectively. Moreover, an input terminal of the first inverter is connected to an output terminal of the second inverter, and an input terminal of the second inverter is connected to an output terminal of the first inverter, to form a latch circuit.  
           [0009]    A related art CMOS type SRAM cell will be explained, with reference to the attached drawings. FIG. 2 illustrates a layout of a related art CMOS type SRAM cell, FIG. 3 illustrates a section across a line II-II in FIG. 2, and FIG. 4 illustrates a section across a line III-III in FIG. 2.  
           [0010]    Referring to FIGS.  2 ˜ 4 , there is a device isolating film  12  formed in a field region of a semiconductor substrate  11  having the field region and an active region defined thereon, and an n-well region  13  and a p-well region  14  are formed in a surface of the semiconductor substrate  11 .  
           [0011]    There is a gate electrode  16  formed in an active region over the semiconductor substrate  11  with a gate insulating film  15  inbetween, and there are insulating sidewalls  17  at both sides of the gate electrode  16 .  
           [0012]    There are source/drain regions  18  in a surface of the semiconductor substrate  11  on both sides of the gate electrode  16 , and a metal silicide film  19  on surfaces of the gate electrode  16  and the semiconductor substrate  11  having the source/drain regions  18  formed therein.  
           [0013]    There are contact holes so as to expose parts of surfaces of the source/drain regions  18  and the gate electrode  16 , and a nitride film  20 , a BPSG film  21 , and a PE-TEOS film  22  stacked in succession.  
           [0014]    There is a tungsten plug  24  inside of the contact hole with a barrier metal film  23  disposed inbetween, and metal interconnections  25  on the tungsten plug  24  and a PE-TEOS film  22  adjacent thereto.  
           [0015]    The metal interconnection  25  has a thickness of approx. 5000 Å for local interconnection of a Vcc line, a Vss line, impurity regions of transistors, and the gate electrode.  
           [0016]    Thus, since the thickness of the metal interconnection in the related art SRAM cell is greater than 5000 Å, a distance A between the n-well region  13  and the p-well region  14  is 0.70 μm (0.40/0.30), and the local metal interconnection  25  has a pitch B of 0.45 μm (L/S=0.22/0.23), to form an area of approx. 4.60 μm 2  in overall.  
           [0017]    However, the related art SRAM cell has the following problems.  
           [0018]    That is, because an area of the SRAM cell with 6-transistors has 4.60 μm 2  when a 0.18 μm technology is employed owing to the local metal interconnection and Vcc/Vss lines each having greater than 5000 Å thickness, there has been a limit in reducing a cell size.  
         SUMMARY OF THE INVENTION  
         [0019]    Accordingly, the present invention is directed to an SRAM cell and a method for fabricating the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.  
           [0020]    An object of the present invention is to provide an SRAM cell and a method for fabricating the same, which can reduce an area of an SRAM cell with 6-transistors when the 0.18 μm technology is employed.  
           [0021]    Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.  
           [0022]    To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the SRAM cell having first, and second access transistors, first, and second drive transistors, and first, and second load transistors on the same semiconductor substrate, includes a first local interconnection connected between first terminals of the first access transistor, the first load transistor, and the first drive transistor, and gates of the second load transistor, and the second drive transistor electrically, a second local interconnection connected between first terminals of the second access transistor, the second load transistor, and the second drive transistor, and gates of the first load transistor, and the first drive transistor electrically, an interlayer insulating film formed on an entire surface having contact holes exposing parts of second terminals of the first, and second access transistors, the first, and second load transistors, and first, and second drive transistors, and a metal interconnection connected between second terminals of the first, and second access transistors, first, and second load transistors, and first, and second drive transistors through the contact holes, electrically.  
           [0023]    In another aspect of the present invention, there is provided a method for fabricating an SRAM cell, in which first, and second access transistors, first, and second drive transistors, and first, and second load transistors are formed on the same semiconductor substrate, including the steps of forming a first interlayer insulating film on an entire surface of the semiconductor substrate, selectively removing the first interlayer insulating film to form first contact holes to expose parts of first terminals of the second access transistor, the second load transistor, and the second drive transistor, parts of gates of the first load transistor, and the first drive transistor, and parts of second terminals of the first, and second access transistors, first, and second load transistors, and first, and second drive transistors, forming a first conductive plug inside of the first contact hole with a first barrier metal film disposed inbetween, forming a local interconnection on the first conductive plug and the first interlayer insulating film adjacent to the first conductive plug, forming a second interlayer insulating film on an entire surface of the semiconductor substrate inclusive of the local interconnection, selectively removing the second interlayer insulating film to form second contact holes to expose parts of second terminals of the first, and second access transistors, first, and second load transistors, and first, and second drive transistors, forming a second conductive plug inside of the second contact hole with a barrier metal film disposed inbetween, and forming a metal interconnection on the second conductive plugs and the second interlayer insulating film adjacent to the second conductive plug.  
           [0024]    It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0025]    The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention:  
         [0026]    In the drawings:  
         [0027]    [0027]FIG. 1 illustrates an equivalent circuit of a related art COMS type SRAM cell;  
         [0028]    [0028]FIG. 2 illustrates a layout of a related art CMOS type SRAM cell;  
         [0029]    [0029]FIG. 3 illustrates a section of the SRAM across a line II-II in FIG. 2;  
         [0030]    [0030]FIG. 4 illustrates a section of the SRAM across a line III-III in FIG. 2;  
         [0031]    [0031]FIG. 5 illustrates a layout of a CMOS type SRAM cell in accordance with a preferred embodiment of the present invention;  
         [0032]    [0032]FIG. 6 illustrates a section of the SRAM across a line IV-IV in FIG. 5;  
         [0033]    [0033]FIG. 7 illustrates a section of the SRAM across a line VI-VI in FIG. 5;  
         [0034]    FIGS.  8 A˜ 8 L illustrate sections across a line VI-VI in FIG. 5 showing the steps of a method for fabricating an SRAM cell in accordance with a preferred embodiment of the present invention;  
         [0035]    FIGS.  9 A˜ 9 L illustrate sections across a line IV-IV in FIG. 5 showing the steps of a method for fabricating an SRAM cell in accordance with a preferred embodiment of the present invention; and  
         [0036]    [0036]FIG. 10 illustrates a section showing a method for fabricating an SRAM cell in accordance with another preferred embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0037]    Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. FIG. 5 illustrates a layout of a CMOS type SRAM cell in accordance with a preferred embodiment of the present invention, FIG. 6 illustrates a section of the SRAM across a line IV-IV in FIG.  5 , and FIG. 7 illustrates a section of the SRAM across a line VI-VI in FIG. 5.  
         [0038]    Referring to FIGS.  5 ˜ 7 , there is a device isolating film  32  in a field region of a semiconductor substrate.  31  having a field region, and first, and second active regions defined thereon, and an n-well region  33  and a p-well region  34  are formed in a surface of the semiconductor substrate  31 . A region the n-well region  33  formed therein is the first active region, and a region the p-well region  34  formed therein is a second active region. The device isolating film  32  of an STI (Shallow Trench Isolation) structure has a trench depth of approx. 3500 Å from the surface of the semiconductor substrate  31 .  
         [0039]    There is a gate electrode  36  over the semiconductor substrate  31  with a gate insulating film  35  disposed inbetween, and insulating film sidewalls  38  at both sides of the gate electrode  36 . The gate insulating film  35  may have different thickness between a region a PMOS transistor is formed therein, and a region an NMOS transistor is formed therein, with a thin region of being approx. 29 Å thickness and a thick region of being approx. 64 Å thickness. The gate electrode  36  is formed of polysilicon to a thickness of approx. 2500 Å.  
         [0040]    There are source/drain regions  39  in a surface of the semiconductor substrate  31  on both sides of the gate electrode  36 , and a metal silicide film  40  formed on surfaces of the gate electrode  36  and the semiconductor substrate  31  having the source/drain regions  39  formed therein. The metal silicide film  40  is formed of a refractory metal (for an example, Co/Ti).  
         [0041]    There are first contact holes to expose surfaces of the source/drain regions  39  and the gate electrode  36 , and a first interlayer insulating film  41 . The first interlayer insulating film  41  has a nitride film  41  a with approx. 300 Å thickness, a BPSG film  41   b  with approx. 5500 Å thickness, and a PE-TEOS film  41   c  with approx. 1000 Å thickness, stacked in succession.  
         [0042]    The first contact hole exposes parts of surfaces of source/drain regions of the first load transistor Q 5 , the first drive transistor Q 3 , and the first access transistor Q 1 , and parts of surfaces of gate electrodes of the second load transistor Q 6  and the second drive transistor Q 4 , which are connected in parallel.  
         [0043]    The first contact hole also exposes parts of surfaces of source/drain regions of the second load transistor Q 6 , the second drive transistor Q 4 , and the second access transistor Q 2 , and parts of surfaces of gate electrodes of the first load transistor Q 5  and the first drive transistor Q 3 , which are connected in parallel.  
         [0044]    There is a first tungsten plug  44  inside of the first contact hole formed to a thickness of approx. 4000 Å, with a first barrier metal film  43  disposed inbetween, and there is a local interconnection metal line  45  formed to a thickness of approx. 300 Å on the first tungsten plug  44  and the first interlayer insulating film  41  adjacent thereto. The local interconnection metal line  45  may be a stack of metal films of low resistances, such as TiN/Ti, with a thickness of the Ti being approx. 200 Å, and a thickness of the TiN of being approx. 100 Å. L/S (Line/Space) of the local interconnection metal line is 0.20/0.19 μm.  
         [0045]    There is a second contact hole to expose parts of source/drain regions of the first, and second access transistors Q 1  and Q 2  and first, and second driver transistors Q 1  and Q 2 , and there is a second interlayer insulating film  46  formed to a thickness of approx. 4000 Å on an entire surface of the semiconductor substrate  31  inclusive of the local interconnection metal line. The second interlayer insulating film  46  is formed of PE-TEOS, and the second contact hole has an approx. 0.23 μm width.  
         [0046]    There is a second tungsten plug  49  inside of the second contact hole with a second barrier metal film  48  disposed inbetween, and there are metal lines  50  of Vcc and Vss on the second tungsten plug  49  and the second interlayer insulating film  46  adjacent thereto. The metal line  50  has a stack of Ti/Al/Ti/TiN films formed to thickness of 100/4500/50/600 Å.  
         [0047]    In the meantime, in the SRAM cell of the present invention, the related art metal interconnection  25  is not used as the local interconnection, but local interconnection  45  is formed to a thickness of approx. 300 Å at a pitch B of 0.39 μm (L/S=0.20/0.19 μm), which permits to reduce a distance A between the active regions down to 0.55 μm, to have an area of approx. 3.63 μm 2  in total.  
         [0048]    FIGS.  8 A˜ 8 L illustrate sections across a line VI-VI in FIG. 5 showing the steps of a method for fabricating an SRAM cell in accordance with a preferred embodiment of the present invention, and FIGS.  9 A˜ 9 L illustrate sections across a line IV-IV in FIG. 5 showing the steps of a method for fabricating an SRAM cell in accordance with a preferred embodiment of the present invention.  
         [0049]    Referring to FIGS. 8A and 9A, a device isolating film  32  is formed in a field region of a semiconductor substrate  31  having an active region and the field region defined thereon.  
         [0050]    Though not shown, the device isolating film  32  is formed by the following method. A pad oxide film (approx. 140 Å) and a nitride film (approx. 1000 Å) are formed on the semiconductor substrate  31  in succession, and, after photoresist is coated on the nitride film, the photoresist is patterned by exposure and development, to define a field region and an active region.  
         [0051]    Then, the nitride film and the pad oxide film are removed selectively by using the patterned photoresist as a mask, and the field region of the semiconductor substrate is removed selectively by using the nitride film as a mask, to form a trench to a depth of approx. 3500 Å.  
         [0052]    In order to compensate the damage given to the semiconductor substrate  31  occurred in the trench formation, the semiconductor substrate  31  is oxidized, to form an oxide film on a surface of the trench (approx. 100 Å).  
         [0053]    Then, a gap-fill HDP oxide film is formed on an entire surface of the semiconductor substrate  31  inclusive of the trench to a thickness of approx. 6000 Å, and annealed for 30 minutes at approx. 1000° C. temperature, and an entire surface of the semiconductor substrate  31  are subjected to CMP (Chemical Mechanical Polishing) taking the pad oxide film as an end point, to form a device isolating film  32  inside of the trench. Then, the semiconductor substrate  31  is washed, to remove the pad oxide film.  
         [0054]    Referring to FIGS. 8B and 9B, n-type and p-type impurity ions are selectively injected into the semiconductor substrate  31 , to form an n-well region  33  and a p-well region  34  in a surface of the semiconductor substrate  31 , respectively. A method for forming the n-well region  33  and the p-well region  34  will be explained in detail.  
         [0055]    A region of the semiconductor substrate  31  the n-well is to be formed therein is exposed by lithography, and phosphor P is injected to the exposed region for three times, i.e., at energies of 700 KeV, 250 KeV, and 140 KeV, successively by using a resist film (not shown) as a mask to form the n-well region  33 .  
         [0056]    Then, arsenic As is injected to the n-well region  33  at an energy of approx. 140 KeV for adjusting a threshold voltage of the n-well region  33 .  
         [0057]    Then, after the resist film is removed, a region the p-well is to be formed therein is exposed by lithography, and boron B is injected to the exposed region for three times, i.e., at energies of 350 KeV, 150 KeV, and 8 KeV, successively by using a resist film (not shown) as a mask, to form the p-well region  34 . Then, boron B is injected to the p-well region  34  at an energy of approx. 20 KeV for adjusting a threshold voltage of the p-well region  34 .  
         [0058]    Referring to FIGS. 8C and 9C, the semiconductor substrate  31  is annealed, to activate the impurity ions injected into the n-well region  33  and the p-well region  34 , and a gate insulating film  35  and a gate polysilicon film are formed on an entire surface of the semiconductor substrate  31  in succession.  
         [0059]    The gate insulating film  35  may be formed as a dual gate insulating film in which a thickness of a region therein an NMOS transistor is to be formed therein and a thickness of a region a PMOS transistor is to be formed therein are different, with a thin region formed to a thickness of approx. 29 Å and a thick region formed to a thickness of approx. 59 Å. The polysilicon film has approx. 2500 Å.  
         [0060]    Then, a photo- and etching process is carried out, to remove the polysilicon film, and the gate insulating film  35  selectively, to form a gate electrode  36 .  
         [0061]    Referring to FIGS. 8D and 9D, n-type and p-type impurity ions are selectively injected into the semiconductor substrate  31  lightly by using the gate electrode  36  as a mask, to form LDD (Lightly Doped Drain) regions  37  in a surface of the semiconductor substrate  31  on both sides of the gate electrode  36 .  
         [0062]    Referring to FIGS. 8E and 9E, an insulating film is formed on an entire surface inclusive of the gate electrode  36 , and etched back, to form insulating sidewalls  38  at both sides of the gate electrode  36 , and n-type and p-type impurity ions are heavily injected into an entire surface of the semiconductor substrate  31  selectively by using the insulating sidewalls  38  and the gate electrode  36  as a mask, to form source/drain regions  39  in the surface of the semiconductor substrate  31 .  
         [0063]    In the meantime, halo ions P or BF 2  may be injected into the semiconductor substrate  31 , with an angle of the injection tilted at 30° with respect to the semiconductor substrate  31 .  
         [0064]    That is, if the halo ions that enhance a well concentration are injected into the source/drain regions  39  with a tilt, for solving the problems of difficulty in operation of the device and a poor performance of the device caused secondarily as a size of the logic device is reduced, such as HCE (Hot Carrier Effect), SCE (Short Channel Effect), and RSCE (Reverse SCE), since a doping concentration is increased locally only on an inside wall of a junction, a channel length can be shortened further while a concentration of the substrate is not increased.  
         [0065]    Moreover, the punch-through can be suppressed with respect to the channel length, a junction breakdown voltage is increased, and cost can be saved since concentration is increased, not in the entire substrate, but locally in a required part.  
         [0066]    Referring to FIGS. 8F and 9F, a refractory metal film (for an example, Co/Ti and the like) is formed on an entire surface of the semiconductor substrate  31  inclusive of the gate electrode  36 , and subjected to RTP (Rapid Thermal Processing), to form a metal silicide film  40  on the gate electrode  36  and the surface of the semiconductor substrate  31  having the source/drain regions  39  formed therein. In this instance, the Co/Ti are sputtered to 150/150 Å thickness.  
         [0067]    The refractory metal film on the gate electrode  36  and the semiconductor substrate  31  made no reaction is removed by wet etching. In the RTP for forming the metal silicide  40 , a first RTP is carried out at approx. 530° C. for 60 seconds, a second RTP is carried out at approx. 750° C. for 30 seconds, and the refractory metal film made no reaction is removed by wet etchant having H 2 O 2  and H 2 SO 4  mixed therein.  
         [0068]    Referring to FIGS. 8G and 9G, a first interlayer insulating film  41  is formed on an entire surface of the semiconductor substrate  31  inclusive of the metal silicide, film  40 . The first interlayer insulating film  41  includes an approx. 1000 Å thick nitride film  41   a , an approx. 5500 Å thick BPSG film  41   b , and an approx. 1000 Å thick PE-TEOS film  41   c , stacked in succession.  
         [0069]    In the meantime, the BPSG film  41   a  is formed to a thickness of approx. 8000 Å on the nitride film  41   a , heat treated at a temperature of approx. 850° C. for 30 seconds, and subjected to CMP on an entire surface thereof down to approx. 2500 Å from a surface thereof, to form a flat surface.  
         [0070]    Then, a photo and etching process is carried out to remove the first interlayer insulating film  41  selectively, to form a first contact hole  42  to expose parts of surfaces of the source/drain regions  39  and the gate electrode  36 . The first contact hole  42  has a width of approx. 0.23 μm.  
         [0071]    The first contact hole  42  is formed to expose parts of surfaces of the source/drain regions of the first load transistor Q 5 , the first drive transistor Q 3 , and the first access transistor Q 1 , and parts of surfaces of the gate electrodes of the second load transistor Q 6  and the second drive transistor Q 4 , which are connected in parallel as shown in FIG. 1.  
         [0072]    The first contact hole  42  is also formed to expose parts of surfaces of the source/drain regions of the second load transistor Q 6 , the second drive transistor Q 4 , and the second access transistor Q 2 , and parts of surfaces of the gate electrodes of the first load transistor Q 5  and the first drive transistor Q 3 .  
         [0073]    Referring to FIGS. 8H and 9H, a first barrier metal film  43  and a first tungsten film are formed in succession on an entire surface of the semiconductor substrate  31  inclusive of the first contact hole  42 , and subjected to CMP to form a first tungsten plug  44  inside of the first contact hole  42 . The first barrier metal film  43  has Ti/TiN films formed to 200/100 Å thickness, and the first tungsten film has a thickness of approx. 500 Å.  
         [0074]    Referring to FIGS. 8I and 9I, a metal film of Ti/TiN films are formed on an entire surface of the semiconductor substrate  31  inclusive of the first tungsten plug  44 , removed selectively by a photo and etching process, to form local interconnection  45  on the first tungsten plug  44  and the first interlayer insulating film  41  adjacent thereto. The local interconnection  45  has an L/S (Line/Space) of 0.20/0.19 μm.  
         [0075]    Referring to FIGS. 8J and 9J, a PE-TEOS film is formed as a second interlayer insulating film  46  to a thickness of approx. 4000 Å on an entire surface of the semiconductor substrate  31  inclusive of the local interconnection  45 , and the second interlayer insulating film  46  and the first interlayer insulating film  41  are removed selectively, to expose parts of surfaces of the source/drain regions  39  having no first tungsten plug  44  formed thereon, to form a second contact hole  47 .  
         [0076]    The second contact hole  47  is formed to expose parts of the source/drain regions of the first, and second access transistors Q 1  and Q 2 , and the first, and second drive transistors Q 3  and Q 4  shown in FIG. 1. The second contact hole  47  has a width of approx. 0.23 μm.  
         [0077]    Referring to FIGS. 8K and 9K, a second barrier metal film  48  and a second tungsten film are formed in succession on an entire surface of the semiconductor substrate  31  inclusive of the second contact hole  47 , and subjected to CMP to form a second tungsten plug  49  inside of the second contact hole  47 . The second barrier metal film  48  has Ti/TiN films formed to 100/100 Å thickness, and the second tungsten film has a thickness of approx. 4000 Å.  
         [0078]    Referring to FIGS. 8L and 9L, a metal film is formed on an entire surface of the semiconductor substrate  31  inclusive of the second tungsten plug  49 . The metal film has an approx. 100 Å thick first titanium film  50   a , an approx. 4500 Å thick aluminum film on the first Ti film, an approx. 50 Å thick second titanium film on the aluminum film, and an approx. 600 Å thick first titanium nitride TiN film on the second titanium film.  
         [0079]    Then, the metal film is selectively removed by a photo and etching process, to form metal interconnection  50 . The metal interconnection  50  is used as a Vcc line, and a Vss line.  
         [0080]    [0080]FIG. 10 illustrates a section showing a method for fabricating an SRAM cell in accordance with another preferred embodiment of the present invention. The steps from FIGS. 8A and  9 A to  8 F and  9 F are the same with the foregoing embodiment.  
         [0081]    Referring to FIG. 10, in the formation of the first contact hole  42 , the first contact hole  42  is formed to expose down to the source/drain regions  39  of the first, and second access transistors Q 1  and Q 2 , and a first barrier metal film  43  and a first tungsten plug  44  are formed.  
         [0082]    Then, a local interconnection  45  is formed, a second interlayer insulating film  46  is formed on an entire surface of the semiconductor substrate  31  inclusive of the local interconnection  45 , and the second interlayer insulating film  46  is removed selectively to expose a surface of the first tungsten plug  44 , to form a second contact hole  47 .  
         [0083]    Then, a second tungsten plug  49  is formed inside of the second contact hole  47  with a second barrier metal film  48  disposed inbetween, and a metal interconnection  50  is formed.  
         [0084]    The following table 1 compares an SRAM cell of the present invention to the related art SRAM cell.  
                                         TABLE 1                                   Related art   The present invention           (4.60 μm 2 )   (3.63 μm 2 )                                    Cell size   1.80 × 2.555   1.61 × 2.255       Access   0.35/0.28   0.255/0.235       transistor (Ta)       Drive transistor   0.35/0.18   0.30/0.18       (Td)       Load Transistor   0.25/0.20   0.23/0.18       (T1)       β-ratio   1.56   1.54       Distance between   0.70 μm   0.55 μm       wells       (0.23/0.32)                  
 
         [0085]    Referring to above table 1, the present invention permits to reduce a cell size within a range the reduction gives no influence to a cell stability (β-ratio=Ta/Ta).  
         [0086]    As has been explained, the SRAM cell and method for fabricating the same of the present invention have the following advantage.  
         [0087]    Even if the same 0.18 μm logic technology is applied, a 6T-SRAM with a 3.63 μm 2  smaller by 21% than the related art 6T-SRAM with a 4.60 μm 2  can be obtained.  
         [0088]    It will be apparent to those skilled in the art that various modifications and variations can be made in the SRAM cell and method for fabricating the same of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.