Abstract:
A method and apparatus are disclosed to control one or more input output (I/O) pads. An input signal is translated to an output signal having a desired logic level using a first latch loop. The state of the first latch loop is maintained by a second latch loop, integrated with the first latch loop, when a latching indication is received. The integration between the first latch loop and the second latch loop is such that the second latch loop creates an input-output connection if transmission gates in the second latch loop are conductive, and disables the input-output connection if the transmission gates are not conductive.

Description:
FIELD OF INVENTION 
     This application is related to computer systems. 
     BACKGROUND 
     Processing devices, such as central processing units (CPUs) and graphics processing units (GPUs), in computer systems may be powered from different supply voltages. Core processing logic that processes data and generates command signals to an external device in a GPU, may be powered by a first supply voltage, while input/output (I/O) logic that drives the command signals onto I/O pads may be powered by a second supply voltage. 
     To facilitate the communications between the digital core and the I/O pads/blocks that are using the different power supply, a level shifter circuit is designed and inserted in between the core blocks and the I/O pads/blocks. Current level shifter designs are based on either a PMOS/NMOS cross latch loop, or an inverter cross latch loop. For each of these designs, only one latch loop is used, and acts as an uncontrolled pass through voltage level translator. 
     An example of a single loop level shifter is illustrated in  FIG. 1 . The level shifter  10  comprises a PMOS transistor  11  and an NMOS transistor  12 , connected in series to power voltage Vdd and ground Vss. A PMOS transistor  13  and NMOS transistor  14  are connected to PMOS transistor  11  and NMOS transistor  13  in a latch form and are connected in series between the power voltage Vdd and ground Vss. 
     The gate of the PMOS transistor  11  is coupled to a voltage output Vout. The gate of the PMOS  13  is connected to the drain of the NMOS  12 . The gate of the NMOS  12  is connected to receive an input signal Vin, and the gate of the NMOS  14  is connected to the input signal Vin by an inverter  15 . 
     When an input voltage is applied to Vin, the NMOS  12  and the PMOS  13  are turned on, and the PMOS  11  and the NMOS  14  are turned off. The output signal Vout is therefore a high voltage signal. 
     When a 0V signal is the input signal Vin, the NMOS  14  and the PMOS  11  are turned on, and the NMOS  12  and the PMOS  13  are turned off. The output signal Vout is therefore a low voltage signal. 
     Known designs, such as the one illustrated in  FIG. 1 , may not have the controllable output latching feature. This feature is important in some situations when a constant output of the level shifter is required regardless of the input of the level shifter. For example, in a core re-power-up sequence, the core may not be in a regular working state during this period of time, and the control signal from the core to the I/O pads/blocks may not be correct and meaningful. Pass through level shifters will simply pass the incorrect control signals direct to the I/O pads/blocks, which may result in a malfunction and unpredictable situation. In this scenario, a level shifter with latched output may be used to maintain the I/O pads/blocks pre-set condition until the core is fully powered up and getting into a normal working state. 
     Known single loop level shifter that support a controllable output latching feature suffer from the glitch and uncertainty when the shifter restores from the latching state to the normal working state which follows the input. Other drawbacks that known designs may have include larger silicon area, more power, complexity, and relatively more duty cycle distortion. 
     Accordingly, there exists a need for an improved method and apparatus that overcome the above problems encountered by the current level shifters, including the level shifting function and controllable output latching. 
     SUMMARY 
     A method and level shifter are disclosed to control one or more input output (I/O) pads. An input signal is translated to an output signal having a desired logic level using a first latch loop. The state of the first latch loop is maintained by a second latch loop, integrated with the first latch loop, when a latching indication is received. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       A more detailed understanding may be had from the following description, given by way of example in conjunction with the accompanying drawings wherein: 
         FIG. 1  shows an example prior art single loop level shifter; 
         FIG. 2  shows an example dual loop level shifter as disclosed; 
         FIG. 3  shows the level shifter of  FIG. 2  in the normal working state; 
         FIG. 4  shows the level shifter of  FIG. 2  when the output latch signal is set; and 
         FIG. 5  shows an example of an alternative dual loop level shifter. 
     
    
    
     DETAILED DESCRIPTION 
     Although the features and elements are described in particular combinations, each feature or element can be used alone, without the other feature or elements, or in various combinations with or without other features and elements. 
     In accordance with a disclosed method and apparatus, a dual loop level shifter is shown in  FIG. 2 . The disclosed level shifter  200  comprises two cross latch loops that are integrated together, a PMOS/NMOS crosslatch loop  210  and an inverter cross latch loop  220 . The PMOS/NMOS cross latch loop  210  comprises PMOS transistors P 1 , P 2  and NMOS transistors N 1 , N 2 , N 3 , and N 4 . The inverter loop  220  comprises inverters inv 1 , inv 2 , and transmission gates tg 1 , tg 2 . The inverter inv 1  and inv 2  create an output to input connection through transmission gate tg 1  and tg 2 . When tg 1  and tg 2  are conductive, inv 1  and inv 2  are feeding each other&#39;s input with its own output and making a firm latch. Once tg 1  and tg 2  are no longer conductive, the output-input feeding will be disconnected and the inverter loop will be broken up. 
       FIG. 3  shows the level shifter  200  when the PMOS/NMOS loop  210  is enabled and working under the normal state. The input is followed and translated to the output having a desired logic level. The inverter cross loop  220  is disabled, but ready to cut in to inherit the state from the PMOS/NMOS loop  210  whenever output latching is enabled by an external control. The inverter cross latch loop  220  may be disconnected by tg 1  and tg 2 . 
     Inv 2  is the path that the output of the PMOS/NMOS loop  210  travels. At higher frequencies with tighter duty cycle distortion applications, inv 1  acts as a capacity load balance dummy that matches the capacity load of the drain of the P 1  and P 2  transistors. Tuning P 1 , P 2 , N 1 , N 2 , N 3  and N 4 , and the PN ratio of inv 2  generates reliable switching and minimized duty cycle distortion. 
     Once the output latch enable signal is set, for example PX-En=“1” and PX-ENB=“0. The PX-EN signal may be received from a system level control block that determines and detects the chip working state. As a result of the setting of the latch enable signal, N 3  and N 4  are tuned off by the ground gate drive (PX-ENB). The path, therefore, from N 1  and N 2  is shutoff, which will be driven by input signals. By doing this, the input is isolated outside of the level transmission cross latch loop.  FIG. 4  shows an example of the level shifter  200  when the output latch enable signal is set. 
     Since the PMOS/NMOS loop  210  and the inverter loop  220  are working in the same direction, inv 1 , inv 2 , which were closed by tg 1  and tg 2 , inherit the state of the PMOS/NMOS loop (i.e., P 1 , P 2 , N 1 , N 2 , N 3 , N 4 ). The output of the level shifter  200  is then driven by the latch state of the inverters inv 1  and inv 2 . The input, therefore, has no effect on the output. 
     When restoring the level shifter  200  from the output latch state back to the normal working state, NMOS transistors N 1  and N 2  start to drive the PMOS/NMOS cross latch loop  210  with the conducting N 3  and N 4 . N 1  and N 2  transistors are connected to the PMOS transistors through N 3  and N 4 . Once N 3  and N 4  are driven by the gate and start to conduct, N 1  and N 2  have direct connection to the PMOS transistors and start to “drive” the loop. The state of the N 1  and N 2  are decided by the input signal. Because inv 1  and inv 2  are still latched to the previous state, driving the drain of P 1  and P 2  as expected from N 1  and N 2 , the state will be transferred from the inverter loop  220  back to the PMOS/NMOS loop  210 . Once the PMOS/NMOS loop  210  is fully in action (transistors N 3  &amp; N 4  are fully turned on), the inverter loop  220  will completely fade out (tg 1  and tg 2  are fully turned off). This transition from the inverter loop  220  to the PMOS/NMOS loop  210  occurs when the input is the same as the output. 
     When the input is different from the previous latched state at the moment of restoring the level shifter  200  back to normal working condition, transistors N 1  and N 2  drive the PMOS/NMOS loop  210  in a different direction as the inverter cross loop  220  is maintained. However, because the PMOS/NMOS latching power has been increasing with the turning on of the transistors N 3  &amp; N 4 , and the inverter cross latch loop  220  latching power is decreasing with the turning off of the transmission gates tg 1  and tg 2 , N 1  and N 2  may over come the previously maintained state and set a new state. 
     Because inverter inv 1  and inv 2  will be cut outside by tg 1  and tg 2 , N 1  and N 2  don&#39;t need to be over driven too much, which means smaller transistor size and smaller area. Also, because tg 1  and tg 2  are only needed to maintain the static state instead of conducting considerable amount of dynamic current, a minimum size transistor could be safely here, lead to small silicon area. 
     An alternative level shifter  500  is shown in  FIG. 5 . The level shifter  500  comprises a PMOS/NMOS loop  510  including PMOS transistors P 5 , P 6  and NMOS transistors N 5 , N 6  and N 7 , an inverter loop including inverters inv 3 , inv 4 , and transmission gates tg 3  and tg 4 . In operation, the level shifter  500  operates similar to the level shifter  200  disclosed above. The N 7  transistor though is used to disconnect the PMOS/NMOS  510  loop from the input, which is triggered by PX-ENBS, targeting at the different control transistors. 
     In another alternative, the inverter cross latch loop may be the main working latch loop and the PMOS/NMOS cross latch loop the maintenance loop. 
     The disclosed level shifter uses a single loop in the normal working state and therefore is able to be easily tuned and has a good duty cycle distortion. The disclosed level shifter also requires less current and power when working under high switching frequency than do current designs. 
     The inverters in the disclosed inverter loop of the level shifter serve as the capacity load balance for the PMOS/NMOS cross loop. Transistor reuse saves silicon area and makes the design less complicated. Because inverter cross latch loop is used in the output latching state, the transmission gates allow for the level shifter to include smaller sized transistors. 
     The level shifter also prevents the glitch and uncertainty when the shifter restores from the output latch state back to the normal working condition. As indicated above, the two loops are working in the same latch direction. Accordingly, when the level shifter is restored from the output latching state, the inverter cross latch loop maintains and transfers the state to the upcoming PMOS/NMOS latch loop until the inverter cross latch loop is disconnected by the transmission gate. For example, the inverter loop inherits the state when entering the output latching state from the PMOS/NMOS cross latch loop, and the PMOS/NMOS cross latch loop inherits the fixed state from the inverter cross latch loop in the restoring process. No uncertainty, glitch, reset or extra timing are required. Therefore, the restore process is smooth and instant. 
     The disclosed dual loop level shifter may be implemented on an integrated circuit, such as an application specific integrated circuit (ASIC), multiple integrated circuits, logical programmable gate array (LPGA), multiple LPGAs, discrete components, or a combination of integrated circuit(s), LPGA(s), and discrete component(s).