Abstract:
A frequency generator with a phase locked loop includes a loop filter, the transfer function of which has a pair of complex conjugated poles. The present invention provides an optimum and greatly improved compromise, in particular as opposed to the prior art, between phase noise and settling time of the phase locked loop of the frequency generator.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     This application is a continuation of co-pending International Application No. PCT/EP2004/003261, filed Mar. 26, 2004, which designated the United States and was not published in English and is incorporated herein by reference in its entirety. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     This invention relates to a frequency generator with a phase locked loop with a loop filter, to a method of generating an oscillating output signal, as well as a method and an apparatus for designing a frequency generator.  
         [0004]     2. Description of the Related Art  
         [0005]     Frequency generators with phase locked loop (PLL) are employed in many areas, for example in a digital wireless communication system, such as Bluetooth. In such a communication system, a frequency generator generates the carrier signal used for modulation in the transmitter or in transmitting and for demodulation in the receiver or in receiving. A frequency band is associated with each communication system. The communication system may utilize all frequencies within this frequency band to transfer data or information from the transmitter to the receiver. The power of signals the transmitter generates outside the associated frequency band is not allowed to exceed a certain limit, in order not to disturb communication systems utilizing neighboring frequency bands. Signal portions outside the associated frequency band are the greater, the greater the phase noise S φ  with which the carrier or the carrier frequency is burdened. For this reason, the phase noise S φ  has to lie below a predetermined limit S φmax  at a certain frequency offset Δf sp  from the carrier.  
         [0006]     A further requirement for a frequency generator is that, after announcement of a to-be-output or desired output frequency or target frequency, it adjusts the output frequency sufficiently accurately to the target output frequency within an as-short-as-possible settling time. There are still further requirements, which among other things depend on the modulation method used. In an FSK method (FSK=frequency shift keying), for example, direct modulation capability of the output frequency of the frequency generator is advantageous and desired.  
         [0007]      FIG. 10  is a schematic circuit diagram showing an example for a frequency generator based on a phase locked loop. A phase/frequency detector PFD  10  includes a reference signal input  12  for receiving a reference signal with a reference frequency f ref , a comparison signal input for receiving a comparison signal with a comparison frequency f 1 , and a control output  16  for outputting an oscillator control signal. The phase/frequency detector then forms the oscillator control signal depending on the difference between the comparison frequency f 1  of the comparison signal present at the comparison signal input  14  and the reference frequency f ref  of the reference signal present at the reference signal input  12 .  
         [0008]     A loop filter  20  includes an input  22  connected to the control output  16  of the phase/frequency detector  10  and an output  24 . The loop filter  20  usually is a low-pass filter, mostly an RC filter. It filters the oscillator control signal received at the input  22  from the phase/frequency detector  10 , in order to generate a filtered oscillator control signal, which it outputs at the output  24 . An oscillator  30  includes an input  32  connected to the output  24  of the loop filter  20  and an output  34 . The oscillator  30  receives the filtered oscillator control signal from the loop filter  20  at its input  32  and generates an output signal with an output frequency f out  at its output  34 . The oscillator  30  generates the output signal so that the output frequency f out  depends on the filtered oscillator control signal.  
         [0009]     The oscillator  30 , for example, is a voltage-controlled oscillator (VCO). A VCO usually includes a varactor diode, the capacity of which depends on a present direct voltage. The varactor diode forms the capacity in an LC resonant circuit. The filtered oscillator control signal is a voltage signal applied to the varactor diode (in reverse direction). The greater the applied voltage, the greater the space charge zone and the smaller the electric capacitance between the electrodes in the varactor diode. The smaller the capacitance of the varactor diode, the greater the natural frequency or resonance frequency or output frequency f out  of the VCO  30 .  
         [0010]     A frequency divider  40  includes an input  42  connected to the output  34  of the oscillator  30 , an output  44  connected to the comparison signal input  14  of the phase/frequency detector  10 , and a control input  46 . The frequency divider receives the output signal with the output frequency f out  from the output  34  of the oscillator  30  at its input  42  and a frequency factor control signal at its control input  46 . The frequency factor control signal represents a frequency factor, which is an integer fraction 1/N of 1. The integer N will be referred to as divisor in the following. The frequency divider  40  generates the comparison signal with the comparison frequency f 1  from the output signal with the output frequency f out  by a frequency division, wherein the comparison frequency f 1  is smaller than the output frequency f out  by the frequency factor 1/N, f 1 =f out /N.  
         [0011]     The frequency generator illustrated in  FIG. 10  further comprises a ΣΔ modulator  50 . The ΣΔ modulator  50  includes an input  52 , a reference signal input  54 , and a control output  56  connected to the control input  46  of the frequency divider  40 . The ΣΔ modulator receives, at its input  50 , a signal representing a desired frequency factor 1/N frac , which does not have to be an integer fraction of 1, as opposed to the frequency factor processed by the frequency divider  40 . The ΣΔ modulator receives, at its reference signal input  54 , the same reference signal the phase/frequency detector  10  receives at its reference signal input  12 . The reference signal serves as clock signal for the ΣΔ modulator.  
         [0012]     The desired frequency factor 1/N frac  or its inverse, the desired divisor N frac , are preferably passed to the ΣΔ modulator  50  in form of an input word K with the binary input word width k at its input  52 , wherein N frac =N 0 +xK/2 k  applies. Here, N 0  is a natural number and x+1 the number of (integer) moduli made available by the frequency divider  40 . The frequency divider  40  divides the output frequency f out  by a divisor N, which takes on one of the integer values N 0 , N 0 +1, N 0 +2, . . . , N 0 +x. If, for example, f ref =8 MHz, N 0 =124, x=2, and k=4 applies, the input word K may take on the values 0, 1, 2, . . . , 15, the divisor N the values N=124, N=125, N=126, and the frequency factor 1/N the values 1/N= 1/124, 1/N= 1/125, and 1/N= 1/126.  
         [0013]     If the ΣΔ modulator  50  receives an input word K=0, 1, 2, . . . , 15 at its input  52 , it controls the frequency divider  40  so that the divisor N corresponds to the desired divisor N frac , i.e. one of the values 124, 0, 124, 125, 124, 250, 124, 375, . . . , 125, 750 or 125, 875, in temporal average. If the desired divisor N frac  is integer (K=0, N frac =124 and K=8, N frac =125), the ΣΔ modulator  50  generates a frequency factor control signal at its control output  56 , which causes the corresponding frequency factor ( 1/124 or 1/125) to be adjusted in the frequency divider  40  in constant manner. If the desired divisor N frac  is not an integer (K=1, N frac =124, 125 to K=7, N frac =124, 875 and K=9, N frac =125, 125 to K=1, N frac =125, 875), the ΣΔ modulator  50  generates, at its control output  56 , a time-variable frequency factor control signal causing the frequency divider  40  to alternatingly set the divisor N to one of the (integer) values 124, 125, 126. The ΣΔ modulator  50  determines the portion the individual frequency factors have of the overall time, so that the temporal average of the frequency factors adjusted by the frequency divider  40  corresponds to the desired frequency factor 1/N frac . In other words, the direct component of the frequency factor control signal generated by the ΣΔ modulator  50  ensures that the (mean) output frequency of the output signal is f out =N frac  f ref .  
         [0014]     While, without the ΣΔ modulator  50 , only the output frequencies f out =992 MHz, 1000 MHz, 1008 MHz would be adjustable by the frequency divider  40 , the ΣΔ modulator  50  controls the frequency divider  40  so that, with the numerical example mentioned, 16 different output frequencies at a distance of 1 MHz can be generated, f out =992 MHz (K=0), 993 MHz (K=1), 994 MHz (K=2), . . . , 1007 MHz (K=15).  
         [0015]     In the embodiment illustrated, a circuit of two current sources  60 ,  62  and two switches  64 ,  66  is connected between the control output  16  of the phase/frequency detector  10  and the input  22  of the loop filter  20 . The first current source  60 , the first switch  64 , the second switch  66  and the second current source  62  are connected in series between a supply potential terminal and ground in this arrangement. The switches  64 ,  66  are connected to the control output  16  of the phase/frequency detector  10  and are controlled individually and depending on the reference frequency f ref  and the comparison frequency f 1  by the phase/frequency detector  10 . They convert the oscillator control signal generated by the phase/frequency detector  10  to a modified oscillator control signal, which is fed to the loop filter  20 . Functionally, the arrangement of the current sources  60 ,  62  and the switches  64 ,  66  may be regarded as a constituent of the phase/frequency detector.  
         [0016]     The phase/frequency detector  10 , the loop filter  20 , the oscillator, and the frequency divider  40  form a locked loop. The oscillator control signal generated by the phase/frequency detector  10  due to a phase difference between the reference signal and the comparison signal controls the oscillator  30  so that the comparison signal has a constant phase relation to the reference signal.  
         [0017]     A further important property of the ΣΔ modulator is that it controls the integer divisors N, N+1, N+2, . . . , N+x (in the concrete numerical example: 124, 125, 126) of the frequency divider  40  in a quasi-random sequence so that the quantization noise of the ΣΔ modulator  50  has an advantageous noise spectrum. The advantageous noise spectrum contains little power at low-noise frequencies and much power at high-noise frequencies. These high-noise frequencies, however, are largely suppressed or removed by the loop filter.  
         [0018]     An advantage of the ΣΔ modulator fractional-N frequency generator or frequency generator with the ΣΔ modulator described on the basis of  FIG. 10  is that it may be operated at an almost arbitrary reference frequency f ref  or the reference frequency f ref  does not restrict the series of possible output frequencies f out  or their frequency distance. Its phase noise and its settling time are substantially determined by the transfer function H PLL (s) of the phase locked loop. The ΣΔ fractional-N frequency generator from  FIG. 10  can further be modulated easily, for example by means of pre-emphasis methods or two-point modulation.  
         [0019]     If the phase locked loop  10 ,  20 ,  30 ,  40  and particularly its loop filter  20  is narrow band, the constant switching of the frequency divider  40  between various frequency factors 1/N or between various divisors N caused by the ΣΔ modulator  50  has a weaker effect on the output frequency f out  than if the phase locked loop is broadband. On the other hand, the more broadband it is, the quicker the phase locked loop is capable of following a desired change of the output frequency f out . Phase noise and settling time of the phase locked loop and the frequency generator thus have to be balanced against each other. How difficult it is to find a compromise here, however, depends on the amplification K VCO  of the VCO  30 , the properties of the phase/frequency detector  10  and of the loop filter  20 , among other things.  
         [0020]     There is a series of influences on the phase noise of a ΣΔ fractional-N frequency generator. Among those are the phase noise of the free-running oscillator  30 , the phase noise of the reference signal, the jitter of the frequency divider  40 , the noise of the phase/frequency detector  10  and of the loop filter  20 . Usually dominant, however, is the quantization noise N q  of the ΣΔ modulator  50 . In their article “A CMOS Monolithic ΣΔ-Controlled Fractional-N Frequency Synthesizer for DCS-1800” (IEEE J. Solid-State Circuits, vol. 37, No. 7, pp. 835-44, 2002), D. de Muer and M. S. J. Steyaert indicate an approximation formula for the contribution of the quantization noise N q  of the ΣΔ modulator to the phase noise S φ  of the ΣΔ fractional-N frequency generator. From this approximation formula, the inequality  
                H   PLL     ⁡     (     2   ⁢           ⁢   π   ⁢           ⁢   Δ   ⁢           ⁢     f   sp       )            &lt;           S   ϕmax     ⁡     (     Δ   ⁢           ⁢     f   sp       )       ⁢       3   ⁢     f   ref     ⁢            1   -     z     -   1              2           Δ   2     ⁢     π   2     ⁢              H   q     ⁡     (   z   )            2                 
 
 may be derived for the magnitude of the transfer function. If this inequality is satisfied, the phase noise S φ  of the frequency generator at a frequency offset Δf sp  from the carrier or a carrier frequency is not greater than the limit S φmax . Here, H PLL (s) is the transfer function of the phase locked loop, f ref  the reference frequency, H q (Z) the noise-forming function of the ΣΔ modulator, z=exp(j2πΔf sp /f ref ), Δ=x/(2 B−1 ), and B the width of the output word of the ΣΔ modulator. 
 
         [0021]     The settling time of a frequency generator is, according to definition, the time the frequency generator needs after announcement of the frequency to be output, to adjust the output frequency f out  accurately up to a relative error α. If the phase difference between the reference signal and the comparison signal remains smaller than 2π during the settling process, the relative frequency error may be calculated by determining the response of the so-called error transfer function H e (s)=(1−H PLL (s)) to a jump of the height ΔN frac /N frac  (at a time instant t=0). The settling time then corresponds to the earliest time instant after which the magnitude of the relative frequency error remains smaller than α.  
       SUMMARY OF THE INVENTION  
       [0022]     It is an object of the present invention to provide a frequency generator, a method of generating an oscillating output signal, a method, a computer program, and an apparatus for designing a frequency generator, which have or provide little phase noise and short settling time.  
         [0023]     In accordance with a first aspect, the present invention provides a frequency generator, having: a phase locked loop with a loop filter, wherein the loop filter is formed such that a transfer function of the loop filter has a pair of complex conjugated poles.  
         [0024]     In accordance with a second aspect, the present invention provides a method of generating an oscillating output signal with an output frequency from a reference signal with a reference frequency, with the steps of: generating the oscillating output signal; generating a comparison signal from the oscillating output signal, wherein a comparison frequency of the comparison signal differs from the output frequency by a frequency factor; comparing the comparison frequency with the reference frequency or a phase of the comparison signal with a phase of the reference signal, in order to generate an oscillator control signal, which depends on the difference of the comparison frequency and the reference frequency or on the difference of the phase of the comparison signal and the phase of the reference signal; filtering the oscillator control signal with a loop filter, in order to obtain a filtered oscillator control signal, wherein the transfer function of the loop filter has a pair of complex conjugated poles; and controlling the output frequency of the output signal depending on the filtered oscillator control signal.  
         [0025]     In accordance with a third aspect, the present invention provides a method of designing a frequency generator with a phase locked loop with a loop filter, with the steps of: determining a maximum phase noise of the phase locked loop and a frequency offset, wherein the phase noise of the phase locked loop is to be no more than equal to the maximum phase noise at the frequency offset from a carrier frequency; calculating a maximum magnitude of a transfer function H PLL (s) of the phase locked loop at the frequency offset from the maximum phase noise and the frequency offset; determining a pair of complex conjugated poles of a transfer function H LF (s) of the loop filter so that the magnitude of the transfer function H PLL (s) of the phase locked loop for the determined pair of complex conjugated poles is equal to the maximum magnitude and the settling time of the phase locked loop is minimal.  
         [0026]     In accordance with a fourth aspect, the present invention provides a computer program with program code for performing, when the computer program is executed on a computer, the method of designing a frequency generator with a phase locked loop with a loop filter, with the steps of: determining a maximum phase noise of the phase locked loop and a frequency offset, wherein the phase noise of the phase locked loop is to be no more than equal to the maximum phase noise at the frequency offset from a carrier frequency; calculating a maximum magnitude of a transfer function H PLL (s) of the phase locked loop at the frequency offset from the maximum phase noise and the frequency offset; determining a pair of complex conjugated poles of a transfer function H LF (s) of the loop filter so that the magnitude of the transfer function H PLL (s) of the phase locked loop for the determined pair of complex conjugated poles is equal to the maximum magnitude and the settling time of the phase locked loop is minimal.  
         [0027]     In accordance with a fifth aspect, the present invention provides an apparatus for designing a frequency generator with a phase locked loop with a loop filter, having: a maximum phase noise determinator for determining a maximum phase noise of the phase locked loop and a frequency offset, wherein the phase noise of the phase locked loop is to be no more than equal to the maximum phase noise at the frequency offset from a carrier frequency; a calculator for calculating a maximum magnitude of a transfer function of the phase locked loop at the frequency offset from the maximum phase noise and the frequency offset; and a pole determinator for determining a pair of complex conjugated poles of a transfer function of the loop filter, for which the magnitude of the transfer function of the phase locked loop is equal to the maximum magnitude and the settling time of the phase locked loop is minimal.  
         [0028]     The present invention is based on the finding to use a loop filter the transfer function of which comprises a pair of complex conjugated poles. Furthermore, the present invention is based on the finding that these complex conjugated poles can be chosen so that the phase noise S φ  of the frequency generator does not exceed a predetermined limit at a certain frequency offset and at the same time the settling time of the frequency generator is minimized.  
         [0029]     According to a preferred embodiment of the present invention, a frequency generator is designed with a phase locked loop. For this, as solution of the minimization object described with boundary conditions, at first poles and zeros of the transfer function of the phase locked loop are determined. From the poles and zeros of the transfer function of the phase locked loop, then the transfer function of the loop filter and its pair of complex conjugated poles may be determined.  
         [0030]     An advantage of the present invention is that it provides an optimum and, particularly as opposed to the prior art, greatly enhanced compromise between phase noise and settling time of a phase locked loop of a frequency generator.  
         [0031]     A further advantage is that the present invention provides a method for synthesis of a frequency generator with a phase locked loop.  
         [0032]     According to preferred embodiments of the present invention, the loop filter includes a coil or an active filter to generate a pair of complex conjugated poles of the transfer function. Especially preferably, the loop filter includes a biquad filter or a current-mode biquad filter. The current-mode biquard filter is preferably constructed of transconductors. An advantage of the realization of the loop filter with a current-mode biquard filter is that this has an especially low power demand.  
         [0033]     Preferably, the loop filter is synthesized from transconductors. This has the advantage that the individual transconductors only influence each other slightly. Different from, for example, the use of passive devices, such as resistors, capacitors, and coils for the synthesis of a filter, the synthesis process with the use of transconductors is relatively linear and uncomplicated. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0034]     These and other objects and features of the present invention will become clear from the following description taken in conjunction with the accompanying drawings, in which:  
         [0035]      FIG. 1  is a schematic diagram illustrating the settling time of a frequency generator according to the invention;  
         [0036]      FIG. 2  is a schematic circuit diagram of a loop filter according to a preferred embodiment of the present invention;  
         [0037]      FIG. 3  is a schematic block circuit diagram of a biquad filter of a loop filter according to the present invention;  
         [0038]      FIG. 4  shows a current-mode integrator of a loop filter according to the present invention;  
         [0039]      FIG. 5  shows a current-mode biquad filter of a loop filter according to a preferred embodiment of the present invention;  
         [0040]      FIG. 6  is a schematic circuit diagram of a transconductor from  FIG. 5 ;  
         [0041]      FIG. 7  is a schematic circuit diagram of an output common-mode regulation for the transconductor from  FIG. 6 ;  
         [0042]      FIG. 8  is a schematic illustration of the transfer function of the transconductor;  
         [0043]      FIG. 9  is a schematic illustration of the transfer function of a biquad filter; and  
         [0044]      FIG. 10  is a schematic circuit diagram of a conventional frequency generator with a phase locked loop. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0045]     As has already been explained, both the settling time T min  and the phase noise S φ  of the frequency generator are functions of the poles and zeros of the transfer function H PLL (s) of the phase locked loop. The transfer function H PLL (s) of the phase locked loop depends on the amplification K VCO  of the oscillator  30  ( FIG. 10 ), on the current I p  of the current operated by the current sources, and on the transfer function Z LF (s) of the loop filter  20  as follows:  
           H   PLL     ⁡     (   s   )       =             K   VCO     ⁢     I   p         2   ⁢           ⁢   π       ⁢       Z   LF     ⁡     (   s   )           1   +           K   VCO     ⁢     I   p         2   ⁢           ⁢   π       ⁢       Z   LF     ⁡     (   s   )                 
 
 (c.f. F. M. Gardner: “Charge-Pump Phase-Lock Loops”, IEEE Trans. Commun., vol. COM-28, pp. 1849-58, 1980). The transfer function of the loop filter of a type II N-th order phase locked loop has N-2 poles s ∞LF,n  different from zero and a zero. Together with the factor K VCO I p , N independent variables exist, which may be mapped one-to-one to the poles s ∞PLL,n  of the transfer function H PLL (s) of the phase locked loop. The poles s ∞PLL,n  (n=1, 2, . . . , N) are represented as 
 
 s   ∞PLL,n   =s   N   s   ∞r,n , 
 
 wherein s N  is a reference location on the negative portion of the real axis of the plane of numbers and s ∞r,n  (n=1, 2, . . . , N) the relative locations of their poles in the complex plane of numbers with reference to the reference location s N . 
 
         [0046]     The transfer function H o,PLL (s) of the open type II phase locked loop is a simple function of the transimpedance Z LF (s) of the loop filter,  
           H     o   ,   PLL       ⁡     (   s   )       =           K   VCO     ⁢     I   p           N   frac     ⁢   2   ⁢           ⁢   π   ⁢           ⁢   s       ⁢         Z   LF     ⁡     (   s   )       .           
 
         [0047]     The transimpedance Z LF (s) of the loop filter is represented as fraction Z LF (s)=P LF (s)/Q LF (s) of two polynomials 
 
 P   LF ( s )=p 1,LF S+p 0,LF  
 
 and 
 
Q LF (s)=q N−1,LF s N−1 +q N−2,LF s N−2 +. . . +q 1,LF s. 
 
         [0048]     The connection between the transfer function H PLL (s) of the closed phase locked loop and the transfer function H o,PLL (s) of the opened phase locked loop is  
           H   PLL     ⁡     (   s   )       =           P   PLL     ⁡     (   s   )           Q   PLL     ⁡     (   s   )         =           H     o   ,   PLL       ⁡     (   s   )         1   +       H     o   ,   PLL       ⁡     (   s   )           .           
 
         [0049]     The coefficients P n,LF (n=0, 1) of the numerator polynomial P LF (s) and q n,LF (n=1, 2, . . . , N−1) of the denominator polynomial Q LF (s) of the loop filter may simply be determined from the coefficients q n,PLL  (n=0, 1, 2, . . . , N) of the denominator polynomial Q PLL (s) of the transfer function H PLL (s) of the phase locked loop:  
         p     n   ,   LF       =         2   ⁢           ⁢   π   ⁢           ⁢     N   frac           K   VCO     ⁢     I   p         ⁢     q     n   ,   PLL       ⁢           ⁢     (       n   =   0     ,   1     )           
     and     
         q     n   ,   LF       =       q       n   +   1     ,   PLL       ⁢           ⁢       (       n   =   1     ,   2   ,   …   ⁢           ,     N   -   1       )     .           
 
         [0050]     It follows from the equations, that both the numerator polynomial P LF (s) and the denominator polynomial Q LF (s) of the transfer function Z LF (s) of the loop filter and the product K VCO I p /N frac  can be calculated alone from the denominator polynomial Q PLL (s) of the transfer function H PLL (s) of the phase locked loop. Furthermore, it follows from the equations that the transfer function H PLL (s) of the phase locked loop has exactly one zero at s 0 =q 1,PLL /q 0,PLL . This zero is not adjusted depending on the poles of the transfer function H PLL (s) of the transfer function of the phase locked loop. The knowledge of the poles s ∞PLL,n  (n=1, 2, . . . , N) of the transfer function H PLL (s) of the phase locked loop or of their relative locations s ∞r,n  is therefore sufficient to determine the transfer function H PLL (s) for an arbitrary s.  
         [0051]     In a first synthesis step, that reference location s N  for which the above inequality is satisfied with the equality sign is determined,  
                H   PLL     ⁡     (     2   ⁢           ⁢   π   ⁢           ⁢   Δ   ⁢           ⁢     f   sp       )            =             S   ϕmax     ⁡     (     Δ   ⁢           ⁢     f   sp       )       ⁢       3   ⁢     f   ref     ⁢            1   -     z     -   1              2           Δ   2     ⁢     π   2     ⁢              H   q     ⁡     (   z   )            2             .         
 
         [0052]     According to the similarity theorem of the Laplace transform, the solution to this equation minimizes the settling time of the phase locked loop for given relative locations s ∞r,n  (n=1, 2, . . . , N) of the poles.  
         [0053]     That theorem of the relative pole locations s ∞r,n  for which the settling time T is minimal (T=T min ) at the optimized reference location s N  is then searched for with a numerical method. Such a numerical method is for example the Nelder-Mead-Algorithmus (J. C. Lagarias et al.: “Convergence Properties of The Nelder-Mead Simplex-Method in Low Dimensions”, SIAM J. Optim, vol. 9, no. 1, pp. 112-47, 1998). The Nelder-Mead algorithm is available in MatLab, for example.  
         [0054]     Between the coefficients q n,PLL  (n=0, 1, . . . , N) of the denominator polynomial Q PLL (s) of the transfer function H PLL (s) of the phase locked loop on the one hand and the zeros s ∞PLL,n=s   N s ∞r,n  (n=1, 2, . . . , N) of the denominator polynomial Q PLL (s), i.e. the poles of the transfer function H PLL (s), on the other hand, there is a simple connection easily obtainable by multiplying the right side of the equation 
 
Q LF (s)=q N-1,LF s N-1 +q N-2,LF s N-1 +q N-2,LF s N-2 + . . . +q 1,LF s=(s−s ∞PLL,1 )·(s−s ∞PLL,2 )· . . . ·(s−s ∞PLL,N ). 
 
         [0055]     In this manner, from the optimized poles s ∞PLL,n =s N s ∞r,n  (n=1, 2, . . . , N) of the transfer function H PLL (s), the coefficients q n,PLL  ((n=0, 1, . . . , N) of the denominator polynomial Q PLL (s) of the transfer function H PLL (s) of the locked loop are acquired.  
         [0056]     From the coefficients q n,PLL  (n=0, 1, . . . , N) of the denominator polynomial Q PLL (s) of the transfer function H PLL (s) of the locked loop, the coefficients P n,LF  (n=0, 1) of the numerator polynomial P LF (s) and the coefficients q n,LF  (n=1, 2, . . . , N−1) of the denominator polynomial Q LF (s) of the transfer function of the loop filter are acquired according to the equations already stated above  
         p     n   ,   LF       =         2   ⁢           ⁢   π   ⁢           ⁢     N   frac           K   VCO     ⁢     I   p         ⁢     q     n   ,   PLL       ⁢           ⁢     (       n   =   0     ,   1     )           
     and     
         q     n   ,   LF       =       q       n   +   1     ,   PLL       ⁢           ⁢       (       n   =   1     ,   2   ,   …   ⁢           ,     N   -   1       )     .           
 
         [0057]     With this, the loop filter or the coefficients of its mathematical representation are completely determined. The calculation of the sizes of individual devices will exemplarily be described in greater detail further below on the basis of FIGS.  2  to  5 .  
         [0058]     In a schematic diagram,  FIG. 1  shows the minimum settling times T min  (ordinate) for phase locked loops with a conventional passive loop filter (curve  102 , dotted) and with the inventive active loop filter (curve  104 , solid) in dependence on the reference frequency f ref  (abscissa). The conventional phase locked loop with a passive loop filter is a 5-th order type II phase locked loop. Both curves  102 ,  104  were calculated for a phase noise of −125 dBc/Hz@2.5 MHz, a modulus jump of ΔN frac /N frac = 1/30, Δ=x/(2 B−1 )=2, and a frequency accuracy of α=20 ppm. It can be seen that, over the entire region of the reference frequency f ref  illustrated, the settling time for the conventional phase locked loop with a passive RC loop filter is more than twice as high than for the inventive phase locked loop with a pair of complex conjugated poles, which have been optimized as indicated above.  
         [0059]      FIG. 2  shows a schematic circuit diagram of a loop filter  20  according to a preferred embodiment of the present invention. The loop filter  20  is a fourth order filter with two real poles and a pair of complex conjugated poles. The real poles are realized out of a resistor R 1  and two capacitors C 1 , C 2  with the aid of a passive RC filter. The resistor R 1  and the first capacitor C 1  are connected in series between the inputs  22   a ,  22   b  and the loop filter  20 . The second capacitor C 2  is connected between the inputs  22   a ,  22   b  in parallel to the series circuit of the resistor R 1  and the first capacitor C 1 . A biquad filter  120  is connected downstream of the passive RC filter of the resistor R 1  and the capacitors C 1 , C 2 , wherein inputs  122   a ,  122   b  of the biquad filter  120  are connected to the inputs  22   a ,  22   b  of the loop filter  20 . Outputs  124   a ,  124   b  of the biquad filter  120  are connected to the outputs  24   a ,  24   b  of the loop filter  20 . The transfer function H biqad (s) of the biquad filter  120  comprises the pair of complex conjugated poles.  
         [0060]      FIG. 3  is a schematic block circuit diagram of the biquad filter  120  from  FIG. 2 . The biquad filter  120  includes a first integrator  132  with the transfer function H 1 (s), a second integrator  134  with the transfer function H 2 (s), a first adder  136 , a second adder  138 , a first multiplier  140 , and a second multiplier  142 . A first input  138   a  of the second adder  138  is connected to the input  122  of the biquad filter  120 . A second input  138   b  of the second adder  138  is connected to an output  142   b  of the second multiplier  142 . An output  138   c  of the second adder  138  is connected to a first input  136   a  of the first adder  136 . A second input  136   b  of the first adder  136  is connected to an output  140   b  of the first multiplier  140 . An output  136   c  of the first adder  136  is connected to an input  132   a  of the first integrator  132 . An output  132   b  of the first integrator  132  is connected to an input  140   a  of the first multiplier  140  and to an input  142   a  of the second integrator  134 . An output  134   b  of the second integrator  134  is connected to an input  142   a  of the second multiplier  142  and the output  124  of the biquad filter  120 .  
         [0061]     In an idealized approximation, the integrators  132 ,  134  are ideal integrators, the transfer functions H 1,ideal (s), H 2,ideal (s) have the simple forms of  
           H     1   ,   ideal       ⁡     (   s   )       ⁢       a   1     s         
     and     
             H     2   ,   ideal       ⁡     (   s   )       ⁢         a   2     s     .     
     ⁢   Hence       ,     
     ⁢         H     Biquad   ,   ideal       ⁡     (   s   )       =       K       s   2     +         ω   0     Q     ⁢   s     +     ω   0   2         =         a   1     ⁢     a   2           s   2     +       a   1     ⁢     b   1     ⁢   s     +       a   1     ⁢     a   2     ⁢     b   2                   
 
 applies, wherein Q is the quality and ω 0  the resonance frequency of the biquad filter  120 . 
 
         [0062]     Ideal integrators, however, do not exist. In a first approximation to reality, the poles of the transfer functions H 1 (s), H 2 (s) are shifted from the origin along the real axis in the complex plane of numbers,  
           H   1     ⁡     (   s   )       ⁢       a   1       s   +     s   ∞1             
     and     
             H   2     ⁡     (   s   )       ⁢         a   2       s   +     s   ∞3         .     
     ⁢   Hence       ,     
     ⁢         H   Biquad     ⁡     (   s   )       =         a   1     ⁢     a   2           s   2     +       (         a   1     ⁢     b   1       +     s   ∞1     +     s   ∞3       )     ⁢   s     +       a   1     ⁢     a   2     ⁢     b   2       +       a   1     ⁢     b   1     ⁢     s   ∞3       +       s   ∞1     ⁢     s   ∞3                 
 
 applies. 
 
         [0063]     From this equation, it can be recognized or derived that the quality Q of the biquad filter is upwardly limited, different from the case of ideal integrators. Furthermore, the resonance frequency ω 0  is downwardly restricted and the direct current amplification diminished, namely the stronger, the closer the pole frequency of the integrators  132 ,  134  lies to the resonance frequency strived for.  
         [0000]     From a comparison with the equation 
 
Q LF (s)=q N-1,LF s N-1 +q N-2,LF s N−2 + . . . + 1,LF s 
 
 already indicated above for the denominator polynomial of the transfer function Z LF (s) of the loop filter, simple connections between the coefficients q n,LF (n=0, 1, 2) of the denominator polynomial Q LF (s) of the transfer function Z LF (s) of the loop filter and the coefficients a 1 , a 2 , s ∞1 , s ∞3  of the transfer functions H 1 (s), H 2 (s) of the (not ideal) integrators of which the biquad filter in this embodiment is constructed, determined according to the above-described method, result: 
 
 q   2,LF =1, 
 
 q   1,LF   =a   1   b   1   +s   ∞1   +s   ∞3 , 
 
 q   0,LF   =a   1   a   2   b   2   +a   1   b   1   s   ∞3   +s   ∞1   s   ∞3  
 
         [0064]     Apart from the fact that the pole of the transfer function of a real integrator cannot lie in the origin, the real transfer function of a real integrator is provided with additional parasitic poles and zeros.  
         [0065]     Common requirements for microelectronic filters are small current consumption or small power demand, little noise, and sufficient linearity. For satisfying these requirements, the biquad filter  120  from  FIGS. 2 and 3  is preferably constructed according to the current-mode technology, for example described in the article “Accurate CMOS Current-Mode-Filters for High Frequencies and Low Power Consumption” by N. Christoffers et al. (Konferenzband der ANALOG&#39;02, pp. 343-48, Bremen 2002). The input voltage signal U in (s) of a current-mode biquad filter is at first converted to a current I in (s)=G m U in (s) by a transconductor with the transconductance G m . By filtering, which is described by the transfer function H biquad (s) of the biquad filter, then a current output signal I out (s)=H biquad (s)I in (s) is determined or calculated from the current input signal I in (s). The output voltage U out (s) results from the output current I in (s) by renewed conversion, U out (s)=I out (s)/G m =H biquad (s)U in (s).  
         [0066]     In the current-mode technology, the input and output signals of the integrators are currents. For this reason, the summation locations or the adders  136 ,  138  can be simplified to simple circuit nodes. According to Kirchoff&#39;s rule of nodes, a linear, noise-free and frequency-independent summation takes place without additional power demand.  
         [0067]      FIG. 4  shows a schematic circuit diagram of an integrator  150  with an input  152  and an output  154  in current-mode technology. The integrator  150  includes a capacitor C connected between the input  152  and ground  156 . The integrator  150  further includes a transconductor  158  with a transconductance G m , which is switched between the input  152  and the output  154  of the integrator  150 , i.e. an input of the transconductor  158  is connected to the input  152  of the integrator  150  and to the capacitor C, and an output  162  of the transconductor  158  is connected to the output  154  of the integrator. In case of an ideal transconductor  158 ,  
           I   out     ⁡     (   s   )       =         G   m     C     ⁢         I   in     ⁡     (   s   )       s             
 then applies for the connection between the input current I in  and the output current I out . 
 
         [0068]      FIG. 5  is a schematic circuit diagram of the biquad filter  120  in current-mode technology. The biquad filter  120  includes a first transconductor  170  with inputs  172   a ,  172   b  connected to the inputs  122   a ,  122   b  of the biquad filter  120  and outputs  174   a ,  174   b . A further transconductor  180  includes inputs  182   a ,  182   b  connected to the outputs  174   a ,  174   b  of the first transconductor  170  as well as outputs  184   a ,  184   b . A third transconductor  190  includes inputs  192   a ,  192   b  connected to the outputs  184   a ,  184   b  of the second transconductor  180  and the outputs  124   a ,  124   b  of the biquad filter and outputs  194   a ,  194   b  cross-connected to the outputs  174   a ,  174   b  of the first transconductor  170  and the inputs  182   a ,  182   b  of the second transconductor. Furthermore, the biquad filter  120  includes a third capacitor C 3 , the first electrode of which is connected to the first output  174   a  of the first transconductor  170 , the first input  182   a  of the second transconductor  180 , and the second output  194   b  of the third transconductor  190 , and the second electrode of which is connected to the second output  174   b  of the first transconductor  170 , the second input  182   b  of the second transconductor  180 , and the first output  194   a  of the third transconductor  190 . Furthermore, the biquad filter  120  includes a resistor R 3  connected in parallel to the third capacitor C 3 . Furthermore, the biquad filter  120  includes a fourth capacitor C 4 , the first electrode of which is connected to a first output  184   a  of the second transconductor  180 , the second input  192   a  of the third transconductor  190 , and the first output  124   a  of the biquad filter  120 , and the second electrode of which is connected to the second output  184   b  of the second transconductor  180 , the second input  192   b  of the third transconductor  190 , and the second output  124   b  of the biquad filter  120 .  
         [0069]     All three transconductors  170 ,  180 ,  190  preferably comprise, as it is shown in  FIG. 5 , the same transconductance G m . For the coefficients a 1 , a 2 , b 1 , b 2  in the above-identified formulae for the transfer function H 1 (s), H 2 (s) of the integrator  132 ,  134  illustrated in  FIG. 3  and in the transfer function H biquad (s) of the biquad filter  120 , a 1 =Gm/C 3 , a 2 =Gm/C 4 , b 1 =1/(G m R 3 ) and b 2 =1. Furthermore,  
       K   =       ω   0     =         G   m           C   3     ⁢     C   4           ⁢           ⁢   and           
       Q   =       R   3     ⁢     C   3     ⁢     ω   0           
 
 applies. 
 
         [0070]     The maximum direct current amplification attainable of the current-mode biquad filter is 1. Since, in reality, both s ∞1  and s ∞3  are finite (s ∞1 &gt;0, s ∞3 &gt;0), the biquad filter  120  attenuates this signal passing through and deteriorates its signal to noise ratio. With a finite output resistance R out  of each of three transconductors  170 ,  180 ,  190 ,  
         s     ∞   ⁢           ⁢   1       =         1       R   out     ⁢     C   3         ⁢             ⁢             ⁢   and   ⁢             ⁢             ⁢     s     ∞   ⁢           ⁢   3         =     1       R   out     ⁢     C   4               
 
 applies. 
 
         [0071]     In order to minimize the attenuation of the signal passing through the biquad filter  120  and the deterioration of the signal to noise ratio, accordingly, an output resistance R out  as great as possible is used.  
         [0072]     If the above identities for the coefficients a 1 , a 2 , b 1 , b 2  are set into the above-identified mathematical connections between the coefficients q n,LF  (n=1, 2) of the denominator polynomial Q LF (s) of the transfer function Z LF (s) of the loop filter and the coefficients a 1 , a 2 , b 1 , b 2  of the transfer functions H 1 (s), H 2 (s) of the integrators, determined according to the above-described method, 
 
 q   2,LF =1, 
 
 q   1,LF   =a   1   b   1   +s   ∞1   +s   ∞3 , 
 
 q   0,LF   =a   1   a   2   b   2   +a   1   b   1   s   ∞3   +s   ∞1   s   ∞3 , 
 
 one will obtain the equations  
             q     2   ,   LF       =   1     ,     
     ⁢       q     1   ,   LF       =             G   m       C   3       ⁢     1       G   m     ⁢     R   3           +     1       R   out     ⁢     C   3         +     1       R   out     ⁢     C   4           =       1       C   3     ⁢     R   3         +     1       R   out     ⁢     C   3         +     1       R   out     ⁢     C   4                 ⁢               
               q     0   ,   LF       =           G   m       C   3       ⁢       G   m       C   4         +         G   m       C   3       ⁢     1       G   m     ⁢     C   3         ⁢     1       R   out     ⁢     C   4           +       1       R   out     ⁢     C   3         ⁢     1       R   out     ⁢     C   4                         =         G   m   2         C   3     ⁢     C   4         +     1       C   3   2     ⁢     R   out     ⁢     C   4         +       1       R   out   2     ⁢     C   3     ⁢     C   4         .                 
 
         [0073]     These equations provide a direct connection between the coefficients q 0,LF =1, q 1,LF =1, q 2,LF  of the denominator polynomial Q LF (s) of the transfer function Z LF (s) of the loop filter on the one hand and the transconductance G m  of the transconductors and the resistances R 3 , R 4 , Rout and capacitances C 3 , C 4  on the other hand, which are acquired as described above. In a last synthesis step, thus, from these equations and the equations  
       K   =       ω   0     =         G   m           C   3     ⁢     C   4           ⁢           ⁢   and           
         Q   =       R   3     ⁢     C   3     ⁢     ω   0         ,       
 
 the device sizes Gm, R 3 , R 4 , R out , C 3 , C 4  for the construction of the inventive biquad filter are acquired. 
 
         [0074]     Typical device sizes of the devices from FIGS.  2  to  6  are: G m =7.5 μS, R 1 =66.3 kΩ, R 3 =137 kΩ, R T =100 kΩ, C 1 =118 pF, C 2 =14 pF, C 3 =C 4 =7.5 pF. The pole quality typically lies in the order of magnitude of 0.1 to 1, the pole frequency typically lies in the range of some 10 kHz.  FIG. 6  is a schematic circuit diagram showing a transconductor  200  according to a preferred embodiment of the present invention. The transconductor  200 , for example, can be used as one of the transconductors  170 ,  180 ,  190  from  FIG. 5 . The transconductor  200  is constructed according to the principle of a degenerated differential amplifier. In order to be able to use capacitors C 3 , C 4  with as-small-as-possible capacitances and therefore as-small-as-possible space requirements in an integrated circuit, a transconductance G m  in the range of a few μS is strived for. So small transconductances are hard to achieve with transistors in strong inversion. Transistors in weak inversion only have small output resistances and are therefore unsuited in view of the present object. Instead, a high transconductance G m  of the transistors used is adjusted. With the aid of a negative feedback by a resistor R T , the transconductance G m  of the transconductor  200  is set to  
         G   m     =       g   m       1   +       R   T     ⁡     (       g   m     +     g   mbs       )               
 
 wherein g mbs  is the bulk-source transconductance of the transistor as result of the substrate effect. 
 
         [0075]     The transconductor  200  has a substantially symmetrical construction of two substantially symmetrical branches  202 ,  204 . The first branch  202  includes four field-effect transistors  210 ,  210 ,  230 ,  240 , the channels or source-drain paths of which are connected between a supply voltage terminal  350  and a ground terminal  253 . The source of the first field-effect transistor  210  is connected to the supply voltage terminal  250 , the drain of the first field-effect transistor  310  is connected to the source of the second field-effect transistor  320 . The drain of the second field-effect transistor  220  is connected to the drain of the third field-effect transistor  230 , the source of the third field-effect transistor  230  is connected to the drain of the fourth field-effect transistor  240 , and the source of the fourth field-effect transistor  240  is connected to the ground terminal  252 . The cascode circuit of the first field-effect transistor  210  and the second field-effect transistor  220  serves for the generation of an especially high output resistance of the transconductor  200 , wherein a voltage U cmfb  is applied to the gate of the first field-effect transistor  210  via a first input  266  from a common-mode regulation described further below with reference to  FIG. 7 . A second input  264  corresponds to one of the inputs  172   a ,  172   b ,  182   a ,  182   b ,  192   a ,  192   b  in the transconductors  170 ,  180 , and  190  from  FIG. 5 , respectively, and is connected to the gate of the third field-effect transistor  230 . The bias current I BIAS , which is the drain current of the third field-effect transistor  30 , is controlled via the second input  264 . A third input  266  is connected to the gate of the fourth field-effect transistor  240  and forms an auxiliary input, the function of which will not be gone into in greater detail in the following. The drain of the second field-effect transistor  220  and the drain of the third field-effect transistor  230  are connected to an output  268  corresponding to one of the outputs  174   a ,  174   b ,  184   a ,  184   b ,  194   a ,  194   b  of the transconductors  170 ,  180 , and  190  from  FIG. 5 , respectively.  
         [0076]     The second branch  204  of the transconductor  200  is constructed symmetrically to the first branch  202 . The devices of the second branch  204  were given the same reference numerals as the corresponding devices of the first branch  202 , but supplemented by an apostrophe (&#39;). The source of the third field-effect transistor  230  of the first branch  202  and the drain of the fourth field-effect transistor  240  of the first branch  202  on the one hand and the source of the third field-effect transistor  230 ′ of the second branch  204  and the drain of the fourth field-effect transistor  240 ′ of the second branch  204  on the other hand are connected to each other via a resistor R T .  
         [0077]     For achieving high output resistance R out  of the transconductor  200 , the cascade M c /M cmfb  of the first field-effect transistor  210  and the second field-effect transistor  220  (the index “cmfb” stands for “common-mode feedback”; the parameter L stands for the gate length of the field-effect transistor) is used as load for the third field-effect transistor  230 . As a further measure for a high output resistance R out  of the transconductor, an output common-mode regulation is chosen, which does not resistively load the output  268 ,  268 ′.  
         [0078]      FIG. 7  is a schematic circuit diagram of an output common-mode circuit for the transconductor from  FIG. 6 . The output common-mode circuit includes a first field-effect transistor  282 , the drain of which is connected to a first supply voltage terminal  284 , the gate of which is connected to a first input  286 , and the source of which is connected to the drain of a second field-effect transistor  288 . The source of the second field-effect transistor  288  is connected to ground  290 , and the gate of the second field-effect transistor  288  is connected to a second input  292 . The drain of a third field-effect transistor  294  is connected to a second supply voltage terminal  296 , the gate of the third field-effect transistor  294  is connected to a third input  298 , and the source of the third field-effect transistor  294  is connected to the drain of a fourth field-effect transistor  300 . The source of the third field-effect transistor  300  is connected to ground  290 , and the gate of the fourth field-effect transistor  300  is, just like the gate of the second field-effect transistor  288 , connected to the second input  292 . The source of a fifth field-effect transistor  312  is connected to a third supply voltage terminal  304 , the gate and the drain of the fifth field-effect transistor  302  are connected to each other and to an output  306 , the drain of a sixth field-effect transistor  308  and the drain of a seventh field-effect transistor  310 . The gate of the sixth field-effect transistor  308  and the gate of the seventh field-effect transistor  310  are connected to each other and to a fourth input  312 . The source of the sixth field-effect transistor  308  is connected to the drain of an eighth field-effect transistor  314  and to the source of the first field-effect transistor  282  and to the drain of the second field-effect transistor  288  via a resistor  316 . The source of the seventh field-effect transistor  310  is connected to the drain of a ninth field-effect transistor  318  and to the source of the third field-effect transistor  294  and the drain of the fourth field-effect transistor  300  via a resistor  320 . The gate of the eighth field-effect transistor  314  and the gate of the ninth field-effect transistor  318  are, just like the gate of the second field-effect transistor  288  and the gate of the fourth field-effect transistor  300 , connected to the second input  292 . The source of the eighth field-effect transistor  314  and the source of the ninth field-effect transistor  318  are connected to ground. Apart from the fifth field-effect transistor  302 , all field-effect transistors  282 ,  288 ,  294 ,  300 ,  308 ,  310 ,  314 ,  318  are formed in substrate regions or wells connected to ground  290 . The fifth field-effect transistor  302  is formed in a substrate region or in a well connected to a fourth supply voltage terminal  322 .  
         [0079]     A voltage U cm,target  is present at the fourth input  312 . The drain currents of the second field-effect transistor  288 , of the fourth field-effect transistor  300 , of the eighth field-effect transistor  314 , and of the ninth field-effect transistor  318  are each I BCMFB . At the output  306 , the output common-mode regulation generates a voltage U cmfb , which is applied to the first input  262 ,  262 ′ of the two branches  202 ,  204  of the transconductor from  FIG. 6 .  
         [0080]     For the output common mode U cmout (s)  
           U   cmout     ⁡     (   s   )       =         Δ   ⁢           ⁢     I   ⁡     (   s   )         -     I   BIAS     +       U   dd         Z   Udd     ⁡     (   s   )         +     2   ⁢       W   cmfb       W   cmsens       ⁢     I   Bcmfb       -     2   ⁢     G   mcm     ⁢       W   cmfb       W   cmsens       ⁢     U     cm   ,   soll                     Z   Udd     ⁡     (   s   )       +       Z   gnd     ⁡     (   s   )               Z   Udd     ⁡     (   s   )       ⁢       Z   gnd     ⁡     (   s   )           +     2   ⁢     G   mcm     ⁢       W   cmfb       W   cmsens                 
 
 is found. 
 
         [0081]     Here, ΔI(s) is a disturbance caused by the deviation of the input common mode from the target value, U dd  the supply voltage, Z udd (s) the impedance between one of the two outputs and the supply voltage node, Z gnd (s) the impedance between the output  306  and the ground  219 , and G mcm (s) the transconductance of an individual differential stage in the output common-mode regulation.  
         [0082]     The greater the ratio G m W cmfb /W cmsens , the better the output common mode may be regulated off. The voltage at the output of the transconductor  200 , however, is not limited by the fact that a linear connection between I cmsens  and the output common mode exists only for  
         u   out     ⁢       &lt;&lt;       4   ⁢           ⁢     I   Bcmfb         G   mcm         .         
 
         [0083]     At greater voltages, the output common-mode regulation fails.  
         [0084]     Since the transconductor from  FIG. 6  and the output common-mode regulation from  FIG. 7  have to be adjusted so that  
         I   Bcmfb     ≈         W   cmsens       2   ⁢           ⁢     W   cmfb         ⁢     (       I   BIAS     -       U   dd         Z   Udd     ⁡     (   s   )           )           
 
 applies,  
         G   m     ⁢       W   cmfb       W   cmsens       ⁢       &lt;&lt;         I   BIAS     -       U   dd         Z   Udd     ⁡     (   s   )             u   out         .         
 
         [0085]     For this reason, the output common-mode regulation becomes the weaker, the greater the maximum output amplitude is.  
         [0086]      FIG. 8  shows a Bode diagram of a simulated transfer function of a transconductor, as it is illustrated in  FIG. 6 . The transconductance Gm of the transconductor is G m =7.5 μS. Furthermore, in the simulation, a load capacitance of C=12.5 pF connected downstream of the outputs  268 ,  268 ′ of the transconductor  200  was assumed. The frequency f of a harmonic signal present at the input  262 ,  262 ′ of the transconductor  300  is associated with the abscissa in logarithmic graduation. With the ordinates, the “attenuation” of the transconductor  200  and the logarithmic ratio log (A out /A in ) of the amplitude A out  of the output signal output at the output  268 ,  268 ′ and the harmonic signal A in  (top) received at the input  262 ,  262 ′ and the phase φ (bottom), respectively, are associated.  
         [0087]     The frequency of the lowest-frequency pole of the transfer function lies at f=6 kHz. A zero and further poles lie at frequencies in the order of magnitude of some hundreds of MHz, and thus far outside the bandwidth strived for of the biquad filter to be formed with the transconductor. The current consumption of the transconductor  200  from  FIG. 6  without the common-mode regulation from  FIG. 7  is 30 μA.  
         [0088]      FIG. 9  is a schematic diagram showing the simulated transfer function of a biquad filter with transconductors, as they are illustrated in  FIG. 6 , in a Bode diagram. The frequency f of a harmonic input signal present at the input of the biquad filter is again associated with the abscissa. The attenuation of the biquad filter (log(A out /A in ) above) and the phase difference Δφ between the harmonic input signal present at the input of the biquad filter and the output signal present at the output of the biquad filter, respectively, are associated with the ordinate. The direct current amplification of the biquad filter, according to expectations, is only minus 0.1 dB. In the area of f≈70 kHz, there is the phase jump associated with the pole pair of the transfer function of the biquad filter, at which the phase difference changes by Δφ=π=180°. At high frequencies f&gt;&gt;10 MHz, magnitude and phase of the transfer function take on great errors attributable to the additional poles and zeros.  
         [0089]     The above statements show that, using biquad filters in a loop filter of a phase locked loop, the settling time T of a ΣΔ fractional-N frequency generator can be substantially shortened. Integrators and biquad filters in the current-mode technology distinguish themselves by small power demand, whereby also the power demand of the loop filter is comparably very small. The described transconductor is based on a degenerated differential amplifier. This enables a very small transconductance of the transconductor.  
         [0090]     The above-described output common-mode regulation measures the output common mode with the aid of a resistive voltage splitter to avoid loading the output of the transconductor and enable high output resistance thereof. Instead, the output common mode is measured with the aid of two differential amplifiers. The output common-mode regulation achieved has great linearity.  
         [0091]     In  FIG. 9 , it can be seen that undesired zeros and poles of the transfer function of the inventive biquad filter only occur at frequencies above about 100 MHz. This shows the versatile applicability of the current-mode biquad filters described.  
         [0092]     The present invention can be implemented as a frequency generator, as a method of generating an oscillating output signal, and as a method, a computer program, and an apparatus for designing a frequency generator. The inventive computer program includes program code for performing the described inventive method of designing a frequency generator, wherein the method of designing is executed when the computer program is executed on a computer.  
         [0093]     While this invention has been described in terms of several preferred embodiments, there are alterations, permutations, and equivalents which fall within the scope of this invention. It should also be noted that there are many alternative ways of implementing the methods and compositions of the present invention. It is therefore intended that the following appended claims be interpreted as including all such alterations, permutations, and equivalents as fall within the true spirit and scope of the present invention.