Abstract:
A non-volatile memory cell and method of writing data thereto. In accordance with some embodiments, the memory cell includes first and second resistive memory elements (RMEs) configured to concurrently store complementary programmed resistive states. The first RME is programmed to a first resistive state and the second RME is concurrently programmed to a second resistive state by application of a common write current in a selected direction through the memory cell.

Description:
RELATED APPLICATION  
       [0001]    The present application makes a claim of domestic priority under 35 U.S.C. §119(e) to U.S. Provisional Patent Application No. 61/104,072 filed Oct. 9, 2008. 
     
    
     BACKGROUND  
       [0002]    Data storage devices can be used to store and retrieve user data in a fast and effective manner. Some data storage devices utilize a semiconductor array of solid-state memory cells to store data. The memory cells can be volatile or non-volatile. Some non-volatile memory cells can be provided with a 1T1R configuration with a single transistor (“T”) and a single programmable resistive memory element (“R”). 
         [0003]    The resistive memory element is programmable to different resistive states through the application of write currents to the memory cell, and these different resistive states can be used to denote different logical states (e.g., logical 0, 1, 10, etc.). The programmed state of the resistive memory element can be sensed by application of a read current to the memory cell, and a comparison of the voltage drop across the cell with a reference voltage using a sense amplifier. The memory cell transistor serves as a switching device to facilitate access to the memory cell during write and read operations, and to decouple the memory cell from adjacent cells at other times. 
         [0004]    A number of resistive memory element (RME) constructions are known, including without limitation magnetic random access memory (MRAM), spin-torque transfer random access memory (STRAM), resistive random access memory (RRAM), phase change random access memory (PCRAM), and programmable metallic cells (PMCs). While operable, a limitation with these and other RME constructions relates to difficulties in reliably sensing the different resistive states to which the cells are programmed. Significant portions of the available semiconductor area may be allocated for circuitry used during read and write operations. This increased overhead can limit overall data storage densities for a given semiconductor size. 
       SUMMARY  
       [0005]    Various embodiments of the present invention are directed to a non-volatile memory cell and a method of writing data thereto. 
         [0006]    In accordance with some embodiments, the non-volatile memory cell includes first and second resistive memory elements (RMEs) configured to concurrently store complementary programmed resistive states. The first RME is programmed to a first resistive state and the second RME is concurrently programmed to a second resistive state by application of a common write current through the memory cell. 
         [0007]    In accordance with other embodiments, the method generally comprises providing a non-volatile memory cell comprising first and second resistive memory elements (RMEs) configured to concurrently store complementary programmed resistive states. A common write current is applied through the memory cell to concurrently program the first RME to a first resistive state and the second RME to a second resistive state. 
         [0008]    These and other features and advantages which characterize the various embodiments of the present invention can be understood in view of the following detailed discussion and the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0009]      FIG. 1  shows an exemplary data storage device in accordance with various embodiments of the present invention. 
           [0010]      FIG. 2  is a schematic depiction of a memory cell of the device of  FIG. 1 . 
           [0011]      FIG. 3  provides an elevational representation of the memory cell of  FIG. 2 . 
           [0012]      FIG. 4  shows the memory cells of  FIGS. 2-3  arranged into rows and columns. 
           [0013]      FIG. 5  provides a schematic depiction of control circuitry in accordance with various embodiments to carry out write and read operations on the memory cells of  FIG. 4 . 
           [0014]      FIG. 6  is a timing diagram corresponding to the control circuitry of  FIG. 5 . 
       
    
    
     DETAILED DESCRIPTION  
       [0015]      FIG. 1  provides a functional block representation of a data storage device  100  constructed and operated in accordance with various embodiments of the present invention. Top level control of the device  100  is carried out by a suitable controller  102 , which may be a programmable or hardware based microcontroller. The controller  102  communicates with a host device via a controller interface (I/F) circuit  104 . A memory space  106  comprises a number of memory arrays  108  (denoted Array  0 -N). Each array  108  comprises a block of semiconductor memory of selected storage capacity. 
         [0016]      FIG. 2  shows an exemplary construction for a memory cell  110  of the memory space  106  of  FIG. 1 . The memory cell  110  has a complementary 2T2R configuration, with first and second resistive memory elements (RMEs)  112 ,  114  and first and second switching devices  116 ,  118 . In some embodiments, the switching devices  116  and  118  are characterized as n-channel metal oxide semiconductor field effect transistors (NMOSFETs). 
         [0017]    The RMEs  112 ,  114  are each selectively programmable to different resistive states, such as a high resistance or a low resistance. The programmed states are complementary in that when the first RME  112  is programmed high, the second RME  114  is concurrently programmed low, and vice versa. As explained below, this cell configuration facilitates improved sensing margin and enhanced data transfer rate performance including high data rate page-mode read operations. 
         [0018]    An overall memory state of the cell  110  can be determined in relation to the programmed state of the first RME  112 ; for example, the memory cell  110  may be identified as storing a logical 0 when the first RME  112  is programmed to the low resistance and the second RME  114  is programmed to the high resistance. The memory cell  110  may be alternatively identified as storing a logical 1 when the first RME  112  is programmed to the high resistance and the second RME  114  is programmed to the low resistance. 
         [0019]    The memory cell  110  is connected between complementary bit lines  120 ,  122  denoted BL and BL′. A cell plate (CP) line  124  is provided between the cell transistors  116 ,  118 . A word line (WL)  126  is connected to respective control gates of the transistors  116 ,  118 . 
         [0020]      FIG. 3  shows an elevational semiconductor representation of the memory cell  110  of  FIG. 2  in accordance with some embodiments. It will be appreciated that other cell configurations can be used as desired. Regions of n+doped material  128 ,  130  and  132  are formed in a semiconductor substrate  134 . Isolated control gates  136 ,  138  span adjacent pairs of the doped regions to form the first and second transistors  116 ,  118 . 
         [0021]    A support structure  140  establishes the aforementioned CP line connection with the middle doped region  130 . Support structures  142  and  144  respectively support and interconnect the first and second RMEs  112 ,  114  with the regions  128  and  132 . 
         [0022]    The first and second RMEs  112 ,  114  are characterized in  FIG. 3  as magnetic tunneling junctions (MTJs) of a spin-torque transfer random access memory (STRAM). Each MTJ includes a fixed reference layer (RL)  146  and a free layer (FL)  148  separated by an intervening tunneling barrier layer  150 . Each reference layer  146  has a fixed magnetic orientation in a selected direction, such as via pinning to a separate permanent magnet layer (not shown). 
         [0023]    The free layers  148  each have a variable magnetic orientation that can be aligned in the same direction as the associated reference layer  146  (parallel) or in an opposing direction as the associated reference layer  146  (anti-parallel). The MTJs will have a low resistance in the parallel state and a high resistance in the anti-parallel state. These respective states can be obtained by passing write currents of suitable magnitude and pulse width through the MTJs in opposing (bipolar) directions. 
         [0024]    While the RMEs  112 ,  114  have been characterized as MTJs in  FIG. 3 , it will be appreciated that such is exemplary and not limiting. Other RME configurations can readily be used including but not limited to MRAM, RRAM, and PMC structures. Suitable RME configurations can include structures that are programmable to different states with the application of bipolar write currents. The first RME  112  can be provided with the same physical orientation within the cell as the second RME  114 , as shown in  FIG. 3 , or the RMEs can be provided with opposing physical orientations. 
         [0025]    In some embodiments, the memory cells  110  are arranged into columns of memory cells in the array  108 . Two such columns are identified at  152  and  154  in  FIG. 4 . Each column is connected between adjacent, complementary bit lines BL  120  and BL′  122 , and includes a selected number of memory cells  0 -N. 
         [0026]    Adjacent memory cells  110  in the respective columns  152 ,  154  form rows  156  of selected length. The cells along each row  156  are coupled to a separate word line  126 , denoted WL 0  to WLN in  FIG. 4 . Each row  156  of cells will be referred to herein as a page of memory, although such is not limiting. 
         [0027]      FIG. 5  shows control circuitry  160  used during write and read operations upon the memory cells  110  in accordance with various embodiments. A separate set of the control circuitry  160  in  FIG. 5  can be provided for each column, and will fit within the 2T2R width of the associated column. For clarity, it will be contemplated that the circuitry  160  in  FIG. 5  is coupled to the memory cells  110  in column  152  in  FIG. 4 . 
         [0028]    The control circuitry  160  includes a sense amplifier  162 , an equalization circuit  164  and a write circuit  166 . The sense amplifier  162  is utilized during read operations and includes n-channel switching devices (transistors)  168 ,  169  and p-channel switching devices (transistors)  170 ,  171  cross-connected as shown. The equalization circuit  164  provides voltage equalization prior to a read operation and includes transistors  172 ,  173  and  174 . The write driver  166  is utilized to write the complementary states to the memory cells  110  and includes complementary driver circuits  175 ,  176  and four switching transistors  177 ,  178 ,  179  and  180 . 
         [0029]    A number of control signals are supplied to or from the circuitry  160  during respective write and read operations. These signals include sense amplifier differential outputs SAP and SAN via lines  180 ,  182 ; a bit line precharge V PRE  signal via path  184 ; an equalization enable EQ signal via line  186 ; a current select CSL signal via line  188 ; and a write enable WE signal via line  190 . A corresponding timing diagram  200  for selected ones of these signals is set forth in  FIG. 6 . 
         [0030]    During a read operation, the bit lines BL, BL′  120 ,  122  are precharged to the V PRE  voltage level. This can be carried out by supplying the V PRE  voltage to line  184  and asserting the EQ signal, as shown in  FIG. 6  at  202 . The cell plate CP line  124  is set to an appropriate voltage V CP , such as 0.5V CC  where V CC  is a selected source voltage level (such as about +3.0V). The precharge voltage V PRE  will be less than V CC  and greater than V CP  (i.e., V CC &gt;V PRE &gt;0.5V CC ). 
         [0031]    The associated word line WL  126  for the selected memory cell  110  to be read is asserted high ( 204  in  FIG. 6 ), which allows the charge stored on the bit lines BL, BL′ to begin discharging through the respective RMEs  112 ,  114  of the selected cell to the CP line  124 . Because the respective resistances of the RMEs  112 ,  114  will be different (e.g., one high and one low), the speed of discharge from the respective bit lines BL, BL′ will be different. 
         [0032]    Upon deassertion of the word line WL  126  and activation of the SAP and SAN via lines  180  and  182 , the sense amplifier  162  will initiate sensing of the differential voltages of the bit lines BL, BL′ as exemplified at  206  and  208  in  FIG. 6 . These voltages will indicate the stored state of the memory cell  110 . For example, if the programmed resistance of the first RME  112  is higher than that of the second RME  114 , the BL′ will discharge at a greater rate than the BL, so that the voltage on the BL will be greater than that of the BL′ when the WL is deasserted. 
         [0033]    The bit line differential voltages will be respectively outputted and will indicate the stored state of the memory cell  110  (see signals  206 ,  208  in  FIG. 6 ). The foregoing read operations can be simultaneously carried out for each memory cell  110  along a selected row  156  ( FIG. 4 ), allowing simultaneous page-mode reading and latching of the contents of each row (page) in the array. 
         [0034]    To write a selected memory state to the selected cell  110 , the WL  126  for the selected cell is asserted high. The CSL and WE signals on lines  188 ,  190  are also asserted high, allowing bipolar write currents to be respectively supplied by the driver circuits  175 ,  176  through the selected cell  110 . A first direction of write current can be from the BL  120  to the BL′  122 , and an opposing, second direction of write current can be from the BL′  122  to the BL  120 . 
         [0035]    In some embodiments the first write current from BL to BL′ can operate to concurrently set the first RME  112  to a first programmed state (such as the parallel, low resistance state) and the second RME  114  to a second programmed state (such as the anti-parallel, high resistance state). The second write current from BL′ to BL can correspondingly operate to concurrently set the first RME  112  to a second programmed state (such as the anti-parallel, high resistance state) and the second RME to the first programmed state (such as the parallel, low resistance state). 
         [0036]    As can be appreciated by one skilled in the art, the various embodiments illustrated herein provide a number of advantages over the prior art, including higher sensing margin, self-referenced read sensing, smaller total semiconductor (chip) area, and faster readout via page-mode reading. It will be appreciated that the various embodiments discussed herein have numerous potential applications and are not limited to a certain field of electronic media or type of data storage devices. 
         [0037]    It is to be understood that even though numerous characteristics and advantages of various embodiments of the present invention have been set forth in the foregoing description, together with details of the structure and function of various embodiments of the invention, this detailed description is illustrative only, and changes may be made in detail, especially in matters of structure and arrangements of parts within the principles of the present invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.