Abstract:
In a Constant Access Time Bounded (CATB) cache, if a dirty line in a search group of the cache is selected for eviction from the cache, marking the dirty line as evicted, selecting a replacement line from a reserve, and inserting the replacement line into the search group.

Description:
BACKGROUND  
       [0001]     Caching is a well-known technique that uses a smaller, faster storage device to speed up access to data stored in a larger, slower storage device. A typical application of caching is found in disk access technology. A processor based system accessing data on a hard disk drive, for example, may achieve improved performance if a cache implemented in solid state memory that has a lower access time than the drive is interposed between the drive and the processor. As is well known to those skilled in the art, such a cache is populated by data from the disk that is accessed by the system and subsequent accesses to the same data can then be made to the cache instead of to the disk, thereby speeding up performance. The use of caching imposes certain constraints on the design of a system, such as a requirement of cache consistency with the main storage device, e.g. when data is written to the cache, as well as performance based constraints which dictate, e.g. what parts of the cache are to be replaced when a data access is made to a data element that is not in the cache and the cache happens to be full (cache replacement policy).  
         [0002]     A well known design for caches, specifically for disk caches, is an N-way set associative cache, where N is some non-zero whole number. In such a design, the cache may be implemented as a collection of N arrays of cache lines, each array representing a set, each set in turn having as members only such data elements, or, simply, elements, from the disk whose addresses map to a set based on an easily computed mapping function. Thus, in the case of a disk cache, any element on a disk can be quickly mapped to a set in the cache by, for example, obtaining the integer value resulting from performing a modulus of the address of the element on disk, that is, its tag, with the number of sets, N, in the cache (the tag MOD N) the result being a number that uniquely maps the element to a set. Many other methods may be employed to map a line to a set in a cache, including bit shifting of the tag, or any other unique set of bits associated with the line, to obtain an index for a set; performing a logical AND between the tag or other unique identifier and a mask; XOR-ing the tag or other unique identifier with a mask to derive a set number, among others well known to those skilled in the art, and the claimed subject matter is not limited to any one or more of these methods.  
         [0003]     To locate an element in a set associative cache, the system uses the address of the data on the disk to compute the set in which the element would reside, and then in a typical implementation searches through the array representing the set until a match is found, or it is determined that the element is not in the set.  
         [0004]     A similar implementation of a cache may use a hash table instead of associative sets to organize a cache. In such a cache, once again, elements are organized into fixed size arrays, usually of equal sizes. However, in this instance, a hashing function is used to compute the array (termed a hash bucket) within which an element is located. The input to the hashing function may be based on the element&#39;s tag and the function then maps the element to a particular hash bucket. Hashing functions and their uses for accessing data and cache organization are well known and are not discussed here in detail.  
         [0005]     To simplify the exposition of the subject matter in this application, the term Constant Access Time Bounded (CATB) is introduced to describe cache designs including the set associative and hash table based caches described above. A key feature of CATB caches in the art is that they are organized into fixed sized arrays, generally of equal size, each of which is addressable in constant time based on some unique aspect of a cache element such as its tag. Other designs for CATB caches may be readily apparent to one skilled in the art. In general the access time to locate an element in a CATB cache is bounded by a constant, or at least is independent of the total cache size, because the time to identify an array is constant and each array is of a fixed size, and so searching within the array is bounded by a constant. For uniformity of terminology, the term search group is used to refer to the array (i.e. the set in a set associative cache or the hash bucket in the hash table based cache) that is identified by mapping an element.  
         [0006]     Each element in a CATB cache, or cache line, contains both the actual data from the slower storage device that is being accessed by the system as well as some other data termed metadata that is used by the cache management system for administrative purposes. The metadata may include a tag i.e. the unique identifier or address for the data in the line, and other data relating to the state of the line including a bit or flag to indicate if the line is in use (allocated) or not in use (unallocated), as well as bits reserved for other purposes.  
         [0007]     Typically, caches are used for both reading and writing data. Generally there are two types of policies that caches may use for writing data to a location that is in the cache. One is termed a write through policy and the other a write-back policy. In a write through cache, data modified at a location that is in a cache is also immediately written to the main storage device, such as a disk. This ensures consistency between the main storage device and the cache, but may impose a performance penalty, because writing to the main storage device is usually significantly slower than writing to the cache. A write-back cache, however, does not immediately write data that is modified in the cache back to the main storage device. Rather, the cache management system waits until an appropriate time to write the data back to the main storage device, such as when the system is idle. During the time between the modification of data in the cache and time the data is written back to main storage, the cache line with the modified data is not consistent with the corresponding location in main storage and is said to be dirty.  
         [0008]     A problem arises when in the course of the operation of the cache, a cache line that the cache replacement policy chooses for eviction from the cache also happens to be dirty. After the data in the cache line is evicted, in a typical cache, the cache line is overwritten by new data. To ensure consistency with main storage, therefore, the modified data in the dirty cache line chosen for eviction may have to be written back to main storage before the line can be evicted. This generally produces an undesirable performance penalty for the system at a time when the system is not idling. Alternatively, in systems where power consumption is an issue, a write-back may cause additional power consumption if a disk drive needs to be spun up from a low power consuming state in order to accomplish the write to the disk. This problem is termed the dirty evict problem. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]      FIG. 1  depicts a data structure that may be used to implement an N-way set associative cache in an embodiment of the claimed subject matter.  
         [0010]      FIG. 2  depicts the cache of  FIG. 1  in a state where a dirty cache line has been selected for eviction in this embodiment of the claimed subject matter.  
         [0011]      FIG. 3  depicts the cache of  FIG. 2  in a state where the cache line has been marked as evicted and a new line has been added to the set from a dirty evict reserve to replace the evicted line in this embodiment of the claimed subject matter.  
         [0012]      FIG. 4  depicts the cache of  FIG. 3  in a state following write-back of the evicted line showing the line that previously contained the dirty evicted data returned to the dirty evict reserve in this embodiment of the claimed subject matter.  
         [0013]      FIG. 5  depicts a first flowchart depicting processing in an embodiment of the claimed subject matter.  
         [0014]      FIG. 6  depicts a second flowchart depicting processing in an embodiment of the claimed subject matter.  
         [0015]      FIG. 7  depicts a processor based system in accordance with one embodiment of the claimed subject matter. 
     
    
     DETAILED DESCRIPTION  
       [0016]     In one embodiment of the claimed subject matter, a non-volatile memory unit is used to implement a disk cache with a portion of the cache reserved to replace lines containing dirty evicted data as shown in  FIG. 1 . In the figure, a portion of the unallocated cache line, termed the dirty evict reserve  160 , is reserved for use when a dirty line is evicted from the cache. The lines in this reserve are placed in a linked list as shown,  180 . The remaining cache lines  120  are allocated to N sets  100  to form a set associative cache using an array of linked lists, in this embodiment. In other embodiments in accordance with the claimed subject matter, a cache may be implemented in a volatile store unlike the embodiment discussed above. The cache may, in yet other embodiments, serve as a cache for purposes other than disk cache, e.g. a networked data or database cache. The actual organization of the sets of the cache may also differ from that shown in the figure in some embodiments of the claimed subject matter. For example, the sets in the cache may or may not be of exactly equal sizes. In some embodiments of the claimed subject matter, a different basic data structure such as a hash table or other structure suitable for CATB caches may be used. Other terms such as ‘elements’ or ‘storage elements’ or ‘entries’ may be used to describe cache lines in other embodiments. These alternative embodiments are discussed to illustrate the many possible forms that an embodiment in accordance with the claimed subject matter may take and are not intended to limit the claimed subject matter only to the discussed embodiments.  
         [0017]     A processor based system such as the one depicted in  FIG. 7  implements one exemplary embodiment of the claimed subject matter. The figure shows a processor  720  connected via a bus system  740  to a memory  760  and a disk and cache system including a disk  780  and a disk cache  700 . In this implementation, the disk cache  700  may be implemented in volatile or in non-volatile memory. The processor may execute programs and access data, causing data to be read and written to disk  780  and consequently cached in disk cache  700 . The system of  FIG. 7  is of course merely representative. Many other variations on a processor based system are possible including variations in processor number, bus organization, memory organization, and number and types of disks. Furthermore, the claimed subject matter is not restricted to process based systems in particular, but may be extended to caches in general as described in the claims.  
         [0018]      FIG. 2  depicts a snapshot of the cache of  FIG. 1  during its operation. To simplify the figure, one of the N sets, numbered k, is depicted. The operation of other sets in the cache in this embodiment is similar. At this point in its operation, a number of lines  260 ,  280  in this set have become “dirty” because a process has written data to these lines but the data has not yet been written out to the disk. Some of the dirty lines,  280 , have been selected for eviction by a cache eviction algorithm. As in the previous figure, a number of unallocated lines  240  is available in the dirty evict reserve, implemented as a linked list in this embodiment of the claimed subject matter.  
         [0019]     In  FIG. 3 , a cache management system responds to the selection of lines such as  340  in set k that are dirty and to be evicted by marking such lines as evicted. The lines are not, however, actually evicted at this stage. Instead, as shown at  360 , a new line is added to the set from the dirty evict reserve to allow continued operation of the set-associative cache of this embodiment with the same number of elements available in set k as were available before line  340  was marked for eviction. So, in one instance, if the line  340  were marked as evicted because new data was to be added to set k, the new data would be added, but into line  360  instead of into line  340 . As such, this allows the cache to continue operation at the same level of performance as it had before the eviction. Further, the fact that the evicted line is still in the correct set for its tag means that cache integrity with respect to the data in the evicted line is preserved. This in turn implies that the evicted line need not be written back to disk immediately, and integrity will still be preserved. Other lines in the set that are dirty but are not yet to be evicted such as  380 , of course, may also remain in the cache as before for normal operation.  
         [0020]      FIG. 5  depicts steps in the processing that is pictorially depicted in  FIG. 3 . In  FIG. 5 , the starting point is a state where the cache management system has determined that a dirty line is to be evicted, and a new line of data is to be inserted in its place. In processing in an embodiment in accordance with the claimed subject matter, the dirty line that is to be evicted is marked as evicted, but is not removed from the set,  500 . Instead, a new line is removed from an evict reserve  520  and any new data that is to be inserted into the set is stored in the new line  540 . The new line is then added to the set,  560 .  
         [0021]      FIG. 4  shows the cache and specifically set k after the cache management system in this embodiment has determined that it may write the evicted data back to disk. The system may do this based on several criteria. First, if performance is critical, the system may wait to do a write-back until the processor based system of the embodiment is idle, so that write-back does not impact other activities of the system. Alternatively, the cache management system may wait to piggyback the write-back on the tail end of some other disk write operation before the disk is idled, thus preventing power-consuming spin-ups of the hard drive in an embodiment of the claimed subject matter implemented in a power-critical application such as in a battery powered notebook computer or PDA. The choice of the time at which write-backs of dirty evicted data may be made based on these and other factors depending on the application. A discussion of such factors is outside the scope of this application. The key point is that write-backs resulting from dirty evicts may be managed as described above and delayed until an appropriate opportunity for a write-back presents itself.  
         [0022]     As before this description of the operation of a cache embodying the claimed subject matter is not limiting. Many other embodiments are possible. For one example, data structures other than linked lists may be used to store the cache lines available in the dirty evict reserve. While in this embodiment the non-evicted lines across the sets appear to stay equal, other embodiments may not maintain exact equality of the number of non-evicted lines across sets of the cache. These alternative embodiments are discussed to illustrate the many possible forms that an embodiment in accordance with the claimed subject matter may take and are not intended to limit the claimed subject matter only to the discussed embodiments.  
         [0023]     In implementations in some embodiments in accordance with the claimed subject matter, a set associative cache with a reserved list for the replacement of evicted lines may be implemented in non-volatile memory, i.e. in a device that retains its data integrity after external power to the device is shut off as may happen if a system is shut down or in a power failure. This may include, in one exemplary embodiment, a cache implemented with non-volatile memory as a disk cache. In such an implementation, it may be possible to recover the state of the cache following a power-down event after power is restored. The addition of a reserved group of cache lines for dirty evicted data as described above does not impact such a recovery.  FIG. 5  is a flowchart of a process that might be used to accomplish a recovery in an implementation of this nature.  
         [0024]     In  FIG. 6 , a recovery process as implemented in one embodiment of the claimed subject matter is shown. The process first inspects each line in the non-volatile cache,  600 - 640 . As long as there are more lines to inspect,  600 , the process inspects the next line  610 . If the line has metadata in which the status information indicates that the line is allocated, i.e. contains valid cached data, it is inserted into the set identified by computing the set&#39;s identifier from the tag of the line,  640 . If the line is unallocated, it may be added to a pool of unallocated lines in some manner,  630 . When all lines are processed, the recovery then enters a second phase, in which each set formed in the first phase of the recovery in a second phase is inspected,  650 - 690 . As long as there are more unprocessed sets  650 , the next unprocessed set is inspected. For each set that has less than a target number of lines, the recovery procedure adds lines from the pool of unallocated lines to the set to maintain a balanced number of lines across all sets,  670 ,  680 . Any remaining lines are returned to the reserve,  690 . Note that at the end of the process, all sets contain the same lines with the same metadata as they did before the power loss, including lines marked as dirty and/or evicted.  
         [0025]     Many other embodiments in accordance with the claimed subject matter relating to this recovery process are possible. For example, in some embodiments, the sets produced by the reconstruction process may not be exactly balanced. In others, the process of allocating allocated lines to sets may differ. These alternative embodiments are discussed to illustrate the many possible forms that an embodiment in accordance with the claimed subject matter may take and are not intended to limit the claimed subject matter only to the discussed embodiments.  
         [0026]     Embodiments in accordance with the claimed subject matter include various steps. The steps in these embodiments may be performed by hardware devices, or may be embodied in machine-executable instructions, which may be used to cause a general-purpose or special-purpose processor or logic circuits programmed with the instructions to perform the steps. Alternatively, the steps may be performed by a combination of hardware and software. Embodiments in accordance with the claimed subject matter may be provided as a computer program product that may include a machine-readable medium having stored thereon data which when accessed by a machine may cause the machine to perform a process according to the claimed subject matter. The machine-readable medium may include, but is not limited to, floppy diskettes, optical disks, DVD-ROM disks, DVD-RAM disks, DVD-RW disks, DVD+RW disks, CD-R disks, CD-RW disks, CD-ROM disks, and magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, magnet or optical cards, flash memory, or other type of media/machine-readable medium suitable for storing electronic instructions. Moreover, embodiments of the claimed subject matter may also be downloaded as a computer program product, wherein the program may be transferred from a remote computer to a requesting computer by way of data signals embodied in a carrier wave or other propagation medium via a communication link (e.g., a modem or network connection).  
         [0027]     Many of the methods are described in their most basic form but steps can be added to or deleted from any of the methods and information can be added or subtracted from any of the described messages without departing from the basic scope of the claimed subject matter. It will be apparent to those skilled in the art that many further modifications and adaptations can be made. The particular embodiments are not provided to limit the invention but to illustrate it. The scope of the claimed subject matter is not to be determined by the specific examples provided above but only by the claims below