Abstract:
Techniques for detecting jammer signals in a received signal are described. In one aspect, high-speed current mirror resistive compensation circuits and output impedance boosting circuits are utilized to increase amplifier bandwidth in an improved wideband amplifier circuit. In another aspect, a dual transistor configuration including common source topology, averaging capacitors and a comparator circuit is utilized to improve the sensing of signal peaks in a peak detector block, which can be used together with the wideband amplifier circuit and a digital jammer detection circuit to detect jammer signals. The digital jammer detection circuit aids in the determination of the presence of jammer signals within the received signal, the determination of which may be variable due to programmability of the digital jammer detection circuit as described.

Description:
CLAIM OF PRIORITY UNDER 35 U.S.C. §119 
       [0001]    The present application for patent claims priority to Provisional Application No. 61/165,090 entitled, “Wideband Jammer Detector” filed Mar. 31, 2009, and assigned to the assignee hereof and hereby expressly incorporated by reference herein. 
     
    
     TECHNICAL FIELD 
       [0002]    The present disclosure relates generally to electronics, and more specifically to a wideband jammer detector. 
       BACKGROUND 
       [0003]    In communication devices, such as Code Division Multiple Access (CDMA) Global System for Mobile communications (GSM) and Wireless Local Area Network (WLAN) communication devices, the ability to detect jammer signals is necessary to improve the performance of the communication device. Communication devices include receiver circuits, which utilize correlation circuits to decipher a desired communication signal from all other received signals. Device performance is degraded when jammer signals are present during the correlation process. 
         [0004]    Jammer signals can be introduced by internal or external sources. An internal jammer signal is a jammer signal which is introduced by the receiver. An example is a clock spur generated by a voltage controlled oscillator (VCO) within the receiver. 
         [0005]    An external jammer signal is a jammer signal, which is introduced by a source external to the receiver. An example is a signal transmitted by a transmitter in another communication device that generates out-of-band emissions in the receive frequency band of the receiver. 
         [0006]    A jammer signal impacts the sensitivity of a receiver in two ways. It can for example de-sense an analog-to-digital converter in the receiver thereby degrading its sensitivity. A jammer signal that appears at odd harmonics of a local oscillator signal in the receiver is down converted into the receive band to degrade signal sensitivity at baseband. Thus, errors may be introduced into the demodulated data packet when jammer signals are not detected by the receiver. 
         [0007]    All jammer signals can thus degrade the performance of the receiver within the communication device, and ultimately the device&#39;s ability to process signals. Therefore, the ability to detect as many jammer signals as possible, even very low power jammer signals, helps to improve the performance of the receiver within the communication device. 
         [0008]    In a typical CDMA device, for example, when a CDMA jammer signal is present, the receiver goes into protected mode where a decision is made by a jammer detector. The jammer detector detects close in jammer signals, such as jammer signals close to the receive (RX) band. A wideband jammer detector is capable of also detecting jammer signals hundreds of MHz away from the RX band. A jammer detector allows the receiver to operate in an un-protected or low power mode when no jammer signal is present and in protected or high power mode in the presence of jammer signals. 
         [0009]    There is a need for a wideband jammer detector capable of detecting low power jammer signals over a wide bandwidth while consuming a minimal amount of power. 
       SUMMARY 
       [0010]    This disclosure describes in general techniques for detecting jammer signals in a received signal. 
         [0011]    In one aspect of the invention high-speed current mirror resistive compensation circuits and output impedance boosting circuits are utilized to increase amplifier bandwidth in an improved wideband amplifier circuit. 
         [0012]    In another aspect of the invention, a dual transistor configuration including common source topology, averaging capacitors and a comparator circuit is utilized to improve the sensing of signal peaks in a peak detector block. 
         [0013]    In another aspect of the invention, the peak detector block is used together with the wideband amplifier circuit and a digital jammer detection circuit to detect jammer signals. 
         [0014]    In yet another aspect of the invention, the wideband amplifier circuit is used together with a peak detection circuit, a comparator circuit and a digital jammer detection circuit form a wideband jammer detector to detect jammer signals in a received signal of a communication device. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]      FIG. 1  is a block diagram of a receiver with a wideband jammer detector. 
           [0016]      FIGS. 2A and 2B  are circuit level diagrams of a standard current mirror resistive compensation circuit and a high-speed current mirror resistive compensation circuit, respectively. 
           [0017]      FIG. 3  is a schematic diagram of a wideband amplifier circuit, a peak detector block and a digital jammer detection circuit in accordance with an exemplary embodiment. 
           [0018]      FIG. 4  shows a schematic diagram of a peak detector block in accordance with a further exemplary embodiment which can be used to peak detect the output RF 2  from the wideband amplifier circuit in the standard receiver of  FIG. 1  as well as a receiver incorporating the wideband amplifier circuit shown in  FIG. 3 . 
           [0019]      FIG. 5  shows an operational flow diagram of a digital jammer detection circuit  350  in accordance with an exemplary embodiment. 
           [0020]      FIGS. 6A and 6B  show two different digital logic configurations for implementing a digital jammer detection circuit in accordance with an exemplary embodiment. 
           [0021]      FIG. 7  is a block diagram of a receiver path. 
       
    
    
       [0022]    To facilitate understanding, identical reference numerals have been used where possible to designate identical elements that are common to the figures, except that suffixes may be added, when appropriate, to differentiate such elements. The images in the drawings are simplified for illustrative purposes and are not necessarily depicted to scale. 
         [0023]    The appended drawings illustrate exemplary configurations of the disclosure and, as such, should not be considered as limiting the scope of the disclosure that may admit to other equally effective configurations. Correspondingly, it has been contemplated that features of some configurations may be beneficially incorporated in other configurations without further recitation. 
       DETAILED DESCRIPTION 
       [0024]    The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments. 
         [0025]    The detailed description set forth below in connection with the appended drawings is intended as a description of exemplary embodiments of the present invention and is not intended to represent the only embodiments in which the present invention can be practiced. The term “exemplary” used throughout this description means “serving as an example, instance, or illustration,” and should not necessarily be construed as preferred or advantageous over other exemplary embodiments. The detailed description includes specific details for the purpose of providing a thorough understanding of the exemplary embodiments of the invention. It will be apparent to those skilled in the art that the exemplary embodiments of the invention may be practiced without these specific details. In some instances, well known structures and devices are shown in block diagram form in order to avoid obscuring the novelty of the exemplary embodiments presented herein.  FIG. 1  is a block diagram of a standard receiver with a wideband jammer detector  100 . A radio frequency input signal RF IN is amplified by a first low noise amplifier (LNA)  101  to generate amplified signal RF 1 . Amplified signal RF  1  is coupled at an input to the wideband jammer detector  100  and also to an input of a second low noise amplifier  107 . A differential output signal RF 3  is generated by the second low noise amplifier  107  to in-phase and quadrature (I/Q) mixer  108 . 
         [0026]    Wideband jammer detector  100  comprises wideband amplifier circuit  102 , peak detection circuit  103 , averaging capacitor  104 , comparator circuit  105 , and digital jammer detection circuit  106 . Wideband amplifier circuit  102  is a low power, wide bandwidth amplifier. Wideband amplifier circuit receives and amplifies RF 1  from LNA  101  to generate amplified signal RF 2 . RF 2  is connected to an input of peak detection circuit  103 . Peak detection circuit  103  generates an output voltage level proportional to a peak voltage of amplified signal RF 2 . 
         [0027]    Capacitor  104  is coupled at one end to ground. The opposite end of capacitor  104  is coupled to the output of peak detection circuit  103  and to a sampling input Vin of comparator circuit  105 . Capacitor  104  serves to average the output of peak detection circuit  103 . Comparator circuit  105  also receives a reference input Vref. The output of comparator circuit  105  varies as a function of input signals Vin and Vref. When Vin is greater than or equal to Vref, the output PEAK_DET of comparator circuit  105  switches to a logic high state. Conversely, when Vin is less than Vref, the output PEAK_DET switches to a logic low state. Peak detection circuit  103 , capacitor  104  and comparator circuit  105  define a peak detector block  107 . 
         [0028]    PEAK_DET is coupled to the input of digital jammer detection circuit  106 . Digital jammer detection circuit  106  samples the value of PEAK_DET over a programmed duration. The programmed duration may be controlled and varied during device operation. When digital jammer detection circuit  106  counts a programmed threshold number of logic level high samples within the programmed duration, digital jammer detection circuit  106  generates an interrupt output jammer detector signal JDET. 
         [0029]      FIGS. 2A and 2B  are circuit level diagrams of a standard current mirror circuit  200 A and a high-speed current mirror resistive compensation circuit  200 B, respectively. 
         [0030]    A standard current mirror circuit  200 A as shown in  FIG. 2A  comprises a current source  201  and two transistors  202  and  203 . Transistors  202  and  203  are NMOS devices. 
         [0031]    Transistor  202  is configured as the reference transistor with the drain of transistor  202  coupled to the gates of both transistors  202  and  203 . A 3 db cutoff frequency for such standard current mirror configuration can be expressed as: 
         [0000]    
       
         
           
             
               
                 
                   
                     W 
                     o 
                   
                   = 
                   
                     
                       g 
                       m 
                     
                     
                       2 
                        
                       
                         C 
                         gs 
                       
                     
                   
                 
               
               
                 
                   Eq 
                   . 
                   
                       
                   
                    
                   
                     ( 
                     1 
                     ) 
                   
                 
               
             
           
         
       
     
         [0000]    where, g m  is the transconductance of transistor  202 , C gs  is the gate to source capacitance of transistor  202 , and ω o  is the 3 dB cutoff frequency in radians. 
         [0032]    By comparison, a high-speed current mirror resistive compensation circuit as shown in  FIG. 2B  comprises a current source  204 , resistor  205 , and two NMOS transistors  206  and  207 . A first terminal of resistor  205  is coupled to the gate of transistor  206 . A second terminal of resistor  205  is coupled to the gate of transistor  207  and the drain of transistor  206 . Transistor  206  is configured as the reference transistor with the drain of transistor  206  coupled to the gate of transistor  207  and to the second terminal of resistor  205 . A 3 dB cutoff frequency for such a high-speed current mirror resistive compensation configuration can be expressed as: 
         [0000]    
       
         
           
             
               
                 
                   
                     H 
                      
                     
                       ( 
                       s 
                       ) 
                     
                   
                   = 
                   
                     
                       
                         ω 
                         o 
                       
                       Z 
                     
                      
                     
                       [ 
                       
                         
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                           Z 
                         
                         
                           
                             s 
                             2 
                           
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                             2 
                              
                             
                               ζω 
                               o 
                             
                              
                             s 
                           
                           + 
                           
                             ω 
                             o 
                             2 
                           
                         
                       
                       ] 
                     
                   
                 
               
               
                 
                   Eq 
                   . 
                   
                       
                   
                    
                   
                     ( 
                     2 
                     ) 
                   
                 
               
             
             
               
                 
                   
                     ω 
                     o 
                   
                   = 
                   
                     
                       
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                            
                           
                               
                           
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                           1 
                         
                       
                       
                         
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                   Eq 
                   . 
                   
                       
                   
                    
                   
                     ( 
                     3 
                     ) 
                   
                 
               
             
             
               
                 
                   Z 
                   = 
                   
                     1 
                     
                       RC 
                       
                         gs 
                          
                         
                             
                         
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                         1 
                       
                     
                   
                 
               
               
                 
                   Eq 
                   . 
                   
                       
                   
                    
                   
                     ( 
                     4 
                     ) 
                   
                 
               
             
             
               
                 
                   ζ 
                   = 
                   
                     
                       
                         C 
                         
                           gs 
                            
                           
                               
                           
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                           1 
                         
                       
                       + 
                       
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                           gs 
                            
                           
                               
                           
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                       2 
                        
                       
                         
                           
                             g 
                             
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                                
                               1 
                             
                           
                            
                           
                             RC 
                             
                               gs 
                                
                               
                                   
                               
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                            
                           
                             C 
                             
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                                
                               2 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   Eq 
                   . 
                   
                       
                   
                    
                   
                     ( 
                     5 
                     ) 
                   
                 
               
             
           
         
       
     
         [0033]    when: 
         [0000]    
       
         
           
             
               
                 
                   R 
                   = 
                   
                     
                       1 
                       
                         g 
                         
                           m 
                            
                           
                               
                           
                            
                           1 
                         
                       
                     
                     ⇒ 
                     
                       
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                             1 
                           
                         
                       
                     
                     ⇒ 
                     
                       
                         f 
                         1 
                       
                        
                       
                         ( 
                         theoretical 
                         ) 
                       
                     
                   
                 
               
               
                 
                   Eq 
                   . 
                   
                       
                   
                    
                   
                     ( 
                     6 
                     ) 
                   
                 
               
             
           
         
       
     
         [0000]    where, g m1  is the transconductance of transistor  202 , C gs1  is the gate to source capacitance of transistor  202 , R is resistor  205 , and ω o  is the 3 dB cutoff frequency in radians. As can be seen, the addition of resistor  205  increases the theoretical 3 dB cutoff frequency by a factor of 2 when resistor  205  has a resistive value equal to the reciprocal of the transconductance of transistor  206 . This results in a significant increase in bandwidth. 
         [0034]      FIG. 3  is a schematic diagram of a wideband amplifier circuit  300 , a peak detector block  350 , and a digital jammer detection circuit  360  in accordance with an exemplary embodiment. Wideband amplifier circuit  300  comprises capacitor C 1 , resistor R 1 , PMOS input transistor  302 , first and second high-speed current mirror resistive compensation circuits  317 ,  318 , operational amplifier  315 , NMOS transistor  316 , and first and second output impedance boosting circuits  319 ,  320 . Peak detection block  350  may comprise peak detection circuit  103 , capacitor  104  and comparator circuit  105 , as in the standard receiver shown in  FIG. 1 . Similarly, digital jammer detection circuit may comprise a circuit as in the digital jammer detection circuit  106  in the standard receiver shown in  FIG. 1 . 
         [0035]    Alternatively, peak detection block  350  and digital jammer detection circuit  360  may correspond to new digital logic circuits described below in connection with  FIGS. 4 and 6 , respectively. 
         [0036]    Referring back to  FIG. 3 , high-speed current mirror resistive compensation circuit  317  includes resistor  305  and PMOS transistors  303  and  304 . High-speed current mirror resistive compensation circuit  318  includes resistor  314  and NMOS transistors  312  and  313 . 
         [0037]    A first terminal of capacitor C 1  is coupled to the signal input RF 1 . A second terminal of capacitor C 1  is coupled to the gate of transistor  302 . The series coupling of the input signal RF 1  through capacitor C 1  provides AC-coupling of the input signal RF 1 . The AC coupling capacitor C 1  isolates the DC level of the previous stage and allows NMOS transistor  302  to be biased at a desired value Vbias. A first terminal of resistor R 1  is coupled to a voltage source V bias . A second terminal of resistor  301  is coupled to the gate of transistor  302 . Varying V bias  controls the bias voltage applied to the gate of transistor  302 . When additional gain is desired Vbias is increased to create an increased voltage between the gate and the source, V GS , of transistor  302 . 
         [0038]    The relationship between V GS  and the transistor drain current can be expressed as: 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                     D 
                   
                   = 
                   
                     
                       
                         
                           μ 
                           n 
                         
                          
                         
                           C 
                           ox 
                         
                       
                       2 
                     
                      
                     
                       W 
                       L 
                     
                      
                     
                       
                         ( 
                         
                           
                             V 
                             gs 
                           
                           - 
                           
                             V 
                             th 
                           
                         
                         ) 
                       
                       2 
                     
                      
                     
                       ( 
                       
                         1 
                         + 
                         
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                            
                           
                               
                           
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                             V 
                             DS 
                           
                         
                       
                       ) 
                     
                   
                 
               
               
                 
                   Eq 
                   . 
                   
                       
                   
                    
                   
                     ( 
                     7 
                     ) 
                   
                 
               
             
           
         
       
     
         [0000]    where, μ n  is the charge-carrier effective mobility, W is the gate width, L is the gate length and C ox  is the gate oxide capacitance per unit area of transistor  302 . The relationship between drain current and transconductance can be expressed as: 
         [0000]    
       
         
           
             
               
                 
                   
                     g 
                     m 
                   
                   = 
                   
                     
                       
                         2 
                          
                         
                           I 
                           D 
                         
                       
                       
                         
                           V 
                           GS 
                         
                         - 
                         
                           V 
                           th 
                         
                       
                     
                     = 
                     
                       
                         2 
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                           I 
                           D 
                         
                       
                       
                         V 
                         ov 
                       
                     
                   
                 
               
               
                 
                   Eq 
                   . 
                   
                       
                   
                    
                   
                     ( 
                     8 
                     ) 
                   
                 
               
             
           
         
       
     
         [0039]    The source of transistor  302  is coupled to ground. The drain of transistor  302  is coupled to an active load including high-speed current mirror resistive compensation circuit  317  and output impedance boosting circuit  319 . As described above, high-speed current mirror resistive compensation circuit  317  provides additional bandwidth by introducing a zero. The output impedance boosting circuit  319  increases the output resistance of transistor  302 . The increase in output resistance increases the gain provided by transistor  302 . 
         [0040]    Output impedance boosting circuit  319  has two purposes. First, the output impedance boosting circuit diverts the DC current away from transistor  303 , thereby allowing transistor  303  to be a small low current device with high bandwidth. Transistors  304  and  303  have a device size ratio of 4:1. The DC current as well as the RF current is amplified going from transistors  303  to  304 . Second, output impedance boosting circuit  319  diverts the DC current away from the main path. However, output impedance boosting circuit  319  should not divert the RF signal from the main path. This is achieved by boosting the output impedance. The output impedance may be expressed as: 
         [0000]        R   OUT =(1 +g   m   R ) r   OUT   Eq. (9) 
         [0000]    where, R is resistor  307  and r OUT  is resistor  306 . 
         [0041]    The output of high-speed current mirror resistive compensation circuit  317  is coupled to high-speed current mirror resistive compensation circuit  318  and output impedance boosting circuit  320 . Similar to output impedance boosting circuit  319 , output impedance boosting circuit  320  has the same two purposes. The output impedance may be expressed as: 
         [0000]        R   OUT   =A (1 +g   m   r   OUT ) r   OUT   Eq. (10) 
         [0000]    where, A is amplifier  310  and r OUT  is resistor  311 . 
         [0042]    The output impedance boosting is achieved with a different technique. The output of high-speed current mirror resistive compensation circuit  318  is coupled to the drain of transistor  316  and the negative input of operational amplifier  315 . The positive input of operational amplifier  315  is coupled to a voltage source set to VDD/2. The operational amplifier  315  configuration drives the DC output of the wideband amplifier to VDD/2 by way of the virtual short effect between the inputs of an operational amplifier (OP AMP)  315 . OP AMP  315  controls the gate voltage of transistor  316  to create a current source to feed transistor  313 . OP AMP  315  ensures that the node RF 2  is biased at VDD/2. This is achieved by driving the gate of the transistor M 6  to whatever voltage in order that RF 2  is set at VDD/2. RF 2  feeds peak detector block  350 . 
         [0043]    The gain from RF input at transistor  302  to output node RF 2  can be expressed as: 
         [0000]    
       
         
           
             
               
                 
                   
                     Gain 
                     DC 
                   
                   = 
                   
                     
                       g 
                       m 
                     
                      
                     M 
                      
                     
                         
                     
                      
                     1 
                      
                     
                       ( 
                       
                         
                           W 
                            
                           
                               
                           
                            
                           4 
                           × 
                           W 
                            
                           
                               
                           
                            
                           5 
                         
                         
                           W 
                            
                           
                               
                           
                            
                           2 
                           × 
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                            
                           
                               
                           
                            
                           3 
                         
                       
                       ) 
                     
                      
                     
                       R 
                       OUT 
                     
                   
                 
               
               
                 
                   Eq 
                   . 
                   
                       
                   
                    
                   
                     ( 
                     11 
                     ) 
                   
                 
               
             
           
         
       
     
         [0044]    In general and as used herein, a gain may be (i) equal to one in linear unit, which is zero dB in logarithm unit, (ii) greater than one in linear unit, or (iii) less than one in linear unit. A gain of greater than one in linear unit corresponds to signal amplification and a positive gain (in dB). A gain of less than one in linear unit corresponds to signal attenuation and a negative gain (in dB). Attenuation is negative gain, so that an attenuation of x dB is equivalent to a gain of −x dB. 
         [0045]      FIG. 4  shows a schematic diagram of a peak detector block  350  in accordance with a further exemplary embodiment which can be used to peak detect the output RF 2  from wideband amplifier circuit  102  in the standard receiver of  FIG. 1  as well as a receiver incorporating the wideband amplifier circuit  300  shown in  FIG. 3 . 
         [0046]    Peak detector block  350  includes a peak detection circuit  103 ′, a capacitor coupling circuit  104 ′ and a comparator circuit  105 ′. Peak detection circuit  103 ′ includes an upper negative-peak detector portion and a lower positive-peak detector portion. The RF 2  amplified output from a preceding stage is coupled to respective peak detector input transistors  400  and  401  in each of upper negative-peak and lower positive-peak detector portions. Transistor  400  is a PMOS transistor. The source of transistor  400  is coupled to VDD. PMOS transistor  400  is biased in weak inversion region to allow it to follow the negative peak of an amplified jammer signal. The drain of transistor  400  is coupled to current source  406 . PMOS transistor  400  is configured in a common source configuration to allow detection of negative peak signals. A first terminal of capacitor  402  is coupled to the drain of transistor  400  and the negative sampling input V neg  of comparator  405 . A second terminal of capacitor  402  is coupled to ground. Capacitor  402  averages the output of transistor  400  to create signal V neg . The negative threshold input V neg     —     ref  is set to a selected threshold voltage level. In some designs the selected threshold voltage level V pos     —     ref  may be programmable. 
         [0047]    Transistor  401  is a NMOS transistor biased to operate in the weak inversion region so the transistor will follow the positive peak of the amplified jammer signal. The source of transistor  401  is coupled to ground. The drain of transistor  401  is coupled to current source  407 . Thus, NMOS transistor  401  is configured in a common source configuration to allow detection of positive peak signals. A first terminal of capacitor  403  is coupled to the drain of transistor  401  and the positive sampling input of comparator  405 . A second terminal of capacitor  403  is coupled to ground. Capacitor  403  averages the output of transistor  401  to create signal V pos . The positive threshold input value V pos     —     ref  is set to a selected threshold voltage level. In some designs, the selected threshold voltage level V pos     —     ref  may be programmable. 
         [0048]    Transistors  400  and  401  are biased to operate in weak inversion mode, otherwise known as “Cut-off” or “Sub-threshold” mode. Weak inversion occurs when the gate to source voltage is less than the threshold voltage of the transistor. Ideally, current should not flow through a transistor in weak inversion mode. However, due to the Boltzman distribution of electron energies some more energetic electrons at the source can enter the channel and flow to the drain of the transistor. This results in a sub-threshold current that is exponentially related to the gate to source voltage applied to the transistor. Operation in weak inversion mode allows transistors  400  and  401  to create an output current large enough to properly drive comparator  405 . The relationship between gate to source voltage and sub threshold current may be expressed as: 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                     D 
                   
                   = 
                   
                     
                       I 
                       DO 
                     
                      
                     
                        
                       
                         
                           
                             V 
                             GS 
                           
                           - 
                           
                             V 
                             th 
                           
                         
                         
                           nV 
                           T 
                         
                       
                     
                   
                 
               
               
                 
                   Eq 
                   . 
                   
                       
                   
                    
                   
                     ( 
                     12 
                     ) 
                   
                 
               
             
           
         
       
     
         [0000]    where, I D0 =current at V GS =V th  and the slope factor n is given by 
         [0000]        n= 1 +C   D   /C   OX   Eq. (13) 
         [0000]    where, C D =capacitance of the depletion layer and C OX =capacitance of the oxide layer. 
         [0049]    Comparator  405  compares the amplitude of input signal V neg  with the amplitude of threshold signal V neg     —     ref . Comparator  405  also compares the amplitude of input signal V pos  with the amplitude of threshold signal V pos     —     ref . When either input signal has larger amplitude than the amplitude of the corresponding threshold signal, the comparator  405  output signal PEAK_DET is set to a logic high state. When both input signals have lower amplitude than the amplitude of the corresponding threshold signal the comparator  405  output signal PEAK_DET is set to a logic low state. 
         [0050]    As described in  FIG. 1 , a conventional digital jammer detection circuit  106  samples the output of comparator  105  over a programmed duration. The programmed duration may be controlled and varied during device operation. When the digital jammer detection circuit  106  counts more than a programmed threshold number of logic level high samples within the programmed duration, digital detection circuit  106  generates an interrupt output signal JDET. 
         [0051]      FIG. 5  shows an operational flow diagram of a digital jammer detection circuit  350  in accordance with an exemplary embodiment. 
         [0052]    In step  500 , the comparator circuit  150  and all counters are initialized. Step  500  may be initiated by different events, such as: powering on the device, jammer detection circuit timeout, single wire bus interface (SBI) override, global reset, or gain mode transition. In step  500 , a digital jammer detection circuit clock is reset. Once the digital jammer detection circuit clock is reset in step  500 , two independent processes begin to operate in parallel. The first independent process includes steps  503 ,  504 , and  505 . The second independent process includes steps  506 ,  507 ,  508  and  509 . 
         [0053]    The first independent process includes steps  503 ,  504 , and  505 . In step  503 , the digital jammer detection circuit timeout period is provided. In step  504 , the digital jammer detection circuit determines whether the jammer detection circuit timeout period provided in step  503  has elapsed. If the digital jammer detection circuit timeout period has not elapsed step  504  is repeated. In step  505 , a reset request is sent if the jammer timeout period has elapsed. 
         [0054]    The second independent process includes steps  506 ,  507 ,  508  and  509 . In step  506  the digital jammer detection circuit samples the output of comparator  105  and determines if the sampled output is a logic high signal. If the sampled output is not a logic high signal the counting is stopped and current count value is maintained. In step  507 , the slave counter determines the average time the jammer was present. In step  508 , the digital jammer detection circuit determines if the peak counter value is greater than the programmed peak threshold value. In step  509 , a jammer interrupt signal is sent and a reset request generated sending the process back to step  501 . 
         [0055]    The digital jammer detection circuit determines if an external reset request has been made. An external interrupt may be initiated by different events, such as: single wire bus interface (SBI) overwrite, global device reset, or gain mode transition. 
         [0056]      FIGS. 6A and 6B  show two different digital logic configurations for implementing digital jammer detection circuit  360  in accordance with an exemplary embodiment. Block  600  is the initialization logic, which generates a digital jammer detection circuit reset signal when any of the following inputs are triggered: global reset, gain mode transition, SBI override, or digital jammer detection circuit timeout. 
         [0057]    In  FIG. 6A , block  601  is an SR latch circuit. An SR latch circuit is an arrangement of logic gates that maintains a stable output after the inputs have been turned off. A SR latch circuit has a set input (S) and a reset input (R). When the set input is logic high state the output is set to a logic high state. When the reset input is a logic high state the output is set to a logic low state. The output of block  601  is coupled to the input of block  602 . 
         [0058]    Block  602  is a relaxation oscillation circuit. A relaxation oscillation circuit is an oscillator circuit that utilizes a capacitor, which is charged gradually and then discharged rapidly. A relation circuit may be implemented with a resistor or current source, a capacitor, and a threshold device such as an injunction transistor or Gunn diode. When the output of block  601  is ON the relaxation oscillator  602  creates an output signal, which oscillates at a predetermined frequency. 
         [0059]    The oscillating output signal is the digital jammer detection circuit clock. The relaxation oscillator output is coupled to the input of the 8-bit counter  603 . The 8-bit counter  603  counts the oscillations sampled. 8-bit counter  603  outputs the number of oscillations, which have been observed. A first input to XOR circuit  604  is coupled to the output of the 8-bit counter  603 . A second input of XOR circuit  604  is coupled to a SBI compare signal. XOR circuit  604  determines a threshold compare value from the SBI compare signal. XOR circuit  604  compares the number provided by the 8-bit counter  603  with the SBI compare value. If the number provided by the 8-bit counter  603  is greater than the SBI compare value the XOR circuit  604  generates a jammer detected interrupt signal. 
         [0060]    In  FIG. 6B , block  605  is a transition detect logic. Transition detect logic  605  detects any change or transition of the logic level of the input signals and generates a constantly high logic level on its corresponding output. The Q output of transition detect logic  605  is coupled to the S input of SR latch  606 . The Q′ output (inverse of Q output) of transition detect logic  605  is coupled to the R input of SR latch  606 . The transition detector purpose is to detect the comparator output going high when a jammer signal is first present after the circuit is initialized. This starts the “scanning” mode when the circuit starts scanning for jammer signals. The transition detector triggers the timeout counter, which determines the time for which the circuit needs to scan for a jammer signal. If the jammer count reaches the desired threshold (determined by slave counter) before the timeout counter triggers then the JDET signal goes HIGH indicating jammer signal detection. 
         [0061]    Block  606  is an SR latch circuit. An SR latch circuit is an arrangement of logic gates that maintains a stable output after the inputs have been turned off. An SR latch circuit has a set input (S) and a reset input (R). When the set input is logic high state the output is set to a logic high state. When the reset input is a logic high state the output is set to a logic low state. The output of block  606  is coupled to the input of block  607 . 
         [0062]    Block  607  is a relaxation oscillator. A relaxation oscillator is an oscillator circuit that utilizes a capacitor, which is charged gradually and then discharged rapidly. A relaxation oscillator may be implemented with a resistor or current source, a capacitor, and a threshold device such as a uni-junction transistor or Gunn diode. When the output of block  606  is a logic high signal the relaxation oscillator  607  creates an output signal which oscillates at a predetermined frequency. The oscillating output signal is the digital jammer detection circuit clock. The relaxation oscillator output is coupled to the input of the 8-bit counter  608 . The 8-bit counter  608  counts the oscillations sampled. 8-bit counter  608  outputs the number of oscillations, which have been observed. 
         [0063]    A first input to XOR circuit  609  is coupled to the output of 8-bit counter circuit  608 . A second input of XOR circuit  609  is coupled to a SBI compare signal. XOR circuit  609  determines a threshold compare value from the SBI compare signal. XOR circuit  609  compares the number provided by the 8-bit counter  608  with the SBI compare value. If the number provided by the 8-bit counter  608  is greater than the SBI compare value the XOR circuit  609  generates a jammer detected interrupt signal. The output of XOR circuit  609  is coupled to the input of pulse stretcher circuit  610 . Pulse stretcher  610  generates a extended reset signal, which is meant to reset the internal states/counters when a jammer timeout occurs 
         [0064]      FIG. 7  shows a block diagram of a receiver path. The differential output terminals of LNA  701  are coupled to I/Q mixer  702 . The input signal coupled to the input of LNA  701  contains the desired RF signal, local oscillator (LO) signals, close in jammer signals and far out jammer signals. In accordance with the exemplary embodiments described herein, wideband jammer detector  100  detects the presence of LO signals, close in jammer signals and far out jammer signals. 
         [0065]    Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. 
         [0066]    Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the exemplary embodiments of the invention. 
         [0067]    The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. 
         [0068]    The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal. 
         [0069]    In one or more exemplary embodiments, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. 
         [0070]    The previous description of the disclosed exemplary embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these exemplary embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.