Abstract:
Complex floating point instructions are executed under millicode control when it is not cost effective to implement its function in hardware. One of the disadvantages to executing complex instructions using millicode routines is that determining and accessing the instructions operands are costly for millicode performance. To determine what the source and target location are, the instruction text is parsed. Furthermore the millicode instruction stream must be modified to access the operand data from and write the result to the program registers specified by the complex floating point instruction. The invention overcomes these disadvantages by providing millicode with register indirect access to the program floating point registers.

Description:
TRADEMARKS 
       [0001]    IBM® is a registered trademark of International Business Machines Corporation, Armonk, N.Y., U.S.A. Other names used herein may be registered trademarks, trademarks or product names of International Business Machines Corporation or other companies. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    This invention relates to the millicode execution of complex floating point operations in a computer system conforming to the IBM z/Architecture Principles of Operations, and particularly to passing operand data from program floating point registers to millicode working registers, and passing results from the millicode working registers back to program floating point registers using register indirect accesses. 
         [0004]    2. Description of Background 
         [0005]    Complex instructions are executed under millicode control when it is not cost effective to implement its function in hardware alone. The function of the complex instruction is programmed in a routine that uses sequences of simpler hardware instructions. 
         [0006]    One of the disadvantages to executing complex instructions using millicode routines is determining what the source and destination operands are for the operation. It is not known what program registers an instruction will use for any particular user program, so it is not possible to write millicode routines that move operand data directly between the program floating point registers and the millicode routine working registers. Instead, when control passes from a program to a millicode routine for the purposes of executing a complex instruction, the original instruction text is parsed to determine what program registers are the source for the instruction. Next an instruction is created that will copy the data to the millicode working registers. This process of copying program register data can be very costly for performance because it requires modifying the instruction stream. Likewise, writing the result from a millicode working register back to the program floating point register (FPR) requires the same process of parsing the instruction text, creating an instruction and forcing that instruction into the instruction stream where it is executed. 
       SUMMARY OF THE INVENTION 
       [0007]    The shortcomings of the prior art are overcome and additional advantages are provided through the provision of register indirect access of the program register set. Millicode Set and Extract Program FPR Indirect instructions (herein EXFDI instructions) allow indirect register access to Program Floating Point registers by a Millicode routine. Rather then using the instruction text of the instruction to determine what the source registers are, upon Millicode entry (or Millicode startup) the register addresses for the source and target operands are written to specific hardware registers called the Register Indirect tags (RI tags). The Extract Program FPR indirect instruction can move the contents of the program&#39;s FPR address to a specified millicode working register by referencing the RI tag that contains the address of the program FPR used for the source of the operation. Similarly, another millicode instruction, the Set Program floating point register indirect instruction (herein a SDFI instruction) can write data directly to a program FPR by referencing the RI tag that contains the destination address for the operation. 
         [0008]    Greater flexibility is available to these operations by allowing an optional offset to the program register referenced from the RI Tags. Specifically, in the z/Architecture, the 64-bit floating point registers may be paired to create a 128-bit register for extended operations, where the paired registers are always offset from each other by 2. Therefore one RI tag can be used to reference both the low register of a 128-bit floating point register pair and can optionally be incremented by 2 to reference the high register of the pair. 
         [0009]    System and computer program products corresponding to the above-summarized methods are also described and claimed herein. 
         [0010]    Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with advantages and features, refer to the description and to the drawings. 
       TECHNICAL EFFECTS 
       [0011]    As a result of the summarized invention, technically we have achieved a solution that will execute a Millicode instruction many cycles faster then would be possible without register indirect access to the program registers. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which: 
           [0013]      FIG. 1  illustrates one example of the process for extracting the source operand data from a program FPR to a millicode working register (MGR) through register indirect access. 
           [0014]      FIG. 2  illustrates one example of the process for setting the data for a program FPR from an MGR through register indirect access. 
       
    
    
       [0015]    The detailed description explains the preferred embodiments of the invention, together with advantages and features, by way of example with reference to the drawings. 
       DETAILED DESCRIPTION OF THE INVENTION 
       [0016]    Turning now to the drawings in greater detail,  FIG. 1  illustrates a preferred embodiment of a process for accessing a Program&#39;s floating point register (FPR) and writing it to a millicode working register (MGR) through register indirect access. In accordance with our process a millicode instruction that performs a register indirect access operation is called Extract Floating Point Register Indirect (EXFDI). As illustrated in  FIG. 1  there is a Program Code ( 100 ) for executing a computation that contains a complex floating point instruction which is programmed with a routine that uses sequences of simpler hardware millicode instructions. This complex Floating Point instruction is referred to as a Millicoded Program Instruction ( 101 ). That Millicoded Program Instruction ( 101 ) passes the instruction text from the Program Code to Millicode Entry ( 10 ) element and to an Instruction Decode multiplexor ( 130 ). The Millicode Entry ( 110 ) sends control information such as the starting address and Instruction Text to a Millicode Routine ( 120 ) which is to perform desired operations for completing the task needed by the Millicoded Program Instruction ( 101 ). That Millicode Routine will contain one or more EXFDI instructions ( 121 ). In addition to sending control information to the Millicode Routine ( 120 ), the Millicode Entry ( 10 ) also sets Register Indirect Tags (R 10 , R 11 , R 12 , R 13 ) in an Indirect Register Control Unit ( 150 ) with the addresses of the operands used by the Millicoded Program Instruction ( 101 ). Up to 3 source program Floating Point Register (FPR) addresses for the operand fields may be stored in Register Indirect Tags referred to as R 11 , R 12  and R 13  contained in  150 . One register indirect tag referred to as RIO is setup during millicode entry with an address of a destination Program Floating Point Register (FPR). In the preferred embodiment these Register Indirect Tags are stored in a special millicode control register of the Indirect Register Control Unit ( 150 ). The Millicode Routine ( 120 ) contains one or more EXFDI instructions ( 121 ) and for any of these which arise in the Millicode routine ( 120 ), as well as instructions from the Program Code ( 100 ), are decoded by Instruction Decode ( 140 ). Both send instruction text to a Instruction Decode multiplexor ( 130 ) which selects the appropriate instruction text for Instruction Decode ( 140 ). During execution of the Millicode Routine ( 120 ) the Millicode Instructions such as EXFDI (which are used to set up the data for execution of the Microcode Routine ( 120 ) calculation and SFDI (which is used to provide the result of the execution of any calculation) are selected by decode multiplexor  130  for execution. This process allows for indirect register access and is the focus of this preferred embodiment. The path for program code ( 100 ) then follows and is included for completion of the desired tasks. For an EXFDI instruction ( 121 ), the decode multiplexor  130  causes the instruction decode ( 140 ) to determine which RI tag is specified by the instruction text and selects that tag with a multiplexor ( 151 ) of the Indirect Register Control Unit ( 150 ). The RI Tag specifies a source FPR address and that FPR address is sent to an FPR address multiplexor ( 160 ). For EXFDI and SFDI instructions either the RI tag or the RI tag incremented by two is selected as the address for the FPR ( 170 ). A field in these instructions determines which value (the incremented RI tag or the unincremented RI tag) is selected. Conditionally modifying the RI tag by two for an EXFDI instruction allows a single RI tag to be used to reference either the low order half or the high order half of a floating point register pair for the purposes of quad precision floating point operations used in Extended Floating Point operations within the z/Architecture. A direct path from Instruction decode to FPR address multiplexor  160  is shown for completeness and this direct path is selected when instructions (as from the Millicode Routine or Program Code) other then EXFDI and SFDI are executed. The FPR address multiplexor ( 160 ) sends the selected address for the EXFDI instruction to the FPR array ( 170 ). The data from the selected FPR address of the FPR array ( 170 ) is sent to the target Millicode General Register MGR ( 180 ). The address of the MGR to be written to with the FPR array ( 170 ) data is determined by Instruction decode ( 140 ). For a single floating point calculation the Program Code ( 100 ) will usually have two of these EXFDI operations to set up a floating point calculation when a complex floating point instruction cannot be executed directly by hardware. 
         [0017]    The results of the calculation of the Millicode Routine ( 120 ) of  FIG. 1  will need to be returned.  FIG. 2  illustrates one example of a process of that return by setting a Program FPR with the contents of a specified millicode working register through register indirect access, During the millicode entry ( 110 ) described above, the RI tag ( 150 ) specified as RIO, which is the register indirect setup tag used during millicode entry with an address of a destination Program Floating Point Register (FPR), is set with the address of the program FPR that is the destination address of the Millicoded Program Instruction ( 101 ) at the point in the Program Code when a result is to be reported. Control is then passed at that point in the Program Code to the Millicode Routine ( 120 ) as has been discussed above. Before the Millicode Routine completes, the results (that are in a millicode working register MGR  180 ) are written to the destination Program FPR ( 170 ) using register indirect access. This is achieved by one or more SFDI instructions ( 122 ) contained in the Millicode Routine ( 120 ). The SFDI instruction text is selected by the Instruction Decode multiplexor  130  and is sent to Instruction decode ( 140 ). Instruction decode ( 140 ) sends the register indirect tag (typically RIO) that contains the address of the Program FPR ( 170 ). Instruction decode ( 140 ) also sends the address of the source MGR ( 180 ) specified by the SDFI instruction ( 214 ). Similar to the EXFDI instruction ( 121 ), the SFDI instruction ( 214 ) may specify that the address contained in the RI tag is to be incremented by two for determining the address of the program FPR( 250 ). This is used for returning the second 64-bits of a 128-bit FPR pair for extended floating point operations. 
         [0018]    The capabilities of the present invention can be implemented in software, firmware, hardware or some combination thereof. 
         [0019]    As one example, one or more aspects of the present invention can be included in an article of manufacture (e.g., one or more computer program products) having, for instance, computer usable media. The media has embodied therein, for instance, computer readable program code means for providing and facilitating the capabilities of the present invention. The article of manufacture can be included as a part of a computer system or sold separately. 
         [0020]    Additionally, at least one program storage device readable by a machine, tangibly embodying at least one program of instructions executable by the machine to perform the capabilities of the present invention can be provided. 
         [0021]    The flow diagrams depicted herein are just examples. There may be many variations to these diagrams or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order, or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention. 
         [0022]    While the preferred embodiment to the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.