Abstract:
An array of unit oscillators interconnected with one another in that the transistors of the oscillators are connected to common lines. Separate lines in proximity provide coupling capacitance for feedback to sustain the oscillation of the unit oscillators. The separate lines also form a grid which results in an antenna for emanation of the oscillators, radiation The array can effectively function at extremely high frequencies (i.e., greater than 30 GHz). The array is specially designed to accommodate monolithic implementation.

Description:
FIELD OF THE INVENTION 
     The invention pertains to microwave power combiners using two-dimensional arrays of solid state devices. The invention more particularly pertains to solid-state power combining arrays utilizing oscillator feedback. 
     BACKGROUND OF THE INVENTION 
     Related art pertaining to a power combining oscillator array at lower frequencies has involved individual gate, source and drain grid lines to separate the direct current (DC) bias feeds for the field effect transistors (FETs) in the oscillator array. In the array, a high power output is provided by coupling together and synchronizing all of the individual oscillators in the array. The coupling for providing the feedback needed for sustaining oscillation is constituted of and controlled by the width of the lines and the spacing between each pair of lines in the grid of the array. The grid spacing is determined and, in turn, restricted by antenna requirements of the array. Problems that arise with such an array at higher frequencies (i.e., &gt;30 GHz) include decreased FET gains which provide insufficient feedback to sustain oscillation. 
     SUMMARY OF THE INVENTION 
     The present invention obviates the aforementioned problems of the related art with features of a structure that improve the coupling for providing feedback in that an increase of coupling is attained and control of coupling is effected independently of the grid spacing and the antenna requirements. To achieve these features, each oscillator has the gate line situated over the drain bias line with a dielectric between the lines to form a coupling capacitor which provides the desired feedback. However, the positions of the gate and drain lines may be reversed depending on design preferences Also, the invention has a feature which permits forming an oscillator having more than one FET. .A plurality of FETs is a basis for increasing oscillator loop gain. The invention may also incorporate other kinds of three terminal devices such as heterojunction bipolar transistors. 
     Monolithic fabrication techniques provide a practical method for implementation of the present invention. Other fabrication techniques may also be used. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1a and 1b are schematics of a unit cell oscillator. 
     FIGS. 2a and 2b are schematics of the powercombining array. 
     FIG. 3 shows the power-combining array placed in a Fabry-Perot resonator. 
     FIGS. 4a and 4b are integrated circuit layouts of the unit cell oscillator. 
     FIG. 5a and 5b reveal the capacitor construction. 
     FIG. 6 is a schematic of the equivalent circuit of the unit cell oscillator. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     An instance of the invention is an improved oscillator 10 as shown in FIGS. 1a and 1b which is used in a power combining array 20 of FIGS. 2a and 2b. Array 20 is placed in a Fabry-Perot resonator 30 as shown in FIG. 3. Resonator 30 has a metal mirror 12 in back of array 20 and a semi-transparent mirror 14 in front of array 20. Emission 118 from the resonator is out through mirror 14. The large surfaces of mirrors 12 and 14 are parallel to that of grid 20. The distances 114 and 114 between mirrors 12 and 14 and grid 20 are set in accordance with the resonant frequency of the Fabry-Perot resonator. The gain of oscillator 10 may be sufficient so as to eliminate the need for mirror 14. 
     Transistor 16 of FIG. 1a has a drain connected to drain line 26 and a source is connected to source line 28. The gate of field effect transistor 16 is connected to gate line 32. The gate of transistor 18 is connected to gate line 34 and the drain is connected to drain line 36. The source of transistor 18 is connected to line 28. Capacitor 22 provides a coupling between gate line 34 and drain line 26. In addition, there is coupling between lines 26 and 34 which is effected by the proximity of lines 26 and 34. Likewise, capacitor 24 provides coupling between gate line 32 and drain line 36. Additional coupling is effected by the proximity of the lines in the actual construction of oscillator array 20. The signals on the drain lines from transistor 16 is sent to gate line 34 which passes the signal onto transistor 18 which provides an amplified signal to drain line 36 which in turn is capacitively coupled by capacitance 24 to base line 32 which is fed to transistor 16 and in turn provides a signal onto drain line 26, and so on. FIG. 1b shows the same configuration using bipolar transistors 17 and 19. Even though the transistors 17 and 19 of FIGS. 1b, 2b and 4b are NPN, transistors 17 and 19 may also be PNP. 
     FIGS. 4a and 4b illustrate an integrated circuit unit section 40 of oscillator grid array 20. Unit cell 40 is defined by assuming an infinite grid. The symmetry of grid 20 imposes boundary conditions which define unit cell 40. Boundary conditions are an electric wall (the tangential electric field is zero) as indicated by dotted lines 42 and 44 on the top and bottom and a magnetic wall (tangential magnetic field is zero) is indicated by the dashed lines 46 and 48 on the sides. This reduces the analysis of grid 20 to that of an analysis of a waveguide. The dimensions required for grid construction are unit cell 40 dimensions 52, 54 and 56 and the width of the conducting lines of array 20 which are shown as dimensions 58, 60 and 62, and the spacing between lines 68 and 70 which is dimension 64. Dimensions 52, 54 and 56 are chosen appropriately for the intended operating frequency of the cell. Typically, dimension 52 is chosen to be from 1/8 to 1/10 of the free space wavelength of the operating frequency. For operation at 35 GHz, dimension 52 would be about one millimeter. Dimensions 54 and 56 are about 1/2 of the magnitude of dimension 52. The width 58 of array lines 26, 28 and 36 would be about 25 to 50 microns for 35 GHz. Dimensions 60, 62 and 64 are chosen to effect feedback between FETs 16 and 18 in FIG. 4a which form oscillator 10 in unit cell 40. Exact dimensions would require circuit simulation of oscillator 10 and selection of specific FETs 16 and 18, for a particular operating frequency Typical dimensions 60, 62 and 64 are 20 microns, 20 microns and 6 microns, respectively. Overall feedback of oscillator 4 is determined by dimensions 58 and 66, the value of capacitors 22 and 24, and inherent coupling between grid lines 32 and 36. A contribution of coupled lines 32 and 36 or capacitor 22 or 24 to the feedback can be adjusted by varying dimensions 58, 60, 62 and 64 to provide a large, moderate or insignificant portion of oscillator coupling. For instance, capacitor 22 or 24 can be made large so that it is a short at the frequency of oscillation or spacing 64 can be made large so there is a little coupling between lines 68 and 70. Similar dimensions would apply to integrated circuit unit section 40 in FIG. 4b incorporating bipolar transistors 17 and 19. 
     Oscillator grid array 20 is formed on substrate 112. Substrate 112 is typically gallium arsenide (GaAs) for the embodiment incorporating FETs 16 and 18 or bipolar transistors 17 and 19. First terminal lines 26 and 36, connected via lines 82 and 70, respectively, to the drains of FETs 16 and 18 or to the collectors of transistors 17 and 19, are deposited and of gold. Third terminal lines 28, connected to the sources of FETs 16 and 18 or to the emitters of transistors 17 and 19, are deposited and of gold. Second terminal lines 32 and 34 are connected via lines 68 and 88, respectively, to the gates of FETs 16 and 18 or to the bases of transistors 17 and 19, and are deposited and of gold. The proximity of lines 34 and 32 to lines 26 and 36, plus the capacitances resulting from the discrete capacitors indicated by 22 and 24, produce feedback for the purpose of sustaining the oscillation of unit oscillators 40. Lines 32 and 34 are bridged over lines 58 so as to avoid electrical contact with lines 58. Lines 26, 82, 58, 36 and 70 form a grid for emanating radiation 118 from unit oscillators 40 of array 20. Proximate to at distance 114 (in FIG. 3) from and parallel to substrate 112 is mirror 12 that reflects radiation 118 from array 20. Semi-reflecting mirror 14 reflects a portion of radiation 118 back towards array 20. Also, mirror 14 passes radiation out of device 30. The distances 114 and 116 are adjusted for the desired amount of emanated radiation and frequency of device 30. 
     All drain lines 26 and 36 are tied together to a common connection which is connected to a positive 5 to 6 volt direct current (DC) source through radio frequency (RF) chokes 120 and 126. All gate lines are likewise connected to a common connection which is connected to an approximately negative 2 volt bias through RF chokes 122 and 128. All source lines are connected to a common connection which is connected to a common ground reference through RF choke 124. Each set of lines on an integrated circuit are tied together at the edge of the array or chip. 
     FIG. 5a illustrates a layout of capacitors 22 and 24 which have electrodes that are part of lines 26 and 34 and lines 36 and 32, respectively. FIG. 5b shows a side view of capacitors 22 and 24 and the position of lines 32, 34 and lines 26, 36 relative to each other. Capacitors 22 and 24 have a dielectric 72 between portions of lines or electrodes 26 and 34 and lines or electrodes 36 and 32, respectively, as illustrated in FIG. 5b. Dielectric 72 may be silicon nitride. 
     FIG. 6 is a schematic of an equivalent circuit 50 of unit cell 40 in FIG. 4a. A schematic of the equivalent circuit of unit cell 40 in FIG. 4 would be similar. Center-tapped transformer 74 represents the coupling of oscillator 10 to free space through grid 20. Center tap 76 is the source bar 28 in grid 40. Inductances 78 and 80 are drain lead 70 and 82 inductances. Inductances 84 and 86 are gate lead 68 and 88 inductances. Inductance 90 and capacitance 94 represent the waveguide nature of unit cell 40. Capacitances 96 and 98 represent capacitors 22 and 24 having silicon nitride dielectric between portions of gate 32, 34 lines and drain 26, 36 lines of FETs 16 and 18, overlaying each other in unit cell 40. Coupled line pairs 100 and 102 represent the pairs of lines 82 and 88, and 68 and 70 in FIG. 4a. These lines are characterized by the line widths and spacing between lines given by dimensions 60, 62 and 64 in FIG. 4a. The coupled line pairs are modelled using these dimensions in commercially available circuit simulation software. Calculation of the lead inductance 90 and capacitance 94 may be determined with the following formulas. The equivalent circuit element values for inductor 90 and capacitor 94 due to the grid elements in the array can be calculated from formulas given by Popovic et. al. as follows below: ##EQU1## and Z mn  TM are the impedances of the mn-th TE and TM modes. The dimension a is the width of the unit cell designated as 52 in FIG. 4a. The dimension W is the width of lines 58 in FIG. 4a. Note that inductances 78, 84, 86 and 80 come from leads or bonding wires used to attach the FETs into the array. 
     With specific values known for equivalent circuit 50 elements and specific FETs (note that FETs 16 and 18 need not be identical), the coupling through capacitors 22 and 24, and coupled lines 68, 70, 32 and 36 are adjusted so that the impedance looking into the oscillator port at leads 104 and 106, where a 377 ohm load 108 is connected, is -377 ohms so that oscillation can occur. Load 110 (jB) is due to Fabry-Perot resonator mirror 12. The impedance presented by mirror 12 is determined by the spacing between mirror 12 and grid 20 and the dielectric constant of materials 112 between mirror 12 and grid 20. 
     Unit cell 40 of grid 20 may be fabricated on substrate material such as alumina or DUROID, using hybrid construction with discrete GaAs FETs 16 and 18, and capacitors 22 and 24 mounted on substrate 112. Metal grid lines 26, 28, 32, 34 and 36 may be made of copper or gold plated copper. Another approach is to use high resistivity silicon as a substrate 112 material having grid lines 26, 28, 32, 34 and 36, capacitors 22 and 24, and interconnects formed with silicon integrated fabrication processes. The active devices (typically GaAs FETs 16 and 18) can be mounted in etched wells in the silicon substrate 112 with wires connecting FETs 16 and 18 to grid and bias lines 26, 28, 32, 34 and 36. This approach is suitable for millimeter wave frequencies and offers a lower thermal resistance than GaAs. 
     Preferred construction is a monolithic implementation with GaAs or InP as a substrate 112 material. FETs 16 and 18 used for active array 20 elements 40 are fabricated on GaAs or InP substrate 112. Grid lines 26, 28, 32, 34 and 36 and FET 16 and 18 interconnections 68, 70, 82 and 88 are formed with gold lines deposited by thermal evaporation or by gold plating. Standard monolithic microwave integrated circuit (MMIC) capacitors having silicon nitride dielectric 72 are used for coupling capacitors 22 and 24. Conventional MMIC fabrication techniques can be used for all grid fabrication steps. The monolithic approach minimizes the size of parasitic elements in array 20. For example, since short metal lines on substrate 112 are used for FET 16 and 18 connections 68, 70, 82 and 88 instead of bond wires, wiring inductance is minimized. Further it may be desirable to use thick plated gold for drain connections 70 and 82 to heatsink FETs 16 and 18. Because of the FET layout in connections, there are currents flowing in opposite directions thereby cancelling out each other&#39;s effects. 
     Backside mirror 12 or ground plane can be a separate metal plate or a ground plane on the back of substrate material 112 used for oscillator grid 20. Partially transparent mirror 14 can be a dielectric material such as quartz or sapphire. If the array gain is high enough, no dielectric material is required (i.e., mirror 14 is fully transparent). In this case, grid 20 itself forms a resonant cavity with mirror 12. However, in practice, a mirror would be desirable to protect the array from the external environment.