Abstract:
A receiver equalizer that provides improved jitter tolerance relative to common adaptation mechanisms and that also provides inter-symbol interference. Improved jitter tolerance is an important benefit for SERDES receivers as tolerance to Sinusoidal Jitter is an important performance metric specified in most industry standards.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of application Ser. No. 13/941,902, filed Jul. 15, 2013, which is hereby incorporated by reference. 
    
    
     FIELD 
     The present disclosure relates generally to receivers. More particularly, the present disclosure relates to reducing jitter and inter-symbol interference in receivers. 
     BACKGROUND 
     High speed data communication between physically separated integrated components is a common function in current communication infrastructure systems. The separated integrated circuits can be physically separated on a common circuit board, or on separate circuit boards connected by a backplane, cable, or other communication medium. 
     As the data rate increases, as the physical separation distance increases, and/or the quality of the communication medium decreases, the transmitted signal will be increasingly impaired by a process commonly called Inter-Symbol Interference (ISI). ISI effectively smears the transmitted pulse waveform such that, at the receiver, each received pulse contains portions of signal energy from previously transmitted symbols (called Post-Cursor ISI) and may even contain portions of signal energy from symbols yet to be received (called Pre-Cursor ISI). 
     The phenomenon of ISI is well understood by those knowledgeable in the art. It is also well known that the impairment process of ISI can largely be mitigated through the use of equalizers, whether they are analog equalizers, digital equalizers, or combination of both. Within the scope of digital equalization, the equalizer can be in the form of a Finite Impulse Response (FIR), Infinite Impulse Response (IIR), Decision Feedback Equalizer (DFE), among others. Within the scope of analog equalization, the equalizer can be in the form of a Continuous Time Linear Equalizer (CTLE), Analog FIR, among others. 
     Often, a complicating issue is that the characteristic response of the transmission channel is unknown and can change from one installation to another. In these cases, a calibration, or adaptation process must be implemented to determine the required configuration of the receive equalizer that will exhibit the least ISI. 
     One type of common receiver architecture has the receiver sampling the received signal at a frequency that is twice the baud rate of the received signal. Using timing recovery strategies of known art, such as, for example, the Gardner method (F. M. Gardner, “ A BPSK/QPSK Timing - Error Detector for Sampled Receivers ”, IEEE Transactions on Communications, vol. COM-34, No. 5, May 1986), the sampling of the received waveform is adjusted such that one set of alternating samples aligns with the center of the received symbol waveform pulse with the opposite alternating samples aligning with the point mid-way between consecutive symbol pulses.  FIG. 1  depicts such a common, prior art receiver architecture including EQ adaptation. 
     Shown in  FIG. 1  is an analog signal, or received analog signal  30 , that contains bit sequences having a baud rate (symbol rate). The received analog signal is sampled, at twice the baud rate, and digitized by an analog to digital converter (ADC)  32 . The digitized output  33  of the ADC  32  is provided to a finite impulse response equalizer (FIR EQ)  34 . The FIR EQ  34  modifies (controls) the digitized output  33  and provides, at the output of the FIR EQ  34  an equalized signal  35 . The equalized signal  35  is provided to a a Serial In/Parallel Out (SIPO) device  36 , which can also be called as serializer/deserializer device. The SIPO device  36  outputs a data signal  37  and a timing signal  38 , each being a digital signal and each having the nominal baud rate to the received analog signal  30 . 
     The timing digital signal  38  and the data signal  37  are provided to a timing error detector (TED)  39 , which controls the timing of a sample clock  40 ; the sample clock  40  controls the ADC  32 . With respect to the data signal  37 , it is processed by a slicer  42 , whose output symbol signal  48  can be Boolean values “0”, or “1”, or, can be the constellation equivalent of the Boolean values, i.e., a “−1” or a “+1”. A summation device  44  takes the difference between the output symbol signal  48  and the data signal  37 . The difference  45  is provided to a controller (or adapter)  46 , which controls the FIR EQ  34  as a function of the difference  45 , and as a function of the digitized output  33 . 
       FIG. 2  depicts an exemplary “eye diagram” of the received waveform and the location of the waveform sampling instances as provided by the timing recovery mechanism of  FIG. 1 . A data sample DS n  is obtained by setting the sample clock  40  such that the middle of the eye in the eye diagram of  FIG. 2  is sampled by the ACD  32 . Timing samples TS n-1  and TS n  are obtained by sampling midway between adjacent eyes The ADC  32  can have many threshold levels (e.g., 32 levels as provided by a 5-bit ADC), or can have fewer levels (e.g., 2-levels as provided by a 1-bit slicer). 
       FIG. 3  shows the same eye diagram as in  FIG. 2  but superimposed with boundaries  50  defining areas within which signals samples are likely to be present/measured.  FIG. 4  shows only the boundaries  50  of  FIG. 3 . 
     A common means of adapting a digital FIR receiver equalizer is to use the Least Mean Square (LMS) algorithm to minimize the signal variation of the signal samples centered in the middle of the eye. Those knowledgeable in the art will recognize that the LMS algorithm is a simple to implement method of approximating the Minimum Mean Square Estimate (MMSE) which minimizes the combination of ISI and noise power at the Baud Sample. 
     While the LMS algorithm applied to eye-centered samples is a commonly used approach to receiver EQ adaptation, and one that optimizes the vertical eye opening at the location of the center eye sample, it is known to be sub-optimal with respect to the horizontal eye opening (for example, see A. C. Carusone, “ An Equalizer Adaptation Algorithm to Reduce Jitter in Binary Receivers ”, IEEE Transactions on Circuits and Systems—II: Express Briefs, Vol. 53, No. 9, September 2006). For example, the exemplary eye diagram of  FIG. 4  could be transformed, by an LMS algorithm applied to eye-centered samples, into the eye diagram of  FIG. 5 , which has a diminished horizontal opening. Those knowledgeable in the art will recognize that the vertical eye has been improved due to the reduction in ISI at the center of the eye, but the horizontal eye opening has been compromised (reduced), and hence, tolerance to sinusoidal jitter has been reduced. The reduction in ISI is shown in  FIG. 5  at reference numeral  52  and the reduced horizontal opening is shown at reference numeral  54 . 
     To mitigate this problem, a common technique in current art is to adapt the receiver EQ (e.g., the FIR EQ  34  in  FIG. 1 ) with the purpose of minimizing the amplitude variation at the zero-crossing between symbols of opposite polarity. Such zero-crossing areas are shown in  FIG. 6 , at reference numeral  56 . While this typically improves horizontal eye opening relative to that provided by normal eye center LMS adaptation, it has been found that zero-crossing adaptation is not reliable when the received signal is impaired by strong sinusoidal jitter or transient timing offset due to other impairments such as spread spectrum frequency modulation. 
     Therefore, improvements in receiver equalization are desirable. 
     SUMMARY 
     In a first aspect, the present disclosure provides a method of controlling a receiver equalizer. The method comprises: receiving an analog signal having a baud rate; sampling the analog signal at a sampling rate of twice that of the baud rate, the sampling to obtain a sampled signal that includes two interleaved digital signals, a first signal of the two interleaved digital signals being a data signal, the data signal comprising data samples sampled at the center of each consecutive symbol of the analog signal, a second of the two interleaved digital signal being a timing signal, the timing signal comprising timing samples sampled between the consecutive symbols; calculating a timing error term for timing samples comprised between data samples that define non-zero crossing transitions; and controlling the receiver equalizer as a function of the timing error term. 
     In a second aspect, the present disclosure provides a receiver. The receiver comprises: a sampling means for sampling an analog signal having a baud rate, the sampling means to sample the analog signal at a sampling rate of twice that of the baud rate, the sampling to obtain a sampled signal that includes two interleaved digital signals, a first signal of the two interleaved digital signals being a data signal, the data signal comprising data samples sampled at the center of each consecutive symbol of the analog signal, a second of the two interleaved digital signal being a timing signal, the timing signal comprising timing samples sampled between the consecutive symbols; processing means operationally connected to the sampling means, the processing means to calculate a timing error term of timing samples comprised between data samples that define non-zero crossing transitions; an equalizer to equalize one of the sampled signal and the analog signal; and a control module operationally connected to the processing means and to the equalizer the control module to control the equalizer as a function of the timing error term. 
     Other aspects and features of the present disclosure will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments in conjunction with the accompanying figures. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments of the present disclosure will now be described, by way of example only, with reference to the attached Figures. 
         FIG. 1  shows a prior art receiver architecture. 
         FIG. 2  shows an example of an eye diagram. 
         FIG. 3  shows the eye diagram of  FIG. 2  superimposed with boundaries of the eye-diagram. 
         FIG. 4  shows the eye diagram boundaries of  FIG. 3 . 
         FIG. 5  shows boundaries of a modified eye-diagram. 
         FIG. 6  shows an eye-diagram with zero-crossing areas. 
         FIG. 7  shows boundaries defining successive eyes with zero-crossing and non-zero-crossing areas. 
         FIG. 8  shows a flowchart of a prior art method of controlling the equalization of a receiver. 
         FIG. 9  shows a flowchart of a method in accordance with certain examples of the present disclosure. 
         FIG. 10  shows examples of data samples defining zero-crossing and non-zero-crossing transitions. 
         FIG. 11  shows an embodiment of a SerDes receiver in accordance with the present disclosure. 
         FIG. 12  shows a plot of when samples of an analog signal are taken in the embodiment of  FIG. 11 . 
         FIG. 13  shows a block diagram of an exemplary implementation of a equalization of signal in accordance with the present disclosure. 
         FIG. 14  shows another embodiment of a SerDes receiver in accordance with the present disclosure. 
         FIG. 15  shows utility upper samples and utility lower samples coincident in time with timing samples, in accordance with the present disclosure. 
         FIG. 16  shows utility upper samples and utility lower samples coincident in time with data samples, in accordance with the present disclosure. 
         FIG. 17  shows yet another embodiment of a SerDes receiver in accordance with the present disclosure. 
         FIG. 18  shows a block diagram of another exemplary implementation of a equalization of signal in accordance with the present disclosure. 
         FIG. 19  shows a block diagram of yet another exemplary implementation of a equalization of signal in accordance with the present disclosure. 
         FIG. 20  shows an embodiment of a receiver that adapts a feed forward equalizer of an upstream transmitter, in accordance with certain embodiments of the present disclosure. 
         FIG. 21  shows a flowchart of another method in accordance with certain examples of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The present disclosure recognizes that with linear electrical channels, the pre- and post-cursor ISI experienced at Timing Sample N (TS n ) is similar for the two following cases: DS n  has the opposite logical value as DS n+1  (i.e., a case of Zero-Crossing Transition, ZCT); and DS n  has the same logical value as DS n+1  (ie. a case of Non-Zero-Crossing Transition, NZCT). This is shown in  FIG. 7  where NZCT zones are at reference numeral  58  and the ZCT zones are at reference numeral  56 . The characteristic ISI is similar in these three zones. 
     Unlike prior art which adapts the receiver EQ based on information at the Timing Sample for cases of ZCT, the present disclosure uses information at the Timing Sample for cases of NZCT, that is, when DS n+1  and DS n  are on the same side of the zero signal level. Under benign jitter and spread spectrum clocking conditions, the disclosed method provides similar adapted EQ performance to prior art with respect to horizontal eye opening. Under conditions of strong jitter and spread spectrum clocking, the present disclosure provides much more robust adaptation than current art. Where current art may fail to adapt properly and provide an acceptable eye opening, the method of the present disclosure continues to work well. 
       FIG. 8  shows a flowchart of a prior art method of controlling the equalization of a receiver. At action  60 , a data sample DS n , a timing sample TS n , and a data sample DS n+1  are obtained. At action  62 , a timing error term is calculated only when DS n  and DS n+1  define a ZCT. Finally, at action  64 , the receiver equalization is controlled as a function of the timing error term calculated at action  62 . 
       FIG. 9  shows a flowchart of a method according to certain embodiments of the present disclosure. At action  66 , a data sample DS n , a timing sample TS n , and a data sample DS n+1  are obtained. At action  68 , a timing error term is calculated only when DS n  and DS n+1  define a NZCT. Finally, at action  70 , the receiver equalization is controlled as a function of the timing error term calculated at action  68 . 
     For greater certainty, data samples DS n  and DS n+1  will define a ZCT when one of them has a positive value and the other has a negative value. A positive value can be “1” or close to “1”; a negative value can be “−1” or close to “−1”. Data samples DS n  and DS n+1  will define a NZCT when both of them have a positive value or both of them have a negative value. 
       FIG. 10  shows examples of data samples DS n    72  and  76 , and data samples DS n+1    74  and  78 . In the case where DS n  is  72  and DS n+1  is  74 , DS n  and DS n+1  can be said to define a NZCT. That is, the “zero” signal level is not crossed in going from  72  to  74 . In the case where DS n  is  72  and DS n+1  is  78 , DSn and DS n+1  can be said to define a ZCT. The “zero” signal level is crossed in going from  72  to  78 . In the case where DS n  is  76  and DS n+1  is  78 , DS n  and DS n+1  can be said to define a NZCT. In the case where DS n  is  76  and DS n+1  is  74 , DS n  and DS n+1  can be said to define a ZCT. 
     Examples of the present disclosure are provided in the context of binary non-return to zero (NRZ) transmission as an example. Those knowledgeable in the art will recognize that the present disclosure is also applicable to other types of transmissions such as, for example, PAM-4 where four amplitude levels are used to carry 2-bits of information per baud symbol. 
       FIG. 11  shows an exemplary implementation of the present disclosure in the context of a SerDes Receiver  73 . A received signal (analog signal)  75  is sampled with an ADC  77 , which can be referred to as a sampling means. The ADC  77  outputs a sampled signal  79 , which is provided to an FIR EQ  80  to remove undesired ISI. The FIR EQ  80  can also be referred to as an equalizer or as equalizing means. The sampled signal  79  can be represented as two interleaved digital signals. One of the two interleaved digital signals is a data signal that comprises data samples sampled at the center of each consecutive symbol of the received analog signal. That is, the data signal comprises data samples DS n , DS n+1 , DS n+2 , . . . etc. A second of the two interleaved digital signal is a timing signal, the timing signal comprising timing samples sampled midway between the consecutive symbols. That is, the timing signal comprises timing samples TS n , TS n+1 , TS n+2 , . . . etc. In the context of the present disclosure, the subscript of the data and time signal are indicative of time. For example, the subscript “n−1” represents an earlier time than the subscript “n”, which represents an earlier time than “n+1”. 
       FIG. 12  shows a plot of when the ADC  77  samples the received signal  77 . The sampling occurs at . . . , TS n-1 , DS n , TS n , DS n+1 , TS n+1 , . . . 
     Returning to  FIG. 11 , the FIR EQ  80  outputs an equalized signal  82 , which can also be referred to as a modified signal. The equalized signal  82  contains an equalized data signal (the previously-mentioned data signal that has been equalized by the FIR EQ  80 ) interleaved with an equalized timing signal (the previously-mentioned timing signal that has been equalized by the FIR EQ  80 ). A SIPO device  84  receives the equalized signal  82  and de-interleaves the equalized data signal from the equalized timing signal. The equalized data signal  86  and the equalized timing signal  88  are shown at the output of the SIPO device  84 . 
     The equalized data signal  86  and the equalized timing signal  88  are provided to a timing error detector  90 , which provides an output signal  92  to a loop filter  94 . The loop filter  94  outputs a control signal  96  that controls the timing of a sample clock  98 ; the sample clock  98  controls the ADC  77  in terms of the frequency at which the ADC  76  samples the received signal  75  and at which portion of a symbol the analog to digital conversion is effected by the ADC  77 . In the present example, the sampling frequency is twice that of the baud rate. 
     Referring again to the equalized data signal  86 , it is provided also to a slicer  100 , which, in the present example, outputs “+1” if an equalized data sample N (EDS n ) has a value larger than “0”, or outputs a “−1” if EDS n  does not have value larger than “0”. Reference numeral  101  represents the output of the slicer  100 . 
     Additionally, the equalized data signal  86  is provided to a data signal error computing module  102 , which computes a data signal error term as a function of the equalized data signal  86 . The data signal error computing module  102  can compute the data signal error term, ε DS    103  for each EDS n  as, for example:
 
ε DS =sign( EDS   n )− EDS   n   (1)
 
where the sign( ) function outputs “+1” if the argument (EDS n  in this case) is positive, “0” if the argument is zero, and “−1” if the argument is negative.
 
     The SerDes receiver  73  example of  FIG. 11  also includes a timing signal error computing module  104  that receives as input, both the equalized data signal  86  and the equalized timing signal  88 , and computes a timing signal error term as a function of the equalized data signal  86  and as a function of the equalized timing signal  88 . The data error computing module  102  and the timing signal error computing module  104  can also be referred to as a processing means. The timing signal error computing module can compute the timing signal error term, ε TS    105  for each ETS n    88  as, for example:
 
ε TS =[sign( ETS   n )− ETS   n   ]·xnor ( EDS   n+1 &gt;0 , EDS   n &gt;0)  (2)
 
where the sign( ) function outputs “+1” if the argument (ETS n  in this case) is positive, “0” if the argument is zero, and “−1” if the argument is negative. The xnor( ) function outputs “1” if both of its arguments have the same value and outputs “0” if its arguments are different (one of the arguments is “1” and the other is “0”). As such, as per equation 2, ε TS  will have a non-zero value only when EDS n+1 &gt;0 and EDS n &gt;0, or when EDS n+1 &lt;0 and EDS n &lt;0. Otherwise, if EDS n+1 &gt;0 and EDS n &lt;0, or vice versa, the value of ε TS  will be nil. That is, the timing signal error ε TS  for a timing signal sample TS n  will be nil in all cases where DS n  and DS n+1  define a ZCT. ε TS  can be non-nil only when DS n  and DS n+1  define a NZCT. As will be understood by the skilled worker, an equivalent form of equation 2 is:
 
ε TS =[sign( ETS   n )− ETS   n   ]·xnor ( EDS   n+1 &lt;0 , EDS   n &lt;0)  (3)
 
That is, as per equation 3, ε TS  will have a non-zero value only when EDS n+1 &lt;0 and EDS n &lt;0, or when EDS n+1 &gt;0 and EDS n &gt;0.
 
     In the example of  FIG. 11 , both ε DS    103  and ε TS    105  are provided to an adapt module  106 , which controls the FIR EQ  80  using, for example, an LMS algorithm or any other suitable algorithm. The adapt module can also be referred to as a control means or as a control module. In addition to receiving ε DS    103  and ε TS    105 , the adapt module  106  also receives a data signal  108  and a timing signal  110 , which are provided at the output of a SIPO device  112 . The SIPO device  112  de-interleaves the data signal  108  from the timing signal  110  in response to receiving a time-delayed signal  114  that contains the data signal  108  interleaved with the timing signal  110 . The time-delayed signal  114  is the sampled signal  79  delayed by a delay module  116 . The reason for the delay module  116  is that processing by the FIR EQ  80 , the data signal error computing module  102  and the timing signal error computing module  104 , will cause the error terms input to the adapt module  106  to be delayed. As such, the data signal  108  and the timing signal  110  need to be delayed accordingly for proper time alignment. This alignment could be done within the adapt module  106 , or explicitly outside the adapt module  106 , at the delay module  116 . 
     According to equations 1 and 2 (or 1 and 3), the computed value of ε TS  will be zero unless successive baud symbols are the same, that is, when a zero-transition is not expected. Those knowledgeable in the art will recognize that if the xnor( ) function in equation 2 (or equation 3) is replaced with a xor( ) function, the operation of the circuit will be similar to a number of the prior art techniques that adapt the FIR EQ based on the zero-crossing transition between baud symbols. 
     The adapt module  106  controls the FIR EQ  80  to equalize the sampled signal  79 , which contains the data signal  108  interleaved with the timing signal  110 , as a function of the timing signal error term ε TS  and the data signal error term ε DS . When only the timing signal error term is considered, the adapt module  106  controls the FIR EQ  80  in accordance with:
 
 Pre 2′= Pre 2+μ TS ·ε TS   ·TS   n+1   (4)
 
 Pre 1′= Pre 1+μ TS ·ε TS   ·DS   n+1   (5)
 
 Curs′=Curs+μ   TS   ·ε   TS   ·TS   n   (6)
 
 Post 1′= Post 1+μ TS ·ε TS   ·DS   n   (7)
 
 Post 2′= Post 2+μ TS ·ε TS   ·TS   n−1   (8)
 
     When only the data signal error term is considered, the adapt module  106  controls the FIR EQ  80  in accordance with:
 
 Pre 2′= Pre 2+μ DS ·ε DS   ·DS   n+1   (9)
 
 Pre 1′= Pre 1+μ DS ·ε DS   ·TS   n   (10)
 
 Curs′=Curs+μ   DS   ·ε   DS   ·DS   n   (11)
 
 Post 1′= Post 1+μ DS ·ε DS   ·TS   n−1   (12)
 
 Post 2′= Post 2+μ DS ·ε DS   ·DS   n−1   (13)
 
     When both the timing signal error and the data signal error terms are taken into account, the adapt module  106  controls the FIR EQ  80  in accordance with:
 
 Pre 2′= Pre 2+μ TS ·ε TS   ·TS   n+1 +μ DS ·ε DS   ·DS   n+1   (14)
 
 Pre 1′= Pre 1+μ TS ·ε TS   ·DS   n+1 +μ DS ·ε DS   ·TS   n   (15)
 
 Curs′=Curs+μ   TS   ·ε   TS   ·TS   n +μ DS ·ε DS   ·DS   n   (16)
 
 Post 1′= Post 1+μ TS ·ε TS   ·DS   n +μ DS ·ε DS   ·TS   n-1   (17)
 
 Post 2′= Post 2+μ TS ·ε TS   ·TS   n−1 +μ DS ·ε DS   ·DS   n-1   (18)
 
     In equations 4-18, the FIR EQ taps (Pre 2 , Pre 1 , Curs, Post 1 , and Post 2 ) are spaced at intervals of ½ baud duration. If a baud-spaced EQ is desired, Pre 1  and Post 1  are set to zero and not updated. If more taps than specified in equations 4-18 are desired, equations 4-18 can easily be adapted, as would be understood by the skilled worker. 
     The choice of adapting based on eye-center criterion or non-zero-crossing criterion, or both, is supported through the independent scaling parameters μ DS  and μ TS . Setting either to zero removes that criterion from the adaptation. Setting the scaling parameters μ DS  and μ TS  to a small positive value includes that criterion in the adaptation. When non-zero, the values selected for the scaling parameters can be less than 1, such as 1/32, or 1/64, or any other suitable value. Those knowledgeable in the art will understand the fundamental tradeoffs of selecting larger or smaller values for the scaling parameters. In the present example, the signal sample at the output of the FIR EQ  80  is described by equation 18a, where the signal  79  is denoted by S n  and the signal  82  is denoted by ES n .
 
 ES   n   =Pre 2 ·S   n+4   +Pre 1· S   n+2   +Curs·S   n   +Post 1· S   n-2   +Post 2· S   n-4   (18a)
 
     A block diagram of an exemplary implementation of equations 14-18 is shown in  FIG. 13 . This implementation supports the adaptation of 5 T/2-spaced FIR EQ coefficients (taps). Upon initial startup, the summing node for the cursor tap is initialized to a value of 1, and the summing node for all other taps are initialized to a value of 0. Shown in  FIG. 13  are the data signal  108  and the timing signal  110 , time delays  118 , multiplication nodes  120 , addition nodes  122 , and summation nodes (e.g., running summation)  124 . 
     The exemplary embodiments of  FIGS. 11 and 13  can be implemented in hardware and or software. 
       FIG. 14  shows an alternative SerDes receiver architecture in accordance with the present disclosure. The exemplary SerDes receiver  126  of  FIG. 14  comprises an Analog FIR (AFIR)  128  used to equalize a received analog signal  130 . The AFIR  128  outputs an equalized signal (modified signal)  132 , which is sampled with a 1-bit slicer  134  at a rate equal to twice the baud rate of the received analog signal  130 . The 1-bit slicer  134  can be referred to as a sampling means. The 1-bit slicer  134  outputs a binary signal  135 . The binary signal  135  can be represented as two interleaved digital signals. One of the two interleaved digital signals is a data signal that comprises data samples sampled at the center of each consecutive symbol of the received analog signal. That is, the data signal comprises data samples DS n , DS n+1 , DS n+2 , . . . etc. A second of the two interleaved digital signal is a timing signal, the timing signal comprising timing samples sampled midway between the consecutive symbols. That is, the timing signal comprises timing samples TS n , TS n+1 , TS n+2 , . . . etc. 
     A SIPO device  136  receives the binary signal  135  and de-interleaves the data signal from the timing signal. The data signal  138  and the timing signal  140  are shown at the output of the SIPO device  136 . 
     The data samples DS n , DS n+1 , DS n+2 , . . . of the data signal  138 , and the timing samples are TS n , TS n+1 , TS n+2 , . . . of the timing signal  140  are used by a timing recovery circuit such that the data samples are aligned in the middle of the eye and the timing samples are aligned with the zero-crossing transitions between baud intervals. The data samples and the timing samples at the output to the SIPO device  136  have a value of either “+1” or “−1”. 
     The data samples  138  and the timing samples  140  are provided to a timing error detector  142 , which provides an output signal  143  to a loop filter  144 . The loop filter  144  outputs a control signal  145  that controls the timing of a sample clock  146 ; the sample clock  146  controls the 1-bit slicer  134  in terms of the frequency at which the 1-bit slicer  134  samples the received signal  130  and at which portion of a symbol the analog to digital conversion is effected by the 1-bit slicer  134 . 
     Additionally, the SerDes receiver  126  comprises a slicer  150  set to output utility lower samples (UL n ) and a slicer  152  set to output utility upper samples (UU n ). The threshold level of the slicer  150  and of the slicer  152  are adjustable. For example, the slicer  150  can be set to output a value of “1” when the signal at the input of the slicer  150  has a value greater than a first threshold value, and a value of “0” otherwise; the slicer  152  can be set to output a value of “1” when the signal at the input of the slicer  152  has a value greater than a second threshold value, and a value of “0” otherwise. 
     Further, the slicers  150  and  152  are operationally connected to the sample clock  146 , which causes the slicers  150  and  152  to sample the equalized signal  132  at a frequency equal to that of the baud rate of the equalized received analog signal  130 . A time delay module  148  controls where, with respect to the bits of the received analog signal  130 , the sampling is effected. The slicers  150  and  152  can also be referred to as sampling means or as additional sampling means. 
     An example of the sampling of the equalized signal  132  with the 1-bit slicers  150  and  152  is shown at  FIG. 15 . In  FIG. 15 , the time delay module  148  is set to have the slicer  150  and the slicer  152  sample the equalized signal  132  coincidently with the slicer  134  sampling the equalized signal  132  to output timing samples TS n . 
     In the case of  FIG. 15 , the error on the timing signal can be calculated by the error calculation module  154  as a function of UU n , TS n , UL n , DS n , and DS n+1 . For example, the error on the timing signal can be computed as:
 
ε TS ={1−2·[(UU n   ∩TS   n )∪( UL   n ∩not( TS   n ))]}· xnor ( DS   n   , DS   n+1 )  (19)
 
     As an example, if UU n  and TS n  are equal to “1” or, if UL n =1 and TS n =0 (not(TS n )=1), ε TS  will be equal to −1, assuming that DS n  and DS n+1  have the same value. However, if either one of UU n  or TSn is equal to “0” and if UL n =0 or not(TS n )=0, then ε TS  will be equal to “+1”, again, assuming that DS n  and DS n+1  have the same value. In any case, if DS n  and DS n+1  have different values, ε TS  will be equal to zero. Table 1 shows ε TS  for different combinations of UU n , TS n , UL n , not(TS n ), DS n , and DS n+1 . Table 1 recognizes that the only valid combinations of (UU n , TS n , UL n ) are {000, 001, 011, 111}. Other combinations are possible only when the threshold voltages are defined such that the condition V UU &gt;V TS &gt;V UL  is not satisfied. For invalid codes, it is optional to implement circuitry to detect these conditions and force the error term ε TS  to a zero value. 
     
       
         
               
               
               
               
               
               
               
             
               
             
               
               
               
               
               
               
               
             
               
             
               
               
               
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 UU n   
                 TS n   
                 UL n   
                 not(TS n )  
                 DS n   
                 DS n+1   
                 ε TS   
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 Valid Combinations 
               
             
          
           
               
                 0 
                 0 
                 0 
                 1 
                 1 
                 1 
                 +1 
               
               
                 0 
                 0 
                 0 
                 1 
                 0 
                 0 
                 +1 
               
               
                 0 
                 0 
                 0 
                 1 
                 1 
                 0 
                 0 
               
               
                 0 
                 0 
                 0 
                 1 
                 0 
                 1 
                 0 
               
               
                 0 
                 0 
                 1 
                 1 
                 0 
                 0 
                 −1 
               
               
                 0 
                 0 
                 1 
                 1 
                 1 
                 1 
                 −1 
               
               
                 0 
                 0 
                 1 
                 1 
                 1 
                 0 
                 0 
               
               
                 0 
                 0 
                 1 
                 1 
                 0 
                 1 
                 0 
               
               
                 0 
                 1 
                 1 
                 0 
                 1 
                 1 
                 +1 
               
               
                 0 
                 1 
                 1 
                 0 
                 0 
                 0 
                 +1 
               
               
                 0 
                 1 
                 1 
                 0 
                 1 
                 0 
                 0 
               
               
                 0 
                 1 
                 1 
                 0 
                 0 
                 1 
                 0 
               
               
                 1 
                 1 
                 1 
                 0 
                 1 
                 1 
                 −1 
               
               
                 1 
                 1 
                 1 
                 0 
                 0 
                 0 
                 −1 
               
               
                 1 
                 1 
                 1 
                 0 
                 0 
                 1 
                 0 
               
               
                 1 
                 1 
                 1 
                 0 
                 1 
                 0 
                 0 
               
             
          
           
               
                 Invalid Combinations 
               
             
          
           
               
                 1 
                 0 
                 1 
                 1 
                 1 
                 1 
                   
               
               
                 1 
                 1 
                 0 
                 0 
                 1 
                 1 
                   
               
               
                 0 
                 1 
                 0 
                 0 
                 1 
                 1 
                   
               
               
                 1 
                 0 
                 0 
                 1 
                 1 
                 1 
                   
               
               
                 1 
                 0 
                 1 
                 1 
                 1 
                 0 
                   
               
               
                 1 
                 1 
                 0 
                 0 
                 1 
                 0 
                   
               
               
                 0 
                 1 
                 0 
                 0 
                 1 
                 0 
                   
               
               
                 1 
                 0 
                 0 
                 1 
                 1 
                 0 
                   
               
               
                 1 
                 0 
                 1 
                 1 
                 0 
                 1 
                   
               
               
                 1 
                 1 
                 0 
                 0 
                 0 
                 1 
                   
               
               
                 0 
                 1 
                 0 
                 0 
                 0 
                 1 
                   
               
               
                 1 
                 0 
                 0 
                 1 
                 0 
                 1 
                   
               
               
                 1 
                 0 
                 1 
                 1 
                 0 
                 0 
                   
               
               
                 1 
                 1 
                 0 
                 0 
                 0 
                 0 
                   
               
               
                 0 
                 1 
                 0 
                 0 
                 0 
                 0 
                   
               
               
                 1 
                 0 
                 0 
                 1 
                 0 
                 0 
               
               
                   
               
             
          
         
       
     
     The error calculation module  154  provides the error on the timing signal to an adapt module  155 , which controls the AFIR  128 . 
     If, instead of having the time delay module  148  is set to have the slicer  150  and the slicer  152  sample the equalized signal  132  coincidently with the slicer  134  sampling the equalized signal  132  to output a timing sample, as shown at  FIG. 15 , the time delay module  148  is set to have the slicer  150  and the slicer  152  sample the equalized signal  132  coincidently with the slicer  134  sampling the equalized signal  132  to output data sample DS n , as shown at  FIG. 16 , the error ε DS  on the data sample can be calculate as a function of UU n , UL n  and DS n :
 
ε DS ={1−2·[( UU   n   ∩DS   n )∪( UL   n ∩not( DS   n ))]}  (20)
 
     Table 2 shows ε DS  for different combinations of UU n , UL n , DS n , and not(DS n ). Table 2 recognizes that the only valid combinations of (UU n , DS n , UL n ) are {000, 001, 011, 111}. Other combinations are possible only when the threshold voltages are defined such that the condition V UU &gt;V DS &gt;V UL  is not satisfied. For invalid codes, it is optional to implement circuitry to detect these conditions and force the error term ε DS  to a zero value. 
     
       
         
               
               
               
               
               
             
               
             
               
               
               
               
               
             
               
             
               
               
               
               
               
             
           
               
                 TABLE 2 
               
               
                   
               
               
                 UU n   
                 DS n   
                 UL n   
                 not(DS n ) 
                 ε DS   
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 Valid Combinations 
               
             
          
           
               
                 0 
                 0 
                 0 
                 1 
                 +1 
               
               
                 0 
                 0 
                 1 
                 1 
                 −1 
               
               
                 0 
                 1 
                 1 
                 0 
                 +1 
               
               
                 1 
                 1 
                 1 
                 0 
                 −1 
               
             
          
           
               
                 Invalid Combinations 
               
             
          
           
               
                 1 
                 0 
                 1 
                 1 
                   
               
               
                 1 
                 1 
                 0 
                 0 
                   
               
               
                 0 
                 1 
                 0 
                 0 
                   
               
               
                 1 
                 0 
                 0 
                 1 
               
               
                   
               
             
          
         
       
     
       FIG. 17  shows another exemplary SerDes receiver  156 , which is the same as the SerDes receiver  126  of  FIG. 14  except that the time delay module  148  is set to have the slicer  150  and the slicer  152  sample the equalized signal  132  coincidently with the slicer  134  sampling the equalized signal  132  to output data sample DS n , as shown at  FIG. 16 . Also, the error calculation module  154  in  FIG. 17  does not require TS n  as an input. 
     The computation of the timing sample error and of the data sample error defined at equations 19 and 20 use standard Boolean notation. The terms inside the square brackets, [ ], yield Boolean values that are then converted to unit amplitude signed values. The multiplication by the xnor( ) term preserves the value or forces to zero. It is important to emphasize that the UU samples used in computing of ε TS  have the timing alignment illustrated in  FIG. 15  while the UU samples used in computation of ε DS  have the timing alignment illustrated in  FIG. 16 . With only a single pair of utility samplers (1-bit slicers  150  and  152 ) it is not possible to simultaneously compute ε TS  and ε DS . Those knowledgeable in the art will recognize that using additional utility samplers (1-bit samplers) will allow simultaneous computation of ε TS  and ε DS . 
     The adapt module  155  controls the AFIR  128  to equalize the received analog signal  130 . When only the timing signal error term is considered, i.e., in the case of the non-zero-crossing criterion related to the SerDes receiver  126  of  FIG. 14  and the sampling of  FIG. 15 , the adapt module  155  controls the AFIR  128  in accordance with:
 
 Pre′=Pre+μ   TS ·ε TS   ·DS   n+2   (21)
 
 Curs′=Curs+μ   TS ·ε TS   ·DS   n   (22)
 
 Post′=Post+μ   TS ·ε TS   ·DS   n-1   (23)
 
     Equations 21, 22, and 23 assume that the AFIR  128  is a 3-tap FIR with baud spacing. 
     When only the data signal error term is considered, i.e., in the case of the eye-center criterion related to the SerDes receiver  156  of  FIG. 17  and the sampling of  FIG. 16 , the adapt module  155  controls the AFIR  128  in accordance with.
 
 Pre′=Pre+μ   DS ·ε DS   ·DS   n+1   (24)
 
 Curs′=Curs+ 82     DS   ·ε   DS   ·DS   n   (25)
 
 Post′=Post+μ   TS ·ε TS   ·DS   n-1   (26)
 
Equations 24, 25, and 26 assume that the AFIR  128  is a 3-tap FIR with baud spacing.
 
     When both the data signal error term and the timing signal error term are considered, the adapt module  155  controls the AFIR  128  in accordance with:
 
 Pre′=Pre+μ   TS ·ε TS   ·DS   n+2 +μ DS ·ε DS   ·DS   n+1   (27)
 
 Curs′=Curs+μ   TS   ·ε   TS   ·DS   n+1 +μ DS ·ε DS   ·DS   n+1   (28)
 
 Post′=Post+μ   TS ·ε TS   ·DS   n-1 +μ DS ·ε DS   ·DS   n-1   (29)
 
     The terms μ TS  and μ DS  are non-negative scalars, having a value typically less than 1, that control the adaptation. When set to zero, they remove that criterion from adaptation. When set to small positive values such as 1/32 or 1/64, they include that criterion in the adaptation of the AFIR  128 . 
     A block diagram of an exemplary implementation of equations 21, 22, and 23 is shown at  FIG. 18 . A block diagram of an exemplary implementation of equations, 24, 25, and 26 is shown at  FIG. 19 . As will be understood by the skilled worker, there are strong similarities between the structures of  FIGS. 18 and 19 ; those knowledgeable in the art will recognize the means by which these two structures can be combined into a single structure. 
     In the embodiment of  FIG. 18  and in the embodiment of  FIG. 19 , upon initial startup, the summing node  124  (running summation node) for the cursor tap is initialized to a value of 1, and the summing nodes  124  for all other taps are initialized to a value of 0. Shown in  FIGS. 18 and 19  is the data signal  160 , time delays  162 , multiplication nodes  164 , addition nodes  122 , and summation nodes (e.g., running summation)  124 . 
     The present disclosure provides details on ADC and slicer based NRZ SerDes receivers, with variations for baud-spaced versus fractional-spaced FIR EQs and Analog versus Digital FIR EQs. 
     The present disclosure is also applicable to multi-level SerDes signaling schemes such as PAM-4 (4-level Pulse Amplitude Modulation). The computation of the error terms ε DS  and ε TS  will need to be generalized but this should be relatively simple for someone knowledgeable in the art based on the inventive description herein. This applies to both ADC and slicer based receivers. For slicer based receivers, additional alterations will be required for the Adapt block to convert the slicer bit pattern to a numerical value representing the received symbol (e.g., +/−1, +/−3 for PAM-4). 
     The present disclosure is presented in the context of a serialized architecture. At very high SerDes data rates, such as above 1 GHz for example, it is often necessary to implement the receiver in a parallel manner to simultaneously process multiple baud periods. The scope of the present disclosure includes such parallel implementations. 
     Examples of the present disclosure describe updating all of the available EQ coefficients. In some cases, it may be desirable to fix some of the EQ coefficients at specific values and use the corresponding update equations to adjust other circuit parameters. For example, the cursor tap coefficient can be fixed at a unit value and the update equation used to adjust the gain setting of a variable gain amplifier in the signal path. 
     Examples of the present disclosure show the adaptation of an equalizer located within a receiver. It is equally possible to adapt an equalizer located within the sending transmitter. There will likely be increased adaptation loop latency in this case which must be managed, but this is common knowledge to those in the art. An exemplary design of a receiver that adapts a feed forward equalizer (FFE) of an upstream Transmitter is shown in  FIG. 20 . The architecture is similar to that of  FIG. 11 , except the input of ADC  77  samples to the Adapt block  106  of  FIG. 11  is replaced with the equalized and sliced Timing and Data Samples  900  and  902  respectively. Also the updated EQ tap values are to be communicated from the adapt module  106  to the upstream transmitter (not shown) through an available Back-Channel Communication channel  904  that is often a part of the SerDes data protocol. 
       FIG. 21  shows a flowchart of a method according to certain embodiments of the present disclosure. At action  910 , an analog signal having a baud rate is received. In the context of the embodiment (example) of  FIG. 11 , the analog signal is received  75  is received at the ADC  77 . In the context of the embodiments (examples) of  FIGS. 14 and 17 , the equalized signal  132 , which is an analog signal is received at the slicer  134 . 
     Returning to  FIG. 21 , at action  912 , the analog signal is sampled. In the context of the example of  FIG. 11 , the analog signal is sampled by the ADC  77 . In the context of the embodiments of  FIGS. 14 and 17 , the analog signal is sampled at the slicer  134 . Action  912  results in obtaining data samples and timing samples. 
     Again with reference to  FIG. 21 , at action  914 , a timing error term is calculated for timing samples comprised between data samples that define NZCT. In the context of the embodiment of  FIG. 11 , this can be achieved through, for example, equation 2. In the context of the embodiment of  FIG. 14 , this can be achieved through, equation 14. 
     Referring yet again to  FIG. 21 , at action  916 , the receiver equalizer is controls as a function of the timing error term. In the context of the embodiment of  FIG. 14 , this can be achieved through the adapt module  106 , which receives the timing error term and control the FIR EQ  80  as a function of the timing error term. In the context of the embodiment of  FIG. 14 , this can be achieved by the adapt module  155 , which receives the timing error term and control the analog FIR  128  as a function of the timing error term. 
     Examples of the present disclosure show the combination of center eye adaptation criterion and non-zero-crossing adaptation criterion. This is not restrictive and numerous other criteria may be included in the adaptation process without departing from the scope of the present disclosure. 
     Examples of the present disclosure assume a sampling rate of twice the signal baud rate. This is the minimum sample rate. Higher sample rates can easily be accommodated, as will be understood by the skilled worker. 
     This present disclosure provides an improved method and apparatus for adapting inter-symbol interference compensating equalizers in a SerDes receiver. The improved adaptation provides increased tolerance to other jitter sources and is more robust in the presence of strong timing impairments. Advantageously, the present disclosure provides better jitter performance with less complex and lower power SerDes architectures. 
     In some embodiments of the present disclosure for high speed serdes receivers, it is possible to incorporate the computation of the error terms and the adaptation of the EQ filter taps in RTL (Register Transfer Level) cast in a standard CMOS silicon device. The adaptation portion can be part of a larger adaptation engine that implements the adaptation of several components in a round-robin fashion, or it can be separate and dedicated for each and every SerDes receiver. A state machine to orchestrate the adaptation procedure can also be implemented within RTL. 
     In other embodiments can have the error computation and filter tap adaptation performed by a firmware based processor using data captured by the SerDes. This processor could be incorporated within the same device as the SerDes receiver or could be off-chip. It is further possible that the computation burden can be shared by RTL and firmware based processing. 
     In the preceding description, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the embodiments. However, it will be apparent to one skilled in the art that these specific details are not required. In other instances, well-known electrical structures and circuits are shown in block diagram form in order not to obscure the understanding. For example, specific details are not provided as to whether the embodiments described herein are implemented as a software routine, hardware circuit, firmware, or a combination thereof. 
     Embodiments of the disclosure can be represented as a computer program product stored in a machine-readable medium (also referred to as a computer-readable medium, a processor-readable medium, or a computer usable medium having a computer-readable program code embodied therein). The machine-readable medium can be any suitable tangible, non-transitory medium, including magnetic, optical, or electrical storage medium including a diskette, compact disk read only memory (CD-ROM), memory device (volatile or non-volatile), or similar storage mechanism. The machine-readable medium can contain various sets of instructions, code sequences, configuration information, or other data, which, when executed, cause a processor to perform steps in a method according to an embodiment of the disclosure. Those of ordinary skill in the art will appreciate that other instructions and operations necessary to implement the described implementations can also be stored on the machine-readable medium. The instructions stored on the machine-readable medium can be executed by a processor or other suitable processing device, and can interface with circuitry to perform the described tasks. 
     The above-described embodiments are intended to be examples only. Alterations, modifications and variations can be effected to the particular embodiments by those of skill in the art without departing from the scope, which is defined solely by the claims appended hereto.