Abstract:
The disclosure discloses a shift register unit, a shift register, a display panel and a display, and belongs to display driving technology. The shift register unit comprises: twelve transistors M 1,  M 2, . . . ,  M 12;  one capacitor C 1;  four signal input terminals INPUT, RESET, CLK, CLKB; one signal output terminal OUTPUT; and one or more power supply terminals. The disclosure may decrease the output delay and attenuation, and improve an anti-interference capability, so that the shift register may operate stably and a driving margin of the shift register could be increased.

Description:
TECHNICAL FIELD OF THE DISCLOSURE 
       [0001]    The present disclosure relates to display driving technology, and particularly to a shift register unit, a shift register, and a display panel and a display including the shift register. 
       BACKGROUND 
       [0002]    Existing shift register commonly comprises transistors and capacitors, and its internal delay is mainly caused by a prolonged turn-on time period of the transistors and attenuation. Therefore, the existing shift register has shortcomings that its delay is long and a reset speed for a node in the existing shift register is slow, such that charging at the node of the shift register is affected and an output delay and attenuation are further deteriorated, which in turn renders the shift register operating unstably. 
       SUMMARY 
     Technical Problem To Be Solved 
       [0003]    Technical problems to be solved by the embodiments of the disclosure are how to decrease the output delay and attenuation, and to improve an anti-interference capability, so that the shift register may operate stably and a driving margin of the shift register could be increased. 
       Solution of The Disclosure 
       [0004]    In one embodiment of the disclosure, there is provided a shift register unit, comprising: twelve transistors M 1 , M 2 , . . . , M 12 ; one capacitor C 1 ; four signal input terminals INPUT, RESET, CLK, CLKB; one signal output terminal OUTPUT; and one power supply terminal VSS, and connection relationships among them are as follows: 
         [0005]    a gate of the M 1  is connected to both the signal input terminal INPUT and gates of the M 6  and M 9 , and a source of the M 1  is connected to drains of the M 2  and M 11 ; 
         [0006]    a gate of the M 2  is connected to the signal input terminal RESET; 
         [0007]    both a gate and a drain of the M 5  are connected to the signal input terminal CLKB, and a source of the M 5  is connected to drains of the M 6  and M 7 ; 
         [0008]    a gate of the M 8  is connected to the source of the M 5 , a drain of the M 8  is connected to both drains of the M 9  and M 10  and gates of the M 11  and M 12 ; 
         [0009]    a drain of the M 3  is connected to the signal input terminal CLK, a gate of the M 3  is connected to one end of the capacitor C 1  and the source of the M 1 , and a source of the M 3  is connected to the other end of the capacitor C 1 , gates of the M 7  and M 10 , drains of the M 12  and M 4  and the signal output terminal OUTPUT; 
         [0010]    sources of M 2 , M 11 , M 6 , M 7 , M 9 , M 10 , M 12  and M 4  are connected to the power supply terminal VSS, and a gate of the M 4  is connected to the signal input terminal RESET. 
         [0011]    The shift register unit further comprises two additional signal input terminals: fifth signal input terminal and sixth signal input terminal. A drain of the M 1  is connected to the fifth signal input terminal, and when the gate of the MI is at the high level, the signal input terminal at the drain of the M 1  is also at a high level. A source of the M 8  is connected to the sixth signal input terminal, and when the gate of the M 8  is at the high level, the signal input terminal at the source of the M 8  is also at a high level. 
         [0012]    In one example, two power supply terminals VDD 1 , VDD 2  are further involved; the fifth signal input terminal connected with the drain of the M 1  is connected to the power supply terminal VDD 1 ; and the sixth signal input terminal connected with the source of the M 8  is connected to the power supply terminal VDD 2 . 
         [0013]    In one example, the fifth signal input terminal connected with the drain of the M 1  is said signal input terminal INPUT, and the drain of the M 1  is also connected to gates of the M 6  and M 9 ; the sixth signal input terminal connected with the source of the M 8  is the signal input terminal CLKB, and the source of the M 8  is also connected to both the gate and the drain of the M 5 . 
         [0014]    In one example, one power supply terminal VDD 1  is further involved; the fifth signal input terminal connected with the drain of the M 1  is connected to the power supply terminal VDD 1 ; the sixth signal input terminal connected with the source of the M 8  is connected to the signal input terminal CLKB, and the source of the M 8  is also connected to both the gate and the drain of the M 5 . 
         [0015]    In another embodiment of the disclosure, there is further provided a shift register including a plurality of shift register units, each shift register unit comprising: twelve transistors M 1 , M 2 , . . . , M 12 ; one capacitor C 1 ; four signal input terminals INPUT, RESET, CLK, CLKB; one signal output terminal OUTPUT; and one power supply terminal VSS, and connection relationships among them are as follows: 
         [0016]    a gate of the M 1  is connected to both the signal input terminal INPUT and gates of the M 6  and M 9 , and a source of the M 1  is connected to drains of the M 2  and M 11 ; 
         [0017]    a gate of the M 2  is connected to the signal input terminal RESET; 
         [0018]    both a gate and a drain of the M 5  are connected to the signal input terminal CLKB, and a source of the M 5  is connected to drains of the M 6  and M 7 ; 
         [0019]    a gate of the M 8  is connected to the source of the M 5 , a drain of the M 8  is connected to both drains of the M 9  and M 10  and gates of the M 11  and M 12 ; 
         [0020]    a drain of the M 3  is connected to the signal input terminal CLK, a gate of the M 3  is connected to one end of the capacitor C 1  and the source of the M 1 , and a source of the M 3  is connected to the other end of the capacitor C 1 , gates of the M 7  and M 10 , drains of the M 12  and M 4  and the signal output terminal OUTPUT; 
         [0021]    sources of M 2 , M 11 , M 6 , M 7 , M 9 , M 10 , M 12  and M 4  are connected to the power supply terminal VSS, and a gate of the M 4  is connected to the signal input terminal RESET. 
         [0022]    The shift register unit further comprises two additional signal input terminals: fifth signal input terminal and sixth signal input terminal. A drain of the M 1  is connected to the fifth signal input terminal, and when the gate of the M 1  is at the high level, the signal input terminal at the drain of the M 1  is also at a high level. A source of the M 8  is connected to the sixth signal input terminal, and when the gate of the M 8  is at the high level, the signal input terminal at the source of the M 8  is also at a high level. 
         [0023]    In one example, the shift register comprises a cascade of a plurality of the shift register units. 
         [0024]    In another embodiment of the disclosure, there is further provided a display panel including said shift register as a gate driver of the display panel. 
         [0025]    In another embodiment of the disclosure, there is further provided a display including the display panel. 
       Effect of The Disclosure 
       [0026]    The disclosure may reduce a reset delay by designing a circuit, so that the output delay and attenuation of the shift register may be decreased. In the circuit of the disclosure, PU node has no direct affections to the resets of PD and PD_CN nodes, which reduces noise interference and enhances the operation stability of the shift register. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0027]      FIG. 1  is a circuit diagram of the shift register unit according to first embodiment of the disclosure; 
           [0028]      FIG. 2  is a operation timing diagram according to the first embodiment of the disclosure; 
           [0029]      FIG. 3  is a circuit diagram of the shift register unit according to second embodiment of the disclosure; 
           [0030]      FIG. 4  is a operation timing diagram according to the second embodiment of the disclosure; and 
           [0031]      FIG. 5  is a circuit diagram of the shift register unit according to third embodiment of the disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0032]    Below detailed implementations of the disclosure will be described in further details in connection with the accompanying drawings and embodiments. The following embodiments are only used to illustrate the disclosure, but not intend to limit the scope of the disclosure. 
       FIRST EMBODIMENT 
       [0033]    The shift register unit in the first embodiment of the disclosure includes: twelve transistors M 1 , M 2 , . . . , M 12  (all of them are P-channel transistors); one capacitor C 1 ; four signal input terminals INPUT, RESET, CLK (a clock signal), CLKB (an inversed signal of the clock signal CLK); one output terminal OUTPUT; and three power supply terminals VSS, VDD 1 , VDD 2 , wherein the VSS is always at a low level, the VDD 1  and VDD 2  are always at a high level, and voltages of the VDD 1  and VDD 2  may be same or different. Cascade refers to connecting a series of same unit elements end to end so as to form a new unit. The connection relationships among the respective elements and the respective input and output signals are as shown in the  FIG. 1 . 
         [0034]    A gate of the M 1  is connected to both the signal input terminal INPUT and gates of the M 6  and M 9 , a drain of the M 1  is connected to the power supply terminal VDD 1 , and a source of the M 1  is connected to drains of the M 2  and M 11 . A gate of the M 2  is connected to the signal input terminal RESET. Both a gate and a drain of the M 5  are connected to the signal input terminal CLKB, and a source of the M 5  is connected to drains of the M 6  and M 7 . A source of the M 8  is connected to the power supply terminal VDD 2 , a gate of the M 8  is connected to the source of the M 5 , a drain of the M 8  is connected to both drains of the M 9  and M 10  and gates of the M 11  and M 12 ; a drain of the M 3  is connected to the signal input terminal CLK, a gate of the M 3  is connected to one end of the capacitor C 1  and the source of the M 1 , and a source of the M 3  is connected to the other end of the capacitor C 1 , gates of the M 7  and M 10 , drains of the M 12  and M 4  and the signal output terminal OUTPUT; sources of M 2 , M 11 , M 6 , M 7 , M 9 , M 10 , M 12  and M 4  are connected to the power supply terminal VSS, and a gate of the M 4  is connected to the signal input terminal RESET. 
         [0035]    An operation timing (i.e., a control logic) designed for the circuit structure of the first embodiment is shown in the  FIG. 2 . Its operation principle may be divided into following five stages and will be described hereinafter. 
         [0036]    The first stage (I stage): the INPUT is at the high level, the transistors M 1 , M 6 , M 9  are turned-on, then a PU node is at the high level and the transistor M 3  is turned-on; CLKB is at the high level, the transistor M 5  is turned-on and the source of the M 5  is at the high level at this time, and the transistors M 11  and M 12  would be turned-off if a PD node is at a low level by setting the proportion between Ratio of Width to Length (w/l Ratio) of channel of M 5  and w/l Ratio of channel of M 6  and the proportion between w/l Ratio of channel of M 8  and w/l Ratio of channel of M 9 ; RESET is at the low level, so the transistors M 2  and M 4  are turned-off; the CLK is at the low level, therefore the output OUTPUT is at the low level and M 7  and M 10  are turned-off 
         [0037]    During this stage, the M 6  and M 9  are turned-on when the INPUT is at the high level, therefore delay hardly exists and the potential of the PD node is pulled down rapidly, so that charging at the PU node is not affected. In particular, in a case of low-temperature, mobility of TFT (particularly, M 1 , M 2 , M 11 , M 6 , M 7 , M 9  and M 10 ) is decreased, the affection to the PU node is more obvious, even the potential of the PD node would be pulled down insufficiently because of over-slowly charging, and finally the shift register could not operate normally. 
         [0038]    The second stage (II stage): the INPUT changes to the low level, and the transistors M 1 , M 6  and M 9  are turned-off, thus the PU node is still at the high level and the transistor M 3  is still turned-on; the CLKB is at the low level, the transistors M 5  and M 8  are turned-off, then the PD node is still at the low level and the transistors M 11  and M 12  are still turned-off; the RESET is still at the low level, then the transistors M 2  and M 4  are still turned-off; the CLK changes to the high level, therefore the output OUTPUT changes to the high level, and the M 7  and M 10  are turned-on. 
         [0039]    The third stage (III stage): the INPUT is still at the low level, and the transistors M 1 , M 6  and M 9  are still turned-off; the RESET changes to the high level, then the transistors M 2  and M 4  are turned-on; thus, the PU node is discharged to the low level, and the transistor M 3  is turned-off; the CLKB is at the high level, the transistors M 11  and M 8  are turned-on, then the PD node changes to the high level, and the transistors M 11  and M 12  are turned-on; the VSS is at the low level, therefore the output OUTPUT changes to the low level, and the M 7  and M 10  are turned-off. 
         [0040]    The fourth stage (IV stage): the INPUT is still at the low level, and the transistors M 1 , M 6  and M 9  are still turned-off; the RESET changes to the low level, then the transistors M 2  and M 4  are turned-off; the PU node is still at the low level, and the transistor M 3  is still turned-off; the CLKB is at the low level, the transistor M 5  is turned-off, then the PD node maintains the high level and the transistors M 11  and M 12  maintain to be turned-on; the VSS is at the low level, therefore the output OUTPUT remains the low level. 
         [0041]    The fifth stage (V stage): the INPUT is still at the low level, and the transistors M 1 , M 6  and M 9  are still turned-off; the RESET is still at the low level, then the transistors M 2  and M 4  are still turned-off; the PU node is still at the low level, and the transistor M 3  is still turned-off; the CLKB is at the high level, the transistor M 5  is turned-on, then the PD node maintains the high level and the transistors M 11  and M 12  maintain to be turned-on; the VSS is at the low level, therefore the output OUTPUT remains the low level. 
         [0042]    Thereafter, the states in the fourth and fifth stages are repeated until timings in the first, second and third stages appear again. Once the first, second and third stages are completed, one shift is realized. 
       SECOND EMBODIMENT 
       [0043]    In this approach, the direct current voltages VDD 1 , VDD 2  are removed from the shift register unit. Its connection manner is shown in  FIG. 3  and its connection relationships are as follows. Both a gate and a drain of the M 1  are connected to both the signal input terminal INPUT and gates of the M 6  and M 9 , and a source of the M 1  is connected to drains of the M 2  and M 11 . A gate of the M 2  is connected to the signal input terminal RESET. Both a gate and a drain of the M 5  are connected to the signal input terminal CLKB and a source of the M 8 , and a source of the M 5  is connected to drains of the M 6  and M 7 . A gate of the M 8  is connected to the source of the M 5 , a drain of the M 8  is connected to both drains of the M 9 , M 10  and gates of the M 11 , M 12 . A drain of the M 3  is connected to the signal input terminal CLK, a gate of the M 3  is connected to one end of the capacitor C 1  and the source of the M 1 , and a source of the M 3  is connected to the other end of the capacitor C 1 , gates of the M 7  and M 10 , drains of the M 12  and M 4  and the signal output terminal OUTPUT. Sources of M 2 , M 11 , M 6 , M 7 , M 9 , M 10 , M 12  and M 4  are connected to the power supply terminal VSS, and a gate of the M 4  is connected to the signal input terminal RESET. 
         [0044]    Herein, the VSS is always at the low level, and its driving timing is as shown in  FIG. 4 . The operation principle of this embodiment is essentially same as that of the first embodiment, but a main difference between them is in that the potential of the PD node would change by following the change of CLKB in the second embodiment, while this would not occur in the first embodiment. Since the VDD 2  is removed in this approach, which enables that the potential of the PD change as the CLKB changes, bias voltages for the M 11  and M 12  are decreased and the lifespan of the shift register is propitious to be prolonged. Furthermore, as compared with the approach in the first embodiment, the second embodiment has advantages of less signal lines and easy layout or wiring because the direct current voltages VDD 1 , VDD 2  are removed, however, the attenuations of the clock signal and the PU node are increased. 
       THIRD EMBODIMENT 
       [0045]    As shown in  FIG. 5 , only the direct current voltage VDD 2  is removed in this approach. A gate of the M 1  is connected to both the signal input terminal INPUT and gates of the M 6  and M 9 , a drain the M 1  is connected to the power supply terminal VDD 1 , and a source the M 1  is connected to drains of the M 2  and M 11 . A gate of the M 2  is connected to the signal input terminal RESET. Both a gate and a drain of the M 5  are connected to the signal input terminal CLKB and a source of the M 8 , and a source of the M 5  is connected to drains of the M 6  and M 7 . A gate of the M 8  is connected to the source of the M 5 , a drain of the M 8  is connected to both drains of the M 9  and M 10  and gates of the M 11  and M 12 . A drain of the M 3  is connected to the signal input terminal CLK, a gate of the M 3  is connected to one end of the capacitor C 1  and the source of the M 1 , and a source of the M 3  is connected to the other end of the capacitor C 1 , gates of the M 7  and M 10 , drains of the M 12  and M 4  and the signal output terminal OUTPUT. Sources of M 2 , M 11 , M 6 , M 7 , M 9 , M 10 , M 12  and M 4  are connected to the power supply terminal VSS, and a gate of the M 4  is connected to the signal input terminal RESET. 
         [0046]    Herein, the VSS is always at the low level, and its driving timing is still as shown in  FIG. 4 . The operation principle of this embodiment is essentially same as that in the first embodiment, but a main difference between them is in that the potential of the PD node would change accordingly when the CLKB changes in the third embodiment, while this would not occur in the first embodiment. The advantages and disadvantages of this approach are same as those in the second embodiment. The only difference from the second embodiment is in that the attenuation of the PU node is reduced but the signal lines are a litter more. 
       FOURTH EMBODIMENT 
       [0047]    This embodiment provides a shift register (which may comprises a plurality of shift register units, and may be formed by a cascade of the plurality of shift register units) including one or more shift register units as shown in  FIGS. 1 ,  3  and  5 . 
       FIFTH EMBODIMENT 
       [0048]    The disclosure further provides a display panel (for example, a liquid crystal display panel) including the above-described shift register (as a gate driver). 
       SIXTH EMBODIMENT 
       [0049]    The disclosure further provides a display (for example, a liquid crystal display) including the above-described display panel. 
         [0050]    The above embodiments are to be considered only illustrative, but not restrictive to the present disclosure, and it will be appreciated by those ordinary in the related art that various changes and modifications may be made in these embodiments without departing from the spirit and scope of the present disclosure. Therefore, any and all of equivalent solutions will fall into the scope of the present disclosure, which is defined in the appended claims.