Abstract:
An MOS compensation circuit for stabilizing the discharge of a timing capacitor including first and second inverter circuits and an interconnecting feedback circuit which effectively compensate for impedance variances in a capacitor-discharging MOS transistor, particularly those impedance variances due to fabrication tolerance dependent parameters.

Description:
BACKGROUND OF THE INVENTION 
     The subject invention relates to circuitry for stabilizing the operation of electrical devices and more particularly to a circuit for stabilizing the operation of MOS devices subject to wide process parameter variations. The invention provides a compensation circuit particularly suitable for stabilizing the RC time constant of an MOS capacitor discharge timing circuit. 
     Large scale integrated fabrication of MOS circuitry has been achieved in many areas of circuit fabrication, and increasing use and reduction of circuit size remain as goals. Associated with large scale production of MOS devices are tolerances which for many purposes can be accomodated. However, where accurate timing circuits are necessary, these tolerances lead to problems. Parameter variations from MOS device to MOS device on the same or different integrated circuit chips have stood in the way of fabricating pulse generators and other circuits requiring precise control of timing circuits without resorting to precision components external to the chip on which the MOS devices reside. 
     SUMMARY OF THE INVENTION 
     It is therefore, an object of the invention to improve circuitry for compensating for parameter variations is MOS devices. 
     It is another object of the invention to provide an improved timing circuit. 
     It is another object of the invention to eliminate the need for precision external components to assure timing precision in an integrated MOS timing circuit. 
     It is yet another object of the invention to construct a compensation circuit for stabilizing the discharge of a timing capacitor entirely from MOS devices. 
     These and other objects of the invention are accomplished by provision of a compensation circuit which detects an undesirable impedance change in an MOS device through which a timing capacitor discharges. The compensation circuit responds to the impedance change by generating a compensating voltage for application to the MOS device. The compensation circuit is constructed entirely of MOS devices, and no precision external components are required. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of the compensation circuit of the preferred embodiment of the invention . 
     FIG. 2 is a circuit schematic of a monostable circuit employing the compensated timing circuitry of the preferred embodiment of the invention. 
     FIG. 3 illustrates waveforms useful in discussing the operation of the circuit of FIG. 2 implemented with PMOS devices. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The preferred embodiment of the invention is illustrated in FIG. 1. The elements of the timing circuit of the preferred embodiment include a capacitor C 1  and a plurality of MOS devices Q 1 , Q 2 , Q 3 , Q 4 , Q 5 , Q 6 , Q 7 , and Q 8 . MOS devices Q 2 , Q 3 , Q 5 , Q 6 , and Q 7  are depletion devices as indicated by the plus sign (+), while MOS devices Q 1 , Q 4  and Q 8  are enhancement type devices. 
     Devices Q 1 , Q 2  and the capacitor C 1  comprise a typical prior art configuration for an RC discharge circuit. A control voltage V in  is applied to the gate (control electrode) 19 of the first MOS device Q 1 . A first non-control electrode 21 of the device Q 1  is connected to a reference voltage V cc . The other noncontrol electrode of the device Q 1  is connected at a junction 15 to one terminal 23 of the capacitor C 1  and to one non-control electrode of the second MOS device Q 2 . The other non-control electrode 25 of the second MOS device Q 2  is grounded. 
     In the prior art, the gate electrode 17 of the second MOS device Q 2  would be either connected to the point 15 or to the grounded electrode 25 depending on whether Q 2  was a depletion or enhancement device, respectively. When the capacitor C 1  is initially charged by an application of a gate voltage V in  to the first MOS device Q 1 , the necessary discharge current flows through the second MOS device Q 2 . In such case, the RC time to discharge the capacitor C 1  is primarily adversely affected by wide process parameter variations for the second MOS device Q 2 . 
     According to the preferred embodiment of the invention, however, the gate electrode of the second device Q 2  is connected to a compensation circuit 27. This compensation circuit 27 effectively controls the gate to source voltage of the MOS device Q 2 . The compensation circuit 27 includes two inverters, one formed by MOS devices Q 7  and Q 8  and the other by MOS devices Q 3  and Q 4 , as well as a feedback circuit formed by MOS devices Q 5  and Q 6 . 
     The first inverter circuit includes two MOS devices Q 7 , Q 8 . A respective non-control electrode of each of the MOS devices Q 7  and Q 8  is connected at a node 11 as is the gate 29 of the MOS device Q 7 . The second non-control electrode 30 of the MOS device Q 7  is connected to the source voltage V cc , while the second non-control electrode 31 of the MOS device Q 8  is grounded. 
     The second inverter circuit is similarly formed by two MOS devices Q 3 , Q 4 , with the gate 33 of the device Q 4  being connected to the reference voltage V cc . The gate 35 of the MOS device Q 8  in the first inverter circuit is connected at a node 13 where the gate 37 and one non-control electrode of the MOS device Q 3  join a non-control electrode of the MOS device Q 4 . One non-control electrode 39 of the MOS device Q 3  is connected to the reference voltage V cc , and one non-control electrode 32 of the MOS device Q 4  is grounded. 
     The feedback circuit includes two MOS devices Q 5 , Q 6 . The gate 41 and one non-control electrode of the MOS device Q 5  is connected to the node 13 in the second inverter circuit. The gate 43 and one non-control electrode of the MOS device Q 6  is connected to the first inverter circuit node 11. The remaining non-control electrodes of the two feedback circuit MOS devices Q 5  and Q 6  are connected together. 
     For accurate operation the transition time of the input voltage V in  is made much faster than the discharge rate through the MOS device Q 2 , and much greater than the threshold voltage V t  of the first MOS device Q 1 . Furthermore, the impedance Z ql  of the first MOS device Q 1  is made much less than the impedance Z q2  of the MOS device Q 2 . 
     In operation, the operating point for the inverter formed by the MOS devices Q 7  and Q 8  is stabilized against parameter variations by the negative feedback provided by the MOS devices Q 5  and Q 6 . If parameters vary to cause the capacitor C 1  to discharge more rapidly than desired, the gate voltage at the first inverter node 11 causes the impedance of the MOS device Q 2  to increase. For example, without the compensation circuit 27, if the parameter dependent voltage V td  of the MOS device Q 2  were to increase, the impedance Z q2  of the MOS device Q 2  would effectively drop, causing the capacitor C 1  to discharge rapidly. However, with the compensation circuit in place, when the parameter dependent voltage V td  increases, the voltage at the second inverter node 13 in the compensation circuit 27 will increase towards V cc , causing the inverted voltage at the first inverter node 11 to approach ground. As the second node voltage approaches ground, the impedance of the MOS device Z q2  effectively increases and compensation is achieved. 
     FIG. 2 illustrates the use of the compensation circuit 27 in a mono stable type pulse shaper. The input voltage V in  is inverted by an inverting amplifier 51 and supplied both to the MOS device Q 1  and the input 50 of a NAND gate 53. The timing capacitor C 2  has one terminal 23 connected to one non-control terminal 55 of an MOS device Q 9 . The other non-control terminal 57 of the MOS device Q 9  is connected to its gate terminal 59 and to a non-control terminal 61 of a second MOS device Q 10 . A third MOS device Q 11  has one non-control terminal 63 connected to the reference voltage V cc . The gate 65 of the third MOS device is connected via a noninverting amplifier 67 to the terminal 23 of the timing capacitor C 1 . The other non-control electrode 69 of the third MOS device Q 11  is connected to a non-control electrode 71 of a fourth MOS device Q 12  and to an input 52 to the NAND gate 53. The gates 73, 75 of the second and fourth MOS devices Q 10 , Q 12  are cross-coupled to their respective ungrounded non-control terminals. The second respective noncontrol terminals 77, 79 of the second and fourth MOS devices Q 10 , Q 12  are grounded. 
     The operation of the pulse shaper of FIG. 2 is illustrated by the timing diagrams of FIG. 3. Prior to time equals zero, t=0, the logical &#34;zero&#34; level of the input voltage pulse V in  to the terminal of the input inverting amplifier 51 is inverted by that amplifier 51 and applied to the MOS device Q 1  and to one input of NOR gate 53. The output V out  of NOR gate 53 is forced to the logical &#34;zero&#34; level. Also the MOS device Q 1  is turned on, thereby connecting the timing capacitor C 1  to the reference source V cc . The timing capacitor voltage V c  then begins to charge via the MOS device Q 1 , its time constant being determined by the impedance of the device Q 1  and the capacitance of the timing capacitor C 1 . When the capacitor C 1  has charged, the inverting amplifier 67 turns off the third MOS device Q 11  in the pulse shaper circuit. The voltage V Q  on the terminal 52 then steps to the logical &#34; zero&#34; level. At t=0 when the initial pulse V in  fed to the NOR gate 53 from the output of the first inverting amplifier 51 goes from the logical &#34;zero&#34; to the logical &#34;one&#34; state, both inputs to the NOR gate 53 are logical &#34;zeros&#34; and the output voltage V out  of the NOR gate 53 drops to the logical &#34;one&#34; state. The capacitor C 1  begins a controlled discharge through MOS device Q 2 , its time constant being determined by the device Q 2  and the capacitance of the timing capacitor C 1 . When the capacitor voltage V c  has discharged, the voltage V Q  on the input 52 to the NOR gate 53 is a logical &#34;ONE&#34; and the output V out  of the NOR gate 53 steps up, terminating the output pulse. The output voltage V out  constitutes the desired timing pulse. 
     From the above discussion, it should be apparent that numerous modifications and adaptations may be made in the preferred embodiment without departing from the scope and spirit of the invention. It is therefore to be understood that, within the scope of the appended claims, the invention may be practiced other than as specifically described herein.