Abstract:
A high side isolated gate drive controller circuit is presented with an on-time limiting circuit to prevent isolation transformer saturation as well as a universal power up circuit adaptable to power the driver with constant voltage for different input voltage levels.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority to and the benefit of Chinese patent application No. 201010261079.5, filed Jul. 5, 2010, the entirety of which is hereby incorporated by reference. 
     BACKGROUND OF THE DISCLOSURE 
     Driver control circuits are often used to actuate power switching devices, such as MOSFETs, IGBTs, etc., in switching power supplies for lighting systems and other power conversion applications, while isolating the switching control circuitry from the high voltages of the power conversion circuits. Many conventional gate drive controller circuits, however, suffer from poor performance and inability to reliably provide drive voltages sufficient to actuate the power MOSFET at high duty cycles, and certain approaches to solve this problem suffer from driver isolation transformer core saturation. 
       FIG. 1A  shows portions of a power converter in which a buck-boost DC-DC converter circuit  300  has one or more power switches driven by isolated driver circuitry. In this system, the converter includes a buck converter stage  310  followed by a boost converter  320 . The buck converter  310  receives a DC input at input terminals Vin+ and Vin−, and includes a MOSFET Q 1  with a drain connected to Vin+ and a source connected to the high side input of the boost converter  320 , as well as a diode D 2  connected across the bock converter output lines. The boost converter  320  has a series inductor L connected to the upper input and a second MOSFET Q 2  connected between the inductor L and the lower terminal, as well as a diode D 3  connected from the common node of the inductor L and Q 2  to an upper output Vout, with a pair of series output capacitors C 2  and C 3  connected between Vout and the lower terminal. 
     The conventional high side drive controller circuit  100   a  in  FIG. 1A  is used to drive the gate-source voltage Vgs of Q 1  for operation of the buck stage  310 . The controller  100   a  receives power (Vcc) from a power up circuit  200   a  and includes a transformer T 1  for isolating the driver switching controls not shown) from the potentially high voltages of the buck-boost converter  300 . A PWM controller  110  selectively provides a square wave to drive the transformer primary circuit including a transformer primary, a DC blocking capacitor C 1 , and a resistance R 1  with a square wave signal. The PWM signal from the controller component  110  is coupled to the transformer primary through a resistor R 1  and a series capacitor C 1 , and the transformer secondary provides isolated AC power to a rectifier circuit including a diode D 1  and resistor Rgs to selectively provide a gate control signal (Vgs) as a voltage between gate and source terminals of the transistor Q 1  in the buck converter  310 . The illustrated controller  100   a , however, suffers from inability to provide the necessary gate drive voltage at high PWM duty cycle levels, and thus may not be able to reliable switch the MOSFET Q 1  on. 
       FIG. 1B  shows another conventional driver circuit  100   b  with a DC blocking capacitor C 2  added to the upper secondary circuit node to address the voltage sufficiency issues with the design of  FIG. 1A  for high duty cycle conditions. Although this approach is an improvement in steady state operation, if the PWM controller  110  stays on too long or shuts off, the driver circuit transformer T 1  can become saturated, leading to the charge from the secondary capacitor C 2  inadvertently turning on the MOSFET Q 1 . In particular, some PWM controllers such as the L6562 will keep the output at a high level all the time if the circuit output is lower than a setpoint voltage. If the drive circuit as shown in  FIG. 1B  is used to drive Q 1  as shown in  FIG. 1A , then after several micro seconds the gate drive transformer T 1  will become saturated, Q 1  will turn off and the input cannot transfer energy to the load. This, in turn, may lead to the Vcc of an L6562 controller  110  falling, with the PWM controller  110  stopping. With the PWM controller  110  off, the primary side DC blocking capacitor C 1  will transfer the energy to the secondary side, resulting in Q 1  being turned on, which can cause Q 1  to fail. Another potential problem in the circuit  100   b  of FIG.  1 B is if the capacitance of C 1  is large and the transformer is not saturated, the DC blocking capacitor C 2  of the secondary circuit may discharge slowly when controller  110  shuts off, which may lead to the FET Q 1  turning on. 
       FIG. 1C  shows a further conventional driver design  100   c  in which a secondary-side MOSFET Q 0  has been added to the lower secondary circuit branch, with a control gate tied to the upper secondary winding. This design uses the transistor Q 0  to control transformer saturation, as described in U.S. Pat. No. 6,807,071, incorporated herein by reference. However, this approach introduces an additional MOSFET component and thus increases the circuit size and cost. 
     As shown in  FIG. 1A , the PWM controller  110  receives power (Vcc) from the power up circuit  200   a . In the case of  FIG. 1A , a charge-pump type power up circuit  200   a  with transformer T 2  is used to generate Vcc, but this circuit suffers from poor output stability for load changes and/or where different AC input voltages are received from the AC input source  210 . 
       FIG. 1D  is a partial schematic diagram illustrating a full wave rectifier power up circuit  200   b  that can be used, but this design also fails to provide steady supply voltages Vcc to the controller  110  and other integrated circuits as input supply levels and/or output loading conditions change. 
     Thus, there remains a need for improved gate driver circuits and power up circuits to provide switching control circuit isolation from driven switching devices while mitigating isolation transformer core saturation. 
     SUMMARY OF THE DISCLOSURE 
     A drive controller circuit is provided for driving a control terminal of a transistor, which includes first and second driver outputs for connection to the terminals of a transistor being driven, as well as a driver transformer having primary and secondary windings wound on a core, with one end of the secondary winding coupled with a second driver output. The driver circuit also includes a pulse width modulation (PWM) driver with a control input and a PWM output, along with a first capacitor coupled between a first end of the primary winding and the PWM output, a second capacitor coupled between the first end of the secondary winding and the first driver output, and a rectifier is coupled between the first and second driver outputs. A limiting circuit is provided, which includes a limiting circuit input coupled with the PWM output, and a limiting control output coupled with the PWM controller, where the limiting control output provides a limiting control signal to the PWM controller to limit the on-time of the PWM output at or below an on-time threshold value. In certain embodiments, the on-time threshold value is set to avoid saturation of the core of the driver transformer. 
     The limiting circuit in certain embodiments includes a resistor coupled between the limiting circuit input and an intermediate node, a limiting circuit capacitance coupled between the intermediate node and a circuit ground, and a limiting circuit diode comprising an anode coupled with the intermediate node and a cathode coupled with the limiting control output. In various embodiments, the second resistor and the limiting circuit capacitance set a time constant of the limiting circuit which determines a rise time of a voltage of the intermediate node to rise to a voltage threshold when the PWM output is activated, and the rise time of the intermediate node voltage determines the on-time threshold value. 
     A power up circuit is provided for powering a PWM controller, which has an input coupleable to an AC input source, and a transformer with a primary coupled to the input to receive AC input power as well as first and second secondary windings. The first secondary winding has a first end coupled to a first power up circuit rectifier and a second end coupled to a circuit ground, and the second secondary winding a first end coupled with the circuit ground and a second end coupled to a second power up circuit rectifier. A power up circuit output is coupled with the first and second rectifiers and provides a generally constant output voltage to power a PWM controller circuit independent of a voltage of the AC input power. 
     In certain embodiments, the first rectifier has an anode coupled to the first end of the first secondary winding and the second rectifier has an anode coupled to the second end of the second secondary and a cathode coupled to the output. The power up circuit in these embodiments also includes a resistance between the cathode of the first rectifier and an intermediate power up circuit node, along with a zener with an anode coupled to the circuit ground and a cathode coupled to the intermediate node. The circuit further includes a transistor with a first terminal coupled to the output, a second terminal coupled to the first rectifier, and a control terminal coupled to the intermediate node, where the voltage between the control terminal and the first terminal determines the transistor impedance between the first and second transistor terminals. The transistor thus selectively connects the first rectifier with the output when the output voltage is less than the zener voltage of the zener diode and disconnects the first rectifier from the output when the output voltage is greater than the zener voltage. 
     The power up circuit in certain embodiments also includes an output capacitance coupled between the output and the circuit ground and a second zener diode comprising an anode coupled to the circuit ground, and a cathode coupled to the output. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       One or more exemplary embodiments are set forth in the following detailed description and the drawings, in which: 
         FIG. 1A  is a schematic diagram illustrating portions of a conventional power conversion system with a charge-pump power up circuit and a high side gate driver circuit; 
         FIG. 1B  is a partial schematic diagram illustrating another conventional driver circuit with an added secondary capacitor; 
         FIG. 1C  is a partial schematic diagram illustrating a further conventional driver circuit with an added secondary circuit transistor to control transformer saturation; 
         FIG. 1D  is a partial schematic diagram illustrating conventional full wave rectifier power up circuit; 
         FIG. 2  is a schematic diagram illustrating portions of a power converter with an exemplary universal power up circuit and an exemplary drive controller circuit with a limiting circuit to mitigate transformer saturation; 
         FIG. 2A  is a partial schematic diagram illustrating another exemplary limiting circuit to mitigate transformer saturation in the drive controller circuit of  FIG. 2 ; 
         FIGS. 2B and 2C  are schematic diagrams illustrating portions of a power converter with further exemplary drive controller circuits including a limiting circuit and an impedance network for discharging a secondary-side DC blocking capacitor; 
         FIG. 3  is a side elevation view showing an exemplary transformer core with primary and secondary windings in the driver circuit of  FIG. 2 ; and 
         FIG. 4  is a graph illustrating operation of the on-time limiting circuit in the driver of  FIG. 2 . 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring now to  FIGS. 2-4 ,  FIG. 2  illustrates portions of a power converter system with an exemplary universal power up circuit  600  and an exemplary driver  500  with a limiting circuit  520  to mitigate transformer saturation. The driver circuit  500  is connected to the above described buck-boost converter  300  to drive the gate G of a power conversion transistor Q 1  by providing the gate-source voltage Vgs via a first driver output  541  operative to selectively provide a drive signal to the gate terminal G and a second driver output  542  coupled with the source terminal S of Q 1 . 
     The driver circuit  500  includes a driver transformer T 51  with a primary winding P 51  and a secondary winding S 51  wound on a core TC 51  (core and windings shown in  FIG. 4 ). A PWM controller  510 , such as an L6562 in certain embodiments, receives its power (Vcc) via a power connection  518  from the power up circuit  600 . The driver circuit  500  provides a pulse width modulated gate drive signal at a PWM output  517  to a primary circuit including a first capacitor C 51  coupled between a first end  531  of the primary winding P 51  and the PWM output  517 , with a second primary end  532  and a ground input  516  of the PWM controller  510  connected to a circuit ground. The PWM controller  510  generates the output  517  according to a control signal  112  received from a control circuit (not shown), and includes a control input  511  operative to selectively turn off or disable the PWM output  517 . 
     The secondary winding S 51  has a first end  533  and a second end  534  coupled with the second driver output  542 . A second capacitor C 52  is coupled between the first end  533  of the secondary winding S 51  and the first driver output  541 , with a first rectifier D 51  and a capacitor C 53  coupled between the first and second driver outputs  541  and  542 . 
     The driver circuit  500  also includes a limiting circuit  520  with an input  521  coupled with the PWM output  517 , and a limiting control output  522  coupled with the control input  511  of the PWM controller  510 . In operation, the limiting control output  522  provides a limiting control signal to the control input  511  to limit the on-time of the PWM output  517  to be at or below an on-time threshold value Tonmax. This operation is shown in  FIG. 4  in which the pulse width modulated driver output  517  stays active at most for Tonmax. 
     In certain embodiments, the on-time threshold value Tonmax is set to avoid saturation of the core TC 51  of the driver transformer T 51 . The on-time limiting operation can be achieved by any suitable on-time limiting circuitry. In the example of  FIG. 2 , the limiting circuit input  521  includes a resistor R 52  coupled between the limiting circuit input  521  and an intermediate node  523 , as well as a capacitance C 54  coupled between the intermediate node  523  and circuit ground and a diode D 52  with an anode coupled with the intermediate node  523  and a cathode coupled with the limiting control output  522 . In addition, the illustrated embodiment includes a second series circuit branch between the input  521  and the intermediate node  523 , including a diode D 53  and resistor R 51 . The resistor R 52  and the capacitor C 54  establish a time constant of the limiting circuit  520 . This time constant determines the rise time of the voltage V C54  across the capacitor C 54  (e.g., the rise time of the intermediate node voltage. This rise time sets the time it takes for the voltage V C54  at the intermediate node  523  to rise to a threshold voltage value Vth (e.g., 2.5 volts in one embodiment) as shown in  FIG. 4 . When this occurs, D 52  turns on and activates the limiting circuit output  522  to cause the PWM output  517  to be deactivated. In this manner, the rise time of the voltage V C54  of the intermediate node  523  of the limiting circuit  520  determines the on-time threshold value Tonmax (e.g., 30 us in one embodiment). The limiting circuit  520  thus operates to mitigate or prevent transformer saturation in the driver circuit  500  without requiring the addition of an extra MOSFET switch as was the case in the circuit of  FIG. 1C  above. 
       FIG. 2A  shows another exemplary limiting circuit  320  similar in most respects to the above-describe limiting circuit in  FIG. 2 , except that the resistor R 52  is connected to an intermediate node between the resistor R 51  and the cathode of D 53  instead of the input  521 . 
     As also shown in  FIG. 2 , the power up circuit  600  provides power (Vcc) to the PWM controller  510 , and provides a steady Vcc voltage level even in the presence of changing output loading conditions and for different AC input voltages. The power up circuit  600  includes an input  602  for receiving input power from an AC input source  210 , where the input terminals are connected to a primary winding P of a power up circuit transformer T 61 . The transformer T 61  has a first secondary winding S 1  with a first end  611  coupled to a first power up circuit rectifier D 61  as well as a second end  612  coupled to the circuit ground. In addition, the transformer T 61  has another secondary S 2  with a first end  621  coupled with the circuit ground and a second end  612  coupled to a second power up circuit rectifier D 62 . An output  630  is coupled with the first and second power up circuit rectifiers D 61  and D 62  and provides a generally constant output voltage Vcc to the power input  518  of the PWM controller  510  independent of a voltage of the AC input source  210 . Any suitable dual rectifier circuit can be used to provide the universal input functionality. 
     In the illustrated example, the anode of rectifier D 61  is coupled to the first end  611  of the first secondary winding S 1 , and the second rectifier D 62  has an anode coupled to the second end  622  of S 2  and a cathode coupled to the output  630 . The circuit  600  further includes a resistance R 61  coupled between the cathode of D 61  and an intermediate node  631 , and a first zener diode Z 61  having an anode coupled to circuit ground and a cathode coupled to node  631 . 
     A transistor Q 64  has a source coupled to the output  630  and drain coupled to the first rectifier D 61 . The gate of Q 4  is coupled to the intermediate node  631  with the gate-source voltage Vgs of Q 4  setting the on/off state of the source-drain path of Q 4 . In this manner, the switching state of Q 4  is used to selectively connect the first rectifier D 61  with the output  630  when the output voltage Vcc at the output  630  is less than the zener voltage of Z 61  (e.g., 15 volts in one example) and to selectively disconnect D 61  from the output  630  when Vcc is greater than the zener voltage of Z 61 . This embodiment of the power up circuit  600  in  FIG. 2  also includes an output capacitance Co coupled between the output  630  and the circuit ground, as well as a second zener diode Z 62  with an anode coupled to the circuit ground and a cathode coupled to the output  630 . 
       FIG. 2B  shows another power converter embodiment with a drive controller circuit  500   a  having a limiting circuit and an impedance network  550  comprising one or more resistances, capacitances, inductances, and/or semiconductor-based impedances (variable or fixed) forming a DC blocking capacitor discharging circuit. In  FIG. 2B , the impedance network  550  is coupled across the DC blocking capacitor C 52  (between the driver output  541  and the first end  533  of the secondary winding S 51  of transformer T 51 ), along with a resistance Rgs across the driver outputs  541  and  542 .  FIG. 2C  illustrates another example in which a drive controller circuit  500   b  includes such an impedance network  550  coupled between the driver outputs  541  and  542 . As noted with respect to the circuit of  FIG. 1B  above, if the capacitance of the secondary-side DC blocking capacitor C 52  in  FIG. 2 ,  2 B, or  2 C is large and the transformer T 51  is not saturated, the DC blocking capacitor C 52  may discharge slowly when controller  510  shuts off, leading to the FET Q 1  turning on. To address this DC blocking capacitor discharge problem, the impedance network  550  is used to accelerate the discharging time of C 52  to avoid or mitigate inadvertent triggering of the transistor Q 1  when the PWM controller IC  510  shuts off. 
     The above examples are merely illustrative of several possible embodiments of various aspects of the present disclosure, wherein equivalent alterations and/or modifications will occur to others skilled in the art upon reading and understanding this specification and the annexed drawings. In particular regard to the various functions performed by the above described components (assemblies, devices, systems, circuits, and the like), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component, such as hardware, software, or combinations thereof, which performs the specified function of the described component (i.e., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the illustrated implementations of the disclosure. In addition, although a particular feature of the disclosure may have been illustrated and/or described with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, references to singular components or items are intended, unless otherwise specified, to encompass two or more such components or items. Also, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in the detailed description and/or in the claims, such terms are intended to be inclusive in a manner similar to the term “comprising”. The invention has been described with reference to the preferred embodiments. Modifications and alterations will occur to others upon reading and understanding the preceding detailed description. It is intended that the invention be construed as including all such modifications and alterations.