Abstract:
Methods and systems for fully differential frequency doubling include receiving a differential input signal having a first frequency, generating a non-inverted or positive output signal having twice the frequency of the input signal, and generating an inverted or negative version of the positive output signal. The positive and negative output signals form a fully differential output. The duty ratio of the output signals substantially matches a duty ratio of the input signals. Fully differential frequency doubling can be implemented with NMOS and/or PMOS devices. The invention further provides optional circuitry for increasing an output signal level.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention is directed to frequency doubling and, more particularly, to fully differential frequency doubling. 
   2. Related Art 
   Conventional frequency doublers suffer from relatively poor power supply rejection ratios (“PSRR”). Conventional frequency doublers also typically output non-50% duty ratios. 
   What are needed are improved methods and systems for frequency doubling. 
   SUMMARY OF THE INVENTION 
   The present invention is directed to fully differential (i.e., double-ended output) frequency doubling. Fully differential circuits in accordance with the invention provide, among other features, improved PSRR, as compared to non-differential circuits, and improved duty ratios. 
   The invention includes receiving a differential input signal having a first frequency, generating a non-inverted or positive output signal having twice the frequency of the input signal, and generating an inverted or negative version of the positive output signal. The positive and negative output signals form a fully differential output. 
   The duty ratio of the output signals substantially matches a duty ratio of the input signals. For example, when the input differential signal has a 50% duty ratio, the output differential signal will have a 50% duty ratio. The duty ratio is defined herein as the ‘on’ time over the ‘period.’ Thus, a sine wave should have a 50% duty ratio. 
   Optional processes include DC biasing the differential current signal. The invention is implemented with NMOS and/or PMOS devices. The invention further provides optional circuitry for increasing an output amplitude level. 
   Additional features and advantages of the invention will be set forth in the description that follows. Yet further features and advantages will be apparent to a person skilled in the art based on the description set forth herein or may be learned by practice of the invention. The advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings. 
   It is to be understood that both the foregoing summary and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES 
     The present invention will be described with reference to the accompanying drawings, wherein like reference numbers indicate identical or functionally similar elements. Also, the leftmost digit(s) of the reference numbers identify the drawings in which the associated elements are first introduced. 
       FIG. 1  is a high-level block diagram of a differential frequency doubler  100 . 
       FIG. 2  is an example block diagram of the frequency doubler  100 , including a differential frequency doubler module  202 , a phase reversal module  204 , and a DC bias module  206 . 
       FIG. 3  is an example circuit diagram of the frequency doubler  100  implemented with NMOS devices. 
       FIG. 4  is a timing diagram for the frequency doubler  100  illustrated in  FIG. 3 . 
       FIG. 5  is an example circuit diagram of the frequency doubler  100  implemented with PMOS devices. 
       FIG. 6  is an example circuit diagram of the frequency doubler  100  implemented with NMOS devices, wherein the phase reversal module  204  includes additional circuitry that allows the frequency doubler  100  to provide a greater output current I output    108 , for a given (W/L) ratio, as compared to the examples of  FIG. 3  and  FIG. 5 . 
       FIG. 7  is an example circuit diagram of the frequency doubler  100  implemented with PMOS devices, wherein the phase reversal module  204  includes additional circuitry that allows the frequency doubler  100  to provide a greater output current I output    108 , for a given (W/L) ratio, as compared to the example of  FIG. 5 . 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The present invention is directed to improved methods and systems for frequency doubling. More particularly, the present invention is directed to improved methods and systems for fully differential (i.e., double-ended output) frequency doubling. 
     FIG. 1  is a high-level block diagram of a double-ended-output differential frequency doubler (“frequency doubler”)  100  in accordance with the invention. The frequency doubler  100  receives a differential input signal V input    102 , having a frequency f. V input    102  includes a positive non-inverted signal V ip    104  and a negative or inverted signal V in    106 . The frequency doubler  100  outputs a fully differential output signal I output    108 , having a frequency 2f. I output    108  includes a positive or non-inverted signal I op    110  and a negative or inverted signal I on    112 . 
   In the example of  FIG. 1 , the output of frequency doubler  100  (i.e., I output    108 ) is illustrated as a current output. The current output can be converted into a voltage output of a desired amplitude range. 
     FIG. 2  is an example block diagram of the frequency doubler  100 , wherein the frequency doubler  100  includes a differential frequency doubler module  202 , a phase reversal module  204 , and a DC bias module  206 . 
   The differential frequency doubler module  202  receives V input    102  with frequency f and generates (AC) current signal I op    110 , having frequency 2f. In  FIG. 2 , the current signal I op    110  is also illustrated as I A . 
   The DC bias module  206  provides DC biasing to the current signal I op    110 . The DC bias module  206  is a relatively high impedance module, or ideally infinite impedance, which substantially prevents the (AC) current signal I op    110  from passing through the DC bias module  206 . The current signal I op    110  is thus forced to flow to phase reversal module  204 . 
   The phase reversal module  204  generates a signal I on    112  that is substantially equal in amplitude to the signal I op    110 , but opposite in phase. As a result, the duty ratio of the output signals I op    110  and I on    112  are substantially 50%, provided that the input signal is also 50% duty ratio. The duty ratio is defined herein as the ‘on’ time over the ‘period.’ Thus, a sine wave should have a 50% duty ratio. In  FIG. 2 , the current signal I on    112  is also illustrated as I B . 
   The frequency doubler module  202 , the phase reversal module  204 , and the DC bias module  206  can be implemented in a variety of ways. Example embodiments of the differential frequency doubler module  202 , the phase reversal module  204 , and the DC bias module  206  are provided below. The invention is not, however, limited to the example embodiments provided herein. Based on the disclosure herein, one skilled in the relevant art(s) will understand that the differential frequency doubler module  202 , the phase reversal module  204 , and/or the DC bias module  206  can be implemented in other embodiments as well. Such other embodiments are within the spirit and scope of the present invention. 
     FIG. 3  is an example circuit diagram of the frequency doubler  100 . In the example of  FIG. 3 , the frequency doubler module  202  includes transistors  302  and  304 , also identified as M 1  and M 2 , respectively. V ip    104  and V in    106  control gates of the transistors M 1  and M 2 , respectively. The phase reversal module  204  includes a transistor  306 , also illustrated as M 3 , having a gate controlled by a common mode voltage V CM =(Vip+Vin)/2. The DC bias module  206  is illustrated as a DC current source  308 . Operation of the differential frequency doubler  100  of  FIG. 3  is described below in conjunction with  FIG. 4 . 
     FIG. 4  is a timing diagram for the frequency doubler  100  illustrated in  FIG. 3 . Operation of the frequency doubler  100  illustrated in  FIG. 3  is now described with reference to the timing diagram of  FIG. 4 . 
   In  FIG. 3 , the current I op    110  includes a current I 1  through M 1 , and a current I 2  through M 2 . Generally, as V ip    104  rises, M 1  increasingly turns on, which increases the current I 1  through M 1 . At the same time, V in    106  falls, which increasingly turns off M 2 , which decreases the current I 2  through M 2 . Similarly, as V ip    104  falls and V in    106  rises, M 1  increasingly turns off and M 2  increasingly turns on, which respectively decreases the current I 1  through M 1  and increases the current I 2  through M 2 . 
   Due to the square law nature of CMOS transistors, the current I 1  through M 1 , and I 2  through M 2 , are directly proportional to the square of their respective input gate voltages. The square behavior of the transistors will cause an exponential output current. The current through the transistors M 1  and M 2  is always positive, without regard to the polarity of their respective input gate voltages. In other words, the current through M 1  is always flowing from the drain to the source, or in one direction only. The same applies to the current I 2  in M 2 . Combining I 1  and I 2  provides a frequency of 2 times the frequency of the input voltage, as described qualitatively below. 
   More specifically, and with reference to  FIG. 4 , at time T 1 , V ip    104  is at a maximum and V in    106  is at a minimum. Therefore, currents I 1  and I 2  are at maximum and minimum respectively due to the squaring of V ip    104  and V in    106 . Combing I 1  and I 2  should cause I op    110  at a maximum due to the exponential effect of the transistors. 
   At time T 2 , V ip    104  and V in    106  approach a midway point between the maximum and minimum amplitudes, also referred to as the AC common-mode point. At this time, I 1  and I 2  are at minimum amplitudes and I op    110  falls to a minimum. 
   At time T 3 , when V ip    104  is at a minimum and V in    106  is at a maximum, I op    110  is again at a maximum because of the squaring of V ip    104  and V in    106 . 
   At time T 4 , as V in    106  and V ip    104  approach the AC common-mode point, I op    110  falls to its minimum. Thus, I op    110  has a frequency that is double the frequency of V ip    104  and V in    106 . Since I op    110  flow to M 3  because of the high impedance (resistance) of the DC bias module  206 , I on    112  is substantially equal to I op    110  in amplitude, but inverted with respect to I op    110 . 
   As noted above, the currents I 1  and I 2  form the current I op    110 . In order for transistor M 3  to carry the combined currents I 1  and I 2 , M 3  is fabricated with a width/length ratio (W/L) that is approximately twice that of the transistors M 1  and M 2 . Since the gate voltage of M 3  is biased by a fixed voltage, V CM , I on    112  is generated by varying V s , the source voltage of M 3 . 
   Advantages of the frequency doubler  100  of  FIG. 3  include fully differential outputs and thus improved power supply rejection ratios (“PSRR”), as compared to conventional frequency doublers. 
   The quantitative relationship between V input    102  and I output    108  for the example of  FIG. 3  can be derived using current equations and is determined as follows: 
           I   1     =         K   *     ⁡     (       V   1     -     V   X       )       2       ;       where   ⁢           ⁢     V   X       =       V   S     +     V   TH         ;       
           I   2     =         K   *     ⁡     (       V   2     -     V   X       )       2       ;       
               I   B     =       2   ⁢         K   *     ⁡     (       V   CM     -     V   X       )       2       =     2   ⁢         K   *     ⁡     [         (       V   1     +     V   2       )     /   2     -     V   X       ]       2                     =     2   ⁢       K   *     ⁡     [         (       V   1   2     +     2   ⁢     V   1     ⁢     V   2       +     V   2   2       )     /   4     -       V   1     ⁢     V   X       -       V   2     ⁢     V   X       +     V   X   2       ]                     =       K   *     ⁡     [         (       V   1   2     +     2   ⁢     V   1     ⁢     V   2       +     V   2   2       )     /   2     -     2   ⁢     V   1     ⁢     V   X       -     2   ⁢     V   2     ⁢     V   X       +     2   ⁢     V   X   2         ]                 
               I   A     =       ⁢         I   1     +     I   2       =           K   *     ⁡     (       V   1     -     V   X       )       2     +         K   *     ⁡     (       V   2     -     V   X       )       2                     =       ⁢       K   *     ⁡     (       V   1   2     -     2   ⁢     V   1     ⁢     V   X       +     V   X   2     +     V   2   2     -     2   ⁢     V   2     ⁢     V   X       +     V   X   2       )                   =       ⁢       K   *     ⁡     (       V   1   2     +     V   2   2     -     2   ⁢     V   1     ⁢     V   X       -     2   ⁢     V   2     ⁢     V   X       +     2   ⁢     V   X   2         )                 
               I   OUT     =       ⁢       I   A     -     I   B                   =       ⁢       K   *     ⁡     (         V   1   2     /   2     +       V   2   2     /   2     -       V   1     ⁢     V   2         )                   =       ⁢       K   /     2   *       ⁢       (       V   1     -     V   2       )     2                 
         I   OUT     =       K   *     ⁢     1   /     2   *       ⁢     V   IN   2           
 
   Where V s  is the source voltage of transistors, and V TH  is the threshold voltage. K is a device parameter and is proportional to W/L. Note I B =2*K because the W/L ratio of M 3  is 2 times of M 1  (and M 2 ). Equation for I 1  (or I 2 ) is a fundamental equation of MOS transistors.
 
Thus,  I   output   =KV   in   2 /2  Eqs. (1)
 
   The derivation above assumes that the transistors M 1 , M 2 , and M 3  generally operate in saturation.
 
Let V IN =sin(f)
 
 I   OUT   =K* ½*sin 2 (f)= K * ½*(½*(1−cos (2f)))
 
   The output current I OUT  will have a DC component and an AC component with a frequency of 2f. The DC component can be removed through a high-pass filter. 
   In the example of  FIG. 3 , the frequency doubler  100  is implemented with NMOS transistors. Alternatively, and/or additionally, the frequency doubler  100  is implemented with PMOS transistors, as illustrated in  FIG. 5 . Operation of the PMOS frequency doubler  100  illustrated in  FIG. 5  is substantially similar to the NMOS frequency doubler  100  illustrated in  FIG. 3 , with the exception that the PMOS transistors M 1 , M 2 , and M 3  in  FIG. 5  turn on as the voltage at their respective gate terminals decrease. 
   In the example above, I on    112  is generated by M 3  by fixing its gate voltage and varying its source voltage. Alternatively, I on    112  is generated by M 3  by fixing its source voltage and varying its gate voltage. For example,  FIG. 6  is an example circuit diagram of the frequency doubler  100  implemented with NMOS devices, wherein the phase reversal module  204  includes an operational or differential amplifier  602  and a fourth transistor  604 , also identified as M 4 . Operation of these devices is described below. Generation of I on  by either of the methods described herein is useful on its own, as well as in a frequency doubler. 
   As with the example of  FIG. 3 , the frequency doubler  100  illustrated in  FIG. 6  provides fully differential current output I output    108 . The frequency doubler  100  illustrated in  FIG. 6  also provides improved PSRR as compared to conventional frequency doublers. 
   In the examples of  FIG. 3  and  FIG. 6 , the bias module  206  includes a DC bias current  308 , approximately equal to 4 times of I.sub.BIAS, which is the bias current for M 4 . In the example of  FIG. 6 , the phase reversal module  204  includes a DC bias current  606 , also illustrated as I.sub.BIAS (i.e., 1/4  of the DC bias current  308 ). Also in  FIG. 6 , M 4  has a W/L ratio substantially similar to the W/L ratios of M 1  and M 2 . 
   The purpose of the operational amplifier  602  in a feedback loop is to copy the voltage at the positive input terminal  603  to that of the negative input terminal  605 . The source voltage, V s , of M 4  is thus copied to that of M 1 , M 2 , and M 3 . Since current source  308  is 4 times of current in current source  606 , and the combined W/L ratio of M 1 , M 2  and M 3  is 4 times of M 4 , the current density of each branch, I 1 , I 2  and I 3  (I B ) is equal to that of I 4  (M 4  current). Since M 4  is biased by V CM  ((Vip+Vin)/2) while M 1  and M 2  is also centered at V CM , the gate voltage of M 3  is centered (dc biased) to V CM  due to the same current density of M 4 . 
   Note that V s  of M 4  is a an AC ground node. Because of the feedback configuration of the operational amplifier  602 , V s , of M 3  is an AC ground node. An AC ground node is defined as a node in which the node voltage is unchanged, or cannot be affected by AC voltage. Since I A  needs to travel to M 3  and the source voltage of M 3  is ac-grounded, the gate voltage of M 3  has to vary in order to generate I B . In  FIG. 3 , note that the gate voltage of M 3  is biased by V CM . Since V CM  is a fixed voltage, the source voltage node of M 3  needs to vary instead. 
   Ideally, the DC bias current source  308  has an infinite output impedance (resistance). However, in practical realization, the output impedance is finite. If the output impedance of the DC bias current source  308  is comparable to the input impedance of M 3  (impedance looking into the source), signal current I A  will not fully flow into M 3  and instead, will partially flow into the DC bias current source  308  and create undesired phase shift and signal lost in amplitude. This is improved by the design in  FIG. 6 , as described below. 
   Since M 3  is biased inside a feedback loop with the operational amplifier  602 , the feedback loop reduces the input source impedance of M 3 . Therefore, the signal current I A  can flow into M 3  even though the output impedance of the DC bias current source  308  is unchanged. 
   A quantitative analysis of the circuit illustrated in  FIG. 6  is generally not feasible, or extremely difficult, if the gate voltage of M 3  is involved. 
   Instead of finding the gate voltage of M 3 , I BIAS  is used as the key of the circuit analysis. The total dc bias current  308  is equal to the sum of both I A  and I B . The current going through M 4  is equal to I BIAS . Therefore, substituting I BIAS  into the total current of I A  and I B  can relate the gate voltage of M 3  with V CM . 
   The derivation below shows that for the W/L ratio of M 4  and the bias current  606  that is ¼ the bias current  608 , the amplitude of the output current I output    108  is doubled. The relationship between V input    102  and I output    108  for the example of  FIG. 6  is derived as follows: 
           I   1     =         K   *     ⁡     (       V   1     -     V   X       )       2       ;       where   ⁢           ⁢     V   X       =       V   S     +     V   TH         ;       
           I   2     =         K   *     ⁡     (       V   2     -     V   X       )       2       ;       
               I   BIAS     =           K   *     ⁡     (       V   CM     -     V   X       )       2     =     2   ⁢         K   *     ⁡     [         (       V   1     +     V   2       )     /   2     -     V   X       ]       2                     =     2   ⁢       K   *     ⁡     [         (       V   1   2     +     2   ⁢     V   1     ⁢     V   2       +     V   2   2       )     /   4     -       V   1     ⁢     V   X       -       V   2     ⁢     V   X       +     V   X   2       ]                     =       K   *     ⁡     [         (       V   1   2     +     2   ⁢     V   1     ⁢     V   2       +     V   2   2       )     /   2     -     2   ⁢     V   1     ⁢     V   X       -     2   ⁢     V   2     ⁢     V   X       +     2   ⁢     V   X   2         ]                 
               I   A     =       ⁢         I   1     +     I   2       =           K   *     ⁡     (       V   1     -     V   X       )       2     +         K   *     ⁡     (       V   2     -     V   X       )       2                     =       ⁢       K   *     ⁡     (       V   1   2     -     2   ⁢     V   1     ⁢     V   X       +     V   X   2     +     V   2   2     -     2   ⁢     V   2     ⁢     V   X       +     V   X   2       )                   =       ⁢       K   *     ⁡     (       V   1   2     +     V   2   2     -     2   ⁢     V   1     ⁢     V   X       -     2   ⁢     V   2     ⁢     V   X       +     2   ⁢     V   X   2         )                 
         I   B     =         4   *     ⁢     I   BIAS       -     I   A           
               I   OUT     =       ⁢         I   A     -     I   B       =       2   ⁢     I   A       -       4   *     ⁢     I   BIAS                       =       ⁢     2   ⁢       K   *     ⁡     (         V   1   2     /   2     +       V   2   2     /   2     -       V   1     ⁢     V   X         )                     =       ⁢         K   *     ⁡     (       V   1     -     V   2       )       2               
         I   OUT     =       K   *     ⁢     V   IN   2           
Thus, I output =KV in   2 Eqs. (2) 
   Where K is proportional to W/L. Recall from Eqs. (1) above that for the example of  FIG. 3 , I output =KV in   2 /2. Thus, the frequency doubler  100  illustrated in  FIG. 6  provides twice the current I output    108 , for a given (W/L) ratio and input voltage. 
   In the example of  FIG. 6  the frequency doubler  100  is implemented with NMOS transistors. Alternatively, and/or additionally, the frequency doubler  100  of  FIG. 6  is implemented with PMOS transistors, as illustrated in  FIG. 7 . Operation of the PMOS frequency doubler  100  illustrated in  FIG. 7  is substantially similar to the operation of the NMOS frequency doublers  100  illustrated in  FIG. 6 , with the exception that the PMOS transistors M 1 , M 2 , M 3 , and M 4  in  FIG. 7  turn on as the voltages at their respective gate terminals decrease. 
   CONCLUSION 
   The present invention has been described above with the aid of functional building blocks illustrating the performance of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed. Any such alternate boundaries are thus within the scope and spirit of the claimed invention. One skilled in the art will recognize that these functional building blocks can be implemented by discrete components, application specific integrated circuits, processors executing appropriate software and the like and combinations thereof. 
   While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.