Abstract:
A structure formed in a semiconductor substrate having at least one area having a high concentration of atoms of a metal such as platinum or gold, in which the area is surrounded with at least one first trench penetrating into the substrate.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to monolithic structures comprising one or several power or high-voltage switching or protection component(s), formed in a semiconductor substrate and methods for forming such structures. The present invention more specifically relates to such components comprising areas with a low concentration and areas with a high concentration of a metal such as gold or platinum.  
         [0003]     2. Discussion of the Related Art  
         [0004]     In such structures, it is sometimes desired to reduce the minority carrier lifetime in a component, for example, to obtain a fast diode. For this purpose, diffusions of metal atoms such as gold or platinum are currently used. Such diffusions result, for example from the deposition of a platinum layer on a semiconductor substrate and from an anneal to diffuse the platinum into the substrate.  
         [0005]     A disadvantage of this method is that the platinum very rapidly diffuses into the substrate and that the process is difficult to control. In particular, it appears to be difficult to perform a platinum diffusion at selected locations only of a silicon substrate.  
       SUMMARY OF THE INVENTION  
       [0006]     An object of the present invention is to provide a semiconductor component manufacturing method which enables introducing platinum into determined areas of a semiconductor substrate.  
         [0007]     Another object of the present invention is to provide a semiconductor component structure in which only certain components or component portions comprise platinum.  
         [0008]     To achieve these and other objects, the present invention provides a structure formed in a semiconductor substrate comprising at least one area having a high concentration of atoms of a metal such as platinum or gold, in which said area is surrounded with at least one first trench penetrating into the substrate.  
         [0009]     According to an embodiment of the present invention, said at least one first trench is filled with an insulator such as silicon oxide.  
         [0010]     According to an embodiment of the present invention, said at least one first trench has a depth ranging between 5 and 50 μm.  
         [0011]     According to an embodiment of the present invention, the structure further comprises at least one second trench in the substrate surface opposite to that comprising said at least one first trench, and substantially opposite thereto.  
         [0012]     According to an embodiment of the present invention, said area corresponds to all or part of the semiconductor areas constitutive of a diode.  
         [0013]     According to an embodiment of the present invention, said at least one first trench is formed in an insulating wall insulating a component comprising said area from other components.  
         [0014]     According to an embodiment of the present invention, the structure forms the association of a fast diode and of a slow diode formed of a semiconductor region of a first type formed in a layer of a second type, said at least one trench being formed short of the periphery of said region.  
         [0015]     The present invention also provides a method for forming, in a semiconductor substrate, an area having a high concentration of atoms of a metal such as platinum, comprising forming at least one first trench penetrating into the substrate around said area; depositing said metal substantially above the central portion of said area; and diffusing the metal into all of said area, the number n, the depth p, the spacing e, and the width t of trenches being a function of the depth  1 ′ of the area and the ratio k between the surface diffusion speed and the volume diffusion speed of the said metal according to the following relation: (2p+e+t)*n&gt;k*1′.  
         [0016]     The foregoing objects, features, and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]      FIG. 1  is a cross-section view of a portion of a semiconductor substrate in which platinum is desired to be introduced;  
         [0018]      FIGS. 2A and 2B  respectively are a cross-section view and a top view of a semiconductor substrate according to the present invention in which platinum is desired to be introduced into a predetermined area;  
         [0019]      FIG. 3  is a cross-section view of a portion of a circuit according to the present invention;  
         [0020]      FIG. 4  is an electric diagram of a power circuit; and  
         [0021]      FIG. 5  is a cross-section view of the circuit schematized in  FIG. 4 . 
     
    
     DETAILED DESCRIPTION  
       [0022]     FIGS.  1  to  5  are partial simplified views and are only intended to simplify the understanding of the following description. It will be within the abilities of those skilled in the art to form practical devices by using known techniques. Further, as usual in the field of the representation of semiconductor components, the dimensions of the various layers and regions are not drawn to scale.  
         [0023]     The present invention is based on an analysis of the diffusion process of a metal such as platinum in a semiconductor substrate, for example, silicon.  
         [0024]      FIG. 1  is a cross-section view of a semiconductor substrate  1  on which a metal portion  2 , which is desired to be diffused into the substrate, has been deposited.  
         [0025]     For a given diffusion time, a volume diffusion of depth  1  is observed in the substrate and a lateral diffusion of length L is observed at the substrate surface. In the case of platinum, length L is approximately  16  times as large as depth  1 , the volume diffusion of the metal being much slower than its surface diffusion. In the case of gold, this ratio is of approximately 7 to 1.  
         [0026]     The following examples will be given in the case of platinum, noting that the present invention also applies to other metals, for example, gold. If platinum is desired to be diffused down to a depth  1  of a few tens of μm, for example, 30 μm, surface diffusion length L is approximately 500 μm on either side of metal portion  2 . For 30 μm of in-depth diffusion, a surface diffusion of the substrate over approximately 1 mm 2  is observed.  
         [0027]     It thus appears to be impossible in practice to form on the same semiconductor substrate areas having undergone a platinum diffusion and platinum-free areas, unless very large distances are provided between these areas.  
         [0028]      FIGS. 2A and 2B  respectively are a cross-section view and a top view of a structure according to the present invention formed in a semiconductor substrate  10 . In this example, platinum is desired to be introduced into central portion  11  of substrate  10  without introducing platinum into peripheral portion  12  of substrate  10 . Before diffusing platinum into substrate  10 , a succession of trenches T 1 , T 2 , T 3 , and T 4  are formed at the front surface of the substrate around central portion  11  of substrate  10 . The trenches are in this example ring-shaped in top view. The trench depth typically is of a few tens of μm. The width and the spacing of the trenches are provided to be as thin as possible, typically of a few μm, to form a large number of trenches on a small substrate surface.  
         [0029]     Number n, depth p, spacing e, and width t of the trenches are determined according to the depth of diffusion  1 ′ which is desired in central portion  11 . The relation between these data is substantially the following: (2p+e+t)*n= 1 ′*16, where 16 corresponds to the ratio between the surface diffusion speed and the volume diffusion speed in the case of platinum. If a diffusion depth  1 ′ of approximately 20 μm is desired to be obtained, approximately 10 trenches of a 15 μm depth, of a 2-μm width, and spaced apart by 3 μm, could be provided.  
         [0030]     Once the trenches have been formed in substrate  10 , a portion of platinum layer  15  is placed above central portion  11  of substrate  10 . The structure is then placed in an enclosure heated at a temperature of approximately 900° C. for a time corresponding to the time necessary to diffuse platinum substantially down to the selected depth  1 ′.  
         [0031]     If platinum is desired to be diffused across the entire thickness of the substrate, by depositing, as previously, platinum at the front surface of the substrate above central portion  11 , it may be necessary to provide trenches T′ 1 , T′ 2 , T′ 3 , and T′ 4  at the rear surface of the substrate, as shown in dotted lines in  FIG. 2A . Trenches T′ 1  to T′ 4  are then used to limit the lateral diffusion of platinum along the rear surface when platinum arrives at the level of the rear surface after having diffused through then entire substrate thickness.  
         [0032]      FIG. 3  is a cross-section view of a portion of a monolithic structure comprising a thyristor and a diode. The monolithic structure is formed in a semiconductor substrate  20 . A heavily-doped P-type anode region  22 , common to the thyristor and to the diode, is formed on the rear surface side of substrate  20 . The thyristor further comprises an N-type cathode region  23 , formed on the front surface side of substrate  20  in a P-type well  24 , itself formed in a portion  25  of substrate  20 . The diode further comprises a heavily-doped N-type cathode contact region  26 , formed on the front surface side in a portion  27  of substrate  20 . Portions  25  and  27  of substrate  20  are separated by a P-type doped insulating wall  28 . An insulating wall  29  is placed between portion  25  of substrate  20  and the circuit edge. An insulating wall  30  insulates the diode from a possible other component of the monolithic structure, not shown. A conductive layer  31  covers the rear surface of substrate  20 .  
         [0033]     In the example of a structure shown in  FIG. 3 , platinum is desired to be introduced into all the semiconductor areas of the diode to create a fast diode, without introducing any platinum into the thyristor, nor into any other component placed next to the diode. For this purpose, trenches are formed in insulating walls  28  and  30  at the front and rear surfaces of the substrate. At the front surface of the substrate, trenches T 10 , T 11 , and T 12  are formed at the surface of insulating wall  28  and trenches T 20 , T 21 , and T 22  are formed at the surface of insulating wall  30 . At the rear surface of the substrate, trenches T 30 , T 31 , and T 32  are formed at the surface of insulating wall  28  and trenches T 40 , T 41 , and T 42  are formed at the surface of insulating wall  30 . Although, in the cross-section view, different reference numerals have been assigned to the trenches located to the right and to the left of the diode, it should be noted that, as illustrated in  FIG. 2B , these may be ring-shaped trenches.  
         [0034]     A method of platinum diffusion into the diode then comprises placing a platinum layer portion  40  substantially above cathode region  26 , then placing the structure in a heated enclosure for a duration corresponding to the time required to diffuse a sufficient amount of platinum to the rear surface of substrate  20  (at least to the interface between substrate portion  27  and P layer  22 ). Grooves T then limit the lateral diffusion of platinum.  
         [0035]      FIG. 4  is an electric diagram of a circuit frequently used in power electronics and comprising a fast diode Dr generally obtained by introducing platinum in all or part of the semiconductor areas constitutive of the diode and a slow diode D 1  which does not contain platinum. Diodes D 1  and Dr are placed in parallel between an anode region A and the ground, their cathodes being grounded. A resistor R may be placed between anode terminal A and the anode of diode D 1 . The value of resistance R is set according to the switching characteristics desired for the circuit.  
         [0036]      FIG. 5  is a cross-section view of an embodiment in the form of a monolithic structure according to the present invention of the two diodes of  FIG. 4 . The structure is formed in a semiconductor substrate  100 . A heavily-doped P-type region  101  is formed on the front surface side of substrate  100  in an N-type thick layer  102 . A heavily-doped N-type cathode region  103  is placed under thick layer  102  on the rear surface side of substrate  100 . A conductive layer  104  covers the rear surface of substrate  100 .  
         [0037]     According to the present invention, trenches t 1  to tn are formed beyond the periphery of anode region  101 . In the case where anode region  101  is square-shaped in top view, trenches t 1  to tn form a set of squares placed one inside of the other. The trenches are, as previously, narrow and close to one another and are preferably filled with an insulating material.  
         [0038]     An insulating layer covers the front surface of substrate  100  except above a central portion of anode region  101  located inside of trenches t 1  to tn. A platinum pad  120  is in contact with the central portion of anode region  101 . Then, after a thermal processing, platinum diffuses into the central portion of P anode region  101 , as well as into a portion of thick layer  102  and possibly into a portion of cathode region  103  placed substantially above this central portion. The limit of the area in which the platinum concentration is sufficient to modify the minority carrier lifetime has been illustrated by a curve C.  
         [0039]     Fast diode Dr then corresponds to the “central” diode formed of the portion delimited by curve C. Slow diode D 1  corresponds to the “peripheral” diode formed of the peripheral portion of the junction between anode region  101  and layer  102  external to the portion defined by curve C. Resistor R corresponds to the resistance of the portion of anode region  101  located between metal pad  120  and the junction between anode region  101  and layer  102 .  
         [0040]     As an example, the thickness of anode region  101  is 20 μm, and the thickness of layer  102  is 40 μm. Curve C starts for example from the limit of the n-th layer and goes down to a depth of approximately 50 μm with respect to the front surface of the substrate. In the case where the trenches have a 15-μm depth, a 5-μm depth, and a 5-μm interval, the number of necessary trenches to obtain curve C is on the order of 20.  
         [0041]     Of course, the present invention is likely to have various alterations, modifications, and improvements which will readily occur to those skilled in the art. In particular, it will be within the abilities of those skilled in the art to implement the present invention to introduce platinum into all or part of the semiconductor areas of various components. Various trench depths may be chosen according to the used technologies and to the implied semiconductor structures. Values comprised between 5 and 50 μm may for example be chosen.  
         [0042]     Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.