Abstract:
SMSK data link degradation in future and immediate past bits produced by carrier phase error and small errors in the sampling instant are reduced by a recursive adaptive equalizer having a feedforward stage with adjustable weight for each future bit to be corrected and a feedback stage with adjustable weight for each immediate past bit to be corrected. The weights are controlled by a controller which samples the output and adjusts each weight until the output is correct.

Description:
BACKGROUND OF THE INVENTION 
     Minimum shift keying (MSK) is an attractive modulation technique for digital communication systems incorporating hard limiting amplifiers in the channel. This is due to its constant envelope and compact spectral characteristics. In addition the MSK signal can be generated with simple hardward by a single data stream. The MSK signal can also be demodulated in serial fashion with simple hardware. This serial MSK (SMSK) is of particular interest because of the inherent advantages of the MSK modulation format and the simplicity of the hardware required. Digital communication systems can be significantly degraded by intersymbol interference caused by band limiting, filter misalignment, and multipath effects. Degradation due to intersymbol interference can often be effectively reduced by an equalizer filter. 
     SUMMARY OF THE INVENTION 
     The present invention pertains to a recursive adaptive equalizer for SMSK data links including a plurality of feedback loops each including at least one bit of delay and each adjustable in weight and polarity and a plurality of feed forward loops each including at least one bit of delay and each adjustable in weight and polarity. 
     The present invention further pertains to a recursive adaptive equalizer for SMSK data links wherein the adjustable weights are controlled by a microprocessor. 
     It is an object of the present invention to provide a new and improved equalizer filter for effectively reducing degradation due to intersymbol interference. 
     It is a further object of the present invention to provide a recursive adaptive equalizer for SMSK data links having at least one stage to reduce the effects of future bits and at least one stage to reduce the effects of past bits, each stage being controlled by a controller which samples the output and adjusts the weight of the stages to reduce intersymbol interference. 
    
    
     These and other objects of the invention will become apparent to those skilled in the art upon consideration of the accompanying specification, claims and drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Referring to the drawings, 
     FIG. 1 is a block diagram of a recursive adaptive equalizer for SMSK data links embodying the present invention; 
     FIG. 2, A, B and C are typical waveforms available at various points in the block diagram of FIG. 1; and 
     FIG. 3 is a block diagram of another embodiment of a recursive adaptive equalizer for SMSK data links embodying the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The output signal of an ideal SMSK system is given by: ##EQU1## where ##EQU2## otherwise d n  =±1 is the data sequence, 
     T is the bit link interval and θ is the carrier reference phase error. 
     When the carrier phase error, θ, is zero, sampling the output signal at t=kT results in the original data sequence, d k . However when θ is not zero, intersymbol interference from the immediate past bit d k-1  and future bit d k+1  will occur. If sampling is done at t=kT+Δt (where Δt represents a small error in the sampling instant) intersymbol interference from two bits in the &#34;future&#34; or past can occur. If multipath, bandlimiting or misaligned filters are present in the system, intersymbol interference from bits farther in the past can be expected. Thus the sampled output of a SMSK communication link can be expected to be of the form: 
     
         r.sub.k =a.sub.2 d.sub.k+2 +a.sub.1 d.sub.k+1 +a.sub.o d.sub.k +a.sub.-1 d.sub.k-1 +a.sub.-2 dk.sub.-2 +a.sub.-3 d.sub.k-3 
    
     where a o  d k  is the desired signal and a 2  d K+2 ,a 1  d k+1 ,a -1  dk -1  etc. are intersymbol interference components from various sources. The intersymbol interference from past bits has been arbitrarily terminated at the third past bit but the system to be described could be easily expanded to accommodatemore terms. Based on the nature of the intersymbol interference expected in a SMSK system the equalizer was selected to have the form shown in FIG. 1. Three feedback taps are incorporated to provide for cancellation of intersymbol interference from up to three past bits and two feedforward paths are provided to reduce intersymbol interference from future bits. 
     Referring specifically to FIG. 1, an input terminal 10 adapted to receive SMSK signals is connected to one input of a summation circuit 12. In this embodiment the summation circuit 12 has three other inputs and an output. The output of the summation circuit 12 is connected through a one bit delay 14 to a junction 15. The junction 15 is connected through a weighting device 16 to one of the inputs to the summation circuit 12. The weighting device 16 has a weight input, designated W 3 , connected to the W 3  output of a controller 20. The weighting device 16 basically multiplies a weight and polarity adjusting signal on the weight input by the signal from the junction 15 to feedback the desired polarity and amplitude of signal. While the weighting device may be a simple multiplier circuit, many other types of circuits which provide the desired weight and polarity signal might be utilized. The feedback loop, including the delay 14 and the weighting device 16, is utilized to reduce errors in the SMSK signal from the immediate past bit. 
     The junction 15 is also connected through a second one bit delay 22 to a second junction 25. The junction 25 is connected through a weighting device 26 to another input of the summation circuit 12. The weighting device 26 has a weight input, designated W 4 , connected to the W 4  output of the controller 20. The loop including the delay 22 and the weighting device 26 is designed to correct intersymbol interference caused by the second immediate past bit. The junction 25 is connected through a one bit delay 28 to a junction 30. The junction 30 is connected through a weighting device 32 to another input of the summation circuit 12. The weighting device 32 has a weight input, designated W 5 , connected to the W 5  output of the controller 20. The loop including the delay 28 and the weighting device 32 is designed to correct intersymbol interference caused by the third past bit. The junction 30 is also connected to one input of a second summation circuit 35, the output of which is available at a terminal 36 and is the corrected SMSK signal at the output of the recursive adaptive equalizer. 
     The junction 15 is also connected through a weighting device 38 to another input of the summation circuit 35. The weighting device 38 has an input, designated W 1 , connected to the W 1  output of the controller 20. The loop including the delay 22 and the weighting device 38 comprises a feedforward loop which corrects the intersymbol interference in the SMSK signal caused by the first future bit. The junction 25 is connected through a weighting device 40 to another input of the summation circuit 35. The weighting device 40 has a weight input, designated W 2 , connected to the W 2  output of the controller 20. The feedforward loop including the delay 28 and the weighting device 40 is designed to correct intersymbol interference in the SMSK signal caused by the second future bit. 
     The signal at the output of the summation circuit 35 is also supplied to the controller 20. The controller 20 supplies the signal from the output of the summation circuit 35 to an AGC amplifier 45. The output of the amplifier 45 is supplied through a fullwave rectifier 47 to one input of a summation circuit 50. The summation circuit 50 also has an input connected to an offset output of the controller 20. The output signal from the summation circuit 50 is supplied through a multiplier 52 to the input of a fullwave rectifier 54. A second input of the multiplier 52 is received from a sampling pulse output of the controller 20. The output of the multiplier 52 is also supplied through a lowpass filter 55 to the control input of the AGC amplifier 45 to operate as an AGC signal. The output of the fullwave rectifier 54 is supplied through a bandpass filter 56 to one input of a multiplier 58. A second input of the multiplier 58 is connected to a dither signal output of the controller 20. The output of the multiplier 58 is supplied through a lowpass filter 60 to the positive input of a comparator 62. The negative input of the comparator 62 is connected to a reference potential, such as ground. The output of the comparator 62 is connected to an input of the controller 20. 
     The weighting signals, W 1  through W 5  are adjusted under the control of the controller 20 to minimize a measure of the intersymbol interference present in the output signal at the output of the summation circuit 35. The measurement is based on the fact that an ideally equalized signal will have an amplitude of +A or -A at the sampling instant, where A is constant for all sampling instants. When intersymbol interference is present, the amplitude of the signal will have a variable magnitude at the sampling instant. 
     Operation of the system of FIG. 1 can be understood through examination of the waveform sketches in FIG. 2. An input waveform containing intersymbol interference is shown by waveform A of FIG. 2 and is illustrated as appearing at the input of the amplifier 45. The fullwave rectified signal at the output of the rectifier 47 is illustrated by waveform B of FIG. 2. A constant offset is subtracted from this waveform in the summation circuit 50 and the difference is multiplied by a sampling pulse, in the multiplier 52, resulting in the signal at point C shown by waveform C of FIG. 2. The constant offset is actually a DC voltage which may be supplied by the controller 20 but in this preferred design is produced simply by capacitively coupling the signal at point B to the multiplier 52. The action of the automatic gain control is to tend to produce a waveform with zero average value at point C. When intersymbol interference is present, the waveform at point C will contain a negative pulse if the input amplitude is reduced by the intersymbol interference or a positive pulse if the input amplitude is increased by the intersymbol interference at the sampling instant. When the input does not contain intersymbol interference the amplitude will be constant in magnitude at the sampling instant and no pulses of either polarity will occur at point C. The pulses at point C are then fullwave rectified in rectifier 54 and the signal resulting at the output thereof will have an average value which is a measure of the amount of intersymbol interference in the input signal. 
     The controller 20 selects each tap weight in turn for adjustment. The tap selected is periodically dithered up and down a small amount. The dithering results in a periodic fluctuation in the average value of the signal at the output of the fullwave rectifier 54. This fluctuation is filtered by the bandpass filter 56, which is centered on the frequency of the dither, and synchronously detected by the multiplier 58 with the reference dither signal supplied by the controller 20. The result is positive or negative depending on whether an increase in the weight signal causes an increase or a decrease in the intersymbol interference content of the signal at the output of the summation circuit 35. This signal is converted to a logic signal and returned to the controller 20 so a decision on whether to increase or decrease the weight signal selected can be made. Thus, in addition to supplying several periodic signals such as the offset, the sampling pulse and the dither signal, the controller basically timeshares the adjustment circuit among the five weight inputs. While a variety of well known switching circuits can be utilized for the controller 20, in the preferred embodiment a microprocessor is utilized to provide the desired functions. 
     Referring specifically to FIG. 3, a slightly modified embodiment of the recursive adaptive equalizer is illustrated. The controller and adaptive adjustment circuit is not illustrated because this circuitry is the same as illustrated in FIG. 1. In the circuit of FIG. 3, an input terminal 65 is connected directly to a junction 67, which is in turn connected through a one bit delay 68 to a second junction 70. The junction 70 is connected through a one bit delay 72 to one input of a summation circuit 75. The junction 67 is connected through a weighting device 76 to another input of the summation circuit 75. The weighting device 76 has a weight input W 1  connected to the W 1  output of the controller, not shown. The junction 70 is connected through a weighting device 78 to another input of the summation circuit 75. The weighting device 78 has a weight input W2 connected to the W2 output of the controller. An output of the summation circuit 75 is connected directly to an output terminal 80 and through a one bit delay 82 to a junction 84. The junction 84 is connected through a one bit delay 86 to a junction 88. The junction 84 is connected through a weighting device 90 to another input of the summation circuit 75. The weighting device 90 has a weight input W 3  connected to the W 3  output of the controller. The junction 88 is connected through a weighting device 92 to another input of the summation circuit 75. The weighting device 92 has a weight input W 4  connected to the W 4  output of the controller. The junction 88 is also connected through a one bit delay 94 to the input of a weighting device 95. The output of the weighting device 95 is connected to another input of the summation circuit 75. The weighting device 95 also has a weight input W 5  connected to the W 5  output of the controller. 
     The feedforward loop including the delay 68 and the weighting device 76 is designed to reduce intersymbol interference from the first future bit while the feedforward loop including the delay 72 and the weighting device 78 is designed to reduce intersymbol interference from the second future bit. The three feedback loops including delay 82 and weighting device 90, delay 86 and weighting device 92, and delay 94 and weighting device 95, respectively, are designed to reduce intersymbol interference due to the first, second and third immediate past bits, respectively. 
     Thus, embodiments of a recursive adaptive equalizer for SMSK data links are disclosed, which substantially reduce intersymbol interference caused by band limiting, filter misalignment, and multipath effects and, therefore, make practical the use of SMSK as a modulation technique or digital communication systems. While we have shown and described specific embodiments of this invention, further modifications and improvements will occur to those skilled in the art. We desire it to be understood, therefore, that this invention is not limited to the particular forms shown and we intend in the appended claims to cover all modifications which do not depart from the spirit and scope of this invention.