Abstract:
A circuit having a first circuit configured to receive an input voltage and generate a first voltage that generates a first current flowing through a resistive device and a second voltage that generates a second current; a node electrically coupled to the resistive device and having a third voltage that generates a third current; and a second circuit configured to generate a fourth voltage having a logic state indicating a logic state of the resistive device.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application claims priority of U.S. Provisional Patent Application Ser. No. 61/221,842, filed on Jun. 30, 2009 which is incorporated herein by reference in its entirety. 
    
    
     TECHNICAL FIELD 
     The present disclosure is related to resistance. Various embodiments provide mechanisms to precisely and efficiently measure eFuse (electrical fuse) resistance and thus overcome limitations of approaches that use testers for such measurements. 
     BACKGROUND 
     Currently, acquiring precise eFuse resistance is inefficient, especially for huge volume analysis. Generally, approaches using testers force a voltage, measure the current, and then calculate the resistance from the current and voltage. For memory arrays, various approaches measure the eFuse resistance of the memory cells bit by bit (e.g., cell by cell), and require connection time between a tester and the memory array for each bit. Approaches using a parameter measurement unit (PMU) can require setup and stabilization time. For example, some approaches, including connection, setup and stabilization time, etc., take about 220ms to measure resistance of an eFuse in a memory cell or about 15 minutes for a memory array of 4k cells, making it inefficient to collect high volume data for statistical analysis. This can affect reliability and quality in eFuse development. Further, during different measurements eFuse resistance can shift, resulting in inaccurate measurements. Additionally, some column selects of PMOS resistance of the memory array with high current can force a programming device for the eFuse into saturation mode, also resulting in inaccurate measurements. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the disclosure will be apparent from the description, drawings, and claims. 
         FIG. 1  shows an exemplary memory array that can benefit from embodiments of the disclosure. 
         FIG. 2  shows a circuit embodiment of the disclosure. 
         FIG. 3  is a flow chart illustrating a method of operation from the circuit of  FIG. 2 . 
         FIG. 4  is a flow chart illustrating a method for measuring a resistance value of an eFuse in the circuit of  FIG. 2 . 
     
    
    
     Like reference symbols in the various drawings indicate like elements. 
     DETAILED DESCRIPTION 
     Embodiments, or examples, of the disclosure illustrated in the drawings are described using specific language. It will nevertheless be understood that no limitation of the scope of the invention is thereby intended. Any alterations and modifications in the described embodiments, and any further applications of principles of the disclosure described in this document are contemplated as would normally occur to one skilled in the art to which the disclosure relates. Reference numbers may be repeated throughout the embodiments, but this does not necessarily require that feature(s) of one embodiment apply to another embodiment, even if they share the same reference number. 
     The Memory Array 
       FIG. 1  shows a memory array  100  that can benefit from various embodiments of the disclosure. For illustration purposes, memory array  100  includes m bit lines BL and n word lines WL. Each bit line BL is associated with a bit line select transistor  116  and a plurality of n memory cells each of which includes an eFuse  114  and a programming device (e.g., transistor)  115 . A bit line BL controls bit line select transistor  116 . When bit line BL is activated (e.g., driven with a high logic (High)) it turns on transistor  116 , and when it is de-activated (e.g., drive with a low logic (Low)), it turns off transistor  116 . A word line WL controls (e.g., turning on or off) a corresponding programming transistor  115 . Circuit  110  including transistor  116 ( 0 , 0 ), eFuse  114 ( 0 , 0 ) and transistor  115 ( 0 , 0 ), for illustration purposes, are explained in conjunction with  FIG. 2  below. 
     An eFuse  114  generally includes two logic states, e.g., a low and a high. In an embodiment, the eFuse  114  is Low when its resistance is Low and is High when its resistance is High. For illustration purposes, the resistance of an eFuse  114  may be referred to as R, and in an embodiment, is about 200 Ohm for a low and about 10K Ohm for a high. Transistors  115  may be referred to as selectors or programming transistors. To access an eFuse  114  (e.g., eFuse  114 ( 0 , 0 ) a corresponding bit line BL (e.g., BL( 0 )) and word line WL (e.g., WL( 0 )) are activated, which in turn activate the corresponding transistors  116 ( 0 , 0 ) and  115 ( 0 , 0 ). 
     EXEMPLARY FEATURES OF VARIOUS EMBODIMENTS 
     Various embodiments of the disclosure provide mechanisms to efficiently and precisely measure resistance of eFuse  114 . For example, in an embodiment, the circuit to measure the eFuse  114  (e.g., circuit  200  in  FIG. 2  as discussed below) is embedded in a same semiconductor chip embodying the memory array (e.g., memory array  100 ), and therefore provides efficient measurements because the long-time communication and/or connection with an external source (e.g., a tester) for such measurement can be avoided. In an application, measuring eFuse resistance of cells in the memory array (e.g., array  100 ) can be done by appropriately toggling the address (e.g., selecting the bit lines BL and word lines WL) of each cell, resulting in efficient (e.g., fast) measurements. Further, measuring resistance of an eFuse  114  of a memory cell takes about 50ns, which is much faster than 220ms required in other approaches. As acquiring eFuse resistance in accordance with embodiments of the disclosure can be done in a short time, volume of resistance data (e.g., for the whole wafer and/or batch of wafers) can be collected and thus greatly benefit designers in electrical characterization analysis. For another example, volume of resistance data for pre-baked and post-baked tests can be collected, and shifts in eFuse resistance from different tests can be identified and analyzed. Additional benefits from the ability to collect huge volume of resistance data in accordance with some embodiments of the disclosure include, for example, margin checks, screen functions, quality enhancement, etc. 
     Circuit Embodiment to Measure eFuse Resistance 
       FIG. 2  shows a circuit  200  used to measure eFuse resistance in accordance with an embodiment of the disclosure. For illustration purposes, circuit  200  includes circuit  210  that corresponds to circuit  110  in  FIG. 1 . 
     Circuit  230  receives the input reference voltage Vref from which voltages Vref 1  and Vref 2  are generated. When voltage Vref activates transistor  231 , it generates current I 4  flowing through transistor  241 , resistor R 1  and transistor  231 , which also generates Vref 1  at the drain and the gate of transistor  241 . Those skilled in the art will recognize that because transistor  231  is an NMOS, current I 4  is proportional to voltage Vref. 
     In an embodiment, a reference resistance, e.g., resistance Rref, is generated from voltage Vref. Once voltage Vref 1  is generated Op Amp  280  buffers this voltage Vref 1  to line  281  so that a voltage measurement device (e.g., voltage meter Mex) external to the chip embodying circuit  200  can measure this voltage Vref 1 . Further, because current I 4  is mirrored to current I 6  through transistor  270 , the drain of transistor  270  is coupled to a current meter (e.g., current meter Iex) external to the chip embodying circuit  200  so that this current meter Iex can measure this current I 6  or in fact, current I 4 . In an embodiment, the external current meter Iex is provided with a voltage having the same value as Vref 1  to provide a better mirror of current I 6  from current I 4 . This is because, for a better current mirror, it is desirable that the voltage at the drain of transistor  270  (e.g., voltage Vex) be similar to the voltage at the drain of transistor  241 , which is Vref 1 . Because Rref=Vex/I 6  and Vex=Vref 1 , Rref=Vref 1 /I 6 . As explained above, voltage Vref 1  is known through voltage meter Mex and current I 6  (or I 4 ) is known through current meter Iex, Rref can be calculated. In an embodiment, a tester provides both voltage meter Mex and current meter Iex. 
     Those skilled in the art will recognize that different values of Vref provide different values of Vref 1  and thus different values of Rref. Further, varying one or a combination of the value of resistor R 1  and the size of transistor  231  varies the value of current I 4 . As a result, varying one or a combination of voltage Vref, the size of transistor  231  and the value of resistor R 1  varies Rref. For illustration purposes a circuit including a resistor R 1  and transistor  231  may be referred to as a current branch. Depending on applications and design choices circuit  200  may include various current branches so that different ranges of Rref may be selected. Depending on the desired values of resistance Rref, one or a combination of different current branches may be selected so that the desired resistance Rref may be generated. For example, branches BR 1 , BR 2 , BR 3  (not shown) provide currents 5nA, 15nA, and 25nA respectively. To have a reference resistance Rref corresponding to 20nA, branches BR 1  and BR 2  may be selected. For a reference resistance Rref corresponding to 30nA, branches BR 1  and BR 3  may be selected, and for a reference resistance corresponding to 40nA, branches BR 2  and BR 3  may be selected, etc. Further, depending on design choices, a resistor (e.g., resistor R 1 ) may or may not be included in a current branch. Alternatively, a resistive circuit (e.g., transistor) may replace the resistor R 1 . The value of a current branch (e.g., 5nA, 15nA, 25nA, etc.) is a design choice and, depending of implementations, depends on the size of the transistor and the value of the resistor constituting the current branches, etc. The above exemplary current branch is for illustration only, various other mechanisms to generate a current branch are within the scope of embodiments of the disclosure. 
     Because the value of the reference voltage Vref can be easily modified (e.g., varied), the value of Rref can be easily varied, providing flexibility in using circuit  200 . For example, in an application, the resistance of eFuse  214  can shift after a temperature bake test. By changing the value of resistance Rref, in conjunction with circuit  200 , the value of eFuse resistance can be easily obtained from the pre- and post-baked tests, the shift of such eFuse resistance from test to test can be easily identified. Depending on applications and design choices, voltage Vref may be varied linearly, setup in a binary search algorithm, or any other convenient techniques. Alternatively, resistance Rref may be varied (e.g., in a linear, a binary search or any other pattern) from which voltage Vref may be input, and the value of eFuse resistance R may be determined and/or measured accordingly. 
     Sense amplifier bias circuit  240  provides currents I 4  and I 5  and voltages Vref 1  and Vref 2 . Current I 4  is generated when voltage Vref turns on transistor  231  allowing current I 4  flowing through PMOS transistor  241 , resistor R 1 , and transistor  231 . Current I 4  is mirrored to current I 5  via PMOS transistor  242  and NMOS transistor  243 . Because transistors  242  and  243  serve as a current mirror of current I 4  to current I 5 , once current I 4  is generated current I 5  is mirrored (e.g., generated), and voltage Vref 2  is also generated. Current I 4  is also mirrored to current I 1  via PMOS transistor  221 . In an embodiment, resistor  244  and transistor  245  serve to provide a reference voltage, e.g., voltage VrefA. Via calculations, a reference resistance, e.g., resistance RrefA (not shown), is calculated from voltage VrefA and is used as a reference resistance for circuit  200  (e.g., similar to resistance Rref). That is, resistance R of eFuse  214  may be determined high or low through sensing circuit  220  with respect to this reference resistance RrefA. 
     Circuit  210  includes an eFuse  214 , the resistance of which, e.g., R, is to be measured. EFuse  214  could be any eFuse  114  of memory array  100  or various other resistors or resistive devices that can benefit from embodiments of the disclosure. Bit line BL 2  and word line WL 2  correspond a bit line BL and a word line WL of memory array  100 . For illustration purposes,  FIG. 2  shows only one eFuse  214 , but embodiments of the disclosure can be used to measure resistance of more than one eFuse (e.g., eFuses for the whole memory array  100 ). When transistor  221  is on current I 1  flows from transistor  221  through transistor  216 , eFuse  214  and transistor  215 . In an embodiment because Vds 216  (not shown), the voltage across the drain and the source of transistor  216 , is insignificant as compared to voltage V 1 , V 1 =R×I 1 . Because current I 1  is a current mirror of current I 4  V 1 =R×I 4  or R=V 1 /I 4 . 
     Sensing circuit  220  detects the logic states of eFuse  214 , e.g., determining whether it is low or high. Voltage Vref 1  at the gate of transistor  221  controls PMOS transistor  221  while voltage Vref 2  at the gate of transistor  222  controls NMOS transistor  222 . As a result, Vref 1  generates current I 1  while Vref 2  generates current I 2 . As discussed above, current I 1  is a current mirrored from current I 4  through transistor  221 , and current I 2  is a current mirrored from current I 5 . Because I 5 =I 4 , I 2 =I 4  . Generally, current I 2  is constant with respect to voltage Vref 2 . 
     Voltage V 1  at the drain of transistor  221  and the gate of transistor  223  controls PMOS transistor  223  and thus generates current I 3 . Because transistor  223  is a PMOS, voltage V 1  is inversely proportionate to current I 3 . That is, if V 1  increases, current I 3  decreases, and if V 1  decreases, I 3  increases. Because R=V 1 /I 4  and Rref=Vref 1 /I 4 , then if R=Rref then V 1 =Vref. As a result, if R&lt;Rref then V 1 &lt;Vref 1 , and if R&gt;Rref then V 1 &gt;Vref 1 . Alternatively expressed, if V 1 =Vref then R=Rref. If V 1 &lt;Vref then R&lt;Rref, and if V 1 &gt;Vref then R&gt;Rref. 
     Because transistor  223  can act as a current mirror for current I 4  when the voltage level at the gate of transistors  241  and  223  are the same, if V 1 , the voltage level at the gate of transistor  223 , equals to Vref 1 , the voltage level at the gate of transistor  241 , then I 3 =I 4  or I 3 =I 2  because I 2  is a mirrored current of I 5 , which is a mirrored current of I 4 . If V 1  increases such that V 1 &gt;Vref (or R&gt;Rref) then I 3  decreases or I 3  &lt;I 2  because I 2  remains unchanged as Vref 2  remains unchanged. Similarly, if V 1  decreases such that V 1 &lt;Vref (or R&lt;Rref) then I 3 &gt;I 2 . Because when V 1 =Vref 1  R=Rref, when V 1 &gt;Vref R&gt;Rref, and when V 1 &lt;Vref R&lt;Rref. Alternatively expressed, if R=Rref then I 3 =I 2 . If R&gt;Rref then I 3 &gt;I 2 , and if R&lt;Rref then I 3 &lt;I 2 . 
     Based on the above analysis, circuit  220  compares currents I 3  and I 2 . If I 3 =I 2  then R=Rref. If I 3 &gt;I 2  then R&lt;Rref, and if I 3 &lt;I 2  then R&gt;Rref. Depending on applications, R may be considered Low if R&lt;Rref, and considered High if R&gt;Rref. Similarly V 1  may be considered a low when V 1 &lt;Vref 1  and considered a high when V 1  &gt;Vref 1 . Because when R&lt;Rref V 1 &lt;Vref, if R is low then V 1  is low and if R is high then V 1  is high. Alternatively expressed, if V 1  is low then R is low, and if V 1  is high then R is high. 
     Inverter INV inverts the logic level of voltage V 2  at the drain of transistor  223  and the drain of transistor  222  to output V 3 . If voltage V 2  is Low then voltage V 3  is High and if voltage V 2  is High then voltage V 3  is Low. As a result, if V 1  is Low then V 2  is High, and V 3  is Low. If V 1  is High then V 2  is Low, and V 3  is High. Alternatively expressed, if R is High then V 3  is Low and if R is High then V 3  is High. Or if V 3  is Low then R is Low and if V 3  is High then R is High. In effect, the logic state of resistor R, or of eFuse  214 , is reflected on voltage V 3 . That is, if eFuse  214  is Low then V 3  is Low, and if eFuse  214  is High then V 3  is High, or if V 3  is Low then eFuse  214  is Low, and if V 3  is High then eFuse  214  is High. As a result, knowing the logic state of voltage V 3  provides the logic state of eFuse resistance R. In an embodiment, voltage V 3  is buffered out of the chip embodying circuit  200  to be used as appropriate. 
     Transistor  270  serves to provide a current I 6  mirrored from current I 4 . Op Amp  280  buffers voltage Vref 1  to line  281  so that this voltage Vref 1  is measured, e.g., by the external voltage meter Mex. External current meter Iex measures current I 6  based on which reference resistance Rref is calculated as Vref 1 /I 6 . Because I 6 =I 4 , Rref=Vref 1 /I 4 . In an embodiment, once voltage Vref 1  is known (e.g., through Op Amp  280 ), the value of voltage Vref 1  is provided to external current meter Iex to provide a better mirror of current I 6  from current I 4 . This is because, for a better current mirror, it is desirable that the voltage at the drain of transistor  270  be similar to the voltage at the drain of transistor  241 , which is Vref 1 . 
     Bit line leakage tracking circuit  250  is used to compensate for the current leakage from bit line BL 2 . Circuit  250  is an imitation of (e.g., compatible with) circuit  210  without an eFuse  214 . Transistors  251  and  252  correspond to transistors  215  and  216 . Circuit  250 , however, does not include a component corresponding to eFuse  214  because this resistance of this eFuse  214 , in an embodiment, is insignificant as compared to that of transistor  252 . If there is any leakage current associated with bit line BL 2  (e.g., through the drain of transistor  216 ), current I 1  would be affected (e.g., increases in the embodiment of  FIG. 2 ). Because currents I 4  and I 1  are mirrored, circuit  250  provides a current path for the change (e.g., increase) in current I 1  to be reflected on current I 4 , resulting in compensation. 
     Exemplary Methods 
       FIG. 3  is a flowchart  300  illustrating a method of operating circuit  100 , in accordance with some embodiments. 
     In step  305 , voltage Vref is applied to turn on transistor  231 . As a result, current I 4  flows, and voltage Vref 1  is created. 
     In step  310 , transistor  242  mirrors current I 4  to current I 5 . Voltage Vref 2  is therefore created, which turns on transistor  222  and generates current I 2 . At the same time, voltage Vref 1  turns on transistor  221  and generates current I 1 . 
     In step  315 , voltage V 1  is created based on current I 1  and the resistance of transistor  216 , eFuse  214 , and transistor  215 , which turns on transistor  223  and generates current I 3 . 
     In step  320 , inverter INV generates voltage V 3  based on currents I 2  and I 3 . 
     In step  325 , the logic level of eFuse  214  is determined based on the logic level of voltage V 3 . 
       FIG. 4  is a flowchart  400  illustrating a method for determining (e.g., measuring) resistance R of eFuse  214 , in accordance with some embodiments. 
     In step  405 , based on a first voltage Vref (e.g., voltage Vref( 1 )) and thus a first value of reference resistance Rref (e.g., resistance Rref( 1 )), the first logic state of eFuse  214  (e.g., logic state State ( 1 )) is determined. For illustration, logic State( 1 ) is High indicating that resistance R of eFuse  214  is higher than resistance Rref( 1 ). 
     In step  410 , voltage Vref is adjusted to a new value, e.g., voltage Vref( 2 ). Based on voltage Vref( 2 ) and thus a new resistance Rref( 2 ), a new logic state State( 2 ) is obtained. For illustration purposes, logic state State( 2 ) is Low indicating that resistance R is lower than resistance Rref ( 1 ). 
     In step  415 , it is determined whether resistance R is equal to resistance Rref. That is, whether Rref( 2 )&lt;R&lt;Rref( 1 ) where Rref( 1 ) is substantially the same as Rref( 2 ). If resistance R is not equal to resistance Rref, then steps  405  and  410  are repeated with one or more values of voltage Vref and thus resistances Rref until Rref(i)&lt;R&lt;Rref(j) where Rref(i) and Rref(j) are substantially equal. In effect R=Rref(i)=Rref(j), or stated another way, R=Rref. The flowchart then ends in step  420 . 
     In the above illustration, there are various mechanisms to adjust voltage Vref and thus resistance Rref, including, for example, using a binary search or linear search method. Embodiments of the disclosures, however, are not limited to any method of adjusting Vref and/or Rref to obtain a resistance R. 
     A number of embodiments of the disclosure have been described. It will nevertheless be understood that various variations and/or modifications may be made without departing from the spirit and scope of the invention. For example, in the illustrative circuits, when a resistor is used, a resistive circuit, component, or device may be used to replace that resistor. Some transistors are shown to be N-type and some others are shown to be P-type, but the disclosure is not limited to such a configuration because selecting a transistor type (e.g., N-type, P-type) is a matter of design choice based on need, convenience, etc. Various embodiments of the disclosure are applicable in all variations and/or combinations of transistor types. Additionally, some signals are illustrated with a particular logic level to operate some transistors (e.g., activated high, deactivated low, etc.), but selecting such levels and transistors are also a matter of design choice, and embodiments of the disclosure are applicable in various design choices. 
     The above methods show exemplary steps, but they are not necessarily performed in the order shown. Steps may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of the disclosed embodiments. Each claim of this document constitutes a separate embodiment, and embodiments that combine different claims and/or different embodiments are within the scope of the disclosed embodiments and will be apparent to those of ordinary skill in the art after reviewing this document.