Abstract:
A memory segment access method and apparatus relates to the field of computer technologies, which are used to resolve a problem of a relatively low memory access bandwidth caused by relatively low utilization of bandwidth resources in a multichannel memory system. The method includes acquiring, by a first scheduler, a quantity of to-be-sent memory access requests in a second scheduler, and receiving, by the first scheduler, a memory access request, and sending the memory access request through a second memory channel corresponding to the second scheduler.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation of International Application No. PCT/CN2014/086592, filed on Sep. 16, 2014, which claims priority to Chinese Patent Application No. 201310422993.7, filed on Sep. 16, 2013, both of which are hereby incorporated by reference in their entireties. 
     
    
     TECHNICAL FIELD 
       [0002]    The present disclosure relates to the field of computer technologies, and in particular, to a memory module access method and apparatus. 
       BACKGROUND 
       [0003]    In the field of computer technologies, to improve a memory access bandwidth, a multichannel memory system is used in many computers. The multichannel memory system includes multiple memory channels, and a memory controller communicates with memory modules using the multiple memory channels. In the multichannel memory system, a mapping relationship between memory addresses and channels is predetermined according to grouping of memory modules such that load of the channels is balanced. When a memory access request is received, a corresponding channel is determined as a target channel according to a memory address in the memory access request, and the memory access request is sent through the target channel. Assuming that a memory system includes two memory modules, a mapping relationship between a memory address and a channel may be determined according to a value of a specific bit in the memory address. For example, a memory access request in which the seventh bit in a memory address is “0” is sent to a target memory module through a channel 0, and a memory access request in which the seventh bit in a memory address is “1” is sent to a target memory module through a channel 1. 
         [0004]    During the implementation of the present disclosure, the inventor finds that the prior art has at least the following problems. 
         [0005]    Because channels between memory modules and a memory controller are independent of each other, when multiple received memory access requests are distributed in an unbalanced manner among multiple channels, for example, when n continuously received memory access requests are all sent to a target memory module through a channel 1, the channel 1 may be congested, and other channels are in an idle state, causing a waste of bandwidth resources, and also causing a relatively low memory access bandwidth. 
       SUMMARY 
       [0006]    Embodiments of the present disclosure provide a memory module access method and apparatus, which can resolve a problem in the prior art that when multiple received memory access requests are distributed in an unbalanced manner among multiple channels, a waste of bandwidth resources is caused, leading to a relatively low memory access bandwidth. 
         [0007]    To achieve the foregoing objective, the embodiments of the present disclosure use the following technical solutions. 
         [0008]    According to a first aspect, an embodiment of the present disclosure provides a memory module access method, applied to a memory system, where the memory system includes at least a first scheduler and a second scheduler, the first scheduler is corresponding to a first memory channel, the second scheduler is corresponding to a second memory channel, and each memory channel is corresponding to one memory module, and the memory system includes multiple memory modules, where a transmission link is established between the multiple memory modules, and a transmission link is established between the first scheduler and the second scheduler, and the method includes acquiring, by the first scheduler, a quantity of to-be-sent memory access requests in the second scheduler, and receiving, by the first scheduler, a memory access request, and sending the memory access request through the second memory channel corresponding to the second scheduler. 
         [0009]    In a first possible implementation manner, the receiving, by the first scheduler, a memory access request, and sending the memory access request through the second memory channel corresponding to the second scheduler includes receiving, by the first scheduler, at least two memory access requests, where the at least two memory access requests include a first memory access request and a second memory access request, where when the first memory access request is sent through the first memory channel corresponding to the first scheduler, the second memory access request is in a to-be-sent state, and if the second memory channel corresponding to the second scheduler is in an idle state, the first scheduler sends the second memory access through the second memory channel corresponding to the second scheduler. 
         [0010]    With reference to the first possible implementation manner, in a second possible implementation manner, before the sending, by the first scheduler, the second memory access request through the second memory channel corresponding to the second scheduler, the method includes sending, by the first scheduler, a memory channel occupation request to the second scheduler, to request to occupy the second memory channel corresponding to the second scheduler to send the second memory access request, and receiving, by the first scheduler, a confirmation response that is returned by the second scheduler in response to the memory channel occupation request. 
         [0011]    With reference to the second possible implementation manner, in a third possible implementation manner, a destination address of the second memory access request is located in a memory module corresponding to the first memory channel. 
         [0012]    With reference to the first aspect or the first possible implementation manner or second possible implementation manner or third possible implementation manner of the first aspect, in a fourth possible implementation manner, the first scheduler has at least two paths, and establishes connections to the first memory channel and the second memory channel using the at least two paths. 
         [0013]    According to a second aspect, an embodiment of the present disclosure provides a memory module access method, applied to a memory system, where the memory system includes at least a first scheduler and a second scheduler, the first scheduler is corresponding to a first memory channel, the second scheduler is corresponding to a second memory channel, and each memory channel is corresponding to one memory module. The memory system includes multiple memory modules, where a transmission link is established between the multiple memory modules, and the method includes receiving, by the first scheduler, at least two memory access requests, including a first memory access request and a second memory access request, and sending, by the first scheduler, the first memory access request through the first memory channel, and sending the second memory access request through the second memory channel. 
         [0014]    In a first possible implementation manner, the sending, by the first scheduler, the second memory access request through the second memory channel includes when the second memory channel is in an idle state, sending the second memory access request through the second memory channel. 
         [0015]    With reference to the first possible implementation manner, in a second possible implementation manner, before the sending the second memory access request through the second memory channel, the method further includes sending, by the first scheduler, a memory channel occupation request to the second scheduler, to request to occupy the second memory channel corresponding to the second scheduler to send the second memory access request, and receiving a confirmation response that is returned by the second scheduler in response to the memory channel occupation request. 
         [0016]    With reference to the second possible implementation manner, in a third possible implementation manner, a destination address of the second memory access request is located in a memory module corresponding to the first memory channel. 
         [0017]    With reference to the second aspect or the first possible implementation manner, or second possible implementation manner, or third possible implementation manner of the second aspect, in a fourth possible implementation manner, each scheduler has multiple paths, and establishes connections to all memory channels using the multiple paths. 
         [0018]    According to a third aspect, an embodiment of the present disclosure provides a memory module access method, applied to a memory system, where the memory system includes at least a first memory channel and a second memory channel, and each memory channel is corresponding to one memory module; and the memory system includes multiple memory modules, where a transmission link is established between the multiple memory modules, and the method includes receiving at least two memory access requests, including a first memory access request and a second memory access request, where destination addresses of the first memory access request and the second memory access request are located in a memory module corresponding to the first memory channel, and sending the first memory access request through the first memory channel, and sending the second memory access request through the second memory channel. 
         [0019]    In a first possible implementation manner, the sending the second memory access request through the second memory channel includes, when the second memory channel is in an idle state, sending the second memory access request through the second memory channel. 
         [0020]    With reference to the first possible implementation manner, in a second possible implementation manner, the memory system includes at least a first scheduler and a second scheduler, the first scheduler is corresponding to the first memory channel, and the second scheduler is corresponding to the second memory channel, and before the sending the second memory access request through the second memory channel, the method further includes sending, by the first scheduler, a memory channel occupation request to the second scheduler, to request to occupy the second memory channel corresponding to the second scheduler to send the second memory access request, and receiving a confirmation response that is returned by the second scheduler in response to the memory channel occupation request. 
         [0021]    With reference to the third aspect or the first possible implementation manner or second possible implementation manner of the third aspect, in a third possible implementation manner, each scheduler has multiple paths, and establishes connections to all memory channels using the multiple paths. 
         [0022]    According to a fourth aspect, an embodiment of the present disclosure provides a memory controller, applied to a memory system, where the memory controller includes at least a first scheduler and a second scheduler, the first scheduler is corresponding to a first memory channel, the second scheduler is corresponding to a second memory channel, and each memory channel is corresponding to one memory module, and the memory system includes multiple memory modules, where a transmission link is established between the multiple memory modules, and a transmission link is established between the first scheduler and the second scheduler. The first scheduler is configured to acquire a quantity of to-be-sent memory access requests in the second scheduler, and the first scheduler is further configured to receive a memory access request, and send the memory access request through the second memory channel corresponding to the second scheduler. 
         [0023]    In a first possible implementation manner, the first scheduler is configured to receive at least two memory access requests, and the at least two memory access requests include a first memory access request and a second memory access request, and the first scheduler is further configured to, when the second memory access request is in a to-be-sent state, if the second memory channel corresponding to the second scheduler is in an idle state, send the second memory access request through the second memory channel corresponding to the second scheduler. 
         [0024]    With reference to the first possible implementation manner, in a second possible implementation manner, the first scheduler is further configured to send a memory channel occupation request to the second scheduler, to request to occupy the second memory channel corresponding to the second scheduler to send the second memory access request, and the first scheduler is further configured to receive a confirmation response that is returned by the second scheduler in response to the memory channel occupation request. 
         [0025]    With reference to the second possible implementation manner, in a third possible implementation manner, a destination address of the second memory access request received by the first scheduler is located in a memory module corresponding to the first memory channel. 
         [0026]    With reference to the fourth aspect or the first possible implementation manner, or second possible implementation manner, or third possible implementation manner of the fourth aspect, in a fourth possible implementation manner, the first scheduler has at least two paths, and establishes connections to the first memory channel and the second memory channel using the at least two paths. 
         [0027]    According to a fifth aspect, an embodiment of the present disclosure provides a memory controller, where the memory controller includes at least a first scheduler and a second scheduler, the first scheduler is corresponding to a first memory channel, the second scheduler is corresponding to a second memory channel, and each memory channel is corresponding to one memory module, and the memory controller includes multiple memory modules, where a transmission link is established between the multiple memory modules, and the first scheduler is configured to receive at least two memory access requests, including a first memory access request and a second memory access request, and send the first memory access request through the first memory channel, and send the second memory access request through the second memory channel. 
         [0028]    In a first possible implementation manner, the first scheduler is configured to send the second memory access request through the second memory channel when the second memory channel is in an idle state. 
         [0029]    With reference to the first possible implementation manner, in a second possible implementation manner, the first scheduler is further configured to send a memory channel occupation request to the second scheduler, to request to occupy the second memory channel corresponding to the second scheduler to send the second memory access request; and receive a confirmation response that is returned by the second scheduler in response to the memory channel occupation request. 
         [0030]    With reference to the second possible implementation manner, in a third possible implementation manner, a destination address of the second memory access request received by the first scheduler is located in a memory module corresponding to the first memory channel. 
         [0031]    With reference to the fifth aspect or the first possible implementation manner, or second possible implementation manner, or third possible implementation manner of the fifth aspect, in a fourth possible implementation manner, each scheduler in the memory controller has multiple paths, and establishes connections to all memory channels using the multiple paths. 
         [0032]    According to a sixth aspect, an embodiment of the present disclosure provides a memory controller, where the memory controller includes at least a first memory channel and a second memory channel, and each memory channel is corresponding to one memory module, and the memory controller includes multiple memory modules, where a transmission link is established between the multiple memory modules. The memory controller is configured to receive at least two memory access requests, including a first memory access request and a second memory access request, where destination addresses of the first memory access request and the second memory access request are located in a memory module corresponding to the first memory channel, and the memory controller is further configured to send the first memory access request through the first memory channel, and send the second memory access request through the second memory channel. 
         [0033]    In a first possible implementation manner, the memory controller is further configured to: when the second memory channel is in an idle state, send the second memory access request through the second memory channel. 
         [0034]    With reference to the first possible implementation manner, in a second possible implementation manner, the memory controller includes at least a first scheduler and a second scheduler, the first scheduler is corresponding to the first memory channel, and the second scheduler is corresponding to the second memory channel. The first scheduler is configured to send a memory channel occupation request to the second scheduler, to request to occupy the second memory channel corresponding to the second scheduler to send the second memory access request, and the first scheduler is further configured to receive a confirmation response that is returned by the second scheduler in response to the memory channel occupation request. 
         [0035]    With reference to the sixth aspect or the first possible implementation manner or second possible implementation manner of the sixth aspect, in a third possible implementation manner, each scheduler in the memory controller has multiple paths, and establishes connections to all memory channels using the multiple paths. 
         [0036]    According to a seventh aspect, an embodiment of the present disclosure provides a central processing unit (CPU), applied to a memory system, where the CPU includes a memory controller, the memory controller includes at least a first scheduler and a second scheduler, the first scheduler is corresponding to a first memory channel, the second scheduler is corresponding to a second memory channel, and each memory channel is corresponding to one memory module, and the memory system includes multiple memory modules, wherein a transmission link is established between the multiple memory modules, and a transmission link is established between the first scheduler and the second scheduler. The first scheduler is configured to acquire a quantity of to-be-sent memory access requests in the second scheduler, and the first scheduler is further configured to receive a memory access request, and send the memory access request through the second memory channel corresponding to the second scheduler. 
         [0037]    In a first possible implementation manner, the first scheduler is configured to receive at least two memory access requests, and the at least two memory access requests include a first memory access request and a second memory access request, and the first scheduler is further configured to, when the second memory access request is in a to-be-sent state, if the second memory channel corresponding to the second scheduler is in an idle state, send the second memory access request through the second memory channel corresponding to the second scheduler. 
         [0038]    With reference to the first possible implementation manner, in a second possible implementation manner, the first scheduler is further configured to send a memory channel occupation request to the second scheduler, to request to occupy the second memory channel corresponding to the second scheduler to send the second memory access request, and the first scheduler is further configured to receive a confirmation response that is returned by the second scheduler in response to the memory channel occupation request. 
         [0039]    With reference to the second possible implementation manner, in a third possible implementation manner, a destination address of the second memory access request received by the first scheduler is located in a memory module corresponding to the first memory channel, and the first memory channel is a memory channel corresponding to the first scheduler. 
         [0040]    With reference to the seventh aspect or the first possible implementation manner, or second possible implementation manner, or third possible implementation manner of the seventh aspect, in a fourth possible implementation manner, the first scheduler has at least two paths, and establishes connections to the first memory channel and the second memory channel using the at least two paths. 
         [0041]    According to an eighth aspect, an embodiment of the present disclosure provides a CPU, including a memory controller, where the memory controller includes at least a first scheduler and a second scheduler, the first scheduler is corresponding to a first memory channel, the second scheduler is corresponding to a second memory channel, and each memory channel is corresponding to one memory module; and the memory controller includes multiple memory modules, where a transmission link is established between the multiple memory modules, and the first scheduler is configured to receive at least two memory access requests, including a first memory access request and a second memory access request, and send the first memory access request through the first memory channel, and send the second memory access request through the second memory channel. 
         [0042]    In a first possible implementation manner, the first scheduler is configured to send the second memory access request through the second memory channel when the second memory channel is in an idle state. 
         [0043]    With reference to the first possible implementation manner, in a second possible implementation manner, the first scheduler is further configured to send a memory channel occupation request to the second scheduler, to request to occupy the second memory channel corresponding to the second scheduler to send the second memory access request, and receive a confirmation response that is returned by the second scheduler in response to the memory channel occupation request. 
         [0044]    With reference to the second possible implementation manner, in a third possible implementation manner, a destination address of the second memory access request received by the first scheduler is located in a memory module corresponding to the first memory channel. 
         [0045]    With reference to the eighth aspect or the first possible implementation manner, or second possible implementation manner, or third possible implementation manner of the eighth aspect, in a fourth possible implementation manner, each scheduler in the memory controller has multiple paths, and establishes connections to all memory channels using the multiple paths. 
         [0046]    According to a ninth aspect, an embodiment of the present disclosure provides a CPU, including a memory controller, where the memory controller includes at least a first memory channel and a second memory channel, and each memory channel is corresponding to one memory module, and the memory controller includes multiple memory modules, where a transmission link is established between the multiple memory modules. The memory controller is configured to receive at least two memory access requests, including a first memory access request and a second memory access request, where destination addresses of the first memory access request and the second memory access request are located in a memory module corresponding to the first memory channel, and the memory controller is further configured to send the first memory access request through the first memory channel, and send the second memory access request through the second memory channel. 
         [0047]    In a first possible implementation manner, the memory controller is further configured to send the second memory access request through the second memory channel when the second memory channel is in an idle state. 
         [0048]    With reference to the first possible implementation manner, in a second possible implementation manner, the memory controller includes at least a first scheduler and a second scheduler, the first scheduler is corresponding to the first memory channel, and the second scheduler is corresponding to the second memory channel. The first scheduler is configured to send a memory channel occupation request to the second scheduler, to request to occupy the second memory channel corresponding to the second scheduler to send the second memory access request, and the first scheduler is further configured to receive a confirmation response that is returned by the second scheduler in response to the memory channel occupation request. 
         [0049]    With reference to the ninth aspect or the first possible implementation manner or second possible implementation manner of the ninth aspect, in a third possible implementation manner, each scheduler in the memory controller has multiple paths, and establishes connections to all memory channels using the multiple paths. 
         [0050]    According to the memory module access method and apparatus provided in the embodiments of the present disclosure, when multiple memory access requests are received, the multiple received memory access requests may be sent through multiple memory channels. Using the method provided in the embodiments of the present disclosure, even if the multiple received memory access requests are distributed in an unbalanced manner among the multiple memory channels, the multiple received memory access requests can be sent through another memory channel in an idle state, thereby improving the utilization of bandwidth resources, and improving a memory access bandwidth. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0051]    To describe the technical solutions in the embodiments of the present disclosure or in the prior art more clearly, the following briefly introduces the accompanying drawings required for describing the embodiments or the prior art. The accompanying drawings in the following description show merely some embodiments of the present disclosure, and a person of ordinary skill in the art may still derive other drawings from these accompanying drawings without creative efforts. 
           [0052]      FIG. 1  and  FIG. 2  are schematic flowcharts of a memory module access method according to Embodiment 1 of the present disclosure; 
           [0053]      FIG. 3  and  FIG. 4  are structural block diagrams of a memory controller according to Embodiment 2 of the present disclosure; 
           [0054]      FIG. 5  and  FIG. 6  are structural block diagrams of a CPU according to Embodiment 3 of the present disclosure; 
           [0055]      FIG. 7  and  FIG. 8  are schematic flowcharts of a memory module access method according to Embodiment 4 of the present disclosure; 
           [0056]      FIG. 9  is a structural block diagram of a memory controller according to Embodiment 5 of the present disclosure; 
           [0057]      FIG. 10  is a structural block diagram of a CPU according to Embodiment 6 of the present disclosure; 
           [0058]      FIG. 11  and  FIG. 12  are schematic flowcharts of a memory module access method according to Embodiment 7 of the present disclosure; 
           [0059]      FIG. 13  is a structural block diagram of a memory controller according to Embodiment 8 of the present disclosure; 
           [0060]      FIG. 14  and  FIG. 15  are structural block diagrams of a CPU according to Embodiment 9 of the present disclosure; 
           [0061]      FIG. 16  is a structural diagram of a dual-channel memory system according to Embodiment 10 of the present disclosure; and 
           [0062]      FIG. 17  is a structural diagram of a three-channel memory system according to Embodiment 11 of the present disclosure. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0063]    The following clearly describes the technical solutions in the embodiments of the present disclosure with reference to the accompanying drawings in the embodiments of the present disclosure. The described embodiments are merely some but not all of the embodiments of the present disclosure. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure. 
       Embodiment 1 
       [0064]    This embodiment of the present disclosure provides a memory module access method, applied to a memory system, where the memory system includes at least a first scheduler and a second scheduler, the first scheduler is corresponding to a first memory channel, the second scheduler is corresponding to a second memory channel, and each memory channel is corresponding to one memory module, and the memory system includes multiple memory modules, where a transmission link is established between the multiple memory modules, and a transmission link is established between the first scheduler and the second scheduler. 
         [0065]    As shown in  FIG. 1 , the method includes the following steps. 
         [0066]    Step  101 : The first scheduler acquires a quantity of to-be-sent memory access requests in the second scheduler. 
         [0067]    Step  102 : The first scheduler receives a memory access request, and sends the memory access request through the second memory channel corresponding to the second scheduler. 
         [0068]    In this embodiment, the memory system includes multiple schedulers, and a communication link is established between the multiple schedulers such that each scheduler can acquire a quantity of to-be-sent memory access requests in another scheduler. Therefore, after receiving a memory access request, each scheduler can determine an idle memory channel and send the memory access request through the idle memory channel. 
         [0069]    Further, on the basis of the method shown in  FIG. 1 , this embodiment of the present disclosure further provides a more detailed memory module access method. As shown in  FIG. 2 , the method includes the following steps. 
         [0070]    Step  201 : The first scheduler acquires a quantity of to-be-sent memory access requests in another scheduler in real time, where the first scheduler is any scheduler in the multiple schedulers, and the other scheduler is the remaining scheduler in the multiple schedulers except the first scheduler. 
         [0071]    Step  202 : The first scheduler receives at least two memory access requests, where the at least two memory access requests include a first memory access request and a second memory access request. 
         [0072]    It should be noted that, generally, destination addresses of the memory access requests received by the first scheduler are all located in a memory module corresponding to the first scheduler, that is, if the memory channel corresponding to the first scheduler is marked as a first memory channel, the destination addresses of both the first memory access request and the second memory access request are located in a memory module corresponding to the first memory channel. 
         [0073]    Step  203 : The first scheduler sends the first memory access request through the first memory channel, and the second memory access request is in a to-be-sent state. 
         [0074]    Step  204 : The first scheduler queries a state of a memory channel corresponding to the other scheduler, to determine an auxiliary scheduler, where a memory channel corresponding to the auxiliary scheduler is in an idle state. 
         [0075]    Furthermore, the first scheduler may determine an auxiliary scheduler using the following method. Querying, by the first scheduler, a quantity of to-be-sent memory access requests in the other scheduler, and determining a scheduler in which a quantity of to-be-sent memory access requests is 0 as the auxiliary scheduler. 
         [0076]    For ease of understanding, in this embodiment, the determined auxiliary scheduler is marked as a second scheduler, a quantity of current to-be-sent memory access requests in the second scheduler is 0, and a memory channel corresponding to the second scheduler is in an idle state. 
         [0077]    It should be noted that, that the quantity of current to-be-sent memory access requests in the second scheduler is 0 indicates that the memory channel corresponding to the second scheduler is in an absolute idle state. It should be emphasized that, as an optional solution, when the memory channel corresponding to the second scheduler is in a relative idle state (for example, the quantity of to-be-sent memory access requests in the second scheduler is not 0, but the quantity of to-be-sent memory access requests in the second scheduler is much smaller than a quantity of to-be-sent memory access requests in the first scheduler), the first scheduler may still determine the second scheduler as an auxiliary scheduler, and send some of the received memory access requests through the memory channel corresponding to the second scheduler. Using such a method, when receiving a large quantity of memory access requests, the first scheduler may transfer some of to-be-sent memory access requests in the first scheduler to the auxiliary scheduler in time such that the first scheduler can buffer more memory access requests, thereby improving a communication capacity of the memory system. 
         [0078]    Step  205 : The first scheduler sends a memory channel occupation request to the second scheduler, to request to occupy the second memory channel corresponding to the second scheduler to send the second memory access request. 
         [0079]    Step  206 : The second scheduler determines that the memory channel corresponding to the second scheduler is in an idle state, allows the first scheduler to occupy the second memory channel corresponding to the second scheduler, and sends a confirmation response to the first scheduler in response to the memory channel occupation request. 
         [0080]    Step  207 : The first scheduler receives the confirmation response that is returned by the second scheduler in response to the memory channel occupation request. 
         [0081]    Step  208 : The first scheduler sends the second memory access request through the second memory channel corresponding to the second scheduler. 
         [0082]    Generally, when receiving multiple memory access requests in one scheduling timeslot, the first scheduler sends the first received memory access request through the memory channel corresponding to the first scheduler, and sends the second received memory access request through a memory channel corresponding to another scheduler. 
         [0083]    It should be noted that, as an optional solution, the first scheduler may also send the first received memory access request through a memory channel corresponding to another scheduler, and send the second received memory access request through the memory channel corresponding to the first scheduler. As another optional solution, provided that enough idle memory channels exist, the first scheduler may send the multiple received memory access requests through memory channels corresponding to other schedulers preferentially. According to the method provided in this embodiment, a memory access request received by any scheduler may be sent through any idle memory channel, and a specific method for allocating memory channels is not limited in this embodiment. 
         [0084]    Step  209 : A memory module corresponding to the second scheduler receives the second memory access request, and sends, according to a destination address in the second memory access request and through a transmission link between memory modules, the second memory access request to a destination memory module, that is, a memory module corresponding to the first scheduler. 
         [0085]    It should be noted that, in this embodiment, each scheduler has multiple paths, and establishes connections to the multiple memory channels using the multiple paths such that each scheduler can send a memory access request through a memory channel corresponding to another scheduler. 
         [0086]    It should be emphasized that, the memory module access method provided in this embodiment may be applied to any multichannel memory system with interconnection paths. 
         [0087]    As a preferred solution, multiple schedulers in this embodiment may be integrated to be one general scheduler, thereby further improving a connection degree among multiple memory channels. The general scheduler schedules memory access requests on all the memory channels in order to maximize the utilization of the memory channels. 
         [0088]    According to the memory module access method provided in this embodiment of the present disclosure, each scheduler may acquire a quantity of to-be-sent memory access requests in another scheduler, and when receiving multiple memory access requests, may send the multiple received memory access requests through multiple memory channels. According to the method provided in this embodiment of the present disclosure, when multiple memory access requests are received, the multiple received memory access requests can be allocated to multiple memory channels for sending, thereby improving the utilization of bandwidth resources, and improving a memory access bandwidth. 
       Embodiment 2 
       [0089]    This embodiment of the present disclosure provides a memory controller, which is applied to a memory system, and can implement the memory module access method shown in  FIG. 1  and  FIG. 2 . As shown in  FIG. 3 , the memory controller includes at least a first scheduler  31  and a second scheduler  32 , the first scheduler  31  is corresponding to a first memory channel, the second scheduler  32  is corresponding to a second memory channel, and each memory channel is corresponding to one memory module, and the memory system includes multiple memory modules, where a transmission link is established between the multiple memory modules, and a transmission link is established between the first scheduler  31  and the second scheduler  32 . 
         [0090]    The first scheduler  31  is configured to acquire a quantity of to-be-sent memory access requests in the second scheduler. 
         [0091]    The first scheduler  31  is further configured to receive a memory access request, and send the memory access request through the second memory channel corresponding to the second scheduler. 
         [0092]    It should be noted that, the first scheduler  31  and the second scheduler  32  in  FIG. 3  are merely used as an example for description. In an actual application, the memory controller includes multiple schedulers. As shown in  FIG. 4 , the memory controller may further include multiple schedulers such as a third scheduler  33 , a fourth scheduler  34 , and the like. A communication link is established between schedulers in the memory system such that each scheduler can acquire a quantity of to-be-sent memory access requests in another scheduler. In this way, after receiving a memory access request, each scheduler can determine an idle memory channel and send the memory access request through the idle memory channel. 
         [0093]    Furthermore, the first scheduler  31  is configured to receive at least two memory access requests, where the at least two memory access requests include a first memory access request and a second memory access request. 
         [0094]    The first scheduler  31  is further configured to send the second memory access request through the second memory channel corresponding to the second scheduler  32  when the second memory access request is in a to-be-sent state and if the second memory channel corresponding to the second scheduler  32  is in an idle state. 
         [0095]    The first scheduler  31  is further configured to send a memory channel occupation request to the second scheduler  32 , to request to occupy the second memory channel corresponding to the second scheduler  32  to send the second memory access request, and the first scheduler  31  is further configured to receive a confirmation response that is returned by the second scheduler  32  in response to the memory channel occupation request. 
         [0096]    Generally, when the first scheduler  31  receives multiple memory access requests in one scheduling timeslot, the first scheduler  31  sends the first received memory access request through the memory channel corresponding to the first scheduler  31 , and sends the second received memory access request through a memory channel corresponding to another scheduler. 
         [0097]    It should be noted that, as an optional solution, the first scheduler  31  may also send the first received memory access request through a memory channel corresponding to another scheduler, and send the second received memory access request through the memory channel corresponding to the first scheduler  31 . As another optional solution, provided that enough idle memory channels exist, the first scheduler  31  may send the multiple received memory access requests through memory channels corresponding to other schedulers preferentially. According to the memory controller provided in this embodiment, a memory access request received by any scheduler may be sent through any idle memory channel, and a specific method for allocating memory channels is not limited in this embodiment. 
         [0098]    A destination address of the second memory access request received by the first scheduler  31  is located in a memory module corresponding to the first memory channel. 
         [0099]    It should be noted that, in this embodiment, each scheduler has multiple paths, and establishes connections to the multiple memory channels using the multiple paths such that each scheduler can send a memory access request through a memory channel corresponding to another scheduler. For example, the first scheduler  31  has at least two paths, and establishes connections to the first memory channel and the second memory channel using the at least two paths. 
         [0100]    It should be stressed that, the memory controller provided in this embodiment may be applied to any multichannel memory system with interconnection paths. 
         [0101]    As a preferred solution, multiple schedulers in the memory controller may be integrated to be one general scheduler, thereby further improving a connection degree among multiple memory channels. The general scheduler schedules memory access requests on all the memory channels in order to maximize the utilization of the memory channels. 
         [0102]    Each scheduler in the memory controller provided in this embodiment of the present disclosure may acquire a quantity of to-be-sent memory access requests in another scheduler, and when receiving multiple memory access requests, may send the multiple received memory access requests through multiple memory channels. With the memory controller provided in this embodiment of the present disclosure, when multiple memory access requests are received, the multiple received memory access requests can be allocated to multiple memory channels for sending, thereby improving the utilization of bandwidth resources, and improving a memory access bandwidth. 
       Embodiment 3 
       [0103]    This embodiment of the present disclosure provides a CPU, which is applied to a memory system, and can implement the method shown in the foregoing  FIG. 1  and  FIG. 2 . As shown in  FIG. 5 , the CPU includes a memory controller  50 , where the memory controller  50  includes a first scheduler  51  and a second scheduler  52 . The first scheduler  51  is corresponding to a first memory channel, the second scheduler  52  is corresponding to a second memory channel, and each memory channel is corresponding to one memory module, and the memory system includes multiple memory modules, where a transmission link is established between the multiple memory modules, and a transmission link is established between the first scheduler  51  and the second scheduler  52 . 
         [0104]    Further, the first scheduler  51  is configured to acquire a quantity of to-be-sent memory access requests in the second scheduler  52 . 
         [0105]    The first scheduler  51  is further configured to receive a memory access request, and send the memory access request through the second memory channel corresponding to the second scheduler. 
         [0106]    It should be noted that, the first scheduler  51  and the second scheduler  52  in  FIG. 5  are merely used as an example for description. In an actual application, the memory controller includes multiple schedulers. As shown in  FIG. 6 , the memory controller may further include multiple schedulers such as a third scheduler  53 , a fourth scheduler  54 , and the like. A communication link is established between schedulers in the memory system such that each scheduler can acquire a quantity of to-be-sent memory access requests in another scheduler. In this way, after receiving a memory access request, each scheduler can determine an idle memory channel and send the memory access request through the idle memory channel. 
         [0107]    Furthermore, the first scheduler  51  is configured to receive at least two memory access requests, where the at least two memory access requests include a first memory access request and a second memory access request. 
         [0108]    The first scheduler  51  is further configured to send the second memory access request through the memory channel corresponding to the second scheduler  52  when the second memory access request is in a to-be-sent state, if the memory channel corresponding to the second scheduler  52  is in an idle state. 
         [0109]    The first scheduler  51  is further configured to send a memory channel occupation request to the second scheduler  52 , to request to occupy the second memory channel corresponding to the second scheduler  52  to send the second memory access request. The first scheduler  51  is further configured to receive a confirmation response that is returned by the second scheduler  52  in response to the memory channel occupation request. 
         [0110]    A destination address of the second memory access request received by the first scheduler  51  is located in a memory module corresponding to the first memory channel. 
         [0111]    Generally, when receiving multiple memory access requests in one scheduling timeslot, the first scheduler sends the first received memory access request through the memory channel corresponding to the first scheduler, and sends the second received memory access request through a memory channel corresponding to another scheduler. 
         [0112]    It should be noted that, as an optional solution, the first scheduler may also send the first received memory access request through a memory channel corresponding to another scheduler, and send the second received memory access request through the memory channel corresponding to the first scheduler. As another optional solution, provided that enough idle memory channels exist, the first scheduler may send the multiple received memory access requests through memory channels corresponding to other schedulers preferentially. According to the CPU provided in this embodiment, a memory access request received by any scheduler may be sent through any idle memory channel, and a specific method for allocating memory channels is not limited in this embodiment. 
         [0113]    It should be noted that, in this embodiment, each scheduler in the memory controller has multiple paths, and establishes connections to the multiple memory channels using the multiple paths. For example, the first scheduler has at least two paths, and establishes connections to the first memory channel and the second memory channel using the at least two paths. 
         [0114]    It should be stressed that, the CPU provided in this embodiment may be applied to any multichannel memory system with interconnection paths. 
         [0115]    As a preferred solution, multiple schedulers in the memory controller  50  may be integrated to be one general scheduler, thereby further improving a connection degree among multiple memory channels. The general scheduler schedules memory access requests on all the memory channels in order to maximize the utilization of the memory channels. 
         [0116]    The CPU provided in this embodiment of the present disclosure includes a memory controller. Each scheduler in the memory controller may acquire a quantity of to-be-sent memory access requests in another scheduler, and when receiving multiple memory access requests, may send the multiple received memory access requests through multiple memory channels. With the CPU provided in this embodiment of the present disclosure, when multiple memory access requests are received, the multiple received memory access requests can be allocated to multiple memory channels for sending, thereby improving the utilization of bandwidth resources, and improving a memory access bandwidth. 
       Embodiment 4 
       [0117]    This embodiment of the present disclosure provides a memory module access method, applied to a memory system, where the memory system includes at least a first scheduler and a second scheduler, the first scheduler is corresponding to a first memory channel, the second scheduler is corresponding to a second memory channel, and each memory channel is corresponding to one memory module, and the memory system includes multiple memory modules, where a transmission link is established between the multiple memory modules, and a transmission link is established between the first scheduler and the second scheduler. 
         [0118]    As shown in  FIG. 7 , the method includes the following steps. 
         [0119]    Step  701 : The first scheduler receives at least two memory access requests, including a first memory access request and a second memory access request. 
         [0120]    Step  702 : The first scheduler sends the first memory access request through the first memory channel, and sends the second memory access request through the second memory channel. 
         [0121]    According to the method in this embodiment, the memory access requests received by multiple schedulers can be shared using multiple memory channels of a memory system, thereby improving the utilization of bandwidth resources of the memory channels. 
         [0122]    Further, on the basis of the method shown in  FIG. 7 , this embodiment of the present disclosure provides a more detailed memory module access method. As shown in  FIG. 8 , the method includes the following steps. 
         [0123]    Step  801 : The first scheduler receives at least two memory access requests, where the at least two memory access requests include a first memory access request and a second memory access request. 
         [0124]    It should be noted that, generally, destination addresses of the memory access requests received by the first scheduler are all located in a memory module corresponding to the first scheduler, that is, if the memory channel corresponding to the first scheduler is marked as a first memory channel, the destination addresses of both the first memory access request and the second memory access request are located in a memory module corresponding to the first memory channel. 
         [0125]    Step  802 : The first scheduler sends the first memory access request through the first memory channel, and the second memory access request is in a to-be-sent state. 
         [0126]    Step  803 : The first scheduler sends a memory channel occupation request to the second scheduler, to request to occupy the second memory channel corresponding to the second scheduler to send the second memory access request. 
         [0127]    It should be noted that, the second scheduler is any scheduler in multiple schedulers in the memory system. When receiving multiple memory access requests, the first scheduler may send a memory channel occupation request to all schedulers in the memory system. In this embodiment, the second scheduler is used as an example for specific description. 
         [0128]    Step  804 : The second scheduler detects whether the memory channel corresponding to the second scheduler is in an idle state. If the second scheduler is in the idle state, perform step  805 , or if the second scheduler is not in the idle state, perform step  809 . 
         [0129]    Step  805 : The second scheduler allows the first scheduler to occupy the second memory channel corresponding to the second scheduler, and sends a confirmation response to the first scheduler in response to the memory channel occupation request. 
         [0130]    Step  806 : The first scheduler receives the confirmation response that is returned by the second scheduler in response to the memory channel occupation request. 
         [0131]    Step  807 : The first scheduler sends the second memory access request through the second memory channel corresponding to the second scheduler. 
         [0132]    Generally, when receiving multiple memory access requests in one scheduling timeslot, the first scheduler sends the first received memory access request through the memory channel corresponding to the first scheduler, and sends the second received memory access request through a memory channel corresponding to another scheduler. 
         [0133]    It should be noted that, as an optional solution, the first scheduler may also send the first received memory access request through a memory channel corresponding to another scheduler, and send the second received memory access request through the memory channel corresponding to the first scheduler. As another optional solution, provided that enough idle memory channels exist, the first scheduler may send the multiple received memory access requests through memory channels corresponding to other schedulers preferentially. According to the method provided in this embodiment, a memory access request received by any scheduler may be sent through any idle memory channel, and a specific method for allocating memory channels is not limited in this embodiment. 
         [0134]    Step  808 : A memory module corresponding to the second scheduler receives the second memory access request, and sends, according to a destination address in the second memory access request and through a transmission link between memory modules, the second memory access request to a destination memory module, that is, a memory module corresponding to the first scheduler. 
         [0135]    Step  809 : The second scheduler rejects the memory channel occupation request sent by the first scheduler. 
         [0136]    It should be noted that, in this embodiment, each scheduler has multiple paths, and establishes connections to the multiple memory channels using the multiple paths such that each scheduler can send a memory access request through a memory channel corresponding to another scheduler. 
         [0137]    It should be emphasized that, the memory module access method provided in this embodiment may be applied to any multichannel memory system with interconnection paths. 
         [0138]    As a preferred solution, multiple schedulers in this embodiment may be integrated to be one general scheduler, thereby further improving a connection degree among multiple memory channels. The general scheduler schedules memory access requests on all the memory channels in order to maximize the utilization of the memory channels. 
         [0139]    According to the memory module access method provided in this embodiment of the present disclosure, when multiple memory access requests are received, the memory access requests received by multiple schedulers can be shared using multiple memory channels of a memory system, and the multiple memory access requests can be sent through multiple memory channels, thereby improving the utilization of bandwidth resources of the memory channels, and improving a memory access bandwidth. 
       Embodiment 5 
       [0140]    This embodiment of the present disclosure provides a memory controller, which can implement the methods shown in  FIG. 7  and  FIG. 8 . As shown in  FIG. 9 , the memory controller includes at least a first scheduler  91  and a second scheduler  92 , where the first scheduler  91  is corresponding to a first memory channel, the second scheduler  92  is corresponding to a second memory channel, each memory channel is corresponding to one or more memory modules, and a transmission link is established between the memory modules. 
         [0141]    The first scheduler  91  is configured to receive at least two memory access requests, including a first memory access request and a second memory access request, and send the first memory access request through the first memory channel, and send the second memory access request through the second memory channel. 
         [0142]    Furthermore, the first scheduler  91  is configured to send the second memory access request through the second memory channel when the second memory channel is in an idle state. 
         [0143]    The first scheduler  91  is further configured to send a memory channel occupation request to the second scheduler  92 , to request to occupy the second memory channel corresponding to the second scheduler  92  to send the second memory access request, and receive a confirmation response that is returned by the second scheduler  92  in response to the memory channel occupation request. 
         [0144]    A destination address of the second memory access request received by the first scheduler  91  is located in a memory module corresponding to the first memory channel. 
         [0145]    Generally, when receiving multiple memory access requests in one scheduling timeslot, the first scheduler  91  sends the first received memory access request through the memory channel corresponding to the first scheduler  91 , and sends the second received memory access request through a memory channel corresponding to another scheduler. 
         [0146]    It should be noted that, as an optional solution, the first scheduler  91  may also send the first received memory access request through a memory channel corresponding to another scheduler, and send the second received memory access request through the memory channel corresponding to the first scheduler  91 . As another optional solution, provided that enough idle memory channels exist, the first scheduler  91  may send the multiple received memory access requests through memory channels corresponding to other schedulers preferentially. According to the memory controller provided in this embodiment, a memory access request received by any scheduler may be sent through any idle memory channel, and a specific method for allocating memory channels is not limited in this embodiment. 
         [0147]    Furthermore, each scheduler in the memory controller has multiple paths, and establishes connections to all memory channels using the multiple paths. 
         [0148]    It should be stressed that, the memory controller provided in this embodiment may be applied to any multichannel memory system with interconnection paths. 
         [0149]    As a preferred solution, multiple schedulers in the memory controller may be integrated to be one general scheduler, thereby further improving a connection degree among multiple memory channels. The general scheduler schedules memory access requests on all the memory channels in order to maximize the utilization of the memory channels. 
         [0150]    In the memory controller provided in this embodiment of the present disclosure, when multiple memory access requests are received, the memory access requests received by multiple schedulers can be shared using multiple memory channels of a memory system, and the multiple memory access requests can be sent through multiple memory channels, thereby improving the utilization of bandwidth resources of the memory channels, and improving a memory access bandwidth. 
       Embodiment 6 
       [0151]    This embodiment provides a CPU, which can implement the methods shown in  FIG. 7  and  FIG. 8 . As shown in  FIG. 10 , the CPU includes a memory controller  1000 , where the memory controller  1000  includes at least a first scheduler  1001  and a second scheduler  1002 , the first scheduler is corresponding to a first memory channel, the second scheduler is corresponding to a second memory channel, each scheduler is corresponding to a memory channel, and each memory channel is corresponding to one or more memory modules; and the memory controller includes multiple memory modules, where a transmission link is established in advance between the multiple memory modules. 
         [0152]    The first scheduler  1001  is configured to receive at least two memory access requests, including a first memory access request and a second memory access request, and send the first memory access request through the first memory channel, and send the second memory access request through the second memory channel. 
         [0153]    Furthermore, the first scheduler  1001  is configured to send the second memory access request through the second memory channel when the second memory channel is in an idle state. 
         [0154]    Generally, when receiving multiple memory access requests in one scheduling timeslot, the first scheduler  1001  sends the first received memory access request through the memory channel corresponding to the first scheduler  1001 , and sends the second received memory access request through a memory channel corresponding to another scheduler. 
         [0155]    It should be noted that, as an optional solution, the first scheduler  1001  may also send the first received memory access request through a memory channel corresponding to another scheduler, and send the second received memory access request through the memory channel corresponding to the first scheduler  1001 . As another optional solution, provided that enough idle memory channels exist, the first scheduler  1001  may send the multiple received memory access requests through memory channels corresponding to other schedulers preferentially. According to the CPU provided in this embodiment, a memory access request received by any scheduler may be sent through any idle memory channel, and a specific method for allocating memory channels is not limited in this embodiment. 
         [0156]    The first scheduler  1001  is further configured to send a memory channel occupation request to the second scheduler  1002 , to request to occupy the second memory channel corresponding to the second scheduler  1002  to send the second memory access request; and receive a confirmation response that is returned by the second scheduler  1002  in response to the memory channel occupation request. 
         [0157]    A destination address of the second memory access request received by the first scheduler  1001  is located in a memory module corresponding to the first memory channel. 
         [0158]    In this embodiment, each scheduler in the memory controller  1000  has multiple paths, and establishes connections to all memory channels using the multiple paths. 
         [0159]    It should be stressed that, the memory controller provided in this embodiment may be applied to any multichannel memory system with interconnection paths. 
         [0160]    As a preferred solution, multiple schedulers in the memory controller may be integrated to be one general scheduler, thereby further improving a connection degree among multiple memory channels. The general scheduler schedules memory access requests on all the memory channels in order to maximize the utilization of the memory channels. 
         [0161]    According to the CPU provided in this embodiment of the present disclosure, when multiple memory access requests are received, the memory access requests received by multiple schedulers can be shared using multiple memory channels of a memory system, and the multiple memory access requests can be sent through multiple memory channels, thereby improving the utilization of bandwidth resources of the memory channels, and improving a memory access bandwidth. 
       Embodiment 7 
       [0162]    This embodiment of the present disclosure provides a memory module access method, applied to a memory system, where the memory system includes at least a first memory channel and a second memory channel, and each memory channel is corresponding to one memory module, and the memory system includes multiple memory modules, where a transmission link is established between the multiple memory modules. 
         [0163]    As shown in  FIG. 11 , the method includes the following steps. 
         [0164]    Step  1101 : A first scheduler receives at least two memory access requests, including a first memory access request and a second memory access request, where destination addresses of both the first memory access request and the second memory access request are located in a memory module corresponding to the first memory channel. 
         [0165]    Step  1102 : Send the first memory access request through the first memory channel, and send the second memory access request through the second memory channel. 
         [0166]    According to the memory module access method provided in this embodiment, when receiving multiple memory access requests, the first scheduler may send the multiple received memory access requests through a memory channel corresponding to another scheduler (for example, a second scheduler in this embodiment). 
         [0167]    Further, on the basis of the method shown in  FIG. 11 , this embodiment of the present disclosure further provides a more detailed memory module access method. As shown in  FIG. 12 , the method includes the following steps. 
         [0168]    Step  1201 : A first scheduler receives at least two memory access requests, including a first memory access request and a second memory access request, where destination addresses of both the first memory access request and the second memory access request are located in a memory module corresponding to the first memory channel. 
         [0169]    Step  1202 : The first scheduler sends the first memory access request through the first memory channel, and the second memory access request is in a to-be-sent state. 
         [0170]    Step  1203 : The first scheduler sends a memory channel occupation request to a second scheduler, to request to occupy the second memory channel corresponding to the second scheduler to send the second memory access request. 
         [0171]    It should be noted that, the second scheduler is any scheduler in multiple schedulers in the memory system. When receiving multiple memory access requests, the first scheduler may send a memory channel occupation request to all schedulers in the memory system. In this embodiment, the second scheduler is used as an example for specific description. 
         [0172]    Step  1204 : The second scheduler detects whether the memory channel corresponding to the second scheduler is in an idle state. If the second scheduler is in the idle state, perform step  1205 , or if the second scheduler is not in the idle state, perform step  1209 . 
         [0173]    Step  1205 : The second scheduler allows the first scheduler to occupy the memory channel corresponding to the second scheduler, and sends a confirmation response to the first scheduler in response to the memory channel occupation request. 
         [0174]    Step  1206 : The first scheduler receives the confirmation response that is returned by the second scheduler in response to the memory channel occupation request. 
         [0175]    Step  1207 : The first scheduler sends the second memory access request through the second memory channel corresponding to the second scheduler. 
         [0176]    Generally, when receiving multiple memory access requests in one scheduling timeslot, the first scheduler sends the first received memory access request through the memory channel corresponding to the first scheduler, and sends the second received memory access request through a memory channel corresponding to another scheduler. 
         [0177]    It should be noted that, as an optional solution, the first scheduler may also send the first received memory access request through a memory channel corresponding to another scheduler, and send the second received memory access request through the memory channel corresponding to the first scheduler. As another optional solution, provided that enough idle memory channels exist, the first scheduler may send the multiple received memory access requests through memory channels corresponding to other schedulers preferentially. According to the method provided in this embodiment, a memory access request received by any scheduler may be sent through any idle memory channel, and a specific method for allocating memory channels is not limited in this embodiment. 
         [0178]    Step  1208 : A memory module corresponding to the second scheduler receives the second memory access request, and sends, according to a destination address in the second memory access request and through a transmission link between memory modules, the second memory access request to a destination memory module, that is, a memory module corresponding to the first scheduler. 
         [0179]    Step  1209 : The second scheduler rejects the memory channel occupation request sent by the first scheduler. 
         [0180]    It should be noted that, in this embodiment, each scheduler has multiple paths, and establishes connections to the multiple memory channels using the multiple paths such that each scheduler can send a memory access request through a memory channel corresponding to another scheduler. 
         [0181]    It should be stressed that, the memory module access method provided in this embodiment may be applied to any multichannel memory system with interconnection paths. 
         [0182]    As a preferred solution, multiple schedulers in this embodiment may be integrated to be one general scheduler, thereby further improving a connection degree among multiple memory channels. The general scheduler schedules memory access requests on all the memory channels in order to maximize the utilization of the memory channels. 
         [0183]    According to the memory module access method provided in this embodiment of the present disclosure, when receiving multiple memory access requests, a first scheduler may send the multiple received memory access requests through a memory channel corresponding to another scheduler (for example, a second scheduler), thereby improving the utilization of bandwidth resources of the memory channels, and improving a memory access bandwidth. 
       Embodiment 8 
       [0184]    This embodiment of the present disclosure provides a memory controller, which can implement the methods shown in  FIG. 10  and  FIG. 11 , where the memory controller includes at least a first memory channel and a second memory channel, and each memory channel is corresponding to one or more memory modules, and the memory controller includes multiple memory modules, where a transmission link is established between the multiple memory modules. 
         [0185]    Furthermore, the memory controller is configured to receive at least two memory access requests, including a first memory access request and a second memory access request, where destination addresses of the first memory access request and the second memory access request are located in a memory module corresponding to the first memory channel. 
         [0186]    The memory controller is further configured to send the first memory access request through the first memory channel, and send the second memory access request through the second memory channel. 
         [0187]    Furthermore, the memory controller is configured to send the second memory access request through the second memory channel when the second memory channel is in an idle state. 
         [0188]    As shown in  FIG. 13 , the memory controller includes at least a first scheduler  1301  and a second scheduler  1302 , where the first scheduler  1301  is corresponding to the first memory channel, and the second scheduler  1302  is corresponding to the second memory channel. 
         [0189]    The first scheduler  1301  is configured to send a memory channel occupation request to the second scheduler  1302 , to request to occupy the second memory channel corresponding to the second scheduler  1302  to send the second memory access request, and the first scheduler  1301  is further configured to receive a confirmation response that is returned by the second scheduler  1302  in response to the memory channel occupation request. 
         [0190]    Generally, when receiving multiple memory access requests in one scheduling timeslot, the first scheduler  1301  sends the first received memory access request through the memory channel corresponding to the first scheduler  1301 , and sends the second received memory access request through a memory channel corresponding to another scheduler. 
         [0191]    It should be noted that, as an optional solution, the first scheduler  1301  may also send the first received memory access request through a memory channel corresponding to another scheduler, and send the second received memory access request through the memory channel corresponding to the first scheduler  1301 . As another optional solution, provided that enough idle memory channels exist, the first scheduler  1301  may send the multiple received memory access requests through memory channels corresponding to other schedulers preferentially. According to the memory controller provided in this embodiment, a memory access request received by any scheduler may be sent through any idle memory channel, and a specific method for allocating memory channels is not limited in this embodiment. 
         [0192]    It should be noted that, each scheduler in the memory controller has multiple paths, and establishes connections to all memory channels using the multiple paths. 
         [0193]    It should be stressed that, the memory controller provided in this embodiment may be applied to any multichannel memory system with interconnection paths. 
         [0194]    As a preferred solution, multiple schedulers in the memory controller may be integrated to be one general scheduler, thereby further improving a connection degree among multiple memory channels. The general scheduler schedules memory access requests on all the memory channels in order to maximize the utilization of the memory channels. 
         [0195]    According to the memory controller provided in this embodiment of the present disclosure, when receiving multiple memory access requests, a first scheduler in the memory controller may send the multiple received memory access requests through a memory channel corresponding to another scheduler (for example, a second scheduler), thereby improving the utilization of bandwidth resources of the memory channels, and improving a memory access bandwidth. 
       Embodiment 9 
       [0196]    This embodiment of the present disclosure provides a CPU, which can implement the methods shown in  FIG. 10  and  FIG. 11 . As shown in  FIG. 14 , the CPU includes a memory controller  1400 , where the memory controller  1400  includes at least a first memory channel and a second memory channel, and each memory channel is corresponding to one or more memory modules, and the memory controller  1400  includes multiple memory modules, where a transmission link is established between the multiple memory modules. 
         [0197]    The memory controller  1400  is configured to receive at least two memory access requests, including a first memory access request and a second memory access request, where destination addresses of the first memory access request and the second memory access request are located in a memory module corresponding to the first memory channel. 
         [0198]    The memory controller  1400  is further configured to send the first memory access request through the first memory channel, and send the second memory access request through the second memory channel. 
         [0199]    Further, the memory controller  1400  is further configured to send the second memory access request through the second memory channel when the second memory channel is in an idle state. 
         [0200]    As shown in  FIG. 15 , the memory controller  1400  includes at least a first scheduler  1401  and a second scheduler  1402 , where the first scheduler  1401  is corresponding to the first memory channel, and the second scheduler  1402  is corresponding to the second memory channel. 
         [0201]    The first scheduler  1401  is configured to send a memory channel occupation request to the second scheduler  1402 , to request to occupy the second memory channel corresponding to the second scheduler  1402  to send the second memory access request, and the first scheduler  1401  is further configured to receive a confirmation response that is returned by the second scheduler  1402  in response to the memory channel occupation request. 
         [0202]    Generally, when receiving multiple memory access requests in one scheduling timeslot, the first scheduler  1401  sends the first received memory access request through the memory channel corresponding to the first scheduler  1401 , and sends the second received memory access request through a memory channel corresponding to another scheduler. 
         [0203]    It should be noted that, as an optional solution, the first scheduler  1401  may also send the first received memory access request through a memory channel corresponding to another scheduler, and send the second received memory access request through the memory channel corresponding to the first scheduler  1401 . As another optional solution, provided that enough idle memory channels exist, the first scheduler  1401  may send the multiple received memory access requests through memory channels corresponding to other schedulers preferentially. According to the CPU provided in this embodiment, a memory access request received by any scheduler may be sent through any idle memory channel, and a specific method for allocating memory channels is not limited in this embodiment. 
         [0204]    It should be noted that, in this embodiment, each scheduler in the memory controller  1400  has multiple paths, and establishes connections to all memory channels using the multiple paths. 
         [0205]    It should be stressed that, the memory controller provided in this embodiment may be applied to any multichannel memory system with interconnection paths. 
         [0206]    As a preferred solution, multiple schedulers in the memory controller may be integrated to be one general scheduler, thereby further improving a connection degree among multiple memory channels. The general scheduler schedules memory access requests on all the memory channels in order to maximize the utilization of the memory channels. 
         [0207]    The CPU provided in this embodiment of the present disclosure includes a memory controller. When receiving multiple memory access requests, a first scheduler in the memory controller may send the multiple received memory access requests through a memory channel corresponding to another scheduler (for example, a second scheduler), thereby improving the utilization of bandwidth resources of the memory channels, and improving a memory access bandwidth. 
       Embodiment 10 
       [0208]    For ease of understanding, in this embodiment, two schedulers are used as an example to describe the technical solutions provided in the present disclosure. 
         [0209]    This embodiment provides a memory module access method, which is applied to a memory system. As shown in  FIG. 16 , the memory system includes a scheduler 0 and a scheduler 1, where the scheduler 0 is corresponding to a memory channel 0, and the scheduler 1 is corresponding to a memory channel 1, and the memory channel 0 is connected to a memory module 0, a memory module 2, and a memory module 4, and the memory channel 1 is connected to a memory module 1, a memory module 3, and a memory module 5. 
         [0210]    Furthermore, as shown in  FIG. 16 , a transmission link  161  is established between the scheduler 0 and the scheduler 1, and is used for communication between the scheduler 0 and the scheduler 1. The scheduler 0 has a path 1 and a path 2, where the path 1 is connected to the memory channel 0, and the path 2 is connected to the memory channel 1. The scheduler 1 has a path 1 and a path 2, where the path 1 is connected to the memory channel 1, and the path 2 is connected to the memory channel 0, and a transmission link  162  is established between the memory module 0 and the memory module 1, and is used for communication between the memory module 0 and the memory module 1. 
         [0211]    With reference to the memory system shown in  FIG. 16 , the memory module access method provided in this embodiment includes the following steps. 
         [0212]    Step S 1 : The scheduler 0 and the scheduler 1 exchange quantities of to-be-sent memory access requests with each other using the transmission link  161 . 
         [0213]    Step S 2 : When receiving at least two memory access requests, the scheduler 0 sends the first memory access request through the path 1, and also checks whether the scheduler 1 currently has a memory access request needing to be sent, and if the scheduler 1 currently does not have a memory access request needing to be sent, sends the second memory access request in the same scheduling timeslot through the path 2. 
         [0214]    It should be noted that, generally, a destination address of the memory access request received by the scheduler 0 is located in a memory module corresponding to the memory channel 0, that is, the memory module 0, the memory module 2, or the memory module 4. A destination address of the memory access request received by the scheduler 1 is located in a memory module corresponding to the memory channel 1, that is, the memory module 1, the memory module 3, or the memory module 5. 
         [0215]    Step S 3 : Send the second memory access request to the memory channel 1 through the path 2 of the scheduler 0, the memory module 1 receives the second memory access request, forwards the second memory access request to the memory module 0 through a transmission link  162 , and forwards the second memory access request to a destination memory module using the memory module 0. 
         [0216]    It should be noted that, in the foregoing step S 1  to step S 3 , the scheduler 0 offloads memory access requests received by the scheduler 0 to the memory channel corresponding to the scheduler 1 (that is, the memory channel 1). According to the same method, the scheduler 1 in this embodiment may offload memory access requests received by the scheduler 1 to the memory channel corresponding to the scheduler 0, which is not described again herein. 
         [0217]    According to the memory module access method provided in this embodiment of the present disclosure, each scheduler may acquire a quantity of to-be-sent memory access requests in another scheduler, and when receiving multiple memory access requests, may send the multiple received memory access requests through multiple memory channels. According to the method provided in this embodiment of the present disclosure, when multiple memory access requests are received, the multiple received memory access requests can be allocated to multiple memory channels for sending, thereby improving the utilization of bandwidth resources, and improving a memory access bandwidth. 
       Embodiment 11 
       [0218]    In  FIG. 16 , a dual-channel memory system is used as an example for description. A memory module access method provided in the present disclosure is applicable to a multichannel system. Next, in this embodiment, an N-channel memory system is used as an example for further description. 
         [0219]    The N-channel memory system includes N schedulers, N memory channels, and N memory modules, where the N schedulers may be marked as a scheduler 0, a scheduler 1, . . . , and a scheduler N−1. The N memory channels are marked as a memory channel 0, a memory channel 1, . . . , and a memory channel N−1, and the N memory modules are marked as a memory module 0, a memory module 1, . . . , and a memory module N−1. The schedulers, the memory channels, and the memory modules are in a one-to-one correspondence, for example, the scheduler 0 is corresponding to the memory channel 0, and the memory channel 0 is corresponding to the memory module 0. 
         [0220]    Each scheduler has N paths (which may be marked as a path 1, a path 2, . . . , and a path N), and the N paths are respectively connected to the N memory channels. For ease of statistics, a connection relationship between a path and a memory channel may be set according to a preset rule. For example, a connection relationship between a path and a memory channel may be set according to a method in which a path m (0≦m≦N) of a scheduler n (0≦n≦N−1) is connected to a memory channel (n+m) mod N, where mod is used to indicate getting a remainder. 
         [0221]    When receiving x memory access requests, if N channels are all in an idle state, the scheduler n may send the x memory access requests successively using the local path 1, path 2, . . . , and path (n+x) mod N. When x≦N, the x memory access requests may be sent to the memory module in one scheduling timeslot. When N&lt;x≦2N, the x memory access requests may be sent to the memory module in two scheduling timeslots. The rest may be deduced by analogy, which is not described again herein. 
         [0222]    For ease of understanding, next, a three-channel memory system is used as an example for description. As shown in  FIG. 17 , the memory system includes a scheduler 0, a scheduler 1, and a scheduler 2, where the scheduler 0 is corresponding to a memory channel 0, the scheduler 1 is corresponding to a memory channel 1, and the scheduler 2 is corresponding to a memory channel 2, and the memory channel 0 is connected to a memory module 0, the memory channel 1 is connected to a memory module 1, and the memory channel 2 is connected to a memory module 2. 
         [0223]    Furthermore, as shown in  FIG. 17 , a transmission link  171  is established between the scheduler 0 and the scheduler 1, a transmission link  172  is established between the scheduler 1 and the scheduler 2, a transmission link  173  is established between the scheduler 0 and the scheduler 2, and the transmission links  171  to  173  are used for communication among the scheduler 0, the scheduler 1, and the scheduler 2. 
         [0224]    The scheduler 0 has a path 1, a path 2, and a path 3, where the path 1 is connected to the memory channel 0, the path 2 is connected to the memory channel 1, and the path 3 is connected to the memory channel 2. The scheduler 1 has a path 1, a path 2, and a path 3, where the path 1 is connected to the memory channel 1, the path 2 is connected to the memory channel 3, the path 3 is connected to the memory channel 0, and the scheduler 2 has a path 1, a path 2 and a path 3, where the path 1 is connected to the memory channel 2, the path 2 is connected to the memory channel 0, and the path 3 is connected to the memory channel 1. 
         [0225]    A transmission link  174  is established between the memory module 0 and the memory module 1, and is used for communication between the memory module 0 and the memory module 1, and a transmission link  175  is established between the memory module 1 and the memory module 2, and is used for communication between the memory module 1 and the memory module 2. 
         [0226]    According to the three-channel memory system shown in  FIG. 17 , the memory module access method is further implemented as follows. 
         [0227]    (1) When the scheduler n receives multiple memory access requests, send, using the path 1, the first memory access request needing to be sent. 
         [0228]    (2) If the scheduler n has the second memory access request needing to be sent, detect whether a scheduler (n+1)mod 3 currently has a memory access request needing to be sent, and if not, send, to the path 2, the second memory access request needing to be sent. 
         [0229]    If the scheduler (n+1)mod 3 currently has a memory access request needing to be sent, detect whether a scheduler (n+2)mod 3 currently has a memory access request needing to be sent, and if not, send, to the path 3, the second memory access request needing to be sent. 
         [0230]    (3) If the scheduler n has the third memory access request needing to be sent, the scheduler (n+1)mod 3 currently does not have a memory access request needing to be sent, and the scheduler (n+2)mod 3 currently does not have a memory access request needing to be sent either, the scheduler n sends, to the path 2, the second memory access request needing to be sent, and sends, to the path 3, the third memory access request needing to be sent. 
         [0231]    According to the memory module access method provided in this embodiment of the present disclosure, each scheduler may acquire a quantity of to-be-sent memory access requests in another scheduler, and when receiving multiple memory access requests, may send the multiple received memory access requests through multiple memory channels. According to the method provided in this embodiment of the present disclosure, when multiple memory access requests are received, the multiple received memory access requests can be allocated to multiple memory channels for sending, thereby improving the utilization of bandwidth resources, and improving a memory access bandwidth. 
         [0232]    Based on the foregoing descriptions of the implementation manners, a person skilled in the art may clearly understand that the present disclosure may be implemented by software in addition to necessary universal hardware or by hardware only. In most circumstances, the former is a preferred implementation manner. Based on such an understanding, the technical solutions of the present disclosure essentially or the part contributing to the prior art may be implemented in a form of a software product. The computer software product is stored in a readable storage medium, such as a floppy disk, a hard disk or an optical disc of a computer, and includes several instructions for instructing a computer device (which may be a personal computer, a server, or a network device) to perform the methods described in the embodiments of the present disclosure. 
         [0233]    The foregoing descriptions are merely specific implementation manners of the present disclosure, but are not intended to limit the protection scope of the present disclosure. Any variation or replacement readily figured out by a person skilled in the art within the technical scope disclosed in the present disclosure shall fall within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.