Abstract:
In one embodiment, a semiconductor package comprises a base frame and a lower semiconductor chip electrically coupled to the base frame. The lower semiconductor chip has a first bond pad formed on a top surface thereof. The package further includes an upper semiconductor chip overlying the lower semiconductor chip. The upper semiconductor chip has a third bond pad formed on a bottom surface thereof. The package comprises a first conductive bump and a second conductive bump jointly coupling the first bond pad to the third bond pad.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     This application claims priority from Korean Patent Application No.  2004-30468,  filed on Apr. 30, 2004, the disclosure of which is incorporated herein in its entirety by reference.  
         [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly to a package including upper and lower semiconductor chips interconnected by flip chip bonding, and a method of manufacturing the same.  
         [0004]     2. Description of the Related Art  
         [0005]     The demand for smaller electronic appliances has required the development of thinner and smaller semiconductor packages which in turn require smaller semiconductor devices. In order to meet the market demand, a System-On-Chip (SOC) configuration and a System-In-Package (SIP) configuration have been suggested for manufacturing semiconductor devices.  
         [0006]     A SOC is a semiconductor device in which a plurality of semiconductor chips are integrated into a single semiconductor chip. An SIP is a semiconductor device in which a plurality of individual semiconductor chips are put into a single semiconductor package. In accordance with the SIP process, a plurality of semiconductor chips are horizontally or vertically loaded within a single semiconductor package and have a typical Multi-Chip package (MCP) concept. Generally, a plurality of semiconductor chips are horizontally loaded in the MCP but are vertically stacked in the SIP.  
         [0007]     In a printed circuit board of a general electronic appliance, a semiconductor device is mounted with a passive device to improve noise characteristics of the semiconductor device. The passive device includes a capacitor, a resistor, and an inductor. The passive device is mounted as close to the semiconductor device as possible to improve characteristics of the semiconductor device. Accordingly, an SIP in which a passive device, such as a capacitor, and a semiconductor chip, such as a microprocessor, are included has been developed.  
         [0008]     A capacitor as the passive device is manufactured using a silicon wafer. The technique of forming a capacitor, using a silicon wafer, is well known. One exemplary technique is disclosed in U.S. patent application Ser. No. 9/386,660 (filed in Aug. 31, 1999), filed by Lucent Technology Co., Ltd.  
         [0009]     A semiconductor package and a method of manufacturing the same are disclosed in U.S. Pat. No. 6,057,598 (entitled “Face on Face Flip Chip Integration,” issued on May 2, 2000), assigned to VLSI Technology Inc. In this patent, upper and lower semiconductor chips are interconnected by flip chip bonding technique.  
         [0010]      FIG. 1  is a cross-sectional view of a conventional semiconductor package  260 .  
         [0011]     Referring to  FIG. 1 , a lower semiconductor chip  212  and an upper semiconductor chip  200  are stacked on a base frame  262  and interconnected with solder bumps  210  interposed between the lower semiconductor chip  212  and the upper semiconductor chip  200  by flip chip bonding. A bond pad  226  placed on an edge of the lower semiconductor chip  212  is electrically connected to a lead (not shown) of the base frame  262  via a wire  264 . The upper and lower semiconductor chips  200  and  212 , the wires  264 , and a portion of the base frame  262  are sealed with a sealing resin  266 .  
         [0012]      FIGS. 2 through 4  are cross-sectional views illustrating interconnection of the lower semiconductor chip  200  and the upper semiconductor chip  212  by flip chip bonding within the conventional semiconductor package.  
         [0013]     Referring to  FIG. 2 , the solder bumps  210  are formed under the upper semiconductor chip  200 . The upper and lower semiconductor chips  200  and  212  are brought together in a direction indicated by arrows A. The upper semiconductor chip  200  has a circuit region  202  and bond pads  208 . The lower semiconductor chip  212  has a circuit region  214  and bond pads  224  corresponding to the bond pads  208  of the upper semiconductor chip  200 . Furthermore, an additional bond pad  226  for wire bonding is separately formed on the edge of the lower semiconductor chip  212 .  
         [0014]      FIG. 3  is a cross-sectional view illustrating an upper structure of a bond pad  12  when the solder bump  210  is formed on the bond pad  12  in a conventional semiconductor package. To form the solder bump  210 , an insulating layer  16  such as a polyimide film is additionally formed on a passivation layer  14  through which the bond pad  12  is exposed. Furthermore, an Under Bump Metallurgy (UBM) layer  18  connected to the bond pad  12  should be formed. A reference numeral  10  denotes the semiconductor chip.  
         [0015]     It is, however, difficult to form the solder bump  210  directly on an aluminum layer or a copper layer generally constituting the bond pad  12 . To solve this problem, the UBM layer  18  facilitates bonding of the solder bump  210  to the bond pad  12  and prevents diffusion of the solder bump constituent into the bond pad  12 . The UBM layer  18  is typically a multiple metal layer structure comprising an interconnecting layer, a diffusion blocking layer and a wettable layer.  
         [0016]      FIG. 4  is an enlarged cross-sectional view of a portion B in  FIG. 1 .  
         [0017]     Referring to  FIG. 4 , the UBM layer  18  and another UBM layer  18 ′ are respectively formed on the bond pads  12  and  12 ′ of the upper semiconductor chip  200  and the lower semiconductor chip  212  to accomplish flip chip bonding using the solder bumps  210 . The UBM layer  18 ′ is formed on the lower semiconductor chip  212  to facilitate bonding of the solder bump  210  that is attached to the upper semiconductor chip  200  and to prevent the diffusion of the solder bump  210  into the bond pad  12 ′ of the lower semiconductor chip  212 .  
         [0018]     The flip chip bonding technique using the solder bump  210  may be preferably used for interconnection because a pressure above a prescribed level can be applied to the semiconductor chip during wire bonding, especially when the bond pad is placed on a center portion of the semiconductor chip. Thus, the pressure can damage the circuit region of the semiconductor chip placed on the lower portion of the bond pad.  
         [0019]      FIG. 5  is a cross-sectional view illustrating a wire bonded to the lower semiconductor chip  212  (a portion C of  FIG. 1 ) of the semiconductor package shown in  FIG. 1 . A metal layer  19  that facilitates wire bonding is formed to another bond pad  226  ( FIG. 1 ) disposed on the lower semiconductor chip  212 . The metal layer may be composed of composite layers of Ni/Au, Ni/Ag, or Ti/Cu/Ni/Au.  
         [0020]     However, in the conventional semiconductor package, a UBM layer is additionally formed in the lower semiconductor chip, which undesirably lengthens the overall manufacturing process time of the SIP and increases manufacturing costs.  
       SUMMARY OF THE INVENTION  
       [0021]     The present invention provides, among other things, a semiconductor package, with a novel structure for flip chip bonding, thereby eliminating the need for a UBM layer on a semiconductor chip not having a solder bump. The present invention also provides a method of manufacturing a novel semiconductor package such as a system-in-package (SIP).  
         [0022]     In one embodiment, a semiconductor package comprises a base frame and a lower semiconductor chip electrically coupled to the base frame. The lower semiconductor chip has a first bond pad formed on a top surface thereof. The package further includes an upper semiconductor chip overlying the lower semiconductor chip. The upper semiconductor chip has a third bond pad formed on a bottom surface thereof. The package comprises a first conductive bump and a second conductive bump jointly coupling the first bond pad to the third bond pad. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0023]     The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which  
         [0024]      FIG. 1  is a cross-sectional view of a conventional semiconductor package;  
         [0025]      FIGS. 2 through 4  are cross-sectional views illustrating a lower semiconductor chip and an upper semiconductor chip interconnected by flip chip bonding in the conventional semiconductor package shown in  FIG. 1 ;  
         [0026]      FIG. 5  is a cross-sectional view illustrating a wire bonded to the lower semiconductor chip in the conventional semiconductor package shown in  FIG. 1 ;  
         [0027]      FIG. 6  is a cross-sectional view of a semiconductor package according to an embodiment of the present invention;  
         [0028]      FIG. 7  is a cross-sectional view illustrating the lower semiconductor chip and the upper semiconductor chip interconnected by flip chip bonding in the semiconductor package shown in  FIG. 6 ;  
         [0029]      FIG. 8  is a cross-sectional view illustrating a wire bonded to the lower semiconductor chip in the semiconductor package shown in  FIG. 6 ;  
         [0030]      FIG. 9  is a cross-sectional view of a semiconductor package according to another embodiment of the present invention;  
         [0031]      FIG. 10  is a cross-sectional view illustrating the lower semiconductor chip and the upper semiconductor chip interconnected by flip chip bonding in the semiconductor package shown in  FIG. 9 ;  
         [0032]      FIG. 11  is a cross-sectional view illustrating a wire bonded to the lower semiconductor chip in the semiconductor package shown in  FIG. 9 ;  
         [0033]      FIG. 12  is a cross-sectional view of a semiconductor package according to yet another embodiment of the present invention;  
         [0034]      FIG. 13  is a cross-sectional view illustrating the lower semiconductor chip and the upper semiconductor chip interconnected by flip chip bonding in the semiconductor package shown in  FIG. 12 ;  
         [0035]      FIG. 14  is a cross-sectional view illustrating a wire bonded to the lower semiconductor chip in the semiconductor package shown in  FIG. 12 ;  
         [0036]      FIG. 15  is a cross-sectional view of a semiconductor package according to still another embodiment of the present invention;  
         [0037]      FIG. 16  is a cross-sectional view illustrating the lower semiconductor chip and the upper semiconductor chip interconnected by flip chip bonding in the semiconductor package shown in  FIG. 15 ;  
         [0038]      FIG. 17  is a cross-sectional view illustrating a wire bonded to the lower semiconductor chip in the semiconductor package shown in  FIG. 15 ;  
         [0039]      FIG. 18  is a plan view illustrating a structure of the base frame, the lower semiconductor chip and the upper semiconductor chip of the semiconductor package according to an embodiment of the present invention; and  
         [0040]      FIG. 19  is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0041]     The present invention will now be described more fully with reference to the accompanying drawings. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.  
         [0042]     Referring to  FIG. 6 , a semiconductor package, e.g., an SIP  100 A according to an embodiment of the present invention includes a base frame  110 . A lower semiconductor chip  120  is attached to a chip pad of the base frame  110  by, for example, an adhesive  160 . A first bond pad  122  is formed on a central portion of the upper surface of the lower semiconductor chip  120  for flip chip interconnection, and a second bond pad  132  is formed on an edge portion or a peripheral area of the upper surface of the lower semiconductor chip  120 . Additionally, the lower semiconductor chip  120  includes a conductive bump  124 , e.g., a gold bump, formed on the first bond pad  122 . The conductive bump  124  may be formed as stud- like or other suitable structures for interconnection.  
         [0043]     The SIP  100 A may include a wire  130  electrically connecting the second bond pad  132  of the lower semiconductor chip  120  to the base frame  110 . Also, an upper semiconductor chip  140  mounted on the lower semiconductor chip  120  includes another conductive bump  144 , e.g., a solder bump, disposed on a third bond pad  142  to be coupled to the gold bump  124  on the first bond pad  122  of the lower semiconductor chip  120 . A sealing resin  150  may tightly seal a portion of the base frame  110 , the wires  130 , the lower semiconductor chip  120  and the upper semiconductor chip  140 .  
         [0044]     A space between the interconnected lower semiconductor chip  120  and the upper semiconductor chip  140  may be filled with the sealing resin  150 , or an underfill material  170  such as epoxy to enhance the reliability of the interconnection.  
         [0045]     The gold bump  124  can be easily formed on the first bond pad  122  using wire bonding equipment during a semiconductor assembly process. The gold bump  124  eliminates the need for a UBM layer over the second bond pad  132 . That is, a UBM layer needs not be formed on the lower semiconductor chip  120  while using the conventionally employed first and second bond pads  122  and  132 . Thus, overall manufacturing process time can be shortened and manufacturing costs can be decreased.  
         [0046]      FIG. 7  is a cross-sectional view illustrating interconnection of the lower semiconductor chip  120  and the upper semiconductor chip  140  using a flip chip technique in the SIP.  FIG. 8  is a cross-sectional view illustrating a wire  130  bonded to the lower semiconductor chip  120 .  
         [0047]     Referring to  FIGS. 7 and 8 , in the SIP  100 A according to this embodiment of the present invention, flip chip bonding may be accomplished by connecting the stud-like gold bump  124  to the solder bump  144 . The upper semiconductor chip  140  having the solder bump  144  is subjected to UBM treatment in which an insulating layer  146  and a UBM layer  148  are formed. However, UBM treatment is not required on the lower semiconductor chip  120  having the gold bump  124 . Also, the wire  130  connecting the lower semiconductor chip  120  with the base frame  110  is directly connected to aluminum constituting the second bond pad  132 . The wire  130  may be composed of Au, Ag or Cu.  
         [0048]     Referring to  FIG. 6 , a method of manufacturing the SIP  100 A according to an embodiment of the present invention will now be described.  
         [0049]     A flexible printed circuit board (PCB) or a rigid type PCB may be used as the base frame  110 . A base frame generally employed for a ball grid array (BGA) may be used as the base frame  110 . Then, the lower semiconductor chip  120  is mounted on the base frame  110 , preferably, using the adhesive  160  such as an adhesive tape or epoxy. The first bond pad  122  suitable for flip chip bonding is formed on the central portion of the lower semiconductor chip  120 , and the second bond pad  132  for wire bonding is formed on the edge portion of the lower semiconductor chip  120 . The gold bump  124  is formed on the first bond pad  122 . The lower semiconductor chip  120  may act as a microprocessor, an LSI, or a logic device.  
         [0050]     The gold bump  124  may be formed in a wafer fabrication process or in a semiconductor chip state after mounting the lower semiconductor chip  120  on the base frame  110 .  
         [0051]     Subsequently, the second bond pad  132  of the lower semiconductor chip  120  is electrically connected to a bond finger ( 112  of  FIG. 18 ) of the base frame  110  by electrical connection means such as the bonding wire  130 . The wire bonding may be performed after loading the upper semiconductor chip  140 .  
         [0052]     The upper semiconductor chip  140  having the third bond pad  142  corresponding to the first bond pad  122  of the lower semiconductor chip  120 , and the solder bump  144  on the third bond pad  142  is prepared. The third bond pad  142  of the upper semiconductor chip  140  is formed with the UBM layer  148  and the insulating layer  146  to facilitate interconnection of the solder bump  144  and to prevent diffusion.  
         [0053]     Then, the gold bump  124  of the lower semiconductor chip  120  is placed in contact with the solder bump  144  of the upper semiconductor chip  140  by flip chip bonding, thereby mounting the upper semiconductor chip  140  on the lower semiconductor chip  120 . After mounting the upper semiconductor chip  140 , an under-fill material, such as liquid-state epoxy, is filled between the lower semiconductor chip  120  and the upper semiconductor chip  140  to improve reliability of the interconnection, and is hardened to form the underfill  170 .  
         [0054]     Thereafter, a portion of the base frame  110 , the wires  130 , and the lower and upper semiconductor chips  120  and  140  may be sealed by the sealing resin  150 . Finally, the solder ball  152  is attached to a solder-ball pad (not shown) disposed below the base frame  110 , and a singulation process of individually separating the SIP  100 A manufactured in a matrix form is performed.  
         [0055]     Referring back to  FIG. 6 , another method of manufacturing the SIP will now be described. Here, the lower semiconductor chip  120  and the upper semiconductor chip  140  are interconnected first, and the interconnected structure is then mounted on the base frame  110 .  
         [0056]     In further detail, the lower semiconductor chip  120  is formed with the first bond pad  122  on the central portion, and the second bond pad  132  on the peripheral portion. The upper semiconductor chip  140  is formed with the third bond pad  142  corresponding to the first bond pad  122  thereon. The stud-like gold bump  124  is formed on the first bond pad  122 , and the solder bump  144  is formed on the third bond pad  142 .  
         [0057]     The gold bump  124  of the lower semiconductor chip  120  and the solder bump  144  of the upper semiconductor chip  140  are placed in contact with each other. Then, the mutually interconnected lower semiconductor chip  120  and upper semiconductor chip  140  are mounted on the base frame  110  using the adhesive  160 . The lower semiconductor chip  120  and the upper semiconductor chip  140  may be subjected to flux cleaning immediately after interconnecting the lower semiconductor chip  120  with the upper semiconductor chip  140 , or after mounting the interconnected lower semiconductor chip  120  and upper semiconductor chip  140  on the base frame  110 .  
         [0058]     The space between the lower semiconductor chip  120  and the upper semiconductor chip  140  is filled with the liquid-state epoxy, which is hardened to form the underfill  170  to improve the reliability of the interconnection.  
         [0059]     Thereafter, the second bond pad  132  of the lower semiconductor chip  120  and the base frame  110  are electrically connected by the wire  130 . The base frame  110 , the wires  130 , and the lower and upper semiconductor chips  120  and  140  may be sealed using the sealing resin  150 . Finally, the solder balls  152  are attached to the lower portion of the base frame  110 , and a singulation process of individually separating the SIP  100 A manufactured in a matrix form is performed.  
         [0060]     Now another embodiment will be described, having a stud-like gold bump applied to an upper semiconductor chip.  FIG. 9  is a cross-sectional view of an SIP according to this embodiment of the present invention.  
         [0061]     Referring to  FIG. 9 , the SIP  100 B includes a base frame  110  on which semiconductor chips can be mounted. A lower semiconductor chip  120  is attached to a chip pad of the base frame  110  using an adhesive  160 , and a first bond pad  122  for flip chip bonding is formed on a central portion of the lower semiconductor chip  120  and a second bond pad  132  is formed on an edge portion of the lower semiconductor chip  120 . A solder bump  124  is formed on the first bond pad  122  of the lower semiconductor chip  120 .  
         [0062]     The SIP  100 B also includes a wire  130  that electrically connects the second bond pad  132  of the lower semiconductor chip  120  to the base frame  110 , and an upper semiconductor chip  140  stacked on the lower semiconductor chip  120 . A third bond pad  142  of the upper semiconductor chip  140  is formed with a gold bump  144  in contact with the solder bump  124  of the lower semiconductor chip  120 .  
         [0063]     Also, the SIP  100 B includes a sealing resin  150  that tightly seals a portion of the base frame  110 , the wires  130 , the lower semiconductor chip  120 , and the upper semiconductor chip  140 . An underfill  170  is formed between the lower semiconductor chip  120  and the upper semiconductor chip  140 . The third bond pad  142  of the upper semiconductor chip  140  formed with the stud-like gold bump  144  eliminates the need for UBM treatment.  
         [0064]      FIG. 10  is a cross-sectional view illustrating flip chip bonding of the lower semiconductor chip  120  and the upper semiconductor chip  140  in the SIP according to the embodiment of the present invention.  FIG. 11  is a cross-sectional view illustrating a wire  130  bonded to the lower semiconductor chip  120 .  
         [0065]     Referring to  FIGS. 10 and 11 , the flip chip bonding is obtained by contacting the stud-like gold bump  144  of the upper semiconductor chip  140  with the solder bump  124  formed on the lower semiconductor chip  120 . The lower semiconductor chip  120  having the solder bump  124  is subjected to UBM treatment. That is, the lower semiconductor chip  120  includes an insulating layer  126  and a UBM layer  128 .  
         [0066]     A metal layer  129  is formed on the UBM layer  128  to help facilitate the wire bonding process. The metal layer  129  can be composed of a composite layer of Ni/Au, Ni/Ag or Ni/Pd. The wire  130  may be Au, Ag, or Cu.  
         [0067]     Hereinafter, a method of manufacturing the SIP  100 B according to this embodiment of the present invention will be described with reference to  FIG. 9 .  
         [0068]     A flexible PCB or a rigid PCB is prepared as the base frame  110 . The lower semiconductor chip  120  is attached to the base frame  110  using the adhesive  160  such as an adhesive tape or epoxy. The first bond pad  122  suitable for flip chip bonding is formed on the central portion of the lower semiconductor chip  120 , and the second bond pad  132  for wire bonding is formed on the edge portion of the lower semiconductor chip  120 . The solder bump  124  is formed on the first bond pad  122 . The lower semiconductor chip  120  may be a microprocessor, a LSI and a logic device while the upper semiconductor chip  140  may be a capacitor device.  
         [0069]     Subsequently, the second bond pad  132  of the lower semiconductor chip  120  is electrically connected to the bond finger  112  (of  FIG. 18 ) of the base frame  110  by wire bonding. This process can also be performed after mounting the upper semiconductor chip  140 .  
         [0070]     Then, the upper semiconductor chip  140  having the third bond pad  142  corresponding to the first bond pad  122  of the lower semiconductor chip  120 , and the gold bump  144  disposed on the third bond pad  142  is prepared. The gold bump  144  can be formed in a wafer fabricating process. The third bond pad  142  of the upper semiconductor chip  140  may not include a UBM layer.  
         [0071]     Thereafter, the solder bump  124  of the lower semiconductor chip  120  and the gold bump  144  of the upper semiconductor chip  140  are interconnected by flip chip bonding, thereby mounting the upper semiconductor chip  140  on the lower semiconductor chip  120 . After mounting the upper semiconductor chip  140 , a liquid-state epoxy is filled between the lower semiconductor chip  120  and the upper semiconductor chip  140 , and is hardened to form the underfill  170  to improve the reliability of the interconnection.  
         [0072]     The base frame  110 , the wires  130 , and the lower and upper semiconductor chips  120  and  140  are sealed by the sealing resin  150 . Finally, the solder balls  152  are attached to a lower portion of the base frame  110 , and the SIP  100 B manufactured in a matrix form are singulated.  
         [0073]     A method of manufacturing the SIP  100 B according to another embodiment of the present invention will now be described with reference to  FIG. 9 . At this time, the lower semiconductor chip  120  and the upper semiconductor chip  140  are interconnected first. Then, the resultant structure is loaded on the base frame  110 .  
         [0074]     In particular, the lower semiconductor chip  120  and the upper semiconductor chip  140  are prepared. At this time, the lower semiconductor chip  120  has the first bond pad  122  on the central portion and the second bond pad  132  on the edge portion. The upper semiconductor chip  140  has the third bond pad  142  corresponding to the first bond pad  122 . The solder bump  124  is formed on the first bond pad  122  and the stud-like gold bump  144  is formed on the third bond pad  142 .  
         [0075]     The solder bump  124  of the lower semiconductor chip  120  and the gold bump  144  of the upper semiconductor chip  140  are placed in contact with each other. The mutually interconnected lower semiconductor chip  120  and upper semiconductor chip  140  are mounted on the base frame  110  using the adhesive  160 . The lower semiconductor chip  120  and the upper semiconductor chip  140  may be flux cleaned immediately after being interconnected or after the already interconnected upper and lower semiconductor chips  140  and  120  are mounted on the base frame  110 .  
         [0076]     To improve reliability of the interconnection, the liquid-state epoxy is filled between the lower semiconductor chip  120  and the upper semiconductor chip  140 , which is then hardened to form the underfill  170 .  
         [0077]     Thereafter, the wire  130  is electrically connected to the second bond pad  132  including the metal layer  129  for facilitating wire bonding to the base frame  110 . The base frame  110 , the wires  130 , and the lower and upper semiconductor chips  120  and  140  are sealed or encapsulated, using the sealing resin  150  or other suitable encapsulants. Finally, the solder balls  152  are attached to the lower portion of the base frame  110 , and the SIP  100 B manufactured in a matrix form are singulated, i.e., individually separated.  
         [0078]     Now still another embodiment will be described that has an electro-plated gold bump applied to a lower semiconductor chip.  
         [0079]      FIG. 12  is a cross-sectional view of an SIP according this embodiment of the present invention.  FIG. 13  is a cross-sectional view illustrating flip chip bonding of the lower semiconductor chip  120  and the upper semiconductor chip  140 , and  FIG. 14  is a cross-sectional view illustrating a wire bonded to the lower semiconductor chip  120 .  
         [0080]     Referring to  FIGS. 12, 13  and  14 , the structure and method of manufacturing the SIP  100 C according to this embodiment of the present invention are similar to those of the first embodiment described above. The descriptions of identical portions will thus be omitted for simplicity.  
         [0081]     As opposed to the first embodiment described, the gold bump  125  disposed on the lower semiconductor chip  120  in the third embodiment is formed by electroplating. The gold bump  125  is formed on the second bond pad  132  on the edge of the lower semiconductor chip  120  and on the first bond pad  122  of the lower semiconductor chip  120 . Therefore, wire bonding to connect the lower semiconductor chip  120  to the base frame  110  is performed on the gold bump  125  disposed on the second bond pad  132 . Therefore, the wire-bonded gold bump  134  has the shape of two stacked ball bonds.  
         [0082]     As in the first embodiment described, UBM treatment is performed on the upper semiconductor chip  140 , but is not required for the lower semiconductor chip  120 . Therefore, the process is simplified and manufacturing costs are decreased.  
         [0083]     Now yet another embodiment will be described, having an electro-plated gold bump applied to an upper semiconductor chip  140 .  
         [0084]      FIG. 15  is a cross-sectional view of an SIP according to this embodiment of the present invention.  FIG. 16  is a cross-sectional view illustrating flip chip bonding of the lower semiconductor chip and the upper semiconductor chip, and  FIG. 17  is a cross-sectional view illustrating a wire bonded to the lower semiconductor chip.  
         [0085]     Referring to  FIGS. 15, 16  and  17 , the structure and method of manufacturing the SIP  100 D according to this embodiment of the present invention are similar to those of the embodiment described in connection with  FIG. 9 . The descriptions of identical portions will thus be omitted for simplicity.  
         [0086]     In contrast with the embodiment shown in  FIG. 9 , a gold bump  144  disposed on a third bond pad  142  of an upper semiconductor chip  140  is formed by electro-plating. As in the embodiment of  FIG. 9 , the lower semiconductor chip  120  is subjected to UBM treatment, which is not performed to the upper semiconductor chip  140 . Therefore, the process is simplified and manufacturing costs are decreased.  
         [0087]      FIG. 18  is a plan view illustrating a structure of the base frame, the lower semiconductor chip and the upper semiconductor chip in the SIP according to embodiments of the present invention.  
         [0088]     Referring to  FIG. 18 , the lower semiconductor chip  120  is mounted on the base frame  110 . The upper semiconductor chip  140  is mounted on the lower semiconductor chip  120 . The second bond pad  132  disposed on the lower semiconductor chip  120  is electrically connected to the bond finger  112  on the base frame  110  via the wire  130 . The material and structure of the flip chip interconnection  180  of the lower and upper semiconductor chips  120  and  140  according to embodiments of the present invention are characterized by the solder bump and the gold bump contact.  
         [0089]     The upper semiconductor chip  140  may be a passive device for improving noise characteristics of the semiconductor device. A method of manufacturing the passive device is well known, and an example of such a method is disclosed in U.S. patent application Ser. No. 9/386660 (filed on Aug. 31, 1999, by Lucent Technology. Co. Ltd), of which detailed description is omitted for simplicity.  
         [0090]     Also, the first bond pad  122  on the central portion of the lower semiconductor chip  120  may be connected to the second bond pad  132  by inner circuit line  121 . The inner circuit line  121  connecting the first and second bond pads  122  and  132  may be formed during or after a wafer manufacturing process for forming a wafer level package (WLP).  
         [0091]     Consequently, power terminals and ground terminals of the upper semiconductor chip  140  serving as a capacitor may be connected to the second bond pads  132  via the first bond pads  122 . Also, the second bond pads  132  may be connected to the bond fingers  112  of the base frame  110  via the wires  130 . The bond fingers  112  may be externally connected via the solder balls (not shown) attached to the lower surfaces of the base frame  110 .  
         [0092]     As a result, the upper semiconductor chip  140  functioning as a capacitor may be loaded adjacent to the lower semiconductor chip  120  functioning as a microprocessor, an LSI device, or a logic device, thereby embodying an SIP capable of improving noise characteristics of the lower semiconductor chip  120 .  
         [0093]     In still another embodiment a lead frame may be used as a base frame.  
         [0094]      FIG. 19  is a cross-sectional view of the SIP according to one embodiment of the present invention. In the previously described embodiments, the base frame  110  may be a flexible PCB or a rigid PCB. However, the SIP  100 E includes a lead frame  110 ′ in place of the PCB included in the above-described embodiments. The lead frame  110 ′ includes a chip pad  114  and a lead  112 . The SIP  100 E may enable various packages such as a Thin Small Out-Line Package (TSOP), a Thin Quad Flat Package (TQFP), and a Quad Flat No-lead Package (QFN) depending on the shapes of the lead frame  110 ′. In this case, after the encapsulation or sealing, the leads  112  externally exposed from the sealing resin  150  may be lead bar trimmed, lead plated, or lead forming. Furthermore, the present invention is applicable to a Pin Grid Array (PGA) package in which pins are connected to a lower surface of the base frame  110  instead of using the solder balls.  
         [0095]     As described above, with embodiments of the present invention, there is no need to perform UBM treatment on a semiconductor chip having a gold bump. Therefore, manufacturing costs of the SIP can be decreased, and the manufacturing process can be simplified.  
         [0096]     While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.