Abstract:
A network device and a transmission method thereof are disclosed. The network device consists of a first network device and a second network device. According to at least one command, the first network device generates serial command, inserts the serial command into gaps between packet data and transmits the serial command to the second network device while outputting those packet data to the second network device. In accordance with the serial command received, the second network device saves data in a register of the second network device. Therefore, the transmission circuit is simplified, heat dissipation efficiency is improved and accuracy of signal transmission is ensured. Moreover, data in the register is retrieved precisely.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    The present invention relates to a communication system, especially to communication interface. 
         [0002]    Along with fast development of internet applications, individuals and industries depend more and more on network, especially applications of Ethernet has become an important part of the network. 
         [0003]    During communication process, chips connect with each other for data/signal transmission and data retrieving/saving in registers. Refer to  FIG. 1 , a network switch includes a media access controller (MAC)  10 ′, and a plurality of physical layer (PHY)  20 ′ that communicate with the MAC  10 ′. In specifications of IEEE 802.3, packet transmission is by an independent interface such as Media Independent Interface (MII), Gigabit Media Independent Interface (GMII), and Reduce Media Independent Interface (RMII). And a Management Data Clock (MDC) as well as a Management Data Input Output (MDIO) is used as transmission interface for reading data in registers of the PHY  20 ′. Because the MII needs to use quite a lot of pins so another prior-art Serializer/Deserializer (SERDES) interface is used to replace the MII for avoiding using too many pins. Refer to  FIG. 1 , the MAC  10 ′ accesses the plurality of PHY  20 ′ data in registers of each other by the MDC/MDIO interface to know the status of each other and transmit packets to each other by the SERDES interface or the independent interface. The MDC is a single-clock transmission line and is connected to each PHY  20 ′ while the MAC  10 ′ sends clocks to each PHY  20 ′ therethrough. The MDIO is a bi-directional transmission line and is connected to each PHY  20 ′ for data transmission according to MDC clock. 
         [0004]    More transmission wires are configured between the MDC/MDIO interface of MAC  10 ′ and that of the plurality of PHY  20 ′. And, the transmission wires mentioned above occupy more area and increase loadings of circuit layout on the printed circuit board (PCB) or chip layout, especially for MAC  10 ′ coupled with the plurality of PHY  20 ′, which makes circuit design more complicated. For example, the 32-port switch includes 32 PHYs  20 ′ which are connected to MAC  10 ′. Furthermore, According to the specifications of IEEE 802.3, the MDC/MDIO interface is slow-speed series interface; there is a need to improve poor transmission speed of the MDC/MDIO interface to enhance the performance of the network device. 
       SUMMARY OF THE INVENTION 
       [0005]    Therefore it is one of objects of the present invention to provide a network device and a transmission method thereof that output access commands in packet gaps simultaneously with outputting a plurality of data packets for accessing register so as to achieve purposes of simplifying transmission circuit, improving heat dissipation efficiency and ensuring accuracy of signal transmission. 
         [0006]    It is one of objects of the present invention to provide a network device and a transmission method thereof that output access commands in packet gaps simultaneously for accessing register so as to simplify transmission circuit. 
         [0007]    It is one of objects of the present invention to provide a network device and a transmission method thereof that send an acknowledge signal for confirming that data in register has been accessed. 
         [0008]    A network device according to the present invention comprises a first circuit and a second circuit. The first circuit receives at least one command and generates a serial command according to the at least one received command. The second circuit, which coupled to the first circuit, receives the serial command and transmits a first packet, an inter-packet gap, and a second packet, wherein the inter-packet gap is between the first and the second packets, and the inter-packet gap comprises at least one portion of the serial command. In addition, the second circuit splits the serial command so that the inter-packet gap comprises at least one portion of the serial command. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    The structure and the technical means adopted by the present invention to achieve the above and other objects can be best understood by referring to the following detailed description of the preferred embodiments and the accompanying drawings, wherein 
           [0010]      FIG. 1  is a block diagram of a conventional network switch; 
           [0011]      FIG. 2  is a block diagram of an embodiment according to the present invention; 
           [0012]      FIG. 3   a  and  FIG. 3   b  are a schematic drawing showing packet transmission according to the present invention; 
           [0013]      FIG. 4  is a block diagram of a network device of an embodiment according to the present invention; 
           [0014]      FIG. 5  is a schematic drawing showing packet transmission of an embodiment according to the present invention; 
           [0015]      FIG. 6A  is a list of command format of an embodiment according to the present invention; 
           [0016]      FIG. 6B  is command format transmitted or received by an embodiment according to the present invention; 
           [0017]      FIG. 7  shows a list of signal definition of IEEE802.3 specification; 
           [0018]      FIG. 8  is a block diagram of another embodiment according to the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0019]    A network device and a transmission method thereof according to the present invention are applied to switching devices. According to the present invention, an interface which is used for transmitting/receiving packet, such as SERDES, MII, GMII, and RMII, is used for simultaneously transmitting/receiving data and accessing registers of each other. 
         [0020]    Refer to  FIG. 2 , the present invention applied to switching device includes at least one MAC  10  and at least one PHY  20 . In a network interface card (NIC), the NIC comprises a MAC and a PHY. In a 32-port switch (or gateway, router) comprises at least one MAC and 32 PHYs. the MAC  10  of the switch device is coupled with a plurality of PHY  20 . Data and instruction (command) transmission between the MAC  10  and the PHY  20  is via a SERDES interface or a MII interface so as to simplify circuit design. 
         [0021]    Next embodiments explain how the present invention performs packet data and command over the same interface under requirements of related specifications such as IEEE 802.3. 
         [0022]    Refer to  FIG. 3A  &amp;  FIG. 3B , according to IEEE 802.3, an inter-packet gap (IPG)  36  is between a first packet  32  and a second packet  34  for separating packets. The IPG  36  is an idle data and meaningless. By such feature, the present invention transmits serial command to simplify transmission circuit. As shown in  FIG. 3B , the MAC  10  replaces the idle data of the IPG  36  with serial command  38  so that the MAC  10  can also transmits the serial command  38  to the PHY  20  for accessing register data and knowing status of the PHY  20  while transmitting packet data such as the first packet  32  and the second packet  34  via the SERDES or the MII interface. With reference of  FIG. 4 , a block diagram of an embodiment according to the present invention is disclosed. The MAC  10  and the PHY  20  can be located in the same chip or respectively in different chips. Refer to  FIG. 5 , due to various size of the IPG  36  between two consecutive packets, the MAC  10  splits the serial command  38  into a first data  360 , a second data  362 , a third data  364  and a fourth data  366 , etc. so that while the MAC  10  transmits the packet data, the serial command  38  is simultaneously sent to the PHY  20  for controlling the PHY  20  or accessing of register in the PHY  20 . 
         [0023]    In an embodiment, the MAC  10  includes a first circuit and a first interface. An embodiment of the first circuit and the first interface of the present invention are a transmitting/receiving processing unit  14  and a transmitting/receiving interface  16 . 
         [0024]    The PHY  20  includes a second circuit, a second interface and a third circuit. An embodiment of the second circuit, the second interface and the third circuit of the present invention are a transmitting/receiving interface  22 , a transmitting/receiving processing unit  24  and a logic  26 . When a computer host sends a command to the MAC  10 , a register  12  located in the MAC  10  is used to store command data corresponding to that command, the transmitting/receiving processing unit  14  generates the serial command  38  according to the command data in the register  12 . In an embodiment, the serial command  38  can include a plurality of command data from host. The transmitting/receiving interface  16  of the MAC  10  transmits the packet  32 ,  34 , the serial command  38 , and the packet  32 ,  34  to the PHY  20 . Then the transmitting/receiving interface  22  of the PHY  20  receives the packet  32 ,  34 , and the serial command  38  and transfers the serial command  38  to the transmitting/receiving processing unit  24 . The transmitting/receiving processing unit  24  sends the packet  32 ,  34 , to a network media such as unshielded twisted-pair (UTP) and generates a control command according to the serial command  38 . After receiving the control command, the logic  26  accesses the register  28  of the PHY  20 . Moreover, after accessing the register  28  of the PHY  20 , the logic circuit  26  sends data in the register  28  of the PHY  20  to the MAC  10  by a reverse path. 
         [0025]    In another embodiment, the MAC  10  and the PHY  20  respectively include an encoding/decoding unit  18 ,  29 . the encoding/decoding units  18 ,  29  encodes and decodes packet  32 ,  34  according to the related specification or/and the serial command  38 . In an embodiment, the transmitting/receiving processing unit  14  adds a checking data such as parity check or cyclical redundancy check (CRC) into the serial command  38 . 
         [0026]    In addition, after receiving the serial command  38 , the PHY  20  sends a return data (ex: an acknowledge signal) to the MAC  10  so as to inform the MAC  10  to read data of register of the PHY  20 . Once the MAC  10  doesn&#39;t receive the acknowledge signal after transmitting the serial command  38  for a certain period time, it can re-send the serial command  38  to the PHY  20 . Due to the serial command  38  inserted in the IPG  36 , the PHY  20  of a first network device can also send the serial command  38  to the second network device so as to access the data in register of the second network device. That is, the first network device of the present invention can monitor/control the second network device of the present invention via a cable. 
         [0027]    Refer to  FIG. 6A .  FIG. 6A  shows a list of an embodiment of the control registers of the MAC according to the present invention. Together with  FIG. 4 , the control registers of the MAC  10  are accessed by the host and can store the command from the host. The Name of control registers of the MAC  10  respectively corresponds to a related command. In  FIG. 6A , the Name of control registers includes such as Access Request, Access Status, Access Address, Write, Ready State, and Read. When the MAC  10  detects that the Access Request register of the MAC  10  is at high level, it reads serial command from corresponding control registers and transmits the serial command to the PHY  20 . The Access Status register is set in a reading status or a writing status by the host, and the MAC  10  controls the PHY  20  to read or write registers in the PHY  20  according to the value of the Access Status register. The value of Access Address register addresses an address of the PHY  20  and address of the register in the addressed PHY  20 . The Write register and Read register performs data writing or data reading according to the value of the Access Status register. The Ready State register is used to indicate whether the MAC  10  receives the acknowledge signal from the PHY  20  or not. When the Ready State register is set at high voltage level (1), this means to the read or write operation of the register of the PHY  20  has been finished. After the MAC  10  sends the serial command  38  for a period of time and the value of the Ready State register is still at low voltage level (0), the MAC  10  re-sends the serial command  38  to the PHY  20 . 
         [0028]    Refer to  FIG. 6B .  FIG. 6B  shows command format transmitted or received by an embodiment according to the present invention. As shown in the figure, the control registers include Transmission Format, Access Status, Access Address, Write, Read and Check. The MAC  10  encodes data of register in  FIG. 6B  and generates serial command  38 . while receiving the command from the computer host. When the MAC  10  detects that the register requested is at high voltage level (1), it reads data of each register and sets the state of the Transmission Format register at high voltage level (1). Moreover, the MAC  10  controls the logic  26  of the PHY  20  according to the value of the Access State register so as to read or write data in the register of the PHY  20 . The Access Address register is used to save address of the PHY  20  and address of the register of the PHY  20 . According to the value of Transmission Format (high voltage level (1) means writing data, and low voltage level (0) means reading data), the PHY  20  reads data from or writes data into the register thereof. A Checking register is used for storing a checking code of transmitted data so as to prevent errors on data received by the PHY  20 . 
         [0029]    Refer to  FIG. 7 ,  FIG. 7  shows a list of signal definition of IEEE802.3 specification. IEEE 802.3 specification specifies idle signals including K28.5/D5.6 or K28.5/D16.2, and the idle signals are meaningless data. Thus K28.5/D5.6 and K28.5/D16.2 are modified to transmit serial command. For example, the serial command is 35-bit command and now is split up 6 parts for transmitting. For example, the 6 parts includes 5-bit first data, 6-bit second data, 6-bit third data, . . . , and 6-bit sixth data. First, the first part (5-bit first data) and a 3′b111 are transmitted and can be distinguished from D5.6 and D16.2. And 6-bit second data and a 2′b00 be transmitted. Thus it takes twelve times to transmit the whole data completely. The way of transmission is as following: 
       1. K28.5 
       [0030]    2. D{3′b111, IBS[34:30]} 
       3. K28.5 
       [0031]    4. D{2′b00, IBS[29:24]} 
       5. K28.5 
       [0032]    6. D{2′b00, IBS[23:18]} 
       7. K28.5 
       [0033]    8. D{2′b00, IBS[17:12]} 
       9. K28.5 
       [0034]    10. D{2′b00, IBS[11:6]} 
       11. K28.5 
       [0035]    12. D{2′b00, IBS[5:0]} 
         [0036]    In an embodiment, the PHY  20  receives K28.5 and the front 3 bit of the next data is 3′b111, this represents the data received by the PHY  20  is the serial command. After receiving data for six times, the complete serial command is sent to a back-end circuit (i.e. logic circuit) for accessing data in registers. No matter reading data from or writing data into the register, the PHY  20  sends an acknowledge (ACK) signal back to inform the device that the data transmission is finished. The way of returning the ACK signal is by means of sending serial command and the register for transmission format is set at low-voltage level (0). After receiving the ACK signal, the MAC  10  sets the register for ready status at low-voltage level (1) to confirm that the register data has been accessed. 
         [0037]    Refer to  FIG. 8 ,  FIG. 8  is a block diagram of another embodiment according to the present invention. A network system includes a first switch device  40  and a second switch device  50  coupled with each other by an optical fiber or a cable. When there is an error occurred on network routes such as a problem of the second switch device  50 , users can access registers of an MAC  54  of the second switch device  50  through the first switch device  40  on computer facilities by a transmission way of the serial command shown in  FIG. 5 . Therefore, not only the status of the second switch device  50  is obtained but the problem of the second switch device  50  can be solved by accessing or setting or initializing the corresponding registers of the second switch device  50 . 
         [0038]    In summary, a circuit for accessing register data and a method thereof according to the present invention uses a first network device to generate serial command according to a plurality of command from host. Then the serial command is sent to a second network device through inter-packet gap for accessing register in the second network device. Therefore, purpose of simplifying circuit is achieved. 
         [0039]    Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details, and representative devices shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.