Abstract:
A method for low power clock tree synthesis using buffer insertion, removal and resizing for high-speed VLSI design is proposed. A developed tool can be embedded in the existing clock tree synthesis design flow to ensure satisfying both specifying database constrains and clock skew constrains. For a given clock tree netlist, location information of buffers, parameters of wires and buffers&#39; timing and power library are all included. Buffer delay and wire delay of the given clock tree netlist are calculated first. Then, a feasible solution is solved if an input netlist is not feasible for given constrains. Finally, a modified low power clock tree netlist, which satisfies timing specifications, is obtained using the proposed method.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a clock tree synthesis and, more particularly, to a clock tree synthesis for low power consumption and low clock skew. 
   2. Description of Related Art 
   In the modem high speed VLSI design era, clock design plays a crucial role in determining chip performance and facilitating timing and design convergence. Clock routing is important in the layout design of a synchronous digital system as it influences correctness, area, speed and power dissipation of the synthesized system [reference 1 and 2]. Drastically increased requirements for high performance and high speed VLSI circuits have posed challenges to the design of high speed clock networks, where minimization of clock delay and clock skew has been a critical problem. So some circuit designers&#39; inclination is toward developing techniques to minimize the power dissipation, the clock delay (latency) and the clock skew as well as developed, understood design and verification flows. 
   Buffer operations are widely used in designing clock distributed networks [reference 3]. Buffers can decouple capacitance to reduce equivalent loading of each wire, so rise time and wire delay could be reduced. Also, when the signal&#39;s transfer time is faster, it can reduce power consumption. Several methodologies are adopted in the power consumption and the clock skew minimization. The previous research inserts the buffers and constructs a H-tree to reach the optimization solution in both circuit area and the power consumption aspects [reference 4]. The balanced buffer insertion scheme attempts to partition the clock tree into several subtrees such that every subtree has equal path length and all source-to-sink paths have an equal number of levels. Clock gating is another well-known technique in reducing the dynamic power dissipation of a digital circuit [reference 5 and 6]. It saves power by shutting off the sequential elements and part of the clock network during an idle state. 
   The design of the clock distribution network also determines the clock skew. The clock skew directly affects chip performance in a close to one-to-one ratio, since it has to be counted as a cycletime penalty. The clock trees need to be incrementally adjusted accordingly with minimum changes to ensure an acceptable clock skew. The buffer insertion usually deals with the clock skew minimization problem [reference 7]. Other research using the buffer insertion method minimizes both the power consumption and the clock skew criterion [reference 4]. 
   SUMMARY OF THE INVENTION 
   The main objective of the present invention is to provide an improved clock tree synthesis that reduces power consumption and clock skew. 
   To achieve the objective, the clock tree synthesis in accordance with the present invention can be embedded in existing clock tree synthesis design flow to ensure satisfying both specifying database constrains and the clock skew constrains. For a given clock tree netlist, the location information of buffers, the parameters of wires and the buffers&#39; timing and power library are all included. Buffer delay and wire delay of the clock tree are calculated first. Then, a feasible solution is solved if a input netlist is not feasible for the given constrains. Finally, a modified low power clock tree netlist, which satisfies timing specifications, is obtained using the proposed method. 
   Further benefits and advantages of the present invention will become apparent after a careful reading of the detailed description with appropriate reference to the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a pseudocode of a design flow of a clock tree synthesis in accordance with the present invention; 
       FIG. 2  is a diagram of power consumption for a three level clock tree design; 
       FIG. 3(   a ) is parastic model between two buffers of the present invention; 
       FIG. 3(   b ) is a reduced standard parasitic format model of the present invention; 
       FIG. 4  is a pseudocode of a simulated annealing based optimization algorithm of the present invention; 
       FIG. 5  is a pseudocode of the simulated annealing algorithm of the present invention: and 
       FIG. 6  is a design layout diagram result of an optimization operation of the clock tree of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   A clock distribution network that has been implemented with a cell placement and an initial clock tree is given. A specified liberty library that includes clock buffers and D-flip-flops (DFF) is also given. A clock network to dissipate minimal power and satisfy clock skew constraint at all receivers (DFFs) is also given. The clock skew should be small, even under process variations. A developed software has to apply allowable techniques, such as buffer insertion, buffer resizing, and buffer removal to reduce the dynamic power under the constraint of the maximum clock skew. It is allowed to resynthesize a better clock tree, except that a root (i.e. a clock input pad) of the clock tree should be the same as a root of the initial clock tree. 
   The power dissipated by the clock distribution network can be attributed to charging and discharging of wiring and load capacitances through interconnect resistance and driver resistance and to the static power dissipated, if any, by the buffers
 
 P=P   static   +P   dynamic   =ΣP   i   +C   o   ·L ( T )· f·V   2   (1)
 
Here, P i  is the static power dissipated by the ith clocked components. C o  is capacitance per unit length and is set to 0.000076 in practical experience. L(T) is wire length of the clock tree and can be simplified to a Manhattan distance,
 
 L ( T )=| X   cell1   −X   cell2   |+|Y   cell1   −Y   cells |  (2)
 
where X cell1  and X cell2  are coordinates of cell i . f and V are frequency of operation and voltage swing, respectively.
 
   The clock network design determines buffer sizes, buffer locations, and buffer interconnect topology. It therefore affects the static power dissipation summation in the first term and the wire length in the second term. In Eq. (1), the static power of each gate is defined in a power model of the specified library. Both rise power and fall power have to be considered in a clock cycle. For CMOS VLSI, the static power consumed by the buffers is negligible, so that the problem has been reduced to minimizing the total capacitance, which is contributed by both wiring and buffers. In ECL (Emitter Coupled Logic), the static power dissipation has been dominated by the buffers. For multichip modules, both dynamic and static power consumption may be equally important. 
   Considering the clock skew constraint, the ith cell&#39;s clock latency can be represented as t cd   i . For a zero clock skew clock tree designs, a clocked component
 
∀( i,j )ε T, s.t. t   cd   i   =t   cd   j   (3)
 
In a digital synchronous circuit, the clock skew T Skew (i,j) between registers R i  and R j  is defined as the algebraic difference,
 
 T   Skew ( i,j )= t   cd   i   −t   cd   j   (4)
 
According to the characteristic of the clock network, the clock tree design considers only the clock latency from the clock root to the sink without thinking about the physical routing path.
 
   In the clock distribution network design problem, the design rule check (DRC) problem is considered, including the input signal transition time and output loading constraints. The input transition time constraints can be defined as
 
∀ i   εT, s.t. T   i   ≦T   k,   (5)
 
where T k  is the specified maximum allowed input transition time of k-type cell, and T i  is the transition time of the signal at the ith sink. Note that the constraint is extremely important as any recognizable clock must have a clock period of at least three times 10% to −90% rise time. The rise time of classically designed clock nets imposes a limit on the frequency of operation, even if logic delays are small.
 
   In this section, a proposed clock tree synthesis tool for both low power consumption and low clock skew using buffer insertion, removal and resizing operations is proposed. Depending on a different technology library, the proposed method adopts various adjustments for the constraints. A pseudocode of the design flow is shown in  FIG. 1 . First, the proposed method loads three input files, including (a) Design: the original clock tree design, (b) library: the technology depended buffer and DFF library, and (c) constraint: the constraint of the optimization target. Second, a program checks whether the original clock tree design meets the constraint or not. If there is a DRC violation condition, the program will modify it and conquer it. Third, a fast buffer resizing operation is executed to decrease the entire power consumption, but it takes risks to violate the design constraint. So the program checks the design again to avoid an unwanted condition in the next step. Finally, a simulated annealing (SA) algorithm based optimization method is told to reduce the power consumption and the clock skew of the clock tree. A detailed procedure is shown below. 
   In the procedure of low power consumption in the clock tree syntheses, the proposed method provides different methodology depending on the different technology library. In the specified buffer library, for instance, CLKBUFXL is the smallest size and CLKBUFX20 is the largest. For example, a simple three level clock tree contains 100 DFFs (D-flip-flops) in the leaves (i.e. clock signal receiving nodes of the DFFs) and buffer CLKBUFX8 in the root node. A diagram of the power consumption of the clock tree is shown in  FIG. 2 . The X axis means the number of the buffer in the second level of the clock tree. If there is only one buffer, then, the buffer should connect to all of the 100 DFFs; if there are two buffers, then, each buffer should connect to 50 DFFs in average. The Y axis means the type of the buffer, the indexes from 1 to 9 means CLKBUFXL, CLKBUFX1, CLKBUFX2, CLKBIJFX3, CLKBUFX4, CLKBUFX8, CLKBUFX12, CLKBUFX16 and CLKBUFX20, respectively. Zero power consumption means that there is a DRC violation condition in the input transition time or the output loading constraints. According to the power distribution in  FIG. 2 , that CLKBUFX8 is the best choice in the fast buffer operation. 
   The timing constraint is depended on a propagation delay from the root buffer to the DFF leaf in the clock tree. It also means the summation of the buffer internal delay and interconnect delay on a entire path, such as 
                   t   cd   i     =         ∑     j   ∈     P   ⁢           ⁢     (   i   )           ⁢           ⁢     BUF   j       +       ∑     k   ∈     P   ⁢           ⁢     (   i   )           ⁢           ⁢     wire   k                 (   6   )               
where P(i) is the path from the root node to the ith buffer, BUF J  means the internal delay of the jth buffer on the path P(i), and wire k  is the kth interconnect on the path P(i). In order to calculate the propagation delay quickly, the parameter of the interconnects can be simplified as a reduced standard parasitic format (RSPF). In this model, the buffer resizing will not affect the interconnect delay.  FIG. 3(   a ) shows the parasitic model between buffer A and buffer B, and transfer function is represented as Y(s).  FIG. 3(   b ) is the parameter of RSPF model, where the π-model (R1, C1 and C2) is an approximation of the first three orders of Y(s). It also means the equivalent loading of buffer A, the value is C1+C2. A pin-to-pin interconnect delay can be simply shown in a RC model, and the value is R2+C3.
 
   In order to simplify a computational cost, the wire loading as a direct proportion of the physical length has been chosen, and only considering a relationship between the delay of buffers and its loading, and neglecting the effects of the interconnect delay. In other words, the buffers or DFFs connected to the same driving buffer have the same input transition time and the same clock latency. The buffer&#39;s internal delay and output transition time uses a table look-up method from the specified library. If there is no exact value in the look-up table, an interpolation method is used instead. Generally speaking, the DFFs often connect in the leaf node: and the number of DFFs is more than ten times the number of buffers in the clock tree design. 
   In this subsection, a benefit of buffer operation for low power consumption and low clock skew constraints is described. In order to meet the low clock skew constraints in the clock tree, all of the DFFs to the leaves nodes is implemented according to the output loading of the connected buffer. The loading of the buffer will affect both its internal delay and its output clock transition time, which is also the input clock transition time of the next components. The large input clock transition time will cause both the large power consumption and large internal delay. So, the balanced output load of the buffers is the target to reduce both the power consumption and the clock latency. 
   In the fast feasible solution operation, the operation of buffer removal and resizing is applied. In the condition of improved performance, the buffers in a common path could be removed for reducing the power consumption. Next, according to the output loading of the leaves, a program changes the buffer size to the minimal requirement and calculates the total power consumption. Then, the proposed method changes all buffers to the same type to decrease the power rapidly. Finally, it chooses one suitable buffers set if it exists. 
   In this subsection, it can be guaranteed that there is no DRC violations in the clock distributed network design when entering this procedure. A pseudocode of optimization flow is shown in  FIG. 4 . A heuristic procedure first disturbs the distribution of a few DFFs. Then, the program checks whether the total power consumption increases or not. If a worse result appears, then, an algorithm will reset the distribution of DFFs to the previous status. In a simulated annealing algorithm procedure, shown in  FIG. 5 , a temperature coefficient T is introduced, and a cooling factor a α=0.9 is used. The cost of changing is defined as
 
Δ c =cos  t ( prev )−cos  t ( opt ),
 
an acceptable probability of changing is
 
             ⅇ         -   Δ     ⁢           ⁢   c     T       ,         
and the new temperature T is defined as α T.
 
   In order to reduce computational complexity, the DFFs in the same level of the clock tree are chosen to vary at the same time. It is reliable that the clock skew could be reduced simultaneously. After the simulated annealing procedure, the program checks the power consumption again. If there is improvement, then, the program will try to disturb the distribution of DFFs again and repeat the procedures above. On the other hand if there is no improvement, the program resets the clock tree structure to the previous status, and the program is terminated. 
   A proposed method in C on a SUN Blade 2000 with gcc 2.95 compiler is implemented. To illustrate accuracy and efficiency of the proposed method, five test cases of the clock tree design were provided for comparison studies. The information of each test case was shown in Table I, including the number of buffers, the number of DFFs, the power consumption, the maximum clock latency and the clock skew of the original clock tree design. After applying the proposed method, the information of maximum clock latency and power consumption of the specified test cases under different clock skew constraint was shown in Table II. A design layout diagram result of an optimization operation of the clock tree was shown in  FIG. 6 , the maximum and the minimum clock latency were highlighted on the figure. It was shown in Table II that the method could decrease the power consumption to 10% in average for a feasible solution, such as Exam. 1 in Table II. Furthermore, with intensifying the clock skew constraint, it could he observed that although the decreasing percentage is smaller, the power consumption of the optimization clock tree design is still smaller than the original one. It was also shown in Table II that the maximum clock latency increases in some cases. It was caused by the buffer inserting operation during the balanced clock tree structure. However, increasing of both maximum clock latency and the minimum clock latency does not matter to the operation of the clock tree. 
   A clock tree synthesis tool to perform buffer insertion, removal, resizing simultaneously for low power consumption and clock skew minimization in digital synchronous circuit design is embodied. Based on a traditional circuit design flow, the method considers different specified technology libraries to satisfy the design objective. Using the simulated annealing based optimization algorithm, the method can reduce more than 10% of the power consumption compared to the original design in average. Experimental results have demonstrated the accuracy and the efficiency of the proposed method. 
   Although the invention has been explained in relation to its preferred embodiment, it is to be understood that many other possible modifications and variations can be made without departing from the spirit and scope of the invention as hereinafter claimed. 
   
     
       
             
           
             
             
             
             
             
             
           
             
             
             
             
             
             
           
         
             
               TABLE I 
             
           
           
             
                 
             
             
               COMPARISONS OF THE FIVE TEST CASES 
             
           
        
         
             
                 
               Case 1 
               Case 2 
               Case 3 
               Case 4 
               Case 5 
             
             
                 
                 
             
           
        
         
             
               Number of 
               30 
               113 
               251 
               238 
               262 
             
             
               Buffer 
             
             
               Number of 
               500 
               1234 
               5000 
               5000 
               500 
             
             
               DFF 
             
             
               Power 
               21.461 
               52.056 
               210.505 
               214.551 
               214.513 
             
             
               Consumption 
             
             
               (mW) 
             
             
               Max. Clock 
               0.874 
               1.130 
               1.214 
               1.224 
               1.223 
             
             
               Latency (ns) 
             
             
               Clock Skew 
               0.014 
               0.020 
               0.055 
               0.064 
               0.060 
             
             
               (ns) 
             
             
                 
             
           
        
       
     
   
   
     
       
             
           
             
             
             
             
             
             
           
             
             
             
             
             
             
             
           
         
             
               TABLE II 
             
           
           
             
                 
             
             
               OPTIMIZATION RESULTS ANALYSIS 
             
           
        
         
             
                 
               Case 1 
               Case 2 
               Case 3 
               Case 4 
               Case 5 
             
             
                 
                 
             
           
        
         
             
               Exam. 1 
               Clock Skew Constraint(ns) 
               0.08 
               0.1 
               0.5 
               0.5 
               0.5 
             
             
                 
               Max clock Latency Increase 
               +40% 
               +54% 
               +124%  
               +104%  
               +43% 
             
             
                 
               Power Consumption(mW) 
               18.014 
               44.323 
               189.736 
               197.257 
               193.030 
             
             
                 
               Power Reduced(%) 
               16.06 
               14.86 
               9.87 
               8.06 
               10.01 
             
             
               Exam. 2 
               Clock Skew Constraint(ns) 
               0.02 
               0.05 
               0.1 
               0.1 
               0.1 
             
             
                 
               Max clock Latency Increase 
               −12% 
               +14% 
               +33% 
               +48% 
               +11% 
             
             
                 
               Power Consumption(mW) 
               18.728 
               45.038 
               192.383 
               196.944 
               197.983 
             
             
                 
               Power Reduced(%) 
               12.73 
               13.48 
               8.60 
               8.2 
               7.59 
             
             
               Exam. 3 
               Clock Skew Constraint(ns) 
               0.01 
               0.02 
               0.05 
               0.08 
               0.07 
             
             
                 
               Max clock Latency Increase 
                +1% 
                +7% 
               +14% 
               +37% 
                +8% 
             
             
                 
               Power Consumption(mW) 
               19.858 
               51.434 
               195.837 
               204.858 
               207.403 
             
             
                 
               Power Reduced(%) 
               7.47 
               1.19 
               6.96 
               4.51 
               3.31 
             
             
               Exam. 4 
               Clock Skew Constraint(ns) 
               0.005 
               0.015 
               0.03 
               0.06 
               0.05 
             
             
                 
               Max clock Latency Increase 
                −6% 
                +4% 
                +4% 
               +46% 
                +7% 
             
             
                 
               Power Consumption(mW) 
               21.394 
               51.723 
               204.903 
               200.482 
               209.710 
             
             
                 
               Power Reduced(%) 
               0.31 
               0.64 
               2.66 
               6.55 
               2.2 
             
             
                 
             
           
        
       
     
   
   REFERENCES 
   
       
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       [4] J. L. Neves, E. G. Friedman, “Design Methodology for Synthesizimg Clock Distribution Networks Exploiting Nonzero Localize Clock Skew,”  IEEE Transactions on VLSI System , Vol.4, No.2, pp. 286–291, 1996. 
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