Abstract:
A digital timing recovery circuit operative upon digital samples of the input signal to a data receiver provided at the sample rate to produce a clock correction signal at the symbol rate utilizing a digital periodic filter providing a double restrictive bandpass characteristic about the band edge frequencies and outputting to a nonlinear device followed by a digital sampling filter designed to require only addition and subtraction of the nonlinear device outputs.

Description:
BACKGROUND OF THE INVENTION 
     The subject invention relates to symbol data modems and more particularly to timing recovery circuits used in the receiver of such modems. The invention is particularly concerned with timing recovery circuits of the so-called envelope variety. 
     Derivation of timing at a data modem receiver is, of course, a critical function, and development of a signal with particular accuracy as far as synchronism with the transmitter symbol timing is highly desirable. Moreover, in today&#39;s microprocessor based modems, it is highly desirable to implement a timing recovery scheme which minimizes the number of microprocessor operations required. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the invention to provide an improved timing recovery scheme for a data samples at the sample rate and produces successive outputs. The successive outputs are then operated on to produce an output signal containing a spectral component at the symbol rate. This output signal may then be supplied to a sampling filter whose output provides an error signal suitable for adjustment of a phase locked timing generator. 
     An aspect of the invention believed novel is the provision of a filter, preferably a periodic filter, providing a double restrictive bandpass characteristic with peaks at F c  ±F o  where F c  is the carrier frequency and F o  is one-half the symbol rate. 
     While the foregoing summarizes inventive aspects of the invention, it is not intended to be limiting. The appended claims, properly construed, should be referred to for delineation of the actual invention. 
     It is yet another object of the invention to provide a clock extraction circuit adapted to a digital implementation which provides accurate timing with a reduced number of microprocessor operations. 
     These and other objects are accomplished according to the invention by provision of a clock extraction circuit employing a filter at the input of a data modem receiver which has a periodic characteristic in the frequency domain. The periodic filter receives samples at the sample rate and provides successive inputs to a nonlinear device at the symbol rate means. The nonlinear device supplies successive outputs to a sampling filter whose output provides an error signal. This signal is used to provide an input a phase locked timing generator which generates sample and symbol rate clocks. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The preferred embodiment of the just summarized invention will now be described in detail in conjunction with the drawings of which: 
     FIG. 1 is a block diagram of a timing recovery scheme according to the preferred embodiment. 
     FIG. 2 is a schematic diagram of the clock extractor circuit of FIG. 1. 
     FIG. 3 is an amplitude vs frequency characteristic useful in illustrating the preferred embodiment. 
     FIG. 4 shows a generalized filter characteristic suitable for use with the preferred embodiment. 
     FIG. 5 is a flowchart illustrating microprocessor implementation of the preferred embodiment. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The timing recovery scheme of the preferred embodiment is illustrated in FIG. 1. The circuit includes a clock extraction circuit 11 and a timing generator 13. 
     The preferred relationship of these elements 11,13 in a modem receiver is indicated by FIG. 1. The clock extraction circuit receives the input signal to the data modem after an analog to digital converter 16 which samples the input signal 15. The sampling gate 16 may be preceded by an antialiasing filter 17 and automatic gain control circuitry not shown. The output of the sampler 16 feeds a filter 19, which is a digital type. The output of the filter 19 supplies an input to other detection apparatus 21, which may contain an adaptive equalizer means. As shown, the timing generator 13 provides a clock at the sample rate to the converter 16 and a clock at the symbol rate used for clocking outputs of the filters 19 and elsewhere in timing operation of the receiver. The sample clock rate is typically faster than the symbol clock, for example 9600 Hz and 1600 Hz respectively. In this example, therefore, a delay of one symbol equals a delay of six samples. 
     FIG. 2 illustrates in detail the clock extraction circuit 11 of FIG. 1. This circuit 11 includes an energy restricting filter 23, a squaring circuit 25, a sampling filter 27 and a low pass filter 29. The energy restriction filter 23 is of a type known as a periodic filter. It is shown as including a twenty-four sample delay element 31 and a summer 33. This filter structure is particularly suited for a 1600 baud, 1800 Hz carrier, 50% raised cosine system. In operation, a sample delayed twenty-four sample times by delay element 31 is subtracted from the current sample. The output of the summer 33 resulting from this subtraction is squared by the squarer 25 and fed to the input 35 of the sampling filter 27. It is noted that the delay through the clock extractor circuit 11 must equal the delay through the filter 19 to within an integer number of symbols. 
     The sampling filter 27 is shown as including a plurality of delay elements each providing a delay of T seconds where T is the sample interval. Certain of the delayed squared samples D 0   2 , D 1   2 , D 2   2 , D 4   2 , D 5   2  and D 6   2  are summed with polarities 1, --1, --1, +1, +1, and -1 by a summer 37. Such a sum is computed each symbol. The output of the summer 37, sampled at the symbol rate, is low passed filtered by the filter 27. The output of the sampling filter 27 is an error signal which can be used to adjust a phase lock loop controlling generation of the sample and symbol clocks. The phase lock loop may provide the low pass filter effect illustrated as filter 29. 
     FIG. 3 illustrates the nature of operation of the periodic filter 23. This illustration is particularly shown for a 1600 Hz clock derivation, for example for a 4800 b.p.s. modem with a carrier centered at 1800 Hz and a so-called `50% raised cosine rolloff`. The circuitry of FIG. 2 is also particularly adapted for use in such a modem. 
     It is known that in such a modem, the clock spectral line is given by ##EQU1## where X(w) is the Fourier Transform (Spectrum) of the input to the squaring circuit. In the above equation, the asterisk indicates complex conjugation and ω o  =(2π) (clock frequency). 
     If we neglect the effects of amplitude distortion in the transmission medium, the 50% raised cosine rolloff spectrum X(2 pi f) at the receiver input will be: ##EQU2## 
     As known to those skilled in the art, the regions about 2600 Hz (f H ) and 1000 Hz (f L ) contribute clock energy independent of the data pattern. It is also known that phase distortion can be deleterious at frequencies 200 Hz or so away from f H  and f L . Finally, it is also known that it is desirable to restrict energy at half the clock frequency prior to squaring. The periodic filter of the preferred embodiment has the desirable advantage of providing transmission nulls at 200 Hz on either side of both f H  and f L  as shown in FIG. 3 and of providing a null at 800 Hz. (half the clock frequency). While a periodic filter is used in the preferred embodiment, any filter providing a characteristic like the periodic filter about f H  and f L  could be utilized. Thus, a shape such as that shown in FIG. 4 would suffice. A filter providing a characteristic like that of FIG. 4 is referred to herein as a &#34;double restrictive bandpass filter.&#34; 
     Curve 47 in FIG. 3 shows the result of computing the point-by-point product of X(2πf) and X(2πf-wo). The amplitude of the resulting product is given by 
     
         A(f)=cos(2π(f-2600)/1600) 
    
     in the region 2200&gt;f&gt;3000H z , after normalizing the maximum amplitude to unity. 
     Curve 43 in FIG. 3 shows the product of the amplitude response of the filter 23 with itself displaced by the clocking frequency. Since in this illustration the clocking frequency is a multiple of the frequency of the filter 23, the result is ##EQU3## (after normalizing the maximum amplitude to unity). 
     Curve 45 in FIG. 3 shows the effect of the filter 23 on the contribution to the clocking energy. The result of passing x(t) thru the filter 23 prior to squaring results in an alternative point-by-point product A&#39;(f). ##EQU4## 
     FIG. 5 illustrates a flow chart for implementing the clock extraction circuit in a microprocessor. The microprocessor functions discussed in the following are well-known to those skilled in the art and will not be described in further detail herein. 
     The flow of FIG. 5 is performed once per symbol. A store denoted &#34;W&#34; stores the 32 most recent samples outputted by the sampler 16 at a rate of, for example, 9600 samples per second. W n  is the most recent sample received. Hence, a first index IR 1  is set to point to W n , while a second index IR 2  is set to point to W n-24 . A counter K is set equal to zero. Then a loop is entered where D k  =W n  -W n-24  is calculated and stored. After calculation of one D k  value, the IR 1  and IR 2  indexes are each decremented by 1 such that the correct W values will be retrieved from the sample storage during the next iteration of the loop. The counter K=K+1 is incremented to keep track of the current iteration. Next a test is performed to ascertain whether 6 D k  &#39;s have been calculated and stored in positions denoted D 0 , D 1 , D 2 , D 3 , D 4 , D 5 . If not, the next D k  is calculated, for example D 1  =W n-1  -W n-25 . After 6 D k  &#39;s are calculated and stored, the clock error equation shown in block 101 are calculated. Finally, since D 0   will be used as D 6  during the next symbol interval, D 0  is saved in the storage location for D 6 . The simplicity and speed of this routine for generating a clock error signal is apparent from FIG. 5 and the foregoing description. 
     The flow chart of FIG. 5 just described illustrates a particular implementation of FIG. 2 in a microprocessor environment. A significant advantage of the invention is that calculations need only be made at the symbol rate, thus conserving valuable microprocessor time. 
     Those skilled in the art will readily appreciate that the subject invention has numerous applications other than in the preferred embodiment just described. Therefore, it is to be understood that, within the scope of the appended claims, the invention may be practiced other than as specifically described herein.