Abstract:
A driving circuit includes an array of driving elements that selectively supply current from a power supply to an array of driven elements at a rate responsive to the difference between a control voltage and the power supply voltage. The control voltage is furnished to the driving elements through a conductive member that extends parallel to the array of driving elements. The driving circuit includes means for adjusting the control voltage independently at each end of the conductive member, to reduce variations in the current supplied by different driving elements.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a circuit for driving an array of elements such as light-emitting diodes used as light sources in an electrophotographic printer or resistive heat-emitting elements used as heat sources in a thermal printer, and to an array head incorporating this circuit.  
           [0003]    2. Description of the Related Art  
           [0004]    As an example of a conventional circuit for driving an array of elements, Japanese Unexamined Patent Application Publication No. 9-174918 discloses a circuit for driving an array of light-emitting diodes (hereinafter, LEDs) in an electrophotographic printer. This circuit and printer will be described below with reference to FIGS.  16  to  24 .  
           [0005]    In the printer, the LED array selectively illuminates a charged photosensitive drum to form a latent image, which is developed by application of toner to form a toner image, and the toner image is transferred to and fused onto a sheet of paper. The control system of the printer is shown in FIG. 16. The printing control unit  1  is a computing device comprising a microprocessor, read-only memory (ROM), random-access memory (RAM), input-output ports, timers, and other facilities. Upon receiving signals SG 1 , SG 2 , etc. from a higher-order controller (not visible), the printing control unit  1  generates signals that control a sequence of operations for printing dot-mapped data. The data are provided in signal SG 2 , which is sometimes referred to as a video signal because it supplies the dot-mapped data one-dimensionally.  
           [0006]    The printing sequence starts when the printing control unit  1  receives a printing command from the higher-order controller by means of control signal SG 1 . First, a temperature (Temp.) sensor  23  is checked to determine whether a fuser  22  is at the necessary temperature for printing. If it is not, current is fed to a heater  22   a  to raise the temperature of the fuser  22 .  
           [0007]    When the fuser  22  is ready, the printing control unit  1  commands a motor driver  2  to drive a develop-transfer process motor (PM)  3 , activates a charge signal SGC to turn on a high-voltage (HV) charging power source  25 , and thereby charges the developing unit (D)  27 .  
           [0008]    In addition, a paper sensor  8  is checked to confirm that paper is present in a cassette (not visible), and a size sensor  9  is checked to determine the size of the paper. If paper is present, another motor driver  4  drives a paper transport motor (PM)  5  according to the size of the paper, first in one direction to transport the paper to a starting position sensed by a pick-up sensor  6 , then in the opposite direction to transport the paper into the printing mechanism.  
           [0009]    When the paper is in position for printing, the printing control unit  1  sends the higher-order controller a timing signal SG 3  (including a main scanning synchronization signal and a sub-scanning synchronization signal) as shown in FIG. 17. The higher-order controller responds by sending the dot data for one page in the video signal SG 2 . The printing control unit  1  sends corresponding dot data (HD-DATA) to an LED head  19  in synchronization with a clock signal (HD-CLK). The LED head  19  comprises a linear array of LEDs for printing respective dots (also referred to as picture elements or pixels).  
           [0010]    After receiving data for one line of dots in the video signal SG 2  and sending the data to the LED head  19 , the printing control unit  1  sends the LED head  19  a latch signal (HD-LOAD), causing the LED head  19  to store the print data (HD-DATA). The print data stored in the LED head  19  can then be printed while the printing control unit  1  is receiving the next print data from the higher-order controller in the video signal SG 2 .  
           [0011]    The video signal SG 2  is transmitted and received one printing line at a time. FIG. 17 illustrates the printing of three consecutive dot lines N−1, N, and N+1. For each line, the LED head  19  forms a latent image of dots with a comparatively high electric potential on the negatively charged photosensitive drum (not visible). In the developing unit  27 , negatively charged toner is electrically attracted to the dots, forming a toner image.  
           [0012]    The toner image is then transported to a transfer unit (T)  28 . The printing control unit  1  activates a high-voltage transfer power source  26  by sending it a transfer signal SG 4 , and the toner image is transferred to a sheet of paper passing between the photosensitive drum and transfer unit  28 . The sheet of paper carrying the transferred toner image is transported to the fuser  22 , where the toner image is fused onto the paper by heat generated by the heater  22   a.  Finally, the sheet of paper carrying the fused toner image is transported out of the printing mechanism, passing an exit sensor  7 , and ejected from the printer.  
           [0013]    The printing control unit  1  controls the high-voltage transfer power source  26  according to the information detected by the pick-up sensor  6  and size sensor  9  so that voltage is applied to the transfer unit  28  only while paper is passing through the transfer unit  28 . When the paper passes the exit sensor  7 , the printing control unit  1  stops the supply of voltage from the high-voltage charging power source  25  to the developing unit  27 , and halts the develop/transfer process motor  3 . The above operations are repeated to print a series of pages.  
           [0014]    [0014]FIG. 18 is a simplified schematic drawing showing the circuit structure of the LED head  19 . The print data signal HD-DATA and clock signal HD-CLK are used to shift bit data for two thousand four hundred ninety-six dots, a number suitable for printing on A4-size paper at a resolution of three hundred dots per inch, into a shift register comprising flip-flops FF 1 , FF 2 , . . . , FF 2496 . The latch signal HD-LOAD causes latches LT 1 , LT 2 , . . . , LT 2496  to latch the bit data. The strobe signal HD-STB-N activates a circuit comprising an inverter G 0 , pre-buffers G 1 , G 2 , . . . , G 2496 , and switching elements Tr 1 , Tr 2 , . . . , Tr 2496  that drive a linear array of light-emitting elements LD 1 , LD 2 , . . . , LD 2496  according to the latched bit data. The switching elements are p-channel metal-oxide-semiconductor (MOS) transistors; the light-emitting elements are LEDs.  
           [0015]    The LED head  19  is supplied with power at a voltage denoted VDD in this drawing and the next. Some of this power is supplied as current to drive the LEDs. The notation VDDH will be used later to denote the voltage of the LED driving power supply.  
           [0016]    As shown in FIG. 19, the LED head  19  comprises a plurality of LED array chips  101  driven by corresponding driver integrated circuits (ICs)  100 . In this example, there are twenty-six LED array chips and twenty-six driver ICs. The driver ICs  100  are connected in cascade. Each LED array chip  101  includes ninety-six LEDs. The LED head  19  also has a reference voltage generator  102  for supplying a reference voltage Vref to the driver ICs  100 .  
           [0017]    Each driver IC  100  has the same internal circuit configuration, comprising: a shift register  100   a  with ninety-six flip-flops that receive the printing data (HD-DATA) in synchronization with the clock signal (HD-CLK); a latch circuit  100   b  that latches the output signals from the shift register  100   a  in response to the latch signal (HD-LOAD); an inverter  100   e  that inverts the strobe signal (HD-STB-N) from negative to positive logic; an AND logic circuit  100   c  that gates the output signals from the latch circuit  100   b  according to the output of the inverter  100   e;  an LED driving circuit  100   d  that supplies driving current to the LEDs in the corresponding LED array chip  101  in response to the output signals of the AND circuit  100   c;  and a control voltage generator  100   f  that supplies a control voltage to the LED driving circuit  100   d.    
           [0018]    In the printing process, when the HD-DATA, HD-CLK, HD-LOAD, and HD-STB-N signals are sent from the printing control unit  1  to the LED head  19 , the LEDs that are driven are driven simultaneously for the same length of time, as determined by the strobe signal HD-STB-N (this time is denoted LDT in FIG. 17). Any variations in the electrical characteristics of transistors Tr 1 , Tr 2 , . . . , Tr 2496  and LEDs LD 1 , LD 2 , . . . , LD 2496  may therefore lead to variations in the driving current, thus to variations in the intensity of the emitted light. As a result, the dots in the latent image formed on the photosensitive drum may differ in size, leading to printed dots of different sizes.  
           [0019]    [0019]FIG. 20 shows an example of the above variations in LED driving current and dot size. DRV 1  to DRV 26  are driver ICs that drive LED array chips CHP 1  to CHP 26 , respectively. The ninety-six LEDs in each LED array chip are wire-bonded to corresponding output terminals of the driver ICs, as will be shown in FIG. 23. The twenty-six driver ICs in FIG. 20 are connected so that externally input printing data are transferred serially from one driver IC to the next.  
           [0020]    Although it is desirable for each of the driver ICs DRV 1  to DRV 26  to supply the same amount of driving current to the LEDs it drives, circuit-element characteristics vary according to various factors in the semiconductor fabrication processes, so there is inevitably some variation in the driving current. As noted above, this variation leads to variations in the amount of light (the optical power) emitted by each LED, so that the photosensitive drum receives uneven exposure energy, and different-sized dots are developed. On a printed page consisting mainly of text, the dot-size variations are rarely noticed, but when a natural image such as a photograph is printed, the dot-size variations become perceptible as variations in printing density, causing undesirable printing quality defects.  
           [0021]    To avoid such printing defects, the LED array head manufacturer screens the driver ICs, selects those in which the driving-current variation does not exceed a certain limit ΔI, groups these driver ICs according to their average driving current, and assembles each LED head with driver ICs taken from the same group.  
           [0022]    Further details of the driver ICs will now be described. FIG. 21 shows the connection relationships between the pre-buffers G 1 , G 2 , . . . , G 2496  in FIG. 18 and their peripheral circuits, showing the circuit elements (LT 1 , G 1 , Tr 1 , LD 1 ) related to the first dot. Pre-buffer G 1  includes an AND gate AD 1 , a p-channel MOS transistor TP 1 , and an n-channel MOS transistor TN 1 .  
           [0023]    [0023]FIG. 21 also shows the control voltage generator  100   f,  which includes an operational amplifier  200 , a reference resistance Rref, and a p-channel MOS transistor  201  that functions as a reference transistor. The reference transistor  201  and the p-channel MOS transistors Tr 1 , Tr 2 , . . . , Tr 2496  that function as switching elements in FIG. 18 have the same gate length, and receive the same voltage VDDH at their source electrodes. For simplicity, it will be assumed below that the reference transistor  201  also has the same gate width as transistors Tr 1 , Tr 2 , . . . , Tr 2496 .  
           [0024]    The operational amplifier  200  receives the reference voltage Vref supplied from the reference voltage generator  102  in FIG. 19 at its inverting input terminal, and outputs a control voltage Vcontrol to the gate electrode of the reference transistor  201 . The operational amplifier  200 , reference transistor  201 , and reference resistance Rref are interconnected to form a feedback control circuit that holds the current Iref flowing through the reference transistor  201  and reference resistance Rref to a constant value determined by Vref and Rref. In effect, the control voltage generator  100   f  detects VDDH and generates a control voltage Vcontrol that produces a constant reference current Iref despite variations in VDDH.  
           [0025]    Vcontrol is also supplied through pre-buffer G 1  to the gate electrode of transistor Tr 1  to switch transistor Tr 1  on. When switched on, transistor Tr 1  supplies LED LD 1  with a constant current equal to the reference current Iref and independent of VDDH.  
           [0026]    [0026]FIG. 22 schematically shows the layout of a conventional driver IC  300 , such as the driver IC disclosed in Japanese Unexamined Patent Application Publication No. 6-297765. This driver IC  300  is a rectangular chip with a row of electrodes  301  arranged along one longitudinal edge for input and output of signals such as HD-DATA, HD-CLK, HD-LOAD, and HD-STB-N. Disposed above this row of electrodes  301 , in order from bottom to top in the drawing, are a shift register  302 , a latch circuit  303 , a pre-buffer circuit  304  including AND gates and inverters, a conductive member  305  used as a ground pattern for the pre-buffer circuit  304 , an LED driving power supply electrode or VDDH electrode  306 , a row of LED driving transistors  307 , and a staggered double row of LED driving electrodes  308 . The ninety-six LED driving electrodes DO 1 , DO 2 , . . . , DO 95 , DO 96  in the double row are aligned with the associated driving transistors  307  and with other associated circuit elements in circuits  302 - 304 , as indicated by the vertical lines in the drawing. The input and output signal electrodes  301  and LED driving electrodes  308  are aluminum pads.  
           [0027]    The VDDH electrode  306  is an aluminum band of width W, disposed between and parallel to the row of pre-buffers  304  and the row of LED driving transistors  307 . A plurality of electrode pads  309  are formed on the VDDH electrode  306  to receive power at voltage VDDH from an external source (not shown). In the drawing, there are three electrode pads  309 , aligned with LED driving electrodes DO 16 , DO 48 , and DO 80 .  
           [0028]    [0028]FIG. 23 shows a schematic side view of the driver IC  300  in FIG. 22. The input and output signal electrodes  301  and VDDH electrode pads  309  are connected by bonding wires  310  to corresponding electrodes on a printed wiring board (not visible) on which the driver IC is mounted. The LED driving electrodes  308  are connected by bonding wires  311  to corresponding electrodes on an LED array chip (not visible).  
           [0029]    [0029]FIG. 24 is an equivalent circuit diagram showing the ninety-six p-channel MOS driving transistors M 1 , M 2 , . . . , M 96  that function as switching elements in one driver IC, and the driven LEDs D 1 , D 2 , . . . , D 96 . These transistors and LEDs correspond to the transistors and LEDs denoted Tr 1 , Tr 2 , . . . and LD 1 , LD 2 , . . . in FIGS. 18 and 21. Also shown is a reference transistor M 0  equivalent to the reference transistor  201  in FIG. 21. The position of reference transistor M 0  is indicated by hatching in FIG. 22.  
           [0030]    The source electrodes of transistors M 1 , M 2 , . . . , M 96  are connected to the VDDH electrode  306  at nodes S 1 , S 2 , . . . , S 96  in FIG. 24. The resistance of the VDDH electrode  306  between these nodes is modeled by resistors R 1 , R 2 , . . . , R 95 . An additional resistor R 0  models the resistance between node S 1  and the source electrode of reference transistor M 0 . The resistance of the three bonding wires  310  that supply power to the VDDH electrode  306  is modeled by resistors R 201 , R 202 , R 203 . Given the layout shown in FIG. 22, in which the VDDH electrode pads  309  are aligned with LED driving electrodes DO 16 , DO 48 , DO 80 , these resistors R 201 , R 202 , R 203  can be considered to be connected to the source electrodes of driving transistors M 16 , M 48 , M 80  at nodes S 16 , S 48 , S 80 , respectively.  
           [0031]    The drain electrodes of driving transistors M 1 , M 2 , . . . , M 96  are connected to the anode electrodes of LEDs D 1 , D 2 , . . . , D 96 . When switched on, the driving transistors M 1 , M 2 , . . . , M 96  supply current Io to the corresponding LEDs at a rate determined by their gate-source voltage, which depends on the control voltage Vcontrol generated by the control voltage generator shown in FIG. 21.  
           [0032]    In FIGS. 22 and 24, driving transistor M 1  and reference transistor M 0  are mutually adjacent and therefore have substantially identical electrical characteristics and gate-source voltages. The current Io supplied by driving transistor M 1  is therefore substantially equal to the constant reference current Iref flowing through reference transistor M 0 , as desired. In the driver IC as a whole, however, the driving current may vary, making it necessary to screen out driver ICs in which the variation exceeds a limit ΔI, as noted above.  
           [0033]    Referring again to FIG. 20, there tends to be little difference in the driving current supplied by the driving transistors at mutually adjacent dot positions within one driver IC chip. Furthermore, the variation within the driver IC chip as a whole tends to be a monotonic increase or decrease according to the dot position, for the following reason.  
           [0034]    The driver ICs are formed on a circular silicon wafer on which electrical characteristics such as MOS transistor threshold voltages usually show a concentric pattern of variation. A driver IC chip formed near the periphery of the wafer, at a point where the long axis of the chip aligns with the concentric pattern, will display little variation in driving current, but only a few such chips can be obtained from each wafer. Most of the chips are disposed in positions where their long axes cut across the concentric pattern, producing driving current that increases or decreases from one dot to the next along the length of the chip.  
           [0035]    As shown in FIG. 20, even if two adjacent driver ICs have the same average driving current value, if they both have the same increasing or decreasing pattern of dot-to-dot current variation, there may be a considerable difference in driving current between the dot at one end of one chip and the adjacent dot at the adjacent end of the other chip. Moreover, even if the dot-to-dot variation within each driver IC chip is ΔI or less, the variation within the whole head may be as large as 2ΔI in the worst case.  
           [0036]    Thus despite the screening of the driver chips, there can be a significant difference in driving current between two mutually adjacent dot positions on different chips, leading to an abrupt change in printing density that persists in the vertical direction on the printed page. While gradual variations in printing density often go unnoticed, the human eye readily perceives an abrupt, persistent change.  
         SUMMARY OF THE INVENTION  
         [0037]    An object of the present invention is accordingly to reduce the size of abrupt element-to-element variations in driving current supplied to an array of driven elements.  
           [0038]    Another object of the invention is to reduce gradual variations in the driving current.  
           [0039]    The invention provides a driving circuit that drives an array of driven elements. The driving circuit includes an array of driving elements that receive a control voltage, and selectively supply current from a power supply to the driven elements at a rate responsive to the difference between the control voltage and the power supply voltage. The control voltage is furnished to the driving elements through a conductive member that extends parallel to the array of driving elements. The driving circuit includes means for adjusting the control voltage independently at each end of the conductive member.  
           [0040]    According to one aspect of the invention, the means for adjusting comprises a pair of control voltage generators. One control voltage generator includes a reference element disposed at a first end of the array of driving elements, and supplies a first control voltage, responsive to the power supply voltage at the first end of the array, to the first end of the conductive member. The other control voltage generator includes a reference element disposed at a second end of the array of driving elements, and supplies a second control voltage, responsive to the power supply voltage at the second end of the array, to the second end of the conductive member.  
           [0041]    In this aspect of the invention, the control voltage supplied to a driven element varies between the first and second control voltages according to the position of the driven element between the two ends of the array, thereby counteracting variations in electrical characteristics in the array and reducing variations in driving current. In particular, the driving current supplied by the driving elements at the two ends of the array can be controlled to substantially the same value, so that in an array head employing a plurality of these driving circuits, there are no abrupt changes in driving current from one driving circuit to the next.  
           [0042]    According to another aspect of the invention, the control voltage is supplied to the center of the conductive member by a single control voltage generator, and the means for adjusting includes a pair of control voltage adjustment circuits, disposed at mutually opposite ends of the conductive member, that can be independently set to source or sink current, thereby independently raising or lowering the control voltage at the two ends of the conductive member. These control voltage adjustments can reduce gradual variations in driving current across the array.  
           [0043]    The single control voltage generator may include a single reference element disposed in the middle of the array of driving elements, or two reference elements disposed at mutually opposite ends of the array. The control voltage supplied to the center of the conductive member may thus be responsive to the power supply voltage at the middle of the array, or to the average of the power supply voltages at the two ends of the array.  
           [0044]    The driving elements and reference elements are, for example, transistors with gate electrodes receiving the control voltage. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0045]    In the attached drawings:  
         [0046]    [0046]FIG. 1 is a schematic plan view showing the layout of a driver IC according to a first embodiment of the present invention;  
         [0047]    [0047]FIG. 2 is an equivalent circuit diagram showing driving transistors in the driver IC in FIG. 1, and the driven LEDs;  
         [0048]    [0048]FIG. 3 shows connection relationships of the control voltage generators, pre-buffers, and their peripheral circuits in the driver IC in FIG. 1;  
         [0049]    [0049]FIG. 4 shows an example of dot-to-dot variations in LED driving current caused by variations in the threshold voltage Vt of the driving transistors in the first embodiment;  
         [0050]    [0050]FIG. 5 is a schematic plan view showing the layout of a driver IC according to a second embodiment of the invention;  
         [0051]    [0051]FIG. 6 is an equivalent circuit diagram showing driving transistors in the driver IC in FIG. 5, and the driven LEDs;  
         [0052]    [0052]FIG. 7 shows connection relationships of the control voltage generator, pre-buffers, their peripheral circuits, and a pair of control voltage adjustment circuits in the driver IC in FIG. 5;  
         [0053]    [0053]FIG. 8 is a circuit diagram showing the structure of the control voltage adjustment circuits in FIG. 7;  
         [0054]    [0054]FIGS. 9A and 9B illustrates a pair of decoders that generate command signals for the control voltage adjustment circuits in FIG. 7;  
         [0055]    [0055]FIG. 10 is a circuit diagram showing the internal structure of the decoders in FIGS. 9A and 9B;  
         [0056]    [0056]FIG. 11 is a truth table illustrating various modes of operation of the second embodiment;  
         [0057]    [0057]FIG. 12 shows an example of dot-to-dot variations in driving current in the second embodiment;  
         [0058]    [0058]FIG. 13 is a schematic plan view showing the layout of a driver IC according to a third embodiment of the invention;  
         [0059]    [0059]FIG. 14 is an equivalent circuit diagram showing the driving transistors in the driver IC in FIG. 13, and the driven LEDs;  
         [0060]    [0060]FIG. 15 shows connection relationships of the control voltage generator, its reference transistors, the pre-buffers, their peripheral circuits, and a pair of control voltage adjustment circuits in the driver IC in FIG. 13;  
         [0061]    [0061]FIG. 16 is a block diagram showing the control system of an electrophotographic printer with an LED head;  
         [0062]    [0062]FIG. 17 is a timing diagram showing various signals in FIG. 16;  
         [0063]    [0063]FIG. 18 shows the general circuit configuration of the LED head in FIG. 16;  
         [0064]    [0064]FIG. 19 shows the structure of the LED head in FIG. 16;  
         [0065]    [0065]FIG. 20 shows an example of dot-to-dot variations in driving current in the LED head in FIG. 16;  
         [0066]    [0066]FIG. 21 shows connection relationships of the control voltage generator, a pre-buffer, and its peripheral circuits in the driver IC in FIG. 16;  
         [0067]    [0067]FIG. 22 is a schematic plan view showing the layout of a conventional driver IC;  
         [0068]    [0068]FIG. 23 is a cross-sectional view of the driver IC in FIG. 22; and  
         [0069]    [0069]FIG. 24 is an equivalent circuit diagram showing the driving transistors in the driver IC in FIG. 22, and the driven LEDs. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0070]    Embodiments of the invention will now be described with reference to the attached drawings, using like reference characters to indicate like elements in different drawings.  
         [0071]    [0071]FIG. 1 schematically shows the layout of a driver IC according to a first embodiment of the invention. Most of the elements shown in FIG. 1 are identical to the corresponding elements in the conventional driver IC in FIG. 22; repeated descriptions of these elements will be omitted.  
         [0072]    The driver IC in FIG. 1 differs from the driver IC in FIG. 22 in that it has reference transistors M 0 , M 97  (indicated by hatching) at both ends of the row of driving elements  307  instead of only one end, and generates two corresponding control voltages, responsive to the LED driving power supply voltage VDDH at the two ends of the array. The conductive member  305  is now a source wiring structure comprising, for example, impurity diffusion regions in the IC chip substrate and polysilicon wires, that supplies the control voltages to the driving transistors  307  through the pre-buffers  304 . The polysilicon wires may include a tungsten silicide layer for improved conductivity.  
         [0073]    Referring to FIG. 2, the LED driving power supply voltage VDDH is supplied to the source nodes S 1 -S 96  of driving transistors M 1 -M 96 , and to the source electrodes of reference transistors M 0 , M 97 . Resistors R 0 -R 96  and R 201 -R 203  model the resistance of the VDDH electrode  306  and its bonding wires, as in FIG. 24, the source electrodes of the reference transistors M 0 , M 97  being connected to nodes S 1 , S 96  through resistors R 0 , R 96 . The drain currents of the driving transistors M 1 -M 96  are supplied to respective LEDs D 1 -D 96 . The drain currents of the reference transistors M 0 , M 97  are reference currents Iref 1 , Iref 2 .  
         [0074]    [0074]FIG. 3 shows the connection relationships of the pre-buffers, control voltage generators, and their peripheral circuits for three dots (dot  1 , dot  95 , dot  96 ), omitting the circuit elements corresponding to dots  2  to  94  for clarity. LEDs D 1 , . . . , D 95 , D 96  are driven by transistors M 1 , . . . , M 95 , M 96  in the same way that LED LD 1  was driven by transistor Tr 1  in FIG. 21. Similarly, transistors TP 1 , . . . , TP 95 , TP 96 , transistors TN 1 , . . . , TN 95 , TN 96 , AND gates AD 1 , . . . , AD 95 , AD 96 , and latches LT 1 , . . . , LT 95 , LT 96  function in the same way as transistor TP 1 , transistor TN 1 , AND gate AD 1 , and latch LT 1  in FIG. 21.  
         [0075]    One of the input terminals of each AND gate AD 1 , . . . , AD 95 , AD 96  is connected to the output terminal of the corresponding latch LT 1 , . . . , LT 95 , LT 96 . The other input terminals of all the AND gates are connected to the output terminal of inverter G 0 . Control voltage generators  321 ,  322 , which correspond to control voltage generator  100   f  in FIG. 21, generate respective control voltages Vcontrol 1  and Vcontrol 2 . Their reference resistances Rref 1  and Rref 2 , which are used to sense the reference currents Iref 1  and Iref 2 , are preferably located near the center of the row of input-output electrodes  301  in FIG. 1. Resistors r 1 , . . . , r 94 , r 95  model the wiring resistance of the conductive member  305 . The polysilicon material (or polysilicon with a tungsten silicide layer) used in the conductive member  305  has a higher sheet resistance than aluminum wiring.  
         [0076]    The voltage VDDH supplied to the source electrode of reference transistor M 0  is substantially the voltage at node S 1  in FIG. 2, while the voltage VDDH supplied to the source electrode of reference transistor M 97  is substantially the voltage at node S 96 . The current supplied by driving transistor M 1  is proportional to the reference current Iref 1  in control voltage generator  321 , while the current supplied by driving transistor M 96  is similarly proportional to the reference current Iref 2  in control voltage generator  322 .  
         [0077]    Next, the operation of the above driver IC will be described with reference to dot  1 . The driver IC is assumed to be used in an LED head having the structure shown in FIGS. 18 and 19, and it is assumed here that a high logic level in the printing data functions as a command to turn on an LED.  
         [0078]    The print data signal HD-DATA is transferred into the shift registers  100   a  in FIG. 19 in the driver ICs. The printing control unit  1  sends the LED head  19  the number of clock pulses (HD-CLK) necessary to transfer one line of dot data. When the transfer of data for one line is completed, the printing control unit  1  activates the latch signal HD-LOAD, and the data held in the shift registers  100   a  are latched by the latch circuits  100   b.  The printing control unit  1  then activates the strobe signal HD-STB-N to turn on the LEDs.  
         [0079]    The logic of the strobe signal HD-STB-N (active low) is inverted by inverter G 0  in FIG. 3. The AND gate AD 1  outputs the logical AND of the resulting positive-logic strobe signal and the signal latched in latch circuit LT 1 . If the signal latched in latch circuit LT 1  has the high logic level, accordingly, the output of AND gate AD 1  changes from the low to the high logic level. The p-channel MOS transistor TP 1  and n-channel MOS transistor TN 1  constitute an inverter that inverts the output of AND gate AD 1 . The output signal of this inverter circuit changes from a potential substantially equal to VDDH to a potential substantially equal to Vcontrol 1 . The gate potential of p-channel MOS transistor M 1  likewise changes from substantially VDDH to substantially Vcontrol 1 , switching on transistor M 1  and supplying driving current to LED D 1 .  
         [0080]    Let L and W be the gate length and the gate width, respectively, of driving transistor M 1 , and Wref 1  be the gate width of reference transistor M 0 . The gate length of reference transistor M 0  is equal to the gate length L of driving transistor M 1 . As these two p-channel MOS transistors M 1  and M 0  have the same gate-source voltage (Vgs), the relationship between the LED driving current Io and reference current Iref 1  can be obtained from the following equations. 
           Io =β( W/L )( Vgs−Vt ) 2   
           Iref   1 =β( Wref   1 / L )( Vgs−Vt ) 2   
         [0081]    where Vt is the MOS transistor threshold voltage. Since the two p-channel MOS transistors M 0  and M 1  are mutually adjacent, they have substantially the same threshold voltage Vt, and the same constant of proportionality β.  
         [0082]    From the above equations, the relationship between the driving current Io and reference current Iref 1  can be expressed as follows. 
           Io/Iref   1 = W/Wref   1 = K   
         [0083]    The ratio K between the two currents is referred to as the mirror ratio.  
         [0084]    A similar relationship holds between driving transistor M 96  and the other control voltage generator  322 , comprising an operational amplifier  200 , reference resistance Rref 2 , and reference transistor M 97 . The relationship between the driving current Io supplied by transistor M 97  and reference current Iref 2  can be expressed as follows. 
           Io/Iref   2 = W/Wref   2 = K   
         [0085]    where Wref 2  is the gate width of reference transistor M 97 . In this embodiment Wref 2  is equal to Wref 1 , although this need not be true in general.  
         [0086]    If the reference resistances Rref 1 , Rref 2  are mutually adjacent and have the same planar form, they will have substantially identical resistance values. The two reference currents Iref 1 , Iref 2  will therefore be substantially equal. The drain currents of the reference transistors M 0 , M 97  will then be substantially equal, even though these reference transistors are positioned at mutually opposite ends of the driver IC. Consequently, the drain currents of driving transistors M 1  and M 96  will be substantially identical. The drain currents of transistors M 1  and M 96  are the currents that drive LEDs D 1  and D 96  to form dot  1  and dot  96 .  
         [0087]    Thus although the proportionality constant β and MOS transistor threshold voltage Vt in the above equations vary across the driver IC chip, the driving currents supplied at the two ends of the array will be the same. The values of the reference resistances Rref 1 , Rref 2  may vary from one driver IC to another, due to unavoidable manufacturing process variations, but it is a simple matter to divide the driver ICs into groups based on their driving current values. Driver ICs in the same group will then have substantially identical reference resistance values. If an LED head is made from driver ICs taken from the same group, all of its constituent driver ICs will have substantially identical reference resistance values, and the drain currents of the driving transistors M 1  and M 96  at the two ends of these driver ICs will all be substantially equal.  
         [0088]    Accordingly, as shown in FIG. 4, there will be no abrupt changes in driving current from one driver IC to the next in the LED head. Moreover, although there may still be some variation in driving current within each driver IC, the driving current will not increase or decrease monotonically as it did in the prior art (FIG. 20). The variation within each driver IC is therefore reduced, the mean driving current value does not depart greatly from the value determined by the reference current, and the total range of variation for the whole LED head will in general be no larger than the range ΔI allowed for a single driver IC.  
         [0089]    The variations in FIG. 4 can be explained as follows. In FIG. 3, the control voltages Vcontrol 1  and Vcontrol 2  are applied to the two ends of a resistance ladder circuit comprising resistances r 1 , . . . , r 94 , r 95  connected in series. The resistances r 1 , . . . , r 94 , r 95  are the resistance of wiring sections of equal width and equal length, so all have substantially the same value. The control voltage potentials at intermediate nodes in the resistance ladder therefore vary linearly between Vcontrol 1  and Vcontrol 2 , according to the node position. The node potentials of the resistance ladder comprising resistance r 1 , . . . , r 94 , r 95 , and hence the gate-source voltage of transistors M 1 , . . . , M 95 , M 96 , thus increase or decrease linearly across the chip. This cancels out any linear variation in the transistor threshold value Vt, but the Vt variation may include nonlinear components due to various factors in the IC fabrication process. This accounts for the residual variations in driving current shown in FIG. 4.  
         [0090]    The variations within each driver IC in FIG. 4, however, are only about half as large as the conventional variations shown in FIG. 20, and since the driving currents at the adjacent ends of adjacent driver ICs are substantially equal, variations in driving current in the LED head as a whole are reduced to less than half the conventional value. The first embodiment accordingly provides high printing quality without significant unevenness in print density.  
         [0091]    [0091]FIG. 5 schematically shows the layout of a driver IC for driving an array of driven elements according to a second embodiment of the invention. Repeated descriptions of elements appearing in FIG. 1 will be omitted.  
         [0092]    The second embodiment differs from the first embodiment in that, instead of two reference transistors positioned at respective ends of the driver IC chip, there is just one reference transistor positioned in the center of the chip, and control voltage adjustment circuits are positioned at both ends of the chip. The reference transistor is indicated by hatching in FIG. 5; the control voltage adjustment circuits will be shown in FIG. 7.  
         [0093]    [0093]FIG. 6 is an equivalent circuit diagram showing the driving transistors in this driver IC and the driven LEDs. Although the reference transistor M 0  is shown at the right end of this drawing, it is physically positioned at the center of the row of driving transistors, with its source electrode connected to node S 48 . Reference current Iref flows from the drain electrode of reference transistor M 0  to a reference resistance (not visible). As in the first embodiment, the reference transistor M 0  has the same gate length L as driving transistors M 1 -M 96 .  
         [0094]    Since the second embodiment has only one reference transistor M 0 , it has only one control voltage generator. FIG. 7 shows the connection relationships of the control voltage generator  333  and the pre-buffers and associated circuits for dot 1 , dot 2 , dot 49 , and dot 96 .  
         [0095]    The two control voltage adjustment circuits  341 ,  342  are both identical, each having UP and DOWN input terminals, a VDDH terminal, and a control voltage adjustment output terminal. A command signal L+ (described below) is input to the UP terminal of control voltage adjustment circuit  342 ; a command signal L− (described below) is input to the DOWN terminal. Control voltage adjustment circuit  342  also has a VDDH terminal connected to node S 96  in FIG. 6, receiving the voltage supplied to the source electrode of driving transistor M 96 , and produces an adjusted control voltage Vcontrol 2  at a control voltage adjustment output terminal, which is connected to the end of the conductive member  305  near pre-buffer G 96 . Similarly, command signals R+ and R− (described below) are input to the UP and DOWN terminals of control voltage adjustment circuit  341 , the VDDH terminal of which is connected to node S 1  in FIG. 6 to receive the voltage applied to the source electrode of driving transistor M 1 . This control voltage adjustment circuit  341  produces an adjusted control voltage Vcontrol 1  at its control voltage adjustment output terminal, which is connected to the end of the conductive member  305  near pre-buffer G 1 .  
         [0096]    [0096]FIG. 8 shows the internal structure of the control voltage adjustment circuits  341 ,  342 . Each control voltage adjustment circuit includes four p-channel MOS transistors  401 - 404 , four n-channel MOS transistors  405 - 408 , and a pair of inverters  409 ,  410 .  
         [0097]    Transistors  403  and  405  form an analog switch controlled from the DOWN input terminal, which is coupled to the gate electrode of transistor  405  and through inverter  409  to the gate electrode of transistor  403 . Transistors  404  and  406  form an analog switch controlled from the UP input terminal, which is coupled to the gate electrode of transistor  406  and through inverter  410  to the gate electrode of transistor  404 . The two analog switches are interconnected at a connecting node, and are in series with transistors  401  and  407 . The connecting node is connected to the control voltage adjustment output terminal, here marked Vcontrol, and to the gate electrode of transistor  402 . Vcontrol in FIG. 8 is equivalent to either Vcontrol 1  or Vcontrol 2  in FIG. 7.  
         [0098]    The source electrodes of transistors  401  and  402  receive VDDH from node S 1  or S 96  in FIG. 6. The source electrodes of transistors  407  and  408  are connected to a ground node. The drain electrode of transistor  402  is connected to the drain electrode of transistor  408 , and to the gate electrodes of transistors  407  and  408 , which thus operate as a current mirror. Transistor  401  has its gate and drain electrodes interconnected, and operates as a current mirror with transistor  402  when the analog switch comprising transistors  403  and  405  is in the conducting state. Transistors  402  and  408  are thus connected in series between VDDH and ground, and in parallel with transistors  401  and  407  and the analog switches.  
         [0099]    Transistors  401  and  402  have the same gate length as the driving transistors M 1 -M 96 , and since they also have the same gate-source voltage, their drain currents Ip 1  and Ip 2  mirror the LED driving current. The drain currents In 1  and In 2  of transistors  407  and  408  also mirror the LED driving current, since In 2  is equal to Ip 2 .  
         [0100]    [0100]FIGS. 9A and 9B show decoders  421 ,  422  that generate the command signals input to the control voltage adjustment circuits  341 ,  342 . The input terminals A 1 , A 0  of decoder  422  are pulled up to the power supply VDD through respective resistances  425 ,  426 , and are connected to respective current adjustment terminals ADJ-L 1 , ADJ-L 0 , which are among the input electrodes  301  (FIG. 5) of the driver IC. Similarly, the input terminals A 1 , A 0  of decoder  421  are pulled up through resistances  423 ,  424 , and are connected to current adjustment terminals ADJ-R 1 , ADJ-R 0 , which are also among the input electrodes  301  of the driver IC. Decoder  421  outputs command signals R− and R+ from output terminals Y 1  and Y 2 , respectively. Decoder  422  outputs command signals L− and L+ from output terminals Y 1  and Y 2 , respectively.  
         [0101]    [0101]FIG. 10 is a circuit diagram of the above decoders. Each decoder comprises a pair of AND gates  431 ,  432  and a pair of inverters  433 ,  434 . Input terminal A 1  of the decoder is connected to the input terminal of inverter  433  and one input terminal of AND gate  431 , while input terminal A 0  is connected to the input terminal of inverter  434  and one input terminal of AND gate  432 . The outputs of inverters  433 ,  434  are connected to the other input terminals of AND gates  432 ,  431 , respectively. The AND gates  431  and  432  output the command signals L+ and L− or R+ and R− in FIGS. 9A and 9B.  
         [0102]    Next, the operation of control voltage adjustment circuits  341 ,  342  will be described.  
         [0103]    To reduce the driving current supplied to the LED (D 1  or D 96 ) at one end of the array, the DOWN signal is set to the high logic level and the UP signal to the low logic level by a procedure described below, so the output of inverter  409  is low, the output of inverter  410  is high, the analog switch comprising transistors  403  and  405  is in the conducting state, and the analog switch comprising transistors  404  and  406  is in the non-conducting state. The control voltage adjustment circuit  341  or  342  now sources current Ip 1  from VDDH through transistor  401  to the conductive member  305 , thus to the Vcontrol output terminal of the control voltage generator  333  and the output terminal of the operational amplifier  200 . The flow of this current through the wiring resistance of the conductive member  305  raises the potential Vcontrol 1  or Vcontrol 2  at the output terminal of the control voltage adjustment circuit  341  or  342 , reducing the gate-source voltage of transistor M 1  or M 96  and decreasing its drain current, i.e., the LED driving current, which is mirrored by the drain current Ip 1 .  
         [0104]    In the specific case in which control voltage Vcontrol 2  is raised, the drain current Ip 1  flows through a series resistance circuit consisting of wiring resistances r 48 , r 49 , . . . , r 94 , r 95 . The potential at resistance r 48  is maintained at Vcontrol by the control voltage generator  333 . The potentials of the successive nodes between r 48  and r 95  increase linearly from Vcontrol to Vcontrol 2 , because the conductive member  305  has uniform wiring width and is divided at equal intervals into resistances r 1 , . . . , r 94 , r 95 , which thus have identical resistance values. These node potentials are supplied as gate potentials to driving transistors M 49 , . . . , M 95 , M 96 . The gate-source voltages and drain currents of transistors M 49 , . . . , M 95 , M 96  therefore decrease monotonically from M 49  to M 96 .  
         [0105]    A similar relation holds for transistors M 1 , M 2 , . . . , M 47 , resistances r 1 , r 2 , . . . , r 47 , and control voltage adjustment circuit  341 .  
         [0106]    Next, an adjustment to increase the driving current of the LED (D 1  or D 96 ) at one end of the driver IC will be described. In this adjustment, the UP signal is set to the high logic level and the DOWN signal to the low logic level. The output of inverter  409  is high, the output of inverter  410  is low, the analog switch comprising transistors  403  and  405  is in the non-conducting state, and the analog switch comprising transistors  404  and  406  is in the conducting state. The control voltage adjustment circuit  341  or  342  now sinks current from the conductive member  305  through transistor  407  to ground, this current (In 1 ) mirroring the LED driving current of driving transistor M 1  or M 96 . As this current In 1  flows through the wiring resistances (r 48 , . . . , r 1  or r 48 , . . . , r 95 ) in the conductive member  305 , a voltage drop occurs, lowering the potential Vcontrol 1  or Vcontrol 2  at the output terminal of control voltage adjustment circuit  341  or  342 . As a result, the gate-source voltage of transistor M 1  or M 96  increases, so its drain current, i.e., the driving current, increases.  
         [0107]    When it is not necessary to increase or decrease the driving current, the UP and DOWN signals are both preferably placed at the low logic level by the procedure described below, so that the outputs of inverters  409 ,  410  are both high and the analog switches consisting of transistors  403  and  405  and transistors  404  and  406  are both in the non-conducting state. As a result, no current flows between the control voltage adjustment circuit and the conductive member  305 , and the control voltage is not adjusted either upward or downward.  
         [0108]    [0108]FIG. 11 is a truth table illustrating various adjustment modes. When the LED head is manufactured, mode  0  is initially selected by wire-bonding the ADJ-L 1 , ADJ-L 0 , ADJ-R 1 , and ADJ-R 0  terminals to a ground electrode on the above-mentioned printed wiring board. When the LED head is inspected, the amount of the light emitted by each LED in this condition is measured. Since ADJ-L 1 , ADJ-L 0 , ADJ-R 1 , and ADJ-R 0  are all at the low logic level, the signals output from decoder terminals Y 1  and Y 2  in the control voltage adjustment circuits  341 ,  342  are also at the low logic level. All of the analog switches in the control voltage adjustment circuits  341 ,  342  are therefore in the non-conducting state, and the control voltage is not adjusted on either the left or right side of the driver C.  
         [0109]    The inspection result in mode  0  is used to decide whether to increase or decrease the driving currents on the left and right sides of the driver IC. If, for example, the LEDs driven from the left side of the driver IC emit too much light, the bonding wire that connects the ADJ-L 0  electrode to ground is removed. The ADJ-L 0  electrode and input terminal A 0  of decoder  422  are then pulled up to the high logic level, corresponding to mode  1  in FIG. 11, through resistor  426 , so the L− signal output from terminal Y 1  of decoder  422  to the DOWN input terminal of control voltage adjustment circuit  342  goes high, decreasing the driving current on the left side of the driver IC. If the LEDs driven from the left side of the driver IC emit too little light, the bonding wire that connects the ADJ-L 1  electrode to ground is removed, corresponding to mode  2  in FIG. 11, and the L+ signal goes high, increasing the driving current on the left side of the driver IC. Similary, the bonding wire can be removed from the ADJ-R 0  electrode to decrease the driving current, or from the ADJ-R 1  electrode to increase the driving current, on the right side of the driver IC.  
         [0110]    In a variation of this operation, the ADJ-L 0 , ADJ-L 1 , ADJ-R 0 , and ADJ-R 1  electrodes are initially left unconnected (mode  3  in FIG. 11). A bonding wire can then be attached between ADJ-L 0  or ADJ-R 0  and ground to increase the driving current, or between ADJ-L 1  or ADJ-R 1  and ground to decrease the driving current, on the corresponding side of the driver IC.  
         [0111]    [0111]FIG. 12 shows an example of dot-to-dot variations in driving current in an LED head according to the second embodiment. The driver ICs in this LED head have been selected for uniform driving current at the center of each driver IC chip, and the driving current has been adjusted as necessary on the left side and the right side of each chip as described above, reducing the range of driving-current variation (ΔI) within each chip. The dot-to-dot variation in driving current within each driver IC is gradual, and any abrupt changes that may occur between two mutually adjacent dots in different driver IC chips are much smaller than the abrupt changes that can occur in a conventional LED head (FIG. 20). Variations in printing density caused by dot-to-dot variations in driving current can thus be considerably reduced as compared with the prior art.  
         [0112]    [0112]FIG. 13 schematically shows the layout of a driver IC in accordance with a third embodiment of the invention. Descriptions of elements identical to the corresponding elements in FIG. 5 will be omitted.  
         [0113]    In the third embodiment, as in the second embodiment, the control voltage is generated at the center of the driver IC chip and adjusted at both ends of the chip. The third embodiment differs from the second embodiment in that the LED driving power supply voltage VDDH is detected by reference transistors positioned at both ends of the chip. The two reference transistors M 0  and M 97  are indicated by hatching in FIG. 13.  
         [0114]    [0114]FIG. 14 is an equivalent circuit showing the driving transistors in this driver IC and the driven LEDs. The two reference transistors M 0  and M 97  have the same gate length as the LED driving transistors M 1 -M 96 .  
         [0115]    [0115]FIG. 15 shows the connection relationships of the control voltage generator  333 , the control voltage adjustment circuits  341 ,  342 , and the pre-buffers and their associated circuits in the third embodiment. The reference resistance Rref in the control voltage generator  333  is connected to the drain electrodes of both reference transistors M 0 , M 97 . The gate electrodes of reference transistors M 0 , M 97  are connected to the conductive member  305  near the control voltage adjustment circuits  341 ,  342 , respectively.  
         [0116]    The control voltage Vcontrol at the center of the chip is therefore generated according to the average of the LED driving power supply voltage VDDH at the left and right ends of the chip, regardless of how the LEDs are driven. This arrangement is more robust than the conventional arrangement in which there is only one reference transistor, at one end of the chip, for the following reason.  
         [0117]    In a given dot line, the left and right halves of the driver IC may drive significantly different numbers of LEDs. For example, LEDs D 1  to D 48  may all be driven simultaneously, while only a few of LEDs D 49  to D 96  are driven. VDDH will then be significantly lower at the right end of the array than in the middle of the array and at the left end. If there is only the conventional single reference transistor M 0  disposed adjacent to driving transistor M 1  at the right end of the array, feedback control will compensate for the reduced VDDH value at the right end by decreasing the control voltage Vcontrol until driving transistor M 1  supplies the correct amount of driving current. Driving transistors near the middle of the array and on the left side will then supply too much current. In the third embodiment, since VDDH is detected at both ends of the chip, the reduced VDDH potential at the right end of the chip is averaged with the normal VDDH potential at the left end of the chip, so Vcontrol is not reduced as much and the driving current remains closer to the correct value overall.  
         [0118]    The third embodiment provides the same effect as the second embodiment in reducing variations in driving current by adjusting the control voltage at both ends of the conductive member  305 , and is also less likely to produce unwanted driving-current variations due to localized VDDH voltage drops.  
         [0119]    Although the present invention has been described with reference an LED head in an electrophotographic printer, it is not limited to this application. The invention can be usefully applied for driving arrays of various types of elements, including resistive heat-emitting elements in thermal printers, and display elements in matrix-type display apparatus.  
         [0120]    The present invention is particularly useful when practiced in an array head comprising a plurality of driver ICs, since it can reduce output differences between adjacent elements driven from different ICs, but the invention also reduces output variations in elements driven from a single IC.  
         [0121]    Those skilled in the art will recognize that many variations in the above embodiments are possible within the scope of the appended claims.