Abstract:
Circuit for discharging to ground, supplied by a supply voltage, comprising a reference voltage, a negative potential node, first circuitry adapted to couple the negative potential node to the reference voltage in response to a control signal. Second circuitry is provided adapted to determine in the first circuitry the passage of a controlled current for the discharge of the negative potential node.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a circuit for discharging to ground, with control of the discharge current, a node having a negative potential, to which a large capacitance is connected, particularly for use in a non volatile memory, such as a Flash EEPROM or EEPROM memory, in operations in which the initial conditions of the voltage values of the nodes are to be restored. 
     2. Discussion of the Related Art 
     Many conventional non volatile memory devices, especially those having a single voltage supply, need to internally generate voltage values out of the range between ground and the supply voltage. There exist therefore negative voltage levels and voltage levels higher than the supply voltage, which are essential for performing the operations of writing and erasing of the memory cells. The nodes of the circuit with negative voltage values, once said operations are terminated, must be restored to their initial voltage values. 
     For instance, making reference to FIG. 1, a Flash EEPROM memory is schematically represented. FIG. 1 could as well represent a sector of a Flash EEPROM memory, in the case this includes more sectors selectively addressable. The memory comprises memory cells  1 , constituted by floating-gate N-channel MOS transistors, conventionally arranged in rows WLO-WLn (“word lines”) and columns BLO-BLm (“bit lines”) to form a matrix. The rows of the matrix are accessible through a row decoder ROW 13 DEC that receives and decodes row address signals RADD. Such decoder includes a plurality of final driving stages of the rows, each one substantially constituted by a CMOS inverter  2  supplied by a voltage VPCX and a voltage node RDS, to which a capacitance  3  is connected. Node RDS can be selectively connected to the ground of the integrated circuit in the case of reading and programming, as well as during erasing, if the particular sector must not be erased. To erase the sector, node RDS is instead connected to a line carrying a negative voltage value (V N ), generated by a charge pump  4 . In this last case, the inputs of all the final inverters  2  are brought to the voltage VPCX. 
     The management of the negative voltage values in a circuit built in CMOS technology can pose some difficulties, in that it may not be possible to apply negative voltages of desired value to the source or drain electrodes of the N-channel MOSFETs, without forward biasing the source/substrate or drain/substrate junctions, since the substrate connects the integrated circuit to ground. 
     Such a problem is solved using CMOS technology that allows isolation of the bulk electrode of the N-chanTel MOSFET transistors from the substrate of the device which is necessarily connected to ground. 
     In FIG. 2, for instance, the section of an N-channel MOS transistor is shown, realized in a triple well technology, and in FIG. 3 the circuit symbol that represents such transistor is shown. In FIG. 2 a deep P type substrate  6  is connected to ground. An N type tub  7  formed inside the substrate  6  is connected to the supply voltage VDD; inside tub  7 , another P type tub  8  is formed with two N+ doped zones corresponding to the drain and source electrodes; the electrode of the tub  8  is connected to the source electrode. The substrate  6  and the tubs  7  and  8  are connected to the respective external electrodes thereof through contact regions that have a higher doping. 
     With this triple well technology the N-channel MOSFET has the N type tub  7  such that by applying the positive supply voltage VDD to this tub it is possible to reverse bias all the parasitic junctions existing inside the structure, even when negative voltages are applied to the source electrode, which is connected to the bulk electrode  8  of the transistor. 
     The way to discharge a node from a voltage value to another value having a small absolute value, provides for connecting the node to a node with constant potential value equal to the final value, through a transresistance. For instance, with reference to FIG. 1, switch means  5  are present that are closed between node RDS and the ground of the memory. 
     Such solution has the drawback that results in a transient whose duration depends, through an exponential relationship, on a time constant directly proportional to the value of the resistance R and of the capacitance C associated with the node that is to be discharged (μ=R*C). When the capacitance associated with the node has a high value, the transient lasts for too long a time. Therefore, to speed up the process it is necessary to decrease the value of the discharge resistance, in such way to have a time constant of acceptable values. 
     However, by decreasing the value of the discharge resistance, the value of the current that flows through such resistance is increased and this creates undesired effects in the circuit: 
     a first effect is due to the fact that a high value current, injected in a node connected to a real (i.e., not ideal) voltage generator, whose internal impedance is therefore different from zero, can cause an undesired variation of the potential of this node; in the case such current is injected in reference nodes such as the ground and the supply voltage, malfunctions of the whole circuit can be caused; 
     a second undesired effect of the high values of current is the high dissipation of power for Joule effect, that can raise the operating temperature of the circuit component and reduce the reliability thereof; 
     a further complication derives from the fact that the cross-section of the conductors that form the electric connections inside the circuit have to be sized according to the maximum value of current density that can transit therethrough, to avoid phenomenons of electromigration, and a high value of the current requires therefore a large conductor cross-section, with a consequent increase of area and of parasitic capacitances. 
     In view of the state of the art described, it is an object of the present invention to provide a circuit capable of discharging to ground a node whose potential has negative values and to which a high capacitance is possibly associated, without incurring in the aforementioned problems. 
     SUMMARY OF THE INVENTION 
     According to the present invention, this and other objects are achieved through a circuit for discharging to ground and fed by a supply voltage, comprising a reference voltage, a node with negative potential, first circuit means for coupling the node with negative potential to the reference voltage in response to a control signal, and comprising second circuit means for determining, in the first circuit means, the passage of a controlled current for the discharge of the negative potential node. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features and advantages of the present invention will result evident from the following detailed description of one embodiment thereof, illustrated by way of a non limiting example in the annexed drawings, wherein: 
     FIG. 1 schematically shows a conventional Flash EEPROM memory; 
     FIG.  2  and FIG. 3 respectively represent the cross-section and the circuit symbol of an N-channel MOS transistor realized in triple well technology, usable in an embodiment of the present invention; 
     FIG. 4 is a circuit diagram of a circuit of discharge according an embodiment of the present invention; 
     FIG. 5 is a circuit diagram of an inverting level translator circuit, usable in an embodiment of the present invention; 
     FIG. 6 schematically shows a Flash EEPROM memory including the circuit of the present invention. 
    
    
     DETAILED DESCRIPTION 
     FIG. 4 is a schematic diagram of a circuit for discharging to ground according to an embodiment of the present invention; such circuit is supplied by a voltage VDD, and by a reference voltage (ground=GND) that also acts as a first input of the circuit. The circuit further receives a second input constituted by a voltage of negative value VNEG. 
     A control signal CNT is supplied to the circuit. Control signal CNT can take two logical levels, low (ground=GND) or high (VDD). 
     The circuit includes an inverting level translator circuit HV 1 , one embodiment of which being shown in FIG. 5, driven by the control signal CNT and whose output OUT 1  drives an N-channel MOSFET transistor M 7 . Transistor M 7  has the source electrode connected to the negative voltage VNEG and the drain electrode that drives an N-channel MOSFET M 8 . Transistor M 8  has in turn its source electrode connected to the negative voltage VNEG and its drain electrode connected to ground. The circuit includes two P-channel MOSFET M 1  and M 3 , supplied by the voltage VDD and connected to form a first current mirror, polarized by the current furnished by a reference current generator IREF. The gate electrode in common between the two MOSFETs M 1  and M 3  is connected to a third P-channel MOSFET M 2 , supplied by the voltage VDD and driven by the control signal CNT. 
     The output of the current mirror constituted by MOSFETs M 1  and M 3 , is connected to two MOSFETs M 4  and M 5 , respectively N-channel and P-channel: transistor M 4  is driven by the complement CNT 1  of the control signal, has the source electrode connected to ground and the drain electrode connected to transistor M 3 , while transistor M 5  has the gate electrode connected to ground, the drain electrode connected to a second current mirror formed by an N-channel MOSFET M 6  and by MOSFET M 8  and the source electrode connected to transistor M 3 . MOSFET M 6  has the source electrode connected to node VNEG and the drain electrode connected to transistor M 5 . 
     The inverting level translator HV 1  can take at the output thereof the values of voltage equal to VDD or VNEG depending on the fact that at the input thereof a signal of voltage equal to 0V or VDD is present, respectively. 
     The N-channel MOSFETs M 6 , M 7  and M 8 , connected to the node with negative potential VNEG, are realized in a triple well technology, i.e., they have an internal structure equal to that shown in FIG.  1 . 
     The bulk electrode of the P-channel MOSFET M 5  is connected to the source electrode thereof, to avoid an excessive difference of potential across the substrate/drain junction. 
     FIG. 5 shows a circuit diagram of an inverting level translator circuit, usable in an embodiment of the present invention, corresponding to the circuit block HV 1  of FIG.  4 . 
     Such circuit receives the control signal CNT, it outputs the signal OUT 1  and it is connected among the supply voltage VDD and the negative voltage VNEG. 
     The circuit has a symmetrical structure and comprises a pair of P-channel MOSFETs T 2  and T 1 , with the source electrode connected to the supply voltage VDD and respectively driven by the control signal CNT and by a logical complement CNT 2  thereof. Signals CNT and CNT 2  also drive respectively two N-channel MOSFETs T 8  and T 7 , that have the respective source electrodes connected to ground and the drain electrodes connected to the drain electrodes of the two MOSFETs T 2  and T 1 , indicated in the drawing with the nodes ND 2  and ND 1 . 
     To nodes ND 2  and ND 1  there are also respectively connected the source electrodes of two P-channel MOSFETs T 4  and T 3 , that have the gate electrodes connected to ground. The drain electrode of transistor T 4  corresponds to the output node OUT 1 . 
     The circuit further includes two N-channel MOSFETs T 6  and T 5  realized in triple well technology, fed to the source thereof by the voltage VNEG. The gate electrode of transistor T 5  is connected, together with the drain electrode of transistor T 6 , to the output node OUT 1  and symmetrically the gate electrode of transistor T 6  is connected to the drain electrode of transistor T 5 . Transistors T 5  and T 6  form therefore a “latch” structure. 
     The operation of such inverting level translator circuit HV 1  will be now analyzed in detail. 
     In the case in which the control signal CNT is at the high logical level (of value equal to VDD), transistor T 2  is off while transistor T 8  is turned on and, as a result, node ND 2  has a voltage value equal to the reference voltage (ground). Transistor T 4  is off and uncouples node ND 2  from the output node OUT 1 . 
     Transistor T 1 , being driven by the complement CNT 2  of the control signal, is turned on while transistor T 7  is off and accordingly node NDI has a voltage of value equal to VDD. Such value turns on transistor T 3  and therefore the node corresponding to the drain electrode of transistor T 3  has a voltage value equal to VDD. Such node, driving transistor T 6 , turns this last on and therefore the output node OUT 1  takes a value of voltage equal to VNEG. Transistor T 5  is off. 
     If now it is desired to set the output node OUT 1  at a voltage value equal to VDD, it is sufficient that the control signal CNT is set to the low logical level: as a result of the symmetry of the structure, all the transistors that before were turned on will now be off and vice versa, those that were off will be turned on, allowing the output node to take the desired value of voltage equal to VDD. 
     The operation of the circuit of FIG. 4 will be now analyzed in detail. 
     In the case in which the control signal CNT is at the high logical level, the inverting level translator HV 1 , provides, at the output node OUT 1  a negative voltage value VNEG that turns transistor M 7  off. The control signal CNT and complement CNT 1  also turn transistors M 2  and M 4  off, respectively, and therefore at the output of the current mirror formed by the two transistors M 1  and M 3  which are turned on, a current I 1  circulates. Current I 1  has a constant value dependent on the value of the current supplied by the current generator IREF and on the dimensions of transistors M 1  and M 3 . 
     Transistor M 5  is turned on and it allows the current I 1  in output of the first current mirror to flow in the second current mirror by transistors M 6  and M 8 , which are turned on: in this way at the output of the second current mirror, that is on the negative potential node VNEG, a constant current I 2  is provided. Current I 2  has a known value, dependent on the value of the current generated by the current generator IREF and on the dimensions of transistors M 1  and M 3 , as well as on the dimensions of transistors M 6  and M 8 . Transistor M 8  is the circuit component through which the discharge of node VNEG to ground is realized, and the discharge current exactly corresponds to the current  12  at the output of the second current mirror, that is constant and of controlled value. 
     In the case in which the control signal CNT is at the low logical level (ground), transistor M 2  is turned on and the two MOSFETs M 1  and M 3  are off; transistor M 4  is turned on and this turns off transistor MS, being the source electrode thereof connected to ground. The two current mirrors are consequently uncoupled. 
     The output OUT 1  of the inverting level translator HV 1  has a voltage value equal to VDD and therefore transistor M 7  is turned on; the two transistors M 6  and M 8  have the gate electrodes at a voltage value equal to VNEB and they are therefore off. The turning off of transistor M 8  prevents to the node with negative potential VNEG from discharging. 
     The circuit of the present invention is useful in a non-volatile, electrically programmable and erasable memory, for instance the Flash EEPROM memory shown in FIG.  6 . 
     Such figure, substantially analogous to FIG. 1, shows the way a circuit  50  according to the present invention, for instance the circuit of FIG. 4, can be used in place of the conventional switch means  5 . As a result of this, it is possible to achieve a controlled-current discharge of capacitance  3 , associated with node RDS, from the negative voltage value V N , generated by the charge pump  4  and used during erasing, to ground. 
     Having thus described at least one illustrative embodiment of the invention, various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only and is not intended as limiting. The invention is limited only as defined in the following claims and the equivalents thereto.