Abstract:
A delay-locked loop (DLL) circuit. In the evaluation period, the DLL circuit adjusts needed delay period of time for a reference clock signal by adjusting the amount of the used delay units which each of has fixed delay period of time digitally and controlling the delay period of time of the voltage control delay circuit analogically. In the locking period, the DLL circuit utilizes the delay time of the delay units, which is decided in the evaluation period, along with the voltage control delay circuit, to lock phase of the reference clock signal. In this way, the stability of the delay period of time of the voltage control delay circuit increases.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a delay-locked loop circuit, and more particularly, to the delay-locked loop circuit having wide frequency locking range and error-locking-avoiding function. 
         [0003]    2. Description of the Prior Art 
         [0004]    Please refer to  FIG. 1 .  FIG. 1  is a diagram illustrating a conventional delay-locked loop (DLL) circuit  100 . The DLL circuit  100  comprises a phase/frequency detector  110 , a current controller  120 , a capacitor C 1 , a voltage control delay line (VCDL)  130 , and a predetermined dummy delay  140 . 
         [0005]    Please continue referring to  FIG. 1 . The phase/frequency detector  110  comprises two input terminals for receiving a reference periodic signal CLK REF  and a feedback periodic signal CKL FB  respectively. The phase/frequency detector  110  determines the phase difference between the reference periodic signal CLK REF  and the feedback periodic signal CKL FB  and accordingly outputs the control signals S UP  or S DN . For the example, when the phase of the reference periodic signal CLK REF  is ahead of the phase of the feedback periodic signal CKL FB , the phase/frequency detector  110  outputs the control signal S UP ; otherwise, when the phase of the reference periodic signal CLK REF  falls behind the phase of the feedback periodic signal CKL FB , the phase/frequency detector  110  outputs the control signal S DN . 
         [0006]    Please continue referring to  FIG. 1 . The current controller  120  is coupled to the output terminal of the phase/frequency detector  110  for receiving the control signals S UP  or S DN . When the current controller  120  receives the control signal S UP , the current controller  120  sources current I X  with the predetermined magnitude (not shown) to capacitor C 1  for increasing the voltage V X ; when the current controller  120  receives the control signal S DN , the current controller  120  sinks the current I X  with the predetermined magnitude to the capacitor C 1  for decreasing the voltage V X . The capacitor C 1  is coupled between the output terminal of the current controller  120  and a ground terminal. 
         [0007]    Please continue referring to  FIG. 1 . The VCDL  130  comprises two input terminals. One input terminal of the VCDL  130  is utilized for receiving the reference periodic signal CLK REF , and the other input terminal of the VCDL  130  is coupled to the capacitor C 1  for receiving the voltage V X . The VCDL  130  delays the reference periodic signal CLK REF  by a corresponding period of time D X  (not shown) according to the voltage V X , and the delayed reference periodic signal CLK REF  is outputted as a delayed periodic signal CLK OUT . 
         [0008]    Please continue referring to  FIG. 1 . The predetermined dummy delay  140  is coupled between the output terminal of the VCDL  130  and the input terminal of the phase/frequency detector  110 . The predetermined dummy delay  140  further delays the received delayed periodic signal CLK OUT  by a predetermined period of time D P  in order to generate the feedback periodic signal CLK FB , and then the generated feedback periodic signal CLK FB  is fed to the phase/frequency detector  110 . 
         [0009]    Please refer to  FIG. 2 .  FIG. 2  is a timing diagram illustrating relationship between the reference periodic signal CLK REF  and the delay periodic signal CLK FB . As shown in  FIG. 2 , by using the conventional DLL circuit  100 , the phase of the delay periodic signal CKL OUT  is set to prior to the phase of the reference periodic signal CLK REF  by the predetermined phase P D  (similar to the above-mentioned predetermined period of time D P ). 
         [0010]    Please refer to  FIG. 3 .  FIG. 3  is a diagram illustrating the relationship between the voltage of the VCDL  130  and the delay time. The VCDL  130  controls the delay analogically. When a user needs to prolong the delay D X , the user can just increase the input voltage V X  of the VCDL  130 . As shown in  FIG. 3 , the axis of the voltage can be divided into three sections: section A, section B, and section C, in which the gradient is increasing gradually from the section A to section C. In other words, in section A, the variation of the voltage V X  has minor effect to the delay D X . On the contrary, the delay D X  varies enormously even when voltage V X  is just slightly changed in section C. Therefore, when the required delay D X  falls within the range of section C, the stability of the voltage V X  becomes very critical. This is because the slightly variation of the voltage V X  may greatly change the delay D X  and to consequently result a huge error. Accordingly, the conventional DLL circuit  100  limits options for the reference periodic signal CLK REF  and the delay phase, which is greatly inconvenient for the user. 
       SUMMARY OF THE INVENTION 
       [0011]    The present invention provides a delay-locked loop circuit with wide frequency locking range and error-locking avoiding function, for generating a delayed locking periodic signal according to a reference periodic signal, the delay-locked loop circuit comprises a phase/frequency detector, a voltage controller, a voltage controlled delay circuit, a predetermined delay circuit, an adjustable delay circuit, a first switch, a second switch, and a third switch. The phase/frequency detector, comprises a first input terminal for receiving the reference periodic signal; a second input terminal; a first output terminal, wherein the phase/frequency detector outputs a first controlling signal via the first output terminal of the phase/frequency detector according to signals at the first input terminal and the second input terminal of the phase/frequency detector; and a second output terminal, wherein the phase/frequency detector outputs a second controlling signal via the second output terminal of the phase/frequency detector according to signals at the first input terminal and the second input terminal of the phase/frequency detector. The voltage controller coupled to the first and the second output terminals of the phase/frequency detector, the voltage controller outputs a corresponded voltage level according to the first controlling signal or the second controlling signal. The voltage controlled delay circuit comprises: an input terminal for receiving the reference periodic signal; a control terminal coupled to the output terminal of the voltage controller; and an output terminal, wherein the voltage controlled delay circuit delays the received reference periodic signal according to the corresponded level voltage outputted from the voltage controller. The predetermined delay circuit delays a received signal for a first predetermined time, an output terminal of the predetermined delay circuit being coupled to the second input terminal of the phase/frequency detector. The adjustable delay circuit adjusts a delay time of the adjustable delay circuit. The first switch comprises: a first terminal couples to the output terminal of the voltage controlled delay circuit; a second terminal couples to an input terminal of the predetermined delay circuit; a third terminal couples to an input terminal of the adjustable delay circuit; and a control terminal is for coupling the first terminal of the first switch to the second terminal or the third terminal of the first switch according to signals received at the control terminal of the first switch. The second switch comprises: a first terminal is for outputting the delayed locking periodic signal; a second terminal couples to the output terminal of the predetermined delay circuit; a third terminal couples to an output terminal of the adjustable delay circuit; and a control terminal is for coupling the first terminal of the second switch to the second terminal or the third terminal of the second switch according to signals received at the control terminal of the second switch. The third switch comprises: a first terminal couples to the first terminal of the second switch; a second terminal couples to the input terminal of the adjustable delay circuit; a third terminal couples to the input terminal of the predetermined delay circuit; and a control terminal is for coupling the first terminal of the third switch to the second terminal or the third terminal of the third switch according to signals received at the control terminal of the third switch. 
         [0012]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]      FIG. 1  is a diagram illustrating a conventional DLL circuit. 
           [0014]      FIG. 2  is a timing diagram illustrating the relationship between a reference periodic signal and a delay periodic signal of the conventional DLL circuit. 
           [0015]      FIG. 3  is a diagram illustrating the relationship between the voltage and the delay of VCDL of the conventional DLL circuit. 
           [0016]      FIG. 4  is a diagram illustrating a DLL circuit according to an embodiment of the present invention. 
           [0017]      FIG. 5  is a diagram illustrating the DLL circuit of the present invention in the evaluation status. 
           [0018]      FIG. 6  is a diagram illustrating an adjustable delay circuit of the DLL circuit of the present invention in the evaluation status. 
           [0019]      FIG. 7  is a timing diagram illustrating the relationship between a reference periodic signal, delayed periodic signals, and a selected periodic signal. 
           [0020]      FIG. 8  is a diagram illustrating the DLL circuit of the present invention in the locking status. 
       
    
    
     DETAILED DESCRIPTION  
       [0021]    Please refer  FIG. 4 .  FIG. 4  is a diagram illustrating a DLL circuit  400  according to an embodiment of the present invention. The delay lock loop circuit  400  comprises a phase/frequency detector  410 , a voltage controller  421 , a startup voltage charging circuit  423 , a voltage controlled delay circuit  430 , three switches SW 1 , SW 2 , and SW 3 , a predetermined delay circuit  440 , a duty cycle correction (DCC) circuit  450 , an adjustable delay circuit  460 , and a frequency divider  470 . 
         [0022]    Please continue referring to  FIG. 4 . The phase/frequency detector  410  comprises two input terminals for respectively receiving a reference periodic signal CLK REF  and a feedback periodic signal CLK FB  that have been divided by the frequency divider  470 . Please note that, a divisor of the frequency divider  470  is set to one for brevity. In other words, the reference periodic signal CLK REF  and the feedback periodic signal CLK FB  that after being divided by the frequency divider  470  are same as the original reference periodic signal CLK REF  and the feedback periodic signal CLK FB  respectively. The phase/frequency detector  410  outputs a control signal S UP  and S DN  according to the reference periodic signal CLK REF  and a feedback periodic signal CLK FB  respectively. For example, when the phase of the reference periodic signal CLK REF  is ahead of the phase of the feedback periodic signal CLK FB , the phase/frequency detector  410  outputs the control signal S UP ; otherwise, when the phase of the reference periodic signal CLK REF  falls behind the phase of the feedback periodic signal CLK FB , the phase/frequency detector  410  outputs the control signal S DN . 
         [0023]    Please continue referring to  FIG. 4 . The voltage controller  421  comprises a current controller  420  and a charging circuit  422 . The charging circuit  422  comprises a capacitor C 3 , and the capacitor C 3  is coupled between an output terminal (node X) of the current controller  420  and a ground terminal. The current controller  420  is coupled to an output terminal of the phase/frequency detector  410  for receiving the control signal S UP  and S DN . When the current controller  420  receives the control signal S UP , the current controller  420  sources a current I X  with the predetermined magnitude (not shown) to the node X for increasing the voltage V X ; when the current controller  420  receives the control signal S DN , the current controller  420  sinks the current I X  with the predetermined magnitude from the node X for decreasing the voltage V X . 
         [0024]    Please continue referring to  FIG. 4 . The voltage controlled delay circuit  430  comprises two input terminals. One of the input terminals of the voltage controlled delay circuit  430  receives the reference periodic signal CLK REF , and the other one of the voltage controlled delay circuit  430  is coupled to the node X for receiving the voltage V X . The voltage controlled delay circuit  430  delays the reference periodic signal CLK REF  by a corresponding period of time D X  (not shown) according to the magnitude of the V X . 
         [0025]    Please continue referring to  FIG. 4 . The switch SW 1  comprises a first terminal  1 , a second terminal  2 , a third terminal  3 , and a control terminal C. The first terminal  1  of the switch SW 1  is coupled to an output terminal of the voltage controlled delay circuit  430 , the second terminal  2  of the switch SW 1  is coupled to an input terminal I 3  of the predetermined delay circuit  440 , the third terminal  3  of the switch SW 1  is coupled to an input terminal I 1  of the adjustable delay circuit  460 , and the control terminal C of the switch SW 1  receives an evaluation/lock signal S X . When the evaluation/lock signal S X  is at a high voltage level, the first terminal  1  of the switch SW 1  is coupled to the second terminal  2  of the switch SW 1 ; when the evaluation/lock signal S X  is at a low voltage level, the first terminal  1  of the switch SW 1  is coupled to the third terminal  3  of the switch SW 1 . Furthermore, according to the present invention, the DLL circuit  400  is assumed in evaluation status when the evaluation/lock signal S X  is at the high voltage level; the DLL circuit  400  is assumed in locking status when the evaluation/lock signal S X  is at the low voltage level. 
         [0026]    Please continue referring to  FIG. 4 . The switch SW 2  comprises a first terminal  1 , a second terminal  2 , a third terminal  3 , and a control terminal C. The first terminal  1  of the switch SW 2  is coupled to an input terminal of the duty cycle correction circuit  450 , the second terminal  2  of the switch SW 2  is coupled to an output terminal O 3  of the predetermined delay circuit  440 , the third terminal  3  of the switch SW 2  is coupled to an output terminal O 1  of the adjustable delay circuit  460 , and the control terminal C of the switch SW 2  receives the evaluation/lock signal S X . When the evaluation/lock signal S X  is at the high voltage level, the first terminal  1  of the switch SW 2  is coupled to the second terminal  2  of the switch SW 2 ; when the evaluation/lock signal S X  is at the low voltage level, the first terminal  1  of the switch SW 2  is coupled to the third terminal  3  of the switch SW 2 . 
         [0027]    Please continue referring to  FIG. 4 . The switch SW 3  comprises a first terminal  1 , a second terminal  2 , a third terminal  3 , and a control terminal C. The first terminal  1  of the switch SW 3  is coupled to an output terminal of the duty cycle correction circuit  450 , the second terminal  2  of the switch SW 3  is coupled to the input terminal I 1  of the adjustable delay circuit  460 , the third terminal  3  of the switch SW 3  is coupled to the input terminal I 3  of the predetermined delay circuit  440 , and the control terminal C of the switch SW 3  receives the evaluation/lock signal S X . When the evaluation/lock signal S X  is at the high voltage level, the first terminal  1  of the switch SW 3  is coupled to the second terminal  2  of the switch SW 3 ; when the evaluation/lock signal S X  is at the low voltage level, the first terminal  1  of the switch SW 3  is coupled to the third terminal  3  of the switch SW 3 . 
         [0028]    Please continue referring to  FIG. 4 . The predetermined delay circuit  440  comprises the input terminal I 3  and the output terminal O 3 . The predetermined delay circuit  440  delays the signal that received at the input terminal I 3  by a predetermined period of time D P  (not shown), and then outputs the delayed signal at its output terminal O 3 . 
         [0029]    Please continue referring to  FIG. 4 . The adjustable delay circuit  460  comprises input terminals I 1 , and I 2 , and output terminals O 1 , and O 8 . The input terminal I 2  of the adjustable delay circuit  460  is utilized for receiving the reference periodic signal CLK REF . The output terminal O 8  of the adjustable delay circuit  460  is utilized for outputting the evaluation/lock signal S X . When the adjustable delay circuit  460  is in the evaluation status (when the evaluation/lock signal S X  is at the high voltage level), the adjustable delay circuit  460  determines the size of the delay D A  according to the signals received at the input terminals  11  and  12 ; and when the adjustable delay circuit  460  is in the locking status (when the evaluation/lock signal S X  is at the low voltage level), the adjustable delay circuit  460  outputs a signal delayed by the delay D A  (predetermined in the evaluation status), and the signal is received at the input terminal I 1  of the adjustable delay circuit  460 . 
         [0030]    Please continue referring to  FIG. 4 . The input terminal of the duty cycle correction circuit  450  is coupled to the first terminal  1  of the switch SW 2 , and the output terminal is utilized for outputting a periodic signal CLK OUT . The duty cycle correction circuit  450  is utilized for adjusting the duty cycle of the received signal in order to output a periodic signal having a duty ratio of 50%/50%. Accordingly, both the rising edge and the falling edge of the periodic signal that are outputted by the duty cycle correction circuit  450  can be provided to the external circuits. 
         [0031]    Please continue referring to  FIG. 4 . An input terminal of the frequency divider  470  is coupled to the output terminal O 3  of the predetermined delay circuit  440  for dividing the received signal to generate the feedback periodic signal CLK FB , another input terminal of the divider  470  receives the reference periodic signal CLK REF , an output terminal of the divider  470  is coupled to the phase/frequency detector  410  for outputting a divided reference periodic signal, and another output terminal of the divider  470  is coupled to the phase/frequency detector  410  for outputting a divided feedback periodic signal CLK FB . The divider  470  is utilized for frequency dividing of the received periodic signal, and the divisor can be set such as 1, 2, or 3. The periodic signal is transmitted to the phase/frequency detector  410  after being divided by the divider  470 . Please note that, in the following description of the present invention, the divisor of the frequency divider  470  is set to 1 for brevity. 
         [0032]    Please refer to  FIG. 5 .  FIG. 5  is a diagram illustrating the DLL circuit  400  of the present invention in the evaluation status. Assuming the evaluation/lock signal is at the high voltage level (logic “1”), then the first terminal  1  of all of the switches SW 1 ˜SW 3  are coupled to the corresponding second terminal  2  as shown in the  FIG. 5 . In  FIG. 5 , when the startup voltage charging circuit  423  is in the evaluation status (when the evaluate/lock signal S X  is at the high voltage level), a startup voltage V INI  is generated for providing to the voltage controlled delay circuit  430  to be the control voltage V X . Then, the control voltage V X  is maintained to a fixed value, which is the startup voltage V INI . In  FIG. 5 , the reference periodic signal CLK REF  is delayed by voltage controlled delay circuit  430 , and then inputted to the predetermined delay circuit  440 . Next, the signal delayed by the delay D P  of the predetermined delay circuit  440  is inputted to the duty cycle correction circuit  450 . Then, the periodic signal CLK OUT  that has been corrected by the duty cycle correction circuit  450  is inputted to the adjustable delay circuit  460 . 
         [0033]    Please refer to  FIG. 6 .  FIG. 6  is a diagram illustrating the adjustable delay circuit  460  of the present invention in the evaluation status. The adjustable delay circuit  460  comprises a selecting circuit  461 , a delay controller  462 , a multiplexer  463 , and a plurality of delay units DU 1   18  DU M  (i.e., M delay units in the embodiment). 
         [0034]    Please refer to  FIG. 6  again. Each of the delay units DU 1 , DU 2 , DU 3 , . . . , and DU M  comprises an input terminal and an output terminal. Each of the delay units DU 1 , DU 2 , DU 3 , . . . , and DU M  delays it received signal by a predetermined period of time D T , and then outputs as the delayed periodic signals CLKI 1 , CLKI 2 , CLKI 3 , . . . , and CLKI M , respectively. The delay units DU 1 ˜DU M  are connected in series. In other words, the input terminal of the delay unit DU 2  is coupled to the output terminal of the delay unit DU 1  for receiving the delayed periodic signal CLKI 1 ; the input terminal of the delay unit DU 3  is coupled to the output terminal of the delay unit DU 2  for receiving the delayed periodic signal CLKI 2 ; the input terminal of the delay unit DU 4  is coupled to the output terminal of the delay unit DU 3  for receiving the delayed periodic signal CLKI 3 , . . . , and the input terminal of the delay unit DU M  is coupled to the output terminal of the delay unit DU (M−1)  for receiving the delayed periodic signal CLKI (M−1) . Furthermore, the input terminal of the delay unit DU 1  is coupled to the input terminal I 1  of the adjustable delay circuit  460  for receiving the periodic signal CLK OUT . 
         [0035]    Please continue referring to  FIG. 6 . The selecting circuit  461  comprises two input terminals and an output terminal, one of the input terminals of the selecting circuit  461  is coupled to an input terminal I 2  of the adjustable delay circuit  460  for receiving the reference periodic signal CLK REF , and the other input terminal of the selecting circuit  461  is coupled to the output terminal of the delay unit DU 1  for receiving the delayed periodic signal CLKI 1 . The output terminal of the selecting circuit  461  is utilized for outputting a selected periodic signal CLK S  after the selecting circuit  461  is selected. As long as the selecting circuit  461  detects that the reference periodic signal CLK REF  is at the low voltage level and a first rising edge occurs in the delayed periodic signal CLKI 1 , the selecting circuit  461  outputs the reference periodic signal CLK REF  as the selected periodic signal CLK S . 
         [0036]    Please continue referring to  FIG. 6 . The delay controller  462  comprises a first input terminal I 4 , a plurality (i.e., M) of second input terminals I 51 , I 52 , I 53 , . . . , and I 5M , an output terminal O 4 , and an output O 6 . The input terminal I 4  of the delay controller  462  is coupled to the output terminal of the selecting circuit  461  for receiving the selected periodic signal CLK S . The output terminal O 6  of the delay controller  462  is coupled to the output terminal O 8  of the adjustable delay circuit  460  for outputting the evaluation/lock signal S X . Each of the M second input terminals I 51 ˜I 5M  of the delay controller  462  is coupled to a corresponding output terminal of the delay units DU 1 ˜DU M  for receiving the delayed periodic signal CLKI 1 ˜CLKI M  respectively. The delay controller  462  generates a control signal S C  to the control terminal C of the multiplexer  463  to control the internal coupling of the multiplexer  463  according to the received selected periodic signal CLK S  and the delayed periodic signals CLKI 1 ˜CLKI M . When in the evaluation status (i.e., when the evaluation/lock signal S X  is at the high voltage level), the delay controller  462  adjusts the value of the control signal S C  according to the received selected periodic signal CLK S  and the delayed periodic signals CLKI 1 ˜CLKI M . Then, when in the locking status (i.e., when the evaluation/lock signal S X  is at the low voltage level), the delay controller  462  outputs the value of the control signal S C  that has been decided in the evaluation status to the control terminal C of the multiplexer  463 . Furthermore, the delay controller  462  sets the voltage level of the evaluation/lock signal S X  according to the delay unit DU M  (the M th  delay unit), and then outputs to the output terminal O 6  of the delay controller  462 . More specifically, before the delay unit DU M  outputs the delayed periodic signal CLKI M , the delay controller  462  sets the evaluation/lock signal S X  at the high voltage level; and after the delay unit DU M  outputs the delayed periodic signal CLKI M , the delay controller  462  sets the evaluation/lock signal S X  at the low voltage level. 
         [0037]    Please continue referring to  FIG. 6 . The multiplexer  463  comprises a plurality (i.e. M) of input terminals I 61 , I 62 , I 63 , . . . , and I 6M , a control terminal C, an activation terminal EN, and an output terminal O 5 . Each of the input terminals I 61 , I 62 , I 63 , . . . , and I 6M  of the multiplexer  463  is coupled to the corresponding output terminal of the delay units DU 1 ˜DU M  for receiving the delayed periodic signal CLKI 1 ˜CLKI M  respectively. The control terminal C of multiplexer  463  is coupled to the output terminal O 4  of the delay controller  462  for receiving the control signal S C . The activation terminal EN of the multiplexer  463  is utilized for receiving the evaluation/lock signal S X . The output terminal O 5  of the multiplexer  463  is coupled to the output terminal O 1  of the adjustable delay circuit  460  for transmitting one of the received delayed periodic signal to the output terminal O 1  of the adjustable delay circuit  460  as the feedback periodic signal CLK FB . The multiplexer  463  couples the output terminal O 5  of the multiplexer  463  to one of the M input terminals I 61 , I 62 , I 63 , . . . , and I 6M  of the multiplexer  463  according to the control signal S C . When in the evaluation status (i.e., when the evaluation/lock signal S X  is at the high voltage level), the multiplexer  463  is inactivated, i.e., the output terminal O 5  of the multiplexer  463  does not output any signal. When in the locking status (i.e., when the evaluation/lock signal S X  is at the low voltage level), the multiplexer  463  is activated, and outputs the feedback periodic signal CLK FB  at the output terminal O 5  of the multiplexer  463  according to the control signal S C  and one of the M input terminals I 61 , I 62 , I 63 , . . . , and I 6M . 
         [0038]    Please refer to  FIG. 7 .  FIG. 7  is a timing diagram illustrating relationship between the reference periodic signal CLK REF , delayed periodic signals CLKI 1 ˜CLKI M , and the selected periodic signal CLK S . Each of the delayed periodic signals CLKI 1 ˜CLKI M  is delayed by a predetermined period of time D T  compared with the previous one, and the selected periodic signal CLK S  is generated when the reference periodic signal CLK REF  is at the low voltage level and after the first rising edge of the delayed periodic signal CLK 1  occurs. Then, the delay controller  462  transmits the control signal S C  according to the selected periodic signal CLK S  and the delayed periodic signal CLKI 1 ˜CLKI M . In  FIG. 7 , when the first rising edge of the selected periodic signal CLK S  occurs between the first rising edges of the delayed periodic signals CLKI N  and CLKI (N+1) , the delay controller  462  transmits the control signal S C  to the multiplexer  463  in order to coupled the input terminal I 6(N−1)  of the multiplexer  463  to the output terminal O 5  of the multiplexer  463 , and to output the delayed periodic signal CLKI (N−1)  as the feedback periodic signal CLK FB . Accordingly, the error phase locking situation of the DLL circuit  400  of the present invention can be avoided. Furthermore, the predetermined delay D A  for delaying the feedback signal CLK FB  outputted from the adjustable delay circuit  460  is (N−1)D T . 
         [0039]    Please refer to  FIG. 8 .  FIG. 8  is a diagram illustrating the DLL circuit  400  of the present invention in the locking status. Assuming in the locking status, the evaluation/lock signal is at the low voltage level (i.e., logic “0”), then all of the first terminals  1  of the switches SW 1 ˜SW 3  are coupled to the third terminals  3  correspondingly as shown in  FIG. 8 . In  FIG. 8 , the reference periodic signal CLK REF  is inputted to the adjustable delay circuit  460  after being delayed by the voltage controlled delay circuit  430 . Next, the delayed reference periodic signal CLK REF  is inputted to the duty cycle correction circuit  450  after being delayed again by the adjustable delay circuit  460  with the delay (N−1)D T . Then, the periodic signal CLKI OUT  that is adjusted by the duty cycle correction circuit  450  is inputted to the predetermined delay circuit  440 . Then, the predetermined delay circuit  440  delays the received periodic signal CLK OUT  by the delay D P , and feedbacks to the phase/frequency detector  410  as the feedback signal CLK FB  via the frequency divider  470 . 
         [0040]    When the DLL circuit  400  of the present invention is in the evaluation status, the required number of the delay unit DU (i.e., the magnitude of the delay D A ) of the adjustable delay circuit  460  is determined by the phase difference between the original reference periodic signal CLK REF  and the periodic signal CLKI OUT  outputted after the voltage controlled delay circuit  430 , the predetermined delay circuit  440 , and the duty cycle correction circuit  450 . In addition, when in the locking status, the DLL circuit  400  of the present invention utilizes the delay obtained from the used delay units DU determined in the evaluation status to perform the delay lock upon the reference periodic signal CLK REF . Accordingly, the usage of the voltage in the section C of the  FIG. 3  can be avoided in the voltage controlled delay circuit  430 . In other words, if the delay required by the entire DLL circuit  400  is D Y , then the delay D Y  should equal to the delay D X  in addition with the delay (N−2)D T . Accordingly, the delay (N−2)D T  reduces the delay D X , which reduces the required voltage in the voltage controlled delay circuit  430 . Consequently, the voltage required in the voltage controlled delay circuit  430  does not fall in section C, as shown in  FIG. 3 , and the stability of the DLL circuit  400  is increased. Furthermore, the range of the entire delay required by the DLL circuit  400  of the present invention is prolonged, and the DLL circuit  400  of the present invention can be applied in the field required wide frequency range. 
         [0041]    To sum up, the DLL circuit  400  of the present invention is more adaptive for the user since the DLL circuit  400  has a wider frequency locking range and low error locking rate, providing greater convenience. 
         [0042]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.