Abstract:
A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.

Description:
BACKGROUND OF INVENTION  
         [0001]    There is a constant motivation to reduce the active power and/or standby power of semiconductor chips and macros. This current focus is dictated by the increased proliferation of semiconductors in mobile and portable applications. Therefore, a need exists for intelligent power management on memory chips and macros.  
           [0002]    In the past power management of memory refresh operations has been described in U.S. Pat. No. 4,120,047 of Varadi entitled “QuasiStatic MOS Memory Array With Standby Operation. The Varadi patent describes a MOSFET” memory array that uses a single voltage source (i.e., 5 volts) and operates basically as a static memory array rather than as a dynamic memory array that requires the gates of the MOS devices of the memory array to be periodically refreshed to restore or refresh the memory states contained therein. Each of the memory cells of the memory array contains four MOS devices that are crossinto a fliptype of memory cell. All of the memory cells connected to a common word line are also connected to a common return line to which is connected a single resistor and a single large MOS or FET device. The large MOS device is turned on during the active operation of the memory array (during write and read operations) and is turned off during the standby operation of the memory array. The resistor functions to insure that some current flow takes place, during the standby operation, from all the memory cells connected to the common return line in order to maintain the data states (“1” or “0”) in each of the memory cells.” In the intervening years since the issuance of the Varadi patent we have found that there remains a need for a method and device for providing low power standby operation that occupies less silicon area and is applicable to word-line driver architectures as well.  
           [0003]    U.S. Pat. No. 6,236,617 of Hsu et al. entitled “High Performance CMOS Wordline Driver” describes wordline DRAM array having n groups of m wordlines, in which one group is driven by a group decoder circuit (having a voltage swing between ground and a circuit high voltage and one driver circuit in each group is exposed to a boosted wordline high voltage greater than the circuit high voltage, in which the wordline driver circuits have an output stage comprising a standard NFET in series with a high threshold voltage PFET. In the example shown there are 1024 wordline drivers and a row (group) decoder “100” which drives the gates of a selected group of four of those wordline drivers. A wordline selector “200” provides an input to the source of a PFET transistors connected in series to a parallel pair of NFET transistors, one of which has its gate connected to the row (group) decoder and the other one of which has its gate connected to a restore circuit. The driver passes voltage Vpp on to a wordline, since WLDV connected to that driver is at Vpp. However, for the remaining (mdrivers in that group, the WLDV signals are kept at Vm (e.g. 0.7V) level and even though the gates of those drivers are pulled low, the high Vt (about of the PFET device, will not prevent the output of those drivers from being maintained by the restore. circuit at a negative level (or The restore circuit opens a path between a terminal and the wordline to restore the quiescent state on the wordline block.  
           [0004]    U.S. Pat. No. 6,426,914 of Dennard et al. entitled “Floating Wordline Using A Dynamic Row Decoder And Bitline VDD Precharge” describes a “wordline driver D consisting of a pullpMOS PU, a pullMOS PD, and a second nMOS pulldevice K which is called a killer device. This killer device is used to deselect the halfselected wordlines so they will not be floating.” Dennard et al states further that “each decoded output from a level shifter is tied to a group of four wordline drivers. One of the four wordline drivers is selected by decoding the sources of the pullup pMOS devices as well as the gates of the killer devices”.  
           [0005]    [0005]FIGS. 1A and 1B describe a prior art DRAM memory configuration with the problem or achieve an of excessive consumption of power during standby operation.  
           [0006]    [0006]FIG. 1A shows a prior art memory configuration for multi-banked a DRAM  10 . The DRAM  8  includes a set of Second Sense Amplifiers (SSA)  11  and sixteen (16) banks  120 ,  121 ,  12 X,  133 ,  134 , and  135 .  
           [0007]    Referring to Second Sense Amplifiers (SSA)  11 , Hanson et al. U.S. Pat. No. 6,115,308 entitled “Sense Amplifier and Method of Using the Same with Pipelined Read, Restore and Write Operations” describes a second sense amplifier memory device which may have a sense amplifier circuit and two drivers connected to the sense amplifier circuit. Two data bus lines may be connected to the sense amplifier circuit to receive data signals. A first equalize signal and a second equalize signal are applied to the sense amplifier circuit to allow the sense amplifier circuit to receive the data signals across the data bus lines. A switch signal is applied to the sense amplifier circuit to connect the data bus lines to a read data bus. The state of the first equalize signal is changed so that the data bus lines either receive new data or the data bus lines are equalized to a predetermined voltage while the data is on the read data bus and is capable of being read.  
           [0008]    As additional background for this invention, the row architecture of one of the banks  12 X of a DRAM  10 , which is shown some in detail in FIG. 1B, is described next. The row path is comprised of three key blocks; the RDEC (Row address DECoder) block  14 , the RSEL (Row SELector level shifter as in Dennard et al.) block  16 , and the row or WLDRV (WordLine DRiVer) block  18  in which there are 128, i.e. (X+1), wordline blocks WLDRV, e.g. wordline blocks DR 1  to DR 512  for control codes WLDRV&lt; 0 &gt;, WLDRV&lt; 1 &gt;, WLDRV&lt; 2 &gt;, WLDRV&lt; 3 &gt;,âz, 900  WLDRV&lt;X&gt; where X=511. In response to control codes from a data processing system (not shown), the RDEC block  14  and the RSEL block  16  perform a process of hierarchical decoding. First, the RDEC block  14  enables the selection of four (4) wordlines out of the total number of 512 wordlines WLDRV&lt; 0 &gt;, WLDRV&lt; 1 &gt;, WLDRV&lt; 2 &gt;, WLDRV&lt; 3 &gt;&gt;,âz, 900  WLDRV&lt; 127 &gt;. For the example of 512 rows in a bank, the RDEC performs a 1/128 decode. Then the RSEL block  16  performs the final 1/4 decode with a twopredecoder (not shown) to activate one (1) of the four WLDRV blocks activated by the RDEC block  14  with a signal on one of the WLDV lines  20 A- 20 D. For example referring to FIG. 2 the RSEL in FIG. 1B can employ the twopredecoder (not shown) to activate line  20 A, which is one of the four wordline drivers  20 A- 20 D Thus, the row selector RSEL block  16  has a selector line  20 A- 20 D connected to n/2 x  of the wordline drivers in said group of n wordline drivers, where x= is an integer greater than 1, e.g the selector line is connected to n/4 or n/8 of the wordline drivers. The signal on WLDECN bus line performs the 1/128 decode, enabling four WLDRVs with horizontal buses. In summary, the RDEC block  14  sends a signal on lines WLDEC- 1  to WLDEC- 128  to select four WLDRV units. For example, as shown line WLDEC- 1  line  15 - 1  can simultaneously energize four wordline drivers WLDRV&lt; 0 : 3 &gt;, i.e. WLDRV&lt; 0 &gt;, WLDRV&lt; 1 &gt;, WLDRV&lt; 2 &gt;, WLDRV&lt; 3 &gt;) from the set of the 512 wordlines with the signal on the WLDECN (WordLine DECoder Signal @ low) line to perform a 1/32 decode. The WLDECN- 128  line  15 - 128  can energize the last four wordline drivers WLDRV&lt; 508 &gt; driver (not shown), WLDRV&lt; 509 &gt; driver (not shown), WLDRV&lt; 510 &gt; driver (not shown), and WLDRV&lt; 511 &gt; driver DR 512  which is the only one of the four shown in FIG. 1B for convenience of illustration.  
           [0009]    Then the RSEL block  16  decodes a one (1) out of the four (4) signals from the data processing system (not shown) to select one of the four wordlines enabled by the RDEC block  14 . The RSEL block  16  then encodes signals on vertical Word Line DriVe (WLDV) lines  20 A- 20 D to enable Â¼ of the Word Line DriVe (WLDRV) blocks with signals on WLDV lines  20 A- 20 D. The output of the RSEL block, Â¼ of the WLDV bus lines  20 A- 20 D will be active while at the same time Â¾ of the Word Line ReSeT (wlrst ) bus lines  22 A- 22 D will be activated to ensure the deactivation of the remaining Â¾ of the wordline blocks WLDRV. In the current state of the art of multi-banked DRAMs and embedded DRAMs, the process of wordline decoding is performed hierarchically.  
           [0010]    The non-activated wordlines are held low by three (3) out of four (4) of the Wordline Reset signals (WLRST&lt; 0 : 3 &gt;) on wordline bus lines  22 A- 22 D. For example, if WLDRV&lt; 0 &gt; is to be selected value on line  20 A for the code WLDV&lt; 0 &gt; will be high. In addition the value on bus lines  22 A- 22 D for the three codes WLRST&lt; 1 : 3 &gt; will be high, the three codes WLDV&lt; 1 : 3 &gt; will be low, and for the single code WLRST&lt; 0 &gt;&gt; line  22 A is high.  
           [0011]    [0011]FIG. 2 shows a portion  18 ″ of the WLDRV block  18 ″ of FIG. 1B which includes two of the prior art wordline driver circuits DR 1  and DR 2  plus BL&lt; 0 &gt; bitline  28 , and array transistors A 0 /A 1  with related array capacitors C 1 /C 2 .  
           [0012]    Block DR 1  includes pull-up PFET transistor P 1 , pull-down NFET transistor N 1  and killer NFET transistor N 2 . For pull-up PFET P 1  the source is connected to WLDV&lt; 0 &gt; line  20 A and the drain is connected to node B 2 , as are the drains of pull-down NFET N 1  and killer NFET N 2 . The gates of transistors P 1  and N 1  are connected via node B 1  to WLDECN line  15 - 1 . The gate of NFET N 2  is connected to WLRST&lt; 0 &gt; line  22 A. The sources of transistors N 1  and N 2  are connected to ground (reference potential). The drains of transistors P 1 , N 1  and N 2  are connected via node B 2  to the wordline output WL&lt; 0 &gt; line  26 - 1  which connects to the gate of NFET array transistor AO which has its source connected to capacitor C 1  (connected to ground) and its drain connected to node B 5 , which is the BL&lt; 0 &gt; line  28 .  
           [0013]    Block DR 2  includes pull-up PFET transistor P 2  and pull-down NFET transistor N 3  and killer NFET transistor N 4 . For PFET P 2  the source is connected to WLDV&lt; 1 &gt; line  20 B and the drain is connected to node B 4 , as are the drains of transistors N 3  and N 4 . As in block DR 1 , the gates of transistors P 2  and N 3  are connected via node B 3  to WLDECN line  15 - 1 . The gate of transistor N 4  is connected to WLRST&lt; 1 &gt; line  22 B. The sources of transistors N 3  and N 4  are connected to ground (reference potential). The drains of transistors P 2 , N 3  and N 4  are connected via node B 4  to the wordline output WL&lt; 1 &gt; line  26 - 2  which connects to the gate of NFET array transistor A 1  which has its source connected to capacitor C 2  (connected to ground) and its drain like the drain of NFET array transistor A 0  is also connected to node B 5 , which is the BL&lt; 0 &gt; line  28 . Examples of voltages applied to the circuit are VDD which has a value of about 1.2V, Vpp which varies between a value of 0V and about 1.5V to 2.5V and WLRST which varies between about 0V and VDD, i.e. 1.2V. The value of WLDV&lt; 0 &gt; is shown to be VPP (e.g. 2.5V) after rising from 0V. The value of WLDV&lt; 1 &gt; is shown to be 0V after falling from VPP (e.g. 2.5V).  
           [0014]    As stated above with respect to FIG. 1B, in the RSEL  16  a twopredecoder (not shown is used to activate line  20 A which is one of the four wordline drivers  20 A- 20 D. Then referring to FIG. 2, in order to activate WL&lt; 0 &gt; line  26 - 1 , the source of,the pMOS pulldevice P 1  is tied to VPP, while the gate of the killer device is tied to Ground on line  22 A. At this moment, the sources of the other three pMOS pulldevices in drivers DR 1 , DR 2 , DR 3  and DR 4  stay at ground, and the gates of the other three killer devices stay at VDD. This second level decoding is applied to all the wordline drivers in the first level decoded group of four.  
           [0015]    Referring to FIG. 2 and the above example, the signal on the shared WLDECN line  15 - 1  from the RDEC block  14  in FIG. 1B is low, preventing NFET transistors N 1  in driver DR 1  WLDRV&lt; 0 &gt; and N 3  in WLDRV&lt; 1 &gt; in driver DR 2  from conducting. The input for code WLDV&lt; 1 &gt; on line  20 B to the source circuit of PFET P 2  in driver DR 2  will be low and for the gate terminal of NFET N 4  single code WLRST&lt; 1 &gt; in driver DR 2  the value will be high, preventing PFET P 2  from conducting and enabling NFET N 4  in driver DR 2  to conduct, respectively. The input WLDV&lt; 0 &gt; on the source terminal of PFET P 1  is high enabling PFET P 1  to conduct and charge the WL&lt; 0 &gt; wordline  26 - 1 , up to VPP, its boosted logic level “1”. The reset value on bus  22 B for code WLRST&lt; 1 &gt; would be high on the gate of NFET N 4 , thereby enabling NFET N 4  to conduct and to discharge the wordline  26 - 2 , WL&lt; 1 &gt; up to ground, its logic level “0”. The activated WL&lt; 0 &gt; wordline  26 - 1  drives the gate of the array transistor PFET A 1  to read data from or to write data into the memory element.  
           [0016]    When the memory array is placed in a standby state, none of the wordlines are activated. Therefore, in that case, all of the array transistor gates will be at the logic level “0” or ground.  
         SUMMARY OF INVENTION  
         [0017]    In accordance with this invention, a memory system is provided which includes a memory array with a plurality of wordline drivers included in a group of wordline drivers with n wordline drivers in a group. A row address decoder block has an output connected to each of the wordline drivers in the group of wordline drivers. A row selector block has a selector line connected to n/2 x  of said wordline drivers in the group of n wordline drivers, where x=is an integer greater than 1. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) are connected to the wordline drivers to lower power consumption thereof as a function of the power down input signal.  
           [0018]    Preferably, the power management circuit includes a plurality of FET devices, an inverter and a negative bias voltage, one of the FET devices connecting a reference potential to the WLPDN output in the absence of a WLPWRDN signal. and another FET connecting a negative voltage WLNEG to the WLPDN output in the presence of a WLPWRDN signal.  
           [0019]    Preferably, the standby power management circuit includes an input terminal and an output terminal, and the output terminal is connected to vary bias to said driver circuits in the wordline driver to vary operation thereof between full power current operation and reduced standby current operation.  
           [0020]    Preferably, the power management circuit includes a plurality of FET devices, an inverter and a negative bias voltage. One of the FET devices connecting a reference potential to the WLPDN output in the absence of a WLPWRDN signal and another FET connecting a negative voltage WLNEG to the WLPDN output in the presence of a WLPWRDN signal.  
           [0021]    In accordance with another aspect of this invention, a standby power management circuit includes an input terminal and an output terminal. Switching means are provided including MOSFET devices for switching between a positive output and a negative output signal at said output terminal as a function of an input on said input terminal. The switching means include at least one inverter and NMOS and PMOS devices.  
           [0022]    Preferably, the input terminal is connected through an inverter to the gate of a pull-up transistor. The output terminal is connected in series with a pass through transistor. A pull down FET transistor having a source/drain circuit is connected in series with a source of negative potential coupled to said output, and control FET transistors are connected to switch the gate of the pull down FET transistor as a function of a power down signal applied to the input.  
           [0023]    The present invention uses a logic device for the array transistor to boost the array performance. The problem caused by using this device is that the cost of the additional performance is standby power of the device is 1000× (pA) that of the DRAM-based array transistor (fA). Therefore, a need exists for a means to manage the standby power of the logic-array device and the memory array constructed with those devices. 
       
    
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0024]    [0024]FIGS. 1A and 1B describe a prior art DRAM memory configuration with the problem or achieve an of excessive consumption of power during standby operation.  
         [0025]    [0025]FIG. 2 shows a portion of the prior art WLDRV block of FIG. 1B which includes two of the prior art wordline driver circuits plus A BL&lt; 0 &gt; bitline , and array transistors with related array capacitors.  
         [0026]    [0026]FIG. 3 illustrates a modified row architecture in accordance with this invention, which provides a means for providing the two operating modes including a high-performance mode or a low-power mode.  
         [0027]    [0027]FIG. 4 shows a modification of the circuit diagram of FIG. 2 in accordance with this invention which demonstrates incorporation therewith of an embodiment of the Standby Power Management (SPM) block of FIG. 3.  
         [0028]    [0028]FIG. 5 illustrates an embodiment of the SPM power management block in accordance with this invention comprising a circuit incorporating MOSFET devices including pull-up PFET transistors, pull-down NFET transistors, a pass-through NFET transistor and an inverter.  
         [0029]    [0029]FIG. 6 illustrates a modification of FIG. 5  in which a SPM” power management block comprising a circuit incorporating MOSFET devices including PFET transistors, NFET transistors and two inverters. 
     
    
     DETAILED DESCRIPTION  
       [0030]    Referring to FIGS. 3-6, the present invention provides a means for managing the standby power of the type of logic-array device shown in FIG. 2. A standby power manager is provided that will modulate the bias of the array device depending on whether the memory array needs to be operated in two operating modes including a high-performance mode or a low-power mode.  
         [0031]    [0031]FIG. 3 illustrates a modified row architecture in accordance with this invention, which provides a means for providing the OLE_LINK 1  two operating OLE_LINK 1  modes including a high-performance mode or a low-power mode. For a memory array  30 , the architecture is comprised of four other blocks; the row address decoder block  14 , the row selector block  16 , the wordline drivers block DR, and the standby power management block  40 . The Standby Power Management (SPM) block  40  generates a WLPDN output on line  32  which modulates the bias point of the array transistor and the logic level “0” of the outputs of the row decoder  14  and wordline driver blocks DR. In normal operation (high performance mode) the logic level “0” of the outputs  15 - 1  to  15 - 128  of the row decoder  14  and wordline driver blocks DR lines  26 - 1  to  26 - 512  is ground. This maintains a bias upon the array the transistor that yields the highest performance. In standby operation (low power mode) the logic level “0” of the outputs of the row decoder  14  and wordline driver blocks DR is a voltage that is negative with respect to ground. Depending upon the technology this voltage can range from 0.2V to 1.5V. This bias condition reduces the array standby current by three orders of magnitude (from Pico-amps to femto-amps). As stated above, the row selector (RSEL) block  16  has a selector line  20 A- 20 D connected to n/2 x  of said wordline drivers in a group of n wordline drivers, where x=is an integer greater than 1, e.g. the row selector is connected to n/4 or n/8 of the wordline drivers.  
         [0032]    [0032]FIG. 4 shows a modification of the circuit diagram of FIG. 2, which demonstrates incorporation therewith of an embodiment of the Standby Power Management (SPM) block  40  of FIG. 3. In FIG. 4 the SPM block  40  is interfaced with two (2) wordline driver circuits DR 1  and DR 2  for purposes of illustration of an implementation which would include the full array of say  512  driver circuits DR 1 -DR 512  as indicated in FIG. 1B.  
         [0033]    In FIG. 4, the difference in the drivers DR 1  and DR 2  from FIG. 2 is that the sources of the pull-down NFET transistor N 1  and killer NFET transistor N 2  in driver DR 1  and the sources of pull-down NFET transistor N 3  and killer NFET transistor N 4  in driver DR 2  are connected via node B 6  to Word Line Power DoWN (WLPDN) line  32  instead of ground (reference potential).  
         [0034]    [0034]FIG. 5 illustrates an embodiment of the SPM power management block  40  comprising a circuit incorporating MOSFET devices including pull-up PFET transistors P 3  and P 4 , pull-down NFET transistors N 5 , N 6 , and N 8 , pass-through NFET transistor N 7  and an inverter  11 . WLPDN line  36  is connected to the gate of pull-up PFET P 3  and the input of inverter I 1 . The sources of pull-up PFET transistors P 3  and P 4  are connected via node B 10  to positive voltage VDD, e.g. about 1.2V. The drain of pull-up PFET P 3  is connected through node B 8  to the gate of pull-down NFET N 5  and the drain of pull-down NFET N 6 . The drains of pull-up PFET P 4  and pull-down NFET N 5  as well as the source of pass-through NFET N 7  and the gate of NFET N 6  are connected via node B 7  to the gate of pull-down NFET N 8 . The sources of pull-down NFET transistors N 5  and N 6  are connected through node B 09  to WordLine NEGative voltage WLNEG, e.g. from about. 0.2 to about 1.0V. The drain of pass-through NFET N 7  and the source of pull-down NFET N 8  are connected via node B 6  to the Wordline Power Down Bus (WLPDN) line  32 .  
         [0035]    The operation of the SPM block  40  is as follows. During high performance mode, the input to the circuit, WLPWRDN on line  36 , is high or logic level “1”. Pull-up PFET transistor P 3  will be off, the output of inverter I 1  having its input connected to WLPWRDN line  36  and its output connected to node B 12  will be logic level “0”. The gates of pull-up PFET transistor P 4  and of pass-through NFET transistor N 7  are connected to node B 12 . The inverter I 1  which is at logic level “0” produces a low potential on node B 12  which prevents pass-through NFET N 7  from conducting. This same low potential on node B 12  at the gate of pull-up PFET P 4  will enable conduction thereof and the drain terminal of pull-up PFET P 4  that is connected to node B 7  will be charged to a logic level “1”. The gate of pull-down NFET N 8  is also connected to node B 7 , so the potential (logic level “1”) at the gate of NFET N 8  will turn-on transistor N 8  discharging the WLPDN output line  32  of the SPM block  40  to ground, which was the condition in the circuit of FIG. 2. The same potential will also enable conduction of pull-down NFET N 6 . Conduction will pull the drain of pull-down NFET N 6 , which also the gate of pull-down NFET N 5  to the WLNEG voltage. This will ensure that pull-down NFET transistor N 5  does not conduct.  
         [0036]    During standby mode, the input to the circuit, WLPWRDN, is low or logic level “0”. Pull-up PFET transistor P 3  will conduct and charge its drain to logic level “1”, the output of inverter I 1  will also be logic level “1”. This potential at the gate of pass-through NFET N 7  will allow it to conduct and pull its drain voltage to the same potential as its source terminal that is connected to node B 7 . The source potential on pass-through through NFET N 7  is set in the following manner. The logic level “1” on node B 12  at the gate of pull-up PFET transistor P 4  will disable conduction thereof into node B 7 . With the drain of P 3  at a logic level “1” node B 8  will be at the potential of node B 10 , so of pull-down NFET transistor N 5  will conduct and discharge its drain terminal that is connected to node B 7  to the WLNEG potential on node B 9 . Node B 7  is also the source terminal of pass-through NFET transistor N 7 . Therefore, the WLPDN bus line  32 , which is connected to node B 6  will be discharged to the WLNEG voltage. This lower voltage on node B 6 , unlike the ground potential of FIG. 2 will bias the row driver circuits DR 1 , DR 2  (up to DR  512 ) and array transistor circuits A 0 /A 1 , etc. to a reduced standby current state. When the WLNEG voltage is connected to the node B 6 , all of the sources of the NFETs in the driver circuits DR 1 -DR 512  are lowered to near the WLNEG voltage, which, when the respective NFETs are conducting lowers the voltage on nodes B 2  and B 4  in FIG. 4  to near WLNEG turning off the wordlines  26 - 1  and  26 - 2 , etc. and placing a negative bias on the gates of the array transistor circuits A 0 /A 1 , etc. which causes the bias of the gate-drain terminals of the memory pass transistor to become reverse biased. This will greatly reduce the leakage current in the capacitive memory elements in which high data or logic level “1” is stored. Since all of the wordlines and consequently all gate-drain terminals of the memory pass transistors will be biased to the standby potential, the total standby current of the memory chip will be reduced by several orders of magnitude.  
         [0037]    [0037]FIG. 6 illustrates a modification of FIG. 5  in which a SPM″ power management block  40 ″ comprising a circuit incorporating MOSFET devices including PFET transistors P 5  and P 6  and NFET transistors N 15 , N 16 , N 17  and two inverters I 2 /I 3 . WLPDN line  32  is connected to the input of inverter I 2 , the output of which is connected via Node B 21  to the gate of PFET P 5  and the input of inverter I 3 , the output of which is connected via node B 22  to the gates of NFET  17  and PFET P 6 . The drain of PFET P 5  is connected to the gate of NFET  15 . The sources of PFET transistors P 5  and P 6  are connected via node B 20  to positive voltage VDD, e.g. about 1.2V. The drain of PFET P 6  is connected through node B 17  to the gate of NFET N 16  and the drain of NFET N 15 . The sources of NFET transistors N 15  and N 16  are connected through node B 19  to WordLine NEGative voltage WLNEG, e.g. from about. 0.2 to about 1.0V. The drains of NFET  17  and the drain of NFET  16  are connected via node B 6  to the Wordline Power Down Bus (WLPDN) line  32 .  
         [0038]    Basically the system of SPM″  40 ″ is analogous to the operation of the SPM  40  in FIG. 5. The conduction of NFET  16  when the node B 17  is high causes the node B 6  to be lowered to the WLNEG potential. The operation of the SPM block  40 ″ is as follows. During high performance mode, the input to the circuit, WLPWRDN on line  36 , is high or logic level “1”. The output of inverter I 2  having its input connected to WLPWRDN line  36  and its output connected to node B 21  will be logic level “0”. The output of inverter I 3  having its input connected to the output B 21  of inverter I 2  and its output connected to node B 22  will be logic level “1”. The gate of pull-up PFET transistor P 5  is connected to node B 21 . The logic level “0” or low potential on node B 21  allows pull-up PFET transistor P 5  to conduct and charge its drain terminal to VDD. The drain terminal of PFET P 5  is connected to the gate terminal of pull-down transistor N 15 . The high potential at its gate terminal will cause pull-down transistor N 15  to conduct and discharge node B 17  to the WLNEG potential. Node B 17  is also connected to the gate terminal of pull-down NFET transistor N 16  and the drain of pull-up PFET transistor P 6 , respectively. The WLNEG potential on node B 17  will disable conduction of pull-down NFET transistor N 16 . Node B 22 , which is at a logic level “1” is connected to the gate of pull-down NFET transistor N 17  and the gate of pull-up PFET transistor P 6 , respectively. The high potential on node B 22  will disable conduction of pull-up PFET transistor P 6  and will enable conduction of pull-down NFET transistor N 17 , respectively. The conduction of pull-down NFET transistor N 17  will discharge the WLDPN bus  32  to ground, the logic level “0”for high performance mode.  
         [0039]    During standby mode, the input to the circuit, WLPWRDN on line  36 , is low or at logic level “0”. In that case, the output of inverter I 2 , having its input connected to WLPWRDN line  36  and its output connected to node B 21 , will be at logic level “1”. The output of inverter I 3 , having its input connected to the output of inverter I 2  via node B 21  and its output connected to node B 22 , will be at logic level “0”. The gate of pull-up PFET transistor P 5  is connected to node B 21 . The high potential on node B 21  will prevent pull-up PFET transistor P 5  from conducting. Node B 17  is also connected to the gate terminal of pull-down NFET transistor N 16  and the drain of pull-up PFET transistor P 6 , respectively. Node B 22 , which is at a logic level “0”, is connected to the gate of pull-down NFET transistor N 17  and the gate of pull-up PFET transistor P 6 , respectively. The low potential on node B 22  will enable conduction of pull-up PFET transistor P 6  and will disable conduction of pull-down NFET transistor N 17 , respectively. The conduction of pull-up PFET transistor P 6  will charge the gate terminal of pull-down NFET transistor N 16  to VDD. This will enable pull-down NFET transistor N 16  to conduct and discharge the WLDPN bus  32  to WLNEG, the logic level “0” for standby mode.  
         [0040]    This lower voltage on node B 6 , unlike the ground potential of FIG. 2 will bias the row driver circuits DR 1 , DR 2  (up to DR  512 ) and array transistor circuits A 0 /A 1 , etc. to a reduced standby current state. When the WLNEG voltage is connected to the node B 6 , all of the sources of the NFETs in the driver circuits DR 1 -DR 512  are lowered to near the WLNEG voltage, which, when the respective NFETs are conducting lowers the voltage on nodes B 2  and B 4  in FIG. 4  to near WLNEG turning off the wordlines  26 - 1  and  26 - 2 , etc. and placing a negative bias on the gates of the array transistor circuits A 0 /A 1 , etc. which causes the bias of the gate-drain terminals of the memory pass transistors to become reverse biased. This will greatly reduce the leakage current in the capacitive memory elements in which high data or logic level “1” is stored. Since all of the wordlines and consequently all gate-drain terminals of the memory pass transistors will be biased to the standby potential, the total standby current of the memory chip will be reduced by several orders of magnitude.  
         [0041]    While this invention has been described in terms of the above specific embodiment(s), those skilled in the art will recognize that the invention can be practiced with modifications within the spirit and scope of the appended claims, i.e. that changes can be made in form and detail, without departing from the spirit and scope of the invention. Accordingly all such changes come within the purview of the present invention and the invention encompasses the subject matter of the claims which follow.