Abstract:
Various embodiments of the invention connect multiple non-volatile memory controllers in a daisy chain manner, so the multiple memory devices may be accessed from a common host controller. Data and control signals may be daisy-chained in this way, so that many memory devices may be connected together, while not increasing the loading on individual signals lines. Transfer with the various memory devices may be interleaved, so that the relatively slow times of the memory devices doesn&#39;t slow down the overall throughout of the memory stem.

Description:
BACKGROUND 
     NAND flash memory devices are typically used to store data that is to be read out in large blocks (e.g., digitized images or music). Because of the slow access times of NAND flash, several devices may be placed on a common bus in parallel and accessed at approximately the same time. When the data from each one is available, it can be read one device at a time. However, placing all those input/output (I/O) pins in parallel may cause capacitive loading that degrades the signal quality on the bus and thereby reduces the maximum useful throughput on the bus. Alternatively, accessing only one device at a time may cause the access times to accumulate, also slowing down overall throughput of the bus. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Some embodiments of the invention may be understood by referring to following description and accompanying drawings that are used to illustrate embodiments of the invention. In the drawings: 
         FIG. 1  shows a block diagram of a non-volatile memory system, according to an embodiment of the invention. 
         FIG. 2  shows a block diagram of a memory device, according to an embodiment of the invention. 
         FIGS. 3A ,  3 B, and  3 C show a flow diagram of a method performed by a memory device, according to an embodiment of the invention. 
         FIG. 4  shows a flow diagram of a method performed by a host controller, according to an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     In the following description, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure an understanding of this description. 
     References to “one embodiment”, “an embodiment”, “example embodiment”, “various embodiments”, etc., indicate that the embodiment(s) of the invention so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Further, some embodiments may have some, all, or none of the features described for other embodiments. 
     In the following description and claims, the terms “coupled” and “connected,” along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” is used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” is used to indicate that two or more elements co-operate or interact with each other, but they may or may not be in direct physical or electrical contact. 
     As used in the claims, unless otherwise specified the use of the ordinal adjectives “first”, “second”, “third”, etc., to describe a common element, merely indicate that different instances of like elements are being referred to, and are not intended to imply that the elements so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner. 
     Various embodiments of the invention may be implemented in one or any combination of hardware, firmware, and software. The invention may also be implemented as instructions contained in or on a machine-readable medium, which may be read and executed by one or more processors to enable performance of the operations described herein. A machine-readable medium may include any mechanism for storing, transmitting, and/or receiving information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium may include a storage medium, such as but not limited to read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; a flash memory device, etc. A machine-readable medium may also include a propagated signal which has been modulated to encode the instructions, such as but not limited to electromagnetic, optical, or acoustical carrier wave signals. 
     Various embodiments of the invention may connect multiple flash memory controllers in a daisy chain manner, so that multiple memory devices may be connected together without the bus loading and inherent signal degradation caused by connecting the device pins in parallel. Signals may also be passed through each controller quickly if the device is merely being used as a pass-through station for another device, or may be buffered for reading and writing to the associated memory array. In some embodiments, each memory device comprises a single integrated circuit containing a memory array and an associated memory controller to control the operations of that memory array, as well as to control passthrough operations in which commands or data that are addressed to other memory devices are passed through the controller for the use of those other devices. Some embodiments comprise a host controller, separate from the memory devices, that initiates commands and write data to the memory devices, and may also receive read data from the memory devices. Note: although the descriptions and drawing frequently refer to flash memory, and in particular to NAND flash memory, the principles described may also be used with other types of non-volatile memory in which the access times are long enough to warrant sequentially accessing each of multiple memory devices for an otherwise contiguous block of data, and in which placing these devices in parallel on a common bus can cause unacceptable bus loading. 
       FIG. 1  shows a non-volatile memory system, according to an embodiment of the invention. In the illustrated system  100 , a host controller  110  may provide overall control of a quantity of n+1 flash memory devices labeled # 0 , # 1 , . . . #n, which are numbered  120  through  12   n . A clock signal CLK may be originated by the host controller and passed to the first memory device  120 , which passes CLK to the next memory device  121 , and so forth until CLK reaches the last memory device in the chain, memory device  12   n . Data may be passed in both direction over multiple parallel data lines, collectively labeled DATA in the drawing. The number of parallel data lines may be any feasible quantity, such as but not limited to 4, 8, 16, 32, etc. Write data may be originated in the host controller and passed from memory device to memory device until it reaches the designated memory device, where it is written into that device&#39;s internal memory array. Read data may be originated in the selected memory device, and passed through multiple memory devices until it reaches the host controller, which may then process the data. Power connections to the various devices are not shown to avoid cluttering the drawing. 
       FIG. 2  shows a block diagram of a memory device, according to an embodiment of the invention. In the illustrated embodiment, the clock, data, and data valid (DV) lines correspond to their counterparts in  FIG. 1 . The flash memory device is numbered  120 , but may correspond to any of the flash memory devices shown in  FIG. 1 . Flash array  230  includes the actual memory portion of the flash memory device, the portion in which data may be stored for use by other devices. As shown in the drawing, the clock signal CLK that originates in the host controller may be brought in through the clkin input and used to clock the command state machine  240 , and may also be passed through from clkin to clkout, using a buffer  210  to reduce the loading that would occur if all the memory devices were tied directly to the same clock line. The command state machine  240  may be used to control overall operations in the flash memory device, based on commands brought in through the data 1  lines. 
     For ease of description, within the context of this document ‘upstream’ indicates data moving toward the host controller, while ‘downstream’ indicates data moving away from the host controller. For example, in  FIG. 1  device  121  would be downstream from device  120 , while device  120  would be upstream from device  121 . The host controller  110  would be upstream from all the memory devices  12   x.    
     Returning to  FIG. 2 , the data signals may be going either upstream or downstream, and may either be passed through the memory device, or originate in the memory device, or be destined for the memory device. Multiplexer/demultiplexer (mux/demux)  271  may be used to provide the proper data path, under control of the command state machine  240 , for data traveling in either direction between this device and the next upstream device. Mux/demux  271  may route downstream data from data 1  to register  262 , where it may be latched and made available to the next downstream device at data 2 . Similarly, upstream data from data 2  that has been latched in register  261  may be made available by mux/demux  271  at data 1  for passthrough to the next upstream device. Although mux/demux  271  is shown as a single functional circuit, in some embodiments it may be implemented as a multiplexer and a separate demultiplexer. 
     To provide proper timing for passthrough data, a data valid (DV) signal may also be passed through in either direction, with the downstream signal being latched in register  263  and the upstream signal being latched in register  264 . Under certain circumstances, such as when the memory device is providing data from its own memory array instead of passing through data from another memory device, the mux/demux  272  may be set to provide a timing signal fclk at DV 1  instead of passing through the DV signal from a downstream device. In some embodiments the signal fclk may be a clock signal that is derived from clkin, but which is only active at certain times, under control of the command state machine  240 . 
     When the host controller is attempting to read data from this particular flash memory device, the data read from flash array  230  may be placed in first-in-first-out buffer (FIFO)  251 , from where the mux/demux  271  may select it for presentation at data 1  for reading by the next upstream device. When the host controller is attempting to write data into this particular memory device, the data at data 1  may be routed to FIFO  252  by mux/demux  271 , from where it may be written into the flash array. 
     The FIFOs may be used to allow for differences in the data transfers rate between the array, which may have a comparatively slow data transfer rate, and the daisy-chain bus, which may have a comparatively high data transfer rate. In some embodiments, a page (or other block-size) of data may be fully written into FIFO  251  by array  230 , before that data is passed upstream through data 1 . Similarly, a full block of data may be written into FIFO  252  through data 1 , before that data is written from FIFO  252  into array  230 . 
     This technique of buffering in the FIFOs may be used advantageously to increase overall throughput of a memory system, by performing an operation with one memory device while another memory device is making an internal transfer with its FIFO. For example, memory device # 0  may be instructed to read data from its array. While it is moving that data from its array to its FIFO, memory device # 1  may be instructed to read data from its own array. Similar read operations may then be started with other memory devices. By the time all the read operations have been started, memory device # 0  may have filled its FIFO, and can transfer that data to the host controller. When that transfer is complete, memory device # 0  may be instructed to read another block of data from its array, which it will begin placing into its FIFO. By now, memory device # 1  may have filled its FIFO, and can transfer that data to the host controller and be instructed to read another block of data into its FIFO. This process may continue with the remaining memory devices until they have all transferred their data to the host controller. By then, memory device # 0  may be instructed to transfer its second block of data from its FIFO to the host controller, and the process can repeat. This process of alternating between different memory devices may continue until all the necessary data has been transferred. A similar process may be followed for write operations, by writing data into each memory device&#39;s FIFO in sequence, and letting one device write the data from its FIFO into its array while the other devices are receiving their data from the host controller. Although this process has been described as selecting the memory devices in the order in which they are daisy-chained together, some operations may select the devices in a different order. 
     It should be noted that all internal data paths, although indicated in the drawing with a single line, may actually contain multiple parallel lines, which in some embodiments will be equal in number to the number of parallel data lines between memory devices. Similarly, FIFOs  251  and  252 , registers  261  and  262 , and mux/demux  271  may all be configured to handle the required number of parallel signals. 
       FIGS. 3A ,  3 B, and  3 C show a flow diagram of a method performed by a memory device, according to an embodiment of the invention. In the illustrated embodiment of flow diagram  300 , the memory device receives a command at  310 . The command may be one of several different types of commands. If the command is a read command that is addressed to another memory device, as determined at  315 , the current memory device may configure its internal multiplexer/demultiplexer (e.g., mux/demux  271  of  FIG. 2 ) for a read passthrough operation at  316 . When the read data from the selected downstream memory device is received, either directly or indirectly through another downstream device, this read data may be passed upstream through the current memory device&#39;s control circuitry at  317 . 
     If the command was a write command for another device as determined at  320 , then the current memory device may configure its mux/demux for a passthrough write operation at  321 . When the write data from the host controller is received, either directly or indirectly through another upstream device, this write data may be passed downstream through the current memory device&#39;s control circuitry at  322 . 
     If the command was a read command addressed to this memory device, as determined at  325 , then the process may continue in  FIG. 3B . The memory device may configure its mux/demux for an internal read at  340 . If previously-requested data is available in the FIFO, as determined at  345 , that data may be sent from that FIFO to the next upstream device at  350 , from where it may be passed through to the host controller. If the FIFO is empty, then the memory device may use the read command to trigger the transfer of data from its own array to its FIFO at  355 . Once the memory device has completed transferring its FIFO data upstream at  350 , or has begun transferring data from its array into its FIFO at  355 , it may return to ‘A’ in  FIG. 3A  to await the next command. The operation at  355  may continue to completion even after the memory device has returned to A. 
     Returning to  FIG. 3A , if the command indicated at  310  was a write command addressed to this memory device, as determined at  330 , then the process may continue in  FIG. 3C . The memory device may configure its mux/demux for an internal write at  360 . If the FIFO is not ready to receive more data because it still contains data from a previous write operation as determined at  365 , then the memory device may do nothing (other than continue to write the remaining data from the FIFO into the array), and return to A to await another command. If the FIFO is ready to receive data, as determined at  365 , then that data may be received from upstream and written into the FIFO at  375 . Once the data is in the FIFO, that data may begin to be written into the array at  380 . Once the transfer of new data into the FIFO at  375  has been completed, and the transfer of data into the array has begun at  380 , the transfer of data into the array may continue to completion, even after the memory device has returned to A to await another command. 
     If a command was received at  310  that was something other than the four commands just described, then the memory device may move to whatever other processing (not described) is required at  335 . In some embodiments, the memory device may return a ‘busy’ or ‘error’ status if it is not ready to perform any of the described options when it receives a command from the host controller. 
       FIG. 4  shows a flow diagram of a method performed by a host controller, according to an embodiment of the invention. In some embodiments, this may be the host controller  110  of  FIG. 1 . In the illustrated flow diagram  400 , the host controller selects the first of multiple memory devices at  410  and sends a command over the daisy-chain bus that is addressed to that memory device at  420 . For simplicity of description, incrementing values of X=0 through X=n are used here to represent sequentially addressing the various memory devices  0  through n, but other embodiments may use other procedures to identify and select the various memory devices. If the selected memory device is ready to transfer data as determined at  430 , the host controller may perform the data transfer at  440 . ‘Ready to transfer data’ means that the selected memory device has data in its FIFO ready to transfer to the host controller (in the case of a read command), or the selected memory device has an available FIFO ready to receive data from the host controller (in the case of a write command). After the data transfer (or immediately if no data was transferred), the host controller may select the next memory device (X=X+1) at  450  and repeat the process with that newly-selected memory device. When all the intended memory devices have been communicated with in this manner, as determined at  460 , the host controller may continue operations with the first memory device and repeat the sequence with more read or write data. When all the transfers have been completed as determined at  470 , the host controller may continue with other processing. In some embodiments, in the case of a read operation, all the data from the data transfers to the host controller may be correctly assembled into a single block of data at  480 . Future data transfers may begin again later at  410 . Similarly, in the case of a write operation, a block of data may initially be separated into various parts, each of which is sent separately to various FIFOs in various memory devices. 
     The foregoing description is intended to be illustrative and not limiting. Variations will occur to those of skill in the art. Those variations are intended to be included in the various embodiments of the invention, which are limited only by the spirit scope of the following claims.