Abstract:
The invention relates to an active symmetrical balance hybrid circuit. The hybrid circuit includes an input, an output and an in/output as well an impedance circuit per half section connected to the input and output which is connected between the in/output and one or more virtual ground points. Between a virtual ground point and one of the supply lines a signal transistor is inserted. The hybrid circuit further includes per half section two auxiliary transistors connected between the supply lines and the in/output. The auxiliary transistors multiply by the same factor the current flowing through a signal transistor together with which the auxiliary transistor is incorporated in a current mirror circuit. A signal transistor can be incorporated in a current mirror circuit with one or two auxiliary transistors in the same half section, but also by means of a universal coupling of the two half sections both with an auxiliary transistor in the one and an auxiliary transistor in the other half section. The overall impedance of the impedance circuit is related to the coefficient of the auxiliary transistors to such an extent that the hybrid circuit fulfills the line matching condition. The partial impedances divided between the in/output, output and input are selected such that the balance condition of the hybrid circuit is fulfilled. The use of complementary signal and auxiliary transistors is preferred in the hybrid circuit. The hybrid circuit has a minimum dissipation and requires very little supply voltage, especially when complementary transistors are used.

Description:
BACKGROUND OF THE INVENTION 
     The invention relates to a hybrid circuit comprising an input, an output and an in/output, at least one signal transistor, at least one auxiliary transistor incorporated as a current multiplier in a circuit with an associated signal transistor and an impedance circuit incorporated in a circuit with associated signal transistor, a junction point of this impedance circuit being connected to the output of the hybrid circuit, the impedance circuit as a whole having such an impedance related to the coefficient of the auxiliary transistor that the hybrid circuit fulfills the line matching condition. 
     A hybrid circuit of the type mentioned hereinbefore is known from the German &#34;Auslegeschrift&#34; No. 2 829 392. 
     The active hybrid circuit known from the above-mentioned publication can be designed to be symmetrical, having two axially symmetrical half sections. This known active hybrid circuit can further be designed to comprise only NPN-transistors in the signal path, as a result of which in accordance with the then state of the art higher limit frequencies could be obtained than if PNP-transistors would have been inserted in the signal path. 
     If the known hybrid circuit is of a symmetrical configuration, each half section comprises two signal transistors, one connected to the input and in/output of the hybrid circuit and a negative supply line and being inserted in a circuit comprising an auxiliary transistor switched as a current multiplier, the auxiliary transistor coefficient being smaller than 1, the other signal transistor being connected between the output and in/output of the hybrid circuit and a positive supply line and being incorporated in a circuit comprising an impedance circuit, in the simplest case composed of a series arrangement of two resistors, with more specifically a first resistor being inserted between the collector of the aforesaid signal transistor, and the positive supply line and having a value amounting to half the line resistance, for example 300 Ohms, and the other resistor being connected between the collector and the base of this signal transistor and having a value equal to the inverse decreased by 1 of the aforesaid coefficient times half the line resistance, in order to meet the requirement of line matching. However, to avoid cross-talk of the input signal at the output of the hybrid circuit the aforesaid resistors of the impedance circuit are not interlinked directly, but by means of a base emitter transistor of an additional transistor of the impedance circuit, whose collector is connected to the positive supply line. 
     The object aimed at with the known hybrid circuit is transmitting onto the line the whole signal current at the input of the hybrid circuit, this object being achieved through the measures of current amplification (division) and impedance transformation, at least as regards transmitting onto the line. Further advantages of the known hybrid circuit are that it is readily integrated relatively simple to construct and that it has a small current consumption. 
     In addition to the advantage of high limit frequencies, the aforementioned advantages are of importance when such a hybrid circuit has to be inserted in an integrated modem circuit for example, for a viewdata system. 
     For such use, however, not only should the current consumption or the dissipation be as low as possible, but especially for direct supply from the line the required supply voltage should be as low as possible, with for example a total available power of approximately 20 mW and a total available supply voltage of approximately 4.5-8 V. 
     Unfortunately, with the known hybrid circuit, specially in practical embodiments thereof, this is not possible owing to the required transistors connected in series and in a totem pole configuration between the supply lines, each requiring a diode voltage (base/emitter voltage) of approximately 0.7 Volt. 
     SUMMARY OF THE INVENTION 
     The object of the invention is to provide a new concept for a hybrid circuit in which the least possible supply voltage is lost on required diode voltages. 
     The invention provides a hybrid circuit of the type mentioned above, characterized in that the impedance circuit is connected between the in/output and at least one virtual ground point of the hybrid circuit and has a further junction point connected to the input of the hybrid circuit, in that the signal transistor(s) is(are) connected between an associated virtual ground point and an associated supply line and in that two auxiliary transistors having the same multiplication coefficient are connected between a respective supply line and the in/output of the hybrid circuit and are incorporated in a current mirror circuit having at least one signal transistor, with junction points in the impedance circuit determining partial impedances being selected such that the hybrid balance condition is fulfilled. 
     Worded differently, the invention provides an active symmetrical balance hybrid circuit, which need not necessarily be axially symmetrical, but which can also have a universal coupling and which comprises in each half section an in/output for connection to a two-way transmission line, an input for connection to a transmitter and an output for connection to a receiver, an impedance circuit connected between the in/output of the hybrid circuit and preferably one virtual ground point, for example a resistor circuit, whose respective branches are connected to the input and the output of the hybrid circuit, preferably one signal transistor connected between the virtual ground point and a respective supply line and two auxiliary transistors each connected between the in/output of the hybrid circuit and a respective supply line as a current amplifier having a multiplication coefficient larger than 1 and inserted in a current mirror circuit preferably comprising the one signal transistor of the relevant half section, the auxiliary transistors in the latter case being complementary, the resistor circuit being dimensioned such that both the condition of line matching and the condition of hybrid balance are fulfilled, implying that the overall impedance of the resistor-circuit, that is to say on the one side the resistance value of a series arrangement of resistors between the in/output of the hybrid circuit and the virtual ground point and on the other side the coefficient of the auxiliary transistors and the line impedance, more specifically, the line resistance of the transmission line to be connected to the in/output of the hybrid circuit are assimilated such that the in/output resistance of the hybrid circuit as seen from the transmission line is equal to the line resistance, worded more generally, that the impedance of the in/output of the hybrid circuit is the complex conjugate of the line impedance and that the partial resistance-values of the resistor circuit between in/output, output input and the virtual ground point of the hybrid circuit are determined such that a signal on the input of the hybrid circuit does not appear on the output of the hybrid circuit. 
     As stated hereinbefore, in a preferred embodiment of the hybrid circuit in accordance with the invention, the auxiliary transistors are complementary, implying PNP transistors to be present in the signal path, whose limit frequency can come close to that of NPN transistors in accordance with the present state of the art, whereas, which is more important, in that case the least supply voltage is required because with a drive to full voltage swung both auxiliary transistors in the half sections can assume a negligibly small collector-emitter voltage. 
     In a further preferred embodiment only NPN-transistors are used in the signal path and the coupling of the half sections is axially symmetrical like in the known hybrid circuit. Per half section, however, exactly one signal transistor is used, this single signal transistor being incorporated in a current mirror circuit with both auxiliary transistors of the same section. 
     As the resistance value of the resistor between the in/output and output of the hybrid circuit is proportional to the coefficient of the auxiliary transistors, this resistor is preferably designed to be an external resistor among others to fulfill the condition that the resistance value on the in/output of the hybrid circuit may have a maximum tolerance of for example 5%. 
     In addition to the advantages of low dissipation by simply designing the matching resistor as a virtual resistor, high cut-off frequencies and simplicity of the circuit, further advantageous features of the suggested hybrid circuit are that the circuit is designed to be balanced and to be driven in class A, making the overall current consumption time-invariant and avoiding cross-talk via the supply lines and that the hybrid circuit is extremely linear. The supply voltage and supply current can also be used rather well by piling the bipolar hybrid circuit with one or more layers of I 2  L. The maximum supply current of 2-4 mA (V·23) can be set or limited by an external resistor. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The invention will now be further explained by way of example with reference to the attached drawing, wherein: 
     FIG. 1 shows the circuit diagram of an embodiment of the hybrid circuit for explaining the principles of the invention; 
     FIG. 2 shows a preferred embodiment of a total hybrid circuit in accordance with the present invention based on the example of FIG. 1; 
     FIG. 3 shows a half section of a further preferred hybrid circuit; and 
     FIGS. 4A-C show examples for realizing a virtual ground point in the case of the hybrid circuit section of FIG. 3. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In FIG. 1 a half section of an axial symmetrical hybrid circuit in accordance with the present invention is shown. The half section comprises two complementary signal transistors T s1 , T s2  and two complementary auxiliary transistors T h1 , T h2 , the bases of the PNP-transistors T s1  and T h1  being jointly connected to the output of an operational amplifier A1, the emitters of these transistors being connected to a positive supply line V 1 . The bases of the NPN-transistors T s2  and T h2  are similarly jointly connected to the output of an operational amplifier A2, their emitters being connected to a negative supply line V 2 . 
     The collectors of the auxiliary transistors T h1 , T h2  are jointly connected to the in/output I/O of this half section of the hybrid circuit, which can be connected to the in/output of the other section by means of a winding of a line transformer (not shown) while the other winding of the line transformer can be connected to a transmission line. 
     The collector of the signal transistor T s1  is connected to the non-inverting input of the operational amplifier A1, the inverting input of the operational amplifier A1 having a slight positive DC bias +dE and this inverting input being grounded for signals, while the collector of the signal transistor T s2  is connected to the non-inverting input of the operational amplifier A2, the inverting input of the operational amplifier A2 having a slight negative DC bias -dE and this inverting input being grounded for signals, which is indicated in the figure by respectively &#34;0&#34;+dE and &#34;0&#34;-dE. As a result of the functioning of operational amplifiers A1, A2 the collectors of the signal transistors T s1 , T s2  are virtually grounded, that is the voltage is at ground level, but the current cannot flow to ground. 
     Worded differently, the signal transistors T s1  and T s2  are virtually switched as diodes and form current mirror circuits with the associated auxiliary transistors T h1  and T h2 , causing the collector currents of the signal transistors T s1  and T s2  to be identical. The auxiliary transistors T h1  and T h2  are switched as current amplifiers, for example as a result of the presence of an emitter resistor (not shown) in the emitter lines of the auxiliary transistors T h1  and T h2 , this resistor being n times smaller than the emitter resistors (not shown) in the emitter lines of the signal transistors T s1  and T s2 , causing the current coefficient to be n, which in the figure is indicated by 1 x  and n x  with the respective signal transistors T s1 , T s2  and the auxiliary transistors T h1 , T h2 . In practice this can be done more accurately by providing correspondingly different emitter surfaces for the integrated signal transistors T s1 , T s2  as the only measure, or in combination with the aforesaid measure. 
     Between the junction point of the in/output I/O of the half hybrid circuit section and the collectors of the auxiliary transistors T h1 , T h2  and the associated junction points of the collector of the signal transistor T s1  and the non-inverting input of the operational amplifier A1 on the one side and of the collector of the signal transistor T s2  and the non-inverting input of the operational amplifier A2 on the other, an impedance circuit is inserted comprising in the shown embodiment a resistor circuit R 1 , R 2  and R 3  as well as a T-section of three small resistors with two small resistors 2dR being inserted in the parallel branch and one small resistor -dR being inserted in the series branch and the unused end of the latter small resistor being connected to the resistor circuit, more specifically R 3 , the unused ends of the small resistors 2dR being connected to respective junction points of signal transistors T s1 , T s2  and the non-inverting inputs of respective operational amplifiers A1, A2. The junction point of resistor -dR and resistor R 3  is indicated by B, the input I of the half hybrid circuit being connected to the junction point of resistor R 2  and R 3  and its output O being connected to the junction point of resistors R 1  and R 2 . For practical reasons preference is given to having R 3  -dR&gt;0. 
     In a state of equilibrium a small direct voltage +dE will be applied to the collector of signal transistor T s1  due to the operation of operational amplifier A1. Similarly a small direct voltage -dE will be applied to the collector of signal transistor T s1 . Consequently, a quiescent current J=2dE/4dR will flow from the collector of signal transistor T s2 , and as a result of the coefficient n of the auxiliary transistors T h1 , T h2  a quiescent current nJ will flow from the collector of the auxiliary transistor T h1  to the collector of the auxiliary transistor T h2 . 
     In n&gt;&gt;1 the largest current consumption will take place in the auxiliary transistors T h1 , T h2 . Assuming a signal current i l  flowing into the in/output I/O, a current flowing into auxiliary transistor T h1  will be approximately nJ-i l  /2, while the current flowing into auxiliary transistor T h2  will be nJ+i 1  /2. 
     Because it was assumed for the half hybrid circuit section shown in FIG. 1 that the line current i l  flowed into the in/output I/O, this current i l  will flow from the in/output of the other half section, so that for this other half section the condition holds that for the auxiliary transistor in the other half section corresponding to auxiliary transistor T h1  the current flowing through this auxiliary transistor will be nJ+i l  /2, and will be analogously nJ-i l  /2 through the auxiliary transistor in the other half section corresponding to the auxiliary transistor T h2 . 
     Consequently, the overall current consumption of the whole hybrid circuit will be 2(n+1)J, irrespective of the signal current i l . In view of the fact that the supply lines in an integrated circuit can cause considerable resistance, a time-invariant current dissipation will avoid circuit cross-talk to further circuits fed by the same supply lines in the entire hybrid. 
     The transistors T h1  and T h2  cannot handle negative current. So the supply current of these transistors nJ has to be larger than the peak value of ni/2. For a large n the condition holds that ni is about equal to the line current i l . The line current i l  consists of a part i lt  coming from a transmitter and a part i lt  intended for a receiver. The following condition should hold: 2nJ&gt;peak value of (i lt  +i lr ). The supply voltage between the supply lines V 1  and V 2  should further be larger than twice the peak value of the line voltage v 1 . If the said supply voltage is E, the following condition should hold: 
     
         E&gt;peak value of (v.sub.lr -v.sub.lt) 
    
     In the worst case with an overall maximum signal level on a transmission line of 600 Ohms in accordance with the V·23 standard of 1 milliwatt there is a transmitter power of 0.5 milliwatt and a receiver power of 0.5 milliwatt, so that the peak value of i lt  +i lr  is the root of 20/3 milliampere and the peak value of V lt  -v lt  is the square root of 2.4 Volts, leading to the theoretical minimum power consumption for the entire hybrid circuit of: ##EQU1## 
     Hereinbelow the line matching condition for the embodiment of the hybrid circuit in accordance with FIG. 1 will be calculated. 
     Let it be assumed that i t  =i r  =0, a signal current i l  flowing into in/output I/O of the half section shown in FIG. 1 will result in a current i in the resistor circuit R 1 , R 2 , R 3 , branching into currents i/2 through signal transistors T s1 , T s2 , causing currents ni/2 to flow into auxiliary transistors T h1 , T h2 . Applying the appropriate Kirchoff&#39;s law to the in/output I/O will yield i l  =ni/2+ni/2+i=(n+1)i. As the collectors of the signal transistors T s1 , T s2  are virtually grounded, the resistors 2dR are connected in parallel with each other and this parallel circuit is connected in series with the resistor -dR, resulting in 0 Ohm net. Let the resistance value of the series arrangement of resistors R 1  +R 2  +R 3  =R tot , let V 1  be the signal voltage on the in/output I/O, and let the connection to the line transformer of the in/output I/O be translated into a virtually grounded half line resistance R l  /2; then the following condition will hold: 
     
         Y.sub.1 =iR.sub.tot =R.sub.l /2·i.sub.l =R.sub.l /2(n+1)i, 
    
     from which it follows that: 
     
         R.sub.tot =(n+1)R.sub.l /2 (line matching condition). 
    
     As a result of a virtual impedance in the place of the balance in the hybrid circuit in accordance with the invention forming a correct terminating impedance because of feedback, an electronic measure is taken to minimize dissipation loss in the balance on transmitting. 
     Subsequently, the hybrid balance condition will be calculated, assuming for convenience that a signal current i t  in the input I results in a signal voltage O at the output O, the signal current i t  in the input I branching into partial signal currents i 2  and i 3  because of the resistors R 2  and R 3 , as represented in FIG. 1, with the following conditions holding for these partial signal currents: ##EQU2## 
     It is likewise assumed that the in/output I/O is virtually grounded via the half line resistor R l  /2. As it is assumed that the transmit current i t  in the input I results in a signal current i r  from the output equalling 0, the total partial signal current i 2  will flow through R 2  and through R 1 . This will result in the following equation: 
     
         i.sub.l ·R.sub.l /2=i.sub.2 ·R.sub.1 
    
     As the partial signal current i 3  equally branches over signal transistors T s1 , T s2  through R 3 , these equally branched partial currents multiplied by the coefficient n will occur in the auxiliary transistors T h1 , T h2 , so that the following condition will hold: 
     
         i.sub.l =ni.sub.3 /2+ni.sub.3 /2-i.sub.2 
    
     Now the following condition holds: 
     
         R.sub.l /2·(ni.sub.3 -i.sub.2)=R.sub.1 ·i.sub.2 
    
     
         or: ##EQU3## TI or: 
    
     
         (nR.sub.2 -R.sub.3)·R.sub.l /2=R.sub.1 ·R.sub.3 (hybrid balance condition). 
    
     If R 2  =R 3  it will follow that: 
     
         (n-1)·R.sub.l /2=R.sub.1. 
    
     If, in addition, R 2  =R 3  =R l  /2 the line matching condition is fulfilled at the same time. 
     If we take R 2  =R 3  =R l  /2=300 Ohms as a numerical example, it will hold that R 1  =(n-1)·300 ohms. If, for example, we take 12 for n, R 1  will be 3.3 kilohms. As observed before this resistor R 1  can be designed to be an external resistor. 
     Owing to the use of complementary auxiliary transistors T h1 , T h2  a design in accordance with FIG. 1 of the hybrid circuit according to the invention will need at least supply voltage, which is the difference in voltages f supply lines V 1  and V 2 , which difference has to exceed the peak value of the signal voltage v 1  incremented by two times the saturation voltage of the collector-emitter path of the auxiliary transistors T h1 , T h2 , which saturation voltage can amount to approximately 100 millivolts. 
     A more practical embodiment of the hybrid circuit with complementary transistors in accordance with the present invention based on the circuit of FIG. 1 will now be further described with reference to FIG. 2. 
     In FIG. 2 is shown a complete hybrid circuit to clearly show that the half sections are not axially symmetrical but form a universal coupling. Elements corresponding with those in FIG. 1 are indicated by the same reference characters. By providing a direct current source S in each half section the resistors -dR and 2dR in FIG. 1 can be omitted and there will be no need of the small direct voltages +dE and -dE at the inverting inputs of the operational amplifiers A1 and A2. Corresponding elements in the upper half section have identical reference characters but are distinguished by an accent. Respective coupling-transistors T k  and T&#39; k  have been extended to the half sections of the complete hybrid circuit in FIG. 2. 
     The half section of the hybrid circuit shown in FIG. 2 corresponding to the half section shown in FIG. 1 will henceforth be called the left section, the other half obviously being called the right section. 
     Let it be assumed that i t  =i r  =0; a signal current i 1  into the in/output I/O of the left section will then result in a current i through the resistor circuit R 1 , R 2 , R 3  to the junction point with the current source S, supplying a current J, to the collector of signal transistor T s2  and the non-inverting input of the operational amplifier A 2 , whose output is connected to the base of signal transistor T s2  and whose inverting input is connected to a reference voltage (ground point) to which the inverting input of operational amplifier A1 is also connected, whose non-inverting input is connected to the collector of signal transistor T s1  and whose output is connected to the base of signal transistor T s1 . By means of the operational amplifiers A1, A2 connected thus, the signal transistors T s1 , T s2  are virtually switched as diodes. The base of signal transistor T s2  is connected to the base of auxiliary transistor T h2  and likewise to the base of coupling transistor T k . Due to this current mirror circuit the collector currents of the signal transistor T s2 , auxiliary transistor T h2  and coupling transistor T k  are interrelated in a ratio of 1:n:1. In a like manner the collector currents of signal transistor T&#39; s2  auxiliary transistor T&#39; h2  and coupling transistor T&#39; k  of the right section are also interrelated in a ratio of 1:n:1. The collector current of signal transistor T s1  of the left section is further equal to the collector current of coupling transistor T&#39; k , due to the universal coupling with coupling transistor T&#39; k  of the right section as the operational amplifier A1 substantially draws no current. The signal transistor T s1  being virtually connected as a diode and its base being connected to the auxiliary transistor T h1 , a current mirror circuit will be formed, causing the collector current of the auxiliary transistor  +  T h1  to be n times the collector current of signal transistor T s1 . The circuit formed by the auxiliary transistor T h1  and signal transistor T s1  in the left section and the coupling transistor T&#39; k  the signal transistor T&#39; s2  and the auxiliary transistor T&#39; h2  in the right section can therefore be called a current mirror circuit. The same applies to the signal transistor T s2 , auxiliary transistor T h2  and coupling transistor T k  of the left section and the signal transistor T&#39; s1  and auxiliary transistor T&#39; h1  in the right section. 
     The hybrid circuit of FIG. 2 can possibly be designed to be complementary, that is to say that PNP-transistors are replaced by NPN-transistors and vice versa. 
     Analogous to FIG. 1, the line matching condition can be calculated as follows: 
     
         R.sub.tot =R.sub.1 +R.sub.2 +R.sub.3 =(2n+1)·R.sub.l /2 
    
     and the hydrid balance condition: 
     
         R.sub.l /2·(2nR.sub.2 -R.sub.3)=R.sub.1 R.sub.3. 
    
     Letting R 2  and R 3  be equal, the two conditions are fulfilled if: 
     
         R.sub.1 =(2n-1)·R.sub.1 /2 and R.sub.2 =R.sub.3 =R.sub.l /2 
    
     A preferred embodiment of an axially symmetrical hybrid circuit will now be described with reference to FIG. 3 showing a half section only using NPN-transistors in the signal paths and with a possibly higher limit frequency having a detrimental effect on the supply voltage requiring a supply voltage which is one base-emitter voltage higher. Elements in FIG. 3 corresponding to those in FIG. 1 are again indicated by identical reference characters. In the half section of FIG. 3 there is a single signal transistor T s  whose collector is virtually grounded through the operational amplifier A having its inverting input connected to a reference voltage (ground), the signal transistor T s  being virtually switched as a diode by connecting the non-inverting input of the operational amplifier A to its collector and by connecting the output of the operational amplifier A to its base. The signal transistor T s  together with auxiliary transistor T h2  forms a current mirror circuit causing the collector current of the auxiliary transistor T h2  to be n times the collector current of the signal transistor T s . The signal transistor T s  not only forms a current mirror circuit with auxiliary transistor T h2 , but with coupling transistor T k  as well. The collector current of coupling transistor T k  is equal to the collector current of the signal transistor T s . The respective transistors T c1  and T c2  are connected in parallel with the auxiliary transistors T h1  and T h2 , transistor T c1  being connected as a diode. The collector of coupling transistor T k  is connected to the collector of transistor T c1 , a direct current source S 2  being connected to the junction point of the collectors and supplying a current 2J. A current source S 1  supplying a current J is connected to the junction point of the resistor circuit R 1 , R 2 , R 3 , the collector of the signal transistor T s  and the non-inverting input of the operational amplifier A. 
     Let it be assumed that a line signal current i l , supplied to the in/output I/O of the half hybrid circuit of FIG. 3 results in a current i through the resistor circuit R 1 , R 2 , R 3  and that i r  =i t  =0, the current i will than flow through the signal transistor T s  and also through the coupling transistor T k  and the transistor T c2  tneand the current ni will flow through the auxiliary transistor T h2 . The current i through the coupling transistor T k  will entail a current i through the transistor T cl  and this current will result in a current ni through the auxiliary transistor T h1 . In other words auxiliary transistors T h1  and T h2  are connected to the signal transistor T s  in a current mirror circuit. 
     Analogous to the aforedescribed embodiments the following condition holds for line matching: 
     
         R.sub.tot =(2n+3)·R.sub.l /2 
    
     As regards the hybrid balance condition the following holds: 
     
         ((2n+2)R.sub.2 -R.sub.3)·R.sub.l /2=R.sub.1 ·R.sub.3. 
    
     If again it is assumed that R 2  =R 3  these two conditions are fulfilled if: 
     
         R.sub.1 =(2n+1)·R/2 and R.sub.2 =R.sub.3 =R/2. 
    
     Although hereinbefore a 1:1 line output transformer ratio was assumed, with a different line output transformer ratio the maximum line signal voltage can be accommodated to the supply voltage. By implementing this measure the other transformer ratio can act as a parameter in the line matching and hybrid balance condition. At a ratio of 1:m the following condition will hold for FIG. 3: 
     
         R.sub.1 =m.sup.2 (2n+1)·R.sub.l /2 and R.sub.2 =R.sub.3 =m.sup.2 R.sub.l /2. 
    
     In FIG. 3 the current source S 2  forces transistor T c1  to supply a current which is complementary to the current through coupling transistor T k  and therefore the current through signal transistor T s . 
     Also in FIG. 3 the current coefficient n provides a virtual input resistance of for example 300 ohms on the in/output I/O. 
     In FIG. 3 a transmitter current i t  in the input I with i r  =0 results in a line current i l  in the in/output I/O which equals: ##EQU4## and if R 2  =R 3  the condition holds that: 
     
         i.sub.l =(n+0.5)·i.sub.t. 
    
     The signal voltage v r  scanned by a receiver on the output O equals: ##EQU5## With R 1  =(2n+1)-R l  /2 and R 2  =R 3  =R l  /2 the following condition holds: ##EQU6## 
     In the embodiments of the integratable symmetrical balance hybrid circuit in accordance with the invention discussed and shown hereinbefore, for clarity&#39;s sake it was assumed to use operational amplifiers for virtually grounding collectors of signal transistors and virtually switching these transistors as diodes to result in a current mirror circuit. Such a use of operational amplifiers is not necessary, though, as will be explained hereinafter with reference to FIGS. 4A-C, likewise indicating how a virtual ground point can be simply provided. 
     FIGS. 4A-C correspond to FIG. 3 and identical reference characters are used. The differences between FIG. 3 and FIG. 4A are that the signal transistor T s  is switched as a diode and the operational amplifier A is substituted for a PNP-transistor T v , whose base is connected to a reference voltage &#34;O&#34; (ground), its collector being connected to the junction point of the bases of the transistors T s , T k , T c2  and T h2 , and its emitter being connected to the junction point of direct current source S 1  and resistor R 3 , the collector of T s  not being connected to the latter junction point. A disadvantage of the circuit of FIG. 4A could be that the virtual ground point between resistor R 3 , direct current source S 1  and the emitter of the PNP-transistor T v  is a virtual ground point only by approximation due to the base emitter voltage of this transistor T v . FIGS. 4B and 4C give solutions to this problem, the PNP-transistor T v  being simulated (T v ) with the aid of a number of transistors and possibly a diode. FIGS. 4B and 4C show the base-emitter and collector connections b, e, c of the simulated PNP-transistor T v . 
     The operation of the circuits shown in FIGS. 4A-C will be clear for those skilled in the art and a further explanation thereof will not be given, while it should be observed that there are and that there can be designed a great many more of these circuits. 
     The direct current sources S, S&#39;, S 1  and S 2  as well as direct current sources which are not shown are preferably PNP-transistors.