Abstract:
A monolithic micro scanning device comprising multiple substrates; source of light for generating a light beam disposed on one of said substrates; and micro mirror disposed on one of said substrates for repetitively and cyclically moving light beam to scan insignia impregnated on a surface of different articles is described. More particularly, the scanning device comprises a combination of stacked dies in suitable form factor to optimize a system configuration and packaging.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention generally relates to integrated scanning systems for reading multiple insignia impregnated on a surface of different articles and, more particularly, to scanning system based on nano-components and integrated in one monolithic device.  
           [0003]    2. Description of Related Art  
           [0004]    A general concept of a scanning device has been discussed in a number of U.S. patents and publications. Multiple scanning devices currently are available on a market for reading various insignia impregnated on a surface. On the other hand, the progress in the nanotechnology and particular in the manufacturing of resonantly excited scanning mirrors, light emitting and receiving components, and micro optics have reached a point when it have become apparent that new concepts for the design of compact monolithic micro scanners should be applied.  
           [0005]    The challenge of designing of integrated scanning devices had evolved over the years as the scale and extend of functions assigned to devices has increased. The integration requirements have evolved in much the same way. As the scale and extend increased, the single function system became less practical. Multifunctional system design presented a new set of problems related to physical, electrical, logical, and etc. system interactions. Collaboration between different components/modules/subsystems carrying out application tasks usually requires a sharing of signals and/or data. Designers typically are solving these collaboration problems by employing specific proprietary schemes.  
           [0006]    For a long time the focus in the system design was on a chip level, making chips smaller, faster, more powerful and more efficient while simultaneously reducing cost and improving reliability. The manufacturers simply designed the integrated circuits and packaged them. There have been several fundamental shifts in the history of electronic packaging that profoundly affected an electronic industry, such as  
           [0007]    Surface mount technology (SMT)  
           [0008]    Area array packages, like ball grid array (BGA)  
           [0009]    Chip scale packaging  
           [0010]    Wafer level packaging (WLP)  
           [0011]    From a functional point of view, a package is a link between the small dimensions of the integrated circuits and the larger dimensions of the printed circuit boards. It is quite obvious that methods developed for integrated microelectronic assembly could be applied for integrating and packaging more complex monolithic systems with multiple physical components. A monolithic micro scanner is expected to have several advantages compared with conventional scanners: smaller physical footprint, less power consumption, and longer lifetime.  
           [0012]    A crucial objective of nanotechnology is to make products inexpensively. Inherently nanotechnology is suitable for low-cost production and high flexibility in production, which is vital for maintaining continuous competitive capability for any technology.  
           [0013]    The design of smaller, lighter, and thinner scanning system is only possible by further miniaturization of system&#39;s components and implementation of the conceptually new design architecture. System on a package (SOP) paradigm provides such desired capabilities.  
           [0014]    SOP offers significant savings in space and costs, as well as provides an optimum distribution of functions between or within system&#39;s components. There are several advantages of SOPs compare to other integrating technologies:  
           [0015]    SOPs can carry diverse components form factors such as flip chips, SMT discretes, etc.  
           [0016]    It is based on techniques and know-how developed for maximum utilization of the surface area of the package; it also relaxing the application board design requirements.  
           [0017]    Low package failure rates can be achieved through the use of different techniques and proven board attachment technologies.  
           [0018]    Electrical characteristics and efficiency are enhanced through shorter interconnections of die on an SOP.  
           [0019]    SOP is shortening a design time. Use of SOP can eliminate the need to design a single, large, complex chip to contain diverse functions. Smaller, functional chips can be tightly integrated into an SOP, often with no sacrifice in layout complexity vs. a single chip solution.  
           [0020]    The integration of MEMS scanning systems fundamentally has close association with particular applications. There is a significant difference between the rationales for packaging integrated circuits (IC) and packaging MEMS based scanning devices. The purpose of IC packaging is to provide physical support for the chip, to provide an electrical interface to active chips in the system, to supply signal, power and ground interconnections, allow heat dissipation, and to isolate the chip physically from its environment. MEMS devices, on the other hand, are intended to interface directly with their environment. Consequently, they need an application specific packaging scheme and a corresponding functional interface. MEMS&#39;s package is a part of a complete system and all components of the system must function together and be compatible with each other.  
           [0021]    Numerous approaches for designing integrated scanning systems are known in the prior art. However, their main focus was on the integration of a scanning device on a common substrate. It is a purpose of the present invention to provide a monolithic scanning device, which can be composed from multiple components with different form factors, utilizes with high efficiency available package space to provide “more functionality in a smaller space”, and has a superior performance.  
         SUMMARY OF INVENTION  
         [0022]    Briefly, and in general terms, the present invention provides a monolithic micro scanning device including multiple substrates; source of light for generating a light beam disposed on one of said substrates; and micro mirror disposed on one of said substrates for repetitively and cyclically moving light beam to scan insignia impregnated on a surface of different articles. More particularly, the scanning device comprises a combination of stacked dies in suitable form factor to optimize a system configuration.  
           [0023]    The novel features which are considered as characteristics for the invention are set forth in particular in the appended claims. The invention itself, however, both as to its construction and its method of operation, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0024]    [0024]FIG. 1 is showing a simplified schematic drawing of a die-up BGA construction.  
         [0025]    [0025]FIG. 2 is showing a simplified schematic drawing of a die down center bond substrate BGA construction.  
         [0026]    [0026]FIG. 3 is showing a simplified schematic drawing of die down bumped die substrate BGA construction.  
         [0027]    [0027]FIG. 4 is showing a simplified schematic drawing of a flip chip package.  
         [0028]    [0028]FIG. 5 is showing a simplified schematic drawing of a pyramid stack package.  
         [0029]    [0029]FIG. 6 is showing a simplified schematic drawing of stacked package with multiple die of the same size.  
         [0030]    [0030]FIG. 7 is showing a simplified schematic drawing of folded-flex stacked package with two die.  
         [0031]    [0031]FIG. 8 is showing a simplified schematic drawing of monolithic scanning engine. 
     
    
     DETAILED DESCRIPTION  
       [0032]    The present invention is directed to a scanning system based on nano-components and integrated in one monolithic device. While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications and embodiments within the scope thereof and additional fields in which the present invention would be of significant utility.  
         [0033]    In the beginning we will describe some packaging constructions, which will be employed in the present invention.  
         [0034]    [0034]FIG. 1, shows a schematic view of the basic configurations of the Ball Grid Array (BGA) package. It is constructed of a substrate  105 , for example made of plastic, silicon oxide, silicon glass, or other low k-dielectric material onto which a die  101  in mounted and an array of balls  104  is attached. The die  101  is attached to the substrate  105  by a die attached material  103 , such, for example, as Ablebond 8380 Electrically Conductive Die Attach Adhesive manufactured by Ablestik Electronic Materials and Adhesives of California. The die  101  is encapsulated by overmold compound  107  for protection. All configurations of BGA package maintain the same ball interface, although they use different die connection methods. In the die-up substrate configuration, see FIG. 1, the die  101  is connected to the substrate  105  by wire bonds  102 . In the die down center bond substrate configuration, see FIG. 2, the die  201  is connected to the substrate  205  by wire bonds  202 . In the die down bumped die substrate configuration, see FIG. 3, the die  301  is connected to the substrate  305  by fine-pitch ball array  302 . The last configuration sometimes identified as a chip scale package (CSP), since overall package size of a CSP is typically no larger that 1.2 times of the silicon die.  
         [0035]    [0035]FIG. 4 shows a schematic drawing of a flip chip package. It is quite easy to see that flip chip package is sharing the same basic architecture as a die down bumped die substrate configuration. The flip chip package comprises first die  401 , second die  405 , die underfill  403 , solder bumps  402 , solder balls  404 , and conductive pads  406 . From a manufacturing point of view, flip chip assembly is the process of connecting face down (flipped) components directly with the board or substrate through conductive bumps on the chip bond pads. In other words, the semiconductor devices are mounted and electrically connected face-down directly onto substrates to the next level of interconnect. The contacts are made directly between the device and the electronic product, rather than through the wires used in wire bonding. This results in significant signal inductance reduction, because the interconnects are much shorter, compared to wire bonding. Since flip chip connections can use the whole area of the die, flip chip can accommodate many connections on a smaller die and the I/O density off the chip can be dramatically increased compare to wire bonding connections. The most important advantages of flip chip package are as follows:  
         [0036]    Superior electrical performance with reduced inductance and capacitance of the connections and shortened signal paths;  
         [0037]    Low electromagnetic emissions;  
         [0038]    Flexibility in layout and the potential for a high number of connections per chip area;  
         [0039]    Better heat transfer characteristics with a heat sink directly attached to the die;  
         [0040]    High potential for cost reduction;  
         [0041]    The most rugged interconnection method; flip chips, when completed with an adhesive “underfill,” are practically solid little blocks of cured epoxy.  
         [0042]    The integration of multiple silicon dies into a stacked package is providing reduced space, weight saving and enhanced electrical performance. The stacking principle is usually applied to bare die. There are several techniques for stacking. One of the simplest techniques is to bond a smaller die on top of a larger one, leaving enough clearance for wire bonding. The pyramid wire bonded stack is shown in FIG. 5, where the die  501  is supporting the die  502 , which in its turn is supporting the die  503 . The bonding wires  504 ,  505 , and  506  are connected to conductive pads  507 ,  508 ,  509  and  510 . First die is wire bonded and then the next die is attached on top of the first followed by wire bonding. The process is repeated until the desired stack is obtained. The stack package also includes die attach layers  511  and  512 , die underfill layer  513 , and plastic substrate  515 , onto which the die  501  is mounted and an array of balls  514  is attached. Flexible circuitry can be used to connect multiple levels. Flex is a best option where the volume of the device must be minimized.  
         [0043]    The stacked die can all be the same size as it is shown on FIG. 6. The significant difference in this design is that die attach layers  611  and  612  do not support all die&#39;s suffices  602  and  603 .  
         [0044]    The folded flex stacked die package, see FIG. 7, is offering a new level of flexibility for the design of micro system. The flexible substrate  705  is folded so to stack at least some of the microelectronic elements (in present example die  701  and  702 ) in substantially vertical alignment with one another to provide a stacked assembly with the conductive terminals (solder balls  704  or lands) exposed at the bottom end of the stack. Die  701  and  702  are connected to flexible substrate  705  by fine-pitch ball array  707 . Die also can be connected to substrate by a bumpless-buildup-layer. Passive components  707  may be added in the same package to increase its functionality.  
         [0045]    The major reasons for implementation of stacked die applications, as it was already mentioned, are reduced space, weight saving and enhanced electrical performance of the portable devices. Stacking of chips, in which two or more ICs of different types are placed at the same coordinates in the x-y plane, is an alternative to silicon integration. Stacked die applications provide flexibility in combining different devices without touching the design level of silicon. The functionality of the device can be doubled or tripled in the same package size. The vertically integrated system in a package has a much higher package integration ratio compared to the single die solution. In addition, the electrical performance and reliability of stacked die is improved because only one package has to be tested.  
         [0046]    The variations of stacked-die package options define a special type of packaging creating which is commonly called as 3-D packages. Depending on the level of functional integration, 3-D packages may also be classified as systems-in-packages (SIP).  
         [0047]    [0047]FIG. 8 shows a simplified schematic drawing of monolithic scanning engine  800 . The flexible substrate  802  is folded to accommodate the following components:  
         [0048]    a light receiving element  804 , such as photodiode, CCD or SMOS imaging component, comprising die  803 , an optical component  806 , and connecting elements  805 ;  
         [0049]    a light emitting element  807 , such as laser diode, LED, or VCSEL, comprising die  808 , an optical component  809 , and connecting elements  810 ;and  
         [0050]    a control and/or processing circuitry  822  comprising die  801  and connecting elements  824 .  
         [0051]    The die of light receiving  804  and emitting elements  807  may be connected to the substrate  802  by fine-pitch ball arrays, bumpless buildup layer, or contacts developed by NanoPierce Technologies Inc. and which consist of embedding small hard particles on a contact pad and plating over it with nickel. These hard, conductive protrusions are then used to make a contact between pads on a chip and pads on a substrate. There is no wafer bumping or wire bonding kind of process to create the connection.  
         [0052]    In another possible embodiment the light receiving and emitting element may be deposed directly on the substrate.  
         [0053]    A control and/or processing circuitry  822  is responsible for the control and/or processing signals from/to light emitting and light receiving elements  804  and  807 .  
         [0054]    The flexible substrate  817  is accommodating a light deflecting element  816  which is comprised of oscillating micro-mirror  815  and connecting elements  814 . The micro-mirror may be such as an electro-statically excited one or two dimensional mirror similar to the micro-mirror developed in Fraunhofer Institute of Microelectronic, Dresden, Germany or thermally actuated micro-mirror developed in Ecole Politechnique Federal de Lausanne, Lausanne, Switzerland.  
         [0055]    A control circuitry  820  is responsible for generating all signals necessary for excitement and oscillation of micro-mirror. It should be pointed out that control circuitry  820  may be integrated with a control and/or processing circuitry  822  on one die.  
         [0056]    The substrates  802  and  817  may be connected by a connector  811  which operationally connects control circuitries  820  and  822  through contact pads  821 . Connector  811  can also serve as a structural element supporting the mechanical integrity of the device.  
         [0057]    To direct a beam a light  828  emitting by the light emitting element  897  to the light deflecting element  820 , an additional mirror  827  is employed. The deflected beam of light  829  is directed through window  826 .  
         [0058]    It will be apparent to those skilled in the art that various modifications and variations can be made in the monolithic scanner by employing multiple packaging schemes without departing from the spirit or scope of the present invention.