Abstract:
A class D amplifier capable of compressing a dynamic range and reproduction by changing on a real time basis a modulation ratio to a non-linear ratio in accordance with amplitude of an input signal. The class D amplifier including a triangular waveform generation circuit that generates a deformed triangular waveform used as a comparison waveform for amplitude modulating an analog input signal, the triangular waveform generation circuit comprising a pulse generation circuit for generating a plurality of first pulse signals, a plurality of pulse extraction circuit for extracting said first pulse signals selectively, and for outputting second pulse signals during the time according to extracted first pulse signals, a plurality of three state buffers to which a clock pulse signal for basic cycles is provided as an input signal, one of said second pulse signals is provided as a control signal, and said clock pulse signal for basic cycles is output during a period for said one of second pulse signal is provided, and a integration circuit, having a time constant thereof changing in accordance with the output of said three state buffer, for generating said deformed triangular waveform corresponding to the time constant based on the clock pulse signal for basic cycles.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     In a class D amplifier for driving highly efficiently speakers in an acoustic apparatus, this invention relates to a class D amplifier equipped with a circuit for generating a deformed triangular wave as a comparison waveform necessary for conducting pulse amplitude modulation of an analog input waveform.  
         [0003]     2. Description of the Related Art  
         [0004]     The class D amplifier according to the prior art uses a triangular wave as a comparison waveform necessary for conducting pulse amplitude modulation of an analog input waveform and this triangular wave is generated from a rectangular wave by using an integration circuit (refer to JP-A-6-319197).  
         [0005]     When the triangular wave is used, however, a modulation ratio is likely to get into saturation when pulse amplitude modulation of an input signal having amplitude exceeding the crest of the triangular wave is conducted. Because the input/output characteristics are linear, a large number of odd-numbered order harmonics develop at a large amplitude output reaching the saturation level and DC components are applied for a long time to the speakers as a load. These drawbacks become more remarkable when a power source voltage of the amplification portion is lower.  
       SUMMARY OF THE INVENTION  
       [0006]     The invention is directed to provide a class D amplifier that can eliminate these problems of the prior art, compresses a dynamic range by changing an amplification ratio to a non-linear ratio on the real time basis in accordance with the amplitude of the input signal and reproduces the input signal.  
         [0007]     To accomplish the object described above, a class D amplifier including a triangular waveform generation circuit that generates a deformed triangular waveform used as a comparison waveform for amplitude modulating an analog input signal, the triangular waveform generation circuit comprising a pulse generation circuit for generating a plurality of first pulse signals, a plurality of pulse extraction circuit for extracting said first pulse signals selectively, and for outputting second pulse signals during the time according to extracted first pulse signals, a plurality of three state buffers to which a clock pulse signal for basic cycles is provided as an input signal, one of said second pulse signals is provided as a control signal, and said clock pulse signal for basic cycles is output during a period for said one of second pulse signal is provided, and a integration circuit, having a time constant thereof changing in accordance with the output of said three state buffer, for generating said deformed triangular waveform corresponding to the time constant based on the clock pulse signal for basic cycles.  
         [0008]     According to the class D amplifier of the invention, the modulation ratio is non-linearly changed on a real time basis in accordance with the amplitude of the input signal so that the amplification ratio can be increased when a small signal is inputted and can be decreased when a large signal is inputted, and the occurrence of large higher harmonics resulting from saturation at the time of the input of the large signal can be suppressed. In addition to the above, reproduction can be made while a mean acoustic level of the output from the speakers is raised and a dynamic range is compressed. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]      FIG. 1  is a block diagram showing a construction of a class D amplifier;  
         [0010]      FIG. 2  is a block diagram showing a construction of a comparison waveform generation circuit;  
         [0011]      FIG. 3  is a block diagram showing a construction of an integration circuit;  
         [0012]      FIG. 4  is a timing chart for acquiring a deformed comparison triangular waveform;  
         [0013]      FIG. 5  is a signal waveform diagram of a class D amplifier using the deformed comparison triangular waveform;  
         [0014]      FIG. 6  is an input/output characteristic diagram of the class D amplifier using the deformed comparison triangular waveform; and  
         [0015]      FIG. 7  is a block diagram showing another construction about connection of resistors in an integration circuit. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0016]     A preferred embodiment of the invention will be hereinafter explained with reference to the accompanying drawings. First, an overall construction of a class D amplifier to which the invention is applied will be explained with reference to a block diagram of  FIG. 1 . As shown in  FIG. 1 , the class D amplifier  1  includes a counter circuit  2  as a pulse generation circuit, a pulse extraction circuit  3 , a 3-state buffer  4 , an integration circuit  5 , a sample-and-hold circuit  6 , a comparator  7 , a current buffer  8  and a low-pass filter  9 . The counter circuit  2 , the pulse extraction circuit  3 , the 3-state buffer  4  and the integration circuit  5  constitute a comparison waveform generation circuit according to the invention. Each constituent element other than the comparison waveform generation circuit has the same construction and the same function as those of the prior art circuits.  
         [0017]     Next, the comparison waveform generation circuit will be explained in detail with reference to  FIG. 2 . The counter circuit  2  is constituted into a ring counter including 32 delay flip-flops (hereinafter called “DFF”)  1  to  32 . The pulse extraction circuit  3  is constituted by seven 4-NAND gates F to L. An output terminal Q of each DFF  1  to  31  is connected to an input terminal D of a next stage and an inversion output terminal QN (a terminal that generates an output having an inverted logic level relative to the output terminal Q) of DFF  32  of the last stage is connected to one of the input terminals of the 4-NAND gate F. A reset terminal CDN of each DFF  1  to  32  is connected to a common terminal RSTN. A logic level of the output terminal Q of each DFF  1  to  32  changes to an “H” level when a reset signal is inputted from the terminal RSTN. A clock terminal CP of each DFF  1  to  32  is connected to the output terminal Q of a common toggle flip-flop (hereinafter called “TFF”)  1 . A counting operation is made by fetching an output from a subsequent stage whenever the clock pulse from this output terminal Q rises.  
         [0018]     An ICLK pulse is inputted to the input terminal CP of the TFF  1 . The output terminal Q of each TFF  1  to  5  is connected to the input terminal CP of each TFF  2  to  6  of the next stage. The reset terminal CDN of each TFF  1  to  6  is connected to the common terminal RSTN. The logic level of the output terminal Q of each TFF  1  to  6  changes to “H” when a reset signal is inputted from the terminal RSTN.  
         [0019]     An output terminal of each 8-NAND gate B, C, D and an output terminal of a 7-NAND gate E are connected to each input terminal of a 4-NOR gate A while an input terminal D of the DFF  1  is connected to the output terminal of the 4-NOR gate A. The inversion output terminal QN of each DFF  1  to  8  is connected to each input terminal of the 8-NAND gate B. The inversion output terminal QN of each DFF  9  to  16  is connected to each input terminal of the 8-NAND gate C. The inversion output terminal QN of each DFF  17  to  24  is connected to each input terminal of the 8-NAND gate D. The inversion output terminal QN of each DFF  25  to  31  is connected to each input terminal of the 7-NAND gate E.  
         [0020]     The inversion output terminal QN of each of the DFF  1 ,  16  and  17  is connected to each input terminal of the 4-NAND gate F in addition to the DFF  32  described above. The inversion output terminal QN of each of the DFF  2 ,  15 ,  18  and  31  is connected to each input terminal of the 4-NAND gate G. The inversion output terminal QN of each of the DFF  3 ,  14 ,  19  and  30  is connected to each input terminal of the 4-NAND gate H. The inversion output terminal QN of each of the DFF  4 ,  13 ,  20  and  29  is connected to each input terminal of the 4-NAND gate I. The inversion output terminal QN of each of the DFF  5 ,  12 ,  21  and  28  is connected to each input terminal of the 4-NAND gate J. The inversion output terminal QN of each of the DFF  6 ,  11 ,  22  and  27  is connected to each input terminal of the 4-NAND gate K. The inversion output terminal QN of each of the DFF  7 ,  10 ,  23  and  26  is connected to each input terminal of the 4-NAND gate L. These seven 4-NAND gates F to L constitute the pulse extraction circuit  3 .  
         [0021]     On the other hand, the output terminal of the 4-NAND gate F is connected to a control input terminal of a 3-state buffer M. The output terminal of the 4-NAND gate G is connected to a control input terminal of a 3-state buffer N. The output terminal of the 4-NAND gate H is connected to a control input terminal of a 3-state buffer O. The output terminal of the 4-NAND gate I is connected to a control input terminal of a 3-state buffer P. The output terminal of the 4-NAND gate J is connected to a control input terminal of a 3-state buffer Q. The output terminal of the 4-NAND gate K is connected to a control input terminal of a 3-state buffer R. The output terminal of the 4-NAND gate L is connected to a control input terminal of a 3-state buffer S. The output terminal Q of the TFF  6  is connected to the input terminal of each 3-state buffer M to S and a ZCLK signal as a basic cycle for generating a comparison waveform outputted from the TFF  6  is inputted. Therefore, the output of each 3-state buffer M to S is inputted to the integration circuit  5 . Therefore, the output pulses of the 4-NAND gates F to L extracting the output pulses of the DFF  1  to  32  become ENABLE and DISABLE signals and control the outputs of the 3-state buffers M to S.  
         [0022]     Next, a construction of the integration circuit  5  will be explained with reference to  FIG. 3 . A feedback capacitance C 101  is interposed between an opposite phase input terminal and an output terminal of an operational amplifier OP 1 . The opposite phase input terminal (−) of the operational amplifier OP 1  is connected to the output terminal Q of the TFF  6  through a resistor R 100 . One of the ends of a resistor R 101  is connected to the output terminal Z 1  of the 3-state buffer M and the other end is connected to an intermediate part between the opposite phase input terminal (−) of the operational amplifier OP 1  and the resistor R 100 . One of the ends of each resistor R 102  to  107  is connected to an output terminal Z 2  to Z 7  of each 3-state buffer N to S. The other end of each resistor R 102  to  107  is connected to an intermediate part between the output terminal Z 1  to Z 6  of each 3-state buffer M to R and each resistor R 101  to  106  connected to the output terminal Z 1  to Z 6 . The resistance value of each resistor  101  to  107  is set to be equal. On the other hand, the positive phase input terminal (+) of the operational amplifier OP 1  is connected to a middle point potential of the power source voltage of the class D amplifier. When the potential of the power source vantage terminal VDD is 2.5 V and the potential of the later-appearing ground terminal GND is 0 V, for example, the positive phase input terminal (+) of the operational amplifier OP 1  is connected to a constant voltage source, not shown, that generates the middle point potential of 1.25 V.  
         [0023]     The operation of the embodiment having the construction described above will be subsequently explained with reference to the timing chart of  FIG. 4 . In  FIG. 4 , symbol RSTN represents a reset signal. Symbol ICLK represents a clock pulse signal inputted to the TFF  1 . Symbol ZCLK represents an output pulse signal from the TFF  6  obtained by frequency dividing ICLK by the TFF  1  to  6 . Symbols Q 1 N to Q 32 N represent the output pulse signals from the inversion output terminals QN of the DFF  1  to  32 , respectively. Symbols Z 1  to Z 7  represent the output signals of the 3-state buffers M to S, respectively. Incidentally, ZCLK forms the basic cycle for generating the comparison waveform that is inputted to the comparator  7 .  
         [0024]     The output Q 1 N to Q 32 N of the inversion output terminal QN of each DFF  1  to  32  changes to “H” when RSTN (reset signal) rises to “H”. Therefore, the output of each 4-NAND gate F to L changes to “L”. Since each 3-state buffer M to S is under the high impedance state, it is in the non-output state. The ICLK is inputted under this state to the TFF  1 , the TFF  6  outputs the pulse signal and ZCLK changes to “H”. The TFF  1  outputs the pulse signal, the output Q 1 N of the inversion output terminal QN of the DFF  1  changes to “L” and the output of the 4-NAND gate F changes to “H”. The output Z 1  of the 3-state buffer M changes to “H” for the period in which this output is inputted, in the same way as ZCLK. The output of the inversion output terminal QN of the DFF  2  to  7  of the next stage changes to “L” whenever the TFF  1  outputs the pulse signal in this way and the output of each 4-NAND gate G to L serially changes to “H”. The output Z 2  to Z 7  of each 3-state buffer N to S serially changes to “H” for the period in which this output is inputted as the ENABLE signal to the control input terminal.  
         [0025]     Similarly, the outputs of the inversion output terminals QN of the DFF  8  and  9  serially change to “L” in succession to the DFF  7 . However, the inversion output terminal QN of each DFF  8 ,  9  remains merely connected to the input terminal of the 8-NAND gate B, C but is not connected to the input terminal of any of the 4-NAND gates F to L. Therefore, the ENABLE signal is not inputted to the control input terminal and all the 3-state buffers M to S are under the non-output state with high impedance.  
         [0026]     Next, when the output Q 10 N of the inversion output terminal QN of the DFF  10  changes to “L”, the output of the 4-NAND gate L changes to “H” and the output Z 7  of the 3-state buffer S changes to “H” for the time in which this output is inputted as the ENABLE signal to the control input terminal in the same way as ZCLK. The output of the inversion output terminal QN of each DFF  11  to  16  of the next stage changes to “L” in this way whenever the TFF  1  outputs the pulse signal and the outputs of the 4-NAND gates K to F serially change to “H” in the sequence opposite to the above. The outputs Z 6  to Z 1  of the 3-state buffers R to M serially change to “H” in the same way as ZCLK for the time in which this output is inputted as the ENABLE signal to the control input terminal.  
         [0027]     The signal ZCLK that is the output pulse signal of the TFF 6  is inverted to change to “L” when the 33 rd  ICLK is inputted to the TFF  1 . The output Q 1 N of the inversion output terminal QN of the DFF 17  changes to “L”. The output of the 4-NAND gate F changes to “H”. The output Z 1  of the 3-state buffer M changes to “L” for the time in which this output is inputted as the ENABLE signal to the control input terminal, in the same way as ZCLK. The output of the inversion output terminal QN of the DFF  18  to  23  of the next stage changes to “L” in this way whenever the TFF  1  outputs the pulse signal and the outputs of the 4-NAND gates G to L serially change to “H”. The outputs Z 2  to Z 7  of the 3-state buffers N to S serially change to “L” in the same way as ZCLK for the time in which this output is inputted as the ENABLE signal to the control input terminal.  
         [0028]     Similarly, the outputs of the inversion output terminals QN of the DFF  24  and  25  serially change to “L” in succession to the DFF  23 . However, the inversion output terminal QN of each DFF  24 ,  25  remains merely connected to the input terminal of the 8-NAND gate D, E but is not connected to the input terminal of any of the 4-NAND gates F to L. Therefore, the ENABLE signal is not inputted to the control input terminal of the 3-state buffers M to S and these 3-state buffers M to S are under the non-output state with high impedance.  
         [0029]     Next, when the output Q 10 N of the inversion output terminal QN of the DFF  26  changes to “L”, the output of the 4-NAND gate L changes to “H” and the output Z 7  of the 3-state buffer S changes to “L” in the same way as ZCLK for the time in which this output is inputted as the ENABLE signal to the control input terminal. The output of the inversion output terminal QN of each DFF  27  to  32  of the next stage changes to “L” in this way whenever the TFF  1  outputs the pulse signal and the outputs of the 4-NAND gates K to F serially change to “H” in the sequence opposite to the above. The outputs Z 6  to Z 1  of the 3-state buffers R to M serially change to “L” in the same way as ZCLK for the time in which this output is inputted as the ENABLE signal to the control input terminal.  
         [0030]     These outputs Z 1  to Z 7  are added to ZCLK and the sum is inputted to the operational amplifier OP 1  of the integration circuit  5 . The resistance value in this instance is R 101  for Z 1 , R 102 +R 101  for Z 2 , R 103 +R 102 +R 101  for Z 3 , R 104 +R 103 +R 102 +R 101  for Z 4 , R 105 +R 104 +R 103 +R 102 +R 101  for Z 5 , R 106 +R 105 +R 104 +R 103 +R 102 +R 101  for Z 6  and R 107 +R 106 +R 105 +R 104 +R 103 +R 102 +R 101  for Z 7 . Therefore, the time constant of the integration circuit  5  changes in a cycle having a pulse width that is {fraction (1/32)} of the cycle of ZCLK. Consequently, the output waveform of the integration circuit  5  becomes the one that is shown in  FIG. 4  as the triangular wave undergoes deformation in accordance with the outputs Z 1  to Z 7  of the 3-state buffers M to S.  
         [0031]     When this deformed comparison waveform is inputted to the comparator  7  and is compared with the signal to be amplified, a comparator output shown in  FIG. 5  can be acquired. Because the comparison waveform has the amplitude that is non-linearly increased in the proximity of the apex, the modulation ratio is not restricted sharply. The input/output characteristics shown in  FIG. 6  can be acquired when the class D amplifier is driven with a single power source and a PWM signal is passed through the current buffer  8  and the low-pass filter  9  with the comparison waveform being the deformed triangular wave shown in  FIG. 5 .  
         [0032]     Output with reduced distortion becomes possible by continuously limiting the modulation ratio above a specific level even at an input signal level at which the class D amplifier according to the prior art gets into saturation. It becomes also possible to improve a mean sound pressure level while reducing distortion even when large amplitude signals having waveforms with rich undulation such as music signals because the modulation ratio is continuously limited when such large amplitude is inputted.  
         [0033]     The invention is not particularly limited to the embodiment described above. For example, when the pulse generation circuit is constituted by 32 stages of ring counters, the number of the pulse extraction circuits can be set to the number obtained by dividing the maximum stage number described above by 4, and the pulse generation circuit can be constituted by 4-NAND gates of the number selected from 1 to 8. Sixteen 2-NAND gates can be employed in place of the 4-NAND gates F to L. In this case, sixteen 3-state buffers and sixteen resistors may well be prepared. Deformation of the triangular wave generated by this construction is asymmetric with respect to the zero-cross point. The pulse generation circuit is not particularly limited to the 32-stage ring counters, either. Connection of the resistors  101  to  107  in the integration circuit  5  is not limited to the connection shown in  FIG. 3  and the connection shown in  FIG. 7  can also be employed.