Abstract:
A system and method to test a host bus adapter&#39;s (“HBAs”) ability to handle stream of invalid characters is provided. A data presenter module presents data to a HBA without being aware of a data format. A data producer module that is aware of the data format and schedules special characters so that the HBA can perform alignment operations. A bit offset change module changes a bit offset that is used by the data presenter module and causes to send random serial data to the HBA, which results in loss of alignment in the HBA and causes the HBA to decode invalid characters.

Description:
BACKGROUND 
   1. Field of the Invention 
   The present invention relates to host bus adapters, and more particularly to testing host bus adapters with PCI-Express port logic. 
   2. Background of the Invention 
   Storage area networks (“SANs”) are commonly used where plural memory storage devices are made available to various host computing systems. Data in a SAN is typically moved between plural host systems (that include computer systems, servers etc.) and storage systems (or storage devices, used interchangeably throughout this specification) through various controllers/adapters. 
   Host systems typically include several functional components. These components may include a central processing unit (CPU), main memory, input/output (“I/O”) devices, and streaming storage devices (for example, tape drives). In conventional systems, the main memory is coupled to the CPU via a system bus or a local memory bus. The main memory is used to provide the CPU access to data and/or program information that is stored in main memory at execution time. Typically, the main memory is composed of random access memory (RAM) circuits. A computer system with the CPU and main memory is often referred to as a host system. 
   Host systems often communicate with storage systems via a host bus adapter (“HBA”, may also be referred to as a “controller” and/or “adapter”) using an interface, for example, the “PCI” bus interface. PCI stands for Peripheral Component Interconnect, a local bus standard that was developed by Intel Corporation®. The PCI standard is incorporated herein by reference in its entirety. 
   PCI-Express is another Input/Output (“I/O”) bus standard (incorporated herein by reference in its entirety) used in this environment. PCI-Express uses discrete logical layers to process inbound and outbound information. 
   Various other standard interfaces are also used to move data between host systems and storage devices. Fibre channel is one such standard. Fibre channel (incorporated herein by reference in its entirety) is an American National Standard Institute (ANSI) set of standards, which provides a serial transmission protocol for storage and network protocols such as HIPPI, SCSI, IP, ATM and others. 
   HBAs that are placed in SANs receive serial data, align the serial data and then convert it into parallel data. A HBA determines data boundary before performing the alignment operation. A comma character is often used by the HBA to determine character and word alignment in a serial stream of data. Once a comma character is detected the HBA assumes that the received character/words are on the same boundary. Hence, it is important for a HBA to properly detect comma (or any other special character) characters in a bit stream in order to correctly process data thereafter. A HBA typically uses a state machine (or other piece of hardware) to detect comma characters and perform the alignment. 
   Conventional systems do not provide an efficient methodology to periodically test a HBA&#39;s ability to detect comma characters and then perform the re-alignment. Therefore, there is a need for a method and system that can generate random data and test a HBA&#39;s ability to detect comma characters and reacquire correct alignment, if needed. 
   SUMMARY OF THE INVENTION 
   In one aspect of the present invention, a system for testing a host bus adapter&#39;s (“HBA&#39;s”) ability to handle stream of invalid characters is provided. The system includes, a data presenter module that presents data to a HBA without being aware of a data format; a data producer module that is aware of the data format and schedules special characters so that the HBA can perform alignment operations; and a bit offset change module that changes a bit offset that is used by the data presenter module and causes to send random serial data to the HBA, which results in loss of alignment in the HBA and causes the HBA to decode invalid characters. 
   In another aspect of the present invention, a method for testing a host bus adapter&#39;s (“HBA&#39;s”) ability to handle stream of invalid characters is provided. The method includes, selecting random data, wherein a data producer module selects random data and is aware of a data format, and schedules special characters in the random data so that the HBA can perform alignment operations; converting the random data to a format that is acceptable to a receive channel in the HBA; and setting a bit off-set that results in loss of alignment in the HBA and causes the HBA to decode invalid characters, wherein a bit-offset module sets the bit offset. 
   In yet another aspect of the present invention, a testing module for testing a host bus adapter&#39;s (“HBA&#39;s”) ability to handle stream of invalid characters is provided. The testing module includes a data presenter module that presents data to a HBA without being aware of a data format; a data producer module that is aware of the data format and schedules special characters so that the HBA can perform alignment operations; and a bit offset change module that changes a bit offset that is used by the data presenter module and causes to send random serial data to the HBA, which results in loss of alignment in the HBA and causes the HBA to decode invalid characters. 
   This brief summary has been provided so that the nature of the invention may be understood quickly. A more complete understanding of the invention can be obtained by reference to the following detailed description of the preferred embodiments thereof concerning the attached drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing features and other features of the present invention will now be described with reference to the drawings of a preferred embodiment. In the drawings, the same components have the same reference numerals. The illustrated embodiment is intended to illustrate, but not to limit the invention. The drawings include the following Figures: 
       FIG. 1A  shows a block diagram of a system with a host bus adapter that is tested according to one aspect of the present invention; 
       FIG. 1B  shows a block diagram of a test module functionally coupled to a HBA, according to one aspect of the present invention; 
       FIG. 1C  shows a block diagram of a HBA that is tested, according to one aspect of the present invention; 
       FIG. 2A  shows a block diagram of a system for testing a HBA, according to one aspect of the present invention; 
       FIG. 2B  shows a block diagram of a PCI-Express receive channel that is used for testing a HBA, according to one aspect of the present invention; 
       FIG. 2C  shows the architecture of a software module for testing a HBA, according to one aspect of the present invention; 
       FIG. 2D  shows an example of character/word alignment that is used for testing a HBA, according to one aspect of the present invention; and 
       FIG. 3  shows a process flow diagram for testing a HBA, according to one aspect of the present invention; and 
       FIG. 4  shows an example of a bit-offset used for testing HBAS, according to one aspect of the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   To facilitate an understanding of the preferred embodiment, the general architecture and operation of a System will be described. The specific architecture and operation of the preferred embodiment will then be described with reference to the general architecture. 
     FIG. 1A  shows a block diagram of a system  101  where a host computing system  102  is coupled to a storage device  105  via a SAN  104 . HBA  106  facilitates data transfer between host  102  and device  105  (shown as  103 ). 
     FIG. 1B  shows a system for testing HBA  106  that is coupled to a test module  106 B via a serial interface  136 A. It is noteworthy that the adaptive aspects of the present invention are not limited to a serial interface. Test module  106 B operates as a part of any computing system. Test module  106 B is not limited to any particular interface/operating system. 
     FIG. 1C  shows a block diagram of adapter  106 . Adapter  106  includes processors (may also be referred to as “sequencers”) “RSEQ”  109  and “XSEQ”  112  for receive and transmit side, respectively for processing data received from storage sub-systems and transmitting data to storage sub-systems. Transmit path in this context means data path from a host memory (not shown) to the storage systems via adapter  106 . Receive path means data path from storage subsystem via adapter  106 . It is noteworthy, that only one processor is used for receive and transmit paths, and the present invention is not limited to any particular number/type of processors. Buffers  111 A and  111 B are used to store information in receive and transmit paths, respectively. 
   Beside dedicated processors on the receive and transmit path, adapter  106  also includes processor  106 A, which may be a reduced instruction set computer (“RISC”) for performing various functions in adapter  106 . 
   Adapter  106  also includes fibre channel interface (also referred to as fibre channel protocol manager “FPM”)  113  that includes modules  113 A and  113 B in receive and transmit paths, respectively (shown as “FC RCV” and “FC XMT”). Modules  113 A and  113 B allow data to move to/from storage systems and are described below in detail. Frames  146 A are received from a fibre channel network, while frames  146 B are transmitted to the fibre channel network. 
   Adapter  106  is also coupled to external memory (not shown) and local memory interface  122 . Memory interface  122  is provided for managing local memory. Local DMA module  137 A is used for gaining access to a channel to move data from local memory ( 108 / 110 ). Adapter  106  also includes a serial/de-serializer (shown as “XGXS/SERDES”)  136  for converting data from 10-bit to 8-bit format and vice-versa. 
   Adapter  106  also includes request queue DMA channel ( 0 )  130 , response queue ( 0 ) DMA channel  131 , response queue ( 1 )  132 A, and request queue ( 1 ) DMA channel  132 ; and a command DMA channel  133  for managing command information. DMA channels are coupled to an arbiter module (not shown) that receives requests and grants access to a certain channel. 
   Both receive and transmit paths have DMA modules “RCV DATA DMA”  129 A and  129 B and “XMT DATA DMA”  135  that are used to gain access to a channel for data transfer in the receive/transmit paths. Transmit path also has a scheduler  134  that is coupled to processor  112  and schedules transmit operations. 
   PCI master interface  107 A and PCI target interface  107 B are both coupled to a PCI-Express Core logic  137  (may also be referred to as “logic  137 ”). Interface  107 A and  107 B includes an arbitration module that processes DMA access to plural DMA channels. 
     FIG. 2A  shows a block diagram with certain components of logic  137  that are used for testing HBA  106 . Logic  137  includes a serial/de-serializer  201  and a PCI-Express receive channel (“PCS”)  202  that are described below in detail. 
   Testing module  106 B sends random serial data via SERDES  106 C and serial interface  136 A. SERDES  201  receives the incoming data stream and passes the data stream to PCS  202 . 
     FIG. 2B  shows a block diagram of PCS  202  with a comma alignment block  202 A, a buffer  202 B and a decoder  202 C. Typically SERDES  201  sends 10-bit data that is received by PCS  202 . A comma character may be used to determine where data boundary begins (or ends). The incoming bits from SERDES  201  are synchronized with respect to the comma character. 
     FIG. 2D  shows an example of how data is sent from SERDES  201 . Three characters  1 ,  2  and  3  are shown in  FIG. 2D . The 20 bits from SERDES  201  may have bits from all the three characters. Hence, it is important to detect a comma character, which allows synchronization of comma characters with words. 
   Comma alignment block  202 A includes a state machine (not shown) that determines where a comma character is located in a bit stream received from SERDES  201 . Based on the location of the comma character, the incoming bits are re-aligned and then stored in a buffer  202 B. Decoder  202 C decodes 10-bit data to 8-bit data and the decoded 8-bit data is sent to other components in HBA  106  for processing. 
   To ensure that a comma character is detected accurately, and proper bit alignment takes place in PCS  202 , testing module  106 B uses a software module that is shown in  FIG. 2C . The software module includes a data presenter module  206 , data producer module  207  and a bit offset change module  208 . 
   Data presenter module  206  presents 20-bit blocks of data that is sent to SERDES  106 C. Data presenter module  206  is unaware of data formatting. Data presenter module  206  uses buffer  210  to present the data. Buffer  210  may be a circular buffer. The size of buffer  210  depends on the type of interface that is used. For example, if a 20-bit interface is used on the receiver side (i.e. PCS  202  side) then a buffer that can accommodate the 20-bit is used by data presenter module  206 . It is noteworthy that buffer  210  may include more than one buffer, as shown in  FIG. 4 . 
   Data Producer module  207  is a software thread that is aware of the data format used by the receiver (PCS  202  in HBA  106 ). Data producer module  207  may choose to create 8-bit data and then convert it into 10-bits. Data in 10-bit format is stored in buffer  210  from where data presenter module  206  sends the data to SERDES  201  via SERDES  106 C. 
   Data producer module  207  schedules (or inserts) sufficient number of comma characters to allow PCS  202  to perform periodic alignment operations (using comma alignment block  202 A). Although data producer module  207  inserts (or commands insertion of) comma characters, it is unaware of any synchronization or loss of synchronization that may occur at PCS  202 . 
   Buffer  210  is also useful, if HBA  106  (via PCS  202 ) wants to examine historical data that is sent by testing module  106 B. This history allows for latency between the time testing module  106 B (the transmitter) has sent data and the time HBA  106  receives data, converts it to parallel data and converts the 10-bit data into 8-bit data. 
   Bit offset change module  208  is unaware of any of the data that is being operated on by data producer module  207  and/or data presenter module  206 . Bit offset change module  208  changes the bit offset that is used by data presenter module  206 . This sends random data from testing module  106 B to HBA  106 . This will cause a loss of alignment by the receiver (PCS  202 ) and force comma alignment block  202 A to perform character re-alignment after the loss of alignment. HBA  106  in general and PCS  202  in particular are tested to see if the character alignment is performed properly after the bit offset. 
   Standard testing software/hardware may used in conjunction with testing module  106 B to track/monitor how HBA  106  performs re-alignment after it receives random data via SERDES  106 C, as described above. 
     FIG. 3  shows a process flow diagram for inducing data alignment errors and testing HBA  106  under the induced errors, according to one aspect of the present invention. 
   Turning in detail to  FIG. 3 , in step S 300 , data producer module  207  selects the data that is to be sent to HBA  106 . In one aspect, the data may be in 8-bit format. 
   In step S 302 , the 8-bit data is converted into a 10-bit format. In step S 304 , the data is placed in buffer  210 . In step S 306 , a 20-bit block of data is created in buffer  210  and in step S 308 , a bit offset is set by bit offset change module  208 . Thereafter, data is sent to PCS  202  in step S 310 . 
     FIG. 4  shows an example of how the bit-offset are used to send data from via SERDES  106 C. Buffer  1  and buffer  2  are a part of buffer  210 . The bit-offset is set at 5 and data presenter module  206  then presents the data to SERDES  106 C and then to PCS  202  via SERDES  201 . 
   In one aspect of the present invention, character/word synchronization is lost in PCS  202  and this causes a stream of invalid characters to be sent. This forces state machines (not shown) in HBA  106  to be tested. Hence, HBA  106 &#39;s character alignment function can be tested from any platform using test module  106 B. 
   Although the present invention has been described with reference to specific embodiments, these embodiments are illustrative only and not limiting. Many other applications and embodiments of the present invention will be apparent in light of this disclosure and the following claims.