Abstract:
An apparatus and method for processing a differential-type signal transmitted through a pair of data lines. First, a voltage range defined by an upper reference and a lower reference and a logic pattern are provided. Then, the signal is tested to generate logic data responsive to the voltage range. Next, the logic data are utilized to compare with the logic pattern so as to generate a test result when the signal enters a transition cycle.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention generally relates to testing methodology. More particular, the present invention relates to an apparatus for testing the crossover voltage of differential signals and its method. 
     2. Description of the Related Art 
     Traditional serial bus connections like RS-232C has at least three shortcomings: transmission speed is slow, use is complicated, and connection is limited to only a few ports. Ever since the introduction of the Universal Serial Bus (referred to as “USB” hereafter) in 1996, USB has been gladly received as the newly established standard for the next generation serial bus connections with new functionality like plug &amp; play, 12 Mbits/sec high speed transmission, support for up to 127 peripheral devices, fault-proof connector design, and low cost, etc. At present, there are a number of computer peripheral devices supporting USB standard on the market such as monitors, keyboards, mouse&#39;s, joysticks, scanners, printers, and digital cameras, etc. 
     The USB bus employs a line pair for transmitting differential-type data signals. Referring to FIG. 1, the voltage waveform on data pins DP and DN of the USB bus is shown schematically, where V H  and V L  denote a logic-high level and a logic-low level, respectively. During a transition cycle, that is, when the voltage of the data pin DP transits from the logic-high level V H  to the logic-low level V L  and the voltage of the data pin DN transits from the logic-low level V L  to the logic-high level V H , or vice versa, the voltage signals intersect at a point A. Usually, the voltage at the crossover point A is denominated as a crossover voltage V crs , where the timing placement of the crossover point A is represented by T crs . If the USB bus runs at a lower transmission rate, such as 1.5 Mbits/sec, the transition cycle is about 75˜300 ns; if the USB bus operates at a higher transmission rate, such as 12 Mbits/sec, the transition cycle will be in the range of about 4˜20 ns. 
     The crossover voltage V crs  is an important parameter for evaluating USB output signals. As an example, assuming that the logic-high level V H  is set to 3.3V and the logic-low level V L  set to 0V, the crossover voltage V crs  should be specified within the range of about 1.3˜2.0V. 
     Referring to FIG. 2, a conventional apparatus for testing the crossover voltage V crs  is schematically illustrated. As shown in the drawing, the conventional testing apparatus includes a comparator  20  configured with two input terminals connected to the data pins DP and DN, respectively. At the crossover point A, the comparator  20  generates an output signal  22  with a abrupt transition edge to trigger a voltage sampler  24 . The voltage sampler  24 , responsive to the abrupt transition edge, samples the voltages of the data pins DP and DN and generates the sampled value at an output terminal  26 . The sampled voltage is then read by a parameter measurement unit (not shown in the drawing) of a tester. 
     Though the operation speed of the comparator  20  and the voltage sampler  24  is so restrictive that the sampled voltage is more or less deviated from the crossover voltage V crs , the sampled voltage can approximate the crossover voltage V crs  quite well. However, the use of the comparator  20  and the voltage sampler  24  require modification of the circuitry on a load board connected between a unit-under-test (UUT) and the tester. The expense required to manufacture a resigned load board is high (up to thousands of U.S. dollars); therefore, it is not a cost-effective approach. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide an apparatus and a method for testing the crossover voltage of differential signals without modifying the circuitry on a load board connected between a UUT and a tester. 
     To attain the above-identified object, the present invention provides an apparatus for processing a signal transmitted through a pair of data lines. The apparatus has two tester channels, each of which corresponds to one of the data lines and comprises a first comparator and a second comparator and a logic circuit. The first comparator is configured with a first inverting input for receiving an upper reference and a first non-inverting input for connecting with the corresponding data line. The second comparator is configured with a second inverting input for connecting with the corresponding data line and a second non-inverting input for receiving a lower reference. The logic circuit is electrically coupled to the first comparator and the second comparator. When the signal enters a transition cycle, the first comparator and the second comparator generate logic data responsive to the upper reference and the lower reference. Then, the logic circuit compares the logic data with a logic pattern and generates a test result, accordingly. 
     In addition, the present invention provides a method for processing a signal transmitted through a pair of data lines. First, a voltage range defined by an upper reference and a lower reference and a logic patter are provided. Then, the signal is tested to generate logic data responsive to the voltage range. Next, the logic data are utilized to compare with the logic pattern so as to generate a test result when the signal enters a transition cycle. 
    
    
     BRIEF DESCRIPTION OF DRAWINGS 
     The following detailed description, given by way of examples and not intended to limit the invention to the embodiments described herein, will best be understood in conjunction with the accompanying drawings, in which: 
     FIG. 1 schematically illustrates the voltage waveform on data pins DP and DN of a USB bus; 
     FIG. 2 schematically illustrates a conventional apparatus for testing the crossover voltage V crs ; 
     FIG. 3 schematically depicts a block diagram of a conventional test system; 
     FIG. 4 schematically depicts a block diagram of an apparatus for testing the crossover voltage of differential signals in accordance with one preferred embodiment of the present invention; and 
     FIG. 5 illustrates the waveform of data lines DP, DN and a select signal STROBE. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIG. 3, a block diagram of a conventional test system is schematically illustrated. In the drawing, a tester  30  is used to test a UUT  32 , such as a USB bus in the following embodiment, according to the required program loaded therein. Moreover, the tester  30  is electrically coupled to the UUT  32  by a load board  34 , which serves as an hardware interface between the tester  30  and the UUT  32 . 
     Because the conventional testing apparatus of FIG. 2 utilizes the comparator  20  and the voltage sampler  24 , the load board  34  coupled between the tester  30  and the UUT  32  must be modified, thereby imposing a cost burden on testing. Therefore, the present invention provides an apparatus and a method for testing the crossover voltage of differential signals which makes some modifications at end of the tester  30 , but none to the load board  34 , thereby saving the expense for redesigning the load board  34 . 
     As shown in FIG. 4, a block diagram of an apparatus for testing the crossover voltage of differential signals in accordance with one preferred embodiment of the present invention is schematically illustrated. The testing apparatus of the present invention can be applied to those UUTs utilizing differential signals, such as USB, IEEE-1394, or Ethernet. In the following, the USB bus is exemplified, but not intended to limit the scope of the present invention to the embodiments described below. In particular, the testing apparatus of FIG. 4 is established by merely modifying the test program loaded into the tester  30 . 
     As shown in FIG. 4, the testing apparatus is provided with two tester channels  40  and  42  connected to the data pins DP and DN, respectively. The tester channel  40  comprises two comparators  401  and  402 , and a pass/fail logic circuit  405 . The comparator  401  is configured with an inverting input terminal connected to an upper reference voltage V OH , while the comparator  402  is configured with a non-inverting input terminal connected to a lower reference voltage V OL . When the crossover voltage V crs  of the USB bus is specified within the range of 1.3˜2.0V, the upper reference voltage V OH  can be set to 2.0V and the lower reference voltage V OL  can be set to 1.3V. In FIG. 4, the non-inverting input terminal of the comparator  401  and the inverting input terminal of the comparator  402  are tied together to connect with the data pin DP. The comparators  401  and  402  are provided with respective output terminals  403  and  404  to send out logic data for the pass/fail logic circuit  405 . The pass/fail logic circuit  405  has an input terminal TP 1  for receiving test patterns to be compared with the logic data at the output terminals  403  and  404 , which are generated by the comparators  401  and  402 , respectively. If the logic data correspond to the test pattern, the pass/fail logic circuit  405  generates a “PASS” signal, or otherwise a “FAIL” signal, from an output terminal R 1 . The corresponding relation among the voltage V DP  at the data pin DP, the logic states at the outputs  403  and  404  of the comparators  401  and  402 , and the test pattern at the input TP 1  are listed in the following Table 1. 
     
       
         
               
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 VDP 
                 403 
                 404 
                 TP1 
               
               
                   
                   
               
             
             
               
                   
                 V DP  &gt; V OH  &gt; V OL   
                 H 
                 L 
                 H 
               
               
                   
                 V OH  &gt; V DP  &gt; V OL   
                 L 
                 L 
                 Z 
               
               
                   
                 V OH  &gt; V OL  &gt; V DP   
                 L 
                 H 
                 L 
               
               
                   
                   
               
             
          
         
       
     
     H denotes the logic-high state, L the logic-low state, and Z a high impedance state. 
     In addition, the tester channel  42  comprises two comparators  421  and  422 , and a pass/fail logic circuit  425 . The comparator  421  is configured with an inverting input terminal connected to the upper reference voltage V OH , while the comparator  422  is configured with a non-inverting input terminal connected to the lower reference voltage V OL . When the crossover voltage V crs  of the USB bus is specified within the range of 1.3˜2.0V, the upper reference voltage V OH  can be set to 2.0V and the lower reference voltage V OL  can be set to 1.3V. In FIG. 4, the non-inverting input terminal of the comparator  421  and the inverting input terminal of the comparator  422  are tied together and connected to the data pin DN. The comparators  421  and  422  are provided with respective output terminals  423  and  424  to send out the logic data for the pass/fail logic circuit  425 . The pass/fail logic circuit  425  has an input terminal TP 2  for receiving test patterns to be compared with the logic data at the output terminals  423  and  424 , which are generated by the comparators  421  and  422 , respectively. If the logic data correspond to the test pattern, the pass/fail logic circuit  425  generates a “PASS” signal, or otherwise a “FAIL” signal, at an output terminal R 2 . The corresponding relations among the voltage V DP  at the data pin DN, the logic states at the outputs  423  and  424  of the comparators  421  and  422 , and the test pattern at the input TP 2  are listed in the following Table 2. 
     
       
         
               
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 VDP 
                 423 
                 424 
                 TP2 
               
               
                   
                   
               
             
             
               
                   
                 V DP  &gt; V OH  &gt; V OL   
                 H 
                 L 
                 H 
               
               
                   
                 V OH  &gt; V DP  &gt; V OL   
                 L 
                 L 
                 Z 
               
               
                   
                 V OH  &gt; V OL  &gt; V DP   
                 L 
                 H 
                 L 
               
               
                   
                   
               
             
          
         
       
     
     H denotes the logic-high state, L the logic-low state, and Z the high impedance state. 
     Moreover, both the pass-fail logic circuits  405  and  425  are controlled by a select signal STROBE. 
     Referring to FIG. 5, the voltage waveform of the data lines DP, DN and select signal STROBE is shown as an example for description. The detailed operation of the testing apparatus of FIG. 4 will be described in conjunction with FIG.  5 . For simplicity and convenience, the timeline is divided into seven cycles 1˜7, wherein the voltage of the data pin DP transits from the logic-high level V H  to the logic-low level V L  and the voltage of the data pin DN transits from the logic-low level V L  to the logic-high level V H  during the cycle  4 , that is, a transition cycle. 
     The corresponding relation between the test pattern at inputs TP 1  and TP 2  and the test results at the outputs R 1  and R 2  are listed in the following Table 3. 
     
       
         
               
               
               
               
               
             
           
               
                 TABLE 3 
               
               
                   
               
               
                 CYCLE 
                 TP1 
                 TP2 
                 R1 
                 R2 
               
               
                   
               
             
             
               
                 1 
                 H 
                 L 
                 P 
                 P 
               
               
                 2 
                 H 
                 L 
                 P 
                 P 
               
               
                 3 
                 H 
                 L 
                 P 
                 P 
               
               
                 4 
                 Z 
                 Z 
                 To be tested 
                 To be tested 
               
               
                 5 
                 L 
                 H 
                 P 
                 P 
               
               
                 6 
                 L 
                 H 
                 P 
                 P 
               
               
                 7 
                 L 
                 H 
                 P 
                 P 
               
               
                   
               
             
          
         
       
     
     P denotes the “PASS” signal generated from the output terminal R 1  or R 2 . 
     According to the present invention, in the transition cycle (cycle  4 ), the crossover voltage of the data pins DP and DN is to be tested. For to the other cycles, both the test output terminals R 1  and R 2  send out the “PASS” signals. As shown in Table 3, both the test patterns of input terminals TP 1  and TP 2  are set to high-impedance state Z in the cycle  4 . Therefore, in response to the select pulse STROBE, the data pins DP and DN are tested to determine whether their voltages are within the specified range, defined by the upper reference voltage V OH  and the lower reference voltage V OL  or not. 
     During the active period of the select pulse STROBE, if the voltages at the data pins DP and DN are within the voltage range defined by the V OH  and VOL? the test output terminals R 1  and R 2  send out the “PASS” signals. If any one voltage at the data pins DP or DN exceeds the voltage range defined by the V OH  and V OL , the corresponding output terminals R 1  or R 2  sends out the “FAIL” signal. 
     Furthermore, the timing of the select pulse STROBE can be generated by means of a linear searching method or a binary searching method. 
     Accordingly, the crossover voltage V crs  of the data pins DP and DN can be tested to determine whether it falls within the voltage range defined by the V OH  and V OL . Moreover, though V OH =2.0V and V OL =1.3V are exemplified as above, the voltage range can be narrowed by redefining V OH  and V OL , such as 1.6V and 1.7V in conjunction with the pulse timing of the select signal STROBE, respectively, so as to approximate crossover voltage V crs  more accurately. 
     Because the testing apparatus of the present invention is installed in the tester  30  of FIG. 3, the tester  30  can control the relays to establish the circuitry of FIG. 4 by merely modifying the test program loaded therein. Although the USB signals are exemplified in the aforementioned embodiment, the testing apparatus of the present invention can be also applied to those circuits employing differential signals, such as IEEE-1394, Ethernet, and so on. 
     While the invention has been described with reference to various illustrative embodiments, the description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those person skilled in the art upon reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as may fall within the scope of the invention defined by the following claims and their equivalents.