Abstract:
Disclosed is a testing apparatus, including: a base having opposite upper and lower surfaces, and a plurality of electrical circuits formed in the base, each of the electrical circuits extending from the upper surface to the lower surface and bending backwards to the upper surface such that two terminal ends of the electrical circuit are located on the upper surface. While in a testing, an element is disposed on the upper surface of the base such that testing probes are placed on the electrical contact spots of both the element and the upper surface of the base, thus without resorting to double sided testing that testing probes are placed on the upper and lower surfaces of the element as mentioned in the prior art. Hence, the testing apparatus and testing method can simplify the testing process and prevent the element from damage caused by mechanical stresses of the testing probes.

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
     This application claims under 35 U.S.C. §119 (a) the benefit of Taiwanese Application No. 101120432, filed Jun. 7, 2012, the entire contents of which is incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to testing apparatus and methods, and, more particularly, to an apparatus and method for testing stacked integrated circuit (IC) packaging structures. 
     2. Description of Related Art 
     3D IC chip stacking packaging technologies have been developed for integrating more electronic elements and functions in a limited area to meet the requirements of multi-function and miniaturization as demanded by electronic products. 
     3D IC chip stacking packaging technologies involve stacking and integrating a plurality of chips having different functions, characteristics or substrates through through-silicon via (TSV) technology, which is also referred to as 2.5D IC technology, on the other hand, the current 3D IC technologies individually make these different functional chips by the most appropriate fabrication processes and then integrate the chips with TSVs, to thereby shorten signal transmission distance and reduce conductive resistance and chip size. Therefore, the advantages of package scaling, high integration, high efficiency, low power consumption, and low cost can be realized to meet the miniaturization requirement of digital electronics. 
     To test a 3D IC (or 2.5D IC) chip structure, especially semiconductor elements having TSVs, is critical for mass production. Testing a semiconductor element generally includes a chip probe (CP) test before a packaging process and a final test (FT) after the packaging process. 
       FIGS. 1A and 1B  illustrate a chip probe test performed on an element  7 . The element  7  to be tested is a wafer substrate  9  having TSVs  90  formed therein and chips  8  bonded thereon. The element  7  is disposed on a testing apparatus  1 . The testing apparatus  1  has a base  10  and a lid  11 . The element  7  contacts both the base  10  and the lid  11  through compression pressure such that pogo pins  110  of the lid  11  are in electrical connection with electrical contacts  91  on an upper side of the wafer substrate  9  to form an electrical circuit loop L 1 , and electrical circuits  100  and conductive bumps  101  of the base  10  are in electrical connection with electrical contacts  92  on a lower side of the wafer substrate  9  to form an electrical circuit loop L 2 , thereby enabling a double-side (upper and lower sides) probe test. 
     However, since a wafer substrate  9  with TSVs is 10 μm to 180 μm thick only, the wafer substrate  9  is easy to crack when the pogo pins  110  come into contact with the wafer substrate  9  downwards. The contact pressure in fact easily do damage to the wafer substrate  9 . 
     Furthermore, the double-side electrical circuit loops L 1 , L 2  complicate the electrical circuit layout. The structure only enables to perform a CP test before the packaging process and does not do an FT test after the packaging process. Therefore, the present technology cannot have a testing apparatus that provides both CP and FT tests for an element having TSVs to be tested. 
     In addition, the contact pressure can cause inaccurate alignment in the electrical circuit loops L 1 , L 2 . 
     Therefore, it is dispensable that there is a need to invent a testing apparatus and method to overcome the above-described disadvantage. 
     SUMMARY OF THE INVENTION 
     In view of the above-described disadvantage, the present invention provides a 3D IC wafer level testing apparatus that allows testing probes to be disposed on a single side of both the element to be tested and the base of testing apparatus, thereby eliminating the need to dispose testing probes on both sides of the element to be tested as described in the prior art to simplify the testing process and electrical circuit design. Furthermore, the testing apparatus is capable of testing ultra-thin dies having TSVs. 
     Accordingly, the present invention provides a testing apparatus, which comprises: at least a base having opposite first and second surfaces; and a plurality of electrical circuits formed in the base, each of the electrical circuits extending from the first surface to the second surface and bending backwards to the first surface such that two terminal ends of each of the electrical circuits are located on the first surface. 
     The present invention further states a testing method, which comprises: providing a testing apparatus comprising at least a base and a plurality of electrical circuits formed in the base, wherein the base has opposite first and second surfaces and each of the electrical circuits extends from the first surface to the second surface and bends backwards to the first surface such that two terminal ends of each of the electrical circuits are located on the first surface; and disposing at least an element to be tested on the base and electrically connecting the element and the electrical circuits for performing a test. 
     In the above-described apparatus and method, a testing placement area can be formed on the first surface of the base for the element to be tested to be placed thereon, and one of the two terminal ends of each of the electrical circuits is located inside the testing placement area and the other one is located at an outer periphery of the testing placement area. 
     In the above-described apparatus and method, a recess can be formed on the first surface of the base for loading the element to be tested. The recess can be formed with chamfers along upper corner edges thereof for disposing the element to be tested in the recess. 
     In the above-described apparatus and method, an elastic part can be formed on the first surface of the base for holding the element to be tested. 
     In the above-described apparatus and method, a positioning structure can be formed on the first surface of the base for positioning the element to be tested. The positioning structure can be a through hole in communication with the first and second surfaces. The testing apparatus can further comprise a vacuum system in communication with the through hole for fixing the element to be tested by vacuum suction. 
     In the above-described apparatus and method, the two terminal ends of each of the electrical circuits can serve as electrical testing contact spots. 
     According to the present invention, the electrical circuit layout of the testing apparatus allows an ultra-thin chip to be tested by a single-side electrical test, thereby simplifying the testing process and enabling both CP and FT tests to be performed. 
     Further, the elastic part, the through hole and the vacuum system can help prevent the element to be tested from damage. 
     Furthermore, the chamfers of the recess and the vacuum structure enable the element to be tested to be accurately positioned on the base without any deviation. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIGS. 1A and 1B  are cross sectional side views illustrating a conventional testing apparatus and method; 
         FIG. 2  is a cross sectional side view illustrating a testing apparatus according to a first embodiment of the present invention; 
         FIGS. 3A to 3C  are views illustrating a testing apparatus and method according to the first embodiment of the present invention; 
         FIGS. 4A and 4B  are cross sectional side views illustrating a testing apparatus and method according to a second embodiment of the present invention; 
         FIG. 5A  is a schematic perspective view illustrating an embodiment of the element to be tested according to the present invention; and 
         FIG. 5B  is a cross-sectional view illustrating another embodiment of the element to be tested according to the present invention. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those with ordinary skill in the art after reading this specification. 
     It should be noted that all the drawings are not intended to limit the present invention. Various modification and variations can be made without departing from the spirit of the present invention. Further, terms such as “upper”, “lower”, “first”, “second”, “a” etc. are merely for illustrative purpose and should not be construed to limit the scope of the present invention. 
       FIG. 2  is a cross sectional side view of a testing apparatus  2  according to a first embodiment of the present invention. Referring to  FIG. 2 , the testing apparatus  2  has a base  20  and a plurality of electrical circuits  21  formed on surfaces of the base  20 . 
     The base  20  has a first surface  20   a  and a second surface  20   b  opposite to the first surface  20   a,  and a testing placement area A is formed on the first surface  20   a  of the base  20 . In an embodiment, the testing placement area A has a recess  200 . The recess  20  is formed with chamfers  201  along upper corner edges thereof. 
     In an embodiment, an elastic part  22  and a positioning structure are formed on a bottom surface of the recess  200 . The elastic part  22  can be made of, but not limited to, rubber or latex. The positioning structure is a plurality of through holes  23  in communication with the first and second surfaces  20   a  and  20   b.  The testing apparatus  2  further has a vacuum system (not shown) in communication with the through holes  23  for fixing an element to be tested in the recess  200  by vacuum suction. But it should be noted that the fixing structure and method for fixing the element to be tested are not limited thereto. 
     The base  20  can be formed by molding or stamping. According to the electrical test requirement of the element to be tested, the base  20  can be made of Vespel (Dupont), PEEK, PBI, Kapton (Dupont), PTFE, POM, Nylon and so on. Then, the recess  200  can be formed by mechanical processing or etching. The through holes  23  can be formed by mechanical drilling before the elastic part  22  is attached to the bottom surface of the recess  200 . 
     Each of the electrical circuits  21  extends from the first surface  20   a  to the second surface  20   b  and bends backwards to the first surface  20   a  such that two terminal ends (a first end  21   a  and a second end  21   b ) of the electrical circuit  21  are located on the first surface  20   a.    
     In an embodiment, each of the electrical circuits  21  forms a J-shape in side view. In other embodiments, each of the electrical circuits  21  can have a U-shape, an arc shape or the like. 
     The electrical circuits  21  can be formed by directly attaching copper foils, copper pillars or other conductive materials on a side surface of the base  20 . Alternatively, a thermosetting resin can serve as an insulating substrate (not shown) such that a liquid insulating material is formed on the substrate by coating and a plurality of layers of conductive traces are formed on the insulating substrate through laser drilling and electroless plating processes to thereby form the electrical circuits  21 . Then, the insulating substrate with the electrical circuits  21  is attached to the side surface of the base  20 . The insulating substrate can be a printed circuit board, a silicon wafer, a glass wafer or PEI. 
     In other embodiments, the electrical circuits  21  can be embedded in the base  20 . It should be noted that there is no special limitation on the method for forming the electrical circuits  21 , as long as each of the electrical circuits  21  has two terminal ends located on the first surface  20   a.    
     The first end  21   a  and the second end  21   b  of each of the electrical circuits  21  serve as electrical testing contacts. The first ends  21   a  are located inside the recess  200  and the second ends  21   b  are located at an outer periphery of the recess  200 . Further, conductive elements  24  such as conductive bumps  24   b  or pins  24   a  are formed on the first ends  24   a  and the second ends  24   b,  respectively. 
       FIGS. 3A and 3C  illustrate a testing method using the testing apparatus  2 . 
     Referring to  FIG. 3A , a plurality of testing apparatuses  2  are disposed on a carrier  3 . Although nine testing apparatuses are shown in the drawing, it should be noted that the number of the testing apparatuses  2  can vary according to the size of dies and other requirements. For example, the number of the testing apparatuses  2  ranges from 4 to 9,192. 
     In an embodiment, the carrier  3  corresponds in shape and size to an 8-inch, 12-inch or 18-inch wafer, and can be directly loaded into a general wafer prober (not shown) or a film frame probing handler (not shown) after singulation. Further, the carrier  3  can be loaded to a die pick-and-place machine to automatically place elements to be tested in the testing apparatus  2 . 
     Referring to  FIG. 3B , an element  7  to be tested is fixed on the bottom surface of the recess  200  of the base  20  by vacuum suction and electrically connected to the first ends  21   a  of the electrical circuits  21  (i.e., the conductive pins  24   a ). 
     In an embodiment, the element  7  to be tested can be a 2.5D IC, a 3D IC or other electronic element to be tested and have a die size or a wafer size. For example, the element  7  to be tested includes a wafer substrate  4 , i.e., an interposer having silicon vias  40  and a plurality of chips  5  bonded thereto. The wafer substrate  4  has a plurality of electrical contacts  41  and  42  formed on upper and lower sides thereof, and the electrical contacts  42  on the lower sides of the wafer substrate  4  electrically connect the first ends  21   a  of the electrical circuits  21  (i.e., the conductive pins  24   a ). The chips  5  can be application specific integrated circuit (ASIC) chips or dynamic random-access memory (DRAM) chips. 
     The chamfers  201  of the recess  200  can slide the element  7  to be tested to align with the base  20 . 
     The elastic part  22  prevents the element  7  to be tested from collision damage between the base  20  and the element  7  to be tested. 
     Further, by the through holes  23  and the vacuum system, the element  7  to be tested can be fixed on the base  20  without any deviation. Also, the element  7  can be conveniently picked and placed. 
     Referring to  FIG. 3C , after the element  7  to be tested is accurately fixed to the testing apparatus  2 , the vertical displacement of a wafer prober is accurately controlled to ensure a certain contact pressure between the element  7  to be tested, the testing apparatus  2  and a wafer tester  6  of the wafer prober. As such, testing probes  60  of the wafer tester  6  are in electrical connection with the electrical contacts  41  on the upper side of the wafer substrate  4  and the second ends  21   b  of the electrical circuits  21  (i.e., the conductive bumps  24   b ) for transmitting and receiving electrical signals of the element  7  to be tested. 
     According to the present invention, although the testing probes  60  are only disposed on the first surface  20   a  of the base  20 , the layout of the electrical circuits  21  allows the testing probes  60  to test the electrical contacts  41  and  42  on both the upper and lower sides of the wafer substrate  4 , thus eliminating the need to dispose testing probes on the second surface  20   b  of the base  20  or the first ends  21   a  of the electrical circuits  21 . As such, the present invention can be used to test ultra-thin dies. Further, the testing process is effectively simplified. 
       FIGS. 4A and 4B  illustrate a testing apparatus  2 ′ according to a second embodiment of the present invention. The second embodiment differs from the first embodiment in the structure of the recess. 
     If an element  7 ′ to be tested has a non-planar surface and an asymmetric structure, that is, a plurality of chips  5   a  and  5   b  bonded to a wafer substrate  4  having different heights, the first surface  20   a  of the base  20  can be formed with recesses  200   a  and  200   b  having different heights corresponding to the chips  5   a  and  5   b.    
     Referring to  FIGS. 5A and 5B , the testing apparatus and method of the present invention can be used to test various kinds of elements  7   a  and  7   b.  Referring to  FIG. 5A , the element  7   a  to be tested includes a wafer substrate  4  and a plurality of logic chips, RF chips, memory chips, digital or analog chips and so on disposed on the wafer substrate  4 . Alternatively, referring to  FIG. 5B , the element  7   b  to be tested includes a wafer substrate  4 , at least a chip  70  and a plurality of stacked memory chips  71  and  71 ′ disposed on the wafer substrate  4 . 
     To test the element  7   b,  the testing apparatus  2  of the first embodiment can be used before the memory chip  71 ′ is stacked on the memory chip  71  to perform a planar test. If it is determined that the element functions normally, the memory chip  71 ′ is stacked on the memory chip  71  and the testing apparatus  2 ′ of the second embodiment is used to perform a non-planar test to easily determine the yield of the chips  71 ′ and  71 . 
     Therefore, the electrical circuit layout of the testing apparatus of the present invention allows an ultra-thin chip to be tested by a single-side electrical test, thereby simplifying the testing process. 
     In summary, the elastic part, the through holes and the vacuum system help prevent the element to be tested from damage as a result of a testing. 
     Furthermore, the chamfers of the recess enable the element to be tested to be accurately positioned on the base. 
     The above descriptions of the detailed embodiments are only to illustrate the preferred implementation according to the present invention, and it is not to limit the scope of the present invention. Accordingly, all modifications and variations completed by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims.