Abstract:
An antenna design of compact dimensions is provided by incorporating the antenna structure into an integrated circuit or small circuit module. A radiation pattern adjustment mechanism permits dynamic, real-time adjustment of the antenna pattern in response to motion, repositioning, handovers, or other changing conditions. Pursuant to one preferred embodiment of the invention, the antenna includes a plurality of substantially conductive elements embedded into or formed on the integrated circuit. At least one of the conductive elements is coupled to a radiation pattern adjustment mechanism in the form of a switching diode or relay. The antenna elements are arranged in a manner so as to provide parasitic interaction.

Description:
CROSS REFERENCE TO RELATED APPLICATION(S) 
   This application claims priority from U.S. Provisional Application No. 60/517,692 filed on Nov. 5, 2003, which is incorporated by reference as if fully set forth. 

   FIELD OF THE INVENTION 
   The present invention relates generally to antennas and, more specifically, to antenna designs that are embedded within integrated circuits. 
   BACKGROUND 
   Handheld wireless communication devices of compact dimensions are often preferred, so as to provide users with a measure of convenience, portability, unobtrusiveness, and ease of maneuverability. In furtherance of these objectives, substantial efforts have been directed towards reducing the spatial volume occupied by semiconductor chips, resistors, capacitors, and circuit substrates. Nonetheless, the amount of space required for an antenna covering a specified frequency range has remained relatively constant. For many practical applications, antenna designs occupy an undesirably large area or volume. 
   An antenna is comprised of one or more elements, which for the purposes of this description can include any combination of active and parasitic radiators, reflectors and directors. Antenna elements also include loading devices and other components providing signal propagation capabilities for transmission and reception. 
   In addition to size, another shortcoming of existing antenna designs is that they are fixedly mounted to the handheld wireless communication device, yet no mechanism is provided for changing the radiation pattern of the antenna, such as in response to movement of the communication device. Accordingly, it is desirable to have an antenna of compact dimensions that includes a radiation pattern adjustment mechanism. 
   One area of growing interest for wireless communications is the use of variable input (VI) arrangements for tracking multiple signals, for example, those coming from different satellites. Typically, variable input communications are conducted using a plurality of receiving antenna elements. One drawback to widespread application is having multiple antenna elements in small receive only devices such as satellite radios, digital video or digital audio systems. It would be desirable to provide such multiple antenna elements in a small device. 
   SUMMARY 
   An antenna design of compact dimensions is provided by incorporating the antenna structure into an integrated circuit or small scale packaged circuit. A radiation pattern adjustment mechanism permits dynamic, real-time adjustment of the antenna pattern in response to motion, repositioning, handovers, or other changing conditions. Pursuant to one preferred embodiment of the invention, the antenna includes a plurality of substantially conductive elements embedded into or formed on the integrated circuit. At least one of the conductive elements is coupled to a radiation pattern adjustment mechanism in the form of a switching diode or relay. The antenna elements are arranged in a manner so as to provide parasitic interaction. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a diagrammatic representation of a semiconductor chip that includes an antenna farm. 
       FIG. 2  is a diagrammatic representation of a semiconductor chip that includes an antenna pattern adjustment mechanism for adjusting the radiation pattern of the antenna farm of  FIG. 1 . 
       FIG. 3  is a diagrammatic representation of an arrangement in which multiple chips are juxtaposed in a face-to-back relationship in order to provide control of antenna elements. 
       FIG. 4  is a diagrammatic representation of an alternate arrangement in which multiple chips are juxtaposed in a face-to-back relationship in order to provide control of antenna elements. 
       FIG. 5  is a diagrammatic representation of an arrangement in which multiple chips are juxtaposed in a facing relationship in order to provide control of antenna elements. 
       FIG. 6  is a diagrammatic representation of an alternate arrangement, in which multiple chips are positioned in a front-to-back relationship, and connected with a membrane. 
       FIG. 7  is a diagrammatic representation of a semiconductor chip that includes a switching array and logic circuitry. 
       FIG. 8  is a diagrammatic representation of a semiconductor chip that includes an antenna farm controlled by the semiconductor chip of  FIG. 7 . 
       FIG. 9  is a cross-sectional view showing three separate semiconductor chips in a package. 
       FIG. 10  is a cross-sectional view of a configuration of an assembly using three chips provided with an alternate connection arrangement. 
       FIG. 11  is a diagrammatic representation of an arrangement in which a semiconductor chip includes an antenna farm connected to antenna elements external to the semiconductor chip. 
       FIG. 12  is a diagram showing a wireless transmit/receive unit (WTRU) using the inventive antenna configuration. 
       FIG. 13  is a diagram showing a configuration in which multiple ICs provide multiple input multiple output (MIMO) communications. 
       FIG. 14  is a diagram showing a configuration in which ICs are mounted on a printed circuit board having an antenna. 
       FIG. 15  is a diagram showing an exemplary use of the invention used in a variable input (VI) receiver. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1  is a diagrammatic representation of a semiconductor chip assembly  11  that includes an antenna farm  12 . The semiconductor chip assembly includes a first semiconductor chip comprising a substrate having a front surface  13 , a rear surface (not shown in  FIG. 1 ) with an interconnection substrate which includes conductive terminals or contact pads  15 , also located on the front surface  13 . The substrate of the first semiconductor chip contains a plurality of antenna elements  16  which, collectively, may be referred to as the “antenna farm”  12 . The antenna elements  16  may be fabricated in any convenient form, such as by plating, deposition of conductive materials or forming degenerate semiconductor areas on the surface of the wafer. Control logic circuitry  17 , as well as other circuit elements may also be included on the chip assembly  11 . 
   Some implementations of the antenna farm  12  are more useful at higher frequencies, although the antenna farms  12  can be used with lower frequencies. To illustrate, GSM frequencies are typically in the 900 MHz and 1.9 GHz ranges. 3 G and UMTS frequencies are in the 1.9 GHz to 2.2 GHz range. PCS code division multiple access (CDMA) communications are transmitted at 1.9 GHz. Other bands go as high as 20 GHz, and consequently antenna elements packaged within an integrated circuit chip package are able to provide signal propagation functions for such communications. While an integrated circuit package is described, it is understood that the components may also be packaged in a small circuit module. It is also possible to provide a small circuit module which includes separately encapsulated integrated circuit chips within the small circuit module. 
   An alternate embodiment of the present invention includes the configuration of  FIG. 1 , but with a second semiconductor chip  21 , depicted in  FIG. 2 . In the example shown, the second semiconductor chip  21  comprises a substrate having a front surface  23 , a rear surface (not shown in  FIG. 2 ) and a plurality of contacts  25  on the front surface. The substrate of the second semiconductor chip contains a respective plurality of switches  26  and/or relays that are arranged in a manner so as to overlay with a corresponding plurality of elements in the antenna farm. The plurality of switches and/or relays  26  are collectively referred to as a “switch farm” or “switch array”  27 . 
   In one embodiment, the switches in the switch array generally correspond to antenna elements  16  in the antenna farm  12 , so that the switches  26  are able to control respective antenna elements  16 . One advantage of providing a separate switch array is that this enables fabrication of the switch elements without integrating them into the fabrication process for producing the integrated circuit chip  11  with the logic circuitry. This also facilitates producing the switch array in a manner which provides improved radio frequency (RF) isolation of the switching elements. In this manner, control of the switching can be effected with logic circuitry, while the actual switching can be effected with circuits which provide good RF switching characteristics. Antenna loading elements may be located on either chip, according to configuration. For example, while inductive loading elements are convenient to manufacture with other antenna elements  16 , capacitive loading elements may be convenient to manufacture either as part of the antenna farm  12  or on the switch array  27 . 
   In one embodiment to enhance cooling of the two chips  11 ,  21 , the chip producing less heat is provided a heat sinking function for the other chip to enhance cooling. 
     FIG. 3  is a diagrammatic representation of an arrangement in which the first and second chips  11 ,  21  are positioned in a package  31  and are juxtaposed in a face-to-back relationship in order to provide control of antenna elements  16  ( FIG. 1 ). In one embodiment, the package  31  is a semiconductor integrated chip carrier package, of the type used to permit a semiconductor integrated circuit chip to be enclosed and communicate with external circuits. Typically, electrical connections are effected between a chip housed within the package and terminations on the package. The terminations extend external to the housing of the package. Such connections between the chip and the package may be made by a number of techniques, such as by leadwires, ball bonding, and other techniques. Leadwires can be used when connected to different ICs integrated in the same package for multichip module or system in package (SIP) configurations. The package such as package  31  containing one or more integrated circuit chips such as chips  11 ,  21  is a semiconductor integrated circuit device or IC. In the specific case of multiple chips packaged within a single package, the IC is a hybrid integrated circuit device or multichip module. 
   A web  34  is provided which includes a plurality of electrically conductive terminals. The web  34  is juxtaposed with the rear surface of the first semiconductor chip so that at least some of the conductive terminals will overlay the rear surface of the first semiconductor chip, and at least one of: (i) a contact on the first semiconductor chip, and (ii) a contact on the second semiconductor chip, is electrically connected to at least one of the conductive terminals. The web  34  includes conductive terminals or contacts  35  which mate with the contacts  15  on the front surface  13  of the first semiconductor chip  11 . The contacts  35  on web  34  are thereby in ohmic contact with the contact pads  15  of the front  13  of the first semiconductor chip. By combining the two chips  22 ,  21  in the package  31 , three layers of antenna, switch and switch control algorithms are provided. 
   While the chip  21  having the switch array  26  is depicted above the chip  11  having the logic circuitry, alternate arrangements for the relative positions of the two chips  11 ,  21  may be used. For example, chip  11  can be mounted over chip  21 , so that chip  21  is nearest the bottom of the package  31 . 
   Pursuant to a further embodiment, the radiation pattern of the antenna farm is adjusted by means of control logic. Such control logic, also referred to as “actuation logic”, may be utilized to provide any of a plurality of different effective antenna configurations. Alternately, these configurations are adaptively selected using one or more adaptive algorithms. Such algorithms may be based upon one or more received signal parameters, providing a real-time response to physical movement and reorientation of the antenna. The switches  26  can also be used to control the radiation pattern of the antenna and to control the effective lengths frequency response characteristics, and active or parasitic characteristics of the antenna elements  16 . 
   Pursuant to another embodiment, the actuation logic is integrated into the same substrate that includes the antenna farm. Alternatively, the actuation logic can be integrated into the substrate of the second semiconductor chip, distributed between them or on another element of the chip assembly. 
   Pursuant to additional embodiments, statistical switching of the antenna farm is provided to control the antenna radiation pattern. Such statistical switching can, but need not, be based upon carrier to interference for pilot signals, signal to noise ratio, transmit power, status of handover, or another type of structured algorithm. Actuation of the antenna farm may be linked with any element of the algorithm. For some applications, non-switched antenna operation may be employed, thereby providing a fixed radiation pattern. If the antenna farm is non-switched, certain elements of  FIGS. 1 and 2  may, but need not, be eliminated. In cases where the antenna farm is switched, learning and cognitive algorithms may be implemented for improved control of the antenna radiation pattern. 
   The structured algorithm can, but need not, be based on a sampling of signals received by the antenna farm in whole or in part. The structured algorithm may be based on a sampling of a combination of signals received by the antenna farm and signals received from another antenna system. The antenna farm radiation pattern may be linked with an addressing/numbering scheme, and/or a serial addressing/numbering scheme. 
   Optionally, at least one of an isolative, conductive, dielectric, or ferrite like material may be employed to improve RF decoupling between the first semiconductor chip (including the antenna farm) and the second semiconductor chip (including the switch array). Pursuant to another optional feature, one or more switches of the switch array may provide a programmable or fixed delay for diversity processing. The switches could, but need not, be programmed to retain a delay value from one time period to another, based on an adaptive learning scenario. The speed at which switching takes place can be controlled to provide switching rates that are greater than, equal to, or less than the chip rate. For example, diodes based on tunneling-assisted impact ionization can switch in a picoseconds timeframe, thereby permitting switching at speeds well in excess of the chip level. The diode can be a switching diode. PIN diode, phase shifter, ferroelectric material or other device able to provide a switching or similar control function. The configuration, described above in connection with  FIG. 2 , facilitates the use of such switching because it avoids requirements to fit the switching elements within the constraints of fabrication of the chip having the logic circuitry. 
   In other embodiments, a separate chip for switching and a separate chip for the antenna farm are provided, in addition to the chip containing the logic. Such a configuration adds an additional chip level, but potentially allows the chips for the different functions to be more economically produced. 
   In other embodiments, a first portion of the antenna farm may be utilized to support communication via a first air interface, whereas another portion of the antenna farm may be utilized to support communication via a second air interface. Alternately, a first portion of the antenna farm may be used to support transmission on one frequency band, and a second portion of the antenna farm used to support transmission on another frequency band. The antenna farm can also be combined with other fixed or variable/smart antennas. 
   Preferably, the antenna farm chip produces a low amount of heat, but is provided with a substantial heat sinking and heat radiating capacity. The antenna farm may be utilized to provide a thermal radiation sink for heat-generating components. 
     FIG. 4  is a diagrammatic representation of an alternate arrangement in which multiple chips are juxtaposed in a face-to-back relationship in order to provide control of antenna elements  16 . The first and second chips  11 ,  21  are positioned in the package  31  and are juxtaposed in a face-to-back relationship. A web  54  is provided which includes a plurality of electrically conductive terminals  55 – 58 . As is the case with web  34  in  FIG. 3 , web  54  is juxtaposed with the rear surface of the first semiconductor chip  21 . Web  54  extends around to the front of the second semiconductor chip  21 , which places the web  54  in a juxtaposed relationship with the face side  23  of the second semiconductor chip  21 . Terminals  55  and  56  are on a side of the web  54  which faces the top side  13  of semiconductor chip  11 , whereas terminals  57  and  58  are on an opposite side of the web  54 . Terminals  57  and  58  are juxtaposed with the top side  23  of the second semiconductor chip  21 . Accordingly, both chips  11 ,  21  are positioned in a face-up position. One particular advantage of this configuration is that it facilitates assembly with differently sized chips. 
   An interconnection substrate is provided which includes contact pads thereon. The conductive terminals of the web  54  are connected to the contact pads of the interconnection substrate. The interconnection substrate is adapted to connect the semiconductor chip assembly with other elements of a circuit, such that at least some of the conductive terminals will overlay the rear surface of the first semiconductor chip. 
   The configuration of  FIG. 4  is also useful in cases in which a first one of the chips  11 ,  21  provides logic circuitry controlling switches on a second one of the chips  11 ,  21 . The web  54  may have antenna elements formed thereon, as by plating. This permits the antenna elements to be placed within the package  31  on a layer separate from that of the logic circuitry and the switching array. 
     FIG. 5  is a diagram showing an arrangement in which a first semiconductor chip  71  is positioned above a second semiconductor chip  72 , but the first semiconductor chip  71  is inverted so that the first and second chips  71 ,  72  face each other. The chips  71 ,  72  have faces  73 ,  74  which are therefore juxtaposed. In order to provide this arrangement, connections must be made either directly between bondpads, or between bondpads on the respective chips and an intermediate connector. Contacts  76  such as raised areas or ball bonds are used to connect circuitry between the top and bottom chips  71 ,  72 . The top and bottom chips  71 ,  72  can be selected to be the chips containing the logic, switching array and logic according to design preference. 
   If an intermediate connector is used, the intermediate connector would be incorporated into the package  31  or leadframe. Alternately, the positions of the first and second semiconductor chips are switched. 
   The first and second semiconductor chips may be positioned so that the rear surface of the first semiconductor chip (with the antenna farm) is juxtaposed with the front surface of the second semiconductor chip (with the switch array). The plurality of switches and/or relays on the second semiconductor chip are arranged in a manner so that the corresponding plurality of elements in the antenna farm overlay the switches. 
   The lower chip may be positioned face down, so that the backsides of the chips are juxtaposed. This permits the lower chip to be bump bonded or otherwise attached to connection points. If connections between the chips are made through the package or leadframe, the lower chip can be bump bonded, attached in an inverted leadframe-over-chip, or similar inverted chip technique. 
     FIG. 5  is a diagram showing a pair of chips positioned so that the faces of the two chips are in a juxtaposed position. This has the advantage of permitting the switching array to be connected to the antenna elements. Further connections between circuit elements on one or both semiconductor substrates can be effected either directly from the chip to the package or by connections between the chips and then from one chip to the package. 
     FIG. 6  is a diagrammatic representation of a packaged semiconductor integrated circuit  90  according to an alternate arrangement, in which the first and second chips  11 ,  21  are positioned in a package  91  and are juxtaposed in a face-to-back relationship. In operation, the rear surface of the second semiconductor chip  21  is juxtaposed with the front surface of the first semiconductor chip  11 . A flexible membrane  92  connects the first and second chips  11 ,  21 . In assembling the packaged integrated circuit  90 , the membrane  92  is folded back on itself, by forming bends  93 ,  94 , so that one side of the membrane  92  bearing contacts  97 – 100  faces the top sides of the first and second chips  11 ,  21 . The first and second chips  11 ,  21  are aligned with the membrane  92  and facing the contacts  97 – 100  of the membrane  91 . The first and second chips  11 ,  21  are bonded to the membrane  92  so as to establish ohmic contact with the membrane  91  through the contacts  97 – 100 , for example by ball bonding to the contacts  97 – 100 . As a result of the membrane  92  being double folded both the first and second chips  11 ,  21  can be positioned face up, with the second chip  21  positioned over the first chip  11  inside the package  91 . The chips  11 ,  21  may then be connected to the package  91 , such as by wirebonds  103 , through the membrane  91  or by other techniques. 
   This configuration of the folded membrane  92  provides ease of assembly in that a single side of the membrane  92  is used to establish connections for the chips  11 ,  21  by bonding the chips  11 ,  21  directly to the membrane  92 . 
   The configuration of  FIG. 6  can be used in cases in which a first one of the chips  11 ,  21  provide logic circuitry controlling switches on a second one of the chips  11 ,  21 . The flexible membrane  92  may have antenna elements formed thereon, as by plating. This permits the antenna elements to be placed within the package  91  on a layer separate from that of the logic circuitry and the switching array. 
     FIG. 7  is a diagrammatic representation of a semiconductor chip  121  that includes a switching array  122  and logic circuitry  125  in accordance with an alternate embodiment of the present invention.  FIG. 8  is a diagrammatic representation of a semiconductor chip  131  that includes an antenna farm  132  controlled by the semiconductor chip  121  of  FIG. 7 . This is the reverse configuration of that depicted in  FIGS. 1–2 , but still involves the connection of the antenna farm  132  to switching array  122  by juxtaposing the two semiconductor chips  121 ,  131 . This configuration has the advantage that the antenna farm  132  can be fabricated in a less complex manner than that required to fabricate semiconductor components with two or more conductive layers. In one configuration, the fabrication of the antenna farm  132  could be made with a metalliztion layer over an oxide layer, or even a resistive substrate. By forming the antenna array on a separate chip, it is possible to use scrap wafers for the antenna array. The use of scrap wafers makes it more economical to provide antenna arrays which occupy more silicon real estate than would be available on the logic chip. 
     FIG. 9  is a cross-sectional view of an assembly  170  in which three separate semiconductor chips  171 – 173  are mounted in a package  174 . The semiconductor chips  171 – 173  are used for control logic  177  (on chip  171 ), switching array  178  (on chip  172 ) and an antenna farm  178  (on chip  173 ). This arrangement permits the use of different fabrication techniques for the different functions of the logic  177 , antenna switching  178  and the antenna farm  179 . The three layers of antenna, switch and algorithms are provided. Wirebond connections  182  are effected between one of the chips  171  and the package  174 . Chips  172 ,  173  are connected with ball bonds  183 , and a wirebond connection  187  is made between chip  172  and chip  171 . It is understood that connections with chip  172  or  173  can be made directly through the package  174 , and connections between the chips  171 – 173  can be effected by connection to package terminations. A lid  189  is provided which, if desired for purposes of signal propagation, may be made of a dielectric material. The specific selection of which of chips  171 – 173  are used for the control logic  177 , the switching array  178  and the antenna farm  178  is one of design choice. 
     FIG. 10  is a cross-sectional view of a configuration of an assembly  200  using an alternate connection arrangement. Separate semiconductor chips  201 – 203  are provided in a package  204 . As is the case with the configuration of  FIG. 9 , semiconductor chips  201 – 203  are used for control logic  207  (on chip  201 ), switching array  208  (on chip  202 ) and an antenna farm  208  (on chip  203 ). Wirebond connections  212  are effected between one of the chips  201  and the package  204  and chips  202 ,  203  are connected with ball bonds  213 . A flexible membrane web  219  is provided between chips  201  and  203 , so that signals are communicated between chips  201  and  203  through the web. Connections between chip  201  and  202  is therefore through chip  203  and the web  219 . As is the case with the arrangement of  FIG. 9 , connections with chip  202  or  203  can be made directly through the package  204 , and connections between the chips  201 – 203  can be effected by connection to package terminations. A lid  222  is provided which, if desired for purposes of signal propagation, may be made of a dielectric material. 
     FIG. 11  is a diagrammatic representation of an arrangement in which a semiconductor chip  251  includes an antenna farm  252  connected to antenna elements  255 ,  256  external to the semiconductor chip  251 . Logic circuitry  259  may be included on the semiconductor chip  251 . The antenna farm  252  consists of a plurality of antenna elements  261 – 268 . The connection of the external elements  255 ,  256  to the elements  261 – 268  of the antenna farm  252  can be fixed to some or all of elements  261 – 268 , or selectively switched. Switching of the internal elements on the antenna farm  252  and switching of the external elements  255 ,  256  can be achieved externally, such as by use of switch array  26 , such as shown in  FIG. 2 . 
   By selectively connecting the antenna elements, it is possible to use a few fixed radiators in the form of the external elements  255 ,  256 , while changing the characteristics of the antenna formed by the combination of the external elements  255 ,  256  and elements  261 – 268  of the antenna farm  252 . Thus, for example, polarization of the antenna can be effected by selectively connecting the elements  261 – 268  of the antenna farm  252 , in some cases without changing the physical orientation of the external elements  255 ,  256 . This change in polarization is achieved by changing the orientation of the electromagnetic field of the antenna by selectively switching the elements  261 – 268  of the antenna farm  252 . 
     FIG. 12  is a diagram showing a wireless transmit/receive unit (WTRU)  301  using an antenna farm. A wireless transmit/receive unit (“WTRU”) includes but is not limited to a user equipment (UE), mobile station, fixed or mobile subscriber unit, pager, fixed portable or any other type of device capable of operating in a wireless environment. These exemplary types of wireless environments include, but are not limited to, wireless local area networks (WLANs) and public land mobile networks. A “base station” includes but is not limited to a base station, Node B, site controller, access point or other interfacing device in a wireless environment. 
   In  FIG. 12 , the WTRU  301  comprises an RF section semiconductor integrated circuit  304  which includes an antenna farm, and also includes external connections  306 ,  307  to antennas  308 ,  309 . The external connections  306 ,  307  are normally internal to the WTRU  301  but external to the RF IC  304 ; however the WTRU  301  may also have an external antenna connection for connection of a remote antenna. 
   The RF IC  304  has further connections, such as to audio processing circuitry  312 . By including an internal antenna farm such as described in connection with  FIGS. 1–11 , the WTRU&#39;s antenna pattern can be adjusted. The adjustment of the antenna pattern can be achieved despite the fact that externally connected antennas  308 ,  309  are in fixed positions with respect to the WTRU  301 . 
   One area of growing interest for wireless communications is the use of a multiple input/multiple output (MIMO) arrangement. Typically, MIMO communications are conducted using a plurality of both transmitting and receiving antenna elements. One drawback to widespread application is having multiple antenna elements in small WTRU devices. The multiple IC embedded antenna elements as described can be used to facilitate such communication. The multiple antennal elements can be utilized for both transmission and reception, either alone or in conjunction with one or more external antenna elements. 
     FIG. 13  is a diagram showing a configuration for a WTRU  340  in which multiple ICs  341 – 346  are provided to facilitate MIMO communications. These multiple ICs provide spatial diversity to facilitate MIMO communication. Alternately, an external antenna  351  can be used. The external antenna is coupled to the ICs  341 – 346  via connections  352 . The use of the IC antenna elements facilitates spatial diversity in a small device, allowing for MIMO communication. 
     FIG. 14  is a diagram showing a configuration of a WTRU  370 , in which multiple ICs  371 – 376  are mounted on a printed circuit board  379  having an antenna  381 . The antenna  381  is printed onto the circuit board  379 , so that the antenna is external to the ICs  371 – 376 , but integral with the board  379 . The WTRU also incorporates an antenna  382  which is separate from the board  379 . The combination of the antenna arrays in one or more of the ICs  371 – 376  and the external antennas  381 ,  382  provide diversity of antenna functions between the ICs  371 – 376 . 
     FIG. 15  is a diagram showing an exemplary use of the invention used in a variable input (VI) receiver  400 . In the case of a small receive-only device such as a satellite radio, digital video or digital audio systems, the multiple IC embedded antenna elements can be used to facilitate such communication. In the embodiment shown, VI arrangements permit the receiver  400  to track multiple signals, for example, those coming from different satellites  411 ,  412 . Such variable input communications may be conducted using a plurality of receiving antenna elements, which may be integrated within one or more ICs  421   426 . According to the present invention, when used in such a receive-only device  400 , the multiple antenna elements can be utilized for reception. In addition to satellite broadcasts, the receiver  400  can receive signals from ground sources or from a combination of ground sources and satellites. As is the case with the WTRU configurations described, the multiple antenna units can be used either alone or in conjunction with one or more external antenna elements, such as antenna elements  428 ,  429 .