Abstract:
I describe and claim a device and method for generating develop voltage signals. The device includes a sense amplifier to sense a voltage difference between a plurality of bit lines responsive to a develop voltage signal, and a voltage generator to generate the develop voltage signal responsive to a reference voltage signal and according to an electrical characteristic of at least one transistor associated with the sense amplifier.

Description:
CROSS-REFERENCE TO RELATED PATENT APPLICATION  
       [0001]     This application claims priority from Korean Patent Application No. 10-2005-0079273, filed on Aug. 29, 2005, which we incorporate by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to memory devices, and more particularly, to the stabilization of the sensing speed of sense amplifiers included in memory devices.  
         [0004]     2. Description of the Related Art  
         [0005]     Generally, semiconductor memory devices include an internal power supply voltage circuit to supply an internal power supply voltage to other circuits associated with the memory devices. An example of a circuit for generating the internal power supply voltage is disclosed in U.S. Pat. No. 6,087,891. The internal power supply voltage is usually generated by reducing the voltage level of the external power supply voltage.  
         [0006]     For instance, sense amplifiers included in memory devices use an internally generated develop voltage to develop a voltage between a pair of bit lines. The develop voltage is generated by a develop voltage generator in response to a develop reference voltage from a develop reference voltage generator. The develop voltage generator generates a develop voltage that has a high current level and has the same voltage level as the develop reference voltage.  
         [0007]      FIG. 1  is a circuit diagram illustrating a develop reference voltage generator included in a conventional semiconductor memory device. Referring to  FIG. 1 , the develop reference voltage generator includes a differential amplifier and a voltage divider. The differential amplifier includes two PMOS transistors P 1  and P 2  connected to a first power supply voltage VDD, and two NMOS transistors N 1  and N 2  connected to the PMOS transistors P 1  and P 2 , respectively. A reference voltage Vref is applied to a gate of NMOS transistor N 1 , and an input voltage Vin is applied to a gate of the NMOS transistor N 2 .  
         [0008]     The differential amplifier includes an NMOS transistor N 3  coupled between the NMOS transistors N 1  and N 2  and a second power supply voltage Vss. A predetermined bias voltage is applied to a gate of the NMOS transistor N 3  to perform differential amplifying operations. The differential amplifying operations are performed until the first reference voltage Vref and the input voltage Vin become equal to each other. In other words, the input voltage Vin is set to the reference voltage Vref by the differential amplifying operations.  
         [0009]     The voltage divider includes a plurality of resistors R 1 , R 2 , and R 3 . The differential amplifier applies the input voltage Vin to the voltage divider between the resistors R 1  and R 2 . A voltage proportional to the input voltage Vin output by the voltage divider as a develop reference voltage Vrefa. For example, when the reference voltage Vref is 1.0 V, the develop reference voltage Vrefa may become 1.2 V by changing the value of the resistors R 1 , R 2 , and R 3 .  
         [0010]     A develop voltage generator (not shown) receives the develop reference voltage Vrefa from the develop reference voltage generator and generates a develop voltage that has a high current level and has the same voltage as the develop reference voltage Vrefa. The develop voltage generator provides the develop voltage to a sense amplifier (not shown) for use in sensing operations.  
         [0011]     Since the manufacture or processing of sense amplifiers is inconsistent, many sense amplifiers require different levels of develop voltages to operate optimally or with a stable sensing speed. Particularly, sense amplifiers include one or more transistors having threshold voltages that vary depending on their manufacturing process. The develop reference voltage generator shown in  FIG. 1 , however, provides a uniform develop reference voltage regardless of manufacturing variations. Accordingly, the sensing speeds of the sense amplifiers are unstable in each die of a semiconductor memory device. This problem becomes magnified when attempting to manufacture circuits with low power consumption, thus reducing the allowable voltage difference between the develop voltage and the threshold voltage of the sense amplifier transistors.  
       SUMMARY OF THE INVENTION  
       [0012]     Embodiments of the present invention provide a device to stabilize sensing speeds of sense amplifiers by varying a develop reference voltage according to variations of a threshold voltage of transistors included in the sense amplifiers. The device includes a sense amplifier to sense a voltage difference between a plurality of bit lines responsive to a develop voltage signal, and a voltage generator to generate the develop voltage signal responsive to a reference voltage signal and according to an electrical characteristic of at least one transistor associated with the sense amplifier. 
     
    
     DESCRIPTION OF THE DRAWINGS  
       [0013]     The features and advantages of the present invention will become more apparent with a detailed description of the exemplary embodiments referencing the attached drawings.  
         [0014]      FIG. 1  is a circuit diagram of a conventional develop reference voltage generator.  
         [0015]      FIG. 2  is a block diagram of a memory device useful with embodiments of the present invention.  
         [0016]      FIG. 3  is a circuit diagram embodiment of the develop reference voltage generator shown in  FIG. 2 .  
         [0017]      FIG. 4  is a circuit diagram embodiment of the voltage boosting unit shown in  FIG. 2 .  
         [0018]      FIG. 5  is a circuit diagram of another embodiment of the voltage boosting unit shown in  FIG. 2 .  
         [0019]      FIG. 6  is a block diagram of another memory device useful with embodiments of the present invention.  
         [0020]      FIG. 7  is a circuit diagram embodiment of the develop reference voltage generator shown in  FIG. 6 . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0021]      FIG. 2  is a block diagram of a memory device useful with embodiments of the present invention. Referring to  FIG. 2 , the memory device includes a develop reference voltage generator  10  to generate a develop reference voltage Vrefa responsive to a reference voltage Vref, a develop voltage generator  20  to generate a develop voltage AIVC responsive to the develop reference voltage Vrefa, and a sense amplifier  30  to sense and amplify a voltage difference between a pair of bit lines BL and /BL responsive to the develop voltage AIVC.  
         [0022]     The develop reference voltage generator  10  includes a proportional voltage generating unit  11 , a buffer unit  12 , and a voltage boosting unit  13 . The proportional voltage generating unit  11  receives the reference voltage Vref and generates a proportional reference voltage that is proportional to the first reference voltage Vref. For instance, the proportional voltage generating unit  11  may generate a proportional reference voltage that is substantially equal to α*Vref, where α is a constant.  
         [0023]     The buffer unit  12  receives and buffers the proportional reference voltage. The buffer unit  12  may be coupled between the proportional voltage generating unit  11  and the voltage boosting unit  13  to electrically isolate them from each other.  
         [0024]     The voltage boosting unit  13  receives the proportional reference voltage from the buffer unit  12 , boosts the proportional reference voltage to generate the develop reference voltage Vrefa. When the boosted portion of the develop reference voltage is β, the develop reference voltage Vrefa may be described as (α*Vref)+β, where both α and β are constants. The value β may be the absolute value of the threshold voltage of a transistor included in the sense amplifier  30 . For instance, when the sense amplifier  30  includes PMOS transistors P 11  and P 12  and NMOS transistors N 11  and N 12 , as shown in  FIG. 2 , the value β may be the absolute value of the threshold voltage of the PMOS transistors P 11  and P 12  or the threshold voltage of the NMOS transistors N 11  and N 12 .  
         [0025]     The develop reference voltage Vrefa generated in the voltage boosting unit  13  is applied to the develop voltage generator  20 . The develop voltage generator  20  receives the develop reference voltage Vrefa and generates the develop voltage AIVC. The develop voltage AIVC may have a high current level and the same voltage as the develop reference voltage Vrefa.  
         [0026]     The sense amplifier  30  may pull up or pull down a voltage level of one or more of the bit lines BL and /BL responsive to the develop voltage AIVC. The memory device may include a pull-up PMOS transistor P 13  to control the application of the develop voltage AIVC to the sense amplifier  30  responsive to a pull-up control signal LAPG. In some embodiments, the voltage boosting unit  13  may increase the voltage level of the proportional reference voltage according to the absolute value of the threshold voltage of the pull-up PMOS transistor P 13 .  
         [0027]      FIG. 3  is a circuit diagram embodiment of the develop reference voltage generator  10  shown in  FIG. 2 . Referring to  FIG. 3 , the develop reference voltage generator  10  includes the proportional voltage generating unit  11 , the buffer unit  12 , and the voltage boosting unit  13 .  
         [0028]     The proportional voltage generating unit  11  includes a differential amplifier and a voltage divider. The differential amplifier includes PMOS transistors P 21  and P 22  coupled to a power supply voltage VDD, and NMOS transistors N 21  and N 22  coupled to the PMOS transistors P 21  and P 22 , respectively. The reference voltage Vref and an input voltage Vin are applied to gates of the NMOS transistors N 21  and N 22 , respectively. An enable transistor N 23  is coupled between the NMOS transistors N 21  and N 22  and a ground voltage Vss. The enable transistor N 23  receives a bias voltage to control the operation of the differential amplifier. When the differential amplifier performs a differential amplifying operation, until the input voltage Vin becomes substantially equal to the reference voltage Vref.  
         [0029]     The voltage divider includes resistors R 11  and R 12  to divide the input voltage Vin. In some embodiments, the voltage divider may include more or less resistors than shown in  FIG. 3 . When a switch P 23  coupled to the voltage divider is turned off, the voltage divider divides the input voltage Vin according to a ratio of the resistors R 11  and R 12 . Thus the voltage output from the voltage divider is proportional to reference voltage Vref, tor α*Vref, where α is a constant. For instance, when the resistors R 11  and R 12  have the same resistance, the proportional reference voltage becomes 0.5*Vref.  
         [0030]     The proportional voltage generating unit  11  provides the proportional reference voltage to the buffer unit  12 . The buffer unit  12  receives and buffers the proportional reference voltage. Accordingly, the proportional voltage generating unit  11  and the voltage boosting unit  13  may be electrically isolated by the buffer  12 .  
         [0031]     The voltage boosting unit  13  receives the proportional reference voltage from the buffer  12 , boosts the proportional reference voltage, and generates the develop reference voltage Vrefa. For example, the voltage boosting unit  13  can boost the proportional reference voltage by the absolute values of the threshold voltages of the PMOS transistors P 11  and P 12  included in the sense amplifier  30  of  FIG. 2 . The voltage boosting unit  13  may include a replica PMOS transistor P 31  having the same threshold voltage as those of the PMOS transistors P 11  and P 12  included in the sense amplifier  30 .  
         [0032]     The voltage boosting unit  13  includes the replica transistor P 31  and a switching transistor P 32  disposed between the power supply voltage VDD and the replica transistor P 31 . The threshold voltage characteristics of the transistors may vary depending on process deviation in each die. Since the replica PMOS transistor P 31  is formed using the same or similar process deviation as the PMOS transistors P 11  and P 12 , the replica PMOS transistor P 31  has the same or similar threshold voltage characteristics as those of the PMOS transistors P 11  and P 12 .  
         [0033]     The replica PMOS transistor P 31  may be diode-connected such that the voltage boosting unit  13  boosts the proportional reference voltage by the absolute values of the threshold voltages of the PMOS transistors P 11  and P 12 . The replica transistor P 31  includes a first terminal is coupled to an output port, a second terminal is coupled to the buffer unit  12 , and a control gate terminal coupled to, or diode-connected to the second terminal. The voltage of the output port is greater than that of the second terminal by the absolute value of the threshold voltage of the replica PMOS transistor P 31 , in accordance with the diode-connection characteristics of the replica transistor P 31 .  
         [0034]     For example, when the resistances of the resistors R 11  and R 12  of the voltage divider are equal to each other and the absolute value of the threshold voltage of the replica transistor P 31  is 0.7 V with a reference voltage Vref of 1 V, the develop reference voltage Vrefa becomes (0.5*Vref)+0.7=1.2V. When the threshold voltage of the PMOS transistors P 11  and P 12  is changed to 0.5 V, the develop reference voltage Vrefa is also changed to 1.0 V. Thus, threshold voltage variations in sense amplifiers generated during transistor formation can be accounted for by proportioning the reference voltage Vref and then boosting the proportional reference voltage. Accordingly, by uniformly maintaining the voltage for developing the pair of bit lines BL and /BL, the sensing speed of the sense amplifiers  30  may be stable.  
         [0035]      FIG. 4  is a circuit diagram embodiment of the voltage boosting unit  13 A shown in  FIG. 2 . Referring to  FIG. 4 , a voltage boosting unit  13 A includes a replica transistor N 31  and a switching transistor P 32  coupled between a power supply voltage VDD and the replica transistor N 31 . In particular, the replica transistor N 31  may be an NMOS transistor, formed using the same or similar process deviation as the NMOS transistors N 11  and N 12  associated with the sense amplifier  30 . The replica NMOS transistor N 31  includes a first terminal coupled to the buffer unit  12 , a second terminal coupled to an output port, and a control gate terminal couple to the second terminal in a diode-connection.  
         [0036]     Accordingly, when the proportional reference voltage from the buffer unit  12  is α*Vref, the voltage boosting unit  13 A generates a develop reference voltage Vrefa according to (α*Vref)+γ, where γ is the threshold voltage of the replica NMOS transistor N 31 . This develop reference voltage Vrefa allows the sense amplifier to maintain a voltage difference between the pair of the bit lines BL and /BL. Thus, even when a pull-down voltage varies due to the difference between the threshold voltages of the NMOS transistors N 11  and N 12  of the sense amplifier  30 , the sense amplifier  30  may maintain a stable sensing speed.  
         [0037]      FIG. 5  is a circuit diagram of another embodiment of the voltage boosting unit  13 B shown in  FIG. 2 . Referring to  FIG. 5 , the voltage boosting unit  13 B includes a replica transistor P 41 , formed using the same or similar process deviation as that of the pull-up transistor (P 13  of  FIG. 2 ) for pulling up the voltage of the output port of the PMOS transistor of the sense amplifier  30 . Similar to  FIG. 4 , a first terminal and a second terminal of the replica transistor P 41  are coupled to a buffer unit  12  and an output port, respectively, and the second terminal and a control gate terminal of the replica transistor P 41  are coupled to each other.  
         [0038]     Accordingly, even when the threshold voltage of the pull-up transistor varies in every die, the develop voltage AIVC generated by the develop voltage generator  20  is uniformly applied to the sense amplifier  30  in each die and thus the sensing speed of the sense amplifier  30  can become stable.  
         [0039]      FIG. 6  is a block diagram of another memory device useful with embodiments of the present invention. The configuration and operation of a develop voltage generating circuit and a sense amplifier  30  shown in  FIG. 6  are the same as those of the above-described embodiment illustrated in  FIG. 2 . Referring to  FIG. 6 , a develop reference voltage generator  100  includes a proportional voltage generating unit  110  and a develop reference voltage generating unit  120 . The develop reference voltage generating unit  120  includes at least one buffer unit  121  and  123  and at least one voltage boosting unit  122  and  124 . For example, the buffer unit includes a first buffer unit  121  and a second buffer unit  123 , and the voltage boosting unit includes a first voltage boosting unit  122  and a second voltage boosting unit  124 .  
         [0040]     The proportional voltage generating unit  110  receives a first reference voltage Vref and generates a second reference voltage proportional to the first reference voltage Vref. The first buffer unit  121  receives and buffers the second reference voltage. The first buffer unit  121  generates a third reference voltage from the second reference voltage and provides the third reference voltage to the first voltage boosting unit  122 .  
         [0041]     The first voltage boosting unit  122  receives and boosts the third reference voltage to generate a fourth reference voltage. The second buffer unit  123  buffers the fourth reference voltage and generates a fifth reference voltage from the fourth reference voltage. The second voltage boosting unit  124  receives and boosts the fifth reference voltage to generate a develop reference voltage Vrefa.  
         [0042]     In some embodiments, the first voltage boosting unit  122  boosts the third reference voltage by the absolute value of the threshold voltage of any one of PMOS transistors P 11  and P 12  included in the sense amplifier  30 , NMOS transistors N 11  and N 12  included in the sense amplifier  30 , or a pull-up PMOS transistor P 13 . The second voltage boosting unit  124  may boost the fifth reference voltage by the absolute value of the threshold voltage of another one of the above-described transistors. In other embodiments, the voltage boosting units  122  and  124  may boost the corresponding reference voltages by the threshold voltages associated with multiple transistors of the sense amplifier  30  and the pull-up PMOS transistor P 13 . The operation of the develop reference voltage generator  100  will be described in greater detail below in  FIG. 7 .  
         [0043]      FIG. 7  is a circuit diagram embodiment of the develop reference voltage generator shown in  FIG. 6 . Referring to  FIG. 7 , the proportional voltage generating unit  110  includes a differential amplifier and a voltage divider. The differential amplifier performs a differential amplifying operation to substantially equalize an input voltage Vin with the first reference voltage Vref. The voltage divider includes one or more resistors R 21  and R 22  to divide the input voltage Vin similarly to the voltage divider shown and described above with reference to  FIG. 3 .  
         [0044]     The second reference voltage generated at the proportional voltage generating unit  110  is proportional to the first reference voltage Vref, and is shown as δ*Vref, where δ is a constant. The first buffer unit  121  buffers the second reference voltage and generates the third reference voltage from the second reference voltage.  
         [0045]     The first voltage boosting unit  122  includes a replica transistor P 61 . The replica transistor P 61  may be a PMOS transistor, and may be formed using the same or similar process deviation as the PMOS transistors P 11  and P 12  included in the sense amplifier  30 . The replica transistor P 61  may be diode-connected as shown and thus the fourth reference voltage generated by the first voltage boosting unit  122  may become (δ*Vref)+|v t61 |, where v t61  is the threshold voltage of replica transistor P 61 . The second buffer unit  123  receives and buffers the fourth reference voltage and generates the fifth reference voltage.  
         [0046]     The second voltage boosting unit  124  receives and boosts the fifth reference voltage to generate the develop reference voltage Vrefa. The second voltage boosting unit  124  may include a diode-connected replica transistor N 71 . The replica transistor N 71  may be an NMOS transistor, and may be formed using the same or similar process deviation as the NMOS transistors N 11  and N 12  included in the sense amplifier  30 . The second voltage boosting unit  124  may increase the voltage level of the fifth reference voltage by the absolute value of the threshold voltage of the replica transistor N 71 . Accordingly, the generated develop reference voltage Vrefa may become (δ*Vref)+|v t61 |+|v t71 |, where v t71  is the threshold voltage of transistor N 71 .  
         [0047]     For example, when the first reference voltage Vref is 1.0 V, resistors R 21  and R 22  respectively have resistances of 7K and 3K, the absolute value of the threshold voltage of the replica transistor P 61  of the first voltage boosting unit  122  is 0.5 V, and the absolute value of the threshold voltage of the replica transistor N 71  of the second voltage boosting unit  124  is 0.4 V, the generated develop reference voltage Vrefa becomes (0.3*1)+0.5+0.4=1.2 V. The generated develop voltage may also vary according to the variation of the threshold voltages of the PMOS transistors P 11  and P 12  and the NMOS transistors N 11  and N 12  of the sense amplifier  30 .  
         [0048]     Although  FIG. 7  shows, the first voltage boosting unit  122  including a replica transistor P 61  similar to the PMOS transistors P 11  and P 12  and the second voltage boosting unit  124  including the replica transistor N 71  similar to the NMOS transistors N 11  and N 12 , in some embodiments the first voltage boosting unit  122  may include a replica transistor of any one of the PMOS transistors P 11  and P 12  included in the sense amplifier  30 , the NMOS transistors N 11  and N 12  included in the sense amplifier  30 , and a pull-up transistor P 13 . The second voltage boosting unit  124  may also include a replica transistor of the other of the above-described transistors.  
         [0049]     Even when at least two of the PMOS transistors P 11  and P 12  inc, the NMOS transistors N 11  and N 12 , and the pull-up transistor P 13  have different transistor characteristics in each die, the voltage difference between the pair of bit lines BL and /BL connected to the sense amplifier  30  can be uniformly maintained, and thus sensing speed can become stable.  
         [0050]     While the present invention has been particularly shown and described with reference to exemplary embodiments thereof it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.