Abstract:
Communication system having a multiprocessor system serving the purpose of central control. Multiprocessor systems are used in communication systems for the purpose of central control. Care must thereby be exercised to ensure that the jobs/messages arriving from a periphery according to the FIFO principle are in turn deposited in the original sequence after being handled by processes being executed on the processors. A coordination procedure required for this purpose thereby uses a holding table. The logical sequence of jobs/messages is thus assured during the processing in the multiprocessor system.

Description:
BACKGROUND OF THE INVENTION 
     The present invention is directed to a communication system having terminal equipment connected via line terminal groups as well as a switching matrix network for through-connection of calls and having a multiprocessor system for central control. 
     During the course of developing more and more complex data processing systems/communication systems, prior art single processing systems were expanded into multiprocessor systems. In contrast to the single processor systems wherein data/status messages are sequentially processed, parallel processing is utilized in multiprocessor systems. Compared to single processor systems, the multiprocessor systems have significant advantages, as indicated, for example, by the great increase in processing speed. The parallel processing of a plurality of tasks is achieved in that a task to be processed is divided into a plurality of sub-tasks, whereby one microprocessor processes respectively one sub-task, and the sub-results are subsequently combined to form an overall result. The sub-tasks are handled on the basis of the processes sequencing at the individual processors. A task/sub-task can thereby be composed of different functional organization sequences in the system. Thus, one process sequencing on a processor handles tasks/sub-tasks of, for example, error correction procedures, time-monitoring procedures or procedures of switching technology. Two or more processes, however, cannot simultaneously handle a sub-task. This is controlled by a monitoring process in the operating system. 
     What is problematical, however, is that various processes simultaneously access a memory register and can thereby produce undefined conditions. European Patent Application 0 274 715 A3  discloses a method for preventing simultaneous access of two processes to a memory register. By entering a processor number into the appertaining memory registers, the disclosed SECURE procedure prevents simultaneous access of a first process and of a competing, second process to this memory register. This occurs in that the competing, second process only modifies the memory contents of a memory register when a processor number is entered therein. Otherwise, this corresponds to the momentary access of an earlier, first process to that memory register and the competing, second process is entered into a waiting queue behind the first process. As soon as the present access is ended, the competing, second process in the waiting queue is now allowed to access this memory register. A simultaneous access of two processes to a memory register is thus prevented. 
     In a communication system, all processes are subjected to a hierarchic organizational structure. This is achieved by a prioritization of the process sequence. Thus, for example, a process having a higher priority can interrupt a process having lower priority at any time. When the process with higher priority has ended its task, a process having a lower priority can continue the handling of its original task. In communication systems, such processes having high priority are usually processes for error correction, time monitoring, etc. This, however, means that a process handling a task can be noticeably retarded in terms of its chronological sequence by a process having a higher priority. This is a particular disadvantage in that the sequence of the sub-tasks must be strictly adhered to. 
     Such a situation is to be avoided under all circumstances. When this situation occurs, the communication system therefore aborts the corresponding connection. One possibility of alleviating this situation is in employing known acknowledgement methods (such as handshaking). These methods can in fact be employed for data processing systems since the user (programmer) can wait a few 100 milliseconds in the least favorable case. In modern communication systems, however, the employment of such methods would lead to such a great load on the central bus system, as well as, on the corresponding processors that the resulting chronological delays could no longer be tolerated. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide the communication system having a multiprocessor system for control such that the handling of tasks in the proper sequence is coordinated and chronological delays of a greater extent are thereby avoided. The multiprocessor system is composed of a central system bus to which processors are connected, and a memory system also connected to the central system bus and shared in common by all units of the multiprocessor system. The memory system has at least one entry list for the set up/administration of connections of terminal equipment. The status messages relevant to the connections are intermediately stored in the entry list for further processing by processes being executed on the processors. The object of the present invention is inventively achieved by a system in which the handling of a status message deposited in the entry list and deriving from a source by a first process being executed on a processor is made dependent on a second process handling a status message and being executed on another processor when both status messages derive from the same source. The second process handling its status message deposits an identifier of the source of this message in a holding table created in the common memory system before the beginning of processing and does not in turn erase this identifier until the conclusion of the handling of its message. The first process only begins handling its status message when no entry of the identifier of the same source due to a different process exists in the holding table at this time. 
     What is important for the present invention is the introduction of the holding table. The exclusive inhibit of the central bus system by a processor for the duration of an access onto the holding table does not mean any limitation of the dynamic loss of the multiprocessor system. The holding procedure thus coordinates the tasks within the system. The time advantage achieved by the parallel handling of the tasks by different processors is disproportionately greater than the slight time loss that arises due to the coordination events themselves (for example, inhibiting the central bus system, placing processors in waiting gueues, etc.). 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The features of the present invention which are believed to be novel, are set forth with particularity in the appended claims. The invention, together with further objects and advantages, may best be understood by reference to the following description taken in conjunction with the accompanying drawing, in which: 
     The single FIGURE depicts a modularly structured multiprocessor system that coordinates decentralized processor units of a communication system. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The present invention has general applicability, but is most advantageously utilized in a system as depicted in the single FIGURE. In general terms the multiprocessor system has the following elements: 
     central system bus B:CMY; 
     a plurality of processor units P 1  . . . P n  connected thereto; 
     a plurality of input/output processors IOP whereby a plurality of line terminal groups LTG . . . LTG n  are connected to at least one of these input/output processors IOP; and 
     a memory system CMY connected to the central system bus and shared in common by all units of the multiprocessor system. 
     The fundamental functioning can be set forth in greater detail with reference to a connection between two subscribers A, B. The two subscribers are thereby respectively connected to one of the line terminal groups LTG 1  . . . LTG n . Four different status messages M 1  . . . M 4  are required for the call setup/call clear-down between two subscribers A, B as follows: 
     M 1  : SEIZURE; 
     M 2  : digit block (select); 
     M 3  : SETUP (call set up in the switching matrix network, ringing the B-subscriber, etc. ); and 
     M 4  : RELEASE. 
     The status messages are deposited according to the FIFO principle in an entry list EL situated in the common memory system CMY and are serviced onto the processes CALLP 1  . . . CALLP n   allocated to the processors P 1  . . . P n . What are referred to as channel registers CHR 1  . . . CHR n  are also allocated to a connection. Parameters about the respective status of a connection are deposited therein (for example, to which line terminal group LTG x  the subscriber is connected or which switching matrix network is involved in the connecting circuit). 
     As an example, let the subscribers A, B be connected to the line terminal group LTG x . The subscriber A picks up the receiver of his terminal equipment. He thereby informs the communication system of a desired connection to what is still an unknown subscriber B. The seizure of the receiver initiates the system to write the corresponding status message M 1  into the entry list EL provided for this purpose and situated in the common memory system CMY. Subsequently, the subscriber A attempts to select the number of the subscriber B. This initiates the system to write a corresponding status message M 2  into the entry list EL. An analogous procedure occurs for the status messages M 3 , M 4  of this connection as well as for the status messages of other connections. Further, all processes CALLP 1  . . . CALLP n  allocated to the processors P 1  . . . P n  are in an active or passive condition depending on whether or not there are corresponding call requests on the part of the subscribers. 
     After a status message has been successfully handled, a process is answered back at the operating system. The operating system assigns the process that has become free the handling of a new status message. In the exemplary embodiment, this is to be the status message M1, denoting that M 1  is handled by the process CALLP x . A second process CALLP y  that has become free should handle the status message M 2  at the same time. Another process having a higher priority can then interrupt, for example, the process CALLP x . This denotes that the result of the status message M 1  can only be deposited in the relevant memory registers (for example, the channel register) at a correspondingly later time. As a result the status messages M 1  . . . M n  originally deposited in the entry list EL according to the FIFO principle are now deposited in the corresponding memory registers in the inverse sequence after they are handled. This sequence, however, is the basis for further handlings. In many instances, however, it now no longer represents an intrinsically logical sequence of status messages. For example, the call set up is characterized in that a status message M 1  (seizing the receiver) is followed by a status message M 2  (selecting). An inversion of this sequence, however, contradicts the logical completion of a call setup, this intrinsically leading to an immediate abort of this connection. Such an abort can be avoided by using the holding table HT in the common memory system CMY. 
     The status messages M 1  . . . M n  of a connection from a source LTG x  are thereby especially affected in view of possible chronological delays since the immediate succession of two status messages of the entry list EL here involves a higher probability of the inversion of the sequence. 
     Before it handles a status message M x , every process CALLP x  that is just activated must therefore verify the origin of the status message, i.e. the line terminal group LTG x  in this example. This is carried out by analyzing the message overhead of the corresponding message that contains the source location. Subsequently, the associated process CALLP x  that has just been activated enters the identifier of the source of the message into the holding table HT. The entry occurs only in case no other message of the same source is being handled at the same time, i.e. when no identifier of the same source resides in the holding table HT. Otherwise, the associated process CALLP x  assumes the handling of the next message residing in the entry list EL. When, however, no identifier of the same source is contained, then the associated process CALLP x  also additionally inscribes the holding table HT with its own process-associated identifier, as well as, with a time-monitoring parameter that shall be discussed later. After the status message M x  has been successfully handled, the process CALLP x  erases the identifier of the source in the holding table HT, wherewith another process CALLP y  that has just been activated can handle a status message M y  of the source LTG x . 
     What this method assures is that only one message of a source is handled at one time and, consequently, an inversion of the sequence of handled messages is prevented. 
     The entry list EL is deposited in a reserved memory area of the memory system CMY. The start is marked by a read character READ-INDEX and the end is marked by a write character WRITE-INDEX. The read index is used by the process CALLP x  for handling the message M x  and is only incremented when a message M x  is read out by the process CALLP x . The read index remains unmodified in the &#34;look ahead&#34; reading due to the holding procedure. 
     It follows from the above procedure that gaps can arise in the entry list EL as a result of the holding procedure. It can thus have messages and empty list elements in an arbitrary sequence between the read index and the write index. When the read index READ-INDEX then indicates an empty list element even though further messages are present and when the write index WRITE-INDEX has not yet been fetched, the read index READ-INDEX is incremented until a list element that is not empty (i.e. a message) is encountered. 
     In order to avoid a simultaneous access of two processes CALLP x  and CALLP y  to the memory location in the holding table HT that contains the identifier of the source, the process that is the first to access inhibits the central bus system B:CMY for the duration of its access. The access of all other equipment connected to the central bus system B:CMY is thus blocked to the central bus system B:CMY. The inhibit of the central bus system B:CMY occurs on the basis of a processor command provided for this purpose. 
     When one of the processors P 1  . . . P n  is down, this has immediate effects on the process CALLP x  just sequencing therein. Due to the holding procedure, the outage of a process just being executed results in the identifier of the source remaining set in the holding table HT and is no longer erased. This would mean that all connections proceeding from subscribers that are connected to the corresponding source (line terminal group) are interrupted because the appertaining messages can no longer be handled. Processes for time monitoring are implemented in the operating system in order to avoid this. These time monitoring processes update the processes CALLP 1  . . . CALLP n  being execute on the processors P 1  . . . P n  with a corresponding timing. During the course of the entry of the identifier of the source as well as of the process identifier into the holding table HT, the associated process CALLP x  then also additionally enters a time parameter. The process implemented in the operating system for time monitoring compares this time parameter to prescribed rated values in a fixed chronological timing and then in turns implements the removal of an identifier that is still set due to the malfunction of an equipment and, thus, has not yet been erased, the processing of the corresponding messages being enabled again. 
     The invention is not limited to the particular details of the apparatus depicted and other modifications and applications are contemplated. Certain other changes may be made in the above described apparatus without departing from the true spirit and scope of the invention herein involved. It is intended, therefore, that the subject matter in the above depiction shall be interpreted as illustrative and not in a limiting sense.