Abstract:
A MOSFET structure having a biased gate covered with an insulator of such a thickness as to render the structure capable of giving a measure of accumulated charge and usable in a stacked structure as a particle spectrometer.

Description:
ORIGIN OF THE INVENTION 
     The invention described herein was made in the performance of work under a NASA Contract and is subject to the provisions of Section 305 of the National Aeronautics and Space Act of 1958, Public Law 85-568 (72 STAT 435; 43 USC 2457). 
    
    
     BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The subject invention relates to charge or voltage sensors and particularly to an improved sensor employing semiconductor device technology. 
     In the prior art, monitoring of spacecraft surface voltages, high energy environments, or internal charges within dielectrics and insulators has required heavy, complicated electronics and sensors. Power demands of such equipment are also high, presenting an additional obstacle to spacecraft use. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the invention to provide an improved voltage/charge sensor. 
     It is another object of the invention to provide a simplified, low power voltage/charge sensor. 
     It is yet another object of the invention to provide a charge sensor employing solid state technology. 
     The foregoing and other objects are achieved according to the invention by a field effect transistor (FET) structure having a biased gate formed within an insulator much thicker than the insulator provided by a typical FET passivating layer. Charges incident upon the thick insulator are accumulated and modulate conduction between the FET&#39;s source and drain. The modulation may be detected by imposing it on a source-to-drain current or other signal to provide a measure of the amount of charge accumulated on the gate insulator. Several such sensors having different gate materials and/or insulator thicknesses may be stacked to provide a particle spectrometer. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The just-summarized invention will now be described in conjunction with the drawings of which: 
     FIG. 1 illustrates a cross-section of a prior art n-channel MOSFET transistor; 
     FIG. 2 illustrates a cross-section of a charge sensor according to the preferred embodiment; 
     FIG. 3 illustrates a schematic of the charge sensor of FIG. 2 in a sampling configuration; 
     FIG. 4 illustrates an equivalent circuit of FIG. 3; and 
     FIG. 5 illustrates a cross-section of a particle spectrometer according to the preferred embodiment. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 is a representation of a prior art n-channel MOSFET transistor. Two N+ islands 11, 13 are diffused in a P substrate between a gate 15 and the two source and drain structures 17, 19. An electric potential applied to the gate 15 will affect the conduction of majority carrier charges between the source 17 and the drain 19. This electric potential causes a conduction channel 23 to be induced in the P substrate 21 between the heavily doped N+ islands 11, 13. 
     By choice of gate bias, the conductivity of the channel 23 can be either enhanced or depleted. Signals superimposed on the gate bias voltage cause proportional changes in channel conductivity. 
     If an N-doped substrate 21 is used, with heavily-doped P islands 11, 13, a P-channel MOSFET is formed. Operation is the same in principle as the N-channel case, but with opposite polarities. Both N and P type MOSFETS are normally used as amplifiers, or as switches, responsive to signals applied to the metallic gate 15. 
     In prior art MOSFETs the transistor is covered with a thin passivating layer (not shown), which is actually an insulator, typically of a nominal thickness of about 1 micron. In the instant invention, illustrated schematically in FIG. 2, the gate 31 is surrounded by an insulator 33 of a thickness two to ten times the nominal thickness of the passivating layer of FIG. 1. The insulation on the gate 31 is built up to the thickness required to accumulate the desired charges (passivation being applied to the rest of the transistor in the usual fashion). Thus, in FIG. 2, the metal gate 31 is not connected to a signal source, but is biased for operation in either the enhancement or depletion mode, as desired. Charge accumulation within the insulator 33 will change the channel conductivity proportionally. This conductivity may be sampled intermittently to measure the charge accumulation. 
     To prevent discharge of the accumulated charges through the gate bias supply, the gate 31 may be isolated by very-low-leakage blocking diodes. When the sampling interval is over, the gate 31 can be &#34;pulled down&#34; (or &#34;up,&#34; depending on mode) to cause the accumulated charge to discharge, and so begin another sampling interval. In strong fields, the gate 31 can be left floating, so that it has no imposed bias value, but takes on the potential of the charges in the insulator 33 as they accumulate. The mode of operation will be determined by the polarity of the charges on the lower surface of the insulator 33. 
     As the charge accumulates, the gate potential will change from its initial zero value, and source-to-drain conductivity will be modulated by the accumulated charges, to the final value. The metal gate 31 can be reconnected for discharge and for checking of operation and calibration. Thus, in the preferred embodiment, the gate insulator 33 operates as the control structure, serving as a virtual, or dielectric gate. The metallic gate 31 serves only as the sample/reset device. 
     FIG. 3 illustrates a schematic of the preferred embodiment in a sampling mode. FIG. 4 illustrates an equivalent circuit model based on the assumptions |v DS  |≦|v GS  -v T  | and v DS  &lt;0; v GS  &lt;0. The various parameters in these circuits are defined according to the following definitions: 
     v in  ≡voltage (with respect to ground) of floating gate 
     v out  ≡measurable voltage at source (low impedance) 
     v GS  ≡voltage between gate and source 
     v in  =(v out  /A V ) 
     V T  =threshold voltage ##EQU1## r ds  =drain resistance, saturation region R s  =source resistance ##EQU2## v DS  =voltage between drain and source W=channel width 
     L=channel length 
     ε ox  =oxide dielectric constant (permittivity) 
     t ox  =oxide thickness ##EQU3## Q SS  =effective surface-state charge density per unit area Q D  =bulk charge per unit area associated with channel depletion region 
     C=capacitance of the gate to channel per unit area 
     R 2  =Internal resistance of the semiconductor device 
     R 1  =Resistance of the external circuit used in the sampling process 
     In any particular design, the parameters of the device which are not fixed by geometry are set to properly interface the device output to a selected spacecraft system. 
     The MOSFET device of the preferred embodiment (FIG. 2) may be placed inside a larger insulator for the purpose of measuring a high-energy field--or the behavior of an insulating material in that field. Being capable of a high degree of miniaturization, the MOSFET of FIG. 2 can act almost as a point-sized detector for field mapping. The MOSFET can be embedded in the outer surface of a spacecraft, with its gate structure acting as a sample area in the skin, in order to monitor spacecraft surface charge, etc. It can also be set against the inner surface of the skin, to measure particle penetration through the skin. 
     By controlling the types and thicknesses of the gate structures 31, 33, a particle spectrometer can be built by stacking several MOSFETs. FIG. 5 shows a schematic cross-sectional view of one possible arrangement including three MOSFET transistors 41, 43, 45 constructed according to FIG. 2. The top transistor 41 is made with an aluminum gate 47 for trapping low-energy charges. The second MOSFET 43 in the stack uses an iron gate 49, and traps medium-energy particles, while the third MOSFET 45 uses a gold gate 51 for trapping high-energy particles. All gates 47, 49, 51 are allowed to float during sampling. Limited only by the transparency of the substrate and insulators to the particle beam, the stack of FIG. 5 may be provided with a large number of layers and resultant higher resolution. Separate short stacks of devices may be used for the lower-energy end of the spectrum to avoid having too many layers of MOSFETs, which may result in erroneous accumulations in the lower levels. Since each device provides some shielding and thus removes electrons from the beam, stacks may be fabricated with identical layers using the same metals, for finer gradations. 
     As is apparent, the just-described embodiments are subject to numerous modifications and adaptations without departing from the scope and spirit of the invention. Therefore, it is to be understood that, within the scope of the appended claims, the invention may be practiced other than as specifically described herein.