Abstract:
An improved driver for differentially driving a differentially conducting cable (e.g., for Ethernet) minimizes the output offset signal coupled to the cable when the driver is idle. When driven to an idle state, the driver provides a shaped output which transitions to a quiescent output level in a manner which eliminates output signal common mode step change and consequently reduces signal distortion on the cable due to reflection of the step change.

Description:
BACKGROUND OF THE INVENTION 
     The invention relates to communications systems which transfer data between a plurality of nodes all of which are connected to a common conducting cable, particularly a cable that differentially conducts data signals. 
     There is an increasing use of local area network systems for the transfer of information between a plurality of information processing sites. A number of standards have been promulgated by the industry which characterize and define structure and operation of such systems. One such standard is the Ethernet system which ties together a plurality of information nodes on a common databus. An Ethernet node includes a cable-transceiver interface which taps the Ethernet bus and communicates with data terminal terminal equipment through an Ethernet drop cable. Signals are transmitted differentially on the Ethernet drop cable and an Ethernet information node must include a cable driver capable of differentially driving the cable according to the Ethernet specification. 
     One mode of signal transmission on the Ethernet drop cable involves the use of inductive coupling to place a differential signal on the cable. In this mode, when a transmitter is idle, that is when the node is not transmitting, the transmitter output must provide a zero differential in order to minimize the total offset voltage present on the cable. Another specification requires that the waveform provided by a transmitter when it ends an active transmission and transitions to its idle state remain at one level for a minimum period of time and then transition to the zero differential level. 
     One integrated circuit family that is easily adapted to the differential transmission requirements of the Ethernet standard is the ECL family. An ECL driver characteristically responds to an input which can be driven differentially to produce a differential output. One problem with using an ECL driver to interface a node with an Ethernet transmission cable is that its open loop voltage gain is high, typically in the range of 20-30, which tends to amplify input and internal parametric offset voltages. 
     Further, the conventional ECL circuitry involved in meeting the active-to-idle transition requirement changes the output voltage abruptly, resulting in a common mode step change in the differential outputs which is propagated and reflected in the Ethernet cable. 
     The present invention is used to advantage as an Ethernet driver. It employs a minimum of internal circuitry to perform the dual function of minimizing the output offset voltage during the idle state and meeting the transition requirement without introducing an output common mode step change into the cable. 
     SUMMARY OF THE INVENTION 
     The present invention is directed to a data network driver for transmitting data signals on a differentially-conducting cable, such as an Ethernet drop cable. The driver includes a differentially-driven input section that responds to a data signal to be transmitted by providing a differential transmission driving signal representative of the data signal. 
     The driver also includes an idle circuit coupled to the input circuit for selectively disabling the circuit from providing a transmission driving signal while, at the same time, providing an idle signal of adjustable characteristics. 
     Both the input and idle circuits are coupled to an output circuit having an output port connected to the differentially-conducting cable and responsive to a driving signal for providing a differential data signal through the port. The output circuit further responds to the idle signal by providing, through the output port, a quiescent signal whose characteristics are dependent upon the characteristics of the idle signal. 
     Finally the driver includes an adjustment circuit coupled to the output port and to the idle circuit for measuring the difference between respective characteristics of the quiescent and differential data signals and for, based upon the measurement, adjusting the characteristics of the idle signal. 
     Therefore it is a primary object of the present invention to provide an improved data network driver for transmitting data signals on a differentially-conducting cable. 
     It is a further object of present invention to provide such a driver which couples a minimum output offset voltage onto the cable when the driver is idle. 
     It is yet another object of the invention to provide such a driver whose output grandually transitions, at the end of a data transmission, to a predetermined quiescent state. 
     Other objects and advantages of the present invention will become more evident when the following detailed description is read in conjunction with the described drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a waveform which represents selected characteristics required of an Ethernet cable driver. 
     FIG. 2 is a block diagram which shows a driver of the invention in a representative operational environment. 
     FIG. 3 is a detailed circuit diagram illustrating the data network driver of the invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     A driver which is useful to provide the transmitting interface for a differentially-driven communications system such as Ethernet is described. Although references are made to specific requirements of the Ethernet system which are satisfied by the described driver, it should be evident that the driver can be used to place a differential signal on any differentially-driven communications cable with a minimum of output offset when the driver is idling and without coupling a common mode step change onto the cable when the driver becomes active. Therefore, it is to be understood that the quantities which below characterize the operation of the invention are merely for purposes of illustration, and are not intended to limit its use or application. 
     Referring now to FIG. 1, there is illustrated an idealized differential waveform which represents certain characteristics required of the output of a driver which is inductively coupled to an Ethernet system. The output waveform provided by the driver is a differential one and transitions between a positive voltage state signified by &#34;+&#34; and a negative state signified by &#34;-&#34;. The average level is positioned between the two states and has a zero voltage level signified in the figure by &#34;0&#34;. At the end of a data transmission, the output waveform transitions at waveform edge 10 to an active-to-idle transition state where the output wave form must remain at the + level for at least 200 nanoseconds before transitioning to the zero differential level midway between the + and - levels. Because the driver is inductively coupled, it is recognized that there will be an undershoot when the waveform transitions to the quiescent level, however, the undershoot must be no greater than 100 millivolts. Finally, while the driver is in the idle state it must provide an output offset voltage of no greater than 40 millivolts. 
     The typical system environment in which the driver&#39;s specifications illustrated in FIG. 1 obtain is illustrated in FIG. 2. Typically, the Ethernet system involves a plurality of nodes through which data is exchanged with the system. One such node is illustrated in FIG. 2 and includes a node control interface 12 which accepts parallel digital data, formats it, and provides it serially to a node encoder-decoder (ENDEC) 14 through an input node 15. ENDEC encodes data signals into a differential digital format. In the FIG. 2 example, the ENDEC 14 interfaces with the driver 16 of the invention by providing the encoded data signals as an input to the driver. The driver 16 responds to the input encoded data signals by providing a differential output signal to an inductive coupler 18, which differentially couples the output signal of the driver to a differentially-conducting drop cable 20. The signals are conducted over the drop cable to a transceiver which couples them into the Ethernet data bus cable. 
     In order to signal the end of the data transmission and the beginning of the idle state, Ethernet control interface 12 provides a negative-logic idle data signal (IDS) through an idle port 22 to the driver 16. The driver 16 responds to IDS by providing an output voltage waveform which follows the active-to idle transition to the quiescent output level as illustrated by the waveform of FIG. 1. 
     The driver 16 of the invention can be understood with reference to FIG. 3. The driver receives the encoded data signals through the input port 15 which includes a pair of nodes A and A&#39; that receive the encoded differential data signals which are to be transmitted on the system drop cable 20. Node A is connected to the base of a transistor Q 1 , while the node A&#39; is connected to the base of a transistor Q 2 . The emitters of Q 1  and Q 2  are connected in common to a conventional constant current source 30 which provides a constant current I 1 . The collectors of Q 1  and Q 2  are connected to the bases of emitter followers Q 3  and Q 4 , respectively. The collector of Q 1  is further connected at a node 1 to one side of a resistor R 2 , the other side of which is connected through a diode D 1  to a positive source of DC voltage V cc . Similarly, the collector of Q 2  is further connected at a node 2 to one side of a resistor R 3  that is connected at its other side to the cathode of diode D 1  in common with the resistor R2. 
     The transistors Q 3  and Q 4  are conventional emitter followers whose collectors are connected through diodes D 2  and D 3 , respectively, to V cc . The output signal of the driver 16 is developed between the nodes 0&#39; and 0 connected to the emitters of Q 3  and Q 4 , respectively. The + portion of the output signal is developed at node 0 by the resistor R 4  which is connected between the nodes 0 and ground. The - portion of the output signal is developed across R 7 , connected between node 0&#39; and ground. 
     The coupler 18 which is connected across the nodes 0 and 0&#39; of the output port 17 is represented by an inductance L 1  and a resistance R 1 . 
     The idle section of the driver 16 includes a pair of transistors Q 5  and Q 6  connected in conventional coupled-emitter configuration between node 1 and node 2, respectively, and the current source 30. The base of Q 5  is connected through a node 3 and a resister R 9  to the collector of a transistor Q 7 . Similarly, the base of Q 6  is connected through a node 4 and a resistor R 6  to Q 7  &#39;s collector. Also connected to the collector of Q 7  are a capacitor C 1  and another constant current source 32 providing a current I 2 . The base of Q 7  is connected through a resistor R 10  to the idle port 22 through which IDS is provided to the driver 16. The emitter of Q 7  is connected to ground. 
     A quiescent output offset adjustment circuit provided in the driver 16 includes a pair of feedback resistors R 5  and R 6  connected in series between output node 0 and one side of the capacitor C 1 . The adjustment circuit further includes a pair of resistors R 8  and R 9  connected in series between the other output node O&#39; and the other side of the capacitor C 1 . A feedback signal is obtained at node 4 between R 5  and R 6  which is connected to the base of Q 6 . Another feedback signal is obtained at node 3 between R 8  and R 9  which is fed to the base Q 5 . 
     During normal operation, when encoded data signals (which can comprise a pair of complementary logic signals) are provided to the driver 16 for transmission onto drop cable 20, the signals operate Q 1  and Q 2 . The positive portion of the input differential data signal is provided at node A of the input port 15 and drives the transistor Q 1 . The negative portion of the differential encoded data signal is provided node A&#39; and drives the transistor Q 2 . At the same time that the differentially-coded data signal is provided at the input port 15 of the driver, IDS is deactivated, placing it in a positive logic voltage level and turning on Q 7 . When operating, Q 7  diverts the current I 2  to ground. Further, Q 7  discharges the capacitor C 1  and keeps the bases of Q 5  and Q 6  at a low voltage level, which keeps the transistors Q 5  and Q 6  turned off. 
     Therefore, while the driver 16 is employed to transmit data signals provided at the input port 15, the transistors Q 1  and Q 2  are driven in a conventional differential fashion, with the current I 1  being switched to the transistor that is currently turned on. The differential action of Q 1  and Q 2   develops a differential driving signal between nodes 1 and 2 which drives the emitter followers Q 3  and Q 4  in conventional differential fashion. For example, when the signal provided at the port 15 exhibits transition to a positive level, the voltage level at node A rises while that at A&#39; drops and I 1  is diverted through Q 1 . This causes the voltage at node 2 to rise relative to that at node 1, resulting in a higher voltage at node 0 than at node 0&#39;. The voltage difference between the nodes 0 and 0&#39; develops a voltage potential across the parallel combination of L 1  and R 1  which is coupled conventionally into the drop cable 20 with a polarity determined by the higher voltage at output node 0 and the lower voltage at the node 0&#39;. Conversely, when the polarities of the signals at the input node 15 invert, the process described above reverses and reverses the polarity between the nodes 0 and 0&#39;. In this manner, the drop cable 20 is differentially driven through the output port 17 by the input signals applied to the input port 15. 
     When the node control interface 12 terminates data transmission, it provides the idle signal IDS to the input node 22 which will cause the driver 16 to place a positive-polarity constant-voltage signal, such as is represented by section 40 of the FIG. 1 waveform, on the drop cable 20. At this time, the waveform of FIG. 1 changes, at transition 10, to the level 40, and the driver returns to the idle state. The low active level of IDS turns Q 7  off. With Q 7  off, the current I 2  charges the capacitor C 1  at a rate of I 2  /C 1  (volts/second). The potential at nodes 3 and 4 rises at the rate with which the capacitor C 1  charges. When the potential at these nodes exceeds the level of the input signal at the port 15, Q 5  and Q 6  turn on. Q 5  and Q 6  assume substantially identical operating points and so divide I 1  evenly between themselves so that I 1  /2 flows through each transistor. The equal operating levels of Q 5  and Q 6  causes the nodes 1 and 2 to assume substantially equal voltage levels, thereby biasing the emitter followers Q 3  and Q 4  equally. In the preferred embodiment, R 4  and R 7  have equal resistance values so that the currents flowing through Q 3  and Q 4  are equal as are the voltages developed at the output nodes O and O&#39;. 
     Since, in the idle state, the output nodes O and O&#39; are at equal potentials, a zero potential is developed across the coupler and the output voltage signal coupled through the port 17 to the cable 20 assumes the 0 voltage level, midway between the maximum + and - levels of the FIG. 1 waveform. However, because of the mismatches in the transistor pairs Q 5  -Q 6  and Q 3  -Q 4  and the resistor pairs R 2  -R 3  and R 4  -R 7 , the voltages developed at the output nodes O and O&#39; are unequal and an output offset voltage is developed. The objective of the Ethernet spcification is to keep this offset voltage below a standard maximum level which, in FIG. 1 is numeral 40 millivolts. Since there is a voltage gain G from the transistor pair Q 5  -Q 6  to the output port, then the input offset developed in the respective circuits of that transistor pair must be kept well below 40/G. Since, a typical value for G is 23, then the voltage offset between nodes 3 and 4 must be kept well below two millivolts. 
     The output offset adjustment circuit comprising the resistors R 5  -R 6  and R 8  -R 9  measures the output offset voltage and develops a differential feedback voltage having a polarity which tends to force the output offset voltage toward the zero voltage level. For example, if the voltage at output node 0 exceeds that at the output node 0&#39;, an incremental feedback voltage ΔV f  having a value given by equation (1) is fed to the base of Q 6 . ##EQU1## where ΔV 0  =the incremental voltage change at node 0. 
     This increases the bias level at the base of Q 6 , turning it on harder relative to Q 5  and lowering the voltage potential at node 2. The lower potential at node 2 relative to that at node 1 causes Q 3  to conduct forward current at a level proportionately less than that conducted by Q 4 , which causes the voltage at the output node O to fall relative to that at node O&#39;, thus reducing the differential between them and the output voltage offset level. 
     Obviously, many modifications and variations of the described invention are possible in light of the above teachings, and it is therefore understood that the invention may be practiced otherwise than as it has been specifically described.