Abstract:
An integrated circuit includes a semiconductor substrate, a silicon layer, a buried isolating layer arranged between the substrate and the layer, a bipolar transistor comprising a collector and emitter having a first doping, and a base and a base contact having a second doping, the base forming a junction with the collector and emitter, the collector, emitter, base contact, and the base being coplanar, a well having the second doping and plumb with the collector, emitter, base contact and base, the well separating the collector, emitter and base contact from the substrate, having the second doping and extending between the base contact and base, a isolating trench plumb with the base and extending beyond the layer but without reaching a bottom of the emitter and collector, and another isolating trench arranged between the base contact, collector, and emitter, the trench extending beyond the buried layer into the well.

Description:
RELATED APPLICATIONS 
       [0001]    Under 35 USC 119, this application claims the benefit of the priority date of French Application No. 1256806, filed on Jul. 13, 2012, the contents of which are herein incorporated by reference. 
       FIELD OF INVENTION 
       [0002]    The invention relates to integrated circuits, and in particular the integrated circuits produced on a substrate of silicon on insulator (SOI) type. SOI technology consists in separating a thin layer of silicon (a few nanometres) on a substrate of silicon with a relatively thick layer of insulator (a few tens of nanometres as a general rule). 
       BACKGROUND 
       [0003]    The integrated circuits produced in SOI technology offer a certain number of advantages. Such circuits generally exhibit a lower electrical consumption for equivalent performance levels. Such circuits also induce lower stray capacitances, so that the switching speed can be improved. Furthermore, the stray triggering (“latchup”) phenomenon encountered with MOS transistors in bulk technology can be avoided. Such circuits therefore prove particularly suited to applications of SoC or MEMS type. It is also found that the SOI integrated circuits are less sensitive to the effects of ionizing radiation and thus prove more reliable in applications where such radiations can induce operating problems, notably in space applications. The SOI integrated circuits may notably include random access memories of SRAM type or logic gates. 
         [0004]    Reducing the steady-state consumption of logic gates while increasing their switching speed is the subject of a great deal of research. Some integrated circuits being developed incorporate both logic gates with low consumption and logic gates with high switching speed. To generate these two types of logic gates on one and the same integrated circuit, the threshold voltage of certain transistors of the fast-access logic gates is lowered, and the threshold voltage of other transistors of the logic gates with low consumption is increased. In bulk technology, the modulation of the threshold voltage level of transistors of the same type is performed by differentiating the level of doping of their channel. However, in FDSOI (“Fully Depleted Silicon On Insulator”) technology, the doping of the channel is almost zero (10 15  cm −3 ). Thus, the level of doping of the channel of the transistors cannot therefore exhibit significant variations, which prevents the threshold voltages from being differentiated in this way. One solution proposed in certain studies for producing transistors of the same type with distinct threshold voltages is to incorporate different gate materials for these transistors. However, the practical production of such an integrated circuit proves technically difficult and economically prohibitive. 
       SUMMARY OF THE INVENTION 
       [0005]    In order to have distinct threshold voltages for different transistors in FDSOI technology, it is also known practice to use a biased ground plane arranged between the thin layer of insulating oxide and the silicon substrate. By acting on the doping of the ground planes and on their bias, a range of threshold voltages can be defined for the different transistors. It will thus be possible to have so-called low threshold voltage transistors LVT, so-called high threshold voltage transistors HVT and so-called average, or “standard”, threshold voltage transistors SVT. 
         [0006]    To enable the different transistors to operate, it is necessary to electrically isolate them from one another. Consequently, the transistors are generally surrounded by the isolating trenches (referred to by the acronym STI, for “Shallow Trench Isolation”) which extend to the wells. 
         [0007]    As is known, such integrated circuits also include devices protecting against accidental electrostatic discharges (ESD) that can damage these transistors. 
         [0008]    There is a need for protection against the electrostatic discharges that does not impact on the compactness of the integrated circuit, that is capable of removing a localized discharge regardless of its bias, and that is inexpensive. The invention thus relates to an integrated circuit as defined in the appended claims. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    Other features and advantages of the invention will emerge clearly from the description which is given thereof hereinbelow, as an indication and in a nonlimiting manner, with reference to the appended drawings, in which: 
           [0010]      FIG. 1  is a schematic plan view of a portion of integrated circuit at the ground planes level of a bipolar transistor according to a first variant; 
           [0011]      FIG. 2  is a transversal cross-sectional view of the bipolar transistor illustrated in  FIG. 1 ; 
           [0012]      FIG. 3  is a transversal cross-sectional view of a bipolar transistor according to a second variant; 
           [0013]      FIG. 4  is a transversal cross-sectional view of a bipolar transistor according to a third variant; 
           [0014]      FIG. 5  is a transversal cross-sectional view of a bipolar transistor according to a fourth variant; 
           [0015]      FIG. 6  is a transversal cross-sectional view of a bipolar transistor according to a fifth variant; 
           [0016]      FIG. 7  is a transversal cross-sectional view of a bipolar transistor according to a sixth variant; 
           [0017]      FIG. 8  is a transversal cross-sectional view of an example of bipolar transistor attached to a field-effect transistor; 
           [0018]      FIG. 9  is a transversal cross-sectional view of another example of bipolar transistor attached to a field-effect transistor. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0019]    The invention proposes using, in an integrated circuit of SOI type, isolating trenches of different depths and dimensions in order to produce bipolar transistors. 
         [0020]      FIG. 1  is a schematic plan view of a portion of an integrated circuit of SOI type. The integrated circuit here comprises a bipolar transistor  3 . The bipolar transistor  3  is illustrated in transversal cross section in  FIG. 2 . The integrated circuit comprises other electronic components formed on a buried isolating layer, not illustrated here. 
         [0021]    The transistor  3  is formed plumb with a semiconductor substrate  91 . This substrate  91  has a p-type doping. The transistor  3  here is of pnp type. The transistor  3  comprises a collector  31 , an emitter  32  and a base contact  33 . The collector  31  includes a semiconductor element with p-type doping, the emitter  32  comprises a semiconductor element with p-type doping, and the base contact  33  comprises a semiconductor element with n-type doping. A semiconductor element with n-type doping forms:
   on the one hand, a well  34  plumb with the collector  31 , the emitter  32  and the base contact  33 ;   on the other hand, a base  35  forming a junction between the collector  31  and the emitter  32 .   
 
         [0024]    The collector  31 , the emitter  32  and the base contact  33  here include implanted areas formed above the well  34 . The implanted areas advantageously have respective dopings P+, P+and N+. The base  35  and the implanted areas of the collector  31 , of the emitter  32  and of the base contact  33  are here coplanar. The term “coplanar” should be understood to mean that it is possible to define a plane passing through the areas concerned and parallel to the buried isolating layer detailed hereinbelow. The collector  31 , the emitter  32  and the base contact  33  are connected respectively to potentials Ec, Ee and Eb. A bipolar transistor  3  is thus formed in which the base contact is laterally offset relative to the collector and to the emitter. 
         [0025]    At its periphery, the transistor  3  comprises an isolating trench  44  extending depthwise to the well  34 . The transistor  3  here comprises, also at its periphery, an isolating trench  41  extending depthwise to the well  34 . The transistor  3  also comprises an isolating trench  43  extending depthwise to the well  34 . The isolating trench  43  separates or is interposed between the emitter  32  and the base contact  33 . The isolating trench  43  does not extend to the substrate  91 . Thus, the well  34  forms a continuous semiconductor element between the base contact  33  and the base  35 . The base  35 , for example, is formed in continuity with the semiconductor element in which the well  34  is formed. The isolating trenches  41  and  44  do not extend to the substrate  91 . 
         [0026]    The transistor  3  also comprises an isolating trench  42  formed plumb with the base  35 . The trench  42  preferably has a width of at least 40 nm for a 20 nm technological node. The isolating trench  42  extends into the base  35 , beyond the top face of the collector  31  and of the emitter  32 . The isolating trench  42  extends, for example, between 5 and 50 nm below the top surface of the collector  31  or of the emitter  32 . The isolating trench  42  may also extend between 5 and 50 nm below the buried isolating layer of the integrated circuit for a transistor  3  of FDSOI type. The bottom of the buried isolating layer is here at the level of the top surface of the collector  31 , of the emitter  32  and of the base contact  33 . The isolating trench  42  does not, however, extend to the interface between the well  34  and the collector  31  or the emitter  32 . The isolating trench  42  is shallower than the isolating trenches  43  and  44 . 
         [0027]    Thus, a bipolar transistor  3  is obtained for which the properties of the base  35  are particularly well controlled during the fabrication process. Moreover, for a use of the transistor  3  in protecting the integrated circuit against electrostatic discharges, such a transistor greatly limits the occurrence of an overcurrent by the snapback phenomenon. The use of an isolating trench  43  that is deeper than the isolating trench  42  makes it possible to increase the triggering sensitivity of the protection to limit the overcurrent induced in the transistor  3  when it is passed through by an electrostatic discharge. 
         [0028]    The well  34  may have a concentration of dopants of between 10 16  cm −3  and 10 18  cm −3 . The well  34  may extend to a depth less than 1 μm and, preferably, less than or equal to 700 nm. 
         [0029]    Advantageously, the implanted areas of the collector  31 , of the emitter  32  and of the base contact  33  each exhibit a concentration of dopants at least fifty times, or a hundred times greater than the concentration of dopants of the well  34 . For example, these implanted areas have concentrations of dopants advantageously greater than or equal to 5*10 18  cm −3  and, preferably, between 10 19  cm −3  and 10 21  cm −3 . 
         [0030]      FIG. 3  is a transversal cross-sectional view of a variant bipolar transistor  300  of the integrated circuit. 
         [0031]    The transistor  300  here is of npn type. The transistor  300  has a structure identical to that of  FIG. 2  and is differentiated therefrom by the types of doping used. Thus, the collector  31  includes a semiconductor element with n-type doping, the emitter  32  comprises a semiconductor element with n-type doping, and the base contact  33  comprises a semiconductor element with p-type doping. A semiconductor element with p-type doping forms: 
         [0032]    on the one hand, the well  34  plumb with the collector  31 , the emitter  32  and the base contact  33 ; 
         [0033]    on the other hand, the base  35  between the collector  31  and the emitter  32 . 
         [0034]    The base  35  and the implanted areas of the collector  31 , of the emitter  32  and of the base contact  33  are here coplanar. 
         [0035]      FIG. 4  is a transversal cross-sectional view of another variant bipolar transistor  301  of the integrated circuit. The transistor  301  is here of pnp type. The transistor  301  has trenches  41 ,  43  and  44  similar to those of the transistor of  FIG. 2 . The collector  31 , the emitter  32 , the base contact  33  and the well  34  of the transistor  301  of  FIG. 4  have a structure and a doping that are identical to those of the transistor of  FIG. 3 . The isolating trench  42  here has a width greater than the width of the trench  42  of the transistor of  FIG. 2 . The isolating trench  421  has the same depth as the trench  42  of the transistor of  FIG. 2 . The trench  421  is here formed plumb with a semiconductor element  36  and the base  35 . The semiconductor element  36  is interposed in contact with the collector  31  and the base  35 . The semiconductor element  36  forms an extension of the collector  31  under the isolating trench  421 . The trench  421  preferably has a width of at least 80 nm for a 20 nm technological node. The semiconductor element  36  comprises a p-type doping and is in contact with the collector  31 . The semiconductor element  36  advantageously comprises a width at least equal to 40 nm for a 20 nm technological node. 
         [0036]    The semiconductor element  36 , the base  35  and the implanted areas of the collector  31 , of the emitter  32  and of the base contact  33  are here coplanar. The addition of the semiconductor element  36  makes it possible to increase the base/emitter breakdown voltage of the transistor  301 . 
         [0037]      FIG. 5  is a transversal cross-sectional view of a variant bipolar transistor  302  of the integrated circuit. The transistor  302  is here of npn type. The transistor  302  has a structure identical to that of  FIG. 4  and is differentiated therefrom by the types of doping used. Thus, the collector  31  includes a semiconductor element with n-type doping, the emitter  32  comprises a semiconductor element with n-type doping, and the base contact  33  comprises a semiconductor element with p-type doping. The semiconductor element  36  comprises an n-type doping. A semiconductor element with p-type doping forms: 
         [0038]    on the one hand, the well  34  plumb with the collector  31 , the emitter  32  and the base contact  33 ; 
         [0039]    on the other hand, the base  35  between the semiconductor element  36  and the emitter  32 . 
         [0040]    The semiconductor element  36 , the base  35  and the implanted areas of the collector  31 , of the emitter  32  and of the base contact  33  are here coplanar. 
         [0041]      FIG. 6  is a transversal cross-sectional view of another variant bipolar transistor  303  of the integrated circuit. The transistor  303  is identical to that of Figure  2  apart from the structure of the collector  31 , of the emitter  32 , and of the base contact  33 . In this example, by means of an epitaxial regrowth, a collector  31 , an emitter  32 , and a base contact  33  have been produced that are flush with the top surface of the isolating trenches  41  to  44 . Consequently, the top surface of the collector  31 , of the emitter  32 , and of the base contact  33  is arranged above the bottom of the buried isolating layer for a transistor  303  of FDSOI type. 
         [0042]      FIG. 7  is a transversal cross-sectional view of another variant of a bipolar transistor  304  of the integrated circuit. The transistor  304  is identical to that of  FIG. 4  apart from the structure of the collector  31 , of the emitter  32 , and of the base contact  33 . In this example, by means of an epitaxial regrowth, a collector  31 , an emitter  32 , and a base contact  33  have been produced that are flush with the top surface of the isolating trenches  41  to  44 . Consequently, the top surface of the collector  31 , of the emitter  32 , and of the base contact  33  is arranged above the bottom of the buried isolating layer for a transistor  304  of FDSOI type. 
         [0043]    In the example of  FIG. 8 , the bipolar transistor  3  is attached to a field-effect transistor  1 . The transistor  1  is, for example, an nMOS or pMOS transistor. The transistor  1  comprises, as is known per se, a source, a drain and a channel, and a gate stack plumb with the channel. The source, the drain and the channel of the transistor  1  are formed in the active semiconductor layer  15 . The transistor  1  comprises a gate stack  16  arranged over the active semi-conductor layer  15 , plumb with the channel. To simplify the drawings, the detailed structure of the active layers is not represented therein. The transistor  1  can be of FDSOI type and comprise, as is known per se, a channel of weakly doped semiconductor material, with a concentration of dopants substantially equal to the concentration of dopants of the substrate  91 . The transistor  1  also comprises source and drain electrodes, which are not illustrated. 
         [0044]    The transistor  1  is formed plumb with a buried isolating layer  92 . The buried isolating layer  92 , as is known per se, electrically isolates the transistor  1  from its ground plane  11 , from its well  34 , and from the substrate  91 . 
         [0045]    A semiconductor ground plane  11  is formed plumb with the transistor  1 , under the buried isolating layer  92 . The doping of the ground plane  11  is here of the same type as the doping of the collector  31 , that is to say of p-type. The implanted area of the collector  31  is in contact with the ground plane  11 . The ground plane  11  is therefore biased to the potential Ec. The biasing of the ground plane  11  can be done via a control circuit that is not represented here. The well  34  extends laterally to plumb with the ground plane  11 . 
         [0046]    The buried isolating layer  92  formed plumb with the transistor  1  is here of UTBOX (“Ultra-Thin Buried Oxide”) layer type. Thus, controlling the biasing of the ground plane  11  makes it possible to modulate the threshold voltage of the transistor  1 . The isolating layer  92  has, for example, a thickness less than or equal to 60 nm, less than or equal to 50 nm, even less than or equal to 20 nm. The isolating layer  92  can be produced, as is known per se, in silicon oxide. 
         [0047]    An isolating trench  45  is formed at the periphery of the transistor  1 . The isolating trench  45  extends through the buried isolating layer  92 , to the well  34 . The isolating trench  45  advantageously has a depth identical to the isolating trenches  43  and  44 . 
         [0048]    The isolating trench  41  is here formed plumb with the contact between the ground plane  11  and the implanted area of the collector  31 . The isolating trench  41  extends through the buried isolating layer  92 . The isolating trench  41  does not extend to the well  34  or to the bottom of the collector  31 , in order to allow a contact between the collector  31  and the ground plane  11 . The isolating trench  41  advantageously has the same depth as the isolating trench  42 . 
         [0049]    The ground plane  11  may have a concentration of dopants of between 10 18  cm −3  and 10 19  cm −3 . The concentrations of dopants of the implanted areas of the collector  31 , of the emitter  32  and of the base contact  33  are, for example, substantially equal to the concentrations of dopants of the source or of the drain of the transistor  1 . Metallic contacts can be deposited after siliconizing directly on each of the implanted areas of the collector  31 , of the emitter  32  and of the base contact  33 , in order to allow for an electrical connection for each of them. 
         [0050]    The bipolar transistor  3  can be used in combination with the field-effect transistor  1 . The transistor  3  can, for example, be used to protect the transistor  1  against electrostatic discharges, or be controlled by the transistor  1  to close in the presence of an electrostatic discharge. The combination of transistors  1  and  3  entails only a small reduction in the integration density: 
         [0051]    the collector  31  of the bipolar transistor  3  is also  30  used to bias the ground plane  11 ; 
         [0052]    the emitter  32  of the bipolar transistor  3  is also used to bias the well  34  plumb with the transistor  1 . 
         [0053]      FIG. 9  illustrates another exemplary bipolar transistor  3  attached to a field-effect transistor  1 . This example differs from that of  FIG. 8  only by the use of a bipolar transistor  3  as defined with reference to  FIG. 4 . In this example, the transistor  3  advantageously provides the transistor  1  with increased protection against the electrostatic discharges by virtue of a higher base/collector breakdown voltage. The triggering threshold of the transistor  3  is here raised, which is useful in particular for a use with high voltage levels. 
         [0054]    Obviously, the bipolar transistors of  FIGS. 6 and 7  may be attached to a field-effect transistor.