Abstract:
There is provided a method of fabricating an EEPROM for forming a memory cell transistor and a selection transistor, the method includes: forming a first source region and a first drain region of the memory cell transistor; forming a first gate oxide film; forming a resist having at least one through hole on the first gate oxide film; adding conductivity type impurities through the through hole; partially removing the first gate oxide film and forming a tunnel oxide film in a region corresponding to the through hole; forming a floating gate electrode and a second gate oxide film formed on the floating gate electrode; forming a control gate electrode and a selection transistor gate electrode on the second gate oxide film and at a region in which the selection transistor is formed; and forming a second source region and a second drain region of the selection cell transistor.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is based on and claims priority under 35 USC 119 from Japanese Patent Application No. 2008-210693 filed on Aug. 19, 2008, the disclosure of which is incorporated by reference herein. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    The present invention relates to a method of fabricating an EEPROM as a non-volatile semiconductor memory which can electrically write and erase data. 
         [0004]    2. Related Art 
         [0005]    When battery power is insufficient in portable mobile electronic equipments represented by a mobile phone, PDA (personal digital assistant: mobile information terminal), a notebook type computer, and a music player, they rely on a non-volatile semiconductor memory to hold data and a program. As ordinary non-volatile semiconductor memories, there are known an ultra-violet erasable EPROM (Ultra-Violet Erasable Programmable Read Only Memory) which can erase stored contents by radiating ultraviolet rays and an EEPROM (Electrically Erasable Programmable Read Only Memory) which can electrically write and erase data. 
         [0006]    As shown in  FIG. 4 , the EEPROM ordinarily has such a structure such that a memory cell transistor  102  and a selection transistor  103  are formed on a Si substrate  101 . The memory cell transistor  102  is composed of diffusion layers  104 ,  105 , gate oxide films  106   a ,  106   b , a tunnel oxide film  107 , a floating gate electrode  108 , and a control gate electrode  109 . In the configuration, the diffusion layer  104  acts as a source and the diffusion layer  105  acts as a drain. The selection transistor  103  is composed of the diffusion layer  105 , a diffusion layer  110 , a gate oxide film  111 , and a gate electrode  112 . In the configuration, the diffusion layer  105  acts as a source and the diffusion layer  110  acts as a drain. 
         [0007]    In fabricating the EEPROM  100  configured as described above, a problem arises in that it is difficult to miniaturize the EEPROM  100  because an allowance must be provided in design taking an alignment offset in photolithography into consideration because the tunnel oxide film  107  is formed on the diffusion layer  105 . A method of solving the problem is disclosed in Japanese Patent Application Laid-Open (JP-A) No. 2001-210730. 
         [0008]    As to formation of a tunnel oxide film to an EEPROM, JP-A No. 2001-210730 discloses to form a resist having a through hole for exposing a forming region on a semiconductor substrate through the through hole, to add conductive impurities to the substrate through the through hole, and thereafter to form the tunnel oxide film to the forming region by removing the resist. The method makes it unnecessary to adjust a tunnel oxide film forming region in alignment with a predetermined position of a diffusion layer which is previously formed on a semiconductor substrate as in a conventional method. 
         [0009]    However, in the method of fabricating the EEPROM disclosed in JP-A No. 2001-210730, a source region of a memory cell is only formed just under the tunnel oxide film, and the source region of the memory cell is not connected to a source region of a selection transistor by a diffusion region having a high impurity concentration. Further, since the source region of the memory cell is formed after a control gate is formed, there is a possibility that it cannot be accurately formed at a desired position. 
       SUMMARY 
       [0010]    An object of the present invention, which was made in view of the above circumstances, is to provide a method of fabricating an EEPROM in which a memory cell transistor is securely connected to a selection transistor by a diffusion region having a high impurity concentration. 
         [0011]    To solve the problems described above, one aspect of the present invention provides a method of fabricating, on a semiconductor substrate, an EEPROM for forming a memory cell transistor and a selection transistor that is a component of the memory cell transistor and the EEPROM, the method including: 
         [0012]    forming a first source region and a first drain region of the memory cell transistor on the semiconductor substrate; 
         [0013]    forming a first gate oxide film on the semiconductor substrate; 
         [0014]    forming a resist having at least one through hole on the first gate oxide film formed on the first drain region; 
         [0015]    adding conductivity type impurities to the semiconductor substrate, on which the resist is formed, through the through hole; 
         [0016]    partially removing the first gate oxide film using the resist and forming a tunnel oxide film in a region corresponding to the through hole; 
         [0017]    forming a floating gate electrode, which covers the tunnel oxide film and parts of the first source region and the first drain region, and a second gate oxide film formed on the floating gate electrode; 
         [0018]    forming a control gate electrode and a selection transistor gate electrode on the second gate oxide film and at a region in which the selection transistor is formed; and 
         [0019]    forming a second source region and a second drain region of the selection cell transistor on the semiconductor substrate, 
         [0020]    wherein the first drain region is connected to the second source region by partial overlapping. 
         [0021]    Further, to solve the problems described above, another aspect of the present invention provides a method of fabricating, on a semiconductor substrate, an EEPROM for forming a memory cell transistor and a selection transistor that is a component of the memory cell transistor and the EEPROM, the method including: 
         [0022]    forming a first source region and a first drain region of the memory cell transistor on the semiconductor substrate; 
         [0023]    forming a first gate oxide film on the semiconductor substrate; 
         [0024]    forming a resist having at least one through hole on the first gate oxide film formed on the first drain region; 
         [0025]    adding conductivity type impurities to the semiconductor substrate, on which the resist is formed, through the through hole; 
         [0026]    forming a tunnel oxide film by partially adjusting the first gate oxide film to a predetermined thickness using the resist; 
         [0027]    forming a floating gate electrode, which covers the tunnel oxide film and parts of the first source region and the first drain region, and a second gate oxide film formed on the floating gate electrode; 
         [0028]    forming a control gate electrode and a selection cell transistor gate electrode on the second gate oxide film and at a region in which the selection transistor is formed; and 
         [0029]    forming a second source region and a second drain region of the selection transistor on the semiconductor substrate, 
         [0030]    wherein the first drain region is connected to the second source region by partial overlapping. 
         [0031]    After source and drain regions of the memory cell transistor are formed on the semiconductor substrate and gate electrode structures of the memory cell transistor and the selection transistor are formed on the semiconductor substrate, a source region of the selection transistor is formed by being partially overlapped with the drain region of the memory cell transistor. As a result, there is provided a method of fabricating an EEPROM in which the memory cell transistor is securely connected to the selection transistor by a diffusion region having a high impurity concentration. 
         [0032]    Still further aspect of the present invention provides a method of fabricating, on a semiconductor substrate, an EEPROM for forming a memory cell transistor and a selection transistor that is a component of the memory cell transistor and the EEPROM, the method including: 
         [0033]    forming a first source region and a first drain region of the memory cell transistor on the semiconductor substrate; 
         [0034]    forming a first gate oxide film on the semiconductor substrate; 
         [0035]    forming a resist having at least one through hole on the first gate oxide film formed on the first drain region; 
         [0036]    adding conductivity type impurities to the semiconductor substrate, on which the resist is formed, through the through hole; 
         [0037]    forming a tunnel oxide film at the bottom of an opening in the through hole; 
         [0038]    forming a floating gate electrode, which covers the tunnel oxide film and parts of the first source region and the first drain region, and a second gate oxide film formed on the floating gate electrode; 
         [0039]    forming a control gate electrode and a selection transistor gate electrode on the second gate oxide film and at a region in which the selection transistor is formed; and 
         [0040]    forming a second source region and a second drain region of the selection cell transistor on the semiconductor substrate, 
         [0041]    wherein the first drain region is connected to the second source region by partial overlapping. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0042]    Exemplary embodiment of the present invention will be described in detail based on the following figures, wherein: 
           [0043]      FIG. 1  is a sectional view of an EEPROM fabricated by a method of fabricating the EEPROM as a first embodiment of the present invention; 
           [0044]      FIGS. 2A to 2K  are sectional views of the EEPROM at respective steps of the method of fabricating the EEPROM as the first embodiment of the invention; 
           [0045]      FIGS. 3A to 3C  are sectional views showing a method of adding conductivity type impurities in the method of fabricating the EEPROM as the first embodiment of the invention; and 
           [0046]      FIG. 4  is a sectional view of a conventional EEPROM. 
       
    
    
     DETAILED DESCRIPTION 
       [0047]    An embodiment of the present invention will be explained below in detail referring to the accompanying drawings below. 
         [0048]    First, a structure of an EEPROM fabricated by a method of fabricating the EEPROM of the embodiment of the invention will be explained in detail referring to  FIG. 1 . 
         [0049]    As shown in  FIG. 1 , a memory cell transistor  12  and a selection transistor  13  are formed on a Si substrate  11  as a P-type semiconductor substrate. 
         [0050]    The memory cell transistor  12  uses an N-type first diffusion layer  14  formed on the Si substrate  11  as a source and an N-type second diffusion layer  15  as a drain. A first gate oxide film  16  is formed on a part of the first diffusion layer  14  and on the second diffusion layer  15 . The first gate oxide film  16  has an opening in a part thereof. A tunnel oxide film  17  having a film thickness thinner than that of the first gate oxide film  16  is formed in the opening. The second diffusion layer  15  has a high concentration diffusion layer  18  which has conductive impurities whose concentration is higher than that of the other portion and is formed just under the tunnel oxide film  17  (i.e., in a portion confronting the tunnel oxide film  17 ). A floating gate electrode  19  is formed on a part of the first gate oxide film  16  and on the tunnel oxide film  17 . A control gate electrode  21  is formed on the floating gate electrode  19  through a second gate oxide film  20 . Further, a side wall  22  is formed to sides of the floating gate electrode  19 , the second gate oxide film  20 , and the control gate electrode  21 . The memory cell transistor  12  is composed of the Si substrate  11 , the first and second diffusion layers  14 ,  15 , the first gate oxide film  16 , the tunnel oxide film  17 , the high concentration diffusion layer  18 , the floating gate electrode  19 , the second gate oxide film  20 , and the control gate electrode  21  described above. Note that a silicon oxide film, for example, is exemplified as the first gate oxide film  16 . A silicon oxide film, for example, is exemplified as the second gate oxide film  20 , and further the second gate oxide film  20  may be a so-called ONO film formed by sequentially laminating a silicon oxide film, a silicon nitride film, a silicon oxide film. 
         [0051]    The selection transistor  13  is formed on the Si substrate  11  and uses an N-type low concentration diffusion layer  23  connected to the second diffusion layer  15  as a source and an N-type low concentration diffusion layer  24  as a drain. The first gate oxide film  16  is formed on the low concentration diffusion layers  23 ,  24 . A selection transistor gate electrode (hereinafter, simply called a gate electrode)  25  is formed on a part of the first gate oxide film  16 , and a side wall  26  is formed on a side of the gate electrode  25 . The selection transistor  13  is composed of the Si substrate  11 , the low concentration diffusion layers  23 ,  24 , the gate electrode  25 , and the side wall  26 . 
         [0052]    Note that although the memory cell transistor  12  and the selection transistor  13  share the first gate oxide film  16 , the first gate oxide film  16  may be preferably formed separately from a view point of design and fabricating steps. Further, the memory cell transistor  12  and the selection transistor  13  may be preferably formed on an N-type semiconductor substrate, and in this case, the relation between a P-type and an N-type is entirely reversed. 
         [0053]    Next, the method of fabricating the EEPROM  10  as the embodiment of the invention will be explained in detail referring to  FIG. 2A  to  FIG. 3C . 
         [0054]    First, after an element isolation region (not shown) is formed on the Si substrate  11  using a device isolation technique such as a LOCOS (Local Oxidation of Silicon) method and the like, an oxide film  31  is formed by a thermal oxidation method and the like ( FIG. 2A ). 
         [0055]    Next, a resist  33  is coated on the oxide film  31 . The resist  33  is patterned by lithography so that a through hole  32  is formed. N-type conductive impurities such as arsenide (As) and the like are added using the patterned resist  33  as a mask, (for example, they may be ion implanted), thereby the first and second diffusion layers  14 ,  15  are formed ( FIG. 2B ). The step is called a source/drain forming step. 
         [0056]    Next, after the resist  33  and the oxide film  31  are removed, the first gate oxide film  16 , which acts as gate oxide films of the memory cell transistor  12  and the selection transistor  13 , are newly formed by thermal oxidation method and the like. The step is called an oxide film forming step. Next, a resist  35  is coated on the first gate oxide film  16 . The resist  35  is patterned by the lithography so that a through hole  34  is formed ( FIG. 2C ). The step is called a resist forming step. 
         [0057]    Next, conductive impurities such as arsenide (As) and the like are ion implanted using the patterned resist  35  as a mask (i.e., through the through hole  34 ) so that the high concentration diffusion layer  18  having a high impurity concentration is formed to a part in the second diffusion layer  15  ( FIG. 2D ). The step is called an impurity adding step, and the conductive impurities may be ion implanted vertically to, for example, the bottom of the opening of the through hole  34 . 
         [0058]    Further, a method of ion implanting the conductive impurities as described below may be used. 
         [0059]    First, as shown in  FIG. 3A , the conductive impurities are ion implanted in a direction oblique to the through hole  34  (for example, in a lower left direction in  FIG. 3A ). The step is called an adding step. 
         [0060]    Next, the Si substrate  11  is rotated a predetermined angle (may be for example, 90° or 180°, and  FIG. 3B  shows a case that it is rotated 180°) using a central portion of the Si substrate  11  as an axis of rotation. The step is called a rotation step. After the Si substrate  11  is rotated, the conductive impurities are ion implanted again by the same method as that described above ( FIG. 3B ). 
         [0061]    A desired high concentration diffusion layer  18  can be formed by repeating the implantation step and the rotation step ( FIG. 3C ). When the method described above is used, since the area of the high concentration diffusion layer  18  is more increased than the case in which the conductive impurities are ion implanted vertically to the bottom of the opening of through hole  34 , stable write characteristics can be obtained because an edge of the tunnel oxide film  17  does not come into contact with the diffusion region having a small impurity concentration. 
         [0062]    Further, the addition step described above may be executed while rotating the Si substrate  11 . This is because the conductive impurities can be more uniformly distributed in the high concentration diffusion layer  18 . 
         [0063]    After the high concentration diffusion layer  18  is formed, the first gate oxide film  16  exposed through the through hole  34  is removed using the patterned resist  35 . The tunnel oxide film  17  is formed by forming a new oxide film having a film thickness thinner than that of the first gate oxide film  16  to the portion, from which the exposed first gate oxide film  16  is removed, by the thermal oxidation method and the like ( FIG. 2E ). Further, as another method, the tunnel oxide film  17  may be preferably formed by flowing an etching solution to the through hole  33  and etching the first gate oxide film  16  in the bottom of the opening of the through hole  33  to a predetermined thickness. Note that, in this case, only the portion of the first gate oxide film  16  positioning in the bottom of the opening of the through hole  33  is made thin and arranged as the tunnel oxide film  17 . The step is called a tunnel oxide film forming step. 
         [0064]    Next, after the resist  35  is removed, a polysilicon layer  36  acting as the floating gate electrode  19  of the memory cell transistor is formed, and an oxidation layer  37  is formed on the polysilicon layer  36  ( FIG. 2F ). The polysilicon layer  36  and the oxidation layer  37  may be preferably formed using, for example, the thermal oxidation method and a CVD method. 
         [0065]    Next, a resist (not shown) is coated on the oxidation layer  37 . The coated resist is patterned by the lithography. Etching is executed using the resist after it is patterned as a mask so that the floating gate electrode  19  and the second gate oxide film  20  are formed ( FIG. 2G ). The step is called a floating gate portion forming step. Note that the unnecessary first gate oxide film  16  may be removed in the step. The position of the unnecessary the first gate oxide film  16  is different depending the difference in the design and the fabricating steps of the EEPROM  10 . 
         [0066]    Next, a laminated film  38  acting as the control gate electrode  21  of the memory cell transistor  12  and as the gate electrode  25  of the selection transistor is formed ( FIG. 2H ). The laminated film  38  may be, for example, polysilicon-tungsten silicide formed by the CVD. 
         [0067]    Next, a resist (not shown) is coated on the laminated film  38 . The coated resist is patterned by the lithography. The laminated film  38  is etched using the resist after it is patterned as a mask so that the control gate electrode  21  and the gate electrode  25  are formed ( FIG. 21 ). Note that the unnecessary first gate oxide film  16  may be removed in the step. 
         [0068]    Next, to form a source and a drain of the selection transistor  13 , conductivity type impurities, for example, phosphorus and the like are ion implanted so that the low concentration diffusion layers  23 ,  24  are formed ( FIG. 2J ). The low concentration diffusion layer  23  is formed by being connected to the second diffusion layer  15 , and the impurity concentration of the low concentration diffusion layers  23 ,  24  is set smaller than that of the first diffusion layers  14 ,  15 . Further, the low concentration diffusion layer  23  acts as the source, and the low concentration diffusion layer  24  acts as the drain. 
         [0069]    Next, the side wall  22  is formed on the sides of the floating gate electrode  19 , the second gate oxide film  20 , and the control gate electrode  21  which constitute the memory cell transistor  12 , and the side wall  26  is formed on the side of the gate electrode  25  of the selection transistor  13  ( FIG. 2K ). Further, a high concentration diffusion layer (not shown) and a contact electrode (not shown) connected thereto may be formed after the side walls  22 ,  26  are formed. 
         [0070]    As described above, according to the method of fabricating the EEPROM of the embodiment, after the first and second diffusion layers  14 ,  15  acting as the source and drain regions of the memory cell transistor  12  are formed on the Si substrate  11  and gate electrode structures of the memory cell transistor  12  and the selection transistor  13  are formed on the Si substrate  11 , the low concentration diffusion layer  23 , which is the source region of the selection transistor  13 , is formed by being partially overlapped with the second diffusion layer  15  which is the drain region of the memory cell transistor  12 . As a result, the memory cell transistor  12  can be securely connected to the selection transistor  13  by the diffusion region having the high impurity concentration.