Abstract:
In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including forming a film on a surface of a substrate, the film designed to prevent the seeding of an electroless plating catalyst, laser ablating the surface of the substrate through the film to form trenches, and seeding the surface of the substrate with an electroless plating catalyst. Other embodiments are also disclosed and claimed.

Description:
FIELD OF THE INVENTION 
       [0001]    Embodiments of the present invention generally relate to the field of integrated circuit package substrates, and, more particularly to selective electroless plating for electronic substrates. 
       BACKGROUND OF THE INVENTION 
       [0002]    Reductions in the size and pitch of integrated circuit devices require advancements in the manufacture of IC package substrates. The use of lasers is becoming more common for patterning substrates. Metallization techniques for plating laser projection patterned (LPP) substrates (among other electronic substrates) are needed that control costs, manufacturing time, and potential damage to the substrate. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0003]    The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements, and in which: 
           [0004]      FIG. 1  is a graphical illustration of a cross-sectional view of a partially formed IC package substrate, in accordance with one example embodiment of the invention; 
           [0005]      FIG. 2  is a graphical illustration of a cross-sectional view of a partially formed IC package substrate, in accordance with one example embodiment of the invention; 
           [0006]      FIG. 3  is a graphical illustration of a cross-sectional view of a partially formed IC package substrate, in accordance with one example embodiment of the invention; 
           [0007]      FIG. 4  is a graphical illustration of a cross-sectional view of a partially formed IC package substrate, in accordance with one example embodiment of the invention; 
           [0008]      FIG. 5  is a graphical illustration of a cross-sectional view of a partially formed IC package substrate, in accordance with one example embodiment of the invention; 
           [0009]      FIG. 6  is a graphical illustration of a cross-sectional view of a partially formed IC package substrate, in accordance with one example embodiment of the invention; 
           [0010]      FIG. 7  is a graphical illustration of a cross-sectional view of a partially formed IC package substrate, in accordance with one example embodiment of the invention; and 
           [0011]      FIG. 8  is a graphical illustration of a cross-sectional view of a partially formed IC package substrate, in accordance with one example embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0012]    In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that embodiments of the invention can be practiced without these specific details. In other instances, structures and devices are shown in block diagram form in order to avoid obscuring the invention. 
         [0013]    Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments. 
         [0014]      FIG. 1  is a graphical illustration of a cross-sectional view of a partially formed IC package substrate, in accordance with one example embodiment of the invention. In accordance with the illustrated example embodiment, package substrate  100  includes one or more of dielectric layer  102 , surface  104 , and pad  106 . 
         [0015]    Dielectric layer  102  represents material such as epoxy resin that has been built on pad  106  (and potentially other layers not shown) as part of a build-up process. Pad  106  may be a layer of copper. 
         [0016]      FIG. 2  is a graphical illustration of a cross-sectional view of a partially formed IC package substrate, in accordance with one example embodiment of the invention. As shown in package substrate  200 , via  202  has been created from surface  104  of dielectric layer  102  down to pad  106 , exposing pad  106 . In one embodiment laser drilling with CO 2  is used to drill dielectric layer  102  forming via  202  Alternatively any different laser may be used to drill the microvia in the substrate. For instance, an excimer or UVYAG type laser may be substituted for the CO 2  laser drilling process. In one embodiment, via  202  is cleared of any debris by desmear techniques. 
         [0017]      FIG. 3  is a graphical illustration of a cross-sectional view of a partially formed IC package substrate, in accordance with one example embodiment of the invention. As shown in package substrate  300 , partially filled via  302  is created through electroless plating of dielectric layer  102  on top of pad  106 . In one embodiment, copper electroless plating on copper pad  106  is time controlled so that partially filled via  302  will reach a predetermined thickness, to be described more fully hereinafter. 
         [0018]      FIG. 4  is a graphical illustration of a cross-sectional view of a partially formed IC package substrate, in accordance with one example embodiment of the invention. As shown in package substrate  400 , film  402  has been deposited on surface  104  and partially filled via  302 . In one embodiment, film  402  is designed to prevent the seeding of an electroless plating catalyst. Film  402  may be made of a material with negligible diffusion of charged species across the membrane and hence forming a barrier for ionic palladium seeding on the epoxy surface. In one embodiment, film  402  comprises alternating layers of oppositely charged polyelectrolytes which are assembled up to a sufficient number of layer pairs to form an effective barrier against charged catalyst diffusion or penetration. The minimum required thickness, which is a function of the number of layers, is experimentally determined. In one embodiment, film  402  comprises about 10 layer pairs (20 layers) of polyallylamine hydrochloride (PAH), a positively charged polyelectrolyte that is pH sensitive (the total ionic charge of the polymer depends on the pH value) and a negatively charged polyelectrolyte, polystyrene sulfonate (PSS). Such a combination of polyelectrolytes is known to deter ionic diffusion across the Polyelectrolyte membrane, as such, any other polyelectrolyte pair with similar charge transport properties may be utilized. In one embodiment, deposition of film  402  is done by dipping package substrate  400  in a polyelectrolyte solution of a specific concentration and pH, with water rinses, or buffer solution rinses in between oppositely charged polymer depositions. In another embodiment, deposition of film  402  is done by spraying the polymers on package substrate  400  (with water or buffer spraying done in between polymer spraying steps). In another embodiment, film  402  may be a laminated polymer film of any nature that resists seeding, such as solder resist-type material. In another embodiment, film  402  may be an acrylate-based polymer film. 
         [0019]      FIG. 5  is a graphical illustration of a cross-sectional view of a partially formed IC package substrate, in accordance with one example embodiment of the invention. As shown in package substrate  500 , laser projection patterning is utilized to ablate material from film  402  and from surface  104  of dielectric layer  102  simultaneously forming trenches  502 . In one embodiment, desmear for trenches  502  is not necessary due to the fact that laser ablation by excimer laser produces very little residue. 
         [0020]      FIG. 6  is a graphical illustration of a cross-sectional view of a partially formed IC package substrate, in accordance with one example embodiment of the invention. As shown in package substrate  600 , seeding has resulted in catalyst  602  resident in trenches  502 , but not on film  402 . In one embodiment, catalyst  602  is an ionic palladium or charged colloidal palladium catalyst and the ionic charge diffusion barrier properties of film  402  prevents palladium seeding. 
         [0021]      FIG. 7  is a graphical illustration of a cross-sectional view of a partially formed IC package substrate, in accordance with one example embodiment of the invention. As shown in package substrate  700 , film  402  has been stripped from surface  104  and partially filled via  302 . In one embodiment, an alkaline bath, perhaps containing NaOH as one of the constituents, is used to strip PAH/PSS multilayers of film  402  due to deprotonation of the PAH polymer. In another embodiment, a long base dip is used to remove solder resist-type material of film  402 . Depth  702  represents a substantially equivalent depth below surface  104  of trenches  502  and partially filled via  302 . Depth  702  may be predetermined so that subsequent electroless plating will fill trenches  502  and partially filled via  302  at substantially the same time. 
         [0022]      FIG. 8  is a graphical illustration of a cross-sectional view of a partially formed IC package substrate, in accordance with one example embodiment of the invention. As shown in package substrate  800 , electroless plating on catalyst  602  and partially filled via  302  has formed traces  802  and filled via  804 . In one embodiment, copper electroless plating fills trenches  502  and partially filled via  302  substantially even with surface  104  without the need for planarization. 
         [0023]    In one embodiment, package substrate  800  is coupled on surface  104  with an integrated circuit die such as a flip chip silicon die. In another embodiment, surface  104  is laminated with another dielectric layer as part of a continued build-up process. 
         [0024]    In the description above, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form. 
         [0025]    Many of the methods are described in their most basic form but operations can be added to or deleted from any of the methods and information can be added or subtracted from any of the described messages without departing from the basic scope of the present invention. Any number of variations of the inventive concept is anticipated within the scope and spirit of the present invention. In this regard, the particular illustrated example embodiments are not provided to limit the invention but merely to illustrate it. Thus, the scope of the present invention is not to be determined by the specific examples provided above but only by the plain language of the following claims.