Abstract:
A complementary self-limiting transmission line driver is capable of driving an unterminated line driver with self-limiting slew rate control to minimize the effects of reflections on the transmission line and minimize the level of noise on power supply distribution paths. The complementary self-limiting driver circuit includes a driving circuit for receiving an output signal. In response to the output signal, a driving signal is provided to an output terminal connected to the unterminated transmission line. A first limiting circuit is connected to the driving means for controlling a slew rate of the driving means and for disabling the driving means when the output signal approaches within a threshold level of the second signal level. A second limiting circuit is optionally connected to the driving means for controlling the slew rate of the driving means and for disabling the driving means when the output signal approaches within a threshold level of the first signal level.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     The present invention claims priority under 35 U.S.C. §119 (e) from U.S. provisional application Ser. No. 60/204,886, entitled “A Self-Limiting Pad Driver,” filed May 17, 2000, the contents of which are incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to circuits to transfer digital signals to a transmission line connecting two integrated circuits. More particularly, this invention relates to circuits that transfer digital signals to an unterminated transmission line while limiting the effects of reflections and noise on power distribution lines. 
     2. Description of the Related Art 
     Driver and receiver circuits for the transfer of digital signals between functions of an electronic or computer system are well known in the art. Bus structures such as the Integrated Drive Electronics (IDE) specified in the American National Standards Institute (ANSI) standard X3T10 describe the electrical power and data interface between a computer system board (motherboard) and an integrated disk controller. Generally these driver circuits consist of transistors configured to transfer signals from internal function circuits of the integrated circuit and to condition the signals to be transferred and to transfer the signals to an input/output pad formed at the surface of a semiconductor substrate on which the integrated circuit is formed. Attached to the input/output pad is wirebond. The wirebond is formed of a fine wire connected to the input/output pad at one end and connected to a wire trace that is formed into a bonding pad on a module on which the semiconductor die is mounted at the opposite end of the bonding wire. The wirebond allows the signal further transferred to printed wiring traces on the module. The printed wiring traces of the module are connected to terminal pins of the module. The terminal pins of the module allow the module to be mounted to a printed circuit board (the motherboard or the integrated disk controller). The pins are either connected through vias (holes in the printed circuit board) or in contact with pads formed of printed wiring traces on the surface of the printed circuit board. The pins will be generally soldered to the vias or the contact pads of the printed circuit board. The vias or contact pads are connected to printed wiring traces that conduct the signals from the integrated circuit to other integrated circuits mounted similarly to the printed circuit board. Alternately, the printed wiring traces will be connected to the terminating connector pins of one end of a cable connected to the printed circuit wiring board. The cable has a second terminating connector connected at the opposite end, which is connected to a second printed circuit wiring board. The cable then transfers the signal from the integrated circuit to printed wiring traces on the second printed circuit board. The wiring traces on the second printed circuit wiring board are connected to the vias or bonding pads having the pins of a second integrated circuit module. The pins of the second integrated circuit module are connected through module wiring traces to the module bonding pads. Wirebonds connect the module bonding pads to an input/output pad on a second semiconductor substrate having a second integrated circuit. The input/output pad is connected by interconnecting layers on the surface of the semiconductor substrate to a receiver. The receiver accepts the transferred signal and conditions it for use by the internal circuits of the second integrated circuit. 
     At lower frequencies, the equivalent circuit of one such signal path to transfer signals between integrated circuit functions on separate printed circuit boards is as shown in FIG.  1 . The output driver is formed of the n-type metal oxide semiconductor (MOS) transistor M 1  and the p-type MOS transistor M 2 . The drains of the n-type MOS transistor M 1  and the p-type MOS transistor M 2  are connected through the I/O signal pad to the load capacitor C L . The load capacitor C L  is composed of the capacitances of the input/output pads on the semiconductor substrate mounted in the second integrated circuit module, wirebond from the input/output pad, the module wiring trace of the second integrated circuit module, module pins of the second integrated circuit module, printed circuit wiring traces of the printed circuit boards, the terminal connectors that attach a cable to the printed circuit boards, the distributed capacitance of the inter-connecting cable, and the input loading capacitance of the receiver. 
     The source of the n-type MOS transistor M 1  is connected through the parasitic inductance L Vss  and the pad connector I/O Vss  to the ground reference potential. The parasitic inductance L Vss  is the lumped inductance of a wirebond from voltage wirebonding pad of the integrated circuit to the module pin, the module pin itself, and any of the printed circuit wiring traces, connectors, and cabling connecting the ground reference potential to the integrated circuit. 
     The source of the p-type MOS transistor M 2  is similarly connected through the parasitic inductance L Vcc  and the pad connector I/O Vss  to the power supply voltage source V cc . The parasitic inductance L Vcc  is the lumped inductance of the wirebond from the integrated circuit to the module pin of the module containing the integrated circuit, the module pin itself, and any of the printed circuit wiring traces, connectors, and cabling connecting the power supply voltage source to the integrated circuit. 
     The gates of the n-type MOS transistor M 1  and the p-type MOS transistor M 2  are connected to the internal circuit Int Ckt of the integrated circuit to receive the output signal that is to be transferred to the receiver REC. When the output signal changes from a first voltage level (i.e. 0V) to a second voltage level, (i.e. V cc ) the n-type MOS transistor M 1  conducts and the p-type MOS transistor M 2  ceases to conduct. Any charge present on the load capacitor CL is conducted through the n-type MOS transistor M 1  to the ground reference potential. 
     Similarly, when the output signal traverses from the second voltage level (V cc ) to the first voltage level, the n-type MOS transistor M 1  ceases to conduct and the p-type MOS transistor M 2  conducts. A current is transferred from the power supply voltage source through the p-type MOS transistor M 2  to charge the load capacitor C L . 
     At shorter physical dimensions and at lower frequencies with slower transition times, the schematic of FIG. 1 is adequate to simulate the performance of the interface. However, as the dimensions increase or the frequency of operation increases, a more accurate model, as shown in FIG. 2, must be used. In FIG. 2, the drains of the n-type MOS transistor M 1  and the p-type MOS transistor M 2  are connected to the transmission line T X  through the input/output signal pad. The opposite end of the transmission line T X  is connected to the load capacitor C L . The load capacitor C L  now represents the lumped capacitance of the terminating pins of the second connector of the cable, the printed circuit wiring traces, the module pins of the second integrated circuit module, the printed wiring traces of the second integrated circuit module, the bonding wire connected to the receiver REC and the input capacitance of the receiver REC itself. The current return lines of the transmission are connected to the ground reference potential. 
     The transmission line effects of the driver providing or sourcing current or receiving or sinking current from an open circuit produces predictable but undesirable effects to the driver signal placed on the transmission line. The effects or reflections often cause “ringing” or self-oscillation of the driver signal during the transitions between the first voltage level (0V) and the second voltage level (V cc ). 
     FIG. 3 shows the addition of a terminating resistor R T  from the junction of the transmission line T X  and the receiver to the ground reference potential. In this example, when the output signal V O  is at the second voltage level, the p-type MOS transistor must remain conducting to keep the input of the receiver at the second voltage level (V cc ). 
     It is well known in the art that the terminating resistor R T  can be placed from the junction of the transmission line and the input of the receiver to the power supply voltage source V cc . Further, the terminating resistor may be a network of resistors connected to both the ground reference potential and the power supply voltage source V cc . 
     The terminating resistor R T  eliminates or reduces any of the noise effect due to reflections on the transmission line. Any remaining reflections are due to discontinuities in the signal path due to factors such as the terminating pins of the connectors that attach the printed circuit boards to the cable forming the transmission line. 
     Refer now to FIG. 4 to examine a communication interface that is made up of multiple signal paths similar to FIG.  2 . In the IDE standard, the interface consists of sixteen data bits or data paths. 
     The interface has multiple drivers D 1 , D 2 , D 3 , . . . , D n , each connected through an input/output signal pad to a transmission line T x1 , T x2 , T x3 , T xn . As described above, each transmission line is connected to a receiver. The load capacitance C L , as described above, is the wiring trace capacitance, the terminating connector capacitance, and the input capacitance of the receiver. 
     Each driver is configured as shown in FIG.  2 . When the output signal V O  is such that the n-type MOS transistor M 1  is turned on and the p-type MOS transistor M 2  is turned off, as described above, the charge present on the load capacitance C L  is discharged through the parasitic inductor L Vss . The voltage V LVss  developed across the parasitic inductor L Vss  is proportional to the change in current resulting from the activation of the n-type MOS transistor M 1 . If any or all of the drivers of the communication interface have their n-type MOS transistors M 1  activated, the resulting currents are added, thus increasing the level of noise or “ground bounce” on the distribution path for the ground reference potential. This “ground bounce,” also referred to as Δi noise, impacts the operation of the internal circuits as well as the drivers of the communication interface. 
     Alternately, when the output signal V O  is such that p-type MOS transistor M 2  is turned on and the n-type MOS transistor M 1  is turned off, the load capacitance C L  is now charged by a current from the power supply voltage source V cc  through the parasitic inductor L Vcc . The voltage V LVcc  across the parasitic inductor L Vcc  is proportional to the change in the charging current flowing to the load capacitance C L  through the p-type MOS transistor M 2 . If any or all the drivers have their p-type MOS transistors activated, the resulting currents are added, thus increasing the level of noise or power supply “bounce” (again Δi noise) on the distribution path for the power supply voltage source. The power supply “bounce” or noise also affects the operation of the internal circuits as well as the drivers of the communication interface. 
     In order to minimize the effect of a very fast rise time on the transfer of the driver signal on the transmission line, the slew rate of the driver as measured in volts/second is lowered. It is well known in the art that if the electrical length of the transmission line T X  is less than one half the rise time or fall time of the driver signal, then the transmission can be considered capacitive and included in the load capacitance C L  as shown in FIG.  1 . 
     FIG. 5 shows a complementary driving circuit of the prior art with slew rate control. The driver circuit DRV is connected to the transmission line T X  as described in FIG.  2 . The slew rate control predrivers SRC 1  and SRC 2  are connected to the driver circuit to control the activation of the driver circuit when the output signal V O  indicates that the driver signal V D  is to change between the first voltage level (0V) and the second voltage level (V cc ). The first and second slew rate control predrivers respectively consist of the n-type MOS transistors M 3  and M 5  and the p-type MOS transistors M 4  and M 6 . The drains of the n-type MOS transistor M 5  and the p-type MOS transistor M 6  are connected to the gate of the n-type MOS transistor M 1 . The drains of the n-type MOS transistor M 3  and the p-type MOS transistor M 4  are connected to the gate of the p-type MOS transistor M 2 . The gates of the n-type MOS transistors M 3  and M 5  and the p-type MOS transistors M 4  and M 6  are connected to the internal circuits to receive the output signal. The sources of the n-type MOS transistors M 3  and M 5  are connected to the ground reference potential through the parasitic inductance L VSS  and the voltage wirebonding pad I/O VSS . The sources of the p-type MOS transistors M 4  and M 6  are connected through the parasitic inductance L VCC  and the voltage wirebonding pad I/O VCC  to the power supply voltage source. 
     An example of a conventional slew rate control is provided in U.S. Pat. No. 6,081,134, the contents of which are incorporated herein by reference. 
     FIG. 6 a  illustrates the “ground bounce” or the voltage VL Vss  across the parasitic inductor L Vss  of FIG.  5 . As is shown, the voltage VL Vss  across the parasitic inductor L Vss  can change by approximately 2.5V when the driver signal V D  is changing from the second voltage level (V cc ) to the first voltage level (0V) and the load capacitance C L  is being discharged. 
     Conversely, FIG. 6 b  illustrates the power supply “bounce” or the voltage developed across the parasitic inductor L Vcc  of FIG.  5 . In this case, the voltage VL Vcc  can change by approximately 600 mV when the driver signal changes from the first voltage level (0V) to the second voltage level (V cc ) and the load capacitance C L  is being charged. 
     This noise is super-positionally added when the driver signal of multiple drivers, as shown in FIG. 4, are simultaneously traversing between the first voltage level (0V) and the second voltage level (V cc ). 
     Refer now to FIG. 7 to discuss the voltage at the near end or transmitter end of the transmission line. The output signal V O  is transmitted to the slew rate control drivers SRC 1  and SRC 2  of FIG.  5 . In response to the output signal V O , the output driver DRV generates the driver signal V D . The point A on the driver signal V D  shows the voltage of the driver signal V D  at the beginning of the transmission down the transmission line T x . The voltage at point A on the driver signal V D  is the voltage divider of the characteristic impedance Z 0  of the transmission line T X  and the voltage drop across the p-type MOS transistor M 2 . The voltage at point B on the driver signal V D  is the result of the reflection from the load capacitance C L . As can be seen, the voltage at the drain of the p-type MOS transistor M 2  can become negative, causing a large instantaneous current flow from the power supply voltage source V cc . The voltage returns at point C on the driver signal V D  to the voltage level of the power supply voltage source V cc  with modest “ringing” or damped self-oscillation. 
     When the output signal V D  changes from the second voltage level (V cc ) to the first voltage level (0V), the driver signal V D  falls to the voltage level at point D. This again is a result of the voltage divider between the driver, in this case, the n-type MOS transistor M 1  and the impedance of the transmission line T x . The returning reflections cause the “ringing” or damped self-oscillation as seen in point E on the driver signal V D . 
     Refer now to FIG. 8 to review the voltage levels at the far end of the transmission line T x  at the input of the receiver. The output signal V O  is, as described above, transferred from the internal circuits to the slew rate control predrivers SRC 1  and SRC 2 . In response to the output signal V O  the driver signal V D  at the receiver is as shown. The arrival of the incident wave of the driver signal at the load capacitance C L , which appears as an open circuit. The driver signal level V D  is doubled to the voltage level at point A on the driver signal V D . Subsequent reflections cause the “ringing” or damped self-oscillation shown at point B on the driver signal V D . 
     When the output signal traverses from the second voltage level (V cc ) to the first voltage level (0V), the incident wave of the driver signal V D  is transmitted down the transmission line to arrive at the load capacitance. The voltage level a point D on the driver signal V D  of FIG. 7 is doubled and the voltage level of point C on the driver signal V D  of FIG. 8 is achieved. The attendant reflections cause the “ringing” or damped self-oscillation shown at point D on the driver signal V D  of FIG.  8 . 
     If the frequency transmitted as the output of the internal circuit is sufficiently high and the slew rate sufficiently large, the “ringing” or damped self-oscillation on the transmission line and the noise on the power supply distribution interconnections is sufficiently large to prevent the receiving of the digital data. The classic IDE standard has a maximum transmission rate of 8 MHz. However, as the system design has improved, it is desirable to transmit the data at 16 MHz without the “ringing” or damped self-oscillation and the power distribution noise. 
     SUMMARY OF THE INVENTION 
     In accordance with an aspect of the present invention, a complementary self-limiting driver circuit within an integrated circuit for driving unterminated transmission lines includes a driving circuit for receiving an output signal that is changing from a first signal level (0V) to a second signal level, and after a period of time, is changing from the second signal level (approximately V cc ) to the first signal level. In response to the output signal, a driving signal is provided to an output terminal connected to the unterminated transmission line. A first limiting circuit is connected to the driving means for controlling a slew rate of the driving means when the driver signal is changing from the first signal level to the second signal level and for disabling the driving means when the output signal approaches within a threshold level of the second signal level. A second limiting circuit is optionally connected to the driving means for controlling the slew rate of the driving means when the driver signal is changing from the second signal level to the first signal level and for disabling the driving means when the output signal approaches within a threshold level of the first signal level. 
     The driving circuit has a first transistor of a first conductivity type. The first transistor of a first conductivity type has a first terminal connected to receive the output signal, a second terminal connected to the output terminal for providing the output signal during the changing from the first signal level to the second signal level, and a third terminal connected to a reference voltage source. The driving circuit also has a first transistor of a second conductivity type. The first transistor of a second conductivity type has a first terminal connected to receive the output signal, a second terminal connected to the output terminal for providing the output signal during the changing from the second signal level to the first signal level, and a third terminal connected to a power supply voltage source. 
     The first limiting circuit is composed of a second transistor of the first conductivity type. The second transistor of the first conductivity type has a first terminal connected to the driving means, a second terminal connected to the internal circuits to receive the output signal, and a third terminal connected to the reference voltage source. The first limiting circuit has a second transistor of the second conductivity type. The second transistor of the second conductivity type has a first terminal connected to the output terminal, a second terminal connected to the internal circuits to receive the output signal, and a third terminal connected to the first terminal of the second transistor of the first conductivity type and to the driving means such that when the output signal activates the driving means, the driving means is functioning as a diode until the driver signal achieves a signal level within the threshold of the first signal level at which time the driving means is disabled. 
     The second optional limiting circuit is composed of a third transistor of the second conductivity type. The third transistor of the second conductivity type has a first terminal connected to the driving means, a second terminal connected to the internal circuits to receive the output signal, and a third terminal connected to the power supply voltage source, The second limiting circuit also has a third transistor of the first conductivity type. The third transistor of the first conductivity type has a first terminal connected to the output terminal, a second terminal connected to the internal circuits to receive the output signal, and a third terminal connected to the first terminal of the third transistor of the second conductivity type and to the driving means such that when the output signal activates the driving means, the driving means is functioning as a diode until the driver signal achieves a signal level within the threshold of the second signal level at which time the driving means is disabled. 
     In order to provide a D.C current level necessary for terminated transmission lines or for receiver requiring a minimum current level, The complementary self-limiting driver circuit further includes a current driving means connected in parallel with the driving circuit. The current driving means also receives the output signal from the internal circuits and in response to the output signal provides a path to source and sink current from the output terminal. 
     For communication interfaces having a higher voltage level than can be tolerated by the transistors of the complementary self-limiting driver circuit, a cascode driving circuit is placed between the driving means and the output terminal. The cascode driving circuit restricts a high voltage present at the output terminal from contacting the driving means and damaging the driving means. The cascode driving means is formed of a fourth transistor of the first conductivity type, and a fourth transistor of the second conductivity type. The fourth transistor of the first conductivity type has a first terminal connected to the output terminal, a second terminal connected to the driving means, and a third terminal connected to a first biasing voltage source. The fourth transistor of the second conductivity type has a first terminal connected to the output terminal, a second terminal connected to the driving means, and a third terminal connected to a second biasing voltage source. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a digital communication interface of the prior art showing an I/O pad driver and a model of the transmission line as a load capacitance. 
     FIG. 2 is a schematic diagram of a digital communication interface of the prior art showing an I/O pad driver and an unterminated transmission line. 
     FIG. 3 is a schematic diagram of a digital communication interface of the prior art showing a terminated transmission line. 
     FIG. 4 is a schematic diagram of a communication interface showing multiple data paths of the prior art. 
     FIG. 5 is a schematic diagram of a slew rate controlled driver on a communication interface of the prior art. 
     FIGS. 6 a  and  6   b  are plots, respectively, of switching noise on the ground reference potential (V ss ) and the power supply voltage source (V cc ) of the slew rate controlled driver of FIG.  5 . 
     FIG. 7 is a plot of the output signal of the internal circuits and the driver signal at the near end of the transmission line of the slew rate controlled driver of FIG.  5 . 
     FIG. 8 is a plot of the output signal of the internal circuits and the driver signal at the far end of the transmission line of the slew rate controlled driver of FIG.  5 . 
     FIG. 9 is a schematic diagram of a communication interface containing a self-limiting driver of this invention. 
     FIGS. 10 a  and  10   b  are plots, respectively, of switching noise on the ground reference potential (V ss ) and the power supply voltage source (V cc ) of the self-limiting driver of this invention as shown in FIG.  9 . 
     FIG. 11 is a plot of the output signal of the internal circuits and the driver signal at the near end of the transmission line of the self-limiting driver of this invention as shown in FIG.  9 . 
     FIG. 12 is a plot of the output signal of the internal circuits and the driver signal at the far end of the transmission line of the self-limiting driver of this invention as shown in FIG.  9 . 
     FIG. 13 is a schematic diagram of a second embodiment of the self-limiting driver of this invention within a communication interface. 
     FIG. 14 is a schematic diagram of a third embodiment of the self-limiting driver of this invention within a communication interface. 
     FIG. 15 is a schematic diagram of a fourth embodiment of the self-limiting driver of this invention within a communication interface. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A self-limiting driver of this invention is shown in FIG. 9 as implemented as a single bit or data path of a communication interface. As shown, the data path of the communication interface has two basic driver circuits DRV H  and DRV L  to form the complementary driver circuit of this invention. The basic driver circuit DRV H  is what is commonly termed a “high side” driver that, when active, allows the load capacitance C L  to charge toward the second voltage level V cc  of the power supply voltage source V cc . The logic level represented by the second voltage level (V cc ) is thus received by the receiver. The structure of the driver circuit DRV H  may optionally disable the driver circuit DRV H  when the voltage level at the output of the driver circuit DRV H  approaches within a threshold voltage of the driver circuit DRV H . 
     The basic driver circuit DRV L  is what is commonly termed a “low side” driver that, when active, allows the load capacitance C L  to discharge toward the first voltage level (0V) of the ground reference potential. The receiver thus receives the logic level represented by the first voltage level (0V). The structure of the driver circuit DRV L  similarly disables the driver circuit DRV L  when the voltage level at the output of the driver circuit DRV L  is within a threshold voltage of the driver circuit DRV L . 
     This disabling of the driver circuits DRV H  and DRV L  as they approach within their respective threshold voltage of the second and first voltage levels self-limits the slew rates of the driver circuits DRV H  and DRV L  and therefore minimizes the “ringing” or damped self-oscillation resulting from reflections on the transmission line T x . Further, the disabling of the driver circuits DRV H  and DRV L  minimizes the magnitude of the Δi noise generated on the distribution wiring and interconnection network for the power supply voltage source V cc  and the ground reference potential. 
     The driver circuit DRV H  is comprised of the p-type MOS transistors M 2  and M 4  and the n-type MOS transistor M 3 . The sources of the p-type MOS transistors M 2  and M 4  are connected through the distribution wiring and interconnection network modeled by the parasitic inductor LV cc  to the power supply voltage source V cc . The gates of the p-type MOS transistor M 4  and the n-type MOS transistor M 3  are connected together to form the input of the driver circuit DRV H  which is connected to the internal circuits Int Ckt to receive the output signal V o . 
     The drains of the p-type MOS transistor M 4  and the n-type MOS transistor M 3  are connected to the gate of the p-type MOS transistor M 2 . The source of the n-type MOS transistor M 3  is connected to the ground reference potential. When the output signal V o  of the internal circuits Int Ckt changes from the first voltage level (0V) to the second voltage level (5V), the n-type MOS transistor M 3  is turned on and the p-type MOS transistor M 4  is turned off; and the n-type MOS transistor M 5  is turned on and the p-type MOS transistor M 6  is turned off. The turning on of the n-type MOS transistors M 3  and M 5 , in turn, turn off the n-type MOS transistor M 1  and turn on the p-type MOS transistor M 2 . The driver circuit DRV H  effectively causes the driver signal to approach the voltage level of the power supply voltage source. This action is similar as to shown in FIG.  5 . 
     The driver circuit DRV L  is comprised of the n-type MOS transistors M 1  and M 5  and the p-type MOS transistor M 6 . The sources of the n-type MOS transistors M 1  and M 5  are connected through the distribution wiring and interconnection network modeled by the parasitic inductor L Vss  to the ground reference potential. The gates of the n-type MOS transistor M 5  and the p-type MOS transistor M 6  are connected together to form the input of the driver circuit DRV L  which is connected to the internal circuits Int Ckt to receive the output signal V o . 
     The drains of the p-type MOS transistor M 6  and the n-type MOS transistor M 5  are connected to the gate of the n-type MOS transistor M 1 . The source of the p-type MOS transistor M 6  is connected to the drain of the n-type MOS transistor M 1  which together form the output of the driver circuit DRV L . 
     When the output signal V o  of the internal circuits Int Ckt changes from the second voltage level (5V) to the first voltage level (0V), the p-type MOS transistor M 6  is turned on and the n-type MOS transistor M 5  is turned off; and the p-type MOS transistor M 4  is turned on and the n-type MOS transistor M 3  is turned off. The turning on of the p-type MOS transistors M 4  and M 6 , in turn, turn off the p-type MOS transistor M 2  and turn on the n-type MOS transistor M 1 . Turning on the p-type MOS transistor M 6  effectively connects the gate of the n-type MOS transistor M 1 , to its gate, thus effectively configuring the n-type MOS transistor M 1  as a diode. The slew rate of the driver signal at the output of the driver circuit DRV L  is thus self-limiting in that when the output voltage approaches within a threshold voltage (V T ) of the n-type MOS transistor M 1 , the n-type MOS transistor M 1  is turned off. The slew rate of the driver signal V D  is self-limiting in that the size of the load capacitance C L  determines the time duration that the n-type MOS transistor M 1  remains turned on. A small load capacitance C L  charges more quickly and reaches a voltage level within the threshold voltage of the ground reference potential sooner. Conversely, a larger load capacitance C L  forces the n-type MOS transistor M 1  to conduct more current for a longer time. 
     In a second embodiment of this invention shown in FIG. 13, the source of the n-type MOS transistor M 3  is connected to the drain of the p-type MOS transistor M 2  which together form the output of the driver circuit DRV H . The second embodiment of this invention makes the driver circuit DRV H  into a self-limiting driver. 
     When the n-type MOS transistor M 3  is configured as the second embodiment shown in FIG. 13, the n-type MOS transistor M 3  effectively connects the gate of the p-type MOS transistor M 2  to its gate, thus effectively configuring the p-type MOS transistor M 2  as a diode. The slew rate of the driver signal V D  at the output of the driver circuit DRV H  is self-limiting in that when the output voltage approaches within a threshold voltage (V T ) of the p-type MOS transistor M 2 , the p-type MOS transistor M 2  is turned off. The slew rate of the driver signal V D  is self-limiting in that the size of the load capacitance C L  determines the time duration that the p-type MOS transistor M 2  remains turned on. A small load capacitance C L  charges more quickly and reaches a voltage level within the threshold voltage of the power supply voltage source sooner. Conversely, a larger load capacitance C L  forces the p-type MOS transistor M 2  to conduct more current for a longer time. 
     The driver circuit DRV L  the first embodiment of this invention of FIG.  9  and driver circuits DRV L  of the second embodiment of this invention of FIG. 13 have an advantage over a slew rate controlled driver circuit of the prior art such as shown in FIG. 5 with respect to the amount of Δi noise present on the distribution wiring and interconnection network of the ground reference potential. 
     The driver circuit DRV H  of the second embodiment of this invention of FIG. 13 have an advantage over a slew rate controlled driver circuit of the prior art such as shown in FIG. 5 with respect to the amount of Δi noise present on the distribution wiring and interconnection network of the power supply voltage source. As soon as the voltage present at the output of the driver circuit DRV L , respectively, approaches the voltage level that is within a threshold voltage (V T ) of the power supply voltage source (V cc ) or the ground reference potential, the driver MOS transistors M 2  or M 1  are turned off, thus limiting the current change on the distribution wiring and interconnection network. Limiting this current limits the induced voltages V LVcc  or V LVss . Refer now to FIG. 10 a  to examine the level of the voltage V LVss  developed across the parasitic inductor L Vss . In this instance, the maximum voltage change is less than 250 mV for the single driver. This is compared to a maximum voltage change of approximately 500 mV for the driver of FIG.  5 . 
     The driver circuit DRV H  of the first embodiment of this invention develops a voltage V LVcc  level across the parasitic inductance L Vcc  that is generally equivalent to that as shown in FIG. 6 b.  The voltage V LVcc  level across the parasitic inductance L Vcc  for the second embodiment of this invention is described in FIG. 10 b.  In this instance, the maximum voltage change is approximately 140 mV. This is compared to a maximum voltage change of approximately 600 mV for the driver circuit of FIG. 5 as shown in FIG. 6 b.    
     Refer now to FIG. 11 to examine the output signal V O , and in response to the output signal V O , the driver signal V D  at the near end of the transmission line T x  at the output end of the complementary driver. 
     When the output signal V O  changes from the first voltage level (0V) to the second voltage level (V cc ), the driver signal V D  rises to the level at point A of the driver signal V D . This voltage level, as described above, is the voltage division of the voltage drop across the p-type MOS transistor M 2  and the characteristic impedance Z 0  of the transmission line T x . The returning reflection from the load capacitance C L  is shown at point B of the driver signal V D . The driver signal V D  increases from the level at point B of the driver signal V D  to the level at point C of the driver signal V D  as the transmission line is brought to the voltage level of the power supply voltage source V cc . 
     When the output signal V O  changes from the second voltage level (V cc ) to the first voltage level (0V), the driver signal V D , in response, falls to the voltage level of point D. The voltage level of point D of the driver signal V D  now is the voltage level determined by the voltage divider of the n-type MOS transistor M 1  and the characteristic impedance Z 0  of the transmission line T x . The first reflection is the voltage level at point E of the driver signal V D . The driver signal V O  then decreases toward the first voltage level (0V). When the driver signal V D  approaches within a threshold of the n-type MOS transistor M 1 , the n-type MOS transistor M 1  turns off and the transmission line T x  appears unterminated and the driver signal V D  approaches the first voltage level (0V) at point F. 
     Refer now to FIG. 12 to examine the output signal V O , and in response to the output signal V O , the driver signal V D  at the far end of the transmission line T x  at the input of the receiver. 
     When the output signal V O  changes from the first voltage level (0V) to the second voltage level (V cc ), the driver signal V O  rises to the level at point A of the driver signal V D . This voltage level, as described above, is the result of the doubling of the incident wavefront of the driver signal “bouncing” or reflecting from the unterminated receiver. There is minimal “ringing” or damped self-oscillation due to reflections since the p-type MOS transistor M 2  has turned off and both ends of the transmission line T x  are unterminated. 
     The individual reflections on the transmission line cause the voltage level of the driver signal V D  to rise to point B at the voltage level of the power supply voltage source V cc . 
     When the output signal V O  changes from the second voltage level (V cc ) to the first voltage level (0V), the driver signal V D , in response, falls to the voltage level of point C. This now is the first voltage level (0V) as determined by the doubling of the negative going incident wavefront of the driver signal arriving at the unterminated receiver input. As before described, the n-type MOS transistor M 1  turns off and the transmission line appears unterminated at the near and far ends. 
     Circuits incorporating receivers that have complementary MOS transistors in the input stage do not require sink or source steady state or D.C. current to the output terminal of the driver. However, designs incorporating terminating resistors or those that have bipolar junction transistors such as in transistor-transistor logic (TTL) require a level of D.C. current to operate correctly. Refer to FIG. 14 to discuss a third embodiment of this invention that can provide the self-limiting features described above and provide a steady state D.C. current. This embodiment contains the complementary driver configured with the basic driver circuits DRV H  and DRV L  as described in FIG. 9. A slew rate controlled driver DRV SRC , as described in FIG. 5, is placed in parallel with the complementary driver. The transistors M 7 , M 8 , M 9 , M 10  , M 11 , and M 12  respectively correspond with the transistors M 1 , M 2 , M 3 , M 4 , M 5 , and M 6  of the slew rate controlled driver described in FIG.  5 . The output signal V O  of the internal circuits Int Ckt is simultaneously the input to the complementary driver and the slew rate controlled driver DRV SRC . 
     The application of the self-limiting driver of this invention is generally in a communication interface that uses a low voltage swing. However, certain of the communication interfaces have high voltage swings. Refer now to FIG. 15 for a description of a fourth embodiment of this invention. The structure of the basic driver circuits DRV H  and DRV L  are as described in FIG.  9 . The n-type MOS transistor M 71  is placed between the output of the basic driver DRV L  and the transmission line T x . The source of the n-type MOS transistor M 71  is connected to the drains of the n-type MOS transistor M 1  and the p-type MOS transistor M 6 . The drain is connected to the near end of the transmission line T x . N-type MOS transistor M 71  is configured in a cascode arrangement with N-type MOS transistor M 1 . The gate of the n-type MOS transistor M 71  is connected to the power supply voltage source V cc . Transistor. 
     While this invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.