Abstract:
An automatic input threshold selector includes a maximum value level decision circuit, and an input threshold setting circuit. The maximum value level decision circuit decides, among m+1 level layers defined by m maximum value decision levels, a level layer to which the maximum value of an input signal belongs. The input threshold setting circuit sets an input threshold by selecting one of n input threshold candidates in response to the level layer to which the input signal maximum value belongs. These circuits are implemented as a simple combination of a voltage comparator, logic gates and the like. This makes it possible to solve a problem of a conventional automatic input threshold selector in that its circuit scale and power consumption is rather large because it includes a peak-hold circuit and a bottom-hold circuit.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an automatic input threshold selector for digitally controlling a signal with an unfixed amplitude level such as a mouse signal by a one-chip microcomputer. 
     2. Description of Related Art 
     A mouse, an input device of a personal computer and the like, includes a light emitting device, a photo-detector and a disk with slits, which is placed between them and rotates in response to the movement of the mouse. The photo-device receives the light emitted from the light emitting device through the disk, and outputs a sinusoidal signal as the disk rotates. The sinusoidal signal is supplied to the one-chip microcomputer or the like to undergo digital processing. The sinusoidal signal, however, has an unfixed amplitude level because of variations in characteristics of the light emitting device and photo-device or of the degradation due to long-term use thereof. Therefore, to achieve accurate digital signal processing of such a sinusoidal signal with an uncertain amplitude level as of the mouse signal, it is necessary to suitably set an input threshold in accordance with the amplitude level of the sinusoidal signal. 
     FIG. 19 is a schematic diagram showing an arrangement of a conventional automatic input threshold selector. In FIG. 19, the reference numeral  21  designates a peak-hold circuit for detecting a maximum value of an input signal IN and for holding it;  22  designates a bottom-hold circuit for detecting a minimum value of the input signal IN and for holding it;  23  designates a voltage comparator for comparing the input signal IN with a reference level VR given as a threshold voltage. The voltage comparator of the automatic input threshold selector receives at its non-inverting input terminal the input signal IN, and at its inverting input terminal the threshold voltage VR generated by dividing with resistors R 1  and R 2  the difference between the maximum voltage output from the peak-hold circuit  21  and the minimum voltage output from the bottom-hold circuit  22 . 
     Next, the operation of the conventional automatic input threshold selector will be described. 
     The voltage comparator  23  compares the input signal IN with the reference level VR. If the input signal IN is lower than the reference level VR, it outputs an “L” level signal as its output signal OUT, and if the input signal IN is higher than the reference level VR, it outputs an “H” level signal as the output signal OUT. 
     With the foregoing structure, the conventional automatic input threshold selector generates the reference level VR by dividing the difference between the maximum voltage and minimum voltage of the input signal held by the peak-hold circuit  21  and bottom-hold circuit  22 . This, however, presents a problem of requiring a rather bulk circuit arrangement and large power consumption, resulting in a cost increase and low performance, considering that the automatic input threshold selector is installed in a semiconductor integrated circuit fabricated by a CMOS process. 
     SUMMARY OF THE INVENTION 
     The present invention is implemented to solve the foregoing problem. It is therefore an object of the present invention to provide an automatic input threshold selector with a rather small size and low power consumption. This is achieved by selecting an input threshold from a few predetermined levels in response to a compared result of the input signal with predetermined reference levels. 
     According to one aspect of the present invention, there is provided an automatic input threshold selector comprising: level decision means for deciding, among a plurality of level layers determined by a predetermined number of decision levels, a level layer to which a level of an input signal belongs; and input threshold setting means for selecting, in response to the level layer decided by the level decision means, at least one of input threshold candidates from among a predetermined number of input threshold candidates. 
     Here, the level decision means may decide, among the plurality of level layers, a level layer to which one of a maximum value and a minimum value of the input signal belongs; and the input threshold setting means may select, in response to the level layer decided by the level decision means, at least one of n input threshold candidates, where n is a natural number. 
     The level decision means may comprise: a reference level selecting switch for selecting one of the predetermined number of decision levels as a reference level; a first voltage comparator for comparing the input signal with the reference level; a logic gate for carrying out on-off control of a clock signal in response to an output signal of the voltage comparator; a shift register for shifting, in response to an output signal of the logic gate, its output state every time the input signal crosses the reference level in one of rising and falling directions of the input signal; and a decoder for outputting signals for identifying the level layer of the input signal in response to output signals of the shift register, wherein the reference level selecting switch may select the reference level in accordance with the output signals of the decoder, the input threshold setting means may comprise: the decoder; and an input threshold selecting switch for selecting, in response to the outputs of the decoder, one of the n input threshold candidates as the input threshold, and the automatic input threshold selector may further comprise a second voltage comparator for comparing the input signal with the input threshold. 
     The level decision means may comprise: maximum value level decision means for deciding, among (j+1) level layers determined by j maximum value decision levels, a level layer to which a maximum value of the input signal belongs, where j is a natural number; and minimum value level decision means for deciding, among (m+1) level layers determined by m maximum value decision levels, a level layer to which a minimum value of the input signal belongs, where m is a natural number, wherein the input threshold setting means may set the input threshold by selecting one of the input threshold candidates in response to the level layer decided by the maximum value level decision means and to the level layer decided by the minimum value level decision means. 
     The input threshold setting means may comprise: a first input threshold selecting switch for selecting, in response to the level layer decided by the level decision means, one of the n input threshold candidates as a first input threshold; and a second input threshold selecting switch for selecting, in response to the level layer decided by the level decision means, another one of the n input threshold candidates as a second input threshold, and the automatic input threshold selector may further comprise Schmitt circuit means for comparing the input signal with the first input threshold when the input signal is rising, and with the second threshold when the input signal is falling. 
     The level decision means may comprise: maximum value level decision means for deciding, among (j+1) level layers determined by j maximum value decision levels, a level layer to which a maximum value of the input signal belongs, where j is a natural number; and minimum value level decision means for deciding, among (m+1) level layers determined by m maximum value decision levels, a level layer to which a minimum value of the input signal belongs, where m is a natural number, the input threshold setting means may comprise: first input threshold setting means for setting a first input threshold by selecting one of predetermined n 1  first input threshold candidates in response to the level layer decided by the maximum value level decision means, where n 1  is a natural number; and second input threshold setting means for setting a second input threshold by selecting one of predetermined n 2  second input threshold candidates in response to the level layer decided by the minimum value level decision means, where n 2  is a natural number, and the automatic input threshold selector may further comprise Schmitt circuit means for comparing the input signal with the first input threshold when the input signal is rising, and with the second threshold when the input signal is falling. 
     The level decision means may comprise: rising decision level identifying means for identifying, when the input signal is rising, a level the input signal exceeds among j rising decision levels, where j is a natural number; and falling decision level identifying means for identifying, when the input signal is falling, a level the input signal falls below among m falling decision levels, wherein the input threshold setting means may set, when the input signal is rising, the input threshold by selecting one of n input threshold candidates in response to the rising decision level decided by the rising decision level identifying means, where n is a natural number, and may set, when the input signal is falling, the input threshold by selecting one of the n input threshold candidates in response to the falling decision level decided by the falling decision level identifying means. 
     The automatic input threshold selector may further comprise input threshold initializing means for initializing by means of software the input threshold that has been set. 
     The automatic input threshold selector may further comprise a signal line, connected to a reset input terminal of the shift register, for supplying the shift register with a shift register initializing signal by means of software. 
     The level decision means may comprise level decision disabling means for halting operation of the level decision means by means of software. 
     The first voltage comparator may comprise an enable signal input terminal for supplying the first voltage comparator with an enable signal for locking an output of the first voltage comparator. 
     The input threshold setting means may comprise input threshold check means for checking, by means of software, the input threshold that has been set. 
     The input threshold setting means may comprise a register for storing the outputs of the decoder. 
     The input threshold setting means may comprise means for setting the input threshold at a desired value by means of software. 
     The input threshold setting means may comprise a register for storing a desired value determined by means of software, and a selector for selecting one of the output of the decoder and an output of the register for controlling the input threshold selecting switch. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram showing a configuration of an embodiment 1 of the automatic input threshold selector in accordance with the present invention; 
     FIG. 2 is a diagram showing an example of waveforms of an input signal IN supplied to the automatic input threshold selector of FIG. 1; 
     FIG. 3 is a graph illustrating relationships between a maximum value VIP of the input signal IN and the input threshold VT 1  of FIG. 1; 
     FIG. 4 is a circuit diagram showing a configuration of an embodiment 2 of the automatic input threshold selector in accordance with the present invention; 
     FIG. 5 is a diagram showing an example of waveforms of the input signal IN supplied to the automatic input threshold selector of FIG. 4; 
     FIG. 6 is a graph illustrating relationships between a minimum value VIB of the input signal IN and the input threshold VT 2  of FIG. 4; 
     FIG. 7 is a circuit diagram showing a configuration of an embodiment 3 of the automatic input threshold selector in accordance with the present invention; 
     FIG. 8 is a table illustrating relationships between a maximum value VIP and minimum value VIB of the input signal IN and the input threshold VT 3  of FIG. 7; 
     FIG. 9 is a circuit diagram showing a configuration of an embodiment 4 of the automatic input threshold selector in accordance with the present invention; 
     FIG. 10 is a diagram illustrating an example waveforms for explaining the operation of the embodiment 4 of the automatic input threshold selector; 
     FIG. 11 is a circuit diagram showing a configuration of an embodiment 5 of the automatic input threshold selector in accordance with the present invention; 
     FIG. 12 is a diagram illustrating an example of waveforms for explaining the operation of the embodiment 5 of the automatic input threshold selector; 
     FIG. 13 is a circuit diagram showing a configuration of an embodiment 6 of the automatic input threshold selector in accordance with the present invention; 
     FIG. 14 is a diagram illustrating an example of waveforms of the input signal IN and output signal OUT together with the input threshold VT 6  in the embodiment 6 of the automatic input threshold selector; 
     FIG. 15 is a circuit diagram showing a configuration of an embodiment  7  of the automatic input threshold selector in accordance with the present invention; 
     FIG. 16 is a circuit diagram showing a configuration of an embodiment 8 of the automatic input threshold selector in accordance with the present invention; 
     FIG. 17 is a circuit diagram showing a configuration of an embodiment 9 of the automatic input threshold selector in accordance with the present invention; 
     FIG. 18 is a circuit diagram showing a configuration of an embodiment 10 of the automatic input threshold selector in accordance with the present invention; and 
     FIG. 19 is a schematic diagram showing a configuration of a conventional automatic input threshold selector. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The embodiments in accordance with the present invention will now be described with reference to the accompanying drawings. 
     Emdodiment 1 
     FIG. 1 is a circuit diagram showing a configuration of an embodiment 1 of the automatic input threshold selector in accordance with the present invention. The present embodiment 1 of the automatic input threshold selector is characterized by setting its input threshold VT 1  in accordance with a decision result of a level layer to which the maximum value of the input signal belongs. In FIG. 1, the reference numeral  1  designates a voltage comparator;  2  designates a two-input AND gate;  3  designates a shift register including three D flip-flops FF 1 , FF 2  and FF 3 ;  4  designates a decoder including three inverters G 2 , G 3  and G 5  and two-input AND gates G 4  and G 6 ;  5  designates a reference level selecting switch;  6  designates an input threshold selecting switch; and  7  designates a voltage comparator. The symbol IN designates an input signal; OUT designates an output signal; CLK designates a clock signal; RST designates a reset signal; VR 1  designates a reference level; VT 1  designates an input threshold; VR 11 , VR 12  and VR 13  each designate a maximum value decision level; and VT 11 , VT 12 , VT 13  and VT 14  each designate an input threshold candidate. Here, the maximum value decision levels are assumed to have a relationship VR 11  &lt;VR 12 &lt;VR 13 . 
     Next, functions of the individual components will be described. 
     The voltage comparator  1  compares the level of the input signal IN with that of the reference level VR 1 , and outputs an “L” level signal when the level of the input signal IN is lower than the reference level VR 1 , and an “H” level signal when the level of the input signal IN is higher than the reference level VR 1 . To achieve this, the voltage comparator  1  receives at its non-inverting input terminal the input signal IN, and at its inverting input terminal the reference level VR 1 . The AND gate  2  outputs a logical multiplication of the output of the voltage comparator  1  and the output of the clock signal CLK. In the case where the clock signal CLK is a steady signal, the AND gate  2  disables the output of the clock signal CLK when the output of the voltage comparator  1  is at the “L” level, and enables the output of the clock signal CLK when the output of the voltage comparator  1  is at the “H” level. In this case, the frequency of the clock signal CLK is about 1 MHz, for example. 
     The shift register  3  has its data input terminal connected to the VCC level, that is, to the “H” level signal, its clock input terminal connected to the output of the AND gate  2 , and its reset input terminal connected to a reset signal RST. The initial value of the shift register  3  is supplied by the reset signal RST (RST=“H”), in which case, all the outputs Q 1 , Q 2  and Q 3  of the D flip-flops FF 1 , FF 2  and FF 3  in the shift register  3  are placed to the “L” level (Q 1 =Q 2 =Q 3 =“L”). When the reset is released in this state (RST=“L”) and the rising edge of the clock signal CLK is supplied to the clock input terminal, Q 1  rises to “H” (Q 1 =“H” and Q 2 =Q 3 =“L”). A next rising edge will place Q 2  at “H” (Q 1 =Q 2 =“H” and Q 3 =“L”), and the following rising edge will place Q 3  at “H” (Q 1 =Q 2 =Q 3 =“H”). Afterward, no rising edges of the clock signal CLK will change the “H” level of the outputs Q 1 , Q 2  and Q 3  of the D flip-flops FF 1 , FF 2  and FF 3 . Thus, the shift register  3  outputs the total of four output patterns: a first output pattern (Q 1 =Q 2 =Q 3 =“L”), second output pattern (Q 1 =“H” and Q 2 =Q 3 =“L”), a third output pattern (Q 1 =Q 2 =“H” and Q 3 =“L”) and a fourth output pattern (Q 1 =Q 2 =Q 3 =“H”). 
     The decoder  4  receives the outputs Q 1 , Q 2  and Q 3  from the shift register  3 , and determines its outputs S 1 , S 2 , S 3 , S 3 ′ and S 4  in response to the output patterns. The decoder  4  outputs S 1 =“H” and S 2 =S 3 =S 3 ′=S 4 =“L” in response to the first output pattern (Q 1 =Q 2 =Q 3 =“L”) supplied from the shift register  3 ; outputs S 2 =“H” and S 1 =S 3 =S 3 ′=S 4 =“L” in response to the second output pattern (Q 1 =“H” and Q 2 =Q 3 =“L”); outputs S 3 =S 3 ′=“H” and S 1 =S 2 =S 4 =“L” in response to the third output pattern (Q 1 =Q 2 =“H” and Q 3 =“L”), and outputs S 3 ′=S 4 =“H” and S 1 =S 2 =S 3 =“L” in response to the fourth output pattern (Q 1 =Q 2 =Q 3 =“H”). 
     The switch  5  selects one of the maximum value decision levels VR 11 , VR 12  and VR 13  as the reference level VR 1  in response to the outputs S 1 , S 2  and S 3 ′ from the decoder  4 , only one of which takes “H” level as described above. Accordingly, the switch  5  supplies as the reference level VR 1  the decision level VR 11  when S 1  is “H”, VR 12  when S 2  is “H”, and VR 13  when S 3 ′ is “H”. 
     On the other hand, the switch  6  selects one of the input thresholds VT 11 , VT 12 , VT 13  and VT 14  as the input threshold VT 1  in response to the outputs S 1 , S 2 , S 3  and S 4  of the decoder  4 , only one of which takes the “H” level as described above. The switch  6  outputs as the input threshold VT 1  the input threshold VT 11  when S 1  is “H”, VT 12  when S 2  is “H”, VT 13  when S 3  is “H” and VT  14  when S 4  is “H”. 
     The voltage comparator  7  compares the level of the input signal IN with that of the input threshold VT 1 , and supplies the compared result as the output signal OUT. Specifically, the voltage comparator  7  produces the output signal OUT of the “L” level when the input signal IN is lower than the input threshold VT 1 , and produces the output signal OUT of the “H” level when the input signal IN is higher than the input threshold VT 1 . To achieve this, the input signal IN is supplied to the non-inverting input terminal of the voltage comparator  7 , and the input threshold VT 1  is supplied to the inverting input terminal. Thus, the voltage comparator  7  functions for the input signal IN as an input buffer with the input threshold of VT 1 . 
     Next, the operation of the present embodiment 1 of the automatic input threshold selector will be described. FIG. 2 illustrates an example of waveforms of the input signal IN to the automatic input threshold selector. The input signal IN is a sinusoidal wave with a frequency of about 5 kHz at the maximum, for example. In FIG. 2, VIP designates the maximum value of the input signal IN. FIG. 3 is a graph illustrating relationships between the maximum value VIP of the input signal IN and the input threshold VT 1 . In the present embodiment 1, the input threshold VT 1  is determined such as VT 1 =VT 11  when VIP&lt;VR 11 , VT 1 =VT 12  when VR 11 &lt;VIP&lt;VR 12 , VT 1 =VT 13  when VR 12 &lt;VIP&lt;VR 13 , and VT 1 =VT 14  when VR 13 &lt;VIP. 
     In addition, the initial value of the present embodiment 1 as shown in FIG. 1 is provided by the reset signal RST (RST =“H”). Because the output of the shift register  3  is at the first output pattern (Q 1 =Q 2 =Q 3 =“L”) in this case, the decoder  4  outputs S 1 =“H” and S 2 =S 3 ′=S 3 =S 4 =“L”, so that the switch  5  selects the maximum value decision level VR 11  as the reference level VR 1  (VR 1 =VR 11 ), and the switch  6  selects the input threshold VT 11  as the input threshold VT 1  (VT 1 =VT 11 ). 
     In response to the release of the reset (RST=“L”), the automatic input threshold selector becomes active, and first, the voltage comparator  1  compares the level of the input signal IN with that of the reference level VR 1  (=VR 11 ). When the maximum value VIP of the input signal IN is lower than the reference level VR 11  (VIP&lt;VR 11 ), the voltage comparator  1  outputs the “L” level signal, and hence the AND gate  2  disables the output of the clock signal CLK. Accordingly, shift register  3  maintains its initial state (Q 1 =Q 2 =Q 3 =“L”) because the rising edge of the clock signal CLK is not supplied to the clock input terminal of the shift register  3 . As a result, the switches  5  and  6  also maintain their initial states (VR 1 =VR 11  and VT 1  =VT 11 ). 
     When the maximum value VIP of the input signal IN becomes higher than the reference level VR 11  (VIP&gt;VR 11 ), the voltage comparator  1  outputs the “H” level signal at the time the level of the input signal IN exceeds the reference level VR 11 , so that the AND gate  2  enables the output of the clock signal CLK. When the rising edge of the clock signal CLK is supplied to the clock input terminal of the shift register  3  through the AND gate  2 , the shift register  3  takes the second output pattern (Q 1 =“H” and Q 2 =Q 3 =“L”), and the decoder  4  outputs S 2 =“H” and S 1  =S 3 =S 3 ′=S 4 =“L”. Thus, the switch  5  selects the maximum value decision level VR 12  as the reference level VR 1  (VR 1 =VR 12 ), and the switch  6  selects the input threshold VT 12  as the input threshold VT 1  (VT 1 =VT 12 ). 
     In response to the change of the reference level VR 1  as described above, the voltage comparator  1  compares the level of the input signal IN with the reference level VR 1  (=VR 12 ). When the maximum value VIP of the input signal IN is lower than the reference level VR 12  (VR 11 &lt;VIP&lt;VR 12 ), the voltage comparator  1  outputs the “L” level signal, and the AND gate  2  disables the output of the clock signal CLK. Therefore, the rising edge of the clock signal CLK is not supplied to the clock input terminal of the shift register  3 , so that the shift register  3  maintains its output state (Q 1 =“H” and Q 2 =Q 3 =“L”), and the switches  5  and  6  also maintain their current states (VR 1 =VR 12  and VT 1  =VT 12 ). 
     When the maximum value VIP of the input signal IN becomes higher than the reference level VR 12  (VIP&gt;VR 12 ), the voltage comparator  1  outputs the “H” level signal at the time the level of the input signal IN exceeds the reference level VR 12 , and the AND gate  2  enables the output of the clock signal CLK. Thus, in response to the rising edge of the clock signal CLK supplied to the clock input terminal of the shift register  3  via the AND gate  2 , the shift register  3  takes the third output pattern (Q 1  =Q 2 =“H” and Q 3 =“L”), and the decoder  4  outputs S 3 =S 3 ′=“H” and S 1 =S 2 =S 4 =“L”. In this case, the switch  5  selects the maximum value decision level VR 13  as the reference level VR 1  (VR 1 =VR 13 ), and the switch  6  selects the input threshold VT 13  as the input threshold VT 1  (VT 1 =VT 13 ). 
     In response to the change of the reference level VR 1  as described above, the voltage comparator  1  compares the level of the input signal IN with the modified reference level VR 1  (=VR 13 ) When the maximum value VIP of the input signal IN is lower than the reference level VR 13  (VR 12 &lt;VIP&lt;VR 13 ), the voltage comparator  1  outputs the “L” level signal, and the AND gate  2  disables the output of the clock signal CLK. Therefore, the rising edge of the clock signal CLK is not supplied to the clock input terminal of the shift register  3 , so that the shift register  3  maintains its output state (Q 1 =Q 2 =“H” and Q 3 =“L”), and the switches  5  and  6  also maintain their current states (VR 1  VR 13  and VT 1 =VT 13 ). 
     When the maximum value VIP of the input signal IN becomes higher than the reference level VR 13  (VIP&gt;VR 13 ), the voltage comparator  1  outputs the “H” level signal when the level of the input signal IN exceeds the reference level VR 13 , and the AND gate  2  enables the output of the clock signal CLK. Thus, in response to the rising edge of the clock signal CLK supplied to the clock input terminal of the shift register  3  via the AND gate  2 , the shift register  3  takes the fourth output pattern (Q 1 =Q 2 =Q 3 =“H”), and the decoder  4  outputs S 3 ′=S 4 =“H” and S 1  =S 2 =S 3 =“L”. In this case, the switch  5  maintains selecting the maximum value decision level VR 13  as the reference level VR 1  (VR 1 =VR 13 ), and the switch  6  selects the input threshold VT 14  as the input threshold VT 1  (VT 1 =VT 14 ). 
     Once this state (VR 1 =VR 13  and VT 1 =VT 14 ) has been established, supply of further rising edges of the clock signal CLK to the clock input terminal of the shift register  3  does not change the output state of the shift register  3 . As a result, the selector maintains the input threshold VT 1  at the level VT 14  until the reset input (RST=“H”) is applied. 
     As described above, according to the present embodiment 1, the voltage comparator  1 , AND gate  2 , shift register  3 , decoder  4  and reference level selecting switch  5  constitute a maximum value level decision means; and the decoder  4  and input threshold selecting switch  6  constitute an input threshold setting means for setting the input threshold VT 1  in response to the level layer to which the maximum value VIP of the input signal IN belongs. This offers an advantage of being able to implement a circuit that can automatically set the input threshold in response to the level layer to which the maximum value of the input signal belongs. 
     In addition, the automatic input threshold selector can be constructed rather easily in the form of a combination of the voltage comparators and logical gates and the like. This offers an advantage of being able to implement a small size, low power consumption circuit. 
     Incidentally, although the present embodiment 1 of the automatic input threshold selector as shown in FIG. 1 has three maximum value decision levels, and four input threshold candidates, it is obvious that their numbers are not limited to these numbers, and can be determined at any numbers according to the performance required of the automatic input threshold selector. 
     Embodiment 2 
     FIG. 4 is a circuit diagram showing a configuration of an embodiment 2 of the automatic input threshold selector in accordance with the present invention. The present embodiment  2  of the automatic input threshold selector is characterized by setting its input threshold in accordance with a decision result of a level layer to which the minimum value of the input signal belongs. In FIG. 4, the same reference numerals designate the same or like portions to those of FIG. 1, and hence the description thereof is omitted here. The present embodiment 2 differs from the foregoing embodiment 1 in that the voltage comparator  1  receives a reference level VR 2  at its non-inverting input terminal, and the input signal INat the inverting input terminal. In FIG. 4, the reference symbol VR 2  designates the reference level; VT 2  designates an input threshold; VR 21 , VR 22  and VR 23  each designate a minimum value decision level; and VT 21 , VT 22 , VT 23  and VT 24  each designate an input threshold candidate. Here, the minimum value decision levels are assumed to have a relationship VR 21 &gt;VR 22 &gt;VR 23 . 
     Next, functions of the individual components will be described. 
     The voltage comparator  1  compares the level of the input signal IN with the reference level VR 2 , and outputs the “L” level signal when the level of the input signal IN is higher than the reference level VR 2 , and the “H” level signal when the level of the input signal IN is lower than the reference level VR 2 . 
     The switch  5  selects one of the minimum value decision levels VR 21 , VR 22  and VR 23  as the reference level VR 2  in response to the outputs S 1 , S 2  and S 3 ′ from the decoder  4 , only one of which takes the “H” level as described above. Thus, the switch  5  supplies as the reference level VR 2  the decision level VR 21  when S 1  is “H”, VR 22  when S 2  is “H”, and VR 23  when S 3 ′ is “H”. 
     On the other hand, the switch  6  selects one of the input threshold candidates VT 21 , VT 22 , VT 23  and VT 24  as the input threshold VT 2  in response to the outputs S 1 , S 2 , S 3  and S 4  of the decoder  4 , only one of which takes the “H” level as described above. Thus, the switch  6  outputs as the input threshold VT 2  the input threshold candidate V 211  when S 1  is “H”, VT 22  when S 2  is “H”, VT 23  when S 3  is “H” and VT  24  when S 4  is “H”. 
     Since the functions of the AND gate  2 , shift register  3 , decoder  4  and voltage comparator  7  as shown in FIG. 4 are the same as those of their counterparts of the foregoing embodiment 1 of the automatic input threshold selector as shown in FIG. 1, the description thereof is omitted here. 
     FIG. 5 shows an example of waveforms of the input signal IN to the automatic input threshold selector. In FIG. 5, the minimum value of the input signal IN is designated by VIB. FIG. 6 is a graph illustrating relationships between the minimum value VIB of the input signal IN and the input threshold VT 2 . As illustrated in FIG. 6, in the present embodiment 2, the input threshold VT 2  is determined such as VT 2 =VT 21  when VIB&gt;VR 21 , VT 2 =VT 22  when VR 21 &gt;VIB&gt;VR 22 , VT 2 =VT 23  when VR 22 &gt;VIB &gt;VR 23 , and VT 2 =VT 24  when VR 23 &gt;VIB. 
     The present embodiment 2 differs from the foregoing embodiment 1 in that the voltage comparator  1  outputs the “H” level signal when the level of the input signal IN is lower than the reference level VR 2 , and that the value of the reference level VR 2  is changed in accordance with the new pattern output from the shift register  3 . Since the remaining operation is the same as that of the embodiment 1, the description of the operation of the present embodiment 2 will be omitted. In brief, although the foregoing embodiment 1 sets the input threshold by deciding the level layer to which the maximum value VIP of the input signal IN belongs, the present embodiment 2 sets the input threshold by deciding the level layer to which the minimum value VIB of the input signal IN belongs. 
     As described above, according to the present embodiment 2, the voltage comparator  1 , AND gate  2 , shift register  3 , decoder  4  and reference level selecting switch  5  constitute a minimum value level decision means; and the decoder  4  and input threshold selecting switch  6  constitute an input threshold setting means for setting the input threshold VT 2  in response to the level layer to which the minimum value VIB of the input signal IN belongs. This offers an advantage of being able to implement a circuit that can automatically set the input threshold in response to the level layer to which the minimum value of the input signal belongs. 
     In addition, the automatic input threshold selector can be constructed rather easily in the form of a combination of the voltage comparators, logical gates and the like. This offers an advantage of being able to implement a small size, low power consumption circuit. 
     Incidentally, although the present embodiment 2 of the automatic input threshold selector as shown in FIG. 4 has three minimum value decision levels, and four input threshold candidates, it is obvious that their numbers are not limited to these numbers, and can be determined at any numbers according to the performance required of the automatic input threshold selector. 
     Embodiment 3 
     FIG. 7 is a block diagram showing an embodiment 3 of the automatic input threshold selector in accordance with the present invention. The present embodiment 3 is characterized by setting the input threshold in accordance with the results of deciding the level layer to which the maximum value of the input signal belongs and the level layer to which the minimum value thereof belongs. 
     In FIG. 7, a voltage comparator  1   a , AND gate  2   a , shift register  3   a , decoder  4   a  and switch  5   a  are the same as the voltage comparator  1 , AND gate  2 , shift register  3 , decoder  4  and switch  5  of the foregoing embodiment 1 as shown in FIG. 1; and a voltage comparator  1   b , AND gate  2   b , shift register  3   b , decoder  4   b , switch  5   b  are the same as the voltage comparator  1 , AND gate  2 , shift register  3 , decoder  4  and switch  5  of the foregoing embodiment 2 as shown in FIG.  4 . Thus, the description thereof is omitted here. The present embodiment 3 of the automatic input threshold selector is a combination of the embodiment 1 as shown in FIG.  1  and the embodiment 2 as shown in FIG.  4 . It decides the level layer to which the maximum value of the input signal IN belongs by the voltage comparator  1   a , AND gate  2   a , shift register  3   a , decoder  4   a  and switch  5   a , and the level layer to which the minimum value of the input signal IN belongs by the voltage comparator  1   b , AND gate  2   b , shift register  3   b , decoder  4   b  and switch  5   b.    
     In FIG. 7, VR 3   a  and VR 3   b  each designate a reference level, VT 3  designates an input threshold, VR 31   a , VR 32   a  and VR 33   a  each designate a maximum value decision level, VR 31   b , VR 32   b  and VR 33   b  each designate a minimum value decision level, VT 31 , VT 32 , VT 33 , VT 34 , VT 35 , VT 36  and VT 37  each designate an input threshold candidate. The maximum value decision levels have a relation VR 31   a &lt;VR 32   a &lt;VR 33   a , whereas the minimum value decision levels have a relation VR 31   b &gt;VR 32   b &gt;VR 33   b.    
     The reference numeral  8  designates a multiplexer. The multiplexer  8  has its input section connected to the outputs S 1   a , S 2   a , S 3   a  and S 4   a  of the decoder  4   a  and to the outputs S 1   b , S 2   b , S 3   b  and S 4   b  of the decoder  4   b , and selects one of the input thresholds VT 31 , VT 32 , VT 33 , VT 34 , VT 35 , VT 36  and VT 37  as the input threshold VT 3  in accordance with the input values. 
     Next, the operation of the embodiment 3 of the automatic input threshold selector will be described. The outputs S 1   a , S 2   a , S 3   a  and S 4   a  from the decoder  4   a  are determined by the maximum value VIP of the input signal IN such as S 1   a =“H” and S 2   a =S 3   a  =S 4   a =“L” when VIP&lt;VR 31   a ; S 2   a =“H” and S 1   a =S 3   a =S 4   a =“L” when VR 31   a &lt;VIP&lt;VR 32   a ; S 3   a =“H” and S 1   a =S 2   a =S 4   a =“L” when VR 32   a &lt;VIP&lt;VR 33   a , and S 4   a =“H” and S 1   a =S 2   a =S 3   a  =“L” when VR 33   a &lt;VIP. On the other hand, the outputs S 1   b , S 2   b , S 3   b  and S 4   b  from the decoder  4   b  are determined by the minimum value VIB of the input signal IN such as S 1   b =“H” and S 2   b =S 3   b =S 4   b =“L” when VIB&gt;VR 31   b ; S 2   b =“H” and S 1   b =S 3   b =S 4   b =“L” when VR 31   b &gt;VIB&gt;VR 32   b ; S 3   b =“H” and S 1   b =S 2   b =S 4   b =“L” when VR 32   b &gt;VIB&gt;VR 33   b ; and S 4   b =“H” and S 1   b =S 2   b =S 3   b  “L” when VR 33   b &gt;VIB. 
     FIG. 8 is a table showing relationships between the maximum value VIP and the minimum value VIB of the input signal IN, and the input threshold VT 3  in the present embodiment 3 of the automatic input threshold selector. As shown in FIG. 8, the input threshold VT 3  is categorized in accordance with the level layer to which the maximum value of the input signal IN belongs and the level layer to which the minimum value thereof belongs. Specifically, the multiplexer  8  selects one of the input threshold candidates VT 31 , VT 32 , VT 33 , VT 34 , VT 35 , VT 36  and VT 37  as the input threshold VT 3  in accordance with the outputs S 1   a , S 2   a , S 3   a  and S 4   a  of the decoder  4   a , which are decided by the maximum value VIP of the input signal IN, and with the outputs S 1   b , S 2   b , S 3   b  and S 4   b  of the decoder  4   b , which are decided by the minimum value VIB of the input signal IN, such that the relationships as shown in FIG. 8 are met. The voltage comparator  7  functions as an input buffer whose input threshold is VT 3  for the input signal IN. 
     As described above, the present embodiment 3 is configured such that the voltage comparator  1   a , AND gate  2   a , shift register  3   a , decoder  4   a  and reference level selecting switch  5   a  constitute a maximum value level decision means; the voltage comparator  1   b , AND gate  2   b , shift register  3   b , decoder  4   b  and reference level selecting switch  5   b  constitute a minimum value level decision means; and the decoder  4   a , decoder  4   b  and multiplexer  8  constitute an input threshold setting means for setting the input threshold VT 3  in accordance with the level layer to which the maximum value VIP of the input signal IN belongs and the level layer to which the minimum value VIB of the input signal IN belongs. This offers an advantage of being able to implement a circuit that can automatically set the input threshold in accordance with the level layer to which the input signal maximum value belongs, and with level layer to which the input signal minimum value belongs. 
     In addition, the automatic input threshold selector can be constructed rather easily in the form of a combination of the voltage comparators, logical gates and the like. This offers an advantage of being able to implement a small size, low power consumption circuit. 
     Incidentally, although the present embodiment 3 of the automatic input threshold selector as shown in FIG. 7 has three maximum value decision levels, three minimum value decision levels, and seven input threshold candidates, it is obvious that their numbers are not limited to these numbers, and can be determined at any numbers according to the performance required for the automatic input threshold selector. 
     Embodiment 4 
     FIG. 9 is a block diagram showing an embodiment 4 of the automatic input threshold selector in accordance with the present invention. The present embodiment 4 of the automatic input threshold selector is characterized in that it configures a Schmitt circuit by setting two input thresholds in accordance with the decision result of the level layer to which the maximum value of the input signal belongs. In FIG. 9, the same reference numerals designate the same or like portions to those of FIG.  1  and the description thereof is omitted here. In FIG. 9, switches  6   a  and  6   b  are analogous to the switch  6  as shown in FIG. 1, and voltage comparators  7   a  and  7   b  are analogous to the voltage comparator  7  as shown in FIG.  1 . 
     In FIG. 9, the reference numeral  9  designates a composite logic gate consisting of a two-input AND gate and a two-input OR gate. Reference symbols VT 4   a  designates a first input threshold, VT 4   b  designates a second input threshold, VT 41   a , VT 42   a , VT 43   a  and VT 44   a  each designate a first input threshold candidate, and VT 41   b , VT 42   b , VT 43   b  and VT 44   b  each designate a second input threshold candidate. Here, the input threshold candidates have relationships of VT 41   a &gt;VT 41   b , VT 42   a &gt;VT 42   b , and VT 43   a &gt;VT 43   b  and VT 44   a &gt;VT 44   b.    
     Next, functions of the individual components will be described. 
     The switch  6   a  selects one of the first input threshold candidates VT 41   a , VT 42   a , VT 43   a  and VT 44   a  as the first input threshold VT 4   a  under the control of the outputs S 1 , S 2 , S 3  and S 4  of the decoder  4 , only one of which takes the “H” level without exception. More specifically, the switch  6   a  selects VT 41   a  when S 1  is “H”, VT 42   a  when S 2  is “H”, VT 43   a  when S 3  is “H” and VT 44   a  when S 4  is “H”, as the first input threshold VT 4   a.    
     Likewise, the switch  6   b  selects one of the second input threshold candidates VT 41   b , VT 42   b , VT 43   b  and VT 44   b  as the second input threshold VT 4   b  under the control of the outputs S 1 , S 2 , S 3  and S 4  of the decoder  4 , only one of which takes the “H” level without exception as in the case of the switch  6   a . More specifically, the switch  6   b  selects VT 41   b  when S 1  is “H”, VT 42   b  when S 2  is “H”, VT 43   b  when S 3  is “H” and VT 44   b  when S 4  is “H”, as the second input threshold VT 4   b.    
     The outputs S 1 , S 2 , S 3  and S 4  of the decoder  4  are determined by the maximum value VIP of the input signal IN such as VT 4   a =VT 41   a  and VT 4   b =VT 41   b  when VIP&lt;VR 11 , VT 4   a =VT 42   a  and VT 4   b  =VT 42   b  when VR 11 &lt;VIP&lt;VR 12 , VT 4   a =VT 43   a  and VT 4   b =VT 43   b  when VR 12 &lt;VIP&lt;VR 13 , and VT 4   a =VT 44   a  and VT 4   b =VT 44   b  when VR 13 &lt;VIP. In other words, the first input threshold VT 4   a  and second input threshold VT 4   b  always hold the relationships of VT 4   a &gt;VT 4   b  as illustrated in FIG.  10 . 
     The voltage comparator  7   a  compares the level of the input signal IN with that of the first input threshold VT 4   a , thereby functioning as an input buffer with the input threshold VT 4   a . Likewise, the voltage comparator  7   b  compares the level of the input signal IN with that of the second input threshold VT 4   b , thereby functioning as an input buffer with the input threshold VT 4   b.    
     The composite logic gate  9 , receiving the logical outputs from the voltage comparators  7   a  and  7   b , produces an output signal OUT. Because the input threshold VT 4   a  of the voltage comparator  7   a  is higher than the input threshold VT 4   b  of the voltage comparator  7   b , the output signal OUT of the composite logic gate  9  is determined by the output state of the voltage comparator  7   a  when the input signal IN rises (when the output signal OUT is placed at the “L” level initially), and by the output state of the voltage comparator  7   b  when the input signal IN falls (when the output signal OUT is placed at the “H” level initially), thereby constructing the Schmitt circuit. 
     Since the functions of the voltage comparator  1 , AND gate  2 , shift register  3  and switch  5  as shown in FIG. 9 are the same as those of the foregoing embodiment 1 as shown in FIG. 1, the description thereof is omitted here. 
     Next, the operation of the embodiment 4 of the automatic input threshold selector in accordance with the present invention will be described. As illustrated in FIG. 10, when the input signal IN makes a transition from the low to high level, the output signal OUT changes its level from the “L” level to the “H” level when the input signal IN exceeds the first input threshold VT 4   a . On the other hand, when the input signal IN makes a transition from the high to low level, the output signal OUT changes its level from the “H” level to the “L” level when the input signal IN falls below the second input threshold VT 4   b.    
     As described above, according to the present embodiment 4, the voltage comparator  1 , AND gate  2 , shift register  3 , decoder  4  and reference level selecting switch  5  constitute a maximum value level decision means; the decoder  4 , and input threshold selecting switches  6   a  and  6   b  constitute an input threshold setting means for setting the two input thresholds VT 4   a  and VT 4   b  in accordance with level layer to which the maximum value VIP of the input signal IN belongs; and the voltage comparators  7   a  and  7   b  and composite logic gate  9  constitute the Schmitt circuit that uses the input threshold VT 4   a  when the input signal rises, and the input threshold VT 4   b  when the input signal falls. This offers an advantage of being able to implement a circuit that can automatically set the two input thresholds in accordance with the level layer to which the input signal maximum value belongs and that can provide the Schmitt circuit using the two input thresholds. 
     In addition, the automatic input threshold selector can be constructed rather easily in the form of a combination of the voltage comparators, logical gates and the like. This offers an advantage of being able to implement a small size, low power consumption circuit. 
     Incidentally, although the present embodiment 4 of the automatic input threshold selector as shown in FIG. 9 constructs the Schmitt circuit by modifying the foregoing embodiment 1, the Schmitt circuit can also be constructed by modifying the foregoing embodiment 2. 
     Embodiment 5 
     FIG. 11 is a block diagram showing an embodiment 5 of the automatic input threshold selector in accordance with the present invention. The present embodiment 5 is characterized by constituting a Schmitt circuit using two input thresholds that are set as the results of the decision of the level layers to which the maximum value and minimum value of the input signal belongs. In FIG. 11, the circuit composed of the voltage comparator  1   a , AND gate  2   a , shift register  3   a , decoder  4   a , switches  5   a  and  6   a  and voltage comparator  7   a  has the same structure and functions as the foregoing embodiment 1 of the automatic input threshold selector; and the circuit composed of the voltage comparator  1   b , AND gate  2   b , shift register  3   b , decoder  4   b , switches  5   b  and  6   b  and voltage comparator  7   b  has the same structure and functions as the foregoing embodiment 2 of the automatic input threshold selector. In addition, the reference numeral  9  designates the same composite logic gate as that of FIG.  9 . 
     In FIG. 11, VR 5   a  designates a first reference level; VR 5   b  designates a second reference level; VR 51   a , VR 52   a  and VR 53   a  each designate a maximum value decision level; VR 51   b , VR 52   b  and VR 53   b  each designate a minimum value decision level; VT 5   a  designates a first input threshold; VT 5   b  designates a second input threshold; VT 51   a , VT 52   a , VT 53   a  and VT 54   a  each designate a first input threshold candidate; and VT 51   b , VT 52   b , VT 53   b  and VT 54   b  each designate a second input threshold candidate. It is assumed here that the maximum value decision levels have a relation VR 51   a &lt;VR 52   a &lt;VR 53   a , and the minimum value decision levels have a relation VR 51   b &gt;VR 52   b &gt;VR 53   b . In addition, the input thresholds VT 5   a  and VT 5   b  are set to have a relation VT 5   a &gt;VT 5   b  as in the foregoing embodiment 4. 
     The voltage comparator  7   a  functions as an input buffer with the input threshold VT 5   a , and the voltage comparator  7   b  functions as the input buffer with the input threshold VT 5   b . In addition, since the relation VT 5   a &gt;VT 5   b  holds, the Schmitt circuit is constructed by supplying the composite logic gate  9  with the output signals of the voltage comparators  7   a  and  7   b.    
     Next, the operation of the embodiment 5 of the automatic input threshold selector in accordance with the present invention will be described. FIG. 12 is a diagram illustrating an example of signal waveforms in the present embodiment 5. As illustrated in FIG. 12, when the input signal IN makes a transition from the low to high level, the output signal OUT changes its level from the “L” to “H” level when the input signal IN exceeds the first input threshold VT 5   a . On the other hand, when the input signal IN makes a transition from the high to low level, the output signal OUT changes from the “H” to “L” level when the input signal IN falls below the second input threshold VT 5   b.    
     As described above, according to the present embodiment 5, the voltage comparator  1   a , AND gate  2   a , shift register  3   a , decoder  4   a  and reference level selecting switch  5   a  constitute a maximum value level decision means; the voltage comparator  1   b , AND gate  2   b , shift register  3   b , decoder  4   b  and reference level selecting switch  5   b  constitute a minimum value level decision means; the decoder  4   a  and input threshold selecting switch  6   a  constitute a first input threshold setting means for setting the input threshold VT 5   a  in accordance with the level layer to which the maximum value VIP of the input signal IN belongs; the decoder  4   b  and input threshold selecting switch  6   b  constitute a second input threshold setting means for setting the input threshold VT 5   b  in accordance with the level layer to which the minimum value VIB of the input signal IN belongs; and the voltage comparators  7   a  and  7   b  and composite logic gate  9  constitute a Schmitt circuit configuration means that uses the input threshold VT 5   a  when the input signal rises, and the input threshold VT 5   b  when the input signal falls. This offers an advantage of being able to provide a circuit that can implement the Schmitt circuit by using the first input threshold automatically set in accordance with the level layer to which the maximum value of the input signal belongs and the second input threshold automatically set in accordance with the level layer to which the minimum value of the input signal belongs. 
     In addition, the automatic input threshold selector can be constructed rather easily in the form of a combination of the voltage comparators, logical gates and the like. This offers an advantage of being able to implement a small size, low power consumption circuit. 
     Incidentally, although the present embodiment 5 of the automatic input threshold selector as shown in FIG. 11 has three maximum value decision levels, three minimum value decision levels, four first input threshold candidates, and four second input threshold candidates, it is obvious that their numbers are not limited to these numbers, and can be determined at any numbers according to the performance required of the automatic input threshold selector. 
     Embodiment 6 
     FIG. 13 is a circuit diagram showing an embodiment 6 of the automatic input threshold selector in accordance with the present invention. The present embodiment 6 of the automatic input threshold selector is characterized by automatically carrying out sequential setting of the input threshold in response to the level change in the input signal. 
     In FIG. 13, the reference numeral  10  designates a shift register; and  11  designates a decoder. The voltage comparator  1   a , switch  5   a , switch  6  and voltage comparator  7  have the same structure as the voltage comparator  1 , switch  5 , switch  6  and voltage comparator  7  shown in FIG.  1 . The voltage comparator  1   b  and switch  5   b  have the same structure as the voltage comparator  1  and switch  5  shown in FIG.  4 . 
     In addition, the reference symbol VR 6   a  designates a first reference level; VR 6   b  designates a second reference level; VR 61   a , VR 62   a  and VR 63   a  each designate a rising decision level; VR 61   b , VR 62   b  and VR 63   b  each designate a falling decision level; VT 6  designates an input threshold; VT 61 , VT 62 , VT 63  and VT 64  each designate an input threshold candidate. Here, the rising decision levels have a relation VR 61   a &lt;VR 62   a &lt;VR 63   a , and the falling decision levels have a relation VR 61   b &gt;VR 62   b &gt;VR 63   b , where VR 61   a &gt;VR 61   b.    
     In the shift register  10 , the reference symbols G 7 , G 8 , G 9  and G 10  each designate a two-input AND gate; and FF 4 , FF 5  and FF 6  each designate a JK flip-flop. The shift register  10  loads the output signals of the voltage comparators  1   a  and  1   b , and the JK flip-flops FF 4 , FF 5  and FF 6  each receive a reset signal RST at their reset input terminal, and a clock signal CLK at their input terminal. The JK flip-flops FF 4 , FF 5  and FF 6  are connected at their output side to signal lines outputting signals Q 61  and Q 61 C, Q 62  and Q 62 C, and Q 63  and Q 63 C, respectively. 
     In the decoder  11 , reference symbols G 11  and G 12  each designate a two-input AND gate. The decoder  11  receives at its input side the output signals Q 61 , Q 61 C, Q 62 , Q 62 C, Q 63  and Q 63 C of the shift register  11 , and is connected at its output side to signal lines outputting signals S 61 , S 62 , S 62 ′, S 63 , S 63 ′ and S 64 . 
     The switch  5   a  selects one of the rising decision levels VR 61   a , VR 62   a  and VR 63   a  as the reference level VR 6   a  under the control of the output signals S 61 , S 62  and S 63 ′ of the decoder  11 . The switch  5   a  selects, as the reference level VR 6   a , VR 61   a  when S 61  is “H”, VR 62   a  when S 62  is “H”, and VR 63   a  when S 63 ′ is “H”. 
     The switch  5   b  selects one of the falling decision levels VR 61   b , VR 62   b  and VR 63   b  as the reference level VR 6   b  under the control of the output signals S 62 ′, S 63  and S 64  of the decoder  11 . The switch  5   b  selects, as the reference level VR 6   b , VR 63   b  when S 62 ′ is “H”, VR 62   b  when S 63  is “H”, and VR 61   b  when S 64  is “H”. 
     The switch  6  selects one of the input thresholds VT 61 , VT 62 , VT 63  and VT 64  as the input threshold VT 6  under the control of the output signals S 61 , S 62 , S 63  and S 64  of the decoder  11 . Here, the switch  6  selects, as the input threshold VT 6 , VT 61  when S 61  is “H”, VT 62  when S 62  is “H”, VT 63  when S 63  is “H” and VT 64  when S 64  is “H”. 
     Next, the operation of the present embodiment 6 of the automatic input threshold selector will be described. FIG. 14 is a diagram illustrating an example of waveforms of the input threshold VT 6  and output signal OUT with respect to the waveforms of the input signal IN of the present embodiment 6. Here, the temporal variations in the level of the input signal IN is depicted as VI(T). As illustrated in FIG. 14, when the input signal level VI (T) varies from the low to high level, the input threshold VT 6  varies as VT 61 →VT 62 →VT 63 →VT 64  every time VI (T) exceeds the rising decision levels VR 61   a , VR 62   a  and VR 63   a . In contrast with this, when the signal level VI (T) varies from the high to low level, the input threshold VT 6  varies as VT 64 →VT 63 →VT 62 →VT 61  every time VI (T) falls below the falling decision levels VR 61   b , VR 62   b  and VR 63   b.    
     The initial state of the automatic input threshold selector as shown in FIG. 13 is established by the reset signal (RST=“H”), in which case, the outputs of the shift register  10  are placed at Q 61 =Q 62 =Q 63 =“L” and Q 61 C=Q 62 C=Q 63 C=“H”, and the outputs of the decoder  11  are placed at S 61 =S 62 ′=“H” and S 62 =S 63 =S 63 ′=S 64 =“L”. In this case, the switch  5   a  selects the rising decision level VR 61   a  as the reference level VR 6   a  (VR 6   a =VR 61   a ), the switch  5   b  selects the falling decision level VR 63   b  as the reference level VR 6   b  (VR 6   b =VR 63   b ), and the switch  6  selects the input threshold VT 61  as the input threshold VT 6  (VT 6 =VT 61 ). 
     If the level VI (T) is below the falling decision level VR 63   b , the reset state is released (RST=“L”). First, the operation when the level VI(T) increases toward the high level from the initial state. When the level VI(T) is lower than VR 63   b , the output of the voltage comparator  1   b  is at the “H” level, and the inverted outputs (QC) of the flip-flops FF 5  and FF 6  are at their initial value “H”. Thus, the inverting inputs (K) of the flip-flops FF 4 , FF 5  and FF 6  are all placed at the “H” level. At the same time, since the output of the voltage comparator la is at the level “L”, the non-inverting input (J) of the flip-flops FF 4 , FF 5  and FF 6  are all placed at the “L” level. When the rising edge of the clock signal CLK is supplied in this state, the non-inverted outputs (Q) of the flip-flops FF 4 , FF 5  and FF 6  are all placed at the “L” level with their inverted outputs (QC) placed at the “H” level, and the outputs of the shift register  10  maintain their initial state. In other words, unless the “H” level is input to any of the non-inverting inputs (J) of the flip-flops FF 4 , FF 5  and FF 6 , the outputs of the shift register  10  do not vary, and hence the description will be omitted of the operation when the level VI (T) exceeds the levels VR 63   b , VR 62   b  and VR 61   b.    
     When the level VI(T) exceeds the level VR 61   a , the output of the voltage comparator la is placed at the “H” level. In this case, since the non-inverted outputs (Q) of the flip-flops FF 4  and FF 5  are at the initial value “L”, only the non-inverting input (J) of the flip-flop FF 4  is placed at “H”. When the rising edge of the clock signal CLK is supplied in this state, the non-inverted output (Q) of the flip-flop FF 4  is changed to “H” and the inverted output (QC) is changed to “L”. In this case, the outputs of the shift register  10  are placed at Q 61 C=Q 62 =Q 63 =“L” and Q 61 =Q 62 C=Q 63 C=“H”, and the outputs of the decoder  11  are placed at S 62 =S 62 ′=“H” and S 61 =S 63 =S 63 ′=S 64 =“L”. The change in the outputs of the decoder  11  causes the switch  5   a  to select VR 62   a  as the reference level VR 6   a  (VR 6   a =VR 62   a ), the switch  5   b  to maintain selecting VR 63   b  as the reference level VR 6   b  (VR 6   b =VR 63   b ), and the switch  6  to select VT 62  as the input threshold VT 6  (VT 6 =VT 62 ). 
     When the level VI(T) exceeds the level VR 62   a , the output of the voltage comparator la is placed at “H”. When the rising edge of the clock signal CLK is supplied in this state, the non-inverted output (Q) of the flip-flop FF 5  is changed to “H”, and the inverted output (QC) is changed to “L”. In this case, the outputs of the shift register  10  are placed at Q 61 C=Q 62 C=Q 63 =“L” and Q 61 =Q 62 =Q 63 C=“H”, and the outputs of the decoder  11  are placed at S 63 =S 63 ′=“H” and S 61 =S 62 =S 62 ′=S 64 =“L”. The change in the outputs of the decoder  11  causes the switch  5   a  to select VR 63   a  as the reference level VR 6   a  (VR 6   a =VR 63   a ), the switch  5   b  to select VR 62   b  as the reference level VR 6   b  (VR 6   b =VR 62   b ), and the switch  6  to select VT 63  as the input threshold VT 6  (VT 6 =VT 63 ). 
     When the level VI(T) exceeds the level VR 63   a , the output of the voltage comparator  1   a  is placed at “H”. When the rising edge of the clock signal CLK is supplied in this state, the non-inverted output (Q) of the flip-flop FF 6  is changed to “H”, nand the inverted output (QC) is changed to “L”. In this case, the outputs of the shift register  10  are placed at Q 61 C=Q 62 C=Q 63 C=“L” and Q 61 =Q 62 =Q 63 =“H”, and the outputs of the decoder  11  are placed at S 63 ′=S 64 =“H” and S 61 =S 62 =S 62 ′=S 63 =“L”. The change in the outputs of the decoder  11  causes the switch  5   a  to maintain selecting VR 63   a  as the reference level VR 6   a  (VR 6   a =VR 63   a ), the switch  5   b  to select VR 61   b  as the reference level VR 6   b  (VR 6   b =VR 61   b ), and the switch  6  to select VT 64  as the input threshold VT 6  (VT 6 =VT 64 ). 
     Thus, when the input signal IN grows from the low to high level, the input threshold VT 6  varies as VT 61 →VT 62 →VT 63 →VT 64  every time the level of the input signal IN exceeds the rising decision levels VR 61   a , VR 62   a  and VR 63   a.    
     Next, the operation will be described when the level VI (T) decreases from a level higher than the rising decision level VR 63   a  toward the lower level. 
     When the level VI(T) is higher than VR 63   a , the output of the voltage comparator  1   a is at the “H” level, and the non-inverted outputs (Q) of the flip-flops FF 4  and FF 5  are at “H”. Thus, the non-inverting inputs (J) of the flip-flops FF 4 , FF 5  and FF 6  are all placed at “H”. At the same time, since the output of the voltage comparator  1   b  is at “L”, the inverting inputs (K) of all the flip-flops FF 4 , FF 5  and FF 6  are placed at “L”. When the rising edge of the clock signal CLK is supplied in this state, the non-inverted outputs (Q) of all the flip-flops FF 4 , FF 5  and FF 6  are placed at “H” with their inverted outputs (QC) placed at “L”, and the outputs of the shift register  10  maintains the previous state. In other words, unless the “H” level is input to any of the inverting inputs (K) of the flip-flops FF 4 , FF 5  and FF 6 , the outputs of the shift register  10  do not vary, and hence the description will be omitted of the operation when the level VI(T) falls below the levels VR 63   a , VR 62   a  and VR 61   a.    
     When the level VI (T) falls below the level VR 61   b , the output of the voltage comparator  1   b  is placed at the “H” level. In this case, since the inverted outputs (QC) of the flip-flops FF 5  and FF 6  are at “L”, only the inverting input (K) of the flip-flop FF 6  is placed at “H”. When the rising edge of the clock signal CLK is supplied in this state, the non-inverted output (Q) of the flip-flop FF 6  is changed to “L” and the inverted output (QC) is changed to “H”. In this case, the outputs of the shift register  10  are placed at Q 61 C=Q 62 C=Q 63 =“L” and Q 61 =Q 62 =Q 63 C=“H”, and the outputs of the decoder  11  are placed at S 63 =S 63 ′=“H” and S 61 =S 62 =S 62 ′=S 64 =“L”. The change in the outputs of the decoder  11  causes the switch  5   a  to maintain selecting VR 63   a  as the reference level VR 6   a  (VR 6   a =VR 63   a ), the switch  5   b  to select VR 62   b  as the reference level VR 6   b  (VR 6   b =VR 62   b ), and the switch  6  to select VT 63  as the input threshold VT 6  (VT 6 =VT 63 ). 
     When the level VI (T) falls below the level VR 62   b , the output of the voltage comparator  1   b  is placed at “H”. When the rising edge of the clock signal CLK is supplied in this state, the non-inverted output (Q) of the flip-flop FF 5  is changed to “L”, and the inverted output (QC) is changed to “H”. In this case, the outputs of the shift register  10  are placed at Q 61 C=Q 62 =Q 63 =“L” and Q 61 =Q 62 C=Q 63 C=“H”, and the outputs of the decoder  11  are placed at S 62 =S 62 ′=“H” and S 61 =S 63 =S 63 ′=S 64 =“L”. The change in the outputs of the decoder  11  causes the switch  5   a  to select VR 62   a  as the reference level VR 6   a  (VR 6   a =VR 62   a ), the switch  5   b  to select VR 63   b  as the reference level VR 6   b  (VR 6   b =VR 63   b ), and the switch  6  to select VT 62  as the input threshold VT 6  (VT 6 =VT 62 ). 
     When the level VI (T) falls below the level VR 63   b , the output of the voltage comparator  1   b  is placed at “H”. When the rising edge of the clock signal CLK is supplied in this state, the non-inverted output (Q) of the flip-flop FF 4  is changed to “L”, and the inverted output (QC) is changed to “H”. In this case, the outputs of the shift register  10  are placed at Q 61 =Q 62 =Q 63 =“L” and Q 61 C=Q 62 C=Q 63 C=“H”, and the outputs of the decoder  11  are placed at S 61 =S 62 ′=“H” and S 62 =S 63 =S 63 ′=S 64 =“L”. The change in the outputs of the decoder  11  causes the switch  5   a  to maintain selecting VR 61   a  as the reference level VR 6   a  (VR 6   a =VR 61   a ), the switch  5   b  to select VR 63   b  as the reference level VR 6   b  (VR 6   b =VR 63   b ), and the switch  6  to select VT 61  as the input threshold VT 6  (VT 6 =VT 61 ). 
     Thus, when the input signal IN decreases from the high to low level, the input threshold VT 6  varies such as VT 64 ÷VT 63 →VT 62 →VT 61  every time the level of the input signal IN falls below the falling decision level VR 61   b , VR 62   b  and VR 63   b.    
     According to the present embodiment 6, the voltage comparator  1   a , shift register  10 , decoder  11  and reference level selecting switch  5   a  constitute a rising decision level identifying means; the voltage comparator  1   b , shift register  10 , decoder  11  and reference level selecting switch  5   b  constitute a falling decision level identifying means; and the decoder  11  and input threshold selecting switch  6  constitute an input threshold setting means for setting the input threshold VT 6  in response to the rising decision level identified by the rising decision level identifying means when the input signal IN is rising, and in response to the falling decision level identified by the falling decision level identifying means when the input signal is falling. This offers an advantage of being able to implement a circuit that can successively set the input threshold automatically in accordance with the level changes in the rising edge and falling edge of the input signal. 
     In addition, the automatic input threshold selector can be constructed rather easily in the form of a combination of the voltage comparators, logical gates and the like. This offers an advantage of being able to implement a small size, low power consumption circuit. 
     Incidentally, although the present embodiment 6 of the automatic input threshold selector as shown in FIG. 13 has three rising decision levels, three falling decision levels and four input threshold candidates, it is obvious that their numbers are not limited to these numbers, and can be determined at any numbers according to the performance required of the automatic input threshold selector. 
     Embodiment 7 
     FIG. 15 is a circuit diagram showing an embodiment 7 of the automatic input threshold selector in accordance with the present invention. The present embodiment 7 of the automatic input threshold selector is characterized in that its initialization is controllable by software. In FIG. 15, the same reference numerals designate the same or like portions to those of FIG. 1, and the description thereof is omitted here. 
     In FIG. 15, the reference numeral  12  designates a two-input OR gate. The reference symbol SRR designates a shift register initializing signal controlled by the central processing unit (CPU) of a one-chip microcomputer, for example. The reference symbol RST designates a reset signal controlled by hardware. The OR gate  12  receives the shift register initializing signal SRR and reset signal RST, and outputs an “H” level signal when at least one of the two inputs takes the “H” level. The output signal line of the OR gate  12  is connected to the reset input terminal of the shift register  3 . 
     Next, the operation of the present embodiment will be described. 
     Even in the state in which the hardware reset is released (RST=“L”), it is possible for the CPU to issue the instruction by software for placing the shift register initializing signal SRR at the “H” level (SRR=“H”) to supply the reset input terminal of the shift register  3  with the “H” level signal. This causes the shift register  3  to be initialized, thereby returning the decoder  4 , switch  5  and switch  6  to the initial state. 
     According to the present embodiment 7, an input threshold initializing means for initializing by software the once established input threshold is configured by connecting the output line of the OR gate  12  that receives the shift register initializing signal SRR to the reset input terminal of the shift register  3 . This offers an advantage of being able to implement the automatic input threshold selector capable of initializing the circuit by software. 
     Although the present embodiment 7 of the automatic input threshold selector as shown in FIG. 15 is constructed by modifying the foregoing embodiment 1, the automatic input threshold selector is not limited to such a circuit configuration. For example, other circuits can be configured in which the shift register initializing signal generated by means of software is directly supplied to the reset input terminal of the shift register  3 . In addition, the present embodiment 7 of the automatic input threshold selector can be embedded into a one-chip microcomputer. 
     Embodiment 8 
     FIG. 16 is a circuit diagram showing an embodiment 8 of the automatic input threshold selector in accordance with the present invention. The present embodiment 8 of the automatic input threshold selector is characterized in that it can control enable/disable of the level decision of the input signal by software. In FIG. 16, the same reference numerals designate the same or like portions to those of FIG. 1, and the description thereof is omitted here. 
     In FIG. 16, the reference numeral  13  designate a voltage comparator with an enable input, which replaces the voltage comparator  1  of the foregoing embodiment 1 of the automatic input threshold selector. The voltage comparator  13  with an enable input carries out the normal operation when the enable input is at the “H” level, whereas it locks its output at the “L” level as long as the enable input is placed at the “L” level. The reference symbol ECMP designates an enable signal supplied to the enable input terminal of the voltage comparator  13 , which is controlled by a CPU. 
     Next, the operation of the present embodiment 8 will be described. 
     While the enable signal ECMP is at the “H” level, the voltage comparator  13  carries out the normal operation, causing the present embodiment 8 of the automatic input threshold selector to perform the same operation as the embodiment 1. In contrast, while the enable signal ECMP is placed at the “L” level, the output of the voltage comparator  13  is locked at the “L” level. This prevents the clock signal CLK from being supplied to the shift register  3 , thereby keeping the state of the shift register  3  unchanged, and maintaining the state of the decoder  4 , switch  5  and switch  6  and the input threshold VT 1 . 
     According to the embodiment 8, the voltage comparator  13  with the enable input for locking its output constitutes an input threshold holding means for holding the present input threshold VT 1  by halting the level decision of the input signal by software. This offers an advantage of being able to implement the automatic input threshold selector capable of holding the present input threshold. In addition, it has an advantage of being able to reduce the power consumption by disabling the level decision operation after the input threshold has been established. 
     Although the present embodiment 8 of the automatic input threshold selector as shown in FIG. 16 is implemented by modifying the foregoing embodiment 1, the configuration of the automatic input threshold selector is not limited to such a circuit configuration. Other circuit configurations can be implemented which are characterized by comprising the voltage comparator  13  with the enable signal input terminal for locking the output of the voltage comparator  13  at the “L” level. In addition, the present embodiment 8 of the automatic input threshold selector can be installed into a one-chip microcomputer. 
     Embodiment 9 
     FIG. 17 is a circuit diagram showing an embodiment 9 of the automatic input threshold selector in accordance with the present invention. The present embodiment 9 is characterized in that it can check the input threshold by software. In FIG. 17, the same reference numerals designate the same or like portions to those of FIG. 1, and the description thereof is omitted here. 
     In FIG. 17, the reference numeral  14  designate a register for storing the outputs S 1 , S 2 , S 3  and S 4  of the decoder  4 . 
     Next, the operation of the present embodiment 9 will be described. 
     The voltage comparator  1 , AND gate  2 , shift register  3 , decoder  4 , switch  5 , switch  6  and voltage comparator  7  as shown in FIG. 17 carry out the same operation as those of the embodiment 1 of the automatic input threshold selector as shown in FIG.  1 . Accordingly, the input threshold VT 1  is determined by the outputs S 1 , S 2 , S 3  and S 4  of the decoder  4 , which are stored in the register  14 . Thus, reading the values stored in the register  14  enables a CPU to check the currently selected input threshold VT 1  indirectly. 
     According to the present embodiment 9, the register  14  for storing the outputs of the decoder  4  constitutes an input threshold check means for checking the current input threshold VT 1  by software. This offers an advantage of being able to implement the automatic input threshold selector capable of checking the input threshold by software. 
     Although the present embodiment 9 of the automatic input threshold selector as shown in FIG. 17 is implemented by modifying the foregoing embodiment 1, the configuration of the automatic input threshold selector is not limited to such a circuit configuration. Other circuit configurations can be implemented which are characterized by comprising the register for storing the outputs of the decoder  4 . In addition, the present embodiment 9 of the automatic input threshold selector can be installed onto a one-chip microcomputer. 
     Embodiment 10 
     FIG. 18 is a block diagram showing an embodiment 10 of the automatic input threshold selector in accordance with the present invention. The present embodiment 10 is characterized by comprising an additional function of setting the input threshold by means of software. In FIG. 18, the same reference numerals designate the same or like portions to those of FIG. 1, and the description thereof it omitted here. In FIG. 18, the reference numeral  15  designates a register, and  16  designates a selector. The reference symbol SEL designates a select signal, which is controlled by a CPU. 
     Next, the operation of the present embodiment 10 will be described. 
     Because the voltage comparator  1 , AND gate  2 , shift register  3 , decoder  4  and switch  5  as shown in FIG. 18 carry out the same operation as those of the embodiment 1 as shown FIG. 1, the outputs S 1 , S 2 , S 3  and S 4  of the decoder  4  are determined by the maximum value of the input signal IN. In addition, the CPU sets logical values R1, R2, R3 and R4 in the register  15 . 
     The selector  16  receives the set of the outputs S 1 , S 2 , S 3  and S 4  of the decoder  4  and the set of the logical values R1, R2, R3 and R4 of the register  15 , and selects one of them under the control of the select signal SEL. Let us assume that when the select signal SEL is at the “H” level, the selector  16  outputs the set of the values S 1 , S 2 , S 3  and S 4 , whereas when the select signal SEL is at the “L” level, the selector  16  outputs the set of the values R1, R2, R3 and R4. The switch  6  selects one of the input threshold candidates VT 11 , VT 12 , VT 13  and VT 14  as the input threshold VT 1  under the control of the output of the selector  16 . The voltage comparator  7  carries out the same operation as the voltage comparator  7  of the embodiment 1. Specifically, setting the value of the register  15  at a desired value by means of software, and placing the select signal SEL at “L” makes it possible to set the input threshold at a desired level. 
     According to the present embodiment 10, the register  15  and selector  16  constitute an input threshold setting means for setting the input threshold at a desired value by means of software. This offers an advantage of being able to implement the automatic input threshold selector capable of setting the input threshold at a desired value by means of software. 
     Although the present embodiment 10 of the automatic input threshold selector as shown in FIG. 18 is implemented by modifying the foregoing embodiment 1, the configuration of the automatic input threshold selector is not limited to such a circuit configuration. Other circuit configurations can be implemented which are characterized by comprising the selector  16  for receiving the outputs of the decoder  4  and register  15 , and for selectively outputting one of them by means of software. In addition, the embodiment 10 of the automatic input threshold selector can be installed onto a one-chip microcomputer. 
     As described above, the automatic input threshold selector of the embodiments 1-10, which is configured rather easily by combining the voltage comparator, logic gates and the like, can be implemented as a small scale, low power consumption circuit. In addition, it is suitably installed onto a one-chip microcomputer because of the small scale circuit configuration. This makes it possible to facilitate various controls in accordance with its applications.