Abstract:
A semiconductor structure and methods for forming the same. The structure includes (a) a substrate; (b) a first device and a second device each being on the substrate; (c) a device cap dielectric layer on the first and second devices and the substrate, wherein the device cap dielectric layer comprises a device cap dielectric material; (d) a first dielectric layer on top of the device cap dielectric layer, wherein the first dielectric layer comprises a first dielectric material; (e) a second dielectric layer on top of the first dielectric layer; and (f) a first electrically conductive line and a second electrically conductive line each residing in the first and second dielectric layers. The first dielectric layer physically separates the first and second electrically conductive lines from the device cap dielectric layer. A dielectric constant of the first dielectric material is less than that of the device cap dielectric material.

Description:
FIELD OF THE INVENTION 
   The present invention relates to dielectric layers separating metal lines, and more specifically, to dielectric layers separating M1 lines (i.e., metal lines in the first metal level). 
   BACKGROUND OF THE INVENTION 
   In a conventional semiconductor chip, the M1 lines are very closely situated. As a result, line-to-line coupling capacitance between the M1 lines is very high. Therefore, there is a need for a structure (and a method for forming the same), in which the line-to-line coupling capacitance between the M1 lines is reduced compared to the prior art. 
   SUMMARY OF THE INVENTION 
   The present invention provides a semiconductor structure, comprising (a) a substrate; (b) a first device and a second device each being on the substrate; (c) a device cap dielectric layer on top of the first and second devices and on top of the substrate, wherein the device cap dielectric layer comprises a device cap dielectric material; (d) a first dielectric layer on top of the device cap dielectric layer, wherein the first dielectric layer comprises a first dielectric material; (e) a second dielectric layer on top of the first dielectric layer, wherein the second dielectric layer comprises a second dielectric material; and (f) a first electrically conductive line and a second electrically conductive line each residing in the first and second dielectric layers, wherein the first dielectric layer physically separates the first and second electrically conductive lines from the device cap dielectric layer, and wherein a dielectric constant of the first dielectric material is less than a dielectric constant of the device cap dielectric material. 
   The present invention provides a semiconductor structure fabrication method, comprising providing a semiconductor structure which includes (a) a substrate, (b) a first device and a second device each being on the substrate, (c) a device cap dielectric layer on top of the first and second devices and on top of the substrate, wherein the device cap dielectric layer comprises a device cap dielectric material, (d) a first dielectric layer on top of the device cap dielectric layer, wherein the first dielectric layer comprises a first dielectric material, and (e) a second dielectric layer on top of the first dielectric layer, wherein the second dielectric layer comprises a second dielectric material; and forming a first electrically conductive line and a second electrically conductive line each residing in the first and second dielectric layers, wherein the first dielectric layer physically separates the first and second electrically conductive lines from the device cap dielectric layer, and wherein a dielectric constant of the first dielectric material is less than a dielectric constant of the device cap dielectric material. 
   The present invention provides a structure (and a method for forming the same), in which the line-to-line coupling capacitance between the M1 lines is reduced compared to the prior art. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIGS. 1A-1I  illustrate (cross-section views) a fabrication method for forming a first semiconductor structure, in accordance with embodiments of the present invention. 
       FIG. 2  shows a cross-section view of a second semiconductor structure, in accordance with embodiments of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIGS. 1A-1I  illustrate (cross-section views) a fabrication method for forming a semiconductor structure  100 , in accordance with embodiments of the present invention. More specifically, with reference to  FIG. 1A , in one embodiment, the fabrication of the semiconductor structure  100  starts out with a semiconductor substrate  110 . Illustratively, the semiconductor substrate  110  comprises a semiconductor material such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), and those materials consisting essentially of one or more compound semiconductors such as gallium arsenic (GaAs), gallium nitride (GaN), and indium phosphoride (InP), etc. 
   Next, in one embodiment, transistors  111   a  and  111   b  are formed on the semiconductor substrate  110  by using a conventional method. For simplicity, only gate electrode regions  112   a  and  112   b  of the transistors  111   a  and  111   b , respectively, are shown in  FIG. 1A . In one embodiment, the gate electrode regions  112   a  and  112   b  comprise an electrically conductive material such as polysilicon. 
   Next, with reference to  FIG. 1B , in one embodiment, a device cap dielectric layer  120  is formed on top of the entire structure  100  of  FIG. 1A . In one embodiment, the device cap dielectric layer  120  can be formed by CVD (Chemical Vapor Deposition) of a dielectric material on top of the entire structure  100  of  FIG. 1A , and then a top surface  120 ′ of the device cap dielectric layer  120  can be planarized by, illustratively, a CMP (Chemical Mechanical Polishing) step. In one embodiment, the dielectric material used to form the device cap dielectric layer  120  can be BPSG (Boro-Phospho-Silicate Glass). 
   Next, with reference to  FIG. 1C , in one embodiment, a first low-k dielectric layer  130  is formed on top of the device cap dielectric layer  120 , wherein k is dielectric constant and “low-k” means k is less than 4.0. In one embodiment, the first low-k dielectric layer  130  can be formed by CVD of a first low-k dielectric material on top of the device cap dielectric layer  120 . In one embodiment, the first low-k dielectric material used to form the first low-k dielectric layer  130  can be FSG (Fluorine-doped Silicate Glass), whose k is 3.6; Bulk SiCOH (carbon-doped silicon oxides), whose k is 3.0; and/or Porous SiCOH, whose k is 2.3; etc. In one embodiment, the dielectric constant of the first low-k dielectric material which is used to form the first low-k dielectric layer  130  is lower than the dielectric constant of the dielectric material used to form the device cap dielectric layer  120 . 
   Next, with reference to  FIG. 1D , in one embodiment, holes  131   a  and  131   b  are formed in the first low-k dielectric layer  130  and the device cap dielectric layer  120 . In one embodiment, the holes  131   a  and  131   b  are formed using a conventional lithography and etching process. In one embodiment, the etching process to form the holes  131   a  and  131   b  essentially stops at the gate electrode regions  112   a  and  112   b  and exposes top surfaces  112   a ′ and  112   b ′ of the gate electrode regions  112   a  and  112   b , respectively, to the surrounding ambient through the holes  131   a  and  131   b , respectively. 
   Next, in one embodiment, the holes  131   a  and  131   b  are filled with a first electrically conductive material so as to form contact regions  132   a  and  132   b , respectively, resulting in the structure  100  of  FIG. 1E . In one embodiment, with reference to  FIGS. 1D and 1E , the contact regions  132   a  and  132   b  are formed by depositing the first electrically conductive material on top of the entire structure  100  of  FIG. 1D  (including in the holes  131   a  and  131   b ), and then polishing by a CMP step to remove excessive material outside the holes  131   a  and  131   b . As a result, the contact regions  132   a  and  132   b  are electrically coupled to the gate electrode regions  112   a  and  112   b , respectively. In one embodiment, the first electrically conductive material used to form the contact regions  132   a  and  132   b  can be tungsten. 
   Next, with reference to  FIG. 1F , in one embodiment, a second low-k dielectric layer  140  is formed on top of the entire structure  100  of  FIG. 1E , wherein k is less than 4.0. In one embodiment, the second low-k dielectric layer  140  can be formed by CVD of a second low-k dielectric material on top of the entire structure  100  of  FIG. 1E . In one embodiment, the second low-k dielectric material used to form the second low-k dielectric layer  140  can be FSG, whose k is 3.6; Bulk SiCOH, whose k is 3.0; and/or Porous SiCOH, whose k is 2.3; etc. In one embodiment, the dielectric constant of the second low-k dielectric material and the dielectric constant of the first low-k dielectric material can be the same. In an alternative embodiment, the dielectric constant of the second low-k dielectric material can be greater or lower than the dielectric constant of the first low-k dielectric material, which is used to form the first low-k dielectric layer  130 . 
   Next, with reference to  FIG. 1G , in one embodiment, trenches  141   a  and  141   b  are formed in the first low-k dielectric layer  130  and the second low-k dielectric layer  140 . In one embodiment, the trenches  141   a  and  141   b  are formed using a conventional lithography and etching process. In one embodiment, the etching process to form the trenches  141   a  and  141   b  (i) is essentially selective to the contact regions  132   a  and  132   b , and (ii) exposes portions of the contact regions  132   a  and  132   b  to the surrounding ambient through the trenches  141   a  and  141   b , respectively. In one embodiment, the etching process to form the trenches  141   a  and  141   b  etches through the second low-k dielectric layer  140  and stops at anywhere in the first low-k dielectric layer  130  before the device cap dielectric layer  120  is exposed to the surrounding ambient through the trenches  141   a  and  141   b.    
   Next, in one embodiment, the trenches  141   a  and  141   b  are filled with a second electrically conductive material so as to form metal lines  142   a  and  142   b , respectively, resulting in the structure  100  of  FIG. 1H . In one embodiment, with reference to  FIGS. 1G and 1H , the metal lines  142   a  and  142   b  are formed by depositing the second electrically conductive material on top of the entire structure  100  of  FIG. 1G  (including in the trenches  141   a  and  141   b ) and then polishing by a CMP step to remove excessive material outside the trenches  141   a  and  141   b . As a result, the metal lines  142   a  and  142   b  are electrically coupled to the contact regions  132   a  and  132   b , respectively. In one embodiment, the second electrically conductive material used to form the metal lines  142   a  and  142   b  comprises copper. 
   Next, with reference to  FIG. 1I , in one embodiment, a first cap layer  150  is formed on top of the entire structure  100  of  FIG. 1I . In one embodiment, the first cap layer  150  can be formed by CVD of a dielectric material on top of the entire structure  100  of  FIG. 1H . In one embodiment, the first cap layer  150  comprises silicon carbide (SiC), silicon nitride (SiN), and/or silicon carbon nitride (SiCN), etc. 
   Next, in one embodiment, additional conventional fabrication steps are performed on the structure  100  of  FIG. 1I  so as to form a final product (not shown). 
   In the embodiments described above, for simplicity, with reference to  FIGS. 1A-1I , the structure  100  comprises only two metal lines  142   a  and  142   b . In general, the structure  100  can comprise multiple metal lines (similar to the metal lines  142   a  and  142   b  as described in  FIGS. 1A-1I ) in the first low-k dielectric layer  130  and the second low-k dielectric layer  140 . 
   With reference to  FIG. 1I , it should be noted that the higher the density of the multiple metal lines in the first low-k dielectric layer  130  and the second low-k dielectric layer  140 , the higher the line-to-line coupling capacitance between the multiple metal lines resulting in lower semiconductor chip speed. It should also be noted that without the presence of the first low-k dielectric layer  130 , the two metal lines  142   a  and  142   b  would be in direct physical contact with the device cap dielectric layer  120 . As a result, the line-to-line coupling capacitance between the two metal lines  142   a  and  142   b  through the device cap dielectric layer  120  would be high (because BPSG is a high-k dielectric material). With the presence of the first low-k dielectric layer  130 , the two metal lines  142   a  and  142   b  are physically separated from the device cap dielectric layer  120  by the first low-k dielectric layer  130 . As a result, the line-to-line coupling capacitance between the two metal lines  142   a  and  142   b  through the device cap dielectric layer  120  is reduced. It should be noted that the line-to-line coupling capacitance between the two metal lines  142   a  and  142   b  through the first low-k dielectric layer  130  is small because the first low-k dielectric material used to form the first low-k dielectric layer  130  has a low dielectric constant. 
     FIG. 2  shows a cross-section view of a second semiconductor structure  200 , in accordance with embodiments of the present invention. In one embodiment, the structure  200  of  FIG. 2  is similar to the structure  100  of  FIG. 1I , except that besides a first cap layer  250 , there is a second cap layer  235  which is sandwiched between a first low-k layer  230  and a second low-k layer  240 . It should be noted that similar regions and layers of the structure  200  of  FIG. 2  and the structure  100  of  FIG. 1I  have the same reference numerals, except for the first digit which is the same as the figure numbers. For instance, a BPSG layer  220  ( FIG. 2 ) and the device cap dielectric layer  120  ( FIG. 11 ) are similar. In one embodiment, the second cap layer  235  comprises silicon carbide (SiC), silicon nitride (SiN), and/or silicon carbon nitride (SiCN), etc. 
   It should be noted that with the presence of the first low-k dielectric layer  230  in  FIG. 2 , two metal lines  242   a  and  242   b  are physically separated from the BPSG layer  220  by the first low-k dielectric layer  230 . As a result, the line-to-line coupling capacitance between the two metal lines  242   a  and  242   b  through the BPSG layer  220  is reduced compared with the case, in which the first low-k dielectric layer  230  is omitted. It should be noted that the line-to-line coupling capacitance between the two metal lines  242   a  and  242   b  through the first low-k dielectric layer  230  is small because the first low-k dielectric material used to form the first low-k dielectric layer  230  has a low dielectric constant. 
   While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.