Abstract:
A differential amplifier has unequal resistance in its legs that compensates for an unequal current flow through the legs during a logic zero data input compared to logic one data input. The unequal resistance may be provided by adding a resistor in parallel to the leg that carries greater current during amplification, lowering the resistance in that leg and also the voltage that is output from that leg. Alternatively, a variable resistance may be provided to at least one of the legs to compensate for current inequalities between the legs. The variable resistance may be provided by a transistor that is controlled by a signal indicating process, voltage and/or temperature conditions of the amplifier and adjacent circuitry. Transistors may be employed in both legs as well as in a current source for the amplifier, providing balanced current regulation for the amplifier. Such current compensated differential amplifiers may be employed for various functions, for example as input receivers or delay elements in high frequency memory systems.

Description:
BACKGROUND 
     The present invention relates to differential amplifier circuitry, and in particular to differential amplifier circuitry for low voltage amplification. 
     Differential amplifiers are well-known electronic devices for amplifying a voltage difference between two input signals. The input signals are provided to a pair of transistor gates of such an amplifier, each of which regulates a larger voltage and current swing through a corresponding leg of the amplifier. The legs are independently connected to a voltage source at one end, each leg including a resistor located between the transistor and voltage source, and are together connected to a voltage or current source at an opposite end. An output signal is taken from each leg between its transistor and resistor. The transistor and resistor of each leg are designed to be matched with those of the other leg, so that any difference in voltage between the input signals generates an amplified difference in voltage between the output signals. An advantage of such a differential amplifier is that the matched pair cancels undesirable voltage swings common to input signals, which may for instance be caused by temperature variations or noise, whereas differences between the input signals are amplified. 
     FIG. 1 shows a prior art MOS differential amplifier  21  that may be used as a receiver for a memory unit. Similar input receivers are disclosed in U.S. Pat. No. 5,319,755 and in U.S. Pat. No. 5,977,798, which are incorporated by reference herein. First and second lines  20  and  22  having matched resistors and transistors are connected to a voltage source Vdd and current source  10 . A reference signal VREF, which has an essentially constant voltage, is input to one transistor and a data signal DATA that varies about VREF is input to the other transistor, a system sometimes termed a single-ended data receiver. Typically the input data signal swings a few volts above and below the input reference signal. When the input data signal voltage is higher than the input reference signal voltage, current flows through line  20  so that an amplified voltage OUT 0  is output on line  25 . When the input data signal voltage is lower than the reference signal voltage, current flows through line  22  so that an amplified voltage OUT_ 0  is output on line  28 . The output lines  25  and  28  may be fed to a latch stage where they are clocked and stored. 
     To operate at higher frequencies with less power consumption, it may be desirable for the input data signal to swing by a smaller amount and to maintain lower voltage at source Vdd. With a low voltage Vdd and low input data signal swings, however, several problems may occur. Variations in rise and fall times of the output data signal make centering of the clock signal on the output data signal challenging. Setup and hold times or their tolerances might be adjusted but this has other costs and becomes more difficult at higher frequencies. Output data signals may not be equally amplified for high and low input data swings, so that a full rail voltage is not achieved for both high and low output data swings, causing errors in reading the data at both rising and falling edges. 
     In addition, high frequency memory devices such as those described in the above-referenced patents may employ a clocking compensation scheme including a delay locked loop (DLL), for which an input receiver setup time is matched with a clock loop phase detector setup time. For differential clock and single-ended data signals of similar amplitude, however, the differential clock may have virtually double the gain as the input receiver, so that the phase detector setup time is less than that of the input receiver. 
     Conventional MOS current source I 0  is shown in more detail in FIG. 2, and corresponding voltage and current characteristics of that current source I 0  are illustrated in FIG.  3 . The differential pair lines  20  and  22  are represented as a single variable potential V 0 . Transistor  30  has its gate held at a fixed voltage, which puts the transistor in a saturated mode for a gate-source voltage exceeding the threshold voltage of that transistor. This condition is indicated in FIG. 3 for an output voltage and current above Vsat and Isat, respectively. For gate-source voltages below the threshold voltage the current is less, as indicated by Vlow and Ilow. With a low Vdd that may not be much greater than V 0 , the current source I 0  may operate in an unsaturated mode that amplifies a positive input data swing more than an equal magnitude negative input data swing. Other factors affecting whether current source I 0  operates in a saturated mode include the structure of transistor  30  and temperature of its operation, both of which may be impractical to change. 
     SUMMARY 
     In accordance with the present invention, a differential amplifier is provided having an unequal resistance in its legs that compensates for an unequal current flow through the legs during a logic zero data input compared to logic one data input. The unequal resistance may be provided by adding a resistor in parallel to the leg that carries greater current during amplification, lowering the resistance in that leg and also the voltage that is output from that leg. Alternatively, a variable resistance may be provided to at least one of the legs to compensate for current inequalities between the legs. The variable resistance may be provided by a transistor that is controlled by a signal indicating process, voltage and/or temperature conditions of the amplifier and adjacent circuitry. Transistors may be employed in both legs as well as in a current source for the amplifier, providing balanced current regulation for the amplifier. Such current compensated differential amplifiers may be employed for various functions, for example as input receivers or delay elements in high frequency memory systems. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a diagram of a differential amplifier that may be used as an input receiver. 
     FIG. 2 is a diagram of a current source used in the differential amplifier of FIG.  1 . 
     FIG. 3 is a plot of the voltage-current characteristics of the current source shown in FIG.  2 . 
     FIG. 4 is a diagram of an input receiver embodiment of a differential amplifier in accordance with the present invention. 
     FIG. 5 is a plot of input data signals and output data signals for the differential amplifier of FIG. 4, showing the effect of compensation for an imperfect current source. 
     FIG. 6 is a diagram of a differential amplifier having a variable current element disposed in several optional locations. 
     FIG. 7 is a diagram of a delay locked loop including a plurality of delay elements and control logic that generates signals that may be used to bias the variable resistance elements of FIG.  6 . 
     FIG. 8 is a diagram of a delay element of FIG. 7 having a variable delay regulated by the control logic of FIG.  7 . 
     FIG. 9 is a diagram of a differential amplifier having an adjustable resistance and gain. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 4 shows an embodiment of an input receiver  100  accordance with the present invention that receives a data signal DATA  101  and reference signal VREF  102 . The data signal and reference signal may pass through an optional conventional level shift  105  that shifts the voltage level of both signals  101  and  102  to levels appropriate for the input receiver. Data signal  101  is then provided to transistor  110  and reference signal  102  is provided to transistor  112 , the transistors matched as a differential pair. Also matched are a pair of resistors R 1  and R 1 ′ that separate transistors  110  and  112  from voltage source Vdd, so that a first electrical path through first transistor  110  and first resistor R 1  is equivalent to a second electrical path through second transistor  112  and second resistor R 2 . In one embodiment, Vdd may be in a range between about 1.0 V and 2.5 V, although lower or higher voltages may be employed. The sources of transistors  110  and  112  are interconnected and coupled to a current source I 1 . This configuration amplifies the voltage difference between the gates of transistors  110  and  112 . I 1  may be a conventional current source similar to I 0  or may include bias features that will be described below. At the high frequencies in which the receiver  100  may operate, typically several hundred megahertz to about one gigaheirz, current source I 1  also provides amplification for the current of data signal  101 , compared to reference signal  102  which may be essentially constant in voltage and therefore provide no current. Output line OUT is connected to first electrical path  115  and output line OUT_B is connected to second electrical path  118 , with OUT and OUT_B provided to a latch stage  130 , where the differential output signals are referenced to a clock signal CLK. A single output may alternatively be provided. 
     FIG. 5 shows data signal DATA  101  varying about reference signal VREF  102 . Both data signal DATA  101  and reference signal VREF  102  may depart from the form and voltage levels illustrated FIG.  5 . Data signal DATA  101  may have a total voltage swing S of less than 2 volts that is centered about an essentially constant reference signal VREF  102 . For example, Vdd may be 1.8 V, VREF  102  may be 1.4 V, and DATA  101  may have high (LOGIC 0) and low (LOGIC 1) voltages spread equally about VREF with a total swing S of 0.8 V. At low Vdd levels, current source I 1  may be saturated for positive relative data voltages but not saturated for negative relative data voltages, or may operate primarily in an unsaturated mode. Thus the voltage gain through the first electrical path  115  would be greater than that through the second electrical path  118 , as shown by output signal  120 . The imbalance in gain causes timing difficulties as well, as shown by the difference in time T 1  for positive output voltage versus time T 2  for negative output voltage. 
     To compensate for this greater current flowing through path  115  than path  118 , an additional resistor R 2  is provided in parallel with resistor R 1 , lowering the overall resistance R 1 ″ through path  115 . As is well known, R 1 ″=R 1 R 2 /(R 1 +R 2 ). The resistor R 2  is chosen so that a ratio of the resistance R 1 ″ of path  115  compared to the resistance R 1 ′ through path  118  is essentially equal to a ratio of the current through path  118  to the current though path  115  at common operating levels. Stated differently, R 1 ″I 115 =R 1 ′I 118 , where I 115  is the current through leg  115  during LOGIC 0 and I 118  is the current through leg  118  during LOGIC 1. Output signal  122  shows the result of this compensation of unbalanced currents with unequal resistances to produce a symmetric voltage output. Output signal  122  includes a slight optional increase in gain to compensate for reductions in voltage caused by either the unsaturated current source or lessened resistance, as described below. Instead of providing a second resistor in parallel to path  115 , a second resistor could be provided in series to path  118 , increasing the resistance in path  118  to compensate for lower relative current through that path. 
     FIG. 6 shows an embodiment of a differential amplifier  200  with an adjustable current flow through legs  202  and  205  and a current source I 1  that can be adjusted with transistor  208 . Much as described above, differential pair transistors  212  and  210  respectively receive a reference signal VREF  218  and a data signal DATA  215  that varies about the reference signal. Transistors  212  and  210  are source-coupled and connected to current source I 1  at one end of legs  202  and  205 , and a voltage source Vdd is independently connected  202  and  205  at an opposite end. Also connected to the sources of transistors  210  and  212  is NMOS transistor  208 , providing a variable conductance to ground that acts as a variable current source. Vdd may be about 2 V or less, and the data signal may swing about the reference voltage by about 1 V. Output line  204  is connected to path  202  and output line  206  is connected to path  205 . Grounded PMOS transistors  225  and  228  have channels that form part of electrical paths  202  and  205 , respectively. PMOS transistors  220  and  222  are supplied with a bias voltage that can be varied to adjust the current in paths  202  and  205 . In addition to or in place of transistors  225  and  228 , resistors may be disposed in paths  202  and  205  between transistors  210  and  212  and voltage source Vdd. 
     The conductance of transistors  208 ,  220  and  222  may be controlled to compensate for conditions that would otherwise vary the speed for which output signals are provided to the latch stage. For example, the level of voltage Vdd can vary the speed of amplifier  200 , with higher voltages corresponding to higher speeds and lower voltages corresponding to lower speeds. Conversely, higher temperatures generally slow the amplifier and lower temperatures raise its speeds. Processing conditions during formation of the amplifier, such as channel lengths and widths and doping concentrations also affect amplifier performance. Controlling current through transistors  208 ,  220  and  222  can also reduce power consumption by providing higher power only when it is needed for higher gain. 
     In the embodiment shown in FIG. 6, conventional digital analog converters DAC  230  and DAC  233  provide analog signals to respective transistors  208 ,  220  and  222  upon receiving a digital signal from bias control circuit  240  indicative of process, voltage and temperature (PVT) conditions of the circuit  200  and surrounding circuits. DAC  230  and DAC  233  may provide different analog signals upon receiving the same PVT state signal from bias control circuit  240 , so that the resistance of transistors  220 ,  222  and  225  can be independently controlled. An advantage of this mechanism for controlling bias signals is that a digital signal indicating PVT conditions can be easily sent uncorrupted to various locations throughout a chip to control various differential amplifiers. 
     As shown in FIG. 7, bias control circuit  240  may be part of a DLL circuit  300 , such as that disclosed in U.S. patent application Ser. No. 6,125,157, entitled “Delay Locked Loop Circuitry for Clock Delay Adjustment,” filed Feb. 6, 1997 and incorporated by reference herein. The DLL  300  includes at least one and preferably a number of adjustable delay elements  303  arranged in a series to provide a desired delay, for instance 180° or 360°, to a clock signal CLK. Delay elements  303  may each have dual inputs and outputs, which are shown in FIG. 7 as single inputs and outputs for clarity. A conventional phase detector  308  detects a phase difference between the clock signal and the delayed clock signal via lines  310  and  313 . 
     The output from the phase detector  308  is provided to bias control circuit  240 , which determines whether an increase or decrease in the delay provided by delay elements  303  is needed to achieve the desired overall delay. To do this, the bias control circuit  240  creates a digital state that is based on the phase detection signal and therefore reflective of PVT conditions, and provides that PVT state to digital analog converter DAC  315 . Bias control circuit  240  contains an optional filter  320  connected to a counter  322  that is incremented or decremented depending upon the output of the phase detector  308 . The filter  320 , which may be a conventional digital filter, reduces oscillations about the desired phase delay. DAC  315  inputs the digital state and outputs a bias voltage to the delay elements  303 , which each may adjust their delay based upon the bias voltage. DAC  230  and DAC  233  may use the same signal from bias control circuit  240  to bias transistors  208 ,  220  and  222  and thereby balance the gain of amplifier  200 . Besides a phase detection mechanism, other bias control circuits may alternatively be employed that utilize, for example, voltage or temperature conditions for controlling differential amplifier load balancing elements such as transistors  220 ,  222  and  225 . 
     FIG. 8 shows an embodiment of a differential amplifier  400  that may be employed, for instance, as delay element  303 . In this embodiment, complimentary input signals are provided to inputs IN  402  and IN_B  404  of differential pair  406  and  408 . Differential pair  406  and  408  are disposed on a first electrical path  410  and a second electrical path  412 , respectively. Output lines OUT  414  and OUT_B  416  are connected to paths  410  and  412 , providing complimentary output signals. P-type transistors  418  and  420  are disposed on paths  410  and  412 , their gates grounded to provide primarily conductive channels for the paths  410  and  412 . P-type transistors  422  and  424  are disposed in parallel with transistors  418  and  420 , respectively, transistors  422  and  424  each receiving a bias signal Pbias to control the loads in paths  410  and  412 . Transistor  430  acts as a current source  12  for the differential amplifier  400 , and is controlled by bias signal Ibias. Signals Pbias and Ibias may be generated by mechanisms that determine relevant operating conditions for the amplifier, such as voltage levels, temperature, and transistor characteristics. As described above, signals Pbias and Ibias may be generated by control logic interpreting a phase detector to produce a digital signal indicating PVT conditions, the digital signal then converted by DACs to the signals Pbias and Ibias. 
     In FIG. 9 an embodiment of a differential amplifier  500  is shown that may be used as an input receiver, similar to amplifier  100 . Much as above, a reference signal VREF  502  and a data signal DATA  505  are provided to input transistors  508  and  506 , the transistors matched as a differential pair. Also matched are a pair of P-type transistors  510  and  512  having gates set to a low voltage or grounded so that their channels are primarily conductive. Transistors  506  and  510  form part of a first electrical path  515  and transistors  508  and  512  form part of a second electrical path  518 . In parallel with transistor  510  is an optional P-type transistor  520 , and in parallel with transistor  512  is an optional P-type transistor  522 . Transistors  520  and  522  are matched and receive a bias voltage Pbias that lowers the resistance through respective electrical paths  515  and  518 . 
     An additional P-type transistor  525  is disposed in parallel with transistors  510  and  520 , transistor  525  also controlled by bias signal Pbias. Transistor  525  regulates the resistance of path  515  compared to path  518 . Output line OUT is connected to first electrical path  515  and output line OUT_B is connected to second electrical path  518 , the output lines reflecting voltage drops from voltage source Vdd in paths  515  and  518 . 
     The sources of transistors  506  and  508  are interconnected and coupled to current source I 3 , which receives a fixed bias Fbias, and to current source I 4 , which receives an adjustable bias lbias. Current source I 4  regulates the current flowing through amplifier  500 , affecting the gain of both outputs equally. Thus amplifier  500  can be adjusted to control both the gain of one leg relative to another and the overall gain. Similar current and resistance compensated comparitors may be used with other small voltage swing systems. 
     Although we have focused on teaching the preferred embodiments of a novel differential amplifier, other embodiments and modifications of this invention will be apparent to persons of ordinary skill in the art in view of these teachings. Therefore, this invention is limited only by the following claims, which include all such embodiments and modifications when viewed in conjunction with the above specification and accompanying drawings.