Abstract:
A voltage translator circuit and a method for operating the same. The voltage translator circuit includes (a) an input node, an output node, and a ground node; (b) a voltage divider circuit including a first and second resistors coupled in series between the input node and the ground node; (c) a start voltage circuit coupled to a first voltage and to the input node; (d) a transfer circuit coupled to the output node; and (e) a capacitive circuit having a first and second capacitive nodes. The first capacitive node is coupled to the voltage divider circuit. The second capacitive node is coupled (i) to the first voltage via the start voltage circuit, and (ii) to the output node via the transfer circuit. In response to the input node changing towards the first voltage, the start voltage circuit is capable of disconnecting the second capacitive node from the first voltage.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Technical Field  
         [0002]     The present invention relates to voltage translator circuits, and more particularly, to voltage translator circuits using capacitive techniques.  
         [0003]     2. Related Art  
         [0004]     In the operation of a typical voltage translator, there are a lot of current spikes. Therefore, there is a need for a voltage translator circuit (and a method for operating the same) that has less current spikes than in the prior art.  
       SUMMARY OF THE INVENTION  
       [0005]     The present invention provides a voltage translator circuit, comprising (a) an input node, an output node, and a ground node, wherein the ground node is electrically coupled to ground; (b) a voltage divider circuit including a first resistor and a second resistor electrically coupled in series between the input node and the ground node; (c) a start voltage circuit electrically coupled to a first voltage and to the input node; (d) a transfer circuit electrically coupled to the output node; and (e) a capacitive circuit having a first capacitive node and a second capacitive node, wherein the first capacitive node is electrically coupled to the voltage divider circuit, wherein the second capacitive node is electrically coupled to the first voltage via the start voltage circuit, wherein the second capacitive node is electrically coupled to the output node via the transfer circuit, and wherein in response to the input node changing in voltage level towards the first voltage, the start voltage circuit is capable of electrically disconnecting the second capacitive node from the first voltage.  
         [0006]     The present invention also provides a circuit operation method, comprising providing a voltage translator circuit which includes: (a) an input node, an output node, and a ground node, wherein the ground node is electrically coupled to ground, (b) a voltage divider circuit including a first resistor and a second resistor electrically coupled in series between the input node and the ground node, (c) a start voltage circuit electrically coupled to a first voltage and to the input node, (d) a transfer circuit electrically coupled to the output node, and (e) a capacitive circuit having a first capacitive node and a second capacitive node, wherein the first capacitive node is electrically coupled to the voltage divider circuit, wherein the second capacitive node is electrically coupled to the first voltage via the start voltage circuit, and wherein the second capacitive node is electrically coupled to the output node via the transfer circuit; and in response to the input node changing in voltage level towards the first voltage, using the start voltage circuit to electrically disconnect the second capacitive node from the first voltage.  
         [0007]     The present invention also provides a voltage translator circuit, comprising (a) an input node, an output node, and a ground node, wherein the ground node is electrically coupled to ground; (b) a voltage divider circuit including a first resistor and a second resistor electrically coupled in series between the input node and the ground node; (c) a start voltage circuit electrically coupled to a first voltage and to the input node; (d) a transfer circuit electrically coupled to the output node; and (e) a capacitive circuit having a first capacitive node and a second capacitive node, wherein the first capacitive node is electrically coupled to the voltage divider circuit, wherein the second capacitive node is electrically coupled to the first voltage via the start voltage circuit, wherein the second capacitive node is electrically coupled to the output node via the transfer circuit, wherein in response to the input node changing in voltage level towards the first voltage, the start voltage circuit is capable of electrically disconnecting the second capacitive node from the first voltage, wherein in response to the input node changing in voltage level towards the first voltage, the voltage divider circuit and the capacitive circuit are capable of changing the second capacitive node from the first voltage to a second voltage, and wherein in response to the input node changing in voltage level towards the first voltage, the transfer circuit is capable of (i) electrically connecting the second capacitive node to the output node, and (ii) electrically disconnecting the output node from the ground node.  
         [0008]     The present invention provides a voltage translator circuit (and a method for operating the same) using a capacitive technique that has less current spike than the prior art. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]      FIG. 1  shows the diagram of a voltage translator circuit, in accordance with embodiments of the present invention.  
         [0010]      FIG. 2  shows a diagram which illustrates the waveforms of different signals at different nodes of the voltage translator circuit of  FIG. 1 , in accordance with embodiments of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0011]      FIG. 1  shows the diagram of a voltage translator circuit  100 , in accordance with embodiments of the present invention.  
         [0012]     More specifically, with reference to  FIG. 1 , in one embodiment, the voltage translator circuit  100  comprises an input terminal INP, an output terminal OUT, a lower voltage supply VOLT 1 , a higher voltage supply VOLT 2 , and a ground voltage supply VSS. In one embodiment, the lower voltage VOLT 1  is at 1 volt, the higher voltage VOLT 2  is at 1.6 volt, and the ground voltage VSS is typically at 0 volt. In one embodiment, the circuit  100  further comprises PFETs (P-channel Field Effect Transistor) T 1 , T 3 , T 4 , T 7 , T 8 , and T 11 ; NFETs (N-channel Field Effect Transistor) T 2 , T 6 , T 9 , T 12 , and T 28 ; resistors R 0  and R 1 ; and a capacitor C 0 . Illustratively, T 1 , T 2 , T 3 , T 4 , T 6 , T 7 , T 8 , T 9 , T 11 , T 12 , T 28 , R 0 , R 1 , C 0 , VOLT 1 , VOLT 2 , and VSS are electrically coupled together as shown in  FIG. 1 . In one embodiment, the resistances of the resistors R 0  and R 1  are selected such that: 
 
VOLT2−VOLT1=VOLT1× R 1/( R 1+ R 0)  (1) 
 
         [0013]     This equation (1) is called a design equation (1). To make description of the present invention simple, let y=VOLT 2 −VOLT 1 .  
         [0014]     In one embodiment, the operation of the voltage translator circuit  100  is as follows. Assume that, the input terminal INP is initially at 0 volt. Therefore, T 4  is on and T 6  is off. As a result, a node Inpb 1  is at VOLT 1 .  
         [0015]     As a result of node Inpb 1  being at VOLT 1 , T 9  is on. Therefore, a node Capbase is electrically coupled to ground via T 9 . As a result, the voltage of the node Capbase (V Capbase ) is at 0 volt. In addition, node Inpb 1  being at VOLT 1  turns off T 3  and turns on T 2 . As a result, a node INT 0  is electrically coupled to the input terminal INP via T 2 , resulting in node INT 0  being at 0 volt. Node INT 0  being at 0 volt turns on T 1 . Besides, the input terminal INP being at 0 volt turns on T 8 . Because T 1  and T 8  are on, node Q 3  is at VOLT 1 , resulting in the capacitor C 0  being charged with a voltage of VOLT 1  across the capacitor C 0 .  
         [0016]     Also, because node Inpb 1  is at VOLT 1 , T 7  is off. Hence, there is no electrical connection between node Q 3  and a node Q 2 . Besides, T 28  is on due to node Inpb 1  being at VOLT 1 . Therefore, node Q 2  is linked to ground via T 28 , resulting in node Q 2  being at 0 volt. Because node Q 2  is at 0 volt, T 11  is on and T 12  is off. Therefore, the output terminal OUT is at VOLT 2 .  
         [0017]     In short, the input terminal INP being at 0 volt causes output terminal OUT to be at VOLT 2 .  
         [0018]     Next, in one embodiment, assume the input terminal INP rises from 0 volt to VOLT 1 . As a result, T 4  is turned off and T 6  is turned on. In response, node Inpb 1  decreases from VOLT 1  to 0 volt. As a result, T 9  is turned off. Besides, R 0  and R 1  form a voltage divider circuit. Therefore, at node Capbase, V Capbase  goes from 0 volt to VOLT 1 ×R 1 /(R 1 +R 0 ). As a result of the design equation (1), in which VOLT 1 ×R 1 /(R 1 +R 0 )=(VOLT 2 −VOLT 1 ), when INP goes from 0 to VOLT 1 , V Capbase  goes from 0 volt to y=(VOLT 2 −VOLT 1 ).  
         [0019]     In one embodiment, the capacitance of the capacitor C 0  is such that the voltage across C 0  essentially does not change instantaneously when V Capbase  changes from 0 volt to y. As a result, when V Capbase  changes from 0 volt to y=(VOLT 2 −VOLT 1 ), node Q 3  jumps from the previous value of VOLT 1  to (VOLT 1 +y)=VOLT 1 +(VOLT 2 −VOLT 1 )=VOLT 2 .  
         [0020]     Input terminal INP increasing from 0 volt to VOLT 1  turns off T 8 . Besides, node Inpb 1  falling from VOLT 1  down to 0 volt turns off T 2  and turns on T 3 . As a result, node INT 0  has the same voltage level as node Q 3 . Therefore, node INT 0  is at VOLT 2 . As a result, T 1  is turned off.  
         [0021]     As a result of node Inpb 1  going from VOLT 1  down to 0 volt, T 28  is turned off and T 7  is turned on. Therefore, the voltage level of Q 2  is equal to the voltage level of Q 3  which is VOLT 2 . In response, T 11  is turned off and T 12  is turned on. As a result, the output terminal OUT is electrically coupled to ground via T 12 . Therefore, the output terminal OUT is at 0 volt.  
         [0022]     In short, the input terminal INP rising from 0 volt to VOLT 1  causes the output terminal OUT to change from VOLT 2  down to 0 volt.  
         [0023]     Next, in one embodiment, assume the input terminal INP decreases from VOLT 1  to 0 volt. As a result, T 4  is turned on and T 6  is turned off. In response, node Inpb 1  is electrically coupled to VOLT 1  via T 4 . As a result, node Inpb 1  changes from 0 volt to VOLT 1 . Therefore, T 9  is turned on.  
         [0024]     At node Capbase, V Capbase  goes from y=(VOLT 2 −VOLT 1 ) to 0 volt. Since the voltage across the capacitor C 0  cannot change instantaneously, node Q 3  drops from the previous value of VOLT 2  down to VOLT 2 −y=VOLT 2 −(VOLT 2 −VOLT 1 )=VOLT 1 .  
         [0025]     It should be noted that when node INP goes from 0 volt to VOLT 1 , T 1  and T 8  are turned on. This helps bring node Q 3  to the voltage level VOLT 1 . More specifically, because T 8  is electrically coupled to the input terminal INP which is at 0 volt, T 8  is turned on. Node Inpb 1  being at VOLT 1  turns off T 3  and turns on T 2 . Hence, node INT 0  is electrically coupled to the input terminal INP. As a result, node INT 0  goes to 0 volt. In response, T 1  is turned on. Because both T 1  and T 8  are turned on, node Q 3  takes the voltage level VOLT 1  as described above.  
         [0026]     On the other hand, node Inpb 1  changing from 0 volt to VOLT 1  turns off T 7 . Hence, node Q 3  becomes electrically disconnected from node Q 2 . Also, T 28  is turned on due to node Inpb 1  changing from 0 volt to VOLT 1 . As a result, node Q 2  is electrically coupled to ground via T 28  and node Q 2  goes to 0 volt. In response, T 11  is turned on and T 12  is turned off. As a result, the output terminal OUT is electrically coupled to VOLT 2  via T 11 . Therefore, the output terminal OUT has the voltage level VOLT 2 .  
         [0027]     In short, the input terminal INP decreasing from VOLT 1  to 0 volt causes the output terminal OUT to rise from 0 volt to VOLT 2 .  
         [0028]     As can be seen in  FIG. 1 , node VOLT 1  is connected to ground via the capacitor C 0  whereas node VOLT 2  is connected to ground via the CMOS inverter T 11 , T 12 . As a result, current spikes during the operation of the voltage translator circuit  100  are minimized.  
         [0029]     In one embodiment, the voltage translator circuit  100  is programmable for adaptability to different voltage domains by using a variable capacitor C 0  and variable resistors R 0  and R 1 . Illustratively, for given values of VOLT 1  and VOLT 2 , the resistors R 0  and R 1  can be varied to satisfy the design equation (1) so that the circuit  100  can be used to translate from one voltage domain (0 volt to VOLT 1 ) to the other voltage domain (0 volt to VOLT 2 ).  
         [0030]     In one embodiment, the variable resistors R 0  and R 1  have resistance control inputs so that the resistances of R 0  and R 1  can be varied by applying appropriate control signals to the resistance control inputs. In one embodiment, the variable capacitor C 0  has capacitance control inputs so that the capacitance of C 0  can be varied by applying appropriate control signals to the capacitance control inputs.  
         [0031]     The capacitance of C 0  determines how quickly node Q 3  follows node Capbase in voltage. The higher the capacitance of C 0  is, the more closely node Q 3  follows node Capbase. In one embodiment, the operating frequency of the voltage translator circuit  100  can be as high as 1000 MHz.  
         [0032]     In summary, when the input terminal INP is initially at 0 volt, a start voltage circuit (including T 1 , T 2 , T 3 , T 4 , T 6 , and T 8 ) and the voltage divider circuit (including R 0  and R 1 ) ensure that node Q 3  is at VOLT 1 . In response, the output terminal OUT is at VOLT 2 . When the input terminal INP rises from 0 volt to VOLT 1 , the start voltage circuit stops driving node Q 3  such that the voltage divider circuit (including R 0  and R 1 ) and the capacitor C 0  can drive Q 3  from VOLT 1  up to VOLT 2 . As a result, the output terminal OUT falls from VOLT 2  down to 0 volt. Next, when the input terminal INP falls from VOLT 1  down to 0 volt, the start voltage circuit and the voltage divider circuit ensure that node Q 3  goes back to VOLT 1  to be ready for the next cycle. As a result, the output terminal OUT rises from 0 up to VOLT 2 . It should be noted that node Q 2  can also be considered as an output node of the voltage translator circuit  100 . This is because when INP rises from 0 volt to VOLT 1 , node Q 2  changes from 0 volt to VOLT 2  and when INP falls from VOLT 1  down to 0 volt, node Q 2  changes from VOLT 2  to 0 volt. Besides, the CMOS inverter (including T 11  and T 12 ) can be considered as a buffer circuit that couples node Q 2  to the output terminal OUT.  
         [0033]      FIG. 2  shows a diagram  200  which illustrates the waveforms of different signals at different nodes of the voltage translator circuit  100  of  FIG. 1 , in accordance with embodiments of the present invention.  
         [0034]     More specifically, in one embodiment, the diagram  200  shows reduction in current spike of the present invention in comparison with prior art. In one embodiment, line  201  illustrates the incoming signal at node INP. Line  202  illustrates the current going from the voltage supply VOLT 1  to the ground voltage supply VSS in the prior art (i.e., when a conventional voltage translator is used instead of the circuit  100  of  FIG. 1 ). Line  203  illustrates the current going from the voltage supply VOLT 2  to the ground voltage supply VSS in the prior art. Line  204  illustrates the current going from the voltage supply VOLT 1  to the ground voltage supply VSS in the present invention. Line  205  illustrates the current going from the voltage supply VOLT 2  to the ground voltage supply VSS in the present invention.  
         [0035]     As can be seen in  FIG. 2 , the lines  202  and  204  illustrate the current spikes which go from the VOLT 1  to the ground in the prior art and in the present invention, respectively. Besides, the lines  203  and  205  illustrate the current spikes which go from the VOLT 2  to the ground in the prior art and the present invention, respectively. It is obvious that the current spike from VOLT 2  of the present invention is reduced in comparison with the prior art. The current spike from VOLT 2  of the present invention has a peak of 0.2 mA at 6.95 nsec and a peak of 0.5 mA at 7.55 nsec whereas the current spike from VOLT 2  of the prior art has a peak of 2.2 mA at 6.95 nsec and a peak of 1.95 mA at 7.55 nsec. So, the current spike of the present invention is one-eleventh of the prior art at 6.95 nsec, and one-fourth of the prior art at 7.55 nsec.  
         [0036]     In one embodiment, the voltage translator circuit  100  can operate in both a step-up mode and a step-down mode. In the step-up mode, the voltage translator  100  converts the incoming signal from a lower voltage domain (VOLT 1 ) to a higher voltage domain (VOLT 2 ), wherein VOLT 1 &lt;VOLT 2 . In the step-down mode, the voltage translator  100  converts the incoming signal from a higher voltage domain (0 volt to VOLT 1 ) to a lower voltage domain (0 to VOLT 2 ), wherein VOLT 1 &gt;VOLT 2 .  
         [0037]     In summary, the present invention uses a capacitive technique to eliminate fighting at nodes, hence, reducing current spikes on the voltage supplies during the incoming signal transitions.  
         [0038]     While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.