Abstract:
Methods of forming pre-encapsulated frames comprise flowing a dielectric encapsulation material around at least one conductive trace. A cavity configured to receive at least one semiconductor device at least partially in the cavity is formed in the encapsulation material. A first connection area of the at least one trace is exposed within the cavity. At least another connection area of the at least one trace is exposed laterally adjacent to the cavity. The dielectric encapsulation material is hardened to form a pre-encapsulated frame.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a divisional of U.S. patent application Ser. No. 12/128,575, filed May 28, 2008, the disclosure of which is hereby incorporated herein by this reference in its entirety. The subject matter of this application is related to U.S. patent application Ser. No. 11/874,531, filed Oct. 18, 2007, now U.S. Pat. No. 7,829,991, issued Nov. 9, 2010, which is a divisional of U.S. patent application Ser. No. 11/063,403, filed Feb. 22, 2005, now U.S. Pat. No. 7,285,442, issued Oct. 23, 2007, which is a continuation of U.S. patent application Ser. No. 10/706,210, filed Nov. 12, 2003, now U.S. Pat. No. 6,858,926, issued Feb. 22, 2005, which is a divisional of U.S. patent application Ser. No. 09/924,635, filed Aug. 8, 2001, now U.S. Pat. No. 6,650,007, issued Nov. 18, 2003, which is a continuation of U.S. patent application Ser. No. 09/344,279, filed Jun. 30, 1999, now U.S. Pat. No. 6,297,548, issued Oct. 2, 2001, which claims the benefit of U.S. Provisional Application No. 60/091,205 filed Jun. 30, 1998, the disclosure of each of which is incorporated herein in its entirety by reference. 
     
    
     FIELD 
       [0002]    This invention relates generally to connectors for high-density semiconductor device configurations using a pre-encapsulated cavity interposer. 
       BACKGROUND 
       [0003]    In response to the demand for semiconductor device packages having the ability to include the largest number of semiconductor devices in the smallest physical space, all components of such packages must occupy the least possible physical volume and use the most efficient manner to interconnect with each other and a power source. 
         [0004]    It is known to form packages for semiconductor devices that include semiconductor memory devices of different types as well as other semiconductor devices with the package being connected to a printed circuit board. As it has become desirable for the amount of physical space that the package occupies to decrease, even though the number of semiconductor devices in the package is increasing, and desirable to have improvements in attachment techniques used for attaching the semiconductor devices to each other in the package itself and the attachment of the package to a printed circuit board are necessary. 
         [0005]    While the use of lead frames and wire bonds to connect semiconductor devices is well known, such techniques can be further advanced. Similarly, while the use of lead frames and flip-chip type attachment techniques to connect semiconductor devices is well known, such techniques can be further advanced. Additionally, while the use of solder bumps to connect semiconductor packages in packages to printed circuit boards is well known, such can be further advanced. 
       BRIEF SUMMARY 
       [0006]    In some embodiments, methods of forming pre-encapsulated frames comprise flowing a dielectric encapsulation material around at least one conductive trace. A cavity configured to receive at least one semiconductor device at least partially in the cavity is formed in the encapsulation material. A first connection area of the at least one trace is exposed within the cavity. At least another connection area of the at least one trace is exposed laterally adjacent to the cavity. The dielectric encapsulation material is hardened to form a pre-encapsulated frame. 
         [0007]    In other embodiments, methods of forming semiconductor device packages comprise flowing a dielectric encapsulation material around at least one conductive trace. A cavity configured to receive at least one semiconductor device at least partially in the cavity is formed in the encapsulation material. A first connection area of the at least one trace is exposed within the cavity. At least another connection area of the at least one trace is exposed laterally adjacent to the cavity. The dielectric encapsulation material is hardened to form a pre-encapsulated frame. At least one semiconductor device is at least partially disposed in the cavity with an active surface of the at least one semiconductor device facing the first connection area of the at least one trace. The first connection area of the at least one trace is connected to the active surface of the at least one semiconductor device. 
         [0008]    In still other embodiments, methods of assembling pre=encapsulated assemblies comprise attaching an imaging semiconductor device to an a first encapsulated structure having a cavity therein, the cavity having a portion of the first encapsulated structure extending thereover, another portion extending therearound, and an aperture in the top thereof and a plurality of traces located in the first encapsulated structure. Each trace has a first portion extending in the portion of the first encapsulated structure extending over the cavity and a second portion extending in the another portion of the encapsulated member connected to the first portion with one end of the second portion being exposed for connection thereto. An adhesive contacting a portion of the first encapsulated structure and a portion of the imaging semiconductor device is dispensed. A transparent member is attached to the first encapsulated structure by contacting the adhesive. The cavity in the encapsulated member is sealed using a liquid material. Solder material is placed on the first encapsulated structure in a pattern. 
     
    
     
       DESCRIPTION OF THE DRAWINGS 
         [0009]      FIG. 1  is a cross-sectional view of a pre-encapsulated frame; 
           [0010]      FIG. 1A  is a view of a portion of a strip of pre-encapsulated frames; 
           [0011]      FIG. 1B  is a view of a portion of a panel of pre-encapsulated frames; 
           [0012]      FIG. 2  is a cross-sectional view of a pre-encapsulated frame having a semiconductor device installed therein; 
           [0013]      FIG. 2A  is a cross-sectional view of an alternative pre-encapsulated frame having a semiconductor device installed therein; 
           [0014]      FIG. 2B  is a cross-sectional view of an alternative pre-encapsulated frame having a semiconductor device installed therein; 
           [0015]      FIG. 2C  is a cross-sectional view of an alternative pre-encapsulated frame having a semiconductor device installed therein; 
           [0016]      FIG. 2D  is a cross-sectional view of an alternative pre-encapsulated frame having a semiconductor device installed therein; 
           [0017]      FIG. 2E  is a cross-sectional view of an alternative pre-encapsulated frame having a semiconductor device installed therein; 
           [0018]      FIG. 3  is a cross-sectional view of two stacked pre-encapsulated frames each having a semiconductor device installed therein and connected using bond wires; 
           [0019]      FIG. 4  is a cross-sectional view of a pre-encapsulated frame having a semiconductor device installed therein having two sides of bond pads on the active surface thereof; 
           [0020]      FIG. 5  is a cross-sectional view of a pre-encapsulated frame having a semiconductor device installed therein having one side of bond pads on the active surface thereof; 
           [0021]      FIG. 5A  is a cross-sectional view of a pre-encapsulated frame having a semiconductor device installed therein having 1.5 sides of bond pads on the active surface thereof; 
           [0022]      FIG. 5B  is a cross-sectional view of a pre-encapsulated frame having a semiconductor device installed therein having one side of bond pads on the active surface thereof along the long side of the semiconductor device; 
           [0023]      FIG. 5C  is a plan view of a pre-encapsulated frame for a semiconductor device having two sides of bond pads on the active surface thereof; 
           [0024]      FIG. 5D  is a plan view of a pre-encapsulated frame for a semiconductor device having one side of bond pads on the active surface thereof; 
           [0025]      FIG. 5E  is a plan view of a pre-encapsulated frame for a semiconductor device having 1.5 sides of bond pads on the active surface thereof; 
           [0026]      FIG. 5F  is a plan view of a pre-encapsulated frame for a semiconductor device having one side of bond pads on the active surface thereof along the long side of the semiconductor device; 
           [0027]      FIG. 6  is a cross-sectional view of two stacked pre-encapsulated frames having semiconductor devices installed therein being interconnected in a DDP arrangement; 
           [0028]      FIG. 7  is a cross-sectional view of four stacked pre-encapsulated frames having semiconductor devices installed therein being interconnected in a QDP arrangement; 
           [0029]      FIG. 8  is a cross-sectional view of a pre-encapsulated frame having two semiconductor devices installed therein in an offset arrangement; 
           [0030]      FIG. 8A  is a cross-sectional view of a pre-encapsulated frame having two semiconductor devices installed therein in a stacked arrangement; 
           [0031]      FIG. 9  is a cross-sectional view of two stacked interconnected pre-encapsulated frames, one frame having a DRAM semiconductor memory device installed therein and the other frame having a NAND semiconductor memory device installed therein; 
           [0032]      FIG. 10  is a cross-sectional view of three stacked interconnected pre-encapsulated frames, one frame having a controller semiconductor device installed therein and two frames having NAND semiconductor memory devices installed therein; 
           [0033]      FIG. 11  is a cross-sectional view of nine stacked interconnected pre-encapsulated frames, one frame having a controller semiconductor device installed therein and eight frames having NAND semiconductor memory devices installed therein; 
           [0034]      FIG. 12  is a cross-sectional view of two stacked interconnected pre-encapsulated frames, each frame having a semiconductor device having bond pads on the active surface thereof arranged essentially in the center of the active surface essentially in a row; 
           [0035]      FIG. 13  is a cross-sectional view of two stacked interconnected pre-encapsulated frames, each frame having a semiconductor device having bond pads on the active surface thereof arranged essentially in the center of the active surface essentially in two rows; 
           [0036]      FIG. 14  is a cross-sectional view of five stacked interconnected pre-encapsulated frames located on a substrate, three frames having a NAND semiconductor devices installed therein, one frame having a DRAM semiconductor device installed therein, and one frame having a controller semiconductor device installed therein; 
           [0037]      FIG. 15  is a cross-sectional view of a pre-encapsulated frame having an aperture therein; 
           [0038]      FIG. 15A  is a plan view of the pre-encapsulated frame of  FIG. 15  from the bottom thereof; 
           [0039]      FIG. 15B  is a cross-sectional view of the pre-encapsulated frame of  FIG. 15  having an imaging type semiconductor device installed therein and a lens installed therewith; 
           [0040]      FIG. 15C  is a cross-sectional view of a pre-encapsulated frame having an imaging type semiconductor device installed therein using bond wire type electrical connections and having a lens installed therewith; 
           [0041]      FIG. 15D  is a view of the process for installing an imaging type semiconductor device in the pre-encapsulated frame; 
           [0042]      FIG. 16  is a cross-sectional view of six stacked interconnected pre-encapsulated frames, one frame having an imaging semiconductor device installed therein and a lens installed therewith, three frames having NAND semiconductor devices installed therein, one frame having a DRAM semiconductor device installed therein, and one frame having a controller semiconductor device installed therein; 
           [0043]      FIG. 17  is a cross-sectional view of two stacked and interconnected pre-encapsulated frames, one frame having an imaging type semiconductor device installed therein and a lens installed therewith and one frame having a lens installed therewith; and 
           [0044]      FIG. 18  is a cross-sectional view of four pre-encapsulated frames, one frame having an imaging semiconductor device installed therein and a lens therewith and three frames having lens installed therewith. 
       
    
    
     DETAILED DESCRIPTION 
       [0045]    Referring to drawing  FIG. 1 , a pre-encapsulated cavity interposer  10 , hereinafter referred to as a pre-encapsulated frame  10 , is illustrated in cross section. The pre-encapsulated cavity frame  10  comprises a pre-encapsulated member  11 , the frame  10 , formed of encapsulating compound  20  having any desired configuration for a semiconductor device to be retained in the member  11  in a cavity  22  therein and having a plurality of traces  12  including a first portion  14 , typically extending horizontally, having any desired shape and configuration, such as rectangular, square, etc., and a second portion  16 , typically extending orthogonally from the first portion  14 , although they may extend at any desired angle, as a post like structure having any desired shape and configuration, such as round, rectangular, square, hexagonal, triangular, elliptical, u-shaped, c-shaped, curved in cross-sectional shape, etc. As many second portions  16  of a trace  12  may be attached in serial fashion to the first portion  14  of a trace  12 , which are illustrated herein. The traces  12  include connection areas  18  formed in the ends of the second portions  16 , which may include grooves therein or roughened surfaces thereon, as desired, for enhanced joint connections, although the connection areas  18  ends may be smooth, an encapsulating compound  20  covering portions of the traces  12 , and a cavity  22  formed by the traces  12  and encapsulation material  20  of the frame  11  for the installation of any desired number, shapes, and types of semiconductor devices therein. The cavity  22  surrounds and encloses any semiconductor device or semiconductor devices installed therein on the top and sides thereof. The cavity  22  having a desired size and a thickness essentially that approximate the semiconductor device to be installed therein, although the cavity  22  can be any desired size and thickness for use with different types of semiconductor devices to be installed therein. 
         [0046]    The traces  12  may be formed of any suitable metal material, such as copper, copper alloy, etc., of any desired thickness of metal material suitable for the application of the pre-encapsulated cavity interposer  10 . Any desired metal coating, such as a layer of gold, silver, nickel, palladium, alloys thereof, etc., and/or any desired coating of material may be used on the traces  12  at any desired location thereon for any purpose. The encapsulating material  20  may be of any suitable type for the application for the pre-encapsulated cavity interposer  10  and may contain any suitable amount of filler material and other additives therein, if desired for the formation of the pre-encapsulated frame  11 . The encapsulation material  20  surrounds each trace  12  insulating the trace  12  while providing a suitable connection area  15  on the first portion  14  for connection to a semiconductor device and connection areas  18  on the second portion. The connection area  15  may include any desired layers of metal thereon, such as gold, silver, nickel, palladium, alloys thereof; etc. A surface  24  formed opposite of the cavity  22  of the pre-encapsulated cavity interposer  10  is generally planar having areas free of encapsulation material for the connection areas  18  of the second portions  16  of the traces  12 . If desired, the surface  24  may include other areas free of encapsulation material  10  for connection areas for the first portion  14  of a trace  12  (not shown) so that both the first portion  14  and second portion  16  of a trace may include connection areas on the upper and lower surfaces thereof. Similarly, if desired, the surface  24  may have a cavity of any desired sized and shape, such as cavity  22 , formed therein (not shown). 
         [0047]    The pre-encapsulated cavity frame  10  may be formed in strip form of any desired length and configuration pattern or in panel form having any desired geometric shape and physical size. The pre-encapsulated cavity frame  10  is constructed using a base material (not shown), having the traces  12  patterned on the base material having any size, pitch, pattern, shape, thickness, length, etc., with the encapsulation material  20  providing support for the traces  12  being applied thereover. After the formation of the pre-encapsulated cavity interposer  10  on the base material, the base material is removed leaving the pre-encapsulation frame  10 . The pre-encapsulated cavity frame  10  may be formed for stacking of multiple pre-encapsulation frames having any desired number of semiconductor devices therein one on top the other being electrically interconnected by the connection areas  18  of the ends of the second portions  16  of the traces  12  contacting each other as desired. 
         [0048]    Referring to drawing  FIG. 1A , illustrated in a top view is a portion of a strip of pre-encapsulation frames  10 , which may be cut or severed into individual pre-encapsulation frames  10  at any desired time of use. 
         [0049]    Referring to drawing  FIG. 1B , illustrated in a top view is a portion of a panel of pre-encapsulation frames  10 , which may be cut or severed into individual pre-encapsulation frames  10  at any desired time of use. 
         [0050]    Referring to drawing  FIG. 2 , the pre-encapsulated cavity frame  10  is illustrated in cross section having a flip-chip type semiconductor device  30  attached to connection areas  15  of the first portions  14  of a leads  12  using solder balls  32 , or solder bumps, solder stud bumps, or gold stud bumps located between bond pads of the semiconductor device  30  and the connection areas  15 . The cavity  22  of the pre-encapsulated cavity frame  10  having the semiconductor device  30  located therein is filled with any suitable liquid encapsulant material, underfill material, etc., to retain and environmentally seal the semiconductor device  30  in the cavity  22  forming an essentially planar lower surface  36  opposite the surface  24  of the pre-encapsulated cavity interposer  10  at essentially the same level as that of the lower surface  18  of the second portion  16  of traces  12 . 
         [0051]    Referring to drawing  FIG. 2A , the pre-encapsulated cavity frame  10  is illustrated in cross section having a flip-chip type semiconductor device  30  attached to connection areas  15 , which extend below the lower surface  20 ′ of the encapsulant material  20  covering the lower surface  18  of the second portion  16  of the traces  12  having one or more grooves or recesses  15 ′ therein of the first portions  14  of a leads  12  using solder balls  32 , or solder bumps, solder stud bumps, or gold stud bumps located between bond pads of the semiconductor device  30  and the connection areas  15 . The one or more grooves or recesses  15 ′ in the connection areas facilitate the location of the semiconductor device  30  in the cavity  22  in the proper location with respect to connection areas  15  using conventional semiconductor device attachment equipment. The one or more grooves or recesses  15 ′ may be formed having any suitable geometric shape and desired depth in the connections areas  15  by any suitable method, such as etching, coining, laser forming, etc. The cavity  22  of the pre-encapsulated cavity frame  10  having the semiconductor device  30  located therein is filled with any suitable liquid encapsulant material, underfill material, etc., to retain and environmentally seal the semiconductor device  20  in the cavity  22  forming an essentially planar lower surface  36  opposite the surface  24  of the pre-encapsulated cavity interposer  10  at essentially the same level as that of the lower surface  18  of the second portion  16  of traces  12 . 
         [0052]    Referring to drawing  FIG. 2B , the pre-encapsulated cavity frame  10  is illustrated in cross section having a flip-chip type semiconductor device  30  attached to connection areas  15 , which extend below the lower surface  20 ′ of the encapsulant material  20  covering the lower surface  18  of the second portion  16  of the traces  12  having two or more grooves or recesses  15 ′ therein of the first portions  14  of a leads  12  using two or more solder balls  32 , or solder bumps, solder stud bumps, or gold stud bumps located between bond pads of the semiconductor device  30  and the connection areas  15 . The two or more grooves or recesses  15 ′ in the connection areas facilitate the location of the semiconductor device  30  in the cavity  22  in the proper location with respect to connection areas  15  using conventional semiconductor device attachment equipment. The two or more grooves or recesses  15 ′ may be formed having any suitable geometric shape and desired depth in the connections areas  15  by any suitable method, such as etching, coining, laser forming, etc. The cavity  22  of the pre-encapsulated cavity frame  10  having the semiconductor device  30  located therein is filled with any suitable liquid encapsulant material, underfill material, etc., to retain and environmentally seal the semiconductor device  20  in the cavity  22  forming an essentially planar lower surface  36  opposite the surface  24  of the pre-encapsulated cavity interposer  10  at essentially the same level as that of the lower surface  18  of the second portion  16  of traces  12 . 
         [0053]    Referring to drawing  FIG. 2C , the pre-encapsulated cavity frame  10  is illustrated in cross section having a flip-chip type semiconductor device  30  attached to connection areas  15 , which are located at essentially the same level as the lower surface  20 ′ of the encapsulant  20  having one or more grooves or recesses  15 ′ therein of the first portions  14  of a leads  12  using solder balls  32 , or solder bumps, solder stud bumps, or gold stud bumps located between bond pads of the semiconductor device  30  and the connection areas  15 . The one or more grooves or recesses  15 ′ in the connection areas facilitate the location of the semiconductor device  30  in the cavity  22  in the proper location with respect to connection areas  15  using conventional semiconductor device attachment equipment. The one or more grooves or recesses  15 ′ may be formed having any suitable geometric shape and desired depth in the connections areas  15  by any suitable method, such as etching, coining, laser forming, etc. The cavity  22  of the pre-encapsulated cavity frame  10  having the semiconductor device  30  located therein is filled with any suitable liquid encapsulant material, underfill material, etc., to retain and environmentally seal the semiconductor device  20  in the cavity  22  forming the essentially planar lower surface  36  opposite the surface  24  of the pre-encapsulated cavity interposer  10  at essentially the same level as that of the lower surface  18  of the second portion  16  of traces  12 . 
         [0054]    Referring to drawing  FIG. 2D , the pre-encapsulated cavity frame  10  is illustrated in cross section having a flip-chip type semiconductor device  30  attached to connection areas  15 , which extend below the lower surface  20 ′ of the encapsulant material  20  covering the lower surface  18  of the second portion  16  of the traces  12  having two or more grooves or recesses  15 ′ therein of the first portions  14  of a leads  12  using two or more solder balls  32 , or solder bumps, solder stud bumps, or gold stud bumps located between bond pads of the semiconductor device  30  and the connection areas  15 . The two or more grooves or recesses  15 ′ in the connection areas facilitate the location of the semiconductor device  30  in the cavity  22  in the proper location with respect to connection areas  15  using conventional semiconductor device attachment equipment. The two or more grooves or recesses  15 ′ may be formed having any suitable geometric shape and desired depth in the connections areas  15  by any suitable method, such as etching, coining, laser forming, etc. The cavity  22  of the pre-encapsulated cavity frame  10  having the semiconductor device  30  located therein is filled with any suitable liquid encapsulant material, underfill material, etc., to retain and environmentally seal the semiconductor device  20  in the cavity  22  forming an essentially planar lower surface  36  opposite the surface  24  of the pre-encapsulated cavity interposer  10  at essentially the same level as that of the lower surface  18  of the second portion  16  of traces  12 . 
         [0055]    Referring to drawing  FIG. 2E , the pre-encapsulated cavity frame  10  is illustrated in cross section having a flip-chip type semiconductor device  30  attached to connection areas  15 , which are located at essentially the same level as the lower surface  20 ′ of the encapsulant  20  having a roughened surface  15 ″ therein of the first portions  14  of a leads  12  using solder balls  32 , or solder bumps, solder stud bumps, or gold stud bumps located between bond pads of the semiconductor device  30  and the connection areas  15 . The roughened surface  15 ″ in the connection areas  15  facilitate the location of the semiconductor device  30  in the cavity  22  in the proper location with respect to connection areas  15  using conventional semiconductor device attachment equipment. The roughened surface  15 ″ may be formed having any suitable geometric shape and desired depth in the connections areas  15  by any suitable method, such as etching, coining, laser forming, etc. The cavity  22  of the pre-encapsulated cavity frame  10  having the semiconductor device  30  located therein is filled with any suitable liquid encapsulant material, underfill material, etc., to retain and environmentally seal the semiconductor device  20  in the cavity  22  forming an essentially planar lower surface  36  opposite the surface  24  of the pre-encapsulated cavity interposer  10  at essentially the same level as that of the lower surface  18  of the second portion  16  of traces  12 . 
         [0056]    Referring to drawing  FIG. 3 , a pair of pre-encapsulated cavity frames  10  are illustrated in cross section, each having a semiconductor device  30  located in cavity  22 . Each semiconductor device  20  is attached to the encapsulation material  20  using a suitable adhesive  38 , which may be either a layer of adhesive or a double-sided adhesive tape, to retain the semiconductor device  20  in the cavity  22  prior to the filling of the cavity  22  with any suitable liquid encapsulant material, underfill material, etc., to retain and environmentally seal the semiconductor device  20  in the cavity  22  forming an essentially planar lower surface  36  opposite the surface  24  of the pre-encapsulated cavity frame  10  at essentially the same level as that of the lower surface  18  of the second portion  16  of traces  12 . As illustrated, the first portions of the traces  12  are connected to the bond pads of the semiconductor device  30  using bond wires  40 , rather than a flip-chip style type of attachment. If desired, an anisotropic conductive film  42  (shown in dashed lines) or non-conductive film  42  (shown in dashed lines) may be used to seal the semiconductor device in the cavity  22  without the use of an encapsulant material  34  in the cavity  22 . A solder paste  44  may be applied to the connection areas  18  of the second portion of traces  12  for reflow and connection of the pre-encapsulated cavity interposers  10 . 
         [0057]    Referring to drawing  FIG. 4 , the pre-encapsulation frame  10  is illustrated in cross section having a flip-chip type semiconductor device  30  having bond pads on the active surface thereof about two sides of the semiconductor device  30  attached to the first portion  14  of the traces  12  with the cavity  22  filled with any suitable liquid encapsulant material, underfill material, etc., to retain and seal the semiconductor device  20  in the cavity  22  forming an essentially planar lower surface  36  opposite the surface  24  of the pre-encapsulated cavity frame  10  at essentially the same level as that of the lower surface  18  of the second portion  16  of traces  12 . If desired, a layer of adhesive or a double-sided adhesive tape  38  may be used to retain the semiconductor device  30  in the cavity  22  prior to the reflow of the solder balls  32  to attach the semiconductor device  30  to the connection areas  15  of the first portion  14  of the traces  12 . 
         [0058]    Referring to drawing  FIG. 5 , the pre-encapsulated cavity frame  10  is illustrated in cross section configured to a semiconductor device  30  having bond pads on the active surface thereof along one side thereof. The traces  12  are formed in a pattern so that a first portion  14  of one trace is longer than the first portion  14  of another trace  12  to connect to a desired bond pad on the semiconductor device  30  in a flip-chip style type of arrangement described hereinbefore. 
         [0059]    Referring to drawing  FIG. 5A , the pre-encapsulated cavity frame  10  is illustrated in cross section configured to a semiconductor device  30  having bond pads on the active surface thereof in a 1.5 sided configuration as known in the art. The traces  12  are formed in a pattern so that a first portion  14  of one trace is longer than the first portion  14  of another trace  12  to connect to a desired bond pad on the semiconductor device  30  in a flip-chip style type of arrangement described hereinbefore. 
         [0060]    Referring to drawing  FIG. 5B , the pre-encapsulated cavity frame  10  is illustrated in cross section configured to a semiconductor device  30  having bond pads on the active surface thereof solely along the long side of the semiconductor device  20 . The traces  12  are formed to in a pattern to vary in length and configuration so that the first portion  14  of a trace connects to a desired bond pad of the semiconductor device  30  in a flip-chip style type arrangement described hereinbefore. 
         [0061]    Referring to drawing  FIG. 5C , a pre-encapsulated cavity frame  10  is illustrated in a plan view to show the layout of the traces  12  for a 2-sided bond pad configuration for a semiconductor device  30  having bond pads on the active surface thereof located on two sides of the semiconductor device  30 . As illustrated the second portions  16  of the traces  12  extend from each side of the pre-encapsulated cavity interposer  10  to extend over bond pads  31  located on the semiconductor die  30 . The pre-encapsulated frame  10  is typically used for a semiconductor device  30  such as described in drawing  FIG. 4 . 
         [0062]    Referring to drawing  FIG. 5D , a pre-encapsulated cavity frame  10  is illustrated in plan view to show the layout of the traces  12  for a 1-sided bond pad configuration for a semiconductor device  30  having bond pads on the active surface thereof located on one side of the semiconductor device  30 . As illustrated the second portions  16  of the traces  12  extend from each side of the pre-encapsulated cavity frame  10  to extend over the bond pads  31  located on the semiconductor die  30 . The pre-encapsulated cavity frame  10  is typically used for a semiconductor device  30  such as described in drawing  FIG. 5 . 
         [0063]    Referring to drawing  FIG. 5E , a pre-encapsulated cavity frame  10  is illustrated in plan view to show the layout of the traces  12  for a 1.5-sided bond pad configuration for a semiconductor device  30  having bond pads on the active surface thereof located on 1.5 sides of the semiconductor device  30 . As illustrated the second portions  16  of the traces  12  extend from each side of the pre-encapsulated frame  10  to extend over the bond pads  31  located on the semiconductor die  30 . The pre-encapsulated frame  10  is typically used for a semiconductor device  30  such as described in drawing  FIG. 5A . 
         [0064]    Referring to drawing  FIG. 5F , a pre-encapsulated frame  10  is illustrated in plan view to show the layout of the traces  12  for a 1-sided bond pad configuration for a semiconductor device  30  having bond pads on the active surface thereof located on a long side of the semiconductor device  30 . As illustrated the second portions  16  of the traces  12  extend from each side of the pre-encapsulated cavity interposer  12  to extend over the bond pads  31  located on the semiconductor die  30 . The pre-encapsulated frame  10  is typically used for a semiconductor device  30  such as described in drawing  FIG. 5B . 
         [0065]    Referring to drawing  FIG. 6 , the pre-encapsulation frame  10  is illustrated in cross section where two pre-encapsulation frames  10  are stacked and connected in DDP form by reflowed solder paste  44  connecting the connecting surfaces  18  of the second portions  16  of the traces  12 . The semiconductor devices  30  are attached to the first portions  14  of the traces  12  in a flip-chip style type of arrangement described hereinbefore. 
         [0066]    Referring to drawing  FIG. 7 , the pre-encapsulation frame  10  is illustrated in cross section where four pre-encapsulation frames  10  are stacked and connected in QDP form by reflowed solder paste  44  connecting the connecting surfaces  18  of the second portions  16  of the traces  12 . The semiconductor devices  30  are attached to the first portions  14  of the traces  12  in a flip-chip style type of arrangement described hereinbefore. 
         [0067]    Referring to drawing  FIG. 8 , the pre-encapsulation frame  10  is illustrated in cross section configured to connect to two semiconductor devices  30  having bond pads on the active surface thereof in a one-sided configuration as known in the art. The traces  12  are formed in a pattern so that a first portion  14  of one trace is longer than the first portion  14  of another trace  12  to connect to a desired bond pad on the semiconductor device  30  in a flip-chip style type of arrangement described hereinbefore. An adhesive  38  may attach the semiconductor device  30  to the encapsulated traces  12  and to each other. The semiconductor devices  30  are stacked having an offset from each other along the side of the semiconductor device  30  having the bond pads located there along. As illustrated, some of the traces  12  are formed having a stepped second portion  14 ′ to attach to bond pads on one side of the lower semiconductor device  30 . 
         [0068]    Referring to drawing  FIG. 8A , the pre-encapsulation frame  10  is illustrated in cross section configured to connect to two semiconductor devices, a controller semiconductor device  60  and a NAND semiconductor device  50 , each having bond pads on the active surface thereof as described herein as known in the art. The traces  12  are foamed in a pattern so that an upper first portion  14  of one trace connects to bond pads of the controller semiconductor device  60  while the lower first portions  14 ′ connect to bond pads on the active surface of a NAND semiconductor device  50  in flip-chip style types of arrangement described hereinbefore. An insulating adhesive or suitable insulating adhesive tape  38 ′ may attach the semiconductor device  60  to the encapsulated traces  12  and to the semiconductor device  50 . The semiconductor devices  30  are in a stacked arrangement with the pre-encapsulation frame  10  being thicker to accommodate two semiconductor devices therein with the cavity  22  being a stepped arrangement to accommodate two semiconductor devices having different sizes. The cavity  22  is filled and environmentally sealed with a suitable encapsulant  36 . 
         [0069]    Referring to drawing  FIG. 9 , the pre-encapsulation frame  10  is illustrated in cross section in a stacked and interconnected configuration for use with a semiconductor device  60 , such as a controller semiconductor device known in the art, and another semiconductor device  50 , such as a DRAM or NAND Flash memory type semiconductor device, is a stacked configuration. Both of the pre-encapsulation frames  10  have been formed having two second portions  16  for the traces  12 . The upper pre-encapsulation frame  10  is formed having the first portions  14  of the traces  12  configured to attach to the bond pads of the semiconductor device  60 , which are located solely along one side thereof, such as described in drawing  FIG. 5B  hereinbefore in a flip-chip style type arrangement. The lower pre-encapsulation frame  10  is formed with the first portions  14  of the traces  12  configured for attachment to the bond pads on the active surface of the semiconductor device  50 , which are located along two sides thereof in a flip-chip style type arrangement as described herein. 
         [0070]    Referring to drawing  FIG. 10 , the pre-encapsulation frame  10  is illustrated in cross section in a stacked and interconnected configuration for use with a semiconductor device  60 , such as a controller semiconductor device known in the art, and two semiconductor devices  30 , such as a NAND Flash memory type semiconductor device. All of the pre-encapsulation frames  10  have been formed having two second portions  16  for the traces  12 . The upper pre-encapsulation frame  10  is formed having the first portions  14  of the traces  12  configured to attach to the bond pads of the semiconductor device  30 , which are located solely along one side thereof, such as described in drawing  FIG. 5B  hereinbefore in a flip-chip style type arrangement. The lower pre-encapsulation frames  10  are formed with the first portions  14  of the traces  12  configured for attachment to the bond pads on the active surface of the semiconductor device  50 , which are located along two sides thereof in a flip-chip style type arrangement as described herein. 
         [0071]    Referring to drawing  FIG. 11 , the pre-encapsulation frame  10  is illustrated in cross section in a stacked and interconnected configuration for use with semiconductor device  60 , such as a controller semiconductor device known in the art, and eight other semiconductor devices  50 , such as a NAND Flash memory type semiconductor device, in a stacked configuration. All pre-encapsulation frames  10  have been formed having two second portions  16  for the traces  12 . The upper pre-encapsulation frame  10  is formed having the first portions  14  of the traces  12  configured to attach to the bond pads of the semiconductor device  60 , which are located solely along one side thereof, such as described in drawing  FIG. 5B  hereinbefore in a flip-chip style type arrangement. The lower pre-encapsulation frame  10  is formed with the first portions  14  of the traces  12  configured for attachment to the bond pads on the active surface of the semiconductor device  50 , which are located along two sides thereof in a flip-chip style type arrangement as described herein. 
         [0072]    Referring to drawing  FIG. 12 , the pre-encapsulation frame  10  is illustrated in cross section in a stacked and interconnected configuration for use with semiconductor devices  50 , such as DRAM Flash memory type semiconductor device having the bond pads located on the active surface thereof in essentially a single column in essentially the center of the active surface. Both pre-encapsulation frames  10  have been formed having two second portions  16  for the traces  12 . The upper pre-encapsulation frame  10  is formed having the first portions  14  of the traces  12  configured to attach to the bond pads of the semiconductor device  50  hereinbefore in a flip-chip style type arrangement. Each pre-encapsulation frame  10  is connected to the other by reflowed solder paste  44  between the connection areas  18  of the second portions  16  of the traces  12 . 
         [0073]    Referring to drawing  FIG. 13 , the pre-encapsulation frame  10  is illustrated in cross section in a stacked and interconnected configuration for use with semiconductor devices  50 , such as DRAM Flash memory type semiconductor device, having the bond pads located on the active surface thereof in essentially a two columns in essentially the center portion of the active surface of the semiconductor devices  50 . Both pre-encapsulation frames  10  have been formed having two second portions  16  for the traces  12 . The upper pre-encapsulation frame  10  is formed having the first portions  14  of the traces  12  configured to attach to the bond pads of the semiconductor device  50  hereinbefore in a flip-chip style type arrangement. Each pre-encapsulation frame  10  is connected to the other by reflowed solder paste  44  between the connection areas  18  of the second portions  16  of the traces  12 . 
         [0074]    Referring to drawing  FIG. 14 , the pre-encapsulation frame  10  is illustrated in cross section in a stacked and interconnected configuration for with use for a variety of different types of semiconductor devices  50 ,  60  having bond pads located on their active surfaces along a number of sides thereof as described hereinbefore with all semiconductor devices  50 ,  60  connected to circuits on a suitable substrate  1 , such as a printed circuit board. All pre-encapsulation frames  10  have been formed having three second portions  16  for the traces  12 . The upper pre-encapsulation frame  10  is formed having the first portions  14  of the traces  12  configured to attach to the bond pads of the semiconductor device  50  hereinbefore in a flip-chip style type arrangement. Each pre-encapsulation frame  10  is connected to the other and to the circuits on the substrate  1  by reflowed solder paste  44  between the connection areas  18  of the second portions  16  of the traces  12  and the circuits on the substrate  1 . 
         [0075]    Referring to drawing  FIG. 15 , a pre-encapsulation frame  10  is illustrated in cross section in a configuration for use with a CMOS imager semiconductor device (not illustrated). The pre-encapsulation frame  10  includes a central aperture  11  therein. 
         [0076]    Referring to drawing  FIG. 15A , the pre-encapsulation frame  10  illustrated in cross section in  FIG. 15  is illustrated in a top view showing the four sides forming the pre-encapsulation frame  10 , the central aperture  11 , first portion  14  and second portion  16  of traces  12 , and encapsulation material  20 . 
         [0077]    Referring to drawing  FIG. 15B , the pre-encapsulation frame  10  is illustrated in cross section having a CMOS imager semiconductor device  70  having an imaging area  72  connected in a flip-chip style to using gold to solder bumps to the first portion  14  of the traces  12  and having a glass  74 , a transparent member, located over central aperture  11  contacting the upper surface  24  of the encapsulant  20  and attached to the CMOS imager semiconductor device  70  by members  76  extending from a lower surface  78  of the glass  74 , through the aperture  11 , and attached to the CMOS imager semiconductor device  70 . 
         [0078]    Referring to drawing  FIG. 15C , the pre-encapsulation frame  10  is illustrated in cross section having a CMOS imager semiconductor device  70  attached to encapsulant  20  using a suitable adhesive with the CMOS imager semiconductor device  70  connected to first portions  14  of the traces  12  using bond wires. The glass  74  is located over aperture  11  having the members  76  attaching the glass to the encapsulant  20 . The second portions  16  of traces  12  are formed having connection areas  18 . 
         [0079]    Referring to drawing  FIG. 15D , the pre-encapsulation frame  10  is illustrated in cross section, as in drawing  FIG. 15  and top view in drawing  FIG. 15A , for the first step in the forming of the CMOS imager semiconductor device  70  attachment thereto in a flip-chip style. In step  2 , the CMOS imager semiconductor device  70  is attached to the first portions  14  of the traces  12  using gold to reflowed solder ball or bump type attachment in a flip-chip type style. In step  3 , the members  76  are attached to the CMOS imager semiconductor device  70  using a suitable type adhesive. In step  4 , the glass  74  is attached to the members  74  using a suitable adhesive. In step  5 , a suitable encapsulant  34  is used to fill the cavity  22  to seal the CMOS imager semiconductor device  70  in the pre-encapsulation frame  10 . In step  6 , solder paste  44  is applied to contact areas  18  of the second portion  16  of the traces  12  for connection of the CMOS imager semiconductor device  70  to a camera chip module (not shown). This process may also be used for a CMOS imager semiconductor device  70  having connections to the first portions  14  of the traces  12  using bond wires has described herein with respect to drawing  FIG. 15C . 
         [0080]    Referring to drawing  FIG. 16 , the pre-encapsulation frame  10  is illustrated in cross section as shown in drawing  FIG. 15C  having a CMOS imager semiconductor device  70  attached thereto and a series of pre-encapsulation frames  10  having various semiconductor devices attached thereto in a stacked configuration as illustrated in drawing  FIG. 14 . 
         [0081]    Referring to drawing  FIG. 17 , the pre-encapsulation frame  10  is illustrated in cross section as shown in drawing  FIG. 15C  having a CMOS imager semiconductor device  70  attached thereto and an additional pre-encapsulation frame  10  having a additional lens  86  attached to first portions  14  of traces  12  by a suitable adhesive  88  in cavity  22  of the pre-encapsulation frame  10 . The second portions  16  of the traces  12  are connected using solder paste  44  at the connection areas  18  of the second portions  16 . As many additional lenses  86  may be attached to pre-encapsulation frames  10  and stacked on a preceding pre-encapsulation frame  10  having a lens  86  installed therein. 
         [0082]    Referring to drawing  FIG. 18 , a pre-encapsulation frame  10  is illustrated in cross section as shown in drawing  FIG. 15C  having a CMOS imager  70  attached thereto and an additional pre-encapsulation frames  10  having an additional lens  86  attached to first portions  14  of traces  12  by a suitable adhesive  88  in cavity  22  of the pre-encapsulation frame  10 . The second portions  16  of the traces  12  are connected using solder paste  44  at the connection areas  18  of the second portions  16 . As many additional lenses  86  may be attached to pre-encapsulation frames  10  and stacked on a preceding pre-encapsulation frame  10  having a lens  86  installed therein. As illustrated, the additional two lenses  86  are used for an optical zoom effect for a camera module (not shown). 
         [0083]    Having described the inventions of the pre-encapsulated interposer frame, it will be apparent to one of ordinary skill in the art that changes and modifications may be made thereto, such as the addition of vertical molded guides in the cavity of the pre-encapsulated interposer frame to guide a semiconductor device in position in the cavity, using a pre-capsulated interposer frame to house three or more semiconductor devices, the use of four or more second portions of the traces connected to first portions of the traces to connect to a semiconductor device, etc. Such changes or modifications are intended to be covered by the claimed inventions.