Abstract:
A regulator circuit and a method for regulating an output voltage. The regulator circuit includes an undervoltage protection stage capable of operating in a plurality of operating modes. In one mode, the undervoltage protection stage compensates for a low undervoltage appearing in the output voltage and in another mode it compensates for a large undervoltage appearing in the output voltage. When the output voltage has a low undervoltage, a portion of the current from a current source is routed to a feedback network to balance the input voltages of the undervoltage protection stage and to place the voltage regulator in a steady state operating mode. When the output voltage has a large undervoltage, the undervoltage protection stage turns on a current sourcing transistor that cooperates with the current from the current source to quickly charge a compensation capacitor and increase the power appearing at the output of the voltage regulator.

Description:
FIELD OF THE INVENTION 
       [0001]    This invention relates, in general, to voltage regulation and, more particularly, to undervoltage protection of a regulated voltage. 
       BACKGROUND OF THE INVENTION 
       [0002]    Voltage regulators that provide AC/DC rectification typically include a full wave voltage rectifier stage, such as, for example, a diode bridge, a main Switch Mode Power Supply (“SMPS”) stage, and a Power Factor Correction (“PFC”) stage inserted between the line and the main SMPS. The SMPS provides regulation of an output waveform and the PFC stage draws a sinusoidal current from the line and provides Direct Current (“DC”) voltage to the main SMPS. For many systems to operate properly, it is desirable for the output voltage of the PFC stage to be within a specified range. PFC circuits deliver a squared sinusoidal power that matches an average power demand of the load. Thus, when the power fed to the load is lower than the demand, an output capacitor within the PFC stage compensates for the lack of energy by discharging and when the power fed to the load is greater than the demand, the capacitor stores the excess energy. As a consequence, a ripple appears in the output voltage that designers compensate for by integrating the output voltage. A drawback with the integration is that it degrades the dynamic performance of the power supplies and makes them slow. For example, an abrupt decrease in the load results in a high output voltage overshoot and an abrupt increase in the load results in a high output voltage undershoot. 
         [0003]    Hence, a need exists for a voltage regulator and a method of improving the dynamic performance and speed of the voltage regulator. In addition, it is desirable for the voltage regulator to be cost and time efficient to manufacture. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]    The present invention will be better understood from a reading of the following detailed description, taken in conjunction with the accompanying drawing figure in which the single FIGURE is a schematic diagram of a voltage regulator having an undervoltage protection circuit in accordance with an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0005]    The single FIGURE is a schematic diagram of a voltage regulator  10  comprising an undervoltage protection stage  14  having an input coupled to a feedback stage  12  and an output coupled to a Pulse Width Modulation (“PWM”) regulation stage  16 . An output of PWM regulation stage  16  is coupled to an input of a Power Factor Correction (“PFC”) stage  18  and an output  20  of PFC stage  18  serves as an output of voltage regulator  10 . An output voltage V OUT  appears at output  20 . A load  22  is coupled between output  20  and a source of operating potential such as, for example, V SS . By way of example, source of operating potential V SS  is set to ground. A voltage rectifier  24  is connected to an input  26  of voltage regulation stage  18 . 
         [0006]    Feedback stage  12 , also referred to as a feedback network, is coupled to output  20  and may be comprised of, for example, a pair of resistors  30  and  32 . One terminal of resistor  32  is coupled for receiving a source of operating potential such as, for example, V SS , and the other terminal of resistor  32  is commonly connected to a terminal of resistor  30  at a node  34 . The other terminal of resistor  30  is connected to output  20 . The commonly connected terminals of resistors  30  and  32  that are connected at node  34  are also connected to an input of undervoltage protection stage  14 . It should be understood that feedback stage  12  is not limited to being a resistor divider network. Although feedback stage  12  may be integrated in a semiconductor substrate along with undervoltage protection stage  14 , PWM regulation stage  16 , and PFC stage  18 , it is preferably provided as an off-chip circuit network. Feedback stage  12  is also referred to as being a feedback network or a feedback section. 
         [0007]    In accordance with one embodiment, undervoltage protection stage  14  comprises an error amplifier  38 , a current source  47 , and a mirror transistor  49 . Error amplifier  38  comprises a differential input stage  40 , a difference amplifier  41 , a current source transistor  42 , and a current sink transistor  44 . Differential input stage  40  has an inverting input and a non-inverting input which serve as inputs of undervoltage protection circuit  14 . An output of differential input stage  40  is connected to an input of difference amplifier  41 . An output of difference amplifier  41  is connected to the base of transistor  42  and another output of difference amplifier  41  is connected to the base of transistor  44 . Error amplifiers are known to those skilled in the art. The collector of transistor  42  is coupled for receiving a source of operating potential such as, for example, V DD . By way of example, source of operating potential V DD  is set to 5 volts. The emitter of transistor  42  is connected to the collector of transistor  44  at node  46  and the emitter of transistor  44  is coupled for receiving a source of operating potential such as, for example, V SS . Node  46  serves as an output of undervoltage protection stage  14  and is connected to the input of PWM regulation stage  16 . In addition, node  46  is coupled to the inverting input of differential input stage  40  through a charge storage device  48 . By way of example, charge storage device  48  is a compensation capacitor. One terminal of a current source  47  is coupled for receiving a source of operating potential such as, for example, V DD , and the other terminal is connected to node  46  and to a terminal of compensation capacitor  48 . Current source  47  provides a current I SOURCE0  to node  46 . Undervoltage protection stage  14  further includes a mirror transistor  49  having a base connected to the base of current source transistor  42 , a collector connected to the inverting input of differential input stage  40 , and an emitter coupled for receiving a source of operating potential such as, for example V SS . Although transistors  42 ,  44 , and  49  are shown and described as bipolar transistors, it should be understood that this is not a limitation of the present invention. For example, they can be Field Effect Transistors (“FETs”) having gates, sources, and drains. It should be further understood that the bases of bipolar transistors and the gates of FETs are also referred to as control electrodes and the emitters and collectors of bipolar transistors are also referred to as current carrying electrodes. Likewise, the drains and sources of FETs are also referred to as current carrying electrodes. 
         [0008]    Circuit implementations for a voltage rectifier such as voltage rectifier  24  and a PWM regulation stage such as PWM regulation stage  16  are known to those skilled in the art. 
         [0009]    PFC correction stage  18  comprises a FET  50  having a gate that serves as an input of PFC circuit  18 , a drain coupled to voltage rectifier stage  24  through an inductor  52 , and a source coupled for receiving a source of operating potential such as, for example, V SS . The source of FET  50  is also connected to the substrate in which FET  50  is formed. The drain of FET  50  is connected to the anode of a diode  54  and the cathode of diode  54  is connected to one terminal of an output capacitor  56 . The other terminal of output capacitor  56  is coupled for receiving a source of operating potential such as, for example, V SS . Thus, a terminal of diode  54  and a terminal of output capacitor  56  are commonly connected to each other to form output  20 . Preferably, load  22  is coupled in parallel with capacitor  56 . 
         [0010]    In operation, PFC stage  18  receives a rectified voltage signal from voltage rectifier  24 , boosts the rectified voltage signal, and generates an output voltage V OUT  at output  20 . Output voltage V OUT  is fed back to feedback network  12  which generates a current I R30  that flows through resistor  30  and a current I R32  that flows through resistor  32 . The sum of voltage V SS  and the voltage across resistor  32  created by current I R32  equals the voltage at node  34 , i.e., voltage V FB  at node  34 . Feedback signal V FB  appears at the inverting input of differential input stage  40 . During operation in the steady state operating mode or condition, i.e., steady state operation, voltage regulator  10  maintains the signal or voltage at the inverting input to be at a value substantially equal to the signal or voltage at the non-inverting input of error amplifier  38 , i.e., voltage V REF . Thus, the voltages at the inputs of differential input stage  40  substantially equal reference voltage V REF . During this operating mode, differential input stage  40  generates an error signal that is used by difference amplifier  41  to generate a control signal for switching on or activating current sink transistor  44  and a control signal for switching off current source transistor  42 . Switching on a transistor is also referred to as turning on the transistor and, switching off a transistor is also referred to as turning off the transistor. Thus, current sink transistor  44  sinks a current I SINK  from node  46  and current source  47  sources a current I SOURCE0  to node  46 . Current I SINK  is substantially equal to current I SOURCE0 . It should be noted that when current is sunk or transmitted away from a node it flows away from the node and when a current is sourced to or transmitted to a node it flows toward the node. It should be further noted that during steady state operation compensation capacitor  48  is neither actively charged nor actively discharged, but a nominal voltage is maintained thereacross. 
         [0011]    In an operating mode or condition in which output voltage V OUT  has a small undershoot, currents I R30  and I R32  which flow through resistors  30  and  32 , respectively, are less than their nominal values. By way of example, a nominal output voltage V OUT  is approximately 400 volts and a light or small undershoot is approximately 10 volts or less. In particular, current I R32  flowing through resistor  32  will be too low to maintain node  34  at reference voltage level V REF . In this case, transistor  44  reduces or decreases current I SINK  such that the sum of currents I SOURCE0  and I SINK  at node  46  is no longer zero. It should be noted that current I SINK  is reduced to a non-zero level. The difference between current I SOURCE0  and reduced current I SINK , i.e., a difference current, flows through compensation capacitor  48  and supplements current I R32  flowing through resistor  32 , thereby raising the voltage at the inverting input of error amplifier  38  so that it is substantially the same as reference voltage V REF . 
         [0012]    In an operating mode or condition in which output voltage V OUT  has a large undershoot, i.e., output voltage V OUT  is lower than a nominal value by more than about 30 volts, current source  47  is unable to maintain the voltage at the inverting input of differential input stage  40  at a value substantially equal to reference voltage V REF . Differential input stage  40  generates an error signal that is amplified by difference amplifier  41 , which in turn generates a control signal that switches off current sink transistor  44  and a control signal that switches on current source transistor  42 . Thus, current sink transistor  44  sinks substantially zero current and current source transistor  42  and mirror transistor  49  generate currents I SOURCE1  and I MIRROR , respectively. A current substantially equal to the sum of the currents I SOURCE1 , and I MIRROR  quickly charge compensation capacitor  48  and provide a current to node  34 . Mirror transistor  49  sinks current I MIRROR  from node  34  which is substantially equal to the current that is provided by source transistor  42 . Because mirror transistor  49  sinks or removes a current from node  34  substantially equal to current I SOURCE1  provided to node  34  by current source transistor  42 , current I SOURCE1  provided by current source transistor  42  does not flow through resistor  32  and does not help maintain the voltage at the inverting input of differential input stage  40  at a level equal to reference voltage V REF . In other words, current I SOURCE1  provided by current source transistor  42  is absorbed by mirror transistor  49 . 
         [0013]    Quickly charging compensation capacitor  48  results in a rapid increase in the voltage at node  46 . This voltage is injected into PWM stage  16  to control the power delivered by PFC stage  18  to load  22 . Thus, rapidly charging capacitor  48  leads to an increase in the power delivered to load  22  and hence to rapidly mitigate any undershoot that may appear in output voltage V OUT . 
         [0014]    By now it should be appreciated that a regulator circuit having an undervoltage protection stage and method for regulating output voltage have been provided. In steady state operation, output voltage V OUT  is at its desired or nominal level and the current I R30  that flows through resistor  30  is substantially the same as current I R32  that flows through resistor  32  in response to reference voltage V REF  appearing across resistor  32 . Since reference voltage V REF  is present on the inverting input of differential input stage  40 , substantially no current flows through capacitor  48  and current I SINK  cancels current I SOURCE0  supplied by current source  47 . 
         [0015]    If output voltage V OUT  decreases, current IR 30  also decreases. When voltage V OUT  and current IR 30  decrease to a level that current IR 30  is not sufficient to maintain the voltage at node  34  to be substantially equal to reference voltage V REF , current I SINK  decreases so that a difference current equal to the difference between current I SOURCE0  and I SINK  provides additional current through resistor  32  to maintain node  34  at a voltage substantially equal to reference voltage V REF . This current also charges capacitor  48  and increases the voltage at node  46 , which increases the power delivered to load  22  by PFC stage  18  and thereby decreases the amount of undershoot appearing in output voltage V OUT . 
         [0016]    If the undershoot in output voltage V OUT  is so severe that current I SOURCE0  sourced by current source  47  is not large enough to maintain the voltage at node  34  substantially equal to reference voltage V REF , current I SINK  from current sink  44  decreases to zero and current source  42  provides additional current I SOURCE . This condition occurs when the undershoot voltage is greater than a voltage equal to the product of current I SOURCE0  and the resistance value of resistor  30 . Current I SOURCE1  is mirrored by mirror transistor  49  and extracted from node  34 , thereby preventing it from maintaining the voltage at node  34  equal to reference voltage V REF . Thus, the voltage at node  34  remains lower than reference voltage V REF  and error amplifier  38  causes current source transistor  42  to source its maximum current to force the voltage appearing at node  34  to be equal to reference voltage V REF . Mirror transistor  49  compensates for this action by absorbing a current substantially equal to current I SOURCH1  produced by current source transistor  42 . Because mirror transistor  49  absorbs current I SOURCE1 , this current charges compensation capacitor  48  without raising the voltage at node  34 . An advantage of the present invention is that current I SOURCE1  helps to charge compensation capacitor  48  at a very high speed, which increases the voltage at node  46  and helps to decrease the undershoot voltage present in output voltage V OUT . Once the undershoot voltage is less than a voltage substantially equal to the product of current I SOURCE0  and the resistance value of resistor  30 , output voltage V OUT  is no longer in the severe undershoot condition but may be in a light undershoot or a steady state condition. 
         [0017]    Although certain preferred embodiments and methods have been disclosed herein, it will be apparent from the foregoing disclosure to those skilled in the art that variations and modifications of such embodiments and methods may be made without departing from the spirit and scope of the invention. For example, the circuit can be modified to overcome overshoot present in the output voltage. One technique for implementing these modifications is to replace current source  47  with a current sink, remove mirror transistor  49  and couple a mirror transistor to transistor  44 . It is intended that the invention shall be limited only to the extent required by the appended claims and the rules and principles of applicable law.