Abstract:
A system with signal converter devices, in particular, ADCs (analog-to-digital converters), a device for use in a signal converter system, and a method for operating a signal converter system is disclosed. In one embodiment, a system with a plurality of signal converter devices is provided, each signal converter device being adapted to variably be assigned one of several predefined roles in the system.

Description:
BACKGROUND  
       [0001]    The invention relates to a system with signal converter devices, in particular, ADCs (analog-to-digital converters), a device for use in a signal converter system, and a method for operating a signal converter system. 
         [0002]    Conventional microcontroller or microprocessor systems comprise one or several CPUs (central processing units). The CPU(s) are connected to one or several memories, e.g. a program memory, and a data memory, etc. 
         [0003]    The memories may be provided on the same chip, as the CPU(s) (“embedded” microcontroller or microprocessor system), or alternatively separately from the CPU(s). 
         [0004]    The program memory, e.g., may store the series of instructions to be executed by the CPU(s) i.e., the program, and the data memory, e.g., respective variables, e.g., variables to be changed by the CPU(s) when executing the program. 
         [0005]    In addition, conventional microcontroller or microprocessor systems often comprise one or several signal converter devices, e.g., ADCs (analog-to-digital converters). 
         [0006]    By use of an ADC, a continuous input signal, e.g., an analog measuring voltage, a respective current signal, etc., can be converted into a digital number. The digital number then, e.g., might be processed by the CPU(s). 
         [0007]    The number of different digital numbers an ADC can produce for the allowed range of a continuous input signal is called the “resolution” of the ADC. For example, an ADC that encodes an analog measuring voltage into one of 256 different digital numbers (0.255) has a resolution of eight bits, since 2 8 =256. 
         [0008]    As the input signal is continuous in time, it is necessary to define the rate at which new digital numbers/new discrete values are to be sampled from the input signal. The rate of new values is called the “sampling rate” or “sampling frequency” of the ADC. 
         [0009]    For some applications, it might be necessary to sample two or more different measuring voltages at the same time. Typical examples are the sampling of measuring voltages referring to two parallely measured phase currents of an AC motor, the position measurement with resolver, etc. 
         [0010]    For these applications, several separate sample and hold devices might be used, whereby the sample and hold devices in parallel at the same capture the respective different measuring voltages, and sequentially provide the captured analog values to the ADC, for sequential conversion of the analog values into respective digital numbers. Alternatively, respective sample and hold devices might be provided on the ADC itself. 
         [0011]    As a further alternative, several ADCs might be used, each ADC in parallel being provided with one of the above different measuring voltages, which are parallely sampled, and then converted in respective digital numbers. 
         [0012]    An advantage of using several ADCs instead of several sample and hold devices is that more measurements/samplings can be performed within a given period of time. 
         [0013]    However, when performing parallel measurements/samplings, the several ADCs need to be synchronized. 
         [0014]    To synchronize the ADCs, a “master” ADC might be provided, and one or several “slave” ADCs. Whenever the master ADCs requests a parallel conversion/sampling from a slave ADC, the slave ADC performs the respective conversion at a predefined point of time (e.g., with respect to a system clock). When the master ADC does not request parallel conversion from the slave ADC, the respective slave ADC might perform separate, independent measurements. However, due to the predefined roles of the ADCs (as either “master” ADC, or “slave” ADC), the flexibility of the system is limited. 
         [0015]    For these or other reasons, there is a need for the present invention. 
       SUMMARY  
       [0016]    One embodiment provides a system with a plurality of signal converter devices, each signal converter device being adapted to variably be assigned one of several predefined roles in the system. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0017]    The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. 
           [0018]      FIG. 1  schematically illustrates a system with ADCs (analog-to-digital converters) according to one embodiment of the invention. 
           [0019]      FIG. 2  schematically illustrates a synchronization register of an ADC illustrated in  FIG. 1 . 
           [0020]      FIG. 3  schematically illustrates a portion of a first and a second ADC illustrated in  FIG. 1 . 
           [0021]      FIG. 4  schematically illustrates a further portion of the first and second ADC illustrated in  FIG. 1 . 
           [0022]      FIG. 5  schematically illustrates a still further portion of the first and second ADC illustrated in  FIG. 1 . 
       
    
    
     DETAILED DESCRIPTION  
       [0023]    In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural or other changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. 
         [0024]      FIG. 1  illustrates a schematic, exemplary representation of a system  1  with several ADCs (analog-to-digital converters)  3   a ,  3   b ,  3   c ,  3   d  according to one embodiment of the invention. 
         [0025]    Each ADC  3   a ,  3   b ,  3   c ,  3   d  is capable of converting a continuous input signal, e.g., an analog measuring voltage, a respective current signal, etc. provided to a respective ADC  3   a ,  3   b ,  3   c ,  3   d  via one of a plurality of input channels  2   a ,  2   b ,  2   c , into a respective digital number. The digital number may then be stored in a respective one of several output registers  4   a ,  4   b ,  4   c ,  4   d  of the ADC  3   a ,  3   b ,  3   c ,  3   d . Later on, the digital number may, e.g., be read out and further processed by a respective microprocessor or microcontroller of a microcontroller or microprocessor system. 
         [0026]    The ADCs  3   a ,  3   b ,  3   c ,  3   d  may be provided on one and the same chip, or alternatively on separate chips. 
         [0027]    The system  1  may include a fixed number of ADCs  3   a ,  3   b ,  3   c ,  3   d , e.g., two, three, four or more ADCs. Alternatively, the number of ADCs  3   a ,  3   b ,  3   c ,  3   d  in the system is variably adjustable (such that the system  1  variably e.g. might comprise two, three, four or more ADCs). 
         [0028]    As will be described in further detail below, each ADC  3   a ,  3   b ,  3   c ,  3   d  is constructed similar or substantially similar. However, as also will be described in further detail below, each ADC  3   a ,  3   b ,  3   c ,  3   d  may be programmed differently, such as to assign one of several predefined roles to a respective ADC. 
         [0029]    In particular, as will be described in further detail below, to each ADC  3   a ,  3   b ,  3   c ,  3   d  variably the role of a “master” ADC, or the role of a “slave” ADC, or the role of an “autonomous” ADC may be assigned. Hence, for example, to the first ADC  3   a  (“ADC 1”) according to the specific needs of a first application the role of a “master” ADC might be assigned, whilst according to the specific needs of a second application, different from the first application to the same ADC  3   a  (“ADC 1”) the role of a “slave” ADC might be assigned. 
         [0030]    As also will be described in further detail below, to each “master” ADC, one or several variably selectable “slave” ADCs might be assigned. Hence, for example, when the role of a “master” ADC is assigned to the first ADC  3   a  (“ADC 1”), according to the specific needs of a third application, e.g., a second ADC  3   b  (“ADC 2”) might be assigned as “slave” ADC to the first ADC  3   a  (“ADC 1”), whilst according to the specific needs of a fourth application, different from the third application, a third and fourth ADC  3   c ,  3   d  (“ADC 3” and “ADC4”) might be assigned as “slave” ADCs to the first ADC  3   a  (“ADC 1”), etc. 
         [0031]    The total number of ADCs to which the role of a “master” ADC, and/or the total number of ADCs to which the role of a “slave” ADC is assigned is variable. 
         [0032]    A “master” ADC and the one or several “slave” ADCs assigned to this “master” ADC form a respective “synchronization group”. As follows from the above explanation, the total number of “synchronization groups” of the system.  1  is variably adjustable. 
         [0033]    As is illustrated in  FIG. 1 , for synchronization of the one or several “master” ADCs with their respective one or several associated “slave” ADCs—in particular, for carrying out a respective parallel conversion, a bus system  5  is provided, connecting each of the ADCs  3   a ,  3   b ,  3   c ,  3   d  of the system  1 . 
         [0034]    The bus system  5  includes a control bus  5   a , by use of which respective control signals referring to a respective set of control data provided by a respective “master” ADC might be sent from the respective “master” ADC to all other ADCs of the system  1 . The set of control data in general only is evaluated taken into account by the one or several “slave” ADCs associated with the respective “master” ADC that sends out the control signals (i.e., the one or several “slave” ADCs that belong to the same synchronization group, as the respective “master” ADC). In the one or several associated “slave” ADCs, the received set of control data is used to control the respective analog-to-digital conversion to be performed (e.g., with regards to channel selection, sampling rate, resolution, timing, etc.). Further, a respective “master” ADC ignores respective sets of control data received via the control bus  5   a . Instead, a respective “master” ADC uses his “own” set of control data (i.e., the above set of control data, e.g. stored in respective registers of the respective “master” ADC, and sent by the respective “master” ADC to the other ADCs via the control bus  5   a ) to control the respective analog-to-digital conversion to be performed in the respective “master” ADC. 
         [0035]    Hence, the analog-to-digital conversions of a respective synchronization group (comprising a respective “master” ADC, and one or several associated “slave” ADCs) is controlled by one single set of control data, provided by the respective “master” ADC of the respective synchronization group. 
         [0036]    In contrast, in an “autonomous” ADC to which neither the role of a “master” ADC, nor the role of a “slave” ADC was assigned (or more precisely, the role of a “master” ADC without any associated “slave” ADC) only a respective “own” set of control data (i.e., only a set of control data stored in respective registers of the respective ADC) is used to control the respective analog-to-digital conversion to be performed. 
         [0037]    As is further illustrated in  FIG. 1 , the bus system  5  in addition to the control bus  5   a  includes a status bus  5   b , by use of which respective status signals referring to status information data, e.g., provided by a respective “slave” ADC might be sent from the respective “slave” ADC to all other ADCs of the system  1 . The status information data in general only is evaluated/taken into account by the “master” ADC associated with the “slave” ADC that sends out the status signals (i.e., the “master” ADC that belongs to the same synchronization group, as the respective “slave” ADC). With the status information data, it might be signalized that a respective “slave” ADC is idle/ready for a new conversion, or not idle/not ready for a new conversion (e.g., because the previous conversion has not yet been finished). 
         [0038]    In the “master” ADC, it is checked by use of the status information data received from all associated “slave” ADCs whether or not all associated “slave” ADCs are idle/ready for new conversions. If one or several associated “slave” ADCs are not idle/not ready, the “master” ADC waits till it receives from all associated “slave” ADCs respective status information data that show that all associated “slave” ADCs are idle/ready for new conversions. Only then, and if the “master” ADC itself is idle/ready for a new conversion the “master” ADC starts a respective (parallel) conversion (and correspondingly similar (i.e., in parallel) the associated “slave” ADCs (see below)). 
         [0039]    Hence, simultaneous, parallel conversions are carried out by all ADCs of the same synchronization group, with the respective sampling phases starting at the same moment. Thereby, respective continuous input signals provided at one and the same, or different input channels  2   a ,  2   b ,  2   c  (see below) are converted into respective digital numbers, and stored in the corresponding output registers  4   a ,  4   b ,  4   c ,  4   d.    
         [0040]    Thereby, it might be achieved that two or more different measuring voltages provided at respective input channels  2   a ,  2   b ,  2   c  are sampled at the same time (e.g., two parallely measured—phase currents of an AC motor, several parallely measured—resolver voltages etc.). 
         [0041]    In contrast to a “master” or “slave” ADC, an “autonomous” ADC need not evaluate/take into account any status information data provided via the status bus  5   b . Hence, an “autonomous” ADC might start a conversion irrespective of status information provided by other ADCs. 
         [0042]    As will be described in further detail below, to assign the above roles (“master”, “slave”, or “autonomous”) to the ADCs  3   a ,  3   b ,  3   c ,  3   d , and to synchronize the ADCs  3   a ,  3   b ,  3   c ,  3   d  of a synchronization group, each ADC  3   a ,  3   b ,  3   c ,  3   d  includes a respective synchronization register  6   a ,  6   b ,  6   c ,  6   d  (see also  FIG. 2 ). The synchronization registers  6   a ,  6   b ,  6   c ,  6   d  of the ADCs  3   a ,  3   b ,  3   c ,  3   d  might be variably programmed by the microprocessor/microcontroller of the above microcontroller or microprocessor system during normal operation of the system. Hence, the data stored in the synchronization registers  6   a ,  6   b ,  6   c ,  6   d  according to specific needs of a respective application might be altered during the runtime of the system. 
         [0043]    As is illustrated in  FIGS. 3 ,  4  and  5 , each ADC  3   a ,  3   b ,  3   c ,  3   d  correspondingly similar as conventional ADCs comprises a digital part  7   a , an analog part  8   a ,  8   b , and an arbiter  9   a ,  9   b . The arbiter  9   a ,  9   b  e.g. decides which conversion is to be started next in a respective ADC  3   a ,  3   b ,  3   c ,  3   d.    
         [0044]    For synchronizing purposes, the arbiters  9   a ,  9   b  of ADCs of the same synchronization group have to run/have to be started in parallel (or more exactly: the state machines of the respective arbiters  9   a ,  9   b ). The same e.g. applies to the analog parts  8   a ,  8   b  (e.g., to internal dividers comprised in the analog parts  8   a ,  8   b  of ADCs of the same synchronization group/to ADC kernel clocks, controlled by respective kernel clock controls  10   a ,  10   b  of the respective ADCs, etc. (see  FIG. 3 )). 
         [0045]    For carrying out a synchronized start of the arbiters  9   a ,  9   b /analog parts  8   a ,  8   b , etc., a variable ANON (Analog On) stored in a register  11   a ,  11   b  of a respective ADC is set to a first, predefined value, e.g., to “00 B ” (see  FIG. 3 ). 
         [0046]    As will be described in further detail below, if a respective ADC is a “master” ADC or an “autonomous” ADC, the value stored in the register  11   a ,  11   b  (e.g., the above first, predefined value “00 B ”) is supplied via a multiplexer  12   a ,  12   b  to a further register  13   a ,  13   b , stored therein, and supplied to the respective arbiter  9   a ,  9   b , and the respective kernel clock control  10   a ,  10   b  of the respective “master”/“autonomous” ADC. 
         [0047]    In response to receiving the above first, predefined value (e.g., the above value “00 B ”) from the further register  13   a ,  13   b , the above internal dividers, arbiter state machines, etc. are brought to a predefined initial state, and the respective analog part  8   a ,  8   b  is switched off. 
         [0048]    As can be seen from  FIG. 3 , the a variable ANON (Analog On) stored in the register  11   a ,  11   b  of a respective ADC is not only as said above provided to the multiplexer  12   a ,  12   b  of the respective ADC, but also via respective lines  105   a ,  105   b ,  105   c ,  105   d  (lines ANONx, ANONy, etc.) of the above buses  5   a ,  5   b  to all other ADCs of the system (more particularly, to respective inputs of the respective multiplexers  12   a ,  12   b  provided in the ADCs  3   a ,  3   b ,  3   c ,  3   d ). For example, as is illustrated in  FIG. 3 , the variable ANON (Analog On) stored in the register  11   a  of the first ADC  3   a  is provided to a first input (anon_ 0 ) of the multiplexer  12   a  of the first ADC  3   a , and via lines  105   b  of the above buses  5   a ,  5   b  e.g. to a third input (anon 2   —   i ) of the multiplexer  12   b  of the above second ADC  3   b , etc. Further, as is also illustrated in  FIG. 3 , the variable ANON (Analog On) stored in the register  11   b  of the second ADC  3   b  is provided to a first input (anon_ 0 ) of the multiplexer  12   b  of the second ADC  3   b , and via lines  105   c  of the above buses  5   a ,  5   b  e.g. to a third input (anon 2   —   i ) of the multiplexer  12   a  of the above first ADC  3   a , etc., etc. This as will be described in further detail below allows the parallel setting of variables in several different ADCs with one single CPU access. 
         [0049]    Which of the values present at the inputs (anon_ 0 , anon 1   —   i , anon 2   —   i , anon 3   —   i ) of a respective multiplexer  12   a ,  12   b  is supplied via the multiplexer  12   a ,  12   b  to the above further register  13   a ,  13   b  depends on the value of a variable STSEL stored in a register  14   a ,  14   b , i.e., a read/writable variable STSEL which as is illustrated in  FIG. 2  is part of the variables stored in the above synchronization register  6   a ,  6   b  of the respective ADC  3   a ,  3   b.    
         [0050]    If the respective ADC  3   a ,  3   b  is to take the role of a “master” ADC, or an “autonomous” ADC, the value of the variable STSEL stored in the register  14   a ,  14   b  of the respective ADC is set to a first, predefined value, e.g., to “00 B ”. In this emodiment, the value present at the first input (anon_ 0 ) of a respective multiplexer  12   a ,  12   b , i.e., the value of the variable ANON (Analog On) stored in the above register  11   a ,  11   b  is supplied via the multiplexer  12   a ,  12   b  to the above further register  13   a ,  13   b.    
         [0051]    If, instead, the respective ADC  3   a ,  3   b  is to take the role of a “slave” ADC of a “master” ADC, the value of the variable STSEL stored in the register  14   a ,  14   b  of the respective ADC is set to a further, predefined value, e.g., to “01 B ”, “10 B ”, or “11 B ”. If the value stored in the register  14   a ,  14   b  e.g. is “01 B ”, the value present at the second input (anon 1   —   i ) of a respective multiplexer  12   a ,  12   b  is supplied via the multiplexer  12   a ,  12   b  to the above further register  13   a ,  13   b . If, however, the value stored in the register  14   a ,  14   b  e.g. is “10 B ”, the value present at the third input (anon 2   —   i ) of a respective multiplexer  12   a ,  12   b  is supplied via the multiplexer  12   a ,  12   b  to the above further register  13   a ,  13   b , and if the value stored in the register  14   a ,  14   b  e.g. is “11 B ”, the value present at the fourth input (anon 3 _i) of a respective multiplexer  12   a ,  12   b  is supplied via the multiplexer  12   a ,  12   b  to the above further register  13   a ,  13   b.    
         [0052]    In particular, the value of the variable STSEL stored in the register  14   a ,  14   b  of a respective “slave” ADC is chosen such that by the respective multiplexer  12   a ,  12   b  the value of the variable ANON provided by the “master” ADC associated with the respective “slave” ADC, i.e., the “master” ADC of the same synchronization group as the respective “slave” ADC (which variable as said above is supplied at the above lines  105   a ,  105   b ,  105   c ,  105   d ) is provided to the register  13   a ,  13   b.    
         [0053]    Hence, if a respective ADC is a “slave” ADC, and when as said above the corresponding “master” ADC in sets the value of the variable ANON stored in the register  11   a ,  11   b  to the above first, predefined value “00 B ”, this value is supplied via the lines  105   a ,  105   b ,  105   c ,  105   d , and the respective multiplexer  12   a ,  12   b  of the “slave” ADC to the “slave” ADC&#39;s (further) register  13   a ,  13   b . Further, correspondingly similar as explained above with respect to the associated “master” ADC, the value (here: “00 B ”) from the register  13   a ,  13   b  is supplied to the respective arbiter  9   a ,  9   b , and the respective kernel clock control  10   a ,  10   b  of the “slave” ADC. 
         [0054]    In response to receiving the above first, predefined value (here: “00 B ”) from the further register  13   a ,  13   b , the above internal dividers, arbiter state machines, etc. of the “slave” ADC correspondingly similar as is the case in the “master” ADC, and parallel thereto (see explanations above) are brought to a predefined initial state, and the respective analog part  8   a ,  8   b  is switched off. 
         [0055]    For actually starting the arbiters  9   a ,  9   b /analog parts  8   a ,  8   b  of an “autonomous” ADC, or for simultaneously starting the arbiters  9   a ,  9   b /analog parts  8   a ,  8   b  of a “master” ADC, and the respective “slave” ADCs, after the above-mentioned first step setting the variable ANON (Analog On) of the register  11   a ,  11   b  to the above first, predefined value “00 B ” the variable ANON (Analog On) of the register  11   a ,  11   b  of the respective “autonomous” or “master” ADC is brought in accordance with the internal settings of the respective “autonomous” or “master” ADC from the above first value (“00 B ”), to a second value, different from the first value (e.g., to a value corresponding to the value of a variable stored in a register with the address GLOBALCTR, programmed in the respective ADC). 
         [0056]    As follows from the above explanations, as the respective ADC is an “autonomous” or “master” ADC (with the value of the variable STSEL stored in the register  14   a ,  14   b  being set to “00 B ”, correspondingly controlling the multiplexer  12   a ,  12   b ), the new value stored in the register  11   a ,  11   b  (i.e., the value of the variable stored in the register with the address GLOBALCTR) is supplied via the multiplexer  12   a ,  12   b  to the further register  13   a ,  13   b , stored therein, and supplied to the respective arbiter  9   a ,  9   b , and the respective kernel clock control  10   a ,  10   b  of the “autonomous” or “master” ADC. 
         [0057]    In response to receiving the above value of the variable stored in the register with the address GLOBALCTR from the further register  13   a ,  13   b , the above internal dividers, arbiter state machines, etc. start to run, in accordance with the settings defined by the variable stored in the register with the address GLOBALCTR. Hence, the respective analog part  8   a ,  8   b  is switched on. 
         [0058]    As also follows from the above explanations, if a respective ADC is a “slave” ADC, and if as said above the corresponding “master” ADC in the above second step has set the value of the variable ANON stored in the register  11   a ,  11   b  to the above second value (i.e., the value of the variable stored in the register with the address GLOBALCTR), this value due to the above setting of the respective register  14   a ,  14   b  controlling the respective multiplexer  12   a ,  12   b  of the “slave” ADC is supplied via the lines  105   a ,  105   b ,  105   c ,  105   d , and the respective multiplexer  12   a ,  12   b  of the “slave” ADC to the “slave” ADC&#39;s (further) register  13   a ,  13   b . Further, correspondingly similar as explained above with respect to the associated “master” ADC, this new value (i.e., the value of the variable stored in the register with the address GLOBALCTR) from the register  13   a ,  13   b  is supplied to the respective arbiter  9   a ,  9   b , and the respective kernel clock control  10   a ,  10   b  of the “slave” ADC. 
         [0059]    In response to receiving the above value of the variable stored in the register with the address GLOBALCTR from the further register  13   a ,  13   b , the above internal dividers, arbiter state machines, etc. of the “slave” ADC —simultaneously with the dividers, state machines, etc. of the associated “master” ADC start to run, in accordance with the settings defined by the variable stored in the register with the address GLOBALCTR provided by the “master” ADC. Hence, the respective analog part  8   a ,  8   b  of the “slave” ADC in parallel to the analog part  8   a ,  8   b  of the “master” ADC (and with corresponding settings)—is switched on. 
         [0060]    Summarized, the above variables STSEL stored in the registers  14   a ,  14   b  controlling the multiplexers  12   a ,  12   b  define which signal from which source is used to start a respective ADC kernel. 
         [0061]    Correspondingly similar as in conventional ADCs, in the arbiter  9   a ,  9   b  of the ADCs  3   a ,  3   b ,  3   c ,  3   d  of the system  1 , it is detected which conversion request has the highest priority, and which input channel number is associated to the respective conversion request. 
         [0062]    The detected channel number as illustrated in FIG.  5 —is provided from the arbiter  9   a ,  9   b  to a register  15   a ,  15   b , and from this register  15   a ,  15   b  to an alias module  16   a ,  16   b , and in unmodified form, or, if the alias function of the alias module is active, in a modified form (see below)—to the respective analog part  8   a ,  8   b  of the ADC  3   a ,  3   b ,  3   c ,  3   d.    
         [0063]    The analog part  8   a ,  8   b  then converts the continuous input signal present at the respective input channel  2   a ,  2   b ,  2   c  as specified by the received channel number into a respective digital number, which as said above is then stored in the output registers  4   a ,  4   b ,  4   c ,  4   d  of the ADC  3   a ,  3   b ,  3   c ,  3   d.    
         [0064]    If the alias function of the alias module  16   a ,  16   b  is active, it is not the channel number as detected by the arbiter  9   a ,  9   b  that is provided to the analog part  8   a ,  8   b , but a modified channel number, i.e., a channel number different to the channel number provided by the arbiter  9   a ,  9   b , but associated to this channel number, and stored in a corresponding variably programmable alias register of the alias module  16   a ,  16   b.    
         [0065]    In this case, the analog part  8   a ,  8   b  converts the input signal present at an input channel  2   a ,  2   b ,  2   c  as specified by the modified channel number (i.e., at a different input channel, as specified by the unmodified channel number). 
         [0066]    As can be seen from  FIG. 5 , the channel number as detected by the arbiter  9   a ,  9   b  of an ADC  3   a ,  3   b ,  3   c  not only is provided from the respective register  15   a ,  15   b  to the corresponding alias module  16   a ,  16   b  the analog part  8   a ,  8   b , but also via respective lines  106   a ,  106   b ,  106   c ,  106   d  of the above buses  5   a ,  5   b  (in particular, a parallel channel number sub-bus) to all other ADCs of the system (more particularly, to respective inputs of respective further multiplexers  112   a ,  112   b  provided in the ADCs  3   a ,  3   b ,  3   c ,  3   d ). 
         [0067]    For instance, as is by way of example illustrated in  FIG. 5 , the channel number parchnr_o stored in the register  15   a  of the first ADC  3   a  is provided via lines  106   d  of the above bus e.g. to a first input of the multiplexer  112   b  of the above second ADC  3   b , etc. Further, as is also illustrated in  FIG. 5 , the channel number parchnr_o stored in the register  15   b  of the second ADC  3   b  is provided via lines  106   c  of the above bus e.g. to a first input of the multiplexer  112   a  of the above first ADC  3   a , etc., etc. 
         [0068]    Which of the values present at the inputs of a respective multiplexer  112   a ,  112   b  is supplied via the multiplexer  112   a ,  112   b  to the respective arbiter  9   a ,  9   b  (and if at all any of the values is supplied to the respective arbiter  9   a ,  9   b  (see below)) again may depend on the value of the above variable STSEL of the respective ADC, i.e., the read/writable variable STSEL which as is illustrated in  FIG. 2  is part of the variables stored in the above synchronization register  6   a ,  6   b  of the respective ADC  3   a ,  3   b.    
         [0069]    Correspondingly similar as was explained above, the value of the variable STSEL of a respective “slave” ADC e.g. might be chosen such that by the respective multiplexer  112   a ,  112   b  the channel number parchnr_o as provided by the “master” ADC associated with the respective “slave” ADC, i.e., the “master” ADC of the same synchronization group as the respective “slave” ADC (which channel number as said above is supplied at the above lines  106   a ,  106   b ,  106   c ,  106   d ) is provided to the respective arbiter  9   a ,  9   b  of the “slave” ADC. 
         [0070]    Further, the variable STSEL of a “master” ADC e.g. is chosen such that the values provided on the above parallel channel number sub-bus/the lines  106   a ,  106   b ,  106   c ,  106   d  are ignored, i.e., not provided by the respective multiplexer  112   a ,  112   b  to the respective arbiter  9   a ,  9   b  of the “master” ADC. 
         [0071]    A respective arbiter  9   a ,  9   b  in addition to detecting, as said above, which conversion request has the highest priority, and which input channel number is associated to the respective conversion request also detects whether the detected input channel is programmed as source for a parallel conversion. 
         [0072]    As is illustrated in  FIG. 5 , if it is detected by a respective arbiter  9   a ,  9   b  that the detected input channel is programmed as source for a parallel conversion, and if the respective ADC comprising this arbiter  9   a ,  9   b  is a “master” ADC, a parallel request signal parqst_o provided on a respective parallel request line is activated. 
         [0073]    The parallel request signal parqst_o is provided from the respective “master” ADC—via respective lines  107   a ,  107   b ,  107   c ,  107   d  of the above buses  5   a ,  5   b  (in particular, a parallel request sub-bus) to all other ADCs of the system (more particularly, to respective inputs of respective additional multiplexers  113   a ,  113   b  provided in the ADCs  3   a ,  3   b ,  3   c ,  3   d ). 
         [0074]    For instance, as is by way of example illustrated in  FIG. 5 , the parallel request signal parqst_o provided by the first ADC  3   a  is provided via a line  107   d  of the above parallel request sub-bus e.g. to a first input of the multiplexer  113   b  of the above second ADC  3   b , etc. Further, as is also illustrated in  FIG. 5 , the parallel request signal parqst-o provided by the second ADC  3   b  is provided via a line  107   c  of the above parallel request sub-bus, e.g. to a first input of the multiplexer  113   a  of the above first ADC  3   a , etc., etc. 
         [0075]    Whether or not a respective parallel request signal parqst_o is provided from the respective multiplexer I  13   a ,  113   b  to the respective arbiter  9   a ,  9   b  of an ADC again may depend on the value of the above variable STSEL of the respective ADC, i.e., the read/writable variable STSEL which as is illustrated in  FIG. 2  is part of the variables stored in the above synchronization register  6   a ,  6   b  of the respective ADC  3   a ,  3   b.    
         [0076]    Correspondingly similar as was explained above, the value of the variable STSEL of a respective “slave” ADC e.g. might be chosen such that by the respective multiplexer  113   a ,  113   b  only a parallel request signal parqst_o of a “master” ADC associated with the respective “slave” ADC i.e., the “master” ADC of the same synchronization group as the respective “slave” ADC—is provided to the respective arbiter  9   a ,  9   b  of the “slave” ADC. 
         [0077]    Further, the variable STSEL of a “master” ADC e.g. is chosen such that the signals provided on the above parallel request sub-bus/the lines  107   a ,  107   b ,  107   c ,  107   d  are ignored, i.e., not provided by the respective multiplexer  113   a ,  113   b  to the respective arbiter  9   a ,  9   b  of the “master” ADC. 
         [0078]    If the respective multiplexers  112   a ,  112   b ,  113   a ,  113   b  of a “slave” ADC as explained above forward a respective parallel request signal parqst_o, and the associated channel number parchnr_o—both as said received from the “master” ADC associated with the respective “slave” ADC to the arbiter  9   a ,  9   b  of the “slave” ADC, the arbiter of the “slave” ADC regardless of other requests—detects the associated (parallel) conversion request from the “master” ADC as the request which has the highest priority. 
         [0079]    Hence, the channel number received from the associated “master” ADC correspondingly similar as explained above is provided from the arbiter  9   a ,  9   b  of the “slave” ADC via the above register  15   a ,  15   b  to the respective alias module  16   a ,  16   b , and from the alias module in modified or unmodified form (see explanations above) to the respective analog part  8   a ,  8   b  of the “slave” ADC. 
         [0080]    The analog part  8   a ,  8   b  of the “slave” ADC parallel to the “master” ADC then converts the continuous input signal present at the respective input channel  2   a ,  2   b ,  2   c  as specified by the received modified or unmodified channel number into a respective digital number, which as said above is then stored in the output registers  4   a ,  4   b ,  4   c ,  4   d  of the “slave” ADC. 
         [0081]    Hence, all ADCs of a synchronization group request the same channel number (as defined by the “master” ADC), but if this channel number is modified by respective alias modules  16   a ,  16   b  may convert signals from different input channels  2   a ,  2   b ,  2   c . In other words, as explained above, a requested channel number may be redirected by the alias setting of a respective alias module  16   a ,  16   b.    
         [0082]    To ensure parallel conversions, the frequencies used by respective clock generators in all ADCs of a respective synchronization group should be identical. Hence, respective registers in the ADCs defining these frequencies have to be programmed to identical values. 
         [0083]    Advantageously, a parallel conversion once started may not be aborted by the “master” ADC, even if the “master” ADC after having started the parallel conversion receives a request with higher priority, than the request associated with the parallel conversion. 
         [0084]    Any “master” ADC can work autonomously (without the associated “slave” ADCS), or if needed can work together with the associated “slaves” ADCs. 
         [0085]    If a “slave” ADC does not receive a parallel conversion request from an associated “master” ADC, the arbiter  9   a ,  9   b  of the respective “slave” ADC can detect a conversion request of the “slave” ADC itself as a request with highest priority. Hence, the respective “slave” ADC then may carry out its own requests. 
         [0086]    If a “slave” ADC which is not idle, and which currently carries out a conversion related to an own request receives a parallel conversion request from the associated “master” ADC, the parallel conversion request leads to a “cancel-repaeat” of the currently carried out conversion in the respective “slave” ADC. Hence, the currently carried out conversion is cancelled, and restarted after finishing of the parallel conversion requested by the “master” ADC. Thus, it can be achieved that a “slave” ADC currently carrying out a conversion with a relatively long sampling phase (due to e.g. a relatively high impedance of the respective source) does not block a relatively important parallel conversion. 
         [0087]    In a “master” or “autonomous” ADC, a “wait-for-read” functionality may be supported. The “wait-for-read” functionality may be activated by correspondingly programming a respective register. If the “wait-for-read” functionality is activated, a new conversion/a new parallel conversion is only carried out if the result of the previous conversion was already read out from the respective output register  4   a ,  4   b ,  4   c ,  4   d  (e.g., by the above microprocessor/microcontroller). 
         [0088]    In contrast thereto, in a “slave” ADC, an activated “wait-for-read” may be ignored, in particular, when a parallel conversion is to be carried out. Hence even if the “wait-for-read” functionality is activated a new (parallel) conversion may be carried out, and the result of the conversion may be written in a respective output register  4   a ,  4   b ,  4   c ,  4   d  even if the result of the previous conversion has not yet been read out from this register  4   a ,  4   b ,  4   c ,  4   d  (hence, the previous result is over-written). 
         [0089]    The actual start of a conversion/parallel conversion is triggered as illustrated in  FIG. 4  by the digital part  7   a ,  7   b  of a respective ADC  3   a ,  3   b . A start is triggered by the respective digital part  7   a ,  7   b  if the corresponding analog part  8   a ,  8   b  of the respective ADC (and the analog parts of the other ADCs of the same synchronization group, if any (see below)) are ready to start a new conversion. 
         [0090]    If it is detected by the digital part  7   a ,  7   b  that the corresponding analog part  8   a ,  8   b  is ready for a new conversion, the respective digital part  7   a ,  7   b  sends out a “ready” signal ready_o on a line  109 . 
         [0091]    As can be seen from  FIG. 4 , the ready signal ready_o is provided to a first input of an AND-Gate  110  of the respective ADC. Further, the ready signal ready_o is sent via a line  108   a  of the above buses  5   a ,  5   b  to all other ADCs of the system (more particularly, to respective inputs of respective OR-Gates  111   a ,  111   b ,  111   c  provided in the ADCs  3   a ,  3   b ,  3   c ,  3   d ). 
         [0092]    For instance, as is by way of example illustrated in  FIG. 4 , a ready signal provided by the digital part  7   a  of the first ADC  3   a  is provided via the line  108   a  of the above bus e.g. to a first input of a first OR-Gate of the above second ADC  3   b , and e.g. to a first input of a second OR-Gate of the above third ADC  3   c , etc. Further, as is also illustrated in  FIG. 4 , a ready signal provided by the digital part of the second ADC  3   b  is provided via a further line  108   b  of the above bus, e.g., to a first input of a first OR-Gate  111   a  of the above first ADC  3   a , and e.g. to a first input of a first OR-Gate of the above third ADC  3   c , etc., etc. 
         [0093]    As is further illustrated in  FIG. 4 , to respective second inputs of the above OR-Gates  111   a ,  111   b ,  111   c , an inverted output of respective registers  122   a ,  122   b ,  122   c  is provided. 
         [0094]    In the registers  122   a ,  122   b ,  122   c  respective variables EVALR 0 , EVALR 1 , EVALR 2  are stored, here: respective read/writable variables EVALR 0 , EVALR 1 , EVALR 2  which as is shown in  FIG. 2  are part of the variables stored in the above synchronization register  6   a ,  6   b  of the respective ADC 3   a , 3   b.    
         [0095]    If an ADC is to be an “autonomous” ADC, the values stored in the registers  122   a ,  122   b ,  122   c  are all set to a first, predefined value, e.g., to “0”. 
         [0096]    Hence, to the second inputs of all OR-Gates  111   a ,  111   b ,  111   c  of a respective ADC, due to the above inversion of the output of the registers  122   a ,  122   b ,  122   c  by respective inverters  123   a ,  123   b ,  123   c  the value “1” is provided. 
         [0097]    Therefore, in the case of an “autonomous” ADC, the value “1” is output at the outputs of the OR-Gates  111   a ,  111   b ,  111   c  regardless of the state of the first inputs of the OR-Gates  111   a ,  111   b ,  111   c.    
         [0098]    As is further illustrated in  FIG. 4 , the outputs of the OR-Gates  111   a ,  111   b ,  111   c  (here: the above values “1”) are provided to a second, third and fourth input of the above AND-Gate  110  of the respective ADC. 
         [0099]    Hence, the output of the AND-Gate  110  in the case of an “autonomous” ADC only depends on the state of the first input of the AND-Gate  110 , i.e., the ready signal provided by the digital part  7   a  of the respective “autonomous” ADC. 
         [0100]    Therefore, in the case of an “autonomous” ADC, the ready signal received on the above line  109  is forwarded via the AND-Gate  110  to a line  120 , which is connected to an input of the digital part  7   a  of the respective ADC. 
         [0101]    If the digital part  7   a  via the line  120  receives a ready signal, it triggers the start of a conversion/parallel conversion by sending a “start” signal on a line  121  to the respective analog part  8   a ,  8   b.    
         [0102]    If an ADC is to be a “master” or “slave” ADC, the values stored in some or all of the registers  122   a ,  122   b ,  122   c  are set to a second, predefined value, e.g., to “1” for all those registers  122   a ,  122   b ,  122   c  associated with OR-Gates  111   a ,  111   b ,  111   c  connected via respective lines  108   a ,  108   b ,  108   c ,  108   d  with digital parts of ADCs of the same synchronization group, as the respective “master” or “slave” ADC. 
         [0103]    For example, if the first ADC  3   a  (e.g., as a “master” ADC), and the second ADC  3   b  (e.g., as a “slave” ADC) are to form a synchronization group, in the register  122   a  of the first ADC  3   a , there is to be stored a value EVALR 0 =“1”, in the register  122   b , there is to be stored a value EVALR 1 =“0”, and in the register  122   c , there is to be stored a value EVALR 2 =“0”. 
         [0104]    Hence, to the second inputs of the OR-Gates  111   b ,  111   c  of the first ADC  3   a , —due to the above inversion of the output of the registers  122   b ,  122   c  —the value “1” is provided, and to the second input of the OR-Gate  111   a  of the first ADC  3   a , the value “0”. 
         [0105]    Therefore, the value “1” is output at the outputs of the OR-Gates  111   b ,  111   c —regardless of the state of the first inputs of the OR-Gates  111   b ,  111   c.    
         [0106]    However, the value output at the output of the OR-Gate  111   a  depends on the state of the first input of the OR-Gate  111   a : The output of the OR-Gate  111   a  only is “1” if the OR-Gate  111   a  via the line  108   b —receives a respective start signal ready 1   —   i  from the second ADC  3   b , i.e., the ADC which belongs to the same synchronization group, as the first ADC  3   a.    
         [0107]    As was explained above, the outputs of the OR-Gates  111   a ,  111   b ,  111   c  are provided to a second, third and fourth input of the above AND-Gate  110  of the respective ADC. 
         [0108]    As the output of the OR-Gate  111   a  depends on the state of its first input, the output of the AND-Gate  110  not only depends on the state of the first input of the AND-Gate  110 , i.e., whether or not a ready signal was provided by the digital part  7   a  of the first ADC  3   a , but also on the state of the second input of the AND-Gate  110 , i.e., whether or not a start signal ready 1   —   i  was provided from the second ADC  3   b.    
         [0109]    Hence, only then a ready signal is output at the output of the AND-Gate  110 , and sent via the line  120  to the digital part  7   a  of the first ADC  3   a  (triggering the sending of a “start” signal from the digital part  7   a  to the analog part  8   a ) if all digital parts of the ADCs of the same synchronization group as the first ADC  3   a  detect that their associated analog parts are ready for a new conversion. In other words, the triggering of the start of a (parallel) conversion is controlled and synchronized by a handshake mechanism between all ADCs of the same synchronization group. 
         [0110]    Preferably, the above values EVALR 0 , EVALR 1 , EVALR 2  stored in the synchronization register  6   a  of a respective ADC  3  a,  3   b  (see  FIG. 2 ) are only taken into account/written in the above registers  122   a ,  122   b ,  122   c  if a synchronized, parallel conversion is to be carried out/requested by a respective “master” ADC. Otherwise, if no synchronized, parallel conversion is to be carried out, the values of the variables EVALR 0 , EVALR 1 , EVALR 2  are to be ignored/not written in the above registers  122   a ,  122   b ,  122   c , such that a value “1” is present at the second inputs of all OR-Gates  111   a ,  111   b ,  111   c  of a respective ADC, which leads to a triggering of a conversion of the respective ADC regardless of the state of the analog parts of ADCs of the same synchronization group. 
         [0111]    Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.