Abstract:
A semiconductor device includes a first semiconductor layer of a first conductivity type formed on one side of a semiconductor substrate; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer; a third semiconductor layer of the first conductivity type formed on the second semiconductor layer; an opening part formed by removing part of the first to third semiconductor layers; a gate insulating film formed so as to cover an inner wall of the opening part; a gate electrode formed inside the opening part via the gate insulating film; a source electrode formed on a surface of the third semiconductor layer; a drain electrode connected to a part corresponding to the gate electrode on another side of the semiconductor substrate; and a fourth electrode formed on the another side of the semiconductor substrate at a part corresponding to the source electrode.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This patent application is based upon and claims the benefit of priority under 35 USC 120 and 365(c) of PCT application JP2010/069733 filed in Japan on Nov. 5, 2010, the entire contents of which are incorporated herein by reference. 
     
    
     FIELD 
       [0002]    The embodiments discussed herein are related to a semiconductor device and a manufacturing method of a semiconductor device. 
       BACKGROUND 
       [0003]    Nitride semiconductors such as GaN, AlN, and InN have a wide band gap and good material properties, and may therefore be used for high breakdown voltage electronic devices or short-wavelength light emitting devices. Particularly, as to field effect transistors (FET) to be used as high breakdown voltage electronic devices, studies are being made in regard to High Electron Mobility Transistors (HEMT), which may be used for high output/high efficiency amplifiers and high power switching devices. 
         [0004]    Incidentally, in a conventional HEMT having a horizontal structure (a structure in which the current flows substantially parallel to the substrate surface), when a sufficient amount of breakdown voltage is to be secured for use in high power/high breakdown voltage switching devices, a long inter-electrode length is to be formed. In this case, the chip size of the device to be formed is increased, and the number of chips that may be manufactured from one wafer is decreased, which leads to an increase in the manufacturing cost, resulting in high cost. 
         [0005]    Therefore, in high power/high breakdown voltage switching devices, a field effect transistor having a vertical structure (a structure in which the current flows substantially perpendicular to the substrate surface) is garnering attention, because the chip size may be decreased with such a structure.
   Patent document 1: Japanese Laid-Open Patent Publication No. 2002-359256   Patent document 2: Japanese Laid-Open Patent Publication No. 2008-53448   Non-patent document 1: Applied Physics Express 1 (2008) 011105   Non-patent document 2: Applied Physics Express 1 (2008) 021104   
 
         [0010]    For example, a field effect transistor having a vertical structure has a source electrode formed on one side of a substrate and a drain electrode formed on the other side of the substrate. Specifically, a description is given of a field effect transistor having a vertical structure, with reference to  FIG. 1 . 
         [0011]    In the field effect transistor having a vertical structure, on a substrate  611  constituted by n + -SiC or n + -GaN, a n-GaN layer  612 , a p-GaN layer  613 , and a n-GaN layer  614  are formed. On part of the surface of the n-GaN layer  614 , a source electrode  621  is formed. Furthermore, an opening part is formed by etching part of the n-GaN layer  614 , the p-GaN layer  613 , and the GaN layer  612  from the surface of the n-GaN layer  614 . An insulating film  615  is formed so as to cover the surface of the n-GaN layer  614  and the surface of the inside of the opening part. Furthermore, in the opening part, a gate electrode  622  is formed via the insulating film  615 . On the back side of the substrate  611 , i.e., on the side opposite to the side on which the semiconductor layer is formed, a drain electrode  623  is formed. 
         [0012]    In a field effect transistor having the above structure, when a voltage is applied between the source electrode  621  and the drain electrode  623 , regardless of the potential of the gate electrode  622 , a leakage current passing the p-GaN layer  613  is generated. That is to say, in an area other than the area that is the current path indicated by a dashed-line arrow A, a leakage current flowing through the p-GaN layer  613  indicated by a dashed-line arrow B is generated. When such a leakage current is generated, properties of the field effect transistor are degraded. 
         [0013]    Thus, there is demand for a semiconductor device and a manufacturing method of a semiconductor device having a high insulation breakdown voltage, a small chip size, and a small amount of leakage current. 
       SUMMARY 
       [0014]    According to an aspect of the embodiments, a semiconductor device includes a first semiconductor layer of a first conductivity type formed on one side of a semiconductor substrate having conductivity; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer; a third semiconductor layer of the first conductivity type formed on the second semiconductor layer; an opening part formed by removing part of the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer; a gate insulating film formed so as to cover an inner wall of the opening part; a gate electrode formed inside the opening part via the gate insulating film; a source electrode formed on a surface of the third semiconductor layer; a drain electrode connected to a part corresponding to the gate electrode on another side of the semiconductor substrate; and a fourth electrode formed on the another side of the semiconductor substrate at a part corresponding to the source electrode. 
         [0015]    The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention as claimed. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]      FIG. 1  is a structural diagram of a field effect transistor having a vertical structure; 
           [0017]      FIG. 2  is a structural diagram of a semiconductor device according to a first embodiment; 
           [0018]      FIGS. 3A through 3C  are manufacturing procedure diagrams of a semiconductor device according to a first embodiment (1); 
           [0019]      FIGS. 4A through 4C  are manufacturing procedure diagrams of a semiconductor device according to the first embodiment (2); 
           [0020]      FIGS. 5A and 5B  are manufacturing procedure diagrams of a semiconductor device according to the first embodiment (3); 
           [0021]      FIGS. 6A through 6C  are manufacturing procedure diagrams of a semiconductor device according to a second embodiment (1); 
           [0022]      FIGS. 7A through 7C  are manufacturing procedure diagrams of a semiconductor device according to the second embodiment (2); 
           [0023]      FIGS. 8A and 8B  are manufacturing procedure diagrams of a semiconductor device according to the second embodiment (3); 
           [0024]      FIGS. 9A through 9C  are manufacturing procedure diagrams of a semiconductor device according to a third embodiment (1); 
           [0025]      FIGS. 10A through 10C  are manufacturing procedure diagrams of a semiconductor device according to the third embodiment (2); 
           [0026]      FIGS. 11A through 11C  are manufacturing procedure diagrams of a semiconductor device according to the third embodiment (3); 
           [0027]      FIGS. 12A through 12C  are manufacturing procedure diagrams of a semiconductor device according to a fourth embodiment (1); 
           [0028]      FIGS. 13A through 13C  are manufacturing procedure diagrams of a semiconductor device according to the fourth embodiment (2); 
           [0029]      FIG. 14  is a manufacturing procedure diagram of a semiconductor device according to the fourth embodiment (3); 
           [0030]      FIGS. 15A through 15C  are manufacturing procedure diagrams of a semiconductor device according to a fifth embodiment (1); 
           [0031]      FIGS. 16A through 16C  are manufacturing procedure diagrams of a semiconductor device according to the fifth embodiment (2); and 
           [0032]      FIGS. 17A and 17B  are manufacturing procedure diagrams of a semiconductor device according to the fifth embodiment (3). 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0033]    Embodiments of the present invention will be explained with reference to accompanying drawings. The same elements are denoted by the same reference numerals and overlapping descriptions are omitted. 
       First Embodiment 
     Semiconductor Device 
       [0034]    A description is given of a semiconductor device according to the present embodiment. As illustrated in  FIG. 2 , a semiconductor device according to the present embodiment is a field effect transistor having a vertical structure. Specifically, on a substrate  11  constituted by n + -SiC or n + -GaN, a n-GaN layer  12 , a p-GaN layer  13 , and a n-GaN layer  14  are formed. On part of the surface of the n-GaN layer  14 , a source electrode  21  is formed. Furthermore, an opening part is formed by etching part of the p-GaN layer  13  and the n-GaN layer  12  from the surface of the n-GaN layer  14 . A gate insulating film  15  is formed so as to cover the surface of the n-GaN layer  14  and the surface of the inside of the opening part. In the opening part, a gate electrode  22  is formed via the gate insulating film  15 . 
         [0035]    On the back side of the substrate  11 , i.e., on the side opposite to the side on which the semiconductor layer is formed, a drain electrode  23  is formed in a part corresponding to the area where the gate electrode  22  is formed and an area surrounding the gate electrode  22 . Furthermore, in a part corresponding to an area other than where the drain electrode  23 , and the area where the source electrode  21  is formed and areas surrounding the source electrode  21 , a fourth electrode  31  is formed via an insulating film  32  which acts as a back side insulating film. Between the drain electrode  23  and the fourth electrode  31 , insulation properties are maintained by the insulating film  32 . 
         [0036]    In the semiconductor device according to the present embodiment, a potential, which is substantially the same as the potential applied to the source electrode  21  or the gate electrode  22 , is applied to the fourth electrode  31 . Accordingly, when a potential that causes an on state is applied to the gate electrode  22 , a current flows through the p-GaN layer  13  near the gate electrode  22  via the gate insulating film  15 , as indicated by a dashed-line arrow C. However, a leakage current hardly flows in the p-GaN layer  13  in areas outside the above area. 
         [0037]    When the same potential as that of the source electrode  21  is applied to the fourth electrode  31 , and a potential that causes an on state is applied to the gate electrode  22 , a current flows from the source electrode  21  to the drain electrode  23  in the p-GaN layer  13  near the gate electrode  22  via the gate insulating film  15 . However, the fourth electrode  31  and the source electrode  21  have the same potential, and the insulating film  32  is formed, and therefore a current does not flow from the source electrode  21  to the fourth electrode  31 . 
         [0038]    Therefore, when a potential, which turns off the current flowing between the source electrode  21  and the drain electrode  23 , is applied to the gate electrode  22 , in this case also, a current hardly flows between the source electrode  21  and the drain electrode  23 . That is to say, in the semiconductor device according to the present embodiment, in the on state, as indicated by a dashed-line arrow C, a current flows in an area of the p-GaN layer  13  via the gate insulating film  15  near the gate electrode  22 , but a current does not flow in areas other than this area. Therefore, the leakage current is significantly decreased in the off state, and therefore device properties are improved. 
         [0039]    Furthermore, the same applies to a case where the potential applied to the fourth electrode  31  is substantially the same as the potential applied to the gate electrode  22 . In this case also, as indicated by the dashed-line arrow C, it is possible to make a current flow only to the p-GaN layer  13  near the gate electrode  22 . Accordingly, it is possible to decrease the leakage current. If the potential applied to the fourth electrode  31  is less than or equal to the potential applied to the drain electrode  23  and greater than or equal to the potential applied to the source electrode  21  or the gate electrode  22 , the same effects are achieved. 
       Manufacturing Method of Semiconductor Device 
       [0040]    Next, a description is given of a manufacturing method of a semiconductor device according to the present embodiment, with reference to  FIGS. 3A through 5B . 
         [0041]    First, as illustrated in  FIG. 3A , on the substrate  11  made of n + -SiC, by a MOVPE (Metal-Organic Vapor Phase Epitaxy) method, a buffer layer (not illustrated) is formed. On this buffer layer, the n-GaN layer  12 , the p-GaN layer  13 , and the n-GaN layer  14  are laminated. 
         [0042]    The n-GaN layer  12  is formed to have a thickness of 1 μm through 10 μm, and 1×10 17  cm −3  through 1×10 20  cm −3  of Si is doped as an impurity element. The p-GaN layer  13  is formed to have a thickness of 10 nm through 1 μm, and approximately 1×10 19  cm −3  of Mg is doped as an impurity element. The n-GaN layer  14  is formed to have a thickness of 10 nm through 1 μm, and 1×10 17  cm −3  through 1×10 2 ° cm −3  of Si is doped as an impurity element. 
         [0043]    Next, as illustrated in  FIG. 3B , an opening part  41  is formed in an area where the gate electrode  22  is formed as described below. Specifically, photoresist is applied on the n-GaN layer  14 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where the opening part  41  is to be formed. Subsequently, dry etching such as RIE (Reactive Ion Etching) is performed with the use of gas including chlorine, to remove part of the n-GaN layer  14 , the p-GaN layer  13 , and the n-GaN layer  12 , and form the opening part  41 . 
         [0044]    Next, as illustrated in  FIG. 3C , the gate insulating film  15  is formed inside the opening part  41  and on the surface of the n-GaN layer  14 , and the gate electrode  22  is formed inside the opening part  41  via the gate insulating film  15 . Specifically, by plasma CVD (Chemical Vapor Deposition), the gate insulating film  15  made of SiN is formed to have a thickness of 1 nm through 1 μm, inside the opening part  41  and on the surface of the n-GaN layer  14 . Subsequently, photoresist is applied on the surface of the gate insulating film  15 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where the gate electrode  22  is to be formed. Furthermore, subsequently, a metal film made of Ni is formed by vacuum vapor deposition, and by dipping this in an organic solvent, the metal film formed on the resist pattern is removed together with the resist pattern by being lifted off. Accordingly, the gate electrode  22  is formed in the opening part  41  via the gate insulating film  15 . 
         [0045]    Next, as illustrated in  FIG. 4A , the source electrode  21  is formed. Specifically, photoresist is applied on the surface of the gate insulating film  15 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where the source electrode  21  is to be formed. Subsequently, dry etching such as RIE is performed by using gas including fluorine, to remove the gate insulating film  15  so that the surface of the n-GaN layer  14  is exposed. Furthermore, subsequently, a metal film made of Ti/Au is formed by vacuum vapor deposition, and by dipping this in an organic solvent, the metal film formed on the resist pattern is removed together with the resist pattern by being lifted off. Accordingly, the source electrode  21  is formed on the n-GaN layer  14 , and subsequently, ohmic contact is realized by performing a heat treatment in a nitrogen atmosphere. 
         [0046]    Next, as illustrated in  FIG. 4B , on the back side of the substrate  11 , the drain electrode  23  is formed at a part corresponding to the area where the gate electrode  22  is formed. Specifically, photoresist is applied on the back side of the substrate  11 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening at the part where the drain electrode  23  is to be formed. Subsequently, a metal laminated film including Au is formed by vacuum vapor deposition, and by dipping this in an organic solvent, the metal laminated film formed on the resist pattern is removed together with the resist pattern by being lifted off. Accordingly, on the back side of the substrate  11 , the drain electrode  23  is formed at a part corresponding to the area where the gate electrode  22  is formed. At this time, the drain electrode  23  is not formed at the part corresponding to the area where the source electrode  21  is formed. 
         [0047]    Next, as illustrated in  FIG. 4C , the insulating film  32  is formed on the back side of the substrate  11  and on the drain electrode  23 . Specifically, on the back side of the substrate  11  and on the drain electrode  23 , the insulating film  32  made of SiN is formed to have a thickness of 10 nm through 10 μm by plasma CVD. 
         [0048]    Next, as illustrated in  FIG. 5A , the fourth electrode  31  is formed in an area on the insulating film  32  where the drain electrode  23  is not formed. Specifically, photoresist is applied on the surface of the insulating film  32 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where the fourth electrode  31  is to be formed. Subsequently, a metal laminated film made of Au is formed by vacuum vapor deposition, and by dipping this in an organic solvent, the metal laminated film formed on the resist pattern is removed together with the resist pattern by being lifted off. Accordingly, the fourth electrode  31  is formed on the insulating film  32 , at a part corresponding to the area where the drain electrode  23  is not formed and the area where the source electrode  21  is formed. 
         [0049]    Next, as illustrated in  FIG. 5B , the insulating film  42  is formed in an area including the fourth electrode  31 , and then by removing part of the insulating films  32  and  42  in the area where the drain electrode  23  is formed, an opening part  43  is formed. Specifically, in an area including the fourth electrode  31 , the insulating film  42  made of SiN is formed by plasma CVD. Subsequently, photoresist is applied on the insulating film  42 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where the opening part  43  is to be formed. Furthermore, subsequently, dry etching such as RIE is performed by using gas including fluorine to remove part of the insulating films  32  and  42 , so that the surface of the drain electrode  23  is exposed. 
         [0050]    As described above, the semiconductor device according to the present embodiment is manufactured. The semiconductor device according to the present embodiment has a structure in which the source electrode  21  and the fourth electrode  31  are electrically connected by a via hole (not illustrated) provided in the substrate  11 . However, as another structure of the semiconductor device according to the present embodiment, the gate electrode  22  may be electrically connected to the fourth electrode  31  by a via hole (not illustrated) provided in the substrate  11 . 
       Second Embodiment 
       [0051]    Next, a description is given of a manufacturing method of a semiconductor device according to a second embodiment, with reference to  FIGS. 6A through 8B . 
         [0052]    First, as illustrated in  FIG. 6A , on the substrate  11  made of n + -SiC, by a MOVPE (Metal-Organic Vapor Phase Epitaxy) method, a buffer layer (not illustrated) is formed. On this buffer layer, the n-GaN layer  12 , the p-GaN layer  13 , and the n-GaN layer  14  are laminated. 
         [0053]    Next, as illustrated in  FIG. 6B , an opening part  41  is formed in an area where the gate electrode  22  is formed as described below. 
         [0054]    Next, as illustrated in  FIG. 6C , the gate insulating film  15  is formed inside the opening part  41  and on the surface of the n-GaN layer  14 , and the gate electrode  22  is formed inside the opening part  41  via the gate insulating film  15 . 
         [0055]    Next, as illustrated in  FIG. 7A , the source electrode  21  is formed. 
         [0056]    Next, as illustrated in  FIG. 7B , on the back side of the substrate  11 , an insulating film  132  to act as a back side insulating film is formed. Specifically, the insulating film  132  made of SiN formed to have a thickness of 10 nm through 10 μm is formed on the back side of the substrate  11  by plasma CVD. 
         [0057]    Next, as illustrated in  FIG. 7C , a fourth electrode  133  is formed on the insulating film  132  in areas other than the part corresponding to the area where the gate electrode  22  is formed. Specifically, photoresist is applied on the insulating film  132 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening at the part where the fourth electrode  133  is to be formed. Subsequently, a metal laminated film including Au is formed by vacuum vapor deposition, and by dipping this in an organic solvent, the metal laminated film formed on the resist pattern is removed together with the resist pattern by being lifted off. Accordingly, the fourth electrode  133  is formed on the insulating film  132  in areas other than the part corresponding to the area where the gate electrode  22  is formed, and at a part corresponding to the area where the source electrode  21  is formed. 
         [0058]    Next, as illustrated in  FIG. 8A , an insulating film  142  is formed on the fourth electrode  133  and the insulating film  132 , and furthermore, the insulating film  132  and the insulating film  142  are removed at parts corresponding to the area where the gate electrode  22  is formed, to form an opening part  143 . Specifically, the insulating film  142  made of SiN is formed on the fourth electrode  133  and the insulating film  132  by plasma CVD. Subsequently, photoresist is applied on the surface of the insulating film  142 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where the opening part  143  is to be formed. Furthermore, subsequently, dry etching such as RIE is performed by using gas including fluorine, to remove the insulating film  132  and the insulating film  142  in the area where the resist pattern is not formed, so that part of the back side of the substrate  11  is exposed and the opening part  143  is formed. 
         [0059]    Next, as illustrated in  FIG. 8B , a metal laminated film including Au is formed on the insulating film  142  and the exposed back side of the substrate  11 , to form a drain electrode  144 . This drain electrode  144  is connected with the substrate  11  whose back side is exposed at the opening part  143 . 
         [0060]    As described above, the semiconductor device according to the present embodiment is manufactured. The semiconductor device according to the present embodiment has a structure in which the source electrode  21  and the fourth electrode  133  are electrically connected by a via hole (not illustrated) provided in the substrate  11 . However, as another structure of the semiconductor device according to the present embodiment, the gate electrode  22  may be electrically connected to the fourth electrode  133  by a via hole (not illustrated) provided in the substrate  11 . 
         [0061]    Contents other than the above are the same as the first embodiment. 
       Third Embodiment 
       [0062]    Next, a description is given of a manufacturing method of a semiconductor device according to a third embodiment, with reference to  FIGS. 9A through 11C . 
         [0063]    First, as illustrated in  FIG. 9A , on the substrate  11  made of n + -SiC, by a MOVPE (Metal-Organic Vapor Phase Epitaxy) method, a buffer layer (not illustrated) is formed. On this buffer layer, the n-GaN layer  12 , the p-GaN layer  13 , and the n-GaN layer  14  are laminated. 
         [0064]    Next, as illustrated in  FIG. 9B , an opening part  41  is formed in an area where the gate electrode  22  is formed as described below. 
         [0065]    Next, as illustrated in  FIG. 9C , the gate insulating film  15  is formed inside the opening part  41  and on the surface of the n-GaN layer  14 , and the gate electrode  22  is formed inside the opening part  41  via the gate insulating film  15 . 
         [0066]    Next, as illustrated in  FIG. 10A , the source electrode  21  is formed. 
         [0067]    Next, as illustrated in  FIG. 10B , on the back side of the substrate  11 , part of the area excluding the part corresponding to the area where the gate electrode  22  is formed is removed by dry etching or ion milling, so that the n-GaN layer  12  is exposed and a back side removal area  230  is formed. Specifically, photoresist is applied on the back side of the substrate  11 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where the back side of the substrate  11  is to be removed. Subsequently, part of the substrate  11  and the n-GaN layer  12  in the area where the resist pattern is not formed is removed by dry etching, so that the n-GaN layer  12  is exposed and the back side removal area  230  is formed. The back side removal area  230  is formed on the back side of the substrate  11  at a part corresponding to an area where the source electrode  21  is formed. 
         [0068]    Next, as illustrated in  FIG. 10C , on the back side of the substrate  11  and the back side removal area  230  where the n-GaN layer  12  is exposed, an insulating film  232  to act as a back side insulating film is formed. Specifically, the insulating film  232  made of SiN formed to have a thickness of 10 nm through 10 μm is formed by plasma CVD. 
         [0069]    Next, as illustrated in  FIG. 11A , a fourth electrode  233  is formed on the insulating film  232  formed on the back side removal area  230 . Specifically, photoresist is applied on the insulating film  232 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening at the part where the fourth electrode  233  is to be formed. Subsequently, a metal laminated film including Au is formed by vacuum vapor deposition, and by dipping this in an organic solvent, the metal laminated film formed on the resist pattern is removed together with the resist pattern by being lifted off. Accordingly, the fourth electrode  233  is formed on the insulating film  232  formed on the back side removal area  230 . The fourth electrode  233  formed as described above is formed at a part corresponding to the area where the source electrode  21  is formed. 
         [0070]    Next, as illustrated in  FIG. 11B , an insulating film  242  is formed on the fourth electrode  233  and the insulating film  232 , and furthermore, the insulating film  232  and the insulating film  242  are removed at a part corresponding to the area where the gate electrode  22  is formed, to form an opening part  243 . Specifically, the insulating film  242  made of SiN is formed on the fourth electrode  233  and the insulating film  232  by plasma CVD. Subsequently, photoresist is applied on the insulating film  242 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where the opening part  243  is to be formed. Furthermore, subsequently, dry etching such as RIE is performed by using gas including fluorine, to remove the insulating film  232  and the insulating film  242  in the area where the resist pattern is not formed, so that part of the back side of the substrate  11  is exposed and the opening part  243  is formed. 
         [0071]    Next, as illustrated in  FIG. 11C , a drain electrode  244  to be connected to the opening part  243  where the back side of the substrate  11  is exposed, is formed. Specifically, photoresist is applied on the surface of the insulating film  242 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where the drain electrode  244  is to be formed. Subsequently, a metal laminated film including Au is formed by vacuum vapor deposition, and by dipping this in an organic solvent, the metal laminated film formed on the resist pattern is removed together with the resist pattern by being lifted off. Accordingly, the drain electrode  244  is formed, which is connected to the opening part  243  where the back side of the substrate  11  is exposed. 
         [0072]    As described above, the semiconductor device according to the present embodiment is manufactured. The semiconductor device according to the present embodiment has a structure in which the source electrode  21  and the fourth electrode  233  are electrically connected by a via hole (not illustrated) provided in the substrate  11 . However, as another structure of the semiconductor device according to the present embodiment, the gate electrode  22  may be electrically connected to the fourth electrode  233  by a via hole (not illustrated) provided in the substrate  11 . 
         [0073]    Contents other than the above are the same as the first embodiment. 
       Fourth Embodiment 
       [0074]    Next, a description is given of a manufacturing method of a semiconductor device according to a fourth embodiment, with reference to  FIGS. 12A through 14 . 
         [0075]    First, as illustrated in  FIG. 12A , on the substrate  11  made of n + -SiC, by a MOVPE (Metal-Organic Vapor Phase Epitaxy) method, a buffer layer (not illustrated) is formed. On this buffer layer, the n-GaN layer  12 , the p-GaN layer  13 , and the n-GaN layer  14  are laminated. 
         [0076]    Next, as illustrated in  FIG. 12B , an opening part  41  is formed in an area where the gate electrode  22  is formed as described below. 
         [0077]    Next, as illustrated in  FIG. 12C , the gate insulating film  15  is formed inside the opening part  41  and on the surface of the n-GaN layer  14 , and the gate electrode  22  is formed inside the opening part  41  via the gate insulating film  15 . 
         [0078]    Next, as illustrated in  FIG. 13A , the source electrode  21  is formed. Specifically, photoresist is applied on the surface of the gate insulating film  15 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where the source electrode  21  is to be formed. 
         [0079]    Next, as illustrated in  FIG. 13B , on the back side of the substrate  11 , the drain electrode  23  is formed at a part corresponding to the area where the gate electrode  22  is formed. The drain electrode  23  is not formed at a part corresponding to an area where the source electrode  21  is formed. 
         [0080]    Next, as illustrated in  FIG. 13C , the insulating film  32  is formed on the back side of the substrate  11  and on the drain electrode  23 . Specifically, on the back side of the substrate  11  and on the drain electrode  23 , the insulating film  32  made of SiN is formed to have a thickness of 10 nm through 10 μm by plasma CVD. 
         [0081]    Next, as illustrated in  FIG. 14 , an opening part  343  is formed by removing part of the insulating film  32  in the area where the drain electrode  23  is formed. Specifically, photoresist is applied on the insulating film  32 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where the opening part  343  is to be formed. Furthermore, subsequently, dry etching such as RIE is performed by using gas including fluorine to remove the insulating film  32  in an area where the resist pattern is not formed, so that part of the surface of the drain electrode  23  is exposed. 
         [0082]    As described above, the semiconductor device according to the present embodiment is manufactured. In the semiconductor device according to the present embodiment, the drain electrode  23  is formed on the back side of the substrate  11  at a part corresponding to the area where the gate electrode  22  is formed, and is not formed at a part corresponding to the area where the source electrode  21  is formed. Therefore, it is possible to decrease the leakage current flowing between the source and the drain without providing a fourth electrode. 
         [0083]    Contents other than the above are the same as the first embodiment. 
       Fifth Embodiment 
       [0084]    Next, a description is given of a manufacturing method of a semiconductor device according to a fifth embodiment, with reference to  FIGS. 15A through 17B . 
         [0085]    First, as illustrated in  FIG. 15A , on the substrate  11  made of n + -SiC, by a MOVPE (Metal-Organic Vapor Phase Epitaxy) method, a buffer layer (not illustrated) is formed. On this buffer layer, the n-GaN layer  12 , the p-GaN layer  13 , and the n-GaN layer  14  are laminated. 
         [0086]    Next, as illustrated in  FIG. 15B , an opening part  41  is formed in an area where the gate electrode  22  is formed as described below. 
         [0087]    Next, as illustrated in  FIG. 15C , the gate insulating film  15  is formed inside the opening part  41  and on the surface of the n-GaN layer  14 , and the gate electrode  22  is formed inside the opening part  41  via the gate insulating film  15 . 
         [0088]    Next, as illustrated in  FIG. 16A , the source electrode  21  is formed. 
         [0089]    Next, as illustrated in  FIG. 16B , on the back side of the substrate  11 , part of the area excluding the part corresponding to the area where the gate electrode  22  is formed is removed by dry etching or ion milling, so that the n-GaN layer  12  is exposed and a back side removal area  230  is formed. Specifically, photoresist is applied on the back side of the substrate  11 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where the back side of the substrate  11  is to be removed. Subsequently, part of the substrate  11  and the n-GaN layer  12  in the area where the resist pattern is not formed is removed by dry etching, so that the back side removal area  230  is formed. The back side removal area  230  is formed at a part corresponding to an area where the source electrode  21  is formed. 
         [0090]    Next, as illustrated in  FIG. 16C , on the back side of the substrate  11  and the back side removal area  230  where the n-GaN layer  12  is exposed, an insulating film  232  is formed. Specifically, the insulating film  232  made of SiN formed to have a thickness of 10 nm through 10 μm is formed by plasma CVD. 
         [0091]    Next, as illustrated in  FIG. 17A , by removing the insulating film  232  at a part corresponding to the area where the gate electrode  22  is formed, an opening part  443  is formed. Specifically, photoresist is applied on the insulating film  232 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where the opening part  443  is to be formed. Furthermore, subsequently, dry etching such as RIE is performed by using gas including fluorine to remove the insulating film  232  in the area where the resist pattern is not formed, so that the back side of the substrate  11  is exposed and the opening part  443  is formed. 
         [0092]    Next, as illustrated in  FIG. 17B , a drain electrode  444  is formed, which is to be connected at the opening part  443  where the back side of the substrate  11  is exposed. Specifically, photoresist is applied on the surface of the insulating film  232 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where the drain electrode  444  is to be formed. Subsequently, a metal laminated film including Au is formed by vacuum vapor deposition, and by dipping this in an organic solvent, the metal laminated film formed on the resist pattern is removed together with the resist pattern by being lifted off. Accordingly, the drain electrode  444  is formed. The drain electrode  444  is connected to the back side of the substrate  11 , at the opening part  443  where the back side of the substrate  11  is exposed. 
         [0093]    As described above, the semiconductor device according to the present embodiment is manufactured. In the semiconductor device according to the present embodiment, the drain electrode  444  is formed on the back side of the substrate  11  at a part corresponding to the area where the gate electrode  22  is formed, and is not formed at a part corresponding to the area where the source electrode  21  is formed. Therefore, it is possible to decrease the leakage current flowing between the source and the drain without providing a fourth electrode. 
         [0094]    Contents other than the above are the same as the third embodiment. 
         [0095]    According to an aspect of the embodiments, a semiconductor device and a manufacturing method of a semiconductor device are provided, in which the insulation breakdown voltage is high, the chip size is small, and the amount of leakage current is small. 
         [0096]    The present invention is not limited to the specific embodiments described herein, and variations and modifications may be made without departing from the scope of the present invention. 
         [0097]    All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.