Abstract:
A synchronous semiconductor memory device having multiple memory banks allows one memory bank to begin executing a data operation (e.g., reading data from a memory cell) while another memory bank is executing another data operation (e.g., writing data to a memory cell). The synchronous semiconductor memory device includes a write data path through which an input data signal is transmitted to the memory cell of a memory bank executing a write operation, and a read data path through which an output data signal is transmitted from the memory cell of a memory bank executing a read operation to an input/output pin. The read and write data paths are each connected to the memory banks via a common input/output line. The operation of the memory banks and the write and read data paths are synchronized, such that once a first memory bank begins executing either the write or read operation, a second memory bank may begin executing the other type of data operation after a predetermined time delay has elapsed, while the first memory bank is still executing its data operation.

Description:
RELATED APPLICATION  
         [0001]    This application claims the benefit under 35 U.S.C. § 119(a) of Korean Patent Application No. 2001-0073737, filed on Nov. 26, 2001, the contents of which are hereby incorporated by reference in their entirety.  
         BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates to a synchronous semiconductor memory device having a multi-bank arrangement, and more particularly, to a synchronous semiconductor memory device having multiple memory banks that perform at least part of their respective data operations at the same time.  
           [0004]    2. Description of the Related Art  
           [0005]    To realize high-speed and highly integrated memory devices, a multi-memory bank that is composed of a plurality of memory banks is generally used. Each of the plurality of memory banks comprises a plurality of blocks arranged as a plurality of cell arrays in the column and row directions.  
           [0006]    Conventional synchronous semiconductor memory devices having a multi-bank arrangement include a plurality of memory banks that are made up of a plurality of memory cells. Here, each memory bank is activated at a predetermined interval to execute a write operation and a read operation sequentially on a memory bank within the respective memory bank. For instance, after a first memory bank completes the write operation, a second memory bank starts executing the read operation.  
           [0007]    [0007]FIG. 1 is a timing diagram of the write and read operations of a conventional synchronous semiconductor memory device having multi-bank scheme. Referring to FIG. 1, a write command WR is generated in synchronization with a first clock signal CLK 1 , and then applied to the synchronous semiconductor memory device. Also, a read command RD is generated in synchronization with a sixth clock signal CLK 6 , and then is applied to the synchronous semiconductor memory device.  
           [0008]    Further, an input data signal DIN, the burst length of which includes four data packets, is fetched by a data strobe signal DQS. Then, the fetched input data is written to a memory cell included in a first memory bank of the synchronous semiconductor memory device in response to a write column selection signal WR_CSL.  
           [0009]    After a fifth period of the clock signal CLK has passed, a read command RD is generated in synchronization with a sixth clock signal CLK 6 , and then, an output data signal (not shown) is read from a memory cell included in a second memory bank of the synchronous semiconductor memory device in response to a read column selection signal RD_CSL. That is, the read operation of the second memory bank starts after the write operation of the first memory bank.  
           [0010]    In a conventional synchronous semiconductor memory device having multi-bank scheme, no read command RD is given until five cycles of the clock signal CLK passes after a write command WR is applied to the synchronous semiconductor memory device. That is, a predetermined time delay occurs after the write operation is performed before the read operation begins. During such a time delay, the data bus line of the synchronous semiconductor memory device is in an idle state, and thus, an input/output data signal is not transferred at this time. For this reason, the performance of the synchronous semiconductor memory device may be inefficient.  
           [0011]    A suggested solution to this problem is to generate the read command RD in synchronization with a third clock signal CLK 3 , rather than the sixth clock signal CLK 6 . However, in this case, a write column selection signal WR_CSL and a read column selection signal RD_CSL are activated at the same time, which would cause malfunction of the synchronous semiconductor memory device.  
           [0012]    [0012]FIG. 2 is a timing diagram of a conventional synchronous semiconductor memory device having multi-bank scheme in which an error occurs. Referring to FIG. 2, a second write command WR2 is applied to a first memory bank in response to a third clock signal CLK, during which a second write column selection signal WR 2 -CSL and a read column selection signal RD_CSL are activated at the same time, thus causing the malfunction of the synchronous semiconductor memory device as indicated by CASE1.  
         SUMMARY OF THE INVENTION  
         [0013]    The present invention is directed to a synchronous semiconductor memory device including multiple memory banks, in which one of memory bank is capable of writing data while another memory bank reads data. The synchronous semiconductor memory device includes a write data path and a read data path, which share a common data bus line (input/output line) used for accessing the multiple memory banks.  
           [0014]    The operation of the memory banks and the write and read data paths are synchronized by signals, which are generated by a synchronization device in the synchronous semiconductor memory device. These signals include data path activation signals for activating the write and read data path, respectively. The synchronization device also generates a write bank selection signal and a read bank selection signal. The write bank selection signal selects the memory bank for performing the write data operation in conjunction with the activated write data path, while the read bank selection signal selects the memory bank for performing the read data operation in conjunction with the activated read data path.  
           [0015]    In one embodiment of the present invention, a first memory bank starts performing either the write or read data operation in response to the synchronization signals. Then, the synchronization signals cause a second memory bank to begin executing the other type of data operation after a predetermined time delay elapses after the first memory bank started performing its data operation. For example, after one memory bank begins writing data, a predetermined time delay (e.g., three clock cycles) elapses, and another memory bank begins reading data from memory cells, even though the former memory bank is still writing data.  
           [0016]    Accordingly, the present invention helps reduce the amount of time that a data bus line (input/output line) is idle when two memory banks need to perform a write and read operation, respectively, thereby allowing the synchronous semiconductor memory device to perform more efficiently. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]    The above objective and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:  
         [0018]    [0018]FIG. 1 is a timing diagram of write and read operations of a conventional synchronous semiconductor memory device having a multi-bank arrangement.  
         [0019]    [0019]FIG. 2 is a timing diagram of a conventional synchronous semiconductor memory device having a multi-bank arrangement illustrating the occurrence of an error.  
         [0020]    [0020]FIG. 3 is a block diagram of a synchronous semiconductor memory device having a multi-bank arrangement according to an exemplary embodiment of the present invention.  
         [0021]    [0021]FIG. 4 is a timing diagram of the operation of the synchronous semiconductor memory device of FIG. 3. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0022]    [0022]FIG. 3 is a block diagram of a synchronous semiconductor memory device  300  having a multi-bank arrangement according to a preferred embodiment of the present invention. Referring to FIG. 3, the synchronous semiconductor memory device  300  includes an address register  305 , a row decoder  310 , a plurality of memory banks  315 , a bit-line sense amplifier  320 , a column decoder  325 , an input/output line driver  330 , an input data multiplexer  335 , an input buffer  340 , an input/output pin DQ  345 , an input/output multiplexer  350 , an input/output line sense amplifier  355 , an output data multiplexer  360 , an output buffer  365 , and a timing device  370 . A plurality of memory banks  315  share a write data path WP and a read data path RP via the bit-line sense amplifier  320 . Hereinafter, the operations of the synchronous semiconductor memory device  300  will now be described on the assumption that a first memory bank executes the write operation and a second memory bank executes the read operation.  
         [0023]    The write data path WP includes the input/output line driver  330 , the input data multiplexer  335 , and the input buffer  340 . The read data path RP includes the input/output multiplexer  350 , the input/output line sense amplifier  355 , the output data multiplexer  360 , and the output buffer  365 . The write data path WP and the read data path RP share the first and second input/output lines IO 1  and IO 2 .  
         [0024]    The timing device  370  generates data path activation signals based on control signals, which are related to the operation of the synchronous semiconductor memory device  300 . The timing device also controls the timing of certain control signals to synchronize the read and write operations, thus generating a write master signal WM, a read master signal RM, a row address strobe signal RASB, a column address strobe signal CASB, and a clock enable signal CKE.  
         [0025]    The above operational signals related to the operation of the synchronous semiconductor memory device  300  may be a clock signal CLK, a clock enable signal CKE, a chip selection signal CSB, the row address strobe signal RASB, the column address strobe signal CASB, a write enable signal WEB and an input data mask signal DM. Here, the clock enable signal CKE is a control signal that activates the clock signal CLK. The chip selection signal CSB is a signal that activates or deactivates the operation of the synchronous semiconductor memory device  300 . The write enable signal WEB is a control signal that activates the write operation of the synchronous semiconductor memory device  300 . The input data mask signal DM is a signal that blocks the input data signal DIN. The row address strobe signal RASB is a signal informing the application of a row address signal RA. The column address strobe signal CASB is a signal informing of the application of the column address signal CA. The timing device  370  controls the timing at which the control signals CKE, RASB, and CASB are sent to other components of the of the synchronous memory device  300 .  
         [0026]    The write master signal WM is a data path activation signal that activates the write data path WP, and controls the input/output line driver  330  and the input data multiplexer  335 . Also, the read master signal RM is a data path activation signal that activates the read data path RP, and controls the input/output multiplexer  350  and the input/output line sense amplifier  335 . By generating the write master signal WM and the read master signal RM to activate the write data path WP and read data path RP, respectively, the timing device  370  can be referred to as a data path activation device.  
         [0027]    Each of the plurality of memory banks  315  includes a plurality memory cells, and the memory cells store data therein.  
         [0028]    The address register  305  generates a write bank selection signal WBA, a read bank selection signal RBA, a row address signal RA and a column address signal CA in response to an address signal ADDR in synchronization with the clock signal CLK. The write bank selection signal WBA is a signal for selecting the first memory bank that executes the write operation, and the read bank selection signal RBA is a signal selecting the second memory bank that executes the read operation. Also, the row address signal RA and the column address signal CA are signals that select the memory cells of the first memory bank and the second memory bank, respectively. The clock enable signal CKE is applied to activate the clock signal CLK for the address register  305 .  
         [0029]    The timing device (data path activation device)  370  and the address register  305  each generate signals for synchronizing the operation of the write data path WP, read data path RP, and the first and second memory banks, such that a read data operation is performed by the second memory bank while at least part of a write data operation is being performed by the first. Therefore, the timing device  370  and the address register  305  collectively form a synchronization device  380  of the synchronous semiconductor memory device  300 . Furthermore, the data path activation signals WM and RM generated by the timing device  370 , along with the write bank selection signal WBA, read bank selection signal RBA, row address signal RA and column address signal CA generated by the address register  305  comprise a set of synchronization signals generated by the synchronization device  380 .  
         [0030]    The row decoder  310  decodes the write bank selection signal WBA, the read bank selection signal RBA and the row address signal RA, and then selects a word line of the first memory bank for writing, and a word line of the second memory bank for reading. These selected word lines respectively correspond to the location of a memory cell in the first memory bank to data is written, and the location of a memory cell in the second memory bank from which data is read. The row address strobe signal RASB is applied to the row decoder  310 .  
         [0031]    The column decoder  325  decodes the column address signal CA, and generates a column selection signal CSL for selecting column selection lines of the first and second memory banks. The selected column selection lines respectively correspond to the location of a memory cell in the first memory bank to which data is written, and the location of a memory cell in the second memory bank from which data is read. The column address strobe signal CASB is applied to the column decoder  325 .  
         [0032]    The bit-line sense amplifier  320  amplifies a data signal written to, or output from, memory cells included in the memory banks  315 , in response to the column selection signal CSL.  
         [0033]    During the operation of the components included in the write data path WP, an input data signal DIN is applied to the input buffer  345  via the input/output pin  345 . Then, the input buffer  340  buffers the input data signal DIN, and transmits the buffered input signal DIN to the input data multiplexer  335 . Next, the input data multiplexer  335  transmits the buffered input data signal DIN to the input/output line IO 2  of the write data path WP, in response to the write master signal WM. Thereafter, the input/output line driver  330  responds to the write bank selection signal WBA, the column address signal CA selecting the memory cell of the first memory, and the write master signal WM by transmitting the input data signal DIN to the memory cell of the first memory bank selected by the column address signal CA. The input data signal DIN is transmitted to the selected memory cell via input/output line IO 1 .  
         [0034]    Next, during the operation of the components included in the read data path RP, the input/output multiplexer  350  responds to the read bank selection signal RBA, the column address signal CA selecting the memory cell of the second memory bank, and the read master signal RM by transmitting an output data signal DOUT, which was transmitted from the memory cell of the second memory bank via the input/output line IO 1 . The input/output multiplexer  350  transmits the output data signal DOUT to the input/output lines IO 2 .  
         [0035]    Then, the input/output line sense amplifier  355  receives and amplifies the output data signal DOUT from the input/output line IO 2  of the read data path RP, and transmits the amplified output data signal DOUT to a first data output line DO 1 , in response to the read master signal RM.  
         [0036]    Next, the output data multiplexer  360  receives the output data signal DOUT from the first data output line DO 1 , and transmits the received output data signal DOUT to a second data output line DO 2 .  
         [0037]    Then, the output buffer  365  receives and buffers the output data signal DOUT from the second data output line DO 2 , and, then transmits the buffered output data signal DOUT to the input/output pin  345 .  
         [0038]    As described above, the synchronous semiconductor memory device  300 , according to one embodiment of the present invention, is capable of executing the write operation of the first memory bank via one write data path in response to the write mater signal WM, and then executing the read operation of the second memory bank via one read data path in response to the read master signal RM after a predetermined time delay, even though the write operation is still being executed. While both the write and read operations are being performed, data bus lines included in the write data path WP and the read data path RP are not in an idle state, allowing the synchronous semiconductor memory device  300  to efficiently use the data bus lines. Preferably, the value of the delay time is three times as much as the period of the clock signal CLK at minimum.  
         [0039]    [0039]FIG. 4 is a timing diagram of the operation of the synchronous semiconductor memory device of FIG. 3. Referring to FIG. 4, BANK 1  denotes a first bank activation signal that indicates that the fist memory bank is activated, and BANK 2  denotes a second bank activation signal that indicates that the second memory bank is activated.  
         [0040]    When a first write command WR1, which is in synchronization with a first clock signal CLK 1 , is applied to the synchronous semiconductor memory device  300  of FIG. 3, the first bank activation signal BANK 1  and the write master signal WM are activated to reach logic ‘high’. Then, a first input data signal D 1  is fetched by a data strobe signal DQS. Next, the column selection signal CSL is generated to write the first fetched input data signal D 1  to the memory cell of the first memory bank. Referring to FIG. 4, CSL_WR 1  denotes a first write column selection line activation signal, which indicates that a column selection line of the memory cell for writing the first input data signal D 1  is activated.  
         [0041]    When a second write command WR2, which is in synchronization with a third clock signal CLK 3 , is applied to the synchronous semiconductor memory device  300 , a second input data signal D 2  is fetched by the data strobe signal DQS. Thereafter, the column selection signal CSL is generated to write the second fetched input data signal D 2  to the memory cell of the first memory bank. Referring to FIG. 4, CSL_WR 2  denotes a second write column selection line activation signal, which indicates that a column selection line of the memory cell for writing the second input data signal D 2  is activated.  
         [0042]    After a time delay TD has passed, which corresponds to three cycles of the clock signal CLK after the second write command WR2 is issued, a read command RD, which is in synchronization with a sixth clock signal CLK 6 , is applied to the synchronous semiconductor memory device  300 . When the read command RD is applied, the second bank activation signal BANK 2  and the read master signal RM are activated to reach logic ‘high.’ In other words, while the first memory bank operates, the second memory bank also operates. Thereafter, the column selection signal CSL is generated, and then, an output data signal DOUT is read from the memory cell of the second memory bank. In FIG. 4, CSL_RD a read column selection line activation signal indicating that a column selection line of the memory cell for reading the output data signal DOUT is activated.  
         [0043]    As indicated by CASE2 of FIG. 4, the column selection line activation signals CSL_WR 2  and CSL_RD are activated to logic ‘high’ at the same time, showing that the second memory bank BANK 2  executes the read operation during the write operation of the first memory bank BANK 1 .  
         [0044]    An exemplary mode of operation is described above for the synchronous semiconductor memory device  300  of the present invention, in which a second memory bank starts executing the read operation while a first memory bank is already executing the write operation. However, the above description is merely illustrative, and in no way limits the present invention to such a mode of operation. For example, the second memory bank may begin executing a write operation while the first memory bank is executing a read operation. Accordingly, a data bus line shared by the first and second memory banks can be efficiently used, thereby enhancing the performance of the synchronous semiconductor memory device.  
         [0045]    While the present invention has been particularly shown and described with reference to an exemplary embodiment thereof, the present invention is not restricted to the above embodiment. Further, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention as defined by the appended claims.