Abstract:
In a voltage generator having a voltage level detector, an oscillator, and a voltage pump, the voltage level detector comprises an amplifier, which, in combination with a first and a second linear current source, provides accurate control of an output voltage of the voltage generator. When a sensed voltage deviates around a reference voltage, a differential detection by the amplifier of this deviation causes the oscillator and the voltage pump to provide a corresponding increase or decrease in the magnitude of an output voltage in order to compensate for the deviation. Use of the amplifier and a predetermined reference voltage allows for an accurate threshold detection level for low-voltage, high-speed operation of the voltage generator. The present invention can be used in both positive and negative voltage generators.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a voltage generator and, more particularly, to a voltage generator using a voltage level detector. The present invention provides a means for accurately monitoring and correcting changes in a sensed voltage rail. 
     2. Description of the Prior Art 
     Devices using a battery as a power source generally include a positive voltage generator that internally generates a voltage higher than the battery voltage. Similarly, a conventional semiconductor memory device also includes a positive voltage generator that generates a voltage having a higher magnitude than an applied voltage and a substrate voltage generator that generates a substrate voltage having a lower magnitude than a ground voltage. 
     Both the positive voltage generator and the substrate voltage generator include a voltage level detector, an oscillator and a pumping circuit. The voltage level detector senses an output voltage and generates a voltage signal that represents whether a sensed voltage is higher or lower than a desired voltage level. The oscillator generates a pulse signal in response to this voltage signal that causes the pumping circuit to change the output voltage to a desired voltage level. The voltage generator is activated only when the output voltage becomes higher or lower than the desired voltage level. 
     The voltage generator generates a voltage having a triangular wave-shape of a predetermined amplitude and period and that is a function of the speed of the voltage level detector and a capacitance associated with the pumping circuit. The generated voltage changes according to a combination of the pumping circuit capacitance and a load capacitance. 
     Also, a voltage detection threshold of the detector can vary with process variations, which in turn can cause significant variations in the output voltage of the voltage generator. As a result, the voltage generator cannot generate a stable output voltage, and as the output voltage rises significantly, the detector will operate at a greatly reduced speed. 
     SUMMARY OF THE INVENTION 
     To overcome the problems described above, preferred embodiments of the present invention provide a voltage level detector of a voltage generator that can stabilize an output voltage level even though an internal voltage detection threshold level varies. This reduction in the variation range of the output voltage level increases the operating speed of the voltage generator. 
     In a preferred embodiment of the present invention, a voltage generator comprising a voltage level detector, an oscillator, and voltage booster provides voltage regulation to an on-chip biasing voltage. The voltage level detector further comprises an amplifier element and an accurate analog-to-digital conversion element, the combination of which provides precision control over an output voltage waveshape and thus the response time of the generator. 
     By employing a first and a second current source in conjunction with a feedback amplifier, a precision voltage theshold can be used to activate a threshold detector which in turn enables a voltage oscillator to provide an appropriate digital pulse signal to the voltage booster. The voltage booster regulates the magnitude of an output voltage which is fed back to the input of the voltage generator. The present invention can be used to create both positive and negative voltage generators. 
     These and other features of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which like reference numerals denote like parts, and in which: 
     FIG. 1 illustrates a block diagram of a conventional positive voltage generator; 
     FIG. 2 illustrates a circuit diagram of a positive voltage level detector element of the conventional positive voltage generator shown in FIG. 1; 
     FIG. 3 illustrates a circuit diagram of an oscillator element of the conventional positive voltage generator shown in FIG. 1; 
     FIG. 4 illustrates a circuit diagram of a voltage booster element of the conventional positive voltage generator shown in FIG. 1; 
     FIG. 5 illustrates a block diagram of a conventional substrate voltage generator; 
     FIG. 6 illustrates a circuit diagram of a substrate voltage level detector element of the conventional substrate voltage generator shown in FIG. 5; 
     FIG. 7 illustrates a circuit diagram of an oscillator element of the conventional substrate voltage generator shown in FIG. 5; 
     FIG. 8 illustrates a circuit diagram of a voltage step-down circuit of the conventional substrate voltage generator shown in FIG. 5; 
     FIG. 9 illustrates an exemplary circuit diagram of a positive voltage level detector element according to a preferred embodiment of the present invention; 
     FIG. 10 illustrates an exemplary circuit diagram of an alternate embodiment of the positive voltage level detector element shown in FIG. 9 according to the present invention; 
     FIG. 11 illustrates a graph showing variations of a high voltage with respect to an external power voltage during a burn-in test of a semiconductor memory device. manufactured according to the present invention; 
     FIG. 12 illustrates an exemplary circuit diagram of another embodiment of the positive voltage level detector element shown in FIG. 10 according to the present invention; 
     FIG. 13 illustrates an exemplary circuit diagram of a substrate voltage level detector according to a preferred embodiment of the present invention; and 
     FIG. 14 illustrates an exemplary circuit diagram of an alternate embodiment of the substrate voltage level detector shown in FIG. 13 according to the present invention. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Korean Patent Application No. 2000-61574, filed on Oct. 19, 2000, entitled “A High Speed and Reliable VPP, VBB Level Detector Circuit” is incorporated herein by reference in its entirety. 
     Preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. For simplicity, a voltage label VINT is used throughout the following description to represent a wide variety of internal biasing voltages. As is known in the art, actual biasing voltages can vary widely from circuit to circuit and within a same circuit without restricting the scope of the present invention, and where a plurality of such labels are included in a single schematic, it is not intended to restrict the invention to a single voltage. 
     Returning now to FIG. 1, a conventional positive voltage generator includes a positive voltage level detector  10 , an oscillator  12  and a voltage booster  14 . The positive voltage level detector  10  generates a positive voltage detection signal VPPS whenever a sensed voltage VPP decreases below a predetermined threshold voltage. Oscillator  12  generates a pulse signal VPPSS in response to the positive voltage detection signal VPPS. Voltage booster  14  increases VPP in response to the pulse signal VPPSS. 
     FIG. 2 illustrates an exemplary circuit diagram of the positive voltage level detector  10  of FIG.  1 . As shown in FIG. 2, the positive voltage level detector  10  includes an attenuator comprised of a PMOS transistor P 1 , NMOS transistors N 1 , N 2 , and N 3  and a logical inverter  102 . The PMOS transistor P 1  and the NMOS transistor N 1  are serially connected between an internal power voltage VINT and a node A and have a gate to which a ground voltage and the high voltage VPP are applied, respectively. The NMOS transistors N 2  and N 3  are serially connected between the node A and the ground voltage and have a gate to which the internal power voltage and the high voltage VPP are applied, respectively. Inverter  102  inverts and buffers a signal of the node A to generate the high voltage detecting signal VPPS. The PMOS transistor P 1  and the NMOS transistors N 1  to N 3  constitute a voltage attenuator. Inverter  102  inverts and buffers a signal at node A  104  to generate a logical positive voltage detection signal VPPS. 
     If it is assumed that transistors N 1  and N 2  are operated as linear current sources having transconductances, gm 1  and gm 2 , respectively, and a voltage at node  104  can be represented by the equation              VA   =     VPP                   gm1     (     gm1   +   gm2     )                 [   1   ]                                
     where VA is the voltage at node  104  and Vpp is the analog input sensed voltage, an exemplary voltage attenuation of variations in VPP according to equation [1] can be between 0.1 to 0.4 VPP. 
     Inverter  102  generates a VPPS signal having a logic “high” level when VA is at a lower voltage than a logic threshold voltage of inverter  102 , and generates a logic “low” level when VA is higher than that threshold. However, such a positive voltage level detector can have significant variations in the threshold voltage of inverter  102  due to manufacturing process variations. Such variations can lead to an inaccurate output voltage signal VPPS. For example, assuming that an attenuation of the positive voltage level detector  10  is set to “0.4”, and a threshold voltage of the inverter  102  is designed to be 1.5 volts in order to generate an output VPP of 4.0 volts, if a process variation produces a threshold voltage of inverter  102  of 1.6 volts, voltage VPP would be generated at 4.25 volts. Similarly, if the threshold voltage of inverter  102  is manufactured at 1.7 volts, VPP becomes 4.5 volts. From the foregoing it is obvious that a conventional positive voltage level detector  10  cannot generate an accurate positive voltage VPP. 
     FIG. 3 illustrates an exemplary circuit diagram of the oscillator  12  of FIG. 1, which includes inverters  121 ,  122 ,  123 ,  124 , and  125 , an NMOS transistor N 4 , and a PMOS transistor P 2 . The inverters  121  to  125  are connected with each other in the form of a ring shape. When a VPPS signal from positive voltage level detector  10  having a logic “high” level is applied, transistor N 4  is turned on to enable oscillator  12 , and inverters  121  to  125  generate an output pulse signal VPPSS. Conversely, when a logic “low” level is applied at VPPS, transistor P 2  is turned on to disable oscillator  12 , and output signal VPPSS is held at a logic “low” level. 
     FIG. 4 illustrates an exemplary circuit diagram of the voltage booster  14  of FIG.  1 . Voltage booster  14  includes an NMOS capacitor NC 1 , NMOS transistors N 5  and N 6 , and a capacitor C 1 . In an exemplary operation, a node B  142  is pre-charged to a voltage (VINT−Vth) where Vth is a threshold voltage of transistor N 5 . When an input pulse voltage VPPSS makes a transition from a logic “low” to a logic “high” level, the voltage VB at node  142  is boosted by a boosting ratio α of the capacitor NC 1  to (VINT−Vth+α VINT), thus turning on transistor N 6 . VB is then coupled to an output node C, or VPP, causing VPP to rise. As VPP charges to VB less a threshold voltage Vth of transistor N 6 , transistor N 6  turns off, thereby halting the charge transfer to VPP. 
     Alternatively, when input pulse voltage VPPSS makes a transition from a logic “high” to a logic “low” level, causing voltage VB to drop below VINT−Vth, transistor N 5  provides charge to node  142  and capacitor NC 1  such that VB rises to a voltage level of VINT−Vth, and subsequent pulse signals on VPPSS cause VPP to reach a voltage {(1+α)VINT−2Vth}. Thus, when output VPP decreases, charge is provided by either capacitor NC 1  or transistor N 5  via transistor N 6  to restore an appropriate output voltage level. 
     From the above, it is clear that with alternating transitions of VPPSS, VPP will have a triangular waveshape of a predetermined amplitude and period due the charging effects of capacitors NC 1  and C 1 . Further, when the amplitude of the triangular wave of VPP becomes large, the operating speed of the detector of FIG. 2 slow significantly, and voltage VPP that may be measured during an instantaneous test may also vary significantly. Typically, to reduce the foregoing effects, the amplitude of the triangular waveshape can be reduced by reducing the size of input capacitor NC 1  and increasing the size of the output capacitor C 1 . 
     FIG. 5 illustrates a block diagram of a conventional substrate voltage generator used in a semiconductor memory device. The substrate voltage generator includes a substrate voltage level detector  20 , an oscillator  22  and a voltage step-down circuit  24 . The substrate voltage level detector  20  generates a substrate voltage detection signal VBBS whenever a sensed substrate voltage VBB increases above a predetermined threshold voltage. Oscillator  22  generates a pulse signal VBBSS in response to the substrate voltage detection signal VBBS. Voltage step-down circuit  24  step-downs the substrate voltage VBB in response to the pulse signal VBBSS. 
     FIG. 6 illustrates an exemplary circuit diagram of the substrate voltage level detector  20  of FIG.  5 . As shown in FIG. 6, the substrate voltage level detector  20  includes PMOS transistors P 3  and P 4 , an NMOS transistor N 7  and an inverter  202 . The PMOS transistor P 3  is connected between an internal power voltage VINT and a node D  204  and has a gate to which a ground voltage is applied. The PMOS transistor P 4  and the NMOS transistor N 7  are serially connected between node  204  and a ground voltage and have a gate to which the substrate voltage VBB and the internal power voltage VINT are applied, respectively. Inverter  202  inverts and buffers a signal at node  204  to generate the substrate voltage detection signal VBBS. The combination of transistors P 3 , P 4 , and N 7  constitute a voltage attenuator. 
     If it is assumed that transconductances of the transistors P 3  and P 4  are, respectively, “gm3” and “gm4”, a voltage at node D  204  can be represented by the equation              VD   =     VBB                   gm3     (     gm3   +   gm4     )                 [   2   ]                                
     where VD is the voltage at node D  204  and VBB is the input sensed voltage. In general, an exemplary voltage attenuation of variation in VBB according to equation [2] can be between 0.1 to 0.4 VBB. 
     Inverter  202  generates a substrate voltage detection signal VBBS having a logic “high” level when a VD is at a lower voltage than a logic threshold voltage of inverter  202 , and generates a logic “low” level when VD is higher. However, like the positive voltage generator of FIG. 2, the substrate voltage level detector  20  can have significant variations in the threshold voltage of inverter  202  due to manufacturing process variations and cannot generate an accurate substrate voltage. 
     FIG. 7 illustrates an exemplary circuit diagram of the oscillator  22  of FIG.  5 . Oscillator  22  includes inverters  220 ,  222 ,  224 ,  226 , and  228 , a PMOS transistor P 5 , and an NMOS transistor N 8 . Inverters  220  to  228  are connected with each other in the form of a ring shape. 
     When a VBBS signal from substrate voltage level detector  20  having a logic “low” level is applied, transistor P 5  is turned on to enable oscillator  22 , and inverters  220  to  228  generate an output pulse signal VBBSS. Conversely, when a logic “high” level is applied at VBBS, transistor N 8  is turned on to disable oscillator  22 , and output signal VBBSS is held at a logic “low” level. 
     FIG. 8 illustrates an exemplary circuit diagram of the voltage step-down circuit  24  of FIG.  5 . The voltage step-down circuit  24  includes an NMOS capacitor NC 2  and NMOS transistors N 9  and N 10 . 
     A voltage at a node E  242  and the substrate voltage VBB are all maintained to be “0” volts. When a pulse signal VBBSS having a logic “high” level is applied, VE is raised to a logic “high” level by capacitor NC 2 . This causes transistor N 9  to turn on draining charge from node  242  and capacitor NC 2 , thus pre-charging/discharging VE to a threshold voltage level Vth of transistor N 9 . As VE decreases below the threshold voltage of transistor N 9 , transistor N 9  turns off. 
     Alternatively, when the pulse signal VBBSS having a transition from a “high” to a “low” logic level is applied, VE is impressed with a voltage Vth−VINT by capacitor NC 2 , thereby turning on transistor N 10  and supplying charge from node  242  to a substrate voltage generating terminal, and VE is raised from a voltage Vth−VINT to a threshold voltage Vth. When VE is equal to the threshold voltage Vth of transistor N 10 , transistor N 10  is turned off, and the substrate voltage VBB is charged to a more negative voltage. 
     By repeatedly performing the operation described above, the substrate voltage VBB is gradually lowered, and when the substrate voltage VBB is equal to a predetermined voltage (2Vth−VINT), a charge supply from node  242  is halted. At this point, in a manner similar to the positive voltage generator  14  of FIG. 2, the substrate voltage signal VBB outputted from the voltage step-down circuit  24  has a triangular wave-shape having a predetermined amplitude and period, and when the amplitude of the triangular wave of the substrate voltage VBB becomes large, the operating speed of the substrate voltage level detector slows. 
     The present invention is directed to improving the positive voltage level detector  10  and the substrate voltage level detector  20  to overcome the foregoing problems relating to speed and accuracy. 
     FIG. 9 illustrates an exemplary circuit diagram of a positive voltage level detector according to a preferred embodiment of the present invention. The positive voltage level detector  50  includes a PMOS transistor P 6 , NMOS transistors N 11  and N 12 , a differential amplifier AMP 1 , and an inverter  302 . 
     The PMOS transistor P 6  and the NMOS transistor N 11  are serially connected between an internal power voltage VINT and a node F and have a gate to which a ground voltage and a high voltage VPP are applied, respectively. The NMOS transistor N 12  is connected between the node F and a ground voltage and has a gate to which a voltage Vout 1  is applied. Differential amplifier AMP 1  amplifies a voltage difference between a reference voltage VREF and a voltage at a node F  304  to generate a controlled intermediate output voltage Vout 1  at a node  306 . Inverter  302  inverts and buffers the voltage Vout 1  to generate a positive voltage detection signal VPPS. 
     If it is assumed that transistors N 11  and N 12  are operated as linear current sources having transconductances, gm 5  and gm 6 , respectively, when an input positive voltage VPP is raised, a current (gm 5 ×ΔVPP) flows to node  304 . A feedback current (gm 6 ×ΔVout 1 ) flows from node  304  though transistor N 12  under control of voltage Vout 1  at node  306 . A feedback loop associated with a linear feedback amplifier AMP 1  will cause the output of amplifier AMP 1  to change such that node  306  remains at a constant voltage that is equal to VREF. Thus, amplifier AMP 1  in conjunction with VREF provides a precision threshold voltage for determining the output voltage VPPS, and satisfies the equation gm 5 ×ΔVPP=gm 6 ×ΔVout 1 . 
     For a brief overview of the operation, when analog input voltage VPP decreases, the current flowing in transistor N 11  decreases, and the voltage at node  306  is correspondingly lowered. Differential amplifier AMP 1  compares the voltage at node  306  with the reference voltage VREF and lowers the voltage Vout 1 . This causes the amount of current flowing through transistor N 12  to proportionately decrease, such that the voltage at node  306  is restored to be equal to VREF. Similarly, an increase in VPP will cause a corresponding increase in the voltages at node  304  and at node  306  as well as in the current conducting in transistor N 12 . 
     Inverter  302  generates VPPS having a binary logic “high” level when VPP is lowered such that voltage Vout 1  is lower than the threshold voltage and generates VPPS having a binary logic “low” level when VPP is boosted so that voltage Vout 1  is higher than the threshold voltage. 
     A voltage gain Av (i.e., ΔVout 1 /ΔVPP) of the positive voltage level detector  50  of FIG. 9 can be represented as “gm5/gm6”, and therefore, a voltage gain can be made higher than “1” by adjusting transconductance values of the transistors N 11  and N 12 . For example, assuming that a voltage gain of the positive voltage detector  50  is set to “1.2,” and a threshold voltage of the inverter  302  is designed to be 1.5 volts in order to generate the output positive voltage VPP of 4.0 volts, if the threshold voltage of the inverter  302  is manufactured at 1.6 volts due to a process variation, the output VPP would be raised to 4.08 volts. Similarly, when the threshold voltage is manufactured to 1.7 volts, the VPP would be raised to 4.16 volts. 
     Therefore, even though a threshold voltage of the inverter  302  can vary significantly due to a process variation, the positive voltage level detector  50  of the present invention can generate a stable positive voltage VPP by making the variations in the positive voltage VPP much lower than the variations in the threshold voltage. Further, VPP is stable, thereby reducing amplitude variations in the output triangular wave and, thus, providing a higher operating speed over conventional embodiments. 
     FIG. 10 illustrates an exemplary circuit diagram  60  having a modification of the positive voltage level detector according to an alternate embodiment of the present invention. In positive voltage level detector  50  of FIG. 9, an NMOS transistor N 13  can be added between the node  304  and a ground voltage. Transistor N 13  is turned on in response to the internal power voltage VINT. This added transistor N 13  can be used to improve variations in VPP with respect to an external power voltage VEXT during a burn-in test of a semiconductor memory device. 
     FIG. 11 illustrates an exemplary graph showing variations in VPP with respect to the external power voltage VEXT during a burn-in test of a semiconductor memory device. In the graph of FIG. 11, a dotted line  62  denotes an ideal variation in VPP with respect to VEXT, and a solid line  64  denotes a variation in VPP with respect to VEXT when the positive voltage level detector  50  of FIG.  9 . is employed in the positive voltage generator according to a preferred embodiment of the present invention. 
     In an alternate embodiment of the circuit diagram shown in FIG. 10, when VEXT is raised to be higher than a voltage V 2 , transistor N 13  draws current away from node  304  to the ground voltage, causing the positive voltage level detector  60  of FIG. 10 to generate the characteristics of dotted line  62  of FIG. 11, i.e. when the external power voltage VEXT is raised to be higher than a voltage V 2 , the internal power voltage VINT, which has identical characteristics as the graph shown in FIG. 11, is applied to the gate of the transistor N 13  so that a larger amount of a current flows through transistor N 13 . Therefore, even though a larger current flows to node  304  through the transistor N 11  due to increases in VPP, the positive voltage level detector of FIG. 10 can have similar characteristics to the dotted line  62  of FIG. 11 due to the sinking capabilities provided by transistor N 13 . 
     FIG. 12 illustrates an exemplary circuit diagram having a modification of a positive voltage level detector  70  according to another embodiment of the present invention. In addition to the positive voltage level detector  60  of FIG. 10, a low-pass resistor-capacitor combination (RC) loop filter  30  is added between node  306  of differential amplifier AMP 1  and the gate of transistor N 12 , which includes a resistor R 1  connected between node  306  and the gate of the transistor N 12 , and a capacitor C 2  connected between node  306  and a ground voltage. RC Loop filter  30  provides for a removal of high frequency components that can be contained in the output voltage Vout 1  before applying that signal to the gate of the transistor N 12 , thereby stabilizing the operation of the positive voltage level detector  70 . 
     FIG. 13 illustrates an exemplary circuit diagram of a negative substrate voltage level detector  80  according to a preferred embodiment of the present invention. As shown in FIG. 13, the substrate voltage level detector  80  includes PMOS transistors P 7 , P 8 , and P 9 , an NMOS transistor N 14 , a differential amplifier AMP 2 , and an inverter  320 . 
     The substrate voltage level detector  80  shown in FIG. 13 is similar to substrate voltage level detector  20  shown in FIG. 6, but additionally includes a PMOS transistor P 9  connected between an internal power voltage VINT and a node G  322  and having a gate to which an output voltage Vout 2  is applied and the differential amplifier AMP 2  amplifying a voltage difference between a voltage of node  322  and a reference voltage VREF to generate the output voltage Vout 2 . 
     If it is assumed that transconductances of the transistors P 8  and P 9  are “gm7” and “gm8”, respectively, a current flowing along the PMOS transistor P 8  is “i1”, and a current flowing along the PMOS transistor P 9  is “i2”. A current Δi 2  can be represented as “gm8×ΔVBB”, and a current Δi 1  can be represented as “gm7×ΔVout2”. When a current i 1  is equal to a current i 2 , a voltage gain ΔVout 2 /ΔVBB is represented as “gm8/gm7”. Therefore, when the equation “gm8×ΔVBB=gm7×ΔVout2” is satisfied, a voltage of node  322  can be maintained at a constant level, and the output voltage Vout 2  of differential amplifier AMP 2  can also be maintained at a constant level. 
     When analog input substrate voltage VBB decreases in magnitude so that the current flowing in transistor P 8  increases, a voltage at node  322  decreases. Differential amplifier AMP 2  compares the voltage at node  322  with the reference voltage VREF and lowers the output voltage Vout 2  to increase an amount of a current flowing through transistor P 9  when a voltage at node  322  is lower than VREF. 
     Alternatively, when the analog input substrate voltage VBB increases such that the current flowing through the transistor P 8  is decreased, the voltage at node  322  increases. The differential amplifier AMP 2  compares the voltage at node  322  with the reference voltage VREF and raises the output voltage Vout 2  to decrease an amount of a current flowing in transistor P 9 , thereby lowering the voltage at node  322 . 
     Inverter  320  generates a substrate voltage detection signal VBBS having a binary logic “high” level when the analog input substrate voltage drops and the output voltage Vout 2  becomes lower than a threshold voltage thereof, and generates the substrate voltage detecting signal VBBS having a binary logic “low” level when the analog input substrate voltage is raised and the output voltage Vout 2  becomes higher than a threshold voltage thereof. 
     FIG. 14 illustrates a circuit diagram having a modification to the substrate voltage level detector shown in FIG.  13 . The substrate voltage level detector  90  of FIG. 14 further includes a RC loop filter  40  in addition to substrate voltage level detector  80  shown in FIG.  13 . The RC loop filter  40  includes a resistor R 2  and a capacitor C 3  between a node of the output voltage Vout 2  and a gate of the PMOS transistor P 9 . The RC loop filter  40  serves to remove a high frequency component contained in the output voltage Vout 2  before applying the signal to the gate of the transistor P 9 , thereby stabilizing the operation of substrate voltage level detector  90 . 
     The positive voltage generator and the substrate voltage generator according to the preferred embodiments of the present invention can be applied to all devices that utilize a battery as a power source and that also require a higher voltage or a lower voltage than the voltage of the battery as well as the semiconductor memory device. 
     As described hereinabove, the voltage level detectors according to preferred embodiments of the present invention exhibit significant advantages. Even though a logical voltage detection threshold can vary widely due to process variations, a stable voltage having small or minor variation can be generated. Also, this leads to a decreased amplitude of the input sensed voltage, which allows for a higher operating speed of the detector stage. 
     Preferred embodiments of the present invention have been disclosed herein, and although specific terms are employed, they are used in a generic and descriptive sense only and not for purpose of limitation. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the invention as set forth in the following claims.