Abstract:
A gain compensation circuit that compensates for variations in gain of a high gain, high frequency amplifier due to changes in mobility of transistor and resistor components of the amplifier. The gain compensation circuit includes a current adjustment circuit and a gain factor evaluation circuit. The current adjustment circuit modifies a bias current provided to each amplifier stage of a plurality of amplifier stages that make up the high gain, high frequency amplifier. The modification of the bias current adjusts the gain factor of the amplifier. The gain factor evaluation circuit is in communication with the current adjustment circuit to determine changes in the gain factor of the high gain, high frequency amplifier. From the determination, the gain factor evaluation circuit provides a compensation signal to the current adjustment circuit indicating a modification factor for the biasing current for each amplifier stage.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to high gain, high frequency amplifier circuits. 
     More particularly, this invention relates to circuits that compensate for changes and fluctuations in the gain of high gain, high frequency amplifier circuits due environmental factors such as manufacturing process, temperature, and operating conditions. 
     2. Description of Related Art 
     The basic structure of a differential amplifier well known in the art and is generally as shown in FIG.  1 . The n-type metal oxide semiconductor (NMOS) transistors M 1  and M 2  are generally coupled at their sources and connected to the current source I B . The drains of the NMOS transistors M 1  and M 2  are respectively connected to the equal valued load resistors RL 1  and RL 2 . The gates of the NMOS transistors Ml and M 2  are respectively connected to the input terminals IN 1  and IN 2 . The drain currents of the NMOS transistors M 1  and M 2  are summed and must be equal to the current of the current source I B . It can thus be shown that the voltage present at the drain of the NMOS transistors M 1  and M 2  is equal to: 
       V   OUTd   =−g   m   RL   n   V   lNd   
     where: 
     V OUTd  is the differential voltage at the output nodes OUT 1  and OUT 2 . 
     g m  is the transconductance of the NMOS transistors M 1  and M 2 . 
     RL n  is the resistance of the resistors RL 1  or RL 2 . 
     V INd  is the differential voltage at the input nodes IN 1  and IN 2 . 
     The variations in the differential voltage V OUTd  due to variations in the environmental factors such as temperature, process parameters, and operating conditions can be shown to effect the values of the transconductance gm of the NMOS transistors M 1  and M 2  and the dependence of the resistors RL 1  and RL 2  to the environmental factors. One method for compensation of these variations is to place the source degeneration resistors Rs 1  and Rs 2  respectively in the source connections of the NMOS transistors M 1  and M 2 . The source degeneration resistors Rs 1  and Rs 2  have resistance designs to sufficiently improve the immunity of the differential amplifier to the variations, but not impact the dynamic range of the output voltage V OUTd . 
     The effective transconductance g ms  of the NMOS transistors M 1  and M 2  in combination with the source degeneration resistors Rs 1  and Rs 2  can be shown to be equal to:                g   ms     =       g   m       1   +       g   m        Rs                 Eq   .              1                                
     Further, the gain of the differential amplifier is then expressed as:              Av   =         V   OUTd       V   INd       =       g   ms          RL   n                 Eq   .              2                                
     As is known the appropriate choices of the materials for the resistors Rs 1  and Rs 2  and the resistors RL 1  and RL 2  minimize the effects of the environmental factors. However, this does not stabilize the gain completely. 
     As the gain requirements for an amplifier increases, multiple differential amplifiers of FIG. 1 are cascaded as shown in FIG.  2 . The first differential stage Av 1  of the cascaded amplifier is formed of the NMOS transistors M 20  and M 21 , the load resistors RL 3  and RL 4 , the current source I B1 , and the source degeneration resistors Rs 1  and Rs 2  configured as shown in FIG.  1 . The second differential stage Av 2  of the cascaded amplifier is formed of the NMOS transistors M 22  and M 23 , the load resistors RL 5  and RL 6 , the current source I B2 , and the source degeneration resistors RS 3  and Rs 4 , also configured as shown in FIG.  1 . Similarly, the third differential stage AV 3  of the cascaded amplifier is formed of the NMOS transistors M 24  and M 25 , the load resistors RL 7  and RL 8 , the current source I B3 , and the source degeneration resistors Rs 5  and Rs 6 , which are configured as shown in FIG.  1 . The input nodes IN 1  and IN 2  are coupled by capacitors C P1  and C P2  to the gates of the NMOS transistors M 20  and M 21 . The bias resistors R B1  and R B2  provide a biasing voltage from the biasing voltage power supply V GG  to bias the amplifier Av 1  to operate in a linear, high gain region. The output terminals of the amplifier Av 1  are coupled through the capacitors C P3  and C P4  to the gates of the NMOS transistors M 22  and M 23 . As described for the bias resistors R B1  and R B2 , the bias resistors R B3  and R B4  provide a biasing voltage from the biasing voltage power supply V GG  to bias the amplifier Av 2  to operate in a linear, high gain region. Next, the output terminals of the amplifier Av 2  are coupled through the capacitors C P5  and C P6  to the gates of the NMOS transistors M 24  and M 26 . As described for the bias resistors R B1  and R B2  and the bias resistors R B3  and R B4 , the bias resistors R B5  and R B6  provide a biasing voltage from the biasing voltage power supply V GG  to bias the amplifier Av 3  to operate in a linear, high gain region. The output signal of the amplifier is coupled through the capacitors C P7  and C P8  to the output terminals OUT 1  and OUT 2 . The gain of the amplifier of FIG. 2 is the product of the individual gains of the differential amplifier stages Av 1 , Av 2 , and Av 3  and are determined as defined above for the amplifier described in FIG.  1 . Further, the number of differential amplifier stages Av 1 , Av 2 , and Av 3  is determined by the total gain required for the amplifier, thus the design of the individual stages may vary to accommodate the design requirements. 
     As described above the source degeneration resistors Rs 3 Rs 4 , Rs 5  and Rs 6 , Rs 7  and Rs 8  are added to partially compensate for the variations in the environmental factors. Further, other compensation techniques employ feedback to adjust the gain of the differential amplifier stages with changes in the environmental factors. However, feedback techniques do not work well when very large gain factors are required for the amplifier. In Analog Integrated Circuit Design, Johns and Martin, John Wiley &amp; Sons, Inc., New York, 1999, pp. 248-251, the author notes that the transconductance of the NMOS transistors of a differential amplifier is the most important parameter to stabilize. The authors detail and analyze basic techniques to prevent variations of the transconductance with variations in the environmental factors. 
     U.S. Pat. No. 6,018,270 (Stuebing, et al.) describes a single biasing circuit for a single or multiple stage low voltage RF circuits including one or more amplifiers and one or more single or double balanced mixers. The biasing circuit incorporates compensation for temperature and integrated circuit process parameters. 
     U.S. Pat. No. 4,409,558 (Knijnenburg, et al.) describes a gain compensated transistor amplifier arrangement for use in power protection circuits. The amplifier includes an emitter-follower transistor. The collector current of the emitter-follower transistor is fed to a resistor to compensate for variations in the current gain factor of the transistors of the amplifier. 
     U.S. Pat. No. 4,916,407 (Olver) illustrates a gain variation compensating circuit for a feed-forward linear amplifier. The gain compensating circuit counteracts the gain variations and restores balance and fundamental cancellation to the circuit while retaining the highly linear characteristics of the amplifier. 
     U.S. Pat. No. 5,274,339 (Wideman, et al.) teaches circuit for compensating for GaAs FET amplifier gain variations over a frequency band as a function of temperature. The circuit includes a passive equalizer circuit having a fixed gain over the frequency band and an active equalizer circuit, in series with the passive equalizer, having a gain, which varies over the frequency band as a function of temperature. 
     U.S. Pat. No. 6,046,642 (Brayton, et al.) describes an active bias compensation circuit that senses a quiescent current flowing in an amplifier and adjusts the quiescent current to maintain an optimal DC biasing of the amplifier over a wide range of temperature variation, process variation, history of the amplifier, etc. 
     U.S. Pat. No. 5,673,047 (Moreland) describes a gain compensating difterential reference circuit that is used to match the gain of an input differential amplifier that is an input of an analog-to-digital converter to provide a biasing voltage to the analog-to-digital converter. 
     U.S. Pat. No. 4,929,909 (Gilbert) teaches a single differential amplifier including a current source for generating a biasing tail current to compensate for the non-ideal transistor geometries and properties. The compensation results in an amplification ratio, which is substantially independent of all component variations. 
     U.S. Pat. No. 5,994,961 (Lunn, et al.) teaches an amplifier circuit that has a gain control input signal to adjust the gain of the amplifier. The gain control input signal is passed through a temperature compensating circuit, which provides a gain compensation to adjust the gain of the amplifier for temperature. The gain of the amplifier is adjusted as desired, however, the amplifier gain is compensated for temperature variations. 
     SUMMARY OF THE INVENTION 
     An object of this invention is to provide a gain compensation circuit that compensates for variations in gain of a high gain, high frequency amplifier. 
     Another object of this invention is to provide a circuit that adjusts biasing currents of a high gain, high frequency amplifier to compensate fully for changes in mobility of transistor and resistor components of the amplifier. 
     To accomplish at least one of these objects and other objects, a gain compensation circuit includes a current adjustment circuit and a gain factor evaluation circuit. The current adjustment circuit modifies a bias current provided to each amplifier stage of a plurality of amplifier stages that make up a high gain, high frequency amplifier. The modification of the bias current adjusts the gain factor of the amplifier. The gain factor evaluation circuit is in communication with the current adjustment circuit to determine changes in the gain factor of the high gain, high frequency amplifier. From the determination, the gain factor evaluation circuit provides a compensation signal to the current adjustment circuit indicating a modification factor for the biasing current for each amplifier stage. 
     In a first embodiment of this invention, the current adjustment circuit has a first reference constant current source mirrored from a reference current source to generate a reference current. A first replica amplifier is connected to the first reference constant current source to conduct a master biasing current that is modified according to the compensation signal. Biasing currents for each amplifier is provided by a plurality of mirroring current sources. Each mirroring current source is in communication with the first replica amplifier stage such that each mirroring current sources generates one bias current proportional to the master bias current of the replica amplifier stage. 
     In a second and third embodiment of this invention, the current adjustment circuit is a plurality of mirroring current sources. The mirroring current sources provide the bias currents for each amplifier stage. The mirroring current sources receive the compensating signal from the gain factor evaluation circuit. In this embodiment, the compensating signal is a compensation current from which the bias currents are mirrored. 
     The gain factor evaluation circuit has a reference voltage source to provide a first and a second reference voltage, which are inputs to a second replica amplifier stage. The second replica amplifier stage amplifies a voltage difference between the first and the second reference voltages. The gain factor evaluation circuit has a compensation signal generator connected to the second replica amplifier stage to receive the amplified voltage difference, modulate a biasing current of the second replica amplifier stage and, when the amplified voltage difference approaches a null level, produce the compensation signal. The compensation signal generator is formed of an operational amplifier having an in-phase input and an out-of-phase input connected to receive the amplified voltage difference. The compensation signal generator has a first master current source that provides the biasing current to the second replica amplifier and a second master current source joined to the out-of-phase input of the operational amplifier. The second master current source causes a voltage level to be present at the out-of-phase input to be modified. The second master current source is coupled to the first master current source such that they are proportional, irrespective of environmental changes. The compensation signal generator further has a current feedback circuit connected between an output of the operational amplifier and the first master current source to sink a compensation current to the first master current source. The biasing current of the second replica amplifier and the compensating current are combined such that, as the operational amplifier changes the compensation current, the biasing current of the second replica amplifier adjusts inversely. The compensation signal generator additionally has a compensation signal converter communicating with the operational amplifier to form the compensation signal as a function of the compensating current. In the preferred implementation the compensation signal converter is a first voltage-to-current converter. 
     The current feedback is formed by a second voltage-to-current converter that transforms a compensating voltage at the output of the operational amplifier to the compensation current. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a differential amplifier stage having degenerative feedback of the prior art. 
     FIG. 2 is a schematic diagram of a high gain, high frequency amplifier of the prior art. 
     FIG. 3 is block diagram drawing of a first embodiment of a gain compensation circuit for a high gain, high frequency amplifier of this invention. 
     FIG. 4 is a schematic diagram of a first embodiment of a gain compensation circuit for a high gain, high frequency amplifier of this invention. 
     FIG. 5 is a schematic diagram of a high gain, high frequency amplifier that employs the first embodiment of a gain compensation circuit of this invention. 
     FIG. 6 is block diagram drawing of a second embodiment of a gain compensation circuit for a high gain, high frequency amplifier of this invention. 
     FIG. 7 is a schematic diagram of a second embodiment of a gain compensation circuit for a high gain, high frequency amplifier of this invention. 
     FIG. 8 is a schematic diagram of a high gain, high frequency amplifier that employs the second embodiment of a gain compensation circuit of this invention. 
     FIG. 9 is block diagram drawing of a third embodiment of a gain compensation circuit for a high gain, high frequency amplifier of this invention. 
     FIG. 10 is a schematic diagram of a third embodiment of a gain compensation circuit for a high gain, high frequency amplifier of this invention. 
     FIG. 11 is a schematic diagram of a high gain, high frequency amplifier that employs the third embodiment of a gain compensation circuit of this invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     To adjust the total gain of the differential amplifier as shown in FIG. 1, the current through the NMOS transistors M 1  and M 2  must be adjusted to compensate for the changes in the transistors parameters due to the variations in the environmental factors such as process, temperature, and applied voltage. In the first embodiment of this invention, the current of the biasing current source I B  is adjusted as the environmental factors change. In the second and third embodiments of this invention, the current of the current source I B  is held as a constant value. A compensation current is added or subtracted with the biasing current source I B  of the NMOS transistors M 1  and M 2 . As the environmental factors change, the parameters such as mobility of the NMOS transistors M 1  and M 2  and the resistivity of the resistors RL 1 , RL 2 , Rs 1 , and Rs 2  change. The compensation current is inversely varied to counteract these effects of the change in the parameters of the NMOS transistors M 1  and M 2  such that the gain of the high gain, high frequency amplifier remains essentially constant. 
     Refer now to FIG. 3 for a description of a bias current generator of the first and principal embodiment of this invention. The master current source I 0  is the reference current source that provides the controlling current for the current sources I 1 , I 2 , I 3 , and I′ 2  that are mirrored from the reference current source I 0 . The current source  11  is coupled to supply the controlling current to the voltage reference generator V REF . The voltage reference generator V REF  produces the reference voltages V REF1  and V REF . 
     The reference voltages V REF1  and V REF2  are the inputs to the differential amplifier DA 1 . The differential amplifier DA 1  is structured as shown in FIG. 1 having similar device geometries and resistance values. The biasing current  18  of the differential amplifier DA 1  is supplied by the current source I 2 . The output nodes N 1  and N 2  are the inputs to the operational amplifier OA 1 . The current source I 3  is connected to the output node N 2  to provide a biasing current the adjusts the voltage level of the output node N 2 . The output of the operational amplifier is connected to a voltage-to-current converter VI 1 . The voltage output of the operational amplifier OA 1  is converted and scaled to a current value within the voltage-to-current converter VI 1 . The compensation current I CT  from the voltage-to-current converter VI 1  is subtracted from the constant current I 2  to form the biasing current I B  for the differential amplifier DA 1 . The compensation current I CT  provides the feedback to adjust the biasing current I B  of the differential amplifier DA 1 . This, in turm, adjusts the voltage at the output nodes N 1  and N 2  by changing the amplification factor of the differential amplifier DA 1 . 
     Any changes in the environmental factors cause the voltage at the output nodes N 1  and N 2  to be different. The compensation current I CT  causes the biasing current I B  to readjust such that the voltages at the output nodes N 1  and N 2  are brought to the same level. This, as shown hereinafter, ensures that the gain of the operational amplifier DA 1  remains constant. 
     In the first embodiment, as explained above, the biasing currents of the differential amplifier stages are modulated to stabilize the gain of the differential amplifier stages as the environmental factors change. In FIG. 5, the high gain, high frequency amplifier is structured and functions as shown in FIG. 2 with the exception the current sources I B1 , I B2 , and I B3  are now incorporated to the gain compensation circuit of this invention. The junction of the resistors RS 3  and RS 4 , the junction of the resistors RS 5  and RS 6 , and the junction of the resistors RS 7  and RS 8  are connected respectively to the nodes N 3 , N 4 , and N 5  that are connected to the gain compensation circuit of this invention. The gain compensation circuit provides the modulated biasing currents I B4 , I B5 , and I B6 . 
     Returning to FIG. 3, the nodes N 3 , N 4 , and N 5  are connected to the current mirror IM 1 , which sinks the modulated biasing currents modulated biasing currents I B4 , I B5 , and I B6 . To generate the modulated biasing currents I B4 , I B5 , and I B6 , the output of the operational amplifier OA 1  is the input to the voltage-to-current converter VI 2 . The voltage-to-current converter VI 2  is connected to the current source I′ 2  and the output of the replica differential amplifier stage DA 2 . The replica differential amplifier stage DA 2  is structured to be equivalent to the differential amplifier DA 1  and has it input connected to the voltage reference generator V REF  to receive the reference voltages V REF1  and V REF2 . The current source I′ 2  is designed to provide a current substantially equal to the current source I 2 . The second compensation output current I′ CT  of the voltage-to-current converter VI 2  is substanially equal to the compensation current I CT , thus the bias current I′ B  is forced to be equal to the bias current I B , which has been adjusted to compensate for variations due to the environmental factors. The biasing current I′ B  is the controlling current for the current mirror IM 1 . The modulated biasing currents I B4 , I B5 , and I B6  are thus dependent upon the biasing current I′ B . 
     Refer now to FIG. 4 for a more detailed description of the gain compensation circuit of this invention. The NMOS transistors M 5 , M 6 , M 7 , M 8 , and M 15  are structured to form a current mirror with the control current being the current source I 0 , and the currents I 1 , I 2 , I 3 , and I′ 2  being mirrored from the control current I 0 . The resistors R 1  and R 2  are connected serially to form a voltage divider. The voltage drop (I 1 R 2 ) across the resistor R 1  determines the reference voltages V REF1  and V REF2 . 
     The differential amplifier DA 1  is formed by the transistors M 3  and M 4 , the source degeneration resistors RS 9  and RS 10 , and the load resistors RL 9  and RL 10  arranged as shown in FIG.  1 . The NMOS transistor M 7  with the NMOS transistor M 5  form the current source I 2  for the differential amplifier DA 1 . The output node N 1  is the junction of the drain of the NMOS transistor M 3  and the load resistor RL 9 . Similarly, the output node N 2  is formed at the junction of the drain of the NMOS transistor M 4  and the load resistor RL 10 . The operational amplifier OA 1  is formed of the single stage differential amplifier A 1 , the capacitors C C1  and C C2 , and the resistors R C1  and R C2 . The capacitors C C1  and C C2 , and the resistors R C1  and R C2  form a compensation network for the differential amplifier A 1 . The noninverting input of the amplifier A 1  is connected to the output node N 1  of the differential amplifier DA 1  and the inverting input of the amplifier A 1  is connected to the output node N 2  of the differential amplifier DA 1 . 
     The current source I 3  is formed by the NMOS transistor M 8  with the NMOS transistor M 5  and is connected to the inverting input (node N 2 ) of the amplifier A 1 . The voltage at the Node N 2  thus changed by the amount equal to RL 10 I 3 . 
     The PMOS transistors M 9  and M 10  respectively form the voltage-to-current converters VI 1  and VI 2 . The PMOS transistors M 9  and M 10  have identical aspect ratios to insure that the compensation currents are I CT  and I′ CT  are essentially equal. The current I CT  is fed back to form the bias current I B  after the subtraction from the current I 2 . 
     The replica differential amplifier DA 2  is formed by the NMOS transistors M 11  and M 12 , and source degeneration resistors RS 11  and RS 12  arranged as shown in FIG.  1 . The load resistors are replaced by the active load configured PMOS transistor M 13 . The NMOS transistor M 15  with the NMOS transistor M 5  form the current source I′ 2  for the replica differential amplifier DA 2 . 
     As is known in the art the active load formed by the PMOS transistor M 13  is essentially a current source. The PMOS transistor M 14  is connected to mirror the current I′ B . The PMOS transistor M 14  and the NMOS M 16  form the controlling current source for the current mirror IM 1  that generates the bias currents I B4 ,  1   B5 , and I B6 . The current through the PMOS transistor M 14  and the NMOS M 16  designed to be essentially equal to the current I′ B . The NMOS transistors M 17 , M 18 , and M 19  are structured respectively to the current sources to sink the bias currents I B4 , I B5 , and I B6 . 
     A negative feedback loop is formed with differential amplifier DA 1 , resistors R 1  and R 2 , operational amplifier A 1 , the voltage-to-current converter VI 1 . The negative feedback loop forces the nodes N 1  and N 2  to the same DC potential. 
     The discussion presented hereinafter describes the function of the negative feedback loop and its operation to compensate for the variation in the environmental factors of temperature, process and power supply variations. The reference voltages V REF1  and V REF2  as created by the voltage drop I 1 R 2  across the resistor R 2  causes a voltage difference between the nodes N 1  and N 2 . The node N 2  is at a higher potential, because of amplification by differential amplifier DA 1  is equal to g ms R L  as shown in Eq. 1. Since the drop across resistor R 2  is fixed, the amount by which the potential at the node N 2  is higher compared that at the node N 1  depends on the magnitude of effective transconductance g ms  only. However, the operational amplifier A 1  is only sensitive to the difference of potentials at nodes N 1  and N 2 . Therefore, the discussion can be simplifier by assuming the voltage level at the node N 1  is fixed at zero potential. The potential at the node N 2  increases with the transconductance g ms  in the positive direction. On the other hand, the current I 3  acts to decrease the voltage potential at the node N 2 . 
     The examination of the feedback loop begins by assuming that the node N 2  is at a positive voltage potential. This voltage potential will be amplified by the amplifier A 1  which will, in turn, will cause the gate of the PMOS transistor M 9  to go low causing the latter&#39;s drain current (the compensation current) I CT  to increase. It can be observed from the circuit that the bias current I B  of differential amplifier DA 1  is actually the difference of current I 2  through the current source formed by the NMOS transistor M 7  and the compensation current I CT . Since the current I 2  is fixed, the bias current I B  reduces as the compensation current I CT  increases, reducing the effective transconductance g ms  in turn. This reduction in the effective transconductance g ms  causes the potential at the node N 2  to decrease until it becomes zero. Conversely, assume that the node N 2  is at a negative voltage potential. This time the amplifier A 1  will cause the gate of the PMOS transistor M 7  to go high causing its drain current (compensation current) I CT  to reduce. Consequently, bias current I B  increases, increasing effective transconductance g ms  and this increases the voltage potential at node N 2  until it becomes zero again. Thus, if the feedback loop is designed correctly, the potentials at the nodes N 1  and N 2  remain virtually equal under steady state conditions. 
     The absolute voltages V N1  and V N2  at nodes N 1  and N 2  are respectively determined by the following equations as:                V   N1     =       V   DD     -       (           g   ms          R   L          I   1          R   2       2     +         I   B          R   L       2       )                   and               Eq   .              3                 V   N2     =       V   DD     -     (       -         g   ms          R   L          I   1          R   2       2       +         I   B          R   L       2       )     -       I   3          R   L                 Eq   .              4                                
     The feedback loop, under steady state conditions ensure that the absolute voltages V N1  and V N2  at nodes N 1  and N 2  are essentially equal. Thus combining equations Eq. 3 and Eq. 4 the effective transconductance g ms  is determined by the equation.                g   ms     =         I   3       I   1            1     R   2                 Eq   .              5                                
     The equation Eq. 5 demonstrates the effect of the feedback loop in determining the transconductance g ms  in terms of resistance R 2 . 
     Without disturbing the feedback loop, several replicas of the bias current I B  are generated using replica biasing and mirroring with voltage-to-current converter VI 2  and the current mirror IM 1 . The voltage gains of the differential amplifier stages AV 1 , AV 2 , and AV 3  are determined by the combination of the equations Eq. 2 and Eq. 5 to become:                A   vN     =         g   ms          R   LN       =         I   3       I   1              R   LN       R   2                   Eq   .              6                                
     The currents I 1  and I 3  track each other as they are generated from the same current source I 0  by mirroring. If the resistors RL 3 , RL 4 , RL 5 , RL 6 , RL 7 , and RL 8  in FIG. 5 are of the same type as R 2  in FIG. 3 then, equation Eq. 2 it can be shown that the voltage gains A vN  of the individual differential amplifier stages are independent of variations in the environmental factors of process, temperature, and power supply voltage. Physically, the master bias current I B  changes with the above variations adjusting g ms  such a manner that the amplifier voltage gain A vN  remains constant. 
     Simulation using the known H-spice simulation program found that a high gain, high frequency amplifier of the prior art has a gain of 55 dB+/−10 dB. Whereas, the high gain, high frequency amplifier employing the gain compensation circuit of this invention improves the gain variation to 55 dB+/−2 dB@190 MHz over the process corners and a temperature range of −35° C. to +85° C. with compensation. 
     Referring now to FIGS. 8 and 11, the high gain, high frequency amplifier is structured and functions as shown in FIG.  2 . The modulation of the biasing current for each of the differential amplifier stages AV 1 , AV 2 , and AV 3  is a result of the addition (FIG. 8) or subtraction (FIG. 11) of the compensation currents I CT1 , I CT2 , I CT3  of FIG.  8  and the compensation currents I CT4 , I CT5 , I CT6  of FIG. 11 from or to the biasing current sources I B1 , I B2 , and I B3 . 
     As shown in FIG. 6, the second embodiment of the gain compensation current of this invention has the voltage reference generator V REF , the differential amplifier DA 1 , the operational amplifier OA 1 , the voltage-to-current converter VI 1 , and the current sources I 1 , I 2 , and I 3  form the feedback loop as described for FIG.  3 . The voltage-to-current converter VI 2  is now connected directly to the current mirror circuit IM 2 . The current mirror circuit IM 2  sinks the compensation currents I CT1 , I CT2 , I CT3 . The compensation currents I CT1 , I CT2 , I CT3  are adjusted as described above where the compensation current I CT  varies as the environmental factors vary. In this embodiment the voltage-to-current converters VI 1  and VI 2  are designed to ensure the compensation current I CT  and the compensation currents I CT1 , I CT2 , I CT3  are equal or proportional to each other over any variation of the environmental factors. 
     Refer now to FIG. 7 for a more detailed discussion of the second embodiment of the gain compensation circuit of this invention. The output current I err  of the voltage-to-current converter VI 1  (the drain of the PMOS transistor M 9 ) is the input to the feedback current mirror IMFB. The output of the feedback current mirror IMFB sinks the compensation current I CT . The NMOS transistors M 42  and M 43  are configured as a current mirror such that the output current I err  of the voltage-to-current converter VI 1  is the control current for the compensation current I CT . 
     The output current I′ err  of the second voltage-to-current converter VI 2  is the control current for the current mirrors that the sink the compensation currents I CT1 , I CT2 , I CT3  and is substantially equal to the output current I err . These currents are added to the bias currents I B1 , I B2 , and I B3  of FIG. 8 respectively. These currents are adjusted as described above by stabilizing the balance between the bias current I B  and the compensating current I CT  as described above. The NMOS transistors M 45 , M 47 , M 48 , and M 49  are configured to form the current mirror IM 2  which functions as current mirror IM 1  of FIG. 4 except the level of the currents are at the level of compensation current rather than the biasing currents. Even though only the compensation currents I CT1 , I CT2 , I CT3  are provided, the gain of the differential amplifier stages AV 1 , AV 2 , and AV 3  is as calculated in Eq. 6. 
     As shown in FIG. 9, the third embodiment of the gain compensation current of this invention also has the voltage reference generator V REF , the differential amplifier DA 1 , the operational amplifier OA 1 , the voltage-to-current converter VI 1 , and the current sources  1   1 , I 2 , and I 3  form the feedback loop as described for FIG.  3 . The voltage-to-current converter VI 2  is now connected to the current mirror circuit IM 3 . The current mirror circuit IM 3  sinks the compensation currents I CT4 , I CT5 , I CT6 . These currents are subtracted to the bias currents I B1 , I B2 , and I B3  of FIG. 11 respectively. The compensation currents I CT4 , I CT5 , I CT6  are adjusted as described above where the compensation current I CT  varies as the environmental factors vary. In this embodiment the voltage-to-current converters VI 1  and VI 2  are designed to ensure the compensation current I CT  and the compensation currents I CT4 , I CT5 , I CT6  are equal or proportional to each other over any variation of the environmental factors. 
     Refer now to FIG. 10 for a more detailed discussion of the third embodiment of the gain compensation circuit of this invention. The output current I err  of the voltage-to-current converter VI 1  (the drain of the NMOS transistor M 62 ) is the input to the feedback current mirror IMFB. The output of the feedback current mirror IMFB sinks the compensation current I CT . The NMOS transistors M 64  and M 65  are configured as a current mirror such that the output current I err  of the voltage-to-current converter VI 1  is the control current for the compensation current I CT . 
     The output current I′ err  of the second voltage-to-current converter VI 2  is the control current for the current mirrors that source the compensation currents I CT4 , I CT5 , I CT6  and is substantially equal to the output current I err . These currents are adjusted as described above by stabilizing the balance between the bias current I B  and the compensating current I CT  as described above. The PMOS transistors M 66 , M 67 , M 68 , and M 69  are configured to form the current mirror IM 2  to provide the level of the currents at the level of compensation current rather than the biasing currents. Even though only the compensation currents I CT4 , I CT5 , I CT6  are provided, the gain of the differential amplifier stages AV 1 , AV 2 , and AV 3  is also as calculated in Eq. 6. 
     As is evident from the second and third embodiment, other configurations of the gain compensation circuit of this invention are possible by substituting PMOS transistors for NMOS transistors and NMOS transistors for PMOS transistors. While this invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.