Abstract:
Circuitry for detecting and correcting errors in data words occurring in Reed-Solomon coded blocks contains a plurality of stages. One stage constructs syndromes in the data flowing through the blocks. Another stage detects erasures in the syndromes. Another stage applies a Euclid&#39;s algorithm with 
     
       T.sub.s (x)={Q.sub.s-1 (x)·T.sub.s-1 (x)}+T.sub.s-2 (x), 
     
     
       R.sub.s (x)={Q.sub.s-1 (x)·R.sub.s-1 (x)}+R.sub.s-2 (x), 
     
     and 
     
       I Q.sub.s-1 (x)=R.sub.s-2 (x)/R.sub.s-1 (x) 
     
     wherein T s  (x), R s  (x), and Q s-1  (x) are polynomials representing the position of the error, its value, and a provisional value respectively, and R s  (x) and T s  (x) can be normalized with a minimal coefficient T s  (0)=δ such that R(x)=R s  (xi/δ and T(x)=T s  (x)/δ. Another stage detects error positions X k  and values Y k  by conducting a Chien zero-root search in conjunction with ##EQU1## wherein T&#39;(X k ) is the first derivative of T at a place x k . Another stage uses the accordingly calculated error positions X k  and values Y k  to correct signal-duration matched data words in a currently occurring Reed-Solomon coded block. when the two counts are equal. An exclusive-OR stage has one input terminal which receives the error value at the top of the fourth stack in accordance with the control signal, another input terminal which receives the signal-duration matched data words, and an output terminal that emits corrected data words.]

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to circuitry for detecting and correcting errors in data words occurring in Reed-Solomon (RS) coded blocks. The circuitry comprises a stage that constructs syndromes (defined hereinafter) in the data flowing through the blocks; a stage that detects erasures in the syndromes; a stage that applies a Euclid&#39;s algorithm with 
     
         T.sub.s (x)={Q.sub.s-1 (x)·T.sub.s-1 (x)}+T.sub.s-2 (x), 
    
     
         R.sub.s (x)={Q.sub.s-1 (x)·R.sub.s-1 (x)}+R.sub.s-2 (x), 
    
     and 
     
         Q.sub.s-2 (x)=R.sub.s-2 (x)/R.sub.s-1 (x), 
    
     wherein T s  (x) , R s  (x) , and Q s-1  (x) are polynomials representing the position of the error, its value, and a provisional value respectively, and wherein R s  (x) and T s  (x) can be normalized with a minimal coefficient T s  (0)=δ such that R(x)=R s  (x)/δ and T(x)=T s  (x)/δ; a stage that detects error positions X k  and values Y K  by conducting a Chien zero-root search in conjunction with ##EQU2## wherein T&#39; (X k ) is the first derivative of T at a place X k  ; and a stage that uses the accordingly calculated error positions X k  and values Y K  to correct signal-duration matched data words in a currently present Reed-Solomon coded block. A Reed-Solomon code is a systematic block code of length n wherein n-k=p checkwords are applied to k information symbols. The coding does not alter communications symbols. A Reed-Solomon code has a minimal Hamming distance d=p+1, that can be freely selected to detect and correct errors. 
     Decoding does not differentiate between data words and checkwords. A Reed-Solomon code block consists of n symbols, each of one or more bits. A symbol width of 8 bits is usually the starting point. 2·t checkwords are usually needed in correcting a symbol error t to calculate its position X i  and value Y i . If the defective symbol is marked as an erasure, its error position X i  will be known. In this event only a single checkword will be needed to calculate error value Y i . In Reed-Solomon codes, 2t+e ≦P=n-k=d-1, wherein i is the number of erasures. Further details on Reed-Solomon codes can be found in &#34;On-the-Fly Decoder for Multiple Byte Errors,&#34; IBM Journal of Research and Development, vol. 30, No. 3 (May 1986), pp. 259-69. 
     Circuitry for decoding Reed-Solomon coded data is known from &#34;A 40 MHz Encoder/Decoder Chip Generated by a Reed-Solomon Code Compiler,&#34; IEEE 1990 Custom Integrated Circuits Conference, CH2860-5/90/0000-0065, pp. 13.5.1-13.5.4. One stage calculates syndromes from the data received in a transmission section. A downstream stage calculates the polynomial error positions and values from the calculated syndrome in accordance with Euclid&#39;s algorithm. The results are subjected to a Chien zero-root search in a third stage. The resulting positions and values are employed in a fourth stage to correct the occurring data with an exclusive OR. 
     Such circuitry cannot be employed to correct a large number of errors in real time. 
     SUMMARY OF THE INVENTION 
     The principal object of the present invention is to improve circuitry of the aforesaid type to the extent that it can correct data arriving at a constant and high rate, higher than 40 MBit/sec for example, in real time. 
     This object, as well as other objects that will become apparent from the discussion that follows are achieved in accordance with the invention by the improvement comprising: 
     a forwards counter for counting up the data words in one block and emitting a target value (X i ) simultaneously with the Chien zero-root detection; 
     a first stack for storing the counts (X i ) that can be extracted from it at the end of each data block; 
     a second stack controlled by a signal for storing the counts (X k ) extracted from the first stack; 
     a third stack for storing, simultaneously with the storage of the counts in the first stack, error values (Y i ) that can be extracted from it at the end of a data block; 
     a fourth stack controlled by a signal for storing the error values extracted from the third stack; 
     a backwards counter for counting down from the value of one block length; 
     a comparator for comparing whatever count is at the top of the second stack with the counts emitted by the backwards counter in order to derive a control signal when the two counts are equal; and 
     an exclusive-OR stage with one input terminal coupled to receive the error value (Y k ) at the top of the fourth stack in accordance with the control signal, with another input terminal coupled to receive the 
     signal-duration matched data words, and with an output terminal that emits corrected data words. 
     One advantage of the circuitry in accordance with the invention with its several stacks is that any number of errors can be corrected in real time. A particular advantage is that the correction operations can be carried out &#34;self-controlled.&#34; 
     The forwards counter in one embodiment includes a multiplexer and a downstream register, whereby a value α 0  =1 is forwarded to one input of the multiplexer at the beginning of a block and the values emitted by the register are multiplied by another value α 1  and forwarded to another of the multiplexer&#39;s inputs at other times. 
     The backwards counter in another embodiment includes another multiplexer and another downstream register, whereby the value of one block length is forwarded to one input terminal of the multiplexer at the beginning of a block and the values emitted by the register are forwarded to another of the multiplexer&#39;s input terminals at other times. 
     The preferred embodiments of the present invention will now be described with reference to the accompanying drawing. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is an overall block diagram of a known Reed-Solomon decoder 
     FIG. 2 is a detailed block diagram of the Chien zero-root search stage in accordance with the invention as applied to the equipment illustrated in FIG. 1, and 
     FIG. 3 is a detailed block diagram of the correction stage in accordance with the invention as applied to the equipment illustrated in FIG. 1. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Every symbol of m bits in a Reed-Solomon code is by definition an element of a Galois field GF(2 m ). The sequence of 2 m  symbols is defined as the basis of the finite field arithmetic by a field-generator polynomial p(x). The symbol width limits the maximal block length of an Reed-Solomon code of 2 m  -1 in that the elements of the field are needed for an unambiguous position number in the block. A zero is a neutral element with respect to addition and an α 0  =1 a neutral element with respect to multiplication. A field is accordingly defined over an irreducible field-generator polynomial. Once a primitive element α of place number m has been defined, all subsequent elements can be expressed as powers of α. Since α is a root of field-generator polynomial p(x) and since there are only m non-zero roots, p(x)=0 for all other elements. A Galois field can accordingly be defined as a finite sequence of 2 m  -1 elements. A binary representation allows simple addition by way of a bit-wise exclusive-OR, and an exponential representation simple multiplication by adding the exponents modulo q=r m  -1. In circuitry terms, this corresponds to a binary adder with its carry-over output terminal communicating with a carried-over input terminal. 
     A Reed-Solomon code of distance d over the field generated by field-generator polynomial p(x) is defined by a code-generator polynomial ##EQU3## 
     Although b=0 here, it can be any constant in field GF(2 m ). A lawful code vector c(x) is constructed by shifting an information vector i(x)·x p  by p places, dividing it by code-generator polynomial G(x), and attaching the resulting parity vector p(x) to the now unoccupied places in information vector i(x). Code vector c(x) can be evenly divided by all the roots of code-generator polynomial G(x). 
     A carried-over Reed-Solomon coded code block c(x) consists as previously mentioned of k information places followed by p checkwords. Such a code ensures that c(x) can be evenly divided by all roots of code-generator polynomial G(x) as long as there are no errors e(x) or erasures u(x). Developing a reception vector r(x) at the roots of code-generator polynomial G(x) will produce values that depend on the errors received but not on the information vectors i(x) carried over. These values are called syndromes. The m syndromes S j  (j=0, . . . , [d-2]) are calculated from the equation: ##EQU4## 
     The intercepted vector (x) can be represented by the polynomial 
     
         r(x)=r.sub.n-1 x.sup.n-1 +r.sub.n-2 x.sup.n-2 r.sub.1 x.sup.1 r.sub.0 
    
     wherein x is a position in the polynomial for each intercepted symbol r 1 . The first intercepted (data) symbol is r n-1  and the last (parity) symbol is r 0 . The polynomial can be stored by way of its coefficients r i  alone. 
     Since the development of an error-free interception vector r(x) at a zero place in the code-generator polynomial supplies the value 0, the values of the syndromes are to be considered sums of the position-weighted errors Y K  at places X k . The symbols constitute remainders from a division of data flow r(x) by all factors (x+α i ) in the code-generator polynomial, whereby ##EQU5## (for all syndromes S 0 , . . . , S d-2  where b=0). 
     When the position of an event X k  is retained during an erasure, up to e=p erasures can be calculated with p syndromes and p error positions X k  as long as 2t+e≦p, wherein t is the number of unidentified errors. 
     Since the syndromes constitute in accordance with the equation a set of n non-linear equations, p solutions can be obtained. The solutions to this system of equations are coefficients of an error-position polynomial that has a value of 0 at the error positions. 
     The decoding of Reed-Solomon coded data blocks in accordance with the aforesaid Euclid&#39;s algorithm is described in &#34;Simplified Procedure for Correcting Both Errors and Erasures of RS Code Using Euclid Algorithm,&#34; by Truong Eastman Reed Hsu, IEEE Proceedings, Vol. 135, Pt. E, No. 6 (November 1988). The Euclid&#39;s algorithm can be broken down into the following steps: 
     1. Calculating a syndrome S j  and an erasure-position polynomial L(x) and setting e=deg L(x), 
     2. Calculating what is called a Forney syndrome τ(x)=S(x)L(x) mod x d-1 , and 
     3. Setting T(x)=L(x) and R(x)=τ(x) for e=d-1=p and otherwise determining T(x) and R(x) with a Euclid&#39;s algorithm comprising the recursive formulas: 
     
         T.sub.s (x)={Q.sub.s-1 (x)·T.sub.s-1 (x)}+T.sub.s-2 (x), 
    
     
         R.sub.s (x)={Q.sub.s-1 (x)·R.sub.s-1 (x)}+R.sub.s-2 (x), 
    
     and 
     
         Q.sub.s-1 (x)=R.sub.s-2 (x)/R.sub.s-1 (x) 
    
     with the initial values 
     
         T.sub.0 (x)=L(x), 
    
     
         T.sub.-1 (x)=0, 
    
     
         R.sub.-1 (x)=x.sup.d-1, 
    
     and 
     
         R.sub.0 (x)=τ(x). 
    
     T s  (x), R s  (x), and Q s-1  (x) are polynomials representing the position of the error, its value, and a provisional value respectively. R s  (x) and T s  (x) can be normalized with the minimal coefficient T s  (0)=δ, whereby R(x)=R s  (x)/δ and T(x)=T s  (x)/δ. R(x) and T(x) are the results of the Euclid&#39;s algorithm. 
     The roots of T(x) are inverse (down-counted) positions of errors and erasures X k   -1 . The individual error positions X k   -1  are located in the present embodiment by a Chien zero-root search. The procedure simultaneously determines error values Y k  from ##EQU6## T&#39; (X k ) is the first derivative of T at a place X k . The derivatives of polynomials are constructed in finite fields, with n-fold addition yielding 0 for even n and the element itself for odd n. The procedure will accordingly determine the desired error position and its corresponding error value. 
     FIG. 1 is an overall block diagram of a Reed-Solomon decoder. A data bus 1 conveys 8-bit wide data words D in  in Reed-Solomon coded data blocks to both a delaying stage 2 and a function stage 3, which essentially constructs syndromes. Paralleling data bus 1, an error signal EF in  is forwarded to delaying stage 2 and function stage 3 over a line 4. 
     The syndromes are calculated in function stage 3 with 16 syndrome generators that construct the remainder of a division c(x)/(x+α i ). The syndrome generators are initiated at the beginning of each block by separating a feedback through an AND gate. The syndromes from the last block are forwarded at the same rate to a function stage 5 that determines erasures in accordance with the aforesaid Euclid&#39;s algorithm. A generator in the same stage detects erasure positions L(x) by counting through all the positions in the block. When an erasure appears, it&#39;s position is stored in an empty register. The registers are also zeroed at the beginning of a block. When more erasures appear than are permitted by a correction ceiling, L(x) is set at 0. In this case, limited error correction can be attempted. Erasure vector L(x) is inverted in function stage 5 over the length of a block. 
     Function stage 5 comprises several banks of registers with widths of 16 and 17 bytes. Since the functionality of this stage is in itself well known, it need not be discussed herein in detail. The aforesaid error-position polynomials T s  (x) and error-value polynomials R s  (x) are constructed by polynomial division and addition and can be obtained at the output terminals of function stage 5. 
     The zero roots of polynomials T s  (x) and R s  (x) are determined in downstream function stages 6 and 7, which will be described in detail hereinafter with reference to FIGS. 2 and 3. Defective data words, which have been forwarded along with the error signal from the output terminal of delaying stage 2 to function stage 7, are corrected from the resulting error values Y k  and error positions X k . Control of the four function stages 3 through 7, as well as the delaying stage 2, is effected by an RS decoder control unit 8. The output of the function stage 7, a stream of 8-bit wide data words D out , can be taken from a bus 9. Any defective words will be corrected in accordance with the corrective capability of the particular decoder employed. Data blocks that exceed the capability of the decoder are characterized by an error signal EF out  that, paralleling the data emitted over data bus 9, is shifted to a line 10. 
     The function stage 6 shown in FIG. 1 is illustrated in detail in FIG. 2. The polynomials obtained from function stage 5 are in the present embodiment forwarded to the thirty-three components of a cyclic decoder 11. The structure of one such component is illustrated by the block diagram inside the dot-and-dash lines in the bottom right corner of the figure. The signals representing the polynomial are loaded at the beginning of the block in a register 13 by way of a multiplexer 12. Each element R i  or T i  is constantly cyclically multiplied by symbols α -i  available in a subsidiary stage 14. If a zero root T(x) is discovered--if, that is, the sum of all elements T i  is 0--the error value can be calculated from Y k  =R(x k )/T&#39;(x k ) for the case where b=0. 
     The derivative T&#39;(x) provides, in accordance with the laws of a Galois field, the polynomial of the even coefficients of T. Cyclic decoders of this type are known from the hereintofore cited IBM Journal of Research and Development. Vol. 30, No. 3 (May, 1986), pp. 259-69. 
     The signals from the individual cyclic decoders are added in stages 15, 16, and 17. The sums VAL, EVENSUM, and ODDSUM at the output terminals of these stages constitute an exclusive-OR gate for all the bits in one plane. In the present case for example, bit 0 is constructed from VAL by way of a 16-fold conjunction of bits 0 from R 0  to R 15 . A division R/T&#39; is carried out by multiplying the inverses in stages 18 and 19. EVENSUM and ODDSUM are added in a stage 20. A zero poll is conducted in stage 21. If the FOUND signal at the output terminal of stage 21 has a HIGH level, the output from a position counter comprising a multiplexer 22, a register 23, and a stage 24 is stacked along with the resulting error value Y k  in a stack 25 that stores error positions X i . It is assumed in the present case that the stack comprises 16 registers. The stacking occurs in a register 0, while the previous contents of registers 0 through 14 move up one step to registers 1 through 15. The contents of register 15 are lost. The stack operates last-in first-out (LIFO) in that the Chien procedure calculates inverse error positions backwards. Another stack 26 operates in parallel with first stack 25 and stores error values Y i . 
     FIG. 3 is a block diagram of function stage 7. It has one stack 27 for error positions X k  and another stack 28 for error values Y k . These factors are taken over at the end of a data block along with the factors in stacks 25 and 26. The circuit illustrated in FIG. 2 can accordingly be re-initialized and will be available for another Chien search. 
     The order of error positions X k  and error values Y k  is reversed with an inverse position counter consisting of a multiplexer 29, a register 30, and a stage 31. Multiplexer 29 loads register 30 with the final block-length value at the beginning of a block. The outputs from register 30 are at other time fed back with, and multiplied by the values of the symbols α -1  by way of stage 31. An error position X k  is located when the data emitted from the inverse position counter is identical with the contents of a register 0 in stack 27. The comparison is carried out in a comparator 32, which emits a FOUND signal in the form of an entry pulse for an AND gate 33. Gate 33 is connected to another output terminal of stack 28. The error value Y K  at the output terminal of AND gate 33 is logically added to data value D in , which has been delayed in delaying stage 2, in an exclusive-OR stage 34, accordingly carrying out the correction. The error signal EF in  arrives, also delayed by delaying stage 2, at an outgoing line 10 by way of a stage 35 and subject to the Reed-Solomon decoder&#39;s controls 8. If there is a logical HIGH level in the FOUND signal, the uppermost factor in stacks 27 and 28 is removed and their registers 1 through 15 will be copied onto register positions 0 through 14. Once all the errors have been corrected, there will be a logical 0 on the stack, in which event no further coincidence with the inverse position counter may occur. 
     The circuitry in accordance with the invention accordingly features in addition to the aforesaid advantages the advantage that no special operating controls are needed to handle any desired number of errors because it is self-controlled by the factors in stack 27. All that is necessary is to load the inverse position counter with a block length at the beginning of a block in order to subsequently count down cyclically. The procedure is equivalent to multiplication by α -1 . When erasures are also corrected in the circuitry in accordance with the invention, the error signal must be delayed in the form of a ninth bit along with the data. Such erasures can also result from drop-out. Otherwise it will be sufficient to delay the arriving data signal D in  at a word width of 8 bits. Controls 8 will modify the delayed error signal EF in  such that a correct status for each data bit obtainable at the output terminal of exclusive-OR stage 34 will be simultaneously available on line 10. The present pipeline processing allows a continuous operating speed of 0 to 20 MHz at a symbol width of 8 bits. The present embodiment supports a Reed-Solomon code with 1 to 16 checkwords. There has thus been shown and described novel circuitry for detecting and correcting errors in data words that fulfills all the objects and advantages sought therefor. Many changes, modifications, variations, and other uses and applications of the subject invention will, however, become apparent to those skilled in the art after considering this specification and the accompanying drawings, which disclose the preferred embodiment thereof. All such changes, modifications, variations, and other uses and applications that do not depart from the spirit and scope of the invention are deemed to be covered by the invention, which is to be limited only by the claims that follow.