Abstract:
A control circuit controls a switch of a switching current converter receiving an input quantity, with a transformer having a primary winding and a sensor element generating a sensing signal correlated to a current in the primary winding. The control circuit has a comparator stage configured to compare a reference signal with a comparison signal correlated to the sensing signal and generate an opening signal for the switch. The comparator stage has a comparator element and a delay-compensation circuit. The delay-compensation circuit is configured to generate a compensation signal correlated to the input quantity and to a propagation delay with respect to the opening signal. The comparator element generates the opening signal with an advance correlated to the input quantity and to the propagation delay.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure relates to a current converter with control of the current on the primary winding side and compensation of the propagation delay. In particular, the present disclosure regards a converter that may be used in a power supply aimed at the market of solid-state-lighting (SSL) apparatus, and more in particular to apparatus comprising lamps including arrays of light-emitting diodes (LEDs). 
         [0003]    2. Description of the Related Art 
         [0004]    Offline-driving power supplies of lighting apparatus that use LEDs comprise a control circuit and a transformer for maintaining a safety insulation between the control circuit and the load (LEDs). In these circuits, it is frequently desirable to regulate the d.c. output current used for driving the LEDs without making use of feedback circuits that use signals acquired on the secondary-winding side. In this way, on the secondary side of the transformer, there is no need of current-detection elements, reference-voltage sources or error amplifiers, nor possible optical couplers for transferring the error signal to the control circuit arranged on the primary side. Frequently, a high power factor (Hi-PF, higher than 0.9) is further desirable in order to meet the emission limits of current harmonics (according to the standards IEC 61000-3-2 in Europe and JEITA-MITI in Japan). 
         [0005]    In order to obtain the above characteristics, switching converters of a Hi-PF flyback type are known, which are made, for example, according to the circuit scheme of  FIG. 1  (see also C. Adragna “Primary-Controlled High-PF Flyback Converters Deliver Constant Dc Output Current” Europe Power Electronics Conference, September 2011, which are referred to for further details). 
         [0006]      FIG. 1  shows a power supply  1  including a bridge rectifier  2  and a flyback converter  3 . 
         [0007]    The bridge rectifier  2  has two input terminals  10   a,    10   b,  designed to receive an a.c. supply voltage V ac  at a frequency f L , and two output terminals supplying an input voltage V in (θ), where θ is the phase of the supply voltage V ac . The output terminals of the bridge rectifier  2  are connected to a first reference potential line (first ground  12 ) and to an input node  13 , respectively. 
         [0008]    The flyback converter  3  comprises a filtering capacitor C in , connected between the input node  13  and the first ground  12  and operating as high-frequency smoothing filter; a transformer  4  including a primary winding L p , a secondary winding L s , and an auxiliary winding L aux ; a control module  15 ; a resistive divider  16  including a first dividing resistor R a  and a second dividing resistor R b ; a power switch M, formed by a power transistor, for example a MOSFET; an auxiliary sensing resistor  21 , having a resistance R aux ; a primary sensing resistor  19  having a resistance R s ; and a clamping circuit  20 . 
         [0009]    In detail, the primary winding L p  of the transformer  4  has a first terminal  4   a  connected to the input node  13  and a second terminal  4   b.  The secondary winding L s  has a first terminal  4   c  and a second terminal  4   d,  the latter connected to a second reference potential line (second ground  17 ). The auxiliary winding L aux  has a first terminal  4   e  connected to the first ground  12  and a second terminal  4   f.  The primary, secondary and auxiliary windings L p , L s , L aux  are coupled together as illustrated in  FIG. 1 , with positive terminals  4   b,    4   c,  and  4   f.    
         [0010]    The first dividing resistor R a  is connected between the input node  13  and an intermediate node  14 . The second resistor R b  has a first terminal connected to the intermediate node  14  and a second terminal connected to the first ground  12 . The intermediate node  14  is coupled to a first input terminal MULT of the control module  15  and supplies a first voltage signal A(θ) proportional to the input voltage V in (θ) through the dividing ratio K p =R b /(R a +R b ) of the resistive divider  16 , according to Eq. (1) below: 
         [0000]        A (θ)= K   p   V   in,pk  sin θ  (1)
 
         [0000]    where V in,pk =√{square root over (2)}V in    
         [0011]    The auxiliary sensing resistor  21  is connected between the second terminal  4   f  of the auxiliary winding L aux  and a second input terminal ZCD of the control module  15 . The primary sensing resistor  19  is connected between the source terminal of the power switch M and the first ground  12 . Further, the source terminal of the power switch M is connected to a third input terminal CS of the control module  15  and supplies thereto a sensing voltage Vcs(t,θ), directly proportional to the current in the primary winding L p  when the power transistor M is on, i.e., during magnetization of the primary winding L p . In fact, the primary sensing resistor  19  detects the current I p (t,θ) flowing in the primary winding L p  when the power switch M is on. 
         [0012]    The transistor M further has its drain terminal connected to the second terminal  4   b  of the primary winding L p  and its gate terminal connected to an output terminal GD of the control module  15 . 
         [0013]    The clamping circuit  20  is arranged between the first and the second terminal  4   a,    4   b  of the primary winding L p  for limiting voltage spikes on the drain terminal of the switch M, caused, for example, by parasitic inductances. 
         [0014]    On the side of the secondary winding L s , the flyback converter  3  comprises a output diode D and an output capacitor C out . The output capacitor C out  is for example of an electrolytic type and has positive and negative plates coupled to a first output terminal  22  and to a second output terminal  23 , which are in turn coupled to a load  18 . The second output terminal  23  is coupled to the second ground  17 . The output diode D has its anode connected to the first terminal  4   c  of the secondary winding L s  and has its cathode connected to the first load terminal  22 . The voltage across the output capacitor C out  thus is an output voltage V out  supplied to the load  18 , here a series of diodes, for example LEDs. 
         [0015]    The control module  15  comprises a reference current source stage  24  and a comparator stage  25 . 
         [0016]    In particular, the reference current source stage  24  (described in detail in patent application US 2013/0088897) has a first input connected to the first input terminal MULT of the control module  15 , a second input connected to a fourth terminal CT of the control module  15 , and an output  27  generating a reference voltage V csREF (θ) variable as a function of the phase θ of the supply voltage V ac , as explained in detail hereinafter. 
         [0017]    The comparator stage  25  comprises a comparator  26 , a latch flip-flop  28  of a set-reset type, a driver  30 , a start-up circuit  32 , a logic gate  34  of an OR type, and a zero-crossing detector (ZCD)  36 . 
         [0018]    The comparator  26  has an inverting input connected to the output  27  of the reference current source stage  24  and a non-inverting input connected to the third input terminal CS of the control module  15 . 
         [0019]    The output of the comparator  26  is connected to the reset input R of the flip-flop  28 , the output Q whereof is connected to the input of the driver  30 , coupled to the output terminal GD of the control module  15 . The output Q of the flip-flop  28  is further connected to the set input of the flip-flop  28  through the start-up circuit  32 . In detail, the input of the start-up circuit  32  is connected to the output Q of the flip-flop  28 , and the output of the start-up circuit  32  is connected to a first input of the first logic gate  34 . The first logic gate  34  has a second input connected to a first output of the ZCD circuit  36  and an output coupled to the set input of the flip-flop  28 . The ZCD circuit  36  has an input connected to the second input terminal ZCD of the control module  15 . 
         [0020]    The reference current source stage  24  comprises a voltage-controlled current source  40  having a control terminal connected to the intermediate node  14 ; a voltage divider  41 , connected between the intermediate node  14  and the fourth terminal CT of the control module  15 ; a first switch  42 ; a second switch  43 ; and a fourth resistor R T . 
         [0021]    The current source  40  has an output terminal  44  supplying a current I CH (θ) proportional to the input voltage V in (θ). The first switch  42  is connected between the output terminal  44  of the current source  40  and the first ground  12 . The second switch  43  is connected between the output terminal  44  of the current source  40  and the fourth terminal CT of the control module  15 . The fourth resistor R T  is coupled between the fourth terminal CT of the control module  15  and the first ground  12  and generates a second voltage signal B(θ). 
         [0022]    The switches  42 ,  43  are governed by phase signals FWN and FW of a logic type, equal and in phase opposition, generated by the ZCD circuit  36 . The fourth terminal CT of the control module  15  is connected to an external capacitor C T  of high value, chosen so that, at least to a first approximation, the a.c. component (at a frequency equal to twice the frequency of the supply voltage V ac ) of the second voltage signal B(θ) is negligible as compared to the d.c. component B 0 . This condition is generally met also because in Hi-PF flyback converters the control loop has a bandwidth much lower than the frequency of the supply voltage V ac . 
         [0023]    Operation of the power supply  1  of  FIG. 1  is described hereinafter, with reference to  FIGS. 2 and 3 , and is described in detail in the paper by C. Adragna referred to above. 
         [0024]    It should be noted that, in the flyback converter  3 , when operating in Hi-PF condition, the filtering capacitor C in  does not operate as energy reservoir so that the input voltage V in  is a rectified sinusoid (Vin(θ)=V in,pk |sin θ| with θε (0,π). 
         [0025]    In these conditions, the voltage A(θ) is proportional to the input voltage V in (θ) according to Eq. (1). Furthermore, since, as mentioned above, the second voltage signal B(θ) may be approximated with the respective d.c. value B 0 , the reference voltage V csREF (θ) on the output of the voltage divider  41  is: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       V 
                       csREF 
                     
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   = 
                   
                     
                       K 
                       D 
                     
                      
                     
                       
                         A 
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                       
                         B 
                         o 
                       
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where K D  is a proportionality constant, equal to the gain of the voltage divider  41 . The reference voltage V csREF (θ) is thus a rectified sinusoidal voltage, the value whereof depends upon the effective value of the supply voltage V ac  on the basis of Eq. (1). 
         [0026]    The reference voltage V csREF (θ) is compared by the comparator  26  with the sensing voltage Vcs(t,θ), which is proportional to the current I p (t,θ) in the primary winding L p  and in the switch M, when the latter is on. 
         [0027]    Assuming that the switch M is initially closed, the current I p (t,θ) through the primary winding L p  is initially increasing, as is the sensing voltage Vcs(t,θ). When the latter reaches the reference voltage V csREF (θ), the comparator  26  switches and resets the output of the flip-flop  28 . The power switch M is thus turned off In this way, the first voltage signal A(θ), which as said has a rectified sinusoid shape, determines the peak value of the current I p (t,θ) in the primary winding L p , which is thus enveloped by a rectified sinusoid. 
         [0028]    When the switch M turns off, the energy stored in the primary winding L p  is transferred by magnetic coupling to the secondary winding L s  and thus to the output capacitor C out  and to the load  18  until the secondary winding L s  is demagnetized completely. 
         [0029]    After switching off of the switch M and as long as current flows in the secondary winding L s , the voltage of the drain terminal of the switch M is equal to V in (θ)+V R , where V R  is the so-called reflected voltage, equal to n·V out , where n is equal to the ratio between the number of the turns of the primary winding L p  and the number of the turns of the secondary winding L s  of the transformer  4 . 
         [0030]    After demagnetization of the secondary winding L s , the diode D switches off and the drain terminal of the switch M becomes floating and tends to assume a voltage equal to the instantaneous value of the input voltage V in (θ), through damped oscillations caused by a parasitic capacitance resonating with the primary winding L p . However, the rapid voltage drop on the drain terminal of the switch M following demagnetization of the transformer  4  is coupled to the second input terminal ZCD of the control module  15  and thus to the ZCD circuit  36  through the auxiliary winding L aux  and the third resistor R aux , as described in greater detail hereinafter. 
         [0031]    The ZCD circuit  36  generates a pulse S on its output connected to the comparator  26  whenever it detects that a falling edge of the voltage on the second input terminal ZCD of the control module  15  drops below a threshold (V ZCDt  in  FIG. 2 ). This pulse forces setting of the flip-flop  28 , the output of which switches, turning on the power switch M and causing start of a new switching cycle. 
         [0032]    The start-up circuit  32  enables, through the logic gate  34 , starting of the first switching cycle after turning-on of the flyback converter  3 , i.e., when no signal is yet present on the second input terminal ZCD of the control module  15 , and further prevents the flyback converter  3  from remaining blocked if for some reason the signal on the second input terminal ZCD of the control module  15  is lost. 
         [0033]    The ZCD circuit  36  also generates the phase signals FW and FWN, which are supplied to the switches  42 ,  43  (as illustrated in  FIG. 2  for the signal FW). In detail, the phase signal FW is high during transformer demagnetization and is used for generating the correct value of the second voltage signal B(θ) so as to regulate the desired value of the d.c. output current, as demonstrated in the cited paper by C. Adragna. 
         [0034]    In the circuit of  FIG. 1 , when the switch M is on, the second input terminal ZCD of the control module  15  is connected (by a controller—not illustrated) to the first ground  12 . Thus, the voltage across the auxiliary sensing resistor  21  is equal to the auxiliary voltage V aux  on the auxiliary winding L aux . In this period, the voltage drop on the primary sensing resistor  19  and on the switch M is negligible, and the input voltage V in  is substantially entirely applied on the primary winding L p , between the terminals  4   a  and  4   b.  Consequently, the auxiliary voltage V aux  and the current in the auxiliary sensing resistor  21  are proportional to the input voltage V in . 
         [0035]    When the switch M turns off, the second input terminal ZCD of the control module  15  is decoupled from the first ground  12 , and the voltage V ZCD  on the second input terminal ZCD follows the plot of the output voltage V out  according to a proportionality coefficient linked to the turn ratio between the secondary winding L s  and the auxiliary winding L aux . After demagnetization of the secondary winding L s , in particular, the voltage on the second input terminal ZCD tends to rapidly drop, as the current in the auxiliary sensing resistor  21 , as illustrated in detail in  FIG. 2 . 
         [0036]    Examples of the signals generated in the flyback converter  3  are represented in  FIG. 2 , where some quantities that follow the pattern of the input voltage V in  have rectilinear stretches, given that the switching frequency f s  (of the order of kilohertz) is much higher than the frequency f L  of the input voltage V in  (generally, 50-60 Hz). 
         [0037]    In particular,  FIG. 2  shows the following quantities:
       the voltage V DS  between the drain and source terminals of the switch M;   the voltage V in,pk  sin θ, where V in,pk  is the peak value of the input voltage V in ;   the voltage V aux  on the auxiliary winding L aux ;   the voltage V ZCD  on the second input terminal ZCD of the control module  15 ;   the threshold V ZCDt  of the voltage V ZCD  where the ZCD circuit  36  generates a pulse supplied to the logic gate  34 ;   the set and reset pulses S, R supplied to the flip-flop  28 ;   the voltage V GD  supplied on the output terminal GD of the control module  15  and driving turning-on and turning-off of the switch M;   the sensing voltage Vcs(t,θ);   the current I s (t,θ) in the secondary winding L s ; and   the freewheel phase signal FW, when demagnetization of the transformer  4  occurs.       
 
         [0048]    Furthermore,  FIG. 2  highlights the following periods:
       the period T ON , when the switch M is on, thus representing the magnetization period of the core of the transformer  4 ;   the period T FW , when the core of the transformer  4  demagnetizes; and   the period T R , i.e., the period that elapses between complete demagnetization of the core of the transformer  4  and subsequent turning-on of the switch M, i.e., start of the new magnetization of the core of the transformer  4 .       
 
         [0052]    The switching period T is thus given by T(θ)=T FW (θ)+T R +T ON . 
         [0053]    The resulting plots of the currents I p (t,θ), I s (t,θ), as well as the corresponding envelopes of the corresponding peaks I pkp (θ), I pks (θ) and the cycle-by-cycle average I in (θ) of the current in the primary winding L p  are represented in  FIG. 3 . 
         [0054]    For practical purposes, the flyback converter  3  is of the quasi-resonant type. In fact, turning-on of the transistor M is synchronized with the instant of complete demagnetization of the transformer  4  (i.e., with the instant when the current in the secondary winding L s  goes to zero), albeit with a delay. Turning-off of the transistor M is instead theoretically determined by detecting when the current I p  in the primary winding L p  reaches the provided threshold (V csREF (θ)/R s ). Furthermore, the flyback converter  3  is of the current-mode control type, and in particular of the peak-current-mode control type. Again, since the peak envelope of the current flowing in the sensing resistor R s  and thus in the primary winding L p  is sinusoidal, a power factor higher than 0.9 is obtained. 
         [0055]    As shown in the paper by C. Adragna referred to above, the regulated d.c. output current I out  that flows in the load  18  is given by: 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                     out 
                   
                   = 
                   
                     
                       
                         nK 
                         D 
                       
                       
                         
                             
                         
                          
                         
                           2 
                            
                           
                               
                           
                            
                           
                             RsG 
                             M 
                           
                            
                           
                             R 
                             T 
                           
                         
                       
                     
                     . 
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where n is the turn ratio between the primary winding L p  and the secondary winding L s  of the transformer  4 , K D  is the gain of the divider  41  (see Eq. (2)) and G M  is the transconductance of the current source  40 . Consequently, with the instant control scheme that uses only quantities available on the primary winding L p  side of the transformer  4 , the mean output current I out  depends ideally only upon external parameters, that may be selected by the user, such as n and R s , or by fixed parameters such as G M , R T , and K D  and does not depend upon the output voltage V out  or the input voltage V in  or upon the switching frequency f s =1/T(θ). 
         [0056]    In the circuit of  FIG. 1 , however, due to propagation delays, the transistor M does not turn off immediately when the sensing voltage Vcs(t,θ) reaches the reference voltage V csREF (θ), i.e., when the current I p (t,θ) in the primary winding L p  reaches the provided threshold V csREF (θ)/R s , but remains turned on for a further time, referred to as “total propagation delay T D ”, as represented in  FIG. 4 . In particular, the total propagation delay T D  is given by the sum of the switching delay of the comparator  26 , the propagation delay of the driver  30 , and the turning-off delay characteristic of the power switch M. It follows that the peak current in the primary winding L p  is higher, as compared to the ideal value, by a quantity ΔI P (θ) equal to: 
         [0000]    
       
         
           
             
               
                 
                   
                     Δ 
                      
                     
                         
                     
                      
                     
                       
                         I 
                         P 
                       
                        
                       
                         ( 
                         θ 
                         ) 
                       
                     
                   
                   = 
                   
                     
                       
                         
                           Vin 
                            
                           
                             ( 
                             θ 
                             ) 
                           
                         
                          
                         
                           T 
                           D 
                         
                       
                       
                         L 
                         P 
                       
                     
                     . 
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
         [0000]    and thus the regulated d.c. output current I out  increases with the effective value of the input voltage V in . 
         [0057]    To compensate for the increase in the peak current linked to the input voltage V in , in power supplies available on the market, a positive offset voltage proportional to the input voltage V in  is added to the sensing voltage Vcs(t,θ), as illustrated in  FIG. 5 . 
         [0058]      FIG. 5  shows a flyback power supply  50  similar to the power supply  1  of  FIG. 1 . Consequently, the elements of the flyback power supply  50  that are in common with those of the diagram of  FIG. 1  are designated by the same reference numbers and the description thereof will not be repeated. 
         [0059]    The flyback power supply  50  comprises a feed-forward resistor  51 , having a resistance R FF  and connected between the source terminal of the switch M and the third input terminal CS of the control module  15 ; and a feed-forward current source  52 , generating the feed-forward current I FF  and governed by a control current I ZCD , which is generated by the ZCD circuit  36  and is proportional to the auxiliary current I aux  flowing in the auxiliary sensing resistor  21  during the time period when the switch M is on. For example, the control current I ZCD  is equal to the auxiliary current I aux  and is generated via a current mirror circuit. 
         [0060]    On this hypothesis, since, as has been mentioned, during the on period T ON  of the transistor M, the second input terminal ZCD of the control module  15  is connected to the first ground  12 , the auxiliary current I aux  and the control current I ZCD  flowing in the auxiliary sensing resistor  21  are: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       I 
                       aux 
                     
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   = 
                   
                     
                       
                         I 
                         ZCD 
                       
                        
                       
                         ( 
                         θ 
                         ) 
                       
                     
                     = 
                     
                       
                         m 
                          
                         
                             
                         
                          
                         
                           Vin 
                            
                           
                             ( 
                             θ 
                             ) 
                           
                         
                       
                       
                         R 
                         aux 
                       
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where m is the turn ratio between the auxiliary winding L aux  and the primary winding L p . 
         [0061]    The feed-forward current source I FF  is a current mirror that generates a current proportional to the current I ZCD  according to the relation: 
         [0000]        I   FF (θ)= K   FF   I   ZCD (θ)
 
         [0000]    where K FF  is the gain of the current mirror. 
         [0062]    The feed-forward current I FF  is supplied to the feed-forward resistor  51 , which generates an additional feedback voltage V FF . Setting R FF &gt;&gt;R S , we have: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       V 
                       FF 
                     
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   = 
                   
                     
                       K 
                       FF 
                     
                      
                     m 
                      
                     
                         
                     
                      
                     
                       
                         R 
                         FF 
                       
                       
                         R 
                         aux 
                       
                     
                      
                     
                       
                         Vin 
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
         [0063]    Imposing that the additional feedback voltage V FF  is equal to the voltage step due to the propagation delays: 
         [0000]      Δ V   CS (θ)= R   S   ΔI   P (θ)= V   FF (θ)
 
         [0000]    and combining with Eq. (4), we obtain the resistance value R FF  of the feed-forward resistor useful for obtaining a compensation: 
         [0000]    
       
         
           
             
               
                 
                   
                     R 
                     FF 
                   
                   = 
                   
                     
                       1 
                       
                         K 
                         FF 
                       
                     
                      
                     
                       1 
                       m 
                     
                      
                     
                       
                         
                           R 
                           aux 
                         
                          
                         
                           R 
                           
                             S 
                              
                             
                                 
                             
                           
                         
                       
                       
                         L 
                         P 
                       
                     
                      
                     
                       
                         T 
                         D 
                       
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
           
         
       
     
         [0064]    In practice, the voltage supplied to the comparator  26  is increased, with respect to the voltage V p  on the primary sensing resistor  19 , by a value such as to anticipate switching of the comparator  26  by a time equal to the total propagation delay T D . In this way, when the comparator  26  switches, the current I P  flowing in the primary sensing resistor  19  is lower than the threshold value, and when the power switch M turns off with a delay T D , the current I P  has reached the desired threshold value, as illustrated in  FIG. 6 . 
         [0065]    It follows that the variation of the output current supplied by the secondary winding L s  proportional to the input voltage V in  due to the total propagation delay may be compensated thereby if the total propagation delay T D  is constant. However, if the total propagation delay T D  varies, also this compensation is not sufficient. 
         [0066]    This is a problem in solid-state lighting apparatuses, where it is increasingly important to obtain a high accuracy in the d.c. output current, with values even lower than ±3%, which cannot always be achieved with the compensation technique represented in  FIG. 5 . 
         [0067]    In addition, the described power supply is used with different power transistors M, according to the applications and requirements of the users. The power transistors M available on the market have similar static characteristics, in particular similar saturation resistance R DS-on , but different switching characteristics, in particular a different switching time. It follows that the output current varies according to the power transistor being used. This requires a modification and an adaptation of the value of the feed-forward resistor  51 , on the basis of Eq. (7), according to the applications and to the power switch used. This setting is, however, complex and costly. 
       BRIEF SUMMARY 
       [0068]    One embodiment of the present disclosure is a current converter that generates a d.c. output current irrespective both of the variations of the supply voltage V ac  and of variations in the propagation delay. 
         [0069]    According to the present disclosure, a control circuit for a switch for a switching current converter, a switching power supply, and a corresponding control method are provided. 
         [0070]    One embodiment of the present application is a control circuit that is based upon the principle of supplying a feed-forward current proportional not only to the input voltage V in , but also to the total propagation delay T D . In particular, the present power supply supplies the feed-forward resistor  51  with a compensation current I COMP : 
         [0000]        I   COMP (θ,  T   D )= K   FF 0 Vin(θ) T   D    (8)
 
         [0000]    where K FFO  is a constant. 
         [0071]    To do this, imposing that the positive offset R FF I FF (θ, T D ) is equal to the sensing-voltage step due to the propagation delay ΔV CS (θ)=R S ΔI P (θ) and taking into account Eq. (4), it results: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       R 
                       FF 
                     
                      
                     
                       K 
                       
                         FF 
                          
                         
                             
                         
                          
                         0 
                       
                     
                      
                     
                       Vin 
                        
                       
                         ( 
                         θ 
                         ) 
                       
                     
                      
                     
                       T 
                       D 
                     
                   
                   = 
                   
                     
                       R 
                       S 
                     
                      
                     
                       
                         
                           
                             Vin 
                              
                             
                               ( 
                               θ 
                               ) 
                             
                           
                            
                           
                             T 
                             D 
                           
                         
                         
                           L 
                           P 
                         
                       
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   9 
                   ) 
                 
               
             
           
         
       
     
         [0072]    Eq. (9) shows that the input voltage V in  and the total propagation delay T D  may both be compensated by using a feed-forward resistor  51  having a resistance R FF  of: 
         [0000]    
       
         
           
             
               
                 
                   
                     R 
                     FF 
                   
                   = 
                   
                     
                       
                         R 
                         s 
                       
                       
                         L 
                         P 
                       
                     
                      
                     
                       
                         1 
                         
                           K 
                           
                             FF 
                              
                             
                                 
                             
                              
                             0 
                           
                         
                       
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   10 
                   ) 
                 
               
             
           
         
       
     
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0073]    For a better understanding of the present disclosure, a preferred embodiment thereof is now described, purely by way of non-limiting example, with reference to the attached drawings, wherein: 
           [0074]      FIG. 1  shows a circuit diagram of a known switching power supply; 
           [0075]      FIGS. 2-4  show time plots of signals generated within the switching power supply illustrated in  FIG. 1 ; 
           [0076]      FIG. 5  shows a circuit diagram of another switching power supply; 
           [0077]      FIG. 6  shows the time plots of some quantities of the circuit of  FIG. 5 ; 
           [0078]      FIG. 7  shows a simplified circuit diagram of an embodiment of the present switching power supply; 
           [0079]      FIG. 7A  shows a generator block used in the circuit diagram of  FIG. 7 ; and 
           [0080]      FIG. 8  shows the time plots of some quantities of the power supply of  FIGS. 7 and 7A . 
       
    
    
     DETAILED DESCRIPTION 
       [0081]      FIG. 7  shows a switching power supply  100  having a similar general structure as the power supply  50  of  FIG. 5 . Consequently, the elements of the switching power supply  100  that are in common with the diagram of  FIG. 4  (and thus the diagram of  FIG. 1 ) are designated by the same reference numbers and will not be described again. 
         [0082]    The switching power supply  100  comprises a current source stage  101  shown in detail in  FIG. 7A  and receiving the control current I ZCD  supplied by the ZCD circuit  36  and the set and reset signals S, R (referred to hereinafter also as duty-cycle set and reset signals S, R) generated respectively by the logic gate  34  and by the comparator  26  (referred to hereinafter also as duty-cycle comparator  26 ) and generates a compensated current I COMP . 
         [0083]    With reference to  FIG. 7A , the current source stage  101  comprises a delay estimation block  102  and a current source block  103 . 
         [0084]    The delay estimation block  102  comprises a first current mirror generator  105  controlled by the control current I ZCD  and supplying at an output  110  a first mirror current I CH1  proportional, in particular equal, to the control current I ZCD ; an auxiliary comparison network  109 ; an estimation comparator  113 ; and a latch flip-flop  114  of a set/reset type. 
         [0085]    The auxiliary comparison network  109  comprises an auxiliary current sensing resistor  111 , coupled between the output  110  of the first current mirror generator  105  and the first ground  12  and having a resistance R 1 , and a filter branch  112 , connected in parallel to the auxiliary current sensing resistor  111 . 
         [0086]    The filter branch  112  in turn comprises a filter resistor  115 , having a resistance R D , and a filter capacitor  116 , having a capacitance C D , which are connected together in series and define an intermediate node  118 . The filter resistor  115  is connected between the output  110  of the first current mirror generator  105  and the intermediate node  118 . The filter capacitor  116  is connected between the intermediate node  118  and the first ground  12 . An offset voltage source  117  for generating a voltage offset of a few tens of millivolts is arranged between the output  110  of the first current mirror generator  105  and an inverting input of the estimation comparator  113 . The estimation comparator  113  further has a non-inverting input directly coupled to the intermediate node  118  and an output connected to a reset input R 1  of the latch flip-flop  114 . The latch flip-flop  114  further has a set input S 1  receiving the reset signal R generated by the flip-flop  28  ( FIG. 7 ) and regulates the duty-cycle of the switch M; thus it is referred to hereinafter also as duty-cycle flip-flop  28 . The latch flip-flop  114  further has its output Q 1  connected to the current source block  103 . 
         [0087]    The current source block  103  comprises a second current mirror generator  120  receiving the control current I ZCD  and outputting a second mirror current I CH2  proportional, in particular equal, to the control current I ZCD ; a control switch  121  coupled between the output of the second current mirror generator  120  and a control node  122 ; a discharge switch  123 , arranged between the control node  122  and the first ground  12 ; a charging capacitor  125 , having a capacitance C TR  and arranged between the control node  122  and the first ground  12 ; a transfer switch  126 , coupled between the control node  122  and a transfer node  127 ; and a hold capacitor  128 , having a capacitance C H  and coupled between the transfer node  127  and the first ground  12 . The charging capacitor  125 , the transfer switch  126 , and the hold capacitor  128  form a memory element  130  of a track-and-hold type, as explained in detail hereinafter. 
         [0088]    The output node  127  is further coupled to a control input of a compensation current source  131 , which outputs the compensation current I COMP  supplied to the feed-forward resistor  51  of  FIG. 7 . The current source block  103  further receives the set signal S generated by the logic gate  34  of  FIG. 7  and fed to a control input of the transfer switch  126  and, through a delay element  132 , to a control input of the discharge switch  123 . 
         [0089]    Operation of the circuit of  FIG. 7, 7A  is described hereinafter. 
         [0090]    The reset signal R generated by the duty-cycle comparator  26  ( FIG. 7 ) when the sensing voltage V cs  on the primary sensing resistor  19  reaches the reference value V csREF , sets the latch flip-flop  114 , which is reset by the estimation comparator  113  after a time equal to the estimate of the total propagation delay T D , as explained hereinafter. 
         [0091]    In fact, the first current mirror generator  105  supplies the auxiliary comparison network  109  with a first mirror current I CH1  equal to the control current I ZCD . By choosing the values of resistance R 1 , R D  of the resistors  111 ,  115  so that R 1 &lt;&lt;R D  and by choosing the value of capacitance C D  of the filter capacitor  116  so that the filter branch  112  forms a lowpass filter with a time constant of the order of nanoseconds, in steady-state conditions, the current I CH1  supplied by the first current mirror generator  105  flows practically entirely in the first auxiliary current sensing resistor  111  so that the voltage on the output node  110  of the first current mirror generator  105  is: 
         [0000]        V   R1 (θ)= R   1   I   ZCD (θ).
 
         [0092]    Instead, the filter branch  112  supplies the estimation comparator  113  with a voltage value correlated to the delayed value of the first mirror current I CH1  and thus of the control current I ZCD . 
         [0093]    In this way, the auxiliary comparison network  109  supplies the estimation comparator  103  with a signal correlated to the instantaneous value and with a delayed signal of the auxiliary current I aux , to enable detection of the instant when the auxiliary current I aux  drops (knee of the curve of  FIG. 8 ). 
         [0094]    In detail, by virtue of the offset voltage generated by the source  117 , when the switch M is off (period t 0 -t 1  in the timing of  FIG. 8 ), the inverting input of the estimation comparator  113  is at a higher potential than the non-inverting input, and the output R 1  of the estimation comparator  113  is low. This behavior repeats throughout the half-period of the input voltage V in , in view of its frequency f L , much lower than the switching frequency f s . 
         [0095]    As soon as the duty-cycle comparator  26  switches and the duty-cycle reset signal R goes high (instant t 1 ), the estimation flip-flop  114  switches, and its output signal Q 1  goes high. 
         [0096]    At the instant t 2 , when the transistor M turns off (with a delay equal to the total propagation delay T D , as explained above), the auxiliary current I aux  drops, as do the control current I ZCD , as represented in the plot of  FIG. 8 , and thus the first mirror current I CH1 , thus determining a sharp voltage reduction on the output  110  of the first current mirror generator  105  and thus switching of the estimation comparator  113 , which resets the estimation flip-flop  114 , the output Q 1  of which goes low. 
         [0097]    It follows that the output Q 1  of the estimation flip-flop  114  has a pulse with a width equal to the total propagation delay T D  and thus represents a delay estimation signal, a parameter (pulse width) whereof is correlated to the total propagation delay T D . 
         [0098]    The output Q 1  of the estimation flip-flop  114  controls turning on and off of the control switch  121 . Precisely, as soon as the output signal Q 1  of the estimation flip-flop  114  turns high (instant t 1 ), when the sensing voltage V cs  on the inverting input of the duty-cycle comparator  26  reaches its threshold value (V csREF ), the control switch  121  closes and the second mirror current I CH2 , equal to the control current I ZCD  and generated by the second current mirror generator  120 , flows to the charging capacitor  125 , thus charging it (in this step, the duty-cycle set signal S is low and thus the discharge switch  123  and the transfer switch  126  are open). The control voltage V CTR  on the charging capacitor  125  thus increases proportionally to the control current I ZCD  and to the auxiliary current I aux . As soon as the output signal Q 1  of the estimation flip-flop  114  switches to low (instant t 2 ), the control switch  121  opens and the second current mirror generator  120  interrupts charging of the charging capacitor  125 . Consequently, the charging capacitor  125  is charged for an estimated period T C  equal to the total propagation delay T D  with a current equal to the control current I ZCD  and proportional to the input voltage V in . 
         [0099]    Assuming, as for the circuit of  FIG. 1 , that the switching frequency f s =1/T(θ) is much higher than the frequency f L  of the input signal V in , the control current I ZCD  and thus the second mirror current I CH2  may be considered constant during the estimated delay T C  in which the charging capacitor  125  is charged, and thus charging capacitor  125  charges linearly. 
         [0100]    The peak voltage V CTR   _   PEAK (θ) reached by the charging capacitor  125  is thus: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       V 
                       CTR_PEAK 
                     
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   = 
                   
                     
                       
                         
                           I 
                           ZCD 
                         
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                       
                         C 
                         TR 
                       
                     
                      
                     
                       
                         T 
                         C 
                       
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   11 
                   ) 
                 
               
             
           
         
       
     
         [0101]    The discharge switch  123  and the transfer switch  126  remain open until a subsequent pulse of the duty-cycle set signal S is received (instant t 3 ) so that the charging capacitor  125  maintains the value V CTR   _   PEAK (θ). 
         [0102]    At instant t 3 , the duty-cycle set signal S switches to high, causing the transfer switch  126  to immediately close and connect the charging capacitor  125  to the output capacitor  128 . Assuming that the output capacitor  128  has a capacitance C H  much lower than capacitance C TR  of the charging capacitor  125 , it charges rapidly to the peak voltage V CTR   _   PEAK (θ) of the charging capacitor  125 . 
         [0103]    In practice, by combining Eq. (11) with Eq. (5), the control voltage V CH  across the output capacitor  128  is given by: 
         [0000]    
       
         
           
             
               
                 V 
                 CH 
               
                
               
                 ( 
                 θ 
                 ) 
               
             
             = 
             
               
                 
                   m 
                    
                   
                       
                   
                    
                   
                     Vin 
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                 
                 
                   R 
                   aux 
                 
               
                
               
                 1 
                 
                   C 
                   TR 
                 
               
                
               
                 
                   T 
                   C 
                 
                 . 
               
             
           
         
       
     
         [0000]    which is proportional to the product of the input voltage V in  and the estimated delay T C , approximately equal to the total propagation delay T D , so that: 
         [0000]    
       
         
           
             
               
                 V 
                 CH 
               
                
               
                 ( 
                 θ 
                 ) 
               
             
             = 
             
               
                 
                   m 
                    
                   
                       
                   
                    
                   
                     Vin 
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                 
                 
                   R 
                   aux 
                 
               
                
               
                 1 
                 
                   C 
                   TR 
                 
               
                
               
                 
                   T 
                   D 
                 
                 . 
               
             
           
         
       
     
         [0104]    The compensation-current source  131  thus generates the compensation current I COMP  proportional to the control voltage V CH , as follows: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       I 
                       COMP 
                     
                      
                     
                       ( 
                       
                         θ 
                         , 
                         
                           T 
                           D 
                         
                       
                       ) 
                     
                   
                   = 
                   
                     
                       g 
                       FF 
                     
                      
                     
                       m 
                       
                         R 
                         aux 
                       
                     
                      
                     
                       1 
                       
                         C 
                         TR 
                       
                     
                      
                     
                       Vin 
                        
                       
                         ( 
                         θ 
                         ) 
                       
                     
                      
                     
                       T 
                       D 
                     
                   
                 
               
               
                 
                   ( 
                   12 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where g FF  is the current-to-voltage gain of the compensation-current source  131 . 
         [0105]    As soon as the duty-cycle set signal S switches again to low, the transfer switch  126  opens again, disconnecting the output capacitor  128  from the charging capacitor  125 . 
         [0106]    In the current source block  103 , the duty-cycle set signal S is supplied with a slight delay (instant t 4 ) also to the discharge switch  123 , which, when it closes, connects the charging capacitor  125  to ground, discharging it rapidly, and then opens again. In the short period of time when the discharge switch  123  is closed, the charging capacitor  125  is disconnected from the output capacitor  128 , which thus remains charged to the value of the control voltage V CTR  previously stored. In this way, the charging capacitor  125  is discharged and recharged to a new value of the control voltage V CTR  at each switching cycle, as illustrated in  FIG. 8 , thus guaranteeing cycle-by-cycle adaptation to possible modified conditions in the input voltage V in  or in the total propagation delay T D . 
         [0107]    The compensation current I COMP  supplied by the current source stage  101  is thus proportional to the product of the input voltage V in  and the total propagation delay T D . 
         [0108]    The switching power supply described herein thus enables compensation of the propagation delay due to the driver  30  and to switching of the switch M (the delay due to the duty-cycle comparator  26  is much lower than the two previous delays and thus negligible) with an adaptive solution that does not require appropriate setting in case of replacement of the power switch M and is independent of the input voltage V in . 
         [0109]    Finally, it is clear that modifications and variations may be made to the circuit described and illustrated herein, without thereby departing from the scope of the present disclosure. 
         [0110]    In particular, the described solution may be applied also to converters of a different type, including current control without output current reading, for example in converters of a buck and buck-boost type. 
         [0111]    The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.