Abstract:
A method and apparatus for improved race detection and expression is disclosed. The race detection method and apparatus disclosed herein detects races statically by analyzing the circuits, which are usually written in a hardware description language (HDL), such as VHDL or Verilog. Compared with known simulation approaches, the inventive method and apparatus has at least the following advantages: no test vectors are required; all potential races can be detected; and in simulator approaches, if the right test vectors are not provided, then the races cannot be found (the invention avoids this last constraint).

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Technical Field  
           [0002]    The invention relates to circuit design. More particularly, the invention relates to race condition detection and expression.  
           [0003]    2. Description of the Prior Art  
           [0004]    A race condition is a very common and serious issue in circuit design. An example of a race condition is shown in Table 1 below by a Verilog program.  
                                                                     TABLE 1                       Race Condition                                    module t(clk, a, b, c);                input clk;                output   a;           input   b;           input   c;           reg   a;                always @ (posedge clk) a = b;           always @ (posedge clk) a = c;                endmodule                      
 
           [0005]    In this example, when the clock “clk” changes from “0” to “1”, that is at the positive edge of clk, either a=b may happen first or a=c may happen first. That is, they may race each other. As a result, signal “a” may get the value of “b” or “c.” In circuit design, this is an undesired effect because the final value of “a” is nondeterministic.  
           [0006]    A race condition is defined as a situation where reading a variable may result in one of several values nondeterministically. To avoid races, circuits are usually designed in some specific ways to prevent a race condition.  
           [0007]    Another approach is to detect during the design stage if the circuits may have races. Some circuit simulation tools can detect a race condition when the simulator finds that, during the same simulation cycle, a signal (also referred to as a wire, register, or variable) is being written to two or more times, or being written to as well as being read from. See, for example, U.S. Pat. Nos. 5,383,167; 5,818,263; 5,901,061; and 6,009,256.)  
           [0008]    An example of a simulator which can detect race conditions is the VCS Verilog Simulator from Synopsys. Such simulators need test vectors to conduct the simulation. The race may or may not be detected depending the way in which the test vectors exercise the design.  
           [0009]    It would be advantageous to provide a method and apparatus for improved race detection and expression.  
         SUMMARY OF THE INVENTION  
         [0010]    The invention provides a method and apparatus for improved race detection and expression. The race detection method and apparatus disclosed herein detects races statically by analyzing the circuits, which are usually written in a hardware description language (HDL), such as VHDL or Verilog.  
           [0011]    Compared with known simulation approaches, the inventive method and apparatus has at least the following advantages:  
           [0012]    No test vectors are required.  
           [0013]    All potential races can be detected.  
           [0014]    In the simulator approaches, if the right test vectors are not provided, then the races cannot be found. The invention avoids this constraint. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]    [0015]FIG. 1 is an example race graph according to the invention;  
         [0016]    [0016]FIG. 2 is an illustration of a computer display in which a race graph is at the right and a Verilog design is at the left according to the invention;  
         [0017]    [0017]FIG. 3 is a another example of a race graph according to the invention;  
         [0018]    [0018]FIG. 4 is a design graph for the Verilog design module foo (in Table 2) according to the invention;  
         [0019]    [0019]FIG. 5 is an example of a more complicated design graph according to the invention;  
         [0020]    [0020]FIG. 6 is an example of the more complicated design graph of FIG. 5 in which traversed nodes are marked with horizontal lines according to the invention;  
         [0021]    [0021]FIG. 7 is an example of the more complicated design graph of FIG. 5 in which traversed nodes are marked with vertical lines according to the invention;  
         [0022]    [0022]FIG. 8 is an example of the more complicated design graph of FIG. 5 in which traversed nodes constitute a race graph according to the invention; and  
         [0023]    [0023]FIG. 9 is an example of the more complicated design graph of FIG. 5 in which traversed nodes constitute another race graph according to the invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0024]    The invention provides a method and apparatus for improved race detection and expression. The race detection method and apparatus disclosed herein detects races statically by analyzing the circuits, which are usually written in a hardware description language (HDL), such as VHDL or Verilog (see IEEE Std 1364-1995,  IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language,  IEEE, ISBN 1-55937-727-5 and IEEE Std 1076-1993,  IEEE Standard VHDL Language Reference Manual (ANSI),  IEEE, ISBN: 1-55937-376-8.)  
         [0025]    Race Graph  
         [0026]    To detect the race statically, it is first necessary to provide a new style of representing (expressing) races. In contrast to conventional race representations, where a race is confined to a signal at a particular time point, the herein disclosed representation uses a race graph to represent the race.  
         [0027]    [0027]FIG. 1 is an example race graph according to the invention. In FIG. 1, O 1  to O 7  are objects. O 1  is the source object, O 7  is the target object, and O 4  and O 6  are anchor objects.  
         [0028]    The race is started from O 1 . This is why it is called the source. While O 1  is executed, O 2  and O 3  are triggered and executed via link E 12  and E 13 , respectively. Executing O 2  then triggers the execution of O 4 . At the same time, executing O 3  triggers the execution of O 5 , and executing O 5  triggers the execution of O 6 . Both O 4  and O 6  are competing for the common target object O 7 . This is why O 4  and O 6  are called the anchors and O 7  is called the target.  
         [0029]    In a real life example, O 7  could be a register in a circuit, and both O 4  and O 6  could be two computing elements which are trying to write to the common register O 7  simultaneously.  
         [0030]    To summarize, a race graph according to the presently preferred embodiment of the invention contains:  
         [0031]    A source node, i.e. the object starting the race;  
         [0032]    A target node, i.e. the object being raced for;  
         [0033]    Two or more anchor nodes, i.e. the objects competing for the target object; and  
         [0034]    Triggering edges, i.e. the edges, each of which links an object A to another object B, where executing A first results in B being executed next.  
         [0035]    Linking a Race Graph with an HDL Design  
         [0036]    The invention also comprises the notion of mapping the race graph to the circuit design, when used in a race detection software tool to help circuit designers to traverse the races easily. For example, suppose the design is written in Verilog. Mouse-clicking on a node or an edge of the race graph brings up a window showing the corresponding Verilog segments (see FIG. 2).  
         [0037]    In the graph of FIG. 2, the race graph  20  is shown at the right and the Verilog design  22  is shown at the left. At the race graph, a node  21  is highlighted by a mouse-clicking. In the corresponding Verilog design, the related source code for that node  23  is highlighted.  
         [0038]    Another example is shown with a Verilog design in Table 2 below, and its race graph in FIG. 3. In a race-detection software tool, mouse-clicking on the node with label “ex01.v:9” (FIG. 3;  31 ) highlights Line  9  of the Verilog code, and mouse-clicking on the link with label “c2” (FIG. 3;  33 ) highlight the “c2” of Line  9  in the Verilog code.  
                                                                                         TABLE 2                       Verilog Design                                    module foo(clk, a, b);   // 1                input clk;   // 2                output   a;   // 3           input   b;   // 4           wire   d1, d2;   // 5           req   c1, c2, a;   // 6                   // 7                always @ (posedge clk) c1 = b;   // 8           always @ (posedge clk) c2 = ˜b;   // 9               // 10           assign d1 = c1;   // 11           assign d2 = c2;   // 12               // 13           always @ (d1) a = d1;   // 14           always @ (d2) a = d2;   // 15                endmodule   // 16                      
 
         [0039]    In this example, symbol a is written at line  14  and line  15 , which are triggered by line  11  and  12  respectively, which in turn are triggered by line  8  and  9  respectively, and which are both sensitive to the value change of clk. That is, once clk is changed, both line  14  and  15  may be executed. However, it is not guaranteed whether line  14  or line  15  is executed earlier. This is called a race.  
         [0040]    To detect a race, the circuit is first translated into a directed graph, referred to as a design graph herein. In this graph, there are two kind of nodes, i.e. computing nodes and data nodes.  
         [0041]    Computing nodes are computing elements, such as an always block in Verilog designs.  
         [0042]    Data nodes are storage or wiring elements, such as a reg in Verilog designs.  
         [0043]    Edges are used to link computing nodes and data nodes to denote signal flows and triggering relations.  
         [0044]    A Verilog always block provides an example. Suppose there is an always block such as the following:  
         always @( a )  b=a;    
         [0045]    In this example, the invention generates:  
         [0046]    One computing node B1 for the always block;  
         [0047]    One data node B2 for symbol “a”;  
         [0048]    One data node B3 for symbol “b”;  
         [0049]    One edge from B2 to B1 because when “a” is changed, B1 must be executed; and  
         [0050]    One edge from B1 to B3 because after B1 is executed, the value of “b” may change.  
         [0051]    The Verilog design module foo above is represented by the design graph of FIG. 4.  
         [0052]    Write-write Race Detection Algorithm  
         [0053]    To detect write-write races in accordance with the presently preferred embodiment of the invention, the following algorithm is applied:  
         [0054]    Target Selection Step  
         [0055]    First, choose a possible target node. In this example, suppose “a” (FIG. 4) is chosen as the target node.  
         [0056]    Anchor Pair Selection Step  
         [0057]    Next, choose a pair of possible anchor nodes. In this example, there are only two possible anchor nodes, i.e. node “15” and node “14”. Nodes “14” and “15” are hence the only possible pair.  
         [0058]    Backward Traversal Step  
         [0059]    Next, starting from each of the anchor nodes, the design graph is traversed in backward direction:  
         [0060]    Backward Traversal for Path 1  
         [0061]    Traverse backward from Node “15” (one of the anchor nodes), and mark all the traversed nodes with “m1”. The marked nodes are “15”, “d2”, “12”, “c2”, “9”, and “clk”.  
         [0062]    Backward Traversal for Path 2  
         [0063]    Also, traverse backward from Node “14” (another anchor node). The traversal stops traversing down an edge whenever it visits a node which has been marked with “m1”. Also, all the nodes that are traversed this time are marked with “m2”. The marked nodes are “14”, “d1”, “11”, “c”, “8”, and “clk”.  
         [0064]    Source Collection Step  
         [0065]    All the nodes that are marked with both “m1” and “m2” are the source nodes. In this example, the only source node is Node “clk”.  
         [0066]    Forward Traversal Step  
         [0067]    Next, starting from a source node, the design graph is traversed in forward direction:  
         [0068]    Forward Traversal for Path 1  
         [0069]    Traverse forward toward Node “15”, over the nodes previously marked with “m1”. The nodes and edges traversed constitute the first path of the race graph.  
         [0070]    Path Condition Collection and Verification for Path 1  
         [0071]    Also, during the traversal the path condition is collected and verified aggregately. Whenever it is found that the path condition becomes always false, the traversal aborts and the process continues with the next possible source node.  
         [0072]    Forward Traversal for Path 2  
         [0073]    Traverse forward toward Node “14”, over the nodes previously marked with “m2”. The nodes and edges traversed constitute the second path of the race graph.  
         [0074]    Path Condition Collection and Verification for Path 2  
         [0075]    Also, the path condition is collected and verified similarly as that for Path 1.  
         [0076]    Dual Path Condition Check Step  
         [0077]    The path conditions of the first and the second paths are combined together to check if they could be always false. If the conditions are found to be always false, there is no race for this source and pair of anchor nodes.  
         [0078]    Race Graph Generation Step  
         [0079]    If the race is not ruled out by the condition checks, then the result is a race graph. The first and the second paths, together with the target node, constitute the race graph. Some work can be done to improve the presentation of the race graph. For example, if a data node is between two computing nodes, one can eliminate the data node, link these two computing nodes directly, and put the data node label as the new edge&#39;s label. By doing this, one gets the race graph (in FIG. 3).  
         [0080]    Single Path Condition Check  
         [0081]    A path condition is the aggregate conditions over a path of the design graph, such that when it is satisfied, executing the starting node of the path results in the execution of the ending node of the path. For example, consider the design of Table 3 below.  
                                                                           TABLE 3                       Example Design                                    always @ (a or b) // B1                if (a == 1&#39;b0)                c = b;                always @ (a or c) // B2                if (a == 1&#39;b1)                d = c;                      
 
         [0082]    Conceptually, there might be a path from the first always block, (computing node B1), to signal “c”, (data node “c”), then to the second always block (computing node B2), and finally to signal “d” (data node “d”). Note that to have “c=b” executed, “a==1′b0” must hold; and to have “d=c” executed, “a==1′b1” must hold. However, the path condition ((a==1′b0) AND (a==1′b1)) is always false. Therefore, there should be no such a path as stated.  
         [0083]    During race detection in the forward traversal stage, one can collect and verify the path condition aggregately, and abort the traversal accordingly. Any condition that can be used to rule out a race can be used as the path condition.  
         [0084]    Single Path Condition Check using Branch Conditions  
         [0085]    In this example, the conditions used are branch conditions. The term branch condition is used to mean the condition in an “if” statement or a “case” statement in most programming languages and hardware description languages. In these statements, the execution branches to one part of the program or another part of the program. This is why the conditions in these statements are called branch conditions.  
         [0086]    Dual Path Condition Check  
         [0087]    The path conditions of the first and the second paths can also be combined together to check if the race is possible. Suppose traversing path 1 needs path condition 1 to hold, and traversing path 2 needs path condition 2 to hold. If condition 1 and condition 2 contradict each other, then the race is not possible.  
         [0088]    Dual Path Condition Check using Branch Conditions  
         [0089]    When branch conditions are used as path conditions, the path conditions of the first and the second paths can also be AND&#39;ed together to check if the race is possible. For example, suppose the first path&#39;s condition is “c==d”, and the second path&#39;s condition is “c!=d”. When these two conditions AND&#39;ed together, the result is ((c==d) AND (c!=d)), which is FALSE. Therefore, there is no race in this situation.  
         [0090]    Dual Path Condition Check using Non-Blocking Assignments  
         [0091]    There are various kinds of path conditions. They could be used to rule out false races that would otherwise be reported. For example, in Verilog design there are so called non-blocking assignments and blocking assignments, which affect the simulation steps. Suppose during the forward traversal, it is found that the first path and the second path have different steps of non-blocking assignments. Then the race can be ruled out. This is another kind of path condition.  
         [0092]    Consider as an example the Verilog code as Table 4 below.  
                                             TABLE 4                       Verilog Code                                    module t(clk, a, b, c);                input clk, b, c;           output a;           reg   a, d, e;           always @ (posedge clk) e &lt;= b; // C1           always @ (e) a &lt;= e; // C2           always @ (posedge clk) d &lt;= c; // C3           always @ (d) a = d; // C4                endmodule // t                      
 
         [0093]    There is an otherwise write-write race to signal “a”, starting from “clk”. Path 1 takes the route “clk=&gt;C1=&gt;e=&gt;C2=&gt;a”, and Path 2 takes the route “clk=&gt;C3=&gt;d=&gt;C4=&gt;a”. However, to get “a” assigned along Path 1, it takes two steps or simulation cycles because there are two non-blocking assignments denoted by “=&gt;” in the path. On the other hand, to get “a” assigned along Path 2 it only takes one step. As a result, assignments to “a” along Path 1 and 2 cannot happen at the same simulation cycle, and hence there is no race.  
         [0094]    The following is a more complicated traversal example. Suppose there is a design graph as shown in FIG. 5. For the following discussion, refer to the steps of detecting write-write races above.  
         [0095]    In the Target Section Step, a data node is chosen. Suppose D10 is selected here.  
         [0096]    Next, in the Anchor Pair Selection Step, all possible anchors (for D10) are identified and each pair of anchors are selected in turn. In this case, there are only two predecessors of D10, so the only pair of D10&#39;s anchor nodes is C7 and C8.  
         [0097]    In the Backward Traversal Step, the process traverses backward from each of the anchor nodes to find the common source node. First, the process traverses backward from C7 (Backward Traversal for Path 1). The traversed nodes are marked with horizontal lines as shown in FIG. 6.  
         [0098]    Next, the process traverses backward from C8 (Backward Traversal for Path 2). The traversed nodes are marked with vertical lines as shown FIG. 7. Note that the nodes which are marked by both horizontal lines and vertical lines are the source nodes (Source Collection Step). In this case, C4 and D4 are the source nodes.  
         [0099]    Next, the process starts from the source node C4 and traverses forward, performing the Forward Traversal Step, including its sub-steps. The traversed nodes constitute a race graph, as shown in FIG. 8.  
         [0100]    The process then starts from another source node D4 and traverses forward, performing the Forward Traversal Step, including its sub-steps. The traversed nodes constitute another race graph, as shown in FIG. 9.  
         [0101]    General Race Detection Algorithm  
         [0102]    The general race detection algorithm is described as shown in Table 5 below.  
                                                                                 TABLE 5                       General Race Detection Algorithm                                do Target Selection;       for each target t, do:                do Anchor Pair Selection;           for each anchor pair (a1, a2),                do Backward Traversal (BT):                do BT from al;           do BT from a2;                do Source Collection;           for each source s,                do Forward Traversal (FT):                do FT and Single Path Condition Check for path 1;           do FT and Single Path Condition Check for path 2;           do Dual Path Condition Check;           do Race Graph Generation;                      
 
         [0103]    The traversals in the Backward Traversal and the Forward Traversal steps are basically graph traversals. That is, depth-first order traversal or breadth-first order traversal can be used to traverse the graph to avoid a node or an edge being traversed multiple times (see, for example, T. Cormen et al,  Introduction to Algorithms,  McGraw-Hill Book Company, New York, (1993) ISBN: 0-07-013143-0).  
         [0104]    Use Predecessor Matrix to Improve Backward Traversal Efficiency  
         [0105]    To improve the efficiency of the Backward Traversal Step, a predecessor matrix can be used. Suppose there are n nodes in the design graph. A predecessor matrix M is an n by n matrix, where element M (i,j) is 1 is Node j is a direct or indirect predecessor of Node i, and M (i, j) is 0 otherwise.  
         [0106]    The predecessor matrix M can be computed as follows:  
         [0107]    For each node, if Node j is a direct predecessor of Node i, set M(i, j) to 1. Otherwise, set it to 0.  
         [0108]    Perform a transitive closure algorithm on the matrix M (see, for example, T. Cormen et al,  Introduction to Algorithms,  McGraw-Hill Book Company, New York, (1993) ISBN: 0-07-013143-0).  
         [0109]    Before the Backward Traversal Step, the predecessor matrix can be computed. After it is computed, row i of M determines the set of all nodes that are predecessors of node i. With Node a and Node b as the anchor pair, one can improve the backward traversal as follows:  
         [0110]    Compute the set of common sources of Node a and Node b, by performing a logical AND operation of the Row a and Row b. Let the resulting vector be called S.  
         [0111]    Suppose during the backward traversal, Node c is now being traversed. If the process can traverse backward from Node c to any one of the common source nodes, then the logical AND of row c of the matrix M, which is the predecessors of Node c, and the vector S should not be a vector of all zeros.  
         [0112]    Using this property, one can avoid traversing further into nodes which do not lead to common source nodes.  
         [0113]    Read-Write Race Detection Algorithm  
         [0114]    To detect read-write races, it is only necessary to change the Anchor Pair Selection Step. All other steps are the same as the steps of detecting write-write races. When detecting read-write races, after a target node “D” is selected, the process does the following for the Anchor Pair Selection Step:  
         [0115]    Put in Set 1 all the computing nodes which read the target node. For example, for the following Verilog always block:  
         always @( b  or  c )  a=b+c;    
         [0116]    If “b” is the target node, then this always block, i.e. a computing node, should be put in Set 1.  
         [0117]    Put in Set 2 all the computing nodes which write to the target node. For example, for the following Verilog always block:  
         always @( d  or  e )  b=d+e;    
         [0118]    If “b” is the target node, then this always block, i.e. a computing node, should be put in Set 2.  
         [0119]    Select one node from Set 1 and another node from Set 2. These two nodes are the anchor pair selected.  
         [0120]    Trigger Races  
         [0121]    The above race detection algorithm can also be used to detect a new, third kind of races, called trigger races. Previously, the art defined a race as a situation where a read/write action may happen before or after another read/write action nondeterministically. In this definition, the target being raced for comprises passive objects, i.e. data nodes, such as circuit registers or HDL program variables.  
         [0122]    In trigger races the target is a computing node instead of a data node, such as a circuit element, where the target node can be triggered by the value changes of two or more signals. As a result, the target node could be triggered once or twice, depending on the arrival order of the events, i.e. value changes of signals. This situation in turn could affect the signal values driven by the target, i.e. computing, node.  
         [0123]    The following is an example of trigger races. In the Verilog circuit design of Table 6 below, the target node can be triggered by the value changes of “a” or “b”. Depending on the value change events order of arrival, the register “c” could be increased once or twice, or even set to other values. For example, suppose a, ai, b, and bi are not equal. There are two possible simulation sequences:  
         [0124]    B1 is executed, B2 is executed, and then the target node is executed. In this case, “c” is increased by 1.  
         [0125]    B1 is executed, the target node is executed, then B2 is executed, and finally the target node is executed again. In this case, “c” is increased by 2.  
         [0126]    As a result, the final value of “c” is nondeterministic. This is a trigger race.  
                                                                                                         TABLE 6                       Trigger Race                                    module t(clk, ai, bi);                input clk;           input  ai;           input  bi;           reg   a, b, c;           always @ (posedge clk) b = bi; // B1           always @ (posedge clk) a = ai; // B2           always @ (a or b)  // target node                begin                if (a != b)                c = c + 1;                else                c = 0;                end                endmodule                      
 
         [0127]    Trigger Race Detection Algorithm  
         [0128]    To detect trigger races, the invention uses the general race detection algorithm described above, but performs a different Target Selection Step and Anchor Pair Selection Step.  
         [0129]    To detect trigger races, a target selected in the Target Selection Step should satisfy the following conditions:  
         [0130]    It is a computing node;  
         [0131]    It has two or more trigger nodes; and  
         [0132]    It assigns a value to a register or a latch.  
         [0133]    A register or a latch is a value storage device of a circuit. In contrast, a wire in a circuit is not a storage device.  
         [0134]    To detect trigger races, the Anchor Pairs are selected as follows:  
         [0135]    For a (computing) target node T, find the set D which contains all the data nodes that trigger the target node T.  
         [0136]    For two distinct data nodes D1 and D2 in D,  
         [0137]    find the set S1 which contains all the computing nodes that write to D1;  
         [0138]    find the set S2 which contains all the computing nodes that write to D2;  
         [0139]    select a node from S1 and a node from S2. These two nodes can be an anchor pair.  
         [0140]    Although the invention is described herein with reference to the preferred embodiment, one skilled in the art will readily appreciate that other applications may be substituted for those set forth herein without departing from the spirit and scope of the present invention. Accordingly, the invention should only be limited by the Claims included below.