Abstract:
A communication method apparatus are disclosed, including a common bus; a plurality of multiplexers that communicate with the common bus; a plurality of memories, each in communication with a separate one of the plurality of multiplexers and each having a different storage capacity, that together form a hierarchical storage structure; a bus arbiter that controls access to the common bus; a first interface that communicates information with the common bus; and a second interface that communicates information with the common bus.

Description:
[0001]    This application claims the benefit of Korean Application No. p2001-18599, filed on Apr. 9, 2001, which is hereby incorporated by reference.  
         BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates to a next generation video communication terminal and, more particularly, to a video communication terminal using internal hierarchical memories.  
           [0004]    2. Background of the Related Art  
           [0005]    In an age of multimedia, information is communicated with voice, text, diagrams, and the like centering around video. As a result, the size of the communicated information becomes enormous, thereby making it difficult to store in a storage media of limited capacity and transmit through a transport channel having a small capacity.  
           [0006]    In order to process such multimedia information effectively, compression of the information is absolutely essential. Therefore, various video compression standards have developed.  
           [0007]    ITU-T H.261 Recommendation defines a discrete cosine transform (DCT) based compression algorithm for encoding and decoding video in real-time. H.261 discusses two types of video formats, common intermediate format (CIF) and quarter-CIF (QCIF), as shown in FIG. 1.  
           [0008]    The formats differ only in their respective picture resolution. CIF consists of 352×288 pixels and QCIF has a quarter of the CIF resolution, 176×144 pixels. Since QCIF is a quarter of CIF&#39;s resolution, four QCIF pictures as needed to construct one CIF picture.  
           [0009]    To overcome the limitation of H.261, H.263 is recommended. H.263 is designed for a wide range of bit rates (i.e., 10 Kb/s˜2 Mb/s).  
           [0010]    H.263 Recommendation supports five different picture resolutions. In addition to CIF and QCIF, which are also supported by H.261, there are sub-QCIF (SQCIF), four times CIF (4CIF), and sixteen times CIF (16CIF). SQCIF has approximately one half the resolution of QCIF. And, 4CIF and 16CIF have four and sixteen times greater resolution than CIF, respectively. Support of 4CIF and 16CIF allows for encoding/decoding video in accordance with H.263, so as to compete with other higher bit-rate video coding standards, such as MPEG standards.  
           [0011]    The motion picture expert group (MPEG) has introduced standards for coding (or compression, diversity, etc.) of audiovisual information. MPEG has set up a process to provide an efficient method of reaching adequate standards for audiovisual communications.  
           [0012]    Specifically, the new work item known as MPEG-4 aims to provide a standard to cope with the requirements of current and future multimedia applications. The MPEG-4 standard intends to support a wide range of multimedia applications, which will surely support functionalities such as security, low delay, synchronization, interworking, and the like. Some of the functionalities have already been or are being addressed by a number of other current or emerging standards. Thus, MPEG-4 standard will use similar or improved solutions, so as to address theses functionalities.  
           [0013]    Video communication is carried out using one of the above motion video compression standards. It is a matter of fact that a video input/output format of the common form is used between two communicating terminals for data transformation.  
           [0014]    Specifically, a mobile communication terminal securing mobility and enabling motion video communication uses three common formats, which are shown in FIG. 1, of the five formats recommended by H.263, because a quantity of video data constructing one output screen is small in general.  
           [0015]    [0015]FIG. 1 illustrates diagrams of standard video formats according to a related art. Each format has the illustrated structure, regardless of whether the video information is color or monochrome. Namely, each of the formats is constructed with a luminance block Y and chrominance blocks Cr and Cb. Yet, in the case of monochrome, the chrominance blocks Cr and Cb are fitted with a dummy value.  
           [0016]    [0016]FIG. 2 illustrates a block diagram of a video output structure in a video communication terminal, according to a related art. The structure includes an external bus interface block  10   a  interfacing external buses to an internal bus; an internal static random access memory (SRAM)  12  connected to the internal bus, so as to store video data by a common format unit; a liquid crystal display (LCD) controller  14  reading the video data stored in the internal SRAM  12 , so as to output the read video data to an LCD window, one central processing unit CPU  16 , and a direct memory access (DMA) port  10   b.  DMA port  10   b  provides the LCD controller  14  access to an external memory directly. In the above construction, the external buses interfaced to the internal bus, by the external bus interface block  10   a,  include a synchronous dynamic random access memory (SDRAM) bus and a static memory bus.  
           [0017]    When the video output structure outputs a substantial amount of video data to the LCD, it occupies an excessive amount of the bus bandwidth. More specifically, when video data is outputted to the LCD, the controller should read one frame of video data through the bus every {fraction (1/60)} sec, thereby having a serious effect on the bus bandwidth.  
           [0018]    Many efforts have been made to prevent the performance reduction of a system due to the excessive occupation of the bus bandwidth. One result of these efforts is the system bus structure shown in FIG. 2. The video output process in a video communication terminal is explained by referring to FIG. 2, as follows.  
           [0019]    The external bus interface block  10   a  interfaces the video data, which is transmitted from another terminal, to the internal bus. Additionally, it interfaces video data, which is outputted through the internal bus, to the external bus. The video data is one of the formats shown in FIG. 1.  
           [0020]    The inputted video data are then communicated through the internal bus and stored in the internal SRAM  12 . SRAM  12  has a storage capacity of 152 kbytes. SRAM  12  is installed internally because an internal memory is more advantageous than an external memory, with regard to the bus bandwidth.  
           [0021]    LCD controller  14  reads the video data stored in the internal SDRAM  12  every {fraction (1/60)} sec, through the internal bus, and then outputs the video data to the LCD. If an external memory is required for extra communication, LCD controller  14  brings the data stored in the external memory through DMA port  10   b.  This reduces the load of the bus bandwidth as the video data is outputted to the LCD.  
           [0022]    For motion video transmission, the memory size requirement is changed. For example, a QCIF video transmission needs approximately twice the memory capacity as does a SQCIF video transmission, and a CIF video transmission needs about 4 times more memory capacity than does a QCIF video transmission.  
           [0023]    A size of the video format to be communicated can be established at call set-up by both terminals communicating the data. Yet, after a call has been set up for video communication, the size of the format to be communicated is determined through negotiation, in accordance with the receiving terminal&#39;s performance.  
           [0024]    For instance, if a first terminal can process CIF and a second terminal can process QCIF at best, the video communication between the terminals is processed using QCIF. In this case, the first terminal should use the internal memory, which has a storage capacity sufficient for storing the CIF format, despite the fact that the communication will use the QCIF format, which uses less data. Thereby, some of the internal memory space is unused.  
           [0025]    Preferably, the structure of FIG. 2 should enable the first and second terminals to handle the same video format, thereby optimizing system efficiency.  
           [0026]    Also, if internal SRAM  12  in one terminal has adequate memory to support a CIF video transmission but a second terminal only supports the QCIF video transmission, both terminals communicate using the QCIF video transmission. In such a case, LCD controller  14  only reads the memory area where the QCIF data is stored. During this read operation, LCD controller  14  occupies the access to internal SRAM  12 . Therefore, access to internal SRAM  12  cannot be given to other processing units, such as CPU  16  and the like, at all.  
           [0027]    In other words, the related art structure using one internal SRAM, having a fixed storage capacity, is sub-optimally efficient, considering the current video communication carried out through various formats.  
           [0028]    The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.  
         SUMMARY OF THE INVENTION  
         [0029]    An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.  
           [0030]    Accordingly, an object of the present invention is to provide a video communication terminal and method of controlling memory access.  
           [0031]    Another object of the present invention is to provide a video communication terminal having storage flexibility.  
           [0032]    Another object of the present invention is to provide a video communication terminal using hierarchical memories.  
           [0033]    Another object of the present invention is to provide a video communication terminal to cope with video data transmitted through various formats.  
           [0034]    Another object of the present invention is to effectively control internal memory access inside a terminal.  
           [0035]    Another object of the present invention is to support video communication carried out through various video formats such as CIF, QCIF, SQCIF, or the like.  
           [0036]    To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a video communication terminal according to the present invention includes an internal bus, a plurality of multiplexers connected to the internal bus, a plurality of memories connected to the corresponding multiplexers and having hierarchical storage capacities respectively, and an arbiter controlling access paths to the respective memories.  
           [0037]    In another aspect of the present invention, in a video communication terminal having a plurality of memories having hierarchical storage capacities, a method of controlling memory access in the video communication terminal includes a first step of determining a video format to be communicated through protocol negotiation and giving access paths to inner memories corresponding to a size of the determined video format, a second step of storing a received video format through the given access paths, and a third step of opening the access paths to the inner memories, in which the received video format is stored, to an LCD controller.  
           [0038]    In a further aspect of the present invention, in a video communication terminal having static random access memories (SRAMs) designed to have a storage capacity of a standardized picture resolution common intermediate format (CIF), to which the total storage capacities of the SRAMs are added, a method of controlling access to the SRAMs includes a first step of allocating an access path to the SRAMs, in which a selected video format will be written according to selecting one of CIF, quarter CIF (QCIF), and sub-quarter CIF (SQCIF) as the video format to be communicated through protocol negotiation, and, after the video format is stored in the SRAMs, a second step of allocating an access path to an LCD controller that will read the stored video format.  
           [0039]    The objects of the present invention may be further achieved in whole or in part by a communication apparatus, including a common bus; a plurality of multiplexers that communicate with the common bus; a plurality of memories, each in communication with a separate one of the plurality of multiplexers and each having a different storage capacity, that together form a hierarchical storage structure; a bus arbiter that controls access to the common bus; a first interface that communicates information with the common bus; and a second interface that communicates information with the common bus.  
           [0040]    The objects of the present invention may be further achieved in whole or in part by a communication method, including selecting a first group of a plurality of memories, each having a different storage capacity, based upon the maximum number of memories that may be selected to store a particular amount of information with the least amount of unused storage capacity remaining in the selected memories after the information is stored; and communicating information, through a common bus, between a first interface and the first group of memories.  
           [0041]    Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0042]    The invention will be described in detail with reference to the following drawings in which like reference numerals refer to like elements wherein:  
         [0043]    [0043]FIG. 1 illustrates diagrams of standard video formats according to a related art;  
         [0044]    [0044]FIG. 2 illustrates a block diagram of a video output process, in a video communication terminal according to a related art;  
         [0045]    [0045]FIG. 3 illustrates a block diagram for a memory access control, in a video communication terminal according to the present invention;  
         [0046]    [0046]FIG. 4 illustrates a table of examples for access control, in a hierarchical memory structure according to the present invention; and  
         [0047]    [0047]FIG. 5 illustrates a flowchart for a method of controlling memory access in a video communication terminal. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0048]    [0048]FIG. 3 illustrates a motion video communication terminal, communicating video with the common formats in FIG. 1, in which a portion of a video codec is shown. An inner structure of a video communication terminal according to the present invention includes an internal bus  20 , a multiplexer- 1   30  connected to internal bus  20 , a multiplexer- 2   31  connected to internal bus  20 , a multiplexer- 3   32  connected to internal bus  20 , an internal static random access memory- 1  (SRAM- 1 )  40  connected to multiplexer- 1   30  and having a hierarchical storage capacity, an internal SRAM- 2   41  connected to multiplexer- 2   31  and having a hierarchical storage capacity, an internal SRAM- 3   42  connected to multiplexer- 3   32  and having a hierarchical storage capacity, and an arbiter  50  controlling access paths to internal SRAMs  40 ,  41 , and  42 , respectively. A liquid crystal display (LCD) controller  60  accesses internal SRAMs  40 ,  41 , and  42  entirely or in part, in accordance with the access path control provided by arbiter  50 , so as to read a standardized video format that is currently stored. A CPU  70  receives access authority for internal SRAMs  40 ,  41 , and  42 . An external bus interface block  80   a  interfaces external buses to the internal bus  20 . And, a direct memory access (DMA) port  80   b  allows LCD controller  60  to gain access to an external memory directly. In the above construction, the external buses interfaced to internal bus  20 , by external bus interface block  80   a,  include a synchronous dynamic random access memory (SDRAM) bus and a static memory bus.  
         [0049]    External bus interface block  80   a  interfaces the video data, which is transmitted from another terminal, to internal bus  20 . Additionally, it communicates video data, which is outputted through internal bus  20 , to the external bus. The video data is one of the video formats shown in FIG. 1.  
         [0050]    The video data inputted through the external bus interface block  80   a  is stored in the internal SRAMs  40  to  42  through internal bus  20 .  
         [0051]    The internal SRAMs  40  to  42  are designed with a hierarchical structure. Preferably, internal SRAM- 1   40 , internal SRAM- 2   41 , and internal SRAM- 3   42  have different capacities, such that internal SRAM- 1   40 &lt;internal SRAM- 2   41 &lt;internal SRAM- 3   42 .  
         [0052]    Design examples of internal SRAMs  40 ,  41 , and  42 , according to the present invention, are explained in detail as follows.  
         [0053]    [First Design Example] 
         [0054]    Internal SRAM- 1   40  is designed to have a storage capacity for a standardized picture resolution of sub-quarter common intermediate format (SQCIF). Together, internal SRAM- 2   41  and internal SRAM- 1   40  are designed to have a combined storage capacity for a standardized picture resolution of quarter common intermediate format (QCIF). Together, internal SRAM- 1   40 , internal SRAM- 2   41 , and internal SRAM- 3   42  are designed to have a combined storage capacity for a standardized picture resolution of common intermediate format (CIF). If a count of the internal SRAMs used for the present invention is N, the sum of the internal SRAM capacities SRAM- 1  through SRAM-M is equal to a storage capacity needed to store the standardized picture resolution of M−2 CIF pictures for all integer M, where 3&lt;M≦N.  
         [0055]    [Second Design Example] 
         [0056]    Each of the internal SRAMs  40  to  42  is designed to have a storage capacity amounting to a picture resolution X*CIF, where X is a variable and CIF is the common intermediate format of a picture transformed from its original image. Preferably, internal SRAM- 1   40  is designed to have a storage capacity of SQCIF, internal SRAM- 2   41  is designed to have a storage capacity of QCIF, and internal SRAM- 3   42  is designed to have a storage capacity of CIF. Preferably, if a count of the internal SRAMs used for the present invention is N, an internal SRAM-M is designed to have a storage capacity of (M−2)*CIF, for every integer value of M where 3&lt;M≦N.  
         [0057]    LCD controller  60  reads the video data stored in internal SRAMs  40  to  42 , through the bus, every {fraction (1/60)} sec, so as to output the read data to an LCD (not shown in the drawing). When the use of the external memory is required for extra communication, LCD controller  60  brings the data stored in the external memory through DMA port  80   b.    
         [0058]    Arbiter  50  controls the access paths to the respective internal SRAMs  40  to  42  so that LCD controller  60  may provide the video data stored in the internal SRAMs  40  to  42  to the LCD. Arbiter  50  also provides CPU  70  access to internal SRAMs  40  to  42 .  
         [0059]    Examples of the memory access control performed by arbiter  50  in the video communication terminal according to the present invention are explained as follows, by referring to the above-described first design example of internal SRAMs  40  to  42 .  
         [0060]    [First Example] 
         [0061]    The video communication terminal according to the present invention communicates with a terminal supporting the video transmission of a picture having the SQCIF resolution. Arbiter  50  allocates the path of multiplexer- 1   30 , connected to internal SRAM- 1   40 , for the video communication and allocates the paths of multiplexer- 2   31  and multiplexer- 3   32 , connected to internal SRAM- 2   41  and internal SRAM- 3   42 , respectively, for the process of CPU  70 , when the CPU  70  demands the use of internal SRAM- 2   41  and internal SRAM- 3   42 .  
         [0062]    If a count of the internal SRAMs used in the video communication terminal is N, paths of multiplexer- 2  to multiplexer-N, connected to internal SRAM- 2  to internal SRAM-N, are allocated to CPU  70 , when CPU  70  requests the use of the internal memories for an output process.  
         [0063]    Through the above first example describing the sizing of internal SRAMs  40  to  42 , another case of the video communication between terminals supporting video transmissions of QCIF and SQCIF, respectively, can be understood with ease, whereby much of the corresponding explanation is skipped.  
         [0064]    [Second Example] 
         [0065]    The video communication terminal according to the present invention communicates with a terminal supporting the QCIF video transmission. Arbiter  50  allocates the paths of multiplexer- 1   30  and multiplexer- 2   31 , connected to internal SRAM- 1   40  and internal SRAM- 2   41 , respectively, for the video communication. Arbiter  50  allocates the path of multiplexer- 3   32 , connected to internal SRAM- 3   42 , for the process of CPU  70 , when CPU  70  request the use of internal SRAM- 3   42 . If a count of the internal SRAMs used in the video communication terminal is N, paths of multiplexer- 3  to multiplexer-N, connected to internal SRAM- 3  to internal SRAM-N, are allocated to CPU  70 , when CPU  70  requests the use of the internal memories for an output process.  
         [0066]    Through the above first example, another case of the video communication between terminals, supporting video transmissions of CIF, is explained below. If a count of the internal SRAMs used in the video communication terminal is N, arbiter  50  allocates the paths of multiplexer- 1   30  to multiplexer- 3   32 , connected to internal SRAM- 1   40  to internal SRAM- 3   42 , respectively, for the video communication. Arbiter  50  allocates the rest of the multiplexer paths, connected to the rest of the internal SRAMs, for CPU  70 , when CPU  70  requests the use of the internal memories for an output process.  
         [0067]    Explained below is a procedure of controlling memory access in the course of communicating with another terminal, using the video communication terminal according to the present invention.  
         [0068]    [0068]FIG. 5 illustrates a flowchart for a method of controlling memory access in a video communication terminal. A video communication terminal according to the present invention and the other terminal determine, together, a video format to communicate through protocol negotiation (S 1 , S 2 ). The video communication terminal according to the present invention tries to determine the video format the other terminal can process.  
         [0069]    Arbiter  50  allocates access paths to the internal SRAMs corresponding to the size of the determined video format (S 3 ). For example, if the video format the other terminal can process is SQCIF, the access path is allocated to internal SRAM- 1 , which has just enough memory to store a SQCIF picture. If the video format the other terminal can process is QCIF, arbiter  50  allocates access paths to internal SRAM- 1   40  and internal SRAM- 2   41 , concurrently. Further, if the video format the other terminal can process is CIF, the access paths are allocated to internal SRAM- 1   40 , internal SRAM- 2   41 , and internal SRAM- 3   42 , concurrently.  
         [0070]    If a predetermined video format is received from the other terminal (S 4 ), the received video format is written through the allocated path(s) (S 5 ). Thereafter, an access path to the internal SRAMs, in which the received video format is written, is closed to internal bus  20  and opened to LCD controller (S 6 ). LCD controller  60  then reads the received video format from the internal SRAMs (S 7 ).  
         [0071]    If an access request for the internal SRAMs is generated from CPU  70  (S 8 ), arbiter  50  checks whether any spare internal SRAMs exist, or not, and then allocates an access path to the spare internal SRAM(s) for CPU  70  (S 9 , S 10 ). A spare internal SRAM is one that is not being accessed currently by internal bus  20  or LCD controller  60 . If no spare internal SRAM is available, the access request generated by CPU  70  is ignored (S 11 ).  
         [0072]    Preferably, when the video format the other terminal can process is SQCIF and internal bus  20  or LCD controller  60  has gained access to the corresponding internal SRAM- 1   40 , arbiter  50  opens the access paths to internal SRAM- 2   41  and internal SRAM- 3   42  for CPU  70 , if an access request for the internal SRAMs is generated from CPU  70 .  
         [0073]    When the video format the other terminal can process is QCIF and internal bus  20  or LCD controller  60  has gained access to the corresponding internal SRAM- 1   40  and internal SRAM- 2   41 , arbiter  50  opens the access path to internal SRAM- 3   42  for CPU  70 , if the access request for the internal SRAMs is generated from CPU  70 .  
         [0074]    [0074]FIG. 4 illustrates a table of examples for access control in a hierarchical memory structure, according to the present invention and the above-described first design example of the internal SRAMs  40  to  42 .  
         [0075]    Referring to FIG. 4, example-1 is a case that the terminal has no input/output. In this case, paths of all internal SRAMs  40 - 42  are fixed to internal bus  20 , so as to be excluded from the influence of LCD controller  60 . Preferably, arbiter  50  sets the path control values for all multiplexers to a value of ‘1’ so that multiplexers  30 - 32  communicate with internal bus  20  and not LCD controller  60 .  
         [0076]    Example-2 is a case where the video communication terminal, according to the present invention, communicates with the terminal supporting the SQCIF video transmission. Internal SRAM- 1   40  is used for the LCD output memory and paths of internal SRAM- 2   41  and internal SRAM- 3   42  are fixed to internal bus  20  only. Preferably, arbiter  50  controls the ‘on/off’ value of multiplexer- 1   30  in accordance with the video input/output and control path values of multiplexer- 2   31  and multiplexer- 3   32  to have values ‘1’ so that these multiplexers communicate with internal bus  20 . Preferably, the path value of multiplexer- 1   30  to internal bus  20  is ‘1’ when the SQCIF video data is written in internal SRAM- 1   40 , and the path value of multiplexer- 1   30  to internal bus  20  is ‘0’ when LCD controller  60  reads the SQCIF video data from internal SRAM- 1   40 .  
         [0077]    Example-3 is a case where the video communication terminal, according to the present invention, communicates with a terminal supporting the QCIF video transmission. Internal SRAM- 1   40  and internal SRAM- 2   41  are used for the LCD output memories and the path of internal SRAM- 3   42  is designated (fixed) for use by internal bus  20  only. Preferably, arbiter  50  controls the ‘on/off’ path access of multiplexer- 1   30  and multiplexer- 2   31  in accordance with the video input/output. A path value of multiplexer- 3   32  to internal bus  20  is set to ‘1’. Preferably, the respective path values of multiplexer- 1   30  and multiplexer- 2   31  to the internal bus  20  are ‘1’, when the QCIF video data are written in internal SRAM- 1   40  and internal SRAM- 2   41 . The respective path values of multiplexer- 1   30  and multiplexer- 2   31  to internal bus  20  are ‘0’ when LCD controller  60  reads the QCIF video data from internal SRAM- 1   40  and internal SRAM- 2   41 .  
         [0078]    Example-4 is a case where the video communication terminal, according to the present invention, communicates with a terminal supporting the CIF video transmission. Here, all of internal SRAM- 1   40  through internal SRAM- 3   42  are used for the LCD output memories. Preferably, arbiter  50  controls the ‘on/off’ path access of multiplexer- 1   30  to multiplexer- 3   32  in accordance with the video input/output. Preferably, the respective path values of multiplexer- 1   30  to multiplexer- 3   32  to internal bus  20  are ‘1’, when the CIF video data are written in internal SRAM- 1   40  to internal SRAM- 3   42 . The respective path values of multiplexer- 1   30  to multiplexer- 3   32  to internal bus  20  ate ‘0’ when LCD controller  60  reads the CIF video data from internal SRAM- 1   40  to internal SRAM- 3   42 .  
         [0079]    In the above-explained examples, illustrated by FIG. 4, when the path of the internal SRAM is fixed to internal bus  20  only, other components inside the terminal such as CPU  70  and the like may use the internal SRAM. Thus, LCD controller  60  and CPU  70  can use separate internal SRAMs in parallel, when the video communication terminal according to the present invention communicates with terminals.  
         [0080]    Accordingly, the video communication terminal and method of controlling memory access, in the same, has the following advantages or effects.  
         [0081]    The terminal according to the present invention is realized by the hierarchical memory structure, thereby enabling it to provide flexibility in the use of internal memories even if the video data are transmitted using various formats.  
         [0082]    Moreover, the present invention controls the access to the internal memories, generated inside the terminal, effectively, thereby enabling it to maximize an efficiency of the internal SRAMs, even when communicating with various video formats such as CIF, QCIF, SQCIF or the like.  
         [0083]    The foregoing embodiments and advantages are merely exemplary and are not to be construed as limiting the present invention. The present teaching can be readily applied to other types of apparatuses. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures.