Abstract:
A method for fabricating a floating gate memory device comprises using a buried diffusion oxide that is below the floating gate thereby producing an increased step height between the floating gate and the buried diffusion oxide. The increased step height can produce a higher GCR, while still allowing decreased cell size using a virtual ground array design.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a divisional application of U.S. patent application Ser. No. 11/534,143, filed Sep. 21, 2006, and titled “Apparatus and Associated Method for Making a Floating Gate Cell With Increased Overlay Between the Control Gate and Floating Gate,” which is hereby incorporated by reference for all purposes. 
     
    
     BACKGROUND 
       [0002]    1. Field of the Invention 
         [0003]    The embodiments described herein are directed to methods for fabricating non-volatile memory devices, and more particularly to methods for fabricating floating-gate memory devices using virtual ground arrays. 
         [0004]    2. Background of the Invention 
         [0005]      FIG. 1  is a schematic representation of a conventional floating gate memory cell  100 . Memory cell  100  comprises a substrate  102  with diffusion regions  104  and  106  formed therein. The diffusion regions correspond to the source and drain of FET-type device. According to one example, substrate  102  can be a P-type substrate and diffusion regions  104  and  106  can be N-type diffusion regions. In other embodiments, cell  100  can comprise an N-type substrate  102  with P-type diffusion regions  104  and  106 . Although it will be understood that a P-type substrate is generally preferred. 
         [0006]    Cell  100  further comprises a gate dielectric layer, sometimes referred to as a tunnel dielectric layer  108  formed over substrate  102  between diffusion regions  104  and  106 . A floating gate  110  is then formed over gate dielectric  108 . Floating gate  110  is typically formed from a polysilicon. An inter-polysilicon (poly) dielectric layer  112  then separates floating gate  110  from a control gate  114 . Control gate  114  is also typically formed from polysilicon. Inter-poly dielectric layer  112  can be formed from, e.g., a silicon dioxide (SiO 2 ) material. In other embodiments, inter-poly dielectric  110  can comprise a multi-layer structure such as an Oxide-Nitride-Oxide (ONO) structure. 
         [0007]    In operation, a high voltage is applied to control gate  114  in order to program cell  100 . This voltage is coupled with floating gate  110  via a control gate capacitance (C CG ). The coupled voltage causes an inversion channel to be formed in the upper layer of substrate  102  between diffusion regions  104  and  106 . Voltages are then applied to diffusion regions  104  and  106  so as to create a large lateral electric field that will cause carriers to flow through the channel, e.g., from one diffusion region towards the other. 
         [0008]    The voltage coupled with floating gate  110  will create an electric field sufficient to cause some of the carriers to tunnel through gate dielectric  108  into floating gate  110 . In other words, the voltage coupled with floating gate  110  needs to be capable of producing an electric field that can supply the carriers with enough energy to allow them to overcome the barrier height of gate dielectric  108 . Accordingly, as mentioned above, sufficient coupling between control gate  114  and floating gate  110  is required in order to ensure that an adequate field is present to induce carriers to pass through gate dielectric  108  onto floating gate  110 . 
         [0009]    It is well known to use virtual ground array designs in order to reduce the cell size for floating gate memory cells and non-volatile memory products, such as flash memory products. Smaller cell sizes, however, often require smaller buried diffusion sizes, which are not necessarily compatible with conventional processing techniques. 
         [0010]    For example, one problem that can occur as a result of the reduced buried diffusion sizes with conventional fabrication techniques is a reduced gate coupling ratio (GCR) between the control gate and floating gate. Sufficient coupling is needed in order to ensure that an adequate field is present in the memory cell to induce carriers to pass through the tunnel oxide layer into the floating gate. 
         [0011]    As is understood, the GCR is a function of the C c  as well as the Source Capacitance (C S ), Bulk Capacitance (C B ), and Drain Capacitance (C D ) illustrated in  FIG. 1 . The relationship is defined as: 
         [0000]        GCR=C   CG /( C   S   +C   B   +C   D   +C   CG ) 
         [0012]    Accordingly, the GCR can be increased by increasing C CG , or by decreasing the Source Capacitance (C S ) or Drain Capacitance (C D ). Thus, by increasing the distance between floating gate  110  and buried diffusion regions  104  and  106 , source and drain capacitances (C S , C D ) can be decreased. As a result, the gate coupling ratio (GCR) of the memory device can be improved. Accordingly, it is important to maintain adequate GCR in virtual ground arrays, despite the smaller buried diffusion sizes. 
       SUMMARY 
       [0013]    A method for fabricating a floating gate memory device comprises using a buried diffusion oxide that is below the floating gate thereby producing an increased step height between the floating gate and the buried diffusion oxide. The increased step height can produce a higher GCR, while still allowing decreased cell size using a virtual ground array design. 
         [0014]    These and other features, aspects, and embodiments of the invention are described below in the section entitled “Detailed Description.” 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]    Features, aspects, and embodiments of the inventions are described in conjunction with the attached drawings, in which: 
           [0016]      FIG. 1  is a schematic diagram illustrating a cross-sectional view of a conventional floating gate memory cell; 
           [0017]      FIG. 2  is a schematic diagram illustrating a cross-sectional view of a floating gate memory device fabricated using a conventional fabrication process; 
           [0018]      FIG. 3  is a schematic diagram illustrating a cross-sectional view of a floating gate memory device fabricated using a conventional fabrication process that does not include a fourth poly step; 
           [0019]      FIG. 4  is a schematic diagram illustrating a cross-sectional view of a floating gate memory cell fabricated in accordance with one embodiment; and 
           [0020]      FIGS. 5A-5G  are schematic diagrams illustrating an exemplary process for fabricating the floating gate memory device of  FIG. 4  in accordance with one embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0021]    In the methods described below, an increased GCR in a scaled virtual ground cell is provided by fabricating the cell in order to produce a large step height between the floating gate and the buried diffusion oxide. As a result, a larger overlay region can be maintained between the control gate and floating gate, which increases the GCR. 
         [0022]      FIG. 2  is a schematic diagram illustrating a cross-sectional view of a conventional floating gate memory device fabricated using a conventional process. As can be seen, device  200  comprises a substrate  202  with diffusion regions  216  implanted therein. A dielectric layer  204  (i.e., a tunnel oxide layer) is formed on substrate  202 . Floating gates for the various cells in device  200  are then formed from polysilicon layers  206  and  208 . These layers can be referred to as the first and fourth poly layers respectively. Buried diffusion oxides  214  are formed over diffusion region  216  and Oxide-Nitride-Oxide (ONO) layer  210 , i.e., an inter-poly dielectric, is then formed over fourth poly layer  208 . It will be understood that buried diffusion oxides  214  correspond with buried diffusion lines that run through the array. 
         [0023]    A control gate polysilicon layer  212 , i.e., the second poly layer, is then formed on ONO layer  210 . As mentioned, as buried diffusion regions  216  decrease in size, the coupling between the control gate and the floating gate is reduced.  FIG. 3  is a diagram illustrating a floating gate memory device constructed using a conventional process that does not include fourth poly layer  208 ; however, it can be shown that simply eliminating fourth poly layer  208  is not sufficient to provide adequate GCR to make an effective memory device. 
         [0024]    Accordingly,  FIG. 4  is a diagram illustrating a floating gate memory device  400  fabricated in accordance with the embodiments described herein. As can be seen, device  400  comprises buried diffusion oxides  420 , wherein the step height (h) between the top of ONO layer  422  above floating gate layer  406  and the top of ONO layer  422  above buried diffusion oxide  420  is larger than in  FIGS. 2 and 3  where the top of floating gate  206  is below the top of buried diffusion oxide  214 . In  FIG. 4 , polysilicon layer  424 , i.e., the second poly layer, overlays ONO layer  422 , i.e., the inter-poly dielectric, which is formed on top of floating gates  406 . The increased step height (h) produces a greater GCR due to the larger overlay between the control gate and floating gate that can then be achieved. 
         [0025]    It should be noted that while an ONO layer  422  is illustrated in the example of  FIG. 4 , layer  422  can be seen as simply a dielectric layer. Accordingly, the example of  FIG. 4  should not be seen as limiting the devices and methods described herein to the use of a particular type of dielectric layer, e.g., an ONO layer  422 , and it will be understood that any suitable dielectric layer can be used. 
         [0026]      FIGS. 5A-5G  are diagrams illustrating an exemplary process for fabricating a device  400  in accordance with one embodiment. First, in  FIG. 5A , a dielectric layer  504 , i.e., tunnel oxide, is formed on substrate  502 . For example, dielectric layer  504  may comprise silicon dioxide (SiO 2 ). After this, a first poly layer  506  is deposited. First poly layer  506  can be anywhere from approximately 600 Å to 1400 Å. A silicon nitride layer  508  can then be deposited on first poly layer  506 . 
         [0027]    As illustrated in  FIG. 5B , a photoresist  510  can then be used to pattern silicon nitride layer  508 , first poly layer  506 , and dielectric layer  504 . Patterned layers  506 ,  508 , and  504  can then be etched as illustrated in  FIG. 5B . The etching process should produce a slight recess in substrate  502  at the bottom of etched regions  514  created during the etching process. Thus, for example, the etching process can be similar to that used for Shallow Trench Isolation (STI) structure formation; however, it will be understood that the recesses created will be more shallow than the trenches produced in STI formation. 
         [0028]    Diffusion regions  512  can then be implanted and heat driven in substrate  502 . For example, if substrate  502  is a P-type substrate, then N+ diffusion regions  512  can be implanted in the P-type substrate  502 . Since silicon nitride layer  508  and first poly layer  506  act as an implant mask, this process is self-aligned. 
         [0029]    Referring to  FIG. 5C , a dielectric layer  516  is then formed over substrate  502  as illustrated. Dielectric layer  516  can be, for example, a SiO 2  layer and can be formed using High Density Plasma (HDP)-CVD. Referring to  FIG. 5D , a portion of dielectric layer  516  is removed to expose the remaining portions of silicon nitride layer  508  and part of the remaining portions of polysilicon layer  506 . For example, a conventional wet etching, such as HF or BOE solution (i.e., isotropic), process can be used to remove a portion of dielectric layer  516 . Removing the right amount of dielectric layer  516  can be achieved by having a high etching selectivity ratio between dielectric layer  516  and silicon nitride layer  508 . 
         [0030]    The etching process also produces oxide regions  520 , which can form the buried diffusion oxides for the device. 
         [0031]    Referring to  FIG. 5E , the remaining portions of silicon nitride layer  508  can then be removed, removing portions  518  of dielectric layer  516  in the process. For example, hot phosphoric acid can be used to remove the remaining portions of silicon nitride layer  508 . Portions  518  of dielectric layer  516  will automatically be removed during the removal of the remaining portions of silicon nitride layer  508  because portions  518  are disconnected from the rest of dielectric layer  516 . 
         [0032]    ONO layer  522  can then be formed over substrate  502  as illustrated in  FIG. 5F . It will be understood that formation of an ONO layer  522  comprises the deposition/formation of a plurality of layers in sequence. These layers typically comprise an oxide layer, a nitride layer, such as a silicon nitride layer (SiN), and another oxide layer. Although, as mentioned above, certain embodiments can make use of an alternative inter-dielectric layer, in which case formation of layer  522  comprises formation of the alternative inter-dielectric material. 
         [0033]    A polysilicon layer  524  can then be formed over ONO layer  522  as illustrated in  FIG. 5G . Polysilicon layer  524  is the second poly layer and can be formed, e.g., using CVD. 
         [0034]    Device processing can continue in accordance with conventional process techniques after the steps illustrated in  FIG. 5G . These steps can include the patterning and etching of the second poly layer, formation of a third poly layer, and patterning and etching of the third poly layer. Conventional Back End of the Line (BEOL) processing techniques can then be used to form the required metal interconnect layers. 
         [0035]    While certain embodiments of the inventions have been described above, it will be understood that the embodiments described are by way of example only. Accordingly, the inventions should not be limited based on the described embodiments. Rather, the scope of the inventions described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.