Abstract:
A delay locked loop (DLL) for compensating for a skew in a synchronous dynamic random access memory includes: a delay model means for delaying an external clock signal by the skew to generate a delayed clock signal; a control unit, in response to the external clock signal and the delayed clock signal, for generating control signals, wherein the control signal includes a control clock signal, a delayed control signal, a replication signal and replication enable signal; a first voltage controlled oscillator, in response to the control clock signal and the delayed control signal, for generating a measurement oscillating signal; a second voltage controlled oscillator, in response to the replication signal and the replication enable signal, for generating a replication oscillating signal; a first unit, in response to the measurement oscillating signal and the replication oscillating signal, for generating a DLL clock signal; and a second unit for comparing a phase difference between the DLL clock signal and the external clock signal to generate a voltage control signal, wherein time periods of the measurement oscillating signal and the replication oscillating signal are changed by the voltage control signal.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to a semiconductor integrated circuitry; and, more particularly, to a delay locked loop for use in synchronous dynamic random access memory, which is capable of obtaining a fast locking time and a reduced jitter.  
         DESCRIPTION OF THE PRIOR ART  
         [0002]    For achieving a high speed operation in a semiconductor memory device, a synchronous dynamic access memory (SDRAM) has been developed. The SDRAM operates in synchronization with an external clock signal. The SDRAM includes a single data rate (SDR) SDRAM, a double data rate (DDR) SDRAM, and the like.  
           [0003]    Generally, when data are outputted in synchronization with the external clock signal, a skew between the external clock signal and the output data is occurred. In the SDRAM, a delay locked loop (DLL) can be used to compensate for the skew between an external clock signal and an output data, or an external clock signal and an internal clock signal.  
           [0004]    A digital DLL is implemented with a plurality of unit delay elements that are coupled in series. For increasing a resolution, a unit delay time should be minimized. As the unit delay time becomes smaller, however, more unit delay elements are needed. Consequently, power consumption as well as a chip size is increased much more.  
         SUMMARY OF THE INVENTION  
         [0005]    It is, therefore, an object of the present invention to provide a delay locked loop which is capable of obtaining a fast locking time and a reduced jitter by combining a digital locking operation with an analog locking operation.  
           [0006]    In accordance with an aspect of the present invention, there is provided a delay locked loop (DLL) for compensating for a skew in a synchronous dynamic random access memory, comprising: a delay model means for delaying an external clock signal by the skew to generate a delayed clock signal; a control means, in response to the external clock signal and the delayed clock signal, for generating control signals, wherein the control signal includes a control clock signal, a delayed control signal, a replication signal and a replication enable signal; a first voltage controlled oscillation means, in response to the control clock signal and the delayed control signal, for generating a measurement oscillating signal; a second voltage controlled oscillation means, in response to the replication signal and the replication enable signal, for generating a replication oscillating signal; a first means, in response to the measurement oscillating signal and the replication oscillating signal, for generating a DLL clock signal; and a second means for comparing a phase difference between the DLL clock signal and the external clock signal to generate a voltage control signal, wherein time periods of the measurement oscillating signal and the replication oscillating signal are changed by the voltage control signal. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]    Other objects and aspects of the invention will become apparent from the following description of the embodiments with reference to the accompanying drawings, in which:  
         [0008]    [0008]FIG. 1 is a timing chart for explaining a principle of a DLL;  
         [0009]    [0009]FIG. 2 is a block diagram illustrating a DLL in accordance with the present invention;  
         [0010]    [0010]FIG. 3 is a circuit diagram illustrating a VCO shown in FIG. 2;  
         [0011]    [0011]FIG. 4 is a circuit diagram illustrating a mirror VCO shown in FIG. 2;  
         [0012]    [0012]FIG. 5 is a circuit diagram illustrating a transition count/replication controller shown in FIG. 2;  
         [0013]    [0013]FIG. 6 is a circuit diagram illustrating a register shown in FIG. 5; and  
         [0014]    [0014]FIG. 7 is a timing chart of a DLL in accordance with the present invention.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0015]    [0015]FIG. 1 is a timing chart for explaining a principle of a DLL. Here, t ck  denotes a time period of an external clock signal CLK.  
         [0016]    As shown, when data is outputted in synchronization with the external clock signal CLK, a skew t d1  between the external clock signal CLK and an output date D out  is caused. The skew t d1  can be compensated by outputting the data in synchronization with an internal clock signal DLL_CLK that precedes the external clock signal CLK by the skew t d1 . At this time, the internal clock signal DLL_CLK is obtained by delaying the external clock signal CLK by a predetermined time t d2  corresponding to (t ck -t d1 ). This internal clock signal DLL_CLK is referred to as a DLL clock signal. Consequently, if the data is outputted in synchronization with the DLL clock signal, and output data D out , is synchronized with the external clock signal CLK.  
         [0017]    [0017]FIG. 2 is a block diagram illustrating a delay locked loop (DLL) in accordance with the present invention.  
         [0018]    Referring to FIG. 2, the DLL in accordance with the present invention includes a first delay model  200 , a control unit  210 , a voltage controlled oscillator (VCO)  220 , a mirror VCO  230  and a transition count/replication controller  240 . Furthermore, the DLL includes a second delay model  250 , a phase detector  260 , a charge pump  270  and a low pass filter (LPF)  280 .  
         [0019]    The first delay model  200  delays an external clock signal CLK by a skew t d2  between the external clock signal CLK and an output data to generate a delayed clock signal CLK_D.  
         [0020]    The control unit  210  receives the external clock signal CLK and the delayed clock signal CLK_D to generate control signals. The control signals include a control clock signal CLK 2 , a delayed control signal /CLK_D 2 , a replication signal /REPLICA and a replication enable signal REP_EN.  
         [0021]    Here, the control clock signal CLK 2  is enabled to a high level from a first rising edge to a second rising edge of the external clock signal CLK, so that the control clock signal CLK 2  has a time period two times as long as the external clock signal CLK. The delayed control signal /CLK_D 2  is enabled to a low level from a first rising edge to a second rising edge of the delayed clock signal CLK_D, so that the delayed control signal /CLK_D 2  has a time period two times as long as the delayed clock signal CLK_D.  
         [0022]    The replication enable signal REP_EN is used to activate the mirror VCO  230 , and the replication signal /REPLICA is a control signal used to toggle a replication oscillating signal R_OSC.  
         [0023]    The VCO  220  performs an oscillation operation to generate a measurement oscillating signal M_OSC in response to the control clock signal CLK 2  and the delayed control signal /CLK_D 2 . The measurement oscillating signal M_OSC is toggled while both the control clock signal CLK 2  and the delayed control signal /CLK_D 2  are enabled. At this time, a time period of the measurement oscillating signal M_OSC is changed according to a voltage control signal Vcon that is outputted form the charge pump  270 .  
         [0024]    The mirror VCO  230  performs an oscillation operation to generate a replication oscillating signal R_OSC in response to the replication signal /REPLICA and the replication enable signal REP_EN. The replication oscillating signal R_OSC is toggled while both the replication signal /REPLICA and the replication enable signal REP_EN are enable. A time period of the replication oscillating signal R_OSC is also changed according to the voltage control signal Vcon.  
         [0025]    The transition count/replication controller  240  generates the DLL clock signal DLL_CLK in response to the measurement oscillating signal M_OSC and the replication oscillating signal R_OSC.  
         [0026]    The second delay model  250  delays the DLL clock signal DLL_CLK by the skew t d1  to generate a comparison clock signal COMP_CLK.  
         [0027]    The phase detector  260 , in response to a phase detection enable signal EN_PD, compares a phase difference between the external clock signal CLK and the comparison clock signal COMP_CLK to generate an up pulse signal UP and a down pulse signal DN according to the phase difference.  
         [0028]    The charge pump  270  generates the voltage control signal Vcon in response to the up pulse signal UP and the down pulse signal DN. At this time, the voltage control signal Vcon is fed back to the VCO  220  and the mirror VCO  230 , to thereby change the time period of the measurement oscillating signal M_OSC and the replication oscillating signal R_OSC.  
         [0029]    The LFP  280  removes high-frequency noise components of the voltage control signal Vcon.  
         [0030]    [0030]FIG. 3 is a circuit diagram illustrating the VCO  220  shown in FIG. 2.  
         [0031]    Referring to FIG. 3, the VCO  220  includes a NOR gate NOR 31 , a delay control unit  32 , a NAND gate ND 31 , a delay unit  31  and an inverter INV 34 . The delay control unit  32  can be implemented with voltage controlled delay (VCD) elements  310  and  320 , and the delay unit  31  can be implemented with a predetermined number of inverters INV 31  to INV 33 .  
         [0032]    The delayed control signal /CLK_D 2  and an output signal of the delay unit  31  are NORed through the NOR gate NOR 31 , and the delay control unit  32  delays an output signal of the NOR gate NOR 31  in response to the voltage control signal Vcon.  
         [0033]    The control clock signal CLK 2  and an output signal of the delay control unit  32  are NANDed through the NAND gate ND 31 , and an output signal of the NAND gate ND 31  is inverted and delayed through the delay unit  31 . At this time, the output signal of the delay unit  31  is feedback to the NOR gate NOR 31 . The inverter INV 34  inverts the output signal of the NAND gate ND 31  to output the measurement oscillating signal M_OSC.  
         [0034]    [0034]FIG. 4 is a circuit diagram illustrating the mirror VCO  230  shown in FIG. 2.  
         [0035]    Referring to FIG. 4, the mirror VCO  220  includes a NOR gate NOR 41 , a delay control unit  42 , a NAND gate ND 41 , a delay unit  41  and an inverter INV 44 . The delay control unit  42  can be implemented with voltage controlled delay (VCD) elements  410  and  420 , and the delay unit  41  can be implemented with a predetermined number of inverters INV 41  and INV 43 .  
         [0036]    The replication clock /REPLICA and an output signal of the delay unit  41  are NORed through the NOR gate NOR 41 , and the delay control unit  42  delays an output signal of the NOR gate NOR 41  in response to the voltage control signal Vcon. During an initial digital locking operation, the voltage control signal Vcon has a predetermined voltage level.  
         [0037]    The replication enable signal and an output signal of the delay control unit  42  are NANDed through the NAND gate ND 41 , and an output signal of the NAND gate ND 41  is inverted and delayed through the delay unit  41 . At this time, the output signal of the delay unit  41  is feedback to the NOR gate NOR 41 . The inverter INV 44  inverts the output signal of the NAND gate ND 41  to output the replication oscillating signal M_OSC.  
         [0038]    [0038]FIG. 5 is a circuit diagram illustrating the transition count/replication controller  240  shown in FIG. 2.  
         [0039]    Referring to FIG. 5, the transition count/replication controller  240  includes a delay measurement unit  500  and a delay replication unit  510 .  
         [0040]    The delay measurement unit  500  includes a plurality of delay units  312  and  315  and registers  531  and  535 . The delay units shift a low level of the delayed control signal /CLK_D 2  to the nodes M 0  to M 4  in response to the measurement oscillating signal M_OSC. The registers  531  to  535  store shifted low levels on the nodes M 0  to M 4  while the control clock signal CLK 2  is a high level. The shifted low levels that are stored in the registers  531  to  535  are outputted to the delay replication unit  510  in response to the control clock signal CLK 2 .  
         [0041]    At this time, the skew t d2  to be measured corresponds to a time interval between a falling edge of the delayed control signal /CLK_D 2  to a falling edge of the control clock signal CLK 2 .  
         [0042]    The delay replication unit  510  performs a logic operation with respect to output signals of the registers  531  to  535  to generate locking signals I 1  to I 5 . In response to the locking signals I 1  to I 5 , the delay replication unit  510  shifts the replication signal /REPLICA according to the replication oscillating signal R_OSC, to thereby generate the replication reset signal REP_RST and the DLL clock signal DLL_CLK.  
         [0043]    [0043]FIG. 6 is a circuit diagram illustrating the registers  531  to  535  shown in FIG. 5.  
         [0044]    Referring to FIG. 6, each register  531  to  535  includes an input unit  610 , which has an input terminal receiving a voltage level of corresponding node M 0  to M 4  and a clock terminal receiving the control clock signal CLK 2 , a storage unit  630  for storing an output signal of the input unit  610 , and an inverter INV 65  for inverting an output signal of the storage unit  630 .  
         [0045]    The input unit  610  includes an inverter INV 61  for receiving the voltage level IN of corresponding node M 0  to M 4  to output an inverted voltage level and a transmission gate TG 61  for transmitting the inverted voltage level in response to the control clock signal CLK 2 . The storage unit  630  includes an inverter INV 63  whose input terminal receives the output signal of the transmission gate TG and an inverter INV 64  whose input terminal and whose output terminal are coupled to an output terminal and the output terminal of the inverter INV 63 , respectively.  
         [0046]    [0046]FIG. 7 is a timing chart illustrating the DLL in accordance with the present invention.  
         [0047]    Hereinafter, an operation of the DLL in accordance with the present invention will be described with reference to FIGS.  2  to  7 .  
         [0048]    While the control clock signal CLK 2  and the delayed control signal /CLK_D 2  are a high level and a low level, respectively, the VCO  220  performs the oscillation operation so that the measurement oscillating signal M_OSC is toggled. Therefore, the low level of the delayed control signal /CLK_D 2  is shifted to the nodes M 0  to M 4  in response to the measurement oscillating signal M_OSC.  
         [0049]    That is , the low level is transferred to the node M 0  at a first rising transition of the measurement oscillating signal M_OSC, and then, the low level is transferred to the node M 1  at a first falling transition of the measurement oscillating signal M_OSC. Then, the low level is transferred to the node M 2  at a second rising transition of the measurement oscillating signal M_OSC. In this manner, the low level is continuously transferred to next nodes until the control clock signal CLK 2  becomes a low level.  
         [0050]    The skew t d2  is measured by the number of the level transitions of the measurement oscillating signal M_OSC. For example, if the level transition is occurred three times, the low level is transferred to the node M 2  so that only the registers  531  to  533  store the low level. Thus, only a third locking signal I 3  becomes a high level and the inverted flag signal /FLAG_RF becomes a low level.  
         [0051]    Then, if the replication signal /REPLICA is activated to a low level, the replication oscillating signal R_OSC is toggled and the low level is sequentially transferred through the nodes R 4 , R 3  and R 2 . At the node R 2 , there are two paths. A first path is to transfer the low level through the nodes R 00  and R_F and a second path is to transfer the low level through the nodes R 1 , R 0  and R_R.  
         [0052]    At this time, since the inverted flag signal /FLAG_RF is a low level, the first path is disabled by the NAND gate ND 51  so that the low level is transferred through the second path, thereby generating the DLL clock signal DLL_CLK. The above-described procedure is called a digital locking operation. The voltage control signal Vcon has a predetermined voltage level until this digital locking operation is completed.  
         [0053]    After the digital locking operation, an analog locking operation is then carried out as follows.  
         [0054]    The second delay model  250  delays the DLL clock signal DLL_CLK by the skew t d1  to generate the comparison clock signal COMP_CLK.  
         [0055]    In response to the phase detector enable signal EN_PD, the phase detector  260  compares the phase difference between the external clock signal CLK and the comparison clock signal COMP_CLK. If the comparison clock signal COMP_CLK precedes the external clock signal CLK, the phase detector  260  generates the down pulse signal DN, and if the external clock signal CLK precedes the comparison clock signal COMP_CLK, the phase detector  260  generates the up pulse signal UP.  
         [0056]    The charge pump  270  decreases or increases the voltage level of the voltage control signal Vcon in response to the down pulse signal DN and the up pulse signal UP, respectively. Thus, when the down pulse signal DN is generated, the charge pump  270  decreases the voltage level of the voltage control signal Vcon so that the time period of the VCO becomes longer. Thus, a skew between the external clock signal CLK and the comparison clock signal COMP_CLK is reduced, and finally, the delay time between the external clock signal CLK and the DLL clock DLL_CLK becomes exactly t d2 , i.e., (t cl -t d1 ).  
         [0057]    As described above, by generating the DLL clock through the digital locking operation and the analog locking operation, it is possible to implement the DLL having a fast locking time and a reduced jitter.  
         [0058]    Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.