Abstract:
A method and structure for encoding information on an integrated circuit chip. The method includes selecting a set of chip pads of the integrated circuit chip for encoding the information; encoding the information during a wirebonding process, the wirebonding process comprising forming ball bonds on chip pads of the integrated circuit chip and wedge bonds on leadframe fingers adjacent to one or more edges of the integrated circuit chip, the ball bonds and the wedge bonds connected by respective and integral wires; and wherein the information is encoded by varying one or more wirebonding parameters on each chip pad of the set of chip pads, the wirebonding parameters selected from the group consisting of the location of a ball bond, the diameter of a ball bond, both the location and diameter of a ball bond, the location of a wedge bond and combinations thereof.

Description:
TECHNICAL FIELD 
       [0001]    The present invention relates to the field of integrated circuits chip; more specifically, it relates to on-chip information encoding. 
       BACKGROUND 
       [0002]    Modern integrated circuit chips include electronic chip identification (ECID) circuits that electronically encode a unique integrated circuit (IC) chip identification, or other IC chip related data that can be read out after manufacturing is complete. However, these ECID circuits must be part of the integrated circuit design and require special equipment to encode the information on the IC chip. Many smaller companies lack the means to implement ECID and many IC designs lack the space or cannot support the cost of ECID. Accordingly, there exists a need in the art to mitigate the deficiencies and limitations described hereinabove. 
       BRIEF SUMMARY 
       [0003]    A first aspect of the present invention is a method of encoding information on an integrated circuit chip, comprising: selecting a set of chip pads of the integrated circuit chip for encoding the information; encoding the information during a wirebonding process, the wirebonding process comprising forming ball bonds on chip pads of the integrated circuit chip and wedge bonds on leadframe fingers adjacent to one or more edges of the integrated circuit chip, the ball bonds and the wedge bonds connected by respective and integral wires; and wherein the information is encoded by varying one or more wirebonding parameters on each chip pad of the set of chip pads, the wirebonding parameters selected from the group consisting of the location of a ball bond on a chip pad, the diameter of a ball bond on a chip pad, both the location and diameter of a ball bond on a chip pad, the location of a wedge bond on a leadframe finger and combinations thereof. 
         [0004]    A second aspect of the present invention is a structure encoding information on an integrated circuit chip, comprising: a set of chip pads on the integrated circuit chip and corresponding leadframe fingers adjacent to a perimeter of the integrated circuit chip; ball bonds on the chip pads of the integrated circuit chip and wedge bonds on the leadframe fingers, the ball bonds and the wedge bonds connected by respective and integral wires; and wherein said information is encoded by locations of ball bonds on selected chip pads, diameters of a ball bonds on selected chip pads, both the locations and diameters of ball bonds on selected chip pads, locations of wedge bonds on selected leadframe fingers and combinations thereof. 
         [0005]    These and other aspects of the invention are described below. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings, wherein: 
           [0007]      FIG. 1  a top view of an exemplary integrated circuit chip illustrating interconnection of the chip to a leadframe using wirebonds; 
           [0008]      FIG. 2  is a side view of an exemplary wirebond; 
           [0009]      FIG. 3  illustrates a method for binary encoding of information on an integrated circuit chip using wirebonds according to embodiments of the present invention; 
           [0010]      FIG. 4  illustrates in more detail, the principle of binary data encoding according to embodiments of the present invention; 
           [0011]      FIG. 5  illustrates non-position dependent binary data encoding of information using wirebonds according to embodiments of the present invention; 
           [0012]      FIG. 6  illustrates a method for tertiary encoding of information on an integrated circuit chip using wirebonds according to embodiments of the present invention; 
           [0013]      FIG. 7  illustrates in more detail, the principle of tertiary data encoding according to embodiments of the present invention; 
           [0014]      FIG. 8  illustrates a first method for N-based encoding of information on an integrated circuit chip using wirebonds according to embodiments of the present invention; 
           [0015]      FIG. 9  illustrates a second method for N-based encoding of information on an integrated circuit chip using wirebonds according to embodiments of the present invention; 
           [0016]      FIG. 10  is a top view of a wirebonded integrated circuit module; 
           [0017]      FIG. 11  is a side view of a wirebonded integrated circuit module; 
           [0018]      FIG. 12  simulates an X-ray of an integrated circuit chip that encodes information according to embodiments of the present invention; 
           [0019]      FIG. 13  illustrates the principle of binary data encoding using the wedge bond according to embodiments of the present invention; and 
           [0020]      FIG. 14  is a flow diagram of the method of encoding information using wirebonds according to embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0021]    The embodiments of the present invention encode integrated circuit specific information based on the position of the ball bond of wirebonds, the size of the ball bond of wirebonds or a combination of the position and size of ball bonds of wirebonds on chip pads of integrated circuit chips. Alternatively, the embodiments of the present invention may be practiced using the position of the wedge bond of wirebonds on leadframe fingers of integrated circuit modules. 
         [0022]    It is a critical feature of the embodiments of the present invention that the position of the ball bond of wirebonds, the size of the ball bond of wirebonds or a combination of the position and size of ball bonds of wirebonds that are used to encode information are placed on chip pads selected for encoding information so that other ball bonds on non-selected chip pads do not encode information even if they mimic the encoded structures as to position of the ball bond or size of the ball bond on the non-selected chip pads. 
         [0023]    Examples of information that may be encoded according to the embodiments of the present information include, but are not limited to: a unique integrated circuit chip identity, a location of the integrated circuit chip on a wafer during fabrication (hundreds of chips may be fabrication on the same wafer simultaneously and then singulated after fabrication is complete), a unique wafer identity, a wafer lot number, an integrated circuit design revision, fabrication facility, a date of manufacture of the integrated circuit chip, a technology type, a fabrication process change level, a semiconductor substrate lattice orientation, a chip performance (speed) sort, a degree of functionality, and a customer identity (the entity that the chips are manufactured for). 
         [0024]      FIG. 1  a top view of an exemplary integrated circuit chip illustrating interconnection of the chip to a leadframe using wirebonds. In  FIG. 1 , an integrated circuit chip includes a plurality of chip pads  105  arranged around the perimeter of integrated circuit chip  100 . A plurality of leadframe fingers  115  are arranged opposite chip pads  105 , but do not touch integrated circuit chip  100 . Chip pads  105  are connected to respective leadframe fingers  115  by electrically conductive wirebonds  120 . Chip pads  105  are electrically connected to semiconductor devices (e.g., field effect transistors (FETs)) of integrated circuit chip  100 . Chip pads  105  may carry signals in and out of integrated circuit chip  100  or may supply power to integrated circuit chip  100 . While four rows of chip pads adjacent to respective edges of integrated circuit chip  100  are illustrated, there may be less than four rows. For example, there may be only two rows arranged on opposite sides of integrated circuit chip  100  (see  FIG. 12 ). Further, while a single row of chip pads  105  is located adjacent to each edge of integrated circuit chip  100 , there may be two rows, an outer row of chip pads between an edge of the integrated circuit chip and inner row of chip pads. There may be two or more wirebonds to the same chip pad. There may be two or more wire bond to the same leadframe finger. Some chip pads may not have any wirebonds formed to them. 
         [0025]    In an enhancement to the embodiments of the present invention, dummy chip pads may be included that are used only for encoding information. Dummy chip pads are not connected to circuits within the integrated circuit chip nor to they carry signals, power or ground. Dummy chip pads may within a row or column of normal pads and may include some or all of the chip pads in the row or column. When there are two rows of chip pads, the dummy chip pads may be in the inner or outer row or column of chip pads. Dummy chip pads need not be arranged in rows or columns, but may be replaced anywhere on the integrated circuit chip. 
         [0026]      FIG. 2  is a side view of an exemplary wirebond. In  FIG. 2 , integrated circuit chip  100  is attached to a chip carrier  125 . Wire bond  120  comprises a ball bond  130  formed on chip pad  105  and a wedge bond  135  formed on leadframe finger  115 . Ball bond  130  is connected to wedge bond  135  by a wire  140  integral to both the wedge bond  135  and ball bond  130 . Wirebonds are formed by an automatic programmable wirebonding machine. In one example, the wirebonding process includes (i) feeding a wire through a capillary supplied by a spool of wire, (ii) melting the end of the wire that protrudes from the capillary forming a ball end, (iii) attaching the ball end to the chip pad by compression and ultrasonic bonding, (iv) looping the wire to the leadframe finger, (v) compression and ultrasonic bonding the wire to the leadframe to form a wedge bond, and (vi) breaking the wire at the wedge bond and starting the process over again on a different chip pad. The wire bonding machine has the capability to control the volume (and thus the diameter) of the ball bond precisely. The wire bonding machine has the capability to position the ball bond on the chip pad precisely. The wire bonding machine has the capability to position the wedge bond on the leadframe finger precisely. The wire bonding machine has the capability to control the wire loop as to height, angle, shape and length precisely. In one example, wirebond  120  is gold. 
         [0027]      FIG. 3  illustrates a method for binary encoding of information on an integrated circuit chip using wirebonds according to embodiments of the present invention. In  FIG. 3 , only the ball bonds of the wirebonds are illustrated for clarity. In  FIG. 3 , a non-encoded set  150 A of chip pads  105  are located adjacent to an edge  145 A of integrated circuit chip  100 . Ball bonds  130  are positioned in the center of respective pads  105 . No information is encoded. Also in  FIG. 3 , an encoded set  150 B of chip pads  105 A through  105 H are located adjacent to edge  145 B of integrated circuit chip  100 . Ball bonds  130  are positioned off the center of respective pads  105  with some ball bonds located at the end of chip pads closest to edge  145 B and some ball bonds located at the end of chip pads furthest from edge  145 B. Thus chip pads  105 A,  105 C,  105 D,  105 F and  105 H encode a  1  (alternatively a 0) and chip pads  105 B,  105 E and  105 G encode a 0 (alternatively a 1). Non-encoded set  150 A and encoded set  150  B may be located adjacent to the same integrated circuit chip edge or located adjacent to different integrated circuit chip edges. Since the location and number of chip pads of the encoded set of chip pads is known, additional sets of chip pads may be used to encode dummy or nonsense information. The number of chip pads in the encoded set may be as few as one or as many as all the chip pads on an integrated circuit chip. 
         [0028]      FIG. 4  illustrates in more detail, the principle of binary data encoding according to embodiments of the present invention. In  FIG. 4 , chip pads  105 X and  105 Y are located adjacent to an edge  145  of an integrated circuit chip  100 . Chip pads  105 X and  105 Y each have a first centerline  155  perpendicular to edge  145  and a second centerline  160  perpendicular to first centerline  155  and parallel to edge  145 . First centerline  155  and second centerline cross  160  cross at the center  165  of chip pad  105 . In a first encoding position (on the left of  FIG. 4 ) a ball bond  130  is placed on chip pad  105 X between centerline  160  and edge  145  of chip  100 . In a second encoding position (on the right of  FIG. 4 ) a ball bond  130  is placed on chip pad  105 Y so centerline  160  is between ball bond  130  and edge  145  of chip  100 . Second centerline  160  partitions pads  105 X and  105 Y into two halves, and in one example, ball bonds are placed in the center of one of the halves. The position of ball bond  130  in the direction parallel to second centerline  160  has no encoding significance in this embodiment. It is only the location of ball bond  130  in the direction parallel to first centerline  155  that has encoding significance. In other words, the first encoding position is that adjacent to the edge of the chip pad closest to the edge of the integrated circuit chip and the second encoding position is that adjacent to the edge of the chip pad furthest from the edge of the integrated circuit chip. 
         [0029]      FIG. 5  illustrates non-position dependent binary data encoding of information using wirebonds according to embodiments of the present invention. In  FIG. 5 , only the ball bonds of the wirebonds are illustrated for clarity. In  FIG. 5 , an encoded set  150 C of chip pads  105 A through  105 H are located adjacent to edge  145 C of integrated circuit chip  100 . Ball bonds  130 A are on positioned chip pads  105 A,  105 C,  105 D,  105 F,  105 G and  105 H. Ball bonds  130 B are positioned on chip pads  105 B and  105 E. Ball bonds  130 A have a diameter A and ball bonds  130 B have a diameter B with B being greater than A. Thus a 1 (alternatively a 0) is encoded on chip pads  105 A,  105 C,  105 D,  105 F,  105 G and  105 H and a 0 (alternatively a 1) is encoded on chip pads  105 B and  105 E. In this embodiment, the position of ball bonds carry no encoding significance and may be positioned any where on the chip pads. A non-encoding set of ball bonds would be all small (e.g.,  130 A) or all large (e.g.,  130 B). Since the location and number of chip pads of the encoding set of chip pads is known, additional sets of chip pads may be used to encode dummy or nonsense information. The number of chip pads in the encoded set may be as few as one or as many as all the chip pads on an integrated circuit chip. 
         [0030]    If the embodiment of  FIG. 5  as to the position of the ball bonds on the chip pads is combined with the embodiment of  FIG. 3  as to the size of the ball bonds on the chip pads a quaternary encoding scheme is created where both the size and position of the ball bond on the chip pad encode information. 
         [0031]      FIG. 6  illustrates a method for tertiary encoding of information on an integrated circuit chip using wirebonds according to embodiments of the present invention. In  FIG. 6 , only the ball bonds of the wirebonds are illustrated for clarity. In  FIG. 6 , an encoded set  150 D of chip pads  105 A through  105 H are located adjacent to edge  145 D of integrated circuit chip  100 . Ball bonds  130  are positioned both on the center and off the center of respective pads  105 A through  105 H with ball some ball bonds located at the end of chip pads closest to edge  145 D and some ball bonds located at the end of chip pads furthest from edge  145 D and some ball bonds located on the center of chip pads. Thus a 1 (alternatively a 0) is encoded on chip pads  105 A,  105 C,  105 F and  105 H, a  0  (alternatively a 1) is encoded on chip pads  105 B and  105 E, and an “X” is encoded on chip pads  105 D and  105 G. Since the location and number of chip pads of the encoded set of chip pads is known, additional sets of chip pads may be used to encode dummy or nonsense information. The number of chip pads in the encoded set may be as few as one or as many as all the chip pads on an integrated circuit chip. 
         [0032]      FIG. 7  illustrates in more detail, the principle of tertiary data encoding according to embodiments of the present invention. In  FIG. 7 , chip pads  105 X,  105 Y and  105 Z are located adjacent to an edge  145  of an integrated circuit chip  100 . Chip pads  105 X,  105 Y and  105 Z each have a first centerline  155  perpendicular to edge  145  and a second centerline  160  perpendicular to first centerline  155  and parallel to edge  145 . First centerline  155  and second centerline cross  160  cross at the center  165  of chip pad  105 . In a first encoding position (on the left of  FIG. 7 ) a ball bond  130  is placed on chip pad  105 X between centerline  160  and edge  145  of chip  100 . In a second encoding position (in the center of  FIG. 7 ) a ball bond  130  is placed on chip pad  105 Y so centerline  160  is between ball bond  130  and edge  145  of chip  100 . In a third encoding position (on the right of  FIG. 7 ) a ball bond  130  is placed on the second centerline  160  of chip pad  105 Z. Second centerline  160  partitions pads  105 X and  105 Y into two halves, and in one example, ball bonds are placed in the center of one of the halves or on the centerline. The position of ball bond  130  in the direction parallel to second centerline  160  has no encoding significance in this embodiment. It is only the location of ball bond  130  in the direction parallel to first centerline  155  that has encoding significance. In other words, the first encoding position is that adjacent to the edge of chip pad closest to the edge of the integrated circuit chip, the second encoding position is that adjacent to the edge of the chip pad furthest from the edge of the integrated circuit chip and the third encoding position is about in the center of the chip pad. 
         [0033]    Alternatively, in a first encoding position (on the left of  FIG. 7 ) a ball bond  130  is placed on chip pad  105 X between centerline  160  and edge  145  of chip  100 . In a second encoding position (in the center of  FIG. 7 ) a ball bond  130  is placed on chip pad  105 Y so centerline  160  is between ball bond  130  and edge  145  of chip  100 . The third position on the right of  FIG. 7  is a non-encoding position reserved for the normal position of ball bond. In this scheme  FIGS. 6 and 7  become binary encoding schemes, but allow easy differential of encoded chip pads from non-encoded chip pads. 
         [0034]    If the embodiment of  FIG. 6  as to the position of the ball bonds on the chip pads is combined with the embodiment of  FIG. 5  as to the size of the ball bonds on the chip pads an octanary encoding scheme is created where both the size and position of the ball bond on the chip pad encode information. 
         [0035]      FIG. 8  illustrates a first method for N-based encoding of information on an integrated circuit chip using wirebonds according to embodiments of the present invention. The encoding scheme of  FIG. 8  is similar to the encoding scheme of  FIG. 7  except the allowed positions A through G for the center of the ball bond and they overlap so a septenary (base N=9) encoding scheme is encoded. Ball bond  130  is shown in by the heavy circle in position D, while the lighter circles show the other allowable eight positions for the ball bond. In  FIG. 7 , by way of example, ball bonds have a diameter D and the allowable spacing between locations is S1, where S1=D/2. In other examples S1&gt;D/2 or S1&lt;D/2. While  FIG. 8  illustrates seven allowable positions for a ball bond, there may be three or more allowable positions for a ball bond. 
         [0036]    Alternatively, only positions A, B, C, E, and G are encoding positions and encoding position D is a non-encoding position reserved for the normal position of ball bond. In this scheme  FIG. 8  becomes a senary (base N=6) encoding schemes, but allow easy differential of encoded chip pads from non-encoded chip pads. 
         [0037]      FIG. 9  illustrates a second method for N-based encoding of information on an integrated circuit chip using wirebonds according to embodiments of the present invention. In  FIG. 9  a chip pad  105 S is divided into four equal area quadrants  170 A,  170 B,  170 C and  170 D by first centerline  155  and second centerline  160 . There are nine allowable positions to place the ball bond to encode information on chip pad  105 S, eight are shown by the light circles and the ninth is shown as a dark circle representing a ball bond  130  over the intersection of first centerline  155  and second centerline  160 . The other eight positions are completely within quadrant  170 A, completely within quadrant  170 B, completely within quadrant  170 C, completely within quadrant  170 D, on first centerline  155  and overlapping only and both quadrants  170 A and  170 B, on first centerline  155  and overlapping only and both quadrants  170 C and  170 D, on second centerline  160  and overlapping only and both quadrants  170 A and  170 C, and on second centerline  160  and overlapping only and both quadrants  170 B and  170 D. While  FIG. 9  illustrates nine allowable positions for a ball bond, there may be four or more allowable positions for a ball bond. While  FIG. 9  shows a 3 by 3 matrix of ball bond positions, the ball bond positions may be in a form of an R row by C column matrix with R and C each being independently equal to 2 or more. When R=1 and C=2 this embodiment reduces to that illustrated in  FIGS. 3 and 4 . When R=1, and C=3 this embodiment reduces to that illustrated in  FIGS. 6 and 7 . 
         [0038]    Alternatively, the position over the intersection of first centerline  155  and second centerline  160  is a non-encoding position reserved for the normal position of the ball bond and the eight other positions are encoding positions. In this scheme  FIG. 9  becomes an octanary (base N=8) encoding schemes, but allow easy differential of encoded chip pads from non-encoded chip pads. 
         [0039]    Alternatively, encoding positions may overlap as in  FIG. 8  and shown in  FIG. 9  by the dashed circles. Thus, the encoding base number can be a very large number and each position could represent a entire “word” rather than a bit of information. 
         [0040]      FIG. 10  is a top view and  FIG. 11  is a side view of a wirebonded integrated circuit module  175 . In  FIGS. 10 and 11 , an integrated chip (not shown in  FIGS. 10 and 11 ) is encapsulated in a plastic body  180  with leadframe fingers  120  extending outside of plastic body  180 . As can be seen in  FIG. 11 , leadframe fingers  120  are bent into “feet” for solder attach to a printed circuit board or other higher level of packaging. While leadframe fingers  120  are shown only on two sides of plastic body  180 , in other form factors, leadframe fingers extend from all four sides of the body. 
         [0041]    In one example, in order to “read” the information encoded on the chip pads, the integrated circuit may be de-packaged, for example by placing the module in hot sulfuric acid to remove the plastic body and leadframe and leave the wire bond attached to the integrated circuit chip. However, modern X-ray equipment, and particularly those equipped with pattern recognition software, can “see through” the module as illustrated in  FIG. 12 . 
         [0042]      FIG. 12  simulates an X-ray of an integrated circuit chip that encodes information according to embodiments of the present invention. In  FIG. 12 , the heaviest lines are the wirebonds  130 , the medium lines are the leadframe fingers/feet  120  and the lightest lines are the chip  100 A, chip pads  105 U and  105 V and plastic body  180 . Chip pads  105 U have been encoded using a binary scheme, while chip pads  105 V have not been encoded The binary code on chip pads  105 U can be easily read. With pattern recognition software coupled to a cross-reference table of ball bond position/size and alphanumeric value, the information can automatically be displayed or printed out. 
         [0043]      FIG. 13  illustrates the principle of binary data encoding using the wedge bond according to embodiments of the present invention. In  FIG. 13 , lead frame fingers  120 X and  120 Y are located adjacent to an edge  145  of an integrated circuit chip  100 . Lead frame fingers  120 X and  120 Y each have a first centerline  185  perpendicular to edge  145  and a second centerline  190  perpendicular to first centerline  185  and parallel to edge  145 . First centerline  185  and second centerline cross  190  cross at the center  195  at a predetermined point on leadframe fingers  120 X and  120 Y. In a first encoding position (on the left of  FIG. 13 ) a wedge bond  135  is placed on leadframe finger  120 X between centerline  190  and edge  145  of chip  100 . In a second encoding position (on the right of  FIG. 13  a wedge bond  135  is placed on leadframe finger  120 Y so centerline  190  is between wedge bond  135  and edge  145  of chip  100 . Second centerline  190  partitions leadframe fingers  120 X and  120 Y into two regions, and in one example, wedge bonds are placed on first centerline  185  in one of the regions. The position of wedge bond  135  in the direction parallel to second centerline  190  has no encoding significance in this embodiment. It is only the location of wedge bond  135  in the direction parallel to first centerline  185  that has encoding significance. In other words, the first encoding position is that adjacent to the edge of the leadframe finger closest to the edge of the integrated circuit chip and the second encoding position is that adjacent to the edge of the leadframe finger furthest from the edge of the integrated circuit chip. 
         [0044]      FIG. 14  is a flow diagram of the method of encoding information using wirebonds according to embodiments of the present invention. In step  200 , the information to be encoded using wirebonds is determined. In step  205 , the method for encoding information is selected from the various embodiments of the present invention. In step  210 , the chip pads (or leadframe fingers) on which the information is to be encoded are selected. In step  215 , the selected chip pads are encoded during wirebonding. In step  220 , the encoded information is read. Between steps  215  and  220 , the encoded integrated circuit chip may be packaged (e.g., in a plastic form package) and optionally mounted on a higher level of packaging (e.g., a printed circuit board). 
         [0045]    Thus, the embodiments of the present invention provide methods and structures for encoding information on individual integrated circuits. 
         [0046]    The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.