Abstract:
Disclosed is a method of forming array substrates having a peripheral wiring area and a display area. The method is processed by only three lithography processes with two multi-tone photomasks and one general photomask. In the peripheral wiring area, the top conductive line directly contacts the bottom conductive line without any other conductive layer. The conventional lift-off process is eliminated, thereby preventing a material (not dissolved by a stripper) from suspending in the stripper or remaining on the array substrate surface.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a Continuation of application Ser. No. 13/325,585, filed on Dec. 14, 2011, which claims priority of Taiwan Patent Application No. 099144150, filed on Dec. 16, 2010, the entirety of which is incorporated by reference herein. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a process of manufacturing a liquid crystal display, and in particular relates to a method of manufacturing an array substrate thereof. 
         [0004]    2. Description of the Related Art 
         [0005]    General processes of forming an array substrate in a liquid crystal display need four or five lithography steps; thus, four or five photomasks are used. A lithography step with only three photomasks utilizes a lift-off process, which firstly forms a photoresist layer as a sacrificing layer of a coating film. Thereafter, the coating film is deposited on regions covered and not covered by the photoresist layer, and then the substrate is dipped in a stripper. The coating film on the photoresist layer can be stripped with the removal photoresist layer, thereby saving use of a photomask. However, using the substrate containing the photoresist layers in general mass production equipment of thin film transistors for depositing the coating is not allowed. The stripped coating film easily adheres to the substrate to form defects, or suspends in the stripper to obstruct stripper pipes. 
         [0006]    Accordingly, a novel method which may replace the conventional lift-off process without increasing photomasks is called for. 
       BRIEF SUMMARY OF THE INVENTION 
       [0007]    One embodiment of the disclosure provides a method of forming an array substrate, comprising: forming a first conductive layer on a substrate; forming a first photoresist layer on the first conductive layer; patterning the first photoresist layer by a lithography process with a first multi-tone photomask to form a first non-photoresist region, a first thin photoresist pattern, and a first thick photoresist pattern; etching the first conductive layer of the first non-photoresist region to form a gate electrode, a gate line connecting to the gate electrode, a common line, and a bottom conductive line, wherein the first thin photoresist pattern is on the gate electrode, the gate line, the common line, and a wiring region of the bottom conductive line, and wherein the first thick photoresist pattern is on a contact region of the bottom conductive line; ashing the first thin photoresist pattern to expose the gate electrode, the gate line, the common line, and the wiring region of the bottom electrode; selectively depositing an insulation layer on the substrate, the gate electrode, the gate line, the common line, and the wiring region of the bottom conductive line; selectively depositing a semiconductor layer on the insulation layer; removing the first thick photoresist pattern; and forming a second conductive layer on the semiconductor layer and the contact region of the bottom conductive line. 
         [0008]    One embodiment of the disclosure provides a method of forming an array substrate, comprising: forming a gate electrode, a gate line connecting to the gate electrode, and a common line on a substrate; depositing an insulation layer on the substrate, the gate electrode, the gate line, and the common line; depositing a semiconductor layer on the insulation layer; depositing a conductive layer on the semiconductor layer; forming a photoresist layer on the conductive layer; patterning the photoresist layer by a lithography process with a multi-tone photomask to form a non-photoresist region, a thin photoresist pattern, a sub-thick photoresist pattern, and a thick photoresist pattern; removing the conductive layer and the semiconductor layer of the non-photoresist region to form a data line, a conductive pattern connecting to the data line, a channel layer, and a top electrode, wherein the data line and the gate line vertically cross with each other for defining a pixel region, wherein the channel layer is disposed between the gate electrode and the conductive pattern, wherein the top electrode covers a part of the common line for defining a storage capacitor, and wherein the thin photoresist pattern corresponds to a center part of the gate electrode, and the sub-thick photoresist pattern corresponds to two sides of the conductive pattern, the data line, and the top electrode; ashing the thin photoresist pattern to expose the conductive pattern on the center part of the gate electrode; removing the exposed part of the conductive pattern to expose the channel layer on the center part of the gate electrode for forming a source electrode and a drain electrode, wherein the thick photoresist pattern corresponds to a part of the drain electrode and a part of the top electrode; ashing the sub-thick photoresist pattern to expose the source electrode, the drain electrode, the data line, and the top electrode; selectively depositing a passivation layer on all regions other than the thick photoresist pattern; ashing the thick photoresist pattern to expose the part of the drain electrode and the part of the top electrode; and forming a pixel electrode pattern on the passivation layer of the pixel electrode, wherein the pixel electrode pattern connects to the exposed part of the drain electrode and the exposed part of the top electrode. 
         [0009]    One embodiment of the disclosure provides an array substrate, comprising: a bottom conductive line on a substrate; an insulation layer on the bottom conductive line and the substrate, wherein the insulation layer includes an opening to expose a part of the bottom electrode; a top conductive line on the insulation layer, wherein the top conductive line connects to the bottom conductive line through the opening; and a passivation layer on the top conductive line and the substrate, wherein the top conductive line and the insulation layer have a semiconductor layer interposed therebetween. 
         [0010]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    The disclosure can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0012]      FIGS. 1A-1D ,  3 A- 3 H,  5 A, and  5 C- 5 G are serial cross sections of a process for manufacturing a display region of an array substrate in one embodiment of the disclosure; and 
           [0013]      FIGS. 1E ,  3 I, and  5 B are serial top views of a process for manufacturing a display region of an array substrate in one embodiment of the disclosure; 
           [0014]      FIGS. 2A-2E  and  4 A- 4 E are serial cross sections of a process for manufacturing a peripheral wiring region of an array substrate in one embodiment of the disclosure; and 
           [0015]      FIGS. 2F and 4F  are serial top views of a process for manufacturing a peripheral wiring region of an array substrate in one embodiment of the disclosure. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0016]    The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
         [0017]    First, a conductive layer and a photoresist layer are sequentially formed on a substrate  10 , and the photoresist layer is patterned by a lithography process with a multi-tone photomask to form a non-photoresist region  11 A, a thin photoresist pattern  11 B, and a thick photoresist pattern  11 C. Subsequently, the conductive layer of the non-photoresist region is removed to expose the substrate  10 . As shown in  FIGS. 1A and 2A , the patterned conductive layer in a display region  100  includes a gate electrode  12 A, a bottom electrode  12 C of a storage capacitor. The patterned conductive layer in a peripheral wiring region  150  includes a bottom conductive line  12 E. The thin photoresist pattern  11 B corresponds to the patterned conductive layer such as the gate electrode  12 A, the bottom electrode  12 C, and a wiring region  121 A of the bottom conductive line  12 E. The thick photoresist pattern  11 C corresponds to a contact region  121 B of the bottom conductive line  12 E. For illustration of the wiring region  121 A and the contact region  121 B of the bottom conductive line  12 E, reference may be made to  FIG. 2F . 
         [0018]    The substrate  10  includes a rigid inorganic material, such as a transparent material (e.g. glass, quartz, or the likes) or an opaque material (such as wafer, ceramic, metal, alloy, or the likes). Alternatively, the substrate  10  includes a flexible organic material such as plastic, rubber, polyester, polycarbonate, or the likes. In addition, the substrate  10  can be a composite of the described organic and inorganic materials, or a stack structure of the organic materials and/or the inorganic materials. In some embodiments, the substrate  10  of the transparent material and thin film transistor products containing the same can be applied in transmissive liquid crystal displays, reflective liquid crystal displays, transflective liquid crystal displays, or self illumination displays. In other embodiments, the substrate  10  of the opaque material or poorly transparent material and thin film transistor products containing the same can be only applied in reflective liquid crystal displays or self illumination displays. 
         [0019]    The conductive layer includes metal, alloy, or multi-layered structures thereof. In some embodiment, the conductive layer can be single-layered structures or multi-layered structures of molybdenum, aluminum, copper, titanium, gold, silver, or alloys thereof. The conductive layer can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering, or the likes. The lithography process includes photoresist coating (e.g., spin-on coating), soft baking, photomask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), other suitable processes, and/or combinations thereof. The photoresist layer can be formed by spin-on coating, slit coating, roll coating, inkjet coating, spray coating, or the likes. The conductive layer can be removed by etching, e.g. dry etching, wet etching, or combinations thereof. 
         [0020]    The multi-tone photomask can be a stack layer photomask or a grey level photomask. It should be understood that the photomask has a transparent region corresponding to the non-photoresist region  11 A, a semi-transparent region corresponding to the thin photoresist pattern  11 B, and a light-shielding region corresponding to the thick photoresist pattern  11 C, respectively, when the patterned photoresist layer is composed of a positive photoresist. Similarly, the photomask has a light-shielding region corresponding to the non-photoresist region  11 A, a semi-transparent region corresponding to the thin photoresist pattern  11 B, and a transparent region corresponding to the thick photoresist pattern  11 C, respectively, when the patterned photoresist layer is composed of a negative photoresist. In short, the photomasks for the positive and negative photoresist layers have opposite patterns, respectively. 
         [0021]    The thin photoresist pattern  11 B is then ashed, thereby exposing the gate electrode  12 A and the bottom electrode  12 C as shown in  FIG. 1B , and exposing the wiring region  121 A of the bottom electrode  12 E as shown in  FIG. 2B , respectively. This ashing step can be performed by oxygen plasma at a temperature of room temperature to 200° C. An overly high ashing temperature may char the photoresist layer and make it difficult to remove in later processes. An overly low ashing temperature may slow the ashing rate, and therefore increase its process period. The ashing step can completely ash the thin photoresist pattern  11 B and partially ash the thick photoresist pattern  11 C. Because the ashing step is an isotropic removal step, the thick photoresist pattern  11 C preferably has a larger profile (or area) than its corresponding region, e.g. the contact region  121 B of the bottom conductive line  12 E. For example, when the thin photoresist pattern  11 B has a thickness of 10 μm, the thick photoresist pattern  11 C has a first profile edge, and the contact region  121 B of the bottom conductive line  12 E has a second profile edge, and the first and second profile edges should have a distance of 10 μm. As such, the ashing step will not shrink the contact region  121 B of the bottom conductive line  12 E. 
         [0022]    The insulation layer  14  is then selectively deposited on the substrate  10 , the gate electrode  12 A, the gate line  12 B, and the common line  12 D (referred to  FIG. 1E ), the bottom electrode  12 C, and the wiring region  121 A of the bottom conductive line  12 E (referred to  FIG. 2F ), as shown in  FIGS. 1C and 2C . In other words, the insulation layer  14  is deposited on all regions other than the thick photoresist pattern  11 C. The selective deposition process can be performed by an atomic layer deposition (ALD) at a temperature of room temperature to 200° C. An overly high depositing temperature may char the photoresist layer and make it difficult to be removed in later processes. An overly low depositing temperature may form particular defects or a non-dense coating film during the deposition process. The ALD has several properties, which is listed as follows. First, ALD may form a dense coating film with a complete step coverage, such that the gate insulation film may have a high quality. Second, the ALD may selectively deposit the coating film on suitable regions other than on the organic surface under appropriate conditions. Contact holes can be directly formed after stripping the photoresist layer, and the stripping process will not cause the coating film to peel. As such, the problems such as polluting the array substrate or obstructing the stripper pipes due to the stripping of the coating film can be avoided. The insulation layer  14  includes aluminum oxide, lanthanum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, other materials suitable for the selective deposition, or multi-layered structures thereof. 
         [0023]    A semiconductor layer  16  is then selectively deposited on the insulation layer  14 , as shown in  FIGS. 1D and 2D . In other words, the semiconductor layer  16  is not deposited on the thick photoresist pattern  11 C. The semiconductor layer  16  can be zinc oxide, indium oxide, indium gallium zinc oxide, tin oxide, or other materials suitable for the selective deposition. A process temperature of the selective deposition can be controlled as previously described and further description is omitted here. 
         [0024]    The remaining thick photoresist pattern  11 C is then removed to form a contact hole  18  exposing the contact region  121 B of the bottom conductive line  12 E, as shown in  FIG. 2E . Because the display region  100  is free of the thick photoresist pattern  11 C, this removing step will not influence the structure as shown in  FIG. 1D . The removal can be performed by the described ashing step or a conventional wet stripping process. It should be understood that a cross-sectional view of a cross-section line A-A′ in  FIG. 1E  is shown in  FIG. 1D , and a cross-sectional view of a cross-section line B-B′ in  FIG. 2F  is shown in  FIG. 2E . 
         [0025]    As shown in  FIGS. 1E and 2F , the patterned conductive layer only serves as the gate electrode  12 A, the gate line  12 B connecting to the gate electrode  12 A, and the common line  12 D (a part of the common line served as the bottom electrode  12 C of a predetermined storage capacitor) in the display region  100  and the bottom conductive line  12 E of the peripheral wiring region  150 . However, the patterned conductive layer may serve as a contact pad or other elements if necessary. As shown in  FIG. 1E , the gate line  12 B and the common line  12 D are alternately arranged in parallel. 
         [0026]    As shown in  FIG. 3A , a conductive layer  32  is then formed on the semiconductor layer  16  and on a bottom and sidewalls of the contact hole  18 . The conductive layer  32  includes metal, alloy, or multi-layered structures thereof, such as a stack of molybdenum/aluminum/molybdenum, molybdenum/copper, molybdenum/copper/molybdenum, or titanium/copper. The conductive layer  32  can be formed by evaporation, sputtering, PVD, or CVD processes. 
         [0027]    A photoresist layer is then formed on the conductive layer  32  and patterned by a lithography process with a multi-tone photomask to form a non-photoresist region  33 A, a thin photoresist pattern  33 B, a sub-thick photoresist pattern  33 C, and a thick photoresist pattern  33 D, as shown in  FIGS. 3B and 4B . The composition and formation of the photoresist layer is similar to that previously described, and thus, further description is omitted here. It should be understood that the photomask has different regions of different transparency as below when the photoresist layer is composed of a positive photoresist. The photomask has a transparent region corresponding to the non-photoresist region  33 A. The photomask has semi-transparent regions corresponding to the thin photoresist pattern  33 B and the sub-thick photoresist pattern  33 C, wherein the semi-transparent region corresponds to the thin photoresist pattern  33 B has a higher transparency than the semi-transparent region corresponds to the sub-thick photoresist pattern  33 C. The photomask has a light-shielding region corresponding to the thick photoresist pattern  33 D. Alternatively, the photomask has different regions of different transparency as below when the photoresist layer is composed of a negative photoresist. The photomask has a light-shielding region corresponding to the non-photoresist region  33 A. The photomask has semi-transparent regions corresponding to the thin photoresist pattern  33 B and the sub-thick photoresist pattern  33 C, wherein the semi-transparent region corresponds to the sub-thick photoresist pattern  33 C has a higher transparency than the semi-transparent region corresponds to the thin photoresist pattern  33 B. The photomask has a transparent region corresponding to the non-photoresist pattern  33 D. In short, the photomasks for the positive and negative photoresist layers have opposite patterns, respectively. 
         [0028]    The conductive layer  32  and the semiconductor layer  16  of the non-photoresist region  33 A are then removed, as shown in  FIGS. 3C and 4C . The conductive layer  32  and the semiconductor layer  16  can be removed by a dry etching, wet etching process, or combinations thereof. The etching step may simultaneously define a data line  32 A (referred to  FIG. 3I ), a conductive pattern  32 B connecting to the data line  32 A, a channel layer  16 A, and a top electrode  32 C in the display region  100 , and a top conductive line  32 D (referred to  FIG. 4F ) in the peripheral wiring region  150 . In the display region  100 , the data lines  32 A vertically cross the gate lines  12 B to define a pixel region  300  (referred to  FIG. 3I ). The channel layer  16 A is interposed between the conductive pattern  32 B and the gate electrode  12 A. The top electrode  32 C covers a part of the common line  12 D (such as the bottom electrode  12 C) to define a storage capacitor  330 . In the peripheral wiring region  150 , the top conductive line  32 D connects to the bottom conductive line  12 E. In a contact region of a conventional peripheral wiring region, a top conductive line connects to a bottom conductive line through other conductive material such as ITO. However, the top conductive line  32 D directly connects the bottom conductive line  12 E through the contact hole  18  of the insulation layer  14 , and there is no transparent material such as ITO interposed between the top conductive line  32 D and the bottom conductive line  12 E. 
         [0029]    Still referring to  FIGS. 3C and 4C , the thin photoresist pattern  33 B corresponds to a center part of the gate electrode  12 A. The sub-thick photoresist pattern  33 C corresponds to two sides of the conductive pattern  32 B, the data line  32 A, and the top electrode  32 C in the display region  100 , and the top conductive line  32 D in the peripheral wiring region  150 . The thick photoresist pattern  33 D corresponds to predetermined contact holes of a drain electrode and the top electrode  32 C. 
         [0030]    The thin photoresist pattern  33 B is then ashed to expose the conductive pattern  32 B on the center part of the gate electrode  12 A, as shown in  FIG. 3D . The conditions of the ashing step are similar to that previously described, and thus, further description is omitted here. The ashing step may totally remove the thin photoresist pattern  33 B and partially remove the sub-thick photoresist pattern  33 C and the thick photoresist pattern  33 D. Because the ashing step is an isotropic removal step, the sub-thick photoresist pattern  33 C preferably has a larger profile (or area) than its corresponding region, e.g. the two side of the conductive pattern  32 B, the data line  32 A, the top electrode  32 C, and the top conductive line  32 D. Similarly, the thick photoresist pattern  33 C preferably has a larger profile (or area) than its corresponding region, e.g. predetermined contact holes of the drain electrode and the top electrode  32 C. 
         [0031]    The conductive pattern  32 B on the center part of the gate electrode  12 A is then removed to form a source electrode  32 E and a drain electrode  32 F, such that the underlying channel layer  16 A is exposed as shown in  FIG. 3E . The part of the conductive pattern  32 B can be removed by a dry etching, wet etching process, or combinations thereof. 
         [0032]    The sub-thick photoresist pattern  33 C is then ashed to expose the bottom conductive line  12 E, the data line  32 A, the top electrode  32 C, the top conductive line  32 D, the source electrode  32 E, and the drain electrode  32 F, as shown in  FIGS. 3F and 4D . The conditions of the ashing step are similar to that previously described, and thus, further description is omitted here. The ashing step may totally remove the sub-thick photoresist pattern  33 C and partially remove the thick photoresist pattern  33 D. Because the ashing step is an isotropic removal step, the thick photoresist pattern  33 D preferably has a larger profile (or area) than its corresponding region, e.g. predetermined contact holes of the drain electrode and the top electrode  32 C. 
         [0033]    A passivation layer  34  is then selectively deposited on all regions other than the thick photoresist pattern  33 D, as shown in  FIGS. 3G and 4E . The composition of the passivation layer  34  is similar to the insulation layer  14 , thus, further description is omitted here. In one embodiment, the selective deposition is ALD. A process temperature of the selective deposition can be controlled as previously described, thus, further description is omitted here. 
         [0034]    The remaining thick photoresist pattern  33 D is then removed to form a drain electrode contact hole  36 A and a top electrode contact hole  36 B to expose a part of the drain electrode  32 F and a part of the top electrode  32 C, respectively, as shown in  FIG. 3H . The removal process can be performed by the described ashing step or a conventional stripping. Because the peripheral wiring region  150  is free of the thick photoresist pattern  33 D, this step will not influence the structure in  FIG. 4E . It should be understood that a cross-sectional view of a cross-section line A-A′ in  FIG. 3I  is shown in  FIG. 3H , and a cross-sectional view of a cross-section line B-B′ in  FIG. 4F  is shown in  FIG. 4E . 
         [0035]    Finally, a pixel electrode pattern  52  is formed in the pixel region  300 . The pixel electrode pattern  52  connects to the drain electrode  32 F of the thin film transistor through the drain electrode contact hole  36 A, and connects to the top electrode  32 C of the storage capacitor  330  through the top electrode contact hole  36 B, respectively. In one embodiment, the array substrate is applied in a transmission liquid crystal display, and the pixel electrode pattern  52  includes a transparent material such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), cadmium tin oxide (CTO), tin oxide (SnO 2 ), zinc oxide (ZnO), silver nanowire, or carbonanotube (CNT). In another embodiment, the array substrate is applied in a reflection liquid crystal display, and the pixel electrode pattern  52  includes a reflective material such as aluminum, gold, tin, silver, copper, iron, lead, chromium, tungsten, molybdenum, neodymium, nitrides thereof, oxynitrides thereof, alloys thereof, or combinations thereof. In addition, the pixel electrode pattern  52  of a reflective type may have an uneven surface to increase the reflection and scattering effect of the light. It should be understood that a cross-sectional view of a cross-section line A-A′ in  FIG. 5B  is shown in  FIG. 5A . 
         [0036]    The pixel electrode  52  can be formed by two major ways. In the first way, a photoresist pattern  53 A is formed on regions without the pixel electrode pattern  52  by a lithography process utilizing a photomask, as shown in  FIG. 5C . The pixel electrode pattern  52  is then selectively deposited in the pixel region  300 , as shown in  FIG. 5D . At last, the photoresist pattern  53 A is removed to form the structure as shown in  FIG. 5A . In the second way, a pixel electrode layer is conformally formed in all regions, as shown in  FIG. 5E . A photoresist pattern  53 B is then formed on the pixel electrode layer  51  in the pixel region  300  by a lithography process with a photomask, as shown in  FIG. 5F . The pixel electrode layer  51  not covered by the photoresist pattern  53 B is then etched, as shown in  FIG. 5G . At last, the photoresist pattern  53 B is removed to form the structure as shown in  FIG. 5A . Because the peripheral wiring region  150  does not need the pixel electrode layer  51 , in the first way, the photoresist pattern  53 A on the peripheral wiring region  150  should be further formed to prevent the pixel electrode pattern  52  from being formed thereon. Thereafter, the photoresist pattern  53 A on the peripheral wring region  150  can be removed. On the other hand, in the second way, the photoresist pattern  53 B on the peripheral wiring region will not be formed, such that the pixel electrode layer  51  on the peripheral wiring region  150  will be etched. 
         [0037]    Accordingly, one embodiment provides a method to form the elements in the display region  100  and the peripheral wiring region  150  by two multi-tone photomasks and one general photomask. In another embodiment, the structure as shown in  FIG. 1E  can be formed by a lithography process with a general photomask, the structure as shown in  FIG. 3I  can be then formed by a lithography process with a multi-tone photomask, and the structure as shown in  FIG. 5B  can be then formed by a lithography process with a general photomask. In short, the display region  100  can be defined by one multi-tone photomask and two general photomasks without considering the peripheral wiring region  150 . In a further embodiment, the structure as shown in  FIG. 2F  can be formed by a lithography process with a multi-tone photomask, and the structure as shown in  FIG. 4F  can be then formed by a lithography process with a general photomask. In short, the peripheral wiring region  150  can be defined by one multi-tone photomask and one general photomask without considering the display region  100 . The array substrate containing the peripheral wiring region  150  can be applied in several optoelectronic devices such as a solar cell transferring a light energy to an electrical energy, or a display transferring an electrical energy to a light energy. In one embodiment, the display can be a large sized flat display (e.g. television), a medium sized display (e.g. e-book), or a small sized display (e.g. cell phone screen). 
         [0038]    Compared to the related art, the multi-tone photomasks of the disclosure may save lithography processes and solve alignment problems. Because the disclosure is free of the lift-off process, there is no material formed on the photoresist layer. Therefore, the step of removing the photoresist layer may prevent the lift-off problems, e.g. material left on the array substrate which reduces production yield, or obstructing the stripper pipes. The selective deposition collocated with three photomasks used to form the insulation layer  14 , the semiconductor layer  16 , and the passivation layer  34  in the display region  100  and/or the peripheral wiring region  150  may increase the possibility of the mass production. 
         [0039]    While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.