Abstract:
An apparatus for amplifying an input signal is disclosed. The apparatus includes a first amplifying circuit and a first resonating circuit. The first amplifying circuit includes a first transistor having a first gate for receiving the input signal. The first amplifying circuit amplifies the input signal to generate a first output signal. The first resonating circuit is coupled to the first amplifying circuit, wherein a first resonating frequency of the first resonating circuit is not equal to the operating frequency.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to an amplifying circuit, and more particularly to a power amplifying circuit for increasing linearity. 
   2. Description of the Prior Art 
   Power amplifiers have been widely used in different kinds of wired or wireless system applications. Normally, there are two means of determining the effectiveness of a power amplifier, the first one being the power gain and the second being the linearity of the power amplifier. The linearity can determine the distortion between the input signal and the output signal of the power amplifier. Furthermore, in advanced CMOS manufacturing techniques, utilizing the ideal system-on-chip (SOC) to implement the whole wireless transmitter chip is more popular. Please refer to C. Wang, M. Vaidyanathan, and L. E. Larson, “A Capacitance Compensation Technique for Improved Linearity in CMOS Class-AB Power amplifiers,”  IEEE - J. Solid - State - Circuits , vol. 39, no. 11, pp. 1927-1937, November 2004 for more information. According to the prior art, the nonlinearity of the CMOS power amplifier is mainly caused by two reasons: the first one is the transconductance Gm of the transistor, which determines the linearity of the transistor; and the second reason is the nonlinear capacitor Cgate at the gate of the transistor, which determines the linearity of the output of the previous stage circuit. The above-mentioned prior art has disclosed a capacitive compensation method to improve the nonlinear capacitor Cgate at the gate of the transistor. However, this conventional method can only be utilized in a CMOS power amplifier having a class AB configuration. Furthermore, the prior art requires an increased chip area and the power gain is not ideal. For the OFDM system, which requires a very high linearity (e.g. the linearity requirement of the specification of 802.11g is as high as 25 dBm at P1 dB), only a power amplifier implemented by a class A configuration can be adopted. However, a power amplifier with a class A configuration will have a bad linearity caused by the above-mentioned problem. 
   SUMMARY OF THE INVENTION 
   Therefore, one of the objectives of the present invention is to provide an amplifying circuit to improve the linearity of a power amplifier. 
   According to an embodiment of the present invention, an amplifying apparatus is provided. The amplifying apparatus comprises a first amplifying circuit comprising a first transistor having a first gate for receiving the input signal, wherein the first amplifying circuit amplifies the input signal to generate a first output signal; and a first resonating circuit, coupled to the first amplifying circuit, wherein a first resonating frequency of the first resonating circuit is not equal to the operating frequency. 
   These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  shows an amplifying apparatus according to an embodiment of the present invention. 
       FIG. 2  shows the relationship between frequencies and transferring characteristics of the amplifying apparatus in  FIG. 1 . 
       FIG. 3  shows the amplifying circuit represented by an NMOS transistor. 
       FIG. 4  shows the relationship between the input capacitor and the voltage at the gate of the NMOS transistor in  FIG. 3 . 
       FIG. 5  shows the relationship between the transconductance and the voltage at the gate of  FIG. 3 . 
   

   DETAILED DESCRIPTION 
     FIG. 1  shows an apparatus  100  according to an embodiment of the present invention. The apparatus  100  is utilized for amplifying an input signal S i , where the input signal S i  corresponds to at least one operating frequency f o . The apparatus  100  comprises a first amplifying circuit  102 , the first resonating circuit  104 , a second amplifying circuit  106 , and a second resonating circuit  108 .  FIG. 1  only shows the devices related to the disclosure of the present invention, but this is not a limitation of the present invention. The first amplifying circuit  102  is utilized for amplifying the input signal S i  to generate a first output signal S o1 , where the first amplifying circuit  102  comprises a first transistor M 1 , and the gate N 1  of the first transistor M 1  receives the input signal S i . Please note that, in this embodiment, the first amplifying circuit  102  is a class AB amplifying circuit. The first resonating circuit  104  comprises an inductor L 1  and a capacitor C 1 , the inductor L 1  being connected in parallel with the capacitor C 1 . A first resonating frequency f soc1  of the first resonating circuit  104  is lower than the operating frequency f o . The second amplifying circuit  106  is utilized for amplifying the first output signal S o1  to generate a second output signal S o2 , the second amplifying circuit  106  comprises a second transistor M 2 , and the gate N 2  of the second transistor M 2  receives the first output signal S o1 . Please note that, in this embodiment, the second amplifying circuit  106  is a class A amplifying circuit. The second resonating circuit  108  comprises an inductor L 2  and a capacitor C 2 , and the inductor L 2  is connected in parallel with the capacitor C 2 . Furthermore, a second resonating frequency f soc2  of the second resonating circuit  108  is higher than the operating frequency f o . Please note that, as is well known by those skilled in this art, either parallel connection or series connection of at least a capacitor, an inductor, and a resistor can implement the above-mentioned resonating circuit, and both modifications fall within the scope of the present invention. 
   The first resonating frequency f soc1  of the apparatus  100  is obtained by equation (1):
 
 f   soc1 =1/(2π( L   1   C   1 ) 1/2 )  (1)
 
   The second resonating frequency f soc2  is obtained by equation (2):
 
 f   soc2 =1/(2π( L   2   C   2 ) 1/2 )  (2)
 
   In real operation, the input signal S i  is received from a previous stage circuit, such as a mixer (not shown), and the second output signal S o2  is transmitted to a next stage circuit, such as an antenna module (not shown). Please note that the applications of the power amplifier are prior art, and are therefore omitted here for brevity. Furthermore, the above-mentioned inductors L 1 , L 2 , and capacitors C 1 , C 2  include the parasitic inductor and parasitic capacitor at the gate N 1  and gate N 2  respectively. Please refer to  FIG. 2 .  FIG. 2  shows the relationship between frequencies and transferring characteristics of  FIG. 1 . The curve  201  is the relationship between frequencies and transferring characteristics from the input signal S i  to the second output signal S o2  of the apparatus  100 . The curve  201  is obtained through the addition of curve  202  and curve  203 . The curve  202  is the relationship between frequencies and transferring characteristics from the input signal S i  to the first output signal S o1  of the apparatus  100 , and the curve  203  is the relationship between frequencies and transferring characteristics from the first output signal S o1  to the second output signal S o2 . Furthermore, the frequency of the peak of the curve  202  and the curve  203  correspond to the first resonating frequency f osc1  of the first resonating circuit  104  and the second resonating frequency f osc2  of the second resonating circuit  108 , respectively, as shown in  FIG. 2 . 
   Because the power (i.e. amplitude) of the input signal S i  received by the apparatus  100  of the present invention is changed in order to conform to system requirements, the equivalent capacitor C 1  at the gate N 1  of the first transistor M 1  of the first amplifying circuit  102  will perform a nonlinear variation with respect to the amplitude of the input signal S i . Similarly, the equivalent capacitor C 2  at the gate N 2  will also perform a nonlinear variation with respect to the amplitude of the first output signal S o1 . For brevity, the class A amplifying circuit and the class AB amplifying circuit of the apparatus  100  are simplified into an NMOS transistor (N-type Metal Oxide Semiconductor Transistor), as shown in  FIG. 2 . Please refer to  FIG. 3 .  FIG. 3  shows the amplifying circuit represented by an NMOS transistor. The gate of the NMOS transistor comprises an input capacitor C gate , wherein the voltage of the gate is V gate , and the transconductance of the NMOS transistor is G m . Furthermore, the values of the input capacitor C gate  of the NMOS transistor are different with respect to the state of the NMOS transistor, which is WC ov  at cut-off, (⅔)WLC ox +WC ov  at saturation, and WLC ox +WC ov  at triode region; wherein W is the effective width of the NMOS transistor, L is the effective length of the NMOS transistor, C ov  is the overlap capacitance per unit width, and C ox  is the oxide layer capacitance. According to the variation of the input capacitor C gate  of the NMOS transistor, a diagram shown in  FIG. 4  is obtained.  FIG. 4  shows the relationship between input capacitor C gate  and the voltage V gate  at the gate of  FIG. 3 . The curve  401  in  FIG. 4  is divided into three regions, which are cut-off region, saturation region and triode region. Furthermore, the value of the input capacitor C gate  increases from the cut-off region to the triode region. Normally, the operating point of the class A amplifying circuit and the class AB amplifying circuit are biased at the range of the saturation region, as shown in  FIG. 4 . The difference is that the bias voltage VB AB  of the class AB amplifying circuit is closer to the cut-off region, and the bias voltage VB A  of the class A amplifying circuit is closer to the triode region. Please refer to  FIG. 5 .  FIG. 5  is a characteristic curve diagram illustrating the relationship between the transconductance G m  and the voltage V gate  at the gate terminal of  FIG. 3 . In  FIG. 5 , the curve  501  is divided into three regions, which are cut-off region, saturation region and triode region, wherein the transconductance G m  is an inverted bowl shape. In comparison to the bias voltage of  FIG. 4 , the bias voltage of the class A amplifying circuit is located in the highest flat region of the curve  501 , and the bias voltage of the class AB amplifying circuit is located near to the highest flat region of the curve  501 , which is the saturation region of the transistor, and does not drop into the cut-off region of the transistor. 
   Accordingly, if the amplitude of the input signal S i  at the class AB amplifying circuit (i.e. the first amplifying circuit  102 ) of the apparatus  100  is increasing gradually, then the partial amplitude that results in the transistor dropping into the cut-off region is larger than the partial amplitude that results in the transistor dropping into the triode region. Equivalently, the first transistor M 1  of the class AB amplifying circuit (i.e. the first amplifying circuit  102 ) will first approach the cut-off state. According to  FIG. 4  and  FIG. 5 , when the amplitude of the input signal S i  gets larger finally resulting in most of the amplitude of the input signal S i  dropping into the cut-off region, the capacitance of the input capacitor C gate  at the gate N 1  decreases, and the transconductance G m  of the class AB amplifying circuit also decreases (i.e. the reason behind the linearity shortcoming in the prior art). However, because the first resonating frequency f osc1  of the first resonating circuit  104  in the apparatus  100  is lower than the operating frequency f o , according to equation (1), when the amplitude of the input signal S i  increases, the decreasing of the input capacitor C gate  will result in the first resonating frequency f osc1  increasing, to become closer to the operating frequency f o . Those skilled in this art know that the curve  202  will also approach the operating frequency f o  at the same time, as shown by curve  204 . Similarly, if the amplitude of the first output signal S o1  received by the class A amplifying circuit (i.e. the second amplifying circuit  104 ) of the apparatus  100  increases gradually, then the partial amplitude resulting in the transistor dropping into the triode region is larger than the partial amplitude resulting in the transistor dropping into the cut-off region. Equivalently, the second transistor M 2  of the class A amplifying circuit (i.e. the second amplifying circuit  104 ) will first approach the triode region state. According to  FIG. 4  and  FIG. 5 , when the amplitude of the output signal S o1  gets larger finally resulting in most of the amplitude of the output signal S o1  dropping into the triode region, the capacitance of the input capacitor C gate  at the gate N 2  will first increase, and then decrease. Furthermore, the transconductance G m  of the class A amplifying circuit also decreases (i.e. the reason behind the linearity shortcoming in the prior art). However, because the second resonating frequency f osc2  of the second resonating circuit  108  in the apparatus  100  is higher than the operating frequency f o , according to equation (2), when the amplitude of the output signal S o1  increases, the decreasing of the input capacitor C gate  will result in the second resonating frequency f osc2  decreasing, to become closer to the operating frequency f o . However, those skilled in this art know that the curve  203  will also approach the operating frequency f o  at the same time, shown by curve  205 . Accordingly, the transferring characteristic curve from the input signal S i  to the second output signal S o2  of the apparatus  100  becomes the curve  206 , which is the addition of the curve  204  and the curve  205 . According to  FIG. 2 , the signal transferring characteristics at the operating frequency f o  are increased, which compensates for the lowering part of the transconductance G m  of the class A amplifying circuit and the class AB amplifying circuit caused by the increasing amplitude of the input signal S i . Therefore, the apparatus  100  improves the problem of nonlinear transferring characteristics of the prior art. 
   Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.