Abstract:
An image processing apparatus and method providing a high speed pipeline structure having a low level of complexity is described. The image processing apparatus includes a memory configured to store a plurality of data in a plurality of memory locations, where an ordinally specified data is in a corresponding ordinal memory location.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority to Korean Patent Application No. 10-2011-0009991 filed on Feb. 1, 2011 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference in its entirely. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to an image processing apparatus and method and, more particularly, to an image processing apparatus and method for performing a discrete cosine transform. 
     2. Description of the Related Art 
     Discrete cosine transform (DCT) and quantization processes perform lossy compression and have high complexity. 
     In order to compress an image, DCT converts image data in a spatial domain into DCT coefficients in a frequency domain, and as a result, DCT has the characteristic of decorrelation with energy compaction. DCT is calculated per block, and a converted DCT coefficient is divided into a low frequency region and a high frequency region in the block. A majority of energy components of a signal are concentrated in the low frequency region. 
     In the spatial domain, correlation between image data is high, while the DCT coefficients in the frequency domain eliminate correlation between coefficients. Accordingly, quantization eliminates signals of the high frequency region which do not significantly affect image quality to allow for the performing of lossy compression by using human visual system (HVS) characteristics. 
     Generally, a separable transform scheme is applied for a 2-dimensional DCT (2D-DCT) operation. In detail, one dimensional DCT (1D-DCT) is first performed on 8×8 pixel blocks in a row direction, and then another 1D-DCT is performed on the result in a column direction. 
     As shown in  FIG. 1 , the DCT operation is divided into a total of six stages, and has multiplication as shown in Table 1 below and fixed constants with respect to scaled DCT coefficients c 0  to c 7 . Here, the computation (or calculation) of the scaled DCT coefficients c 0  to c 7  may be included in a quantization process in which a division operation is performed after the 2D-DCT in order to reduce computational quantity. 
     
       
         
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
             
             
               
                 0.125 
                 0.090119978 
                 0.095670858 
                 0.106303762 
                 0.125 
                 0.159094823 
                 0.230969883 
                 0.453063723 
               
               
                 0.090119978 
                 0.064972883 
                 0.068974845 
                 0.076640741 
                 0.090119978 
                 0.114700975 
                 0.166520006 
                 0.326640741 
               
               
                 0.095670858 
                 0.068974845 
                 0.073223305 
                 0.081361377 
                 0.095670858 
                 0.121765906 
                 0.176776695 
                 0.346759961 
               
               
                 0.106303762 
                 0.076640741 
                 0.081361377 
                 0.090403918 
                 0.106303762 
                 0.135299025 
                 0.19642374 
                 0.385299025 
               
               
                 0.125 
                 0.090119978 
                 0.095670858 
                 0.106303762 
                 0.125 
                 0.159094823 
                 0.230969883 
                 0.453063723 
               
               
                 0.159094823 
                 0.114700975 
                 0.121765906 
                 0.135299025 
                 0.159094823 
                 0.202489301 
                 0.293968901 
                 0.576640741 
               
               
                 0.230969883 
                 0.166520006 
                 0.176776695 
                 0.19642374 
                 0.230969883 
                 0.293968901 
                 0.426776695 
                 0.837152602 
               
               
                 0.453063723 
                 0.326640741 
                 0.346759961 
                 0.385299025 
                 0.453063723 
                 0.576640741 
                 0.837152602 
                 1.642133898 
               
               
                   
               
             
          
         
       
     
     In order to perform 1D-DCT on eight pixels, five multiplication processes and 29 addition processes must be performed, and in order to perform 2D-DCT on 8×8 pixel blocks, a total of 80 multiplication processes and 464 addition processes must be performed. When the separable transform scheme is employed to implement 2D-DCT with respect to 8×8 pixel blocks, an arithmetic operation unit must perform 10 multiplication processes (5×2=10) and 58 addition (29×2=58) processes. 
     The related art for 2D-DCT requires a relatively large computational quantity, which, thus, has difficulties in satisfying requirements of a SoC type CMOS image sensor for low complexity and high speed operation. 
     SUMMARY OF THE INVENTION 
     An aspect of the present invention provides an image processing apparatus and method having a high speed-based pipeline structure and low complexity. 
     According to an aspect of the present invention, there is provided an image processing apparatus including: a memory configured to store a plurality of data in a plurality of memory locations, where an ordinally specified data is in a corresponding ordinal memory location. The apparatus also includes an arithmetic operation unit configured to receive data from the memory and update the memory with results of arithmetic operations performed on the plurality of data. In a first stage the arithmetic operation unit is configured to update for use in a second stage a first memory location with a sum of first and eighth data, a second memory location with a sum of second and seventh data, a seventh memory location with a difference between the second and the seventh data, and an eighth memory location with a difference between the first and the eighth data. 
     According to an aspect of the present invention, there is provided an image processing method that includes initializing first to eighth data, where each of the first to eighth data comprises a plurality of bits. The method may also include updating in a first stage for use in a second stage the first data with a sum of the first and the eighth data, a second data with a sum of second and seventh data, a seventh data with a difference between the second and the seventh data, and an eighth data with a difference between the first and the eighth data. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other aspects, features, and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings: 
         FIG. 1  is a view explaining a discrete cosine transform (DCT) operation according to a related art; 
         FIG. 2  is a view showing a partial structure of an exemplary image processing apparatus according to an embodiment of the present invention; 
         FIG. 3  is a view explaining an exemplary discrete cosine transform (DCT) operation according to an embodiment of the present invention; 
         FIG. 4  is a block diagram showing an exemplary configuration of a DCT 1  according to an embodiment of the present invention; 
         FIG. 5  is a block diagram showing an exemplary configuration of a DCT 2  according to an embodiment of the present invention; 
         FIG. 6  is a view showing an exemplary configuration of three addition units of an arithmetic operation unit according to an embodiment of the present invention; 
         FIG. 7  is a view showing an exemplary configuration of three subtraction units of the arithmetic operation unit according to an embodiment of the present invention; 
         FIG. 8  is a view showing an exemplary configuration of four multiplication units of the arithmetic operation unit according to an embodiment of the present invention; 
         FIG. 9  is a signal timing diagram showing an operational example of the multiplication units according to an embodiment of the present invention; 
         FIG. 10  is a view showing an exemplary configuration of a first transpose memory TM 1  according to an embodiment of the present invention; 
         FIG. 11  is a view showing an exemplary pingpong type memory accessing procedure used by the TM 1  according to an embodiment of the present invention; 
         FIG. 12  is a view showing an exemplary pingpong type memory accessing procedure used by a second transpose memory TM 2  according to an embodiment of the present invention; 
         FIG. 13  is a signal timing diagram of control signals of an exemplary image processing apparatus according to an embodiment of the present invention; and 
         FIG. 14  is a view showing operational results of an exemplary image processing apparatus having 2D-DCT according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. 
     In the drawings, the shapes and dimensions may be exaggerated for clarity, and the same reference numerals will be used throughout to designate the same or like components. 
     Throughout the specification and claims, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising,” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements. 
       FIG. 2  is a view showing a partial structure of an exemplary image processing apparatus according to an embodiment of the present invention. 
     With reference to  FIG. 2 , the image processing apparatus may include a line memory controller (LMC)  100 , a two-dimensional discrete cosine transform unit (2D-DCT)  200 , and a quantization unit  300 . The LMC  100  reads 8×8 pixel blocks of data from a line memory. The 2D-DCT unit  200  performs 2D-DCT on the 8×8 pixel blocks of data, and a quantization unit  300  performs quantization on the results of the two-dimensional discrete transform from the 2D-DCT unit  200  and provides the quantized results to a variable length coding (VLC) unit (not shown) at a rear stage. The 2D-DCT unit  200  may include a first discrete cosine transform unit DCT 1  and a second discrete cosine transform unit DCT 2 . Each of DCT 1  and DCT 2  performs discrete cosine transform (DCT) by using, for example, three addition units, three subtraction units, and four multiplication units. A transpose memory  1  (TM 1 )  230  stores the results outputted from the DCT 1   210  in a row direction and reads the stored results in a column direction to provide to the DCT 2   220 . A transpose memory  2  (TM 2 )  240  stores the results outputted from the DCT 2   220  in a row direction and reads the stored results in a zigzag manner to provide to the quantization unit  300 . 
     When the LMC  100  outputs data in units of 8×8 pixel blocks, the LMC  100  packs two 8-bit data into one 16-bit data. 
     The DCT 1   210  receives the data in units of 8×8 pixel blocks from the LMC  100  and performs DCT thereon. The data outputted from the DCT 1   210  is delivered to the DCT 2   220  in the column direction through the TM 1   230 . When the DCT 2   220  performs DCT on the data transferred through the TM 1   230 , the TM 2   240  converts the resultant data into zigzag reordering sequence data and provides the stored data to the quantization unit  300 . 
       FIG. 3  is a view for explaining an exemplary discrete cosine transform (DCT) operation according to an embodiment of the present invention. A fast DCT process called the AAN DCT according to an embodiment of the present invention is optimized in structure in terms of timing and domain so as to be suitable for hardware implementation. 
     As shown in  FIG. 3 , arithmetic operation units required for DCT according to an embodiment of the present invention include three addition units ADD 0  to ADD 2 , three subtraction units SUB 0  to SUB 2 , and four multiplication units MUL 0  to MUL 3 . These arithmetic operation units perform DCT according to an arithmetic operation process determined in each step by using a step counter scnt[2:0] having a 3-bit width. The addition units ADD 0  to ADD 2  and subtraction units SUB 0  to SUB 2  may require a calculation time of one clock, while the multiplication units MUL 0  to MUL 3  may require a calculation time of two clocks. 
     Nine pong registers p 0   —   r   0 [15:0]˜p 0   —   r   8 [15:0] store outputs from the arithmetic operation units, and in particular, the ninth pong register retrieves an input of a multiplication process from a different pong register and stores it in order to allow the multiplication units MUL 0 ˜MUL 3  requiring the calculation time of two clocks to smoothly operate. 
     The operation of the fast AAN DCT is designed to be performed in real-time with minimum logic, and the operation is performed in order in the direction indicated by the arrows in  FIG. 3  along with the step counter scnt[2:0]. Namely, after eight pong registers p 0   —   r   0 [15:0]˜p 0   —   r   7 [15:0] are initialized with eight ping data provided by the LMC  100 , the arithmetic operation units ADD 0 ˜ADD 2 , SUB 0 ˜SUB 2 , and MUL 0 ˜MUL 3  receive the data currently stored in the pong registers at every clock and perform calculation, and update the pong registers with the calculated values for a next operation. 
     In stage 1 (scnt=1), the sum of a first and an eighth data (b 0 =a 0 +a 7 ) is written to the first register, the sum of a second and a seventh data (b 1 =a 1 +a 6 ) is written to the second register, the difference between the second and the seventh data (b 6 =a 1 −a 6 ) is written to the seventh register, and the difference between the first and eighth data (e 7 =a 0 −a 7 ) is written to the eighth register. The other registers remain the same. 
     In stage 2 (scnt==2), the sum of a third and a sixth data (b 2 =a 2 +a 5 ) is written to the third register, the sum of a fourth and a fifth data (b 3 =a 3 +a 4 ) is written to the fourth register, the difference between the fourth and the fifth data (b 4 =a 3 −a 4 ) is written to the fifth register, and the difference between the third and the sixth data (b 5 =a 2 −a 5 ) is written to the sixth data. The other registers remain the same. 
     In stage 3 (scnt==3), the sum of the fifth and the sixth data (c 4 =b 4 +b 5 ) is written to the fifth register, the sum of the sixth and the seventh data (d 5 =b 5 +b 6 ) is written to the sixth register, and the sum of the seventh and the eighth data (c 6 =b 6 +b 7 ) is written to the seventh register. The other data remain the same. 
     In stage 4 (scnt==4), the sum of the first and the fourth data (c 0 =b 0 +b 3 ) is written to the first register, the sum of the second and the third data (c 1 =b 1 +b 2 ) is written to the second register, the difference between the second and the third data (c 2 =b 1 −b 2 ) is written to the third register, the difference between the first and the fourth data (c 3 =b 0 −b 3 ) is written to the fourth register, and the difference between the fifth and the seventh data (d 6 =c 4 −c 6 ) is written to the ninth register. The other data remain the same. In a first clock of a 2-clock multiplication, the second cosine constant and the fifth data are multiplied (e 4 =m 2   c   4 ), a first cosine constant and the sixth data are multiplied (e 5 =m 1   d   5 ), and a third cosine constant and the seventh data are multiplied (e 6 =m 3   c   6 ). 
     In stage 5 (scnt==5), the sum of the first and the second data (g 0 =c 0 +c 1 ) is written to the first register, the difference between the first and the second data (g 1 =c 0 −c 1 ) is written to the second register, and the sum of the third data and the fourth data (d 2 =c 2 +c 3 ) is written to the third register. In the second clock of the 2-clock multiplication, the product of the second cosine constant and the fifth data (e 4 =m 2   c   4 ) is written to the fifth register, the product of the first cosine constant and the sixth data (e 5 =m 1   d   5 ) is written to the sixth register, and the product of the third cosine constant and the seventh data (e 6 =m 3   c   6 ) is written to the seventh register. In the first clock of the 2-clock multiplication, the fourth cosine constant and the ninth data (e 8 =m 4   d   8 ) are multiplied. The other data remain the same. 
     In stage 6 (scnt==6), the sum of eighth and sixth data (f 5 =e 7 +e 5 ) is written to sixth register, and the difference between the eighth and sixth data (f 7 =e 7 −e 5 ) is written to the eighth register. In the second clock of the 2-clock multiplication, the product of the fourth cosine constant and the ninth data (e 8 =m 4   d   8 ) is written to the ninth register. In the first clock of the 2-clock multiplication, the first cosine constant and the third data (e 2 =m 1   d   2 ) are multiplied. The other data remain the same. 
     In stage 7 (scnt==7), in the second clock of the 2-clock multiplication, the product of the first cosine constant and the third data (e 2 =m 1   d   2 ) is written to the third register. The sum of the fifth data and the eighth data (f 4 =e 4 +e 8 ) is updated into the fifth register, and the sum of the seventh and the eighth data (f 6 =e 6 +e 8 ) is written to the seventh register. The other data remain the same. 
     At stage 8 (scnt==8), the sum of the fourth and the third data (g 2 =c 3 +e 2 ) is written to the third register, the difference between the fourth and the third data (g 3 =c 3 −e 2 ) is written to the fourth register, the sum of the eighth and the fifth data (g 4 =f 7 +f 4 ) is written to the fifth register, the sum of the sixth and the seventh data (g 5 =f 5 +f 6 ) is written to the sixth register, the difference between the sixth and the seventh data (g 6 =f 5 −f 6 ) is written to the seventh register, and the difference between the eighth and the fifth data (g 7 =f 7 −f 4 ) is written to the eighth register. Thereafter, the previously obtained first and second data (g 0 , g 1 ) and the currently obtained third to eighth data (g 2 ˜g 8 ) are provided, for example, serially to the memories TM 1   230  or TM 2   240 . 
     When DCT is performed on the eight pixels in this order, a total of eight clock cycles is required as a calculation time, and 17 clock cycles are required as pipelined latency taken from a first frame until when a first DCT result is obtained. 
       FIG. 4  is a block diagram showing an exemplary configuration of the DCT 1   210  according to an embodiment of the present invention. 
     With reference to  FIG. 4 , the DCT 1   210  may include three multiplexers  211 - 1  to  211 - 3 , three ping registers  212 - 1  to  212 - 3 , four multiplexers  213 - 1  to  213 - 4 , four level shifters  214 - 1  to  214 - 4 , nine multiplexers  215 - 1  to  215 - 9 , nine pong registers  216 - 1  to  216 - 9 , and an arithmetic operation unit  217 . 
     The multiplexers  211 - 1  to  211 - 3  and  213 - 1  to  213 - 4  may be implemented as 2-input and 1-output multiplexers (2×1 MUX), the multiplexers  215 - 1  to  215 - 9  may be implemented as 8-input and 1-output multiplexers (8×1 MUX), and the ping registers  212 - 1  to  212 - 3  and the pong registers  216 - 1  to  216 - 9  may be implemented as registers having a 16-bit width. 
     The multiplexers  211 - 1  to  211 - 3  store first input 16-bit data in the ping register  212 - 1  (i_vid&amp;(dcnt==‘00’)), second input 16-bit data in the ping register  212 - 2  (i_vid&amp;(dcnt==‘01’), and third input 16-bit data in the ping register  212 - 3  (i_vid&amp;(dcnt==‘10’). 
     In this state, when fourth 16-bit data is input, the level shifter  214 - 4  delivers the fourth input 16-bit data to the multiplexer  215 - 1  to  215 - 9 , and at the same time, the other remaining level shifters  214 - 1  to  214 - 3  deliver the data stored in the ping registers  212 - 1  to  212 - 3  to the multiplexers  3   215 - 1  to  215 - 9 . The 16-bit data is unpacked through the level shifters  214 - 1  to  214 - 4 , and a data range is converted from 0˜255 to −128˜127. The data range conversion operation can be easily implemented by inverting a most significant bit (MBS) of the input data. 
     The multiplexers  215 - 1  to  215 - 9  update the pong registers  216 - 1  to  216 - 9  by using the outputs from the level shifters  214 - 1  to  214 - 4  and the outputs from the arithmetic operation unit  217 , and the arithmetic operation unit  217  performs the operation procedure as shown in  FIG. 3  by using the data stored in the pong registers  216 - 1  to  216 - 9 . 
     This operation is iteratively performed until such time as the DCT operation of the DCT 1   210  is completed, and the pong registers  216 - 1  to  216 - 9  are iteratively updated. 
       FIG. 5  is a block diagram showing an exemplary configuration of the DCT 2   220  according to an embodiment of the present invention. With reference to  FIG. 5 , the DCT 2   220  according to an embodiment of the present invention is configured and operated in a similar manner to the DCT 1   210 , except that the DCT 2   220  includes eight 16-bit ping registers, instead of three 16-bit ping registers, and does not have level shifters like those in the DCT 1   210 . 
     The DCT 2   220  does not need level shifters because DCT 1  has already performed data conversion. The reason for replacing the three 16-bit ping registers with eight 16-bit ping registers is because unpacked data is used in the DCT 2   220 . 
       FIG. 6  is a view showing an exemplary configuration of the three addition units of the arithmetic operation unit according to an embodiment of the present invention, in which inputs and outputs of the addition units are 16 bits and operate in one clock cycle. 
     With reference to  FIG. 6 , the three addition units  400  include three adders  413  to  433 , first and second input units  411 ,  421 ,  431 , and  412 ,  422 ,  432  controlling inputs to the adders  413  to  433 , multiplexers  414  to  434  controlling outputs from the adders  413  to  433 , and a controller  440  generating signals adden[0:2] for controlling operation of the multiplexers  414  to  434 . The controller  440  includes a 2×1 multiplexer  441 , a 8×1 multiplexer  442 , and a flipflop  443 , and generates a 3-bit operation control signal adden( 3 ). 
     The first and second input units  411 ,  421 ,  431 , and  412 ,  422 ,  432  provide the data stored in the pong registers  216 - 1  to  216 - 9  to the adders  413  to  433  according to the operation procedure of  FIG. 3 . For example, as described with respect to  FIG. 3 , the first input unit  411  connected to the adder  413  may sequentially output first data a 0 , third data a 2 , fifth data b 4 , first data b 0 , first data c 0 , eighth data e 7 , fifth data e 4 , and fourth data c 3 . Similarly, the second input unit  412  may sequentially output eighth data a 7 , sixth data a 6 , sixth data b 5 , fourth data b 3 , second data c 1 , sixth data e 5 , ninth data e 8 , and fourth data c 3 . 
     Then, the adders  413  to  433  may add the outputs from the first and second input units  411 ,  421 ,  431 , and  412 ,  422 ,  432 , and the multiplexers  414  to  434  may select addition results to be provided to the multiplexers  215 - 1  to  215 - 9  according to a control signal (adden[0], [1], [2]) from the controller  440 . 
       FIG. 7  is a view showing an exemplary configuration of the three subtraction units of the arithmetic operation unit according to an embodiment of the present invention. In  FIG. 7 , the three subtraction units are configured and operated in a similar manner to the three addition units of  FIG. 6 . 
     The three subtraction units  500  in  FIG. 7  include three subtractors  513  to  533  that are able to perform a 2&#39;s complement operation, first and second input units  511 ,  521 ,  531 , and  512 ,  522 ,  532  controlling inputs to the subtractors  513  to  533 , multiplexers  514  to  534  controlling outputs from the subtractors  513  to  533 , and a controller  540  generating a signal suben[0:2] for controlling operation of the multiplexers  514  to  534 . The subtractors  513  to  533  may be implemented as an inverter  533   a  inverting second data sub 0 _in 2 ( 16 ) and an adder  533   b  adding 1 and first data sub 0 _in 1 ( 16 ) to an output from the inverter  533   a.    
       FIG. 8  is a view showing an exemplary configuration of the four multiplication units of the arithmetic operation unit according to an embodiment of the present invention. The four multiplication units in  FIG. 8  are configured and operate in a similar manner to the three addition units. 
     The four multiplication units  600  of  FIG. 8  may include four multipliers  613  to  643  performing a multiplication operation, first and second input units  611 ,  621 ,  631 ,  641  and  612 ,  622 ,  632 ,  642  controlling inputs to the multipliers  613  to  643 , multiplexers  614  to  644  controlling outputs from the multipliers  613  to  643 , and a controller  650  generating signal mulen[0:4] for controlling the operation of the multiplexers  614  to  644 . 
     Here, the multipliers  614  to  644  is required to process data having a data range including a negative number, so they must be able to perform both a shift operation and addition (shift+adder) along with a signed extension. 
     The first input units  611 ,  621 ,  631 , and  641  first divide cosine constants m 1  to m 4  including floating points into a 1-bit integral part and 10-bit decimal part, and assigns a total of 11 bits, and the second input units  612 ,  622 ,  632 , and  642  receive 16-bit data from the pong registers. The multipliers  614  to  644  perform a rounding operation by using the outputs from the first and second inputs  611 ,  621 ,  631 ,  641  and  612 ,  622 ,  632 ,  642  to generate 26 bits, and selectively stores only 16-bit integral part in a corresponding pong register. 
     The four multiplication units  600  are designed by using a multi-cycle path as shown in  FIG. 9  to secure a timing margin, and an operation cycle time is 2 clock cycles. 
       FIG. 10  is a view showing an exemplary configuration of the TM 1   230  according to an embodiment of the present invention. 
     The TM 1   230  of  FIG. 10  includes two register type single-port block memories  231  and  232  each having a 64-bit depth and 16-bit width, and a multiplexer  233  selectively outputting one of outputs from the memories  231  and  232 . The TM 1   230  performs memory access in a pingpong manner as shown in  FIG. 11 . 
     A write activation signal mwen, a 6-bit memory address signal maddr( 6 ), and a 16-bit memory input mdin( 16 ), and a clock signal jclk are used to read data dout 0 ( 16 ) and dout 1 ( 16 ) from the single-port block memories  231  and  232 , respectively. One of the output data dout 0 ( 16 ) and dout 1 ( 16 ) are selected by a memory trigger (mtrg) signal as a 16-bit output dout( 16 ) of the TM 1   230 . 
       FIG. 11  is a view showing an exemplary pingpong type memory accessing procedure used by the TM 1   230  according to an embodiment of the present invention. 
     As shown in  FIG. 11 , write access is performed in the row direction, and read access is performed in the column direction. Data, which have passed through the DCT in the row direction, are stored in one of the single-port block memories  231  and  232  in the row direction, while data are read in the column direction from the other of the single-port block memories  231  and  232 . 
     Here, a memory address (addr) is generated by using a partial combination of counter signals (rcnt[2:0], rcen[5:3]) and (rcnt[2:0], mcen) with respect to reading and writing. 
     The TM 2   240  according to an embodiment of the present invention is configured as shown in  FIG. 10 , but it performs a memory accessing procedure as shown in  FIG. 12  to zigzag-reorder data output from the DCT 2   220   
       FIG. 12  is a view showing an exemplary pingpong type memory access procedure used by the TM 2  according to an embodiment of the present invention. 
     As shown in  FIG. 12 , write access is performed in the row direction and read access is performed in a zigzag manner. A read address is generated by using a memory (ROM) having a 62-bit depth and a 16-bit width formed by zigzag reordering sequence mapping (addr=zzaddr), and a write address is generated by using a partial combination of counter signals (mcen,rcnt[2:0]). 
     For reference, various control signals required for the operations in an embodiment of the present invention may have a signal timing diagram as shown in  FIG. 13 . 
       FIG. 14  is a view showing operational results of an exemplary image processing apparatus having 2D-DCT according to an embodiment of the present invention. 
     As shown in  FIG. 14 , it is noted that when the image processing apparatus according to an embodiment of the present invention is used, in one frame, as for first pipelined latency t 1 , the results with respect to 8×8 pixel blocks are output every 17 clocks; as for 8×8 pixel 2D-DCT latency t 1 ˜t 3 , the results with respect to 8×8 pixel blocks are output at every 100 clocks; and as for final latency t 1 ˜t 5 , the results with respect to 8×8 pixel blocks are output at every 173 clocks, and the results with respect to 8×8 pixel blocks are output at every 64 clocks from a pipeline full. 
     As set forth above, according to embodiments of the invention, the image processing apparatus and method can provide a high speed-based pipeline structure and low complexity. 
     While the present invention has been shown and described in connection with the embodiments, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the spirit and scope of the invention as defined by the appended claims.