Abstract:
An electrostatic discharge (ESD) protection circuit and method thereof are presented. In some embodiments, a high voltage tolerant input/output circuit comprises an ESD detection circuit, a first first-type transistor, a first second-type transistor, and a second second-type transistor. The first first-type transistor and the first second-type transistor are coupled to a pad. The ESD detection circuit determines whether ESD occurs at the pad and, if so, couples the gates of the first and second second-type transistors to the second power rail.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates in general to an ESD protection circuit and method thereof, and more specifically to a high voltage tolerant input/output circuit avoiding damage to N-type MOS transistors from electrostatic discharge (ESD).  
         [0003]     2. Description of the Related Art  
         [0004]     In the development of the semiconductor manufacture process, dimensions of complementary metal-oxide-semiconductor transistor (CMOS) have reached sub-micron level to upgrade the performance of very large scale integrated (VLSI) circuits and computational speed. As dimensions shrinks, reliability and ESD tolerance of VLSI circuits decline significantly.  
         [0005]     ESD models include human-body model (HBM), machine model (MM), and charged-device model (CDM). All three generate instantaneous current of several amperes only for hundreds or even several nanoseconds.  
         [0006]      FIG. 1  is a schematic diagram of a conventional high voltage tolerant CMOS VLSI input/output circuit. As shown in  FIG. 1 , the sources of the PMOS transistors P 110 -P 11   n  are coupled to the power rail Vcc 1 , gates of the PMOS transistors P 110  and P 111  are coupled to the power rail Vcc 1 , and gates of the PMOS transistors P 112 -P 11   n  are coupled to pre-driver P 1 . The drains of the NMOS transistors N 110 -N 11   n  and the corresponding drains of the PMOS transistors P 110 -P 11   n  are coupled to a pad  10 , and all gates of the NMOS transistors N 110 -N 11   n  are coupled to the power rail Vcc 1 . The sources of the NMOS transistors N 120 -N 12   n  in another row are coupled to the corresponding sources of the NMOS transistors N 110 -N 11   n . According to the driving requirement, gates of the NMOS transistors N 120  and N 121  are connected to the power rail Vss 1 , and gates of the NMOS transistors N 122 -N 12   n  are coupled to pre-driver N 1 . The NMOS transistors N 110 -N 11   n  and the NMOS transistors N 120 -N 12   n  are connected in series, and the reliability of the NMOS transistors N 120 -N 12   n  is enhanced by voltage division. When ESD occurs at the pad  10 , the discharge current follows the path of the PMOS transistors P 110 -P 11   n , the NMOS transistors N 110 -N 11   n , and the NMOS transistors N 120 -N 12   n . Because the bias conditions of each transistor differ, current discharge is not even, and some transistors damaged.  
         [0007]     The NMOS transistor has an extremely thin gate oxide vulnerable to ESD damage. For example, at the output buffer stage, a commonly used NMOS transistor with a channel width of 300 submicrons can tolerate an ESD voltage of more than 3000 volts if fabricated by conventional 2-submicron manufacture process, and less than 2000 volts if by 1-submicron manufacture process with low-doping-drain (LDD) technology, and about 1000 volts if by 1-submicron manufacture process with LDD and silicide technology. Furthermore, ESD generates an instantaneous discharge current of several amperes in hundreds of nanoseconds. In the high voltage tolerant input/output circuit shown in  FIG. 1 , the ESD current follows a path of some components only, such that current discharge is uneven and slow, and some components are damaged.  
       SUMMARY OF THE INVENTION  
       [0008]     Accordingly, the present invention provides an ESD protection circuit and method thereof. When ESD occurs, the discharge path is increased to evenly discharge the current and avoid damage to N-type MOS transistors.  
         [0009]     One embodiment of the present invention provides an ESD protection circuit comprising an ESD detection circuit, a first first-type transistor, a first second-type transistor, and a second second-type transistor, wherein the drains of the first first-type and second-type transistors are coupled to a pad, the source of the first second-type transistor is coupled to the drain of the second second-type transistor, the source of the first first-type transistor is coupled to a first power rail, and the source of the second second-type transistor is coupled to a second power rail, and, in normal operation, the gate of the first second-type transistor is coupled to the first power rail and the gate of the second second-type transistor is controlled by a pre-driver. The ESD detection circuit determines whether ESD occurs at the pad and, if so, couples the gates of the first and second second-type transistors to the second power rail.  
         [0010]     Another embodiment of the present invention provides a method for protecting devices from ESD, appropriate for a driver circuit wherein the driver circuit has a first first-type transistor, a first second-type transistor, and a second second-type transistor wherein the drains of the first first-type and second-type transistors are coupled to a pad, the source of the first second-type transistor is coupled to the drain of the second second-type transistor, the source of the first first-type transistor is coupled to a first power rail, and the source of the second second-type transistor is coupled to a second power rail. Some embodiments of the method comprise the steps of determining whether ESD occurs at the pad, and, when ESD occurs, coupling the gates of the first and second second-type transistors to the second power rail. When ESD does not occur, the gate of the first second-type transistor is coupled to the first power rail and the gate of the second second-type transistor is controlled by a pre-driver. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]     The following detailed description, given by way of example and not intended to limit the invention solely to the embodiments described herein, is best understood in conjunction with the accompanying drawings, in which:  
         [0012]      FIG. 1  is a schematic diagram of the high voltage tolerant CMOS VLSI input/output circuit according to the prior art.  
         [0013]      FIG. 2  is a block diagram of the high voltage tolerant CMOS VLSI input/output circuit according to an embodiment of the present invention; and  
         [0014]      FIG. 3  is a schematic diagram of the high voltage tolerant CMOS VLSI input/output circuit according to another embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0015]      FIG. 2  is a block diagram of the high voltage tolerant CMOS VLSI input/output circuit according to an embodiment of the present invention. The high voltage tolerant input/output circuit comprises a driver circuit  20 , a redundant circuit  21 , an ESD detection circuit  22 , NOR gates  23  and  26 , inverter circuits  24  and  27 , a voltage shifter  25 , a pad  28 , and a pre-driver P 2  wherein the transistors P 200  and P 201  are PMOS transistors and the transistors N 200 , N 201 , N 202 , and N 203  are NMOS transistors.  
         [0016]     When ESD occurs in the pad  28 , the ESD detection circuit  22  outputs a signal S 22  with a high logic level to the inverter circuit  27  and the NOR gate  26 . The inverter circuit  27  outputs a signal S 22 ′ with a high logic level to gates of the NMOS transistors N 200  and N 202  after receiving S 22 . The voltage levels of S 22 ′ and the power rail Vss 2  are equal, such that gates of the NMOS transistors N 200  and N 202  are coupled to the power rail Vss 2 . The NOR gate  26  outputs a signal S 20 ′ to the gate of the NMOS transistor N 201  after receiving S 22 . The voltage levels of S 20 ′ and the power rail Vss 2  are equal, such that the gate of the NMOS transistor N 201  is coupled to the power rail Vss 2 .  
         [0017]     In normal operation, the ESD detection circuit  22  outputs a signal S 22  with a low logic level to the inverter circuit  27  and the NOR gate  26 . The inverter circuit  27  outputs a signal S 22 ′ with a low logic level to gates of the NMOS transistors N 200  and N 202  after receiving S 22 . The voltage levels of S 22 ′ and the power rail Vcc 2  are equal, such that gates of the NMOS transistors N 200  and N 202  are coupled to the power rail Vcc 2 . In normal operation, a signal S 20  is input into the NOR gate  23 , through the inverter circuit  24 , the voltage shifter  25 , and the NOR gate  26 , and is output as a new signal S 20 ′ to the gate of the NMOS transistor N 201 . The logic levels of S 20 ′ and S 20  are inverted, thus the gate of the NMOS transistor N 201  is coupled to the power rail Vcc 2  or the power rail Vss 2 . Moreover, in normal operation, the gate of the PMOS transistor P 200  receives the signal from pre-driver P 2 .  
         [0018]      FIG. 3  shows detailed circuits and descriptions of several components shown in  FIG. 2 .  
         [0019]     The driver circuit  20  comprises a PMOS transistor P 200  and NMOS transistors N 200  and N 201  wherein the drain of the PMOS transistor P 200  and the drain of the NMOS transistor N 200  are coupled to a pad  28 , the source of the NMOS transistor N 200  is coupled to the drain of the NMOS transistor N 201 , the source of the PMOS transistor P 200  is coupled to a power rail Vcc 2 , as shown in  FIG. 3 . The source of the NMOS transistor N 201  is coupled to a power rail Vss 2 .  
         [0020]     The redundant circuit  21  comprises a PMOS transistor P 201  and NMOS transistors N 202  and N 203 , wherein the drain of the PMOS transistor P 201  and the drain of the NMOS transistor N 202  are coupled to the pad  28 . The source of the NMOS transistor N 202  is coupled to the drain of the NMOS transistor N 203 . The source of the PMOS transistor P 201  is coupled to the high power rail Vcc 2 . The source and the gate of the NMOS transistor N 203  are coupled to the low power rail Vss 2 .  
         [0021]     The ESD detection circuit  22  is coupled to the power rail Vcc 2 , thereby detecting ESD at the pad  28  according to the voltage of the power rail Vcc 2 . The ESD detection circuit  22  comprises a plurality of NMOS transistors connected together in series wherein the drain and the gate of each NMOS transistor are coupled. The ESD detection circuit  22  couples gates of the NMOS transistors N 200 , N 201 , and N 202  to the power rail Vss 2  when ESD occurs at the pad  28 .  
         [0022]     The NOR gate  23  is controlled by the voltage of the power rail Vss 2  and the received signal S 20 . The NOR gate  23  outputs a signal S 23  at the output end wherein the logic levels of S 23  and S 20  are inverted.  
         [0023]     The inverter circuit  24  comprises a PMOS transistor P 202  and an NMOS transistor N 204  wherein the gates of PMOS transistor P 202  and NMOS transistor N 264  are coupled to receive the signal S 23 . The source of the PMOS transistor P 22  is coupled to a power rail Vcc 3 . The source of the NMOS transistor N 204  is coupled to the power rail Vss 2 . The sources of the PMOS transistor P 202  and the NMOS transistor N 204  are coupled at a node  3 .  
         [0024]     The voltage shifter  25  is coupled to the inverter circuit  24  at node  3 . The voltage shifter  25  comprises PMOS transistors P 203  and P 204  and NMOS transistors N 205  and N 206 . The gate of the NMOS transistor N 206  is coupled to node  3 . The gate of the NMOS transistor N 205  is coupled to the output end of the NOR gate  23  to receive the signal S 23 . The gate of the PMOS transistor P 203 , the drain of the PMOS transistor P 204 , and the drain of the NMOS transistor N 206  are coupled at node  4 . Both sources of the PMOS transistors P 203  and P 204  are coupled to the power rail Vcc 2 . Both sources of the NMOS transistors N 205  and N 206  are coupled to the power rail Vss 2 . The drain of the PMOS transistor P 203 , the gate of the PMOS transistor P 204 , and the drain of the NMOS transistor N 205  are coupled at node  5 . A plurality of diodes T 0 -Tn are connected in series between the voltage supplies Vcc 2  and Vcc 3 , such that the voltage of the power rail Vcc 3  is lower than that of the power rail Vcc 2 . If the PMOS transistor P 202  is turned on and the NMOS transistor N 204  is turned off, node  3  is coupled to the power rail Vcc 3 , thus the voltages of node  3  and the power rail Vcc 3  are equal. The output end of the voltage shifter  25 , node  5 , is coupled to the power rail Vcc 2 . Thus, the voltages of node  5  and the power rail Vcc 2  are equal.  
         [0025]     The NOR gate  26  is coupled to the ESD detection circuit  22 , to receive the signal S 22 , and to the voltage shifter  25  at node  5 . In normal operation, the NOR gate  26  controls the gate of the NMOS transistor N 201  according to the voltage level of node  5 . When ESD occurs at the pad  28 , the NOR gate  26  couples the gate of the NMOS transistor N 201  to the power rail Vss 2  according to the ESD detection circuit  22 . The NOR gate  26  comprises PMOS transistors P 205  and P 206  and NMOS transistors N 207  and N 208 . The gates of PMOS transistor P 205  and NMOS transistor N 207  are coupled to the ESD detection circuit  22 . The gates of PMOS transistor P 206  and NMOS transistor N 208  are coupled to the voltage shifter  25  at node  5 . The source of the PMOS transistor P 205  is coupled to the drain of the PMOS transistor P 206 . The source of PMOS transistor P 206  is coupled to the power rail Vcc 2 . The sources of the NMOS transistors N 207  and N 208  are coupled to the power rail Vss 2 . The drains of PMOS transistor P 205 , NMOS transistor N 207 , and NMOS transistor N 208  are coupled to the gate of the NMOS transistor N 201  at node  2 .  
         [0026]     The inverter circuit  27  is coupled to the ESD detection circuit  22  to receive the signal S 22  and to couple the gates of the NMOS transistors N 200  and N 202  to the power rail Vss 2  when ESD occurs at the pad  28 . The inverter circuit  27  is composed of a NOR gate having two input ends. One end is coupled to the power rail Vss 2 , and the other end receives the signal S 22 . The NOR gate comprises PMOS transistors P 207  and P 208  and an NMOS transistor N 209 . The gates of PMOS transistor P 207  and NMOS transistor N 209  are coupled to receive the signal S 22 . The gate, the source, and the drain of the PMOS transistor P 208  are coupled to the power rail Vss 2 , the power rail Vcc 2 , and the source of PMOS transistor P 207 , respectively. The drains of PMOS transistor P 207  and NMOS transistor N 209 , and gates of NMOS transistor N 200  and NMOS transistor N 202 , are all coupled at node  1 .  
         [0027]     When ESD occurs, the voltage of the pad  28  increases. Because of the PN junction current leakage of the PMOS transistor P 201 , the voltage level of the power rail Vcc 2  also increases. When the voltage level of the power rail Vcc 2  reaches a fixed value, the plurality of NMOS transistors in the ESD detection circuit  22  coupled to the power rail Vcc 2  is turned on (here regarded as diodes due to connection type). With voltage division, the signal of the power rail Vcc 2  goes through the plurality of NMOS transistors to output the signal S 22  with a high logic level. Meanwhile, the signal S 22  is input into the inverter circuit  27 , such that the NMOS transistor N 209  is turned on and the PMOS transistor P 207  is turned off. Node  1  is coupled to the power rail Vss 2 . Thus, the voltages of node  1  and the power rail Vss 2  are equal, and gates of the NMOS transistors N 200  and N 202  are coupled to the power rail Vss 2 . Also, the signal S 22  is input into NOR gate  26 . The signal S 22 , with a high logic level, turns on the NMOS transistor N 207  and turns off the PMOS transistor P 205 , such that node  2  is coupled to the power rail Vss 2 . Thus, the voltages of node  2  and the power rail Vss 2  are equal. Moreover, the gate of the NMOS transistor N 201  is coupled to the power rail Vss 2 .  
         [0028]     In normal operation, the power rail Vcc 2  is at a high voltage level and the power rail Vss 2  is at a low voltage level. The voltage of the power rail Vcc 2  turns on the plurality of NMOS transistors in the ESD detection circuit  22  coupled to the power rail Vcc 2  (here regarded as diodes due to connection type). With voltage division, the signal of the power rail Vcc 2  goes through the plurality of NMOS transistors to output the signal S 22  with a low logic level. The logic level of the signal S 22  can be adjusted by controlling the number of NMOS transistors inside the ESD detection circuit  22 . The voltage levels of Vcc 2  differ in normal operation and when ESD occurs, such that the logic level of the signal S 22  is low during normal operation and high during ESD.  
         [0029]     The signal S 22  is input into the inverter circuit  27  to turn off the NMOS transistor N 209  and turn on the PMOS transistor P 207 . Thus, node  1  is coupled to the power rail Vcc 2 , and the voltages of node  1  and the power rail Vcc 2  are equal. Moreover, gates of the NMOS transistors N 200  and N 202  are coupled to the power rail Vcc 2 .  
         [0030]     Furthermore, in normal operation, if the NOR gate  23  receives signal S 20  with a high logic level, then the NOR gate  23  outputs the signal S 23  with a low logic level. The inverter circuit  24  receives the signal S 23  to turn on the PMOS transistor P 202  and to couple node  3  to the power rail Vcc 3  with a high voltage level. Consequently, the voltage level of Vcc 3  is lower than the voltage level of Vcc 2 . Because the gate of the NMOS transistor N 206  of the voltage shifter  25  is coupled to node  3 , NMOS transistor N 206  is turned on and node  4  is coupled to the power rail Vss 2 , and the PMOS transistor P 203  is turned on and node  5  is coupled to the power rail Vcc 2 . Furthermore, the NOR gate  26  receives the signal S 22  with a low logic level to turn off the NMOS transistor N 207  and turn on the PMOS transistor P 205 . Because the gate of the PMOS transistor P 206  and the gate of the NMOS transistor N 208  are coupled to node  5 , the PMOS transistor P 206  is turned off and the NMOS transistor N 208  is turned on. Thus, node  2  is coupled to the power rail Vss 2 , and the voltages of node  2  and the power rail Vss 2  are equal. Moreover, the gate of the NMOS transistor N 201  is coupled to the power rail Vss 2 .  
         [0031]     Similarly, in normal operation, if the NOR gate  23  receives the signal S 20  with a low logic level, then the NOR gate  23  outputs the signal S 23  with a high logic level. The inverter circuit  24  receives the signal S 23  to turn on the NMOS transistor N 204  and to couple node  3  to the power rail Vss 2 . Because the gate of the NMOS transistor N 206  of the voltage shifter  25  is coupled to node  3 , the NMOS transistor N 206  is turned off. The gate of the NMOS transistor N 205  receives the signal S 23  with a high logic level to turn on the NMOS transistor N 205  and to couple node  5  to the power rail Vss 2 . Furthermore, the NOR gate  26  receives the signal S 22  with a low logic level to turn off the NMOS transistor N 207  and turn on the PMOS transistor P 205 . Because the gate of the PMOS transistor P 206  and the gate of the NMOS transistor N 208  are coupled to node  5 , the PMOS transistor P 206  is turned on and the NMOS transistor N 208  is turned off. Thus, node  2  is coupled to the power rail Vcc 2 , and the voltages of node  2  and the power rail Vcc 2  are equal. Moreover, the gate of the NMOS transistor N 201  is coupled to the power rail Vcc 2 .  
         [0032]     In conclusion, in normal operation, gates of the NMOS transistors N 200  and N 202  are coupled to the power rail Vcc 2 , and the gate of the NMOS transistor N 201  is coupled to the power rail Vcc 2  or the power rail Vss 2  according to the signal S 20 . The PMOS transistor P 200  is controlled by pre-driver P 2  and outputs signals at the pad  28  to a back end. When ESD occurs, gates of the NMOS transistors N 201 , N 200 , and N 202  are coupled to the power rail Vss 2 , such that the bias conditions of the NMOS transistors N 200 , N 201 , N 202 , and N 203  are the same. Thus the NMOS transistors can be turned on at the same time to discharge the ESD current, thereby increasing the discharge path to avoid potential damage to transistors.  
         [0033]     While embodiments of the invention have been described by way of example and in terms of the preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.