Abstract:
A semiconductor memory device provided with an improved word line drive circuit is disclosed. The memory device comprises a pair of decoding units, a plurality of word lines, a plurality of N-channel transistors coupled between first ends of the word lines and the output terminal of one of the pair of decoding unit, and a plurality of P-channel transistors coupled between second, opposite ends of the word lines and the output terminal of the other of the pair of decoding units.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a semiconductor memory device fabricated on a semiconductor substrate and more particularly to a word line drive circuit thereof for selectively driving word lines. 
     Semiconductor memories are formed by arranging a large number of memory cells in a matrix form of rows and columns and memory cells are coupled to word lines arranged in rows and digit lines in columns. A read operation is performed by selecting one of the word lines The memory cells coupled to the selected word line produce read-out signals on the respective digit lines. While, in a write operation, one of the word lines is selected and the memory cells coupled to the selected memory cells are enabled to take therein the levels of the respective digit lines to which write data signals are applied. 
     In a recent tendency, the number of memory cells, that is memory capacity, is remarkably increased, and 256 k-bit and 1 M-bit memory devices are now commercially available 
     Accompanied by the increase in the memory capacity, the number of word lines is greatly increased and the number of address signals for selecting each word line is also increased. Therefore, the number of transistors of each decoding unit for each word line is thus increased and hence it has become difficult to arrange each decoding unit with a minimum pitch of the word lines. Under such circumstance, it has been proposed such technique that a plurality of word lines are classified into a plurality of word line groups and a first decoder for selecting one of the word lines groups and a second decoder for selecting one of the word lines of the selected word line group are employed. According to the above technique, a transfer gate field effect transistor is coupled between each word line and the relevant output of the first decoder for selectively transferring the output of the first decoder to the relevant word line under control of the second decoder. 
     However, as is well known in the art, the potential applied to the selected word line is lower than the potential of a power voltage (Vcc) by a threshold voltage (Vth) of the transfer gate transistor. 
     Therefore, it is difficult to raise the potential of the selected word line to the power voltage Vcc for high speed operation and maximum utilization of the power voltage. 
     Moreover, the capacitances of the respective word lines are also increased in proportion to the increase in the memory capacity, so that a time constant of the word line is increased in its longitudinal direction, causing low speed driving of the word line. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a semiconductor memory device provided with an improved word line drive circuit which can drive a selected word line at a high speed. 
     The semiconductor memory device according to the present invention comprises at least one group of word lines arranged in parallel, memory cells coupled to the word lines, at least one pair of decoding units generating the same logic level of output signals simultaneously, a plurality of first field effect transistors of N-channel type coupled between one ends of the word lines of the same group and the output terminal of one of the pair of decoding units, and a plurality of second field effect transistors of P-channel type coupled between second, opposite ends of the word lines of the same group and the output terminal of the other of the pair of decoding units. The plurality of first and second transistors are controlled in such manner that one of the first transistors and one of the second transistors associated with the same word line coupled to the above one first transistor are made simultaneously conductive to allow the output signals of the pair of decoding units to be applied to the word line via the conductive one first transistor and the conductive one second transistor. 
     According to the present invention, the word line to be selected is driven at its both ends via the N-channel transistor and the P-channel transistor simultaneously. Therefore, the word line can be rapidly raised to the power voltage without level reduction upon selection, and rapidly changed from the selected state to the non-selected state to reach the reference voltage. 
     Thus, the word line can be driven with full swing of the power supply voltage range at a high speed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic block diagram showing a memory device according to a prior art; 
     FIG. 2 is a schematic block diagram showing a major part of a semiconductor memory device according to one embodiment of the invention; and 
     FIG. 3 is a timing diagram showing operations of the memory device of FIG. 2: 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIG. 1, a semiconductor memory device according to a prior art will be explained. 
     A plurality of word lines WL 11  -WL n4  are arranged in rows and every four adjacent word lines are classified into &#34;n&#34; word line groups 10-l to 10-n. A plurality of digit lines DL l  -DL m  are arranged in columns. A plurality of memory cells MC each composed of a known floating gate field effect transistor Q M  are provided with connection to the word lines and the digit lines. 
     NAND gates NA l  -NA n  receiving combinations true and complementary row address signals A l  (A l )-A k  (A k ) are provided in association with the word line groups 10-l to 10-n, respectively, and a selected one of the NAND gates produces a &#34;0&#34; level out signal while other remaining NAND gates produce a &#34;1&#34; level output. The outputs of the NAND gates NA l  -NA n  are applied to inputs of inverters I l  -I n . Between the output of the inverter I l  and the four word lines WL 11  -WL 14 , transfer gates transistors Q 11  -Q 14  of an N-channel type are connected while N-channel transistors Q 21  -Q 24  are connected between the word lines WL 11  -WL 14  and a reference voltage Vss such as a ground potential. 
     Selection signals a 1  -a 4  are applied to gates of the transistors and their complementary signals a 1  -a 4  are applied to gates of the transistors Q 21  -Q 24 , as illustrated. The signals a 1  -a 4  and a 1  -a 4  are such signals that are generated by decoding 2-bits of row address signals other than A l  -A k  in a known way. 
     When the word line WL 11  is to be selected, the output of NA l  is at a &#34;0&#34; (low) level and therefore the output of the inverter I l  is at a &#34;1&#34; (high) level. Also, the signals a 1  and a 1  are at &#34;1&#34; and &#34;0&#34; levels, respectively with a 2  -a 4  at a &#34;0&#34; level and a 2  -a 4  at a &#34;1&#34; level. Thus, the transistor Q 11  is rendered conductive to transmit the &#34;1&#34; level output of the inverter I l  to the word line WL 11 . While in this instance, the transistors Q 12  -Q 14  are non-conducting and the transistors Q 22  -Q 24  are conducting so that the word lines WL 12  -WL 14  are nonselected but clamped to Vss. 
     In the memory circuit of FIG. 1, the &#34;1&#34; level output of the inverter I 1  is usually the Vcc level and the &#34;1&#34; level of the signal a l  is also the Vcc level so that the level of the selected word line WL 11  is at the level of (Vcc-Vth) (Vth being a threshold voltage of the transistors Q 11 ). Therefore, it is impossible to apply the power voltage Vcc to the selected word line via the transfer gate transistor Q 11 . For example, in case of Vcc=5 V, Vth=0.8V, the selected word line is driven only to 4.2 V, resulting in low utilization efficiency of the power voltage. 
     Moreover, the word lines have time constant in their length and the far end of the selected word line needs some delay time for being driven to the selected level (Vcc-Vth). 
     Referring to FIG. 2, a semiconductor memory according to a preferred embodiment of the invention will be explained. 
     In FIG. 2, the portions or elements corresponding to those in FIG. 1 are denoted by the same reference codes. 
     The NAND gates NA l  -NA h  and the inverters I l  -I n  are arranged on a left side of the word line groups 10-1 to 10-n similarly to the memory of FIG. 1: NAND gates NA l  &#39; to NA n  &#39; and inverters I l  &#39; to I n  &#39; are provided on a right side of the word line groups 10-1 to 10-n, respectively. 
     The right-side NAND gates NA l  &#39; to NA n  &#39; correspond to the left-side NAND gates NA l  to NA n  in function, respectively. Namely, each one of the left-side NAND gates, e.g. NA l  and one of the right-side NAND gates associated with the same word line group e.g. 10-1 receive the same combination of row address signals and produce the same state of output signals. 
     In the group 10-1, N-channel type field effect transistors Q 11  to Q 14  are coupled between the output of the left-side inverter I l  and the left ends of the word lines WL 11  to WL 14 . The transistors Q 11  -Q 14  are controlled by the selection signals a l  -a 4 . 
     While between the output of the right-side inverter I l  &#39; and the right ends of the word lines WL 11  to WL 14 , P-channel field effect transistors Q 31  to Q 34  are coupled, respectively. The P-channel transistors Q 31  to Q 34  are controlled by the selection signals a l  to a 4  which are complementary to the selection signals a l  to a 4 , respectively. 
     The N-channel transistors Q 21  to are coupled between the center portions N 1  to N 4  of the word lines WL 11  to WL 14  and the reference voltage Vss, respectively. The N-channel transistors Q 21  to Q 24  are controlled by the signals a l  to a 4 , respectively. As explained in connection with FIG. 1, the selection signals a to a 4  and their complementary signals a 1  to a 4  are the decoded signals of 2-bits of row address signals other than A l  -A k  and one of a l  to a 4  is made the selective (&#34;1&#34;) level. The structure of other groups 10-2 to 10-n is the same as the group 10-1. 
     With reference to FIG. 3, the operation of the memory of FIG. 2 will be explained. 
     At a time point t l , a new access cycle (T l ) is initiated and a new state of row address signals A l  -A k  are received Then, one of the left-side NAND gates and one of the right side NAND gates associated with the same word line group produce the &#34;0&#34; (low) level outputs. For example, when the word line WL 11  is to be selected, the outputs A 11  and A 12  of the NAND gate NA l  and NA l  &#39; are at the &#34;0&#34; level while the outputs of other NAND gates are at the &#34;1&#34; level. 
     Also, one of the selection signals, in this case a l  is selected and made at the &#34;1&#34; level with other signals a 2  -a 4  of the &#34;0&#34; level 
     Therefore, the complementary signal a 1  and a 2  to a 4  are at the &#34;0&#34; level and &#34;1&#34; level, respectively. 
     As a result, the N-channel transistor Q 11  and the P-channel transistor Q 31  are both conductive so that the &#34;1&#34; level outputs of the inverters I l  and I l  &#39; are transmitted to the left and right ends of the word line WL 11  via Q 11  and Q 31 , respectively. 
     Since, the left end NL l  of the word line WL 11  is driven via the N-channel transistor Q 11 , the left end NL l  is first raised to the voltage of &#34;Vcc-V TN  &#34; (V TN  being a threshold voltage of the N channel transistor Q 11 ) while the right end NR 1  of the word line WL 11  is immediately raised to the Vcc level via the P-channel transistor Q 31 . Then, after a transmission delay of the Vcc level from NR l  to the center portion N l  and further to the left end NL l , the potentials of the center portion N 1  and the left end NL 1  are raised to the Vcc level. In this instance, the non-selected word lines WL 12  -WL 14  are clamped to the Vss level via the transistors Q 22  to Q 24  which are rendered conductive in response to the &#34;1&#34; level of a 2  to a 4   
     Then, at a time point t 2 , the cycle T 1  is terminated and the selection of the word line WL 11  is also terminated. Therefore, the outputs A 11  and of the NAND gates NA l  and NA 2  are changed to the &#34;1&#34; level. 
     In this instance, the selection signal a 1  remains at the &#34;1&#34; level for a short period Thus, the Vcc level of the word line WL 11  is discharged to the &#34;0&#34; level outputs of the inverters I l  and I l  &#39; via the transistors and Q 31 . The level of the right end NR l  is once fallen to the level of &#34;Vss+|V TP  |&#34; (V TP  being a threshold voltage of the P-channel transisto Q 31 ) while the left end NL l  is immediately fallen to the Vss level via the transisto Q 11 . Then, the center portion and the right end NR 1  of the word line WL 11  are gradually fallen to the Vss level 
     Since the clamp transistors to Q 21  Q 24  are coupled to the center portions of the respective word lines, the word lines are effectively clamped to the Vss level in the case of non-selection. 
     As has been explained, the selected word line is driven to the selective level from its both ends via the N-channel transistor and the P-channel transistor Therefore, the selected word line can be raised to the Vcc level without level reduction at a high speed upon selection thereof and fallen to the Vss level at a high speed upon non-selection Thus, a high speed drive of the word line can be achieved.