Abstract:
An active pixel sensor cell array in which a two-stage amplifier amplifies the output of each cell. The two-stage amplifier design reduces fixed pattern noise in the image data generated by reading the array, by providing increased gain for the output of each cell without impractically increasing the size and complexity of each cell. For each column of cells of the array, one part of the two-stage amplifier for each cell is shared by all cells of the column, and another part of the two-stage amplifier for each cell is included within the cell itself. Preferably, each cell includes only NMOS transistors (no cell includes a PMOS transistor). In preferred embodiments, a differential amplifier within each cell is the primary stage of the cell&#39;s output amplifier, PMOS load circuitry including a secondary output amplifier stage is shared by all cells of the column, and the two amplifier stages for each cell together comprise an op amp. In some such preferred embodiments, the op amp is provided with capacitor feedback for increased gain. Another aspect of the invention is an active pixel sensor cell including a differential amplifier, and PMOS transistor load circuitry coupled to the cell. Preferably, the differential amplifier is the first stage of an op amp, and the remainder of the op amp, including optional capacitor feedback circuitry, is coupled to the cell but is not included within the cell.

Description:
FIELD OF THE INVENTION 
     The present invention pertains to an output amplifier for an active pixel sensor cell array. More particularly, the invention pertains to an output amplifier for an active pixel sensor cell array, the amplifier having a two-stage design that reduces fixed pattern noise in the image data output from the array. 
     DESCRIPTION OF THE RELATED ART 
     Charge-coupled devices (CCDs) have been the mainstay of conventional imaging circuits for converting photons incident at individual pixel sensor cells (of a pixel sensor cell array) into electrical signals indicative of the intensity of light energy incident at each cell. In general, a CCD uses a photogate to convert light energy incident at a cell into an electrical charge, and a series of electrodes to transfer the charge collected at the photogate to an output sense node. 
     Although CCDs have many strengths, including high sensitivity and fill-factor, CCDs also suffer from a number of weaknesses. These weaknesses include limited readout rates and dynamic range limitations, and notably, the difficulty in integrating CCDs with CMOS-based microprocessors. 
     To overcome the limitations of CCD-based imaging circuits, imaging circuits have been developed which use active pixel sensor cells to convert pixels of light energy into electrical signals. An active pixel sensor cell typically includes a conventional photodiode and a number of transistors which provide amplification, readout control, and reset control in addition to producing the electrical signal output from the cell. 
     FIG. 1 is an example of two identical CMOS active pixel sensor cells (10 and 11) having conventional design, connected along a column of an active pixel sensor cell array, and circuitry 21 for use in reading all cells connected along the column. 
     As shown in FIG. 1, cell 10 includes photodiode d1 (connected as shown between ground and Node 3), and reset transistor N1. Transistor N1 is an NMOS transistor whose drain is connected to a power supply node (Node 1) maintained at potential V cc , whose source is connected to Node 3, and whose gate is connected to Node 2. The gate of transistor N1 is controlled (in a manner to be described below) by a RESET voltage supplied to Node 2. 
     Cell 10 also includes buffer transistor N2 and row select transistor N3, each of which is an NMOS transistor. Transistor N2 has a drain connected to Node 1, a source connected to Node 4, and a gate connected to Node 3. Transistor N3 has a drain connected to Node 4, a source connected to Node 6, and a gate connected to Node 5. The gate of transistor N3 is controlled (in a manner to be described below) by a ROW SELECT voltage supplied to Node 5. 
     As shown in FIG. 1, circuitry 20 includes detection and calculation circuit 21 whose input terminal is connected to Node 6. Circuit 21 includes a sense amplifier which outputs digital data indicative of light intensity incident at each selected cell along the column in response to voltages at Node 6 during a sampling period when each such cell is selected. Circuit 21 typically also implements correlated double sampling (&#34;CDS&#34;) or another post-processing method on the digital data output from the sense amplifier. 
     In normal operation, circuit 21 receives a sequence of voltages at Node 6 (which node is common to all cells connected along the column), with each pair of consecutive voltages being indicative of light intensity incident (during a sampling period) at a different one of the cells along the column. 
     Circuitry 20 also includes NMOS transistor N6 (whose drain is connected to Node 6 and whose source is connected to ground) and a current mirror (comprising current source I1 and NMOS transistors N4 and N5 connected as shown) which provides the necessary load for reading out the cells. Transistor N5 of the current mirror preferably sinks no more than a small current (from Node 6 to ground), since fixed pattern noise resulting from mismatches in the channel lengths of the buffer transistors in the cells will increase with increasing current sunk by the current mirror. 
     The gate of transistor N6 (at Node 8) is controlled by a Column Reset signal. Use of a column reset transistor such as transistor N6 is described in U.S. patent application Ser. No. 08/871,519 entitled &#34;Active Pixel Sensor Cell that Reduces Noise in the Photo Information Extracted from the Cell,&#34; filed on Jun. 9, 1997, naming Richard B. Merrill as inventor and assigned to the assignee of the present application. 
     Briefly, in operation of the FIG. 1 array, transistor N6 is used as a switch to place a defined voltage (ground potential) on Node 6 before circuit 21 reads one of the cells (e.g., cell 10). Preferably, the gate of transistor N6 is pulsed with a high level of column reset voltage &#34;COLUMN RESET&#34; prior to each pulsing of the row select voltage ROW SELECT. By pulsing the column select voltage COLUMN RESET just prior to each pulsing of the row select voltage ROW SELECT, the voltage at Node 6 is pulled to zero (ground potential) just prior to reading of the relevant one of the cells. When the voltage on Node 6 is set to zero immediately prior to pulsing the row select voltage, resulting noise (in the data determined by circuit 21) is reduced substantially. For example, in one implementation of FIG. 1, the noise is reduced from approximately 15 mV (in the case that N6 remains &#34;off&#34; at all times) to approximately one millivolt. 
     Also in accordance with the teaching of U.S. patent application Ser. No. 08/871,519 entitled &#34;Active Pixel Sensor Cell that Reduces Noise in the Photo Information Extracted from the Cell,&#34; filed Jun. 9, 1997, switch transistor N6 is optionally replaced by a switch transistor whose channel terminals are connected between Node 6 and power supply Node 1, and whose gate is coupled to receive the column select voltage COLUMN RESET. By pulsing the voltage COLUMN RESET just before each pulsing of the row select voltage, the switch transistor pulls up the voltage at Node 6 to voltage Vcc just prior to reading of each cell. This technique also reduces noise in the data determined by circuit 21. 
     The operation of sampling (reading) each cell (e.g., cell 10) begins by briefly pulsing the gate of the cell&#39;s reset transistor N1 with a high level of reset voltage &#34;RESET.&#34; This high level of the reset voltage (typically equal to Vcc, where Vcc is typically 5 volts) resets the voltage on photodiode d1 to an initial integration voltage to begin an image collection cycle. 
     Immediately after assertion of such pulse of the voltage signal &#34;RESET,&#34; the initial integration voltage on photodiode d1 (the voltage at Node 3) is V ini  =VRESET-V TN1  -V CLOCK , where V TN1  is the threshold voltage of transistor N1, VRESET is the high level of the voltage signal &#34;RESET,&#34; and V CLOCK  represents reset noise from the pulsed reset voltage (assumed to be constant). Similarly, the initial integration voltage at Node 4 is VRESET-V TN1  -V CLOCK  -V TN2 , where V TN2  is the threshold voltage of buffer transistor N2 (functioning as a source follower). 
     After the reset voltage has been pulsed and the voltage on photodiode d1 (the voltage at Node 3) has been reset, the gate of transistor N3 is pulsed with a high level of row select voltage signal &#34;ROW SELECT.&#34; The high level of the row select voltage causes the voltage at Node 4, which represents the initial integration voltage of the cycle, to appear at Node 6. Detection and calculation circuit 21 then amplifies, digitizes, and stores the value of the initial integration voltage as it appears at Node 6. 
     Next, for a selected time period, photons are allowed to strike photodiode d1, thereby creating electron-hole pairs. Photodiode d1 is designed to limit recombination between the newly formed electron-hole pairs. 
     As a result, the photogenerated holes are attracted to the ground terminal of photodiode d1, while the photogenerated electrons are attracted to the positive terminal of photodiode d1, each additional electron reducing the voltage at Node 3. At the end of this image collection cycle, a final integration voltage will be present at Node 3. The final integration voltage is V f  =V ini  -V S  =VRESET-V TN1  -V CLOCK  -V S , where V S  represents the change in voltage (at Node 3) due to the absorbed photons. Similarly, the final integration voltage at Node 4 is VRESET-V TN1  -V CLOCK  -V TN2  -V S . 
     At the end of the image collection cycle, the gate of transistor N3 is again pulsed with a high level of row select voltage signal &#34;ROW SELECT&#34; to cause the voltage at Node 4, which represents the final integration voltage of the cycle, to appear at Node 6. Detection and calculation circuit 21 amplifies and digitizes the value of the final integration voltage as it appears at Node 6, and generates data indicative of the number of photons that have been collected during the image collection cycle by calculating the difference (V S ) between the digitized final integration voltage taken at the end of the cycle and the digitized stored initial integration voltage taken at the start of the cycle. 
     After the final integration voltage has been latched by detection and calculation circuit 21, the reset voltage RESET is again pulsed to reset the voltage on photodiode d1 to begin another image collection cycle. 
     One of the problems with active pixel sensor cells (e.g., cell 10 of FIG. 1) is that during typical operation, the reset voltage RESET and the row select voltage ROW SELECT have high levels for periods (typically about 30 msec) which are sufficiently long to introduce a substantial amount of 1/f noise into the cell. Such 1/f noise, which results from trapping and detrapping of surface charges, can be accurately modeled as variations in the threshold voltages of transistors N1, N2, and N3. Due to such noise, the number of photons which are absorbed by photodiode d1 during an image collection cycle is more properly expressed as (VRESET-V TN1  -V CLOCK  -V TN2 )-(VRESET-V TN1  -V CLOCK  -V TN2  -V S  -V.sub.α), where V.sub.α  is a contribution due to variations in the threshold voltages of transistors N1, N2, and N3 due to 1/f noise. Thus, the variations in the threshold voltages of transistors N1, N2, and N3 add an error term V.sub.α  which erroneously yields V S  +V.sub.α  as the value determining the number of absorbed photons, thereby limiting the accuracy of the cell. 
     In some applications (as explained in U.S. patent application Ser. No. 08/707,933, filed on Sep. 10, 1996, naming Richard B. Merrill and Kevin E. Brehmer as inventors and assigned to the assignee of the present application), it is desirable to choose Vcc to be substantially less than VRESET (the high level of the reset voltage RESET). For example, Vcc may be chosen to be 3.3 volts and VRESET may be chosen to be 5 volts. This forces reset transistor N1 to operate in the linear region in which the high level of the reset voltage causes N1 to pull the voltage at Node 3 up to V ini  in a manner subject to reduced variation due to changes in the threshold voltage of reset transistor N1 due to 1/f noise. However, this technique does not eliminate fixed pattern noise due to systematic and random variation among the characteristics of cells of an active pixel sensor cell array. 
     Active pixel sensor cell arrays that use a conventional source follower amplifier in each cell (e.g., arrays of the type described with reference to FIG. 1) are subject to fixed pattern noise due to systematic and random variation between cells. Such fixed pattern noise is due to many different sources of gain variation that cannot easily be corrected with post processing techniques such as correlated double sampling. It has been proposed to implement a better amplifier within each cell (which would be less subject to such gain variation from cell to cell) by including a CMOS amplifier within each cell. Such a CMOS amplifier includes at least one PMOS transistor as a current source load for high gain (in addition to one or more NMOS transistors). Unfortunately, it is not currently possible to integrate a PMOS transistor into a single cell (of an active pixel sensor cell array) without increasing the cell size to an acceptable degree. 
     Conventional CCD imagers are typically subject to significantly less fixed pattern noise than are active pixel sensor cell arrays that include a conventional source follower output amplifier in each cell. It would be desirable to implement an active pixel sensor cell array that is subject to no more fixed pattern noise than a conventional CCD imager, without unacceptably increasing the cell size of such active pixel sensor cell array. 
     SUMMARY OF THE INVENTION 
     In a class of embodiments, the invention is an active pixel sensor cell array in which a two-stage amplifier amplifies the output of each cell of the array. For each column of cells of the array, one part of the two-stage amplifier for each cell is shared by all cells of the column, and another part of the two-stage amplifier for each cell is included within the cell itself. Preferably, the output amplification circuitry within each cell includes only NMOS transistors and does not include any PMOS transistor. In preferred embodiments, a differential amplifier within each cell is the primary stage of the cell&#39;s output amplifier, and PMOS load circuitry including a secondary output amplifier stage is shared by all cells of the column. Preferably, a switchable bias circuit is provided to assert a bias voltage (to the gate of at least one transistor of the load circuitry) whose level depends on the state of a bias control signal. The bias voltage undergoes a transition which rapidly turns off each such transistor of the load circuitry (to reduce power consumption by the array) in response to a transition of the bias control signal from a first level to a second level, and the bias voltage undergoes a transition which causes each such transistor to conduct a desired bias current (needed to amplify fully the photodiode output of each cell to be read) in response to a transition of the bias control signal from the second level to the first level. 
     In preferred embodiments, the two-stage amplifier for each cell is an op amp, and the op amp for each cell comprises NMOS transistors (at least one of which is included in the cell itself) and at least one PMOS transistor, but no PMOS transistor is included within the cell itself. In some such preferred embodiments, at least one op amp is provided with capacitor feedback for increased gain. 
     Another aspect of the invention is an active pixel sensor cell including a differential amplifier (which asserts an amplified signal indicative of a sampled output voltage of the cell&#39;s photodiode) and load circuitry coupled to the cell. The load circuitry includes a secondary amplifier stage (which further amplifies the amplified signal produced within the cell and typically includes at least one PMOS transistor). Preferably, the differential amplifier includes no PMOS transistor. Also preferably, the differential amplifier is the first stage of an op amp, and the remainder of the op amp (including optional capacitor feedback circuitry) is included in the load circuitry. Thus, the remainder of the op amp is coupled to the cell but not included within the cell itself. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of two CMOS active pixel sensor cells (having conventional design) connected along a column of an active pixel sensor cell array, and circuitry for use in reading all cells connected along the column. 
     FIG. 2 is a schematic diagram of two CMOS active pixel sensor cells (which embody the invention) connected along a column of an active pixel sensor cell array, and circuitry which embodies the invention for use in reading all cells connected along the column. 
     FIG. 3 is a simplified schematic diagram of a variation on the FIG. 2 circuit, with only one cell connected along the column. 
     FIG. 4 is a schematic diagram of an alternative embodiment of the invention which is a variation on the FIG. 3 embodiment. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 2 is a schematic diagram of a portion of an active pixel sensor array which embodies the present invention, including active pixel sensor cells 100 and 101 connected along a column of the array, and circuitry (comprising transistors P1, P2, P3, P4, N5, N7, N8, N9, and N10 and current sources I1 and I2) for use in reading cells 100, 101, and all other cells connected along the column. Cell 100 has several structural similarities to cell 10 of FIG. 1. Thus, the same reference numerals are used in FIGS. 1 and 2 to designate the structures which are common to both cells. In FIG. 2, transistors P1, P2, P3, and P4 are PMOS transistors, and transistors N7, N8, N9, N10, and N11 are NMOS transistors. 
     With reference to FIG. 2, the column along which cells 100 and 101 are connected has four column lines: line C1 (to which the drains of N1 and N2 and the channel of P2 are coupled); line C2 (to which the drain of N11 and the channel of P1 are coupled); line C3 (to which the gate of N11, the source of P4, and circuit 21 are coupled); and line C4 (to which the source of N3 and the drain of N5 are coupled). In contrast, in the FIG. 1 array, the column along which cells 10 and 11 are connected has only two column lines (one to which the drain of N1 is coupled and another to which circuit 21 is coupled). In an integrated circuit implementation, the two extra wires needed to fabricate the two extra column lines of the FIG. 2 array can be accommodated with a minimal amount of extra space if three-layer metal is used (so that the two extra wires can be implemented as a third metal layer overlaying either of the other two meal layers). 
     The dashed portions of lines C1-C4 indicate that additional cells (identical to cells 100 and 101) will typically also be connected along the array column including cells 100 and 101. Of course, it is contemplated that the array includes many additional columns (not shown). Thus, the signals ROW SELECT and RESET2 are provided simultaneously to all the cells connected along the same row as is cell 100 (i.e., to one cell in each column of the array). Similarly, the signals ROW SELECT n  and RESET2 n  (which have the same function as signals ROW SELECT and RESET2, respectively, but are asserted independently from signals ROW SELECT and RESET2) are provided simultaneously to all the cells connected along the same row as is cell 101 (i.e., to one cell in each column of the array). If a separate detection and calculation circuit 21 is provided for each column, one cell from each column can be simultaneously read. 
     In operation, the voltage (RESET1) at the gate of PMOS transistor P3 (Node 1) is pulsed low before each read of a cell (e.g., during a sequential read of all cells connected along the column, Node 1 is pulsed low, then cell 100 is read, then Node 1 is again pulsed low, and then cell 101 is read). In cell 100, the step of applying a low voltage pulse to Node 1 resets column line C1 to reference voltage Vref (Vref is typically 3 volts) in order to reduce variation (due to noise) in the voltage at Node 3 during subsequent resetting of photodiode d1. 
     Optionally also, a column reset pulse is asserted to the gate of a column reset transistor whose channel is connected to Node 6, in order to reset Node 6 to a known voltage before each read of a cell by circuit 21 (as described in the above-referenced U.S. patent application entitled &#34;Active Pixel Sensor Cell that Reduces Noise in the Photo Information Extracted from the Cell,&#34; filed on Jun. 9, 1997). 
     After column line C1, and optionally also column line C3 (and thus Node 6), have been reset, a read of a cell is performed. For specificity, the following description of such a read is with reference to cell 100, although it applies (with obvious modifications) to a read of any cell of the array. 
     Initially, the gate (Node 2) of cell 100&#39;s reset transistor N1 is briefly pulsed with a high level of reset voltage &#34;RESET2.&#34; This high level of the reset voltage (typically equal to 5 volts) resets the voltage on photodiode d1 to an initial integration voltage to begin an image collection cycle. 
     Immediately after assertion of such pulse of reset voltage &#34;RESET2,&#34; the initial integration voltage on photodiode d1 (the voltage at Node 3) is V ini  =VRESET-V TN1  -V CLOCK , where V TN1  is the threshold voltage of transistor N1, VRESET is the high level of the voltage signal &#34;RESET2,&#34; and V CLOCK  represents reset noise from the pulsed reset voltage (assumed to be constant). 
     After the reset voltage has been pulsed and the voltage on photodiode d1 (the voltage at Node 3) has been reset, the gate of transistor N3 (Node 5) is pulsed with a high level of row select voltage signal &#34;ROW SELECT.&#34; In accordance with the invention, each sampled photodiode voltage (at Node 3) is amplified by a two-stage amplifier to produce an output voltage (at Node 6) which is detected and processed by detection and calculation circuit 21. Specifically, circuit 21 amplifies, digitizes, and stores the value of the amplified initial integration voltage at Node 6, then amplifies and digitizes the value of the amplified final integration voltage at Node 6, and subtracts the former digital value from the latter digital value to generate data indicative of the number of photons incident at photodiode d1 during the image collection cycle (between the two pulses of the &#34;ROW SELECT&#34; voltage). The difference value (V S ) indicative of the difference between the digitized final integration voltage and the digitized initial integration voltage preferably undergoes correlated double sampling (&#34;CDS&#34;) or other conventional post-processing in circuit 21. 
     The first stage (sometimes referred to herein as the &#34;primary&#34; stage) of the two-stage amplifier comprises NMOS transistors N2 and N11 (connected as shown with their sources at Node 4, the drain of N2 coupled to column line C1, and the drain of N11 connected to column line C2 and thus to the common gate and drain of P1) which form a differential amplifier whose tail current flows to ground through NMOS transistors N3 and N5, and PMOS transistors P1 and P2 (connected as shown with their gates connected together and their sources held at supply voltage Vcc). Transistors P1 and P2 form matched loads for the differential pair N2, N11. Supply voltage Vcc is typically 5 volts. 
     The output of the first stage (the voltage at the drain of N2) is asserted via column line C1 to the gate of PMOS transistor P4. This output is further amplified in the second gain stage (sometimes referred to herein as the &#34;secondary&#34; stage) which consists of PMOS transistor P4 and NMOS transistor N10 connected as shown (with supply voltage Vcc applied to the source of transistor P4, the drain of P4 connected to the drain of N10, and the source of N10 connected to ground). The common drain of transistors P4 and N10 (Node 6) is the output of the secondary stage. 
     As in the FIG. 1 circuit, the gate of transistor N3 (Node 5) is twice pulsed with a high level of row select voltage &#34;ROW SELECT&#34; to read a cell (a first time to assert an initial integration voltage at Node 6, and a second time to assert a final integration voltage at Node 6). Each time the gate of transistor N3 (Node 5) is pulsed with a high level of row select voltage &#34;ROW SELECT&#34; (assuming transistors N10 and N5 are &#34;on&#34; in response to a low voltage at Node 10 and transistor P3 is off in response to a high voltage at Node 1), a partially amplified voltage indicative of the Node 3 voltage (the initial or final integration voltage on photodiode dl) appears on column line C1 and a fully amplified voltage (also indicative of the Node 3 voltage) appears at Node 6 (on column line C3). 
     Between the assertion of the two pulses of the high level of voltage ROW SELECT at the gate of transistor N3 (Node 5), photons are allowed to strike photodiode d1, thereby creating electron-hole pairs. The photogenerated holes are attracted to the ground terminal of photodiode d1, and the photogenerated electrons are attracted to the positive terminal of photodiode d1, each additional electron reducing the voltage at Node 3. At the end of this image collection period, the following final integration voltage will be present at Node 3: V f  =V ini  -V S  =VRESET-V TN1  -V CLOCK  -V S , where V S  represents the change in voltage (at Node 3) due to the absorbed photons. 
     After a read operation is performed on cell 100, another cell (e.g., cell 101) can be read in essentially the same manner: the cell&#39;s first column line (e.g., line C1, for each cell connected along the column that includes cells 100 and 101) is initially reset to reference voltage Vref (optionally also the cell&#39;s output column line, e.g., line C3 for each cell connected along the column that includes cells 100 and 101, is reset), then the cell&#39;s photodiode is reset, and then two pulses of the high level of voltage ROW SELECT are asserted sequentially to the cell to cause two pulses of tail current to flow from the cell&#39;s differential pair to ground. In response to the two pulses of voltage ROW SELECT, detection and calculation circuit 21 generates data indicative of the number of photons incident at the cell&#39;s photodiode during the image collection period (the time period between the two pulses of the voltage ROW SELECT). 
     The described two-stage amplifier (whose primary stage is the differential amplifier comprised of P1, P2, N2, N3, N11 and N5, and whose secondary stage comprises P4 and N10) can be implemented using conventional CMOS fabrication techniques to have a gain of 10,000 or more. Such a large gain effectively reduces typical error due to pixel gain to 0.01% or less, in the following sense. When many cells are read sequentially after each is exposed to identical incident light energy, the error in the output voltage at Node 6 due to systematic and random variation among the characteristics of the cells is not more than 0.01% of the average output voltage at Node 6 (averaged over all cells). 
     In accordance with the invention, a first part of the two-stage amplifier for each cell is implemented within the cell itself (e.g., elements N1, N2, N3 and N11 within cell 100) and another part of the two-stage amplifier is implemented outside the cell (e.g., elements P1, P2, P4, N5 and N10). The latter portion of the two-stage amplifier is shared by all the cells connected along a single column of an array. 
     Still with reference to FIG. 2, the function of the circuit comprising elements N8, N9, N7, I1, and I2 is to turn off transistors N5 and N10 rapidly when desired and to bias them when desired to sink current from their drains. It is desirable to conserve power by turning transistors N5 and N10 off rapidly at times when it is not necessary to sink current through them. The channel of NMOS transistor N7 is connected between supply voltage Vcc and Node 10, and current sink I2 is connected between Node 10 and ground. The gate of N7 is connected to one channel terminal of NMOS transistor N8, and the other channel terminal of transistor N8 is connected to the drain of NMOS transistor N9. The source of transistor N9 is connected to ground and the gate of transistor N9 is connected to Node 10. Current source I1 is connected between supply voltage Vcc and the drain of transistor N9. 
     The level of the voltage &#34;bias on&#34; asserted to the gate of transistor N8 controls the state of transistors N5 and N6 as follows. When &#34;bias on&#34; switches from a low level (e.g., ground potential) to a high level (e.g., 5 volts), elements I1, N9, N8, and N7 function (with transistors N10 and N5) as a current mirror to cause Node 10 to rise rapidly to a level which biases transistors N5 and N10 to sink a level of current appropriate for reading a cell (a cell connected along the column comprising cells 100 and 101). When &#34;bias on&#34; switches from a high level (e.g., 5 volts) to a low level (e.g., ground potential) voltage, Node 10 is rapidly pulled down to ground potential, thereby rapidly turning off transistors N5 and N10. 
     Optionally, elements I1, I2, N7, N8, and N9 of the FIG. 2 embodiment (and variations thereon) are replaced by conventional bias circuitry such as the circuit comprising current source I1 and transistor N4 of FIG. 1. 
     FIG. 3 is a simplified schematic diagram of a variation on the FIG. 2 circuit, with only one cell connected along the column. The FIG. 3 circuit is identical to that shown in FIG. 2 except that the column includes only one cell (cell 100). In FIG. 3, the op amp is implemented by elements P1, P2, N2, N3, N11, P4, N5, N7, N8, N9, I1, I2, and N5 of FIG. 2 (connected as shown in FIG. 2). 
     FIG. 4 is a variation on the FIG. 3 embodiment, which includes capacitor feedback circuitry (capacitors CAP1 and CAP2, and NMOS transistor N12) for increasing the gain of the op amp. The other components of the FIG. 4 circuit are identical to the corresponding, identically identified components of the FIG. 3 circuit and the above description of them with reference to FIGS. 2 and 3 will not be repeated with reference to FIG. 4. In the FIG. 4 circuit, capacitor CAP1 is connected between output node 6 and the gate of transistor N3 (shown in FIG. 2) of the op amp, and capacitor CAP2 is connected between the gate of transistor N3 and ground. As shown in FIG. 4, capacitors CAP1 and CAP2 provide an additional gain of  (CAP1+CAP2)/CAP1! to the output of the cell. 
     In FIG. 4, the channel of transistor N12 and capacitor CAP1 are connected in parallel between output node 6 and the gate of transistor N3 of the op amp. The gate of transistor N12 receives control voltage V3, whose level is varied to switch transistor N12 off and on at desired times during operation. 
     It should be understood that it will typically be desirable to implement any of the embodiments of the inventive cell array so that different gain is provided from cell to cell by the &#34;in-cell&#34; portions of the two-stage amplifiers (the amplifier portion within each cell of the array). For example, the FIG. 2 embodiment can be implemented with the characteristics of transistors N2, N3, and N11 within cell 100 being different from the characteristics of the corresponding transistors within cell 101, so that different &#34;primary stage&#34; gain provided at the gate of transistor P4 when reading cell 100 than is provided at the gate of transistor P4 when reading cell 101. This may be desirable for example, when the output of cell 100 indicates intensity of blue light incident at cell 100&#39;s photodiode and the output of cell 101 indicates intensity of red light incident at cell lolls photodiode (since a photodiode will typically have different response to red light than to blue light, and thus it is desirable to compensate for such different response by the amount of &#34;primary stage&#34; gain provided in the cell). 
     It should be understood that various alternatives to the embodiment of the invention described herein may be employed in practicing the invention. For example, the concepts of the present invention can readily be applied to a row of cells in an array of cells. With an array of cells, a latch/column sense amplifier and a current mirror are utilized with each column of cells. 
     Thus, it is intended that the following claims define the scope of the invention and that structures within the scope of these claims and their equivalents be covered thereby.