Abstract:
A motherboard detection device for a motherboard having a plurality of power input terminals. The power detection device includes a current sampling module, a voltage sampling module, a processor, and a display unit. The current sampling module is connected to the power input terminals for obtaining the current of each power input terminal. The voltage sampling module is connected to the power input terminals for obtaining the voltage of each power input terminal. The processor is connected to the current sampling module and the voltage sampling module for acquiring the current and the voltage of each power input terminal and calculating the input power of each power input terminal based on the current and the voltage of each power input terminal to obtain input power data. The display unit is connected to the processor for receiving the input power data from the processor and displaying the input power data.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure relates to a power detection device for a motherboard. 
         [0003]    2. Description of Related Art 
         [0004]    Many computer motherboards include multiple power input terminals connecting to output terminals on a power supply. It is necessary to determine the input power of the computer motherboard during design. Conventionally, the voltage and the current of each power input terminal is manually determined and input power of each power input terminal is calculated according to the result, a complicated and time consuming requirement. 
         [0005]    What is needed, therefore, is a power detection device capable of overcoming the described limitations. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    Many aspects of the embodiments can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the embodiments. 
           [0007]      FIG. 1  is a schematic view of a power detection device according to an exemplary embodiment, together with a power supply and a motherboard. 
           [0008]      FIG. 2  is a circuit diagram of a voltage sampling module and a current sampling module of the power detection device of  FIG. 1 , together with the power supply and the motherboard. 
           [0009]      FIG. 3  is a circuit diagram of a first electronic switch of the power detection device of  FIG. 1 . 
           [0010]      FIG. 4  is a circuit diagram of a second electronic switch of the power detection device of  FIG. 1 . 
           [0011]      FIG. 5  is a circuit diagram of a processor of the power detection device of  FIG. 1 . 
           [0012]      FIG. 6  is a circuit diagram of a liquid crystal display integrated circuit of the power detection device of  FIG. 1 . 
       
    
    
     DETAILED DESCRIPTION 
       [0013]    Embodiments of the present disclosure are described in detail as follows, with reference to the accompanying drawings. 
         [0014]    Referring to  FIG. 1 , a power detection device  100 , according to an exemplary embodiment, is electrically connected between a power supply  200  and a motherboard  300 . The motherboard detection device  100  includes a processor  10 , a switching unit  20 , an interface module  30 , a current sampling module  40 , a voltage sampling module  50 , and a display unit  60 . 
         [0015]    The processor  10  is a microcontroller unit. In this embodiment, the processor  10  is a PIC16F73 microchip. The processor  10  is connected to the switching unit  20 , the interface module  30 , and the display unit  60 . The interface module  30  is connected to the current sampling module  40  and the voltage sampling module  50 . The current sampling module  40  and the voltage sampling module  50  are both connected to the power supply  200  and the motherboard  300 . 
         [0016]    Referring to  FIG. 2 , the power supply  200  includes a first power output terminal  202 , a second power output terminal  204 , a third power output terminal  206 , a fourth power output terminal  208 , and a fifth power output terminal  210 . The motherboard  300  includes a first power input terminal  302 , a second power input terminal  304 , a third power input terminal  306 , a fourth power input terminal  308 , and a fifth power input terminal  310 . The current sampling module  40  includes a first, a second, a third, a fourth, and a fifth operational amplifiers  410 ,  411 ,  412 ,  413  and  414  and a first, a second, a third, a fourth, and a fifth Manganin wires  420 ,  421 ,  422 ,  423  and  424 . The first Manganin wire  420  is electrically connected between the first power output terminal  202  and the first power input terminal  302 . The second Manganin wire  421  is electrically connected between the second power output terminal  204  and the second power input terminal  304 . The third Manganin wire  422  is electrically connected between the third power output terminal  206  and the third power input terminal  306 . The fourth Manganin wire  423  is electrically connected between the fourth power output terminal  208  and the fourth power input terminal  308 . The fifth Manganin wire  424  is electrically connected between the fifth power output terminal  210  and the fifth power input terminal  310 . 
         [0017]    In this embodiment, each of the first and second power output terminals  202 ,  204  is configured to provide a 12V power source, the third power output terminal  206  is configured to provide a 5V standby power source, the fourth power output terminal  208  is configured to provide a 5V power source, and the fifth power output terminal is configured to provide a 3.3V power source. 
         [0018]    The first operational amplifier  410  detects and amplifies the voltage of the first Manganin wire  420  for the purpose of acquiring the current of the first power input terminal  202 . The first operational amplifier  410  is a LM324DR microchip. The first operational amplifier  410  includes three sub-amplifiers  410   a ,  410   b ,  410   c . The sub-amplifiers  410   a  and  410   b  calculate the voltage of the first Manganin wire  420 , and the sub-amplifier  410   c  amplifies the voltage of the first Manganin wire  420  to acquire a first voltage V I1 . The first voltage V I1  is output to the interface module  30 . 
         [0019]    Each of the second, third, fourth and fifth amplifiers  411 ,  412 ,  413 ,  414  has the same structure as the first amplifier  410 . Each of the second, third, fourth and fifth Manganin wires  421 ,  422 ,  423  and  424  has the same structure as the first Manganin wire  420 . The second, third, fourth and fifth amplifiers  411 ,  412 ,  413 ,  414  are connected to the second, third, fourth and fifth Manganin wires  421 ,  422 ,  423 ,  424  correspondingly. The second, third, fourth and fifth amplifiers  411 ,  412 ,  413 ,  414  respectively output first voltages V I2 , V I3 , V I4 , V I5  to the interface module  30 . 
         [0020]    The voltage sampling module  50  includes a first, a second, a third, a fourth, a fifth voltage dividers  510 ,  511 ,  512 ,  513 ,  514  correspondingly connected to the first, second, third, fourth and fifth power input terminals  302 ,  304 ,  306 ,  308  and  310 . The first voltage divider  510  includes two resistors  510   a ,  510   b  connected in series between the first power input terminal  302  and the ground, for creating and sending a second voltage V V1  to the interface module  30 . 
         [0021]    Each of the second, third, fourth and fifth voltage dividers  511 ,  512 ,  513  and  514  has the same structure as the first voltage divider  510 . The second, third, fourth and fifth voltage dividers  511 ,  512 ,  513  and  514  are respectively configured to output second voltages V V2 , V V3 , V V4 , V V5  to the interface module  30 . 
         [0022]    The interface module  30  converts the current sampling module  40  port and the voltage sampling module  50  port to the processor  10  port. The interface module  30  includes a first electronic switch  31  and a second electronic switch  32 . Also referring to  FIGS. 3 and 4 , the first electronic switch  31  and the second electronic switch  32  are both CD4053BM96 microchips. Each first voltage and a corresponding second voltage both correspond to the same power input terminal and are output to a port of the processor  10  through one of the first and second electronic switches  31  and  31 . 
         [0023]    In this embodiment, the first voltage V I1  is output to a terminal  5  of the first electronic switch  31 . The second voltage V v1  is output to a terminal  3  of the first electronic switch  31 . The first electronic switch  31  transmits the first voltage V I1  and the second voltage V v1  from a terminal  4  thereof to the terminal RA 0 /AN 0  of the processor  10  in order. 
         [0024]    Also referring to  FIG. 5 , The first voltage V I2  is output to a terminal  2  of the first electronic switch  31 . The second voltage V v2  is output to a terminal  1  of the first electronic switch  31 . The first electronic switch  31  transmits the first voltage V I2  and the second voltage V v2  from terminal  15  thereof to the terminal RA 1 /AN 1  of the processor  10  in order. 
         [0025]    The first voltage V I3  is output to a terminal  12  of the first electronic switch  31 . The second voltage V v3  is output to a terminal  13  of the first electronic switch  31 . The first electronic switch  31  transmits the first voltage V I3  and the second voltage V v3  from a terminal  14  thereof to the terminal RA 2 /AN 2  of the processor  10  in order. 
         [0026]    The first voltage V I4  is output to terminal  2  of the second electronic switch  32 . The second voltage V v4  is output to a terminal  1  of the second electronic switch  32 . The second electronic switch  32  transmits the first voltage V I4  and the second voltage V v4  from a terminal  15  thereof to the terminal RA 4  of the processor  10  in order. 
         [0027]    The first voltage V I5  is output to terminal  12  of the second electronic switch  32 . The second voltage V v5  is output to the terminal  13  of the second electronic switch  32 . The second electronic switch  32  transmits the first voltage V I5  and the second voltage V v5  from the terminal  14  thereof to the terminal RA 5  of the processor  10  in order. 
         [0028]    The processor  10  controls the first electronic switch  31 , the second electronic switch  32  through the terminals RA 0 /AN 0 , RA 1 /AN 1 , RA 2 /AN 2 , RA 4  and RA 5 . The processor  10  calculates the input voltage of each power input terminal by: U i =V vi ×(R i /R i0 ), wherein U i  is the input voltage of each power input terminal, V Vi  is the second voltage, R i  is a total impedance of each voltage divider, R i0  is a resistance of a resistor of each voltage divider connected to the ground, i=1, 2, 3, 4, 5. The processor  10  calculates the input current of each power input terminal by: 
         [0000]    
       
         
           
             
               
                 I 
                 i 
               
               = 
               
                 
                   V 
                   Ii 
                 
                 
                   A 
                   × 
                   
                     R 
                     0 
                   
                 
               
             
             , 
           
         
       
     
         [0000]    where I i  is the input current of each power input terminal, V Ii  is the first voltage, A is an amplification factor of each amplifier, R 0  is a resistance of the Manganin wire  420 ,  421 ,  422 ,  423  or  424  of each power input terminal, i=1, 2, 3, 4, 5. The processor  10  calculates the input power of each power input terminal by: P i =U i ×I i , the processor  10  calculates the total power of all power input terminals by: P=ΣP i . The processor  10  outputs the input voltage, input current, input power of each power input terminal, and total power of all power input terminals to the display unit  60  to display. 
         [0029]    The switching unit  20  is connected to the terminal RB 7  of the processor  10 . The switching unit  20  sends a starting signal to start the calculating process of the processor  10 . In the present embodiment, the switching unit  20  includes a pull-up resistor  21  and a button switch  22 . One pin of the button switch  22  is connected to the pull-up resistor  21  and the terminal RB 7 , and the other pin of the button switch  22  is connected to the ground. The terminal RB 7  is connected to the ground when the button switch  22  is closed. When the terminal RB 7  is connected to the ground, the processor  10  will calculate the result. 
         [0030]    Referring to  FIG. 6 , the display unit  60  includes a liquid crystal display integrated circuit  61 . The liquid crystal display integrated circuit  61  includes data pins A 0 -A 2 . The data pins A 0 -A 2  are connected to the RC 0 -RC 2  terminals of the processor  10  correspondingly and configured for receiving the calculation result. 
         [0031]    While certain embodiments have been described and exemplified above, various other embodiments will be apparent to those skilled in the art from the foregoing disclosure. The present disclosure is not limited to the particular embodiments described and exemplified, and the embodiments are capable of considerable variation and modification without departure from the scope of the appended claims.