Abstract:
An integrated circuit interconnection comprising a transmission line having a low characteristic impedance, and including a first end and a second end. A driver is coupled to the first end of the transmission line, and the transmission line is terminated with a current sense amplifier having an input impedance corresponding to the characteristic impedance of the transmission line. A plurality of components selected from the group consisting of capacitive elements, inductive elements and a combination of capacitive and inductive elements are connected at spaced intervals to the transmission line between the first and second ends.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to minimizing clock skews by current mode signals. More particularly, the present invention relates to minimizing clock skews by current mode signals and changing apparent line lengths and transmission time delays. 
     2. Discussion of the Related Art 
     Clock distribution is rapidly becoming one of the dominant design problems due to the increasing die sizes and clock frequencies, even for clock frequencies below 1 GHz. Since the speed of integrated circuits is expected to eventually reach above 10 GHZ, radically different on-chip interconnection and clock distribution schemes will be needed. Consideration has been given to both wireless and optical clock distribution. Wireless communication is described by K. Khong and K. O. Kenneth, “Characteristics of Integrated Dipole Antennas on Bulk, SOI and SOS Substrates for Wireless Communication”, Int. Interconnect Technology Conf., San Francisco, Calif., Jun. 1998, pp. 21-23. Also, U.S. Pat. No. 5,812,708 discloses a method and apparatus for distributing an optical clock in an integrated circuit. 
     The problem with current techniques is that most clock distribution is achieved by voltage signals on RC lines and on capacitance dominated lines. As shown in FIGS. 1A and 1B, the delay (t delay ) in the clocking step signal (v driver (t)) is limited by the RC time constant of the distribution line  20  if the line is high resistance polysilicon, or the RC time constant of the driver  22  output resistance and line capacitance if low resistance metal lines are used. 
     The delay is represented by the equation:        D   =       Zdrv                   C   T       +       (     R1                 C1     )     /   2               where                             D   =   delay     ,                                Zdrv   =     output                 impedance                 of                 the                 driver       ,                                  C   T     =     total                 capacitance                 seen                 by                 the                 driver       ,                                R   =     resistance                 per                 unit                 length                 of                 the                 line                 of                 length       ,   1   ,   and                                C   =     capacitance                 per                 unit                 length                 of                 the                 line                 of                 length       ,   1.                                    
     Known techniques for minimizing clock skew are a tree type distribution system with buffers to drive short lines of equal length, and having all buffers on the same die as described in U.S. Pat. Nos. 5,586,307 and 4,860,322. Other known circuits include a daisy chain clock distribution network described in U.S. Pat. No. 5,546,023. 
     A circuit having lines of equal length is an H-tree distribution network illustrated in FIG. 2 for a 4×4 array of cells to provide lines of equal length. The H-tree network has the property that the clock signal is delayed by an equal amount for each sub-block because all blocks are equidistant from the clock source. 
     L. Maliniak in “DAC Attacks Designer Issues”, Electronic Design, vol. 43, p. 66, Jun. 12, 1995, describes other techniques for minimizing clock skew and delays including making some lines wider than others to increase the capacitance to account for the shorter lengths. Further, U.S. Pat. No. 5,307,381 provides a technique which uses buffers or drivers with various delays designed to compensate for different RC time constant delays and/or delays with can be varied by programming. 
     At higher clock speeds the inductance of even low resistance lines becomes important because the rise time on the waveforms approaches the transit time down the line, or transmission line effects become important. See A. Deutsch et al, “When are Transmission-Line Effects Important for On-Chip Interconnections?”, IEEE Trans. Microwave Theory and Techniques, vol. 45, no. 10, pp. 1836-1846, 1997. 
     Unfortunately such transmission lines use large voltage swings or voltage signaling, and cannot be terminated by a load resistor equal to the characteristic low impedance of the lines. As a result, reflections and ringing occurs which corrupts the clock signal. Also, large voltage signals and low impedance loads will result in excessive power consumption. See L. Maliniak, supra. 
     SUMMARY OF THE INVENTION 
     In accordance with the present invention, clock skew is avoided or at least minimized by changing the apparent length of transmission lines. The apparent length of a line is changed by adding capacitive and/or inductive elements to change the propagation constant and delay time of the line. 
     This is not the same technique as adding capacitance to RC dominated lines to change the time constant of the RC circuit. Adding capacitance to RC dominated lines serves to reduce the rise time or response time and further degrade the signal quality. 
     The capacitive and/or inductive elements are added in accordance with the present invention to change the propagation constant and delay time in the propagation of the signal down the line. Changing the delay time in this manner and by providing matched termination on the line cause the shape and quality of the signal to be maintained and only delays the signal in the time domain. In this manner the delay time along lines of different lengths are made to match and clock skews are eliminated or at least minimized. Conversely desired delays can be purposefully designed into the circuits to provide desired delay times between clocks and/or signals. 
     In accordance with the present invention, there is provided an integrated circuit interconnection comprising a transmission line having a low characteristic impedance, and including a first end and a second end. A driver is coupled to the first end of the transmission line, and the transmission line is terminated with a current sense amplifier having an input impedance corresponding to the characteristic impedance of the transmission line. A plurality of components selected from the group consisting of capacitive elements, inductive elements and a combination of capacitive and inductive elements are connected at spaced intervals to the transmission line between the first and second ends. 
     The combination of low characteristic impedance transmission lines terminated in their characteristic impedance and current sense amplifiers which can discriminate against noise will result in well defined signals with well defined delays. 
     As used herein, “low characteristic impedance” means less than 100 ohms, and preferably less than 50 ohms. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1A is a graph plotting voltage against time to show the delay in the clocking step signal; 
     FIG. 1B is a schematic of a circuit showing the distribution on an R-C line of a clock signal emanating from an equivalent circuit of a driver having a voltage step signal output; 
     FIG. 2 is a schematic drawing of an H-tree distribution network having transmission lines of equal length; 
     FIG. 3 shows an equivalent circuit of a transmission line with load equal to characteristic impedance; 
     FIG. 4 is a top view of a transmission line substrate having capacitive and/or inductive elements added thereto; 
     FIG. 5 is an equivalent circuit of the transmission line of FIG. 4 showing noded capacitive elements added to change the signal delay; 
     FIG. 6A is a graph plotting voltage against time and showing signal delay on a transmission line having matched termination; 
     FIG. 6B is another graph plotting voltage against time and showing the signal on the R-C dominated distribution line wherein increasing capacitance of line further degrades rise time of the signal; 
     FIG. 7 is schematic of a transmission line showing current signal clock distribution with variable delay by added capacitive elements in accordance with the present invention; 
     FIG. 8 is a schematic diagram illustrating an embodiment of the invention with a differential amplifier; 
     FIG. 9 is a schematic diagram illustrating an embodiment of the invention with a pseudo differential amplifier circuit (or pseudo differential latch or single ended receiver); 
     FIG. 10 is a schematic diagram illustrating an embodiment of the invention with a pseudo differential current sense amplifier circuit; 
     FIG. 11A shows a schematic drawing of an embodiment of the invention which includes a current sense amplifier with hysteresis; and 
     FIG. 11B is a graph illustrating the operation of the current sense amplifier of FIG.  11 A. 
    
    
     The above and other features and advantages of the invention will be more readily understood from the following detailed description which is provided in conjunction with the accompanying drawings. 
     DETAILED DESCRIPTION OF THE INVENTION 
     The following disclosure describes current mode signaling for clock distribution on low impedance transmission lines with matched terminations. Ringing and reflections on these lines are minimized and the delay on these lines is known and can be easily characterized. These lines can be shielded lines, shielded differential lines and/or shielded twisted pairs to reduce noise. Current sense amplifiers with hysteresis can be used to further discriminate against noise signals. 
     The combination of low impedance transmission lines terminated in their characteristic impedance and current sense amplifiers which can discriminate against noise will result in well defined signals with well defined delays. 
     FIG. 3 shows an equivalent circuit of a transmission line between a load  32  and a driver  31 . The load  32  is equal to the characteristic impedance. The inductor symbols  34  in FIG. 3 represent inductance per unit length of the transmission line  30 , and the capacitor symbols  36  represent capacitance, per unit length of the line  30 . The delay on the line  30  is characterized by the propagation constant of the line in accordance with:        B   =     j                 w                     (   LC   )       1   /   2                 where                             B   =     propagation                 constant                 of                 line       ,                                L   =     inductance                 of                 line                 per                 unit                 length       ,   and                              C   =     capacitance                 of                 line                 per                 unit                   length   .                                        
     The transit time delay down the line of length is:          t   d     =     l   /   v             where                             t   d     =     transit                 time                 delay                                  l   =     length                 of                 line       ,   and                              v   =       velocity                 of                 the                 signal     =     1   /         (   LC   )       1   /   2       .                                          
     Clock skew could be avoided by having all lines of the same length. However, this would result in excessively long lines since all lines must be as long as the longest one required. It would also result in little flexibility in circuit designs. 
     With reference to FIG. 4, the present invention provides for changing the apparent length of a transmission line  44  in a substrate  40  by adding capacitive and/or inductive elements  42  to alter the propagation constant and delay time of the line  44 . FIG. 5 is an equivalent circuit of the transmission line  44  of FIG. 4 showing noded capacitive elements  42 A added to change the signal delay. As discussed above with reference to FIG. 3, the inductor symbols  46  in FIG. 4 represent inductance per unit length of the transmission line  44 , and the capacitor symbols  48  represent capacitance per unit length of the line  44 . 
     The addition of capacitive and/or inductive elements  42 , as described with reference to FIGS. 4 and 5, is not the same technique as adding capacitance to RC dominated lines to change the time constant of the RC circuit. As shown in FIG. 6B, adding capacitance to a RC dominated line reduces the rise time or response time and further degrades the signal quality. 
     However, when the capacitive and/or inductive elements are added in accordance with the invention the propagation constant and delay time in propagation of the signal down the line are changed. Changing the delay time in this manner and also providing matched termination on the line function to preserve the shape and quality of the signal and only delays the signal in the time domain as shown in FIG.  6 A. The delay time along lines of different lengths is thereby made to match and clock skews are eliminated or at least minimized. Also, desired delays can be designed into the circuits to provide planned delay times between clocks and/or signals. 
     With reference to FIG. 7, there is shown a schematic drawing of a transmission line  70  between a driver  72  and a current sense amplifier  74 . A plurality of interconnection (transmission) lines  76  are provided along the transmission line  70 . Current mode signaling is used on lines which normally have a low characteristic impedance on integrated circuits. These lines are terminated in their characteristic impedance to reduce ringing and reflections. A plurality of capacitive elements  78  are connected at spaced intervals to the transmission line  70  to vary clock signal delay times in accordance with the present invention. 
     The illustration of FIG. 7 shows the capacitive elements  78  as extensions of the interconnection metal wiring. The desired capacitance of elements  42  (FIG.  4 ),  42 A (FIG. 5) and  78  (FIG. 7) can also be provided by the gate capacitances of field effect transistors (FETs) where the FETs are used as capacitors. Specialized capacitive structures such as metal-metal, metal-polysilicon or polysilicon-polysilicon capacitors are also suitable. 
     As noted above with reference to at least FIG. 4, clock signal delay times can also be varied by adding inductive elements in series to the line  44 . If inductors are introduced into the series path they can be implemented as spiral inductors. Also, the self inductance of the line  44  can be increased by the deposition of materials with a higher magnetic permeability. 
     With reference to FIG. 8, there is shown a differential receiver designed for current signaling in order to better impedance match high speed low impedance transmission lines. Low impedance transmission lines such as those which exist on CMOS integrated circuits are more amenable to current signaling over longer transmission lines. The receiver employs feedback to decrease the input impedance of the receiver. The receiver of the present invention can match the low impedance of transmission lines while keeping the sizes of devices small and the power dissipation low. 
     FIG. 8 illustrates a pair of cross coupled complementary metal oxide semiconductor (CMOS) amplifiers, A 1  and A 2  for coupling with interconnection (transmission) lines  152 A,  152 B. Each amplifier, A 1  and A 2 , includes a first transistor, Q 1  and Q 2  respectively, of a first conductivity type. Each first transistor Q 1  and Q 2  includes a source region,  107 A and  107 B, respectively, a drain region,  108 A and  107 B, and a gate,  109 A and  109 B, opposing a body region  110 A and  110 B. Each amplifier, A 1  and A 2 , includes a second transistor Q 3  and Q 4  of a second conductivity type. Each second transistor Q 3  and Q 4  includes a source region,  114 A and  114 B, respectively, a drain region,  116 A and  116 B and a gate,  118 A and  118 B, opposing a body region  120 A and  120 B. In one embodiment, each first transistor, Q 1  and Q 2 , of the first conductivity type includes an n-channel metal-oxide semiconductor (NMOS) transistor. In this embodiment, each second transistor, Q 3  and Q 4 , of the second conductivity type includes a p-channel metal-oxide semiconductor (PMOS) transistor. 
     A plurality of interconnection (transmission) lines  76 A,  76 B are provided along transmission lines  152 A,  152 B. A plurality of capacitive elements  78 A,  78 B are connected at spaced intervals along the transmission lines  152 A,  152 B to vary clock signal delay times as described above with reference to FIG.  7 . 
     As shown in FIG. 8, each amplifier in the pair of cross coupled amplifiers A 1  and A 2  includes a signal input node,  122 A and  122 B, coupled to the source region  107 A and  107 B for the first transistor Q 1  and Q 2 . A signal output node  124 A and  124 B is coupled to the drain regions  108 A and  107 B of the first transistors Q 1  and Q 2  as well as to the drain regions  116 A and  116 B of each second transistor Q 3  and Q 4 . 
     Further, a third transistor, Q 5  and Q 6 , respectively, is included in each of the amplifiers A 1  and A 2 . Each third transistor, Q 5  and Q 6 , includes a source region,  130 A and  130 B respectively, a drain region,  132 A and  132 B, and a gate,  134 A and  134 B, opposing a body region  136 A and  136 B. The gate,  134 A and  134 B, of each third transistor, Q 5  and Q 6 , is coupled to the signal input node,  122 A and  122 B, for each amplifier in the pair of cross coupled amplifiers A 1  and A 2 . The drain region  132 A and  132 B for each third transistor Q 5  and Q 6  is coupled to a positive voltage supply,  138 A and  138 B. The source region  130 A and  130 B for each third transistor Q 5  and Q 6  is coupled to a lower potential,  140 A and  140 B. The drain region  132 A and  132 B for each third transistor Q 5  and Q 6  is additionally coupled to the gate  109 A and  109 B for each first transistor Q 1  and Q 2 . 
     In the embodiment shown in FIG. 8, each amplifier, A 1  and A 2 , includes a fourth transistor, Q 7  and Q 8  respectively, of the first conductivity type. Each fourth transistor Q 7  and Q 8  includes a source region,  144 A and  144 B respectively, a drain region,  146 A and  146 B, and a gate,  148 A and  148 B, opposing a body region  150 A and  150 B. The drain region  146 A and  146 B for each fourth transistor, Q 7  and Q 8 , is coupled to the signal input node,  122 A and  122 B, for each amplifier in the pair of cross coupled amplifiers A 1  and A 2 . 
     In one embodiment of the circuit of FIG. 8, the signal output node  124 A for first amplifier A 1  is cross coupled to the gates  118 B and  148 B for the second transistor Q 4  and the fourth transistor Q 8  of the second amplifier A 2 . Similarly, the signal output node  124 B for second amplifier A 2  is cross coupled to the gates  118 A and  148 A for the second transistor Q 3  and the fourth transistor Q 7  of the first amplifier A 1 . 
     Each signal input node,  122 A and  122 B, for each amplifier in the pair of cross coupled amplifiers A 1  and A 2  is coupled to an input transmission line,  152 A and  152 B respectively, which has a length of at least 500 micrometers (μm), but may have a length of at least 1000 micrometers (μm). In one embodiment, each signal input node,  122 A and  122 B, is coupled to the input transmission line  152 A and  152 B which has a characteristic impedance (Zo) of less than 50 Ohms. In another embodiment, each signal input node,  122 A and  122 B, in the pair of cross coupled amplifiers A 1  and A 2  is coupled to an input transmission line  152 A and  152 B which has a characteristic impedance (Zo) of less than 75 Ohms. Preferably, each signal input node,  122 A and  122 B has an input impedance (Zin) which matches the characteristic impedance (Zo) of the transmission line  152 A and  152 B. 
     FIG. 9 shows another embodiment of the invention having a “pseudo-differential” amplifier  300 . The amplifier  300  is coupled to interconnection (transmission) lines  352 . A plurality of interconnection (transmission) lines  376  are provided along the transmission line  352 . A plurality of capacitive elements  378  are connected at spaced intervals along the transmission line  352  to vary clock signal delay times as described above with reference to FIG.  7 . 
     As used herein, “pseudo-differential amplifier” means an amplifier circuit wherein a single transmission line interconnection is used, and one input of the voltage sense amplifier is driven with a reference potential. The pseudo differential amplifier includes a single signal input node coupled to the single transmission line interconnections, and a pair of signal output nodes, whereby the amplifier is able to convert a single ended input current received at the single signal input node into a differential input signal. 
     Unfortunately, achieving high data rates is difficult with prior art circuits having single-ended or unbalanced signal transmission lines at high frequencies because of large amount of noise is generated in the interconnection system including crosstalk and radiation in backplanes, connectors and cables. The amplifier of FIG. 9 has a single signal input node which is coupled to a source region for one of the transistors in the pair of cross coupled transistors and to a current mirror such that the pseudo differential amplifier is able to convert a single ended input current received at the single signal input node into a differential input signal. 
     FIG. 9 is a schematic diagram which illustrates a pseudo differential amplifier circuit (or pseudo differential latch, or single ended receiver)  300 . FIG. 9 illustrates a pair of cross coupled amplifiers, A 1  and A 2 . The pair of cross coupled amplifiers, A 1  and A 2 , comprise two cross coupled inverters. Each amplifier, A 1  and A 2 , includes a first transistor, Q 1  and Q 2 , respectively, of a first conductivity type. Each first transistor Q 1  and Q 2  includes a source region,  307 A and  307 B, respectively, a drain region,  308 A and  308 B, and a gate,  309 A and  309 B, opposing a body region  310 A and  310 B. Each amplifier, A 1  and A 2 , includes a second transistor Q 3  and Q 4  of a second conductivity type. Each second transistor Q 3  and Q 4  includes a source region,  314 A and  314 B, respectively, a drain region,  316 A and  316 B, and a gate,  318 A and  318 B, opposing a body region  320 A and  320 B. In an embodiment, each first transistor, Q 1  and Q 2 , of the first conductivity type includes a metal oxide semiconductor field effect transistor (MOSFET). In another embodiment, each first transistor, Q 1  and Q 2 , of a first conductivity type includes an n-channel metal-oxide semiconductor (NMOS) transistor. In one embodiment, each second transistor, Q 3  and Q 4 , of the second conductivity type includes a metal oxide semiconductor field effect transistor (MOSFET). Alternatively, each second transistor, Q 3  and Q 4 , of the second conductivity type includes a p-channel metal-oxide semiconductor (PMOS) transistor. The NMOS and PMOS transistors are fabricated according to a complementary metal oxide semiconductor (CMOS) process technology. 
     In FIG. 9, the single signal input node  322  is coupled to the source region,  307 A or  307 B, for one of the first transistors, Q 1  and Q 2 , in the pair of cross coupled amplifiers A 1  and A 2 . By way of illustration, FIG. 9 shows the single signal input node  322  coupled to the source region  307 A of transistor Q 1 . A signal output node  324 A and  324 B in each inverter A 1  and A 2  is coupled to the drain regions  308 A and  308 B of the first transistors Q 1  and Q 2  as well as to the drain regions  316 A and  316 B of each second transistor Q 3  and Q 4 . The signal output nodes  324 A and  324 B in each one of the cross coupled inverters A 1  and A 2  is further coupled to the gates of the first and the second transistors in the other inverter. Hence, signal output node  324 A is coupled to gates  309 B and  318 B of inverter A 2 , and signal output node  324 B is coupled to gate  309 A and  318 A of inverter A 1 . In one embodiment, the signal output nodes  324 A and  324 B are coupled respectively to a pair of output transmission lines  354 A and  354 B. The single signal input node  322  is additionally coupled to a current mirror MI. In one embodiment, the transmission line  352  which has a characteristic impedance (Zo) of less than 50 Ohms is coupled to the signal input node  322 . 
     In FIG. 9, a third transistor, Q 5  and Q 6  respectively, of a first conductivity type is coupled to each amplifier, A 1  and A 2 . Each third transistor includes a source region,  344 A and  344 B respectively, a drain region,  346 A and  346 B, and a gate,  348 A and  348 B, opposing a body region  350 A and  350 B. The drain region  346 A and  346 B for each third transistor, Q 5  and Q 6 , is coupled to the source region,  307 A and  307 B, for each first transistor Q 1  and Q 2  in the pair of cross coupled amplifiers A 1  and A 2 . The single signal input node  322  additionally couples to the gate,  348 A and  348 B, for each third transistor Q 5  and Q 6 . In one embodiment, each third transistor, Q 5  and Q 6 , of a first conductivity type comprise a second pair of MOSFETs of a first conductivity type for the pseudo differential amplifier circuit  300 . In this embodiment, the second pair of MOSFETs of first conductivity type includes a pair of NMOS transistors Q 5  and Q 6 . Also in this embodiment, the pair of NMOS transistors Q 5  and Q 6  are part of the current mirror M 1 . Here, a drain region,  346 A and  346 B, for each one of the pair of NMOS transistors Q 5  and Q 6  in the current mirror M 1  is coupled to a source region,  307 A and  307 B respectively, for each NMOS transistor Q 1  and Q 2  in the pair of cross coupled inverters A 1  and A 2 . The single signal input node  322  is coupled a gate on each one of the pair of NMOS transistors Q 5  and Q 6  in the current mirror M 1 . 
     The pseudo differential amplifier circuit of FIG. 9 eliminates a special problem in the prior art which requires two input signals by facilitating differential sensing capability using a single ended receiver. This solution is achieved as follows. With reference to FIG. 9, the current mirror M 1  converts a single ended input current received at the single signal input node  322  into a differential input signal. 
     For example, output node  324 A and  324 B are precharged to a voltage potential prior to the sensing operation. Next, a current signal is input from input transmission line  352  into single signal input node  322 . When the current signal arrives at single signal input node  322  a portion of the signal flows into the gates  348 A and  348 B for transistors Q 5  and Q 6  serving to turn “on” these transistors. This creates conduction between source region  344 A and drain region  346 A of transistor Q 5  as well as between source region  344 B and drain region  346 B of transistor Q 6 . If the input current signal flows into the drain region  346 A of transistor Q 5  then some current will also flow into the source region  307 A of transistor Q 1 . The current flowing into the source region  307 A of transistor Q 1  will decrease the current flowing out of the drain region  316 A of transistor Q 3  and out of the source region  307 A of transistor Q 1 . The precharged voltage potential, or node voltage V 1 , at output node  324 A will subsequently increase which serves to turn transistor Q 2  on and turn off transistor Q 4 . At the same time, an increase in the conduction between source region  344 A and drain region  346 A in transistor Q 5  will cause the potential, or node voltage V 3 , at the signal input node  322  to increase which in turn increases the voltage on gate  348 B of transistor Q 6 . An increasing gate voltage on transistor Q 6  will further turn on transistor Q 6  such that transistor Q 6  conducts more current through transistor Q 6  between drain region  346 B and source region  344 B. This increase in conduction through transistor Q 6  will tend to cause the current flowing out of the source region  307 B of transistor Q 2  to increase. The increased conduction through transistors Q 2  and Q 6  tend to pull signal output node  324 B to ground reducing the node voltage V 2  at signal output node  324 B. As the node voltage V 2  of signal output node  324 B is reduced, transistor Q 3  is further turned on. In this manner, the single ended receiver, or pseudo differential amplifier circuit  300  operates in a differential amplifier fashion. The single ended current signal which was input from transmission line  352  into signal input  322  is thus converted into a differential current signal in that the source current at source region  307 A of transistor Q 1  tends to decrease and the source current at source region  307 B of transistor Q 2  tends to increase. As a result, the pseudo differential amplifier of FIG. 9 produces the same effect that a fully differential signal would have on a conventional differential current sense amplifier. 
     Also, the pseudo differential amplifier avoids the necessity having two transmission lines as in a conventional differential current sense amplifier. The pseudo differential amplifier circuit  300  can latch a voltage output signal on the pair of signal output nodes,  324 A and  324 B, and the pair of output transmission lines  354 A and  354 B when a single sided current signal of 2.0 mA or less is received at the single signal input node  322 . The pseudo differential amplifier circuit  300  can latch this voltage output signal to the pair of signal output nodes,  324 A and  324 B in less than 300 nanoseconds (ns). This is a very rapid response time and is on a par with that provided by conventional differential current sense amplifiers. Further, the pseudo differential amplifier circuit described here is fully capable of fabrication in a streamlined CMOS process. 
     FIG. 10 is a schematic diagram illustrating another pseudo differential current sense amplifier circuit, or single ended amplifier  400 . The amplifier  400  is coupled to transmission line  452 . A plurality of interconnection (transmission) lines  376 A are provided along the transmission line  452 . A plurality of capacitive elements  378 A are connected at spaced intervals along the transmission line  452  to vary clock signal delay times as described above with reference to FIG.  7 . 
     The pseudo differential amplifier circuit  400  of FIG. 10 is useful in amplifier roles which do not require a latching action. FIG. 10 illustrates a pair of cross coupled amplifiers, B 1  and B 2 . Each amplifier, B 1  and B 2 , includes a first transistor, Z 1  and Z 2 , respectively, of a first conductivity type. Each first transistor Z 1  and Z 2  includes a source region,  407 A and  407 B, respectively, a drain region,  408 A and  408 B, and a gate,  409 A and  409 B, opposing a body region  410 A and  410 B. Each amplifier, B 1  and B 2 , includes a load resistor Z 3  and Z 4 . Each load resistor Z 3  and Z 4  is coupled to the drain region for each one of the first transistors Z 1  and Z 2  respectively in the pair of cross coupled amplifiers B 1  and B 2 . In one embodiment, each first transistor, Z 1  and Z 2 , of a first conductivity type includes a pair of metal oxide semiconductor field effect transistors (MOSFET). Alternatively, each first transistor, Z 1  and Z 2 , of the first conductivity type includes an n-channel metal-oxide semiconductor (NMOS) transistor. 
     In FIG. 10, a single signal input node  422  is coupled to the source region,  407 A or  407 B of one of the first transistors, Z 1  and Z 2 , in the pair of cross coupled amplifiers A 1  and A 2 . By way of illustration, FIG. 10 shows the single signal input node  422  coupled to the source region  407 A of transistor Z 1 . A signal output node  424 A and  424 B in each amplifier in the pair of cross coupled amplifiers B 1  and B 2  is coupled to the drain regions  408 A and  408 B of the first transistors Z 1  and Z 2  as well as to the load resistors Z 3  and Z 4 . The signal output nodes  424 A and  424 B in each one of the cross coupled amplifiers B 1  and B 2  is further coupled to the gate of the first transistor in the other amplifier. Hence, signal output node  424 A is coupled to gate  409 B of amplifier B 2 , and signal output node  424 B is coupled to gate  409 A of amplifier B 1 . In one embodiment, the signal output nodes  424 A and  424 B are coupled respectively to a pair of output transmission lines  454 A and  454 B. The single signal input node  422  is additionally coupled to a current mirror X 1 . In one embodiment, the transmission line  452  which has a characteristic impedance (Zo) of less than 50 Ohms is coupled to the signal input node  422 . 
     In FIG. 10, a second transistor, Z 5  and Z 6  respectively, of a first conductivity type is coupled to each amplifier, B 1  and B 2 . Each second transistor Z 5  and Z 6  includes a source region,  444 A and  444 B respectively, a drain region,  446 A and  446 B, and a gate,  448 A and  448 B, opposing a body region  450 A and  450 B. The drain region  446 A and  446 B for each second transistor, Z 5  and Z 6 , is coupled to the source region,  407 A and  407 B, for each first transistor Z 1  and Z 2  in the pair of cross coupled amplifiers A 1  and A 2 . The single signal input node  422  additionally couples to the gate,  448 A and  448 B, for each second transistor Z 5  and Z 6 . Alternatively, each second transistor, Z 5  and Z 6 , of a first conductivity type comprise a second pair of MOSFETs of a first conductivity type for the pseudo differential amplifier circuit  400 . In this embodiment, the second pair of MOSFETs of a first conductivity type includes a pair of NMOS transistors Z 5  and Z 6 . Also in this embodiment, the pair of NMOS transistors Z 5  and Z 6  are part of the current mirror X 1 . Here, a drain region,  446 A and  446 B, for each one of the pair of NMOS transistors Z 5  and Z 6  in the current mirror X 1  is coupled to a source region,  407 A and  407 B respectively, for each NMOS transistor Z 1  and Z 2  in the pair of cross coupled amplifiers B 1  and B 2 . The single signal input node  422  is coupled to a gate on each one of the pair of NMOS transistors Z 5  and Z 6  in the current mirror X 1 . 
     The operation of the pseudo differential amplifier circuit  400  in FIG. 10 is analogous to the operation of the pseudo differential amplifier circuit  300  in FIG.  9 . The pseudo differential amplifier circuit  400  conserves chip surface area by facilitating differential sensing capability using a single ended receiver. In the pseudo differential amplifier circuit  400  shown in FIG. 10 the amplifier action of the upper transistors Q 3  and Q 4  shown in FIG. 9 have been replaced by load resistors Z 3  and Z 4 . The use of load resistors Z 3  and Z 4  rather than active transistors Q 3  and Q 4  as load devices results in a lower gain, slower response and more input current being required to achieve latching action if such is desired. Nonetheless, the pseudo differential amplifier circuit  400  is very well suited to and responsive in an amplifying signal detection role. The pseudo differential amplifier circuit  400  can provide a differential voltage signal to the pair of signal output nodes  424 A and  424 B and the pair of output transmission lines  454 A and  454 B when a single ended input current of less than 1.0 mA is received at the single signal input node  422 . The pseudo differential amplifier circuit  400  can provide the differential voltage signal to the pair of signal output nodes in less than 300 nanoseconds (ns). This is a very rapid response time and is on par with that provided by conventional differential current sense amplifiers. The pseudo differential amplifier circuit  400  is fully capable of fabrication in a streamlined CMOS process. Further, since the pseudo differential amplifier circuit  400  operates with only a single signal input node and single input transmission line, precious chip surface area is conserved. 
     With reference to FIGS. 11A and 11B, there is shown a current sense amplifier (or current comparator)  800  with hysteresis fabricated according to CMOS process technology. The amplifier  800  is coupled to a transmission line  852 . A plurality of interconnection (transmission) lines  876  are provided along the transmission line  852 . A plurality of capacitive elements  878  are connected at spaced intervals along the transmission line  852  to vary clock signal delay times as described above with reference to FIG.  7 . 
     The introduction of hysteresis into the current sense amplifiers and/or receivers will allow them to discriminate against noise transients since the output will not change states unless the signal becomes more positive than a high trip point, or more negative than a low trip point. 
     The current sense amplifier  800  includes a first amplifier  810 , and a second amplifier  820 . Each amplifier,  810  and  820 , includes a first transistor of a first conductivity type, M 1  and M 2  respectively. Each amplifier,  810  and  820 , includes a second transistor of a second conductivity type, M 3  and M 4  respectively. The first transistor of a first conductivity type, M 1  and M 2 , includes an n-channel metal oxide semiconductor (NMOS) transistor, M 1  and M 2 . In this embodiment, the second transistor of a second conductivity type, M 3  and M 4 , includes a p-channel metal oxide semiconductor (PMOS) transistor, M 3  and M 4 . Transistors M 1  and M 2  are driven by a gate potential at node  7 . Each amplifier,  810  and  820 , includes a current sink, shown in FIG. 11A as transistors M 5  and M 6  which are driven by a gate potential at node  6 . The first and second transistors, M 1  and M 3 , of the first amplifier  810  are coupled at a drain region,  821  and  822  respectively, to node  1 . 
     Node  1  couples the drain region,  821  and  822 , for the first and the second transistor, M 1  and M 3 , in the first amplifier  810  to gates,  840  and  841 , of the second transistor, M 3  and M 4 , in the first and the second amplifier  810  and  820 . The first and second transistors, M 2  and M 4 , of the second amplifier  820  are coupled at a drain region,  823  and  824  respectively. In the embodiment shown in FIG. 11A, a signal output node  2  is coupled to the drain region,  823  and  824 , of the first and the second transistor, M 2  and M 4 , in the second amplifier  820 . In an alternative embodiment, the signal output node  2  can be coupled to the drain region,  821  and  822 , of the first and the second transistor, M 1  and M 3 , in the first amplifier  810 . As shown in FIG. 11A the signal output node is further coupled to a gate  880  of a third transistor M 8 . In one embodiment, the third transistor M 8  is an n-channel metal oxide semiconductor (NMOS) transistor M 8 . Each amplifier,  810  and  820 , includes a signal input node,  5  and  4  respectively, which is coupled to a source region,  825  and  826 , of the first transistor, M 1  and M 2 . 
     A source region,  827  and  828 , for the second transistor, M 3  and M 4  respectively, in the first and second amplifier,  810  and  820 , is coupled to a voltage supply Vdd at node  3 . In one embodiment, a drain region  836  of the third transistor M 8  is coupled to a source region  828  of the second transistor M 4  in the second amplifier  820 . In this embodiment, a source region  837  of the third transistor M 8  is coupled to the signal input node  4  of the second amplifier  820 . The signal input node  5  of the first amplifier  810  receives an input current, I 1 , and the signal input node  4  of the second amplifier  820  receives a reference current, I 2 . 
     FIG. 11B is an I-V graph illustrating the operation of the current sense amplifier circuit  800  shown in FIG.  11 A. The operation of the current sense amplifier circuit  800  is explained by reference to FIGS. 11A and 11B. The third transistor M 8  introduces a controlled hysteresis into the current sense amplifier  800  of FIG.  11 A. Beginning at the left hand side of the graph, FIG. 11B illustrates the output voltage, V 2 , at a high state output voltage. The high state output voltage, V 2 , turns on third transistor M 8  which then drives an input current, IM 8 , into node  4 . In other words, the third transistor M 8  provides an input current, IM 8 , into node  4  which acts in conjunction with the reference current I 2 . The single ended input current, I 1 , must overcome this combination of the reference, or differential current, I 2 , and the input current, IM 8 , before the output voltage, V 2 , can change states. At this point, the switching action of the output voltage, V 2 , of the current sense amplifier  800  is given by V 2 =−Zv(I 1 −(I 2 +IM 8 )). The value of (I 1 −(I 2 +IM 8 )) must become non zero or positive for the output to switch, or go to the second state, e.g. low state. Due to the input current IM 8 , I 1  will not “trip” the state of the current sense amplifier  800  until I 1  exceeds a certain positive current value, i.e. a high trip point, shown at  850  in FIG.  11 B. The size and doping levels of the third transistor M 8  can be varied to provide a set magnitude of input current, IM 8 , into node  4 . In this manner, the circuit design of the current sense amplifier  800  can be manipulated to introduce a range of hysteresis for positive input current, I 1 , values into the current sense amplifier  800 . The set hysteresis introduced, by the addition of the third transistor M 8 , allows the current sense amplifier  800  to discriminate against small transient noise values which would otherwise cause the current sense amplifier to switch states prematurely and provide an inaccurate output voltage, V 2 . 
     In reverse operation, the single ended input current, I 1 , is decreased from a higher positive value, e.g. above trip point value  850 . As shown in FIG. 11B, while the input current, I 1 , is above trip point  850  the output voltage, V 2 , will be at a low state output voltage. In this low state, the voltage potential applied to gate  880  of the third transistor M 8  will not turn “on” transistor M 8 . Thus, the third transistor M 8  is effectively removed from the current sense amplifier circuit  800 . In the embodiment of FIGS. 11A and 11B, node  4  will only see a reference current, I 2 , here held at zero amperes. In other words, the third transistor is not providing any input current, IM 8 , into node  4 . In reverse operation, the single ended input current, I 1 , must again upset the balance of the current sense amplifier  800 , but in the opposite direction, e.g. the input current, I 1 , must overcome the reference or differential current,  12 , of zero amperes before the output voltage, V 2 , will again change states. At this point, the output voltage, V 2 , of the current sense amplifier  800  is given by V 2 =−Zv(II−I 2 ). In this reverse direction, (I 1 −I 2 ) must become negative for the output voltage, V 2 , to switch back, or return to the high state output voltage. I 1  will not “trip” the state of the current sense amplifier  800  until I 1  passes below a second current value, i.e. a low trip point, shown at  860  in FIG.  11 B. In the embodiment shown in FIGS. 11A and 11B, the output voltage, V 2 , will not change states until I 1  has reached zero. Other high and low trip points can be achieved by varying the amount of hysteresis introduced by the third transistor M 8  and/or by varying the differential/reference signal  12  of the current sense amplifier  800 . 
     Although the present invention has been described with reference to preferred embodiments, it is to be understood that modifications and variations may be made without departing from the spirit and scope of this invention, as those skilled in the art will readily understand. All such modifications and variations are considered to be part of the invention. Accordingly, the invention is not limited by the foregoing description, but is only limited by the scope of the appended claims.