Abstract:
The invention provides an interposer substrate and a method of fabricating the same. The method includes: etching a carrier to form a recessed groove thereon; filling a dielectric material in the recessed groove to form a first dielectric material layer, or forming a patterned first dielectric material layer on the carrier; forming a first wiring layer, a first conductive block and a second dielectric material layer on the carrier and the first dielectric material layer sequentially, with the first wiring layer and the first conductive block embedded in the second dielectric material layer; and forming a second wiring layer and a second conductive block on the second dielectric material layer. A coreless interposer substrate having fine pitches is thus fabricated.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to interposer substrates, and, more particularly, to an interposer substrate and a method of fabricating the interposer substrate. 
         [0003]    2. Description of Related Art 
         [0004]    With the development in miniaturization for semiconductor packages, a typical printed circuit board (PCB) has smaller surface available to accommodate semiconductor packages. Therefore, a Package on Package (PoP) is developed having multiple packaging structures, each being stacked on top of the other in order to meet the high density requirement. 
         [0005]    Traditional stacked packages are formed by stacking a semiconductor package via a plurality of solder balls such that it is electrically connected to another semiconductor package. However due to the limitation of the fabricating process, a certain size and distance must remain for the solder balls, as a result, the electrical external connection points would be reduced as only a limited area of the package is available, which leads to an increase in thickness of the overall package structure. 
         [0006]    Referring to  FIG. 1 , in order to increase I/O number and meet the low-profile and compact-size requirements for the stacked package structures, an interposer substrate  10  is provided between a first semiconductor package  1 A and a second semiconductor package  1 B, and a first wiring layer  11  and a second wiring layer  12  are formed on the first surface and second surface of the interposer  10 , respectively. The interposer substrate  10  has conductive vias  13  for electrically connecting the first wiring layer  11  with the second wiring layer  12 . 
         [0007]      FIGS. 2A-2F  illustrate a method of fabricating an interposer substrate. 
         [0008]    As shown in  FIG. 2A , a core board  20  is provided. The core board  20  has a first surface  20   a  and an opposing second surface  20   b . A plurality of vias  20   c  are formed on the core board  20  and penetrate the first and second surfaces  20   a  and  20   b . A metal layer  21  is plated on the first surface  20   a , the second surface  20   b  and the vias  20   c  of the core board  20 . 
         [0009]    As shown in  FIG. 2B , the metal layer  21  on the first surface  20   a  and second surface  20   b  are patterned to form the first wiring layer  21   a  and second wiring layer  21   b  that are electrically connected through the metal layer in the vias (i.e., the conductive vias  21   c ). An insulating layer (a solder mask layer)  22  is formed on the first wiring layer  21   a  and the second wiring layer  21   b , and a plurality of openings are formed on the insulating layer to expose a portion of the first wiring layer  21   a  and the second wiring layer  21   b.    
         [0010]    As shown in  FIG. 2C , a conductive layer  23  and a resist layer  24  are formed on the insulating layer  22  of the first surface  20   a  and the second surface  20   b  of the core board  20 . 
         [0011]    As shown in  FIG. 2D , the resist layer  24  is patterned to form a plurality of openings to expose a portion of the second wiring layer  21   b . An electroplating process is performed to form in the openings of the resist layer  24  a conductive material that is electrically connected with the second wiring layer  21   b.    
         [0012]    As shown in  FIG. 2E , the resist layer  24  and the conductive layer  23  covered by the resist layer  24  are removed to form an interposer substrate. 
         [0013]    However, the method is complex and the cost thereof is high. The additionally disposed conductive layer is likely to deteriorate the electrical performance of the interposer substrate. In addition, the thickness of the interposer substrate is also limited, such that when the thickness is smaller (such as under 130 μm), it is difficult to be fabricated and damages could easily occur. Further the design of the wiring would be limited by, the line width/line space (L/S). The yield may be influenced when L/S is lower than 25/25 μm. 
         [0014]    Hence, there is an urgent need to solve the foregoing problems encountered in the prior art. 
       SUMMARY OF THE INVENTION 
       [0015]    In view of the foregoing drawbacks, the present invention provides a method of fabricating an interposer substrate, comprising: forming a plurality of recessed grooves on a carrier, and forming a first dielectric material layer in the recessed grooves; forming a first wiring layer on the carrier and the first dielectric material layer; forming a plurality of first conductive blocks on the first wiring layer; covering the first wiring layer and the first conductive blocks with a second dielectric material layer, with terminal portions of the first conductive blocks exposed from the second dielectric material layer; forming on the second dielectric material layer a second wiring layer that is electrically connected with the first conductive blocks; forming second conductive blocks on the second wiring layer; and removing the carrier. 
         [0016]    The present invention provides an interposer substrate, comprising: a second dielectric material layer having opposing first and second surfaces; a first wiring layer embedded in the second dielectric material layer and having a first surface flush with the first surface of the second dielectric material layer and a second surface opposing to the first surface of the first wiring layer; a first dielectric material layer formed on the first surface of the second dielectric material layer and having a plurality of openings, from which a portion of the first wiring layer is exposed; a plurality of first conductive blocks embedded in the second dielectric material layer and having first terminal surfaces connected to the second surface of the first wiring layer and second terminal surfaces opposing to the first terminal surfaces and flush with the second surface of the dielectric material layer; a second wiring layer formed on the second surface of the second dielectric material layer and having a first surface connected to the second terminal surfaces of the first conductive blocks and a second surface opposing to the first surface of the second wiring layer; and a plurality of second conductive blocks formed on the second surface of the second wiring layer. 
         [0017]    The present invention provides a method of fabricating an interposer substrate, comprising: forming on a carrier a first dielectric material layer that has a plurality of openings, from which the carrier is exposed; forming a first wiring layer on the carrier and the first dielectric material, with a first portion of the first wiring layer formed in the openings of the first dielectric material layer and a second portion the first wiring layer formed on the first dielectric material layer; forming a plurality of first conductive blocks on the first wiring layer; covering the first dielectric material layer, the first wiring layer and the first conductive blocks with a second dielectric material layer, with terminal portions of the first conductive blocks exposed from the second dielectric material layer; forming on the second dielectric material layer a second wiring layer that is electrically connected with the first conductive blocks; forming a plurality of second conductive blocks on the second wiring layer; and removing the carrier. 
         [0018]    The present invention provides an interposer substrate, comprising: a first dielectric material layer having opposing first and second surfaces and a plurality of openings penetrating the first and second surfaces; a first wiring layer having a first portion formed on the second surface of the first dielectric material layer and a second portion formed in the openings of the first dielectric material layer and exposed from the first surface of the first dielectric material layer; a plurality of first conductive blocks formed on the first wiring layer; a second dielectric material layer covering the second surface of the first dielectric material layer and the first wiring layer and encapsulating the first conductive blocks, with terminal portions of the first conductive blocks exposed from the second dielectric material layer; a second wiring layer formed on the second dielectric material layer and electrically connected with the first conductive blocks; and a plurality of second conductive blocks formed on the second wiring layer. 
         [0019]    In summary, the present invention provides an interposer substrate and a method of fabricating the same, which are characterized by forming recessed grooves on a carrier by an etching method, with a first dielectric material layer formed in the recessed grooves, forming a patterned first dielectric material layer on the carrier, forming a first wiring layer, first conductive blocks, and a second dielectric material layer on the carrier and the first dielectric material layer, with the first wiring layer and first conductive blocks embedded in the second dielectric material layer, and forming second wiring layer and second conductive blocks on the second dielectric material layer, to form a coreless interposer substrate having and fine pitches, so as to meet the low-profile and compact-size requirements. In addition, the present invention also solves the problem that the design limitation due to line width/line space (L/S) in prior art. Besides only a portion of the first wiring layer is exposed, for mounting and electrically connecting the external electronic elements, without a need of disposing an insulating layer (solder mask layer), as well as any additional conductive layer, as a result the fabricating process is simplified and the cost is reduced. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0020]    The present invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein: 
           [0021]      FIG. 1  is a schematic cross-sectional view showing a conventional stacked package structure; 
           [0022]      FIGS. 2A-2E  are schematic cross-sectional views showing a conventional interposer substrate; 
           [0023]      FIGS. 3A-3K  are schematic cross-sectional views showing an interposer substrate in accordance with a first embodiment of the present invention; 
           [0024]      FIGS. 4A and 4B  are schematic cross-sectional views showing an interposer substrate in accordance with a second embodiment of the present invention; 
           [0025]      FIGS. 5A-5I  are schematic cross-sectional views showing an interposer substrate in accordance with a third embodiment of the present invention; and 
           [0026]      FIGS. 6A and 6B  are schematic cross-sectional views showing an interposer substrate in accordance with a fourth embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0027]    The present invention is described in the following with specific embodiments, so that one skilled in the pertinent art can easily understand other advantages and effects of the present invention from the disclosure of the present invention. 
         [0028]    It should be noted that all the drawings are not intended to limit the present invention. Various modification and variations can be made without departing from the spirit of the present invention. Further, terms, such as “on”, “first”, “second” and “top”, “bottom” and etc., are merely for illustrative purpose and should not be construed to limit the scope of the present invention. 
         [0029]      FIGS. 3A-3K  are schematic cross-sectional views of an interposer substrate according to a first embodiment of the present invention. 
         [0030]    As shown in  FIG. 3A , a carrier  30  and a first resist layer  31  covering the carrier  30  are provided. A pattering process is performed on the first resist layer  31   a  to forming a plurality of openings for exposing the carrier  30 . The carrier  30  is, but not limited to, a substrate such as a copper foil substrate. 
         [0031]    As shown in  FIG. 3B , an etching method is performed to remove a portion of the carrier  30  covered by the first resist layer  31   a , to form a plurality of recessed grooves  300  on the carrier  30 . 
         [0032]    As shown in  FIG. 3C , the first resist layer  31   a  is removed and the recessed grooves  300  are filled with a dielectric material, so as to form a first dielectric material layer  32   a . The first dielectric material layer can be formed in the recessed grooves  300  via a molding, a coating, or a lamination method. The dielectric material can be epoxy resin for instance. 
         [0033]    As shown in  FIG. 3D , a patterned second resist layer  31   b  is formed on the carrier  30  and the first dielectric material layer  32   a , and the second resist layer  31   b  has a plurality of openings to expose the first dielectric material layer  32   a  and a portion of the carrier  30 . Subsequently, a first wiring layer  33   a  is formed in the openings of the second resist layer  31   b.    
         [0034]    As shown in  FIG. 3E , a third resist layer  31   c  is formed and covers the first wiring layer  33   a  and the second resist layer  31   b , and is patterned to form a plurality of openings on the third resist layer  31   c  to expose a portion of the first wiring layer  33   a . Subsequently, a plurality of first conductive blocks  34   a  are formed in the openings of the third resist layer  31   c.    
         [0035]    As shown in  FIG. 3F , the second resist layer  31   b  and the third resist layer  31   c  are removed to expose the first wiring layer  33   a  and the first conductive blocks  34   a.    
         [0036]    As shown in  FIG. 3G , the first dielectric material layer  32   a , the first wiring layer  33   a  and the first conductive blocks  34   a  are covered with a second dielectric material layer  32   b , such that the terminal portions of the first conductive blocks  34   a  are exposed from the second dielectric material layer  32   b.    
         [0037]    As shown in  FIG. 3H , the second dielectric material layer  32   b  is covered with a fourth resist layer  31   d , and the fourth resist layer  31   d  is patterned to form a plurality of openings for exposing the first conductive blocks  34   a  and a portion of the second dielectric material layer  32   b . A second wiring layer  33   b  is formed in the openings of the fourth resist layer  31   d . The second wiring layer  33   b  is electrically connected with the first wiring layer  33   a  via the first conductive blocks  34   a.    
         [0038]    As shown in  FIG. 3I , the fourth resist layer  31   d  and the second wiring layer  33   b  are covered with a fifth resist layer  31   e , and the fifth resist layer  31   e  is patterned to form a plurality of openings for exposing a portion of the second wiring layer  33   b . Second conductive blocks  34   b  are formed in the openings of the fifth resist layer  31   e  and electrically connected with the second wiring layer  33   b.    
         [0039]    As shown in  FIG. 3J , the fifth resist layer  31   e  and the fourth resist layer  31   d  are removed, for exposing the second wiring layer  33   b  and the second conductive blocks  34   b.    
         [0040]    As shown in  FIG. 3K , the carrier  30  is removed, to expose a portion of the first wiring layer  33   a , so as to complete the fabrication of the interposer substrate according to the present invention. In addition, it is also applicable to etch away the central portion of the carrier, to form a frame-type carrier on the retained first dielectric material layer, to function as a supporting means for the interposer substrate. 
         [0041]    Referring to  FIG. 3K , the interposer substrate according to the present invention comprises: a first dielectric material layer  32   a , a second dielectric material layer  32   b , a first wiring layer  33   a , a second wiring layer  33   b , first conductive blocks  34   a , and second conductive blocks  34   b.    
         [0042]    The second dielectric material layer  32   b  has a first surface  321   b  and an opposing second surface  322   b.    
         [0043]    The first wiring layer  33   a  has a first surface  331   a  and an opposing second surface  332   a.    
         [0044]    The first wiring layer  33   a  is embedded in the second dielectric material layer  32   b , and the first surface  331   a  of the first wiring layer  33   a  is flush with the first surface  321   b  of the second dielectric material layer  32   b.    
         [0045]    The first dielectric material layer  32   a  is formed on the first surface  321   b  of the second dielectric material layer  32   b , and the first dielectric material layer  32   a  has a plurality of openings to expose a portion of the first wiring layer  33   a . The partly exposed first wiring layer  33   a , such as bonding pads served as an electrical connecting means for electrically connecting external electronic elements (such as semiconductor packages) with the bonding pads via conductive elements such as solder balls. Each of the first conductive blocks  34   a  has an opposing first terminal portion  341   a  coupled to the second surface  332   a  of the first wiring layer  33   a , and an opposing second terminal portion  342   a  flush with the second surface  322   b  of the second dielectric material layer  32   b.    
         [0046]    The second wiring layer  33   b  has a first surface  331   b  and an opposing second surface  332   b . The second wiring layer  33   b  is formed on the second surface  322   b  of the second dielectric material layer  32   b , and a portion of the first surface  331   b  of the second wiring layer  33   b  is coupled to the second terminal portion  342   a  of the first conductive blocks  34   a.    
         [0047]    The second conductive blocks  34   b  are formed on the second surface  332   b  of the second wiring layer  33   b.    
         [0048]      FIGS. 4A-4B  are schematic cross-sectional views showing a method of fabricating the interposer substrate in accordance with a second embodiment of the present invention. 
         [0049]    As shown in  FIG. 4A , after the fifth resist layer and the fourth resist layer are removed to expose the second wiring layer  33   b  and second conductive blocks  34   b  corresponding in  FIG. 3J , an insulative protection layer  35  is formed to cover the second dielectric material layer  32   b , the second wiring layer  33   b  and the second conductive blocks  34   b.    
         [0050]    As shown in  FIG. 4B , a portion of the insulative protection layer  35  is removed to expose the second conductive blocks  34   b , and the carrier  30  is removed to expose the first dielectric material layer  32   a  and a portion of the first wiring layer  33   a.    
         [0051]      FIGS. 5A-5I  are schematic cross-sectional views showing an interposer substrate in accordance with a third embodiment of the present invention. 
         [0052]    As shown in  FIG. 5A , a carrier  50  is provided with a patterned first dielectric material layer  52   a  formed on the surface of the carrier  50 , and a plurality of openings are formed on the first dielectric material layer  52   a  to expose a portion of the carrier  50 . 
         [0053]    As shown in  FIG. 5B , a patterned first resist layer  51   a  is formed on the carrier  50  and the first dielectric material layer  52   a , and a plurality of openings are formed on the patterned first resist layer  51   a  to expose a portion of the carrier  50  and a portion of the first dielectric material layer  52   a . A first wiring layer  53   a  is formed in the openings of the first resist layer  51   a . The openings for exposing the first resist layer correspond in position to the openings of the first dielectric material layer  52   a.    
         [0054]    As shown in  FIG. 5C , a patterned second resist layer  51   b  is formed on the first resist layer  51   a  and the first wiring layer  53   a , and has a plurality of openings for exposing a portion of the first wiring layer  53   a . First conductive blocks  54   a  are formed in the openings of the second resist layer  51 , and electrically connected with the first wiring layer  53   a . The openings of the second resist layer correspond in position to the openings of the first resist layer  51   a.    
         [0055]    As shown in  FIG. 5D , the second resist layer  51   b  and the first resist layer  51   a  are removed to expose the first dielectric material layer  52   a , the first wiring layer  53   a , and the first conductive blocks  54   a.    
         [0056]    As shown in  FIG. 5E , the first dielectric material layer  52   a , the first wiring layer  53   a , and the first conductive blocks  54   a  are covered with a second dielectric material layer  52   b , with the terminal portions of the first conductive blocks  54   a  exposed from the second dielectric material layer  52   b.    
         [0057]    As shown in  FIG. 5F , a patterned third resist layer  51   c  is formed on the second dielectric material layer  52   b , and has openings for exposing the first conductive blocks  54   a  and a portion of the second dielectric material layer  52   b . A second wiring layer  53   b  is formed in the openings of the third resist layer  51   c , and electrically connected with the first conductive blocks  54   a.    
         [0058]    As shown in  FIG. 5G , a patterned fourth resist layer  51   d  is formed on the third resist layer  51   c  and the second wiring layer  53   b , and has a plurality of openings to expose the second wiring layer  53   b . Second conductive blocks  54   b  are formed in the openings of the fourth resist layer  51   d , and electrically connected with the second wiring layer  53   b.    
         [0059]    As shown in  FIG. 5H , the fourth resist layer  51   d  and the third resist layer  51   c  are removed to expose the second wiring layer  53   b  and second conductive blocks  54   b.    
         [0060]    As shown in  FIG. 5I , the carrier  50  is removed to expose the first dielectric material layer  52   a  and a portion of the first wiring layer  53   a , so as to complete the fabrication of the interposer substrate according to the present invention. In addition, it is also applicable to etch away the central portion of the carrier, to form a frame-type carrier on the remaining first dielectric material layer, to function as a supporting means for the interposer substrate. 
         [0061]    Referring to  FIG. 5I , the interposer substrate according to the present invention comprises: a first dielectric material layer  52   a , a second dielectric material layer  52   b , a first wiring layer  53   a , a second wiring layer  53   b , first conductive blocks  54   a , and second conductive blocks  54   b.    
         [0062]    The first dielectric material layer  52   a  has a first surface  521   a  and an opposing second surface  522   a , and a plurality of openings penetrating the first surface  521   a  and the second surface  522   a.    
         [0063]    The first wiring layer  33   a  has a first surface  531   a  and an opposing second surface  532   a . A portion of the first wring layer  53   a  is formed on the second surface  522   a  of the first dielectric material layer  52   a , and a portion of the first surface  531   a  is formed in the openings of the first dielectric material layer  52   a  and is flush with the first surface  521   a  of the first dielectric material layer  52   a . The partly exposed first wiring layer  53   a , such as bonding pads served as an electrical connecting means for electrically connecting external electronic elements (such as semiconductor packages) with the bonding pads via conductive elements such as solder balls. 
         [0064]    The first conductive block  54   a  are formed on the second surface  532   a  of the first wiring layer  53   a  and electrically connected with the first wiring layer  53   a.    
         [0065]    The second dielectric material layer  52   b  covers the second surface  522   a  of the first dielectric material layer  52   a  and the second surface  532   a  of the first wiring layer  53   a  and encapsulates the first conductive bumps  54   a  in such a way that the terminal portions of the first conductive bumps  54   a  are exposed from the second dielectric material layer  52   b.    
         [0066]    The second wiring layer  353   b  is formed on the second dielectric material layer  52   b , and electrically connected with first conductive blocks  54   a.    
         [0067]    The second conductive blocks  54   b  are formed on the second wiring layer  53   b.    
         [0068]      FIGS. 6A-6B  are schematic cross-sectional views showing an interposer substrate in accordance with a fourth embodiment of the present invention. 
         [0069]    As shown in  FIG. 6A , the fourth resist layer and the third resist layer are removed, as did in  FIG. 5H , to expose the second wiring layer  54   b , and the carrier  50  is removed to expose the first dielectric material layer  52   a  and a portion of the first wiring layer  53   a.    
         [0070]    In summary, the present invention provides an interposer substrate and a method of fabricating the same, which are characterized by forming recessed grooves on a carrier by an etching method, with a first dielectric material layer formed in the recessed grooves, forming a patterned first dielectric material layer on the carrier, forming a first wiring layer, first conductive blocks, and a second dielectric material layer on the carrier and the first dielectric material layer, with the first wiring layer and first conductive blocks embedded in the second dielectric material layer, and forming a second wiring layer and second conductive blocks on the second dielectric material layer, to form a coreless interposer substrate having and fine pitches, so as to meet the low-profile and compact-size requirements. In addition, the present invention also solves the problem that the design limitation due to line width/line space (L/S) in prior art. Besides only a portion of the first wiring layer is exposed, for mounting and electrically connecting the external electronic elements, without a need of disposing an insulating layer (solder mask layer), as well as any additional conductive layer, as a result the fabricating process is simplified and the cost is reduced. 
         [0071]    The present invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the present invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.