Abstract:
A method for evaluating cross-talk of a circuit and signal degrading due to mutual electric coupling between wires of a circuit. The method includes: simulating the signal transmitting on wires of the circuit during the normal operation of the circuit, and implementing cross-talk analysis of the circuit to modify the analysis according to the signal variation during the practical operation of the circuit in order to evaluate the cross talk on each wire in the circuit.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]    The application claims the benefit of U.S. Provisional Application No. 60/380,929, filed May 17, 2002, and included herein by reference. 
     
    
     
       BACKGROUND OF INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention provides a method to evaluate a circuitry cross-talk during the practical operation of a circuit for the matching between the analysis result and the cross-talk on each wire in the circuit.  
           [0004]    2. Description of the Prior Art  
           [0005]    In the highly developed modern information society, an electric circuit used in signal processing and data calculation is the most vital fundamental part of information development. From portable cellular phones, personal digital assistants (PDA), to desktop computers, and network servers, different system demands for electric signal processing and information integration are fulfilled by complex electric circuits. The principal part of modern electric circuits is an integrated circuit manufactured in a wafer manufacturing process. An integrated circuit will be packaged in a chip to be applied in a semiconductor system.  
           [0006]    With the advancements of wafer manufacturing processing, circuit layout size of an electric circuit gradually scales down and components integration will increase such that the chip volume will be decreased to further fulfill the demands of a tiny circuit of modern information society. However, as circuit volume is getting much smaller, distance between each component and wires becomes much less, signals transmitted in wires will be interrupted each other because of mutual electric coupling effects, and communication quality will deteriorate. Signal interference between wires in a circuit because of mutual electric coupling effects is so-called “cross-talk” effect. To further explain the cause of cross-talk, please refer to FIG. 1. FIG. 1 is a schematic diagram of a conventional circuit  10 . In circuit  10 , circuit blocks  12 A,  12 B,  14 A,  14 B,  16 A,  16 B,  18 A, and  18 B are the construct components of circuit  10 ; each illustrated block represents a plurality of organized logic gates or transistors for performing specified function. Wires L 1  to L 4  in circuit  10  connect blocks  12 A to  12 B,  14 A to  14 B,  16 A to  16 B, and  18 A to  18 B, respectively with functions of transmitting electric signal between each electric circuit block.  
           [0007]    Since circuit  10  has dense component integration, distance between each wire will be very small, such as distance D 12  and D 23  illustrated in FIG. 1. In present 0.18 μm (micron) wafer manufacturing processing, distance between each wire could be less than 1 μm wherein mutual electric coupling effects between each wire will increase. Although in circuit  10  the wires L 1 , L 2 , L 3 , and L 3  are insulated from each other, between each wire, a capacitor will be formed in equivalent circuit, which makes wires couple mutually via this equivalent capacitor. As illustrated in FIG. 1, mutual electric coupling effects between L 1  and L 2  could be represented as an equivalent capacitor C 12 . Signals transmitted in L 1  and L 2  will interrupt each other via this equivalent capacitor C 12  because of cross-talk effect. The mutual electric coupling effects between L 2  and L 3  could also be represented as an equivalent capacitor C 23  and the mutual electric coupling effects between L 4  and L 1 , L 2 , and L 3  could be represented as a capacitor C 14 , C 24 , and C 34 , respectively. Among them, L 1  is much closer to L 2 , which means that D 12  is less than D 23 , and the parallel portion between L 1  and L 2  is longer, which means that D 0  is longer. This means that the mutual electric coupling effects between L 1  and L 2  is much larger than that between others.  
           [0008]    In order to further explain the effects of mutual electric coupling on a circuit, please refer to FIG. 2A and FIG. 1. FIG. 2A is a time sequence of signals transmitted in different wires. The horizontal axis represents time scale and the vertical axis represents signal potential scale. In an ideal situation, a good electric insulation exists between each wire in circuit  10  and signals transmitted in different wires will not interrupt each other. Wave patterns  20 A and  20 B illustrated in FIG. 2A represent digital signals transmitted in two different wires, such as L 1  and L 2  for example, in such an ideal situation. However, in reality, the mutual electric coupling effects between different wires will make signals of two wires interrupt each other and result in cross-talk. The wave pattern  20 C illustrated in FIG. 2A represents the real wave pattern of wave pattern  20 A, which is influenced by mutual electric coupling effects in circuit  10 . From time point t0 to t1, the wave pattern  20 A in the wire L 1  shall maintain at low potential, but the wave pattern  20 B in wire L 2  is at high potential in the same time span, which prevents the wave pattern  20 A from maintaining its low potential through the mutual electric coupling effects between wires and results in the wave pattern  20 C having a slightly increased potential. Similarly, in the period from time t1 to t2, the wave pattern of the signal transmitted in L 1  shall maintain its high potential such as  20 A, but low potential wave pattern  20 B in L 2  make the wave pattern of L 1  lower its potential through mutual electric coupling effects to become the wave pattern  20 C. When the ideal wave pattern  20 A in L 1  degrades to the wave pattern  20 B, noise margin of the signal in L 1  will decrease. As the wave pattern illustrated from time point t0 to t2 in FIG. 2A, there is a potential transition V 0  in the ideal wave pattern  20 A, but potential transition V 1  in the wave pattern  20 B is less than V 0 . If the potential transition V 1  is too small or noise is too large, it cannot be determined whether the digital signal is at its high level or low level. Besides, at time point t3, both the wave pattern of L 1  and L 2  increase to a high potential level, and the wave pattern in L 1  will exceed the normal potential level to a much higher level through the mutual electric coupling effects between wires, such as wave pattern  20 C, which may result in burning out of the wire L 1  for its forcing signal.  
           [0009]    Cross-talk effects influence not only signal potential mentioned above, but also time domain expression. Please refer to FIG. 2B. Illustrated in FIG. 2B are time sequence representing different locations in wire L 1  and L 2 . The horizontal axis represents time and the vertical axis represents signal potential. The electric block  12 A should transmit signals to the electric block  12 B through the wire L 1 , the electric block  14 B should transmit signals to the electric block  14 A through the wire L 2 , the wave pattern  26 A,  26 B, and  26 C represent the wave patterns having potential transitions in location  22 A,  22 B and  22 C of the wire L 2  and the wave pattern  28 A,  28 B, and  28 C represent the wave patterns having potential transitions in location  24 A,  24 B and  24 C of the wire L 2 . As illustrated in FIG. 2B, wave pattern  26 B has its rising edge at time point t5 and t6, but wave pattern  28 B has its falling edge at the same time points. The falling edge of the wave pattern  28 B will lower the rising velocity of the rising edge of the wave pattern  26 B through mutual electric coupling, which results in a longer time needed for the wave pattern  26 B to rise, and influences the potential transition speed of the wave pattern  26 C. In other words, unexpected delay will occur in signals transmitted in the wire L 1  for a rising edge and a falling edge occurring at the same time in different wires, and each electric block in circuit  10  will not operate concisely according to its default time domain.  
           [0010]    Please refer to FIG. 3. In order to decrease cross-talk effects in a circuit due to mutual electric coupling, cross-talk effects of a circuit shall be analyzed specifically during electric circuit design process. FIG. 3 is a schematic diagram of a prior art flow  100  for analyzing cross-talk effects during electric circuit design. The flow  100  is as follows:  
           [0011]    Step  102 : Circuit Functions Design. According to function demands, needed electric components, such as transistors, or logic gates will be assigned in this step. In other words, in this step transistors or logic gates will be chose to fulfill the demand for functions of a circuit. In FIG. 1, flow  100  will perform electric circuit design and cross-talk analysis for circuit  10 . Circuit  10  is provided with functions of receiving signal A and B in electric circuit blocks  12 A and  12 B, applying an “AND” operation on signal A and B, inverting the resulting signal and outputting it as signal C; receiving signal in electric circuit blocks  16 A and  16 B, buffering and outputting it as a signal G with highly driving capacity; and receiving signal H in electric circuit blocks  18   a  and  18 B, inverting the resulting signal and outputting it as signal  1 . Therefore, as illustrated in an attached graph in FIG. 3, components such as AND gate  30 A and inverter  30 B will be chosen to achieve the above-mentioned functions in this step.  
           [0012]    Step  104 : Circuit Layout Design. After determining the components assignment in circuit  10 , how to practice the circuit design determined in step  102  with circuit layouts in real wafer manufacturing processing will be considered in this step. To a person having ordinary skills in the art, in wafer manufacturing processing, a doped region (active region), oxide layer, field oxide layer, conductive layer, and polysilicon layer will be applied to layouts of transistors, logic gates, or other components. In this step, square measure of each transistor and logic gate in different layers, layout layer between each transistor and logic gate (use a conductive layer to practice the wire L 1  to L 3 , and another conductive layer to practice the wire L 4  for example) and the layout widen and length illustrated in the attached graph  34  in FIG. 3 will be determined practically, wherein the associated layouts of circuit blocks  12 A and  12 B is known by those skilled the art without need to be illustrated in the attached graph  34 . After circuit layout design, the occupied square measure of each circuit block in circuit  10  and the geometric structure of the wire L 1  to L 4  have been determined. In order to practice this step in operation, CAD software could be applied to achieve the function demand for automatic localization and APR, auto placement and routing.  
           [0013]    Step  106 : Parameters Determination. After circuit layout design in step  104 , mutual electric coupling parameters between each wire such as resistance distributed in the circuit and capacity of mutual coupling equivalent capacitor between wires will be calculated according to the layout geometric structure. In wafer manufacturing processing, a square measure unit of each conductive polysilicon, and conductive layer is provided with a certain distributed resistance. After determining the wire layout layer and geometric structure, distributed resistance of each wire could be calculated. Similarly, the equivalent capacitance of each wire is related to the geometric distance of each wire, which could be calculated in this step. In order to practice this step in operation, resistor and capacitor analysis software, such as STAR_RC, can be applied.  
           [0014]    Step  108 : Coupling Nets Determination. Parameters determined in step  106  would be applied to make up a coupling net, which is needed for cross-talk analysis. Parameters such as distributed resistance, and mutual coupling capacitance between each wire in circuit  10  shall be determined in order to consider cross-talk effects between wires. After step  106 , associated parameters could be determined. As illustrated in an attached graph  38  in FIG. 3, parameters about distributed resistance and mutual coupling equivalent capacitance of the wire L 1  to L 4  have been determined, and wires in the circuit  10  have been organized to make up a coupling net having resistors and inductors. After making up the coupling net, mutual electric coupling effects between each wire have to be further analyzed. During a practical operation, this step can be done in step  106  by applying software resistor and capacitor analysis software. Generally, after analysis in step  106  and  108  with the aid of resistor and capacitor analysis software, a plurality of wires with critical mutual electric coupling effects among wires in circuit  10  can be determined and listed. In a more complex circuit, such as one of an application chip, there may be thousands of inter-connected wires between each circuit block, resistor and capacitor analysis software can list a plurality of wires with most critical mutual electric coupling effects just as the circuit designer wishes; for example, the most critical one thousand wires.  
           [0015]    Step  110 : Cross-Talk Analysis, which could be called SI, signal integrity, analysis. Cross-talk effects between wires to signals transmitted in them can be determined according to the coupling net determined in step  108 . It prior art, it is the most pessimistic condition being taken into accounts in cross-talk analysis. As illustrated in FIG. 2B, it will be considered in conventional cross-talk analysis that two signals reverse transmitted at the same time in the wire L 1  and L 2  to compensate each other completely, which make the delay time of signal transmitted in the wire L 1  longest. Or as illustrated in FIG. 2A, which frequent transitions in both L 1  and L 2  results in the most critical interruption to signal transmitted in L 1 . Additionally, there is a potential transition from low to high just in both L 1  and L 2  such that the mutual coupling influence in the wire L 1  is so large so as to have a highest potential in L 1 . In other words, in a conventional pessimistic cross-talk analysis, each transmitted signal will be considered whether or not generate the most critical cross-talk influences. In a practical operation of this step, signal analysis application software, such as MDC_SI, can be applied. As mentioned in step  108 , after applying resistor and capacitor analysis software to list a plurality of wires having most critical mutual electric coupling effects, signal analysis application software can be applied to analyze influences of cross-talk of these plural wires. Usually, after analysis in this step, influences of cross-talk to each wire in circuit  10  can be listed for comparison so that the circuit designer is capable of telling which wires in circuit  10  are most intended to be influenced by cross-talk and what the influences are. The circuit designer can rearrange circuit layout according to the analytic result, and go back to step  104  to reduce cross-talk effects of such wires.  
           [0016]    Though it is a strictly conservative standard to analyze cross-talk effects of each wire in step  110 , to some of wires during a practical operation of circuit  10 , the pessimistic condition will not occur. For example, in step  110  the wire L 1  is analyzed to be easily influenced by cross-talk of L 2  such that a frequent potential transition occurs in L 2  to influence signal in L 1  by mutual electric coupling. However, during a practical operation of circuit  10 , there may be no frequent transition in L 2  because only signals with low frequency or direct current would be transmitted in L 2 . The transition frequency in unit time is much lower in L 2  than in L 1 . In such a condition, the rate in which L 2  happens to have mutual compensation or addition coupling in pessimistic condition is very low because frequency difference between the two wires is so large that it is not easy for appearance of transitions synchronization. Cross-talk effects of practical operation of circuit  10  are not as critical as the result analyzed in step  110 . It is the coupling net determined in step  108  being taken into accounts to do pessimistic analysis in step  110 . The coupling net having only parameters information about coupling capacitance and distributed resistance cannot represent how circuit  10  operates and what kinds of signals are transmitted in each wire. Therefore, in order to get the pessimistic condition that signals happen to compensate or add each other in each wire, an analytic result with stricter standard shall be considered.  
           [0017]    To each wire in circuit  10 , if during a practical operation of the circuit the analytic pessimistic condition is highly different to real conditions, a cross-talk analysis result will mislead the circuit designer such that the circuit designer could not modify the circuit design correctly. For example, if the cross-talk analysis in step  110  represents that the wire L 1  will be influenced seriously by cross-talk of the wire L 2 , the circuit designer has to return to step  104  from step  110  to redesign circuit layout of L 1 . However, during a practical operation of the circuit  10 , rate of occurrence of the most pessimistic condition that signals transmitted in L 1  and L 2  synchronized is very rare. In such condition, too serious cross-talk analysis causes an unnecessary layout redesign. Besides the unnecessary waste of time, in modern highly integrated electric circuit design, each element usually interrupts each other, which is called trade-off. Some elements might be compromised in order to redesign the circuit. For example, it may result in signal deterioration while increasing a wire length. Some compromises are unnecessary. Therefore, ignoring signals transmitted during a practical operation of a circuit and strictly analyzing the cross-talk in pessimistic condition may result in unnecessary waste and a compromising circuit design.  
         SUMMARY OF INVENTION  
         [0018]    It is therefore a primary objective of the claimed invention to provide a cross-talk analysis method considering a practical operation of a circuit to overcome the problems of the prior art.  
           [0019]    In the prior art, cross-talk analysis is evaluated in the most pessimistic condition, which does not consider the real situation of signals transmitted in each wire during a practical operation of a circuit, and may result in incorrect analytic results wasting time on circuit layout redesign.  
           [0020]    It is provided in the claimed invention a circuit function simulation process to analyze signals transmitted in each wire in operation to modify the most pessimistic analytic result. If the frequency with two transmitted signals both having potential transition in the same time span is high, the most pessimistic cross-talk analytic result will determine that there is a critical mutual electric coupling between these two wires, which means it is very possible to have cross-talk between these two wires in a practical operation of the circuit. Otherwise, that frequency of potential transition of these two wires is highly different means during a practical operation of the circuit, cross-talk will not influence these two wires much even if the most pessimistic analytic result determines that the cross-talk effects between these two wires are critical. The claimed invention takes use of a circuit function simulation result to reexamine the most pessimistic cross-talk analytic result to determine whether or not the most pessimistic condition occurs during a practical operation of a circuit. Without any possible appearance of the most pessimistic condition, there is no demand for circuit redesign, which makes the circuit designer concentrate on wires with high possibility to be influenced by cross-talk. In another preferred embodiment, the circuit functions simulation result could be applied for cross-talk analysis of the most pessimistic condition, which involves applying pessimistic cross-talk analysis to a wire with high frequency of potential transition or ignoring the analytic process to a wire without high frequency of potential transition in order to accelerate circuit design.  
           [0021]    These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings. 
       
    
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0022]    [0022]FIG. 1 is a schematic diagram of a conventional circuit.  
         [0023]    [0023]FIG. 2A and 2B are schematic diagrams illustrating cross-talk effects on signals transmitted in two wires.  
         [0024]    [0024]FIG. 3 is a flow chart of a conventional cross-talk analysis.  
         [0025]    [0025]FIG. 4 is a schematic diagram of a cross-talk analysis flowchart according to the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0026]    Please refer to FIG. 4. The flow chart illustrated in FIG. 4 is a present invention cross-talk analysis flow  200 . The following is as follows:  
         [0027]    Step  202 : Circuit Functions Design. Like step  102  illustrated in FIG. 3, components such as transistors and logic gates will be arranged in step  202  to achieve default circuit functions.  
         [0028]    Ste  204 : Circuit Layout Design. Like step  104  illustrated in step  104 , circuit wiring and layout of the circuit designed will be determined in step  202 . After step  204 , a geometric layout structure of wires of the circuit will be determined.  
         [0029]    Step  206 : Parameters Determination. Like step  106  illustrated in step  106 , after step  204 , equivalent mutual coupling capacitors and distributed resistors will be calculated according to parameters (such as resistance of each polysilicon layers and conductive layers) of the geometric layout structure and wafer manufacturing processing  
         [0030]    Step  208 : Coupling Nets Determination. Like the relationship between step  106  and step  108 , after parameters determination in step  206 , the mutual electric coupling effects will be determined and listed according to the determined coupling net. Application software RC can be applied in step  206  and step  208  for determining a plurality of wires having most critical mutual electric coupling effects.  
         [0031]    Step  210 : Setup of Signals Monitoring. A difference between the present invention and the prior art is that the real condition of a circuit during a practical operation in cross-talk analysis is considered in the preset invention. In order to achieve the objective; a plurality of wires with most critical mutual electric coupling effects will be monitored for analyzing the real condition in operation. According to a plurality of wires with most critical mutual coupling effects determined in step  208 , the wires, which should be monitored in step  210 , could be determined.  
         [0032]    Step  212 : Circuit Functions Simulation. In this step, circuit functions during a practical operation will be simulated in cooperation with monitored wires set up in step  210  to monitor and analyze the real condition of signals transmitted in wires in operation. In a practical operation, circuit functions simulation application software can be applied in step  210  and step  212 . For example, in digital circuit design, simulation software called Verilog can be applied to simulate each input and output signal of logic gates in circuit operation, and a plug-in of Verilog can be applied in step  210  in cooperation with Verilog to point out the simulated results Verilog monitoring.  
         [0033]    Step  214 : Cross-Talk Analysis. In an embodiment of the present invention, cross-talk analysis of this step can apply the most pessimistic cross-talk analysis discussed in step  110  to list a plurality of wires with most critical mutual electric coupling effects, and analyze the influences of the wires in a most pessimistic condition. The present invention can further reexamine the most pessimistic or similar condition according to the signal transmitted simulation results in step  212 , and determine whether or not the most pessimistic condition will occur in a practical operation of a circuit. If the simulation results in step  212  determine that potential transitions occur frequently in a certain two wires during practical operation of a circuit or potential transitions occur synchronized in these two wires, signal transmitted conditions of these two wires is very similar to the most pessimistic condition and cross-talk effects analyzed in the most pessimistic cross-talk analysis would be very similar to what really happens during a practical operation of the circuit. Otherwise, if the simulated results in step  212  determine that the potential frequency of dynamic signals of some two wires is highly different during a practical operation of a circuit or it is not easy to have rising or falling edges synchronized, which is different to the most pessimistic condition, cross-talk effects between these two wires will not be critical. After reexamination of cross-talk analysis results determined in step  210  and step  212  in the present invention, the circuit designer could concentrate on wires with critical cross-talk effects in operation and not on wires without possibility. In another preferred embodiment, this step can perform pessimistic cross-talk analysis on wires having frequent potential transitions, which are determined in step  210  and step  212 . In other words, a plurality of wires with frequent potential transitions and a high possibility to have the most pessimistic conditions can be listed in step  210  and step  212  and analyzed for pessimistic cross-talk conditions in this step. No matter which embodiment mentioned above is used, the present invention aided by the simulated results determined in step  210  and step  212  can represent practical cross-talk effects. A circuit designer can go back to step  202  or step  204  according to these cross-talk analysis results to modify circuit design or layout.  
         [0034]    Besides step  202 ,  204 ,  206 ,  208 ,  210 ,  212 , and  214 , the present invention flow  200  can still apply some steps of the prior art flow  100  to do cross-talk analysis of step  216  after performing step  206 . The cross-talk analysis of step  216  is basically the same as that of step  110 . After step  216 , step  204  can be applied for circuit layout redesign. Since it is considered the practical operation condition of a circuit according to circuit functions in step  210 ,  212 , and  214  of the present invention, a circuit designer can go back to step  202  to redesign circuits in order to further design circuit in the components level, which makes it more flexible to design function and circuits to reduce cross-talk effects.  
         [0035]    In the prior art, the real signal transmitted condition during practical operation of a circuit will not be considered in analysis and evaluation of cross-talk. The most pessimistic cross-talk analysis of a circuit does not represent the real cross-talk effects in operation, and may result in unnecessary circuit redesign and time waste. On the contrary, he real signal transmitted conditions is being taken into consideration in the present invention, which makes a circuit designer concentrate on wires actually containing critical cross-talk effects during operation, which avoids unnecessary waste and performs better on design to modify circuit functions and layout at the same time.  
         [0036]    Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.