Abstract:
A memory controller includes an address decoder and a protocol controller, where the address decoder is arranged for decoding a received signal to generate a plurality of command signals, where the plurality of signals are for accessing a plurality of banks of the memory and the protocol controller is arranged for re-scheduling an executing order of the plurality of command signals according to opening banks and pages, and for accessing the memory according to the plurality of command signals.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a memory, and more particularly, to a Dynamic Random-Access Memory (DRAM) controller and an associated control method. 
         [0003]    2. Description of the Prior Art 
         [0004]    In Synchronous Dynamic Random-Access Memory (SDRAM), a read/write data procedure comprises the following actions: (1) if the non-active page of the corresponding bank is not set, an active command needs to be sent for opening the specific non-active page of the corresponding accessed bank; (2) if the active page of the corresponding bank is set, a read/write operation can be executed directly when there is a page hit; in the case of a page miss, a precharge command needs to be sent to close the current corresponding page, and then an active command must be sent to set the page which is going to be read/written, and a read/write command must be sent for performing data read/write; and (3) an auto-refresh/refresh command needs to be executed after a certain amount of time for maintaining the content data of the SDRAM. 
         [0005]    In the control operating procedure described above, the page status of the corresponding bank needs to be checked for each access, which comprises determining a non-active page, active page, page hit or page miss, and performing a corresponding operation according to the current status for correctly performing a read or write operation to the SDRAM. Because the operating procedure is a fixed and regular decision, a Finite State Machine (FSM) method is used to control the SDRAM. The efficiency of the FMS method is usually limited, however, so the frequency of an executing command cannot be elevated, which delays the executing period. This may degrade the read/write operation performance of the memory. 
         [0006]    To elevate the performance of an SDRAM, using an optimization discriminant procedure flow and changing the hardware design to a pipeline can optimize the SDRAM command operation, which further achieves an effective increase in the frequency of the memory. The disadvantage is that the control is complex, which increases design difficulty, and the design cost of hardware is thus increased. 
       SUMMARY OF THE INVENTION 
       [0007]    One of the objectives of the present invention is therefore to provide a controller of an SDRAM, and an associated method, which can simplify the control design of a memory and optimize the operating performance therein to solve the problems in the prior art. 
         [0008]    According to an embodiment of the present invention, a memory controller comprises an address decoder and a protocol control, wherein the address decoder is arranged to perform decoding on a receiving signal to generate a plurality of command signals, wherein the plurality of command signals comprise command signals accessing a plurality of banks of a memory; and the protocol controller is arranged to reschedule the executing sequence of the plurality command signals according to the opening bank and page in the memory to access the memory via the plurality of command signals. 
         [0009]    According to another embodiment of the present invention, a memory control method comprises: performing decoding on a receiving signal to generate a plurality of command signals, wherein the plurality of command signals comprise the command signals accessing a plurality of banks of a memory; and rescheduling the executing sequence of the plurality of command signals according to the opening banks and page in the memory to access the memory via the plurality of command signals. 
         [0010]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a diagram illustrating a memory controller according to an embodiment of the present invention. 
           [0012]      FIG. 2  is a flowchart illustrating a memory controller accessing a memory according to an embodiment of the present invention. 
           [0013]      FIG. 3  is a diagram illustrating a hardware architecture according to an embodiment of the present invention. 
           [0014]      FIG. 4  is a diagram illustrating an accessing command format. 
           [0015]      FIG. 5  is a timing diagram illustrating a page accessing different banks according to the prior art. 
           [0016]      FIG. 6  is a timing diagram illustrating a page accessing different banks according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0017]    Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should not be interpreted as a close-ended term such as “consist of”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. 
         [0018]      FIG. 1  is a diagram illustrating a memory controller  100  according to an embodiment of the present invention. As shown in  FIG. 1 , the memory controller  100  is coupled to the memory  108 , and connected to elements needed to access memory  108  such as the central processing unit  102 , the graphics processing unit  104 , and the High Definition Multimedia Interface (HDMI) element  106  via the bus  101 . The main function of the memory controller  100  is to control reading the data content of the memory  108  and writing data into the memory  108 , and to perform auto refresh for maintaining the data content of the memory  108 . For brevity,  FIG. 1  only depicts the address decoder  110  and the protocol controller  120 , but one skilled in the art should understand the memory controller  100  also comprises other necessary circuit elements. 
         [0019]    In this embodiment, the memory controller  100  is an SDRAM controller, and the memory  108  is an SDRAM. In various SDRAM specifications, e.g. JESD79F, JESD79-2C, JESD79-3D, read/write operations to the memory  108  which to be obeyed are all stipulated. For example: (1) for the page/row address of the read/write bank, if the active command is performed on a closed bank, the corresponding waiting time of the next command is as follows: (1.1) if the next command is an active command and for a different bank, the waiting time is tRRD; (1.2) if the next command is an active command and for the same bank, the waiting time is tRC; (1.3) if the next command is a precharge command, the waiting time is tRAS. (2) if the corresponding bank has opened the page, it needs to be confirmed if the page is the same; if not, then a precharge command needs to be executed to close the current page so the wanted page can be opened, and if the precharge command is executed, the next command needs to wait for the time tRP. (3) After opening the page of the corresponding page, the read/write command can be executed, and the next read/write command needs to wait for the time tCCD. More specifically, if a reading command is being executed then, when the next command is a writing command, the waiting time is tRTW, and when the next command is a precharge command, the waiting time is tRTP; if a writing command is being executed then, when the next command is a reading command, the waiting time is tWTR, and when the next command is a precharge command, the waiting time is tWR. (4) because the memory  108  needs to charge every row address for every tREFI in order to maintain the correctness of the content of the memory  108 , the auto-refresh/refresh needs to be executed in this time, and the next command needs to wait for the time tRFC; and before executing the auto-refresh/refresh command, a precharge all/precharge command needs to be executed first. 
         [0020]    According to the above mentioned operating commands, when executing different commands, a next command has a different time limit (waiting time), and in these different time limits, there is no connection between some commands. In addition, there is a plurality of banks in the memory  108 , wherein each bank may have a different page address (row address). During every read/write of data, it needs to be confirmed if the page of the corresponding bank is opened. 
         [0021]    Therefore, the present invention provides a method for accessing the memory  108  according to a command and the memory control characteristics so that the architecture can be a pipeline to process a plurality of command operations in parallel.  FIG. 2  is a flowchart illustrating a memory controller  100  accessing a memory  108  according to an embodiment of the present invention, wherein the flow is described as follows. 
         [0022]    In step  200 , the memory controller  100  receives a new accessing command for a read/write of at least a page of a bank of the memory  108 . In step  201 , the memory controller  100  inspects the status of the page, wherein if the page of the bank is not opened, the flow moves to step  203  to open the page; if the page of the bank is opened, the flow moves to step  204  to wait for the command to be executed in the command queue; if another page is opened in the bank and there is no command waiting or being executed, the flow enters step  202  to close the current page; and, if another page of the bank is opened and there is a command waiting or being executed, the flow enters step  204  for waiting in the command queue. 
         [0023]    In step  202 , after confirming the time limit is not met, the precharge command is executed for closing the opening page of the bank. The flow enters step  203 . 
         [0024]    In step  203 , after confirming the time limit is not met, the active command is executed for opening the page. The flow then enters step  204 . 
         [0025]    In step  204 , the command which enters the command queue follows the first in first out rule. When the next command waits at the output terminal to entering step  205  for executing the operation, it is determined if the page needs to be reopened. If the pages accessed by the next command and the executing command are located in different banks, the flow enters step  207  to reopen the page, i.e. executing the precharge operation and the active command. When the current command finishes executing, the flow enters step  205 ; and if the pages accessed by the next command and the current executing command are located in the same bank, the flow waits until the current command finishes then enters step  207  to reopen the page, i.e. executing the precharge operation and the activate command. The flow then enters step  205 . 
         [0026]    In step  205 , the current command is executed and if there is a command waiting to be executed in the command sequence of step  204 , the waiting command will be executed. Step  206  is then entered to end the flow. 
         [0027]    The memory  108  needs to maintain the correctness of the data, therefore, step  202  is triggered to close all banks or corresponding banks then the update command is executed in step  208 . 
         [0028]    According to the operating flow shown in  FIG. 2 , a pipeline may be applied to the hardware architecture. A further advantage is that the method can coordinate with associated hardware information so it is checked in each step whether memory command control can be emitted, and after an optimize order, the command which needs to be executed is selected. 
         [0029]      FIG. 3  is a diagram illustrating a hardware architecture according to an embodiment of the present invention, wherein the steps  302  to  307  shown in  FIG. 3  are implemented by the protocol controller  120  of the memory controller  100 . The element  308  may be a register which is arranged to store the opening bank and page. The SDRAM timer is arranged to determine when to trigger the auto-refresh/refresh command, the bank timer  310  is arranged to determine when to launch the precharge command, and the update controller  311  is arranged to determine, according to a timekeeping result of the SDRAM timer  309 , when to trigger the auto-refresh/refresh command. The elements  308 ,  309 ,  310 ,  311  are positioned within the memory controller  100 . 
         [0030]    In step  300 , a new accessing command is received, wherein the format of the accessing command may comprise read/write information  400 , burst length information  401 , address information  402  and bank conflict information  403  as shown in  FIG. 4 . 
         [0031]    In the page checking stage  301 , the opening bank and page recorded in the element  308  and the address information  402  in the accessing command need to be checked to determine whether the corresponding page (row address) conflicts. The flow then goes to the precharge stage  302 , opening stage  303  or the command queue  304  according to different statuses, and records whether to reopen the page (row address) into the bank conflict information  403  of the accessing command. 
         [0032]    In the precharge stage  302 , the opening stage  303  and the command queue  304 , the SDRAM timer  309  and the bank timer  310  need to be checked to determine whether to execute the step command to avoid violating the command time limit of the SDRAM. 
         [0033]    For the command queue stage  304 , in a hardware design, a register with a FIFO-like architecture is used to store command information. Due to the limit storing space in the command queue stage  304 , when the register has storing space, it is capable of receiving the commands sent by the previous step; if the number of commands waiting to be executed in the register reaches the maximum storing number, then the commands from the previous steps need to wait to be received. 
         [0034]    In the command queue stage  304 , the command at the output is defined to be the next command  313 ; if the next command  313  needs to reopen the page(row address), it checks with the command in the command executing stage  306  to see whether they are the same bank. If not, the flow goes to the reopening stage  305  to execute the operation of reopening a page in advance; when the page has finished opening, the next command  313  is sent from the command queue stage  304  and goes to the command executing stage  306 . In contrast, if the page which needs to be reopened in the next command  313  is in the same bank as the page accessed by the command in the command executing stage  306 , then the flow waits until the executing command in the command executing stage  306  is finished then performs a reopening operation to avoid affecting the command reading/writing address in the command executing stage. 
         [0035]    In the command queue stage  304 , it is determined whether to open the page, wherein once the auto-refresh/refresh command is executed, the precharge all/precharge command is executed first which may close all of the banks or some specific banks. If the page was closed before, the flow requests to open again in the command queue stage  304  then executes the read/write command one or more times consecutively according to the element  308  and the bank conflict information  403 . When the command is finished executing, the next command  313  is checked to see whether launching an inflow request is favorable for executing a read/write consecutively in a next time. 
         [0036]    When executing selection stage  307 , the order of executing priority is performed according to the precharge stage  302 , the opening stage  303 , the reopening stage  305 , and the command executing stage  306  so that the memory controller  100  can process a plurality of read/write requests, and determine, according to different banks, whether to execute the operation corresponding to the row address setting in advance to reduce the waiting time when a read/write command operation needs to be executed. The priority order of executing substantially follows the auto-refresh/refresh command, the command executing stage  306 , the reopening stage  305 , the opening stage  303  and the precharge stage  302  in sequence. 
         [0037]    For an example of how the architecture shown in  FIG. 3  can improve the performance of the memory controller  100  when accessing the memory  108 , refer to  FIGS. 5 and 6 .  FIG. 5  is a timing diagram illustrating the page accessing different banks in the prior art and  FIG. 6  is a timing diagram illustrating the page accessing different banks according to an embodiment of the present invention. 
         [0038]    Referring to the timing diagram shown in  FIG. 5 , assume the memory controller  100  needs to read the data of the 0 th  page in the first bank first then the data of the 0 th  page in the second bank, and the 1 st  page in the second bank is opening. In the prior art, the memory controller  100  transmits the opening command  501  (open_b1p0) via the command pins to the memory  108  for opening the 0 th  page in the first bank, then transmits the read command  502  (rd_cmd0) to the memory  108  for reading data data0_0, data0_1, data0_2, data0_3 from the memory  108  via the data pins. Next, the memory controller  100  transmits the closing command  503  (close_b2p1) to the memory  108  for closing the 1 st  page in the second bank. Next, the memory controller  100  transmits the opening command  504  (open_b2p0) to the memory  108  for opening the 0 th  page in the second bank, then transmits the read command  505  (rd_cmd1) to the memory  108  for reading data data1_0, data1_1, data1_2, data1_3 from the memory  108 . In the operation shown in  FIG. 5 , because it is necessary to wait between every command, and there is also a necessary waiting time between the read command and starting to read data, reading data has a poorer performance. 
         [0039]    Referring to the timing diagram shown in  FIG. 6 , assume the memory controller  100  needs to read the data of the 0 th  page in the first bank first then the data of the 0 th  page in the second bank, and the 1 st  page in the second bank is opening. In this embodiment of the present invention, the memory controller  100  transmits the opening command  601  (open_b1p0) via the command pins to the memory  108  for opening the 0 th  page in the first bank. Next, because the waiting time between the opening command  601  and the closing command  602  for closing the 1 st  page in the second bank is not very long, after opening the command  601 , the memory controller  100  can transmit the closing command  602  (close_b2p1) immediately to the memory  106  for closing the 1 st  page in the second bank. Next, the memory controller  100  transmits the read command  603  (rd_cmd0) to the memory  108  to ask for reading the data in the memory  108 . Then, because the waiting time between the read command  603  and the opening command  604  of the 0 th  page in the second bank is not very long, after the read command  603 , the memory controller  100  can transmit the opening command  604  (open_b2p0) immediately to the memory  108  for opening the 0 th  page in the second bank. Next, the memory  108  starts to correspond to the read command  603  to transmit the data data0_0, data0_1, data0_2, data0_3 back via the data pins, and during the process of transmitting back the data data0_0, data0_1, data0_2, data0_3, the memory controller  100  can send the read command  605  (rd_cmd1) to the SDRAM 108  to ask to read the data in the 0 th  page in the second bank of the memory  108 . Therefore, after transmitting the data data0_0, data0_1, data0_2, data0_3, the memory  108  can correspond to the read command  605  immediately to send data data1_0, data1_1, data1_2, data1_3 back via the data pins. 
         [0040]    Compared to the prior art method of  FIG. 5 , in the flow of  FIG. 6 , because the steps of closing the 1 st  page in the second bank and opening the 0 th  page in the second bank are moved forward for executing, after the memory  108  corresponds to the read command  603  to transmit the data data0_0, data0_1, data0_2, data0_3 back, the memory  108  can correspond to the read command  605  immediately to transmit the data data1_0, data1_1, data1_2, data1_3 back so that the memory controller  100  can constantly receive the needed data via the data pins to increase the accessing efficiency of the memory controller  100 . It should be noted that the commands  601  and  603  are not limited to be the examples illustrated in the embodiment of  FIG. 6 . In other embodiments, the commands  601  and  603  can be any normal DRAM command. For example, active command, precharge command, write command or read command, etc. These alternative designs shall be fall within the scope of the present invention. 
         [0041]    Briefly summarized, the memory controller and the associated control method optimize the operating performance of the memory via an order rearrange with respect to accessing command by the protocol controller. More particularly, the memory controller and control method can open the following pages waiting to be accessed in advance to make the data transmission between the memory controller and the memory as consecutive as possible for increasing the usage rate of the memory bandwidth. 
         [0042]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.