Abstract:
Sintered connection structures and methods of manufacture are disclosed. The method includes placing a powder on a substrate and sintering the powder to form a plurality of pillars. The method further includes repeating the placing and sintering steps until the plurality of pillars reach a predetermined height. The method further includes forming a solder cap on the plurality of pillars. The method further includes joining the substrate to a board using the solder cap.

Description:
FIELD OF THE INVENTION 
       [0001]    The invention relates to semiconductor structures and, more particularly, to sintered connection structures and methods of manufacture. 
       BACKGROUND 
       [0002]    Current solder bump connection technologies can be costly and are limited by masking and plating processes. For example, fabrication processes constrain the thickness of copper pillars to about 75 um tall due to the aspect ratio of the photoresist expose and strip process. 
       SUMMARY 
       [0003]    In an aspect of the invention, a method comprises placing a powder on a substrate and sintering the powder to form a plurality of pillars. The method further comprises repeating the placing and sintering steps until the plurality of pillars reach a predetermined height. The method further comprises forming a solder cap on the plurality of pillars. The method further comprises joining the substrate to a board using the solder cap. 
         [0004]    In an aspect of the invention, a method comprises: placing a wafer in a chuck and coating the wafer with a plurality of layers of conductive powder, followed by a laser sintering after each coating to form conductive pillars of a predetermined height; forming a solder cap, on the conductive pillars; removing non-sintered powder by a cleaning process; joining a chip to the wafer between the conductive pillars; and joining the wafer to a board by a bonding process of the solder cap of the conductive pillars to the board. 
         [0005]    In an aspect of the invention, a structure comprises: a plurality of sintered copper pillars with a solder cap, comprising a height of approximately 75 μm or greater on a wafer; a chip joined to the wafer, between a plurality of sintered copper pillars; a laminate board joined to the wafer by the solder cap of the plurality of sintered copper pillars or other conductive material; and an underfill material bonding the chip, the wafer and the laminate board. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    The present invention is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present invention. 
           [0007]      FIGS. 1-5  show fabrication processes and respective structures in accordance with aspects of the invention. 
           [0008]      FIG. 6  shows fabrication processes and a respective structure in accordance with additional aspects of the invention. 
           [0009]      FIG. 7  shows fabrication processes and a respective structure in accordance with additional aspects of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0010]    The invention relates to semiconductor structures and, more particularly, to sintered connection structures and methods of manufacture. In more specific embodiments, the connection structures are fine pitched structures, which enable chip beneath chip stacking. In even more specific embodiments, the fine pitched structures are pillars with higher standoff (than conventional structures) to allow additional joining of chips. The pillars can be copper pillars with a solder cap, fabricated using fine pitch selective laser sintering (e.g., a version of 3D printing). In embodiments, the pillars can also be composed of alloys, with multiple heights and shapes. 
         [0011]    In embodiments, the connection structures described herein can be used for under bump metallurgy (UBM) deposition, amongst other structures. In further embodiments, the fabrication processes and resulting structures can be used to form discrete devices such as inductors, resistors, RF antennas and RF shielding, as well as micro bump printing for stacked chips. 
         [0012]    Advantageously, the fabrication processes enable formation of pillars that extend beyond 75 um in height, up to approximately 500 um in height or more. In fact, the fabrication processes and resulting structures provide controlled bump profiles for strain reduction. Also, the fabrication processes allow for controlled (e.g., software controlled) printing of binary and trinary metal systems on the wafer without additional plating steps, e.g., eliminating the need for masking and lithography processes. Accordingly, the fabrication processes described herein significantly reduce overall fabrication costs and time. Also, the fabrication processes described herein provide the ability to selectively develop different sized and shaped solder bumps on the same wafer. 
         [0013]      FIG. 1  shows a structure and respective fabrication processes in accordance with aspects of the invention. The structure  10  includes a wafer or substrate  12  mounted in a chuck  14 . In embodiments, the substrate  12  can be a semiconductor material composed of any suitable material including, but not limited to, Si, SiGe, SiGeC, SiC, Ge alloys, GaAs, InAs, InP, and other III/V or II/VI compound semiconductors. 
         [0014]    As further shown in  FIG. 1 , a powder  16  is formed on the substrate  12 . In embodiments, the powder  16  is a copper powder; however, the present invention contemplates the use of any conductive material such as tungsten or other metals or metal alloys. In further embodiments, the powder  16  can be an insulator material or even a polymer or nylon as examples. The powder  16  can be deposited to a thickness from about 1 micron to about 25 microns or more in each pass, and preferably about 5 microns in height. Subsequent to each coating of the powder deposition, a software controller laser  20  sinters portions of the powder to form pillars  18 . In embodiments, the sintering is provided in an inert atmosphere. 
         [0015]    The pillars  18  can be approximately 5 microns to greater than 200 microns in diameter and, in embodiments, can be provided in many different shapes as described further herein. In embodiments, the laser  20  can be a CO 2  laser or Yb laser, as examples, with a pulse of power or energy high enough to sinter the powder to form the pillars  18 . In embodiments, the power or energy of the pulse should melt but not reflow the powder  16 , noting that the power or energy of the pulse will thus vary depending on the material of the powder. 
         [0016]    As further shown in  FIG. 2 , additional powder  16  is formed on the substrate  12 . The powder  16  can be deposited to an additional thickness from about 3 microns to about 25 microns in this pass, and preferably about 5 microns in height. Subsequent to the powder deposition, the laser  20  can sinter portions of the additional powder to continue the formation of the pillars  18  to a greater height, as already described herein. In embodiments, the deposition and sintering processes can continue until the pillars extend beyond 75 um in height, up to approximately 500 um in height, which can enable a chip under chip configuration. 
         [0017]    In  FIG. 3 , additional powder  22  is formed on the upper layer of the powder  16 . In specific embodiments, the additional powder  22  is a solder powder coated on the powder  16 . As previously described, the additional powder  22  undergoes a sintering process. This sintering process will form a solder connection  24 . The solder connection  24  can be of varying height, depending on the particular application. 
         [0018]    In  FIG. 4 , any non-sintered powder (e.g., powder  16  and powder  22 ) is removed using conventional processes. For example, the non-sintered powder can be removed by a cleaning process such as a blowing process. After the removal of the non-sintered powder, pillars  25  will remain on the substrate  12 . In embodiments, the pillars  25  can be a combination of materials formed to a height of approximately 500 um or more, which is not possible with conventional plating processes. 
         [0019]    After a desired height is obtained, the structure will undergo a reflow process to round the pillars  25  and, more particular, to form a solder cap  24 ′ (e.g., solder cap). The wafer can then be diced to form separate chips  26 . In embodiments, the dicing can be performed in any conventional manner, e.g., scribing and breaking, by mechanical sawing or by laser cutting. 
         [0020]    In  FIG. 5 , a chip  28  is bonded to the chip  26  between the pillars  25 . In embodiments, the chip  28  includes plating of micro-bumps consisting of either traditional C4 or copper pillars designated at reference numeral  30 . The chip  28  can be bonded to the substrate  12  by a reflow of the C4 solder connection or thermocompression bonding connection, on a same side of the chip  26  as the pillars  25 . The chip  26  is then joined to a laminate, e.g., board  32 , by the solder cap  24 ′ (with the chip  28  bonded between the pillars  25 ). In embodiments, the board  32  can be an organic laminate and the bonding can be provided by a reflow of the solder cap  24 ′ at a reflow temperature of less than 300° C. and more specifically at a temperature which will not melt the copper pillar, e.g., about 250° C. to about 260° C. 
         [0021]    In embodiments, due to the increased height of the pillars  25 , the pillars  25  can be used to provide stress relieve (e.g., absorb stress) resulting from coefficient thermal expansion (CTE) mismatch between the chip  26  and the board  32 . Drop test results will also be improved by the increased pillar height. That is, the pillars  25  will provide strain reduction. In optional embodiments, an underfill  34  can be added for improved reliability; that is, an epoxy or other paste  34  can provided between the chip  28 , chip  26  and board  32 . 
         [0022]      FIG. 6  shows fabrication processes and a respective structure in accordance with additional aspects of the invention. In this structure  10 ′, the pillars  25 ′ can be cone or tapered shaped with a larger diameter “x” at the base and a narrower section “y” at the solder cap  24 ′. In embodiments, the ratio of x:y can be about 2:1. The shape of the pillars  25 ′ can further reduce the stress in the chip back end of the line (BEOL) by increasing the area of chip interconnect and increasing bump height, while enabling increased routing density in the laminate (board  32 ). As shown and described with respect to  FIG. 5 , a chip  28  is bonded to the chip  26  between the pillars  25 , and the chip  26  is then joined to a laminate, e.g., board  32 , by the solder cap  24 ′ (with the chip  28  bonded between the pillars  25 ). 
         [0023]      FIG. 7  shows fabrication processes and a respective structure in accordance with additional aspects of the invention. In this structure  10 ″, the pillars  25 ″ can have a concave shape (e.g., hourglass shape), with a larger diameter at both the base and the solder cap  24 ′, designated at “x” and a narrower section “y” therebetween. In embodiments, the ratio of x:y can be about 2:1. The shape of the pillars  25 ″ distributes the bump stress more uniformly across the copper pillar  25 ″ while maintaining a large interconnect to both the chip  26  and the laminate (board)  32 . As shown and described with respect to  FIG. 5 , a chip  28  is bonded to the chip  26  between the pillars  25 , and the chip  26  is then joined to a laminate, e.g., board  32 , by the solder cap  24 ′ (with the chip  28  bonded between the pillars  25 ). 
         [0024]    Accordingly, by using the processes and resultant structures described herein, it is now possible to tailor the shapes of the pillars to accommodate bending of the pillars, thus relieving stress within the structure due to CTE mismatch. In addition, the processes described can provide complex shapes and increase the height to width ratio to about 5:1, which is not feasible or even possible with conventional plating processes. 
         [0025]    The method(s) as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor. 
         [0026]    The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.