Abstract:
In embodiments of the present invention, the problems of poor low-frequency response, slow speed, high cost and high power consumption in conventional voltage translators are addressed by processing high frequency and low frequency components of an input signal separately in two parallel stages without the use of large passive components or slow devices. At the output, the processed high frequency and low frequency components are seamlessly merged at a combining stage that maintains the integrity of the frequency response over the complete translator bandwidth.

Description:
RELATED APPLICATIONS 
       [0001]    The present application claims priority under 35 U.S.C. §119 from U.S. Provisional Patent Application Ser. No. 61/174,689, filed on May 1, 2009, the entire contents of which are hereby incorporated by reference. 
     
    
     FIELD OF THE INVENTION  
       [0002]    The present invention relates generally to voltage translators used in integrated circuits (ICs), and more specifically, to wideband voltage translators used in high-speed ICs. 
       BACKGROUND OF THE INVENTION  
       [0003]    In high-speed ICs, it is often necessary to drive signals, i.e. translate signal voltages, from one voltage domain to another (higher or lower) voltage domain. For example, in high-speed ICs, it may be required to translate signal voltages between an “I/O” voltage domain and a “core” voltage domain, or between a “clean” analog voltage domain and a “dirty” digital voltage domain. The signals to be translated may be single-ended signals or differential signals. In the case of single-ended signals, the voltage translation effectively changes the reference voltage of the signals of interest, and in the case of differential signals, the voltage translation alters the common mode voltage of the signals. 
         [0004]    Various implementations of a voltage translation circuit exist in the prior art; the following is a discussion of three conventional implementations. The first implementation translates signal voltage from an input voltage domain to an output voltage domain by using large series AC-coupling capacitors tied to large resistors. In effect, the capacitors block the DC components and pass the AC components of the signal, and generate the output signal in the output voltage domain. The resistors and capacitors in this implementation are required to be large to pass the low-frequency content without undesirable “droop” in the frequency response. However, the use of large resistors or large capacitors results in large circuit area and high cost, which are undesirable. In addition, the parasitic capacitance of the AC-coupling capacitor tends to negatively effect the high frequency performance of the circuit. 
         [0005]    The second implementation uses emitter followers or source followers to shift voltages between input and output domains, hence eliminating the need for large passive components, like in the first implementation, with minimal compromise of speed. However, this implementation does not readily allow an arbitrary shift in the voltage level of a signal, and particularly, with regard to differential signals, this implementation has an undesirable property that the output common mode voltage is proportional to the input common mode voltage. 
         [0006]    The third implementation employs a transconductance amplifier to convert the input voltage signal to a current signal that is delivered across the voltage domain boundary. At the output side of this implementation, either a resistive load or another transconductance stage may be used to convert the current signal back to a voltage signal. This approach also does not require large passive components, but is often much slower than the two above-discussed implementations because it often requires slower high-voltage devices or p-type devices in the signal path. 
       SUMMARY OF THE INVENTION  
       [0007]    In embodiments of the present invention, the problems of poor low-frequency response, slow speed, high cost and high power consumption in voltage translators are addressed by processing high frequency and low frequency components of an input signal separately in two parallel stages without the use of large passive components or slow devices. At the output, the processed high frequency and low frequency components are seamlessly merged at a combining stage that maintains the integrity of the frequency response over the complete translator bandwidth. In various embodiments, voltage translators and methods pertaining to this invention may be used in programmable gain amplifiers (PGAs) in an RF communication system operating over a wide range of frequencies. 
         [0008]    Accordingly, in one aspect, the invention pertains to a voltage level translator for translating an input signal in an input voltage domain to an output signal in an output voltage domain. The translator includes a low frequency stage, a high frequency stage, and a combining stage. The low frequency stage receives and processes the input signal to generate a first processed signal in a low frequency range, wherein the first processed signal is in the output voltage domain. The high frequency stage receives and processes the input signal to generate a second processed signal in a high frequency range, wherein the second processed signal determines a bandwidth of the translator. The combining stage combines the first and second processed signals to generate the output signal in the output voltage domain. 
         [0009]    In various embodiments, at least one of the input signal and the output signal is a single-ended signal or a differential signal. 
         [0010]    In various embodiments, the translator is implemented using CMOS or BiCMOS technology. 
         [0011]    In various embodiments, the low frequency stage includes a DC-coupled amplifier. In one embodiment, the DC-coupled amplifier includes a transconductance amplifier for converting the input voltage signal into a current signal. The DC-coupled amplifier may further comprise a conversion stage for receiving and converting the current signal into the first processed signal. In one embodiment, the DC-coupled amplifier further includes a cascode stage operatively connected between the transconductance amplifier and the conversion stage for transferring the current signal therebetween. 
         [0012]    In various embodiments, the high frequency stage comprises an AC-coupled amplifier. In one embodiment, the AC-coupled amplifier includes a source follower or an emitter follower amplifier for amplifying the input signal to generate the second processed signal. In another embodiment, the AC-coupled amplifier further includes a gain enhancement block. 
         [0013]    In one embodiment, the combining stage includes an RC, an LC or an RLC filter. 
         [0014]    In one embodiment, the low frequency and high frequency stages are implemented using the same transistors. 
         [0015]    In another aspect, the invention pertains to a method of translating an input signal in an input voltage domain to an output signal in an output voltage domain. The method includes receiving the input signal at a low frequency stage and at a high frequency stage. In one embodiment, at the low frequency stage, the input signal is processed to generate a first processed signal in a low frequency range, wherein the first processed signal is in the output voltage domain. At the high frequency stage, the input signal is processed to generate a second processed signal in a high frequency range, wherein the second processed signal determines a bandwidth of the translator. The method further includes combining the first and second processed signals at a combining stage to generate the output signal. 
         [0016]    In various embodiments, the method is used in a voltage level translation circuit which is implemented using CMOS or BiCMOS technology. 
         [0017]    In various embodiments, processing the input signal at the low frequency stage includes converting the input voltage signal into a current signal. In one embodiment, the processing at the low frequency stage further includes converting the current signal into the first processed signal. 
         [0018]    In various embodiments, processing the input signal at the high frequency stage includes amplifying the high frequency component of the input signal to generate the second processed signal. 
         [0019]    The foregoing and other features and advantages of the present invention will be made more apparent from the description, drawings, and claims that follow. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0020]    In the drawings, like reference characters generally refer to the same parts throughout the different views. Also, the drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the present invention are described with reference to the following drawings, in which: 
           [0021]      FIG. 1  depicts a block diagram of a voltage translator according to an illustrative embodiment of the invention; 
           [0022]      FIG. 2  depicts a CMOS implementation of the voltage translator depicted in  FIG. 1 ; 
           [0023]      FIG. 3  depicts a block diagram a voltage translator according to another illustrative embodiment of the invention; 
           [0024]      FIG. 4  depicts a CMOS implementation of the voltage translator depicted in  FIG. 2 ; 
           [0025]      FIG. 5  depicts a merged BiCMOS implementation of the voltage translator depicted in  FIG. 1 ; and 
           [0026]      FIG. 6   a  depicts the magnitude of a frequency response of the BiCMOS implementation depicted in  FIG. 5 . 
           [0027]      FIG. 6   b  depicts the phase of a frequency response of the BiCMOS implementation depicted in  FIG. 5 . 
       
    
    
     DESCRIPTION OF THE INVENTION  
       [0028]    In general, the present invention pertains in various embodiments to voltage level translators and methods for translating signals from one voltage domain to another voltage domain. To provide an overall understanding of the invention, certain illustrative embodiments are described, including voltage level translators and methods for translating signals in, e.g. radio frequency (RF) range from about 10 MHz to about 5000 MHz, in an RF communication system. 
         [0029]      FIG. 1  shows a block diagram of a voltage translator  100  according to an illustrative embodiment of the invention. The illustrated translator translates the signal voltage from an input voltage domain, V in , to an output voltage domain, V out . The translator  100  includes a low frequency processing stage  102  and a high frequency processing stage  104 , both receiving the same input signal  106 . The input signal  106  may be a single-ended signal or a differential signal. If the input signal is a single-ended signal, the input voltage domain, V in , is represented by the reference value of the input signal  106 . When input signal  106  is a differential signal, V in  is represented by the common mode voltage of the input signal  106 , and in this case, as well known to a person skilled in the art, the input signal  106  will include two 180-degree phase-shifted signals, e.g.  106   p,    106   n.    
         [0030]    The low frequency processing stage  102  may be configured to process the input signal  106  to generate a signal  108  in a low frequency range. In one embodiment, the reference voltage or the common mode voltage of the signal  108  does not determine the overall bandwidth of the translator, but is directly related to the voltage domain of the output signal of the translator  100 . Accordingly, the signal  108  may have the reference voltage value (for the single-ended case) or the common mode voltage value (for the differential case) in the desired output voltage domain, V out . 
         [0031]    The high frequency processing stage  104  may be configured to process the input signal  106  to generate a signal  110  in a high frequency range. In one embodiment, the reference voltage or the common mode voltage of the signal  110  does not contribute toward or is not relevant to the voltage domain of the output signal of the translator  100 , but determines the overall bandwidth of the translator  100 . Generally, the implementations of the stages  102 ,  104  may be chosen such that the translator  100  has favorable characteristics in terms of speed, breakdown voltages, power consumption, and size, for both low and high frequency ranges. For example, in one embodiment, the stage  104  is implemented without the use of passive components, or any slow or p-type devices. 
         [0032]    In one embodiment, the low frequency processed signal  108  and the high frequency processed signal  110  are combined at a combining stage  112 . The combining stage  112  combines the signals  108 ,  110  to produce an output signal  114 , which collectively has the properties of the signals  108 ,  110 . In other words, the output signal  114  has the reference voltage or the common mode voltage in the desired output voltage domain, V out , and also has the frequency range which covers the complete bandwidth of the translator  100 . In one embodiment, the values chosen for the components in the combining stage  112  determine the frequency (within the translator bandwidth) at which the low frequency processed signal  108  and the high frequency processed signal  110  are merged while still maintaining the integrity of the overall frequency response of the translator  100 . 
         [0033]      FIG. 2  shows a CMOS implementation of the embodiment of the translator  100  shown in  FIG. 1 , and accordingly, uses the same labels for the components shown in both  FIGS. 1 and 2 . This implementation is shown and will be discussed with respect to differential signals. 
         [0034]    In this embodiment, the low frequency processing stage  102  comprises a transconductance amplifier and two “folded” cascode amplifiers. In one embodiment, the transconductance amplifier includes n-type field-effect transistors (FETs) T 1  and T 2 , the gates of both of which receive input signals  106   p,    106   n.  The input signals  106   p,    106   n  have a phase difference of 180 degrees and together constitute the differential input signal  106  (which is in input voltage domain, V in ) of  FIG. 1 . The source of the transistor T 1  is connected to a current source I 1  which is connected to ground. Similarly, the source of the transistor T 2  is connected to a current source I 2  which is connected to ground. A resistor R 1  is connected at the top of the current sources I 1 , I 2 . At node  202 , the drain of the transistor T 1  is connected to one end of a current source I 3 , the other end of which is connected to a voltage supply, Vdd. Similarly, at node  204 , the drain of the transistor T 2  is connected to one end of a current source I 4 , the other end of which is also connected to the voltage supply Vdd. In this embodiment, the transconductance amplifier converts the input voltage signals  106   p,    106   n  into respective current signals  206 ,  208  supplied at nodes  202 ,  204 . 
         [0035]    In one embodiment, one folded cascode amplifier of the low frequency processing stage  102  includes the transistor T 1  and a p-type FET T 3 , and processes the current signal obtained from the difference of a current signal from I 3  and the current signal  206 . The other folded cascode amplifier includes the transistor T 2  and a p-type FET T 4 , and processes the current signal obtained from the difference of a current signal from  14  and the current signal  208 . The drain of the transistor T 3  is connected at node  202 , and the drain of the transistor T 4  is connected at node  204 . The gates of the transistors T 3 , T 4  are connected to a biasing voltage source, Vcas, and their sources are connected to load resistors R 2  and R 3 , respectively. The other ends of the resistors R 2 , R 3  are commonly connected to the source of an n-type transistor T 5 , the gate of which is self-biased and the drain is connected to ground. In one embodiment, Vcas is not greater than Vdd. In one embodiment, the transistors T 1 , T 2 , T 3 , T 4  operate in the input voltage domain, V in , and the transistor T 5  operates in the output voltage domain, V out . In one embodiment, the load resistors R 2 , R 3 , and the transistor T 5  constitute a conversion stage to convert current signals from nodes  202 ,  204  into voltage signals  108   p,    108   n.  The conversion stage may include other passive and active components connected in different topologies. 
         [0036]    The current signal from node  202  passes through the transistor T 3 , and is converted back to a voltage signal  108   n  at the resistor R 2 . Similarly, the current signal from node  204  passes through the transistor T 4 , and is converted back to a voltage signal  108   p  at the resistor R 3 . In one embodiment, the common mode voltage of the signals  108   p,    108   n  is in the desired output voltage domain, V out , and is calculated as a sum of the voltage difference between the gate and source, V gs  of T 5  and the current value (at R 2  or R 3 ) times the resistance value (of R 2  or R 3 ). The voltage signals  108   p,    108   n  may have the phase difference of 180 degrees and may be available at nodes  210 ,  212 , respectively to be supplied to combining stages  112   p,    112   n.    
         [0037]    Still referring to  FIG. 2 , in one embodiment, the high frequency processing stage  104  is implemented as an emitter-follower differential amplifier pair. This differential amplifier pair includes two n-type FETs T 6 , T 7 . The gates of the transistors T 6 , T 7  receive the input signals  106   p,    106   n,  the drains are commonly connected to the voltage supply Vdd, and the sources are connected to ground through current sources  15 ,  16 . In one embodiment, according to the voltage swing of the input signals  106   p,    106   n,  the transistors T 6 , T 7  generate outputs  110   p,    110   n  at their respective sources, which are received at nodes  214 ,  216 . The common mode voltage of the signals  110   p,    110   n  may be less than Vdd, and not in the desired output voltage domain V out . In one embodiment, the gain of the differential amplifier pair is g 1 , where g 1  is desirably equal to one. However, in practical implementations, achieving unity gain may not be possible due to parasitic components in the differential amplifier pair, and the actual gain may be less than one. Accordingly, in one embodiment, a gain enhancement block  218  is connected at nodes  220 ,  222 . The gain enhancement block  218  may include n-type FETs T 8 , T 9 , and a current source I 7 . 
         [0038]    In one embodiment, the low frequency processed signal  108   p  is combined with the high frequency processed signal  110   p  at a combiner  112   p.  Similarly, the low frequency processed signal  108   n  is combined with the high frequency processed signal  110   n  at a combiner  112   n.  The combiners  112   p,    112   n  may be structurally similar or different. As shown in  FIG. 2 , both the combiners are the same and each includes a resistor and a capacitor. The combiner  112   p  includes a resistor R 4  connected with a capacitor C 1 , and the combiner  112   n  includes a resistor R 5  connected with a capacitor C 2 . In another embodiment, the combiners  112   p,    112   n  include passive networks comprising a resistor, a capacitor, and an inductor, or a capacitor and an inductor. 
         [0039]    For the signal  108   p  coming in at the resistor R 4 , the combiner  112   p  may act as a first-order low pass RC filter, and for the signal  110   p  at the node  212  arriving at the capacitor C 1 , the combiner  112   p  may serve as a first-order high pass CR filter. The cut-off frequency of both the low pass and the high pass filters is the same, and is calculated as the inverse of the product of the resistance of (R 4 +R 3 ) and the capacitance of C 1 . Accordingly, the combination of the low-pass signal  108   p  and the high-pass signal  110   p,  in the frequency response sense, may be seamless. 
         [0040]    The signal  110   p  entering the CR high-pass filter is DC blocked due to the capacitor C 1 , while the rest of the frequencies are passed with different attenuations. Accordingly, the DC component of the signal  110   p  may not be related to the desired output voltage domain V out , and the signal  110   p  may determine the overall bandwidth of a translator  100 . As discussed above, the signal  108   p  is in the output voltage domain V out , and hence, upon combination with the high-pass signal  110   p,  the combiner  112   p  generates an output signal  114   p  which is in the voltage domain V out , and has the frequency range equal to the bandwidth of the translator  100 . 
         [0041]    Similar to the operation of the combiner  112   p,  the combiner  112   n  receives the low frequency processed signal  108   n  and act as a first-order low-pass filter for that signal, and receives the high frequency processed signal  110   n  at the node  216  and acts as a first-order high-pass filter for the signal  110   n.  The cut-off frequency of each of these filters is calculated as the inverse of the product of the resistance of (R 5 +R 2 ) and the capacitance of C 2 , and this cut-off frequency may be different than the cut-off frequency of the filter of the combiner  112   p.  The combiner  112   n  combines the signals  108   n  and the signal  110  to generate an output signal  114   n,  and the common mode voltage of the signal  114   n  is, as desired, in the output voltage domain V out . 
         [0042]      FIG. 3  shows a block diagram of a voltage translator  100  according to another illustrative embodiment of the invention. The illustrated translator translates the signal voltage from an input voltage domain, V in , to an output voltage domain, V out . The translator  100  includes a low frequency processing stage  102 , a high frequency processing stage  104  providing an overall gain g 1 , and a high frequency processing stage  302  with an overall gain g 2 . In one embodiment, there is only one low frequency processing stage  102  required to work in parallel with one or more high frequency processing stages, e.g., stages  104 ,  302 . In another embodiment, the high frequency processing stages  110 ,  304  are implemented differently to provide different gains. Such a translator implementation with multiple gains may be required as part of a programmable gain amplifier application for various communications and signal processing systems. 
         [0043]    In this embodiment, all the stages receive the same input signal  106 , which may be a single-ended signal or a differential signal. The low frequency processing stage  102  may be configured to process the input signal  106  and generate a signal  108  in a low frequency range. In one embodiment, the reference voltage (for the single-ended case) or the common mode voltage (for the differential case) of the low frequency processed signal  108  is in the desired output voltage domain, V out . The high frequency processing stages  104 ,  302  may be configured to process the input signal  106  to generate signals  110 ,  304 , respectively, in high frequency range. In one embodiment, the signals  110 ,  304  determine the overall bandwidth of the translator. 
         [0044]    In one embodiment, the low frequency processed signal  108  and the high frequency processed signal  110  are combined at a combining stage  112 , and the signal  108  is also combined with the high frequency processed signal  304  at a combining stage  306 . The combining stages  112 ,  306  may be structurally different to maintain the different gains from the high frequency processing stages  104 ,  302 . The combining stages  112 ,  306  combine their respective input signals to generate output signals  114 ,  308 . In one embodiment, the signals  114 ,  308 , each have the reference voltage or the common mode voltage in the desired output voltage domain, V out , and also have the frequency range which covers the complete bandwidth of the translator  100 . 
         [0045]      FIG. 4  shows the detailed CMOS implementation of an embodiment of the translator  100  shown in  FIG. 3 . This implementation is shown and will be discussed with respect to differential signals. In this implementation, the stages  102 ,  104  and the combiners  112   p,    112   n  are structurally identical to those shown in  FIG. 2 . 
         [0046]    In this implementation, the high frequency processing stage  104  provides unity gain, i.e., g 1 =1, and the high frequency processing stage  302  provides gain, g 2 =½. In one embodiment, the implementation of the stage  302  is based on the implementation of the stage  104 , i.e., including a source follower differential amplifier pair and a gain enhancement block. However, to provide a gain of ½ at the output, the differential input signals  106   p,    106   n  may not be directly coupled to the gates of the transistor pair, as shown for the stage  104 . In one embodiment, the input signals  106   p,    106   n  are fed to a voltage divider network including resistors R 6 , R 7 , R 8 . Capacitors C 3 , C 4  may be connected in parallel to the resistors R 6 , R 7 , respectively, to pass the AC component and block the DC component of the input signals  106   p,    106   n  which is processed through the divider network. 
         [0047]    In one embodiment, the implementations of the combiners  306   p,    306   n  are based on the implementations of the combiners  112   p,    112   n,  i.e., each including a resistor and a capacitor, but further includes a voltage divider network comprising resistors R 9 , R 10 , R 11  in accordance with the specific gain requirement of the stage  302 . The divider network including R 9 , R 10 , R 11  is connected with the low frequency processed signals  108   p,    108   n  (which determine the voltage domain V out  of the output signal). Output signals  308   p,    308   n  from the combiners  306   p,    306   n  may have the common mode voltage in the domain V out  with gain equal to ½. 
         [0048]      FIG. 5  shows a merged BiCMOS implementation of an embodiment of the translator  100  shown in  FIG. 1 . In this implementation, bipolar junction transistors (BJTs) T 1 , T 2  operate both as a transconductance amplifier for the low frequency processing stage  102 , and as an emitter follower differential amplifier pair for the high frequency processing stage  104  of the translator  100 . The bases of the transistors T 1 , T 2  receive a differential signal including signals  106   p,    106   n  with a common mode voltage in the input voltage domain V in . The outputs of the transconductance amplifier  108   p,    108   n  may be received at nodes  502 ,  504  across resistors R 1 , R 2  connected to the collectors of the transistors T 1 , T 2 . The outputs of the emitter follower differential amplifier pair  110   p,    110   n  may be received at the emitters of the transistors T 1 , T 2  through capacitors C 1 , C 2 . In one embodiment, the signals  108   p,    110   p  are combined at a combining stage comprising the resistor R 1  and the capacitor C 1  to generate an output signal  114   p.  In another embodiment, the signals  108   n,    110   n  are combined at a combining stage comprising the resistor R 2  and the capacitor C 2  to generate an output signal  114   n.  The common mode voltage of the output signals  114   p,    114   n  may be in the output voltage domain V out . 
         [0049]    In various embodiments, the translator  100  is powered between power supplies, Vdd and Vss, each of which may be a positive or a negative power supply. 
         [0050]      FIG. 6   a,    6   b  plot the magnitude and phase, respectively, of a frequency response of the BiCMOS implementation of  FIG. 5 . Plots  602 ,  604  show the magnitude and phase frequency responses of the output of the low frequency processing stage  102  (i.e., the transconductance amplifier), plots  606 ,  608  show the magnitude and phase frequency responses of the output of the high frequency processing stage  104  (i.e., the emitter follower differential amplifier), and plots  610 ,  612  show the magnitude and phase frequency responses of the combined output. 
         [0051]    It will therefore be seen that the foregoing represents a highly advantageous approach to translate signal voltage between different voltage domains in high-speed ICs. The terms and expressions employed herein are used as terms of description and not of limitation and there is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described or portions thereof, but it is recognized that various modifications are possible within the scope of the invention claims.