Abstract:
An attenuating circuit including a reference signal path that is attenuated by an amount which is related to the attenuation in an attenuation signal path for the purpose of improving attenuation accuracy.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to attenuating circuits. 
     It is known to provide attenuating circuits using relays, PIN diodes, or Gallium Arsenide switches to alternate between an attenuation signal path, which attenuates a signal, and a reference signal path, which passes the signal without attenuation. The reference signal path is used to initially calibrate, using a leveling circuit, the attenuating circuit to compensate for signal denigration such as signal rolloff due to transmission of the signal. 
     SUMMARY OF THE INVENTION 
     It has been discovered that by providing a reference signal path that is attenuated by an amount which is related to the attenuation in an attenuation signal path, an attenuating circuit which has superior offset characteristics and a wide frequency range is advantageously produced. 
     In preferred embodiments: the attenuation path amount includes an attenuator value and a calibration value, and the reference path amount is substantially equal to the calibration value; the attenuating circuit further includes an input, an output, and first and second switches configured to alternately connect the attenuation signal path and the reference signal path between the input and the output; the first and second switches are single-pole, double-throw switches; the first and second switches have a significant series resistance; the first and second switches are Gallium Arsenide (GaAs) switches; the attenuation signal path and the reference signal path have substantially equal characteristic impedances, the calibration value is small; and, the calibration value is less than ldB. 
     In another aspect, the invention includes a step attenuator circuit including a plurality of attenuating circuits, each attenuating circuit having a value and including an attenuation signal path being configured to attenuate a signal by an amount related to the attenuating circuit value and a reference signal path being configured to attenuate the signal by a second amount, the second amount being related to the respective attenuating circuit value. 
     In preferred embodiments of this aspect of the invention, the attenuating circuit values include attenuation values and calibration values, and the second amounts are substantially equal to respective calibration values; the attenuation values are substantially equal to binary numbers; there are six attenuating circuits, and the attenuating circuits have attenuating circuit values of -1, -2, -4, -8, and -16 and -16 dB, respectively; the calibration value is small; and, the calibration value is less than ldB. 
     In another aspect, the invention is a signal generation system including a signal generator being configured to output a signal, an attenuating circuit configured to receive the signal and output an attenuated signal, the attenuating circuit including an attenuation signal path being configured to attenuate the signal by a first amount and a reference signal path being configured to attenuate the signal by a second amount, the second amount being related to the first amount, a leveling circuit, the leveling circuit being configured to provide a base signal using the signal attenuated by the second amount and receive the signal attenuated by the first amount and to output a calibrated test signal. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The drawings will first be briefly described. 
     FIG. 1 shows a system utilizing a digital attenuator according to the invention. 
     FIG. 2 shows an attenuator circuit of the FIG. 1 system. 
     FIG. 3 shows a schematic diagram of an unattenuated signal path. 
     FIG. 4 shows a schematic diagram of an attenuated signal path. 
    
    
     Structure 
     Referring to FIG. 1, signal generating system 10 includes signal generator 12 (e.g., a RF/microwave signal generator) outputting a signal to n-bit step attenuator circuit 14. Attenuator circuit 14 outputs an attenuated signal to leveling circuit 16. The output of leveling circuit 16 provides the input to a test circuit, e.g., a device under test (DUT). Attenuator circuit 14 is controlled by controller 18. 
     Referring to FIG. 2, n-bit step attenuator circuit 14 includes n single bit attenuator circuits 20. (E.g., a 3-bit step attenuator includes 3 single bit attenuator circuits.) Attenuator circuits 20 are arranged to provide attenuation values which correspond to binary numbers thereby allowing a range of attenuator values to be available to controller 18. (E.g., a 6-bit step attenuator could have attenuator circuit values of -1, -2, -4, -8 -16 and -16 dB to provide an attenuation range from -1 dB to -47 dB.) 
     Each single bit attenuator circuit 20 includes an attenuation path 22 and a reference path 24. At any given time, one of these paths is chosen by switches 26, 28, which may be, e.g., single-pole, double-throw Gallium Arsenide (GaAs) switches. GaAs switches allow extremely fast switching over a broad frequency range, e.g., GaAs switches are commercially available having usable frequency ranges from D.C. to approximately 20 GHz. Switches 26, 28 are controlled by controller 18 which is connected to individual switches 26, 28 via respective control lines 30. 
     Attenuation path 22 includes attenuation path attenuator 32 having an attenuator value equal to the binary value of attenuation circuit 20 plus a calibration value. The calibration value is preferably small, e.g., less than 1 dB. Reference path 24 includes reference path attenuator 34 having an attenuator value substantially equal to the calibration value of attenuation path attenuator 32. Attenuators 32, 34 also have characteristic impedances that are substantially equal. 
     operation 
     Referring to FIGS. 1 and 2, prior to using attenuator circuit 14 to attenuate signals, system 10 is leveled by leveling circuit 16 such that a base signal having a nominal reference power, P n , is constant over frequency. This leveling takes into account such things as rolloff due to transmission of the signal through the cables. This leveling also compensates for attenuators that are present in the reference signal path. GaAs switches have an impedance of about 5-10 Ω, have a significant series impedance. 
     More specifically, switches 26, 28 of attenuator circuits 20 are controlled to pass the signal outputted from signal generator 12 through the reference paths. Due to reference path attenuator 34, the voltage divider loss due to the series resistances of the switches is incorporated into the reference path calibrated by leveling circuit 16. Because the value of attenuator 34 equals the calibration value of attenuator 32 the offset of the outputted signal is equalized for both paths through attenuator circuit 20. Because this voltage divider loss is calibrated during the leveling of system 10, this loss does not cause an offset when attenuation path 22 is used. 
     After system 10 is calibrated, attenuation circuits 20 may be switched to attenuation paths 22 by controller 18 according to the amount the inputted signal is to be attenuated. Thus, the signal inputted to the test circuitry is attenuated without a corresponding offset. 
     Referring to FIGS. 3 and 4, the offset error between a reference signal path having no attenuation (i.e., an example that does not describe the invention herein as there is attenuation in both the attenuation path and the reference signal path in the invention) and an attenuation signal path is shown. In FIGS. 3 and 4 it is assumed that switches SW1 and SW2 have a 5Ω series resistance. 
     Referring to FIG. 3, in the reference signal path, for a matched circuit (i.e., the load resistance equals the source resistance), V ZZ , the voltage after switch SW1 is defined by the following formula: ##EQU1## where, Z1 =55Ω, 
     Z 2  =55Ω, and 
     V o  =Voltage of Source. 
     Thus, V ZZ  =0.5 V o . 
     In FIG. 4, when the signal path includes an attenuator, the output of SWl, V 22 , drops before it gets attenuated. Thus, table 1 shows the additional attenuation, which equals the offset error, for different attenuation values compared to V Z2 , the voltage after switch SW1 for a matched circuit. 
     
                       TABLE 1______________________________________                   AdditionalAttenuation    VZ.sub.2 &#39;                   Attenuation______________________________________ 1 dB          .498 Vo  -0.10 dB 2 dB          .497 Vo  -0.17 dB 4 dB          .486 Vo  -0.27 dB 8 dB          .480 Vo  -0.38 dB16 dB          .479 Vo  -0.39 dB______________________________________ 
    
     When attenuation is provided on the reference signal path, as it is in the present invention, the circuit is calibrated to compensate for the additional attenuation. 
     Other Embodiments 
     Other embodiments are within the following claims. 
     E.g., switches 26, 28 may be constructed within a single switch such as a transfer switch, thereby providing shorter signal paths for each single bit attenuation circuit 20. 
     Also, e.g., switches 26, 28 may be constructed of a plurality of single-pole single-throw switches. 
     Also, e.g., the values of reference path attenuators 34 are not necessarily equal as long as these values are equal to the offset value of their respective attenuation path.