Abstract:
High density integrated circuits and more particularly to a high density integrated circuit incorporating a multiplicity of functional chips arranged on a substrate comprised of a plurality of dielectric and conductive layers which interface the semiconductor dies with a ball gate array (BGA) arranged on the underside of the substrate and wherein the main heat generating areas of the semiconductor dies are directly coupled to selected balls of the BGA for directly carrying heat from the major heat sources away from the device.

Description:
[0001]     This application claims benefit to Provisional Application No. 60/668,172 which was filed on Apr. 4, 2005. 
     
    
     FIELD OF INVENTION  
       [0002]     The present invention relates to high density integrated circuits and more particularly to a high density integrated circuit incorporating a multiplicity of functional chips arranged on a common substrate comprised of a plurality of interspersed insulated dielectric and conductive layers which selectively interface terminals of the semiconductor dies to one another and to a ball grid array (BGA) arranged on the underside of the substrate and wherein the main heat generating areas of the semiconductor dies are directly coupled to selected balls of the ball grid array for directly carrying heat from the major heat sources away from the device.  
       BACKGROUND  
       [0003]     Leaded ceramic devices comprise a semiconductor die having leads typically around two or more sides of the perimeter of the device and which are typically connected to terminals on a printed circuit board arranged beneath the outwardly extending leads. These devices are typically referred to as leaded devices and in some instances leaded ceramic devices.  
         [0004]     By providing the input/output (I/O) connections on the bottom of the package, this significantly reduces the footprint of the device when compared with a leaded ceramic device.  
         [0005]     In addition to the above, there is a need to conduct heat away from the device in a direct and highly efficient manner.  
       SUMMARY  
       [0006]     The present invention is a plastic encapsulated ball grid array (BGA) device having the capabilities of a leaded ceramic device but with the advantages of utilizing a BGA and capable of conducting heat away from the high density device in a highly efficient manner.  
         [0007]     The device of the present invention comprises a multichip module (MCM) and in one preferred embodiment, comprises a protocol die, plural transceiver dies and an optional random access memory (RAM) die. The semiconductor dies are bonded to a substrate which is a high thermal gradient (Tg) BT utilizing a conductive epoxy, BT being known as a high temperature type of FR4. The components of the circuit are interconnected, preferably with gold wires bonded between the semiconductor devices and printed wiring on layers of the BT multilayer substrate. This assembly is then over-molded using an epoxy compound. I/O is achieved with the attached of an array of solder balls arranged in a regular matrix of rows and columns on the bottom of the substrate yielding the finished BGA package configuration. The multilayer substrate is comprised of a plurality of alternating copper and insulating layers. Micro vias, both “blind” and “through” vias, are provided to connect surface mounted components to selected ones of the conductive layers for interconnecting terminals of different dies. Vias “Through” vias serving as heat pipes are provided to directly conduct heat from high heat concentration regions of die mounted components so as to conduct the heat preferably in the shortest practical paths available. Selected ones of the die terminals are electrically connected to selected ones of the balls in the BGA for electrical connection to external terminals/components.  
         [0008]     Since the I/O are on the bottom of the package, the board area (i.e. the footprint of the package) is the same as the outer perimeter of the package thus significantly reducing the footprint required as compared with a leaded ceramic device having the same functional capability and components.  
         [0009]     In another embodiment, a RAM of double the memory capacity is provided, available as well as being provided with additional devices such as a quad buffer and multibit parity checking circuits. However, any number and variety of high density devices may be produced using the design and techniques of the present invention. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]      FIGS. 1A, 1B  and  1 C are top, side and bottom views of a first embodiment of the invention.  
         [0011]      FIG. 1D  is a plan view of the dies embodied in the finished package showing  FIGS. 1A-1C .  
         [0012]      FIG. 1E  is a detailed elevational view of the substrate.  
         [0013]      FIG. 1F  is a plan view of a common hole pattern for two layers of the substrate of  FIG. 1E .  
         [0014]      FIG. 1G  is a detailed elevational view of a portion of the multilayer substrate of  FIGS. 1A-1D .  
         [0015]      FIGS. 2A, 2B  and  2 C respectively show top, side and bottom views of another embodiment of the present invention.  
         [0016]      FIG. 2D  shows a layout of the dies encapsulated in the finished package shown in  FIGS. 2A-2C . 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0017]      FIGS. 1A-1C  show a first embodiment of a high density MCM  10  of the present invention which is a finished package preferably formed of a suitable epoxy compound. The top surface  10   a  is typically provided with alphanumeric indicia which may be arranged within the dashed lined areas to identify the nature of the MCM as well as other functions and capabilities.  10   c  represents the multilayered BT substrate, as will be described in detail below. The bottom surface  10   d  is provided with a plurality of balls arranged in a regular matrix array of x-rows and y-columns. In the embodiment shown, an array of eighteen (18) rows labeled 1-18 and eighteen (18) columns labeled A-H, J-N, P-R and T-V for a total of 324 balls make up the BGA. The diameter of the balls in the embodiment shown is 0.56 mm and the balls extend downwardly from the bottom surface  10   d  by distance of the order of 0.38 mm. The balls are preferably formed of Sn/Pb.  
         [0018]      FIG. 1D  is a top plan view of the dies incorporated within the finished package  10  shown, for example, in  FIG. 1A , the dies having been shown enlarged as compared with the package shown in  FIG. 1A  for purposes of clarity.  
         [0019]     The embodiment  10  is designed to function as one of a remote terminal (RT), monitor and bus controller (BC), and comprises a protocol die  14 , two transceiver dies  16  and  18  and a 64K RAM die  20 . Each of the dies  14 - 20  are bonded to the substrate, which is a high thermal gradient fiber reinforced material (Tg BT)  22  using a suitable conductive epoxy to electrically and mechanically secure the ground plane of each die to the substrate. The terminals of the dies are interconnected with gold wires G bonded at one end to each terminal of the dies  16 - 20  and at the other end to the multilayer substrate  22  which, although not shown for purposes of clarity, should be understood to be provided with conductive printed wiring for properly interconnecting the circuits. Connections of selected terminals of the dies  16 - 20  are electrically connected to selected terminals of other ones of the dies  16 - 20  through selected layers of the multi-layer substrate. After interconnection of all of the circuits, the dies are over-molded employing an epoxy compound that is impervious to moisture. The I/O is achieved by attaching the substrate terminals of the dies  14 - 20  to selective ones of the balls  12  of the BGA through substrate  10   c . In the preferred embodiment, the outer perimeter of the device  10  is 0.815 in.×0.815 in. Since the BGA is provided along the bottom of the package, the board area required is a maximum of the aforesaid outer perimeter which is less than 45% of the board area required by a conventional leaded ceramic device. The device is mounted on a printed circuit board having an array of terminals (not shown) which matches the BGA, for connection to external circuitry; power sources, ground planes and heat conducting planes, for example.  
         [0020]      FIG. 1E  is a detailed elevational view useful in showing the manner in which one preferred substrate design is produced, such as the substrate utilized for the embodiment  10  shown, for example, in  FIGS. 1A-1C . The substrate  10   c  is comprised of a total of eight (8) conductive layers labeled L 1  through L 6  as well as conductive layers G and VDDL. All of the aforementioned conductive layers are separated by seven (7) insulation layers I 1  through I 7 . The insulation layers are preferably 0.0035 inches thick. All of the inner conductive layers L 2  through L 5 , G and VDDL are 0.0007 inches thick. The two outer (i.e., top and bottom) layers L 1  and L 6  are 0.0014 inches thick and are further provided with layers of the order of 100 to 200 micro inches of nickel and 20 to 30 micro inches of gold for enhancing the gold wire bonding and for Sn/Pb ball attachment of the BGA  12 .  
         [0021]     Each layer is produced individually and the layers are then stacked upon one another. Insulating layer I 7  is provided with a conductive copper layer L 5  and the bottom, outer layer L 6 . These layers are then etched in a conventional manner to remove all of the copper from layers L 5  and L 6  except for the desired printed wiring pattern. Once the desired pattern is etched and the surface is cleaned, holes H are drilled through conductive layer L 5  and insulating layer I 7  in accordance with the hole pattern shown in  FIG. 1F . The printed wiring pattern provided on the top surface of insulating layer I 7  has been omitted from  FIG. 1F  for purposes of simplicity. After the holes H have been drilled, the holes which are marked by a circle are then plated to provide a conductive path through the insulating layer I 7 . Each of the remaining insulating layers, except layer I 1 , is covered with a thin copper layer, etched and cleaned, then drilled and then plated through selective ones of the drill holes. The layers are then stacked one upon the other in the manner and configuration shown in  FIG. 1E . The identical drill pattern shown in  FIG. 1F  is utilized for drilling and plating the holes in insulating layer I 2 . It should be understood that the thick top and bottom conductive layers L 1  and L 6  have printed wiring patterns etched in a similar manner as described above with regard to conductive layers L 5  and L 2 . The layers are joined together by application of heat and pressure as is conventional. As a final step, the bottom conductive layer is comprised of circular-shaped “dots” corresponding to the arrangement shown in, for example, in  FIG. 1C . The balls  12  of the BGA are placed in a holder having hemispherical recesses with through openings for each ball  12 . The holder is vibrated to properly seat each ball  12  in its recess and the holder is placed on and registered with the matrix array of conductive dots on the bottom of layer I 5 . The balls are initially perfect spheres and are slightly flattened in the region where they are joined to an associated “dot” by application of heat of a sufficient temperature for a sufficient time interval.  
         [0022]     The dies, such as, for example, the dies  16  through  20  shown in  FIG. 1D  are mounted upon the upper surface of insulating layer I 1  having the printed wiring layer L 1  by a suitable conductive epoxy.  FIG. 1G  shows a portion of dies  16 - 20  in which the gold wires G of a diameter of the order of 0.001 inches are connected between dies  16 - 20  and selected conductive pads T on the thicker top layer L 1  of the substrate  10 C. It should be understood that the layers and terminals are greatly enlarged as compared with their actual size for purposes of clarity. Layer L 1  is deposited on insulating layer I 1 . Layer L 2  is a conductive copper layer deposited on layer I 2 , a dielectric layer and so forth with the conductive copper and dielectric layers being arranged in alternating fashion as shown in  FIG. 1E . Vertically aligned conductive members hereinafter referred to as micro vias V, make electrical connections at selective layers for interconnecting components in the dies  16 - 20  as well as providing ground vias, electrical connection vias to external terminals/components and thermal vias. The thermal vias such as V′, for example, directly connect those portions of the dies  16 ,  18  which generate the greatest amount of heat within dies  16 ,  18  and are thus directly connected to a selected ball or balls  12 ′ for directly conducting heat preferably over the shortest practical path in order to convey heat away from the regions of high heat generation. The balls  12 ′ of the BGA carrying the heat away from the device  10  are connected to a conductive plane on the substrate (not shown) upon which the device  10  is mounted for conducting heat away from the device  10 . The vias conducting heat away from the high heat regions of the dies are preferably filled with conductive material such as solder. The holes conducting heat are preferably of the order of 0.004″ in diameter, while the holes for electrically coupling electrical terminals are preferably of the order of 0.004″ in diameter. Vias V″ connect one terminal T of die  16  to one terminal T′ of die  18 , vias V″ being electrically connected through a printed wiring pattern L 2 ′ on insulating layer I 2 .  
         [0023]      FIGS. 2A-2C  show another preferred embodiment  10 ′ of the present invention wherein the main difference as shown in  FIGS. 2A-2C  is the overall size of the completed package, the thickness of the package  10 ′ being substantially identical to the thickness of the package  10  as shown  FIGS. 2B and 1B  while the outer dimensions are different. The embodiment  10 ′ may also function as an RT, BC or monitor. In the embodiment  10 ′ the package has an outer perimeter of 1.10 in.×0.850 in. and the BGA of the balls  12  in the embodiment  10 ′ has a regular matrix array comprised of a total of 475 solder balls  12 , the solder balls of both embodiments preferably being formed of Sn/Pb. The balls  12  in both embodiments preferably have substantially the same diameter.  
         [0024]     The thermal resistance in both embodiments  10  and  10 ′ are comparable with a maximum of 15° C. per watt (C/W). There are two semiconductor devices in each of the embodiments  10  and  10 ′ that produce the bulk of the heat generated. This heat is dissipated through several solder balls which are arranged directly under each of the heat devices, together with additional thermal vias connected to ground planes within the FR4 substrate and brought out to other solder balls of the BGA. The embodiment  10 ′, as shown in  FIG. 2D , is comprised of a protocol chip  14 ′, two transceiver chips  16 ′,  18 ′ and a 128K dual port RAM  20 ′, one quad buffer  24  with tri-state outputs and two nine-bit parity checkers  26  and  28 . Three 2.4K ohm thin film resisters are used for pull ups. These dies are likewise bonded to the substrate  22 ′ employing a conductive epoxy and are similarly interconnected with gold wires G′ bonded between the semiconductor devices  14 ′- 20 ′ and  24 - 28  and terminals T on the multilayer substrate  22 ′. The assembly is similarly over-molded employing an epoxy compound.  
         [0025]     The terminals T are connected to selected layers L 1 -L N  and vias V to obtain the appropriate electrical connections between and among the components of the device and to provide heat conduction of maximum efficiency away from the high heat producing regions by dissipating this heat through a plurality of solder balls  12  arranged directly under each of the heat producing devices as well as employing additional thermal vias connected to ground planes in the BT substrate which ground planes extend to selected solder balls  12  of the BGA.