Abstract:
A circuit includes a first pre-charge module, a first multiplexer module, a second pre-charge module, a second multiplexer module, a sense amplifier circuit, a third pre-charge module, an output module. The circuit is operatively coupled to a first core block and a second core block to provide the desired matching characteristics. The first core block and the second core block are memory blocks used for storing data bits for read-write operations. The circuit utilizes a unique operational coupling with one of the core blocks to provide the matching characteristics.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to sensing schemes for non-differential signals, and more specifically, to a biased sensing scheme for enhancing matching characteristics with an improved response time. 
       BACKGROUND OF THE INVENTION 
       [0002]    A differential amplifier circuit is used to compare two signals for detecting a differential signal or to offset the noise of two simultaneously input signals, and is a circuit used in electronic devices. A balanced differential amplifier employs a need based strategy of matching the two branches of the differential pair (desire is to have minimum offset). In the case of balanced differential amplifier, noise that is generated due to high capacitances is cancelled out. In conventional unbalanced difference amplifiers, one of the differential input nodes is coupled to a reference node and the other is coupled to a signal source. The reference may not be in synchronization with the actual charge feeding or sinking of the branch coupled to the signal source. This creates additional offset over and above the offset introduced by asymmetric devices. Thus, a conventional unbalanced amplifier may be highly susceptible to failures due to mismatches between the differential branches feeding it. 
         [0003]      FIG. 1  illustrates a circuit diagram  100  of a conventional biasing circuit. The circuit  100  includes a core block  102 , pre-charge modules, such as  104 A,  104 B and  104 C, a multiplexer module  106 , a latch circuit  108 , and two PMOS pass transistors  110  and  112  coupled to the latch nodes SAT and SAF. In one embodiment, the core block  102  can be a NAND block, where input non-differential signals are allowed to enter a branch. The pre-charge modules  104 A,  104 B and  104 C include PMOS transistors. The latch circuit  108  includes two PMOS transistors  114  and  116  and two NMOS transistors  118  and  120 . The transistors  114  and  118  and the transistors  116  and  120  are individually coupled to form two inverters. 
         [0004]    The two inverters are cross coupled to form the latch circuit  108 . A pull down transistor  122  is coupled to the latch circuit  108 . A drain terminal of the pull down transistor  122  is coupled to the source terminals of the NMOS transistors  118  and  120  and the source terminal is coupled to a ground terminal. The gate terminal is controlled by a control signal SON. A source terminal of the PMOS pass transistor  110  is coupled to a node NET A, a drain terminal is coupled to a latch output node SAT, and the gate terminal is controlled by the control signal SON. A source terminal of the PMOS pass transistor  112  is coupled to a node NET B, a drain terminal is coupled to a latch output node SAF, and the gate terminal is controlled by the control signal SON. 
         [0005]    A non-differential input signal may enter the branch, when a clock signal CK is enabled. The non-differential input signal is multiplexed and is passed onto the latch output node SAT through the PMOS transistor  110 . A reference signal is given to the latch output node SAF through the PMOS transistor  112 . The non-differential signals are read in three phases. First, the branches, the reference line and latch output nodes SAT and SAF are pre-charged before a read or resolving cycle. Second, when the control signal CK is enabled, the pre-charge circuits are turned off, as their inputs go high. However, the reference pre-charge will not be turned off. It is in an on state. One of multiplexer pass transistors is turned on (i.e., its input turns low) depending on the multiplexer address, and the input signal gets coupled to the latch output node SAT or SAF. A control signal SON is turned high and the pull down transistor is turned on and latch output nodes are decoupled from the external signal. The sense amplifier resolves the initial difference created between SAT and SAF. 
         [0006]    However, due to the inherent mismatch in the devices coupled to the differential branches, the conventional method presents several problems at different stages of manufacturing as well as in the circuitry or architecture, where the non-differential amplifier is employed. It suffers from active and poly masking problems like STI (Shallow Trench Isolation) matching, mask misalignment, doping gradient and poly shadowing. It suffers from device level problems like large figure size, gate/drain/metal capacitance mismatches and physical effects like individual signal and supply capacitance differences, charge feed through internal node capacitance, and pass transistor shared node capacitance differences between the differential nodes. 
         [0007]    Therefore, there is a need for a sensing scheme for a low swing non-differential signal with a low input referred offset, so that the robustness of the system is improved. 
       SUMMARY OF THE INVENTION 
       [0008]    It is an object of the present invention to provide a biased sensing circuit for sensing non-differential signals with enhanced matching characteristics. It is another object to provide a biased sensing circuit with an improved response time. 
         [0009]    To achieve the aforementioned objectives, one aspect provides a biased sensing circuit for sensing non-differential signals comprising a first pre-charge module operatively coupled to a first core block for charging, and a first multiplexer module operatively coupled between the first pre-charge module and a first pass transistor. A second pre-charge module may be operatively coupled to a second core block for charging, and a second multiplexer module may be operatively coupled between the second pre-charge module and a second pass transistor. A sense amplifier circuit may be operatively coupled between the first multiplexer module and the second multiplexer module for receiving differential inputs through the first pass transistor and the second pass transistor to provide an output. A third pre-charge module may be operatively coupled to the differential inputs of the sense amplifier circuit, and an output module operatively may be coupled to the sense amplifier for providing an output signal. 
         [0010]    There may be a sense amplifier circuit comprising a latch circuit having a first inverter circuit cross-coupled to a second inverter circuit, a first pull down transistor operatively coupled to latch circuit for receiving a first control signal, a first pass transistor operatively coupled to the first inverter circuit, and a second pass transistor is operatively coupled to the second inverter circuit. A second pull down transistor operatively coupled to the first pass transistor and the second pass transistor for receiving a second control signal. 
         [0011]    Furthermore, a read only memory (ROM) comprises a plurality of memory blocks for storing data bits and a biased sensing circuit coupled to the plurality of memory blocks for providing enhanced matching characteristics. The biased sensing circuit may comprise a first pre-charge module operatively coupled to a first core block for charging, a first multiplexer module operatively coupled between the first pre-charge module and a first pass transistor, and a second pre-charge module operatively coupled to a second core block for charging. A second multiplexer module may be operatively coupled between the second pre-charge module and a second pass transistor. A sense amplifier circuit may be operatively coupled between the first multiplexer module and the second multiplexer module for receiving differential inputs through the first pass transistor and the second pass transistor to provide an output. A third pre-charge module may be operatively coupled to the differential inputs of the sense amplifier circuit, and an output module may be operatively coupled to the sense amplifier for providing an output signal. 
         [0012]    Another aspect is directed to a method of sensing non-differential signals through a biased sensing circuit. The method may comprise precharging input nodes, output nodes and sensing branches of the biased sensing circuit, selecting one of a first core block and a second core block through a selection line, applying a clock signal to turn off pre-charge modules to conduct through a selected multiplexer module for allowing an input signal to enter into one of the first core block and the second core block. The method may also include inverting the input signal, when the input signal enters in the second core block, and multiplexing the output lines with a select signal, when the input signal does not enter in the second core block. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]      FIG. 1  illustrates a circuit diagram of a biased sensing scheme, in accordance with the prior art. 
           [0014]      FIG. 2  illustrates a circuit diagram of a biased sensing scheme according to the present invention. 
           [0015]      FIG. 3  illustrates a circuit diagram of a sense amplifier according to the present invention. 
           [0016]      FIG. 4  illustrates a flow diagram of a method for sensing non-differential signals for providing minimum mismatching according to the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0017]    The preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the preferred embodiments. The present invention can be modified in various forms. The preferred embodiments of the present invention are only provided to explain more clearly the present invention to the ordinarily skilled in the art of the present invention. In the accompanying drawings, like reference numerals are used to indicate like components. 
         [0018]    One aspect provides a biased sensing module for minimizing the mismatch with an enhanced response time. 
         [0019]      FIG. 2  illustrates a circuit diagram  200  of a biased sensing circuit. The circuit  200  includes a first core block  202 A, a second core block  202 B, a first pre-charge module  204 A, a second pre-charge module  204 B, a third pre-charge module  204 C, a first multiplexer module  206 A, a second multiplexer module  206 B, a sense amplifier circuit  208 , a first PMOS transistor  210 , a second PMOS transistor  212  and an output module  214 . 
         [0020]    The first core block  202 A and the second core block  202 B are NAND blocks, where input non-differential signals are allowed to enter. The first core block  202 A is coupled to the pre-charge module  204 A. The first pre-charge module  204 A is coupled to the first multiplexer module  206 A. The first multiplexer module  206 A is coupled to the first PMOS transistor  210  through a node NET A. The second core block  202 B is coupled to the second pre-charge module  204 B. The second pre-charge module  204 B is coupled to the second multiplexer module  206 B. The second multiplexer module  206 B is coupled to the second PMOS transistor  212  through a node NET B. The third pre-charge module  204 C is coupled to sensing branches SAT and SAF of the sense amplifier circuit  208 . 
         [0021]    The third pre-charge module  204 C comprises three PMOS transistors  216 ,  218  and  220 . A source terminal of the PMOS transistor  216  is coupled to a voltage source, a drain terminal is coupled to the sensing branch SAT of the sense amplifier circuit  208 , and a gate terminal is coupled to a node N 1 . A source terminal of the PMOS transistor  218  is coupled to the voltage source, a drain terminal is coupled to the sensing branch SAF of the sense amplifier circuit  208  and a gate terminal is coupled to the gate terminal of the PMOS transistor  216  through the node N 1 . A source terminal of the PMOS transistor  220  is coupled to the drain terminal of the PMOS transistor  218 , a drain terminal is coupled to the drain terminal of the PMOS transistor  216 , and a gate terminal is coupled to the gate of the PMOS transistor  216  and the PMOS transistor  218  through the node N 1 . 
         [0022]    The output module  214  comprises multiplexed output lines. An output from the true sensing branch (SAT) of the sense amplifier circuit  208  is given to one output line. Two NOT gates are coupled to the output line. An output from the false sensing branch (SAF) of the sense amplifier circuit  208  is given to another output line. The two output lines are multiplexed using a PMOS transistor  218  and an NMOS transistor  216  to provide an output. 
         [0023]    The non-differential multiplexed signals have been split into a first core block  202 A and a second core block  202 B. Before the start of the cycle nodes SAT, SAF, NETA, NETB and the input lines are pre-charged. Before the arrival of a clock signal CK, selection of the core block is made by select lines, which also change the bias (on which side, i.e., SAT or SAF, the weaker pull down is to be coupled in the sense amplifier circuit  208 ). 
         [0024]    At the arrival of clock signal CK, the pre-charge modules are turned off, and selected multiplexer pass transistor is turned on irrespective of their coupling to the SAT or SAF branch. This is done in order to ensure similar (miller or parasitic) charge feeding or sinking at the differential nodes, both before and after sense pass transistors  210  and  212 . An input referred offset from the input branches has now been nullified. 
         [0025]      FIG. 3  illustrates a circuit diagram of a sense amplifier circuit  208 . The circuit  208  includes two PMOS transistors  302  and  304  and two NMOS transistors  306  and  308 . The NMOS transistor  306  is a weak transistor compared to the NMOS transistor  308 . The transistors  302  and  306  and the transistors  304  and  308  are individually coupled to form two inverters. The two inverters are cross-coupled to form a latch circuit. A pull down transistor  310  is coupled to the latch. A drain terminal of the pull down transistor  310  is coupled to the source terminals of the NMOS transistors  306  and  308  and the source terminal is coupled to a ground voltage level. The gate terminal is controlled by a control signal SON 1 . Two NMOS transistors  312  and  314  are coupled to the latch circuit. A drain terminal of the NMOS transistor  312  is coupled to a latch output node N 2  and the source terminal is coupled to a drain terminal of a pull down transistor  316 . A gate terminal of the transistor  312  is coupled to the gate terminals of the transistors  302  and  306 . The gate terminal of the transistor  312  is also coupled to the drain terminal of the PMOS transistor  304  and to the drain terminal of the NMOS transistor  308 . A drain terminal of the NMOS transistor  314  is coupled to a latch output node N 3  and the source terminal is coupled to a drain terminal of a pull down transistor  316 . A gate terminal of the transistor  314  is coupled to the gate terminals of the transistors  304  and  308 . The gate terminal of the transistor  314  is also coupled to the drain terminal of the PMOS transistor  302  and to the drain terminal of the NMOS transistor  306 . The transistor  312  is a strong transistor as compared to the transistor  314 . A source terminal of the pull down transistor  316  is coupled to the ground voltage level and a gate terminal is controlled by a control signal SON 2 . 
         [0026]    The two control signals SON 1  and SON 2 , depending on which multiplexer portion is to be selected, are used to select the bias created by the weak transistor  306  or  314  on one side and the strong transistor  308  or  312  at the other. If a control signal Select 1  is applied, the first core block  202 A may be selected and the control signal SON 1  may be enabled and the signal at the SAT branch will be resolved. If a control signal Select 2  is applied, the second core block  202 B may be selected and the control signal SON 2  may be enabled and the signal at the SAF branch may be resolved. The sense may be perfectly balanced in terms of the load and capacitive coupling at the two differential branches. 
         [0027]    If an input from an upper or lower portion is to be read (depends on select signal Select 1  or Select 2 ) after the differential voltage development phase, control signals Son 1  or Son 2  goes high, so that the side being read is pulled down slower as compared to the other side. The voltage difference for a read- 0  (bit line discharge) may be sufficient enough to offset this difference in transistor strengths for correct read- 0  operation (read- 1  operation is favored by the bias). 
         [0028]    No differentiation is done at the multiplexer pass transistor level on whether a signal from the branch coupled to SAT or SAF is to be resolved, but the differentiation is shifted to two different levels. First, inside the sense amplifier circuit  208 , where the select signal decides whether a signal at the SAT branch may be resolved or a signal at the SAF branch has to be resolved. Second, at the core block level, where the select signal is mixed with the clock signal CK, is decided whether the signal from the branch coupled to SAT or SAF should be allowed to enter. 
         [0029]    The input signals on the second core block  202 B are inverted. This has to be done if an input from the lower half is to be resolved, a low swing on that input should swing the sense in the same direction as that if a low swing on an input from upper half is to be resolved. 
         [0030]    The above method may not be possible in some applications. Then another approach is to multiplex the output lines with the select signal through the output module  214 . 
         [0031]      FIG. 4  illustrates a flow diagram of a method for sensing non-differential signals with minimized mismatch. At step  402 , input nodes, output nodes and sensing branches of the biased sensing circuit are pre-charged. At step  404 , one of a first core block and a second core block is selected through a selection line. At step  406  a clock signal is applied to turn off pre-charge modules to conduct through a selected multiplexer module for allowing input signals to enter into one of the first core block and the second core block. At step  408 , the input signals are inverted, when the input signals enter the second core block. At step  410 , the output lines are multiplexed with a select signal. 
         [0032]    These devices and methods offer many advantages. First, robustness of the system is improved as the input referred offset is very low. Second, the speed is increased as a lower voltage difference has now to be ensured which is attributed to a lower input referred offset. The increase in speed is further attributed to a lower capacitance due to a split multiplexer circuit. Third, there is reduction in power as the input lines reduce the swing to detect a zero. Fourth, the effort in making a layout is reduced as the structure is now fully differential. Fifth, a reduction in area as the reference branch has been managed. 
         [0033]    Although the disclosure of system and method has been described in connection with the embodiments of the present invention illustrated in the accompanying drawings, they are not limited thereto. It will be apparent to those skilled in the art that various substitutions, modifications and changes may be made thereto without departing from the scope and spirit of the disclosure.