Abstract:
A display panel including a first sub-pixel, a second sub-pixel, and a processing unit is disclosed. The first sub-pixel includes a first storage capacitor for storing a first voltage. The second sub-pixel includes a second storage capacitor for storing a second voltage. The processing unit processes the first voltage and transmits the processed result to the first or the second capacitor according to a control signal group.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The invention relates to a display panel and an electronic system, and more particularly to a low power display panel and an electronic system utilizing the same. 
         [0003]    2. Description of the Related Art 
         [0004]    Liquid crystal displays (LCD) are widely used, as they possess the favorable advantages of thin profile, light weight, and low radiation. LCDs are frequently utilized in portable devices, such as digital still cameras (DSC), notebook computers, and personal digital assistants (PDA) among others. LCD driving methods include static driving, simple matrix driving, and active matrix driving. Simple matrix driving (also known as passive matrix) comprises a twisted nematic (TN) type and a super twisted nematic (STN) type. Thin film transistors (TFT) are typically utilized in active matrix LCDs. 
         [0005]    Because LCDs do not emit light, a backlight, preferably capable of providing high, uniform brightness, is utilized. An LCD typically comprises a source driver for providing data signals to a plurality of sub-pixels. Each sub-pixel comprises a liquid crystal component. A data signal rotates a corresponding liquid crystal component to allow light emitted from backlight to pass through the liquid crystal component. Thus, a pixel displays a gray level. The source driver must continuously provide data signals resulting in excessive power consumption. 
       BRIEF SUMMARY OF THE INVENTION 
       [0006]    Display panels are provided. An exemplary embodiment of a display panel comprises a first sub-pixel, a second sub-pixel, and a processing unit. The first sub-pixel comprises a first storage capacitor for storing a first voltage. The second sub-pixel comprises a second storage capacitor for storing a second voltage. The processing unit processes the first voltage and transmits the processed result to the first or the second capacitor according to a control signal group. 
         [0007]    Electronic systems are also provided. An exemplary embodiment of an electronic system comprises a display panel and a main module. The display panel comprises a first sub-pixel, a second sub-pixel, and a processing unit. The first sub-pixel comprises a first storage capacitor for storing a first voltage. The second sub-pixel comprises a second storage capacitor for storing a second voltage. The processing unit processes the first voltage and transmits the processed result to the first or the second capacitor according to a control signal group. The main module executes associated functions. 
         [0008]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    The invention can be more fully understood by referring to the following detailed description and examples with references made to the accompanying drawings, wherein: 
           [0010]      FIG. 1  is a schematic diagram of an exemplary embodiment of an electronic system; 
           [0011]      FIG. 2  is a schematic diagram of an exemplary embodiment of a display panel; 
           [0012]      FIG. 3  is a schematic diagram of an exemplary embodiment of sub-pixels in a column; 
           [0013]      FIG. 4  is a schematic diagram of an exemplary embodiment of a processing unit, 
           [0014]      FIG. 5  is a schematic diagram of another exemplary embodiment of a processing unit; and 
           [0015]      FIG. 6  is a timing diagram of control signals. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0016]    The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
         [0017]      FIG. 1  is a schematic diagram of an exemplary embodiment of an electronic system. The electronic system  100  comprises a power supply  110 , a main module  120 , and a display panel  130 . Power supply  110  is a battery for directly providing power PW. The power PW is a direct current (DC). In some embodiments, power supply  110  is an adapter for transforming an alternating current (AC) power to DC power. 
         [0018]    Main module  120  receives the power PW and executes associated functions according to the type of electronic system  100 . For example, if electronic system  100  is a mobile phone, main module  120  executes associated communication functions. If electronic system  100  is a PDA, main module  120  executes data processing functions. In some embodiments, electronic system  100  is a NB, a personal computer (PC), or a digital TV. 
         [0019]    Display panel  130  is controlled by main module  120  for displaying images.  FIG. 2  is a schematic diagram of an exemplary embodiment of a display panel. Display panel  130  comprises a gate driver  210 , a source driver  220 , and sub-pixels P 11 ˜P mn . Gate driver  210  provides scan signals to sub-pixels P 11 ˜P mn  via scan line S 1 ˜S n . Source driver  220  provides data signals to sub-pixels P 11 ˜P mn  via data line D 1 ˜D m . All sub-pixels in a row (one scan line) are turned on or off by one scan signal,thus, data signals are stored in the corresponding sub-pixels. In this embodiment, all sub-pixels in a column (one data line) are controlled by a control signal group S G . In some embodiments, all sub-pixels in a column are respectively controlled by a plurality of control signal groups. 
         [0020]    Description of the operation of gate driver  210  and source driver  220  is omitted, as they are well known to those skilled in the art. In this embodiment, data signals control whether light generated by a backlight (not shown) passes through the sub-pixels P 11 ˜P mn . Additionally, sub-pixels P 11 ˜P mn  can be red (R), green (G), or blue (G). In other words, a single pixel comprises three sub-pixels, R, G, and B. 
         [0021]      FIG. 3  is a schematic diagram of an exemplary embodiment of sub-pixels in a column. In this embodiment, each sub-pixel comprises a processing unit controlled by a control signal group. In some embodiments, the processing unit does not comprise a sub-pixel and one control signal group controls all processing units. Additionally, a processing unit controls all sub-pixels P 11 ˜P mn . 
         [0022]    Taking sub-pixel P 12  as an example, when a transistor  321  is turned on by a scan signal on scan line S 2 , a data signal on data line D 1  is transmitted to a storage capacitor  322  via transistor  321 . Thus, sub-pixel P 12  displays the corresponding brightness. Processing unit  323  processes voltage stored in storage capacitor  322  according to a control signal group S G2  and transmits the processed result to storage capacitor  312 ,  322 , or  332 . 
         [0023]    When display panel  130  desires to display the same images, processing unit  323  stores the processed result in storage capacitor  322 . When display panel  130  is required to display imperceptible changes between images, processing unit  323  stores the processed result in storage capacitor  312  or  332  according to control signal group S G2 . 
         [0024]    Initially, source driver  220  provides original data signals to sub-pixels, the processing unit subsequently processes the original data signals to generate a new data signal and provides the processed result (new data signal) to the corresponding sub-pixel. Because source driver  220  does not repeatedly provide data signals, the power consumption is reduced. 
         [0025]      FIG. 4  is a schematic diagram of an exemplary embodiment of a processing unit. Processing unit  323  comprises a sample-hold device  410 , an inverter  420 , and a control device  430 . 
         [0026]    Sample-hold device  410  latches voltage stored in storage capacitor  322  to generate a latch signal S L1  according to a control signal C 1  of the control signal group S G2 . In this embodiment, sample-hold device  410  comprises a transistor  411  and a capacitor  412 . Transistor  411  is an N type transistor and is connected to capacitor  412  in series between data line D 1  and control device  430 . 
         [0027]    Inverter  420  inverts the latch signal S L1  to generate an inverted signal S IL1  according to a control signal C 2  of the control signal group S G2 . In this embodiment, inverter  420  comprises transistors  421  and  422 . Transistors  421  and  422  are N type transistors and connected in series between data line D 1  and control device  430 . 
         [0028]    Control device  430  transmits the inverted signal S IL1  to storage capacitor  312  or  322  according to a control signal C 3  of the control signal group S G2 . In this embodiment, control device  430  comprises transistor  431  and  432 . Transistor  431  is an N type transistor and transistor  432  is a P type transistor. 
         [0029]    Because the source and the drain of a transistor are determined according to the direction of the current, the two terminals of the transistor are referred to source/drain and drain/source. Transistor  431  comprises a gate receiving the control signal C 3 , a drain/source coupled to storage capacitor  312 , and a source/drain coupled to inverter  420 . Transistor  432  comprises a gate receiving the control signal C 3 , a drain/source coupled to storage capacitor  322  and sample-hold device  410 , and a source/drain coupled to the source/drain of transistor  431 . 
         [0030]    When the control signal C 3  is high, the inverted signal S IL1  is transmitted to storage capacitor  312 . When the control signal C 3  is low, the inverted signal S IL1  is transmitted to storage capacitor  322 . In this embodiment, the control signals C 1  and C 2  are the same. 
         [0031]      FIG. 5  is a schematic diagram of another exemplary embodiment of a processing unit.  FIG. 5  is similar to  FIG. 4  with the exception that a sample-hold device  510  directly connects to an inverter  520 . Because the operating principle of sample-hold devices  410 ,  510 , and  540  is identical, description of sample-hold devices  510  and  540  is omitted. Because the operating principle of inverters  420 ,  520 , and  550  is identical, description of inverters  520  and  550  is omitted. Because the operating principle of control devices  430 ,  530 , and  560  is identical, description of control devices  530  and  560  is omitted. 
         [0032]    Assuming that the level of one control signal is high or low, the corresponding device is activated or deactivated.  FIG. 6  is a timing diagram of control signals. In this embodiment, because control signals C 1  and C 2  are high with a predetermined sequence and control signal C 3  is low, sample-hold device  510  and inverter  520  process voltage stored in storage capacitor  322  for generating an inverted signal S IL1 . Additionally, sample-hold device  540  and inverter  550  process voltage stored in storage capacitor  332  for generating an inverted signal S IL2 . 
         [0033]    Processing unit  323  transmits the inverted signal S IL1  to storage capacitor  312 ,  322 , or  332  according to the control signals C 1 ˜C 3 . Additionally, processing unit  333  transmits the inverted signal S IL2  to storage capacitor  322  or  332  or a next storage capacitor (not shown) according to the control signals C 1 ˜C 3 . 
         [0034]    For example, if control signal C 3  is continuously low, processing unit  323  transmits the inverted signal S IL1  to storage capacitor  322  and processing unit  333  transmits the inverted signal S IL2  to storage capacitor  332 . If control signal C 3  changes from low to high, processing unit  323  transmits the inverted signal S IL1  to storage capacitor  312  and processing unit  333  transmits the inverted signal S IL2  to storage capacitor  322 . 
         [0035]    If control signals C 1  and C 3  are high and control signal C 2  is low, sample-hold device  510  receives voltage stored in storage capacitor  312  and sample-hold device  540  receives voltage stored in storage capacitor  322 . When control signal C 2  are high and control signals C 1  and C 3  is low, sample-hold device  510  and inverter  520  process voltage stored in storage capacitor  312  to generate the inverted signal S IL1  and subsequently stores the inverted signal S IL1  in storage capacitor  322 . Similarly, sample-hold device  540  and inverter  550 , process voltage stored in storage capacitor  322  to generate the inverted signal S IL2  and subsequently stores the inverted signal S IL2  in storage capacitor  332 . 
         [0036]    As discussed above, processing unit processes the voltage stored in the corresponding storage capacitor and transmits the processed result to the previous or the next storage capacitor according to the control signal group. For example, processing unit  323  processes the voltage stored in the storage capacitor  322  and transmits the processed result to the previous storage capacitor  312  or the next storage capacitor  332  according to the control signal group S G2 . 
         [0037]    If the voltage is transmitted to the previous storage capacitor, a last sub-pixel comprising the next storage capacitor is disposed in a non-display region and other sub-pixels are disposed in a display region. The non-display region is not capable of displaying images and the display region is capable of displaying images. Taking  FIG. 3  as an example, when the processing unit transmits the processed result to the previous storage capacitor, sub-pixel P 1n  is disposed in the non-display region and sub-pixels P 11 ˜P 1(n-1)  are disposed in the display region. When the processing unit transmits the processed result to the next storage capacitor, sub-pixel P 11  is disposed in the non-display region and sub-pixels P 12 ˜P 1n  are disposed in the display region. When the processing unit transmits the processed result to the previous or the next storage capacitor, sub-pixels P 11  and P 1n  are disposed in the non-display region and sub-pixels P 12 ˜P 1(n-1)  are disposed in the display region. 
         [0038]    When imperceptible changes occur between images, the processing unit processes the voltage stored in the corresponding storage capacitor and transmits the processed result to the previous or the next storage capacitor. If the images displayed in the display panel are the same, the processing unit transmits the processed result to the corresponding storage capacitor. The source driver initially provides original data signals to all sub-pixels and the processing unit subsequently processes the original data signals to generate new data signals, thus, power consumption is reduced. 
         [0039]    While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.