Abstract:
A speech decoder having a muting circuit which mutes the output of decoded speech when either the accumulated number of error-correcting codes corrected or the number of error-detecting codes detected within a received signal frame exceeds the set threshold value. Because that part of the decoded speech which fails to meet a reference level is suppressed, noise is eliminated from the decoded speech.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a speech codec which decodes an error-corrected signal (frame-structured received signal) in order to output decoded speech. 
     2. Description of the Prior Art 
     FIG. 1 is a block diagram showing a prior art speech codec. In the figure, reference numeral 1 is a received signal; numeral 2 is an error-corrected signal output from an error correcting circuit after error correction, indicated later; numeral 3 is decoded speech obtained by decoding the error-corrected signal 2; numeral 41 is the above-mentioned error correcting circuit, and numeral 12 is a speech decoding circuit. 
     In operation, the error correcting circuit 41 decodes error-correcting codes in the received signal 1 so as to correct or detect any errors that may have occurred during transmission. The circuit 41 then outputs the error-corrected signal 2. The speech decoding circuit 12 decodes the error-corrected signal 2 to output the decoded speech 3. 
     Constructed as described above, prior art speech codecs have a drawback that, when the number of transmission errors in the received signal 1 exceeds the correcting capacity of error-correcting codes, wrong corrections and uncorrected errors which result cause the decoded speech 3 to contain noise. 
     SUMMARY OF THE INVENTION 
     It is therefore the principal object of the present invention to provide a speech codec that eliminates the above-described problem of prior art speech codecs, that is, to remove said noise from the decoded speech. 
     According to a first aspect of the present invention, there is provided a speech codec in which a correcting and decoding means decodes error-correcting codes in a received frame-structured signal, detects any transmission errors therein, corrects them if they are correctable, and decodes the error-corrected signal to provide a decoded speech. Meanwhile, accumulators are provided to calculate the number of the error-correcting codes corrected in a frame of the received signal as well as the number of error-detecting codes detected therein. These counts are compared with the corresponding threshold values by comparators. The results are used by a muting circuit to mute the decoded speech from the correcting and decoding means as needed. 
     According to a second aspect of the present invention, there is provided a speech codec in which upon detecting a starting position of a frame by using a frame-synchronizing code in a received signal, a threshold value inserting circuit substitutes a threshold value for the frame-synchronizing code bits in the frame-structured received signal, so that the comparators can extract threshold values to be used therein from the frame of the received signal. 
     The above and other related objects and features of the invention, as well as the novelty thereof, will clearly appear from the following description and from the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a prior art speech codec; 
     FIG. 2 is a block diagram of a speech codec according to the first aspect of the present invention; 
     FIG. 3 is a block diagram of a speech codec according to the second aspect of the present invention; and 
     FIG. 4 is a view showing the formats of signals at several points indicated in FIG. 3. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     There will now be described preferred embodiments of the present invention by referring to the accompanying drawings. FIG. 2 is a block diagram showing the architecture of a preferred embodiment according to the above-described first aspect of the invention. In the figure, reference numeral 1 is a received signal; numeral 2 is an error-corrected signal; numeral 3 is decoded speech; numeral 4 is speech output; numeral 5 is a frame timing signal that is input for every received signal; numeral 11 is an error correcting circuit; numeral 12 is a speech decoding circuit; numerals 13 and 14 are each an accumulator; numerals 15 and 16 are each a comparator; numerals 17 and 18 are threshold value setting circuits which set threshold values for the number of error-correcting codes corrected and for the number of error-detecting codes detected, respectively, and illustratively made up of switches; numeral 19 is a muting circuit that mutes the decoded speech output from the comparators 15 and 16 as needed; reference character A is a correcting and decoding means; character B is an accumulating means; and character C is a comparing means. 
     In operation, the error correcting circuit 11 decodes error-correcting codes in the received signal 1 and detects any errors therein. After correcting transmission errors that are detected and found correctable, the circuit 11 outputs the error-corrected signal 2. At this time, the number of the error-correcting codes corrected and the number of the error-detecting codes detected are accumulated respectively by the accumulators 13 and 14 of the accumulating means B. These accumulators, which are reset by the frame timing signal 5, calculate the number of the error-correcting codes corrected and the number of the error-detecting codes detected within the frame of the received signal respectively. The results are compared by the comparators 15 and 16 of the comparing means C with the threshold values set up by the threshold value setting circuits 17 and 18. When the number of the corrected error-correcting codes or of the detected error-detecting codes exceeds the corresponding threshold value, the muting circuit 19 mutes the decoded speech 3 coming from the speech decoding circuit 12. That is, the speech output 4 is inhibited or suppressed. 
     FIG. 3 is a block diagram showing a preferred embodiment according to the above-described second aspect of the invention. In the figure, reference numeral 1 is a received signal; numeral 2 is an error-corrected signal; numeral 3 is decoded speech; numeral 4 is speech output; numeral 5 is a frame timing signal; numeral 6 is a received signal with threshold values inserted therein; numeral 21 is a threshold value inserting circuit which inserts into the received signal 1 the threshold values established by threshold value setting circuits 17A and 18A, as pointed out later; numeral 11 is an error correcting circuit; numeral 22 is a threshold value separating circuit; numeral 12 is a speech decoding circuit; numerals 13 and 14 are accumulators; numerals 15 and 16 are comparators; numerals 17A and 18A are the above-mentioned threshold value setting circuits; numeral 19 is a muting circuit; and reference character D is a correcting and decoding means. 
     In operation, the frame-structured received signal 1 contains frame-synchronizing code bits that indicate the beginning of each frame. By use of the frame-synchronizing code bits, the frame timing signal 5 is extracted from the signal and the beginning of the frame is determined accordingly. Then the frame-synchronizing code bits become unnecessary. At this time, the frame-synchronizing code bits in the received signal are replaced with the threshold values set by the threshold value setting circuits 17A and 18A. The resulting signal is sent to the error correcting circuit 11. The circuit 11 decodes the error correcting codes of the received signal 6 with the threshold values inserted therein, corrects or detects the transmission errors, and outputs the error-corrected signal 2. At this stage, the number of the error-correcting codes corrected and that of the error-detecting codes detected are accumulated by the accumulators 13 and 14 of the accumulating means B respectively. These accumulators, which are reset by the frame timing signal, calculate the number of the error-correcting codes corrected and that of the error-detecting codes detected within the frame respectively. Meanwhile, the threshold value separating circuit 22 separates the inserted threshold values from the error-corrected signal 2. The results are input to the comparators 15 and 16 for comparison with the predetermined threshold values. When either the number of the error-correcting codes corrected or the number of the error-detecting codes detected exceeds the corresponding threshold value, the muting circuit 19 mutes the decoded speech 3 coming from the speech decoding circuit 12. That is, the speech output 4 is inhibited or suppressed. 
     FIG. 4 depicts the relationships among the signal 1 received by the threshold value inserting circuit 21, the received signal 6 with threshold values inserted therein, and the error-corrected signal 2. 
     As described above, according to the first and the second aspects of the present invention, there is provided a speech codec adapted to mute the decoded speech when the number of the error-correcting codes corrected or the numbers of error-detecting codes detected in each frame exceeds the corresponding threshold value determined in advance. In this manner, the speech codec can eliminate noise from its speech output.