Abstract:
A synchronous rectifier, including an energy storage element having a terminal; a power supply input, connected to the terminal of the storage element in a first time interval; a reference line connected to the terminal of the storage element in a second time interval; and a zero comparator, coupled to the terminal of the storage element to detect a current flowing in the energy storage element and disconnect the terminal of the storage element from the reference line upon detecting a zero current, the zero comparator having an offset and a propagation time; the zero comparator further having an offset control input and an output. An offset regulating loop is coupled between the output of the zero comparator and the offset control input and regulates the offset of the zero comparator to compensate the propagation time.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a synchronous rectifier, in particular, but not exclusively, for use in mobile applications. 
         [0003]    2. Discussion of the Related Art 
         [0004]    As known, mobile applications require high-efficiency synchronous rectifiers, having precise on/off switching times, where a diode that dissipates most of the power. Such applications include particularly Switched Mode Power Supplies (SMPS) of all topologies. In the following, reference will be made to a step down (buck) converter, although the invention is not limited thereto, but can be used in any application where rectification efficiency is needed. 
         [0005]    A typical buck converter  1  is shown in  FIG. 1 . The buck converter  1  comprises an inductor L storing energy from a power supply V CC  (for example a battery) and transferring the stored energy to an output node OUT; a switch T 1 , here a PMOS transistor, for connecting the power supply V CC  to a first terminal of the inductor L (node LX between the inductor L and the switch T 1 ) during a charging step and disconnecting the inductor L from the power supply V CC  during an energy transfer step; a freewheeling diode D, connecting the first terminal of the inductor L to ground and allowing recirculation of the inductor current I L  during the energy transfer step; an output capacitor CO connected to the output node OUT (second terminal of the inductor L) for filtering an output voltage V O ; a second switch T 2 , here an NMOS transistor, connected in parallel to the diode D; a feedback circuit including an integrator (error amplifier) EA and a first comparator Comp 1 , connected to the output node OUT; and a logic circuit  5  receiving an output signal of the feedback circuit, Comp 1  and generating a first and a second control signals s 1 , s 2  for, respectively, the first and second switches T 1 , T 2 . In a known manner, integrator EA receives the output voltage V O  and a reference voltage V REF  and generates an error signal e fed to the first comparator Comp 1 ; first comparator Comp 1  also receives a saw-tooth signal and generates a duty-cycle signal s 3  used by logic circuit  5  to drive switches T 1  and T 2 . 
         [0006]    In the simplest implementation, NMOS transistor T 2  is not necessary and the conduction of the recirculation current is carried out by diode D. The disadvantage in using only diode D resides in the large power loss when diode D is forward biased (i.e., during the freewheeling period). In particular, the power losses P are approximately given by: 
         [0000]    
       
         
           
             P 
             = 
             
               
                 1 
                 T 
               
                
               
                 
                   ∫ 
                   
                     t 
                     1 
                   
                   
                     t 
                     2 
                   
                 
                  
                 
                   
                     V 
                     FD 
                   
                    
                   
                     I 
                     L 
                   
                    
                   
                       
                   
                    
                   
                      
                     t 
                   
                 
               
             
           
         
       
     
         [0007]    wherein: 
         [0008]    1/T is the working frequency of the converter  1 ; 
         [0009]    t 2 −t 1  is the conduction time of the diode D; 
         [0010]    I L  is the current through the inductor L (equal to the diode current in the recirculation step); 
         [0011]    and V FD  is the diode forward voltage. 
         [0012]    Since Schottky diodes have a lower forward voltage as compared to PN diodes, they are preferred and allow an improvement of the recirculation losses by a factor of two. 
         [0013]    A further improvement is obtained through NMOS transistor T 2 , which can be driven so as to have a very low voltage drop. NMOS transistor T 2  is controlled by control signal s 2  so as to be on only during the recirculation step, as explained in greater detail hereinafter, with reference to the plots of  FIG. 2 .  FIG. 2  show the behavior of the current I L  flowing through the inductor L and of the voltage V LX  on node LX in case of a small load connected to the output OUT of the converter  1 . 
         [0014]    Initially, at time to, PMOS transistor T 1  is switched on and connects node LX to the power supply V cc ; NMOS transistor T 2  is off. Thus the inductor current I L  rises linearly with a slope SL: 
         [0000]        SL =( V   cc   −V   O )/ L    
         [0015]    wherein L is the inductance of the inductor L. 
         [0016]    At time t 1 , determined by the feedback circuit EA, Comp 1 , PMOS transistor T 1  is switched off and NMOS transistor T 2  is switched on. Thereafter, neglecting the negative spike due to the switching-on time of the NMOS transistor T 2 , voltage V LX  is equal to the voltage drop across NMOS transistor T 2  and depends on the resistance R DSon  of the NMOS transistor T 2  and the recirculation current I L , as follows: 
         [0000]        V   LX =−( R   DSon   *I   L ).  (1) 
         [0017]    When inductor current I L  reaches zero (time t 2 ), neglecting a negative spike due to the switching-off time of the NMOS transistor T 2 , voltage V LX  becomes equal to the output voltage V O , in turn equal to the reference voltage V REF . 
         [0018]    In this circuit, the correct timing of both turning-on and turning-off of the NMOS transistor T 2  is critical. In fact:
       if NMOS transistor T 2  is turned on too early, some charging current flows from the power supply to ground, causing undesired power consumption and reduction in efficiency;   if NMOS transistor T 2  is turned on too late or is turned off too early, part of the recirculation current flows through the diode D, causing large losses on the same;   if NMOS transistor T 2  is turned off too late, the inductor current I L  reverses and reduces the overall efficiency.       
 
         [0022]    There are very different design requirements for the logic circuit  5  managing the turn on and turn off control signals s 1 , s 2 . For example, the design requirements are dictated by the operation mode, i.e., whether the step-down converter  1  is operated in Pulse Width Modulation PWM mode or in Pulse Frequency Modulation PFM mode. In fact, the PFM mode is totally asynchronous, thus preventing the use of any solution based on periodic clocking. 
         [0023]    However, ideally, the design should cover both operation modes, that is any type of Discontinuous Conduction Mode DCM. 
         [0024]    Hereinafter, in particular the problem of exactly determining the switching-off instant of the NMOS transistor T 2  will be addressed. 
         [0025]    As indicated, the NMOS transistor T 2  should be ideally switched off when the current I L  through the inductor L exactly reaches the zero value. According to a possible solution, shown in  FIG. 3 , the current I L  through the inductor L is sensed by a sense resistor R s  arranged in series to the NMOS transistor T 2  and diode D. The voltage across the sense resistor R s  is detected by a second comparator Comp 2  which generates a suitable signal Z when current I L  reaches zero. Signal Z is fed to the logic circuit  5  to cause switching off of the NMOS transistor T 2 . 
         [0026]    In this solution, the resistance of the sense resistor R 3  should satisfy conflicting requirements. In fact, the larger the resistance, the higher the current-to-voltage gain and thus the accuracy of the second comparator Comp 2 . However, the larger the resistance, the larger the losses on the sense resistor R s . Thus such a solution is not suitable for high efficiency applications. 
         [0027]    According to a different solution, the resistive behavior of the NMOS transistor T 2  is exploited, as shown in  FIG. 4 . In fact, according to (1), during the energy transfer step, NMOS transistor T 2  has a voltage drop proportional to its R DSon , which can be used for detecting the inductor current. In this case, a zero comparator ZComp has a first input connected to node LX, a second input connected to ground, and an output supplying a zero signal Z C  and connected to the logic circuit  5 . 
         [0028]    R DSon  has a very low value (of about 100 mΩ), which puts extreme requirements on the zero comparator ZComp in terms of input offset and propagation delay. 
         [0029]    In fact, the attainable input offset is greater than the quantity to be measured. This is clear from consideration of the plots  FIGS. 5   a  and  5   b .  FIG. 5   a  shows an enlarged portion of the current I L  and the voltage V LX  near time t 2  (neglecting the voltage spike).  FIG. 5   b  shows a typical distribution of the comparator offset of a CMOS process usable for the intended application. In particular, for an inductor current I L =10 mA, assuming R DSon =100 mΩ, V LX =1 mV. Typical matching characteristics of a CMOS process give an offset comprised in a ±8 mV range. Therefore the zero comparator ZComp should measure a 1 mV voltage with a ±8 mV accuracy. This is not possible, since a 8 mV offset may cause the zero comparator ZComp to generate the zero signal Z C  and thus switching off of the NMOS transistor T 2  while 80 mA are still flowing through the inductor L. Considering that the peak value of the inductor current I L  may be comprised between 100 and 150 mA, the synchronous rectifier would be inefficient for most of the time. 
         [0030]    A source of error also lies in the propagation time, that is the time needed by the zero comparator ZComp to generate the zero signal Z C  after detecting the zero condition (also called decision time). As known, the propagation time also depends on the voltage level at the input of the zero comparator ZComp. A low voltage level causes the decision time of the zero comparator ZComp to dramatically extend. For example, a zero comparator driven with a 1V/μs triangular waveform may have a decision time of 8 ns, while the same comparator drive with a 1 μV/μs has a 45 ns decision time. Since the inductor current slope SI L  for an output voltage V O =2V and an inductance L=4.7 μH is: 
         [0000]        SI   L =( V   LX   −V   O )/ L≈− 2 V/4.7 μH≈−0.4 A/μs 
         [0000]    the propagation delay may cause the NMOS transistor T 2  to switch off when the inductor current reaches −0.4 A/μs*45 ns=−18 mA. Such a reverse current in the inductor L is not acceptable. 
       SUMMARY OF THE INVENTION 
       [0031]    An aspect of the invention provides a synchronous rectifier operating in an accurate and efficient way in spite of the above discussed problems of offset and propagation time. 
         [0032]    According to one embodiment of the present invention, there is provided a synchronous rectifier, comprising an energy storage element having a terminal; a power supply input, connected to the terminal of the storage element in a first time interval; a reference line connected to the terminal of the storage element in a second time interval; a zero comparator, coupled to the terminal of the storage element to detect a current flowing in the energy storage element and disconnect the terminal of the storage element from the reference line upon detecting a zero current, the zero comparator having an offset and a propagation time; the zero comparator further having an offset control input and an output; and an offset regulating loop coupled between the output of the zero comparator and the offset control input and regulating the offset of the zero comparator to compensate the propagation time. 
         [0033]    According to another embodiment of the present invention, there is provided a method for controlling switching of a synchronous rectifier comprising an energy storage element, comprising connecting a terminal of the energy storage element to a power supply input in a first time interval; connecting the terminal of the energy storage element to a reference line in a second time interval; detecting a current flowing in the energy storage element using a zero comparator having an offset and a propagation time; disconnecting the terminal of the energy storage element from the reference line upon detecting a zero current in the energy storage element; the method further comprising regulating the offset of the zero comparator to compensate the propagation time. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0034]    For the understanding of the present invention, a preferred embodiment thereof is now described, purely as a non-limitative example, with reference to the enclosed drawings, wherein: 
           [0035]      FIG. 1  is a schematic diagram of a known buck converter; 
           [0036]      FIG. 2  shows the plot of electric quantities in the circuit diagram of  FIG. 1 ; 
           [0037]      FIG. 3  is a schematic diagram of a buck converter including a first zero detection circuit; 
           [0038]      FIG. 4  is a schematic diagram of a buck converter including a different zero detection circuit; 
           [0039]      FIGS. 5   a  and  5   b  show plots of some quantities for the circuit of  FIG. 4 ; 
           [0040]      FIG. 6  shows a schematic diagram of a buck converter including a compensated zero detection circuit according to an embodiment of the invention; 
           [0041]      FIGS. 7-9  show different timing diagrams for the circuit of  FIG. 6  in three different conditions; 
           [0042]      FIG. 10  shows the transfer function of the compensated zero detection circuit of  FIG. 6 ; 
           [0043]      FIGS. 11 and 12  are circuit schemes of two components of the diagram of  FIG. 6 ; and 
           [0044]      FIG. 13  shows the truth table for the logic circuit of  FIG. 12 . 
       
    
    
     DETAILED DESCRIPTION 
       [0045]      FIG. 6  shows an embodiment of a buck converter  10  having the basic structure shown in  FIG. 1  (and thus not described any more) and including a compensated zero detection circuit  20 . Zero detection circuit  20  comprises a timing detector  21 ; a charge pump  22 ; a filter  23  and an offset-controlled comparator  24 , representing a zero comparator. 
         [0046]    Offset-controlled comparator  24  (an embodiment whereof is shown in  FIG. 11 ) has a first input connected to node LX, a second input connected to ground, an output connected to logic circuit  5  and an offset regulation input  24   a.    
         [0047]    Timing detector  21  (an embodiment whereof is shown in  FIG. 12 , including also the scheme of the logic circuit  5 ), has a first input connected to the gate of the NMOS transistor T 2 , a second input connected to the output of the offset-controlled comparator  24 , a first output supplying a first digital signal UP and a second output supplying a second digital signal DOWN. Charge pump  22  comprises an upper current source  25  and a lower current source  26  connected in series between power supply V CC  and ground. Upper and lower current sources  25 ,  26  are of a switcheable type and receive respectively the first and the second digital signals UP and DOWN so as to be switched on/off alternatively and in counter-phase. 
         [0048]    An intermediate node  27  between the upper and the lower current sources  25 ,  26  is connected to the offset regulation input  24   a  of the offset-controlled comparator  24 . 
         [0049]    Filter  23  comprises an integration capacitor arranged between intermediate node  27  and ground. 
         [0050]    The compensated zero detection circuit  20  automatically adjusts the offset voltage Voff of the offset-controlled comparator  24  through the charge pump  22  so as to compensate the (constant but unknown) propagation time Δt thereof and cause the NMOS transistor T 2  to switch off when the inductor current I L  is nearly zero. Thereby, the conduction time of the diode and thus the power loss is reduced to a minimum. 
         [0051]    The operation of the compensated zero detection circuit  20  of  FIG. 6  will now be described with reference to  FIG. 7 , showing the plot of some quantities and signals in a balanced condition of the compensated zero detection circuit  20 , starting from an intermediate portion of the recirculation step, between instants t 1  and t 2  of the  FIG. 2  plot. 
         [0052]    In this interval, as above discussed, the inductor current I L  is decreasing linearly and the voltage V LX  is increasing linearly (due to the resistive behavior of the NMOS transistor T 2 ) and is in the range of a few mV. 
         [0053]    At time t 3  the voltage V LX  becomes equal to the offset voltage Voff of the offset-controlled comparator  24 , causing the switching of the zero signal Z C  to high; thus, the logic circuit  5  causes the second control signal s 2  to switch to low and the NMOS transistor T 2  to turn off (instant t 4 ). Consequently, the inductor current I L  starts flowing through the diode D and voltage V LX  drops to −V FD , due to the diode forward voltage. 
         [0054]    The decrease of the voltage V LX  below the offset voltage Voff is detected by the offset-controlled comparator  24 , whose output signal (zero signal Z C ) is forced back to zero (time t 5 ). The falling edge of the zero signal Z C  is detected by the timing circuit  21  which turns on the first digital signal UP, causing turning on of the respective first current source  25 . 
         [0055]    In the meantime, the inductor current I L  reaches the zero value (time t 2 ), turning off the diode D; thus, voltage V LX  instantly raises to the output voltage V O . Therefore, zero signal Z C  switches again to high; this time, the propagation delay of the offset-controlled comparator  24  is negligible because the input voltage swing is of the order of volts. 
         [0056]    The second leading edge of the zero signal Z C  is detected by the timing circuit  21 , which forces the first digital signal UP to low and the second digital signal DOWN to high, thus turning off first current source  25  and turning on second current source  26 . After a delay, the second digital signal DOWN is forced to low by the falling edge of delayed control signal DS 2 , which is a delayed replica of the second control signal s 2 . 
         [0057]    During interval t 5 −t 6 , the current (positive or negative) generated by the charge pump  22  is fed to the filter  23  that integrates it and generates an offset control voltage VC supplied to the offset regulation input  24   a  of the offset-controlled comparator  24 , thus regulating the offset thereof so as to compensate the propagation time Δt. 
         [0058]    In particular, the compensated zero detection circuit  20  represents a closed loop that regulates the on/off times of the first and second current sources  25 ,  26  to be equal. Thus, when the compensated zero detection circuit  20  is in equilibrium, the length of the pulses of the digital signals UP and DOWN is equal. The NMOS transistor T 2  does not actually turn off when the inductor current is zero, but, in the balanced condition of the compensated zero detection circuit  20 , it turns off a small time before the zero crossing (advance time Δt 1 ), which is built-in into the timing detector  21 , as explained in more detail later on. Thus, the delay between the control signal s 2  and the delayed control signal Ds 2  is chosen to be twice the advance time at equilibrium (2Δt 1 ). For example, for a delay 2Δt 1  between the second control signal s 2  and the delayed control signal Ds 2  of 40 ns (and thus an equilibrium advance time Δt 1 =20 ns), the inductor current is: 
         [0000]        I   L =−0.4 mA/ns*(−20 ns)=8 mA, 
         [0000]    which is much smaller than according to the prior art. 
         [0059]    In fact, the above value is a worst-case scenario because the second rising edge of the zero signal Z C  has a propagation delay with respect to time t 2  which is smaller than Δt, but such as to push the actual switch off time of the NMOS transistor T 2  closer to the ideal one. 
         [0060]    As indicated above, in an unbalanced condition, the duration of the UP and DOWN pulses is automatically controlled, as shown in  FIGS. 8 and 9 . 
         [0061]    In detail,  FIG. 8  refers to a situation where the offset voltage Voff_e is lower than the balanced value Voff. In such a condition, the zero detector  24  detects the zero crossing at time t 3 ′, earlier than time t 3  by Δt 2 , and the first switching of the zero signal Z C  occurs also earlier, at time t 4 ′. Since time t 2  (when the inductor current I L  reaches the zero value and the second digital signal DOWN is forced to the high level) does not change, but time t 6 ′ (end of the DOWN pulse) occurs earlier (also by Δt 2 ), this cause the first digital signal UP to be much longer and the second digital signal DOWN to be much shorter than in the balanced situation. Therefore upper current source  25  is activated for a longer time than lower current source  26 , causing an increase in the offset control voltage VC and thus an increase in the offset voltage Voff_e to bring it nearer to the balanced condition. 
         [0062]    Analogously, if the actual offset voltage (Voff_d) is too high, as shown in the plots of  FIG. 9 , zero crossing detecting occurs at t 3 ″, later than t 3  by Δt 3 , the rising edge of the first digital signal UP occurs at t 4 ″, the falling edge of the first pulse of the zero signal Z C  occurs at t 5 ″; thus the second digital signal DOWN is much longer than the first digital signal UP, causing a reduction in the offset voltage Voff_d toward the balanced condition. 
         [0063]    If the initial timing error is so large that the NMOS transistor T 2  turns off after the zero crossing of the inductor current I L  (not shown), that is when the inductor current has reversed, the voltage V LX  does not become negative and consequently there is only one rising edge of the zero signal Z C . The first digital signal UP has no pulses and the second digital signal DOWN has a constant length. This behavior inserts a non-linearity into the timing detector  21 . Similarly, a large negative timing error results in the first digital signal UP whose falling edge may occur after the falling edge of the delayed control signal DS 2  will be longer than the delayed control signal DS 2 , due to the early switching of the second control signal s 2 ; thus no second digital signal DOWN may be generated. In this case, the gain timing detector is reduced to a half, because the length of the pulse of the first digital signal UP is always proportional to the timing error. 
         [0064]    The above behavior is visible in  FIG. 10 , wherein te is the timing error, I AV  is the average current supplied by the current sources  25 ,  26 , EP is the equilibrium point, region B is the equilibrium region, region C is the non-linear region where no UP pulse is generated, region A is the non-linear region where no DOWN pulse is generated, Δt 1  is the equilibrium advance time and 2Δt 1  is the delay between control signal s 2  and delayed control signal DS 2 . 
         [0065]      FIGS. 12 and 13  show an embodiment of the timing detector  21  and its operation, wherein delay element  30  introduces a delay of 2Δt 1 . In this circuit, a short pulse is present on the second digital signal DOWN before the pulse of the first digital signal UP; however it does not impair the operation of the circuit. In fact, such a short pulse is integrated by the loop filter and just causes a small timing shift of the equilibrium point. 
         [0066]    The advantages of the present invention are clear from the above. In particular, the described synchronous rectifier ensures a timely switching of the NMOS transistor, reducing to a minimum conduction time of the diode D and thus the losses caused by the latter. 
         [0067]    Furthermore, the voltage of the filter  23  does not change with the load nor with the operation mode (PWM or PFM) of the circuit; thus the circuit of  FIG. 6  operates reliably and reproducibly in different conditions. 
         [0068]    Finally, it is clear that numerous variations and modifications may be made to the synchronous rectifier described and illustrated herein, all falling within the scope of the invention as defined in the attached claims. In particular, it is stressed that the present invention is applicable to synchronous rectifiers of any type, not limited to the described topology or application; and the circuits of  FIGS. 11 and 12  are only representative of possible solution, without the invention being limited thereto. 
         [0069]    Having thus described at least one illustrative embodiment of the invention, various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only and is not intended as limiting. The invention is limited only as defined in the following claims and the equivalents thereto.