Abstract:
A data transfer device having a post charge logic circuit which utilizes signals on a pair of data lines performs a post charge operation on the other a plurality of data line pairs. A data transfer device uses only signals on a pair of data lines to perform the post charge operation to the other data lines, thereby reducing the area of the memory device.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a data transfer device with a post charge logic. In particular, it relates to a data transfer device with a post charge logic, which initializes data lines in a memory device after data is transferred. 
     2. Description of the Prior Art 
     In general, a post charge operation is to initialize data lines by using the signals transferred on the data lines, after a data receiving circuit has received data outputted from a data transferring circuit through the data lines. 
     FIG. 1 represents a circuit diagram of a conventional data transfer device with a post charge logic circuit. In the diagram, each of the data bus sense amplifiers  10  and  40  is coupled to the corresponding receiving parts  20  and  50  through corresponding data line pairs DL 1 , DL 2  and DL 3 , DL 4 . 
     The data bus sense amplifiers  10  and  40  transfer high/low level data to the receiving part  20  and  50  through the corresponding data line pairs DL 1 , DL 2  and DL 3 , DL 4 . This is conducted by controlling the data driving elements N 1 , N 2 , N 3 , and N 4  provided between the data lines DL 1 , DL 2 , DL 3 , and DL 4  and ground voltage. 
     As shown in FIG. 1, post charge logic circuits  30  and  32  are provided on the data line pair DL 1  and DL 2  to initialize the data lines after the data has been transferred from the data bus sense amplifier  10  to the data lines. Post charge logic circuits  60  and  62  are provided on the data line pair DL 3  and DL 4  to initialize the data lines after the data has been transferred from the data bus sense amplifier  40  to the data lines. 
     The post charge logic circuit  30  comprises an inverter circuit  30   a  for receiving data on the data line DL 1 , delay circuit  30   b  for delaying the output signal from the inverter  30   a  for a predetermined time, an inverter circuit  30   c  for receiving the output signal from the delay circuit  30   b,  and a switching element P 1  (wherein P 1  is a PMOS transistor) for controlling the voltage level on the data line DL 1  in response to an output signal from the inverter  30   c.  The construction of the other post charge logic circuits  32 ,  60 , and  62  is identical with that of the post charge logic circuit  30 . 
     The operation of the conventional data trnsfer device with a post charge logic in consideration of the operations of the data bus sense amplifier and the receiving part will be expalined hereinafter in detail. 
     The operation which transfers high level data to the receiving parts will be illustrated. At the beginning, the voltage levels of the data lines DL_ 1 , and DL_ 2  are predetermined by a pheriperal circuit (not shown), and generally are set to a high level. When one (for example, N 1 ) of the data driving elements N 1  and N 2  is turned on in response to the output signal from the data bus sense amplifier  10 , the voltage level of the data line DL 1  is changed from a high level to a low level. 
     In the beginning, the PMOS transistor P 1  within the post charge logic circuit  30  is turned off until the data line DL 1  has changed from a high level to a low level, thus the voltage of the data line DL 1  is high level. When the voltage level of the data line DL 1  has changed to a low level, the PMOS P 1  will be turned on after a time lapse. 
     Therefore, the voltage level of the data line DL 1  is initialized in response to the turned on PMOS transistor P 1  after the signal of high data has been transferred to the receiving part. 
     On the contrary, the operation which transfers high level data to the receiving parts will be illustrated. At the beginning, the voltage levels of the data lines DL_ 1 , and DL_ 2  are predetermined by a pheriperal circuit (not shown), and generally are set to a high level. When one (for example, N 2 ) of the data driving elements N 1  and N 2  is turned on in response to the output signal from the data bus sense amplifier  10 , the voltage level of the data line DL 2  is changed from a high level to a low level. The PMOS transistor P 2  within the post charge logic circuit  32  is turned off until the data line DL 2  has changed from a high level to a low level, thus the voltage of the data line DL 2  is high level. 
     When the voltage level of the data line DL 2  has changed to a low level, the PMOS P 2  will be turned on after a time lapse. 
     Therefore, the voltage level of the data line DL 2  is initialized in response to the turned on PMOS transistor P 2  after the signal of high data has been transferred to the receiving part. 
     The operation of the other data bus sense amplifier  40  and receving part  50  is identicel with that of the data transfer device illustrated above. In general, there is a plurality of data bus sense amplifiers and receving parts in the data transfer device. 
     As shown in FIG.  1  and illustrated above, the conventional data transfer device comprises a plurality of post charge logic circuits, each of which is provided on the each data line, resulting in an increase in the power consumption and an increase in a layout area. 
     SUMMARY OF THE INVENTION 
     Accordingly, the present invention for resolving the above illustrated problems is directed to a data transfer device with a post charge logic circuit which performs a post charge operation to a plurality of data line pairs by using of the signals only one data line pair. 
     To achieve the above object, a data transfer device according to the present invention includes: a plurality of data transferring means; a plurality of data line pairs; a plurality of driving means connected between each of the data lines and ground voltage; a plurality of data receiving means connected to a plurality of driving means through a plurality of data line pairs; and a post charge logic means for receiving a pair of data onto a pair of data line pair of the plurality of data line pairs and for performing a post charge operation at all of the plurality of data line pairs. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Further objects and other advantages of the present invention will become apparent from the following description in conjunction with the attached drawings, in which: 
     FIG. 1 is a circuit diagram of a conventional data transfer device with a post charge logic circuit; 
     FIG. 2 is a circuit diagram of a data transfer device with a post charge logic circuit in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings. 
     FIG. 2 shows a circuit diagram of a data transfer device with a post charge logic circuit in accordance with the present invention. Each of the data driving elements N 1 , N 2 , N 3 , and N 4  (MOS transistors) is provided between the corresponding data lines DL_ 11 , DL_ 12 , DL_ 13 , and DL_ 14  and the ground voltage, and is operated by the output signal from the data transferring circuit ( 10 ,  40  : i.e., data bus sense amplifier). 
     The data lines DL_ 11 , DL_ 12 , DL_ 13 , and DL_ 14  are connected between the corresponding drains of the data driving elements and the corresponding gates of the PMOS transistors P 3 , P 4 , P 7 , and P 8  within the receiving parts  20  and  50 . The data lines transfer the data from the data transfer devices  10  and  40  to the receiving parts  20  and  50  by the turn on/off operation of a plurality of the data driving elements N 1 , N 2 , N 3 , and N 4 . 
     The post charge logic circuit  70  receives only the signals on one data line pair among a plurality of data line pairs DL_ 11 , DL_ 12  and DL_ 13 , DL_ 14  and intializes all the data line pairs. 
     The post charge logic circuit  70  comprises a NAND gate  70   a,  a delay circuit  70   b  for receiving the output signal from the NAND gate  70   a  and delaying it for a certain amount of time, an inverter circuit  70   c  for receving the output signal from the delay circuit  70   b,  and a plurality of PMOS transistors P 1 , P 2 , P 5 , and P 6  of which the gates for each transistor are connected to the output terminal of the inverter  70   c.    
     The input terminals of the NAND gate  70   a  are connected to the data lines DL_ 11 , DL_ 12 , so that the signals on the data lines are NAND operated by the NAND gate  70   a.    
     Each of the PMOS transistors P 1 , P 2 , P 5 , and P 6  is provided between the power supply voltage and the corresponding data lines DL_ 11 , DL_ 12 , DL_ 13  and DL_ 14 , and all of the gates of the transistors are connected to the output terminal of the inverter  70   c.  Thus, the voltage level of the data lines may be determined by the output signal from the inverter  70   c.    
     The operation of the data transfer device with the post charge logic in accordance with the present invention will be explained hereinafter. 
     First, the operation which transfers high level data to the receiving parts  20  and  50  will be illustrated. 
     In the beginning, the voltage levels of the data lines DL_ 11 , DL_ 12 , DL_ 13 , and DL_ 14  are predetermined by a pheriperal circuit (not shown), and generally are set at a high level. At this time, the status of the data driving elements N 1 , N 2 , N 3 , and N 4  is maintained in a turned off state. In this case, the data driving elements N 1  and N 3  are turned on and the data driving elements N 2  and N 4  are selectively turned off by the output signals from the data bus sense amplifiers  10  and  40 . Therefore, the voltage levels of the data lines DL_ 12  and DL_ 14  are maintained in a high level, and the voltage levels of the other data lines DL_ 11  and DL_ 13  will be changed from a high level to a low level. 
     The voltage level of the data lines DL_ 11  to DL_ 14  is maintained at a high level which is a initial voltage state until the voltage level of the data lines DL_ 11  and DL_ 13  have changed to a low level. Therefore, the NAND gate  70   a  within the post charge logic circuit  70  outputs a of high level signal, and the PMOS transistors P 1 , P 2 , P 5 , and P 6  are turned off by the high level output signal from the inverter  70   c.    
     From now on, when the voltage levels of the data lines DL_ 11  and DL_ 13  are changed to a low level, the PMOS transistor P 3  in a receiving part  20  and the PMOS transistor P 7  in a receiving part  50  are turned on. Thus, a high level signal is transferred to the receiving parts  20  and  50 . 
     In this way, when the voltage levels of the data lines DL_ 11  and DL_ 13  are changed to a low level, the output signal from the NAND gate  70   a  within the post charge logic circuit  70  is changed to a high level, and the PMOS transistors P 1 , P 2 , P 5 , and P 6  are ultimately turned on by the output signal from the inverter  70   c.  Thus, a high level signal is transferred to the receiving parts  20  and  50 , and the voltage levels of the data lines DL_ 11 , DL_ 12 , DL_ 13 , and DL_ 14  which are connected to the turned-on PMOS transistors P 1 , P 2 , P 5 , and P 6  are initialized again at high levels. 
     On the contrary to the above case, the operation which transfers low level data to the receiving parts  20  and  50  will be illustrated. 
     In the beginning, the voltage levels of the data lines DL_ 11 , DL_ 12 , DL_ 13 , and DL_ 14  are predetermined by a pheriperal circuit (not shown), and generally are set at a high level. At this time, the status of the data driving elements N 1 , N 2 , N 3 , and N 4  is maintained in a turned off state. In this case, the data driving elements N 2  and N 4  are turned on, and the data driving elements N 1  and N 3  are selectively turned off by the output signals from the data bus sense amplifiers  10  and  40 . Therefore, the voltage levels of the data lines DL_ 11  and DL_ 13  are maintained at a high level, and the voltage levels of the other data lines DL_ 12  and DL_ 14  will be changed from a high level to a low level. 
     The voltage level of the data lines DL_ 11  to DL_ 14  is maintained at a high level which is a initial voltage state until the voltage levels of the data lines DL_ 12  and DL_ 14  have been changed to low levels. Therefore, the NAND gate  70   a  within the post charge logic circuit  70  outputs a low level signal, and the PMOS transistors P 1 , P 2 , P 5 , and P 6  are turned off by the high level output signal from the inverter  70   c.    
     From now on, when the voltage levels of the data lines DL_ 12  and DL_ 14  are changed to a low level, the PMOS transistor P 4  in a receiving part  20  and the PMOS transistor P 8  in a receiving part  50  are turned on. Thus, a low level signal is transferred to the receiving parts  20  and  50 . 
     In this way, when the voltage levels of the data lines DL_ 12  and DL_ 14  are changed to a low level, the output signal from the NAND gate  70   a  within the post charge logic circuit  70  is changed to a high level, and the PMOS transistors P 1 , P 2 , P 5 , and P 6  are ultimately turned on by the output signal from the inverter  70   c.  Thus, a low level signal is transferred to the receiving parts  20  and  50 , and the voltage levels of the data lines DL_ 11 , DL_ 12 , DL_ 13 , and DL_ 14  which are connected to the turned-on PMOS transistors P 1 , P 2 , P 5 , and P 6  are initialized again at high levels. 
     As described above, in an operation of transferring data through data lines, the present invention conducts the post charge operation to a plurality of data lines by using the signals on the one pair of data lines, thereby reducing the area of the memory device. 
     It is understood that various other modifications will be apparent to and can be readily made by those skilled in the art without departing from the scope and spirit of this invention. Accordingly, it is not intended that the scope of the claims appended hereto be limited to the description as set forth herein, but rather that the claims be construed as encompassing all the features of a patentable novelty that reside in the present invention, including all features that would be treated as equivalents thereof by those skilled in the art to which this invention pertains.