Abstract:
An output of an element under test is captured and stored, through a multiplexer, in a capture register. At a clock edge (either rising or falling edge) the element under test catches the “edge” and “strobes” the output. The multiplexer is strobed, and the delay and duty cycle are measured. Both the rising and falling edge are used as the timer.

Description:
BACKGROUND  
       [0001]     1. Field of the Invention  
         [0002]     The invention relates to built in test circuitry having a clock duty cycle based access timer combined with standard stage clocked output register.  
         [0003]     2. Background Art  
         [0004]     When performing maximum frequency (f max) analysis on microprocessors, testers can simply increase the global clock frequency until the system fails. This does not give good insight into the maximum frequency or the maximum performance of the individual parts of the microprocessor or even the amount of guard band that is built into a microprocessor or integrated circuit. Increasing the frequency only tells you the f max of the slowest component.  
         [0005]     By way of exemplification, one such critical component is the SRAM and another such critical component is a logic unit.  
         [0006]     In addition to knowing the maximum sustainable frequency of the element, it is often important to know the true data access times of the elements on a chip.  
         [0007]     Elaborate clock choppers have been used in the past, but these circuits can be quite large and take up valuable real estate. In the case of a SRAM, such large circuitry would need to be placed outside of the SRAM macro. Placing such critical timing circuits away from the element under test will result in inaccurate timing results. Thus, a need exists for a more compact solution to track timing delays in circuit elements.  
       SUMMARY OF THE INVENTION  
       [0008]     According to the disclosed invention the output of the element under test is captured and stored in a capture register. Specifically, according to the invention described herein, a MUX (multiplexer) is used instead of the cumbersome built in delay clock of the prior art. The programmable delay associated with the delay clock is replaced with a MUX, and at a clock edge (either rising or falling edge) the grid (element under test) catches the “edge” and “strobes” the output. The MUX is strobed, and the delay and duty cycle are measured. Both the rising and falling edge are used as the timer.  
         [0009]     The invention involves changing the capture clock strobe timing of the output capture register of the circuit element under test such that the relative access time of the element can be measured. The technique for adjusting this strobe timing can be done with the duty cycle of the clock instead of using elaborate programmable clock choppers. A correct signature in the output register for the circuit element under test is known.  
         [0010]     Then, the duty cycle of the global clock will be decreased until the capture register fails to receive the output of the circuit element under test. The method and system of our invention is advantageous due to the fact that the circuit element is compact, taking up little real estate, and fitting within the macro of the circuit element under test. Moreover, the test circuit is a simple circuit with little delay. This is in direct contrast to large clock choppers and oscillators.  
         [0011]     Moreover, the duty cycle based access time circuit can be used as a normal cycle staged clock with applying stress to the access time.  
     
    
     THE FIGURES  
       [0012]     Various embodiments and exemplifications of our invention are shown in the Figures appended hereto.  
         [0013]      FIG. 1  illustrates an array access timer as described herein, with an array, having an L1/L2 latch, logic, and L1/L2 capture registers.  
         [0014]      FIG. 2  illustrates a timing diagram for DC mode operation of the test circuit.  
         [0015]      FIG. 3  illustrates a timing diagram for AC mode operation of the test circuit. 
     
    
     DETAILED DESCRIPTION  
       [0016]     A built in test circuit  111  is shown in  FIG. 1 . The test circuit has a clock duty cycle based access timer combined with standard stage clocked output register. As shown in  FIG. 1 , the circuit  100 , including the circuit element under test  103  and the test circuit includes a clock input  107  and outputs a data output  109 . The data out  109  is compared with the content of the capture register  105 .  
         [0017]     The element under test may be a memory element, as a SRAM, or any other digital element.  
         [0018]     A “strobe on/off” L1/L2 latch pair  101  waits to receive a signal to activate the timer. The timer includes two NAND circuits,  121  and  123 . The DC mode timer receives as its inputs a signal from the L1 latch of the L1/L2 latch  101 , a global_clock_b input, and a dc_mode control signal. The AC mode timer, NAND gate  123 , receives a control signal from the L2 latch of the L1/L2 latch  101 , a global_clock signal, and an ac_mode control signal. The signals from the timers  121  and  123  are input to NAND gate  131 . The output of NAND gate  131  is input, along with the signal from the circuit element under test, to the L1 latch of the capture register  105 , and as an inverted input  141  to the L2 latch of the Capture Register  105 . The timer has two modes of operation, DC mode, having the timing diagram shown in  FIG. 2 , and AC mode having the timing diagram shown in  FIG. 3 .  
         [0019]     In the DC mode,  FIG. 2 , the timer will clock the capture well after the data from the circuit element  103  under test has reached the input of the capture register  105 . In the DC mode the Capture Register  105  acts like a normal staged register such that its clock (strobe) closes on a normal cycle time boundary. No AC timing measurements can be made in this mode other then cycle time f max.  
         [0020]     In the DC mode, in effect, the capture register  105  is clocked by the global_clock with some amount of delay. The input and outputs are as shown in  FIG. 2 , with global_clock output  201 , array d_out  203 , and capture regular_clock  205 .  
         [0021]     The second mode is the AC mode, with the inputs and output shown in  FIG. 3 , which will allow for the access time measurement. The timer_on signal will be sent from the L2 portion of the “Strobe On/Off” latch on the falling edge of the global_clock (i.e., the inverted global_clock) will be used to clock the capture register  105 . The input and outputs are as shown in  FIG. 3 , with global_clock output  301 , array d_out  303 , and capture regular_clock  305 .  
         [0022]     This means the mid-cycle edge of the clock (the duty cycle dependent edge) is used to strobe the closing of the capture register latch. This clock signal should reach the capture register at approximately the same time as the data output of the circuit element under test when the access time of the circuit element under test is being measured at its limit. Through the use of a tester or the already existing clock circuitry on the chip, the duty cycle of the global_clock can be manipulated. In fact this can usually be done by just changing the frequency of a 50% duty cycle clock. This is because the access time of the element under test is usually longer then one half of the cycle time f max of the circuit element.  
         [0023]     In this case, in order to measure the access time of the element under test in the AC mode, the cycle time of the clock is actually slowed down until the timing of the mid-cycle edge of the global_clock equals the access time of the circuit element under test.  
         [0024]     Either way, the falling edge of the global_clock_b can be adjusted until the capture register  105  reaches its pass/fail point. By examining timing of the global_clock mid-cycle edge, an access time range can be simply calculated. Even if a means doesn&#39;t exist to find an accurate absolute timing of the mid-cycle edge, the relative point of failure for the circuit element and/or individual addresses and bits in the element can be measured for “outlier” timing defects.  
         [0025]     The method described herein measures access time without complicated clock chopper circuit logic and the concomitant area usage.  
         [0026]     While the invention has been described with respect to certain preferred exemplifications and embodiments, it is not intended to limit the scope of the invention thereby, but solely by the claims appended hereto.