Abstract:
An object is to increase the retention characteristics of a memory device formed using a semiconductor with a wide bandgap, such as an oxide semiconductor. A transistor including a back gate (a back gate transistor) is inserted in series at one end of a bit line so that the back gate is constantly at a sufficiently negative potential. The minimum potential of the bit line is set higher than that of a word line. When power is turned off, the bit line is cut off by the back gate transistor, ensuring prevention of outflow of charge accumulated in the bit line. At this time, the potential of a source or a drain (bit line) of a cell transistor is sufficiently higher than that of a gate of the cell transistor (0 V), so that the cell transistor is put in a sufficiently off state; thus, data can be retained.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. application Ser. No. 13/478,215, filed May 23, 2012, now U.S. Pat. No. 8,891,285, which claims the benefit of a foreign priority application filed in Japan as Serial No. 2011-129685 on Jun. 10, 2011, both of which are incorporated by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a memory device formed using a semiconductor. 
     2. Description of the Related Art 
     Semiconductor memory devices include dynamic random access memories (DRAMs) (see Patent Document 1, for example). In a DRAM, memory cells  105  each including a cell transistor  106  and a capacitor  107  as illustrated in  FIG. 2B  are arranged in a matrix as illustrated in  FIG. 2A , and a gate and a drain of the cell transistor  106  are connected to a word line  103  and a bit line  104 , respectively. Moreover, the DRAM includes a row driver  101  for driving a plurality of word lines and a column driver  102  for driving a plurality of bit lines. 
     The DRAM is powered by an external power supply to drive the row driver  101  and the column driver  102 . Note that a cell transistor formed using silicon semiconductor has a small drain current (off-state current) even in the off state, and thus requires tens of refresh operations (operations for replenishing the capacitor with charge) per second. In other words, the DRAM needs to be powered by the external power supply to retain a stored state. 
     In recent years, it has been found that charge can be retained for a very long period of time by utilizing the very low off-state current of transistors formed using an oxide semiconductor whose bandgap is two or more times that of silicon semiconductor. For example, the theoretical off-state current (drain current in the off state) of a semiconductor with a bandgap of 2.5 electron volts or more is 10 −26  A or less. The use of a memory circuit utilizing this as a nonvolatile memory has been proposed (see Patent Documents 2 to 4). 
     A transistor used in such a memory needs to exhibit sufficiently high off resistance (the resistance of the transistor in the off state), i.e., sufficiently low off-state current. For example, in order to retain charge in a capacitor of 30 fF, which is the capacitance of capacitors used in a DRAM in common use, for 10 years, a transistor exhibiting a resistance of as high as 1×10 22 Ω or more in the off state is required. Assuming that the drain voltage is +1 V, the off-state current of the transistor needs to be 100 yA (1×10 −22  A) or less. 
     The drain current of a transistor formed using an oxide semiconductor with a wide bandgap in the subthreshold region can be roughly estimated from the subthreshold value and the threshold voltage. The theoretical lower limit of the subthreshold value at room temperature (27° C.) is 60 mV/decade. 
     For example, assuming that the threshold voltage is +1 V, the subthreshold value is 60 mV/decade, and the drain current obtained when the threshold voltage is +1 V is 1 μA (the source potential Vs is 0 V, while the drain potential Vd is +1 V), the drain current is 100 yA with a gate potential Vg of +40 mV. With a gate potential Vg of 0 V, the drain current of the transistor is less than 100 yA, so that the charge in the capacitor can be retained for 10 years. 
     Note that the retention period is not limited to 10 years, and may be determined in the range from 10 seconds to 100 years depending on intended use. The capacitance of the capacitor or the off resistance or off-state current of the transistor may be set according to the retention period. 
     The above-described drain current is obtained at room temperature. In practice, some problems arise here. The subthreshold value depends on temperature. As temperature increases, the subthreshold value increases. Because it is also possible that the semiconductor memory device is stored at a high temperature, sufficient retention characteristics need to be also ensured at a temperature exceeding room temperature. 
     For example, the theoretical lower limit of the subthreshold value at 95° C. is 74 mV/decade. When the subthreshold value is 74 mV/decade, gate potential Vg with which the drain current becomes 100 yA is −180 mV. When the gate potential Vg is 0 V, the drain current is 10 zA (1×10 −20  A), so that charge retention time is 1% of that at room temperature. 
     As transistor size is decreased, the subthreshold value increases owing to short channel effects. The conductivity type of silicon semiconductor can be controlled by doping. Therefore, in the case of an n-channel transistor, for example, short channel effects can be reduced by increasing the concentration of a p-type dopant in the channel formation region. 
     In contrast, the conductivity type of an oxide semiconductor cannot be controlled by controlling dopant concentration as in the case of silicon semiconductor. The intensity of one conductivity type of an oxide semiconductor can be changed, but the conductivity type of an oxide semiconductor cannot be reversed; for example, an n-type oxide semiconductor cannot be turned into a p-type one by doping. For this reason, short channel effects cannot be reduced by reversing the conductivity type of the channel formation region. 
     Therefore, with a channel length of 100 nm or less, the subthreshold value is 100 mV/decade or more, and the gate potential Vg needs to be maintained at −0.6 V or less. The threshold voltage is +1 V in the above description; when the threshold voltage is low, even the gate potential Vg at room temperature or with a long channel needs to be less than 0 V in order to sufficiently increase the off resistance. Note that the threshold voltage is dependent on the work function of a material for the gate; thus, it is difficult to increase the threshold voltage to +1.5 V or higher. 
     Under such conditions, data loss may occur when power from the external power supply to the semiconductor memory device is interrupted and the potential of the gate becomes the same as that of the source (i.e., Vg=0 V). Since potential is relative, the potentials of portions of the semiconductor memory device are assumed, in the description below, to become 0 V after the interruption of power from the external power supply, although it may take slightly longer or shorter. 
     REFERENCES 
     
         
         [Patent Document 1] U.S. Pat. No. 4,777,625 
         [Patent Document 2] United States Patent Application Publication No. 2011/0101351 
         [Patent Document 3] United States Patent Application Publication No. 2011/0156027 
         [Patent Document 4] United States Patent Application Publication No. 2011/0182110 
       
    
     SUMMARY OF THE INVENTION 
     It is an object of one embodiment of the present invention to provide a memory device that is formed using a semiconductor with an irreversible conductivity type and a bandgap of 2.5 electron volts or more, such as an oxide semiconductor, is sufficiently integrated, and is capable of retaining data for a needed period even during interruption of power from an external power supply. It is another object of one embodiment of the present invention to provide a memory device with a novel structure or a method for driving the memory device, particularly a memory device whose power consumption can be reduced or a method for driving the memory device. 
     The terms used in this specification for the description of the present invention are briefly described. First, when one of a source and a drain of a transistor is called a drain, the other is called a source in this specification. That is, they are not distinguished depending on the potential level. Therefore, a portion called a source in this specification can be alternatively referred to as a drain. 
     Further, even when the expression “be connected” is used in this specification, there is a case in which no physical connection is made in an actual circuit and a wiring is just extended. For example, in a transistor circuit, there is a case in which one wiring serves as gates of a plurality of transistors. In that case, one wiring may have a plurality of branches to gates in a circuit diagram. In this specification, the expression “a wiring is connected to a gate” is also used to describe such a case. 
     One embodiment of the present invention is a semiconductor memory device, which includes a column driver, at least one bit line, at least one word line, at least one memory cell, and a transistor including a back gate (a back gate transistor). The memory cell includes a transistor and a capacitor. A source of the transistor is connected to the bit line. A drain of the transistor is connected to one electrode of the capacitor. A gate of the transistor is connected to the word line. A drain of the back gate transistor is connected to the bit line. A source of the back gate transistor is connected to the column driver. The potential of the back gate of the back gate transistor is lower than the minimum potential of the word line. 
     One embodiment of the present invention is a semiconductor memory device, which includes a column driver, at least one bit line, at least one word line, and at least one memory cell. The memory cell includes a transistor and a capacitor. A source of the transistor is connected to the bit line. A drain of the transistor is connected to one electrode of the capacitor. A gate of the transistor is connected to the word line. The bit line is connected to the column driver. The bit line includes a back gate transistor at one end. The potential of a back gate of the back gate transistor is lower than the minimum potential of the word line. 
     One embodiment of the present invention is a semiconductor memory device, which includes a column driver, at least one bit line, at least one word line, at least one memory cell, and a back gate transistor. The memory cell includes a transistor and a capacitor. A source of the transistor is connected to the bit line. A drain of the transistor is connected to one electrode of the capacitor. A gate of the transistor is connected to the word line. The bit line is connected to the column driver. The back gate transistor is inserted in series in the bit line. The potential of a back gate of the back gate transistor is lower than the minimum potential of the word line. 
     In the above-described semiconductor memory devices, two or more back gate transistors may be inserted in the bit line. A wiring connected to the back gate of the back gate transistor may be in a floating state. The back gate of the back gate transistor may be connected to a negative electrode of a battery which is additionally provided in the semiconductor memory device. Further, the drain of the transistor in a memory cell may be connected to a gate of another transistor in that memory cell. Furthermore, one or more sense amplifiers may be inserted in the bit line. The semiconductor memory device preferably includes a circuit for controlling a gate of the back gate transistor. 
     Moreover, it is preferable that the minimum potential of the bit line be higher than the minimum potential of the word line by 1 V or more. Further, it is preferable that the maximum potential of the gate of the back gate transistor be higher than the maximum potential of the word line by 1 V or more. Furthermore, it is preferable that the potential of the back gate of the back gate transistor be lower than the potential of any other portion. 
     Note that the foregoing applies to the case where the transistor in the memory cell and the back gate transistor are n-channel transistors. In the case where the transistor in the memory cell and the back gate transistor are p-channel transistors, the above-described potential combination is reversed; the one expressed with “high” and the one expressed with “low” in the above description are expressed with “low” and “high”, respectively, and the one expressed with “maximum” and the one expressed with “minimum” in the above description are expressed with “minimum” and “maximum”, respectively. 
     First, the effect of the back gate transistor will be described. The back gate transistor has a structure in which a semiconductor layer is sandwiched between the gate and the back gate. In one embodiment of the present invention, the potential of the back gate is preferably set constant. The off-state current of the back gate transistor can be sufficiently reduced by using a semiconductor with a wide bandgap as described above. 
     The drain current Id of an n-channel transistor which does not have a back gate is represented by a curve A in  FIG. 5A . It is assumed here that the source potential Vs of the transistor is 0 V and the drain potential Vd thereof is higher than 0 V. As illustrated, at a gate potential Vg of 0 V, the drain current Id is considerably large. On the other hand, at a gate potential Vg of −V 1  (&lt;0), the drain current Id is at a negligible level. The value of V 1  may be set as appropriate depending on the structure of the transistor or the like, but is preferably higher than or equal to +1 V. 
     Note that the minimum of the drain current Id ideally depends on the bandgap of a semiconductor, and that of a transistor formed using a semiconductor with a bandgap of 3.2 electron volts and with no defects (with the channel length and the channel width equal to each other and with short channel effects not taken into consideration), for example, is approximately 10 −31  A. 
     On the other hand, when the potential of the back gate of the back gate transistor is set to an appropriate value, the drain current Id can be sufficiently small even at a gate potential Vg of 0 V. For example, when the potential of the back gate is set so that the potential of a gate-side surface of the semiconductor layer of the transistor is substantially equal to or lower than −V 1  at a gate potential Vg of 0 V, the drain current Id is represented by a curve B in  FIG. 5A . In other words, at the gate potential Vg of 0 V, the drain current Id is sufficiently small and is at a negligible level. 
     This is largely attributed to the suppression of leakage current (which is due to a short channel effects) on the back side (the side opposite to the gate) of the semiconductor layer which is achieved with the back gate having a negative potential, and also to the resulting decrease in the subthreshold value. Note that the threshold voltage can also be largely changed according to the potential of the back gate. 
     The back gate is preferably held at a constant potential, and for that purpose, the back gate may be in a floating state. For example, the back gate may be connected to one electrode of a capacitor which is provided to retain electric charge of the back gate. Alternatively, the back gate may be connected to a negative electrode of a battery which is additionally provided in the semiconductor memory device. In any case, the amount of charge released from the back gate to the outside is significantly small, and a potential change in the capacitor and a battery drain are quite limited. 
     The use of the back gate transistor as described above enables the drain current to be sufficiently small even in the state where power is not supplied from the outside (the state where both the gate potential and the source potential are 0 V). However, in some cases, it may be difficult to use such a back gate transistor as a transistor in every memory cell. 
     In terms of the structure of the back gate transistor, it is necessary to add a back gate to an ordinary transistor, which may cause an increase in the number of processes. In addition, since the back gate is provided, the degree of integration in a circuit design may be lowered. Furthermore, in the case where there is a large potential difference between the back gate and another circuit, the back gate needs to be located sufficiently away from the circuit, which may also cause the degree of integration to be lowered. 
     To solve such problems, the present inventor has found that all memory cells can have sufficient retention characteristics by inserting a small number of back gate transistors in appropriate portions of bit lines. 
     In one embodiment of the present invention described above, the back gate transistor is provided, for example, between the column driver and the bit line to put the bit line in a floating state; thus, the potential of the bit line can be kept constant. If the potential of the bit line is a constant value, the drain current can be sufficiently reduced even when the gate of the transistor in the memory cell has a potential of 0 V. This is described with reference to  FIGS. 5A to 5C . 
       FIG. 5B  illustrates a back gate transistor  108  inserted in a bit line  104 . A drain of the back gate transistor  108  is connected to the bit line  104 , and a source thereof is connected to a column driver  102 . A gate of the back gate transistor  108  is connected to a bit line controlling line  112 , and a back gate thereof is connected to a back gate line  111 . Note that the back gate line  111  is constantly held at a potential V 3  (&lt;0 V). 
     A bit line capacitance  121  exists in the bit line  104 . Most of the bit line capacitance  121  is a parasitic capacitance and is usually 10 fF or more, typically 100 fF or more, although it depends on the length of the bit line  104 , the circuit configuration, or the like. It is needless to say that a capacitance intentionally provided in parallel to the bit line may be used as part of the bit line capacitance  121 . 
     The potential of the bit line  104 , which changes according to written or read data, is set to the value V 1  (&gt;0 V) or more while the semiconductor memory device is powered by the external power supply. It is assumed here that the potential of the bit line  104  is V 1 . While the semiconductor memory device is powered by the external power supply, the potential of the bit line controlling line  112  is an appropriate positive value (e.g., V 2  (&gt;0 V)), so that the back gate transistor  108  is in the on state as represented by the curve B in  FIG. 5A . 
     If power from the external power supply is interrupted here, the semiconductor memory device detects the interruption of power and sets the potential of the bit line controlling line  112  to 0 V or less. Consequently, the back gate transistor  108  is turned off. When the potentials of many portions of the semiconductor memory device sufficiently decrease, the potential of the bit line controlling line  112  becomes 0 V. In addition, the potential of the column driver  102  also become 0 V; thus, the source potential of the back gate transistor  108  also becomes 0 V. 
     However, the back gate transistor  108  is turned off at the same time as interruption of power from the external power supply, so that the potential of the bit line  104  (the drain of the back gate transistor  108 ) remains at V 1 . Furthermore, the drain current of the back gate transistor  108  at a gate potential of 0 V is significantly small as represented by the curve B in  FIG. 5A ; thus, the potential of the bit line  104  can be retained at a value close to V 1  for a very long period of time. 
     The bit line  104  is connected to the memory cell  105 . While the semiconductor memory device is powered by the external power supply, the potential of the drain of the cell transistor  106  in the memory cell  105 , which changes according to written data as shown in  FIG. 5C , is V 1  or more because the potential of the bit line  104  is V 1  or more. It is assumed here that the potential of the drain of the cell transistor  106  is V 4  (≧V 1 ). 
     After interruption of power from the external power supply, the potential of the bit line  104  is V 1  as described above, so that the potential of the source of the cell transistor is V 1 . On the other hand, the potential of the word line  103  (the potential of the gate of the cell transistor  106 ) becomes 0 V owing to interruption of power from the external power supply. The drain current of the cell transistor in this state is equivalent to that in the case where the gate potential Vg is set to −V 1  in the curve A of  FIG. 5A . In other words, the drain current becomes a very low value and charge in the capacitor  107  can be retained for a sufficient period of time. 
     That is, by inserting the back gate transistor  108  in the bit line  104 , the potential of the bit line  104  can be retained at an appropriate positive value for a sufficient period of time even during interruption of power from the external power supply. Thus, the semiconductor memory device can exhibit sufficient data retention characteristics even when using cell transistors with a variety of channel lengths and threshold voltages at a wider range of temperatures. Placing a limited number of back gate transistors can produce an effect equivalent to the case of using a back gate transistor in every memory cell. 
     Since the back gate transistor  108  is inserted in series in the bit line  104 , its resistance in the on state is desirably as low as possible. An effective way to accomplish this is to increase the potential of the gate of the back gate transistor  108 . For example, the potential of the gate of the back gate transistor  108  is preferably higher than the maximum potential of the gate of another transistor (e.g., the maximum potential of the word line  103 ) by 1 V or more. Alternatively, the channel width of the back gate transistor may be 10 or more times as large as the minimum feature size. 
     By setting the minimum potential of the word line  103  to −V 1  in the state where the semiconductor memory device is powered by the external power supply, the resistance of the cell transistor  106  in the off state can be sufficiently increased and charge accumulated in the capacitor  107  can be retained. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A and 1B  each illustrate an example of a semiconductor memory device according to the present invention. 
         FIGS. 2A and 2B  illustrate an example of a conventional semiconductor memory device. 
         FIG. 3  illustrates an example of a semiconductor memory device according to the present invention. 
         FIGS. 4A and 4B  illustrate an example of a semiconductor memory device according to the present invention. 
         FIGS. 5A to 5C  illustrate principles of one embodiment of the present invention. 
         FIGS. 6A to 6C  illustrate an example of a manufacturing process of a semiconductor memory device according to the present invention. 
         FIGS. 7A and 7B  illustrate an example of a manufacturing process of a semiconductor memory device according to the present invention. 
         FIG. 8  illustrates an example of a manufacturing process of a semiconductor memory device according to the present invention. 
         FIGS. 9A to 9D  illustrate an example of a manufacturing process of a semiconductor memory device according to the present invention. 
         FIGS. 10A to 10C  illustrate an example of a manufacturing process of a semiconductor memory device according to the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Hereinafter, embodiments will be described with reference to drawings. However, the embodiments can be implemented with various modes. It will be readily appreciated by those skilled in the art that modes and details can be changed in various ways without departing from the spirit and scope of the present invention. Thus, the present invention should not be interpreted as being limited to the following description of the embodiments. 
     Embodiment 1 
     In this embodiment, a semiconductor memory device in  FIG. 1A  will be described. The semiconductor memory device in  FIG. 1A  includes a row driver  101 , a column driver  102 , a plurality of word lines  103  connected to the row driver  101 , a plurality of bit lines  104  (indirectly) connected to the column driver  102 , and memory cells  105  each provided at the intersection of the word line  103  and the bit line  104 . This structure is the same as that of the conventional DRAM in  FIGS. 2A and 2B . 
     The semiconductor memory device in  FIG. 1A  further includes back gate transistors  108  each inserted between the column driver  102  and the bit line  104 . It can also be said that the back gate transistor  108  is inserted in the bit line  104 . It can also be said that a source of the back gate transistor  108  is connected to the column driver  102 , and a drain of the back gate transistor  108  is connected to the bit line  104 . It can also be said that the back gate transistor  108  is inserted between the column driver  102  and the memory cell  105  that is the closest to the column driver  102 . 
     A gate of the back gate transistor  108  is connected to a bit line controlling line  112 , and a back gate of the back gate transistor  108  is connected to a back gate line  111 . The potential of the bit line controlling line  112  is set by a bit line controlling circuit  110 . The back gate line  111  is connected to one electrode of a capacitor  109 , and the potential thereof is held at an appropriate negative value regardless of whether or not an external power supply is provided. 
     For that purpose, charge may be injected so that the potential of the capacitor  109  (the back gate line  111 ) becomes appropriate, and then the back gate line  111  may be brought into a floating state. Alternatively, with the back gate line  111  placed in a floating state, an electron beam with an energy of several tens of kilo electron volts or higher may be injected into part thereof. 
     Note that as illustrated in  FIG. 1B , the back gate line  111  may be connected to a negative electrode of a battery  113  provided over a substrate where the semiconductor memory device is formed or in a package including the substrate. Since the amount of current flowing through the back gate line  111  is significantly small, the capacity of the battery  113  can be extremely low. 
     When the semiconductor memory device is powered by an external power supply and is determined to be usable, the bit line controlling circuit  110  supplies the bit line controlling line  112  with an appropriate potential to turn on the back gate transistor  108 . When interruption of power from the external power supply is detected, or termination of the use of the semiconductor memory device is detected even while the semiconductor memory device is powered by the external power supply, the bit line controlling circuit  110  sets the potential of the bit line controlling line  112  to 0 V or less to rapidly turn off the back gate transistor  108 . 
     Embodiment 2 
     A semiconductor memory device according to this embodiment will be described with reference to  FIG. 3 . The semiconductor memory device in  FIG. 3  has sense amplifiers  114  inserted in bit lines  104 . The sense amplifier  114  is used to divide the bit line  104  into appropriate lengths to lower the bit line capacitance during read operation so that read accuracy can be increased. 
     With the sense amplifier  114  inserted in the bit line  104  in this manner, when power from an external power supply is interrupted, for example, the charge in the bit line  104  flows out also through the sense amplifier  114 . As a result, when power from the external power supply is interrupted, the potential of the bit line  104  connected to the sense amplifier decreases to 0 V. 
     Therefore, it is necessary to prevent charge in the bit lines  104  from flowing out when power from the external power supply is interrupted, by providing the back gate transistors such that the sense amplifier  114  is sandwiched therebetween. 
     The semiconductor memory device in  FIG. 3  includes a column driver  102 , a plurality of word lines  103 , a plurality of bit lines  104 , and memory cells  105  each provided at the intersection of the word line  103  and the bit line  104 . In addition, the sense amplifier  114  is inserted in the bit line  104 . 
     Like the semiconductor memory device described in Embodiment 1, the semiconductor memory device in  FIG. 3  further includes back gate transistors  108 _ 1  each inserted between the column driver  102  and the bit line  104 . A gate of the back gate transistor  108 _ 1  is connected to a bit line controlling line  112 _ 1 , and a back gate of the back gate transistor  108 _ 1  is connected to a back gate line  111 _ 1 . The potential of the back gate line  111 _ 1  is held at an appropriate negative value regardless of whether or not the external power supply power is provided. 
     The semiconductor memory device in  FIG. 3  further includes back gate transistors  108 _ 2  and back gate transistors  108 _ 3  each provided between the sense amplifier  114  connected to the bit line  104  and the memory cell  105  that is the closest to the sense amplifier  114 . A gate of the back gate transistor  108 _ 2  is connected to a bit line controlling line  112 _ 2 , and a gate of the back gate transistor  108 _ 3  is connected to a bit line controlling line  112 _ 3 . A back gate of the back gate transistor  108 _ 2  is connected to a back gate line  111 _ 2 , and a back gate of the back gate transistor  108 _ 3  is connected to a back gate line  111 _ 3 . The potentials of the back gate line  111 _ 2  and the back gate line  111 _ 3  are each held at an appropriate negative value regardless of whether or not the external power supply power is provided. 
     In such a semiconductor memory device, the potentials of the bit line controlling lines  112 _ 1  to  112 _ 3  change according to conditions in a manner similar to that in Embodiment 1. In other words, when the semiconductor memory device is powered by an external power supply and is usable, the bit line controlling lines  112 _ 1  to  112 _ 3  are supplied with such a potential that the back gate transistors  108 _ 1  to  108 _ 3  are turned on. 
     In contrast, when power from the external power supply is interrupted or when the use of the semiconductor memory device is terminated even while the semiconductor memory device is powered by the external power supply, the bit line controlling lines  112 _ 1  to  112 _ 3  are supplied with such a potential that the back gate transistors  108 _ 1  to  108 _ 3  are turned off. 
     For example, when power from the external power supply is interrupted, the potential of the bit line controlling lines  112 _ 1  to  112 _ 3  rapidly becomes 0 V or less to turn off the back gate transistors  108 _ 1  to  108 _ 3 . Consequently, the bit line  104  is divided by the back gate transistors  108 _ 1  to  108 _ 3 . Thus, even if the potential of portions of the bit line  104  connected to the column driver  102  and the sense amplifier  114  becomes 0 V, the potential of the other portions (portions connected to the memory cells  105 ) can remain at an appropriate value (&gt;0 V). 
     On the other hand, because the potential of the word line  103  is 0 V, the cell transistor in the memory cell has sufficiently high resistance, and thus enables charge accumulated in the capacitor to be retained for a long period of time. 
     Embodiment 3 
     A semiconductor memory device in  FIGS. 4A and 4B  will be described. Memory cells  117  in the semiconductor memory device in  FIGS. 4A and 4B  have the same configuration as those described in Patent Document 4. Refer to Patent Document 4 for the operation and the like of the memory cells  117 . 
     As illustrated in  FIG. 4B , the memory cell  117  according to this embodiment includes a write transistor  118 , a read transistor  119 , and a capacitor  120 . A source of the write transistor  118  and a source of the read transistor  119  are connected to a bit line  104 . A gate of the write transistor  118  is connected to a write word line  115 . A drain of the write transistor  118  and a gate of the read transistor  119  are connected to one electrode of the capacitor  120 . The other electrode of the capacitor  120  is connected to a read word line  116 . 
     The potentials of the write word lines  115  and the read word lines  116  are controlled by a row driver  101 . The potential of the bit line  104  is controlled by a column driver  102 . 
     While there are such many differences between the memory cell  105  according to Embodiment 1 or 2 and the memory cell  117  according to this embodiment, these memory cells are the same in that the source of the write transistor  118  (which corresponds to the cell transistor  106  in the memory cell  105  in  FIG. 1A ) is connected to the bit line  104  and the drain of the write transistor  118  is connected to one electrode of the capacitor  120 . In other words, for data retention, the write transistor  118  needs to exhibit high resistance in the off state. 
     Thus, in a manner similar to that in Embodiments 1 and 2, back gate transistors  108  each inserted between the column driver  102  and the bit line  104  are provided, which can achieve sufficiently high resistance even when power from an external power supply is interrupted (see  FIG. 4A ). A gate of the back gate transistor  108  is connected to a bit line controlling line  112 , and a back gate of the back gate transistor  108  is connected to a back gate line  111 . The potential of the back gate line  111  is held at an appropriate negative value regardless of whether or not the external power supply is provided. 
     In such a semiconductor memory device, the potential of the bit line controlling line  112  changes according to conditions in a manner similar to that in Embodiment 1. In other words, when the semiconductor memory device is powered by the external power supply and is usable, the bit line controlling line  112  is supplied with such a potential that the back gate transistor  108  is turned on. 
     In contrast, when power from the external power supply is interrupted or when the use of the semiconductor memory device is terminated even while the semiconductor memory device is powered by the external power supply, the bit line controlling line  112  is supplied with such a potential that the back gate transistor  108  is turned off. 
     For example, when power from the external power supply is interrupted, the potential of the bit line controlling line  112  rapidly becomes 0 V or less to turn off the back gate transistor  108 . Consequently, the potential of the bit line  104  can remain at an appropriate value (&gt;0 V). 
     On the other hand, because the potential of the write word line  115  is 0 V, the write transistor  118  in the memory cell  117  has sufficiently high resistance, and thus enables charge in the capacitor  120  to be retained for a long period of time. 
     The memory cell  117  is characterized by being capable of amplifying a signal with the read transistor  119  and output the amplified signal to the bit line even if the capacitance of the capacitor  120  is low. However, the fact that the capacitance of the capacitor  120  is low means that it is difficult to retain data for a required time if the resistance of the write transistor  118  in the off state is not sufficiently high. Therefore, keeping, during power interruption, the potential of the bit line  104  at an appropriate positive value with the back gate transistor  108  to increase the resistance of the write transistor  118  in the off state is particularly effective in this embodiment. 
     Embodiment 4 
     A brief description is given of a process for manufacturing the semiconductor memory device illustrated in, for example,  FIGS. 1A and 1B  or  FIG. 3  with reference to  FIGS. 6A to 6C ,  FIGS. 7A and 7B , and  FIG. 8 . Refer to known semiconductor integrated circuit manufacturing techniques for the details. Note that  FIGS. 6A to 6C ,  FIGS. 7A and 7B , and  FIG. 8  illustrate the concepts of the manufacturing process and do not show specific cross sections. 
     &lt; FIG. 6A &gt; 
     First, device isolation insulators  202 , n-type impurity regions  203 N, p-type impurity regions  203 P, an n-channel transistor gate  204 N, a p-channel transistor gate  204 P, a first interlayer insulator  205 , first contact plugs  206   a  to  206   d , and the like are formed over a surface of a substrate  201  of a semiconductor or the like by known semiconductor integrated circuit manufacturing techniques. The n-channel transistor or the p-channel transistor here may be used in a row driver, a column driver, a sense amplifier, or the like in a semiconductor memory device. 
     &lt; FIG. 6B &gt; 
     Next, first layer wirings  208   a  to  208   d  are formed so as to be embedded in a first embedment insulator  207 . These wirings are used in, for example, the row driver  101  or the column driver  102  in  FIGS. 1A and 1B , or the sense amplifier  114 . 
     &lt; FIG. 6C &gt; 
     Further, a second interlayer insulator  209 , a second contact plug  210 , a second embedment insulator  211 , second layer wirings  212   a  to  212   c  are formed. Here, the second layer wiring  212   b  corresponds to the back gate of the back gate transistor  108  or the back gate line  111  in  FIGS. 1A and 1B . Note that one or more layers including another wiring may be additionally provided between a layer including the second layer wirings  212   a  to  212   c  and a layer including the first layer wirings  208   a  to  208   d.    
     &lt; FIG. 7A &gt; 
     Further, a third interlayer insulator  213 , third contact plugs  214   a  to  214   c , a third embedment insulator  215 , and third layer wirings  216   a  to  216   e  are formed. Note that the first contact plug  206   a , the first layer wiring  208   a , the second contact plug  210 , the second layer wiring  212   a , the second layer wiring  212   c , the third contact plug  214   a , the third contact plug  214   b , the third layer wiring  216   a , and the third layer wiring  216   b  serve as part of the bit line  104  in  FIGS. 1A and 1B . 
     &lt; FIG. 7B &gt; 
     Subsequently, an oxide semiconductor layer  217   a  and an oxide semiconductor layer  217   b  are formed, and a gate insulator  218  is formed so as to cover them. At this time, it is preferable that the physical thickness of the gate insulator  218  be two or more times that of the oxide semiconductor layer  217   a  and the oxide semiconductor layer  217   b , because this enables the oxide semiconductor layer  217   a  and the oxide semiconductor layer  217   b  to be covered with the gate insulator  218  reliably, thereby preventing shorts between wirings. 
     On the other hand, it is preferable that the effective thickness of the gate insulator (e.g., the equivalent oxide thickness) be less than or equal to that of the oxide semiconductor layer  217   a  and the oxide semiconductor layer  217   b . Therefore, it is preferable that the gate insulator  218  be formed using a material whose dielectric constant is twice that of the oxide semiconductor layer  217   a  and the oxide semiconductor layer  217   b.    
     For example, the gate insulator  218  may be formed using a high dielectric constant material such as hafnium oxide, tantalum oxide, or zirconium oxide. Materials such as barium oxide, strontium oxide, calcium oxide, and lithium oxide which form silicides on silicon semiconductor have been prevented from being used with silicon semiconductor, but may be used with an oxide semiconductor without problems. Therefore, any of these materials can be used for the gate insulator  218  as long as it has high dielectric constant. 
     Then, fourth layer wirings  219   a  to  219   d  are formed. The fourth layer wiring  219   a  here corresponds to the gate of the back gate transistor  108  or the bit line controlling line  112  in  FIG. 1A . The fourth layer wirings  219   b  to  219   d  correspond to the word lines  103  in  FIG. 1A . 
     &lt; FIG. 8 &gt; 
     Stacked capacitors are formed by known DRAM manufacturing techniques. Specifically, a fourth interlayer insulator  220 , a fourth contact plug  221   a , and a fourth contact plug  221   b  are formed, and then a fifth interlayer insulator  222 , a capacitor electrode  223   a  and a capacitor electrode  223   b  are formed thereover. Subsequently, a capacitor insulator  224  and a cell plate  225  are formed. Thus, the semiconductor memory device can be manufactured. 
     Embodiment 5 
     A brief description is given of a process for manufacturing the semiconductor memory device illustrated in  FIGS. 4A and 4B  with reference to  FIGS. 9A to 9D  and  FIGS. 10A to 10C . Refer to known semiconductor integrated circuit manufacturing techniques or Patent Document 2 for the details. Note that  FIGS. 9A to 9D  and  FIGS. 10A to 10C  illustrate the concepts of the manufacturing process and do not show specific cross sections. 
     &lt; FIG. 9A &gt; 
     First, a BOX layer  302 , an SOI layer  303   a , and an SOI layer  303   b  are formed over a surface of a substrate  301  of a semiconductor or the like by known semiconductor integrated circuit manufacturing techniques. 
     &lt; FIG. 9B &gt; 
     Next, read gates  304   a  and  304   b  are formed, and an impurity is added to the SOI layer  303   a  and the SOI layer  303   b  by using these gates as a mask to form impurity regions  305   a  to  305   d . Here, the impurity region  305   a  corresponds to the back gate of the back gate transistor  108  or the back gate line  111  in  FIG. 4A . The read gates  304   a  and  304   b  correspond to the gates of the read transistors  119  in  FIGS. 4A and 4B . Then, a first interlayer insulator  306  is formed and then is planarized to expose top surfaces of the read gates  304   a  and  304   b.    
     &lt; FIG. 9C &gt; 
     First layer wirings  307   a  to  307   e  and a first embedment insulator  308  are formed. 
     &lt; FIG. 9D &gt; 
     Subsequently, an oxide semiconductor layer  309   a  and an oxide semiconductor layer  309   b  are formed, and a gate insulator  310  is formed so as to cover them. Then, second layer wirings  311   a  to  311   e  are formed. The second layer wiring  311   a  here corresponds to the gate of the back gate transistor  108  or the bit line controlling line  112  in  FIG. 4A . The second layer wirings  311   c  and  311   d  correspond to the write word lines  115  in  FIGS. 4A and 4B . The second layer wirings  311   b  and  311   e  correspond to the read word lines  116  in  FIGS. 4A and 4B . 
     &lt; FIG. 10A &gt; 
     A second interlayer insulator  312  with a plane surface is formed. Then, contact plugs  313   a ,  313   b , and  313   c  connected to the first layer wirings  307   a ,  307   b , and  307   d  are formed. 
     &lt; FIG. 10B &gt; 
     Third layer wirings  314   a  and  314   b  are formed. The third layer wirings  314   a  and  314   b  correspond to the bit line  104  in  FIG. 4A . 
     &lt; FIG. 10C &gt; 
     A third interlayer insulator  315  is formed. Any other wirings, interlayer insulators, and the like may additionally be formed. Through the aforementioned process, a semiconductor memory device including a back gate transistor  316 , a read transistor  317 , a write transistor  318 , and a capacitor  319  is formed. The back gate transistor  316  corresponds to the back gate transistor  108  in  FIG. 4A . 
     The read transistor  317 , the write transistor  318 , and the capacitor  319  form one memory cell. The read transistor  317 , the write transistor  318 , and the capacitor  319  correspond to the read transistor  119 , the write transistor  118 , and the capacitor  120  in  FIG. 4B , respectively. 
     Note that  FIG. 10C  illustrates two memory cells (a memory cell  320   a  and a memory cell  320   b ). These memory cells are connected to the same bit line. 
     This application is based on Japanese Patent Application serial no. 2011-129685 filed with Japan Patent Office on Jun. 10, 2011, the entire contents of which are hereby incorporated by reference.