Abstract:
A method is disclosed to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor. The method includes forming a MHK gate stack upon a substrate, the MHK gate stack having a bottom layer of high dielectric constant material, a middle layer of metal, and a top layer of one of amorphous silicon or polycrystalline silicon. The method further forms a depleted sidewall layer on sidewalls of the MHK gate stack so as to overlie the middle layer and the top layer, and not the bottom layer. The depleted sidewall layer is one of amorphous silicon or polycrystalline silicon. The method further forms an offset spacer layer over the depleted sidewall layer and over exposed surfaces of the bottom layer.

Description:
TECHNICAL FIELD 
       [0001]    The exemplary embodiments of this invention relate generally to semiconductor devices and methods to fabricate them and, more specifically, exemplary embodiments of this invention relate to a class of devices known as metal high dielectric constant (high-k or MHK) transistors. 
       BACKGROUND 
       [0002]    MHK transistors are experiencing extremely active development in the industry. One observed problem relates to the presence of an elevated outer fringe capacitance (C of), on the order of 40-80 aF/μm. The elevated value of C of is of concern, in that it at least impairs high frequency operation of the MHK transistor. 
         [0003]    In U.S. Pat. No. 7,164,189 B2 Chien-Chao Huang et al. describe a method that includes providing a semiconductor substrate including a polysilicon or a metal gate structure including at least one overlying hardmask layer; forming spacers selected from the group consisting of oxide/nitride and oxide/nitride/oxide layers adjacent the polysilicon or metal gate structure; removing the at least one overlying hardmask layer to expose the polysilicon or metal gate structure; carrying out an ion implant process; carrying out at least one of a wet and dry etching process to reduce the width of the spacers; and, forming at least one dielectric layer over the polysilicon or metal gate structure and spacers in one of tensile and compressive stress. 
         [0004]    In U.S. Pat. No. 6,448,613 B1 Bin Yu describes a field effect transistor that is fabricated to have a drain overlap and a source overlap to minimize series resistance between the gate and the drain and between the gate and the source of the field effect transistor. The parasitic Miller capacitance formed by the drain overlap and the source overlap is said to be reduced by forming a depletion region at the sidewalls of the gate structure of the field effect transistor. The depletion region is formed by counter-doping the sidewalls of the gate structure. The sidewalls of the gate structure at the drain side and the source side of the field effect transistor are doped with a type of dopant that is opposite to the type of dopant within the gate structure. Such dopant at the sidewalls of the gate structure forms a respective depletion region from the sidewall into approximately the edge of the drain overlap and source overlap that extends under the gate structure to reduce the parasitic Miller capacitance formed by the drain overlap and the source overlap. 
         [0005]    At least one drawback of this latter approach is that it does not address the reduction of parasitic Miller capacitance when metal-like materials (such as TiN) are used. 
       SUMMARY 
       [0006]    The foregoing and other problems are overcome, and other advantages are realized, in accordance with the exemplary embodiments of this invention. 
         [0007]    In a first aspect thereof the exemplary embodiments of this invention provide a method to form a metal high dielectric constant (MHK) transistor, where the method includes providing a MHK stack disposed on a substrate, the MHK stack comprising a layer of high dielectric constant material and an overlying layer comprised of a metal, the MHK stack having an overlying layer comprised of silicon; selectively removing only the layer comprised of silicon and the layer comprised of metal, without removing the layer of high dielectric constant material, to form an upstanding portion of a MHK gate structure comprised of a portion of the layer comprised of silicon, an underlying portion of the layer comprised of metal, and an overlying portion of the layer comprised of silicon; forming a sidewall layer comprised of silicon on sidewalls of the upstanding portion of the MHK gate structure; removing that portion of the layer of high dielectric constant material than does not underlie the upstanding portion of the MHK gate structure; and forming an offset spacer layer over the sidewall layer and over exposed surfaces of a remaining portion of the layer of high dielectric constant material that underlies the upstanding portion of the MHK gate structure. 
         [0008]    In a further aspect thereof the exemplary embodiments of this invention provide a MHK transistor that comprises a substrate; a MHK gate structure disposed on the substrate between a source region and a drain region, the MHK gate structure comprising a layer of high dielectric constant material and an overlying layer comprised of a metal, the MHK gate structure having an overlying layer comprised of silicon, where a lateral extent of the layer of high dielectric constant material is greater than a lateral extent of the overlying layer of metal; a sidewall layer comprised of silicon disposed on sidewalls of the MHK gate structure to cover the layer comprised of metal and the overlying layer comprised of silicon, said sidewall layer also being disposed over a top surface of the underlying layer of high dielectric constant material; and an offset spacer layer disposed over the layer comprised of silicon and over exposed portions of the layer of high dielectric constant material. 
         [0009]    In another aspect thereof the exemplary embodiments of this invention provide a method to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor. The method includes forming a MHK gate stack upon a substrate, the MHK gate stack comprising a bottom layer comprised of high dielectric constant material, a middle layer comprised of metal, and a top layer comprised of one of amorphous silicon or polycrystalline silicon; forming a depleted sidewall layer on sidewalls of the MHK gate stack so as to overlie the middle layer and the top layer, and not the bottom layer, said depleted sidewall layer comprised of one of amorphous silicon or polycrystalline silicon; and forming an offset spacer layer over the depleted sidewall layer and over exposed surfaces of the bottom layer. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The foregoing and other aspects of the embodiments of this invention are made more evident in the following Detailed Description, when read in conjunction with the attached Drawing Figures, wherein: 
           [0011]      FIGS. 1A through 1G  are each an enlarged cross-sectional view of a semiconductor-based structure and depict metal gate process flow in accordance with the exemplary embodiments of this invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0012]    Although well-known to those skilled in the art, certain abbreviations that appear in the ensuing description and/or in the Figures are defined as follows: 
         [0000]    BOX buried oxide
 
CMOS complementary metal-oxide semiconductor
 
CVD chemical vapor deposition
 
FET field effect transistor
 
HfO 2  hafnium oxide
 
MLD multi-layer deposition
 
PECVD plasma enhanced chemical vapor deposition
 
PR photoresist
 
RIE reactive ion etch
 
RTA rapid thermal anneal
 
SOI silicon on insulator
 
STI shallow trench isolation
 
TiN titanium nitride
 
poly polycrystalline silicon
 
Si silicon
 
         [0013]    The inventors have realized that, as compared to conventional poly-gated FETs, the origin of the increased C of is due to a lack of sidewall depletion in the metal gate. This added capacitance adds to the Miller capacitance (Cmiller) and thus has a tangible performance impact. It can be determined that there can exist an approximately a 3.2% per 10 aF/μm of C of increase (assuming that N-type FETS (NFETs) and P-type FETs (PFETs) track together in Cof). 
         [0014]    The exemplary embodiments of this invention overcome this problem by providing a silicon sidewall spacer, in combination with a MHK gate, to reduce C of and thus also reduce Cmiller. 
         [0015]    The use of exemplary embodiments of this invention creates a structure with a thin-polysilicon or amorphous silicon sidewall that gates the FET extension region. Since the gate sidewall is made to be silicon, the sidewall depletion that occurs beneficially lowers the C of to similar levels as in poly-silicon gated FETs. Additionally, since primarily only the extension regions are gated with silicon (and therefore a relaxed EOT is present), the scaled EOT in the MHK transistor channel is maintained. 
         [0016]    In general, the overall fabrication scheme described below may be standard until the gate stack etch. As in a normal process flow the metal etch stops on the hi-k material (such as on a layer of HfO 2 ). At this step, in accordance with the exemplary embodiments of this invention, deposition occurs of polysilicon (either CVD or PECVD) in the thickness range of about 10-20 nm. Then, using RIE, a thin poly-silicon sidewall gate is formed that is disposed largely over the device extension region. Then, processing may continue as in a conventional MHK process flow, such as by removing the hi-k material and growing MLD nitride and subsequent diffusion spacers. 
         [0017]      FIGS. 1A through 1G  are each an enlarged cross-sectional view of a semiconductor-based structure and depict metal gate process flow in accordance with the exemplary embodiments of this invention. In these Figures an NFET and a PFET are shown arranged in a side-by-side manner for convenience of description, and not as a limitation upon the practice of the exemplary embodiments of this invention. 
         [0018]      FIG. 1A  shows a Si substrate  10  having an overlying oxide layer  12  (e.g., 3 μm) and overlying Si and STI regions  14 A,  14 B. A conventional HfO 2 /TiN deposition may provide gate stack layers  16  and  18 , respectively. The HfO 2  layer  16  may be considered as the high-k layer (e.g., k in a range of about 20-25, as compared to 3.9 for SiO 2 ) and may have a thickness in a range of about 1-3 nm. The TiN layer  18  may be considered as the metal (or metal-like layer) and may have a thickness of about 10 nm. Layers  16  and  18  together form the (as yet unpatterned) MHK gate stack. This initial structure may represent a standard SOI (or without BOX bulk) CMOS with a MHK gate stack. 
         [0019]    Note that the exemplary embodiments of this invention are not limited for use with HfO 2  as the high-k material, and other metal oxide-based materials may be used as well, such as a uniform or a composite layer comprised of one or more of Ta 2 O 5 , TiO 2 , Al 2 O 3 , Y 2 O 3  and La 2 O 5 . Materials other than TiN that may be used for the metal-containing layer  18  include, but need not be limited to, one or more of Ta, TaN, TaCN, TaSiN, TaSi, AlN, W and Mo. 
         [0020]      FIG. 1B  shows the deposition of an amorphous Si or a poly Si layer  20 , which may have a thickness in a range of about 30-100 nm, and subsequent deposition and patterning of PR to form PR regions  22 . Each PR region  22  is located where a device gate is desired to be formed. 
         [0021]      FIG. 1C , depicted without the underlying Si substrate  10  and oxide layer  12  for simplicity, shows the result of a gate stack etch (which also removes the PR regions  22 ). In accordance with an aspect of this invention, the gate stack etch stops at the high-k layer  16  of HfO 2 . 
         [0022]      FIG. 1D  shows a blanket deposition by, for example, CVD or PECVD of a layer  24  of amorphous Si or polycrystalline (poly) Si. The Si layer  24  may have a thickness in a range of about 10-20 nm.  FIG. 1D  also shows, further in accordance with the exemplary embodiments, the selective etching of the Si layer  24  so that it remains as a thin layer only on the gate sidewalls, and has a thickness in a range of about 3-6 nm. Again, the etching stops on the high-k layer  16 . Over the metal portions (the TiN portions  18 ) of the underlying gate structure the Si sidewall layer  24  is depleted, which is a desired outcome. 
         [0023]      FIG. 1E  shows the etching and removal of the high-k HfO 2  layer  16 , except for that portion within each gate stack and underlying the TiN  18 . Note that as a result of the removal of the high-k HfO 2  layer  16  a lateral extent of the remaining portion of the layer  16  of high dielectric constant material is greater than a lateral extent of the overlying layer  18  of metal. The remaining portion of the high-k HfO 2  layer  16  may be seen to resemble a pedestal-like structure that supports both the overlying metal layer  18 , the amorphous or polycrystalline Si layer  20 , and the amorphous or polycrystalline depleted Si sidewall layer  24 . 
         [0024]    As but one example a wet etch using a dilute hydrofluoric acid (DHF) solution may be used to remove the high-k HfO 2  layer  16 , as described in an article “Etching of zirconium oxide, hafnium oxide, and hafnium silicates in dilute hydrofluoric acid solutions”, Viral Lowalekar, Srini Raghavan, Materials Research Society, Vol. 19, #4, pgs. 1149-1156. 
         [0025]      FIG. 1E  also shows a result of depositing and etching a thin (e.g., about 3-6 nm) nitride or oxide offset spacer  26  that covers the Si layer  24  remaining on the gate sidewalls. 
         [0026]    The remainder of the metal gate process flow may be conventional for CMOS processing, and can include providing oxide and/or nitride diffusion spacers and implants and final RTA. 
         [0027]    For example,  FIG. 1F  shows a result of selectively masking alternatively the NFET and PFET so as to implant the other to provide extensions  28  and halos  30 , and  FIG. 1G  shows the result of the deposition and etching of a final spacer  32  (nitride or oxide deposited by PECVD), typically having a thickness of about 2-10 nm.  FIG. 1G  involves masking the PFET and implanting the NFET (using for example As or P), and masking the NFET and implanting the PFET (using for example B or BF 2 ). Subsequent annealing provides relatively deep diffusions for forming source and drain regions separated by the gate region. Subsequent processing may provide, in a conventional manner, silicide gates and diffusions (typically with Ni or Co) to complete the NFET and PFET transistors. 
         [0028]    It may be appreciated that even if one were to experience an increase in extension resistance of about 6%, when applied to the NFET and the PFET this would translate into a resistance penalty on the order of about 1.4%, which is more than compensated for by the improvement in the Cmiller. 
         [0029]    The exemplary embodiments of this invention can provide an undoped (intrinsic) Si gate sidewall  24  that doping in the main poly  20  may later diffuse into. The exemplary embodiments of this invention can also provide in-situ doped or implanted silicon (poly or amorphous) sidewalls  24 , and both for the NFET and the PFET. 
         [0030]    It can be appreciated that the MHK device fabrication processes discussed above are compatible with CMOS semiconductor processing methodology. 
         [0031]    Various modifications and adaptations may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims. As but some examples, the use of other similar or equivalent MHK material systems may be attempted by those skilled in the art. However, all such and similar modifications of the teachings of this invention will still fall within the scope of this invention. 
         [0032]    For example, it should be noted again that the exemplary embodiments of this invention are not limited for use with MHK gate structures comprised only of HfO 2  and TiN. As non-limiting examples, a ZrO 2  or a HfSi x O y  material may be used instead, as both exhibit a high dielectric constant (k of approximately 20-25) needed to provide a larger equivalent oxide thickness. In addition, the various layer thicknesses, material types, deposition techniques and the like that were discussed above are not be construed in a limiting sense upon the practice of this invention. 
         [0033]    Furthermore, some of the features of the examples of this invention may be used to advantage without the corresponding use of other features. As such, the foregoing description should be considered as merely illustrative of the principles, teachings, examples and exemplary embodiments of this invention, and not in limitation thereof.