Abstract:
A method for increasing the surface area of an original surface in a semiconductor device is disclosed. In an exemplary embodiment of the invention, the method includes forming a layered mask upon the original surface, the layered mask including a masking layer thereatop having a varying thickness. An isotropic etch is then applied to the layered mask, which isotropic etch further removes exposed portions of the original surface as the layered mask is removed. Thereby, the isotropic etch enhances the non-uniformity of the masking layer and creates a non-uniformity in planarity of the original surface.

Description:
BACKGROUND  
         [0001]    The present invention relates generally to semiconductor device processing and, more particularly, to methods of enhancing the surface of devices, such as capacitors, used in computer memory systems.  
           [0002]    Modem dynamic random access memories (DRAMs) commonly use a single capacitor as a data storage element. As the packing density of DRAMs continues to increase over time, the size of the individual transistors and capacitors within an individual memory cell have correspondingly decreased. However, as the dimensions of the capacitors decrease, so too will the capacitance values associated therewith if no additional measures are taken.  
           [0003]    In order for a DRAM memory cell to operate reliably, the capacitor therein should have a relatively large capacitance value so that the capacitor is less likely to be affected by noise or by the parasitic capacity of the metal lines and wires. Accordingly, a capacitor having an increased surface area is commonly used to maintain a sufficient capacitance value. Nevertheless, even with the use of deep trench capacitors or stacked capacitors, the available device cell area continues to shrink and, as a result, the capacitance value is difficult to maintain.  
           [0004]    Given a limited amount of lateral width and vertical depth or height available for capacitors, another existing approach to maintaining the necessary capacitance values has been to increase the surface area of the capacitor without increasing the lateral or vertical dimensions of the capacitor itself. For example, hemispherical grains (HSG) of silicon may be attached to the surfaces of the capacitor. However, while this process may result in increased surface area and hence increased capacitance, it typically requires specialized tools for the implementation thereof. Furthermore, there is an inherent risk of capacitor leakage associated with this process, due to the use of non-crystalline silicon.  
         BRIEF SUMMARY  
         [0005]    The foregoing discussed drawbacks and deficiencies of the prior art are overcome or alleviated by a method for increasing the surface area of an original surface in a semiconductor device. In an exemplary embodiment of the invention, the method includes forming a layered mask upon the original surface, the layered mask including a masking layer thereatop having a varying thickness. An isotropic etch is then applied to the layered mask, which isotropic etch further removes exposed portions of the original surface as the layered mask is removed. Thereby, the isotropic etch creates a non-uniformity in planarity of the original surface.  
           [0006]    In a preferred embodiment, the method further includes forming a silicon layer upon the original surface, and then forming the masking layer upon the silicon layer. The silicon layer and the masking layer are included within the layered mask. The isotropic etch is then applied to both the masking layer and the silicon layer, with the isotropic etch enhancing the varying thickness and further removing the exposed portions of the original surface as the silicon layer is removed. The silicon layer is etched at a faster rate than the masking layer, which masking layer further comprises a nitride layer. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]    Referring to the exemplary drawings wherein like elements are numbered alike in the several FIGS.:  
         [0008]    FIGS.  1 ( a )- 1 ( e ) are cross-sectional views which illustrate the processing steps of a method for increasing the surface area of a semiconductor device, such as a deep trench capacitor, in accordance with an embodiment of the invention; and  
         [0009]    FIGS.  2 ( a )- 2 ( d ) are cross-sectional views which illustrate the processing steps of a method for increasing the surface area of a semiconductor device, in accordance with an alternative embodiment of the invention. 
     
    
     DETAILED DESCRIPTION  
       [0010]    Referring initially to FIGS.  1 ( a )- 1 ( e ), there is illustrated the processing steps of a method for increasing the surface area of an original surface in semiconductor device, such as a deep trench capacitor, in accordance with an embodiment of the invention. It is to be understood that although the following surface enhancement method embodiments are described in their application to a deep trench capacitor, this is by way of example only, and the method embodiments may also be equally applied to other structures which may rise above the surface of a semiconductor wafer. In FIG. 1( a ), a trench  10  is initially formed within a silicon substrate  12  which may include a pad dielectric  14  (e.g., nitride) thereatop. An insulator collar  16  may also be located at the top of the trench  10  in order to prevent the outward leakage of charge stored within the capacitor. It should be noted that the depth of the trench  10  is significantly greater than the diameter (or width) thereof. Thus, the trench  10  as shown in the FIGS. is illustrative only and not depicted to scale.  
         [0011]    In FIG. 1( b ), a thin base layer  18  is conformally formed on the sides  20  and bottom  22  surfaces of trench  10 . The base layer  18  may include, for example, a nitride layer formed by the deposition of silicon nitride, or by nitridation of the silicon surface interface, resulting in roughly 10 angstroms (Å) of silicon nitride. The purpose of the base layer  18  is to provide good conditions for a subsequent layer of silicon formed thereupon.  
         [0012]    Following the formation of base layer  18 , a silicon layer  24  (e.g., polysilicon or amorphous silicon) is conformally deposited. Silicon layer  24  is formed in a nonuniform manner with regard to layer thickness, degree of crystallization, size, orientation of grains or domains, or any combination thereof. The average thickness of the silicon layer  24  may range from about 30 Å to about 150 Å, and, more specifically, may be about 100 Å. Then, a masking layer  26  is created upon the silicon layer  24 . The masking layer  26  may be created by nitridation of the silicon. The masking layer  26  has a non-uniform thickness due to structural properties, such as the grain boundaries of the silicon layer  24 , and may have a general, representative thickness of about 10 Å. Thus created, the masking layer  26  provides a starting non-uniform topography for a layered mask  27 , comprising masking layer  26 , silicon layer  24  and base layer  18 . The starting non-uniform topography of masking layer  26  in layered mask  27  is then later enhanced and transferred into the trench silicon by subsequent etching.  
         [0013]    Referring now to FIG. 1( c ), a surface roughening etch process is begun by applying an isotropic etch, which etches silicon significantly faster than the masking layer  26  (e.g, silicon nitride). The isotropic etch may be performed as either a dry etch or a wet etch. First, the isotropic etch begins to thin the non-uniform masking layer  26  in a homogeneous manner. Eventually, those portions of masking layer  26  that were initially the thinnest are completely etched away, exposing portions of the silicon layer  24  underneath. The remaining portions of masking layer  26  that were initially the thickest continue to be etched away at a homogeneous rate. At this point, the spatial thickness distribution of the remaining masking layer  26  corresponds to the spatial thickness distribution of the masking layer  26 , as originally applied.  
         [0014]    However, as shown in FIG. 1( d ), once portions of the silicon layer  24  have been exposed, the etching process then starts to etch the silicon at a much faster rate than the remainder of the masking layer  26 . As can be seen, the quicker etching of the silicon creates depressions  28  within the silicon layer  24 , which depressions result in an amplification of the non-uniformity of the existing surface. Eventually, most, if not all, of the remaining portions of the masking layer  26  are be etched away. This is shown in FIG. 1( e ).  
         [0015]    By the time the remainder of masking layer  26  is substantially etched away, those portions of the silicon layer  24 , initially exposed and then etched, are themselves nearly or entirely removed. Again, these areas correspond to the depressions  28  shown in FIG. 1( d ). Once portions of the base layer  18  are exposed, the isotropic etch will begin to remove the same, but at a much slower rate than the silicon layer  24 . At this point, the silicon layer  24  has substantially achieved a maximum surface roughness, as illustrated by the remaining bumps  30  of silicon material.  
         [0016]    When portions of the base layer  18  have been exposed, the surface roughening etch process may be discontinued. An optical emission signal may be recorded and used to monitor the etch plasma, if the etch process used is a dry etch. By tracking a change in the optical emission signal, it can be determined when the masking layer  26  has been removed from the silicon surface or when the base layer  18  has been exposed and, at that point, the etching process is stopped.  
         [0017]    Finally, a transfer etch process is optionally applied, as shown in FIG. 1( e ). In the transfer etch process, any remaining portions of the masking layer  26 , the silicon layer  24 , and the base layer  18  can subsequently be removed. The transfer etch process is also carried out as either a dry or a wet isotropic etch, in which all remaining layers of the layered mask  27  (the silicon layer  24  and, for example, nitride layers  18  and  26 ) are etched at about the same rate. As a result, the surface roughness (or non-uniformity) formed by the silicon bumps  30  in FIG. 1( e ) is transferred into the crystal silicon material of the trench side and bottom surfaces  20 ,  22 . This effect is illustrated in FIG. 1( f ). In addition, the removal of the silicon and nitride residues helps to reduce the risk of device leakage.  
         [0018]    It will be noted that the resulting surface roughness in the trench surfaces may not be quite as pronounced as the roughness of the silicon bumps  30 . However, the final surface roughness is sufficient to increase the overall surface area of the trench surfaces and, accordingly, the capacitance value. Furthermore, this increase on overall surface area does not come at the cost of any significant increase in trench depth or diameter.  
         [0019]    Referring now to FIGS.  2 ( a )- 2 ( d ), an alternative embodiment for increasing the surface area of an original surface of a semiconductor device is illustrated. In FIG. 2( a ), the silicon layer  24  is conformally deposited upon the sides  20  and bottom  22  surfaces of trench  10 , without a base layer thereundemeath. The silicon layer  24  in this embodiment includes a degree of non-uniformity (as also described in the earlier embodiment) so as to provide good conditions for a non-uniformity of a subsequently applied masking layer. An average thickness variation for the silicon layer may range from about 20 Å to about 100 Å and, more specifically, about 50 Å. Depending upon the particular deposition tools and processes used, additional measures may be taken to avoid epitaxial growth of the polysilicon on the crystalline silicon.  
         [0020]    Following the formation of the silicon layer  24 , a masking layer  26  is formed thereupon. Again, as in the previous embodiment, the masking layer  26  may be a nitride layer which is formed, for example, by nitridation of the silicon layer  24 . It will be noted that in this embodiment, the layered mask  27  comprises only the silicon layer  24  and the masking layer  26 , there being no base layer thereundemeath. The masking layer  26  has a general, non-uniform thickness of about 10 Å. Next, in FIG. 2( b ), a surface roughening etch process is used to amplify the non-uniformity of the masking layer  26  into the silicon layer  24 . As is the case for the previous embodiment, the roughening etch is an isotropic etch which etches silicon more quickly than a nitride layer. The thinnest portions of the masking layer  26  are etched away first, thereby exposing the silicon layer  24  and creating amplified depressions  28  therein.  
         [0021]    As etch time passes, most (if not all) of the masking layer  26  is removed and the roughening etch process continues through the silicon layer  24  and into the crystalline silicon surfaces  20 ,  22  of the trench  10 . This is illustrated in FIG. 2( c ).  
         [0022]    Because there is no base layer between the silicon layer  24  and the crystalline trench surface, the etching rate may remain substantially the same. As a result, depressions  32  are created in the crystalline silicon surfaces where the masking layer  26  was initially the thinnest (and where amplified depressions  28  in the silicon layer  24  were created), in addition to the remaining bumps  30  of polysilicon where the masking layer  26  was initially the thickest. Thus, as compared to FIG. 1( e ), the etching process is not significantly slowed by a base layer  18 , and the overall roughness can be amplified beyond the silicon layer  24  of the layered mask  27 .  
         [0023]    Finally, in FIG. 2( d ), the roughness pattern created by the masking layer  26  and amplified by etching of the silicon layer may be partially or completely transferred into the crystalline trench surfaces. In the present embodiment, this may be carried out by a transfer etch as described earlier. Alternatively, the roughening etch may be continued until substantially all of the silicon and masking layers  24 ,  26  have been removed. Further, the silicon layer  24  in the second embodiment may be thinner than in the first embodiment, since it need only create appropriate conditions for the non-uniformity of the masking layer  26 . In the first embodiment, the silicon layer  24  (being first deposited on base layer  18 ) also helps to define a maximum amplitude for the final non-uniformity of the trench surfaces.  
         [0024]    In addition to the embodiments described hereinbefore, other process variations are contemplated. For example, the insulating collar  16 , while widely used in DRAM technology, need not be present atop the trench  10  for the implantation of the above described method embodiments. As another example, the pad dielectric  14  need not be present atop the trench  10  for the implementation of the above described method embodiments. Because of the isotropic nature of the processing steps, specifically the roughening and transfer etches, the methods for increasing the surface area can be applied to all contemplated geometries. This includes, but is not limited to trenches of all aspect ratios (e.g., tapered trenches, bottle-shaped trenches, and the like) and elevated structures (e.g., pillar-shaped, crown shaped, and the like).  
         [0025]    Also, an additional annealing step may be implemented to modify the structure of the silicon layer  24  such that the silicon grain size thereof is increased, thereby creating more favorable conditions for a non-uniform masking layer  26 . The structure of the silicon layer  24  may also be modified by a wet etch step prior to the formation of the masking layer  26  to further enhance a non-uniform creation of the masking layer  26 . Both or either of the silicon layer  24  and/or the underlying silicon  12  (e.g., trench wall) may also be doped at any process step where they are exposed to the possibility of doping (i.e., before they are covered by a deposition or are uncovered by an etch step such as by gas phase doping). Additional cleaning steps may also be performed before either deposition or an etch step.  
         [0026]    Finally, other types of liner material (in lieu of a nitride layer) may be substituted for the masking layer  26  and the base layer  18 . In the embodiments where the entire silicon layer  24  is removed, its material may also be substituted with a material such as amorphous germanium, for example. While the resulting etch chemistries may vary, depending upon the composition of the layers, the isotropic nature of the etch is the same.  
         [0027]    Regardless of the specific embodiment(s) or processing steps implemented, the end result of the aforementioned disclosure is increased surface area. It is to be understood that neither the dominant lateral wavelength of the created roughness, nor the amplitude of a created surface wave, is solely responsible for a significant increase in surface area. They may lie in a wide range within the boundaries given by the geometry of the particular semiconductor device. Rather, it is the ratio of the amplitude to the wavelength of a surface wave which is enhanced for optimal results.  
         [0028]    While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims.