Abstract:
A method of forming a high-k dielectric material which exhibits a substantially lower amount of trap charge within a gate stack region is provided. The method maintains high-temperatures (250° C. or above) such that the substrate wafer is not cooled during the various processing steps. Such a method leads to the formation of a high-k dielectric material which does not exhibit a hysteric behavior in a capacitance-voltage curve as well as an increased mobility on FETs using conventional CMOS processing.

Description:
FIELD OF THE INVENTION 
     The present invention relates to semiconductor devices, and more particularly to a method of forming a dielectric material for use in an electronic semiconductor device such as a field effect transistor (FET). Additionally, the method of the present invention can also be used in forming a capacitor. 
     BACKGROUND OF THE INVENTION 
     In the semiconductor industry, dielectric materials in high-density circuits appear as capacitors in dynamic random access memory (DRAM) applications, gate dielectrics in transistors and as decoupling capacitors. The dielectric materials in these structures are typically silicon dioxide, SiO 2 , which has a dielectric constant of about 4.0. As today&#39;s generation of circuits become smaller and smaller, the dielectric materials employed therein must be made thinner to satisfy circuit requirements. 
     The use of thin, low dielectric constant materials in today&#39;s generation of circuits is undesirable since such materials lead to leaky circuits and therefore large power consumption. Thus, it would be beneficial if the dielectric constant of the dielectric material used in such circuits could be increased. By increasing the dielectric constant, thicker oxides with a lower leakage current could be obtained which are electrically equivalent to thinner SiO 2 . 
     In semiconductor field effect transistor devices, for example, SiO 2  gate oxide leakage currents are rapidly increasing as device dimension are shrinking. For devices containing a gate length of about 100 nm or less, SiO 2  may not be able to be used for future microprocessors and memory chips. 
     Most of the current research is in developing high dielectric constant, i.e., high-k, dielectrics that are based upon binary metal oxides and silicates; See, for example, G. D. Wilk, et al., J. Appl. Phys., 89 (2001), page 5243 and other references cited therein. Recently, it has been demonstrated that Al 2 O 3  NFETs (k=10) with an effective channel length, 1 eff , of 0.08 μm, show more than 100×reduction in leakage currents and equal or better reliability than SiO 2  at room temperature. The foregoing results have been published by D. A. Buchanan, et al., IEDM Technical Digest (2000), page 223. A standard polysilicon, i.e., poly Si, FET process was employed in the Buchanan, et al. article except that Al 2 O 3  was employed as the gate dielectric instead of SiO 2 . Generally, in such a process, cooling of the substrate occurs prior to formation of the binary metal oxide thereon. 
     One main problem with the prior art approach mentioned above is that the devices, i.e., NFETs, containing Al 2 O 3  as a gate dielectric show a much-reduced mobility (a 5×reduction) as compared to SiO 2 . The term “mobility” as used herein denotes the ability of electrons or holes in the semiconductor to move from one end of the channel to the other end. High channel mobility using a given gate dielectric material is important in the semiconductor industry. High channel mobility and therefore faster switching speeds are achieved by reducing trapped charge in the gate stack region. Reduced trapped charge leads to a device which does not exhibit hysteresis in the capacitance-voltage curve. Such a hysteric behavior in the capacitance-voltage curve is shown, for example, in FIG.  1 . 
     In view of the above drawbacks mentioned with prior art high-k dielectrics, there is a continued need for developing a new and improved method of forming a high-k dielectric on the surface of a substrate wherein the mobility of charge carriers within the channel is significantly increased as compared with high-k dielectrics that are prepared by conventional processes. 
     SUMMARY OF THE INVENTION 
     One object of the present invention is to provide a high-k dielectric material. 
     Another object of the present invention is to provide a high-k dielectric material which exhibits low leakage current that is on the order of about 1 A/cm 2  or less at its operating potential. 
     A further object of the present invention is to provide a high-k dielectric material which provides an increased mobility by reducing trapped charge or moving said charge away from the underlying semiconductor substrate. 
     A yet further object of the present invention is to provide a high-k dielectric film that is made using processing steps that are compatible with existing complementary metal oxide semiconductor (CMOS) processing steps. 
     These and other objects and advantages are obtained in the present invention by providing a method wherein the wafer is kept at elevated temperatures (of about 250° C. or above) during the entire process. That is, during the various processing steps of the present invention, especially during the transfer from one reactor chamber to another, the wafer is not allowed to cool to room temperature. By maintaining the temperature of the wafer at about 250° C. or above, a large improvement in electrical characteristics, particularly the mobility, is observed. While not be bound by any theory, it is believed that by not allowing the wafer to cool, a cleaner process with less contaminants is obtained. 
     Specifically, the inventive method of the present invention comprises the steps of: 
     (a) placing a substrate in a first reactor chamber; 
     (b) forming an interfacial dielectric layer on an upper surface of said substrate at a temperature of about 300° C. or above; 
     (c) transferring said substrate from said first reactor chamber to a second reactor chamber in a controlled gaseous ambient or vacuum, while maintaining said substrate at a temperature of about 300° C. or above; and 
     (d) forming a high-k dielectric material atop said interfacial dielectric layer. 
     In accordance with the present invention, the substrate may optionally be transferred to another reactor chamber wherein a gate contact is formed atop the high-k dielectric material. When such a transferring step is employed, the substrate including the high-k dielectric material may also be maintained at a temperature of about 300° C. or above. In another embodiment of the present invention, the substrate is cooled after deposition of the high-k dielectric material, and the gate contact is formed in a separate system. 
     It is noted that the term high-k dielectric material includes any dielectric material that has a dielectric constant that is higher than SiO 2 . Examples of such high-k dielectric materials include, but are not limited to: metal oxides such as Al 2 O 3 , ZrO 2 , HfO 2 , or Ta 2 O 5 ; perovskite-type oxides; metal silicates; metal nitrides; and any combination or multilayer thereof. In a preferred embodiment, the high-k dielectric is a metal oxide, with Al 2 O 3  being one preferred metal oxide. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a curve of capacitance, C, (pF) vs. voltage, V, of a prior art FET device (area of about 2.5E-5 cm 2  and equivalent oxide thickness of about 13.0 Å) wherein Al 2 O 3  was employed as the gate dielectric. Note that the hysterisis curve shown is indicative of charge trapping. 
     FIGS. 2A-2D are pictorial representations (through cross-sectional views) showing the various processing steps of the present invention. 
     FIG. 3 is curve of capacitance, C, (pF) vs. voltage, V, of an FET device prepared utilizing the method of the present invention. Note that the FET device has approximately the same area and equivalent oxide thickness as the prior art FET device employed in FIG.  1 . 
     FIG. 4 is a curve of mobility (cm 2 /V-s) vs. Effective Field (MV/cm) for various gate n-FETs; A is universal Takagi curve (S. Takagi, et al., IEEE Trans. Elec. Dev., Vol. 41, pp 2357-2362, 1994), B is SiO 2 , C is prior art Al 2 O 3  wherein the substrate is cooled between oxynitride growth and Al 2 O 3  formation; and D is Al 2 O 3  prepared using the present invention. 
     FIG. 5 is a pictorial representation of a capacitor structure that can be formed utilizing the processing steps of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention, which provides a method of forming a high-k dielectric film using a process in which the temperature is maintained at about 250° C. or above during the entire process, will now be described in greater detail by referring to the drawings that accompany the present invention. It is noted that in the accompanying drawings, like and/or corresponding elements are referred to by like reference numerals. 
     Reference is first made FIGS. 2A-2D which illustrate an FET formed utilizing processing steps that include the method of the present invention. Specifically, FIG. 2A illustrates a structure that formed after interfacial dielectric layer  12  is formed on an upper surface of semiconductor substrate  10 . 
     The structure shown in FIG. 2A is comprised of conventional materials well known in the art. For example, semiconductor substrate  10  is comprised of a semiconductor material including, but not limited to: Si, Ge, SiGe, GaAs, InAs, InP and all other III/V or II/VI semiconductor compounds. Semiconductor substrate  10  may also include a layered substrate comprising the same or different semiconductor material, e.g., Si/Si or Si/SiGe, as well as a silicon-on-insulator (SOI) substrate. The substrate may be of the n- or p-type depending on the desired polarity of the device to be fabricated. 
     Additionally, semiconductor substrate  10  may contain active device regions, wiring regions, isolation regions or other like regions that are typically present in CMOS-containing devices. For clarity, these regions are not shown in the drawings, but are nevertheless meant to be included within region  10 . In one highly preferred embodiment of the present invention, semiconductor substrate  10  is comprised of Si. 
     In one embodiment of the present invention, the substrate is subjected to a treatment step prior to forming the interfacial dielectric layer thereon. In this embodiment of the present invention, any conventional process which is capable of forming a hydrogen terminated surface layer on the substrate can be employed. For example, a DHF dip process may be used in the present invention to form a hydrogen terminated surface layer on the surface of substrate  10 . 
     The substrate, which may be optionally treated in the above manner, is then placed within a first reactor chamber of a reaction vessel and after locking and evacuating to a desired pressure range, interfacial dielectric layer  12  is formed on the surface of the substrate at a temperature of about 300° C. or above, preferably the interfacial dielectric film is formed at a temperature of from about 650° to about 1200° C. The reaction vessel employed in the present invention includes any multi-chamber reaction vessel well known to those skilled in the art that is capable of at least forming a plurality of films on a surface of a substrate. 
     The interfacial dielectric layer may be comprised of an oxide, nitride, oxynitride or any combination thereof including multilayers. A highly preferred interfacial oxide layer employed in the present invention is an oxynitride. 
     When an oxynitride is employed as interfacial dielectric layer  12 , the interfacial dielectric layer is formed in the presence of any oxygen/nitrogen-containing ambient which may, optionally, be admixed with an inert gas. Suitable oxygen/nitrogen-containing ambients include, but are not limited to: NO, NO 2 , N 2 /O 2 , N 2 O and any mixtures thereof. The term “inert gas” as used herein denotes He, Ar, Ne, Kr, Xe, N 2  and mixtures thereof. 
     In one preferred embodiment, the interfacial dielectric layer is formed in an oxygen/nitrogen-containing ambient that comprises from about 2% to 20% NO which is admixed in N 2 . Preferably, the oxynitride interfacial dielectric layer is formed at a temperature ranging from about 600° to about 900° C. 
     When an oxide or nitride layer is employed, a conventional oxidation or nitridation process may be employed in forming the same. 
     The interfacial dielectric layer may be formed utilizing rapid thermal conditions, or alternatively, furnace conditions may be employed in forming the same. When rapid thermal conditions are employed in forming the interfacial dielectric layer, interfacial dielectric layer  12  is formed at the above temperatures for a time period of about 120 seconds less, preferably for a time period of from about 5 to about 60 seconds. When furnace conditions are employed, interfacial dielectric layer  12  is formed at the above temperatures for a time period of from about 2 minutes or greater, with a time period of from about 5 to about 10 minutes being more highly preferred. 
     It is noted that the above conditions for forming the interfacial dielectric layer are exemplary and that other conditions well known to those skilled in the art can be used so as long as the temperature of interfacial dielectric layer formation is about 300° C. or above. 
     The thickness of the interfacial dielectric layer formed at this point of the present invention is not currently critical to the inventive process, but typically the interfacial dielectric layer has a thickness of from about 0.2 to about 2 nm, with a thickness of from about 0.5 to about 1.2 nm being more highly preferred. 
     Next, the substrate containing the interfacial dielectric layer is transferred to a second reactor chamber within the vessel wherein high-k dielectric film  14  is formed atop interfacial dielectric layer  12 . It should be noted that during the transferring process from the first reactor chamber to the second reactor chamber, the temperature of the substrate including interfacial dielectric layer  12  is maintained at about 300° C. or above. More preferably, the substrate containing interfacial dielectric layer  12  is maintained at temperature of from about 300° to about 700° C. during the entire transfer process. 
     It is noted that during the entire transferring process, the substrate including interfacial dielectric layer  12  is maintained within a controlled gaseous ambient or in a vacuum (pressure of from about 200 mT to about 1E-8 Torr). Illustrative examples of controlled gaseous ambients that can be employed in the present invention include, but are not limited to: inert gas such as He, Ar, N 2 , Ar, Kr, Xe, Ne and mixtures thereof. A highly preferred gaseous ambient employed during the transferring of the substrate from the first to second rector chamber is N 2 . 
     As stated above, a layer of high-k dielectric material  14  is then formed on a surface of interfacial dielectric layer  12  providing the structure shown, for example, in FIG.  2 B. The layer of high-k dielectric material may be formed utilizing a conventional deposition process such as chemical vapor deposition (CVD), plasma-assisted CVD, evaporation, chemical solution deposition, atomic layer deposition (ALD), metal oxide CVD (MOCVD) or any other like deposition process. Preferred deposition processes used in forming high-k dielectrics include ALD and MOCVD. The MOCVD process may be carried out using the conditions disclosed in co-assigned U.S. application Ser. No. 09/676,882, filed Sep. 29, 2000, the entire content of which is incorporated herein by reference. 
     Notwithstanding the type of deposition process used in forming the high-k dielectric, the deposition temperature used in forming the high-k dielectric is from about 250° C. or above, with a deposition temperature of from about 250° to about 700° C. being more highly preferred. 
     The thickness of the layer of high-k dielectric material is not critical to the present invention, but typically, the high-k dielectric material has a thickness of from about 0.5 to about 100 nm after deposition, with a thickness of from about 1 to about 40 nm being more highly preferred. It is noted that the high-k dielectric material employed in the present invention is any dielectric having a dielectric constant higher than SiO 2 , ie., 4.0 or more. More preferably, the high-k dielectric material of the present invention has a dielectric constant of about 7 or greater, with a dielectric constant of from about 10 to about 50 being more highly preferred. 
     The high-k dielectrics that can formed in the present invention include, but are not limited to: metal oxides such as ZrO 2 , Ta 2 O 5 , HfO 2  or Al 2 O 3 ; perovskite-type oxides; metal silicates; metal nitrates; and combinations or multilayers thereof, i.e., a stack of high-k dielectrics. 
     It is noted that the term perovskite-type oxides denotes a material that includes one acidic oxide containing at least one metal selected from Group IVB (Ti, Zr or Hf), Vb (V, Nb or Ta), VIB (Cr, Mo or W), VIIB (Mn or Re), IIIA (Al, Ga or In) or IB (Cu, Ag or Au) of the Periodic Table of Elements (CAS version) and at least one additional cation having a positive formal charge of from about 1 to about 3. Such perovskite-type oxides typically, but not always, have the basic formula: ABO 3 , wherein A is one of the above-mentioned cations and B is one of the above-mentioned metals. Crystalline as well as amorphous forms of such perovskite-type oxides are contemplated herein. 
     Suitable perovskite-type oxides that can be employed in the present invention include, but are not limited to: a titanate system material such as barium titanate, strontium titanate, barium strontium titanate, lead titanate, lead zirconate titanate, lead lanthanum zirconate titanate, barium lanthanum titanate and barium zirconium titanate; an aluminate such as lanthanum aluminate and yttrium aluminate; a niobate or tantalate system material such as lead magnesium niobate, lithium niobate, lithium tantalate, potassium niobate, strontium aluminum tantalate and potassium tantalum niobate; a tungsten-bronze system material such as barium strontium niobate, lead barium niobate, barium titanium niobate; and a Bi-layered perovskite system material such as strontium bismuth tantalate, and bismuth titanate. 
     Of the above-mentioned high-k dielectrics, it is highly preferred that a metal oxide be employed as the high-k dielectric material. Of the various metal oxides, Al 2 O 3  has been exemplified herein. 
     After forming the high-k dielectric material on the surface of interfacial dielectric layer  12 , the substrate including interfacial dielectric layer  12  and high-k dielectric  14  may be optionally transferred from the second reactor chamber to a third reactor chamber wherein a gate contact will be subsequently formed on the high-k dielectric. Note that during the transfer step, the temperature of the substrate may also be maintained at about 300° C. or above (preferably from about 300° to about 500° C.) using the same or different controlled gaseous ambient or vacuum as mentioned above. 
     In another embodiment of the present invention, the gate contact is formed in a separate system from that used in forming the interfacial dielectric material and the high-k dielectric. In such an embodiment, the substrate including interfacial dielectric material and high-k dielectric is cooled and transferred to another system in air. 
     Gate contact  16 , which includes at least a gate material, is then formed on the high-k dielectric material; See FIG.  2 C. The term “gate material” as used herein denotes a conductive material, a material that can be made conductive via a subsequent process such as ion implantation, or any combination thereof. Illustrative examples of suitable gate materials include, but are not limited to: polysilicon, amorphous silicon, elemental metals that are conductive such as W, Pt, Pd, Ru, Rh, Re and Ir, alloys of these elemental metals, silicide or nitrides of these elemental metals and combinations thereof, e.g., a gate stack including a layer of polysilicon and/or a layer of conductive metal. A highly preferred gate material employed in the present invention is a gate material that is comprised of polysilicon or amorphous silicon. 
     The gate material is formed on the surface of the high-k dielectric material utilizing a conventional deposition process including, but not limited to: CVD, plasma-assisted CVD, evaporation, plating or chemical solution deposition. When metal silicides are employed, a conventional silicide process may be used in forming the silicide layer. One such silicide process that can be used in the present invention includes the steps of: first forming an elemental metal on the gate dielectric material, annealing the layers so as to form a metal silicide layer therefrom, and removing any unreacted elemental metal utilizing a conventional wet etch process that has a high selectivity for removing elemental metal as compared to silicide. 
     When polysilicon is employed as the gate material, the polysilicon layer may be formed utilizing an in-situ doping deposition process or by a conventional deposition process followed by ion implantation. Note that the ion implantation step may be formed immediately after deposition of the polysilicon layer, or in a later step of the present invention, i.e., after patterning of the gate stack. 
     It is noted that in embodiments wherein a gate stack including a layer of polysilicon and a layer of conductive elemental metal is employed, an optional diffusion barrier (not shown in the drawings) may be formed between each layer of the gate stack. The optional diffusion barrier, which is formed utilizing a conventional deposition process such as CVD or plasma-assisted CVD, is comprised of a material such as SiN, TaN, AlN, TaSiN, WN, TiN, and other like materials which can prevent diffusion of a conductive material therethrough. 
     After forming the gate contact on the high-k dielectric material, the substrate is cooled to room temperature and thereafter it is removed from the reactor chamber. The cooled substrate is then patterned utilizing conventional processing steps well known in the art which are capable of forming the patterned structure shown in FIG.  2 D. Specifically, the structure shown in FIG. 2D is formed by lithography, material deposition and etching. 
     The lithography step includes the following: applying a photoresist (not shown in the drawings) to the top surface of the gate contact, exposing the photoresist to a pattern of radiation and developing the pattern utilizing a conventional resist developer solution. 
     Etching is typically performed utilizing a conventional dry etching process such as reactive-ion etching, plasma etching, ion beam etching, laser ablation or a combination thereof. The etching step may remove portions of the gate contact and the underlying high-k dielectric material and interfacial dielectric layer that are not protected by the patterned photoresist in a single step, or alternatively, multiple etching steps may be performed wherein the exposed portions of the gate contact is first removed stopping on a surface of the high-k dielectric material, thereafter the exposed portions of the high-k dielectric are removed stopping on the surface of interfacial dielectric layer  12 , and thereafter the exposed portions of the interfacial dielectric layer are removed stopping on semiconductor substrate  10 . Following the etching process, the patterned photoresist is removed utilizing a conventional stripping process well known in the art providing the structure shown, for example, in FIG.  2 D. 
     At this point of the present invention, and if not previously done, the patterned gate contact region may be subjected to a conventional ion implantation step and an activation annealing process. Additionally, various implants which are capable of forming source/drain extension regions and halo implants (not shown in the drawings) may be performed. After each implant, an activation annealing process may be performed, or alternatively, each implant region, including the gate stack, may be activated utilizing a single activation annealing process. 
     Note that the deep source/drain diffusion regions (not shown in the drawings) are formed utilizing conventional processes (i.e., ion implantation and annealing) anytime after the spacers (also not shown) are formed on the exposed vertical sidewalls of the structure shown in FIG.  2 D. 
     FIG. 3 shows the capacitance-voltage curve of an FET device which was made in accordance with the inventive processing steps mentioned above. Note that the curve shows substantially no hysterisis; therefore the inventive FET which includes Al 2 O 3  as the gate dielectric has reduced charge trapping as compared to the FET shown in FIG.  1 . 
     FIG. 4 shows the mobility-Effective Field curve for various gate n-FETs. In this figure A is universal Takagi curve, B is SiO 2 , C is prior art Al 2 O 3  wherein the substrate is cooled between oxynitride growth and Al 2 O 3  formation; and D is Al 2 O 3  prepared using the method of the present invention. The peak mobility for the prior art process which allows cooling between oxynitride formation and Al 2 O 3  formation is about 70 cm 2 /V-s, which agrees with previous work reported in the Buchanan, et al. article mentioned in the background section of the application. A significant improvement in mobility (or about 2×) is obtained when the inventive process is employed. This data is consistent with the reduced trapped charge found in the non-hysteric behavior of the high frequency capacitance-voltage curve shown in FIG.  3 . 
     In another embodiment of the present invention, as shown in FIG. 5, high-k dielectric  14  is formed between two conductive electrode plates  20  and  22 , respectively. Note that in this embodiment, the conductive electrode plates may comprise the same or different conductive material as mentioned above in regard to the gate contact. In such an embodiment, the bottom plate (i.e., reference numeral  20 ) of the capacitor is formed on a substrate (not shown) using one of the aforementioned deposition processes used in forming the gate material. Interfacial dielectric layer  12  is then formed on the bottom conductive plate using the processing steps mentioned hereinabove. Following deposition of the interfacial dielectric layer, high-k dielectric material  14  is formed as described above and thereafter top plate  22  is formed using one of the above-mentioned processes used in forming the gate contact. Note that during the formation of the capacitor device, the structure is maintained throughout the entire process at a temperature of about 250° C. or above and that the various elements of the capacitor are formed in a single reaction vessel which includes multiple reactor chambers. 
     While the present invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.