Abstract:
An ESD circuit includes a plurality of MOS devices arranged in a stack, wherein each of the MOS devices comprises a source, a drain, and a gate; a voltage source inputting a supply voltage to the stack of MOS devices; a first plurality of resistors dividing the supply voltage to each source and each drain of the MOS devices in the stack; a second plurality of resistors biasing the supply voltage to each gate of the MOS devices in the stack; an inverter device operatively connected to the second plurality of resistors; a time lag circuit that turns the inverter device on and off; and a plurality of capacitors pulling the voltage to each gate of the MOS devices in the stack to the supply voltage upon the inverter device turning off.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The embodiments herein generally relate to circuit design, and, more particularly, to electrostatic discharge (ESD) protection circuitry used in complementary metal-oxide-semiconductor (CMOS) technology. 
         [0003]    2. Description of the Related Art 
         [0004]    Protecting electric circuits and devices from ESD continues to be a problem in integrated circuit technology. ESD protection circuits and devices can be used to overcome ESD problems. Typical ESD protection circuitry, such as that described in U.S. Pat. No. 8,059,376 can generally handle a DC voltage up to 7.5v. However, there are certain market segments where a high voltage interface is needed and thus a special ESD protection technique is required. For example, a low noise block (LNB) controller should interface with a 19v DC supply from a cable setup box. Generally, this voltage far exceeds all conventional ESD breakdown limits. Moreover, due to the complexity of the 19v design, there are certain inherent start-up issues which the conventional ESD protection circuits that handle a DC voltage only up to 7.5v do not have to deal with and cannot deal with. Additionally, the conventional approach is to use a high voltage interface circuit, usually manufactured in a bipolar high voltage process, to regulate the voltage down to approximately 3-5 volts as the supply for the LNB controller. However, to minimize the cost of the total system solution, integrating the voltage regulation functionality onto the controller, which is typically manufactured in CMOS technology, is highly desirable. 
         [0005]    A conventional ESD protection clamp is illustrated in  FIG. 1 . A clamp device (M_clamp) is connected between the supply and ground. A resistor/capacitor pair (R_clamp) forms a time lag apparatus to create a time lag when an ESD event occurs on the supply and creates a ground current return path to allow the ESD charge to flow from the supply to ground. This assumes a low and constant voltage level (e.g. up to 7.5v) on the effected device/circuit. However, when the DC voltage increases (e.g., over 7.5v), the ESD device runs the risks of breaking down if no protective measure is undertaken. Therefore, it is desirable to develop ESD protection circuitry that overcomes these challenges. 
       SUMMARY 
       [0006]    In view of the foregoing, an embodiment herein provides an ESD circuit comprising a plurality of metal-oxide-semiconductor (MOS) devices arranged in a stack, wherein each of the MOS devices comprises a source, a drain, and a gate; a voltage source inputting a supply voltage to the stack of MOS devices; a first plurality of resistors dividing the supply voltage to each source and each drain of the MOS devices in the stack; a second plurality of resistors biasing the supply voltage to each gate of the MOS devices in the stack; an inverter device operatively connected to the second plurality of resistors; a time lag circuit that turns the inverter device on and off; and a plurality of capacitors pulling the voltage to each gate of the MOS devices in the stack to the supply voltage upon the inverter device turning off. 
         [0007]    The ESD circuit may further comprise a diode that keeps a gate voltage of the inverter device higher than a turn-on threshold voltage of the stack of MOS devices. Each of the first plurality of resistors and the second plurality of resistors may comprise a resistor ladder. The time lag circuit may comprise a voltage divider connected in parallel with a capacitor. Preferably, the time lag circuit holds a voltage to a gate of the inverter device close to ground in order to turn off the inverter device. The stack of MOS devices preferably opens to form a ground return current path upon the inverter device turning off. A gate-to-source voltage of each of the MOS devices in the stack may be less than a turn-on threshold voltage of the MOS devices. Preferably, no leakage current flows through the stack of MOS devices during steady state. Preferably, the inverter device is temporarily turned off. Preferably, the stack of MOS devices is temporarily opened. The stack of MOS devices may comprise complementary metal-oxide-semiconductor (CMOS) thick oxide devices. 
         [0008]    Another embodiment provides an ESD circuit comprising a stacked MOS device having a biasing structure and time lag circuit that provides current clamping during an ESD event and that is configured to handle DC voltage levels greater than ESD breakdown levels of a MOS device. The stacked MOS device may comprise a plurality of MOS devices each comprising a source, a drain, and a gate, and wherein the ESD circuit may further comprise means for providing a supply voltage to the stacked MOS device; a first plurality of resistors dividing the supply voltage to each source and each drain of the plurality of MOS devices; a second plurality of resistors biasing the supply voltage to each gate of the plurality of MOS devices; an inverter device operatively connected to the second plurality of resistors; a time lag circuit that turns the inverter device on and off; a plurality of capacitors pulling the voltage to each gate of the MOS devices in the stack to the supply voltage upon the inverter device turning off; and a diode that keeps a gate voltage of the inverter device higher than a turn-on threshold voltage of the stack of MOS devices. 
         [0009]    Each of the first plurality of resistors and the second plurality of resistors may comprise a resistor ladder, and wherein the time lag circuit may comprise a voltage divider connected in parallel with a capacitor. The time lag circuit may hold a voltage to a gate of the inverter device close to ground in order to turn off the inverter device, and wherein the stack of MOS devices opens to form a ground return current path upon the inverter device turning off. A gate-to-source voltage of each MOS device in the stacked MOS device may be less than a turn-on threshold voltage of the MOS device, and wherein no leakage current flows through the stack of MOS devices during steady state. Preferably, the inverter device is temporarily turned off, and wherein the stack of MOS devices is temporarily opened. The stacked MOS device may comprise CMOS thick oxide devices. 
         [0010]    Another embodiment provides a method of controlling ESD in a semiconductor structure, the method comprising providing a stack of MOS devices, wherein each of the MOS devices may comprise a source, a drain, and a gate; inputting a supply voltage to the stack of MOS devices; dividing the supply voltage to each source and each drain of the MOS devices in the stack; biasing the supply voltage to each gate of the MOS devices in the stack; clamping current through the semiconductor structure during an ESD event occurring in the semiconductor structure; and pulling voltage to each gate of the MOS devices in the stack to the supply voltage upon the biasing occurring, wherein no leakage current flows through the stack of MOS devices during steady state. The stack of MOS devices is preferably configured to handle DC voltage levels greater than ESD breakdown levels of the semiconductor structure. 
         [0011]    These and other aspects of the embodiments herein will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following descriptions, while indicating preferred embodiments and numerous specific details thereof, are given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the embodiments herein without departing from the spirit thereof, and the embodiments herein include all such modifications. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    The embodiments herein will be better understood from the following detailed description with reference to the drawings, in which: 
           [0013]      FIG. 1  is a circuit diagram illustrating a conventional ESD clamp structure; 
           [0014]      FIG. 2  is a circuit diagram illustrating a NMOS ESD clamp with a biasing structure and safeguard device according to an embodiment herein; 
           [0015]      FIG. 3  is a system block diagram of the circuit of  FIG. 2  according to an embodiment herein; and 
           [0016]      FIG. 4  is a flowchart illustrating a method according to an embodiment herein. 
       
    
    
     DETAILED DESCRIPTION 
       [0017]    The embodiments herein and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. Descriptions of well-known components and are omitted so as to not unnecessarily obscure the embodiments herein. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments herein may be practiced and to further enable those of skill in the art to practice the embodiments herein. Accordingly, the examples should not be construed as limiting the scope of the embodiments herein. 
         [0018]    The embodiments herein provide a circuit that provides ESD protection against a positive ESD event using a CMOS device for high DC voltage interface capabilities. Referring now to the drawings, and more particularly to  FIGS. 2 through 4 , where similar reference characters denote corresponding features consistently throughout the figures, there are shown preferred embodiments. 
         [0019]    The embodiments herein provide an ESD clamp circuit  103  that is capable of handling high DC voltages (for example, up to approximately 21 volts DC) and which uses CMOS technology to facilitate more integration and lower the cost of the total solution.  FIGS. 2 and 3  illustrate a stacked NMOS ESD clamp  103  using NMOS devices in a N-well configuration with a time lag circuit  109 . In  FIG. 2  “s” denotes source, “d” denotes drain, and “g” denotes gate in accordance with industry standards. The various numeric values given in  FIG. 2  are given as examples only and for illustrative purposes, and the embodiments herein are not limited to the values given in  FIG. 2 . Those skilled in the art would readily understand using different values corresponding to the voltages given in  FIG. 2 , for example, based on the particular application and desired result. 
         [0020]    In  FIG. 2 , M_ 1 , M —2 , M_ 3 , M_ 4 , M_ 5 , and M_ 6  are all thick oxide devices, which may be configured as 3.3v CMOS thick oxide devices, in one embodiment, and are stacked on top of each other to provide the current clamping function during ESD events. As mentioned the thick oxide devices could be configured as 3.3v CMOS devices or, in other embodiments, could be configured in other sizes (e.g., 5v devices), with the size depending on the technology and device choice. As an example, assuming a 21v supply voltage is input from a voltage source  101  and provided at the drain of M_ 6 , the resistor ladder  105  of Rd&#39;s biases the source/drain voltages of M_ 1  to M_ 6  to respective voltage levels of 3.5, 7, 10.5, 14, and 17.5 volts. The resistor ladder  107  of Rg&#39;s biases the gate voltages Vg_ 1  to Vg_ 6  to their respective voltage levels of 0, 3.5, 7, 10.5, 14, and 17.5 volts. As each device M_ 1  through M_ 6  has a 0 gate-to-source voltage, which is less than the turn-on threshold voltage of the MOS device (approximately 0.7v), it is evident that no leakage current flows through the ESD clamp  103  during steady state. In this regard, steady state refers to the environment where after an ESD event occurs, the device is functioning under normal operating conditions, which indicates that the supply is a stable DC voltage. All devices M_ 1  to M_ 6  shown in  FIG. 2  have their drain-to-source voltage (Vds), gate-to-drain voltage (Vgd), gate-to-source voltage (Vgs) as well as source-to-bulk voltage (Vsb) and drain-to-bulk voltage (Vdb) within CMOS technology limits. In this regard, if the thick oxide device that are used are 3.3v capable devices, then 3.5v is the technology limits for the device; if the device is a 5v device, then 6 volt is the technology limit, etc. 
         [0021]    For example, M_ 6  is the device in  FIG. 2  that has the highest stress voltage. M_ 6  has the following stress voltage across its four terminals: Vds=3.5v, Vgd=−3.5v, Vgs=0v, Vdb=10.5v, and Vsb=7v. M_ 5  has the following stress voltage across its four terminals: Vds=3.5v, Vgd=−3.5v, Vgs=0v, Vdb=7v, and Vsb=3.5v. M_ 4  has the following stress voltage across its four terminals: Vds=3.5v, Vgd=−3.5v, Vgs=0v, Vdb=3.5v, and Vsb=0v. M_ 3  has the following stress voltage across its four terminals: Vds=3.5v, Vgd=−3.5v, Vgs=0v, Vdb=3.5v, and Vsb=0v. M_ 2  has the following stress voltage across its four terminals: Vds=3.5v, Vgd=−3.5v, Vgs=0v, Vdb=7v, and Vsb=3.5v. M_ 1  has the following stress voltage across its four terminals: Vds=3.5v, Vgd=−3.5v, Vgs=0v, Vdb=3.5v, and Vsb=0v. 
         [0022]    In the semiconductor wafer manufacturing industry, the normal CMOS reverse junction breakdown voltage for the N-well to the P substrate is approximately 11v. Thus, in accordance with  FIGS. 2 and 3 , the ESD clamp  103  provided by the embodiments herein is safe (i.e., and the semiconductor structure  100  attached to the ESD clamp is safe) during a DC condition (i.e., the voltage levels do not change) and does not cause any leakage current because the Vgs level for all of the devices M_ 1  through M_ 6  is 0v. During ESD events, however, the resistor  6 R and R as well as the capacitor C form a time lag circuit  109  and hold the gate voltage of M_inv inverter device  115  close to ground, thus temporarily turning off the device M_inv  115  and allowing the Cg capacitors  113  to pull the gate voltages of Vg_ 1 , . . . , Vg_ 6  to supply. This temporarily opens the device M_ 1  to M_ 6  to form the ground return current path for the ESD clamp  103 . The length of time that devices M_ 1  to M_ 6  open depends on the time constant of the time lag circuit  109  and the current conducting capability of the ESD clamp  103 , which then determines how much ESD charge is returned to ground. The  6 R and R divider  111  ensures that during DC conditions, a gate voltage of approximately 3.5v is provided at the gate of the M_inv  115  to turn on the M_inv  115 . The diode device Qb is provided as a safe guard device  117  to make sure the gate voltage of M_inv  115  during DC conditions is higher than the MOS turn-on threshold voltage (approximately 0.7v). For example, if the DC supply voltage at the drain of M_ 6  is less than 5v, then the gate of M_inv  115  is less than 0.7v and thus does disturb the biasing scheme of the overall circuit. However, with the diode Qb, under all conditions, the M_inv  115  turns on at DC. 
         [0023]      FIG. 4 , with reference to  FIGS. 2 and 3 , is a flow diagram illustrating a method of controlling ESD in a semiconductor structure  100  according to an embodiment herein. The method comprises providing ( 200 ) a stack of MOS devices M_ 1  through M_ 6 , wherein each of the MOS devices M_ 1  through M_ 6  may comprise a source (s), a drain (d), and a gate (g); inputting ( 202 ) a supply voltage to the stack of MOS devices M_ 1  through M_ 6 ; dividing ( 204 ) the supply voltage to each source (s) and each drain (d) of the MOS devices M_ 1  through M_ 6  in the stack; biasing ( 206 ) the supply voltage to each gate (g) of the MOS devices M_ 1  through M_ 6  in the stack; clamping ( 208 ) current through the semiconductor structure  100  during an ESD event occurring in the semiconductor structure  100 ; and pulling ( 210 ) voltage to each gate (g) of the MOS devices M_ 1  through M_ 6  in the stack to the supply voltage upon the biasing occurring, wherein no leakage current flows through the stack of MOS devices M_ 1  through M_ 6  during steady state. The stack of MOS devices M_ 1  through M_ 6  is preferably configured to handle DC voltage levels (e.g., 21v) greater than ESD breakdown levels of the semiconductor structure  100 . 
         [0024]    The foregoing description of the specific embodiments will so fully reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modification within the spirit and scope of the appended claims.