Abstract:
A device, comprising: a first layer and a second layer wherein both said first layer and said second layer are mono-crystalline, wherein said first layer comprises first transistors, wherein said second layer comprises second transistors, wherein at least one of said second transistors substantially overlays one of said first transistors, and wherein both said first transistors and said second transistors are processed following the same lithography step.

Description:
CROSS-REFERENCE OF RELATED APPLICATION 
     This application is a continuation of U.S. patent application Ser. No. 12/901,890, which was filed on Oct. 11, 2010, the contents of which are incorporated by reference herein. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention describes applications of monolithic 3D integration to semiconductor chips performing logic and memory functions. 
     2. Discussion of Background Art 
     Over the past 40 years, one has seen a dramatic increase in functionality and performance of Integrated Circuits (ICs). This has largely been due to the phenomenon of “scaling” i.e. component sizes within ICs have been reduced (“scaled”) with every successive generation of technology. There are two main classes of components in Complimentary Metal Oxide Semiconductor (CMOS) ICs, namely transistors and wires. With “scaling”, transistor performance and density typically improve and this has contributed to the previously-mentioned increases in IC performance and functionality. However, wires (interconnects) that connect together transistors degrade in performance with “scaling”. The situation today is that wires dominate performance, functionality and power consumption of ICs. 
     3D stacking of semiconductor chips is one avenue to tackle issues with wires. By arranging transistors in 3 dimensions instead of 2 dimensions (as was the case in the 1990s), one can place transistors in ICs closer to each other. This reduces wire lengths and keeps wiring delay low. However, there are many barriers to practical implementation of 3D stacked chips. 
     These include: 
     
         
         
           
             Constructing transistors in ICs typically require high temperatures (higher than ˜700° C.) while wiring levels are constructed at low temperatures (lower than ˜400° C.). Copper or Aluminum wiring levels, in fact, can get damaged when exposed to temperatures higher than ˜400° C. If one would like to arrange transistors in 3 dimensions along with wires, it has the challenge described below. For example, let us consider a 2 layer stack of transistors and wires i.e. Bottom Transistor Layer, above it Bottom Wiring Layer, above it Top Transistor Layer and above it Top Wiring Layer. When the Top Transistor Layer is constructed using Temperatures higher than 700° C., it can damage the Bottom Wiring Layer. 
             Due to the above mentioned problem with forming transistor layers above wiring layers at temperatures lower than 400° C., the semiconductor industry has largely explored alternative architectures for 3D stacking In these alternative architectures, Bottom Transistor Layers, Bottom Wiring Layers and Contacts to the Top Layer are constructed on one silicon wafer. Top Transistor Layers, Top Wiring Layers and Contacts to the Bottom Layer are constructed on another silicon wafer. These two wafers are bonded to each other and contacts are aligned, bonded and connected to each other as well. Unfortunately, the size of Contacts to the other Layer is large and the number of these Contacts is small. In fact, prototypes of 3D stacked chips today utilize as few as 10,000 connections between two layers, compared to billions of connections within a layer. This low connectivity between layers is because of two reasons: (i) Landing pad size needs to be relatively large due to alignment issues during wafer bonding. These could be due to many reasons, including bowing of wafers to be bonded to each other, thermal expansion differences between the two wafers, and lithographic or placement misalignment. This misalignment between two wafers limits the minimum contact landing pad area for electrical connection between two layers; (ii) The contact size needs to be relatively large. Forming contacts to another stacked wafer typically involves having a Through-Silicon Via (TSV) on a chip. Etching deep holes in silicon with small lateral dimensions and filling them with metal to form TSVs is not easy. This places a restriction on lateral dimensions of TSVs, which in turn impacts TSV density and contact density to another stacked layer. Therefore, connectivity between two wafers is limited. 
           
         
       
    
     It is highly desirable to circumvent these issues and build 3D stacked semiconductor chips with a high-denstity of connections between layers. To achieve this goal, it is sufficient that one of three requirements must be met: (1) A technology to construct high-performance transistors with processing temperatures below ˜400° C.; (2) A technology where standard transistors are fabricated in a pattern, which allows for high density connectivity despite the misalignment between the two bonded wafers; and (3) A chip architecture where process temperature increase beyond 400° C. for the transistors in the top layer does not degrade the characteristics or reliability of the bottom transistors and wiring appreciably. This patent application describes approaches to address options (1), (2) and (3) in the detailed description section. In the rest of this section, background art that has previously tried to address options (1), (2) and (3) will be described. 
     U.S. Pat. No. 7,052,941 from Sang-Yun Lee (“S-Y Lee”) describes methods to construct vertical transistors above wiring layers at less than 400° C. In these single crystal Si transistors, current flow in the transistor&#39;s channel region is in the vertical direction. Unfortunately, however, almost all semiconductor devices in the market today (logic, DRAM, flash memory) utilize horizontal (or planar) transistors due to their many advantages, and it is difficult to convince the industry to move to vertical transistor technology. 
     A paper from IBM at the Intl. Electron Devices Meeting in 2005 describes a method to construct transistors for the top stacked layer of a 2 chip 3D stack on a separate wafer. This paper is “Enabling SOI-Based Assembly Technology for Three-Dimensional (3D) Integrated Circuits (ICs),”  IEDM Tech. Digest , p. 363 (2005) by A. W. Topol, D. C. La Tulipe, L. Shi, et al. (“Topol”). A process flow is utilized to transfer this top transistor layer atop the bottom wiring and transistor layers at temperatures less than 400° C. Unfortunately, since transistors are fully formed prior to bonding, this scheme suffers from misalignment issues. While Topol describes techniques to reduce misalignment errors in the above paper, the techniques of Topol still suffer from misalignment errors that limit contact dimensions between two chips in the stack to &gt;130 nm. 
     The textbook “Integrated Interconnect Technologies for 3D Nanoelectronic Systems” by Bakir and Meindl (“Bakir”) describes a 3D stacked DRAM concept with horizontal (i.e. planar) transistors. Silicon for stacked transistors is produced using selective epitaxy technology or laser recrystallization. Unfortunately, however, these technologies have higher defect density compared to standard single crystal silicon. This higher defect density degrades transistor performance. 
     In the NAND flash memory industry, several organizations have attempted to construct 3D stacked memory. These attempts predominantly use transistors constructed with poly-Si or selective epi technology as well as charge-trap concepts. References that describe these attempts to 3D stacked memory include “Integrated Interconnect Technologies for 3D Nanoelectronic Systems”, Artech House, 2009 by Bakir and Meindl (“Bakir”), “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory”, Symp. VLSI Technology Tech. Dig. pp. 14-15, 2007 by H. Tanaka, M. Kido, K. Yahashi, et al. (“Tanaka”), “A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device,” Symposium on VLSI Technology, 2010 by W. Kim, S. Choi, et al. (“W. Kim”), “A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device,” Symposium on VLSI Technology, 2010 by Hang-Ting Lue, et al. (“Lue”) and “Sub-50 nm Dual-Gate Thin-Film Transistors for Monolithic 3-D Flash”, IEEE Trans. Elect. Dev., vol. 56, pp. 2703-2710, November 2009 by A. J. Walker (“Walker”). An architecture and technology that utilizes single crystal Silicon using epi growth is described in “A Stacked SONOS Technology, Up to 4 Levels and 6 nm Crystalline Nanowires, with Gate-All-Around or Independent Gates (ΦFlash), Suitable for Full 3D Integration”, International Electron Devices Meeting, 2009 by A. Hubert, et al (“Hubert”). However, the approach described by Hubert has some challenges including use of difficult-to-manufacture nanowire transistors, higher defect densities due to formation of Si and SiGe layers atop each other, high temperature processing for long times, difficult manufacturing, etc. 
     It is clear based on the background art mentioned above that invention of novel technologies for 3D stacked chips will be useful. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows process temperatures required for constructing different parts of a single-crystal silicon transistor. 
         FIGS. 2A-E  depict a layer transfer flow using ion-cut in which a top layer of doped Si is layer transferred atop a generic bottom layer. 
         FIGS. 3A-E  show process flow for forming a 3D stacked IC using layer transfer which requires &gt;400° C. processing for source-drain region construction. 
         FIG. 4  shows a junctionless transistor as a switch for logic applications (prior art). 
         FIGS. 5A-F  show a process flow for constructing 3D stacked logic chips using junctionless transistors as switches. 
         FIGS. 6A-D  show different types of junction-less transistors (JLT) that could be utilized for 3D stacking applications. 
         FIGS. 7A-F  show a process flow for constructing 3D stacked logic chips using one-side gated junctionless transistors as switches. 
         FIGS. 8A-E  show a process flow for constructing 3D stacked logic chips using two-side gated junctionless transistors as switches. 
         FIGS. 9A-V  show process flows for constructing 3D stacked logic chips using four-side gated junctionless transistors as switches. 
         FIGS. 10A-D  show types of recessed channel transistors. 
         FIGS. 11A-F  shows a procedure for layer transfer of silicon regions needed for recessed channel transistors. 
         FIGS. 12A-F  show a process flow for constructing 3D stacked logic chips using standard recessed channel transistors. 
         FIGS. 13A-F  show a process flow for constructing 3D stacked logic chips using RCATs. 
         FIGS. 14A-I  show construction of circuits using sub-400° C. transistors (e.g., junctionless transistors or recessed channel transistors). 
         FIGS. 15A-F  show a procedure for accurate layer transfer of thin silicon regions. 
         FIGS. 16A-F  show an alternative procedure for accurate layer transfer of thin silicon regions. 
         FIGS. 17A-E  show an alternative procedure for low-temperature layer transfer with ion-cut. 
         FIGS. 18A-F  show a procedure for layer transfer using an etch-stop layer controlled etch-back. 
         FIG. 19  show a surface-activated bonding for low-temperature sub-400° C. processing. 
         FIGS. 20A-E  show description of Ge or III-V semiconductor Layer Transfer Flow using Ion-Cut. 
         FIGS. 21A-C  show laser-anneal based 3D chips (prior art). 
         FIGS. 22A-E  show a laser-anneal based layer transfer process. 
         FIGS. 23A-C  show window for alignment of top wafer to bottom wafer. 
         FIGS. 24A-B  show a metallization scheme for monolithic 3D integrated circuits and chips. 
         FIGS. 25A-F  show a process flow for 3D integrated circuits with gate-last high-k metal gate transistors and face-up layer transfer. 
         FIGS. 26A-D  show an alignment scheme for repeating pattern in X and Y directions. 
         FIGS. 27A-F  show an alternative alignment scheme for repeating pattern in X and Y directions. 
         FIGS. 28  show floating-body DRAM as described in prior art. 
         FIGS. 29A-H  show a two-mask per layer 3D floating body DRAM. 
         FIGS. 30A-M  show a one-mask per layer 3D floating body DRAM. 
         FIGS. 31A-K  show a zero-mask per layer 3D floating body DRAM. 
         FIGS. 32A-J  show a zero-mask per layer 3D resistive memory with a junction-less transistor. 
         FIGS. 33A-K  show an alternative zero-mask per layer 3D resistive memory. 
         FIGS. 34A-L  show a one-mask per layer 3D resistive memory. 
         FIGS. 35A-F  show a two-mask per layer 3D resistive memory. 
         FIGS. 36A-F  show a two-mask per layer 3D charge-trap memory. 
         FIGS. 37A-G  show a zero-mask per layer 3D charge-trap memory. 
         FIGS. 38A-D  show a fewer-masks per layer 3D horizontally-oriented charge-trap memory. 
         FIGS. 39A-F  show a two-mask per layer 3D horizontally-oriented floating-gate memory. 
         FIGS. 40A-H  show a one-mask per layer 3D horizontally-oriented floating-gate memory. 
         FIGS. 41A-B  show periphery on top of memory layers. 
         FIGS. 42A-E  show a method to make high-aspect ratio vias in 3D memory architectures. 
         FIGS. 43A-F  depict an implementation of laser anneals for JFET devices. 
         FIGS. 44A-D  depict a process flow for constructing 3D integrated chips and circuits with misalignment tolerance techniques and repeating pattern in one direction. 
         FIGS. 45A-D  show a misalignment tolerance technique for constructing 3D integrated chips and circuits with repeating pattern in one direction. 
         FIGS. 46A-G  illustrate using a carrier wafer for layer transfer. 
         FIGS. 47A-K  illustrate constructing chips with nMOS and pMOS devices on either side of the wafer. 
         FIG. 48  illustrates using a shield for blocking Hydrogen implants from gate areas. 
         FIG. 49  illustrates constructing transistors with front gates and back gates on either side of the semiconductor layer. 
         FIGS. 50A-E  show polysilicon select devices for 3D memory and peripheral circuits at the bottom according to some embodiments of the current invention. 
         FIGS. 51A-F  show polysilicon select devices for 3D memory and peripheral circuits at the top according to some embodiments of the current invention. 
         FIGS. 52A-D  show a monolithic 3D SRAM according to some embodiments of the current invention. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of the present invention are now described with reference to  FIGS. 1-52 , it being appreciated that the figures illustrate the subject matter not to scale or to measure. Many figures describe process flows for building devices. These process flows, which are essentially a sequence of steps for building a device, have many structures, numerals and labels that are common between two or more adjacent steps. In such cases, some labels, numerals and structures used for a certain step&#39;s figure may have been described in previous steps&#39; figures. 
     Section 1: Construction of 3D Stacked Semiconductor Circuits and Chips with Processing Temperatures Below 400° C. 
     This section of the document describes a technology to construct single-crystal silicon transistors atop wiring layers with less than 400° C. processing temperatures. This allows construction of 3D stacked semiconductor chips with high density of connections between different layers, because the top-level transistors are formed well-aligned to bottom-level wiring and transistor layers. Since the top-level transistor layers are very thin (preferably less than 200 nm), alignment can be done through these thin silicon and oxide layers to features in the bottom-level. 
       FIG. 1  shows different parts of a standard transistor used in Complementary Metal Oxide Semiconductor (CMOS) logic and SRAM circuits. The transistor is constructed out of single crystal silicon material and may include a source  0106 , a drain  0104 , a gate electrode  0102  and a gate dielectric  0108 . Single crystal silicon layers  0110  can be formed atop wiring layers at less than 400° C. using an “ion-cut process.” Further details of the ion-cut process will be described in  FIGS. 2A-E . Note that the terms smart-cut, smart-cleave and nano-cleave are used interchangeably with the term ion-cut in this document. Gate dielectrics can be grown or deposited above silicon at less than 400° C. using a Chemical Vapor Deposition (CVD) process, an Atomic Layer Deposition (ALD) process or a plasma-enhanced thermal oxidation process. Gate electrodes can be deposited using CVD or ALD at sub-400° C. temperatures as well. The only part of the transistor that requires temperatures greater than 400° C. for processing is the source-drain region, which receive ion implantation which needs to be activated. It is clear based on  FIG. 1  that novel transistors for 3D integrated circuits that do not need high-temperature source-drain region processing will be useful (to get a high density of inter-layer connections). 
       FIGS. 2A-E  describes an ion-cut flow for layer transferring a single crystal silicon layer atop any generic bottom layer  0202 . The bottom layer  0202  can be a single crystal silicon layer. Alternatively, it can be a wafer having transistors with wiring layers above it. This process of ion-cut based layer transfer may include several steps, as described in the following sequence: 
     Step (A): A silicon dioxide layer  0204  is deposited above the generic bottom layer  0202 .  FIG. 2A  illustrates the structure after Step (A) is completed. 
     Step (B): The top layer of doped or undoped silicon  206  to be transferred atop the bottom layer is processed and an oxide layer  0208  is deposited or grown above it.  FIG. 2B  illustrates the structure after Step (B) is completed. 
     Step (C): Hydrogen is implanted into the top layer silicon  0206  with the peak at a certain depth to create the plane  0210 . Alternatively, another atomic species such as helium or boron can be implanted or co-implanted.  FIG. 2C  illustrates the structure after Step (C) is completed.
 
Step (D): The top layer wafer shown after Step (C) is flipped and bonded atop the bottom layer wafer using oxide-to-oxide bonding.  FIG. 2D  illustrates the structure after Step (D) is completed.
 
Step (E): A cleave operation is performed at the hydrogen plane  0210  using an anneal. Alternatively, a sideways mechanical force may be used. Further details of this cleave process are described in “Frontiers of silicon-on-insulator,” J. Appl. Phys. 93, 4955-4978 (2003) by G. K. Celler and S. Cristoloveanu (“Celler”) and “Mechanically induced Si layer transfer in hydrogen-implanted Si wafers,” Appl. Phys. Lett., vol. 76, pp. 2370-2372, 2000 by K. Henttinen, I. Suni, and S. S. Lau (“Hentinnen”). Following this, a Chemical-Mechanical-Polish (CMP) is done.  FIG. 2E  illustrates the structure after Step (E) is completed.
 
     A possible flow for constructing 3D stacked semiconductor chips with standard transistors is shown in  FIGS. 3A-E . The process flow may comprise several steps in the following sequence: 
     Step (A): The bottom wafer of the 3D stack is processed with a bottom transistor layer  0306  and a bottom wiring layer  0304 . A silicon dioxide layer  0302  is deposited above the bottom transistor layer  0306  and the bottom wiring layer  0304 .  FIG. 3A  illustrates the structure after Step (A) is completed.
 
Step (B): Using a procedure similar to  FIGS. 2A-E , a top layer of p− or n− doped Silicon  0310  is transferred atop the bottom wafer.  FIG. 3B  illustrates the structure after Step (B) is completed.
 
Step (C) Isolation regions (between adjacent transistors) on the top wafer are formed using a standard shallow trench isolation (STI) process. After this, a gate dielectric  0318  and a gate electrode  0316  are deposited, patterned and etched.  FIG. 3C  illustrates the structure after Step (C) is completed.
 
Step (D): Source  0320  and drain  0322  regions are ion implanted.  FIG. 3D  illustrates the structure after Step (D) is completed.
 
Step (E): The top layer of transistors is annealed at high temperatures, typically in between 700° C. and 1200° C. This is done to activate dopants in implanted regions. Following this, contacts are made and further processing occurs.  FIG. 3E  illustrates the structure after Step (E) is completed.
 
The challenge with following this flow to construct 3D integrated circuits with aluminum or copper wiring is apparent from  FIGS. 3A-E . During Step (E), temperatures above 700° C. are utilized for constructing the top layer of transistors. This can damage copper or aluminum wiring in the bottom wiring layer  0304 . It is therefore apparent from  FIGS. 3A-E  that forming source-drain regions and activating implanted dopants forms the primary concern with fabricating transistors with a low-temperature (sub-400° C.) process.
 
Section 1.1: Junction-Less Transistors as a Building Block for 3D Stacked Chips
 
     One method to solve the issue of high-temperature source-drain junction processing is to make transistors without junctions i.e. Junction-Less Transistors (JLTs). An embodiment of this invention uses JLTs as a building block for 3D stacked semiconductor circuits and chips. 
       FIG. 4  shows a schematic of a junction-less transistor (JLT) also referred to as a gated resistor or nano-wire. A heavily doped silicon layer (typically above 1×10 19 /cm 3 , but can be lower as well) forms source  0404 , drain  0402  as well as channel region of a JLT. A gate electrode  0406  and a gate dielectric  0408  are present over the channel region of the JLT. The JLT has a very small channel area (typically less than 20 nm on one side), so the gate can deplete the channel of charge carriers at 0V and turn it off I-V curves of n channel ( 0412 ) and p channel ( 0410 ) junctionless transistors are shown in  FIG. 4  as well. These indicate that the JLT can show comparable performance to a tri-gate transistor that is commonly researched by transistor developers. Further details of the JLT can be found in “Junctionless multigate field-effect transistor,” Appl. Phys. Lett., vol. 94, pp. 053511 2009 by C.-W. Lee, A. Afzalian, N. Dehdashti Akhavan, R. Yan, I. Ferain and J. P. Colinge (“C-W. Lee”). Contents of this publication are incorporated herein by reference. 
       FIGS. 5A-F  describes a process flow for constructing 3D stacked circuits and chips using JLTs as a building block. The process flow may comprise several steps, as described in the following sequence: 
     Step (A): The bottom layer of the 3D stack is processed with transistors and wires. This is indicated in the figure as bottom layer of transistors and wires  502 . Above this, a silicon dioxide layer  504  is deposited.  FIG. 5A  shows the structure after Step (A) is completed.
 
Step (B): A layer of n+ Si  506  is transferred atop the structure shown after Step (A). It starts by taking a donor wafer which is already n+ doped and activated. Alternatively, the process can start by implanting a silicon wafer and activating at high temperature forming an n+ activated layer. Then, H+ ions are implanted for ion-cut within the n+ layer. Following this, a layer-transfer is performed. The process as shown in  FIGS. 2A-E  is utilized for transferring and ion-cut of the layer forming the structure of  FIG. 5A .  FIG. 5B  illustrates the structure after Step (B) is completed.
 
Step (C): Using lithography (litho) and etch, the n+ Si layer is defined and is present only in regions where transistors are to be constructed. These transistors are aligned to the underlying alignment marks embedded in bottom layer  502 .  FIG. 5C  illustrates the structure after Step (C) is completed, showing structures of the gate dielectric material  511  and gate electrode material  509  as well as structures of the n+ silicon region  507  after Step (C).
 
Step (D): The gate dielectric material  510  and the gate electrode material  508  are deposited, following which a CMP process is utilized for planarization. The gate dielectric material  510  could be hafnium oxide. Alternatively, silicon dioxide can be used. Other types of gate dielectric materials such as Zirconium oxide can be utilized as well. The gate electrode material could be Titanium Nitride. Alternatively, other materials such as TaN, W, Ru, TiAlN, polysilicon could be used.  FIG. 5D  illustrates the structure after Step (D) is completed.
 
Step (E): Litho and etch are conducted to leave the gate dielectric material and the gate electrode material only in regions where gates are to be formed.  FIG. 5E  illustrates the structure after Step (E) is completed. Final structures of the gate dielectric material  511  and gate electrode material  509  are shown.
 
Step (F): An oxide layer is deposited and polished with CMP. This oxide region serves to isolate adjacent transistors. Following this, rest of the process flow continues, where contact and wiring layers could be formed.  FIG. 5F  illustrates the structure after Step (F) is completed. Note that top-level transistors are formed well-aligned to bottom-level wiring and transistor layers. Since the top-level transistor layers are made very thin (preferably less than 200 nm), the lithography equipment can see through these thin silicon layers and align to features at the bottom-level. While the process flow shown in  FIGS. 5A-F  gives the key steps involved in forming a JLT for 3D stacked circuits and chips, it is conceivable to one skilled in the art that changes to the process can be made. For example, process steps and additional materials/regions to add strain to junctionless transistors can be added or a p+ silicon layer could be used. Furthermore, more than two layers of chips or circuits can be 3D stacked.
 
       FIGS. 6A-D  shows that JLTs that can be 3D stacked fall into four categories based on the number of gates they use: One-side gated JLTs as shown in  FIG. 6A , two-side gated JLTs as shown in  FIG. 6B , three-side gated JLTs as shown in  FIG. 6C , and gate-all-around JLTs as shown in  FIG. 6D . The JLT shown in  FIGS. 5A-F  falls into the three-side gated JLT category. As the number of JLT gates increases, the gate gets more control of the channel, thereby reducing leakage of the JLT at 0V. Furthermore, the enhanced gate control can be traded-off for higher doping (which improves contact resistance to source-drain regions) or bigger JLT cross-sectional areas (which is easier from a process integration standpoint). However, adding more gates typically increases process complexity. 
       FIGS. 7A-F  describes a process flow for using one-side gated JLTs as building blocks of 3D stacked circuits and chips. The process flow may include several steps as described in the following sequence: 
     Step (A): The bottom layer of the two chip 3D stack is processed with transistors and wires. This is indicated in the figure as bottom layer of transistors and wires  702 . Above this, a silicon dioxide layer  704  is deposited.  FIG. 7A  illustrates the structure after Step (A) is completed.
 
Step (B): A layer of n+ Si  706  is transferred atop the structure shown after Step (A). The process shown in  FIGS. 2A-E  is utilized for this purpose as was presented with respect to  FIG. 5 .  FIG. 7B  illustrates the structure after Step (B) is completed.
 
Step (C): Using lithography (litho) and etch, the n+ Si layer  706  is defined and is present only in regions where transistors are to be constructed. An oxide  705  is deposited (for isolation purposes) with a standard shallow-trench-isolation process. The n+ Si structure remaining after Step (C) is indicated as n+ Si  707 .  FIG. 7C  illustrates the structure after Step (C) is completed.
 
Step (D): The gate dielectric material  708  and the gate electrode material  710  are deposited. The gate dielectric material  708  could be hafnium oxide. Alternatively, silicon dioxide can be used. Other types of gate dielectric materials such as Zirconium oxide can be utilized as well. The gate electrode material could be Titanium Nitride. Alternatively, other materials such as TaN, W, Ru, TiAlN, polysilicon could be used.  FIG. 7D  illustrates the structure after Step (D) is completed.
 
Step (E): Litho and etch are conducted to leave the gate dielectric material  708  and the gate electrode material  710  only in regions where gates are to be formed. It is clear based on the schematic that the gate is present on just one side of the JLT. Structures remaining after Step (E) are gate dielectric  709  and gate electrode  711 .  FIG. 7E  illustrates the structure after Step (E) is completed.
 
Step (F): An oxide layer  713  is deposited and polished with CMP.  FIG. 7F  illustrates the structure after Step (F) is completed. Following this, rest of the process flow continues, with contact and wiring layers being formed.
 
Note that top-level transistors are formed well-aligned to bottom-level wiring and transistor layers. Since the top-level transistor layers are made very thin (preferably less than 200 nm), the lithography equipment can see through these thin silicon layers and align to features at the bottom-level. While the process flow shown in  FIGS. 7A-F  illustrates several steps involved in forming a one-side gated JLT for 3D stacked circuits and chips, it is conceivable to one skilled in the art that changes to the process can be made. For example, process steps and additional materials/regions to add strain to junction-less transistors can be added. Furthermore, more than two layers of chips or circuits can be 3D stacked.
 
       FIGS. 8A-E  describes a process flow for forming 3D stacked circuits and chips using two side gated JLTs. The process flow may include several steps, as described in the following sequence: 
     Step (A): The bottom layer of the 2 chip 3D stack is processed with transistors and wires. This is indicated in the figure as bottom layer of transistors and wires  802 . Above this, a silicon dioxide layer  804  is deposited.  FIG. 8A  shows the structure after Step (A) is completed.
 
Step (B): A layer of n+ Si  806  is transferred atop the structure shown after Step (A). The process shown in  FIGS. 2A-E  is utilized for this purpose as was presented with respect to  FIGS. 5A-F . A nitride (or oxide) layer  808  is deposited to function as a hard mask for later processing.  FIG. 8B  illustrates the structure after Step (B) is completed.
 
Step (C): Using lithography (litho) and etch, the nitride layer  808  and n+ Si layer  806  are defined and are present only in regions where transistors are to be constructed. The nitride and n+ Si structures remaining after Step (C) are indicated as nitride hard mask  809  and n+ Si  807 .  FIG. 8C  illustrates the structure after Step (C) is completed.
 
Step (D): The gate dielectric material  810  and the gate electrode material  808  are deposited. The gate dielectric material  810  could be hafnium oxide. Alternatively, silicon dioxide can be used. Other types of gate dielectric materials such as Zirconium oxide can be utilized as well. The gate electrode material could be Titanium Nitride. Alternatively, other materials such as TaN, W, Ru, TiAlN, polysilicon could be used.  FIG. 8D  illustrates the structure after Step (D) is completed.
 
Step (E): Litho and etch are conducted to leave the gate dielectric material  810  and the gate electrode material  808  only in regions where gates are to be formed. Structures remaining after Step (E) are gate dielectric  811  and gate electrode  809 .  FIG. 8E  illustrates the structure after Step (E) is completed.
 
Note that top-level transistors are formed well-aligned to bottom-level wiring and transistor layers. Since the top-level transistor layers are made very thin (preferably less than 200 nm), the lithography equipment can see through these thin silicon layers and align to features at the bottom-level. While the process flow shown in  FIGS. 8A-E  gives the key steps involved in forming a two side gated JLT for 3D stacked circuits and chips, it is conceivable to one skilled in the art that changes to the process can be made. For example, process steps and additional materials/regions to add strain to junction-less transistors can be added. Furthermore, more than two layers of chips or circuits can be 3D stacked. An important note in respect to the JLT devices been presented is that the layer transferred used for the construction is usually thin layer of less than 200 nm and in many applications even less than 40 nm. This is achieved by the depth of the implant of the H+ layer used for the ion-cut and by following this by thinning using etch and/or CMP.
 
       FIGS. 9A-J  describes a process flow for forming four-side gated JLTs in 3D stacked circuits and chips. Four-side gated JLTs can also be referred to as gate-all around JLTs or silicon nanowire JLTs. They offer excellent electrostatic control of the channel and provide high-quality I-V curves with low leakage and high drive currents. The process flow in  FIGS. 9A-J  may include several steps in the following sequence: 
     Step (A): On a p− Si wafer  902 , multiple n+ Si layers  904  and  908  and multiple n+ SiGe layers  906  and  910  are epitaxially grown. The Si and SiGe layers are carefully engineered in terms of thickness and stoichiometry to keep defect density due to lattice mismatch between Si and SiGe low. Some techniques for achieving this include keeping thickness of SiGe layers below the critical thickness for forming defects. A silicon dioxide layer  912  is deposited above the stack.  FIG. 9A  illustrates the structure after Step (A) is completed.
 
Step (B): Hydrogen is implanted at a certain depth in the p− wafer, to form a cleave plane  920  after bonding to bottom wafer of the two-chip stack. Alternatively, some other atomic species such as He can be used.  FIG. 9B  illustrates the structure after Step (B) is completed.
 
Step (C): The structure after Step (B) is flipped and bonded to another wafer on which bottom layers of transistors and wires  914  are constructed. Bonding occurs with an oxide-to-oxide bonding process.  FIG. 9C  illustrates the structure after Step (C) is completed.
 
Step (D): A cleave process occurs at the hydrogen plane using a sideways mechanical force. Alternatively, an anneal could be used for cleaving purposes. A CMP process is conducted till one reaches the n+ Si layer  904 .  FIG. 9D  illustrates the structure after Step (D) is completed.
 
Step (E): Using litho and etch, Si  918  and SiGe  916  regions are defined to be in locations where transistors are required. Oxide  920  is deposited to form isolation regions and to cover the Si/SiGe regions  916  and  918 . A CMP process is conducted.  FIG. 9E  illustrates the structure after Step (E) is completed.
 
Step (F): Using litho and etch, Oxide regions  920  are removed in locations where a gate needs to be present. It is clear that Si regions  918  and SiGe regions  916  are exposed in the channel region of the JLT.  FIG. 9F  illustrates the structure after Step (F) is completed.
 
Step (G): SiGe regions  916  in channel of the JLT are etched using an etching recipe that does not attack Si regions  918 . Such etching recipes are described in “High performance 5 nm radius twin silicon nanowire MOSFET(TSNWFET): Fabrication on bulk Si wafer, characteristics, and reliability,” in  Proc. IEDM Tech. Dig.,  2005, pp. 717-720 by S. D. Suk, S.-Y. Lee, S.-M. Kim, et al. (“Suk”).  FIG. 9G  illustrates the structure after Step (G) is completed.
 
Step (H): This is an optional step where a hydrogen anneal can be utilized to reduce surface roughness of fabricated nanowires. The hydrogen anneal can also reduce thickness of nanowires. Following the hydrogen anneal, another optional step of oxidation (using plasma enhanced thermal oxidation) and etch-back of the produced silicon dioxide can be used. This process thins down the silicon nanowire further.  FIG. 9H  illustrates the structure after Step (H) is completed.
 
Step (I): Gate dielectric and gate electrode regions are deposited or grown. Examples of gate dielectrics include hafnium oxide, silicon dioxide, etc. Examples of gate electrodes include polysilicon, TiN, TaN, etc. A CMP is conducted after gate electrode deposition. Following this, rest of the process flow for forming transistors, contacts and wires for the top layer continues.  FIG. 9I  illustrates the structure after Step (I) is completed.  FIG. 9J  shows a cross-sectional view of structures after Step (I). It is clear that two nanowires are present for each transistor in the figure. It is possible to have one nanowire per transistor or more than two nanowires per transistor by changing the number of stacked Si/SiGe layers. Note that top-level transistors are formed well-aligned to bottom-level wiring and transistor layers. Since the top-level transistor layers are very thin (preferably less than 200 nm), the top transistors can be aligned to features in the bottom-level. While the process flow shown in  FIG. 9A-J  gives the key steps involved in forming a four-side gated JLT with 3D stacked components, it is conceivable to one skilled in the art that changes to the process can be made. For example, process steps and additional materials/regions to add strain to junctionless transistors can be added. Furthermore, more than two layers of chips or circuits can be 3D stacked. Also, there are many methods to construct silicon nanowire transistors and these are described in “High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling,”  Electron Devices Meeting  ( IEDM ), 2009  IEEE International , vol., no., pp. 1-4, 7-9 Dec. 2009 by Bangsaruntip, S.; Cohen, G. M.; Majumdar, A.; et al. (“Bangsaruntip”) and in “High performance 5 nm radius twin silicon nanowire MOSFET(TSNWFET): Fabrication on bulk Si wafer, characteristics, and reliability,” in  Proc. IEDM Tech. Dig.,  2005, pp. 717-720 by S. D. Suk, S.-Y. Lee, S.-M. Kim, et al. (“Suk”). Contents of these publications are incorporated herein by reference. Techniques described in these publications can be utilized for fabricating four-side gated JLTs without junctions as well.
 
       FIGS. 9K-V  describes an alternative process flow for forming four-side gated JLTs in 3D stacked circuits and chips. It may include several steps as described in the following sequence. 
     Step (A): The bottom layer of the 2 chip 3D stack is processed with transistors and wires. This is indicated in the figure as bottom layer of transistors and wires  950 . Above this, a silicon dioxide layer  952  is deposited.  FIG. 9K  illustrates the structure after Step (A) is completed.
 
Step (B): A n+ Si wafer  954  that has its dopants activated is now taken. Alternatively, a p− Si wafer that has n+ dopants implanted and activated can be used.  FIG. 9L  shows the structure after Step (B) is completed.
 
Step (C): Hydrogen ions are implanted into the n+ Si wafer  954  at a certain depth.  FIG. 9M  shows the structure after Step (C) is completed. The plane of hydrogen ions is indicated as Hydrogen  954 .
 
Step (D): The wafer after step (C) is bonded to a temporary carrier wafer  960  using a temporary bonding adhesive  958 . This temporary carrier wafer  960  could be constructed of glass. Alternatively, it could be constructed of silicon. The temporary bonding adhesive  958  could be a polymer material, such as a polyimide.  FIG. 9N  illustrates the structure after Step (D) is completed.
 
Step (E): A anneal or a sideways mechanical force is utilized to cleave the wafer at the hydrogen plane  954 . A CMP process is then conducted.  FIG. 9O  shows the structure after Step (E) is completed.
 
Step (F): Layers of gate dielectric material  966 , gate electrode material  968  and silicon oxide  964  are deposited onto the bottom of the wafer shown in Step (E).  FIG. 9P  illustrates the structure after Step (F) is completed.
 
Step (G): The wafer is then bonded to the bottom layer of wires and transistors  950  using oxide-to-oxide bonding.  FIG. 9Q  illustrates the structure after Step (G) is completed.
 
Step (H): The temporary carrier wafer  960  is then removed by shining a laser onto the temporary bonding adhesive  958  through the temporary carrier wafer  960  (which could be constructed of glass). Alternatively, an anneal could be used to remove the temporary bonding adhesive  958 .  FIG. 9R  illustrates the structure after Step (H) is completed.
 
Step (I): The layer of n+ Si  962  and gate dielectric material  966  are patterned and etched using a lithography and etch step.  FIG. 9S  illustrates the structure after this step. The patterned layer of n+ Si  970  and the patterned gate dielectric for the back gate (gate dielectric  980 ) are shown. Oxide is deposited and polished by CMP to planarize the surface and form a region of silicon dioxide  974 .
 
Step (J): The oxide layer  974  and gate electrode material  968  are patterned and etched to form a region of silicon dioxide  978  and back gate electrode  976 .  FIG. 9T  illustrates the structure after this step.
 
Step (K): A silicon dioxide layer is deposited. The surface is then planarized with CMP to form the region of silicon dioxide  982 .  FIG. 9U  illustrates the structure after this step.
 
Step (L): Trenches are etched in the region of silicon dioxide  982 . A thin layer of gate dielectric and a thicker layer of gate electrode are then deposited and planarized. Following this, a lithography and etch step are performed to etch the gate dielectric and gate electrode.  FIG. 9V  illustrates the structure after these steps. The device structure after these process steps may include a front gate electrode  984  and a dielectric for the front gate  986 . Contacts can be made to the front gate electrode  984  and back gate electrode  976  after oxide deposition and planarization. Note that top-level transistors are formed well-aligned to bottom-level wiring and transistor layers. While the process flow shown in  FIGS. 9K-V  shows several steps involved in forming a four-side gated JLT with 3D stacked components, it is conceivable to one skilled in the art that changes to the process can be made. For example, process steps and additional materials/regions to add strain to junction-less transistors can be added.
 
     All the types of embodiments of this invention described in Section 1.1 utilize single crystal silicon or monocrystalline silicon transistors. Thicknesses of layer transferred regions of silicon are &lt;2 um, and many times can be &lt;1 um or &lt;0.4 um or even &lt;0.2 um. Interconnect (wiring) layers are preferably constructed substantially of copper or aluminum or some other high conductivity material. 
     Section 1.2: Recessed Channel Transistors as a Building Block for 3D Stacked Circuits and Chips 
     Another method to solve the issue of high-temperature source-drain junction processing is an innovative use of recessed channel inversion-mode transistors as a building block for 3D stacked semiconductor circuits and chips. The transistor structures described in this section can be considered horizontally-oriented transistors where current flow occurs between horizontally-oriented source and drain regions. The term planar transistor can also be used for the same in this document. The recessed channel transistors in this section are defined by a process including a step of etch to form the transistor channel. 3D stacked semiconductor circuits and chips using recessed channel transistors preferably have interconnect (wiring) layers including copper or aluminum or a material with higher conductivity. 
       FIGS. 10A-D  shows different types of recessed channel inversion-mode transistors constructed atop a bottom layer of transistors and wires  1004 .  FIG. 10A  depicts a standard recessed channel transistor where the recess is made up to the p− region. The angle of the recess, Alpha  1002 , can be anywhere in between 90° and 180°. A standard recessed channel transistor where angle Alpha &gt;90° can also be referred to as a V-shape transistor or V-groove transistor.  FIG. 10B  depicts a RCAT (Recessed Channel Array Transistor) where part of the p− region is consumed by the recess.  FIG. 10C  depicts a S-RCAT (Spherical RCAT) where the recess in the p− region is spherical in shape.  FIG. 10D  depicts a recessed channel Finfet. 
       FIGS. 11A-F  shows a procedure for layer transfer of silicon regions required for recessed channel transistors. Silicon regions that are layer transferred are &lt;2 um in thickness, and can be thinner than 1 um or even 0.4 um. The process flow in  FIGS. 11A-F  may include several steps as described in the following sequence: 
     Step (A): A silicon dioxide layer  1104  is deposited above the generic bottom layer  1102 .  FIG. 11A  illustrates the structure after Step (A). 
     Step (B): A wafer of p−Si  1106  is implanted with n+ near its surface to form a layer of n+ Si  1108 .  FIG. 11B  illustrates the structure after Step (B). 
     Step (C): A layer of p− Si  1110  is epitaxially grown atop the layer of n+ Si  1108 . A layer of silicon dioxide  1112  is deposited atop the layer of p− Si  1110 . An anneal (such as a rapid thermal anneal RTA or spike anneal or laser anneal) is conducted to activate dopants. Note that the terms laser anneal and optical anneal are used interchangeably in this document.  FIG. 11C  illustrates the structure after Step (C). Alternatively, the n+ Si layer  1108  and p− Si layer  1110  can be formed by a buried layer implant of n+ Si in the p− Si wafer  1106 .
 
Step (D): Hydrogen H+ is implanted into the n+ Si layer  1108  at a certain depth  1114 . Alternatively, another atomic species such as helium can be implanted.  FIG. 11D  illustrates the structure after Step (D).
 
Step (E): The top layer wafer shown after Step (D) is flipped and bonded atop the bottom layer wafer using oxide-to-oxide bonding.  FIG. 11E  illustrates the structure after Step (E).
 
Step (F): A cleave operation is performed at the hydrogen plane  1114  using an anneal. Alternatively, a sideways mechanical force may be used. Following this, a Chemical-Mechanical-Polish (CMP) is done. It should be noted that the layer-transfer including the bonding and the cleaving could be done without exceeding 400° C. This is the case in various alternatives of this invention.  FIG. 11F  illustrates the structure after Step (F).
 
       FIGS. 12A-F  describes a process flow for forming 3D stacked circuits and chips using standard recessed channel inversion-mode transistors. The process flow in  FIGS. 12A-F  may include several steps as described in the following sequence: 
     Step (A): The bottom layer of the 2 chip 3D stack is processed with transistors and wires. This is indicated in the figure as bottom layer of transistors and wires  1202 . Above this, a silicon dioxide layer  1204  is deposited.  FIG. 12A  illustrates the structure after Step (A).
 
Step (B): Using the procedure shown in  FIGS. 11A-F , a p− Si layer  1205  and n+ Si layer  1207  are transferred atop the structure shown after Step (A).  FIG. 12B  illustrates the structure after Step (B).
 
Step (C): The stack shown after Step (A) is patterned lithographically and etched such that silicon regions are present only in regions where transistors are to be formed. Using a standard shallow trench isolation (STI) process, isolation regions in between transistor regions are formed. These oxide regions are indicated as  1216 .  FIG. 12C  illustrates the structure after Step (C). Regions of n+ Si  1209  and p− Si  1206  are left after this step.
 
Step (D): Using litho and etch, a recessed channel is formed by etching away the n+ Si region  1209  where gates need to be formed. Little or none of the p− Si region  1206  is removed.  FIG. 12D  illustrates the structure after Step (D).
 
Step (E): The gate dielectric material and the gate electrode material are deposited, following which a CMP process is utilized for planarization. The gate dielectric material could be hafnium oxide. Alternatively, silicon dioxide can be used. Other types of gate dielectric materials such as Zirconium oxide can be utilized as well. The gate electrode material could be Titanium Nitride. Alternatively, other materials such as TaN, W, Ru, TiAlN, polysilicon could be used. Litho and etch are conducted to leave the gate dielectric material  1210  and the gate electrode material  1212  only in regions where gates are to be formed.  FIG. 12E  illustrates the structure after Step (E).
 
Step (F): An oxide layer  1214  is deposited and polished with CMP. Following this, rest of the process flow continues, with contact and wiring layers being formed.  FIG. 12F  illustrates the structure after Step (F).
 
It is apparent based on the process flow shown in  FIGS. 12A-F  that no process step requiring greater than 400° C. is required after stacking the top layer of transistors above the bottom layer of transistors and wires. While the process flow shown in  FIGS. 12A-F  gives the key steps involved in forming a standard recessed channel transistor for 3D stacked circuits and chips, it is conceivable to one skilled in the art that changes to the process can be made. For example, process steps and additional materials/regions to add strain to the standard recessed channel transistors can be added. Furthermore, more than two layers of chips or circuits can be 3D stacked. Note that top-level transistors are formed well-aligned to bottom-level wiring and transistor layers. This, in turn, is due to top-level transistor layers being very thin (preferably less than 200 nm). One can see through these thin silicon layers and align to features at the bottom-level.
 
       FIGS. 13A-F  depicts a process flow for constructing 3D stacked logic circuits and chips using RCATs (recessed channel array transistors). These types of devices are typically used for constructing 2D DRAM chips. These devices can be utilized for forming 3D stacked circuits and chips with no process steps performed at greater than 400° C. (after wafer to wafer bonding). The process flow in  FIGS. 13A-F  may include several steps in the following sequence: 
     Step (A): The bottom layer of the 2 chip 3D stack is processed with transistors and wires. This is indicated in the figure as bottom layer of transistors and wires  1302 . Above this, a silicon dioxide layer  1304  is deposited.  FIG. 13A  illustrates the structure after Step (A).
 
Step (B): Using the procedure shown in  FIGS. 11A-F , a p− Si layer  1305  and n+ Si layer  1307  are transferred atop the structure shown after Step (A).  FIG. 13B  illustrates the structure after Step (B).
 
Step (C): The stack shown after Step (A) is patterned lithographically and etched such that silicon regions are present only in regions where transistors are to be formed. Using a standard shallow trench isolation (STI) process, isolation regions in between transistor regions are formed.  FIG. 13C  illustrates the structure after Step (C). n+ Si regions after this step are indicated as n+ Si  1308  and p− Si regions after this step are indicated as p− Si  1306 . Oxide regions are indicated as Oxide  1314 .
 
Step (D): Using litho and etch, a recessed channel is formed by etching away the n+ Si region  1308  and p− Si region  1306  where gates need to be formed. A chemical dry etch process is described in “The breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor (RCAT) for 88 nm feature size and beyond,”  VLSI Technology,  2003 . Digest of Technical Papers.  2003  Symposium on , vol., no., pp. 11-12, 10-12 Jun. 2003 by Kim, J. Y.; Lee, C. S.; Kim, S. E., et al. (“J. Y. Kim”). A variation of this process from J. Y. Kim can be utilized for rounding corners, removing damaged silicon, etc after the etch. Furthermore, Silicon Dioxide can be formed using a plasma-enhanced thermal oxidation process, this oxide can be etched-back as well to reduce damage from etching silicon.  FIG. 13D  illustrates the structure after Step (D). n+ Si regions after this step are indicated as n+ Si  1309  and p− Si regions after this step are indicated as p− Si  1311 ,
 
Step (E): The gate dielectric material and the gate electrode material are deposited, following which a CMP process is utilized for planarization. The gate dielectric material could be hafnium oxide. Alternatively, silicon dioxide can be used. Other types of gate dielectric materials such as Zirconium oxide can be utilized as well. The gate electrode material could be Titanium Nitride. Alternatively, other materials such as TaN, W, Ru, TiAlN, polysilicon could be used. Litho and etch are conducted to leave the gate dielectric material  1310  and the gate electrode material  1312  only in regions where gates are to be formed.  FIG. 13E  illustrates the structure after Step (E).
 
Step (F): An oxide layer  1320  is deposited and polished with CMP. Following this, rest of the process flow continues, with contact and wiring layers being formed.  FIG. 13F  illustrates the structure after Step (F).
 
It is apparent based on the process flow shown in  FIGS. 13A-F  that no process step at greater than 400° C. is required after stacking the top layer of transistors above the bottom layer of transistors and wires. While the process flow shown in  FIGS. 13A-F  gives several steps involved in forming a RCATs for 3D stacked circuits and chips, it is conceivable to one skilled in the art that changes to the process can be made. For example, process steps and additional materials/regions to add strain to RCATs can be added. Furthermore, more than two layers of chips or circuits can be 3D stacked. Note that top-level transistors are formed well-aligned to bottom-level wiring and transistor layers. This, in turn, is due to top-level transistor layers being very thin (preferably less than 200 nm). One can look through these thin silicon layers and align to features at the bottom-level. Due to their extensive use in the DRAM industry, several technologies exist to optimize RCAT processes and devices. These are described in “The breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor (RCAT) for 88 nm feature size and beyond,”  VLSI Technology,  2003 . Digest of Technical Papers.  2003  Symposium on , vol., no., pp. 11-12, 10-12 Jun. 2003 by Kim, J. Y.; Lee, C. S.; Kim, S. E., et al. (“J. Y. Kim”), “The excellent scalability of the RCAT (recess-channel-array-transistor) technology for sub-70 nm DRAM feature size and beyond,”  VLSI Technology,  2005. ( VLSI - TSA - Tech ). 2005  IEEE VLSI - TSA International Symposium on , vol., no., pp. 33-34, 25-27 Apr. 2005 by Kim, J. Y.; Woo, D. S.; Oh, H. J., et al. (“Kim”) and “Implementation of HfSiON gate dielectric for sub-60 nm DRAM dual gate oxide with recess channel array transistor (RCAT) and tungsten gate,”  Electron Devices Meeting,  2004 . IEEE International , vol., no., pp. 515-518, 13-15 Dec. 2004 by Seong Geon Park; Beom Jun Jin; Hye Lan Lee, et al. (“S. G. Park”). It is conceivable to one skilled in the art that RCAT process and device optimization outlined by J. Y. Kim, Kim, S. G. Park and others can be applied to 3D stacked circuits and chips using RCATs as a building block.
 
     While  FIGS. 13A-F  showed the process flow for constructing RCATs for 3D stacked chips and circuits, the process flow for S-RCATs shown in  FIG. 10C  is not very different. The main difference for a S-RCAT process flow is the silicon etch in Step (D) of  FIGS. 13A-F . A S-RCAT etch is more sophisticated, and an oxide spacer is used on the sidewalls along with an isotropic dry etch process. Further details of a S-RCAT etch and process are given in “S-RCAT (sphere-shaped-recess-channel-array transistor) technology for 70 nm DRAM feature size and beyond,”  Digest of Technical Papers.  2005  Symposium on VLSI Technology,  2005 pp. 34-35, 14-16 Jun. 2005 by Kim, J. V.; Oh, H. J.; Woo, D. S., et al. (“J. V. Kim”) and “High-density low-power-operating DRAM device adopting 6F 2  cell scheme with novel S-RCAT structure on 80 nm feature size and beyond,”  Solid - State Device Research Conference,  2005 . ESSDERC  2005 . Proceedings of  35 th European , vol., no., pp. 177-180, 12-16 Sep. 2005 by Oh, H. J.; Kim, J. Y.; Kim, J. H, et al. (“Oh”). The contents of the above publications are incorporated herein by reference. 
     The recessed channel Finfet shown in  FIG. 10D  can be constructed using a simple variation of the process flow shown in  FIGS. 13A-F . A recessed channel Finfet technology and its processing details are described in “Highly Scalable Saddle-Fin (S-Fin) Transistor for Sub-50 nm DRAM Technology,”  VLSI Technology,  2006 . Digest of Technical Papers.  2006  Symposium on , vol., no., pp. 32-33 by Sung-Woong Chung; Sang-Don Lee; Se-Aug Jang, et al. (“S-W Chung”) and “A Proposal on an Optimized Device Structure With Experimental Studies on Recent Devices for the DRAM Cell Transistor,”  Electron Devices, IEEE Transactions on , vol. 54, no. 12, pp. 3325-3335, December 2007 by Myoung Jin Lee; Seonghoon Jin; Chang-Ki Baek, et al. (“M. J. Lee”). Contents of these publications are incorporated herein by reference. 
     Section 1.3: Improvements and Alternatives 
     Various methods, technologies and procedures to improve devices shown in Section 1.1 and Section 1.2 are given in this section. Single crystal silicon (this term used interchangeably with monocrystalline silicon) is used for constructing transistors in Section 1.3. Thickness of layer transferred silicon is typically &lt;2 um or &lt;1 um or could be even less than 0.2 um, unless stated otherwise. Interconnect (wiring) layers are constructed substantially of copper or aluminum or some other higher conductivity material. The term planar transistor or horizontally oriented transistor could be used to describe any constructed transistor where source and drain regions are in the same horizontal plane and current flows between them. 
     Section 1.3.1: Construction of Circuits with Sub-400° C. Processed Transistors 
       FIGS. 14A-I  show procedures for constructing circuits using sub-400° C. processed transistors (i.e. junction-less transistors and recessed channel transistors) described thus far in this document. When doing layer transfer for junction-less transistors and recessed channel transistors, it is easy to construct just nMOS transistors in a layer or just pMOS transistors in a layer. However, constructing circuits requires both nMOS transistors and pMOS transistors, so it requires additional ideas. 
       FIG. 14A  shows one procedure for forming circuits. nMOS and pMOS layers of circuits are stacked atop each other. A layer of n-channel sub-400° C. transistors (with none or one or more wiring layers)  1406  is first formed over a bottom layer of transistors and wires  1402 . Following this, a layer of p-channel sub-400° C. transistors (with none or one or more wiring layers)  1410  is formed. This structure is important since circuits typically require both n-channel and p-channel transistors. A high density of connections exist between different layers  1402 ,  1406  and  1410 . The p-channel wafer  1410  could have its own optimized crystal structure that improves mobility of p-channel transistors while the n-channel wafer  1406  could have its own optimized crystal structure that improves mobility of n-channel transistors. For example, it is known that mobility of p-channel transistors is maximum in the (110) plane while the mobility of n-channel transistors is maximum in the (100) plane. The wafers  1410  and  1406  could have these optimized crystal structures. 
       FIGS. 14B-F  shows another procedure for forming circuits that utilizes junction-less transistors and repeating layouts in one direction. The procedure may include several steps, in the following sequence: 
     Step (1): A bottom layer of transistors and wires  1414  is first constructed above which a layer of landing pads  1418  is constructed. A layer of silicon dioxide  1416  is then constructed atop the layer of landing pads  1418 . Size of the landing pads  1418  is W x + delta (W x ) in the X direction, where W x  is the distance of one repeat of the repeating pattern in the (to be constructed) top layer. delta(W x ) is an offset added to account for some overlap into the adjacent region of the repeating pattern and some margin for rotational (angular) misalignment within one chip (IC). Size of the landing pads  1418  is F or 2F plus a margin for rotational misalignment within one chip (IC) or higher in the Y direction, where F is the minimum feature size. Note that the terms landing pad and metal strip are used interchangeably in this document.  FIG. 14B  is a drawing illustration after Step (1).
 
Step (2): A top layer having regions of n+ Si  1424  and p+Si  1422  repeating over-and-over again is constructed atop a p− Si wafer  1420 . The pattern repeats in the X direction with a repeat distance denoted by W. In the Y direction, there is no pattern at all; the wafer is completely uniform in that direction. This ensures misalignment in the Y direction does not impact device and circuit construction, except for any rotational misalignment causing difference between the left and right side of one IC. A maximum rotational (angular) misalignment of 0.5 um over a 200 mm wafer results in maximum misalignment within one 10 by 10 mm IC of 25 nm in both X and Y direction. Total misalignment in the X direction is much larger, which is addressed in this invention as shown in the following steps.  FIG. 14C  shows a drawing illustration after Step (2).
 
Step (3): The top layer shown in Step (2) receives an H+ implant to create the cleaving plane in the p− silicon region and is flipped and bonded atop the bottom layer shown in Step (1). A procedure similar to the one shown in  FIGS. 2A-E  is utilized for this purpose. Note that the top layer shown in Step (2) has had its dopants activated with an anneal before layer transfer. The top layer is cleaved and the remaining p− region is etched or polished (CMP) away until only the N+ and P+ stripes remain. During the bonding process, a misalignment can occur in X and Y directions, while the angular alignment is typically small. This is because the misalignment is due to factors like wafer bow, wafer expansion due to thermal differences between bonded wafers, etc; these issues do not typically cause angular alignment problems, while they impact alignment in X and Y directions.
 
Since the width of the landing pads is slightly wider than the width of the repeating n and p pattern in the X-direction and there&#39;s no pattern in the Y direction, the circuitry in the top layer can shifted left or right and up or down until the layer-to-layer contacts within the top circuitry are placed on top of the appropriate landing pad. This is further explained below:
 
Let us assume that after the bonding process, co-ordinates of alignment mark of the top wafer are (x top , y top ) while co-ordinates of alignment mark of the bottom wafer are (x bottom , y bottom ).  FIG. 14D  shows a drawing illustration after Step (3).
 
Step (4): A virtual alignment mark is created by the lithography tool. X co-ordinate of this virtual alignment mark is at the location (x top +(an integer k)*W x ). The integer k is chosen such that modulus or absolute value of (x top +(integer k)*W x −x bottom )&lt;=W x /2. This guarantees that the X co-ordinate of the virtual alignment mark is within a repeat distance (or within the same section of width W x ) of the X alignment mark of the bottom wafer. Y co-ordinate of this virtual alignment mark is y bottom  (since silicon thickness of the top layer is thin, the lithography tool can see the alignment mark of the bottom wafer and compute this quantity). Though-silicon connections  1428  are now constructed with alignment mark of this mask aligned to the virtual alignment mark. The terms through via or through silicon vias can be used interchangeably with the term through-silicon connections in this document. Since the X co-ordinate of the virtual alignment mark is within the same ((p+)-oxide-(n+)-oxide) repeating pattern (of length W x ) as the bottom wafer X alignment mark, the through-silicon connection  1428  always falls on the bottom landing pad  1418  (the bottom landing pad length is W x  added to delta (W x ), and this spans the entire length of the repeating pattern in the X direction).  FIG. 14E  is a drawing illustration after Step (4).
 
Step (5): n channel and p channel junctionless transistors are constructed aligned to the virtual alignment mark.  FIG. 14F  is a drawing illustration after Step (5).
 
From steps (1) to (5), it is clear that 3D stacked semiconductor circuits and chips can be constructed with misalignment tolerance techniques. Essentially, a combination of 3 key ideas—repeating patterns in one direction of length W x , landing pads of length (W x + delta (W x )) and creation of virtual alignment marks—are used such that even if misalignment occurs, through silicon connections fall on their respective landing pads. While the explanation in  FIGS. 14B-F  is shown for a junction-less transistor, similar procedures can also be used for recessed channel transistors. Thickness of the transferred single crystal silicon or monocrystalline silicon layer is less than 2 um, and can be even lower than 1 um or 0.4 um or 0.2 um.
 
       FIGS. 14G-I  shows yet another procedure for forming circuits with processing temperatures below 400° C. such as the junction-less transistor and recessed channel transistors. While the explanation in  FIGS. 14G-I  is shown for a junction-less transistor, similar procedures can also be used for recessed channel transistors. The procedure may include several steps as described in the following sequence: 
     Step (A): A bottom wafer  1438  is processed with a bottom transistor layer  1436  and a bottom wiring layer  1434 . A layer of silicon oxide  1430  is deposited above it.  FIG. 14G  is a drawing illustration after Step (A). 
     Step (B): Using a procedure similar to  FIGS. 2A-E  (as was presented in  FIGS. 5A-F ), layers of n+Si  1444  and p+ Si  1448  are transferred above the bottom wafer  1438  one after another. The top wafer  1440  therefore include a bilayer of n+ and p+ Si.  FIG. 14H  is a drawing illustration after Step (B).
 
Step (C): p-channel junctionless transistors  1450  of the circuit can be formed on the p+ Si layer  1448  with standard procedures. For n-channel junction-less transistors  1452  of the  circuit, one needs to etch through the p+ layer  1448  to reach the n+ Si layer  1444 . Transistors are then constructed on the n+ Si  1444 . Due to depth-of-focus issues associated with lithography, one requires separate lithography steps while constructing different parts of re-channel and p-channel transistors.  FIG. 14I  is a drawing illustration after Step (C).
 
Section 1.3.2: Accurate Transfer of Thin Layers of Silicon with Ion-Cut
 
     It is often desirable to transfer very thin layers of silicon (&lt;100 nm) atop a bottom layer of transistors and wires using the ion-cut technique. For example, for the process flow in  FIGS. 11A-F , it may be desirable to have very thin layers (&lt;100 nm) of n+ Si  1109 . In that scenario, implanting hydrogen and cleaving the n+ region may not give the exact thickness of n+ Si desirable for device operation. An improved process for addressing this issue is shown in FIGS.  15 A-F. The process flow in  FIGS. 15A-F  may include several steps as described in the following sequence: 
     Step (A): A silicon dioxide layer  1504  is deposited above the generic bottom layer  1502 .  FIG. 15A  illustrates the structure after Step (A). 
     Step (B): An SOI wafer  1506  is implanted with n+ near its surface to form a n+ Si layer  1508 . The buried oxide (BOX) of the SOI wafer is silicon dioxide  1505 .  FIG. 15B  illustrates the structure after Step (B). 
     Step (C): A p− Si layer  1510  is epitaxially grown atop the n+ Si layer  1508 . A silicon dioxide layer  1512  is deposited atop the p− Si layer  1510 . An anneal (such as a rapid thermal anneal RTA or spike anneal or laser anneal) is conducted to activate dopants.
 
Alternatively, the n+ Si layer  1508  and p− Si layer  1510  can be formed by a buried layer implant of n+ Si in a p− SOI wafer.
 
Hydrogen is then implanted into the p− Si layer  1506  at a certain depth  1514 . Alternatively, another atomic species such as helium can be implanted or co-implanted.  FIG. 15C  illustrates the structure after Step (C).
 
Step (D): The top layer wafer shown after Step (C) is flipped and bonded atop the bottom layer wafer using oxide-to-oxide bonding.  FIG. 15D  illustrates the structure after Step (D).
 
Step (E): A cleave operation is performed at the hydrogen plane  1514  using an anneal. Alternatively, a sideways mechanical force may be used. Following this, an etching process that etches Si but does not etch silicon dioxide is utilized to remove the p− Si layer  1506  remaining after cleave. The buried oxide (BOX)  1505  acts as an etch stop.  FIG. 15E  illustrates the structure after Step (E).
 
Step (F): Once the etch stop  1505  is reached, an etch or CMP process is utilized to etch the silicon dioxide layer  1505  till the n+ silicon layer  1508  is reached. The etch process for Step (F) is preferentially chosen so that it etches silicon dioxide but does not attack Silicon.  FIG. 15F  illustrates the structure after Step (F).
 
It is clear from the process shown in  FIGS. 15A-F  that one can get excellent control of the n+ layer  1508 &#39;s thickness after layer transfer.
 
     While the process shown in  FIGS. 15A-F  results in accurate layer transfer of thin regions, it has some drawbacks. SOI wafers are typically quite costly, and utilizing an SOI wafer just for having an etch stop layer may not always be economically viable. In that case, an alternative process shown in  FIGS. 16A-F  could be utilized. The process flow in  FIGS. 16A-F  may include several steps as described in the following sequence: 
     Step (A): A silicon dioxide layer  1604  is deposited above the generic bottom layer  1602 .  FIG. 16A  illustrates the structure after Step (A). 
     Step (B): A n− Si wafer  1606  is implanted with boron doped p+ Si near its surface to form a p+ Si layer  1605 . The p+ layer is doped above 1E20/cm 3 , and preferably above 1E21/cm 3 . It may be possible to use a p− Si layer instead of the p+ Si layer  1605  as well, and still achieve similar results. A p− Si wafer can be utilized instead of the n− Si wafer  1606  as well.  FIG. 16B  illustrates the structure after Step (B).
 
Step (C): A n+ Si layer  1608  and a p− Si layer  1610  are epitaxially grown atop the p+ Si layer  1605 . A silicon dioxide layer  1612  is deposited atop the p− Si layer  1610 . An anneal (such as a rapid thermal anneal RTA or spike anneal or laser anneal) is conducted to activate dopants. Alternatively, the p+ Si layer  1605 , the n+ Si layer  1608  and the p− Si layer  1610  can be formed by a series of implants on a n− Si wafer  1606 .
 
Hydrogen is then implanted into the p− Si layer  1606  at a certain depth  1614 . Alternatively, another atomic species such as helium can be implanted.  FIG. 16C  illustrates the structure after Step (C).
 
Step (D): The top layer wafer shown after Step (C) is flipped and bonded atop the bottom layer wafer using oxide-to-oxide bonding.  FIG. 16D  illustrates the structure after Step (D).
 
Step (E): A cleave operation is performed at the hydrogen plane  1614  using an anneal. Alternatively, a sideways mechanical force may be used. Following this, an etching process that etches the n− Si layer  1606  but does not etch the p+ Si etch stop layer  1605  is utilized to etch through the n− Si layer  1606  remaining after cleave. Examples of etching agents that etch n− Si or p− Si but do not attack p+ Si doped above 1E20/cm 3  include KOH, EDP (ethylenediamine/pyrocatechol/water) and hydrazine.  FIG. 16E  illustrates the structure after Step (E).
 
Step (F): Once the etch stop  1605  is reached, an etch or CMP process is utilized to etch the p+ Si layer  1605  till the n+ silicon layer  1608  is reached.  FIG. 16F  illustrates the structure after Step (F).
 
It is clear from the process shown in  FIGS. 16A-F  that one can get excellent control of the n+ layer  1608 &#39;s thickness after layer transfer.
 
     While silicon dioxide and p+ Si were utilized as etch stop layers in  FIGS. 15A-F  and  FIGS. 16A-F  respectively, other etch stop layers such as SiGe could be utilized. An etch stop layer of SiGe can be incorporated in the middle of the structure shown in  FIGS. 16A-F  using an epitaxy process. 
     Section 1.3.3: Alternative Low-Temperature (Sub-300° C.) Ion-Cut Process for Sub-400° C. Processed Transistors 
     An alternative low-temperature ion-cut process is described in  FIGS. 17A-E . The process flow in  FIGS. 17A-E  may include several steps as described in the following sequence: 
     Step (A): A silicon dioxide layer  1704  is deposited above the generic bottom layer  1702 .  FIG. 17A  illustrates the structure after Step (A). 
     Step (B): A p− Si wafer  1706  is implanted with boron doped p+ Si near its surface to form a p+ Si layer  1705 . A n− Si wafer can be utilized instead of the p− Si wafer  1606  as well.  FIG. 17B  illustrates the structure after Step (B). 
     Step (C): A n+ Si layer  1708  and a p− Si layer  1710  are epitaxially grown atop the p+ Si layer  1705 . A silicon dioxide layer  1712  is grown or deposited atop the p− Si layer  1710 . An anneal (such as a rapid thermal anneal RTA or spike anneal or laser anneal) is conducted to activate dopants.
 
Alternatively, the p+ Si layer  1705 , the n+ Si layer  1708  and the p− Si layer  1710  can be formed by a series of implants on a p− Si wafer  1706 .
 
Hydrogen is then implanted into the p− Si layer  1706  at a certain depth  1714 . Alternatively, another atomic species such as helium can be (co-)implanted.  FIG. 17C  illustrates the structure after Step (C).
 
Step (D): The top layer wafer shown after Step (C) is flipped and bonded atop the bottom layer wafer using oxide-to-oxide bonding.  FIG. 17D  illustrates the structure after Step (D).
 
Step (E): A cleave operation is performed at the hydrogen plane  1714  using a sub-300° C. anneal. Alternatively, a sideways mechanical force may be used. An etch or CMP process is utilized to etch the p+ Si layer  1705  till the n+ silicon layer  1708  is reached.  FIG. 17E  illustrates the structure after Step (E).
 
The purpose of hydrogen implantation into the p+ Si region  1705  is because p+ regions heavily doped with boron are known to require lower anneal temperature required for ion-cut. Further details of this technology/process are given in “Cold ion-cutting of hydrogen implanted Si, Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms”, Volume 190, Issues 1-4, May 2002, Pages 761-766, ISSN 0168-583X by K. Henttinen, T. Suni, A. Nurmela, et al. (“Hentinnen and Suni”). The contents of these publications are incorporated herein by reference.
 
Section 1.3.4: Alternative Procedures for Layer Transfer
 
     While ion-cut has been described in previous sections as the method for layer transfer, several other procedures exist that fulfill the same objective. These include: 
     Lift-off or laser lift-off: Background information for this technology is given in “Epitaxial lift-off and its applications”, 1993 Semicond. Sci. Technol. 8 1124 by P Demeester et al. (“Demeester”). 
     Porous-Si approaches such as ELTRAN: Background information for this technology is given in “Eltran, Novel SOI Wafer Technology”, JSAP International, Number 4, July 2001 by T. Yonehara and K. Sakaguchi (“Yonehara”) and also in “Frontiers of silicon-on-insulator,” J. Appl. Phys. 93, 4955-4978, 2003 by G. K. Celler and S. Cristoloveanu (“Celler”).
 
Time-controlled etch-back to thin an initial substrate, Polishing, Etch-stop layer controlled etch-back to thin an initial substrate: Background information on these technologies is given in Celler and in U.S. Pat. No. 6,806,171.
 
Rubber-stamp based layer transfer: Background information on this technology is given in “Solar cells sliced and diced”, 19 May 2010, Nature News.
 
The above publications giving background information on various layer transfer procedures are incorporated herein by reference. It is obvious to one skilled in the art that one can form 3D integrated circuits and chips as described in this document with layer transfer schemes described in these publications.
 
       FIGS. 18A-F  shows a procedure using etch-stop layer controlled etch-back for layer transfer. The process flow in  FIGS. 18A-F  may include several steps in the following sequence: 
     Step (A): A silicon dioxide layer  1804  is deposited above the generic bottom layer  1802 .  FIG. 18A  illustrates the structure after Step (A). 
     Step (B): A SOI wafer  1806  is implanted with n+ near its surface to form a n+ Si layer  1808 . The buried oxide (BOX) of the SOI wafer is silicon dioxide  1805 .  FIG. 18B  illustrates the structure after Step (B). 
     Step (C): A p− Si layer  1810  is epitaxially grown atop the n+ Si layer  1808 . A silicon dioxide layer  1812  is grown/deposited atop the p− Si layer  1810 . An anneal (such as a rapid thermal anneal RTA or spike anneal or laser anneal) is conducted to activate dopants.  FIG. 18C  illustrates the structure after Step (C).
 
Alternatively, the n+ Si layer  1808  and p− Si layer  1810  can be formed by a buried layer implant of n+ Si in a p− SOI wafer.
 
Step (D): The top layer wafer shown after Step (C) is flipped and bonded atop the bottom layer wafer using oxide-to-oxide bonding.  FIG. 18D  illustrates the structure after Step (D).
 
Step (E): An etch process that etches Si but does not etch silicon dioxide is utilized to etch through the p− Si layer  1806 . The buried oxide (BOX) of silicon dioxide  1805  therefore acts as an etch stop.  FIG. 18E  illustrates the structure after Step (E).
 
Step (F): Once the etch stop  1805  is reached, an etch or CMP process is utilized to etch the silicon dioxide layer  1805  till the n+ silicon layer  1808  is reached. The etch process for Step (F) is preferentially chosen so that it etches silicon dioxide but does not attack Silicon.  FIG. 18F  illustrates the structure after Step (F).
 
At the end of the process shown in  FIGS. 18A-F , the desired regions are layer transferred atop the bottom layer  1802 . While  FIGS. 18A-F  shows an etch-stop layer controlled etch-back using a silicon dioxide etch stop layer, other etch stop layers such as SiGe or p+ Si can be utilized in alternative process flows.
 
       FIG. 19  shows various methods one can use to bond a top layer wafer  1908  to a bottom wafer  1902 . Oxide-oxide bonding of a layer of silicon dioxide  1906  and a layer of silicon dioxide  1904  is used. Before bonding, various methods can be utilized to activate surfaces of the layer of silicon dioxide  1906  and the layer of silicon dioxide  1904 . A plasma-activated bonding process such as the procedure described in US Patent 20090081848 or the procedure described in “Plasma-activated wafer bonding: the new low-temperature tool for MEMS fabrication”, Proc. SPIE 6589, 65890T (2007), DOI:10.1117/12.721937 by V. Dragoi, G. Mittendorfer, C. Thanner, and P. Lindner (“Dragoi”) can be used. Alternatively, an ion implantation process such as the one described in US Patent 20090081848 or elsewhere can be used. Alternatively, a wet chemical treatment can be utilized for activation. Other methods to perform oxide-to-oxide bonding can also be utilized. While oxide-to-oxide bonding has been described as a method to bond together different layers of the 3D stack, other methods of bonding such as metal-to-metal bonding can also be utilized. 
       FIGS. 20A-E  depict layer transfer of a Germanium or a III-V semiconductor layer to form part of a 3D integrated circuit or chip or system. These layers could be utilized for forming optical components or form forming better quality (higher-performance or lower-power) transistors.  FIGS. 20A-E  describes an ion-cut flow for layer transferring a single crystal Germanium or III-V semiconductor layer  2007  atop any generic bottom layer  2002 . The bottom layer  2002  can be a single crystal silicon layer or some other semiconductor layer. Alternatively, it can be a wafer having transistors with wiring layers above it. This process of ion-cut based layer transfer may include several steps as described in the following sequence: 
     Step (A): A silicon dioxide layer  2004  is deposited above the generic bottom layer  2002 .  FIG. 20A  illustrates the structure after Step (A). 
     Step (B): The layer to be transferred atop the bottom layer (top layer of doped germanium or III-V semiconductor  2006 ) is processed and a compatible oxide layer  2008  is deposited above it.  FIG. 20B  illustrates the structure after Step (B). 
     Step (C): Hydrogen is implanted into the Top layer doped Germanium or III-V semiconductor  2006  at a certain depth  2010 . Alternatively, another atomic species such as helium can be (co-) implanted.  FIG. 20C  illustrates the structure after Step (C). 
     Step (D): The top layer wafer shown after Step (C) is flipped and bonded atop the bottom layer wafer using oxide-to-oxide bonding.  FIG. 20D  illustrates the structure after Step (D). 
     Step (E): A cleave operation is performed at the hydrogen plane  2010  using an anneal or a mechanical force. Following this, a Chemical-Mechanical-Polish (CMP) is done.  FIG. 20E  illustrates the structure after Step (E). 
     Section 1.3.5: Laser Anneal Procedure for 3D Stacked Components and Chips 
       FIGS. 21A-C  describes a prior art process flow for constructing 3D stacked circuits and chips using laser anneal techniques. Note that the terms laser anneal and optical anneal are utilized interchangeably in this document. This procedure is described in “Electrical Integrity of MOS Devices in Laser Annealed 3D IC Structures” in the proceedings of VMIC 2004 by B. Rajendran, R. S. Shenoy, M. O. Thompson $ R. F. W. Pease. The process may include several steps as described in the following sequence: 
     Step (A): The bottom wafer  2112  is processed with transistor and wiring layers. The top wafer may include a layer of silicon  2110  with an oxide layer above it. The thickness of the silicon layer  2110 , t, is typically &gt;50 um.  FIG. 21A  illustrates the structure after Step (A).
 
Step (B): The top wafer  2114  is flipped and bonded to the bottom wafer  2112 . It can be readily seen that the thickness of the top layer is &gt;50 um. Due to this high thickness, and due to the fact that the aspect ratio (height to width ratio) of through-silicon connections is limited to &lt;100:1, it can be seen that the minimum width of through-silicon connections possible with this procedure is 50 um/100=500 nm. This is much higher than dimensions of horizontal wiring on a chip.  FIG. 21B  illustrates the structure after Step (B).
 
Step (C): Transistors are then built on the top wafer  2114  and a laser anneal is utilized to activate dopants in the top silicon layer. Due to the characteristics of a laser anneal, the temperature in the top layer  2114  will be much higher than the temperature in the bottom layer  2112 .  FIG. 21C  illustrates the structure after Step (C).
 
An alternative procedure described in prior art is the SOI-based layer transfer (shown in  FIG. 18A-F ) followed by a laser anneal. This process is described in “Sequential 3D IC Fabrication: Challenges and Prospects”, by Bipin Rajendran in VMIC 2006.
 
     An alternative procedure for laser anneal of layer transferred silicon is shown in  FIGS. 22A-E . The process may include several steps as described in the following sequence. 
     Step (A): A bottom wafer  2212  is processed with transistor, wiring and silicon dioxide layers.  FIG. 22A  illustrates the structure after Step (A). 
     Step (B): A top layer of silicon  2210  is layer transferred atop it using procedures similar to  FIG. 2 .  FIG. 22B  illustrates the structure after Step (B). 
     Step (C): Transistors are formed on the top layer of silicon  2210  and a laser anneal is done to activate dopants in source-drain regions  2216 . Fabrication of the rest of the integrated circuit flow including contacts and wiring layers may then proceed.  FIG. 22C  illustrates the structure after Step (C).
 
 FIG. 22(D)  shows that absorber layers  2218  may be used to efficiently heat the top layer of silicon  2224  while ensuring temperatures at the bottom wiring layer  2204  are low (&lt;500° C.).  FIG. 22(E)  shows that one could use heat protection layers  2220  situated in between the top and bottom layers of silicon to keep temperatures at the bottom wiring layer  2204  low (&lt;500° C.). These heat protection layers could be constructed of optimized materials that reflect laser radiation and reduce heat conducted to the bottom wiring layer. The terms heat protection layer and shield can be used interchangeably in this document.
 
     Most of the figures described thus far in this document assumed the transferred top layer of silicon is very thin (preferably &lt;200 nm). This enables light to penetrate the silicon and allows features on the bottom wafer to be observed. However, that is not always the case.  FIGS. 23A-C  shows a process flow for constructing 3D stacked chips and circuits when the thickness of the transferred/stacked piece of silicon is so high that light does not penetrate the transferred piece of silicon to observe the alignment marks on the bottom wafer. The process to allow for alignment to the bottom wafer may include several steps as described in the following sequence. 
     Step (A): A bottom wafer  2312  is processed to form a bottom transistor layer  2306  and a bottom wiring layer  2304 . A layer of silicon oxide  2302  is deposited above it.  FIG. 23A  illustrates the structure after Step (A). 
     Step (B): A wafer of p− Si  2310  has an oxide layer  2306  deposited or grown above it. Using lithography, a window pattern is etched into the p− Si  2310  and is filled with oxide. A step of CMP is done. This window pattern will be used in Step (C) to allow light to penetrate through the top layer of silicon to align to circuits on the bottom wafer  2312 . The window size is chosen based on misalignment tolerance of the alignment scheme used while bonding the top wafer to the bottom wafer in Step (C). Furthermore, some alignment marks also exist in the wafer of p− Si  2310 .  FIG. 23B  illustrates the structure after Step (B).
 
Step (C): A portion of the p− Si  2310  from Step (B) is transferred atop the bottom wafer  2312  using procedures similar to  FIGS. 2A-E . It can be observed that the window  2316  can be used for aligning features constructed on the top wafer  2314  to features on the bottom wafer  2312 . Thus, the thickness of the top wafer  2314  can be chosen without constraints.  FIG. 23C  illustrates the structure after Step (C).
 
     Additionally, when circuit cells are built on two or more layers of thin silicon, and enjoy the dense vertical through silicon via interconnections, the metallization layer scheme to take advantage of this dense 3D technology may be improved as follows.  FIG. 24A  illustrates the prior art of silicon integrated circuit metallization schemes. The conventional transistor silicon layer  2402  is connected to the first metal layer  2410  thru the contact  2404 . The dimensions of this interconnect pair of contact and metal lines generally are at the minimum line resolution of the lithography and etch capability for that technology process node. Traditionally, this is called a “1X” design rule metal layer. Usually, the next metal layer is also at the “1X” design rule, the metal line  2412  and via below  2405  and via above  2406  that connects metals  2412  with  2410  or with  2414  where desired. Then the next few layers are often constructed at twice the minimum lithographic and etch capability and called ‘2X’ metal layers, and have thicker metal for current carrying capability. These are illustrated with metal line  2414  paired with via  2407  and metal line  2416  paired with via  2408  in  FIG. 24A . Accordingly, the metal via pairs of  2418  with  2409 , and  2420  with bond pad opening  2422 , represent the ‘4X’ metallization layers where the planar and thickness dimensions are again larger and thicker than the 2X and 1X layers. The precise number of 1X or 2X or 4X layers may vary depending on interconnection needs and other requirements; however, the general flow is that of increasingly larger metal line, metal space, and via dimensions as the metal layers are farther from the silicon transistors and closer to the bond pads. 
     The metallization layer scheme may be improved for 3D circuits as illustrated in  FIG. 24B . The first crystallized silicon device layer  2454  is illustrated as the NMOS silicon transistor layer from the above 3D library cells, but may also be a conventional logic transistor silicon substrate or layer. The ‘1X’ metal layers  2450  and  2449  are connected with contact  2440  to the silicon transistors and vias  2438  and  2439  to each other or metal line  2448 . The 2X layer pairs metal  2448  with via  2437  and metal  2447  with via  2436 . The 4X metal layer  2446  is paired with via  2435  and metal  2445 , also at 4X. However, now via  2434  is constructed in 2X design rules to enable metal line  2444  to be at 2X. Metal line  2443  and via  2433  are also at 2X design rules and thicknesses. Vias  2432  and  2431  are paired with metal lines  2442  and  2441  at the 1X minimum design rule dimensions and thickness. The thru silicon via  2430  of the illustrated PMOS layer transferred silicon  2452  may then be constructed at the 1X minimum design rules and provide for maximum density of the top layer. The precise numbers of 1X or 2X or 4X layers may vary depending on circuit area and current carrying metallization requirements and tradeoffs. The layer transferred top transistor layer  2452  may be any of the low temperature devices illustrated herein. 
       FIGS. 43A-G  illustrate the formation of Junction Gate Field Effect Transistor (JFET) top transistors.  FIG. 43A  illustrates the structure after n− Si layer  4304  and n+ Si layer  4302  are transferred on top of a bottom layer of transistors and wires  4306 . This is done using procedures similar to those shown in  FIGS. 11A-F . Then the top transistor source  4308  and drain  4310  are defined by etching away the n+ from the region designated for gates  4312  and the isolation region between transistors  4314 . This step is aligned to the bottom layer of transistors and wires  4306  so the formed transistors could be properly connected to the underlying bottom layer of transistors and wires  4306 . Then an additional masking and etch step is performed to remove the n− layer between transistors, shown as  4316 , thus providing better transistor isolation as illustrated in  FIG. 43C .  FIG. 43D  illustrates an optional formation of shallow p+ region  4318  for the JFET gate formation. In this option there might be a need for laser or other optical energy transfer anneal to activate the p+.  FIG. 43E  illustrates how to utilize the laser anneal and minimize the heat transfer to the bottom layer of transistors and wires  4306 . After the thick oxide deposition  4320 , a layer of Aluminum  4322 , or other light reflecting material, is applied as a reflective layer. An opening  4324  in the reflective layer is masked and etched, allowing the laser light  4326  to heat the p+ implanted area  4330 , and reflecting the majority of the laser energy  4326  away from layer  4306 . Normally, the open area  4324  is less than 10% of the total wafer area. Additionally, a copper layer  4328 , or, alternatively, a reflective Aluminum layer or other reflective material, may be formed in the layer  4306  that will additionally reflect any of the laser energy  4326  that might travel to layer  4306 . This same reflective $ open laser anneal technique might be utilized on any of the other illustrated structures to enable implant activation for transistors in the second layer transfer process flow. In addition, absorptive materials may, alone or in combination with reflective materials, also be utilized in the above laser or other optical energy transfer anneal techniques. A photonic energy absorbing layer  4332 , such as amorphous carbon of an appropriate thickness, may be deposited or sputtered at low temperature over the area that needs to be laser heated, and then masked and etched as appropriate, as shown in  FIG. 43F . This allows the minimum laser energy to be employed to effectively heat the area to be implant activated, and thereby minimizes the heat stress on the reflective layers  4322  $  4328  and the base layer  4306 . The laser reflecting layer  4322  can then be etched or polished away and contacts can be made to various terminals of the transistor. This flow enables the formation of fully crystallized top JFET transistors that could be connected to the underlying multi-metal layer semiconductor device without exposing the underlying device to high temperature. 
     Section 2: Construction of 3D Stacked Semiconductor Circuits and Chips where Replacement Gate High-K/Metal Gate Transistors can be Used. Misalignment-Tolerance Techniques are Utilized to Get High Density of Connections. 
     Section 1 described the formation of 3D stacked semiconductor circuits and chips with sub-400° C. processing temperatures to build transistors and high density of vertical connections. In this section an alternative method is explained, in which a transistor is built with any replacement gate (or gate-last) scheme that is utilized widely in the industry. This method allows for high temperatures (above 400 C) to build the transistors. This method utilizes a combination of three concepts:
         Replacement gate (or gate-last) high k/metal gate fabrication   Face-up layer transfer using a carrier wafer   Misalignment tolerance techniques that utilize regular or repeating layouts. In these repeating layouts, transistors could be arranged in substantially parallel bands.
 
A very high density of vertical connections is possible with this method. Single crystal silicon (or monocrystalline silicon) layers that are transferred are less than 2 um thick, or could even be thinner than 0.4 um or 0.2 um.
       

     The method mentioned in the previous paragraph is described in  FIGS. 25A-F . The procedure may include several steps as described in the following sequence: 
     Step (A): After creating isolation regions using a shallow-trench-isolation (STI) process  2504 , dummy gates  2502  are constructed with silicon dioxide and poly silicon. The term “dummy gates” is used since these gates will be replaced by high k gate dielectrics and metal gates later in the process flow, according to the standard replacement gate (or gate-last) process. Further details of replacement gate processes are described in “A 45 nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193 nm Dry Patterning, and 100% Pb-free Packaging,” IEDM Tech. Dig., pp. 247-250, 2007 by K. Mistry, et al. and “Ultralow-EOT (5 Å) Gate-First and Gate-Last High Performance Achieved by Gate-Electrode Optimization,” IEDM Tech. Dig., pp. 663-666, 2009 by L. Ragnarsson, et al.  FIG. 25A  illustrates the structure after Step (A).
 
Step (B): Rest of the transistor fabrication flow proceeds with formation of source-drain regions  2506 , strain enhancement layers to improve mobility, high temperature anneal to activate source-drain regions  2506 , formation of inter-layer dielectric (ILD)  2508 , etc.  FIG. 25B  illustrates the structure after Step (B).
 
Step (C): Hydrogen is implanted into the wafer at the dotted line regions indicated by  2510 .  FIG. 25C  illustrates the structure after Step (C).
 
Step (D): The wafer after step (C) is bonded to a temporary carrier wafer  2512  using a temporary bonding adhesive  2514 . This temporary carrier wafer  2512  could be constructed of glass. Alternatively, it could be constructed of silicon. The temporary bonding adhesive  2514  could be a polymer material, such as a polyimide. A anneal or a sideways mechanical force is utilized to cleave the wafer at the hydrogen plane  2510 . A CMP process is then conducted.  FIG. 25D  illustrates the structure after Step (D).
 
Step (E): An oxide layer is deposited onto the bottom of the wafer shown in Step (D). The wafer is then bonded to the bottom layer of wires and transistors  2522  using oxide-to-oxide bonding. The bottom layer of wires and transistors  2522  could also be called a base wafer. The temporary carrier wafer  2512  is then removed by shining a laser onto the temporary bonding adhesive  2514  through the temporary carrier wafer  2512  (which could be constructed of glass). Alternatively, an anneal could be used to remove the temporary bonding adhesive  2514 . Through-silicon connections  2516  with a non-conducting (e.g. oxide) liner  2515  to the landing pads  2518  in the base wafer could be constructed at a very high density using special alignment methods to be described in  FIGS. 26A-D  and  FIGS. 27A-F .  FIG. 25E  illustrates the structure after Step (E).
 
Step (F): Dummy gates  2502  are etched away, followed by the construction of a replacement with high k gate dielectrics  2524  and metal gates  2526 . Essentially, partially-formed high performance transistors are layer transferred atop the base wafer (may also be called target wafer) followed by the completion of the transistor processing with a low (sub 400° C.) process.  FIG. 25F  illustrates the structure after Step (F). The remainder of the transistor, contact and wiring layers are then constructed.
 
It will be obvious to someone skilled in the art that alternative versions of this flow are possible with various methods to attach temporary carriers and with various versions of the gate-last process flow.
 
       FIGS. 26A-D  describes an alignment method for forming circuits with a high density of connections between 3D stacked layers. The alignment method may include moving the top layer masks left or right and up or down until all the through-layer contacts are on top of their corresponding landing pads. This is done in several steps in the following sequence: 
       FIG. 26A  illustrates the top wafer. A repeating pattern of circuits  2604  in the top wafer in both X and Y directions is used. Oxide isolation regions  2602  in between adjacent (identical) repeating structures are used. Each (identical) repeating structure has X dimension=W x  and Y dimension=W y , and this includes oxide isolation region thickness. The alignment mark in the top layer  2606  is located at (x top , y top ).
 
 FIG. 26B  illustrates the bottom wafer. The bottom wafer has a transistor layer and multiple layers of wiring. The top-most wiring layer has a landing pad structure, where repeating landing pads  2608  of X dimension W x + delta(W x ) and Y dimension W y + delta(W y ) are used. delta(W x ) and delta(W y ) are quantities that are added to compensate for alignment offsets, and are small compared to W x  and W y  respectively. Alignment mark for the bottom wafer  2610  is located at (x bottom , y bottom ). Note that the terms landing pad and metal strip are utilized interchangeably in this document.
 
After bonding the top and bottom wafers atop each other as described in  FIGS. 25A-F , the wafers look as shown in  FIG. 26C . Note that the circuit regions  2604  in between oxide isolation regions  2602  are not shown for easy illustration and understanding. It can be seen the top alignment mark  2606  and bottom alignment mark  2610  are misaligned to each other. As previously described in the description of  FIG. 14B , rotational or angular alignment between the top and bottom wafers is small and margin for this is provided by the offsets delta(W x ) and delta(W y ). Since the landing pad dimensions are larger than the length of the repeating pattern in both X and Y direction, the top layer-to-layer contact (and other masks) are shifted left or right and up or down until this contact is on top of the corresponding landing pad. This method is further described below:
 
Next step in the process is described with  FIG. 26D . A virtual alignment mark is created by the lithography tool. X co-ordinate of this virtual alignment mark is at the location (x top +(an integer k)*W x ). The integer k is chosen such that modulus or absolute value of (x top +(integer k)*W x −x bottom )&lt;=W x /2. This guarantees that the X co-ordinate of the virtual alignment mark is within a repeat distance of the X alignment mark of the bottom wafer. Y co-ordinate of this virtual alignment mark is at the location (y top +(an integer h)*W y ). The integer h is chosen such that modulus or absolute value of (y top +(integer h)*W y −y bottom )&lt;=W y /2. This guarantees that the Y co-ordinate of the virtual alignment mark is within a repeat distance of the Y alignment mark of the bottom wafer. Since silicon thickness of the top layer is thin, the lithography tool can observe the alignment mark of the bottom wafer. Though-silicon connections  2612  are now constructed with alignment mark of this mask aligned to the virtual alignment mark. Since the X and Y co-ordinates of the virtual alignment mark are within the same area of the layout (of dimensions W x  and W y ) as the bottom wafer X and Y alignment marks, the through-silicon connection  2612  always falls on the bottom landing pad  2608  (the bottom landing pad dimensions are W x  added to delta (W x ) and W y  added to delta (W y )).
 
       FIGS. 27A-F  show an alternative alignment method for forming circuits with a high density of connections between 3D stacked layers. The alignment method may include several steps in the following sequence: 
       FIG. 27A  describes the top wafer. A repeating pattern of circuits  2704  in the top wafer in both X and Y directions is used. Oxide isolation regions  2702  in between adjacent (identical) repeating structures are used. Each (identical) repeating structure has X dimension=W x  and Y dimension=W y , and this includes oxide isolation region thickness. The alignment mark in the top layer  2706  is located at (x top , y top ).
 
 FIG. 27B  describes the bottom wafer. The bottom wafer has a transistor layer and multiple layers of wiring. The top-most wiring layer has a landing pad structure, where repeating landing pads  2708  of X dimension W x + delta(W x ) and Y dimension F or  2 F are used. delta(W x ) is a quantity that is added to compensate for alignment offsets, and are smaller compared to W. Alignment mark for the bottom wafer  2710  is located at (x bottom , y bottom ).
 
After bonding the top and bottom wafers atop each other as described in  FIGS. 25A-F , the wafers look as shown in  FIG. 27C . Note that the circuit regions  2704  in between oxide isolation regions  2702  are not shown for easy illustration and understanding. It can be seen the top alignment mark  2706  and bottom alignment mark  2710  are misaligned to each other. As previously described in the description of  FIG. 14B , angular alignment between the top and bottom wafers is small and margin for this is provided by the offsets delta(W x ) and delta(W y ).
 
 FIG. 27D  illustrates the alignment method during/after the next step. A virtual alignment mark is created by the lithography tool. X co-ordinate of this virtual alignment mark is at the location (x top +(an integer k)*W x ). The integer k is chosen such that modulus or absolute value of (x top +(integer k)*W x −x bottom )&lt;=W x /2. This guarantees that the X co-ordinate of the virtual alignment mark is within a repeat distance of the X alignment mark of the bottom wafer. Y co-ordinate of this virtual alignment mark is at the location (y top +(an integer h)*W y ). The integer h is chosen such that modulus or absolute value of (y top +(integer h)*W y −y bottom )&lt;=W y /2. This guarantees that the Y co-ordinate of the virtual alignment mark is within a repeat distance of the Y alignment mark of the bottom wafer. Since silicon thickness of the top layer is thin, the lithography tool can observe the alignment mark of the bottom wafer. The virtual alignment mark is at the location (x virtual , y virtual ) where x virtual  and y virtual  are obtained as described earlier in this paragraph.
 
 FIG. 27E  illustrates the alignment method during/after the next step. Though-silicon connections  2712  are now constructed with alignment mark of this mask aligned to (x vutual , y bottom ). Since the X co-ordinate of the virtual alignment mark is within the same section of the layout in the X direction (of dimension W x ) as the bottom wafer X alignment mark, the through-silicon connection  2712  always falls on the bottom landing pad  2708  (the bottom landing pad dimension is W x  added to delta (W x )). The Y co-ordinate of the through silicon connections  2712  is aligned to y bottom , the Y co-ordinate of the bottom wafer alignment mark as described previously.
 
 FIG. 27F  shows a drawing illustration during/after the next step. A top landing pad  2716  is then constructed with X dimension F or  2 F and Y dimension W y + delta(W y ). This mask is formed with alignment mark aligned to (X bottom , y virtual ). Essentially, it can be seen that the top landing pad  2716  compensates for misalignment in the Y direction, while the bottom landing pad  2708  compensates for misalignment in the X direction.
 
The alignment scheme shown in  FIGS. 27A-F  can give a higher density of connections between two layers than the alignment scheme shown in  FIGS. 26A-D . The connection paths between two transistors located on two layers therefore may include: a first landing pad or metal strip substantially parallel to a certain axis, a through via and a second landing pad or metal strip substantially perpendicular to a certain axis. Features are formed using virtual alignment marks whose positions depend on misalignment during bonding. Also, through-silicon connections in  FIGS. 26A-D  have relatively high capacitance due to the size of the landing pads. It will be apparent to one skilled in the art that variations of this process flow are possible (e.g., different versions of regular layouts could be used along with replacement gate processes to get a high density of connections between 3D stacked circuits and chips).
 
       FIGS. 44A-D  and  FIGS. 45A-D  show an alternative procedure for forming circuits with a high density of connections between stacked layers. The process utilizes a repeating pattern in one direction for the top layer of transistors. The procedure may include several steps in the following sequence: 
     Step (A): Using procedures similar to  FIGS. 25A-F , a top layer of transistors  4404  is transferred atop a bottom layer of transistors and wires  4402 . Landing pads  4406  are utilized on the bottom layer of transistors and wires  4402 . Dummy gates  4408  and  4410  are utilized for nMOS and pMOS. The key difference between the structures shown in  FIGS. 25A-F  and this structure is the layout of oxide isolation regions between transistors.  FIG. 44A  illustrates the structure after Step (A).
 
Step (B): Through-silicon connections  4412  are formed well-aligned to the bottom layer of transistors and wires  4402 . Alignment schemes to be described in  FIGS. 45A-F  are utilized for this purpose. All features constructed in future steps are also formed well-aligned to the bottom layer of transistors and wires  4402 .  FIG. 44B  illustrates the structure after Step (B).
 
Step (C): Oxide isolation regions  4414  are formed between adjacent transistors to be defined. These isolation regions are formed by lithography and etch of gate and silicon regions and then fill with oxide.  FIG. 44C  illustrates the structure after Step (C).
 
Step (D): The dummy gates  4408  and  4410  are etched away and replaced with replacement gates  4416  and  4418 . These replacement gates are patterned and defined to form gate contacts as well.  FIG. 44D  illustrates the structure after Step (D). Following this, other process steps in the fabrication flow proceed as usual.
 
       FIGS. 45A-D  describe alignment schemes for the structures shown in  FIGS. 44A-D .  FIG. 45A  describes the top wafer. A repeating pattern of features in the top wafer in Y direction is used. Each (identical) repeating structure has Y dimension=W y , and this includes oxide isolation region thickness. The alignment mark in the top layer  4502  is located at (x top , y top ).  FIG. 45B  describes the bottom wafer. The bottom wafer has a transistor layer and multiple layers of wiring. The top-most wiring layer has a landing pad structure, where repeating landing pads  4506  of X dimension F or  2 F and Y dimension W y + delta(W y ) are used. delta(W y ) is a quantity that is added to compensate for alignment offsets, and is smaller compared to W y . Alignment mark for the bottom wafer  4504  is located at (x bottom , y bottom ). 
     After bonding the top and bottom wafers atop each other as described in  FIGS. 44A-D , the wafers look as shown in  FIG. 45C . It can be seen the top alignment mark  4502  and bottom alignment mark  4504  are misaligned to each other. As previously described in the description of  FIG. 14B , angle alignment between the top and bottom wafers is small or negligible.
 
 FIG. 45D  illustrates the next step of the alignment procedure. A virtual alignment mark is created by the lithography tool. X co-ordinate of this virtual alignment mark is at the location (x bottom ). Y co-ordinate of this virtual alignment mark is at the location (y top +(an integer h)*W y ). The integer h is chosen such that modulus or absolute value of (y top +(integer h)*W y −y bottom )&lt;=W y /2. This guarantees that the Y co-ordinate of the virtual alignment mark is within a repeat distance of the Y alignment mark of the bottom wafer. Since silicon thickness of the top layer is thin, the lithography tool can observe the alignment mark of the bottom wafer. The virtual alignment mark is at the location (x virtual , y virtual ) where x virtual  and y virtual  are obtained as described earlier in this paragraph.
 
 FIG. 45E  illustrates the next step of the alignment procedure. Though-silicon connections  4508  are now constructed with alignment mark of this mask aligned to (X virtual , y virtual ). Since the X co-ordinate of the virtual alignment mark is perfectly aligned to the X co-ordinate of the bottom wafer alignment mark and since the Y co-ordinate of the virtual alignment mark is within the same section of the layout (of distance W y ) as the bottom wafer Y alignment mark, the through-silicon connection  4508  always falls on the bottom landing pad (the bottom landing pad dimension in the Y direction is W y  added to delta (W y )).
 
       FIGS. 46A-G  illustrate using a carrier wafer for layer transfer.  FIG. 46A  illustrates the first step of preparing transistors with dummy gates  4602  on first donor wafer (or top wafer)  4606 . This completes the first phase of transistor formation.  FIG. 46B  illustrates forming a cleave line  4608  by implant  4616  of atomic particles such as H+.  FIG. 46C  illustrates permanently bonding the first donor wafer  4606  to a second donor wafer  4626 . The permanent bonding may be oxide to oxide wafer bonding as described previously.  FIG. 46D  illustrates the second donor wafer  4626  acting as a carrier wafer after cleaving the first donor wafer off; leaving a thin layer  4606  with the now buried dummy gate transistors  4602 .  FIG. 46E  illustrates forming a second cleave line  4618  in the second donor wafer  4626  by implant  4646  of atomic species such as H+.  FIG. 46F  illustrates the second layer transfer step to bring the dummy gate transistors  4602  ready to be permanently bonded on top of the bottom layer of transistors and wires  4601 . For the simplicity of the explanation we left out the now obvious steps of surface layer preparation done for each of these bonding steps.  FIG. 46G  illustrates the bottom layer of transistors and wires  4601  with the dummy gate transistor  4602  on top after cleaving off the second donor wafer and removing the layers on top of the dummy gate transistors. Now we can proceed and replace the dummy gates with the final gates, form the metal interconnection layers, and continue the 3D fabrication process. 
     An interesting alternative is available when using the carrier wafer flow described in  FIGS. 46A-G . In this flow we can use the two sides of the transferred layer to build NMOS on one side and PMOS on the other side. Timing properly the replacement gate step such flow could enable full performance transistors properly aligned to each other. As illustrated in  FIG. 47A , an SOI (Silicon On Insulator) donor (or top) wafer  4700  may be processed in the normal state of the art high k metal gate gate-last manner with adjusted thermal cycles to compensate for later thermal processing up to the step prior to where CMP exposure of the polysilicon dummy gates  4704  takes place.  FIG. 47A  illustrates a cross section of the SOI donor wafer substrate  4700 , the buried oxide (BOX)  4701 , the thin silicon layer  4702  of the SOI wafer, the isolation  4703  between transistors, the polysilicon  4704  and gate oxide  4705  of n-type transistors with dummy gates, their associated source and drains  4706  for NMOS, and the NMOS interlayer dielectric (ILD)  4708 . Alternatively, the PMOS device may be constructed at this stage. This completes the first phase of transistor formation. At this step, or alternatively just after a CMP of layer  4708  to expose the polysilicon dummy gates  4704  or to planarize the oxide layer  4708  and not expose the dummy gates  4704 , an implant of an atomic species  4710 , such as H+, is done to prepare the cleaving plane  4712  in the bulk of the donor substrate, as illustrated in  FIG. 47B . The SOI donor wafer  4700  is now permanently bonded to a carrier wafer  4720  that has been prepared with an oxide layer  4716  for oxide to oxide bonding to the donor wafer surface  4714  as illustrated in  FIG. 47C . The details have been described previously. The donor wafer  4700  may then be cleaved at the cleaving plane  4712  and may be thinned by chemical mechanical polishing (CMP) and surface  4722  may be prepared for transistor formation. The donor wafer layer  4700  at surface  4722  may be processed in the normal state of the art gate last processing to form the PMOS transistors with dummy gates. During processing the wafer is flipped so that surface  4722  is on top, but for illustrative purposes this is not shown in the subsequent  FIGS. 47E-G .  FIG. 47E  illustrates the cross section with the buried oxide (BOX)  4701 , the now thin silicon layer  4700  of the SOI substrate, the isolation  4733  between transistors, the polysilicon  4734  and gate oxide  4735  of p-type dummy gates, their associated source and drains  4736  for PMOS, and the PMOS interlayer dielectric (ILD)  4738 . The PMOS transistors may be precisely aligned at state of the art tolerances to the NMOS transistors due to the shared substrate  4700  possessing the same alignment marks. At this step, or alternatively just after a CMP of layer  4738  to expose the PMOS polysilicon dummy gates or to planarize the oxide layer  4738  and not expose the dummy gates, the wafer could be put into high temperature cycle to activate both the dopants in the NMOS and the PMOS source drain regions. Then an implant of an atomic species  4740 , such as H+, may prepare the cleaving plane  4721  in the bulk of the carrier wafer substrate  4720  for layer transfer suitability, as illustrated in  FIG. 47F . The PMOS transistors are now ready for normal state of the art gate-last transistor formation completion. As illustrated in  FIG. 47G , the inter layer dielectric  4738  may be chemical mechanically polished to expose the top of the polysilicon dummy gates  4734 . The dummy polysilicon gates  4734  may then be removed by etch and the PMOS hi-k gate dielectric  4740  and the PMOS specific work function metal gate  4741  may be deposited. An aluminum fill  4742  may be performed on the PMOS gates and the metal CMP&#39;ed. A dielectric layer  4739  may be deposited and the normal gate  4743  and source/drain  4744  contact formation and metallization. The PMOS layer to NMOS layer via  4747  and metallization may be partially formed as illustrated in  FIG. 47G  and an oxide layer  4748  is deposited to prepare for bonding. The carrier wafer and two sided n/p layer is then permanently bonded to bottom wafer having transistors and wires  4799  with associated metal landing strip  4750  as illustrated in  FIG. 47H . The carrier wafer  4720  may then be cleaved at the cleaving plane  4721  and may be thinned by chemical mechanical polishing (CMP) to oxide layer  4716  as illustrated in  FIG. 47I . The NMOS transistors are now ready for normal state of the art gate-last transistor formation completion. As illustrated in  FIG. 47J , the oxide layer  4716  and the NMOS inter layer dielectric  4708  may be chemical mechanically polished to expose the top of the NMOS polysilicon dummy gates  4704 . The dummy polysilicon gates  4704  may then be removed by etch and the NMOS hi-k gate dielectric  4760  and the NMOS specific work function metal gate  4761  may be deposited. An aluminum fill  4762  may be performed on the NMOS gates and the metal CMP&#39;ed. A dielectric layer  4769  may be deposited and the normal gate  4763  and source/drain  4764  contact formation and metallization. The NMOS layer to PMOS layer via  4767  to connect to  4747  and metallization may be formed. As illustrated in  FIG. 47K , the layer-to-layer contacts  4772  to the landing pads in the base wafer are now made. This same contact etch could be used to make the connections  4773  between the NMOS and PMOS layer as well, instead of using the two step ( 4747  and  4767 ) method in  FIG. 47H . 
     Another alternative is illustrated in  FIG. 48  whereby the implant of an atomic species  4810 , such as H+, may be screened from the sensitive gate areas  4803  by first masking and etching a shield implant stopping layer of a dense material  4850 , for example 5000 angstroms of Tantalum, and may be combined with 5,000 angstroms of photoresist  4852 . This may create a segmented cleave plane  4812  in the bulk of the donor wafer silicon wafer and may require additional polishing to provide a smooth bonding surface for layer transfer suitability, 
     Using procedures similar to  FIGS. 47A-K , it is possible to construct structures such as  FIG. 49  where a transistor is constructed with front gate  4902  and back gate  4904 . The back gate could be utilized for many purposes such as threshold voltage control, reduction of variability, increase of drive current and other purposes. 
     Section 3: Monolithic 3D DRAM. 
     While Section 1 and Section 2 describe applications of monolithic 3D integration to logic circuits and chips, this Section describes novel monolithic 3D Dynamic Random Access Memories (DRAMs). Some embodiments of this invention may involve floating body DRAM. Background information on floating body DRAM and its operation is given in “Floating Body RAM Technology and its Scalability to 32 nm Node and Beyond,”  Electron Devices Meeting,  2006 . IEDM &#39; 06 . International , vol., no., pp. 1-4, 11-13 Dec. 2006 by T. Shino, N. Kusunoki, T. Higashi, et al., Overview and future challenges of floating body RAM (FBRAM) technology for 32 nm technology node and beyond, Solid-State Electronics, Volume 53, Issue 7, Papers Selected from the 38th European Solid-State Device Research Conference—ESSDERC&#39;08, July 2009, Pages 676-683, ISSN 0038-1101, DOI: 10.1016/j.sse.2009.03.010 by Takeshi Hamamoto, Takashi Ohsawa, et al., “New Generation of Z-RAM,”  Electron Devices Meeting,  2007 . IEDM  2007 . IEEE International , vol., no., pp. 925-928, 10-12 Dec. 2007 by Okhonin, S.; Nagoga, M.; Carman, E, et al. The above publications are incorporated herein by reference. 
       FIG. 28  describes fundamental operation of a prior art floating body DRAM. For storing a ‘1’ bit, holes  2802  are present in the floating body  2820  and change the threshold voltage of the cell, as shown in  FIG. 28(   a ). The ‘0’ bit corresponds to no charge being stored in the floating body, as shown in  FIG. 28(   b ). The difference in threshold voltage between  FIG. 28(   a ) and  FIG. 28(   b ) may give rise to a change in drain current of the transistor at a particular gate voltage, as described in  FIG. 28(   c ). This current differential can be sensed by a sense amplifier to differentiate between ‘0’ and ‘1’ states. 
       FIGS. 29A-H  describe a process flow to construct a horizontally-oriented monolithic 3D DRAM. Two masks are utilized on a “per-memory-layer” basis for the monolithic 3D DRAM concept shown in  FIGS. 29A-H , while other masks are shared between all constructed memory layers. The process flow may include several steps in the following sequence. 
     Step (A): A p− Silicon wafer  2901  is taken and an oxide layer  2902  is grown or deposited above it.  FIG. 29A  illustrates the structure after Step (A). 
     Step (B): Hydrogen is implanted into the p− wafer  2901  at a certain depth denoted by 2903.  FIG. 29B  illustrates the structure after Step (B). 
     Step (C): The wafer after Step (B) is flipped and bonded onto a wafer having peripheral circuits  2904  covered with oxide. This bonding process occurs using oxide-to-oxide bonding. The stack is then cleaved at the hydrogen implant plane  2903  using either an anneal or a sideways mechanical force. A chemical mechanical polish (CMP) process is then conducted. Note that peripheral circuits  2904  are such that they can withstand an additional rapid-thermal-anneal (RTA) and still remain operational, and preferably retain good performance. For this purpose, the peripheral circuits  2904  may be such that they have not had their RTA for activating dopants or they have had a weak RTA for activating dopants. Also, peripheral circuits  2904  utilize a refractory metal such as tungsten that can withstand high temperatures greater than 400° C.  FIG. 29C  illustrates the structure after Step (C).
 
Step (D): The transferred layer of p− silicon after Step (C) is then processed to form isolation regions using a STI process. Following, gate regions  2905  are deposited and patterned, following which source-drain regions  2908  are implanted using a self-aligned process. An inter-level dielectric (ILD) constructed of oxide (silicon dioxide)  2906  is then constructed. Note that no RTA is done to activate dopants in this layer of partially-depleted SOI (PD-SOI) transistors. Alternatively, transistors could be of fully-depleted SOI type.  FIG. 29D  illustrates the structure after Step (D).
 
Step (E): Using steps similar to Step (A)-Step (D), another layer of memory  2909  is constructed. After all the desired memory layers are constructed, a RTA is conducted to activate dopants in all layers of memory (and potentially also the periphery).  FIG. 29E  illustrates the structure after Step (E).
 
Step (F): Contact plugs  2910  are made to source and drain regions of different layers of memory. Bit-line (BL) wiring  2911  and Source-line (SL) wiring  2912  are connected to contact plugs  2910 . Gate regions  2913  of memory layers are connected together to form word-line (WL) wiring.  FIG. 29F  illustrates the structure after Step (F).
 
 FIG. 29G  and  FIG. 29H  describe array organization of the floating-body DRAM. BLs  2916  in a direction substantially perpendicular to the directions of SLs  2915  and WLs  2914 .
 
       FIGS. 30A-M  describe an alternative process flow to construct a horizontally-oriented monolithic 3D DRAM. This monolithic 3D DRAM utilizes the floating body effect and double-gate transistors. One mask is utilized on a “per-memory-layer” basis for the monolithic 3D DRAM concept shown in  FIGS. 30A-M , while other masks are shared between different layers. The process flow may include several steps that occur in the following sequence. 
     Step (A): Peripheral circuits with tungsten wiring  3002  are first constructed and above this a layer of silicon dioxide  3004  is deposited.  FIG. 30A  illustrates the structure after Step (A). 
     Step (B):  FIG. 30B  shows a drawing illustration after Step (B). A wafer of p− Silicon  3006  has an oxide layer  3008  grown or deposited above it. Following this, hydrogen is implanted into the p-Silicon wafer at a certain depth indicated by  3010 . Alternatively, some other atomic species such as Helium could be (co-)implanted. This hydrogen implanted p− Silicon wafer  3006  forms the top layer  3012 . The bottom layer  3014  may include the peripheral circuits  3002  with oxide layer  3004 . The top layer  3012  is flipped and bonded to the bottom layer  3014  using oxide-to-oxide bonding.
 
Step (C):  FIG. 30C  illustrates the structure after Step (C). The stack of top and bottom wafers after Step (B) is cleaved at the hydrogen plane  3010  using either a anneal or a sideways mechanical force or other means. A CMP process is then conducted. At the end of this step, a single-crystal p− Si layer exists atop the peripheral circuits, and this has been achieved using layer-transfer techniques.
 
Step (D):  FIG. 30D  illustrates the structure after Step (D). Using lithography and then implantation, n+ regions  3016  and p− regions  3018  are formed on the transferred layer of p− Si after Step (C).
 
Step (E):  FIG. 30E  illustrates the structure after Step (E). An oxide layer  3020  is deposited atop the structure obtained after Step (D). A first layer of Si/SiO 2    3022  is therefore formed atop the peripheral circuit layer  3002 .
 
Step (F):  FIG. 30F  illustrates the structure after Step (F). Using procedures similar to Steps (B)-(E), additional Si/SiO 2  layers  3024  and  3026  are formed atop Si/SiO 2  layer  3022 . A rapid thermal anneal (RTA) or spike anneal or flash anneal or laser anneal is then done to activate all implanted layers  3022 ,  3024  and  3026  (and possibly also the peripheral circuit layer  3002 ). Alternatively, the layers  3022 ,  3024  and  3026  are annealed layer-by-layer as soon as their implantations are done using a laser anneal system.
 
Step (G):  FIG. 30G  illustrates the structure after Step (G). Lithography and etch processes are then utilized to make a structure as shown in the figure.
 
Step (H):  FIG. 30H  illustrates the structure after Step (H). Gate dielectric  3028  and gate electrode  3030  are then deposited following which a CMP is done to planarize the gate electrode  3030  regions. Lithography and etch are utilized to define gate regions over the p− silicon regions (eg. p− Si region after Step (D)). Note that gate width could be slightly larger than p− region width to compensate for overlay errors in lithography.
 
Step (I):  FIG. 30I  illustrates the structure after Step (I). A silicon oxide layer  3032  is then deposited and planarized. For clarity, the silicon oxide layer is shown transparent in the figure, along with word-line (WL) and source-line (SL) regions.
 
Step (J):  FIG. 30J  illustrates the structure after Step (J). Bit-line (BL) contacts  3034  are formed by etching and deposition. These BL contacts are shared among all layers of memory.
 
Step (K):  FIG. 30K  illustrates the structure after Step (K). BLs  3036  are then constructed. Contacts are made to BLs, WLs and SLs of the memory array at its edges. SL contacts can be made into stair-like structures using techniques described in “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,”  VLSI Technology,  2007  IEEE Symposium on , vol., no., pp. 14-15, 12-14 Jun. 2007 by Tanaka, H.; Kido, M.; Yahashi, K.; Oomura, M.; et al., following which contacts can be constructed to them. Formation of stair-like structures for SLs could be done in steps prior to Step (K) as well.
 
 FIG. 30L  shows cross-sectional views of the array for clarity. The double-gated transistors in  FIG. 30L  can be utilized along with the floating body effect for storing information.
 
 FIG. 30M  shows a memory cell of the floating body RAM array with two gates on either side of the p− Si layer  3019 .
 
A floating-body DRAM has thus been constructed, with (1) horizontally-oriented transistors—i.e., current flowing in substantially the horizontal direction in transistor channels, (2) some of the memory cell control lines, e.g., source-lines SL, constructed of heavily doped silicon and embedded in the memory cell layer, (3) side gates simultaneously deposited over multiple memory layers, and (4) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut.
 
       FIGS. 31A-K  describe an alternative process flow to construct a horizontally-oriented monolithic 3D DRAM. This monolithic 3D DRAM utilizes the floating body effect and double-gate transistors. No mask is utilized on a “per-memory-layer” basis for the monolithic 3D DRAM concept shown in  FIGS. 31A-K , and all other masks are shared between different layers. The process flow may include several steps in the following sequence. 
     Step (A): Peripheral circuits with tungsten wiring  3102  are first constructed and above this a layer of silicon dioxide  3104  is deposited.  FIG. 31A  shows a drawing illustration after Step (A). 
     Step (B):  FIG. 31B  illustrates the structure after Step (B). A wafer of p− Silicon  3108  has an oxide layer  3106  grown or deposited above it. Following this, hydrogen is implanted into the p− Silicon wafer at a certain depth indicated by  3114 . Alternatively, some other atomic species such as Helium could be (co-)implanted. This hydrogen implanted p− Silicon wafer  3108  forms the top layer  3110 . The bottom layer  3112  may include the peripheral circuits  3102  with oxide layer  3104 . The top layer  3110  is flipped and bonded to the bottom layer  3112  using oxide-to-oxide bonding.
 
Step (C):  FIG. 31C  illustrates the structure after Step (C). The stack of top and bottom wafers after Step (B) is cleaved at the hydrogen plane  3014  using either a anneal or a sideways mechanical force or other means. A CMP process is then conducted. A layer of silicon oxide  3118  is then deposited atop the p− Silicon layer  3116 . At the end of this step, a single-crystal p− Si layer  3116  exists atop the peripheral circuits, and this has been achieved using layer-transfer techniques.
 
Step (D):  FIG. 31D  illustrates the structure after Step (D). Using methods similar to Step (B) and (C), multiple p− silicon layers  3120  are formed with silicon oxide layers in between.
 
Step (E):  FIG. 31E  illustrates the structure after Step (E). Lithography and etch processes are then utilized to make a structure as shown in the figure.
 
Step (F):  FIG. 31F  illustrates the structure after Step (F). Gate dielectric  3126  and gate electrode  3124  are then deposited following which a CMP is done to planarize the gate electrode  3124  regions. Lithography and etch are utilized to define gate regions.
 
Step (G):  FIG. 31G  illustrates the structure after Step (G). Using the hard mask defined in Step (F), p− regions not covered by the gate are implanted to form n+ regions. Spacers are utilized during this multi-step implantation process and layers of silicon present in different layers of the stack have different spacer widths to account for lateral straggle of buried layer implants. Bottom layers could have larger spacer widths than top layers. A thermal annealing step, such as a RTA or spike anneal or laser anneal or flash anneal, is then conducted to activate n+ doped regions.
 
Step (H):  FIG. 31H  illustrates the structure after Step (H). A silicon oxide layer  3130  is then deposited and planarized. For clarity, the silicon oxide layer is shown transparent, along with word-line (WL)  3132  and source-line (SL)  3134  regions.
 
Step (I):  FIG. 31I  illustrates the structure after Step (I). Bit-line (BL) contacts  3136  are formed by etching and deposition. These BL contacts are shared among all layers of memory.
 
Step (J):  FIG. 31J  illustrates the structure after Step (J). BLs  3138  are then constructed. Contacts are made to BLs, WLs and SLs of the memory array at its edges. SL contacts can be made into stair-like structures using techniques described in “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,”  VLSI Technology,  2007  IEEE Symposium on , vol., no., pp. 14-15, 12-14 Jun. 2007 by Tanaka, H.; Kido, M.; Yahashi, K.; Oomura, M.; et al., following which contacts can be constructed to them. Formation of stair-like structures for SLs could be done in steps prior to Step (J) as well.
 
 FIG. 31K  shows cross-sectional views of the array for clarity. Double-gated transistors may be utilized along with the floating body effect for storing information. A floating-body DRAM has thus been constructed, with (1) horizontally-oriented transistors—i.e. current flowing in substantially the horizontal direction in transistor channels (2) some of the memory cell control lines, e.g., source-lines SL, constructed of heavily doped silicon and embedded in the memory cell layer, (3) side gates simultaneously deposited over multiple memory layers, and (4) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut.
 
     With the explanations for the formation of monolithic 3D DRAM with ion-cut in this section, it is clear to one skilled in the art that alternative implementations are possible. BL and SL nomenclature has been used for two terminals of the 3D DRAM array, and this nomenclature can be interchanged. Each gate of the double gate 3D DRAM can be independently controlled for better control of the memory cell. To implement these changes, the process steps in  FIGS. 30A-M  and  31  may be modified. Moreover, selective epi technology or laser recrystallization technology could be utilized for implementing structures shown in  FIGS. 30A-M  and  FIGS. 31A-K . Various other types of layer transfer schemes that have been described in Section 1.3.4 can be utilized for construction of various 3D DRAM structures. Furthermore, buried wiring, i.e. where wiring for memory arrays is below the memory layers but above the periphery, may also be used. In addition, other variations of the monolithic 3D DRAM concepts are possible. 
     Section 4: Monolithic 3D Resistance-based Memory 
     While many of today&#39;s memory technologies rely on charge storage, several companies are developing non-volatile memory technologies based on resistance of a material changing. Examples of these resistance-based memories include phase change memory, Metal Oxide memory, resistive RAM (RRAM), memristors, solid-electrolyte memory, ferroelectric RAM, MRAM, etc. Background information on these resistive-memory types is given in “Overview of candidate device technologies for storage-class memory,”  IBM Journal of Research and Development , vol. 52, no. 4.5, pp. 449-464, July 2008 by Burr, G. W.; Kurdi, B. N.; Scott, J. C.; Lam, C. H.; Gopalakrishnan, K.; Shenoy, R. S. 
       FIGS. 32A-J  describe a novel memory architecture for resistance-based memories, and a procedure for its construction. The memory archtecture utilizes junction-less transistors and has a resistance-based memory element in series with a transistor selector. No mask is utilized on a “per-memory-layer” basis for the monolithic 3D resistance change memory (or resistive memory) concept shown in  FIGS. 32A-J , and all other masks are shared between different layers. The process flow may include several steps that occur in the following sequence. 
     Step (A): Peripheral circuits  3202  are first constructed and above this a layer of silicon dioxide  3204  is deposited.  FIG. 32A  shows a drawing illustration after Step (A). 
     Step (B):  FIG. 32B  illustrates the structure after Step (B). A wafer of n+ Silicon  3208  has an oxide layer  3206  grown or deposited above it. Following this, hydrogen is implanted into the n+ Silicon wafer at a certain depth indicated by  3214 . Alternatively, some other atomic species such as Helium could be (co-)implanted. This hydrogen implanted n+ Silicon wafer  3208  forms the top layer  3210 . The bottom layer  3212  may include the peripheral circuits  3202  with oxide layer  3204 . The top layer  3210  is flipped and bonded to the bottom layer  3212  using oxide-to-oxide bonding.
 
Step (C):  FIG. 32C  illustrates the structure after Step (C). The stack of top and bottom wafers after Step (B) is cleaved at the hydrogen plane  3214  using either a anneal or a sideways mechanical force or other means. A CMP process is then conducted. A layer of silicon oxide  3218  is then deposited atop the n+ Silicon layer  3216 . At the end of this step, a single-crystal n+ Si layer  3216  exists atop the peripheral circuits, and this has been achieved using layer-transfer techniques.
 
Step (D):  FIG. 32D  illustrates the structure after Step (D). Using methods similar to Step (B) and (C), multiple n+ silicon layers  3220  are formed with silicon oxide layers in between.
 
Step (E):  FIG. 32E  illustrates the structure after Step (E). Lithography and etch processes are then utilized to make a structure as shown in the figure.
 
Step (F):  FIG. 32F  illustrates the structure after Step (F). Gate dielectric  3226  and gate electrode  3224  are then deposited following which a CMP is performed to planarize the gate electrode  3224  regions. Lithography and etch are utilized to define gate regions.
 
Step (G):  FIG. 32G  illustrates the structure after Step (G). A silicon oxide layer  3230  is then deposited and planarized. The silicon oxide layer is shown transparent in the figure for clarity, along with word-line (WL)  3232  and source-line (SL)  3234  regions.
 
Step (H):  FIG. 32H  illustrates the structure after Step (H). Vias are etched through multiple layers of silicon and silicon dioxide as shown in the figure. A resistance change memory material  3236  is then deposited (preferably with atomic layer deposition (ALD)). Examples of such a material include hafnium oxide, well known to change resistance by applying voltage. An electrode for the resistance change memory element is then deposited (preferably using ALD) and is shown as electrode/BL contact  3240 . A CMP process is then conducted to planarize the surface. It can be observed that multiple resistance change memory elements in series with junctionless transistors are created after this step.
 
Step (I):  FIG. 32I  illustrates the structure after Step (I). BLs  3238  are then constructed. Contacts are made to BLs, WLs and SLs of the memory array at its edges. SL contacts can be made into stair-like structures using techniques described in “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,”  VLSI Technology,  2007  IEEE Symposium on , vol., no., pp. 14-15, 12-14 Jun. 2007 by Tanaka, H.; Kido, M.; Yahashi, K.; Oomura, M.; et al., following which contacts can be constructed to them. Formation of stair-like structures for SLs could be achieved in steps prior to Step (I) as well.
 
 FIG. 32J  shows cross-sectional views of the array for clarity.
 
A 3D resistance change memory has thus been constructed, with (1) horizontally-oriented transistors—i.e. current flowing in substantially the horizontal direction in transistor channels, (2) some of the memory cell control lines, e.g., source-lines SL, constructed of heavily doped silicon and embedded in the memory cell layer, (3) side gates that are simultaneously deposited over multiple memory layers for transistors, and (4) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut.
 
       FIGS. 33A-K  describe an alternative process flow to construct a horizontally-oriented monolithic 3D resistive memory array. This embodiment has a resistance-based memory element in series with a transistor selector. No mask is utilized on a “per-memory-layer” basis for the monolithic 3D resistance change memory (or resistive memory) concept shown in  FIGS. 33A-K , and all other masks are shared between different layers. The process flow may include several steps as described in the following sequence. 
     Step (A): Peripheral circuits with tungsten wiring  3302  are first constructed and above this a layer of silicon dioxide  3304  is deposited.  FIG. 33A  shows a drawing illustration after Step (A). 
     Step (B):  FIG. 33B  illustrates the structure after Step (B). A wafer of p− Silicon  3308  has an oxide layer  3306  grown or deposited above it. Following this, hydrogen is implanted into the p− Silicon wafer at a certain depth indicated by  3314 . Alternatively, some other atomic species such as Helium could be (co-)implanted. This hydrogen implanted p− Silicon wafer  3308  forms the top layer  3310 . The bottom layer  3312  may include the peripheral circuits  3302  with oxide layer  3304 . The top layer  3310  is flipped and bonded to the bottom layer  3312  using oxide-to-oxide bonding.
 
Step (C):  FIG. 33C  illustrates the structure after Step (C). The stack of top and bottom wafers after Step (B) is cleaved at the hydrogen plane  3314  using either a anneal or a sideways mechanical force or other means. A CMP process is then conducted. A layer of silicon oxide  3318  is then deposited atop the p− Silicon layer  3316 . At the end of this step, a single-crystal p− Si layer  3316  exists atop the peripheral circuits, and this has been achieved using layer-transfer techniques.
 
Step (D):  FIG. 33D  illustrates the structure after Step (D). Using methods similar to Step (B) and (C), multiple p− silicon layers  3320  are formed with silicon oxide layers in between.
 
Step (E):  FIG. 33E  illustrates the structure after Step (E). Lithography and etch processes are then utilized to make a structure as shown in the figure.
 
Step (F):  FIG. 33F  illustrates the structure on after Step (F). Gate dielectric  3326  and gate electrode  3324  are then deposited following which a CMP is done to planarize the gate electrode  3324  regions. Lithography and etch are utilized to define gate regions.
 
Step (G):  FIG. 33G  illustrates the structure after Step (G). Using the hard mask defined in Step (F), p− regions not covered by the gate are implanted to form n+ regions. Spacers are utilized during this multi-step implantation process and layers of silicon present in different layers of the stack have different spacer widths to account for lateral straggle of buried layer implants. Bottom layers could have larger spacer widths than top layers. A thermal annealing step, such as a RTA or spike anneal or laser anneal or flash anneal, is then conducted to activate n+ doped regions.
 
Step (H):  FIG. 33H  illustrates the structure after Step (H). A silicon oxide layer  3330  is then deposited and planarized. The silicon oxide layer is shown transparent in the figure for clarity, along with word-line (WL)  3332  and source-line (SL)  3334  regions.
 
Step (I):  FIG. 33I  illustrates the structure after Step (I). Vias are etched through multiple layers of silicon and silicon dioxide as shown in the figure. A resistance change memory material  3336  is then deposited (preferably with atomic layer deposition (ALD)). Examples of such a material include hafnium oxide, which is well known to change resistance by applying voltage. An electrode for the resistance change memory element is then deposited (preferably using ALD) and is shown as electrode/BL contact  3340 . A CMP process is then conducted to planarize the surface. It can be observed that multiple resistance change memory elements in series with transistors are created after this step.
 
Step (J):  FIG. 33J  illustrates the structure after Step (J). BLs  3338  are then constructed. Contacts are made to BLs, WLs and SLs of the memory array at its edges. SL contacts can be made into stair-like structures using techniques described in “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,”  VLSI Technology,  2007  IEEE Symposium on , vol., no., pp. 14-15, 12-14 Jun. 2007 by Tanaka, H.; Kido, M.; Yahashi, K.; Oomura, M.; et al., following which contacts can be constructed to them. Formation of stair-like structures for SLs could be done in steps prior to Step (I) as well.
 
 FIG. 33K  shows cross-sectional views of the array for clarity.
 
A 3D resistance change memory has thus been constructed, with (1) horizontally-oriented transistors—i.e. current flowing in substantially the horizontal direction in transistor channels, (2) some of the memory cell control lines—e.g., source-lines SL, constructed of heavily doped silicon and embedded in the memory cell layer, (3) side gates simultaneously deposited over multiple memory layers for transistors, and (4) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut.
 
       FIGS. 34A-L  describes an alternative process flow to construct a horizontally-oriented monolithic 3D resistive memory array. This embodiment has a resistance-based memory element in series with a transistor selector. One mask is utilized on a “per-memory-layer” basis for the monolithic 3D resistance change memory (or resistive memory) concept shown in  FIGS. 34A-L , and all other masks are shared between different layers. The process flow may include several steps as described in the following sequence. 
     Step (A): Peripheral circuits with tungsten wiring  3402  are first constructed and above this a layer of silicon dioxide  3404  is deposited.  FIG. 34A  illustrates the structure after Step (A). 
     Step (B):  FIG. 34B  illustrates the structure after Step (B). A wafer of p− Silicon  3406  has an oxide layer  3408  grown or deposited above it. Following this, hydrogen is implanted into the p− Silicon wafer at a certain depth indicated by  3410 . Alternatively, some other atomic species such as Helium could be (co-)implanted. This hydrogen implanted p− Silicon wafer  3406  forms the top layer  3412 . The bottom layer  3414  may include the peripheral circuits  3402  with oxide layer  3404 . The top layer  3412  is flipped and bonded to the bottom layer  3414  using oxide-to-oxide bonding.
 
Step (C):  FIG. 34C  illustrates the structure after Step (C). The stack of top and bottom wafers after Step (B) is cleaved at the hydrogen plane  3410  using either a anneal or a sideways mechanical force or other means. A CMP process is then conducted. At the end of this step, a single-crystal p− Si layer exists atop the peripheral circuits, and this has been achieved using layer-transfer techniques.
 
Step (D):  FIG. 34D  illustrates the structure after Step (D). Using lithography and then implantation, n+ regions  3416  and p− regions  3418  are formed on the transferred layer of p− Si after Step (C).
 
Step (E):  FIG. 34E  illustrates the structure after Step (E). An oxide layer  3420  is deposited atop the structure obtained after Step (D). A first layer of Si/SiO 2    3422  is therefore formed atop the peripheral circuit layer  3402 .
 
Step (F):  FIG. 34F  illustrates the structure after Step (F). Using procedures similar to Steps (B)-(E), additional Si/SiO 2  layers  3424  and  3426  are formed atop Si/SiO 2  layer  3422 . A rapid thermal anneal (RTA) or spike anneal or flash anneal or laser anneal is then done to activate all implanted layers  3422 ,  3424  and  3426  (and possibly also the peripheral circuit layer  3402 ). Alternatively, the layers  3422 ,  3424  and  3426  are annealed layer-by-layer as soon as their implantations are done using a laser anneal system.
 
Step (G):  FIG. 34G  illustrates the structure after Step (G). Lithography and etch processes are then utilized to make a structure as shown in the figure.
 
Step (H):  FIG. 34H  illustrates the structure after Step (H). Gate dielectric  3428  and gate electrode  3430  are then deposited following which a CMP is done to planarize the gate electrode  3430  regions. Lithography and etch are utilized to define gate regions over the p− silicon regions (eg. p− Si region  3418  after Step (D)). Note that gate width could be slightly larger than p− region width to compensate for overlay errors in lithography.
 
Step (I):  FIG. 34I  illustrates the structure after Step (I). A silicon oxide layer  3432  is then deposited and planarized. It is shown transparent in the figure for clarity. Word-line (WL) and Source-line (SL) regions are shown in the figure.
 
Step (J):  FIG. 34J  illustrates the structure after Step (J). Vias are etched through multiple layers of silicon and silicon dioxide as shown in the figure. A resistance change memory material  3436  is then deposited (preferably with atomic layer deposition (ALD)). Examples of such a material include hafnium oxide, which is well known to change resistance by applying voltage. An electrode for the resistance change memory element is then deposited (preferably using ALD) and is shown as electrode/BL contact  3440 . A CMP process is then conducted to planarize the surface. It can be observed that multiple resistance change memory elements in series with transistors are created after this step.
 
Step (K):  FIG. 34K  illustrates the structure after Step (K). BLs  3436  are then constructed. Contacts are made to BLs, WLs and SLs of the memory array at its edges. SL contacts can be made into stair-like structures using techniques described in “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,”  VLSI Technology,  2007  IEEE Symposium on , vol., no., pp. 14-15, 12-14 Jun. 2007 by Tanaka, H.; Kido, M.; Yahashi, K.; Oomura, M.; et al., following which contacts can be constructed to them. Formation of stair-like structures for SLs could be achieved in steps prior to Step (J) as well.
 
 FIG. 34L  shows cross-sectional views of the array for clarity.
 
A 3D resistance change memory has thus been constructed, with (1) horizontally-oriented transistors—i.e. current flowing in substantially the horizontal direction in transistor channels, (2) some of the memory cell control lines, e.g., source-lines SL, constructed of heavily doped silicon and embedded in the memory cell layer, (3) side gates simultaneously deposited over multiple memory layers for transistors, and (4) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut.
 
       FIGS. 35A-F  describes an alternative process flow to construct a horizontally-oriented monolithic 3D resistive memory array. This embodiment has a resistance-based memory element in series with a transistor selector. Two masks are utilized on a “per-memory-layer” basis for the monolithic 3D resistance change memory (or resistive memory) concept shown in  FIGS. 35A-F , and all other masks are shared between different layers. The process flow may include several steps as described in the following sequence. 
     Step (A): The process flow starts with a p− silicon wafer  3502  with an oxide coating  3504 .  FIG. 35A  illustrates the structure after Step (A). 
     Step (B):  FIG. 35B  illustrates the structure after Step (B). Using a process flow similar to  FIG. 2 , a portion of the p− silicon layer  3502  is transferred atop a layer of peripheral circuits  3506 . The peripheral circuits  3506  preferably use tungsten wiring.
 
Step (C):  FIG. 35C  illustrates the structure after Step (C). Isolation regions for transistors are formed using a shallow-trench-isolation (STI) process. Following this, a gate dielectric  3510  and a gate electrode  3508  are deposited.
 
Step (D):  FIG. 35D  illustrates the structure after Step (D). The gate is patterned, and source-drain regions  3512  are formed by implantation. An inter-layer dielectric (ILD)  3514  is also formed.
 
Step (E):  FIG. 35E  illustrates the structure after Step (E). Using steps similar to Step (A) to Step (D), a second layer of transistors  3516  is formed above the first layer of transistors  3514 . A RTA or some other type of anneal is performed to activate dopants in the memory layers (and potentially also the peripheral transistors).
 
Step (F):  FIG. 35F  illustrates the structure after Step (F). Vias are etched through multiple layers of silicon and silicon dioxide as shown in the figure. A resistance change memory material  3522  is then deposited (preferably with atomic layer deposition (ALD)). Examples of such a material include hafnium oxide, which is well known to change resistance by applying voltage. An electrode for the resistance change memory element is then deposited (preferably using ALD) and is shown as electrode  3526 . A CMP process is then conducted to planarize the surface. Contacts are made to drain terminals of transistors in different memory layer as well. Note that gates of transistors in each memory layer are connected together perpendicular to the plane of the figure to form word-lines (WL). Wiring for bit-lines (BLs) and source-lines (SLs) is constructed. Contacts are made between BLs, WLs and SLs with the periphery at edges of the memory array. Multiple resistance change memory elements in series with transistors may be created after this step.
 
A 3D resistance change memory has thus been constructed, with (1) horizontally-oriented transistors—i.e. current flowing in substantially the horizontal direction in the transistor channels, and (2) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut.
 
     While explanations have been given for formation of monolithic 3D resistive memories with ion-cut in this section, it is clear to one skilled in the art that alternative implementations are possible. BL and SL nomenclature has been used for two terminals of the 3D resistive memory array, and this nomenclature can be interchanged. Moreover, selective epi technology or laser recrystallization technology could be utilized for implementing structures shown in  FIGS. 32A-J ,  FIGS. 33A-K ,  FIGS. 34A-L  and  FIGS. 35A-F . Various other types of layer transfer schemes that have been described in Section 1.3.4 can be utilized for construction of various 3D resistive memory structures. One could also use buried wiring, i.e. where wiring for memory arrays is below the memory layers but above the periphery. Other variations of the monolithic 3D resistive memory concepts are possible. 
     Section 5: Monolithic 3D Charge-Trap Memory 
     While resistive memories described previously form a class of non-volatile memory, others classes of non-volatile memory exist. NAND flash memory forms one of the most common non-volatile memory types. It can be constructed of two main types of devices: floating-gate devices where charge is stored in a floating gate and charge-trap devices where charge is stored in a charge-trap layer such as Silicon Nitride. Background information on charge-trap memory can be found in “ Integrated Interconnect Technologies for  3 D Nanoelectronic Systems ”, Artech House, 2009 by Bakir and Meindl (“Bakir”) and “A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device,” Symposium on VLSI Technology, 2010 by Hang-Ting Lue, et al. The architectures shown in  FIGS. 36A-F ,  FIGS. 37A-G  and  FIGS. 38A-D  are relevant for any type of charge-trap memory. 
       FIGS. 36A-F  describes a process flow to construct a horizontally-oriented monolithic 3D charge trap memory. Two masks are utilized on a “per-memory-layer” basis for the monolithic 3D charge trap memory concept shown in  FIGS. 36A-F , while other masks are shared between all constructed memory layers. The process flow may include several steps, that occur in the following sequence. 
     Step (A): A p− Silicon wafer  3602  is taken and an oxide layer  3604  is grown or deposited above it.  FIG. 36A  illustrates the structure after Step (A). 
     Step (B):  FIG. 36B  illustrates the structure after Step (B). Using a procedure similar to the one shown in  FIG. 2 , the p− Si wafer  3602  is transferred atop a peripheral circuit layer  3606 . The periphery is designed such that it can withstand the RTA required for activating dopants in memory layers formed atop it.
 
Step (C):  FIG. 36C  illustrates the structure after Step (C). Isolation regions are formed in the p− Si region  3602  atop the peripheral circuit layer  3606 . This lithography step and all future lithography steps are formed with good alignment to features on the peripheral circuit layer  3606  since the p− Si region  3602  is thin and reasonably transparent to the lithography tool. A dielectric layer  3610  (eg. Oxide-nitride-oxide ONO layer) is deposited following which a gate electrode layer  3608  (eg. polysilicon) are then deposited.
 
Step (D):  FIG. 36D  illustrates the structure after Step (D). The gate regions deposited in Step (C) are patterned and etched. Following this, source-drain regions  3612  are implanted. An inter-layer dielectric  3614  is then deposited and planarized.
 
Step (E):  FIG. 36E  illustrates the structure after Step (E). Using procedures similar to Step (A) to Step (D), another layer of memory, a second NAND string  3616 , is formed atop the first NAND string  3614 .
 
Step (F):  FIG. 36F  illustrates the structure after Step (F). Contacts are made to connect bit-lines (BL) and source-lines (SL) to the NAND string. Contacts to the well of the NAND string are also made. All these contacts could be constructed of heavily doped polysilicon or some other material. An anneal to activate dopants in source-drain regions of transistors in the NAND string (and potentially also the periphery) is conducted. Following this, wiring layers for the memory array is conducted.
 
A 3D charge-trap memory has thus been constructed, with (1) horizontally-oriented transistors—i.e. current flowing in substantially the horizontal direction in transistor channels, and (2) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut. This use of monocrystalline silicon (or single crystal silicon) using ion-cut can be a key differentiator for some embodiments of the current invention vis-à-vis prior work. Past work described by Bakir in his textbook used selective epi technology or laser recrystallization or polysilicon.
 
       FIGS. 37A-G  describes a memory architecture for single-crystal 3D charge-trap memories, and a procedure for its construction. It utilizes junction-less transistors. No mask is utilized on a “per-memory-layer” basis for the monolithic 3D charge-trap memory concept shown in  FIGS. 37A-G , and all other masks are shared between different layers. The process flow may include several steps as described in the following sequence. 
     Step (A): Peripheral circuits  3702  are first constructed and above this a layer of silicon dioxide  3704  is deposited.  FIG. 37A  shows a drawing illustration after Step (A). 
     Step (B):  FIG. 37B  illustrates the structure after Step (B). A wafer of n+ Silicon  3708  has an oxide layer  3706  grown or deposited above it. Following this, hydrogen is implanted into the n+ Silicon wafer at a certain depth indicated by  3714 . Alternatively, some other atomic species such as Helium could be implanted. This hydrogen implanted n+ Silicon wafer  3708  forms the top layer  3710 . The bottom layer  3712  may include the peripheral circuits  3702  with oxide layer  3704 . The top layer  3710  is flipped and bonded to the bottom layer  3712  using oxide-to-oxide bonding.
 
Step (C):  FIG. 37C  illustrates the structure after Step (C). The stack of top and bottom wafers after Step (B) is cleaved at the hydrogen plane  3714  using either a anneal or a sideways mechanical force or other means. A CMP process is then conducted. A layer of silicon oxide  3718  is then deposited atop the n+ Silicon layer  3716 . At the end of this step, a single-crystal n+ Si layer  3716  exists atop the peripheral circuits, and this has been achieved using layer-transfer techniques.
 
Step (D):  FIG. 37D  illustrates the structure after Step (D). Using methods similar to Step (B) and (C), multiple n+ silicon layers  3720  are formed with silicon oxide layers in between.
 
Step (E):  FIG. 37E  illustrates the structure after Step (E). Lithography and etch processes are then utilized to make a structure as shown in the figure.
 
Step (F):  FIG. 37F  illustrates the structure after Step (F). Gate dielectric  3726  and gate electrode  3724  are then deposited following which a CMP is done to planarize the gate electrode  3724  regions. Lithography and etch are utilized to define gate regions. Gates of the NAND string  3736  as well gates of select gates of the NAND string  3738  are defined.
 
Step (G):  FIG. 37G  illustrates the structure after Step (G). A silicon oxide layer  3730  is then deposited and planarized. It is shown transparent in the figure for clarity. Word-lines, bit-lines and source-lines are defined as shown in the figure. Contacts are formed to various regions/wires at the edges of the array as well. SL contacts can be made into stair-like structures using techniques described in “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,”  VLSI Technology,  2007  IEEE Symposium on , vol., no., pp. 14-15, 12-14 Jun. 2007 by Tanaka, H.; Kido, M.; Yahashi, K.; Oomura, M.; et al., following which contacts can be constructed to them. Formation of stair-like structures for SLs could be performed in steps prior to Step (G) as well.
 
A 3D charge-trap memory has thus been constructed, with (1) horizontally-oriented transistors—i.e. current flowing in substantially the horizontal direction in transistor channels, (2) some of the memory cell control lines—e.g., bit lines BL, constructed of heavily doped silicon and embedded in the memory cell layer, (3) side gates simultaneously deposited over multiple memory layers for transistors, and (4) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut. This use of single-crystal silicon obtained with ion-cut is a key differentiator from past work on 3D charge-trap memories such as “A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device,” Symposium on VLSI Technology, 2010 by Hang-Ting Lue, et al. that used polysilicon.
 
     While  FIGS. 36A-F  and  FIGS. 37A-G  give two examples of how single-crystal silicon layers with ion-cut can be used to produce 3D charge-trap memories, the ion-cut technique for 3D charge-trap memory is fairly general. It could be utilized to produce any horizontally-oriented 3D mono crystalline-silicon charge-trap memory.  FIGS. 38A-D  further illustrate how general the process can be. One or more doped silicon layers  3802  can be layer transferred atop any peripheral circuit layer  3806  using procedures shown in  FIG. 2 . These are indicated in  FIG. 38A ,  FIG. 38B  and  FIG. 38C . Following this, different procedures can be utilized to form different types of 3D charge-trap memories. For example, procedures shown in “A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device,” Symposium on VLSI Technology, 2010 by Hang-Ting Lue, et al. and “Multi-layered Vertical Gate NAND Flash overcoming stacking limit for terabit density storage”, Symposium on VLSI Technology, 2009 by W. Kim, S. Choi, et al. can be used to produce the two different types of horizontally oriented single crystal silicon 3D charge trap memory shown in  FIG. 38D . 
     Section 6: Monolithic 3D Floating-Gate Memory 
     While charge-trap memory forms one type of non-volatile memory, floating-gate memory is another type. Background information on floating-gate flash memory can be found in “Introduction to Flash memory”, Proc. IEEE 91, 489-502 (2003) by R. Bez, et al. There are different types of floating-gate memory based on different materials and device structures. The architectures shown in  FIGS. 39A-F  and  FIGS. 40A-H  are relevant for any type of floating-gate memory. 
       FIGS. 39A-F  describe a process flow to construct a horizontally-oriented monolithic 3D floating-gate memory. Two masks are utilized on a “per-memory-layer” basis for the monolithic 3D floating-gate memory concept shown in  FIGS. 39A-F , while other masks are shared between all constructed memory layers. The process flow may include several steps as described in the following sequence. 
     Step (A): A p− Silicon wafer  3902  is taken and an oxide layer  3904  is grown or deposited above it.  FIG. 39A  illustrates the structure after Step (A). 
     Step (B):  FIG. 39B  illustrates the structure after Step (B). Using a procedure similar to the one shown in  FIG. 2 , the p− Si wafer  3902  is transferred atop a peripheral circuit layer  3906 . The periphery is designed such that it can withstand the RTA required for activating dopants in memory layers formed atop it.
 
Step (C):  FIG. 39C  illustrates the structure after Step (C). After deposition of the tunnel oxide  3910  and floating gate  3908 , isolation regions are formed in the p− Si region  3902  atop the peripheral circuit layer  3906 . This lithography step and all future lithography steps are formed with good alignment to features on the peripheral circuit layer  3906  since the p− Si region  3902  is thin and reasonably transparent to the lithography tool.
 
Step (D):  FIG. 39D  illustrates the structure after Step (D). A inter-poly-dielectric (IPD) layer (eg. Oxide-nitride-oxide ONO layer) is deposited following which a control gate electrode  3920  (eg. polysilicon) is then deposited. The gate regions deposited in Step (C) are patterned and etched. Following this, source-drain regions  3912  are implanted. An inter-layer dielectric  3914  is then deposited and planarized.
 
Step (E):  FIG. 39E  illustrates the structure after Step (E). Using procedures similar to Step (A) to Step (D), another layer of memory, a second NAND string  3916 , is formed atop the first NAND string  3914 .
 
Step (F):  FIG. 39F  illustrates the structure after Step (F). Contacts are made to connect bit-lines (BL) and source-lines (SL) to the NAND string. Contacts to the well of the NAND string are also made. All these contacts could be constructed of heavily doped polysilicon or some other material. An anneal to activate dopants in source-drain regions of transistors in the NAND string (and potentially also the periphery) is conducted. Following this, wiring layers for the memory array is conducted.
 
A 3D floating-gate memory has thus been constructed, with (1) horizontally-oriented transistors—i.e. current flow in substantially the horizontal direction in transistor channels, (2) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut. This use of monocrystalline silicon (or single crystal silicon) using ion-cut is a key differentiator for some embodiments of the current invention vis-à-vis prior work. Past work used selective epi technology or laser recrystallization or polysilicon.
 
       FIGS. 40A-H  show a novel memory architecture for 3D floating-gate memories, and a procedure for its construction. The memory architecture utilizes junction-less transistors. One mask is utilized on a “per-memory-layer” basis for the monolithic 3D floating-gate memory concept shown in  FIGS. 40A-H , and all other masks are shared between different layers. The process flow may include several steps that as described in the following sequence. 
     Step (A): Peripheral circuits  4002  are first constructed and above this a layer of silicon dioxide  4004  is deposited.  FIG. 40A  illustrates the structure after Step (A). 
     Step (B):  FIG. 40B  illustrates the structure after Step (B). A wafer of n+ Silicon  4008  has an oxide layer  4006  grown or deposited above it. Following this, hydrogen is implanted into the n+ Silicon wafer at a certain depth indicated by  4014 . Alternatively, some other atomic species such as Helium could be implanted. This hydrogen implanted n+ Silicon wafer  4008  forms the top layer  4010 . The bottom layer  4012  may include the peripheral circuits  4002  with oxide layer  4004 . The top layer  4010  is flipped and bonded to the bottom layer  4012  using oxide-to-oxide bonding.
 
Step (C):  FIG. 40C  illustrates the structure after Step (C). The stack of top and bottom wafers after Step (B) is cleaved at the hydrogen plane  4014  using either a anneal or a sideways mechanical force or other means. A CMP process is then conducted. A layer of silicon oxide  4018  is then deposited atop the n+ Silicon layer  4016 . At the end of this step, a single-crystal n+ Si layer  4016  exists atop the peripheral circuits, and this has been achieved using layer-transfer techniques.
 
Step (D):  FIG. 40D  illustrates the structure after Step (D). Using lithography and etch, the n+ silicon layer  4007  is defined.
 
Step (E):  FIG. 40E  illustrates the structure after Step (E). A tunnel oxide layer  4008  is grown or deposited following which a polysilicon layer  4010  for forming future floating gates is deposited. A CMP process is conducted.
 
Step (F):  FIG. 40F  illustrates the structure after Step (F). Using similar procedures, multiple levels of memory are formed with oxide layers in between.
 
Step (G):  FIG. 40G  illustrates the structure after Step (G). The polysilicon region for floating gates  4010  is etched to form the polysilicon region  4011 .
 
Step (H):  FIG. 40H  illustrates the structure after Step (H). Inter-poly dielectrics (IPD)  4012  and control gates  4014  are deposited and polished.
 
While the steps shown in  FIGS. 40A-H  describe formation of a few floating gate transistors, it will be obvious to one skilled in the art that an array of floating-gate transistors can be constructed using similar techniques and well-known memory access/decoding schemes.
 
A 3D floating-gate memory has thus been constructed, with (1) horizontally-oriented transistors—i.e. current flowing in substantially the horizontal direction in transistor channels, (2) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut, (3) side gates that are simultaneously deposited over multiple memory layers for transistors, and (4) some of the memory cell control lines are in the same memory layer as the devices. The use of monocrystalline silicon (or single crystal silicon) layer obtained by ion-cut in (2) is a key differentiator for some embodiments of the current invention vis-à-vis prior work. Past work used selective epi technology or laser recrystallization or polysilicon.
 
Section 7: Alternative Implementations of Various Monolithic 3D Memory Concepts
 
     While the 3D DRAM and 3D resistive memory implementations in Section 3 and Section 4 have been described with single crystal silicon constructed with ion-cut technology, other options exist. One could construct them with selective epi technology. Procedures for doing these will be clear to those skilled in the art. 
     Various layer transfer schemes described in Section 1.3.4 can be utilized for constructing single-crystal silicon layers for memory architectures described in Section 3, Section 4, Section 5 and Section 6. 
       FIGS. 41A-B  show it is not the only option for the architecture, as depicted in  FIG. 28-FIGS .  40 A-H, to have the peripheral transistors below the memory layers. Peripheral transistors could also be constructed above the memory layers, as shown in  FIG. 41B . This periphery layer would utilize technologies described in Section 1 and Section 2, and could utilize junction-less transistors or recessed channel transistors. 
     The double gate devices shown in  FIG. 28-FIGS .  40 A-H have both gates connected to each other. Each gate terminal may be controlled independently, which may lead to design advantages for memory chips. 
     One of the concerns with using n+ Silicon as a control line for 3D memory arrays is its high resistance. Using lithography and (single-step of multi-step) ion-implantation, one could dope heavily the n+ silicon control lines while not doping transistor gates, sources and drains in the 3D memory array. This preferential doping may mitigate the concern of high resistance. 
     In many of the described 3D memory approaches, etching and filling high aspect ratio vias forms a serious limitation. One way to circumvent this obstacle is by etching and filling vias from two sides of a wafer. A procedure for doing this is shown in  FIGS. 42A-E . Although  FIGS. 42A-E  describe the process flow for a resistive memory implementation, similar processes can be used for DRAM, charge-trap memories and floating-gate memories as well. The process may include several steps that proceed in the following sequence: 
     Step (A): 3D resistive memories are constructed as shown in  FIGS. 34A-K  but with a bare silicon wafer  4202  instead of a wafer with peripheral circuits on it. Due to aspect ratio limitations, the resistance change memory and BL contact  4236  can only be formed to the top layers of the memory, as illustrated in  FIG. 42A .
 
Step (B): Hydrogen is implanted into the wafer  4202  at a certain depth  4242 .  FIG. 42B  illustrates the structure after Step B.
 
Step (C): The wafer with the structure after Step (B) is bonded to a bare silicon wafer  4244 . Cleaving is then performed at the hydrogen implant plane  4242 . A CMP process is conducted to polish off the silicon wafer.  FIG. 42C  illustrates the structure after Step C.
 
Step (D): Resistance change memory material and BL contact layers  4241  are constructed for the bottom memory layers. They connect to the partially made top BL contacts  4236  with state-of-the-art alignment.  FIG. 42D  illustrates the structure after Step D.
 
Step (E): Peripheral transistors  4246  are constructed using procedures shown previously in this document.  FIG. 42E  illustrates the structure after Step E. Connections are made to various wiring layers.
 
     The charge-trap and floating-gate architectures shown in FIGS.  36 A-F- FIGS. 40A-H  are based on NAND flash memory. It will be obvious to one skilled in the art that these architectures can be modified into a NOR flash memory style as well. 
     Section 8: Poly-Silicon-Based Implementation of Various Memory Concepts 
     The monolithic 3D integration concepts described in this patent application can lead to novel embodiments of poly-silicon-based memory architectures as well. Poly silicon based architectures could potentially be cheaper than single crystal silicon based architectures when a large number of memory layers need to be constructed. While the below concepts are explained by using resistive memory architectures as an example, it will be clear to one skilled in the art that similar concepts can be applied to NAND flash memory and DRAM architectures described previously in this patent application. 
       FIGS. 50A-E  shows one embodiment of the current invention, where polysilicon junctionless transistors are used to form a 3D resistance-based memory. The utilized junction-less transistors can have either positive or negative threshold voltages. The process may include the following steps as described in the following sequence: 
     Step (A): As illustrated in  FIG. 50A , peripheral circuits  5002  are constructed above which a layer of silicon dioxide  5004  is made. 
     Step (B): As illustrated in  FIG. 50B , multiple layers of n+ doped amorphous silicon or polysilicon  5006  are deposited with layers of silicon dioxide  5008  in between. The amorphous silicon or polysilicon layers  5006  could be deposited using a chemical vapor deposition process, such as LPCVD or PECVD.
 
Step (C): As illustrated in  FIG. 50C , a Rapid Thermal Anneal (RTA) is conducted to crystallize the layers of polysilicon or amorphous silicon deposited in Step (B). Temperatures during this RTA could be as high as 500° C. or more, and could even be as high as 800° C. The polysilicon region obtained after Step (C) is indicated as  5010 . Alternatively, a laser anneal could be conducted, either for all layers  5006  at the same time or layer by layer. The thickness of the oxide  5004  would need to be optimized if that process were conducted.
 
Step (D): As illustrated in  FIG. 50D , procedures similar to those described in  FIGS. 32E-H  are utilized to construct the structure shown. The structure in  FIG. 50D  has multiple levels of junction-less transistor selectors for resistive memory devices. The resistance change memory is indicated as  5036  while its electrode and contact to the BL is indicated as  5040 . The WL is indicated as  5032 , while the SL is indicated as  5034 . Gate dielectric of the junction-less transistor is indicated as  5026  while the gate electrode of the junction-less transistor is indicated as  5024 , this gate electrode also serves as part of the WL  5032 .
 
Step (E): As illustrated in  FIG. 50E , bit lines (indicated as BL  5038 ) are constructed. Contacts are then made to peripheral circuits and various parts of the memory array as described in embodiments described previously.
 
       FIGS. 51A-F  show another embodiment of the current invention, where polysilicon junction-less transistors are used to form a 3D resistance-based memory. The utilized junction-less transistors can have either positive or negative threshold voltages. The process may include the following steps occurring in sequence: 
     Step (A): As illustrated in  FIG. 51A , a layer of silicon dioxide  5104  is deposited or grown above a silicon substrate without circuits  5102 . 
     Step (B): As illustrated in  FIG. 51B , mulitple layers of n+ doped amorphous silicon or polysilicon  5106  are deposited with layers of silicon dioxide  5108  in between. The amorphous silicon or polysilicon layers  5106  could be deposited using a chemical vapor deposition process, such as LPCVD or PECVD abbreviated as above.
 
Step (C): As illustrated in  FIG. 51C , a Rapid Thermal Anneal (RTA) or standard anneal is conducted to crystallize the layers of polysilicon or amorphous silicon deposited in Step (B). Temperatures during this RTA could be as high as 700° C. or more, and could even be as high as 1400° C. The polysilicon region obtained after Step (C) is indicated as  5110 . Since there are no circuits under these layers of polysilicon, very high temperatures (such as 1400° C.) can be used for the anneal process, leading to very good quality polysilicon with few grain boundaries and very high mobilities approaching those of single crystal silicon. Alternatively, a laser anneal could be conducted, either for all layers  5106  at the same time or layer by layer at different times.
 
Step (D): This is illustrated in  FIG. 51D . Procedures similar to those described in  FIGS. 32E-H  are utilized to get the structure shown in  FIG. 51D  that has multiple levels of junctionless transistor selectors for resistive memory devices. The resistance change memory is indicated as  5136  while its electrode and contact to the BL is indicated as  5140 . The WL is indicated as  5132 , while the SL is indicated as  5134 . Gate dielectric of the junction-less transistor is indicated as  5126  while the gate electrode of the junction-less transistor is indicated as  5124 , this gate electrode also serves as part of the WL  5132 .
 
Step (E): This is illustrated in  FIG. 51E . Bit lines (indicated as BL  5138 ) are constructed. Contacts are then made to peripheral circuits and various parts of the memory array as described in embodiments described previously.
 
Step (F): Using procedures described in Section 1 and Section 2 of this patent application, peripheral circuits  5198  (with transistors and wires) could be formed well aligned to the multiple memory layers shown in Step (E). For the periphery, one could use the process flow shown in Section 2 where replacement gate processing is used, or one could use sub-400° C. processed transistors such as junction-less transistors or recessed channel transistors. Alternatively, one could use laser anneals for peripheral transistors&#39; source-drain processing. Various other procedures described in Section 1 and Section 2 could also be used. Connections can then be formed between the multiple memory layers and peripheral circuits. By proper choice of materials for memory layer transistors and memory layer wires (e.g., by using tungsten and other materials that withstand high temperature processing for wiring), even standard transistors processed at high temperatures (&gt;1000° C.) for the periphery could be used.
 
Section 9: Monolithic 3D SRAM
 
     The techniques described in this patent application can be used for constructing monolithic 3D SRAMs as well. 
       FIGS. 52A-D  represent SRAM embodiment of the current invention, where ion-cut is utilized for constructing a monolithic 3D SRAM. Peripheral circuits are first constructed on a silicon substrate, and above this, two layers of nMOS transistors and one layer of pMOS transistors are formed using ion-cut and procedures described earlier in this patent application. Implants for each of these layers are performed when the layers are being constructed, and finally, after all layers have been constructed, a RTA is conducted to activate dopants. If high k dielectrics are utilized for this process, a gate-first approach may be preferred. 
       FIG. 52A  shows a standard six-transistor SRAM cell according to one embodiment of the current invention. There are two pull-down nMOS transistors, and  5202  represents a pull-down nMOS transistor in  FIGS. 52A-D . There are also two pull-up pMOS transistors, each of which is represented by  5216 . There are two nMOS pass transistors  5204  connecting bit-line wiring  5212  and bit line complement wiring  5214  to the pull-up transistors  5216  and pull-down transistors  5202 , and these are represented by  5214 . Gates of nMOS pass transistors  5214  are represented by  5206  and are connected to word-lines (WL) using WL contacts  5208 . Supply voltage VDD is denoted as  5222  while ground voltage GND is denoted as  5224 . Nodes n 1  and n 2  within the SRAM cell are represented as  5210 . 
       FIG. 52B  shows a top view of the SRAM according to one embodiment of the current invention. For the SRAM described in  FIGS. 52A-D , the bottom layer is the periphery. The nMOS pull-down transistors are above the bottom layer. The pMOS pull-up transistors are above the nMOS pull-down transistors. The nMOS pass transistors are above the pMOS pull-up transistors. The nMOS pass transistors on the topmost layer  5204  are displayed in  FIG. 52B . Gates  5206  for pass transistors  5204  are also shown in  FIG. 52B . All other numerals have been described previously in respect of  FIG. 52A . 
       FIG. 52C  shows a cross-sectional view of the SRAM according one embodiment of the current invention. Oxide isolation using a STI process is indicated as  5200 . Gates for pull-up pMOS transistors are indicated as  5218  while the vertical contact to the gate of the pull-up pMOS and nMOS transistors is indicated as  5220 . The periphery layer is indicated as  5298 . All other numerals have been described in respect of  FIG. 52A  and  FIG. 52B . 
       FIG. 52D  shows another cross-sectional view of the SRAM according one embodiment of the current invention. The nodes n 1  and n 2  are connected to pull-up, pull-down and pass transistors by using a vertical via  5210 .  5226  is a heavily doped n+ Si region of the pull-down transistor,  5228  is a heavily doped p+ Si region of the pull-up transistor and  5230  is a heavily doped n+ region of a pass transistor. All other symbols have been described previously in respect of  FIG. 52A ,  FIG. 52B  and  FIG. 52C . Wiring connects together different elements of the SRAM as shown in  FIG. 52A . 
     It can be seen that the SRAM cell shown in  FIGS. 52A-D  is small in terms of footprint compared to a standard 6 transistor SRAM cell. Previous work has suggested building six-transistor SRAMs with nMOS and pMOS devices on different layers with layouts similar to the ones described in  FIGS. 52A-D . These are described in “The revolutionary and truly 3-dimensional 25 F 2  SRAM technology with the smallest S 3  (stacked single-crystal Si) cell, 0.16 um 2 , and SSTFT (stacked single-crystal thin film transistor) for ultra high density SRAM,” VLSI Technology, 2004. Digest of Technical Papers.  2004  Symposium on, vol., no., pp. 228-229, 15-17 Jun. 2004 by Soon-Moon Jung; Jaehoon Jang; Wonseok Cho; Jaehwan Moon; Kunho Kwak; Bonghyun Choi; Byungjun Hwang; Hoon Lim; Jaehun Jeong; Jonghyuk Kim; Kinam Kim. However, these devices are constructed using selective epi technology, which suffers from defect issues. These defects severely impact SRAM operation. The embodiment of this invention described in  FIGS. 52A-D  is constructed with ion-cut technology and is thus far less prone to defect issues compared to selective epi technology. 
     It is clear to one skilled in the art that other techniques described in this patent application, such as use of junction-less transistors or recessed channel transistors, could be utilized to form the structures shown in  FIGS. 52A-D . Alternative layouts for 3D stacked SRAM cells are possible as well, where heavily doped silicon regions could be utilized as GND, VDD, bit line wiring and bit line complement wiring. For example, the region  5226  (in  FIG. 52D ), instead of serving just as a source or drain of the pull-down transistor, could also run all along the length of the memory array and serve as a GND wiring line. Similarly, the region  5228  (in  FIG. 52D ), instead of serving just as a source or drain of the pull-up transistor, could run all along the length of the memory array and serve as a VDD wiring line. The region  5230  could run all along the length of the memory array and serve as a bit line.