Abstract:
A digital signal processor (DSP) includes an instruction fetch unit, an instruction decode unit, a register set and a plurality of work units in communication with the instruction decode unit. A first embodiment calculates two divisions on packed numerators and packed denominators. The DSP work units calculate indexes into a 1/d look-up table and make a final sign correction. A second embodiment calculates an approximation of a vector magnitude of a complex number x+jy. The approximation is based upon √(x 2 +y 2 )≈α*max(|x|, |y|)+β*min(|x|, |y|). The DSP work units calculate the absolute values, find the maxima and minima, and form the packed results of two vector magnitude calculations.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a non-provisional application claiming priority to provisional application Ser. No. 61/153,458, filed on Feb. 18, 2009, entitled “Low Complexity Vectorized Mathematical Functions On Texas Instruments&#39; C64x+™ Platforms”, the teachings of which are incorporated by reference herein. 
    
    
     BACKGROUND 
     A large variety of algorithms need to use specialized mathematical functions, like sin( ), cos( ), a tan( ), and div( ), for their implementation. Some platforms provide special hardware blocks for these functions while other platforms do not have such hardware accelerators and need to implement this functionality in software. The complexity of these software implementations become especially important if these functions need to be called repeatedly in a loop. Also, some applications need high precision versions of these functions while other applications can tolerate approximations. 
     SUMMARY 
     In accordance with at least some embodiments, a digital signal processor (DSP) includes an instruction fetch unit and an instruction decode unit in communication with the instruction fetch unit. The DSP also includes a register set and a plurality of work units in communication with the instruction decode unit. A vector math instruction decoded by the instruction decode unit causes input vectors and output vectors to be aligned with a maximum boundary of the register set and causes parallel operations by the work units. 
     In at least some embodiments, a method for a digital signal processor (DSP) with a register set and work units is provided. The method includes decoding a vector math instruction. In response to decoding the vector math instruction, the method aligns input vectors and output vectors with a maximum boundary of the register set. Further, in response to decoding the vector math instruction, the method performs parallel operations with the register set and work units to complete a math function. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a detailed description of exemplary embodiments of the invention, reference will now be made to the accompanying drawings in which: 
         FIG. 1  illustrates a digital signal processor (DSP) core architecture in accordance with an embodiment of the disclosure; 
         FIGS. 2A-2B  illustrate a division algorithm for the DSP core architecture of  FIG. 1  in accordance with an embodiment of the disclosure; 
         FIG. 3A-3C  illustrate an A tan 2 algorithm for the DSP core architecture of  FIG. 1  in accordance with an embodiment of the disclosure; and 
         FIG. 4  illustrates a complex magnitude algorithm for the DSP core architecture of  FIG. 1  in accordance with an embodiment of the disclosure. 
     
    
    
     NOTATION AND NOMENCLATURE 
     Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . .” Also, the term “couple” or “couples” is intended to mean either an indirect or direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. The term “system” refers to a collection of two or more hardware and/or software components, and may be used to refer to an electronic device or devices or a sub-system thereof. Further, the term “software” includes any executable code capable of running on a processor, regardless of the media used to store the software. Thus, code stored in non-volatile memory, and sometimes referred to as “embedded firmware,” is included within the definition of software. 
     DETAILED DESCRIPTION 
     The following discussion is directed to various embodiments of the invention. Although one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, including the claims. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is meant only to be exemplary of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodiment. 
     Embodiments of the disclosure are directed to techniques for improving the efficiency of vectorized mathematical functions on a digital signal processor (DSP) with a register set and a plurality of work units. In at least some embodiments, a decoded vector math instruction causes input vectors and output vectors to be aligned with a maximum boundary of the DSP register set and causes parallel operations by DSP work units. The vectorized mathematical functions may be approximations that simplify the DSP operations and/or enable parallel operations. The techniques described herein were developed for Texas Instrument&#39;s C64x+™ DSP core, but are not limited to any particular DSP. Rather, the techniques described herein may be utilized to improve the efficiency of vectorized mathematical functions for any digital signal processor (DSP) with features a register set and work units. 
     In accordance with at least some embodiments, vectorized, low-precision, low-complexity versions of a division function, an A tan 2 function, and a complex magnitude function are provided for a DSP. These functions are mapped herein to the C64x+™ DSP core, but are not limited to a particular DSP. The performance of the functions will also be described herein in terms of cycle-performance and the normalized maximum absolute error (NMAE). The division function is referred to herein as “div_lp — 16b — 16b” to indicate that it is a low-precision division function that operates on 16-bit inputs to produce 16-bit results. The A tan 2 function is referred to herein as “a tan 2_lp — 16b — 16b” to indicate that it is a low-precision function to compute the four-quadrant inverse tangent and it operates on 16-bit inputs to produce 16-bit results. The complex magnitude function is referred to herein as “cplxMag_lp — 16b — 16b” to indicate that it is low-precision function to compute the magnitude of a complex number and it operates on 16-bit inputs to produce 16-bit results. 
     It should be noted that the mathematical notation herein uses upper case letters to represent vectors while lower case counterparts represent elements in that vector. For example, x represents elements in vector X (i.e., X={x}). Also, subscripts used with a vector indicates its length, while subscripts used with its elements indicate their index (position) in the vector (e.g., x l  represents the l th  element in X L , which is a vector of length L). 
       FIG. 1  illustrates a digital signal processor (DSP) core architecture  100  in accordance with embodiments of the disclosure. The DSP architecture  100  corresponds to the C64x+™ DSP core, but may also correspond to other DSP cores as well. As shown in  FIG. 1 , the DSP core architecture  100  comprises an instruction fetch unit  102 , a software pipeline loop (SPLOOP) buffer  104 , a 16/32-bit instruction dispatch unit  106 , and an instruction decode unit  108 . The instruction fetch unit  102  is configured to manage instruction fetches from a memory (not shown) that stores instructions for use by the DSP core architecture  100 . The SPLOOP buffer  104  is configured to store a single iteration of a loop and to selectively overlay copies of the single iteration in a software pipeline manner. The 16/32-bit instruction dispatch unit  106  is configured to split the fetched instruction packets into execute packets, which may be one instruction or multiple parallel instructions (e.g., two to eight instructions). The 16/32-bit instruction dispatch unit  106  also assigns the instructions to the appropriate work units described herein. The instruction decode unit  108  is configured to decode the source registers, the destination registers, and the associated paths for the execution of the instructions in the work units described herein. 
     In accordance with C64x+ DSP core embodiments, the instruction fetch unit  102 , 16/32-bit instruction dispatch unit  106 , and the instruction decode unit  108  can deliver up to eight 32-bit instructions to the work units every CPU clock cycle. The processing of instructions occurs in each of two data paths  110 A and  110 B. As shown, the data path A  110 A comprises work units, including a L 1  unit  112 A, a S 1  unit  114 A, a M 1  unit  116 A, and a D 1  unit  118 A, whose outputs are provided to register file A  120 A. Similarly, the data path B  110 B comprises work units, including a L 2  unit  112 B, a S 2  unit  114 B, a M 2  unit  116 B, and a D 2  unit  118 B, whose outputs are provided to register file B  120 B. 
     In accordance with C64x+ DSP core embodiments, the L 1  unit  112 A and L 2  unit  112 B are configured to perform various operations including 32/40-bit arithmetic operations, compare operations, 32-bit logical operations, leftmost 1 or 0 counting for 32 bits, normalization count for 32 and 40 bits, byte shifts, data packing/unpacking, 5-bit constant generation, dual 16-bit arithmetic operations, quad 8-bit arithmetic operations, dual 16-bit minimum/maximum operations, and quad 8-bit minimum/maximum operations. The S 1  unit  114 A and S 2  unit  114 B are configured to perform various operations including 32-bit arithmetic operations, 32/40-bit shifts, 32-bit bit-field operations, 32-bit logical operations, branches, constant generation, register transfers to/from a control register file (the S 2  unit  114 B only), byte shifts, data packing/unpacking, dual 16-bit compare operations, quad 8-bit compare operations, dual 16-bit shift operations, dual 16-bit saturated arithmetic operations, and quad 8-bit saturated arithmetic operations. The M unit  116 A and M unit  116 B are configured to perform various operations including 32×32-bit multiply operations, 16×16-bit multiply operations, 16×32-bit multiply operations, quad 8×8-bit multiply operations, dual 16×16-bit multiply operations, dual 16×16-bit multiply with add/subtract operations, quad 8×8-bit multiply with add operation, bit expansion, bit interleaving/de-interleaving, variable shift operations, rotations, and Galois field multiply operations. The D unit  118 A and D unit  118 B are configured to perform various operations including 32-bit additions, subtractions, linear and circular address calculations, loads and stores with 5-bit constant offset, loads and stores with 15-bit constant offset (the D 2  unit  118 B only), load and store doublewords with 5-bit constant, load and store nonaligned words and doublewords, 5-bit constant generation, and 32-bit logical operations. Each of the work units reads directly from and writes directly to the register file within its own data path. Each of the work units is also coupled to the opposite-side register file&#39;s work units via cross paths. For more information regarding the architecture of the C64x+ DSP core and supported operations thereof, reference may be had to Literature Number: SPRU732H, “TMS320C64x/C64x+ DSP CPU and Instruction Set”, October 2008, which is hereby incorporated by reference herein. 
       FIGS. 2A-2B  illustrate a division algorithm (div_lp — 16b — 16b)  200  for the DSP core architecture  100  of  FIG. 1  in accordance with an embodiment of the disclosure. In vectorized division, for each element in the input vectors containing the input numerators, N L ={n l }, and denominators, D L ={d l }, the division result, R L ={r l } is given by, 
                 r   l     =       n   l       d   l         ,       where   ⁢           ⁢   0     ≤   l   ≤     (     L   -   1     )             
There are various ways to approximate this result. One method would be to use a repeated subtract-and-compare approach. Although such a method would be very accurate, it would need several iterations and thereby would need several cycles on a DSP. Another approach would be to use a look-up table (LUT) to determine
 
               1     d   l       ,         
and then multiply this value by n l  to determine r l . A small LUT is sufficient for applications that are able to tolerate a moderate precision. In accordance with at least some embodiments, an LUT method is used for the division algorithm  200 . In such embodiments, the LUT is assumed to contain the values in unsigned Qx.y format (denoted as UQx.y). Assuming that n l , d l ,
 
             1     d   l           
and r l  are all 16-bit numbers, r l  maintains user-defined q fractional bits, and the LUT is of length 2 K . The computation steps (in fixed point) for the division algorithm  200  are given as,
 
                                     h = norm(d l ),   where 0 ≦ l ≦ (L − 1), h = 0, . . . 15       a = |n l |, b = |d l |;   where 0 ≦ l ≦ (L − 1)       i = (b &lt;&lt; h) &gt;&gt; (15 − K);   where 0 ≦ l ≦ (L − 1), 0 ≦ i ≦ (2L − 1)       i = min(i, 2 K );       g = (32 − y − q − h);   where 0 ≦ q ≦ 15, 0 ≦ y ≦ 15       rndC = 1 &lt;&lt; g;       w = (LUT[i]*a+ rndC) &gt;&gt; g;       w = min(MAX _INT16, w);   // Saturate w       rl = w*sign(n l )*sign(d l );                    
Note that the function “norm” is assumed to return the number of unused bits in the fixed point number.
 
     In  FIGS. 2A-2B , the division algorithm  200  is repeated N/2 times to process N points. As shown in  2 A, packed 16-bit numerators (x n  and x n+1 )  202  and packed 16-bit denominators (y n  and y n+1 )  204  are loaded into 32-bit registers  210  and  218  respectively. Such numerators and denominators may be pre-packed in memory and the loading operations  206  and  208  are performed by at least one D unit (e.g., the D unit  118 A and/or the D unit  118 B). In the division algorithm  200 , the packed numerators in the register  210  are accessed and their absolute value is determined using an ABS2 operation  212  performed by at least one L unit (e.g., the L unit  112 A and/or the L unit  112 B). The results of the ABS2 operation  212  are stored in a 32-bit register  214 . 
     Further, in the division algorithm  200 , the packed denominators in the register  218  are accessed and their absolute value is determined by an ABS2 operation  215  performed by at least one L unit (e.g., the L unit  112 A and/or the L unit  112 B). The results of the ABS2 operation  215  are stored in a 32-bit register  220 . The absolute values of the denominators are accessed from the register  220  and are shifted by operations  222 ,  224 ,  226 ,  228  to create division table LUT indexes (i n+1  and i n ). The shift operations  222 ,  224 ,  226 ,  228  are performed by at least one S unit (e.g., the S unit  114 A and/or the S unit  114 B). As shown, the shift operations  224  and  228  may be performed in parallel with the shift operations  222  and  226  to determine i n+1  and i n . 
     Further, the absolute values of the denominators are accessed from the register  220  to determine headrooms (h n  and h n+1 )  256 ,  258  and shift-factors (s n  and s n+1 )  260 ,  262  for points n and n+1. The “&amp; 0xffff0000” operation  244  allows the top 16 bits (containing ay n+1 ) to be isolated while the “&amp; 0x0000ffff” operation  246  isolates the bottom 16 bits (containing ay n ). Once the two 16-bit numbers are isolated, the headroom on these numbers (h n+1  and h n ) are determined by NORM operations  248  and  250 , which return the headroom in a 32-bit input. Masking operations (&amp; 0xf)  252  and  254  are used so that only the bottom 4 bits of the NORM result is used to determine the number of unused headroom bits in the 16-bit numbers (ay n+1  and ay n ). After the headrooms are determined, the corresponding shift factors (s n+1  and s n ) are computed as s n+1 =h n+1 +(23−q 0 ) and s n =h n +(23−q 0 ). For the division algorithm  200 , s0=(23−q 0 ). The NORM and masking operations are implemented to track shifting factors that enable the division LUT indexes to have less precision than the points being operated on. As shown, the operations  224 ,  248 ,  252  may be performed in parallel with the operations  246 ,  250 ,  254  to determine s n  and s n+ 1. 
     Further, in the division algorithm  200 , the packed numerators (x n  and x n+1 ) and denominators (y n  and y n+1 ) are accessed from registers  210  and  218  and are XOR&#39;d with the result (d n  and d n+1 ) of the XOR operation  216  being stored in a 32-bit register  234 . The XOR operation  216  is performed by at least one L unit, S unit, or D unit. The values d n  and d n+1  are then operated on to create multiplicative factors (m n  and m n+1 ) using the signs of the numerator and denominator for points n and n+1. If both the numerator and denominator ({x n , y n } or {x n+1 , y n+1 } have the same sign, the most significant bit of the XOR results, represented as MSB(d n ) and MSB(d n+1 ), will be 0. If the numerator and denominator have opposite signs, the most significant bit of the XOR result will be 1. In the division algorithm  200 , the operations  238  and  236  (m n =1−2*MSB(d n )) enable the XOR results to be converted to the appropriate sign for the division result. Thus, if {x n , y n } or {x n+1 , y n+1 } have the same sign, the XOR result will be 0 and m=1, indicating that the final division result should be multiplied by +1. If {x n , y n } or {x n+1 , y n+1 } have different signs, the XOR result will be 1 and m=−1, indicating that the final division result should be multiplied by −1. As shown, the operation  238  may performed in parallel with operation  236  to determine m n  and m n+1 . 
     In  FIG. 2B  of the division algorithm  200 , the normalized values of 1/y are packed into a register  266  for points n and n+1 by a PACK2 operation  265 , where the packed values are labeled dV n  and dV n+1 . As previously mentioned, packing operations are performed by at least one L unit or S unit. Unsigned multiplication of x (accessed from register  214 ) and 1/y (accessed from register  266 ) is then performed for points n and n+1 by multiply operations  268  and  270 . In at least some embodiments, the unsigned multiplication corresponds to MPYHU and MPYU operations performed by at least one M unit (e.g., the M unit  116 A and/or the M unit  116 B). The results of the unsigned multiplications are rounded by adding (ADD operations  272  and  274 ) a round value (mdVal). The ADD operations  272  and  274  may be performed by at least one D unit, L unit, or S unit. A saturated left shift by the headroom values (previously determined) are performed on the rounded results to determine the absolute value for points n and n+1. In at least some embodiments, the shifts correspond to SSHVL operations  276  and  278  performed by at least one M unit. The shifted values are multiplied by the appropriate sign (previously determined) to obtain a result for points n and n+1. In at least some embodiments, this multiplication corresponds to MPYHL operations  280  and  282  performed by at least one M unit. The results (z n  and z n+1 ) are packed using a PACK2 operation  284  performed by at least one L unit or S unit. Finally, a store word operation (STW)  285  is used to store the packed results to a 32-bit register  286 . The STW operation  285  is performed by at least one D unit. As shown, the operations  268 ,  272 ,  276 ,  280  are performed in parallel with the operations  270 ,  274 ,  278 ,  282  to determine z and z+1. 
     To summarize, several optimization techniques may be implemented when the division algorithm  200  is mapped to the C64x+ core. For example, to facilitate use of wide load and store instructions, all input and output vectors may be aligned on 64-bit boundaries. Further, the loop may be unrolled 2 or 4 times. Further, wide load instructions (LDW or LDDW) may be used for loading the numerator and denominator, and wide store instructions (STW or STDW) may be used to store the results. Further, absolute values of two numerators and denominators may be simultaneously found using ABS2 intrinsics. Further, if packed versions of two numerators (16-bits each) and two denominators (16-bits each) are available, the numerators and denominators can be xor&#39;d in a single cycle to determine the sign of the result. A “1” in bit- 15  (and bit- 31 ) would indicate a negative result for the lower (and upper) half word, while a “0” would indicate a positive result. Further, computing m 0 =1−2b 0  and m 1 =1−2b 1  and converting the sign bit with value 1/0 to a 16-bit representation of −1 or +1 may be used as a scale factor later. Note that the values of b 0  (bit- 15 ) and b 1  (bit- 31 ) need to be extracted (e.g., by EXTU intrinsics) from this xor&#39;d result before the scale factor can be generated. Further, the headroom in the numerator and denominator can be found using the NORM intrinsic. Assuming the use of an 8-bit division table, the table index may be found by using the most significant 8 bits (after ignoring the headroom bits). Further, two consecutive values of (1/d 1 ) can be looked up from the table, multiplied with the corresponding numerators, and rounded. The rounding value, which may correspond to one of 16 possible values since the shifts are always less than 16, may also be looked up from the small LUT in order to move complexity from S units to D units, since the division algorithm  200  is S unit limited. Further, the results of the division need to be shifted appropriately, multiplied by m 0  and m 1 , and packed and stored with wide-store instructions. Note that the shift in this case may be accomplished using SSHVL instructions which moves complexity from S units to M units. The performance results of the division algorithm  200  mapped to the C64x+ core were found to be 4 cycles (in terms of cycles per output point using C+ intrinsics code) and the NMAE (with respect to floating point implementation) was found to be less than 10%. Implementation achieves pipelined performance of 4 cycles/output for the C64x+ core. 
       FIG. 3A-3C  illustrate an A tan 2 algorithm (a tan 2_lp — 16b — 16b)  300  for the DSP core architecture  100  of  FIG. 1  in accordance with an embodiment of the disclosure. The A tan 2 algorithm  300  operates on input complex vectors, Z=X+jY, where X={x} and Y={y}, and computes the result, θ=a tan 2(y, x), for each point, where −π≦a tan 2 (y, x)≦π. The resulting output is in 16 bit vector format (SQ3.13 format). In at least some embodiments, the A tan 2 algorithm  300  uses the approximation given below, 
     
       
         
           
             
               
                 
                   
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     In at least some embodiments, the A tan 2 algorithm  300  implements a modified equation (shown below) instead of the equations above to avoid conditional code. 
     
       
         
           
             
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     In  FIGS. 3A-3C , the A tan 2 algorithm  300  is repeated N/2 times to process N points. Each point is represented as a packed 16-bit complex number x+jy. As shown in  FIG. 3A , points n and n+1 (block  302 ) are loaded to a register pair  304 . In at least some embodiments, a load doubleword (LDDW) operation  303  performed by at least one D unit is used to load points n and n+1 to the register pair  304 . A zero-scale (z) is obtained for points n and n+1 by operations  338  and  340 , and the results are packed using a PACK2 operation performed by at least one L unit or S unit. The packed results (zn n+1  and zn n ) are then stored in a register  344 . In  FIG. 3A , an XOR operation  346  is performed on the zero-scaled points accessed from the register  344  and the results are stored in another register  348 . The XOR operation  346  is performed by at least one L unit, S unit, or D unit. The result of the XOR operation is z=0, if the complex number is zero. Otherwise, z=1. 
     As shown in  FIG. 3A , points n and n+1 are also accessed from the register pair  304  to perform a DPACK2 operation  306  that separates the real and imaginary parts into separate registers of a register pair  308 . At operation  310 , c is obtained from the imaginary parts accessed from the register pair  308  and a rotate left operation (ROTL)  314  is performed. The ROTL operation  314  is performed by at least one M unit, which changes shifting operations from S units (typically used for shift operations) to M units. Thereafter, a subtract operation (SUB2)  318  is performed. The results (c n+1  and c n ) of the SUB2 operation  318  are stored in a register  322 . At operation  326 , c n+1  and c n  are multiplied by z n+1  and z n  using an MPY2LL operation  326 , performed by at least one M unit. The results (g n+1  and g n ) are stored in a register pair  330 . A packing operation (PACK2)  334  is performed on g n+1  and g n , which are accessed from the register pair  330 , and the result (v n+1  and v n ) of the PACK2 operation  334  is stored in a register  336 . The PACK2 operation  334  is performed by at least one L unit or S unit. 
     Returning to register pair  308 , a value f is obtained from the real parts stored in the register pair  308  using operation  312 . An XOR operation  316  is then performed by at least one L unit, S unit, or D unit. The result of the XOR operation  316  is multiplied, using a MPY2LL operation  320 , by a packed value b n+1  and b n , where b=3 if the real part is negative. Otherwise, b=1. The MPY2LL operation  320  is performed by at least one M unit. The result (t n+1  and t n ) of the MPY2LL operation  320  is stored by a register pair  324 . The values for t n+1  and t n  are then accessed from the register pair  324  and are packed using a PACK2 operation  328 , where the PACK2 operation  328  is performed by at least one L unit or S unit. The result (f n+1  and f n ) of the PACK2 operation  328  is stored in a register  332 . As shown, operations  310 ,  314 ,  318 ,  326  are performed in parallel with operations  312 ,  316 ,  320 ,  328 . 
     In  FIG. 3B , the real and imaginary parts for n and n+1 are accessed from the register pair  308  for several calculations. As shown, the absolute values for the real and imaginary parts are determined by ABS2 operations  361  and  355 . Further, shift right operations (SHR2)  356  and  362  are performed on the absolute value results by at least one S unit. Subtraction (SUB2) and addition (ADD2) operations  358  and  363  are then performed on the results of the shift operations  356  and  362  by at least one S unit, L unit, or D unit. The absolute value of the result (packed [e n+1  and e n ] for the numerator) of the SUB2 operation  358  is determined by an ABS2 operation  360  and is referred to as “packed [m n+1  and m n ]”. As shown, the operations  355 ,  356 ,  358  are performed in parallel with operations  361 ,  362 ,  363 . 
     Further, the results of the ADD2 operation  363  are shifted by operations  364 ,  365 ,  366 ,  367  to determine LUT indexes i n  and i n+1 . The shift operations  364 ,  365 ,  366 ,  367  are performed by at least one S unit. The “&amp; 0xffff” operation  368  corresponds to a bit-wise AND operation with hexadecimal number 0xffff to isolate the number represented by the least 16-bits of the input. As shown, the operations  364 ,  366  may be performed in parallel with the operations  365 ,  367  to determine i n  and i n+1 . Further, the results of the ADD2 operation  363  are operated on to determine headroom values h n  and h n+1  for the denominator. The “&amp; 0xffff0000” operation  372  allows the top 16 bits of the ADD2 operation  363  result to be isolated while the “&amp; 0x0000ffff” operation  371  isolates the bottom 16 bits of the ADD2 operation  363  result. Once the two 16-bit numbers are isolated, the headroom on these numbers (h n+1  and h n ) are determined by NORM operations  373  and  374 , which return the headroom in a 32-bit input. Masking operations (&amp; 0xf)  375  and  376  are used so that only the bottom 4 bits of the NORM result is used to determine the headroom values (h n+1  and h n ). As shown, the operations  371 ,  373 ,  375  may be performed in parallel with operations  372 ,  374 ,  376  to determine h n  and h n+1 . 
     In  FIG. 3B , the real parts from register pair  308  are also XOR&#39;d with packed values [e n+1  and e n ] by operation  350 . The XOR operation  350  is performed by at least one L, S, or D unit. The result of the XOR operation  350  is compared with 0 using a CMPGT2 operation  351 , performed by at least one S unit. The result (p n+1  and p n ) of the CMPGT2 operation  351  is loaded by LWD operation  352  to a register  354 . 
     In  FIG. 3C , numerators [m n+1  and m n ] and 1/denominators (divTable[i n+1 ] and divTable[i n ]) are multiplied using MPYHL and MPY operations  380  and  381 , performed by at least one M unit. The results of the multiplication operations  380  and  381  are shifted by SSHVL operations  382  and  383 , performed by at least one M unit. Subsequently, these shifted values are multiplied by p n+1  and p n  (previously determined) using MPYH and MPYHL operations  384  and  385 , performed by at least one M unit. The results of the MPYH and MPYHL operations  384  and  385  are packed together by a PACK2 operation  386 , performed by at least one L unit or S unit. A SUB2 operation  388  is performed on the PACK2 result by at least one L unit, S unit, or D unit, with f n+1  and f n  (previously determined) being subtracted. The results of the SUB2 operation  388  are multiplied by v n+1  and v n  using a MPY2LL operation  390 , performed by at least one M unit. The results (u n+1  and u n ) of the MPY2LL operation  390  are stored by a register pair  392 . The values u n+1  and u n  are then accessed from the register pair  392  and are packed using a PACK2 operation  394 , performed by at least one L unit or S unit. A store operation (STW)  395 , performed by at least one S unit, is used to store the results (r n+1  and r n ) of the PACK2 operation  394  to a memory  396 . The values r n+1  and r n  are the final result of the A tan 2 algorithm  300 . As shown, the operations  380 ,  382 ,  384  are performed in parallel with the operations  381 ,  383 ,  385  in the process of determining r n+1  and r n . 
     To summarize, several optimization techniques may be implemented when the A tan 2 algorithm  300  is mapped to the C64x+ core. For example, to facilitate use of wide load and store instructions, all input and output vectors may be aligned on 64-bit boundaries. Further, the loop may be unrolled 2 or 4 times, wide load instructions (LDW or LDDW) may be used for loading two consecutive complex numbers, and wide store instructions (STW or STDW) may be used to store the results. Further, the a tan 2(0,0) corner case needs to be handled separately and the output set to 0. To avoid conditional code, first the packed 32-bit numbers (consisting of both real and imaginary parts) are compared to 0, resulting in 1 (if both parts are zero) or 0 (if at least one of them is non-zero). The results are packed into a 32-bit register and LSBs of the upper and lower half-words are flipped (xor&#39;d with 0x00010001) to obtain a multiplicative scale factor, z, for two consecutive complex numbers. Note that each half of z equals 1 if the inputs are non-zero, or 0 if the inputs are zero. To avoid conditional code, a modified A tan 2 equation (shown below) is implemented. 
     
       
         
           
             
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             where 
           
         
       
       
         
           
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     In the modified A tan 2 equation, the factor, a, is generated by masking the sign-bits (MSBs) on the upper and lower half-words of the packed real parts (x), converting to the 3 or 1 (downshifting it by 14 and adding 1). Further, the factor 
             a   ⁢     π   4           
is computed for two complex numbers with a single instruction by multiplying (MPY2) the results of the previous step with a register containing identical values (π/4) in the upper and lower halves. The factor, b, is generated (for two consecutive complex numbers) by first isolating the sign bits of the imaginary parts of the two numbers (by masking the MSBs of the upper and lower half-words of the packed imaginary parts), rotating the sign bits left by 18 and subtracting the sign bits from a register containing “1” in the upper and lower halves. Note that rotating the sign bits left by 18 is identical to shifting it to the right by 14 (as done for the real parts). However, rotating the sign bits left by 18 moves the computation from the M units (free during these computations) to the S units (heavily loaded during these computations). The combined factor, c=b*z, is computed for two complex numbers in parallel using the MPY2 intrinsic. The numerator and denominator are derived using |x|/2 and |y|/2 for two complex numbers in parallel, using ABS2 and SHR2 intrinsics. Note that the divide by 2 allows the Q-point of the numerator and denominator to remain same as the inputs. Beyond this the division is accomplished using the LUT approach, similar to the division algorithm  200  described previously. The final results of two numbers are scaled by a factor, c, and the results are packed and stored with wide store instructions (STW or STDW). The performance results of the A tan 2 algorithm  300  mapped to the C64x+ core were found to be 4.5 cycles (the pipelined loop kernel performance in terms of cycles per output point using C+ intrinsics code) and the NMAE (with respect to floating point implementation) was found to be less than 0.1 radians. Implementation achieves pipelined performance of 4.5 cycles/output for the C64x+ core.
 
       FIG. 4  illustrates a complex magnitude algorithm (cplxMag_lp — 16b — 16b)  400  for the DSP core architecture  100  of  FIG. 1  in accordance with an embodiment of the disclosure. The complex magnitude algorithm  400  computes the magnitude of a vector of complex numbers, X+jY, where X={x} and Y={y}. In at least some embodiments, the complex magnitude algorithm  400  approximates the value of √{square root over (x 2 +y 2 )} as α max(|x|, |y|)+β min(|x|, |y|), where α and β are two constants whose values are chosen to trade off among RMS error, peak error, and implementation complexity. Various possible values for the constants are known in the art. As an example, the values α=0.947543636291 and β=0.392485425092 may be used. Alternatively, the values α=0.960433870103 and β=0.397824734759 may be used. 
     In  FIG. 4 , the complex magnitude algorithm  400  is repeated N/4 times to process N points. Each point is represented as a packed 16-bit complex number x+jy. As shown in  FIG. 4 , point n+3, n+2, n+1, and n (shown as blocks  401 - 404 ) are loaded to respective registers  409 - 412  using LDW operations  405 - 408  performed by at least one D unit. The absolute values for n+3, n+2, n+1, and n are determined by respective ABS2 operations  413 - 416 , with the results being stored in registers  417 - 420 . As shown, each of the load operations  405 - 408  and each of the ABS2 operations  413 - 416  are performed in parallel. 
     The absolute values for n+3 and n+2 are accessed from registers  417 ,  418  and are packed using a DPACK2 operation  422 , performed by at least one L unit. Similarly, the absolute values for n+1 and n are accessed from registers  419 ,  420  and are packed using a DPACK2 operation  424 , performed by at least one L unit. As shown, the DPACK2 operations  422  and  424  are performed in parallel. 
     The results of the DPACK operation  422  is stored in register pair  426 . As shown, a MAX2 operation  430  and a MIN2 operation  432  are performed on the contents of the register pair  426 . The MAX2 operation  430  is performed by at least one L unit or S unit. Likewise, the MIN2 operation  432  is performed by at least one L unit or S unit. The results of the MAX2 operation  430  and the MIN2 operation  432  are packed using a DPACK2 operation  438 , performed by at least one L unit. The results of the DPACK2 operation  438  are stored in register pair  442 . The contents of the register pair  442  are accessed for DOTPRSU2 operations  446 ,  448 , performed by at least one M unit. The results of the DOTPRSU2 operations  446 ,  448  are packed using a PACK2 operation  454 , performed by at least one L unit or S unit. A store operation (STW)  458  is used to store the results (z n+3  and z n+2 ) of the PACK2 operation  454  in a register  462 , where the STW operation  458  is performed by at least one D unit. 
     A similar process occurs for n+1 and n, with the results of the DPACK operation  424  being stored in register pair  428 . As shown, a MAX2 operation  434  and a MIN2 operation  436  are performed on the contents of the register pair  428 . The MAX2 operation  434  is performed by at least one L unit or S unit. Likewise, the MIN2 operation  436  is performed by at least one L unit or S unit. The results of the MAX2 operation  434  and the MIN2 operation  436  are packed using a DPACK2 operation  440 , performed by at least one L unit. The results of the DPACK2 operation  440  are stored in register pair  444 . The contents of the register pair  444  are accessed for DOTPRSU2 operations  450 ,  452 , performed by at least one M unit. The results of the DOTPRSU2 operations  450 ,  452  are packed using a PACK2 operation  456 , performed by at least one L unit or S unit. A store operation (STW)  460  is used to store the results (z n+1  and z n ) of the PACK2 operation  456  in a register  464 , where the STW operation  460  is performed by at least one D unit. As shown, the operations for determining z n+3  and z n+2  are performed in parallel with the operations for determining z n+1  and z n . Further, various operations (e.g., MAX2 and MIN2 operations; and DOTPRSU2 operations) are performed in parallel for each point. 
     To summarize, several optimization techniques may be implemented when the complex magnitude algorithm  400  is mapped to the C64x+ core. For example, to facilitate use of wide load and store instructions, all input and output vectors may be aligned on 64-bit boundaries. Further, the loop may be unrolled 2 or 4 times. Further, wide load instructions (LDW or LDDW) may be used for loading the real and imaginary parts of two numbers together, and wide store instructions (STW or STDW) may be used to store the results. Improvements may be achieved by unrolling the loop once more and using 64-bit loads and stores. Further, absolute values of two numerators and denominators values may be simultaneously found using ABS2 instructions. Further, the real parts of the two consecutive points need to be packed together followed by their imaginary parts. The DPACK2 intrinsic may be used to do the half-word shuffling. Further, the MAX2 and MIN2 intrinsics may be used on the packed output of the previous step to find maximum and minimum values of the real and imaginary parts. Note that various intrinsics can work on a pair of complex numbers in parallel. Again, the intrinsic DPACK2 may be used to pack the max and min values of each number together. Further, the intrinsic DOTPRSU2 may be used to compute α max(|x|, |y|)+β min(|x|, |y|) for each complex value separately. Note that the max/min values are packed as the output of the previous step. Prior to starting the loop, the values for α/2 and β/2 can be packed together in a 32-bit register to facilitate the parallel multiple-and-add. A factor of 2 is used on the constants to prevent overflow. Further, wide aligned store instructions (STW or STDW) may be used to store the final results. The performance results of the complex magnitude algorithm  400  mapped to the C64x+ core were found to be 1 cycle (the pipelined loop kernel performance in terms of cycles per output point using C+ intrinsics code) and the NMAE (with respect to floating point implementation) was found to be less than 5%. Implementation achieves pipelined performance of 1 cycle/output for the C64x+ core. 
     Although various embodiments described herein are mapped to the C64x+ DSP core, it should be understood that the division algorithm  200 , the A tan 2 algorithm  300 , and the complex magnitude algorithm  400  may be mapped to other DSP cores. Other DSP cores may have different register sizes, different arrangement of work units (e.g., L units, D units, S units, and M units), different instruction sets, and different operations (e.g., intrinsics). In accordance with embodiments, the algorithms described herein, maximize the amount of data operated on per clock cycle. This is accomplished by filling available registers to a maximum amount, maximizing each load and store operation, and distributing operations to different work units (e.g., L units, D units, S units, and M units) to enable parallel operations. 
     The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.