Abstract:
A step-down switching regulator prevents an output voltage undershoot and enables a quick lowering of an output voltage immediately after turning off of power supply. The step-down switching regulator includes an NMOS transistor connected between an output terminal and a ground voltage and another NMOS transistor connected in parallel with a synchronous rectification transistor. Upon reception of an on/off signal for terminating the operation of the switching regulator, the NMOS transistors are turned on into an on-state.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention generally relates to step-down switching regulators for supplying power to electronic devices. Particularly, the invention relates to technologies for protecting a power supply circuit and a load circuit upon termination of power supply by quickly lowering a voltage applied to an electronic circuit and preventing the development of an output voltage undershoot due to an inductor. 
         [0003]    2. Description of the Related Art 
         [0004]    When an operation of a power supply circuit supplying power to a load is stopped, it is necessary to quickly lower the voltage inputted to the load. This is because a delay in lowering the applied voltage may lead to an extended application of a low voltage outside a guaranteed operation range to a load electronic circuit, resulting in a malfunction of the electronic circuit or other unexpected troubles. 
         [0005]    In high-efficiency power supply circuits used for small electronic devices, a non-insulated type switching regulator employing an inductor is widely used. In this type of power supply circuits, the use of the inductor may lead to the development of a high voltage across the inductor unless a path is provided for discharging the energy stored in the inductor after turning off of power supply. Such a high voltage often causes malfunctioning or other troubles of the electronic components of the power supply circuit or an electronic circuit connected to an output terminal. 
         [0006]    Japanese Laid-Open Patent Application No. 2007-288863 (hereafter referred to as “Patent Document 1”) discusses a technology whereby the charge stored in an output capacitor is discharged by causing a first switching element in a switching regulator of which one end is connected to ground voltage to turn on when the load circuit is turned off. 
         [0007]    Japanese Laid-Open Patent Application No. 2004-336972 (to be hereafter referred to as “Patent Document 2”) discusses a technology wherein a series circuit of a resistor and a transistor is connected in parallel with a synchronous rectification switching element. The transistor is turned on after turning off of power supply in order to prevent an undershoot that develops at a power-supply-side terminal of an inductor upon turning off of power supply. 
         [0008]    In the switching regulator according to Patent Document 1, the first switching element functions as a switching element for synchronous rectification. Immediately after turning off of power supply, both the main switching element and the synchronous rectification switching element are turned off. As a result, a large negative voltage is produced at the power-supply-side terminal of the inductor immediately after turning off of power supply. 
         [0009]    Because the aforementioned negative voltage is applied across the synchronous rectification switching element, a current flows from the ground voltage to the inductor via a parasitic diode of the synchronous rectification switching element. However, if the power supply is turned off by the activation of an overcurrent protection function or the like, the parasitic diode may be destroyed by the large energy stored in the inductor. The destruction of the parasitic diode leads to a loss of the function of the synchronous rectification switching element, resulting in a failure of the power supply circuit per se. 
         [0010]    In the switching regulator according to Patent Document 2, the charge stored in the output capacitor is discharged via the inductor and the resistor, so that it takes time for the output voltage to decrease after turning off of power supply. Thus, there remains the problem of the extended application of a low voltage outside a guaranteed operation range to an electronic circuit connected to the output terminal. 
       SUMMARY OF THE INVENTION 
       [0011]    It is therefore a general object of the present invention to provide a step-down switching regulator whereby one or more of the aforementioned problems of the prior art are eliminated. 
         [0012]    A more specific object is to provide a step-down switching regulator whereby the undershoot of an output voltage immediately after turning off of power supply can be prevented and the output voltage can be lowered quickly. 
         [0013]    According to one embodiment of the present invention, a synchronous-rectification-type step-down switching regulator converts an input voltage at an input terminal of the switching regulator into a predetermined constant voltage that is applied to a load connected at an output terminal of the switching regulator. 
         [0014]    The switching regulator includes a first switching element configured to perform a switching in accordance with a control signal; an inductor that is charged by the input voltage when the first switching element performs the switching; a second switching element for synchronous rectification configured to discharge the inductor by performing a switching in accordance with the control signal; a control circuit unit configured to control the switching of the first switching element in order to obtain the predetermined constant voltage at the output terminal, the control circuit also being configured to cause the second switching element to perform the switching in an opposite manner to the switching of the first switching element; and a short-circuiting unit configured to connect the output terminal to a ground voltage and also short-circuit the second switching element when the control circuit unit is deactivated. 
         [0015]    In another embodiment, a synchronous-rectification-type step-down switching regulator for converting an input voltage at an input terminal of the switching regulator into a predetermined constant voltage that is applied to a load connected at an output terminal of the switching regulator includes a first switching element configured to perform a switching in accordance with a control signal; an inductor that is charged by the input voltage when the first switching element performs the switching; a second switching element for synchronous rectification configured to discharge the inductor by performing a switching in accordance with the control signal; a control circuit unit configured to control the switching of the first switching element in order to obtain the predetermined constant voltage at the output terminal, the control circuit also being configured to cause the second switching element to perform the switching in an opposite manner to the switching of the first switching element; a short-circuiting unit configured to connect the output terminal to a ground voltage when the control circuit unit is deactivated; and a voltage detecting circuit unit configured to detect a voltage at a connecting portion between the inductor and the second switching element. 
         [0016]    The voltage detecting circuit unit, when the voltage at the connecting portion between the inductor and the second switching element is a negative voltage, turns on the second switching element into a conducting state upon reception of an external signal for terminating the operation of the control circuit unit. 
         [0017]    In another embodiment, a synchronous-rectification-type step-down switching regulator for converting an input voltage at an input terminal of the switching regulator into a predetermined constant voltage that is applied to a load connected at an output terminal of the switching regulator includes a first switching element configured to perform a switching in accordance with a control signal; an inductor that is charged by the input voltage when the first switching element performs the switching; a second switching element for synchronous rectification configured to discharge the inductor by performing a switching in accordance with the control signal; a control circuit unit configured to control the switching of the first switching element in order to obtain the predetermined constant voltage at the output terminal, the control circuit also being configured to cause the second switching element to perform the switching in an opposite manner to the switching of the first switching element; a short-circuiting unit configured to connect the output terminal to a ground voltage when the control circuit unit is deactivated; and an inverse current detection circuit unit configured to turn off the second switching element into a shutdown state upon detection of an inverse current that flows from the output terminal to the second switching element. 
         [0018]    Upon reception of an external signal for terminating the operation of the control circuit unit, the inverse current detection circuit unit turns on the second switching element into a conducting state when a voltage at a connecting portion between the inductor and the second switching element is a negative voltage. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0019]    These and other objects, features and advantages of the invention will be apparent to those skilled in the art from the following detailed description of the invention, when read in conjunction with the accompanying drawings in which: 
           [0020]      FIG. 1  shows a circuit diagram of a step-down switching regulator according to a first embodiment of the present invention; 
           [0021]      FIG. 2  shows a timing chart illustrating waveforms of various signals in the switching regulator shown in  FIG. 1 ; 
           [0022]      FIG. 3  shows a circuit diagram of a step-down switching regulator according to a second embodiment of the present invention; 
           [0023]      FIG. 4  shows a timing chart illustrating waveforms of various signals in the switching regulator shown in  FIG. 3 ; 
           [0024]      FIG. 5  shows a circuit diagram of a step-down switching regulator according to a third embodiment of the present invention; and 
           [0025]      FIG. 6  shows a timing chart illustrating waveforms of various signals in the switching regulator shown in  FIG. 5 . 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0026]    In the following, preferred embodiments of the present invention are described with reference to the drawings. 
         [0027]      FIG. 1  shows a circuit diagram of a step-down switching regulator  1  according to a first embodiment of the present invention. 
         [0028]    The step-down switching regulator  1  is of a synchronous rectification type whereby an input voltage Vin at an input terminal IN is converted into a predetermined constant voltage in order to produce an output voltage Vout at an output terminal OUT that is applied to a load  10 . 
         [0029]    The switching regulator  1  includes a switching transistor M 1  and a synchronous rectification transistor M 2 . The switching transistor M 1 , which is a PMOS transistor, performs a switching operation for an output control for the input voltage Vin. The synchronous rectification transistor M 2  is a NMOS transistor. 
         [0030]    The switching regulator  1  further includes a reference voltage generating circuit  2 ; resistors R 1  and R 2  for output voltage detection; an inductor L 1 ; an output capacitor Co; an error amplifying circuit  3 ; an oscillating circuit  4 ; a pulse wave modulation (PWM) comparator  5 ; a driver circuit  6 ; and NMOS transistors M 3  and M 4 . 
         [0031]    The switching transistor M 1  provides a first switching element, while the synchronous rectification transistor M 2  provides a second switching element. The reference voltage generating circuit  2 , the resistors R 1  and R 2 , the error amplifying circuit  3 , the oscillating circuit  4 , the PWM comparator  5 , and the driver circuit  6  constitute a control circuit unit. The NMOS transistors M 3  and M 4  constitute a short-circuiting unit, in which the NMOS transistor M 3  provides a first short-circuiting switching element and the NMOS transistor M 4  provides a second short-circuiting switching element. The individual circuits other than the inductor L 1  and the capacitor Cl may be integrated into a single integrated circuit (IC). 
         [0032]    The reference voltage generating circuit  2  generates and outputs a predetermined reference voltage Vref. The output-voltage-detecting resistors R 1  and R 2  divide the output voltage Vout to produce a divided voltage Vfb. The error amplifying circuit  3  amplifies a voltage difference between the input divided voltage Vfb and the reference voltage Vref to produce an error voltage Ve. 
         [0033]    The oscillating circuit  4  produces and outputs a predetermined triangular wave signal TW. The PWM comparator  5  generates and outputs a pulse signal Spw for PWM control from the error voltage Ve from the error amplifying circuit  3  and the triangular wave signal TW. The driver circuit  6  produces control signals P 1  and N 1  based on the input pulse signal Spw. The driver circuit  6  then outputs the control signals P 1  and N 1  to the corresponding gate of the switching transistor M 1  and the synchronous rectification transistor M 2  in order to control the driving of the switching transistor M 1  and the synchronous rectification transistor M 2 . 
         [0034]    The switching transistor M 1  and the synchronous rectification transistor M 2  are connected in series between the input terminal IN and the ground voltage Vss. The connecting portion between the switching transistor M 1  and the synchronous rectification transistor M 2  is designated Lx. The inductor L 1  is connected between the connecting portion Lx and the output terminal OUT. 
         [0035]    Between the output terminal OUT and the ground voltage Vss, the resistors R 1  and R 2  are connected in series. The output capacitor Co is also connected between the output terminal OUT and the ground voltage Vss. The divided voltage Vfb is obtained at the connecting portion between the resistors R 1  and R 2 . In the error amplifying circuit  3 , the inverting input terminal is supplied with the divided voltage Vfb while the non-inverting input terminal is supplied with the reference voltage Vref. The output terminal of the error amplifying circuit  3  is connected to the non-inverting input terminal of the PWM comparator  5 . 
         [0036]    The inverting input terminal of the PWM comparator  5  is supplied with the triangular wave signal TW. The pulse signal Spw outputted by the PWM comparator  5  is supplied to one of the input terminals of the driver circuit  6 . The gate of each of the switching transistor M 1  and the synchronous rectification transistor M 2  is connected to the corresponding output terminal of the driver circuit  6 , so that the corresponding control signal P 1  or N 1  is supplied to the gate. 
         [0037]    The NMOS transistor M 3  is connected between the output terminal OUT and the ground voltage Vss. The NMOS transistor M 4  is connected between the connecting portion Lx and the ground voltage Vss. The other input terminal of the driver circuit  6  and the gate of each of the NMOS transistors M 3  and M 4  are supplied with an on/off signal ST that is externally inputted for an on/off control of the switching regulator  1 . The diode D 1  is a parasitic diode that is formed when the synchronous rectification transistor M 2  is implemented on an IC chip. 
         [0038]      FIG. 2  shows a timing chart illustrating examples of each of the signals in the switching regulator  1  shown in  FIG. 1 . iL indicates an inductor current that flows in the inductor L 1 . VLx indicates a voltage at the connecting portion Lx. M 1  through M 4  indicate the operation of each of the transistors M 1  through M 4 . 
         [0039]    With reference to  FIG. 2 , an operation of the switching regulator  1  shown in  FIG. 1  is described. When the on/off signal ST is at a low level (“L”), the switching regulator  1  is activated. When the on/off signal ST is at a high level (“H”), the switching regulator  1  is deactivated. 
         [0040]    When the on/off signal ST is at low level, the driver circuit  6  is activated while the NMOS transistors M 3  and M 4  are turned off into a shutdown state. In this state, as the output voltage Vout of the switching regulator  1  increases, the error voltage Ve outputted by the error amplifying circuit  3  decreases, so that the duty cycle of the pulse signal Spw outputted by the PWM comparator  5  is reduced. As a result, the time in which the switching transistor M 1  is on becomes shorter. Correspondingly, the time in which the synchronous rectification transistor M 2  is on becomes longer, so that the output voltage Vout of the switching regulator  1  decreases. 
         [0041]    As the output voltage Vout of the switching regulator  1  decreases, the error voltage Ve of the error amplifying circuit  3  increases, whereby the duty cycle of the pulse signal Spw outputted by the PWM comparator  5  increases. As a result, the time in which the switching transistor M 1  is on becomes longer. Correspondingly, the time in which the synchronous rectification transistor M 2  is on becomes shorter, so that the output voltage Vout of the switching regulator  1  increases. By repeating such an operation, the output voltage Vout is controlled to stay at a predetermined voltage. 
         [0042]    Thus, when the on/off signal ST is at low level and the switching regulator  1  is operating, the driver circuit  6  controls the on/off of the switching transistor M 1  and the synchronous rectification transistor M 2  in a complementary manner in accordance with the pulse width of the pulse signal Spw inputted from the PWM comparator  5 . When the switching transistor M 1  is on and the synchronous rectification transistor M 2  is off, the inductor current iL increases, so that the voltage VLx at the connecting portion Lx is substantially equal to the input voltage Vin. 
         [0043]    When the switching transistor M 1  is off and the synchronous rectification transistor M 2  is on, the inductor current iL decreases, so that the voltage VLx at the connecting portion Lx assumes a negative voltage. 
         [0044]    When the on/off signal ST is at high level at time t 1 , the driver circuit  6  turns off both the switching transistor M 1  and the synchronous rectification transistor M 2  regardless of the input pulse signal Spw, thereby terminating the operation of the switching regulator  1 . Because both the NMOS transistors M 3  and M 4  turn on, the energy stored in the inductor L 1  is quickly consumed via the NMOS transistors M 3  and M 4 . The charge in the output capacitor Co is quickly discharged via the NMOS transistor M 3 . 
         [0045]    Although a large negative voltage (undershoot) develops at the connecting portion Lx due to the inverse electromotive force of the inductor L 1 , such undershoot is absorbed by the NMOS transistor M 4 . Thus, the development of undershoot is controlled. By making the impedance when the NMOS transistor M 4  is on smaller than a forward impedance of the parasitic diode D 1  of the synchronous rectification transistor M 2 , hardly any current flows through the parasitic diode D 1 , thereby preventing the destruction of the parasitic diode D 1 . 
         [0046]    Thus, in the switching regulator according to the present embodiment, the development of undershoot immediately after the turning off of power supply can be controlled, and the output voltage Vout can be quickly lowered. 
       Embodiment 2 
       [0047]      FIG. 3  shows a circuit diagram of a step-down switching regulator according to a second embodiment of the present invention. In  FIG. 3 , parts identical or similar to those shown in  FIG. 1  are referenced with similar numerals or signs, with the following description being directed only to different portions from the embodiment of  FIG. 1 . 
         [0048]    The second embodiment in  FIG. 3  differs from the first embodiment of  FIG. 1  in that the NMOS transistor M 4  is eliminated while a comparator  15 , an AND circuit  16 , and an OR circuit  17  are additionally provided. 
         [0049]    In  FIG. 3 , the switching regulator  1   a  is a synchronous rectification type step-down switching regulator whereby an input voltage Vin at an input terminal IN is converted into a predetermined constant voltage to produce an output voltage Vout at an output terminal OUT that is applied to a load  10 . 
         [0050]    The switching regulator  1   a  includes a switching transistor M 1 ; a synchronous rectification transistor M 2 ; a reference voltage generating circuit  2 ; output-voltage-detecting resistors R 1  and R 2 ; an inductor L 1 ; an output capacitor Co; an error amplifying circuit  3 ; an oscillating circuit  4 ; a PWM comparator  5 ; a driver circuit  6 ; and an NMOS transistor M 3 . 
         [0051]    In addition, the switching regulator la includes the aforementioned comparator  15 , AND circuit  16 , and OR circuit  17 . 
         [0052]    The NMOS transistor M 3  provides a first short-circuiting switching element as well as a short-circuiting unit. The comparator  15 , the AND circuit  16 , and the OR circuit  17  constitute a voltage detecting circuit unit. The individual circuits other than the inductor L 1  and the capacitor C 1  may be integrated into a single IC. 
         [0053]    A non-inverting input terminal of the comparator  15  is connected to a ground voltage Vss, while its inverting input terminal is connected to a connecting portion Lx. The output terminal of the comparator  15  is connected to one input terminal of the AND circuit  16 . The other input terminal of the AND circuit  16  is supplied with an on/off signal ST. The output terminal of the AND circuit  16  is connected to one input terminal of the OR circuit  17 . The other input terminal of the OR circuit  17  is supplied with a control signal N 1 . The output terminal of the OR circuit  17  is connected to the gate of the synchronous rectification transistor M 2 . 
         [0054]      FIG. 4  shows a timing chart illustrating examples of the waveforms of the various signals in the switching regulator  1   a  shown in  FIG. 3 . M 1  through M 3  indicate the operation of the transistors M 1  through M 3 . With reference to  FIG. 4 , an operation of the switching regulator  1   a  is described. 
         [0055]    When the on/off signal ST is at a low level (“L”) and the switching regulator la is activated, the output terminal of the AND circuit  16  is constantly at low level, so that the operation is identical to that of the switching regulator  1  shown in  FIG. 1 . 
         [0056]    As the on/off signal ST has a high level (“H”) at time t 1 , the driver circuit  6  produces and outputs the control signals P 1  and N 1  so that the switching transistor M 1  and the synchronous rectification transistor M 2  are both turned off. Because the switching transistor M 1  is turned off, the switching regulator  1   a  ceases operating. At this time, the voltage VLx of the connecting portion Lx decreases to a negative voltage, so that the output signal SA of the comparator  15  assumes a high level. As a result, the AND circuit  16  outputs a signal with the same signal level as the signal level of the input on/off signal ST, i.e., a signal of high level. 
         [0057]    Because the output terminal of the AND circuit  16  is connected to the input terminal of the OR circuit  17 , the output signal of the OR circuit  17  also becomes high, thereby turning on the synchronous rectification transistor M 2 . Thus, the undershoot that develops at the connecting portion Lx due to the inverse electromotive force of the inductor L 1  is absorbed by the synchronous rectification transistor M 2 , thus controlling the development of the undershoot. Further, because the NMOS transistor M 3  performs in the same way as in the case of  FIG. 1 , the energy stored in the inductor L 1  is consumed by the synchronous rectification transistor M 2  and the NMOS transistor M 3 . 
         [0058]    When all of the energy in the inductor L 1  is drained, the voltage VLx of the connecting portion Lx assumes the ground voltage Vss, so that the output signal SA of the comparator  15  becomes low. Then, the output signal of the AND circuit  16  assumes low level, and so does the output signal of the OR circuit  17 . Thus, the synchronous rectification transistor M 2  turns off into a shutdown state. 
         [0059]    Preferably, an offset voltage is provided for the input of the comparator  15  so that a low level signal can be reliably obtained at the output terminal of the comparator  15  when the inverting input terminal of the comparator  15  is at the ground voltage Vss. 
         [0060]    Thus, in the switching regulator according to the present embodiment, the development of undershoot immediately after the turning off of power supply can be prevented by using the synchronous rectification transistor M 2  in place of the NMOS transistor M 4  that is used in the first embodiment. Thus, the output voltage Vout can be quickly lowered as in the first embodiment. Further, because the NMOS transistor M 4  shown in  FIG. 1  requires a large transistor with substantially the same size as the synchronous rectification transistor M 2 , the circuit area can be reduced and the chip size when integrated can be reduced even with the addition of the comparator  15 , the AND circuit  16 , and the OR circuit  17 . 
       Embodiment 3 
       [0061]      FIG. 5  shows a circuit diagram of a step-down switching regulator according to a third embodiment of the present invention. In  FIG. 5 , parts identical or similar to those shown in  FIG. 3  are designated with similar numerals, with the following description being directed only to the difference from the embodiment shown in  FIG. 3 . 
         [0062]    The third embodiment shown in  FIG. 5  differs from the second embodiment shown in  FIG. 3  in that the OR circuit  17  is eliminated. 
         [0063]    In  FIG. 5 , the switching regulator  1   b  is a synchronous rectification type step-down switching regulator whereby an input voltage Vin at an input terminal IN is converted into a predetermined constant voltage in order to produce an output voltage Vout at an output terminal OUT that is outputted to a load  10 . 
         [0064]    The switching regulator  1   b  includes a switching transistor M 1 ; a synchronous rectification transistor M 2 ; a reference voltage generating circuit  2 ; output-voltage-detecting resistors R 1  and R 2 ; an inductor L 1 ; an output capacitor Co; an error amplifying circuit  3 ; an oscillating circuit  4 ; a PWM comparator  5 ; a driver circuit  6 ; an NMOS transistor M 3 ; a comparator  15 ; and an AND circuit  16 . 
         [0065]    The NMOS transistor M 3  provides a first short-circuiting switching element as well as a short-circuiting unit. The comparator  15  and the AND circuit  16  constitute an inverse current detection circuit unit. The individual circuits other than the inductor L 1  and the capacitor C 1  may be integrated into a single IC. 
         [0066]    One input terminal of the AND circuit  16  is supplied with a control signal N 1  from the driver circuit  6 . The output terminal of the AND circuit  16  is connected to the gate of the synchronous rectification transistor M 2 . The comparator  15  and the AND circuit  16  constitute an inverse current detection circuit. 
         [0067]      FIG. 6  shows a timing chart illustrating examples of waveforms of various signals in the switching regulator  1   b  shown in  FIG. 5 . M 1  through M 3  indicate the operation of each of the transistors M 1  through M 3 . 
         [0068]    With reference to  FIG. 6 , an operation of the switching regulator  1   b  is described. Initially, a case is considered in which the on/off signal ST is at low level and the switching regulator  1   b  is operating in a continuous mode. 
         [0069]    The interval between time t 0  and time t 1  and the interval between time t 4  and time t 5  are the continuous mode operating intervals. In these operating intervals, the voltage VLx of the connecting portion Lx when the switching transistor M 1  is on and the synchronous rectification transistor M 2  is off is close to the input voltage Vin, so that the output signal SA of the comparator  15  becomes low. When the switching transistor M 1  is off and the synchronous rectification transistor M 2  is on, the voltage VLx at the connecting portion Lx assumes a negative voltage, so that the output signal SA of the comparator  15  becomes high. Thus, the AND circuit  16  outputs a signal with the same signal level as that of the control signal N 1  supplied from the driver circuit  6  to the gate of the synchronous rectification transistor M 2 . 
         [0070]    Next, a case is considered where the switching regulator  1   b  is operating in a non-continuous mode. 
         [0071]    The interval between time t 1  and time t 4  is the non-continuous mode operating interval. In this operating interval, when the switching transistor M 1  is on and the synchronous rectification transistor M 2  is off, the voltage VLx of the connecting portion Lx is close to the input voltage Vin, as in the continuous mode, so that the output signal SA of the comparator  15  becomes low. 
         [0072]    When the switching transistor M 1  is off and the synchronous rectification transistor M 2  is on, the energy stored in the inductor L 1  flows from the ground voltage Vss to the output terminal OUT via the synchronous rectification transistor M 2  that is on and the inductor L 1 . The inductor current iL decreases as the energy stored in the inductor L 1  decreases, whereby the voltage VLx at the connecting portion Lx gradually increases from a negative voltage. 
         [0073]    At time t 2  or time t 3 , the entire energy stored in the inductor L 1  is discharged, so that the voltage VLx at the connecting portion Lx assumes the ground voltage Vss. As the on-time of the synchronous rectification transistor M 2  is further extended, the direction of flow of the inductor current iL is reversed; i.e., it flows from the output terminal OUT to the ground voltage Vss via the inductor L 1  and the synchronous rectification transistor M 2 . Thus, the voltage VLx at the connecting portion Lx becomes a positive voltage, and the output signal SA of the comparator  15  becomes low. As a result, the output signal of the AND circuit  16  also becomes low, whereby the synchronous rectification transistor M 2  is turned off. Thus, the development of the reverse current from the output terminal OUT to the synchronous rectification transistor M 2  can be prevented. 
         [0074]    As the on/off signal ST becomes high at time t 5 , the driver circuit  6  turns off the switching transistor M 1  and turns on the synchronous rectification transistor M 2 . This state is identical to the state where the switching transistor M 1  is turned off when the switching regulator  1  is activated. Namely, the energy stored in the inductor L 1  flows to the output terminal OUT via the synchronous rectification transistor M 2  and the inductor L 1 , resulting in a gradual increase in the voltage VLx of the connecting portion Lx. When the entire energy stored in the inductor L 1  is drained and the voltage VLx at the connecting portion Lx becomes the ground voltage Vss, the signal level of the output signal SA of the comparator  15  is inverted to low level. Consequently, the output signal of the AND circuit  16  also becomes low, whereby the synchronous rectification transistor M 2  is turned off. 
         [0075]    Thus, in the switching regulator according to the third embodiment, during the detection of the inverse current by the inverse current detection circuit, the synchronous rectification transistor M 2  turns on to consume, together with the NMOS transistor M 3  that is on, the energy in the inductor L 1 , as in the second embodiment. Thus, the undershoot of the output voltage Vout can be controlled and the output voltage Vout can be quickly lowered. Furthermore, by employing the inverse current detection circuit to prevent the undershoot in the output voltage Vout, addition of circuitry can be minimized. 
         [0076]    In the third embodiment, the synchronous rectification transistor M 2  is turned off directly by the output signal of the inverse current detection circuit. Preferably, the output signal of the inverse current detection circuit may be inputted to the driver circuit  6  so that the synchronous rectification transistor M 2  can be turned off by the control signal N 1  outputted by the driver circuit  6 . Preferably, as in the second embodiment, an offset voltage is provided to the input of the comparator  15 . 
         [0077]    Although this invention has been described in detail with reference to certain embodiments, variations and modifications exist within the scope and spirit of the invention as described and defined in the following claims. 
         [0078]    The present application is based on the Japanese Priority Application No. 2008-046023 filed Feb. 27, 2008, the entire contents of which are hereby incorporated by reference.