Abstract:
A polyphase filter having a DC offset cancellation network is disclosed. The polyphase filter includes a first filter section to generate a first set of I- and Q- output signals, a second filter section to generate a second set of I- and Q- output signals, and a DC offset cancellation feedback device to generate four DC offset cancellation signals such that when combined with the input I- and Q- signals, the level of DC offset within the polyphase filter is substantially reduced. Also, a transconductance cell useful for the polyphase filter is disclosed. The transconductance cell includes a first pair of FETs having common gates to receive an input signal and common drains to generate a complementary output signal, a second pair of FETs having common gates to receive a complementary input signal and common drains to generate an output signal, and tail current FET to control the transconductance.

Description:
CROSS-REFERENCE TO A RELATED APPLICATION  
       [0001]    This application claims the benefit of the filing date of Provisional Patent Application No. 60/313,139, filed on Aug. 16, 2001, and entitled “Low Noise Image-Reject GM-C Filter with New Transconductance Cell”, which is herein incorporated by reference. 
     
    
     
       FIELD OF THE INVENTION  
         [0002]    This invention relates generally to image-reject filters as used in receivers, and in particular, to a low noise image reject gm-c polyphase filter.  
         BACKGROUND OF THE INVENTION  
         [0003]    Polyphase filters are typically employed in radio frequency (RF) signal receiving applications. Specifically, these filters are used to remove any image signals generated during the down-converting or demodulating stages. A typical receiver includes a low noise amplifier (LNA) to boost the signal level of the received signal while minimizing the amplifier noise added to the signal. Following the LNA stage, a mixer or quadrature mixer is employed to down-convert the received signal to a lower frequency range. The down-converting typically generates the desired signal plus an image signal on the mirror side of the local oscillator signal. To eliminate the image signal, band pass filters, low pass filter, or other types of filters are employed. If a quadrature mixing stage is used which generates I and Q outputs, polyphase filters are used to remove the image signal.  
           [0004]    [0004]FIG. 1 illustrates a block diagram of an exemplary receiver  100  using a prior art image-reject polyphase filter. The receiver  100  consists of a signal source  102  such as an antenna including an LNA to boost the received signal. The receiver  100  further consists of a quadrature demodulator  104  to down-convert and generate the I and Q phases of the received signal. As previously discussed, the down-converted I and Q signals may each include an image signal which needs to be substantially filtered out. Accordingly, the receiver  100  further consists of a polyphase filter  106  including a first polyphase low pass filter (LPF) section  106   a  coupled to a second polyphase LPF section  106   b.    
           [0005]    There are several undesirable characteristics of the prior art polyphase filter  106 . One such characteristic relates to possible DC offset present at the I and Q inputs to the polyphase filter  106  add space. DC offset present at the I and Q inputs to the polyphase filter  106  may saturate and/or imbalance the output of the filter  106 . This DC offset may further degrade the linearity of the receiver  100 . In the prior art, DC blocking capacitors are employed at the inputs and outputs of the polyphase filter  106  to reduce DC offset problems. However, at low frequency filtering applications, the DC blocking capacitors need to be large, which makes it difficult to implement them in integrated circuit. To overcome this problem, another approach of reducing DC offset problems is by using a DC servo loop.  
           [0006]    [0006]FIG. 2 illustrates a block diagram of a prior art servo loop  200  used for DC offset cancellation. The servo loop  200  consists of an adder  202 , a main amplifier  204 , an error amplifier  206 , and a low pass filter (LPF)  208 . An input signal having an undesired DC offset may be present at the input of the main amplifier  204 . The main amplifier  204  amplifies the input signal along with the DC offset. The DC offset at the output of the main amplifier  204  represents an error. The error amplifier  206  generates an error signal which varies as a function of the DC offset at the output of the main amplifier. The low pass filter (LPF)  208  generates the DC offset portion of the error signal which is inversely applied to the adder  202 . In theory, the DC offset error signal cancels the DC offset present in the input signal.  
           [0007]    One problem with the servo loop approach is that it does not work well at canceling DC offset for polyphase filters. The reason being is that an output of a polyphase filter is a function of all of its inputs due to the interconnections of the two filter sections. Thus, the I OUT  of the polyphase filter  106  varies a function of both the I IN  and I OUT . Similarly, the Q OUT  vanes as a function of both I IN  and I OUT . Accordingly, the DC offset at the outputs I OUT  and Q OUT  vary as a function of the DC offsets at both inputs I IN  and I OUT . Thus, the servo loop method, which is useful for only single-input/single output applications, does not work well for canceling DC offset for polyphase filters.  
           [0008]    [0008]FIG. 3 illustrates a block diagram of a prior art transconductance stage  300  used in a polyphase filter. Another drawback of the prior art polyphase filter is the use of its transconductance stage  300 . The transconductance stage  300  consists of input field effect transistors (FETs) Q 1  and Q 2  having their gates coupled in common to receive an input signal, their drains coupled in common, and their sources coupled respectively to V DD  and ground potential. In addition, the transconductance stage  300  consists of output field effect transistors (FETs) Q 3  and Q 4  having their gates and drains coupled in common, to the drains of transistors Q 1  and Q 2  and to generate the transconductance output, and their sources coupled respectively to V DD  and ground potential.  
           [0009]    A drawback of the prior art transconductance stage  300  is that the output transistors Q 3  and Q 4 , acting as an active load for the transconductance stage  300 , add noise to the output current, while not adding to the transconductance. Therefore, the noise added by the prior art transconductance stage degrades the received signal of the receiver  100 . 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]    [0010]FIG. 1 illustrates a block diagram of a communications system using a prior art image-reject polyphase filter;  
         [0011]    [0011]FIG. 2 illustrates a block diagram of a prior art servo loop used for DC offset cancellation;  
         [0012]    [0012]FIG. 3 illustrates a block diagram of a prior art transconductance stage used in a polyphase filter;  
         [0013]    [0013]FIG. 4 illustrates a block diagram of an exemplary communications system using an image-reject polyphase filter in accordance with an embodiment of the invention;  
         [0014]    [0014]FIG. 5 illustrates a schematic diagram of an exemplary image-reject polyphase filter in accordance with another embodiment of the invention;  
         [0015]    [0015]FIG. 6 illustrates a schematic diagram of an exemplary transconductance stage in accordance with another embodiment of the invention; and  
         [0016]    [0016]FIG. 7 illustrates a schematic diagram of an exemplary bias control loop for the exemplary transconductance stage in accordance with another embodiment of the invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0017]    [0017]FIG. 4 illustrates a block diagram of an exemplary communications system  400  using an image-reject polyphase filter in accordance with an embodiment of the invention. The communications system  400  can be configured as a receiver and/or transmitter. The communications system  400  comprises a signal source  402  such as an antenna and/or LNA in the case of a receiver or a baseband subsystem in the case of a transmitter. The communications system  400  further comprises a quadrature demodulator (in the case of a receiver) or modulator (in the case of a transmitter)  404  to generate the I- and Q- input signals. In addition, the communications system  400  comprises a polyphase filter  406  to substantially reduce the power level of any image signal generated by the quadrature demodulator or modulator  404 .  
         [0018]    The polyphase filter  406 , in turn, comprises a first polyphase filter section  406   a,  a second polyphase filter section  406   b,  an inverse linear transfer function section  408 , and four adders  410   a - d.  The first and second polyphase filters  406   a - b  may be configured as low pass filters, band pass filters, or other types of polyphase filters. As customary of polyphase filters, the first and second polyphase filters  406   a - b  include a plurality of interconnections between the two filters  406   a - b.  The inverse linear transfer function  408  includes four inputs coupled respectively to the four outputs of the polyphase filters sections  406   a - b,  and includes four outputs coupled respectively to the adders  410   a - d.  The I-signal output of the quadrature demodulator or modulator  404  is coupled to adders  410   a  and  410   c.  Also, the Q-signal output of the quadrature demodulator or modulator  404  is coupled to adders  410   b  and  410   d.    
         [0019]    As previously discussed in the Background section, each output of the polyphase filter  406  is a function of the four inputs to the filter  406 . Accordingly, the DC offset at each output of the polyphase filter  406  is a function of the various DC offsets at the two inputs to the polyphase filter  406 . In order to substantially reduce the DC offset at the outputs of the polyphase filter  406 , the inverse linear function  408  includes four transfer functions which are inverse to the transfer function of the outputs of the polyphase filter  406  at a frequency near zero (e.g. at DC). Hence, the following relationships substantially hold for the transfer functions H 1-4  of the inverse linear function  408 :  
         [0020]    a. H 1 =I OUT1  ƒ −1 (I IN , Q IN ) @ freq.˜0  
         [0021]    b. H 2 =Q OUT1  ƒ −1 (I IN , Q IN ) @ freq.˜0  
         [0022]    c. H 3 =I OUT2  ƒ −1 (I IN , Q IN ) @ freq.˜0  
         [0023]    d. H 4 =Q OUT2  ƒ −1 (I IN , Q IN ) @ freq.˜0  
         [0024]    where I OUT1  ƒ −1  (I IN , Q IN ) @freq.˜0 is the inverse transfer function for I OUT1  as a function of the inputs I IN , Q IN  at a frequency approximately zero, Q OUT1  ƒ −1 (I IN , Q IN ) @ freq.˜0 is the inverse transfer function for Q OUT1  as a function of the inputs I IN , Q IN  at a frequency approximately zero, I OUT2  ƒ −1 (I IN , Q IN ) @ freq.˜0 is the inverse transfer function for I OUT2  as a function of the inputs I IN , Q IN  at a frequency approximately zero, and Q OUT2  ƒ −1 (I IN , Q IN ) @ freq.˜0 is the inverse transfer function for Q OUT2  as a function of the inputs I IN , Q IN  at a frequency approximately zero.  
         [0025]    Since the inverse transfer function  408  generates DC offset cancellation signals by taking the inverse functions at approximately zero frequency for the respective outputs of the polyphase filter as a function of the inputs I IN , Q IN , the addition of the DC offset cancellation signals with the inputs I IN , Q IN  by the respective adders  410   a - d  substantially cancels out any DC offset at the output of the polyphase filter  406 .  
         [0026]    [0026]FIG. 5 illustrates a schematic diagram of an exemplary image-reject polyphase filter  500  in accordance with another embodiment of the invention. The polyphase filter comprises a first filter section coupled between the I-signal input and the I-signal output, and comprising capacitors C 11 , C 12 , and C 13 , and transconductance stages g m11 , g m12 , g m13 , and g m14 . The capacitors C 11 , C 12 , and C 13  are connected in-shunt with a pair of circularly-connected transconductance stages g m11 , and g m12  connected in-series between shunt capacitors C 11 , and C 12 , and another pair of circularly-connected transconductance stages g m13  and g m14  connected in-series between shunt capacitors C 12  and C 13 .  
         [0027]    The polyphase filter  500  further comprises a second filter section  500  coupled between the Q-signal input and the Q-signal output, and comprising capacitors C 21 , C 22 , and C 23 , and transconductance stages g m1 , g m22 , g m23 , and g m24 . The capacitors C 21 , C 22 , and C 23  are connected in-shunt with a pair of circularly-connected transconductance stages g m21  and g m22  connected in-series between shunt capacitors C 21  and C 22 , and another pair of circularly-connected transconductance stages g m23  and g m24  connected in-series between shunt capacitors C 22  and C 23 .  
         [0028]    The first and second filter sections are interconnected by three circularly-connected transconductance stages. Specifically, a pair of circularly-connected transconductance stages g m31  and g m32  are connected from the I-signal input to the Q-signal input. Another pair of circularly-connected transconductance stages g m35  and g m36  are connected from the I-signal output to the Q-signal output. And, another pair of circularly-connected transconductance stages g m33  and g m33  are connected from shunt capacitor C 12  to shunt capacitor C 22 .  
         [0029]    The polyphase filter  500  can be configured as a low pass filter (LPF) or band pass filter (BPF) depending on the values of the capacitors and the transconductances. A pair of circularly-connected transconductance simulates an inductive impedance. As previously discussed in the Background section, the prior art transconductance stage include output transistors that add noise to the output current, while not adding to the transconductance. Thus, an improved transconductance stage is described below.  
         [0030]    [0030]FIG. 6 illustrates a schematic diagram of an exemplary transconductance stage  600  in accordance with another embodiment of the invention. The transconductance stage  600  comprises a first pair of field effect transistors (FETs) Q A  and Q B  having their gates connected together, their drains connected in together, and their sources connected to the respective sources of FETs M 1  and M 2 . The transconductance stage  600  further comprises a second pair of FETs Q C  and Q D  having their gates connected together, their drains connected in together, and their sources connected to the respective sources of FETs M 1  and M 2 . The drains of FETs M 1  and M 2  are connected respectively to V DD  and ground potential.  
         [0031]    The input signal V INP  and its complementary signal V INN  are applied to the respective gates of FETs Q A-B  and FETs Q C-D . The output signal V OUTP  and its complementary signal V OUTN  are taken off the respective drains of FETs Q C-D  and FETs Q A-B . A bias signal V CMFB  is applied to the gate of FET M 1  to control the biasing of the transistors Q A-D . Also a tail current control feedback signal is applied to the gate of FET M 2  to control the current through the FETs, and therefore the transconductance gain. Since the inputs V INP  and V INN  are applied to the gates of both the NMOS FETs Q B  and Q D  and the PMOS FETs Q A  and Q C , they all add to the transconductance and act as active loads for one another. Therefore, effectively the noise of the transconductance stage is as low as the noise of one MOS transistor.  
         [0032]    [0032]FIG. 7 illustrates a schematic diagram of an exemplary bias control loop  700  for the exemplary transconductance stage  500  in accordance with another embodiment of the invention. The input signal V INP  and its complementary signal V INN  are applied to the transconductance stage  500 , which generates the output signal V OUTP  and its complementary signal V OUTN . The bias control loop  700  comprises a reference current source  702  to generate a constant current I fixOut  and differential amplifier  704 . The reference current source  702  is connected on opposite ends respectively to the outputs of the transconductance stage  500 . The positive and negative input terminals of the differential amplifier  704  are connected respectively to the outputs V OUTP  and V OUTN  of the transconductance stage  500 . The output of the differential amplifier  704  generates the transconductance gain control signal V CURBIAS , and is coupled to the gate of FET M 2 .  
         [0033]    In operation, if the transconductance stage  500  generates a current different than the reference current I fixOut , a voltage differential appears at the inputs to the differential amplifier  704 . In response to this voltage differential, the differential amplifier  704  changes its output (i.e. the transconductance gain control signal V CURBIAS ) to substantially equalize its input voltages. The changing of the transconductance gain control signal V CURBIAS  changes the transconductance of the stage  500  until the output current substantially equal to the reference current I fixout . When this occurs, the transconductance is equal to the desired transconductance for the stage  500  as determined by the reference current I fixOut .  
         [0034]    In the foregoing specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.