Abstract:
A direct capacitance-to-digital converter is provided, including a plurality of switches, an ADC, a reference voltage circuit and a trigger unit. By using trigger unit to control a plurality of switches, and combining the reference voltages outputted by the reference voltage circuit, the converter can directly sense the external to-be-measured capacitor and related stray capacitor, and directly convert the capacitance of the to-be-measured capacitor into accurate digital signal. The present invention can be integrated with other sensors into a single chip to form an integrated direct capacitance-to-digital converter.

Description:
FIELD OF THE INVENTION 
     The present invention generally relates to a direct capacitance-to-digital converter, and more specifically to a converter able to directly sensing the capacitance and converting to precise digital signal without external amplifier. 
     BACKGROUND OF THE INVENTION 
     With the rapid progress of digital technology and the development of semiconductor manufacturing process, the electronic industry has developed highly integrated and powerful processor or graphic chips. However, these powerful digital chips can only operate with the digital input signal, while most of the electrical signals are analog. Therefore, many analog-to-digital converters (ADC) have been developed to meet different demands, such as, high speed or high resolution ADC. The analog electrical signal is usually generated by sensors, such as, voltage sensor, luminance sensor, temperature sensor, ultrasonic sensor, speed sensor or humidity sensor. In particular, the rapid development of sensors applied to Microelectro-mechanical System (MEMS) in recent years has gained popularity in many consumer electronic products. For example, Wii from Nintendo uses a MEMS-based three-axial acceleration sensor to work with wireless controller to achieve the highly creative entertainment. In addition, touch panel is another popular application. 
     These applications use sensors and amplifier to connect to ADC. Among them, Σ-Δ (sigma-delta) ADC is a common choice of ADC. 
       FIG. 1  shows a schematic view of a functional diagram of the conventional apparatus for converting inductive capacitance. As shown in  FIG. 1 , an apparatus  1  for converting inductive capacitance includes a sensor  10 , a sensor amplifier  20 , a bias circuit  30  and ADC  40 , where sensor amplifier  20  amplifies the output signal from sensor  10 , and ADC  40  converts into digital signals. Bias circuitry  30  provides suitable bias voltage for sensor amplifier  20  and ADC  40 . 
       FIG. 2  shows a detailed view of  FIG. 1 . As shown in  FIG. 2 , the electric model of sensor  10  shows a capacitor CS and equivalent input impedance R. Capacitor CS has a capacitance change ACS caused by the external environmental change. Under the condition of bias voltage Vbias, capacitor CS voltage change is ΔVCS, which is amplified by sensor amplifier  20  and input to ADC  40 . Take a one-stage Σ-Δ ADC as an example. ADC  40  includes a first-stage converter circuit  41  and a comparator  45 , where first-stage converter circuit  41  further includes a subtracter  42 , an adder  43 , a delay relay  44  and a digital-to-analog converter (DAC)  46 . DAC  46  converts the digital output signal Vout from comparator  45  into analog signal. Subtracter  42  finds the difference between the output signal of sensor amplifier  20  and the output signal of DAC  46 . Adder  43  adds the output signal of delay relay  44  to the difference, and outputs to delay relay  44  so as to complete the entire ADC operation. As Σ-Δ ADC is a commonly known technique, the above description is only to highlight the key points. 
     In  FIG. 2 , stray capacitor C 2  is connected to capacitor CS and ground. Stray capacitor is an additional equivalent capacitor generated by errors in manufacturing process or circuit layout, and the capacitance of capacitor C 2  will vary with different manufacturing process and circuit. 
     In addition, in a conventional Σ-Δ ADC structure, to improve the resolution of ADC, a structure with a plurality of serial stages is usually used. That is, the output signal of first-stage converter circuit  41  can be passed to the next stage converter circuit, and the last stage converter circuit is connected to the comparator. 
     However, the conventional technique has the drawback of requiring a bias circuit able to generate a bias voltage and a first-stage amplifier so as to increase the sensing sensitivity. However, it is a difficult challenge for the general IC fabrication process to overcome the noise in the bias circuit, and also difficult to integrate into the other existing function blocks operating at low voltage. 
     Another drawback of the conventional technique is requiring a high quality amplifier to amplify the low inductive voltage to the voltage range processable by ADC. As the amplifier requires a large size chip area, the chip cost increases and the offset, gain and noise of the amplifier will also increase the signal error. 
     Yet another drawback of the convention technique is the accuracy of the overall ADC by the stray capacitor due to manufacturing errors or circuit layout, which also varies with the manufacturing process and circuit, leading to the unstable ADC. 
     Hence, it is imperative to devise an apparatus able to directly convert the capacitance to digital signal, by using ADC to directly convert the low level output signal to digital signal to save the sensor amplifier and the bias circuit to facilitate a smaller-size chip area, as well as eliminating the unstable problem of ADC caused by stray capacitor and increasing the ADC accuracy. 
     SUMMARY OF THE INVENTION 
     The primary object of the present invention is to provide a direct capacitance-to-digital converter, by using a trigger unit to control a plurality of switches, combining with reference voltage outputted by reference voltage circuit to directly measure the to-be-measured capacitance change and directly convert into digital signal so as to improve the accuracy of the digital signal, as well as integrating plural switches, converter, reference voltage circuit, and controller into a single chip to form an integrated single-chip without the extra external high voltage bias circuit and high quality sensor amplifier. 
     Another object of the present invention is to provide a direct capacitance-to-digital converter, by using a differential ADC having a differential integrator to convert the inductive capacitance of the to-be-measured element into digital signal in a differential manner so as to improve the anti-interference of noise. 
     Hence, the direct capacitance-to-digital convert of the present invention can solve the drawbacks caused by the stray capacitance of the to-be-measured element. 
     The foregoing and other objects, features, aspects and advantages of the present invention will become better understood from a careful reading of a detailed description provided herein below with appropriate reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention can be understood in more detail by reading the subsequent detailed description in conjunction with the examples and references made to the accompanying drawings, wherein: 
         FIG. 1  shows a functional block diagram of a conventional apparatus for converting the inductive capacitance to voltage; 
         FIG. 2  shows a detailed schematic view of  FIG. 1 ; 
         FIG. 3  shows a functional block diagram of an ADC converter according to the present invention; 
         FIG. 4  shows a detailed schematic view of  FIG. 3 ; 
         FIG. 5  shows a schematic view of the first operation of the first embodiment of the present invention; 
         FIG. 6  shows the waveform of  FIG. 5 ; 
         FIG. 7  shows a schematic view of the second operation of the first embodiment of the present invention; 
         FIG. 8  shows the waveform of  FIG. 7 ; 
         FIG. 9  shows a schematic view of the second embodiment of the first operation of the embodiment; 
         FIG. 10  shows the waveform of  FIG. 9 ; 
         FIG. 11  shows a schematic view of the second embodiment of the present invention; and 
         FIG. 12  shows a schematic view of the second-stage integrator and the comparator of the second embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       FIG. 3  shows a schematic view of the functional block diagram of the direct capacitance-to-digital converter of the present invention. As shown in  FIG. 3 , a direct capacitance-to-digital converter  2  of the present invention includes an ADC  50  and a trigger unit  60 , for sensing the capacitance of to-be-measured capacitor C 1 , and stray capacitor C 2  being the stray capacitance generated by the manufacturing process and being related to capacitor C 1 , where ADC  50  includes a a first-stage integrator  51 , a second-stage integrator  53  and a comparator  55 . Trigger unit  60  controls a first end P 1  and a second end P 2  of to capacitor C 1 , where stray capacitor C 2  is connected to second end P 2  of to-be-measured capacitor C 1 , and trigger unit  60  controls first-stage integrator  51  of ADC  50 . Second-stage integrator  53  and comparator  55  can be implemented with general integrator and comparator. It is worth noting that second-stage integrator  53  can be plural serially-connected integrators to improve the resolution. 
       FIG. 4  shows a detailed schematic view of  FIG. 3 .  FIG. 4  shows the circuit of first-stage integrator  51 . First-stage integrator  51  includes a DAC capacitor C 3 , an external compensation capacitor C 4 , an amplifier OP 1 , an integral capacitor CT, a first switch SW 1 , a second switch SW 2 , a third switch SW 3 , a fourth switch SW 4 , a fifth switch SW 5 , a sixth switch SW 6 , a seventh switch SW 7 , an eighth SW 8  and a ninth switch SW 9 , where all the switches SW 1 -SW 9  are controlled by a first switch signal φ 1 , a second switch signal φ 2 , a third switch signal φ 3 , a third inverted switch signal φ 3 B, a fourth switch signal φ 4  and a fifth switch signal φ 5  generated by trigger unit  60 , for performing charging and discharging on capacitor C 1 , stray capacitor C 2 , DAC capacitor C 3  and external compensation capacitor C 4 , while using the integrator formed by amplifier OP 1  and integral capacitor CT to perform integration to generate a first-stage integrator output voltage Vout 1 . 
     Bias voltage Vbias of  FIG. 4  is generated by a bias circuit (not shown), and first reference voltage V 1 , second reference voltage V 2 , third reference voltage V 3 , high level reference voltage VR+ and low level reference voltage VR− are generated by reference circuit (not shown), where third reference voltage V 3  is higher than second reference voltage V 2 , second reference voltage V 2  is higher than first reference voltage V 1 , and high level reference voltage VR+ is higher than low level reference voltage VR−. 
     Bias circuit and reference circuit can be implemented with general technology, such as Wilson current mirror or Widlar current source as the bias circuit, and breakdown diode with temperature compensation circuit or bandgap reference circuit as the reference circuit. It is worth noting that the present invention is not limited to any specific implementation of the bias circuit or the reference circuit. Any implementation able to provide required bias voltage and reference voltage is within the scope of the present invention. In addition, trigger unit  60  is for generating the switch signals. Therefore, trigger unit  60  implemented by, such as, microprocessor with firmware or logic circuit, is also within the scope of the present invention. 
     DAC capacitor C 3  uses high level reference voltage VR+ and low level reference voltage VR− to realize the DAC function. That is, when comparator  55  outputs a bit “1”, third switch signal φ 3  or fifth switch signal φ 5  generated by trigger unit  60  uses high level reference voltage VR+ to charge DAC capacitor C 3 . When comparator  55  outputs a bit “0”, third inverted switch signal φ 3 B or fourth switch signal φ 5  generated by trigger unit  60  uses low level reference voltage VR− to charge DAC capacitor C 3 . That is, the digital bit “1” is converted into analog high level reference voltage VR+ and digital bit “0” is converted into analog low level reference voltage VR−. 
     External compensation capacitor C 4  is to compensate the parasitic capacitance, and can be implemented by using capacitor array and the internal circuit performing self-rectification of a plurality of bits, or using laser trimming or current trimming to perform the fine-tuning of a plurality of bits. 
     The operation of direct capacitance-to-digital converter  2  of the present invention includes a first operation and a second operation, where the first operation is for sensing the stray capacitance C 2  and the second operation is to combine with the result of the first operation to perform conversion of the to-be-measured capacitor C 1  so as to generate accurate digital signal. The following describes the first and the second operations. 
       FIG. 5  shows a schematic view of the first operation of the first embodiment of the present invention. As shown in  FIG. 5 , first switch signal φ 1 , second switch signal φ 2 , third switch signal φ 3  and third inverted switch signal φ 3 B generated by trigger unit  60  are used to control switches SW 1 -SW 9 . The following description also refers to the waveform of  FIG. 6 . In  FIG. 6 , the operation waveforms of first switch signal φ 1 , second switch signal φ 2 , third switch signal φ 3  and third inverted switch signal φ 3 B are divided into three steps, including reset operation, charge operation and integral operation for setting first end voltage VP 1  of first end P 1  to first reference voltage V 1 , third reference voltage V 3  or second reference voltage V 2 . 
     In the reset operation, first switch signal φ 1  is at high level, second switch signal φ 2  and third switch signal φ 3  are at low level, and third inverted switch signal φ 3 B is at high level. Therefore, first end P 1  and second end P 2  are connected to first reference voltage V 1  to discharge capacitor C 1  and the cross-over voltage is 0V, while stray capacitor C 2  is also discharged to 0V if select right voltage V 1  (note, the symbol “ground” in the schematic is a reference ground, it can be any voltage). 
     In the charge operation, second switch signal φ 2  is at high level, first switch signal φ 1  and third switch signal φ 3  are at low level, and third inverted switch signal φ 3 B is at high level. Therefore, first end P 1  and second end P 2  are connected to third reference voltage V 3  so that the cross-over voltage of capacitor C 1  remains 0V, while stray capacitor C 2  is charged from first reference voltage V 1  to third reference voltage V 3 . 
     In the integral operation, third switch signal φ 3  is at high level, first switch signal φ 1 , second switch signal φ 2  and third inverted switch signal φ 3 B are at low level. 
     Therefore, first end P 1  is connected to second reference voltage V 2 , and second end P 2  is connected to inverted input end of amplifier OP 1 . The charge transfer to OP 1  is C 2 *(V 2 −V 3 ). In the mean time, DAC capacitor C 3  is switched from high level reference voltage VR+ to low level reference voltage VR−. External compensation capacitor C 4  is switched from bias voltage Vbias to high level reference voltage VR+ and the voltage difference is added to the inverted input end of amplifier OP 1 . Amplifier OP 1  and integral capacitor CT perform integral operation on the signal at the inverted input end and generates a first integrator output voltage Vout 1  related to stray capacitor C 2  at the output end of amplifier OP 1 . 
     The total time for the reset operation and the charge operation is T 1 / 2 , and the time for integral operation is T 1 /2, where T 1  is the first operation period. 
       FIG. 7  shows a schematic view of the second operation of the first embodiment of the present invention. As shown in  FIG. 7 , fourth switch signal φ 4  and fifth switch signal φ 5  generated by trigger unit  60  are used to control switches SW 1 -SW 9 . The following description also refers to the waveform of  FIG. 8 . In  FIG. 8 , the operation waveforms of fourth switch signal φ 4  and fifth switch signal φ 5  are divided into two steps, including charge operation and integral operation. 
     In the charge operation, fourth switch signal φ 4  is at high level, and fifth switch signal φ 5  is at low level. Therefore, first end P 1  of capacitor C 1  is connected to second reference voltage V 2 , and second end P 2  is connected to first reference voltage V 1  so that the cross-over voltage of capacitor C 1  is V 1 −V 2 . Stray capacitor C 2  is charged to first reference voltage V 1 . (note, the ground symbol in the schematic is stand for reference ground level, it could be any voltage). First end of DAC capacitor C 3  and first end of external compensation capacitor C 4  are connected to second end P 2  of capacitor C 1 . Second end of DAC capacitor C 3  is connected to high level reference voltage VR+, and second end of external compensation capacitor C 4  is connected to bias voltage Vbias. The time for charge operation is T 2 /2, where T 2  is the second operation period. 
     In the integral operation, fifth switch signal φ 5  is at high level, and fourth switch signal φ 4  is at low level. Therefore, first end P 1  of capacitor C 1  is connected to first reference voltage V 1 , and second end P 2  is connected to inverted input end of amplifier OP 1 . In the mean time, DAC capacitor C 3  is switched from high level reference voltage VR+ to low level reference voltage VR−. External compensation capacitor C 4  is switched from bias voltage Vbias to high level reference voltage VR+ and the voltage difference is added to the inverted input end of amplifier OP 1 . Amplifier OP 1  and integral capacitor CT perform integral operation on the signal at the inverted input end and generates a first integrator output voltage Vout 1  related to capacitor C 1  at the output end of amplifier OP 1 . The time for integral operation is T 2 /2, and therefore the time for charge operation is the same as the time for integral operation. 
     The accurate digital signals can be obtained through first integrator output voltage Vout 1  generated by the aforementioned first and the second operations. 
     Refer to  FIG. 9 . The first operation of the present invention can also have different order and voltage to achieve the identical result. 
     As shown in  FIG. 9 , first switch signal φ 1 , second switch signal φ 2 , third switch signal φ 3  and third inverted switch signal φ 3 B generated by trigger unit  60  are used to control switches SW 1 -SW 9 . The following description also refers to the waveform of  FIG. 10 . In  FIG. 10 , the operation waveforms of first switch signal φ 1 , second switch signal φ 2 , third switch signal φ 3  and third inverted switch signal φ 3 B are divided into two steps, including charge operation and integral operation. 
     In the charge operation, first switch signal φ 1  is at high level, second switch signal φ 2  and third switch signal φ 3  are at low level, and third inverted switch signal φ 3 B is at high level. Therefore, first end P 1  and second end P 2  are connected to first reference voltage V 1  to discharge capacitor C 1  and the cross-over voltage is 0V, while stray capacitor C 2  is charged to first reference voltage V 1 . 
     In the integral operation, second switch signal φ 2  and third switch signal φ 3  are at high level, while first switch signal φ 1  and third inverted switch signal φ 3 B are at low level. Therefore, first end P 1  is connected to second reference voltage V 2 , and second end P 2  is connected to inverted input end of amplifier OP 1 . In the mean time, DAC capacitor C 3  is switched from high level reference voltage VR+ to low level reference voltage VR−. External compensation capacitor C 4  is switched from bias voltage Vbias to high level reference voltage VR+ and the voltage difference is added to the inverted input end of amplifier OP 1 . Amplifier OP 1  and integral capacitor CT perform integral operation on the signal at the inverted input end and generates a first integrator output voltage Vout 1  related to stray capacitor C 2  at the output end of amplifier OP 1 . Again, the “ground reference” symbol can be any voltage. 
     The time for the charge operation is T 1 /2, and the time for integral operation is T 1 /2, where T 1  is the first operation period. 
       FIG. 11  shows a schematic view of a second embodiment of the present invention. Compared to the first embodiment in  FIG. 4 , the second embodiment of the present invention uses differential amplifier to replace the single-ended amplifier of the first embodiment. That is, a differential amplifier OP 1 D is used to replace amplifier OP 1  of  FIG. 4 . In the mean time, inverted integration capacitor CT 1  and non-inverted integration capacitor CT 2  are used to replace integration capacitor CT of  FIG. 4 . In addition, the differential to-be-measure capacitor formed by inverted to-be-measured capacitor C 1   a  and non-inverted to-be-measured capacitor C 1   b  replaces to-be-measured capacitor C 1 , where the voltages at the two ends of inverted to-be-measured capacitor C 1   a  and non-inverted to-be-measured capacitor C 1   b  are controlled by trigger unit  60 . A differential stray capacitor formed by inverted stray capacitor C 2   a  and non-inverted stray capacitor C 2   b  replaces stray capacitor C 2 , a differential DAC capacitor formed by inverted DAC capacitor C 3   a  and non-inverted DAC capacitor C 3   b  replaces DAC capacitor C 3 , and a differential external compensation capacitor formed by inverted external compensation capacitor C 4   a  and non-inverted external compensation capacitor C 4   b  replaces external compensation capacitor C 4 . As the switch signals are the same as in the first embodiment and the overall operation of the circuit is identical, the description is omitted here. 
       FIG. 12  shows a schematic view of the second-stage integrator and the comparator of the second embodiment of the present invention. As shown in  FIG. 10 , the second-stage integrator of the second embodiment includes a differential amplifier OP 2 D, an inverted integration capacitor C 7   a , and non-inverted integration capacitor C 7   b . Comparator Comp is a differential comparator. Inverted DAC capacitor C 6   a  and non-inverted DAC capacitor C 6   b  are to realize the function of DAC, as DAC capacitor C 3  of the first embodiment. Hence, combining the first-stage integrator of  FIG. 9  and the second-stage integrator and comparator of  FIG. 10 , the formed differential ADC has a better anti-noise capability and is applicable to the electrical environment difficult to rid of noise. 
     Although the present invention has been described with reference to the preferred embodiments, it will be understood that the invention is not limited to the details described thereof. Various substitutions and modifications have been suggested in the foregoing description, and others will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims.