Abstract:
A switching circuit between a main circuit and a redundant circuit in a semiconductor device is disclosed. The redundant circuit replaces the main circuit by blowing a fuse. But a nullifying means can nullify blowing of the fuse, if needed. A switching element connected in parallel with the fuse and a control means enable nullification. The control means turn on the switching element to ascertain whether nullification is effective, and fix the nullification by blowing a fuse in the control means.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a switching circuit in a semiconductor device, which enables switching from a main circuit to a redundant circuit in the semiconductor device.  
           [0003]    2. Background Art  
           [0004]    In recent years, ever-greater improvements in density and performance of an IC have been achieved. Moreover, manufacturing processes have also become more minute and precise. Hence, manufacture of a perfectly flawless IC is extremely difficult. For this reason, there has been implemented a method of fabricating a redundant circuit in an IC. If a defective circuit is detected in a test, a flawless redundant circuit will replace it. A replacement is usually implemented with a switching circuit having a fuse.  
           [0005]    A switching circuit having a fuse is also used to tune the internal potential of a circuit to an optimal potential for a circuit operation.  
           [0006]    [0006]FIG. 5 is a schematic diagram showing one example of a prior-art switching circuit.  
           [0007]    As illustrated, reference numeral  1  designates a switching element for supplying an address selection signal to a gate terminal of the redundant circuit; and  2  designates a switching element for supplying a pre-charge signal to the gate terminal. A source terminal of the switching element  1  is grounded, and a drain terminal of the switching element  1  is connected to a source terminal of the switching element  2  by way of a fuse  3 . The drain terminal of the switching element  1  is connected further with a power supply Vcc. A word line (WL) selection signal is supplied to a drain terminal of the switching element  4 . The source terminal of the switching element  4  is connected to a redundant (spare) word line (hereinafter abbreviated as “WL”).  
           [0008]    Here, reference numeral  5  designates a switching element whose gate terminal is to be supplied with an address selection signal; and  6  designates a switching element whose gate terminal is to be supplied with a pre-charge signal. A source terminal of the switching element  5  is grounded, and a drain terminal of the switching element  5  is connected to a source terminal of the switching element  6  and further to a gate terminal of a switching element  8  by way of an inverter  7 .  
           [0009]    A drain terminal of the switching element  6  is connected to a power source Vcc, and a WL selection signal is supplied to a drain terminal of the switching element  8 . A source terminal of the switching element  6  is connected to a main WL. Reference numeral  9  designates a switching element whose gate terminal is connected to a gate terminal of the switching element  4 . A drain terminal of the switching element  9  is connected toa gate terminal of the switching element  8 . Further, a source terminal of the switching element  8  is grounded.  
           [0010]    The operation of the switching circuit will now be described.  
           [0011]    When an address selection signal is input to the switching elements  1  and  5 , either a main WL for effecting read/write of a main cell or a spare WL for effecting read/write of a spare cell is selected. In an initial state of the redundant circuit, the pre-charge signal is input to the switching elements  2  and  6 , thereby turning on the switching elements  2  and  6 . As a result, nodes N 1  and N 2  enter a high level “H.” 
           [0012]    When the redundant circuit is not used, the fuse  3  remains unblown and as is. When an address selection signal is input, the switching elements  1  and  5  are turned on, and a current flows to GND, whereupon the nodes N 1  and N 2  enter a low level “L.” In this state, the switching element  4  is turned off, and the WL selection signal does not enter the spare WL. In this state, the switching element  9  also remains in an OFF state, and hence a node N 3  enters a high level “H.” Further, the switching element  8  is turned on. As a result, the WL selection signal enters a main WL, and a corresponding main cell is selected.  
           [0013]    When the redundant circuit is used, the fuse  3  is blown. When an address selection signal is input, the switching elements  1  and  5  are turned on. The node N 2  enters a low level “L,” and the node N 1  remains in a high level “H” as a result of the fuse  3  having been blown. Since the node N 1  is in a high level “H,” the switching element  4  is turned on, and the WL selection signal enters a spare WL, thereby selecting a corresponding spare cell. In contrast, the switching element  9  is turned on as a result of the node N 1  remaining in a high level “H,” and the node N 3  enters a low level “L.” As a result, the switching element  8  is turned off, and the WL selection signal does not enter the main WL. Thus, a corresponding main cell is not selected.  
           [0014]    In the prior-art circuit, once the fuse is blown for switching, the circuit cannot be restored to its original state. Therefore, if a redundant circuit is found to be defective after the fuse is blown, a semiconductor device including the redundant circuit must be taken as defective.  
         SUMMARY OF THE INVENTION  
         [0015]    The purpose of the present invention is to provide a new switching circuit between a main circuit and a redundant circuit in a semiconductor device, which enable to nullify switching after blowing a fuse.  
           [0016]    According to one aspect of the present invention, a switching circuit comprises one-way-switching means, for example a fuse, to switch from the main circuit to the redundant circuit. And the switching circuit also comprises nullifying means to nullify switching by the one-way-switching means.  
           [0017]    The nullifying means may comprise a switching element, such as a transistor switch, connected in parallel with the one-way-switching means, and a control means to control the switching element. The control means may operate to tentatively turn on the switching element in a test mode to enable to ascertain whether a nullification of switching by the one-way-switching element is effective or not. The control means preferably has a fuse to be blown to fix the switching element ON, that is, to fix the nullification.  
           [0018]    Other and further objects, features and advantages of the invention will appear more fully from the following description. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0019]    [0019]FIG. 1 is a circuit diagram showing a switching circuit according to a first embodiment of the present invention.  
         [0020]    [0020]FIG. 2 is a circuit diagram showing a switching circuit according to a second embodiment.  
         [0021]    [0021]FIG. 3 is an address table used in a second embodiment.  
         [0022]    [0022]FIG. 4 is a circuit diagram showing a switching circuit according to a third embodiment.  
         [0023]    [0023]FIG. 5 is a schematic diagram showing one example of a prior-art switching circuit. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0024]    Embodiments of the present invention will be described hereinbelow with reference to the accompanying drawings while the case of a semiconductor memory device to which the present invention is applied is taken as an example.  
       FIRST EMBODIMENT  
       [0025]    [0025]FIG. 1 is a circuit diagram showing a switching circuit according to a first embodiment of the present invention. In FIG. 1, elements which are the same as those shown in FIG. 5 are assigned the same reference numerals, and repetition of their detailed explanations is omitted.  
         [0026]    As shown in FIG. 1, reference numeral  10  designates a laser trimming (abbreviated as “LT”) nullifying circuit serving as nullifying means which nullifies the laser trimming. The laser trimming nullifying circuit  10  has switching elements  11  through  13 , an inverter  14 , and a fuse  15 . A drain terminal and a source terminal of the switching element  11  are connected across a fuse  3  (one-way-switching means). Further, a gate terminal of the switching element  11  is connected to a power source side of a fuse  15  connected between a power source Vcc and GRD, by way of a node N 5  and a switching element  13 .  
         [0027]    A drain terminal and a gate terminal of the switching element  12  are connected commonly to a node N 4  to which a test mode signal is to be supplied. A source terminal of the switching element  12  is connected to a node N 5 . The node N 4  is connected to a gate terminal of a switching element  13  by way of an inverter  14 . In the LT nullifying circuit  10 , constituent elements other than the switching element  11  are constituted as control means for controlling the operation of the switching element  11 .  
         [0028]    The operation of the switching circuit will be described. Here, the operation of the switching circuit other than the operation of the LT nullifying circuit  10  is identical with that of the switching circuit shown in FIG. 5. Hence, explanations of operation of the switching circuit are omitted here.  
         [0029]    Blowing of the fuse  3  is nullified by means of turning on the switching element  11 , thereby enabling the switching circuit to return to its original state before laser trimming has been effected. The ON/OFF state of the switching element  11  is controlled by means of an “H” or “L” signal level of the node N 5 . In order to control the signal level of the node N 5 , the fuse  15  and the node N 4  are provided. The node N 4  is controlled in a test mode. When the LT nullifying circuit  10  is not used, the node N 4  is set to a low level “L.” 
         [0030]    If nullifying of blowing of the fuse  3  is desired after the fuse  3  is blown, the switching circuit is set to a test mode, thereby bringing the node N 4  to a high level “H.” As a result, a switching element  12  is turned on, and a switching element  13  is turned off, whereupon the node N 5  enters a high level “H.” Further, the switching element  11  is turned on, thereby nullifying blowing of the fuse  3 . The fuse  15  and the power source Vcc is substantially cut off from the switching elements  11  and  12 , by means of reversing the high level “H” of the node N 4  through an inverter  14  and applying a low-level “L” signal to a gate terminal of the inverter  14 , thereby turning off the switching element  13 . A test is effected in this state, thereby determining whether to nullify blowing of the fuse  3 .  
         [0031]    Finally, when nullifying of blowing of the fuse  3  is desired, the fuse  15  of the LT nullifying circuit  10  is blown. At this time, the node N 4  remains in a low level “L,” and hence the node N 5  is switched to a high level “H,” thereby turning on the switching element  11 . Blowing of the fuse  3  can be nullified by means of blowing the fuse  15 . When switching of a memory cell in an X direction is desired to be changed to relief of a memory cell in a Y direction, use of the LT nullifying circuit  10  enables more appropriate operation.  
         [0032]    As mentioned above, in the present embodiment, a switching circuit is provided with an LT nullifying circuit to be used when nullifying of blowing of a fuse effected at the time of use of a redundant circuit is desired. If a found defect in a test after switching is a relievable one, another appropriate operation relieves the semiconductor device from being defectives, and as a result contributing to an improvement in product yield.  
       SECOND EMBODIMENT  
       [0033]    [0033]FIG. 2 is a circuit diagram showing a switching circuit according to a second embodiment of the present invention. In FIG. 1, elements which are the same as those shown in FIG. 2 are assigned the same reference numerals, and repetition of their detailed explanations is omitted.  
         [0034]    As illustrated, reference numeral  3 A designates a fuse box in which a plurality of fuses  30  through  33  are connected in parallel with each other. Terminals provided at one end of the respective fuses  30  through  33  are connected commonly to a node N 1 . Terminals provided at the other end of the respective fuses  30  through  33  are grounded by way of drain and source terminals of corresponding switching elements  100  through  103 .  
         [0035]    As shown in FIG. 3, an address selection signal x 0  is input to a gate terminal of the switching element  100 ; an address selection signal x 1  is input to a gate terminal of the switching element  101 ; an address selection signal x 2  is input to a gate terminal of the switching element  102 ; and an address selection signal x 3  is input to a gate terminal of the switching element  103 . In the present embodiment, the plurality of address selection signals x 0  through x 3  are connected commonly to a single node N 1  connected to a gate terminal of a switching element  4 . An output terminal of the switching element  4  is connected to a spare cell.  
         [0036]    A drain terminal and a source terminal of a switching element  11  of the LT nullifying circuit  10 A are placed across the fuses  30  through  33 . Agate terminal of the switching element  11  is connected to the power supply Vcc by way of a node N 5 , a switching element  13 , and a resistor  16 . The LT nullifying circuit  10 A is identical in circuit configuration with the LT nullifying circuit  10 , except for addition of the resistor  16 .  
         [0037]    A switching element  50  corresponding to the switching element  5  shown in FIG. 1 is provided between the node N 2  and ground. The address selection signal x 0  is input to a gate terminal of the switching element  50 . Similarly, switching elements  51  through  53  are connected between the node N 2  and ground, wherein the address selection signal x 1  is input to a gate terminal of the switching element  51 , the address selection signal x 2  is input to a gate terminal of the switching element  52 , andthe address selection signal x 3  is input to agate terminal of the switching element  53 . A line which corresponds to the node N 2  and is connected to drain terminals of the respective switching elements  51  through  53  is omitted.  
         [0038]    An output side of the switching element  8  whose gate terminal is connected to the node N 3  is connected to a main cell. In other respects, the LT nullifying circuit  10 A is identical with in configuration with the LT nullifying circuit  10  shown in FIG. 1.  
         [0039]    The operation of the LT nullifying circuit  10  will now be described.  
         [0040]    The address selection signal x 0  is input to the switching elements  50  and  100 ; the address selection signal x 1  is input to the switching elements  51  and  101 ; the address selection signal x 2  is input to the switching elements  52  and  102 ; and the address selection signal x 3  is input to the switching elements  53  and  103 . As shown in FIG. 3, each of the address selection signals x 0  through x 3  is composed of two bits of address signals a 0  and a 1 . When the address signals a 0  and a 1  assume “00,” the switching elements  50  and  100  are selected. When the address signals a 0  and a 1  assume “10,” the switching elements  51  and  101  are selected. When the address signals a 0  and a 1  assume “01,” the switching elements  52  and  102  are selected. When the address signals a 0  and a 1  assume “11,” the switching elements  53  and  103  are selected.  
         [0041]    Selection of either a main WL for effecting read/write of a main cell or a spare WL for effecting read/write of a spare cell is effected, by means of inputting the address selection signals x 0  through x 3  into the switching elements  50  through  53  and the switching elements  100  through  103  in a manner identical with that described in connection with the first embodiment.  
         [0042]    The LT nullifying circuit  10 A is substantially identical with that of the LT nullifying circuit  10  described in connection with the first embodiment. In the present embodiment, the switching element  11  is connected in parallel with the fuses  30  through  33  provided in the fuse box  3 A. Hence, nullification of the fuses  30  through  33  is performed simultaneously by means of turning on or off the switching element  11  connected to the fuses  30  through  33 .  
         [0043]    In the present embodiment, a plurality of fuses connected to a spare cell are turned on or off simultaneously. Hence, a plurality of switching operations are corrected simultaneously, thereby contributing to an improvement in product yield and productivity.  
       THIRD EMBODIMENT  
       [0044]    [0044]FIG. 4 is a circuit diagram showing a switching circuit according to a third embodiment of the present invention. In FIG. 4, elements which are the same as those shown in FIGS. 1 and 3 are assigned the same reference numerals, and repetition of their detailed explanations is omitted.  
         [0045]    In the present embodiment, a plurality of fuse boxes are disposed. When nullifications of more than one fuse are needed, the entire fuse box including the fuses is nullified and the next fuse box is subjected to desired LT.  
         [0046]    In the illustrations, reference numerals  3 A 1  through  3 An designate fuse boxes having the same configuration as that of the fuse box  3 A. The fuse boxes  3 A 1  through  3 An are provided respectively with LT nullifying circuit s  10 A 1  through  10 A n  analogous to the LT nullifying circuit  10 A shown in FIG. 2. Terminals provided at one end of the fuse boxes  3 A 1  through  3 A n  are connected to the gate terminal of the switching element  4 . A plurality of switching elements  9   1  through  9   n  analogous to the switching element  9  shown in FIG. 2 are provided for the fuse boxes  3 A 1  through  3 A n . Source terminals of the respective switching elements  9   1  through  9   n  are grounded, and drain terminals of the same are connected to the node N 3 .  
         [0047]    An address decoder  17  including a circuit substantially corresponding to the switching elements  50  through  53  and  100  through  103  is interposed between the node N 2  and the fuse boxes  3 A 1  through  3 A n .  
         [0048]    The operation of the switching circuit will now be described.  
         [0049]    Here, the node N 1  for selecting a spare WL of a spare cell and the node N 2  for selecting the main WL of a main cell are in an initial state; that is, a high level state “H.” Here, when an address selection signal is in put from the address decoder  11 , relief information about a fuse box which does not use any LT nullifying circuit is reflected on the relief operation of the switching circuit. Here, the node N 1  is set to a high level “H,” and the node N 2  is set to a low level “L.” Since the node N 1  is in a high level “H,” the switching element  4  is turned on, so that the spare WL is turned on.  
         [0050]    Further, the node N 1  is in a high level “H,” and the switching element  9  is turned on. The switching element  8  is turned off, so that the main WL is turned off.  
         [0051]    In the present embodiment, laser trimming is effected while the LT nullifying circuits are connected in parallel with each other. Further, LT information about a fuse box which does not use any LT nullifying circuit is reflected in the relief operation of the switching circuit, thus further contributing to an improvement in product yield and productivity.  
         [0052]    Through the foregoing embodiments, an explanation has been given of a case where the present invention is applied to a semiconductor memory device. However, the present invention is not limited to these embodiments and can be applied to other types of semiconductor devices in the same manner. Thus, there are yielded the same advantages as those yielded in the previous embodiments.  
         [0053]    Obviously many modifications and variations of the present invention are possible in the light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may by practiced otherwise than as specifically described.  
         [0054]    The entire disclosure of a Japanese Patent Application No.2001-015000, filed on Jan. 23, 2001 including specifications, claims drawings and summary, on which the Convention priority of the present application is based, are incorporated herein by reference in its entirety.