Abstract:
A method for generating a channel stream. The method generally comprises the steps of (A) transforming a plurality of data streams, wherein every data stream entering the channel stream experiences a unique transformation and (B) serializing the data streams as transformed into the channel stream.

Description:
FIELD OF THE INVENTION 
   The present invention relates to a method and/or architecture for data stream multiplexing and demultiplexing generally and, more particularly, to data transport for bit-interleaved streams supporting lane identification with invalid streams. 
   BACKGROUND OF THE INVENTION 
   The telecommunications industry uses serial data transmission to move large amounts of data from one point to another. Both conventional Plesiochronous Digital Hierarchy (PDH) (i.e., T1/E1, T3/E3, etc.) and conventional Synchronous Optical Network/Synchronous Digital Hierarchy (SONET/SDH) systems multiplex or aggregate multiple source streams together to allow a single serial stream to carry multiple lower speed sources. The conventional systems multiplex the source streams based upon character boundaries that force additional latency into the system to allow the channels to be interleaved. 
   Recent backplane designs for transporting the source data streams are using bit interleaving to reduce the latency, and lower the hardware overhead needed to handle the multiplexing and demultiplexing functions. Each source data stream is accepted as a serial stream, and the bits of each source data stream are sequentially bit-wise interleaved or aggregated to generate a single faster bit stream. Multiplexing ‘n’ source data streams together produces a serial data stream that is n-times faster than each of the source data streams. 
   Where the aggregation function is desired but a logic overhead and delay of full framers are not available or wanted, the aggregation function can still occur by doing a bit-level or byte-level multiplexing of the individual source data streams. Since there are generally no distinguishing characteristics within the data itself to identify which source data stream is which, and the fact that more than one of the source data streams can theoretically be carrying the same data, there needs to be some way to distinguish each of the source data streams for separation at the receiver. Furthermore, there needs to be some way to resolve the received source data stream into particular lanes. When the single higher-speed serial data stream arrives at the destination, the ‘n’ source data streams need to be separated. Standard clock recovery, data recovery, and demultiplex functions can provide the separation, but the extracted (de-interleaved) serial data streams have no default orientation as to which source data stream should come out on a specific output bit-stream or lane. 
   Referring to  FIG. 1 , a block diagram of a conventional data stream interleaving and de-interleaving system  10  is shown. The system  10  inverts  12  a master source data stream (i.e., J) among several source data streams (i.e., J–M) in a transmitter  14  prior to a serializer  16 . The serializer  16  interleaves the source data streams J–M into a channel stream (i.e., T) that is transmitted through a channel  18 . The inversion  12  is effectively a lossless and reversible form of data manipulation that allows the master source data stream J to be identified from the other source data streams K–M at a receiver  20 . 
   At the receiver  20 , the channel stream T is separated into multiple destination streams (i.e., P–S) using a deserializer  22 . The destination streams P–S are passed to a barrel shifter  23  to allow each of the possible destination streams P–S to be allocated to one of several lanes  24   a–d . The particular destination stream P–S routed through the lane  24   a  is then inverted  26  to produce an inverted stream (e.g., W). The inverted stream W is tested for characteristics of the master source data stream J. Testing involves scanning  28  the inverted stream W for a specific frame construct that may be present. If the frame construct is not found, the barrel shifter  23  is ordered to rotate  30  to route a next destination stream P–S through the inverter  26 . Scanning  28  and rotation  30  are continued until the specific frame construct is found in the inverted stream W. In practice, the non-inverted source data streams K–N should not generate a match condition when inverted  26 . However, the inverted master source data stream J (after the secondary inversion  26 ) will allow proper detection of the frame construct. 
   The system  10  works while the four source data streams J–M are always present. However, SONET/SDH equipment does not provide for each source data stream J–M to originate from the same card, nor to be active all at the same time. Therefore, it is possible for one or more of the source data streams J–M to be missing or void of valid information. If a channel generating the master source data stream J ever goes away, the receiver  20  has no way of identifying the proper destination of the resulting destination data streams P–S. Therefore, allocating the destination streams P–S among the proper lanes  24   a–d  becomes impractical. 
   SUMMARY OF THE INVENTION 
   The present invention concerns a method for generating a channel stream. The method generally comprises the steps of (A) transforming a plurality of data streams, wherein every data stream entering the channel stream experiences a unique transformation and (B) serializing the data streams as transformed into the channel stream. 
   The objects, features and advantages of the present invention include providing a method and/or architecture for data transport of bit-interleaved streams supporting lane identification that may (i) operate with non-standard or invalid source channels, (ii) uniquely identify data streams containing similar or the same data at a receive end, (iii) detect when some and/or all of the data streams may be invalid/non-standard, and/or (iv) add no overhead to the transmitted data. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
       FIG. 1  is a block diagram of a conventional data stream interleaving system; 
       FIG. 2  is a block diagram of an example implementation of a transmitter circuit incorporating a preferred embodiment of the present invention; 
       FIG. 3  is a block diagram of an example implementation of a receiver circuit; 
       FIG. 4  is a flow diagram of a method for generating a channel stream; 
       FIG. 5  is a flow diagram of a method for adding a valid data stream to a channel stream; 
       FIG. 6  is a flow diagram of a method for recovering data streams at a receiver circuit; 
       FIG. 7  is a flow diagram of a method for detecting a reference pattern in a receiver circuit; 
       FIG. 8  is a block diagram of an example implementation of a multi-bit transformation circuit; 
       FIG. 9  is a block diagram of a second example implementation of a transformation circuit; and 
       FIG. 10  is a block diagram of a third example implementation of a transformation circuit. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   Referring to  FIG. 2 , a block diagram of an example implementation of a circuit  100  is shown incorporating a preferred embodiment of the present invention. The circuit  100  may be implemented as a transmitter circuit. The transmitter circuit  100  may be configured to interleave multiple signals or source data streams (e.g., J 1 –M 1 ) received at an input  101  into a single signal or stream (e.g., T). The stream T may be referred to as a high-speed stream, a transmission stream, a transport stream, and/or a channel stream. Each source data stream J 1 –M 1  may be simultaneously transformed by a unique transformation, synchronized if appropriate, and then serialized to generate the channel stream T. The transformations may be reversible (e.g., lossless) to permit recovery of the original source data streams J 1 –M 1  at a receiving end. 
   The transmitter circuit  100  generally comprises multiple circuits  102   a–d , multiple register circuits  104   a–d , and a serializer circuit  106 . The transmitter circuit  100  may optionally comprise a scan circuit  108  and a pattern generator circuit  110 . The transmitter circuit  100  may be designed to receive more or less than four source data streams J 1 –M 1  to meet the design criteria of a particular application. Furthermore, the transmitter circuit  100  may be configured to multiplex the source data streams J 1 –M 1  into multiple channel streams T to meet the design criteria of a particular application. The four-to-one multiplexing shown may be considered as an example for illustrative purposes. 
   The circuits  102   a–d  may be configured as transformation circuits. Each transformation circuit  102   a–d  may perform a modification to a respective source data stream J 1 –M 1  to generate transformed data streams (e.g., J 2 –M 2 ). The modifications performed by each transformation circuit  102   a–d  may be unique among the other modifications or transformations. In one embodiment, the modifications may be designed as zero-overhead modifications, meaning that a same amount of data may be generated by the transformation circuits  102   a–d  as received by the transformation circuits  102   a–d . In another embodiment, the modifications may introduce some overhead to the transformed data streams J 2 –M 2 . 
   Each register circuit  104   a–d  may be configured as a single flip-flop in the form of a pipeline register present in each data stream. The register circuits  104   a–d  may be optionally implemented to keep latencies matched for (e.g., synchronize) all four transformed data streams J 2 –M 2  where appropriate. Each register circuit  104   a–d  may be configured to store a unit of a respective transformed data stream J 2 –M 2 . The unit may be defined as a bit, a nibble, a byte, a 9-bit word, a 10-bit word, a 16-bit word, a 32-bit word, a 64-bit word, a frame, or similarly bounded amount of data. More or fewer registers may be added to each stream without effect on the data content or operation of the circuit, with the only impact being latency of data transferred though the circuit  100 . In one embodiment, the storing may be performed in a serial fashion storing a single bit at a time. In another embodiment, the storing may be performed in a sequential fashion where several bits may be stored at a time. Presentation of the stored data may be performed serially, in parallel, or sequentially. The register circuits  104   a–d  may present stored data streams (e.g., J 3 –M 3 ) respectively to the serializer circuit  106 . 
   The serializer circuit  106  may receive each of the stored data streams J 3 –M 3  in register circuits  112   a–d . The register circuits  112   a–d  may receive the stored data streams J 3 –M 3  in the same fashion (serial or parallel) as presented by the register circuits  104   a–d . The register circuits  112   a–d  may be interconnected to generate the channel stream T from the stored data streams J 3 –M 3 . In one embodiment, the channel stream T may be implemented as a single-bit wide serial data stream. In another embodiment, the channel stream T may be implemented as a multi-bit wide data stream, multiple signals, and/or one or more signals having multiple levels and/or phases. 
   The following transformation examples may be based on a single-bit wide source data streams J 1 –M 1 . The transformation circuit  102   a  may be configured to perform an inverting transformation. The transformation circuit  102   a  may comprise an inverter  114  configured to receive the source data stream J 1  and generate the transformed data stream J 2 . The inverting transformation may be defined by equation 1 as follows:
 
 G ( X )=−1  Eq. (1)
 
   The transformation circuit  102   b  may be configured to perform an NRZI encode operation. An XOR gate  116  may receive the source data stream K 1  and a history data stream (e.g., K 4 ) as inputs to generate the transformed data stream K 2 . The transformed data stream K 2  may be captured in a register circuit  128  to generate the history data stream K 4 . Thus, the data stream K 2  may be a non-return to zero invert-on-one (NRZI) modification of the source data stream K 1 . The NRZI transformation may be defined by equation 2 as follows:
 
 G ( X )=X+1  Eq. (2)
 
   The transformation circuit  102   c  may be configured to perform an inverted NRZI encode operation on the source data stream L 1 . Inversion of the source data stream L 1  may be provided by an inverter  118 . The inverter  118  may be connected in series with an XOR gate  120  that also receives a history data stream (e.g., L 4 ). The XOR gate  120  may generate the transformed data stream L 2 . The transformed data stream L 2  may be captured in a register circuit  129  to generate the history data stream L 4 . Therefore, the data stream L 2  may be an NRZI transformation of the inverted source data stream L 1 . The inverted NRZI transformation may be defined by equation 3 as follows:
 
 G ( X )= X− 1  Eq. (3)
 
   The transformation circuit  102   d  may be configured to perform a unity transformation on the source data stream M 1 . The unity transformation may be implemented as a non-inverting amplifier (not shown) or a conductor  122  (shown) conveying the source data stream M 1  to the register circuit  104   d . Therefore, the transformed data stream M 2  may be identical to the source data stream M 1 . The unity transformation may be defined by equation 4 as follows:
 
 G ( X )=1  Eq. (4)
 
   In general, there may be ‘n’ transformation circuits  102   a–d , one for each of the ‘n’ source data streams J 1 –M 1 . In one embodiment, n−1 of the transformations may be implemented with active logic circuitry while a single transformation (e.g., in the transformation circuit  102   d ) may be implemented with passive circuitry or may be absent. Each transformation may be unique from the other transformations. Furthermore, each transformation may be reversible through complementary logic at a receiver ( FIG. 3 ). Each transformation circuit  102   a–d  may be implemented to provide a single step or a multi-step transformation. In the domain of logic, there may be effectively a large number of the logic transforms that may be applied to any given source data stream J 1 –M 1 . The transformations may include, but are not limited to, logic transformations, polynomial transformations, synchronous scrambler transformations, encryption transformations, and the like. The uniqueness and reversibility of the transformations generally allows every source data stream J 1 –M 1  to be distinguished and identified at the receiver when at least one of the source data streams J 1 –M 1  may be valid. 
   The pattern generator circuit  110  may be included in the transmitter circuit  100  for situations where all of the source data streams J 1 –M 1  may be invalid, non-standard, and/or none of the source data streams J 1 –M 1  may contain a predetermined reference pattern expected by the receiver. The pattern generator circuit  110  may be configured to generate a valid source data stream (e.g., N 1 ) having the predetermined reference pattern either continuously or when appropriate. The source data stream N 1  may be inserted into the serializer  106  in place of one of the stored data streams J 3 –M 3 . For example, a multiplexer  124  may be used to replace the (invalid or non-standard) stored data stream M 3  with the source data stream N 1 . Control of the multiplexer  124  may be provided from the pattern generator circuit  110 , the scan circuit  108 , or a host (not shown). In another embodiment, the source data stream N 1  may be inserted in place of one of the source data streams J 1 –M 1  before the transformation circuits  102   a–d.    
   The pattern generator circuit  110  may be directed by the host. Control by the host may be provided through a set of signals (e.g., STATUSa–d). The host may mark each signal STATUSa–d with a valid or invalid/non-standard condition of a respective source data stream J 1 –M 1 . If all of the source data streams J 1 –M 1  are marked invalid/non-standard by the host, the pattern generator circuit  110  may generate and present the valid source data stream N 1 . 
   Control of the multiplexer  124  may be provided from the scan circuit  108  through a signal (e.g., CMD 1 ). The scan circuit  108  may monitor the source data streams J 1 –M 1  for the predetermined reference pattern. If the predetermined reference pattern is found in at least one source data stream J 1 –M 1 , the scan circuit  108  may generate the signal CMD 1  in a valid state. The valid state of the signal CMD 1  may instruct the multiplexer  124  to route the source data stream M 3  to the serializer circuit  106 . If the predetermined reference pattern is not found in any of the source data streams J 1 –M 1 , the scan circuit  108  may generate the signal CMD 1  in an invalid state. The invalid state of the signal CMD 1  may instruct the multiplexer  124  to route the source data stream N 1  in place of the stored data stream M 3  (as shown), one of the source data streams J 1 –M 1 , or one of the other stored data streams J 3 –L 3 . 
   The predetermined reference pattern or other validation signature may be specific to each particular application. For example, in a Synchronized Optical Network/Synchronous Digital Hierarchy (SONET/SDH) application and/or an Optical Transport Network (OTN), a frame construct may be used as the predetermined reference pattern. In one embodiment, the predetermined reference pattern may comprise a sequence of consecutive A1 characters followed by consecutive A2 characters. In another embodiment, the predetermined reference pattern may comprise three consecutive A1 characters followed by three consecutive A2 characters. Other reference patterns may be implemented to meet the design criteria of a particular application. 
   The scan circuit  108  generally scans each of the source data streams J 1 –M 1  continuously. Per SONET/SDH, the A1/A2 characters may be repeated every 125 microseconds (μs). Therefore, the scan circuit  108  may wait for 125 μs, or slightly longer (e.g., ≧1 bit after 125 μs) before determining that the framing pattern construct may be missing from a source data stream J 1 –M 1 . Other scan periods may be implemented to determine if and when the predetermined reference pattern becomes absent. 
   Referring to  FIG. 3 , a block diagram of an example implementation of a circuit  130  is shown. The circuit  130  may be implemented as a receiver circuit. The receiver circuit  130  may be configured to de-interleave and deserialize the channel stream T into multiple received data streams (e.g., P 1 –S 1 ). Each received data stream P 1 –S 1  may be routed to a unique transformation to undo the transformations of the transformation circuits  102   a–d  in the transmitter circuit  100 . While the received data streams P 1 –S 1  may be routed to the correct reverse transformations, the original source data streams J 1 –M 1  may be reproduced at an output  131  of the receiver circuit  130 . 
   The receiver circuit  130  generally comprises a deserializer circuit  132 , a circuit  134 , multiple register circuits  136   a–d , multiple circuits  138   a–d , a scan circuit  140 , and a rotate circuit  142 . The circuit  134  may be implemented as a multiplexer circuit or a barrel shifter circuit. Each register circuit  136   a–d  may be configured as n (where n is an integer) flip-flops in the form of pipeline registers present in each data stream. Each circuit  138   a–d  may be implemented as a transformation circuit. 
   The deserializer circuit  132  may be configured to convert the channel stream T into the received data streams P 1 –S 1 . The deserializer circuit  132  generally comprises multiple register circuits  144   a–d . Each register circuit  144   a–d  may be coupled together to receive the channel stream T in a serial fashion. Reception may match the width of the channel stream T. For example, a single-bit wide channel stream T may be received by the register circuit  144   d  one bit at a time. A multi-bit wide channel stream T may be received several bits at a time. As each new bit or bits are received, the older bits may be shifted serially down through the register circuits  144   a–d . When all of the register circuits  144   a–d  are generally full, the contents of the register circuits  144   a–d  may be presented to the barrel shifter circuit  134  as portions of the received data streams P 1 –S 1 . Each received data stream P 1 –S 1  may be implemented as a single-bit wide or multiple-bit wide signal. 
   The barrel shifter circuit  134  may be operational to route each of the received data streams P 1 –S 1  to one of several lanes  146   a–d  of the receiver circuit  130 . The received data streams P 1 –S 1  may be referred to as shifted data streams W 1 –Z 1  while residing in the lanes  146   a–d . An allocation of the received data streams P 1 –S 1  to the shifted data streams W 1 –Z 1  may be determined by the shifting or multiplexing functionality provided by the barrel shifter circuit  134 . For example, if the received data stream P 1  is routed to the shifted data stream Y 1  in the lane  146   c , the other received data streams Q 1 , R 1 , and S 1  may be routed to the shifted data streams Z 1 , W 1 , and X 1  respectively. 
   The register circuits  136   a–d  may keep latencies matched for all four shifted data streams W 1 –Z 1 . Each register circuit  136   a–d  may be configured to store a unit or portion of the respective shifted date stream W 1 –Z 1 . The unit may be defined to be the same as in the transmitter circuit  100 . In one embodiment, storing may be performed in a serial fashion storing a single bit at a time. In another embodiment, storing may be performed sequentially where several bits are stored at a time. Presentation of the stored data may be performed serially, in parallel, or sequentially. The register circuits  136   a–d  may present stored data streams (e.g., W 2 –Z 2 ) respectively to the transformation circuits  138   a–d.    
   Each transformation circuit  138   a–d  may be designed to perform a transformation unique among the other transformations. Generally, each of the transformation circuits  138   a–d  in the receiver  130  may implement a reverse transformation of a complimentary transformation circuit  102   a–d  in the transmitter circuit  100 . Furthermore, the assignment of the transformation circuits  138   a–d  to the lanes  146   a–d  may match the assignment of the transformation circuits  102   a–d  to the inputs of the serializer circuit  106 . 
   The transformation circuit  138   a  may be configured to perform an inverting transformation. The transformation circuit  138   a  may comprise an inverter  148 . The inverter  148  may be configured to receive the stored data stream W 2  and generate a transformed data stream W 3 . 
   The transformation circuit  138   b  may be configured to perform an NRZI decode operation. An XOR logic gate  150  may receive the stored data stream X 2  and a history data stream (e.g., X 4 ) as inputs to generate a transformed data stream X 3 . The stored data stream X 2  may be captured in a register circuit  158  to generate the history data stream X 4 . Therefore, the stored data stream X 3  may be an NRZI decode transformation of the shifted data stream X 1 . 
   The transformation circuit  138   c  may be configured to perform an inverted NRZI decode operation. An XNOR operation may be provided by an XOR logic gate  152  in series with an inverter  154 . The XOR logic gate  152  may receive the stored data stream Y 2  and a history data stream (e.g., Y 4 ) as inputs. The inverter  154  may invert the output signal generated by the XOR logic gate  152 . The stored data stream Y 2  may be captured in a register circuit  159  to generate the history data stream Y 4 . Therefore, a transformed data stream Y 3  may be an inverted NRZI transformation of the shifted data stream Y 1 . 
   The transformation circuit  138   d  may be configured to perform a unity transformation on the stored data stream Z 2 . The unity transformation may be implemented as a non-inverting amplifier (not shown) or a conductor  156  (shown) conveying the stored data stream Z 2 . Therefore, a transformed data stream Z 3  may be identical to the stored data stream Z 2 . 
   Similar to the transmitter circuit  100 , the receiver circuit  130  may have ‘n’ transformation circuits  136   a–d , one for each of the ‘n’ shifted data streams W 1 –Z 1 . In one embodiment, n−1 of the transformations may be implemented with active logic circuitry while a single transformation (e.g., provided by the transformation circuit  138   d ) may be implemented with passive circuitry or may be absent. Each transformation may be unique among the other transformations. Each transformation may also be a reverse of the respective transformation logic in the transmitter circuit  100 . Each transformation circuit  138   a–d  may be implemented to provide a single step or a multi-step transformation. In the domain of logic, there may be effectively a large number of the logic transforms that may be applied to any given shifted data stream W 1 –Z 1 . The transformations may include, but are not limited to logic transformations, polynomial transformations, synchronous de-scrambler transformations, decryption transformations, and the like. The uniqueness and reversibility of the transformations generally allows every shifted data stream W 1 –Z 1  to be distinguished at the receiver circuit  130  while at least one of the shifted data streams W 1 –Z 1  may be valid. 
   The scan circuit  140  may receive one or more of the transformed date streams W 3 –Z 3 . The scan circuit  140  may generate a signal (e.g., CMD 2 ). The scan circuit  140  may also generate multiple status signals (e.g., VALIDa–d), one for each lane  146   a–d.    
   The scan circuit  140  may search each received transformed data stream W 3 –Z 3  for the predetermined reference pattern. In the embodiment where the predetermined reference pattern may be the frame construct of a SONET/SDH data stream, the scan circuit  140  may scan each transformed data stream W 3 –Z 3  for at least slightly longer (e.g., ≧1 bit) than the 125 μs frame rate. If a valid predetermined reference pattern may be absent in all of the scanned transformed data streams W 3 –Z 3  after a set period or number of bits have been scanned, the scan circuit  140  may generate the signal CMD 2  in the invalid state. The invalid state of the signal CMD 2  may instruct the rotate circuit  142  to command a rotation of the barrel shifter circuit  134 . The rotate circuit  142  may generate a signal (e.g., CMD 3 ) to instruct the barrel shifter circuit  134  to reroute or shift the received data streams P 1 –S 1  by one or more lanes  146   a–d . For example, the received data stream P 1  may be rerouted from the lane  146   b  to the lane  146   c . Thereafter, the shifted data stream Y 1  may match the received data stream P 1 . Scanning and rotating may be continued until the predetermined reference pattern is generally detected in at least one of the transformed data streams W 3 –Z 3 . When the scan circuit  140  detects the predetermined reference pattern in at least one of the transformed data streams W 3 –Z 3 , the scan circuit  140  may generate the signal CMD 2  in the valid state. The signal CMD 2  in the valid state may instruct the rotate circuit  142  to hold the signal CMD 3  at a current value. 
   An advantage of the present invention as compared to the conventional system  10  may be that the receiver circuit  130  may not rely on a presence of a valid single master source data stream. If any one or more of the transformed data streams W 3 –Z 3  contains the reference pattern, the receiver circuit  130  may identify the correct alignment of the received data streams J 1 –S 1  to the lanes  146   a–d . Therefore, the transmitter circuit  100  and receiver circuit  130  may remain synchronized with each other while one or several of the source data streams J 1 –M 1  may be absent, invalid, non-standard, and/or lack the reference pattern. 
   For each lane  146   a–d  monitored, the scan circuit  140  may generate a respective signal VALIDa–d. The scan circuit  140  may generate the respective signal VALIDa–d in the invalid state where the scan circuit  140  fails to find the predetermined reference pattern in the associated transformed data stream W 3 –Z 3 . The scan circuit  140  may generate the respective signal VALIDa–d in the valid state where the predetermined reference pattern may be detected in the associated transformed data stream W 3 –Z 3 . The signals VALIDa–d may be used at the receiver end to indicate status of the received data streams P 1 –S 1 . 
   The barrel shifter circuit  134  may be useful in the receiver circuit  130  since the deserializer circuit  132  may have no knowledge of how the individual transformed data streams J 3 –M 3  are interleaved into the channel stream T. By stepping through each possible allocation of the received data streams P 1 –S 1  through the various transformation circuits  138   a–d , a correct match or shifting between the received data streams P 1 –S 1  and the shifted data streams W 1 –Z 1  may be determined by the scan circuit  140 . 
   While the barrel shifter circuit  134  does not provide the correct match, the various transformation circuits  138   a–d  generally may not properly reverse the transformations performed in the transmitter circuit  100 . In contrast, while the barrel shifter circuit  134  provides the correct routing of the received data streams P 1 –S 1  to the shifted data streams W 1 –Z 1 , the transformation circuits  138   a–d  may reverse the transformations performed on the source data streams J 1 –M 1  in the transmitter circuit  100 . Each transformed data stream W 3 –Z 3  may then represent an accurate reproduction of a respective source data stream J 1 –M 1 . Therefore, for each source data stream J 1 –M 1  incorporating the predetermined reference pattern generally results in the predetermined reference pattern appearing in the associated transformed data stream W 3 –Z 3 . The scan circuit  140  may detect the predetermined reference patterns and maintain the present condition of the barrel shifter circuit  134 . As a result, even if only one transformed data stream W 3 –Z 3  has the predetermined reference pattern, then all of the transformed data streams W 3 –Z 3  may be allocated to the proper lanes  146   a–d , and undergo the correct reverse transformation. Therefore, each transformed data stream W 3 –Z 3  may be identifiable with the source data streams J 1 –M 1  based upon the final lane allocation. The identification may be useful where two or more of the source data streams J 1 –M 1  carry similar, nearly identical, or even identical information that may make distinguishing the data streams difficult. 
   Referring to  FIG. 4 , a flow diagram of a method for generating the channel stream T is shown. The method generally begins with reception of the one or more source data streams from the host (e.g., block  160 ). The transmitter circuit  100  then performs a unique transformation on each of the data streams (e.g., block  162 ). After experiencing the transformations, the data streams may be buffered or stored, if appropriate, to equalize the latency for all of the data streams (e.g., block  164 ). After storage, the data streams may be serialized to interleave the individual data streams to generate the channel stream T (e.g., block  166 ). Finally, the channel stream T may be transmitted to the receiver circuit  130  (e.g., block  168 ). 
   Referring to  FIG. 5 , a flow diagram of a method for adding a valid data stream to the channel stream T is shown. The method may begin either by scanning the source data streams for the reference pattern (e.g., block  170 ) or by the host marking all of the source data streams as invalid/non-standard (e.g., block  172 ). If scanning of the source data streams identifies at least one valid data stream (e.g., the YES branch of decision block  174 ), the multiplexer  124  may address or route the source data stream (e.g., block  176 ). Continuously, or while all of the data streams are generally invalid/non-standard (e.g., the NO branch of decision block  174 ), as determined by the scan circuit  108  and/or the host, the pattern generator circuit  110  may generate a valid data stream (e.g., block  178 ). The valid data stream may then be inserted in place of one or more of the data streams (e.g., block  180 ). 
   Referring to  FIG. 6 , a flow diagram of a method for recovering the data streams at the receiver circuit  130  is shown. The method may begin upon receipt of a portion of the channel stream T sufficient for the deserializer circuit  132  to operate (e.g., block  182 ). The deserializer circuit  132  may then deserialize and de-interleave the channel stream T into multiple data streams (e.g., block  184 ). The barrel shifter circuit  134  may route the individual data streams among the lanes (e.g., block  186 ). The data streams may then be stored or buffered in each lane (e.g., block  188 ). Unique reverse transformations may be applied to each data stream (e.g., block  190 ). Finally, the transformed data streams may be presented by the receiver circuit  130  to other circuitry (e.g., block  192 ). 
   Referring to  FIG. 7 , a flow diagram of a method for detecting the reference pattern in the receiver circuit  130  is shown. Detection may include scanning one, several, or all of the data streams after shifting, buffering, and transforming (e.g., block  194 ). A status signal may be generated for each lane to indicate if the data stream in the lane may be valid or not (e.g., block  196 ). If at least one valid reference pattern has been detected (e.g., the YES branch of decision block  197 ), shifting may be halted at a current position and scanning continued in case the reference pattern or patterns disappear. If no valid streams have been detected (e.g., the NO branch of decision block  197 ), a duration may be checked. If an entire frame has not been scanned (e.g., the NO branch of decision block  198 ), scanning may continue (e.g., block  194 ). If an entire frame has been scanned without detecting at least one reference pattern (e.g., the YES branch of decision block  198 ), the scan circuit  140  may instruct the rotate circuit  142  to command the barrel shifter circuit  134  to shift the data streams (e.g., block  200 ). Scanning and shifting may continue until all possible shift combinations between the received data signals and the lanes have been tested. If no valid data streams are detected, the barrel shifter circuit  134  may rotate back to an initial configuration and scanning may continue. 
   Referring to  FIG. 8 , a block diagram of an example implementation of a multi-bit transformation circuit  202  is shown. The transformation circuit  202  may be implemented in the transmitter circuit  100  and/or in the receiver circuit  130 . The transformation circuit  202  generally comprises a circuit  204  in series between a serial-to-parallel converter circuit  206  and a parallel-to-serial converter circuit  208 . By way of example, a single-bit wide signal or data stream (e.g., C) may be received by the serial-to-parallel converter circuit  206 . The serial-to-parallel converter circuit  206  may store a unit comprising ‘n’ bits of the data stream C. The resulting n-bit wide data stream (e.g., D) may be transferred to the circuit  204 . The circuit  204  may transform the n-bit data stream D into an m-bit signal (e.g., E). The transformation may be performed on the entire unit all at once. The resulting m-bit data stream E may be presented to the parallel-to-serial conversion circuit  208 . The parallel-to-serial conversion circuit  208  may convert the data stream E back into a single-bit data stream (e.g., F). 
   A value of ‘m’ may be equal to or greater than a value of ‘n’ in the transmitter circuit  100 . The value of ‘m’ may be less than or equal to the value of ‘n’ in the receiver circuit  130 . The transformation may be a reversible block conversion using a lookup table and/or an appropriate mapping. A potential use of an n-bit to m-bit block conversion may be to change long sequences of all logical ones or all logical zeros into patterns having some logical ones and some logical zeros (e.g., reduce a DC component of a signal). Examples of reversible block conversions may be 8B/10B and 10B/8B block conversions. In another example, the block conversion may be implemented as an encryption in the transmitter circuit  100  and as a decryption in the receiver circuit  130 . Other block conversions may be implemented to meet the design criteria of a particular application. 
   Referring to  FIG. 9 , a block diagram of a second example implementation of a transformation circuit  210  is shown. The transformation circuit  210  may be suitable for implementation in the transmitter circuit  100 . The transformation circuit  210  generally comprises multiple registers  212   a–d  and multiple adders  214   a–b.    
   The registers  212   a–d  may be configured as a serial shift register with the first register  212   a  receiving a signal (e.g., C 4 ). A first modulo-two adder  214   a  may sum the signal C 4  with an output signal (e.g., C 1 ) from the third register  212   c  to generate a signal (e.g., S). A second modulo-two adder  214   b  may sum the output signal (e.g., C 0 ) of the fourth register  212   d  and the signal S to generate a transformed signal (e.g., F). The transformation G(X) provided by the circuit  210  may define a polynomial as shown in equation 5 as follows:
 
 G ( X )=1 +X+X   4   Eq. (5)
 
   Referring to  FIG. 10 , a block diagram of a third example implementation of a transformation circuit  216  is shown. The transformation circuit  216  may be suitable for implementation in the receiver circuit  130 . The transformation circuit  216  may provide a reverse transformation of the transformation circuit  210 . 
   The transformation circuit  216  generally comprises multiple registers  218   a–d  and multiple adders  220   a–b . The registers  218   a–d  may be configured to form a serial shift register. The first modulo-two adder  220   a  may sum the signal F (generated by the transformation circuit  210 ) with an output signal (e.g., V) from the second adder  220   b . The second modulo-two adder  220   b  may sum an output signal (e.g., H 1 ) generated by the third register  218   c  and an output signal (e.g., H 0 ) generated by the fourth registers  218   d  to generate the output signal V. The sum generated by the first modulo-two adder  220   a  (e.g., H 4 ) may be provided to the first register  218   a  and may also reproduce the original signal C 4 . 
   Referring to  FIGS. 2 and 3 , an example implementation of the transmitter circuit  100  may be to aggregate four OC12 bit streams that may be transported across an equivalent of an OC48 serial link. The channel stream T may be segregated back into four OC12 bit streams by the receiver circuit  130 . By appropriate setting of the barrel shifter circuit  134 , an allocation of the received OC12 bit streams may be directed to the proper lanes  146   a–d . Therefore, each unique transformation performed in the transmitter circuit  100  may be completely reversed by the matching transformation in the receiver circuit  130 . 
   More or fewer data streams may be multiplexed together by changing a size of the serialization/deserialization (SERDES) functions provided by the serializer circuit  106  and the deserializer circuit  132 . Furthermore, the logic transform functions may be moved to any data stream in any order. For example, the unity transformation may be associated with the second source data stream K 1  in the transmitter circuit  100  and the second shifted data stream X 1  in the receiver circuit  130 . In another embodiment, all of the data streams (instead of just n−1 data streams) may undergo non-unity transformations. 
   Interfaces to the serializer circuit  106  and the deserializer circuit  132  may be some multiple (other than 1) of a number of bit streams merged together. For example, the SERDES interfaces may be 8-bits wide and still accept and deliver four single-bit data streams. The multiple may also be configured as a non-integer by implementing gearbox logic to transform from a first width domain to a second width domain. Other designs may be implemented to meet the design criteria of a particular application. 
   The various signals of the present invention are generally “on” (e.g., a digital HIGH, valid, or 1) or “off” (e.g., a digital LOW, invalid, or 0). However, the particular polarities of the on (e.g., asserted) and off (e.g., de-asserted) states of the signals may be adjusted (e.g., reversed) accordingly to meet the design criteria of a particular implementation. Additionally, inverters may be added to change a particular polarity of the signals. As used herein, the term “simultaneously” is meant to describe events that share some common time period but the term is not meant to be limited to events that begin at the same point in time, end at the same point in time, or have the same duration. 
   While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.