Abstract:
A field-effect transistor (FET) with a round-shaped nano-wire channel and a method of manufacturing the FET are provided. According to the method, source and drain regions are formed on a semiconductor substrate. A plurality of preliminary channel regions is coupled between the source and drain regions. The preliminary channel regions are etched, and the etched preliminary channel regions are annealed to form FET channel regions, the FET channel regions having a substantially circular cross-sectional shape.

Description:
RELATED APPLICATION 
       [0001]    This application is a divisional application of the U.S. patent application Ser. No. 11/303,408, filed on Dec. 16, 2005, which claims the benefit of Korean patent application number 10-2005-0024543, filed on Mar. 24, 2005, in the Korean Intellectual Property Office, the contents of which applications are incorporated herein in their entirety by reference. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The invention relates to field-effect transistors (FETs) on semiconductor substrates and manufacturing methods thereof, and, more particularly, to a FET having a round-shaped, i.e., circular, nano-wire channel and a fabricating method thereof. 
       DESCRIPTION OF THE RELATED ART 
       [0003]    As applications for semiconductor devices expand, highly-integrated and/or high-speed semiconductor devices are increasingly in demand. As integration density of semiconductor devices increases, a design rule becomes smaller. As a result of the decreasing design rule, a channel length and a channel width of a field effect transistor (FET) similarly decrease. A decrease in channel length may result in a short channel effect. A decrease in channel width may result in a narrow channel effect. The short channel effect may significantly influence potential in a source/drain region upon a channel region. The narrow channel width effect may generally increase a threshold voltage. However, in the case of a device using a STI (Shallow Trench Isolation), a channel width that is too narrow may decrease a threshold voltage. This is referred to as an inverse narrow width effect. In an attempt to prevent generation of the short channel effect and/or the narrow channel effect, various FETs having new structures have been proposed. 
         [0004]    Recently, efforts have been made, particularly in the area of nano-size technology in the semiconductor field, to increase drive current of a transistor and decrease the short channel effect. Conventionally, several methods have been used in an effort to achieve these results. Examples of these attempts include a recessed channel array transistor (RCAT), a fin-type FET (FinFET), and gate-all-around transistor (GAT) technologies. 
         [0005]    Each of these conventional devices and the corresponding methods of fabricating these devices, suffer from one of more disadvantages. For example, these conventional devices are limited in an ability to perform fast operations. Moreover, the number of spaced channel layers in these conventional devices is limited due to fabrication limitations, e.g., with respect to an etching depth that can be achieved during dry etching. 
       SUMMARY OF THE INVENTION 
       [0006]    The present invention is therefore directed to a FET having one or more nano-wire channels and a method of manufacturing the FET, which substantially overcome one or more of the drawbacks due to the limitations and disadvantages of the prior art. 
         [0007]    According to a first aspect, the invention is directed to a method of fabricating a field effect transistor (FET). According to the method, source and drain regions are formed on a semiconductor substrate. A plurality of preliminary channel regions are formed coupled between the source and drain regions. The preliminary channel regions are etched, and the etched preliminary channel regions are annealed to form FET channel regions, the FET channel regions having a substantially circular cross-sectional shape. 
         [0008]    In one embodiment, the preliminary channel regions have a substantially rectangular cross-sectional shape. In one embodiment, the preliminary channel regions have corners in cross-section. 
         [0009]    In one embodiment, the etching is performed in an atmosphere containing one or both of HCl and H 2 . In one embodiment, a ratio of a flow rate of HCl to a flow rate of H 2  is from 3:7 to 1:1. In one particular embodiment, the ratio of flow rate of HCl to flow rate of H 2  is 3:5. 
         [0010]    In one embodiment, the etching is performed at a temperature of 600 to 900 degrees C. The etching can be performed for a period of 1 to 120 seconds. The etching can be performed at a pressure of 10 to 100 Torr. 
         [0011]    In one embodiment, the annealing is performed in an atmosphere containing H 2 . The annealing can be performed with H 2  introduced at a flow rate of 1 to 500 seem. The annealing can be performed at a temperature of 600 to 900 degrees C., and, more particularly, at a temperature of 810 degrees C. The annealing can be performed for a period of 10 to 800 seconds, and, more particularly, for a period of 500 seconds. 
         [0012]    In one embodiment, the method further comprises, after forming the preliminary channel regions, cleaning the structure to remove oxide from the structure. The cleaning can be performed in an atmosphere containing at least one of H 2 , Ar and He. The cleaning can be performed at a temperature of 600 to 900 degrees C. The cleaning can be performed at a gas flow rate of 1 to 500 sccm. The cleaning can be performed for a period of 1 to 5 minutes. The cleaning can be performed at a pressure of 0.1 to 10 Torr. In one embodiment, forming the plurality of preliminary channel regions comprises forming a channel layer and a sacrificial layer vertically adjacent to the channel layer. In one embodiment, the channel layer and the sacrificial layer are formed epitaxially. In one embodiment, the channel layer is a silicon layer. In one embodiment, the sacrificial layer is a SiGe layer. 
         [0013]    In one embodiment, forming the plurality of preliminary channel regions further comprises trimming the channel layer to a desired dimension such that a front surface of at least one of the preliminary channel regions is offset with respect to a front surface of the source and drain regions in a direction normal to the front surface of the source and drain regions. The trimming can included etching the channel layer. Etching the channel layer can include a chemical dry etch. 
         [0014]    In one embodiment, forming the plurality of preliminary channel regions further comprises forming a mask layer over the channel layer and sacrificial layer, the mask layer defining a region separating the FET channel regions. 
         [0015]    In one embodiment, forming the plurality of preliminary channel regions comprises forming a plurality of sacrificial layers vertically adjacent to a channel layer. The sacrificial layers can comprise SiGe. An upper sacrificial layer can have a lower concentration of germanium than a lower sacrificial layer. 
         [0016]    In one embodiment, the method further comprises purging a process chamber between etching the preliminary channel regions and annealing the etched preliminary channel regions. 
         [0017]    In one embodiment, the etching and annealing steps are performed at least two times. In one embodiment, the method further comprises purging steps between a prior etching step and a next annealing step. 
         [0018]    In one embodiment, the method further comprises forming a gate dielectric layer on the FET channel regions. 
         [0019]    In one embodiment, the method further comprises forming a gate surrounding the FET channel regions. the gate can include polysilicon. Also, the gate comprises metal. 
         [0020]    According to another aspect, the invention is directed to a method of fabricating a field effect transistor (FET). According to the method, at least one channel layer and at least one sacrificial layer are alternately stacked on a substrate. Source and drain regions are formed on the substrate coupled to the alternately stacked at least one channel layer and at least one sacrificial layer. The alternately stacked at least one channel layer and at least one sacrificial layer are patterned to form a plurality of preliminary channel regions coupled between the source and drain regions. A remaining portion of the at least one sacrificial layer is removed. The preliminary channel regions are etched, the etched preliminary channel regions are annealed to form FET channel regions, the FET channel regions having a substantially circular cross-sectional shape. 
         [0021]    In one embodiment, the preliminary channel regions have a substantially rectangular cross-sectional shape. In one embodiment, the preliminary channel regions have corners in cross-section. 
         [0022]    In one embodiment, the at least one channel layer and the at least one sacrificial layer are formed epitaxially. 
         [0023]    In one embodiment, the at least one channel layer is a silicon layer. In one embodiment, the at least one sacrificial layer is a SiGe layer. 
         [0024]    In one embodiment, forming the plurality of preliminary channel regions further comprises trimming the at least one channel layer to a desired dimension such that a front surface of at least one of the preliminary channel regions is offset with respect to a front surface of the source and drain regions in a direction normal to the front surface of the source and drain regions. In one embodiment, the trimming comprises etching the at least one channel layer. Etching the at least one channel layer can include a chemical dry etch. 
         [0025]    In one embodiment, forming the plurality of preliminary channel regions further comprises forming a mask layer over the at least one channel layer and at least one sacrificial layer, the mask layer defining a region separating the FET channel regions. 
         [0026]    In one embodiment, forming the plurality of preliminary channel regions comprise forming a plurality of sacrificial layers vertically adjacent to the channel layer. 
         [0027]    The sacrificial layers can comprise SiGe. In one embodiment, an upper sacrificial layer has a lower concentration of germanium than a lower sacrificial layer. 
         [0028]    In one embodiment, the method further comprises purging a process chamber between etching the preliminary channel regions and annealing the etched preliminary channel regions. 
         [0029]    In one embodiment, the method further comprises forming a gate dielectric layer on the FET channel regions. 
         [0030]    In one embodiment, the method further comprises forming a gate surrounding the FET channel regions. The gate can include polysilicon. Also, the gate can include metal. 
         [0031]    According to another aspect, the invention is directed to a method of fabricating a field effect transistor (FET). According to the method, source and drain regions are formed on a semiconductor substrate. A plurality of preliminary channel regions are formed coupled between the source and drain regions. Forming the plurality of preliminary channel regions comprises: (i) forming a channel layer and a sacrificial layer vertically adjacent to the channel layer, and (ii) trimming the channel layer to a desired dimension such that a front surface of at least one of the preliminary channel regions is offset with respect to a front surface of the source and drain regions in a direction normal to the front surface of the source and drain regions. The preliminary channel regions are etched, and the etched preliminary channel regions are annealed to form FET channel regions, the FET channel regions having a substantially circular cross-sectional shape. 
         [0032]    In one embodiment, the preliminary channel regions have a substantially rectangular cross-sectional shape. In one embodiment, the preliminary channel regions have corners in cross-section. 
         [0033]    In one embodiment, the method further comprises, after forming the preliminary channel regions, cleaning the structure to remove oxide from the structure. 
         [0034]    In one embodiment, the channel layer and the sacrificial layer are formed epitaxially. 
         [0035]    The channel layer can be a silicon layer, and the sacrificial layer can be a SiGe layer. 
         [0036]    In one embodiment, the trimming comprises etching the channel layer. Etching the channel layer can include a chemical dry etch. 
         [0037]    In one embodiment, forming the plurality of preliminary channel regions comprises forming a plurality of sacrificial layers vertically adjacent to the channel layer. The sacrificial layers can include SiGe. An upper sacrificial layer can have a lower concentration of germanium than a lower sacrificial layer. 
         [0038]    In one embodiment, the method further comprises purging a process chamber between etching the preliminary channel regions and annealing the etched preliminary channel regions. 
         [0039]    In one embodiment, the method further comprises forming a gate dielectric layer on the FET channel regions. 
         [0040]    In one embodiment, the method further comprises forming a gate surrounding the FET channel regions. In one embodiment, the gate comprises polysilicon. In one embodiment, the gate comprises metal. 
         [0041]    According to another aspect, the invention is directed to a method of fabricating a field effect transistor (FET). According to the method, source and drain regions are formed on a semiconductor substrate. A preliminary channel region is formed coupled between the source and drain regions, forming the preliminary channel region comprising: (i) forming a channel layer and a sacrificial layer vertically adjacent to the channel layer, and (ii) trimming the channel layer to a desired dimension such that a front surface of the preliminary channel region is offset with respect to a front surface of the source and drain regions in a direction normal to the front surface of the source and drain regions. A remaining portion of the sacrificial layer is removed. The trimmed channel layer is etched, and the etched channel layer is annealed to form a FET channel region, the FET channel region having a substantially circular cross-sectional shape. 
         [0042]    According to another aspect, the invention is directed to a method of fabricating a field effect transistor (FET). According to the method, source and drain regions are formed on a semiconductor substrate. A preliminary channel region is formed coupled between the source and drain regions, forming the preliminary channel region comprising forming a channel layer and a sacrificial layer vertically adjacent to the channel layer. A remaining portion of the sacrificial layer is removed. The preliminary channel region is etched, and the etched preliminary channel region is annealed to form a FET channel region, the FET channel region having a substantially circular cross-sectional shape. 
         [0043]    According to another aspect, the invention is directed to a method of fabricating a field effect transistor (FET). According to the method, source and drain regions are fainted on a semiconductor substrate. A plurality of preliminary channel regions are formed coupled between the source and drain regions. The preliminary channel regions are etched, and the etched preliminary channel regions are annealed to form FET channel regions, the FET channel regions having a substantially circular cross-sectional shape. 
         [0044]    According to another aspect, the invention is directed to a field effect transistor (FET) having a semiconductor substrate and source and drain regions on the semiconductor substrate. A plurality of FET channel regions are coupled between the source and drain regions, the FET channel regions having a substantially circular cross-sectional shape, the FET channel regions being trimmed to a desired dimension such that a front surface of at least one of the FET channel regions is offset with respect to a front surface of the source and drain regions in a direction normal to the front surface of the source and drain regions. 
         [0045]    In one embodiment, the FET further comprises a gate dielectric layer on the FET channel regions. 
         [0046]    In one embodiment, the FET further comprises a gate surrounding the FET channel regions. 
         [0047]    In one embodiment, the FET further comprises the gate comprises polysilicon. In one embodiment, the FET further comprises the gate comprises metal. 
         [0048]    According to another aspect, the invention is directed to a field effect transistor (FET) comprising a semiconductor substrate and source and drain regions on the semiconductor substrate. A FET channel region is coupled between the source and drain regions, the FET channel region having a substantially circular cross-sectional shape, the FET channel region being trimmed to a desired dimension such that a front surface of the FET channel region is offset with respect to a front surface of the source and drain regions in a direction normal to the front surface of the source and drain regions. 
         [0049]    According to the invention, a round-shaped (circular) nano-wire channel is produced in a FET using an etching process and an annealing process using H 2 . This process of manufacturing the FET reduces an electric field concentration phenomenon that occurs at the corner of a conventional FET having a square-shaped nano-wire channel. In producing the round-shaped nano-wire channel, the H2 annealing is done at relatively low temperature. Annealing at high temperature results in a nano-wire whose shape can result in the FET channel being cut or interrupted due to a silicon migration effect. Also, an uppermost silicon germanium layer used as a sacrificial layer can have a higher percentage of germanium than the other layers. This results in preventing the uppermost silicon channel layer from being consumed during etching. A damascene process can be used to form a self-aligned transistor gate. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0050]    The foregoing and other features and advantages of the invention will be apparent from the more particular description of preferred aspects of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. In the drawings, the thickness of layers and regions are exaggerated for clarity. 
           [0051]      FIG. 1  is a schematic top plan view of a FET with a round or circular shaped nano-wire channel in accordance with an embodiment of the invention. 
           [0052]      FIG. 2A  is a schematic cross-sectional view of one embodiment of the FET of  FIG. 1 , taken along line A-A′ of  FIG. 1 . 
           [0053]      FIG. 2B  is a schematic cross-sectional view of the embodiment of the FET of  FIG. 2A  taken along line B-B′ of  FIG. 1 . 
           [0054]      FIG. 3  is a schematic cross-sectional view of another embodiment of the FET of  FIG. 1 , corresponding to line A-A′ of  FIG. 1 . 
           [0055]      FIG. 4A  is a schematic cross-sectional view of another embodiment of the FET in accordance with the invention corresponding to the line A-A′ of  FIG. 1 . 
           [0056]      FIG. 4B  is a schematic cross-sectional view of the embodiment of the FET of  FIG. 4A  corresponding to the line B-B′ of  FIG. 1 . 
           [0057]      FIG. 5  is a schematic cross-sectional view of another embodiment of the FET of  FIG. 1 , corresponding to line A-A′ of  FIG. 1 . 
           [0058]      FIG. 6A  is a schematic cross-sectional view of another embodiment of a FET in accordance with the invention corresponding to the line A-A′ of  FIG. 1 . 
           [0059]      FIG. 6B  is a schematic cross-sectional view of the FET of  FIG. 6A  corresponding to the line B-B′ of  FIG. 1 . 
           [0060]      FIG. 7  is a schematic cross-sectional view of another embodiment of the FET of  FIG. 1 , corresponding to line A-A′ of  FIG. 1 . 
           [0061]      FIG. 8  is a logical flow diagram illustrating the process of forming the round-shaped nano-wire channels and gate of the FET according to the invention. 
           [0062]      FIGS. 9A through 9D  are schematic perspective views illustrating the steps in the process of forming the nano-wire channels and gate of the invention. 
           [0063]      FIG. 10  is a detailed flow diagram illustrating the process of forming a round nano-wire channel from a square nano-wire channel, according to an embodiment of the invention. 
           [0064]      FIGS. 11A through 11M  are schematic perspective views illustrating steps in a process of manufacturing the FET of the invention, in accordance with an embodiment of the invention. 
           [0065]      FIGS. 12A through 12K  are views illustrating steps in a process of manufacturing the FET of the invention, in accordance with another embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0066]    In the following detailed description, when a layer is described as being formed on another layer or on a substrate, the layer may be formed on the other layer or on the substrate, or a third layer may be interposed between the layer and the other layer or the substrate. 
         [0067]      FIG. 1  is a schematic top plan view of a FET with a round or circular shaped nano-wire channel in accordance with an embodiment of the invention.  FIG. 2A  is a schematic cross-sectional view of one embodiment of the FET of  FIG. 1 , taken along line A-A′ of  FIG. 1 .  FIG. 2B  is a schematic cross-sectional view of the embodiment of the FET of  FIG. 2A  taken along line B-B′ of  FIG. 1 . 
         [0068]    Referring to  FIGS. 1 ,  2 A and  2 B, the FET structure of the invention includes a semiconductor substrate  110 . Source/drain regions  14  are formed on the substrate  110 . the source/drain regions  14  include a stacked structure of a first silicon germanium (SiGe) layer  14   a , a silicon layer  14   b  and a second SiGe layer  14   c  sequentially stacked as shown. The first and second SiGe layers and the silicon layers can be epitaxial layers. The silicon layer  14   b  includes a round-shaped nano-wire channel region  12  extending across the structure along a longitudinal line X between the source/drain regions  14 . A portion of the substrate  110  protrudes above the surface of the substrate in the region beneath the nano-wire channel region  12 . As noted in  FIG. 2B , the nano-wire channel  12  and the protruding portion of the substrate  110  are separated by a distance d. An isolation region  116  isolates the FET from other devices. A gate dielectric layer  30  made of a material such as silicon oxide surrounds the nano-wire channel region  12 . The gate dielectric layer  30  also surrounds the protruding portion of the substrate. A gate  20  made of a conductive material such as polysilicon, metal or a combination of polysilicon and metal surrounds the nano-wire channel region  12 . The gate  20  is insulated from the nano-wire channel  12  by the gate dielectric layer  30 . 
         [0069]      FIG. 3  is a schematic cross-sectional view of another embodiment of the FET of  FIG. 1 , corresponding to line A-A′ of  FIG. 1 . The device  100 B of  FIG. 3  differs from that of  FIGS. 2A and 2B  in that, instead of the multiple-layer stack having the first and second SiGe layers  14   a  and  14   c  and the Si layer  14   b , the device of  FIG. 3  has only a single Si layer  14   d , which serves as the source/drain regions of the device and provides the round-shaped nano-wire channel  12  of the device. 
         [0070]      FIG. 4A  is a schematic cross-sectional view of another embodiment of the FET in accordance with the invention corresponding to the line A-A′ of  FIG. 1 .  FIG. 4B  is a schematic cross-sectional view of the embodiment of the FET of  FIG. 4A  corresponding to the line B-B′ of  FIG. 1 . 
         [0071]    Referring to  FIGS. 4A and 4B , the structure is different from that of the forgoing embodiments in that the FET  100 C includes multiple, i.e., two, round-shaped nano-wire channels  112   a  and  112   b , instead of a single nano-wire channel  12 . The structure  100 C includes a semiconductor substrate  110 . Source/drain regions  114  are formed on the substrate  110 . The source/drain regions  114  are formed of a stacked structure of a first SiGe layer  114   a , a first Si layer  114   b , a second SiGe layer  114   c , a second Si layer  114   d  and a third SiGe layer  114   e  sequentially stacked as shown. The first, second and third SiGe layers  114   a ,  114   c  and  114   e  and the first and second Si layers  114   b  and  114   d  can be epitaxial layers. The first Si layer  114   b  includes a first round-shaped nano-wire channel region  112   a  extending along a longitudinal line X 1  across the structure between the source/drain regions  114 . The second Si layer  114   d  includes a second round-shaped nano-wire channel  112   b  extending along a longitudinal line X 2  across the structure between the source/drain regions  114 . A portion of the substrate  110  protrudes above the surface of the substrate in the region beneath the nano-wire channel regions  112   a  and  112   b . As noted in  FIG. 4B , the first nano-wire channel  112   a  and the protruding portion of the substrate  110  are separated by a distance d 1 . Also, the second nano-wire channel region  112   b  and the protruding portion of the substrate  110  are separated by a distance d 2 . An isolation region  116  isolates the FET  100 C from other devices. A gate dielectric layer  30  made of a material such as silicon oxide surrounds the first and second nano-wire channel regions  112   a  and  112   b . The gate dielectric layer  30  also surrounds the protruding portion of the substrate. A gate  20  made of a conductive material such as polysilicon, metal or a combination of polysilicon and metal surrounds the nano-wire channel regions  112   a  and  112   b . The gate  20  is insulated from the nano-wire channels  112   a  and  112   b  by the gate dielectric layer  30 . 
         [0072]      FIG. 5  is a schematic cross-sectional view of another embodiment of the FET of  FIG. 1 , corresponding to line A-A′ of  FIG. 1 . The device  100 D of  FIG. 5  differs from that of  FIGS. 4   a  and  4   b  in that, instead of the multiple-layer stack having the first, second and third SiGe layers  114   a ,  114   c  and  114   e  and the first and second Si layers  114   b  and  114   d , the device of  FIG. 5  has only a single Si layer  114   f , which serves as the source/drain regions of the device and provides the round-shaped nano-wire channels  112   a  and  112   b  of the device. 
         [0073]      FIG. 6A  is a schematic cross-sectional view of another embodiment of a FET in accordance with the invention corresponding to the line A-A′ of  FIG. 1 .  FIG. 6B  is a schematic cross-sectional view of the FET of  FIG. 6A  corresponding to the line B-B′ of  FIG. 1 . 
         [0074]    Referring to  FIGS. 6A and 6B , the structure is different from that of the forgoing embodiments in that the FET  100 E includes multiple, i.e., three, round-shaped nano-wire channels  212   a ,  212   b  and  212   c , instead of the single nano-wire channel  12  or the two nano-wire channels  112   a  and  112   b . The structure  100 E includes a semiconductor substrate  110 . Source/drain regions  214  are formed on the substrate  110 . The source/drain regions  214  are formed of a stacked structure of a first SiGe layer  214   a , a first Si layer  214   b , a second SiGe layer  214   c , a second Si layer  214   d , a third SiGe layer  214   e , a third Si layer  214   f  and a fourth SiGe layer  214   g  sequentially stacked as shown. The first, second, third and fourth SiGe layers  214   a ,  214   c ,  214   e  and  214   g  and the first, second and third Si layers  214   b ,  214   d  and  214   f  can be epitaxial layers. The first Si layer  214   b  includes a first round-shaped nano-wire channel region  212   a  extending along a longitudinal line X 3  across the structure between the source/drain regions  214 . The second Si layer  214   d  includes a second round-shaped nano-wire channel  212   b  extending along a longitudinal line X 4  across the structure between the source/drain regions  214 . The third Si layer  214   f  includes a third round-shaped nano-wire channel  212   c  extending along a longitudinal line X 5  across the structure between the source/drain regions  214 . A portion of the substrate  110  protrudes above the surface of the substrate in the region beneath the nano-wire channel regions  212   a ,  212   b  and  212   c . As noted in  FIG. 6B , the first nano-wire channel  212   a  and the protruding portion of the substrate  110  are separated by a distance d 1 . Also, the second nano-wire channel region  212   b  and the protruding portion of the substrate  110  are separated by a distance d 2 . Also, the third nano-wire channel  212   c  and the protruding portion of the substrate  110  are separated by a distance d 3 . An isolation region  116  isolates the FET  100 E from other devices. A gate dielectric layer  30  made of a material such as silicon oxide surrounds the first, second and third nano-wire channel regions  212   a ,  212   b  and  212   c . The gate dielectric layer  30  also surrounds the protruding portion of the substrate. A gate  20  made of a conductive material such as polysilicon, metal or a combination of polysilicon and metal surrounds the nano-wire channel regions  212   a ,  212   b  and  212   c . The gate  20  is insulated from the nano-wire channels  212   a ,  212   b  and  212   c  by the gate dielectric layer  30 . 
         [0075]      FIG. 7  is a schematic cross-sectional view of another embodiment of the FET of  FIG. 1 , corresponding to line A-A′ of  FIG. 1 . The device  100 F of  FIG. 7  differs from that of  FIGS. 6A and 6B  in that, instead of the multiple-layer stack having the first, second, third and fourth SiGe layers  214   a ,  214   c ,  214   e  and  214   g  and the first, second and third Si layers  214   b ,  214   d  and  214   f , the device of  FIG. 7  has only a single Si layer  214   h , which serves as the source/drain regions of the device and provides the round-shaped nano-wire channels  212   a ,  212   b  and  212   c  of the device. 
         [0076]      FIG. 8  is a logical flow diagram illustrating the process of forming the round-shaped nano-wire channels and gate of the FET according to the invention.  FIGS. 9A through 9D  are schematic perspective views illustrating the steps in the process of forming the nano-wire channels and gate of the invention. The process of forming the nano-wire channels, the gate and the FET of the invention described herein is applicable to any of the embodiments of the FET described herein. Specifically, the formation process is applicable to a FET having any number of round-shaped nano-wire channels. 
         [0077]    Referring to  FIGS. 8 and 9A  through  9 D, in step S 50 , an active Si pattern having a polygonal cross-sectional shape is formed. For example, referring specifically to  FIG. 9A , the active Si pattern  402  can have flat exterior surfaces  402   b  and a substantially square shape  402   a  in cross section. 
         [0078]    Next, in step S 60 , a cleaning process is performed to remove any oxide that may have formed on the active Si pattern  402 . 
         [0079]    Next, in step S 70 , etching is performed to remove square corners from the active pattern  402 . An annealing step is performed to complete the round-shaped Si nano-wire channel  404 . As shown in  FIG. 9B , the channel  404  has a substantially round shape  404   a  in cross section. 
         [0080]    Next, in step S 80 , a gate dielectric layer  406  is formed surrounding the round-shaped nano-wire channel region  404 , as shown in  FIG. 9C . 
         [0081]    Next, in step S 90 , a gate electrode  408  is formed surrounding the gate dielectric layer  406  and the round-shaped or cylindrical Si nano-wire channel  404 , as shown in  FIG. 9D . The gate electrode  408  is made of a conductive material such as polysilicon, metal, or a combination of polysilicon and metal. 
         [0082]      FIG. 10  is a detailed flow diagram illustrating the process of forming the round nano-wire channel  404  from the square nano-wire channel  402 .  FIG. 10  will be described below in detail. 
         [0083]      FIGS. 11A through 11M  are schematic perspective views illustrating steps in a process of manufacturing the FET of the invention, in accordance with an embodiment of the invention. Referring to  FIG. 11A , a silicon substrate  500  is provided. A first silicon germanium (SiGe) layer  512  is formed on top of the substrate  500 . The first SiGe layer  512  can have a thickness of 5-50 nm and can contain 15-20% germanium. An active silicon layer  514  is formed over the first SiGe layer. The silicon layer  514  is the layer of which the round-shaped nano-wire channel region of the FET will eventually be formed. A second SiGe layer  516  is formed on the silicon layer  514 . The second SiGe layer  516  can be formed to a thickness of 5-50 nm and can contain 5-10% germanium. The second SiGe layer  516  may have a lower concentration of germanium such that during a subsequent etching process, the rate at which the upper layer of SiGe is consumed is lower to prevent damage to the silicon layer  514  to ensure a good nano-wire channel. In one embodiment, the first and second SiGe layers  512  and  516  and the silicon layer  514  are grown epitaxially to the thickness of 5-50 nm. 
         [0084]    A capping layer  518  is then formed over the second SiGe layer  516 . The capping layer may be a buffer oxide layer made of a material having a high etch selectivity with respect to silicon nitride (SiN), such as silicon oxide, for a subsequent etching process. Next, a hard mask layer, made of a material such as SiN, is formed on the buffer oxide layer  518 . The hard mask layer is patterned such as by photolithographic and etching processes to form a hard mask pattern  520  on the buffer oxide layer  518 . 
         [0085]    Referring to  FIG. 11B , the structure is etched using the hard mask pattern  520  as an etching mask to form a STI trench  522 . In one embodiment, the trench depth is 150-350 nm. 
         [0086]    Referring to  FIG. 11C , next, a shallow trench isolation (STI)  524  is formed in the trench  522 . The STI is formed by a high density plasma (HDP) process to deposit an oxide. After the HDP process, a chemical mechanical polishing (CMP) process is carried out to expose the top surface of the hard mask pattern  520 . As shown in the drawing, the slurry used during the CMP process has a higher polishing rate on the HDP oxide  524  than it has on the hard mask pattern  520  such that a step is created between the HDP oxide  524  and the hard mask pattern  520 . 
         [0087]    Next, referring to  FIG. 11D , the hard mask pattern  520  and a portion of the HDP oxide is removed using phosphoric acid, leaving the buffer oxide layer  518  and the top surface of the HDP oxide  524  exposed on the top of the structure. 
         [0088]    Next, referring to  FIG. 11E , a second hard mask pattern  530  is formed on the top surface of the structure by forming a hard mask layer made of SiN and then applying photolithographic and etching processes to pattern the hard mask layer. 
         [0089]    Next, referring to  FIG. 11F , the structure is etched using the second hard mask pattern  530  as an etching mask to form a STI recess  532 . The depth of the recess  532  is controlled to be deeper than the total thickness of the first and second SiGe layers  512 ,  516  and the Si layer  514 . That is, the recess  532  extends down into the structure deeper than the bottom of the epitaxial SiGe and Si layers. The width of the remaining epitaxial SiGe and Si layers, as well as a portion of the substrate beneath the epitaxial layers is indicated in the figure as W 1 . 
         [0090]    Next, referring to  FIG. 11G , the remaining portion of the SiGe epitaxial layers  512  and  516 , the remaining portion of the active Si layer  514   a  and the raised portion of the substrate beneath the epitaxial layers having the width W 1  are optionally trimmed by etching, such that the remaining portion of the epitaxial layers and the raised portion of the substrate beneath the epitaxial layers has a width W 2 . The etching is preferably a chemical dry etch (CDE), which can be carried out, for example, at 400 W, 225 mTorr, 250 degrees C. for 20 seconds, in an atmosphere containing CF 4  and O 2  at flow rates of 60 and 150 seem, respectively. The width W 2  is selected based on a desired size of the final nano-wire channel to be formed. The CDE is performed to reduce the channel width to W 2  and to make the channel square in cross-section.  FIG. 11H  is the structure of  FIG. 11G  rotated 90 degrees to clearly illustrate the resulting structure. 
         [0091]    Next, referring to  FIG. 11I , the sacrificial SiGe layers  512  and  516  on the top and bottom of the channel region  514   a  are removed to completely expose the channel region  514   a . It is also noted that a rectangular portion of the substrate  500  also remains beneath the channel region  514   a  following this step. This step is performed by a chemical wet etch using a chemical including CH 3 COOOH (or CH 3 COOH)+HF+DIW (deionized water) (+H2O2+surfactant, etc.). 
         [0092]    Next, referring to  FIG. 11J , the square cross-sectional channel region  514   a  is formed into a nano-wire channel  514   b  having a round or circular cross-section. This is performed by etching and annealing the square cross-sectional channel region  514   a  until it becomes the round nano-wire channel  514   b.    
         [0093]      FIG. 12  is a flow diagram illustrating the process of forming the round nano-wire channel  514   b  from the square nano-wire channel  514   a . First, an optional cleaning step S 100  is performed in an atmosphere of H2. In one embodiment, the cleaning is performed in an atmosphere of 100% H2. Alternatively, the atmosphere can also contain Ar and/or He with or without the H2. In one embodiment, the cleaning is performed at a pressure of 0.1 to 10 Torr and a temperature of 600-900 degrees C. In one particular embodiment, the cleaning is performed at a temperature of 700-800 degrees C. The gas flow rate during the cleaning step can be 1-500 sccm, and the process time can be 1-5 minutes. 
         [0094]    After the cleaning step, the four corners of the square nano-wire channel  514   a  are etched in step  5200 . The etching is carried out by introducing a combination of HCl and H2 gas into the process chamber. In one particular embodiment, the gas flow rate of HCl during the etching is 100-2000 sccm, and the gas flow rate of the H2 is 100-2000 sccm. The flow rate ratio of HCl:H2 can be in a range of 5:5 to 3:7. In one particular embodiment, the flow rate ratio of HCl:H2 is 300 sccm: 500 sccm. The etch temperature can be in the range of 600-900 degrees C., and the pressure can be 10-100 Torr. The time of the etch can be in the range of 1-120 seconds. 
         [0095]    The etch of step  5200  can be performed under one of at least three possible sets of conditions. For a relatively long-duration, low-temperature etch, the etch temperature can be in the range of 600-700 degrees C. For a relatively short-duration, high-temperature etch, the etch temperature can be in the range of 850-900 degrees C. Between the two process conditions above, the middle-duration, middle-temperature etch can be carried out at a temperature between 750 and 820 degrees C. 
         [0096]    After the etching process, a low-temperature annealing is carried out in step S 300  to form the round-shaped nano-wire channel region  514   b . The annealing is performed in an atmosphere of H2 gas. In one embodiment, the annealing is performed at a pressure of 0.1-10 Torr. If the pressure is lowered, the process time can also be lowered. In one embodiment, the annealing is performed at a temperature of 600-900 degrees C. for a period of 10-800 seconds. In one embodiment, the H 2  gas flow rate is 1-500 sccm. In one particular embodiment, the annealing is carried out at a temperature of about 810 degrees C., at a pressure of 5 Torr and for a period of 500 seconds. 
         [0097]    The etching and annealing steps can be repeated as many times as are needed to form the final round-shaped nano-wire channel  514   b . Between the annealing step S 300  and the next repeated etching step S 200 , a purging step S 400  can be performed to remove the remaining annealing H 2  gas from the process chamber. The purge can be performed using at least one of Ar, He and H 2  gas. 
         [0098]    After the purging step S 400 , a determination is made in step S 500  as to whether the channel  514   b  is the desired size and/or shape. If the channel  514   b  is of the proper shape and size, the process ends. If not, the process returns to step S 200  to begin another cycle of etching, annealing (S 300 ) and optional purging (S 400 ). 
         [0099]    Referring to  FIG. 11K , after the round-shaped nano-wire channel  514   b  is formed, a gate dielectric layer is formed on the structure, including surrounding the nano-wire channel  514   b . The gate dielectric can be formed by growing SiO2 on the structure using O2 gas. Next, a gate material such as polysilicon or a metal layer with polysilicon is formed surrounding the nano-wire channel  514   b . Then the gate material is planarized such as by chemical mechanical polishing (CMP) to form the gate  540  surrounding the nano-wire channel  514   b.    
         [0100]    Next, referring to  FIG. 11L , the second hard mask pattern  530  is removed.  FIG. 11M  illustrates the final structure with the gate pattern  540  shown in phantom.  FIG. 11M  shows the round-shaped nano-wire channel  514   b  and the raised portion of the substrate  500 , which have both been formed into a round shape by the etching and annealing steps of the invention. 
         [0101]    It is noted that this embodiment of manufacturing a FET is applicable to formation of any number of channel regions. Where more channel regions are to be formed, more alternating layers of SiGe and Si are initially formed. 
         [0102]    It should be noted that  FIG. 2A  corresponds to a cross-sectional view of  FIG. 11L , taken along line IIa-IIa′ of  FIG. 11L . Likewise,  FIG. 2B  corresponds to a cross-sectional view of  FIG. 11L , taken along line IIb-IIb′ of  FIG. 11L . 
         [0103]      FIGS. 12A through 12K  are views illustrating steps in a process of manufacturing the FET of the invention, in accordance with another embodiment of the invention. The initial steps used in the embodiment of  FIGS. 12A through 12K  are the same as those illustrated in the previously described embodiment for steps  11 A through  11 D. For the remaining steps, where a step is analogous to a step described in connection with the embodiment of  FIGS. 11A through 11M , the step is carried out in similar fashion. Therefore, description of those steps will not be repeated.  FIG. 12A-12F  are schematic cross-sectional views of the structure of  FIG. 11D , taken along line XII-XII′ of  FIG. 11D , illustrating steps in the process of manufacturing a FET according to the embodiment of the invention.  FIGS. 12G-12K  are schematic perspective views illustrating steps in the process of manufacturing a FET according to the embodiment of the invention. Referring to  FIG. 12A , the structure resulting after performance of steps  11 A through  11 D is illustrated. 
         [0104]    Next, referring to  FIG. 12B , a hard mask pattern  630  is formed on the structure. The hard mask pattern  630  can be formed by patterning a layer of SiN. 
         [0105]    Next, referring to  FIG. 12C , recessed regions  632  are formed in the structure. This can be performed by etching a trench to a depth deeper than the first epitaxial SiGe layer  512  using the hard mask pattern  630  as an etching mask. 
         [0106]    Next, referring to  FIG. 12D , the recess  632  is partially filled by epitaxially growing a Si layer  640  in the recess. In one embodiment, the epitaxial Si layer  640  is grown to a depth higher than the second epitaxial SiGe layer  516 . 
         [0107]    Next, referring to  FIG. 12E , another hard mask pattern made of, for example, SiN is formed above the epitaxial Si layer  640  and adjacent to the hard mask pattern  630 . 
         [0108]    Referring to  FIGS. 12F and 12G , the hard mask pattern  630  is then removed, exposing the top or second epitaxial SiGe layer  516  and a portion of the top surface of the STI dielectric layer  524 . 
         [0109]    Next, referring to  FIG. 12H , the structure is etched to remove a portion of the STI dielectric layer  524  to form a damascene recessed region  532  to expose the sides of the stack of the first and second SiGe layers  512  and  516 , the Si layer  514  and a portion of the substrate  500  beneath the stacked epitaxial layers  512 ,  514  and  516 . 
         [0110]    Next, referring to  FIG. 12I , the structure is etched, preferably by a chemical dry etch to trim the first and second sacrificial SiGe layers  512  and  516 , the Si layer  514  and the protruding portion of the substrate  500 . The trimming also exposes a portion of the epitaxial Si layer  640  as shown. 
         [0111]    Next, referring to  FIG. 12J , the sacrificial SiGe layers  512  and  516  on the top and bottom of the channel region  514   a  are removed to completely expose the channel region  514   a . It is also noted that the rectangular protruding portion of the substrate  500  also remains beneath the channel region  514   a  following this step. This step is performed by a chemical wet etch using a chemical including CH 3 COOOH (or CH 3 COOH)+HF+DIW (deionized water) (+H2O2+surfactant, etc.). 
         [0112]    Next, referring to  FIG. 12K , the channel region  514   a  is cleaned, etched and annealed in accordance with the description of  FIG. 10  to form the round-shaped nano-wire channel region  514   b . It is noted that in this embodiment, the source/drain regions of the FET are made from the single epitaxial Si layer  640 , as opposed to the stacked structure of epitaxial SiGe and Si layers. It is also noted that this embodiment, like the previously described embodiment, is applicable to formation of any number of channel regions. Where more channel regions are to be formed, more alternating layers of SiGe and Si are initially formed. 
         [0113]    While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.