Abstract:
A thin film transistor liquid crystal display (TFT LCD), including a TFT array substrate, a color filter substrate and a post spacer disposed between the TFT array substrate and the color filter substrate. The TFT array substrate includes a gate line, a data line, and a TFT disposed in a pixel area defined by the gate line and the data line crossing with each other, and the TFT comprises a source/drain electrode. The post spacer is located in a region at least partially surrounded by the source/drain electrode, the data line and the gate line.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    The present invention relates to a thin film transistor liquid crystal display (TFT LCD). 
         [0002]    Among the various flat panel display technologies, TFT LCDs are dominating the flat panel display market due to lower power consumption, relatively low manufacturing cost, no radiation, etc. A TFT LCD can be formed by assembling an array substrate and a color filter substrate with a liquid crystal layer interposed therebetween. Post spacers are typically formed on the color filter substrate to maintain a cell gap between the substrates. 
         [0003]      FIG. 1   a  is a schematic view showing a conventional TFT LCD. As shown in  FIG. 1   a , there are a plurality of gate lines  1 , a plurality of common electrodes  12 , and a plurality of data lines  5  perpendicular to the gate lines  1  on the array substrate of the TFT LCD. The adjacent gate lines and data lines cross with each other to define pixel areas. Each pixel area comprises a TFT switching device, a transparent pixel electrode  10 , two light blocking bars  11 , and a part of the common electrode  12 .  FIG. 2   a  is a schematic view of the color filter of the TFT LCD shown in  FIG. 1   a . As shown in  FIG. 2   a , there are a black matrix  14  and color filters  15  of primary colors such as red, green, and blue on the color filter substrate of the TFT LCD. Each color filter  15  corresponds to one pixel area on the array substrate. Post spacers  13  are arranged uniformly across the color filter substrate. The post spacers  13  are located above the TFT switching device after the assembling of the substrates. 
         [0004]    As shown in  FIG. 1   b , the TFT switching device comprises a gate electrode  2 , a gate insulating layer  4 , a semiconducting active layer  3 , and a source electrode  6  and a drain electrode  7 . A transparent electrode  10  is connected with the drain electrode  7  of the TFT device via a through-hole  9  in a passivation layer  8 . The top end of post spacer  13  is pressed against the TFT device. It can be seen that since the post spacer  13  contacts the TFT substrate on the TFT device, the highest position of the TFT array substrate, the post spacer tends to be moved to a lower position under pressure or upon impact, and also it is difficult for the post spacer to return to the original position once being moved, thus causing light leakage. Thus caused poor performance will significantly affect the yield as well as the display quality of the TFT LCD. 
       SUMMARY OF THE INVENTION 
       [0005]    In view of the problems in the conventional TFT LCD, the present invention provides a novel TFT LCD with a more stable configuration. 
         [0006]    In one aspect of the present invention, there is provided a TFT LCD. The TFT LCD comprises a TFT array substrate, a color filter substrate, and a post spacer disposed between the TFT array substrate and the color filter substrate. The TFT array substrate comprises a gate line extending in a first direction, a data line extending in a second direction perpendicular to the first direction, and a TFT disposed in a pixel area defined by the gate line and the data line crossing with each other. The TFT comprises a source/drain electrode extending in the second direction. The post spacer is located in a region at least partially surrounded by the source/drain electrode, the data line, and the gate line. 
         [0007]    Preferably, in one embodiment, the TFT LCD further includes a light blocking bar in the pixel area. The light blocking bar comprises a bending end extending towards the source/drain electrode, and the post spacer is located in the region at least partially surrounded by the bending end of the light blocking bar, the source/drain electrode, the data line, and the gate line. 
         [0008]    The bending end of the light blocking bar may be about 1-60 μm in length and is separated from the source/drain electrode. The distance between the bending end of the light blocking bar and the gate line may be about 1-60 μm. 
         [0009]    Preferably, in another embodiment of the present invention, a part of the data line adjacent to the position where the data line and the gate line cross with each other and a corresponding active layer under the part of the date line have a bending shape so as to form a closed region with the source/drain electrode and the gate line, and the post spacer is located in the closed region. 
         [0010]    Preferably, the bending shape of the part of the data line and the corresponding active layer therebelow is a V-shape. 
         [0011]    Preferably, the longitudinal sectional shape of the post spacers may be a trapezoid, while the cross-sectional shape of the post spacer may be a circle or a polygon, such as a tetragon. 
         [0012]    Preferably, one end of the post spacer on the TFT array substrate may have a width of about 1-40 μm while another end of the post spacer on the color filter substrate may have a width of about 1-80 μm. 
         [0013]    Preferably, an opening is formed in the at least partially surrounded region of the TFT array substrate and one end of the post spacer is located in the opening. The opening may expose a pixel electrode on an underlying substrate of the TFT substrate. 
         [0014]    Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from the following detailed description. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]    The present invention will become more fully understood from the detailed description given hereinafter and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention and wherein: 
           [0016]      FIG. 1   a  is a schematic view showing a conventional TFT LCD. 
           [0017]      FIG. 1   b  is a cross-sectional view of the conventional TFT LCD taken along line A-A′ in  FIG. 1   a.    
           [0018]      FIG. 2   a  is a schematic view of the color filter of the conventional TFT LCD shown in  FIG. 1   a.    
           [0019]      FIG. 2   b  is a cross-sectional view of the color filter taken along line B-B′ in  FIG. 2   a.    
           [0020]      FIG. 3   a  is a top plan view of a TFT LCD according to a first embodiment of the present invention. 
           [0021]      FIG. 3   b  is a cross-sectional view of the TFT LCD of the first embodiment, taken along line C-C′ in  FIG. 3   a.    
           [0022]      FIG. 3   c  is a cross-sectional view of the TFT LCD of the first embodiment, taken along line D-D′ in  FIG. 3   a.    
           [0023]      FIG. 4   a  is a schematic view of the color filter corresponding to the first embodiment of the TFT LCD shown in  FIG. 3   a.    
           [0024]      FIG. 4   b  is a cross-sectional view of the color filter taken along line E-E′ in  FIG. 4   a.    
           [0025]      FIG. 5  is a top plan view of the TFT LCD array substrate of the present invention after the first mask process. 
           [0026]      FIG. 6   a  is a cross-sectional view of the TFT LCD of a second embodiment, taken along line C-C′ in  FIG. 3   a.    
           [0027]      FIG. 6   b  is a cross-sectional view of the TFT LCD of the second embodiment taken along line D-D′ in  FIG. 3   a.    
           [0028]      FIG. 7   a  is a top plan view of the TFT LCD array substrate after the deposition of the passivation layer according to the second embodiment of the present invention. 
           [0029]      FIG. 7   b  is a cross-sectional view of the second embodiment of the TFT LCD array substrate, taken along line F-F′ in  FIG. 7   a.    
           [0030]      FIG. 7   c  is a cross-sectional view of the second embodiment of the TFT LCD array substrate, taken along line G-G′ in  FIG. 7   a.    
           [0031]      FIG. 8   a  is a top plan view of the TFT LCD array substrate after the etching of the opening according to the second embodiment of the present invention. 
           [0032]      FIG. 8   b  is a cross-sectional view of the second embodiment of the TFT LCD array substrate, taken along line H-H′ in  FIG. 8   a.    
           [0033]      FIG. 8   c  is a cross-sectional view of the second embodiment of the TFT LCD array substrate, taken along line I-I′ in  FIG. 8   a.    
           [0034]      FIG. 9   a  is a top plan view of the TFT LCD according to a third embodiment of the present invention. 
           [0035]      FIG. 9   b  is a cross-sectional view of the third embodiment of the TFT LCD taken along line C-C′ in  FIG. 9   a.    
           [0036]      FIG. 9   c  is a cross-sectional view of the third embodiment of the TFT LCD taken along line D-D′ in  FIG. 9   a.    
           [0037]      FIG. 10   a  is a schematic view of the color filter corresponding to the third embodiment of the TFT LCD shown in  FIG. 9   a.    
           [0038]      FIG. 10   b  is a cross-sectional view of the TFT LCD of the third embodiment taken along line E-E′ in  FIG. 9   a;    
           [0039]      FIG. 11  is a top plan view of the TFT LCD array substrate after the first mask process according to the present invention. 
           [0040]      FIG. 12  is a top plan view of the TFT LCD array substrate after the second mask process according to the present invention. 
           [0041]      FIG. 13  is a top plan view of the TFT LCD array substrate after the third mask process according to the present invention. 
           [0042]      FIG. 14  is a top plan view of the TFT LCD array substrate after the fourth mask process according to the present invention. 
           [0043]      FIG. 15   a  is a cross-sectional view of the TFT LCD array substrate taken along line C-C′ in  FIG. 9   a  according to a fourth embodiment of the present invention. 
           [0044]      FIG. 15   b  is a cross-sectional view of the fourth embodiment of the TFT LCD array substrate taken along line D-D′ in  FIG. 9   a.    
           [0045]      FIG. 16  is a top plan view of the TFT LCD array substrate after the fourth mask process according to the fourth embodiment of the present invention. 
           [0046]      FIG. 17  is a top plan view of the TFT LCD according to another pixel structure of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0047]    Exemplary embodiments of the present invention will be described hereinafter with reference to the accompanying drawings. It will be understood that when a layer or an element is referred to as being “on” or “connected to” another layer or substrate, it can be directly on or connected to the other layer or substrate, or intervening layers may also be present. The same reference number refers to the same part in the following drawings. 
       The First Embodiment 
       [0048]    The TFT LCD according to the first embodiment of the present invention comprises a color filter substrate, a TFT array substrate, a liquid crystal layer sealed between the color filter substrate and the TFT array substrate, and post spacers are disposed between the color filter substrate and the TFT array substrate to maintain the cell gap between the substrates after assembling. 
         [0049]      FIG. 3   a  is a schematic plan view showing the TFT LCD according to the first embodiment of the present invention. As shown in  FIG. 3   a , there are a plurality of gate lines  1 , a plurality of common electrodes  12 , and a plurality of data lines  5  perpendicular to the gate lines  1  arranged on the TFT array substrate of the TFT LCD. The adjacent gate lines and data lines cross with each other to define pixel areas. Each pixel area comprises a TFT switching device, a transparent pixel electrode  10 , a light blocking bar  11 , and a part of the common electrode  12 . As shown in  FIGS. 3   a  and  3   c , each of the TFT devices comprises a gate electrode  2 , a gate insulating layer  4 , a semiconductor active layer  3 , and a source electrode  6  and a drain electrode  7 . The transparent pixel electrode  10  is connected to the drain electrode  7  of the TFT device via a through-hole  9  in a passivation layer  8 . 
         [0050]    According to the present embodiment, a post spacer  13  is located in the region at least partially surrounded by the drain electrode  7 , one data line  5 , and one gate line  1 . Furthermore, the shape of a light blocking bar  11  arranged along the data line on the TFT array substrate is changed by bending the end of the light blocking bar  11  adjacent to the post spacer  13  towards the drain electrode  7 . The bending angle is preferable 90 degree. The length of the bending portion is about 1-60 μm, and the light blocking bar does not make contact with the drain electrode  7 , i.e., is separated from the drain electrode  7 . The distance between the bending end and the gate line is about 1-60 μm so as to limit the movement of the post spacer  13  more effectively. Optionally, such shape change can also be applied to the light blocking bar at the positions not adjacent to the post spacer. 
         [0051]    In the above case, the post spacer  13  is located between the drain electrode  7  and the data line  5  as well as between the light blocking bar  11  and the gate line  1 . Preferably, in order to increase the contact area between the post spacer  13  and the surrounding parts of the at least surrounded region to enhance the stability, the cross sectional shape of the post spacer  13  can also be changed to a tetragon or other polygon from a circle shape. Since the contact position between the post spacer  13  and the TFT array substrate is changed compared with that in the conventional LCD, it is necessary to increase the height of the post spacer  13  by the increment that is equal to the step difference of the TFT structure in order to maintain the same cell gap. 
         [0052]    As shown in  FIGS. 3   b  and  3   c , the post spacer  13  is located between the gate line  1  and the light blocking bar  11  in the sectional view along line C-C′, while the post spacer  13  is located between the drain electrode  7  and the data line  5  in the sectional view along line D-D′. The step difference of TFT structure in all the four directions is about 2000-10,000 Å, and the height of the post spacer  13  is about 2-4 μm, i.e., about 20,000-40,000 Å. The spacing between the post spacer  13  and the surrounding parts is about 1-10 μm in view of matching the required and actual alignment accuracy. 
         [0053]    As shown in  FIG. 4   a  (the top plan view) and  FIG. 4   b  (the cross sectional view), the color filter substrate according to the first embodiment of the present invention comprises a color filter panel (e.g., a glass substrate), a black matrix  14 , and a color filter  15  (for example, a red, green, or blue filter). The shape of the area of the color filter  15  corresponding to the pixel area of the TFT substrate is also changed to accommodate the positional change of the post spacer. 
         [0054]    The above TFT LCD is only an exemplary embodiment. The structure with other shape and pattern is also within the scope and spirit of the present invention as long as the post spacer is moved to a region at least surrounded by the drain electrode  7 , the data line  5 , and the gate line  1 . 
         [0055]    The above TFT LCD according to the first embodiment of the present invention can be manufactured by the following method. 
         [0056]    First, a gate metal film is formed on an underlying substrate such as a glass substrate in a thickness between about 1000 Å and 7000 Å by a magnetron sputtering method, for example. As shown in  FIG. 5 , at least one gate line  1  and the gate electrode  2  and the pattern of the common electrode  12  and the light blocking bar  11  are formed on a specified area of the glass substrate by an exposure and etching process, that is, a patterning process, using a gate mask plate. The end of the light blocking bar  11  adjacent to a position where the post spacer is to be located is bended towards the drain electrode to be formed with a preferred bending angle of 90 degree. 
         [0057]    Thereafter, a gate insulating layer film in a thickness between about 1000 Å and 6000 Å and a semiconductor film such as an amorphous silicon film in a thickness between about 1000 Å and 6000 Å are successively deposited on the array substrate by a chemical vapor deposition (CVD) method, for example. The amorphous silicon film is etched after an exposure and etching with a mask plate for the active layer so as to form a silicon island serving as an active layer of a TFT. The gate insulating layer between the gate metal film and the amorphous silicon serves as an etching stop layer. 
         [0058]    Next, a metal film in a thickness between about 1000 Å and 7000 Å similar to the thickness of the gate metal film is deposited on the array substrate by a preparation method similar to the gate line. At least one data line  5 , the source electrode  6 , the drain electrode  7  are formed on a specific area by patterning with a mask plate for the source/drain electrode. The source electrode  6  and the drain electrode  7  are connected with respective ends of the active layer of the TFT, respectively. 
         [0059]    Next, a passivation layer  8  in a thickness between about 1000 Å and 6000 Å is deposited on the whole array substrate with a preparation method similar to the gate insulating layer and the active layer. A passivation layer through-hole  9  (with variation such as a trench or other structure) over a part of drain electrode is formed by an exposure and etching process with a mask plate for the passivation layer. 
         [0060]    Finally, a pixel electrode film, for example, of a transparent material is deposited on the substrate and the pixel electrode  10  is formed by patterning process with a mask plate for the pixel electrode. The typical materials for the transparent pixel electrode may be indium tin oxide (ITO), indium zinc oxide (IZO), or aluminum zinc oxide (AZO) in a thickness between about 100 Å and 1000 Å. The completed TFT pixel structure is shown in  FIGS. 3   a  and  3   c , respectively. 
       The Second Embodiment 
       [0061]    In the first embodiment, the post spacer contacts the pixel electrode formed on the passivation layer, as shown in  FIGS. 3   b  and  3   c , while in a second embodiment, the post spacer contacts the pixel electrode formed directly on the glass substrate as the underlying substrate with the passivation layer and the gate insulating layer being removed by an opening etching method, as shown in  FIGS. 6   a  and  6   b . The sidewall of the opening  16  has a sloping angle in a range of about 20-90 degree. 
         [0062]    The step difference around the post spacer  13  is increased with such design so as to limit the movement of the post spacer more effectively. In order to maintain the same cell gap as that in the first embodiment after assembling, it is necessary to further increase the height of the post spacer  13  by an increment that is equal to the sum of the passivation layer  8  and the gate insulating layer  4 . Optionally, the depth of the opening can be also smaller than the sum of the passivation layer  8  and the gate insulating layer  4 , that is, the passivation layer  8  and the gate insulating layer  4  can be partially removed. 
         [0063]    The TFT LCD according to the second embodiment can be manufactured by the following method. 
         [0064]    The active layer, source/drain metal layer, and the passivation layer can be formed with the same method as that in the first embodiment. The resultant TFT structure is shown in  FIG. 7   a , while the opening for the post spacer  13  can be formed as shown in  FIGS. 7   b  and  7   c . The through-hole  9  in the passivation layer  8  over the part of the drain electrode  7  and the opening  16  in the position of the post spacer  13  are formed by an exposure and the etching process with a mask plate for the passivation layer, as shown in  FIGS. 8   a ,  8   b , and  8   c . Because of the etching selectivity, the etching process for the passivation through-hole  9  would stop after the passivation layer over the part of drain electrode is removed, while the etching process for the post spacer opening  16  would continue until the gate insulating layer is completely removed. Finally, the pixel electrode  10  is formed by a patterning process with a mask plate for the pixel electrode. The typical materials for the transparent pixel electrode may be ITO, IZO, or AZO in a thickness between about 100 Å and 1000 Å. 
         [0065]    Also, the post spacer preferably contacts the glass substrate directly as the underlying substrate without pixel electrode formed thereon via the opening  16 . In the above process, when patterning the pixel electrode  10 , the pixel electrode layer that is deposited within the opening  16  can be etched away, thus exposing the underlying substrate. 
       The Third Embodiment 
       [0066]      FIG. 9   a  is a schematic plan view showing the TFT LCD according to a third embodiment of the present invention. As shown in  FIG. 9   a , there are a plurality of gate lines  1 , a plurality of common electrodes  12 , and a plurality of data lines  5  perpendicular to the gate lines  1  arranged on the TFT array substrate of the TFT LCD. The adjacent gate lines and data lines cross with each other to define pixel areas. Each pixel area comprises a TFT switching device, a transparent pixel electrode  10 , a light blocking bar  11 , and a part of the common electrode  12 . As shown in  FIGS. 9   a  and  9   c , each of the TFT devices comprises a gate electrode  2 , a gate insulating layer  4 , a semiconductor active layer  3 , and a source electrode  6  and a drain electrode  7 . A transparent pixel electrode  10  is connected to the drain electrode  7  of the TFT via a through-hole  9  in a passivation layer  8 . 
         [0067]    According to the third embodiment of the present invention, the shape of a part of the data line  5  and the corresponding active layer therebelow is changed by bending the part of data line  5  adjacent to (below as shown) the position where the data line  5  and the gate line  1  cross with each other towards source electrode  6  in the plan view to form a V-shape. The bending angle between the extending data line and the bending portion is about 45 degree while the V-shape bending angle of the bending portion is preferably 90 degree. The length of the bending portion is preferable about 1-60 μm. The shape of the source electrode  6  and the data line  5  is also changed accordingly, so that the source electrode  6 , the gate line  1 , and the bended data line  5  together form a closed region in order to limit the movement of post spacer located therein. 
         [0068]    In the above case, the post spacer  13  is located in closed region surrounded by the source electrode  6 , the gate line  1 , and the bended data line  5 . Preferably, in order to increase the contact area between the post spacer  13  and the surrounding parts of the closed region to enhance the stability, the cross sectional shape of the post spacer can also be changed to tetragon or other polygon from a circle shape. Since the contact position between the post spacer and the TFT array substrate is changed compared with that in the conventional TFT LCD, it is necessary to increase the height of the post spacer  13  by the increment that is equal to the step difference of the TFT structure in order to maintain the same cell gap after assembling. 
         [0069]    As shown in  FIGS. 9   b  and  9   c , the post spacer  13  is located between the source electrode  6  and the data line  5  in the sectional view along line C-C′, while the post spacer  13  is located between the gate line  1  and the data line  5  in the sectional view along line D-D′. The step difference of TFT structure in all the four directions is about 2000-10000 Å, and the height of the post spacer is about 2-4 μm, i.e., about 20,000-40,000 Å. The spacing between the post spacer  13  and the surrounding parts of the closed region is about 1-10 μm in view of matching the required and actual alignment accuracy. 
         [0070]    As shown in  FIG. 10   a  (the top plan view) and  FIG. 10   b  (the cross sectional view), the color filter substrate according to the third embodiment of the present invention comprises a color filter panel (e.g., a glass substrate), a black matrix  14 , a color filter (e.g., a red, green, or blue filter)  15 . The shape of the area of the color filter  15  corresponding to the pixel area of the TFT substrate is also changed to accommodate the positional change of the post spacer. 
         [0071]    The above TFT LCD is only another exemplary embodiment. The structure with other shape and pattern is also within the scope and spirit of the present invention, as long as the post spacer  13  is moved to the position in a region surrounded by the source electrode  6 , the gate line  1 , and the data line  5 . For example, as shown in  FIG. 17 , the cross section of the post spacer could be a hexagonal shape. 
         [0072]    The above TFT LCD according to the third embodiment can be manufactured by the following method. 
         [0073]    First, a gate metal film is prepared on an underlying substrate such as a glass substrate in a thickness between about 1000 Å and 7000 Å by a magnetron sputtering method, for example. As shown in  FIG. 11 , at least one gate line  1  and the gate electrode  2  and the pattern of the common electrode  12  and the light blocking bar  11  are formed on a specified area of the glass substrate by an exposure and etching process, i.e., a patterning process, using a gate mask plate. 
         [0074]    Thereafter, a gate insulating layer film in a thickness between about 1000 Å and 6000 Å and a semiconductor film such as an amorphous silicon film in a thickness between about 1000 Å and 6000 Å are successively deposited on the array substrate by the a CVD method, for example. The amorphous silicon film is etched after an exposure and patterning process with a mask plate for the active layer so as to form a silicon island serving as an active layer of a TFT. The gate insulating layer between the gate metal film and the amorphous silicon serves as an etching stop layer. In this step, the active layer  3  adjacent to (below as shown) the position where the gate line  1  and the data line  5  to be formed cross with each other is bended to be formed in a V-shape. The resultant structure after this step is shown in  FIG. 12 . 
         [0075]    Next, a metal film in a thickness between about 1000 Å and 7000 Å similar to the gate metal film is deposited on the array substrate by a preparation method similar to the gate line. At lease one data line  5 , the source electrode  6 , the drain electrode  7  are formed on a specific area by patterning with a mask plate for the source/drain electrode. The source electrode  6  and the drain electrode  7  are connected with respective ends of the active layer of the TFT, respectively. In this step, a part of the data line  5  is also bended toward the source electrode into a V-shape in accordance with the shape of the active layer therebelow. The resultant structure after this step is shown in  FIG. 13 . 
         [0076]    Next, a passivation layer  8  in a thickness between about 1000 Å and 6000 Å is deposited on the whole array substrate with a preparation method similar to the gate insulating layer and the active layer. A passivation layer through-hole  9  (with variation such as a trench or other structure) over a part of drain electrode is formed by an exposure and etching process with a mask plate for the passivation layer. The resultant structure after this step is shown in  FIG. 14 . 
         [0077]    Finally, a pixel electrode film, for example, of a transparent material is deposited on the substrate and the pixel electrode  10  is formed by patterning with a mask plate for the pixel electrode. The typical materials for the transparent pixel electrode may be ITO, IZO, or AZO in a thickness between about 100 Å and 1000 Å. The completed TFT pixel structure is shown in  FIGS. 9   a  and  9   c  in a plan view and a cross-section view, respectively. 
       The Fourth Embodiment 
       [0078]    In the third embodiment, the post spacer  13  contacts the passivation layer  8 , as shown in  FIGS. 9   b  and  9   c , while in a fourth embodiment, the post spacer  13  directly contacts the glass substrate as the underlying substrate with the passivation layer and the gate insulating layer being removed by an opening etching method, as shown in  FIGS. 15   a  and  15   b . The sidewall of the opening  16  has a sloping angle in a range of about 20-90 degree. 
         [0079]    The step difference around the post spacer  13  is further increased with such design so as to limit the movement of the post spacer more effectively. In order to maintain the same cell gap as that in the first embodiment, it is necessary to further increase the height of the post spacer  13  by an increment equal to the sum of the passivation layer  8  and the gate insulating layer  4 . Optionally, the depth of the opening  16  can also be smaller than the sum of the passivation layer  8  and the gate insulating layer  4 , that is, the passivation layer  8  and the gate insulating layer  4  can be partially removed. 
         [0080]    The above TFT LCD according to the fourth embodiment can be manufactured by the following method. 
         [0081]    The active layer, source/drain metal layer, and the passivation layer can be formed with the same method as that in the third embodiment. The through-hole  9  in the passivation layer  8  over the part of the drain electrode  7  and the opening  16  where the post spacer is located are formed by an exposure and etching process with a mask plate for the passivation layer, as shown in  FIG. 16 . Because of the etching selectivity, the etching process for the passivation opening  9  would stop after the passivation layer over the part of drain electrode is removed, while the etching process for the post spacer opening  16  would continue until the gate insulating layer  4  is completed removed. Finally, the pixel electrode  10  is formed by patterning with a mask plate for the pixel electrode, and also the underlying substrate is exposed through the opening  16  through the patterning. The typical materials for the transparent pixel electrode may be ITO, IZO, or AZO in a thickness between about 100 Å and 1000 Å. 
         [0082]    In the above embodiments of the present invention, the post spacer is located in a region at least partially surrounded by a source/drain electrode, a data line, and a gate line after assembling of the substrates, that is, is located in a lower position of the TFT structure. This design can prevent the post spacer from moving beyond the at least partially surrounded region under pressure or upon impact and thus prevent light leakage even when the maximum dislocation arises in the alignment accuracy. The spacing between the post spacer and surrounding parts depends on the alignment requirement and is compatible with the actual alignment accuracy. 
         [0083]    The above embodiments are only exemplary embodiments of the present invention. The other embodiments are also possible by modifying the structure of the TFT device, changing the number of the post spacers or the spacing of the post spacers, or introducing other additional spacers. Such modification and variation is also included within the scope of the present invention. 
         [0084]    Although the present invention has been described in detail referring to the preferable embodiments, the above embodiments are used only for illustration and not for the purpose of limitation. Accordingly, it will be understood by those of ordinary skilled in the art that it is possible to use other materials and equipments if necessary, that is, various modification or equivalent alteration may be made to the embodiments of the present invention without departing from the spirit and scope of the present invention as set forth in the following claims.