Abstract:
A scalable analog-to-digital (A/D) converter with digital down conversion (DDC) may be utilized to substitute a very-high-speed A/D converter. The A/D converter has flexibility and scalability including the number of low-speed A/D converters, fine-adjustable attenuations, digital FIR filters or one digital FIR filter, with operating in parallel. The scalable A/D converter has aliasing free and does not have phase distortion. The DDC may be able to shift bandpass signals into baseband signals and decimate the baseband signals according to different down samplings. The DDC may have scalability to deal with multirate operation. The scalable A/D converter with DDC may be adapted to decrease the computational complexity of the resulting calculations, making the system amenable to use in high frequency sampling sensitive applications and in those situations where the available processor&#39;s performance is relatively limited. The entire system may be implemented in an efficient way either hardware or software.

Description:
BACKGROUND  
         [0001]    This invention relates generally to ultra wideband communications.  
           [0002]    Ultra wideband communications (UWB) is true digital radio communication; completely unlike the radios we listen to and communicate every day. UWB is a wireless broadband communications technology fundamentally different from all other radio frequency (RF) communications. UWB achieves wireless broadband communication without using a RF carrier. Instead, UWB is a sequence of very short electrical pulses, billionths of a second long, which exist not on any particular frequency but on all frequencies simultaneously. UWB uses modulated pulses with less one nanosecond in duration. The modulated pulse is usually assigned a digital representation of 0 or 1 to the transmitted and received pulse based on where the pulse is place in time. The key to turning the digital pulses into wireless broadband communication lies in the timing of the pulses. In order to hear the information in that code, a UWB receiver has to know the exact pulse sequence used by the transmitter.  
           [0003]    Each pulse can exist simultaneously across an extensive band of frequencies if the distributed energy of the pulse at any given frequency exists in the noise floor. Therefore, UWB can co-exist with RF carrier-based communications with no discernable interference. This opens vast new communications with providing tremendous wireless bandwidth to ease the growing bandwidth crunch.  
           [0004]    The U.S. Federal Communications Commission (FCC) on Feb. 14, 2002 authorized limited commercial use of wireless devices based on a communication technology called ultra wideband. The FCC&#39;s restrictions require that commercial ultra wideband devices must operate in radio spectrum in the frequency ranges from 3.1 GHz to 10.6 GHz. UWB communication devices should also satisfy by Part 15.209 rule, which set emission limits for operation.  
           [0005]    UWB communication transceivers can transfer information data at rates of 100 mega-bit per second (Mbps) to 1 giga-bit per second (Gbps), with sending repeated ultra-short pulse signals across distances as great as 500 feet, even up to 2 kilometers.  
           [0006]    With transmitting repeated ultra-short pulse signals for the high data rate up to 1 Gbps in the frequency ranges from 3.1 to 10.6 GHz, an analog-to-digital (A/D) converter should operate at very high sampling rate F s  so that UWB communication receiver can implement in a digital domain. Usually, the sampling rate F s  must be greater than two-time the highest frequency F max  in the ultra-short pulse signals. This may lead to have a difficult problem to design an A/D converter with such high-speed operation in an UWB communication transceiver.  
           [0007]    In addition, digital down conversion (DDC) should shift the bandpass ultra-shout pulse signals of the output of the A/D converter into the baseband signals and perform the decimation of the baseband signals with high sampling rate into low sampling rate due to the repeated pulse signals during transmitting.  
           [0008]    Thus, there is a continuing need for a scalable A/D converter with operating at very high-speed along with a digital down conversion for a digital UWB communication device.  
         SUMMARY  
         [0009]    In accordance with one aspect, a scalable A/D converter for UWB communication transceiver may include an analyzed sequence switch, a synthesized sequence switch, a set of A/D converters, a set of fine-adjustable attenuations, and a set of digital FIR filters, with operating in parallel.  
           [0010]    Other aspects are set forth in the accompanying detailed description and claims. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]    [0011]FIG. 1 is a block diagram of showing one embodiment of an UWB communication transceiver in accordance with the present invention;  
         [0012]    [0012]FIG. 2 is a block diagram of showing a transmitter section of the UWB communication transceiver as shown in FIG. 1;  
         [0013]    [0013]FIG. 3 is a block diagram of the receiver section of the UWB communication transceiver as shown in FIG. 1;  
         [0014]    [0014]FIG. 4 is a block diagram of showing one embodiment of the present invention, including an analyzed sequence switch, a synthesized sequence switch, a set of A/D converters, a set of fine-adjustable attenuations, and a set of digital FIR filters, with operating in parallel;  
         [0015]    [0015]FIG. 5 is a block diagram of showing one embodiment of the present invention, including an analyzed sequence switch, a synthesized sequence switch, a set of A/D converters, a set of fine-adjustable attenuations, with operating in parallel, and one Mth-band digital FIR filter;  
         [0016]    [0016]FIG. 6 is a block diagram of showing one embodiment of the present invention, including a complex multiplier, a complex oscillator, a decimation lowpass FIR filter H N (z), a down sampling N selector, a clock control, and a set of down sampling with a selectable MUX function;  
         [0017]    [0017]FIG. 7 is a block diagram of showing one embodiment of the present invention, including a complex multiplier, a complex oscillator, a decimation lowpass FIR filter H D (z), a down sampling N selector, a clock control, and a set of down sampling with a selectable MUX function; FIG. 7 has the exact output comparing with the output as shown in FIG. 6, but the present invention as shown in FIG. 7 is different from the present invention in FIG. 6. 
     
    
     DETAILED DESCRIPTION  
       [0018]    Referring to FIG. 1, an UWB communication transceiver  8  in accordance with one embodiment of the present invention includes a low-noise amplifier (LNA) and power amplifier (PA) section  10 , which is coupled to transmitting and receiving antennas. The low-noise amplifier/power amplifier section  10  is coupled to an A/D and D/A converter section  12 . The A/D and D/A converter section  12  is coupled to the digital signal processing section  14 . The digital signal processing section  14  is coupled to a network interface section  16 . The network interface  16  interfaces with Ethernet network  18 . In accordance with one embodiment of the present invention, the system  8  is a so-called ultra wideband communication transceiver that both transmits and receives speech, audio, image, and video and data information by using a sequence of the ultra-short pulses.  
         [0019]    A dedicated physical channel of showing transmitter in the UWB communication transceiver, as shown in FIG. 2, receives dedicated physical data channel  20  user data bits, such as information data at 1 Gbps. The information data  20  is passed through a one-second-rate convolution encoder  22  that may produce the double data rate of 2 giga-symbols per second (Gsps) by adding redundancy. The data is then interleaved and produced 2 Gsps by using a block interleaver  24 . Thus, the output data symbols from the block interleaver  24  are modulated by using a pulse position modulation (PPM)  26 , which is able to produce eight digital Gaussian-monocycle pulses based on one symbol data. The PPM technique  26  is to assign a time-window, and shift the position of the Gaussian-monocycle pulses within the window in time. The sequence generator  28  is a time-hopping encoding sequence generator. Using the sequence generator  28  and the clock control  32  controls the pulse generator  30  to produce the ultra-short Gaussian monocycle pulses and the pulse position in time for the PPM technique  26 . The output ultra-short Gaussian-monocycle pulses from the PPM  26  are then passed through the pulse-shaping digital FIR filter  34  to create the frequency spectrum of the pulses in which can meet the FCC&#39;s requirements. Then, the output pulses from the pulse-shaping digital FIR filter  34  are used for the digital-to-analog (D/A) converter  36 , which is operated at the sampling frequency of 22 gigahertz (GHz). The analog reconstruct filter  38 , which is a bandpass filter, is used for reconstructing the analog ultra-short pulse signals. Thus, the analog pulse signals from the output of the analog reconstruct filter  38  is passed the power amplifier  40  through an antenna into air.  
         [0020]    The transmitter in an UWB communication transceiver, as shown in FIG. 2, can also transmit the dedicated physical data channel  20  user data bits with scalability, such as information data of 50 Mbps, 100 Mbps, 200 Mbps, 250 Mbps, and 500 Mbps. In these cases, the PPM  26  produces 160, 80, 40, 32, 16 ultra-short Gaussian-monocycle pulses based on one symbol data for the information data of 50 Mbps, 100 Mbps, 200 Mbps, 250 Mbps, and 500 Mbps, respectively.  
         [0021]    Referring to FIG. 3, which is the dedicated physical channel of showing the receiver in an UWB communication transceiver, the LNA  50  receives the ultra-short Gaussian-monocycle pulses from an antenna. The analog signals are passed through the analog anti-aliasing filter  52 , which is a bandpass filter. The bandlimited analog signals are then sampled and quantized by using an A/D converter  54 , with the sampling rate at 22 GHz. The digital bandpass signals of the output of the A/D converter  54  are then shifted into the baseband signals with down sampling by eight by using the digital down conversion (DDC)  56 . Thus, the DDC  56  produces the digital data of 2 Gsps. Both the A/D converter  54  and the DDC  56  are controlled by the clock control  64 . The output data from the DDC  56  is used for the channel estimate  62 , and the rake receiver  58 . The channel estimate  62  is used to estimate the channel phase and frequency that are passed into the rake receiver  58 . The rake receiver  58  calculates the correlation between the received ultra-short pulses and the template pulses, which are generated by using the template pulse generator  66 , and performs coherent combination. The template pulse generator  66  is controlled by three functions: clock control  64 , sequence generator  68 , and synchronization  70 . The output of the rake receiver  58  is passed through the block de-interleaver  60 . Thus, the output data of the block de-interleaver is used for the Viterbi decoder  72  to decode the encoded data and produce the information data of 1 Gbps.  
         [0022]    The receiver in an UWB communication transceiver, as shown in FIG. 3, can also receive the symbol data with scalability to produce the information data of 50 Mbps, 100 Mbps, 200 Mbps, 250 Mbps, and 500 Mbps. In these cases, the DDC  56  has to shift the bandpass ultra-short pulse signals into baseband signals, and performs the down sampling by a factor of 160, 80, 40, 32, and 16, respectively.  
         [0023]    An effective flexibility and scalability analog-to-digital converter, as shown in FIG. 4, which may be used to simultaneously, substitutes a very-high-speed A/D converter  54  in FIG. 3. The scalable A/D converter  54 , shown in FIG. 4, contains forty low-speed A/D converters  86   a - 86 M, forty fine-adjustable attenuations  88   a - 88 M, forty digital FIR filters  90   a - 90 M, with operating in parallel, as well as one analyzed sequence switch  80 ,  82 ,  84 , and one synthesized sequence switch  92 ,  94 ,  96 .  
         [0024]    The scalable A/D converter  54 , shown in FIG. 4, is to first decompose the analog bandpass signals into subband signals by using the analyzed sequence switch  80 ,  82 ,  84 . The analyzed sequence switch  80 ,  82 ,  84  is a counterclockwise commutator-model circuit that is equivalent to polyphase implementation for downsampling. The analyzed sequence switch  80 ,  82 ,  84  rotates at uniform speed and takes on the forty positions in the way as shown in FIG. 4. The analog bandpass signals are achieved the downsampling of forty for each branch by using the analyzed sequence switch  80 ,  82 ,  84 , and sampled by forty low-speed A/D converters  86   a - 86 M in parallel. Each one of low-speed A/D converters  86   a - 86 M is sampled at a sampling rate of 550 MHz with 8-bit resolution. Thus, these analog bandpass signals are converted into the digital subband signals, with non-overlapping frequency bands of bandwidth F s / 40 . The digital subband signals are parallel passed through the forty fine-adjustable attenuations  88   a - 88 M, and forty digital FIR filters  90   a - 90 M. Then these digital subband signals are sequentially rotated for polyphase implementation of upsampling by using the synthesized sequence switch  92 ,  94 ,  96  to recover the desired sampling rate F s  and to obtain the digitally reconstructed signals.  
         [0025]    The forty fine-adjustable attenuations  88   a - 88 M are used for eliminating the gain error of the scalable A/D converters due to the mismatch problem among the forty A/D converters  86   a - 86 M, and for reducing the narrow interference as well due to other radio operation within the frequency band from 3.1 GH to 10.6 GHz.  
         [0026]    As shown in FIG. 4, the fine-adjustable attenuations A k  (k=0, 1, 2, . . . 40)  88   a - 88 M are mainly used to compensate and reduce the gain error among all of the A/D converters  86   a - 86 M since all of the A/D converters  86   a - 86 M are not exactly equal in practical implementation.  
         [0027]    For the digital filter bank R k (z), (where k=0, 1, 2, . . . 40),  90   a - 90 M, as shown in FIG. 4, the z-transform function {circumflex over (X)}(z) is expressed in terms of X(z) as follows:  
                   X   ^          (   z   )       =       (       z     -     (     M   -   1     )         M     )          (       ∑     i   =   0       M   -   1                       X        (     z                   W   M   i       )         )          (       ∑     k   =   0       M   -   1                R   k          (     z   M     )            W   M       -   k                   i           )         ,           (   1   )                               
 
         [0028]    where W M =e −j2π/M . So, the scalable A/D converter system  54  in FIG. 4 is alias-free if and only if,  
                 (       ∑     k   =   0       M   -   1                R   k          (     z   M     )            W   M       -   k                   i           )     =   0     ,     1   ≤   i   ≤     M   -   1.               (   2   )                               
 
         [0029]    Because of W M W M *=MI, equation (2) can be rewritten as  
               [             R   0          (   z   )                   R   1          (   z   )               ⋮               R     M   -   1            (   z   )             ]     =         W   M          [           R        (   z   )               0           ⋮           0         ]       .             (   3   )                               
 
         [0030]    This implies that the scalable A/D converter system  54  is aliasing free if  
           R   k ( z )= R ( z ), for all of  k.    (4)  
         [0031]    Thus, under the condition of equation (4), the z-transform function {circumflex over (X)}(z) in FIG. 4 is given by  
           {circumflex over (X)} ( z )= z   −(M−1)   R ( z   M ) X ( z ),   (5)  
         [0032]    where R(z M ) is a Mth-band digital FIR filter of R(z). Thus, for the scalable A/D converter  54  as shown in FIG. 4, the aliasing is completely canceled. However, this scalable A/D converter system  54  has amplitude distortion  
           T ( z )= z   −(M−1)   R ( z   M ).   (6)  
         [0033]    The amplitude distortion can also be canceled if the filter R(z M ) is one allpass filter. The scalable A/D converter system  54  does not have phase distortion since the digital filter R(z) is a FIR filter with a linear phase. In addition, the FIR filter R(z) is able to eliminate the narrow interference of other radio operations within each branch of the scalable A/D converter  54  in FIG. 4.  
         [0034]    In accordance with another embodiment of the present invention, instead of using the forty digital FIR filters  90   a - 96 M with operating in parallel for the scalable A/D converter in FIG. 4, another present invention of this scalable A/D converter system  54 , as shown in FIG. 5, uses only one digital FIR filter H(z M )  116  after the synthesized sequence switch  110 ,  112 ,  114 . Thus, memory of the filter coefficients  116  can be used in a minimum size. The architecture of the scalable A/D converter  54  can be simplified. The power consumption of the scalable A/D converter  54  can be reduced. This scalable A/D converter system  54  is also aliasing free, no phase distortion, but has amplitude distortion as shown in equation (6). This scalable A/D converter system  54  is also able to eliminate the narrow interference within each branch by using the Mth-band digital FIR filter H(z M )  116 .  
         [0035]    Referring to FIG. 6, one embodiment of the present invention is called the digital down conversion (DDC)  56 . The DDC  56  works by first shifting the ultra wideband signals with a frequency range from 3.1 GHz to 10.6 GHz of interest to baseband signals by using the complex multiplying  120  the received signals of the scalable A/D converter  54  by a complex oscillator  122 . The baseband signals of output of the complex multiplier  120  are passed through the decimation lowpass FIR filter H N (z)  124 , which is controlled by the clock control  128  and is selected one of the down sampling N (N=8, 16, 32, 40, 80, 160) for the filter cutoff frequency by using the down sampling N selector  126 . The output signals from the decimation lowpass FIR filter H N (z)  124  are then passed one of the down sampling blocks  130   a - 130   g  through the selectable MUX  132 , which is controlled by the clock control  128  and the down sampling N selector  126 . Thus, the selectable MUX  132  produces one of the data rates of 1 Gbps, 500 Mbps, 250 Mbps, 200 Mbps, 100 Mbps, 50 Mbps based on the down sampling blocks  130   b,    130   c,    130   d,    130   e,    130   f,    130   g,  respectively.  
         [0036]    In accordance with another embodiment of the present invention  56 , shown in FIG. 7, the down sampling blocks  144   a - 144   g  in the DDC  56  are implemented before the decimation lowpass filter FIR filter H D (z)  152 , which is designed to be a Nth-band decimation lowpass FIR filter H D (Z N ). Thus, the operation of the decimation lowpass filter FIR filter H D (z)  152  is based on the low sampling rate to achieve the efficient implementation.  
         [0037]    Referring to FIG. 7, one embodiment of the present invention of the DDC  56  operates by first shifting the interested ultra wideband (3.1 GHz to 10.6 GHz) to the baseband signals by using the complex multiplying  140  the received signals of the scalable A/D converter  54  by a complex oscillator  142 . The output baseband signals of the complex multiplier  140  are passed one of the down sampling blocks  144   a - 144   g  through the selectable MUX  146 . The selectable MUX  146  is controlled by the clock control  150  and the down sampling N selector  148  for selecting one down sampling rate N, (including N=8, 16, 32, 40, 80, 160). Then, the output signals of the selectable MUX  146  are passed through the decimation lowpass FIR filter H D (z)  152  to produce one of the band-limited signal with the data rates of 1 Gbps, 500 Mbps, 250 Mbps, 200 Mbps, 100 Mbps, 50 Mbps based on the down sampling blocks  144   b,    144   c,    144   d,    144   e,    144   f,    144   g,  respectively.  
         [0038]    While the present inventions have been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of these present inventions.