Abstract:
A method for processing enhanced dedicated channel data in a wireless transmit/receive unit is described. An interrupt message is received at a medium access control (MAC) layer. The interrupt message is processed by the MAC layer, including at least one of: performing grant processing, on a condition that a grant is included in the interrupt message; obtaining buffer occupancy information; performing transport format combination recovery and elimination; generating a rate request; or multiplexing multiple protocol data units (PDUs) into a single MAC-e PDU.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation of U.S. patent application Ser. No. 13/046,050, filed Mar. 11, 2011, which is a continuation of U.S. patent application Ser. No. 11/471,402, filed Jun. 19, 2006, now U.S. Pat. No. 7,916,751, issued Mar. 29, 2011, which claims the benefit of U.S. Provisional Patent Application No. 60/692,473, filed Jun. 21, 2005, which are all incorporated by reference as if fully set forth herein. 
     
    
     FIELD OF INVENTION 
       [0002]    The present invention is related to a wireless communication system. More particularly, the present invention is related to a method and apparatus for efficient operation of an enhanced dedicated channel (E-DCH). 
       BACKGROUND 
       [0003]    Methods for improving uplink (UL) coverage, throughput and transmission latency are being investigated in Release 6 (R6) of the 3rd Generation Partnership Project (3GPP). In order to successfully implement these methods, scheduling and assigning of UL physical resources have been moved from a radio network controller (RNC) to a Node-B such that the Node-B can make decisions and manage UL radio resources on a short-term basis more efficiently than the RNC, even if the RNC retains overall control over the Node-B. 
         [0004]      FIG. 1  is a block diagram of a conventional wireless communication system  100  configured in accordance with the present invention. The system  100  comprises a wireless transmit/receive unit (WTRU)  102 , a Node-B  104  and an RNC  106 . The RNC  106  controls overall enhanced uplink (EU) operation by configuring EU parameters for the Node-B  104  and the WTRU  102  such as initial transmit power level, maximum allowed EU transmit power or available channel resources per Node-B. Between the WTRU  102  and the Node-B  104 , an E-DCH  108 , a UL EU signaling channel  110  and a DL EU signaling channel  112  are established for supporting EU operations. 
         [0005]    For E-DCH transmissions, the WTRU  102  sends a rate request to the Node-B  104  via the UL EU signaling channel  110 . In response, the Node-B  104  sends a rate grant to the WTRU  102  via the DL EU signaling channel  112 . After EU radio resources are allocated for the WTRU  102 , the WTRU  102  transmits E-DCH data via the E-DCH  108 . In response to the E-DCH transmissions, the Node-B  104  sends an acknowledgement (ACK) or non-acknowledgement (NACK) message for hybrid automatic repeat request (H-ARQ) operation via the DL EU signaling channel  112 . The Node-B  104  may also respond with rate grants to the WTRU  102  in response to E-DCH data transmissions. 
         [0006]      FIG. 2  is a block diagram of conventional protocol architecture of the WTRU  102 . The protocol architecture of the WTRU  102  includes higher layers  202 , a radio link control (RLC) layer  204 , a medium access control (MAC) layer  206  and a physical layer (PHY)  208 . The MAC layer  206  includes a dedicated channel MAC (MAC-d)  210  and an E-DCH MAC (MAC-e/es)  212 . The MAC-e/es  212  handles all functions related to the transmission and reception of an E-DCH including, but not limited to, H-ARQ transmissions and retransmissions, priority of data, MAC-d/MAC-es multiplexing and transport format combination (TFC) selection. 
         [0007]    One or more independent UL transmissions are processed on an E-DCH between a WTRU and a universal mobile telecommunication system (UMTS) terrestrial radio access network (UTRAN) within a common time interval. One example of this would be a MAC layer H-ARQ or a simple MAC layer automatic repeat request (ARQ) operation, where each individual transmission may require a different number of retransmissions to be successfully received by the UTRAN. This operation may result in a loss of transmission sequence at the MAC layer. 
         [0008]    In accordance with the 3GPP standards, the transmission time interval (TTI) for the E-DCH is set to either 10 ms or 2 ms. In order to achieve a higher data rate and throughout, the operations of the E-DCH at the WTRU should be carefully designed to accommodate the required timing. 
       SUMMARY 
       [0009]    Some embodiments provide a method for processing enhanced dedicated channel data in a wireless transmit/receive unit is described. An interrupt message is received at a medium access control (MAC) layer. The interrupt message is processed by the MAC layer, including at least one of: performing grant processing, on a condition that a grant is included in the interrupt message; obtaining buffer occupancy information; performing transport format combination recovery and elimination; generating a rate request; or multiplexing multiple protocol data units (PDUs) into a single MAC-e PDU. 
         [0010]    Some embodiments provide a wireless transmit/receive unit for processing enhanced dedicated channel data, including a medium access control (MAC) layer. The MAC layer is configured to receive an interrupt message and process the interrupt message. Processing the interrupt message includes at least one of: performing grant processing, on a condition that a grant is included in the interrupt message; obtaining buffer occupancy information; performing transport format combination recovery and elimination; generating a rate request; or multiplexing multiple protocol data units (PDUs) into a single MAC-e PDU. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a block diagram of a conventional wireless communication system configured in accordance with the present invention; 
           [0012]      FIG. 2  is a block diagram of conventional protocol architecture of a WTRU utilized in accordance with the present invention; 
           [0013]      FIG. 3  is a block diagram of a WTRU including the PDU processor in accordance with the present invention; 
           [0014]      FIG. 4  is a signaling diagram of a process for efficient operation of an E-DCH in accordance with a first embodiment of the present invention; and 
           [0015]      FIG. 5  is a signaling diagram of a process for efficient operation of an E-DCH in accordance with a second embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0016]    Hereafter, the terminology “WTRU” includes, but is not limited to, a user equipment, a mobile station, a fixed or mobile subscriber unit, a pager, or any other type of device capable of operating in a wireless environment. When referred to hereafter, the terminology “Node-B” includes but is not limited to a base station, a site controller, an access point or any other type of interfacing device in a wireless environment. 
         [0017]    The present invention provides functional partitioning and interaction between software and hardware entities of E-DCH operations at the WTRU. The present invention is applicable to any type of wireless communication systems including, but not limited to, UMTS frequency division duplex (FDD), time division duplex (TDD) and time division synchronous code division multiple access (TD-SCDMA) systems. 
         [0018]    The features of the present invention may be incorporated into an integrated circuit (IC) or be configured in a circuit comprising a multitude of interconnecting components. 
         [0019]    In accordance with the present invention, a WTRU  102  may include an optional protocol data unit (PDU) processor  310  (i.e., protocol engine) for processing data.  FIG. 3  is a block diagram of the WTRU  102  including the PDU processor  310  in accordance with the present invention. The WTRU  102  includes a stack processor  302 , an L1 processor  304 , a stack memory  306 , an L1 memory  308  and a PDU processor  310 . The L1 processor  304  primarily executes physical layer software (mostly control processing and potentially some signal processing). The L1 processor  304  may also run certain MAC tasks, such as control related to H-ARQ for high speed downlink packet access (HSDPA) or high speed uplink packet access (HSUPA) and some RLC tasks. The stack processor  302  primarily runs the rest of the protocol stack operations. The stack processor  302  may also be used as an application processor. The stack processor  302  and the L1 processor  304  each have their own memory (the stack memory  306  and the L1 memory  308 , respectively). In a conventional implementation, a significant number of cycles are wasted for re-packaging data as the data is moved through the stack (e.g., concatenation and separation of PDUs, adding headers, ciphering, or the like). 
         [0020]    The PDU processor  310  runs parallel to the stack processor  302  and the L1 processor  304 . The PDU processor  310  is a programmable entity used primarily for moving data between L1 memory  308  and the stack memory  306 . The PDU processor  310  also performs data packet fragmentation/de-fragmentation, composition/de-composition and ciphering/de-ciphering as it moves the data. Optionally, the PDU processor  310  may also be capable of building and interpreting the RLC and MAC PDU headers. 
         [0021]    The PDU processor  310  has specific instructions for manipulating incoming and outgoing bit streams. These instructions reduce the overhead of interpreting bit fields that make up headers or constructing a sequence of bit fields during the generation of headers. The PDU processor  310  builds MAC-e/es PDUs directly from a set of PDU descriptors. The PDU descriptors are a set of shared data structures that describe RLC PDUs and MAC-e/es PDUs (i.e., contents of data and PDU headers) in a software friendly format (e.g., byte/word accessible data for fast processing with no bit shifting). The PDU processor  310  builds the MAC-e/es PDU based on the PDU descriptors as the MAC-e/es PDU is written into a physical layer shared memory (i.e., L1 memory  308 ) for transmission. The advantage of this scheme is significant reduction of L2/3 processing and parallel processing of protocol stack operation. Frame asynchronous operations are not blocked due to frame synchronous PDU construction processing and L2/3 processing is offloaded to the PDU processor. 
         [0022]    It should be noted that  FIG. 3  is provided as an example and any variations are possible. For example, a single processor incorporating the L1 processor  304  and the stack processor  302  may be used, and the stack memory  306  and the L1 memory  308  may be the same memory or different memories either on or off the same integrated circuit. 
         [0023]    Physical layer processing is typically performed by hardware or mixed hardware/software components. The physical layer processing for HSUPA includes, but is not limited to, turbo encoding, rate matching, interleaving and H-ARQ processing to implement data re-transmission. The physical layer processing includes computation of various control parameters (for example, a specific puncturing pattern) followed by actual processing of the data. In the prior art, these operations in the physical layer can be commenced only after the MAC-e processing is complete. 
         [0024]    In accordance with the present invention, the computation of the control parameters is performed asynchronously from the associated data operation. For example, it can be performed in advance even while the data is still in the RLC layer  204 . This enables the latency constraint on making the data available to be significantly relaxed and allows an additional slot of latency in the processing. The MAC layer  206  provides information needed for computation of the control parameters to the physical layer as early as possible, while the data is being processed in parallel. It should be noted that the ability to do so does not depend on the PDU processor  310  being utilized. 
         [0025]      FIG. 4  is a signaling diagram of a process  400  implemented in the WTRU  102  for efficient operation of an E-DCH in accordance with a first embodiment of the present invention. In accordance with the first embodiment, E-DCH operations are implemented with the PDU processor  214 . MAC layer processing is triggered by an interrupt message (or primitive) sent by the physical layer  208  (step  402 ). The MAC layer processing may be triggered at each transmission time interval (TTI) for which an H-ARQ process is available for transmission, each TTI that new scheduling grant information is received, or every E-DCH TTI. 
         [0026]    The physical layer  208  generates the interrupt message when an H-ARQ process is available for an upcoming TTI. Availability of a particular H-ARQ process is determined when the physical layer  208  receives an ACK for a previous H-ARQ transmission via the H-ARQ process, when the maximum number of retransmissions for the H-ARQ process has reached so that the H-ARQ process is released, or when the H-ARQ process was not used in the previous TTI. The physical layer  208  may also generate the interrupt message when the WTRU  102  receives updated scheduling grant information from the Node-B  104 . The interrupt message may be a TTI based clock interrupt. 
         [0027]    The interrupt message contains several information elements including, but not limited to, 1) an absolute grant with indication if received with a primary or secondary enhanced uplink radio network temporary identity (E-RNTI); 2) a relative grant(s) from serving and non-serving cells; 3) an H-ARQ indicator (HI) of previous transmissions; 4) a current dedicated physical control channel (DPCCH) power; or 5) clock interrupt. 
         [0028]    Upon being invoked by the physical layer  208 , the MAC layer  206  performs several tasks. The MAC layer  206  performs grant processing in accordance with the updated scheduling grant information, if provided, including an absolute grant and relative grants to derive current scheduling grant and corresponding remaining transmit power for E-DCH transmission (step  404 ). The MAC layer  206  also obtains buffer occupancy (step  406 ). The buffer occupancy may be obtained using a function call to the PDU processor  214 , as shown by steps  406  and  408 , if the PDU processor  214  and the MAC layer  206  share a memory between them. At such point, any RLC asynchronized tasks (such as timer processing, control PDUs processing, or the like) are blocked to maintain buffer occupancy consistency. The MAC layer  206  performs a transport format combination (TFC) recovery and elimination process to determine E-DCH TFCs that are allowed with the remaining transmit power for E-DCH (step  410 ). The MAC layer  206  may also generate a rate request to request a resource from the Node-B  104  (step  412 ). The MAC layer  206  may also perform a multiplexing procedure for multiplexing multiple MAC-d PDUs into MAC-es PDUs and one or multiple MAC-es PDUs into a single MAC-e PDU (step  414 ). The foregoing description of the MAC layer tasks of steps  404 - 414  may be performed in different order or simultaneously and not all the tasks may be necessary. 
         [0029]    The MAC layer  206  then sends a message to the physical layer  208  to enable the physical layer  208  to calculate control parameters while the data is being processed by other entities, such as the MAC layer  206 , the PDU processor  214  or the RLC layer  204  (step  416 ). The message includes an H-ARQ profile, a transport block (TB) size, a power offset, or the like. The H-ARQ profile indicates a power offset attributes and a maximum number of retransmissions for H-ARQ processes. By sending this message to the physical layer  208  before MAC-e processing is complete, the latency constraint can be significantly relaxed. The processing delay up to step  416  is the MAC layer processing delay and should be less than a certain delay limit (e.g., 1.7 ms). 
         [0030]    The MAC layer  206  then sends a message (or a primitive) (i.e., UMAC status indicator and MAC-e/es descriptor) to request the PDU processor  214  to build a MAC-e PDU (step  418 ). The message (or primitive) includes the number and size of required RLC PDUs for each logical channel and MAC-e/es descriptor(s) defining the multiplexing of the MAC-e/es PDU. 
         [0031]    Upon receiving the message (or a primitive) from the MAC layer  206 , the PDU processor  214  updates buffer occupancy accordingly (step  420 ). At such time, the blocking of RLC asynchronized task (such as timer processing, control PDUs processing, or the like) is removed. The PDU processor  214  then moves the data to the physical layer  208  or, alternatively, builds a MAC-e PDU while moving the data from the stack memory  306  to the L1 memory  308  (step  422 ). The PDU processor  214  builds RLC PDUs including the RLC headers according to the PDU number and size requested by the MAC layer  206 . The PDU processor  214  also builds a MAC-e header and a MAC-es header and corresponding MAC-es PDUs and a MAC-e PDU based on the MAC-e/es descriptor. The PDU processor  214  also sets up RLC PDU specific timers and state variables. 
         [0032]    The PDU processor  214  may send a finish confirmation message (or primitive) to the physical layer  208  (step  424 ). Alternatively, this may be implicitly known to the physical layer  208  by the reception of the MAC-e PDU. The PDU processor  214  then sends a data transmit indication message (or primitive) to the RLC layer  204  (step  426 ). Upon receiving this transmit indication message, the RLC layer  204  may process state variables, timers, or the like, if blocked during the data transfer (step  428 ). The RLC layer  204  then updates buffer occupancy accordingly (step  430 ). 
         [0033]    The delay between the UMAC status indicator at step  418  and the MAC-e PDU generation at step  424  is the RLC layer and PDU processor processing delay. The sum of the RLC layer and PDU processor processing delay and the MAC processing delay should be limited to a reasonable delay limit (e.g., 2.37 ms). In order to avoid parallel processing, the maximum delay limit may be reduced to a period less than 2 ms. Otherwise, parallel processing may be allowed. 
         [0034]      FIG. 5  is a signaling diagram of a process  500  implemented in the WTRU  102  for efficient operation of an E-DCH in accordance with a second embodiment of the present invention. In accordance with the second embodiment, the present invention is implemented without a PDU processor. The MAC layer  206  preferably runs at least each TTI for which an H-ARQ process is available for transmission and/or for each TTI new scheduling grant information is received. Alternatively, the MAC layer  206  may run at every E-DCH TTI. MAC layer processing is triggered by an interrupt message (or primitive) sent by the physical layer  208  (step  502 ). The interrupt from the physical layer  208  may be based on one or more of the events enumerated hereinbefore with respect to the first embodiment. 
         [0035]    Upon being invoked by the physical layer  208 , the MAC layer  206  performs several tasks. The MAC layer  206  performs grant processing in accordance with updated scheduling grants, if provided, including absolute grants and relative grants to derive current scheduling grant and corresponding remaining transmit power for E-DCH transmission (step  504 ). The MAC layer  206  also obtains buffer occupancy information by sending a function call to the RLC layer  204  (step  506 ). The RLC layer  204  calculates buffer occupancy and returns it to the MAC layer  206  (step  508 ). The MAC layer  206  performs a TFC recovery and elimination process to determine E-DCH TFCs that are allowed with the remaining transmit power for E-DCH (step  510 ). The MAC layer  206  may also generate a rate request to request resources from the Node-B  104  (step  512 ). The MAC layer  206  performs a multiplexing procedure for multiplexing multiple MAC-d PDUs into MAC-es PDUs and one or multiple MAC-es PDUs into a single MAC-e PDU (step  514 ). The foregoing description of the MAC layer tasks at steps  504 - 514  may be performed in different order or simultaneously and not all the tasks may be necessary. 
         [0036]    The MAC layer  206  then sends a message including an H-ARQ profile, a TB size, a power offset, or the like to the physical layer  208  (step  516 ). By sending this message to the physical layer  208  before MAC-e processing is complete, the latency constraint can be significantly relaxed. The processing delay up to step  516  is part of the overall MAC processing delay, denoted as “MAC processing delay part 1”, and should be less than a certain delay limit (e.g., 1.7 ms). 
         [0037]    The MAC layer  206  requests data from the RLC layer  204  by sending a UMAC status indicator (step  518 ). With the UMAC status indicator, the RLC layer  204  is notified about the size of required RLC PDUs. Upon receiving the UMAC status indicator from the MAC layer  206 , the RLC layer  204  processes state variables, timers, or the like (step  520 ). The RLC layer  204  builds RLC PDUs including RLC headers according to the PDU number and size requested by the MAC layer  206  (step  522 ). The RLC layer  204  then updates buffer occupancy accordingly (step  524 ). 
         [0038]    The RLC layer  204  then sends the RLC PDUs to the MAC layer  206  (step  526 ). The delay between the message at step  516  and the message at step  526  is the RLC processing delay. Upon receiving the RLC PDUs, the MAC layer  206  builds MAC-es headers and a MAC-e header and builds corresponding MAC-es PDUs and MAC-e PDU (step  528 ). The MAC layer  206  then sends the MAC-e PDU to the physical layer  208  (step  530 ). The delay between step  526  and step  530  is part of the overall MAC processing delay as denoted “MAC processing delay part 2.” 
         [0039]    The sum of the RLC processing delay and MAC processing delay should be limited to a reasonable delay limit (e.g., 2.37 ms). In order to avoid parallel processing, the maximum delay limit may be reduced to a period less than 2 ms. Otherwise, a parallel processing may be allowed. 
         [0040]    Although the features and elements are described in particular combinations, each feature or element may be used alone without the other features and elements or in various combinations with or without other features and elements.