Abstract:
A method for forming a capacitor by stacking impurity-doped polysilicon layers having different concentrations to form a bottom electrode, treating surfaces of the bottom electrode to prevent a low dielectric constant material from being generated on the surface of the bottom electrode, and forming a dielectric layer and a top electrode on the bottom electrode.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to a method for forming a semiconductor capacitor and, more particularly, to a capacitor in a metal insulator silicon (MIS) structure.  
         DESCRIPTION OF THE PRIOR ART  
         [0002]    Recently, a Ta 2 O 2  layer has been used as a dielectric layer of a capacitor. A Ta 2 O 2  material of a high dielectric constant has been substituted for a nitride oxide (NO) material in forming a semiconductor capacitor.  
           [0003]    [0003]FIG. 1 is a cross-sectional view illustrating a conventional capacitor in a metal insulator silicon (hereinafter, referred to as a MIS) structure. A polysilicon layer is used as a bottom electrode of a semiconductor capacitor for a storage electrode  11 , a metal layer is used as a top electrode for a plate electrode  13  and a Ta 2 O 2  layer is used as a dielectric layer  12  between the storage electrode  11  and the plate electrode  13 . As stated above, in the MIS structure, the polysilicon and metal layers are respectively used as the storage electrode  11  and the plate electrode  13  to overcome some difficulties in the metal electrode etching process and junction in a polysilicon substrate  10 .  
           [0004]    However, in the MIS structure, due to a work function gap and a resistance between the storage electrode and the plate electrode, electric characteristics of the capacitor have a lot of polarity according to a bias. That is, if a plus bias is applied to the storage electrode, a depletion layer to decrease the capacitance thereof is formed in the surface between the Ta 2 O 5  layer and the storage electrode because the polysilicon layer is used as the storage electrode. Since the metal electrode has a larger work function than that of the polysilicon electrode in leakage current, when a bias is applied to the plate electrode, electric characteristics of leakage current and an insulation destroying voltage deteriorate.  
           [0005]    The decrease of capacitance, which is caused by the depletion layer, may be prevented by a high doping concentration in the polysilicon layer for the storage electrode. However, it is difficult to increase concentration of P more than 5×10 20 /cm 3  based on the conventional doped polysilicon deposition. Further, an excessive injection of PH 3  into a reaction chamber to obtain a concentration of 1×10 21 /cm 3  decreases the deposition rate, so a sufficient thickness of 200 Å or more may not be obtained and particles from anti-reacting sources causing an allied nuclei reaction may be generated.  
           [0006]    Also, if a Ta 2 O 2  layer is deposited on the storage electrode, a low dielectric constant layer, SiO 2 , is formed on the polysilicon so that the capacitance of the capacitor is decreased.  
           [0007]    To compensate for the above problems, a meta stable polysilicon (MPS) layer is employed on the storage electrode, but a low P concentration of the storage electrode is needed for the use of such a layer and, since the result is capacitance, then a capacitance difference to the bias, ? C, becomes greater. As described above, to use the MPS layer to increase the size of the capacitor, the P concentration of the storage electrode may be kept lower than 1×10 20 /cm 3  and the capacitance decrease caused by the depletion layer has an amount of 15%˜30% compared to that with no depletion layer.  
           [0008]    On the other hand, although a metal insulator metal (MIM) structure is also used, which uses the same metal layers in the storage electrode and the plate electrode, there are many difficulties in forming a storage electrode pattern.  
         SUMMARY OF THE INVENTION  
         [0009]    It is, therefore, an object of the present invention to provide a method for forming a semiconductor capacitor which prevents the generation of a low dielectric constant layer and a capacitance decrease by a depletion layer and provides a capacitor with a high quality degree of integration.  
           [0010]    In accordance with an aspect of the present invention, there is provided a method for forming a capacitor, the method comprising steps of a) stacking impurity-doped polysilicon layers which have a different concentration, thereby forming a bottom electrode; b) treating surfaces of the bottom electrode for preventing a low dielectric constant material from being generated on the surface of the bottom electrode; and c) forming a dielectric layer and a top electrode on the bottom electrode. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]    The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which:  
         [0012]    [0012]FIG. 1 is a cross-sectional view illustrating a conventional capacitor manufacturing method;  
         [0013]    [0013]FIG. 2 is a cross-sectional view illustrating a capacitor manufacturing method in accordance with the present invention;  
         [0014]    [0014]FIG. 3 is a cross-sectional view showing a structure of a multi polysilicon layer of FIG. 2 in accordance with a first embodiment of the present invention;  
         [0015]    [0015]FIG. 4 is a cross-sectional view showing a structure of a multi polysilicon layer of FIG. 2 in accordance with a second embodiment of the present invention; and  
         [0016]    [0016]FIG. 5 is a cross-sectional view showing a structure of a multi polysilicon layer of FIG. 2 in accordance with a third embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0017]    Hereinafter, a semiconductor capacitor according to the present invention will be described in detail referring to the accompanying drawings.  
         [0018]    First, FIG. 2 is a cross-sectional view illustrating a capacitor manufacturing method in accordance with the present invention. As shown in FIG. 2, a storage electrode  22  which is a bottom electrode is formed on a semiconductor substrate  21 , a Ta 2 O 6  layer and a TaON layer are formed on the storage electrode  22  as a dielectric layer  23 , and a plate electrode  24  which is a top electrode is formed on the dielectric layer  23 . Here, the storage electrode  22  is formed with a multi polysilicon layer and the plate electrode  24  uses a metal layer, thereby forming a capacitor with the MIS structure.  
         [0019]    [0019]FIG. 3 is a cross-sectional view showing a structure of the multi polysilicon layer of FIG. 2 in accordance with a first embodiment of the present invention. A doped polysilicon layer having a plurality of polysilicon layers is deposited as the storage electrode  22 . First polysilicon layers  25   a,    25   b  and  25   c  at a P (phosphorous) concentration of 8×10 20 /cm 3 ˜1×10 22 /cm 3  and second polysilicon layers  26   a  and  26   b  at a P concentration of 1×10 19 /cm 3 ˜5×10 20 /cm 3  are formed in turn by using the low pressure chemical vapor deposition (LPCVD) method, and then the multi polysilicon layer is formed in-situ. In other words, the doped polysilicon layers, each of which has a different concentration range of P, are alternately formed.  
         [0020]    At this time, the first polysilicon layers  25   a  and  25   c  may be a bottom layer and a top layer respectively. The second polysilicon layer  26   a  is formed on the first polysilicon layer  25   a,  and then the first polysilicon layer  25   b  is formed on the polysilicon layer  26   a  in turn.  
         [0021]    [0021]FIG. 4 is a cross-sectional view showing a structure of the multi polysilicon layer of FIG. 2 in accordance with the second embodiment of the present invention. A P-doped polysilicon layer  27   a  is formed to a thickness of 5 Å˜50 Å by using a PH 3  gas as a reaction gas and the doped second polysilicon layer  26   a  is formed in turn on the P-doped layer  27   a.  Subsequently, a P-doped polysilicon layer  27   b  is formed on the doped second polysilicon layer  26   a,  and then the doped second polysilicon layer  26   b  is formed on the P-doped polysilicon layer  27   b.  The doped second polysilicon layer  26   b  may be a top layer at a thickness of 5 Å˜50 Å.  
         [0022]    [0022]FIG. 5 is a cross-sectional view showing a structure of the multi polysilicon layer of FIG. 2 in accordance with the third embodiment of the present invention. The storage electrode has a stacked structure which is comprised of the first polysilicon layer  25   a  with a high P concentration, the second polysilicon layer  26   a  with low P concentration, the P-doped polysilicon layer  27   a,  the second polysilicon layer  26   b  and the first polysilicon layer  25   b.  As in the storage electrode which stacks up the first polysilicon layer  25   a,  the second polysilicon layer  26   a,  the P-doped polysilicon layer  27   a  and the second polysilicon layer  26   b  successively, the P-doped layer  27   a  is inserted between the second silicon layers  26   a  and  26   b.    
         [0023]    As described in the FIGS.  3  to  5 , the storage electrode  22  is formed by a plurality of conducting layers, each of which has a different concentration of P, and a thermal treatment is carried out.  
         [0024]    After alternately depositing the first polysilicon layers  25   a,    25   b  and  25   c  with a high P concentration and the second polysilicon layers  26   a  and  26   b  with a low P concentration to increase the P concentration deposition in the storage electrode  22 , or inserting the P-doped polysilicon layer between the two second polysilicon layers which have a low P concentration, the thermal treatment is carried out so that the whole storage electrode  22  maintains an even and high concentration of 8×10 20 /cm 3 .  
         [0025]    At this time, to prevent a depletion layer from being generated between a surface of the storage electrode  22  and the dielectric layer  23 , the P concentration on the surface of the storage electrode  22  has to be higher than that of a bulk region within the storage region  22 .  
         [0026]    Then, a pretreatment using a cleaning gas or nitrogen gas is carried out to clean the surface of the storage electrode in the stacked structure and, based on this pretreatment, a passivation layer may be formed on the surface thereof and such a passivation layer may prevent a low dielectric constant layer, such as a SiO 2  layer or a SiON layer, from being generated on the surface of the storage electrode.  
         [0027]    In the case where a NH 3  gas is used in the pretreatment, a nitride layer may be formed at a thickness of 3 Å˜30 Å by the rapid thermal process at 650 z, 900           C˜950                    C, and in the case where NH 3 , N 2  and N 2 O plasma are used, a nitride layer may be formed at a thickness of 3 Å˜ 30  Å. Also, in the LPCVD method, a Si 3 N 4  layer may be formed at a thickness of 3 Å˜ 30  Å. The CVD method make a tantalum based dielectric, e.g., Ta 2 O 5  and TaON, or after forming a top electric layer, e.g., PZT and SBT, the thermal treatment in the presence of an O 2 gas, at 700                    C˜1000                    C may be carried out for crystallizing the dielectric layer  23  and for inducing P diffusion into the storage electrode  22 .  
         [0028]    A metal layer is formed on the dielectric layer  23  by using one of the TiN, WN, RuO 2 , IrO 2  and Pt metals as the plate electrode  24 , and the metal layer uses a metal of low resistivity. As described above, the nitrogen protective layers, in accordance with embodiments of the present invention, prevent a capacitance decrease caused by the depletion layer and a low dielectric constant layer, and without the MPS layer which increases the size of the capacitor, capacitance acquisition over 25 fF/cell is possible.  
         [0029]    If the Ta 2 O 5 , which is the dielectric, is used in the MIS structure, the capacitance can be increased about 1.5 times because the dielectric rate is larger than that of Si 3 N 4  by about 4˜10 times so, without MPS, it is possible to obtain a sufficient capacitance.  
         [0030]    As described above, the capacitor of the present invention increases the P concentration of the storage electrode to prevent the capacitance decrease caused by a depletion and thereby, increase a charge capacity by more than 20% and makes integration easier than with the MIM structure. Without using MPS, it is possible to obtain enough capacitance to reduce expenditure, increase yield and downsize the device.  
         [0031]    While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims.