Abstract:
This disclosure provides detailed information on a capacitor chain successive approximation analog-to-digital converter. This specific innovation will replace the binary scaled capacitor of the prior art in capacitor successive approximation analog to digital converters comprises a chainable capacitor cell where each cell in the chain is identical. This will provide for a smaller, more compact circuit, allowing better capacitor matching.

Description:
FIELD OF INVENTION  
         [0001]    This invention relates to successive approximation analog to digital converters.  
           [0002]    The remainder of this contains six sections. The first provides background on analog-to-digital converters (ADC) in general, and successive approximation analog-to-digital converters (SA-ADC) in particular. The second section describes the art existing prior to the innovation. The third describes the problems associated with the prior art. The fourth presents the capacitor chain SA-ADC innovation as a solution to thee problems, and the fifth discusses the capacitor chain and its electrical operation in some detail. Finally, a summary recaps the most important points.  
         BACKGROUND  
         [0003]    Many transducers that create varying voltages or currents. This analog output will vary between a minimum and maximum value and is continuous in time. An example is a microphone that produces a continuous voltage in response to the variation in air pressure.  
           [0004]    A digital representation of an analog signal is easier to store, manipulate, and transmit. Consequently an analog-to-digital converter (ADC) is used to convert an analog signal into its digital representation. Usually the analog signal is represented by ‘n’ digital (base 2) binary digits allowing a resolution of the analog to a value of 1/2n.  
           [0005]    There are a large number of ADC technologies available: flash, single slope, dual slope, pipeline, and cyclic architectures. One type well suited for implementation in CMOS (Complementary Metal-Oxide Semiconductor) is the successive approximation ADC.  
           [0006]    The technique used by a successive approximation analog to digital converter consists of comparing an unknown voltage with a series of calibrated voltages. Calibrated voltages are binary scaled where the first calibrated voltage is {fraction (1/2 )} the maximum voltage required to be measured and successive voltages are ½ the previous voltage (e.g. the voltages are scaled ½ V max , ¼ V max , ⅛ V max , etc). The digital resolution of the analog signal is dependent on the number of calibrated voltages.  
           [0007]    The reference voltages are created using a voltage divider. It is common to use a bank of binary-scaled capacitors, that is, each successive capacitor is half the value of the previous one. One end of each capacitor is connected to a common line that to goes to the comparator; the other end of each is connected to a switch that can toggle between a reference voltage and ground (0 volts).  
           [0008]    Each capacitor forms a voltage divider between its switched end and the common node that is connected to the comparator, so when the switch is thrown from the ground to the reference voltage, the voltage on the common node increases by some fraction of the reference voltage, where the exact fraction depends upon the size of the capacitance. When the switch connected to the largest capacitor is thrown, the common node voltage increases by V ref /2. Since the next largest capacitor is thrown, the common node voltage increases by V ref /4. Similarly, throwing the switch connected to each successive capacitor increases the common node voltage by V ref /8, V ref /16, V ref /32, respectively.  
           [0009]    An AC analysis of the circuit will show that the capacitors are independent, so throwing the switch on a given capacitor increases the common node voltage by the same amount, with regard to what the common node voltage was to begin with. Therefore, throwing the switch to the second largest capacitor sends the common node voltage to ¼ V ref  or ¾ V ref , respectively, depending on whether the common node voltage was 0 ro ½ V ref , that is whether the switch to the largest capacitor connected to ground or to V ref .  
           [0010]    In order to do a conversion, all of the switches are originally set to ground so that the voltage on the common node is zero while voltage voltage to be converted is stored on its capacitor. Then the switch of each capacitor is thrown from ground to the reference voltage in turn. For each, if the comparator flips the switch is return to ground; otherwise it is left at V ref . In this fashion, the voltage on the common node is successively closer to the voltage to be converted, and the state of the switches serves as a binary coded form of the digital value of the voltage, once the conversion is complete.  
           [0011]    No disclosure herein is to be construed, as an admission that any reference cited herein is prior art against the present invention.  
         BRIEF SUMMARY OF THE INVENTION  
         [0012]    Analog to Digital Converters (ADC) are widely used to convert the value of an analog signal into an equivalent digital representation. Of the many types of ADC&#39;s, one type, a Successive Approximation Analog to Digital Converter (SA-ADC) is popular because of its flexibility and low cost. One implementation of a SA-ADC utilizes a network of capacitors and switches to generate a reference voltage. In previous implementations this network required that the capacitors be proportionally scaled. This scaling can lead to implementation problems on integrated circuits since it is difficult to fabricate capacitors with differing values.  
           [0013]    This invention implements a SA-ADC that needs only one value for the capacitors. This alleviates the problems of fabrication where multiple values of the capacitors are utilized.  
           [0014]    Objects and Advantages  
           [0015]    The first object of the SA-ADC using a bank of binary-scaled capacitors requires a wide range of capacitors with values accurately scaled in powers of 2. This leads to two problems: first, it is difficult to match the capacitors accurately when their absolute size is changing so dramatically, and second, the size of the largest capacitor limits how small the ADC can be.  
           [0016]    A capacitor is made from two plate conductors separated by an insulator. The capacitance is approximately given by the area of the plates times a property of the insulator times the dielectric constant, divided by the distance between the plates. However, the electric field in the capacitor doesn&#39;t end abruptly at the end of the plates, resulting in an additional contribution to the capacitance proportional to the perimeter of the plates. The wiring used to connect the capacitor also contributes capacitance, and structures near a capacitor, especially near the edges, can influence the capacitance. Therefore doubling the plate area of a capacitor does not necessarily double the capacitance exactly.  
           [0017]    While edge effects and other stray capacitance contributions can be measured, it still makes it difficult to accurately match the values of capacitors of widely different sizes. For example, in a 10-bit ADC the largest capacitor capacitance value that is 512 times the smallest, and it must be exactly 512 times the value, within a part in a thousand or so. This at the limit of how closely the stray capacitances can be controlled from one manufacturing run to another. Secondly, it is poor design practice to use capacitors where the capacitance value is dominated by the stray capacitance from wiring and the edges. Since the perimeter to area ration increases as capacitance size is decreased; this implies a minimum area for the smallest capacitor in the binary series. Since the capacitor of the largest capacitor is some fixed number times that of the smallest (512 times, for the 10-bit example used previously) and since in a CMOS process the chip designer can only change the capacitor area (the plate-to-plate distance and the dielectric constant of the insulator are fixed for a given CMOS process), this implies a minimum area for the largest capacitor. In practice, the minimum area can be large: in present imager designs using column parallel ADC&#39;s, the ADC&#39;s can take up nearly as much chip area as the active imaging area.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]    [0018]FIG. 1 is an illustration of a generic successive approximation analog-to-digital converter. The voltage to be converted is compared against the sum of a set of binary-scaled voltages. Each voltage is switched in, in turn, from the largest to the smallest. If the comparator indicates that the sum is less than the voltage to be converted, then the voltage is left in and a “1” is recorded in the output; if the sum is greater than the voltage to be converted, the voltage is switched out again, and a “0” is recorded.  
         [0019]    [0019]FIG. 2 is an abbreviated schematic of a capacitive successive approximation analog-to-digital converter of the prior art. The sum of binary weighted voltages is generated by throwing one end of successively smaller capacitors from ground to V ref . The design requires a wide range of capacitor values.  
         [0020]    [0020]FIG. 3 is an abbreviated schematic of a capacitive successive approximations analog-to-digital using a terminated chain of identical capacitor cells. The sum of binary-weighted voltages is generated by throwing the switch on the cells successively farther away from the connection to the comparator from ground to V ref . Using two capacitors in parallel to get the “2C” value of capacitance, the design can be implemented using only a single capacitor value.  
         [0021]    [0021]FIG. 4 shows the detail of a single cell, with the capacitors implemented using a single capacitor type, and with the switches implemented using field-effect transistors (FETs) as would be done in an actual CMOS design.  
         [0022]    [0022]FIGS. 5A, 5B,  5 C and  5 D provide various configurations of capacitors.  
         [0023]    [0023]FIG. 6 shows the equivalent capacitance seen looking left from node n 1  of a cell in the capacitor chain towards a chain of n cells terminated with the T 1  termination cell.  
         [0024]    [0024]FIG. 7 shows the equivalent circuit for calculating how the cell node voltage changes when that cells switch is thrown from the ground to V ref . The circuit forms a capacitive divider, dividing the voltage by 3.  
         [0025]    [0025]FIG. 8 shows the equivalent circuit for calculating how the node voltage changes in cells along the chain, when one cell&#39;s switch is thrown from ground to V ref . The node of the switched  
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0026]    In FIG. 1, 11 a set of Calibrated voltages  13  are binary scaled where the first calibrated voltage is ½ the maximum voltage required to be measured and successive voltages are ½ the previous voltage (e.g. the voltages are scaled ½ Vmax, ¼ Vmax, ⅛ Vmax, etc). The digital resolution of the analog signal is dependent on the number of calibrated voltages. These voltages may be summed  15  and fed to a comparator  17  to be compared to the unknown voltage  19 . The calibrated voltages may be created using a set of scaled capacitors (capacitor array) FIG. 221, that proportional in value, i.e. the first capacitor has a value of Cmax  25 A, the second capacitor has a value of Cmax/2  25 B, the third capacitor has a value of Cmax/4  25 C, etc. The individual voltages may be adjusted by moving individual toggle switches  23 A  23 B  23 C, etc from reference ground to Vmax. This reference voltage is fed to the negative terminal of the comparator  27 . The unknown, voltage is fed to the positive terminal of the comparator  27 . This voltage is sampled using a switch  31  combined with a capacitor  29 .  
         [0027]    The innovation is to replace the binary-scaled set of capacitors all connected to the common node going into the comparator with a chain of capacitor cells. Only one cell is connected to the comparator directly; the second cell connects to the first, the third connects to the second, etc. Each cell in the chain is identical except for special termination cells at each end of the chain.  
         [0028]    Each cell contains two capacitors, one having twice the capacitance of the other. In practice, the large capacitor can be made from two capacitors in parallel, so that the cell actually consists of three identical capacitors, two of which are tied together. One cell is needed for each bit of ADC resolution.  
         [0029]    This provides a solution to the two problems discussed above. First, because all of the capacitors can be identical it is much easier to match them accurately. Identical capacitors will have identical areas, identical perimeters, etc. Second, this scheme allows the total area of the capacitor bank to be much smaller. With three capacitors per cell and one cell per bit, a 10 bit ADC requires 30 capacitors. If each capacitor is minimum size, the entire bank requires 30 times the area of the minimum size capacitor. By contrast, in the prior art (FIG. 1) using a binary-scaled bank of individual capacitors, the largest capacitor is 512 times the smallest in a 10-bit ADC, and the total area taken by all capacitors is 1024 times area of a minimum size capacitor. The proposed innovation can reduce the area required by more than 30 times.  
         [0030]    A schematic representation of the proposed successive approximation analog-to-digital converter using a chain of capacitor cells is shown in FIG. 341. Just as in the prior art, the ADC contains a comparator  53  and a capacitor  57  for the holding the voltage to be converted, with this voltage fed to one input of the comparator. However, the bank of binary-scaled capacitors for generating the voltage sum in the prior art is replaced with a chain of capacitor cells. FIG. 4 shows the detail of a single cell, with the capacitors implemented using a single capacitor type, and with the switches implemented using field-effect transistors (FETs) as would be done in an actual CMOS design.  
         [0031]    To see how the ADC functions electrically, consider first an AC analysis of the chain. In the AC sense, all voltage sources are replaced with ground, so it doesn&#39;t matter whether the switches for the cells are set to V ref  or ground. Consider the situation shown in FIG. 5. FIG. 5 a  shows the termination cell T 2  consisting of a single capacitor C. Clearly the capacitance seen looking into n 1  of this cell is simply C. Now consider the situation of FIG. 5 b , where a single chain cell is combined with the T 2  termination cell. The capacitance seen looking into node n 2  of the chain cell is then  2 C in series with a parallel combination of C and C.  
         Ceff=1/(1/2C+1/(C+C))  
         Ceff=1/(2/2C)  
         Ceff=C  
         Ceff=1/(1/2C+1/2C)  
         [0032]    Now consider the situation of FIG. 5 c  where two chain cells are connected with the termination cell of T 2 . To find the effective capacitance looking in to node n 2  of the second cell, we need to know the effective capacitance tied to node n 1  of the cell. This, however, is just the value solved for from FIG. 5 b , that is, C. With the value C tied to node n 1 , however, the situation of FIG. 5 c  reduces to that of FIG. 5 b , so the effective capacitance looking into the node n 2  equal to C.  
         [0033]    Then consider the situation shown in FIG. 671, where a series of capacitor cells are terminated with a slightly different termination cell, T 1    79 A  79 B  79 C. The effective capacitance looking to the left of node n 1  (but not including the capacitor in the cell itself) represents just a flipping of the same situation analyzed in FIG. 5 d . Therefore the effective capacitance is again just C. With a properly terminated series of chain cells of any length connected together, each cell sees an effective capacitance of C to the right of node n 1  and C to the left of n 1 . The steady-state response with respect to switching can then be analyzed by considering the equivalent circuit shown in FIG. 781. A capacitor C is connected from node n 1  to the switch. In addition, n 1  sees a capacitance to ground of C looking left and C looking right. This forms a capacitive divider, so that the change in voltage at n 1  as the switch is thrown from ground to V ref .  
         ΔV n1 =(V ref −0)(C/C+C+C)  
         ΔV n1 =⅓(Vref)  
         [0034]    This voltage change is independent of the initial voltage, so the final voltage is just the sum of the initial voltage and the voltage change. This change is reversible, so that if the switch is thrown back to ground the voltage on the node returns to its original value. Throwing the switch for a given cell then simply changes that cell&#39;s node voltage by ⅓ V ref .  
         ΔV 1 =ΔV 0 (½)  
         ΔV 1 =ΔV 0 (2C/2C+C+C)  
         ΔV 1 =ΔV 0 (2C/4C)  
         [0035]    Now consider the effect that throwing a switch for a given cell has on other cells. First consider the neighboring cell to the left. For the steady state value of the effect of throwing a given switch, the capacitors connected to other switches may be considered connected to ground in the transient sense, regardless of whether they are connected to ground or to V ref . The effective circuit is then that shown in FIG. 891. The capacitor from cell 0  to cell 1  together with the cell 1  capacitor to ground in effective capacitance from the remaining cells in the chain going left form a capacitive divider, so  
         [0036]    Since the chain repeats exactly, this effect continues down the chain, so ΔV 2 =½ *ΔV 1 , ΔV 3 =½ *ΔV 2 , ΔV 4 =½ *ΔV 3 ,etc. We have already found the effect of throwing a switch on the cell&#39;s own voltage, so in general  
         ΣΔVn=⅓ (ΔVref)(½N)  
         [0037]    Where n is the distance, in cells, between the switched and measured cell.  
         [0038]    With the exception that V ref  of the prior art is replaced by ⅔ V ref  in the innovation, the operation of the two types of SA-ADC&#39;S is the same. Referring back to the schematic of FIG. 341, the voltage to be converted is sampled onto its capacitor that connects to one input of the comparator. All switches are in the capacitor chain are connected to ground so that the voltage to the other input of the comparator is zero. The switches are then thrown in turn, starting from the cell connected to the comparator. If after a switch is thrown, the voltage produced by the capacitor chain is greater than the value to be converted, that switch is returned to ground. If not, that switch is left connected to V ref . The effect is the same as in the prior art: the operation with the most significant cell determines whether voltage to be converted is in the upper or lower half of the range. Each successive operation narrows the remaining range by a factor of two.  
         [0039]    Summary  
         [0040]    Replacing the bank of binary scaled capacitors in the capacitive successive approximation analog-to-digital converter of the prior art with a properly terminated chaining of capacitive divider cells will allow a significant size reduction of the ADC while promoting better capacitor matching for increased accuracy. The operation of the ADC will remain almost completely unchanged, except that the reference voltage must be scaled by 1.5 times to maintain the same input voltage range.