Abstract:
Provided is a transmission circuit with which it is possible to facilitate error correction of burst errors without increasing the processing load in multiframes configured from a plurality of OTN frame signals. This transmission circuit is provided with: a transmission-side signal recognition unit for detecting MFAS and recognizing the order of N number of OTN frame signals; an intra-multiframe sequence conversion unit for converting the sequence of data signals inside the multiframe in response to the recognized order; a transmission-side rearranging unit for consolidating the sequentially converted data signals into lengths equal to those of the OTN frame signals and creating N number of quasi-OTN frame signals; and a transmission unit for transmitting the multiframes configured from the N number of quasi-OTN frame signals.

Description:
TECHNICAL FIELD 
       [0001]    The present invention relates to a transmission circuit, a reception circuit, an optical transfer system, and a method for transmitting a multiframe, and in particular, to a transmission circuit that transmits a multiframe including a plurality of OTN (Optical Transport Network) frame signals, a reception circuit, an optical transfer system, and a method for transmitting a multiframe. 
       BACKGROUND ART 
       [0002]    With an increase in capacity of data communication in recent years, in optical communication, multiplexing of optical wavelengths and speeding-up of transfer speed are advancing. In WDM (Wavelength Division Multiplexing) transfer, optical communication using an OTN recommended by ITU-T (International Telecommunication Union Telecommunication Standardization Sector) G.709 has become mainstream. In the ITU-T G.709, an OTN frame of 4080 bytes/subframe×4 rows independent of transfer speed is defined. This OTN frame includes overhead and FEC code (Forward Error Correction code) for compensating quality degradation in transfer path. 
         [0003]    In the WDM transfer, interference between wavelengths and self-interference may be generated due to a transfer characteristic of an optical fiber, resulting in generation of burst errors. In the ITU-T G.709, an error correction code is generated after sequence conversion of data signals in a subframe, and a sequence of data signals during the error correction code generation is converted (interleaved), whereby errors are dispersed inside the subframe to cope with burst errors. The interleaving is disclosed in PTL 1 or the like. Further, a method for coping with burst errors using an error correction code is disclosed in PTL 2 or the like. 
         [0004]    However, due to increase of transfer speed, a time length for error-correctable burst errors becomes short. While an error correction code is generated for each subframe, a size of a subframe is fixed, and therefore with an increase in transfer speed, a time slot per frame relatively becomes short. While, of OTN frames, for example, a lowest-speed OTU1 frame has a transfer speed of 2.7 Gbps and a time slot per frame of 49 μsec, a highest-speed OTU4 frame has a transfer speed of 111.8 Gbps and a time slot per frame of 1.2 μsec. The time slot of the OTU4 frame is approximately 1/50 of that of the OTU1 frame, and therefore, in the OTU1, errors are dispersed and error correction can be performed, but in the OTU4, it is impossible in some cases to disperse errors and perform error correction. 
         [0005]    In PTL 3, it is proposed that, by continuously using data series for a plurality of frames, a predetermined rule is rearranged in a frame unit and interleaving is performed in a plurality of inter-frame units. 
       CITATION LIST 
     Patent Literature 
       [0006]    [PTL 1] Japanese Laid-open Patent Publication No. H 6 -014001 
         [0007]    [PTL 2] Japanese Laid-open Patent Publication No. 2011-61636 
         [0008]    [PTL 3] Japanese Laid-open Patent Publication No. 2003-110430 
       SUMMARY OF INVENTION 
     Technical Problem 
       [0009]    However, in the technique of PTL 3, it is necessary to continue to process, without interruption, data of a plurality of frames transmitted/received continuously, and therefore a processing load remarkably increases. 
         [0010]    In view of the above problem, the present invention has been made, and an object of the present invention is to provide an optical transfer system and an optical transfer method capable of easily performing error correction on burst errors for a multiframe including a plurality of OTN frame signals without increasing a processing load. 
       Solution to Problem 
       [0011]    In order to achieve the above object, a transmission circuit according to the present invention is a transmission circuit that transmits a multiframe including N OTN (Optical Transport Network) frame signals that each accommodate an MFAS (Multiframe Alignment Signal) and a plurality of data signals, the transmission circuit including: a transmission-side signal recognition means for detecting the MFAS and recognizing an order i (1≦i≦N) of the OTN frame signal; an intra-multiframe sequence conversion means for converting a sequence of the plurality of data signals inside the multiframe in accordance with the recognized order i; a transmission-side rearranging means for acquiring the sequence-converted data signals in a multiframe unit, consolidating the sequence-converted data signals into lengths equal to those of the OTN frame signals respectively, and generating N quasi-OTN frame signals being sequentially added with an MFAS; and a transmission means for transmitting a multiframe including the N generated quasi-OTN frame signals. 
         [0012]    In order to achieve the above object, a reception circuit according to the present invention is a reception circuit that receives a multiframe transmitted from the transmission circuit, the reception circuit including: a reception means for receiving a multiframe including N quasi-OTN frame signals; a reception-side signal recognition means for detecting an MFAS of the quasi-OTN frame signal and recognizing an order of the quasi-OTN frame signal; an intra-multiframe sequence restoring means for restoring a sequence of the plurality of data signals inside the multiframe in accordance with the recognized order by using a procedure opposite to that of the intra-multiframe sequence conversion means; and a reception-side rearranging means for acquiring the sequence-restored data signals in a multiframe unit, consolidating the sequence-restored data signals into lengths equal to those of the quasi-OTN frame signals respectively, and restoring N OTN frame signals being sequentially added with an MFAS. 
         [0013]    In order to achieve the above object, an optical transfer system according to the present invention includes the transmission circuit and the reception circuit. 
         [0014]    In order to achieve the above object, a method for transmitting a multiframe according to the present invention is a method for transmitting a multiframe including N OTN frame signals that each accommodate an MFAS and a plurality of data signals, the method including: detecting the MFAS; recognizing an order i (1≦i≦N) of the OTN frame signal; converting a sequence of the plurality of data signals inside the multiframe in accordance with the recognized order i; acquiring the sequence-converted data signals in a multiframe unit; consolidating the sequence-converted data signals into lengths equal to those of the OTN frame signals respectively; generating N quasi-OTN frame signals being sequentially added with an MFAS; and transmitting a multiframe including the N generated quasi-OTN frame signals. 
       Advantageous Effects of Invention 
       [0015]    According to the above-described aspects of the present invention, it is possible to perform error correction easily on burst errors for a multiframe including a plurality of OTN frame signals without increasing a processing load. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0016]      FIG. 1A  is a system configuration diagram of an optical transfer system  10  according to a first example embodiment. 
           [0017]      FIG. 1B  is a block configuration diagram of a transmission circuit  20  according to the first example embodiment. 
           [0018]      FIG. 1C  is a block configuration diagram of a reception circuit  30  according to the first example embodiment. 
           [0019]      FIG. 2  is a diagram illustrating data signal sequences of OTN frame signals and quasi-OTN frame signals. 
           [0020]      FIG. 3  is a system configuration diagram of an optical transfer system  100  according to a second example embodiment. 
           [0021]      FIG. 4  is a frame configuration diagram of an OTN frame signal. 
           [0022]      FIG. 5  is a block configuration diagram of a multiframe interleaver  250  according to the second example embodiment. 
           [0023]      FIG. 6  is a diagram illustrating a sequence replacement procedure of data signals in the multiframe interleaver  250  according to the second example embodiment. 
           [0024]      FIG. 7  is a block configuration diagram of a multiframe deinterleaver  320  according to the second example embodiment. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
     First Example Embodiment 
       [0025]    A first example embodiment of the present invention will be described. A system configuration diagram of an optical transfer system according to the present example embodiment is illustrated in  FIG. 1A . As illustrated in  FIG. 1A , an optical transfer system  10  includes a transmission circuit  20  and a reception circuit  30 . 
         [0026]    The transmission circuit  20  transmits a multiframe including N OTN (Optical Transport Network) frame signals that each accommodate an MFAS (Multiframe Alignment Signal) and a plurality of data signals. 
         [0027]    The reception circuit  30  receives the multiframe transmitted from the transmission circuit  20 . 
         [0028]    In the present example embodiment, a quasi-OTN frame signal generated by replacing data signals of an OTN frame signal in a multiframe unit is transmitted from the transmission circuit  20 . The reception circuit  30  having received the quasi-OTN frame signal restores the quasi-OTN frame signal to the original OTN frame signal in a multiframe unit. The transmission circuit  20  and the reception circuit  30  will be described in detail. 
         [0029]    First, the transmission circuit  20  will be described. A block configuration diagram of the transmission circuit  20  according to the present example embodiment is illustrated in  FIG. 1B . In  FIG. 1B , the transmission circuit  20  includes a transmission-side signal recognition means  21 , an intra-multiframe sequence conversion means  22 , a transmission-side rearranging means  23 , and a transmission means  24 . 
         [0030]    The transmission-side signal recognition means  21  detects an MFAS of an input OTN frame signal and recognizes an order i (1≦i≦N) of the OTN frame signal from the detected MFAS. 
         [0031]    The intra-multiframe sequence conversion means  22  replaces a sequence of data signals of N OTN frame signals configuring a multiframe in accordance with the order i recognized in the transmission-side signal recognition means  21  and configures data signals of a multiframe including N quasi-OTN frame signals. The intra-multiframe sequence conversion means  22  according to the present example embodiment sequentially accommodates, as illustrated in  FIG. 2 , N continuous data signals accommodated in the input i-th OTN frame signal in an i-th data signal area of the N quasi-OTN frame signals arranged in an MFAS order and thereby sequence-converts the data signals. 
         [0032]    The transmission-side rearranging means  23  acquires the data signals sequence-converted in a multiframe unit, consolidates the sequence-converted data signals into lengths equal to those of the OTN frame signals respectively, and generates, by sequentially adding an MFAS, N quasi-OTN frame signals illustrated in  FIG. 2 . In  FIG. 2 , the transmission-side rearranging means  23  adds an MFAS indicating an i-th order to signals in which i-th data signals of OTN frame signals inside a multiframe are arranged in an MFAS order of the OTN frame signal and thereby generates an i-th quasi-OTN frame signal. 
         [0033]    The transmission means  24  transmits a multiframe including N generated quasi-OTN frame signals. 
         [0034]    When sequence replacement of data signals is performed in a multiframe unit, sequence replacement may be performed always for a predetermined number of data signals, and therefore compared with a case where sequence replacement is performed intermittently for input data signals, a processing load on the transmission circuit  20  can be reduced. 
         [0035]    Next, the reception circuit  30  will be described. A block configuration diagram of the reception circuit  30  according to the present example embodiment is illustrated in  FIG. 1C . In  FIG. 1C , the reception circuit  30  includes a reception means  31 , a reception-side signal recognition means  32 , an intra-multiframe sequence restoring means  33 , and a reception-side rearranging means  34 . 
         [0036]    The reception means  31  receives a multiframe including N quasi-OTN frame signals transmitted from the transmission circuit  20 . 
         [0037]    The reception-side signal recognition means  32  detects an MFAS of the input quasi-OTN frame signal and recognizes an order i of the input quasi-OTN frame signal from the detected MFAS. 
         [0038]    The intra-multiframe sequence restoring means  33  restores a sequence of data signals of the quasi-OTN frame signal to the original sequence inside the multiframe using a procedure opposite to that of the intra-multiframe sequence conversion means  22  of the transmission circuit  20  in accordance with the order i recognized in the reception-side signal recognition means  32 . 
         [0039]    The reception-side rearranging means  34  acquires the sequence-restored data signals in a multiframe unit, consolidates the sequence-restored data signals into lengths equal to those of the quasi-OTN frame signals respectively, and restores N OTN frame signals being sequentially added with an MFAS. 
         [0040]    When sequence restoration of data signals is performed in a multiframe unit, sequence restoration may be performed for a predetermined number of data signals, and therefore compared with a case where sequence restoration is performed intermittently for input data signals, a processing load on the reception circuit  30  can be reduced. 
         [0041]    In the optical transfer system  10  according to the present example embodiment, a multiframe in which data signals are replaced using a predetermined procedure inside a multiframe is transferred between the transmission circuit  20  and the reception circuit  30 . Thereby, even when burst errors exceeding a size of a frame are generated, the errors are dispersed between frames and error correction can be performed. 
         [0042]    In the optical transfer system  10  according to the present example embodiment, data signals are replaced in a multiframe unit using a predetermined procedure. In this case, the transmission circuit  20  and the reception circuit  30  may perform sequence conversion and restoration for a predetermined number of data signals. Therefore, the optical transfer system  10  according to the present example embodiment can easily perform error correction of burst errors without increasing a processing load on the transmission circuit  20  and the reception circuit  30 . 
       Second Example Embodiment 
       [0043]    A second example embodiment will be described. A system configuration diagram of an optical transfer system according to the present example embodiment is illustrated in  FIG. 3 . In  FIG. 3 , an optical transfer system  100  includes a transmission-side circuit  200  and a reception-side circuit  300 . The transmission-side circuit  200  and the reception-side circuit  300  transmit/receive a multiframe including 256 OTN frame signals. The OTN frame signal according to the present example embodiment conforms to a frame configuration defined in ITU-T G.709. A frame configuration of the OTN frame signal is illustrated in  FIG. 4 . 
         [0044]    As illustrated in  FIG. 4 , the OTN frame signal includes four subframes  1  to  4 . A size of each subframe is 4080 bytes including a 16-byte OTN overhead, a 3808-byte payload area, and a 256-byte FEC area. 
         [0045]    In the OTN overhead, a fame alignment and various types of overheads are accommodated. In a head of the subframe  1 , an FAS (Frame Alignment Signal) that is a frame synchronization signal and an MFAS (Multiframe Alignment Signal) that is management information of a transfer path side are accommodated. A byte value of the FAS is F6F6F6282828 and its transmission is performed without scrambling. On the other hand, the MFAS is assigned with numbers of 0 (00000000) to 255 (11111111) in a generation order of OTN frame signals. 
         [0046]    Data signals are accommodated in a payload area of 3808×4 bytes. Further, in an FEC area of 256 bytes of each subframe, 16 pieces of 16-byte FEC blocks are arranged, and in the OTN frame, 64 FEC blocks are arranged. 
         [0047]    Next, the transmission-side circuit  200  and the reception-side circuit  300  will be described. First, the transmission-side circuit  200  will be described. As illustrated in  FIG. 3 , the transmission-side circuit  200  includes an OTN frame generation unit  210 , an interleaver  220 , an FEC encoder  230 , a deinterleaver  240 , a multiframe interleaver  250 , and a transmission unit  260 . 
         [0048]    The OTN frame generation unit  210  generates an OTN fame signal conforming to a frame configuration defined in ITU-T G.709 based on a transfer signal input to the transmission-side circuit  200  and further outputs, to the interleaver  220 , the generated signal being added with an OTN overhead described in  FIG. 4 . 
         [0049]    The interleaver  220  replaces a signal sequence of the input OTN frame signal in a predetermined order for each subframe and outputs the replaced sequence to the FEC encoder  230 . The interleaver  220  according to the present example embodiment replaces the signal sequence of the OTN frame signal in accordance with a sequence conversion method defined in ITU-T G.975 (a code correction method of a submarine system). The interleaver  220  is included in an inter-subframe sequence conversion means of CLAIMS. 
         [0050]    The FEC encoder  230  generates an error correction code using data signals included in a payload area of the OTN frame signal. The FEC encoder  230  embeds the generated correction code in an FEC area (256 bytes) of an OTN frame signal in which the signal sequence input from the interleaver  220  has been replaced and outputs the OTN frame signal to the deinterleaver  240 . The FEC encoder  230  is included in an error correction code adding means of CLAIMS. 
         [0051]    The deinterleaver  240  restores the OTN frame signal input from the FEC encoder  230  to an OTN frame signal of the original sequence using a procedure opposite to that of the interleaver  220 . The deinterleaver  240  outputs the restored OTN frame signal to the multiframe interleaver  250 . The deinterleaver  240  is included in an inter-subframe sequence restoring means of CLAIMS. 
         [0052]    The multiframe interleaver  250  replaces data (data signals, a correction code, etc.) excluding a frame alignment of the input OTN frame signal in a multiframe unit and outputs the replaced data to the transmission unit  260 . In other words, the multiframe interleaver  250  replaces  256  input OTN frame signals among  256  OTN frames. An OTN frame signal in which a signal sequence has been replaced in a multiframe unit is output to the transmission unit  260 . Replacement of a signal sequence of a multiframe unit in the multiframe interleaver  250  will be described later. 
         [0053]    The transmission unit  260  performs E/O (electrical-to-optical) conversion of the OTN frame signal input from the multiframe interleaver  250  and transmits the converted signal as a transmission signal. The transmission signal transmitted from the transmission-side circuit  200  passes through a transfer path and is received by the reception-side circuit  300 . 
         [0054]    Next, the reception-side circuit  300  will be described. As illustrated in  FIG. 3 , the reception-side circuit  300  includes a reception unit  310 , a multiframe deinterleaver  320 , an interleaver  330 , an FEC decoder  340 , a deinterleaver  350 , and an OTN frame termination unit  360 . 
         [0055]    The reception unit  310  performs O/E (optical-to-electrical) conversion of the transmission signal received from the transmission-side circuit  200  via the transfer path and outputs the converted signal to the multiframe deinterleaver  320  as a reception signal. 
         [0056]    The multiframe deinterleaver  320  replaces a sequence in the input reception signal in a multiframe unit using a procedure opposite to that of the multiframe interleaver  250  of the transmission-side circuit  200 , restores the signal subjected to the replacement to the original OTN frame signal, and outputs the restored signal to the interleaver  330 . Restoration of a signal sequence of a multiframe unit in the multiframe deinterleaver  320  will be described later. 
         [0057]    The interleaver  330  replaces a signal sequence for the input OTN frame signal in accordance with the sequence conversion method defined in ITU-T G.975 in the same manner as the interleaver  220  of the transmission-side circuit  200  and outputs the signal subjected to the replacement to the FEC decoder  340 . 
         [0058]    The FEC decoder  340  error-corrects data signals of the input OTN frame and outputs the data signals after error correction to the deinterleaver  350 . The transmission signal passes through a transfer path in a state where a signal sequence of a multiframe unit has been replaced in the multiframe interleaver  250  of the transmission-side circuit  200 , and therefore errors generated during passing through a transfer path are dispersed (uniformed) inside the multiframe. Therefore, even when burst errors exceeding a size of a subframe are generated during transfer in the transfer path, the errors are dispersed between frames and error correction is performed in the FEC decoder  340 . The FEC decoder  340  is included in an error correction executing means of CLAIMS. 
         [0059]    The deinterleaver  350  restores the error-corrected OTN frame signal input from the FEC decoder  340  to an OTN frame signal of the original sequence using a procedure opposite to that of the interleaver  330  and outputs the restored signal to the OTN termination unit  360 . 
         [0060]    The OTN frame termination unit  360  terminates an OTN overhead of the input OTN frame signal and eliminates an error correction code. Further, the OTN frame termination unit  360  restores the original transmission signal from signals of a payload area of the OTN frame signal and outputs the restored signal as a transfer signal. 
         [0061]    Next, replacement and restoration of a signal sequence of a multiframe unit in the multiframe interleaver  250  of the transmission-side circuit  200  and the multiframe deinterleaver  320  of the reception-side circuit  300  will be described. 
         [0062]    First, the multiframe interleaver  250  of the transmission-side circuit  200  will be described. A block configuration diagram of the multiframe interleaver  250  is illustrated in  FIG. 5 . In  FIG. 5 , the multiframe interleaver  250  includes a frame synchronizer  251 , a demultiplexer interleaver  252 , a memory  253 , and a multiplexer  254 . In  FIG. 5 , a direction of an arrow between blocks is not limited to a direction in the figure. 
         [0063]    The frame synchronizer  251  detects a head of an OTN frame signal input from the deinterleaver  240  by monitoring an FAS accommodated in the OTN overhead illustrated in  FIG. 4  and further recognizes a number (1 to 256) of the OTN frame by referring to an MFAS. Hereinafter, an i-th OTN frame signal input to the frame synchronizer  251  will be described as an OTN frame signal i (i=1 to 256). 
         [0064]    The demultiplexer interleaver  252  converts, based on the number (MFAS) of the OTN frame detected in the frame synchronizer  251 , data (data signals, a correction code, etc.) excluding a frame alignment of the OTN frame signal to parallel signals and replaces a sequence. The demultiplexer interleaver  252  stores data signals subjected to the parallel conversion and the sequence replacement on the memory  253 . 
         [0065]    Data signals of which a sequence has been replaced, that are output from the demultiplexer interleaver  252 , are written onto the memory  253 . 
         [0066]    The multiplexer  254  reads data signals for one multiframe cycle from the memory  253  every time data signals for one multiframe cycle are written onto the memory  253 . The multiplexer  254  adds, to a head of the read data signals, a corresponding FAS and MFAS and generates N OTN frame signals  1 ′ to  256 ′ (i′=1 to 256). 
         [0067]    The OTN frame signals  1  to  256  written on the memory  253  are illustrated on the left side of  FIG. 6 , and the OTN frame signals  1 ′ to  256 ′ generated in the multiplexer  254  are illustrated on the right side of  FIG. 6 . As illustrated in  FIG. 6 , one multiframe includes 256 OTN frame signals, and an OTN frame signal i′ is generated by sequentially inserting i-th data signals of the OTN frame signal  1  to the OTN frame signal  256  after an FAS and an MFAS. 
         [0068]    In the present example embodiment, the multiplexer  254  further converts the generated OTN frame signals  1 ′ to  256 ′ to serial signals and outputs the resulting serial signals to the transmission unit  260 . The multiplexer  254  according to the present example embodiment deletes the data signals used to generate the serial signals from the memory  253  after outputting the serial signals to the transmission unit  260 . 
         [0069]    Next, the multiframe deinterleaver  320  of the reception-side circuit  300  will be described. A block configuration diagram of the multiframe deinterleaver  320  is illustrated in  FIG. 7 . In  FIG. 7 , the multiframe deinterleaver  320  includes a frame synchronizer  321 , a demultiplexer deinterleaver  322 , a memory  323 , and a multiplexer  324 . In  FIG. 7 , a direction of an arrow between blocks is not limited to a direction in the figure. 
         [0070]    The frame synchronizer  321  synchronizes with an OTN frame signal, monitors a FAS and an MFAS and thereby detects a head (an OTN frame signal  1 ′) of a multiframe input from the reception unit  310 . 
         [0071]    The demultiplexer deinterleaver  322  replaces, based on the detected head of the multiframe, a sequence of data signals using a procedure opposite to that of the demultiplexer interleaver  252  of the multiframe interleaver  250  of the transmission-side circuit  200  and restores the original OTN frame. In other words, data signals of the OTN frame signal  1 ′ are sorted into OTN frame signals  1  to  256 , and data signals of an OTN frame signal  2 ′ are sorted in such a way as to be arranged immediately after the OTN frame signals  1  to  256 . In the present example embodiment, the demultiplexer deinterleaver  322  stores the sequence-replaced data signals of OTN frame signals  1 ′ to  256 ′ on the memory  323 . 
         [0072]    The data signals are temporarily stored on the memory  323  until completion of sequence conversion of data signals for 256 OTN frames  1 ′ to  256 ′ inside a multiframe in the demultiplexer deinterleaver  322 . 
         [0073]    The multiplexer  324  reads in parallel data signals for one multiframe cycle from the memory  323  every time data signals for one multiframe cycle are written onto the memory  323 . The multiplexer  324  adds, to a head of the read data signals, a corresponding FAS and MFAS and generates OTN frame signals  1  to  256 . Thereby, the OTN frame signals  1  to  256  illustrated on the left side of  FIG. 6  are restored from the OTN frame signals  1 ′ to  256 ′ illustrated on the right side of  FIG. 6 . The multiplexer  324  further converts the restored OTN frame signals  1  to  256  to serial signals and outputs the resulting serial signals to the interleaver  330 . The multiplexer  324  according to the present example embodiment deletes the data signals used to generate the serial signals from the memory  323  after outputting the serial signals to the interleaver  330 . 
         [0074]    As described above, the optical transfer system  100  according to the present example embodiment replaces, in the multiframe interleaver  250  of the transmission-side circuit  200 , data signals of an input OTN frame signal in a multiframe unit and transfers the OTN frame signals  1 ′ to  256 ′ in which a sequence of data signals has been replaced in a multiframe unit. The multiframe deinterleaver  320  of the reception-side circuit  300  restores the original OTN frame signals  1  to  256  in a multiframe unit using a procedure opposite to that of the multiframe interleaver  250  of the transmission-side circuit  200 . 
         [0075]    In this case, it is possible to disperse (uniform) burst errors generated in a transfer path inside a multiframe and perform error correction of burst errors in the FEC decoder  340  of the reception-side circuit  300 . Further, when sequence restoration is performed in a multiframe unit, compared with a case where sequence restoration is intermittently performed for input data signals, a processing load on the transmission-side circuit  200  and the reception-side circuit  300  can be inhibited from increasing. 
         [0076]    Therefore, the optical transfer system  100  according to the present example embodiment can easily perform error correction of burst errors for a multiframe including a plurality of OTN frame signals without increasing a processing load. 
         [0077]    The present invention is not limited to the above example embodiments, and even design modifications and the like without departing from the gist of the invention are also included in the invention. 
       INDUSTRIAL APPLICABILITY 
       [0078]    The present invention is widely applicable to an optical transfer system that transfers a multiframe including a plurality of OTN frame signals. 
         [0079]    This application is based upon and claims the benefit of priority from Japanese patent application No. 2015-005055, filed on Jan. 14, 2015, the disclosure of which is incorporated herein in its entirety by reference. 
       REFERENCE SIGNS LIST 
       [0000]    
       
           10  Optical transfer system 
           20  Transmission circuit 
           21  Transmission-side signal recognition means 
           22  Intra-multiframe sequence conversion means 
           23  Transmission-side rearranging means 
           24  Transmission means 
           30  Reception circuit 
           31  Reception means 
           32  Reception-side signal recognition means 
           33  Intra-multiframe sequence restoring means 
           34  Reception-side rearranging means 
           100  Optical transfer system 
           200  Transmission-side circuit 
           210  OTN frame generation unit 
           220  Interleaver 
           230  FEC encoder 
           240  Deinterleaver 
           250  Multiframe interleaver 
           260  Transmission unit 
           300  Reception-side circuit 
           310  Reception unit 
           320  Multiframe deinterleaver 
           330  Interleaver 
           340  FEC decoder 
           350  Deinterleaver 
           360  OTN frame termination unit