Abstract:
A CMOS image sensor has a pixel array provided with a plurality of unit pixels arranged in a matrix shape of rows and columns. Each of the unit pixel includes a photocharge generation means for generating photocharges by absorbing an external light; and a sensing node for receiving the photocharges transferred from the photocharge generation means, wherein the sensing node of the unit pixel in a previous scan line is shared with a sensing node of a unit pixel in a current scan line in response to a line select signal of the current line.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to a complementary metal oxide semiconductor (hereinafter, referred to as a CMOS) image sensor; and, more particularly, to a pixel array of a CMOS image sensor for increasing storage capacitance of a sensing node. 
       DESCRIPTION OF RELATED ARTS 
       [0002]    In general, an image sensor is an apparatus for capturing an image using a characteristic of a semiconductor which is sensitive to a light. Every portion of each object existing in nature has different brightness and wavelength so that it shows different electrical values at respective pixels that sense an incident light corresponding to each portion of the object. In this manner, the image sensor serves a role of converting these electrical values into predetermined levels of signals which can be processed through a circuitry. 
         [0003]      FIG. 1  is a block diagram setting forth a conventional CMOS image sensor. 
         [0004]    Referring to  FIG. 1 , the conventional CMOS image sensor includes an interface unit  10 , a pixel array  20 , an analog-digital converter  30  and a buffer  40 . Herein, the interface unit  10  controls overall operation of the CMOS image sensor, and acts as an interface with respect to an external system. The pixel array  20  is configured with an N number of pixel columns and an M number of pixel rows to have N×M number of pixels so that the pixel array  20  senses information with regard to an image inputted from an exterior, wherein each pixel is constructed such that its photosensitivity may be maximized. The analog-digital converter  30  converts an analog voltage sensed at each pixel of the image sensor into a digital voltage to be processed at a digital system. The buffer  40  stores the digitalized image data of the pixel in response to the output of the analog-digital converter  30 . 
         [0005]    In addition, the analog-digital converter  30  is provided with a digital-analog converter (DAC)  31  and a voltage comparator  32 . The DAC  31  generates a reference voltage in ramp type which is linearly decreased with a clock, wherein the reference voltage is used for being compared with a voltage sensed at each pixel. The voltage comparator  32  configured with N number of arrangements compares the sensed voltage, i.e., an analog voltage, outputted from the pixel array  20  with the reference voltage of the DAC  31 , and outputs a write enable signal which allows a counter value outputted from the interface unit  10  to be written to the buffer  40  while the reference voltage is higher than the sensed voltage. 
         [0006]    If the CMOS image sensor employs a correlated double sampling (CDS) method in order to produce high quality image, each unit pixel  100  and  120  of the pixel array is configured with one photodiode and four transistors, as illustrated in  FIG. 2 . In detail, the four transistors are configured with a transfer transistor M 21  for transferring photocharges generated at the photodiode  101  to a sensing node A, a reset transistor M 11  for discharging the photocharges stored at the sensing node A in order to detect a next signal, a drive transistor M 31  for acting as a source follower, and a select transistor M 41  for switching and addressing. 
         [0007]    Herein, in the CDS method, a voltage corresponding to a reset level is obtained by turning on the reset transistor M 11  but turning off the transfer transistor M 21 , and subsequently, the photocharges generated at the photodiode  101  are read to obtain a data voltage level by turning off the reset transistor M 11  but turning on the transfer transistor M 21 . Thereafter, a voltage difference between the reset voltage level and the data voltage level is obtained as a pure image data signal. 
         [0008]      FIG. 3  is a control timing diagram illustrating signals controlling each transistor in the unit pixel of  FIG. 2 . Referring to  FIG. 3 , an operation of the unit pixel will be set forth for every section in detail herebelow. 
         [0009]    1) A Section 
         [0010]    In this section, the transfer transistor M 21  and the reset transistor M 11  are turned on, but the select transistor M 41  is turned off. Therefore, the photodiode  101  is in a state of a fully depletion. 
         [0011]    2) B Section 
         [0012]    In this section, the transfer transistor M 21  is turned off so that the photodiode  101  absorbs the light to generate the photocharges. Thus, the generated photocharges are integrated during this section. Meanwhile, the section B maintains till the transfer transistor M 21  is turned on again regardless of the states of the reset and select transistors M 11  and M 41 . 
         [0013]    3) C Section 
         [0014]    In this section, the reset transistor M 11  is turned on, and the transfer transistor M 21  maintains to be turned off, bur the select transistor M 41  is turned on so that a reset voltage level is transferred through the drive transistor M 31  and the select transistor M 41 . 
         [0015]    4) D Section 
         [0016]    In this section, the reset transistor M 11  is turned off so as to settle the reset voltage level generated during the section C. 
         [0017]    5) E Section 
         [0018]    This is a section for sampling the reset voltage level of the section D. 
         [0019]    6) F Section 
         [0020]    In this section, the reset transistor M 11  and the select transistor M 41  maintain to be turned off and on, respectively, and the transfer transistor M 21  is turned on so that the photocharges integrated at the photodiode  101  during the section B are transferred to the sensing node A. Thus, a data voltage level is transferred through the drive transistor M 31  and the select transistor M 41 . 
         [0021]    7) G Section 
         [0022]    In this section, the transfer transistor M 21  is turned off so as to settle the data voltage level generated during the section F. 
         [0023]    8) H Section 
         [0024]    This section is for sampling the data voltage level of the section G. 
         [0025]    The reset voltage level and the data voltage level which are sampled at the section E and H respectively, are outputted to the analog-digital converter  30  and then, are converted into a digital data. The difference value between the digitally-converted reset voltage level and the data voltage level becomes an output image data of the CMOS image sensor for the image inputted through the photodiode  101 . 
         [0026]    Herein, the other unit pixels of the conventional CMOS image sensor operate like that of the unit pixel  100  which has been described above. In case of employing a row-by-row scanning type in the pixel array, the scanning is performed from a first row to a last row in sequence. 
         [0027]    Therefore, for example, when obtaining a data from a pixel of an nth row after obtaining a data from a pixel of an n−1th row, photocharges are integrated anew after cleaning up all the pixels corresponding to a first to the n−1th rows. 
         [0028]    Meanwhile, as described above, the photodiode constituting each unit pixel should have high capacitance for generating the photocharges and integrating them in order to obtain good image quality. To this end, an attempt for improving fill-factor has been made using a technology of increasing a photodiode area and so forth. 
         [0029]    However, the sensing node in the conventional CMOS image sensor, which is implemented as a high concentration impurity diffusion region, does not have capacitance enough to receive increased photocharges in spite of the enhanced fill-factor, which makes it difficult to obtain a desired photosensitivity after all. 
       SUMMARY OF THE INVENTION 
       [0030]    It is, therefore, an object of the present invention to provide a CMOS image sensor of which a capacitance of a sensing node is increased by sharing the sensing node of an adjacent non-selected pixel while a selected pixel operates, in order that the sensing node may receive photocharges generated much more due to an enhanced fill-factor. 
         [0031]    In accordance with an aspect of the present invention, there is provided A CMOS image sensor having a pixel array provided with a plurality of unit pixels arranged in a matrix shape of rows and columns, each of the unit pixel including: a photocharge generation means for generating photocharges by absorbing an external light; and a sensing node for receiving the photocharges transferred from the photocharge generation means, wherein the sensing node of the unit pixel in a previous scan line is shared with a sensing node of a unit pixel in a current scan line in response to a line select signal of the current line. 
         [0032]    In accordance with another aspect of the present invention, there is provided A CMOS image sensor including: a pixel array in which a plurality of unit pixels are arranged in a matrix shape of rows and columns; and a switching means for interconnecting a sensing node of a selected unit pixel to a sensing node of another neighboring unit pixel in response to a select signal, to increase a storage capacitance of the sensing node of the selected pixel. Herein, the unit pixel includes a photocharge generation means for generating photocharges by absorbing an external light; a sensing node for receiving the photocharges transferred from the photocharge generation means; a transfer means for transferring the photocharges from the photocharge generation means to the sensing node; a rest means for resetting the sensing node; an output means for outputting an electric signal in response to the sensing node; and an addressing means of which one side is connected to the output means for switching and addressing in response to the select signal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0033]    The above and other objects and features of the present invention will become better understood with respect to the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which: 
           [0034]      FIG. 1  is a block diagram of a conventional CMOS image sensor; 
           [0035]      FIG. 2  is a circuit diagram setting forth a pixel array of the conventional CMOS image sensor; 
           [0036]      FIG. 3  is a timing diagram setting forth a unit pixel of  FIG. 2 ; and 
           [0037]      FIG. 4  is a circuit diagram illustrating a pixel array of a CMOS image sensor in accordance with an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0038]    A CMOS image sensor with shared sensing node in accordance with exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. 
         [0039]      FIG. 4  is a circuit diagram illustrating a pixel array of a CMOS image sensor in accordance with an embodiment of the present invention. In particular,  FIG. 4  represents three unit pixels which are successively arranged in the same column among a plurality of unit pixels in the pixel array. 
         [0040]    The CMOS image sensor of the present invention is configured with a pixel array in which a plurality of unit pixels are arranged in a column direction and a row direction, like typical constitutions. The CMOS image sensor is driven by a line scanning fashion where a scanning is performed line by line, i.e., row by row or column by column, in sequence. Unlike the prior art, a sensing node SN 2  of a pixel in a currently scanning line, e.g., an nth row of  FIG. 4 , is shared with a sensing node SN 1  of a pixel in a lately scanned line, e.g., an n−1th row of  FIG. 4 , and receives photocharges from a photodiode PD 2  of the pixel in the currently scanning line. 
         [0041]      FIG. 4  illustrates one embodiment that the line scanning is performed row by row, in which the sensing nodes are shared with a nearest-neighboring pixel arranged in the same column. However, if the line scanning is a column scanning fashion, i.e., scanned column by column, the sensing nodes are shared with a nearest-neighboring pixel arranged in the same row. 
         [0042]    The sharing scheme of the sensing nodes is accomplished through a switching device which connects the sensing nodes of the neighboring pixels, wherein the switching device is controlled by a line select signal. To this end, the switching device in the embodiment of  FIG. 4  is configured with an NMOS transistor M 400  of which a source and a drain are connected between the sensing node SN 2  of the selected pixel and the sensing node SN 1  of the lately selected pixel, wherein a row select signal SX 2  of the currently scanning row is inputted a gate thereof. 
         [0043]    Referring to  FIG. 4 , the CMOS image sensor in accordance with the present invention will be set forth more fully in detail herebelow. 
         [0044]    In  FIG. 4 , it is shown only three unit pixels for the sake of illustrative purpose, which are arranged at intersections of a predetermined one column and an n−1th row, an nth row and an n+1th row, respectively. 
         [0045]    Considering the constitutions of the unit pixel of the nth row, the unit pixel includes a photocharge generator PD 2  for receiving a light from an object to generate photocharges, a sensing node SN 2  for receiving the photocharges from the photocharge generator PD 2 , a transfer unit M 421  for transferring the photocharges from the photocharge generator PD 2  to the sensing node SN 2 , a reset unit M 422  for resetting the sensing node SN 2 , an output unit M 423  for outputting an electric signal corresponding to the sensing node SN 2 , and an addressing unit M 424  of which one side is connected to the output unit M 423  for switching and addressing in response to a row select signal SX 2 . Herein, the photocharge generator PD 2  is configured with a photodiode. The addressing unit M 424  is configured with an NMOS transistor of which one side is connected to the output unit M 423  and the other side is connected to an output line. The output unit M 423  is configured with an NMOS transistor of which one side is connected to a first power terminal VCC and the other is connected to the addressing unit M 424 . The reset unit M 422  is configured with an NMOS transistor of which one side is connected to the first power terminal VCC and the other side is connected to the sensing node SN 2 . The transfer unit M 421  is configured with an NMOS transistor of which one side is connected to the photocharge generator PD 2  and the other is connected to the sensing node SN 2 . 
         [0046]    The unit pixels in the n−1th row and the n+1th row are identical in the constitution to the unit pixel of the nth row. Thus, further descriptions for them will be omitted herein. 
         [0047]    In addition, as described above, in order to increase the storage capacitance of the sensing node, the CMOS image sensor of the present invention further includes the switching device M 400  and M 450  for interconnecting the sensing node of the currently selected pixel to the sensing node of the nearest-neighboring pixel which is lately scanned, in response to the row select signal. In detail, the switching device M 400  and M 500  is configured with an NMOS transistor of which a source and a drain are connected to the sensing node of the currently selected pixel and the sensing node of the nearest-neighboring pixel which is lately scanned, wherein the row select signal is inputted to a gate thereof. 
         [0048]    For example, if the unit pixel of the nth row is being scanned now, the sensing node SN 1  of the unit pixel in the n−1th row which has been scanned lately and the sensing node SN 2  of the unit pixel in the nth row are shared with each other so as to receive the photocharges from the photodiode PD 2  of the unit pixel in the nth row. 
         [0049]    As stated above, since the CMOS image sensor of the present invention shares the sensing node of the nearest-neighboring unit pixel of a non-selected line when the specific unit pixel of a selected line is operating, it is possible to receive much more photocharges generated due to the enhanced fill-factor. That is, the storage capacitance of the sensing node is increased in virtue of the sharing scheme of the sensing node between nearest-neighboring pixels so that it is possible to implement a high quality CMOS image sensor. 
         [0050]    The present application contains subject matter related to the Korean patent application No. KR 2005-08654, filed in the Korean Patent Office on Jan. 31, 2005, the entire contents of which being incorporated herein by reference. 
         [0051]    While the present invention has been described with respect to certain preferred embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.