Abstract:
A memory includes a local word line driver for a memory array having a first word line and a second word line. The local word line driver includes a first selection transistor, a second selection transistor, and a middle transistor disposed between the first and second selection transistors. The first word line couples to the first selection transistor and the middle transistor, and the second word line couples to the middle transistor and the second selection transistor.

Description:
TECHNOLOGICAL FIELD 
       [0001]    Embodiments of the present invention relate generally to memory devices and, more particularly, relate to a programmable memory array, such as an array including multi-level flash memory cells, having a word line driver with reduced area. 
       BACKGROUND 
       [0002]    Memory devices such as, for example, semiconductor random access memory (RAM) circuits store logic states by applying either high or low voltage levels to memory cell transistors that comprise a memory cell array. As an example, flash memory cells store a charge on a floating gate that may, for example, be doped polysilicon. The stored charge changes a threshold voltage (Vt) of the memory cell. In a “read” operation, a read voltage is applied to the gate of the memory cell, and the corresponding indication of whether the memory cell turns on (e.g., conducts current) indicates the programming state of the memory cell. For example, a memory cell that conducts current during the “read” operation may be assigned a digital value of “1,” and a memory cell that does not conduct current during the “read” operation may be assigned a digital value of “0”. Charge may be added to and removed from the floating gate to program and erase the memory cell (e.g., to change the memory cell value from “1” to “0”). 
         [0003]    In order to control the application of voltage to the gate lines of selected cells in a memory cell array, gate line (or word line) voltage control circuits are typically employed. In general, memory cells are accessible by applying activation voltages to word lines and bit lines (drain lines). In this regard, word lines are typically used to activate memory cells and bit lines provide data to or retrieve data from activated memory cells. In a word line voltage control circuit, high and low (or negative) voltage levels may be applied to selected word lines of a memory cell array by a decoder circuit (e.g., a word line driver) in order to activate selected memory cells. In other words, when memory access is desired, an activation voltage may be applied to the corresponding word line by the word line driver to perform the desired function (e.g., read or write). In some cases, when memory access is not needed, the word line driver may apply a deactivation voltage to cease memory access function. 
         [0004]    Although the function of word line drivers, as generally described above, is relatively simple, conventional word line drivers have often suffered from various complicating conditions. In this regard, bouncing (e.g., voltage ripples that can occur when a word line is pulled down from an activation voltage) and leakage currents (e.g., resultant from shorting adjacent word lines or word lines and adjacent bit lines) are examples of conditions that can damage memory cells, increase power consumption and/or result in improper operation. To prevent or otherwise mitigate the impacts of such conditions, various designs have been put forth for word line drivers. However, current designs often require relatively large area footprints due to the inclusion of a large number of transistors relative to the number of word lines. In other words, conventional word line drivers often take up a relatively large area and have a relatively high ratio of transistors to word lines. 
         [0005]      FIG. 1  illustrates an example showing a conventional word line driver for a single word line (lwl 0 ) in which the word line driver requires three transistors for a 3:1 ratio of transistors to word lines.  FIG. 2  illustrates an alternative conventional word line driver for two word lines (lwl 0  and lwl 1 ), but for which five transistors (a 5:2 or 2.5:1 ratio) are required. The single word line driver of  FIG. 1  is augmented in the example of  FIG. 2  in order to support the provision of a word line driver capable of driving two word lines. 
         [0006]    Accordingly, it may be desirable to provide an improved word line driver in terms of area consumption. 
       BRIEF SUMMARY OF EXEMPLARY EMBODIMENTS 
       [0007]    Embodiments of the present invention are therefore provided that may enable a reduction in the area of a word line driver. Moreover, some embodiments may provide a word line driver with a 1.5 to 1 ratio of transistors to word lines. 
         [0008]    In one exemplary embodiment, a memory is provided that includes a local word line driver for a memory array having a first word line and a second word line. The local word line driver includes a first selection transistor, a second selection transistor, and a middle transistor disposed between the first and second selection transistors. The first word line couples to the first selection transistor and the middle transistor, and the second word line couples to the middle transistor and the second selection transistor. 
         [0009]    In another exemplary embodiment, a memory is provided that includes a group of local word line drivers for a memory array having a first word line and a second word line. Each local word line driver of the group includes a first selection transistor, a second selection transistor, and a middle transistor disposed between the first and second selection transistors. The first word line couples to the first selection transistor and the middle transistor, and the second word line couples to the middle transistor and the second selection transistor 
         [0010]    In another exemplary embodiment, a memory including a group word line decoder and a plurality of groups of local word line drivers for a memory array having a first word line and a second word line of a plurality of local word lines is provided. Each local word line driver of each group includes a first selection transistor, a second selection transistor, and a middle transistor disposed between the first and second selection transistors. The group word line decoder is configured to provide selection of one of the groups. A first word line couples to the first selection transistor and the middle transistor, and the second word line couples to the middle transistor and the second selection transistor. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S) 
         [0011]    Having thus described the invention in general terms, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and wherein: 
           [0012]      FIG. 1  illustrates an example of a conventional word line driver for a single word line; 
           [0013]      FIG. 2  illustrates an example of a conventional word line driver for two word lines; 
           [0014]      FIG. 3  illustrates a local word line driver according to an exemplary embodiment of the present invention; 
           [0015]      FIG. 4  illustrates a diagram of the local word line driver of  FIG. 3  scaled to drive sixteen word lines according to an exemplary embodiment; 
           [0016]      FIG. 5  illustrates an example of the scalability of a word line driver for up to 512 word lines according to an exemplary embodiment of the present invention; 
           [0017]      FIG. 6  illustrates a word line driver for up to 512 word lines and including a word line pre-decoder provided to enable selection of desired word lines among the 512 word lines according to an exemplary embodiment of the present invention; 
           [0018]      FIG. 7 , which includes  FIGS. 7A ,  7 B and  7 C, illustrates an example in which a single word line is selected for either program or read operation and other word lines have deselected output values according to an exemplary embodiment of the present invention; 
           [0019]      FIG. 8 , which includes  FIGS. 8A ,  8 B and  8 C, illustrates an alternative example in which a different word line is selected according to an exemplary embodiment of the present invention; 
           [0020]      FIG. 9 , which includes  FIGS. 9A and 9B , illustrates another alternative example in which negative voltage operation is provided to illustrate flexibility of implementation options provided by examples of embodiments of the present invention; 
           [0021]      FIG. 10 , which includes  FIGS. 10A and 10B , illustrates an example for providing an erase operation to memory cells of all word lines according to an exemplary embodiment of the present invention; 
           [0022]      FIG. 11  illustrates an example in which all word lines are deselected for a particular local word line driver according to an exemplary embodiment of the present invention; 
           [0023]      FIG. 12  shows an alternate decode method for de-selection of all word lines according to an exemplary embodiment of the present invention; and 
           [0024]      FIG. 13 , which includes  FIGS. 13A ,  13 B and  13 C, illustrates an example for providing selection of a particular local word line with de-selection of all other word lines being indicated by a negative voltage according to an exemplary embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0025]    Some embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. Indeed, various embodiments of the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. 
         [0026]    Some embodiments of the present invention may provide a mechanism by which improvements may be experienced in relation to the area taken up by a word line driver. In this regard, some embodiments of the present invention provide a reduced ratio of transistors to word lines to 1.5:1. 
         [0027]      FIG. 3  shows a word line driver according to an exemplary embodiment of the present invention. As shown in  FIG. 3 , a local word line driver (LWL driver)  10  is provided including a first transistor  12 , a second transistor  14  and a third transistor  16  (e.g., three n-channel metal oxide semiconductor (NMOS) field effect transistors) for driving two word lines (LWL 0  and LWL 1 ). Thus, the embodiment of  FIG. 3  provides a 1.5 NMOS transistor word line driver (having a ratio of 1.5 transistors per word line) in order to reduce the area of the local word line driver  10 . Each transistor may include a first terminal (e.g., either a drain or source terminal) and a second terminal (e.g., either a source or drain dependent upon the configuration of the first terminal) and a gate terminal. The transistors of the local word line driver  10  may be arranged such that a second terminal of a preceding transistor is connected to a first terminal of a subsequent transistor. Voltage sources with selectable voltage levels may be provided at each end of a chain of the three transistors (e.g., GWL 0  and GWL 1 , which may be defined as word line driver group selection values). For example, the first terminal of the first transistor  12  may be connected to GWL 0 , and the second terminal of the first transistor  12  may be connected to the first terminal of the second transistor  14 . The second terminal of the second transistor  14  may then be connected to the first terminal of the third transistor  16  and the second terminal of the third transistor  16  may be connected to GWL 1 . Values of GWL 0  and GWL 1  may be respective different ones of a positive voltage source, a negative voltage source or a ground voltage (e.g., 0V). In some embodiments, the first transistor  12  may be referred to as a first selection transistor, the second transistor  14  may be referred to as a middle transistor and the third transistor  16  may be referred to as a second selection transistor. 
         [0028]    The gates of the transistors of the local word line driver  10  may each be configured to receive an input signal used to select a corresponding one of the word lines (LWL 0  or LWL 1 ). In an exemplary embodiment, the gate of the first transistor  12  may be configured to receive a first word line selection input (WL_SEL 0 ), and the gate of the third transistor  16  may be configured to receive a second word line selection input (WL_SEL 1 ). The gate of the second transistor  14  may be configured to receive a selection middle input (WL_SEL_MID). 
         [0029]    Although the local word line driver  10  of  FIG. 3  can be used for two word lines, example embodiments of the present invention are also scalable to service of virtually any number of word lines. As an example, eight local word line drivers such as the one shown in  FIG. 3  could be utilized for selection of sixteen word lines.  FIG. 4  illustrates an example of a word line driver configured to enable selection with respect to sixteen word lines. In this regard, a word line driver for sixteen lines (LWL_ 16 ) may include a first LWL driver  21 , a second LWL driver  22 , five additional local word line drivers similar to the first and second LWL drivers  21  and  22  corresponding to third through seventh LWL drivers (not shown in detail, but represented by LWL drivers  23 - 27 ), and an eighth LWL driver  28 . Since each LWL driver includes two word lines (e.g., the first LWL driver  21  includes LWL 0 [ 0 ] and LWL 1 [ 0 ], the second LWL driver  22  includes LWL 0 [ 1 ] and LWL 1 [ 1 ], . . . , and the eight LWL driver  28  includes LWL 0 [ 7 ] and LWL 1  [ 7 ]) and there are a total of eight LWL drivers, the total number of word lines provided is sixteen. In the example of  FIG. 4 , the first LWL driver  21  and the other LWL drivers up to and including the eight LWL driver  28  define a word line driver group including sixteen word lines (e.g., LWL_ 16 ). 
         [0030]    In some cases, one or more units that each provide a particular number of LWL drivers (or groups of LWL drivers) may be provided in a scalable manner to provide for word line selection among a relatively large number of word lines. For example,  FIG. 5  illustrates a word line driver for up to 512 word lines, where 32 individual LWL_ 16   s  may be provided. In the example of  FIG. 5 , each individual LWL_ 16  may be provided with its own respective GWL values to enable selection of a particular one of the LWL_ 16   s  based on the GWL values provided. As shown in the example of  FIG. 5 , GWL 0  and GWL 1  are provided to represent the GWL values for the first LWL_ 16  which provides the sixteen word lines LWL 0 [ 14 ,  12 ,  10 , . . . ,  0 ] and LWL 1 [ 15 ,  13 ,  11 , . . . ,  1 ], GWL 2  and GWL 3  represent the GWL values for the second LWL —    16  which provides the sixteen word lines LWL 0 [ 30 ,  28 ,  26 , . . . ,  16 ] and LWL 1 [ 31 ,  29 ,  27 , . . . ,  17 ], corresponding GWLs for third to thirty-first LWL_ 16   s  (not shown), and GWL 62  and GWL 63  represent the GWL values for the thirty-second LWL_ 16  which provides the sixteen word lines LWL 0 [ 510 ,  508 ,  506 , . . . ,  496 ] and LWL 1 [ 511 ,  509 ,  507 , . . . ,  497 ]. As shown in  FIG. 5 , the gate lines of the transistors of each of the LWL drivers may share selection inputs. In other words, the selection inputs for the first LWL_ 16  (i.e., WL_SEL 0 [ 7 : 0 ], WL MID[ 7 : 0 ] and WL_SEL 1 [ 7 : 0 ]) may be shared with each other LWL_ 16 . Accordingly, individual word lines may be selected based on the GWL values as shown in  FIG. 6 . 
         [0031]      FIG. 6  illustrates a word line driver (LWL_ 512 ) for up to 512 word lines, where a word line pre-decoder (WL pre-decoder  30 ) may be provided to enable selection of desired word lines among the 512 word lines of the LWL_ 512 . In an exemplary embodiment, the WL pre-decoder  30  may include a GWL decoder  32  configured to receive address and/or grouping information to enable identification of the GWL value to be output to the LWL_ 512 . However, once selected by the GWL decoder  32 , a group of LWL drivers (e.g., a selected LWL_ 16 ) may provide selection of a particular word line for activation based on word lines selection inputs provided thereto by a WL_select_decoder  34 . 
         [0032]    Thus, the WL pre-decoder  30  may also include the WL_select_decoder  34  configured to receive address and/or grouping information to enable identification of word line selection values (i.e., via a selected code provided to WL_SEL 0 [ 7 : 0 ], WL_MID[ 7 : 0 ] and WL_SEL 1 [ 7 : 0 ]) to be provided to the LWL_ 512  to identify a selected word line to be activated. Based on the word line selection values and the GWL values provided to the LWL_ 512 , selection of desired word lines may be provided. Thus, for example, an address may be output to GWL[ 63 : 0 ] to provide that a corresponding desired one of the LWL_ 16   s  is selected, and thus the identified word line to be activated based on the word line selection values provided will be activated for the selected one of the LWL_ 16   s.  Of note, although the examples above describe employment in a LWL_ 512 , it should be appreciated that alternative embodiments are scalable to LWLs and decoding systems for use with smaller or larger scales. Thus, for example, embodiments with  1024  or  2048  word lines may also be supported as well as multi-sector common decoders. 
         [0033]    In general terms, a coded word line selection input may be provided based on the address (or addresses) to be written to, read or erased. The coded word line selection input may be generated based on the address to be written to in order to ensure that the corresponding word line within a particular LWL_ 16  is activated. In general, the word line selection input may otherwise enable each corresponding same word line in all LWL_ 16   s  if the GWL values permitted activation. Thus, the address to be written to, read or erased not only forms the basis for the coded word line selection inputs generated by the WL_select_decoder  34 , but also forms the basis for the GWL values provided by the GWL decoder  32 . The GWL decoder  32  provides GWL values to ensure de-selection of all word lines of LWL_ 16   s  that do not include the word line to be activated. The GWL decoder  32  provides GWL values to the LWL_ 16  that includes the word line to be activated that enable activation of the word line to be activated. Thus, WL pre-decoder  30  uses the address to be written to, read or erased to generate coded values that activate the word line that corresponds to the address. 
         [0034]      FIG. 7 , which includes  FIGS. 7A ,  7 B and  7 C, illustrates an example in which a single word line is selected (e.g., as indicated by the output value HV (e.g., 8V or 5V)) for either program or read operation, and other word lines have deselected output values of 0V. In the example of  FIG. 7 , HVS represents the value of GWL 0  and the value of GWL 1  is 0V. HVG represents an input voltage value (e.g., 9V) applied to word line selection lines as an alternative to 0V.  FIG. 7A  illustrates the first LWL_ 16 , and  FIGS. 7B and 7C  represent the second and third LWL_ 16   s,  respectively. Other LWL_ 16   s,  although includable to whatever scale is desired (e.g., LWL_ 512 , LWL_ 1024 , LWL_ 2048 ), are not shown since the example shown can be fully explained with three LWL_ 16 s. 
         [0035]    In order to select LWL 0 [ 0 ] (i.e., the first LWL of the first LWL_ 16 ), the same word line selection values may be provided to the word selection lines of each LWL_ 16  by the WL_select_decoder  34 . In this regard, the first LWL driver of each LWL_ 16  may have HVG applied to the WL_SEL 0 [ 0 ], 0V applied to the WL_MID[ 0 ] and HVG applied to the WL_SEL 1 [ 0 ]. Every other LWL driver (i.e., LWL drivers two through eight) may have 0V applied to their respective WL_SEL 0  lines (e.g., WL_SEL 0 [ 1 ], WL_SEL 0 [ 2 ], . . . , WL_SEL 0 [ 7 ]) and HVG applied to their respective WL_MID lines (e.g., WL_MID[ 1 ], WL_MID[ 2 ], . . . , WL_MID[ 7 ]) and WL_SEL 1  lines (e.g., WL_SEL 1 [ 1 ], WL_SEL 1 [ 2 ], . . . , WL_SEL 1 [ 7 ]). However, the GWL decoder  32  may only provide HVS for GWL 0  and all other GWL values (e.g., GWL 1 , GWL 2 , GWL 3 , GWL  4 , GWL 5 , . . . ) may be 0V. The results of these selection values being applied are shown in  FIGS. 7A to 7C . 
         [0036]    As shown in  FIG. 7A , by setting WL_SEL 0 [ 0 ] to HVG, the first transistor of the first LWL driver in  FIG. 7A  is gated and HV is output to LWL 0 [ 0 ]. HV may be clamped by HVG or HVS. Due to the application of 0V on WL_MID[ 0 ] and HVG on WL_SEL 1 [ 0 ], the second transistor of the first LWL driver is not gated and the third transistor is gated placing 0V on LWL 1 [ 0 ]. For the second through eighth LWL drivers of  FIG. 7A , the presence of 0V on WL_SEL 0 [ 1 ] to WL_SEL 0 [ 7 ] leaves each respective first transistor not gated, while HVG on WL_MID[ 1 ] to WL_MID[ 7 ] and WL_SEL 1 [ 1 ] to WL_SEL  1  [ 7 ] gate all respective transistors to pull all corresponding word lines (LWL 0 [ 1 ] to LWL 0 [ 7 ] and LWL 1 [ 1 ] to LWL 1 [ 7 ] down to 0V. 
         [0037]    Due to the application of 0V for GWL 2 , GWL 3 , GWL 4 , GLW 5 , . . . , by the GWL decoder  32 , each other LWL_ 16  provides a 0V output on all corresponding word lines as shown in  FIGS. 7B and 7C , even though the WL_select_decoder  34  provides the same word line selection inputs to each LWL_ 16 . 
         [0038]      FIG. 8 , which includes  FIGS. 8A ,  8 B and  8 C, illustrates an alternative example in which a different word line is selected. As shown, LWL 3 [ 1 ] is selected in  FIG. 8B  by applying 0V to all GWLs except GWL 3 , providing HV to all WL_SEL 0 [ 7 : 0 ] selection lines, and applying HV to WL_SEL 1 [ 1 ] and WLMID[ 7 , 6 , 5 , 4 , 3 , 2 , 0 ], while applying 0V to WL_SEL 1 [ 7 , 6 , 5 , 4 , 3 , 2 , 0 ] and WL_MID[ 1 ]. As shown in  FIGS. 8A and 8C , all other LWL_ 16   s  other than the LWL_ 16  of  FIG. 8B  will provide 0V on their corresponding word lines even though they share the same word line selection inputs as the LWL_ 16  of  FIG. 8B . Meanwhile, the LWL_ 16  of  FIG. 8B  provides 0V for the non-selected word line LWL 2 [ 1 ] and HV as an output on the selected word line LWL 3 [ 1 ]. Accordingly, in the example of  FIG. 8  as well, the WL_select_decoder  34  provides the same word line selection inputs to each LWL  16 , but the GWL decoder  32  only provides a GWL value to select the corresponding LWL_ 16  to provide the selection of the desired word line. 
         [0039]      FIG. 9 , which includes  FIGS. 9A and 9B , illustrates another alternative example in which negative voltage operation is provided to further illustrate the flexibility of implementation options provided by examples of embodiments of the present invention.  FIG. 9  shows negative voltage group decoding for an erase operation. In the example of  FIG. 9 , LWL 0 [ 7 : 0 ] and LWL 1 [ 7 : 0 ] are provided with a −V(negative voltage) output for providing an erase operation to memory cells of the corresponding word lines (see  FIG. 9A ). Meanwhile, all other word lines produce either 0V or +V−Vt (positive voltage minus a threshold voltage) as an output to prevent erasing operations with respect to the corresponding word lines (see  FIG. 9B  as an example applicable to all other LWL_ 16   s.  In the operation of the example of  FIG. 9 , the WL_select_decoder  34  provides the same word line selection inputs to each LWL_ 16 , namely +V(positive voltage) to each WL_SEL 0 [ 7 : 0 ] and WL_SEL 1  [ 7 : 0 ], while providing 0V to each WL_MID[ 7 : 0 ]. These word line selection inputs provide for the GWL value of each LWL_ 16  to be passed through as the word line output value. Since all other LWL_ 16   s  have GWL of 0V or +V (positive voltage) provided by the GWL decoder  32  and the first LWL_ 16  has −V (negative voltage) provided for GWL 0  and GWL 1 , the output of word lines LWL 0 [ 7 : 0 ] and LWL 1  [ 7 : 0 ] is −V (negative voltage) for providing the erase operation and all other word lines produce either 0V or +V−Vt (positive voltage minus threshold voltage). 
         [0040]      FIG. 10 , which includes  FIGS. 10A and 10B , illustrates an example for providing an erase operation to memory cells of all word lines. Similar to the example of  FIG. 9 , the WL_Select_decoder  34  provides the same word line selection inputs to each LWL_ 16 , namely +V (positive voltage) to each WL_SEL 0 [ 7 : 0 ] and WL_SEL 1 [ 7 : 0 ], while providing 0V to each WL_MID[ 7 : 0 ]. However, the GWL decoder  32  provides −V (negative voltage) for all GWL values thereby enabling −V (negative voltage) to be provided as the output of every word line (e.g., LWL 0 [ 7 : 0 ] to LWL 3 [ 7 : 0 ], and all other LWLs of any additional LWL_ 16   s  that may be provided. 
         [0041]      FIG. 11  illustrates an example in which all word lines are deselected for a particular LWL_ 16  (e.g., the second LWL_ 16  of the example LWL_ 512  described in connection with  FIG. 7 ). In this regard, the WL_select_decoder  34  provides +V (positive voltage) to the WL_SEL 0 [ 0 ], WL MID[ 7 , 6 , 5 , 4 , 3 , 2 , 1 ] and WL_SEL 1 [ 7 : 0 ], and provides 0V to the WL —  SEL 0 [ 7 , 6 , 5 , 4 , 3 , 2 , 1 ] and WL —  MID[ 0 ] in order to provide deselected 0V outputs to each word line in response to GWL 2  and GWL 3  having 0V applied thereto.  FIG. 12  shows an alternate decode method for de-selection of all word lines. In the example of  FIG. 12 , again the GWL decoder  32  has applied 0V to GWL 2  and GWL 3 , but the WL_select_decoder  34  has provided +V (positive voltage) to WL_SEL 0 [ 7 : 0 ] and WL_SEL 1 [ 7 : 0 ], and 0V to WL_MID[ 7 : 0 ]. 
         [0042]      FIG. 13 , which includes  FIGS. 13A ,  13 B and  13 C, illustrates an example for providing selection of LWL 0 [ 0 ] with de-selection of all other word lines being indicated by a negative voltage (−V). In the example of  FIG. 13 , essentially the same coding provided in the example of  FIG. 7  is employed except that 0V is replaced with −V (negative voltage). As such, in order to provide selection of word line LWL 0 [ 0 ], the WL_select_decoder  34  is configured to provide WL_SEL 0 [ 0 ], WL_SEL 1 [ 7 : 0 ] and WL_MID[ 7 , 6 , 5 , 4 , 3 , 2 , 1 ] with values of HVG. The WL_select_decoder  34  may also provide WL_SEL 0 [ 7 , 6 , 5 , 4 , 3 , 2 , 1 ] and WL_MID[ 0 ] with −V (negative voltage). Meanwhile, the GWL decoder  32  may be configured to provide HVS to GWL 0  and −V (negative voltage) to all other GWLs (e.g., GWL 1  to GLW 63 ). As a result, as shown in  FIG. 13A , LWL 0 [ 0 ] is selected (as indicated by the word line value of HV), while all other word lines are deselected (as indicated by the word line value −V (negative voltage) of  FIGS. 13A ,  13 B and  13 C). In each of the examples above, Pwell may be connected to the lowest voltage. 
         [0043]    Many modifications and other embodiments of the inventions set forth herein will come to mind to one skilled in the art to which these inventions pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the inventions are not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Moreover, although the foregoing descriptions and the associated drawings describe exemplary embodiments in the context of certain exemplary combinations of elements and/or functions, it should be appreciated that different combinations of elements and/or functions may be provided by alternative embodiments without departing from the scope of the appended claims. In this regard, for example, different combinations of elements and/or functions than those explicitly described above are also contemplated as may be set forth in some of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.