Abstract:
A thin film transistor having a semiconductor layer arranged on a substrate, a gate insulation layer arranged on the substrate and on a semiconductor layer, and a gate arranged on the gate insulation layer, the gate insulation layer arranged to have a thickness from equal to a thickness of the semiconductor layer to 1.5 times of thickness of the semiconductor layer. The gate insulation layer can be a nitride film only, an oxide film only, or a laminated film made up of both nitride layers and oxide layers. The thin film transistor can be incorporated into a design for a flat panel display.

Description:
CLAIM OF PRIORITY  
         [0001]    This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. §119 from an application for THIN FILM TRANSISTOR earlier filed in the Korean Intellectual Property Office on 25 Jun. 2003 and there duly assigned Serial No. 2003-41751.  
         BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the invention  
           [0003]    The present invention relates to a novel design for a thin film transistor (or TFT) that maximizes the mobility in the semiconductive layer.  
           [0004]    2. Description of Related Art  
           [0005]    In thin film transistors used in flat panel display devices, if the thickness of polysilicon film used as a semiconductor layer is decreased, the mobility is increased due to the improved crystallization characteristics, and it is possible to decrease the thickness of the gate insulation film (or gate oxide film) so that the threshold voltage of the thin film transistor may be decreased.  
           [0006]    As the thickness of gate insulation film is decreased, the electrical characteristics, for example, threshold voltage (or V th ) characteristics are improved. However, there is a disadvantage in that decreasing the thickness of the gate insulation film also can causes breakage of the device due to breakdown. On the other hand, there have been problems in that mobility is decreased and the V th  is increased when the thickness of the gate insulation film is increased.  
           [0007]    A technology for increasing carrier mobility in a channel layer under gate insulation film is disclosed in Korean Patent No. 10-0267491. In order to increase mobility in a channel layer of a semiconductor layer, the gate oxide film is formed on the pretreated surface of the silicon substrate, following pretreating the surface of silicon substrate to reduce the surface roughness of the silicon substrate. Furthermore, a technology for increasing mobility by forming gate oxide film on the tilted step after forming a step tilted to an angle of 4 degrees on silicon substrate is disclosed in Korean Patent Publication No. 2000-0025409.  
           [0008]    Thus, the above documents relate to methods for increasing mobility by pretreating a silicon substrate or increasing mobility by forming step on the silicon substrate before forming gate oxide film in semiconductor device. However, a technology capable of preventing breakage of the TFT as maintaining characteristics of mobility and threshold voltage values of the TFT when forming gate insulation film on semiconductor layer formed of polysilicon film like thin film transistor TFTs in flat panel display devices is not suggested in these documents. Therefore, what is needed is a method of making and a design for a TFT that results in a TFT with good mobility characteristics and good threshold voltage characteristics while maintaining good electrical characteristics.  
         SUMMARY OF THE INVENTION  
         [0009]    It is therefore an object of the present invention to provide an improved thin film transistor design.  
           [0010]    It is also an object of the present invention to provide a method of making a thin film transistor that produces a thin film transistor having good mobility while not having voltage breakdown.  
           [0011]    It is further an object of the present invention to provide an improved design for a thin film transistor by controlling a ratio of thicknesses of the of gate insulation film to the thickness of the polysilicon active layer.  
           [0012]    It is another object of the present invention to provide a thin film transistor having improved electrical characteristics without device quality deterioration.  
           [0013]    These and other objects can be achieved by a thin film transistor having a semiconductor layer formed on a substrate, a gate insulation film formed over the substrate and over the semiconductor layer and a gate formed on the gate insulation film on the upper part of the semiconductor layer, where the ratio of the thickness of the gate insulation film to the thickness of the semiconductor layer is between 1.0 to 1.5. Preferably, the semiconductor layer including the channel layer is crystalized polysilicon and is subjected to an HF pretreatment resulting to further improved mobility. Preferably, the novel thin film transistor is part of a flat panel display device structure.  
           [0014]    The flat panel display device further comprises a third insulation film formed between a lower electrode as the pixel electrode and the source/drain electrode and including a via hole for connecting the pixel electrode to one of the source/drain electrodes, an organic thin film layer formed on the lower electrode, and an upper electrode formed on the organic thin film layer. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]    A more complete appreciation of the invention, and many of the attendant advantages thereof, will be readily apparent as the same becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings in which like reference symbols indicate the same or similar components, wherein:  
         [0016]    [0016]FIG. 1 is a cross sectional view of a thin film transistor according to preferred embodiment of the present invention;  
         [0017]    [0017]FIG. 2 is a graph empirically illustrating a mobility in a TFT versus the ratio of the thicknesses of the gate insulation film to the polysilicon film for cases where the polysilicon is pretreated by HF and where the polysilicon film is not pretreated; and  
         [0018]    [0018]FIG. 3 illustrates a cross section view of flat panel display device using the novel thin film transistor of FIG. 1 according to a preferred embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0019]    Turning now to the figures, FIG. 1 illustrates a cross section view of thin film transistor  200  for flat panel display device according to a preferred embodiment of the present invention. Referring to FIG. 1, a buffer layer  20  is formed on an insulation substrate  10 , and a semiconductor layer  30  made of polysilicon film is formed on the buffer layer  20 . The semiconductor layer  30  includes source/drain regions  31  and  35  which are doped with high concentration impurities having a P or N type conductivity. A portion of the semiconductor layer  30  between the source/drain regions  31  and  35  is a channel layer  33  which is an intrinsic region. A gate insulation film  40  is formed on the buffer layer  20  and on top of the semiconductor layer  30 , and a gate  45  is formed on the gate insulation film  40  over the channel layer  33  of the semiconductor layer  30 . As illustrated in FIG. 1, gate insulation film  40  has a thickness t 40  and semiconductor layer  30  has a thickness t 30 .  
         [0020]    After formation of the semiconductor layer  30  and the gate insulation film  40 , a gate layer  45  is formed on the gate insulation film  40 . Then, an interlayer insulation film  50  is formed on the gate insulation film  40  and on the gate  45 . Interlayer insulation film  50  is perforated by contact holes  51  and  55  exposing the doped source/drain regions  31  and  35  respectively of semiconductor layer  30 . Contact holes  51  and  55  are formed by etching the interlayer insulation film  50 . Source/drain electrodes  61  and  65  are formed in contact holes  51  and  55  respectively to electrically connected to the source/drain regions  31  and  35  respectively through the contact holes  51  and  55 , respectively.  
         [0021]    Turning now to FIG. 2, FIG. 2 illustrates empirical results of measured mobility in the TFT of FIG. 1 versus the ratio R of the thickness t 40  of the gate insulation film to the thickness t 30  of the semiconductor layer. In FIG. 2, two lines are illustrated. The first line (line  1 ) in FIG. 2 illustrates the measured mobility μ versus the thickness ratio R when no pretreatment process is carried out on the semiconductor layer after the deposition and patterning of the semiconductor layer and after the crystallizing the silicon film. The second line (line  2 ) in FIG. 2 illustrates the measured mobility μ versus the thickness ratio R when the patterned semiconductor layer  30  is subjected to an HF pretreatment.  
         [0022]    Referring to FIG. 2, it is clear that the mobility is greatest when the t 40  to t 30  ratio R is in the preferred range of 1.0 to 1.5. Expressed as an inequality, the ratio R=t 40 /t 30  preferably satisfies the inequality 1.0≦R≦1.5. In this 1.0 to 1.5 range, the mobility varies little within this range and the mobility in this range is essentially saturated. In addition, in this preferred 1.0 to 1.5 range, the mobility is higher when the polysilicon is pretreated with HF than when no pretreatment occurs. When the ratio of the thicknesses of t 40  to t 30  exceeds 1.5 and is thus outside the preferred range, the mobility falls off sharply as illustrated empirically in FIG. 2. At the other extreme, when the thickness t 40  of the gate insulation film  40  is less than the thickness t 30  of the polysilicon film of the semiconductor layer  30 , the uniformity of film thickness t 40  of the gate insulation film  40  is deteriorated. In particular, a protrusion part generated during crystallization of the polysilicon film using laser is exposed, and failure is caused during TFT fabrication process accordingly if thickness t 40  of the gate insulation film  40  is less than thickness of the polysilicon film t 30 . For this reason, it is not preferable to make the TFT where the ratio R of t 40  to t 30  is less than 1.0.  
         [0023]    The gate insulation film  40  is formed of gate insulation material such as oxide film or nitride film in a single layer structure or formed of the oxide film and nitride film in a laminated layer structure, and the polysilicon film is formed using an ordinary crystallization method such as solid phase crystallization method or laser crystallization method.  
         [0024]    Turning now to FIG. 3, FIG. 3 illustrates a cross section view of flat panel display device  300  using a thin film transistor according to a preferred embodiment of the present invention. The TFT used in flat panel display  300  may be the same as TFT  200  of FIG. 1 but this invention is not limited thereto. Referring to FIG. 3, a buffer layer  110  is formed on an insulation substrate  100 , and a semiconductor layer  120  is formed on the buffer layer  110 . The semiconductor layer  120  includes source/drain regions  125  and  121  which are doped with high concentration impurities having a P or N type conductivity. A portion of the semiconductor layer  120  between the source/drain regions  121  and  125  is a channel layer  123  remains intrinsic and is not doped. A gate insulation film  130  is formed on the buffer layer  110  and on the semiconductor layer  120 , and a gate  135  is formed on the gate insulation film (or gate insulation layer)  130  over the intrinsic channel layer  123  of the semiconductor layer  120 .  
         [0025]    The semiconductor layer  120  includes polysilicon film crystallized through a crystallization method. The gate insulation film  130  includes one of a single-layered film of silicon oxide or silicon nitride and a multi-layered film of silicon oxide and silicon nitride. The gate insulation film  130  is preferably formed to has a thickness t 130  between 1.0 and 1.5 times a thickness t 120  of the semiconductor layer  120  to boost the mobility in the semiconductor layer  120 . Then, an interlayer insulation film  140  is formed on the gate insulation film  130  and on the gate  135 . Interlayer insulation film  140  is perforated by contact holes  141  and  145  respectively to expose source/drain regions  121  and  125  respectively of semiconductor layer  120 . Contact holes  141  and  145  respectively are filled in by source/drain electrodes  155  and  151  respectively. Source/drain electrodes  151  and  155  respectively form electrical contact with source/drain regions  121  and  125  respectively on semiconductor layer  120 .  
         [0026]    A passivation layer  160  and a planarization layer  165  are formed over the substrate and include a via hole  170  exposing a portion of one of the source/drain electrodes  151  and  155  (drain electrode  155  illustrated in FIG. 3). A lower electrode  175  is formed on the planarization layer  165  and fills via hole  170  to form electrical contact with source/drain electrode  151  and  155  ( 151  illustrated in FIG. 3). A pixel defining layer  180  having an opening  185  for exposing the lower electrode  175  is formed over the substrate and an organic thin film layer  190  and an upper electrode  195  are formed on the lower electrode  175  and the pixel defining layer  180 . Therefore, organic electroluminescence (EL) device including the lower electrode  175 , the organic thin film layer  190  and the upper electrode  195  is fabricated and forms electrical contact to the underlying TFT.  
         [0027]    Preferably, the lower electrode  175  is made out of a light reflective material and preferably the upper electrode  195  is made out of an optically transmissive material to allow light generated in the film layer  190  to escape from the top of the device through upper electrode  195 . The organic thin film layer  190  can be made out of a hole injection layer, a hole transport layer, an organic light emitting layer, a hole barrier layer, an electron transport layer or an electron injection layer.  
         [0028]    As described in the above, a thin film transistor according to preferred embodiments of the present invention has merits in that the thin film transistor not only optimizes mobility, but also improves characteristics of device and prevents failure of the device by optimizing thickness of the gate insulation film in relation to the thickness of the polysilicon film.  
         [0029]    While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.