Abstract:
Disclosed herein is a CMOS image sensor for improving an image quality by removing an offset noise occurred in a path difference. The CMOS image sensor includes a pixel array including a plurality of a first pixel and a second pixel; a first analog data bus and a second analog data bus for transferring a first pixel data and a second pixel data, each generated from the first pixel and the second pixel; a first analog signal processing unit and a second analog signal processing unit, each for amplifying an inputted pixel data to extract a pure pixel data; and a swapping unit for swapping the first pixel data and the second pixel data to thereby delivery each of first and second swapped pixel data into each of the first and the second analog signal processing unit.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to a complementary metal oxide semiconductor (CMOS) image sensor; and, more particularly, to a CMOS image sensor for improving an image quality by removing an offset noise caused by a path difference.  
       BACKGROUND OF THE INVENTION  
       [0002]     In general, a complementary metal oxide semiconductor (CMOS) image sensor is a semiconductor device that converts an optical image to an electrical signal. The image sensor is basically classified into a charge coupled device (CCD) image sensor and a complementary metal oxide semiconductor (CMOS) image sensor.  
         [0003]     Among the image sensors, the CCD image sensor is the semiconductor device that each of metal-oxide-silicon (MOS) capacitors is placed in close proximity and charge carriers are stored in and transferred. The CMOS image sensor adopts a switching method for sequentially detecting outputs of many metal oxide semiconductor (MOS) transistors constituent with the number of pixels based on CMOS technology.  
         [0004]     The CMOS image sensor is cheaper than the CCD image sensor and has power consumption as much as 1/10 of that of the CCD image sensor.  
         [0005]     A conventional CMOS image sensor which process image data (analog signals) acquired from pixels is described in  FIG. 1 .  
         [0006]      FIG. 1  is a block diagram showing a conventional COMS image sensor. In detail,  FIG. 1  describes a data path transmitting an analog data generated a pixel array in the conventional COMS image sensor.  
         [0007]     As shown in  FIG. 1 , the conventional CMOS image sensor includes a pixel array  10 , a correlated double sampling (CDS) block  20  and an analog signal processor (ASP)  30 . The pixel array includes plural red (R), green (G) and blue (B) pixels arranged in an M×N matrix. The correlated double sampling (CDS) block  20  including CDS circuits at each column is located at a lower side of the pixel array  10 . The analog signal processor (ASP)  30  processing the analog signals outputted from the CDS block  20  is located at a right side of the pixel array  10 .  
         [0008]     The output signals of the CDS block  20  are transferred to the ASP  30  through an analog data bus. The analog data bus is constituent with a first analog data bus  52  and a second analog data bus  54 .  
         [0009]     The output signals of the CDS block  20  are loaded on the first analog data bus  52  or the second analog data bus  54  by a selecting block  60  which is controlled by a select signal, e.g., CS 0 , generated from a column driver  40 . The selecting block  60  includes plural switches for selectively delivery the outputs of CDS block  20  into one of the first analog data bus  52  or the second analog data bus  54 .  
         [0010]     The ASP  30  has an ASP-A  32  and an ASP-B  34  to amplify each analog data transferred through the first analog data bus  52  and the second analog data bus  54 .  
         [0011]     The CDS block  20  samples a reset signal and a data signal from each pixel and supplies the sampled reset and data signals on the analog data bus. Then, the ASP  30  calculates a difference between the reset signal and the data signal and amplifies the difference. Accordingly, an analog pixel data of a captured object can be obtained.  
         [0012]     Further, the column driver  40  receives a column address to thereby generate the select signals, e.g., CS 0 .  
         [0013]     Hereinafter, the process of the CMOS image sensor is described as follows.  
         [0014]     When the CMOS image sensor reads pixel data, the pixels arranged along one row of the pixel array  10  are transferred to the CDS circuits of the CDS block  20  at once and at the same time (at the same clock). Under the control of a column driver  40 , output signals of the CDS circuits are loaded on one of the first analog data bus  52  and the second analog data bus  54  by a selecting block  60  and are sequentially transferred to the ASP  30 .  
         [0015]     For example, a sequence that pixel data generated from a first row and a second row in the pixel array  10  are loaded on the first analog data bus  52  and the second analog data bus  54  is as the following Table 1.  
                                                                 TABLE 1                                   The first row   The second row                                    The first   B 11     B 13     B 15     . . .   G 21     G 23     G 25     . . .       analog data bus       The second   G 12     G 14     G 16     . . .   R 22     R 24     R 26     . . .       analog data bus                  
 
         [0016]     Referring to Table 1, among pixel data located at the same row, pixel data corresponding to every odd column line are loaded on the first analog data bus and pixel data corresponding to every even column line are loaded on the second analog data bus.  
         [0017]     In detail, even the same green (G) pixel data pass through the path A on the first analog data bus or the path B on the second analog data bus according to the located column line. Also, the Red (R) and Blue (B) pixel data pass through the path A or path B according to the located column. That is, pixel data are transmitted through different paths according to pixel location, not a type of pixel. Thus, even the same type pixel data have an offset because of passing through the different paths.  
         [0018]     As above described, if the offset occurs because of a path difference, an offset noise appears in a real image to thereby deteriorate an image quality.  
       SUMMARY OF THE INVENTION  
       [0019]     It is, therefore, an object of the present invention to provide a CMOS image sensor for improving an image quality by removing an offset noise caused by a difference between paths which same type pixel data go through.  
         [0020]     In an aspect of the present invention, there is provided a CMOS image sensor, including: a pixel array including a plurality of a first pixel and a second pixel; a first analog data bus and a second analog data bus for transferring a first pixel data and a second pixel data, each generated from the first pixel and the second pixel; a first analog signal processing unit and a second analog signal processing unit, each for amplifying an inputted pixel data to extract a pure pixel data; and a swapping unit for swapping the first pixel data and the second pixel data to thereby delivery each of first and second swapped pixel data into each of the first and the second analog signal processing unit.  
         [0021]     In accordance with another aspect of the present invention, there is provided an apparatus for converting image data into electric signals, including: a pixel array including a plurality of a first pixel and a second pixel; a first analog data bus and a second analog data bus for transferring a first pixel data and a second pixel data, each generated from the first pixel and the second pixel; a first analog signal processing unit and a second analog signal processing unit, each for amplifying an inputted pixel data to extract a pure pixel data; and a swapping unit for swapping the first pixel data and the second pixel data to thereby delivery each of first and second swapped pixel data into each of the first and the second analog signal processing unit.  
         [0022]     In accordance with another aspect of the present invention, there is provided a method for processing a pixel data in an apparatus for converting image data into electric signals, including the steps of: loading a first pixel data and a second pixel data, each generated from the first pixel and the second pixel, on the first analog data bus and the second analog data bus; swapping the first pixel data and the second pixel data to thereby delivery each of first and second swapped pixel data into each of a first and a second analog signal processing unit; and amplifying the pixel data transferred to the first analog signal processing unit and the second analog signal processing unit. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0023]     The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments given in conjunction with the accompanying drawings, in which:  
         [0024]      FIG. 1  is a block diagram showing a conventional COMS image sensor;  
         [0025]      FIG. 2  is a block diagram describing a CMOS image sensor in accordance with an embodiment of the present invention;  
         [0026]      FIG. 3A  and  FIG. 3B  are block diagrams illustrating an operation of a swapping block in accordance with the present invention;  
         [0027]      FIG. 4  is a block diagram showing an ASP block in accordance with another embodiment of the present invention;  
         [0028]      FIG. 5  is a waveform demonstrating an operation of a de-multiplexer shown in  FIG. 4 ;  
         [0029]      FIG. 6  is a block diagram depicting an ASP block in accordance with another embodiment of the present invention;  
         [0030]      FIG. 7  is a block diagram showing a re-swapping block shown in  FIG. 6 ; and  
         [0031]      FIG. 8  is a waveform illustrating an operating of the re-swapping block shown in  FIG. 7 . 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0032]     Hereinafter, a CMOS image sensor in accordance with the present invention will be described in detail referring to the accompanying drawings.  
         [0033]      FIG. 2  is a block diagram describing a CMOS image sensor in accordance with an embodiment of the present invention.  
         [0034]     As shown in  FIG. 2 , the CMOS image sensor of the present invention includes a first analog data bus  112  and a second analog data bus  114  in order to transfer pixel data. Also, the CMOS image sensor includes a pixel array  100 , a correlated double sampling (CDS) block  120  and an analog signal processor (ASP)  130 . The pixel array includes plural red (R), green (G) and blue (B) pixels arranged in an M×N matrix. The correlated double sampling (CDS) block  120  including CDS circuits at each column is located at a lower side of the pixel array  100 . The analog signal processor (ASP)  130  processing the analog signals outputted from the CDS block  120  is located at a right side of the pixel array  100 .  
         [0035]     The output signals of the CDS block  120  are loaded on the first analog data bus  112  or the second analog data bus  114  by a selecting block  160 , which is controlled by a select signal (CS 0 , CS 1 , CS 2  . . . ) generated from a column driver  140 .  
         [0036]     Particularly, the ASP  130  includes a swapping block  200  and amplifying blocks ASP-A  132  and an ASP-B  134  to amplify output signals of the swapping block  200 . The swapping block  200  swaps the pixel data so that same type pixel data among the pixel data transferred through the first analog data bus  112  and the second analog data bus  114  pass through a same path.  
         [0037]      FIG. 3A  and  FIG. 3B  are block diagrams illustrating an operation of a swapping block in accordance with the present invention.  
         [0038]     Hereinafter, an operation of the ASP  130  included in the CMOS image sensor according to the present invention is described referring to  FIG. 3A  and  FIG. 3B .  
         [0039]     First,  FIG. 3A  shows the case that the swapping block  200  passes pixel data located at the first row, which are loaded on the first analog data bus  112  and the second analog data bus  114 .  
         [0040]     The CDS block  120  samples and saves the pixel data located at the first row, e.g., “B 11 , G 12 , B 13 , G 14 , B 15 , G 16  . . . ”. Then, the pixel data at the same row and every odd column, i.e., “B 11 , B 13 , B 15  . . . ”, are loaded on the first analog data bus  112  by a selecting block. Also, the pixel data located at the same row and every even column, i.e., “G 12 , G 14 , G 16  . . . ”, are loaded on the second analog data bus  114  by the selecting block. Continuously, the swapping block  200  passes the pixel data on the first analog data bus  112  and the second analog data bus  114 . That is, the pixel data at the same row and every odd column are transferred to A-path through the ASP-A  132  and the pixel data at the same row and every even column are transferred to B-path through the ASP-B  134 . Accordingly, the blue (B) pixel data at the first row, i.e., “B 11 , B 13 , B 15  . . . ”, go through A-path, and the green (G) pixel data at the first row, i.e., “G 12 , G 14 , G 16  . . . ”, go through B-path. A pixel data sequence can be briefly described as the following Table 2.  
                                                                 TABLE 2                                   The first row   The second row                                    A-Path   B 11     B 13     B 15     . . .   R 22     R 24     R 26     . . .       B-Path   G 12     G 14     G 16     . . .   G 21     G 23     G 25     . . .                  
 
         [0041]      FIG. 3B  shows the case that the swapping block  200  swaps pixel data at the second row, which are loaded on the first analog data bus  112  and the second analog data bus  114 .  
         [0042]     Referring to  FIG. 3B , the swapping block  200  swaps the green (G) pixel data loaded on the first analog data bus  112 , i.e., “G 21 , G 23 , G 25  . . . ”, for the red (R) pixel data loaded on the second analog data bus  114 , i.e., “R 22 , R 24 , R 26  . . . ”. So, the outputs of the swapping block  200  are crossed and outputted. Continuously, each output of the swapping block  200  is transferred to A-path or B-path through the ASP-A  132  or ASP-B  134 . As can be seen the second row in Table 2, the red (R) pixel data at the second row, i.e., “R 22 , R 24 , R 26  . . . ”, go through A-path, and the green (G) pixel data at the second row, i.e., “G 21 , G 23 , G 25  . . . ”, go through B-path.  
         [0043]     As described above, the ASP  130  of the present invention has the swapping block  200  which passes the pixel data located at the every even row and swaps the pixel data located at the every odd row. Therefore, the red (R) pixel data and the blue (B) pixel data go through A-path and the green (G) pixel data go through B-path.  
         [0044]     Consequently, in the present invention, the CMOS image sensor having the swapping block  200  which makes all green (G) type pixel data go through the same path. It is well known by people skilled in the art that the green (G) pixel data is an important factor determining a luminance, a brightness, chroma, etc. That is, the CMOS image sensor improves an image quality by removing the offset noise caused by the path difference e.g., green (G) type pixel data go through different paths.  
         [0045]     Hereinafter, when the same type pixel data are transferred through the same path by the swapping block  200 , rearrangement methods for preventing input and output data of ASP block from confusing a sequence of original pixel data are described.  
         [0046]      FIG. 4  is a block diagram showing an ASP block in accordance with another embodiment of the present invention.  
         [0047]     As shown in  FIG. 4 , the ASP block  130  according to the present invention includes the first analog data bus  112  and the second analog data bus  114  in order to transfer pixel data. Also, the ASP block  130  includes a swapping block  200 , amplifying blocks ASP-A  132  and an ASP-B  134 , a de-multiplexer  210  and an analog to digital converter (ADC) block  220 . The swapping block  200  makes the same type of pixel data, which is transferred to the first analog data bus  112  and the second analog data bus  114 , go through the same path. The amplifying blocks ASP-A  132  and an ASP-B  134  amplify output signals of the swapping block  200  and put the output signals on A-path and B-path. The de-multiplexer  210  outputs the pixel data of A-path and B-path to only one output line in turns; also, makes a sequence of the pixel data swapped by the swapping block  200  as that of an original image in response to a swap control signal swp_ctr. The ADC block  220  is for converting the output data of the de-multiplexer  210  into digital signals (OUT).  
         [0048]     Referring to  FIG. 3A  and  FIG. 3B , the swapping block  200  makes the red (R) pixel data and the blue (B) pixel data go through A-path and the green (G) pixel data go through B-path by passing the pixel data corresponding to the every even row and swapping the pixel data corresponding to the every odd row.  
         [0049]     The de-multiplexer  210  outputs the pixel data from A-path and B-path to only one output line and adjusts the output sequence in response to the swap control signal swp_ctr.  
         [0050]      FIG. 5  is a waveform demonstrating an operation of a de-multiplexer  210 .  
         [0051]     Hereinafter, with reference to the drawings, the de-multiplexer  210  of the present invention will be explained in detail.  
         [0052]     In  FIG. 5 , ‘a de-multiplexer select path signal’ according to the swap control signal swp_ctr and ‘de-multiplexer output’ according to the de-multiplexer select path signal are provided.  
         [0053]     In case of ‘α’, the pixel data at the first row are loaded on the A-path and B-path; and, in case of ‘β’, the pixel data at the second row are loaded on the A-path and B-path.  
         [0054]     First, in case of ‘α’, since the swap control signal swp_ctr is a logic level ‘L’, the de-multiplexer  210  outputs pixel data, in turns, as a sequence from data on the A-path to data on the B-path. Accordingly, pixel data B 11  loaded on the A-path is outputted, and then, pixel data G 12  loaded on the B-path is outputted.  
         [0055]     Next, in case of ‘β’, since the swap control signal swp_ctr is logic level ‘H’, the de-multiplexer  210  outputs pixel data, in turns, as a sequence from data on the B-path to data on the A-path. Accordingly, pixel data G 21  loaded on the B-path are outputted, and then pixel data R 22  loaded on the A-path is outputted.  
         [0056]     As described above, the sequence of the pixel data outputted by the de-multiplexer  210  is shown as the following Table 3.  
                                                                                         TABLE 3                                   The case of ‘α’   The case of ‘β’           (The first row)   (The second row)                                    De-   B 11     G 12     B 13     G 14     B 15     G 16     . . .   G 21     R 22     G 23     R 24     G 25     R 26     . . .       multiplexer                  
 
         [0057]     Referring to Table 3, the de-multiplexer  210  rearranges the sequence of the pixel data swapped by the swapping block  200  and outputs the rearranged pixel data.  
         [0058]     Therefore, to remove the offset noise caused by the path difference of the same type pixel data, e.g., a green (G) type pixel data, the CMOS image sensor of the present invention has the swapping block  200  which makes the same type pixel data go through the same path. Also, the de-multiplexer  210  returns the swapped sequence of the pixel data to the sequence of the original image data.  
         [0059]      FIG. 6  is a block diagram depicting an ASP block in accordance with another embodiment of the present invention.  
         [0060]     Referring to  FIG. 6 , the ASP block according to the present invention includes the first analog data bus  112  and the second analog data bus  114  to transfer pixel data. Also, the ASP block  130  includes a swapping block  200 , amplifying blocks ASP-A  132  and an ASP-B  134 , a de-multiplexer  210  and a re-swapping block  230 . The swapping block  200  makes green (G) pixel data, among the pixel data transferred to the first analog data bus  112  and the second analog data bus  114 , go through the same path. The amplifying blocks ASP-A  132  and an ASP-B  134  amplify output signals of the swapping block  200  and put the output signals on A-path and B-path. The de-multiplexer  210  outputs pixel data of A-path and B-path to only one output line in turns, regardless of a sequence of an original image. The ADC block  220  converts the output data of the de-multiplexer  210  to digital signals. Also, the re-swapping block  230  is for outputting the same sequence of the pixel data as that of the pixel array by re-swapping output digital signals of the ADC block  220 .  
         [0061]     The process of the CMOS image sensor is described as follows.  
         [0062]     Referring to  FIG. 3A  and  FIG. 3B , the swapping block  200  makes red (R) pixel data and blue (B) pixel data go through A-path and green (G) pixel data go through B-path by passing the pixel data corresponding to every even row and swapping the pixel data corresponding to every odd row.  
         [0063]     Then, the de-multiplexer  210  outputs the pixel data of A-path and B-path to only one output line in turns. The output pixel data of the de-multiplexer  210  are explained as the following Table 4.  
                                                                                         TABLE 4                                   The first row   The second row                                    De-   B 11     G 12     B 13     G 14     B 15     G 16     . . .   R 22     G 21     R 24     G 23     R 26     G 25     . . .       multiplexer                  
 
         [0064]     As shown in Table 4, the pixel data located at the second row are outputted in sequence of “R 22 , G 21 , R 24 , G 23 , R 26 , G 25  . . . ”. The above output sequence is different from a sequence of the pixel array in the matrix, i.e. the red (R) pixel data are outputted before the green (G) pixel data are outputted.  
         [0065]     That is, because the swapping block  200  swaps the pixel data in order to make the green (G) pixel data go through the same path, a re-swapping process is needed so as to output the same sequence of the swapped pixel data as the sequence of the pixel array.  
         [0066]     On the other hand, the output signals of the de-multiplexer  210  are converted to digital signals by the ADC block  220 . The ADC block  220  maintains the sequence of the output signals of the de-multiplexer  210  because the ADC block  220  outputs the output signals as a sequence of input data.  
         [0067]     The re-swapping block  230  re-swaps the output signals of the ADC block  220  correspond to the pixel data swapped by the swapping block  200  and outputs the signals as the sequence of the pixel array.  
         [0068]     That is the re-swapping block  230  passes the signals corresponding to the pixel data which are located at the first row, and so do not swapped by the swapping block  200 . Also, the re-swapping block  230  swaps the signals corresponding to the pixel data at every even column for the signals corresponding to the pixel data at every odd column, among the signals corresponding to the pixel data at the second row.  
         [0069]     For example, the re-swapping block  230  holds pixel data R 22  at the second column and outputs pixel data G 21  at the first column. Then, the re-swapping block  230  outputs pixel data R 22  at the second column. In this way, the re-swapped pixel data are shown in Table 5, as follows.  
                                                                                         TABLE 5                                   The first row   The second row                                    Re-swapping   B 11     G 12     B 13     G 14     B 15     G 16     . . .   G 21     R 22     G 23     R 24     G 25     R 26     . . .       block                  
 
         [0070]     As shown in Table 5, the ASP block  130  of this invention has the re-swapping block  230  which re-swaps the sequence of the pixel data swapped by the swapping block  200 . so, it is possible to reconstruct the original pixel image.  
         [0071]     Hereinafter, an embodiment of said re-swapping block  230  is shown in  FIG. 7  and  FIG. 8 .  
         [0072]      FIG. 7  is a block diagram showing a re-swapping block  230  shown in  FIG. 6 .  
         [0073]     Referring to  FIG. 7 , the re-swapping block  230  includes a first flip-flop (F/F)  151  to output an input signal synchronized with a clock and a second F/F  152  to output output signals of the first F/F  151  synchronized with the clock. Also, the re-swapping block  230  includes a first de-multiplexer  154 , a second de-multiplexer  155 , a control signal generating block  156  and a third de-multiplexer  153 . The first de-multiplexer  154  selects between a first delay clock clk_dly_f 1  and a first swapping clock clk_swap_f 1  in response to a swap control signal swp_ctr and provides the selected clock for the first F/F  151 . The second de-multiplexer  155  selects between a second delay clock clk_dly_f 2  and a second swapping clock clk_swap_f 2  in response to the swap control signal swp_ctr and provides the selected clock for the second F/F  152 . The control signal generating block  156  generates a control signal ctr from the swap control signal swp_ctr and a pass control signal ps_ctr. The third de-multiplexer  153  selects between the input signal and the output signal of the second F/F  152  in response to the control signal ctr and outputs the selected signal (OUT).  
         [0074]     The control signal generating block  156  includes an AND gate whose inputs include the swap control signal swp_ctr and the pass control signal ps_ctr.  
         [0075]      FIG. 8  is a waveform illustrating an operating of the re-swapping block  230  shown in  FIG. 7 .  
         [0076]     As shown in  FIG. 8 , input signals of the re-swapping block  230  is “A, B, C, D, E, F, G, H, I”.  
         [0077]     In case of ‘α’, the re-swapping block  230  passes the input signals. The first de-multiplexer  154  selects the first delay clock clk_dly_f 1  and provides the first delay clock clk_dly_f 1  for the first F/F  151 . Also, the second de-multiplexer  155  selects the second delay clock clk_dly_f 2  and provides the delay clock clk_dly_f 2  for the second F/F  152 . Then, the first F/F  151  outputs ff 1 _dly according to the first delay clock clk_dly_f 1  and the second F/F  152  outputs ff 2 _dly according to the second delay clock clk_dly_f 2 . The third de-multiplexer  153  passes the output signals of the second F/F  152  according to the control signal ctr. Therefore, output signals (OUT) of the third de-multiplexer  153  are the same sequence as that of input signals.  
         [0078]     In case of ‘β’, the re-swapping block  230  swaps the input signals at every odd number for the input signals at every even number. Hence, the sequence of output signals from the re-swapping block  230  is “B, A, D, C, F, E, H, G”.  
         [0079]     First, the first de-multiplexer  154  and the second de-multiplexer  155  select the first swap clock clk_swap_f 1  and the second swap clock clk_swap_f 2  and provide the selected swap clock for the first F/F  151  and the second F/F  152 , respectively. Then, the first F/F  151  outputs the input signal “A” with synchronizing the first swap clock clk_swap_f 1 , and the second F/F  152  outputs the output signal “A” of the first F/F  151  with synchronizing the second swap clock clk_swap_f 2 . While the second F/F  152  holds the output signal of the first F/F  151 , the signal “B” is the present input signal.  
         [0080]     According as the pass control signal ps_ctr is toggled, the control signal generating block  156  toggles the control signal ctr. Consequently, for an active section of the pass control signal ps_ctr, the present input signal “B” is outputted by the control signal ctr. Also, for an inactive section of the pass control signal ps_ctr, the holding signal “A” of the second F/F  152  is outputted by the control signal ctr.  
         [0081]     That is, the flip-flops hold the input signals at every odd number and output the input signals at every even number at once. After outputting the input signals at every even number, the holding input signals at every odd number are outputted.  
         [0082]     As described above, the sequence of output signals of the re-swapping block  230  is “B, A, D, C, F, E, H, G” because said re-swapping block  230  swaps the input signals at every odd number for the input signals at every even number.  
         [0083]     Therefore, to remove the offset noise caused by the path difference of the same type pixel data, the CMOS image sensor of the present invention has the swapping block  200  for making the same type pixel data go through the same path. In addition, because of said swapping, a sequence of the output signals of the ADC block  220  is different from that of the pixel array. To solve this problem, the re-swapping block  230  which outputs the same sequence of the pixel data as that of the pixel array by re-swapping is provided.  
         [0084]     As described above, the CMOS image sensor improves an image quality by removing an offset noise caused by the path difference throughout a swapping operation and a de-swapping operation.  
         [0085]     The present application contains subject matter related to Korean patent application Nos. 2004-69038, 2004-69046 and 2004-69218, filed in the Korean Patent Office on Aug. 31, 2004, the entire contents of which being incorporated herein by reference.  
         [0086]     While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.