Abstract:
The number of off and possibly leaking transistors in circuitry such as look-up table (LUT) circuitry is reduced by dividing the LUT or LUT-type circuitry into two separate or at least partly separate circuits. One of these circuits operates on first manifestations of the signals selectable by the circuitry. The other circuit operates on electrically different second manifestations of the selectable signals. Selections made by the two circuits are combined to produce an output of the circuitry.

Description:
BACKGROUND OF THE INVENTION 
   This invention relates to programmable look-up tables (LUTs) that have less leakage current than those in the prior art. 
   The logic cells that comprise a programmable logic device (PLD) often use programmable look-up tables (LUTs) as a means of implementing logic functions. (See, for example, Jefferson et al. U.S. Pat. No. 6,215,326.) These LUTs typically have N inputs that control a 2 N -input multiplexer (mux), with 2 N  programmable static RAM bits, each feeding one of the 2 N  inputs of the mux. This allows the LUT to implement any combinational logic function of the N inputs. Typically, to avoid RAM-disturb issues, the output of each RAM feeding the LUT will be buffered with an inverter before feeding the input to the LUT. The 2 N -input mux is typically created out of either an NMOS or full CMOS tree (e.g.,  FIGS. 1 and 2  herein, respectively). The CMOS tree (e.g.,  FIG. 2 ) has the advantage that the output of the LUT experiences a full voltage swing, while the NMOS mux (e.g.,  FIG. 1 ) has a Vt threshold voltage drop when the output is high, and thus may require a level-restorer on its output. 
   As CMOS processes have scaled down, transistors that would normally be “off” have begun to leak current. Whenever an off-transistor has its source and drain tied to different voltages, there is the potential for leakage current. In the examples shown  FIGS. 1 and 2 , the “off” transistors that may leak current have arrows pointing toward them. In devices with millions of transistors, this leakage current can add up to a large amount of stand-by power consumption. The invention described herein reduces the number of leaking transistors in the LUT, thus reducing the DC power consumption of the programmable device. 
   SUMMARY OF THE INVENTION 
   In order to reduce transistor leakage current in circuitry (e.g., LUT circuitry) for selecting a desired signal from a plurality of selectable signals in accordance with this invention, each of the selectable signals is provided in two, electrically different, signal manifestations. Each of the two electrically different manifestations of a selectable signal is itself different, depending on the logical state (0 or 1) of the selectable signal. For example, if a selectable signal has a first logical state (e.g., 0), the first manifestation of that signal may be logic 1 and the second manifestation may be “no drive.” (“No drive” means that a node receiving that signal manifestation is not driven to any particular voltage level by that signal manifestation.) If a selectable signal has a second logical state (e.g., 1), the first manifestation may be no drive and the second manifestation may be logic 0. The first and second manifestations of the selectable signals are respectively operated on by at least partly separate selection circuits, both of which are responsive to one or more selection control signals to select the desired signal. The selections made by the at least partly separate selection circuits are combined to produce an output of the desired signal. 
   As a result of the foregoing circuit configuration, more of the transistors in the circuitry that are off are in series with other off transistors, as compared to prior circuitry that does not use the invention. This substantially reduces transistor leakage current in the circuitry of this invention as compared to the prior circuitry. 
   The invention can be implemented in apparatus or method forms. 
   Further features of the invention, its nature and various advantages, will be more apparent from the accompanying drawings and the following detailed description. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a simplified schematic diagram of illustrative, known, LUT circuitry. 
       FIG. 2  is a simplified schematic diagram of other illustrative, known, LUT circuitry. 
       FIG. 3  is a simplified schematic diagram of an illustrative embodiment of the invention. 
       FIG. 4  is a simplified schematic diagram of another illustrative embodiment of the invention. 
       FIG. 5  is a simplified schematic diagram of still another illustrative embodiment of the invention. 
       FIG. 6  is a simplified schematic diagram of yet another illustrative embodiment of the invention. 
       FIG. 7  is a simplified schematic diagram of still another illustrative embodiment of the invention. 
       FIG. 8  is a table summarizing illustrative signal conditions at certain locations in the circuitry shown in  FIGS. 3–7  in accordance with the invention. 
   

   DETAILED DESCRIPTION 
     FIG. 1  shows a well known LUT configuration  10  that is mentioned in the background section of this specification and that can be further described here briefly (because it is so well known). LUT  10  is a two-input LUT, but it will be understood that this is only illustrative and that LUTs can have any other number of inputs (e.g., one input, or more than two inputs). The two inputs to LUT  10  are A and B. The values shown for A and B in  FIG. 1  are only illustrative, and these values can be different under different operating conditions of LUT  10 . For example, input B is shown having the value that applies logic 0 to lead  23   a  and logic 1 to lead  23   b , but these values could be reversed (i.e., logic 1 applied to lead  23   a  and logic 0 applied to lead  23   b ). 
   As a two-input LUT, LUT  10  has four programmable RAM bits  20 - 0  through  20 - 3 . RAM bits  20  are shown programmed with particular values (e.g.,  20 - 0  is programmed logic 0;  20 - 1  is programmed logic 1; etc.). Again, these values are only illustrative, and any desired values can be programmed into RAM bits  20 . 
   The output of each RAM bit  20  is applied to a respective one of buffers  22 . Each buffer  22  includes a PMOS transistor connected in series with an NMOS transistor between VCC (logic 1) and GND (logic 0). For example, buffer  22 - 0  includes PMOS transistor  22 - 0   a  connected in series with NMOS transistor  22 - 0   b  between VCC and GND. Each buffer  22  inverts the output of the associated RAM bit  20 . 
   The outputs of buffers  22  are the selectable inputs to the mux portion of LUT  10 . Inputs A and B are the selection control inputs to that mux circuitry. The first stage of the mux selection is performed by NMOS transistors  24 , controlled by signals derived from selection control input B. For example, input B may be applied to lead  23   a  and thus to the gates of NMOS transistors  24 - 0   a  and  24 - 1   a . The complement of input B may be applied to lead  23   b  and thus to the gates of NMOS transistors  24 - 0   b  and  24 - 1   b . The second stage of the mux selection is performed by NMOS transistors  26 , controlled by signals derived from selection control input A. For example, input A may be applied to lead  25   a  and thus to the gate of NMOS transistor  26   a . The complement of input A may be applied to lead  25   b  and thus to the gate of NMOS transistor  26   b.    
   Given the particular values programmed into RAM bits  20  and the particular values shown for inputs A and B, the following transistors in LUT  10  will be on:  22 - 0   a ,  22 - 1   b ,  22 - 2   b ,  22 - 3   a ,  24 - 0   b ,  24 - 1   b , and  26   b . The following transistors will nominally be off but potentially leaking:  22 - 0   b ,  22 - 1   a ,  22 - 2   a ,  22 - 3   b ,  24 - 0   a ,  24 - 1   a , and  26   a . The nominally off but possibly leaking transistors are indicated by the arrows pointing toward them in  FIG. 1 . The particular values of A and B shown in  FIG. 1  cause LUT  10  to output (on lead  30 ) the contents of RAM bit  20 - 0  as inverted by inverter  22 - 0 . The value of the signal on lead  30  in this particular example is shown as 1′ because the voltage of this signal is VCC minus the voltage drop across series-connected NMOS transistors  24 - 0   b  and  26   b . (The voltage drop across an NMOS transistor is Vt.) 
     FIG. 2  is similar to  FIG. 1 , but illustrates the use of full CMOS circuitry in the mux portion of LUT  10 ′. For example, in  FIG. 2 , NMOS transistor  24 - 0   b  is augmented by PMOS transistor  24 - 0   bp , which is connected in parallel with the NMOS transistor. Assuming again that the complement of B is applied to the gate of transistor  24 - 0   b  via lead  23   b , B is applied to the gate of transistor  24 - 0   bp  via lead  23   a . Use of full CMOS mux circuitry as in  FIG. 2  avoids loss of logic 1 voltage. Thus the output signal on lead  30  in  FIG. 2  is logic 1, rather than 1′ as in  FIG. 1  and described above. Given the particular data ( 20 ) and control (A and B) signal values employed in the example shown in  FIG. 2 , the following transistors will be on:  22 - 0   a ,  22 - 1   b ,  22 - 2   b ,  22 - 3   a ,  24 - 0   b ,  24 - 0   bp ,  24 - 1   b ,  24 - 1   bp ,  26   b , and  26   bp . The following transistors will be nominally off but possibly leaking:  22 - 0   b ,  22 - 1   a ,  22 - 2   a ,  22 - 3   b ,  24 - 0   a ,  24 - 0   ap ,  24 - 1   a ,  24 - 1   ap ,  26   a , and  26   ap.    
   In accordance with certain embodiments of the invention (see, e.g.,  FIG. 3 ), a CMOS LUT tree  110  is split into two independent trees joined only at their outputs  130 . The first tree includes only NMOS gates  124 - 0   a ,  124 - 0   b ,  124 - 1   a ,  124 - 1   b ,  126   a , and  126   b , while the second tree includes only PMOS gates  124 - 0   ap ,  124 - 0   bp ,  124 - 1   ap ,  124 - 1   bp ,  126   ap , and  126   bp . The CMOS inverter  122 , which is typically used to buffer the output of the RAMs  120 , is also split: with the drain of the NMOS device (e.g.,  122 - 0   b ) tied to an input of the NMOS tree, and the drain of the PMOS device (e.g.,  122 - 0   a ) tied to the input of the PMOS tree. Thus, the sources of all the NMOS devices (e.g.,  124 - 0   a ) in the NMOS tree (including the NMOS gate (e.g.,  122 - 0   b ) fed by the RAM (e.g.,  120 - 0 )) are either tied to GND or the drains of other NMOS devices (except for the output  130  of the NMOS tree), and the sources of all the PMOS devices (e.g.,  124 - 0   bp ) in the PMOS tree (including the PMOS gate (e.g.,  122 - 0   a ) fed by the RAM (e.g.,  120 - 0   a )) are either tied to VCC or the drains of other PMOS devices (except for the output  130  of the PMOS tree). Because of this, any leakage current from GND to VCC through the N-level LUT needs to follow a path all the way through N NMOS devices to the output  130  of the LUT, and then back down through N PMOS devices. It is well known in the art that the leakage current through two (or more) off transistors in series is much less than the leakage current through a single off transistor. 
   In a CMOS N-input LUT constructed in accordance with this invention, there will be at most (N+1) off transistors that are not in series with some other off transistor. These transistors are shown with arrows pointing toward them in  FIG. 3  (for a particular, illustrative set of data ( 120 ) and control (A and B) signal values). In a normal CMOS LUT  10 ′, as shown in  FIG. 2 , there can be up to 3*2 N −2 off transistors that are not in series with some other off transistor, while having different voltages on their sources and drains. Thus, for a large LUT, the number of transistors that have significant leakage is exponentially less for a LUT constructed in accordance with this invention. This LUT, like the conventional CMOS LUT  10 ′, has the advantage that the output  130  of the LUT experiences a full voltage swing, and thus does not require a level restorer on the output. 
   In  FIG. 3  (and subsequent FIGS.) some nodes are described as being “tristate” (indicated by an X on the node in the drawing). This means that the node is floating, i.e., that there is no path from that node through transistors that are on to either VCC or GND. There may be some small leakage current through these nodes via the off transistors, but typically they will float to a voltage somewhere between VCC and GND (e.g., approximately 0.5V). Of course, the particular nodes that are tristate in  FIG. 3  will depend on the particular data ( 120 ) and control (A and B) signal values that the circuit sees. Different data and control signal values will cause different nodes to be tristate, just as different data and control signal values cause different nodes to be 0, 1, and 1′. 
     FIG. 4  shows an alternative embodiment  210  of the invention in which the PMOS tree of  FIG. 3  is replaced by an NMOS tree  224 - 0   a ′,  224 - 0   b ′,  224 - 1   a ′,  224 - 1   b ′,  226   a ′, and  226   b ′. In this case, a level-restoring circuit may be required on the output  230  of the LUT  210 , because replacing a PMOS tree with an NMOS tree no longer allows the output to experience a full voltage swing. If NMOS devices have significantly better drive characteristics than PMOS devices, using NMOS devices in both trees may nevertheless result in a faster LUT. Again, transistors that are off and not in series with another off transistor are indicated by the arrows in  FIG. 4  (for a particular, illustrative set of data and control signal values). 
     FIG. 5  shows another alternative implementation  310  of the invention in which not only the PMOS tree is replaced by an NMOS tree (e.g., as in  FIG. 4 ), but the PMOS transistor (e.g.,  122 - 0   a  in  FIG. 3 ) which is used to buffer the output of each RAM (e.g.,  120 - 0  in  FIG. 3 ) (i.e., the PMOS transistor whose gate is tied to the output of the RAM) is replaced with an NMOS transistor (e.g.,  322 - 0   a ) whose gate is tied to the inverted output of the RAM (e.g.,  320 - 0 ). If the RAM has an inverted output available, and if NMOS devices have significantly better drive characteristics than PMOS devices, this modification may result in a faster LUT. Again in  FIG. 5 , transistors that are off and not in series with another off transistor are indicated by arrows (for a particular, illustrative set of input signal values). 
   Both of the  FIG. 4  and  FIG. 5  modifications still result in LUTs with exponentially fewer leaking transistors than in the prior art. 
     FIG. 6  shows another alternate implementation  410  of the invention in which some, but not all, of the internal nodes in the corresponding NMOS and PMOS trees are tied together. This may speed up those inputs that feed the subsequent (downstream) stage(s) of the mux tree. 
   The embodiment shown in  FIG. 6  is similar to the embodiment shown in  FIG. 3 . Accordingly, the  FIG. 3  reference numbers are used again for all  FIG. 3  elements that are repeated in  FIG. 6 . The additional elements in  FIG. 6  are conductors  440 - 0  and  440 - 1 . Conductor  440 - 0  connects the outputs of NMOS transistors  124 - 0   a  and  124 - 0   b  to the outputs of PMOS transistors  124 - 0   ap  and  124 - 0   bp . Conductor  440 - 1  similarly connects the outputs of NMOS transistors  124 - 1   a  and  124 - 1   b  to the outputs of PMOS transistors  124 - 1   ap  and  124 - 1   bp . The presence of conductors  440  tends to speed up the mux selection circuitry downstream from those conductors. For example, comparing the signal levels associated with transistor  126   a  in  FIGS. 3 and 6 , it will be seen that in  FIG. 3  to the left of transistor  126   a  is only 1′ (i.e., somewhat less than VCC). But in  FIG. 6  the signal at that location is 1 (i.e., full or substantially full VCC). This is an example of signal conditions that tend to make LUT  410  ( FIG. 6 ) somewhat faster than LUT  110  ( FIG. 3 ). 
   Once again in  FIG. 6  transistors that are off and not in series with another off transistor are indicated by arrows (for a particular, illustrative set of signal values). There are more such arrows in  FIG. 6  than in  FIG. 3 , but fewer than in  FIG. 2 , indicating that leakage current should still be less in circuitry of the type shown in  FIG. 6  than in prior art circuitry as in  FIG. 2 . 
     FIG. 7  shows yet another alternate implementation  510  of the invention in which some stages of the N-input mux are rebuffered. In this implementation the internal nodes of the N-level mux are rebuffered after the first M stages, where after M stages there are 2 N−M  partial “2 M -to-1” muxes which feed the M+1′ th stage of the mux as if they were the outputs of 2 N−M  RAMs feeding the first stage of a 2 N−M -to-1 mux (as is elsewhere shown and described in this specification). If the LUT has many inputs, this may result in a faster LUT. It should be understood that any of the separate stages may itself be implemented in any of the other variations described in this specification. 
   In the example shown in  FIG. 7  the circuitry is basically similar to what is shown in  FIG. 6 . Accordingly, the reference numbers used in  FIG. 6  are used again for similar elements in  FIG. 7 . The elements added in  FIG. 7  are rebuffering transistors  550  between the first stage of mux selection (controlled by input signal B) and the second stage of mux selection (controlled by input signal A). For example, NMOS rebuffering transistor  550 - 0  is connected between the outputs of first stage NMOS transistors  124 - 0   a  and  124 - 0   b  and the input of second stage NMOS transistor  126   b . As another example, PMOS rebuffering transistor  550 - 1   p  is connected between the outputs of first stage PMOS transistors  124 - 1   ap  and  124 - 1   bp  and the input of second stage PMOS transistor  126 - ap.    
   Again in  FIG. 7  the transistors that are off and not in series with another off transistor are indicated by arrows (for the illustrative input signal values). Also, again, there are more such arrows in  FIG. 7  than in  FIG. 3 , but fewer than in  FIG. 2 , indicating that leakage current should still be less in circuitry of the type shown in  FIG. 7  than in prior art circuitry like that shown in  FIG. 2 . 
     FIG. 8  is a table which summarizes certain signal conditions in each of the illustrative embodiments of the invention that are shown in  FIGS. 3–7  and described above. In particular,  FIG. 8  shows how each possible logical state of a selectable signal ( 120 / 320 ) is manifested at the output of each of the two buffer transistors ( 122 / 322 ) controlled by that selectable signal. For example, the first line of  FIG. 8  is for the illustrative embodiment  110  shown in  FIG. 1 . The left-hand two columns are for the first logical state (e.g., 0) of a selectable signal ( 120 ) in that embodiment, and the right-hand two columns are for the second logical state (e.g., 1) of that same selectable signal. Continuing with the example of the first line in  FIG. 8 ,  FIG. 3  shows that if a selectable signal (e.g.,  120 - 0 ) is 0, the output of the associated buffer transistor (e.g.,  122 - 0   a ) feeding the selection tree on the left is logic 1, and the output of the associated buffer transistor (e.g.,  122 - 0   b ) feeding the selection tree on the right is “no drive” (i.e., exemplary transistor  122 - 0   b  is off, so that its output node is not driven to any particular logic level by that transistor). Accordingly, the two left-hand entries in the first line in  FIG. 8  are 1 and no drive.  FIG. 3  further shows that if a selectable signal has the other logical state (i.e., 1) then the output of the associated buffer transistor on the left is no drive, and the output of the associated buffer transistor on the right is logic 0. (Selectable signal  120 - 1  and its associated buffer transistors  122 - 1   a  and  122 - 1   b  in  FIG. 3  illustrate this set of signal conditions.) Accordingly, the two right-hand entries in the first line of  FIG. 8  are no drive and 0. 
     FIG. 8  uses as column headings the terms “first manifestation” and “second manifestation.” These first and second signal manifestations are respectively the inputs to the first and second selection circuits that are employed in accordance with the invention. For example, in  FIG. 3  the first selection circuit may be the selection circuitry ( 124   p / 126   p ) on the left, and the second selection circuit may be the selection circuitry ( 124 / 126 ) on the right. Thus  FIG. 8  shows that in each embodiment of the invention, each selectable signal is provided in two, electrically different, signal manifestations; and each of these manifestations is different, depending on the logical state of the selectable signal. If a selectable signal is logic 0, its first manifestation may be logic 1 (electrically full VCC or (in the case of  FIG. 5 ) VCC-Vt) and its second manifestation may be no drive. If the same selectable signal is logic 1, its first manifestation may be no drive and its second manifestation may be logic 0. Stated another way, the first manifestation of a selectable signal is selected from the group consisting of logic 1 and no drive (depending on the logical state of the selectable signal), the second manifestation of that signal is selected from the group consisting of no drive and logic 0 (again depending on the logical state of the selectable signal), and the first and second manifestations are always electrically different from one another (i.e., only one manifestation is no drive for either state of any selectable signal). 
   It will be understood that a selectable signal may cause a no drive manifestation of that signal to be applied to an input node of selection circuitry, but that node may be driven to a particular state by other downstream circuitry. In  FIG. 3 , for example, the output node of NMOS buffer transistor  122 - 3   b  receives a no drive signal manifestation of selectable signal  120 - 3  from that transistor. That no drive signal manifestation has no particular effect on the electrical potential of the node receiving it, but that node is driven to 1′ by other downstream circuitry. This does not alter the fact that the output manifestation of selectable signal  120 - 3  at this node is no drive. The signal “manifestations” referred to herein are at the upstream ends of selection trees, not after any selection within a selection tree or any upstream flow through any selection tree circuitry. 
   The particular relationships between (1) the logical state of a selectable signal and (2) the first and second manifestations of that signal shown in  FIG. 8  and described above are only examples, and these particular relationships can be altered if desired without departing from the invention. For example, it is said above that when a selectable signal is logic 0, its two output manifestations can be logic 1 and no drive; and that when the selectable signal is logic 1, its two output manifestations can be no drive and logic 0. These relationships can be changed so that, for example, when a selectable signal is logic 1, its two output manifestations are logic 1 and no drive; and when the selectable signal is logic 0, its two output manifestations are no drive and logic 0. Other variations are, of course, also possible. 
   It will be understood that the foregoing is only illustrative of the principles of the invention, and that various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention. For example, the two-input LUTs shown in all the FIGS. herein are only an example. The invention is equally applicable to larger and smaller LUTs, as desired. Also, application of the invention to LUTs is only an example of possible uses of the invention, because the invention is equally applicable to any tree decoder (of which LUTs are an example). It will also be understood that the particular signal levels or conditions (e.g., 1, 1′, 0, or X) shown throughout the drawings herein are only examples. Different data in the RAM cells and/or different selection input signal values can result in different signal values or conditions at various points throughout the circuitry. This can mean different transistors being on and off, with the consequence that different transistors would be pointed out by the arrows in the FIGS. But the examples shown in the FIGS. are generally representative of the kinds of conditions that occur in the depicted circuitry in all of the various possible operating situations.