Abstract:
Memory devices and methods of forming include a mixed valent oxide located between a first electrode and a second electrode. Implantation of a metal below a surface of one of the electrodes allows formation of the mixed valent oxide with a direct interface to the electrode. An intermetallic oxide can be subsequently formed between the mixed valent oxide and the electrode by annealing the structure.

Description:
TECHNICAL FIELD 
     Various embodiments described herein relate to apparatus, systems, and methods associated with semiconductor memories. 
     BACKGROUND 
     In semiconductor memories, there is continuous pressure in industry to reduce component dimensions and fit more components in a given amount of chip area. As dimensions shrink, numerous technical hurdles become more significant. Alternative materials are used to provide unique properties necessary to reduce the size of components such as memory cells. The use of alternative materials can present technical hurdles. For example, some alternative materials must be formed under unique processing conditions to create characteristics such as a desired microstructure, a desired stoichiometry, desired electrical properties. Improved memory device configurations and methods are desired to provide improved device operation and ability to operate at smaller scales. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a block diagram of a memory device according to an embodiment of the invention. 
         FIG. 2  shows a substrate in a stage of processing according to an embodiment of the invention. 
         FIG. 3  shows a substrate in a stage of processing according to an embodiment of the invention. 
         FIG. 4  shows a substrate in a stage of processing according to an embodiment of the invention. 
         FIG. 5  shows an information handling system, utilizing structures formed according to an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     In the following detailed description of the invention, reference is made to the accompanying drawings that form a part hereof and in which are shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and logical, electrical, material changes, etc. may be made. 
     The term “horizontal” as used in this application is defined as a plane parallel to the substrate surface, such as a wafer or die, regardless of the orientation of the substrate. The term “vertical” refers to a direction perpendicular to the horizontal as defined above. Prepositions, such as “on”, “side” (as in “sidewall”), “higher”, “lower”, “over” and “under” are defined with respect to the surface being on the top surface of the substrate, regardless of the orientation of the substrate. The following detailed description is, therefore, not to be taken in a limiting sense. 
       FIG. 1  shows a block diagram of a memory device  100  according to an embodiment of the invention. Memory device  100  includes a memory array  102  with memory cells  103  that may be arranged in rows and columns along with access lines  104  and data lines  105 . Memory device  100  can use access lines  104  to access memory cells  103  and data lines  105  to transfer information with memory cells  103 . Row access  107  and column access circuitry  108  respond to an address register  112  to access memory cells  103  based on row address and column address signals on terminals  110 ,  111 , or both. A data input/output circuit  114  transfers data between memory cells  103  and terminals  110 . Terminals  110  and  111  may be external terminals of memory device  100  (e.g., terminals exposed outside a chip or semiconductor package that contains memory device  100 ). 
     A control circuit  116  controls operations of memory device  100  based on signals present on terminals  110  and  111 . A device (e.g., a processor or a memory controller) external to memory device  100  may send different commands (e.g., write commands and read commands) to memory device  100  using different combinations of signals on terminals  110 ,  111 , or both. 
     Memory device  100  responds to commands to perform operations such as write (e.g., programming), read, and erase operations. A write operation may store information received at terminals  110  into memory cells  103  (e.g., transfer information from terminals  110  to memory cells  103 ). A read operation retrieves stored information from memory cells  103  (e.g., transfer information from memory cells  103  to terminals  110 ). An erase operation erases information (e.g., clears information) from all memory cells  103  or from a selected portion of memory cells  103 . 
     Memory device  100  receives supply voltages Vcc and Vss. Vcc may include a positive voltage value, and Vss may include a ground potential. Memory device  100  can also include a voltage generator  140 . Voltage generator  140  and control circuit  116  operate to provide different voltages to memory array  102  or to cause memory array  102  to receive different voltages during the operations (e.g., write and read operations) of memory device  100 . 
     Memory device  100  may include an error correction unit  118  to check for errors in information retrieved from memory cells  103 . Error correction unit  118  may include error correction circuitry to correct errors based on an error correction code (ECC), as is well-known to those of ordinary skill in the art. 
     Memory device  100  may include a storage unit  120 , which may include circuit components such as registers. Storage unit  120  may include a hardware portion, a firmware portion, or both, of memory device  100 . Storage unit  120  may also be used to store codes (e.g., software programming instructions). 
     Memory device  100  can be a flash memory device such as a NAND flash or a NOR flash memory device, a resistive random access memory (RRAM) device, a phase change memory device, and other kinds of memory devices. 
     Memory device  100  can be a single-level-cell memory device such that memory cells  103  can include memory element to store information to represent a value of a single bit of information. For example, memory cells  103  may store information that represents either a binary “0” value or a binary “1” value of a single bit of information. 
     Memory device  100  can be a multi-level-cell (MLC) memory device such that each of memory cells  103  can include memory element to store information represented by a value corresponding to multiple bits of information (e.g., a value corresponding to two, three, four, or some other number of bits of information). For example, when each of memory cells  103  corresponds to a 2-bit per cell, each of memory cells  103  may store information to represent a value corresponding to one of four possible combinations of two binary bits of information (i.e., combination 00, 01, 10, and 11 corresponding to two bits of information). 
     Single level and MLC memory devices may be combined within memory device  100 . One of ordinary skill in the art will readily recognize that memory device  100  can include other parts, which are omitted from  FIG. 1  to help focus on the various embodiments described herein. Memory device  100  may include structures formed by one or more of the embodiments described below with reference to  FIG. 2  through  FIG. 4 . 
       FIG. 2  shows a substrate  200 . In one example, the substrate  200  includes a base portion  201 . Examples of base portion  201  may include silicon, germanium, gallium arsenide, or other semiconductor materials. Other examples of base portion  201  may include composite structures such as silicon on insulator structures. 
     An electrode  204  is shown located over the base portion  201 . The electrode is located within a dielectric material  202 . As an example, the electrode  204  includes a platinum electrode. Platinum provides chemical and structural properties that encourage nucleation and growth of subsequent structures, as explained in more detail below. Other electrode materials may include, other noble metals, other refractory metals, alloys of platinum, alloys of other noble metals, and/or alloys of other refractory metals. Examples of dielectric materials  202  include silicon oxide, other oxides, or other electrically insulating materials. 
     In  FIG. 2 , energetic species  206  are shown implanting metal ions  208  below a surface  205  of the electrode  204 . In one example, the metal ions include a single species, however, two or more species are contemplated. Some example single species metal ions include zirconium, aluminum, titanium, tantalum, or hafnium. The species of metal ions are chosen to later form an intermetallic oxide, as described in more detail below. In one example, both zirconium and hafnium are implanted at the same time to later form a zirconium hafnium oxide. Zirconium and hafnium are only used as example metal ions, to illustrate the method. Other metal species may be used to form other desired intermetallic oxides, depending on the material properties of the resulting intermetallic oxide desired. Desired intermetallic oxide properties may include dielectric constant, microstructure, compatibility with adjacent materials, etc. 
     In one example the energetic species  206  include processes other than ion implantation to place metal ions  208  below the surface  205  of the electrode  204 . For example, the energetic species  206  includes gas cluster ion bombardment (GCIB) or plasma implantation. 
     In one example, the energetic species  206  include both metal ions and oxygen ions. In later processing operations, the implanted oxygen ions combine with the implanted metal ions to form an intermetallic oxide. 
       FIG. 3  shows formation of a mixed valent oxide  210  over the electrode  204 . Examples of mixed valent oxides  210  include any of several magnetite perovskite oxide materials that exhibit resistive switching behavior. For example, praseodymium calcium manganese oxide (PrCaMnO), or lanthanum calcium manganese oxide (LaCaMnO). 
       FIG. 3  also shows a top electrode  212  formed over the mixed valent oxide  210 . In operation as a memory cell, a resistive state, corresponding to stored data, is stored in the mixed valent oxides  210 . When a potential is placed between the electrode  204 , and the top electrode  212 , if the resistive state of the mixed valent oxides  210  is relatively low, a current will conduct between the electrode  204  and the top electrode  212 , indicating a stored state. 
     Formation of mixed valent oxide  210  can be technically challenging. It has been discovered that mixed valent oxide  210  formation is facilitated by a direct interface with platinum or a similar metal, as listed above. Because the metal ions  208  are implanted below the surface  205  of the electrode, the mixed valent oxide  210  can form a direct interface with the electrode  204  during deposition. In one example, the mixed valent oxide  210  is substantially crystalline, and the platinum or a similar metal, as listed above, promotes crystallinity in formation of the mixed valent oxide  210 . 
     In  FIG. 4 , the device has been annealed. The anneal temperature is sufficient to drive the metal ions  208  from beneath the surface  205  of the electrode  204 , up to the surface  205 , which forms an interface between the mixed valent oxide  210  and the electrode  204 . One example of an anneal procedure includes a temperature in a range of approximately 200-700° C. In another example, the temperature is in a range of approximately 300-500° C. One example of an anneal procedure includes holding an anneal temperature for a time in a range of approximately 10-60 minutes. In another example, the anneal temperature is held for approximately 15-30 minutes. 
     In one example, the metal ions  208  react with oxygen from the mixed valent oxide  210  to form an intermetallic oxide  220 . In examples where both oxygen and metal ions were implanted in  FIG. 1 , at least a portion of the implanted oxygen combines with the metal ions  208  to form the intermetallic oxide  220 . Embodiments using implanted oxygen in addition to implanted metal ions  208  can adjust the oxygen content within the intermetallic oxide  220  by adjusting variables such as the amount of oxygen implanted, the depth of implant, and the ratio of oxygen to metal ions  208 . 
     In addition to forming the intermetallic oxide, the anneal operation may further promote crystalline growth of the mixed valent oxide  210 . 
     An embodiment of an information handling system such as a computer is included in  FIG. 5  to show an embodiment of a high-level device application.  FIG. 5  is a block diagram of an information handling system  500  incorporating a substrate such as a chip or chip assembly  504  that includes a mixed valent oxide memory cell according to an embodiment of the invention. The information handling system  500  shown in  FIG. 5  is merely one example of a system in which the present invention can be used. Other examples include, but are not limited to, personal data assistants (PDAs), cellular telephones, MP3 players, aircraft, satellites, military vehicles, etc. 
     In this example, information handling system  500  comprises a data processing system that includes a system bus  502  to couple the various components of the system. System bus  502  provides communications links among the various components of the information handling system  500  and may be implemented as a single bus, as a combination of busses, or in any other suitable manner. 
     Chip assembly  504  is coupled to the system bus  502 . Chip assembly  504  may include any circuit or operably compatible combination of circuits. In one embodiment, chip assembly  504  includes a processor  506  that can be of any type. As used herein, “processor” means any type of computational circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuit or cores thereof. Multiple processors such as “multi-core” devices are also within the scope of the invention. 
     In one embodiment, a memory device  507 , is included in the chip assembly  504 . Those skilled in the art will recognize that a wide variety of memory device configurations may be used in the chip assembly  504 . Acceptable types of memory chips include, but are not limited to, Dynamic Random Access Memory (DRAMs) such as SDRAMs, SLDRAMs, RDRAMs and other DRAMs. Memory chip  507  can also include non-volatile memory such as NAND memory or NOR memory. 
     In one embodiment, additional logic chips  508  other than processor chips are included in the chip assembly  504 . An example of a logic chip  508  other than a processor includes an analog to digital converter. Other circuits on logic chips  508  such as custom circuits, an application-specific integrated circuit (ASIC), etc. are also included in one embodiment of the invention. 
     Information handling system  500  may also include an external memory  511 , which can include one or more memory elements, such as one or more hard drives  512 , and/or one or more drives that handle removable media  513  such as floppy diskettes, compact disks (CDs), digital video disks (DVDs), and the like. 
     Information handling system  500  may also include a display device  509  such as a monitor, additional peripheral components  510 , such as speakers, etc. and a keyboard and/or controller  514 , which can include a mouse, or any other device that permits a system user to input data into and receive data from the information handling system  500 . 
     While a number of embodiments of the invention are described, the above lists are not intended to be exhaustive. Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of embodiments of the present invention. It is to be understood that the above description is intended to be illustrative and not restrictive. Combinations of the above embodiments, and other embodiments, will be apparent to those of skill in the art upon studying the above description.