Abstract:
A semiconductor integrated circuit includes a pump circuit configured to raise an external power supply voltage to generate a stepped-up voltage, and a detector circuit configured to detect the stepped-up voltage generated by the pump circuit to control activation/deactivation of the pump circuit, wherein the detector circuit includes a differential amplifier configured to compare the stepped-up voltage with a reference voltage, and a current control circuit configured to control an amount of a bias current running through the differential amplifier in response to the activation/deactivation of the pump circuit.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     This is a continuation of International Application No. PCT/JP2003/008212, filed on Jun. 27, 2003, the entire contents of which are hereby incorporated by reference. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention generally relates to semiconductor integrated circuits, and particularly relates to a semiconductor integrated circuit provided with an internal power supply circuit such as a stepped-up power supply circuit or stepped-down power supply circuit.  
         [0004]     2. Description of the Related Art  
         [0005]     In semiconductor integrated circuits, a stepped-up voltage Vpp and/or a stepped-down voltage Vii are generated from an external power supply voltage Vdd for provision to the core circuit. In semiconductor memory devices, for example, a stepped-up voltage Vpp is used to drive a word line or the like, and a stepped-down voltage Vii is used as a power supply voltage in the memory core circuit and peripheral circuits. In order to generate the stepped-up voltage and stepped-down voltage, power supply circuits such as a stepped-up voltage generating circuit and a stepped-down voltage generating circuit are used.  
         [0006]     A stepped-up voltage generating circuit includes a detector circuit and a pump circuit. When the detector circuit detects a drop of the stepped-up voltage, the pump circuit is activated in response, thereby raising the stepped-up voltage.  FIG. 1  is a circuit diagram showing an example of the configuration of the detector circuit.  
         [0007]     The detector circuit of  FIG. 1  includes NMOS transistors  11  through  13 , PMOS transistors  14  and  15 , resistors  16  and  17 , and an inverter  18 . The resistors  16  and  17  together constitute a potential divider, which divides the stepped-up voltage Vpp. The NMOS transistors  11  through  13  and the PMOS transistors  14  and  15  together constitute a differential amplifier, which supplies to the inverter  18  a voltage responsive to a difference between a reference voltage Vref and the voltage made by dividing the stepped-up voltage Vpp. An output pump_on of the inverter  18  is supplied to the pump circuit. When the stepped-up voltage Vpp drops, the voltage obtained by dividing the stepped-up voltage Vpp becomes smaller than the reference voltage Vref, resulting in the input into the inverter  18  being LOW. As a result, the output pump_on becomes HIGH. In response, the pump circuit is activated to raise the stepped-up voltage Vpp.  
         [0008]      FIG. 2  is a diagram showing changes in the stepped-up voltage Vpp. As shown in  FIG. 2 , the stepped-up voltage Vpp gradually drops due to leak currents in the core circuit during the standby mode of the semiconductor integrated circuit (i.e., the period indicated as pump-off in  FIG. 2 ). When the stepped-up voltage Vpp drops to a predetermined level, the pump circuit is activated to boost the stepped-up voltage Vpp. When the stepped-up voltage Vpp rises to reach a predetermined level, the operation of the pump-circuit is suspended. In  FIG. 2 , the period during which the pump-circuit operates is indicated as pump-on. Through the operations described above, the stepped-up voltage Vpp is maintained at a constant potential.  
         [0009]     In  FIG. 1 , a bias current Ib 1  flowing through the NMOS transistor  11  is set to an amount corresponding to the operation speed required for the pump circuit active in operation (during the pump-on period shown in  FIG. 2 ). If the bias current Ib 1  is large, the operation speed of the differential amplifier shown in  FIG. 1  is fast, thereby being able to detect a potential change in response to a rapid change in the stepped-up voltage Vpp. If the amount of the bias current Ib 1  is insufficient, the operation speed during the pump-on period shown in  FIG. 2  becomes insufficient. In this case, the potential detection is delayed, and the stepped-up voltage Vpp experiencing a rapid rise becomes an excessive voltage level exceeding a predetermined level. Because of this, the bias current Ib 1  needs to be set to an amount corresponding to the operation speed required during the active operation of the pump circuit.  
         [0010]     If the bias current Ib 1  is set such as to fit with the operation period of the pump circuit, however, the current consumption of the bias current Ib 1  during the pump-off period becomes a needless waste. That is because a large amount of the bias current Ib 1  is used despite the fact that high response speed is not required during the pump-off period because changes in the stepped-up voltage Vpp are gradual.  
         [0011]     In consideration of the above, there is a need for a configuration that can reduce current consumption in the stepped-up voltage generating circuit during the standby mode.  
         [0012]     A needless current is also consumed in the stepped-down voltage generating circuit.  FIG. 3  is a diagram showing a portion relating to the stepped-down voltage generating circuit. In  FIG. 3 , a power-down control circuit  21 , a VGI generating circuit  22 , NMOS transistors  23  and  24 , and a power-down control pad  25  are illustrated. The NMOS transistor  24  serves as the circuit portion that generates the stepped-down voltage. The gate of the NMOS transistor  24  receives a predetermined gate voltage Vgi, with its drain node connected to a power supply voltage Vdd and its source node supplying an internal stepped-down potential Vii. When the stepped-down potential Vii drops due to current consumption in the core circuit, a difference between the gate potential Vgi and the source potential (the stepped-down potential Vii) widens, resulting in an increase in the current flowing through the NMOS transistor  24 . In response, the stepped-down potential Vii rises. In this manner, the stepped-down potential Vii is controlled to be a constant potential defined by the gate potential Vgi.  
         [0013]     In the configuration shown in  FIG. 3 , a signal from the exterior to the power-down control pad  25  is asserted during a power-down mode, resulting in an output signal PD of the power-down control circuit  21  becoming HIGH. The NMOS transistor  23  thus becomes conductive, turning the output of the VGI generating circuit  22  to LOW (i.e., a ground potential VSS), resulting in the NMOS transistor  24  being nonconductive. In this manner, the supply of the internal stepped-down voltage Vii to the core circuit is suspended during the power-down mode (for example, see Patent Document 1).  
         [0014]     Depending on the type of the semiconductor integrated circuit, there may be a case in which it is desired to set the potential of the internal stepped-down voltage Vii to a voltage slightly higher than an ordinary voltage. In such a case, since there is a limit as to how high the gate voltage Vgi can be raised, it is a general practice to use a transistor having a small threshold voltage as the NMOS transistor  24 . If a transistor having a small threshold voltage is used as the NMOS transistor  24 , however, the NMOS transistor  24  will not be completely turned off even when the gate voltage Vgi becomes LOW in the power-down mode, resulting in a continuous flow of some electric current. Because of this, current consumption relatively increases during the power-down mode.  
         [0015]     In consideration of the above, there is a need to provide a configuration that can reduce current consumption in the stepped-down voltage generating circuit during the power-down mode.  
         [0016]     [Patent Document 1] Japanese Patent Application Publication No. 2002-373026.  
       SUMMARY OF THE INVENTION  
       [0017]     It is a general object of the present invention to provide a semiconductor integrated circuit that substantially obviates one or more problems caused by the limitations and disadvantages of the related art.  
         [0018]     It is a first specific object of the present invention to provide a semiconductor integrated circuit that can reduce current consumption in the stepped-up voltage generating circuit during the standby mode.  
         [0019]     In order to achieve the above objects, a semiconductor integrated circuit according to the present invention includes a pump circuit configured to raise an external power supply voltage to generate a stepped-up voltage, and a detector circuit configured to detect the stepped-up voltage generated by the pump circuit to control activation/deactivation of the pump circuit, wherein the detector circuit includes a differential amplifier configured to compare the stepped-up voltage with a reference voltage, and a current control circuit configured to control an amount of a bias current running through the differential amplifier in response to the activation/deactivation of the pump circuit.  
         [0020]     The semiconductor integrated circuit described above can secure a sufficient response speed by increasing the bias current during the period in which the pump circuit is activated, and can reduce needless current consumption by decreasing the bias current during the period in which the pump circuit is deactivated. Provision is thus made to reduce current consumption in the stepped-up voltage generating circuit during the standby mode.  
         [0021]     Further, it is a second specific object of the present invention to provide a semiconductor integrated circuit that can reduce current consumption in the stepped-down voltage generating circuit during the power-down mode.  
         [0022]     In order to achieve the above objects, a semiconductor integrated circuit according to the present invention includes a voltage generating circuit configured to generate a predetermined voltage, an NMOS transistor configured to receive at a gate node thereof the predetermined voltage generated by said voltage generating circuit, to receive at a drain node thereof an external power supply voltage, and to generate at a source node thereof a stepped-down voltage by reducing the external power supply voltage in response to the predetermined voltage, and a PMOS transistor, provided between the drain node of said NMOS transistor and the external power supply voltage, configured to receive at a gate node thereof a power-down signal indicative of a power-down mode.  
         [0023]     The semiconductor integrated circuit described above makes the PMOS transistor nonconductive during the power-down mode so as to reduce a current flowing towards the internal stepped-down potential. With this provision, a consumed current flowing out of the stepped-down potential generating circuit can be reduced during the power-down mode even if the NMOS transistor does not become completely nonconductive during the power-down mode. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0024]     Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings, in which:  
         [0025]      FIG. 1  is a circuit diagram showing an example of the configuration of a detector circuit;  
         [0026]      FIG. 2  is a diagram showing changes in a stepped-up voltage;  
         [0027]      FIG. 3  is a diagram showing a portion relating to a stepped-down voltage generating circuit;  
         [0028]      FIG. 4  is a block diagram showing a typical configuration of a semiconductor memory device as an example of a semiconductor integrated circuit to which the present invention is applied;  
         [0029]      FIG. 5  is a block diagram showing the configuration of a Vpp generating circuit;  
         [0030]      FIG. 6  is a circuit diagram showing an example of the configuration of a detector circuit according to the present invention;  
         [0031]      FIG. 7  is a circuit diagram showing the configuration of another embodiment of the detector circuit;  
         [0032]      FIG. 8  is a circuit diagram showing the configuration of a further embodiment of the detector circuit;  
         [0033]      FIG. 9  is a circuit diagram showing an example of the circuit configuration of a pump circuit;  
         [0034]      FIG. 10  is a circuit diagram showing an example of the circuit configuration of a Vii generating circuit according to the present invention;  
         [0035]      FIG. 11  is a circuit diagram showing another example of the circuit configuration of the Vii generating circuit according to the present invention;  
         [0036]      FIG. 12  is a circuit diagram showing another example of the circuit configuration of the Vii generating circuit according to the present invention; and  
         [0037]      FIG. 13  is a circuit diagram showing the circuit configuration of a VGI generating circuit. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0038]     In the following, embodiments of the present invention will be described with reference to the accompanying drawings.  
         [0039]      FIG. 4  is a block diagram showing a typical configuration of a semiconductor memory device as an example of a semiconductor integrated circuit to which the present invention is applied.  
         [0040]     The semiconductor memory device of  FIG. 4  includes a power supply circuit  31 , a peripheral circuit  32 , a memory core circuit  33 , and internal power supply lines  34 . The power supply circuit  31  includes a Vpp generating circuit  35  for generating a stepped-up potential and a Vii generating circuit  36  for generating a stepped-down potential. A stepped-up potential Vpp generated by the Vpp generating circuit  35  and a stepped-down potential Vii generated by the Vii generating circuit  36  are supplied to the peripheral circuit  32  and the memory core circuit  33  via the respective internal power supply lines  34 . The semiconductor memory device has an active mode in which data input/output is performed, a standby mode in which data is retained without any data input/output, and a power-down mode in which data is not retained.  
         [0041]      FIG. 5  is a block diagram showing the configuration of the Vpp generating circuit  35 . The Vpp generating circuit  35  of  FIG. 5  includes a detector circuit  41  and a pump circuit  42 . When the detector circuit  41  detects a drop in the stepped-up voltage Vpp, the pump circuit  42  is activated in response, thereby raising the stepped-up voltage Vpp.  
         [0042]      FIG. 6  is a circuit diagram showing an example of the configuration of the detector circuit according to the present invention.  
         [0043]     The detector circuit  41  shown in  FIG. 6  includes NMOS transistors  51  through  53 , PMOS transistors  54  and  55 , resistors  56  and  57 , an inverter  58 , and NMOS transistors  61  and  62 . The resistors  56  and  57  together constitute a potential divider, which divides the voltage of the stepped-up voltage Vpp. The NMOS transistors  51  through  53  and the PMOS transistors  54  and  55  together constitute a differential amplifier, which supplies to the inverter  58  a voltage responsive to a difference between a reference voltage Vref and the voltage obtained by dividing the stepped-up voltage Vpp. An output pump_on of the inverter  58  is supplied to the pump circuit  42 . When the stepped-up voltage Vpp drops, the voltage obtained by dividing the stepped-up voltage Vpp becomes lower than the reference voltage Vref, resulting in the input into the inverter  58  being LOW. As a result, the output pump_on becomes HIGH. In response, the pump circuit  42  is activated to raise the stepped-up voltage Vpp.  
         [0044]     In the detector circuit  41  according to the present invention, the NMOS transistors  61  and  62  are provided. The gate of the NMOS transistor  62  receives the output pump_on of the inverter  58 . With this provision, the NMOS transistor  62  becomes conductive during the period in which the pump circuit  42  is activated.  
         [0045]     If a combined current of a current Ib 1  running through the NMOS transistor  51  and a current Ib 2  running through the NMOS transistor  62  is large, the response speed of the differential amplifier shown in  FIG. 6  is fast, thereby being able to detect a potential change in response to a rapid change in the stepped-up voltage Vpp. In the present invention, the combined bias current Ib 1 +Ib 2  is set to a large amount during the period in which the pump circuit  42  is activated (i.e., the pump-on period shown in  FIG. 2 ), thereby securing a sufficient response speed. On the other hand, the combined bias current is set to a small amount during a period in which the pump circuit  42  is deactivated (i.e., the pump-off period shown in  FIG. 2 ), thereby reducing needless current consumption. Provision is thus made to reduce current consumption in the semiconductor memory device during the standby mode.  
         [0046]     The NMOS transistor  61  is driven by a gate voltage Vbias applied to the NMOS transistor  51 , and serves as a current source in the same manner as the NMOS transistor  51 . Since the NMOS transistor  62  only serves as a switch that is merely turned on or turned off, the use of the NMOS transistor  62  alone results in an excessive current flowing through the differential amplifier. The NMOS transistor  61  serving as a current source is thus provided to adjust the amount of the current Ib 2 .  
         [0047]      FIG. 7  is a circuit diagram showing the configuration of another embodiment of the detector circuit. In  FIG. 7 , the same elements as those of  FIG. 6  are referred to by the same numerals, and a description thereof will be omitted.  
         [0048]     In a detector circuit  41 A shown in  FIG. 7 , the gate potential of the NMOS transistor  51  and the gate potential of the NMOS transistor  61  are set to potentials Vbias 1  and Vbias 2 , respectively, which are independent of each other. Other than this, the configuration is the same as that of the detector circuit  41  shown in  FIG. 6 . With the configuration of  FIG. 6 , the current Ib 1  and the current Ib 2  have the same current amount if the NMOS transistors  51  and  61  have the same characteristics. With the configuration shown in  FIG. 7 , on the other hand, it is possible to set the current Ib 1  and the current Ib 2  to respective, different current amounts.  
         [0049]      FIG. 8  is a circuit diagram showing the configuration of a further embodiment of the detector circuit. In  FIG. 8 , the same elements as those of  FIG. 6  are referred to by the same numerals, and a description thereof will be omitted.  
         [0050]     In a detector circuit  41 B shown in  FIG. 8 , the NMOS transistor  61  that is present in  FIG. 6  is removed. Other than this, the configuration is the same as that of the detector circuit  41  shown in  FIG. 6 . As was previously described, the NMOS transistor  62  in the configuration of  FIG. 6  only serves as a switch that is merely turned on or turned off, and the NMOS transistor  61  serving as a current source is thus provided to adjust the amount of the current Ib 2 . In the configuration shown in  FIG. 8 , the NMOS transistor  61  serving as a current source is removed, and the NMOS transistor  62  alone is used to adjust the current amount. Namely, the amount of the current flowing through the NMOS transistor  62  when the NMOS transistor  62  is in the on state is defined by the voltage between the gate and source of the NMOS transistor  62 . In order to adjust the current amount to a proper amount in this case, adjustment may be made to the channel size of the NMOS transistor. The method of adjusting the current amount of the detector circuit used in  FIG. 6 ,  FIG. 7 , and  FIG. 8  may also be used for voltage detection in a negative-potential power supply.  
         [0051]      FIG. 9  is a circuit diagram showing an example of the circuit configuration of the pump circuit  42 .  
         [0052]     The pump circuit  42  of  FIG. 9  includes a NAND circuit  71 , inverters  72  and  73 , a capacitor  74 , and NMOS transistors  75  and  76 . As the signal pump_on from the detector circuit  41  becomes HIGH, a ring oscillator comprised of the NAND circuit  71  and the inverters  72  and  73  starts to oscillate. Voltage changes in each cycle of the oscillation of the ring oscillator propagate to the NMOS transistors  75  and  76  via a capacitance coupling of the capacitor  74 . Due to the voltage changes in each cycle of the oscillation, electric charge supplied from the power supply voltage Vdd accumulates cumulatively, resulting in the stepped-up potential Vpp higher than the power supply voltage Vdd being generated.  
         [0053]      FIG. 10  is a circuit diagram showing an example of the circuit configuration of the Vii generating circuit  36  according to the present invention.  
         [0054]     The Vii generating circuit  36  shown in  FIG. 10  includes a power-down control circuit  81 , a VGI generating circuit  82 , NMOS transistors  83  and  84 , a power-down control pad  85 , and an NMOS transistor  86 . The NMOS transistor  84  serves as the circuit portion that generates the stepped-down voltage. The gate of the NMOS transistor  84  receives a predetermined gate voltage Vgi, with its drain node connected to the power supply voltage Vdd and its source node supplying the internal stepped-down potential Vii. When the stepped-down potential Vii drops due to current consumption in the core circuit, a difference between the gate potential Vgi and the source potential (the stepped-down potential Vii) widens, resulting in an increase in the current flowing through the NMOS transistor  84 . In response, the stepped-down potential Vii rises. In this manner, the stepped-down potential Vii is controlled to be a constant potential defined by the gate potential Vgi.  
         [0055]     A signal from the exterior to the power-down control pad  85  is asserted during a power-down mode, resulting in an output signal PD of the power-down control circuit  81  becoming HIGH. The NMOS transistor  83  thus becomes conductive, turning the output of the VGI generating circuit  82  to LOW (i.e., the ground potential VSS), which results in the NMOS transistor  84  being nonconductive. In this manner, the supply of the internal stepped-down voltage Vii to the core circuit is suspended during the power-down mode.  
         [0056]     In the configuration shown in  FIG. 10 , the potential of the internal stepped-down voltage Vii may be set to a voltage slightly higher than an ordinary potential. To this end, an NMOS transistor having a low threshold voltage is used, and the source potential is coupled to the substrate potential, thereby removing a back-bias effect. This reduces the threshold voltage of the NMOS transistor  84 .  
         [0057]     In the present invention, the PMOS transistor  86  is further provided, with its gate node receiving the output signal PD of the power-down control circuit  81  that becomes HIGH during the power-down mode. The PMOS transistor  86  thus becomes nonconductive during the power-down mode, so that a current flowing toward the internal stepped-down potential Vii decreases. With this provision, it is possible to reduce the consumption of the current flowing out of the Vii generating circuit  36  during the power-down mode even if the NMOS transistor  84  does not become completely nonconductive during the power-down mode.  
         [0058]      FIG. 11  is a circuit diagram showing another example of the circuit configuration of the Vii generating circuit according to the present invention. In  FIG. 11 , the same elements as those of  FIG. 10  are referred to by the same numerals, and a description thereof will be omitted.  
         [0059]     In a Vii generating circuit  36 A shown in  FIG. 11 , an NMOS transistor  84 A having an ordinary threshold voltage is provided in place of the NMOS transistor  84  having a low threshold voltage shown in  FIG. 10 . Other than this, the configuration is the same as that shown in  FIG. 10 . The configuration shown in  FIG. 11  also can reduce the consumption of the current flowing out of the Vii generating circuit  36 A during the power-down mode.  
         [0060]      FIG. 12  is a circuit diagram showing another example of the circuit configuration of the Vii generating circuit according to the present invention. In  FIG. 12 , the same elements as those of  FIG. 10  are referred to by the same numerals, and a description thereof will be omitted.  
         [0061]     In a Vii generating circuit  36 B shown in  FIG. 12 , a plurality of NMOS transistors  84 - 1 ,  84 - 2 , . . . are provided in place of the NMOS transistor  84  shown in  FIG. 10 . Further, a plurality of PMOS transistors  86 - 1 ,  86 - 2 , . . . , are provided in place of the PMOS transistor  86  shown in  FIG. 10 . The plurality of PMOS transistors  84 - 1 ,  84 - 2 , . . . and the plurality of NMOS transistors  86 - 1 ,  86 - 2 , . . . are arranged in a spaced-apart manner at different locations in the semiconductor memory device, and supply the internal stepped-down voltage Vii at the respective positions where they are located within the semiconductor memory device. Other than this, the configuration is the same as that shown in  FIG. 10 .  
         [0062]      FIG. 13  is a circuit diagram showing the circuit configuration of the VGI generating circuit  82 .  
         [0063]     The VGI generating circuit  82  includes NMOS transistors  101  through  104 , PMOS transistors  105  through  108 , resistors  109  and  110 , and an inverter  111 . The NMOS transistors  101  through  104  and the PMOS transistors  106  and  107  together constitute a differential amplifier, and the resistors  109  and  110  together constitute a potential divider. The potential divider divides the output voltage Vgi, and the divided voltage is compared with the reference potential Vref by the differential amplifier. A voltage responsive to the difference between the divided voltage and the reference potential Vref drives the PMOS transistor  108 , thereby generating the output signal Vgi. In this manner, the VGI generating circuit  82  adjusts the output signal Vgi to a desired voltage level through feedback control.  
         [0064]     During the power-down mode, the power-down signal PD becomes HIGH, so that the output of the inverter  111  becomes LOW. In response, the NMOS transistor  102  becomes nonconductive, resulting in the operation of the differential amplifier being suspended. At this time, the output signal Vgi of the VGI generating circuit  82  is clamped to the ground potential via the NMOS transistor  83  provided for the clamping purpose.  
         [0065]     Further, the present invention is not limited to these embodiments, but various variations and modifications may be made without departing from the scope of the present invention.