Abstract:
A display element and a method of manufacturing the same are provided. The method comprises the following steps: forming a first patterned conducting layer with a gate on a substrate and a dielectric layer thereon; forming a patterned semiconductor layer on the dielectric layer, wherein the patterned semiconductor layer has a channel region, a source and a drain, and wherein the source and the drain lie on the opposite sides of the channel region; selectively depositing a barrier layer, which only wraps the patterned semiconductor layer; forming a second patterned conducting layer on the barrier layer and above the source and the drain. In the display element manufactured by the method, the barrier layer only wraps the patterned semiconductor layer.

Description:
[0001]    This application is a divisional of application Ser. No. 12/115,855, filed on May 6, 2008, which claimed benefits of the priority based on Taiwan Patent Application No. 096132084 filed on Aug. 29, 2007; the disclosures of which are incorporated by reference herein in their entirety. 
     
    
     CROSS-REFERENCES TO RELATED APPLICATIONS 
       [0002]    Not applicable. 
       BACKGROUND OF THE INVENTION 
       [0003]    1. Field of the Invention 
         [0004]    The present invention relates to a display element and a method of manufacturing the same. More particularly, the present invention relates to a thin-film transistor (TFT) comprising a copper electrode and a method of manufacturing the same; and especially relates to forming a barrier layer only onto the semiconductor layer of the transistor by using an electroless plating process with deposition selectivity. 
         [0005]    2. Descriptions of the Related Art 
         [0006]    As liquid crystal display (LCD) panels gradually increase in size, the resolution thereof needs to increase accordingly. As a result, aluminum has been gradually being replaced by copper as the conductive material in the manufacturing process of the LCD panels. This is because copper has many advantages over aluminum, such as a lower resistivity, a lower thermal expansion coefficient, a higher melting point, a higher thermal conductivity and a greater resistance to electro-migration. Therefore, copper conductors may lead to a display panel with a higher circuit density and a more superior imaging quality, and may also reduce the manufacturing cost thereof. As a result, the manufacturing process adopting copper conductors has become common and popular for large-sized high-resolution LCDs. 
         [0007]    However, a number of problems still exist in the existing LCD manufacturing processes when copper is adopted as the conductive material. Some examples include: the inability to form a self-protective oxide layer, poor adhesion with the dielectric layer, a high diffusion coefficient in the semiconductor layer and the dielectric layer, and reaction with silicon at a low temperature which forms a silicide. All these problems may lead to the degradation of electrical performance of such conductors in the LCDs, thus causing an adverse impact on the quality of LCDs. 
         [0008]    In order to alleviate such problems, copper is generally used in combination with a barrier layer in the art at present. For example, when copper is used as the source/drain electrode of a TFT, a barrier layer is typically disposed between the copper and a semiconductor layer to prevent an undesired diffusion effect due to the direct contact therebetween. Such a barrier layer is typically made of nickel (Ni), tantalum (Ta), titanium (Ti), molybdenum (Mo), chromium (Cr), tungsten (W), or an alloy thereof. 
         [0009]      FIG. 1  depicts a schematic cross-sectional view of a conventional display element adopting such a combination. In this display element, a transistor region  111  and a capacitance region  113  are defined on a substrate  11 . The transistor region  111  has a transistor structure formed therein, which comprises in sequence (from bottom to top): a gate  131 , a dielectric layer  15 , a patterned semiconductor layer  17 , a patterned barrier layer  19 , a source/drain electrode  211 , a passivation layer  23 , and a patterned pixel electrode  25 . The patterned semiconductor layer  17  further comprises a channel layer  171  and a source/drain layer  173 . The capacitance region  113  comprises in sequence from bottom to top a first conductor  133 , a dielectric layer  15 , a patterned barrier layer  19 , a second conductor  213 , a passivation layer  23 , and a patterned pixel electrode  25 . The gate  131  and the first conductor  133  are respectively a portion of a first patterned conducting layer  13 , while the source/drain electrode  211  and the second conductor  213  are respectively a portion of a second patterned conducting layer  21 . The second patterned conducting layer  21  is made of copper or its alloys, although other conductive metal materials such as aluminum may also be optionally used. 
         [0010]    In the structure depicted in  FIG. 1 , as described above, a barrier layer  19  is formed between the source/drain electrode  211  made of copper and the semiconductor layer  17  for separation therebetween, which is accomplished by a usual deposition and followed with lithographic and etching processes. Although this may overcome the diffusion problem described above, the barrier layer  19 , which typically has a much higher resistivity than the conducting layers  13 ,  21 , will increase the overall resistance significantly. Actually, the barrier layer  19  is also formed in some unnecessary regions of the display element such as the region circled by the dashed line. However, due to the limitation of lithographic and etching processes or out of convenience, the presence of the barrier layer  19  in these unnecessary regions is typically unavoidable. Therefore, elimination of such an unnecessary dual-layer structure in these regions can prevent an unnecessary increase in the resistance, thereby improving the performance of the resulting transistor. 
         [0011]    Additionally, when the lithographic and etching processes, especially a wet etching process is performed, differential electrochemical reactions, i.e. different etching rates, to copper and the barrier layer tend to occur, and resulting in an undercutting to the barrier layer  19  at the periphery of the second patterned conductor  213 . Such an undercut may cause degradation of the electrical performance of the thin-film transistor (TFT) and render it difficult to control the width of the conductor. 
         [0012]    Although the formation of a barrier layer under the copper electrode in the existing TFT manufacturing process may obviate the diffusion effect, it will unnecessarily cause an increased resistance and undercut the barrier layer. In view of this, it is highly desirable to provide a method for manufacturing a display element that can eliminate all of the problems mentioned above. 
       SUMMARY OF THE INVENTION 
       [0013]    Through research, inventors have found that a barrier layer by using such as an electroless plating with selective deposition can be selectively formed to only wraps the semiconductor layer but not any other layers during the manufacturing of a TFT. As a result, improper increase of the overall resistance and the copper diffusion of the electrode are prevented. In particular, this invention relates to a selectively depositing process by using an electroless plating procedure in manufacturing a TFT. In other words, prior to the formation of a copper electrode, an electroless plating procedure is performed to selectively form a barrier layer that only wraps a semiconductor layer. In this way, a uniform barrier layer may be obtained without using any additional masks, thus eliminating the above problems. 
         [0014]    Therefore, one object of this invention is to provide a method for manufacturing a display element structure, which comprises the following steps: sequentially forming a first patterned conducting layer and a dielectric layer on the substrate, wherein the first patterned conducting layer includes a gate while the dielectric layer covers the first patterned conducting layer; forming a patterned semiconductor layer on the dielectric layer, wherein the patterned semiconductor layer includes a channel region, a source and a drain, and wherein the source and the drain lie on the opposite sides of the channel region; selectively depositing a barrier layer which only wraps the source and the drain; and finally, forming a second patterned conducting layer covering portions of the barrier layer above the source and the drain. 
         [0015]    Another object of this invention is to provide a method for manufacturing a display element structure, which comprises the following steps: sequentially forming a first patterned conducting layer and a dielectric layer on a substrate with a transistor region and a capacitance region defined therein, wherein the first patterned conducting layer includes a gate while the dielectric layer covers the first patterned conducting layer; forming a patterned semiconductor layer on the dielectric layer in the transistor region, wherein the patterned semiconductor layer includes a channel region, a source and a drain, and wherein the source and the drain lie on the opposite sides of the channel region; selectively depositing a barrier layer which only wraps the patterned semiconductor layer; forming a second patterned conducting layer covering portions of the barrier layer above the source and the drain as well as portions of the dielectric layer in the capacitance region; forming a patterned passivation layer on the substrate, which defines an opening for exposing the portion of the second patterned conducting layer above the drain; and finally, forming a pixel electrode on the portion of the patterned passivation layer and within the opening, which is electrically connected to the second patterned conducting layer above the drain. 
         [0016]    Yet a further object of this invention is to provide a display element structure on a substrate. The display element structure comprises the following components: a gate disposed on the substrate; a dielectric layer covering the gate and the substrate; a patterned semiconductor layer disposed on the dielectric layer, wherein the patterned semiconductor layer includes a channel region above the gate as well as a source and a drain lying on opposite sides of the channel region; a barrier layer, which only wraps the source and the drain; and a second patterned conducting layer disposed on the barrier layer and the dielectric layer. 
         [0017]    The detailed technology and preferred embodiments implemented for the present invention are described in the following paragraphs accompanying the appended drawings for people skilled in this field to well appreciate the features of the claimed invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0018]      FIG. 1  is a schematic cross-sectional view of a conventional display element structure; and 
           [0019]      FIGS. 2A to 7  are schematic cross-sectional views of the present invention. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0020]    Initially, refer to  FIG. 2A , a transistor region  3011  and a capacitance region  3013  are defined on a substrate  301 . The substrate  301  is generally a glass substrate, but is not just limited thereto; optionally, a quartz substrate, a polymer substrate or other transparent substrates may also be used. Then, a conducting layer is formed on the substrate  301  by a suitable process such as a sputtering process to deposit thereon. The conducting layer can be made of copper or its alloys, but other suitable conductive metal materials such as aluminum may also be optionally used. Subsequently, a lithographic process and an etching process are utilized to pattern the conducting layer into a first patterned conducting layer  303 , which comprises a gate  3031  located in the transistor region  3011  and a first conductor  3033  located in the capacitance region  3013 . 
         [0021]    Next, refer to  FIG. 2B  a dielectric layer  305  is formed by any suitable conventional deposit processes (e.g., a chemical vapor deposition (CVD) process) to cover the first patterned conducting layer  303 . The dielectric layer  305  may be made of silicon nitride. However, a silicon oxide layer, a composite layer of silicon nitride and silicon oxide, or other suitable dielectric layers may also be used. 
         [0022]    Next, a patterned semiconductor layer  307  is formed at a predetermined transistor location on the dielectric layer  305 . Specifically, refer to  FIG. 3 , a channel layer  3071  and a source/drain layer  3073  are formed in sequence on the dielectric layer  305  by using any suitable conventional deposition processes (e.g., a CVD process). Generally, the channel layer  3071  can be an amorphous silicon layer, while the source/drain layer  3073  can be a doped amorphous silicon layer, for example, an N+ doped amorphous silicon layer. Next, lithographic and etching processes are performed to pattern the channel layer  3071  and the source/drain layer  3073  to form a patterned semiconductor layer  307  on the predetermined transistor location. Typically, the resulting channel layer  3071  will become a channel region on the gate of the transistor, while the resulting source/drain layer  3073  will provide a source and a drain located at opposite sides of the channel region. 
         [0023]    Subsequently, refer to  FIG. 4 , a selectively depositing process is performed to selectively form a barrier layer  309 , which only wraps or covers the patterned semiconductor layer  307 . The barrier layer  309  is typically made of a metal, which may be a material selected from a group consisting of nickel (Ni), Chromium (Cr), cobalt (Co), manganese (Mn), niobium (Nb), Ruthenium (Ru), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), gold (Au), silver (Ag), other transition metals and a combination thereof. The selective depositing process may be for example an electroless plating process or other electrochemical plating process. 
         [0024]    The electroless plating process is, in short, a kind of chemical plating method, which does not need a current but rather utilizes electric charges released from the oxidation of a reductant agent in an electroplating solution. These electric charges are supplied to the surrounding metal ions, so that the metal ions will be reduced to deposit on a target surface with a catalytic effect or a seed crystallized effect. As the target surface catalyzes the electroless plating reaction, the metal adheres on the target surface to form a metal layer, which in turn serves to catalyze the reductive deposition of the next layer of metal. Consequently, the thickness of the metal layer builds up gradually to finally result in a uniform and compact metal layer. Generally, a suitable electroplating solution may be selected for the electroless plating process depending on the metal to be formed, so that the metal will be only deposited on the surface of a particular material. It can be seen that the electroless plating process features deposition selectivity, i.e., the metal is only deposited on a surface with a catalytic effect or a seed crystallized effect. By forming a barrier layer using such a characteristic, the conventional problems of lithographic and etching process can be eliminated. 
         [0025]    An example of forming a nickel barrier layer on a patterned semiconductor layer by using an electroless plating process will be described hereinafter. In this illustrative electroless plating process, a nickel-containing electroplating solution may be used, for example, a NiSO 4  containing solution. The electroplating solution should preferably comprise 0.01 to 0.1 M of NiSO 4 .6H 2 O, 0.01 to 0.5 M of NH 4 Cl, 1 to 20 wt % (weight percentage) of N 2 H 4 , and 0.5 to 5.0 wt % of NH 4 OH. The electroplating solution used for the electroless nickel plating process may comprise 0.03 M of NiSO 4 .6H 2 O, 0.1 M of NH 4 Cl, 30 wt % of N 2 H 4 , and 1.4 wt % of NH 4 OH. In the electroless plating process of this embodiment, nickel is substantially only formed on the patterned semiconductor layer  307 , which has silicon-silicon bonds, but not on the dielectric layer  305  which has silicon-nitrogen bonds. As a result, the nickel barrier layer will only wrap the patterned semiconductor layer  307 . The barrier layer thus formed is uniform and compact, and has a thickness typically in the range from 10 to 800 nm. 
         [0026]    Next, refer to  FIG. 5A , a second conducting layer  311  is deposited on the substrate  301  using a suitable process such as sputtering. A suitable material for the second conducting layer  311  can be copper and its alloys, but aluminum or other conductive metals may also be optionally used. Subsequently, refer to  FIG. 5B , lithographic and etching processes are performed to pattern the second conducting layer  311  into a second patterned conducting layer  313 , which comprises a source electrode  3131  and a drain electrode  3133  in the transistor region  3011  as well as the second conductor  3135  in the capacitance region  3013 . Specifically, a portion of both the doped amorphous silicon layer  3073  and the barrier layer  309  above the gate  3031  in the transistor region  3011  are simultaneously removed in the etching process. The removal of these portions may be accomplished by using a wet etching or a dry etching process. As a result, in the transistor region  3011 , the second patterned conducting layer  313  remains on the barrier layer  309  above the patterned semiconductor layer  307  (i.e., on the barrier layer  309  above the source and the drain), to serve as the source electrode  3131  and the drain electrode  3133  electrically connected with the source and the drain respectively. Correspondingly, in the capacitance region  3013 , the second patterned conducting layer  313  remains on the dielectric layer  305  above the first conductor  3033  as a second conductor  3135 . 
         [0027]    It can be seen from  FIG. 5B  that a barrier layer  309  may be selectively formed only around the semiconductor layer  307  by using an electroless plating process without any additional masks, i.e., the barrier layer  309  only wraps the semiconductor layer  307 . Additionally, since the electroless plating process only forms a barrier layer  309  around the patterned semiconductor layer  307 , the barrier layer  309  only exists between the patterned semiconductor layer  307  and the source electrode  3131 /the drain electrode  3133 . That is, the barrier layer  309  only exists underneath a portion of the second patterned conducting layer  313  above the patterned semiconductor layer  307 , and not underneath other portions of the second patterned conducting layer  313 , as shown by the dashed lines in  FIG. 5B . This may not only reduces the exposed interface between the second patterned conducting layer  313  and the barrier layer  309 , but also reduces the regions where the dual-layer structure of the second patterned conducting layer  313  and the barrier layer  309  exists, thus, eliminating unnecessary resistance and improving the overall performance of the transistor. 
         [0028]    Next, refer to  FIG. 6 , a patterned passivation layer  315  is formed above the substrate  301 . The patterned passivation layer  315  has a first opening  3151  exposing a portion of the drain electrode  3133  and a second opening  3153  exposing a portion of the second conductor  3135 . The patterned passivation layer  315  is typically made of silicon nitride, but a silicon oxide layer, a composite layer of silicon nitride and silicon oxide, or other suitable dielectric layers may also be used. 
         [0029]    Finally, refer to  FIG. 7 , a pixel electrode  317  is formed on a portion of the patterned passivation layer  315  and within the openings  3151 ,  3153  for electrical connection to the drain electrode  3133  and the second conductor  3135 . 
         [0030]    In summary, according to the invention, a uniform and compact barrier layer can be formed only on the semiconductor layer by using a selective deposition process. As an electroless plating process, the selective deposition does not require any additional masks. Thus, conventional problems of manufacturing a transistor are eliminated by using the present invention. That is, the undercutting of the barrier layer is eliminated, thus preventing the degradation of the transistor and allows control of the conductor width. In addition the resistance attributed to the dual-layer structure comprised of the conducting layer and the barrier layer is maintained. 
         [0031]    The above disclosure is related to the detailed technical contents and inventive features thereof. People skilled in this field may proceed with a variety of modifications and replacements based on the disclosures and suggestions of the invention as described without departing from the characteristics thereof. Nevertheless, although such modifications and replacements are not fully disclosed in the above descriptions, they have substantially been covered in the following claims as appended.