Abstract:
A voltage switching apparatus and method are disclosed. At least one disclosed method includes providing, when a mode selection signal is in a first state, a first power rail voltage on a first power voltage line and a second, different power rail voltage on a second power voltage line. After the mode selection signal transitions to a second state, a second power rail voltage is provided on the first power voltage line and a switch between the first and second power voltage lines is closed.

Description:
CROSS-REFERENCE TO A RELATED APPLICATION  
       [0001]     The present application claims the benefit of, and incorporates by reference, provisional application Ser. No. 60/574,456, filed May 25, 2004, and entitled “Apparatus And Method For Voltage Switching.” 
     
    
     BACKGROUND  
       [0002]     Personal computer systems typically include a peripheral component interconnect bus, which is more commonly known as a PCI bus. Industry standards for the PCI bus and closely related bus technologies are defined by a special interest group, PCI-SIG®. PCI-SIG has defined industry standards for PCI Conventional, PCI Express, and PCI-X technologies. These different standards reflect an evolution of the PCI standard in response to a need for increased bus bandwidth. In designing the newer standards, PCI-SIG provided for backward compatibility with the older standards.  
         [0003]     Computers with PCI-compliant buses employ slot connectors having a number of conductive spring-loaded contacts. When a PCI-compliant circuit board is inserted into the slot connector, the spring-loaded contacts make contact with conductive traces near one edge of the circuit board. The slot connectors have only a fixed number of contacts, and hence the standard provides for only a fixed number of bus signal lines. As new PCI-related standards are defined, the functions of some of these bus signal lines are redefined.  
         [0004]     To provide for backward compatibility, computers may employ a bus that operates in different modes. For example, the PCI-X standard provides that more recent PCI-X buses should operate in at least two different modes. Mode  1  provides backward compatibility with legacy PCI-X devices, while mode  2  provides enhanced bus performance. In mode  1 , the power signal for the bus is 3.3 volts, while in mode  2  the power signal is 1.5 volts. A bus controller identifies the appropriate mode for the devices in each slot, and employs some switching mechanism to supply the appropriate power to the power signal line(s). The switching mechanism must satisfy fairly various electrical requirements in the PCI-X standard. Improvements relating to such switching mechanisms are desirable. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0005]     The following detailed description can be better understood with reference to the following figures:  
         [0006]      FIG. 1  is a block diagram of a computer system including a PCI-X bus bridge and a PCI-X bus, according to various embodiments of the present invention;  
         [0007]      FIG. 2  is a block diagram of a PCI-X bus bridge connected to a PCI-X bus having multiple PCI slots, according to various embodiments of the present invention;  
         [0008]      FIG. 3  is a block diagram of a switching circuit, according to one embodiment of the present invention; and  
         [0009]      FIG. 4  is a block diagram of another switching circuit, according to one embodiment of the present invention. 
     
    
       [0010]     While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the appended claims.  
       NOTATION AND NOMENCLATURE  
       [0011]     Certain terms are used throughout the following description and claims to refer to particular system components and configurations. As one skilled in the art will appreciate, companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function.  
         [0012]     In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . .” 
         [0013]     The term “couple” or “couples” is intended to mean either an indirect or a direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.  
         [0014]     The term “power rail” is intended to mean a conductor carrying a direct-current (DC) voltage from a power source.  
         [0015]     The components within the drawings are not necessarily to scale relative to each other, emphasis instead being placed upon clearly illustrating the disclosed principles. Matching reference numerals indicate corresponding components throughout the various figures.  
       DETAILED DESCRIPTION  
       [0016]      FIG. 1  shows a block diagram of an illustrative computer system  100  having (among other things) a processor  102 , a memory bridge  105 , a system memory  110 , a video controller  115 , and an I/O bridge  120 . The memory bridge  105  couples the processor  102  to system memory  110  and to the I/O bridge  120 . The video controller  115  may be coupled to the processor  102  via the memory bridge  105 , or via the I/O bridge  120 . The processor  102  executes software instructions stored in memory  110  to retrieve data from any of various I/O devices, to process the data, and to produce results that typically are displayed on a monitor (not shown) coupled to video controller  115 . The processor  102  may alternatively or additionally provide computational results to various I/O devices.  
         [0017]     The I/O bridge  120  couples the processor  102  and memory  110  (via memory bridge  105 ) to one or more peripheral buses. Examples of peripheral buses include a small computer system interface (“SCSI”) bus  125 , a low pin count (“LPC”) bus  135 , and a PCI-X bus  150 . The various I/O devices couple to one of the peripheral buses to communicate with the rest of the computer system  100 . In  FIG. 1 , for example, a nonvolatile storage device  130  (such as a magnetic or optical disk) couples to the SCSI bus  125 . A keyboard  140  and a mouse  145  couple to the LPC bus  135 . Socket connectors for other peripherals  155 A,  155 B (such as a sound card, a network interface, a modem, an external information storage device, or a data acquisition card) couple to the PCI-X bus  150 . I/O bridge  120  includes a PCI-X bus bridge  160  that supports communications with any PCI-X devices that may be inserted in the socket connectors.  
         [0018]     In at least some embodiments, the PCI-X bus bridge  160  may support PCI-X mode  1  and PCI-X mode  2  devices. As is described below in more detail, the PCI-X bus bridge  160  is configured to receive a mode selection signal that results from the influence of each attached PCI-X device  155 A,  155 B. Each device may ground or isolate the mode selection signal line in accordance with a desired operating mode for that device. The PCI-X bus bridge may determine the operating mode for the PCI-X bus  150  in response to the resulting mode selection signal.  
         [0019]      FIG. 2  shows a block diagram of the PCI-X bus bridge  160  connected to a PCI-X bus  150  having PCI slots  240 A,  240 B. The PCI-X bus bridge  160  includes a mode selection circuit  205  coupled to a 1.5 volt power rail and a 3.3 volt power rail. The mode selection circuit  205  sources a power voltage (“Bridge V I/O ”) for the PCI-X bus bridge control circuitry and a power voltage (“Slot V I/O ”) for devices inserted in the PCI slots. This configuration allows tight control of variations between these power voltages.  
         [0020]     Power voltages Bridge V I/O  and Slot V I/O  are provided on power lines  210  and  225 , respectively.  FIG. 2  shows various elements of PCI-X bus  150 , including a ground line  220 , Slot V I/O  power line  225  (noted above), a set of control lines  230 , and a set of data lines  235 . Other signal lines may be included as well.  FIG. 2  further shows the various signal lines connected to PCI slots  240 A and  240 B, which in turn are respectively coupled to removable PCI-X devices  255 A and  255 B. In one particular embodiment, slot  240 A may support both PCI-X mode  1  and mode  2 , while slot  240 B may be limited to PCI-X mode  1 .  
         [0021]     The PCI-X devices in the above-described embodiments may be PCI cards that fit a PCI socket. PCI sockets hold such cards by frictional contact, allowing the cards to be easily removed. In alternative embodiments, the PCI-X devices may be integrated onto a circuit board with the PCI-X bus bridge  160  and other computer components.  
         [0022]      FIG. 3  shows a block diagram of the switching circuit  205  according to one embodiment of the present invention. Switching circuit  205  includes a control circuit  310  coupled to two selector circuits  320 A,  320 B by a pair of control signals  322  and  324 . A mode selection signal is generated by the operation of removable PCI-X devices on bus  150  (e.g., by each device&#39;s grounding or high-impedance connection of a bus signal line in accordance with their desired bus operating mode). The control circuit  310  receives a mode selection signal  305  and converts it into two control signals  322 ,  324 . In the embodiment of  FIG. 3 , the mode selection signal is 0 and 3.3 volts for logical low and logical high, respectively. The control signals  322 ,  324  are 0 and 12 volts for logical low and logical high, respectively. Control signal  322  may be logically low when the mode selection signal  305  is low, and may be logically high when the mode selection signal is high. Loosely speaking, the control signal  324  is the logical inverse of control signal  322 , although in one embodiment positive-going edges of control signal  322  are slightly delayed relative to negative-going edges of control signal  324 . The control circuit  310  uses both control signals  322 ,  324  to control each of the two selector circuits  320 A,  320 B.  
         [0023]     The selector circuits  320 A,  320 B each have four input lines (SEL+, SEL−, INP 0 , INP 1 ) and one output line (OUT). Each selector circuit electrically couples the INP 0  signal line to the OUT signal line when the SEL+ control line is logically high. Similarly, each selector circuit electrically couples the INP 1  signal line to the OUT signal line when the SEL− control line is high. The electrical connections may be provided via a transistor, a relay, or some other form of electrical switch internal to the selector circuit.  
         [0024]     Selector circuit  320 A may be configured as follows. The SEL+ control line receives control signal  322 , the SEL− control line receives control signal  324 , the INP 0  signal line is coupled to a 3.3V power rail, the INP 1  signal line is coupled to a 1.5V power rail, and the OUT signal line is coupled to the Slot V I/O  power line  225 . In response to the various control and input signals, selector circuit  320 A provides the Slot V I/O  power voltage on line  225 .  
         [0025]     Selector circuit  320 B may be configured as follows. The SEL+ control line receives control signal  324 , the SEL− control line receives control signal  322 , the INP 0  signal line is coupled to Slot V I/O  power voltage line  225 , the INP 1  signal line is coupled to a 1.5V power rail, and the OUT signal line is coupled to the Bridge V I/O  power voltage line  210 . In response to the various control and input signals, selector circuit  320 B provides the Bridge V I/O  power voltage on line  210 .  
         [0026]     The operation of switching circuit  205  is as follows. A low mode selection signal  305  causes control circuit  310  to force control signal  322  low and to force control signal  324  high. This assertion of control signal  324  causes selector circuit  320 A to electrically couple the Slot V I/O  power voltage line  225  to the 1.5V power rail, and causes selector circuit  320 B to electrically couple the Bridge VI/O power voltage line  210  to the Slot V I/O  power voltage line  225 . This configuration is suitable for PCI-X mode  2  operation of bus  150 . A transition of the mode selection signal  305  from low to high causes control circuit  310  to force control signal  324  to transition from high to low. In one embodiment, control signals  322  and  324  are both momentarily low before control signal  322  transitions from low to high. While both control signals are low, both selector circuits electrically isolate their OUT signal lines from both of the input signal lines. After control signal  322  transitions to a logical high, selector circuit  320 A electrically connects the Slot V I/O  power voltage line  225  to the 3.3V power rail, and selector circuit  320 B electrically connects the Bridge VI/O power voltage line  210  to the 1.5V power rail. This configuration is suitable for PCI-X mode  1  operation of bus  150 .  
         [0027]      FIG. 4  shows an illustrative implementation of switching circuit  205 . The illustrative implementation employs a 0.1 μF capacitor C 1 , two 1 kΩ resistors R 1 , R 2 , and six n-channel MOSFETs Q 1 -Q 6 . Capacitor C 1 , resistors R 1  and R 2 , and transistors Q 1  and Q 2  form one implementation of control circuit  310 . Transistors Q 3  and Q 4  form one implementation of selector circuit  320 A, and transistors Q 5  and  06  form an implementation of selector circuit  320 B.  
         [0028]     Transistor Q 1  has a gate coupled to the mode selection signal line  305 , a drain coupled to a 12V power rail via resistor R 1 , and a source coupled to ground. The control signal line  324  is coupled between the drain of transistor Q 1  and the gates of transistors Q 2 , Q 4 , and Q 5 . Transistor Q 2  has a drain coupled to the 12V power rail via resistor R 2 , and a source coupled to ground. The control signal line  322  is coupled from the drain of transistor Q 2  to the gates of transistors Q 3  and Q 6 . Capacitor C 1  is coupled between ground and control signal line  322 . Transistor Q 3  has a drain coupled to a 3.3V power rail, and a source coupled to Slot V I/O  power voltage line  225 . Transistor Q 4  has a drain coupled to Slot V I/O  power voltage line  225 , and a source coupled to a 1.5V power rail. Transistor Q 5  has a drain coupled to the Slot V I/O  power voltage line  225 , and a source coupled to the Bridge V I/O  power voltage line  210 . Transistor Q 6  has a source coupled to the Bridge V I/O  power voltage line  210 , and a source coupled to the 1.5V power rail.  
         [0029]     The operation of the  FIG. 4  implementation is as follows. When mode selection signal  305  is low (about 0V), transistor Q 1  is OFF. When transistor Q 1  is OFF, resistor R 1  pulls control signal  324  high (about 12V), causing transistors Q 2 , Q 4 , and Q 5  to turn ON. Transistor Q 2  pulls control signal line  322  low (about 0V), causing transistors Q 3  and Q 6  to turn OFF. Transistor Q 4  couples the Slot V I/O  power voltage line  225  to the 1.5V power rail, and transistor Q 5  couples the Bridge V I/O  power voltage line  210  to the Slot V I/O  power voltage line  225 . This configuration is suitable for PCI-X mode  2  operation of bus  150 .  
         [0030]     When mode selection signal  305  transitions from low to high (about 3.3V), transistor Q 1  turns ON, pulling control signal line  324  to go low (about 0V) and causing transistors Q 2 , Q 4 , and Q 5  to turn OFF. Then transistor Q 2  is OFF, capacitor C 1  begins charging via resistor R 2 , bringing control signal line  322  high (about 12 V) after a few tenths of a millisecond. While both control signal lines  322  and  324  are low, transistors Q 3 -Q 6  are OFF, causing both the Slot V I/O  power voltage line  225  and the Bridge V I/O  power voltage line  210  to be isolated from the voltage rails. As control signal line  322  goes high, transistors Q 3  and Q 6  turn ON. Transistor Q 3  couples the Slot V I/O  power voltage line  225  to the 3.3V power rail, and transistor Q 6  couples the Bridge V I/O  power voltage line  210  to the 1.5V power rail. This configuration is suitable for PCI-X mode  1  operation of bus  150 .  
         [0031]     Although various illustrative embodiments have been described with respect to specific voltages and parameter values, the present invention is not so limited. Other embodiments may use different voltages and different parameter values. Although the various embodiments described above are discrete hardware implementations, a software implementation may be feasible. The software embodiments may comprise a series of computer instructions either fixed on a computer-readable storage medium (e.g. a diskette, a CD-ROM, a ROM, or fixed disk) or transmittable to a modem or other interface device in a computer system via a transmission medium. The transmission medium can be a tangible medium such as optical or analog communications lines, or may be intangible such as a wireless communications network. It may also be the Internet.  
         [0032]     It will be apparent to those skilled in the art that many modifications and variations may be made to the embodiments as set forth above without departing substantially from the principles of the present invention. All such modifications and variations are intended to be limited only by the appended claims.