Abstract:
A core voltage to input output voltage level shifter of the type that uses a reference voltage source to generate a reference voltage to limit a drain voltage on at least one voltage sensitive node connected to a voltage sensitive switching device, that resides on a high voltage domain. A feed back line runs from the voltage sensitive node to the reference voltage source. A feed back structure varies the reference voltage in response to the drain voltage on the at least one voltage sensitive node, and thereby maintains the drain voltage at a substantially constant desired value.

Description:
FIELD  
         [0001]    This invention relates to the field of integrated circuit design. More particularly, this invention relates to voltage level shifting between relatively voltage sensitive core transistors and relatively voltage tolerant input output transistors.  
         BACKGROUND  
         [0002]    Traditionally, all of the various components of an integrated circuit were powered at a single voltage level. However, in more recent technologies, different components of an integrated circuit are powered from different voltage sources. For example, in some new technologies the core of an integrated circuit, such as the memory or logic components, is powered off of one voltage source, and the input output components of the integrated circuit are powered off of a different voltage source. Typically, the core voltage level, generally designated as VDDcore, is nominally 1.2 volts or less and the input output voltage level, generally designated VDDio, is nominally 3.3 volts. An integrated circuit that is powered by more than one voltage source typically uses a level translator, also called a voltage level shifter, to step digital signals between the core voltage level and the input output voltage level.  
           [0003]    However, as integrated circuit designs have evolved, the demands on level shifters have also evolved. For example, as the core voltage has dropped in potential, it has approached the lower-most levels at which the relatively voltage tolerant input output transistors function, also known as the threshold voltage of the input output transistors. In other words, the signals received from a voltage sensitive core transistor by a voltage tolerant input output transistor may be at so low a level, that the voltage tolerant input output transistor may not operate properly or reliably in response to the lower voltage signal. Thus, there is a need for an alternate signal to trigger the operation of the relatively voltage tolerant input output transistors in level shifters.  
           [0004]    Conversely, as the core voltage has dropped in potential, the relatively voltage sensitive core transistors have become increasingly sensitive to the relatively higher input output voltage potentials. In other words, the signals received from a voltage tolerant input output transistor by a voltage sensitive core transistor are at so high a level, that the voltage sensitive core transistor may be damaged in response to the higher voltage signal. Thus, there is a need for a reliable signal threshold to limit the signal to the relatively voltage sensitive core transistors in level shifters.  
           [0005]    There is a need, therefore, for new designs of level shifters.  
         SUMMARY  
         [0006]    The above and other needs are met by an improvement in a core voltage to input output voltage level shifter of the type that uses a reference voltage source to generate a reference voltage to limit a drain voltage on at least one voltage sensitive node connected to a voltage sensitive switching device, that resides on a high voltage domain. A feed back line runs from the voltage sensitive node to the reference voltage source. A feed back structure varies the reference voltage in response to the drain voltage on the at least one voltage sensitive node, and thereby maintains the drain voltage at a substantially constant desired value. It is appreciated that when it is stated herein that the drain voltage at the voltage sensitive node is maintained at a substantially constant desired value, this does not mean that the voltage sensitive node is held at this potential during a logical low state, but rather the voltage sensitive node is held at the constant desired value during the logical high state. Any problem that there may be with the voltage sensitive node drawing down to a logical low state is not specifically considered herein.  
           [0007]    Thus, in a most preferred embodiment as described herein, the reference voltage source uses feed back from the voltage sensitive node to control the voltage potential on the voltage sensitive node. In this manner, the preferred designs tend to be less sensitive to models and model predictability, temperature, and VDDio drift. Further, the preferred designs generate a stable protection voltage on the voltage sensitive node, rather than just a specific reference voltage value. These designs are also very tolerant of temperature, process, and voltage variations on the voltage sensitive regulating devices.  
           [0008]    In various preferred embodiments the feed back structure is an op amp with a first input tied to the feed back line, and a second input tied to one of a variety of different inputs. For example, the second input can be tied to a low voltage domain, such as VDDcore, or an X gain stage that produces an output that is a desired multiple of an input to the X gain stage. In one embodiment the input to the X gain stage is the low voltage domain, such as VDDcore. In an alternate embodiment the input to the X gain stage is a band gap reference voltage with an input on the high voltage domain, such as VDDio. The X gain stage is most preferably a circuit that produces an output that is a multiple of its input and a ratio of two passive elements, such as resistors.  
           [0009]    According to another aspect of the invention there is also presented a method for limiting a drain voltage on at least one voltage sensitive node connected to a voltage sensitive switching device residing on a high voltage domain in a core voltage to input output voltage level shifter. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]    Further advantages of the invention are apparent by reference to the detailed description when considered in conjunction with the figures, which are not to scale so as to more clearly show the details, wherein like reference numbers indicate like elements throughout the several views, and wherein:  
         [0011]    [0011]FIG. 1 is a circuit diagram of a level shifter,  
         [0012]    [0012]FIG. 2 is a circuit diagram of an alternate embodiment of a level shifter,  
         [0013]    [0013]FIG. 3 is a circuit diagram of a level shifter with a reference voltage,  
         [0014]    [0014]FIG. 4 is a circuit diagram of an alternate embodiment of a level shifter with a reference voltage,  
         [0015]    [0015]FIG. 5 is a circuit diagram of a level shifter with a reference voltage from a voltage divider,  
         [0016]    [0016]FIG. 6 is a circuit diagram of a level shifter replica bias circuit for generating a reliable level shifter cascade reference voltage,  
         [0017]    [0017]FIG. 7 is a circuit diagram of a level shifter replica bias circuit for generating a reliable level shifter cascade reference voltage, using a multiple of the VDDcore supply voltage,  
         [0018]    [0018]FIG. 8 is a circuit diagram of an adjustable source,  
         [0019]    [0019]FIG. 9 is a circuit diagram of a level shifter with a feed back reference voltage from a band gap reference voltage, and  
         [0020]    [0020]FIG. 10 is a functional block diagram of an integrated circuit with the level shifters according to a preferred embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0021]    [0021]FIGS. 1 and 2 depict two level shifter designs  10 . FIG. 1 depicts a signal to gate MOS level shifter  10 , and FIG. 2 depicts a signal to source MOS level shifter  10 . Although not all of the various embodiments presented herein are depicted in combination with both of these two designs, it is appreciated that the various embodiments are equally applicable to both of these designs, and that such additional embodiments are within the scope of the present invention.  
         [0022]    With reference now to FIG. 10, the level shifters  10  shift the voltage of digital signals between the voltage potential used for core devices  17 , such as transistors, and the voltage potential used for input output devices  15 , such as transistors, which make electrical connections to the bonding pads  13  of the integrated circuit  11 . As described elsewhere herein, the core devices  17  preferably operate at a relatively lower voltage, nominally about 1.2 volts or lower, and thus are relatively more voltage sensitive than the input output devices  15 . Similarly, the input output devices  15  preferably operate at a relatively higher voltage, nominally about 3.3 volts, and thus are relatively less voltage sensitive than the core devices  17 . The voltage potential of the core devices  17  tends to be insufficient to reliably drive the input output devices  15 , and the voltage potential of the input output devices  15  tends to be great enough to damage the core devices  17 . In FIG. 10, individual core devices  17  and individual input output devices  15  are not depicted, rather just the general regions of such devices are depicted, so as to not unnecessarily encumber the figure with inessential details.  
         [0023]    With reference again to FIGS. 1 and 2, the level shifter  10  is fabricated with both relatively voltage sensitive core transistors  14 , and relatively voltage tolerant input output transistors  12 . It is appreciated that although the relatively sensitive transistors  14  are generally designated as core transistors herein, they do not necessarily perform the same functions as the core transistors of the integrated circuit. Rather, the designation of core transistor as applied to the relatively sensitive transistors  14  implies that they are of a similar design as the core transistors, with regard to at least their voltage sensitivity and the voltage domain in which they are primarily designed to function. Similarly, although the relatively tolerant transistors  12  are generally designed as input output transistors herein, they also do not necessarily perform the same functions as the input output transistors of the integrated circuit. Rather, the designation of input output transistor as applied to the relatively tolerant transistors  12  implies that they are of a similar design as the input output transistors, with regard to at least their voltage sensitivity and the voltage domain in which they are primarily designed to function.  
         [0024]    With reference to the voltage shifters  10  of FIGS. 1 and 2, VDDcore, or VDD 12 , with a voltage of no more than about 1.2 volts is applied to the gate of at least one of the voltage tolerant transistors  12 , because the drain of that device may go to VDDio. However, as described above, reducing the high gate potential on a voltage tolerant device  12  to such a low value, such as 1.2 volts, 1.0 volt, 0.8 volts or even lower with current technology, tends to cause the voltage tolerant device  12  to function very slowly and also requires it to be quite big in terms of surface area. Often, such a device does not function reliably, because the VDDcore is so close to the threshold voltage of the voltage tolerant device  12  that the voltage tolerant device  12  does not switch reliably.  
         [0025]    With reference now to FIG. 3, there is depicted a modified embodiment of the voltage shifter  10  of FIG. 1, in which a reference voltage from a reference voltage source  20  is applied on line  18  at the gates of two additional transistors  12   a  within the voltage shifter  10 . FIG. 4 depicts the voltage shifter  10  of FIG. 2 that has been modified with a reference voltage source  20  that provides a reference voltage on line  18  at the gates of two additional transistors  12  with the voltage shifter  10 . The subsequent figures depict only the various embodiments in reference to the voltage shifter  10  of FIG. 1. However, as mentioned above, it is appreciated that all such alternate embodiments are applicable to the design of FIG. 2, even though not explicitly depicted herein.  
         [0026]    With the reference voltage applied to their gates, the voltage tolerant devices  12   a  act as voltage regulators within the voltage shifter  10 . The reference voltage is preferably selected to insure that the drain of the switching device  14   a  does not exceed VDDcore. In this manner, the voltage sensitive devices  14   a , as depicted in FIGS. 3 and 4, are protected from a voltage potential that would tend to damage them. Thus, the switching transistors  14   a  in the embodiments of FIGS. 3 and 4 can be fabricated from faster voltage sensitive devices, rather than from slower voltage tolerant devices  12 , as depicted in FIGS. 1 and 2.  
         [0027]    With reference now to FIG. 5, there is depicted a specific embodiment of reference voltage source  20 , where the reference voltage is derived from VDDio with a voltage divider. Unfortunately, the voltage divider of the reference voltage source  20  of this embodiment may not provide a constant reference voltage under certain circumstances, and thus may not adequately limit the voltage that is seen by the voltage sensitive switching devices  14   a . For example, such a voltage divider tends to be sensitive to temperature drift, has direct sensitivity to variations and noise in VDDio, is sensitive to VDD ramp during power up, and draws direct current power between VDDio and VSS. To minimize the direct current power, the reference voltage becomes a high impedance node and may move considerably in value while the level shifter  10  switches. Further, even with a steady reference voltage in this configuration, the reliability critical voltages on the input nodes  25  will tend to vary over process and temperature as the threshold voltage and gamma of the voltage tolerant regulator devices  12   a  vary.  
         [0028]    With reference now to FIG. 6 there is depicted a further embodiment of the voltage shifter  10 , where an op amp  24  is employed as the reference voltage source  20 . One of the inputs as depicted is tied to VDDcore, but may also be tied to VSS. The other input of the op amp  24  is tied to at least one of the voltage sensitive input nodes  25  via line  22 . In this manner, the voltage potential on the nodes  25 , and thus the voltage potential on the inputs of the voltage sensitive switching devices  14   a , is preferably never greater than about VDDcore. Whenever a drift in the voltage potential on the nodes  25  begins to occur, the drift is corrected by the controlling output of the op amp  24  on line  18 . Thus, the reference voltage source  20  of this preferred embodiment incorporates a feed back on line  22 . The op amp  24  is preferably of a type that remains substantially linear from about to VSS to about VDDcore, and is most preferably a PMOS input stage. However, a high gain op amp is not required. Rather, a very simple, slow, low power op amp may be used.  
         [0029]    In some cases, the drain voltage reliability of the MOSFETS of the voltage shifter  10  is different than their gate voltage reliability. For example, in some cases hot electron degradation may dictate that the voltage on the sensitive nodes  25  be preferably limited to a lower potential than VDDcore, such as (0.9)(VDDcore). Alternately, in some cases the devices are more drain voltage tolerant than gate voltage tolerant, such as due to voltage division between the drain depletion layer and the gate oxide. In the designs as presented, the overriding design goal is most preferably to limit Vdrain on the voltage sensitive switching devices  14   a , and not necessarily Vgate.  
         [0030]    Therefore, if it is known that the voltage sensitive switching devices  14   a  have different drain voltage tolerances, such as X(VDDcore), where X is preferably a number between about 0.8 and 1.2, then the reference voltage source  20  is preferably fabricated as depicted in FIG. 7. The embodiment of the voltage shifter  10  as depicted in FIG. 7 places an X gain stage  26  on the input of the op amp  24 , and then puts VDDcore as an input to the X gain stage  26 . FIG. 8 depicts a preferred embodiment of the X gain Stage  26 , where the output  28  of the X gain stage  26  is substantially equal to the input, which in this case is VDDcore, multiplied by the ratio of the value of two passive elements, which in the embodiment of FIG. 8 are resistors R 1  and R 2 . Thus, the output  28  of the X gain stage  26  can be either greater than or less than the input of the X gain stage  26 .  
         [0031]    In some embodiments it may be desirable to use a band gap reference voltage rather than VDDcore as the input to the X gain stage  26 . The band gap reference voltage tends to be more stable over process and temperature than VDDcore, has less noise than VDDcore, and can be generated off of VDDio. Thus, the reference voltage source  20  can produce the reference voltage on line  18  before VDDcore comes up. This embodiment is depicted in FIG. 9, Where the reference voltage source  20  includes a band gap reference voltage  30  that is tied to one of the inputs of the X gain stage  26 .  
         [0032]    Thus, in the most preferred embodiment as described herein, the reference voltage source  20  is a low impedance node rather than a high impedance node, which tends to be more stable when the level shifter  10  operates at higher frequencies. Further, the preferred designs tend to be less sensitive to models and model predictability, temperature, and VDDio drift. Further, the preferred designs generate a stable protection voltage on the voltage sensitive nodes  25 , rather than just a specific reference voltage potential on the reference voltage line  18 . These designs are also very tolerant of temperature, process, and voltage variations on the regulating devices  12   a.    
         [0033]    The foregoing embodiments of this invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise form disclosed. Obvious modifications or variations are possible in light of the above teachings. The embodiments are chosen and described in an effort to provide illustrations of the principles of the invention and its practical application, and to thereby enable one of ordinary skill in the art to utilize the invention in various embodiments and with various modifications as is suited to the particular use contemplated. All such modifications and variations are within the scope of the invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally, and equitably entitled.