Abstract:
In an apparatus for controlling a signal processing system to operate in high and low speed modes, a control unit determines a speed of system clock signals in accordance with the interpretation of a program when external clock signals are received. When a speed of the system clock signals is determined, the control unit controls the production of the system clock signals of a frequency dependent on the speed. As a result, a peripheral circuit of a low speed can be controlled to operate without the necessity of a complicated interface circuit, and a system of a high speed such as a system for the so-called television game can also be controlled to operate. Further, a limitation on an operation speed of a peripheral circuit is excluded so that an expansion of a signal processing system can be easy to be performed. Still further, all circuits of the signal processing system can be under operation states because a low speed mode is first realized when a power supply is turned on.

Description:
This application is a continuation of application Ser. No. 07/876,807 filed Apr. 30, 1992 now abandoned, which is a continuation of application Ser. No. 07/696,274, filed May 2, 1991 now abandoned, which is a continuation of application Ser. No. 07/247,440 filed Sep. 6, 1988 now abandoned. 
    
    
     FIELD OF THE INVENTION 
     The invention relates to an apparatus for controlling a signal processing system to operate in high and low speed modes, and more particularly to an apparatus for controlling a signal processing system to operate in high and low speed modes in which system clock signals of a predetermined speed are produced in accordance with a speed of an operation mode. 
     BACKGROUND OF THE INVENTION 
     One of conventional apparatus for controlling a signal processing system to operate in high and low speed modes comprises a circuit for producing system clock signals and a control unit for controlling the signal processing system to operate in a predetermined mode. The circuit for producing system clock signals is controlled to produce system clock signals of a high or low speed in accordance with a high or low speed operation mode by the control unit. Therefore, the signal processing system can be switched over to operate in a low speed operation mode in accordance with system clock signals of a low speed in a case where a peripheral circuit of a low speed operation is included in the signal processing system. 
     According to the conventional apparatus for controlling a signal processing system to operate in high and low speed modes, however, there is a disadvantage that signals which are processed in accordance with high and low speed clock signals compete with each other on a bus in a case where a charge-over command by which the low speed operation mode is changed over to the high speed operation mode is produced in accordance with an error or a misinterpretation of a program when the low speed operation mode is being conducted. A further disadvantage is that a complicated interface circuit is required to be provided in a case where a peripheral circuit of a low speed operation is controlled to operate. A still further disadvantage is that an apparatus for controlling a signal processing system to operate in a low speed mode can not control a system of a high speed operation mode such as a system for the so-called television game. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the invention to provide an apparatus for controlling a signal processing system to operate in high and low speed modes in which signals which are processed in accordance with high and low clock signals are avoided to compete with each other on a bus. 
     It is a further object of the invention to provide an apparatus for controlling a signal processing system to operate in high and low speed modes a complicated interface circuit is not require to be provided even in a case where a peripheral circuit of a low operation speed is controlled to operate. 
     It is a still further object of the invention to provide an apparatus for controlling a signal processing system to operate in high and low speed modes in which a speed of system clock signals is controlled to change in accordance with a program. 
     According to the invention, an apparatus for controlling a signal processing system to operate in high and low speed modes comprises a memory in which a predetermined program is stored, a circuit for producing system clock signals, and a control unit for the system to operate in a predetermined mode. The predetermined program stored in the memory includes a content by which a speed of system clock signals is determined, and the circuit for producing system clock signals produces system clock signals of a high or low speed in accordance with the division of external clock signals by a predetermined frequency dividing ratio. The control unit interprets the program to determine a speed of a system operation thereby controlling the circuit to produce system clock signals of an above determined speed, and produces a mode signal corresponding to the speed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will be explained in more detail in conjunction with appended drawings wherein, 
     FIG. 1 is a block diagram showing an image displaying apparatus to which an apparatus for controlling a signal processing system to operate in high and low speed modes according to the invention is applied, 
     FIG. 2 is a block diagram showing an apparatus for controlling a signal processing system to operate in high and low speed modes in an embodiment according to the invention, and 
     FIGS. 3 to 5 are timing charts showing operations in the embodiment. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In FIG. 1, there is shown an apparatus for displaying a color image to which an apparatus for controlling a signal processing system (CPU) 1 according to the invention is applied. In the apparatus for displaying a color image, a CPU 1 performs a predetermined control in accordance with a program stored in ROM 5 so that data, arithmetical results etc. are stored into a RAM 6 temporarily. A video display controller 2 is provided therein to supply a video color encoder 3 with video data of a story, for instance, for a so-called television game read from a video RAM (VRAM) 7 in accordance with a control of the CPU 1 which deciphers a program for the television game stored in the ROM 5. The video color encoder 3 to which the video data are supplied produces RGB analog signals obtained in accordance with color data stored therein, or produces video color signal including a luminance signal and color difference signals obtained in accordance with the color data. Further, a programable sound generator 4 is provided therein to produce analog sound signals as left and right stereo sounds in accordance with a content of the ROM 5 which is supplied through the CPU 1 thereto. The video color signal produced in the video color encoder 3 is supplied through an interface 8 to a receiving circuit of a television set 9 as a composite signal, and the RGB analog signal is supplied through an interface 10 directly to a CRT of the television set 9 which functions as an exclusive use monitor means. On the other hand, the left and right analog sound signals are supplied through amplifiers 11a and 11b to speakers 12a and 12b to produce sounds. 
     FIG. 2 shows the CPU 1 and the programable sound generator 4 as encircled by a dotted line in FIG. 1. The CPU 1 in which an apparatus for controlling a signal processing system in the embodiment is included and comprises an instruction register 20, an instruction decoder 21, a bus interface register 22, an arithmetic and logic unit (ALU) 23, a set of registers 24, a mapping register 25, a chip enable decoder 26, a timing and control unit 27, an input and output port 28, a timer 29, an interrupt request register 30, an interrupt disable register 31, and so on. These units will be explained as follows. 
     (1) Instruction Register 20 
     The register 20 is loaded with an instruction code at an instruction fetch cycle. 
     (2) Instruction Decoder 21 
     The decoder 21 performs a sequential operation determined in accordance with an output of the instruction register 20, an interrupt input from a peripheral circuit or a reset input, and further performs a control of a brunch command changing a flow of a program in accordance with informations of a status register described later. 
     (3) Bus Interface Register 22 
     The register 22 controls a transfer of data among a B-bus 32, a U-bus 33 and an external bus D0 to D7. The ALU 23 and the set of registers 24 are connected by the B-bus 22 and the U-bus 33, and is connected to internal peripheral circuits. Further, a L-bus 34 for transferring lower eight bits of a logical address and a H-bus 35 for transferring upper eight bits of the logical address are provided. A logical address low register 48 is connected to the L-bus 34, and a logical address high register 49 is connected to the H-bus 35. 
     (4) ALU 23 
     The ALU 23 is provided with an A register 36 and a B register 37, and performs all of arithmetic and logical operation. The A and B registers 36 and 37 are loaded with one or two data so that an arithmetic operation is performed in accordance with a control signal of the instruction decoder 21 to supply one of the B, L and H-buses 32, 34 and 35 with a result of the arithmetic operation. 
     (5) Set of Registers 24 
     The set of registers 24 comprises following ten registers each being of eight bits. 
     (a) accumulator 38 
     The accumulator 38 is a wide use register which plays the most important role in an arithmetic and logical operation to be conducted when a memory arithmetic flag T of a status register described later is &#34;0&#34;. Data thereof is supplied to an input of the ALU 23, and a result of the arithmetic is stored therein. The accumulator 38 is also used for a transfer of data between memories and between a memory and a peripheral circuit, and for a count of a data block length when a block transfer of data is performed. A lower data of the length are stored therein after data stored therein at the very moment are evacuated into a stack region of the RAM 6. 
     (b) X and Y registers 39 and 40 
     The registers 39 and 40 are wide use registers which are mainly used for an index addressing. The X register 39 is used for a designation of an address on page &#34;0&#34; of a memory which is a destination of an arithmetic operation, and for a storage of lower data of a source address after data stored therein at the very moment are evacuated into a stack region of the RAM 6 when a block transfer of data is performed. On the other hand, the Y register 40 stores lower data of a destination address after data stored therein at the very moment are evacuated into a stack region of the RAM 6 when a block transfer of data is performed. 
     (c) program counters 41 and 42 
     An up counter of sixteen bits is composed of the program counter 41 of upper eight bits and the program counter 42 of lower eight bits. The up counter is automatically incremented in accordance with the conduct of a command to designate an address of a command or operand to be next conducted. Contents of the counters 41 and 42 are evacuated into a stack region of the RAM 6 in a case where a command of sub-routine is conducted, and an interrupt is produced, or after an interruption command of a software is conducted. 
     (d) stack pointer 43 
     The stack pointer 43 designates lower eight bits of the highest address on a stack region of the RAM 6, and is decremented after the pushing of data into the stack region and incremented before the pulling of the data from the stack region. For instance, two hundreds fifty-six (256) bytes of addresses &#34;2100&#34; to &#34;21FF&#34; are allocated to the stack region in a logical address. 
     (e) source high register 45, destination high register 46, and length high register 47 
     These registers function in case of a command of a block transfer. The source high register 45 provides an upper byte of a source address to designate the source address together with a content of the X register 39. The destination high register 46 provides an upper byte of a destination address to designate the destination address together with a content of the Y register 40. The length high register 47 provides upper eight bits for a down counter together with a content of the accumulator 38 so that a length of a block transfer is counted by a byte unit. 
     (6) Mapping Register 25 
     The mapping register 25 is composed of eight registers each being of eight bits to convert a logical address of sixteen bits to a physical address of twenty-one bits, and is selected by upper three bits of the H-bus 35. 
     (7) Chip Enable Decoder 26 
     The chip enable decoder 26 provides chip enable outputs for following peripheral circuits by decoding upper eleven bits of a physical address. 
     (a) a chip enable for the RAM 6 . . . CER 
     (b) a chip enable for the video display controller 2 . . . CE7 
     (c) a chip enable for the video color encoder 3 . . . CEK 
     (d) a chip enable for the programable sound generator 4 . . . CEP 
     (e) a chip enable for the timer 29 . . . CET 
     (f) a chip enable for the input and output port . . . CEIO 
     (g) a chip enable for the interrupt request register 30 and the interrupt disable register 31 . . . CECG 
     (8) Timing and Control Unit 27 
     The unit 27 is connected to following terminals. 
     (a) RD terminal 
     A read timing signal is supplied through the RD terminal at a reading cycle. 
     (b) WR terminal 
     A write timing signal is supplied through the WR terminal at a writing cycle. 
     (c) SYNC terminal 
     A synchronous signal of &#34;high&#34; is supplied through the SYNC terminal at an instruction fetch cycle, that of &#34;low&#34; is supplied therethrough at a system reset timing. 
     (d) NMI terminal 
     A non-maskable interrupt is produced when NMI input signal is supplied through the NMI terminal. A sub-routine call is conducted by reading lower address from the logic address &#34;FFFC&#34; and upper address from the logical address &#34;FFFD&#34; when a command which is conducted in a program is completed. 
     (e) IRQ1 and IRQ2 terminals 
     A sub-routine call is conducted by reading lower address from the logical 1 address &#34;FFF8&#34; and upper address from the logical address &#34;FFF9&#34; when IRQ1 input becomes &#34;low&#34; in a case where a corresponding bit in the interrupt disable register 31 is &#34;0&#34;, and a corresponding bit in the status register 44 is &#34;0&#34;. At this time, the corresponding bit is set in the status register 44, and other corresponding bits are reset therein. 
     A sub-routine call is conducted by reading lower address from the logical address &#34;FFF6&#34; and upper address from the logical address &#34;FFF7&#34; when IRQ2 input becomes &#34;low&#34; in a case where a corresponding bit in the interrupt disable register 31 is &#34;0&#34;, and a corresponding bit in the status register 44 is &#34;0&#34;. At this time, the corresponding bit is set in the status register 44, and other corresponding bits are reset therein. 
     (f) REST terminal 
     A program is started by reading lower address from the physical address &#34;001FFE&#34; and upper address from the physical address &#34;001FFF&#34; when a RESET input becomes &#34;low&#34;. 
     (g) RDY terminal 
     The CPU1 is started to operate when a RDY input is changed from &#34;low&#34; to &#34;high&#34;. 
     (h) SX terminal 
     A complementary signal of a system clock signal is supplied through the SX terminal. 
     (i) OSCI terminal 
     An external clock signal is input through the OSCI terminal. 
     (j) EA1 to EA3 terminals 
     These are input terminals for a test of the CPU1. 
     (k) HSM terminal 
     A speed signal of &#34;high&#34; is supplied through the HSM terminal in case of a high speed mode of 21.47727 MHz/3, and that of &#34;low&#34; is supplied therethrough in case of a low speed mode of 21.47727 MHz/12. 
     (9) Input and Output Port 28 
     The port 28 is connected to following terminals. 
     (a) K0 to K7 terminals 
     The terminals are input ports from which data are written in accordance with the conduct of a reading cycle in regard to the physical addresses &#34;1FF000&#34; to &#34;1FF3FF&#34;. 
     (b) 00 to 07 terminals 
     The terminals are output ports with latches to which data are supplied in accordance with the conduct of a writing cycle in regard to the physical addresses &#34;1FF000&#34; to &#34;1FF3FF&#34;. 
     (10) Timer 29 
     The timer 29 is connected to a test input terminal EAT for the CPU1 and provides a timer signal through the U-bus thereto. 
     (11) Interrupt Request Register 30 
     The register 30 is of eight bits among which five bits are not used, while the remaining two bits are &#34;1&#34; to show the IRQ1 and IRQ2terminals &#34;low&#34; and the remaining one bit is &#34;1&#34; to show a timer interrupt caused. The register 30 is only used for &#34;read&#34;. 
     (12) Interrupt Disable Register 31 
     The register 31 is of eight bits among which five bits are not used, while the remaining two bits are &#34;0&#34; to make an interrupt request of the IRQ1 and IRQ2 terminals disable, and the remaining one is &#34;0&#34; to make an interrupt request disable in accordance with the timer interrupt signal. 
     Next, operation of an apparatus for controlling a signal processing system to operate in high and low speed modes in the embodiment will be explained. 
     (1) High Speed Mode (HSM) 
     When external clock signals of 21.47727 MHz is supplied through the terminal OSCI to the timing and control unit 27 as shown in FIG. 2, the CPU 1 interprets a program stored in ROM 5 thereby determining a high speed mode to be selected so that a command of CSH (Change Speed High) is conducted to set a high speed mode. In the high speed mode, system clock signals S 1 , S 2 , and S 3  (7.16 MHz) as shown in FIG. 3 are produced by dividing the external clock signals of 21.47727 MHz by one-third. Simultaneously, a high speed mode signal &#34;1&#34; is supplied through the terminal HSM to a peripheral circuit. As a result, the video display controller 2, the video color encoder 3, the programable sound generator 4 and so on which are connected to the CPU 1 are controlled to operate in the high speed mode. The system clock signals S 1 , S 2 , and S 3  are supplied as complementary signals through the terminal SX to a periphery circuit wherein one bus cycle is defined as a period from a rising edge of the system clock signal S 1 , to a next rising edge thereof. The one bus cycle is a basic bus cycle by which a command conduct cycle is defined in each of commands. 
     (2) Low Speed Mode (LSM) 
     External clock signals of 21.47727 MHz which are supplied through the terminal OSCI in accordance with a command CSL (Change Speed Low) are divided by one-twelfth. As a result, system clock signals (1.79 MHz) are produced as shown in FIG. 4, and supplied as complementary signals through the terminal SX to a peripheral circuit. Simultaneously, a low speed mode signal &#34;0&#34; is supplied through the terminal HSM to peripheral circuit. 
     (3) Change Over Between Two Modes 
     FIG. 5 shows a change over between high and low speed modes. Here, it is assumed that a command CSH by which a processing speed of the CPU 1 is set as a high speed mode, a non-operation command NOP, and a command CSL by which a processing speed of the CPU 1 is set as a low speed mode are produced at timings shown therein. A starting time at which the command CSH is produced is in a low speed mode during which system clock signals S 1 , S 2  and S 3  are of 1.79 MHz in accordance with one-twelfth frequency division and supplied as complementary signals through the terminal SX. At this time, a mode signal HSM is &#34;0&#34;. After one bus cycle is then elapsed, a high speed mode is realized in accordance with the command CSH so that system clock signals are of 7.16 MHz in accordance with one-third frequency division. At this time, a mode signal HSM is &#34;1&#34;. Next, when a command CSL is produced, a low speed mode is then realized after one cycle bus thereof. During operations, a program is counted by a program counter PC. 
     Although the invention has been described with respect to specific embodiment for complete and clear disclosure, the appended claims are not to thus limited but are to be construed as embodying all modification and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.