Abstract:
The invention describes structures and a process for providing ESD protection between multiple power supply lines or buses on an integrated circuit chip. Special diode strings are used for the protection devices whereby the diodes are constructed across the boundary of an N-well and P substrate or P-well. The unique design provides very low leakage characteristics during normal circuit operation, as well as improved trigger voltage control achieved by stacking 2 or more diodes in a series string between the power buses.

Description:
FIELD OF THE INVENTION 
   The present invention relates generally to the structure and process for an ESD protection arrangement for ESD protection of single and multiple power supply feeds for integrated circuits and specifically to diode protection devices with associated parasitic bipolar transistors for power to power ESD protection. 
   DESCRIPTION OF PRIOR ART 
   Protection of integrated circuits from large, abnormal voltage or current surges such as caused by electrostatic discharge events (ESD) is increasingly important as device geometry is decreased. In particular the high impedance and relatively fragile gate oxide of field effect (FET) devices places further emphasis on the need for ESD protection. In addition multiple power lines often called power or voltage buses or rails require ESD protection with the protection devices affording minimum leakage between the various voltages levels and between the voltage levels and the reference level, typically ground. Some typical multiple power rail applications are mixed voltage interface circuitry and some dynamic random access memory applications. 
   One type of device typically used for ESD protection is the diode used singularly as shown in Prior Art  FIG. 1A  or in a “stacked” series string as indicated in Prior Art FIG.  2 A. Stacking the diodes in a series string can increase the breakdown threshold or trigger voltage, but not as much as often desired to match application requirements Although diodes can provide effective ESD protection, conventional diodes have a leakage current component during normal operation which can be detrimental to normal circuit operation. The logic circuits being protected are represented by element  8  in Prior Art  FIGS. 1A and 2A . 
     FIG. 1B  shows a typical prior art ESD protection diode device structure. An N-well  14  is shown on a P doped substrate  10 . The basic diode D 1  is contained within the P-well  14 . The anode is formed by the P+ region  16 , while the cathode is formed by the N-well  14  and the N+ contact region  18 . The diode device D 1  is therefore in series with the P+ anode contact region  16  and the N+ cathode contact region  18 . VDD 2  is connected to the N+ contact  18  and is typically a higher positive potential than VDD 1 , which is connected to the P+ contact  16 . 
   Also shown in  FIG. 1B  is the parasitic PNP bipolar transistor TX 1  whose emitter is formed by the P+ contact region  16 , the base is formed by the N-well  14  and the collector is formed by the substrate  10 . The collector is connected to the reference voltage Vss, typically ground, through a substrate diffusion resistance represented by R 1 , and the substrate P+ contact  12 . 
   During a positive ESD event on VDD 2 , the diode D 1  goes into a secondary breakdown mode conducting the ESD energy between VDD 2  and VDD 1 . The bipolar transistor TX 1  also will go into breakdown mode conducting the ESD energy to the reference voltage source, or ground. The secondary breakdown current occurs at a “snapback” voltage level much less than the threshold voltage, reducing the power dissipation in this region that is also known as the holding current region. 
     FIG. 2A  illustrates a diode series string protection circuit. The multiple diodes D 1 , D 2  are intended to increase the trigger or threshold voltage of the protection circuit. 
   The device structure of a prior art series diode string is illustrated in FIG.  2 B. In addition to the first N-well  14 , with related P+ contact  16  and N+ contact  18  and which contains a first diode D 1  with associated parasitic PNP bipolar transistor TX 1 , a second N-well  124  is present on the P doped substrate  10 . The second N-well  24  contains the second diode D 2 , with associated parasitic bipolar transistor TX 2 . 
   Diode D 2  is formed in a similar way in the second N-well  24  as diode D 1  is formed in the first N-well  14 . The anode of diode D 2  is formed from the P+ doped contact region  26 , while the second N-well  24  forms the cathode. The emitter of TX 2  is formed by the P+ contact  26 , the base by the second N-well  24  and the N+ contact  28 , and the collector by the P substrate  10  and performs a similar function as TX 1  in N-well  14 . 
   The first N-well  14  N+ doped contact region  18  is connected by a conductor element  20  to the P+ doped contact region  26  of the second N-well  24 . The two diodes in series increase the reverse threshold voltage to provide a measure of “tuning” the protective circuit to the application requirements. 
   However, as noted, leakage can increase appreciably with this method of creating the ED protection devices. 
   The invention provides a unique and novel method and structure for providing diode devices with minimum leakage for ESD protection by utilizing a diode device structure outside of the N-well proper. 
   The following patents and reports pertain to ESD protection. 
   U.S. Pat. No. 5,907,464 (Maloney et al.) discusses diode strings in ESD devices in the prior art section. 
   U.S. Pat. No. 5,877,927 (Paret et al) shows an ESD device with diode strings. 
   U.S. Pat. No. 6,157,530 (Pequignot et al.) shows an ESD device with diode strings. 
   U.S. Pat. No. 5,959,820 (Ker et al.) shows a LVTSCR and ESD device. 
   SUMMARY OF THE INVENTION 
   Accordingly, it is the primary objective of the invention to provide an effective structure and manufacturable method for providing an ESD clamping protection element for power bus protection and connection. 
   It is a further objective of the invention to provide ESD protection for power-to-power incidents while providing lower protection device leakage and the ability to increase operating voltage with increased diodes in a string without appreciably increasing protection device leakage. 
   A still additional objective of the invention is to provide the ESD protection with reduced device leakage without changing the characteristics of the internal circuits being protected and by using a process compatible with the process of integrated MOS device manufacturing. 
   The above objectives are achieved in accordance with the methods of the invention that describes a structure and a manufacturing process for semiconductor ESD protection devices with reduced leakage characteristics. 
   One embodiment of the invention utilizes a PN diode as an ESD energy clamp from an integrated circuit first voltage source (VDD 1 ) to an integrated circuit second voltage source (VDD 2 ). The second voltage source (VDD 2 ) is typically at a higher potential than the first voltage source (VDD 1 ). A typical example would be where VDD 1  would be 1.8 volts and VDD 2  would be 3.3 volts. 
   VDD 1  is connected to a P+ doped contact region within a N-well on a P substrate. VDD 2  is connected to a N+ doped contact region on the substrate in proximity to, but outside of, the N-well. A unique feature of the invention is in relocating the N+ contact from within the N-well and locating it within the P substrate or within a P well external to the N-well. This separates the P+ and N+ elements by an additional N−P junction, which provides additional isolation and hence reduced leakage. 
   A second embodiment of the invention is to string two or more ESD power protection devices in series. This is again accomplished by locating the N+ cathode terminal of the device outside of the associated N-well. The second device is replicated by using a second N-well and connecting the first device N+ cathode terminal to the second device P+ terminal by means of a separate electrical conductor. The two devices are now in series, but maintain a reduced leakage characteristic. The number of series devices can be increased to a relatively large practical number because of the low leakage characteristic. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1A  shows a schematic representation of a prior art ESD protection scheme with a single diode between VDD 1  and VDD 2 . 
       FIG. 1B  shows the device configuration of the prior art single diode ESD device. 
       FIG. 2A  shows a schematic representation of a prior art two-diode string protection device scheme. 
       FIG. 2B  shows the device configuration for the prior art two diode string protection device scheme. 
       FIG. 3  shows the device configuration for one embodiment of the invention. 
       FIGS. 4A and 4B  show the device configuration for another embodiment of the invention with more than one device in the series string. 
       FIGS. 5A and 5B  show the I-V holding characteristics of the invention devices for 1, 2 and 3 diodes plus one new with one prior art diode showing the controlled differences for turn-on threshold voltages for the different configurations. 
       FIGS. 6A and 6B  show the test leakage currents for prior art diode protection devices at both 25° C. and 125° C. 
       FIGS. 7A and 7B  show the test leakage currents for the invention devices at 25° C. and 125° C. showing the improved leakage characteristics of the invention. 
       FIG. 8A  shows the ESD protection current for prior art devices. 
       FIG. 8B  shows the ESD protection current for the invention devices. 
   

   DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 3  shows the device structure arrangement of one embodiment of the invention. Starting with a P doped substrate  110 , typically created on a single crystal silicon wafer of &lt;100&gt; crystal orientation and with a typical doping level of between 1E15 and 5E15 a/cm 3 , processing is initiated as is well known in the art to define the active device areas. 
   After appropriate processing as is well understood in the art, an N-well is defined. This is typically done using a donor dopant such as phosphorous (P) in an ion implant process with an implant energy typically in the range of between 400 and 800 KeV and a dopant concentration of between 6E12 and 2E13 a/cm 2 . The resulting N-well has a typical dopant density of between 1E16 and 1E18 a/cm 3 . 
   Contained within the N-well  114  is a P+ contact  116 . Again, this is created by methods well known in the art. One such method is ion implant with an acceptor element such as boron (B) in a dosage of between 1E15 and 5E15 a/cm 2  and implant energy of between 4 and 10 KeV. The resultant P+ region  116  has a typical dopant concentration of between 1E20 and 1E21 a/cm 3 . 
   As shown in  FIG. 3 , the P substrate  110  contains a N+ doped contact region  118 . Again, this contact region or element is created by conventional methods as is well known in the art such as ion implant. A typical donor dopant such as arsenic (As) at a dosage of between 1E15 and 6E15 a/cm 2 , an implant energy of between 20 and 80 KeV could typically be used to create the N+ region  118 . The resulting N+ region  118  typically has a dopant density of between 1E20 and 1E21 a/cm 3 . 
   The P+ region  116  forms the anode of protection device diode D 11 . It also forms the emitter of the parasitic PNP bipolar transistor TX 11 . The N-well  114  forms the cathode of the protection diode D 11  as well as the base region of the parasitic PNP transistor TX 11  and the collector of a parasitic NPN bipolar transistor TX 13 . The diode D 11  is essentially electrically in parallel with the transistor TX 11  emitter-base junction. 
   The P substrate  110  forms the collector of parasitic PNP transistor TX 11  and also forms the base of the NPN bipolar transistor, TX 12 . TX 12  is a NPN parasitic transistor whose collector is formed by the N-well  114 , the base as previously noted by the substrate  110 , and the emitter by the substrate N+ contact region  118 . The substrate  110  also forms the anode of protection diode D 12 . The cathode of D 12  is formed by the substrate N+ contact region  118 . 
   The essence of this embodiment of the invention is the moving of the N+ region from inside the N-well  114  as in prior art to a region outside of, but adjacent to, the N-well  114 . This provides a base collector junction in addition to the protection diode junctions, which reduces the leakage characteristic of a single diode junction as in prior art. 
   In the invention arrangement, the N-well  114  P+ doped contact  116  and the substrate  110  N+ contact  118  in proximity to N-well  114  essentially form a doped region pair. The doped region pair, or doped pair, together with the N-well  114  and substrate  110 , contains all the required elements of the invention protection device. 
   Diode D 11  anode is connected to a first logic voltage supply VDD 1 , by an external conductor  117 . External conductor  119  connects the cathode of diode D 12  to a second supply voltage, VDD 2 . VDD 2  is normally a higher voltage potential than VDD 1  in normal circuit operation. In the event of a positive ESD event on power line VDD 2 , diodes D 12  and D 11  will go into reverse breakdown and conduct the energy into the first power line VDD 1 . This low voltage conduction path shunts the ESD energy away from the normal active logic circuits or other elements that may be attached to the power bus. 
   Another embodiment of the invention is shown in  FIG. 4A  for the case when it is desirable to connect more than one diode in a series string between the power buses. Again, the devices are on a P doped substrate  110 . The substrate  110  doping is similar to before, that is, the P dopant concentration is in the range between 1E15 and 5E15 a/cm 3 . There is a first N-well  114  created from a known process such as ion implant from a donor dopant such as P to produce a N-well with a dopant concentration of between 1E16 and 1E18 a/cm 3 . 
   As shown in  FIG. 4A , a P+ doped region  116  exists within the first N-well  114 . Again, the dopant concentration of P+ region  116  is typically in the range of between 1E20 and 1E21 a/cm 3 . The P+ doped region is connected to a first voltage, VDD 1 , by an external conductor element  117 . 
   Within the substrate  110  is a second N-well  124  with similar dopant characteristics to the first N-well  114 . The second N-well  124  also has a P+ doped region  128 , with similar dopant characteristics to the P+ doped region  116  within the first N-well  114 . That is a dopant concentration in the range between 1E20 and 1E21 a/cm 3 . 
   Again referring to  FIG. 4 , it can be seen that external to the two N-well areas are a first N+ region  118  in proximity to N-well  114  and a second N+ region  128  in proximity to N-well  124 . Each substrate N+ contact region ( 118 ,  128 ) essentially forms a doped pair with the associated N-well P+ contacts ( 116 ,  126 ). That is, N+ contact region  118  is essentially paired with P+ contact  116 , and N+ contact  128  is essentially paired with P+ contact  126 . 
   The two N+ regions have been created in a similar well-known manner. For example by means of ion implantation with a donor dopant such as As at a dosage of between 1E15 and 5E15 a/cm 2  and a energy between 20 and 80 KeV. The resultant N+ regions will have a dopant concentration of between 1E20 and 1E21 a/cm 3 . 
   The first substrate N+ region  118  is connected to the second N-well P+ region  126  by an external conductor element  120 . The second substrate N+ element  128  is connected to a second voltage source, VDD 2 , by means of an external conductor element  119 . 
   The first N-well  114  P+ region  116  forms the anode of protection diode D 11  and the emitter of the parasitic PNP bipolar transistor TX 11 . The first N-well  114  forms the diode D 11  cathode and the base of PNP bipolar transistor TX 11 . The first N-well  114  also forms the collector of parasitic bipolar NPN transistor TX 12 . The P substrate forms the anode of diode  12  and the base of transistor TX 12 . 
   The second N-well  124  P+ region  126  forms the cathode of diode D 13  and the emitter of bipolar transistor TX 13 . The second N-well  124  forms the base of TX 113 , the cathode of diode D 13 , and the collector of transistor TX 14 . The substrate  110  forms the collector of transistor TX 13 , the base of parasitic NPN bipolar transistor TX 14 , and the anode of diode D 14 . Completing the circuit, the N+ substrate contact  128  forms the emitter of the NPN bipolar transistor TX 14  and the cathode of diode D 14 . The cathode of D 12  is connected to the anode of D 13  by an external conductor element  120  that is connected to N+ region  118  and the P+ region  126 . 
   The circuit arrangement enabled by this invention embodiment allows two or more diodes to be placed in series between the two power supply lines.  FIG. 4B  illustrates a case where n devices in series are inserted between VDD 1  and VDD 2 . The number of devices can vary from 2 to 10 to match application conditions. 
   The n-th protection devices are contained in and derived from the n-th doped pair and are essentially the same type devices as derived from the first and second doped pair. 
     FIG. 5A  shows the results of the “Hold” I-V characteristics of the invention device designated as P+/NW−N+. The test conditions are 25 degrees centigrade (° C.) and with the P substrate tied to ground. The onset or threshold of breakdown is clearly seen for each configuration followed by the “snapback” region where the voltage rapidly decreases from the initial voltage. A relatively constant voltage is reached where current rapidly increases. This voltage is known as the “holding” voltage and should be reasonably low in order to minimize the power dissipation during the ESD event. 
   The invention diode devices are designated as P+/NW−N+. A series string of 2 invention diodes is designated by the suffix ^2 and a three invention diode string is designated by ^3. A special case of one invention diode device and one prior art device in a series string designated as P+/NW−N+ diode is included for comparison purposes. The data for this arrangement is very similar to the curve trace for P+/NW−N+ ^2 demonstrating no degradation in holding voltage characteristics for the invention devices. 
     FIG. 5B  shows the same test conditions repeated at 125° C. Again, the consistency of the holding voltage relative to the prior art device can be seen. 
   It can be seen in  FIG. 5A  that an increase in the number of diodes in the string from one to 3 increases the threshold, or ESD turn-on voltage, from approximately 3.0 volts for one diode to 7.0 volts for 2 diodes and almost 13 volts for 3 invention diode devices. This demonstrates the degree of control in threshold voltage obtained by using a different number of diodes in the string from one power bus to another. 
   Table 1 below is a summary of the “Holding Voltages”, exhibited by the invention devices and one invention device and one prior art device designate 1+1 in the table. The holding voltage is a key characteristic of ESD protection devices as the lower the holding voltage, the less the power dissipation for a given current level. 
   The table illustrates the maximum change in holding voltage for different numbers of invention diode devices in the diode string at 25° C. and 125° C. and the P substrate grounded. Included in the table is an addition test case at 25° C. whereby the substrate is left floating. 
   The 25° C. and 125° C. rows are measurements taken at the respective temperatures with the substrate Vss connection grounded The Vss Floating row represents measurements taken with the substrate Vss connection floating. 
   As indicated in the table, the maximum holding voltage is 3.34 volts for 3 diodes in a string. 
   
     
       
             
           
             
             
             
             
             
           
         
             
               TABLE 1 
             
             
                 
             
             
               Holding Voltage vs. Number of Invention Device Diodes 
             
             
               Holding Voltage vs. Number of Invention Diodes 
             
             
                 
             
           
           
             
                 
             
           
        
         
             
               No. of Diodes 
               1 
               2 
               3 
               1 + 1* 
             
             
                25° C. - Vss Gnd 
                1.0 V 
               2.16 V 
               3.34 V 
               1.98 V 
             
             
               125° C. - Vss Gnd 
                0.9 V 
               1.86 V 
               2.78 V 
                1.6 V 
             
             
                25° C. - Vss Floating 
               0.92 V 
                2.0 V 
                2.3 V 
                1.0 V 
             
             
                 
             
             
               *1 + 1 diodes is 1 invention diode, 1 prior art diode  
             
           
        
       
     
   
     FIGS. 6A and 6B  show the DC I-V characteristics of the prior art diode strings at 25° C. and 125° C. It is seen that the leakage current starts rising rapidly with increasing voltage. For example, if a “turn-on” current is assumed to be 1 microamp (uamp), this value is reached at a nominal voltage of 0.6 volts for a single prior art diode at 25° C. At 125° C. the leakage current curve is much steeper, with 1 uamp of current being reached at a nominal 0.4 volts. 
     FIGS. 7A and 7B  show the leakage characteristics of the invention devices at 25° C. and at 125° C. showing significant improvement in the leakage current over prior art devices. Indeed, a 1 uamp current is not reached until a nominal voltage of 10 volts for both 25° C. and 125° C. This outstanding improvement in leakage current characteristics shows one significant advantage of the invention devices. 
     FIGS. 8A and 8B  show the ESD protection breakdown I-V characteristics of prior art devices and the invention devices respectively. The one prior art diode device is designated “diode” in the legend, a three prior art diode string is designated “diode ^3”, and five prior art diodes are designated “diode ^5” in the chart legend. The invention device characteristics are shown in  FIG. 8B. A  single invention diode is designated “P+/NW−N+” in the chart legend. Two invention devices are designated “P+/NW−N+^2” and three invention devices are designated “P+/NW−N+^3”. An invention diode device in series with a prior art device is designated “P+/NW−N++ diode”. 
   The prior art diode together with the invention device exhibits similar protection characteristics as two of the invention devices. Also, comparing  FIGS. 8A and 8B  shows that ESD protection current characteristics are similar for both prior art and invention devices. Therefore, there is no degradation in ESD protection for invention devices that exhibit superior leakage characteristics as shown in  FIGS. 6A through 7B . 
   Table 2 below summarizes the maximum ESD current capability before failure for various diode string configurations as shown in  FIGS. 8A and 8B . The maximum current is essentially the same for all configurations, which is between 5.3 amps and 5.6 amps. 
   
     
       
             
           
             
             
             
             
             
             
           
         
             
               TABLE 2 
             
             
                 
             
             
               Maximum ESD Current vs. Number of Invention Devices in String 
             
             
               Maximum Current vs. Number of Devices 
             
             
                 
             
           
           
             
                 
             
           
        
         
             
               No. of Devices 
               1 
               2 
               3 
               5 
               1 + 1* 
             
             
               Invention Devices 
               5.5 A 
               5.5 A 
               5.5 A 
               — 
               5.5 A 
             
             
               Vss Floating 
             
             
               Invention Devices 
               5.4 A 
               5.4 A 
               5.4 A 
               — 
               5.4 A 
             
             
               Vss Ground 
             
             
               Prior Art Devices 
               5.3 A 
               — 
               5.6 A 
               5.4 A 
             
             
                 
             
             
               *1 + 1 diodes is 1 invention diode, 1 prior art diode  
             
           
        
       
     
   
   While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.