Abstract:
A cascade A/D converter configured by connecting in cascade two or more stages of electronic circuits, each stage comprising a comparator to convert an analog input signal to a digital signal, a latch circuit to hold the output of the comparator, a D/A converter to convert the output of the comparator to an analog signal, and a subtractor to subtract the output of the D/A converter from the analog input signal; wherein are provided a waveform composition circuit to compose code changing waveforms in the comparators, a plurality of detecting devices for detecting each vicinity of code changing points for detecting the code changes in the comparators by receiving the changing waveforms in the waveform composition circuit as inputs, and an error correction circuit that rejects noise generated at the code changing points based on the outputs of the detecting devices; whereby errors due to noise are substantially eliminated.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of Invention 
     This invention relates to a cascade A/D converter with error correction that is error free; and more particulary, to such converter that prevents generation of errors due to noise. 
     2. Description of the Prior Art 
     A/D converters include those which are of small scale, low power consumption and low input capacity. This type of converter uses a single clock and provides high speed operation. However, there is a problem of error generation in such converters. The inventors had disclosed in Japan Unexamined Application SN 9/238,077 (1997), a cascade A/D converter which uses a single clock and is operable without errors. Such a device is described in FIG. 1, which shows a cascade 5-bit A/D converter that outputs an alternate binary code (also called “gray” code). The device comprises comparators  8   a - 8   d ; latch circuits  9   a - 9   e ; D/A converters  10   a - 10   c ; subtractors  11   a - 11   c ; comparators  13   a - 13   h ; logical product circuits (called “AND circuits”)  14 - 17 ; exclusive logical sum circuits (called “EOR circuits”)  18 - 20 ; logical sum circuits (called “OR circuits”)  21 - 23 ; and AND circuits  24 ,  25 . Analog input signal  100   a  and digital output signal  101   a  are provided as shown. 
     Comparators  13   a , 3   b  and AND circuit  14  comprise window comparator  50   a . Comparators  13   c ,  13   d  and AND circuit  15  comprise window comparator  50   b . comparators  13   e , 13   f  and AND circuit  16  comprise window comparator  50   c . Comparators  13   g ,  13   h  and AND circuit  17  comprise window comparator  50   d . OR circuits  21 - 23  and and circuits  24 , 25  comprise error correction circuit  51 . 
     Analog input signal  100   a  is applied to each non-inverted input terminal of comparators  8   a  and  13   a , inverted input terminal of comparator  13   b  and the addition input terminal of subtractor  11   a . The output terminal of comparator  8   a  is connected to latch circuit  9   a , D/A converter  10   a , and one input terminal of EOR circuit  18 . The output terminal of D/A converter  10   a  is connected to the subtraction input terminal of subtractor  11   a . The output terminal of comparators  13   a  and  13   b  are connected to the input terminals of AND circuit  14 . The output terminal of AND circuit  14  is connected to one input terminal of OR circuit  21  and to the negative logic input terminals of AND circuits  15 - 17 ,  24  and  25 . 
     The output terminal of subtractor  11   a  is connected to each noninverted input terminal of comparators  8   b  and  13   c , inverted input terminal of comparator  13   d  and the addition input terminal of subtractor  11   b . The output terminal of comparator  8   b  is connected to D/A converter  10   b , the other input terminal of EOR circuit  18 , and one input terminal of EOR circuit  19 . The output terminal of D/A converter  10   b  is connected to the subtraction input terminal of subtractor  11   b . Each output terminal of comparators  13   c  and  13   d  is connected to the other two positive logic input terminals of AND circuit  15 , respectively. The output terminal of AND logic circuit  15  is connected to one input terminal of OR circuit  22  and each of the negative logic input terminals of AND circuits  16 , 17  and  25 . The output terminal of EOR circuit  18  is connected to the other input terminal of OR circuit  21 . The output terminal of OR circuit  21  is connected to the latch circuit  9   b.    
     The output terminal of subtractor  11   b  is connected to each non-inverted input terminal of comparators  8   c  and  13   e , the inverted input terminal of comparator  13   f , and the addition input terminal of subtractor  11   c . The output terminal of comparator  8   c  is connected to D/A converter  10   c , the other input terminal of EOR circuit  19 , and one input terminal of EOR circuit  20 . The output terminal of EOR circuit  19  is connected to the other input terminal of OR circuit  22 . The output terminal of OR circuit  22  is connected to the positive logic input terminal of AND circuit  24 . The output terminal of AND circuit  24  is connected to latch circuit  9   c . Each output terminal of comparators  13   e  and  13   f  is connected to the other two positive logic input terminals of AND circuit  16 , respectively. The output terminal of AND circuit  16  is connected to one input terminal of OR circuit  23  and the negative logic input terminal of AND circuit  17 . The output terminal of subtractor  11   c  is connected to the non-inverted input terminals of comparators  8   d  and  13   g  and the inverted input terminal of comparator  13   h.    
     The output terminal of comparator  8   d  is connected to the other input terminal of EOR circuit  20 . The output terminal of EOR circuit  20  is connected to the other input terminal of OR circuit  23 . The output terminal of OR circuit  23  is connected to the positive logic input terminal of AND circuit  25 . The output terminal of AND circuit  25  is connected to the latch circuit  9   d . Each output terminal of comparators  13   g  and  13   h  is connected to the other two positive logic input terminals of AND circuit  17 , respectively. The output terminal of AND circuit  17  is connected to latch circuit  9   e . The output terminal of latch circuit  9   a - 9   e  are used to output digital output signal  101   a.    
     The inverted input terminals of comparators  8   a - 8   d  are grounded. The voltages of +ΔV is applied to the non-inverted input terminals of comparators  13   b , 13   d , 13   f , and  13   h . The voltages of −ΔV is applied to the inverted input terminals of comparators  13   a , 13   c , 13   e  and  13   g , respectively. However, ΔV=FS/32, wherein FS=full scale. 
     Operation of the device of FIG. 1 will now be described with refference to FIGS. 2 and 3, which show characteristic curves that indicate each output or each input for analog input signal  10   a  from −FS/2 to +FS/2. In FIGS. 2 and 3, lines (a) to (d) show the outputs of comparators  8   a - 8   d ; lines (e) to (h) show the outputs of window comparators  50   a  to  50   d ; lines (i) to (k) show the outputs of EOR circuits  18 - 20 ; and lines (l) to (p) show the inputs to latch circuits  9   a - 9   e , respectively. 
     Comparators  8   a - 8   d  judge the zero crossing of analog input signal  100   a , the output of subtractor  11   a , the output of subtractor  11   b , and the output of subtactor  11   c , respectively. 
     Each of window comparators  50   a - 50   d  outputs a “high level” signal when the input signal is in each vicinity of “zero” and the output of the window comparator at the preceding stage is at a “low level” signal. Hence, window comparator  50   a  outputs a “high level” signal when analog input signal  100   a  is in each vicinity of “zero” as shown in line (e) of FIG.  2 . 
     Window comparator  50   b  can output a “high level” signal when analog input signal  100   a  is in each vicinity of “zero” and “+FS/4” as shown in line (b) of FIG.  2 . However, since the output signal from window comparator  50   a , at the preceding stage is at a “high level” when analog input signal  100   a  is in each vicinity of “zero”, window comparator  50   b  output “high level” signals only in each vicinity of “+FS/4” as shown in line (f) of FIG.  2 . 
     Window comparator  50   c  can output a “high level” signal in seven positions as shown in line (c) of FIG.  2 . However, since the positions where window comparator  50   a  or  50   b  at the previous states outputs a “high level” signal, are rejected, the output of window comparator  50   c  is of the waveform shown in line (g) of FIG.  2 . Similarly, window comparator  50   d  can output a “high level” signal in 15 positions, as shown iin line (d) of FIG.  2 . However, since the positions where window comparator  50   a ,  50   b , or  50   c  at the previous stages outputs a “high level” signal are rejected, the output of window comparator  50   d  is of the waveform shown in line (h) of FIG.  2 . 
     The output signals from EOR circuit  18 - 20  comprise “gray codes” of intermediate bits in digital output signal  101   a ; but, it is known that the output signals generate spike like noise as shown in lines (i)-(k) of FIG.  3 . This is caused because the changes of signals from “high level” to “low level” or from “low level” to “high level” are not steep. Error correction circuit  51  rejects or eliminates the spike like noise as shown in lines (m)-(o) of FIG. 3, by correcting the portions where the spike like noise is generated using the output signals from the window comparators  50   a - 50   d . That is, the spike like noise, shown in lines (i)-(k) of FIG. 3 is eliminated or rejected by masking with the output signal from window comparator  50   a , the output signals from window Comparators  50   a , 50   b , and the output signals from window comparators  50   a ,  50   b , and  50   c , respectively. 
     The output signals from window comparators  50   a - 50   c  act to change to “high level” in a certain region (called “window width”) near the code changing points to establish all the lower codes. Considering the first stage window comparator  50   a , the second bit is forced to a “high level” and the third bit, fourth bit and the least significant bit (LSB) which is the fifth bit are forced to “low level” near the changing point for the most significant bit (MSB). 
     The window widths for establishing each bit are not required to be essentially the same. As shown in line (m) of FIG. 3, the region in which the second bit is changed to “high level” can be up to a half of a full scale. As shown in line (n) of FIG. 3, a region of up to ¼ of the full scale can be allowed for the third bit. The allowable window width becomes narrower as the bit becomes lower and at the least significant bit (LSB) as shown in line (p) of FIG. 3, the upper limit of window width becomes {fraction (1/16)} of the full scale, or 2 LSB. 
     However, since window comparator  50   a  that detects the changing points for MSB propagates its output to the lower bits, the window width must be constant. For example, the window width for making the second bit at a “high level” at the MSB changing point must be the same as the window width for carrying the LSB to a “low level” Accordingly, a problem arises when the window width comes near the noise level with high resolution, namely, that an error is generated in the code of the second bit where the window comparator  50   a  malfunctions due to noise. 
     SUMMARY OF THE INVENTION 
     Accordingly, an object of the invention is to overcome the aforementioned and other deficiencies and disadvantages of the prior art. 
     Another object is to provide a cascade A/D converter which substantially eliminates error generation due to noise. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram depicting a conventional cascade A/D converter. 
     FIG. 2, comprising lines (a)-(h), is a diagram depicting characteristic curves illustrating operation of the device of FIG.  1 . 
     FIG. 3, comprising lines (i)-(p), is a diagram depicting characteristic curves illustrating operation of the device of FIG.  1 . 
     FIG. 4 is a circuit diagram depicting a first illustrative embodiment of the invention. 
     FIG. 5, comprising lines (a)-(g), is a diagram depicting characteristic curves illustrating operation of the embodiment of FIG. 4 
     FIG. 6, comprising lines (h)-(o), is a diagram depicting characteristic curves illustrating operation of the embodiment of FIG.  4 . 
     FIG. 7 is a circuit diagram depicting a second illustrative embodiment of the invention. 
     FIG. 8, comprising lines (a)-(f), is a diagram depicting characteristic curves illustrating operation of the embodiment of FIG.  7 . 
     FIG. 9, comprising lines (g)-(k), is a diagram depicting characteristic curves illustrating operation of the embodiment of FIG.  7 . 
     FIG. 10, comprising lines (l)-(r), is a diagram depicting characteristic curves illustrating operation of the embodiment of FIG.  7 . 
     FIG. 11, comprising lines (s)-(v), is a diagram depicting characteristic curves illustrating operation of the embodiment of FIG.  7 . 
     FIG. 12 is a circuit diagram depicting a third illustrative embodiment of the invention. 
     FIG. 13, comprising lines (a)-(f), is a diagram depicting characteristic curves illustrating operation of the embodiment of FIG.  12 . 
     FIG. 14, comprising lines (g)-(l), is a diagram depicting characteristic curves illustrating operation of the embodiment of FIG.  12 . 
     FIG. 15, comprising lines (m)-(u), is a diagram depicting characteristic curves illustrating operation of the embodiment of FIG.  12 . 
     FIG. 16 is a circuit diagram depicting a fourth illustrative embodiment of the invention. 
     FIG. 17, comprising lines (a) and (b), is a diagram depicting characteristic curves illustrating operation of the embodiment of FIG.  16 . 
     FIG. 18 is a drawing depicting an illustrative window comparator. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     First Illustrative Embodiment 
     FIG. 4 shows a first illustrative embodiment wherein the components and identifying symbols identical to those in FIG. 1 are not discussed hereat for sake of clarity of discussion. The embodiment comprises subtactors  11   d - 11   f ; comparators  13   a - 13   p ; AND circuits  14   a , 15   a , 15   b , 16   a ,  16   b ,  17   a  and  25   a ; amplifiers  60   a - 60   c ; and analog multiplexers  61   a , 61   b . Analog input signal  100   b  and digital output signal  101   b  are used. Comparators  13   i  and  13   j  and AND circuit  14   a  comprise window comparator  50   e . Comparators  13   k  and  13   l  and AND circuit  15   a , 15   b  comprise window comparator  50   f . Comparators  13   m , 13   n  and AND circuits  16   a , 16   b  comprise window comparator  50   g , Comparators  13   o , and  13   p  and AND circuit  17   a  comprise window comparator  50   h . The window comparators  50   e , 50   f ,  50   g  and  50   h  act to detect each vicinity of code changing points. Amplifiers  60   a - 60   c  and analog multiplexer  61   a  and  61   b  comprise waveform composition circuit  60 . 
     The connections of the various components are basically the same as those in FIG. 1 with the following differences. Subtractors  11   d - 11   f  are provided in place of subtractors  11   a - 11   c  and outputs each resulting output signal after amplifying twice the subraction results, respectively. 
     Analog input signal  100   b  is applied to the non-inverted input terminals of comparators  8   a  and  13   i , the inverted input terminal of comparator  13   j , the addition input terminal of subtractor  11   d , and amplifier  60   a . The output terminals of comparators  13   i  and  13   j  are connected to the input terminals of AND circuit  14   a , respectively. The output terminal of AND circuit  14   a  is connected to one input terminal of OR circuit  21 , negative logic input terminal of AND circuits  15   b  and  24 , the selection terminal SB of analog multiplexer  61   a , and one selection terminal SC of analog multiplexer  61   b . The output terminal of amplifier  60   a  is connected to one input terminal eg B of analog multiplexer  61   a.    
     The output terminal of subtractor  11   d  is connected to the non-inverted terminal of comparator  8   b , addition input terminal of subtractor  11   e , and the other input terminal, eg A, of analog multiplexer  61   a . The output terminal of analog multiplexer  61   a  is connected to the non-inverted input terminal of comparator  13   k , the inverted input terminal of comparator  13   l , and amplifiers  60   b  and  60   c , respectively. The output terminal of comparators  13   k  and  13   l  are connected to AND circuit  15   a , respectively. The output terminal of AND circuit  15   a  is connected to the positive logic input terminal of AND circuit  15   b  and the negative logic input terminals of AND circuits  16   b  and  25   a . The output terminal of AND circuit  15   b  is connected to one input terminal of OR circuit  22  and the other selection terminal SB of analog multiplexer  61   b . The output terminal of OR circuit  23  is connected to the positive logic input terminal of AND circuit  25   a . The output terminal of AND circuit  25   a  is connected to latch circuit  9   d . The output terminals of amplifiers  60   b  and  60   c  are connected to the input terminals B,C of analog multiplexer  61   b , respectively. 
     The output terminal of subtractor  11   e  is connected to the non-inverted input terminal of comparator  8   c , the addition input terminal of subtractor  11   f , and the input terminal A of analog multiplexer  61   b . The output terminal of analog multiplexer  61   b  is connected to the noninverted input terminal of comparator  13   m  and the inverted input terminal of comparator  13   n . The output terminals of comparators  13   m  and  13   n  are connected to the input terminals of AND circuit  16   a , respectively. The output terminal of AND circuit  16   a  is connected to the positive logic input terminal of AND circuit  16   b  and the negative logic input terminal of AND circuit  17   a . The output terminal of AND circuit  16   b  is connected to one input terminal of OR circuit  23 . The output terminal of subtractor  11   f  is connected to the non-inverted input terminals of comparators  8   d  and  13   o  and the inverted input terminal of comparator  13   p . The output terminals of comparators  13   o  and  13   p  are connected to the other two positive logic input terminals of AND circuit  17   a , respectively. The output terminal of AND circuit  17   a  is connected to latch circuit  9   e . The output signals from latch circuits  9   a - 9   e  are provided as digital signal  10   b.    
     Voltages of +FS/16, +3FS/32, +FS/8, and +FS/4 are applied to the non-inverted input terminals of comparators  13   j ,  13   l ,  13   n , and  13   p , respectively. Also, voltages of −FS/16, −3FS/32, −FS/8 and −FS/4 are applied to the inverted input terminals of comparators  13   i ,  13   k ,  13   m  and  13   o , respectively. 
     The operation of the embodiment of FIG. 4 will now be described with reference to FIGS. 5 and 6, wherein line (a) shows analog input signal  100   b  from −FS/2 to +FS/2; line (b) shows output of AND circuit  14   a ; line (c) shows the output of subtractor  11   d ; line (d) shows the output of amplifier  60   a ; and line (e) shows the output of analog multiplexer  61   a . Lines (f) and (g) show the outputs of AND circuits  15   a  and  15   b , respectively; line (h) shows the output of subtractor  11   e ; lines (i) and (j) show the outputs of amplifiers  60   b  and  60   c , respectivley; line (k) shows the output of analog multiplexer  61   b ; lines (l) and (m) show the outputs of AND circuits  16   a  and  16   b , respectively; line (n) shows the output of subtractor  11   f ; and line (o) shows the output of AND circuit  17   a.    
     Comparator  8   a  judges the zero crossings of analog input signal  100   b  and outputs the result thereof to latch circuit  9   a , D/A converter  10   a , and EOR circuit  18 . The D/A converter converts the output signal from comparator  8   a  into an analog signal and outputs the resulting signal to subtractor lid. Subtractor lid subtracts the output signal from D/A converter  10   a  from the analog input signal  100   b , and then outputs the resulting output signal obtained by amplifying twice the subtraction result (see “X2” on right of subtractor  11   d - 11   f  in FIG. 4, which represents the amplifying function. 
     As shown in line (b) of FIG. 5, window comparator  50   e  outputs a “high level” signal in window width of FS/8 in each vicinity of “zero” of analog input signal  100   b , as shown in line (a) of FIG.  5 . 
     Comparator  8   b  judges the zero crossing of the output signal from subtractor lid and outputs the judged result to D/A converter  10   b  and EOR circuits  18 , 19 . D/A converter  10   b  converts the output signal from comparator  8   b  into an analog signal and outputs the resulting signal to subtractor  11   e . Subtractor lie subtracts the output signal from D/A converter  10   b  from the output signal form subtractor lid and outputs the resulting output signal obtained by amplifying twice the subtractraction results. 
     Analog multiplexer  61   a  multiplexes the signal obtained by amplifying analog input signal  100   b  by a factor of (−2) with amplifier  60   a  and the output signal from subtactor  11   d . More specifically, analog multiplexer  61   a  selects the output signal from amplifier  60   a  shown in line (d) of FIG. 5 at the interval where the output of window comparator  50   e  (comprising AND circuit  14   a ) is at a “high level”; and selects the output signal from subtractor  11   d  shown in  11   e  (c) of FIG. 5 at the interval where the output signal from window comparator  50   e  is at a “low level”; and creates the code changing waveform shown in line (e) of FIG. 5; and provides an output signal to window comparator  50   f.    
     As shown in line (f) of FIG. 5, window comparator  50   f  outputs “high level” signals in the window width of 3FS/32 in each vicinity of “zero” of the input signal from AND circuit  15   a . As shown in line (g) of FIG. 5, window comparator  50   f  also outputs “high level” signals in the window width of 3FS/32 in each vicinity of “zero” of the input signal from AND circuit  15   b  except the interval where the output signal from window comparator  50   e  is at a “high level”. 
     Comparator  8   c  judges the zero crossing of the output signal from subtractor lie and outputs the judged results to D/A converter  10   c , and EOR circuits  19  and  20 . D/A converter  10   c  converts the output signal from comparator  8   c  into an analog signal and outputs the resulting signal to subtractor  11   f . Subtractor  11   f  subtracts the output signal from D/A converter  10   c  from the output signal from subtractor lie and provides the resulting output signal obtained by amplifying twice the subtraction results. 
     Analog multiplexer  61   b  multiplexes the signals obtained by amplifying the output signal from analog multiplexer  61   a  by factors of (−2) and (+2) with amplifiers  60   b  and  60   c , respectively, and the output signals from subtractor  11   e . More specifically, analog multiplexer  61   b  selects the output signal from amplifier  60   b  shown in line (i) of FIG. 6 at the interval where the output signal from AND circuit  15   b  in window comparator  50   f  is at a “high level”; selects the output signal from amplifier  60   c  shown in line (j) of FIG. 6 at the interval where the output signal from window comparator  50   e  is at a “high level”; selects the output signal from subtractor  11   e  shown in line (h) of FIG. 6 at the interval where both output signals from window comparators  50   e  and  50   f  are at a “low level”; creates the code changing waveform shown in line (k) of FIG. 6; and provides the resulting output signal to window comparator  50   g.    
     As shown in line (l) of FIG. 6, window comparator  50   g  outputs “high level” signals from AND circuit  16   a  in the window width of FS/16 in each vicinity of “zero” of the input signal. As shown in line (m) of FIG. 6, window comparator  50   g  also outputs “high level” signals from AND circuit  16   b  in the window width of FS/16 in each vicinity of “zero” of the input signal except the interval where the output of AND circuit  15   a  in window comparator  50   f  is at a “high level” Comparator  8   d  judges the zero crossing of the outupt signal from subtractor  11   f  and outputs the resulting singal to EOR circuit  20 . 
     As shown in line (o) of FIG. 6, window comparator  50   h , comprising AND circuit  17   a , outputs a “high level” signal in the window width of FS/16 in each vicinity of “zero” of the input signal shown in line (n) of FIG.  6 . Then, similar to the conventional apparatus, EOR circuits  18 - 20  output “gray” codes including the spike like noise of the intermediate bits in the digital output signal  101   b.    
     Error correction circuit  51  eliminates the spike like noise in the “gray” codes by correcting the portions where the spike like noise is generated using the output signals from the window comparators. 
     As discussed above, the code changing waveforms are created to include the code changes at the previous stages in the waveform composition circuit  60 . Thus, the window widths, i.e. the widths detecting each vicinity of code changing points, of window comparators  50   e - 50   h  can, advantageously, be set freely to increase the window widths for the upper bits and, hence, increase accuracy. Advantageously, the voltage accuracy at later stages can be made less restrictive by increasing the gains of subtractors  11   d - 11   f  and amplifiers  60   a - 60 , by factors of two or more. Moreover, advantageously, the circuits are considerably simplified by the invention. 
     Second Illustrative Embodiment 
     In FIG. 7, components and identifying symbols identical to those in FIGS. 1 and 4 are omitted from discussion for sake of clarity. FIG. 7 shows an embodiment comprising comparators  71   a - 71   h  and  72   a - 72   h ; and log-AND circuits  25   a ,  73   a - 73   h ,  74   d , and  74   e . comparators  71   a , 72   a  and AND circuit  73   a  comprise window comparator  70   a . Comparators  71   b , 72   b  and AND circuit  73   b  comprise window comparator  70   b . Comparators  71   c , 72   c  and AND circuit  73   c  comprise comparator  70   c . Comparators  71   d  and  72   d  and AND circuits  73   d  and  74   d  comprise window comparator  70   d . Comparators  71   e  and  72   e  and AND circuits  73   e  and  74   e  comprise window comparator  703 . Comparators  71   f  and  72   f  and AND circuit  73   f  comprise window comparator  70   f . Comparator  71   g  and  72   g  and AND circuit  73   g  comprise window comparator  70   g . Comparators  71   h  and  72   h  and AND circuit  73   h  comprise window comparator  70   h . The window comparators  70   a - 70   h  comprise means for detecting each vicinity of the code changing points. 
     The connections for the components are substantially the same as those in FIG. 1, except for the following differences. Subtractors  11   d - 11   f  are provided in place of subtractors  11   a - 11   c  and provide output signals which are obtained by amplifying by a factor of for example two the subtraction results, respectively. Analog input signal  100   b  is applied to the non-inverted input terminals of comparators  8   a  and  71   a - 71   c , the inverted input terminals of comparators  72   a - 72   c , the addition input terminal of subtractor  11   d , and amplifier  60   a.    
     The output terminals of comparators  71   a  and  72   a  are connected to the input terminals of AND circuit  73   a , respectively. The output terminal of AND circuit  73   a  is connected to one input terminal of OR circuit  21 . The output terminals of comparators  71   b  and  72   b  are connected to the input terminals of AND circuit  73   b , respectively. The output terminal of AND circuit  73   b  is connected to the negative logic input terminals of AND circuits  24 , 74   d  and  74   e , and the selection terminal SB of analog multiplexer  61   a . The output terminal of comparators  71   c  and  72   c  are connected to the input terminals of AND circuit  73   c , respectively. The output terminal of AND circuit  73   c  is connected to one selection terminal, e.g. SC, of analog multiplexer  61   b . The output terminal of amplifier  60   a  is connected to one input terminal, eg B, of analog multiplexer  61   a.    
     The output terminal of subtractor  11   d  is connected to the noninverted input terminal of comparator  8   b , the addition input terminal of subtractor  11   e , and the other input terminal, e.g. A, of analog multiplexer  61   a . The output terminal of analog multiplexer  61   a  is connected to the non-inverted input terminals of comparators  71   d  and  71   e , the inverted input terminals of comparators  72   d  and  72   e , and amplifiers  60   b  and  60   c.    
     The output terminals of comparators  71   d  and  72   d  are connected to the input terminals of AND circuit  73   d , respectively. The output terminal of AND circuit  73   d  is connected to the positive logic input terminal of AND circuit  74   d . The output terminal of AND circuit  74   d  is connected to one input terminal of OR circuit  22 . The output terminals of comparators  71   e  and  72   e  are connected to the input terminals of AND circuit  73   e , respectively. The output terminal of AND circuit  73   e  is connected to the positive logic input terminal of AND circuit  74   e  and the negative logic input terminals of AND circuits  25   a  and  73   f . The output terminal of AND circuit  74   e  is connected to the other selection terminal e.g. SB, of analog multiplexer  61   b . The output terminal of OR circuit is connected to the positive logic input terinal of AND circuit  25   a . The output terminal of AND circuit  25   a  is connected to latch circuit  9   d.    
     The output terminals of amplifiers  60   b  and  60   c  are connected to each input terminal B,C of analog multiplexer  61   b , respectively. The output terminal of subtractor  11   e  is connected to the non-inverted input terminal of comparator  8   c , the addition input terminal of subtractor  11   f , and one input terinal, e.g.  1 A, of analog multiplexer  61   b . The output terminal of analog multiplexer  61   b  is connected to the non-inverted input terminals of comparators  71   f  and  71   g  and to the inverted input terminals of comparators  72   f  and  72   g.    
     The output terminal of comparators  71   f  and  72   f  are connected to each positive logic input terminal of AND circuit  73   f , respectively. The output terminal of AND circuit  73   f  is connected to one input terminal of OR circuit  23 . The output terminal of comparators  71   g  and  72   g  are connected to each input terminal of AND circuit  73   g , respectively. The output terminal of AND circuit  73   g  is connected to the negative logic input terminal of AND circuit  73   h . The output terminal of subtractor  11   f  is connected to the non-inverted input terminals of comparators  8   d  and  71   h  and the inverted input terminal of comparator  72   h . The output terminal of comparators  71   h  and  72   h  are connected to each positive logic input terminal of AND circuit  73   h . The output terminal of AND circuit  73   h  is connected to latch circuit  9   e.    
     The output signals from latch circuits  9   a - 9   e  are provided as digital signals  101   b . Voltages of +FS/4, +FS/8, +FS/16, +FS/4, +FS/8, +FS/4, +FS/8 and +FS/4 are applied to the non-inverted input terminals of comparators  72   a - 72   h , respectively. Also, voltages of −FS/4, −FS/8, −FS/16, −FS/4, −FS/8, −FS/4, −FS/8, and −FS/4 are applied to the inverted input terminals of comparators  71   a - 71   h , respectively. 
     The operation of the embodiment of FIG. 7, will now be described with reference to FIGS. 8-11, wherein in FIG. 8, line (a)shows analog input signal  100   b  from −FS/2 to +FS/2, line (b) shows the output of comparator  8   a , line (c) shows the output of subtractor  11   d , line (d) shows the output fo comparator  8   b , line (e) shows the output of subtractor  11   e , and line (f) shows the output of comparator  8   c ; in FIG. 9, dline (g) shows the output of subtractor  11   f , line (h) shows the output of comparator  8   d , and liens (i)-(k) show the outputs of AND circuits  73   a - 73   c , resepctively; in FIG. 10, line (l) shows the output of analog multiplexer  61   a , lines (m) and (o) show the outputs of AND circuits  74   d ,  73   e  and  74   e , respectively, line (p) show the output of analog multiplexer  61   b , and lines (q)-(r) show the outputs of AND circuits  73   f  and 73   g ; and in FIG. 11, line (s) shows the output of AND circuit  73   h , line (t) shows the output of OR circuit  21 , and lines (u) and (v) show the outputs of AND circuits  24  and  25   a , respectively. 
     Comparator  82  judges the zero crossing of analog input signal lOOb and supplies the judged result to latch circuit  9   a , D/A converter  10   a , and EOR circuit  18 . D/A converter  10   a  converts the output signal from comparator  8   a  into an analog signal and outputs the resulting signal to subtractor  11   d . Subtractor  11   d  subtracts the ouput signal from D/A converter  10   a  from analog input signal  100   b  and provides the resulting output signal obtained by multiplying, by a factor for example of two, the subtraction results. 
     As shown in line (i) of FIG. 9, window comparator  70   a  outputs a “high level” signal in the window width of FS/2 in each vicinity of “zero” of analog input signal  100   b  shown in line (a) of FIG.  8 . The output signal from AND circuit  73   a  is used for rejecting spike like noise in the second bit from the MSB. As shown in line (j) of FIG. 9, window comparator  70   b  outputs a “high level” signal in the window width of FS/4 in each vicinity of “zero” of analog input signal lOOb shown in line (a) of FIG.  8 . The output signal from AND circuit  73   b  is used for rejecting spike like noise in the third bit from the MSB. As shown in line (k) of FIG. 9, window comparator  70   c  outputs a “high level” signal in the window width of FS/8 in each vicinity of “zero” of analog input signal  100   b  shown in line (a) of FIG.  8 . 
     Comparator  8   b  judges the zero crossing of the output signal from subtractor  11   d  and supplies the resulting output signal to D/A converter  10   b  and EOR circuits  18  and  19 . D/A converter  10   b  converts the output signal from comparator  8   b  into an analog signal and then supplies the analog signal to the subtractor  11   e . Subtractor  11   e  subtracts the output signal from the D/A converter from the outut signal from subtractor  11   d  and provides the resulting output signal obtained by amplifying by a factor for example of two the subtraction result. Analog multiplexer  61   a  multiplexes the signal obtained by amplifying analog input signal  100   b  by a factor of (−2) with amplifier  60   a  and the output signal from the subtractor lid. More specifically, analog multiplexer  61   a  selects the output signal from amplifier  60   a  at the interval where the output signal from window comparator  70   b , comprising AND circuit  73   b , is at a “high level”; selects the output signal from subtractor lid, shown in line (c) of FIG. 8, at the interval where the output signal from window comparator  70   b  is at a “low level”; creates the code changing waveform shown in line (l) of FIG. 10; and supplies the output signal to window comparators  70   d  and  70   e . Window comparator  70   d  outputs a “high level” signal from AND circuit  73   e  in the window width of FS/4 in each vicinity of “zero” of the input signal. That is, as shown in line (l) of FIG. 10, the “high level” signal is obtained in the window width from −3FS/8 to +3FS/8. As shown in line (m) of FIG.  10 ,AND circuit  74   d  outputs “high level” signals in the window width of FS/4 in each vicinity of “zero” of the input signal except the interval where the output of window comparator  70   b  is at a “high level”. The output signal from AND circuit  74   d  is used to eliminate the spike like noise in the third bit from the MSB. 
     As shown in line (n) of FIG. 10, window comparator  70   e  outputs a “high level” signal from the AND circuit  73   e  in the window width of FS/8 in each vicinity of “zero” of the input signal. As shown in line (o) of FIG. 10, AND circuit  74   e  outputs “high level” signals in the window width of FS/8 in each vicinity of “zero” of the input signal except the interval where the outut signal from window comparator  70   b  is at a “high level”. The output signal form AND circuit  73   e  is used to eliminate the spike like noise in the fourth bit from the MSB. 
     Comparator  8   c  judges the zero crossing of the output signal from subtractor lie and provides the judged result to D/A converter  10   c  and EOR circuits  19  and  20 . D/A converter converts the output signal from comparator  8   c  into an analog signal and supplies the analog signal to subtractor  11   f . Subtractor  11   f  subtracts the output signal from D/A converter  10   c  from the output signal from subtractor lie and supplies the resulting output signal obtained by amplifying by a factor for example of two the subtraction result. 
     Analog multiplexer  61   b  multiplexes the signals obtained by amplifying the output signal from analog multiplexer  61   a  by factors of (−2) and (+2), respectively, with amplifiers  60   b  and  60   c , and the output signal from subtractor lie. More specfically, analog multiplexer  61   b  selects the output signal from amplifier  60   b  at the interval where the output signal from AND circuit  74   e  of window comparator  70   e  is at a “high level”; selects the output signal from amplifier  60   c  at the interval where the output signal form window comparator  70   c  is at a “high level”; selects the output signal from subractor lie shown in line (e) of FIG. 8 at the interval where both of the window comparator output signals are at a “low level”; then creates the code changing waveform shown in line (p) of FIG. 10, and provides the resulting output signal to the input terminal of window comparators  70   f  and  70   g.    
     As shown in line (q) of FIG. 10, window comparator  70   f  outputs “high level” signals from AND circuit  73   f  in the window width of FS/8 in each vicinity of “zero” of the input signal except the interval where the output signal from AND circuit  73   e  of window comparator  70   e  is at a “high level”. The output signal from AND circuit  73   f  is used to eliminate the spike like noise in the fourth bit from the MSB. As shown in line (r) of FIG. 10, window comparator  70   g  outputs “high level” signals from AND cirucit  73   g  in the window width of FS/16 in each vicinity of “zero” of the input signal. The output signal from AND circuit  73   g  is used for eliminating noise in the LSB. 
     Comparator  8   d  judges the zero crossing of the output signal from subtractor  11   f  and supplies the results to EOR circuit  20 . The output signal from window comparator  70   h , which comprises AND circuit  73   h , can become “high level” in 15 positions, as shown in line (g) of FIG.  9 . However, sine the portions where the output signal from window comparator  70   g  is at a “high livel” are except from the 15 positions, the output signal from AND circuit  73   h  is as shown in line (s) of FIG.  11 . 
     Similar to the conventional devices, the output signal from EOR circuit  18 - 20  are “gray” codes having spike like noise of the intermediate bits within the digital output signal  101   b . Error correction circuit  51  corrects the portions where the spike like noise is generated with the output signals from the window comparators to eliminate the spike like noise in “gray” codes. In other words, the spike like noise shown in line (i) of FIG. 3 is eliminated by masking the spike like noise with the output signal from the window comparator  70   a . The spike like noise shown in line (j) of FIG. 3 is eliminated by being masked by the output signal from window comparators  70   b  and  70   d . The spike like noise shown in line (k) of FIG. 3 can be eliminated by masking with the output signals from window comparators  70   e  and  70   f , respectively. 
     As described above , with the embodiment the code changing waveforms are created including the code changes in the previous stages with waveform composition circuit  60 . Thus, advantageously, the window widths i.e. widths for detecting each vicinity of code changing points, of window comparators  70   a - 70   h  can be set freely and wider window widths can be obtained for the upper bits. Hence, advantageously, effects due to noise are reduced and accuracy is increased. 
     In addition, advantageously, since window comparators  70   a - 70   g , whose window widths are different in each stage, are provided, the window widths for eliminating noise can be made as large as possible with respect to all of the bits. That is, advantageously, effects due to noise are reduced and accuracy is increased. Moreover, advantageously, voltage accuracy at later stages is made less restrictive by increasing, by a factor of two or more, the gains of the subtractors  11   d - 11   f  and amplifiers  60   a - 60   c ; and the circuit configuration is simplified. The analog multiplexer may also include amplifier functions. 
     Third Illustrative Embodiment 
     In FIG. 12, the components and identifying symbols identical to those shown in FIG. 1 are not described hereat for sake of clarity. The embodiment comprises comparators  8   e - 8   h ; D/A converters  10   d - 10   f ; comparators  13   i - 13   p ; AND circuits  14   a , 15   a , 15   b ,  16   a ,  16   b ,  17   a , and  25   a ; and analog multiplexers  62 , 63 . An analog input signal  100   b  and digital output signal  101   b  are provided. 
     Comparators  13   i ,  13   j  and AND circuit  14   a  comprise window comparator  50   e . Comparators  13   k ,  13   l  and AND circuits  15   a , 15   b  comprise window comparator  50   f . Comparators  13   m  and  13   n  and AND circuits  16   a  and  16   b  comprise comparator  50   g . Comparators  13   o  and  13   p  and AND circuit  17   a  comprise window comparator  50   h . The window comparators  50   e - 50   h  comprise means for detecting each vicinity of code changing points. Analog multiplexers  62  and  63  comprise waveform composition circuit  61 . 
     The connections between the components which differ from those of FIG. 1 are described below. Analog input signal  100   b  is applied to the non-inverted input terminals of comparators  8   e - 8   h , respectively. The positive logic output terminal of comparator  8   e  is connected to latch circuit  9   a , D/A converter  10   d , the non-inverted input terminal of comparator  13   i , the inverted input terminal of comparator  13   j , and one input terminal of EOR circuit  18 . The negative logic output terminal of comparator  8   e  is connected to one input terminal, e.g. B, of analog multiplexer  62 . The output terminal of D/A converter  10   d  is connected to the inverted input terminal of comparator  8   f  and one input terminal of adder  11   g . In addition, each output terminal of comparators  13   i  and  13   j  is connected to the input terminals of AND circuit  14   a , respectively. The output terminal of AND circuit  14   a  is connected to one input terminal of OR circuit  21 , the negative logic input terminal of AND circuits  15   b  and  24 , the selection terminal SB of analog multiplexer  62  and one selection terminal, e.g. SC, of analog multiplexer  63 . 
     The output terminal of comparator  8   f  is connected to D/A converter  10   e , the other input terminal of EOR circuit  18 , one input terminal of EOR circuit  19 , and the other input terminal , e.g. A, of analog multiplexer  62 . The positive logic output terminal of analog multiplexer  62  is connected to the non-inverted input terminal of comparator  13   k , the inverted input terminal of comparator  13   l , and one input terminal, e.g. C, of analog multiplexer  63 . The negative logic output terminal of analog multiplexer  62  is connected to the second input terminal e.g. B, of analog multiplexer  63 . In addition, each output terminal of comparators  13   k  and  13   l  is connected to AND circuit  15   a , respectively. The output terminal of AND circuit  15   a  is connected to the positive logic input terminal of AND circuit  15   b  and to the negative logic input terminals of AND circuits  16   b  and  25   a . The output terminal of AND circuit  15   b  is connected to one input terminal of OR circuit  22  and the other selection terminal, e.g. SB, of analog multiplexer  63 . The output terminal of OR circuit  23  is connected to the positive logic input terminal of AND circuit  25   a . The output terminal of AND circuit  25   a  is connected to latch circuit  9   d.    
     The output terminal of D/A converter  10   e  is connected to the other input terminal of adder  11   g . The output terminal of adder  11   g  is connected to the inverted input terminal of comparator  8   g  and one input terminal of adder  11   h . The output terminal of comparator  8   g  is connected to D/A converter  10   f , the other input terminal of EOR circuit  19 , one input terminal of EOR circuit  20 , and the third input terminal, e.g. A, of analog multiplexer  63 . The output terminal of analog multiplexer  63  is connected to the non-inverted input terminal of comparator  13   m  and the inverted input terminal of comparator  13   n . Each output terminal of comparators  13   m  and  13   n  is connected to the input terminals of AND circuits  16   a , respectively. The output terminal of AND circuit  16   a  is connected to the positive logic input terminal of AND circuit  16   b  and the negative logic input terminal of AND circuit  17   a . The output terminal of AND circuit  16   b  is connected to one input terminal of OR circuit  23 . 
     The output terminal of D/A converter  10   f  is connected to the other input terminal of adder  11   h . The output terminal of adder  11   h  is connected to the inverted input terminal of comparator  8   h . The output terminal of comparator  8   h  is connected to the non-inverted input terminal of comparator  13   o , the inverted input terminal of comparator  13   p , and the other input terminal of EOR circuit  20 . Each outputterminal of comparators  13   o  and  13   p  is connected to the other two positive logic input terminals of AND circuit  17   a , respectively. The output terminal of AND circuit  17   a  is connected to latch circuit  9   e . Furthermore, the output signals from latch circuits  9   a - 9   e  are provided as digital output signal  101   b . The inverted input terminal of comparator  8   e  is grounded. 
     Voltages of +V1, +V2, +V3, and +V4 are applied to the non-inverted input terminals of comparators  13   j ,  13   l ,  13   n , and  13   p , respectively. Voltages of −V, −V2, −V3, and −V4 are applied to the inverted input terminals of comparators  13   i ,  13   k ,  13   m  and  13   o , respectively. Voltage V1 is selected to be of a value with which the window width of window comparator  50   e  becomes FS/8 at the differential operation interval of comparator  8   e . Voltage V2 is selected to be of a value with which the window width of window comparator  50   f  becomes 3FS/32 at the differential operation interval of comparators  8   e  and  8   f . Voltage V3 is selected to be of a value with which the window width of window comparator  50   g  becomes FS/16 at the differential operation interval of comparators  8   e - 8   g . Voltage V4 is selected to be of a value with which the window width of window comparator  50   h  becomes FS/16 at the differential operation interval of comparator  8   h.    
     The operation of the embodiment of FIG. 12 will now be described with reference to FIGS.  13 - 15 ,wherein in FIG. 13, line (a) shows analog input signal  100   b  of −FS/2 to +FS/2, line (b) shows the output of comparator  8   e , line (c) shows the output of D/A converter  10   d , line (d) shows the output of comparator  8   f , line (e) shows the output of D/A converter  10   e , and line (f) shows the output of adder  11   g ; in FIG. 14, line (g) shows the output of comparator  8   g , line (h) shows the output of D/A converter  10   f , line (i) shows the output of adder  11   h , line (j) shows the output of comparator  8   h , line (k) shows the output of AND circuit  14   a , and line (l) shows the positive logic output of analog multiplexer  62 ; and in FIG. 15, line (m) and line (n) show the outputs of AND circuits  15   a  and  15   b , respectively, line (o) shows the output of analog multliplexer  63 , lines (p)-(r) show the outputs of AND circuits  16   a ,  16   b , and  17   a , respectively, and lines (s)-(u) show each input of latch circuits  9   b  to  9   d , respectively. 
     Comparator  8   e  compares the analog input signal  100   b , shown in line (a) of FIG. 13, with the zero point and provides differential amplification as shown in line (b) of FIG.  13 . In this case, a comparator having less gain than comparator  8   a  of the conventional device is used as comparator  8   e . Comparator  8   e  provides positive logic output signal to latch circuit  9   a , D/A converter  10   d , comparators  13   i  and  13   j  and EOR circuit  18 , and negative logic output signal to analog multiplexer  62 . D/A converter  10   d  converts the positive logic output signal from comparator  8   e  into an analog signal, as shown in line (c) of FIG.  13  and provides the analog signal to comparator  8   f.    
     As shown in line (k) of FIG. 14, window comparator  50   e  outputs a “high level” signal in the window width of FS/8 in each vicinity of “zero” of the output signal from comparator  8   e  as shown in line (b) of FIG.  13 . Comparator  8   f  compares analog input signal  100   b  with the output signal from the D/A converter  10   d  and provides differential amplification, as shown in line (d) of FIG.  13 . In addition, a comparator, whose gain is smaller than that of a comparator used in conventioal devices, is used as comparator  8   f . The output siganl from comparator  8   f  is provided to D/A converter  10   e , EOR circuit  18  and  19  and analog multiplexer  62 . 
     As shown in line (e) of FIG. 13, D/A converter  10   e  converts the output signal from comparator  8   f  into an analog signal and provides the resulting signal to adder  11   g . AS shown in line (f) of FIG. 13, adder  11   g  adds the output signal from D/A converter  10   d  to the output signal from D/A converter  10   e  and provides the results of the addition to comparator  8   g  and adder  11   h.    
     Analog multiplexer  62  multiplexes the output signals from comparators  8   e  and  8   f . More specifically, analog multiplexer  62  selects the output signal from comparator  8   e , shown in line (b) of FIG. 13, at the interval where the output signal from window comparator  50   e , comprising AND circuit  14   a , is at a “high level”; selects the output signal from comparator  8   f , shown in line (d) of FIG. 13, at the interval where the window comparator output signal is at a “low level”; and creates the code changing waveform shown in line (l) of FIG.  14 . This code changing waveform is applied to window comparator  50   f  and analog multiplexer  63  and the inverted output signal of the code changing waveform is also applied to analog multiplexer  63 . 
     As shown in line (m) of FIG. 15, window comparator  50   f  outputs “high level” signals from AND circuit  15   a  in the window width of 3FS/32 in each vicinity of “zero” of the input signal. As shown in line (n) of FIG. 15, window comparator  50   f  outputs “high level” signals from AND circuit  15   b  in the window width of 3FS/32 in each vicinity of “zero” of the input signal, except the interval where the output signal from window comparator  50   e  is at a “high level”. 
     Comparator  8   g  compares analog input signal  100   b  with the output signal from the adder  11   g  and provides differential amplification, as shown in line (g) of FIG.  14 . Also, a comparator whose gain is smaller than that of the comparator used in the conventional devices is used as comparator  8   g . The output signal from comparator  8   g  is applied to D/A converter  10   f , EOR circuits  19  and  20 , and analog multiplexer  63 . 
     As shown in line (h) of FIG. 14, D/A converter  10   f  converts the output signal from comparator  8   g  into an analog signal and provides this analog signal to adder  11   h . As shown in line (i) of FIG. 14, adder  11   h  add the output signal from D/A converter  10   f  to the output signal from adder  11   g  and provides the results of the addition to comparator  8   h.    
     Analog multiplexer  63  multiplexes the output signal from analog multiplexer  62  and the output signal from comparator  8   g . More specifically, analog multiplexer  63  selects the inverted output signal from the analog multiplexer  62  at the interval where the output signal from AND circuit  15   a  in window comparator  50   f  is at a “high level”; selects the output signal from analog multiplexer  62 , as shown in line (l) of FIG. 14 at the interval where the output signal from window comparator  50   e  is at a “high level”; selects the output signal from comparator  8   g , shown in line (g) of FIG. 14 at the interval where both of the window comparator output signals are at a “low level”; creates the code changing waveform shown in line (o) of FIG. 15; and provides the resulting output signals to window comparator  50   g.    
     As shown in line (p) of FIG. 15, window comparator  50   g  outputs “high level” signals from AND circuit  16   a  in the window width of FS/16 in each vicinity of “zero” of the input signal. As shown in line (q) of FIG. 15, window comparator  50   g  outputs “high level” signals from AND circuit  16   b  in the window width of FS/16 in each vicinity of “zero” of the input signal, except the intervals where the output signals from AND circuit  15   a  in window comparator  50   f  is at a “hgih level”. 
     As shown in line (j) of FIG. 14, Comparator  8   h  compares analog input signal  100   b  with the output signal from adder  11   h  and provides differential amplification. In addition, a comparator whose gain is smaller than that used in conventional devices is used for comparator  8   h . The output signal from comparator  8   h  is provided to AND circuits  13   o  and  13   p  and EOR circuit  20 . 
     As shown in line (r) of FIG. 15, window comparator  50   h  outputs “high level” signals in the window width of FS/16 in each vicinity of “zero” of the input signal shown in line (j) of FIG.  14 . except “high level” intervals of the output signal from AND circuit  16   a  in window comparator  50   g.    
     Then, similar to conventional devices, the output signal from EOR circuits  18 - 20  comprise “gray” codes having spike like noise of intermediate bits within the digital output signal  101   b . Error correction circuit  51  corrects the portions where the spike like noise is generated using the output signal from window comparators to eliminate spike like noise in “gray” codes. 
     As described above, code changing waveforms are created including the code changes in the previous stages using waveform composition circuit  61 . Thus, advantageously, window widths, that is the widths used for detecting each vicinity of code changing points, of window comparators  50   e - 50   h  can be set freely and wider window widths can be used for the upper bits. That is, advantageously, effects due to noise are reduced and accuracy increased. Moreover, advantageously, since the analog input signal  100   b  is applied directly to comparators  8   e - 8   h , operation of subtracting the output signal from D/A converter from analog signals becomes unnecessary and hence settling is improved. Also, advantageously, subtractors are unnecessary. This reduces the scale of the circuitry and power consumption. Although adders to add output signals from the D/A converters may be used, a very simple configuration of such adders can be used with the addition performed by current addition using appropriate circuit connections only. 
     Fourth Illustrative Embodiment 
     In FIG. 16, the components and identifying symbols identical to those shown in FIG. 1 will not be described hereat for sake of clarity. The embodiment comprises comparators  521 - 524 ; AND circuits  525  and  526 ; with provision of analog input signal  10   b  and digital output signal  101   b . Window comparator  52   a  comprises comparators  521  and  522  and AND circuit  525 . Window comparator  52   b  comprises comparators  523  and  524  and AND circuit  625 . Window comparators  52   a  and  52   b  comprise means for detecting each vicinity of code changing points. 
     The connections of components are similar to those of the prior embodiments, except for the following differences. 
     Analog input signal  100   b  is applied to the non-inverted input terminals of comparators  8   a , 13   a , and  521 , the inverted input terminal of comparators  13   b  and  522 , and the addition input terminal of subtractor  11   a.    
     Each output terminal of comparators  521  and  522  is connected to the input termnals of AND circuits  525 , respectively. The output terminal of AND circuit  525  is connected to one input terminal of OR circuit  21 , and negative logic input terminals of AND circuits  15  and  526 , in place of AND circuit  14  in the conventional device. The output terminal of AND circuit  14  is connected to the negative logic input terminals of AND circuits  16  and  17 . The output terminal of subtractor  11   a  is connected to the non-inverted input terminal of comparator  523  and the inverted input terminal of comparator  524 . Each output terminal of comparators  523  and  524  is connected to the input terminals of AND circuit  526 , respectively. The output terminal of AND circuit  526  is connected to one input terminal of OR circuit  22 , in place of AND circuit in the conventional device. The output terminal of AND circuit  15  is connected to the negative logic input terminals of AND circuits  16 ,  17  and  25 . The output signals generated by latch circuits  9   a - 9   e  are outputted as a digital output signal  101   b.    
     A voltage of +3FS/32 is applied to the non-inverted input terminals of comparators  522  and  524 . A voltage of −3FS/32 is applied to the inverted input terminals of comparators  521  and  523 . 
     Operation of the embodiment of FIG. 16 will now be described with reference to FIGS. 17,  2  and  3 . The characteristic curves for the embodiment are similar to those shown in FIGS. 2 and 3, except that in line (a) of FIG. 2 shows analog input signal  10   b . In FIG. 17, line (a) shows the output signal from AND circuit  525 , line (b) shows the output signal from AND circuit  526 . 
     Each of comparators  8   a - 8   d  judges the zero crossing of the analog input signal  10   b , of the output signal from subtractor  11   a , of the output signal from subtractor  11   b , and of the output signal from subtractor  11   c , respectively. Window comparator  50   a  outputs “high level” signals in the window width of FS/16 in each vicinity of “zero” of analog input signal  10   b , as shown in line (e) of FIG.  2 . AND circuit  525  in window comparator  52   a  outputs “high level” signals in the window width of 3FS/16 in each vicinity of “zero” of analog input signal  100   b  as shown in line (a) of FIG.  17 . 
     As shown in line (b) of FIG. 2, window comparator  50   b  can output “high level” signals in the window width of FS/16 in each vicinity of “zero” of analog input signal  100   b . However, since the output signal from comparator  52   a  in the preceding stage in the vicinity of “zero” of analog input signal  100   b  is at a “high level”, the output signal from window comparator  50   b  is at a “high level” only in each vicinity of “±FS/4”, as shown in line (f) of FIG.  2 . 
     As shown in line (b) of FIG. 2, window comparator  52   b  comprising ADN circuit  526  can output “high level” signals in the window width of 3FS/16 in each vicinity of “zero” and “±FS/4” of analog input signal  100   b . However, since the output signal from comparator  52   a  in the preceding stage in each vicinity of “zero” of the analog input signal  100   b , is at a “high level”, the output signal from the window comparator  52   b  is at a “high level” only in each vicinity of “±FS/4”, as shown in line (b) of FIG.  17 . 
     As shown in line (c) of FIG. 2, window comparator  50   c  can output signals of “high level” in  15  positions. However, since the portions where the output signal for window comparators  50   a - 50   c  in previous stages are at a “high level” are excepted, the output signal from window comparator  50   d  becomes of “high level” in eight positions of window width of FS/16, as shown in line (h) of FIG.  2 . 
     The output signals from EOR circuits  18 - 20  compare “gray” codes of intermediate bits in digital signal  101   b  and produce spike like noise as shown in lines (i)-(k) of FIG.  3 . This is caused by changes from “high level” to “low level” or from “low level” to “high level” in the output signal from comparators  8   a - 8   d , which are not steep. Error correction circuit  51  eliminates the spike like noise, as shown in lines (m)-(o) of FIG. by correcting the portions where the spike like noise is generated using the output signal from window comparators to mask the spike like noises. That is, the spike like noise, shown in lines (i)-(k) of FIG. 3 is eliminated by masking with the output signal from comparator  52   a , the output signals from window comparators  52   a  and  52   b , and the output signals from window comparators  50   a , 50   b , and  50   c , respectively. 
     Advantageously, since the code changes are detected using the window widths in two stages using the window comparators  50   a , 50   b ,  52   a  and  52   b , error elimination or rejection by the error correction circuit  51  can be done selectively for the different bits. That is, advantageously, effects due to noise are reduced or completely eliminated and accuracy is increased substantially by taking wider window widths, for example, in the upper bits. 
     Moreover, the invention attains the advantage of being applicable to cascade A/D converters that provide binary codes; but, the invention is not so limited and may also provide “gray” codes. Also, advantageously, the invention is not limited by the number of output bits. Moreover, the same effects are attainable when the gains of the subtractors  11   d - 11   f  and amplifiers  60   a - 60   c  are larger than a factor of one and not limited to a factor of two. Also, advantageously, configurations may be used wherein amplifying function may be used in the analog multiplexers. Moreover, the window comparators  50   a    50   h ,  52   a ,  52   b , and  70   a - 70   h  which are used as means for detecting each vicinity of code changing points may comprise the circuitry shown in FIG.  18 . 
     In FIG. 18, the window comparator comprises absolute value circuit  12  and comparator  13 . Taking the device shown in FIG. 4 as an example, absolute value circuit  12  provides an absolute value when analog input signal  100   b  is inputted thereinto, together with the output signal from analog multiplexer  61   a , the output signal from analog multiplexer  61   b , or the output signal from subtractor  11   f.    
     In comparator  13 , the output signal from absolute value circuit  12  is applied to the positive logic input terminal thereof and +ΔV(+FS/16, +FS/32, +FS/8 or +FS/4) is applied to the negative logic input terminal. The output signal from comparator  13  becomes the output signal from AND circuit  14   a , the output signal from AND circuit  15   a , the output signal from AND circuit  16 , or the input signal applied to the two positive logic input terminals of AND circuit  17   a . The means for detecting each vicinity of code changing points uses two or three stages of window widths. However, four or more stages may also be used. 
     The foregoing description is illustrative of the principles of the invention. Numerous modifications and extensions thereof would be apparent to the worker skilled in the art. All such extensions and modifications are to be construed to be within the spirit and scope of the invention.