Abstract:
In a digital delay-locked loop circuit, a variable delay circuit for delaying an input signal and generating an output signal includes a first variable delay circuit for delaying the input signal with a first delay time changed at first intervals and a second variable delay circuit for delaying the input signal with a second delay time changed at second intervals smaller than the first intervals. A phase comparator compares the phase of a feedback signal derived from the output signal with the phase of said reference signal. A counter circuit controls the first and second delay times in accordance with a difference in phase between the feedback signal and the reference signal so that the difference in phase is brought close to zero.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a digital delay-locked loop (DLL) circuit. 
     2. Description of the Related Art 
     A prior art digital DDL circuit is constructed by a variable delay circuit formed by an inverter chain for delaying an input signal to generate an output signal, a phase comparator for comparing the phase of a feedback signal with the phase of a reference signal, and a ring counter for adjusting the delay time of the delay circuit. Thus, the delay time of the delay circuit is controlled in accordance with the output of the phase comparator, so that the difference in phase between the feedback signal and the reference signal is brought close to zero. This will be explained later in detail. 
     In the above-described prior art digital DDL circuit however, since the accuracy of the delay time of the variable delay circuit is determined by the value defined by two inverters of the inverter chain, it is impossible to carry out a more fine delay time control, which increases jitter in the output signal. 
     Also, if the accuracy of the delay time of the variable delay circuit is improved by dereasing the delay time of each inverter, it will take a longer locking time. 
     Therefore, in the prior art digital DDL circuit, the decrease of jitter has a trade-off relationship to the decrease of the locking time. 
     Further, in order to enlarge the range of the delay time of the variable delay circuit, if the inverter chain is lengthened, a selector for selecting the inverter chain is also increased in size, which increases the delay time of the selector. As a result, the minimum delay time of the variable delay circuit is increased. Further, the longer inverter chain will take a longer locking time. 
     Additionally, if the difference in phase between the feedback signal and the reference signal is smaller than − 180  ° or larger than +180°, it is impossible to correctly lock the feedback signal to the reference signal. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a digital DDL circuit capable of decreasing jitter as well as decreasing the locking time. 
     Another object is to correctly lock a feedback signal to a reference signal even if the difference in phase is large. 
     According to the present invention, in a digital delay-locked loop circuit, a variable delay circuit for delaying an input signal and generating an output signal includes a first variable delay circuit for delaying the input signal with a first delay time changed at first intervals and a second variable delay circuit for delaying the input signal with a second delay time changed at second intervals smaller than the first intervals. A phase comparator compares the phase of a feedback signal derived from the output signal with the phase of the reference signal. A counter circuit controls the first and second delay times in accordance with a difference in phase between the feedback signal and the reference signal so that the difference in phase is brought close to zero. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be more clearly understood from the description as set forth below, as compared with the prior art, with reference to the accompanying drawings, wherein: 
     FIG. 1 is a block circuit diagram illustrating a prior art digital DDL circuit; 
     FIG. 2 is a detailed circuit diagram of the delay circuit of FIG. 1; 
     FIG. 3 is a table showing the output of the ring counter of FIG. 1; 
     FIGS. 4A and 4D are timing diagrams showing examples of the reference signal and the feedback signal of FIG. 1; 
     FIGS. 5A and 5B are timing diagrams showing other examples of the reference signal and the feedback signal of FIG. 1; 
     FIG. 6 Is a block circuit diagram illustrating an embodiment of the digital DDL circuit according to the present invention; 
     FIGS. 7A and 7B are tables showing the output of the ring counters of FIG. 6; 
     FIG. 8 is a detailed circuit diagram of the coarse variable delay circuit of FIG. 6; 
     FIG. 9 is a graph showing the delay time of the coarse variable delay circuit of FIG. 7; 
     FIG. 10 is a detailed circuit diagram of the fine variable delay circuit of FIG. 6; 
     FIG. 11 is a graph showing the delay time of the fine variable delay circuit of FIG. 10; 
     FIG. 12 is a graph showing the delay time of the variable delay circuit of FIG. 6; 
     FIG. 13 is a detailed circuit diagram of the phase comparator of FIG. 6; 
     FIGS. 14A through 14P are timing diagrams showing the operation of the phase comparator of FIG. 13; 
     FIG. 15 is a circuit diagram illustrating a modification of the phase comparator of FIG. 13; and 
     FIG. 16 is a block circuit diagram illustrating of the variable delay circuit of FIG.  6 . 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Before the description of the preferred embodiment, a prior art digital DDL circuit will be explained with reference to FIGS. 1,  2  and  3 . 
     In FIG. 1, a variable delay circuit  101  delays an input signal IN to generate an output signal OUT. Also, a phase comparator compares the phase of a feedback signal FB which is in this case the output signal OUT with the phase of a reference signal REF. An output of the phase comparator  102  is supplied to a ring counter  103  for adjusting a delay time T of the delay circuit  101 . Thus, the delay time T of the delay circuit is controlled in accordance with the output of the phase comparator  102 , so that the difference in phase between the feedback signal FB and the reference signal REL is brought close to zero. 
     As illustrated in FIG. 2, the variable delay circuit  101  is constructed by an inverter chain formed by inverters  1011 ,  1011 ′,  1012 ,  1012 ′, . . .  101   n− 1,  101   n− 1′, and a selector  1010 . In this case, two of the inverters such as  1011  and  1011 ′ form a delay element having a delay time T d . Therefore, the selector  1010  is operated by the output of the ring counter  103  to select one of nodes N 0 , N 1 , . . . , N n−1  as an output so that the delay time T of the variable delay circuit  101  is 0, T d , 2T d , . . . , or (n−1)T d . 
     Returning to FIG. 1, the phase comparator  102  is constructed by a D-type flip-flop which has a clock input for receiving the reference signal REF and a data input for receiving the feedback signal FB. As a result, when the phase of the feedback signal FB advances the phase of the reference signal REF, the output Q of the D-type flip-flop becomes “1”. On the other hand, when the feedback signal FB retards the phase of the reference signal REP, the output Q of the D-type flip-flop output becomes “0”. 
     The ring counter  103  is an up/down n-ary ring counter with a decoding function. Therefore, when the output Q of the D-type flip-flop is “1”, the state of the ring counter  103  is changed from state “0” via state “1”, state “2”, . . . , to state “n−1” as shown in FIG.  3 . On the other hand, when the output Q of the D-type flip-flop is “0”, the state of the ring counter  103  is from state “n−1” via state “n−2”, state “n−3”, . . . , to state “0” as shown in FIG.  3 . 
     In the digital DDL circuit of FIG. 1, since the accuracy of the delay time T of the variable delay circuit  101  is determined by the value T d  defined by two inverters it is impossible to carry out a more fine delay time control than that determined by the value T d , which increases jitter in the output signal OUT. 
     Also, if the accuracy of the delay time T of the variable delay circuit  101  is improved by dereasing the value T d , it will take a longer locking time. 
     Therefore, in the digital DDL circuit of FIG. 1, the decrease of jitter has a trade-off relationship to the decrease of the locking time. 
     Further, in order to enlarge the range of the delay time T of the variable delay circuit  101 , if the inverter chain is lengthened, the selector  1010  is also increased in size, which increases the delay time of the selector  1010 . As a result, the minimum delay time of the variable delay circuit  101  is increased. Further, the longer inverter chain will take a longer locking time. 
     Additionally, as shown in FIGS. 4A and 4B, if the difference in phase between the feedback signal FB and the reference signal REP is within a range from −180° to +180°, it is possible to correctly lock the feedback signal FB to the reference signal REF so that the difference in phase therebetween is zero. However, as shown in FIGS. 5A and 5B, if the difference in phase between the feedback signal FB and the reference signal REF is smaller than −180° or larger than +180°, it is impossible to correctly lock the feedback signal FB to the reference signal REF. In this case, the difference in phase therebetween is locked at 360°·m where m is ±1, ±2, . . . . 
     In FIG. 6, which illustrates an embodiment of the present invention, a variable delay circuit  1  is constructed by a series of a coarse variable delay circuit  11  and a fine variable delay circuit  12 . That is, a delay time T of the variable delay circuit  1  is determined by 
     
       
         
           T=T 
           1 
           +T 
           2  
         
       
     
     where T 1  is a delay time of the coarse variable delay circuit  11 , and 
     T 2  is a delay time of the fine variable delay circuit  12 . 
     Also, a phase comparator  2  is constructed by a pulse selection circuit  21 , a pulse selection circuit  22 , a large phase comparator  23  and a small phase comparator  24 . 
     The pulse selection circuit  21  receives the reference signal REF and numbers the pulses therein. 
     Also, the pulse selection circuit  21  selects the pulses having a special number such as “1” and transmits them to the large phase comparator  23  and the small phase comparator  24 . 
     The pulse selection circuit  22  receives the feedback signal FB and numbers the pulses therein. 
     Also, the pulse selection circuit  22  selects the pulses having a special number such as “1” and transmits them to the small phase comparator  24 . On the other hand, the pulse selection circuit  22  transmits the non-selected pulses to the large phase comparator  23 . 
     The large phase comparator  23  compares the phase of the feedback signal FB with that of the reference signal REF, when the difference in phase therebetween is large. On the other hand, the small phase comparator  24  compares the phase of the feedback signal FB with that of the reference signal REF, when the difference in phase therebetween is small. Note that, when the large phase comparator  23  is operated to generate one of control signals UP-C and DOWN-C, the small phase comparator  24  is disabled to deactivate both control signals UP-F and DOWN-F. 
     A counter  3  is constructed by a ring counter  31  connected between the large phase comparator  23  and the coarse variable delay circuit  11  and a ring counter  32  connected between the small phase comparator  24  and the fine variable delay circuit  12 . Thus, the coarse delay circuit  11  is controlled in accordance with the output of the large phase comparator  23 , and the fine delay circuit  12  is controlled in accordance with the output of the small phase comparator  24 . 
     The ring counter  31  Is an up/down  8 -ary ring counter without a decoding function. That is, when the control signal UP-C is “1”, the state of the ring counter  31  is changed from state “0” via state “1”, state “2”, . . . to state “7” as shown in FIG.  7 A. On the other hand, when the control signal DOWN-C is “1”, the state of the ring counter  31  is changed from state “7” via state “6”, state “5”, . . . to state “0” as shown in FIG.  7 A. 
     The ring counter  32  is an up/down  4 -ary ring counter with a decoding function. That is, when the control signal UP-F is “1”, the state of the ring counter  32  is changed from state “0” via state, “1” and state “2” to state “4” as shown in FIG.  7 B. On the other hand, when the control signal DOWN-F is “1”, the state of the ring counter  32  is changed from state “3” via state “2” and state “1” to state “0” as shown in FIG.  7 B. 
     In FIG. 8, which is a detailed circuit diagram of the coarse variable delay circuit  11  of FIG. 6, seven delay elements  110 ,  111 , . . .  117  are connected in series. Each of the delay elements  110 ,  111 , . . .  116  is formed by a dynamic NAND circuit such as  110   a  for passing an input signal through each of the delay elements  110 ,  111 , . . .  116 , a dynamic HAND circuit such as  110   b  for folding the input signal, a static NAND circuit such as  110   c , and an inverter such as  110   d . The delay element  117  is formed by only a dynamic NAND circuit  117   b  and a static NAND circuit  117   c  for folding the input signal. 
     The delay circuits  110 ,  111 , . . . ,  116  are controlled by output signals C 0 , C 1 , . . . C 6 , respectively, of the ring counter  31 . The output signals C 0 , C 1 , . . . , C 6  are as shown in FIG.  7 A. 
     For example, if the state of the ring counter  31  is state “1”, “0”, the output signals C 0 , C 1 , . . . , C 6  are “0”, “0”, . . . , “0” as shown in FIG.  7 A. As a result, the input signal IN is folded by the dynamic NAND circuit  110   b  and the static NAND circuit  110   c  within the delay element  110 . In this case, if a delay time T, is defined by one dynamic NAND circuit and one static NAND circuit, the delay time T, of the coarse variable delay circuit  11  is determined by the dynamic NAND circuit  110   b  and the static NAND circuit  110   c , so that the delay time T 1 , is T c . 
     Also, if the state of the ring counter  31  is state “1”, the output signals C 0 , C 1 , . . . , C 6  are “1”, “0”, . . . , “0” as shown in FIG.  7 A. As a result, the input signal IN is folded by the dynamic NAND circuit  111   b  and the static NAND circuit  111   c  within the delay element  111 . In this case, since the delay time T, of the coarse variable delay circuit  11  is determined by the dynamic NAND circuits  110   a  and  111   b  and the static NAND circuits  111   a  and  110 C, the delay time T 1  is 2·T c . 
     Further, if the state of the ring counter  31  is state “7”, the output signals C 0 , C 1 , . . . , C 6  are “1”, “1”, . . . , “1” as shown in FIG.  7 A. As a result, the input signal IN is folded by the dynamic NAND circuit  117   b  and the static NAND circuit  117   c  within the delay element  117 . In this case, since the delay time T 1  of the coarse variable delay circuit  11  is determined by the dynamic NAND circuits  110   a ,  111   a , . . . ,  117   b  and the static NAND circuits  117   c ,  116   c , . . . ,  110   c  the delay time T 1  is 8·T c . 
     Thus, if the ring counter  31  has eight states “0”, “1”, . . . , “7” as shown in FIG. 7A, the delay time T 1  of the coarse variable delay circuit  11  is changed stepwise at eight values T c , 2·T c , . . . , 8·T c , as shown in FIG.  9 . 
     In FIG. 8, since the NAND circuits such as  110   a  and  110   b  are dynamic, even if a change occurs in the output signals C 0 , C 1 , . . . , C 6  of the ring counter  31 , the generation of a spurious pulse in the output of the coarse variable delay circuit  11  can be prevented. 
     Also, If the number of delay elements is increased, the maximum value of the delay time T 1  can be easily increased, while the minimum value of the delay time T 1  is T c . In this case, note that the selector  1010  of FIG. 2 which is of a large scale is unnecessary. 
     In FIG. 10, which is a detailed circuit diagram of the fine variable delay circuit  12  of FIG. 6, two delay elements  120  and  121  having the same configuration are connected in series. Each of the delay elements  120  and  121  are controlled via inverters  1220 ,  1221 , and  1222  by the output signals F 0 , F 1  and F 2  of the ring counter  32  as shown in FIG.  7 B. 
     The delay element  120  ( 121 ) includes an inverter formed by two P-channel MOS transistors  1201   a  and  1201   b  ( 1211   a  and  1211   b ) and two N-channel MOS transistors  1202   a  and  1202   b  ( 1212   a  and  1212   b ). 
     Also, connected between a nods N 1201  (N 1211 ) of the transistors  1201   a  and  1201   b  ( 1211   a  and  1211   b ) and a ground terminal GND are three series of two P-channel MOS transistors  1203   a  and  1203   b ,  1205   a  and  1205   b , and  1207   a  and  1207   b  ( 1213   a  and  1213   b ,  1215   a  and  1215   b , and  1217   a  and  1217   b ). Similarly, connected between a node N 1202  (N 1212 ) of the transistors  1202   a  and  1202   b  ( 1212   a  and  1212   b ) and a power supply terminal V cc  are three series of two N-channel MOS transistors  1204   a  and  1204   b ,  1206   a  and  1206   b , and  1208   a  and  1208   b  ( 1214   a  and  1214   b ,  1216   a  and  1216   b , and  1218   a  and  1218   b ). 
     The gates of the transistors  1203   b ,  1204   b ,  1205   b ,  1206   b .  1207   b  and  1208   b  ( 1213   b ,  1214   b ,  1215   b ,  1216   b ,  1217   b  and  1218   b ) are connected to the output of the inverter (izola,  1201   b .  1202   a ,  1202   b ,  1211   a ,  1211   b .  1212   a ,  1212   b ). Also, the gates of the transistors  1203   a ,  1205   a  and  1207   a  ( 1213   a ,  1215   a  and  1217   a ) are controlled by the inverted signals of the control signals F 0 . F 1 , and F 2 , respectively. Further, the gates of the transistors  1204   a .  1206   a , and  1208   a  ( 1214   a ,  1216   a  and  1218   a ) are controlled by the control signals F 0 , F 1  and F 2 , respectively. 
     The transistors  1203   a ,  1203   b , . . . ,  1208   a ,  1208   b  are operated to increase the logic threshold voltages of the inverter ( 1201   a ,  1201   b ,  1202   a ,  1202   b ), and the transistors  1213   a ,  1213   b ,  1218   a .  1218   b  are operated to increase the logic threshold voltages of the inverter ( 1211   a ,  1211   b ,  1212   a ,  1212   b ). 
     If the gate width of the transistors  1203   a  and  1203   b  ( 1213   a  and  1213   b ) is W P1 , the gate width of the transistors  1205   a  and  1205   b  ( 1215   a  and  1215   b ) is W P2 , and the gate width of the transistors  1207   a  and  1207   b  ( 1217   a  and  1217   b ) is W P3 , the following condition is satisfied: 
     
       
         W P1 &lt;W P2 &lt;W P3    
       
     
     Similarly, if the gate width of the transistors  1204   a  and  1204   b  ( 1214   a  and  1214   b ) is W n1 , the gate width of the transistors  1206   a  and  1206   b  ( 1216   a  and  1216   b ) is W n2 , and the gate width of the transistors  1208   a  and  1208   b  ( 1218   a  and  1218   b ) is W n3 , the following condition is satisfied: 
     
       
         W n1 &lt;W n2 &lt;W n3    
       
     
     Under the above-mentioned two conditions, if the ring counter  32  has four states “0”, “1”, “2” and “3” as shown in FIG. 7B, the delay time T 2  of the fine variable delay circuit  12  stepwise at four values T f0 , T f1 , T f2  and T f3  as shown in FIG.  11 . In this case, if the gate widths W P1 , W P2 , W P3 , W n1 , W n2  and W n3  are suitably adjusted, the following conditions can be satisfied: 
     
       
           T   f1   −T   f0   =T   c /4  
       
     
     
       
           T   f2   −T   f1   =T   c /4  
       
     
     
       
           T   f3 −T f2   =T   c /4  
       
     
     The delay time T of the variable delay circuit z can be obtained by combining the graphs of FIGS. 9 and 11 into a graph as shown in FIG.  12 . 
     For example, assume the (C 0 , C 1 , C 2 , C 3 , C 4 , C 5 , C 6 )=(0, 0, 0, 0, 0, 0, 0). In this case, if (F 0 , F 1 , F 2 )=(0, 0, 0), 
     
       
         
           T=T 
           1 
           +T 
           2 
           =T 
           c 
           +T 
           f0  
         
       
     
     Also, if (F 0 , F 1 , F 2 )=(1, 0, 0), 
     
       
           T=T   1   +T   2   =T   c   +T   f0   +T   c /4  
       
     
     Further, if (F 0 , F 1 , F 2 )=(0, 1, 0), 
     
       
           T=T   1   +T   2   =T   c   +T   f0   +T   c /2  
       
     
     Additionally, if (F 0 , F 1 , P 2 ) =(0, 0, 1). 
     
       
           T=T   1   +T   2   =T   c   +T   f0 +3·T c /4  
       
     
     Next, assume that (C 0 , C 1 , C 2 , C 3 , C 4 , C 5 , C 6 )=(1, 0, 0, 0, 0, 0, 0) 
     In this case, if (F 0 , F 1 , F 2 )=(0, 0, 0), 
     
       
           T=T   1   +T   2 =2·T c   +T   f0    
       
     
     Also, if (F 0 , F 1 , F 2 )=(1, 0, 0). 
     
       
           T=T   1   +T   2 =2 ·T   c   +T   f0   +T   c /4  
       
     
     Further, if (F 0 , F 1 , F 2 )=(0, 1, 0), 
     
       
           T=T   1   +T   2 =2 ·T   c +3· T   c /4  
       
     
     Additionally, if (F 0 , F 1 , F 2 )=(0, 0, 1), 
     
       
           T=T   1   +T   2 =2· T   c   +T   f0 +3· T   c /4  
       
     
     Next, assume that (C 0 , C 1 , C 2 , C 3 , C 4 , C 5 , C 6 )=(1, 1, 0, 0, 0, 0, 0) 
     In this case, if (F 0 , F 1 , F 2 )=(0, 0, 0), 
     
       
           T=T   1   +T   2 =3· T   c   +T   f0    
       
     
     Also, if (F 0 , F 1 , F 2 )=(1, 0, 0), 
     
       
         T=T 1   +T   2 =3· T   c   +T   f0   +T   c /4  
       
     
     Further, if (F 0 , F 1 , F 2 )=(0, 1, 0), 
     
       
           T=T   1   +T   2 =3· T   c   +T   f0   +T   c   / 2     
       
     
     Additionally, if (F 0 , F 1 , F 2 )=(0, 0, 1). 
     
       
           T=T   1   +T   2 =3· T   c   +T   f0 +3· T   c /4  
       
     
     C 5 , C 6 )=(1, 1, 1, 0, 0, 0, 0) 
     In this case, if (F 0 , F 1 , F 2 )=(0, 0, 0). 
     
       
           T=T   1   +T   2 =4· T   c   +T   f0    
       
     
     Also, if (P 0 , F 1 , P 2 )=(1, 0, 0), 
     
       
           T=T   1   +T   2 =4· T   c   +T   f0   +T   c /4  
       
     
     Further, if (F 0 , F 1 , F 2 )=(0, 1, 0), 
     
       
           T=T   1   +T   2 =4·T c   +T   f0   +T   c /2  
       
     
     Additionally, if (F 0 , F 1 , F 2 )=(0, 0, 1), 
     
       
           T=T   1   +T   2 =4· T   c   +T   f0 +3· T   c /4  
       
     
     Next, assume that (C 0 , C 1 , C 2 , C 3 , C 4 , C 5 , C 6 )=(1, 1, 1, 1, 0, 0, 0) 
     In this case, if (F 0 , F 1 , F 2 )=(0, 0, 0), 
     
       
           T=T   1   +T   2 =5· T   c   +T   f0    
       
     
     Also, if (F 0 , F 1 , F 2 )=(1, 0, 0), 
     
       
           T=T   1   +T   2 =5· T   c   +T   f0   +T   c /4  
       
     
     Further, if (F 0 , F 1 , F 2 )=(0, 1, 0), 
     
       
         T=T 1   +T   2 =5 ·T   c   +T   f0   +T   c /2  
       
     
     Additionally, If (F 0 , F 1 , F 2 )−(0, 0, 1), 
     
       
           T=T   1   +T   2 =5· T   c   +T   f0 +3· T   c /4  
       
     
     Next, assume that (C 0 , C 1 , C 2 , C 3 , C 4 , C 5 , C 6 )=(1, 1, 1, 1, 1, 0, 0) 
     In this case, if (F 0 , F 1 , F 2 )=(0, 0, 0), 
     
       
           T=T   1   +T   2 =6· T   c   +T   f0    
       
     
     Also, if (F 0 , F 1 , F 2 )=(1, 0, 0), 
     
       
           T=T   1   +T   2 =6· T   c   +T   f0   +T   c /4  
       
     
     Further, if (F 0 , F 1 , F 2 )=(0, 1, 0), 
     
       
           T=T   1   +T   2 =6· T   c   +T   f0   +T   c /2  
       
     
     Additionally, if (F 0 , F 1 , F 2 )=(0, 0, 1), 
     
       
           T=T   1   +T   2 =6· T   c   +T   f0 +3· T   c /4  
       
     
     Next, assume that (C 0 , C 1 , C 2 , C 3 , C 4 , C 5 , C 6 )=(1, 1, 1, 1, 1, 1, 0) 
     In this case, if (F 0 , F 1 , F 2 )β(0, 0, 0), 
     
       
           T=T   1   +T   2 =7·T c   +T   f0    
       
     
     Also, if (F 0 , F 1 , F 2 )=(1, 0, 0), 
     
       
           T=T   1   +T   2 =7· T   c   +T   f0   +T   c /4  
       
     
     Further, if (F 0 , F 1 , F 2 )=(0, 1, 0), 
     
       
           T=T   c   +T   2 =7· T   c   +T   f0   +T   c /2  
       
     
     Additionally, if (F 0 , F 1 , F 2 )=(0, 0, 1), 
     
       
           T=T   1   +T   2 =7· T   c   +T   f0 +3· T   c /4  
       
     
     Finally, assume that (C 0 , C 1 , C 2 , C 3 , C 4 , C 5 , C 6 )=(1, 1, 1, 1, 1, 1, 1) 
     In this case, if (F 0 , F 1 , F 2 )=(0, 0, 0), 
     
       
           T=T   1   +T   2 =8· T   c   +T   f0    
       
     
     Also, if (F 0 , F 1 , F 2 )=(1, 0, 0), 
     
       
           T=T   1   +T   2 =8· T   c   +T   f0   +T   c /4  
       
     
     Further, If (F 0 , F 1 , F 2 )=(0, 1, 0), 
     
       
           T=T   1   +T   2 =8· T   c   +T   f0   +T   c /2  
       
     
     Additionally, If (P 0 , F 1 , F 2 )=(0, 0 1), 
     
       
           T=T   1   +T   2 =8· T   c   +T   f0 +3· T   c /4  
       
     
     FIG. 13 is a detailed block circuit diagram of the phase comparator  2  of FIG. 6, and FIGS. 14A through 14P are timing diagrams showing the operation the phase comparator  2  of FIG.  13 . 
     The pulse selection circuit  21  is formed by a 4-ary ring counter  21   a  with a decoding function and an AND circuit  21   b . That is, when the ring counter  21   a  receives the reference signal REF as shown in FIG. 14A, the ring counter  21   a  numbers each pulse of the reference signal REF at its rising edge. As a result, the outputs S 0 , S 1 , S 2  and S 3  of the ring counter  21   a  corresponding to the numbers “0”, “1”, “2” and “3”, respectively are changed as shown in FIGS. 14B,  14 C,  14 D and  14 E, respectively. Also, since the AND circuit  21   b  receives the reference signal REF and the output S 1  of the ring counter  21   a , the AND circuit  21   b  selects only the pulses of the reference signal REF having the number “1”, so that the AND circuit  21   b  generates a signal S 1 ′ as shown in FIG.  14 F. 
     Also, the pulse selection circuit  22  is formed by a 4-ary ring counter  22   a  with a decoding function and an AND circuit  22   b . That is, when the ring counter  22   a  receives the feedback signal FB as shown in FIG. 14G, the ring counter  22   a  numbers each pulse of the feedback signal FB at its rising edge. As a result, the outputs R 0 , R 1 , R 2  and R 3  of the ring counter  22   a  corresponding to the numbers “0”, “1”, “2”, and “3”, respectively are changed as shown in FIGS. 14H,  14 I,  14 J and  14 K, respectively. Also, since the AND circuit  22   b  receives the feedback signal FB and the output R 1  of the ring counter  22   a , the AND circuit  22   b  selects only the pulses of the feedback signal FB having the number “1”, so that the AND circuit  22   b  generates a signal R 1 ′ as shown in FIG.  14 L. 
     The signal S 1 ′ of the AND circuit  21   b  and the output signals R 0 , R 2  and R 3  of the ring counter  22   a  are supplied to the large phase comparator  23  for determining whether the phase of the feedback signal FB advances by 180° or more as compared with the phase of the reference signal REP and determining whether the phase of the feedback signal FB retards by 180° or more as compared with the phase of the reference signal REF. The large phase comparator  23  is formed by an OR circuit  23   a  and two D-type flip-flops  23   b  and  23   c . The D-type flip-flop  23   b  is clocked by the rising edge of the signal S 1 ′ to fetch the output signal R 2  or R 3  of the counter  22   a . That is, if the difference in phase between the feedback signal FB and the reference signal REF is 180°˜900°, the output Q of the D-type flip-flop  23   b  is “1”, i.e. the control signal UP-C is “1”. On the other hand, the D-type flip-flop  23   c  is clocked by the rising edge of the signal S 1 ′ to fetch the output signal RO of the counter  22   a . That is, if the difference in phase between the feedback signal FB and the reference signal REF is −180°˜540°, the output Q of the D-type flip-flop  23   c  is “1” i.e. the control signal DOWN-C is “1”. Note that the control signals UP-C and DOWN-C are shown in FIGS. 14M and 14N. 
     When the control signal UP-C is “1”, the content of the ring counter  31  is increased to increase the delay time T 1  of the coarse variable delay circuit  11 . On the other hand, when the control signal DOWN-C is “1”, the content of the ring counter  31  is decreased to decrease the delay time T 1  of the coarse variable delay circuit  11 . 
     The signal S 1 ′ of the AND circuit  21   b  and the signal R 1 ′ of the AND circuit  22   b  are supplied to the small phase comparator  24  for determining whether the phase of the feedback signal FB advances by 180° or less as compared with the phase of the reference signal REF and determining whether the phase of the feedback signal PB retards by 180° or less as compared with the phase of the reference signal REP. The small phase comparator  24  is formed by two D-type flip-flop  24   b  and  24   c  and two AND circuits  24   c  and  24   b . The D-type flip-flop  24   a  is clocked by the rising edge of the signal S 1 ′ to fetch the signal R 1 ′. That is, if the difference in phase between the feedback signal FB and the reference signal REF is 0°˜180°, the output Q of the D-type flip-flop  24   a  is “1”, so that the control signal UP- 1  is “1”, since the output {overscore (Q)} of the D-type flip-flop  23   b  is “1”. On the other hand, the D-type flip-flop  24   b  is clocked by the rising edge of the signal R 1 ′ to fetch the output signal S 1 ′. That is, if the difference in phase between the feedback signal FB and the reference signal REF is −180°˜0° the output Q of the D-type flip-flop  24   b  is “1”, so that the control signal DOWN-F is 1, since the output {overscore (Q)} of the D-type flip-flop  23   c  is “1”. Note that the control signals UP-E and DOWN-F are shown in FIGS. 14O and 14P. 
     When the control signal UP-F is “1”, the content of the ring counter  32  is increased to increase the delay time  11  of the fine variable delay circuit  12 . On the other hand, when the control signal DOWN-F is “1”, the content of the ring counter  32  is decreased to decrease the delay time T 2  of the fine variable delay circuit  12 . 
     In FIG. 13, the AND circuit  24   c  and  24   d  are provided, so that if the large phase comparator  23  is substantially operated, the small phase comparator  24  is not substantially operated. That is, if the control signal UP-C is “1”, the control signal UP-F is always “0”, and if the control signal DOWN-C is “0”, the control signal DOWN-F is always “0”. In other words, only one of the phase comparators  23  and  24  is substantially operated, to stabilize the operation of the variable delay circuit  1 . However, as illustrated in FIG. 15, the AND circuits  24   c  and  24   d  can be omitted. 
     Also, in FIG. 6, although the variable delay circuit  1  is a series of the coarse variable delay circuit  11  and the fine variable delay circuit  12 , the variable delay circuit  1  can be a series of the fine variable delay circuit  12  and the coarse variable delay circuit  11  as illustrated in FIG.  16 . 
     Further, in FIG. 6, although the feedback signal FB is obtained directly by the output signal OUT, the feedback signal FB is obtained indirectly by the output signal OUT. For example, a frequency divider is provided between an output terminal for the output signal OUT and a terminal for the feedback signal FB. 
     As explained hereinabove, according to the present invention, when the difference in phase between the feedback signal and the reference signal is relatively large, the large phase comparator is operated to remarkably change the delay time, and when the above-mentioned difference is relatively small, the small phase comparator is operated to gradually change the delay time. As a result, the decrease of jitter as well as the decrease of the locking time can be both obtained. Additionally, due to the large phase comparator, even if the difference in phase is large, the feedback signal can be correctly locked to the reference signal.