Abstract:
An integrated phase adjusting circuit ( 12 ) for the generation of a clock output signal (CLK out ) with a phase intermediate the phases of first and second input signals of equal frequency with a fixed phase shift between said first and second signals is proposed. The circuit has an interpolator unit ( 30 ) which determines the phase of the clock signal relative to either one of the first input signal and the second input signal, and is controlled externally by a control signal (PH fine ) to execute a phase step if the phase of the clock signal is to be shifted. The circuit ( 12 ) comprises a synchronization unit ( 40 ) which synchronizes the phase step with the clock output signal generated by the circuit.

Description:
FIELD OF INVENTION  
       [0001]     The present invention relates to an integrated phase adjusting circuit for the generation of a clock output signal with a phase intermediate the phases of first and second input signals of equal frequency with a fixed phase shift between said first and second signals.  
       BACKGROUND OF THE INVENTION  
       [0002]     Such circuits are commonly used with voltage controlled oscillators (VCO) in phase locked loops (PLL). The circuit comprises an interpolator unit which receives two input signals of similar phase and frequency but slightly different in phase from the VCO and outputs the desired clock signal with a phase interpolated between the phase of the first input signal and the second input signal. The design and function of this interpolator is known in the art for example from DE 100 28 603. The interpolator is controlled externally to determine the phase of the clock signal relative to either one of the first input signal or the second input signal. To change the phase of the clock output signal, a phase step has to be executed. This phase step is executed by the interpolator unit shifting the phase of the clock signal closer to the phase of either the first or the second input signal when it receives a phase step command. When the phase step is executed, the following crosspoint between the complementary output signals is shifted, which means that one period of the clock signal is extended in duration. Capacitive coupling through switches within the interpolator can cause an additional shift of the following crosspoint. As a result, the extended period is prolonged further and the following period is shortened by the same amount. This unintended effect will appear as phase jitter in the generated clock signal.  
       SUMMARY OF THE INVENTION  
       [0003]     A general object of the present invention is an integrated phase adjusting circuit for the generation of a clock output signal with minimized irregularities at phase steps.  
         [0004]     This and other objects and features are provided, in accordance with one aspect of the invention by a phase adjusting circuit for the generation of a clock output signal with a phase intermediate the phases of first and second input signals of equal frequency with a fixed phase shift between said first and second signals is provided. The circuit has an interpolator unit which determines the phase of the clock signal relative to either one of the first input signal and the second input signal. The interpolator unit is controlled externally by a control signal to execute a phase step when the phase of the clock signal is to be shifted. The circuit comprises a synchronization unit which synchronizes the phase step with the clock output signal generated by the circuit. It has been found that the effect of the unwanted coupling which additionally prolongs the period preceding the phase step is strongly dependent on the relative phase when the phase step is executed. By synchronizing the phase step with the phase of the output clock signal, a shortened period after the phase step can be avoided and, thus, additional phase jitter in the output clock signal is avoided.  
         [0005]     In accordance with another aspect of the invention, the synchronization unit comprises a command input for receiving a phase step command, a detector for detecting when the phase of the clock output signal is within a phase window in which a phase step can be executed without adding phase jitter to the clock output signal, and a latch for forwarding the phase step command to the interpolator when the phase of the clock output signal is within said phase window. The synchronization unit receives a phase step command and stores it until it detects that the output clock signal is within the afore-mentioned phase window.  
         [0006]     Further features and advantages of the invention will become apparent from the following detailed description with reference to the drawings.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]      FIG. 1  is a block diagram illustrating the basic structure of a clock signal generator using a phase adjusting circuit according to the invention.  
         [0008]      FIG. 2  is a diagram illustrating the phases of the signals generated by the VCO of  FIG. 1 .  
         [0009]      FIG. 3  is a schematic of the interpolator of  FIG. 1 .  
         [0010]      FIG. 4  is a diagram illustrating a clock output signal generated by a circuit from the state of the art.  
         [0011]      FIG. 5  is a diagram illustrating another clock output signal generated by a circuit from the state of the art.  
         [0012]      FIG. 6  is a diagram illustrating yet another clock output signal generated by a circuit from the state of the art.  
         [0013]      FIG. 7  is a diagram illustrating a clock signal generated by a circuit according to the present invention.  
         [0014]      FIG. 8  is a diagram illustrating phase windows for executing a phase step.  
         [0015]      FIG. 9  is a schematic of a phase adjusting circuit according to a first embodiment of the present invention.  
         [0016]      FIG. 10  is a schematic of a phase adjusting circuit according to a second embodiment of the invention.  
     
    
     DETAILED DESCRIPTION  
       [0017]     The block diagram in  FIG. 1  shows a clock signal generator  10  with a phase adjusting circuit  12  according to the invention, with an oscillator  20  and two multiplexers  22  and  24 . The clock signal generator  10  generates a clock output signal CLK out  that can be used in circuit configurations which require a signal with a shiftable phase, e.g. a phase locked loop (PLL).  
         [0018]     The oscillator  20  is a voltage controlled oscillator (VCO), preferably a ring oscillator, and provides a plurality of similar signals φ 1  to φ n  at the same frequency but with a fixed phase shift between signals φ m  and φ m+1 , wherein 1≦m≦n. The phase shift corresponds exactly to the propagation time τ delay  for a high/low transition of one oscillator stage. As such a transition of the signal has to pass through all n stages of the ring oscillator and two transitions make one period, the time between two neighboring phases is: 
 
τ delay =360°/2  n.  
 
         [0019]      FIG. 2  is a phase diagram that illustrates exemplary of the VCO signals φ 1  to φ n . The phases of the n VCO signals φ 1  to φ n  and their inverted equivalents φ 1   −1  to φ n   −1  divide one period into 2n sectors φ 1  to φ 2   n.    
         [0020]     The VCO outputs providing the VCO signals φ 1  to φ n  are connected to the multiplexers  22 ,  24 . The VCO outputs providing the signals φ 1 , φ 3  . . . with odd phases are connected to the first multiplexer, which in the following will be referred to as the odd multiplexer  22 , and those VCO outputs providing the signals φ 2 , φ 4  . . . with even phases are connected to the second multiplexer which in the following will be referred to as the even multiplexer  24 .  
         [0021]     The odd multiplexer  22  has a signal output  16  and a control input  26 . The even multiplexer  24  has a signal output  18  and a control input  28 . Both multiplexers  22 ,  24  are externally controlled by a control unit (not shown) for selecting two signals with neighboring phases, e.g. φ 2  and φ 3  or φ 3  and φ 4 . The selected signals are provided at the outputs  16 ,  18  of the multiplexers  22 ,  24 . In the following, the signal provided at the output  16  of the odd multiplexer  22  will be referred to as odd signal φ odd  and the signal provided at the output  18  of the even multiplexer  24  will be referred to as even signal φ even . By picking the signals φ odd  and φ even , out of the plurality of signals φ 1  to φ n , one of the sectors S 1  to S 2   n  (c.f.  FIG. 2 ) for the clock output signal CLK out  has been selected. So, this selection is a coarse tuning for the phase of the clock output signal CLK out .  
         [0022]     The fine tuning of the phase of the clock output signal CLK out  within this selected sector is done in the phase adjusting circuit  12  which will be described in detail in the following.  
         [0023]     The phase adjusting circuit  12  comprises an interpolator unit  30  and a synchronization unit  40 . The interpolator unit  30  interpolates from the two input signals φ odd  and φ even  the clock output signal with a phase intermediate the phases of the first input signal φ odd  and the second input signal φ even . The interpolator unit  30  has a first input  32  for receiving a first input signal φ odd  from the odd multiplexer  22 , a second input  34  for receiving a second input signal φ even  from the even multiplexer  24 , a signal output  36  to provide the clock output signal CLK out  and a control input  38 .  
         [0024]     Referring now to  FIG. 3 , there is shown a schematic of the interpolator  30 . The design of an interpolator is known in the state of the art, e.g. from DE 100 28 603. Therefore, the description of the design and function of the interpolator  30  will be restricted to those details needed for comprehension of the invention.  
         [0025]     The interpolator  30  comprises a first charging circuit L 1 , having a capacitor C 1  and a resistor R 1 . The capacitor C 1  of the charging circuit L 1  can be charged and discharged, thus the voltage of the capacitor C 1  which defines the clock output signal CLK out  will oscillate. A second charging circuit L 2  having a capacitor C 2  and a resistor R 2  is provided which operates inverse to the first charging circuit L 1 . Therefore, the interpolator  30  can provide a differential clock output signal CLK out . This is advantageous for use with various applications requiring differential clock signals.  
         [0026]     The interpolator  30  further comprises a set of switching stages SW 1 -SW 32  which are configured identically. The structure of these switching stages SW 1 -SW 32  is described in detail in the following by example of the first switching stage SW 1 .  
         [0027]     The first switching stage SW 1  comprises a current source S 1  providing a current I 0  for charging the capacitors C 1 , C 2 , a first current switch TR 1   a,  a second current switch TR 1   b,  and a control circuit CC 1  for controlling the current switches TR 1   a  and TR 1   b.    
         [0028]     The first switching stage SW 1  further comprises a first switch couple PS 1   a - 1 , PS 1   b - 1 , controlled by the first input signal φ odd , and a second switch couple PS 2   a - 1 , PS 2   b - 1 , controlled by the second input signal φ even . The first switch couple PS 1   a - 1 , PS 1   b - 1  is connected to the first current switch TR 1   a  and can connect the current source S 1  to either the first charging circuit L 1  or the second charging circuit L 2 . Similarly, the second switch couple PS 2   a - 1 , PS 2   b - 1  is connected to the second current switch TR 1   b  and can connect the current source S 1  to either the first charging circuit L 1  or the second charging circuit L 2 .  
         [0029]     In the figures, the reference signs of the components of the switching stages SW 1 -SW 32  are indexed by numbers 1 to 32. So, switch couples PS 1   a - 2 , PS 1   b - 2  and PS 2   a - 2 , PS 2   b - 2 , switches TR 2   a,  TR 2   b  and control circuit CC 2  belong to switching stage SW 2 , switch couples PS 1   a - 3 , PS 1   b - 3  and PS 2   a - 3 , PS 2   b - 3 , switches TR 3   a,  TR 3   b  and control circuit CC 3  belong to switching stage SW 3 , etc.  
         [0030]     The first switch couples PS 1   a - 1 , PS 1   b - 1  to PS 1   a - 32 , PS 1   b - 32  are assigned to a switch set which is controlled by the first input signal φ odd  and in the following will be referred to as PS 1 . The second switch couples PS 2   a - 1 , PS 2   b - 1  to PS 2   a - 32 , PS 2   b - 32  are assigned to a switch set which is controlled by the second input signal φ even  and in the following will be referred to as PS 2 . For simplicity, also the other components of the switching stages SW 1 -SW 32  will in the following be referenced without the indexing numbers.  
         [0031]     The number of the switching stages SW 1 -SW 32  in this embodiment is 32, and represents the number of steps f, the phase of the clock output signal can be shifted within one sector between the phase of the first input signal φ odd  and the second input signal φ even  (see  FIG. 2 ). But any other number may be implemented, depending on the desired number of steps.  
         [0032]     The current switches TR 1  to TR 32  are controlled by control circuits CC 1  to CC 32 , for selectively connecting each of the current sources to either the first or the second set of phase switches. So, by selecting the number of current sources S which are connected to the first set of phase switches PS 1  and to the second set of phase switches PS 2 , the current charging the Capacitors C 1 , C 2  can be controlled, and thus the phase of the clock output signal CLK out  can be determined to be closer to the phase of the first input signal φ odd  or the second input signal φ even .  
         [0033]     To determine the fine tuning of the phase of the clock output signal CLK out , the interpolator  30  is controlled externally by a control signal PH fine , which is received through the control input  38  and may be a digital code for example. The interpolator does this fine tuning by performing a phase shift, which means, that it executes a phase step when it receives the respective command through the control input  38 .  
         [0034]     If a phase step command is to be executed, one of the current sources S is switched from the first set of phase switches PS 1  to the second set of phase switches PS 2  or vice versa, by one of the control circuits CC changing the status of its assigned current switches TRa and TRb.  
         [0035]     The diagram of  FIG. 4  shows a theoretical output signal CLK out  with a basic period λ 0  when such a phase step is performed. For reasons of simplified illustration, the signal is drawn single ended only. The phase step is executed at t=t 0 . As a result, one period λ 0  of the clock output signal CLK out  is extended to a period λ step . To illustrate the resulting phase shift, the signal as it would have been without the phase step is drawn in dotted line.  
         [0036]     In the interpolator known from the state of art, the extended period λ step  suffers an additional cross point shifting. This additional crosspoint shifting is due to coupling effects in the switching transistors of the interpolator, which influence the charging current for the capacitors C 1 , C 2 , thus changing the steepness of subsequent rising or falling edges of the signal. The results of this phenomenon are illustrated in the diagram of  FIG. 5 .  
         [0037]     A phase step is assumed to be executed at t=t 0 . Without a coupling effect, the crosspoint X following the phase step will be shifted resulting in the clock output signal CLK out  showing one extended period λ step  (broken line). Due to the coupling mentioned above, the crosspoint X is additionally shifted by an amount δλ. This amount can have a positive or a negative sign. As a result, the extended period λ step  is additionally prolonged by the amount δλ and the following period is shortened by the same amount. This unintended prolonging and shortening of the extended period λ step  and the following period in the clock output signal CLK out  causes additional phase jitter in the output signal.  
         [0038]     The applicant has found that the influence of the coupling effect on variations in the period of the clock output signal CLK out  is strongly dependent on the phase relationship when the phase step is executed. This is illustrated in  FIGS. 6 and 7 .  
         [0039]      FIG. 6  shows the differential clock output signal CLK out  with a phase step executed at t=t pre , less than 90° before a crosspoint X of the signal. Additional cross point shifting is produced through coupling, resulting in an additionally prolonged period λ step +δλ followed by a shortened period λ 0 −δλ. Shown in dashed lines is the theoretical signal as it would have been without coupling effect.  
         [0040]      FIG. 7  shows the differential clock output signal CLK out  when the phase step is executed at t=t post  after a crosspoint X. In this case, the capacitive coupling has no influence on the period λ step . The next crosspoint X +1  is shifted by the desired amount, but no additional cross point shifting δλ occurs. The only effect of the coupling is that the rising edge of the signal CLK out  reaches its peak pk following the phase step at t=t post  a little bit later. However, this does not shift the crosspoint X +1  because after the peak pk, the signal is determined by the first input signal φ odd  and the second input signal φ even  only, just like it was prior to the phase step. Then, the extended period λ step  is followed by original periods λ 0 .  
         [0041]     Thus, a phase window Δφ can be defined where a phase step can be executed without causing additional irregularities. The width of this phase window Δφ depends on the application that uses the clock output signal CLK out . If only full periods are considered, the window has a width of Δφ h &lt;270°. If half periods are considered also, the window width is roughly a quarter of a period or Δφ f &lt;90°. Both cases are illustrated in the diagram of  FIG. 8 .  
         [0042]     In order to provide a clock output signal CLK out  with minimized irregularities, the phase adjusting circuit  12  according to the invention comprises a synchronization unit  40  with a control input  42  for receiving the external control signal PH fine  designated for the interpolator  30 , a control output  44  which is connected to the control input  38  of the interpolator  30  for forwarding the external control signal PH fine  to the interpolator  30 , and a feedback input  46  which is connected to the signal output  36  of the interpolator  30 .  
         [0043]     When the synchronization unit  40  receives an external phase step command in the control signal PH fine , it will store this command for forwarding it to the command input  38  of the interpolator  30  just at the right moment in order to synchronize the execution of the phase step command with the clock output signal CLK out . To find this right moment, the clock output signal CLK out  is branched off into the feedback input  46  of the synchronization unit  40 , allowing the synchronization unit  40  to detect when the clock output signal CLK out  is within the phase window Δφ.  
         [0044]     Referring now to  FIG. 9 , there is shown a schematic of a synchronization unit  40  for use in a phase adjusting circuit  12  according to a first embodiment of the invention.  
         [0045]     The synchronization unit  40  comprises a conversion stage  60  for converting the differential clock output signal CLK out  into a single ended trigger signal TRIG. Preferably, the conversion stage  60  is similar to an oscillator stage of the VCO and is therefore process, temperature, voltage and frequency compensated.  
         [0046]     The synchronization unit  40  further comprises a latch constituted by one double flip-flop  50  for each of the control circuits CC 1  to CC 32 . The double flip-flop  50  has a data input  52 , a trigger input  54  and an output  56  connected to the associated control circuit. The double flip-flop  50  is clocked by the trigger signal TRIG. If a phase step command from the control signal PH fine  has to be executed, the data input  52  of the respective latch is preloaded. Then, at the output  56  the phase step command is forwarded to the assigned control circuit CC of the interpolator  30  when the double flip-flop is triggered. This means that the phase step command is latched with the trigger signal TRIG and thus synchronized with the clock output signal CLK out .  
         [0047]     Considering the propagation time for a signal throughout the interpolator  30  and the synchronization unit  40 , in this embodiment, the phase step is executed after  
         T     pd   ⁢           ⁢   total       =     1     4   ⁢     (       T     pd   ⁢           ⁢   conversion       +     T     pd   ⁢           ⁢   FF       +     T     pd   ⁢           ⁢   int         )             
 
 where 
 
         [0048]     T pdconversion  is the propagation time for the conversion of the clock output signal CLK out  into a single-ended signal,  
         [0049]     T pdFF  is the propagation time through the double flip-flop  50  from the clock input  52  to the output  56  and  
         [0050]     T pdInt  is the propagation time within the interpolator  30  from the command input  38  to the output  36 .  
         [0051]     It can be found that T pdtotal  may be longer than the a quarter of a period of the clock output signal CLK out . In this case, the phase step would be executed outside the acceptable phase window Δφ.  
         [0052]     To avoid this, the synchronization unit  40  comprises a delay circuit  58  for delaying the branched-off clock output signal CLK out  before it is converted within the conversion unit  60 . So, the trigger signal TRIG for the double flip-flop  50  is delayed to the next phase window Δφ in the following period of the clock output signal CLK out . Preferably, the stages of the delay circuit  58  are copies of the VCO stages and are therefore process, temperature, voltage and frequency compensated.  
         [0053]     To remain within the acceptable phase window Δφ, the variation of T pdtotal  has to be smaller than a quarter of a period of the clock output signal. Since the propagation time through the double flip-flop T pdFF  and the propagation time within the interpolator T pdInt  are not process-, temperature voltage and frequency compensated, the first embodiment can be used up to a maximum frequency of  
           f   max     =     1     4   ⁢     (       Δ   ⁢           ⁢     T     pd   ⁢           ⁢   FF         +     Δ   ⁢           ⁢     T     pd   ⁢           ⁢   int           )           ,       
 
 with 
 
         [0054]     ΔT pdFF  being the variation of propagation time through the double flip-flop and  
         [0055]     ΔT pdInt  being the variation of propagation time through the integrator.  
         [0056]     Referring now to  FIG. 10 , there is shown a schematic of a synchronization unit  140  for a phase adjusting circuit according to a second embodiment of the invention. For components already used in the first embodiment, reference numbers augmented by 100 are used. The phase adjusting circuit of this embodiment uses an interpolator similar to the one described in the first embodiment.  
         [0057]     The synchronization unit  140  comprises a conversion stage  160  for conversion of the differential clock output signal CLK out  into a single ended trigger signal TRIG. Preferably, the conversion stage  160  is similar to an oscillator stage of the VCO and is therefore process, temperature, voltage and frequency compensated. Also, for the reasons given above, a delay circuit  158  is included.  
         [0058]     The synchronization unit  140  further comprises a monoflop  170  having an input  172  and an output  174 . The output of the conversion stage  160  is connected to the input  172  of the monoflop  170 . The monoflop  170  transforms a positive edge of the trigger signal TRIG into a high potential provided at the output  174 .  
         [0059]     The synchronization unit  140  also includes a latch constituted by a set of similar D-flip-flops  180 , one of them being illustrated in  FIG. 10 . The D-flip-flop  180  has a data input  182 , a trigger input  184 , connected to the output  174  of the monoflop  170 , and a differential output  186 ,  188  for controlling the current switches TR of the assigned switching stage SW within the interpolator. So, the D-flip-flop  180  likewise constitutes a control circuit for the switch TR and is preferably integrated into the interpolator, i.e. into the control circuit CC. The data input  182  of the D-flip-flop  180  is provided with the external phase step command in the control signal PH fine .  
         [0060]     The double flip-flop  180  is clocked by the trigger signal TRIG. If a phase step command from the control signal PH fine  has to be executed, the data input  182  of the respective latch is preloaded. When the double flip-flop  180  is triggered by the conditioned trigger signal TRIG from the monoflop  170 , it acts as control circuit CC and toggles the associated switch TR TR of the interpolator  30 . This means that the phase step command is latched with the trigger signal TRIG and thus synchronized with the clock output signal CLK out .  
         [0061]     This embodiment can be used up to a maximum frequency of  
         f   max     =       1     4   ⁢     (       Δ   ⁢           ⁢     T     pd   ⁢           ⁢     NOR   /   INV           +     Δ   ⁢           ⁢     T     pd   ⁢           ⁢   int           )         .         
 
 where 
 
         [0062]     ΔT pdNOR/INV  is the variation in propagation time through the NOR-Gates and the inverter and  
         [0063]     ΔT pdInt  is the variation in propagation time through the integrator.  
         [0064]     This maximum frequency is considerably higher than the maximum frequency of the first embodiment, because the variation in the double flip-flop propagation time T pdFF  of the first embodiment is at least two to three times higher than the variation in propagation time T pdNOR/INV  through the NOR-Gates and the inverter.  
         [0065]     Further, the power consumption of the second embodiment is much lower, since the monoflop  170  has to be implemented only one time whereas the double flip-flop  50  in the first embodiment must be implemented for every switch stage in the interpolator.  
         [0066]     While the invention has been shown and described with reference to preferred embodiments thereof, it is well understood by those skilled in the art that various changes and modifications can be made in the invention without departing from the spirit and scope of the invention as defined by the appended claims.