Abstract:
A compensated regulator includes a transconductance stage having a positive input for receiving a reference voltage, a negative input, and an output, an adjustable compensation block coupled between the output of the transconductance stage and ground, a feedback circuit having a first node coupled to the output of the compensated regulator, a second node coupled to the negative input of the transconductance stage, and a third node coupled to ground, and a driver stage having an input coupled to the output of the transconductance stage, a current output coupled to the output of the compensated regulator, and a sense output coupled to the adjustable compensation block.

Description:
RELATED APPLICATION 
       [0001]    The present application claims priority of Chinese Application No. 200610074740.5 filed Mar. 17, 2006, which is incorporated herein in its entirety by this reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    The present invention is related to linear regulator circuits, and, more particularly, to a linear regulator circuit having a stable compensation circuit and method that is particularly useful when used in automotive applications. 
         [0003]    A traditional regulator integrated circuit  100  for use in automotive applications is shown in  FIG. 1 . In a typical example, transistors M 1  and M 2  are 5V NMOS devices, transistors M 4  and M 5  are HV-NDMOS devices, and transistors M 3  and M 6  are HV-PMOS devices. Transistors Q 1  and Q 2  are bipolar transistors. An external 14.4V battery voltage is applied at node  102 , an internal 5V battery voltage is applied at node  104 , and a bandgap voltage VBG is applied at node  106 . An operational amplifier or gm stage  108  is used in the feedback loop. The output of the regulator  100  drives the output load as shown. 
         [0004]    In the regulator loop of the circuit shown in  FIG. 1 , there are three poles and two zeros that are the main contribution to stability as listed below:
       P 0 =Req 3 *Co; P 1 =Req 1 *Cc; P 2 =Req 2 *Ceq;   Z 0 =ESR*Co; Z 1 =Rc*Cc.       
 
         [0007]    where: 
         [0008]    Co: Output capacitor, 
         [0009]    Cc: Internal compensation capacitor, 
         [0010]    Ceq: equivalent capacitor in the gate node of M 6 , 
         [0011]    ESR: equivalent series resistor of Co, 
         [0012]    Req 1 : output resistor of gm stage, 
         [0013]    Req 2 : equivalent resistor in the gate node of M 6 , and 
         [0014]    Req 3 : equivalent resistor in the output node of the regulator. 
         [0015]    The problem with the low drop-out regulator  100  shown in  FIG. 1  is that a different load current results in different Idr 1  and Idr 2  currents. Equivalent resistors Req 2  and Req 3  are also different for different load currents, and hence poles P 0  and P 2  are undesirably variable. 
         [0016]    In a practical design, zero Z 1  is constant and used to cancel pole P 2 . Poles P 0  and P 1  are dominant poles, but P 1  is constant while P 0  is variable. Therefore, if Z 1 =P 2  are under light load conditions, then regulator  100  tends to over-compensate under heavy load conditions. This is because poles P 2  and P 0  are much farther out in frequency in heavy load conditions than in light load conditions, while Z 1  is quite low in frequency. If Z 1 =P 2  under heavy load conditions, then regulator  100  tends to under-compensate under light load conditions, because poles P 2  and P 0  are much lower in frequency in light load than in heavy load while Z 1  is quite high. And so a stable regulator requires that the capacitance and ESR of the output capacitor should be in a very limited range to avoid worsening over-compensation or under-compensation any further. 
         [0017]    What is desired, therefore, is a low drop-out regulator that can be easily compensated without any of the drawbacks such as load current sensitivity and the requirement of a limited output capacitance range that is present in prior art regulators. 
       SUMMARY OF THE INVENTION 
       [0018]    A compensated regulator for use in automotive and other applications includes a transconductance stage having a positive input for receiving a reference voltage, a negative input, and an output, an adjustable compensation block coupled between the output of the transconductance stage and ground, a feedback circuit having a first node coupled to the output of the compensated regulator, a second node coupled to the negative input of the transconductance stage, and a third node coupled to ground, and a driver stage having an input coupled to the output of the transconductance stage, a current output coupled to the output of the compensated regulator, and a sense output coupled to the adjustable compensation block. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0019]    The aforementioned and other features and objects of the present invention and the manner of attaining them will become more apparent and the invention itself will be best understood by reference to the following description of a preferred embodiment taken in conjunction with the accompanying drawings, wherein: 
           [0020]      FIG. 1  is a schematic diagram of a traditional regulator used in automotive applications, according to the prior art; 
           [0021]      FIG. 2  is a schematic diagram of a regulator using the compensation circuit and method according to the present invention; 
           [0022]      FIG. 3  is a plot of Req 2  and Rzero with respect to load current of the compensated regulator of the present invention; 
           [0023]      FIG. 4  is a plot of the ratio of Rzero to Req 2  with respect to load current of the compensated regulator of the present invention; 
           [0024]      FIG. 5  is a plot of the ratio of P 2  to Z 1  with respect to load current of the compensated regulator of the present invention; 
           [0025]      FIG. 6  is a plot of the regulated output voltage and load transients with the output capacitor=0.1 uF and ESR=0 ohm according to the present invention; 
           [0026]      FIG. 7  is a plot of the regulated output voltage and load transients with the output cap=0.1 uF and ESR=30 ohm according to the present invention; 
           [0027]      FIG. 8  is a plot of the regulated output voltage and load transients with the output cap=100 uF and ESR=0 ohm according to the present invention; and 
           [0028]      FIG. 9  is a plot of the regulated output voltage and load transients with the output cap=100 uF and ERS=30 ohm according to the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0029]    According to the present invention, the compensation method and circuit  200  shown in  FIG. 2  forces zero Z 1  and pole P 2  to have substantially the same dependence on the load current (Iload). 
         [0030]    Referring to  FIG. 2 , internal zero Z 1  is defined by: 
         [0000]        Z 1 =R zero× Cc =( Rc +( Rp∥R   onM8 ))× Cc    (1) 
         [0031]    Transistors M 6  and M 7  have an area ratio of n:1, and transistors M 8  and M 9  have an area ratio of 1:1. In a low quiescent current (Iq) regulator, resistors R 1  and R 2  are very large and therefore I ds     —     M6 ≈Iload. Buffer  210  is used to force V gs     —     M8 =V gs     —     M9 . Transistor M 8  generally operates in the triode region and transistor M 9  generally operates in the saturation region, hence: 
         [0000]    
       
         
           
             
               
                 
                   
                     R 
                     
                       onM 
                        
                       
                           
                       
                        
                       8 
                     
                   
                   = 
                   
                     
                       1 
                       
                         g 
                         
                           m 
                            
                           
                               
                           
                            
                           9 
                         
                       
                     
                     = 
                     
                       1 
                       
                         
                           2 
                            
                           
                             k 
                             
                               m 
                                
                               
                                   
                               
                                
                               8 
                             
                           
                           × 
                           
                             Iload 
                             n 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
         [0032]    Under heavy load conditions, R onM8  is of the kohm order, but under light load conditions, R onM8  is of the 10 Mohm order. In order to let the compensation resistor of the internal zero have a smoother transition from light load to heavy load conditions, resistors Rc and Rp are used. Resistor Rc is of the 10 kohm order, and resistor Rp is of the 100 kohm order. From light load conditions to heavy load conditions, therefore, the compensation resistor of the internal zero changes from the 100 kohm order to the 10 kohm order and change with the square root of the load current (Iload). Capacitor Cc is of the 10 pf order and does not change substantially with operating conditions. Therefore, zero Z 1  also changes with the square root of the load current (ILoad). 
         [0033]    From  FIG. 2 , pole P 2  can also be determined: 
         [0000]        P 2 =Req 2 ×Ceq    (3) 
         [0034]    Capacitor Ceq is the equivalent total capacitance on the gate node of power transistor M 6 , which mainly comes from the gate capacitance of transistor M 6  and does not change with operating conditions. Assuming the area ratio of transistors M 1  and M 2  is 1:1, then Idr 1 =Idr 2 =Idr. Resistor R 4  is of the kohm order, and resistor R 3  is of the  100 kohm order. Resistor R 3  is quite large and can be ignored to facilitate calculation and so: 
         [0000]    
       
         
           
             
               
                 
                   
                     Req 
                      
                     
                         
                     
                      
                     2 
                   
                   = 
                   
                     
                       
                         Vt 
                         
                           Ilow 
                           + 
                           Idr 
                         
                       
                       + 
                       
                         
                           
                             R 
                              
                             
                                 
                             
                              
                             4 
                           
                           + 
                           
                             R 
                             
                               onM 
                                
                               
                                   
                               
                                
                               3 
                             
                           
                         
                         
                           β 
                           npn 
                         
                       
                     
                     = 
                     
                       
                         Vt 
                         
                           Ilow 
                           + 
                           Idr 
                         
                       
                       + 
                       
                         1 
                         
                           
                             β 
                             npn 
                           
                           × 
                           
                             
                               2 
                                
                               
                                 k 
                                 
                                   M 
                                    
                                   
                                       
                                   
                                    
                                   3 
                                 
                               
                               × 
                               Idr 
                             
                           
                         
                       
                       + 
                       
                         
                           R 
                            
                           
                               
                           
                            
                           4 
                         
                         
                           β 
                           npn 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
             
               
                 
                   
                     
                       Idr 
                       × 
                       R 
                        
                       
                           
                       
                        
                       4 
                     
                     + 
                     
                       V 
                       
                         gsM 
                          
                         
                             
                         
                          
                         3 
                       
                     
                   
                   = 
                   
                     V 
                     
                       gsM 
                        
                       
                           
                       
                        
                       6 
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
         [0000]    Both transistors M 3  and M 6  operate in the saturation region, hence: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       Idr 
                       × 
                       R 
                        
                       
                           
                       
                        
                       4 
                     
                     + 
                     
                       
                         
                           2 
                            
                           Idr 
                         
                         
                           K 
                           
                             M 
                              
                             
                                 
                             
                              
                             3 
                           
                         
                       
                     
                   
                   = 
                   
                     
                       
                         2 
                         × 
                         Iload 
                       
                       
                         K 
                         
                           M 
                            
                           
                               
                           
                            
                           6 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
         [0000]    Solving equation (6) gives: 
         [0000]    
       
         
           
             
               
                 
                   
                     Idr 
                   
                   = 
                   
                     
                       
                         
                           
                             2 
                             
                               K 
                               
                                 M 
                                  
                                 
                                     
                                 
                                  
                                 3 
                               
                             
                           
                           + 
                           
                             4 
                             × 
                             R 
                              
                             
                                 
                             
                              
                             4 
                             × 
                             
                               
                                 
                                   2 
                                   × 
                                   Iload 
                                 
                                 
                                   K 
                                   
                                     M 
                                      
                                     
                                         
                                     
                                      
                                     6 
                                   
                                 
                               
                             
                           
                         
                       
                       - 
                       
                         
                           2 
                           
                             K 
                             
                               M 
                                
                               
                                   
                               
                                
                               3 
                             
                           
                         
                       
                     
                     
                       2 
                        
                       R 
                        
                       
                           
                       
                        
                       4 
                     
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
           
         
       
     
         [0035]    Comparing equations (3) and (4) with equation (7), it can be seen that pole P 2  changes with the square root of the load current (Iload) and has the same dependence on the square root of load current (Iload) as zero Z 1 . Therefore, the compensation circuit and method of the present invention substantially mitigates over-compensation during heavy load conditions and under-compensation during light load conditions. This results in a compensation method and circuit that has excellent stability. During design, proper component values are chosen to allow zero Z 1  to be slightly lower in frequency than pole P 2 . As the load current increases, Idr also increases pushing pole P 2  farther and farther out in frequency. Simultaneously, zero Z 1  is pushed farther and farther out in frequency due to the same dependence on the square root of load current (ILoad). 
         [0036]    Using the compensation method of the present invention, it is not necessary to exert strict limitations on the capacitance and ESR of the output capacitor any longer to achieve a stable LDO (low drop-out) regulator. In a typical design, a stand-by LDO regulator with an output=3.3V and drop-out voltage=0.6V@170 mA can stay stable under the following extreme conditions:
   i) Capacitance of the output capacitor is greater than 0.1 uF, and   ii) ESR of the output capacitor is less than 30 ohm.   
 
         [0039]    The compensation circuit and method of the present invention has certain advantages over the prior art. An LDO regulator using the present compensation method has good stability even with a very small output capacitor, and does not require an output capacitor with small ESR. Thus, there is almost no limitation on the capacitor type that can be used. The circuit and method of the present invention decreases quiescent current (Iq) of the regulator significantly, especially under heavy load conditions. The compensated LDO regulator of the present invention is ideally suited for use in automotive applications, but it is apparent to those skilled in the art that the regulator can be used in a wide range of other applications as well. 
         [0040]    For an example design using a particular semiconductor process, the following values are taken for the components referred to in  FIG. 2 :
   R 1 =1.2 Mohm, R 2 =665 kohm, Rc=10 kohm, Rp=250 kohm,   R 3 =250 kohm, R 4 =5.5 kohm,   M 1 =100 u/3μ, M 2 =150 u/3μ, M 3 =60μ/2.6μ,   M 6 =30 mm/2.6μ, M 7 =3×“8.4μ/2.6μ” (in series)   M 8 =5 u/2μ M 9 =5 u/2μ   Cc=9 pF Ilow=4 μA.   
 
         [0047]    Transistors M 1 /M 2 /M 8 /M 9  are the same type of NMOS transistor with uCox/2=34 uA/V 2 . Transistors M 3 /M 6 /M 7  are the same type of PMOS transistor with R on *Area=0.87 ohm@Vgs=5V The current source Ilow is included to provide better stability during no-load or low load operating conditions. 
         [0048]    The following results shown in  FIGS. 3-9  are from a simulation using a specific semiconductor process model. Simulation results will be different using different component values and different models required for a specific application. It is appreciated by those skilled in the art that different component values and different semiconductor processes can be used in conjunction with the compensation method and circuit of the present invention, while still realizing the stable compensation benefits as described herein. 
         [0049]    Referring now to the plots of  FIG. 3  and  FIG. 4 , both Rzero  302  and Req 2   304  decrease with output load current, but Req 2  decreases slightly faster as shown in the ratio plot  400  of  FIG. 4 . 
         [0050]    Based on simulation results, Ceq=58.5 pF, while Cc=9 pF, and so the ratio  500  of  FIG. 5  shows that zero Z 1  is always lower than pole P 2 , but relatively close to pole P 2  throughout the entire range of the load current. The ratio  500  graph of  FIG. 5  demonstrates the stability of the compensation method of the present invention, which makes designing an LDO regulator easier. 
         [0051]    All of the following  FIGS. 6-9  show the simulated performance of a 3.3V-standby LDO regulator with 0.6V dropout at 170 mA of load current utilizing the present invention. An output load pulse and transient output voltage spikes, as well as regulated output voltage are shown. 
         [0052]      FIG. 6  shows the regulated output voltage  602  with the load transient spikes, and an output load pulse  604 , with an output capacitor of 0.1 μF and an ESR of zero ohms, both with respect to time. 
         [0053]      FIG. 7  shows the regulated output voltage  702  with the load transient spikes, and an output load pulse  704 , with an output capacitor of 0.1 μF and an ESR of 30 ohms, both with respect to time. 
         [0054]      FIG. 8  shows the regulated output voltage  802  with the load transient spikes, and an output load pulse  804 , with an output capacitor of 100 μF and an ESR of zero ohms, both with respect to time. 
         [0055]      FIG. 9  shows the regulated output voltage  902  with the load transient spikes, and an output load pulse  904 , with an output capacitor of 100 μF and an ESR of 30 ohms, both with respect to time. 
         [0056]    In the regulator loop of the circuit of the present invention as shown in  FIG. 2 , there are a total of three poles and two zeros that are the main contribution to improved stability as before. However, zero Z 1  is determined by a variable resistance as described above, times capacitance Cc. In the circuit of the present invention, zero Z 1  varies with the load current, whereas in the prior art zero Z 1  is fixed. In the circuit of the present invention zero Z 1  and pole P 2  remain close to each other in frequency for the entire range of load current range. Effectively, zero Z 1  cancels pole P 2  and so there are only two remaining poles P 0  and P 1 , one remaining zero Z 0 . This, in turn, makes the loop stability design of the regulator easier. 
         [0057]    While there have been described above the principles of the present invention in conjunction with specific memory architectures and methods of operation, it is to be clearly understood that the foregoing description is made only by way of example and not as a limitation to the scope of the invention. Particularly, it is recognized that the teachings of the foregoing disclosure will suggest other modifications to those persons skilled in the relevant art. Such modifications may involve other features which are already known per se and which may be used instead of or in addition to features already described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure herein also includes any novel feature or any novel combination of features disclosed either explicitly or implicitly or any generalization or modification thereof which would be apparent to persons skilled in the relevant art, whether or not such relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as confronted by the present invention. The applicant hereby reserves the right to formulate new claims to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.