Abstract:
Methods and systems for conditioning wireline communications to remove intersymbol interference are provided that used adaptive equalization. The method and systems include using a digital finite state machine to control two feedback loops that adjust the gain and power of the input signal relative to a supplied reference. The eye height of the input signal is conditioned by a gain feedback loop so that signal equalization can be performed in a known state. The digital finite state machine allows the loops to be flexibly run in sequence or concurrently. The adaptation functions can be shut off when adequate signal equalization has been achieve, thus saving power.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure relates to the field of signal conditioning in high-speed wireline communications. More specifically, the present disclosure relates to systems and methods for using adaptive equalization control to condition signals for high-speed wireline communications. 
         [0003]    2. Discussion of Related Art 
         [0004]    Whenever electrical signals are transmitted over wires, the integrity of the signal can be degraded. The signal that was originally placed on the wire will have some differences from the signal that is received at the other end of the wire. This is due to inherent physical properties of the wire. 
         [0005]    In a digital signal, the frequency components of a bit of data can spread apart as the higher and lower frequency components travel at slightly different rates through the wireline. This can cause intersymbol interference (ISI) in which one bit can interfere with the preceding and subsequent bits. In recent years, as data has been required to travel with higher data rates over longer distances of wirelines, the problems of maintaining signal integrity and minimizing ISI have increased. 
         [0006]    Several techniques have been developed to deal with ISI. Some of these techniques include, for example, error correction coding, separating signals in time, and using an equalizer. Equalizers can be used in an effort to correct for the distortions caused by the non-uniform frequency response of the wireline. However, the equalizers that have been developed to date have not been satisfactory in every respect. 
       SUMMARY 
       [0007]    Embodiments of a receiver are provided herein for facilitating adaptive equalization control. The receiver includes a variable gain amplifier configured to receive an input signal at a signal input, an equalizer peaking amplifier coupled to an output of the variable gain amplifier, a regulated amplifier coupled to an output of the equalizer peaking amplifier; and an adaptation block coupled to the variable gain amplifier, the equalizer peaking amplifier, and the regulated amplifier. 
         [0008]    Embodiments of a method for conditioning transmissions in a high-speed wireline communications are also provided. Such a method may include receiving an input signal at a voltage gain amplifier, providing a reference voltage level. The method may include steps of controlling a voltage gain amplifier with a digital finite state machine, the digital finite state machine controlling the voltage gain amplifier based at least in part on the reference voltage level, and the voltage gain amplifier modifying the input signal; and controlling an equalizer peaking amplifier with a digital finite state machine, the digital finite state machine controlling the equalizer peaking amplifier based at least in part on the reference voltage level, the equalizer peaking amplifier modifying the input signal. In the method, controlling the voltage gain amplifier and controlling the equalizer peaking amplifier are performed to equalize the input signal. 
         [0009]    Additionally, embodiments of another method for conditioning transmissions in a high-speed wireline communications are provided. The embodiments may include receiving an input signal at a voltage gain amplifier, controlling the voltage gain amplifier so as to condition an eye height of the input signal to match a reference level, and tuning an equalizer peaking amplifier to control equalizer peaking of the input signal after the input signal has been matched to the reference level. 
         [0010]    These and other embodiments will be described in further detail below with respect to the following figures. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  illustrates a system for facilitating adaptive equalization control at a wireline receiver. 
           [0012]      FIG. 2  illustrates a receiver for facilitating adaptive equalization control at a wireline receiver depicting more detail of the adaptation block. 
           [0013]      FIG. 3  illustrates a flowchart illustrating a method for conditioning high-speed wireline signals by using adaptive equalization. 
           [0014]      FIG. 4  illustrates a flowchart illustrating an additional method for conditioning high-speed wireline signals by using adaptive equalization. 
           [0015]      FIGS. 5A and 5B  illustrate an embodiment of a Finite State Machine that can be utilized in the receiver of  FIG. 2 . 
           [0016]      FIGS. 6A ,  6 B, and  6 C illustrate an example of operation of a receiver as is illustrated in  FIG. 2 . 
           [0017]      FIGS. 7A ,  7 B, and  7 C illustrate another example of operation of a receiver as is illustrated in  FIG. 2 . 
       
    
    
       [0018]    In the drawings, elements having the same designation have the same or similar functions. 
       DETAILED DESCRIPTION 
       [0019]      FIG. 1  shows a diagram of an adaptively equalized receiver  100  for conditioning high-speed wireline communication signals according to some embodiments of the present invention. Receiver  100  includes a variable gain amplifier  102  that may be configured to receive a data input from a high-speed wireline, for example a Universal Serial Bus (USB) connection or other high speed connection. The output signal from variable gain amplifier  102  may be coupled to an equalizer peaking amplifier  104 . The output signal from equalizer peaking amplifier  104  may be coupled to a regulated amplifier  106 . Regulated amplifier  106  may have an output signal that is routed to particular destinations. 
         [0020]      FIG. 1  also depicts an adaptation block  108 . Adaptation block  108  may be coupled to receive signals from equalizer peaking amplifier  104  and the data output of regulated amplifier  106 . Adaptation block  108  may also be coupled to transmit control signals to variable gain amplifier  102 , equalizer peaking amplifier  104 , and regulated amplifier  106 . While  FIG. 1  depicts the signal path as showing variable gain amplifier  102  first, equalizer peaking amplifier  104  second, and regulated amplifier  106  third in the data path, the blocks may be arranged in any order without departing from the scope of the invention. 
         [0021]    In operation, embodiments of receiver  100  as depicted in  FIG. 1  may receive an incoming high-speed communications signal at the input of variable gain amplifier  102 . As indicated, application block  108  may be coupled to variable gain amplifier  102  so that application block  108  may send a signal to adjust the gain of variable gain amplifier  102 . This adjustment may be based on a feedback control loop that includes a generated reference signal. The output of the variable gain amplifier  102  may be adjusted by equalizer peaking amplifier  104  so as to substantially restore the original frequency components of the signal to that of the originally sent signal. As such, Equalizing peaking amplifier  104  may include a series of one or more individual peaking amplifiers such as that described in U.S. Pat. No. 8,081,031 to Han Bi, issued on Dec. 20, 2011, which is herein incorporated by reference in its entirety. Each of the equalizing peak amplifiers may amplify different ranges of signal frequencies. 
         [0022]    As shown in the embodiment of  FIG. 1 , equalizer peaking amplifier  104  receives control signals from adaption block  108 . The control signals from adaption block  108  may be adapted to control the amplification provided by each of the serially coupled peak amplifiers. Therefore, based on the control signal from adaptation block  108 , equalizer peaking amplifier  104  may adjust the frequency response correction applied to data input signal. The adjustments made to equalizer peaking amplifier  104  may be based on all frequencies contained in the received data signals, and not on a subset of signal frequencies. The adjustment may be based on a feedback loop which includes the output of regulated amplifier  106 . 
         [0023]      FIG. 2  depicts an embodiment of adaptively equalized receiver  100 , which in some embodiments improves signal integrity in high-speed wireline communications. As shown in  FIG. 2  variable gain amplifier  102  is coupled to receive the data input signal, an equalizer peaking amplifier  104  is coupled to receive the signal from amplifier  102 , and a regulated amplifier  106  is coupled to receive the signal from equalizer peak amplifier  104 . Each of variable gain amplifier  102 , equalizer peaking amplifier  104 , and regulated amplifier  106  may be coupled to receive control signals from adaptation block  108 . 
         [0024]    As shown in  FIG. 2 , adaptive block  108  includes a digital finite state machine (FSM)  202 . FSM  202  may be configured to receive differential error control signals and to output control signals to variable gain amplifier  102 , equalizer peaking amplifier  104 , and regulated amplifier  106 . FSM  202  may output a gain control signal to variable gain amplifier  102 , the gain control signal may adjust, by an increase or decrease, the gain applied by variable gain amplifier  102  to the data input signal. The gain of variable gain amplifier  102  may be increased or decreased to cause an eye height of the data input signal to be within a desired range or at a desired level. As is well known, an eye pattern or eye diagram is a diagram of a data transmission signal formed on an oscilloscope display where the digital signal is applied to the vertical input and the data rate triggers the horizontal sweep. The variable gain amplifier  102  may thereby control the low frequency swing of the data input signal by adjusting the eye height of the data input signal. 
         [0025]    FSM  202  may also output a peaking control signal to equalizer peaking amplifier  104 . The peaking control signal may adjust the amplification of certain frequency ranges present in the input signal. This can, for example, be accomplished by adjusting individual peak amplifiers that are serially coupled in equalizer peak amplifier  104 . Thus, the equalizer peaking amplifier may adjust components in particular frequency ranges, for example the high frequency components of the data input signal. 
         [0026]    As illustrated in  FIG. 2 , a reference voltage is input to a reference generator  204 . Further, the output signal from equalizer peaking amplifier  104  is input to peak detector  206 . Reference generator  204  generates reference peak levels while peak detector  206  determines the peak levels of the signal from equalizing peak amplifier  104 . A peak level error signal  210  is determined by convoluting the signals from reference generator  204  and peak detector  206  in combiner  214 . The peak level error signal  210  is then input to finite state machine  202 . In some embodiments, peak level error signal  210  includes a digital up or down signal, instructing FSM  202  to increase or decrease gain. 
         [0027]    As is further shown, the output signal from equalizer peaking amplifier  104  and the data output signal are input to power rectifier  208 . Power rectifier  208  rectifies those signals to determine the average power of the signal from equalizer peaking amplifier  104  and the data output signal. Those two signals are convoluted in combiner  214  to generate a peaking error signal  212 . Peaking error signal  212  may also be a digital up or down signal indicating to FSM  202  either to increase or decrease the overall gain of variable gain amplifier  102  and equalizer peaking amplifier  104 . 
         [0028]    As indicated above, FSM  202  receives the peak level error signal  210  and the power output error signal  212  and determines the gain and peaking control signals to variable gain amplifier  102  and equalizer peaking amplifier  104 . FSM  202  may produce the control signals as part of two feedback loops. In a gain control loop, the signal output from variable gain amplifier  102  may be received and altered by equalizer peaking amplifier  104 . The resulting equalized signal may be routed to a peak detector  204 . Peak detector  204  may be configured to compare the eye height of the equalized signal with the level of a reference signal. 
         [0029]    Therefore, as illustrated in  FIG. 2 , receiver  100  includes an automatic peak boosting loop and an automatic gain control. In this control loop, after the equalized signal leaves equalizer peaking amplifier  104  it may be received at the input of regulated amplifier  106 . Regulated amplifier  106  may also receive the same reference voltage that is applied to reference generator  206  in the automatic gain control loop. The reference voltage may cause the output of regulated amplifier  106  to have the same swing value as the output of reference generator  206 . The output of regulated amplifier  106  may be the data output of system  200 . Additionally, the output of regulated amplifier  106 , the regulated signal, may be sent to power rectifier  208 , which may also receive the equalized signal from the output of equalizer peaking amplifier  104 . Power rectifier  208  may detect a power difference between the equalized signal and the regulated signal. In some embodiments power rectifier  208  may include two separate power rectifiers, one for each of the two signals. The power difference from combiner  216  may be sent on as a peaking error signal. The peaking error signal may be quantized before transmission to FSM  202 . FSM  202  may use the peaking error signal to determine a peaking control signal, which is then sent to equalizer peaking amplifier  104 . The peaking control signal may cause equalizer peaking amplifier  104  to adjust so as to control the power of the output signal from regulated amplifier  106 . This may be accomplished by selectively increasing or decreasing the magnitude of certain frequency components in the signal. This may complete the automatic peak boosting loop. 
         [0030]    In both of the above-described loops, FSM  202  may use one of several locking algorithms in communicating with the variable gain amplifier  102  and the equalizer peaking amplifier  104 . FSM  202  may use a locking algorithm to ensure proper communication with variable gain amplifier  102  and equalizer peaking amplifier  104 . In some embodiments, the gain control signal and the peaking control signal may be multi-bit (e.g., 3 bit) signals, or may be a series of multi-bit signals. In some embodiments, the automatic gain control loop (the AGC loop) may operate first, while the automatic peak boosting loop (the boost loop) may operate second. In other embodiments, both the AGC loop and the boost loop may operate concurrently. 
         [0031]    As indicated, adaptation block  108  may include a reference voltage. Additionally, the adaptation block may include a clock signal, a configuration signal, and a control signal. These three signals may be included as inputs to FSM  202 . In some embodiments, the clock, configuration, and control signals may be the same for the AGC loop and the boost loop. In other embodiments, the clock, configuration, and control signals may be programmable independently for the automatic gain control and automatic peak boosting loops. This may allow greater flexibility to optimize performance of each control loop. 
         [0032]    When the eye height of the corrected signal matches that produced by reference generator  206  and the equalized signal power matches the regulated signal power, adaptation block  108  may turn off to decrease the power consumption of the adaptive equalization system. However, the gain control and peaking control signals may be maintained even when adaptation block  108  is shut off. 
         [0033]      FIG. 3  depicts a flowchart for a method  300  for conditioning signals transmitted in high-speed wireline communications systems by using adaptive equalization control. Method  300  may be implemented using an adaptive equalization system such as system  100  or  200  as described above. Those systems will be used herein to provide details regarding the operation of method  300 . However, method  300  should not be understood as limited to implementation in those particular systems. 
         [0034]    Method  300  may begin in step  302 , when the system receives an input signal that may need equalization due to channel-loss introduced intersymbol interference. Step  304  includes providing a reference voltage to the system. Steps  306  and  308  may be performed by finite state machine  202 . So, in step  306 , the receiver  100  may control a voltage gain amplifier using finite state machine  202 . Finite state machine  202  may exert control based in part on the provided reference voltage to modify the eye height of the input signal received by the system. In step  308 , the system may control an equalizer peaking amplifier based in part on the reference voltage to modify the power of the input signal. The system may control the equalizer peaking amplifier with the same finite state machine as used in step  308 . 
         [0035]    Using receiver  100  as a non-limiting example, method  300  may begin when a voltage gain amplifier  102  receives an input signal at its input (step  302 ). The input signal may exhibit a degree of intersymbol interference to be corrected. Adaptation block  108  may be provided with a reference voltage (step  304 ). The reference voltage may be coupled to a reference generator  206  that may generate a reference signal. The reference voltage may also be coupled to a regulated amplifier  106  to regulate its output swing. 
         [0036]    Reference  100  may exert control of voltage gain amplifier  102 . This may be accomplished through adjustments to an automatic gain control loop. The loop may begin at the output of voltage gain amplifier  102  which may be routed through an equalizer peaking amplifier  104 , producing an equalized signal. A peak detector  206  may detect the difference between an eye height of the equalized signal and the reference voltage. The difference may be quantized to produce a gain error signal that can be transmitted to an FSM  202 . FSM  202  may determine an appropriate gain control signal to transmit to variable gain amplifier  102 , based on the gain error signal (step  306 ). 
         [0037]    System  200  may also exert control of equalizer peaking amplifier  104 . This may be accomplished through adjustments to an automatic peak boosting loop. The loop may begin at the output of equalizer peaking amplifier  104  with the equalized signal. The equalized signal may be routed to a regulated amplifier  108  and a power rectifier  208 . The output of regulated amplifier  108  may also be routed to power rectifier  208 , where power rectifier  208  may detect a difference between the regulated and the equalized signals. The difference is quantized and provided to the FSM  202 . FSM  202  may then use the quantized difference to determine a peaking control signal, which FSM  202  may transmit to equalizer peaking amplifier  104 . Equalizer peaking amplifier  104  may be adjusted by the peaking control signal to minimize the power difference between the equalized and regulated signals (step  308 ). 
         [0038]      FIG. 4  depicts a flowchart of a method  400  for conditioning signals transmitted in high-speed wireline communications systems by using adaptive equalization control. As was the case for  FIG. 3 , method  400  may be implemented using an adaptive equalization system such as in receiver  100 , as described above. While those systems may be used to provide details regarding the operation of method  400 , the explanatory use of systems  100  of  200  herein should not be understood as limiting method  400  to any particular system. 
         [0039]    Method  400  may begin in step  402 , when an adaptive equalization system receives an input signal at a voltage gain amplifier. In step  404 , a peak detector may compare an eye height of the input signal to a generated reference signal. The difference between the two signals may be to create a gain error signal. The gain error signal may be used to provide feedback to the voltage gain amplifier. The system may adjust the voltage gain amplifier so that the eye height of the input signal matches the generated reference signal, in step  406 . 
         [0040]    Method  400  may continue in step  408 , when a power rectifier may detect a power difference between an equalized signal with a regulated signal. The difference between the equalized signal and the regulated signal may be used to create a peaking error signal. The peaking error signal may be used by the system to provide feedback to an equalizer peaking amplifier. The equalizer peaking amplifier  104  may be tuned so that the power of the equalized signal matches the power of the regulated signal, in step  410 . The tuning of the equalizer peaking amplifier may be performed after the eye height of the input signal has been matched to the reference level. 
         [0041]    Using adaptive equalization system  200  as an example, method  400  may begin when an input signal transmitted over a high-speed wireline is received by a voltage gain amplifier  102  (Step  402 ). The signal may be altered and transmitted to an equalizer peaking amplifier  104 . After the signal has passed through equalizer peaking amplifier  104  it may be transmitted to a peak detector  204 . Peak detector  204  may compare the eye height of the input signal to a reference signal generated from a reference voltage by a reference generator  206 . The comparison performed by peak detector  204  may provide a gain error signal. In some embodiments, the gain error signal may be quantized and transmitted to a digital finite state machine, such as FSM  202 . The gain error signal may be used to produce a gain control signal. In turn, the gain control signal may be transmitted to variable gain amplifier  102  and may adjust it so that the eye height of the input signal matches the generated reference signal (Step  406 ). 
         [0042]    The output of equalizer peaking amplifier  104  may also be routed to a power rectifier  208 . Power rectifier  208  may also receive the output of a regulated amplifier  106 . Power rectifier  208  may compare the power of the equalized signal with the power of the regulated signal to determine a power difference (Step  408 ). This power difference may serve as a peaking error signal (Step  408 ). The peaking error signal may, in some embodiments, then be quantized and transmitted to FSM  202 . FSM  202  may generate a peaking control signal from the peaking error signal. The peaking control signal may be transmitted to equalizer peaking amplifier  104 . Equalizer peaking amplifier  104  may respond by adjusting so that the power of the equalized signal matches the power of the regulated signal (Step  410 ). 
         [0043]    After equalizer peaking amplifier  104  has been properly tuned, the eye height of the input signal will match the reference level, and the power of the equalized and regulated signals will match as well. In these conditions, adaptation block  108  as seen in  FIGS. 1 and 2  may shut off to conserve power. In such an instance, the gain control and peaking control signals may be maintained so that the state of adaptive equalization system continues to equalize the input signal. In those embodiments of method  400  that include quantizing and transmission to FSM  202 , the gain and peaking control signals may be digital signals of multiple-bit word lengths transmitted in parallel, or a series thereof. 
         [0044]      FIGS. 5A and 5B  illustrate an embodiment of a loop that is operated by FSM  202 . In general, FSM  202  includes two control logic loops. One loop, which may be referred to as an automatic gain control loop, receives signal  210  and outputs a gain control signal to variable gain amplifier  102 . The other loop, also referred to as the boost loop, receives signal  212  and outputs a gain control signal to equalizer peaking amplifier  104 . In some embodiments, signals  210  and  212  are digital signals, either 1 or 0. Signal  210 , which is the input to the AGC loop, is 1 if the signal from peak detector  206  is greater than the signal from reference generator  204 , and 0 if the signal from peak detector  206  is less than the signal from reference generator  204 . Similarly, signal  212 , which is the input signal for the boost loop, is 1 if the regulated signal from regulated amplifier  106  is greater than the regulated signal from equalizer peaking amplifier  104  and 0 if the regulated signal from equalizer peaking amplifier  104  is greater than the regulated signal from regulated amplifier  106 . 
         [0045]    The control algorithm for the AGC loop and the Boost loop are substantially the same. In some embodiments, the algorithm executed by FSM  202  includes AGC and Boost initial gains and the two loops working in sequence. In some embodiments, the two loops operate simultaneously.  FIG. 6C  illustrates the AGC loop and the Boost loop working in sequence.  FIG. 7C  illustrates the AGC loop and the Boost loop working simultaneously. FSM  202  may include a processor that executes code to perform the control algorithm. Alternatively, FSM  202  may include hardware that performs the steps of the control algorithm. 
         [0046]      FIG. 5A  illustrates an embodiment of a control algorithm  500  that can be executed by FSM  202 . Control algorithm  500  can represent either the AGC loop or the Boost loop of FSM  202 . As shown in  FIG. 5A , control algorithm  500  begins at start  502 . In start  502  the loop is initialized by loading an initial gain value and setting a cycle number to zero. Control algorithm  500  then proceeds to step  504  where the input signal (signal  210  or signal  212 ) is sampled. In some embodiments, step  504  is performed every clock cycle so that an input signal is sampled every clock cycle. In step  506 , if the input signal is 1, algorithm  500  proceeds to step  508 . If the input signal is 0, algorithm  500  proceeds to step  510 . 
         [0047]    In step  508 , the algorithm  500  determines if the gain signal is saturated at a high level. If not, then algorithm  500  proceeds to step  512  where the gain signal is incremented by 1. If step  508  determines that the gain is saturated, then algorithm  500  proceeds to step  514  where the gain is not changed. 
         [0048]    In step  510 , algorithm  500  determines if the gain is saturated at a low level. If not, then algorithm  500  proceeds to step  518  where the gain is decremented by 1. If the gain is saturated, the algorithm  500  proceeds to step  516  where the gain is not changed. 
         [0049]    From steps  512 ,  514 ,  516 , or  518 , algorithm proceeds to step  520 . In step  520 , algorithm  500  makes a loop lock condition judgment. Algorithm  500  saves previous values of the input signal (for example the last six values—last continuous five values and the current value). In some embodiments, if six values are kept, and the last six values are equal to “101010” or “010101” or “100110” or “100101” or “101001” or “011001” or “011010” or “010110” and the current cycle number, which is incremented on each clock cycle, is larger than a set value (for example 12, but any number can be used) then the loop lock condition is considered to be met. 
         [0050]      FIG. 5B  illustrates the loop lock condition. As shown in  FIG. 5B , if the gain remains in a small range (e.g., from g−1 to g+1, where g is a constant) in a multiple of clock cycles, for example six clock cycles, then the loop has converged. If the condition occurs after a larger number of clock cycles, for example 12 clock cycles, then the loop lock may be more reliable. Therefore, in loop  520 , algorithm  500  checks for the loop lock condition described above and that the number of cycles has exceed a minimum number before declaring the condition. 
         [0051]    If, in step  520 , algorithm  500  determines that the loop lock condition is satisfied, then algorithm  520  proceeds to end equalization  524 . In step  524 , an external host may be notified that equalization has ended. The gain is set at its current value for the duration of operation, or until the external host restarts the equalization by returning loop algorithm  500  to start  502 . 
         [0052]    If, in step  520 , algorithm  500  determines that the loop lock condition is not satisfied, then algorithm  500  proceeds to step  522 . In step  522 , if the cycle number has exceed a maximum number, for example 31 cycles, then algorithm  500  “times out” and proceeds to end equalization  524 . Otherwise, algorithm  522  returns to step  504  to sample another input signal. 
         [0053]    In this fashion, loop algorithm  500  quickly cycles and locks onto a gain value. Gain high or low saturation occurs because the gain is a quantized code. Saturation occurs to prevent the gain code from overflow or underflow conditions. When the host starts the adaptive equalization of loop algorithm  500  depends on which application field is utilizing the equalization. For example, a USB3.0 host starts algorithm  500  when a super-speed signal (5 Gbps signal) is detected. Generally, the first super-speed signal will be training symbols transmitted directly after link initialization. If the USB 3.0 device is removed and re-connected, the host will restart loop algorithm  500 . 
         [0054]    In general, FSM  202  may include any number of loops such as loop algorithm  500 . As shown in  FIG. 2 , there are the AGC loop providing a gain signal to variable gain amplifier  102  and a boost loop providing a gain signal to equalizer peaking amplifier  104 . 
         [0055]      FIGS. 6A ,  6 B, and  6 C illustrate an example of operation of some embodiments of receiver  100  according to the present invention.  FIG. 6A  illustrates an eye diagram of a data input signal to receiver  100 .  FIG. 6B  illustrates an eye diagram of a data output signal from receiver  100 . As can be seen in  FIG. 6B , much of the intersymbol interference has been removed from the data signal.  FIG. 6C  illustrates operation of error signals  210  and  212 . As illustrated in  FIG. 5C , the automatic gain control (AGC) can be on or off. When AGC is on, signal  210  provides up or down control signals to FSM  202 . Further, Automatic peaking boost control can be on or off. When boost is on, signal  212  provides up or down control signals to FSM  202 . 
         [0056]      FIGS. 7A ,  7 B, and  7 C illustrate another example of operation of some embodiments of receiver  100  according to the present invention.  FIG. 7A  illustrates an eye diagram of a data input signal to receiver  100 .  FIG. 7B  illustrates an eye diagram of a data output signal from receiver  100 . As can be seen in  FIG. 7B , much of the intersymbol interference has been removed from the data signal.  FIG. 7C  illustrates operation of error signals  210  and  212 . As illustrated in  FIG. 7C , the automatic gain control (AGC) can be on or off. When AGC is on, signal  210  provides up or down control signals to FSM  202 . Further, Automatic peaking boost control can be on or off. When boost is on, signal  212  provides up or down control signals to FSM  202 . 
         [0057]    In the detailed description above, specific details have been set forth describing certain embodiments. It will be apparent, however, to one skilled in the art that the disclosed embodiments may be practiced without some or all of these specific details. The specific embodiments presented are meant to be illustrative, but not limiting. One skilled in the art may realize other material that, although not specifically described herein, is still within the scope and spirit of this disclosure.