Abstract:
A semiconductor wafer manufacturing method comprising the steps of preparing first and second semiconductor wafers, bonding a main surface of said second semiconductor wafer to a main surface of said first semiconductor wafer, thinning said first semiconductor wafer, implanting oxygen ions from said first semiconductor wafer side into a neighborhood of a part where said first and second semiconductor wafers are bonded to each other, and forming the portion implanted with the oxygen ions into an oxide film layer by a thermal treatment.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is a divisional application of U.S. application Ser. No. 11/223,970, filed Sep. 13, 2005, which is a divisional application of U.S. application Ser. No. 10/461,352, filed Jun. 16, 2003, and claims priority to Japanese Patent Application 2002-285160 filed Sep. 30, 2002. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a semiconductor wafer and a manufacturing method thereof.  
         [0004]     2. Description of the Background Art  
         [0005]     In a conventional SOI (Silicon On Insulator or Semiconductor On Insulator) wafer, an oxide film layer resides on one main surface of a supporting substrate wafer made of, e.g. a silicon substrate, and an SOI layer resides on the top surface of the oxide film layer. Such SOI and oxide film layers are formed by bonding to the supporting substrate wafer an SOI layer wafer that has a silicon substrate with an oxide film formed on its main surface and then removing part of it.  
         [0006]     After the supporting substrate wafer and the SOI layer wafer are bonded together, an unwanted portion of the SOI layer wafer is removed by adopting a method such as SMART CUT® or ELTRAN®; refer to Patent Document 1 shown below.  
         [0007]     When a MOS (Metal Oxide Semiconductor) transistor is formed in the SOI layer, it is arranged so that its channel direction is parallel to a &lt;100&gt; crystal direction of the SOI layer, for example. It is known that arranging the channel direction in parallel with &lt;100&gt; crystal direction enhances the current driving capability of the P-channel MOS transistor by about 15 percent and also reduces the short-channel effect.  
         [0008]     It is thought that the current driving capability is enhanced because the hole mobility in &lt;100&gt; crystal direction is larger than that in &lt;110&gt; crystal direction, and that the short-channel effect is reduced because the value of the boron diffusion coefficient in &lt;100&gt; crystal direction is smaller than that in &lt;110&gt; crystal direction.  
         [0009]     Now, with SOI wafers, the SOI layer wafer, in which SOI and oxide film layers are formed, may be bonded to the supporting substrate wafer with their crystal directions shifted at 450 (or 135°) with respect to each other. Specifically, the two wafers are bonded together in such a way that a &lt;100&gt; crystal direction of the SOI layer and a &lt;110&gt; crystal direction of the supporting substrate wafer coincide with each other. The reason is shown below.  
         [0010]     (100) wafers cleave along {110} crystal planes. Accordingly, when the SOI layer wafer and the supporting substrate wafer are bonded together so that the &lt;100&gt; crystal direction of the former coincides with the &lt;110&gt; crystal direction of the latter, the wafer can be cleaved, for experiments and studies, along {110} cleavage planes of the supporting substrate wafer  1  that forms a large part of the wafer thickness. On the other hand, in the SOI layer whose crystal direction is shifted, an MOS transistor can be formed so that its channel direction is parallel with a &lt;100&gt; crystal direction.  
         [0011]     Thus, when cleaved, the supporting substrate wafer  1  breaks along &lt;110&gt; crystal direction, while the SOI layer breaks along &lt;100&gt; crystal direction. In this way, bonding the two wafers with their crystal directions shifted from each other provides the advantage that a section along the MOS transistor channel direction can be easily exposed.  
         [0012]     The following list shows prior art reference information related to the present invention:  
         [0013]     Patent Document 1: Japanese Patent Application Laid-Open No. 2002-134374,  
         [0014]     Patent Document 2: Japanese Patent Application Laid-Open No. 9-153603 (1997), and  
         [0015]     Non-Patent Publication 1: G. Scott et al., “NMOS Drive Current Reduction Caused by Transistor Layout and Trench Isolation Induced Stress,” (US), IEDM, 1999.  
         [0016]     A conventional SOI wafer is manufactured by a method shown below, for example.  
         [0017]     First, an SOI layer wafer and a supporting substrate wafer are prepared, both of which are a (100) wafer having a (100) plane as a main surface. Next, a notch (or an orientation flat) is formed at a &lt;100&gt; crystal direction edge of the SOI layer wafer and a notch (or an orientation flat) is formed at a &lt;110&gt; crystal direction edge of the supporting substrate wafer. Then, the two substrates are bonded together in such a way that the &lt;100&gt; crystal direction of the SOI layer and the &lt;110&gt; crystal direction of the supporting substrate wafer coincide with each other.  
         [0018]     In this bonding process, the two wafers are bonded so that the notch of the supporting substrate wafer and the notch of the SOI layer wafer coincide with each other. However, when the two wafers are positioned by utilizing these notches only, the SOI layer &lt;100&gt; crystal direction and the supporting substrate wafer &lt;110&gt; crystal direction may not be precisely aligned.  
         [0019]     With such a positioning error between wafers, the MOS transistor channel direction cannot be precisely aligned with the SOI layer &lt;100&gt; crystal direction and a deviation is caused between the two. This is because MOS transistors are formed on the basis of the position of the supporting substrate wafer.  
         [0020]     Then the current driving capability of the MOS transistors cannot be enhanced satisfactorily. Furthermore, electric characteristic variations will occur among MOS transistors formed on the surfaces of different SOI wafers.  
       SUMMARY OF THE INVENTION  
       [0021]     Accordingly, an object of the present invention is to provide a semiconductor wafer and a manufacturing method thereof in which the current driving capability of a MOS transistor can be sufficiently enhanced.  
         [0022]     According to a first aspect of the present invention, a semiconductor wafer includes a first semiconductor wafer and a second semiconductor wafer.  
         [0023]     The first semiconductor wafer has a plurality of cuts formed at edge portions in crystal directions, and the second semiconductor wafer has a cut formed at an edge portion in a crystal direction.  
         [0024]     One of the plurality of cuts of the first semiconductor wafer and the cut of the second semiconductor wafer are formed in different crystal directions. The first and second semiconductor wafers are bonded to each other with said one of the plurality of cuts of the first semiconductor wafer and the cut of the second semiconductor wafer coinciding with each other.  
         [0025]     The first semiconductor wafer has a plurality of cuts and the first and second semiconductor wafers are bonded together in such a way that one of the plurality of cuts of the first semiconductor wafer and the cut of the second semiconductor wafer coincide with each other. That one of the plurality of cuts of the first semiconductor wafer and the cut of the second semiconductor wafer are positioned in different crystal directions. Thus, when the two wafers are bonded together using the coinciding cuts for positioning, another cut of the first semiconductor wafer can be engaged with a guide portion of the semiconductor wafer manufacturing apparatus to prevent positioning error due to relative turn between the wafers. This allows the two wafers to be highly precisely positioned. Thus the semiconductor wafer can be easily cleaved so that a section along MOS transistor channel direction is exposed, and a MOS transistor having a remarkably enhanced current driving capability can be formed on the semiconductor wafer.  
         [0026]     According to a second aspect of the present invention, a semiconductor wafer manufacturing method includes the following steps (a) to (d). In the step (a), first and second semiconductor wafers are prepared. In the step (b), a main surface of the second semiconductor wafer is bonded to a main surface of the first semiconductor wafer. In the step (c), oxygen ions are implanted from the first semiconductor wafer side into a neighborhood of a part where the first and second semiconductor wafer are bonded to each other. In the step (d), the portion implanted with the oxygen ions is formed into an oxide film layer by a thermal treatment.  
         [0027]     After the first and second semiconductor wafers are bonded together, oxygen ions are implanted and the oxygen-ion-implanted portion is processed into an oxide film layer through a thermal treatment. Thus, by bonding together the first and second semiconductor wafers in crystal directions shifted from each other, it is possible to form an SOI wafer that includes an SOI layer and a supporting substrate having crystal directions shifted with respect to each other. Furthermore, forming the oxide film layer by oxygen ion implantation and thermal process provides an SOI wafer with reduced SOI layer thickness nonuniformity. The reduced SOI layer thickness nonuniformity enhances the current driving capability. Thus the semiconductor wafer can be easily cleaved so that a section along the MOS transistor channel direction is exposed, and an MOS transistor having a remarkably enhanced current driving capability can be formed on the semiconductor wafer.  
         [0028]     According to a third aspect of the present invention, a semiconductor wafer manufacturing method includes the steps (a) to (e). In the step (a), a first semiconductor wafer having a plurality of cuts formed at edge portions in crystal directions is prepared. In the step (b), a second semiconductor wafer having a cut formed at an edge portion in a crystal direction that is different from the crystal direction of one of the plurality of cuts of the first semiconductor wafer is prepared. In the step (c), the first and second semiconductor wafers are bonded to each other while using said one of the plurality of cuts of the first semiconductor wafer and the cut of the second semiconductor wafer in order to position the first and second semiconductor wafers, with another one of the plurality of cuts of the first semiconductor wafer being engaged with a guide portion of a semiconductor wafer manufacturing apparatus. In the step (d), oxygen ions are implanted from the first semiconductor wafer side into a neighborhood of a part where the first and second semiconductor wafers are bonded to each other. In the step (e), the portion implanted with the oxygen ions is formed into an oxide film layer by a thermal treatment.  
         [0029]     After the first and second semiconductor wafers are bonded together, oxygen ions are implanted and the oxygen-ion-implanted portion is processed into an oxide film layer through a thermal treatment. Accordingly, by bonding together the first and second semiconductor wafers in crystal directions shifted from each other, it is possible to form an SOI wafer that includes an SOI layer and a supporting substrate having crystal directions shifted with respect to each other. Furthermore, forming the oxide film layer by oxygen ion implantation and thermal process provides an SOI wafer with reduced SOI layer thickness nonuniformity. The reduced SOI layer thickness nonuniformity enhances the current driving capability. Thus the semiconductor wafer can be easily cleaved so that a section along MOS transistor channel direction is exposed, and a MOS transistor having a remarkably enhanced current driving capability can be formed on the semiconductor wafer. Moreover, in the step (c), the first and second semiconductor wafers are bonded together with another one of the plurality of cuts of the first semiconductor wafer engaged with a guide portion of the semiconductor wafer manufacturing apparatus. This prevents positioning error due to relative turn between the wafers. Thus the two wafers can be highly precisely positioned and a MOS transistor with a sufficiently enhanced current driving capability can be formed on the semiconductor wafer with the two wafers bonded in different crystal directions with respect to each other. Furthermore, electric characteristic variations are less likely to occur among MOS transistors formed on different semiconductor wafers.  
         [0030]     These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0031]      FIG. 1  is the top view of a semiconductor wafer according to a first preferred embodiment;  
         [0032]      FIG. 2  is a cross-sectional view of the semiconductor wafer of the first preferred embodiment;  
         [0033]     FIGS.  3  to  5  are cross-sectional views showing a bonding process for forming the semiconductor wafer of the first preferred embodiment;  
         [0034]      FIG. 6  is the top view of a semiconductor wafer manufacturing apparatus that is used in the semiconductor wafer bonding process of the first preferred embodiment;  
         [0035]      FIG. 7  is a cross-sectional view of the semiconductor wafer manufacturing apparatus used in the semiconductor wafer bonding process of the first preferred embodiment;  
         [0036]      FIG. 8  is a diagram depicting the semiconductor wafer bonding process of the first preferred embodiment; and  
         [0037]     FIGS.  9  to  11  are cross-sectional views showing a semiconductor wafer manufacturing method according to a second preferred embodiment. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
     First Preferred Embodiment  
       [0038]      FIG. 1  is the top view of a semiconductor wafer according to this preferred embodiment. This semiconductor wafer  100  is a (100) wafer that has a (100) plane as its main surface (in  FIG. 1 , the circle containing a point inside represents an arrow that shows the normal direction to the (100) plane.  FIG. 2  shows the II-II section of  FIG. 1 .  
         [0039]     The SOI wafer  100  includes a supporting substrate wafer  1  formed of, e.g. a silicon substrate, an oxide film layer  2  resides on one main surface of the supporting substrate wafer  1 , and an SOI layer  32  resides on top of the oxide film layer  2 . This SOI layer  32  and the oxide film layer  2  are formed by bonding to the supporting substrate wafer  1  an SOI layer wafer that has a silicon substrate and an oxide film formed on its main surface and then removing part of it. While the SOI layer  32  and oxide film layer  2  and the supporting substrate wafer  1  generally have approximately the same diameter, their diameters may be somewhat different from each other depending on the manufacturing process.  
         [0040]     Semiconductor devices, including MOS transistors and interconnections among them, are formed in the surface of the SOI layer  32 . The MOS transistor TR 1  of  FIG. 1  is an example of such a semiconductor device. In the MOS transistor TR 1 , “S” denotes its source, “D” denotes its drain, and “G” denotes its gate.  
         [0041]     This MOS transistor TR 1  is arranged so that its channel direction is parallel with a &lt;100&gt; crystal direction of the S 01  layer  32 .  
         [0042]     In the semiconductor wafer  100 , the supporting substrate wafer  1  has a notch  1   a  formed at an edge portion in a &lt;110&gt; crystal direction and the SOI layer  32  has a &lt;100&gt; crystal direction notch  32   a  and a &lt;110&gt; crystal direction notch  32   b.    
         [0043]     The bonding of the supporting substrate wafer and the SOI layer wafer is now described, where a SMART CUT method is shown by way of example.  
         [0044]     Before bonding, the oxide film layer  2  is formed on a surface of an SOI layer wafer  320  and a crystal defect layer DF is formed by a hydrogen ion implantation IP 2  in a portion deeper than the oxide film layer  2  by the thickness DP 1  of the SOI layer  32  (see  FIG. 3 ).  
         [0045]     Next, as shown in  FIG. 4 , the oxide film layer  2  of the SOI layer wafer  320  is bonded to a main surface of the supporting substrate wafer  1 . In  FIG. 4 , the position of the bonded plane is shown as BD. Note that the supporting substrate wafer  1  and the SOI layer wafer  320  are bonded so that their &lt;100&gt; crystal directions are at an angle of 45° or 135° with respect to each other.  
         [0046]     Next, a thermal treatment is applied to weaken the crystal defect layer DF and the SOI layer wafer  320  is separated at the crystal defect layer DF as shown in  FIG. 5 . At this time, the peripheral portions of the SOI layer wafer  320 , which are not bonded firmly, are also removed.  FIG. 5  shows the dividing plane as DT.  
         [0047]     Then the structure is further heat-treated to increase the bonding strength between the SOI layer  32  and the supporting substrate wafer  1 , and the surface of the SOI layer  32  is lightly polished to remove the residue of the crystal defect layer. The semiconductor wafer  100  shown in  FIGS. 1 and 2  are obtained in this way.  
         [0048]     Next, the process of bonding the supporting substrate wafer  1  and the SOI layer wafer  320  is described in greater detail. The bonding process is performed by using a semiconductor wafer manufacturing apparatus as shown in  FIGS. 6 and 7 , for example.  FIG. 7  shows the VII-VII section of  FIG. 6 .  
         [0049]     This manufacturing apparatus includes a holder HD for holding the supporting substrate wafer  1 , a wafer guide GD 2  used as a guide for positioning the SOI layer wafer  320  to be bonded, and an air pin AP for sucking and holding the semiconductor wafer.  FIG. 6  shows the SOI layer wafer  320  with broken line and clearly depicts the supporting substrate wafer  1  underneath.  
         [0050]     The holder HD has a recess HL having a depth DP 2 , where the supporting substrate wafer  1  is placed. A raised portion HLa is formed at the edge of the recess HL; the supporting substrate wafer  1  is placed there with the raised portion HLa engaged with or fitted in the notch  1   a.    
         [0051]     The wafer guide GD 2  is a guiding member that is situated on the holder HD to surround the recess HL. The raised portion HLa is extended also on the wafer guide GD 2  so that it can be engaged also with the notch  32   a  of the SOI layer wafer  320 .  
         [0052]     The wafer guide GD 2  includes another raised portion GD 1  that can be moved back and forth along the arrow Q shown in the drawings. The raised portion GD 1  can be moved to protrude from the wafer guide GD 2  toward the SOI layer wafer  320 , so that it can be engaged with the &lt;110&gt; direction notch  32   b  of the SOI layer wafer  320 . The raised portion GD 1  and the raised portion HLa are positioned on the wafer guide GD 2  at an angle of 45° with respect to each other. The raised portion GD 1  is situated at a level higher than the supporting substrate wafer  1  placed in the recess HL so that it will not touch the supporting substrate wafer  1  when it is moved.  
         [0053]     When this manufacturing apparatus is used, the raised portion GD 1  is set in the withdrawn position in the wafer guide GD 2 , the supporting substrate wafer  1  is placed in the recess HL of the holder HD, and then the raised portion GD 1  is moved to protrude from the wafer guide GD 2 . Next the SOI layer wafer  320  is carried with the air pin AP and moved down onto the supporting substrate wafer  1  so that the notch  32   a  and the notch  32   b  are engaged respectively with the raised portions HLa and GD 1 , and then the SOI layer wafer  320  and the supporting substrate wafer  1  are bonded together. Subsequently, the raised portion GD 1  is withdrawn into the wafer guide GD 2  and the bonded wafers  1  and  320  are pulled up and taken out with the air pin AP.  
         [0054]     When the depth DP 2  of the recess HL is sized smaller than the thickness of the supporting substrate wafer  1 , the supporting substrate wafer  1  placed in the recess HL slightly protrudes above the surface of the holder HD. In this case, when the raised portion GD 1  is moved to protrude from the wafer guide GD 2 , the bottom of the raised portion GD 1  and the surface of the supporting substrate wafer  1  are not excessively spaced apart, and then the SOI layer wafer  320  can be put down while ensuring the engagement between the notch  32   b  and the raised portion GD 1 .  
         [0055]     During this process of bonding the two wafers, they are positioned so that the notch  1   a  of the supporting substrate wafer  1  and the notch  32   a  of the SOI layer wafer  320  coincide with each other, while the notch  32   b  of the SOI layer wafer  320  is engaged with the raised portion GD 1  that serves as a guide member of the semiconductor wafer manufacturing apparatus.  
         [0056]     Note that “the notch  1   a  and the notch  32   a  coincide with each other” does not mean that their shapes perfectly coincide with each other. For example, the depths of the two notches  1   a  and  32   a  in the wafer radius direction may somewhat differ from each other. Also, the central angles of the two notches  1   a  and  32   a , i.e. the angle between the two sides of each “fan” shape, may somewhat differ from each other. The notch  1   a  and notch  32   a  work as long as their shapes coincide with each other to such an extent that the positioning can be achieved precisely.  
         [0057]     Thus, the raised portion GD 1  engaged with the notch  32   b  limits the turning movement of the SOI layer wafer  320  in the wafer plane direction, which makes it possible to more effectively prevent positioning error due to relative turn between the wafers, than in conventional bonding process where wafers are positioned using only the notches  1   a  and  32   a . Thus the wafers can be highly precisely positioned, so that an MOS transistor TR 1  having a sufficiently enhanced current driving capability can be formed on the semiconductor wafer, with the two wafers positioned in crystal directions shifted from each other. Furthermore, electric characteristic variations are less likely to occur among MOS transistors TR 1  formed on different semiconductor wafers.  
         [0058]     Note that the rest of the semiconductor wafer  100  manufacturing process, other than the bonding process, may be conducted by adopting other method, such as an ELTRAN method, as well as the SMART CUT method.  
         [0059]     This preferred embodiment thus provides a semiconductor wafer and a manufacturing method thereof in which the &lt;100&gt; crystal direction notch  32   a  and the &lt;110&gt; crystal direction notch  32   b  are formed in the SOI layer wafer  320  and the two wafers  1  and  320  are bonded together with the &lt;100&gt; crystal direction notch  32   a  and the &lt;110&gt; crystal direction notch  1   a  of the supporting substrate wafer  1  coinciding with each other (see  FIG. 8 ).  
         [0060]     As shown above, the SOI layer wafer  320  has the notches  32   a  and  32   b . Accordingly, while the supporting substrate wafer  1  and the SOI layer wafer  320  are positioned by utilizing the notch  1   a  of the wafer  1  and the notch  32   a  of the wafer  320 , the notch  32   b  of the SOI layer wafer  320  can be engaged with a guide member of the semiconductor wafer manufacturing apparatus to prevent positioning error between the wafers that would be caused if the wafers turn relative to each other. This allows the two wafers  1  and  320  to be precisely positioned. As a result, it is easy to cleave the semiconductor wafer to expose a section along the MOS transistor channel direction, and it is possible to form an MOS transistor with a sufficiently enhanced current driving capability on the semiconductor wafer.  
         [0061]     While this preferred embodiment has shown an example in which the SOI layer wafer  320  and the supporting substrate wafer  1  are bonded together to form an SOI wafer, the present invention is not limited by this example. That is to say, the present invention can be applied also to bulk wafers that have no oxide film layer  2 . That is, the present invention can be applied to the formation of a bulk wafer in which two bulk wafers are bonded together with their crystal directions shifted from each other, so as to form a bulk wafer whose surface crystal direction differs from that in the deeper portion.  
         [0062]     Also, while this preferred embodiment has shown an example in which notches are used to indicate crystal directions, any cuts of other shapes, such as orientation flats, may be used to show the crystal directions.  
         [0063]     Moreover, while this preferred embodiment has shown an example in which the notches  32   a  and  32   b  are formed in the SOI layer wafer  320  respectively in &lt;100&gt; and &lt;110&gt; crystal directions, the invention is not limited by this example. Notches  32   a  and  32   b  may be formed in directions other than &lt;100&gt; and &lt;110&gt; crystal directions, and they may be positioned in other relationship with respect to each other.  
       Second Preferred Embodiment  
       [0064]     This preferred embodiment shows a method suited to manufacture SOI wafers in which, as shown with the semiconductor wafer  100  of  FIG. 1 , an SOI layer and a supporting substrate wafer are bonded in crystal directions shifted from each other.  
         [0065]     FIGS.  9  to  11  are cross-sectional views showing a semiconductor wafer manufacturing method according to this preferred embodiment.  
         [0066]     First, an SOI layer wafer  321  and a supporting substrate wafer  1 , both of which are a semiconductor wafer that has a (100) plane as a main surface, are prepared and bonded together in such a way that a &lt;100&gt; crystal direction of the SOI layer wafer  321  and a &lt;110&gt; crystal direction of the supporting substrate wafer  1  coincide with each other (see  FIG. 9 ).  FIG. 9  shows the position of the bonded plane as BD. At this stage, no oxide film layer exists on the SOI layer wafer  321  and the supporting substrate wafer  1 .  
         [0067]     Preferably, in this bonding process, a plurality of notches are formed on the edge of the SOI layer wafer  321  as has been shown in the first preferred embodiment and the two wafers are precisely positioned by using the semiconductor wafer manufacturing apparatus shown in  FIGS. 6 and 7 . However, this preferred embodiment is not limited to this example.  
         [0068]     Next, the surface of the SOI layer wafer  321  is processed by grinding, CMP (Chemical Mechanical Polishing), chemical treatment or the like, so as to thin the SOI layer wafer  321  to form a semiconductor layer  322  (see  FIG. 10 ). The thickness TH of the semiconductor layer  322  may be about 100 to 1000 nm, for example.  
         [0069]     Next, an oxygen ion implantation IP 1  is applied from the semiconductor layer  322  side into the portion where the two wafers are bonded to each other (into a neighborhood of the bonded plane BD). Then the structure is thermally processed at a temperature of about 1300° C. to 1400° C. to form the oxygen-ion-implanted portion into an oxide film layer  2 . Thus the portion of the semiconductor layer  322  that is left unoxidized forms the SOI layer  32  (see  FIG. 11 ). The dosage of oxygen ions can be 1×10 17  to 1×10 18  cm −2 , for example.  
         [0070]     According to this preferred embodiment, the SOI layer wafer  321  and the supporting substrate wafer  1  are bonded together with their crystal directions shifted from each other, implanted with oxygen ions, and thermally processed to form the oxygen-ion-implanted portion into the oxide film layer  2 .  
         [0071]     In general bonding methods, an oxide film layer is formed on a surface of one wafer and then this wafer is bonded to another wafer, without the need for oxygen ion implantation. However, nonuniformity of the film thickness of the SOI layer can be easily prevented by precisely controlling the oxygen ion implantation, so as to form a thin film with uniform thickness.  
         [0072]     Thus, this preferred embodiment enables the manufacture of an SOI wafer that has the SOI layer  32  with reduced film thickness nonuniformity. The reduced thickness nonuniformity of the SOI layer enhances the current driving capability. In this way, the semiconductor wafer can be easily cleaved so that a section along MOS transistor channel direction is exposed, and a MOS transistor having a remarkably enhanced current driving capability can be formed on the semiconductor wafer.  
         [0073]     While the invention has been described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is understood that numerous other modifications and variations can be devised without departing from the scope of the invention.