Abstract:
An apparatus and method that permits signal traces of different widths and the same impedance to be placed on the same layer of a printed circuit board (PCB). Alternatively, signal traces of different impedances but the same width may be placed on the same layer of the PCB. Ground and power planes are paired on adjacent layers of the PCB with a portion of the power plane relative to the ground plane removed. Signal traces of the same width and different impedances or vice-versa can be placed on the same layer because each signal trace is referenced to different planes.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This is a divisional of U.S. Ser. No. 10/437,619, filed May 14, 2003, now U.S. Pat. No. 7,259,968, which is hereby incorporated by reference. 
    
    
     BACKGROUND 
     A circuit board, that may be a printed circuit board (PCB), includes many layers of conducting and nonconducting material. The PCB contains signal traces connecting the input and output pins of electronic components that may perform a particular function or set of functions. Examples of components that may be integrated within a PCB include memory devices, application specific integrated circuits (ASICs) and processing devices such as digital signal processors (DSPs). Each PCB may have one or more ground planes and power planes that connect to the electronic components. 
     In a PCB, electronic components are connected to each other through signal traces. In order to route in and out of the small pins of the electronic components, the signal traces may have to be of the same sufficiently narrow width. Some of the signal traces connecting electronic components may have to be of low impedance and low direct current (DC) resistance to carry high frequency and other types of signals. Because the impedance and resistance of a signal trace generally decreases with increasing trace width or, vice-versa, increases with decreasing trace width, the narrow width for routing generally makes the trace impedance and resistance high. 
     Signals being driven between the electronic components through the signal traces on the same layer of the PCB may be subject to detrimental impedance effects. One manifestation of these impedance effects is unwanted reflections due to impedance mismatches. The signals may also be prone to cross-talk and electromagnetic interference (EMI). 
     The impedance of a trace is also affected by the distance between the trace and adjacent conducting planes on layers above and below the trace. Thus, the conflicting requirements described for the two situations above suggest that for each situation the signal traces be routed on separate layers. However, the additional layers needed to provide route paths may increase the cost of a PCB. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows an example of a PCB with an array of signal traces. 
         FIG. 2  shows a perspective view of some of the layers of a multi-layer PCB in accordance with embodiments of the present invention. 
         FIG. 3  shows the layers of conductive material in the multi-layer PCB of  FIG. 2  with different trace widths and same impedance in accordance with an embodiment of the present invention. 
         FIG. 4  shows layers of conductive material of  FIG. 2  with same trace widths and different impedances in accordance with another embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Referring to  FIG. 1 , an example of an array of signal traces between first and second electronic components  70  and  72  is shown. In this example, the signal traces are 5 mil (a mil being equal to 1/1000 of an inch) in width while the distance x between adjacent signal traces may be large enough so that there are no contributions to a trace impedance from its adjacent traces. The signal traces connect electronic components  70  and  72  through input/output pins  60 . In the example shown in  FIG. 1 , the signal traces are on the mounting layer  50  of the PCB; however, in other examples as described below with reference to  FIG. 2 , the signal traces may be sandwiched between adjacent layers of the PCB. Signal traces on a layer embedded between adjacent layers be coupled by input/output pins  60 . A via travels vertically through the adjacent layers to connect to respective structures at its two ends. 
     Turning now to  FIG. 2 , some of the layers  210  of a sample multi-layer PCB are shown. These layers  210  typically include one or more signaling layers as well as a plurality of power and ground layers that, in some embodiments of the invention, are placed above and below the signaling layers. In some embodiments, the complete PCB may have a total of 6 to 20 layers with the top and bottom layers (not shown in  FIG. 2 ) containing electronic components mounted on these layers. Layers containing conducting material such as copper may be sandwiched between nonconducting dielectric layers. Thus, as shown in  FIG. 2 , first layer  80  containing copper signal traces  91  and  92  and second layer  84  containing copper power plane  81  include a dielectric layer between them. The portion of the multi-layer PCB shown in  FIG. 2  may also include a ground plane  88  on third layer  89 , a fourth layer  82  containing power plane  83 , and fifth layer  86  containing ground plane  90 . Thus, the multilayer PCB may include a total of five copper layers and four dielectric layers (shown in  FIG. 2 ) between the copper layers. In some implementations, the copper conductive material on the signal trace, power plane, and ground plane layers may be formed onto nonconducting materials such as a dielectric to create the signal traces, power plane and ground plane on each respective layer. Thus, for example as shown in  FIG. 2 , the whole top surface of third layer  89  may be formed with copper conducting materials to form ground plane  88 . In a similar fashion, power plane  81  may be formed by depositing the whole top surface of second layer  84  with copper conductive material and then removing half of the copper to form a void. 
     Referring now to  FIG. 3 , the layers of  FIG. 2  are shown. In  FIG. 3 , traces  91  and  92  have respective widths W 2  and W 1 , with W 2  greater than W 1 . The ground plane  88  extends substantially the whole width of third layer  89 , while power plane  81  extends approximately half the width of second layer  84 . In some embodiments of the invention, to provide a low impedance power plane, the power plane and ground plane may be combined into closely spaced pairs as shown in  FIG. 3 . Removing part of the power plane in each of the closely spaced pairs allows traces with the same impedance but different widths to be placed on the same routing layer  80 . This is because, as mentioned above, the impedance of a trace is formed by the width of the trace and the thickness of the dielectric between the trace layers and a power/ground layer, determined by the distance between the trace and adjacent planes on layers above and below the trace. Thus, as shown in  FIG. 3  for some embodiments of the invention, the impedance of signal trace  92  is determined by its width W 1  and the dielectric thickness to the power planes  81  and  83 . Each of the dielectric thicknesses between power planes  81  and  83  and the signal trace  92  is H 1 . The impedance of the signal trace  91  is determined by its width W 2  and dielectric thicknesses to the ground planes  88  and  90 . These thicknesses are each H 2 . Thus, even though signal trace  91  has a broader width than signal trace  92 , the impedances of the signal traces  91  and  92  can be matched by varying dielectric thicknesses between the traces  91  and  92  and respective power/ground layers. For example, the impedance of each of the signal traces  91  and  92  can be set at 50 ohms. 
     Thus, as shown in  FIG. 3 , portions of the power planes  81  and  83  at regions above and below the signal trace  91  are removed to increase the effective dielectric thickness of the signal trace  91  to a power/ground plane. 
     Referring now to  FIG. 4 , layers of a PCB according to another embodiment are shown. The layers  80  includes signal traces  425  and  430 , each having the same width. The layers also include a ground plane  415  extending substantially the width of third layer  89  and power plane  420  extending approximately half the width of second layer  84 . Removing part of the power plane in each of the closely spaced power plane/ground plane pairs allows traces with the same width but different impedances to be placed on the same routing layer. This is because, as mentioned above, the impedance of a trace is formed by the width of the trace and the dielectric thickness between the trace and adjacent planes on layers above and below the trace. By varying the dielectric thicknesses between signal traces  425  and  430  and respective power/ground planes, the impedances of signal traces  425  and  430  are set to different values. For example, the signal trace  425  has an impedance of 70 ohms, while the signal trace  430  has an impedance of 50 ohms. 
     Again, portions of the power planes  420  and  435  in regions above and below the signal trace  425  are removed to increase the effective dielectric thickness between the signal trace  425  and power/ground planes. More generally, tailoring of the impedance of a signal trace is achieved by removing portions of a power or ground plane in regions that are vertically above and below the signal trace. This effectively creates an opening or void region in the power or ground plane. The opening in void region lacks the electrically conductive material (e.g., copper) making up the power or ground plane. The opening or void region is located vertically above or below the signal trace. 
     In the foregoing description, numerous details are set forth to provide an understanding of the present invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these details. While the invention has been disclosed with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover such modifications and variations as fall within the true spirit and scope of the invention.