Abstract:
A means and a method applied in syndrome generation in the Video/Audio processing system is disclosed. The syndromes thereof are effectively and rapidly generated simply using shift register and an exclusive or adder by a recursive operation. For the code words having a number of bytes, the syndromes can be generated by repeating exclusive or (XOR) operation between a shift bit and the above-mentioned bytes, without the extra step of table-matching, saving large memory capacity, greatly reducing the operation cycle and completing the operation rapidly.

Description:
BACKGROUND OF THE INVENTION 
     This application incorporates by reference Taiwanese application Serial No. 80105249, Filed Apr. 2, 1999. 
     1. Field of the Invention 
     This invention is related to a means for syndrome generation in a Video/Audio processing system, and more particularly to a generation means and a method for identifying the receiving code words in the compact disk (CD) decoding process. 
     2. Description of the Related Art 
     Syndrome generation is a checking process for identifying the receiving code words. The syndrome is generated by multiplying the receiving code words by the checking vectors. The equation of syndrome generation is given as follows: 
     
       
           S =Σ( R   i ×α i ), 
       
     
     wherein S represents the syndromes, R i  represents the code words, α represents the checking vector, which is a shift byte and i is the order. α is the element of a Galois Field, and the value of it is (00000010) b . Taking A, an element of the Galois Field, as an example, the product of A multiplied by α i  can be yielded by left shifting A by i bit, if i is not larger than 7. If i is larger than 7, the product of A multiplied by α i  can be generated by the following equation derived from the character of the Galois Field: 
     
       
         α 8 =α 4 ⊕α 3 ⊕α 2 ⊕α 0,   
       
     
     wherein “⊕” is an Exclusive OR (XOR) operator. 
     For any element of the Galois Field, A, as the Most Significant Bit (MSB) is 1, the product of A multiplied by α is the XOR operation result of (00011101) b  and the value of A left-shifting one bit. On the other hand, as the MSB is not 1, the product of A multiplied by is the value of A after left shifting by one bit. This left-shifting and XOR operation are so-called shift operation, and therefore α is called a shift byte. Conventionally, as the mathematics characteristic of a Galois Field is applied in the multiplication performed by any software and hardware, table-matching or logic circuit including a large number of the gate counts is necessary. 
     It is sometimes possible that a compact disk (CD) may suffer from physical damage, for example, scratches, during production or use. To prevent logical continuous data from being lost as a result of the physical damage, a data scramble technique is typically employed during the data-write process of CD read-only-memory (CD-ROM) production. In short, each logical continuous data stream is first divided into a plurality of blocks according to a predetermined algorithm. Afterwards, another algorithm is employed to scramble blocks of one logical continuous data stream with blocks of other logical continuous data streams. The resulting scrambled data are then sequentially and continuously written into the physical spaces of the CD. When, unfortunately, a certain portion of the CD is damaged, the portion of damaged data belonging to one logical continuous data stream may be recovered by the associated un-damaged data of the respective logical continuous data stream via the algorithm. Therefore, in addition to the raw data, some extra data, including control code, sync code, and protection code are added to the raw data to form the complete data in the CD. 
     In order to prevent data damage or loss, when original data are to be stored in disks, the following encoding operations are sequentially performed: C 3  encoding, C 2  encoding, interleaving, and C 1  encoding. 
     The interleaving operation re-partitions frames of C 2  coded data into different frames for C 1  coding. After interleaving, if data is damaged, the damaged data is dispersed among different frames of the decoded data, and thus correction probability is enhanced. 
     Therefore, when data in a disk is read, the following decoding operations are sequentially performed: C 1  decoding, deinterleaving, C 2  decoding, and C 3  decoding. Deinterleaving is a reverse operation of interleaving. 
     During the process of writing data into the CD, encoding the C 3  code, encoding the C 2  code, interleaving codes and encoding the C 1  code are the essential steps, wherein the C 3  code is encoded by sectors, each sector has 98 frames and each frame has 24 bytes. The C 2  code is encoded by frame. In the step of encoding the C 2  code, each frame has an additional four parity check bytes beyond the 24 bytes output from the C 3  code. The original 24 bytes and the additional 4 parity check bytes are yielded by the following equation: 
       W   3   ×G   2   =V   2,   
     wherein W 3  is the 24-byte code word matrix of C 2  output from C 3 , which is a 1×24 matrix, G 2  is a generating matrix, which is a 24×28 matrix, and V 2  is the code word of the C 2  code, which is a 1×28 matrix, and also the code word after the C 2  code encoding step. 
     Similarly, the 28-byte code word of the C 2  code is first processed through interleaving codes, then multiplied by a generating matrix G 1  of the C 1  code to yield a 32-byte code word V 1 . V 1  is the code word after the C 1  code encoding. The 32-byte code word V 1  includes the above 28 bytes from the C 2  code word and the other four bytes of the parity check code. Then, the data after encoding is written in the CD. 
     While the data is read from the CD, the read source code has to be decoded. The process of decoding includes sequentially the steps of decoding the C 1  code, deinterleaving codes, decoding the C 2  code, and decoding the C 3  code. The steps of decoding the C 1  code include multiplying the read 32-byte code word, which is a 1×32 matrix V 1 , by a 32×4 checking matrix H 1  to yield a 1×4 syndromes matrix S. The equation is given as follows. 
     
       
           S=V   1   ×H   1   =[S   0   S   1   S   2   S   3 ], 
       
     
     wherein 
     
       
           S   0   =V   0   ⊕V   1   ⊕V   2 ⊕ 31 ; 
       
     
     
       
           S   1   =V   0   ⊕V   1   α⊕V   2 α 2   ⊕ . . . V   31 α 31 ; 
       
     
       S   2   =V   0   ⊕V   1 α 2   ⊕V   2 α 4   ⊕ . . . V   31 α 62 ; and 
     
       
           S   3   =V   0   ⊕V   1 α 3   ⊕V   2 α 6   ⊕ . . . V   31 α 93 . 
       
     
     The yielded data are identified to be correct if the values of S 0 , S 1 , S 2  and S 3  are all equal to zero. If not, there must exist errors. 
     The processes of decoding the C 2  code and the C 3  code include also similar syndrome generation steps. It is therefore not further described herein. 
     The equation for generating the four syndromes can be represented as followed: 
     
       
           S   j   =ΣR   1 ×(α i ) j , 
       
     
     wherein, R i  represents the receiving code words R 0 , R 1 , R 2 , R 3 , . . . , and R 31 , i=0˜31, and S j  represents the syndromes S 0 , S 1 , S 2 , and S 3 , j=0˜3 
     Let (S j ) i =R 0 ×(α 0 ) j ⊕R 1 ×(α 1 ) j ⊕R 2 ×(α 2 ) j ⊕ . . . ⊕R i ×(α i ) j , wherein the syndrome (S j ) i  is the result for generating recursively for i+1 times. 
     FIG. 1 is a block diagram of the conventional syndrome generating means. Referring to FIG. 1, the code word R 0  is first written in the register  10 , which is the syndrome (S j ) 0 . At the next timing, the code word R 1  is multiplied by the checking vector (α 1 ) j  using a multiplier  12 . The product yielded by the above-mentioned multiplication operation and the output value of the register  10  are then processed through an XOR operation by an XOR gate  14  to yield the syndrome (S j ) 1 , and then the syndrome (S j ) 1  is fed back to the register  10 . At the next timing, similar operation is performed to yield the syndrome (S j ) 2 . By such recursive operation, the finally yielded syndrome (S j ) 31  is syndrome Sj. 
     For every multiplication operation, using the conventional syndrome generating means, table matching or complicate logic circuits have to be utilized. For a syndrome generation, a multiplication operation and an XOR operation are both necessary so that not only a large number of table matching steps have to be taken but also a great number of logic gates are used, which needs large memory capacity and extends the processing period. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the invention to provide a means and method for syndrome generation which makes use of a shift register and an XOR gate for decoding and generating the syndrome recursively. The means and method is used in the Video/Audio processing system, which rapidly and effectively accomplishes the syndrome generation. This invention has the advantages of simple structure, reducing significant operation time, and reducing the memory capacity. 
     It is therefore another object of the invention to provide a means for syndrome generation, which is able to accomplish the syndrome generation for a code word with a number of bytes. The means for syndrome generation includes an XOR gate and a register for receiving a shift byte of the bytes. Then, XOR operation is then performed to yield the syndrome. 
     It is therefore another object of the invention to propose a method for syndrome generation, which is used for generating the syndrome for a code word with a number of bytes. First, let one of the bytes be a register value. Next, an XOR operation of the register value, a shift byte and another one of the bytes is performed. The result of the XOR operation replaces the register value and the step is repeated until the syndrome generation is accomplished. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other objects, features, and advantages of the invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The description is made with reference to the accompanying drawings in which: 
     FIG. 1 (Prior Art) is the block diagram of a conventional syndrome generation means: 
     FIG. 2 is a block diagram of a syndrome generation means according a preferred embodiment of the invention; and 
     FIG. 3 is the structure of a syndrome generation means according a preferred embodiment of the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The decoding process in a video/audio processor, for example, a CD ROM, the receiving code word can be, for example, a 32-byte C 1  code. Such a code can be represented as (R 0 , R 1 , R 2 , R 3 , . . . , R 31 ), wherein R 0 , R 1 , R 2 , R 3 , . . . and, R 31  are all bytes. The equation for generating the four syndromes S 0 , S 1 , S 2 , S 3  is as follows. 
     
       
           S   j =Σ i=0˜31   R   i ×(α i ) j , 
       
     
     wherein j=0˜3. 
     In this embodiment, an 8-byte syndromes S 1 , as j=1, in the C 1  code decoding process is taken as an example for further illustration. 
     First, the equation of generating the syndrome S 1  is rearranged as follows. 
     
       
         S 1   =ΣR   i ×(α i )=((( . . . (((( R   31   ×α⊕R   30 )×α⊕ R   29 )×α⊕R 28 ) . . . ×α⊕ R   2 )×α⊕ R   1 )×α⊕ R   0 )  (1) 
       
     
     Wherein, shift byte a is the element of a Galois Field, the value of which is (00000010) b , “×” represents a multiplication operation, “⊕ represents an XOR operation. The equations of generating syndromes S 2  and S 3  are similar to that of the syndrome S 1 . 
     Referring to FIG. 2, it is the block diagram of a syndrome generation means according a preferred embodiment of the invention. 
     Taking the generation of the syndrome S 1  as an example, the value of the first byte R 31  is first written in the register  20 , the value of the first byte R 31  written in the register  20  is then multiplied by a shift byte a by a multiplier  22  to yield an output value. The result of the XOR operation, using an XOR gate  24 , of the above-mentioned output value and the second byte R 30  is then output and again written in the register  20 . Further, the result of the XOR operation written in the register  20  is multiplied by the shift byte a and after the XOR operation with the third byte R 29 , the result is again written in the register  20 . The foregoing recursive operation has to be done for each byte of the code word. The final output result of the XOR gate  24  is the value of the syndrome S 1 . 
     The shift byte a includes 8 bits. The first bit is defined as the least significant bit (LSB) and the eighth bit is defined as the most significant bit (MSB). For the multiplication operation of an 8-byte Galois Field&#39;s element and the shift byte α, while as the above-mentioned generating means is applied for syndrome generation, the product is equal to the value of left-shifting the first to the seventh bits for 1 bit if the MSB is not 1. However, the product of the same multiplication operation is equal to the result of XOR operation of the value of left-shifting the first to the seventh bits one bit of the 8-byte Galois Field&#39;s element and (00011101) b  if the MSB, is an effective one, which is 1. Consequently, a multiplier can be replaced by a simple XOR gate, which accomplishes an equal multiplication operation, in the syndrome generation means in FIG.  2 . Only simple XOR gates with the input of the shift byte α, R i  and the output of the register are required for the multiplication operation. 
     Referring to FIG. 3, it shows the structure of a syndrome generation means according a preferred embodiment of the invention. According to the preferred embodiment, by the principle of the shift register, the 8-byte syndrome can be generated only using a register  30  and XOR gates  31 ,  32 ,  33 ,  34 ,  35 ,  36 ,  37 ,  38 . 
     In the equation (1), the operation of “×α” can be accomplished directly by left-shifting the first to the seventh bits for one bit. However, as the MSB is 1, the operation of “×α” is equal to the XOR operation of the value of left-shifting the first to the seventh bits for one bit and (00011101) b . Therefore, simply XOR gates are needed for the multiplication operation. 
     The syndrome S 1  is a value having 8 bits. Let S 1,i  be equal to the value of (( . . . ((((R 31 ×α⊕R 30 )×α⊕R 29 )×α⊕R 28 ) . . . R 31−(i−1) )×α⊕R 31−i ), wherein i=0 . . . 31. S 1,i  represents the value after i times of multiplication and XOR operation are repeated. For example, as i=1, S 1,1 =R 31 ×α⊕R 30 , then S 1,i+1 =S 1,i ×α⊕R 31−(i+1) , wherein S bi,0 , S bi,1 , S bi,2 , S bi,3 , S bi,4 , S bi,5 , S bi,6 , and S bi,7  respectively represent the values of the eight bits of S 1,i  from the LSB to the MSB and R bi,0 , R bi,1 , R bi,2 , R bi,3 , R bi,4 , R bi,5 , R bi,6 , and R bi,7  respectively the 8 bits of one byte R i  of the receiving code word, and the subscript b represents that each bit is the binary value of R i , or S 1,i , is a binary bit. 
     Let 
     
       
           S   1,0   =R   31 ; 
       
     
     
       
           S   1,1   =R   31   ×α⊕R   30   =S   1,0   ×α⊕R   30 ; 
       
     
       S   1,2 =( R   31   ×α⊕R   30 )×α⊕ R   29   =S   1,1   ×α⊕R   29 ; 
     
       
         . . .  
       
     
     
       
           S   1,31 =((( . . . (((( R   31   ×α⊕R   30 )×α⊕ R   29 )×α⊕ R   28 ) . . . ×α⊕ R   2 )×α⊕ R   1 )×α⊕ R   0 )= S   1   (2) 
       
     
     The first step is the multiplication operation of R 31 ×α. Since α=(00000010) b , the product of the multiplication operation of R 31 ×α is the result of the XOR operation of R 30  and the value of left-shifting each bit of S 1,0  for one bit. The result is then output and written in the register  30 . Therefore, the output value of the register  30  is S 1,1 . The 8 bits of S 1,1  are shown as follows: 
     
       
           S   b1,0   =R   b30,0 ; 
       
     
     
       
           S   b1,1   =S   b0,0   ⊕R   b30,1 ; 
       
     
     
       
           S   b1,2   =S   b0,1   ⊕R   b30,2 ; 
       
     
     
       
           S   b1,3   =S   b0,2   ⊕R   b30,3 ; 
       
     
     
       
           S   b1,4   =S   b0,3   ⊕R   b30,4 ; 
       
     
     
       
           S   b1,5   =S   b0,4   ⊕R   b30,5 ; 
       
     
     
       
           S   b1,6   =S   b0,5   ⊕R   b30,6 ; and 
       
     
       S   b1,7   =S   b0,6   ⊕R   b30,7   (3) 
     That is to say the operation of S 1,1 =S 1,0 ×α⊕R 30  is by now accomplished. 
     According to a similar rule, the value of S 1,i+1  can be yielded by a recursive operation. The value of S 1,i+1 , at the next timing, is the XOR operation value of R (31−(i+1))  and left-shifting the value of S 1,i . The generating equation is S 1,i+1 =S 1,i ×α⊕R (31−(i+1)) =( . . . (((R 31 ×α⊕R 30 )×α⊕R 29 )×α⊕R 28 ) . . . ×α⊕R (31−(i+1)) ), wherein 
     
       
           S   b(i+1),0   =R   b(30−i),0 ; 
       
     
     
       
           S   b(i+1),1   =S   bi,0   ⊕R   b(30−i),1 ; 
       
     
     
       
           S   b(i+1),2   =S   bi,1   ⊕R   b(30−i),2 ; 
       
     
     
       
           S   b(i+1),3   =S   bi,2   ⊕R   b(30−i),3 ; 
       
     
     
       
           S   b(i+1),4   =S   bi,3   ⊕R   b(30−i),4 ; 
       
     
     
       
           S   b(i+1),5   =S   bi,4   ⊕R   b(30−i),5 ; 
       
     
     
       
           S   b(i+1),6   =S   bi,5   ⊕R   b(30−i),6 ;d 
       
     
     
       
           S   b(i+1),7   =S   bi,6   ⊕R   b(30−i),7   (4) 
       
     
     Therefore, the value of S 1,i+1  can be generated. 
     However, the left-shifting rule can not be applied to a multiplicand, an element of the Galois Field, having an effective MSB, 1. It is because the ninth bit becomes 1, while each bit of the multiplicand having an effective MSB is left shifted by one bit, but only 8 bits are included in a byte. As a result, the character of the Galois Field has to be applied in the multiplication operation. All elements of the Galois Field satisfy the following polynomial: 
     
       
           P ( x )= x   8   ⊕x   4   ⊕x   3   ⊕x   2 ⊕1; 
       
     
     therefore, α 8 =α 4 ⊕α 3 ⊕α 2 ⊕1. 
     For each 8-bit element of the Galois Field, the foregoing polynomial is always true. For example, while α 7  having an MSB of 1 is left-shifted by one bit, an additional bit may occur. Therefore, α 8  can be represented as (00011101) b . Consequently, the simple operation of being multiplied by a has to be replaced by the XOR operation of (0001101) b  and the value of the multiplicand after each bit of it is left-shifted by one bit if the multiplicand has an MSB of 1. 
     In other words, if S bi,7  of S 1,i  is 1, the generation of S 1,i+1  can be accomplished by left-shifting each bit of the S 1,i  by one bit, performing the XOR operation of the left-shifting value and (00011101) b  and then performing another XOR operation with R (31−(i+1)) . Referred to FIG. 3, the operation can be directly designed in the hardware, simply by adding the third input terminals to the XOR gates, which originally have two input terminals. In other words, 
     
       
           S   b(i+1),0 =1 ⊕R   b(30−i),0 ; 
       
     
     
       
           S   b(i+1),1 =0 ⊕S   bi,0   ⊕R   b(30−i),1 ; 
       
     
     
       
           S   b(i+1),2 =1 ⊕S   bi,1   ⊕R   b(30−i),2 ; 
       
     
     
       
           S   b(i+1),3 =1 ⊕S   bi,2   ⊕R   b(30−i),3 ; 
       
     
     
       
           S   b(i+1),4 =1 ⊕S   bi,3   ⊕R   b(30−i),4 ; 
       
     
     
       
           S   b(i+1),5 =0 ⊕S   bi,4   ⊕R   b(30−i),5 ; 
       
     
     
       
           S   b(i+1),6 =0 ⊕S   bi,5   ⊕R   b(30−i),6 ; and 
       
     
     
       
           S   b(i+1),7 =0 ⊕S   bi,6   ⊕R   b(30−i),7   (5) 
       
     
     However, the circuit design can be further simplified because the XOR operation with (00011101) b  has to be taken only when S bi,7  is 1. Therefore, the XOR operation with (00011101) b  can be replaced by an XOR operation with (0 0 0 S bi,7  S bi,7  S b,7  0 S bi,7 ) b . Also, to generate S 1,i+1 , the XOR operation of the 4 bits and 0 can be omitted since it does not effect the output result. In other words, the generation of S 1,i+1  in equation (5) can be modified as followed: 
       S   b(i+1),0   =S   bi,7   ⊕R   b(30−i),0 ; 
     
       
           S   b(i+1),1   =S   bi,0   ⊕R   b(30−i),1 ; 
       
     
     
       
           S   b(i+1),2   =S   bi,7   ⊕S   bi,1   ⊕R   b(30−i),2 ; 
       
     
     
       
           S   b(i+1),3   =S   bi,7   ⊕S   bi,2   ⊕R   b(30−i),3 ; 
       
     
     
       
           S   b(i+1),4   =S   bi,7   ⊕S   bi,3   ⊕R   b(30−i),4 ; 
       
     
     
       
           S   b(i+1),5   =S   bi,4   ⊕R   b(30−i),5 ; 
       
     
     
       
           S   b(i+1),6   =S   bi,5   ⊕R   b(30−i),6 ; and 
       
     
     
       
           S   b(i+1),7   =S   bi,6   ⊕R   b(30−i),7   (6) 
       
     
     The XOR operations shown in equation (6) can be accomplished simply by using the XOR gates  31 ,  32 ,  33 ,  34 ,  35 ,  36 ,  37 ,  38  and adding new input terminals S bi,7  to the XOR gates  31 ,  33 ,  34 ,  35 , respectively. 
     That is to say, while the MSB S bi,7  of S 1,i  is 1, S 1,i ×α is equal to the result of the XOR operation of left-shifting S 1,i  and (00011101) b . Simultaneously, the forgoing result is then taking an XOR operation with R (31−(i+1)) . The result of the XOR operation with R (31−(i+1))  is then output to the register to yield S 1,i+1 . If the MSB S bi,7  of S 1,i  is not 1 but 0, S bi,7  does not effect the output of the XOR operation. Thus, S 1,i ×α is equal to the result of the XOR operation of R (31−(i+1))  and the value of S 1,1 , the result of which is then output to the register to yield the value of S 1,i+1 . 
     As a result, two different generation methods of different MSBs S bi,7  can be performed in a single circuit, using this means. Moreover, the syndrome S i  is generated by recursive operation from S 1,1  to S 1,31 . 
     For generating the syndrome S 0 , the equation is: 
     
       
           S   0   =ΣR   i ×(α i ) 0   R   31   ⊕R   30   ⊕R   29   ⊕ . . . ⊕R   1   ⊕R   0 . 
       
     
     The generating of S 0  does not involve the problem of shifting bit but only a simple XOR operation. Therefore, each XOR register does not need the input of S bi,7 . 
     For the generation of the syndrome S 2 , the equation is as follows. 
     
       
           S   2   =ΣR   i ×(α i ) 2 =(( . . . ((R 31 ×α 2   ⊕R   30 )×α 2   ⊕R   29 )×α 2 ⊕ . . . ×α 2   ⊕R   1 )×α 2   ⊕R   0 ) 
       
     
     Left-shifting the multiplicand by two bits may result in the occurrence of the effective bit, 1, in the highest two bits. Similarly, some necessary XOR gates are input with S bi,6  and S bi,7 . 
     Further, the generation equation of S 3  is as follows: 
     
       
           S   3   =ΣR   i ×(α i ) 3 =(( . . . ((R 31 ×α 3   ⊕R   30 )×α 3   ⊕R   29 )×α 3 ⊕ . . . ×α 3   ⊕R   1 )×α 3   ⊕R   0 ). 
       
     
     According to the invention, using the principle of the shift register not only saves a great number of control gates but also reduces the period of generating syndromes. For example, conventionally, table-matching or a direct multiplication operation is used for the multiplication operation with the multiplicand of α to α 93 . However, it is time-consuming. On the other hand, using the shift register and the XOR gate of the invention does not require such a large number of operation cycles, but only the XOR operation to complete the generation of the syndromes. The means and method for syndromes generation of the invention include simple structure and further save a significant operation period and memory capacity. 
     Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as described in the accompanying claims.