Abstract:
A number of voltage-controlled resistance cells, each formed by a transistor with a biasing capacitor connected between the gate and source and an associated controller coupled to the capacitor to maintain a steady charge on the biasing capacitor and keep the gate-source voltage at a control voltage corresponding to a desired resistance, are employed to form a voltage-controlled resistance structure. The gate voltage applied to each transistor is able to “float” together with the source voltage in order to keep the gate-source voltage constant, and the resistance structure exhibits improved voltage-dependent resistance linearity together with a larger range of biasing while lowering needed refresh frequencies to avoid noise injection.

Description:
TECHNICAL FIELD OF THE INVENTION 
     The present invention is directed, in general, to voltage controlled resistors and, more specifically, to voltage controlled resistors with high resistance-to-voltage linearity for use in tuning circuits and the like. 
     BACKGROUND OF THE INVENTION 
     Voltage controlled resistors, having a resistance which varies with an applied voltage, have use in a wide variety of applications, including, for example, tuning circuits. Metal oxide semiconductor (MOS) transistors may function as voltage controlled resistors if operated in the ohmic region, with the gate-source voltage controlling the resistance. 
     Within the signal path of a signal processing circuit, however, the resistance of an MOS transistor employed to provide voltage controlled resistance also changes with the source-drain voltage. If the gate voltage is held constant, the resistance of the transistor changes with the source voltage, introducing high non-linearity in the resistive behavior of the transistor. This non-linearity becomes higher as the overdrive voltage applied to the transistor—the gate-source voltage minus the threshold voltage (Vgs−Vt)—decreases. As the voltage supply becomes lower, providing a good overdrive of the transistor becomes increasingly difficult, particularly if the source (assuming an n-channel transistor) cannot be connected to ground. 
     There is, therefore, a need in the art for a voltage controlled resistor having a high linearity of resistance per unit change in applied voltage. 
     SUMMARY OF THE INVENTION 
     To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide, for use in an integrated circuit, a voltage-controlled resistance structure formed from a number of voltage-controlled resistance cells, each including a transistor with a biasing capacitor connected between the gate and source and an associated controller coupled to the capacitor to maintain a steady charge on the biasing capacitor and keep the gate-source voltage at a control voltage corresponding to a desired resistance. The gate voltage applied to each transistor is able to “float” together with the source voltage in order to keep the gate-source voltage constant, and the resistance structure exhibits improved voltage-dependent resistance linearity together with a larger range of biasing while lowering needed refresh frequencies to avoid noise injection. 
     The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art will appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form. 
     Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words or phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term “controller” means any device, system or part thereof that controls at least one operation, whether such a device is implemented in hardware, firmware, software or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, and those of ordinary skill in the art will understand that such definitions apply in many, if not most, instances to prior as well as future uses of such defined words and phrases. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, wherein like numbers designate like objects, and in which: 
         FIG. 1  depicts a voltage controlled resistance structure according to one embodiment of the present invention; 
         FIG. 2  illustrates in greater detail a voltage controlled resistor portion of a resistance cell according to one embodiment of the present invention; 
         FIG. 3  illustrates a voltage controlled resistor and associated controller for a resistance cell according to one embodiment of the present invention; 
         FIG. 4  illustrates a timing diagram for driving the control inputs to voltage controlled resistor and associated controller for each resistance cell according to one embodiment of the present invention; 
         FIG. 5  depicts a plot of the voltage-dependent resistance of a resistance structure having 10 resistance cells according to one embodiment of the present invention connected in series; and 
         FIG. 6  depicts a plot of the voltage-dependent resistance of a resistance structure having only one resistance cell according to one embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIGS. 1 through 6 , discussed below, and the various embodiments used to describe the principles of the present invention in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the invention. Those skilled in the art will understand that the principles of the present invention may be implemented in any suitably arranged device. 
       FIG. 1  depicts a voltage controlled resistance structure according to one embodiment of the present invention. Voltage controlled resistance structure  100  includes a set of n (where n is any positive integer) voltage controlled resistance cells  101 a- 101 n connected in series. In the exemplary embodiment, each voltage controlled resistance cell  101 a- 101 n receives three control signals WS, WC and WG 2  in addition to a control voltage Vg, as described in further detail below. 
       FIG. 2  illustrates in greater detail a voltage controlled resistor portion of each resistance cell according to one embodiment of the present invention. Each resistance cell  101 n includes voltage controller resistor  200  formed by a metal oxide semiconductor (MOS) field effect transistor M 0  (an n-channel transistor in the exemplary embodiment) with a capacitor cgate connecting the gate to the source. If the charge of capacitor agate is kept constant, then the gate-source voltage Vgs—and the channel resistance, as well—of transistor M 0  will also remain constant. In this configuration, because no direct current (DC) path exists which can discharge the capacitor cgate, any variation in the source voltage Vs will automatically result in the same variation of the gate voltage Vg, keeping the gate-source voltage Vgs constant in this manner. The resistance structure of  FIG. 1  is formed by connected the source of transistor M 0  in one resistance cell to the drain of transistor M 0  in another transistor cell. 
       FIG. 3  illustrates a voltage controlled resistor and associated controller for each resistance cell according to one embodiment of the present invention. As with the circuit of  FIG. 2 , the resistance structure of  FIG. 1  is formed by connected the source of transistor M 0  in one resistance cell to the drain of transistor M 0  in another transistor cell. The associated controller  300  for each resistance cell is not interconnected with controllers for other resistance cells, although each receives the same control inputs WC, WS and WG 2 . 
     Controller  300  is employed with each resistance cell  101 n in order to maintain a constant charge on capacitor cgate within voltage controlled resistor  200 . Controller  300  includes two transistors MWG 1  and MWG 2  connected in series between the gate (node g) of transistor M 0  and the input for control voltage Vg. Transistors MWG 1  and MWG 2  are an n-channel transistor and a p-channel transistor, respectively, in the exemplary embodiment, having their sources connected together with the drain of transistor MWG 1  connected to the control voltage input Vg and the drain of transistor MWG 2  connected to the gate of transistor MO. The gate-source voltage Vgs which is to be “translated” into a resistance is applied to the control voltage input Vg. 
     Controller  300  also includes a capacitor cvreg connected in parallel with the capacitor cgate by transistor MWG 2 , which connects one terminal of capacitor cvreg to a terminal (node n 1 ) of capacitor cgate and to the gate of transistor M 0  (node g), and by transistor MSWS, an n-channel transistor in the exemplary embodiment which connects the other terminal (node n 2 ) of capacitor cvreg to both the second terminal of capacitor cgate and the source of transistor M 0  (node s). The gate of transistor MWG 2  is connected to the control input WG 2  while the gate of transistor MSWS is connected to the control input WS. 
     Transistor MSWS is connected at the source to capacitor cgate and the source of transistor M 0  (node s) and at the drain to capacitor cvreg and the drain of transistor MWC (node n 2 ). Transistor MWC, an n-channel transistor in the exemplary embodiment, is connected at the source to a ground voltage level gnd and a the gate to both the gate of transistor MWG 1  and the control input WC. 
     In operation, when control input WS is high and control inputs WG 2  and WC are both low, transistors MWG 2  and MSWS are on, shorting capacitors cvreg and cgate together, while transistors MWG 1  and MWc are both off. Both capacitors cvreg and cgate are therefore allowed to “follow” the voltage at the source of transistor M 0  (node s). When control input WS goes low and control input WG 2  goes high (while control input WC remains low), transistors MWG 2  and MSWS are off, thus disconnecting capacitor cvreg from capacitor cgate, although capacitor cgate is still allowed to “float” and follow the voltage at the source of transistor M 0  (node s). Once disconnected from capacitor cgate, capacitor cvreg is ready to be recharged by the input voltage Vg, which is enabled by control input WC going high and turning on transistors MWG 1  and MWC. 
       FIG. 4  illustrates a timing diagram for driving the control inputs to voltage controlled resistor and associated controller for each resistance cell according to one embodiment of the present invention. The control signals shown are applied to the control inputs WC, WS and WG 2  of the circuits in  FIGS. 1 and 3 . As shown, control inputs WG 2  and WS are inversely related, and control input WC is driven high only while control input WS is low and control input WG 2  is high, disconnecting capacitor cvreg from capacitor cgate. 
     The voltage controlled resistance structure of the present invention has several advantages over other voltage controlled resistance structures: Power dissipation is very small, since only a small amount of charge is needed to compensate the losses on the capacitors (leakage currents) once the circuit has reached rest biasing. By connecting a number of resistance cells of the type disclosed in series, the variation of each source-drain voltage (Vds) is smaller, so that the resistance is much more linear over the Vds variation, which is now reduced. 
       FIGS. 5 and 6  illustrate the improvement of resistance linearity as the number of resistance cells connected in series to form a voltage controlled resistance structure increases. In both plots, the horizontal axis represents the voltage drop across the entire resistance structure, while the vertical axis represents resistance. In the ideal case, the lines should be horizontal (no resistance variation when the applied voltage changes). The different steps correlate to the differing values of gate-source voltage (Vgs) applied to the resistance structure (where the same Vgs is applied to each transistor).  FIG. 5  depicts the voltage-dependent resistance of a resistance structure having 10 resistance cells according to the present invention connected in series;  FIG. 6  depicts the voltage-dependent resistance of a resistance structure having only one resistance cell according to the present invention. 
     The improved voltage-dependent resistance linearity of the voltage-controlled resistance structure of the present invention is possible because the gate-source voltage Vgs applied to each transistor is able to “float”, together with the source voltage, which also allows a larger range of biasing since if the voltage at the sources (node s) of each transistor M 0  grows, the voltage at the gate (node g) also grows and may even become higher than the supply voltage if necessary (and not harmful to the circuit). The improved voltage-dependent resistance linearity within the voltage-controlled resistance structure of the present invention also allows the frequency of the refreshing signals (control inputs WC, WS and WG 2 ) to be relatively low, limiting problems due to noise injection on nodes sensitive to such problems. 
     Although the present invention has been described in detail, those skilled in the art will understand that various changes, substitutions, and alterations herein may be made without departing from the spirit and scope of the invention in its broadest form.