Abstract:
Methods for enhancing strain in an integrated circuit are provided. Embodiments of the invention include using a localized implant into an active region prior to a gate etch. In another embodiment, source/drain regions adjacent to the gates are recessed to allow the strain to expand to full potential. New source/drain regions are allowed to grow back to maximize stress in the active region.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]    This application is a divisional of co-pending U.S. patent application Ser. No. 12/908,306, filed on Oct. 20, 2010, which received a Notice of Allowance on Feb. 6, 2013. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]    The subject matter disclosed herein relates to enhancing strain in an integrated circuit. Specifically, the subject matter disclosed herein relates to a structure and method for enhancing strain in an integrated circuit by using a localized implant into a gate region prior to gate etch. 
         [0003]    The application of stresses to field effect transistors (FETs) is known to improve their performance. When applied in a longitudinal direction (i.e., in the direction of current flow), tensile stress is known to enhance electron mobility (or n-channel FET (NFET) drive currents) while compressive stress is known to enhance hole mobility (or p-channel FET (PFET) drive currents). Typical methods for enhancing stress in an integrated circuit involve the use of a blanket implantation across an entire semiconductor substrate. For example, as shown in  FIG. 1 , semiconductor substrate  100  is provided, including a region defining a gate region  102 . A thin gate layer  104  is then deposited across substrate  100 . Substrate  100  is then blanket implanted, i.e., implanted across the entire surface of substrate  100 , as illustrated by arrows  106 . A thicker gate layer  108  ( FIG. 2 ) is then deposited across substrate  100  and finally substrate  100  is annealed to create the desired stress. 
       BRIEF DESCRIPTION OF THE INVENTION  
       [0004]    Methods for enhancing strain in an integrated circuit are provided. Embodiments of the invention include using a localized implant into an active region prior to a gate etch. In another embodiment, source/drain regions adjacent to the gates are recessed to allow the strain to expand to full potential. New source/drain regions are allowed to grow back to maximize stress in the active region. 
         [0005]    A first aspect of the invention provides a method comprising: providing a semiconductor substrate having an active region defined therein; depositing a first gate layer on the semiconductor substrate; implanting a stress-inducing material only into the active region; depositing a second gate layer on the semiconductor substrate; and annealing the semiconductor substrate, creating a stress in the active region, wherein the implanting occurs prior to the annealing. 
         [0006]    A second aspect of the invention provides a method comprising: providing a semiconductor substrate including an active region and a non-active region defined therein; depositing a first gate layer on the semiconductor substrate; implanting a stress-inducing material into the first gate layer; removing the first gate layer over the non-active region; depositing a second gate layer; and annealing the semiconductor substrate, wherein the implanting occurs prior to the annealing. 
         [0007]    A third aspect of the invention provides a method comprising: providing a semiconductor substrate including an active region defined therein; forming a first gate layer on the semiconductor substrate having a stress-inducing material implanted therein only over the active region; depositing a second gate layer; annealing the semiconductor substrate; forming the first gate layer and the second gate layer into a gate structure; recessing a source/drain region in the semiconductor substrate adjacent to the active region, allowing stress in the active region to increase; and re-growing the source/drain region adjacent to the gate structure. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0008]    These and other features of this invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings that depict various embodiments of the invention, in which: 
           [0009]      FIGS. 1 and 2  show cross-sectional views of a method and structure for enhancing strain in an IC as known in the art. 
           [0010]      FIGS. 3 and 4  show cross-sectional views of a method according to an embodiment of the invention. 
           [0011]      FIG. 5  shows a top view of the method of  FIGS. 3-4 . 
           [0012]      FIGS. 6-8  show cross-sectional views of a method according to another embodiment of the invention. 
           [0013]      FIGS. 9-11  show cross-sectional views of a process of the method according to embodiments of the invention. 
           [0014]      FIG. 12  shows cross-sectional views of a process of the method according to another embodiment of the invention. 
       
    
    
       [0015]    It is noted that the drawings of the invention are not to scale. The drawings are intended to depict only typical aspects of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements between the drawings. 
       DETAILED DESCRIPTION OF THE INVENTION  
       [0016]    Methods for enhancing stress in an integrated circuit (IC) according to embodiments of this invention are disclosed. 
         [0017]    Turning to  FIGS. 3-4 , a first embodiment of the invention is shown. In  FIGS. 3-4 , a semiconductor substrate  200  is provided having an active region  202  defined therein. Active region  202  may not be structurally defined other than being an area reserved for gates to be built on, or it may be doped with a particular dopant. Areas outside of active region  202  define non-active regions  203 . Semiconductor substrate  200  may include but is not limited to silicon, germanium, silicon germanium, silicon carbide, and those consisting essentially of one or more III-V compound semiconductors having a composition defined by the formula Al X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4 , where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions, each greater than or equal to zero and X1+X2+X3+Y1+Y2+Y3+Y4=1 (1 being the total relative mole quantity). Other suitable substrates include II-VI compound semiconductors having a composition Zn A1 Cd A2 Se B1 Te B2 , where A1, A2, B1, and B2 are relative proportions each greater than or equal to zero and A1+A2+B1+B2=1 (1 being a total mole quantity). 
         [0018]      FIG. 3  also shows depositing a first gate layer  204  on semiconductor substrate  200 . First gate layer  204  may be relatively thin, e.g., approximately 5 nm to approximately 50 nm. First gate layer  204  may include any of the semiconductor materials listed for semiconductor substrate  200 . As used herein, the term “depositing” or “deposition” may include any now known or later developed techniques appropriate for the material to be deposited including but not limited to, for example: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metalorganic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, and evaporation. 
         [0019]    According to embodiments of this invention, a localized implant, as illustrated by arrows  205  ( FIG. 3 ), of a stress-inducing material only into first gate layer  204  and active region  202  is then performed. As shown in  FIG. 3 , implanting into first gate layer  104  results in a stress including gate layer  210 . Localized implant  205  ( FIG. 3 ) dosage can be less than the entire active region  202 , as long as the active portions of active region  202  are included. For example,  FIG. 5  shows a top view of substrate  200 , illustrating an implanted region  212  that is doped less than a final gate region  210 . Implanting  205  may employ any now known or later developed implanting technique, e.g., ion beam implanting, plasma ion implanting, etc., that generates an implanted species density in the range of approximately 2×10 20  to approximately 3×10 21  atoms/cm 3 . Masks (not shown) may be employed where necessary. Stress-inducing material may be any appropriate material capable of creating the appropriate stress. For example, an N-type dopant in NFET or p-type dopant in PFET or neutral type implant (such as silicon). 
         [0020]    In an alternative embodiment, shown in  FIGS. 6-8 , rather than performing localized implant  205  ( FIG. 3 ) just in active region  202 , an implant  220  ( FIG. 6 ) is performed across first gate layer  204 , i.e., across entire semiconductor substrate  200 . Again, implanting  220  may employ any now known or later developed implanting technique, e.g., ion beam implanting, plasma ion implanting, etc., and generates an implanted species density in the range of approximately 2×10 20  to approximately 3×10 21  atoms/cm 3 . Masks (not shown) may be employed where necessary. Then, as shown in  FIG. 7 , mask  208  can be placed over non-active regions  203  ( FIG. 8 ) of semiconductor substrate  200  such that an etch process, as illustrated by arrows  207  ( FIG. 7 ), can be performed to remove first gate layer  204  where not masked, i.e., over non-active region(s)  203 . Consequently, the stress imparted by the dopants in first gate layer  204  is removed from non-active regions  203  ( FIG. 8 ). As shown in  FIG. 8 , stress including gate layer  210  over only active region  202  is the result. 
         [0021]    In either embodiment, as shown in  FIGS. 9 and 10 , a second gate layer  206  is deposited on semiconductor substrate  200 .  FIG. 9  shows the  FIGS. 3-4  embodiment, while  FIG. 10  shows the  FIG. 8  embodiment. Second gate layer  206  can range in thickness from approximately 5 nm to approximately 75 nm. As also shown in  FIGS. 9 and 10 , semiconductor substrate  200  is then annealed  221  to create a stress in active region  202 . The implanting of  FIGS. 3 and 6  occurs prior to the annealing of  FIGS. 9 and 10 . 
         [0022]      FIG. 11  shows forming first gate layer  204  and second gate layer  206  into a gate structure  230  after second gate layer  206  is deposited. Gate structure  230  forming, however, can occur prior to annealing ( FIGS. 9 and 10 ) or after annealing. Gate structure  230  may be formed using any now known or later developed techniques, for example, depositing a cap layer  222 , patterning a mask (not shown), etching gate layers  204 ,  206  and cap layer  222  and forming a spacer(s)  223 . Gate structure  230  thus includes spacer(s)  220  about first gate layer  204  and second gate layer  206 , and a cap  222  above second gate layer  206 . 
         [0023]    A second embodiment according to aspects of this invention is shown in  FIGS. 11-12 . As  FIG. 11  illustrates, the steps discussed with respect to the above-described embodiments have been performed such that substrate  200  includes gate layer  204  (stress including gate layer  210 ) and gate layer  206  just over active region  202 . According to this embodiment, as shown in  FIG. 11 , after substrate  200  has been annealed, spacers  223  and a cap  222  are used to recess and/or remove source/drain regions  224  (shown in phantom) adjacent to gate structure  230  to allow the stress in active region  202  to increase. Then, as shown in  FIG. 12 , a new source/drain region  226  is epitaxially re-grown adjacent to gate structure  230  to maximize stress in active region  202 . 
         [0024]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
         [0025]    The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The embodiments were chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure for various embodiments with various modifications as are suited to the particular use contemplated.