Abstract:
A process for decomposing safety software involves the steps of providing a first software module associated with a first logical unit, providing a second software module associated with a second logical unit, instructing the first software module to implement a first safety goal based on a quality management level, and instructing the second software module to implement a second safety goal based on a safety integrity level, where the second software module uses at least one input and at least one output of the second logical unit to determine if the second safety goal is satisfied. Consequently, the second software module uses a result of the first software module to determine if the first safety goal has been completed, and the second software module uses at least one algorithm to verify an operational status of the first logical unit.

Description:
RELATED APPLICATION 
       [0001]    This application claims the benefit under 35 U.S.C. §119(e) of U.S. Provisional Patent Application Ser. No. 61/621,656, filed Apr. 9, 2012 and U.S. Provisional Patent Application Ser. No. 61/663,282, filed Jun. 22, 2012, which are incorporated by reference herein in their entirety. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The present invention relates to a functional architecture pattern used in a process to decompose software. More particularly, the present invention relates to a functional architecture pattern used in a process to decompose safety software. 
       BACKGROUND OF THE INVENTION 
       [0003]    Currently, governments and industries are imposing functional safety standards on a variety of entities, for example, the automotive industry. Usually, these functional safety standards are realized by way of safety software that utilizes standard functional architecture patterns. Unfortunately, these functional safety standards, software, and architecture patterns are very rigid and do not give OEMs or integrators enough flexibility to maintain or upgrade the functionality of the safety-related systems, without incurring considerable added costs to an overall system. 
         [0004]    Specifically, functional safety standards require time consuming design and certified validation, where no integration with associated non-safety related applications exists. Hence, expensive hardware and software designs are required because the safety software and standard functional architecture patterns are dedicated. When upgrades are required to a non-safety related application, both the safety application and the associated non-safety related application must be recertified, thereby adding costs and loss of functional system time to an entity. 
         [0005]    What is sought is a way to separate the safety related application from the associated non-safety related application, so that when the associated non-safety related application requires maintenance and upgrading, the safety related application does not have to be recertified. Thereby, saving an entity much time and labor costs. 
       SUMMARY OF THE INVENTION 
       [0006]    A process for decomposing software comprises the steps of providing a first software module associated with a first logical unit, providing a second software module associated with a second logical unit, instructing the first software module to implement a first safety goal based on a quality management level, and instructing the second software module to implement a second safety goal based on a safety integrity level, wherein the second software module uses at least one input and at least one output of the second logical unit to determine if the second safety goal is satisfied. Consequently, the second software module uses a result of the first software module to determine if the first safety goal has been completed, and the second software module uses at least one algorithm to verify an operational status of the first logical unit. 
         [0007]    Further objects and advantages of the present invention will be apparent from the following description and appended claims, reference being made to the accompanying drawings forming a part of a specification, wherein like reference characters designate corresponding parts of several views. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]      FIG. 1  is a block diagram of a first functional architecture in accordance with present invention; 
           [0009]      FIG. 2  is a block diagram of an MPC5668EG processor in accordance with the present invention; 
           [0010]      FIG. 3  is a listing of user-level and supervisor-level registers of an e200z6 core of the MPC5668EG processor of  FIG. 2 ; 
           [0011]      FIG. 4  is an effective address to real address translation flow diagram in accordance with the present invention; 
           [0012]      FIG. 5  is a virtual address and TLB entry compare process diagram in accordance with the present invention; 
           [0013]      FIG. 6  is an MMU granting of access permissions diagram in accordance with the present invention; 
           [0014]      FIG. 7  is a TLB entry bit fields listing in accordance with the present invention; 
           [0015]      FIG. 8  is a block diagram of a second functional architecture in accordance with the present invention; and 
           [0016]      FIG. 9  is an architectural structure of memory addresses for SG on an e200z0 core in accordance with the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0017]    It is to be understood that the invention may assume various alternative orientations and step sequences, except where expressly specified to the contrary. It is also to be understood that the specific devices and processes illustrated in the attached drawings, and described in the following specification are simply exemplary embodiments of the inventive concepts defined in the appended claims. Hence, specific dimensions, directions or other physical characteristics relating to the embodiments disclosed are not to be considered as limiting, unless the claims expressly state otherwise. 
         [0018]    Table 1 lists some of the abbreviations used throughout the disclosure. 
         [0000]    
       
         
               
             
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 Abbreviations 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 BSP: Board support packages 
               
               
                   
                 ECC: Error correction code 
               
               
                   
                 inet: Internet source 
               
               
                   
                 MMU: Memory management unit 
               
               
                   
                 MSR: Machine status register 
               
               
                   
                 PDF: Portable document format 
               
               
                   
                 PID: Process identifier 
               
               
                   
                 QM: Quality Management 
               
               
                   
                 RAM: Random Access Memory 
               
               
                   
                 RTOS: Real-time operating system 
               
               
                   
                 SG: Safety goal(s) 
               
               
                   
                 SRS: Sharepoint site 
               
               
                   
                 SW-C: Software component(s) 
               
               
                   
                 SW-S/A: Software sensor/actuator component(s) 
               
               
                   
                 TLB: Translation lookaside buffer 
               
               
                   
                 uC: Microcontroller 
               
               
                   
                   
               
             
          
         
       
     
         [0019]    Some of the advantages of the instant invention that will become apparent are the following. Design and validate are only required of a small part of the functional safety related application according to standards known as Safety Integrity Levels (SIL). Design and validation of major parts of the functional safety related application are achieved according to Quality Management (QM) levels. Non-safety related applications (design and validation according to QM level) are integrated with safety related applications. The design for all applications (safety related or not) is achieved with generic hardware/software. Hence, major parts of functional safety related applications are upgraded without re-certification. 
         [0020]      FIG. 1  illustrates a first pattern (functional architecture) in accordance with the present invention that uses the following principles. As indicated by the dashed vertical line separating the SW and SG modules, an SIL decomposition is used to make a split-off between safety-related generic reusable software (called the SW module) and safety-related application specific software (called the SG module), wherein the SW and SG modules have their own separate logical unit (uC). Therefore, it is guaranteed that the SW cannot interfere (such as write code, write memory, and/or write data) with the SG. 
         [0021]    Also, the SW implements safety goals in a generic functional way according to the QM level. Thereby, the SG implements safety goals in a dedicated application-specific way according to the SIL level on three levels. 
         [0022]    Regarding safety-related function monitoring, the SG uses inputs and outputs of its logical unit in order to diagnose if the safety goals are still satisfied. Regarding safety-related application monitoring, the SG uses intermediate results of the SW in order to diagnose if the safety goals are satisfied. Regarding generic application monitoring, the SG uses a question-answer algorithm to check if the SW logical unit is working correctly. 
         [0023]    To obtain these results, the following logical entities exist, uC (logical unit) modules are hardware, OS (operating system) module that is developed according to the SIL level, BSP (board support packages) modules that are also developed according to the SIL level, SW (software) module that is developed according to QM level, and SG module that is developed according to the SIL level. 
         [0024]      FIG. 2  illustrates the specifics for a global memory manager controller MPC5668EG implemented in both of the preferred embodiments that are respectively illustrated in  FIGS. 1 and 8 . In the supervisor mode/user mode, an e200z6 core (see MASTERS box in upper portion of  FIG. 2 ) defines the following two levels of programming environments. 1) a user level that defines the base user-level instruction set, registers, data types, memory conventions, and the memory and programming models seen by application programmers and 2) a supervisor level that defines supervisor-level resources typically required by an operating system, i.e., the memory management model, supervisor level registers, and the exception model. However, one skilled in the art recognizes that a different global memory manager controller having the hereinto described elements and functionality of the MPC5668EG device could be used in place thereof. 
         [0025]      FIG. 3  shows the e200z6 core register set for the MPC5668EG controller, which indicates registers that are accessible in supervisor mode and those accessible in user mode. The MSR register of the e200z6 core of the MPC5668EG controller, which contains a “problem state” (PR) bit where a “0” indicates that the processor is in a supervisor mode, where any instruction can be executed, and any resource (for example, general purpose GPRs, supervisor purpose SPRs, machine status MSR registers) can be accessed. On the other hand, the “1” bit indicates that the processor is in a user mode, where no privileged instructions can be executed, and no access to any privileged resources is permitted. 
         [0026]    The MMU, which is shown in the “Masters” block of the MPC5668EG processor in  FIG. 2 , is utilized in the present invention to achieve a clear separation between safety-related software and other QM software. To achieve this separation, several architectural choices have been made that impact the requirements for the MPC5668EG processor. The MPC5668EG processor utilizes the supervisor/user mode, MMU, dual RAM, and dual cores (e200z6 and e200z0), wherein the MPC5668EG provides an MMU with 32-bit effective addresses that are translated to 32-bit real addresses using a 41-bit interim virtual address (see  FIG. 4 ), the MMU may only be available to the e200z6 core and not the e200z0 core, a PID (process identifier) is associated with each effective address (instruction or data), the e200z6 core implements a single PID register (called PID0), where several values for PID0 are defined herebelow. 
         [0027]    Further, the translation is done based on TLB entries, specifically, if the PID value in the PID0 matches with a TLB entry in which all of the other criteria are met (see  FIG. 6 ), then that entry will be used for translation. If the translation match was successful, then permission bits are checked. A hit to multiple TLB entries is considered to be a programming error (see  FIG. 5 ), wherein, if this occurs, the TLB generates an invalid address and TLB entries may be corrupted (an exception will not be reported). 
         [0028]    Regarding the MMU configuration, the TLB entries need to be defined at initialization time. An example of a TLB entry is shown in the listing of  FIG. 7 . Also, the MPC5668EG has two SRAM units; one unit with 80 KB on board and a second unit with 512 KB on board, where both units are provided by the ECC. It is preferred that both SRAM units are to be used and that the ECC, along with both e200z6 core and e200z0 cores are to be supported. 
         [0029]    An architectural overview of a second pattern is given in  FIG. 8  where it is illustrated as a functional architecture that is in accordance with the present invention that uses the following principles. As indicated by the dashed vertical line separating the SW-S/A (sensors/actuators), SW-C (components), and a dRTE (Dana run time environment) module from the SG. The SW-S/A, SW-C, and dRTE modules are considered as developed according to QM standards. The OS, both BSP&#39;s, and SG modules are considered as developed according to SIL standards. Therefore, as in the first functional architectural pattern of  FIG. 1 , an SIL decomposition is used to make a split-off between a safety-related generic reusable software SW-S/A, SW-C and the safety-related application specific software SG, wherein these SW&#39;s and the SG have their own separate logical unit. Therefore, it is guaranteed that the SW&#39;s cannot interfere (such as write code, write memory, and/or write data) with the SG. 
         [0030]    The second pattern architecture allows the SW-S/A, SW-C, and dRTE modules and OS, both BSP&#39;s, and SG modules to reside in the same memory space (code and data space), and on the same uC, without the S/A, SW-C, and dRTE modules being able to corrupt the OS, both BSP&#39;s, and SG modules. 
         [0031]    For the second pattern, the SG runs on a separate (e200z0) core of the MCP5668EG, where the SW-C only communicates within itself by means of the dRTE. Further, the SW-S/A makes a link between the left BSP and the SW-C. Although the S/A, SW-C, and dRTE are running in supervisor mode (which is discussed in detail herebelow), the S/A, SW-C, and dRTE are shown separately in  FIG. 8 . 
         [0032]    System requirements for the second pattern are to support both the user mode/supervisor mode features, wherein both cores e200z6 and e200z0 are supported, both SRAM units are given ECC support, and the MMU feature is supported. Also, architecture support is given to both the user mode/supervisor mode, both cores e200z6 and e200z0, the 80 KB SRAM and the 512 KB SRAM, both with ECC. The MMU in the MCP5668EG of the second pattern is integrated with Actia (Automotive Corporation of France) BSP modules. 
         [0033]      FIG. 9  illustrates the second pattern from a memory address space point-of-view where the following items are defined. The BSP is the driver code/memory, the OS is supplied by RTOS, SG is the safety-critical code/memory, SW-S/A is the sensor and actuator software components code/memory, SW-C module is the application software components. 
         [0034]    OS interrupts run in supervisor mode, BSP interrupts run in supervisor mode, and the SW-S/A runs in supervisor mode, where the SW-S/A is the only software component(s) that may access BSP. Also, the SW-S/A may read and write the shared memory. 
         [0035]    The SW-C runs in user mode but may not access BSP, nor read and write the shared memory. The SG runs in supervisor mode and may access BSP and may read the shared memory. 
         [0036]    The second architectural concept of  FIG. 9 , taken from a memory address space point of view, has access rights to various memory address spaces, for the different modules. As shown down the left side of  FIG. 9 , the rights are defined as—SR: Supervisor read, SW: Supervisor write, SX: Supervisor execute, UR: User read, UW: User write, UX: User execute. These access rights for the different modules in  FIG. 9 , are as follows. 
         [0037]    The following memory address spaces have SR,SX (shown in normal font orientation)—lower BSP and OS. The following memory address spaces have SR, SX (shown in italicized font orientation)—lower BSP and SW-S/A. The following memory address space has UR,UX (shown in bold font orientation)—lower SW-C. The following memory address spaces have SR,SW (shown in normal font orientation)—upper BSP, SHARED, OS, and both HARDWARE REGISTERS. The following memory address spaces have SR,SW (shown in italicized font orientation)—upper BSP, SW-S/A, SHARED, and both HARDWARE REGISTERS. The following memory address space has UR,UW (shown in bold font orientation)—upper SW-C and SHARED. SG has rights on the entire memory address space on the e200z0 core, with no MMU (shown in a dashed box on the right of the memory address space). 
         [0038]    The memory address space of  FIG. 9  is configured as a static configuration, and is based on a linker output. This provides the user flexibility to define the regions, rights and the corresponding sizes. 
         [0039]    Only BSP configures the MMU, such that when a miss is detected by the MMU, the BSP makes sure that the controller resets. The OS will configure the user and supervisor mode for the SW-S/A and SW-C and the OS will set the corresponding PID. 
         [0040]    The basic safety strategy plans are: 1) ASIL (ISO 26262) decomposition principle is used to make a split-off between safety-related generic re-usable software (while following the QM process of Dana dFLAME software) and safety-related application specific software (implementing specifically the safety goals for a specific application while following an SIL process in dFLAME. 2) The safety-related generic re-usable software is mapped onto the SW-C and SW-S/A modules. 3) The safety-related application specific software is mapped onto the SG module. 4) The SW-C and SW-S/A cannot corrupt the SG code space and memory space. 5) The ECC is used for all entities, for both code space and memory space. 6) The SW-C and SW-S/A run on the e200z6 core. 7) The SG runs on the e200z0 core. 8) The SW-C and SW-S/A use the 512 KB SRAM unit. 9) The SG uses the 80 KB SRAM unit. 10) Both cores monitor each other periodically. 11) BSP is developed according to SIL. The monitoring of both cores is also known as “controller monitoring” (for example, E-Gas monitoring concept for engine management systems of gasoline and diesel engines). 
         [0041]    This type of monitoring is function (application) independent, by way of question-answer algorithms. 
         [0042]    Consequently, SG implements the safety goals in an application-specific way where two levels are defined: 1) Outputs are directly correlated to inputs and checked for safe behavior. 2) Function monitoring where Intermediate results in the SW-C and SW-S/A are checked for safe behavior. 
         [0043]    Safety-related data that comes over CAN (e.g. engine speed) must be both available for the SW-S/A and SG. The callback of the CAN is to be developed according to SIL and specifically route safety related data to SG. 
         [0044]    BSP is to be able to support both calls from SW-S/A and SG. 
         [0045]    Consequently, the advantages of the instant invention are that the design and validation are only required of a small part of the functional safety related application according to SIL. The major parts of the functional safety related application are achieved according to QM levels and non-safety related applications are integrated with safety related applications. The design for all applications (safety related or not) is achieved by way of generic hardware/software. Hence, major parts of functional safety related applications are upgraded without re-certification. Thereby, saving an entity much time and labor costs. 
         [0046]    In accordance with the provisions of the patent statutes, the present invention has been described in what is considered to represent its preferred embodiments. However, it should be noted that the invention can be practiced otherwise than as specifically illustrated and described without departing from its spirit or scope.