Abstract:
A sensing circuit with independent write-back capability includes a write back function block having a write-back output signal, a sense amplifier that receives an input and a reference signal. The sense amplifier generates an output signal and the write back function block further receives this output signal. An optional data buffer also receives the output signal.

Description:
BACKGROUND 
     The digital differential comparator, shown in FIG. 1, has been used in Dynamic Random-Access memories (DRAMs), as well as Static Random-Access memories (SRAMs). However, this circuit usually finds application in the data path external to the memory array itself, amplifying the data signal received from the memory array and passing it on to the output buffer. Since this circuit lacks any ability to write-back onto the input nodes, and since it is somewhat more complex than the traditional latching sense amplifier, shown in FIG. 2, it does not normally find use in the memory array itself. 
     Ferroelectric memories are superior to EEPROMs and Flash memories in terms of write-access time and overall power consumption. They are used in applications where a non-volatile memory is required with these features, e.g. digital cameras and contact less smart cards. Contact less smart cards require non-volatile memories with low power consumption as they use only electromagnetic coupling to power up the electronic chips on the card. Digital cameras require both low power consumption and fast frequent writes in order to store and restore an entire image into the memory in less than 0.1 seconds. 
     A typical read access of a ferroelectric memory consists of a write access followed by sensing. To illustrate, a “0” is written to the ferroelectric capacitor to discover the original data content of the memory cell. If the original content of the memory cell is a “1”, writing a “0” reverses the direction of the polarization within the ferroelectric capacitor. This induces a large current spike on the sense wire. On the other hand, there is no current spike on the sensing wire if the original content of the ferroelectric capacitor was also a “0”. Therefore, by sensing the presence of a current spike on the sensing wire, the original data of the accessed ferroelectric capacitor are determined. 
     The read operation as described is destructive since a “0” is written to any memory cell that is accessed for a read. The original data, however, are saved in the sense amplifier and can be restored back into the accessed memory cell. In other words, a read access is only complete after the second write that restores the original data. 
     SUMMARY 
     A sensing circuit with independent write-back capability includes a sense amplifier that receives an input and a reference signal and a tri-statable write-back block receiving a write enable signal and the sense amplifier&#39;s output signal. An optional data buffer also receives the sense amplifier&#39;s output signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a digital differential comparator of the prior art. 
     FIG. 2 illustrates as prior art latching sense amplifier. 
     FIG. 3 illustrates a functional block diagram of the present invention. 
     FIG. 4 illustrates the write-back function block shown in FIG.  3 . 
     FIG. 5 illustrates the sense amplifier shown in FIG.  4 . 
     FIG. 6 illustrates the optional data buffer shown in FIG.  5 . 
     FIG. 7 illustrates the optional data buffer  16  shown in FIG.  3 . 
    
    
     DETAILED DESCRIPTION 
     The optimum number of cells per bit line of a ferroelectric memory tends to be larger than that of a DRAM. Therefore, a somewhat more complex sense amplifier can be more easily tolerated, since there are fewer partitions of the memory array and the cell efficiency tends to be higher. The higher bit line capacitance of the FeRAM, due to the larger number of bits, means that use of a prior latching sense amplifier (shown in FIG. 2) results in even slower access time. Since an adequate voltage separation between bit line and bit line bar must occur before they can be coupled to the output data path, additional time is required to charge or discharge the heavily loaded bit lines. 
     A functional block diagram lo of the present invention is shown in FIG.  3 . The write-back function block  12  is enabled by input signal WB. During operation, the sense amplifier compares the voltage on the bit line (BL) to the voltage on the reference input (REF). The sense amplifier&#39;s output signal (OUT) is received by the write-back function block  12 . An optional data buffer  16  also receives the output signal. Thus, the heavily loaded bit line is separated from the lightly loaded internal sensing nodes. 
     FIG. 4 illustrates the write-back function block  12  shown in FIG.  3 . Serially connected from power to ground are a first and second p-channel transistor followed by a first and a second n-channel transistor. The BL signal is connected to the node between the second p-channel transistor and first n-channel transistor. The gates of the first p-channel transistor and the second n-channel transistor are tied together to node OUT bar which is the complement of the sense amplifier&#39;s output signal OUT. The gate of the second p-channel transistor receives a control signal write-back bar (WBB) while the gate of the first n-channel transistor receives a control signal write-back (WB). 
     FIG. 5 illustrates the sense amplifier  14  shown in FIG. 3. A third p-channel transistor MP 1  has its source connected to power and its drain connected to the first and second leg. Each leg includes two serially connected p-channel transistors (MP 2 , MP 4 ; MP 3 , MP 5 ) followed by two parallel connected n-channel transistors (MN 3 , MN 1 ; MN 2 , MN 4 ). 
     For the first leg, at the OUT bar port, the node between the drain of the second p-channel transistor MP 4  and the drains of the two parallel connected n-channel transistors MN 3 , MN 1  are connected to the gate of the second p-channel transistor MP 5  of the second leg and the gate of the n-channel transistor MN 2 . For the second leg, at the OUT port, the node between the drain of the second p-channel transistor MP 5  and the drains of the two parallel connected n-channel transistors MN 2 , MN 4  are connected to the gate of the second p-channel transistor MP 4  of the first leg and the gate of the second n-channel transistor MN 1 . 
     FIG. 6 illustrates an alternate embodiment for the sense amplifier shown in FIG.  3 . In addition to the electrical connectivity as described in FIG. 5, a fifth n-channel transistor MN 5  connects nodes N 1  and N 2  and is used for equalization. A sixth n-channel transistor MN 6  is serially connected to the gate of p-channel transistor MP 2 . A seventh n-channel transistor MN 7  is serially connected to the gate of the p-channel transistor MP 3 . The gates of n-channel transistors MN 5 , MN 6 , and MN 7  are connected to EN bar. N-channel transistors MN 6  and MN 7  are isolation devices. 
     FIG. 7 illustrates the optional data buffer  16  shown in FIG. 3. A first and a second p-channel transistor are serially connected between power and port DATA. The gate of the first p-channel transistor receives signal OUT, while the gate of the second p-channel transistor receives signal VDD. Two n-channel transistors are serially connected between port DATA and ground. The gate of the first n-channel transistor connects to OUT while the gate of the second n-channel transistor receives signal YS. 
     In operation, the lack of write-back capability inherent in the standalone sense amplifier is overcome by the addition of the series p-channel and series n-channel transistors tied to BL, which in a memory array would be the bit or data line. WB and WBB are additional complementary control signals that are generated after the sense amplifier has been activated by applying VSS to EN bar and VDD to EN after OUT and OUT bar have been driven to their full logic levels. Simultaneous with the write-back restore on the bit line, data can be accessed via the YS signal and started on its path to the chip&#39;s data output buffer, irrespective of the time required to accomplish the write-back.