Abstract:
A semiconductor package structure includes: a dielectric layer; a metal layer disposed on the dielectric layer and having a die pad and traces, the traces each including a trace body, a bond pad extending to the periphery of the die pad, and an opposite trace end; metal pillars penetrating the dielectric layer with one ends thereof connecting to the die pad and the trace ends while the other ends thereof protruding from the dielectric layer; a semiconductor chip mounted on the die pad and electrically connected to the bond pads through bonding wires; and an encapsulant covering the semiconductor chip, the bonding wires, the metal layer, and the dielectric layer. The invention is characterized by disposing traces with bond pads close to the die pad to shorten bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging encountered in prior techniques.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to semiconductor package structures, and more particularly, to a semiconductor package structure characterized by high quality of wire bonding but not susceptible to solder bridging. 
         [0003]    2. Description of Related Art 
         [0004]    In a conventional lead frame based semiconductor package such as a QFN (Quad Flat Non-lead) package, a semiconductor chip is attached and wire-bonded to a lead frame and encapsulated by an encapsulant, and metal portions around the lead frame are exposed from the encapsulant to serve as contact pads for connection with an external device. Such a semiconductor package structure is advantageously characterized by reduced size, improved electrical performance, and wide application in the industry. 
         [0005]      FIG. 1A  shows a conventional semiconductor package structure as disclosed by U.S. Pat. No. 6,143,981, U.S. Pat. No. 6,424,024, U.S. Pat. No. 6,414,385, U.S. Pat. No. 5,942,794, U.S. Pat. No. 6,420,779, U.S. Pat. No. 6,399,415 and U.S. Pat. No. 6,291,274. 
         [0006]    Referring to  FIG. 1A , a semiconductor chip  11  is disposed on a lead frame  10  and electrically connected to contact pads  101  peripherally provided on the lead frame  10  through bonding wires  12 , and an encapsulant  13  is formed on the lead frame  10  to encapsulate the semiconductor chip  11  and the bonding wires  12 , thereby allowing the side surfaces and bottom surfaces of the contact pads  101  to be exposed from the encapsulant  13 . 
         [0007]      FIG. 1B  is a side view of the semiconductor package structure  1  of  FIG. 1A  connected to a circuit board  15 . Referring to  FIG. 1B , the contact pads  101  are connected to solder pads  151  of the circuit board  15  through a solder material  14 . However, since the contact pads are closely arranged and do not protrude from the bottom surface of the semiconductor package structure  1 , when the semiconductor package structure  1  is soldered to the circuit board  15 , the gap between the contact pads  101  and the solder pads  151  of the circuit board  15  is so small that it is difficult to control the gap. As a result, the reliability of the solder joints is low, the solder joints are easy to crack, and the soldering situation is difficult to check. Due to the small gap between the semiconductor package structure  1  and the circuit board  15 , the solder material  14  overflows readily to thereby cause solder bridging. 
         [0008]    Further, the semiconductor package structure  1  cannot provide array arranged contact pads and accordingly cannot provide a semiconductor package structure with high density I/O connections. 
         [0009]    Accordingly, U.S. Pat. No. 6,498,099, U.S. Pat. No. 7,049,177, U.S. Pat. No. 6,238,952, U.S. Pat. No. 6,700,188 and U.S. Pat. No. 6,777,265 disclose a semiconductor package structure, as shown in  FIGS. 2A and 2B . 
         [0010]      FIG. 2A  is a cross-sectional view of a semiconductor package structure  2  and  FIG. 2B  is a top view of the semiconductor package structure  2 . Referring to  FIGS. 2A and 2B , half of the thickness of the lead frame  20  is etched away; a semiconductor chip  21  is disposed on the lead frame  20  and electrically connected to contact pads  201  peripherally provided on the lead frame  20  through bonding wires  22 ; an encapsulant  23  is formed on the lead frame  20 ; and then the semiconductor package structure  2  is etched for a second time such that each of the contact pads  201  protrudes from the bottom of the semiconductor package structure  2  by about half of the thickness of the lead frame  20 . Further, the contact pads  201  can be arranged in array. 
         [0011]    However, although a certain gap is provided between the contact pads and the circuit board and array-arranged contact pads are provided, since long bonding wires are required to electrically connect the semiconductor chip to the contact pads located far away, it adversely affects the electrical performance of the package structure. Further, due to tangling of the bonding wires, it is difficult for the package structure to provide high density I/O connections. 
         [0012]    Therefore, it is imperative to overcome the above drawbacks of the prior art. 
       SUMMARY OF THE INVENTION 
       [0013]    In view of the above drawbacks of the prior art, the present invention provides a semiconductor package structure, which comprises: a dielectric layer having a third surface and an opposite fourth surface; a metal layer disposed on the third surface and having a die pad and a plurality of traces, each of the traces comprising a trace body, a bond pad extending to the periphery of the die pad and a trace end opposite to the bond pad; a plurality of metal pillars penetrating the third surface and the fourth surface of the dielectric layer, wherein one ends of the metal pillars exposed from the third surface connect to the die pad and the trace ends, respectively, and the other ends of the metal pillars protrude from the fourth surface, respectively; a semiconductor chip mounted on the die pad; a plurality of bonding wires electrically connecting the semiconductor chip to the bond pads; and an encapsulant covering the semiconductor chip, the bonding wires, the metal layer and the third surface of the dielectric layer. 
         [0014]    The semiconductor package structure can further comprise a plurality of metal pads disposed on the ends of the metal pillars protruding from the fourth surface, respectively. 
         [0015]    The metal pillars can be made of copper; the dielectric layer can be made of a polymer material comprising an epoxy resin; and the metal layer and the metal pads can be made of one or more selected from the group consisting of Au, Pd, and Ni. 
         [0016]    In addition, the contact pad areas are arranged in array to surround the die mounting area, and the bond pads are disposed at the periphery of the die pad, thereby shortening the bonding wires electrically connecting the semiconductor chip and the bond pads. 
         [0017]    The present invention further provides a semiconductor package structure, which comprises: a dielectric layer having a third surface and an opposite fourth surface, wherein the third surface has a die mounting area and a plurality of contact pad areas; a plurality of traces disposed on the third surface, each of the traces comprising a trace body, a bond pad extending into the die mounting area and a trace end opposite to the bond pad; a plurality of metal pillars penetrating the third surface and the fourth surface of the dielectric layer, wherein one ends of the metal pillars exposed from the third surface connect to the trace ends, respectively, and the other ends of the metal pillars protrude from the fourth surface, respectively; a semiconductor chip disposed on the bond pads to electrically connect to the traces; and an encapsulant covering the semiconductor chip, the traces and the third surface of the dielectric layer. 
         [0018]    According to the present invention, the bond pads and traces formed at the chip mounting side of the dielectric layer shorten the bonding wires and prevent tangling of the bonding wires, thereby improving the electrical connection quality of the package structure. Further, when the semiconductor package structure is soldered to a circuit board, since the metal pillars protrude from the bottom surface of the dielectric layer, it facilitates the formation of stable solder joints between the metal pillars and the circuit board and prevents solder overflow and bridging. In addition, the present invention provides high density and array arranged I/O connections so as to extend the application range of the semiconductor package structure. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0019]      FIG. 1A  is a cross-sectional view of a conventional semiconductor package structure; 
           [0020]      FIG. 1B  is a side view of the semiconductor package structure of  FIG. 1A  connecting to a circuit board; 
           [0021]      FIGS. 2A and 2B  are a cross-sectional view and top view of another conventional semiconductor package structure; 
           [0022]      FIGS. 3A to 3G  are cross-sectional views showing a semiconductor package structure and a fabrication method thereof according to a preferred embodiment of the present invention, wherein FIG.  3 E′ is a top view,  FIG. 3E  is a cross-sectional view taken along line  3 E- 3 E of FIG.  3 E′; and 
           [0023]      FIGS. 4A to 4G  are cross-sectional views showing a semiconductor package structure and a fabrication method thereof according to another embodiment of the present invention, wherein FIG.  4 E′ is a top view,  FIG. 4E  is a cross-sectional view taken along line  4 E- 4 E of FIG.  4 E′. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0024]    The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those in the art after reading this specification. 
         [0025]      FIGS. 3A to 3G  are cross-sectional views showing a semiconductor package structure and a fabrication method thereof according to a preferred embodiment of the present invention, wherein FIG.  3 E′ is a top view, and  FIG. 3E  is a cross-sectional view taken along line  3 E- 3 E of FIG.  3 E′. 
         [0026]    Referring to  FIG. 3A , a metal plate  30  having a first surface  30   a  and an opposite second surface  30   b  is provided, wherein the first surface  30   a  has a die mounting area  301  and a plurality of contact pad areas  302 . The metal plate  30  can be made of copper. 
         [0027]    Referring to  FIG. 3B , the metal plate  30  is patterned from the first surface  30   a  towards the second surface  30   b  so as to form a plurality of concave portions  300  in the metal plate  30  outside the die mounting area  301  and the contact pad areas  302 , wherein the concave portions  300  surrounding the die mounting area  301  and the contact pad areas  302 . The patterning of the metal plate  30  or the formation of the concave portions  300  can be implemented by means of a resist layer (not shown) and performed by an etching process. Since such a technique is well known in the art, detailed description thereof is omitted herein. 
         [0028]    Referring to  FIG. 3C , a dielectric layer  31  is formed on the patterned metal plate  30 , with the die mounting area  301  and the contact pad areas  302  exposed from the dielectric layer  31 . Specifically speaking, a dielectric layer  31  is coated in the concave portions  300  and on the first surface  30   a , and then a portion of the dielectric layer  31  which is higher than the first surface  30   a  is removed to expose the die mounting area  301  and the contact pad areas  302 . The dielectric layer  31  can be made of a polymer material comprising an epoxy resin. In addition, the higher portion of the dielectric layer  31  can be removed by a grinding process such that the dielectric layer  31  thus ground is flush with the surfaces of the die mounting area  301  and the contact pad areas  302 . 
         [0029]    Referring to  FIG. 3D , a first resist layer  32   a  is formed on the first surface  30   a  and the dielectric layer  31 , and a plurality of first open areas  320   a  is formed in the first resist layer  32   a ; meanwhile, a second resist layer  32   b  is formed on the second surface  30   b , and a plurality of second open areas  320   b  is formed in the second resist layer  32   b  such that the second open areas  320   b  thus formed correspond in position to the die mounting area  301  and the contact pad areas  302 , respectively. 
         [0030]    Referring to FIGS.  3 E and  3 E′, a metal layer  33  is formed in the first open areas  320   a , and a plurality of metal pads  34  is formed in the second open areas  320   b , respectively. The metal layer  33  comprises a die pad  333  corresponding in position to the die mounting area  301  and a plurality of traces  332 . Each of the traces  332  comprises a trace body  3321 , a bond pad  3322  extending to the periphery of the die pad  333 , and a trace end  3323  opposite to the bond pad  3322  and connected to a corresponding one of the contact pad areas  302 . The metal pads  34  correspond in position to the die mounting area  301  and the contact pad areas  302 , respectively. Thereafter, the first resist layer  32   a  and the second resist layer  32   b  are removed. The metal layer  33  and the metal pads  34  can be formed by an electroplating process and can be made of one or more selected from the group consisting of Au, Pd, and Ni, for example, Au/Pd/Ni/Pd. 
         [0031]    Referring to FIG.  3 E′, the contact pad areas  302  are arranged in array to surround the die mounting area  301 , and the bond pads  3322  are disposed at the periphery of the die pad  333  to surround the die pad  333 . 
         [0032]    Referring to  FIG. 3F , a semiconductor chip  35  is mounted on the die pad  333  and electrically connected to the bond pads  3322  through a plurality of bonding wires  36 , and an encapsulant  37  is formed to cover the semiconductor chip  35 , the bonding wires  36 , the metal layer  33  and the dielectric layer  31 . 
         [0033]    Referring to  FIG. 3G , the portions of the metal plate  30  that are not covered by the metal pads  34  are removed so as to form a plurality of metal pillars  303  corresponding in position to the die mounting area  301  and the contact pad areas  302  and protruding from the dielectric layer  31 . Finally, a singulation process is performed to obtain a semiconductor package structure  3 . 
         [0034]    The present invention further discloses a semiconductor package structure  3 , which comprises: a dielectric layer  31  having a third surface  31   a  and an opposite fourth surface  31   b ; a metal layer  33  disposed on the third surface  31   a  and comprising a die pad  333  and a plurality of traces  332 , each of the traces  332  comprising a trace body  3321 , a bond pad  3322  extending to the periphery of the die pad  333 , and a trace end  3323  opposite to the bond pad  3322 ; a plurality of metal pillars  303  penetrating the third surface  31   a  and the fourth surface  31   b  of the dielectric layer  31 , wherein one ends of the metal pillars  303  exposed from the third surface  31   a  are connected to the die pad  333  and the trace ends  3323 , and the surfaces of the exposed ends of the metal pillars  303  are flush with the third surface  31   a , and the other ends of the metal pillars  303  protrude from the fourth surface  31   b ; a semiconductor chip  35  mounted on the die pad  333 ; a plurality of bonding wires  36  electrically connecting the semiconductor chip  35  to the bond pads  3322 ; and an encapsulant  37  covering the semiconductor chip  35 , the bonding wires  36 , the metal layer  33  and the third surface  31   a  of the dielectric layer  31 . 
         [0035]    The semiconductor package structure  3  further comprises a plurality of metal pads  34  disposed on the ends of the metal pillars  303  protruding from the fourth surface  31   b , respectively. 
         [0036]    In the semiconductor package structure  3 , the metal pillars  303  can be made of copper; the dielectric layer  31  can be made of a polymer material comprising an epoxy resin; the metal layer  33  and the metal pads  34  can be made of one or more selected from the group consisting of Au, Pd, and Ni. Preferably, the metal layer  33  and the metal pads  34  are made of the same material. 
         [0037]    Further, referring to FIG.  3 E′, the metal pillars  303  are arranged in array to surround the die pad  333 , and preferably, the bond pads  3322  are disposed at the periphery of the die pad  333  to surround the die pad  333 . 
         [0038]      FIGS. 4A to 4G  are cross-sectional views showing a semiconductor package structure and a fabrication method thereof according to another embodiment of the present invention, wherein FIG.  4 E′ is a top view, and  FIG. 4E  is a cross-sectional view taken along line  4 E- 4 E of FIG.  4 E′. 
         [0039]    Referring to  FIG. 4A , a metal plate  40  having a first surface  40   a  and an opposite second surface  40   b  is provided, wherein the first surface  40   a  has a die mounting area  401  and a plurality of contact pad areas  402 . The metal plate  40  can be made of copper. 
         [0040]    Referring to  FIG. 4B , the metal plate  40  is patterned from the first surface  40   a  towards the second surface  40   b  so as to form a plurality of concave portions  400  in the metal plate  40  outside the contact pad areas  402 , respectively. The patterning of the metal plate  40  or the formation of the concave portions  4300  can be implemented by means of a resist layer (not shown) and performed by an etching process. Since such a technique is well known in the art, detailed description thereof is omitted herein. 
         [0041]    Referring to  FIG. 4C , a dielectric layer  41  is formed on the patterned metal plate  40 , with the contact pad areas  402  exposed from the dielectric layer  41 . Specifically speaking, a dielectric layer  41  is coated in the concave portions  400  and on the first surface  40   a , and then a portion of the dielectric layer  41  which is higher than the first surface  40   a  is removed to expose the contact pad areas  402 . The dielectric layer  41  can be made of a polymer material comprising an epoxy resin. In addition, the dielectric layer  41  can be removed by a grinding process such that the dielectric layer  41  thus ground is flush with the surfaces of the contact pad areas  402 . 
         [0042]    Referring to  FIG. 4D , a first resist layer  42   a  is formed on the first surface  40   a  and the dielectric layer  41 , and a plurality of first open areas  420   a  is formed in the first resist layer  42   a ; meanwhile, a second resist layer  42   b  is formed on the second surface  40   b , and a plurality of second open areas  420   b  is formed in the second resist layer  42   b  such that the second open areas  420   b  thus formed correspond in position to the contact pad areas  402 , respectively. 
         [0043]    Referring to FIGS.  4 E and  4 E′, a plurality of traces  432  is formed in the first open areas  420   a , and a plurality of metal pads  44  is formed in the second open areas  420   b . Each of the traces  432  comprises a trace body  4321 , a bond pad  4322  extending into the die mounting area  401 , and a trace end  4323  opposite to the bond pad  4322  and connected to a corresponding one of the contact pad areas  402 . The metal pads  44  correspond in position to the contact pad areas  402 , respectively. Thereafter, the first resist layer  42   a  and the second resist layer  42   b  are removed. The traces  432  and the metal pads  44  can be formed by an electroplating process and can be made of one or more selected from the group consisting of Au, Pd, and Ni, for example, Au/Pd/Ni/Pd. 
         [0044]    Referring to FIG.  4 E′, the contact pad areas  402  can be arranged in array to surround the die mounting area  401 , and the bond pads  4322  can be arranged in array in the die mounting area  401 . 
         [0045]    Referring to  FIG. 4F , a semiconductor chip  45  is flip-chip mounted on the bond pads  4322  so as to be electrically connected to the traces  432 , and an encapsulant  47  is formed to cover the semiconductor chip  45 , the traces  432  and the dielectric layer  41 . 
         [0046]    Referring to  FIG. 4G  the portions of the metal plate  40  that are not covered by the metal pads  44  are removed so as to form a plurality of metal pillars  403  corresponding in position to the contact pad areas  402  and protruding from the dielectric layer  41 . Finally, a singulation process is performed to obtain a semiconductor package structure  4 . 
         [0047]    The present invention further discloses a semiconductor package structure  4 , which comprises: a dielectric layer  41  having a third surface  41   a  and an opposite fourth surface  41   b , the third surface  41   a  having a die mounting area  401  and a plurality of contact pad areas  402 ; a plurality of traces  432  disposed on the third surface  41   a , each of the traces  432  comprising a trace body  4321 , a bond pad  4322  extending into the die mounting area  401 , and a trace end  4323  opposite to the bond pad  4322 ; a plurality of metal pillars  403  penetrating the third surface  41   a  and the fourth surface  41   b  of the dielectric layer  41 , wherein one end of each of the metal pillars  403  is exposed from the third surfaces  41   a  and connected to the trace ends  4323  of the traces  432 , allowing the exposed surfaces of the ends of the metal pillars  403  to be flush with the third surface  41   a  of the dielectric layer  41 , and the other ends of the metal pillars  403  protrude from the fourth surface  41   b ; a semiconductor chip  45  mounted on the bond pads  4322  and electrically connected to the traces  432 ; and an encapsulant  47  covering the semiconductor chip  45 , the traces  432  and the third surface  41   a  of the dielectric layer  41 . 
         [0048]    The semiconductor package structure  4  can further comprise a plurality of metal pads  44  disposed at the ends of the metal pillars  403  protruding from the fourth surface  41   b , respectively. 
         [0049]    In the semiconductor package structure  4 , the metal pillars  403  can be made of copper; the dielectric layer  41  can be made of a polymer material comprising an epoxy resin; the traces  432  and the metal pads  44  can be made of one or more selected from the group consisting of Au, Pd, and Ni. Preferably, the traces  432  and the metal pads  44  are made of the same material. 
         [0050]    Further, referring to FIG.  4 E′, the metal pillars  403  can be arranged in array to surround the die mounting area  401 , and preferably, the bond pads  4322  are annularly arranged within the die mounting area  401 . 
         [0051]    According to the present invention, the bond pads and traces formed at the chip mounting side of the dielectric layer shorten the bonding wires and prevent tangling of the bonding wires, thereby improving the electrical connection quality of the package structure. Further, when the semiconductor package structure is soldered to a printed circuit board, since the metal pillars protrude from the bottom surface of the dielectric layer, it facilitates the formation of stable solder joints between the metal pillars and the printed circuit board and prevents solder overflow and bridging. In addition, the present invention provides high density and array arranged I/O connections so as to extend the application range of the semiconductor package structure. 
         [0052]    The above description of the specific embodiments is intended to illustrate the preferred implementation according to the present invention but is not intended to limit the scope of the present invention. Accordingly, all modifications and variations completed by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims.