Abstract:
A designing method of a semiconductor integrated circuit is composed of providing a library storing a macro mask pattern for a macro circuit including buffer circuits, selecting one of the buffer circuits as a selected buffer circuit and arranging the macro mask pattern and a third wiring pattern to produce an integrated circuit mask. Each of buffer circuits is composed of first and second wirings apart from each other, a firs semiconductor element selectively supplying the first wiring with a power supply potential in accordance with the output signal and a second semiconductor element selectively supplying the second wiring with a grounded potential in accordance with the output signal. The macro mask pattern includes buffer mask patterns, each of which corresponds to one of the buffer circuits. Each of the buffer mask patterns is composed of a first wiring pattern for the first wiring, and a second wiring pattern for the second wiring. In the integrated circuit mask pattern, the first and second wiring patterns of the selected buffer circuit are connected with each other by the third wiring pattern.

Description:
Background of the Invention  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a designing method of a semiconductor integrated circuit. Particularly, the present invention relates to a designing method of a semiconductor integrated circuit using a library storing a mask pattern of a macro circuit.  
           [0003]    2. Description of the Related Art  
           [0004]    When a layout of a semiconductor integrated circuit is designed, a macro circuit is used which is a circuit block having a certain function. The usage of the macro circuit facilitates design of the layout.  
           [0005]    A layout method for a semiconductor integrated circuit using a macro circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 1-293534) and corresponding Japanese Patent No. 2575180. In the known layout method, mega-cells  101 ,  102  and  103  constituted by combinations of a plurality of standard cells are arranged as shown in FIG. 1. A macro circuit  101  has terminals Pa 1  to Pa 3 , terminals Pb 1  to Pb 3  and terminals Pc 1  to Pc 3 . The terminals Pa 1  to Pa 3 , the terminals Pb 1  to Pb 3  and the terminals Pc 1  to Pc 3  are located in a plurality of sides on a rectangular area defining the macro circuit  101 . Wirings connected to the macro circuit  101  are connected to the terminals Pa 1  to Pa 3 , the terminals Pb 1  to Pb 3  and the terminals Pc 1  to Pc 3  are. The known layout method protects the mounted wiring from bypassing the macro circuit  101 .  
           [0006]    However, an output buffer for outputting a signal from the macro circuit is not noted in the above-mentioned Japanese Laid Open Patent Application (JP-A-Heisei 1-293534) and corresponding Japanese Patent No. 2575180.  
           [0007]    Another layout method for a semiconductor integrated circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 4-78153). In this known layout method, a logical cell array  202 , memories  204 ,  205  and input/output buffer cell  206   s  are mounted in a semiconductor integrated circuit  201 , as shown in FIG. 2. A large number of logical cells  203 , which are small-scale macro cells, are mounted in the logical cell array  202 . The memories  204 ,  205  are large-scale macro cells. The input/output buffer cells  206  are small-scale macro cells. In this known semiconductor integrated circuit, the wiring between the small-scale macro cells is laid so as to bypass the memories  204 ,  205 .  
           [0008]    At first, terminal extension areas  211 ,  212  and  213  are defined around the memories  204  and  205 , as shown in FIG. 3. Terminals of the logical cells  203  and the input/output buffer cells  206 , are extensively laid in the terminal extension areas  211 ,  212  and  213 . Extensive positions  211   a ,  212   a  and  213   a  of the terminal are defined as tip ends of the terminal extension areas  211 ,  212  and  213 .  
           [0009]    Moreover, extensive routes  211   b ,  212   b  and  213   b  are defined from the terminal of the input/output buffer cell  206  to the respective extensive positions  211   a ,  212   a  and  213   a , as shown in FIG. 4.  
           [0010]    Moreover, as shown in FIG. 2, a terminal B of the input/output buffer cell  206  is extended up to the respective extensive positions  211   a ,  212   a  and  213   a  along the extensive routes  211   b ,  212   b  and  213   b . The extended terminal B is referred to as an extensive terminal B 1  hereinafter. The extensive terminal B 1  is connected to a terminal A of the logical cell  203 .  
           [0011]    This known layout method can shorten a time required to find out a wiring route of a wiring for connecting the logical cell  203  and the input/output buffer cell  206 .  
           [0012]    Also, still another layout method for a semiconductor integrated circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 11-260923). In this known layout method for the semiconductor integrated circuit, a spare cell is mounted in addition to usage cells. When the design of the circuit is changed, the spare cell is used to easily change the circuit. This known layout method relates to the layout method for the spare cell.  
           [0013]    A spare cell having a structure shown in FIG. 5 is firstly placed in designing a semiconductor integrated circuit. The spare cell is provided with a P-type MOS transistor  310  and an N-type MOS transistor  302 . A source  301   a  of the P-type MOS transistor  301  and a source  302   a  of the N-type MOS transistor  302  are respectively connected through wirings  307 ,  306  to a ground line  316 . Both the sources  301   a ,  302   a  are electrically separated from a power supply line  315 .  
           [0014]    When a circuit included in the semiconductor integrated circuit is changed, the spare cell is used. When the spare cell is used, its structure is changed as shown in FIG. 6. The source  301   a  of the P-type MOS transistor  301  is separated from the ground line  316  and connected through a wiring  310  to the power supply line  315 . Thus, the spare cell serves as an inverter. The usage of the spare changes the circuit included in the semiconductor integrated circuit.  
           [0015]    When the spare cell placed in this known layout method is at a non-usage state, there is no route through which a current flows from the power supply cell  315  to the ground line  316 . Thus, it is possible to reduce a consumptive current in the semiconductor integrated circuit designed on the basis of this known layout method.  
           [0016]    Also, a semiconductor integrated circuit in which a consumptive current is reduced is disclosed in Japanese Laid Open Patent Application (JP-A-Showa, 62-23131). In this known semiconductor integrated circuit, a usage unit cell  404  and a non-usage unit cell  404 A are mounted as shown in FIG. 7. In the usage unit cell  404 , MISFETs Qp′, Qn′ are connected through a wiring  416 ′ to each other. The MISFETs Qp′, Qn′ constitute an inverter. An output signal of the inverter is outputted from the wiring  416 ′. On the other hand, the non-usage unit cell  404 A contains MISFETs Qp, Qn. A wiring  416  is cut away, and drain areas  410 ,  411  of the MISFETs Qp, Qn are electrically separated from each other. Thus, it is possible to reduce a consumptive current in the semiconductor integrated circuit.  
           [0017]    However, an arrangement of a macro circuit is not noted in Japanese Laid Open Patent Application (JP-A-Heisei, 11-260923 and JP-A-Showa 62-23131).  
         SUMMARY OF THE INVENTION  
         [0018]    An object of the present invention is to provide a wiring method for a semiconductor integrated circuit, in which a wiring included in the semiconductor integrated circuit can be designed so as not to bypass a macro circuit, an apparatus for wiring a semiconductor integrated circuit, and a macro library.  
           [0019]    Another object of the present invention is to provide a wiring method for a semiconductor integrated circuit, which can reduce a consumptive power of a designed semiconductor integrated circuit, an apparatus for wiring a semiconductor integrated circuit, and a macro library.  
           [0020]    Still another object of the present invention is to provide a wiring method for a semiconductor integrated circuit, in which a wiring included in the semiconductor integrated circuit can be designed so as not to bypass a macro circuit, and further a consumptive power of the designed semiconductor integrated circuit is reduced, an apparatus for wiring a semiconductor integrated circuit, and a macro library.  
           [0021]    In order to achieve an aspect of the present invention, a designing method of a semiconductor integrated circuit is composed of providing a library storing a macro mask pattern for a macro circuit including buffer circuits, selecting one of the buffer circuits as a selected buffer circuit and arranging the macro mask pattern and a third wiring pattern to produce an integrated circuit mask. Each of buffer circuits is composed of first and second wirings apart from each other, and first and second semiconductor elements. The first semiconductor element selectively supplies the first wiring with a power supply potential in accordance with the output signal. The second semiconductor element selectively supplies the second wiring with a grounded potential in accordance with the output signal. The macro mask pattern includes buffer mask patterns, each of which corresponds to one of the buffer circuits. Each of the buffer mask patterns is composed of a first wiring pattern for the first wiring, and a second wiring pattern for the second wiring. In the integrated circuit mask pattern, the first and second wiring patterns of the selected buffer circuit are connected with each other by the third wiring pattern.  
           [0022]    The first semiconductor element is desirably a P-channel MISFET including a first source connected to a power supply line having a power supply voltage, a first drain connected to said first wiring, and a first gate having a first gate voltage in response to said output signal.  
           [0023]    The second semiconductor element is desirably an N-channel MISFET including a second source connected to a grounded line, a second drain connected to said first wiring and a second gate having a first gate voltage in response to said output signal.  
           [0024]    The macro mask pattern may be accommodated in a rectangular area having four sides. In this case, one of said plurality of buffer mask patterns is located on one of said four sides, and another one of said plurality of buffer mask patterns is located on another one of said four sides.  
           [0025]    The integrated circuit mask pattern may include a cell mask pattern for a cell included said semiconductor integrated circuit and said third wiring is connected to said cell. In this case, said selected buffer circuit is selected such that said third wiring is as short as possible.  
           [0026]    In order to achieve another aspect of the present invention, a designing apparatus of a semiconductor integrated circuit is composed of a library and an arrangement wiring tool. The library stores a macro mask pattern for a macro circuit. The macro circuit includes an inner circuit outputting an output signal and a plurality of buffer circuits. Each of the plurality of buffer circuits is composed of first and second wirings apart from each other, a first semiconductor element selectively supplying said first wiring with a power supply potential in accordance with said output signal, and a second semiconductor element selectively supplying said second wiring with a grounded potential in accordance with said output signal. The macro mask pattern includes a plurality of buffer mask patterns, each of which corresponds to one of said plurality of buffer circuits. Each of said plurality of buffer mask patterns is composed of a first wiring pattern for said first wiring and a second wiring pattern for said second wiring. The arrangement wiring tool selects one of said plurality of buffer circuits as a selected buffer circuit. The arrangement wiring tool arranges said macro mask pattern and a third wiring pattern for a third wiring to produce an integrated circuit mask pattern based on said library such that said first and second wiring patterns of said selected buffer circuit are connected with each other by said third wiring pattern.  
           [0027]    In order to achieve still another aspect of the present invention, a computer-readable recording medium records a library for designing an integrated circuit. The library is composed of a macro mask pattern for a macro circuit. The macro circuit includes an inner circuit outputting an output signal and buffer circuits. Each of the buffer circuits is composed of first and second wirings apart from each other, and first and second semiconductor elements. The first semiconductor element selectively supplies the first wiring with a power supply potential in accordance with the output signal. The second semiconductor element selectively supplies the second wiring with a grounded potential in accordance with the output signal. The macro mask pattern includes buffer mask patterns, each of which corresponds to one of the buffer circuits. Each of the buffer mask patterns is composed of a first wiring pattern for the first wiring, and a second wiring pattern for the second wiring.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0028]    [0028]FIG. 1 shows a conventional layout method for a semiconductor device;  
         [0029]    [0029]FIG. 2 shows another conventional layout method for a semiconductor device;  
         [0030]    [0030]FIG. 3 shows the other conventional layout method for a semiconductor device;  
         [0031]    [0031]FIG. 4 shows the other conventional layout method for a semiconductor device;  
         [0032]    [0032]FIG. 5 shows a structure of a spare cell used in still another conventional layout method;  
         [0033]    [0033]FIG. 6 shows a structure of a spare cell used in still another conventional layout method;  
         [0034]    [0034]FIG. 7 shows a structure of a spare cell used in yet still another conventional layout method;  
         [0035]    [0035]FIG. 8 shows a method for designing a layout of a semiconductor integrated circuit, according to the present embodiment;  
         [0036]    [0036]FIG. 9 shows a schematic of its macro circuit registered in the arrangement wiring library  25 ;  
         [0037]    [0037]FIG. 10 shows the inner structure of the macro circuit  1 ;  
         [0038]    [0038]FIG. 11 shows a part of an equivalent circuit of the inner portion  2 ;  
         [0039]    [0039]FIG. 12 shows an equivalent circuit at a state when the first outer wiring S 0  is connected to the first output buffer D 00  contained in the macro circuit  1 ;  
         [0040]    [0040]FIG. 13A shows a mask layout before the first outer wiring S 0  is connected to the first output buffer D 00 ; and  
         [0041]    [0041]FIG. 13B shows a mask layout at a state when the first outer wiring S 0  is connected to the first output buffer D 00 .  
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0042]    A designing method of a semiconductor integrated circuit of an embodiment according to the present invention will be described below with reference to the attached drawings.  
         [0043]    The designing method is executed by an integrated circuit designing apparatus  20  shown in FIG. 8. The integrated circuit designing apparatus  20  includes a logic synthesizing tool  23 . A function description design data  21  is inputted to the logic synthesizing tool  23 . In the function description design data  21 , functions of a semiconductor integrated circuit are described in a language of a register transfer level (RTL).  
         [0044]    The logic synthesizing tool  23  refers to a logic synthesizing library  22 , and generates a gate level net list  24  in accordance with the function description design data  21 . In the logic synthesizing library  22 , design information is registered with regard to macro circuits. A logical function for the macro circuit is recorded in the logic synthesizing library  22 . A desirable function is attained by the combination of the macro circuits registered in the logic synthesizing library  22 . In the gate level net list  24 , the connection relation of signal lines between those macro circuits is described. The gate level net list  24  is inputted to an arrangement wiring tool  26 .  
         [0045]    The arrangement wiring tool  26  refers to an arrangement wiring library  25  and executes the arrangement and the wiring of the macro circuit in accordance with the gate level net list  24 . The arrangement wiring library  25  stores therein the information with regard to the arrangement and the wiring for each macro circuit registered in the logic synthesizing library  22 . The arrangement wiring library  25  includes a layout data corresponding to a mask pattern for each macro circuit. The information of a shape, a dimension and a terminal for each macro circuit, and a wiring inhibition area information are registered in the arrangement wiring library  25 . The above-mentioned terminal information includes a position of the terminal, a terminal attribute of an input/output, a capacity of the capacity, and an output impedance.  
         [0046]    The arrangement wiring tool  26  outputs a layout data  27  and a delay database  28 . The layout data  27  indicates a mask pattern for a semiconductor integrated circuit designed integrated circuit designing apparatus  20 . The delay database  28  stores therein a delay data for each net. The delay database  28  is used for logical verification.  
         [0047]    In this case, a computer is used as the above-mentioned logic synthesizing tool  23  and the arrangement wiring tool  26 . Also, the logic synthesizing library  22  and the arrangement wiring library  25  is stored in a computer-readable medium and accessed by the computer.  
         [0048]    [0048]FIG. 9 shows a schematic of the macro circuit registered in the arrangement wiring library  25 . The macro circuit  1  is a macro circuit for a SRAM (Static Random Access Memory). An inner portion  2  of the macro circuit  1  is provided with first to eighth output buffers D 00  to D 07  and first to eighth auxiliary output buffers D 00 ′ to D 07 ′ for outputting an 8-bit signal. The first output buffers D 00  is connected to the first auxiliary output buffers D 00 ′ in the inner portion  2 . The second output buffers D 01  is connected to the second auxiliary output buffers D 01 ′ in the inner portion  2 . The third output buffers D 02  is connected to the third auxiliary output buffers D 02 ′ in the inner portion  2 . The fourth output buffers D 03  is connected to the fourth auxiliary output buffers D 03 ′ in the inner portion  2 . The fifth output buffers D 04  is connected to the fifth auxiliary output buffers D 04 ′ in the inner portion  2 . The sixth output buffers D 05  is connected to the sixth auxiliary output buffer D 05 ′ in the inner portion  2 . The seventh output buffers D 06  is connected to the seventh auxiliary output buffers D 06 ′ in the inner portion  2 . And, the eighth output buffers D 07  is connected to the eighth auxiliary output buffers D 07 ′ in the inner portion  2 .  
         [0049]    The macro circuit  1  is accommodated in a rectangular area having four sides. The first to eighth output buffers D 00  to D 07  are located on the lower one of the four sides. The first to eight auxiliary output buffers D 00 ′ to D 07 ′ are located on the upper one of the four sides.  
         [0050]    [0050]FIG. 10 shows the inner structure of the macro circuit  1  in further detail. The inner portion  2  of the macro circuit  1  has first to fourth memory banks B 0  to B 3 . The first bank B 0  is composed of first to eighth memory areas MA 00  to MA 07  and first to eighth output buffers Q 00  to Q 07 . The first to eighth output buffers Q 00  to Q 07  respectively output signals from the first to eighth memory areas MA 00  to MA 07 . The second bank B 1  is composed of 11th to 18th memory areas MA 10  to MA 17  and 11th to 18th output buffers Q 10  to Q 17 . The 11th to 18th output buffers Q 10  to Q 17  respectively output signals from the 11th to 18th memory areas MA 10  to MA 17 . The third bank B 2  is composed of 21st to 28th memory areas MA 20  to MA 27  and 21st to 28th output buffers Q 20  to Q 27 . The 21st to 28th output buffers Q 20  to Q 27  respectively output signals from the 21st to 28th memory areas MA 20  to MA 27 . And, the fourth bank B 3  is composed of 31st to 38th memory areas MA 30  to MA 37  and 31st to 38th output buffers Q 30  to Q 37 . The 31st to 38th output buffers Q 30  to Q 37  respectively output signals from the 31st to 38th memory areas MA 30  to MA 37 .  
         [0051]    A control circuit  3  receives a clock signal CLK, a write signal WE, a write data DI, an address signal AD and an enable signal EN. The signals and the data are transferred to the first to fourth banks B 0  to B 3 .  
         [0052]    The first output buffer Q 00 , the 11th output buffer Q 10 , the 21st output buffer Q 20  and the 31st output buffer Q 30  are connected to the first output buffer D 00  and the first auxiliary output buffer D 00 ′. The second output buffer Q 01 , the 12th output buffer Q 11 , the 22nd output buffer Q 21  and the 32nd output buffer Q 31  are connected to the second output buffer D 01  and the second auxiliary output buffer D 01 ′. The third output buffer Q 02 , the 13th output buffer Q 12 , the 23rd output buffer Q 22  and the 33rd output buffer Q 32  are connected to the third output buffer D 02  and the third auxiliary output buffer D 02 ′. The fourth output buffer Q 03 , the 14th output buffer Q 13 , the 24th output buffer Q 23  and the 34th output buffer Q 33  are connected to the fourth output buffer D 03  and the fourth auxiliary output buffer D 03 ′. The fifth output buffer Q 04 , the 15th output buffer Q 14 , the 25th output buffer Q 24  and the 35th output buffer Q 34  are connected to the fifth output buffer D 04  and the fifth auxiliary output buffer D 04 ′. The sixth output buffer Q 05 , the 16th output buffer Q 15 , the 26th output buffer Q 25  and the 36th output buffer Q 35  are connected to the sixth output buffer D 05  and the sixth auxiliary output buffer D 05 ′. The seventh output buffer Q 06 , the 17th output buffer Q 16 , the 27th output buffer Q 26  and the 37th output buffer Q 36  are connected to the seventh output buffer D 06  and the seventh auxiliary output buffer D 06 ′. And, the eighth output buffer Q 07 , the 18th output buffer Q 17 , the 28th output buffer Q 27  and the 38th output buffer Q 37  are connected to the eighth output buffer D 07  and the eighth auxiliary output buffer D 07 ′.  
         [0053]    The first output buffer D 00  and the first auxiliary output buffer D 00 ′ output the substantially same signals to a rectangular area in which the macro circuit  1  is mounted. If a wiring is laid for connecting another circuit to the macro circuit  1 , the wiring can be also connected to any of the first output buffer D 00  and the first auxiliary output buffer D 00 ′. The similar configuration can be established between the second to eighth output buffers D 01  to D 07  and the second to eighth auxiliary output buffers D 01 ′ to D 07 ′. Thus, it is possible to avoid the wiring connected to the macro circuit  1  from being laid so as to bypass the macro circuit  1 .  
         [0054]    [0054]FIG. 11 shows a part of an equivalent circuit of the inner portion  2 . FIG. 11 shows the part of the equivalent circuit in relation to a first output buffer Q 00 , an 11th output buffer Q 10 , a 21st output buffer Q 20 , a 31st output buffer Q 30 , a first output buffer D 00  and a first auxiliary output buffer D 00 ′, in the inner portion  2 .  
         [0055]    The first output buffer Q 00  is constituted by a gate circuit to which an input signal Q 00  and an enable signal EN 0  are inputted. The input signal /Q 00  is generated by the memory area MA 00 . The 11th output buffer Q 10  is constituted by a gate circuit to which an input signal /Q 10  and an enable signal EN 1  are inputted. The input signal /Q 10  is generated by the memory area MA 10 . The 21st output buffer Q 20  is constituted by a gate circuit to which an input signal /Q 20  and an enable signal EN 2  are inputted. The input signal /Q 20  is generated by the memory area MA 20 . And, the 31st output buffer Q 30  is constituted by a gate circuit to which an input signal /Q 30  and an enable signal EN 3  are inputted. The input signal /Q 30  is generated by the memory area MA 30 .  
         [0056]    The first output buffer D 00  includes a buffer circuit composed of an N-type CMOS field effect transistor TR 0  and a P-type CMOS field effect transistor TR 1 . The first auxiliary output buffer D 00 ′ includes a buffer circuit composed of an N-type CMOS field effect transistor TR 2  and a P-type field effect transistor TR 3 .  
         [0057]    Gates of the transistor TR 0  and the transistor TR 1  are connected through an inner data line DB 0  to the first output buffer Q 00 , the 11th output buffer Q 10 , the 21st output buffer Q 20  and the 31st output buffer Q 30 . A power supply voltage VDD is applied to a source of the transistor TR 1 . A source of the transistor TR 0  is connected to a ground GND. A drain of the transistor TR 0  forms an open first wiring end. A drain of the transistor TR 1  forms an open second wiring end. The first and second wiring ends composed of a pair of open drains can be connected by an outer wiring, as described later. The pair of drains forms an output wiring for sending an output signal corresponding to an input signal.  
         [0058]    Gates of the transistor TR 2  and the transistor TR 3  are connected through the inner data line DB 0  to the first output buffer Q 00 , the 11th output buffer Q 10 , the 21st output buffer Q 20  and the 31st output buffer Q 30 . The power supply voltage VDD is applied to a source of the transistor TR 3 . A source of the transistor TR 2  is connected to the ground GND. A drain of the transistor TR 3  and a drain of the transistor TR 2  are opened. The pair of open drains can be connected by an outer wiring, as described later.  
         [0059]    [0059]FIG. 13A shows a mask pattern for the output buffer D 00  stored in the arrangement wiring library  25 . The gate  41  of the transistor TR 0  and the gate  44  of the transistor TR 1  are connected to each other. The source  42  of the transistor TR 0  is connected to the grounded line  47 . The source  45  of the transistor TR 1  is connected to a power supply line  48  which is provided with the power supply voltage VDD. The first wiring  49  is connected to the drain  43 . The second wiring  50  is connected to the drain  46 . The first and second wiring  49  and  50  are apart from each other. The terminal IN is connected to the above mentioned output buffers Q 00 , Q 10 , Q 20  and Q 30 . The transistor TR 0  and TR 1  are exclusively turned on or off in response to a signal inputted to the terminal IN. The output buffers D 01  to D 07  and the auxiliary output buffers D 00 ′ to D 07 ′ has the same mask pattern as the output buffers D 00 .  
         [0060]    A semiconductor integrated circuit is designed by the above-mentioned integrated circuit designing apparatus  20  as described below.  
         [0061]    As shown in FIG. 8, the gate level net list  24  is generated by the logic synthesizing tool  23  in accordance with the function description design data  21 . The gate level net list  24  contains a net list corresponding to the macro circuit  1 .  
         [0062]    Next, the layout data  27  is generated by the arrangement wiring tool  26 . In response to the net list, the layout data  27  includes the mask layout pattern of the macro circuit  1  registered in the arrangement wiring library  25  is included in the layout data  27 .  
         [0063]    Moreover, one of the output buffer D 00  and the auxiliary output buffer D 00 ′ is selected as a first selected output buffer. A first outer wiring S 0  is connected to the first selected output buffer.  
         [0064]    Also, one of the output buffer D 01  and the auxiliary output buffer D 01 ′ is selected as a second selected output buffer. A second outer wiring S 1  is connected to the second selected output buffer.  
         [0065]    Also, one of the output buffer D 02  and the auxiliary output buffer D 02 ′ is selected as a third selected output buffer. A third outer wiring S 2  is connected to the third selected output buffer.  
         [0066]    Also, one of the output buffer D 03  and the auxiliary output buffer D 03 ′ is selected as a fourth selected output buffer. A fourth outer wiring S 3  is connected to the fourth selected output buffer.  
         [0067]    Also, one of the output buffer D 04  and the auxiliary output buffer D 04 ′ is selected as a fifth selected output buffer. A fifth outer wiring S 4  is connected to the fifth selected output buffer.  
         [0068]    Also, one of the output buffer D 05  and the auxiliary output buffer D 05 ′ is selected as a sixth selected output buffer. A sixth outer wiring S 5  is connected to the sixth selected output buffer.  
         [0069]    Also, one of the output buffer D 06  and the auxiliary output buffer D 06 ′ is selected as a seventh selected output buffer. A seventh outer wiring S 6  is connected to the seventh selected output buffer.  
         [0070]    Also, one of the output buffer D 07  and the auxiliary output buffer D 07 ′ is selected as a eighth selected output buffer. A eighth outer wiring S 7  is connected to the eighth selected output buffer.  
         [0071]    The outer wiring S 0  to S 8  are connected to other cells included in the integrated circuit designed by the integrated circuit designing apparatus  20 . In this case, the first to eighth selected output buffers are desirably selected such that the outer wiring S 0  to S 8  are as short as possible.  
         [0072]    In the present embodiment, the first to fourth outer wirings S 0  to S 3  are connected to the first to fourth output buffers D 00  to D 03  as in FIG. 9. The fifth to eighth outer wirings S 4  to S 7  are connected to the fifth to eighth auxiliary output buffers D 04 ′ to D 07 ′.  
         [0073]    [0073]FIG. 12 shows an equivalent circuit at a state when the first outer wiring S 0  is connected to the first output buffer D 00  contained in the macro circuit  1 . When the first outer wiring S 0  is connected to the first output buffer D 00 , the first outer wiring S 0  couples the drain of the transistor TR 0  and the drain of the transistor TR 1  to each other. Due to this coupling, a current corresponding to a gate input flows through an output wiring composed of the drain of the transistor TR 0  and the drain of the transistor TR 1 . Thus, an output signal is sent to the first outer wiring S 0 .  
         [0074]    On the other hand, the first outer wiring S 0  is not connected to the first auxiliary output buffer D 00 ′. The open state is maintained between the drains of the transistors TR 2 , TR 3 , namely, between the first wiring and the second wiring. This open state reduces the power consumption caused by the transistors TR 2 , TR 3 .  
         [0075]    [0075]FIG. 13B shows a mask layout at a state when the first outer wiring S 0  is connected to the first output buffer D 00 . The first outer wiring S 0  connects the first and second wiring  49  and  50  are connected to each other through the first outer wiring S 0 . In this state, the first outer wiring S 0  is used as a output terminal for outputting the signals from the output buffers Q 00 , Q 10 , Q 20  and Q 30 .  
         [0076]    Similarly, the disconnected drains of each of the output buffers D 01 , D 02 , D 03  and the auxiliary output buffers D 04 ′, D 05 ′, D 06 ′, and D 07 ′ are respectively connected by the outer wiring S 1 , S 2 , S 3 , S 4 , S 5 , S 6  and S 7 . Also, the disconnected drains of each of the output buffers D 01 , D 02 , D 03  and the auxiliary output buffers D 04 ′, D 05 ′, D 06 ′ are left opened. The disconnected drains reduce the power consumption.  
         [0077]    When a plurality of output terminals to one signal are mounted in a macro block, a capacitance difference is induced because of a difference between wiring lengths within the macro circuit. The capacitance difference results in a condition that a signal delay is different for each output terminal. In the semiconductor apparatus according to the present invention, a parameter with regard to a signal delay is set so as to obtain a constant delay performance, even if a signal is taken out of any of the plurality of output terminals. The parameter is stored in the logic synthesizing library  22  or the arrangement wiring library  25 , and included in the delay database  28 .  
         [0078]    Although the invention has been described in its preferred form with a certain degree of particularity, it is understood that the present disclosure of the preferred form has been changed in the details of construction and the combination and arrangement of parts may be resorted to without departing from the spirit and the scope of the invention as hereinafter claimed.