Abstract:
A system is provided for enabling a plurality of wireless communication transceivers to communicate. The system includes at least three wireless communication transceivers operable to communicate using a time division multiple access (TDMA) protocol. The at least three wireless communication transceivers are operable to alternatively serve as a master device according to a predetermined scheme to establish time slots for each of the transceivers, thereby enabling the at least three wireless communication transceivers to communicate in a conference-like manner and without a base station.

Description:
BACKGROUND  
         [0001]    1. Field of Invention  
           [0002]    This invention relates to the field of wireless communications, specifically to multiple wireless handset time division multiple access (TDMA) conferencing communications.  
           [0003]    2. Prior Art  
           [0004]    Radios of the past have broadcasted their signals from one user to another user or to a group of users. Two-way communications were established between two entities by taking turns talking and by using a push-to-talk button. Group conversations could not be conducted without some order of taking turns. Conferencing (simultaneous conversation) has only been possible when a base station radio device has been employed to automatically control or connect the parties in a way that all parties can speak and be heard simultaneously. Mobility of the radios in the group and therefore the mobility of the users was restricted to staying in range of the base station.  
           [0005]    Cellular telephone companies use TDMA to allow many individuals to communicate digitized voice information to a central station. This usually requires one of the time slots in the TDMA system to be used for overhead to communicate to each radio transceiver which time slot each radio will use for voice communication. These systems also use a separate transmit and receive channel. Communication between users must go through the central location.  
           [0006]    Previously, devices such as cordless telephones have restricted the operation of the portable handset to being within range of the base station (a telephone base unit that is connected to the wired telephone line). In cases where a cordless telephone system included more than one handset, the handsets could not communicate with each other without communicating through the base station. This severely limited the use of the radio handsets. The handsets communicate with each other or conference as a group without the base station because the base station is used to control the communication link. In some systems, the base station can give control to a handset to create a handset-to-handset communication link. This same problem of requiring the use of a central control or base station exists with other radio communications systems and appliances.  
         SUMMARY OF THE INVENTION  
         [0007]    The invention enables a group of radios to communicate in a conference-like manner without having to take turns using a push-to-talk button or being in the presence of a base station. For example, handsets for cordless telephones can now be used as personal radios to communicate with other handsets associated with the same cordless telephone system. This allows these handsets to be used away from the base station located at the home or office.  
         OBJECTS AND ADVANTAGES  
         [0008]    It is a principal object of the present invention to provide a radio communication system that will allow several users to communicate over radio links in a full duplex conferencing-type system without using a base unit, and each user can take the radio anywhere and communicate in a conference-like manner to one or more other users who are in range.  
           [0009]    It is another principal object of the present invention to provide a radio communication system that will allow several independent conferencing groups to operate simultaneously. Individual users can switch between different conferencing groups.  
           [0010]    It is another principal object of the present invention to provide a conferencing system where voice data and other types of data can be transmitted to and from transceivers in a communication link. Simultaneous voice/analog and digital data can coexist within a communication link.  
           [0011]    In an application where the present invention is implemented in a cordless telephone, handsets for a cordless telephone system can now be used as personal radios to communicate with other handsets associated with the same cordless telephone system. This allows handsets to be used away from the base station located at the home or office. Each handset can be part of a conference call using the base station to connect the communication link to a telephone line. The transceiver portion of the telephone base unit functions in the same manner as a handset. In the case of a cordless telephone system that has more than one telephone line, the base unit transceiver can simultaneously communicate with handsets conducting a normal telephone call over one telephone line and process digital information from other handsets over a different line.  
           [0012]    A communication system has been described which features one embodiment of the invention. It is to be understood, however, that the scope of the invention is not limited to such a system or to the specific frequencies, circuit designs, values, parameters, etc. suggested, but only by the scope of the following claims. Various other embodiments and modifications thereof will become apparent to persons skilled in the art, and will fall within the scope of invention as defined in the following claims. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]    [0013]FIG. 1 is a block diagram of the preferred embodiment for a TDMA wireless conferencing system;  
         [0014]    [0014]FIG. 2 is a block diagram of the electronics in the preferred embodiment;  
         [0015]    [0015]FIG. 3 is a schematic of a power supply, reset circuit and data discriminator;  
         [0016]    [0016]FIG. 4 is a schematic of a field programmable gate array (FPGA);  
         [0017]    [0017]FIG. 5 is a schematic of a microcontroller and an electrically erasable programmable read only memory (EEPROM);  
         [0018]    [0018]FIG. 6 is a schematic of coders/decoders (codecs) and how their analog outputs are connected together through filters;  
         [0019]    [0019]FIG. 7 is a schematic of a fourth codec which is connected to the codecs in FIG. 6 through a filter. It also shows how the microphone and speaker are connected through amplifiers to the codecs;  
         [0020]    [0020]FIG. 8 is a schematic of a portion of the FPGA which is used for loading parameters;  
         [0021]    [0021]FIG. 9 is a block diagram of four shift register systems used in the FPGA;  
         [0022]    [0022]FIG. 10 is a block diagram of an audio clock generator and an output shift register system used in the FPGA;  
         [0023]    [0023]FIG. 11 is a schematic of each of the shift register systems in FIG. 9;  
         [0024]    [0024]FIG. 12 is a schematic of the output shift register system in FIG. 10;  
         [0025]    [0025]FIG. 13 is a schematic of a portion of the audio clock generator system in FIG. 10  
         [0026]    [0026]FIG. 14 is a schematic of another portion of the audio clock generator system in FIG. 10;  
         [0027]    [0027]FIG. 15 is a block diagram of an input shift register system and of an output shift register system used for radio data and found in the FPGA;  
         [0028]    [0028]FIG. 16 is a schematic of the output shift register system in FIG. 10;  
         [0029]    [0029]FIG. 17 is a schematic of the clocking system used for the output shift register system in FIG. 10;  
         [0030]    [0030]FIG. 18 is a schematic of the input shift register system in FIG. 10;  
         [0031]    [0031]FIG. 19 is a block diagram of a clock recovery system and start byte detect system used for the received radio data and found in the FPGA;  
         [0032]    [0032]FIG. 20 is a schematic of the TIMER section of FIG. 19;  
         [0033]    [0033]FIG. 22 is a schematic of another part of the clock recovery circuit in FIG. 19;  
         [0034]    [0034]FIG. 23 is a schematic of a part of a six register up/down counter found in FIG. 21;  
         [0035]    [0035]FIG. 24 is a schematic of another part of a six register up/down counter found in FIG. 21;  
         [0036]    [0036]FIG. 25 is a schematic of part of a digital phase lock loop found in FIG. 19;  
         [0037]    [0037]FIG. 26 is a schematic of part of a digital phase lock loop found in FIG. 19;  
         [0038]    [0038]FIG. 27 is a schematic of part of a digital phase lock loop found in FIG. 19;  
         [0039]    [0039]FIG. 28 is a schematic of digital filtering and data recovery circuits found in FIG. 19;  
         [0040]    [0040]FIG. 29 is a schematic of part of a start word detect circuit found in FIG. 19;  
         [0041]    [0041]FIG. 30 is a schematic of part of a start word detect circuit found in FIG. 19;  
         [0042]    [0042]FIG. 31 is a schematic of part of a start word detect circuit found in FIG. 19;  
         [0043]    [0043]FIG. 32 is a schematic of a latch system found in FIG. 31  
         [0044]    [0044]FIG. 33 is a schematic of part of a start word detect circuit found in FIG. 19;  
         [0045]    [0045]FIG. 34 is a block diagram and schematic of a bus driver and tri-state interface to a microcontroller port or bus;  
         [0046]    [0046]FIG. 35 is a schematic of a block found in FIG. 34;  
         [0047]    [0047]FIG. 36 is a block diagram of a multiple handset cordless telephone with a wireless conferencing system and handset that can work independently of a base station;  
         [0048]    [0048]FIG. 37 is a block diagram of the base station electronics used for the basic cordless telephone system of FIG. 36; and  
         [0049]    [0049]FIG. 38 is a block diagram of the electronics used in a two telephone line interface for FIG. 37. 
     
    
     DETAILED DESCRIPTION  
       [0050]    A block diagram of the preferred embodiment is shown in FIG. 1. In the preferred embodiment, all communication transceivers  301 ,  302 ,  303 , and  304  are frequency hopping spread spectrum type radio receivers. In the frequency hopping transmission timing, each channel hop takes less than  200  microseconds. When a transceiver turns on, it first goes into a search-for-master mode to see if another transceiver is acting as a master transceiver looking for transceivers to add in as slaves. The transceiver stays in the search-for-master mode for a specified period of time. If it sees no other transceivers acting as a master transceiver, it becomes a master transceiver. As a master transceiver, the transceiver sends an information packet telling other transceivers it is a master transceiver looking for slaves to come on line. When a master transceiver is looking for slaves to add in to slave time slots, it is in master mode.  
         [0051]    The transmission sequence consists of sending a string of repeating zeros and ones that represent the clock rate of the data for 500 microseconds, sending the start word and then sending the data packet. An information packet includes the clock recovery bits, the start word and the data packet. If clock recovery is not needed, the information packet includes all of the above except the clock recovery bits. The data packet includes a group number and command that tells the other transceivers which time slot to add into. The command byte can be used for sending acknowledge-type signals, bad RF channel information, pushed button information, etc. A string of data bytes consisting of various kinds of digital data is also included in the data packet. The various kinds of data include modem data, digitized voice, caller-identification data, video data, etc.  
         [0052]    Addresses can be used instead of group numbers in other embodiments. When addresses are used instead of group numbers, all the addresses of transceivers that can communicate in a conference-like manner have to be held in a buffer.  
         [0053]    In the preferred embodiment, four equal length time slots are used. In other embodiments, unequal length time slots can be used and the number of time slots can be more or less than four. If, after a certain length of time, the master transceiver does not find any slaves to add into one of the time slots, the master goes back into the search-for-master mode to wait for another device to come on and act as a master. In the preferred embodiment, the amount of time each individual transceiver acts as a master looking for slaves is different. Therefore, no two transceivers will remain in a master mode or a search-for-master mode at the same time. In alternative embodiments, the search-for-master mode timing can vary between transmitters or both search-for-master mode and master mode timings can vary. It should be noted that there are a certain number of reasonable variations in the timing so that no two transceivers will have the exact same timing. This problem can be solved by programming the units with this variable timing to make sure that no two are the same within the same system. In the preferred embodiment, the length of time waiting in the master mode is varied according to the address.  
         [0054]    After a master transceiver sends its data packet in slot 1, it listens for another unit to request to be added in during slots 2, 3, and 4. Included in the master data packet is a command requesting a slave unit to occupy a particular empty time slot if one is available. When a transceiver that is in search-for-master mode, receives the request to add into a particular time slot from the master, it transmits a data packet back to the other transceivers requesting the master to add it into the open time slot. This transmission occurs during the open time slot. Requests are acknowledged only from units having the same group number. The command in the data packet of the slave transceiver tells the master which slot it wants to add into and tells the master that the data bytes hold the unit address of the transceiver making the request. In other embodiments, the command byte can be used to tell the other transceivers what kind of data is contained in the data packet such as caller-identification data or modem-type data. Since each transceiver holds a unit address, the master can send an acknowledgment command back to each transceiver with the unit address of the unit it is responding to (again in the data bytes). This will eliminate two transceivers trying to add to the same time slot. Once a slave is added into a time slot, it can now receive voice or other data from the other transceivers. In other embodiments, the group number can be eliminated and the address can be used to determine if a slave is to be added into a time slot. Each transceiver is allocated a particular time slot in which to operate. If all the time slots are being used, the master transceiver sends a different command so that other slave transceivers are not requested to add into a time slot. In the preferred embodiment, other slave transceivers go into a receive-only mode where information is received from all the transceivers that occupy time slots.  
         [0055]    In other embodiments, slave units can be set up that have no capability to transmit and therefore cannot become master transceivers but can receive the information sent by the master transceiver and other slave transceivers.  
         [0056]    In other embodiments, the master transceiver can keep certain transceivers from having access to an open slot or receiving and using the information because each transceiver has its own address. By keeping a list of addresses in a buffer that is to be blocked from joining a communication link, a master transceiver can block specific transceivers from getting an open time slot. The master transceiver can also have private communications with one or more other transceivers by only allowing transceivers with specific addresses to add into open time slots or listen to the communication link.  
         [0057]    Transceiver  301  sends a data packet to transceivers  302 ,  303 , and  304  in the communication link. Transceivers  302 ,  303 , and  304  all receive the data packet in the communication link. Assuming transceiver  301  is the master, transceiver  302  is in slot 2, transceiver  303  is in slot 3, and transceiver  304  is in slot 4, then transceiver  302  would begin its transmission sequence right after receiving the last byte of the data packet of transceiver  301 . Transmitter  303  would begin its transmission sequence right after receiving the last byte of the data packet of transceiver  302 . Transceiver  304  would begin its transmission sequence right after receiving the last byte of the data packet of transceiver  303 . When a time slot has no transceiver sending information, the transceivers use timers to estimate the timing that would have been used by a transceiver to transmit its information. This allows all the transceivers to stay in synchronization even though a slot is not being used.  
         [0058]    In the preferred embodiment, two different timers are used. The first timer tells the transceiver that it should have received a start word before the timer times out. If a start word is detected, this timer is disabled. If a start word is not detected, a second timer is started when the first timer times out and the receive buffer is filled with a data sequence that creates a constant voltage out of the appropriate decoder. The second timer times out when the next time slot is ready to be received and the first timer is started again. If a good packet of data is received, the first timer is started at the end of receiving a good data packet unless it is time to transmit the data buffer over the communication link to the other transceivers. At the end of transmitting a data buffer, the first timer is started again.  
         [0059]    In other embodiments, instead of two timers, one timer could be used for each time slot duration and/or a timer for the next time to start transmission sequence could be used to keep all the units in synchronization.  
         [0060]    Also in alternative embodiments, the timers may be of different duration depending on the time slot being received or the type of device sending the information.  
         [0061]    All data packets are received from every transceiver so that all audio information from the other three transceivers can be summed and put to the speaker at each unit.  
         [0062]    A transceiver going out of range of another transceiver causes errors in the group number, the command byte or the start word. If the start word has too many errors, no data will come through and the data buffer is filled with a data sequence that creates a constant voltage out of the appropriate decoder. If either the group number or the command byte is good, the data bytes are accepted. Both the group number and the command byte must be correct when a transceiver is trying to add into a slot. A master transceiver will drop a slave transceiver from a time slot if it receives too many bad packets in a row. The master transceiver then sends a command to request a transceiver to add into that time slot that was dropped. This tells the transceiver that was dropped that it needs to request to be added in again. A counter is used in microprocessor  307  to determine if too many bad packets have been received. The counter is reset every time a good packet of data is received.  
         [0063]    In other embodiments, other error detection techniques can be used. Error detection techniques can be used for the whole data packet instead of just the address and/or the command byte to determine if a bad packet was received. Error correction codes can be used to correct bit errors in data packets if not too many bit errors were received. Using error correction codes can help to reduce bad packets of data and keep transceivers in synchronization.  
         [0064]    [0064]FIG. 2 is a block diagram of the electronics in the communication transceiver preferred embodiment. RF section  305  is a frequency hopping spread spectrum transceiver. The RF section  305  can be termed as a transceiver by itself but for the purpose of this description, the whole of FIG. 2 will be called transceiver or communication transceiver. The output of RF section  305  is the quadrature detected analog signal showing frequency demodulated data. The preferred embodiment uses frequency shift keyed (FSK) data but any form of data modulation could be used with the appropriate demodulation. The quadrature detected signal goes into the analog section  306  where it is digitized and sent to the FPGA  308 . The FPGA  308  takes the data in, recovers the clock from the first  500  microseconds of transmission, confirms that the start word is received correctly, tells the microprocessor  307  that data is coming, converts the incoming data stream to a parallel format, and sends one byte of received data at a time to the microprocessor  307 . The microprocessor  307  receives the radio data and stores it in appropriate buffers for each time slot. The microprocessor  307  can also be called a microcontroller. The microprocessor  307  also controls the RF section  305 , programs the audio codecs  309 , FPGA  308 , etc. The microprocessor  307  operates timing functions. The microprocessor  307  keeps separate buffers for each transceiver from which it receives data. The audio data received from other transceivers is sent in a parallel form to separate buffers for each audio path in the FPGA  308 . The FPGA  308  converts each of the audio data buffers to a serial form, synchronizes the data and sends it to different audio codecs  309  for each audio channel. The audio codecs  309  convert the serial data stream to an analog form which is input into a summing amplifier  52  (show in FIG. 7). This amplifier  52  sends the combined signal to speaker  311 . Microphone  310  amplifies voice information and sends it into audio codec  309  which digitizes the audio into a serial data stream that is sent in to FPGA  308 . FPGA  308  converts the serial data into a parallel format and sends it to microprocessor  307 . Microprocessor  307  stores this information in a transmission buffer. At the appropriate time during the transmission time of a transceiver, microprocessor  307  sends the transmission buffer a byte at a time to FPGA  308 . FPGAS  308  converts received parallel data into a serial format and sends it to the RF section  305 .  
         [0065]    [0065]FIG. 3 shows a detailed schematic of the analog section  306  in FIG. 2. It shows the power supply  319  and  320  for the transceiver. Connection  312  goes to the RF section  305 . The circuit containing resistor dividers  313  and  314  and comparator  315  is the power-on reset for the transceivers. DC reference  316  creates a comparison point for comparator  318  which is the demodulator for the received quadrature detected data. Filter  317  AC couples the quadrature detected data and filters it before being compared to reference  316 . The resulting RF data  167  goes into the FPGA  308 . The received signal strength indicator (RSS) is buffered by transistor  323  and then sent to an AND input on microprocessor  307 . On/off switch  322  controls the power for the system. The microprocessor  307  can control the power to the RF section  305  through switch  321 . This allows the microprocessor  307  to do other functions such as receiving parameters or programming other devices without losing current to the RF section  305 . Resistor  324  creates a voltage level that is sent to an A/D input of microprocessor  307  for use as a low battery detector.  
         [0066]    [0066]FIG. 4 shows the connections to the FPGA  308 . Data is sent through resistors  326  to the RF section  305  where the data is transmitted. Resistors  326  center the voltage when the output from FPGA  308  is in tri-state. Crystal  327  is the crystal for setting the frequency at which the microprocessor  307 , the FPGA  308  and the RF section  305  operate.  
         [0067]    [0067]FIG. 5 shows the connections to the microprocessor  307 . Switch  331  causes the transceiver to change between two different group numbers. This allows a unit to have more than one group number. A transceiver with more than one group number can be part of different conferencing groups by changing switch  331  which changes the transceiver&#39;s group number to a different group number that was stored in memory. Each time the switch  331  changes state, the transceiver goes into a search-for-master mode in order to be added to the appropriate conferencing group with the new group number. In alternative embodiments, a keypad or other means can be used to go between two or more group numbers. Also in alternative embodiments, the group number can be changed to any group number through a keypad interface. Alternate embodiments may also use addresses or parts of addresses instead of group numbers. Switch  330  is used as a push-to-talk function. Even though only four transceivers can transmit at one time in the preferred embodiment, unlimited transceivers can listen to the four transceivers that are transmitting. The preferred embodiment includes the capability of keeping slot 4 open for push-to-talk transceivers which use switch  330  when they want to transmit. Other embodiments can use different time slots with push-to-talk transceivers. Connector  329  is used to program parameters into microprocessor  307  or EEPROM  328 . Some microprocessors may have internal EEPROM to eliminate the need for external EEPROM  328 .  
         [0068]    [0068]FIG. 6 shows that the preferred embodiment uses continuously variable slope delta (CVSD) modulators/demodulators (codecs)  333 ,  334 ,  335 , and  342 . Other types of codecs or audio compression type chips or techniques can be used. Some of the more advanced compression techniques will help to increase the number of time slots or simultaneous communication paths available to the system without increasing the bandwidth requirements of the RF channels. Capacitors  339 ,  340 ,  341  (FIG. 6) and  360  (FIG. 7) are used to block any DC signal from reaching the summing amplifier  52  (FIG. 7). These capacitors can be eliminated if the DC reference used by the codecs  333 ,  334 ,  335 , and  342  is the same as the reference used by the summing amplifier  52 . Filters  336 ,  337 ,  338 , and  349  filter the analog outputs from the codecs  333 ,  334 ,  335 , and  342  to get rid of any digital and high frequency noise before going into summing junction  348 . Codecs  333 ,  334 , and  335  convert digital data to analog signals. Codec  342  of FIG. 7 converts digital data to analog signals and also converts analog signals from amplifier  345  to digital data. Amplifier  345  is a differential amplifier that receives voice information from microphone  310 . A differential amplifier was used in the preferred embodiment because the microphone  310  could be several feet from amplifier  345 . A single ended amplifier can be used in most embodiments. Even though the preferred embodiment shows the use of voice information coming into amplifier  345 , any form of analog data can be used in other embodiments. Amplifier  346  sends a stable DC reference to amplifier  345  and to power microphone  310 . Transistor  347  acts as a switch which is controlled by microprocessor  307 . This enables the microprocessor  307  to turn off the reference so that amplifier  345  is essentially turned off. This keeps unwanted noise from this transceiver from interfering with communication between other transceivers in a high noise environment. The microprocessor  307  can also send tonal information to the user by putting a digital wave-form out on SOPT  50 . This signal is filtered through filter  51  and sent to the speaker  311 . This allows microprocessor  307  to send information to the user such as low battery warnings, busy signals, ring signals, etc. In alternative embodiments, any analog-type signal can be summed with other signals into summing junction  348  allowing the user to receive information such as stored messages from other users, frequency synthesized words, etc.  
         [0069]    [0069]FIGS. 8, 9,  11 ,  15 ,  19  and  34  are upper level schematics that show all the functions in FPGA  308  and show information flow inside the FPGA  308 . FIG. 8 is a schematic showing how parameters are loaded into the FPGA  308  from microprocessor  307 . Programming is enabled by pulling SDEN  54  high while sending dock  55  and data  56  signals into shift register  57 . The contents of shift register  57  are latched into register  58  when SDEN  54  is brought low again.  
         [0070]    [0070]FIG. 9 shows the upper level of how the microprocessor  307  clocks parallel audio data into FPGA  308  by using data bus  325  and clock signals  59 ,  60 ,  61 , and  62 . OUTAUDIO circuits  63 ,  64 ,  65 , and  66  then convert the parallel audio data to serial data and shift this data to the codecs  333 ,  334 ,  335 , and  342  on signals  71 ,  72 ,  73 , and  74 . When the audio buffer is ready for more data, it sends a buffer-empty signal  67 ,  68 ,  69 , and  70  to the microprocessor  307 . With these four audio paths, users can listen to four other people talking at the same time. Additional audio circuits identical to circuits  59 ,  63 ,  67 , and  71  need to be added to support more simultaneous conversations.  
         [0071]    [0071]FIG. 10 is a schematic of the circuits inside each OUTAUDIO block  63 ,  64 ,  65 , and  66 . It shows how the data is double buffered. When the circuit sends a buffer-empty signal out of flip flop  84 , the microprocessor  307  clocks a new data byte into register  86  with clock  82 . ACLKIN  82  triggers flip flop  85  to clear flip flop  84 . The data is held in register  86  until shift register  83  shifts out its last bit at which time ALOAD  87  loads the data from register  86  into shift register  83  and triggers flip flop  84  to send the buffer-empty signal. Clock signal  88  controls the data rate for shifting data out of shift register  83 .  
         [0072]    [0072]FIG. 11 shows the upper level schematic of INAUDIO  77  which shows how the microprocessor  307  clocks parallel audio data from FPGA  308  by using the signal ACLKOUT  75  to put data onto bus  253 . It also shows the upper level schematic of AUDCLK  81  which generates the audio clock signal  88 , the audio load signal  87  and other clocking signals for the system. All clock signals start from reference clock MHZ7P  80 . INAUDIO  77  receives digitized audio data from the microphone  310  via signal  76  and converts it to parallel form for sending to the microprocessor  307  where it is buffered and finally transmitted to the other users. Each time INAUDIO  77  is ready to send data to the microprocessor  307 , it sets signal  78  high.  
         [0073]    [0073]FIG. 12 is a schematic of the circuits inside INAUDIO  77 . AUDCLK  88  clocks serial data  76  into shift register  89 . When shift register  89  is full, the byte of data is loaded into register  91  by load signal  87  and flip flop  93  is triggered to send a buffer-full signal  78  to the microprocessor  307 . After reading the data, the microprocessor  307  clears flip flop  93  by setting flip flop  92  with ACLKOUT  75 .  
         [0074]    [0074]FIGS. 13 and 14 are schematics of the circuits inside AUDCLK  81  of FIG. 11. Counters made up of flip flop  96 , ripple counter  104  and flip flops  105  and  106  divide the main crystal frequency  80  to create the audio clock signal  88  and the main clock for shifting data into and out of the audio codecs  333 ,  334 ,  335 , and  342 . Flip flops  107 - 110  further divide the audio clock signal  88  to create the register load signal ALOAD  87 . This circuitry keeps all the audio data shift registers synchronized. All the buffers will shift at the same time and will empty at the same time. This approach eases the load requirements in microprocessor  307 .  
         [0075]    ALOAD  87  is further divided by flip flops  101 ,  111 , and  112  to create a time base for the speeding up and the slowing down of the AUDCLK  88  signal. With a wireless conferencing system, the complexity of the system is reduced if the time bases of the different transceivers are synchronized. Thus, all audio buffers on all communicating transceivers will empty at the same rate. Since there are inaccuracies in the crystals in each transceiver, a means to keep all the transceivers synchronized is needed. One method is to phase lock the crystal in each of the transceivers by using the recovered clock in one of the data streams as a reference in a phase lock loop. In another method, the crystal or the time base of each transceiver is synchronized to an external time base like the Global Positioning Satellite (GPS) system time base or any common time base that can be received by all the transceivers. An external time base can also be used to keep accurate positioning of the time slots. In the preferred embodiment, the crystals are not phase locked but the speed of the clock that is used to create AUDCLK  88  signal is increased or decreased to match the transmission times of the master transceiver. When the master transceiver starts sending its data packet, each of the slave transceivers will have a pointer to a memory address in the audio buffer for sending information to the speaker. This pointer should always be pointing at the same memory address when the master transceiver starts its transmission. If the pointer is ahead or behind the correct address, the microprocessor  307  will speed up or slow down the audio clock rate. This will simulate phase locking all the crystals of the transceivers.  
         [0076]    Microprocessor  307  causes the audio clock speed to change by first sending an enable signal  103  and then sending a direction bit  102  which causes the audio clock to speed up or slow down depending on whether the direction bit  102  is high or low. The signal coming out of flip flop  101  allows flip flop  98  to go high when signal  103  is also high. On the next clock signal out of flip flop  96 , flip flop  97  will go high which toggles digital switch  95 . Toggling digital switch  95  causes the clock going into flip flop  96  to invert from high to low. This will cause the frequency coming out of flip flop  96  to speed up by one half of a cycle of MHZ7  80  which in turn causes AUDCLK  88  to speed up. If direction bit  102  is high, then the output of flip flop  100  will go high which causes flip flop  96  not to toggle for one of its clock cycles. The effect of this is that the frequency coming out of flip flop  96  slows down by one half of a cycle of MHZ7  80 . Flip flop  99  is used for clearing flip flop  100  at the appropriate time.  
         [0077]    [0077]FIG. 19 is the upper level schematic of the clock recovery  157 , data clock phase lock loop  156 , data recovery  159 , start word detect  158 , and timer circuits  155  for received RF data  167 . When the microprocessor  307  is expecting to receive a new pack of data from another transceiver, it toggles NEWPACK  153  twice to go high then low in order to initialize the circuits of FIG. 19. A new data packet starts with 500 micro seconds of high-low combinations that represents the clock rate of the upcoming data. This data comes in on RFDINP  167  and goes into CLKREC  157 . FIG. 20 is a detailed schematic of TIMER  155 . The signal NPACK  153  initializes counter  161  and flip flops  162  and  164 . A short delay after the beginning of the new data packet reception starts, counter  161  clocks flip flop  164  which sets the STPLL signal  165 . STPLL  165  stops the phase lock loop operation in DCLKPLL  156 . After an additional delay, counter  161  clocks flip flop  162  which sets the TIMST signal  163 . TIMST  163  enables the start word detect circuit  158  to start looking for the start word of the data packet.  
         [0078]    [0078]FIGS. 21 and 22 are detailed schematics of CLKREC  157  (FIG. 19). The received RF data signal DATAIN  167  in FIG. 21 goes through gates  168  to an up-down counter  169 . Counter  169  is a 6 bit up-down counter that has been reduced from a standard 8 bit up-down counter. FIGS. 23 and 24 are detailed schematics of counter  169  which illustrates the 6 bit counter using flip flops  182 , 183 ,  184 ,  185 ,  186 , and  187 . Counter  169  is set up with feed back so that it will never go above a certain number or below a certain number. If these limits are ever reached, the DATAIN  167  is inverted through gates  168  which causes the up-down signal  181  to toggle for one count. This causes the counter  169  to dither back-and-forth at the upper or lower limit until DATAIN  167  changes to a different state. The outputs of counter  169  cause UCNT 1171  to clock flip flop  175  several counts below the upper limit and cause DCNT1  172  to clear flip flop  175  several counts above the lower limit. The output of flip flop  175  is the recovered clock from the RF data stream  167 . To compensate for this phase delay, flip flops  176 ,  178 , and  179  with counter  170  start a delay function after the rising edge of DCNTCLR  177 . When counter  170  counts to the right time delay, it causes TCNT  173  to go high which in turn clocks flip flop  179  to go high. Counter  170  continues to count for the time period of one half cycle of the expected received RF data rate. At this half cycle time period, SCNT  174  goes high to clear Flip flop  179 . Thus, DATACLK  180  is a square wave clock signal that is in phase and at the same frequency as the clock signal contained in the received RF data stream.  
         [0079]    The above technique is used in the preferred embodiment because it helps to recover the received RF data clock in a high noise environment. Other methods can be used to recover the received RF data clock such as first edge detection, analog phase lock loops, or Digital Signal Processing algorithms and still work in this system.  
         [0080]    Once the received RF data clock is recovered in DATACLK  180 , it Is fed into the DCLKPLL circuit  156  of FIG. 19. FIGS. 25, 26, and  27  are detailed schematics of the DCLKPLL circuit  156 . Flip flops  191 , 192 , 193 , and  200 - 204  constitute a ripple counter structure that divides the reference frequency  80  down to the RF data clock  206 . This DCLK  206  must be brought in phase with the received RF data clock DATACLK  180 . When the start word byte and other data comes in on the RF data stream, the DCLK  206  will be used to decode and clock in the received RF data. The DCLK  206  goes into a phase detector made up of flip flops  189  and  188 . The DATACLK signal  180  is used as the reference signal into the same phase detector. When DCLK  206  is lagging behind DATACLK  180 , the UP signal  198  goes high. When DCLK  206  is ahead of DATACLK  180 , the DWN signal  199  goes high. A high on UP signal  198  or DWN signal  199  allows the output of flip flop  194  to go high when GN4  94  goes low. When GN4  94  goes high again, flip flop  196  will go high which toggles digital switch  154 . Toggling digital switch  154  causes the clock going into flip flop  193  to invert from high to low. This will cause the frequency coming out of flip flop  193  to speed up by one half of a cycle of MHZ2  90  which in turn causes DCLK  206  to speed up. A high on DWN signal  199  causes output of flip flop  195  to go high so that flip flop  193  will not toggle for one of its clock cycles. The effect of this is that the frequency coming out of flip flop  193  slows down by one half of a cycle of MHZ2  90 . Flip flop  197  is used for clearing flip flop  195  at the appropriate time. This circuit will bring DCLK  206  in phase with DATACLK  180 . The phase lock loop is turned off when the timer signal STPLL  165  goes high or when a string of zeros is detected by the STRBYTE circuit  158 . DATAEN  214  is created using flip flop  190 . DATAEN  214  is used in circuit STRBYTE  158  to indicate that another RF data bit is coming.  
         [0081]    With the received data clock is recovered and phase locked to DCLK  206 , circuitry in NDAT  159  is ready to decode the data bits from RFDIN  167 . FIG. 28 is the detailed schematic of the NDAT circuit  159 . In FIG. 28, RFDIN  167  and DCLK  206  are input to gate  207  to decode the data from Manchester encoded data. In the preferred embodiment, Manchester encoding is used to send data over the RF channel. Other types of encoding (or no encoding) can be used to eliminate the need for gate  207 . The output of gate  207  is signal  343  which is the decoded data. Counter  208  does a form of digital filtering on decoded data signal  343 . The counter  208  is cleared when DCLK  206  clocks the output of flip flop  82  high. When decoded data signal  343  is high, counter  208  is enabled to count. If decoded data signal  343  stays high longer than it is low during a DCLK  206  cycle, a high is clocked through flip flops  79  and  212  onto NDAT  213 . This means that NDAT  213  is the filtered and decoded data. During the first 500 microseconds of a transmission, all zeros are received by this circuit. While searching for this string of zeros, the signal SRCH  209  stays high. While SRCH  209  is high, selector  210  changes the filter counter which determines whether a one or a zero bit is received. This special filtered method helps improve the performance of the system in high noise environments for detecting the 500 microseconds of lead-in zeros to a packet. When Manchester encoded, these same zeros are the received data clocks used by CLKREC  157 .  
         [0082]    NDAT  213  goes to the start word detect circuit  158  on FIG. 19. FIGS. 29, 30,  31 , and  33  are the detailed schematics of the STRBYTE circuit  158 . NDAT  213  (also called DATAIN) is clocked into shift register  215  when DATAEN  214  goes high. X16CLK  216  is a clock signal that is 16 times faster than DCLK  206 . X16CLK  216  is the clock signal for shift register  215 . Therefore, shift register  215  will receive 16 clocks between each new bit of data. The shift register  215  is a 15 bit recirculating register that always shifts out of SD[14]  218  the last 15 bits of NDAT  213  received. Normally 16 shifts would take place but counter  220  (FIG. 30) stops the shifts when ST[4}  306  goes high. Counter  223  (FIG. 31) increments by one, whenever STOPC  222  is low and STRCLK  219  is high. During the first 500 microseconds of transmission, STRCLK  219  is selected to be the same as SD[14]  218  by SRCH  209 . Therefore, counter  223  counts how many ones are in the last 15 bits of NDAT  213 . Counter  223  is cleared to start the count again each time a new NDAT  213  bit is loaded by DATAEN  214 . Circuits  226 ,  227 ,  228 ,  229 , and  225  set ENRCVCK  230  high if at least 12 of the last 15 bits received in NDAT  213  were zeros. FIG. 32 is a detailed schematic of TREGC4  225 . At the end of checking the last 15 bits received in NDAT  213 , the signal STOPC  222 , which is created from flip flop  221 , clocks the data from circuit  226 ,  227 ,  228 , and  229  into flip flops  231 ,  232 ,  233 , and  234 . These in turn, clock flip flops  235 ,  236 ,  237 , and  238  to have high outputs if any of the flip flops  231 - 234  were triggered high. If any of the flip flops  235 - 238  are high, ENRCVCK  230  will go high. The first time that ENRCVCK  230  goes high during the first 500 microseconds of a transmission, indicates that the DCLK  206  is phase locked to the DATACLK  180 . In FIG. 33, ENRCVCK  230  then clocks flip flop  243  which causes SRPLLS  239  to go high. A high on SRPLLS  239  will stop the phase comparator in FIG. 25 and causes SRCH  209  to be cleared through flip flops  244  and  242 . SRCH  209  was initially set by microprocessor  307  programming the signal SEARCH  241  high and toggling NPACK  153  to go high then low twice.  
         [0083]    After SRPLLS  239  goes high, ENRCVCK  230  will be cleared and the search for the start word will begin. The start word is created by shift register  216  using feed back Q[3] 217  (FIG. 29). This forms a 15 bit long pseudo-random number generator. A longer generator could have been used or a simple shift register that is loaded with the start bits could have been used instead of shift register  216 . The start word is shifted out of shift register  216  through Q[3]  217  and compared with SD[14]  218 . The result of this comparison comes out on STRCLR  219 . Whenever Q[3]  217  and SD[14]  218  are not equal, counter  223  will be increment. Circuits  226 ,  227 ,  228 ,  229 , and  225  sets ENRCVCK  230  high if at least 12 of the last 15 bits received in NDAT  213  are equal to the start word. When ENRCVCK  230  goes high because the start word matches the received NDAT  213  bits, ENRCVD  247 , RBYCNT  248  and FBCLK  150  go high. These signals are used in FIG. 18 for getting the first byte of RF data.  
         [0084]    [0084]FIG. 15 shows the upper level schematic for a microprocessor interface to the RF data. FIG. 18 is the detailed schematic of the INRF  113  which brings the received RF data in on NDAT  213  and converts the data into a parallel format. The data is then read in and buffered by microprocessor  307 . After being buffered, the data is sent to the appropriate codec in the preferred embodiment. In other embodiments, the data can be sent to a modem or other device.  
         [0085]    In FIG. 18, RCVDCLK  206  or FBCLK  150  clocks serial data NDAT  213  into shift register  139 . When shift register  139  is full, the byte of data is loaded into register  140  by the buffer-full signal  116 . The buffer-full signal  116  is created by FLOAD  149  allowing flip flop  143  to be clocked. A high on the output of flip flop  143  is a buffer-full signal  116  for the microprocessor  307 . After reading the data, the microprocessor  307  clears flip flop  143  by setting flip flop  142  with RFOE  115 . Data is only allowed to be clocked into register  139  when ENRCVD  151  is high. FBCLK  150  clocks the first bit of data into shift register  139  after detecting the start byte in FIG. 33. The FLOAD signal  149  is created by the counter made up of flip flops  144 ,  145 ,  146 , and  147  which counts the number of bits that have been shifted into shift register  139 . RBYCNT  148  resets and synchronizes flip flops  144 ,  145 ,  146 , and  147  to the first received data bit on NDAT  213 .  
         [0086]    [0086]FIG. 15 shows the upper level of how the microprocessor  307  clocks parallel RF data into FPGA  308  by using data bus  325  and clock signal RCLKIN  117 . OUTRF  114  then converts the parallel RF data to serial data and shifts this data to the RF section on signal RFDOP  120 . When the RF buffer is ready for more data, it sends a buffer-empty signal RFBUFEP  121  to the microprocessor  307 . DINV  119  is controlled by the microprocessor  307 . It inverts the data going to the RF section depending on which channel the frequency hopping transmitter is transmitting.  
         [0087]    [0087]FIG. 16 and FIG. 17 are schematics of the circuits inside OUTRF  114  and show how the data is double buffered. When the circuit sends a buffer-empty signal  121  out of flip flop  128 , the microprocessor  307  clocks a new data byte into register  122  with clock RCLKIN  117 . RCLKIN  117  triggers flip flop  127  to clear flip flop  128 . The data is held in register  122  until shift register  123  shifts out its last bit at which time FLOAD  129  loads the data from register  122  into shift register  123  and triggers flip flop  128  to send the buffer-empty signal BUFE  121 . Clock signal DCLK  206  controls the data rate for shifting data out of shift register  123 . After the RF data is shifted out of shift register  123 , it passes through encoder  126  where the data is Manchester encoded and sent out on signal Z7  124 .  
         [0088]    [0088]FIG. 17 includes a counter with flip flops  132 ,  133 ,  134 , and  135  which counts the number of bits shifted out of shift register  123 . When all the bits are shifted out of shift register  123 , FLOAD  129  goes high and loads shift register  123  with another byte of data. When microprocessor  307  wants to send the first byte of a data packet, it sets RFDEN  118  high. A high on RFDEN  118  pulls RFDOP  120  out of tri-state through flip flop  136 . RFDEN  118  also resets and synchronizes the counter made up of flip flops  132 ,  133 ,  134 , and  135  to the first byte of data through flip flops  136 ,  137 , and  138  and the signal FDLD  125 .  
         [0089]    [0089]FIG. 34 is a schematic of the data bus interface to microprocessor  307 . Tri-state driver  255  sends data to microprocessor  307  from BUSDR  252 . There is a tri-state driver  255  for each data bit. Buffer  257  sends data from microprocessor  307  to data bus  325 . FIG. 35 is a detailed schematic of BUSDR  252 . It shows how RFOE  115  and ACLKOUT  94  select between the audio data bus  253  and the RF data bus  254  through 8 selectors like selector  256 .  
         [0090]    In the preferred embodiment, a frequency hopping spread spectrum system is used to create the communication link for groups of transceivers to communicate to one another. Each transceiver uses the same hopping pattern to communicate to other transceivers. Even transceivers with different group numbers use the same hopping pattern. The timing that a particular group of transceivers is communicating on a particular radio channel is different or delayed compared to another group of transceivers. This allows multiple groups of transceivers to operate at the same time. In an alternate embodiment, different groups of transceivers could use different hopping patterns or hopping patterns which use different channels.  
         [0091]    In other embodiments, a direct sequence spread spectrum system could be used in which different groups of transceivers use different spreading codes, different radio channels, and/or time-offset spreading codes to create the different communication links. Starting the spreading sequence at different times to differentiate between different groups of transceivers all having the same spreading code is known as a time-offset spreading code technique.  
         [0092]    In another embodiment, multiple master transceivers can be part of the same communication link. One of the master transceivers would be used to time synchronize all the clocks to maintain timing in filling buffers. This timing information can be passed from master transceivers to master transceivers in systems where all the transceivers cannot communicate with one another. The master transceivers can still communicate with one another but each master transceiver can also independently assign slave transceivers to other available slots. All master transceivers need to know which time slots are available to be assigned to other transceivers. This can be done by each master transceiver receiving all the information on the communication link or by special packets received from other master transceivers that hold the time slot assignments associated with each of the other master transceivers. The master transceivers can be limited to specific slots or assigned to any slot by the original master transceiver in the communication link. Each master transceiver can communicate to all other master and slave transceivers. In some applications, the master transceivers can set up mini-communication links to specific time slots in a multiple master transceiver system so that each master transceiver can have private communications with specific slave transceivers. This embodiment can be set up because each transceiver has a unique address or each mini-communications link has its own group number. In these embodiments all transceivers do not have to buffer information from all other transceivers, but only those associated with their mini-communication link.  
         [0093]    In embodiments where higher data rates are needed for specific transceivers, multiple time slots can be assigned to individual transceivers. If multiple time slots that are assigned to a transceiver are consecutive, only the first time slot in the consecutive time slot string has to have the clock recover string, the start word, an address or group number, and a command.  
         [0094]    In other embodiments, all or part of the analog section  306 , the FPGA  308 , the microprocessor  307 , the audio codecs  309 , and the interface to the speaker and microphones can be replaced by a Digital Signal Processor or combination Digital Signal Processor/microprocessor. A Digital Signal Processor could allow for better filtering, better sensitivity in the wireless received data and more functions that are common in telephone applications.  
         [0095]    Another application would be to interface one of the transceivers to a telephone line to make a cordless telephone system or a wireless PBX system. In this application, a Digital Signal Processor could also be used for echo canceling and telephone line balancing.  
         [0096]    From the above description, it is apparent that other types of radios can be used instead of a frequency hopping spread spectrum radio to create a full duplex conferencing radio system. A single channel radio with enough bandwidth or a direct sequence/code division multiple access (CDMA) spread spectrum radio could also be used.  
         [0097]    [0097]FIG. 36 is a block diagram of an alternative embodiment showing each communication transceiver as a cordless telephone hand set or as a base station to a cordless telephone. Cordless telephone handsets  258 ,  259 , and  260  can communicate to each other in a conference-like manner independent of the base  270  or with the base  270  making the connection to the telephone system  271 . In other embodiments, the base  270  and telephone lines,  271  can be replaced with an interface to any other communication system such as business band radio, cellular radios, PBXs, etc.  
         [0098]    [0098]FIG. 37 is a block diagram showing how a communication transceiver is changed to become a cordless telephone base station transceiver  270 . Telephone interface  285  replaces the microphone  310  and speaker  311  of FIG. 2 to create a telephone base station  270 .  
         [0099]    [0099]FIG. 38 is a more detailed block diagram of a possible telephone interface showing how to connect two telephone lines to the same system. Telephone lines  295  and  296  each go to their own 2 to 4 wire converters  293  and  294 . Microprocessor  307  controls all the on/off hook functions, ring detect functions, etc. of the telephone interfaces  293  and  294 . This configuration also shows how a modem  284  could be connected to one of the phone lines  295  for sending the receiving data that can also be sent to the handsets  258 ,  259 , and  260 . Whether the modem is used or the codecs are used is controlled by microprocessor  307  through relays  299  and  300 . A modem could also be connected to the other phone line  296 . Transmit codec  286  and  287  can receive information from telephone line interface  293  or  294  depending on the position of relay  297 . This allows for configuration of one transmit codec talking to all or some of the handsets  258 ,  259 , and  260  or each transmit codec  286  and  287  occupying one of the time slots but communicating using different group numbers to individual handset or groups or handsets. Microprocessor  307  controls relay  298  which routes receiving codecs  288 ,  289 , and  290  to the appropriate summing amplifiers  291  and  292 . By adding more relays, codecs, telephone line interfaces, telephone lines, and time slots, a conferencing-capable wireless PBX can be implemented.  
         [0100]    Program for the  65524  OKI Microcontroller  307  of FIG. 3 in Intel Hex Format:  
         [0101]    :100020000001030106010C010F0112011501180165  
         [0102]    :100030001B012101240127012A012D013001330177  
         [0103]    :0300400080360106  
         [0104]    :03006000803601E6  
         [0105]    :100100008000018003012C2D95442E83800C0180FA  
         [0106]    :100110000F018012018015018018012C2D95442CAF  
         [0107]    :1001200083802101802401802701802A01802D0104  
         [0108]    :1001300080300180D7052AEF3A2090147F95150072  
         [0109]    :10014000E29515F0E3951500E4951500E595150188  
         [0110]    :10015000E89515DBE9951500EC9515ACED9515A026  
         [0111]    :10016000EE951504B89515FFB9951500BA95150FBC  
         [0112]    :10017000BB951502BC951500B795150CAB95150DE3  
         [0113]    :10018000AB951520F395150ADA951500F69515002F  
         [0114]    :10019000F78844145530C0E8C2FB155EA01513A1C2  
         [0115]    :1001A00015AAA21555A32A7F2ABF8E008844896408  
         [0116]    :1001B0009788849789A695150F2895150727951573  
         [0117]    :1001C0000A3D95150A3695150A3795150A3802AF76  
         [0118]    :1001D00014954530951530059515001F9495E0EC64  
         [0119]    :1001E0000380B602818E089515FFE514559505E448  
         [0120]    :1001F00095A7E295B7E295A4E295B4E295A5E295BC  
         [0121]    :10020000B5E295A6E295B6E2143081A808813A02DB  
         [0122]    :100210003A4095AE2495AF259515003C9495E5BEE2  
         [0123]    :1002200009950B3C95AE2295AF23951501359504A4  
         [0124]    :100230002107070795053480FD082A7F2ABF9515F9  
         [0125]    :1002400000EE9515ACED951500EC14808122049517  
         [0126]    :10025000052095920521148181220495052295920D  
         [0127]    :100260000523148281220495052495920525148383  
         [0128]    :100270008122049505029592050314848122049439  
         [0129]    :100280007955049279AA22951566209515442195F1  
         [0130]    :1002900015AA223A408EAA951555238F55951555C6  
         [0131]    :1002A0002495155AA252ABF8A009515A0EE9515ACB0  
         [0132]    :1002B000ED951500EC82813A02955620299556213C  
         [0133]    :1002C000289556222B9556232A9556242D9556254A  
         [0134]    :1002D0002C9556022E9556032F951500EE95152058  
         [0135]    :1002E000EC95152CED8028039495E0EC389495E777  
         [0136]    :1002F000ECF681020595052881FB0495052981FB13  
         [0137]    :100300000495052A81FB0495052B81FB0495052C9A  
         [0138]    :1003100081FB0495052D81FB0495052E81FB049539  
         [0139]    :10032000052F8067038036019495E7ECFB95042840  
         [0140]    :10033000812D0595042981260595042A8126059598  
         [0141]    :10034000042B81260595042C81260595042D8126F4  
         [0142]    :100350000595042E81260595042F81260595E7EC49  
         [0143]    :10036000FC95B5EC80E80295B7EC951500EE951577  
         [0144]    :10037000ACED951500EC2A7F2ABF95A3EC95A5EC72  
         [0145]    :1003800095A7EC95B7EC14309515083B073F0695FB  
         [0146]    :10039000A5EC80980395B5PC95A7EC95B7EC951B6B  
         [0147]    :1003A0003B3DE995B3EC95562930955628311440DC  
         [0148]    :1003B00081860495562B3095562A31144181860446  
         [0149]    :1003C00095562D3095562C31144281860495562E23  
         [0150]    :1003D0003095562F31144381860495155530951567  
         [0151]    :1003E000AA31144481860495A3EC95A5EC95A7EC5D  
         [0152]    :1003F00095B7EC14009515083B073F0695A5EC80D2  
         [0153]    :10040000050495B5EC95A7EC95B7EC951B3B3DE93C  
         [0154]    :1004100095B3EC9515A0EE9515ACED951500EC8017  
         [0155]    :10042000B60295A3EC95A5EC95A7EC95B7EC9515C0  
         [0156]    :10043000083B073F0695A5EC803E0495B5EC95A7D3  
         [0157]    :10044000EC95B7EC951B3B3DE99515083B95A7EC62  
         [0158]    :100450009495E6EC053A01805C042AFE920795B774  
         [0159]    :10046000EC951B3B3DE79515083B95A7EC9495E66D  
         [0160]    :10047000EC053A018079042AFE0795B7EC951 B3B011  
         [0161]    :100480003DE895B3EC8295A3EC95A5EC95A7EC958A  
         [0162]    :10049000B7EC9515083B073F0695A5EC80A204959F  
         [0163]    :1004A000B5EC95A7EC95B7EC951B3B3DE995043170  
         [0164]    :1004B0009515083B073F0695A5EC80C00495B5EC63  
         [0165]    :1004C00095A7EC95B7EC951B3B3DE9950430951548  
         [0166]    :1004D000083B073F0695A5EC80DE0495B5EC95A793  
         [0167]    :1004E000EC95B7EC951B3B3DE99583EC95B7EC95D6  
         [0168]    :1004F000A3EC9495E6ECFB95B3EC829515083B8054  
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