Abstract:
A method of electrically isolating a MEMS device is provided. In one example, a piezo-resistive pressure sensor having an exposed silicon region undergoes a Local Oxidation of Silicon (LOCOS) process. An electrically insulating structure is created in the LOCOS process. The insulating structure has a rounded, or curved, interface with the piezo-resistive pressure sensor. The curved interface mitigates stresses associated with exposure to high temperatures and pressures. Additionally, the electrically insulating line may be patterned so that it has curved angles, further mitigating stress.

Description:
FIELD  
       [0001]     The present invention relates generally to the fabrication of micro-electro-mechanical structures, and more particularly, relates to a favorable method of creating electrical isolation for a micro-electro-mechanical structure that minimizes stress concentrations.  
       BACKGROUND  
       [0002]     Silicon-On-Insulator (SOI) based technology allows a micro-electronic or Micro-Electro-Mechanical System (MEMS) device to be fabricated in a silicon layer that is located above an insulating layer (e.g. a buried oxide layer). The insulating layer is located over a silicon substrate. Electronic devices, such as transistors and MEMS-type devices are fabricated in the layer of silicon located on top of the insulating layer. This technique may provide higher speeds and use less power by reducing capacitance, reducing or eliminating the reverse leakage of the p-n junctions and thus making device operation in SOI superior to devices fabricated in conventional Complementary Metal-Oxide Semiconductor (CMOS) bulk silicon based processing.  
         [0003]     One MEMS type device that may be implemented in SOI is a pressure sensor. Pressure sensors typically include a piezo-resistor coupled with a diaphragm. The piezo-resistor is embedded in the diaphragm, and responds to a change in stress of the diaphragm with a change in resistance as a consequence of the piezo-resistive effect. When the pressure applied to the diaphragm changes, the amount of deflection of the diaphragm changes accordingly, which results in a change in the stress level in the silicon diaphragm. This in turn causes the piezo-resistor element to increase or decrease in resistance. Thus, the increase or decrease in resistance may be used to gauge the amount of pressure being applied to the diaphragm.  
         [0004]     Pressure sensors are used in a wide variety of environments. Some environments include high temperatures and/or high pressures. Because the pressure sensor is fabricated from semiconductor materials that have different thermal coefficients, extreme temperatures may cause the various layers of the pressure sensors to expand at different rates. In particular, the silicon dioxide (SiO 2 ) electrical isolation layer expands and contracts at a different rate than the silicon layer that comprises the piezo-resistor.  
         [0005]     As a pressure sensor is cycled between low and high temperatures, the electrical isolation layer may begin to crack. This is especially true if stress concentration areas are present. Cracking may also be caused by extremely high pressures or the combined effects of high temperature and pressure. The present application describes a way to minimize stress concentration areas in piezo-resistive, SOI pressure sensors and other MEMS devices.  
       SUMMARY  
       [0006]     The present application describes a method of creating electrical isolation for a MEMS device which eliminates stress cracking due to the affects of higher temperatures and/or pressures. The method includes forming a mask over the MEMS device and growing a silicon dioxide (SiO 2 ) electrical isolation layer, via a Local Oxidation of Silicon (LOCOS), in between the MEMS device and other MEMS devices. The LOCOS process creates a curved, or rounded, interface between the SiO 2  layer and the MEMS device. The rounded interface relaxes stresses associated with high temperatures or pressures.  
         [0007]     In a provided example, one type of MEMS device, a piezo-resistive pressure sensor, is masked. The unmasked regions surrounding the sensor are then oxidized, via LOCOS, to produce an electrical isolation layer. The rounded interface of the electrical isolation layer minimizes stresses associated with high temperature and high pressure environments.  
         [0008]     In a second provided example, the electrical isolation layer is patterned so that 90 degree angles are rounded. The rounded angles further mitigate stresses associated with high temperatures  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]     Presently preferred embodiments are described below in conjunction with the appended drawing figures, wherein like reference numerals refer to like elements in the various figures, and wherein:  
         [0010]      FIG. 1  is a cross sectional view of an SOI substrate;  
         [0011]      FIG. 2  is a cross sectional view of the formation of a mask layer on the substrate of  FIG. 1 ;  
         [0012]      FIG. 3  is a cross sectional view of the growth of a silicon dioxide layer during a LOCOS process;  
         [0013]      FIG. 4  is a cross sectional view of the removal of the mask layer and subsequent doping of the silicon to form the leadout and piezo-resistors;  
         [0014]      FIG. 5  is a cross-sectional view of the substrate of  FIG. 1  including a cavity;  
         [0015]      FIG. 6A  is a top view of an electrically isolating line; and  
         [0016]      FIG. 6B  is a top view of another electrically isolating line.  
     
    
     DETAILED DESCRIPTION  
       [0017]     A method of electrically isolating a MEMS device is presented. A variety of MEMS devices, such as comb drives, micro-actuators, accelerometers, etc., may be fabricated using the disclosed method. One type of MEMS device, a piezo-resistive based pressure sensor structure, may also be electrically isolated using this method.  
         [0018]     Turning now to  FIG. 1 , one such piezo-resistive sensor  100  is illustrated. The piezo-resistive sensor  100  includes an epitaxial layer  102 , which may be n-type or p-type silicon, a dielectric layer  104 , which may be silicon-dioxide (SiO 2 ), and a substrate layer  106 , which may be n-type, p-type, or bulk silicon.  
         [0019]     Although the substrate layer  106  is shown as a single layer, additional layers may be included. An “etch-stop” layer, for example, may be located in between the second layer  104  and the bulk substrate layer  106 . In addition, a cavity may also be included in the substrate layer  106 . The cavity may serve as a diaphragm for a pressure sensor. Alternatively, the cavity may be fabricated at a subsequent step. The inclusion of a cavity will be further described with reference to  FIG. 5 .  
         [0020]      FIG. 2  shows a mask  108  formed on top of the epitaxial layer  102 . The mask  108  may be silicon nitride (Si 3 N 4 ), for example. Forming the mask  108  may include growing a thin thermal oxide followed by the deposition of a mask layer (such as a Si 3 N 4 ) and patterning the mask layer so as to define the mask  108 . The mask  108  made be patterned by a conventional photolithography and etching process. The mask  108  includes an “island” which is located on top of the piezo-resistor structure. The island inhibits oxidation of the surface area above the piezo-resistor structure. In the un-covered areas  107  of the epitaxial layer  102  that are in close proximity to the mask  108 , the rate of oxidation may be reduced in relation to the oxidation rate of un-covered areas that are not in close proximity to the mask  108 .  
         [0021]     In  FIG. 3 , the SOI substrate  100  has undergone a Local Oxidation of Silicon (LOCOS) process. LOCOS is an isolation scheme commonly used in MOS/CMOS silicon technology. LOCOS is used to thermally grow thick pads of silicon dioxide which are used to separate adjacent devices (e.g. such as CMOS Field Effect Transistors or FETs). As described above, the un-covered areas of the mask  108  (such as first exposed portion  107  in  FIG. 2 ) are locally oxidized, hence, “local” oxidation. During the oxidation, silicon reacts with oxygen, the silicon is consumed, and a SiO 2  layer is produced. After the LOCOS step, the mask  108  may be removed by a conventional etching process, such as dry or wet chemical etch.  
         [0022]     During the LOCOS step, silicon reacts with oxygen at a high temperature. Thus, as shown in  FIG. 3 , a layer of silicon dioxide  110  is grown on the first exposed portions  107  of the epitaxial layer  102 . Because the growth rate of the silicon dioxide is reduced in the un-covered areas  107  in close proximity to the mask  108 , the epitaxial layer  102  is not oxidized as quickly in the areas of close proximity to the mask  108 . Therefore, a reduced silicon dioxide thickness is produced in those areas. As a result, the piezo-resistor, or epitaxial layer  102 , will have a curved, or graded, profile, commonly referred to as a “bird&#39;s beak.” 
         [0023]     The mask layer is then removed as shown in  FIG. 4 . The radius of curvature of the rounded profile  130  is dependent upon the conditions of the LOCOS process (i.e., time, temperature, film thicknesses, etc.) In contrast to having an abrupt transition between the silicon dioxide layer  110  and the piezo-resistor structure, the rounded profile  130  offers a more gradual transition. This gradual transition reduces cracking when the piezo-resistor structure is exposed to high temperatures and/or pressures.  
         [0024]     The epitaxial layer  102  in the example of  FIG. 4  includes leadout resistances  103 A and  103 B, and a piezo-resistor  105 . The readout resistances  103 A and  103 B may be used to provide an ohmic contact to the piezo-resistor  105 . Conventional or novel CMOS fabrication methods may be used to create the piezo-resistor  105  and leadout resistances  103 A and  103 B. Such methods include ion implantation, photolithography and development, and/or chemical wet and dry etching. The doping density of the leadout resistances  103 A and  103 B may be established at various points of the piezo-resistor structure. For example, the piezo-resistor  105  may have an intrinsic doping density or it may be implanted and/or annealed at a later fabrication step. The leadout resistances  103 A and  103 B may also be tailored to provide a desired contact to the piezo-resistor  105 .  
         [0025]     Prior to or subsequent to forming an electrical isolation, a cavity  120  may be formed in the bulk substrate layer  106 . The cavity  120 , illustrated in  FIG. 5 , may serve to form a diaphragm which allows the piezo-resistor  105  to vary with applied pressure. Because the epitaxial layer is crystalline in nature, a larger pressure applied to the diaphragm will deflect the diaphragm and change the resistance of the piezo-resistor  105 . The cavity  120  may be designed to form diaphragms of higher aspect ratios so that the piezo-resistor is more sensitive to changes in applied pressure.  
         [0026]     Another method which may be used to reduce cracking associated with the silicon dioxide layer  110 , is to have an electrical isolation scheme where the silicon dioxide based isolation lines are also laid out with a curved or rounded profile. Generally, electrical isolation lines are laid out perpendicular to each other. In  FIG. 6A , a top view of electrical isolation line  140  is used to isolate MEMS device  142  from MEMS device  144 . The isolation line  140  has sharp 90 degree angles  146 . These sharp angles  146  create localized stress points that are vulnerable to cracking at high temperatures. In  FIG. 6B , the vulnerability of the stress points is mitigated by using electrical isolation line  148 , which has curved angles  150 . The stress points may be eliminated by distributing the stress associated with line  148  across the curved angles  150 . Mask layer  108  may be pattered so as to create the curved angles  150  (see  FIG. 2 ). Additionally, the curved angles  150  may be produced at a later subsequent patterning step.  
         [0027]     While certain features and embodiments of the present invention have been described in detail herein, it is to be understood that other variations may be made without departing from the intended scope of the invention. For example, a variety of MEMS devices using an assortment of semiconductor fabrication techniques, including various methods of etching and deposition, may be electrically isolated without departing from the scope of the invention itself. The claims should not be read as limited to the described order or elements unless stated to that effect. Therefore, all embodiments that come within the scope and spirit of the following claims and equivalents thereto are claimed as the invention.