Abstract:
The present invention provides a dual mode phase and frequency detector for use with a charge pump and a loop filter. The charge pump is adapted to adjust charging or discharging of the loop filter to adjust a VCO for generating a digital clock. The dual mode phase and frequency detector includes a phase and frequency detector and a first delay element. The phase and frequency detector is arranged to receive the VCO clock for tracking a reference clock signal. The phase and frequency detector generates control signals in response to the VCO clock and the reference clock signal. The control signals control charging or discharging of a loop filter in a DLL when the phase and frequency detector is operating in a phase and frequency detector mode. The first delay element is coupled to receive one of the control signals from the phase and frequency detector for generating an auxiliary control signal in response to the VCO clock. The first delay element generates the auxiliary control signal when the phase and frequency detector is operating in a phase detector mode. In this arrangement, the auxiliary control signal and the control signals control the charge pumps to charge or discharge the loop filter for adjusting the digital clock of the VCO when the phase and frequency detector is operating in the phase detector mode.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates generally to the field of data synchronizers. More particularly, the present invention relates to phase and frequency detectors in data synchronizers that can function as phase detectors without the need for a delay lock loop (DLL). 
     2. Description of the Related Art 
     Data communication and synchronization applications typically use a clock signal to synchronize and regulate the processing of data signal. For data processing, for example, the clock signals typically extracted from an incoming digital (e.g., binary) data signal in a digital signal format such as non-return-to-zero (NRZ) format. These applications generally use a phase-locked loop (PLL), often called data synchronizer or frequency synthesizer, to synchronize a clock signal with a digital data signal. 
     In data transmission, user data is often preceded by a preamble such as a sync field that contains a regular pattern of digital data. In data synchronizers, a phase and frequency detector may be used to lock the phase and frequency of the clock signal to that of the sync data whenever a sync field is encountered. In this manner, the clock in the data synchronizer is kept synchronized to the phase and frequency of the sync data. 
     After locking phase and frequency of the clock to the sync data, the data synthesizer receives data in the data field. In contrast to the data, the data in the data field is a random pattern of 0&#39;s and 1&#39;s. When such random data pattern is encountered, the data synchronizer needs to maintain a phase lock to the data while detecting the data. For such purposes, the data synchronizer uses a phase detector to maintain the phase lock. 
     Conventional data synchronizers have two main modes of operation: data/clock recovery and idle. During an idle mode, a data synchronizer locks to both the frequency and phase of a reference clock. On the other hand, during data recovery, the data synchronizer locks to only the phase of the incoming data since the frequency of the data changes depending on the data pattern. For example, a data pattern “001100110011” has a frequency twice that of a data pattern “000011110000.” However, because the data rate is the same for both patterns, the data synchronizer must recover the same clock for both patterns. 
     Traditionally, a delay lock loop (DLL), which is well known in the art, is used in conjunction with a phase and frequency detector to perform the two modes of operation. When used alone, the phase and frequency detector will perform both phase and frequency detection at the same time. The DLL is used to produce a data stream that is exactly 50% delayed. The non-delayed data is used to enable the phase and frequency detector. The delayed data is sent to the phase and frequency detector as data. Hence, the phase and frequency detector is enabled only for error correction when the data makes a transition from a “0” to “1”. In this manner, the DLL allows the phase and frequency detector to make only phase corrections and not frequency corrections. 
     FIG. 1 shows a schematic circuit diagram of a conventional phase and frequency detector  100  used with a data synchronizer. The phase and frequency detector  100  includes a pair of D flip-flops  102  and  104 , an AND gate  106 , and an OR gate  108 . The D flip-flops  102  and  104  are configured to receive a reference clock REFCLK which is the 50% delayed DATA and a voltage controlled oscillator (VCO) clock VCOCLK from a VCO (not shown), respectively. In addition, the “D” input ports of the flip-flops  102  and  104  are coupled to a high voltage rail vdd. The D flip-flops  102  and  104  generate output signals UP and DOWN, respectively. The UP and DOWN signals are correction signals that are provided to a charge pump (not shown) to speed up and slow down, respectively, the VCO that generates the VCOCLK. 
     As is well known in the art, each of the D flip-flops  102  and  104  outputs the states that is present on the “D” input as UP or DOWN signal whenever the clock signal goes high at the other input port (i.e., REFCLK and VCOCLK). The AND gate  106  is coupled to receive the outputs of the D flip-flops  102  and  104  as inputs and generates an output signal, which is provided to the OR gate  108  as an input. The OR gate  108  also configured to receive DATA during the phase only mode only. During phase and frequency lock mode, i.e., sync field, DATA is set to “1.” In response to the input signals, the OR gate  108  generates a reset signal RESET that is used to reset the flip-flops  102  and  104 . By either speeding up or slowing down the VCO via the charge pump using the UP and DOWN signals, the phase and frequency detector  100  locks the phase and frequency of the VCOCLK to those of the reference clock REFCLK. 
     When the phase and frequency detector  100  is used to detect data, the D flip-flop  102  receives incoming data signal as REFCLK. FIG. 2 illustrates a timing diagram  200  of the phase and freguency detector  100  when synchronizing REFCLK to DATA preamble signal. At the rising edge of the reference clock signal REFCLK at time T3, the signal DOWN is activated while UP signal remains inactive. Then, for a full cycle from time T3 time T5, the DOWN signal is provided to the charge pump to slow down the VCO because the REKCLK is deemed to be faster than the data. At the rising edge of next REFCLK pulse (i.e., time T5), the phase and frequency detector  100  detects the transition of data signal to high. The signals UP and DOWN are both high at this point so that no correction is needed. In response to the simultaneous activation of UP and DOWN signals, the AND gate  106  generates a RESET signal, which is provided for resetting the flip-flops  102  and  104 . As used herein, the DOWN and UP signals are correction signals and the net result of DOWN and UP signals is shown in FIG. 2 as waveform CORRECTION. 
     As can be seen from the timing diagram  200 , however, the phase and frequency detector  100  over corrects by a full clock cycle when a data pattern of two clocks periods is received. For example, from T3 to T5 and again from T7 to T9, the phase and frequency detector  100  overcorrects as indicated by the CORRECTION signal. This is because the signal DOWN should not have been activated at the second rising edge of REFCLK signal (i.e., time T3) because the REFCLK phase is aligned properly in phase. On the following REFCLK cycle (i.e., at time T5), the phase and frequency detector then activities the UP signal which resets the phase and frequency detector  100 . This same error occurs again at time T7. 
     The source of such over correction is that the phase and frequency detector  100  is comparing the incoming data&#39;s phase and frequency against the data synchronizer clock, which is typically a stream of pattern such as “010101010101.” If the data pattern were in a form such as “001100110011,” the phase and frequency detector would try to slow the data synchronizer clock down to match the frequency of the data. In practice, however, the data synchronizer clock typically need to be at higher frequency. Otherwise, the data will be recovered at the improper data rate. Clearly, the phase and frequency detector  100  will not recover data correctly without a gating signal. A DLL will provide the 50% delay DATA as a gating pulse. 
     The drawback of using the phase and frequency detector  100  to synchronize only phase of the VCOCLK to the data signal REFCLK is cost. In particular, using the phase and frequency detector  100  to track the phase of the data signal requires costly analog hardware such as a delay lock loop (DLL) with its own charge pump, loop filter, and a phase and frequency detector. Furthermore, such hardware arrangement typically requires substantially higher power that a complete digital solution for proper operation. 
     Thus, what is needed is a phase and frequency detector that can also be used for efficiently tracking phase of data signals without the high costs involved in conventional phase and frequency detectors. 
     SUMMARY OF THE INVENTION 
     Broadly speaking, the present invention fills these needs by providing a dual mode phase and frequency detector for a data synchronizer. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, computer readable media, or a device. Several inventive embodiments of the present invention are described below. 
     In one embodiment, the present invention provides a dual mode phase and frequency detector for use with charge pump and a loop filter. The charge pump is adapted to adjust charging or discharging of the loop filter to adjust VCO for generating a digital clock. The dual mode phase and frequency detector includes a phase and frequency detector and a first delay element. The phase and frequency detector is arranged to receive the VCO clock for tracking a reference clock signal. The phase and frequency detector generators control signals in response to the VCO clock and the reference clock signal. The control signals control charging or discharging of a loop filter in a DLL when the phase and frequency detector is operating in a phase and frequency detector mode. The first delay element is coupled to receive one of the control signals from the phase and frequency detector for generating an auxiliary control signal in response to the VCO clock. The first delay element generates the auxiliary control signal when the phase and frequency detector is operating in a phase detector mode. In this arrangement, the auxiliary control signal and the control signals control the charge pump to charge or discharge the loop filter for adjusting the digital clock of the VCO when the phase and frequency detector is operating in the phase detector mode. 
     In another embodiment, the present invention provides a dual mode phase and frequency detector for use with a charge pump and a loop filter, which is adapted to adjust a VCO for generating a VCO clock. The dual mode phase and frequency detector includes a phase and frequency detector and a first delay element. The phase and frequency detector is arranged to receive the VCO clock for tracking a reference clock signal. The phase and frequency detector generates a first control signal and a second control signal in response to the VCO clock and the reference clock signal. The first and second control signals control the charge pump for charging or discharging the loop filter when the phase and frequency detector is operating in a phase and frequency detector mode. The first delay element is coupled to receive the second control signal from the phase and frequency detector for generating an auxiliary control signal in response to the VCO clock. The first delay element generates the auxiliary control signal when the phase and frequency detector is operating in a phase detector mode. In this configuration, the auxiliary control signal and the first and second control signals control the charge pump that adjusts the charging or discharging of the loop filter for controlling the VCO clock when the phase and frequency detector is operating in the phase detector mode such that the VCO clock tracks only the phase of the reference clock signal. 
     In yet another embodiment, a data synchronizer is disclosed. The data synchronizer includes a charge pump, a loop filter, a VCO, a phase and frequency detector, and a first delay element. The charge pump is configured to generate an output signal for adjusting charging or discharging of the loop filter that generates a VCO control signal. The VCO is coupled to receive the VCO control signal from the loop filter where the VCO control signal is adapted to adjust the VCO for generating a VCO clock. The phase and frequency detector is coupled to receive the VCO clock for tracking a reference signal that has a phase and a frequency. The phase and frequency detector generates first control signals in response to the VCO clock and the reference signal. The control signals are adapted to control adjust the charge pump for tracking the phase and frequency of the reference signal. The first delay element is coupled to the phase and frequency detector for generating a second control signal. The first delay element generates the second control signal in response to one of the first control signals for tracking only the phase of the reference signal. In this arrangement, the first control signals and the second control signal are adapted to adjust the charge pump for tracking only the phase of the reference signal. 
     Advantages the use of the delay element (e.g., flip-flop, latch with reset capability) in conjunction with a phase and frequency detector provides significant savings in the cost, power, and die area over conventional solutions that typically uses expensive data locked loops with additional circuits such as a charge pump, filter, divider, etc. In addition, the present invention allows efficient correction for the worst case of half cycle delay with minimal data detection window closing that causes racing conditions and allows proper corrections to be made for less severe pulse sliding situations as well. Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustration by way of example the principles of the invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be readily understood by the following detailed description in conjunction with the accompanying drawings, in which like reference numerals designated like structural elements. 
     FIG. 1 shows a schematic circuit diagram of a conventional phase and frequency detector for use in a data synchronizer. 
     FIG. 2 illustrates a timing diagram of the phase and frequency detector in FIG. 1 when synchronizing REFCLK to DATA preamble. 
     FIG. 3 shows a dual mode phase and frequency detector in accordance with one embodiment of the present invention. 
     FIG. 4 illustrates a timing diagram of the dual mode phase and frequency detector when operating as a phase detector in accordance with one embodiment of the present invention. 
     FIG. 5 illustrates a more detailed block diagram of a delay element in accordance with one embodiment of the present invention. 
     FIG. 6 shows a timing diagram of signal waverforms when a data pulse slides forward in time by a half clock cycle. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention provides a dual mold phase and frequency detector that can function as either phase and frequency detector or phase-only detector. It will be obvious, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention. 
     FIG. 3 shows a data synchronizer  300  including a dual mode phase and frequency detector  301  in accordance with one embodiment of the present invention. The data synchronizer  300  also includes a charge pump  312 , a loop filter  316 , a VCO  314 , and an optional driver  318 . As will be discussed in more detail below, the dual mode phase and frequency detector  301  provides correction signals to the charge pump  312 . In response, the charge pump  312  generates a signal, a current in this embodiment, for controlling the VCO  314 . The filter  316 , which is preferably a low pass filter, receives and converts the current into a voltage, which is provided to the VCO  314 . In response to the voltage signal, the VCO  314  adjusts the speed of its output clock. The output clock is then fed into the driver, which divides the output clock by a specified factor to generate an adjusted VCOCLK. The VCOCLK is then provided as an input to the dual mode phase and frequency detector  301 . The entire loop reacts until the VCOCLK matches the phase and frequency of REFCLK. 
     The dual mode phase and frequency detector  301  includes flip-flops  302 ,  304 , and  308 , an AND gate  306 , and a delay circuit  310 . The flip-flops  302  and  304  receive a reference clock REFCLK and VCOCLK from the divider  318 , respectively, as inputs. The REFCLK is data when the detector  301  operates in a phase detection mode. On the other hand, the REFCLK is a preamble of the data when operating in a phase and frequency detection mode. 
     In addition, one of the input ports (e.g., D input ports) of each flip-flop  302  and  304  is coupled to a supply voltage rail vdd. In the illustrated embodiment, the flip-flops  302 ,  304 , and  308  are D flip-flops that outputs the state of the D input ports whenever the other input signal at the clock port transitions from low to high state. However, the flip-flops  302 ,  304 , and  308  may also be implemented by using any well known delay elements (e.g., latches, flip-flops, etc.) that can be set and reset. In an another embodiment, the AND gate may be implemented using any suitable logic elements such as a NAND gate to provide the equivalent function. 
     Each of the flip-flops  302 ,  304 , and  308  outputs the state of the D input ports as output signals UP 1 , DOWN, and UP 2 , respectively, when the input clock signal at the respective flip-flops  302 ,  304 , and  308  transitions from low to high. The output signals UP 1 , DOWN, and UP 2  of the flip-flops  302 ,  304 , and  308  are provided to a charge pump  312  for controlling the charge pump  312 , respectively, to adjust charging or discharging of the loop filter  316 . For example, the UP 1  and UP 2  signals enable the charge pump  312  to charge up the loop filter  316  while the DOWN signal allows the charge pump  312  to charge down the loop filter  316 . In response to the UP 1 , DOWN, and UP 2  signals, the charge pump  312  generates current signal that is provided to the loop filter  316 , which converts the current into a voltage signal. The charging of the loop filter  316  is a function of the net sum of the three signals UP 1 , UP 2 , and DOWN. That is, the net sum is the difference between the total charge up signals UP 1  and UP 2  and the DOWN signal, which is described as DOWN waveform XORed with UP 1  and UP 2  waveform. These signals adjust the charge pump  312  to charge up, down, or remain neutral depending on the net sum of the signals UP 1 , UP 2 , and DOWN. 
     The charge pump  312  outputs the current that is used, via loop filter  316 , to slow down or speed up the VCO  314 , which generates the VCOCLOK for tracking the input signal REFCLK at the flip-flop  302 . By controlling the charging of the charge pump  312  and thus the VCO, the phase and frequency detector  301  tracks the phase of the VCOCLK to that of the REFCLK. The AND gate  306  is coupled to receive the outputs of the flip-flops  302  and  304  as inputs. In response to the inputs, the AND gate  306  generates a reset signal as an output that is fed to the delay circuit  310 . The delay circuit  310 , which is optional, adds a delay to the reset signal. The delayed reset signal is then provided for resetting the flip-flops  302  and  304 . 
     The flip-flop  308  is coupled to receive the VCOCLK at its input clock port from the divider  318  and the DOWN signal at its D input port from the flip-flop  304 . When the signal at the input clock port changes state from low to high, the flip-flop  308  outputs the state of the DOWN signal at its “D” input port as UP 2  signal. The flip-flop  308  can be either enable or disable in response to an enable signal ENABLE (e.g., reset signal). For example, when ENABLE signal is inactive, the flip-flop  308  is disabled so that the flip-flop  308  does not generate the UP 2  signal. In this case, the dual mode phase and frequency detector  301  functions in phase and frequency detector mode. During this mode, the flip-flop  302  receives a regular pattern for signal REFCLK such as preamble of data. 
     On the other hand, when the ENABLE signal is active, the flip-flop  308  is activated to generate the UP 2  signal. In this case, the dual mode phase and frequency detector  301  functions as a phase-only detector. Thus, the dual mode phase and frequency detector  301  may function as either a phase and frequency detector or a phase detector. 
     FIG. 4 illustrates a timing diagram  400  of the dual mode phase and frequency detector  301  when operating as phase detector in accordance with one embodiment of the present invention. When operating in the phase-only detection mode, the flip-flop is enable by ENABLE signal. In addition, the flip-flops  304  and  308  receive VCOCLK at the input clock ports while the flip-flop  302  receives data for REFCLLK as DATA signal. At the rising edge of CLK (i.e., VCOCLK) at time T1, both DATA and VCOCLK signals transition from low to high. Hence, both UP 1  and DOWN signals transition from low to high at the outputs of flip-flop  302  and  304 , respectively. However, the UP 2  signal remains low at the output of the flip-flop  308  because the DOWN signal at the input of flip-flop  308  is still low during this transition time. In response to the high UP 1  and DOWN signals, the AND gate activates RESET 1 . Then, the flip-flops  302  and  304  are reset in response to RESET 1  so that both UP 1  and DOWN signals transition to low at time T2. Additionally, because the UP 1  and DOWN signals cancel each other out, the charge pump  312  does not change the charging state. Hence, no correction on VCOCLK takes place between T1 and T3. 
     Then, at the next rising edge of VCOCLK at T3, DOWN signal at the ouput of flip-flop  304  is activated (i.e., high). In the meantime, UP 1  signal remains inactive (i.e., low) at the output of flip-flop  302  because DATA is low at T3. Additionally, the UP 2  signal remains low at the output of the flip-flop  308  because the DOWN signal at the input of flip-flop  308  is still low during the transition time. In response to the low UP 1  and high DOWN states, the AND gates generates RESET 1  signal, which is low. According, the flip-flops  302  and  304  are not reset. Then, for a full clock cycle from time T3 to time T5, the activated DOWN signal is provided to the charge pump  312  as correction signal to slow down the VCO  314 , which is incorrect since the phase is aligned. This is because the correction signal CORRECTION corresponds to the net sum of the DOWN signal, which is high, and UP 1  and UP 2  signals, which are low during this period. This results in a negative correction, i.e., charge down, for one CLK cycle from T3 to T5. 
     During the next VCOCLK cycle from T5 to T7, the phase detector  300  performs a positive correction, i.e., charge up, to offset the positive correction performed during the previous VCOCLK cycle between T3 and T5. Specifically, at the rising edge of next VCOCLK pulse (i.e., T5), the flip-flop  304  samples and outputs the state of vdd at its “D” input port is DOWN, which is high. At the output of the flip-flop  308 , UP 2  signal also transitions from low to high because DOWN is high at T5. Similarly, UP 1  signal also transitions from low to high since DATA is high at T5. The AND gate  306  receives the high UP 1  and DOWN signals from the flip-flops  302  and  304  and generates a high state for RESET 1  signal. The optional delay element  310  delays the RESET 1  signal by a specified delay time and provides the delayed RESET 1  signal to reset the flip-flop  302  and  304 . 
     To cancel out the correction made in the previous CLK cycle from T3 to T5, the correction signal UP 2  remains high for one VCOCLK cycle width between T5 and T7. The net sum of the correction signals UP 1 , UP 2 , and DOWN is positive as shown in CORRECTION waveform between T5 and T7. Accordingly, the negative correction of the previous CLK cycle is offset by the positive correction to produce an overall correction of zero. This process continues in a similar manner so that, over time, the overall CORRECTION waveform exhibits zero net change when integrated over time. In this manner, the correction signal from flip-flop  308  is used to cancel out the over correction of the previous clock cycle. By using the flip-flop  308 , the dual mode phase and frequency detector  301  provides significant savings in cost, power, and die area over conventional solutions that typically use expensive data locked loops with additional analog circuits such as a charge pump, filter, divider, etc. 
     In the phase and frequency detector  301 , the delay element  310  functions to provide a specified delay for resetting the flip-flops  302  and  304 . For example, the delay element  310  may add a half cycle of delay to the reset signal from the AND gate  306  by employing any suitable number of delay logic elements such as inverters, flip-flops, etc. In one embodiment, delay logic elements may be inserted between flip-flops  302  and  304  and the charge pump  312  to ensure that minimum width of the UP 1  and DOWN signals to allow the charge pump  312  to turn on and off without causing a glitch. 
     In the example above, the phase and frequency detector  301  may cause the data synchronizer loop to go the wrong direction for a clock cycle before the correction takes place. This may add jitter to the data synchronizer clock. To reduce such jitter, UP 1  and DOWN signals may be delayed by a full clock cycle to allow the correction signal UP 2  to occur at the same time as the phase and frequency detector starts to go the wrong way. In one embodiment, one or more delay elements (e.g. inverts, buffers, latches, etc.) may be inserted in the signal paths to provide the full clock cycle delay. 
     During the detection of data in phase detection mode, the data signal may slide forward in time with reference to CLK signal. For example, one or more data pulses may slide forward in time. Typically, the worst case is where a data pulse slides forward in time by a half clock cycle. As is well known in the art, this may cause and undesirable race condition in a timing loop, thereby preventing effective tracking of the data signal phase. The race condition causes the DOWN and UP signals to reset before UP 2  can be clocked by the rising edge of VCOCLK. 
     In one embodiment, the delay element  310  is configured to add a half cycle of delay to the reset signal from the AND gate  306  to prevent such race conditions. FIG. 5 illustrates a more detailed block diagram of the delay element  310  in accordance with one embodiment of the present invention. The delay element  310  includes a flip-flop  502 , a pair of inverters  504  and  506 , and a multiplexer (MUX)  508 . In the phase and frequency detector mode, the reset signal from the AND gate  306  is provided to the inverters  504  and  506 , which are arranged to provide a specified minimum pulse width. The delayed reset signal is then provided to the multiplexer  508  as input. 
     In the phase detector mode, on the other hand, the flip-flop  502  is enabled by ENABLE signal and receives the reset signal from the AND gate  306  and an inverse VCO clock {overscore (VCOCLK)}. The flip-flop  502  delays the reset signal for half VCOCLK cycle and feeds the delayed reset signal to the multiplexer  508 . The multiplexer  508  transmits one of the delayed reset signals as RESET 1  signal in response to the ENABLE signal. On the other hand, if the ENABLE signal indicates a phase and frequency detection mode, the multiplexer  508  outputs the delayed reset signal from the inverter  506 . It should be noted that the ENABLE signal provided to the flip-flop  502  and the multiplexer  508  is the same signal provided to the flip-flop  308  used in generating correction signal UP 2  in FIG.  3 . In doing so, the flip-flop  502  allows efficient delaying of DOWN and UP by half cycle and therefore allows proper corrections to be made. 
     FIG. 6 shows a timing diagram  600  of signal waveform when a data pulse  602  slides forward in time by a half clock in accordance with one embodiment of the present invention. The VCOCLK, DOWN, and data waveforms in FIG. 6 are identical to those FIG. 4 except that the data pulse  604  has slid forward by a half clock cycle in time to data pulse  602 . When the data pulse  604  slides forward in time from by a half VCOCLK cycle, the positive and negative corrections will not cancel out to produce a CORRECTION waveform that exhibits zero net charge when integrated over time. 
     Initially, the timing diagram  600  is same as timing diagram  400  until time T4, which is falling edge of VCOCLK. When data pulse  602  that has slid forward in time by half a clock cycle is received at time T4, the DOWN signal at the output of flip-flop  304  remains high, which is a false correction. At the same time, the output signal UP 1  of flip-flop  302  transitions from low to high. In response to the high DOWN and UP 1  signals, the AND gate  306  and the delay element  310  produce a RESET 1  signal that is delayed by a half CLK cycle. This causes the flip-flops  302  and  304  to reset so that the DOWN and UP 1  signals transition to low at T6. On the other hand, the correction signal UP 2  at the output of flip-flop  308  transitions from low to high at T5 in response to the high DOWN signal and the rising edge of VCOCLK and remains high for one VCOCLK cycle from T5 and T7. As shown in FIG. 6, the net correction as indicated by CORRECTION signal  606  between T3 and T7 is positive for a half clock cycle. In response to this positive half clock, the charging pump  312  charges up the loop filter  316  to accelerate the VCO  314 . 
     The present invention, a dual mode phase and frequency detector, is thus described. Although the foregoing invention has been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced with the scope of appended claims. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified with the scope and equivalents of the appended claims.