Abstract:
The present invention relates to a power managing apparatus utilized for controlling a first supply voltage, a second supply voltage, and a substrate voltage of a digital circuit. The power managing apparatus includes a voltage generating device, for generating a first reference voltage and a second reference voltage; and a voltage switching device, coupled to the voltage generating device, for adjusting the first supply voltage, the second supply voltage, and the substrate voltage. When the digital circuit operates in a first operating mode, the voltage switching device outputs the second reference voltage to the first supply voltage and the substrate voltage; and when the digital circuit operates in a second operating mode, the voltage switching device outputs the first reference voltage to the first supply voltage, and outputs the second reference voltage to the second supply voltage.

Description:
BACKGROUND OF THE INVENTION  
       [0001]    1. Field of the Invention 
         [0002]    The present invention is related to power management, and more particularly, to a power management circuit using a voltage regulator to control the substrate bias and supply voltage in a CMOS digital circuitry. 
         [0003]    2. Description of the Prior Art 
         [0004]    With the advances in complementary metal oxide semiconductor (CMOS) technology, the channel length and the diffusion area of a transistor are decreased, and which getting an advantage of low parasitic capacitance effect in design a CMOS circuitry. However, with the diffusion area of the transistor is reduced, the short channel effect will occur. It will increase the leakage current of the transistor to further cause larger power consumption in an integrated circuit. In order to overcome such problem, body biasing apparatus is designed. The body biasing apparatus in the CMOS circuit is capable of decreasing the junction capacitance between the diffusion region and substrate. 
         [0005]    Please refer to  FIG. 1 .  FIG. 1  is diagram illustrating a conventional body biasing apparatus  10 . The conventional body biasing apparatus  10  utilizes a charge pump  14   a ,  14   b  to generate a positive voltage V+ that is higher than a system voltage (Vdd), and to generate a negative voltage V− that is lower than a ground voltage (Vgnd), respectively control the body of the PMOS transistor MP and the body of the NMOS transistor MN of CMOS circuit  12 . In normal operation, switching control signal SB_enable controls switches  16   a ,  16   b  to selectively connect to the system voltage Vdd and the ground voltage Vss. In other words, the body of the PMOS transistor MP and the body of the NMOS transistor MN are respectively connected to the system voltage Vdd and the ground voltage Vss. Please note that, when the source of the PMOS transistor MP and the source of the NMOS transistor MN are respectively connected to the system voltage Vdd and the ground voltage Vss, the body of the PMOS transistor MP and the body of the NMOS transistor MN are also connected to the system voltage Vdd and the ground voltage Vss, respectively. Alternatively, when system operates in standby mode, switching control signal SB_enable controls switch  16   a  to choose voltage V+, then the substrate of the PMOS transistor MP is connected to a voltage that is higher than the system voltage Vdd. Accordingly, the threshold voltage of PMOS transistor MP is thereby increased that will reduce the leakage current because the substrate voltage is higher than the source voltage. Similarly, in the standby mode, switching control signal SB_enable controls switch  16   b  to choose voltage V− to thereby increase the threshold voltage of NMOS transistor MN that will also reduce the leakage current. 
         [0006]    However, the operation of charge pumps  14   a ,  14   b  is driven by an oscillator that provides the clock signal to control the charging and the discharging of the capacitor, therefore an extra consume current is required by the conventional body biasing apparatus  10  that will increase the number of devices on the chip. Furthermore, if the voltage V+, V− is provided by, for example, an off chip source, then not all of the voltage can be supplied from off chip, thereby some of the pins of the chip will be needed for adding the receiving voltage V+, V−. 
       SUMMARY OF THE INVENTION  
       [0007]    It is therefore an objective of the present invention is to provide a power managing apparatus that utilizes a body biasing and provide a supply voltage, to solve the above-mentioned problems. 
         [0008]    According to an embodiment of the present invention, a power managing apparatus is disclosed. The power managing apparatus, for controlling a first supply voltage, a second supply voltage, and a substrate voltage of a digital circuit, includes: a voltage generating device, for generating a first reference voltage and a second reference voltage; a voltage switching device, coupled to the voltage generating device, for adjusting the first supply voltage, the second supply voltage, and the substrate voltage; wherein when the digital circuit operates in a first operating mode, the voltage switching device outputs the second reference voltage to be the first supply voltage and be the substrate voltage; and when the digital circuit operates in a second operating mode, the voltage switching device outputs the first reference voltage to be the first supply voltage, and outputs the second reference voltage to be the second supply voltage. 
         [0009]    According to another embodiment of the present invention, a power managing apparatus is disclosed. The power managing apparatus is for controlling supply voltage of transistors in a digital circuit, where the digital circuit comprises at least a PMOS transistor and an NMOS transistor. The power managing apparatus includes: a voltage generating device, for generating a first reference voltage and a second reference voltage; and a voltage switching device, coupled to the voltage generating device, for adjusting the supply voltage of the PMOS transistor and the NMOS transistor. When the digital circuit operates in a first operating mode, the voltage switching device outputs the second reference voltage to source terminal of the PMOS and body of the PMOS; and when the digital circuit operates in a second operating mode, the voltage switching device outputs the first reference voltage to source terminal of the PMOS transistor, and outputs the second reference voltage to source terminal of the NMOS transistor. 
         [0010]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0011]      FIG. 1  is diagram illustrating a conventional body biasing apparatus. 
           [0012]      FIG. 2  is a diagram illustrating a power managing apparatus according to an embodiment of the present invention. 
           [0013]      FIG. 3  is a diagram illustrating a power managing apparatus according to a second embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION  
       [0014]    Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, consumer electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . ” The terms “couple” and “couples” are intended to mean either an indirect or a direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. 
         [0015]    Please refer to  FIG. 2 .  FIG. 2  is a diagram illustrating a power managing apparatus  200  according to an embodiment of the present invention. The power managing apparatus  200  is utilized for biasing a CMOS circuit. Please note that to the power managing apparatus  200  is intended to represent an embodiment and is not a limitation of the present invention, specifically, the PMOS transistor and NMOS transistors are not limiting factors. In  FIG. 2 , the P-substrate of the NMOS transistor M 2  is connected to ground (e.g., connected to a ground voltage Vgnd). The power managing apparatus  200  comprises a first voltage generator  104 , a second voltage generator  106 , and a voltage switching apparatus  108 . The first voltage generator  104  is utilized for providing a first reference voltage V 1  to PMOS transistor M 1 ; the second voltage generator  106  is utilized for providing a second reference voltage V 2  to NMOS transistor M 2 , wherein the both first, second reference voltage V 1 , V 2  are positive voltage and the first reference voltage VI is higher than the second reference voltage V 2 . 
         [0016]    The voltage switching apparatus  108  is coupled to a first, and a second voltage source  104 ,  106 , a first system voltage Vdd, a ground voltage Vgnd, a PMOS transistor M 1 , and an NMOS transistor M 2 . In this embodiment, the first, and the second voltage generator  104 ,  106  are implemented by a voltage regulator. For the voltage switching apparatus  108 , a first switching device  110  is coupled to the source of the PMOS transistor M 1  and the second voltage source  106  in a first circuit connecting configuration, and coupled to the source of the PMOS transistor M 1  and the first voltage source  104  in a second circuit connecting configuration; a second switching device  112  is coupled to the substrate of the PMOS transistor M 1  and the second voltage source  106  is in the first circuit connecting configuration, and coupled to the substrate of the PMOS transistor M 1  and a third reference voltage (such as the system voltage Vdd) is in the second circuit connecting configuration. In this embodiment, the third reference voltage is higher than the first reference voltage; and a third switching device  114  coupled to the source of the NMOS transistor M 2  and the ground voltage Vgnd in the first circuit connecting configuration, and coupled to the source of the NMOS transistor M 2  and the second voltage source  106  in the second circuit connecting configuration. 
         [0017]    When the power managing apparatus  200  operates in a first operating mode that comprises the first circuit connecting configuration, the CMOS circuit  102  is in the normal operation. As described above in reference to  FIG. 1 , in the normal operation, the source voltage level of the PMOS transistor M 1  and the NMOS transistor M 2  should be equal to the voltage level of the substrate. For the purpose of description, this embodiment sets Vdd, V 1 , V 2 , and Vgnd to be 1.8V, 1.5V, 1V, and 0V, respectively. The voltage switching apparatus  108  controls the first switching device  110  to couple the source of the PMOS transistor M 1  to the second voltage source  106 , therefore the source voltage of the PMOS transistor M 1  is the second reference voltage V 2  (i.e., 1V). Additionally, the voltage switching apparatus  108  controls the second switching device  112  to couple the substrate of the PMOS transistor M 1  to the second voltage source  106 , therefore the substrate voltage of the PMOS transistor M 1  is the second reference voltage V 2  (i.e., 1V). Additionally, the voltage switching apparatus  108  controls the third switching device  114  to couple the source of the NMOS transistor M 2  to the ground voltage Vgnd, therefore the source voltage of the NMOS transistor M 2  is 0V. 
         [0018]    On the other hand, when power managing apparatus  200  operates in a second operating mode that comprises the second circuit connecting configuration, the CMOS circuit  102  is in the standby mode. As described above in reference to  FIG. 1 , in the standby mode, the body effect of the PMOS transistor M 1  and the NMOS transistor M 2  will increase the threshold voltage of the PMOS transistor M 1  and the NMOS transistor M 2  thereby consequently decreasing the leakage current. Therefore, the voltage switching apparatus  108  controls the first switching device  110  to couple the source of the PMOS transistor M 1  to the first voltage source  104 , therefore the source voltage of the PMOS transistor M 1  is the first reference voltage V 1  (i.e., 1.5V). Additionally, the voltage switching apparatus  108  controls the second switching device  112  to couple the substrate of the PMOS transistor M 1  to the third reference voltage (e.g., the third reference voltage is the system voltage Vdd in this embodiment, 1.8V). Additionally, the voltage switching apparatus  108  controls the third switching device  114  to couple the source of the NMOS transistor M 2  to the second voltage source  106 , therefore the source voltage of the NMOS transistor M 2  is in this embodiment 0.8V. Accordingly, the substrate voltage of the PMOS transistor M 1  is higher than the source voltage 0.3V, and the substrate voltage of the NMOS transistor M 2  is higher than the source voltage 0.8V, thereby conforming to the condition of generating the body effect. The CMOS circuit  102  is capable of reducing the leakage current in standby mode and thereby reducing the power loss. Please note that the CMOS circuit  102  is simplified as an inverter in  FIG. 2 . 
         [0019]    Furthermore, in this embodiment of the present invention, to generate the body effect of the PMOS transistor M 1  in the standby mode, the first reference voltage V 1  that generated of the first voltage generator  104  is a positive voltage, and lower than the third reference voltage (i.e., the system voltage Vdd). However, it is well known that whenever the substrate voltage is higher than the source voltage, the body effect results. Therefore, the present invention is not limited to the positive voltage of the first reference voltage V 1  that is generated by the first voltage generator  104 . For example, in another embodiment of the present invention, the first voltage generator  104  can be designed to output a first reference voltage V 1  that corresponds to a negative voltage which can also drive the PMOS transistor M 1  to have the body effect in the standby mode. 
         [0020]    Please refer to  FIG. 3 .  FIG. 3  is a diagram illustrating a power managing apparatus  400  according to a second embodiment of the present invention. In  FIG. 3 , a voltage level shifter  308  coupled to an output terminal Out of the CMOS circuit  102  is utilized for adjusting a logic level of the output signal. The voltage level shifter  308  is well known to those having average skill in this art, and therefore additional description is omitted for the sake of brevity. The power managing apparatus  400  comprises a first regulating circuit  304 , a second regulating circuit  306 , and voltage switching apparatus  108 . The first regulating circuit  304  is utilized for providing a first reference voltage V 1  to the PMOS transistor M 1 . The second regulating circuit  306  is utilized for providing a second reference voltage V 2  to the NMOS transistor M 2 . The power managing apparatus  400  as shown in  FIG. 3  adopts a current reuse method to implement the first regulating circuit  304  and the second regulating circuit  306 . 
         [0021]    In this embodiment of the present invention, the first regulating circuit  304  comprises a first shunt voltage regulator  3042  and a p-channel pass transistor Mp 1 , wherein an output terminal of the first shunt voltage regulator  3042  is coupled to the source of the p-channel pass transistor Mp 1 . The first shunt voltage regulator  3042  provides the first reference voltage V 1  of the Vdd-V_SVR 1 , however, the current is only I_VR 1 . Furthermore, the total current I_load 1  that consumed by the first regulating circuit  304  can be reused by CMOS circuit  102  because the first regulating circuit  304  is not connected to ground directly. When the current I_load 1  changed, the first shunt voltage regulator  3042  adjusts the gate voltage Vctrl 1  of the p-channel pass transistor Mp 1  to adjust the current I_PE 1 . Next, the first shunt voltage regulator  3042 provides the current I_load 1  as a feedback. Furthermore, the second regulating circuit  306  comprises a second shunt voltage regulator  3062  and an n-channel pass transistor Mn 1 , wherein an output terminal of the second shunt voltage regulator  3062  is coupled to the source of the n-channel pass transistor Mn 1 . The second shunt voltage regulator  3062  provides the second reference voltage V 2  of the V_SVR 2 -Vgnd, however, the current is only I_VR 2 . Furthermore, the total current I_load 2  that consumed by the second regulating circuit  306  is equal to the current of CMOS circuit  102  because the second regulating circuit  306  is not connected to the system voltage Vdd directly. When the current I_load 2  of the CMOS circuit  302  changes, the second shunt voltage regulator  3062  adjusts the gate voltage Vctrl 2  of the n-channel pass transistor Mn 1  to adjust the current I_PE 2 , then feedbacks to current I_load 2 . Please note that, this embodiment of the present invention; the shunt voltage regulator is utilized by way of example and not limitation. It is well known to those having average skill in this art that a conventional voltage regulator, a linear regulator, or switching regulator can also be utilized according to the given requirements. 
         [0022]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.