Abstract:
A new method of forming source/drain buried contact junctions is described. The method of forming a buried contact to a source/drain junction or other active device region in a silicon substrate is described. A first polysilicon layer is deposited over the surface of a silicon substrate. A second layer of polysilicon is deposited over the first layer of polysilicon wherein the polysilicon grain boundaries of the first and second polysilicon layers will be mismatched. The second polysilicon layer is doped. The grain boundary mismatch will slow the diffusion of the dopant into the silicon substrate. The dopant is driven in to form the buried contact with a shallow junction.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming shallow buried contact junctions in the fabrication of integrated circuits. 
     2. Description of the Prior Art 
     A typical buried contact process flow is to deposit a doped layer of polysilicon over and on the planned buried contact regions, which may be source/drain regions. The structure is heated and the source/drain regions are doped by outdiffusion of dopants from the doped polysilicon layer into the silicon substrate. The doped polysilicon layer is allowed to remain on the source/drain regions as their contacts. This is called the buried contact process. 
     Because of the high diffusivity of the polysilicon dopant, it is difficult to control junction depth. A number of patents have addressed this and other problems involving forming source/drain regions. U.S. Pat. No. 5,049,514 to Mori shows a process of doping polysilicon, forming an opening to the substrate, forming a metal silicide layer within the opening, ion implanting, and annealing to form the source/drain region. U.S. Pat. No. 5,030,584 to H. Nakata describes a process involving outdiffusion to form source/drain regions and to leave the contact and source of dopants for the source/drain regions in place. While this patent&#39;s invention has the advantage of self alignment of the contact to the source/drain, it does not have the desired tailoring of the source/drain regions to the optimum conditions for the under one micron era. Patent disclosure Ser. No. 07/941229 to J. Y. Lee filed on Sept. 9, 1992 uses two layers of polysilicon to form a buried contact region in the substrate, However, only poly 2 actually touches the substrate. 
     SUMMARY OF THE INVENTION 
     A principal object of the present invention is to provide an effective and very manufacturable method of forming buried contact junctions. 
     Another object of the present invention is to provide a method of forming shallow buried contact junctions with a junction depth that is 1/3 to 1/2 that of the prior art. 
     In accordance with the objects of this invention a new method of forming source/drain buried contact junctions is achieved. The method of forming a buried contact to a source/drain junction or other active device region in a silicon substrate is described. A first polysilicon layer is deposited over the surface of a silicon substrate. A second layer of polysilicon is deposited over the first layer of polysilicon wherein the polysilicon grain boundaries of the first and second polysilicon layers will be mismatched. The second polysilicon layer is doped. The grain boundary mismatch will slow the diffusion of the dopant into the silicon substrate. The dopant is driven in to form the buried contact with a shallow junction. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the accompanying drawings forming a material part of this description, there is shown: 
     FIG. 1 schematically illustrates in cross-sectional representation the polysilicon grain boundaries of the process of the prior art. 
     FIG. 2 schematically illustrates in cross-sectional representation the polysilicon grain boundaries of the process of the present invention. 
     FIG. 3 schematically illustrates a circuit diagram of one preferred embodiment of this invention for a static random access memory (SRAM). 
     FIG. 4 schematically illustrates a top view of one preferred embodiment of this invention for a SRAM. 
     FIG. 5 schematically illustrates in cross-sectional representation the view 5--5 of FIG. 4. 
     FIG. 6A schematically illustrates in cross-sectional representation one alternative of the view 6--6 of FIG. 4. 
     FIG. 6B schematically illustrates in cross-sectional representation a second alternative of the view 6--6 of FIG. 4. 
     FIG. 7 schematically illustrates a circuit diagram of a second preferred embodiment of this invention for a dynamic random access memory (DRAM). 
     FIG. 8 schematically illustrates a top view of one preferred embodiment of this invention for a DRAM. 
     FIG. 9 schematically illustrates in cross-sectional representation the view 9--9 of FIG. 8. 
     FIGS. 10, 11, and 12 illustrate in graphical representation the sheet resistance of various wafer samples. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring now more particularly to FIG. 1, there is shown a portion of a partially completed integrated circuit of the prior art. There is shown a monocrystalline semiconductor substrate 10 in which there are formed field oxide regions 12. A polysilicon layer 13 has been deposited over the surface of the substrate. The polysilicon layer is doped. The dopant diffuses into the silicon substrate to form the buried junction region 20 with a junction depth of 21. 
     The process of the invention now will be described. Referring to FIG. 2, there is shown a portion of a partially completed integrated circuit. There is shown a monocrystalline semiconductor substrate 10 in which there are formed field oxide regions 12. 
     The polysilicon layer 14 is blanket deposited by low pressure chemical vapor deposition (LPCVD) at a temperature of between about 450° to 625° C. to a thickness of between about 50 to 2500 Angstroms. The wafer is removed from the furnace and allowed to cool to between about 25° to 380° C. The wafer is returned to the furnace and a second layer 16 of polysilicon is deposited at the same temperature of between about 450° to 625° C. to a thickness of between about 100 to 2500 Angstroms. The wafer is again cooled, and a third layer of polysilicon (not shown) may be deposited, as described above. 
     Cooling the wafer to less than about 300° C. between polysilicon layer depositions prevents the growth of native oxide between the layers. Alternatively, a dilute hydrofluoric acid dip before subsequent layer deposition will prevent native oxide formation between layers. 
     After the polysilicon layers have been formed, the dopant is applied either by diffusion or by ion implanting the top polysilicon layer. For diffusion, a POCl 3  process is used at a high temperature of between about 850° to 950° C. For ion implantation, phosphorus or arsenic ions are implanted to produce N+ regions or boron or BF 2  ions are implanted to produce P+ regions. Preferred dosages are in the range of about 5 E 14 to 5 E 16 atoms/cm 2 . Alternately, the top polysilicon layer could be in-situ doped with phosphine. 
     Polysilicon grain growth is affected by deposited surface condition. Therefore, the grain orientation is different for deposition on single crystal silicon, silicon dioxide, or polysilicon layers. This causes the mismatch in grain boundaries seen in FIG. 2. The mismatched polysilicon grain boundaries prevent the channeling of the dopants so that the diffusivity of the dopants into the silicon substrate is reduced. 
     The dopants are driven into the silicon substrate at a temperature of between about 800° to 1000° C. This is done typically in subsequent back-end thermal cycles such as source/drain oxidation, interlevel dielectrics densification, and borophosphosilicate glass (BPSG) flow. The completed buried junction 22 has a junction depth 23 which is 1/3 to 1/2 the junction depth 21 of the prior art, shown in FIG. 1. 
     This approach can be directly applied on static random access memory (SRAM) buried contacts and dynamic random access memory (DRAM) cell contacts for the next generation technology development. 
     Referring now to FIG. 3, there is shown a circuit diagram of a SRAM cell. This SRAM cell is a 4-transistor polysilicon-load flip-flop inverter connection. It includes 2 access transistors T1 and T2, 2 pull-down transistors T3 and T4, and 2 high-resistivity polysilicon regions P1 and P2 as load elements. Bit line (BL) A and word line (WL) are also shown. Buried contacts BC1 and BC3 are shown. S1 is a stacked contact. FIG. 4 is a top view of the SRAM circuit in FIG. 3. (View 3--3 is indicated on FIG. 4) The stacked contact S1 is not illustrated in FIG. 4. 
     FIG. 5 illustrates view 5--5 of FIG. 4. Polysilicon layers 14 and 16 form the gates of the pull-down transistors T3 and T4. Junction depth 23 is between about 0.5 to 0.8 microns. For 0.8 micron technology, the junction depth 23 will be approximately 0.7 microns. For 0.65 micron technology, the junction depth 23 will be approximately 0.5 microns. 
     FIGS. 6A and 6B illustrate view 6--6 of FIG. 4. Polysilicon layers 14 and 16 form the capacitor bottom plate of the SRAM. Regions 29 are formed by dopant diffusion from layer 16, which is doped by diffusion or ion implantation. Lightly doped N- regions 25 are formed using arsenic or phosphorus implantation at a dosage of between about 5 E 12 to 5 E 14 atoms/cm 2  and energy of between about 50 to 100 KeV. In the approach illustrated in FIG. 6A, there is no N+ implantation into the DRAM cell. This is so to reduce any junction leakage caused by the N+ implantation. As described above, junction depth 23 is between about 0.5 to 0.8 microns. The depth 27 of the lightly doped source/drain region 25 is between about 0.15 to 0.20 microns. 
     In a second approach, illustrated in FIG. 6B, heavily doped N+ regions 28 are formed within the silicon substrate by using arsenic implantation at a dosage of between about 1 E 15 to 6 E 15 atoms/cm 2 . The junction depth 27 will be between about 0.20 to 0.25 microns. As above, the junction depth 23 is between about 0.5 to 0.8 microns. 
     Referring now to FIG. 7, there is shown a circuit diagram of a DRAM cell consisting of an access transistor T1 and a capacitor C1 for charge storage. FIG. 8 is a top view of the DRAM circuit in FIG. 7. Capacitor bottom plates 28 are illustrated here, in FIG. 7, and in FIG. 9, which illustrates view 9--9 of FIG. 8. Also shown in FIG. 8 are word lines (WL) and bit lines (BL). Bit line contact 34 is shown to the left of FIG. 8. Referring to FIG. 9, the capacitor bottom plates 28 are shown. 30 is the interlevel oxide layer. The capacitor dielectric and top capacitor plate are not shown in FIG. 9. 
     For a 4 Megabit DRAM, the feature size 32 (in FIG. 8) is about 0.7 microns. Junction depth 23 of buried contact region 22 in FIG. 9 will be approximately 0.6 microns for a conventional buried contact. For a 16 Megabit DRAM, the feature size 32 is about 0.5 microns. Junction depth 23 will be approximately 0.3 microns. 
     EXAMPLES 
     The following Examples are given to show the important features of the invention and to aid in the understanding thereof and variations may be made by one skilled in the art without departing from the spirit and scope of the invention. 
     Two or three layers of polysilicon with varying thicknesses were consecutively deposited on bare silicon. The control group had a single deposited polysilicon layer with the same thickness as the total thickness of the experimental samples. All samples were under identical thermal treatment of 30 minutes at 850° C. SIMS analyses were performed to determine junction depth. 
     EXAMPLE 1 
     The first Example compared junction depths of buried contacts formed using a two-layer polysilicon sample to the control sample having a total polysilicon thickness of 3500 Angstroms. Dopant sources were ion implant of phosphorus at an energy of 50 KeV and dosage of 6 E 15 atoms/cm 2  or diffusion of POCl 3  at 850° C. The results are shown in Table 1. 
     
                       TABLE 1______________________________________#     Poly-Si Layer              Dopant       Junction Depth______________________________________1     3500 A       P/50/6E15    0.12 um2     2000 A/1500 A              P/50/6E15    0.04 um3     3500 A       850° C. POCl.sub.3                           0.13 um4     2000 A/1500 A              850° C. POCl.sub.3                           0.07 um______________________________________ 
    
     EXAMPLE 2 
     The second Example compared junction depths of buried contacts formed using a three-layer polysilicon sample to the control sample having a total polysilicon thickness of 5000 Angstroms. Dopant sources were ion implant of phosphorus at an energy of 50 KeV and dosage of 6 E 15 atoms/cm 2 , ion implant of arsenic at an energy of 100 KeV and dosage of 6 E 15 atoms/cm 2 , or diffusion of POCl 3  at 850° C. The results are shown in Table 2. 
     
                       TABLE 2______________________________________#    Poly-Si Layer   Dopant      Junction Depth______________________________________1    5000 A          P/50/6E15   0.20 um2    2000 A/1500 A/1500 A                P/50/6E15   0.07 um3    5000 A          As/100/6E15 0.12 um4    2000 A/1500 A/1500 A                As/100/6E15 0.08 um5    5000 A          850° C. POCl.sub.3                            0.20 um6    2000 A/1500 A/1500 A                850° C. POCl.sub.3                            0.06 um______________________________________ 
    
     From the two Examples shown above, it can be seen that junction depth is significantly reduced, from 1/3 to 1/2, for samples with multiple deposits of polysilicon layers. Representative SIMS analysis profiles are shown in FIGS. 10, 11, and 12. FIG. 10 is the SIMS profile 51 for the sample number 1 in Table 1. FIG. 11 is the SIMS profile 52 for the sample number 2 in Table 1. FIG. 12 shows the SIMS profile for samples 3 (line 53) and 4 (line 54) in Table 2. From the surface concentration of SIMS profiles, it can be seen that the sheet resistance of the multiple layer samples is comparable or smaller than the sheet resistance of the control group. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.