Abstract:
A clock distribution apparatus for providing a local clock signal having a first voltage swing to a circuit unit being on a same substrate includes a global clock distribution network for generating and distributing a global clock signal having a second voltage swing being less than the first voltage swing; and a local clock converting unit being electrically connected between the global clock distribution network and the circuit unit. The local clock converting unit includes a level shifter for converting the global clock signal into the local clock signal.

Description:
BACKGROUND  
       [0001]     The present invention relates to clock distribution circuitry, and more particularly, to low power clock distribution circuitry.  
         [0002]     In integrated circuit designs, a clock distribution network (also referred to as a “clock tree”) consumes a considerable percentage of the total active power of the integrated circuit. Therefore, in the related art, a power savings technique referred to as “clock-gating” is widely applied to moderate overall power consumption within the integrated circuit.  
         [0003]     The clock-gating technique reduces the power consumption of the clock distribution tree by disabling or “gating off” the clocks fed to some circuit units of the integrated circuit while those circuit units are not in use.  
         [0004]     A problem with clock gating is that it requires additional logic (e.g., clock gating logic) and a control unit to manage the clock gating control signals. In order to have a net power savings, the clock gating logic must consume less power than is saved by gating the clocks off.  
         [0005]     Unfortunately, the related art clock gating techniques do not provide significant power reduction when the integrated circuit is in full operation. That is, the power savings of the integrated circuit is not obvious or is limited when intensive processing is occurring and/or all circuit units of the integrated circuit are in use. Accordingly, a need exists for improving the power consumption of clock trees.  
       SUMMARY OF INVENTION  
       [0006]     It is therefore an objective of the claimed invention to provide a low power clock distribution apparatus and related method to solve the above-mentioned problems.  
         [0007]     According to an exemplary embodiment of the present invention, a clock distribution apparatus for providing a local clock signal having a first voltage swing to a circuit unit is disclosed comprising: a global clock distribution network for generating and distributing a global clock signal having a second voltage swing being less than the first voltage swing; and a local clock converting unit electrically connected between the global clock distribution network and the circuit unit, the local clock converting unit comprising a level shifter for converting the global clock signal into the local clock signal. Wherein the clock distribution apparatus and the circuit unit are on a same substrate.  
         [0008]     According to another exemplary embodiment of the present invention, a method for providing a local clock signal having a first voltage swing to a circuit unit is disclosed. The method comprises generating a global clock signal having a second voltage swing being less than the first voltage swing; distributing the global clock signal; and utilizing a level shifter to convert the global clock signal into the local clock signal.  
         [0009]     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0010]      FIG. 1  is a block diagram of a clock distribution network according to a first embodiment of the present invention.  
         [0011]      FIG. 2  is a simplified block diagram of a clock distribution network according to a second embodiment of the present invention.  
         [0012]      FIG. 3  shows a layout diagram of a clock distribution network according to an exemplary embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0013]     Please refer to  FIG. 1 , which shows a block diagram of a clock distribution network  100  according to a first embodiment of the present invention. As shown in  FIG. 1 , the clock distribution network  100  comprises a global clock generator  120 , a distribution network  130  electrically connected to the global clock generator  120 , and two level shifters  142  and  144  electrically connected between the distribution network  130  and a high-voltage area  150 . In this embodiment, the high-voltage area  150  comprises at least two circuit units  152  and  154 . The two circuit units  152  and  154  operate at a first operating voltage VCCH and are electrically connected to the first level shifter  142  and the second level shifter  144 , respectively. The two circuit units  152  and  154  may be any IC component. Generally, all components of the clock distribution network  100  are on a same substrate.  
         [0014]     The clock distribution network  100  reduces power consumption by lowering the voltage swing of clock signal to be distributed. Specifically, the global clock generator  120  receives an input clock signal SCLK and accordingly produces a global clock signal GCLK, wherein the voltage swing of GCLK is lower than the voltage swing of SCLK. In practical implementations, the input clock signal SCLK is generated by a clock source (not shown) such as a crystal oscillator, a DCO (digital controlled oscillator), etc. In this embodiment, the input clock signal SCLK has a first voltage swing, which is substantially from a ground voltage GND to the first operating voltage VCCH, while the global clock signal GCLK has a second voltage swing, which is substantially from the ground voltage GND to a second operating voltage VCCL lower than the first operating voltage VCCH. The operation and implementations of the global clock generator  120  are well known in the art and therefore are not described further herein. The global clock signal GCLK is then distributed through the distribution network  130 .  
         [0015]     Depending on the circuit designs, the timing and/or phase of a global clock signal been transmitted to the first level shifter  142  may be differ to another global clock signal been transmitted to the second level shifter  144 . Accordingly, as shown in  FIG. 1 , the global clock signal received by the first level shifter  142  is denoted as GCLK 1  while the global clock signal received by the second level shifter  144  is denoted as GCLK 2 . Generally, both the global clock signals GCLK 1  and GCLK 2  have the same voltage swing as the global clock signal GCLK produced from the global clock generator  120 . In other words, both the global clock signals GCLK 1  and GCLK 2  are low swing clock signals.  
         [0016]     As shown in  FIG. 1 , each of the level shifters  142  and  144  is coupled to both the first operating voltage VCCH and the second operating voltage VCCL. In this embodiment, for example, the second operating voltage VCCL is 1.6V while the first operating voltage VCCH is 1.8V. In this embodiment, the first level shifter  142  is used for converting the low swing global clock signal GCLK 1  into a full swing first local clock signal LCLK 1 . The second level shifter  144  is used for converting the low swing global clock signal GCLK 2  into a full swing second local clock signal LCLK 2 . Preferably, both the first local clock signal LCLK 1  and the second local clock signal LCLK 2  have the same voltage swing as the input clock signal SCLK, i.e., the voltage swing of the first and second local clock signals LCLK 1  and LCLK 2  are substantially from the ground voltage GND to the first operating voltage VCCH. Accordingly, the local clock signals LCLK 1  and LCLK 2  can drive the circuit units  152  and  154 , respectively. Depending on the circuit designs, the timing and/or phase of the first local clock signal LCLK 1  could differ to that of the second local clock signal LCLK 2 .  
         [0017]     As mentioned above, the low swing global clock signal GCLK is distributed through the distribution network  130 . In order to achieve low power clock distribution, components of the distribution network  130  of this embodiment are designed to properly operate with the low swing global clock signal GCLK. In other words, all the components of the distribution network  130  are low-voltage components, which operate properly at the second operating voltage VCCL.  
         [0018]     In the embodiment shown in  FIG. 1 , the distribution network  130  comprises a plurality of low-voltage components  130   a ˜ 130   f.  Each of the plurality of low-voltage components  130   a  through  130   f  may be a driving stage for re-driving the global clock signal GCLK, a delay unit for delaying the timing of the global clock signal GCLK, a logical operating unit for performing a logical operation, a clock gating unit for serving the function of logic clock gating, or a multiplexer. For example, in the shown embodiment of  FIG. 1 , each of the low-voltage components  130   a  through  130   c  is a driving stage and could be implemented with a buffer. The low-voltage component  130   d  is an inverter, and the low-voltage component  130   e  is a delay unit, which could also be implemented with a buffer. The low-voltage component  130   f  is a clock gating unit and is typically implemented with a AND gate. In this embodiment, the clock distribution network  100  further comprises a control unit (not shown) for providing a gate control signal GCS to control the clock gating unit  130 f. While the second circuit unit  154  is not in use, the transmission of the global clock signal GCLK generated by the clock gating unit  130   f  to the second level shifter  144  could be stopped according to the gate control signal GCS. In other embodiments, the clock gating unit may be implemented with an OR gate. In practice, clock gating may be performed at any stage of the distribution network  130 .  
         [0019]     As mentioned in the foregoing illustration, the global clock generator  120  is used for generating a low swing global clock signal GCLK and the distribution network  130  is used for distributing the low swing global clock signal GCLK. Thus, the combination of the global clock generator  120  and the distribution network  130  is regarded as a global clock distribution network. In addition, the disclosed techniques of the present invention could be used in conjunction with other known or future techniques for even further power reductions.  
         [0020]     As is well known in the art, the level shifter could be integrated or embedded within other components (such as a logic gate, gating unit, buffer, etc.) in practical implementations.  
         [0021]      FIG. 2  is a simplified block diagram of a clock distribution network  200  according to a second embodiment of the present invention. As shown, a distribution network  230  composed of low-voltage components operating at the second operating voltage VCCL distributes a low swing global clock signal GCLK to local clock converting units  242  and  244 . The distribution network  230  is substantially the same as the distribution network  130  shown in  FIG. 1 , and a repeated description of its operation is therefore omitted here. In this embodiment, the first local clock converting unit  242  receives a low swing global clock signal GCLK 3  from the distribution network  230  and accordingly produces a full swing local clock signal LCLK 3  to a circuit unit  252  of a high-voltage area  250 . The second local clock converting unit  244  receives a low swing global clock signal GCLK 4  from the distribution network  230  and accordingly produces a full swing local clock signal LCLK 4  to a corresponding circuit unit  254  of the high-voltage area  250 . Similarly, the circuit units  252  and  254  operate at the first operating voltage VCCH while components of the distribution network  230  operate at the second operating voltage VCCL, which is lower than the first operating voltage VCCH.  
         [0022]     In this embodiment, the first local clock converting unit  242 , which may be integrated or embedded in a buffer, a delay unit, or a logic gate, is a level shifter for converting the low swing global clock signal GCLK 3  into the full swing third local clock signal LCLK 3 . The second local clock converting unit  244  acts as a level shifter for converting the low swing global clock signal GCLK 4  into the full swing fourth local clock signal LCLK 4  and also acts as a clock enabling unit for enabling or disabling the clock signal based on an enabling signal ES. Typically, the enabling signal ES is controlled by a control unit (not shown) so as to disable the clock signal and avoid driving the second circuit unit  254  when the second circuit unit  254  is not in use. The second local clock converting unit  244  could be a clock gating unit comprising a level shifter. For example, the second local clock converting unit  244  could be with the integration of an AND gate and a level shifter.  
         [0023]     Typically, employing a proper layout design could reduce the power consumption and chip area. As mentioned above, the distribution network composed of low-voltage components operating at the second voltage VCCL and the high-voltage area composed of high-voltage circuit units operating at the first voltage VCCH are generally on the same substrate. In other words, two different voltage supply lines are required in the same substrate.  
         [0024]      FIG. 3  shows a layout diagram of a circuit layout  300  according to an exemplary embodiment of the present invention. In the circuit layout  300 , high-voltage areas composed of high-voltage components are labeled as H while low-voltage areas composed of low-voltage components are labeled as L. As shown in  FIG. 3 , a dual-rail power mesh is employed for reducing the total length of voltage supply lines and signal lines. Due to the circuit layout  300 , any two neighboring voltage supply lines can share the same ground voltage line, and each of the high-voltage areas and low-voltage areas can be supplied with the required operating voltage in a shortest distance. As a result, the power consumption contributed on the clock distribution networks is further reduced.  
         [0025]     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.