Abstract:
An apparatus and method for an improved hardware implementation of a digital phase shifter which provides a simplified process for phase correction of digital signals and eliminates the use of a lookup ROM and complex digital Multipliers. The digital phase shifter operates by applying a phase correction to complex digital I/Q samples in separate stages, where each stage performs a phase rotation by an amount specified directly by the binary values of an integer input phase. In one aspect, an apparatus for applying a phase shift to a complex digital signal comprises a plurality of phase shift stages each having a phase shift value associated therewith, whereby each of the plurality of phase shift stages selectively applies the corresponding phase shift value to the complex digital signal.

Description:
BACKGROUND 
     1. Technical Field 
     The present application relates generally to a digital phase shifter and, more particularly, to an apparatus and method for providing an improved hardware implementation of a digital phase shifter. 
     2. Description of the Related Art 
     Modern communications systems often require the implementation of complex digital signal processing algorithms. One such algorithm is used in a conventional digital phase shifter (or mixer). A digital phase shifter is a key functional component in a large number of modern communication systems such as Direct Satellite System (DSS) receivers, digital cellular phones, satellite modems, and wireless local area network (LAN) modems. In particular, one important application of the digital phase shifter is in a digital phase-locked loop (PLL) which is used to remove phase and/or frequency error from a received signal. The use of digital PLLs simplify system design by obviating the need for external analog voltage-controlled oscillators and associated circuitry. 
     Referring now to FIG. 1, a block diagram illustrates a conventional digital communications demodulator having a digital phase shifter. The operation of the conventional digital phase shifter will be described in the context of the digital communications demodulator since this is one of its primary applications. In the system diagram of FIG. 1, a radio signal is received by an antenna  10  and then translated from a carrier frequency to baseband (or “zero-IF”) I and Q signals by a quadrature demodulator  12 . The baseband I and Q signals (i.e., complex signals) respectively refer to the “in-phase” and “quadrature phase” components of the radio signal. As shown in FIG. 2, the I and Q baseband signals form a complex vector “z” in a cartesian plane, where the tip of the vector “z” is equal to (I+jQ). In addition z, I and Q can be represented as a function of time using the functional notation z(t)=I(t)+jQ(t), where “j” is equal to the square root of negative 1, and represents a location in the Cartesian plane of (0,1). 
     Referring back to FIG. 1, the analog I and Q signals from the quadrature demodulator  12  are digitized by a first analog-to-digital (A/D) converter  14  and a second A/D converter  16 , respectively, and the digitized I and Q signals are sent to a digital demodulator  18 . The digital demodulator  18  includes a digital phase shifter (mixer)  20  which receives the digitized I and Q signals and mixes them with a locally generated phase reference φ(n) so as to apply a phase correction to the digitized samples. The phase is normally updated on a sample-by-sample basis so that the system can remove the phase error effects due to frequency offset or other dynamic phase fluctuations which may occur during transmission in the radio channel. The phase-corrected samples are then integrated by a matched-filter correlator  22  which produces an estimate of the transmitted information symbol. The transmitted information symbol is transformed into information bits (data) by a decoder  24 . 
     The phase reference φ(n) is typically provided by a carrier recovery module  26  which utilizes an algorithm that is driven by symbol decision-error directed computations provided by the decoder  24 . The carrier recovery module  26  determines the correct phase φ(n) to apply to the digital phase shifter  20  in order to cancel the phase error on the digitized I/Q samples that are received by the digital demodulator  18 . In particular, the digital phase shifter  20  rotates the vector z=I+jQ (which represents corresponding I/Q samples) by the phase reference angle φ(n). Mathematically, the rotation of the complex vector. “z” by phase “φ” is accomplished through multiplication with a complex exponential e jφ  (i.e., (I+jQ)*e jφ ). 
     Typically, conventional digital phase shifters used in high data rate systems such as DSS receivers or high speed wireless LANs are implemented in hardware. The conventional hardware-based digital phase shifter employs a read-only memory. (ROM) lookup table and a complex-multiply operation. Referring now to FIG. 3, a block diagram illustrates a conventional hardware realization for a conventional digital phase shifter, such as the one shown in FIG.  1 . In FIG. 3, I(n) and Q(n) represent discrete samples which are received by the digital phase shifter  20 , φ(n) represents the correction phase applied to the input I(n) and Q(n) samples, and Iout(n) and Qout(n) represent the phase-corrected samples output from the digital phase shifter  20 . The digital phase shifter  20  includes a complex multiply module  20   b  which multiplies the input samples I(n) and Q(n) (i.e., I(n)+jQ(n)) by the complex exponential e jφ . Specifically, since e jφ =cos(φ)+jsin(φ) by Euler&#39;s identity, the complex multiply module  20   b  performs a fast phase-rotation by first retrieving the values for cos(φ) and sin(φ) from a lookup ROM  20   a , and then performing one complex multiplication (i.e., [I(n)+jQ(n)]*[cos(φ)+jsin(φ)]) to form the phase-rotated output samples (i.e., Iout(n)=I(n) cos(φ)−Q(n) sin(φ) and Qout(n)=I(n) sin(φ)+Q(n) cos(φ)). 
     As shown, the complex multiplication requires four multiplications and two additions to generate the phase-corrected output samples. The complex multiplication process of the conventional digital phase shifter  20  requires the implementation of sophisticated digital multipliers. There is a need, therefore, for an improved hardware-based digital phase shifter which utilizess a simplified phase correction process and obviates the need for the complex digital multipliers and ROM of the conventional hardware-based digital phase shifter. 
     SUMMARY 
     The present application is directed to an apparatus and method for an improved hardware implementation of a digital phase shifter which provides a simplified process for phase correction of digital signals and eliminates the use of a lookup ROM and complex digital multipliers. The present digital phase shifter operates by applying a phase correction to digital samples in separate phase-shift stages, where each phase-shift stage performs a phase rotation by an amount specified directly by the binary values of an integer input phase. 
     In one aspect, an apparatus for applying a phase shift to a complex digital signal, comprises: a plurality of phase shift stages each having a phase shift value associated therewith, whereby each of said plurality of phase shift stages selectively applies the corresponding phase shift value to the complex digital signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram which illustrates a conventional digital communications demodulator using a conventional digital phase shifter; 
     FIG. 2 is a graphical illustration of an I/Q modulation signal in cartesian plane; 
     FIG. 3 is a block diagram of a conventional hardware digital phase shifter; 
     FIG. 4 is a diagram which illustrates a mapping of integer values to phase values in a complex plane in accordance with one aspect of the present invention; 
     FIG. 5 is a diagram which illustrates a mapping of binary phase digits to phase value in accordance with one aspect of the present invention; 
     FIG. 6 is a block/flow diagram which illustrates a binary phase shifter having a cascade of binary phase-shift stages for performing phase rotation in accordance with an embodiment of the present invention; 
     FIG. 7 is a block diagram which illustrates components of a binary phase-shift stage in accordance with an embodiment of the present invention; 
     FIG. 8 is a block/flow diagram which illustrates phase error compensation in accordance with one aspect of the present invention; 
     FIG. 9 is a block/flow diagram which illustrates a phase shifter in accordance with an embodiment of the present invention; and 
     FIG. 10 is a block/flow diagram which illustrates a digital phase shifter in accordance with another embodiment of the present invention. 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
     In general, the input phase in a hardware based digital signal processing system is normally represented as a 2&#39;s complement integer. A 2&#39;s complement system with “N” bits of precision can represent integer values ranging from −2 (N−1)  to 2 (N−1) −1. For example, assuming N=6, 64 integer values in the range from −32 to 31 can be represented. Assuming further (for N=6) that the integer values are used to represent phase values, the minimum integer value −32 can represent a phase value of −π (or π) radians, −16 can represent a phase value −π/2 radians, and 16 can represent a phase value of π/2. This mapping of integer values to phase values in a complex plane is shown in FIG.  4 . 
     Now assuming further that the 2&#39;s complement integer phase value is represented in binary form, then each binary digit can represent a phase value proportional to its numerical value. In particular, each bit of a binary number has a weight associated therewith. Since each bit can be only one of two values (i.e., 0 or 1) the weights ascend in powers of 2. For example, with N=6 (i.e, a binary number having the bit string b 5 , b 4 , b 3 , b 2 , b 1 , b 0 ) a binary weight of 32, 16, 8, 4, 2 and 1 is associated with bits b 5 , b 4 , b 3 , b 2 , b 1 , b 0 , respectively. Therefore, the binary weight 32 for bit b 5  can represent −π (or equivalently, π), the binary weight of 16 for bit b 4  can represent π/2, the binary weight of 8 for b 3  can represent π/4, the binary weight of 4 for b 2  can represent π/8, the binary weight of 2 for bit b 1  can represent π/16, and the binary weight of 1 for bit b 0  can represent π/32. This mapping of binary digits of the integer phase to phase values is shown in FIG.  5 . 
     Referring now to FIG. 6, a block diagram illustrates a binary phase shifter having a cascade of binary phase-shift stages for performing phase rotation in accordance with one embodiment of the present invention. In particular, FIG. 6 illustrates a preferred phase correction method (i.e., phase rotation) using a 6-bit integer phase value, whereby a phase shift is applied to a complex number (i.e., I/Q sample pair) by sending the complex number through a cascade of phase-shift stages S 1 -S 6 . Each phase-shift stage adds the appropriate phase weight for the corresponding binary digit of the integer phase. In particular, each phase-shift stage in the phase-rotation cascade applies a phase shift corresponding to the weight of the binary phase bit which controls it. If the binary integer phase bit is logic “0” for a corresponding phase-shift stage, the phase-shift stage will pass the complex number through with no phase rotation. On the other hand, if the respective binary integer phase bit is logic “1”, the phase-shift stage will add a phase shift corresponding to the phase weight of its binary digit to the complex number. It is to be appreciated that a 6-bit integer phase provides a phase quantization interval of 360°/64, or approximately 6°, which is adequate accuracy for use with a quadrature-phase shift keyed (QPSK) system. 
     Advantageously, the embodiment shown in FIG. 6 avoids the computation of a complex exponential (which, as stated above, is typically performed with a ROM lookup table) since it directly applies the phase rotation prescribed by the binary bits of the integer phase value. More importantly, it is possible to efficiently approximate the required phase rotation in each of the phase-shift stages using low complexity binary shifters, adders, and negates. Notwithstanding that these approximations typically add some phase and amplitude error to the resulting output, it is possible to achieve sufficiently accurate results to render viable the direct-phase rotation concept shown in FIG. 6 for use in many communications systems when distortion associated with imperfect rotation (i.e., approximation) is negligible as compared to other system degradations such as thermal noise. Referring now to FIG. 7, a diagram illustrates components of a binary phase-shift stage S shown in FIG.  6 . Each phase-shift stage includes a “phase-shift path” having a phase shift/scaling module  80  for applying the prescribed phase rotation and amplitude scaling factor to the input complex number (i.e., I/Q signals). The phase-shift stage also includes a “non-phase-shift path” having an amplitude compensation module  82  which provides the appropriate amplitude scaling factor when the I/Q signals are passed through the phase-shift stage S with no phase rotation. A 2:1 multiplexer  84  switches between the phase-shift and non-phase-shift paths in response to the corresponding binary phase bit of the integer phase. In particular, when the input binary phase digit is logic “1”, the multiplexer will allow the phase-shifted I/Q signals to pass (i.e., the phase shifter applies the prescribed phase rotation to the input complex number). When the input binary phase bit is logic “0”, the multiplexer will only pass the I/Q signals with the scaled amplitude (i.e., the phase-shifter passes the complex input through unchanged in phase, but with a scaled amplitude). 
     It is to be understood that the amplitude scaling factor that is applied in the amplitude compensation module  82  is similar to the prescribed amplitude scaling which occurs in the phase shift/scaling module  80  so that the amplitude gain of the I/Q signals in the phase-shift or non-phase shift path is as identical as possible. This is done to prevent unwanted phase-shift dependent amplitude modulation of the signal by the phase mixer. It is to be further understood that, although a fixed amplitude scale may be applied in each of the phase-shift stages in the phase shift-cascade, an amplitude scale factor can be applied with a separate scaling stage after the last phase-shift stage to provide the desired signal output level. 
     It is to be appreciated that not all of the phase-shift stages shown in FIG. 6 are required to have the structure shown in FIG.  7 . For instance, a phase rotation by “π” is equivalent to multiplication by −1. Consequently, the “π” phase shift can be implemented using a single negation structure (as explained in further detail below with reference to FIG.  9 ). It is to be further appreciated that, as stated above, in order to efficiently implement the phase-shift process in the other phase-shift stages, the prescribed phase shifts should be realized using low complexity binary shifters and adders. Consequently, the actual complex multiplication factors for the phase-shift/scale modules  80  in each of the phase-shift stages should closely approximate the prescribed phase shift. 
     Table 1 contains the preferred effective complex multiplication factors which can be used for 6-bit phase quantization. In Table 1, the “Rotation” column lists the prescribed phase rotation for each of the binary phase-shift stages shown in FIG.  6 . The “Complex Multiplier” column lists the approximate complex multiplication factors used to obtain the prescribed phase-shifts for the corresponding binary phase-shift stages. The “Amplitude” column lists the amplitude scaling factor that is realized in accordance with the corresponding complex multiplication factor and the “Phase Error” column lists the phase error that results from utilizing the corresponding complex multiplication factor. 
     
       
         
               
             
               
               
               
               
               
             
               
               
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 Binary Phase Shifter Phase and Amplitude Approximations 
               
             
          
           
               
                   
                   
                 Complex 
                   
                 Phase Error 
               
               
                   
                 Rotation 
                 Multiplier 
                 Amplitude 
                 (deg.) 
               
               
                   
                   
               
             
          
           
               
                   
                 π 
                 −1 + j0 
                 1.0 
                 0.0 
               
               
                   
                 π/2.0 
                   0 + j1 
                 1.0 
                 0.0 
               
               
                   
                 π/4.0 
                   1 + j1 
                 1.414 
                 0.0 
               
               
                   
                 π/8.0 
                   1 + j½ 
                 1.118 
                 +4.06 
               
               
                   
                 π/16.0 
                   1 + j¼ 
                 1.031 
                 +2.78 
               
               
                   
                 π/32.0 
                   1 + j⅛ 
                 1.008 
                 +1.50 
               
               
                   
                   
               
             
          
         
       
     
     In particular, the phase error refers to the difference between the prescribed phase rotation and the phase rotation that results from utilizing the approximated complex multiplication factor. It is to be understood that since (as stated above) the prescribed phase shifts in each of the phase-shift stages are preferably performed using low complexity binary shifts and additions, the complex multiplication factors in Table 1 are chosen such that they can be realized with low complexity binary adders and binary shifters, while at the same time providing a phase component which is close to the prescribed phase rotation. For example, for π/8.0 (i.e., 22.5°), the corresponding complex multiplication factor of 1+j.5 provides a phase shift of tan −1  (0.5/1)=26.57°, thereby resulting in a phase error of (26.56°)−(22.5°)=4.06°. 
     Furthermore, the amplitude scaling factors can be adjusted for the amplitude compensation module  82  in the non-phase rotated paths of the phase-shift stages such that the amplitude compensation module  82  can be realized using low complexity binary shifters and adders. For instance the amplitude scaling factor of 1.414 corresponding to the complex multiplication factor 1+j1 for the π/4 phase-shift stage is adjusted to an amplitude scaling factor of 1.5 which can be efficiently realized with one binary addition. It is to be understood that more accurate amplitude scaling factors can be realized at the expense of additional hardware. 
     In Table 2 below, the “Amplitude Comp.” column lists preferred amplitude error compensation values which can be implemented in the amplitude compensation module  82 . The “Amplitude Comp/Amplitude” column lists the corresponding ratio of the compensated amplitude scaling in the non-phase-rotated path to the amplitude scaling in the phase-rotated path for each of the phase-shift stages. As shown in Table 2, there is no amplitude compensation applied in the non-phase-rotated paths for the phase-shift stages π, π/2, π/16 and π/32. In particular, for π and π/2, no amplitude compensation is required in the non-phase-rotated path because the resulting amplitude scaling in the phase-rotated path is equal to 1 (as-shown in the “Amplitude” column). In addition, no amplitude compensation is required in the non-phase rotated paths for the phase-shift stages π/16 and π/32 since the corresponding amplitude scaling in the phase-rotated paths is virtually 1. 
     
       
         
               
             
               
               
               
               
               
             
               
               
               
               
               
             
           
               
                 TABLE 2 
               
             
             
               
                   
               
               
                 Amplitude Error Compensation 
               
             
          
           
               
                   
                 Complex 
                   
                 Amplitude 
                 Amplitude 
               
               
                 Rotation 
                 Multiplier 
                 Amplitude 
                 Comp. 
                 Comp/Amplitude 
               
               
                   
               
             
          
           
               
                 π 
                 −1 + j0 
                 1.0 
                 1.0 (none) 
                 1.000 
               
               
                 π/2.0 
                   0 + j1 
                 1.0 
                 1.0 (none) 
                 1.000 
               
               
                 π/4.0 
                   1 + j1 
                 1.414 
                 1.5 
                 1.060 
               
               
                 π/8.0 
                   1 + j½ 
                 1.118 
                 1.125 
                 1.006 
               
               
                 π/16.0 
                   1 + j¼ 
                 1.031 
                 1.0 (none) 
                 0.970 
               
               
                 π/32.0 
                   1 + j⅛ 
                 1.008 
                 1.0 (none) 
                 0.992 
               
               
                   
               
             
          
         
       
     
     It is to be appreciated that since the phase error at any given phase-shift stage is a known function of the input phase, phase error compensation can also be designed into the system. In particular, referring back to Table 1, the only phase error incurred due to the preferred complex multiplication factors is in the lower 3 bits of the 6-bit binary integer phase. In other words, only the preferred complex multiplication factors which are approximated for the π/8, π/16 and π/32 phase-shift stages result in any phase error. Consequently, all phase error combinations may be found by examining the lower three bits of the integer phase value. 
     This concept is illustrated in Table 3 below, which lists the resulting phase error for all combinations of the lower three bits of the binary integer phase. For instance, notwithstanding the logic state of the upper three bits of the preferred six bit integer phase, when the lower three bits are “1 0 1”, the resulting phase error is 5.57° (i.e. 4.06°+1.50°). Indeed, the greatest phase error of +8.34° occurs when all three low order bits are logic “1” (i.e., when all three lower bits select phase rotation for the corresponding phase-shift stage). 
     
       
         
               
             
               
               
               
               
               
             
               
               
               
               
               
             
           
               
                 TABLE 3 
               
             
             
               
                   
               
               
                 Phase Error Compensation 
               
             
          
           
               
                   
                   
                 Phase 
                 Phase 
                 Compensated 
               
               
                   
                 b2 b1 b0 
                 Error 
                 Compensation 
                 Phase Error 
               
               
                   
                   
               
             
          
           
               
                   
                 1 1 1 
                 8.35 
                 −7.125 
                 1.23 
               
               
                   
                 1 1 0 
                 6.85 
                 −7.125 
                 −2.74 
               
               
                   
                 1 0 1 
                 5.57 
                 −7.125 
                 −1.56 
               
               
                   
                 1 0 0 
                 4.07 
                 −7.125 
                 −3.06 
               
               
                   
                 0 1 1 
                 4.29 
                 −7.125 
                 −2.84 
               
               
                   
                 0 1 0 
                 2.79 
                 0.0 
                 2.79 
               
               
                   
                 0 0 1 
                 1.50 
                 0.0 
                 1.50 
               
               
                   
                 0 0 0 
                 0.0  
                 0.0 
                 0.0 
               
               
                   
                   
               
             
          
         
       
     
     It is to be appreciated that the phase error in the system as a result of the complex multiplication factors for the lower three bits of the input phase can be reduced by initially compensating the input phase value. In particular, since a rotation by 1+j⅛ is equal to +7.125 degrees, the maximum error of 8.35° can be compensated by subtracting one from the input phase value. Referring to Table 3, a comparison is shown between the “phase error” associated with the various low-order phase bit patterns using no phase compensation and the corresponding “compensated phase error” using the optimal “phase compensation” for all possible error patterns of input phase. For the lower 3 bit combinations having decimal equivalent values of 0, 1 and 2, the phase error is negligible and is not compensated. 
     As shown in Table 3, the “compensated phase error” values range from −2.84° to +3.06° with a mean error of −0.3°. Since the phase quantization is equal to 5.625° (i.e., 360°/64) when the preferred 6-bit integer phase is used, the range of the compensated phase error values is only slightly larger than the phase error that results from phase quantization alone, which is −2.8125° to +2.8125°. 
     Referring now to FIG. 8, a block/flow diagram illustrates a method for phase error compensation in accordance with one aspect of the present invention. A phase error compensation module  92  receives the binary input phase and determines if the lower 3 bits have a value that is greater than or equal to 3. If so, the phase error compensation module  92  will subtract a value of “1” from the binary input phase (via a phase compensation algorithm) to generate a compensated phase input. The compensated phase will then be applied to the phase shifter  90  (which contains the cascade of binary phase-shift stages shown in FIG.  6 ). In this manner, as illustrated in Table 3 above, a phase rotation of −7.125° will initially be applied to the integer phase (when the lower three bits have decimal equivalents greater than or equal to 3) in order to compensate for the phase error associated with the lower three bits of the binary integer phase that results from the approximated complex multiplier values. 
     Referring now to FIG. 9, a block/flow diagram illustrates an embodiment of the phase shifter having phase shift and gain compensation in each phase-shift stage. As explained above with reference to FIG. 8, a six-bit input phase is first compensated by subtracting one from its value if the low three phase bits of the 6-bit binary integer phase have a value greater than or equal to three. In this embodiment, the compensated phase value drives a five-stage binary phase-shifter cascade. The first stage S 1  applies a multiplication of (4+j1) in the rotated path and (4+j0) in the non-rotated path for phase bit b 1 . The second stage S 2  applies a multiplication of (1+j⅛) in the rotated path, and (1+j0) in the non-rotated path for phase bit b 0 . The third stage S 3  applies a multiplication of (1+j0.5) in the rotated path, and (0.125+j0) in the non-rotated path for phase bit b 2 . The fourth stage S 4  applies a multiplication of (1+j1) in the rotated path and (1.5+j0) in the non-rotated path for phase bit b 3 . The fifth stage S 5  handles rotation by π and π/2 efficiently using one conditional negate based on the values of phase bits b 4  and b 5 . The final output multiplexer in stage five S 5  reverses the order of the I/Q data if bit phase b 4  (corresponding to rotation by π/2) is 1. 
     As shown in FIG. 9, each phase-shift stage of the phase shifter  90  routes either the phase-shifted or non-phase-shifted I and Q data through a 2:1 multiplexer  84  which is controlled by the appropriate binary bit from the integer phase. Each multiplexer selects either the two upper signals or the two lower signals to be output. The logic “1” or “0” which is placed next to the signal lines represent the signal lines which are selected for output when the input phase control bit is equal to that value. The final outputs of the phase shifter  90  may be scaled and rounded in module  100  as may be required for numerical precision for a particular hardware system design. A summary of the phase-shifter path multipliers for the implementation in FIG. 9 is given in Table 4 below. 
     
       
         
               
             
               
               
               
               
             
           
               
                 TABLE 4 
               
             
             
               
                   
               
               
                 Phase Shifter Multipliers 
               
             
          
           
               
                   
                   
                 Rotated Path 
                 Non-Rotated 
               
               
                 Phase Bit 
                 Rotation 
                 Multiplier 
                 Path Multiplier 
               
               
                   
               
               
                 b5 
                 π 
                 −1 + j0 
                    1 + j0 
               
               
                 b4 
                 π/2 
                   0 + j1 
                    1 + j0 
               
               
                 b3 
                 π/4 
                   1 + j1 
                  1.5 + j0 
               
               
                 b2 
                 π/8 
                   1 + j0.5 
                 1.125 + j0 
               
               
                 b1 
                 π/16 
                   4 + J1 
                    4 + j0 
               
               
                 b0 
                 π/32 
                   1 + j0.125 
                    1 + j0 
               
               
                   
               
             
          
         
       
     
     As shown in FIG.  9  and Table 3 above, a complex multiplier of 4+j is used for bit b 1  in FIG. 9 whereas Table 1 shows the multiplier for b 1  being equal to 1+j0.25. The complex multiplier of 4+j1 is used in the first stage of FIG. 9 to increase the magnitude of the input samples by a factor of 4, or two binary bits. This magnitude scaling is done to provide increased precision in the computations of the integer implementation of the phase shifter. 
     It is to be understood that the ordering and level scaling of the binary-shift stages has no impact on the input/output transfer function outside of an (ideally) constant magnitude scale. In an integer implementation such as shown in FIG. 9, it may be advantageous to order the binary phase-shift stages in a particular sequence to exploit optimal numerical precision and/or output level scaling. For example, in FIG. 9, bit b 1  is processed before bit b 0 . This ordering of phase shift stages is optimized to maintain adequate numerical precision for an integer implementation while providing a desired output signal level. 
     Referring now to FIG. 10, a block diagram illustrates a phase shifter having generalized phase and amplitude compensation in accordance with another embodiment of the present invention. In particular, in the embodiment of FIG. 10, the phase error compensation is generalized for phase shifters that are designed for higher levels of phase precision. In this system, an input phase is sent through compensation function f 1 (p)  92  which produces a compensated output phase to drive the primary phase shifter  90  (similar to the embodiment shown in FIG.  8 ). The input phase is also sent through compensation function f 2 (p)  102 , which computes a correction phase value for an auxiliary phase shifter  106  which is designed to reduce the residual phase error that results from correction function f 1 (p) in conjunction with the primary phase shifter  90 . For amplitude correction, the phase is sent through function f 3 (p)  104 , which computes an amplitude correction multiplier value as a function of input phase. The multiplier is applied to an amplitude scale module  108  which scales the magnitude of the I/Q samples coming from the-phase shift network(s)  90  and  106  to produce an output value with the desired amplitude error tolerance. In other words, the amplitude scaling module  108  may optionally be implemented to compensate for the aggregate amplitude errors induced by the entire sequence of binary phase-shift stages in the primary phase shifter  90  and the auxiliary phase shifter  106  similar to the manner by which the phase error compensation blocks are designed to compensate for the aggregate phase error through the entire sequence of binary shifters. The output may be scaled and rounded in module  100 , which (as stated above) may be required for numerical precision for the given hardware system design. 
     It is to be understood that the +−3° error and the small amplitude error that results with the system shown in FIG. 8 (i.e., where f 2 (p)=0 and f 3 (p)=1.0) is sufficiently accurate for QPSK systems. For modulation systems employing higher order constellations, or other applications where higher accuracy is required, the generalized compensation network shown in FIG. 10 may be implemented. 
     Advantageously, the present digital phase shifter implementation provides a reduction of hardware resources, which results in a savings in both cost and power consumption for hardware implementation of, e.g., a digital PLL, or any hardware-based digital signal processing algorithm utilizing phase-shifting functionality. Indeed, the present invention has application in a wide range of digital communications systems such as satellite modems, high-speed wireless networking modems, and any other hardware design which requires a complex phase shift, such as a tuneable digital local oscillator (LO) or complex equalizer. The present phase-shift process can be applied to enhance the instruction set of a programmable digital signal processor (DSP) since it allows the implementation of a single instruction complex mixer which performs the operations described above. Indeed, the conventional DSP would be required to compute a complex exponential followed by a full complex multiply operation to achieve the functionality which could be achieved in one instruction using the phase shifting methods described herein. 
     Although the illustrative embodiments of the present invention have been described herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be affected therein by one skilled in the art without departing from the true scope or spirit of the invention. All such changes and modifications are intended to be included within the scope of the invention as defined by the appended claims.