Abstract:
In accordance with the teachings described herein, systems and methods are provided for a time-interleaved pipeline analog to digital converter. An example pipeline analog to digital converter may include passive sampling circuits and a multiplying digital to analog converter circuit. A first passive sampling circuit includes an input terminal coupled to an analog input signal, and outputs a first sample voltage that is responsive to the analog input signal. A second passive sampling circuit includes an input terminal coupled to the analog input signal, and outputs a second sample voltage that is responsive to the analog input signal. The first and second passive sampling circuits are clocked such that the first sample voltage and the second sample voltage are time-interleaved. A multiplying analog to digital converter (MDAC) circuit receives the time-interleaved first and second sample voltages from the first and second passive sampling circuits and processes the time-interleaved first and second sample voltages to generate a residue output voltage.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority from U.S. Provisional Patent Application No. 61/345,444, filed on May 17, 2010, and entitled “New Low Power High Speed Pipeline ADC,” the entirety of which is incorporated herein by reference. 
    
    
     FIELD 
     The technology described in this patent application relates generally to pipelined analog to digital converters. More particularly, systems and methods are disclosed for a low power high speed pipeline analog to digital converter. 
     BACKGROUND 
     High speed analog to digital converters (ADC) are typically used in electronics such as wireless receivers, cameras, modems, HDTV, and ultrasound systems. These electronics utilize sampling rates ranging between 40 MHz and 100 MHz for analog to digital conversion. At these frequencies, pipelined ADCs may provide low power consumption, low noise, and high speed. Pipeline ADCs are often used in applications where dynamic performance is of importance. 
     An active sample and hold amplifier is used in many configurations because it provides the ADC with a settled input voltage, allowing the subsequent circuit stages to capture the high frequency input signals. In order to achieve low power consumption and low noise while keeping performance high, some configurations remove the active sample and hold amplifier. The active sample and hold amplifier is not a necessity in ADCs and may also add noise and distortion to the analog input signal. In addition, an active sample and hold amplifier may consume large amounts of power and area on the die. 
     Aperture error in a typical ADC is the error caused by variation in the time at which the ADC transitions from sample mode to hold mode, usually resulting from noise on the clock or input signal. In a pipeline ADC architecture, sampling a continuous time signal, rather than a held signal in an active sample and hold device, may present additional aperture error. With reference to the pipeline ADC system  100  in  FIG. 1A , this error results from a bandwidth mismatch of the sub-ADC  102  and the multiplying digital to analog converter (MDAC)  104 . The aperture error in a pipeline ADC without active sample and hold can be demonstrated by the following equations. 
     Assuming a full-scale sine wave at the input:
 
 V   in   =V   REF ×sin(2π f   in   t )
 
     The maximum slope of the signal is represented by: 
     
       
         
           
             
               
                 
                   
                     ⅆ 
                     
                       V 
                       in 
                     
                   
                   
                     ⅆ 
                     t 
                   
                 
                  
               
               Max 
             
             = 
             
               
                 V 
                 REF 
               
               × 
               2 
               ⁢ 
               
                   
               
               ⁢ 
               π 
               ⁢ 
               
                   
               
               ⁢ 
               
                 f 
                 in 
               
             
           
         
       
     
     If the time constant mismatch between the sub-ADC  102  and the MDAC  104  is Δτ=ε×τ, then the maximum aperture error may be represented by:
 
 V   error | Max   =V   REF ×2π f   in ×ε×τ
 
     For the 2.5 bit first stage, the error should be smaller than the correction range, that is V error | Max &lt;⅛V REF . In addition, the maximum input frequency f in  of the input sampling networks of sub-ADC  102  and MDAC  104  should be less than or equal to 
               0.1   τ     .         
The time constant error may then be represented by:
 
     
       
         
           
             
               
                 
                   ɛ 
                    
                 
                 Max 
               
               &lt; 
               
                 1 
                 
                   2 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   π 
                   × 
                   0.1 
                   × 
                   8 
                 
               
             
             = 
             0.2 
           
         
       
     
     Because the aperture error grows rapidly with respect to the input frequency,  FIG. 1A  utilizes a sampling switch  106 . The sampling switch  106  is shared by both the sub-ADC  102  and the MDAC  104 . Because the switch is shared, the aperture error can be reduced by matching the time constant of the sampling networks with the following equations: 
     
       
         
           
             
               
                 
                   
                     2 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       C 
                       1 
                     
                   
                   + 
                   
                     C 
                     
                       p 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                   
                 
                 
                   
                     2 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       C 
                       2 
                     
                   
                   + 
                   
                     C 
                     
                       p 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       2 
                     
                   
                 
               
               = 
               
                 
                   1 
                   / 
                   
                     g 
                     m 
                   
                 
                 
                   R 
                   sm 
                 
               
             
             ; 
           
         
       
       
         
           
             
               
                 R 
                 sm 
               
               = 
               
                 1 
                 
                   
                     u 
                     n 
                   
                   ⁢ 
                   
                     C 
                     ox 
                   
                   ⁢ 
                   
                     W 
                     L 
                   
                   ⁢ 
                   
                     
                       ( 
                       
                         
                           V 
                           gs 
                         
                         - 
                         
                           V 
                           TH 
                         
                       
                       ) 
                     
                     sm 
                   
                 
               
             
             ; 
             
                 
             
             ⁢ 
             and 
           
         
       
       
         
           
             
               g 
               m 
             
             = 
             
               
                 u 
                 n 
               
               ⁢ 
               
                 C 
                 ox 
               
               ⁢ 
               
                 W 
                 L 
               
               ⁢ 
               
                 
                   
                     ( 
                     
                       
                         V 
                         gs 
                       
                       - 
                       
                         V 
                         TH 
                       
                     
                     ) 
                   
                   preamp 
                 
                 . 
               
             
           
         
       
     
     In the above equations, g m  is the transconductance of the preamplifier  108 , R sm  is the on-resistance of the MDAC switch  110 , and C p1  and C p2  are the total parasitic capacitance at nodes T 1   112  and T 2   114 . To optimize the time constant mismatch, the ratio of 1/g m  to R sm  should be set to 1. This approach, however, provides for increased power consumption by the preamplifiers  108 . 
     As shown in  FIG. 1B , the time window for T LATCH  reduces the net amplification duration of MDAC  116 . This scenario requires the operational transconductance amplifier of the MDAC  116  to consume twice the amount of power as compared to a traditional structure. Because the sampling duration is made shorter than the normal 50% duty cycle, the preamplifiers  108  must also be faster to complete their operations during T LATCH . The faster operation causes the preamplifiers to consume more power. 
     A typical approach to reducing the power consumption of the pipeline ADC circuit of  FIG. 1A  is shown in  FIG. 2A . Compared with the system  100  in  FIG. 1A , the pipeline ADC system  200  of  FIG. 2A  provides each flash comparator  202  and the MDAC  204  with their own input sampling switches  206   a  and  206   b , respectively. Using separate sampling switches provides for no kickback from the latches  208  to the MDAC  204 . Accordingly, each flash comparator  202  does not require a preamplifier and can only include a latch  208 . Because there are no preamplifiers in the flash comparators  202 , the sampling duration is shortened as compared to the typical 50% duty cycle, as shown in  FIG. 2B . In contrast to  FIG. 1A , however, there are no preamplifiers to consume power, so there is no power tradeoff at the MDAC  204 . 
     Even though there is reduced power consumption in the system  200  of  FIG. 2A  as compared to the system  100  in  FIG. 1A , the lack of preamplifiers in the flash comparators  202  creates a larger than normal input-inferred offset in each of the flash comparators  202 . The large offset may occupy a significant portion of the digital correction range and leave only a small window for the aperture error correction. 
     SUMMARY 
     In accordance with the teachings described herein, systems and methods are provided for a time-interleaved pipeline analog to digital converter. An example of a pipeline analog to digital converter may include passive sampling circuits and a multiplying digital to analog converter circuit. A first passive sampling circuit includes an input terminal coupled to an analog input signal, and outputs a first sample voltage that is responsive to the analog input signal. A second passive sampling circuit includes an input terminal coupled to the analog input signal, and outputs a second sample voltage that is responsive to the analog input signal. The first and second passive sampling circuits are clocked such that the first sample voltage and the second sample voltage are time-interleaved. A multiplying analog to digital converter (MDAC) circuit receives the time-interleaved first and second sample voltages from the first and second passive sampling circuits and processes the time-interleaved first and second sample voltages to generate a residue output voltage. 
     The first and second passive sampling circuits may each further include a flash analog to digital converter (ADC) circuit coupled to a first decoder. The MDAC may further comprise a first hold capacitor coupled to the output of the first passive sampling circuit and a second hold capacitor coupled to the output of the second passive sampling circuit. The MDAC input is coupled to the output terminal of the first and second hold capacitors. 
     The first passive sampling circuit receives the analog input voltage when a first sample clock signal is in a logic high state and the second passive sampling circuit receives the analog input voltage when a second sample clock signal is in a logic high state. The MDAC receives the first sample voltage when a first hold clock signal is in a logic high state and the MDAC receives the second sample voltage when a second hold clock signal is in a logic high state. 
     The first sample clock signal is in a logic high state at every other logic high state of the first input clock signal and the second sample clock signal is in a logic high state at every other logic high state of the first input clock signal, such that at each logic high state of the first input clock signal, only one of the first or second sample clock signals is in a logic high state. 
     The first hold clock signal is in a logic high state at every other logic high state of the second input clock signal and the second hold clock signal is in a logic high state at every other logic high state of the second input clock signal, such that at each logic high state of the second input clock signal, only one of the first or second hold clock signals is in a logic high state. 
     An example of a method for processing an analog input signal in a pipelined converter includes receiving the analog input signal at a first passive sampling circuit and outputting a first sample voltage that is responsive to the analog input signal; receiving the analog input signal at a second passive sampling circuit and outputting a second sample voltage that is responsive to the analog input signal; time-interleaving the first and second sample voltages; and receiving, at a multiplying analog to digital converter (MDAC), the time-interleaved first and second sample voltage from the first and second passive sampling circuits and processing the time-interleaved first and second sample voltages to generate a residue output voltage. 
     A second example of a method for processing an analog signal input in a pipelined converter, includes receiving, at a first passive sampling circuit, an input voltage when a first sample clock signal is in a logic high state, the first sample clock signal being in a logic high state at every other logic high state of a first input clock signal; receiving, at a second passive sampling circuit, an input voltage when a second sample clock signal is in a logic high state, the second sample clock signal being in a logic high state at every other logic high state of the first input clock signal, such that at each high logic state of the first input clock signal, only one of the first or second sample clock signals is in a logic high state; outputting a sampled voltage, by the first passive sampling circuit, to a multiplying digital to analog converter (MDAC) when a first hold clock signal is in a logic high state, the first hold clock signal being in a logic high state at every other logic high state of a second input clock signal; and outputting a sampled voltage, by the second passive sampling circuit, to the MDAC when a second hold clock signal is in a logic high state, the second hold clock signal being in a logic high state at every other logic high state of the second input clock signal, such that at each high logic state of the second input clock signal, only one of the first or second hold clock signals is in a logic high state. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A and 2A  illustrate a typical configuration for a pipeline ADC system. 
         FIGS. 1B and 2B  are timing diagrams corresponding to  FIGS. 1A and 2A , respectively. 
         FIG. 3  is an example of a time-interleaved pipeline ADC system with high speed capabilities and low power consumption. 
         FIGS. 4A and 4B  are a circuit diagram for a time-interleaved pipeline ADC system. 
         FIG. 5  illustrates clock signals for a time-interleaved pipeline ADC system. 
         FIG. 6  is a flow diagram illustrating a method of time-interleaving sub-analog-to-digital converters in a pipeline ADC system. 
         FIG. 7  is a flow diagram illustrating operation of time-interleaving sub-analog-to-digital converters in a pipeline ADC system. 
         FIG. 8  is an example of a system that may utilize a time-interleaved pipeline ADC. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 3  is a block diagram of an example of a time-interleaved pipeline ADC system  300  with high speed capabilities and low power consumption. The pipeline ADC system  300  includes Sub-ADC 1   302 , Sub-ADC 2   304 , a time-interleaved module  306 , and a MDAC  308 . In operation, the pipeline ADC system receives an analog input signal V IN  at both Sub-ADC 1   302  and Sub-ADC 2   304 . The Sub-ADCs  302  and  304  perform sampling operations on the analog input signal V IN  and generate a processed signal. The time-interleaved module  306  controls the timing of the Sub-ADCs so that they operate in a time-interleaved manner. The time-interleaved module may be implemented, for example, in a microprocessor or a clocking circuit. The Sub-ADCs  302  and  304  operate in a time-interleaved manner so that the MDAC  308  receives the processed signals output from each Sub-ADC in an alternating fashion. 
     The alternating, time-interleaved, pipeline ADC system  300  allows the Sub-ADCs  302  and  304  extra time to complete the sampling operations. Because of this extra time, the sub-ADCs  302  and  304  run with reduced current, and thus, consume less power. The extra time also allows the sub-ADCS  302  and  304  to more accurately capture and process the entire signal and negates the effects of any delay caused by the preamplifiers to the signal processing operation. 
     The sub-ADCs  302  and  304  and the MDAC  308  each utilize a separate sampling switch and capacitors. This allows for the aperture to be greatly reduced because the time constants of each circuit may be matched with the following formula: 
     
       
         
           
             
               
                 
                   2 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     C 
                     1 
                   
                 
                 + 
                 
                   C 
                   
                     p 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                 
               
               
                 
                   2 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     C 
                     2 
                   
                 
                 + 
                 
                   C 
                   
                     p 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                   
                 
               
             
             = 
             
               
                 1 
                 / 
                 
                   g 
                   m 
                 
               
               
                 R 
                 sm 
               
             
           
         
       
     
     Because the time constants may be matched and the time for the flash comparators to sample the input voltage is lengthened, the time-interleaved pipeline ADC system  300  can operate with low power consumption and nominal offset. 
       FIGS. 4A and 4B  provide a more detailed example of the time-interleaved pipeline ADC system of  FIG. 3 . The pipeline ADC system  400  of  FIGS. 4A-B  includes Sub-ADC 1   402 , Sub-ADC 2   404 , flash comparators  406  and  408 , decoders  410 , and a MDAC  412 . In operation, the pipeline ADC system  400  processes an input analog voltage V IN  based on the clock signals illustrated in  FIG. 5 . Therefore, the operation of the pipeline ADC system  400  will be described with reference to  FIGS. 4A ,  4 B, and  5 . 
     The input analog voltage V IN  is received at both Sub-ADC 1   402  and Sub-ADC 2   404 . When clock signal CKS 1  goes high  502  ( FIG. 5 ), switches SW 0 -SW 4  close, allowing the input analog voltage V IN  to be received at the flash comparators  406  in Sub-ADC 1   402 . As shown in  FIGS. 4A-B , Sub-ADCs  402  and  404  may comprise a plurality of flash comparators  406  and  408 , depending on the bit size being sampled. The input analog voltage V IN  is subsequently sampled across capacitors C 3  before entering the preamplifier  414  and latch  416  for digitization. The digitized output voltage from the latch in Sub-ADC 1   402  is not received by the MDAC  412 , however, until clock signal CKH 1  goes high  504 . 
     As shown in  FIG. 5 , clock signal CKH 1  does not go high until a time period T S  had elapsed. The time period T S  represents the time interval for the preamplifier  414  and latch  416  to process the analog input voltage V IN . Therefore, the digitized output voltage is output from the latch prior to clock signal CKH 1  transitioning to a high state. This digitized output voltage may be output to another stage of the pipeline ADC, such as a digital error correction stage, so that the digital output may be utilized in an electronic device. 
     When clock signal CKH 1  goes high  504 , switches SW 5  and SW 7  close and switch SW 6  opens, allowing the digitized output voltage to also be received at the MDAC  412  after passing through hold capacitor C 1 . 
     Because the pipeline ADC system  400  operates the Sub-ADCs  402  and  404  in a time-interleaved manner, Sub-ADC 1   402  and Sub-ADC 2   404  output a digitized voltage at alternating intervals. As illustrated in  FIG. 5 , each Sub-ADC  402  and  404  outputs a digitized voltage during a T S  time period. Following the time period TS, the Sub-ADCs  402  and  404  process the digitized signal in the MDAC  412 . 
     Sub-ADC 2   404  operates in a similar manner as Sub-ADC 1   402 . As shown in  FIG. 5 , when Sub-ADC 1   402  is performing its digitization of the input analog signal V IN  during the time period T S , clock signal CKH 2   506  goes high. At this moment, any output from the Sub-ADC 2   404  may be input to the MDAC  412  and clock signal CKS 2   508  is low so that the input analog voltage V IN  is not input to the flash comparators  498 . Following the high state of CKH 2   506 , clock signal CKS 2   508  goes high. At this moment, switches SW 8 - 12  close, allowing the input analog voltage V IN  to be received at the flash comparators  408  in Sub-ADC 2   404 . The input analog voltage V IN  is subsequently sampled across capacitors C 4  before entering the preamplifier  414   b  and latch  416   b  for digitization. The digitized output voltage from the latch in Sub-ADC 2   404  is not received by the MDAC  412 , however, until clock signal CKH 2  goes high  510 . 
     As shown in  FIG. 5 , clock signal CKH 2  does not go high at  510  until a second time period (2*T S ) has elapsed. Just as in Sub-ADC 1   402 , a digitized output voltage in Sub-ADC 2   404  is output from the latch  410   b  prior to clock signal CKH 2  transitioning to a high state  510 . When clock signal CKH 2  goes high  510 , switches SW 13  and SW 15  close and switch SW 14  opens, allowing the digitized output voltage to be received at the MDAC  412  after passing through hold capacitor C 2 . 
     The MDAC  412  processes the digitized output voltage during each hold interval of the system—when clock signal CKH 1  or CKH 2  are in a high state. The MDAC  112  then outputs analog output voltage V OUT , as illustrated in  FIG. 5 . The output analog voltage, or residue, V OUT  may subsequently be received by a next stage configured to process the residue voltage. This time-interleaved process may repeat as long as necessary to process each subsequent sample. 
     Moving the preamp and latch time from T LATCH  in  FIG. 2B  to T S  in  FIG. 5  is an advantage of passive time-interleaved sampling. T S  may be much longer than T LATCH , allowing for much less power to be consumed by the preamp and latch. In addition, because the preamp and latch time is moved, no T LATCH  is needed and the net amplification duration of the MDAC may be extended to near half of T S , allowing for less power consumption by the MDAC. 
       FIG. 6  is a flow diagram illustrating an example of a method of time-interleaving sub-analog-to-digital converters in a pipeline ADC system. At  602  a first sub-ADC receives an input analog voltage signal and converts the input analog voltage signal to an output digital voltage signal. Similarly, at  604 , a second sub-ADC receives the input analog voltage signal and converts the input analog voltage signal to a second output digital voltage signal. At  606 , the sub-ADCs are operated in a time-interleaved, or ping-pong, fashion. The time-interleaved operation of the sub-ADCs produces the output digital voltage signals at alternating time intervals. Therefore, at step  608 , the output digital voltage signals are received, for example by a MDAC, in a time-interleaved fashion. 
       FIG. 7  is a flow diagram illustrating the operation of clock signals for a method of time-interleaving sub-analog-to-digital converters in a pipeline ADC system, such as the method shown in  FIG. 6 . At  702 , clock signal CK 1  is high and clock signal CK 2  is low (see, e.g., CK 1  and CK 2  in  FIGS. 4 and 5 ). For this condition, at  704 , clock signal CKS 1  goes high and an input analog voltage is sampled in sub-ADC 1 . After  704 , the time period T S  begins. During this time period, the input analog voltage signal is digitized. Also during this time period, at  706 , clock signal CK 1  goes low and clock signal CK 2  goes high. During this condition, clock signal CKH 2  also goes high and an output digitized voltage from sub-ADC 2  is held at  708 . At  710 , clock signal CK 1  returns to a high state and clock signal CK 2  returns to a low state. At  712 , clock signal CKS 2  goes high and the input analog voltage is sampled at sub-ADC 2 . Following  712  is also the end of the T S  time period. At  714 , clock signal CK 1  enters the low state and clock signal CK 2  enters the high state. Subsequently, at  716 , clock signal CKH 2  goes high and the digitized output voltage produced during the time period T S  is held for sub-ADC 1 . The process then returns at  702  and processes the next sample bits for the system. 
       FIG. 8  illustrates an example of a system that may utilize a time-interleaved pipeline ADC. As shown in  FIG. 8 , a system utilizing a time-interleaved pipeline ADC may include a signal processing and/or control circuit  852 , such as a microprocessor or DSP, a plurality of input/output devices  856 ,  858 ,  860 ,  862 , a memory  866 , a mass data storage  864 , and/or wireless communication circuitry  851 ,  868 . In different embodiments, the system illustrated in  FIG. 8  may be included (in whole or in part) in a cellular telephone, a computer, a DVD player, a television, a set-top box, a vehicle, a digital media player and/or other suitable systems or devices. 
     This written description uses examples to disclose the invention, include the best mode, and also to enable a person skilled in the art to make and use the invention. The patentable scope of the invention may include other examples that occur to those skilled in the art. For instance, although the example time-interleaved pipeline ADC systems described herein include two Sub-ADCs, other examples may include more than two Sub-ADCs.