Abstract:
A process for the manufacture of power-MOS semiconductor devices achieves high cell density by the use of self-aligning techniques and photographic exposure equipment of the stepper type. The process calls for definition and formation of the source by a complementary spacer technique and metallization of the source and gate contact areas by silicides after formation of spacers on the gate wall.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a process for the manufacture of power-MOS semiconductor devices with high density of the elementary MOS cells. 
     2. Description of the Prior Art 
     In the manufacture of power-MOS devices there are commonly used techniques aimed at the embodiment of high cell density typical of Large Scale Integration (LSI) technology which allow the integration of numerous cells of the device and structures with ever smaller characteristic dimensions, i.e. with smaller silicon areas, or with better performances for a given silicon area used. The present density of power-MOS devices is on the order of 2-3 million elementary cells per square inch, to which corresponds for the elementary cell a typical &#34;Xpitch&#34; dimension of approximately 17 μm where Xpitch stands for (see FIG. 1) the sum of the side dimension Xd (approximately 7 μm) of the gate electrode, and of the dimension Xc (approximately 10 μm) of the opening in the polycrystalline silicon layer. 
     The minimum dimensions of the cell obtained in accordance with conventional processes are conditioned by the resolving power and the alignment limits of the photographic exposure system used, as well as the tolerances imposed by the various steps of the production process. More precisely, the minimal dimensions Xc are determined by the requirement to effect three successive alignments inside the polycrystalline silicon, and by the technological limit associated with the smallest possible openings. Using conventional photographic exposure equipment with projection the minimal dimensions of Xc are approximately 8 μm. 
     The smallest side dimensions of the gate (Xd) are linked to the requirement of allowing sufficiently deep diffusion of the body dopant to prevent the formation of short circuits due to the so-called spikes of aluminum which occur in conventional metallizations. Said minimal dimensions of Xd are approximately 6-7 μm regardless of the technique used. 
     SUMMARY OF THE INVENTION 
     The object of the present invention is to considerably reduce the minimal dimensions of the elementary cells (Xpitch) of a power-MOS device so as to increase the density of integration of the corresponding devices and at the same time simplify the manufacturing process. 
     The process for manufacture of power-MOS semiconductor devices in accordance with the present invention comprises the following steps: 
     epitaxial growth on a silicon substrate having a certain conductivity type of at least one layer of silicon of the same conductivity type; 
     gate oxidation over the entire substrate; 
     deposition of a layer of polycrystalline silicon on a face of the substrate; 
     opening by photoengraving of a gate window in the layer of polycrystalline silicon for definition of the gate polysilicon; 
     implantation and diffusion of a dopant into the aforesaid gate window for formation of the body; 
     implantation and diffusion of a dopant in the body for formation of the source regions; 
     deposition of P-Vapox dielectric on the face of the substrate; 
     opening of windows on the face of the substrate for formation of the source contacts, and 
     deposition of aluminum on the face of the substrate to provide source metallization and metallization of the source and gate pads; 
     wherein: 
     definition and formation of the source regions take place using a silicon oxide mask obtained by formation of spacers of dielectric material placed against the gate wall, and wherein 
     metallization of the source and gate contact areas is effected with silicides of refractory metals after formation of a spacer of dielectric material along the gate walls. 
     Other solutions in accordance with the invention are indicated below in the claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will now be described with reference to a nonlimiting embodiment example with reference to the annexed drawings wherein: 
     FIG. 1 shows the structure of a known power-MOS; 
     FIGS. 2-10 show the different steps of a process in accordance with the present invention; 
     FIG. 11 shows a power-MOS device obtained by the same process. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     An example of an embodiment of the process in accordance with the present invention is explained below for the manufacture of an N-channel power-MOS. However, with the necessary modifications clear to those skilled in the art, it also applies to the case of manufacture of a P-channel power-MOS transistor. 
     The process comprises in sequence the following steps, of which the initial ones, specifically from a. to d., are already provided for in the known art. 
     a. Epitaxial growth of a layer of type N silicon on a type N+ silicon substrate. 
     b. Growth of a layer of silicon dioxide (field oxide) on the epitaxial layer and subsequent definition of the edge of the chip by photoengraving. 
     c. Formation of a layer 2 of silicon dioxide (gate oxide) over the entire substrate and subsequent deposition of a layer 3 of polycrystalline silicon (poly). 
     d. Photoengraving of the poly for formation of the gate. 
     e. Implantation of the region 4 with type P dopant and in particular with boron (FIG. 2). 
     f. Deposition of a layer 5 of silicon nitride Si 3  N 4  200-400 ångstrom thick. 
     g. Deposition on the layer 5 of silicon nitride, by a Chemical Vapor Deposition (CVD) process, of a layer 6 of silicon dioxide SiO 2  (vapox) having a thickness on the order of 5000 ångstrom (FIG. 3). 
     h. Reactive Ion Etching (RIE) of the layer 6 of vapox dioxide so as to create a spacer 7 along the gate walls (FIG. 4). 
     i. Etching of the silicon nitride layer 5 in the unprotected area of the spacer. 
     l. Stripping of the vapox dioxide constituting the spacer to uncover the underlying silicon nitride 5 (FIG. 5). 
     m. Diffusion of the dopant present in 4 with the resulting formation of the region 8 of the body. 
     n. Formation of the layers 9 and 10 of silicon dioxide on the body and on the gate poly by a selective oxidation process using planox technology (FIG. 6). 
     o. Stripping of the layer of Si 3  N 4  from the area previously occupied by the spacer. 
     p. Implantation or predeposition of dopant, in particular arsenic, on the area 11 previously occupied by the spacer, using as a mask the layer 9 of silicon dioxide (FIG. 7). 
     q. Diffusion of the arsenic with resulting formation of the source regions 12 (FIG. 8). 
     r. Stripping of the layers 9 and 10 of dioxide previously formed on the body and on the gate poly. 
     s. Deposition of a vapox layer approximately 1500 ångstrom thick and subsequent RIE thereof with resulting provision of a spacer 14 along the gate walls (FIG. 8). 
     t. Deposition of a layer 15 of refractory metal, in particular titanium (FIG. 9). 
     u. Formation on the contact areas 16 of FIG. 10 of a silicide TiSi by Rapid Thermal Annealing (RTA). 
     v. Selective etching to eliminate the refractory metal covering said spacer 14 followed by further RTA and resulting sintering of the titanium to TiSi 2  (layer 16 of FIG. 10). 
     Indicated below are the steps, already provided in the known art, which follow: deposition of a layer of dielectric 17 approximately 11000 ångstrom thick on the face of the substrate, opening of windows in the dielectric layer for formation of the source contacts, metallization on the front (layer 18 of FIG. 11) and subsequent photoengraving, passivation and further photoengraving and finally finishing of the back face of the substrate. 
     The structure of the device obtained at the end of the process is shown schematically in FIG. 11. 
     Step o. of the process indicated above is optional. Indeed, implantation of dopant for formation of the source regions can take place without previous stripping of the layer of Si 3  N 4 . 
     For the photoengraving there is used photolithographic exposure equipment of the 5:1 stepper type which allows minimum apertures on the order of 1 μm with maximum misalignment between two successive photoengravings of 0.35 μm. 
     The use of these photographic exposure units together with self-alignment techniques such as those of spacers and self-aligned silicide make it possible to obtain considerable improvements without advanced photolithographic techniques. 
     In accordance with the present invention, the Xpitch dimension of the elementary cell is reduced to values not in excess of approximately 2-3 μm with the possibility of achieving a cell density on the order of 8·10 7  cells per square inch. As an indication Xc can be approximately 1.8 μm., and Xd about 1 μm. Indeed, the Xc dimension is conditioned by a single alignment and can fall to values of approximately 1.8 μm while Xd can fall to values of approximately 1 μm. 
     The sequence of operations is simplified with a reduction of maskings from 7 to 5. 
     Silicides on the source, on the body and on the gate polysilicon allow considerable reduction of the increase in parasite resistances due to the considerable reduction of the metal/semiconductor contact areas on the active regions and reduction of the increase in the resistance of the gate poly due to high integration. This also allows elimination of the risk of spikes on the aluminum of the metallization and consequently permits reduction of the body depth (not more than 0.4 μm) and the side dimensions of the body and gate. 
     Among other advantages the RTA process makes it possible to limit the side growth of the silicide on the spacer, which would otherwise risk short circuiting the gate with the other electrodes. 
     To the above advantages are to be added the following electrical advantages: 
     reduction of the size of the source produces a decrease in the R on  by a factor of 2 on the low voltage devices; 
     reduction of the base-emitter resistance R BE  of the parasite bipolar transistor improves the strength of the device with respect to the rapid voltage variations; 
     reduction of the size of the source, which goes from the present 4-6 μm to approximately 0.5 μm results in an increase of the strength of the power-MOS by a factor of 10. 
     Although the present invention has been described for a specific embodiment it is evident that many alternatives and variations, such as in materials and dimensions, will be apparent to those skilled in the art in light of the foregoing description. Accordingly, the invention is intended to embrace all of the alternative and variants that fall within the spirit and scope of the invention. For example, one of the variants can provide in step t. of the above described process the deposition of another refractory metal such as Co, W or an alloy thereof and in the latter case the formation of the related silicides in step u. 
     Another variant can consist of effecting a further self-aligned ionic implantation of dopant to form a deep body P+ region between steps i. and l. described above.