Abstract:
A data driving apparatus for a liquid crystal display includes a plurality of output buffer integrated circuits for buffering a plurality of pixel signals and outputting the plurality of pixel signals to a plurality of data lines; a plurality of digital to analog converter integrated circuits, each of which are commonly connected to input terminals of at least two of the plurality of output buffer integrated circuits, for converting input pixel data to the plurality of pixel signals and selectively outputting the plurality of pixel signals to the at least two output buffer integrated circuits; and timing control means for controlling the plurality of digital to analog converter integrated circuits and making a time division of the pixel data into at least two regions to sequentially supply the pixel data to the plurality of data lines.

Description:
This application claims the benefit of Korean Patent Application No. P2001-63207, filed in Korea on Oct. 13, 2001, which is hereby incorporated by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a liquid crystal display, and more particularly to a data driving apparatus and method for a liquid crystal display wherein a digital to analog converter and an output buffer are separately integrated to dramatically reduce a loss caused by a poor tape carrier package. Also, the present invention is directed to a data driving apparatus and method for a liquid crystal display wherein a digital to analog converter is driven on a time division basis to reduce the number of integrated circuits for providing a digital to analog conversion function. 
     2. Discussion of the Related Art 
     Generally, a liquid crystal display (LCD) controls a light transmittance of a liquid crystal using an electric field to display a picture. To this end, the LCD includes a liquid crystal display panel having liquid crystal cells arranged in a matrix, and a driving circuit for driving the liquid crystal display panel. 
     In the liquid crystal display panel, gate lines and data lines are arranged in such a manner as to cross each other. A liquid crystal cell is positioned at each intersection of the gate lines and the data lines. The liquid crystal display panel is provided with a pixel electrode and a common electrode for applying an electric field to each of the liquid crystal cells. Each pixel electrode is connected, via source and drain electrodes of a thin film transistor as a switching device, to any one of data lines. The gate electrode of the thin film transistor is connected to any one of the gate lines allowing a pixel voltage signal to be applied to the pixel electrodes for each one line. 
     The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, and a common voltage generator for driving the common electrode. The gate driver sequentially applies a scanning signal to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal display panel one line at a time. The data driver applies a data voltage signal to each of the data lines whenever the gate signal is applied to any one of the gate lines. The common voltage generator applies a common voltage signal to the common electrode. Accordingly, the LCD controls a light transmittance by an electric field applied between the pixel electrode and the common electrode in accordance with the data voltage signal for each liquid crystal cell, to thereby display a picture. Each of the data drivers and gate drivers is formed from an integrated circuit (IC) chip. They are mounted in a tape carrier package (TCP) and connected to the liquid crystal display panel by a tape automated bonding (TAB) system mainly. 
       FIG. 1  schematically shows a data driving block in a conventional LCD. 
     Referring to  FIG. 1 , the data driving block includes data driving ICs  4  connected, via TCPs  6 , to a liquid crystal display panel  2 , and a data printed circuit board (PCB)  8  connected, via the TCPs  6 , to the data driving ICs  4 . 
     The data PCB  8  receives various control signals from a timing controller (not shown), and data signals and driving voltage signals from a power generator (not shown) to interface them to the data driving ICs  4 . Each of the TCPs  6  is electrically connected to a data pad provided at the upper portion of the liquid crystal display panel  2  and an output pad provided at each data PCB  8 . The data driving ICs  4  convert digital pixel data into analog pixel signals to apply them to data lines. 
     To this end, as shown in  FIG. 2 , each of the data driving ICs  4  includes a shift register part  14  for applying a sequential sampling signal. A latch part  16  sequentially latches a pixel data VD in response to the sampling signal and outputs the pixel data VD at the same time. A digital to analog converter (DAC)  18  for converts the pixel data VD from the latch part  16  into a pixel signal. An output buffer part  26  buffers the pixel signal from the DAC  18  to output it. Further, the data driving ICs  4  each include a signal controller  10  for interfacing various control signals from a timing controller (not shown) and the pixel data VD. A gamma voltage part  12  supplies positive and negative gamma voltages required in the DAC  18 . Each of the data driving ICs  4  drives n data lines DLl to DLn. 
     The signal controller  10  controls various control signals such as, for example, SSP, SSC, SOE, REV and POL, and the pixel data VD to output them to the corresponding elements. The gamma voltage part  12  sub-divides several gamma reference voltages from a gamma reference voltage generator (not shown) for each gray level and outputs the sub-divided gamma reference voltges. 
     Shift registers included in the shift register part  14  sequentially shift a source start pulse SSP from the signal controller  10  in response to source sampling clock signal SSC to output the source start pulse SSP as a sampling signal. 
     A plurality of n latches included in the latch part  16  sequentially sample the pixel data VD from the signal controller  10  in response to the sampling signal from the shift register part  14  to latch it. Subsequently, the n latches respond to a source output enable signal SOE from the signal controller  10  to output the latched pixel data VD at the same time. In this case, the latch part  16  restores the pixel data VD modulated in such a manner to have a reduced transition bit number in response to a data inversion selecting signal REV and then outputs the pixel data VD. This is because the pixel data VD, having a transition bit number going beyond a reference value, is supplied such that it is modulated to have a reduced transition bit number in order to minimize an electromagnetic interference (EMI) upon data transmission from the timing controller. 
     The DAC  18  converts the pixel data VD from the latch part  16  into positive and negative pixel signals at the same time and outputs the signals. To this end, the DAC  18  includes a positive (P) decoding part  20  and a negative (N) decoding part  22 , each of which are commonly connected to the latch part  16 , and a multiplexor (MUX)  24  for selecting output signals of the P and N decoding parts  20  and  22 . 
     A plurality of n P decoders, which are included in the P decoding part  20 , convert n pixel data simultaneously inputted from the latch part  16  into positive pixel signals with the aid of positive gamma voltages from the gamma voltage part  12 . A plurality of n N decoders, which are included in the N decoding part  22 , convert n pixel data simultaneously inputted from the latch part  16  into negative pixel signals with the aid of negative gamma voltages from the gamma voltage part  12 . The multiplexor  24  responds to a polarity control signal POL from the signal controller  10  to selectively output the positive pixel signals from the P decoding part  20  or the negative pixel signals from the N decoding part  22 . 
     A plurality of n output buffers included in the output buffer part  26  consist of voltage followers which are connected to the n data lines DLl to DLn in series. These output buffers buffer the pixel signals from the DAC  18  and apply the signals to the data lines DLl to DLn. 
     As described above, each of the conventional data driving ICs  4  should have n latches and 2n decoders so as to drive n data lines DLl to DLn. As a result, the conventional data driving IC  4  has a disadvantage in that it has a complex configuration and a relatively high manufacturing cost. 
     Furthermore, each of the conventional data driving ICs  4  is attached to the TCP  6  in a single chip to adhered to the liquid crystal display panel  2  and the data PCB  8  as shown in  FIG. 1 . Accordingly, the TCP has a high probability of, for example, breaking or short-circuiting. Thus, a large loss in costs results since the data driving ICs  4  mounted in the TCP  6  also cannot be used when the TCP  6  breaks or short-circuits. 
     SUMMARY OF THE INVENTION 
     Accordingly, the present invention is directed to a data driving apparatus and method for liquid crystal display that substantially obviate one or more of the problems due to limitations and disadvantages of the related art. 
     An object of the present invention is to provide a data driving apparatus and method for a liquid crystal display wherein a digital to analog converter and an output buffer are separately integrated to dramatically reduce loss caused by a poor tape carrier package. 
     Another object of the present invention is to provide a data driving apparatus and method for a liquid crystal display wherein a digital to analog converter is driven on a time division basis to reduce the number of integrated circuits for providing a digital to analog conversion function. 
     Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings. 
     To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the data driving apparatus for a liquid crystal display includes: a plurality of output buffer integrated circuits for buffering a plurality of pixel signals and outputting the plurality of pixel signals to a plurality of data lines; a plurality of digital to analog converter integrated circuits, each of which are commonly connected to input terminals of at least two of the plurality of output buffer integrated circuits, for converting input pixel data to the plurality of pixel signals and selectively outputting the plurality of pixel signals to the at least two output buffer integrated circuits; and timing control means for controlling the plurality of digital to analog converter integrated circuits and making a time division of the pixel data into at least two regions to sequentially supply the pixel data to the plurality of data lines. 
     A data driving apparatus for a liquid crystal display according to another aspect of the present invention includes: a plurality of output buffer integrated circuits for buffering a plurality of pixel signals and outputting the plurality of pixel signals to a plurality of data lines; and a plurality of digital to analog converter integrated circuits, each of which are commonly connected to input terminals of at least two of the plurality of output buffer integrated circuits, for converting input pixel data to the plurality of pixel signals and outputting the plurality of pixel signals to the at least two output buffer integrated circuits in a time division of the pixel signals. 
     In another aspect, a method of driving a data driving apparatus for driving a plurality of data lines arranged at a liquid crystal display panel, wherein the driving apparatus includes a plurality of output buffer integrated circuits connected to the plurality of data lines, and a plurality of digital to analog converter integrated circuits commonly connected to input terminals of at least two of the plurality of output buffer integrated circuits, includes: making a time division of pixel data to be supplied to each of the plurality of digital to analog converter integrated circuits into at least two regions; converting the pixel data into analog pixel signals; and selectively applying the converted pixel signals to the at least two output buffer integrated circuits and to the plurality of data lines. 
     A method of driving a data driving apparatus for a liquid crystal display panel display according to another aspect of the present invention includes: converting at least two pixel data into analog pixel data, and outputting the converted pixel signals to at least two output buffer integrated circuits in a time division of the pixel signals. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. 
         FIG. 1  is a schematic view showing a data driving block in a conventional liquid crystal display. 
         FIG. 2  is a block diagram showing a configuration of the data driving integrated circuit in  FIG. 1 . 
         FIG. 3  is a block diagram showing a configuration of a data driver in a liquid crystal display according to an embodiment of the present invention. 
         FIG. 4A  and  FIG. 4B  are comparative waveform diagrams of driving signals of the latch part shown in  FIG. 2  and the latch part shown in  FIG. 3 , and  FIG. 4C  is a waveform diagram of a driving signal of the demultiplexor shown in  FIG. 3 . 
         FIG. 5  is a schematic view showing a data driving block in the liquid crystal display including the data driver shown in  FIG. 3 . 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. 
       FIG. 3  is a block diagram showing a configuration of a data driving apparatus for a liquid crystal display according to an embodiment of the present invention. 
     Referring to  FIG. 3 , the data driving apparatus is largely divided into DAC means having a digital to analog conversion function and buffer means having an output buffering function, which are integrated into a separated chip. In other words, the data driving apparatus has a DAC IC  30  and at least two output buffer ICs  50  configured separately. Particularly, the DAC IC  30  is divided into at least two regions on a time basis such that the at least two output buffer ICs  50  are commonly connected to a single DAC IC  30  for driving, to thereby provide a DAC function. 
     Hereinafter, a case where two output buffer ICs  50  are commonly connected to a single DAC IC  30  will be described as an example. 
     The DAC IC  30  includes a shift register part  36  for applying a sequential sampling signal. A latch part  38  sequentially latches a pixel data VD in response to the sampling signal and outputs the pixel data VD at the same time. A digital to analog converter (DAC)  40  converts the pixel data VD from the latch part  38  into a pixel signal. A demultiplexor  48  sequentially applies the pixel signal from the DAC  40  to the two output buffer ICs  50 . Furthermore, the DAC IC  30  includes a signal controller  32  for interfacing various control signals from a timing controller (not shown) and the pixel data VD. A gamma voltage part  34  supplies positive and negative gamma voltages required in the DAC  40 . Each DAC IC  30  is driven on a time division basis to sequentially output pixel signals to be applied to 2n data lines DL 1 l to DL 1 n and DL 2 l to DL 2 n n by n. 
     In order to permit the DAC IC  30  to drive twice the number of data lines as compared to the number of data lines in the conventional data driving IC, driving signals have frequencies that are twice those of the conventional data driving IC. 
     The signal controller  32  controls various control signals such as, for example, SSP, SSC, SOE, REV, and POL, from a timing controller and the pixel data VD to output them to the corresponding elements. In this case, the timing controller allows the various control signals and the pixel data VD to have a frequency twice that of the prior art. Particularly, the timing controller makes a time division of 2n pixel data VD corresponding to the 2n data lines DL 1 l to DL 1 n and DL 2 l to DL 2 n into two regions to sequentially supply them n by n. 
     The gamma voltage part  34  sub-divides a plurality of gamma reference voltages from a gamma reference voltage generator (not shown) for each gray level and outputs the sub-divided gamma reference voltages. 
     Shift registers included in the shift register part  36  sequentially shift a source start pulse SSP from the signal controller  32  in response to a source sampling clock signal SSC to output the source start pulse SSP as a sampling signal. In this case, the shift register part  36  responds to the source start pulse SSP and the source sampling clock signal SSC each having a frequency doubled to output a sampling signal at twice the speed in comparison to the prior art. 
     A plurality of n latches included in the latch part  38  sequentially sample the pixel data VD from the signal controller  32  in response to the sampling signal from the shift register part  36  to latch it. Subsequently, the n latches respond to a source output enable signal SOE from the signal controller  32  to output the latched pixel data VD at the same time. In this case, the latches restore the pixel data VD modulated in such a manner as to have a reduced transition bit number in response to a data inversion selecting signal REV and then output the pixel data VD. This is because the pixel data VD, having a transition bit number going beyond a reference value, is supplied such that it is modulated to have a reduced transition bit number in order to minimize an electromagnetic interference (EMI) upon data transmission from the timing controller. 
     Herein, the source sampling clock signal SSC and the source output enable signal SOE applied to the shift register part  36  and the latch part  38  have twice frequency of the “SSC” and “SOE” applied to the conventional shift register part  14  and latch part  16  shown in  FIG. 2 , as indicated by “NSSC” and “NSOE” in  FIG. 4A  and  FIG. 4B , respectively. 
     The DAC  40  converts the pixel data VD from the latch part  38  into positive and negative pixel signals at the same time and outputs the signals. To this end, the DAC  40  includes a positive (P) decoding part  42  and a negative (N) decoding part  44 , each of which are commonly connected to the latch part  38 , and a multiplexor (MUX)  46  for selecting output signals of the P and N decoding parts  42  and  44 . 
     A plurality of n P decoders, which are included in the P decoding part  42 , convert n pixel data simultaneously inputted from the latch part  38  into positive pixel signals with the aid of positive gamma voltages from the gamma voltage part  34 . A plurality of n N decoders, which are included in the N decoding part  44 , convert n pixel data simultaneously inputted from the latch part  38  into negative pixel signals with the aid of negative gamma voltages from the gamma voltage part  34 . The multiplexor  46  responds to a polarity control signal POL from the signal controller  32  to selectively output the positive pixel signals from the P decoding part  42  or the negative pixel signals from the N decoding part  44 . The DAC  40  converts the pixel data into pixel signals n by n at a speed twice that of the conventional DAC  18 , to thereby convert the 2n pixel data into pixel signals. 
     The demultiplexor  48  outputs n pixel signals from the multiplexor  46  to the first output buffer IC  50  or the second output buffer IC  50  in response to a selection control signal SEL inputted from the signal controller  32  as shown in  FIG. 4C . The selection control signal SEL has an inverted logical value every period of the source output enable signal SOE applied to the latch part  38 , thereby allowing each of the n pixel signals to sequentially be output to the first output buffer IC  50  and the second output buffer IC  50 . 
     Each of the first and second output buffer ICs  50  includes an output buffer part  52  for buffering pixel signals from the DAC IC  30  to output them to the n data lines DL 1 l to DL 1 n or DL 2 l to DL 2 n. n output buffers included in each output buffer part  52  consist of voltage followers which are connected to the n data lines DL 1 l to DL 1 n or DL 2 l to DL 2 n in series. These output buffers make a buffering of the pixel signals from the DAC  18  and apply them to the data lines DL 1 l to DL 1 n or DL 2 l to DL 2 n. 
     As shown in  FIG. 5 , the DAC ICs  30  are mounted in a data PCB  68  while the output buffer ICs  50  are mounted in a TCP  66 . The data PCB  68  sends various control signals from a timing controller (not shown) and data signals to the DAC ICs  30 , and sends pixel signals from the DAC ICs  30  to the output buffer ICs  50  via the TCP  66 . The TCP  66  is electrically connected to data pads provided at the upper portion of a liquid crystal display panel  62  and output pads provided at the PCB  68 . As described above, the simply configured output buffer ICs  50 , having only a buffering function, are mounted in the TCP  66 , so that only the output buffer ICs  50  are damaged when the TCP  66  is damaged. As a result, the large loss in costs resulting from an inability to use the expensive data driving ICs caused by a damaged TCP  66  in the prior art can be reduced dramatically. Furthermore, the DAC IC  30  is divided on a time basis to sequentially apply the pixel signals to at least two output buffer ICs  50  n by n. Accordingly, the number of DAC ICs  30  is reduced to ½ in comparison to prior art arrangements, so that it becomes possible to reduce the manufacturing cost. 
     As described above, according to the present invention, the DAC means and the output buffering means are integrated into a separate chip to thereby mount only the simply configured output buffer ICs in the TCP having a high probability of breaking or short-circuiting. Accordingly, it is possible to dramatically reduce loss resulted from the inability to use the expensive data driver ICs due to a damaged TCP in prior art arrangements. 
     Moreover, according to the present invention, the DAC IC is driven on a time division basis with the aid of driving signals having higher frequencies to thereby commonly connect a single DAC IC to at least two output buffer ICs, so that it becomes possible to reduce the number of DAC ICs and thus the manufacturing cost. 
     It will be apparent to those skilled in the art that various modifications and variations can be made in the data driving apparatus and method for liquid crystal display of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.