Abstract:
Disclosed herewith is a packet transfer apparatus that carries out 1+1 protection switching for traffics to be received variably in both length and cycle. The apparatus enables flows to be multiplexed and the link usage efficiency to be improved without generating any buffer overflow errors. The data transfer apparatus, upon receiving the third sequentially numbered data from the first communication route before receiving the preceding second sequentially numbered data, stores the received third data in a buffer. And upon receiving the second sequentially numbered data from the second communication route, the apparatus sends the second and third data sequentially. Then, upon receiving the third sequentially numbered data from the second communication route before receiving the second sequentially numbered data, the apparatus sends the third data when a predetermined waiting time expires.

Description:
CLAIM OF PRIORITY 
       [0001]    The present application claims priority from Japanese application JP 2007-182971 filed on Jul. 12, 2007, the content of which is hereby incorporated by reference into this application. 
       FIELD OF THE INVENTION 
       [0002]    The technique disclosed in this specification relates to a packet transfer apparatus, more particularly to a packet transfer apparatus and a system provided with a protection switching function, respectively and connected to each other through a plurality of links. 
       BACKGROUND OF THE INVENTION 
       [0003]    The Japanese government, which had shown “e-Japan strategy” and “e-Japan priority plans” previously, has now presented a goal to formation of a high-grade information communication network society and concrete policies required to achieve the goal with priority. One of the subject matters to achieve the great plans is fusion of broadcasting and communications. If the broadcasting that has accumulated a variety of abundant programs and contents and computer networks that have been improved rapidly in convenience and serviceability are fused into one, new network services will be born. Such expectations have been increasingly built up in recent years. 
         [0004]    A streaming technique is one of the techniques that have been most expected to realize such broadcasting services on the existing networks. In case of a streaming service, it is required to reproduce frames at specified times, respectively, so that the data including the one to be reproduced several seconds later are held in an application buffer. If this buffer does not store data enough to be reproduced consecutively, the reproduction is suspended until a certain amount of data are accumulated in the buffer. Consequently, the quality of broadcasting services comes to be affected significantly by delays and jittering of the communication, as well as frame losses. Preventing such frame losses has thus been considered to be most important in those broadcasting services. 
         [0005]    The current IP (Internet Protocol) network prevents such frame losses through the retransmission control by the TCP (Transport Control Protocol), which is an upper layer protocol. However, the retransmission control might cause communication delays to increase. This is why the retransmission control cannot apply to such services as broadcasting services that do not allow significant delays. And under such circumstances, the UDP (User Datagram Protocol) is used as an upper layer protocol for transferring broadcasting service data. The UDP does not have any function to prevent frame losses as described above, however. A protection switching function is effective to duplicate the communication route, thereby preventing such frame losses. Particularly, the 1+1 protection switching function that enables a copy of each frame to be sent from a sender apparatus to a plurality of routes, those frames and their copies to be selected at and transferred from the receiver apparatus is the most effective means to prevent the frame losses as described above. 
         [0006]    In case of the 1+1 protection switching function, the sender apparatus adds a sequence number to each frame and copies the frame, then sends out those frames and their copies into a plurality of communication routes. A frame and its copy are given a same sequence number. On the other hand, the receiver apparatus checks the sequence number of each frame received from the plurality of communication routes and selects and transfers only normal frames. 
         [0007]    In case of the technique disclosed in JP-A No. 2006-100900, the sender apparatus sends VoIP (Voice over IP) frames to a plurality of routes. And the receiver apparatus stores the frames received from the plurality of routes in a frame buffer of which addresses are assigned so as to correspond to the sequence numbers of those frames, respectively. The receiver apparatus then reads those frames from the frame buffer in the order of sequence numbers, thereby transferring the frames in the order of sequence numbers. Consequently, frame missing and frame disordering are prevented without requiring any complicated processings such as frame sorting in the buffer. 
       SUMMARY OF THE INVENTION 
       [0008]    In case of each of the conventional 1+1 protection switching functions including the one disclosed in JP-A No. 2006-100900, it is premised that subject services handle only the frames that are fixed in sending cycle and frame length just like those of the VoIP and TDM (Time Division Multiplex) emulation. Consequently, even when a plurality of logic flows are multiplexed, it is possible to assign a time slot to each logic flow and read frames from the frame buffer periodically. 
         [0009]    However, as described above, in case of broadcasting services, it is premised that subject data including the one to be reproduced several seconds later are held in an application buffer beforehand, so that the frame traffic comes to have burst characteristics and frames do not arrive periodically. Furthermore, the frames are variable in length. Consequently, if a plurality of flows are multiplexed, a time slot cannot be assigned to each flow. This is because the timing must be adjusted to the maximum frame length at the time of time slot assignment to each variable length frame and in such a situation, it is impossible to utilize the bandwidth of the subject communication line sufficiently, and furthermore the number of logic flows to be multiplexed comes to be limited by the bandwidth of the subject communication line. And if those logic flows are multiplexed up to the upper limit of the subject bandwidth, assignment of the timing to the maximum frame length cannot catch up with the transfer speed of frames that arrive like bursts, thereby buffer overflows might often occur. 
         [0010]    This is why frames are required to be read irregularly from the buffer in such a case. In other words, frames are required to be kept read from the buffer as long as there are any frames stored in the buffer. In addition, frames are required to be transferred in the order of sequence numbers, so that if one frame loss occurs in one communication route (e.g., the communication route  0 ), even when the next frame is received normally and stored in the buffer, the receiver apparatus is required to wait for the arrival of a frame having the same sequence number from the other communication route (e.g., the communication route  1 ). 
         [0011]    Concretely, for example, there is a conceivable case in which a frame having a sequence number (SN):2 to be received from the communication route  0  is lost and the receiver apparatus receives the next SN:3 frame. In this case, at the time of receiving the SN:3 frame from the communication route  0 , the receiver apparatus does not receive the SN:2 frame from the communication route  1  yet due to the transfer delay difference between the communication routes  0  and  1 . Consequently, the receiver apparatus is required to wait for the transfer of the SN:3 frame until receiving the SN:2 frame from the communication route  1 . However, if the SN:2 frame is also lost in the communication route  1 , the receiver apparatus cannot receive the frame from any of the routes  0  and  1 . As a result, the very transfer of the SN:3 frame stored in the buffer is disabled at this time. 
         [0012]    In order to avoid such a problem, there is a conceivable case in which when the receiver apparatus receives the SN:3 frame from both of the communication routes  0  and  1 , it is determined that the SN:2 frame is lost in both of the communication routes  0  and  1  and the sender apparatus is enabled to send the SN:3 frame. In this case, it is premised that no frame disordering has occurred in each communication route. Actually, in case of a highly reliable network provided with the 1+1 protection switching function, the network is easily prevented from occurrence of frame disordering in a same flow and the network is built up such way as a matter of course. In case of the above controlling method, however, for example, if the receiver apparatus cannot receive the SN:3 and its subsequent frames from the communication route  1  due to a line trouble that has occurred in the communication route  1 , the transfer apparatus is disabled to transfer any frames even when receiving those frames from the normal communication route  0 . This has been a problem. And this makes the execution of the 1+1 protection switching function meaningless. 
         [0013]    Under such circumstances, it is a typical object of the present invention disclosed in this specification to provide a data transfer apparatus comprising a plurality of interfaces connected to one or more communication routes; a buffer that stores data temporarily; and a buffer controller that controls the buffer. The plurality of interfaces include a first interface and a second interface and the plurality of communication routes include a first communication route connected to the first interface and a second communication route connected to the second interface. The first and second interfaces receive sequentially numbered data from the first and second communication routes, respectively. If the data transfer apparatus receives sequentially numbered second data from the first communication route before receiving sequentially numbered first data, the buffer controller stores the received second data in the buffer. And when the data transfer apparatus receives the first sequentially numbered data from the second communication route, the buffer controller stores the received first data in the buffer, read the first and second data from the buffer in the order of their sequence numbers, and sends to one of the plurality of interfaces. If the data transfer apparatus receives the second sequentially numbered data from the second communication route before receiving the first sequentially numbered data, the buffer controller reads the second data from the buffer and sends to one of the plurality of interfaces. Then, the buffer controller checks whether or not a predetermined waiting time has expired. If the predetermined waiting time has already expired, the buffer controller reads the second data from the buffer and sends to one of the plurality of interfaces. 
         [0014]    According to an aspect of the present invention, because a 1+1 protection switching function is executed for such services as broadcasting services of which variable-length frames arrive irregularly, frame losses can be prevented, thereby providing users with high quality services. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]      FIG. 1  is a block diagram of a communication network to which a packet transfer apparatus in a first embodiment of the present invention applies; 
           [0016]      FIG. 2  is a diagram illustrating an outline of an operation of the packet transfer apparatus in the first embodiment of the present invention; 
           [0017]      FIG. 3  is a format of the frames used for the communication between a terminal and the packet transfer apparatus in the first embodiment of the present invention; 
           [0018]      FIG. 4  is a format of the frames used in the communication in a communication route in the first embodiment of the present invention; 
           [0019]      FIG. 5  is a block diagram of the packet transfer apparatus in the first embodiment of the present invention; 
           [0020]      FIG. 6  is a format of an inner header added by an input/output line interface in the first embodiment of the present invention; 
           [0021]      FIG. 7  is a format of a header processing table in the first embodiment of the present invention; 
           [0022]      FIG. 8  is a block diagram of an input frame buffer controller in the first embodiment of the present invention; 
           [0023]      FIG. 9  is a flowchart of a buffer write processing executed by a buffer write processor in the first embodiment of the present invention; 
           [0024]      FIG. 10  is a flowchart of a sequence number check processing executed by the buffer write processor in the first embodiment of the present invention; 
           [0025]      FIG. 11  is a flowchart of a user data receiving processing executed by the buffer write processor in the first embodiment of the present invention; 
           [0026]      FIG. 12  is a configuration of an input frame buffer in the first embodiment of the present invention; 
           [0027]      FIG. 13  is a flowchart of a send frame request processing executed by a buffer read processor in the first embodiment of the present invention; 
           [0028]      FIG. 14  is a first part of a processing of a request to send frames in the order of sequence numbers, executed by a buffer read processor in the first embodiment of the present invention; 
           [0029]      FIG. 15  is a second part of the flowchart of the processing of the request to send frames in the order of sequence numbers, executed by the buffer read processor in the first embodiment of the present invention; 
           [0030]      FIG. 16  is a flowchart of a send user data request processing executed by the buffer read processor in the first embodiment of the present invention; 
           [0031]      FIG. 17  is a configuration of a waiting time holding table in the first embodiment of the present invention; 
           [0032]      FIG. 18  is a flowchart of a frame sending processing executed by the buffer read processor in the first embodiment of the present invention; 
           [0033]      FIG. 19  is a configuration of a copying table in the first embodiment of the present invention; 
           [0034]      FIG. 20  is a configuration of a sending SN table in the first embodiment of the present invention; 
           [0035]      FIG. 21  is a diagram illustrating an outline of an operation of a packet transfer apparatus in a second embodiment of the present invention; 
           [0036]      FIG. 22  is a diagram illustrating an outline of an operation of a packet transfer apparatus in a variation of the second embodiment of the present invention; 
           [0037]      FIG. 23  is a block diagram of an input frame buffer controller in the second embodiment of the present invention; 
           [0038]      FIG. 24  is a flowchart of a sequence number check processing executed by a buffer write processor in the second embodiment of the present invention; 
           [0039]      FIG. 25  is a first part of a flowchart of a waiting time updating processing executed by the buffer write processor in the second embodiment of the present invention; 
           [0040]      FIG. 26  is a second part of the flowchart of the waiting time updating processing executed by the buffer write processor in the second embodiment of the present invention; 
           [0041]      FIG. 27  is a configuration of the waiting time holding table in the second embodiment of the present invention; 
           [0042]      FIG. 28  is a first part of a flowchart of a processing to send frames in the order of sequence numbers, executed by the buffer read processor in the second embodiment of the present invention; and 
           [0043]      FIG. 29  is a second part of the flowchart of the processing to send frames in the order of sequence numbers, executed by the buffer read processor in the second embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0044]    Hereunder, there will be described the preferred embodiments of the present invention with reference to the accompanying drawings. 
         [0045]      FIG. 1  shows a block diagram of a communication network to which a packet transfer apparatus in a first embodiment of the present invention is applied. 
         [0046]    In  FIG. 1 , a packet transfer apparatus  10 A is connected to another packet transfer apparatus  10 N through two or more communication routes. (e.g., a communication route  0  NW 0  and a communication route  1  NW 1 ). These communication routes  0  NW 0  and  1  NW 1  may be physical lines or networks composed of one or more packet transfer apparatuses, respectively. Furthermore, the packet transfer apparatus  10 A is connected to a terminal  70 - 1 . 
         [0047]    The packet transfer apparatus  10 A, disposed between the packet transfer apparatus  10 N and the terminal  70 - 1 , intermediates the transfer of frames between them. In the other words, the packet transfer apparatus  10 A receives frames and processes the received frames as needed, and sends those received and processed frames to the terminal  70 - 1  and the packet transfer apparatus  10 N. More concretely, when the terminal  70 - 1  outputs a frame  30  to the packet transfer apparatus  10 A, the packet transfer apparatus  10 A adds a sequence number  32  to the frame  30 . The sequence number  32  represents the ordering information of frames to be sent. The packet transfer apparatus  10 A then copies the frame  30  and sends the frame  30  and its copy to the communication routes  0  NW 0  and  1  NW 1 , respectively. 
         [0048]    Specific fixed addresses are set for the interfaces of the packet transfer apparatuses  10 A and  10 N, respectively. Those apparatuses  10 A and  10 N are connected to the communication routes  0  NW 0  and  1  NW 1 , respectively. The packet transfer apparatus  10 A, upon sending the frame  30  to each communication route  0 / 1 , adds a header  33  that includes a destination address to the frame  30  so that the frame  30  arrives at the interface of the receiving side packet transfer apparatus  10 N corresponding to each communication route. 
         [0049]    The opposite packet transfer apparatus  10 N monitors the frames having the sequence number  32  among those to be received from a plurality of communication routes for sequence number loss and disordering, then transfers the frame  34  in the order of sequence numbers to the terminal  70 - n . The frame  34  is generated as follows; the packet transfer apparatus  10 N, upon receiving the frame  32 , deletes the unnecessary sequence number  32  and header  33  from the received frame, thereby generating the frame  34 . 
         [0050]    While frames are flown from the terminal  70 - 1  to the terminal  70 - n  here as described above, frames are also flown in the reverse direction similarly. In other words, the packet transfer apparatus  10 A and the packet transfer apparatus  10 N are completely the same in configuration. 
         [0051]    The packet transfer apparatuses  10 A and  10 N may also transfer Ethernet (registered trademark) frames that include an IP (Internet Protocol) packet as a payload, respectively. The present invention can apply to any data transfer apparatuses capable of transferring data in any formats. 
         [0052]      FIG. 2  shows a diagram illustrating an outline of an operation of the packet transfer apparatus  10 N in the first embodiment of the present invention. 
         [0053]    Concretely,  FIG. 2  shows an example of a timing at which the packet transfer apparatus  10 N receives frames from the communication routes  0  NW 0  and  1  NW 1  and an example of a processing of the packet transfer apparatus  10 N, executed upon receiving those frames. In each example shown in  FIG. 2 , two horizontal axes correspond to two communication routes. Each of those horizontal axes shows a timing at which the packet transfer apparatus  10 N receives frames through each communication route. It denotes that the father frames are displayed toward the right side, the earlier they are received. 
         [0054]    The packet transfer apparatus  10 N receives frames from two communication routes, that is, from the communication routes  0  NW 0  and  1  NW 1 , respectively. A sequence number (SN) is added to each frame to be received. The sequence number (SN) represents an order of frame sending. If a same sequence number is given to some frames, those frames include at least a same payload  405  (refer to  FIG. 3 ). In the description to be made below, if some frames include a same content, it means that those frames include at least a same payload  405 . The packet transfer apparatus  10 N stores received frames once in the buffer (refer to  FIG. 5 ). And if there is even one frame in the buffer, the packet transfer apparatus  10 N reads the frame from the buffer immediately and transfers the read frame to the terminal  70 - n . At this time, the packet transfer apparatus  10 N keeps checking sequence numbers for missing and disordering, thereby transferring frames in the order of their sequence numbers. 
         [0055]    In the example shown in  FIG. 2 , the packet transfer apparatus  10 A sends out frames of which sequence numbers are from (SN):1 to SN:4 sequentially. 
         [0056]    In the example shown in  FIG. 2 , the transfer delay of the communication route  0  NW 0  is smaller than that of the communication route  1  NW 1 . Consequently, the frames transferred through the communication route  0  NW 0  always arrive in the packet transfer apparatus  10 N earlier than the frames transferred through the communication route  1  NW 1  even when the contents are the same between those frames transferred through those two communication routes. The packet transfer apparatus  10 N, upon receiving frames from the communication route  0  NW 0 , usually stores those frames in the buffer, then sends those frames out immediately to the destination. 
         [0057]    In the example shown in  FIG. 2 , the packet transfer apparatus  10 N receives the frame  301  of SN:1 from the communication route  0  NW 0  first. In this case, the packet transfer apparatus  10 N stores the received frame  301  in the buffer, then sends the frame  301  to the terminal  70 - n . At this time, the packet transfer apparatus  10 N, as described with reference to  FIG. 1 , deletes the sequence number  32  and header  33  from the frame  301  to be sent to the terminal  70 - n.    
         [0058]    After that, the packet transfer apparatus  10 N receives the frame  311  of SN:1 from the communication route  1  NW 1 . If the frame  301  is already sent out at this time, the packet transfer apparatus  10 N never sends the frame  311  to the terminal  70 - n.    
         [0059]    The packet transfer apparatus  10 N, if there occurs no frame loss, is scheduled to receive the SN:2 frame  302  after receiving the SN:1 frame  301 . In the example shown in  FIG. 2 , however, the frame  302  is lost. In this case, the packet transfer apparatus  10 N receives the SN:2 frame  312  from the communication route  1  NW 1  and stores the frame  312  in the buffer, then sends the frame  312  to the terminal  70 - n.    
         [0060]    In some cases, however, the packet transfer apparatus  10 N happens to receive the SN:3 frame  303  from the communication route  0  NW 0  before receiving the frame  312  due to the transfer delay difference between the communication routes  0  NW 0  and  1  NW 1 . In this case, the packet transfer apparatus  10 N, although it has already received the SN:3 frame  303 , is required to wait for the SN:2 frame  312  that is expected to arrive from the communication route  1  NW 1 . In other words, the packet transfer apparatus  10 N stores the received frame  303  in the buffer, but cannot send the frame  303  before receiving and completing of sending the frame  312  to the terminal  70 - n . Consequently, if the frame  312  is also lost at this time, the packet transfer apparatus  10 N is disabled to send the frame  303 , which is already received normally. 
         [0061]    In each communication route  0  NW 0 / 1  NW 1 , therefore, no frame disordering occurrence will be a conceivable case. In this case, upon receiving the frames  303  and  313  having the sequence number SN:3 from both of the communication routes  0  NW 0  and  1  NW 1  before receiving the frames  302  and  312  having the sequence number SN:2, the packet transfer apparatus  10 N determines the loss of the frames  302  and  312  in both of the communication routes  0  NW 0  and  1  NW 1 , thereby the packet transfer apparatus  10 N is enabled to send the frame  303  or  313  having the sequence number SN:3 to the terminal  70 - n.    
         [0062]    According to the controlling method as described above, if the SN:3 frame  313  and its subsequent frames are further lost in the communication route  1  NW 1  due to a trouble in the communication route, the packet transfer apparatus  10 N cannot send the SN:3 frame  303  received normally from the communication route  0  NW 0  and furthermore, the packet transfer apparatus  10 N comes to be disabled to send any of the subsequent received frames to the destination. 
         [0063]    In order to avoid such a trouble, therefore, the packet transfer apparatus  10 N in this embodiment, upon detecting a loss of any sequence number due to a frame loss as described above, stops the frame sending temporarily. At this time, the packet transfer apparatus  10 N sets the transfer delay difference between both of the routes  0  NW 0  and  1  NW 1  for the timer (refer to  FIG. 8 ) and starts the timer count-down. In other words, when the count-down begins, the value set for the timer is reduced with time and becomes ‘0’ finally. And when this timer value becomes ‘0’, when the packet transfer apparatus  10 N receives the SN:2 frame, or when the packet transfer apparatus  10 N receives the SN:3 frame from both of the routes  0  NW 0  and  1  NW 1 , the packet transfer apparatus  10 N restarts the frame sending. 
         [0064]    As a result, if the SN:3 frame  313  is lost in the communication route  1  NW 1  as shown in  FIG. 2 , and even if a line error occurs in one of the communication routes  0  NW 0  and  1  NW 1 , the frame sending is not stopped completely, thereby frame losing is prevented. 
         [0065]    In the description to be made below, if a frame is lost (if the packet transfer apparatus  10 N cannot receive the frame), it is conceivable that the frame has arrived normally at the packet transfer apparatus  10 N, but it is not received correctly by the apparatus  10 N due to an error detected in the frame FCS  406  or  417  (refer to  FIGS. 3 and 4 ) as a result of an error check. In this case, the frame is discarded. Thus the packet transfer apparatus  10 N cannot transfer the received frame. 
         [0066]      FIG. 3  shows a format of the frame  40  used in the communication between the terminal  70  and the packet transfer apparatus  10 A/ 10 N. 
         [0067]    In other words, the frame  40  is equivalent to each of the frames  30  and  34  shown in  FIG. 1 . 
         [0068]    The frame  40  includes fields of destination MAC address  401 , source MAC address  402 , VLAN tag  403 , type value  404 , payload  405 , and frame check sequence (FCS)  406 . 
         [0069]    In the field of destination MAC address  401  is set the packet transfer apparatus  10 A, which is the destination of the frame  40 , as well as the MAC address of the interface of the packet transfer apparatus  10 A or terminal  70  (e.g., an input/output line interface  11  shown in  FIG. 5 ). 
         [0070]    In the field of source MAC address  402  are set the packet transfer apparatus  10 A, which is the source of the frame  40 , as well as the MAC address of the interface of the packet transfer apparatus  10 N or terminal  70 . 
         [0071]    The VLAN tag  403  denotes the value of the VLAN ID (VID#) to be assumed as a flow identifier. 
         [0072]    The type value  404  denotes the type of the subsequent header. 
         [0073]    The fields from the destination MAC address  401  to the type value  404  are combined to form a MAC header. 
         [0074]    The payload  405  is data (payload) to be carried by the frame  40 . The payload  405  may store an upper-order protocol packet (e.g., IP packet). 
         [0075]    The FCS  406  is a check code used to detect frame error existence. The receiving side packet transfer apparatus  10 N, etc. check this FCS  406  of each received frame. If an error is detected in the check, the packet transfer apparatus  10 N, etc. discard the received frame. In other words, the frame is determined as a lost one. 
         [0076]      FIG. 4  is a format of the frame  41  used for the communication in the communication routes  0  NW 0  and  1  NW 1  in the first embodiment of the present invention. 
         [0077]    The frame  41  is equivalent to each frame transferred from the packet transfer apparatus  10 A to the packet transfer apparatus  10 N in the example shown in  FIG. 1 . 
         [0078]    The frame  41  consists of fields of destination MAC address  411 , source MAC address  412 , type value  413 , MPLS header  414 , sequence number  415 , payload  416 , and frame check sequence (FCS)  417 . 
         [0079]    In the field of destination MAC address  411  is set the MAC address of the interface of the packet transfer apparatus (packet transfer apparatus  10 A in the example shown in  FIG. 1 ), which is the destination of the frame  41 . 
         [0080]    In the field of source MAC address  412  is set the MAC address of the interface of the packet transfer apparatus (packet transfer apparatus  10 N in the example shown in  FIG. 1 ), which is the source of the frame  41 . 
         [0081]    The type value  413  denotes the type of the subsequent header. 
         [0082]    The fields from the destination MAC address  411  to the type value  413  are combined to form a MAC header. 
         [0083]    The MPLS header  414  denotes a value (label #) of the label assumed as a flow identifier. 
         [0084]    In the field of sequence number  415  is set consecutive integers denoting the frame sending order in each flow. The smaller the sequence number  415  is, the earlier the subject frame is sent out from the source. 
         [0085]    In the field of payload  416  is stored the frame  40  received from the terminal  70  as is. 
         [0086]    The frame check sequence (FCS)  417  is a check code used to detect error existence in the frame  41 . The FCS  417  is checked by the packet transfer apparatus  10 N, etc. at the receiving side. 
         [0087]      FIG. 5  shows a block diagram of the packet transfer apparatus  10 N in the first embodiment of the present invention. 
         [0088]    The packet transfer apparatus  10 A and the packet transfer apparatus  10 N are the same in configuration, so that the description of the configuration of the packet transfer apparatus  10 A will be omitted here. 
         [0089]    The packet transfer apparatus  10 N includes a plurality of network interface boards (NIF)  10 - 1  to  10 - n  and a frame switching block  15  connected to those interface boards. Hereunder, there will be described those interface boards NIF  10 - 1  to  10 - n  that will be described as NIF  10  generically in common descriptions for them. 
         [0090]    The NIF  10  includes a plurality of input/output line interfaces  11 - 1  to  11 - 2  that function as communication ports, respectively. The NIF  10  is connected to the terminal  70  through the communication route  0  NW 0  or  1  NW 1 . Hereunder, those input/output line interfaces  11 - 1  and  11 - 2  will be described as the input/output line interface  11  generically in the common description for them. Although two input/output line interfaces  11  are shown in  FIG. 5 , the NIF  10  may include many more input/output line interfaces  11 . The input/output line interface  11  in this first embodiment is an Ethernet (registered trademark) line interface. 
         [0091]    The NIF  10  includes an input header processor  12  connected to the input/output line interface  11  and an input frame buffer controller  13  connected to the input header processor  12 . Furthermore, the NIF  10  includes a plurality of switch (SW) interfaces  14 - 1  to  14 - 2  connected to the frame switching block  15 , an output header processor  16  connected to those SW interfaces  14 - 1  and  14 - 2 , and an output frame buffer controller  17  connected to the output header processor  16 . Hereunder, the SW interfaces  14 - 1  and  14 - 2  will be described generically as the SW interface  14  in the common descriptions for them. Although two SW interfaces  14  are shown in  FIG. 5 , the NIF  10  may also include many more SW interfaces  14 . 
         [0092]    The SW interface  14 - i  corresponds to the input/output line interface  11 - i . Input frames received by the input/output line interface  11 - i  are transferred to the frame switching block  15  through the SW interface  14 - i . The output frame dispatched from the frame switching block  15  to the SW interface  14 - i  are sent to an output line through the input/output line interface  11 - i.    
         [0093]    In the example shown in  FIG. 5 , “i” is 1 or 2. For example, input frames received by the input/output line interface  11 - 1  are transferred to the frame switching block  15  through the SW interface  14 - 1 . The output frames dispatched from the frame switching block  15  to the SW interface  14 - 1  are sent to an output line through the input/output line interface  11 - 1 . On the other hand, the input frames received by the input/output line interface  11 - 2  are transferred to the frame switching block  15  through the SW interface  14 - 2 . The output frames dispatched from the frame switching block  15  to the SW interface  14 - 2  are sent to an output line through the input/output line interface  11 - 2 . Such way, the SW interface  14  and the input/output line interface  11  is related to each other at one-to-one correspondence. 
         [0094]    If frames sent from the terminal  70 - 1  arrive at the terminal  70 - n  through the packet transfer apparatuses  10 A and  10 N sequentially as shown in the example in  FIG. 1 , the output line connected to the packet transfer apparatus  10 A is assumed as the communication route  0  NW 0 . The output line connected to the packet transfer apparatus  10 N is a line led to the terminal  70 - n.    
         [0095]    For example, the packet transfer apparatus  10 A shown in  FIG. 1  includes at least three input/output line interfaces  11  and one of those interfaces  11  is connected to the terminal  70 - 1 , another is connected to the communication route  0  NW 0 , and still another is connected to the communication route  1  NW 1 . The input/output line interface  11  connected to the terminal  70 - 1  belongs to the NIF  10 , which is different from the NIF  10  of the two input/output line interfaces connected to the two communication routes  0  NW 0  and  1  NW 1 . Consequently, frames received by the packet transfer apparatus  10 A from the terminal  70 - 1  are received by one NIF  10  and transferred from the NIF  10  to another NIF  10  connected to the two communication routes  0  NW 0  and  1  NW 1  through the frame switching block  15 . The transferred frames are then sent from the input/output line interface of the NIF  10  connected to the two communication routes  0  NW 0  and  1  NW 1  to those two communication routes  0  NW 0  and  1  NW 1 . 
         [0096]    The input/output line interface  11 - i , upon receiving the frame  40  or  41  from an input line, adds an inner header  42  as shown in  FIG. 6  to the received frame. 
         [0097]    In the example shown in  FIG. 1 , the input line connected to the packet transfer apparatus  10 A is used to pass the frame  30  sent from the terminal  70 - 1 . The input line connected to the packet transfer apparatus  10 N is the communication route  0  NW 0 . 
         [0098]    The NIF  10  further includes an output frame buffer  18 , a setting register  19 , a header processing table  20 , a waiting time holding table  21 , a copying table  22 , a send sequence number (SN) table  23 , and a header conversion table  24 . The input frame buffer controller  13  includes an input frame buffer  136 . The setting register  19  and each buffer may be predetermined areas secured in the storage area provided in the NIF  10 . Each table may also be held in a predetermined area secured in the storage area provided in the NIF  10 . The setting register  19  and each table will be described later. 
         [0099]      FIG. 6  shows a configuration of the inner header  42  added by the input/output line interface  11  in the first embodiment of the present invention. 
         [0100]    The inner header  42  consists of fields of input port ID  421 , output network interface board identifier (NIF ID)  427 , output port ID  422 , flow ID  423 , sequence number SNnow  424 , copy bit  425 , and frame length  426 . Of those fields, the output NIF ID  427  and the output port ID  422  are used as inner routing information. The frame switching block  15  transfers input frames to a specified SW interface  14  of a specified NIF  10  according to those inner routing information. 
         [0101]    When the input/output line interface  11 - i  adds an inner header  42  to an input frame, the fields of output NIF ID  427 , output port ID  422 , flow ID  423 , sequence number SNnow  424 , and copy bit  425  are still blank. In those fields are set valid values by the input header processor  12 . 
         [0102]    The input header processor  12  sets necessary values in the fields of output NIF ID  427 , output port ID  422 , flow ID  423 , copy bit  425  in the inner header  42  of each input frame by referring to the header processing table  20  ( FIG. 7 ). Furthermore, the input header processor  12  analyzes the MAC header of each input frame. And if a value is set in the field of sequence number  415  of the received frame, the processor  12  sets the value of the sequence number  415  in the field of sequence number NSnow  424 . 
         [0103]      FIG. 7  shows a configuration of the header processing table  20  in the first embodiment of the present invention. 
         [0104]    The header processing table  20 , as shown in  FIGS. 7A and 7B , consists of two tables, that is, a header processing table  20 A and a header processing table  20 B. 
         [0105]    The header processing table  20 A includes table entries of MPLS label  202 , output NIF ID  208 , output ID  203 , flow ID  204 , source MAC address  205 , destination MAC address  206 , and copy flag  207 . The value in the VLAN ID  201  is used as a search key to make searches in this table. 
         [0106]    The source MAC address  205  is a MAC address added to an input/output line interface  11 - i  identified by the output port ID  203 . 
         [0107]    The destination MAC address  206  denotes the MAC address of a packet transfer apparatus assumed as a frame destination and connected through the above described input/output line interface  11 - i.    
         [0108]    The copy flag  207  denotes whether to send each input frame received from the terminal  70  to a plurality of routes (communication routes  0  NW 0  and  1  NW 1 ), that is, whether to make a copy of the frame. In the example shown in  FIG. 7 , the value ‘0’ set in the copy flag  207  denotes that there is no need to make a copy from the frame and ‘1’ denotes that a copy should be made from the frame. 
         [0109]    The header processing table  20 B includes table entries such as VLAN ID  201 , output NIF ID  208 , output port ID  203 , flow ID  204 , source MAC address  205 , and destination MAC address  206 . The value set in the field of MPLS label  202  is used as a search key to make searches in this table. 
         [0110]    The source MAC address  205  denotes the MAC address added to an input/output line interface  11 - i  identified by the output port ID  203 . It denotes the MAC address of a terminal assumed as the subject frame destination and connected through the above described input/output line interface  11 - i.    
         [0111]    If the frame  40  is received from the terminal  70  and it is formatted as shown in  FIG. 3 , the input frame processor  12  searches a table entry from the header processing table  20 A. The table entry includes a field of VLAN ID  201  that stores a value of VID (VID#) denoted by the VLAN tag  403  of the input frame. Then, the input header processor  12  adds a header newly to the input frame  40 . The header includes a value denoted by the searched table entry. As a result, the format of the input frame is converted as shown in  FIG. 4 . At this time, the inner header  42  added to the head of the input frame before the conversion is not converted; it is kept positioned as is. Concretely, the input header processor  12  sets the values of the MPLS label  202 , source MAC address  205 , and destination MAC address  206  denoted by the searched table entry, respectively in the fields of the MPLS header  414 , source MAC address  412 , and destination MAC address  411 . At this time, the input frame buffer controller  13  sets a valid value in the field of sequence number  415 , which has been blank. 
         [0112]    Furthermore, the input header processor  12  sets the values of the output NIF ID  208 , output port ID  203 , flow ID  204 , and copy flag  207  denoted by the table entry searched from the above header processing table  20 A in the fields of output NIF ID  427 , output port ID  422 , flow ID  423 , and copy flag  425  of the inner header  42 , respectively. Then, the input header processor  12  transfers the inner header  42  added input frame to the input frame buffer controller  13 . 
         [0113]    If the frame  41  is received from the communication route  0  NW 0  or  1  NW 1  and it is formatted as shown in  FIG. 4 , the input header processor  12  searches a table entry from the header processing table  20 B. The table entry includes the field of MPLS label  202  that stores a value of the MPLS (level #) denoted by the MPLS header  414  of the input frame. Then, the input header processor  12  rewrites the header of the input frame with the values denoted by the searched table entry. Concretely, the input header processor  12  sets the values of VLAN ID  201 , source MAC address  205 , and destination MAC address  206  denoted, respectively by the searched table entry in the fields of VLAN tag  403 , source MAC address  402 , and destination MAC address  401 . As a result, the format of the input frame is converted as shown in  FIG. 3 . 
         [0114]    Furthermore, the input header processor  12  adds the inner header  42  to the input frame formatted as shown in  FIG. 3 . Then, the input header processor  12  sets the values of output NIF ID  208 , output port ID  203 , flow ID  204 , and copy flag  207  denoted by the table entry searched from the above header processing table  20 B in the fields of output NIF ID  427 , output port ID  422 , flow ID  423 , and copy bit  425  in the inner header  42 , respectively. Furthermore, the input header processor  12  sets the value of the sequence number  415  of the received frame in the field of sequence number SNnow  424  of the inner header  42  and transfers the inner header  42  added input frame to the input frame buffer controller  13 . 
         [0115]    Next, a description will be made with reference to  FIG. 5  again. 
         [0116]    The input frame buffer controller  13 , upon receiving a frame from the input header processor  12 , stores the received frame in the input frame buffer  136  as an input frame according to the operation mode set in the setting register  19  set for each NIF  10 . The operation mode set in the setting register  19  and the processing to be executed according to the operation mode will be described later with reference to  FIG. 9 . The input frame buffer controller  13  then reads the frames accumulated in the input frame buffer  136  according to the operation mode set in the setting register  19  and dispatches each of those frames to the SW interface  14  corresponding to the input port ID  421  denoted by the inner header of the frame itself. 
         [0117]    The operation mode set in the setting register  19  depends on whether the input port of the subject NIF  10  (input/output line interface  11  that receives the subject frame) is connected to the terminal  70  or one of the communication routes  0  NW 0  and  1  NW 1 . The input frame buffer controller  13  refers to the operation mode upon changing its processing. 
         [0118]    If the input port is connected to the terminal  70 , the “terminal connected mode” is set as the operation mode in the setting register  19 . In this case, the input frame buffer controller  13  copies the input frame and sends the original input frame and its copy to a plurality of communication routes ( 0  NW 0  and  1  NW 1 ). 
         [0119]    On the other hand, if the input port is connected to the communication route  0  NW 0  or  1  NW 1 , “network connected mode” is set as the operation mode in the setting register  19 . In this case, the input frame buffer controller  13  checks the sequence number of each input frame. Upon detecting a frame loss, the input frame buffer controller  13  stops the frame sending temporarily and waits for the arrival of the frame having the same content as that of the frame lost in one communication route from the other communication route. After that, upon detecting an event of “restart frame sending”, the input frame buffer controller  13  restarts the frame sending, thereby restoring the normal operation. The details of the processing executed in each of the operation modes will be described later. 
         [0120]    As shown in the example shown in  FIG. 1 , if a terminal  70 - n  receives a frame from the terminal  70 - 1  through the packet transfer apparatus  10 A and communication route  0  NW 0  or through the communication route  1  NW 1  and packet transfer apparatus  10 N sequentially, the frame is inputted to the input/output line interface  11  (assumed as an input port) of the NIF  10  connected to the terminal  70 - 1  among the plurality of NIFs  10  of the packet transfer apparatus  10 A. Otherwise, the frame is inputted to the input/output line interface  11  (assumed as an input port) of the NIF  10  connected to the communication route  0  NW 0  among the plurality of NIFs  10  of the packet transfer apparatus  10 N. 
         [0121]    The frame switching block  15  receives frames from the SW interfaces  14 - 1  to  14 - 2  of each GIN  10  and transfers those frames to a SW interface  14 - i  of the NIF  10  identified by the output NIF ID  427  and the output port ID  422  set in the inner header of each input frame. 
         [0122]    Frames received by each SW interface  14  is transferred to the output header processor  16  sequentially. In this first embodiment, the input header processor  12  converts the format of each input frame to the format of each output frame by referring to the header processing table  20 . However, instead of the input header processor  12 , the output header processor  16  may refer to the header conversion table  24  to make the format conversion. In this case, the header conversion table  24  comes to hold information required for the header conversion (e.g., the same information as that held in the header processing table  20 ). In case where the input header processor  12  executes the format conversion, the output header processor  16  sends the frames received from the SW interface  14  to the output frame buffer controller  17  as are. The output frame buffer controller  17  then accumulates those received frames in the output frame buffer  18 . 
         [0123]    The output frame buffer controller  17  then reads those accumulated frames from the buffer  18  and transfers them to the input/output line interface  11  corresponding to the output port ID  422  set in the inner header  42  of each output frame. The input/output line interface  11  then removes the inner header  42  from each received frame and sends the frame formatted as shown in  FIG. 3  or  4  to an output line. 
         [0124]      FIG. 8  shows a block diagram of the input frame buffer controller  13  in the first embodiment of the present invention. 
         [0125]    The input frame buffer controller  13  consists of buffer controllers  131 - 1  to  131 - n , each corresponding to a flow ID, and a scheduling unit  132  connected to those buffer controllers  131 - 1  to  131 - n , and a frame dispatcher  133  connected to the buffer controllers  131 - 1  to  131 - n . Hereunder, those buffer controllers  131 - 1  to  131 - n  will be described as the buffer controller  131  generically in the common descriptions for them. 
         [0126]    In the example shown in  FIG. 1 , it is premised that only one flow passes through the subject network to simplify the description. Actually, however, the network shown in  FIG. 1  can process a plurality of flows. The input frame buffer controller  13  in this first embodiment, as shown in  FIG. 8 , includes a plurality of buffer controllers  131 , each of which is allocated to a flow so as to cope with the processings of a plurality of flows as a whole. Each buffer controller  131  corresponding to a flow ID processes only the frames of the corresponding flow. For example, the buffer controller  131 - 1  corresponding to the flow ID# 0  processes only the frames of the flow of which ID is ‘#0’. However, according to the present invention, one buffer controller  131  can cope with the processings of frames of a plurality of flows. 
         [0127]    Each buffer controller  131  includes a buffer write processor  134 , a buffer read processor  135 , and an input frame buffer  136 . 
         [0128]    Furthermore, each buffer controller  131  holds fields of frame storage flag  13 A, read counter  13 B, flow ID  13 C, residual frame counter  13 D, read timer  13 E, and write counter  13 F. Those fields may also be held in a storage area provided in the packet transfer apparatus  10 N, etc. 
         [0129]    The frame storage flag  13 A denotes whether or not a not-requested-yet frame is stored in the input frame buffer  136 . 
         [0130]    The read counter  13 B holds a value to be used as a read address of the input frame buffer  136 . 
         [0131]    The flow ID  13 C holds the identifier of a flow to be processed by each buffer controller  131 . The value is fixed to the subject hardware. For example, the value in the flow ID field  13 C held by the buffer controller  131 - 1  corresponding to the flow ID# 0 , which processes the flow identified by the flow ID ‘#0’, is ‘#0’. The flow ID  13 C may be held in a no-volatile memory area provided in the packet transfer apparatus  10 N, etc. 
         [0132]    The residual frame counter  13 D denotes the number of frames accumulated in the input frame buffer  136  and not requested yet for sending. 
         [0133]    The read timer  13 E, upon occurrence of a sequence number loss, measures a time required until the frame sending is restarted. 
         [0134]    The write counter  13 F holds a value to be used as an address of writing to the input frame buffer  136 . 
         [0135]    The buffer write processor  134 , upon receiving a frame from the input header processor  12 , refers to the flow ID  423  field in the inner header  42  of the received frame. If the flow ID  423  does not denote the identifier of the flow to which the self-buffer controller  131  is allocated, the buffer write processor  134  discards the received frame. If the flow ID  423  denotes the identifier of the flow to which the self-buffer controller  131  is allocated, the buffer write processor  134  executes the buffer write processing S 100  for the received frame according to the operation mode set in the setting register  19 . The buffer write processor  134  then stores the processed frame in the buffer  136 . The detail of these processings will be described later with reference to  FIG. 9 . 
         [0136]    For example, the buffer controller  131 - 1  corresponding to the flow ID# 0  is allocated to process the flow identified by the identifier ‘#0’. The buffer write processor  134  of the buffer controller corresponding to the flow ID# 0  refers to the flow ID  423  set in the received frame. If the value set in the flow ID  423  is ‘#0’, the identifier is the same as the identifier of the flow to which the self buffer controller  131  (the buffer controller  131 - 1  corresponding to the flow ID# 0 ) is allocated. In this case, the buffer write processor  134  executes the buffer write processing S 100  for the received frame and stores the processed frame in the buffer  136 . 
         [0137]    The buffer read processor  135  executes the processing of a send frame request S 400  according to the operation mode set in the setting register  19 . As a result, a send frame request that includes the ID information of the flow to which the self buffer controller  131  is allocated is sent to the scheduling unit  132 . The details of this processing will be described later with reference to  FIG. 13 . 
         [0138]    Upon receiving the send frame request from the buffer read processor  135 , the scheduling unit  132  stores the request once in the send request storage FIFO  137 . The scheduling unit  132  then reads the stored send frame request from the send request storage FIFO  137  according to its sequence number. The scheduling unit  132  then sends a send enabling signal to the flow ID buffer controller  131 , which is the source of the send frame request read from the FIFO  137 . 
         [0139]    The FIFO  137  is a memory area managed by the scheduling unit  132 . Just like the input frame buffer  136 , the FIFO  137  may be a predetermined area secured in the memory area provided in each NIF  10 . 
         [0140]    Upon receiving the send enabling signal, the buffer read processor  135  reads frames from the input frame buffer  136  and outputs those frames to the frame dispatcher  133 . 
         [0141]    The frame dispatcher  133 , upon receiving a frame from the buffer read processor  135 , refers to the input port ID  421  set in the inner header  42  and selects the SW interface  14  corresponding to the input port ID  421 , then transfers the frame to the selected SW interface  14 . For example, as shown in the example in  FIG. 5 , when the input/output line interface  11 - 1  corresponds to the SW interface  14 - 1 , if the value of the input port ID  421  set in the received frame is ‘port#0’ (the identifier of the input/output line interface  11 - 1 ), the frame dispatcher  133  transfers the frame to the SW interface  14 - 1  corresponding to the input/output line interface  11 - 1 . 
         [0142]      FIG. 9  shows a flowchart of a buffer write processing S 100  executed by the buffer write processor  134  in the first embodiment of the present invention. 
         [0143]    The buffer write processor  134 , upon receiving a frame from the input header processor  12 , obtains the values of the input port ID  421 , flow ID  423 , sequence number SNnow  424 , and frame length  426  from the inner header  42  of the received frame (S 101 ). 
         [0144]    The buffer write processor  134  then compares the obtained value of the flow ID  423  with that of the flow ID  13 C fixed to the hardware and held by the corresponding flow buffer controller  131  (S 102 ). 
         [0145]    As a result of the comparison in S 102 , if the two flow IDs are the same, the self buffer controller  131  (the buffer controller  131  related to the buffer write processor  134  that is executing the processing shown in  FIG. 9 ) is the one allocated to process the flow of the received frame. In this case, the buffer write processor  134  checks the operation mode set in the setting register  19  (S 103 ). 
         [0146]    Concretely, if ‘0’ is set in the setting register  19 , the buffer write processor  134  determines the operation mode as “terminal connected mode”. If ‘1’ is set in the setting register  19 , the buffer write processor  134  determines the operation mode as “network connected mode”. 
         [0147]    If the operation mode is determined as “network connected mode” in the check in S 103 , the buffer write processor  134  executes the sequence number check processing S 200  shown in  FIG. 10 , then exits the processing (S 104 ). On the other hand, if the operation mode is determined as “terminal connected mode”, the buffer write processor  134  executes the user data receiving processing S 300  shown in  FIG. 11 , then exits the buffer write processing (S 104 ). 
         [0148]    If the two flow IDs are the same in S 102 , it means that the self-buffer controller  131  is not allocated to process the flow of the received frame. In this case, the buffer write processor  134  exits the buffer write processing without fetching the received frame (S 104 ). In other words, in this case, the buffer write processor  134  does not execute any of the sequence number check processing S 200  and the user data receiving processing S 300  for the received frame. 
         [0149]      FIG. 10  shows a flowchart of the sequence number check processing S 200  executed by the buffer write processor  134  in the first embodiment of the present invention. 
         [0150]    The processing S 200  is executed as follows. At first, upon starting the sequence number check processing S 200 , the buffer write processor  134  compares the sequence number SNnow  424  obtained from the inner header  42  of the received frame with the value of the read counter  13 B held by the buffer controller  131  (S 201 ). 
         [0151]    The read counter  13 B denotes the read address of the input frame buffer  136 . More concretely, the read counter  13 B denotes the address of the input frame buffer  136 , in which the frame to be requested next for sending (refer to S 505  shown in  FIG. 14 ) is stored. In other words, the read counter  13 B denotes the next address to be read among those of the input frame buffer that stored the last requested frame. 
         [0152]    The buffer write processor  134  uses the sequence number SNnow  424  as the address of writing to the input frame buffer  136 . Consequently, comparison between the above read counter  13 B and the sequence number SNnow  424  enables determination to be made on whether or not sending of the frame having the same content as that of the received frame or its subsequent frame is already requested. A frame having the same content as that of the received frame means a frame having the same sequence number of that of the received frame. Its subsequent frame means a frame having a sequence number larger than that of the received frame. 
         [0153]    If the value of the sequence number SNnow  424  is larger than the value of the read counter  13 B as a result of the comparison in S 201 , it means that it is not requested yet to send the frame having the same content as that of the received frame or its subsequent frame. In this case, it might be requested to send the received frame later. Consequently, if the frame having the same content as that of the received frame is not stored in the frame buffer  136 , the received frame should be stored in the frame buffer  136 . The buffer write processor  134  thus reads an object frame from the input frame buffer  136  according to the value set in the sequence number SNnow field  424  of the received frame, which is used as the read address (S 202 ). 
         [0154]      FIG. 12  shows a configuration of the input frame buffer  136  in the first embodiment of the present invention. 
         [0155]    In the input frame buffer  136  shown in  FIG. 12  are held a communication route  0  receive bit  1362  that denotes whether or not a frame is received from the communication route  0  NW 0 ; communication route  1  receive bit  1363  that denotes whether or not a frame is received from the communication route  1 ; and frame data  1364  with respect to each address  1361 . The value of the address  1361  corresponds to the value of the sequence number SNnow  424 . 
         [0156]    In the example shown in  FIG. 12 , the value ‘1’ in the communication route  0  receive bit  1362  means that a frame is received from the communication route  0  NW 0 . The value ‘1’ in the communication route  1  receive bit  1363  means that a frame is received from the communication route  1  NW 1 . For example, ‘1’ and ‘0’ are set in the receive bits  1362  and  1363  of the communication routes  0  and  1  corresponding to the value ‘6’ of the address  1361  shown in  FIG. 12 , respectively. This means that the packet transfer apparatus that includes the input frame buffer  136  shown in  FIG. 12  has already received a frame in which ‘6’ is set in its sequence number SNnow field  424  from the communication route  0  NW 0  and has not received the frame yet from the communication route  1  NW 1 . In this case, in the DATA 6 field of the frame data  1364  is stored the content of the frame received from the communication route  0  NW 0 . 
         [0157]    Instead of storing the data itself, which is the content of each frame in the frame data  1364 , it is also possible to store the pointer denoting the data stored position in the frame data  1364  and store the data itself in another frame buffer. 
         [0158]    Next, there will be described the processings in and after S 202  with reference to  FIG. 10  again. 
         [0159]    In S 202 , the buffer write processor  134  reads the values from the fields of the receive bits  1362  and  1363  of the communication routes  0  and  1 , as well as the frame data  1364  according to the sequence number SNnow  424  of the received frame. The values in the fields of the receive bits  1362  and  1363  correspond to the value of the address  1361 . 
         [0160]    The buffer write processor  134  then checks whether or not ‘1’ is set at least in either of the fields of communication route  0  receive bit  1362  and communication route  1  receive bit  1363  (S 203 ). 
         [0161]    In S 203 , if ‘0’ is set in both of the fields of the receive bits  1362  and  1363 , the packet transfer apparatus has not received the frame having the same content as that of the received frame from any of the communication routes  0  and  1  before receiving the currently received frame. For example, in the example shown in  FIG. 2 , if the packet transfer apparatus  10 N has received the SN:1 frame  301 , it means that the packet transfer apparatus  10 N has not received the SN:1 frame before the frame  301 , so that it is determined in S 203  that ‘0’ is set in both of the receive bits  1362  and  1363 . 
         [0162]    In this case, the buffer write processor  134  sets ‘1’ in the field of communication route  0  receive bit  1362  or communication route  1  receive bit  1363  corresponding to the input port ID  421  obtained from the inner header  42  of the received frame and stores the received frame together with the inner header  42  in the field of the frame data  1364  (S 204 ). Concretely, if the frame is received from the communication route  0  NW 0 , the processor  134  sets ‘0’ in the receive bit  1362  and if the frame is received from the communication route  1  NW 1 , the processor  134  sets ‘1’ in the receive bit  1363 . 
         [0163]    After this, the buffer write processor  134  sets ‘1’ in the frame storage flag  13 A held in the buffer controller  131  (S 202 ), then exits the processing (S 207 ). This frame storage flag  13 A denotes whether or not a frame that is not requested yet for sending is stored in the input frame buffer  136 . In this embodiment, the value ‘1’ set in the frame storage flag  13 A means that such a frame is already stored in the input frame buffer  136 . 
         [0164]    On the other hand, if ‘1’ is set in any one of the receive bits  1362  or  1363  in S 203 , it means that the packet transfer apparatus  10 N has already received a frame having the same content as that of the currently received frame from a communication route before receiving the currently received frame. For example, in the example shown in  FIG. 2 , if the packet transfer apparatus  10 N receives the SN:1 frame  311 , it means that the packet transfer apparatus  10 N has already received the SN:1 frame  301  in prior to the frame  311 . Thus it is determined in S 203  that ‘1’ is set in any of the receive bits  1362  or  1363  (concretely, ‘1’ is set in the communication route  0  receive bit  1362 ). 
         [0165]    In this case, a frame having the same content as that of the currently received frame is already stored in the input frame buffer  136 . Consequently, the buffer write processor  134  does not update the value in the frame data  1364  (this means that the processor  134  writes back the content of the frame data field  1364  read in S 202  in the input frame buffer  136  as is) and sets ‘1’ in the receive bit corresponding to the input port ID (S 206 ), then exits the sequence number check processing (S 207 ). 
         [0166]    If the value set in the sequence number SNnow field  424  is smaller than the value set in the read counter  13 B as a result of the comparison in S 201 , sending of a frame having the same content as that of the received frame or its subsequent frame is already requested. In other words, the buffer write processor  134  is not required to store the received frame in the input frame buffer  136  at that time. Consequently, the buffer write processor  134  discards the received frame and exits the sequence number check processing (S 207 ). 
         [0167]      FIG. 11  shows a flowchart of a user data receiving processing S 300  executed by the buffer write processor  134  in the first embodiment of the present invention. 
         [0168]    The processing S 300  is executed as follows. Upon starting the user data receiving S 300  shown in  FIG. 11 , the buffer write processor  134  sets ‘1’ in the communication route  0  receive bit  1362  and in the communication route  1  receive bit  1363 , respectively according to the write address, which is the value set in the write counter  13 F, then stores the received frame including the inner header  42  in the frame data field  1364  (S 301 ). 
         [0169]    After this, the buffer write processor  134  counts up the value in the write counter  13 F by one and sets ‘1’ in the frame storage flag  1 A (S 302 ), then exists the user data receiving processing (S 303 ). 
         [0170]    The write counter  13 F holds a value used as an address of writing to the input frame buffer  136  and it is used only for the user data receiving processing S 300 . 
         [0171]      FIG. 13  shows a flowchart of a send frame request processing executed by the buffer read processor  135  in the first embodiment of the present invention. 
         [0172]    The buffer read processor  135 , upon detecting a status change of the frame storage flag  13 A from ‘0’ to ‘1’, checks the operation mode set in the setting register  19  (S 401 ). If the operation mode is “network connected mode”, the buffer read processor  135  executes a processing of requesting to send frames in the order of sequence numbers S 500  shown in  FIGS. 14 and 15 , then exits the send frame request processing (S 402 ). On the other hand, if the operation mode set in the setting register  19  is “terminal connected mode”, the buffer read processor  135  executes the send user data request processing S 600  and exits the send frame request processing (S 402 ). 
         [0173]      FIGS. 14 and 15  show flowcharts of the processing of requesting to send frames in the order of sequence numbers S 500  executed by the buffer read processor  135  in the first embodiment of the present invention. 
         [0174]    The processing S 500  is executed as follows. At first, upon starting the processing of requesting to send frames in the order of sequence numbers S 500  shown in  FIGS. 14 and 15 , the buffer read processor  135  clears the frame storage flag  13 A (reset to ‘0’) (S 501 ). 
         [0175]    After that, the buffer read processor  135  reads the object frame from the frame buffer  136  according to the read address that is the value set in the read counter  13 B (S 502 ). In parallel to the processing in S 502 , the buffer read processor  135  makes a search in the waiting time holding table  21  shown in  FIG. 17  according to the flow ID  13 C used as the search key (S 503 ). 
         [0176]    Although S 502  and S 503  are executed simultaneously in the example shown in  FIG. 14 , it is also possible to execute S 502  first, then S 503  or execute S 503  first, then S 502 . 
         [0177]      FIG. 17  shows a configuration of the waiting time holding table  21  in the first embodiment of the present invention. 
         [0178]    In this embodiment, the waiting time holding table  21  includes a field of delay difference between both of the communication routes  0  NW 0  and  1  NW 1  with respect to each flow ID  211 . This delay difference  212  denotes a delay time difference between communication routes, measured at the time of setting a communication route  2  with respect to each flow and it is set by the subject network manager. 
         [0179]    For example, if S 503  is executed by the buffer read processor  135  of the buffer controller  131 - 1  corresponding to the flow ID# 0 , the value ‘Ddif0’ of the delay difference  212  is obtained in S 503 . The ‘Ddif0’ corresponds to ‘0’ set in the flow ID  211 . 
         [0180]    Next, there will be described processings to be executed after S 502  and S 503  with reference to  FIG. 14  again. 
         [0181]    After executing the processings in S 502  and  503 , the buffer read processor  135  checks the receive bits  1362  and  1363  of the communication routes  0  and  1 , set in the frame read from the input frame buffer  136  in S 502  (S 504 ). If ‘1’ is held in any one of the receive bits  1362  and  1363 , the object frame is stored in the address denoted by the value set in the read counter  13 B in the input frame buffer  136  (this means that a frame having the same sequence number as the value set in the read counter  13 B is already received). In this case, the buffer read processor  135  sends a send frame request together with the flow ID  13 C and the value of the read counter  13 B to the scheduling unit  132  (S 505 ). 
         [0182]    After this, the buffer read processor  135  counts up the value in the read counter  13 B by one (S 506 ). 
         [0183]    The buffer read processor  135  then checks whether or not all ‘0’ is set in the residual frame counter  13 D (S 507 ). The residual frame counter  13 D denotes the number of frames stored in the input frame buffer  136 , but not requested yet for sending when frame sending stops temporarily. 
         [0184]    If the value in the residual frame counter  13 D is determined to be all ‘0’ in the check in S 507 , it means that there is no frame requested for sending in the input frame buffer  136 . In this case, the buffer read processor  135  exits the processing for requesting to send frames in the order of sequence numbers (S 509 ). 
         [0185]    On the other hand, if all ‘0’ is not set in the residual frame counter  13 D in S 507 , it means that there is no frame requested for sending in the input frame buffer  136 . In this case, the buffer read processor  135  counts down the value in the residual frame counter  13 D by one (S 508 ). This is because the number of frames stored in the input frame buffer  136  and not requested yet for sending is reduced by one as a result of the processing executed in S 505 . 
         [0186]    After this, the residual frame counter  13 D executes the processings in S 502  and S 503 , as well as their subsequent processings again. 
         [0187]    On the other hand, if ‘0’ is set in both of the receive bits  1362  and  1363  in S 504 , the buffer read processor  135  determines it as a sequence number loss. In other words, in  FIG. 2 , if the SN:2 frame  302  is lost and the packet transfer apparatus  10 N receives the SN:3 frame  303  before receiving the SN:2 frame  312 , the buffer read processor  135  determines in S 504  that ‘0’ is set in both of the receive bits  1362  and  1363 . 
         [0188]    In this case, the buffer read processor  135  stops the frame sending until receiving a frame having the same content as that of the lost frame from the other communication route  0  NW 0 / 1  NW 1 . However, if the buffer read processor  135  cannot receive the frame having the same content as that of the lost frame from the other communication route within a predetermined time (the value set in the delay difference  212  obtained in S 503 ), the buffer read processor  135  determines that two frames having the same content are lost in both of the two communication routes  0  NW 0  and  1  NW 1 , then restarts sending of frames. Consequently, the buffer read processor  135  sets the value of the delay difference  212  obtained in S 503  for the read timer  13 E and begins the timer  13 E count-down (S 510 ). This read timer  13 E is used to measure the waiting time required until the restart of frame sending. The value set in the read timer  13 E is reduced with time after the count-down begins and becomes ‘0’ finally. 
         [0189]    After this, the buffer read processor  135  checks whether or not all ‘0’ is set in the read timer  13 E (S 511 ). 
         [0190]    If all ‘0’ is not set in the read timer  13 E, it means that the waiting time does not expire yet. In this case, the buffer read processor  135  checks whether or not ‘1’ is set in the frame storage flag  13 A (S 512 ). If ‘1’ is set in the flag  13 A, it means that a frame is received before the read timer  13 E expires (the waiting time expires). In this case, the buffer read processor  135  reads the frame from the input frame buffer according to the value in the red counter  13 B used as the read address (S 513 ), then checks whether or not ‘1’ is set either in the communication route  0  receive bit  1362  or in the communication route  1  receive bit  1363  (S 514 ). 
         [0191]    If ‘1’ is set in at least one of the receive bits  1362  and  1363 , it means that the frame having the lost sequence number has arrived. In this case, the buffer read processor  135  clears the frame storage flag  13 A (S 520 ). The buffer read processor  135  then executes the processings in and after S 505  to create a send sequence number request with respect to the arrived frame. 
         [0192]    If ‘0’ is set in both of the receive bits  1362  and  1363  in S 514 , it means that the frame that has arrived does not have the lost sequence number. In this case, the buffer read processor  135  reads a frame from the input frame buffer  136  (S 515 ) according to the read address, which is a value obtained by adding ‘1’ to the value in the read counter  13 B, then checks whether or not the frame having the next sequence number of the lost one has been received from both of the communication routes  0  NW 0  and  1  NW 1 . Then, the buffer read processor  135  checks whether or not ‘1’ is set in both of the receive bits  1362  and  1363  (S 516 ). 
         [0193]    If ‘1’ is set in both of the receive bits  1362  and  1363 , it means that the frame having the lost sequence number has been lost in the two communication routes  0  NW 0  and  1  NW 1 . In this case, the buffer read processor  135  counts up the value in the read counter  13 B by one (S 519 ). The buffer read processor  135  then executes the processings in and after S 520  to create a send frame request with respect to the frame having the next sequence number of the lost one. 
         [0194]    If ‘0’ is set in at least one of the receive bits  1362  and  1363  in the check carried out in S 516 , the buffer read processor  135  is required to continuously wait for the arrival of the frame having the lost sequence number. Consequently, the buffer read processor  135  clears the frame storage flag  13 A (S 517 ) and counts up the value in the residual frame counter  13 D by one, then executes the processings in and after S 511 . 
         [0195]    If all ‘0’ is set in the read timer  13 E in S 511 , the buffer read processor  135  determines that the frame having the lost sequence number has been lost in the two communication routes NW 0  and NW 1 . In this case, the buffer read processor  135  executes the processings in and after S 506  to create a send frame request with respect to a frame having the next sequence number of the lost one. Thus the frame sending is restarted to send the frame having the next sequence number of the lost one. 
         [0196]    If ‘0’ is set in the frame storage flag in S 512 , the buffer read processor is required to continuously wait for the arrival of the frame having the lost sequence number. Thus the buffer read processor  135  executes the processings in and after S 511 . 
         [0197]    For example, in  FIG. 2 , if the SN:2 frame  302  is lost and the packet transfer apparatus  10 N receives the SN:2 frame  312  after receiving the SN:3 frame  303  and before the time of the delay difference  81  expires, the buffer read processor  135  determines in S 511  that all ‘0’ is not set in the read timer  13 E, and in S 512  that ‘1’ is set in the frame storage flag  13 A. Furthermore, the buffer read processor  135  also determines in S 514  that ‘1’ is set in the receive bit  1363  of the communication route  1 . 
         [0198]    In the example shown in  FIG. 2 , if the SN:2 frame  312  is lost and the packet transfer apparatus  10 N receives the SN:3 frame  313  before the time of the delay difference  81  expires, it is determined in S 511  that all ‘0’ is not set in the read timer  13 E. And it is also determined in S 512  that ‘1’ is set in the frame storage flag  13 A. Furthermore, it is determined in S 514  that ‘0’ is set in the receive bits  1362  and  1363  of both of the communication routes  0  and  1 . Furthermore, it is determined in S 516  that ‘1’ is set in both the receive bits  1362  and  1363  of both of the communication routes  0  and  1 . 
         [0199]    In the example shown in  FIG. 2 , if the time of the delay difference  81  expires before the packet transfer apparatus  10 N does not receive any of the SN:2 frame  312  and the SN:3 frame  313 , it is determined in S 511  that all ‘0’ is set in the read timer  13 E. 
         [0200]      FIG. 16  shows a flowchart of a send user data request processing S 600  executed by the buffer read processor  135  in the first embodiment of the present invention. 
         [0201]    The processing S 600  is executed as follows. At first, upon starting the send user data request processing S 600  shown in  FIG. 16 , the buffer read processor  135  clears the frame storage flag  13 A (S 601 ). 
         [0202]    After this, the buffer read processor  135  sends a send frame request to the scheduling unit  132  together with the values in the flow ID  13 C and in the read counter  13 B (S 602 ). 
         [0203]    Then, the buffer read processor  135  counts up the value in the read counter  13 B by one (S 603 ), then exits the processing (S 604 ). 
         [0204]    As described above, the send user data request processing S 600  is completed when the user data receiving processing S 300  reads frames from the input frame buffer  136  sequentially in the order of addresses. 
         [0205]    Although not shown in the flowchart in  FIG. 16 , the scheduling unit  132 , upon receiving the above send user data request from the buffer read processor  135 , stores the received request in the send request storage FIFO  137  together with the flow ID and the read counter value notified simultaneously, then multiplexes the send request received from the subject flow ID buffer controller  131 . Then, the scheduling unit  132  reads the send requests one by one from the send request storage FIFO  137  to notify the send enable and the read counter value to each buffer controller  131 - i  corresponding to each flow ID read from the FIFO  137 . 
         [0206]      FIG. 18  shows a flowchart of a frame sending processing S 700  executed by the buffer read processor  135  in the first embodiment of the present invention. 
         [0207]    At first, upon receiving a send enabling signal from the scheduling unit  132 , the buffer read processor  135  obtains the read counter value sent together with this send enabling signal (S 701 ). 
         [0208]    Then, the buffer read processor  135  reads the object frame from the input frame buffer  136  according to the obtained read counter value used as the read address. After that, the buffer read processor  135  overwrites all ‘0’ in the entry of the address (S 702 ). 
         [0209]    Then, the buffer read processor  135  checks the operation mode set in the setting register (S 703 ). 
         [0210]    If the operation mode is determined to be “network connected mode” in S 703 , the frame read in S 702  is required to be sent to another packet transfer apparatus through at least one of the communication routes  0  NW 0  and  1  NW 1 . In this case, the buffer read processor  135  checks the copy bit  425  set in the inner header  42  (S 704 ). 
         [0211]    If ‘0’ is set in the copy bit  425  in S 704 , it means that there is no need to copy the read frame. Consequently, the buffer read processor  135  sends the frame data  1364  read from the input frame buffer  136  just by the frame length  426  set in the inner header  42  (S 705 ). 
         [0212]    The buffer read processor  135  then notifies the scheduling unit  132  of the completion of the sending (S 708 ), then exits the frame sending processing (S 709 ). 
         [0213]    On the other hand, if ‘1’ is set in the copy bit  425  of the inner header  42  in S 704 , it means that it is required to copy the read frame. Thus the buffer read processor  135  makes a search in the copying table  22  shown in  FIG. 19  according to the flow ID  13 C used as the search key (S 706 ). As a result, the buffer read processor  135  obtains the object header information to be added to the copied frame. 
         [0214]      FIG. 19  shows a configuration of the copying table  22  in the first embodiment of the present invention. 
         [0215]    The copying table  22  holds header information to be added to each copied frame. In other words, the copying table  22  is used to search table entries denoting the MPLS label  222 , output NIF ID  223 , output port ID  224 , source MAC address, and destination MAC address  226  according to the flow ID  221  used as the search key. Here, the source MAC address  225  is added to an input/output line interface  11 - i  identified by the value set in the output port ID  224 . The destination MAC address  226  is added to a packet transfer apparatus connected to the input/output line interface  11 - i  and assumed as a destination of a frame. 
         [0216]    Next, there will be described a processing that follows that in S 706  with reference to  FIG. 18  again. 
         [0217]    Upon obtaining the header information to be added to a copy of a frame in S 706 , the buffer read processor  135  sends the subject frame just like in the frame sending processing in S 705  and copies the frame, then sends the copy of the frame (S 707 ). 
         [0218]    Concretely, the buffer read processor  135  sends the subject frame just like in the frame sending processing in S 705 . Furthermore, the buffer read processor  135  copies the frame to be sent. The buffer read processor  135  then overwrites the destination MAC address  226 , source MAC address  225 , and MPLS label  222  obtained, respectively from the copying table in S 706  on the destination MAC address  411 , source MAC address  412 , and MPLS header  414  set, respectively in the MAC header of the copy frame. Furthermore, the buffer read processor  135  overwrites the output ID  223  and the output port ID  224  obtained from the copying table in S 706  on the output NIF ID  427  and output port ID  422  set in the inner header  42  of the copy frame. Furthermore, the buffer read processor  135  inverts the input port ID  421  of the frame copy. Then, the buffer read processor  135  sends the frame portion read in accordance with the frame length  426  set in the inner header  42 . 
         [0219]    The reason why the input port ID  421  is inverted in S 707  is that the frame copy is required to be sent to the other communication route that is not used by the original frame. The frame dispatcher  133  sends each frame to the SW interface  14  corresponding to the input port ID  421 . Consequently, if the buffer read processor  135  changes the input port ID  421  in S 707 , the frame dispatcher  133  dispatches frame copies to the other (empty) port. 
         [0220]    After this, the buffer read processor  135  notifies the scheduling unit  132  of the completion of sending (S 708 ), then exits the frame sending processing (S 709 ). 
         [0221]    If “terminal connected mode” is set in the setting register in S 703 , the buffer read processor  135  makes a search in the sending SN table  23  shown in  FIG. 20  according to the flow ID  13 C used as the search key (S 710 ). 
         [0222]      FIG. 20  shows a configuration of the sending SN table  23  in the first embodiment of the present invention. 
         [0223]    The sending SN table shown in  FIG. 20  holds send sequence numbers  232  added to the sequence number field  415  of each frame to be sent and searched according to the flow ID  231  used as the search key. In other words, the field of the sequence number  232  holds a sequence number to be added to a frame to be sent next in each flow. The buffer read processor  135  executes the processing in S 710  to obtain the sequence number to be added to the next object frame to be sent. 
         [0224]    After executing the processing in S 710 , the buffer read processor  135  overwrites the sequence number  232  obtained from the send SN table on the field of the sequence number  415  in the frame (S 711 ). Then, the buffer read processor  135  writes back an obtained value in the entry in the send SN table  23  (S 712 ). The value is obtained by adding ‘1’ to the sequence number  232  obtained from the table. 
         [0225]    The buffer read processor  135  then executes the processings in and after S 704  that checks the copy bit  425  in the inner header  42  to send the sequence number overwritten frame. 
         [0226]    As described above, the packet transfer apparatus in the first embodiment of the present invention, if a frame is lost in one communication route, waits for the frame having the same content as that of the lost one from the other communication route. If it is possible to receive a frame having the same content as that of the lost one such way, frame losses will be prevented by transferring such an alternative frame. Furthermore, the packet transfer apparatus in the first embodiment of the present invention restarts transfer of frames subsequent to the lost frame according to predetermined conditions even when not receiving any alternative frame having the same content as that of the frame lost in one communication route from the other communication route. Consequently, the packet transfer apparatus in the first embodiment of the present invention can prevent a case in which frame transfer is disabled even while holding frames that can be transferred. 
         [0227]    Next, there will be described a second embodiment of the present invention. 
         [0228]      FIG. 21  shows a diagram that describes an operation of a packet transfer apparatus LON in the second embodiment of the present invention. 
         [0229]    In  FIG. 21 , there are only two differences from  FIG. 2 ; how the packet transfer apparatus  10 N sets a waiting time for a frame having the same sequence number as that of a lost frame and what value is to be set for the waiting time. Hereunder, there will be described only those differences between  FIG. 21  and  FIG. 2 . In the description to be made with reference to  FIG. 21 , the same portions as those of  FIG. 2  will thus be omitted. 
         [0230]    In  FIG. 21 , the packet transfer apparatus  10 N sets a delay difference  81  and an average frame time interval (an average value of frame time intervals)  82  for the timer (refer to  FIG. 23 ) each time it receives a frame having a sequence number (SN) that has not received yet from any of the communication routes  0  and  1 , then begins count-down of the timer. The average frame time interval  82  is an average value of the time intervals for receiving frames in each flow checked by the packet transfer apparatus  10 N. 
         [0231]    Usually, if there is no frame loss detected, the timer is updated each time a frame is received and the received frame is sent out immediately. However, if a frame is lost (e.g., the SN:2 frame  302  to be received from the communication route  0  NW 0 ) and its sequence number loss is detected, the packet transfer apparatus  10 N stops the frame sending temporarily without updating the timer. Then, when the timer is reset to ‘0’ or the SN:2 frame  312  that is lost in one communication route is received from the other communication route, or when the SN:3 frame is received from both of the routes, the packet transfer apparatus  10 N restarts the frame sending. 
         [0232]    Concretely, the packet transfer apparatus  10 N, if receiving the SN:3 frame  303  in prior to the SN:2 frame  302 , determines that the frame  302  is lost in the communication route  0  NW 0 . And if receiving the SN:2 frame having the same content as that of the lost frame from the communication route  1  NW 1  before the timer is reset to ‘0’, the packet transfer apparatus  10 N sends the frame  312  to the destination. Furthermore, if receiving the SN:3 frame  313  from the communication route  1  NW 1  before the timer is reset to ‘0’ or before receiving the SN2: frame  312 , the packet transfer apparatus  10 N sends the SN:3 frame  303  or frame  313  to the destination. 
         [0233]    Then, if the timer is reset to ‘0’ before receiving the SN:2 frame  312  or SN:3 frame  313 , the packet transfer apparatus  10 N sends the SN:3 frame  303  to the destination. 
         [0234]      FIG. 22  is a diagram that describes a variation of the operation of the packet transfer apparatus  10 N in the second embodiment of the present invention. 
         [0235]    In  FIG. 22 , instead of the average frame time interval  82 , the maximum value of the frame time interval  83  is set for the timer. Other items in  FIG. 22  are the same as those shown in  FIG. 21 . In other words, the maximum value of the frame time interval  83  described above means the maximum value of the frame receiving time interval of each flow checked by the packet transfer apparatus  10 N. 
         [0236]    The method shown in  FIG. 21  is suitable for a mixed network in which the TDM emulation or VoIP traffic with less frame jittering exists together with the streaming traffic that has made bandwidth adjustment with use of a traffic shaper at the inlet of the subject network. 
         [0237]    On the other hand, the method shown in  FIG. 22  can also cope with the traffics having extremely large frame jittering, although the method is required not to set such a period as a break of a stream, in which no traffic arrives, as the maximum frame time interval  83 . This is why each packet transfer apparatus may have its own maximum value and the maximum value may be limited only within a certain multiple of the current maximum. 
         [0238]    As described above, the methods shown in  FIGS. 21 and 22  can be adjusted to the characteristics of the traffic of each flow, thereby the present invention can apply to any cases in which different characteristic traffics are mixed. 
         [0239]    According to the methods shown in  FIGS. 21 and 22 , just like in  FIG. 2 , if the SN:3 frame  313  is lost in the communication route  1  NW 1  and a line error occurs in one communication route, frame loss can be prevented without stopping the frame sending completely. 
         [0240]    Furthermore, according to the method shown in  FIG. 2 , the packet transfer apparatus is required to wait for a frame just by a fixed delay time set in the table. Consequently, the packet transfer apparatus cannot cope with delay changes to be caused by the actual usage or setting of the network. According to the method shown in  FIGS. 21 and 22 , however, the traffics in the past are reflected on the frame waiting time. Thus the method can cope with the above described changes in the usage of the network automatically. 
         [0241]    The configuration of the packet transfer apparatus  10 N in this second embodiment is the same as that shown in  FIG. 5  in the first embodiment. The configuration and functions of only the input frame buffer controller  13  differs from those in the first embodiment. Hereunder, therefore, there will be described only those differences from the first embodiment.  FIG. 23  shows a block diagram of a configuration of the input frame buffer controller  13  in this second embodiment of the present invention. 
         [0242]    The input frame buffer controller  13  includes buffer controllers  1301  ( 1301 - 1  to  1301 - n ) corresponding to flow IDs, respectively, a scheduling unit  132  connected to those buffer controllers  1301 , and a frame dispatcher  133  connected to those buffer controllers  1301 . 
         [0243]    The buffer controller  1301  includes a buffer write processor  1304 , a buffer read processor  1305 , and an input frame buffer  136 . 
         [0244]    Furthermore, the buffer controller  1301  holds a frame storage flag  130 A, a read counter  130 B, a flow ID  130 C, a residual frame counter  130 D, a read timer  130 E, a write counter  130 F, a sending stop flag  130 G, a sending stop sequence number (SN)  130 H, and a time counter  130 J. 
         [0245]    The frame storage flag  130 A, read counter  130 B, flow ID  130 C, residual frame counter  130 D, read timer  130 E and write counter  130 F are all the same as those in the first embodiment. 
         [0246]    The sending stop flag  130 G is set when frame sending stops. 
         [0247]    The sending stop SN  130 H holds a sequence number just in prior to a lost sequence number (the sequence number of the last frame sent out just before the sending stops). 
         [0248]    The time counter  130 J holds the current time. 
         [0249]    The configuration of the input frame buffer  136  is the same as that in the first embodiment (refer to  FIG. 12 ). 
         [0250]    The buffer write processor  1304 , upon receiving a frame from the input header processor  12 , refers to the flow ID  423  set in the inner header  42  of the received frame. If the flow ID  423  differs from the identifier of the flow to which the self buffer controller  1301  is allocated, the buffer write processor  1304  discards the received frame. If the flow ID  423  is the same as the identifier of the flow to which the self buffer controller  1301  is allocated, the buffer write processor  1304  executes the buffer write processing S 100  for the received frame according to the operation mode set in the setting register  19 . As a result, the received buffer is stored according to the sequence number in the buffer  136 . 
         [0251]    The buffer read processor  1305  executes the send frame request processing S 400  according to the operation mode set in the setting register  19 . As a result, the send frame request including the ID information of the flow to which the self buffer controller  1301  is allocated is sent to the scheduling unit  132 . 
         [0252]    Upon receiving the above send frame request, the scheduling unit  132  stores the request once in the request storage FIFO  137 . The scheduling unit  132  reads the requests stored in the request storage FIFO  137  sequentially as needed. Then, the scheduling unit  132  sends a send enabling signal to the request source buffer controller  1301 . 
         [0253]    Upon receiving the send enabling signal, the buffer read processor  1305  reads the requested frame from the input frame buffer  136  and outputs the frame to the frame dispatcher  133 . 
         [0254]    Upon receiving the frame from the buffer read processor  1305 , the frame dispatcher  133  refers to the input port ID  421  set in the inner header  42  of the received frame to select a SW interface  14  corresponding to the input port ID  421 , then transfers the frame to the selected SW interface  14 . 
         [0255]    The relationship between the input/output line interface and the SW interface  14  is the same as that in the first embodiment (refer to the description with reference to  FIG. 5 ). 
         [0256]    The buffer write processor  1304  in this second embodiment executes the buffer write processing  5100  shown in  FIG. 9  just like the buffer write processor  134  in the first embodiment. However, the buffer write processor  1304  in this second embodiment executes the sequence number check processing S 800  shown in  FIG. 24  instead of the sequence number check processing S 200 . 
         [0257]      FIG. 24  shows a flowchart of the sequence number check processing S 800  executed by the buffer write processor  1304  in this second embodiment of the present invention. 
         [0258]    Upon starting the sequence number check processing S 800  shown in  FIG. 24 , the buffer write processor  1304  compares the sequence number SNnow  424  obtained from the inner header  42  of the received frame with the value set in the read counter  130 B held by the buffer controller  131  (S 801 ). The read counter  130 B denotes a read address of the input frame buffer  136 . 
         [0259]    The buffer write processor  1304  uses the sequence number SNnow  424  as an address of writing to the input frame buffer  136 . This is why the buffer write processor is enabled to determine whether or not a frame having the same content as that of the received frame is already requested for sending by comparing the value set in the read counter  130 B with the sequence number SNnow  424 . 
         [0260]    As a result of the comparison in S 801 , if the value of the sequence number SNnow  424  is over the value set in the read counter  130 B, it means that the frame having the same content as that of the received frame is not requested yet for sending. In other words, the frame having the same content as that of the received frame might not be stored yet in the input frame buffer  136 . In this case, the buffer write processor  1304  reads the input frame buffer  136  shown in  FIG. 12  according to the read address that is the value of the sequence number SNnow  424  of the received frame (S 802 ). This reading procedure is the same as that in S 202  shown in  FIG. 10 . 
         [0261]    After this, the buffer write processor  1304  checks whether or not ‘1’ is set in at least one of the receive bits  1362  and  1363  read above (S 803 ). 
         [0262]    If ‘0’ is set in both of the receive bits  1362  and  1363  in S 803 , the buffer write processor  1304  sets ‘1’ in the receive bit  1362  or  1363  corresponding to the input port ID  421  obtained from the inner header  42  of the received frame, then stores the received frame in the frame data  1364  together with its inner header  42  (S 804 ). 
         [0263]    After this, the buffer write processor  1304  sets ‘1’ in the frame storage flag  130 A held in the buffer controller  1301  (S 805 ). 
         [0264]    Furthermore, the buffer write processor  1304  executes the waiting time updating processing S 900  in parallel to the above frame storing S 804 . Although the waiting time updating S 900  is executed in parallel to the frame storing S 804  in the example shown in  FIG. 24 , the waiting time updating S 900  may be executed before S 804  or after S 804  or S 805 . 
         [0265]    Termination the processing in S 805  or S 900 , the buffer write processor  1304  exits the sequence number check processing (S 807 ). 
         [0266]    On the other hand, if ‘1’ is set in one of the receive bits  1362  and  1363  in S 803 , it means that a frame having the same content as that of the currently received frame is already stored in the input frame buffer  136 . Consequently, the buffer write processor  1304  sets ‘1’ in the receive bit  1382  or  1363  corresponding to the input port ID without updating the frame data  1364  (writing back the content of the frame data  1364  read in S 802  in the input frame buffer  136  as is) (S 806 ). Then, the buffer write processor  1304  exits the sequence number check processing (S 807 ). 
         [0267]    As a result of the comparison in S 801 , if the value of the sequence number SNnow  424  is under the value of the read counter  130 B, a frame having the same content as that of the received frame or its subsequent frame is already requested for sending. This means that there is no need to store the received frame in the input frame buffer  136 . Thus the buffer write processor  1304  discards the received frame and exits the sequence number check processing (S 807 ). 
         [0268]      FIGS. 25 and 26  show flowcharts of the waiting time updating processing S 900  executed by the buffer write processor  1304  in this second embodiment of the present invention. 
         [0269]    Then, the buffer write processor  1304  makes a search in the waiting time holding table  21  according to the flow ID  130 C used as the search key (S 901 ). 
         [0270]      FIG. 27  shows a configuration of the waiting time holding table in this second embodiment of the present invention. 
         [0271]    The waiting time holding table in this second embodiment holds entries of delay difference Ddif  212  between communication routes  0  NW 0  and  1  NW 1 , calculation mode MODE  213 , preceding sequence number SNpre  214 , preceding arrival time Tpre  215 , frame time interval IFG  216 , and time counter lap count TLap  217 . 
         [0272]    The delay difference Ddif  212  is the same as that shown in  FIG. 17 . 
         [0273]    The calculation mode MODE  213  represents a method to calculate the frame time interval IFG. The value ‘0’ set in the Mode entry  213  denotes that the average value of the frame time intervals in the past is calculated as the frame time interval IFG. The value ‘1’ denotes that the maximum value of the frame time intervals in the past is calculated as the frame time interval IFG. The calculated value is held in the field of the frame time interval IFG  216 . 
         [0274]    The preceding sequence number SNpre  214 , the preceding arrival time Tpre  215 , and the frame time interval IFG  216  are fields to be updated each time a frame is received. In the field of preceding sequence number SNpre  214  is overwritten the sequence number of each received frame. In the field of preceding arrival time Tpre  215  is overwritten the value of the timer counter  130 J each time a frame is received. In the field of frame time interval IFG  216  is overwritten a frame time interval calculated according to the value in the field of Mode  213 . 
         [0275]    The time counter lamp count TLap  217  denotes whether or not how many times the time counter  130 J is reset to ‘0’ from the maximum value between the previous table updating and the current time. The time counter  130 J holds the current time. The time held in this time counter  130 J is counted up at each clock according to the operation frequency of the subject packet transfer apparatus. 
         [0276]    Next, there will be described the processing that follows S 901  with reference to  FIG. 25  again. 
         [0277]    The buffer write processor  1304  makes a search in the waiting time holding table in S 901 . As a result, the buffer write processor  1304  obtains a value at which the flow identifier corresponds to the flow ID  211 . The buffer controller  1301  to which the buffer write processor  1304  belongs is allocated to that flow. Furthermore, the buffer write processor  1304  holds the value of the time counter  130 J as the time on which the frame is received this time, that is, the current arrival time Tnow (S 902 ). 
         [0278]    After this, the buffer write processor  1304  checks whether or not the value of the sequence number SNnow  424  set in the inner header  42  of the received frame is the same as the value obtained by adding ‘1’ to the value of the preceding sequence number SNpre  214  obtained in S 902  (S 903 ). 
         [0279]    If both of the values are the same in S 903 , the buffer write processor  1304  checks the value of the time counter TLap  217  obtained in S 902  (S 904 ). 
         [0280]    The processings in S 904  to S 908  are executed to calculate a frame time interval between the currently received frame and the precedingly received frame. In principle, the frame time interval can be calculated by subtracting the value of the preceding arrival time Tpre  215  from the value of the current arrival time Tnow obtained from the time counter  130 J. However, because the number of digits in the time counter  130 J is limited, the value of the time counter  130 J is returned to ‘0’ from the maximum value, then counted up cyclically. At this time, ‘1’ is added to the value of the time counter TLap  217 . Consequently, the frame time interval is required to be calculated according to the currently arrival time Tnow, the preceding arrival time Tpre  215 , and the time counter lap count TLap  217 . 
         [0281]    If ‘0’ is set in the field of time counter TLap  217  in S 904 , the value of the time counter  130 J does not reach the maximum value yet after the preceding frame is received. In this case, the buffer write processor  1304  subtracts the value of the preceding arrival time Tpre  215  from the Tnow and holds the result as the frame time interval IFGnow (S 905 ). 
         [0282]    If ‘1’ is set in the field of the time counter lap count TLap  217  in S 904 , the value of the time counter  130 J has reached the maximum value once after the preceding frame is received, then reset to ‘0’. In this case, the buffer write processor  1304  checks whether or not the value Tnow of the time counter  130 J is larger than the value of the preceding arrival time Tpre  215  (S 906 ). 
         [0283]    If the value of the time counter Tnow  130 J is under the value of the preceding arrival time Tpre  215  in S 906 , the buffer write processor  1304  adds the value obtained by subtracting the value of Tpre  215  from the maximum value Tmax of the time counter  130 J to the value Tnow. The buffer write processor  1304  then holds the result of the addition as the frame time interval IFGnow (S 907 ). 
         [0284]    If the value of the time counter Tnow  130 J is over the value of the preceding arrival time Tpre  215  in S 906  and the value of the time counter lap count TLap is over ‘2’ in S 904 , respectively, the actual frame time interval is larger than Tmax. In this case, the buffer write processor  1304  holds the value Tmax as the frame time interval IFGnow (S 908 ). Here, Tmax should be set over the maximum delay time within an upper limit range of the network. 
         [0285]    Completing the processing in S 905 , S 907 , or S 908 , the buffer write processor  1304  checks the calculation mode Mode  213  (S 911 ). 
         [0286]    If ‘0’ is set in the field of the calculation mode Mode  213  in S 911 , the buffer write processor  1304  sets the average value of frame time intervals as the value of the frame time interval IFG  216 . In this case, the buffer write processor  1304  calculates (IFGnow+IFG  216 )/2 as the average frame time interval (IFGave) (S 912 ). Then, the buffer write processor  1304  holds the calculated IFGave as the value IFG to be written back in the waiting time holding table  21  (S 913 ). 
         [0287]    If ‘1’ is set in the field of the calculation mode Mode  213  in S 911 , the buffer write processor  1304  sets the maximum frame time interval value as the frame time interval IFG  216 . In this case, the buffer write processor  1304  calculates (IFGnow, IFG  216 ) as the maximum frame time interval (IFGmax) (S 914 ). Here, the max (A, B) is a function meaning that A or B, whichever is larger, is selected. Furthermore, other conditions may be added to the condition of the function; for example, such a condition may be that a value over a certain value is not selected or a value over a certain multiple of B is not selected. Consequently, if the IFGnow is so large at a break of a traffic, its IFGnow value can be excluded there. 
         [0288]    After that, the buffer write processor  1304  holds the calculated IFGmax as the value IFG to be written back into the waiting time holding table  21  (S 915 ). 
         [0289]    In parallel to the processing in S 904 , the buffer write processor  1304  checks the sending stop flag  130 G held by the buffer controller  1301  corresponding to the subject flow ID (S 909 ). 
         [0290]    If ‘0’ is set in the sending stop flag  130 G in S 909 , the buffer write processor  1304  adds the delay difference Ddif  212  between routes  0  and  1  to the obtained frame time interval IFG  216  and sets the result in the field of the read timer  130 E, then begins count-down of the timer  130 E (S 910 ). ‘1’ is set in the sending stop flag  130 G when the buffer write processor  1304  detects a sequence number loss. While ‘1’ is set in this sending stop flag  130 G, the buffer write processor  1304  stops the frame sending and waits for arrival of a frame having the same sequence number as that of the lost frame. 
         [0291]    The buffer write processor  1304 , after executing the processing in S 910 , exits the waiting time updating processing (S 919 ). 
         [0292]    If ‘1’ is set in the sending stop flag  130 G in S 909 , the buffer write processor  1304  exits the waiting time updating processing without updating the read timer  130 E (S 919 ). 
         [0293]      FIG. 25  shows an example in which the buffer write processor  1304  executes the processings in S 909  to S 910  in parallel to the processings S 904  to S 908 , as well as S 911  to S 919 . However, the buffer write processor  1304  may execute the processings in S 909  and S 910  before the processing in S 904  or after the processing S 916 . In other words, the buffer write processor  1304  may execute the processing in S 904  after the processings in S 909  to S 910  or may execute the processing in S 909  after the processing in S 916 . 
         [0294]    If the value of the sequence number SNnow  424  is not the same as a value obtained by adding ‘1’ to the value of the preceding sequence number SNpre  214  in  903 , the buffer write processor  1304  determines that a sequence number loss has occurred due to a frame loss. In this case, the buffer write processor  1304  holds the frame time interval IFG  216  obtained in S 902  as the value IFG to be written back into the waiting time holding table (S 917 ). 
         [0295]    Upon completing the processing in S 913 , S 915 , or S 917 , the buffer write processor  1304  updates the waiting time holding table  21  (S 916 ). Concretely, among the table values obtained in S 902 , the buffer write processor  1304  writes back the value of SNnow  424  in the field of the preceding sequence number SNpre  214 , the value Tnow of the current time counter  130 J in the field of the preceding arrival time Tpre  215 , the write-back value IFG in the field of the frame time interval IFG  216 , and ‘0’ in the field of the time counter lap count TLap, respectively. 
         [0296]    Upon completing the processing in S 916 , the buffer write processor  1304  exits the waiting time updating processing (S 919 ). 
         [0297]    In parallel to the processing in S 917 , the buffer write processor  1304  sets ‘1’ in the sending stop flag  130 G and sets the value of the SNpre  214  in the field of the sending stop SN 130 H (S 918 ). As a result, in the sending stop SN 130 H is held the preceding sequence number of the lost one (that means the sequence number of the last sent-out frame). 
         [0298]    Upon the completion of the processing in S 918 , the buffer write processor  1304  exits the waiting time updating processing (S 919 ). 
         [0299]    While  FIG. 26  shows an example in which S 918  is executed in parallel to S 917 , S 917  may be executed after S 918  or S 918  may be executed after S 917 . 
         [0300]    The buffer read processor  1305  in this second embodiment executes the send frame request processing S 400  shown in FIG.  13 . However, the buffer read processor  1305  executes the processing of the request to send frames in the order of sequence numbers S 1000  shown in  FIG. 28  instead of the processing of the request to send frames in the order of sequence numbers S 500 . 
         [0301]      FIGS. 28 and 29  show flowcharts of the processing of the request to send frames in the order of sequence numbers S 1000  executed by the buffer read processor  1305  in this second embodiment of the present invention. 
         [0302]    Upon the start of the processing of the request to send frames in the order of sequence numbers S 1000 , the buffer read processor  1305  clears the frame storage flag (S 1001 ). 
         [0303]    Then, the buffer read processor  1305  reads the necessary data from the input frame buffer  136  according to the value of the read counter  130 B used as the read address (S 1002 ). 
         [0304]    After this, the buffer read processor  1305  checks the receive bits  1362  and  1363  of both of the routes  0  and  1  read from the input frame buffer  136  (S 1003 ). As a result of the check, if ‘1’ is held in any one of the receive bits  1362  and  1363 , the buffer read processor  1305  determines that a frame is stored in the address denoted by the value of the read counter  13 B provided in the input frame buffer  136 . In this case, the buffer read processor  1305  sends the values of both the flow ID  130 C and the read counter  130 B together with a send frame request to the scheduling unit  132  (S 1004 ). 
         [0305]    The buffer read processor  1305  then counts up the value of the read counter  130 B by one (S 1005 ). 
         [0306]    After this, the buffer read processor  1305  checks whether or not all ‘0’ is set in the field of the residual frame counter  130 D (S 1006 ). 
         [0307]    If the check result in S 1006  is YES (all ‘0’ set), it means that there is no frame remained in the input frame buffer  136 . In this case, the buffer read processor  1305  exits the processing of the request to send frames in the order of sequence numbers (S 1007 ). 
         [0308]    On the other hand, if the check result in S 1006  is NO (all ‘0’ not set), it means that there is a frame remained in the input frame buffer  136 . In this case, the buffer read processor  1305  counts down the value in the residual frame counter  130 D by one (S 1008 ). 
         [0309]    After this, the buffer read processor  1305  executes the processings in and after S 1002  again. 
         [0310]    If ‘0’ is set in both of the receive bits  1362  and  1363  in S 1003 , the buffer read processor  1305  determines that a sequence number is lost. In this case, a frame loss has occurred in either of the two communication routes  0  and  1 . The buffer read processor  1305  is thus required to wait for the arrival of the frame. And the buffer read processor  1305  checks the sending stop flag  130 G (S 1009 ). 
         [0311]    If ‘1’ is set in the sending stop flag  130 G in S 1009  the buffer read processor  1305  checks whether or not the value obtained by adding ‘1’ to the value in the read counter  130 B is the same as the value of the sending stop SN  130 H (S 1010 ). 
         [0312]    If the check result in S 1010  is YES (equal), the buffer read processor  1305  determines that the frame having the sequence number denoted by the current read counter  130 B is lost. In this case, the buffer read processor  1305  checks whether or not all ‘0’ is set in the field of the read timer  130 E (S 1011 ). 
         [0313]    If the check result in S 1011  is NO (not all ‘0’), it means that the buffer read processor  1305  is still waiting for the arrival of the frame. Consequently, the buffer read processor  1305  checks whether or not ‘1’ is set in the frame storage flag  130 A (S 1012 ). 
         [0314]    If the check result in S 1012  is YES (‘1’ set), it means that a frame has arrived before the time set in the read timer  130 E expires. In this case, the buffer read processor  1305  reads the frame from the input frame buffer  136  according to the value of the read counter  130 B used as the read address (S 1013 ). 
         [0315]    After this, the buffer read processor  1305  checks whether or not ‘1’ is set in the receive bit  1362  or  1363  (S 1014 ). 
         [0316]    If the check result in S 1014  is YES (‘1’ set), it means that a frame having the same sequence number as the lost one determined in S 1003  has arrived. In this case, the buffer read processor  1305  clears the frame storage flag  130 A (S 1020 ). Then, the buffer read processor  1305  executes the processings in and after S 1004  to generate a send frame request with respect to the arrived sequence number. 
         [0317]    If the check result in S 1014  is NO (‘0’ set in both), it means that there has been arrived a frame having a sequence number other than the lost one. In this case, the buffer read processor  1305  reads the frame from the input frame buffer  136  according to the value obtained by adding ‘1’ to the value of the read counter  130 B used as the read address, thereby checking whether or not a frame having the next sequence number of the lost one has been received from both of the two communication routes  0  and  1  (S 1015 ). The buffer read processor  1305  then checks whether or not ‘1’ is set in both of the receive bits  1362  and  1363  (S 1016 ). 
         [0318]    If the check result in S 1016  is YES (‘1’ set in both), the buffer read processor  1305  determines that the frame having the lost sequence number has been lost in both of the communication routes  0  and  1 . In this case, the buffer read processor  1305  counts up the value in the read counter  130 B by one (S 1019 ). The buffer read processor  1305  then executes the processings in and after S 1020  to generate a send frame request with respect to the frame having the next sequence number of the lost one. 
         [0319]    If the check result in S 1016  is NO (‘0’ set in either), the buffer read processor  1305  is still waiting for the arrival of the frame having the lost sequence number. Consequently, the buffer read processor  1305  clears the frame storage flag  130 A (S 1017 ), then counts up the value in the residual frame counter  130 D by one (S 1018 ) and executes the processings in and after S 1009 . 
         [0320]    If ‘0’ is set in the sending stop flag  130 G in S 1009 , it means that the buffer read processor  1305  is not waiting for any frame. In this case, therefore, the buffer read processor  1305  executes the processings in and after S 1005  to generate a send frame request with respect to the frame having the next sequence number. 
         [0321]    If the check result in S 1010  is NO (not equal), the buffer read processor  1305  determines that there has occurred a frame change; the frame having the sequence number of which sending should be stopped is changed to another. In this case, the buffer read processor  1305  executes the processings in and after S 1005  to generate a send frame request with respect to the frame having the next sequence number. 
         [0322]    If the check result in S 1011  is YES (all ‘0’), the buffer read processor  1305  determines that the frame having the lost sequence number has been lost in both of the communication routes  0  and  1 . In this case, the buffer read processor  1305  executes the processings in and after S 1005  to generate a send frame request with respect to the frame having the next sequence number of the lost one. 
         [0323]    If the check result in S 1012  is NO (‘0’ set), the buffer read processor  1305  keeps waiting for the frame having the lost sequence number. Consequently, the buffer read processor  1305  executes the processings in and after S 1009 . 
         [0324]    Next, there will be described a case in which the SN:2 frame  302  is lost, so that the packet transfer apparatus  10 N receives the SN:3 frame  303  after receiving the SN:1 frame  301 . In this case, if the packet transfer apparatus  10 N receives the SN:2 frame  312  before the waiting time expires after receiving the frame  301 , it means that all ‘0’ is not set in the read timer field  130 E in S 1011 . In this case, the waiting time is a total of the delay difference  81  between both routes and the average frame time interval  82 . And it is determined in S 1012  that ‘1’ is set in the frame storage flag  130 A. Furthermore, it is determined in S 1014  that ‘1’ is set in the receive bit  1363  of the communication route  1 . 
         [0325]    In the example shown in  FIG. 21 , if the SN:2 frame  312  is also lost and the packet transfer apparatus  10 N receives the SN:3 frame  313  before the waiting time expires, it means that all ‘0’ is not set in the read timer  130 E in S 1011  and ‘1’ is set in the frame storage flag  130 A in S 1012 . Furthermore, it means that ‘0’ is set in both of the receive bits  1362  and  1363  of the communication routes  0  and  1  in S 1014  and ‘1’ is set in both of the receive bits  1362  and  1363  of the communication routes  0  and  1  in S 1016 . 
         [0326]    In the example shown in  FIG. 2 , if the waiting time expires while the packet transfer apparatus  10 N receives none of the SN:2 frame  312  and the SN:3 frame  313 , it means that all ‘0’ is set in the read timer  130 E in S 1011 . 
         [0327]    As described above, according to the second embodiment of the present invention, just like the first embodiment, it is possible to prevent a case in which frame transfer cannot be restarted while a frame to be transferred is held. Furthermore, according to this second embodiment, a timing to restart frame transfer is determined by a frame time interval of each flow. Consequently, the present invention can apply appropriately to the characteristics of the subject traffic.