Abstract:
Disclosed is a image sensor (e.g., a CMOS image sensor) including pixels each having a transfer transistor and a drive transistor, in which the gate of at least one of the transistors has a boosting gate disposed over it comprised of a conductive film pattern with interposing an insulation film. Thus, a voltage applied to the boosting gate is capacitively coupled to at least one of the transfer gate of the transfer transistor and a drive gate of the drive transistor. The transfer gate is supplied with the sum of the transfer voltage and the boosting gate-coupling voltage as a result and there is no need for providing a high voltage generator for the image sensor. The dynamic range of operation may be enhanced if such a coupling voltage is applied to the drive gate of the drive transistor.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 of Korean Patent Application 2005-05007 filed on Jan. 19, 2005, the entire contents of which are hereby incorporated by reference.  
       BACKGROUND  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to image sensors, and more particularly relates to CMOS image sensors and methods of operating and fabricating the same.  
         [0004]     2. Description of the Related Art  
         [0005]     The rapid advancement of digital camera technology and a resulting increase of their popularity has made high performance digital cameras in high demand among consumer electronics. The basic components of a digital camera that determine its performance level are an optical lens and an image sensor. The image sensor functions to transform light applied thereto (through the optical lens) into an electronic signal representing an image.  
         [0006]     A typical image sensor is composed of a pixel array in which a plurality of pixels are arranged in a two dimensional matrix. Each pixel includes a light detection unit (or a photodetector), and a transmission and signal output (readout) unit. Image sensors may be normally classified into two types: the charge coupled device image sensors (hereinafter, referred to as CCD image sensors); and the complementary metal-oxide-semiconductor image sensors (hereinafter, referred to as CMOS image sensors). The CCD image sensor employs MOS (metal oxide semiconductor, field effect transistor) capacitors for transferring and outputting signals and charge carriers are stored in a capacitor are transferred to an adjacent capacitor, by a potential difference between the capacitors. By comparison, the CMOS image sensor utilizes a switching scheme sequentially detecting output signals of MOS transistors that are formed in the pixels thereof.  
         [0007]     Thus, the CCD image sensors are able to take better images than CMOS image sensors because of having less noise therein, but have disadvantages of higher product costs and larger power consumption. In other words, the CMOS image sensors have the advantages of lower power operation, (low power consumption), compatibility with integrated or operatively coupled CMOS circuits, random accessing of image data, reduced cost (e.g., by using standard CMOS techniques), and so forth. Thus, the CMOS image sensors are more widely used for various applications such as digital cameras, smart phones, PDAs, notebook computers, security cameras, barcode sensors, high definition televisions, high resolution cameras, toys, and so on.  
         [0008]      FIG. 1A  is an equivalent circuit diagram illustrating the pixel structure of a conventional CMOS image sensor including a photo-receiving device and four transistors (hereinafter, referred to as ‘four-transistor pixel structure’), and  FIG. 1B  is a timing diagram illustrating an operation of the CMOS image sensor of  FIG. 1A .  
         [0009]     Referring to  FIG. 1A , the image sensor with four-transistor pixel structure is composed of four transistors, (i.e., a transfer transistor  13 , a reset transistor  15 , a drive transistor  17 , a selection transistor  19 ), and a photo-receiving device  11 .  
         [0010]     The typical operation of the four-transistor pixel structure is as follows. Referring to  FIG. 1B , a selection voltage φSG is applied to the (selection) gate of the selection transistor  19  during a signal output period Td, turning the selection transistor  19  ON. After the selection transistor  19  is turned ON, a reset voltage φRG is applied to the (reset) gate RG of the reset transistor  15 , by which the reset transistor  15  is turned ON to reset a floating diffusion node  14  to a power supply voltage level VDD approximately. Thereby, the pixel is reset. Then, the supply voltage level VDD is applied to the (drive) gate DG of the drive transistor  17  as a drive voltage φDG, so that a reference voltage Vref is provided to an output node Vout within a first signal output period Td 1 .  
         [0011]     After resetting the pixel, when light is incident upon the photo-receiving device  11 , electron-hole pairs (EHP) are generated proportionally in response to the incident light. And then, if a transfer voltage φTG is applied to the transfer gate TG, the potential barrier (resistance) between the photo-receiving device  11  and the floating diffusion node  14  becomes lower (allowing a transfer of signal charges from the photo-receiving device  11  to the floating diffusion node  14 ). Thereby, the potential at the floating diffusion node  14  varies in proportion with the amount of signal charges transferred thereto. Thus, the drive voltage φDG applied to the drive gate DG drops down under the initial (supply) voltage VDD, and a (pixel) signal data voltage Vpix appears at an output node Vout within a second signal output period Td 2 . An image signal is output as a value arising from a difference value Vsig between the reference voltage Vref and the signal data voltage Vpix.  
         [0012]     As such, it is very important to entirely transfer the signal charges, which are generated at the photo-receiving device  11 , to the floating diffusion node  14  through the transfer gate TG. If the signal charges generated remain in the photo-receiving device  11  without being wholly transferred to the floating diffusion node  14 , the remaining signal charges causes the phenomenon of “image lagging” that leaves afterimages in the next frame, resulting in degradation of picture quality in the image sensor.  
       SUMMARY OF THE INVENTION  
       [0013]     Various aspects of the present invention provide an image sensor, for example, a CMOS image sensor, and other aspects of the invention may be applicable to provide another type of image sensor, e.g., a CCD image sensor. Exemplary embodiments of the invention provide a CMOS image sensor having the four-transistor pixel structure, wherein at least one of the (four) transistors (e.g., the Transfer transistor, and/or a Drive Transistor) has a stacked gate structure that provides a capacitive self-boosting effect. The boosting effect may be applied to elevate a bias voltage applied to the transfer gate or to reduce an electrostatic potential.  
         [0014]     An aspect of the present invention prevents the “image lagging” effect in the image sensor, e.g., by elevating a bias voltage applied to the transfer gate or reducing an electrostatic potential at the photo-receiving device. As the bias voltage to the transfer gate becomes higher, the potential barrier between the photo-receiving device and the floating diffusion node becomes lower. Also, the lower potential at the photo-receiving device lowers the potential barrier between the photo-receiving device and the floating diffusion node.  
         [0015]     However, the scheme that increases the bias voltage to the transfer gate needs to forcibly increase the bias voltage of the transfer gate by means of a high voltage generator that supplies a high voltage to the transfer gate. Meanwhile, the scheme of lowering the potential at the photo-receiving device causes a decrease of charge accumulation capacity in the photo-receiving device and an overflow of signal charges.  
         [0016]     Accordingly, embodiments of the present invention provide a high quality image sensor and methods of operating and fabrication the same.  
         [0017]     An aspect of the invention provides a CMOS image sensor comprised of a photo-receiving device (e.g., a photodiode), and a signal transformer converting signal charges of the photo-receiving device into voltages. The signal transformer includes a transfer gate, a reset gate, a drive gate, and a selection gate. Thus, each pixel of the image sensor is composed of the photo-receiving device, the transfer gate, the reset gate, the drive gate, and the selection gate. The control gate controls the operation of transferring the signal charges from the photo-receiving device to a floating diffusion region that is a charge storage area. For this, a transfer voltage is applied to the transfer gate as a control signal. The reset gate controls an operation of initializing (resetting) the signal charges of the floating diffusion region, for which a reset voltage is applied to the reset gate as a control signal. The drive gate is connected to the floating diffusion region, sensing a potential corresponding to the signal charges transferred to the floating diffusion region. The selection gate controls the operation of outputting the sensed potential, for which a selection voltage is applied to the selection gate as a control signal.  
         [0018]     In the exemplary embodiments of the invention shown in the figures, a boosting gate is disposed over one of the transfer and drive gates with an interposing (high-dielectric) insulation film. Thereby, the transfer gate, the dielectric film, and the boosting gate function as a capacitor. Similarly, the drive gate, the dielectric film, and the boosting gate finction as a capacitor. Thus, a bias voltage (boosting voltage) applied to the boosting gate is coupled with the transfer gate and/or the drive gate. As a result, the transfer gate is supplied with the sum of the voltage of the transfer voltage directly applied thereto and the voltage (boosting gate-coupling voltage) coupled thereto by the boosting voltage applied to the boosting gate pattern. Similarly, with a driving gate-coupling voltage (i.e., the boosting gate-coupling voltage) coupled to the drive gate by the boosting voltage, the floating diffusion region is variable in potential and thereby a dynamic range of the image sensor is enlarged.  
         [0019]     When after applying the transfer voltage to the transfer gate and floating the transfer gate, the boosting voltage is applied to the boosting gate pattern, the transfer gate is supplied with the sum of the transfer voltage and the boosting gate-coupling voltage as a result. As the boosting gate-coupling voltage (i.e., a transfer coupling voltage) as well as the transfer voltage is applied to the transfer gate, the transfer voltage and the boosting voltage applied to the boosting gate do not need to be (externally supplied) high voltages. Therefore, it is unnecessary to provide a high-voltage generator.  
         [0020]     Preferably, the boosting gate is electrically connected to the selection gate. In other words, the selection voltage applied to the selection gate is simultaneously applied also to the boosting gate as the boosting voltage. Thus, there is no need of an additional voltage supply source for supplying the boosting voltage. And, it is easy to supply the boosting voltage to the boosting gate just by using the selection voltage applied directly to the boosting gate pattern.  
         [0021]     The photo-receiving device may be a photodiode, a phototransistor, a pinned photodiode, a photogate, a MOSFET, or so forth, without limited to a specific one.  
         [0022]     Embodiments of the invention also provide a method of fabricating each pixel of an image sensor. The method comprises: confining an active region in a semiconductor substrate by a field isolation process; sequentially forming a first conductive film, a dielectric film, and a second conductive film on the semiconductor substrate; forming a boosting gate (pattern) from the second conductive film (e.g., by conducting a first photolithography and etching process); forming a transfer gate, a reset gate, a drive gate, and a selection gate from the first conductive film (e.g., by conducting a second photolithography and etching process against the first dielectric film); forming a photo-receiving device; and forming a local interconnection line to electrically connect the boosting gate(s), which is disposed over the transfer gate and/or the drive gate, to the selection gate(s) of pixels.  
         [0023]     The method may further comprise forming an analog capacitor in a peripheral circuit area. In this case, while forming the boosting gate from patterning the second conductive film by means of the first photolithography and etching process, the second conductive film of the peripheral circuit area is patterned to form the top electrode of the analog capacitor at the same time. And, while forming the transfer gate, the reset gate, the drive gate, and the selection gate from patterning the dielectric film and the first conductive film by means of the second photolithography and etching process, the dielectric film and the first conductive film those positioned in the peripheral circuit area are patterned to form a dielectric film and the bottom electrode of the analog capacitor at the same time.  
         [0024]     In this method, since the boosting gate (pattern) is disposed over the transfer gate (adjacent to the photo-receiving device), it does not cause an injection of ionic impurities into the substrate under the transfer gate even though there may be a misalignment during an ion implantation process for forming the photo-receiving device. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0025]     Embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be constructed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present invention and, together with the description, serve to explain principles of the present invention. In the drawings, the thickness of layers and regions are exaggerated for clarity. It will also be understood that when a layer is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In the drawings, like numerals and labels refer to like elements throughout the specification, and:  
         [0026]      FIG. 1A  is a schematic circuit diagram illustrating a pixel structure of a conventional CMOS image sensor including a photo-receiving device and four transistors;  
         [0027]      FIG. 1B  is a waveform diagram showing an operation by the CMOS image sensor of  FIG. 1A ;  
         [0028]      FIG. 2A  is a top view of an image sensor having a four transistor pixel structure in accordance with a preferred embodiment of the invention;  
         [0029]      FIG. 2B  is a sectional view along the section line I-I of  FIG. 2A , and  FIG. 2C  is a sectional view along the section line II-II of  FIG. 2A ;  
         [0030]      FIG. 3  is a detail from  FIG. 2B  or  2 C illustrating a boosting gate-coupling voltage φBG combined to a transfer gate  105   a  by a boosting voltage φBG applied to a boosting gate  109   a  shown in  FIGS. 2A through 2C ;  
         [0031]      FIGS. 4A through 4D  are electrostatic potential views illustrating the transfer of signal charges from a photo-receiving device to a floating diffusion region in an image sensor in accordance with an embodiment of the invention;  
         [0032]      FIG. 5A  is a top view illustrating an image sensor having a four transistor structure in accordance with another preferred embodiment of the invention,  FIG. 5B  is a sectional view along the section line I-I of  FIG. 5A , and  FIG. 5C  is a sectional view along the section line II-II of  FIG. 5A ;  
         [0033]      FIG. 6A  is a schematic diagram of the image sensor shown in  FIGS. 2A through 2C ;  
         [0034]      FIG. 6B  is a waveform diagram of signals in the image sensor of  FIG. 6A  illustrating the operation of the image sensor shown in  FIG. 6A ;  
         [0035]      FIG. 7A  is a schematic diagram of the image sensor shown in  FIGS. 5A through 5C , and  FIG. 7B  is a waveform diagram of signals illustrating an operation of the image sensor shown in  FIG. 7A ; and  
         [0036]      FIGS. 8A through 13A  and  8 B through  13 B are sectional diagrams illustrating processing steps for fabricating the image sensor show in  FIGS. 2A through 2C ,  FIGS. 8A through 13A  being taken along the section line I-I of  FIG. 2A  while  FIGS. 8B through 13B  being taken along the section line II-II of  FIG. 2A .  
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0037]      FIG. 2A  is a top view of an integrated image sensor having a four-transistor pixel structure in accordance with an embodiment of the invention.  FIG. 2B  is a sectional view along the section line I-I of  FIG. 2A , and  FIG. 2C  is a sectional view along the section line II-II of  FIG. 2A .  
         [0038]     Referring  FIGS. 2A through 2C , the CMOS image sensor includes a plurality of pixels, and each pixel is composed of a photo-receiving device PD ( 115 ) for receiving right, a transfer gate (TG)  105   a  for transferring signal charges from the photo-receiving device PD ( 115 ) to a floating diffusion region (FD)  117 , a reset gate (RG)  105   b  for discharging the signal charges form the floating diffusion region  117  to a reset diffusion region (RD)  119 , a drive gate (DG)  105   c  for outputting a voltage (by amplifying the voltage of the signal charges stored in the floating diffusion region  117 ), and a selection gate (SG)  105   d . A boosting gate  109   a  (BG) is disposed (patterned) over the transfer gate (TG)  105   a , with an interposing dielectric film  107   a  therebetween. A plurality of pixels each having this structure are arranged in a two-dimensional matrix, forming a pixel array of the image sensor.  
         [0039]     The boosting gate  109   a  is electrically connected to the selection gate  105   d  by a first local metal line  131  a (and through contact plugs  129   a  and  129   d  in the contact holes  127   a  and  127   d , see  FIG. 2B ). The floating diffusion region  117  is electrically connected to the drive gate  105   c  by a second local metal line  131   b  (and through contact plugs  129   b  and  129   c  in the contact holes  127   b  and  127   c , see  FIG. 2C ). The interconnections shown in  FIG. 2A , between the boosting gate  109   a  and the selection gate  105   d , and between the floating diffusion region  117  and the drive gate  105   c , are just examples and may be modifiable in various other arrangements and patterns.  
         [0040]     The photo-receiving device PD  115  is formed in an active region  102 A and the gates  105   a - 105   d  are formed over another active region  102 B. The active regions  102 A and  102 B are connected to each other, and are electrically isolated from their adjacent active regions by field isolation films  103  ( FIGS. 2B &amp; 2C ).  
         [0041]     The photo-receiving device PD  115  may be a photodiode composed of an N-region  111  and a P-region  113  (e.g., adjacent to each other). The transfer gate  105   a  (TG) is located adjacent to the photo-receiving device  115 . The photo-receiving device  115  is not confined in form to a photodiode, and may instead be implemented as a phototransistor, a pinned photodiode, a photogate, a MOSFET, or so forth.  
         [0042]     Referring to  FIGS. 2A and 2C , the floating diffusion region  117  (FD) is disposed between the transfer gate  105   a  and the reset gate  105   b . And the reset diffusion region  119  is disposed between the reset gate  105   b  and the drive gate  105   c . A voltage VDD is applied to reset the reset diffusion region  119 . The drive gate  105   c  is disposed between the reset diffusion region  119  (held at voltage VDD) and a first impurity diffusion region  121 . The first impurity diffusion region  121  is disposed between the drive gate  105   c  and the selection gate  105   d , and a second impurity diffusion region  123  is disposed between the selection gate  105   d  and the field isolation film  103 .  
         [0043]     On the other hand, it is practicable to exchange the positions of the selection gate  105   d  and the drive gate  105   c  relative to each other. For example, the reset diffusion region  119  may be designed to be disposed between the reset gate  105   b  and the selection gate  105   c.    
         [0044]     Differing from a conventional pixel structure (see  FIG. 1A ), the “four transistor” pixel structure according to an embodiment of the invention comprises the boosting gate  109   a  that is positioned over the transfer gate  105   a  with an interposing the dielectric film  107   a  therebetween. Further, the boosting gate  109   a  may be electrically connected to the selection gate  105   d . Thus, when the transfer gate  105   a  is floating and a predetermined bias voltage (i.e., selection voltage) φSG is applied, after applying a predetermined bias voltage (i.e., transfer voltage) φTG, to the transfer gate  105   a , the boosting gate  109   a  is charged with a boosting (e.g., boosted) voltage φBG by the selection voltage φSG. Thereby, the boosting voltage φBG makes the floating transfer gate  105   a  be further coupled with a boosting gate-coupling voltage φCBG. As a result, the transfer gate  105   a  is charged with the transfer voltage φTG and the boosting gate-coupling voltage φCBG. By this (boosting) mechanism, it is practicable to sufficiently lower the potential barrier between the photo-receiving device  115  and the floating diffusion region  117  without applying an additional (e.g., external) high voltage to the transfer gate  105   a , while enhancing the efficiency of transferring signal charges in the CMOS image sensor.  
         [0045]      FIG. 3  is a detail from  FIG. 2B  or  2 C further illustrating the boosting gate-coupling voltage φCBG combined to the transfer gate  105   a  (TG) by the boosting voltage φBG applied to the boosting gate  109   a  as shown in  FIGS. 2A through 2C . It is now assumed that C1 denotes the capacitance between the transfer gate  105   a  and a transfer channel  116  formable between the floating diffusion region  116  and the photo-receiving device  115 . And C2 denotes the capacitance between the transfer gate  105   a  and the boosting gate  109   a . Then, a final transfer gate voltage φFTG applied to the transfer gate  105   a  is defined by the following Equation 1: 
 φ FTG={C 1/( C 1+ C 2)}*φBG+φTG  (Equation 1)  
         [0046]     From Equation 1, it can be seen that the voltage value {C1/(C1+C2)}*φBG, (i.e., corresponding to the boosting gate-coupling voltage φCBG), is applied to the transfer gate  105   a  in addition to the transfer voltage φTG. Further, it is simple and easy to apply the boosting voltage φBG because the voltage applied to the selection gate  105   d  is also used for the boosting voltage φBG applied to the boosting gate  109   a . For raising a coupling ratio {C1/(C1+C2)} therein, it is preferable for the dielectric film  107   a  to be formed of a material with high dielectric constant.  
         [0047]     Now, a mechanism of transferring signal charges from the photo-receiving device (PD)  115  to the floating diffusion region (FD)  117  will be described with reference to  FIGS. 4A through 4D .  
         [0048]      FIGS. 4A through 4D  are electrostatic potential diagrams illustrating the transfer of signal charges.  
         [0049]      FIG. 4A  shows the potential in the photo-receiving device PD and in the floating diffusion region FD after completing the reset operation for the pixel. As illustrated in  FIG. 4A , between the photo-receiving device PD and the floating diffusion region FG, the transfer gate  105   a  is located under the boosting gate  109   a  with interposing the dielectric film  107   a  therebetween. The reset gate RG is located between the floating diffusion region FD and the reset diffusion region held at voltage VDD (not shown). And, the field isolation film (FOX)  103  is positioned at the other side of the photo-receiving device PD opposite from the transfer gate TG.  
         [0050]     The electrostatic potentials of the photo-receiving device PD and the floating diffusion region FD are determined by the concentration of (doping) impurities. For instance, the electrostatic potential under the transfer gate  105   a  is 0V and the electrostatic potential under the reset gate RG is 0V. The electrostatic potential under the field isolation film (FOX)  103  is 0V. The electrostatic potentials under the transfer gate  105   a , the reset gate RG, and the field isolation film  103  may be established in various values without instead of the above values.  
         [0051]     If the reset voltage φRG is applied to the reset gate RG and thereby the reset operation is conducted for the pixel, signal charges remaining in the floating diffusion region FD are all removed. Therefore, when light hν is incident upon the photo-receiving device PD after resetting the pixel, pixel signal charges  41  are trapped in a potential well  411  generated by potential differences under the photo-receiving device, the field isolation film, and the transfer gate.  
         [0052]     Referring to  FIG. 4B , next when the transfer voltage φTG is applied to the transfer gate TG, the electrostatic potential under the transfer gate TG decreases and the potential barrier between the photo-receiving device PD and the floating diffusion region FD is lowered. As a result, the signal charges  43  are transferred to the floating diffusion region FD. Otherwise, unless the transfer voltage φTG applied to the transfer gate TG makes the electrostatic potential thereunder to be sufficiently lowered (i.e., unless the electrostatic potential under the transfer gate TG is lowered to the bottom of the potential well  411 ), some signal charges  45  may remain at the bottom of the potential well  411 .  
         [0053]     Therefore, according to the invention, for the purpose of completely transferring the (remaining) signal charges  45 , which may remain at the bottom of the potential well  411 , to the floating diffusion region FD, the boosting voltage φBG is applied to the boosting gate BG over the transfer gate TG (e.g., after removing the transfer voltage φTG applied to the transfer gate TG (i.e., after floating the transfer gate TG)). Thus, the boosting gate-coupling voltage φCBG is further coupled to the transfer gate TG and as illustrated in  FIG. 4C , the electrostatic potential under the transfer gate TG is lowered to the bottom of the potential well  411  (or less) and thereby the signal charges  45  remaining at the bottom of the potential well  411  are entirely transferred to the floating diffusion region FD.  
         [0054]     Referring to  FIG. 4D , when the boosting voltage φBG is removed from the boosting gate  109   a , the remaining signal charges  45  transferred to the floating diffusion region FD are stored in a potential well  413  generated by electrostatic potential differences among the floating diffusion region FD, the substrate under the transfer gate TG, and the substrate under the reset gate RG. Accordingly, the  10  potential of the floating diffusion region FD is changed based on the transferred signal charges  45 .  
         [0055]     A voltage corresponding to the potential of the floating diffusion region FD, as changed by the signal charges  45  transferred to the floating diffusion region FD, is applied to the drive gate DG as the drive voltage φDG.  
         [0056]      FIG. 5A  is a top view illustrating a pixel in an image sensor, pixel having a four-transistor pixel structure in accordance with another embodiment of the invention.  FIG. 5B  is a sectional view along the section line I-I of  FIG. 5A , and  FIG. 5C  is a sectional view along the section line II-II of  FIG. 5A .  
         [0057]     Referring to  FIGS. 5A through 5C , the architecture of the pixels of the image sensor according to this embodiment is substantially similar to that of the first embodiment ( FIG. 2A ), except that a drive gate  505   c  is located under a boosting gate  509   a  with interposing a dielectric film  507   a  therebetween. The boosting gate  509   a  is again connected to a selection gate  505   d.    
         [0058]     The local interconnections between the boosting gate  509   a  and the selection gate  505   d , and between a floating diffusion region  517  and the drive gate  505   c , are illustrated just as examples and may be modified in various patterns.  
         [0059]     According to this embodiment of the invention, the boosting gate-coupling voltage φCBG is generated at the drive gate  505   c  (e.g., not the transfer gate TG  505   a ) by the boosting voltage φBG applied to the boosting gate  509   a , resulting in a variation of the electrostatic potential in the floating diffusion region  517 . For instance, the depth of the potential well  413  (see  FIGS. 4A  to  4 D) may be increased more than it was in the case of  FIGS. 4A through 4D . Therefore, the dynamic range of the image sensor may be enlarged.  
         [0060]     Operation of the Image Sensor  
         [0061]      FIG. 6A  is a schematic diagram of the image sensor shown in  FIGS. 2A through 2C , and  FIG. 6B  is a waveform diagram of signals in the image sensor of  FIG. 6A  illustrating the operation of the image sensor shown in  FIG. 6A .  
         [0062]     First, referring to  FIG. 6A , each of the pixels of the image sensor according to the first embodiment of the invention is comprised of a photo-receiving device  61 , a transfer transistor  63  having stacked gate structure, a reset transistor  65 , a drive transistor  67 , and a selection transistor  69 . The transfer transistor  63  includes a stacked gate structure formed of the transfer gate TG, the high-dielectric film, and the boosting gate BG. The boosting gate BG may be electrically connected to the selection gate SG of the selection transistor  69 . The transfer transistor  63  transfers the signal charges that are generated at the photo-receiving device  61 , to the floating diffusion region  64 .  
         [0063]     Referring to  FIG. 6B , a first selection voltage φSG 1  is applied to the selection gate SG of the selection transistor  69  during the first signal output phase Td 1  (t 0 ˜t 3 ) of the signal output period, which turns the selection transistor  69  ON. After turning the selection transistor  69  ON (at t 0 ), the reset voltage φRG is applied to the reset gate RG of the reset transistor  65  within the period t 1 ˜t 2  thus turning ON the reset transistor  65  is turned (to make the potential of the floating diffusion region  64  be set to a reference potential VFD, resetting the pixel). Thus, when the voltage corresponding to the reference potential VFD of the floating diffusion region  64  is applied to the drive gate DG of the drive transistor  67  (as the drive voltage φDG) at the time t 2 , the reference voltage Vref is output to the output node Vout at about time t 2 .  
         [0064]     If light is incident on the photo-receiving device  61  (e.g., from a lens), electron-hole pairs are generated and accumulated therein. After resetting the pixel, if the transfer voltage φTG is applied to the transfer gate TG at the time t 3 , the potential barrier between the photo-receiving device  61  and the floating diffusion region  64  becomes lower forming a charge transfer channel therebetween. Thus, the signal charges accumulated in the photo-receiving device  61  are transferred to the floating diffusion region  64 , and the potential of the floating diffusion region  64  varies in proportion to the amount of the signal charges transferred thereto. As a result, the drive voltage φDG applied to the drive gate DG decreases below the initial reference potential VFD, so that the signal data voltage Vpix appears at the output node Vout from the time t 3 .  
         [0065]     At time t 4  in the second signal output phase Td 2  (t 3 ˜t 6 ), the first selection voltage φSG 1  is removed (i.e., inactivated) to float the transfer gate TG.  
         [0066]     A second selection voltage φSG 2  is further applied to the selection gate SG at the time t 5 . Then, as the second selection voltage φSG 2  is conducted also to the boosting gate BG as the boosting voltage φBG, the resulting boosting gate-coupling voltage φCBG is added to the floated transfer gate TG around the time t 5 . As a result, the signal charges remaining in the photo-receiving device  61  are transferred to the floating diffusion region  64 . The second selection voltage φSG 2  is then removed from the selection gate SG at the time t 6 .  
         [0067]     The reference voltage Vref is sampled in the first signal output phase Td 1  after the time t 2  and the signal data voltage Vpix is sampled in the second signal output phase Td 2  after the time t 5 , so that an image signal is output from the difference value Vsig between the sampled reference voltage Vref and signal data voltage Vpix.  
         [0068]     The waveforms shown in  FIG. 6B  are just illustrative examples, and the dimensions of the signals and voltages and their settling times may be properly variable in various other manners. For example, in the operation of the image sensor having pixels characterized by  FIGS. 6A and 6B , the transfer voltage may be applied to the transfer gate TG at the time t 4  or between the time t 4  and the time t 5 , and removed at the time t 5 . Further, the second transfer voltage φSG 2  may be applied thereto between the time t 3  and the time t 4 .  
         [0069]      FIG. 7A  is a schematic diagram of a pixel in an image sensor having a plurality of pixels having the structure shown in  FIGS. 5A through 5C , and  FIG. 7B  is a waveform diagram of signals of the pixel of  FIG. 7A  illustrating the operation of the pixel the image sensor shown in  FIG. 7A .  
         [0070]     Referring to  FIGS. 7A and 7B , during the first signal output phase Td 1  (t 0 ˜t 3 ) the first selection voltage φSG 1  is applied to the selection gate  79 , and the reset transistor RG is turned ON to generate the reference voltage at the output node Vout. At the beginning (the time t 3 ) of the second signal output phase Td 2  (t 3 ˜t 6 ), the transfer voltage φTG is applied to the transfer gate TG. Thus, the signal charges stored in the photo-receiving device  71  are transferred to the floating diffusion region  74 , so that the signal data voltage Vpix starts appearing at the output node Vout. During the term of t 5 ˜t 6  in the second signal output phase Td 2 , the second selection voltage φSG 2  is additionally applied to the selection gate SG and the boosting gate BG is coupled with the second selection voltage φSG 2  as the boosting voltage φBG. As a result, since the boosting gate-coupling voltage φCBG generated by the boosting voltage φDBG is added to the drive gate DG, the potential of the floating diffusion region  74  goes to a higher level from the initial value by ΔV+ΔφCBG. Therefore, the dynamic range of the image sensor can be increased.  
         [0071]     In the first exemplary embodiment aforementioned ( FIG. 2A ), the boosting gate may additionally be disposed over the drive gate  105   c  with interposing the dielectric film (and electrically connected to the selection gate  105   d ). And, likewise, in the second embodiment aforementioned ( FIG. 5A ), the boosting gate may be also disposed over the transfer gate  105   c  with an interposing dielectric film (and electrically connected to the selection gate  105   d ).  
         [0072]     Moreover, in the first and second embodiments described above, the boosting gate may be also provided over the reset gate with an interposing dielectric film and connected to the selection gate. In this case, the boosting gate over the reset gate acts as a dummy gate without any bias voltage applied thereto.  
         [0073]     A method of fabricating the image sensor including pixels having the structure shown in  FIGS. 2A through 2C  will now be described with reference to  FIGS. 8A through 13A  and  8 B through  13 B.  
         [0074]      FIGS. 8A through 13A  and  8 B through  13 B are sectional diagrams illustrating processing steps for fabricating the image sensor including pixels having the structure show in  FIGS. 2A through 2C .  FIGS. 8A through 13A  are taken along the section line I-I of  FIG. 2A  and  FIGS. 8B through 13B  are taken along the section line II-II of  FIG. 2A . The area shown throughout  FIGS. 8A  to  13 B corresponds to a region of the pixel array, excluding a peripheral region including an analog capacitor, and so on. This embodiment is exemplarily practiced to form a CMOS image sensor with a P-type semiconductor substrate, and the pixel comprised of four transistors and a photodiode as the photo-receiving device, but various other embodiments of the invention may be practiced, forming other various CMOS image sensors or CCD image sensors by those skilled in the art, within the scope of the invention.  
         [0075]     First, referring to  FIGS. 8A and 8B , the processing steps of fabricating the image sensor according to an embodiment of the invention begin with preparing a semiconductor substrate  101 . The semiconductor substrate  101  may be provided by a wafer cut from Czochralski or float zone of single crystalline bulk silicon, including an epitaxial layer, a buried oxide film, or a doped region in order to improve the characteristic and construct a desired structure. For example, the semiconductor substrate  101  is a P-type substrate doped with impurities such as boron (B).  
         [0076]     The field isolation film  103  is formed to confine (isolate) active regions  102  ( 102 A and  102 B). The active region  102 A is provided to form the photo-receiving device (e.g., photodiode) of one pixel. The active region  102 B is provided to form various transistors (e.g., four transistors) of the pixel for transferring the signal charges generated from the photo-receiving device, converting the signal charges into the (pixel) signal data voltage Vpix, and outputting the (pixel) signal data voltage Vpix. The field isolation film  103  may be formed by means of a well-known technique, e.g., by shallow trench isolation (STI).  
         [0077]     Referring to  FIGS. 8A and 8B , a gate insulation film  104 , a first conductive film  105 , a dielectric film  107 , and a second conductive film  109  (comprising patterned portion  109   a  shown in  FIGS. 9A and 9B ), are deposited sequentially (e.g., by known methods). The gate insulation film  104  may be deposited by a thermal oxidation process for example. The first conductive film  105  may be formed of a doped polysilicon, for example. The first conductive film  105  (e.g., “gate poly”) is provided for forming the gates constructing the (four) transistors of each pixel in the pixel array area. (And, the first conductive film  105  is also used for the bottom electrode of a capacitor in the peripheral circuit area, not shown). The dielectric film  107  (e.g., a high-dielectric film) may be formed of an oxide-nitride-oxide (ONO) film by depositing an oxide film, a nitride film, and an oxide film, in that order. The second conductive film  109  (comprising patterned boosting gate portion  109   a  shown in  FIGS. 9A and 9B ) may be formed of a doped polysilicon (e.g., “gate poly”) or a metal. The second conductive film  109  is provided for forming (patterning) the boosting gate (pattern) in the pixel array area. The second conductive film  109  may also be used to form the top electrode of a capacitor in the peripheral circuit area (not shown).  
         [0078]     Next, referring to  FIGS. 9A and 9B , a photolithography and etching process is carried out to form (pattern) the boosting gate (pattern)  109   a  from the second conductive film  109 . (Meanwhile, the top electrode of the capacitor is formed in the peripheral circuit area (not shown)). The photolithography process is conducted to form a photoresist pattern  110   a  on the second conductive film  109 . With the photoresist pattern  110   a  used as an etch mask, a portion of the second conductive film  109  is etched away to leave (form, pattern) the boosting gate (pattern)  109   a  within the pixel array area (and the top electrode of the capacitor in the peripheral circuit area, not shown).  
         [0079]     Referring to  FIGS. 10A and 10B , a photolithography and etching process is carried out to form (pattern) the transfer gate  105   a , the reset gate  105   b , the drive gate  105   c , and the selection gate  105   d , from the first conductive film  105 . The transfer gate  105   a  is aligned under the boosting gate  109   a . (Meanwhile, in the peripheral circuit area, the dielectric film and bottom electrode of the capacitor are formed.) The photolithography process is conducted to form photoresist patterns  110   b   1 ,  110   b   2 ,  110   b   3 , and  110   b   4  on the dielectric film  107 . Here, the photoresist pattern  110   b covers the boosting gate (pattern)  109   a , and defines the transfer gate  105   a . The photoresist patterns  110   b   2 ,  110   b   3 , and  110   b   4  define the reset gate  105   b , the drive gate  105   c , and the selection gate  105   d , respectively. (Meanwhile, in the peripheral circuit area (not shown), the dielectric film and the first conductive film  105 , are selectively etched away by means of the photoresist patterns  110   b   1 ˜ 110   b   4  as etch masks.  
         [0080]     Then, (referring to  FIGS. 11A and 11B ), after forming an ion implantation mask (not shown, the ion implantation mask is formed to uncover the active region  102 A) for forming N-type regions of the photodiode, N-type ionic impurities are injected into the active region  102 A to form the N-type region  111  of the photodiode as the photo-receiving device. The N-type region  111  is disposed at one side of the transfer gate  105   a.    
         [0081]     After forming an ion implantation mask (not shown, during this process, the ion implantation mask is formed to uncover the active region  102 A) for forming a P-type region of the photodiode, P-type ionic impurities are injected into the N-type region  111  of the active region  102 A to form the P-type region  113  of the photodiode as the photo-receiving device. As a result, the N-type and P-type regions,  111  and  113 , constitute the photodiode  115 .  
         [0082]     For the purpose of preventing the signal charges, which are generated in the N-type region  111  of the photodiode  115 , from leaking into the P-type substrate  103 , after forming an N-type epitaxial silicon layer, a P-type well as a barrier layer may be formed to be interposed between the P-type substrate  103  and the N-type epitaxial silicon layer. The processing steps of forming the N-type epitaxial silicon layer and the P-type well are carried out before depositing the gate oxide film after completing the field isolation process.  
         [0083]     An N-type ionic impurity implantation process is carried out to form N-type impurity diffusion regions (e.g.,  117 ,  119 ,  121 ,  123 ) between adjacent gates in the substrate  103 . The impurity diffusion region between the transfer gate  105   a  and the reset gate  105   b  functions as the floating diffusion region  117 . The impurity diffusion region between the reset gate  105   b  and the drive gate  105   c  functions as the reset diffusion region  119  RD. And, the impurity diffusion regions between the drive gate  105   c  and the selection gate  105   d , and between the selection gate  105   d  and the field isolation film  103 , function as source and drain regions  121  and  123  (of transistors SG and DG, see  FIG. 6A ).  
         [0084]     Next, referring to  FIGS. 12A and 12B , after dielectric spacers are formed on sidewalls of the gates as an optional process, an interlevel insulation film  125  is deposited on the resultant structure. The interlevel insulation film  125  may be formed using a well-known film deposition process, e.g., being made of an insulation film of an oxide group.  
         [0085]     Then, the interlevel insulation film  125  is patterned to form a contact hole  127   a  disclosing the boosting gate (pattern)  109   a , a contact hole  127   b  disclosing the floating diffusion region  117 , a contact hole  127   c  disclosing the drive gate  105   c , and a contact hole  127   d  disclosing the selection gate  105   d . Although not shown, contact holes disclosing the transfer and reset gates may be formed at the same time with the contact holes  127   a ˜ 127   d.    
         [0086]     And, referring to  FIGS. 13A and 13B , a conductive material (i.e., metal) film  131  is deposited on the interlevel insulation film  125  to fill up the contact holes  127   a ˜ 127   d . A photography and etching process is carried out upon the conductive material film  131 , forming local metal interconnection lines including local metal interconnection line  13  la that electrically connects the boosting gate  109   a  with the selection gate  105   d  through contact plugs  129   a  and  129   d  in the contact holes  127   a  and  127   d , and local metal interconnection line  131   b  that electrically connects the floating diffusion region  117  with the drive gate  105   c  through contact plugs  129   b  and  129   c  in the contact holes  127   b  and  127   c . During this process, contact plugs filling up the contact holes disclosing the transfer and reset gates may be formed.  
         [0087]     Subsequently, usual processing steps are performed for completing the architecture of the CMOS image sensor, e.g., those of forming metal lines to apply control voltages to the local metal interconnection lines and contact plugs.  
         [0088]     Another method of fabricating the image sensor according to another embodiment of the invention t is similar to that by the last described method embodiment, except that the boosting gate is formed over the drive gate (see  FIGS. 5A  to  5 C). In this case, the boosting gate over the drive gate is electrically connected to the selection gate.  
         [0089]     Although the present invention has been described in connection with the exemplary embodiments of the present invention illustrated in the accompanying drawings, it is not limited thereto. It will be apparent to those skilled in the art that various substitution, modifications and changes may be thereto without departing from the scope and spirit of the invention.  
         [0090]     According to the features of the invention described above, the boosting gate is disposed over the transfer gate and/or the drive gate with an interposing dielectric film, and is electrically connected to the selection gate. Therefore, when the selection voltage is applied to the selection gate (e.g., after floating the transfer gate), it is possible to enhance the transfer efficiency of the signal charges generated in the photo-receiving device because the floated transfer gate is coupled with a predetermined voltage having the effect of capacitive self-boosting.  
         [0091]     Moreover, the dynamic range of the image sensor may be increased or adjusted, since the electrostatic potential floating diffusion region is variable .