Abstract:
Imprint lithography templates for patterning substrates are described. The templates include a section having a mold, a first pattern of alignment forming areas and template alignment marks. The additional sections are generally devoid of a mold. One or more of the additional sections may include a second pattern of alignment forming areas and template alignment marks. The second pattern may correspond to the first pattern.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    The present application is a continuation of U.S. patent application Ser. No. 10/895,214 filed Jul. 20, 2004, which is incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    The present invention relates to a method of improving imprint lithography alignment as well as a system and template to be used for same. The method, system, and template herein described have particular utility in subfield alignment of sub 100 nm features requiring registration of about 25 nm. 
         [0003]    Micro-fabrication involves the fabrication of very small structures, e.g., having features on the order of micrometers or smaller. One industry that has been driving the fabrication of increasingly smaller structures is the electronics industry. As electronic devices have become smaller and faster, the integrated circuits that drive them have necessarily become smaller. 
         [0004]    A technique known as ‘photolithography’, or simply ‘lithography’, is typically employed in the manufacture of integrated circuits. Lithographic techniques are generally used to pattern the various levels of an integrated circuit. Typically, these lithographic techniques include applying a photosensitive material to a semiconductor substrate. These photosensitive materials, commonly referred to as “resist,” are selectively exposed to a form of radiation. An exposure tool and photomask are often used to obtain the desired selective exposure. Such exposure changes the solubility of the resist such that the photomask&#39;s pattern is formed in the resist following a development process to remove the soluble resist. The resulting patterned resist serves to protect underlying conductive or dielectric material from etching or ion implantation. 
         [0005]    It is critical to align successive layers of an integrated circuit to each other to ensure proper operation of the circuit. In particular, the photomask pattern must be properly aligned to previously formed semiconductor topography features during the lithography process. In the extreme, lithographic misalignment may lead to shorting between structures that should be isolated from each other, and isolation of structures that should be coupled to each other. 
         [0006]    Imprint lithography is capable of manufacturably producing sub-100 nm features. Several imprint lithography techniques have been investigated as low cost, high volume manufacturing alternatives to conventional photolithography for high-resolution patterning. In this emergent technology, a relief image in a template is used to replicate a surface relief into a polymerizable material arranged upon the surface of a substrate. The template makes mechanical contact with the material arranged upon the substrate, and the material is subjected to conditions to solidify and/or to polymerize the same such that a relief structure complimentary to that of the template is formed on the substrate. The material may be solidified or polymerized by, for example, heat or actinic light. Such patterning and polymerization techniques may be referred to as thermal imprint lithography or ultraviolet (‘UV’) imprint lithography, respectively. Typical substrates may include semiconductors, dielectric materials, magnetic materials, or optoelectronic materials. 
         [0007]    Imprint lithography may be used in wide variety of applications. That is, imprint lithography applications are not limited to the manufacture of integrated circuits. However, typical applications require alignment of subsequently imprinted device layers to previously imprinted device layers. Properly aligning subsequent imprint lithography device layers becomes increasingly difficult as feature sizes become ever smaller. Imprint lithography systems are currently capable of printing features in the sub-100 nm range with a 3σ overlay alignment capability of less than about 500 nm. Despite a high degree of alignment accuracy, current imprint lithography systems are challenged by the degree of precision required to consistently align multiple layers having minimum feature sizes. Devices having such minimum feature sizes may also have registration tolerances of about 25 nm or less. Consequently, proper alignment of multi-layered devices having minimum feature sizes may be a relatively infrequent event. It is desired, therefore, to provide improvement to imprint lithography alignment. 
       SUMMARY OF THE INVENTION 
       [0008]    Presented herein is an improved alignment method with particular utility in imprint lithography applications. In an embodiment, the method of improving lithographic alignment essentially comprises imprinting a first layer on a substrate and imprinting a second layer on the first layer, the first layer including an array of first-layer geometries each arranged within a respective subfield with each first-layer geometry including at least one first-layer feature, and the second layer including an array of second-layer geometries each arranged within a respective subfield with each second-layer geometry including at least one second-layer feature, where at least one second-layer feature has at least one corresponding first-layer feature, where at least one second-layer geometry has a corresponding first-layer geometry, and where at least one second-layer geometry is intentionally offset from its corresponding first-layer geometry. In an embodiment, at least two second-layer geometries are intentionally offset from their corresponding first layer geometries, and said offsets are not equal. 
         [0009]    Also in an embodiment, the present invention essentially comprises a method of improving lithographic alignment between subsequent imprinted device layers within a subfield. Such a method includes establishing an (x,y) grid whereby a centermost point of a subfield arranged within a central region has (x,y) coordinates (0,0). Such a method further includes establishing an array having ‘N’ subfields arranged in ‘J’ rows and ‘K’ columns, where each column has a width ‘w’ and each row has a height ‘h’, and a device is arranged entirely within a single subfield. The method further includes imprinting a first layer having an array of ‘N’ first-layer geometries, where a centermost point of a central first-layer geometry has (x,y) coordinates (0,0), where a centermost point of each first-layer geometry is commensurate with a centermost point of its respective subfield, where a centermost point of a first-layer geometry is a spaced distance ‘w’ from a centermost point of an immediately laterally adjacent first-layer geometry, and where a centermost point of a first-layer geometry is a spaced distance ‘h’ from a centermost point of an immediately vertically adjacent first-layer geometry. The method further includes imprinting a second layer, where the second layer includes an array of ‘N’ second-layer geometries, where each second-layer geometry has a corresponding first-layer geometry, where a centermost point of a central second-layer geometry has (x,y) coordinates (0,0), where a centermost point of a second-layer geometry is a spaced distance ‘w+Δw’ from a centermost point of an immediately laterally adjacent second-layer geometry and a centermost point of a second-layer geometry is a spaced distance ‘h+Δh’ from a centermost point of an immediately vertically adjacent first-layer geometry, where Δw and Δh are both non-zero. 
         [0010]    Also in an embodiment, the present invention essentially comprises a set of lithography templates providing improved lithographic alignment. Such a template set includes a first template having an array of first geometries and a second template having an array of second geometries, where each second geometry has a corresponding first geometry, and where at least one second geometry is intentionally offset from its corresponding first geometry. 
         [0011]    These and other embodiments are herein described. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]      FIG. 1  is a plan view of a wafer substrate illustrating the wafer field and the print fields which comprise the wafer field. 
           [0013]      FIG. 2  is a plan view of a print field having multiple subfields. 
           [0014]      FIG. 3  is a plan view of a print field having first and second-layer geometries imprinted thereupon. 
           [0015]      FIG. 4  is a plan view of the print field of  FIG. 4  imposed upon x and y axes. 
           [0016]      FIG. 5  is a more detailed view of  FIG. 5 . 
       
    
    
       [0017]    The same reference numerals refer to the same parts throughout the various figures. 
       DETAILED DESCRIPTION OF THE INVENTION 
       [0018]    Although an imprint lithography system may have a high degree of alignment accuracy, the alignment precision may not suffice for multi-layered devices having sub 100 nm features. Using typical lithography methods, systems, and devices, a system having a three sigma alignment accuracy of less than about 500 nm may not be sufficient to produce functional, multi-layered devices having, for example, registration tolerances of about 25 nm or less, and having minimum feature sizes of, for example, about 50 nm or less. An exemplary lithographic system is available under the trade name IMPRIO® 100 from Molecular Imprints, Inc. having a place of business at 1807 Braker Lane, Bldg. C-100, Austin, Tex. 78758. The system description for the IMPRIO® 100 is available at www.molecularimprints.com and is incorporated herein by reference. 
         [0019]    Typically all the layers within a respective print field are replicated substantially identically, resulting in substantially identical devices within each print field. This strategy is useful when producing devices which have design tolerances well within the capabilities of the lithography system, or systems, used. In such cases, successful device production may be defined by a high yield of functional devices. However, the instant invention is intended to aid in producing leading-edge devices that have design tolerances which test the capabilities of the best lithography systems now available. In the manufacture of such leading-edge devices, success may be defined as producing as few as a single functional device on an entire wafer. Where design tolerances such as alignment or registration test the limits of a lithography system, success may be attained by deliberately offsetting device features. That is, it may be desirable to deliberately offset features of an imprinted image within an individual subfield as described below. 
         [0020]      FIG. 1  illustrates substrate  16 , which in this case is a semiconductor wafer. Upon substrate  16 , a wafer field  18 , comprising print fields  20 , is defined. Typically, a wafer field  18  is comprised of an integral number of print fields  20 . The dimensions of a print field may be as large as a lithography system&#39;s maximum field. An imprint lithography system&#39; maximum field is the largest area the system can simultaneously imprint. That is, the maximum area that can be imprinted with one flash. In an embodiment, the maximum field size of an imprint lithography system is 25 mm×25 mm. An optical lithography system&#39;s maximum field is the largest area the system can expose in one exposure. A wide variation of maximum optical lithography field sizes exist, ranging from about 25 mm×33 mm to about 800 mm×920 mm. Although the instant invention is directed toward an imprint lithography system, the methods, systems, and templates described herein may also be applicable to at least some optical lithography systems. 
         [0021]      FIG. 2  illustrates a print field  20  having multiple subfields  22 . Typically, a print field is comprised of an integral number of subfields. Subfields  22  are shown a spaced distance from the perimeter of the print field  20  merely for clarification. Similarly, the subfields  22  are shown a spaced distance from one another merely for clarification. In an embodiment, subfields  22  may abut one another. Each subfield may accommodate one or more devices. The devices may or may not have similar geometries, features, and/or functions. 
         [0022]    A first-layer geometry is created within each subfield  22 . The first layer geometry includes first-layer features for one or more devices which may or may not be similar. The first layer features may have minimum feature sizes in the range of, for example, 100 nm or smaller. Each first-layer geometry is arranged such that its features are arranged entirely within its respective subfield  22 . In the embodiment shown, the first layer geometry has a centermost point which is substantially commensurate with the centermost point of the subfield. Thus, in an embodiment, each first-layer geometry is similarly arranged within its corresponding subfield. Such arrangement is in contrast to the second-layer geometries to be discussed below. 
         [0023]      FIG. 3  illustrates the print field  20  having second-layer geometries  24  imprinted upon first-layer geometries. Each second-layer geometry is comprised of second-layer features, where at least one second-layer feature has a corresponding first-layer feature to which proper alignment is required for proper device operation. Typically, a second-layer geometry will occupy the same approximate area as its corresponding first-layer geometry. Therefore, it is noted that first-layer geometries do not necessarily extend to the perimeter of their respective subfields, as second-layer geometries may be printed entirely within their respective subfields. As used herein, first-layer or second-layer geometries may not necessarily include sacrificial diagnostic features. Such features may be created within the print field yet outside the subfields. 
         [0024]    As shown, no two second-layer geometries are similarly arranged within their respective subfields. A centermost second-layer geometry  26  has a centermost point which is substantially commensurate with that of its respective subfield. However, each other second-layer geometry&#39;s centermost point is offset from that of its respective subfield. Further, each offset second-layer geometry has a unique offset. In an embodiment, each offset with respect to a centermost point of the subfield may be a multiple of about 25 nm. In this case, the offset multiple is therefore 25 nm. The offset multiple is a function of the capability of the lithography template-making process, system, and apparatus(es). Consequently, as template manufacturing improves, offset multiples may shrink accordingly. 
         [0025]      FIG. 4  illustrates the arrangement of the first-layer geometries and second-layer geometries with the aid of an (x,y) axis. Central second-layer geometry  26  is arranged such that its centermost point is substantially commensurate with the origin of the axis, (0,0). The subfields are arranged in an array having ‘J’ rows and ‘K’ columns. In this case, J=K=5. However, it is not required that J=K. Each column has a width ‘w’ and each row has a height ‘h’. In this embodiment, the first-layer geometries are spaced commensurate with the subfields. Thus, the first layer geometries are not offset with respect to their respective subfields. Therefore, a center of any first-layer geometry is a horizontal distance of ‘w’ or a vertical distance of ‘h’ from any immediately laterally adjacent first-layer geometry. In the embodiment shown, ‘w’ equals ‘h’, and the centers of the first-layer geometries are equally spaced one from the next. 
         [0026]    As more clearly illustrated by  FIG. 5 , the centers of the second-layer geometries are also equally spaced. However, the spacing of the second-layer geometries are not equal to the spacing of the first-layer geometries. The columns of the second-layer geometries have a width ‘w+Δw’, and the rows have a height ‘h+Δh’. It is noted that the offset multiples, Δw and Δh, may be any non-zero number. For example, the offset multiples shown in  FIG. 5  are negative. In an embodiment, a centermost subfield is imprinted with geometries having no offset with respect to the centermost subfield, and geometries imprinted on remaining subfields have (x,y) offsets equivalent to the product of the respective offset multiples, (Δw,Δh), and the number of rows and columns from the centermost subfield. As an example, second-layer geometry  30  is one column, zero rows from the centermost subfield. Hence, the offset of second-layer geometry  30  is (Δw,0). 
         [0027]    While preferred embodiments of the instant invention have been described in detail, it should be apparent that modifications and variations thereto are possible, all of which fall within the true spirit and scope of the invention. With respect to the above description then, it is to be realized that the optimum dimensional relationships for the parts of the invention, to include variations in size, materials, shape, form, function and manner of operation, assembly and use, are deemed readily apparent and obvious to one skilled in the art, and all equivalent relationships to those illustrated in the drawings and described in the specification are intended to be encompassed by the present invention. As described above, a single wafer substrate is contemplated. However, it is recognized that the invention herein described may be employed with any number of lithography applications. 
         [0028]    Additionally, although the designations first-layer and second-layer are used, it is understood that the terminology is not intended to be limiting. That is, although in an embodiment the first-layer may precede the second-layer, the first-layer does not necessarily immediately precede the second layer. Further, in an embodiment, the described second-layer having at least one offset second-layer geometry may actually precede the first-layer geometry having no offset geometries. That is, a layer having offsets with respect to the subfields may be printed prior to a layer having no such offsets. Further, both layers may have offsets. That is, there may be no layer having no offset geometries with respect to the respective subfields. Furthermore, the instant invention is not limited to 2 layers. Three or more layers may be employed without deviating from the intents and purposes of the instant invention. Consequently, a subfield may itself be comprised of subfields, or sub-subfields. Such sub-subfields may or may not comprise entire devices. 
         [0029]    Further, the number of subfields which comprise a print field may not be constant, even within a single wafer. Maximum print field size is lithography system dependent. Therefore, the print field size may vary within a single wafer in those cases where processing is performed by multiple lithographic systems, each having a distinct print field size. Thus, the print field size may vary from one processing layer to another. Each print field may be comprised of multiple subfields, where each subfield accommodates one or more devices, and each subfield may be comprised multiple sub-subfields which may or may not accommodate whole devices and which may or may not include offset geometries. 
         [0030]    However, whole print fields typically have an integral number of devices. Yet, partial print fields may be imprinted or patterned by the lithography system, particularly around a perimeter of the substrate. It is possible for a partial print field to produce yielding devices in those instances where a print field accommodates multiple devices. In the instances where a print field accommodates only a single device, partial print fields may also be imaged or patterned although no possibility of a yielding device exists. For example, such wafer edge processing may be advantageous in terms of, for example, layer uniformity and wafer planarity. 
         [0031]    Although improving alignment registration for features less than about 100 nm has been described, it should be appreciated that the invention herein described is also suitable for improving alignment registration for any size features as may be required in the fabrication of, for example, an integrated circuit. Thus, as patterning resolution improves, the methods, systems, and templates described herein may continue to aid in improve lithographic alignment. Further, applications for the instant invention may exist in the manufacture of devices having features much larger than about 100 nm. 
         [0032]    Therefore, the foregoing is considered as illustrative only of the principles of the invention. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and operation shown and described, and accordingly, all suitable modifications and equivalents may be resorted to, falling within the scope of the invention.