Abstract:
Fast and slow channels are attached to a cached peripheral storage system, having a front store and a backing store preferably with a plurality of data storage devices. The peripheral data storage device data transfer rate is not greater than the data rate of the fast channels but greater than the data rate of the slow channels. For data associated with a fast channel, data promotion from the backing store to the front store is designed to encourage read hits while discouraging write hits. For the slow channel, all data goes through the front store. Cache bypassing controls are handled through the LRU (least recently used) replacement algorithm for the slow channels. A common demotion of data from the front store to the backing store is used for all channels. Front store occupancy varies in that buffering for slow channels (data rate change) tends to store and keep full tracks, while caching for fast channels limits data occupancy. For a fast channel, a cache miss results in directly accessing the backing store. The data storage devices are preferably disk data storage devices (DASD) or magnetic tape recorders.

Description:
FIELD OF THE INVENTION 
     The present invention relates to peripheral storage hierarchies preferably of the type where a random access data cache provides an apparent store for a slower backing store, such as a magnetic storage disk file or a magnetic storage tape file. 
     BACKGROUND OF THE INVENTION 
     Data processing has always relied on peripheral storage units such as magnetic tape units and magnetic disk units for storing large amounts of data. Data from such paripheral storage units have been transferred on a demand basis to a main memory of the data processing unit such as shown by Kilburn, et al in U.S. Pat. Nos. 3,217,298 and 3,218,611. In these instances the main memory was used to queue the data awaiting use by the computer programs which required the data. The notion of enhanced performance of a peripheral storage device through the use of data buffers is set forth by Gregory, et al, U.S. Pat. No. 2,960,683. Gregory, et al teach that data can be queued in a first in first out (FIFO) buffer interposed between a peripheral data recorder and a data processing main memory. The effect of the Gregory, et al data buffer is to tend to mask the mechanical delays of the peripheral data recorder from the data processing unit to which it is attached. The desire for high performance and great storage capacity was not satisfied by any of the above solutions. 
     The Eden, et al, U.S. Pat. No. 3,569,938 shows the concept of a peripheral apparent store characterized as having a high speed storage which operates with the data processing unit and a bulk storage which stores large amounts of data. A control closely associated with the high speed storage and the bulk storage responds to the request from a data processing unit for maintaining data in the high speed storage that is expected to be next used by the data processing unit. This control, called a storage manager, responds to requests from the data processor for paging data from the bulk storage to the high speed storage and in the reverse direction in accordance with predetermined space allocation and replacement rules. In one embodiment the high speed storage was a magnetic core random accessed memory similar to the present day semiconductor memories. The bulk storage can be magnetic disk storage or magnetic tape storage. Also, magnetic disk storage may be a high speed storage for a magnetic tape store. The apparent peripheral store was to provide data and receive data from a plurality of computer connections. The Arnold, et al U.S. Pat. No. 3,670,307 shows a way of improving the operations of a two-level storage hierarchy in that only altered data is moved from the high speed store to the bulk store. Greater flexibility of the apparent store is shown by Amdahl, et al in U.S. Pat. No. 3,670,309 wherein a plurality of ports or host attachment circuits are provided; each port has its own control and has the capability of queuing access requests such that internal operations of the two-level hierarchy is enhanced. Other enhancements of this peripheral storage hierarchy includes placing a data buffer in a channel such as shown in U.S. Pat. No. 3,699,530. This buffer appears to be a first in first out buffer wherein data is queued prior to being assigned to main memory. The variation of a buffer in a channel is shown in U.S. Pat. No. 3,735,360 wherein each processor has its own cache buffer, i.e. rather than a FIFO buffer, a true managed buffer for cache data is provided for each channel. A host attachment for attaching a peripheral storage system to a host is shown in U.S. Pat. No. 3,812,475. Yet another buffered disk storage apparatus is shown in U.S. Pat. No. 3,839,704 how an input/output channel of data processing system accesses data from a disk storage apparatus when a caching buffer is provided. A more elaborate storage hierarchy is shown by Dejohn, et al in U.S. Pat. No. 4,053,752 wherein a plurality of disk storage apparatus cache data from an automatic tape library. Data transfers between a tape library and the caching disk storage apparatus is via a FIFO buffer wherein data is queued in either direction of transfer. A small serializer/deserializer buffer is interposed between the host input/output channel and the caching disk storage apparatus. 
     The idea of caching in memory also exists between the main memory and a processor. For example, in U.S. Pat. No. 4,189,770 the cache is selectively bypassed on certain operand data transfers. U.S. Pat. No. 4,157,586 shows updating the main memory cache when the back store for main memory is also updated. Transferring data from the cache to the main memory while measuring the rate of accesses to the cache by the processor and then taking time out to do the main memory data transfers shown in U.S. Pat. No. 4,159,517. Caches have been organized in a plurality of caches each having a directory such as shown in U.S. Pat. No. 4,142,234. A copy back control in a multilevel storage hierarchy is shown in U.S. Pat. No. 4,084,231. U.S. Pat. No. 4,020,466 shows copying back to lower levels all changes in upper levels of storage. U.S. Pat. No. 3,588,839 shows moving altered data from a high level in the storage hierarchy to a lower level as soon as possible. 
     Peripheral systems traditionally attach to various types of computers. Rather than redesign attachments for each type of computer, so-called channels have been developed which couple diverse computers to diverse peripheral systems. With channels, one peripheral system can simultaneously be connected to several different types of computers. It turns out that even with channels, diverse computers have different I/O or channel commands. To accommodate different command sets, the peripheral systems have included diverse circuits. For example, U.S. Pat. No. 3,721,961 shows connecting a peripheral system to diverse computers having diverse command sets. A circuit accommodates the computer diversity by enhancing recovery capabilities of one computer to that of another computer. 
     Even with all of the above techniques a more optimal performing peripheral storage hierarchy has yet to be devised. Certain improvements in such storage hierarchy internal operations which enhance data integrity as well as providing faster access to the data is still highly desirable. As peripheral devices have increased capability, there is still a requirement that those devices operate with older and probably slower hosts. In particular, input/output or peripheral channel data transfer capacities have substantial data rate variations. For example, a so-called streaming channel can have a capacity for transferring three megabytes per second while older channels may have a capacity of 1.5 megabytes or less per second. Therefore, when new devices are incorporated into a storage hierarchy, it is desired that that hierarchy be capable of attaching not only to the faster channels but also to the slower channels. Such attachments may require substantially diverse data handling techniques for providing an efficient storage hierarchy. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a peripheral data handling system which automatically adjusts its internal operations in accordance with the relative data transfer capabilities of the attaching channels with respect to the internal data handling capability of the peripheral system. 
     A path or channel having a data transfer capability of not less than the peripheral system in certain instances is encouraged to directly access the peripheral devices even though caching of data between the host and the device may occur. In a specific aspect, data transfers in a first direction to the devices is encouraged to be direct to the devices, while data transfers from the devices to a using host via a cache is encouraged. For data transfers via data channels having a data transfer rate less than the data transfer capability of the peripheral devices, i.e. slow channels, data caching occurs for all transfers. A selection of the internal operations is on an operation by operation basis and is not data related. Additionally, the using unit sends intent signals to the peripheral system for indicating a desired operative relationship to be established between the cache and the devices. The same intent signals are interpreted by the peripheral system for fast and slow channels in diverse ways for maintaining efficiency and desirable operative connections. In particular, selectively bypassing the cache results in diverse internal controls. Internal controls for space management of the cache are made independent of fast and slow channels except as affected by the transfer of signals between the host and the devices over such diverse channels. 
     The foregoing and other objects, features, and advantages of the invention will be apparent from the following more particular description of the preferred embodiments of the invention, as illustrated in the accompanying drawings. 
    
    
     DESCRIPTION OF THE FIGURES 
     FIG. 1 is a logic block diagram of a peripheral data storage system incorporating the teachings of the present invention with respect to attaching to hosts via relatively fast and relatively slow channels. 
     FIG. 2 is a logic block diagram of a preferred embodiment of the present invention which is based upon the FIG. 1 illustration. 
     FIG. 3 is a generalized flow chart of machine operations for a peripheral data handling system as shown in FIGS. 1 and 2. 
     FIG. 4 is a diagrammatic showing of a cache directory and a device control block usable with the FIGS. 1 and 2 illustrated system with particular reference to explaining the present invention. 
     FIG. 5 diagrammatically illustrates a mode set command for providing control to a peripheral data handling system as shown in FIGS. 1 and 2 with particular reference to practicing the present invention using the mode setting intent signals. 
     FIG. 6 is a machine operations chart illustrating execution of a mode set command, as shown in FIG. 5, by the FIGS. 1 and 2 illustrated system. 
     FIGS. 7 and 8 are a machine operations chart illustrating operations of the FIGS. 1 and 2 illustrated systam during a data transfer. 
     FIG. 9 is a machine operations chart illustrating asynchronous or so-called post-chaining operations of the FIGS. 1 and 2 illustrated system which pertain to practicing the present invention in a best mode. 
    
    
     DETAILED DESCRIPTION 
     Referring now more particularly to the drawing, like numerals indicate like parts and structural features in the various diagrams. As best seen in FIGS. 1 and 2, hierarchical peripheral storage system 10 is attached to hosts (also termed using units) 11 for receiving and supplying data signals for host and storage utilization. In a typical application of storage system 10, hosts 11 consist of central processing units (CPUs). In other variations, hosts 11 can include virtual machines or a set of virtual machines running on a hardware CPU. Hosts 11 may also be multi-processors, uni-processors with attached processors and the like. Storage system 10 for a paging and swapping connection is usually attached to a single host while for general applications it is usually attached to a plurality of hosts 11. 
     Communications between the paging storage system 10 and hosts 11 occur via a plurality of input/output connections 12 which are constructed in accordance with the input/output peripheral channels of the IBM 370 series of computers available from International Business Machines Corporation, Armonk, N.Y. Such input/output connections, commonly referred to as channels and subchannels, are so well known, their individual description is not necessary. Hosts 11 have I/O channels of varying data transfer rate capabilities. Fast channels 13 enable data transfers between hosts 11 and peripheral system 10 at a given maximal data rate, such as three megabytes or more per second. Slow channels 14 provide for a slower data transfer rate such as 700 kilobytes per second, 1.5 megabytes per second and the like. In accordance with the invention, peripheral system 10 provides efficient data transfers with any of these channels, fast or slow. 
     Storage system 10 has a lower or backing store consisting of a plurality of direct access storage devices (DASD) 16 and separately enumerated D0, D1, . . . All accessing of data and storage of data by host 11 with respect to peripheral storage system 10 is by addressing DASDs 16. This addressing is achieved by using the known architecture of the input/output connections 12. In some instances, hosts 11 transfer data directly with DASDs 16 while at other times cache 40 of system store 30 is interposed between hosts 11 and DASDs 16. For performance purposes (rapid access to data areas), control 31 manages peripheral system 10 such that data stored in cache 40, which is a selected partial replication of data stored in DASDs 16, is that data most likely to be accessed by hosts 11. Cache 40 is constructed to provide a data transfer rate not less than the data transfer rate of the fastest channel attaching peripheral system 10 to hosts 11. 
     The data transfer rates of DASDs 16 determine the minimum channel data transfer rate usable with such DASDs. That is, once a data transfer is initiated with a DASD, then the data transfer rate of that DASD determines any nonbuffered data transfer rate for all connected units. Accordingly, for a channel 13, 14 to operate directly through I/O connection 12 with a DASD, that channel must have a data transfer capability of not less than the data transfer rate of the DASD. Also, the main storage (not shown) of hosts 11, or other store that the channels may use to supply or receive data to or from a DASD, must have a capacity to transfer a minimal sized block of data signals. 
     As new DASDs are developed, the data transfer rates generally increase. It is also desired that these newer high transfer rate DASDs be connected to diverse types of hosts; some of these hosts may have I/O channels with the data transfer rate less than that of the new DASD. Such I/O channels are called slow channels 14; fast channels 13 have a data transfer rate capability of not less than the data transfer rate of a DASD. It is also desired and is provided by the present invention to enable a peripheral data storage system to connect to a diversity of fast and flow channels and yet provide data in cache 40 which is most likely to be used by hosts 11 while selectively permitting direct data transfers between hosts 11, fast channel 13 and DASDs 16. The invention also eases host programming requirements by interpreting certain channel commands in accordance with the data rate capacity relative to the peripheral device data rate of the channel which will handle a given data transfer. Cache 40 provides a rate changing buffer between DASDs 16 and slow channels 14. In accordance with the invention, operations of peripheral system control 31 are modified in accordance with whether a fast channel or a slow channel is currently transferring data to or from peripheral system 10. The operations of the channels can be mixed. For example, data may be supplied by fast channel 13 to peripheral system 10, while slow channel 14 may fetch such data. In a multipathing environment a command can be received over one channel while the data transfer can occur over another channel. The operations of control 31 automatically adjusts in accordance with which channel is currently accessing peripheral system 10 with respect to data to be transferred within a given chain or chains of I/O commands (such chains of command are those chains used in the IBM 370 series computers and the like). In this manner, control 31 and host 11 efficiently cooperate with no particular control structures required except the knowledge by peripheral system 10 of the relative data transfer capability of the I/O channel attaching the peripheral system 10 to hosts 11 and certain host supplied intent signals. 
     The storage hierarchy of peripheral system 10 includes a system storage 30 of the semiconductor random access type which has a portion 40 designated as a cache for DASDs 16. Control 31 receives peripheral commands from hosts 11 for accessing DASDs 16 or cache 40 based upon DASD 16 addresses. Data is automatically transferred by peripheral system 10 between cache 40 and DASDs 16. These transfers use the same known principles of transfers as between host 11 and DASDs 16. That is, hosts 11 access DASDs 16 in a direct mode (bypass cache) via channel adaptors 32, also individually denominated CAA, CAB, CAC and CAD, then over bus 70 using direct access control 56, data flow circuits 33, device adaptor DAA 34 and device control attachment DCA 35. Received peripheral commands (also referred to as channel command words, CCWs) are interpreted by control 31 for determining the direction of data flow between hosts 11 and DASDs 16 as well as other functions, as is well known for controlling this type of storage apparatus. That is, while hosts 11 provide control via a series of peripheral commands, the control 31 provides data transfers between cache 40 and DASDs 16 by using a plurality of internal command words (ICW) which are structured in a similar manner to the CCWs. Certain efficiencies in data transfers can be provided by altering the ICWs with respect to the CCWs. The ICWs, instead of going through the channel adaptors 32, more from control 31&#39;s cache access control CAC 61 (which operates system storage 30) directly over path 66 to direct access control DAC 56. DAC 56 responds to the ICWs in the same way it responds to CCWs; hence, this detail is omitted. Each ICW includes a command byte corresponding to a command byte of a CCW. It should be appreciated that the code permutations for identical commands are the same. Some additional ICW commands may be provided. Each ICW may also have a command modifier byte similar to the command modifier byte of a CCW. Each ICW also includes a chain control bit &#34;CHAIN&#34; which replaces the chaining indication normally provided by hosts 11 to control 31 via channel adaptors 32. (The chaining indication by host 11 is the supplying of a SUPPRESS OUT tag signal at final status time.) Since CAC 61 does not use tag signals, the ICW command modifier byte having a &#34;chain&#34; bit replaces that tag control signal. 
     Cache 40 transfers data signals through channel adaptors 32 with hosts 11 via bus 41. In a similar manner, data signals are transferred between DASDs 16 through data circuits 33 to cache 40 via bus 42. When simultaneous transfers between cache 40 and hosts 11 or DASDs 16 are not required, buses 41 and 42 are combined into a single bus which is time shared by the data transfers. Accessing cache 40, which can be a relatively large memory (several megabytes), requires CAC 61 to transfer the host supplied device address together with the cylinder and record addresses CHR over bus 72 to a hash circuit (not shown) of system store 30. The hash circuit, which may be microcode implemented, converts the DASD address into a hash class indicator. Since the storage capacity of cache 40 is much less than DASDs 16, the address range of DASDs 16 are concentrated into classes called hash classes for ease of cache access. A scatter index table SIT 45 in systems store 30 has one register for each of the hash classes. The contents of the registers in SIT 45 are address pointers to a directory DIR 43 which contains the address DCHR used to access DASDs 16. When data is stored in cache 40, the DASD 16 DCHR address together with the cache 40 address is stored in a so-called entry of DIR 43. Since a plurality of DASD 16 addresses corresponds to one hash class, a singly-linked hash class list is provided in the entries of DIR 43 such that scanning cache 40 using hashing only requires scanning the entries within a given hash class. Based upon the contents of directory 43, cache 40 is accessed using known techniques. If no related entries are found in directory 43, then a miss occurs requiring CAC 61 to either allocate space in cache 40 for receiving data from hosts 11 or to transfer data between DASDs 16 and cache 40 or host 11 as will be explained. The identification and operational status of each DASD is kept in a respective one of device control block registers of DCB 62. 
     Control 31 includes the usual portion of those control units that attach system 10 to hosts 11. For example, address and command evaluator ACE 50 communicates with channel adaptors 32 via buses 51, 52, 53 and 54 for receiving command signals from hosts 11 and supplying status signals to hosts 11. ACE 50 evaluates the received CCWs and instructs peripheral system 10 to perform the commanded function as well as indicating the chaining conditions and receiving status signals from the other portions of the peripheral system for relaying to hosts 11. ACE 50 supplies the commands to either DAC 56 or CAC 61, DAC 56 responds to ACE 50 to control data flow circuits 33 as in present day DASD storage systems; CAC 61 searches directory 43 or activates DAC 56 using ICWs. 
     When CAC 61 detects a cache miss indication from searching the hash class of DIR 43, a request for a data transfer from DASD 16 to cache 40 is supplied over bus 66 to DAC 56. A bus 66 signal alerts DAC 56 to the request and identifies the ICWs. In the preferred microcode embodiment, the transfer over bus 66 is a microcode controlled transfer, as will become apparent. DAC 56 responds to the ICWs in the same manner that it responds to the host CCWs. Upon completion of the CAC 61 requested data transfer, DAC 56 supplies status signals over bus 66 to CAC 61. At that time, cache 40 has data available for host 11. This procedure is always followed for transferring data from a DASD 16 through slow channels 14. For efficiently handling these data transfers, a set of queuing registers 67 queue DASD-related operations requested by CAC 61. In this manner, DAC 56 may not be concerned with the queueing requests to the DASDs but can operate in the same way for either host 11 or for CAC 61. In this manner, DAC 56 cannot only be used in connection with the hierarchy, but can be identically used when cache 40 is bypassed or deactivated. 
     CAC 61 also includes additional controls, for example, register ADEB 76 contains one entry of directory 43 with which CAC 61 is currently operating. That is, the address of a DASD 16 resulted in a cache hit or a portion of cache 40 was allocated to data to be supplied by host 11; by placing the entry in register ADEB 76, operation of CAC 61 is enhanced. Directory 43 is a part of system storage 30; by placing the active entry in ADEB 76, system storage 30 is free to transfer data over buses 41 and 42 independent of control 31. 
     FIG. 2 is a block diagram of a preferred embodiment of the invention which employs a programmed microprocessor 31P in control 31. Bus 70 extends from channel adaptors 32 to data circuits 33 and operates in an identical manner as shown in FIG. 1. Buses 41 and 42 respectively extend from channel adaptors 32 and data flow circuits 33 to system storage 30. Buses 41 and 42 may be combined into one bus with data transfers time sharing the single bus. Processor 31P in controlling the data transfers between data flow circuits 33 and system storage 30 provides control signals over bus 71 to circuits 33 and address and sequencing control signals over bus 72 to system storage 30. 
     Operation of processor 31P is in accordance with microcode programs stored in control store 73 which is preferably writable, although a portion can be writable while another portion containing certain programs can be read-only. Bus 74 couples processor 31P to control store 73. Within control store 73 are programs ACE 50P which implement the functions of address and command evaluator 50, DAC 56P which are programs which implement the functions of direct access control 56, CAC program 61P which implements the functions of cache access control 61 and OP 75 which are other programs necessary for operation of the storage system 10 but which are not necessary to an understanding of the present invention. The registers used by processor 31P to control the system 10 via the programs 50P, 56P and 61P include channel control block CCB 63, (which contains status and control information about a current data transfer with a channel 13, 14), DCB 62, queue registers 67, ADEB 76, SIT 45, bound list 60 (lists data bound or pinned in cache 40) and DEV-D 20 which indicates in given chains of commands which DASDs 16 are to be accessed directly (D=1) and which are to be accessed via cache 40 (D=0). Registers DCB 62 and DEV-D are pertinent to an understanding of the present invention. For an extremely large cache 40, SIT 45 can be stored in system storage 30. To enhance performance, a set of registers for containing a page of SIT 45 can be reserved in control store 73. In a peripheral system employing two storage directors or central units each having a separate control 31, system 10 and data integrity purposes, certain control data structure should be stored in a commonly-accessible storage unit, such as system store 30. These control data structures include directory 43, SIT 45 and bound lists 60. 
     FIG. 3 is a generalized showing of machine operations useful for understanding the environment in which the present invention is practiced in the FIGS. 1 and 2 illustrated system. Numerals 80-91 refer to peripheral or input/output type of operations within a single chain of peripheral commands. A chain of commands in many computers are indicated by a tag-out signal called &#34;SUPPRESS OUT&#34; from the host to the peripheral system at final status reporting time. Removal of the &#34;SUPPRESS OUT&#34; tag signal at final status time indicates the end of the chain, as at 91. Each chain can be initiated by so-called MODE-SET command at 80. The MODE-SET command supplies control signals to the peripheral system 10 from host 11 indicating to the peripheral system the type of operations to be performed as well as how to interpret some of the commands in the command chain. The MODE-SET command may result in a mode being set that extends over a plurality of chains. Accordingly, not every chain of commands need start with a MODE-SET command. Further, within certain limitations, MODE-SET commands can be interspersed between other commands in a chain of commands for changing modes of operation of the peripheral system. An exemplary MODE-SET command is described later with respect to FIG. 5. 
     In a DASD environment, a host 11 sends a SEEK command at 81 instructing the peripheral system to adjust the DASD radial head position to accommodate ensuing data transfer commands. An example of the SEEK command is to seek the head to a particular cylinder (all tracks at one radial position) of the storage surfaces of a DASD. Once the cylinder of tracks is accessed by the SEEK command, as at 81; then the rotational position of the recording surface must be set by a SET-SECTOR command at 83. This action can be followed by a SEARCH command at 84 for identifying a record at a given rotational position roughly indicated by the SET-SECTOR command at 83. The SEARCH command at 84 is followed by a data storage area access type command at 85 which can be a READ command or a WRITE command. All of the functions, 83, 84 and 85 are termed references to a track. Such references in combination with the control information of the MODE-SET command at 80 and the type of operations at 85 have a controlling effect, on the internal operation of peripheral system 10, as will become apparent. 
     In accordance with the invention, the control of accesses to the data storage area, either to cache 40 or to DASDs 16, requires certain pre-access functions to be performed, as at 86, as well as some post-accessing functions at 87. Such accessing functions are described later with respect to the machine operations chart of FIGS. 7 and 8. Numeral 90 indicates that a plurality of commands in a series of reads and writes can occur within a single chain of commands. The end-of-chain is detected at 91. Then, in accordance with the invention, certain post-chain operations occur at 92. Such post-chain operations are illustrated in the machine operations chart of FIG. 9. The term post-chain means the operations are initiated between the ending of one chain and the beginning of a subsequent chain of commands. For reducing the number of asynchronous data transfers in the peripheral system 10, such as between cache 40 and DASD 16, the post-chain operations 92 may be deferred until a next start I/O (SIO) is received from host 12 but before the first command of the succeeding chain is executed. In the alternative, post-chain operations 92 may occur immediately following detection of the end of the chain at 91. Post-chain operations 92 schedule and set up asynchronous operations at 93. Such asynchronous operations include the transfer of data signals from DASD 16 to cache 40 in preparation for a succeeding READ command to be received from host 11, transfer of data from cache 40 to DASD 16 in connection with space management of cache 40 or in response to certain control signals received from host 11, as well as other operations as will become apparent. 
     FIG. 4 illustrates directory DIR 43 and device control block DCB 62 data structures usable with the present invention. Directory 43 includes a plurality of addressable registers 100 preferably within system electronic random-access storage 30. There is one register 100 for each of the allocatable portions of cache 40. When backing store 16 contains DASD, then the allocatable portions are preferably the extent of storage areas required to store the data contents of one DASD track. In other arrangements, a track of DASD data may be broken into segments or record areas. In those situations where the record areas are fixed lengths, then the allocatable storage space of cache 40 can be set to those record area sizes. In any event, there is one register 100 for each of the allocatable storage areas of cache 40 which also are addressable units. HL&#39;s (hash class linkage list) 101, in registers 100, constitute a singly-linked list for identifying a hash class, i.e. an addressing segment of cache 40 based upon the addressing structure of backing store 16. Such hash addressing is known and not detailed for that reason. Index 102 is useful for identifying the directory 43 registers 100 without address hashing through HL 101. DADDR 103 contains the device address of backing store 16 containing the cache stored data; the address includes denomination of which DASD is being addressed, the cylinder address CC, the head or record surface address HH and a record number, if pertinent. CADDR 104 contains the address in cache 40 storing the data represented by the entry in the respective register 100. LRU 105 is a portion of a doubly-linked list having an entry in each of the registers 100 useful in replacement control of cache 40 stored data contents. One end of the doubly-linked list is the least recently used (LRU) allocatable storage area of cache 40 while the other end of the doubly-linked list is the most recently used (MRU) allocatable storage area. Updating the LRU doubly-linked list is known and not described for that reason. M bit 106 indicates whether or not the indicated data contents of cache 40 were modified by data received from a using unit 10 and the corresponding copy in DASD 16 has not yet been updated. This bit corresponds to the laterdescribed track activity vector TAV 122 in DCB 62. P bit 107 indicates that a partial track or record is stored in cache 40. Such partial track may include data from a track beginning at a given sector (rotational position indicated at set sector 83, for example) through the end of the track (index). The beginning or front position of the track is not in cache 40. B bit 108 indicates that the using unit 11, has sent a signal to the storage hierarchy 10 that the data contents of the storage area indicated by the register 100 in cache 40 is to be maintained (bound or pinned) in cache 40. Only a subsequent signal from a using unit 11 for erasing B bit 108 using known peripheral command procedures may change B bit 108. M bit 106 is reset whenever the contents of cache 40 and the backing store 16 with regard to the particular data stored are made equal, such as by demoting data to backing store 16. 
     The illustrated device control block DCB 62 is stored within programmed processor 51; such as in control store 73. Functions ACE 50, DAC 56 and CAC 61 access DCB 62 in controlling the storage hierarchy. There is one entry or register set 110 for each of the addressable devices 16 in the backing store. A first portion CCR 111 indicates whether or not a channel command retry CCR was sent to host 11 with respect to an operation related to the DASD 16 indicated by the respective register set. Tally 112 contains the later-described tally of write commands for the current chain of commands relating to the addressed DASD. Section 113 contains the current command received from using unit 11 during the current chained peripheral operations associated with the addressed DASD 16. Also, as an alternative, each CCHH search address used is also listed with identification of the last command received in the current chain of commands from using unit 11. CNL (channel) 114 is a bit significant section indicating which channel adaptor 32 received the current command. This control is used to identify fast and slow channels during peripheral operations. Section 115 contains the seek cylinder address CC for the cylinder of tracks currently being accessed. WR 116 indicates whether or not a write operation has occurred in the chain of peripheral operations; the type of write operation is indicated in tally 112. Bit MT 117 indicates whether or not a multitrack (MT) operation occurred in the current chain of commands. That is, a peripheral command may request a data transfer from a plurality of record tracks within a given cylinder CC address. D bit 118 indicates a direct mode access was made to the device during the chained peripheral operation, such as caused by a cache miss. That is, for a fast channel 13 if cache 40 does not have space allocated (cache miss) to service a data access request (read or write), then within the cylinder CC data direct accesses to backing store 16 satisfy the current request as well as all subsequent accesses within the cylinder and within the chained peripheral operation. C bit 120 indicates that cache 40 was accessed or intended to be accessed (cache operating mode as opposed to a cache bypassing mode, such as taught in U.S. Pat. No. 4,075,686). When both bits D 118 and C 120 are set to unity, a cache miss is indicated and recorded in miss bit 127. F bit 121 indicates that the channel adaptor 32 currently active is connected to a fast channel 13; with F=0 a slow channel 14 is indicated. Track activity vector TAV 122 contains one bit position for each record track in a cylinder set of such tracks. The bits indicate which tracks were written into during the current command chain. So long as CC 115 is constant, the TAV 122 contains a bit pattern showing which tracks in DASD 16 received data being written to the storage hierarchy. TAV 122 is updated by each write command execution in a usual manner. CNL DC 123 is a field having one bit for each of the channel adaptors 32. The bits may persist between a sequence of chains. For a fast channel, DC indicates deactivation of caching for the addressed DASD 16 with respect to a given channel as represented by a channel adaptor 32. Data stored in a DASD 16 will not be promoted to cache 40 when the attaching host 11 has indicated that caching should be deactivated (DC=1) for that DASD 16. In the alternative, a signal from an attaching host 11 that caching for the device should be deactivated can apply to all channel adaptors, i.e. cache 40 will be unavailable for all references to the address DASD. In the latter instance, a channel mask relating to deactivation of caching is not needed. Deactivation of caching for a slow channel 14 results in all references in cache 40 for the slow channel being made least recently used, i.e. first replaced. 
     In a similar manner, CNL IC 124 indicates that caching is inhibited for the DASD 16. That is, data access references to DASD 16 made by the current command chain result in no tracks being good candidates for promotion to cache 40. Such host system 11 references are either a stand alone reference to the cache or in a group of references which cannot take full advantage of cache. For example, reference patterns which do not benefit from caching are those access references spread randomly across a large set of tracks, i.e. the peripheral system 10 cannot predict which data to promote to cache 40 for enhancing performance. Also, when command chains have been optimized to DASD operating characteristics and there are large units of data being transferred, as an example a memory dump which results in transferring a plurality of tracks in a fast sequence, may not benefit from caching. Where references to the DASD are series of recording or write operations during inhibit cache loading, following completion of such a command chain to which the IC attribute applies, no data from DASD 16, are promoted to cache 40 except to make currently resident data stored in cache 40 consistent with DASD updates performed by the command chain. For example, any data bound to the cache by the B bit 108 will be updated such that there is congruence of data between the cache 40 copies and the DASD 16 copies. If the current command chain modified only the last track referenced and that track image is inconsistent (noncongruent) with the current contents of DASD, that track image in cache 40 is updated from DASD 16 except for the two following specific instances; sequential data is being processed or multiple writing operations occurred in the current chain of commands. 
     Any copies of data which have become incongruent with the DASD 16 data copies as a result of executing command chains are demoted from cache 40. It should be noted that the IC attribute is a property of the current reference pattern and not a property of the data, per se. Therefore, any access involving the IC attribute to a DASD track which does have an image in cache is not an indication that that particular data should be demoted from cache; i.e. some other references may have caused the data image to be promoted into cache 40. The IC attribute also does not indicate that earlier data promotions were incorrect. Accordingly, the cache 40 copy of the data should continue to reside in cache subject to the replacement algorithm, as if the IC attribute reference had not occurred. For this reason, the IC attribute with respect to an image of data in cache does not cause that data&#39;s position in the LRU list to be adjusted. All of the above relates to fast channel 13 operations. For a slow channel 14, any data arriving into cache 40 during execution of a command chain with an IC attribute active are identified at the bottom of the LRU list making such data the more likely candidates for replacement. It should be noted that data in the cache 40 related to the addressed device 16 but not placed in cache 40 as a result of the current references to the addressed DASD are not subject to these controls. 
     BC bit 125 indicates that the cache should be bypassed for the current command chain. When BC is specified in a mode set command, host 11 during the current command chain works directly with DASD 16 as though there were no cache 40 in existence. The cache directory 43 is not searched; a reference to a track in DASD which happens to have a copy of its data in cache 40 does not result in any adjustment to the replacement algorithm LRU list ordering. In this mode, all write commands are preferably inhibited in any command chain subject to an active BC attribute. The reason for this inhibition is for data integrity. During a BC attribute, a write command could cause data to be recorded into a DASD 16 without updating cache 40. As a result there will be noncongruent copies of data in the storage hierarchy resulting in a loss of data integrity. The above applies for fast channel 13 operation. For a slow channel 14, which always requires the use of cache 40, all data subject to the bypass cache attribute results in the data being identified as least recently used data, making the data most likely candidates for replacement. From the above, it can be seen that for fast channel 13 operations, the controls relating to certain usages of cache have a given effect, i.e. actually intend to avoid usage of the cache. When the storage hierarchy is attached to a slow channel 14, then such cache usage attributes result in associated data being the least recently used, i.e. the best candidate for replacement. 
     CNL SEQ field 126 is a bit significant field indicating which channel adaptor 32 is to transfer sequential data within the current chain of commands (the bit is reset each time a chain of commands is terminated). The effect of the sequential data control on the operation with a fast channel 13 and a slow channel 14 within a chain of commands is described later. Both of the data structures shown in FIG. 4 will contain other controls not pertinent to the understanding of the present invention but which may be desirable for operating a storage hierarchy. 
     FIG. 5 diagrammatically illustrates a mode-setting command, such as received in a chain of commands as a first command, as at 80 in FIG. 3. It is to be understood that such mode-setting commands can be received at any time within a chain of commands. As will become apparent, the effect on system 10 of such a mode-setting command varies depending upon its location within a chain of commands. The actual mode-set command structure 130 includes a DADDR field 131 which identifies the DASD 16 being addressed. This field is the first byte sent accross I/O connection 12. Such DADDR signals are supplied when the &#34;ADDRESS OUT&#34; tag signal is being supplied by host 11. Such signals form a part of the 360-370 input/output interface and are not shown for that reason. Command byte 132 identifies the command as a mode setting command. A plurality of bits 133-138 are contained in the command modifier byte for storage in peripheral system 10 and usage, to alter system 10&#39;s modes of operation. These bits being zero is a normal mode of operation. Any bit being set to unity indicates that a change in system 10 operation is to occur as set forth below. B bit 133 being set to unity indicates that all of the data defined in extent field 139 is to be bound or pinned to cache 40. Execution of the mode-setting command results in the data identified by extent field 139 to be placed into bound list 60 (FIG. 2) contained in control store 73 (in system store 30 for a two control unit embodiment) as well as setting the bit 108 of directory 43 (FIG. 4). As a part of executing the mode set command, that data is promoted to cache 40 from DASD 16. Bit 133A indicates that the data defined in extent field 139 are to be unbound (UB) from cache 40. Bit 108 is reset to indicate the unbind command. Bits 133 and 133A are never simultaneously set; if both are reset, no bind or unbind action occurs. SEQ bit 134 indicates that the next several data transfers will be largely sequential data. This bit results in CNL SEQ field 126 being altered for the duration of the current chain of commands in accordance with the channel adaptor through which the current mode-setting command was received. IC bit 135 sets the corresponding bit in CNL IC 124 of DCB 62 in FIG. 4. In a similar manner, bits BC 136 and DC 137 respectively result in bits 125 and 123 being set to the active condition for the respective channel adaptors. DSS 138 indicates that system store 30, including cache 40, should be deactivated. It should be noted that using diagnostic procedures, peripheral system 10 can deactivate system storage 30 to prevent loss of data integrity. Numeral 140 indicates other fields may be used in connection with mode-setting commands, such as establishing upper and lower bounds of access, setting file masks for controlling writing into DASD 16 and the like; all of such mode-setting controls are not pertinent to an understanding of the present invention. 
     A mode-setting command supplied by a host 11 is received by peripheral system 10 in the usual manner through channel adapter 32. ACE 50 receives the mode-setting command via one of the buses 51-54. The command is decoded and evaluated using known techniques. When ACE 50 recognizes a command as a mode-setting command, it forwards the received command and the command modifier data to CAC 61P for execution as shown in the machine operations chart of FIG. 6. CAC 61P, a program in processor 31P, receives the mode setting command at 145. At 146, B bit 133 (FIG. 5) is examined. B bit 133 will indicate to peripheral system 10 that data defined in the extent field 139 is to be bound to cache 40. If B bit 133 is zero, then it is possible that data currently bound to cache 40 is to be unbound. At 146A, UB bit 133A is examined. If it is zero, no changes will be made to bound status, processor 31P proceeds to logic path 149. For an unbind indicated at 133A, at 147, 148 processor 31P examines directory 43 to unbind the data indicated in extent field 139. At 147, directory 43 is examined (using extent field 139) to address one or more tracks indicated in the extent field for examining the respective B bits 108 (FIG. 4) indicating what data is currently bound to directory 43. All of the data in directory 43 identified by the scan at 147 are added to the LRU list at 148, i.e. all of the DASD tracks having data in cache 40 are made least recently used (TRK=LRU). This act is achieved by adding the tracks indicated in extent field 139 to the LRU input of the doubly-linked list in directory 43 occurring in section 105 (FIG. 4). If there are no data bound to directory 43, step 148 is omitted allowing processor 31P (CAC 61) to follow logic path 149 to then execute later described steps. 
     When B bit 133 is unity, then at 150, extent field 139 is scanned. If the extent field is zero, an error condition is logged at 144 for reporting to host 11. Optionally, an error exit from execution of the mode-setting command may be taken. Returning to step 150, based upon the contents of extent field 139, directory 43 is scanned for each track having an entry in directory 43 which is also identified in extent 139. Processor 31P accesses directory 43 at 152 to set the B bits 108 of the respective directory entries identifying the data signified in extent field 139 for binding that data to directory 43. For each miss, i.e. the data desired to be bound to cache 40 that is not currently resident in cache 40, processor 31P at 151 schedules the promotion of data from the DASD 16 addressed by the mode setting command such that directory 43 can have its B bits 108 set to unity for binding the data promoted to cache 40. Preferably such data promotions can occur before completion of a mode setting command which ensures to the host 11 that the desired bound data is in cache 40 prior to completion of the command. In the alternative, the data promotion may be scheduled and promoted asynchronously upon completion of the current chain of commands in which the mode setting command resides. Accordingly, step 151 represents not only scheduling the data to be promoted, but also the actual transfer of data signals from the addressed DASD 16 to cache 40. 
     Sequential data indicating bit 134 of the received mode-setting command is examined at 160. When sequential data is indicated for a given chain of commands, processor 31P at 161 accesses DCB 62 for setting the appropriate sequential indicator 126 for the channel adaptor over which the mode setting command was received. As an example, the illustrated peripheral system 10 has four channel adaptors CAA through CAD. In this instance, field 126 has four bits, one bit for each of the channel adaptors. The CNL field 114 was previously filled by ACE 50 upon receipt of the command from the respective channel adapter CAA-CAD as indicated by which of the buses 51-54 carried the command, for example. Logic path 162 leads processor 31P from the sequential analysis to examine bit IC 135 which selectively instructs peripheral system 10 to inhibit cache load. When this bit is active, processor 31P at 164 accesses DCB 62 field 124 to set the IC bit that corresponds to the commandreceiving channel adaptor (which also represents the channel and host which sent the mode setting command). Logic path 165 leads processor 31P from the inhibit cache load analysis to examine BC bit 136 to determine whether or not cache 40 should be bypassed during the current command chain. When BC is equal to unity, processor 31P at 171 accesses DCB bit BC 125 for setting it to unity. Logic path 172 is then followed to examine DC bit 137 at 173. When the cache 40 is to be disabled for the addressed device, processor 31P at 174 accesses DCB 62 field CNL DC 123 for setting the DC bit corresponding to the channel sending the command. The DC bits persist between successive command chains. In the three fields, 123, 124 and 126, the channel source of the mode-setting command is indicated. These bits are maintained within one chain of commands. In this manner, multiplexed operations of peripheral system 10 are provided. For the respective bits 133-137 being zero, the corresponding fields in DCB 62 are reset to zero as indicated in steps 180, 181, 182 and 183, respectively. In certain circumstances where a plurality of mode setting commands can be received within a given chain of commands, certain of the resetting functions may be inhibited. For example, the sequential bit may only be reset at the beginning of the chain of command. In a similar manner, bypass cache can only be reset at the beginning of a chain. This limitation can be used for providing system integrity by requiring the host to generate a new chain of commands for each major change in operations of peripheral system 10. 
     Following the memorization of the intent signals 133-137, processor 31P follows logic path 175 to perform other miscellaneous mode setting functions at 176. Such miscellaneous mode setting functions may include setting file masks, limiting addressing extent of a particular chain of commands and the like. ACE 50 is returned to at 177 for reporting a successful completion of the mode setting command to the sending host 11. 
     The FIG. 7 including accommodation of operational differences for fast and slow channels shows machine operations chart accessing a record and corresponds to steps 85, 86, 87 of FIG. 3. It is to be understood that for the FIG. 3 illustrated set sector 83 and search 84 steps, similar fast-slow channel accommodation occurs for ensuring that functions to be performed in the chain of commands for the respective fast or slow channels, 13, 14 are appropriate. Since accessing data performs all of the functions with regard to fast and slow channels, only data access accommodations are detailed. The received data access command can be either a read or write type. In some embodiments, a separate machine operation chart may be used for all read operations as well as for all write operations. For ease of explanation and since the functions are appropriately interrelated for read or write, a single machine operations chart is shown as a best mode of implementing the invention in that a minimal number of microcode words will be used. 
     Processor 31P upon receiving the command performs several functions in ACE 50P, as represented by numeral 190. In the processing of a received command by ACE 50P, processor 31P accesses DCB 62 for setting the register set 110 in accordance with the received command. This includes inserting the command and address information in section 113, identifying which channel adaptor 32 (viz channel) supplied the command in section 114 set MT 117 for any multitrack command (multiple track access is enabled), set F at 121 in accordance with FS map 77 and CNL 114. These same steps are performed in executing the earlier described mode setting command. 
     Upon completion of the ACE 50P portion of command processing, CAC 61P is activated for to perform the FIG. 7 machine operations, these operations include some preliminary steps 192 not pertinent to the understanding of the present invention. At 193 processor 31P, acting through CAC 61P, examines DEV-D 20 of control store 73 (FIG. 2) to determine if a previous command had set the addressed device to the direct mode D or if the addressed device is in the caching mode C for the channel adaptor 32 which received the current data access command. For a direct mode indication processor 31P at 194 examines F bit 121 to see whether the channel over which the present command was transmitted is a fast or a slow channel. For a slow channel in a direct mode the operation cannot ensue in the direct mode to DASD because the channel cannot receive data from the DASD 16 fast enough. For a write operation, the slow channel cannot supply information signals fast enough to satisfy the constant data rate requirements of DASD 16. Therefore, an error, probably an error in ACE 50P, is indicated at 195. When the host indicates direct mode (bypass cache) for a slow channel, the cache 40 is still used as later described. For a fast channel in the direct mode, processor 31P proceeds through logic path 196 to step 197 to determine whether or not BC 125 was set by a previous mode setting command. For BC 125 active and the command signified in section 113 of DCB 62 being a write command, an error may be indicated at 198. Remember, that for a bypass cache condition, writing to DASD 16 to the exclusion of cache 40 may create a data integrity problem in that cache 40 may have data relating to the write operation. The error prevents another host from accessing cache 40 through an alternate channel 32 and thereby get data that is not currently accurate. Writing to DASD can be permitted provided the corresponding data in cache 40 is appropriately invalidated or updated. From step 197, for BC=0 or not a write command, a data access occurs in accordance with step 85. For a direct access to DASD 16, at 199, DAC 56P is activated from CAC 61P to access the addressed DASD 16 and transfer data using known DASD data transfer techniques. The direct data transfer path includes data flow circuits 33, bus 70 and the activating channel adaptor 32. Upon completion of that data transfer, processor 31P follows logic path 212 to post-command processing 87, as later described. 
     Returning to step 193 of pre-command processing 86 in CAC 61P, when caching is indicated for the addressed DASD, processor 31P follows logic path 200 to perform some preliminary cache-examining steps at 201. Such steps for verifying status of cache 40 are not pertinent to an understanding of the present invention. At 202 F bit 121 of DCB 62 is examined to determine whether a fast or a slow channel supplied the present command. For a slow channel, logic path 203 leads processor 31P to search directory 43 at 204. Bypassing cache 40 from a slow channel results in data in cache 40 being invalidated and the copy of data stored in DASD being promoted from DASD to cache, as later described for caching operations. For a fast channel indicated at 202, processor 31P at 205 examines DCB 62 bit BC 125 to determine whether or not caching is bypassed for the current command chain. When caching is not bypassed, logic path 206 leads processor 31P to search directory 43 at step 204. For a bypassing cache indication, processor 31P sets DEV D 20 for the addressed DASD 16 to unity at step 208. From step 208, processor 31P goes through step 197 to direct data access step 199 of data access 85. 
     For a caching operation, from logic paths 203, 206, the directory search at 204 results in either a cache hit or miss. The directory search, remember, is based upon the DASD 16 address including device, cylinder number and track number using the above-referred to hashing technique. Based upon the results of that directory search, a known technique, processor 31P at 210 examines for a hit or miss. For a cache hit, processor 31P, at 211, examines DCB bypass cache bit 125 and section 114 for a slow channel 14. For the conditions not being met, the data transfer occurs at 212 under CAC 61P supervision by transferring data between cache 40 and channel adaptor 32. Such data transfer can be to cache 40 or from cache 40. For the conditions being met, remember the slow channels must use cache and that bypass cache BC indicates the host wants the DASD copy of the data. Therefore, at 213 the copy of data in cache is invalidated, a channel command retry CCR is sent to the host and the copy of data in DASD is promoted to cache 40. The CCR is satisfied by system 10 reconnecting to host 11 and effecting the requested data transfer in accordance with the machine operations shown in FIG. 7. Then host 11 can send additional commands. Also, upon completion of steps 199 or 212 in data access 85, logic path 214 leads processor 31P to later-described post-command processing 87. 
     For a cache miss at 210, processor 31P follows logic path 215 to send a channel command retry CCR to host 11 at 216. Such CCR is supplied also to device control block 62 section 111 such that the next received command that matches the command listed in section 113 is identified as a CCR response by host 11. The cache miss is tallied in tally section 112 for the addressed DASD 16 at 217. At 220, F bit 121 is again examined for determining whether a fast or slow channel supplied the current command. For a fast channel, on a cache miss it is desired to access DASD 16 directly to the exclusion of cache 40. 
     Accordingly, at 221 DEV D for the addressed DASD is set to unity indicating a direct access. The next time a data access command is supplied to peripheral system in response to the CCR a direct access is indicated via steps 193, 194 and 197. To prepare for the upcoming retransmittal of a data access command, peripheral system 10 at 222 supplies a set sector command to DASD 16 for establishing a DASD rotational relationship. At 219, intervening and unrelated machine operations may occur. When the conditions for SET SECTOR are satisfied, at 223 a device end (DE) is supplied to host 11 to signify that the data access command can be retransmitted. When the data access command is retransmitted, it is again decoded by processor 31P acting through ACE 50P. Then at 193 the direct access is detected and the actual access occurs through step 199. Step 199 is repeated for all subsequent data access commands for the addressed DASD within the current command chain for all tracks in the same cylinder of tracks. 
     On the other hand, for a slow channel, cache 40 must still be used. Accordingly, at 224 processor 31P schedules promotion of data to cache 40 from the addressed DASD 16. Upon completion of that asynchronous promotion of data to cache 40, the CCR 111 field of DCB 62 (which will be transferred to other control data structures not pertinent to an understanding of the present invention) will signify to processor 31P that a device end should be sent to host 11, as at 223. Host 11 then resubmits the command resulting in reexecution of FIG. 7 but with a hit occurring at step 210. This action is signified in step 224 as reconnect and transfer. At this point, all of the functions related to data access have been completed. Processor 31P then proceeds through logic path 225 from logic path 214 to perform some nonpertinent functions at 226, at 227 checks chaining and reports final status to the host 11 in accordance with known command completion procedures. 
     Post-command processing 87 begins at 230 where F bit 121 is again checked for a fast or slow channel. When the command was received over a slow channel, at 231 processor 31P examines DCB 62 fields DC 123, BC 125 and IC 124 to determine whether or not the DASD addressed data contained in cache 40 should be made LRU. In a preferred form of implementing the present invention, such data is identified as being less recently used, than presently indicated but not the least recently used data. For example, in a thousand segment LRU list, it could be adjusted one hundred segments toward the LRU end of the list or a given number of entries (e.g. 15 entries) from the LRU end of the list. That is, whenever there is a bypass cache or inhibit cache indication (caching is deactivated for an identified channel and device) from host 11, the data that was referenced is still stored in cache 40 and should be removed from cache. In the event that there was a hit at 210 (a miss indicates the data is not in cache 40), directory 43 is accessed at 232 such that the addressed track data stored in cache is made less recently used cache data by adjusting the doubly-linked LRU list of section 105. Otherwise, from step 230 or 231, as shown in FIG. 8 processor 31P examines directory 43 B bit 108 at 235 to determine if the addressed data stored in cache 40 is bound. If the data is bound and a write operation occurred as indicated by field 116 of DCB 62 as set by processor 31P in step 211 with the DASD and cache data copies still being non-congruent data from DASD 16 is promoted to cache 40 at 236 for making the cache copy congruent with DASD. This action does not occur for a slow channel. That is, the data that is stored in the retentive backing store is maintained as the congruent copy in cache 40. However, for data integrity purposes when data is bound to cache 40, that data is treated as being identical to DASD 16 data such that cache 40 and DASD 16 data contents are kept congruent. From steps 235 or 236, processor 31P follows logic path 237 to perform some nonpertinent functions at 238. Then at 240, WR bit 116 is again examined. If a write occurred in the current command chain, the write is tallied at 241. The tally includes identification of a format write and the like. At 242, DCB 62 is examined for updating the track activity vector 122. 
     Programmed processor 31P then proceeds over logic path 244. A fourth check at 249 is for a received command which is a device-related command. This type of command includes the RECALIBRATE command as used on present day DASD. When the checks are performed after command execution, step 248 occurs in command preprocessing, such as by ACE 50P steps 192 of FIG. 7. Then it determines at 249 whether or not there was a change in operations of a fast channel due to a cache miss (DCB 62; MISS 127) and DEV D=1 (number 20, FIG. 1). If a miss resulted in direct access to DASD 16 (fast channel 13), such direct access is limited to a cylinder of tracks, a chain of commands or address extent as checked by check steps 250. These check steps may be performed for each command upon sending final status to using unit 11 or upon receiving a next peripheral command but before execution of such next peripheral command. At 251 processor 31P checks for end of the chain (EOCH) which was detected by the absence of the SUPRESS OUT tag signals at final status time. The second check at 252 is for the end of the cylinder (EOCYL); that is all of the set of tracks within a cylinder have a predetermined address space, tracks 1 through 17, for example. Depending upon the addressing increment direction, i.e. increasing or decreasing track addresses, upon completion of an access to a track, the next track can be in an adjacent cylinder or within the same cylinder. If the next track to be accessed is expected to be in an adjacent cylinder, then at 261 programmed processor 31P resets DEV D 20 to zero to reinstitute caching. The third check at 253 is for out of bounds (OOB). It is common practice in present day DASD peripheral systems to have a define extent (mode setting) command received from a using unit 10. A define extent command establishes a range of addresses which defines bounds of permitted access. Accordingly, if programmed processor 31P in processing the peripheral command indicates that the address being processed is at the boundary of the defined extent; then an out of bounds condition occurs, i.e. the next desired access will be outside of the previously defined extent, i.e. a change in operation in that access to the data area will be denied if attempted without an intervening DEFINE EXTENT command that extends the extent. 
     If all of the steps 248-253 result in no branch being taken, then programmed processor 31P returns to ACE 50P via return 255 for receiving another command and to schedule asynchronous operations within peripheral system 10. If any one of the conditions set forth for step 250 are met, then programmed processor 31P follows logic path 260 to reset DEV D 20 to the C (caching state) for the addressed DASD 16. Following step 261 or from step 249 (with no cache miss or operations with a slow channel), processor 31P returns to ACE 50P via return 255. 
     FIG. 9 shows post-chain operations 92. Upon complet:on of a chained peripheral operation 270, as detected at 271 by ACE 50P after final status has been sent to host 11, the tallied status bits stored in tally 112 of DCB 62 are examined by processor 31P as a branch control for executing branches 272. Branches 272 are the usual branch instructions within programmed processor 31P. A first branch instruction 273 examines the sequential bit SEQ 126 of DCB 62 received from a using unit 11 for chained peripheral operation 270 and whether a write command was received in that chain as indicated by WR 116 of DCB 62. If the write occurred via a fast channel, then logic step 275 deletes the data contents of cache 40 corresponding to the DASD 16 altered data by erasing the corresponding directory 43 entries. For a slow channel, all tracks referenced in cache 40, except the last track referenced, are deleted from cache. The last track referenced is made less recently used. In a similar manner, at 274 a format write (FMT) was executed (tally 112) and cache 40 was not updated, i.e. all writing was to DASD 16. When this occurs, logic step 275 is also performed. If neither of the conditions in branch steps 273, 274 are satisfied; then at 280, if a format write command was received and a write operation was made to cache 40 via CAC 61P, then logic path 283 is followed to step 284 for moving the altered data from cache 40 to DASD 16 and then delete that data from cache 40. Even with the end-of-chaining condition at 271, the chain of commands have not been completed by system 10. That is, in response to the host signalling &#34;end-of-chain,&#34; system 10 supplied a CHANNEL END but no DEVICE END telling host 11 that data is still to be written from cache 40 to DASD 16. Upon completion of such demotion, system 10 sends a DEVICE END using the usual procedures for late DEVICE END reporting. In a similar manner at 281 if a write to cache 40 occurred when sequential data is indicated (SEQ 126=1), then such updated tracks, except the last track referenced, are removed from cache 40. Also, at 282 when the number of records updated in a track stored in cache 40 is greater than one, then those tracks are removed from cache 40. If none of the conditions in steps 273 through 285 are satisfied, then the sequential attribute set forth in SEQ bit 126 of DCB 62 has been received for the current command chain and no writing has occurred. For sequential data, processor 31P wants to determine data promotion and demotion for the sequential data set. This promotion and demotion is determined differently for fast and slow channels. Accordingly, at 290 processor 31P examines F bit 121 for the current command chain that was just completed. If the F bit is set to unity for data promotion relating to a fast channel, processor 31P at 291 examines whether the cache inhibit IC bit 124, bypass cache bit 125 and deactivate caching bit 123 are zero and the extent of the data transfer to host 11 from peripheral system 10 (please remember that there were no writes in the command chain). A data transfer must be not greater than a given percentage of the track capacity, for example, one-half of a track. The size of the data transfer is monitored during data access portion 85 which includes a byte count (not shown) stored in control store 73 for the duration of a command chain. Since the capacity of each DASD storage track is known, at the completion of the chain of command, the tallied byte count for the current command chain for each of the tracks accessed is compared with the track capacity to determine the amount of data transferred to host 11. For all of these conditions met or a slow channel was involved with the command chain, processor 31P at 292 transfers the track following the last track referenced (LTR) to cache 40 from DASD 16. LTR is identified in section 113 of DCB 62 for the last command in the chain. Then at 293, processor 31P causes the track immediately preceding the last track referenced to be demoted from cache 40. 
     From steps 275, 284, 285, 291 and 293, logic path 295 leads processor 31P to step 296 whereupon directory 43 is accessed (ADEB 76 may still contain the entry and therefore may be accessed in lieu of accessing directory 43) to read P bit 107. If P bit equals unity, a partial copy of the data in last track referenced is currently residing in cache 40. If this is the case, at 297, processor 31P actuates DAC 56P to promote data from DASD 16 to complete the partial copy in cache 40. Generally a partial copy is copied into cache 40 in a manner that the last portion of the track, i.e. the portion of the data immediately preceding the index mark is in cache 40. Therefore, finishing the track promotion amounts to promoting the first part of the track through the first referenced point (which marks beginning of the copy in cache 40) into cache 40. To reduce data promotion times, such promotion of the first portion of LTR is deferred until a cache miss occurs as a result of accessing such unpromoted first portion. At this preferred arrangement, step 297 is incorporated into step 224 of FIG. 7. 
     From step 297 or 296 processor 31P follows logic path 298 to perform further data promotion analyses. At 300 for a fast channel supplied command in the immediately preceding chain of commands, processor 31P at 301 examines DCB 62 DC bit 123, IC bit 124, WR bit 116 and operational status (SSNA system storage not available) cache of 40 for determining its availability. If cache 40 is not available or any of the other criteria were set to unity, then all inter-chain or asynchronous data promotion is inhibited. Processor 31P then proceeds directly to terminating steps 302 which enables processor 31P to exit the post chaining operation. On the other hand, if none of the above-stated conditions are met, then at 306 processor 31P examines miss bit 127 of DCB 62 for the device address of the immediately preceding command chain. For a cache miss with a fast channel at 306 the last track referenced (LTR) is promoted on a selective basis to cache 40. For a slow channel all promotion has occurred except in sequential data processing the data contents of the next track to be accessed has not yet been promoted. If the last data access or reference from the miss (which could have been satisfied by directly accessing DASD 16) is in the last 80 percent of the track immediately preceding the index mark, then that portion is promoted to cache 40. That is, that portion from the point of reference to the index mark. If the reference to LTR was in the first 20 percent of the track, then the entire track is promoted to cache 40. The percentages can vary from the last 98 to the last 40 percent. Again, LTR is identified in field 113 of DCB 62. For no cache miss having occurred; there is no data promotion, i.e. the data is already in cache 40. 
     For a slow channel, processor 31P at 308 determines whether or not a host 11 has sent a set sector command for LTR. For a set sector command, processor 31P at 309 promotes that portion of the data track from the sector identified in the said sector to the index mark, i.e. a partial track promotion. For a slow channel, partial track promotion occurs at step 86 of FIG. 3 (synchronous to the I/O operation). Step 92 promotes the next track in sequential data for the slow channel. A host sending the set sector command is signifying to the peripheral system 10 that the host is interested in data beginning at the sector identified in the set sector command. Accordingly, only that data which is indicated as being of interest to the host is promoted. Without a set sector command being detected at 308, processor 31P at 310 promotes the entire track of data of any track referenced by the host such as in a seek command but did not have a set sector command. From steps 309, 310, processor 31P proceeds to ending nonpertinent steps 302. 
     Upon completion of the post chaining operation, processor 31P proceeds to look for new work. For example, at 315 if a new operation (new op) or a new command was received from host 11; then logic path 316 would follow to perform new operations. Such a new operation may also be an alert signal received from a DASD 16. Upon returning from such operations as via path 317 or if no new operation occurred at 315, processor 31P proceeds via path 318 to step 320 for scanning the LRU list 105 of directory 43 (FIG. 4) up to a given threshold, for any data identified in cache 40 that has the M bit 106 set to the active condition. Such data is demoted from cache 40 to DASD 16 at 321. The processor 31P proceeds to look for additional system work in a usual manner. 
     While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.