Abstract:
Embodiments of a pipeline analog-to-digital converter is provided. In accordance with some embodiments, a pipeline analog-to-digital converter includes a stage, the stage including a residue amplifier that amplifies a residual voltage generated by the stage to obtain an amplified residual voltage; a backend digitizer that digitizes the amplified residual voltage to generate a digitized residual; and a digital correction circuit that corrects the digitized residual according to which zone the digitized residual is found.

Description:
TECHNICAL FIELD 
       [0001]    Embodiments of the present invention are related pipeline Analog-to-Digital converters (ADCs) and, in particular, digital correction of residue amplifiers involved in stages of a pipeline ADC. 
       DISCUSSION OF RELATED ART 
       [0002]    Analog-to-Digital converters are used anywhere there is a need to digitize analog signals. High performance ADCs are used in numerous applications and are typically characterized by operating at higher clock frequencies, with higher resolution, and at lower power consumption. One large application for high-performance ADCs is in telecommunications base stations, which receives large numbers of incoming signals that are all digitized. In such cases, the desired clock frequencies are typically in the GHz range. Further, because of the need to process a large number of input signals, the demand for a high number of ADCs on a single die is high. 
         [0003]    One type of commonly used ADC is a pipeline ADC. A pipeline ADC includes a number of series connected stages, where each stage receives an input voltage. The input voltage may be the input voltage to the ADC if the stage is the first stage or a residue voltage received from the preceding stage in the pipeline. Each stage roughly digitizes the input signal and produces one or more bits of digitized data. The digitized portion is subtracted from the input voltage resulting in a difference voltage, which is amplified in a residue amplifier to generate a residue voltage. The residue voltage is then the input voltage to the following stage. The digitized data from each stage is then summed appropriately to form the digitized representation of the ADC&#39;s input voltage. 
         [0004]    One of the limiting factors involved with ADCs is the quality of residue amplifier that is involved in each stage of the pipeline-ADC. High quality, linear amplifiers where the gain is well known are difficult and expensive to produce, especially in the numbers that are often used to obtain the necessary processing. The consequence is that ADCs are being implemented in more advanced complementary metal oxide semiconductor (CMOS) nodes. Advanced CMOS technology exhibits high performance for digital processing. Further, analog processing benefits from the higher speed and lower power consumption of digital-like functions such as clocks and comparators. However, high quality linear amplifiers are more difficult to achieve in Advanced CMOS technologies because the intrinsic gain of the transistors is smaller and the voltage range is also smaller. 
         [0005]    Digital correction of some of the difficulties of the residue amplifier has been proposed. For example, a statistically based background digital calibration of the residue amplifier is described in “A 12b 75 MS/s Pipelined ADC Using Open-Loop Residue Amplification,” Boris Murmann and Berhard E. Boser, IEEE Journal of Solid-State Circuits, Vol. 38, No. 12, December 2003. However, the statistically based extraction method as described in Murmann &amp; Boser is slow, requires a large sampling base to converge, and requires dynamic analog references that add complexity to the analog processing. Another calibration procedure was disclosed in “A 12-Bit 200-MHz CMOS ADC’, Bibhu Datta Sahoo and Behzad Razavi, IEEE Journal of Solid-State Circuits, Vol. 44, No. 9, September 2009. However, although some samples are reserved for calibration, no background extraction for non-linearity is provided. Another correction algorithm is provided in “A 130 mW 100 MS/s Pipelined ADC with 69 dB SNDR Enabled by Digital Harmonic Distortion Correction,” Andrea Panigada and Ian Galton, IEEE Journal of Solid-State Circuits, Vol. 44, No. 12, December 2009. However, the approach provided requires multiple pseudo-random sequences and resultingly complicated processing. 
         [0006]    Therefore, there is a need to develop high quality ADCs that can operate at higher clock frequencies with lower power consumption. 
       SUMMARY 
       [0007]    In accordance with aspects of the present invention, a pipeline analog-to-digital converter is provided. In accordance with some embodiments, a pipeline analog-to-digital converter includes a stage, the stage including a residue amplifier that amplifies a residual voltage generated by the stage to obtain an amplified residual voltage; a backend digitizer that digitizes the amplified residual voltage to generate a digitized residual; and a digital correction circuit that corrects the digitized residual according to which zone the digitized residual is found. 
         [0008]    A method of correction in a pipeline ADC according to some embodiments of the present invention includes determining a gain parameter based on a backend digitized value; determining an operating zone from a plurality of zones of a transfer function that is associated with the backend digitized value; integrating the gain parameter in one of a plurality integrators associated with the operating zone; and providing a correction of the backend digitized value associated with operation within each of the plurality of zones using parameters from the integrator associated with each of the plurality of zones. 
         [0009]    These and other embodiments are further discussed below with respect to the following figures. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]      FIG. 1  illustrates a pipeline ADC. 
           [0011]      FIG. 2  illustrates a single stage of a pipeline ADC. 
           [0012]      FIG. 3A  illustrates a stage of a pipeline ADC which includes digital processing. 
           [0013]      FIG. 3B  illustrates an example of digital processing and corrections for a pipeline ADC. 
           [0014]      FIG. 4  illustrates residue transfer functions in a pipeline ADC. 
           [0015]      FIG. 5  illustrates a non-linear transfer function of a pipeline ADC. 
           [0016]      FIG. 6  illustrates digital processing according to some embodiments of the present invention. 
           [0017]      FIG. 7  illustrates a transfer function using multiple zones. 
           [0018]      FIGS. 8A and 8B  illustrate performance of an analog-to-digital converter according to some embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0019]    In the following description, specific details are set forth describing some embodiments of the present invention. It will be apparent, however, to one skilled in the art that some embodiments may be practiced without some or all of these specific details. The specific embodiments disclosed herein are meant to be illustrative but not limiting. One skilled in the art may realize other elements that, although not specifically described here, are within the scope and the spirit of this disclosure. 
         [0020]    This description and the accompanying drawings that illustrate inventive aspects and embodiments should not be taken as limiting—the claims define the protected invention. Various changes may be made without departing from the spirit and scope of this description and the claims. In some instances, well-known structures and techniques have not been shown or described in detail in order not to obscure the invention. 
         [0021]      FIG. 1  illustrates a pipeline analog-to-digital converter  100 . As shown in  FIG. 1 , an analog input voltage V is received by stage  110 - 1 . Successive stages  110 - 1  through  110 -N are arranged sequentially to digitize the input voltage. Each of stages  110 - 1  through  110 -N outputs a digitized value D 1  through D N , respectively, and a residue voltage V RES1  through V RESN , respectively. The digitized values D 1  through D N  are summed appropriately in adder  112  to provide a digitized value D of the input voltage V. The last residue voltage from stage  110 -N can provide an indication of the error in digitizing the input voltage, or may itself be digitized to provide higher resolution to the resulting digitized value. 
         [0022]      FIG. 2  illustrates a stage  110 , which may be any one of stages  110 - 1  through  110 -N. As shown in  FIG. 2 , stage  110  receives a voltage V IN  and outputs a residual voltage V RES . Voltage V IN  is digitized in an analog-to-digital converter  202 , which outputs a digitized version D flash . D flash  is then converted by digital-to-analog converter  204 , which matches ADC  202 , to provide analog signal V flash . V flash  is subtracted from V IN  in summer  206  to provide a residual voltage RES. Voltage RES is then amplified in amplifier  208  to provide the digital voltage V RES  for the following stage  110 . V RES  is then further digitized in back-end ADC  210  to provide the digitized back-end D BE , which is the digitized voltage V RES . D flash , D BE , and other digitized voltages from others of stages  110  represent digitized values D 1  through D N  shown in  FIG. 1 , with D flash  being one of digitized values D 1  through D N  and D BE  representing the summed values of the digitized values from the following ones of stages  110 . 
         [0023]    In a conventional pipelined ADC, amplifier  208 —also referred to as the residue amplifier —has severe requirements in terms of gain and linearity accuracy. At each stage  110 , the settling time of residue amplifier  208  determines the maximum speed at which ADC  100  can run. These constraints result because residue amplifier is the dominant source of power consumption in pipeline ADC  100 . This issue becomes even more difficult in advanced complementary metal-oxide semiconductor (CMOS) technologies where the voltage headroom is small. For these reasons, there is a need to reduce the constraints on residue amplifier  208  in order to reduce power consumption and increase speed. 
         [0024]    As shown in  FIGS. 1 and 2 , pipeline ADC stage  110  processes an incoming input signal, V in , and delivers D flash , which is a coarse digitized form of the input signal V in . The voltage V RES  is an analog residue created by subtracting the analog value of D flash  from the input voltage V in , amplified by residue amplifier  208 . The residue, V RES , is then digitized by the backend ADC  210  resulting in the digitized value D BE . The digital equivalent of the input signal D out  is then the sum of the stage D flash , typically representing the most-significant-bits (MSBs) and of D BE  representing the least-significant-bits (LSBs). As is illustrated in  FIGS. 1 and 2 , D flash  can be any number of bits and DBE can be any number of bits. If any stages precede the particular stage  110  illustrated in  FIG. 2 , then that stage provides the input voltage V IN  of the illustrated stage  110 . Therefore V IN  may be the residue voltage from the immediately preceding stage. 
         [0025]    The gain of residue amplifier  208  can be any value. However, scaling of the digital outputs D flash  of individual stages that are combined in summer  112  to provide the digitized value representing the input voltage ADC  100  is simpler if the gain is a power of two (2), e.g. 2, 4, 8, or other power of two. For example, if D flash  is three-bits, then it is convenient for the gain of amplifier  208  to be four (which provides some redundancy). 
         [0026]    For high resolution ADCs, the residue amplifier gain should be determined with high precision. The traditional approach is to embed residue amplifier  208  within a feedback loop. The gain is therefore set by a ratio of passive elements (usually capacitors), at the condition that the amplifier open loop gain is sufficiently high (more than 80 dB typically). The residue amplifier  208  should settle within half a clock period. These and other constraints on the performance of residue amplifier  208  usually result in residue amplifier  208  being the dominant source of power consumption in a pipeline ADC  100 . 
         [0027]    Further, while implementing a pipeline ADC in advanced CMOS technologies, there are additional difficulties. For example, the voltage headroom allowed for transistors gets smaller and transistor reliability becomes an issue, resulting in increased difficulty to build a linear amplifier. Additionally, the transistor intrinsic gain gets smaller, resulting in difficulty in implementing an amplifier with sufficient gain. On the other hand, digital processing becomes more efficient at each new generation of CMOS technology. Consequently, techniques that reduce the analog implementation, even if additional digital processing is required, are highly desirable. 
         [0028]    In accordance with embodiments of the present invention, the constraint that residue amplifier  208  be linear is removed. Removing this constraint allows the use of a less linear residue amplifier  208  that results in lower power consumption, and lower cost. Digital processing can then be used to adjust the stages to correct for the non-linearity of residue amplifier  208  and discrepancies in the gain and reduce the requirements on the analog processing portions of each stage  110 . Digital processing can be much more cost and power efficient in advanced CMOS technologies than is analog processing. Consequently, in accordance with embodiments of the present invention, digital processing provides feed-back loops for correction gain and for correction of linearity. 
         [0029]    In some embodiments, a known pseudo-random sequence can be injected at the input of residue amplifier and then subtracted from the digitized value digitally. The correlation of the pseudo-random sequence with the signal after digital subtraction can determine whether the gain on the residue (both from the residue amplifier  208  and other processing) is too low or too high. Consequently, the gain of residue amplifier can be corrected. A digital feedback loop including the correlator and multiplier according to embodiments of the present invention may cause the system to converge to zero gain error. The presence of the ADC signal in the feedback loop can be averaged out by the correlator. 
         [0030]    In some embodiments, the non-linearity of the residue amplifier can also be adjusted digitally. The residue amplifier output signal can be split into multiple zones, for example an inner zone (small signals) and an outer zone (large signals). In that case, multiple correlators can be used and a particular correlator can be associated with each zone. For example, a correlator associated with an outer zone, where the non-linearity of the residue amplifier will be most evident, can be used to correct non-linearity (e.g., distortion of order  3  that dominates) while the correlator associated with the inner zone, where the non-linearity of the residue amplifier will be least evident, can be used to correct for gain errors. Both gain and linearity extraction and correction loops can be used in parallel, are fully digital, and can be operating in the background. 
         [0031]      FIG. 3A  illustrates an embodiment of a stage  300 , which can be used in place of stages  110  shown in  FIG. 1 . As shown in  FIG. 3A , the input voltage V IN , which may be the input voltage to the pipeline ADC as a whole if stage  300  is the first stage or a residue voltage from a preceding stage if stage  300  is a later stage, is received and digitized in ADC  302 . ADC  302  can be a digitizer of any bit size that produces a digital representation D flash  of V in  appropriate for its resolution. The digital output from ADC  302 , D flash , is then input to DAC  304 . DAC  304  is a digital-to-analog converter comparable with ADC  302  that produces an analog voltage V flash  according to the digital value D flash . In summer  306 , V flash  is subtracted from the input voltage V in  to generate a residual voltage. As shown in  FIG. 3A , the residual voltage from summer  306  is input into summer  310 . A digitized pseudo-random binary sequence (PRBS) from a known PRBS generator is digitized in a 1-bit DAC  308  and summed with the residual voltage in summer  310 . The resulting residual is amplified in amplifier  312  to produce V RES . As discussed with respect to  FIG. 2 , V RES  is digitized by back-end ADC  210  to result in the digitized value Of V RES , D BE . 
         [0032]      FIG. 3B  illustrates digital processing  330  of the correction for amplifier gain consistent with stage  300  shown in  FIG. 3A . As shown in  FIG. 3B , PRBS generator  314  is the known PRBS generator that generates a pseudo-random number sequence D prbs , which is input to DAC  308  shown in  FIG. 3A . Digital processing  330  includes a gain extraction  318  and a gain correction  316 . As input, digital processing  330  receives the digitized input D BE . In summer  322 , D BE  is summed with the output signal from gain correction  316  to produce a signal Da. The generated sequence D prbs  is then subtracted from D a  in summer  328 . The digitized value D flash  from the stage  300  illustrated in  FIG. 3A  is then added in summer  332  to arrive at the digitized value D out . 
         [0033]    Gain extraction  318  receives the digital value D b  and multiplies it by D prbs  in multiplier  326  to generate the parameter K 0 . Since the input signal D BE  itself is averaged out by integrator  324  and D prbs  is equal to ±1, the parameter K 0  can be given by 
         [0000]        K   0 =( GD   prbs   −D   prbs ) D   prbs   =G− 1, 
         [0000]    where G is the normalized gain defined as g act /g ideal , g act  being the actual gain and g ideal  being the desired gain. The output correction factor γ c , then, is the value K 0  integrated in integrator  324 . Since the desired overall normalized residue gain (analog and digital) is 1, once convergence is complete the correction factor γ c  should be the difference between the normalized gain and 1. For example, if the actual gain g act  is 3.96 and the ideal gain g ideal  is 4, then γ c  will converge to 0.01. Gain correction  316  multiplies the correction factor γ c  by the input value D BE  in multiplier  320  and adds that to the input value D BE  in summer  322  to correct for gain. 
         [0034]    In order to further remove operational constraints on the residue amplifier, embodiments of the present invention further compensates for residue amplifier nonlinearity.  FIG. 4  illustrates the residue transfer functions and a correction according to some embodiments of the present invention. In  FIG. 4 , the y-axis represents the output voltage of the amplifier while the x-axis indicates the input voltage of the amplifier. As illustrated in  FIG. 4 , curve  402  illustrates the analog transfer function of the residue amplifier, which illustrates significant non-linearity at the extremes and primarily linear behavior for small values. Curve  406  illustrates the digital correction that would linearize curve  402 . Curve  404  illustrates the resulting corrected curve (curve  402  corrected by curve  406 ). Typically, the residue amplifier compresses the residue signal. 
         [0035]    In some examples, the amplifier dominant term of non-linearity is primarily of third order. A third order correction, although not exactly generating the correction, can be accurate enough to remove most of the non-linearity and can be easily implemented with multipliers and other digital components that are easily provided in CMOS technologies. For example, if the amplifier input is x, assuming a third-order non-linearity the amplifier output y is given by 
         [0000]        y=x−δ   3   x   3 . 
         [0000]    The residue, after linearity correction, is then given by 
         [0000]    
       
         
           
             
               
                 
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                             3 
                           
                         
                       
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                                 3 
                               
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                       3 
                     
                   
                 
               
             
             
               
                 
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                     + 
                     
                       
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         [0000]    Setting the correction δ 3 ≈δ c , with both parameters being much smaller than 1, then in most cases z≈x. In other words, the linearity correction has provided a linear response to the input value x. 
         [0036]      FIG. 5  illustrates a linearity extraction method according to some embodiments of the present invention. The residue amplifier transfer function curve  402  is shown along with the linear (gain 1) curve  404 . As shown in  FIG. 5 , multiple zones are defined. In  FIG. 5 , Zone  1  includes the outer zones of the transfer function, which are the zones where the non-linearity of transfer function curve  402  become the most prominent. Zone  2  is the inner zone, where the non-linearity of transfer function curve  402  is mostly linear, with small non-linearity of curve  402 . As is further discussed below, extractions provided in Zone  2  can be used for gain correction while extractions provided in Zone  1  can be used for linearity correction. In some embodiments, multiple zones can be used, especially if the non-linearity correction involves higher-order corrections. 
         [0037]      FIG. 6  illustrates digital processing  600  that can be used with the stage  300  illustrated in  FIG. 3A  in place of digital processing  330  illustrated in  FIG. 3B . Digital process  600  provides for both a gain correction and a non-linearity correction utilizing a multi-zone processes according to some embodiments of the present invention. As shown in  FIG. 6 , digital processing  600  includes PRBS generator  314  to generate the pseudo-random binary sequence Dprbs. In the embodiment shown in  FIG. 6 , there are two feed-back loops represented by gain correction  602  and linearity correction  604 . 
         [0038]    As shown in  FIG. 6 , the digital input D BE  is added to an output from gain correction  602  in summer  620 . The output from summer  620  is added to the output from linearity correction  604  in summer  626  and D prbs  is subtracted in summer  628 . The resulting digital value is summed with the digitized value D flash  in summer  630  to form the output digital value D out . 
         [0039]    Gain extraction  606  receives the output from summer  628  and multiplies it by D prbs  in multiplier  612 . As discussed above with respect to gain extraction  318 , the value K 0 =G−1. The output of gain extraction  606 , K 0 , is input to switch  618 , which switches K 0  to integrator  616  or integrator  614  depending on the output of zone extraction  610 . Zone extraction  610  switches K 0  to integrator  614  if D BE  is in an inner zone (Zone  2 ) as shown in  FIG. 5  and switches K 0  to integrator  616  if D BE  is in an outer zone (Zone  1 ) as shown in  FIG. 5 . Although only two zones are illustrated in  FIG. 6 , where Zone  2  is primarily a linear zone and Zone  1  is a non-linear zone, there may be any number of zones included in the processing. 
         [0040]    Zone  2 , as shown in  FIG. 5 , is within the linear portion of the residue amplifier transfer function. Therefore, integrator  614 , which integrates the value K 0  if D BE  is within Zone  2 , generates a gain correction factor γ c0  that is used in gain correction  602 . As shown in  FIG. 6 , gain correction  602  multiplies the value D BE  by the gain correction factor γ c0  in multiplier  618 . The result of the multiplication in multiplier  618  is added to D BE  in summer  620 . 
         [0041]    Zone  1 , as shown in  FIG. 5 , is within the non-linear portion of the residue amplifier transfer function. Therefore, integrator  616 , which integrates the value of K 0  if D BE  is within Zone  1 , generates a linearity correction factor δ c  that is input to linearity correction  604 . Linearity correction  604  includes multiplier  622  and multiplier  624 . Multiplier  622  inputs D BE  corrected by the amount γ c0 D BE  from summer  620  and forms its cube, Db 3 . Multiplier  624  receives D b   3  from multiplier  622  and multiplies D b   3  by the linearity correction factor δ c . As shown in  FIG. 6 , the output from linearity correction  604 , δ c D b   3 , is added to the output from summer  620 , D b , in summer  626 . 
         [0042]    Therefore, for each sample within the inner zone (Zone  2 ), correlation is applied and the error signals are fed back to the gain correction integrator  614 . For each sample within the outer, non-linear, zone, a similar correlation is applied and the error gains are fed to integrator  616  and applied to the linearity correction  604 . In steady state, the residue transfer slope in the inner zone (Zone  2 ) and that in the outer zone (Zone  1 ) are thus both adjusted. 
         [0043]    As is further shown in  FIG. 6 , zone extraction  610  receives the value DBE and determines the position of switch  618 . A simple comparison of the value DBE with the definition of the zone boundaries will determine whether switch  618  is set consistent with the zones. For example, from  FIG. 5 , if the absolute value of DBE is greater than 2/8 switch  618  is set to integrator  616  (Zone  1 ) and if less than 2/8 switch  618  is set to integrator  614  (Zone  2 ). 
         [0044]    As discussed above, and illustrated in  FIG. 6 , the correction for the remaining residue z=y+δ c y 3  was utilized. However, any kind of nonlinear correction function can be used and implemented in digital correction according to embodiments of the present invention. Systems with more extraction zones and more parameters can be used and implemented digitally. 
         [0045]      FIG. 7  illustrates a residue amplifier transfer function that, as an example, has been segregated into six zones, labeled Zone − 3 , Zone − 2 , Zone − 1 , Zone  1 , Zone  2 , and Zone  3 . Zone − 1  and Zone  1  represent the roughly linear portion of the curve while the other zones are nonlinear portions. The slope of the transfer function, which corresponds to the gain G, in each of Zone − 3 , Zone − 2 , Zone − 1 , Zone  1 , Zone  2 , and Zone  3  is given p −3 , p −2 , p −1 , p 1 , p 2 , and p 3 , respectively. 
         [0046]    The correction function can account for a 5 th  order distortion and an offset, given by 
         [0000]        z=a   1 ( y−y   0 )+ a   3 ( y−y   0 ) 3   +a   5 ( y−y   0 ) 5 . 
         [0000]    This correction function has four parameters to be calibrated, y 0 , a 1 , a 3 , and a 5 . The parameters can be calculated from the extracted slopes as 
         [0000]        y   0 =( p   1   +p   2   +p   3 )−( p   −1   +p   −2   +p   −3 )
 
         [0000]    
       
      
       a 
       1 
       =p 
       −1 
       +p 
       1  
      
     
         [0000]    
       
      
       a 
       3 
       =p 
       −2 
       +p 
       2  
      
     
         [0000]    
       
      
       a 
       5 
       =p 
       −3 
       +p 
       3  
      
     
         [0000]    Similar to digital processing  600  illustrated in  FIG. 6 , a digital processing can be provided to implement this, or any other, correction function. 
         [0047]      FIGS. 8A and 8B  illustrate a simulation of a CMOS open loop residue amplifier, with and without a digital correction according to some embodiments of the present invention. The simulation shows a Fourier Transform up to the Nyquist frequency of the pipeline model ADC converter. The chart shows decibels compared to full scale (dBFS) as the y-axis and frequency on the x-axis. As shown in  FIG. 8A , without correction according to embodiments of the present invention, the spurious-free dynamic range SFDR is 83.5 dBc with a signal-to-noise ration SNDR of 77.1 dBc. However, with correction, as shown in  FIG. 8B , the SFDR is improved to 109.7 dBC and the SNDR is improved to 102.7 dBc. 
         [0048]    The above detailed description is provided to illustrate specific embodiments of the present invention and is not intended to be limiting. Numerous variations and modifications within the scope of the present invention are possible. The present invention is set forth in the following claims.