Abstract:
A semiconductor device and fabricating method thereof are disclosed, by which channel mobility is enhanced and by which effect of flicker noise can be minimized. Embodiments relate to a method of fabricating a semiconductor device which includes forming a first epi-layer over a substrate, forming a second epi-layer over the first epi-layer, forming a gate electrode over the second epi-layer, forming a spacer over both sides of the gate electrode, etching an area adjacent both sides of the spacer to a depth of the substrate, forming an LDD region in a region under the spacer, and forming a third epi-layer for a source/drain region over the etched area adjacent both of the sides of the spacer.

Description:
[0001]    The present application claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-2007-0087002 (filed on Aug. 29, 2007), which is hereby incorporated by reference in its entirety. 
       BACKGROUND 
       [0002]    Generally, as semiconductor devices become more highly integrated, performing fabrication processes gets more difficult. For instance, in a MOS transistor, as a gate/source/drain electrode is reduced in size, the length of a channel is reduced as well. As the channel length is reduced, a thickness of a gate insulating layer is reduced as well, reducing the mobility of electrons. 
         [0003]    Moreover, as the concentration of channel impurities rises, flicker noise increases to affect analog signal characteristics. Therefore, in manufacturing semiconductor devices for SoC (system on chip) technology, it is difficult to ensure reliability of operation. The flicker noise is a sort of intrinsic noise in an active device. As flicker noise is inversely proportional to frequency, it may be called ‘1/f noise’. The flicker noise rapidly increases on a low frequency band. The flicker noise is associated with electron mobility, channel impurity and the like. In an SoC for a stable radio frequency signal, the flicker noise may cause a serious problem. 
       SUMMARY 
       [0004]    Embodiments relate to a semiconductor technology, and more particularly, to a semiconductor device and fabricating method thereof. Embodiments relate to a semiconductor device and fabricating method thereof, by which channel mobility is enhanced and by which effect of flicker noise can be minimized. 
         [0005]    A semiconductor device according to embodiments includes a first epi-layer over a substrate, a second epi-layer over the first epi-layer, a gate electrode over the second epi-layer, a spacer over both sides of the gate electrode, and an LDD region formed under the spacer and to a depth of the first epi-layer. The first epi-layer may include an epitaxial layer doped with channel impurity and the second epi-layer may include an undoped epitaxial layer not containing channel impurity. The semiconductor may further include a third epi-layer next to both sides of the spacer and over an etched portion of the substrate including the first and second epi-layers to become a source/drain region. 
         [0006]    Embodiments relate to a method of fabricating a semiconductor device which includes forming a first epi-layer over a substrate, forming a second epi-layer over the first epi-layer, forming a gate electrode over the second epi-layer, forming a spacer over both sides of the gate electrode, etching an area adjacent both sides of the spacer to a depth of the substrate, forming an LDD region in a region under the spacer, and forming a third epi-layer for a source/drain region over the etched area adjacent both of the sides of the spacer. 
         [0007]    The spacer forming step may include forming an oxide layer over the second epitaxial layer adjacent both sides of the gate electrode, forming a first nitride layer over the gate electrode the nitride layer having a width greater than that of the gate electrode, and extending over the top of the oxide layer, and removing a portion of the oxide layer using the first nitride layer as a mask. The first nitride layer may be further used as a mask in etching the first nitride layer in part to the depth of the substrate after forming the spacer. 
         [0008]    After etching the area adjacent both of the sides of the spacer to the depth of the substrate, the method may further include applying a stress to the substrate exposed by the etching step in a vertical direction. Applying the stress to the substrate in the vertical direction may include forming a second nitride layer over the substrate including the gate electrode and the spacer. 
         [0009]    The stress may be applied to the exposed substrate in a vertical direction to enable the stress to be memorized in a channel region of the gate electrode. 
     
    
     
       DRAWINGS 
         [0010]    Example  FIG. 1  is a cross-sectional diagram of a semiconductor device according to embodiments after a second epitaxial layer has been formed. 
           [0011]    Example  FIG. 2  is a cross-sectional diagram of a semiconductor device according to embodiments after a gate electrode has been formed. 
           [0012]    Example  FIG. 3  is a cross-sectional diagram of a semiconductor device according to embodiments after an oxide layer has been formed. 
           [0013]    Example  FIG. 4  is a cross-sectional diagram of a semiconductor device according to embodiments after a nitride layer and a photoresist layer have been formed. 
           [0014]    Example  FIG. 5  is a cross-sectional diagram of a semiconductor device according to embodiments after an oxide layer and a portion of a substrate have been removed. 
           [0015]    Example  FIG. 6  is a cross-sectional diagram of a semiconductor device according to embodiments after a second nitride layer has been formed. 
           [0016]    Example  FIG. 7  is a cross-sectional diagram of a semiconductor device according to embodiments after a second nitride layer has been removed. 
           [0017]    Example  FIG. 8  is a cross-sectional diagram of a semiconductor device according to embodiments after an LDD region has been formed. 
           [0018]    Example  FIG. 9  is a cross-sectional diagram of a completed semiconductor device according to embodiments. 
       
    
    
     DESCRIPTION 
       [0019]    Example  FIG. 1  is a cross-sectional diagram of a semiconductor device according to embodiments after a second epitaxial layer  130  has been formed. Referring to example  FIG. 1 , a first epi-layer  120  heavily doped with channel impurity is grown over a semiconductor substrate  110 , e.g., a mono-crystalline silicon substrate. The first epi-layer  120  may contain channel impurity levels between about 2×10 13  ions/cm 2  to 2×10 16  ions/cm 2 . In NMOS transistors, for example, the channel impurity may include boron (B) or the like. In PMOS transistors, for example, the channel impurity may include As, P or the like. 
         [0020]    After the first epi-layer  120  has been grown and doped with the channel impurity, a second epi-layer  130  may be grown over the first epi-layer  120 . The second epi-layer  130  is not doped with impurity. Each of the epi-layers  120  and  130  may have the same thickness, which may be about 10 nm˜30 nm. After the first and second epi-layers, which correspond to a epitaxial layer doped with channel impurity and an epitaxial layer undoped with channel impurity, respectively, have been formed, a gate electrode  140  explained in the following description may be formed. 
         [0021]    Example  FIG. 2  is a cross-sectional diagram of a semiconductor device according to embodiments after a gate electrode has been formed. Referring to example  FIG. 2 , to form a gate electrode  140 , a gate oxide may be grown over the second epi-layer  130 . The gate oxide may then be coated with polysilicon. A gate electrode  140  may be formed using a photoresist and a dry etch process in turn. The gate oxide etched by the dry etch process becomes a gate insulating layer  141  and the etched polysilicon becomes an electrode  142 . In the following description, the term gate electrode  140  will refer to both gate insulating layer  141  and electrode  142 . The gate electrode  140  maybe approximately 130 nm˜170 nm tall. 
         [0022]    Example  FIG. 3  is a cross-sectional diagram of a semiconductor device according to embodiments after an oxide layer  152  has been formed. Referring to example  FIG. 3 , an oxide layer  152  may be formed over both sides of the gate electrode  140  by deposition and planarization. In particular, after the gate electrode  140  has been formed, oxide may be deposited over the second epi-layer  130  including the gate electrode  130 . The oxide may be deposited by CVD (Chemical Vapor Deposition). The oxide may be polished by planarization such as CMP (Chemical Mechanical Polishing) until a top surface of the gate electrode  140  is exposed. 
         [0023]    Example  FIG. 4  is a cross-sectional diagram of a semiconductor device according to embodiments after a nitride layer  154  and a photoresist layer  156  have been formed. Referring to example  FIG. 4 , after completion of the planarization performed over the oxide to form the oxide layer  152  over both sides of the gate electrode  140 , a first nitride  154  may be formed over the oxide layer  152  including the gate electrode  140 . A photoresist layer  156  may be formed to cover the gate electrode  140  and a portion of the first nitride  154  over both sides of the gate electrode  140 . The photoresist layer  156  may be formed to have a width greater than that of the gate electrode  140 . More particularly, the photoresist layer  156  may be formed to extend from both sides of the gate electrode  140  by about 45 nm˜55 nm. 
         [0024]    The photoresist layer  156  may be used as a mask to etch the first nitride  154 . A first nitride layer  154   a  may be formed by etching, using the photoresist layer  156 . The first nitride layer  154   a  (shown in  FIG. 5 ) may formed with a width greater than that of the gate electrode  140  to extend over the oxide layer  152 . The first nitride layer  154   a  may be used as an etch mask to form a dummy spacer. 
         [0025]    Example  FIG. 5  is a cross-sectional diagram of a semiconductor device according to embodiments after an oxide layer and a portion of a substrate have been removed. Referring to example  FIG. 5 , after the first nitride layer  154   a  has been formed by etching, using the photoresist layer  156  as a mask, the photoresist layer  156  may be removed. A portion of the oxide layer  152  may be removed by a first dry etching process using the first nitride layer  154   a  as a mask. The portion of the oxide layer remaining over both sides of the gate electrode  140  becomes a dummy spacer  152   a.    
         [0026]    After the portion of the oxide layer  152  has been removed, a second dry etch process using the first nitride layer  154   a  as a mask may be performed. In the second dry etch process, the substrate  110  may be etched to a depth of approximately 95 nm˜105 nm from a surface of the substrate  110 . Therefore, a portion of the substrate  110  including the first and second epi-layers  120  and  130  not covered with both sides of the spacer  152   a  may be removed. The nitride layer  154   a,  which was used as the etch masks in forming the dummy spacer  152   a  and removing the portion of the substrate  110  including the first and second epi-layers  120  and  130 , may be removed. 
         [0027]    Example  FIG. 6  is a cross-sectional diagram of a semiconductor device according to embodiments after a second nitride layer  160  has been formed, and example  FIG. 7  is a cross-sectional diagram of a semiconductor device according to embodiments after a second nitride layer  160  has been removed. After the first nitride layer  154   a  has been removed, a second nitride layer  160  may be formed over the partially-etched substrate  110   a  including the gate electrode  140  and the spacer  152   a  to apply a vertical stress to the substrate  110   a  exposed by the etch. The stress may be concentrated vertically with respect to a channel region under the gate electrode  140  by high-temperature annealing. The stress may be memorized in the channel region of the gate electrode  140 . The second nitride layer  160  may be formed of SIN based material. After completion of the channel memorizing process of stress, the second nitride layer  160  may be removed. By memorizing the stress in the channel region, the channel region of the gate electrode  140  is activated, and electron mobility is enhanced in the channel region. 
         [0028]    Example  FIG. 8  is a cross-sectional diagram of a semiconductor device according to embodiments after an LDD region  170  has been formed. After the second nitride layer  160  has been removed, an LDD region  170  may be formed by ion implantation. For instance, in forming a p-type LDD region, ion implantation may be performed using BF 2  ions with 5 KeV˜50 KeV energy and a dose of 1×10 14 ˜5×10 15  ions/cm 2 . In forming an n-type LDD region, ion implantation may be performed using As ions with 10 KeV˜70 KeV energy and a dose of 1×10 14 ˜5×10 15  ions/cm 2 . With the above LDD structure, the drain-gate voltage around the channel region and the source/drain junction is mitigated and the considerable potential fluctuation is reduced. Therefore, the LDD structure helps suppress the hot-carrier generation. 
         [0029]    By controlling the ion implantation energy, the first epi-layer  120  and the substrate  110  may be made to confine the LDD region  170 . In other words, the LDD region  170  can be defined according to the configuration of the first epi-layer  120   a  etched together with the substrate  110 . Therefore, the LDD region  170  may be formed under the spacer  152   a  and to the depth of the first epi-layer  120   a  etched by the second dry etch process. 
         [0030]    Example  FIG. 9  is a cross-sectional diagram of a semiconductor device according to embodiments after completion of fabrication. After the LDD region  170  has been formed, a third epi-layer  180  may be formed to cover the portion of the substrate etched by the second dry etch process. The third epi-layer  180  may be formed to have the same height of the bottom of the spacer  152   a.  In particular, the third epi-layer  180  may be formed over the etched substrate areas next to both sides of the spacer  152   a.  Each of the substrate areas functions as a source/drain region. More particularly, the third epi-layer  180  may be formed over the etched portion of the substrate  110  including the first and second epi-layers  120  and  130  neighbor to both sides of the spacer  152   a  by the second dry etch process. The third epi-layer  180  becomes the source and drain regions. 
         [0031]    Subsequently, a silicide layer may be formed over the third epi-layer  180  of the source/drain region and the gate electrode  140  by salicidation. A series of subsequent processes, for example, for contacts, metal wires and the like, may then be performed. Details for the subsequent processes will be omitted for lack of relevance to embodiments. 
         [0032]    Accordingly, embodiments provide the following effects and/or advantages. Embodiments intensively apply stress with a nitride layer to a channel region using channel memorization, thereby enhancing the mobility of electrons. Embodiments form a multi-layered epi-layer structure in a channel region, thereby reducing the dose of channel impurity and also thereby enhancing electron mobility. Therefore, embodiments maximize device reliability even if a semiconductor device is integrated at the level of tens of nanometers or below. Embodiments minimize influence caused by flicker noise, thereby enhancing the analog characteristics of a device. In applying the SoC technology to a semiconductor device, embodiments minimize the influence of interference signals between neighbor devices. 
         [0033]    It will be obvious and apparent to those skilled in the art that various modifications and variations can be made in the embodiments disclosed. Thus, it is intended that the disclosed embodiments cover the obvious and apparent modifications and variations, provided that they are within the scope of the appended claims and their equivalents.