Abstract:
According to one embodiment, a memory controller is disclosed. The memory controller includes assignment logic and a transaction assembler. The assignment logic receives a request to access a memory channel. The transaction assembler combines the request into one or more additional requests to access two or more independently addressable subchannels within the channel.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to computer systems; more particularly, the present invention relates to accessing memory control.  
       BACKGROUND  
       [0002]     Computer systems implementing Unified Memory Architecture (UMA) feature a graphics controller that accesses main memory for video memory. However, the memory efficiency of UMA graphics systems may be limited due to CPU cache line size requirements. For example, the ideal memory access size for graphics may be 4 to 16 bytes, since graphics controllers can operate on one or a few pixels or texels at a time. Nevertheless, memory architectures are often optimized for the 64 byte CPU cache line size to optimize CPU memory efficiency. The result is that, on average, a significant amount of data read from memory may never used by the graphics controller.  
         [0003]     Manufacturers of discrete graphics controllers minimize this over fetch by using narrower memory channels. This solution, however, is not available for UMA-based integrated graphics controllers.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0004]     The invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which:  
         [0005]      FIG. 1  is a block diagram of one embodiment of a computer system;  
         [0006]      FIG. 2  illustrates one embodiment of a memory controller;  
         [0007]      FIG. 3  illustrates one embodiment of a logical virtual address;  
         [0008]      FIG. 4  illustrates another embodiment of a memory controller;  
         [0009]      FIGS. 5A &amp; 5B  illustrate performance benefits;  
         [0010]      FIG. 6  illustrates one embodiment of identity subchannel assignment;  
         [0011]      FIG. 7  illustrates another embodiment of identity subchannel assignment;  
         [0012]      FIG. 8  illustrates yet another embodiment of identity subchannel assignment;  
         [0013]      FIG. 9  illustrates another embodiment of a memory controller;  
         [0014]      FIG. 10  illustrates one embodiment of non-identity subchannel assignment; and  
         [0015]      FIG. 11  illustrates another embodiment of a computer system.  
     
    
     DETAILED DESCRIPTION  
       [0016]     A mechanism for memory request combination is described. In the following detailed description of the present invention numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.  
         [0017]     Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.  
         [0018]      FIG. 1  is a block diagram of one embodiment of a computer system  100 . Computer system  100  includes a central processing unit (CPU)  102  coupled to an interface  105 . In one embodiment, CPU  102  is a processor in the Pentium® family of Pentium® IV processors available from Intel Corporation of Santa Clara, Calif. Alternatively, other CPUs may be used. For instance, CPU  102  may be implemented using multiple processing cores. In yet other embodiments, computer system  100  may include multiple CPUs  102   
         [0019]     In a further embodiment, a chipset  107  is also coupled to interface  105 . Chipset  107  includes a memory control component  110 . Memory control component  110  may include a memory controller  112  that is coupled to a main system memory  115 . Main system memory  115  stores data and sequences of instructions that are executed by CPU  102  or any other device included in system  100 . In one embodiment, main system memory  115  includes dynamic random access memory (DRAM); however, main system memory  115  may be implemented using other memory types. Additional devices may also be coupled to interface  105 , such as multiple CPUs and/or multiple system memories.  
         [0020]     Memory control component  110  may be coupled to an input/output (I/O) control component  140  via an interface. I/O control component  140  provides an interface to I/O devices within computer system  100 . I/O control component  140  may support standard I/O operations on I/O busses such as peripheral component interconnect (PCI) Express, accelerated graphics port (AGP), universal serial bus (USB), low pin count (LPC) bus, or any other kind of I/O bus (not shown).  
         [0021]     According to one embodiment, graphics controller  160  is in communication with chipset  107  and is implemented to provide video graphics to a display monitor (not shown) coupled to computer system  100 . Graphics controller  160  accesses main memory  115  for video memory. As discussed above, the memory efficiency of memory device supporting both a graphics system and a CPU is limited since memory access size for graphics is often ideally 4 to 16 bytes, while memory architectures are optimized for the 64 byte CPU line size to optimize CPU memory efficiency.  
         [0000]     Micro-Tiling  
         [0022]     According to one embodiment, memory control component  110  features Micro-Tiling in order to reduce memory request size for graphics devices, while maintaining 64 byte memory transactions. A standard memory channel such as based on DDR DRAM technology, has some physical width of m bits. A memory transaction includes T transfers for a total logical width of M=m*T/8 bytes. The bytes within each transaction are considered to have consecutive addresses. In subsequent discussion, the term width means the logical width.  
         [0023]     Micro-Tiling breaks the M byte wide channel into S subchannels that are each N=M/S bytes wide and where N bytes of data are transferred on each subchannel. An address may be presented to each subchannel, in which some number, I, of independent address bits may be different from corresponding bits in the addresses presented to the other subchannels. The data transferred on each subchannel may be considered to represent a contiguous address range. However, the blocks of data on each subchannel are not necessarily from a contiguous address range. Each subchannel includes a subset of the total memory locations of the channel.  
         [0024]      FIG. 2  illustrates one embodiment of an memory control component  110  supporting Micro-Tiling. In one embodiment, a multi-channel memory subsystem has a Micro-Tiling memory controller per channel. Thus, as illustrated in  FIG. 2 , memory control component  110  includes two memory controllers  112  (memory controllers  1  and  2 ), one for each of the two channels. Each channel includes S subchannels, each N bytes wide. Thus each channel may be M=N*S bytes wide.  
         [0025]     In this figure, requests to read or write memory are depicted as 2×2 arrays of squares possibly representing a 2×2 array of pixels or texels. Requests are shown before being assigned to a subchannel. After subchannel assignment, requests are numbered  0 -S- 1  to suggest subchannel assignment. The N byte returns to requester  205  coupled to memory control component  110  occur in the case of a read transaction.  
         [0026]     Memory control component  110  includes channel assignment logic  210  coupled to memory controllers  112 . Channel assignment  210  assigns each request received from requester  205  to a memory channel  240  via a memory controller  112 . Further, each memory controller  112  includes subchannel assignment  215 , reorder buffer  220  and transaction assembler  230 . Thus, requests are assigned to memory controller  1  or memory controller  2  shown in  FIG. 2 .  
         [0027]     Subchannel assignment  215  assigns each request to a subchannel within a memory channel  240 . Reorder buffer  220  collects requests to enable transaction assembler  230  to attempt to assemble memory accesses for each memory  240  subchannel. According to one embodiment, each subchannel has an equal N byte width.  
         [0028]     During operation of the system shown in  FIG. 2 , a request to read or write a block of N bytes of data at address A enters a memory controller ( 1  or  2 ) may be assigned to a subchannel and may be placed in a reorder buffer  220 . In one embodiment, the Identity Subchannel Assignment, s, may be defined by the following process: the request address, A, is shifted right by P=log 2 (N) bits, resulting in a new integer value Ã (e.g., Ã=A&gt;&gt;P); and s is the least significant Q=log 2 (S) bits of Ã (e.g., s=Ã &amp; ((1&lt;&lt;Q)−1)).  
         [0029]     The memory controller forms a memory read transaction by selecting S read requests, one for each subchannel, from the reorder buffer  220 . The memory controller forms a memory write transaction by selecting S write requests, one for each subchannel, from reorder buffer  220 . The portion of the address represented by shared address lines may be the same for all subchannel requests in the transaction.  
         [0030]      FIG. 3  illustrates one embodiment of an interpretation of address bits in a physical address. The choice of shared and independent address bits, and subchannel select bits shown in  FIG. 3  is for illustrative purposes since the division of the address bits above the P subchannel data address bits into shared and independent address bits, and subchannel select bits may be arbitrary. The independent address bits are different across subchannels, and are not necessarily contiguous. The address bits sent to a subchannel are the shared address bits and the independent address bits of that subchannel.  
         [0031]      FIG. 4  illustrates an embodiment of memory control component  110  assembling a 64 byte transaction from four 16 byte requests with only a single channel being shown.  FIG. 4  shows reorder buffer  220  implemented as a reorder queue for each subchannel. However, in other embodiments, reorder buffer  220  may be implemented via other mechanisms.  
         [0032]     In this embodiment, transaction assembler  230  constructs a 64 B memory request from 16 B requests, one for each subchannel. All 16 byte requests forming the memory request have the same shared address bits. Thus assembler  230  looks into the queue for requests that can be assembled into a single transaction based upon whether requests have a common shared address.  
         [0033]     Note that in the embodiment shown in  FIG. 4 , assembler  230  cannot find a request for subchannel  1   c . When attempting to form a transaction, the memory controller may not be able to find a request for each subchannel such that all have the same shared address segment (e.g., such that the value of each shared address bit may be the same across all requests).  
         [0034]     If a subchannel cannot be filled by a request in the corresponding queue, the effect is that no transfer may be performed from/to that subchannel. In one embodiment, if a subchannel cannot be filled by a request, an arbitrary location may be read and the results are discarded. In an alternative embodiment, an additional control line may be included per subchannel, which may be used to power down a subchannel when there is no corresponding request to that channel.  
         [0035]     The Micro-Tiling memory subchannels can access discontiguous memory addresses within some address ranges determined by the shared address bits and the I independent address bits. A judicious choice of I can provide the increased concurrency and bandwidth efficiency of independent subchannels, balanced against the cost of duplicating I address signals to each subchannel.  
         [0036]      FIGS. 5A &amp; 5B  illustrate performance benefits for Micro-Tiling. Each figure shows the rasterization of a triangle in a tiled address space, with each small square representing a 4 byte pixel or texel.  FIG. 5A  shows overfetch in a standard memory system when requests are 64 bytes each. Each 4×4 block of pixels represents a 64 byte aligned block of memory. The triangle encompasses 57 pixels. With a standard memory subsystem, those 57 pixels are in 11 (64 byte) blocks of memory. Thus, in order to access those 57 pixels, an additional 119 pixels worth of data may be accessed that may not be used (e.g., resulting in 32% efficiency).  
         [0037]      FIG. 5B  shows the over fetch if requests are 16 bytes each and if all such requests can be utilized by the Micro-Tile Assembler to build 64 byte memory transactions with no unused subchannels. In this case, the triangle touches 23 2×2 pixel arrays, resulting in 35 additional pixels worth of data being accessed (e.g., resulting in 62% efficiency). The effectiveness of Micro-Tiling depends on the ability of the Assembler to construct fully populated memory transactions.  
         [0000]     Micro-Tiling Request Mapping  
         [0038]     As discussed above, the Identity Subchannel Assignment, s, may be defined by: the request address, A, is shifted right by P=log 2 (N) bits, resulting in a new integer value Ã (e.g., Ã=A&gt;&gt;P); and s is the least significant Q=log 2 (S) bits of Ã (e.g., s=Ã &amp; ((1&lt;&lt;Q)−1)).  FIG. 6  illustrates one embodiment of identity subchannel assignment for the case of a linear address space. In this embodiment, a channel may be composed of four subchannels (S=4).  
         [0039]      FIG. 6  shows the subchannel assignment of a portion of linear address space, relative to some address A, in which each small block represents N bytes. A block  0  represents an address range that will be assigned to subchannel  0 , block  1  represents an address range that will be m assigned to subchannel  1 , block  2  represents an address range that will be assigned to subchannel  2 , and block  3  represents an address range that will be assigned to subchannel  3 .  
         [0040]      FIG. 7  illustrates another embodiment of identity subchannel assignment for the case of an example 2D tiled address space, again relative to some address A. Note that there are many possible 2D address space tilings, and that higher dimensionality tilings are also possible.  
         [0041]     An implementation of identity subchannel assignment may not perform well if request addresses are not uniformly distributed over the subchannels. For example,  FIG. 8  illustrates one embodiment of identity sub-channel assignment on an exemplary tiled address space such as might be used in graphics applications.  
         [0042]      FIG. 8  includes the outline of a triangle to suggest the N byte blocks that are accessed during the rendering of a triangle. Note that requests to access blocks along the left and bottom edges of the triangle are not distributed uniformly among the subchannels. As a result, the transaction assembler  230  might not be able to assemble complete transactions, including requests to all subchannels.  
         [0043]     According to one embodiment, non-identity subchannel assignment may be provided to the Micro-Tiling architecture in order to maximize the likelihood that request addresses are uniformly distributed over the subchannels, and, consequently, improve Micro-Tiling BW reduction.  
         [0044]      FIG. 9  illustrates another embodiment of a memory controller implementing Micro-Tiling. This embodiment provides mapping logic  950  coupled to subchannel assignment  215  in each memory controller. Similar to above,  FIG. 9  shows reorder buffers  220  implemented as a reorder queue for each subchannel. This configuration has two channels, and thus two memory controllers. Each channel includes four subchannels, each 16 bytes wide. Thus each channel may be 64 bytes wide.  
         [0045]     In one embodiment, mapping logic  950  transmits an input signal to subchannel assignment  215  indicating how requests are assigned to the subchannels in order to reduce pattern repetition. As a result, the mapping may be changed so that objects are drawn evenly across the subchannels to avoid hot-spotting. In another embodiment, mapping logic  950  provides different mappings to different regions of its address space. The mapping applied to some region of the address space can change over time whenever the data within the region may be no longer of interest.  
         [0046]      FIG. 10  illustrates one embodiment of non-identity sub-channel mapping in which the blocks have the same meaning as described above with respect to  FIG. 8 . In this case requests to access blocks along the left and bottom edges of the triangle are distributed more uniformly among the subchannels. The effect of this subchannel assignment can be to reduce bandwidth by more efficiently populating Micro-Tiling requests to the memory channel(s). Similarly, in the case of a linear address space, a suitably chosen non-identity subchannel assignment mapping can yield reduced BW particularly where memory accesses typically have a stride that may be a multiple of M bytes.  
         [0047]      FIG. 11  illustrates another embodiment of computer system  100 . In this embodiment, chipset  107  includes a single control hub  1120  as opposed to a separate memory control component and I/O control component. Consequently, memory controller  112  may be included within CPU  102 , with memory  115  being coupled to CPU  102 . In such an embodiment, graphics controller  160  may be coupled to control hub  1120  and accesses main memory  115  via CPU  102   
         [0048]     Whereas many alterations and modifications of the present invention will no doubt become apparent to a person of ordinary skill in the art after having read the foregoing description, it is to be understood that any particular embodiment shown and described by way of illustration is in no way intended to be considered limiting. Therefore, references to details of various embodiments are not intended to limit the scope of the claims, which in themselves recite only those features regarded as essential to the invention.