Abstract:
A method is disclosed for producing an integrated circuit arrangement with an auxiliary indentation, particularly with aligning marks, and an integrated circuit arrangement. The invention also relates to a method for producing aligning marks. During the method, a planarization is carried out before material is removed from an auxiliary indentation.

Description:
PRIORITY CLAIM 
   This application is a continuation-in-part of International Patent Application No. PCT/EP2005/051362, filed Mar. 23, 2005, and claims the benefit of priority of German Patent Application No. DE 10 2004014676.4, filed Mar. 25, 2004, which the contents of both are hereby incorporated by reference in their entirety herein. 

   BACKGROUND 
   1. Technical Field 
   The invention relates to a method for producing an integrated circuit arrangement. In particular, the invention relates to a method for producing an integrated circuit arrangement with at least one auxiliary indentation. 
   2. Background Information 
   An alignment mark may serve for the alignment of a mask with respect to the integrated circuit arrangement. This is called an alignment. The form of the alignment marks depends on the manufacturer of the irradiation apparatus used for irradiation, for example the manufacturer of an exposure apparatus. Alignment marks contain, for example, a plurality of strips of identical or different lengths that are arranged parallel to one another. To simultaneously perform an alignment in an x direction and in a y direction at right angles with respect thereto, an alignment mark contains angled strips, by way of example. As an alternative, marks are produced separately for each alignment direction. 
   The alignment mark may also serve to monitor the position of a developed resist on the integrated circuit arrangement. This is called an overlay mark. By way of example, the overlay mark has the form of a rectangle or frame. When inspecting the position of the exposed resist, for example a photoresist, use is made of a so-called box-in-box method, for example, which involves determining either the offset of a rectangular overlay mark with respect to a frame structure in a layer situated deeper or the offset of a frame-type overlay mark with respect to a rectangular structure in a deeper layer. If the offset exceeds a predetermined tolerance value in one direction, then the already developed resist is not used for an etching operation. The developed resist is removed and, after the application of a resist, the exposure and development are repeated. 
   In connection with a planarization during the production of the integrated circuit arrangement, a planar area arises, so that topology-containing alignment marks are absent. If, moreover, an optically impermeable or only inadequately permeable layer is applied to the planar area after planarization, then alignment marks already fabricated in an earlier method step can no longer be used either. 
   BRIEF SUMMARY 
   It is an object of the disclosure to specify a simple method for producing an integrated circuit arrangement, the method being intended to enable, in particular, small alignment tolerances between elements of different layers of the integrated circuit arrangement. 
   The disclosure is based on the consideration that the alignment errors are particularly small when, despite the planarization and subsequent deposition of an optically impermeable layer, it is possible to use alignment marks whose position had already been defined prior to the planarization. This is because an alignment error is associated with each mask. If the alignment is effected directly with respect to the preliminary plane, then said alignment error is incorporated only once into the resulting overall error (Δf). If, in contrast, it is necessary to introduce an additional mask between two mutually adjacent planes, then this results in an error of 1.41×Δf. 
   Therefore, the following steps are performed in the method: producing at least one useful indentation and at least one auxiliary indentation in a substrate, applying a filling layer to the substrate provided with the useful indentation and with the auxiliary indentation, with filling material being introduced into the useful indentation and into the auxiliary indentation; planarization of the filling material, the filling material remaining in the useful indentation and the filling material remaining in the auxiliary indentation; and selective removal of at least a portion of the filling material in the auxiliary indentation after planarization, with no filling material being removed from the useful indentation. 
   The auxiliary indentation, despite the planarization, can be used as a starting point for a topology formation after the deposition of a layer, in particular an optically impermeable layer. In addition, the planarization is performed prior to the selective removal. This results in a surface with a small topology in the event of planarization. Moreover, abraded material or other contaminants are prevented from passing into the useful indentation during planarization. Such contaminants would be difficult to remove and, upon remaining in the auxiliary indentation would impair the function thereof as an alignment mark. A resist serving for selective removal e.g. a photoresist, likewise does not impede the planarization. 
   The auxiliary indentation or a topology arising on the auxiliary indentation may be used as an alignment mark during the patterning of a layer, which is applied after the selective removal. 
   The planarization may be carried out in chemical mechanical process, with a polishing pad and a polishing liquid being used. The chemical mechanical polishing (CMP) is employed particularly in the case of filling materials comprising copper or a copper alloy. As an alternative, a dielectric filling material, in particular an oxide, may be used as filling material, in particular in the case of indentations in a semiconductor substrate, for example in a silicon substrate. 
   A covering layer may be applied after the selective removal, a portion of the covering layer being deposited in the auxiliary indentation, but not in the useful indentation. If the covering layer contains metal or contains silicon, then it is impermeable to light or permeable to light only in a very narrow frequency range. 
   The covering layer may be patterned by a photolithographic method, the topology produced as a result of the auxiliary indentation in the covering layer being used as an alignment mark. This method step is suitable in particular when a copper metal layer or a copper via filling is followed by application of an aluminum layer, for example a topmost aluminum layer, on which better bonding can be effected in comparison with copper. 
   The selective removal may be carried out by application of a resist layer, irradiation of the resist layer and the development of the resist layer and also subsequent dry-chemical or wet-chemical etching. After the development of the resist layer, only the auxiliary indentation, but not the useful indentation, is uncovered. The alignment for the irradiation of the resist layer or for monitoring the position of the developed resist layer can be carried out by optical methods, because the resist layer is transmissive for a relatively large light range. 
   However, in one arrangement, the alignment tolerances are at least a factor of 3 higher in comparison with at least one other alignment during the production of the integrated circuit arrangement because only regions in which auxiliary indentations are situated and in which useful indentations are situated are intended to be differentiated. Useful indentations are covered over a large area. Auxiliary indentations remain open over a large area. 
   The filling material may be removed from the auxiliary indentation wet-chemically, preferably using dilute sulfuric acid peroxide (DSP) mixture or by a DSP chemical (dilute sulfuric acid peroxide mixture with hydrofluoric acid HF in the ppm range). The etching chemicals mentioned are suitable at room temperature or higher temperatures for the selective removal of copper or a copper alloy with respect to a liner made of tantalum nitride. 
   The filling material may be completely removed from the auxiliary indentation. The topology differences brought about by the auxiliary indentation are as large as possible. 
   The substrate may comprise a semiconductor substrate in which the useful indentation and the auxiliary indentation are arranged. The useful indentation and also the auxiliary indentation are isolation trenches, for example, which serve for electrically isolating components of the integrated circuit arrangement. As an alternative, the substrate contains a semiconductor substrate and a dielectric layer, the useful indentation and the auxiliary indentation being arranged in the dielectric layer. The dielectric layer is arranged between two metal layers for example. 
   An integrated circuit arrangement is also disclosed having a wiring indentation and an auxiliary indentation in a dielectric layer. The wiring indentation contains a metal through which current flows during operation of the circuit arrangement, for example copper or a copper alloy having at least 50 atomic percent copper or tungsten. The auxiliary indentation may likewise contain a metal but one through which an electric current does not flow during operation of the circuit arrangement. The auxiliary indentation only serves as an alignment mark during the production of the integrated circuit arrangement. In one configuration, the auxiliary indentation contains aluminum or an aluminum alloy having at least 50 atomic percent of aluminum. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Exemplary embodiments of the invention are explained below with reference to the accompanying drawings in which: 
       FIG. 1  is an example first production stage in the production of an integrated circuit arrangement. 
       FIG. 2  is an example second production stage in the production of an integrated circuit arrangement. 
       FIG. 3  is an example third production stage in the production of an integrated circuit arrangement. 
       FIG. 4  is an example fourth production stage in the production of an integrated circuit arrangement. 
       FIG. 5  is an example fifth production stage in the production of an integrated circuit arrangement. 
   

   DETAILED DESCRIPTION 
     FIG. 1  is an example first production stage in a production of an integrated circuit arrangement. An integrated circuit arrangement contains a semiconductor substrate (not illustrated in  FIG. 1 ), for example a monocrystalline silicon substrate, in which a multiplicity of electronic components are formed, such as transistors. A metal layer  12  contains interconnects made of metal, for example an interconnect  14 . The interconnects  14  of the metal layer  12  are arranged in one plane. 
   By way of example, the interconnect  14  comprises copper or a copper alloy having more than 90 atomic percent of copper. As an alternative, the interconnects  14  of the metal layer  12  comprise aluminum or an aluminum alloy having more than 90 percent of aluminum. 
   After the patterning of the metal layer  12 , for example in a dry-chemical etching process or with the aid of a polishing operation, an insulating layer  16  was applied, which is also referred to as an interlayer dielectric (ILD). The insulating layer  16  contains silicon dioxide, for example, and has a thickness of 500 nm, for example, in particular greater than 300 nm. 
   After the production of the insulating layer  16 , a resist layer  18  was applied to the insulating layer  16 ,  30  irradiated and developed, cutouts  20 ,  22 ,  24  and  26  having been produced. Alignment marks situated beneath the insulating layer  16  or in the metal layer  12  were used for aligning a photo mask used during the irradiation of the resist layer  18  and for monitoring the position  35  of the developed resist. The alignment and the monitoring are noncritical because the insulating layer  16  is optically transmissive. In a subsequent etching process, for example in a dry chemical etching process, the cutouts  20 ,  22 ,  24  and  26  were deepened into the insulating layer  16 . The cutouts  20  and  22  in the insulating layer  16  serve, for example, to take up so-called vias and have a diameter of 200 nm, for example, in particular less than 500 nm. In contrast, cutouts  24  and  26  produced in the insulating layer  16  or the height differences brought about by the cutouts  24  and  26  serve as alignment marks. By way of example, the cutout  24  has a rectangular cross section having a length of greater than 10 μm and a width of greater than 3 μm. In the exemplary embodiment, the cutout  24  has a length of 20 μm and a width of 5 μm. 
   The cutout  26  has the same dimensions as the cutout  24 . The cutouts  20  and  22  end on the interconnect  14 . The metal layer  12  may be used as a stop layer for the cutouts  24  and  26  as well. It is thereby possible to set a defined depth of the auxiliary indentations. The bottom of the cutouts  24  and  26  is situated approximately at the level of the interconnect  14  in the insulating layer  16 . The depth of the cutouts  24  and  26  is 600 nm, for example, but is also deeper in the absence of metallization layer  12 . 
   As is further illustrated in  FIG. 2 , the residues of the resist layer  18  are removed after the dry etching of the insulating layer  16 . A liner layer  50  is subsequently applied by sputtering, said liner layer comprising tantalum nitride and having a thickness of 70 nm, by way of example. The liner layer  50  is deposited outside the cutouts  20 ,  22 ,  24  and  26 , on the side walls of the cutouts  20  to  26  and on the bottoms of the cutouts  20 ,  22 ,  24  and  26 . Copper is subsequently deposited, for example, with the aid of a galvanic method. In this case, copper is deposited both outside the cutouts  20 ,  22 ,  24  and  26  and within the cutouts  20 ,  22 ,  24  and  26 . In the exemplary embodiment, the cutouts  20 ,  22 ,  24  and  26  have been completely filled after the deposition of the copper. With the aid of a subsequent chemical mechanical polishing, the copper is removed from the liner layer  50  outside the cutouts  20 ,  22 ,  24  and  26 . By way of example, the liner layer  50  serves as a stop layer during the chemical mechanical polishing. The stop layer is likewise removed by a chemical mechanical polishing in a further step. 
   After the polishing, there are via fillings  52 ,  54  in the cutouts  20  and  22 . Fillings  56 ,  58  made of copper are situated in the cutouts  24  and  26 . The fillings  52  to  58  completely fill the cutouts  20 ,  22 ,  24  and  26 . 
   Although a single damascene method is explained with reference to  FIGS. 1 to 5 , the method steps explained can also be carried out in a dual damascene method. Copper interconnects and copper vias are produced simultaneously in a dual damascene method. 
   As illustrated in  FIG. 3 , after the polishing a resist layer  100  is applied, exposed and developed, cutouts  102  and  104  being produced in the resist layer  100 , the bottom of said cutouts adjoining the opening of the cutout  24  and the opening of the cutout  26 , respectively. After the development of the resist layer  100 , the via fillings  52  and  54  are covered by the resist layer  100 , while the fillings  56  and  58  are uncovered at the bottom of the cutout  102  and  104 , respectively. 
   The alignment of the mask for the irradiation of the resist layer  100  is once again unproblematic because the resist layer  100  exhibits good optical transmission. By way of example, the fillings  56  and  58  can be used for alignment. A tolerance range T 1  for the left-hand side area  106  of a resist region  108  lying between the cutouts  24  and  26  is more than 400 nm, for example, and is thus considerably greater than the tolerances that are otherwise customary for the alignment and for monitoring of the overlay measurements of 50 nm to 200 nm. 
   In an alternative configuration, no alignment is carried out during the exposure of the resist layer  100 . This is possible if tolerances of 1 μm, for example, are permissible because the cutouts  24  and  26  are at such a distance away from other structures of the integrated circuit arrangement. 
   After the development of the resist layer  100 , the fillings  56  and  58  are removed from the cutouts  24  and  26 , so that only the liner layer  50  remains in the cutouts  24  and  26 . As an alternative, however, the liner layer  50  is also concomitantly removed. In the exemplary embodiment, the fillings  56  and  58  are removed by one of the etching chemicals mentioned above. The residues of the resist layer  100  that remained on the insulating layer  16  are subsequently removed. 
   As is further illustrated in  FIG. 4 , after the removal of the residues of the resist layer  100 , a metal layer  150  is applied, e.g. by sputtering on an aluminum layer having a thickness of 3 μm or greater than 500 nm. The thickness of the metal layer  150  is coordinated with the width of the cutouts  24  and  26  in order to be able to make a sufficiently good topology available in the subsequent plane  150 . 
   After the metal layer  150  has been applied by sputtering, a resist layer  160  is applied to the metal layer  150 , irradiated and developed, cutouts  162 ,  164 ,  166  and  168  arising. The indentations  152  and  154  are used in the alignment of the mask used for the exposure of the resist layer  160 . The alignment is tested after the development of the resist layer  160  with the aid of resist structures  170  and  172  situated between the cutouts  24  and  26 , the resist structure  170  lying closer to the indentation  152  and the resist structure  172  lying closer to the indentation  154 . An optical method is used to determine a distance a in the x direction between the center of the indentation  152  and the center of the resist structure  170 . A distance b between the center of the indentation  154  and the center of the resist structure  172  is likewise determined. If the distances a and b that have been 15 determined are identical, then an ideal value for the overlay measurement is present. The same analogously holds true for the alignment in the y direction. 
   Deviations in the range of + and −50 nm are permitted per orientation, for example. If these tolerances are exceeded, then a new resist layer  160  must be applied. The developed resist layer  160  additionally contains a resist structure  174  situated above the cutouts  20  and  22 . 
   After successful overlay measurement, the metal layer  150  is patterned e.g. wet-chemically or dry-chemically using the developed resist layer, as in  FIG. 5 . A multiplicity of interconnects, for example an interconnect  200  adjoining the via fillings  52  and  54 , arise in the metal layer in the process. Metal structures  202 ,  204 ,  206 , and  208 , which do not influence the function of the developed circuit arrangement  10  arise beneath the resist structures  170 ,  172  and in the cutouts  24  and  26 , respectively. 
   The production of the integrated circuit arrangement  10  is then continued, for example with the production of further insulating layers and metal layers or with the application of passivation layers if the metal layer  150  is the topmost or furthest away metal layer of the integrated circuit arrangement. 
   As has been explained with reference to  FIGS. 1 to 5 , an alignment error of a mask for the exposure of the resist layer  100  does not affect the total offset error of aluminum plane  150  with respect to copper plane because only already existing alignment marks  24 ,  26  that have already been produced in the contact hole plane or in the via plane are uncovered by this auxiliary mask. The uncovered topology generates indentations  152 ,  154  that are imaged on or over the metal layer  150 . 
   The overall error is significantly reduced by the direct alignment of a mask for the patterning of an aluminum layer relative to marks  24 ,  26  that have been produced in the preceding contact hole plane. A method for direct alignment in the transition from copper to aluminum is thus specified. Apart from being applied to copper technologies relating to the transition to an aluminum plane, however, the method can also be applied to other metallization materials or to other conductive materials. 
   It is therefore intended that the foregoing detailed description be regarded as illustrative rather than limiting, and that it be understood that it is the following claims, including all equivalents, that are intended to define the spirit and scope of this invention.