Abstract:
A method and apparatus for efficient encoding of linear block codes uses a lookup table including a set of impulse responses to support faster performance by encoding in parallel. Advantages include a scalability that is lacking in existing schemes.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to transfer (i.e. transmission and/or storage) of digital signals. More specifically, the present invention relates to encoding of linear block codes. 
     2. Description of the Related Art 
     Digital signals are commonly used in applications such as voice, data, and video communications and image, data and document storage, processing, and archiving. Unfortunately, because storage media and transmission channels are not perfect, they tend to introduce errors into the digital information passing through them. In a storage medium, for example, errors may arise because of defects which prevent some or all of the digital signal from being properly stored, retained, or retrieved. In a transmission channel, errors may arise because of interference from another signal or variations in channel quality due to a fading process, for example. 
     To increase data robustness, an error detection scheme may be employed wherein a check value is calculated from the digital signal and transferred along with it. (In one common practice, the digital signal is divided into blocks, and a check value is calculated from and appended to each block before transfer. In other schemes, the digital signal and the check value may be interleaved and/or may have some other relative arrangement in time.) When the signal is retrieved or received, the check value calculation is repeated. If the check values calculated before and after the transfer agree, then the transferred signal may be assumed error-free. If the check values do not agree, then the signal may be assumed to contain at least one error. When a linear block code is used in such a calculation, the resulting check value is called a checksum, and when a cyclic code is used in such a calculation, the resulting check value is called a cyclic redundancy checksum or CRC. Depending on the type of code used and the number and/or type of errors encountered, it may be possible to correct such errors without retransmission of the digital signal. 
     For an (n, k) cyclic code C, k information symbols are encoded into an n-symbol code word. For example, a (48, 32) cyclic code produces a 48-bit code word comprising the 32 original information symbols and a 16-bit CRC. A cyclic code of this type may be uniquely defined by a generator polynomial G(X) of degree n−k having the form          G        (   X   )       =     1   +     (       ∑     i   =   1       n   -   k   -   1                         g   i          X   i         )     +       X     n   -   k       .                              
     A checksum calculated according to such a code has a length of n−k bits. An exemplary format for an (n, k) code is shown in FIG.  1 . 
     Addition over the Galois field GF( 2 ) reduces to a logical exclusive-OR (XOR) operation, while multiplication over this finite field reduces to a logical AND operation. For a cyclic code generated by a generator polynomial as described above and applied over GF( 2 ), therefore, an encoder may be implemented using the logical circuit shown in FIG.  2 . In this figure, the g i  represent the coefficients of the generator polynomial G(X), each of the (n−k) storage elements holds one bit value, and the contents of the storage elements are updated in unison (i.e. values are shifted into the storage elements at every clock cycle). During the first k shifts, the switch pulls are in the upper positions to allow the information signal to be loaded into the encoder (and passed through to the output if desired). For the next (n−k) shifts, the switch pulls are moved to the lower positions to allow the state of the encoder (i.e. the string of bits corresponding to the ordered contents of the storage elements) to be clocked out as the checksum signal. 
     If the generator polynomial is known during the design of the encoder, the circuit of FIG. 2 may be simplified by omitting the i-th AND gate (for g i =0) or replacing it with a connection (for g i =1). For example, the code polynomial 
     
       
           G ( X )= X   16   +X   15   +X   14   +X   11   +X   6   +X   5   +X   2   +X+ 1 
       
     
     (as specified in, e.g., sections 2.1.3.4.2.1 and 2.1.3.5.2.1 of part  2  of the IS-2000 standard published by the Telecommunications Industry Association, Arlington, Va.) may be implemented with the logical circuit shown in FIG.  3 . 
     Although they have very low hardware requirements, using very little storage and only a few logic gates, serial encoder implementations as shown in FIGS. 2 and 3 process only one bit of the input signal per clock period. Such performance may be unacceptably slow, especially for applications that involve real-time data streams (for example, communications applications). 
     Encoders that operate on more than one bit per cycle have been implemented by using precalculated lookup tables. In these implementations, a remainder for the current cycle is used as an index for choosing a value from a lookup table, and the chosen value is used to calculate a remainder for the next cycle. Although such an encoder processes multiple bits per cycle, it requires a lookup table whose size is related exponentially to the length of the remainder. Therefore, such implementations scale poorly and may not be suitable for applications that require both high speed and low storage consumption. 
     SUMMARY 
     In an apparatus according to an embodiment of the invention, a logic matrix receives an information signal and impulse responses that correspond to portions of the information signal. The logic matrix outputs a checksum that is based on a summation of at least two of the impulse responses. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a diagram showing a format of a code word. 
     FIG. 2 is a logical diagram for a generic encoder for a cyclic code. 
     FIG. 3 is a logical diagram for an encoder for a particular cyclic code. 
     FIG. 4 is a block diagram for an apparatus according to an embodiment of the invention. 
     FIG. 5 is a circuit diagram for logic matrix  120 . 
     FIG. 6 shows an XOR gate constructed from a tree of XOR gates having smaller capacities. 
     FIG. 7 shows a flow chart for a method for generating lookup table  110 . 
     FIG. 8 depicts one iteration of subtasks P 120  and P 130  of the method of FIG.  7 . 
     FIG. 9 is a block diagram for an apparatus according to another embodiment of the invention. 
     FIG. 10 is a graphical depiction of a data signal comprising instances of information signals. 
     FIG. 11 shows a flow chart for a method for generating lookup table  210  that continues the flow chart shown in FIG.  7 . 
     FIG. 12 depicts one iteration of subtasks P 180 , P 190 , and P 200  of the method of FIG.  11 . 
     FIG. 13 is a circuit diagram for logic matrix  220 . 
     FIG. 14A is a graphical depiction of a signal stream comprising instances of data signals. 
     FIG. 14B is a graphical depiction of an encoded signal stream. 
     FIG. 15 is a block diagram for an apparatus according to a further embodiment of the invention. 
     FIG. 16 is a block diagram for a flow control block. 
     FIG. 17 is a block diagram for an apparatus according to a further embodiment of the invention. 
    
    
     DETAILED DESCRIPTION 
     As shown in FIG. 4, an apparatus  100  according to an embodiment of the invention receives an information signal  20  of width k bits which is inputted to logic matrix  120 . Lookup table  110  provides predetermined encoder response information to another set of inputs of logic matrix  120 . Logic matrix  120  performs a predetermined logical function on its inputs to produce a checksum signal  30 . 
     Lookup table  110  stores information relating to impulse responses of an encoder for a cyclic code generated by a particular generator polynomial G(X) (e.g. an encoder according to a specific implementation of the circuit of FIG. 2) and having a predetermined initial state. Specifically, lookup table  110  stores k impulse responses of such an encoder, where the j-th impulse response (j being an integer from 1 to k) is the state of the encoder that results from shifting in the j-th impulse input (i.e. the string of length k wherein only the j-th bit has a nonzero value). Exemplary methods of constructing lookup table  110  are discussed below. 
     Logic matrix  120  selects impulse responses from lookup table  110  that correspond to nonzero bits of information signal  20  and outputs the summation of these responses. FIG. 5 shows a block diagram for an exemplary implementation of logic matrix  120  that includes k AND gates  140  and one XOR gate  150 . Each AND gate  140 ( m ) (where m is an integer from 1 to k) has a one-bit-wide control input and a (n−k)-bit-wide data input. If the control input to gate  140 ( m ) has a value of one, then the data input is passed to the output; otherwise, the gate&#39;s output is zero. For each gate  140 ( m ) in matrix  120 , the control input is the m-th bit of the information signal  20  and the data input is the m-th impulse response as obtained from lookup table  110 . In an exemplary implementation, an AND gate  140 ( m ) comprises several or many logical gates having more limited input capacities (e.g. two-input NAND gates) that are arranged to perform the logical function described above. 
     XOR gate  150  receives the k outputs of AND gates  140 ( m ) and produces a (n−k)-bit-wide output. The p-th bit of the output of XOR gate  150  (where p is an integer from 1 to (n−k)) has (a) a value of one if an odd number of the p-th bits of the outputs of AND gates  140 ( m ) have values of one and (b) a value of zero if an even number of the p-th bits of the outputs of AND gates  140 ( m ) have values of one. In other words, the output of XOR gate  150  is a bitwise XOR of the inputs, the p-th bit of the output being the XOR of the p-th bits of the inputs. 
     XOR gate  150  may be implemented as a tree of XOR gates having smaller input capacities. For example, FIG. 6 shows how a four-input XOR gate may be constructed from a tree of three two-input XOR gates (each of which may be implemented from other logical gates). In an exemplary implementation, XOR gate  150  comprises several or many logical gates having more limited input capacities (e.g. two-input NAND gates) that are arranged to perform the logical function described above. 
     Note that in implementing the logical functions described above, the actual construction of logic matrix  120  may take many forms other than the particular one shown in FIG.  5 . Because lookup table  110  is a constant for a fixed initial encoder state and fixed G(X), n, and k, for example, it may be knowable a priori that certain bits of the data inputs to AND gates  140 ( m ) will be zero and that corresponding bits of the outputs of these gates, therefore, will also be zero. Because the operation of logic matrix  120  may be described using a logical expression, applying such a priori knowledge to eliminate terms from this expression that are known to be zero may be performed to reduce the expression and simplify the corresponding implementation (e.g. in logical gates). Such reduction may be performed manually or automatically. In one embodiment of an apparatus according to the invention, the configuration of logic matrix  120  for a specified G(X), n, and k and a specified initial encoder state is reduced to a more optimal form (e.g. a form that requires fewer logical gates to perform a logical operation equivalent to that of the structure shown in FIG. 5) by using an electronic design tool such as the Design Compiler produced by Synopsis, Inc. (Mountain View, Calif.). 
     FIG. 7 shows a flowchart for an exemplary method of generating lookup table  110  by inputting a sequence of impulse inputs to an encoder for the cyclic code generated by the preselected polynomial G(X). In this method, the encoder may be implemented in hardware (e.g. according to a specific implementation of the circuit of FIG.  2 ). Note, however, that once the construction of lookup table  110  is completed, it is possible to practice the invention without further reference to such an encoder. Therefore, it may be desirable to implement at least a part of the encoder in software instead. Once the information to be stored in lookup table  110  is available, it is possible to practice the invention without reference to such an encoder either in hardware or in software (e.g. as seen in the apparatus of FIG.  4 ). 
     In subtask P 110 , a counter value i is set to 1. As the encoder&#39;s response depends upon its initial state, subtask P 110  also includes initializing the encoder by storing a predetermined string of values into its storage elements. Note that if an encoder according to FIG. 2 is initialized to a zero state (i.e. an initial value of zero is stored into each of its storage elements), the encoder will not change its state when a string of values of zero is inputted. Because such strings are common leading sequences in some applications, it may be desirable to initialize the encoder with a string of values of one (or with some other nonzero string) instead. 
     In subtask P 120 , the i-th impulse input (i.e. the string of length k wherein only the i-th bit has a nonzero value) is inputted to the encoder (or simulation thereof). In subtask P 130 , the encoder&#39;s response to this input (i.e. the string of (n−k) bits that represents the state of the encoder after the impulse input has been loaded) is stored to a corresponding location in lookup table  110 . Via the test of subtask P 140  and the loop maintenance and initialization operations in subtask P 150 , subtasks P 120  and P 130  are repeated until an impulse response has been stored for all k possible impulse inputs. 
     FIG. 8 is a graphical depiction of one iteration of subtasks P 120  and P 130 . In this example, the encoder&#39;s response to the i-th impulse input is stored in the i-th row of the lookup table, although any other predetermined correspondence between input identifier and table location may be used. Besides the method shown in FIGS. 7 and 8, many other methods for generating a lookup table  110  suitable for use in apparatus  100  are possible. 
     A method and apparatus as herein described exhibit excellent scalability. For example, note that the size of lookup table  110  increases only linearly as n increases with k constant (or as k increases with (n−k) constant). In such case, the depth of a tree of XOR gates used to implement XOR gate  150  would be expected to grow as log 2 (n). 
     FIG. 9 shows a block diagram for an apparatus  200  according to another embodiment of the invention. In this apparatus, response signal  60  as outputted by logic matrix  220  may be stored into an encoder state register  340  for use as an initial encoder state in a subsequent encoding and/or outputted as checksum signal  30  as described below. 
     In certain applications, it may be desired to use an (n, k) cyclic code to calculate a checksum of (n−k) bits from a data signal of more than k bits. In an exemplary application of apparatus  200 , a data signal to be encoded is divided into adjacent and nonoverlapping strings (i.e. blocks) of k bits, which are successively inputted to apparatus  200  (in synchronism with update signal  40 ) as instances of information signal  20 . FIG. 10 shows the example of a data signal  50  divided into four k-bit instances  20 - 1  through  20 - 4  of an information signal  20 . 
     Lookup table  210  stores information relating to impulse responses of an encoder for a cyclic code generated by a particular generator polynomial G(X) (e.g. according to a specific implementation of the circuit of FIG.  2 ). Specifically, lookup table  210  stores k impulse responses of an encoder having a zero initial state (i.e. each storage element holds a value of zero). The j-th impulse response (where j is an integer from 1 to k) is the state of the encoder that results from shifting in the j-th impulse input, this input being the string of length k wherein only the j-th bit has a nonzero value. 
     In order to account for changes in the initial state of the encoder (e.g. from one instance of information signal  20  to the next), lookup table  210  also stores (n−k) zero responses of the encoder. Specifically, the q-th zero response (where q is an integer from 1 to (n−k)) is the state that results when a string of k zero-value bits is shifted into an encoder having the q-th component initial state, the q-th component initial state being the string of length (n−k) wherein only the q-th bit has a nonzero value. 
     FIG. 11 shows a flowchart for an exemplary method of generating the zero-response portion of lookup table  210 . This method comprises inputting a zero input to an encoder for the cyclic code generated by the preselected polynomial G(X) that has one of a set of predetermined initial states (note that this method includes the method shown in the flowchart of FIG.  7  and continues from task P 140  in that flowchart). As above, the encoder may be implemented in hardware (e.g. according to a specific implementation of the circuit of FIG.  2 ), although once the construction of lookup table  210  is completed, it is possible to practice the invention without further reference to such an encoder. Therefore, it may be desirable to implement at least a part of the encoder in software instead. Once the information to be stored in lookup table  210  is available, it is possible to practice the invention without reference to such an encoder either in hardware or in software (e.g. as seen in the apparatus of FIG.  9 ). 
     In subtask P 160 , a counter value q is set to 1. In subtask P 170 , the counter value i is incremented (or, equivalently, set to the value (k+q)). In subtask P 180 , the encoder is initialized to the q-th component initial state by storing a string of (n−k) values into its storage elements, with the q-th value being one and all other values being zero. 
     In subtask P 190 , a zero input (i.e. a string of k zero bits) is inputted to the encoder (or simulation thereof). In subtask P 200 , the encoder&#39;s response to this input (i.e. the string of (n−k) bits that represents the state of the encoder after the zero input has been loaded) is stored to a corresponding location in lookup table  210 . Via the test of subtask P 210  and the loop maintenance operation in subtask P 220 , subtasks P 170 , P 180 , P 190 , and P 200  are repeated until a zero response has been stored for all (n−k) possible component initial states. 
     FIG. 12 is a graphical depiction of one iteration of subtasks P 180 , P 190 , and P 200 . In this example, the first k rows of lookup table  210  are the same as the k rows of lookup table  110  as described above, and the zero response of an encoder having the q-th component initial state is stored in the i-th row of lookup table  210 , although any other predetermined correspondence between input identifier and table location may be used. Besides the method shown in FIGS. 7,  8 ,  11 , and  12 , many other methods for generating sets of impulse responses and zero responses appropriate for use in lookup table  210  are possible. 
     FIG. 13 shows a block diagram for logic matrix  220 , which includes n AND gates  140  and one XOR gate  250 . As described above, each AND gate  140 ( r ) (where r is an integer from 1 to n) has a one-bit-wide control input and a (n−k)-bit wide data input. If the control input to gate  140 ( r ) has a value of one, then the data input is passed to the output; otherwise, the gate&#39;s output is zero. 
     For each gate  140 ( s ) in matrix  220  (where s is an integer from 1 to k), the control input is the s-th bit of information signal  20  and the data input is the s-th impulse response, obtained from lookup table  210 . For each gate  140 ( t ) in matrix  220  (where t is an integer from (k+1) to n), the control input is the (t−k)-th bit of the encoder state signal  80  and the data input is the (t−k)-th zero response as obtained from lookup table  210 . 
     XOR gate  250  receives the n outputs of AND gates  140 ( r ) and produces a (n−k)-bit-wide output. The p-th bit of the output of XOR gate  150  (where p is an integer from 1 to (n−k)) has (a) a value of one if an odd number of the p-th bits of the outputs of AND gates  140 ( r ) have values of one and (b) a value of zero if an even number of the p-th bits of the outputs of AND gates  140 ( r ) have values of one. In other words, the output of XOR gate  250  is a bitwise XOR of the inputs, the p-th bit of the output being the XOR of the p-th bits of the inputs. The output of XOR gate  250  is stored into CRC register  340  in response to a specified transition (e.g. a rising edge and/or a trailing edge) of update signal  40 . 
     As discussed above with respect to XOR gate  150 , in an exemplary implementation XOR gate  250  may comprise several or many logical gates having more limited input capacities (e.g. two-input NAND gates) that are arranged to perform the logical function described above. Additionally, as with logic matrix  120 , note that in implementing the logical functions described above, the actual construction of logic matrix  220  may take many forms other than the particular one shown in FIG.  10 . Because lookup table  210  is a constant for fixed G(X), n, and k, for example, it may be knowable a priori that certain bits of the data inputs to AND gates  140 ( r ) will be zero and that corresponding bits of the outputs of these gates, therefore, will also be zero. In one embodiment of an apparatus according to the invention, the configuration of logic matrix  220  is reduced to a more optimal form (e.g., a form that requires fewer logical gates to perform a logical operation equivalent to that shown in FIG. 13) by using an electronic design tool such as the Design Compiler produced by Synopsis, Inc. (Mountain View, Calif.). 
     Encoder state signal  80  represents the current state of encoder state register  340 . In an exemplary implementation, encoder state register  340  is initialized to store the desired encoder initial state. At a time when the first instance  20 - 1  of information signal  20  is present at the appropriate input of logic matrix  220 , encoder state register  340  presents this desired initial state to an appropriate input of logic matrix  220  via a first instance  80 - 0  of encoder state signal  80 . After sufficient time has passed for the output of logic matrix  220  (i.e. response signal  60 ) to stabilize, a specified transition of update signal  40  causes encoder state register  340  to store that output and to forward it to logic matrix  220  as a second instance  80 - 1  of encoder state signal  80 . 
     At a time when encoder state signal  80 - 1  is present at the appropriate input of logic matrix  220 , the next instance  20 - 2  of information signal  20  is present at the corresponding appropriate input of logic matrix  220 . After sufficient time has passed for response signal  60  to stabilize, a specified transition of update signal  40  causes encoder state register  340  to store that signal and to forward it to logic matrix  220  as a third instance  80 - 2  of encoder state signal  80 . This process continues until the final instance  20 -x of information signal  20 , and instance  80 -(x−1) of encoder state signal  80 , are presented to the appropriate inputs of logic matrix  220 . The output of logic matrix  220  (i.e. response signal  60 ) responsive to these inputs represents the desired checksum for the original data signal  50 , and this signal is outputted as checksum signal  30 . 
     For most applications, it will not be necessary for apparatus  200  to output any of the other instances of response signal  60  as checksum signal  30 . In another implementation, therefore, a register and/or gate may be provided at the output of apparatus  200  (e.g. controlled by an appropriate timing signal that may be based on update signal  40 ) in order to prevent other instances of response signal  60  from appearing on checksum signal  30 . 
     It may not be necessary for the total number of bits in data signal  50  to be a multiple of k. For example, data signal  50  may be padded by zeros to a length that is a multiple of k. Note, however, that in such case it may be necessary to perform a reverse cyclic shift on the final instance of checksum signal  30  (the number of shift positions corresponding to the number of padded zeros) in order to obtain a result equivalent to that which would be produced by shifting the unpadded data signal  50  into an encoder as shown, e.g., in FIG.  2 . 
     FIG. 14A shows a signal stream wherein each data signal  52  of a signal stream comprises a number of instances of information signals  22  of width k. FIG. 14B shows one example of how this signal stream may be configured after encoding to include the checksum signals  30 . 
     FIG. 15 shows an apparatus according to a further embodiment of the invention. With respect to encoder state register  340 , clock signal  70  performs a function in this apparatus analogous to that of update signal  40  in the apparatus of FIG.  9 . It is desirable for the period of clock signal  70  to be at least as long as the maximum time required for logic matrix  220  to stabilize after new instances of information signal  22  and staged encoder state signal  85  are presented at its inputs. 
     We begin a description of an exemplary application of the apparatus shown in FIG. 15 with the arrival of information signal  22   a   1  at an input to logic matrix  220 . Flow control  410  is configured (as described below, for example) such that staged encoder state signal  85  having the desired encoder initial state is present at an input to logic matrix  220  together with information signal  22   a   1 . After sufficient time to allow the state of apparatus  300  to settle, the resulting output of logic matrix  220  (i.e. response signal  60 ) is clocked into encoder state register  340  (and onto encoder state signal  80 ) by an assertion of clock signal  70 . Flow control  410  is configured to pass encoder state signal  80  (as staged encoder state signal  85 ) to an input of logic matrix  220 . 
     Information signal  22   a   2  now arrives at an input to logic matrix  220 . After sufficient settling time, response signal  60  is clocked into encoder state register  340  by another assertion of clock signal  70 . The desired checksum  30   a  (i.e. corresponding to an encoding of data signal  50   a  with the cyclic code generated by G(X)) is now present at the output of encoder state register  340  and may be outputted by apparatus  300  as needed. 
     In a similar manner, information signal  22   b   1  arrives at an input to logic matrix  220 , and flow control  410  is configured such that staged encoder state signal  85  presents the desired encoder initial state at another input to logic matrix  220 . The resulting output of matrix  220  (i.e. response signal  60 ) is clocked into encoder state register  340  (and onto encoder state signal  80 ) by an assertion of clock signal  70 . Flow control  410  is configured to pass encoder state signal  80  (as staged encoder state signal  85 ) to an input of logic matrix  220 . Information signal  22   b   2  then arrives at an input to logic matrix  220 . After sufficient settling time, clock signal  70  is asserted to clock response signal  60  into encoder state register  340  and thereby to the output of encoder state register  340  for output as the desired checksum  30   b . In an exemplary application, the data signals and corresponding checksums are then assembled as shown in FIG.  14 B. 
     Timed presentation of the initial encoder state to an input of logic matrix  220  is accomplished automatically via flow control block  410 . As illustrated in FIG. 16, block  410  may include a multiplexer  440  which passes staged encoder state signal  85  to an input of logic matrix  220  (i.e. to the (n−k) input lines shown to receive encoder state signal  80  in FIG.  10 ). Depending on a signal received from counter  420 , multiplexer  440  causes staged encoder state signal  85  to carry either encoder state signal  80  or the (n−k)-bit-wide initial encoder state (stored in initial value register  430 ). 
     Counter  420  operates according to a predetermined parameter z, where        z   =     ⌈     D   k     ⌉                            
     (i.e. the smallest integer not less than D/k) and D is the length of data signal  50  in bits. In the example of FIG. 16, z=2. The counting value of counter  420  is incremented at every cycle of clock signal  70  and is reset to zero every z clock cycles. When a counting value of counter  420  is zero, counter  420  causes multiplexer  440  to pass the initial encoder state from initial value register  430 . Otherwise, counter  420  causes multiplexer  440  to pass encoder state signal  80 . Many other arrangements for placing encoder state signal  80  and the initial encoder value onto staged encoder state signal  85  as appropriate are possible. 
     As shown in FIG. 17, an apparatus  400  according to a further embodiment of the invention may include an input register  230 , which receives data signal  52  and outputs k-bit-wide instances of information signal  22 . Input register  230  may receive the individual values of data signal  52  in series and/or in parallel. It is desirable for data signal  52  to supply data to input register  230  at a sufficient rate to allow input register  230  to supply the next instance of information signal  22  at each cycle of clock signal  70 . In an exemplary implementation, input register  230  may be constructed as a circular queue or ‘ring buffer.’ In another implementation, input register  230  may be constructed as a double buffer. In an implementation where read and write access to input register  230  may conflict, input register  230  may be implemented using a dual-port storage element. 
     The foregoing presentation of the described embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments are possible, and the generic principles presented herein may be applied to other embodiments as well. For example, the invention may be implemented in part or in whole as a hard-wired circuit, as a circuit configuration fabricated into an application-specific integrated circuit, or as a firmware program loaded into non-volatile storage or a software program loaded from or into a data storage medium as machine-readable code, such code being instructions executable by an array of logic elements such as a microprocessor, microcontroller, or other digital signal processing unit. Thus, the present invention is not intended to be limited to the embodiments shown above but rather is to be accorded the widest scope consistent with the principles and novel features disclosed in any fashion herein.