Abstract:
A correlated double sampler (CDS) circuit having a ping/pong architecture which employs only a single amplifier, and a CCD image sensor output processing circuit including such a CDS circuit and preferably also an analog-to-digital converter for processing the output of the CDS circuit and a black level correction feedback loop. In one cycle of operation (during processing of the raw output of a CCD sensor), the CDS circuit receives a first set of control signals followed by a second set of control signals, its output signal in response to the first set is indicative of the value of one pixel of a sensed image, and its output signal in response to the second set is indicative of the value of the next pixel of the image. Preferably, each set of control signals consists of a clamp signal, a sample signal, and a hold signal. Since the output signal of the CDS circuit has the same offset voltage for all pixels of an image, black level correction can be implemented using only one black level correction feedback loop. Use of a single amplifier (rather than two) and one black level correction loop (rather than two) reduces power consumption. Preferably, the amplifier of the CDS circuit produces a differential output so that the CDS circuit has a better power supply rejection ratio than do conventional CDS circuits. Also preferably, the invention is implemented with CMOS technology as an integrated circuit or portion of an integrated circuit.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to circuitry for preliminary processing of the raw output signal from a CCD image sensor. More particularly, the invention is (or includes) a correlated double sampler circuit including a single amplifier, having ping-pong architecture, and capable of processing a raw output signal from a CCD image sensor to generate an analog signal indicative of the value of each pixel of a sensed image. 
     2. Description of the Related Art 
     CCD (charge coupled device) image sensors are widely used to convert images into electronic signals that can be captured, transmitted, stored and displayed. Camcorders and digital still cameras typically use CCDs. 
     A CCD divides an image into a large number of discrete cells or pixels. The raw output signal produced by a CCD image sensor has a waveform of the type shown in FIG.  3 . The FIG. 3 signal is a series of discrete analog voltage levels. The high voltage level (which immediately precedes the low level portion of each cycle) is commonly called the “reset level”, while the lower voltage level is commonly called the “signal level”, as indicated in FIG.  3 . The difference between a signal level and its preceding reset level indicates the amount of light (typically of a particular color) that has fallen on one particular pixel of the image sensor. 
     One characteristic of CCDs is that each reset level is slightly different from the others due to noise. For this reason, it is important to quantify the difference between the signal level and its preceding reset level; not the absolute value of the signal level. It is common practice in systems that use CCDs to employ a circuit called a correlated double sampler (CDS) to sample and hold the difference between these two voltage levels (for each pixel of the sensed image). 
     FIG. 1 is a simplified block diagram of a conventional circuit, which includes two CDS circuits (CDS 1  and CDS 2 ) and has “ping-pong” architecture,” for preliminary processing of the raw output signal (labeled “IN”) of a CCD image sensor. The expression “ping-pong architecture” denotes that the FIG. 1 circuit is configured and controlled to process consecutive samples (of the signal IN) at the rate of one sample per clock cycle, with CDS 2  processing every even sample and CDS 1  processing every odd sample. This architecture provides an efficient solution to the problem of how to accomplish three sequential functions (clamp, sample, and hold) in response to two clock edges only per clock cycle. Another advantage of this architecture is that the hold cycle during which amplifier PGA takes the difference between the reset level and signal level (of a single sampled pixel) and presents this difference as output signal OUT can be a full clock cycle long. 
     It is well known to implement correlated double samplers (CDS&#39;s). For example, the AD9801 integrated circuit product manufactured by Analog Devices, implements the FIG. 1 circuit, which in turn includes two CDS&#39;s (CDS 1  and CDS 2 ). This implementation of the FIG. 1 circuit is described in C. Mangelsdorf, et al., “A CMOS Front-End for CCD Cameras,” Paper FA 11.5, Proceedings of the 1996 IEEE International Solid-State Circuits Conference (pp. 146-147 and 186-187). 
     In FIG. 1, CDS 1  includes circuitry implementing identical sample and hold circuits  1  and  2  and subtraction unit  5 , the circuits  1  and  2  being connected in parallel between the input node and subtraction unit  5 . CDS 2  includes circuitry implementing identical sample and hold circuits  3  and  4  (which are identical to circuits  1  and  2 ) and subtraction unit  6 , the circuits  3  and  4  being connected in parallel between the input node and subtraction unit  6 . Each of circuits CDS 1  and CDS 2  is a sample and hold amplifier (which consumes power and has an offset value). Switch S 1  selectively passes the output of CDS 1  or CDS 2  to amplifier  7 , and the output of amplifier  7  is asserted to sample and hold circuit  8 . The amplified signal output from amplifier  7  (the “OUTPUT” signal) is typically asserted by circuit  8  to an analog-to-digital converter (not shown). 
     Elements  9 ,  10 , and  13  (connected as shown) comprise a black level correction loop for CDS 1 , and elements  11 ,  12 , and  14  (connected as shown) comprise a black level correction loop for CDS 2 . Each black level correction loop provides feedback to set the output voltage OUTPUT to a known value for CCD pixel outputs of zero value (black). 
     The difference between portions of the OUTPUT signal indicative of black pixels (i.e., corresponding to masked portions of the CCD sensor) which have been processed by CDS 1 , and a desired output signal, are integrated in integration circuit  9 . The output of circuit  9  is amplified in inverse amplifier  10  (whose gain is the inverse of amplifier  7 &#39;s gain) and fed back to one input of addition unit  13 , and unit  13  adds the output of amplifier  10  to the output of unit  5  being asserted to the other input of unit  13 . The difference between portions of the OUTPUT signal indicative of black pixels which have been processed by CDS 2 , and a desired output signal, are integrated in integration circuit  11  (which is identical to circuit  9 ). The output of circuit  11  is amplified in inverse amplifier  12  (whose gain is the inverse of amplifier  7 &#39;s gain) and fed back to one input of addition unit  14 , and unit  14  adds the output of amplifier  10  to the output of unit  6  being asserted to the other input of unit  14 . 
     In each of correlated double samplers CDS 1  and CDS 2 , three functions must be executed during each clock cycle: sampling of the reset level, sampling of the signal level, and taking the difference between the two samples. The ping/pong approach, in which every odd sample of input signal IN (i.e., the first sample, the third sample, and so on) is processed by a first (ping) amplifier CDS 1  and every even sample is processed by a second (pong) amplifier CDS 2 , is an efficient solution to the problem of how to accomplish the three sequential functions in response to only two clock edges per amplifier per clock cycle. 
     Waveforms of the periodic control signals needed to operate the circuit of FIG. 1 are shown in FIG.  1 A. On the falling edge of control signal Q 1 , CDS 1  samples the input signal IN and asserts this sample (which is the sampled reset level) to subtraction unit  5 . On the falling edge of control signal Q 2 , CDS 1  again samples the input signal IN and asserts this sample (which is the sampled signal level) to subtraction unit  5 , and a control signal (not shown) is asserted to switch S 1  to cause switch S 1  to couple the output of CDS 1  to amplifier  7 . Then, while switch remains in this state, CDS 2  samples the input signal IN on the falling edge of control signal Q 3  and asserts this sample (which is the sampled reset level for the next pixel) to subtraction unit  6 . Then, on the falling edge of control signal Q 4 , CDS 2  again samples the input signal IN and asserts this sample (which is the sampled signal level for the same pixel) to subtraction unit  6 , and another control signal (not shown) is asserted to switch S 1  to cause switch S 1  to couple the output of CDS 2  to amplifier  7  (thereby decoupling the output of CDS 1  from amplifier  7 ). An advantage of the FIG. 1 implementation is that the hold cycle during which each of amplifiers CDS 1  and CDS 2  takes the different between a reset level and a signal level and presents this difference as an output signal (through switch S 1  to amplifier  7 ) is a full clock cycle in duration (such a full clock consists of a half cycle in which Q 1  is high and a half cycle in which Q 2  is high, or a half cycle in which Q 3  is high and a half cycle in which Q 4  is high). 
     A problem with the FIG. 1 circuit is that each of sample and hold amplifiers CDS 1  and CDS 2  has its own offset voltage. Since each of CDS 1  and CDS 2  has a different offset voltage, two separate black level correction loops must be employed, one for each of circuits CDS 1  and CDS 2 . 
     Another problem with conventional implementations of the FIG. 1 circuit is that the outputs of each of circuits CDS 1  and CDS 2  is referenced to ground (single ended). As a result, the FIG. 1 circuit has a poor power supply rejection ratio (PSRR). 
     U.S. Pat. Nos. 5,757,440 and 5,736,886 disclose implementations of the FIG. 1 circuit and variations thereon. For example, FIG. 8 of U.S. Pat. No. 5,757,440 discloses a variation on the FIG. 1 circuit which has ping-pong architecture and includes four sample and hold circuits (96, 98, 100, and 102) and a single subtraction element (“difference element” 127). However, there is no suggestion in either reference that a circuit having ping-pong architecture (for preliminary processing of a CCD image sensor&#39;s raw output) should be implemented to include only a single amplifier (having a single offset), and no suggestion as to how to implement such a single amplifier circuit. 
     It is known to implement a pipelined circuit to include a single operational amplifier (“op amp”) which is shared between adjacent stages of the pipelined circuit, and to implement other circuits including such a shared op amp. See, for example, Yu and Lee, “A 2.5-V, 12-b, 5-MSample/s Pipelined CMSO ADC,” IEEE Journal of Solid-State Circuits, Vol. 31, No. 12 (December 1996), pp. 1854-1861. 
     However, until the present invention, such an amplifier sharing technique has not been applied to a circuit implementing a CDS function for CCD processing applications (e.g., to overcome the limitations and disadvantages of conventional CDS circuits such as that described above with reference to FIG.  1 ). 
     SUMMARY OF THE INVENTION 
     In a class of preferred embodiments, the invention is a correlated double sampler (CDS) circuit having a ping/pong architecture, which includes only a single active amplifier (and thus a single offset voltage associated with the amplifier). In another class of embodiments, the invention is a CCD image sensor output processing circuit including such a CDS circuit. The CDS circuit includes capacitor and switch circuitry (comprising switches and capacitors, but not an amplifier) coupled between the input node (at which the raw CCD sensor output is received), the input of the amplifier, and the output of the amplifier. 
     In one cycle of operation during processing of the raw output of a CCD image sensor, the CDS circuit receives a first set of control signals followed by a second set of control signals, its output signal in response to the first set of control signals is indicative of the value of one pixel of a sensed image, and its output signal in response to the second set of control signals is indicative of the value of the next pixel of the image. In preferred implementations, each set of control signals consists of a clamp signal, a sample signal, and a hold signal. Since the output signal of the CDS circuit has the same offset voltage for all pixels of an image (including both even and odd pixels), black level correction can be implemented using only one black level correction feedback loop. Use of a single amplifier (rather than two or more amplifiers as in the prior art) and one black level correction loop (rather than two black level correction loops) reduces power consumption. 
     In preferred implementations, the amplifier of the inventive CDS circuit is an op amp which produces a differential output and therefore has a better power supply rejection ratio than does the prior art. 
     Preferably, the invention is implemented with CMOS technology as an integrated circuit (or portion of an integrated circuit). 
     The inventive circuit preferably has a continuous differential output. In operating the circuit, it is not important to cancel amplifier offset since the entire signal chain is in an offset adjusting feedback loop. It is important to keep the offset the same for every input signal sample (including samples of even pixels and samples of odd pixels) to avoid “even sample”-to-“odd sample” offset differences, and to minimize power consumption. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a conventional circuit, including two CDS circuits (CDS 1  and CDS 2 ), for preliminary processing of the raw output signal (labeled “IN”) of a CCD image sensor. 
     FIG. 1A is a timing diagram of the waveforms of several control signals asserted during operation of the FIG. 1 circuit. 
     FIG. 2 is a schematic diagram of a preferred embodiment of the inventive correlated double sampler circuit. 
     FIG. 3 is a diagram of the waveform of a raw output signal of a CCD image sensor (which is processed by the FIG. 2 circuit). 
     Each of FIGS. 4-9 is a diagram of the waveform of a different control signal asserted during operation of the FIG. 2 circuit. 
     FIG. 10 is a schematic diagram of a CMOS implementation an op amp which is suitable (in some applications) for implementing the op amp of FIG.  2 . 
     FIG. 11 is a block diagram of a circuit including the inventive correlated double sampler (element  21 ), an analog to digital converter (element  31 ), and black level correction circuitry (including element  33 ). 
     FIG. 12 is a block diagram of a variation on the circuit of FIG.  11 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 2 is simplified schematic diagram of a preferred embodiment of the inventive CDS circuit. The circuit of FIG. 2 comprises op amp  20  whose differential output (OUT P −OUT N ) has a sequence of values, each value indicative of an amount of light (typically having a particular frequency or narrow range of frequencies) that has fallen on a different one of the pixels of a CCD image sensor coupled to the input node IN. Each value of the amplifier output is indicative of the difference between a signal level and a reset level associated with one such pixel. The FIG. 2 circuit also includes capacitor and switch circuitry (comprising switches SW 1 -SW 22  and capacitors Cin 1 -Cin 4  and Cf 1 -Cf 4  connected as shown) coupled between the input node IN, the differential input of amplifier  20 , and the differential output of amplifier  20 . The capacitor and switch circuitry does not itself include any amplifier. 
     FIG. 3 is a diagram of the waveform of a raw output signal produced by a CCD image sensor. Such raw CCD sensor output signal is an example of the input signal (provided at node “IN” of FIG. 2) that is processed by the FIG. 2 circuit. 
     FIG. 4 is a diagram of the waveform of control signal C 1  (“Clamp 1”) asserted during operation of the FIG. 2 circuit, FIG. 5 is a diagram of the waveform of control signal S 1  (“Sample 1”) asserted during operation of the FIG. 2 circuit, FIG. 6 is a diagram of the waveform of control signal H 1  (“Hold 1”) asserted during operation of the FIG. 2 circuit, FIG. 7 is a diagram of the waveform of control signal C 2  (Clamp  2 ) asserted during operation of the FIG. 2 circuit, FIG. 8 is a diagram of the waveform of control signal S 2  (Sample  2 ) asserted during operation of the FIG. 2 circuit, and FIG. 9 is a diagram of the waveform of control signal H 2  (Hold  2 ) asserted during operation of the FIG. 2 circuit. 
     With reference to FIG. 2, the input signal is asserted at input node IN from a CCD image sensor (not shown). Each of the switches labeled SW 1 , SW 2 , SW 3 , and SW 4  has a first terminal coupled to the input node. Switch SW 1  has a second terminal coupled to capacitor Cin 4 , switch SW 2  has a second terminal coupled to capacitor Cin 2 , switch SW 3  has a second terminal coupled to capacitor Cin 1 , and switch SW 4  has a second terminal coupled to capacitor Cin 3 . Switch SW 5  is connected between the second terminal of switch SW 2  and the second terminal of switch SW 3 , switch SW 6  is connected between the second terminal of switch SW 1  and the second terminal of switch SW 4 , switches SW 7  and SW 8  are connected in series between Node  1  and Node  2 , and switches SW 9  and SW 10  are connected in series between Node  3  and Node  4 . A first terminal of switch SW 11  is connected to Node  3 , a first terminal of switch SW 12  is connected to Node  1 , a first terminal of switch SW 13  is connected to Node  2 , and a first terminal of switch SW 14  is connected to Node  4 . 
     A first terminal of capacitor Cf 4  is connected to Node  3 , a first terminal of capacitor Cf 2  is connected to Node  1 , a first terminal of capacitor Cf 1  is connected to Node  2 , and a first terminal of capacitor Cf 3  is connected to Node  4 . Switch SW 15  is connected between a second terminal of capacitor Cf 4  and output node  10 , switch SW 16  is connected between a second terminal of capacitor Cf 2  and output node  10 , switch SW 17  is connected between a second terminal of capacitor Cf 1  and output node  11 , and switch SW 18  is connected between a second terminal of capacitor Cf 3  and output node  11 . Switches SW 19  and SW 20  are connected in series between Node  5  and Node  6 , and switches SW 21  and SW 22  are connected in series between Node  8  and Node  9 . Preferably, capacitors Cf 1  and Cf 2  have identical capacitances and capacitors Cin 1  and Cin 2  have identical capacitances (but the capacitance of Cf 1  need not be the same as that of Cin 1  in all preferred embodiments). 
     Switches SW 1 , SW 2 , SW 3 , SW 4 , SW 5 , SW 6 , SW 7 , SW 8 , SW 9 , SW 10 , SW 11 , SW 12 , SW 13 , SW 14 , SW 15 , SW 16 , SW 17 , SW 18 , SW 19 , SW 20 , SW 21 , and SW 22  are controlled by signals S 2 , S 1 , C 1 , C 2 , H 1 , H 2 , S 1 , C 1 , S 2 , C 2 , H 2 , H 1 , H 1 , H 2 , H 2 , H 1 , H 1 , H 2 , H 1 , H 2 , H 2 , and H 1  respectively. 
     In operation, signals S 1 , S 2 , C 1 , C 2 , H 1 , and H 2  initially have values which open all of switches SW 1 , SW 2 , SW 3 , SW 4 , SW 5 , SW 6 , SW 7 , SW 8 , SW 9 , SW 10 , SW 11 , SW 12 , SW 13 , SW 14 , SW 15 , SW 16 , SW 17 , SW 18 , SW 19 , and SW 22 . Then, a falling edge of signal C 1  causes switches SW 3  and SW 8  to close. In response to the falling edge of signal C 1 , a sample of input signal at input node IN (indicative of the reset level of a first pixel) is sampled onto capacitor Cin 1  while the right plate of Cin 1  is held at a constant voltage (cmi). At the same time, the left plate of feedback capacitor Cf 1  is held at the constant voltage (cmi) while its right plate is held at another constant voltage (cmo). 
     Then, a falling edge of signal S 1  causes switches SW 2  and SW 7  to close. In response to the falling edge of signal S 1 , a sample of input signal at input node IN (indicative of the signal level of the first pixel) is sampled onto the left plate of capacitor Cin 2  while the right plate of capacitor Cin 2  is held at the constant voltage, cmi. At the same time, the left plate of feedback capacitor Cf 2  is connected to the constant voltage cmi, while its right plate is held at the other constant voltage (cmo). 
     Then, a falling edge of signal H 1  causes switches SW 5 , SW 12 , SW 13 , SW 16 , SW 17 , SW 19 , and SW 22  to close. In response to the falling edge of signal H 1 , the right plates of capacitors Cin 1  and Cin 2  are connected to the input nodes of op amp  20  (which is a differential amplifier) and the left plates of capacitors Cin 1  and Cin 2  are shorted together. At the same time, feedback capacitors Cf 1  and Cf 2  are connected between the input and output nodes of the differential amplifier. Since charge must be conserved, and since the right plates of capacitors Cin 1  and Cin 2  and the left plates of capacitors Cf 1  and Cf 2  remain at the voltage level cmi, the difference between the output nodes of differential amplifier  20  must equal the difference between the reset level and the signal level of the first pixel, assuming that the capacitances are equal (i.e., Cin 1 =Cin 2 =Cf 1 =Cf 2 ). If Cin 1 =Cin 2  and Cf 1 =Cf 2 , but Cin 1  is not equal to Cf 1 , there will be a gain associated with the circuit whose value is readily apparent to those of ordinary skill in the art. 
     After the falling edge of S 1  and before the falling edge of H 1 , a falling edge of signal C 2  causes switches SW 4  and SW 10  to close. In response to the falling edge of signal C 2 , a sample of input signal at input node IN (indicative of the reset level of a second pixel) is sampled onto capacitor Cin 3  while the right plate of Cin 3  is held at the constant voltage (cmi). At the same time, the left plate of feedback capacitor Cf 3  is held at the constant voltage (cmi) while its right plate is held the other constant voltage (cmo). 
     After the falling edge of C 2  but before the falling edge of H 1 , a falling edge of signal S 2  causes switches SW 1  and SW 9  to close. In response to the falling edge of signal S 2 , a sample of input signal at input node IN (indicative of the signal level of the second pixel) is sampled onto the left plate of capacitor Cin 4  while the right plate of capacitor Cin 4  is held at the constant voltage, cmi. At the same time, the left plate of feedback capacitor Cf 4  is connected to the constant voltage cmi, while its right plate is held at the other constant voltage (cmo). 
     Then, a falling edge of signal H 2  causes switches SW 6 , SW 11 , SW 14 , SW 15 , SW 18 , SW 20 , and SW 21  to close, and a rising edge of signal H 1  causes switches SW 5 , SW 12 , SW 13 , SW 16 , SW 17 , SW 19 , and SW 22  to open. In response to these transitions of signals H 1  and H 2 , the right plates of capacitors Cin 3  and Cin 4  are connected to the input nodes of differential amplifier  20  and the left plates of capacitors Cin 3  and Cin 4  are shorted together. At the same time, feedback capacitors Cf 3  and Cf 4  are connected between the input and output nodes of the differential amplifier (and capacitors Cf 1  and Cf 2  are disconnected from the input and output nodes of the differential amplifier). Since charge must be conserved, and since the right plates of capacitors Cin 3  and Cin 4  and the left plates of capacitors Cf 3  and Cf 4  remain at the voltage level cmi, the difference between the output nodes of differential amplifier  20  must equal the difference between the reset level and the signal level of the second pixel, assuming that the capacitances are equal (i.e., Cin 3 =Cin 4 =Cf 3 =Cf 4 ). 
     Thus, the differential output (OUT P −OUT N ) of amplifier  20  progresses from one difference signal to the next as the clocks H 1  and H 2  alternate (180 degrees out of phase with respect to each other). 
     In other words, the FIG. 2 circuit comprises: 
     a first capacitor branch (including SW 2  and Cin 2 ) configured to sample a reset level of an odd pixel of a raw sensor output signal in response to a first set of values of control signals S 1 , C 1 , H 1 , S 2 , C 2 , and H 2 ; 
     a second capacitor branch (including SW 3  and Cin 1 ) configured to sample a signal level of the odd pixel in response to a second set of values of the control signals; 
     a third capacitor branch (including SW 1  and Cin 4 ) configured to sample a reset level of an even pixel of the raw sensor output signal in response to a third set of values of the control signals; 
     a fourth capacitor branch (including SW 4  and Cin 3 ) configured to sample a signal level of the even pixel in response to a fourth set of values of the control signals; and 
     fifth switch and capacitor circuitry (the other elements of the FIG. 2 circuit, excluding amplifier  20 ) configured to assert the signal level of the odd pixel, the reset level of the odd pixel, and first feedback signals (through switches SW 16  and SW 17 ) from the output terminals of amplifier  20  to the input terminals of amplifier  20  in response to a fifth set of values of the control signals, and configured to assert the signal level of the even pixel, the reset level of the even pixel, and second feedback signals (through switches SW 15  and SW 18 ) from the output terminals of amplifier  20  to the input terminals of amplifier  20  in response to a sixth set of values of the control signals. 
     The differential output of amplifier  20  of FIG. 2 is typically amplified in a programmable gain amplifier (not shown in FIG. 2) and then provided to an analog-to-digital converter (not shown in FIG.  2 ). The FIG. 2 circuit can be implemented as an integrated circuit whose output is provided to an integrated circuit analog-to-digital converter, or the FIG. 2 circuit can be implemented as part of an integrated circuit which also includes an analog-to-digital converter. 
     The FIG. 2 circuit has a continuous differential output, in the sense that the differential output (OUT P −OUT N ) of amplifier  20  does not periodically return to zero. In operating the circuit, it is not necessary to cancel amplifier offsets since the entire signal chain is in an offset adjusting feedback loop. The offsets remain the same for every input signal sample (including samples of both even and odd pixels), so that the circuit avoids offset differences between even samples and odd samples. As a consequence, the FIG. 2 circuit consumes low power during operation. 
     FIG. 10 is a schematic diagram of a CMOS implementation an op amp which is suitable (in some applications) for implementing differential amplifier  20  of FIG.  2 . The FIG. 10 circuit comprises four NMOS transistors, four PMOS transistors, and a current sink, connected as shown. 
     FIG. 11 is a block diagram of a circuit including correlated double sampler  21  (CDS  21  is an embodiment of the present invention, preferably the embodiment described above with reference to FIG.  2 ), programmable gain amplifier  27  which amplifies the corrected output of CDS  21  (the output of CDS  21  is corrected by units  23  and  25  in a manner to be described), sample and hold unit  29  (which is controlled to sample and hold the output of amplifier  27 ), analog to digital converter  31  (which converts samples of the analog output of amplifier  27  to digital signals), and black level correction circuitry (including addition units  23  and  25 , and black clamp circuit  33 ), connected as shown. The black level correction circuitry implements a loop which provides feedback to set the differential output signal of CDS  21  to a known value for CCD pixel outputs of zero value (black). 
     Black clamp circuit  33  receives the digitized output (OUT) of A-to-D converter  31 , and operates in response to control signals CTL to integrate the differences between portions of this digitized output indicative of black pixels (i.e., portions which correspond to masked portions of the CCD sensor) and a desired reference level, and generate a differential analog signal (a correction signal) indicative of the output of the integration. Circuit  33  also applies inverse gain (i.e., inverse to the gain applied by amplifier  27 ) to the output of the integration operation, so that the level of the correction signal does not depend on the gain applied by amplifier  27 . The correction signal is a differential signal comprising analog signal CP and analog signal CN. Signal CP is fed back to one input of addition unit  23 , and signal CN is fed back to one input of addition unit  25 . Units  23  and  25  correct the differential output (OUT P −OUT N ) of CDS  21  by generating corrected differential output signal O CP −O CN , where the level of O CP  is OUT P +CP and the level of O CN  is OUT N +CN. 
     The FIG. 11 circuit can be implemented as an integrated circuit, or as part of an integrated circuit. 
     In variations on the FIG. 11 circuit, the black level correction circuitry is implemented in any of a number of alternative ways. For example, a first one of such variations (shown in FIG. 12) differs from the FIG. 11 only in that the black level correction feedback loop is accomplished with analog circuitry. Elements  21 ,  23 ,  25 ,  27 ,  29 , and  31  of the FIG. 12 circuit are identical to the identically numbered elements in FIG.  11 . In FIG. 12, black clamp circuit  33  is replaced by analog black clamp circuit  133  which receives the analog input to A-to-D converter  31  (rather than the output of the A-to-D converter), and performs (with analog circuitry) analog counterparts to the described operations performed by black clamp circuit  33 . In the FIG. 12 embodiment, the black level correction circuitry is implemented entirely with analog circuitry. 
     In another variation, black clamp circuit  33  generates a single analog output signal (rather than two analog output signals which together determine a differential output signal), and circuits  23  and  25  are replaced by a circuit (at the input of CDS  21 ) which adds this single analog output signal to the raw CCD signal. In a third variation, black clamp circuit  33  of FIG. 11 is replaced by a circuit which receives the analog input to A-to-D converter  31 , performs (with analog circuitry) analog counterparts to the described operations performed by black clamp circuit  33  to generate a single analog output signal (rather than two analog output signals which together determine a differential output signal), and circuits  23  and  25  are replaced by a circuit (at the input of CDS  21 ) which adds this single analog output signal to the raw CCD signal. 
     Although only preferred embodiments have been described in detail herein, those having ordinary skill in the art will certainly understand that many modifications are possible without departing from the teachings hereof. All such modifications are intended to be encompassed within the following claims.