Abstract:
A power semiconductor device comprising a trench IGBT, a trench MOSFET and a fast switching diode for reduction of turn-on loss is disclosed. The inventive semiconductor power device employs a fast switching diode instead of body diode in the prior art. Furthermore, the inventive semiconductor power device further comprises an additional ESD protection diode between emitter metal and gate metal.

Description:
FIELD OF THE INVENTION 
       [0001]    This invention relates generally to the device configuration for fabricating the semiconductor power device. More particularly, this invention relates to an improved and novel device configuration for providing a power semiconductor power device comprising a trench IGBT (Insulation Gate Bipolar Transistor), trench MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and fast switching diode for reduction of turn-on loss. 
       BACKGROUND OF THE INVENTION 
       [0002]      FIG. 1A  shows an equivalent circuit of a hybrid trench IGBT and trench MOSFET with a parasitic body diode for on-resistance reduction at Vice (Voltage between collector and emitter, similarly hereinafter) below 0.6V, please refer to the cross sectional view in  FIG. 1B  having a parasitic P+ body diode underneath each the trenched source-body contact which is disclosed in U.S. Pat No. 6,627,961. 
         [0003]    However, the P+ heavily doped parasitic body diode in the trench MOSFET has low switching speed and high reverse recovery current due to the fact that high values of Trr (body diode reverse recovery time, similarly hereinafter) and Qrr (body diode reverse recovery charge, similarly hereinafter) increase complimentary MOSFET turn-on loss. Moreover, kr (body diode reverse recovery current, similarly hereinafter) may increase to a point at which the circuit is damaged. 
         [0004]    Please refer to  FIG. 1C  for wave form of body diode reverse recovery current. The prior art discussed above inherently has wave form  21  (solid line) of body diode showing a high peak reverse recovery current Irrp 1  with a steep slope of dIrr 1 /dt and ringing because the p+ heavily doped parasitic body diode in  FIG. 1B  is heavily doped that causes high hole injection efficiency. The softness of the recovery wave form corresponds to the slope of Irr 1  (i.e. dIrr 1 /dt) as it tends toward zero after time t. The stepper the slope, the less soft the recovery wave form and the greater the chance that the ringing will result. The ringing is caused by the kr overshoots too quickly and then oscillates back and forth till zero, and Qrr has high value as mentioned above as defined by 0.5*Irrp*trr. The softness is mainly determined by P− type doping concentration of the P+ body diode. The higher doping concentration, the less softness. The wave form  22  (dash line) of body diode having less P-type doping concentration shows a less peak reverse recovery current Irrp 2  with a less slope of dIrr 2 /dt and no ring oscillation. 
         [0005]    Accordingly, it would be desirable to provide a new and improved semiconductor power device configuration to avoid the constraint discussed above. 
       SUMMARY OF THE INVENTION 
       [0006]    It is therefore an aspect of the present invention to provide a new and improved semiconductor power device comprising a trench IGBT, trench MOSFET and fast switching diode for reduction of switching loss, further comprising: an emitter node of the trench IGBT connected to a source node of the trench MOSFET and an anode node of the fast switching diode; a collector node of the trench IGBT connected to a drain node of the trench MOSFET and a cathode node of the fast switching diode; and a gate node of the trench IGBT connected to that of the trench MOSFET. 
         [0007]    In accordance with another aspect of the present invention, the novel semiconductor power device can be implemented by a trench MOSFET monolithically integrated with a fast switching diode, copacked together with a trench IGBT of a separate discrete die on a common heat sink in same package; or a trench IGBT monolithically integrated with a trench MOSFET and a fast switching diode into a same die. 
         [0008]    In accordance with another aspect of the present invention, the fast switching diode can be implemented by a Schottky diode with Schottky barrier layer or a soft recovery diode formed by PN junction. 
         [0009]    In accordance with another aspect of the present invention, the trench IGBT can by implemented by a trench PT (Punch-Through) IGBT or a trench NPT (Non-Punch-Through) IGBT. 
         [0010]    In accordance with another aspect of the present invention, the inventive semiconductor power device further comprises an ESD gate protection diode. 
         [0011]    Briefly, in a preferred embodiment of the present invention, the inventive semiconductor power device comprises a copacked trench PT IGBT with a trench MOSFET monolithically integrated with a Schottky diode. The trench PT IGBT is formed in an N− epitaxial layer onto an N+ epitaxial layer supported onto a P+ substrate coated with collector metal on rear side. The trench PT IGBT further comprises: a plurality of trenched gates which are spaced apart by a plurality of P base regions and a plurality of n+ emitter regions encompassed in the P base regions; a plurality of trenched emitter-base contacts penetrating through an insulation layer and the n+ emitter regions, and extending into the P base regions between every two adjacent of the trenched gates; a plurality of p+ base ohmic contact doped regions formed within the P base regions and surrounding at least bottom of each the trenched emitter-base contact underneath the n+ emitter region; an emitter metal overlying the insulation layer and connected to all the trenched emitter-base contacts. The trench MOSFET monolithically integrated with a Schottky diode is formed in the N− epitaxial layer supported on an N+ substrate coated with drain metal on rear side. The trench MOSFET monolithically integrated with a Schottky diode further comprises: a plurality of the trenched gates formed in the second N− epitaxial layer; a plurality of P body regions encompassing a plurality of n+ source regions between every two adjacent of the trenched gates in the trench MOSFET portion; a plurality of trenched source-body contacts penetrating through the insulation layer in the trench MOSFET portion and the n+ source regions, and extending into the P body regions in the trench MOSFET portion; a plurality of p+ body ohmic contact doped regions formed within the P body regions and surrounding at least bottom of each the trenched source-body contact underneath the n+ source regions in the trench MOSFET portion; a plurality of trenched anode contacts penetrating through the insulation layer and extending into the second N− epitaxial layer in the Schottky diode portion; a plurality of n− Schottky barrier height enhancement regions surrounding bottom and sidewall of each the trenched anode contact within the second N− epitaxial layer in the Schottky diode portion. 
         [0012]    Briefly, in a second preferred embodiment of the present invention, the inventive semiconductor power device has a similar configuration with the first embodiment, except that the trench MOSFET is monolithically integrated with a soft recovery diode which is formed by a PN junction. Therefore, in the soft recovery diode portion, bottom and sidewall of each the trenched anode contact is surrounded by a p type anode doped region P* having peak concentration less than 1E19 cm −3  instead of the n− Schottky barrier height enhancement region within the second N− epitaxial layer. 
         [0013]    Briefly, in a third preferred embodiment of the present invention, the inventive semiconductor power device has a similar configuration with the first embodiment, except that the trench IGBT is a trench NPT IGBT which is formed in an N− FZ (Float Zone) of which rear side has P+ doped region as collector region of the trench NPT IGBT. 
         [0014]    Briefly, in a fourth preferred embodiment of the present invention, the inventive semiconductor power device has a similar configuration with the second embodiment, except that the trench IGBT is a trench NPT IGBT which is formed in an N− FZ of which rear side has P+ doped region as collector region of the trench NPT IGBT. 
         [0015]    Briefly, in a fifth preferred embodiment of the present invention, the inventive semiconductor power device comprises a trench NPT IGBT monolithically integrated with a trench MOSFET and a Schottky diode into a same die. The trench NPT IGBT, the trench MOSFET and the Schottky diode are all formed in an N− FZ of which rear side has P+ doped region as collector region of the trench NPT IGBT in the trench NPT IGBT portion, and has an N+ doped region as drain region of the trench MOSFET and as cathode region of the Schottky diode in the trench MOSFET and the Schottky diode portions, respectively. The N+ doped region is also disposed in a termination region. The fifth embodiment of the present invention further comprises: a plurality of trenched gates formed in the N− FZ substrate; a plurality of P base regions locating between every two adjacent of the trenched gates in the trench NPT IGBT and the trench MOSFET portions; a plurality of n+ emitter regions encompassed in and near top surface of the P base regions; a plurality of trenched emitter-base contacts penetrating through an insulation layer and the n+ emitter regions, and extending into the P base regions in the trench NPT IGBT and the trench MOSFET portions; a plurality of p+ base ohmic contact doped regions within the P base regions and surrounding at least bottom of each the trenched emitter-base contact underneath the n+ emitter region; a plurality of P body regions encompassing a plurality of n+ source regions between every two adjacent of the trenched gates in the trench MOSFET portion; a plurality of trenched source-body contacts penetrating through the insulation layer and the n+ source regions, and extending into the P body regions in the trench MOSFET portion; a plurality of p+ body ohmic contact doped regions formed within the P body regions and surrounding at least bottom of each the trenched source-body contact underneath the n+ source regions in the trench MOSFET portion; a plurality of trenched anode contacts penetrating through the insulation layer and extending into the N− FZ substrate in the Schottky diode portion; a plurality of n− Schottky barrier height enhancement regions surrounding bottom and sidewall of each the trenched anode contact within the N− FZ substrate in the Schottky diode portion; an emitter metal overlying the insulation layer and connected to the trenched emitter-base contacts, trenched source-body contacts and trenched anode contacts; a collector metal disposed on rear side of the P+ and the N+ doped regions. 
         [0016]    Briefly, in a sixth preferred embodiment of the present invention, the inventive semiconductor power device has a similar configuration with the fifth embodiment, except that the trench MOSFET is monolithically integrated with a soft recovery diode. Therefore, in the soft recovery diode portion, bottom and sidewall of each the trenched anode contact is surrounded by a P* anode doped region instead of the n− Schottky barrier height enhancement region within the N− FZ substrate to form a P*/N epitaxial junction diode. 
         [0017]    Briefly, in a seventh embodiment of the present invention, the inventive semiconductor power device has a similar configuration with the fifth embodiment, except further comprising an ESD gate protection diode next to the Schottky diode portion. The ESD gate protection diode includes an array of doped regions alternatively doped with n+ type dopant and p type dopant with a first and last doped regions doped with n+ type dopant wherein one of the two doped regions is connected to the emitter metal and another connected to gate metal by trenched ESD contact. Specially, underneath each of the trenched ESD contact, a trenched gate is formed as a buffer layer to avoid ESD diode shortage issue to the base or body regions disposed underneath the ESD gate protection diode in case the trenched ESD contact is overetched through the n+ doped regions. 
         [0018]    Briefly, in an eighth embodiment of the present invention, the inventive semiconductor power device has a similar configuration with the sixth embodiment, except further comprising an ESD gate protection diode next to the soft recovery diode. The ESD gate protection diode includes an array of doped regions alternatively doped with n+ type dopant and p type dopant with a first and last doped regions doped with n+ type dopant wherein one of the two doped regions connected to the emitter metal and another connected to gate metal by trenched ESD contact. Specially, underneath each of the trenched ESD contact, a trenched gate is formed as a buffer layer to avoid the ESD shortage issue. 
         [0019]    These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment, which is illustrated in the various drawing figures. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0020]    The present invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein: 
           [0021]      FIG. 1A  is an equivalent circuit of a hybrid IGBT and MOSFET with a parasitic body diode of prior art. 
           [0022]      FIG. 1B  is a cross-section view of an IGBT monolithically integrated with MOSFET having a parasitic body diode of prior art. 
           [0023]      FIG. 1C  is a wave form showing body diode reverse recovery current. 
           [0024]      FIG. 2  is another equivalent circuit of copacked trench IGBT with a trench MOSFET monolithically integrated with a Schottky diode according to the present invention. 
           [0025]      FIG. 3  is another equivalent circuit of copacked trench IGBT with a trench MOSFET monolithically integrated with a soft recovery diode according to the present invention. 
           [0026]      FIG. 4  is another equivalent circuit of monolithically integrated trench IGBT with a trench MOSFET and a Schottky diode as well as an ESD gate protection diode according to the present invention. 
           [0027]      FIG. 5  is another equivalent circuit of monolithically integrated trench IGBT with a trench MOSFET, a soft recovery diode as well as an ESD gate protection diode according to the present invention. 
           [0028]      FIG. 6A  is a cross-sectional view of the PT trench IGBT portion according to the first and second embodiments. 
           [0029]      FIG. 6B  is a cross-sectional view of a copacked NPT trench IGBT according to the third and fourth embodiments. 
           [0030]      FIG. 6C  is a cross-sectional view of the trench MOSFET monolithically integrated with the Schottky diode portion according to the first and third embodiments. 
           [0031]      FIG. 6D  is a cross-sectional view of the trench MOSFET monolithically integrated with the soft recovery diode portion according to the second and fourth embodiments. 
           [0032]      FIG. 7A  is a cross-sectional view of the present invention according to the fifth embodiment. 
           [0033]      FIG. 7B  is a cross-sectional view of the present invention according to the sixth embodiment. 
           [0034]      FIG. 8A  is a cross-sectional view of the present invention according to the seventh embodiment. 
           [0035]      FIG. 8B  is a cross-sectional view of the present invention according to the eighth embodiment. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0036]    Please refer to  FIG. 2  for an equivalent circuit of the present invention comprising a copacked trench IGBT with a trench MOSFET monolithically integrated with a Schottky diode in a same package, wherein the trench IGBT can be implemented by a trench PT IGBT or by a trench NPT IGBT. The equivalent circuit comprises an emitter node of the trench IGBT connected to a source node of the trench MOSFET and an anode node of the Schottky diode, a collector node of the trench IGBT connected to a drain node of the trench MOSFET and cathode node of the Schottky diode, and a gate node of the trench IGBT connected to that of the trench MOSFET. 
         [0037]    Please refer to  FIG. 3  for an equivalent circuit of the present invention comprising a copacked trench IGBT with a trench MOSFET monolithically integrated with a soft recovery diode in a same package, wherein the trench IGBT can be implemented by a trench PT IGBT or by a trench NPT IGBT. 
         [0038]    Please refer to  FIG. 4  for an equivalent circuit of the present invention comprising an integrated trench IGBT with a trench MOSFET and a Schottky diode on a single die. More particularly, an ESD gate protection diode is optionally added between the emitter region and gate region. 
         [0039]    Please refer to  FIG. 5  for an equivalent circuit of the present invention comprising an integrated trench IGBT with a trench MOSFET and a soft recovery diode on a single die. More particularly, an ESD gate protection diode is optionally added between the emitter region and gate region. 
         [0040]    Please refer to  FIG. 6A  for cross-sectional view of a copacked trench PT IGBT portion which formed in an N− epitaxial layer  200  grown onto an N+ epitaxial layer  201  supported onto a P+ substrate  202  coated with collector metal  203  on rear side. A plurality of trenched gates  204  are formed in the first N− epitaxial layer  200  and surrounded by a plurality of P base regions  205  encompassing n+ emitter regions  206  near top surface. A plurality of trenched emitter-base contacts  207  are penetrating through an insulation layer  208 , the n+ emitter regions  206  and extending into the P base regions  205 . A plurality of p+ base ohmic contact doped regions  209  are formed within the P base regions  205  and surrounding at least bottom of each the trenched emitter-base contacts  207 . An emitter metal  210  is formed overlying the insulation layer  208  and connected to all the trenched emitter-base contacts  207  to contact with the P base regions  205 , the n+ emitter regions  206 , as well as a deep P well  213  in termination area which comprising multiple of the deep P wells. 
         [0041]    Please refer to  FIG. 6B  for cross-sectional view of a copacked trench NPT IGBT portion which has similar configuration with  FIG. 6A , except that the trench NPT IGBT is formed in an N− FZ substrate  300  of which rear side has a P+ doped region  301  as collector region. 
         [0042]    Please refer to  FIG. 6C  for cross-sectional view of a trench MOSFET monolithically integrated with a Schottky diode which formed in an N− epitaxial layer  400  grown on an N+ epitaxial layer  401  coated with drain metal  403  on rear side. A plurality of trenched gates  404  are formed in the N− epitaxial layer  400  and surrounded by a plurality of P body regions  405  encompassing n+ source regions  406  near top surface in the trenched MOSFET portion. A plurality of trenched source-body contacts  407  are penetrating through an insulation layer  408 , the n+ source regions  406  and extending into the P body regions  405  in the trench MOSFET portion. A plurality of p+ body ohmic contact doped regions  409  are formed within the P body regions  406  and surrounding at least bottom of each the trenched source-body contact  407  underneath the n+ source regions  406  in the trenched MOSFET portion. A plurality of trenched anode contacts  417  are penetrating through an insulation layer  408  and extending into the N− epitaxial layer  400  wherein the source and body regions in the trench MOSFET portion do not exist in the Schottky diode portion. A plurality of n− Schottky barrier height enhancement regions  402  in contact with a silicide layer are formed surrounding bottom and sidewall of each the trenched anode contact  417  within the N− epitaxial layer  400  in the Schottky diode portion. A source metal  410  is formed overlying the insulation layer  408  and connected to the P body regions  405  and the n+ source regions  406  in the trenched MOSFET portion and the n− barrier height enhancement regions  402  in the Schottky diode portion through contact metal plugs filled in the trenched source-body contacts  407  and the trenched anode contacts  417 . Meanwhile, the source metal  410  is connected to a deep P well  413  in termination area which comprising multiple of the deep P wells. 
         [0043]    Please refer to  FIG. 6D  for a trench MOSFET monolithically integrated with a soft recovery diode which has similar configuration with  FIG. 6C , except that in the soft recovery diode portion, bottom and sidewall of each the trenched source-body contact  517  is surrounded by a P* anode doped region  502  within the N− epitaxial layer  500 , having peak concentration less than 1E19 cm −3 . 
         [0044]    Therefore, according to the present invention, the first preferred embodiment comprises copacked trench PT IGBT in  FIG. 6A  and trench MOSFET monolithically integrated with a Schottky diode in  FIG. 6C ; the second preferred embodiment comprises copacked trench NPT IGBT in  FIG. 6B  and trench MOSFET monolithically integrated with a Schottky diode in  FIG. 6C ; the third preferred embodiment comprises copacked trench PT IGBT in  FIG. 6A  and trench MOSFET monolithically integrated with a soft recovery diode in  FIG. 6D ; the fourth preferred embodiment comprises copacked trench NPT IGBT in  FIG. 6B  and trench MOSFET monolithically integrated with a soft recovery diode in  FIG. 6D . 
         [0045]    Please refer to  FIG. 7A  for cross-sectional view of the fifth preferred embodiment of the present invention which comprises a trench NPT IGBT monolithically integrated with a trench MOSFET and a Schottky diode into a same die. The fifth preferred embodiment is formed in an N− FZ substrate  600  of which rear side has a p+ doped region  601  as collector region in the trench NPT IGBT portion, and an N+ doped region  602  as drain region in the trench MOSFET and as cathode region in the Schottky diode portion. A plurality of trenched gates  604  are formed in the N− FZ substrate  600  and surrounded by a plurality of P base regions  605  encompassing n+ emitter regions  606  in the trench NPT IGBT portion and the trench MOSFET portion. A plurality of trenched emitter-base contacts  607  are penetrating through an insulation layer  608 , the n+ emitter regions  606  and extending into the P base regions  605  in trench NPT IGBT portion. A plurality of p+ base ohmic contact doped regions  609  are formed within the P base regions  605  and surrounding at least bottom of each the trenched emitter-base contact  607 . A plurality of trenched source-body contacts  617  are penetrating through the insulation layer  608 , the n+ source regions  616  and extending into the P body regions  615  in trench MOSFET portion. A plurality of trenched anode contacts  627  are penetrating through the insulation layer  608  and extending into the N− FZ substrate in Schottky diode portion. A plurality of n− Schottky barrier height enhancement regions  610  in contact with a silicide layer are formed surrounding bottom and sidewall of each the trenched anode contact  627  within the N− FZ substrate  600  in the Schottky diode portion. An emitter metal  611  is formed overlying the insulation layer  608  and connected to the P base regions  605  and the n+ emitter regions  606  in the trench NPT IGBT portion, the body region  615  and n+ source region  616  in the trench MOSFET portion, and the anode region in the Schottky diode portion through contact metal plugs filled in the trenched emitter-base, source-body and anode contacts. Meanwhile, the emitter metal  611  is connected to a deep P well  613  in termination area which comprises multiple of the deep P wells. A collector metal  612  is formed on rear side of the P+ doped region  601  and the N+ doped region  602 . 
         [0046]    Please refer to  FIG. 7B  for cross-sectional view of the sixth preferred embodiment of the present invention which comprises a trench NPT IGBT monolithically integrated with a trench MOSFET and a soft recovery diode into a same die. Therefore, bottom and sidewall of each the trenched anode contact  717  is surrounded by a P* anode doped region  710  within the N− epitaxial layer  700 . 
         [0047]    Please refer to  FIG. 8A  for cross-sectional view of the seventh preferred embodiment of the present invention with an additional ESD gate protection diode comparing to  FIG. 7A . The ESD gate protection diode comprises an array of doped regions alternatively doped with n+ type dopant and p type dopant with a first and last doped regions with n+ type dopant wherein one of two doped regions connected to the emitter metal  811  and another connected to gate metal  814  by trenched ESD contacts  815 . Specially, underneath each of the trenched ESD contact, a trenched gate  816  is formed as a buffer layer to avoid the ESD diode shortage issue to the base or body regions disposed underneath the ESD gate protection diode in case the trenched ESD contact is overetched through the n+ doped regions. 
         [0048]    Please refer to  FIG. 8B  for cross-sectional view of the eighth preferred embodiment of the present invention with an additional ESD gate protection diode comparing to  FIG. 7B . The ESD gate protection diode comprises an array of doped regions alternatively doped with n+ type dopant and p type dopant with a first and last doped regions with n+ type dopant wherein one of two doped regions connected to the emitter metal  911  and another connected to gate metal  914  by trenched ESD contacts  915 . Specially, underneath each of the trenched ESD contact, a fourth-type trenched gate  916  is formed as a buffer layer to avoid the ESD diode shortage issue. 
         [0049]    Although the present invention has been described in terms of the presently preferred embodiments, it is to be understood that such disclosure is not to be interpreted as limiting. Various alternations and modifications will no doubt become apparent to those skilled in the art after reading the above disclosure. Accordingly, it is intended that the appended claims be interpreted as covering all alternations and modifications as fall within the true spirit and scope of the invention.