Abstract:
A semiconductor package and method for producing the same has a substrate. A prepackaged semiconductor device is coupled to the substrate. At least one die is coupled to a top surface of the prepackaged semiconductor device. An adhesive layer is laid between the prepackaged semiconductor device and the first die to coupled the two together. A mold compound is then used to encapsulate the semiconductor package.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application is a division of U.S. patent application Ser. No. 10/000,923, filed on Nov. 2, 2001, now abandoned. 
    
    
     FIELD OF THE INVENTION 
     This invention relates to semiconductor devices and, more specifically, to a semiconductor package which has one or more die stacked on a pre-packaged device and a method therefor. 
     BACKGROUND OF THE INVENTION 
     As electronic devices get smaller, the components within these devices must get smaller as well. Because of this, there has been an increased demand for the miniaturization of components and greater packaging density. Integrated Circuit (IC) package density is primarily limited by the area available for die mounting and the height of the package. One way of increasing the density is to stack multiple die vertically in an IC package. Currently, die stacking with flash memory, Static Random Access Memory (SRAM), logic and/or Application Specific Integrated Circuit (ASIC) devices have been introduced for increasing the density of chip integration. 
     In order to provide high quality multi-chip stacked devices, the devices used for stacking must be either high yield FAB (i.e., memory devices) or known good die (KGD). Certain devices, like ASIC and logic devices, have a lower yield than devices like memory. Thus, these types of devices need to be screened if they are to be used in a multi-chip stacked device. A problem arises in that it is expensive to get a KGD prepared. Wafer component testing and burn-in testing is a very expensive process. However, testing of these types of devices is necessary in order to sort out potentially problematic chips and to prevent any quality and reliability issues. 
     Presently, if a logic or ASIC device in an assembled stacked die package is rejected after testing, the good semiconductor die coupled to these rejected logic or ASIC devices must be scraped. This is problematic for many end customers due to the cost of scraping the good die. 
     Therefore, a need existed to provide a device and method to overcome the above problems. 
     SUMMARY OF THE INVENTION 
     A semiconductor package and method for producing the same has a substrate. A prepackaged semiconductor device is coupled to the substrate. At least one semiconductor die is coupled to the prepackaged semiconductor device. An adhesive layer is laid between the prepackaged semiconductor device and the first semiconductor die to couple the two together. A mold compound is then used to encapsulate the semiconductor package. 
     The present invention is best understood by reference to the following detailed description when read in conjunction with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a cross-sectional side view of one embodiment of the present invention showing a semiconductor package with a single die stacked on a pre-packaged device. 
         FIG. 2  is a cross-sectional side view of another embodiment of the present invention showing a semiconductor package with multiple die stacked on a prepackaged device. 
         FIG. 3  is a cross-sectional side view of another embodiment of the present invention showing a semiconductor package with different size die stacked on a prepackaged device. 
         FIG. 4  is a cross-sectional side view of another embodiment of the present invention showing a semiconductor package with different size die stacked horizontally on a prepackaged device. 
         FIG. 5  is a cross-sectional side view of another embodiment of the present invention showing a semiconductor package with die stacked on a leadframe prepackaged device. 
         FIG. 6  is a cross-sectional side view of another embodiment of the present invention showing a semiconductor leadframe package with die stacked on a prepackaged leadframe device. 
     
    
    
     Common reference numerals are used throughout the drawings and detailed description to indicate like elements. 
     DETAILED DESCRIPTION 
     Referring to  FIG. 1 , one embodiment of a semiconductor package  10  of the present invention is shown. The semiconductor package  10  will allow one or more die to be stacked on a known good die to ensure good electrical functionality of the semiconductor package  10 . 
     The semiconductor package  10  has a prepackaged device  12 . The prepackaged device  12  is a fully encapsulated package which has a semiconductor die  14 . The semiconductor die  14  may be any type of device. For example, the semiconductor die  14  may be a memory device, a logic device, an ASIC device, and other like elements. It should be noted that the listing of types for the above semiconductor die  14  is given as an example and should not be seen as to limit the scope of the present invention. While any type of semiconductor die  14  may be used, the semiconductor die  14  is generally a type of device which has a lower manufacturing yield and which would require testing of some kind in order to sort out potentially problematic devices and to prevent any quality and reliability issues. 
     The semiconductor die  14  is coupled to an upper surface  16   a  of a substrate  16 . An adhesive layer  18  is used to couple the semiconductor die  14  to the substrate  16 . One or more wirebonds  20  are used to electrically connect the semiconductor device  14  to the upper surface  16   a  of substrate  16 . A mold compound  22  is then used to encapsulate the prepackaged device  12 . As shown in  FIG. 1 , the mold compound  32  covers the upper surface  16   a  of substrate  16 , the semiconductor die  14 , the adhesive  18 , and the wirebonds  20 . 
     In the embodiment depicted in  FIG. 1 , the prepackaged device  12  is a Ball Grid Array (BGA) type of package. However, this should not be seen as to limit the scope of the present invention. A leadframe type of prepackaged device  12  may be used. This embodiment will be described later. 
     The prepackaged device  12  is coupled to an upper surface  24   a  of a substrate  24 . In the embodiment depicted in  FIG. 1 , a plurality of solder balls  23  are used to couple the prepackaged device  12  to the substrate  24 . However, as stated above, the prepackaged device  12  may also be a leadframe type of device. The substrate  24  may be a tape, a laminate substrate, or the like. In the embodiment depicted in  FIG. 1 , a plurality of solder balls  25  are coupled to a lower, unencapsulated surface  24   b  of the substrate  24 . The solder balls  25  will provide an electrical connection to the semiconductor package  10 . However, it should be noted that other types of connections may be used. These other types of connections will be described later in another embodiment. 
     A semiconductor die  26  is coupled to a top section of the prepackaged device  12 , in particular, to an uppermost surface  22   a  of the mold compound  22 . The semiconductor die  26  may be any type of device. However, a memory device or a passive chip component is generally used. The semiconductor die  26  may be coupled to the prepackaged device  12  in a plurality of different ways. In general, some type of adhesive  28  is used. The adhesive  28  is placed on the surface  22   a  of the mold compound  22  of the prepackaged device  12 . The semiconductor die  26  is then placed on top of the adhesive  28 . The adhesive  28  may be an epoxy adhesive which can be either electrically or non-electrically conductive. The adhesive  28  may be an adhesive tape, a paste, or the like. A spacer and an adhesive  28  may also be used. The spacer will provide additional clearance between the prepackaged device  12  and the semiconductor die  26 . The spacer is generally a silicon spacer. 
     Once the semiconductor die  26  is coupled to the prepackaged device  12 , the semiconductor die  26  is further electrically coupled to the substrate  24 . In the embodiment depicted in  FIG. 1 , the semiconductor die  26  is electrically coupled to the substrate  24  by wirebonding. One or more wirebonds  30  are used to electrically couple the semiconductor die  26  to the substrate  24 . Once the wirebonds  30  are complete, a mold compound  32  is used to encapsulate the entire package  10 . As shown in  FIG. 1 , the mold compound  32  covers the exterior surfaces of the prepackaged device  12 , including the upper surface  22   a  and exterior side surfaces  22   b  of mold compound  22 , the lower surface  16   b  of substrate  16 , and the solder balls  23 , as well as the upper surface  24   a  of substrate  24 , the semiconductor die  26 , adhesive  28 , and wirebonds  30 . 
     Referring now to  FIG. 2 , another embodiment of the semiconductor package  10  of the present invention is shown. The semiconductor package  10  of  FIG. 2  is similar to that shown in  FIG. 1 . The semiconductor package  10  has a prepackaged device  12 . The prepackaged device  12  is a fully encapsulated package which has a semiconductor die  14 . The semiconductor die  14  may be any type of device. The semiconductor die  14  is coupled to an upper surface  16   a  of a substrate  16 . An adhesive layer  18  is used to couple the semiconductor die  14  to the substrate  16 . One or more wirebonds  20  are used to electrically connect the semiconductor die  14  to the upper surface  16   a  of the substrate  16 . A mold compound  22  is then used to encapsulate the prepackaged device  12 . 
     The prepackaged device  12  is coupled to the upper surface  24   a  of a substrate  24 . The substrate  24  may be a tape, a laminate substrate, or the like. In the embodiment depicted in  FIG. 2 , the prepackaged device  12  is a Ball Grid Array (BGA) type of package. A plurality of solder balls  23  are used to couple the prepackaged device  12  to the upper surface  24   a  of the substrate  24 . However, this should not be seen as to limit the scope of the present invention. A leadframe type of prepackaged device  12  may be used. This embodiment will be described later. 
     A semiconductor die  26  is coupled to a top section of the prepackaged device  12 , in particular to the upper surface  22   a  of mold compound  22 . The semiconductor die  26  may be any type of device. However, a memory device or a passive chip component is generally used. The semiconductor die  26  may be coupled to the prepackaged device  12  in a plurality of different ways. In general, some type of adhesive  28  is used. The adhesive  28  is placed on the upper surface  22   a  of the mold compound  22  of the prepackaged device  12 . The semiconductor die  26  is then placed on top of the adhesive  28 . The adhesive  28  may be an epoxy adhesive which can be either electrically or non-electrically conductive. The adhesive  28  may be an adhesive tape, a paste, or the like. A spacer and an adhesive  28  may also be used to provide additional clearance between the prepackaged device  12  and the semiconductor die  26 . The spacer is generally a silicon spacer. 
     Once the semiconductor die  26  is coupled to the prepackaged device  12 , the die  26  is further electrically coupled to the upper surface  24   a  of the substrate  24 . In the embodiment depicted in  FIG. 1 , the semiconductor die  26  is electrically coupled to the substrate  24  by wirebonding. One or more wirebonds  30  are used to electrically couple the semiconductor die  26  to the substrate  24 . 
     A second semiconductor die  34  is coupled to a top surface of the first semiconductor die  26 . The second semiconductor die  34  may be any type of device. However, a memory device or a passive chip component is generally used. In the embodiment depicted in  FIG. 2 , the second semiconductor die  34  is approximately the same size as the first die  26 . The second semiconductor die  34  may be coupled to the first semiconductor die  26  in a plurality of different ways. In general, some type of adhesive  36  is used. The adhesive  36  is placed on the top surface of the first semiconductor die  26 . The second semiconductor die  34  is then placed on top of the adhesive  36 . The adhesive  36  may be an epoxy adhesive which can be either electrically or non-electrically conductive. The adhesive  36  may be an adhesive tape, a paste, or the like. A spacer and an adhesive  36  may also be used to provide additional clearance between the prepackaged device  12  and the semiconductor die  26 . The spacer is generally a silicon spacer. The thickness of the adhesive  36  has to be of a sufficient height so that the wirebonds  30  do not come in contact with the second semiconductor die  34 . 
     Once the second semiconductor die  34  is coupled to the first semiconductor die  26 , the second semiconductor die  34  is further electrically coupled to the upper surface  24   a  of the substrate  24 . In the embodiment depicted in  FIG. 2 , the second semiconductor die  34  is electrically coupled to the substrate  24  by wirebonding. One or more wirebonds  30  are used to electrically couple the second semiconductor die  34  to the substrate  24 . 
     Additional die may be place on top of the second die  34 . The additional die would be attached in the same manner as described above. Again, a sufficient amount of space must be had between dies so that the wirebond  30  of a lower die does not come in contact with a die directly above. Once the wirebonds  30 , of the final stacked die is complete, the entire package  10  is encapsulated using a mold compound  32 . As shown in  FIG. 2 , the mold compound  32  covers the exterior surfaces of the prepackaged device  12 , including the upper surface  22   a  and exterior side surface  22   b  of mold compound  22 , the lower surface  16   b  of substrate  16 , and the solder balls  23 , as well as the upper surface  24   a  of substrate  24 , the semiconductor dies  26  and  34 , adhesive  28 , and wirebonds  30 . 
     Referring now to  FIG. 3 , another embodiment of the semiconductor package  10  of the present invention is shown. The semiconductor package  10  of  FIG. 3  is similar to that shown in  FIG. 2 . The only difference is that the second semiconductor die  34  is a different size from that of the first semiconductor die  24 . 
     Referring now to  FIG. 4 , another embodiment of the semiconductor package  10  of the present invention is shown. The semiconductor package  10  of  FIG. 4  is similar to that shown in  FIGS. 2 and 3 . The main difference is that the second semiconductor die  34  has been replaced with two smaller semiconductor dies  38  and  40 . The two smaller semiconductor dies  38  and  40  are placed next to one another (i.e., horizontally stacked) and are on top of the first semiconductor die  26 . The two semiconductor dies  38  and  40  are coupled to the first semiconductor die  26  in a manner as previously discussed above. Wirebonds  30  are used to coupled the semiconductor dies  38  and  40  to the substrate  24 . Wirebonds are further used to coupled the semiconductor dies  38  and  40  to one another. Once the wirebonds  30  are complete, the entire semiconductor package  10  is encapsulated. 
     Referring now to  FIG. 5 , another embodiment of the semiconductor package  10  of the present invention is shown. In this embodiment, the prepackaged device  12  is a leadframe prepackaged device  12 A. The leadframe prepackaged device  12 A includes a substrate  16  with a plurality of leads  23 A and a die pad  23 B. The semiconductor die  14  is electrically connected to the leads  23 A by wirebonds  20 . The leads  23 A are used to couple the leadframe prepackaged device  12 A to the upper surface  24   a  of the substrate  24 . In any of the previous embodiments, the prepackaged device  12  may be a BGA prepackaged device  12  as shown in the  FIGS. 1–4  or a leadframe prepackaged device  12 A as shown in  FIG. 5 . The mold compound  22  of the prepackaged device  12 A has a lower surface  22   c  that faces upper surface  24   a  of substrate  24 , with mold compound  22  between them. 
     Referring now to  FIG. 6 , another embodiment of the semiconductor package  10  of the present invention is shown. In this embodiment, the semiconductor package  10  is a leadframe type of package. Prepackaged device  12 A includes a substrate  16  that includes leads  23 A and a die pad  23 B. Leads  23 A are electrically connected to semiconductor die  14  by wirebonds  20 . Leads  23 A are electrically connected to upper surface  24   a  of substrate  24  by solder balls  23 . One or more leads  42  are used to provide electrical contact with the semiconductor package  10 . In any of the previous embodiments, the semiconductor package  10  may be a BGA package as shown in the  FIGS. 1–5  or a leadframe package as shown in  FIG. 6 . 
     This disclosure provides exemplary embodiments of the present invention. The scope of the present invention is not limited by these exemplary embodiments. Numerous variations, whether explicitly provided for by the specification or implied by the specification, such as variations in structure, dimension, type of material and manufacturing process may be implemented by one of skill in the art in view of this disclosure.