Abstract:
A method and apparatus that restrict the differential output voltage (VOD) for an LVDS input buffer is provided. Specifically, VOD is prevented from exceeding a predetermined threshold. The input and output common-mode voltage, as well as the input and output differential voltage swing, are maintained during the VOD restriction. The VOD restriction reduces output jitter of the LVDS input buffer and provides a more robust LVDS system as compared to an LVDS system not using a VOD restriction circuit. Clamping circuits are used to restrict the VOD. Each half of the differential output voltage may be clamped to restrict the differential output voltage. The clamping circuits are activated in response to the VOD reaching the predetermined threshold. When a clamping circuit is active, an alternate current path is provided maintaining the level of the signal before clamping.

Description:
FIELD OF THE INVENTION 
     The present invention is related to electronic circuits, and more specifically to voltage restriction circuits for use with LVDS input buffers. 
     BACKGROUND OF THE INVENTION 
     Differential signaling has been in existence for many years. For example, teletypes were some of the first.equipment to use differential signaling to communicate. Electronic devices (i.e. computers) often communicate between ports by means of Low Voltage Differential Signaling (LVDS) driver and receiver pairs. 
     LVDS is a differential signaling technique commonly used in data transmission systems. A low voltage differential signal produced by a line driver typically has peak-to-peak amplitudes in the range from 250 mV to 450 mV. The low voltage swing minimizes power dissipation, while maintaining high transmission speeds. Typical transmission speeds are over 100 Mbps (Mega-bits per second). 
     LVDS input buffers are designed to receive a wide variety of input signals while producing a fairly constant output signal. The input signals received by the LVDS input buffers may vary in frequency, peak-to-peak voltage, as well as common-mode voltage. Some LVDS input buffers, however, generate jitter that may cause problems within the LVDS system. 
     SUMMARY OF THE INVENTION 
     The present invention is directed at restricting the differential output voltage (VOD) for LVDS input buffers. Specifically, VOD is prevented from exceeding a predetermined threshold. The input and output common-mode voltage, as well as the input and output differential voltage swing, are maintained during the VOD restriction. The VOD restriction reduces output jitter of the LVDS input buffer and provides a more robust LVDS system as compared to an LVDS system not using a VOD restriction circuit. 
     According to one aspect of the invention, the VOD of the LVDS input buffer is restricted when a predetermined threshold has been reached. According to one embodiment of the invention, the predetermined threshold is about 650 mV. 
     According to another aspect of the invention, clamping circuits are used to restrict the VOD. Each half of the differential output voltage may be clamped to restrict the differential output voltage to be below or at the predetermined threshold. The clamping circuits are activated in response to the VOD reaching the predetermined threshold. 
     According to yet another aspect of the invention, an alternate signal path is created when a clamping circuit is activated. The alternate current path helps to ensure that the output signals from the VOD restriction circuit are maintained at the previous levels before the clamping circuits activate. 
     According to another aspect of the invention, an apparatus for restricting a differential output voltage of an input buffer is provided. The apparatus includes a first and second current-limiting device for producing the differential output voltage. The apparatus also includes a first and second clamping circuit that restricts the VOD based upon a predetermined threshold. 
     According to a further aspect of the invention, a method for restricting a differential output voltage of an LVDS input buffer is provided. The differential output voltage is restricted to help ensure that the VOD does not exceed a predetermined threshold. The VOD is monitored to determine when the VOD reaches the predetermined threshold. Clamping is activated when the predetermined threshold is reached thereby restricting VOD. An alternate current path is also provided allowing the output signal to be maintained during the clamping. The clamping is deactivated when the measured VOD is less than the predetermined threshold. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a schematic block diagram of an output differential voltage restriction (VOD) restriction circuit for use with LVDS input buffers; 
     FIG. 2 shows a schematic diagram of a VOD restriction circuit for use with LVDS input buffers; and 
     FIG. 3 illustrates a flow chart for a process for restricting the output differential voltage for use with LVDS input buffers, in accordance with aspects of the invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In the following detailed description of exemplary embodiments of the invention, reference is made to the accompanied drawings, which form a part hereof, and which is shown by way of illustration, specific exemplary embodiments of which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized, and other changes may be made, without departing from the spirit or scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims. 
     Throughout the specification and claims, the following terms take the meanings explicitly associated herein, unless the context clearly dictates otherwise. The meaning of “a,” “an,” and “the” includes plural reference, the meaning of “in” includes “in” and “on.” The term “connected” means a direct electrical connection between the items connected, without any intermediate devices. The term “coupled” means either a direct electrical connection between the items connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means either a single component or a multiplicity of components, either active and/or passive, that are coupled together to provide a desired function. The term “signal” means at least one current, voltage, or data signal. 
     Briefly described, the present invention is directed at providing a method and apparatus for restricting the differential output voltage (VOD) of an LVDS input buffer. Clamp circuits are activated to restrict VOD within a predetermined range. The clamp circuits provide an alternate signal path while VOD is clamped, thereby maintaining the signal level. 
     FIG. 1 is a schematic block diagram of an output differential voltage (VOD) restriction circuit for use with LVDS input buffers, in accordance with aspects of the invention. As shown in the figure, VOD restriction circuit  100  includes clamping circuit  102 , clamping circuit  104 , and differential output voltage circuit  106 . 
     Clamping circuit  102  has an input coupled to node N 6  and an output coupled to node N 2 . Clamping circuit  104  has an input coupled to node N 8  and an output coupled to node N 4 . Differential output voltage circuit  106  has an input coupled to node N 6 , an input coupled to node N 8 , an output coupled to node N 2 , and an output coupled to node N 4 . Node N 6  and node N 8  are coupled to signal S 1 . 
     VOD restriction circuit  100  is directed at preventing the differential output voltage produced by differential output voltage circuit  106  from exceeding a predetermined threshold. According to one embodiment of the invention, the predetermined threshold is 650 mV. 
     Differential output voltage circuit  106  produces signals S 3  and S 4  in response to signal S 1 . Clamping circuit  102  and clamping circuit  104  restrict VOD from exceeding a predetermined threshold. Clamping circuit  102  and clamping circuit  104  are both inactive (“off”) when the differential output voltage produced by differential output voltage circuit  106  is less than the predetermined threshold. Signal S 1  does not pass through clamping circuit  102  and clamping circuit  104  during the periods clamping circuit  102  and clamping circuit are  104  are off. While the clamping circuits are off, signal S 1  is routed to differential output voltage circuit  106 . 
     Clamping circuit  102  activates (turns “on”) when the negative half of the differential output voltage becomes lower than the positive half of the differential output voltage by the predetermined threshold. Upon activation of clamping circuit  102 , an alternate signal path is created. While clamping circuit  102  is on, signal S 1  is received by clamping circuit  102  creating an alternate path to node N 2 . Signal S 3 , therefore, remains constant. 
     Clamping circuit  104  activates when the positive half of the differential output voltage becomes lower then the negative half of the differential output voltage by the predetermined threshold. Upon activation of clamping circuit  104 , an alternate signal path is created. While clamping circuit  104  is on, signal S 1  is received by clamping circuit  104  creating an alternate path to node N 4 . Signal S 4 , therefore, remains constant. 
     An alternate current path is provided when either clamping circuit  102  or  104  is active. When clamping circuit  102  is active or when clamping circuit  104  is active, the differential output voltage is restricted. The differential output voltage is thereby prevented from exceeding the predetermined threshold by activation of clamping circuit  102  or clamping circuit  104 . 
     FIG. 2 is a schematic diagram of a voltage restriction circuit (VOD) for an LVDS driver, according to one embodiment of the invention. As shown in the figure, voltage restriction circuit  200  includes resistors R 21 , R 22 , R 23 , and R 24  and transistors M 21 , M 22 , M 23 , and M 24 . 
     Resistor R 21  is coupled between node N 21  and node N 22 . Resistor R 22  is coupled between node N 22  and node N 23 . Resistor R 23  is coupled between node N 21  and node N 24 . Resistor R 24  is coupled between node N 24  and node N 25 . Transistor M 21  has a drain coupled to node N 21 , a gate coupled to node N 21 , and a source coupled to node N 23 . Transistor M 22  has a drain coupled to node N 21 , a gate coupled to node N 21 , and a source coupled to node N 25 . Transistor M 23  has a drain coupled to node N 23 , a gate coupled to bias signal S 23 , and a source coupled to node N 26 . Transistor M 24  has a drain coupled to node N 25 , a gate coupled to bias signal S 24 , and a source coupled to node N 26 . Node N 21  is coupled to a voltage source (VDD). Node N 26  is coupled to VSS. 
     Transistor M 23  and transistor M 24  are configured such that when M 23  is fully on, M 24  is fully off, and vice versa. Differential output voltage VOD is the difference in voltage between node N 22 ,and node N 24 . Differential output voltage VOD may be restricted by clamping the voltage across resistor R 21  and resistor R 23 . 
     Transistors M 21  and M 22  are configured as diodes and act as clamps restricting VOD. Transistor M 21  clamps the voltage across resistor R 21 . Transistor M 22  clamps the voltage across resistor R 23 . Transistors M 21  and M 22  are both disabled (“off”) when differential output voltage VOD remains below a predetermined threshold. 
     Transistor M 21  acts as a pure diode when VOD reaches the V TH  Of transistor M 21 . Therefore, transistor M 21  is enabled when VOD− becomes less than the VOD+ by the predetermined threshold. Resistor circuit R 22  creates a voltage offset between the drain and source of transistor M 21 . The enablement of transistor M 21  prevents the differential output voltage (VOD) from exceeding the predetermined threshold. When transistor M 21  is on an alternative path for the current is created, thereby restricting VOD by preventing the voltage drop across resistor R 21  from increasing. The levels of signals S 21  and S 22  remain constant since the current is merely rerouted. 
     Similarly, transistor M 22  is enabled when VOD+ becomes less than VOD− by the predetermined threshold. Resistor circuit R 24  creates a voltage offset, between the drain and source of transistor M 22 . Transistor M 22  acts as a pure diode when VOD reaches the V TH  of transistor M 22 . The enablement of transistor M 22  prevents the differential output voltage (VOD) from exceeding the predetermined threshold. When transistor M 22  is on, an alternative path for the current is created, thereby restricting VOD by preventing the voltage drop across resistor R 23  from increasing. The levels of signals S 21  and S 22  remain constant since the current is merely rerouted. 
     Resistors R 22  and R 24  create a sufficient voltage drop across transistors M 21  and M 22  to turn the transistors on. According to one embodiment of the invention, the value of resistors R 22  and R 24  is approximately 50  106  . The resistance of resistors R 21  and R 22  is chosen such that transistor M 21  will turn on when VOD− is less than VOD+ by the predetermined threshold. According to one embodiment, the value of R 21  is 200  106  . The resistance of resistors R 23  and R 24  is chosen such that transistor M 22  will turn on when VOD+ is less than VOD− by the predetermined threshold. According to one embodiment, the value of R 23  is 200  106  . 
     The resistance of resistor R 21  is equal to the resistance of resistor R 22 . The resistance of R 23  is equal to the resistance of R 24 . According to one embodiment of the invention, resistors R 21 , R 22 , R 23 , and R 24  are p + −poly resistors. P + −poly resistors are chosen to reduce capacitance. 
     Although transistors M 21  and M 22  are used as the clamping circuits, transistors M 21  and M 22  may each be replaced by a diode. Transistors M 21 , M 22 , M 23 , and M 24  may be n-channel or p-channel devices, NPN transistors, PNP transistors, Bipolar devices, MOS devices, GaAsFET devices, JFET devices, as well as one or more components that are arranged to provide the function of transistors M 21 , M 22 , M 23 , and M 24  in the above described example. N-channel devices are used in one embodiment of the invention as they add less capacitance as compared to P-channel devices. 
     FIG. 3 shows a flow chart for restricting the differential output voltage (VOD) for LVDS input buffers, according to one embodiment of the present invention. After a start block, the logic moves to block  302  where the logic determines a differential output voltage (VOD) from VOD− and VOD+. Transitioning to decision block  304 , the process determines if VOD− is less than VOD+ by a predetermined threshold. According to one embodiment of the invention, the predetermined threshold is 650 mV. 
     When VOD− is less than VOD+ by the predetermined threshold, the process moves to block  306  where a first clamping circuit is activated. The clamping circuit restricts VOD from exceeding the predetermined threshold. Transitioning to block  308 , an alternate signal path is provided when the first clamping circuit is activated. The alternate signal path provides a path for the current to flow such that VOD is restricted. 
     When VOD− is not less than VOD+ the process flows to decision block  310  where the logic determines whether VOD+ is less than VOD− by the predetermined threshold. When VOD+ is not less than VOD− by the predetermined threshold, the logic returns to block  302 . When VOD+ is less than VOD− by the predetermined threshold, the logic steps to block  312  where a second clamping circuit is activated. Transitioning to block  312 , an alternate signal path is provided when the second clamping circuit is activated. The alternate signal path provides a path for the current to flow such that VOD is restricted. The process then moves to decision block  316  where the logic determines if VOD is less than the predetermined threshold. When VOD is less than the predetermined threshold, any clamping circuit activated is turned off. The logical flow then ends. 
     The above specification, examples and data provide a complete description of the manufacture and use of the composition of the invention. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention resides in the claims hereinafter appended.