Abstract:
An internal voltage generation method includes the steps of: setting first to third sections by using a reference voltage; determining to which section an internal voltage level corresponds, among the first to third sections; and generating the internal voltage by controlling a voltage pumping amount according to a section corresponding to the internal voltage level.

Description:
CROSS-REFERENCES TO RELATED APPLICATION 
       [0001]    The present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2011-0105996, filed on Oct. 17, 2011, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    The present invention relates generally to a semiconductor apparatus, and more particularly to an internal voltage generation circuit and method. 
         [0004]    2. Related Art 
         [0005]    A semiconductor apparatus includes a circuit for generating a variety of internal voltages VPP, VBB, and VCORE from an external voltage by a charge pumping method or down converting method, in order to perform a stable operation. The charge pumping method is used for generating a boosting voltage VPP or back bias voltage VBB, and the down converting method is used for generating a core voltage VCORE which is an internal voltage having a lower level than the external voltage. 
         [0006]      FIG. 1A  is a circuit diagram of a known internal voltage generation circuit based on the charge pumping method. 
         [0007]      FIG. 1A  illustrates an example of an internal voltage generation circuit which generates an internal voltage by controlling a plurality of pumps. 
         [0008]    The internal voltage generation circuit includes an internal voltage detection unit  20 , a pumping control signal generation unit  30 , and a pump unit  40 . 
         [0009]    The internal voltage detection unit  20  is configured to activate a detection signal DET when the level of a fed-back internal voltage VINT is lower than the level of a reference voltage VREF which is a target level. The pumping control signal generation unit  30  is configured to generate an oscillating signal OSC at an oscillator  31 , when the detection signal DET is activated. Furthermore, the pumping control signal generation unit  30  delays the oscillating signal OSC by one or more of clock cycle through first to third flip-flops  32 _ 1  to  32 _ 3 , and generates first to third pumping control signals PU_CTRL 1  to PU_CTRL 3 . The first to third pumping control signals PU_CTRL 1  to PU_CTRL 3  are used to control first to third pumps  41  to  43  of the pump unit  40 , respectively. 
         [0010]    In the known internal voltage generation circuit, the plurality of pumps are provided to generate the internal voltage, and the first pump  41  is driven at the initial state. However, when the internal voltage has not reached the target level after amplifying the internal voltage by the first pump  41 , the second pump  42  is driven after a predetermined time passes. Furthermore, when the internal voltage has not reached the target level even after amplifying the internal voltage by the second pump  42 , the third pump  43  is driven. 
         [0011]      FIG. 1B  is a waveform diagram of the known internal voltage generation circuit. 
         [0012]    When the semiconductor apparatus consumes a current, the internal voltage VINT may drop below the reference voltage VREF. At this time, the detection signal DET is activated. At the initial stage of the charge pumping method, only the first pumping control signal PU_CTRL 1  is activated. However, if the internal voltage VINT has not reached the target level, the second pumping control signal PU_CTRL 2  is activated. Then, if the internal voltage VINT has not reached the target level even after amplifying the internal voltage by the first and second pump, the third pumping control signal PU_CTRL 3  is activated. Accordingly, the internal voltage VINT reaches the reference voltage VREF, the detection signal DET is deactivated, and the pumping operation is stopped. 
         [0013]    In the known internal voltage generation circuit which sequentially controls the plurality of pumps to generate the internal voltage, an amount of voltage to be pumped increases at each cycle of the clock signal. Therefore, as shown in  FIG. 1B , the known internal voltage generation circuit may have a wide range of fluctuation of the pumping voltage (corresponding to a range A). This may degrade the voltage characteristic of the internal voltage generation circuit. 
       SUMMARY 
       [0014]    An internal voltage generation circuit and method capable of elaborately generating an internal voltage by controlling a plurality of pumps according to the level of a fed-back internal voltage is described herein. 
         [0015]    In one embodiment of the present invention, an internal voltage generation method includes the steps of: setting first to third sections by using a reference voltage; determining to which section an internal voltage level corresponds, among the first to third sections; and generating the internal voltage by controlling a voltage pumping amount according to the section corresponding to the internal voltage level. 
         [0016]    In another embodiment of the present invention, an internal voltage generation circuit includes: a sub voltage generation unit configured to divide a target level of an internal voltage by a predetermined interval and output first and second sub voltages; a is detection unit configured to compare the internal voltage with the first and second sub voltages and generate first and second detection signals according to the comparison results; a pumping control signal generation unit configured to generate first and second pumping control signals according to whether the first and second detection signals are activated or not; and a pump unit configured to receive the first and second pumping control signals and generate the internal voltage. 
         [0017]    In another embodiment of the present invention, an internal voltage generation circuit includes: a sub voltage generation unit configured to generate a plurality of sub voltages from a reference voltage; a detection unit configured to receive an internal voltage, compare the internal voltage with the plurality of sub voltages, and generate a plurality of detection signals according to the comparison results; a pumping control signal generation unit configured to activate one or more pumping control signals among a plurality of pumping control signals, during a period where one or more of the corresponding detection signals are activated; and a pump unit configured to generate the internal voltage according to the plurality of pumping control signals. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0018]    Features, aspects, and embodiments are described in conjunction with the attached drawings, in which: 
           [0019]      FIG. 1A  is a circuit diagram of a known internal voltage generation circuit based on the charge pumping method; 
           [0020]      FIG. 1B  is a waveform diagram of the known internal voltage generation circuit of  FIG. 1A ; 
           [0021]      FIG. 2  is a circuit diagram of an internal voltage generation circuit according to an embodiment; 
           [0022]      FIG. 3  is a circuit diagram illustrating a detailed configuration of the internal voltage generation circuit of  FIG. 2 ; and 
           [0023]      FIG. 4  is a waveform diagram explaining the operation of the internal voltage generation circuit according to an embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0024]    Hereinafter, an internal voltage generation circuit and method according to the present invention will be described below with reference to the accompanying drawings through exemplary embodiments. 
         [0025]      FIG. 2  is a circuit diagram of an internal voltage generation circuit according to an embodiment of the present invention. 
         [0026]    The internal voltage generation circuit includes a sub voltage generation unit  100 , a detection unit  200 , a pumping control signal generation unit  300 , and a pump unit  400 . 
         [0027]    The sub voltage generation unit  100  is configured to receive a reference voltage VREF, divide the reference voltage VREF, and output the divided voltages as first to third sub voltages VREF 1  to VREF 3 . The reference voltage VREF corresponds to a target level of the internal voltage VINT generated by the internal voltage generation circuit according to an embodiment of the present invention. The reference voltage VREF may be applied from outside through a pad. Alternatively, the reference voltage VREF may be generated and supplied by an internal reference voltage generator. 
         [0028]    The detection unit  200  is configured to receive the internal voltage VINT and compare the internal voltage VINT with the first to third sub voltages VREF 1  to VREF 3 . Therefore, when the internal voltage VINT is lower than the first sub voltage VREF 1 , the detection unit  200  activates a first detection signal DET 1 . Similarly, when the internal voltage VINT is lower than the second sub voltage VREF 2 , the detection unit  200  activates a second detection signal DET 2 , and when the internal voltage VINT is lower than the third sub voltage VREF 3 , the detection unit  200  activates a third detection signal DET 3 . 
         [0029]    The pumping control signal generation unit  300  is configured to receive the first to third detection signals DET 1  to DET 3  and generate first to third pumping control signals PU_CTRL 1  to PU_CTRL 3  corresponding to the first to third detection signals DET 1  to DET 3 , respectively. Further, during a period where each of the first to third detection signals DET 1  to DET 3  is activated, a corresponding pumping control signal among first to third pumping control signals PU_CTRL 1  to PU_CTRL 3  is activated. 
         [0030]    The pump unit  400  includes a plurality of pumps, and is configured to generate the internal voltage VINT according to the first to third pumping control signals PU_CTRL 1  to PU_CTRL 3 . That is, a pump corresponding to an activated signal, among the first to third pumping control signals PU_CTRL 1  to PU_CTRL 3 , is enabled to control a charge pump amount. 
         [0031]    According to an embodiment of the present invention, the number of enabled pumps of the pump unit  400  is controlled according to the level of the internal voltage VINT. Therefore, the generation of the internal voltage VINT may be stably performed. The sub voltage generation unit  100  serves to divide the target level into minute sections, in order to determine the level of the internal voltage VINT. As the reference voltage VREF is divided into the first to third sub voltages VREF 1  to VREF 3 , the target level may be divided into a section from the reference voltage VREF to the first sub voltage VREF 1 , a section from the first sub voltage VREF 1  to the second sub voltage VREF 2 , and a section from the second sub voltage VREF 2  to the third sub voltage VREF 3 . The detection unit  200  serves to determine to which section the internal voltage VINT corresponds among the sections, through the detection signals DET 1  to DET 3 . 
         [0032]    When the level of the internal voltage VINT corresponds to a section having a relatively low level, a plurality of pumps are simultaneously enabled to pump a large amount of charge. When the level of the internal voltage VINT corresponds to a section having a relatively high level, a smaller number of pumps are enabled to pump a relatively small amount of charge. Accordingly, it is possible to stably generate the internal voltage VINT with the target level. 
         [0033]    In an embodiment of the present invention, the sub voltage generation unit  100  generates the first to third sub voltages VREF 1  to VREF 3  to divide the target level into three sections. However, the present invention is not limited thereto, and the number of sections may be controlled to a smaller or larger number. 
         [0034]      FIG. 3  is a circuit diagram illustrating a detailed configuration of the internal voltage generation circuit of  FIG. 2 . 
         [0035]    The sub voltage generation unit  100  includes first and second resistors R 1  and R 2  and a constant current source DC_current_sink. The sub voltage generation unit  100  is configured to divide the level of the reference voltage VREF using the voltage division characteristic of the resistors. The first and second resistors R 1  and R 2  are coupled in series between the reference voltage terminal VREF and the constant current source DC_current_sink. Also, the sub voltage generation unit  100  outputs a voltage of a node between a terminal of the reference voltage VREF and the first resistors R 1  as the first sub voltage VREF 1 , outputs a voltage of a node between the first and second resistors R 1  and R 2  as the second sub voltage VREF 2 , and outputs a voltage of a node between the second resistor R 2  and the constant current source DC_current_sink as the third sub voltage VREF 3 . 
         [0036]    The detection unit  200  includes first to third detectors  210  to  230 . The first detector  210  is configured to compare the internal voltage VINT with the first sub voltage VREF 1  and output the first detection signal DET 1  which is activated when the level of the internal voltage VINT is lower than the level of the first sub voltage VREF 1 . The second detector  220  is configured to compare the internal voltage VINT with the second sub voltage VREF 2  and output the second detection signal DET 2  which is activated when the level of the internal voltage VINT is lower than the level of the second sub voltage VREF 2 . The third detector  230  is configured to compare the internal voltage VINT with the third sub voltage VREF 3  and output the third detection signal DET 3  which is activated when the level of the internal voltage VINT is lower than the level of the third sub voltage VREF 3 . The first to third detectors  210  to  230  may include a comparator, that is, an operational amplifier (OP-AMP). 
         [0037]    The pumping control signal generation unit  300  includes first to third oscillators  310  to  330 . The first oscillator  310  is configured to generate the first pumping control signal PU_CTRL 1  which is activated in a period where the first detection signal DET 1  is activated. The second oscillator  320  is configured to generate the second pumping control signal PU_CTRL 2  which is activated in a period where the second detection signal DET 2  is activated. The third oscillator  330  is configured to generate the third pumping control signal PU_CTRL 3  which is activated in a period where the third detection signal DET 3  is activated. Since the detailed configuration of the first to third oscillators  310  to  330  is obvious to those skilled in the art, the detailed descriptions thereof are omitted herein. 
         [0038]    The pump unit  400  includes first to third pumps  410  to  430 . The first pump  410  is configured to generate the internal voltage by pumping charges when the first pumping control signal PU_CTRL 1  is activated and inputted. The second pump  420  is configured to generate the internal voltage by pumping charges when the second pumping control signal PU_CTRL 2  is activated and inputted. The third pump  430  is configured to generate the internal voltage by pumping charges when the third pumping control signal PU_CTRL 3  is activated and inputted. When a large number of pumping control signals are activated at the same time, a large amount of charge is pumped, and thus the internal voltage is generated at high speed. When a small number of pumping control signals are activated, a small amount of charge is pumped, and thus the internal voltage is generated at low speed. Since the detailed configuration of the first to third pumps  410  to  430  is obvious to those skilled in the art, the detailed descriptions thereof are omitted herein. 
         [0039]      FIG. 4  is a waveform diagram explaining the operation of the internal voltage generation circuit according to an embodiment of the present invention. 
         [0040]    When the semiconductor apparatus is operated to consume a current, the level of an internal voltage may drop. Referring to  FIG. 4 , since the level of the internal voltage VINT drops below the level of the third sub voltage VREF 3 , all of the first to third detection signals DET 1  to DET 3  are activated during a period from the initial time point to a time point X. Therefore, since all of the first to third pumping control signals DET 1  to DET 3  are activated during this period, the internal voltage VINT is generated at high speed. 
         [0041]    Then, when the level of the internal voltage VINT is higher than the third sub voltage VREF 3  but lower than the second sub voltage VREF 2 , that is, during a period from the time point X to a time point Y, only the first and second detection signals DET 1  and DET 2  are activated. Therefore, since only the first and second pumping control signals PU_CTRL 1  and PU_CTRL 2  are activated during this period, the internal voltage is generated at lower speed than when all of the first to third pumping control signals PU_CTRL 1  to PU_CTRL 3  are activated. 
         [0042]    Then, when the level of the internal voltage VINT is higher than the second sub voltage VREF 2  but lower than the first sub voltage VREF 1 , that is, during a period from the time point Y to a time point Z, only the first detection signal DET 1  is activated. Therefore, since only the first pumping control signal PU_CTRL 1  is activated during this period, the internal voltage VINT is generated at lower speed than when the first and second pumping control signals PU_CTRL 1  and PU_CTRL 2  are activated. 
         [0043]    The internal voltage generation circuit according to an embodiment of the present invention includes the plurality of pumps to control the plurality of pumping operations according to the level of the internal voltage. The internal voltage generation circuit may detect the level of the internal voltage and control the pumping amount, thereby stably generating the internal voltage with a desired target level. 
         [0044]    While certain embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of example only. Accordingly, the internal voltage generation circuit described herein should not be limited based on the described embodiments. Rather, the internal voltage generation circuit described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.