Abstract:
The present invention provides a method of fabricating a semiconductor apparatus including a vertical transistor and a semiconductor apparatus fabricated thereby which protect a pillar-shaped channel region to stabilize an operating characteristic of the semiconductor apparatus. The method of fabricating the semiconductor apparatus according to the present invention comprises: forming a pillar-shaped pattern on a semiconductor substrate; depositing a conductive layer surrounding the pattern; changing a feature of some portion of the conductive layer through an ion implanting process to form an oxide film; and removing the oxide film using an etching selectivity difference.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    The present application claims priority to Korean patent application No. 10-2008-00132463 filed on Dec. 23, 2008, which is incorporated by reference in its entirety. 
       BACKGROUND OF THE INVENTION 
       [0002]    The present invention relates to a method of fabricating a highly integrated semiconductor apparatus, and more particularly, to a fabricating method which can improve integration, operating characteristics and semiconductor chip yield. 
         [0003]    In general, a semiconductor is a material belonging to an intermediate region between a conductor and insulator. Although the semiconductor is similar to the insulator in a pure state, its electrical conductivity can be increased by the addition of impurities or other manipulation. The impurity is added to the semiconductor and a conductor is connected thereto to generate a semiconductor device such as a transistor. An apparatus with various functions fabricated using the semiconductor device is a semiconductor apparatus. A representative example of the semiconductor apparatus is a semiconductor memory apparatus. 
         [0004]    The semiconductor memory apparatus includes a plurality of unit cells, each of which is composed of a capacitor and a transistor. The capacitor is used to store data. The transistor is used to transfer data between a bit line and the capacitor, corresponding to a control signal (word line). The transistor is composed of three regions, i.e. a gate, source and drain. A control signal input to the gate causes electric charges to move between the source and the drain. The movement of the electric charges occurs through a channel region. This channel uses the properties of the semiconductor to conduct a current. 
         [0005]    In a case where a general transistor is formed on a semiconductor substrate, a gate is formed on the semiconductor substrate, and an impurity is doped into both sides of the gate to form a source and a drain. In this case, a space between the source and the drain below the gate becomes a channel region of the transistor. The transistor having this horizontal channel region occupies a certain area of semiconductor substrate. In the case of a complicated semiconductor memory apparatus, it is difficult to reduce the overall area due to a plurality of transistors included therein. 
         [0006]    If the total area of the semiconductor memory apparatus is reduced, the number of the semiconductor memory apparatuses that can be produced per wafer can be increased, which leads to higher productivity. A variety of methods have been suggested to reduce the entire area of the semiconductor memory apparatus. One of the methods is to use a vertical transistor having a vertical channel region, instead of using the conventional horizontal transistor having the horizontal channel region. 
       BRIEF SUMMARY OF THE INVENTION 
       [0007]    Various embodiments of the invention are directed to providing a method of fabricating a semiconductor apparatus including a vertical transistor and a semiconductor apparatus fabricated thereby which protect a pillar-shaped channel region by changing film quality of a conductive layer through an ion implanting process in forming a gate and selectively removing the same through wet etch, to thereby stabilize an operating characteristic of the semiconductor apparatus. 
         [0008]    According to an embodiment of the present invention, a method of fabricating a semiconductor apparatus comprises: forming a pillar-shaped pattern on a semiconductor substrate; depositing a conductive layer surrounding the pattern; changing a feature of some portion of the conductive layer through an ion implanting process to form an oxide film; and removing the oxide film using an etching selectivity difference. 
         [0009]    Preferably, the method of fabricating the semiconductor apparatus further comprises implanting an impurity into the semiconductor substrate exposed between the patterns to form a bit line, after removing the oxide film. 
         [0010]    Preferably, the method of fabricating the semiconductor apparatus further comprises depositing an oxide film on the pattern and the conductive layer, prior to forming the bit line. 
         [0011]    Preferably, forming the pillar-shaped pattern on the semiconductor substrate comprises: depositing a pad oxide film on the semiconductor substrate; depositing a hard mask film on the pad oxide film; pattering the hard mask film through an exposure process; and etching the pad oxide film and some portion of the semiconductor substrate, using the patterned hard mask film. 
         [0012]    Preferably, a gate oxide film is formed between the pattern and the conductive layer. 
         [0013]    Preferably, the ion implanting process comprises: a first ion implanting process for implanting oxygen ions vertically; and a second ion implanting process for implanting the oxygen ions, rotating with a certain gradient. 
         [0014]    Preferably, a length of a gate is determined by the certain gradient of the second ion implanting process. 
         [0015]    Preferably, removing the oxide film is implemented by wet etch. 
         [0016]    According to another embodiment of the present invention, a method of fabricating a semiconductor memory apparatus comprises: determining a length of a gate surrounding a channel region of a vertical transistor; and implanting an impurity into a semiconductor substrate to form a bit line, after determining the length of the gate. 
         [0017]    Preferably, determining the length of the gate comprises: depositing a conductive layer surrounding the channel region; changing a feature of some portion of the conductive layer through an ion implanting process to form an oxide film; and removing the oxide film using an etching selectivity difference. 
         [0018]    Preferably, the conductive layer is TiN and the oxide film is TiON. 
         [0019]    Preferably, the channel region is a pattern formed in a pillar shape by etching some portion of the semiconductor substrate. 
         [0020]    Preferably, the ion implanting process comprises: a first ion implanting process for implanting oxygen ions vertically; and a second ion implanting process for implanting the oxygen ions, rotating with a certain gradient. 
         [0021]    Preferably, removing the oxide film is implemented by wet etch. 
         [0022]    Preferably, the method of fabricating the semiconductor memory apparatus further comprises depositing an oxide film on the channel region and the gate, prior to forming the bit line. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0023]      FIGS. 1   a  to  1   f  are sectional diagrams for explaining a method of fabricating a semiconductor apparatus including a vertical transistor according to an embodiment of the present invention. 
           [0024]      FIGS. 2   a  to  2   g  are sectional diagrams for explaining a method of fabricating a semiconductor apparatus including a vertical transistor according to another embodiment of the present invention. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0025]    Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. 
         [0026]      FIGS. 1   a  to  1   f  are sectional diagrams for explaining a method of fabricating a semiconductor apparatus including a vertical transistor according to an embodiment of the present invention. Particularly, a case where the vertical transistor is used as a cell transistor included in each unit cell in a semiconductor memory apparatus will be explained as an example. 
         [0027]    Referring to  FIG. 1   a,  so as to form the vertical transistor, a pad oxide film  104  is formed on a semiconductor substrate  102  and a hard mask nitride film  106  is deposited on the pad oxide film  104 . Next, the hard mask nitride film  106  is patterned through an exposure process using a mask defining a channel region of the vertical transistor. In addition, the pad oxide film  104  and the semiconductor substrate  102  are etched using the patterned hard mask nitride film  106 , to thereby form a pillar-shaped channel region. 
         [0028]    Referring to  FIG. 1   b,  a gate oxide film  108  and a conductive layer  110 , which is a gate electrode material, are sequentially deposited on the entire surface of the structure on the semiconductor substrate  102 . For example, the conductive layer  110  may be TiN. 
         [0029]    Referring to  FIG. 1   c,  the horizontal sections of the conductive layer  110  deposited on the hard mask nitride film  106  and between the pillar-shaped channel regions on the semiconductor substrate  102  is removed through an etch-back process or the like. It is similar to a process for forming a spacer on a sidewall of a gate pattern included in a general semiconductor memory apparatus. Thereafter, an impurity is implanted into the semiconductor substrate  102  exposed between the pillar-shaped channel regions through an ion implanting process, to thereby form a buried bit line  112 . 
         [0030]    As illustrated in  FIG. 1   d,  an insulating material is deposited sufficiently high to cover the structure formed on the semiconductor substrate  102 , and planarized through a Chemical Mechanical Polishing (CMP) process to an appropriate height, thereby forming an interlayer insulating film  114 . 
         [0031]    Referring to  FIG. 1   e,  an upper portion of the interlayer insulating film  114  is removed through an etch-back process using a dry etch process to expose some portion of the conductive layer  110 . Here, the etch is performed such that the surface of the interlayer insulating film  114  is lower than the height of the pad oxide film  104  and some portion of the conductive layer  110  surrounding the pillar-shaped channel region is exposed. At this time, a final gate length of the vertical transistor is determined according to a depth of the interlayer insulating film  114  removed. 
         [0032]    Referring to  FIG. 1   f,  the conductive layer  110  exposed by the etch-back process is removed, and then the remaining interlayer insulating film  114  is removed. The remaining conductive layer  110  which has not been etched due to the interlayer insulating film  114  is used as the gate of the vertical transistor. 
         [0033]    Hereinafter, problems that may occur in fabricating the vertical transistor according to the foregoing embodiment will be explained. 
         [0034]    During the etch-back process for etching the upper portion of the interlayer insulating film  114  as explained with reference to  FIG. 1   e,  not only the interlayer insulating film  114  is removed but also the hard mask nitride film  106  formed on the pillar-shaped channel region is damaged. Particularly, since the etch-back process for etching the upper portion of the interlayer insulating film  114  as explained with reference to  FIG. 1   e  is implemented by dry etch, the damage of the hard mask nitride film  106  may be maximized. 
         [0035]    Beforehand, in the etch-back process for forming the buried bit line  112  as explained with reference to  FIG. 1   c,  some portion of the hard mask nitride film  106  serving as an etch barrier film has already been damaged. 
         [0036]    Moreover, although not illustrated, the hard mask nitride film  106  should function as the etch barrier film in a succeeding process for forming a word line. However, if a large volume of hard mask nitride film  106  has already been damaged after the etch-back process of  FIG. 1   e,  before forming the word line, the pillar-shaped channel region may be damaged in the succeeding process for forming the word line. If any portion of the pillar-shaped channel region is damaged, a problem occurs at a location between one side of a source and a drain of the vertical transistor, which increases a leakage current. 
         [0037]    In order to solve the foregoing problem, the hard mask nitride film  106  may be deposited and patterned sufficiently thick to compensate for a portion damaged in the succeeding processes. However, if the thickness of the hard mask nitride film  106  is large, when the pillar-shaped channel region and the hard mask nitride film  106  are combined, the pattern may collapse due to a high aspect ratio. Therefore, there is a limitation in increasing the thickness of the hard mask nitride film  106 . 
         [0038]    As another method for solving the problem, the etch-back process for etching the upper portion of the interlayer insulating film  114  as explained with reference to  FIG. 1   e  can be done by wet etch so as to reduce damage of the hard mask nitride film  106 . However, when the etch-back process is implemented by the wet etch, since it is difficult to control a consistent etch depth of the interlayer insulating film  114 , the exposed area of the conductive layer  110  surrounding each pillar-shaped channel region may be different. In this case, since the plurality of transistors will have a different gate length, this method is not preferable for forming the vertical transistor as a plurality of cell transistors requires a uniform operating characteristic. 
         [0039]    The present invention forms the gate through the ion implanting process and the wet etch instead of the dry etch so as to solve the problems occurring in the process for forming the pillar-shaped vertical transistor to fabricate the high integrated semiconductor apparatus. Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. 
         [0040]      FIGS. 2   a  to  2   g  are sectional diagrams for explaining a method of fabricating a semiconductor apparatus including a vertical transistor according to another embodiment of the present invention. 
         [0041]    Referring to  FIG. 2   a,  so as to form the vertical transistor, a pad oxide film  204  is formed on a semiconductor substrate  202  formed of silicon, and a hard mask film  206 , e.g., a nitride film, is deposited on the pad oxide film  204 . Next, the hard mask film  206  is patterned through an exposure process using a mask defining a channel region of the vertical transistor. In addition, the pad oxide film  204  and the semiconductor substrate  202  are etched using the patterned hard mask film  206 , to thereby form a pillar-shaped channel region. 
         [0042]    Referring to  FIG. 2   b,  a gate oxide film  208  and a conductive layer  210 , which is a gate electrode material, are sequentially deposited on the entire surface of the structure on the semiconductor substrate  202 . For example, the conductive layer  210  may be TiN. 
         [0043]    Referring to  FIG. 2   c,  a feature of some portion of the conductive layer  210  is changed through an ion implanting process. Here, the ion implanting process includes a first ion implanting process for implanting oxygen ions vertically, and a second ion implanting process for implanting the oxygen ions, at different angles. The first ion implanting process serves to remove the conductive layer  210  deposited between the pillar-shaped channel regions to separate gates connected between the neighboring channel regions, and to form a bit line below the channel region. The second ion implanting process serves to determine a length of the gate surrounding each channel region. 
         [0044]    Referring to  FIG. 2   d,  portions of the conductive layer  210  is changed into a first oxide film  211   a  and a second oxide film  211   b  due to the ion implanting process. If the conductive layer  210  is formed of TiN, the oxide films  211   a  and  211   b  become TiON. The aforementioned ion implanting process not only implants the oxygen ions vertically but also implants the oxygen ions at different angles. Therefore, a first portion of the conductive layer  210  deposited between the pillar-shaped channel regions and a second portion over a certain height of the pillar-shaped channel regions are converted to the first and second oxide films  211   a  and  211   b,  respectively. The conductive layer  210  provided between the first and second oxide films remain conductive since they did not receive a significant amount of oxygen ions. 
         [0045]    Particularly, since the ion implanting process implants the oxygen ions, rotating at 90° with a certain gradient, it is possible to evenly implant the ions into the conductive layer  210  surrounding the pillar-shaped channel region. Accordingly, as compared with the prior art controlling the etched degree through the etch-back process, the present invention can uniformly and precisely determine the gate length of the vertical transistor. 
         [0046]    As illustrated in  FIG. 2   e,  the first and second oxide films  211   a  and  211   b  are removed through wet etch, using an etching selectivity difference between the conductive layer  210  and the oxide film  211 . Here, the remaining conductive layer  210  becomes the gate of the vertical transistor. 
         [0047]    Differently from the method associated with  FIGS. 1   a - 1   f,  the present embodiment changes film quality of portions of the conductive layer through the ion implanting process and selectively removes those portions through wet etch. In this case, since it is possible to reduce damage of the hard mask film  206  protecting the pillar-shaped channel region, the pillar-shaped channel region can be prevented from being damaged by an etching process for forming a word line after forming the gate. 
         [0048]    Referring to  FIG. 2   f,  a buffer oxide film  213  is additionally deposited on the pillar-shaped channel region and the conductive layer  210  used as the gate. Here, the buffer oxide film  213  is deposited to undo the damage that may occur in the gate oxide film  208 , when the oxide film  211  is removed by wet etch. In addition, the buffer oxide film  213  can protect the pillar-shaped channel region from a process for implanting an impurity in a succeeding process for forming a bit line. 
         [0049]    Referring to  FIG. 2   g,  an impurity is implanted into the semiconductor substrate  202  exposed between the pillar-shaped channel regions through an ion implanting process, to thereby form a buried bit line  212 . While the prior art forms the buried bit line before completing the gate of the vertical transistor, the present invention implants the impurity to form the bit line  212  after determining the length of the gate. 
         [0050]    As set forth herein, in the first embodiment the channel region is damaged in forming the word line due to the dry etch performed in forming the gate of the conventional vertical transistor. The method of fabricating the semiconductor apparatus according to the present invention forms the gate through the ion implanting process and the wet etch, thereby preventing the channel region from being damaged in the succeeding process. 
         [0051]    Accordingly, it is not necessary to deposit the hard mask film  206  thick to protect the pillar-shaped channel region, and it is possible to prevent the pillar-shaped pattern from falling due to a high aspect ratio. Moreover, according to the present invention, the size of the gate of the vertical transistor is determined adjusting the gradient angle of implanting the ions in the ion implanting process. Therefore, when cell transistors are formed using the plurality of vertical transistors, the respective vertical transistors can have a uniform operating characteristic. 
         [0052]    The above embodiments of the present invention are illustrative and not limitative. Various alternatives and equivalents are possible. The invention is not limited by the embodiments described herein. Nor is the invention limited to any specific type of semiconductor device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.