Abstract:
A printed wiring board includes a resin insulating layer, a projecting conductor layer formed on a surface of the resin insulating layer such that the projecting conductor layer is projecting from the surface of the resin insulating layer, and an integral conductor structure formed in the resin insulating layer and including a via conductor portion and an embedded conductor layer portion such that the embedded conductor layer portion is embedded in the resin insulating layer on the opposite side of the resin insulating layer with respect to the projecting conductor layer and has an exposed surface exposed from the resin insulating layer and the via conductor portion is formed through the resin insulating layer and is connecting the embedded conductor layer portion and projecting conductor layer. The projecting conductor layer and integral conductor structure are formed such that the projecting conductor layer and integral conductor structure are individual conductor structures.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application is based upon and claims the benefit of priority to Japanese Patent Application No. 2016-000565, filed Jan. 5, 2016, the entire contents of which are incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    Field of the Invention 
         [0003]    The present invention relates to a printed wiring board and a method for manufacturing the printed wiring board. 
         [0004]    Description of Background Art 
         [0005]    Japanese Patent Laid-Open Publication No. 2014-27250 describes a coreless substrate and a method for manufacturing the coreless substrate. The entire contents of this publication are incorporated herein by reference. 
       SUMMARY OF THE INVENTION 
       [0006]    According to one aspect of the present invention, a printed wiring board includes a resin insulating layer, a projecting conductor layer formed on a surface of the resin insulating layer such that the projecting conductor layer is projecting from the surface of the resin insulating layer, and an integral conductor structure formed in the resin insulating layer and including a via conductor portion and an embedded conductor layer portion such that the embedded conductor layer portion is embedded in the resin insulating layer on the opposite side of the resin insulating layer with respect to the projecting conductor layer and has an exposed surface exposed from the resin insulating layer and that the via conductor portion is formed through the resin insulating layer and is connecting the embedded conductor layer portion and the projecting conductor layer. The projecting conductor layer and the integral conductor structure are formed such that the projecting conductor layer and the integral conductor structure are individual conductor structures. 
         [0007]    According to another aspect of the present invention, a method for manufacturing a printed wiring board includes forming a plating resist on a surface of an intermediate wiring board such that the plating resist has an opening portion for an integral conductor structure including a via conductor portion and an embedded conductor layer portion, applying plating in the opening portion of the plating resist such that a plating film is formed in the opening portion of the plating resist, forming an etching resist for the via conductor portion of the integral conductor structure on the plating film in the opening portion of the plating resist, reducing a thickness of an exposed portion of the plating film exposed from the etching resist such that the integral conductor structure including the via conductor portion and the embedded conductor layer portion is formed in the opening portion of the plating resist, removing the etching resist from the plating film, removing the plating resist from the intermediate wiring board, forming a resin insulating layer on the surface of the intermediate wiring board such that a surface of the via conductor has an exposed surface exposed from the resin insulating layer, and forming a projecting conductor layer on the resin insulating layer such that the projecting conductor layer connects to the exposed surface of the via conductor portion in the integral conductor structure. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]    A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein: 
           [0009]      FIG. 1A-1C  illustrate cross-sectional views of printed wiring boards according to second and third embodiments of the present invention; 
           [0010]      FIG. 2A-2F  are manufacturing process diagrams of the printed wiring board of the third embodiment; 
           [0011]      FIG. 3A-3C  are manufacturing process diagrams of the printed wiring board of the third embodiment; 
           [0012]      FIG. 4A-4C  are manufacturing process diagrams of the printed wiring board of the third embodiment; 
           [0013]      FIG. 5A-5C  are manufacturing process diagrams of the printed wiring board of the third embodiment; 
           [0014]      FIG. 6A-6C  are cross-sectional views of a printed wiring board according to a first embodiment of the present invention; 
           [0015]      FIG. 6D  is a plan view of a land; and 
           [0016]      FIG. 6E  is a manufacturing process diagram of the first embodiment. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0017]    The embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals designate corresponding or identical elements throughout the various drawings. 
       First Embodiment 
       [0018]      FIG. 6A  illustrates a cross section of a printed wiring board  10  of a first embodiment. The printed wiring board  10  of the first embodiment includes: a second resin insulating layer ( 50 B) that has a third surface (F 3 ) and a fourth surface that is on an opposite side of the third surface (F 3 ); a second conductor layer ( 58 A) that is formed on the third surface (F 3 ) of the second resin insulating layer ( 50 B); a third conductor layer ( 58 B) that is formed on the fourth surface (F 4 ) of the second resin insulating layer ( 50 B); and a second via conductor ( 36 B) that penetrates the second resin insulating layer ( 50 B) and connects the second conductor layer ( 58 A) and the third conductor layer ( 58 B). 
         [0019]    The second resin insulating layer ( 50 B) has a thickness (d 2 ). The thickness (d 2 ) is a distance between the second conductor layer ( 58 A) and the third conductor layer ( 58 B). The thickness (d 2 ) is 1.5 μm or more and 3.5 μm or less. For example, the thickness (d 2 ) is 2.5 μm. 
         [0020]    The second conductor layer ( 58 A) has multiple conductor circuits ( 58 AW). The second conductor layer ( 58 A) has an upper surface ( 58 AU) and a lower surface ( 58 AL) that is on an opposite side of the upper surface ( 58 AU). The second conductor layer ( 58 A) is embedded in the second resin insulating layer such that the lower surface ( 58 AL) is exposed from the third surface (F 3 ). The second conductor layer ( 58 A) has a thickness (t 2 ). The thickness (t 2 ) is 1.5 μm or more and 3.5 μm or less. For example, the thickness (t 2 ) is 2.5 μm. 
         [0021]    The second via conductor ( 36 B) and the second conductor layer ( 58 A) are integrally formed. The second via conductor ( 36 B) is formed on a conductor circuit ( 58 AW) in the second conductor layer ( 58 A). The second via conductor ( 36 B) and the conductor circuit ( 58 AW) in the second conductor layer ( 58 A) are integrally formed. The second via conductor ( 36 B) and the conductor circuit ( 58 AW) are formed from one plating film. Therefore, reliability of connection between the conductor circuit ( 58 AW) and the second via conductor ( 36 B) is high. For example, by thinning an outer periphery of a plating film by etching, the second via conductor ( 36 B) and the conductor circuit ( 58 AW) are formed one plating film. 
         [0022]    In  FIG. 6A , the second via conductor ( 36 B) has a shape of a substantially circular cylinder. Examples of the shape of the second via conductor ( 36 B) are illustrated in  FIGS. 6B and 6C . In  FIGS. 6B and 6C , a side surface of the second via conductor ( 36 B) is curved. In  FIG. 6B , the second via conductor ( 36 B) is gradually increased in diameter from the third conductor layer ( 58 B) toward the second conductor layer ( 58 A). The second via conductor ( 36 B) is increased in diameter from the fourth surface (F 4 ) toward the third surface (F 3 ). In  FIG. 6C , the side surface of the second via conductor ( 36 B) has an inflection point ( 36 BP). The second via conductor ( 36 B) is gradually reduced in diameter from the third conductor layer ( 58 B) toward the inflection point ( 36 BP), and is gradually increased in diameter from the inflection point ( 36 BP) toward the second conductor layer ( 58 A). The second resin insulating layer ( 50 B) is unlikely to be peeled off from the second via conductor ( 36 B). Migration is unlikely to occur. Insulation reliability of the printed wiring board  10  is increased. Even when the printed wiring board  10  warps, the second via conductor ( 36 B) is likely to be able to follow the warping. Reliability of connection via the second via conductor ( 36 B) can be increased. The second resin insulating layer ( 50 B) is formed from resin only. Or, the second resin insulating layer ( 50 B) is formed from resin and inorganic particles only. In this case, strength of the second resin insulating layer ( 50 B) is low. Therefore, when the conductor circuit ( 58 AW) and the second via conductor ( 36 B) are embedded in one resin insulating layer, stress is likely to concentrate on an interface between the conductor circuit ( 58 AW) and the second via conductor ( 36 B). However, in the present embodiment, the second via conductor ( 36 B) and the conductor circuit ( 58 AW) are integrally formed. Therefore, the second via conductor ( 36 B) is unlikely to be peeled off from the conductor circuit ( 58 AW). 
         [0023]    The second via conductor ( 36 B) has a length (t 5 ). The length (t 5 ) is substantially equal to the thickness (d 2 ). 
         [0024]    The third conductor layer ( 58 B) is formed on the fourth surface (F 4 ) of the second resin insulating layer ( 50 B). The third conductor layer ( 58 B) projects from the fourth surface (F 4 ) of the second resin insulating layer ( 50 B). The third conductor layer ( 58 B) and the second via conductor ( 36 B) are individually formed. An interface exists between the third conductor layer ( 58 B) and the second via conductor ( 36 B). The third conductor layer ( 58 B) has multiple conductor circuits ( 58 BW) in the third conductor layer ( 58 B). The conductor circuit ( 58 BW) and the second via conductor ( 36 B) are individually formed. The third conductor layer ( 58 B) has a thickness (t 3 ). The thickness (t 3 ) is 1.5 μm or more and 3.5 μm or less. For example, the thickness (t 3 ) is 2.5 μm. 
       Second Embodiment 
       [0025]      FIG. 1  A illustrates a cross-sectional view of a printed wiring board  10  of a second embodiment. The printed wiring board of the second embodiment is formed by adding to the printed wiring board of the first embodiment a first conductor layer  34 , a first resin insulating layer ( 50 A) on the first conductor layer  34 , and a first via conductor ( 36 A) that penetrates the first resin insulating layer ( 50 A) and connects the first conductor layer  34  and the second conductor layer ( 58 A). 
         [0026]    The first resin insulating layer ( 50 A) has a first surface (F 1 ) and a second surface (F 2 ) that is on an opposite side of the first surface (F 1 ). The second conductor layer ( 58 A) and the second resin insulating layer ( 50 B) are formed on the second surface (F 2 ). The second surface (F 2 ) opposes the third surface (F 3 ). The second surface (F 2 ) and the lower surface ( 58 AL) of the second conductor layer ( 58 A) oppose each other. The first resin insulating layer ( 50 A) is formed below the lower surface ( 58 AL) of the second conductor layer ( 58 A) and the third surface (F 3 ) of the second resin insulating layer ( 50 B). The first resin insulating layer ( 50 A) is formed from resin only. Or, the first resin insulating layer ( 50 A) is formed from resin and inorganic particles only. The first resin insulating layer ( 50 A) has a thickness (d 1 ). The thickness (d 1 ) is a distance between the first conductor layer  34  and the second conductor layer ( 58 A). The thickness (d 1 ) is 1.5 μm or more and 3.5 μm or less. For example, the thickness (d 1 ) is 2.5 μm. 
         [0027]    The first conductor layer  34  has an upper surface ( 34 T), a lower surface ( 34 B) that is on an opposite side of the upper surface ( 34 T), and a side surface ( 34 W). The first conductor layer  34  is embedded in the first resin insulating layer ( 50 A) such that only the lower surface ( 34 B) is exposed from the first surface (F 1 ). A thickness (t 1 ) of the first conductor layer  34  is 1.5 μm or more and 3.5 μm or less. For example, the thickness (t 1 ) is 2.5 μm. 
         [0028]    As illustrated in  FIG. 1A , the first via conductor ( 36 A) is gradually reduced in diameter from the second conductor layer ( 58 A) toward the first conductor layer  34 . When the first via conductor ( 36 A) is gradually reduced in diameter from the second conductor layer ( 58 A) toward the first conductor layer  34  and the second via conductor is gradually reduced in diameter from the second conductor layer ( 58 A) toward the third conductor layer ( 58 B), symmetry of the via conductors ( 36 A,  36 B) that sandwich the second conductor layer ( 58 A) is increased. Warpage of the printed wiring board can be reduced. When the first via conductor ( 36 A) has the shape illustrated in  FIG. 1A  and the second via conductor ( 36 B) has the shape illustrated in  FIG. 6C , stress propagating via the first via conductor ( 36 A) and the second conductor layer ( 58 A) to the second via conductor ( 36 B) is relaxed by the inflection point ( 36 BP). Reliability of connection via the via conductors ( 36 A,  36 B) is increased. 
         [0029]    The first via conductor ( 36 A), the second via conductor ( 36 B), and the conductor circuit ( 58 AW) in the second conductor layer ( 58 A) that is sandwiched by the first via conductor ( 36 A) and the second via conductor ( 36 B), are integrally formed. The first via conductor ( 36 A), the second via conductor ( 36 B) and the conductor circuit ( 58 AW) are simultaneously formed. The first via conductor ( 36 A), the second via conductor ( 36 B) and the conductor circuit ( 58 AW) are formed from the same plating film. Even when the printed wiring board has warpage, peeling is unlikely to occur between the first via conductor ( 36 A) and the conductor circuit ( 58 AW). Peeling is unlikely to occur between the second via conductor ( 36 B) and the conductor circuit ( 58 AW). 
         [0030]    As illustrated in  FIG. 1C , a solder bump ( 76 S) can be formed on a lower surface ( 34 B) of a conductor circuit (pad) ( 34 P) in the first conductor layer  34  of the printed wiring board  10  of the first embodiment or the second embodiment. In  FIG. 1C , the first conductor layer  34  has a wiring ( 34 S) in addition to the pad ( 34 P). Due to the pad ( 34 P), the printed wiring board  10  of the second embodiment can be connected to another circuit substrate or an electronic component. Due to the wiring ( 34 S), a signal or the like is transmitted in the first conductor layer  34 . The first conductor layer  34  of the printed wiring board  10  of  FIG. 1C  has the pad ( 34 P) and the wiring ( 34 S). However, it is also possible that the first conductor layer  34  of the printed wiring board  10  of the second embodiment is formed by the pad ( 34 P) only. 
         [0031]    When the printed wiring board of the first embodiment is connected to another circuit substrate or an electronic component, the conductor circuit ( 58 AW) in the second conductor layer ( 58 A) functions as a pad. In this case, the second conductor layer ( 58 A) can be formed by the pad only. 
         [0032]    As illustrated in  FIG. 1C , it is also possible that the printed wiring board  10  of the second embodiment has a solder resist layer ( 70 F) on the second resin insulating layer ( 50 B) and on the third conductor layer ( 58 B). The solder resist layer ( 70 F) has an opening  72 , and the third conductor layer ( 58 B) exposed by the opening  72  functions as an upper side pad  74 . A solder bump ( 76 F) is formed on the upper side pad  74 . An IC chip is mounted on the printed wiring board  10  via the solder bump ( 76 F). It is also possible that the printed wiring board  10  of the first embodiment has the solder resist layer ( 70 F), the upper side pad  74  and the solder bump ( 76 F) illustrated in  FIG. 1C  on the second resin insulating layer ( 50 B) and the third conductor layer ( 58 B). 
         [0033]      FIG. 1B  illustrates a printed wiring board  10  of a third embodiment. The printed wiring board  10  of the third embodiment has a third resin insulating layer ( 50 C) that is formed on the second resin insulating layer ( 50 B) and the third conductor layer ( 58 B)of the second embodiment, a fourth conductor layer ( 58 C) on the third resin insulating layer ( 50 C). and a third via conductor ( 36 C) that penetrates the third resin insulating layer ( 50 C) and connects the third conductor layer ( 58 B) and the fourth conductor layer ( 58 C). The third resin insulating layer ( 50 C) has a thickness (d 3 ). The thickness (d 3 ) is 1.5 μm or more and 3.5 μm or less. For example, the thickness (d 3 ) is 2.5 μm. Each of the thicknesses (d 1 , d 2 , d 3 ) of the resin insulating layers ( 50 A,  50 B,  50 C) is a distance between the conductor layers sandwiching the resin insulating layer. The fourth conductor layer ( 58 C) has a thickness (t 4 ). The thickness (t 4 ) is 1.5 μm or more and 3.5 μm or less. For example, the thickness (t 4 ) is 2.5 μm. The third via conductor ( 36 C) has a length (t 6 ). The length (t 6 ) is substantially equal to the thickness (d 3 ). 
         [0034]    The third via conductor ( 36 C) has the same shape as the second via conductor ( 36 B). Examples of the shape of the third via conductor ( 36 C) are illustrated in  FIG. 6A-6C . 
         [0035]    The third via conductor ( 36 C) and the third conductor layer ( 58 B) are integrally formed. The third via conductor ( 36 C) and the third conductor layer ( 58 B) are simultaneously formed. The third via conductor ( 36 C) and the third conductor layer ( 58 B) are formed from the same plating film. Even when the printed wiring board has warpage, peeling is unlikely to occur between the third via conductor ( 36 C) and the third conductor layer ( 58 B). 
         [0036]    As illustrated in  FIGS. 6C and 6D , the conductor layer that is simultaneously formed with the via conductor has a land (( 58 ALL)) that is directly connected to the via conductor.  FIG. 6D  illustrates a plan view obtained by observing the via conductor and the land from above the via conductor. An outer periphery of the via conductor ( 36 B) is depicted using a dotted line, and an outer periphery of the land (( 58 ALL)) is depicted using a solid line. A size of the land is larger than a size of the via conductor. The entire outer periphery of the land is exposed from the via conductor. 
         [0037]    As illustrated in  FIG. 1B , the solder resist layer ( 70 F) is formed on the third resin insulating layer ( 50 C) and the fourth conductor layer ( 58 C). The solder resist layer ( 70 F) has the opening  72  that exposes the upper side pad  74 . The solder bump ( 76 F) can be formed on the upper side pad  74 . An electronic component such as an IC chip (not illustrated in the drawings) is mounted on the printed wiring board via the solder bump ( 76 F). The printed wiring board  10  of the first embodiment or the second embodiment may also have the solder resist layer ( 70 F) on the second resin insulating layer ( 50 B). 
       Method for Manufacturing Printed Wiring Board of Third Embodiment 
       [0038]      FIG. 2A-5C  illustrate a method for manufacturing the printed wiring board of the third embodiment. 
         [0039]    A support plate ( 12   z ) is prepared. The support plate ( 12   z ) is formed by a insulating substrate  12  and a copper foil  14  laminated on both sides of the insulating substrate  12 . A copper foil  16  is laminated on the support plate ( 12   z ) ( FIG. 2A ). A plating resist  22  is formed on the copper foil  16 . An electrolytic copper plating film  24  is formed by electrolytic copper plating on the copper foil  16  exposed from the plating resist  22  ( FIG. 2C ). The plating resist is removed. The first conductor layer  34  is formed from the electrolytic copper plating film  24  ( FIG. 2D ). The thickness (t 1 ) of the first conductor layer  34  is, for example, 2.5 μm. The first resin insulating layer ( 50 A) is formed on the first conductor layer  34  and the copper foil  16  ( FIG. 2E ). The first resin insulating layer ( 50 A) has the first surface (F 1 ) and the second surface (F 2 ), the first surface (F 1 ) opposing the support plate. The first conductor layer  34  is embedded in the first resin insulating layer ( 50 A). 
         [0040]    A first opening ( 51 A) for the first via conductor reaching the first conductor layer  34  is formed in the first resin insulating layer ( 50 A) using laser. The first conductor layer  34  is formed on the copper foil  16 . Therefore, heat generated by laser is transmitted from the first conductor layer  34  to the copper foil  16 . Therefore, laser is unlikely to penetrate the first conductor layer  34 . 
         [0041]    An electroless plating film (seed layer) ( 52 A) is formed on the second surface (F 2 ) of the first resin insulating layer ( 50 A) and in the first opening ( 51 A) for the first via conductor. Thereafter, a plating resist ( 53 A) is formed on the electroless plating film ( 52 A). The plating resist has a second opening ( 53 AO 1 ) and a third opening ( 53 AO 2 ). The second opening ( 53 AO 1 ) is formed on the first opening ( 51 A). The second opening ( 53 AO 1 ) and the first opening ( 51 A) are connected to each other. The third opening ( 53 AO 2 ) exposes the seed layer ( 52 A) on the second surface (F 2 ). The third opening ( 53 AO 2 ) is not connected to the first opening ( 51 A). By electrolytic plating, a plating film (electrolytic plating film) ( 54 A) is formed on the electroless plating film ( 52 A) exposed from the plating resist ( 53 A) ( FIG. 2F ). In this case, since the second opening ( 53 AO 1 ) is formed on the first opening ( 51 A), the first opening ( 51 A) for the first via conductor is filled with the plating film ( 54 A). The plating film ( 54 A) is simultaneously formed in the second opening ( 53 AO 1 ) and the first opening ( 51 A). The plating film ( 54 A) is simultaneously formed in the first opening ( 51 A), the second opening ( 53 AO 1 ) and the third opening ( 53 AO 2 ). In this case, the plating film ( 54 A) is formed in the third opening ( 53 AO 2 ). A thickness sum (t 7 ) ( FIG. 2F ) of a thickness of the electroless plating film ( 52 A) and a thickness of the plating film ( 54 A) on the second surface (F 2 ) of the first resin insulating layer ( 50 A) is 5 μm or more. In  FIG. 2F , the sum (t 7 ) is 5 μm. 
         [0042]    An etching resist composition ( 55 α) is applied on the plating resist ( 53 A) and the plating film ( 54 A) ( FIG. 3A ). In order to form the second via conductor ( 36 B) and the second conductor layer ( 58 A) from the plating film ( 54 A), an etching resist ( 55 A) is formed on the plating film ( 54 A) ( FIG. 3B ). The etching resist ( 55 A) is formed from the etching resist composition ( 55 α) using a photographic technology. A position at which the etching resist ( 55 A) is formed is on the second via conductor ( 36 B). By partially thinning the plating film ( 54 A), the second via conductor ( 36 B) and the second conductor layer ( 58 A) are formed. When the second conductor layer ( 58 A) is formed from the plating film ( 54 A), the second conductor layer ( 58 A) is formed by thinning the plating film ( 54 A). Therefore, the etching resist ( 55 A) is not formed on the plating film ( 54 A) for forming the second conductor layer ( 58 A). The plating film  54  that changes to the second conductor layer ( 58 A) is exposed from the etching resist. A size of the etching resist is smaller than a size of the second opening ( 53 AO 1 ) of the plating resist. Therefore, the land is formed. As illustrated in  FIG. 3C , a thickness of the plating film ( 54 A) exposed from the etching resist ( 55 A) is reduced. The thickness (t 2 ) of the electroless plating film ( 52 A) and the electrolytic plating film ( 54 A) is adjusted to 2.5 μm. 
         [0043]    The etching resist  55 A) is removed. Thereafter, the plating resist ( 53 A) is removed. Or, the etching resist ( 55 A) is removed after the plating resist ( 53 A) is removed. Or, the plating resist ( 53 A) and the etching resist ( 55 A) are simultaneously removed. The electroless plating film ( 52 A) exposed from the plating film ( 54 A) is removed. The second conductor layer ( 58 A), the second via conductor ( 36 B) and the first via conductor ( 36 A) are formed ( FIG. 4A ). When the second opening ( 53 AO 1 ) and the first opening ( 51 A) are connected to each other, the first via conductor ( 36 A), the second via conductor ( 36 B) and the land ( 58 ALL) are simultaneously formed. The first via conductor ( 36 A), the second via conductor ( 36 B) and the land ( 58 ALL) are formed from the same plating film ( 54 A). When the third opening ( 53 AO 2 ) and the first opening ( 51 A) are not connected to each other and the third opening ( 53 AO 2 ) is directly formed on the electroless plating film ( 52 A), the second via conductor ( 36 B) and the land ( 58 ALL) are simultaneously formed. The second via conductor ( 36 B) and the land ( 58 ALL) are formed from the same plating film ( 54 A). The first via conductor ( 36 A) and the land ( 58 ALL) may include the seed layer ( 52 A). 
         [0044]    In  FIG. 4A , the thickness (t 2 ) of the second conductor layer ( 58 A) is 2.5 μm, and a length (t 5 ′) of the second via conductor ( 36 B) is longer than 2.5 μm. In the manufacturing method of the present embodiment, the first via conductor ( 36 A) and the second via conductor ( 36 B) are simultaneously formed. Manufacturing time can be shortened and manufacturing cost can be reduced. 
         [0045]    The second resin insulating layer ( 50 B) is formed on the first resin insulating layer ( 50 A) and the second conductor layer ( 58 A) such that the second via conductor ( 36 B) is embedded ( FIG. 4B ). In order to expose a top part (upper side) of the second via conductor ( 36 B), a surface of the second resin insulating layer ( 50 B) is polished ( FIG. 4C ). An electroless plating film ( 52 B) is formed on the surface of the second resin insulating layer ( 50 B) and on the top part of the second via conductor ( 36 B). A plating resist ( 53 B) is formed on the electroless plating film ( 52 B). An electrolytic plating film (plating film) ( 54 B) is formed on the electroless plating film ( 52 B) exposed from the plating resist ( 53 B) ( FIG. 5A ). A thickness of the plating film ( 54 B) exposed from the etching resist is reduced using the same method as that illustrated in  FIG. 3A-3C . The etching resist and the plating resist ( 53 B) are removed. The electroless plating film ( 52 B) exposed from the plating film ( 54 B) is removed. The third conductor layer ( 58 B) and the third via conductor ( 36 C) are formed. The third resin insulating layer ( 50 C) is formed on the second resin insulating layer ( 50 B) and the third conductor layer ( 58 B) using the same method as that illustrated in  FIGS. 4B and 4C  ( FIG. 5B ). The fourth conductor layer ( 58 C) is formed on the third resin insulating layer ( 50 C) using a semi-additive method or the like ( FIG. 5C ). The thickness (t 4 ) of the fourth conductor layer ( 58 C) is 2.5 μm. An intermediate substrate  110  including the first resin insulating layer ( 50 A), the second resin insulating layer ( 50 B) and the third resin insulating layer ( 50 C) is formed ( FIG. 5C ). 
         [0046]    The intermediate substrate  110 , together with the copper foil  16 , is separated from the support plate ( 12   z ). The copper foil  16  is removed from the intermediate substrate  110 , and the printed wiring board  10  of the third embodiment is formed. The solder resist layer ( 70 F) having the opening  72  for exposing the upper side pad  74  is formed on the third resin insulating layer ( 50 C) of the printed wiring board  10  ( FIG. 1B ). The solder bump ( 76 F) can be formed on the upper side pad  74 . The solder bump ( 76 S) can be formed on the pad ( 34 P) in the first conductor layer  34 . 
         [0047]    Forming the third via conductor ( 36 C), the third resin insulating layer ( 50 C) and the fourth conductor layer ( 58 C) cab be removed from the method for manufacturing the printed wiring board of the third embodiment. The printed wiring board  10  of the second embodiment is manufactured. 
         [0048]    In the manufacturing method of the third embodiment, the first conductor layer  34  is formed in  FIG. 2B . Instead, as illustrated in  FIG. 6E , the plating resist ( 53 A) having the second opening ( 53 AO 1 ) and the third opening ( 53 AO 2 ) can be formed on the copper foil  16 . The plating resist ( 53 A) is formed on a surface that is formed by an upper surface of the copper foil  16 . The plating film ( 54 A) for forming the second conductor layer is formed in the openings ( 53 AO 1 ,  53 AO 2 ). Thereafter, the same processes as those illustrated in  FIGS. 3A-3C and 4A-4C  are performed. Thereafter, the third conductor layer ( 58 B) is formed on the second resin insulating layer ( 50 B). As a result, the printed wiring board  10  of the first embodiment is manufactured. In this case, the land does not have a seed layer. 
         [0049]    When the printed wiring board  10  of the embodiments is manufactured, the support plate ( 12   z ) is present. Therefore, when the printed wiring board of the second embodiment or the third embodiment is manufactured, the first opening ( 51 A) for forming the first via conductor ( 36 A) can be formed using laser. Only for a resin insulating layer that is closest to the support plate ( 12   z ), an opening for a via conductor can be formed using laser. It is not essential to form an opening for a via conductor in other resin insulating layers using laser. It is unnecessary to form an opening for a via conductor using laser. For example, the opening for the via conductor ( 36 A) is formed using laser only in the first resin insulating layer ( 50 A). The second resin insulating layer ( 50 B) and the third resin insulating layer ( 50 C) do not have openings for the via conductors ( 36 B,  36 C) that are formed using laser. When an opening for a via conductor is formed using laser, the conductor layer has a predetermined thickness. This is because, when the conductor layer is thin, laser is likely to penetrate the conductor layer. According to the embodiments, a via conductor is formed using a method in which laser is not sued. Therefore, the thickness of the conductor layer can be reduced. Therefore, the thickness of the printed wiring board can be reduced. 
         [0050]    A manufacturing method of Japanese Patent Laid-Open Publication No. 2014-27250 includes: forming a pillar on a carrier substrate; forming an insulating layer on the carrier substrate such that the pillar is embedded; exposing the pillar by polishing the insulating layer; and forming a circuit on the insulating layer, the circuit connecting to the pillar. When a multilayer coreless substrate is manufactured using the technology of Japanese Patent Laid-Open Publication No. 2014-27250, the formation of the pillar, the formation and the polishing of the insulating layer, and the formation of the circuit are likely to be repeated. For example, due to the polishing, stress is likely to accumulate in the coreless substrate. Warpage of the coreless substrate is expected to increase. Reliability of connection between the pillar and the circuit is likely to decrease. 
         [0051]    A printed wiring board according to an embodiment of the present invention includes: a second resin insulating layer that has a third surface and a fourth surface that is on an opposite side of the third surface; a second conductor layer that has an upper surface and a lower surface that is on an opposite side of the upper surface, and is embedded in the second resin insulating layer such that the lower surface is exposed from the third surface; a third conductor layer that is formed on the fourth surface of the second resin insulating layer, and projects from the fourth surface of the second resin insulating layer; and a second via conductor that penetrates the second resin insulating layer and connects the second conductor layer and the third conductor layer. The second conductor layer and the second via conductor are integrally formed. The third conductor layer and the second via conductor are individually formed. 
         [0052]    A method for manufacturing a printed wiring board according to an embodiment of the present invention includes: forming a plating resist on a surface, the plating resist having a second opening for a second via conductor and a third opening for a second conductor layer; forming a plating film in the second opening and the third opening; forming an etching resist on the plating film in the second opening; forming the second via conductor and the second conductor layer by thinning the plating film exposed from the etching resist; removing the etching resist; removing the plating resist; forming a second resin insulating layer on the second conductor layer and on the surface such that an upper surface of the second via conductor is exposed; and forming a third conductor layer on the second resin insulating layer, the third conductor layer connecting to the second via conductor. 
         [0053]    According to an embodiment of the present invention, the second via conductor and the second conductor layer are integrally formed. The first via conductor, the second via conductor, and the second conductor layer that is sandwiched by the first via conductor and the second via conductor, are integrally formed. Therefore, reliability of connection between the second via conductor and the second conductor layer can be increased. Reliability of connection between the first via conductor and the second via conductor can be increased. Since the number of times of polishing can be reduced, stress in the printed wiring board can be reduced. Warpage of the printed wiring board can be reduced. Yield of the printed wiring board can be increased. 
         [0054]    Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.