Abstract:
A data storage device that includes a nonvolatile memory device, a controller suitable for controlling the nonvolatile memory device and for reading and writing data to the nonvolatile memory device, and a power management unit suitable for supplying power to the nonvolatile memory device. The controller may control the power management unit to adjust the power supplied to the nonvolatile memory device.

Description:
CROSS-REFERENCES TO RELATED APPLICATION 
       [0001]    The present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2014-0024070, filed on Feb. 28, 2014, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    Various embodiments relate to a data storage device. 
         [0004]    2. Related Art 
         [0005]    Recently, the paradigm for computer surroundings has changed to ubiquitous computing where computer systems may be used anytime, anywhere. The use of portable electronic devices such as mobile phones, digital cameras, and laptop computers has rapidly increased. In general, such portable electronic devices use a data storage device including a memory device. The data storage device stores data, which is then used in the portable electronic device. 
         [0006]    Since data storage devices using memory devices have no moving parts, the data storage device may have excellent stability and durability. Furthermore, the data storage device may have high access speeds and low power consumption. Data storage devices having such advantages may include a universal serial bus (USB) memory device, a memory card having various interfaces, a universal flash storage UFS device, and a solid-state drive (SSD). 
       SUMMARY 
       [0007]    Various embodiments of the present invention are directed to a data storage device capable of reducing power consumption. 
         [0008]    In an embodiment of the present invention a data storage device may include a nonvolatile memory device; a controller suitable for controlling, storing data, and reading data in the nonvolatile memory device; and a power management unit suitable for supplying power to the nonvolatile memory device. The controller may control the power management unit to adjust the power supplied to the nonvolatile memory device. 
         [0009]    In an embodiment of the present invention, a data storage device may include a nonvolatile memory device, a power management unit suitable for providing driving power to the nonvolatile memory device, and a controller suitable for determining whether data to be processed through the nonvolatile memory device is sequential data or random data, and controlling the power management unit to adjust the power supplied. 
         [0010]    In an embodiment of the present invention, a data storage device may include a nonvolatile memory device, a controller suitable for controlling the nonvolatile memory device, and a power management unit suitable for supplying power to the nonvolatile memory device. The power management unit may adjust the power supplied to the nonvolatile memory device in response to control of the controller. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    Features, aspects, and embodiments are described in conjunction with the attached drawings, in which: 
           [0012]      FIG. 1  is a block diagram illustrating a data storage device according to an embodiment of the present invention; 
           [0013]      FIG. 2  is a flowchart for explaining an operating method of the data storage device according to the embodiment of the present invention; 
           [0014]      FIGS. 3 and 4  are detailed diagrams of a power management unit shown in  FIG. 1 . 
           [0015]      FIG. 5  is a block diagram illustrating a controller according to the embodiment of the present invention; and 
           [0016]      FIG. 6  is a block diagram illustrating a computer system in which the data storage device in accordance with the embodiment of the present invention is mounted. 
       
    
    
     DETAILED DESCRIPTION 
       [0017]    Exemplary embodiments of the present invention will be described below in more detail with reference to the accompanying drawings, The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. 
         [0018]    Throughout the disclosure, reference numerals correspond directly to like numbered parts in the various figures and embodiments of the present invention. The drawings are not necessarily to scale and, in some instances, proportions may have been exaggerated in order to dearly illustrate features of the embodiments. In this specification, specific terms have been used. The terms are used to describe the present invention, and are not used to qualify the sense or limit the scope of the present invention. 
         [0019]    In this specification, ‘and/or’ represents that one or more of components arranged before and after ‘and/or’ is included. Furthermore, ‘connected/coupled’ represents that one component is directly coupled to another component or indirectly coupled through another component. In this specification, a singular form may include a plural form, and vice versa, as long as it is not specifically mentioned. Furthermore, ‘include/comprise’ or ‘including/comprising’ used in the specification represents that one or more components, steps, operations, and elements exists or are added. 
         [0020]    Hereafter, embodiments of the present invention will be described with reference to the drawings. 
         [0021]      FIG. 1  is a block diagram illustrating a data storage device according to an embodiment of the present invention. The data storage device  100  may store data, which is accessed by a host device (not shown), such as a mobile phone, an MP 3  player, a laptop computer, a desktop computer, a game player, a TV, or an in-vehicle infotainment system, The data storage device  100  may be referred to as a memory system. 
         [0022]    The data storage device  100  may be fabricated as any one of various types of storage devices according to an interface protocol coupled to the host device. For example, the data storage device  100  may be implemented with any one of various types of storage devices such as a solid-state drive (SSD), a multi-media card in the form of a MMC, an eMMC, a RS-MMC, a MMC-micro, a secure digital card in the form of an SD, a Mini-SD, or a Micro-SD, a universal storage bus (USB) device, a universal flash storage (UFS) device, a personal computer memory card international association (PCMCIA) card-type storage device, a peripheral component interconnection (PCI) card-type storage device, a PCI express (PCI-E) card-type storage device, a compact flash (CF) card, a smart media card, and a memory stick. 
         [0023]    The data storage device  100  may be fabricated in one of various types of packages. For example, the data storage device  100  may be implemented with packages such as a package on package (POP), a system in package (SIP), a system on chip (SOC), a multi-chip package (MCP), a chip on board (COB), a wafer-level fabricated package (WFP), and a wafer-level stack package (WSP). 
         [0024]    The data storage device  100  may include a controller  110 , a nonvolatile memory device  120 , and a power management unit  130 . Although not shown, the data storage device  100  may further include a volatile memory device capable of buffering or caching data, which is to be transmitted from the host device to the nonvolatile memory device  120  or from the nonvolatile memory device  120  to the host device. 
         [0025]    The controller  110  may control overall operations of the data storage device  100  by driving firmware or software loaded in an internal working memory device (not shown). The controller  110  may decode and drive a code instruction or algorithm such as firmware or software. The controller  110  may be implemented in hardware or a combination of hardware and software. The controller  110  may include a micro control unit (MCU), a central processing unit (CPU) or the like. 
         [0026]    The controller  110  may control the nonvolatile memory device  120 . For example, the controller  110  may control the nonvolatile memory device  120  to perform a read, write, or erase operation. Furthermore, the controller  110  may control an operation mode MD such that the nonvolatile memory device  120  operates in a low speed mode or a high speed mode. 
         [0027]    The controller  110  may include an input/output driver  111 _ 1 . The input/output driver  111 _ 1  may drive control signals to be provided to the nonvolatile memory device  120 . The input/output driver  111 _ 1  may drive data signals to be provided to the nonvolatile memory device  120 . Furthermore, the input/output driver  111 _ 1  may receive data signals or state signals from the nonvolatile memory device  120 . 
         [0028]    The nonvolatile memory device  120  may operate as a storage medium of the data storage device  100 . The nonvolatile memory device  120  may be implemented with any one of various nonvolatile memory devices such as a NAND flash memory device, a NOR flash memory device, a ferroelectric random access memory (FRAM) using a ferroelectric capacitor, a magnetic random access memory using a tunneling magneto-resistive (TMR) layer, a phase change random access memory (PCRAM) using a chalcogenide alloy, and a resistive random access memory (RERAM) using transition metal oxide. The FRAM, MRAM, PCRAM, and RERAM are nonvolatile random access memory devices in which memory cells may be randomly accessed. The nonvolatile memory device  120  may be implemented with a combination of a NAND flash memory device and the above-described nonvolatile random access memory devices. 
         [0029]    The power management unit  130  may supply power to internal function blocks of the data storage device  100 , such as the controller  110  and the nonvolatile memory device  120 . For example, the power management unit  130  may generate controller power PWRC based on source power inputted from an external device, and supply the generated controller power PWRC to the controller  110 . The power management unit  130  may generate memory power PWRM based on source power inputted from an external device, and supply the generated memory power PWRM to the nonvolatile memory device  120 . The power management unit  130  may generate the memory power PWRM to be supplied to the nonvolatile memory device  120 , based on a power control signal PCTRL provided from the controller  110 . 
         [0030]    The controller  110  may determine the properties of a work, which is to be processed by the controller  110 , based on the attributes of an operation requested from the host device or the attributes of data requested from the host device. The controller  110  may dynamically vary power PWRM supplied to the nonvolatile memory device  120 , based on the properties of the work to be processed. When the power PWRM supplied to the nonvolatile memory device  120  is dynamically varied, unnecessary power consumption may be reduced. Thus, the power consumption of the data storage device  100  may be reduced. 
         [0031]    The controller  110  may provide the power control signal PCTRL to the power management unit  130  based on the properties of the work to be processed. The controller  110  may control the operation mode MD of the nonvolatile memory device  120  based on the properties of the work to be processed. That is, the controller  110  may set the operation mode MD of the nonvolatile memory device  120  such that the nonvolatile memory device  120  operates in an operation mode corresponding to the memory power PWRM supplied to the nonvolatile memory device  120 . Furthermore, the controller  110  may set a driving voltage level of the input/output driver  111 _ 1  corresponding to the set operation mode of the nonvolatile memory device  120 . 
         [0032]    The controller  110  may determine whether data to be processed through the nonvolatile memory device  120 , that is, data to be written to the nonvolatile memory device  120  or data to be read from the nonvolatile memory device  120 , is sequential data or random data. The controller  110  may control the power management unit  130  to adjust the power, for example, having different voltage levels, to the nonvolatile memory device  120  depending on the determination of whether the data to be processed is sequential or random data (the determination result). 
         [0033]      FIG. 2  is a flowchart for explaining an operating method of the data storage device according to the embodiment of the present invention. Referring to  FIGS. 1 and 2 , the operation of the data storage device will be described in detail. 
         [0034]    At step S 110 , the controller  110  may determine whether an operation related to sequential data is requested from the host device based on the properties of the work to be processed. For example, the controller  110  may receive the attribute information of the requested operation from the host device and determine the properties of the work to be processed based on the attribute information of the requested operation. Further, the controller  110  may determine the attribute information of data requested from the host device based on address mapping information, and determine the properties of the work to be processed according to the determination result. The address mapping information may include address mapping information of the nonvolatile memory device  120  on an address of the host device, which is to be referred to in order to process the data requested from the host device through the nonvolatile memory device  120 , that is, in order to store the data in the nonvolatile memory device  120  or read the data from the nonvolatile memory device  120 . 
         [0035]    When the operation related to sequential data is requested from the host device, the procedure may proceed to step S 120 . 
         [0036]    At step S 120  the controller  110  may supply first power to the nonvolatile memory device  120 . That is, the controller  110  may provide the power control signal PCTRL to the power management unit  130  to supply the first power to the nonvolatile memory device  120 . Furthermore, the power management unit  130  may generate first power based on the power control signal PCTRL, and supply the generated first power as memory power PWRM to the nonvolatile memory device  120 . 
         [0037]    The first power, which is supplied to the nonvolatile memory device  120  when the operation related to sequential data is requested, may have a first voltage level. 
         [0038]    At step S 130 , the controller  110  may set the operation mode MD of the nonvolatile memory device  120  such that the nonvolatile memory device  120  operates in a first operation mode corresponding to the first power. The first operation mode may include a high-speed mode. The first operation mode may include a double data rate (DDR) mode in which data is captured at rising and falling edges of a data strobe signal. When the operation mode is changed according to the control of the controller  110 , the nonvolatile memory device  120  may be reset or operate in the set operation mode until the operation mode is changed to another operation mode. 
         [0039]    At step S 140 , the controller  110  may set the voltage level corresponding to the first operation mode to a driving voltage level of the input/output driver  111 _ 1 . That is, the controller  110  may set the driving voltage level of the input/output driver  111 _ 1  to a second voltage level corresponding to the first operation mode such that the levels of signals transmitted and received between the input/output driver  111 _ 1  and the nonvolatile memory device  120  operating in the first operation mode are matched. 
         [0040]    On the other hand, when the operation related to sequential data is not requested from the host device, that is, when the operation related to random data is requested from the host device, the procedure may proceed to step S 150 . 
         [0041]    At step S 150  the controller  110  may supply second power to the nonvolatile memory device  120 . That is, the controller  110  may provide the power control signal PCTRL to the power management unit  130  to supply the second power to the nonvolatile memory device  120 . The power management unit  130  may generate the second power based on the power control signal PCTRL, and supply the generated second power as memory power PWRM to the nonvolatile memory device  120 . 
         [0042]    The second power, which is supplied to the nonvolatile memory device  120  when an operation related to random data is requested, may have a third voltage level. The third voltage level may be lower than the first voltage level of the first power supplied to the nonvolatile memory device  120  when an operation related to sequential data is requested. 
         [0043]    At step S 160 , the controller  110  may set the operation mode MD of the nonvolatile memory device  120  such that the nonvolatile memory device  120  operates in a second operation mode corresponding to the second power. The second operation mode may include a low-speed mode. The second operation mode may include a single data rate (SDR) mode in which the data strobe signal is not used. When the operation mode is changed according to the control of the controller  110 , the nonvolatile memory device  120  may be reset or operate in the set operation mode until the operation mode is changed to another operation mode. 
         [0044]    At step S 170 , the controller  110  may set a voltage level corresponding to the second operation mode to the driving voltage level of the input/output driver  111 _ 1 . Namely, the controller  110  may set the driving voltage level of the input/output driver  111 _ 1  to a fourth voltage level corresponding to the second operation mode such that the levels of signals transmitted and received between the input/output driver  111 _ 1  and the nonvolatile memory device  120  operating in the second operation mode are matched. 
         [0045]    The fourth voltage level corresponding to the second operation mode may be higher than the second voltage level corresponding to the first operation mode. 
         [0046]    At step S 180  after step S 140  or S 170 , the controller  110  may perform the requested operation, that is, the work to be processed by the controller  170 . 
         [0047]    At step S 190 , the controller  190  may determine whether the data storage device  110  enters a power-off state. When the data storage device  110  does not enter the power-off state, the procedure may proceed to step S 110 . On the other hand, when the data storage device  110  enters the power-off state, the procedure may be ended. That is, the controller  110  may dynamically vary the memory power PWRM supplied to the nonvolatile memory device  120  based on the properties of the work to be processed, and process the requested operation, until the operation of the data storage device  100  is ended. 
         [0048]      FIG. 3  is detailed diagram of the power management unit shown in  FIG. 1 . Referring to  FIG. 3 , the power management unit  130 _A may include a power generation block  131 _A and a register set  133 _A. 
         [0049]    The controller  110  of  FIG. 1  may provide the voltage level of the memory power PWRM, which is to be supplied to the nonvolatile memory device  120 , as the power control signal PCTRL to the power management unit  130 _A. In this case, the register set  133 _A may store the power management signal PCTRL provided from the controller  110 . 
         [0050]    The power generation block  131 _A may generate the memory power PWRM by referring to the voltage level of the memory power PWRM stored in the register set  133 _A, and supply the generated memory power PWRM to the nonvolatile memory device  120 . For example, when the voltage level of the first power PWRM 1  is provided as the power control signal PCTRL, the power generation block  131 _A may generate first power PWRM 1 , and supply the generated first power PWRM 1  to the nonvolatile memory device  120 . For another example, when the voltage level of the second power PWRM 2  is provided as the power control signal PCTRL, the power generation block  131 _A may generate the second power PWRM 2 , and supply the generated second power PWRM 2  to the nonvolatile memory device  120 . 
         [0051]    That is, when the power control signal PCTRL, which directly indicates the voltage level of the memory power PWRM to be supplied to the nonvolatile memory device  120 , is provided from the controller  110 , the power management unit  130 _A may generate the memory power PWRM corresponding to the power control signal PCTRL, and supply the generated memory power PWRM to the nonvolatile memory device  120 . 
         [0052]      FIG. 4  is a detailed diagram of a power management unit shown in  FIG. 1 . Referring to  FIG. 4 , the power management unit  130 _B may include a power generation block  131 _B and a voltage selection block  135 _B. 
         [0053]    The power generation block  131 _B may generate first and second powers PWRM 1  and PWRM 2  as the memory power PRWM. The first and second powers PWRM 1  and PWRM 2  generated through the power generation block  131 _B may be provided to the power selection block  135 _B. 
         [0054]    The power selection block  135 _B may select any one of the first and second powers PWRM 1  and PWRM 2  in response to the power control signal PCTRL provided from the controller  110  of FIG,  1 , and supply the selected power as the memory power PWRM to the nonvolatile memory device  120 . 
         [0055]      FIG. 5  is a block diagram illustrating the controller according to the embodiment of the present invention. Referring to  FIG. 5 , the controller may include a memory interface unit  111 , a host interface unit  112 , an error correction code (ECC) unit  113 , a control unit  114 , and a RAM  115 . 
         [0056]    The memory interface unit  111  may provide a command and address to the nonvolatile memory device of  FIG. 1 . Furthermore, the memory interface unit  111  may exchange data with the nonvolatile memory device  120 . For this operation, the memory interface unit  111  may include an input/output driver  111 _ 1 . 
         [0057]    The host interface unit  112  may interface a host device and the data storage device  100  of  FIG. 1  in response to a protocol of the host device. For example, the host interface unit  112  may communicate with the host device through any one of a USB protocol, a UFS protocol, a multimedia card (MMC) protocol, a parallel advanced technology attachment (PATA) protocol, a serial advanced technology attachment (SATA) protocol, a small computer system interface (SCSI) protocol, a peripheral component interconnection (PCI) protocol, and a PCI-express (PCI-E) protocol. Furthermore, the host interface unit  112  may perform a disk emulation function of supporting the host device to recognize the data storage device  100  as a hard disk drive (HDD). 
         [0058]    The ECC unit  113  may generate a parity bit based on data transmitted to the nonvolatile memory device  120 . The generated parity bit may be stored in a spare area of the nonvolatile memory  120 . The ECC unit  113  may detect errors of data read from the nonvolatile memory device  120 . When the number of detected errors falls within a correction range, the ECC unit  113  may correct the detected errors. 
         [0059]    The control unit  114  may analyze and process a signal inputted from the host device. The control unit  114  may control overall operations of the controller  110  in response to a request of the host device. The control unit  114  may control operations of function blocks of the data storage device  110  according to firmware or software for driving the data storage device  100 . The RAM  115  may be used as a working memory device for driving the firmware or software. 
         [0060]      FIG. 6  is a block diagram illustrating a computer system in which the data storage device in accordance with the embodiment of the present invention is mounted. Referring to  FIG. 6 , the computer system  3000  may include a network adapter  3100 , a CPU  3200 , a data storage device  3300 , a RAM  3400 , a ROM  3500 , and a user interface  3600 , which are electrically coupled to a system bus  3700 . The data storage device  3300  may include the data storage device  120  illustrated in  FIG. 1 . 
         [0061]    The network adapter  3100  may interface the computer system  3000  and external networks. The CPU  3200  may perform overall arithmetic operations for driving an operating system or application programs staying in the RAM  3400 . 
         [0062]    The data storage device  3300  may store overall data required by the computer system  3000 . For example, the operating system for driving the computer system  3000 , application programs, various program modules, program data, and user data may be stored in the data storage device  3300 . 
         [0063]    The RAM  3400  may be used as a working memory device of the computer system  3000 . During booting, the operating system, application programs, and various program modules, which are read from the data storage device  3300 , and program data required for driving the programs may be loaded into the RAM  3400 . 
         [0064]    The ROM  3500  may store a basic input/output system (BIOS), which is enabled before the operating system is driven. 
         [0065]    Through the user interface  3600 , information exchange may be performed between the computer system  3000  and a user. 
         [0066]    Although not shown in the drawing, the computer system  3000  may further include a battery, an application chipset, a camera image processor (CIP) and the like. 
         [0067]    According to the embodiments of the present invention, the power consumption of the data storage device may be reduced. 
         [0068]    While certain embodiments of the present invention have been described above, it will be understood to those skilled in the art that the embodiments of the present invention described are for example only. Accordingly, the data storage device described herein should not be limited based on the described embodiments of the present invention. Rather, the data storage device described herein should be limited only in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.