Abstract:
A voltage comparator for comparing an input voltage with a comparison voltage having a hysteresis characteristic. The comparison voltage is derived by combining a voltage drop developed across a fixed resistor by supplying a constant current therethrough from a constant current source and a reference voltage from a constant voltage source.

Description:
This application is a continuation of application Ser. No. 08/171,854filed Dec. 22, 1993, abandoned, which is a continuation of application Ser. No. 07/938,669, filed on Sep. 1, 1992, abandoned, which is a continuation of application Ser. No. 07/758,429, filed on Sep. 3, 1991, abandoned, which is a continuation of application Ser. No. 07/539,312, filed on Jun. 18, 1990, abandoned, which is a continuation of application Ser. No. 07/406,181, filed on Sep. 13, 1989, abandoned, which is a continuation of application Ser. No. 07/256,197, filed on Oct. 11, 1988, abandoned, which is a continuation of application Ser. No. 07/097,626, filed on Sep. 16, 1987, abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a voltage comparator, and more particularly to an improvement in a circuit having a hysteresis characteristic. 
     2. Related Background Art 
     In a voltage comparator, when an input voltage which is a DC voltage approaches a comparison voltage, an output of the comparator is repeatedly turned on and off and assumes an oscillation state. This is not desirable in a circuit operation. 
     In order to avoid such a phenomenon, the voltage comparator is usually designed to have a hysteresis characteristic as shown in FIG. 1. 
     FIG. 2 shows a prior art voltage comparator numeral 1 denotes a power supply terminal to which a power supply voltage is applied, numeral 2 denotes an input terminal to which an input voltage is applied, numeral 3 denotes an output terminal from which an output voltage is produced, and numeral 4 denotes a voltage source, Q 1 , Q 2 , Q A  and Q 9  denotes NPN transistors, Q 3  and Q 4  denote PNP transistors and R A , R B , R C , R 3 , R 4  and R 5  denote resistors. 
     In the circuit shown in FIG. 2, as the transistor Q A  is turned on from its turn-off state, a comparison voltage changes from ##EQU1## and a difference therebetween serves as a hysteresis voltage. 
     In this circuit, relatively accurate comparison voltage and hysteresis voltage are obtained if the power supply voltage V CC  is stable and constant, but if the power supply voltage varies, those voltages vary. Accordingly, this comparator is not appropriate to an application where accuracy in absolute value is required. 
     FIG. 3 shows another prior art voltage comparator. The like elements to those shown in FIG. 2 are designated by the like numerals and explanation thereof is omitted. 
     Q B  and Q 10  denote PNP transistors, R D , R E  and R 6  denote resistors and V R  denotes a reference voltage. 
     In this circuit, when an input voltage is high, the reference voltage V R  is used as a comparison voltage, and when the input voltage is lower than the reference voltage V R  and the transistor Q B  is turned on, the comparison voltage rises by ##EQU2## Thus, a hysteresis voltage is attained. 
     In this circuit, since the reference voltage V R  is used, the comparison voltage is not affected by the variation of the power supply voltage V CC , but the hysteresis voltage is affected by the power supply voltage V CC  and an output impedance of the reference voltage V R , as a result, the accuracy is not assured. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a voltage comparator in which a comparison voltage and a hysteresis voltage are not affected by a variation of a power supply voltage and which assures high precision. 
     In order to achieve the above object, in accordance with the present invention, the comparison voltage has a hysteresis characteristic determined by a current supplied from a stable constant current source. 
     Namely, in the voltage comparator in which the comparison voltage has a hysteresis characteristic and it is compared with an input voltage, the comparison voltage is produced by combining a voltage drop developed by supplying a constant current from a constant current source to a fixed resistor and a reference voltage from a constant voltage source. 
     In accordance with the present invention, a comparison voltage having a stable hysteresis characteristic is attained and the input voltage is compared with high precision. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a conventional hysteresis characteristic, 
     FIG. 2 shows a conventional voltage comparator, 
     FIG. 3 shows another conventional voltage comparator, 
     FIG. 4 shows one embodiment of the present invention, and 
     FIG. 5 shows a constant current source in the embodiment. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     An embodiment of the present invention is explained in detail with reference to the drawings. 
     FIG. 4 shows a circuit diagram of one embodiment of the present invention. Numeral 1 denotes a power supply terminal, numeral 2 denotes an input terminal, numeral 3 denotes an output terminal and numerals 4 and 4&#39; denote constant current sources. Q 1  and Q 2  denote NPN transistors, Q 3  ˜Q 8  denote PNP transistors, R 1  and R 2  denote resistors, V R  denotes a reference voltage and numeral 5 denotes a reference voltage input terminal to which the reference voltage V R  is applied. 
     The input terminal 2 is connected to a base of the NPN transistor Q 1 . An emitter of the NPN transistor Q 1  is connected to the constant current source 4 and an emitter of the NPN transistor Q 2 . The other terminal of the constant current source 4 is grounded. 
     A collector of the NPN transistor Q 1  is connected to a collector of the PNP transistor Q 3  and bases of the PNP transistors Q 7  and Q 8 . A collector of the NPN transistor Q 2  is connected to a collector of the PNP transistor Q 4  and a base of the NPN transistor Q 2  is connected to a collector of the PNP transistor Q 5  and one end of the resistor R 1 . The other end of the resistor R 1  is connected to the reference voltage input terminal 5. 
     An emitter of the PNP transistor Q 3  is connected to the power supply terminal 1, and a base thereof is connected to base and collector of the PNP transistor Q 4 . An emitter of the PNP transistor Q 4  is connected to the power supply terminal 1. An emitter of the PNP transistor Q 5  is connected to the power supply terminal 1, and a base thereof is connected to base and collector of the PNP transistor Q 6  and the constant current source 4&#39;. The other terminal of the constant current source 4&#39; is grounded. 
     An emitter of the PNP transistor Q 6  is connected to an emitter of the PNP transistor Q 7  and the power supply terminal 1. A collector of the PNP transistor Q 6  is connected to a collector of the PNP transistor Q 7 . An emitter of the PNP transistor Q 8  is connected to the power supply terminal 1 and a collector thereof is connected to one end of the resistor R 2  and the output terminal 3. The other end of the resistor R 2  is grounded. 
     An operation of the present embodiment is explained in sequence. 
     When an input voltage applied to the input terminal 2 is sufficiently higher than the reference voltage V R , the NPN transistor Q 1  is turned on and draws base currents of the PNP transistors Q 7  and Q 8 . Thus, the PNP transistor Q 8  is turned on and the output terminal 3 assumes a high level. As the PNP transistor Q 7  turns on, the collector voltage of the PNP transistor Q 7  drops from the power supply voltage V CC  by a saturation voltage. Since the saturation voltage is lower than a forward voltage which causes the PNP transistor Q 6  to turn on, the PNP transistor Q 6  is turned off and hence the PNP transistor Q 5  is also turned off. As a result, no current flows through the resistor R 1  and the reference voltage V R  is applied to the base of the NPN transistor Q 2 . 
     When the input voltage is lower than the reference voltage V R , the NPN transistor Q 1  is turned off and the PNP transistors Q 7  and Q 8  are turned off, the output voltage at the output terminal 3 is rendered low level and the PNP transistor Q 6  is turned on. A current I determined by the constant current source 4&#39; flows through the PNP transistor Q 6 . Since the PNP transistors Q 5  and Q 6  constitute a current mirror circuit, a current which is substantially equal to I flows through the PNP transistor Q 5 . 
     The voltage applied to the base of the NPN transistor Q 2  rises to a sum of the reference voltage V R  and a voltage drop IR 1  across the resistor R 1 . As the input voltage again rises, the output voltage does not change until the input voltage reaches a comparison voltage V R  +IR 1 . Thus, the voltage IR 1  serves as a hysteresis characteristic voltage. 
     FIG. 5 shows a circuit diagram of the constant current source in the embodiment. Numeral 1 denotes the power supply terminal, and numeral 5 denotes a constant current output terminal. D 1 , D 2 , D 3  and D 4  denote diodes, R 21 , R 22  and R 23  denote resistors, and the diode D 1  to D 4  and the resistor R 21  constitute a start circuit. Q 21  and Q 22  denote PNP transistors and Q 23 , Q 24  and Q 25  denote NPN transistors. 
     An operation of the constant current circuit of FIG. 5 is explained. 
     The resistor R 22  is selected such that IR 22  =2 V D  (where V D  is a forward voltage of the diode) is met by the collector current I of the PNP transistor Q 21 . When the power supply voltages V CC  applied, currents are supplied to the NPN transistors Q 23 , Q 24  and Q 25  through the resistor R 22 . When the constant current circuit becomes steady state, a voltage drop across the diode D 4  is zero and is non-conductive so that the start circuit is isolated. 
     The NPN transistor Q 24  has an emitter area which is twice as large as that of the NPN transistor Q 23 , and the PNP transistors Q 21  and Q 22  have equal emitter area. 
     The collector currents I C23  and I C24  of the NPN transistors Q 23  and Q 24 , the emitter areas A E23  and A E24  and the base emitter electrode V BE23  and V BE24  have the following relationship. ##EQU3## where V T  is a thermal voltage of the transistor. 
     Since the NPN transistor Q 23 , Q 24  and Q 25  constitute a current mirror circuit, the current I of the constant current output terminal 6 is given by ##EQU4## Thus, the current I from the constant current output terminal 6 of the constant current circuit does not depend on the power supply voltage. 
     In accordance with the present embodiment, the circuit which is hardly affected by the power supply voltage is used as the constant current source which develops the hysteresis characteristic voltage of the voltage comparator. As a result, a high precision and stable hysteresis characteristic voltage is produced.