Abstract:
An improved technique for mixing picture signals directed at a monitor screen. Two analog video signals (such as an analog VGA input and an analog RGB signal produced in response to a stored digital still or moving image) may be multiplexed in analog form. An analog chromakey mixer detects a background color in the first video signal (such as the analog VGA input), and replaces the portion of that first video signal with the second video signal. The time delays of the first video and the second video signal may be adjusted so that they reach the monitor screen (by means o a multiplexer output) at the same time. An alignment detector may attempt to align chromakey mixer until the time difference between the first and the second video signals falls below a threshold.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to an analog video chromakey mixer. 
     2. Description of Related Art 
     When still or moving images in digital form are displayed in a computer system, the digital images must generally be decoded and displayed as images on a computer monitor screen. Typically, the monitor screen is the only monitor screen in the computer system. However, those decoded and displayed images must be coordinated with other display signals directed at the same monitor screen, such as those signals directed that the monitor screen by an RGB or VGA monitor driver. Typically, the two sets of signals directed at the monitor screen must be multiplexed in some way. 
     Generally, it is desired that the two sets of signals must be smoothly multiplexed, with no breaks that would be visible to the human eye. It is also generally desired that the two sets of signals should be multiplexed quickly, so that high quality, high speed images may be displayed. It is also generally desired that any method for multiplexing the two sets of signals should work with a wide variety of computer systems and with a minimum of adaptation required for any of them. 
     However, one problem that has arisen in the art is that high quality, high speed multiplexing of analog and digital video signals can be difficult. For example, if it were desired to digitize the analog video signals and multiplex them with the digital signals entirely digitally, it could require an A/D converter that produced 16 million colors (24 bits) at a 75 MHz pixel rate. Present A/D converters do not operate at this combination of precision and speed, at least not at anything near a reasonable cost for a personal computer system. 
     One method of the prior art has been to multiplex the digital data provided by the computer system&#39;s processor (or CPU) to the monitor driver. While this method sometimes achieves the goal of synchronizing digital and analog video sources, it has the drawback that it requires substantial information about the method of color encoding used by the VGA monitor driver. As monitor drivers have been changed with improvements in monitors and in drivers, this method also has the drawback that it may fail to work for certain classes of monitor drivers. 
     Accordingly, it is an object of the invention to provide an improved technique for mixing picture signals directed at a monitor screen. 
     SUMMARY OF THE INVENTION 
     The invention provides an improved technique for mixing picture signals directed at a monitor screen. 
     In a preferred embodiment, two analog video signals, such as an analog VGA input and an analog RGB signal produced in response to a stored digital still or moving image, may be multiplexed in analog form. An analog chromakey mixer detects a background color in the first video signal and replaces the portion of that first video signal with the second video signal. 
     In a preferred embodiment, the time delays of the first video signal and the second video signal may be adjusted so that they reach the monitor screen (by means of a multiplexer output) at the same time. An alignment detector may attempt to align two known signals (such as a VGA sync signal and a signal generated for this purpose), and may adjust a set of time delays in the analog chromakey mixer until the time difference between the first and second video signals falls below a threshold. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a video system architecture. 
     FIG. 2 shows a block diagram of an analog chromakey mixer. 
     FIG. 3 shows signal waveforms for video signal matching. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     System Architecture 
     FIG. 1 shows a video system architecture. 
     In a preferred embodiment, a video system  101  embedded in a computer system comprises a VGA input  102 , having a sync input  103  for a horizontal sync (HS) signal  104  and a vertical sync (VS) signal  105 , and having a first video input  106  for a first analog signal  107  (such as an analog RGB video signal). In a preferred embodiment, the VGA input  102  may be coupled to a VGA monitor driver, such as a personal computer system comprising a monitor driver card or another monitor driver circuit. VGA monitor drivers are known in the art. The sync input  103  is coupled to a sync output  108 . 
     The sync input  103  and the first analog signal  107  are coupled to an analog chromakey mixer  109 , which detects a key color in the analog RGB video signal and multiplexes the first analog signal  107  with a second analog RGB signal. 
     The analog chromakey mixer  109  is coupled to a set of reference voltages  110 , comprising a +5 volt source and a −5 volt source in a preferred embodiment, to a CCLK signal  111  and a CDATA signal  112 , for communication with the computer system, to a PCLK signal  113  and a VRDY signal  114 , and to a second video input  115 . The analog chromakey mixer  109  provides an output FBLANK signal  116  and an output FCLOCK signal  117 , and a video output  118 . 
     The sync input  103  is coupled to a digital signal processor (DSP)  119 , which provides a digital video signal  120  having a sequence of digital pixels. The DSP  119  is coupled to the FBLANK signal  116  and the FCLOCK signal  117  from the analog chromakey mixer  109 . The DSP  119  provides the PCLK signal  113  and the VRDY signal  114 . 
     The digital video signal  120  is coupled to a video D/A converter  121 , which converts the digital video signal  120  to a second analog signal  122  having a sequence of analog pixels. The second analog signal  122  is coupled to the analog chromakey mixer  109  at the second video input  115 . 
     System Operation 
     In a preferred embodiment, the HS signal  104  and the VS signal  105  provide sync information for the first analog signal  107 , and for the multiplexed video signal coupled to the video output  118 . 
     The analog chromakey mixer  109  is described in further detail with reference to FIG.  2 . 
     The reference voltages  110  provide power and logical references for the analog chromakey mixer  109 . Reference voltages are known in the art. In a preferred embodiment, the reference voltages  110  may also be coupled to other circuits for similar purposes. 
     The CCLK signal  111  and a CDATA signal  112  are for communication with the computer system. These signals are used by the computer system to program voltage reference levels and internal registers of the analog chromakey mixer chip  109 . Programming reference levels and internal registers of a chip by means of input signals is known in the art. 
     The PCLK signal  113  is a clock for the VRDY signal  114 . The VRDY signal  114  indicates whether a digital pixel in the a digital video signal  120  comprises valid data. 
     The FBLANK signal  116  provides a composite blanking signal for the DSP  119 . The FCLOCK signal  117  provides a pixel clock for the DSP  119 . 
     In a preferred embodiment, the DSP  119  may comprise the Piccolo chip (available from Sigma Designs, Inc., of Fremont, Calif.). 
     In a preferred embodiment, the digital video signal  120  comprises a sequence of digital pixels, each having 8 bits of precision for each of three colors (red, green, and blue), at a rate of about 20 nanoseconds per digital pixel. 
     The D/A converter  121  converts each digital pixel to a set of three analog voltages, one for each of three colors. D/A converters are known in the art. In a preferred embodiment, the D/A converter  121  may comprise the BT 121  device (available from Brooktree Corporation of San Diego, Calif.). 
     Analog Chromakey Mixer 
     FIG. 2 shows a block diagram of an analog chromakey mixer. 
     In a preferred embodiment, the HS signal  104  is coupled to a line locked phase locked loop (PLL)  201 , which recovers a clock signal from the HS signal  104 . Phase locked loops are known in the art. The line locked PLL  201  is coupled to a phase adjuster  202 , which provides an adjustable delay. An output of the phase adjuster  202  provides the FCLOCK signal  117 . The phase adjuster  202  is coupled to a counter  203 , which provides the FBLANK signal  116 . 
     The HS signal  104  and the VS signal  105  are coupled to a polarity detector  204 . In a preferred embodiment, the HS signal  104  and the VS signal  105  may have any polarity. The polarity detector  201  uses the FCLOCK signal  117  to sample the HS signal  104 ; if the same value is sampled for more than  256  consecutive clock pulses, that value is considered to represent the inverse of the polarity of the HS signal  104 . Similarly, the polarity detector  201  uses the FCLOCK signal  117  to sample the VS signal  105 ; if the same value is sampled for more than  256  consecutive clock pulses, that value is considered to represent the inverse of the polarity of the VS signal  105 . 
     The first analog signal  107  is coupled to a chromakey detector  205 , which determines whether a present analog pixel of the analog RGB video signal matches the color to be replaced (the chromakey). The chromakey detector  205  is coupled to a set of six D/A converters  206  that provide a set of three minimum/maximum values for the red (R), green (G), and blue (B) color components of the analog RGB video signal. The chromakey detector  205  determines a color match when the detected color falls within the minimum/maximum values for all three color components, and generates a match signal  208 . 
     The first analog signal  107  is coupled, by means of a delay  207 , to a first input of an analog multiplexer  209 . 
     The CCLK signal  111  and the CDATA signal  112  are coupled to a control circuit  210 , for programming voltage reference levels and internal registers of the analog chromakey mixer chip  109 . Programming reference levels and internal registers of a chip by means of input signals is known in the art. 
     The PCLK signal  113  is used to clock the VRDY signal  114  to an input of a programmable delay  211 , which provides an output VRDY 1  signal  212 . The VRDY 1  signal  212  is coupled to a fine delay  213 , which provides an output VRDY 2  signal  214 . The VRDY 2  signal is coupled to an input of a logical AND gate  215 . 
     The match signal  208  is coupled to another input of the logical AND gate  215 . An output of the logical AND gate  215  is coupled to a select input of the analog multiplexer  209 . The second analog signal  122  is coupled to a second input of the analog multiplexer  209 . An output of the analog multiplexer  209  is coupled to the video output  118 . 
     Analog Chromakey Mixer Operation 
     In a preferred embodiment, the chromakey detector  205  detects the chromakey in the first analog signal  107 ; the match signal  208  indicates that the chromakey detector  205  found a match. When a match is found, at the next valid pixel from the D/A converter  121 , the match signal  208  and the VRDY signal  114  will both be logical “1”, and the logical AND gate  215  will cause the analog multiplexer  209  to select the second analog signal  122  instead of the first analog signal  107 . 
     A cumulative time delay t 1  between input and output of the first analog signal  107  may comprise time delays as shown in table 2-1: 
     
       
         
               
               
             
               
             
           
               
                 TABLE 2-1 
               
               
                   
               
               
                 Time Delay 
                 Cause of Time Delay 
               
               
                   
               
             
             
               
                 t251 
                 from the first video input 106 to an input of the delay 207 
               
               
                 t252 
                 across the delay 207 
               
               
                 t253 
                 from the output of the delay 207 to the output of the analog 
               
               
                   
                 multiplexer 209 
               
             
          
           
               
                 Thus, t1 = t251 + t252 + t253, where t252 is adjustable. 
               
               
                   
               
             
          
         
       
     
     A cumulative time delay t 2  between input and output of the second video signal  122  may comprise time delays as shown in table 2-2: 
     
       
         
               
               
             
               
             
           
               
                 TABLE 2-2 
               
               
                   
               
               
                 Time Delay 
                 Cause of Time Delay 
               
               
                   
               
             
             
               
                 t261 
                 across the line locked PLL 201 
               
               
                 t262 
                 across the phase adjuster 202 
               
               
                 t263 
                 from the output of the FCLOCK signal 117 to the output of 
               
               
                   
                 the digital video signal 120 from the DSP 119 
               
               
                 t264 
                 across the D/A converter 121 
               
               
                 t265 
                 from the output of the D/A converter 121 to the output of 
               
               
                   
                 the analog multiplexer 209 
               
             
          
           
               
                 Thus, t2 = t261 + t262 + t263 + t264 + t265, where t262 is adjustable. 
               
               
                   
               
             
          
         
       
     
     A cumulative time delay t 3  between input and output of the first video signal  107  may alternatively comprise time delays as shown in table 2-3: 
     
       
         
               
               
             
               
             
           
               
                 TABLE 2-3 
               
               
                   
               
               
                 Time Delay 
                 Cause of Time Delay 
               
               
                   
               
             
             
               
                 t251 
                 from the first video input 106 to an input of the delay 207 
               
               
                 t272 
                 from the input of the delay 207 to the output of the chroma- 
               
               
                   
                 key detector 205 
               
               
                 t273 
                 from the output of the chromakey detector 205 to the output 
               
               
                   
                 of the logical AND gate 215 
               
               
                 t274 
                 from the output of the logical AND gate 215 to the output 
               
               
                   
                 of the analog multiplexer 209 
               
             
          
           
               
                 Thus, t3 = t251 + t272 + t273 + t274, where none of these values is 
               
               
                 adjustable. 
               
               
                   
               
             
          
         
       
     
     A cumulative time delay t 4  between input and output of the second video signal  122  may alternatively comprise time delays as shown in table 2-4: 
     
       
         
               
               
             
               
             
           
               
                 TABLE 2-4 
               
               
                   
               
               
                 Time Delay 
                 Cause of Time Delay 
               
               
                   
               
             
             
               
                 t261 
                 across the line locked PLL 201 
               
               
                 t262 
                 across the phase adjuster 202 
               
               
                 t283 
                 from the output of the FCLOCK signal 117 to the output of 
               
               
                   
                 the VRDY signal 114 from the DSP 119 
               
               
                 t284 
                 across the programmable delay 211 
               
               
                 t285 
                 across the fine delay 213 
               
               
                 t286 
                 from the output of the fine delay 213 to the output of the 
               
               
                   
                 logical AND gate 215 
               
               
                 t274 
                 from the output of the logical AND gate 215 to the output 
               
               
                   
                 of the analog multiplexer 209 
               
             
          
           
               
                 Thus, t4 = t261 + t262 + t283 + t284 + t285 + t286 + t274, where t262, 
               
               
                 t284, and t285 are adjustable. 
               
               
                   
               
             
          
         
       
     
     In a preferred embodiment, all four cumulative time delays must be equal: t 1 =t 2 =t 3 =t 4 . Each time delay t 1 , t 2 , and t 4 , comprises at least one adjustable time delay. Cumulative time delay t 1  comprises adjustable time delay t 252 . Cumulative time delay t 2  comprises adjustable time delay t 262 . Cumulative time delay t 4  comprises adjustable time delays t 262 , t 284 , and t 285 . Accordingly, adjusting time delays t 252 , t 262 , t 284 , and t 285 , allows all four cumulative time delays t 1 , t 2 , t 3 , and t 4 , to be adjusted until they are equal. 
     An alignment detector  216  is coupled to an output of the analog multiplexer  209 . The alignment detector  216  is also coupled to a set of control lines  217 , coupled to each device that controls an adjustable time delay: delay  207  (controlling time delay t 252 ), phase adjuster  202  (controlling time delay t 262 ), programmable delay  211  (controlling time delay t 284 ), and fine delay  213  (controlling time delay t 285 ). 
     In a preferred embodiment, delay  207  and programmable delay  211  may be set when the analog chromakey mixer  109  is manufactured, so that t 1 =t 3 . Thus, only t 2  and t 4  need to be adjusted, by adjusting t 262  and t 285 . 
     Video Signal Matching 
     FIG. 3 shows signal waveforms for video signal matching. 
     In a preferred embodiment, the alignment detector  216  may operate when the video system  101  is first powered on, or when the video system  101  is reset. During operation of the alignment detector  216 , a first test signal  301  is generated and coupled to the first signal input  106  of the video system  101 . The first test signal  301  comprises a sequence of spikes  302  of a first color, with a black background. A second test signal  303  is generated by the DSP  119  and coupled to the video system  101  as the digital video signal  120 . The second test signal  303  comprises a background of a second color, with a sequence of black spikes  304 . 
     The chromakey is set so that the positive voltage spikes  302  of the first test signal  301  are replaced by the black spikes  304  of the second test signal  303 . The first test signal  301  and the second test signal  303  are generated so that when properly aligned, the output signal  305  from the video output  118  will be completely black. 
     The alignment detector  216  detects any color spikes in the output signal  305 , whether the first color or the second color. If color spikes are not present, the first test signal  301  and the second test signal  303  are perfectly aligned, and no adjustment of time delays is needed. If color spikes are present, the first test signal  301  and the second test signal  303  are not perfectly aligned, and one or more time delays must be adjusted to obtain perfect alignment. 
     The alignment detector  216  adjusts the values of the time delays t 262  and t 285  until there are no color spikes (or at least until the color spikes are minimized) in the output signal  305 . In a preferred embodiment, there are about 64 possible values for time delay t 262  and about 64 possible values for time delay t 285 , so it is possible for the alignment detector  216  to try all possible values of time delays t 262  and t 285  in only a few seconds. Thereafter, there is no need to adjust any of the time delays further. 
     Alternative Embodiments 
     While preferred embodiments are disclosed herein, many variations are possible which remain within the concept and scope of the invention, and these variations would become clear to one of ordinary skill in the art after perusal of the specification, drawings and claims herein.