Abstract:
A method of forming a fin liner and the resulting device are provided. Embodiments include forming silicon (Si) fins over negative channel field-effect transistor (nFET) and positive channel field-effect transistor (pFET) regions of a substrate, each of the Si fins having a silicon nitride (SiN) cap; forming a SiN liner over the Si fins and SiN caps; forming a block mask over the pFET region; removing the SiN liner in the nFET region; removing the block mask in the pFET region; forming a diffusion barrier liner over the Si fins; forming a dielectric layer over and between the Si fins; planarizing the dielectric layer down to the SiN caps in the nFET region; and recessing the dielectric layer to expose an upper portion of the Si fins.

Description:
RELATED APPLICATION 
       [0001]    The present application is a Divisional of application Ser. No. 14/835,786, filed on Aug. 26, 2015, the disclosure of which is incorporated herein by reference in their entirety. 
     
    
     TECHNICAL FIELD 
       [0002]    The present disclosure relates to the manufacture of semiconductor devices including fin-shaped field effect transistors (finFET). In particular, the present disclosure relates to a fin liner used in manufacturing a semiconductor device in the 14 nanometer (nm) technology node and beyond. 
       BACKGROUND 
       [0003]    A finFET includes a narrow source-channel-drain region (the fin) around which is formed a gate. Activation of the gate, source and drain facilitates current drivability in the channel between the source and the drain, thereby facilitating operation of the finFET. Defects in the channel regions of the fins, such as dislocation and stacking fault-like defects, can arise when punch through stop (PTS) implant is performed. Moreover, during reactive ion etching (RIE) of the fins, the positive channel field-effect transistor (pFET) fins end up being smaller than the negative channel field-effect transistor (nFET) fins due to the faster etch rate of the pFET fins formed of silicon germanium (SiGe). Further, punch through leakage is a main component of off-state leakage in bulk finFETs, and it is usually suppressed by forming various punch through stop liners. The punch through is a leakage current between the source and drain in a transistor, so that it is more vulnerable in a short channel device where the distance between source and drain is short. That is, the closer the distance, the larger punch through leakage current. Various liners, such as silicon nitride (SiN), silicon dioxide (SiO 2 )/silicon nitride (SiN), and SiO 2 /siliconborocarbonitride (SiBCN) have been used, but can affect device performance. 
         [0004]    A need therefore exists for methodology enabling elimination of the PTS implant, prevention of channel damage, elimination of a lithography step to simplify integration, improved nFET and pFET short channel (SC) performance, and better gap fill friendly integration than borosilicate glass (BSG) and phosphosilicate glass (PSG) schemes and the resulting devices. 
       SUMMARY 
       [0005]    An aspect of the present disclosure includes a more simplified methodology that eliminates a lithography step and channel damage by foregoing PTS implanting, while maintaining device performance. 
         [0006]    Another aspect of the present disclosure is a device having no channel damage caused by PTS implants and, therefore, improved nFET and pFET SC performance. 
         [0007]    Additional aspects and other features of the present disclosure will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present disclosure. The advantages of the present disclosure may be realized and obtained as particularly pointed out in the appended claims. 
         [0008]    According to the present disclosure, some technical effects may be achieved in part by a method including: forming silicon (Si) fins over nFET and pFET regions of a substrate, each of the Si fins having a SiN cap; forming a SiN liner over the Si fins and SiN caps; forming a block mask over the pFET region; removing the SiN liner in the nFET region; removing the block mask in the pFET region; forming a diffusion barrier liner over the Si fins; forming a dielectric layer over and between the Si fins; planarizing the dielectric layer down to the SiN caps in the nFET region; and recessing the dielectric layer to expose an upper portion of the Si fins. 
         [0009]    Aspects include the diffusion barrier liner including SiBCN. Other aspects include removing the SiN cap and SiBCN from the exposed upper portion of the Si fins with a hot phosphorous treatment. Still further aspects include the dielectric layer including silicon dioxide (SiO 2 ). Additional aspects include annealing the SiO 2  layer to densify the SiO 2  layer. Other aspects include the Si fins in the pFET region including silicon germanium adjacent an upper portion of the Si fins. Further aspects include the Si fins in the nFET region being larger than the Si fins in the pFET region. Yet other aspects include oxidizing exposed regions of the Si fins in the nFET region with an in-situ steam generation (ISSG) process to form a 1 nanometer (nm) thick liner of SiO 2 , wherein the Si fins in the nFET region are the same size as the Si fins in the pFET region following the ISSG process. Another aspect includes forming an optical planarization layer (OPL) over the nFET and pFET regions and an anti-reflective coating (ARC) over the OPL. Additional aspects include removing the OPL in the pFET region by wet etching. Other aspects include planarizing the dielectric layer by chemical mechanical polishing (CMP). 
         [0010]    Another aspect of the present disclosure is a device including: Si fins formed over nFET and pFET regions of a substrate; a SiO 2  liner over the Si fins in the nFET region; a dielectric layer disposed between a lower portion of the Si fins, leaving an exposed upper portion of the Si fins; and a SiBCN liner disposed between the Si fins and the dielectric layer and on a bottom surface of the dielectric layer. 
         [0011]    Aspects include the exposed upper portion of the Si fins in the pFET region including SiGe. Other aspects include the SiO 2  liner in the nFET region being disposed between the SiBCN liner and the Si fins. Further aspects include the SiO 2  liner having a thickness of 1 nm on opposing sides of the Si fins. Additional aspects include a SiN liner disposed on the Si fins in the pFET region between the SiBCN liner and the Si fins. Another aspect includes the nFET channel region is being doped with boron (B). Another aspect includes the dielectric layer including SiO 2 . 
         [0012]    Another aspect of the present disclosure is a method including: forming Si fins, each having a SiN cap, over nFET and pFET regions of a substrate, the Si fins in the pFET region including a SiGe portion below the SiN cap, and the Si fins in the nFET region being larger than the Si fins in the pFET region; depositing a SiN liner over the Si fins and SiN caps; depositing an OPL over the nFET and pFET regions and an ARC over the OPL in the pFET region; etching the OPL in the nFET region to remove the SiN liner in the nFET region; removing the OPL in the pFET region; oxidizing exposed regions of the Si fins in the nFET region; depositing a SiBCN liner over the Si fins; depositing a SiO 2  layer over and between the Si fins; planarizing the SiO 2  layer down to the SiN caps of the nFET region with CMP; recessing the SiO 2  layer to expose an upper portion of the Si fins; and removing the SiN liner and SiBCN liner from the exposed upper portion of the Si fins in the nFET region. 
         [0013]    Aspects include removing the SiN cap and SiBCN from the exposed upper portion of the Si fins with a hot phosphorous treatment. 
         [0014]    Additional aspects and technical effects of the present disclosure will become readily apparent to those skilled in the art from the following detailed description wherein embodiments of the present disclosure are described simply by way of illustration of the best mode contemplated to carry out the present disclosure. As will be realized, the present disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]    The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which: 
           [0016]      FIGS. 1 through 13  illustrate, in cross sectional view, a process flow to produce a liner over fins, in accordance with an exemplary embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0017]    In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about”. 
         [0018]    The present disclosure addresses and solves the current problems of channel damage caused by PTS implanting and deterioration of performance caused by fin liners. 
         [0019]    Still other aspects, features, and technical effects will be readily apparent to those skilled in this art from the following detailed description, wherein preferred embodiments are shown and described, simply by way of illustration of the best mode contemplated. The disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive. 
         [0020]    Adverting to  FIG. 1 , fins  101  are formed over substrate  103 . Substrate  103  includes a Si substrate. Other examples of materials that may be suitable for use in the substrate  103  include silicon-on-insulator (SOI), SiGe, germanium (Ge), and/or compound semiconductor materials. Processes, such as, photolithography and etch processes, can be used to create the fins  101 . The fins  101  may include silicon. 
         [0021]    The fins  101  include the channels of a finFET. The fins  101  may be coupled to the source/drain regions of the finFET. A gate structure (not shown for illustrative convenience) can be formed on and over the fins  101  and spacers may be provided on sides of the gate structure. The gate structure may include polysilicon, silicon-germanium, a metal including metal compounds such as Mo, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, and/or other suitable conductive materials. 
         [0022]    In the example of  FIG. 1 , the fins  101  formed over nFET channel region  105  of substrate  103  an doped with p-type dopants including boron (B). A positively doped channel is formed in nFET channel region  105 . The fins  101  formed over pFET channel region  107  of substrate  103  are to be doped with n-type dopants including phosphorous (P). A negatively doped channel is formed in pFET channel region  107 . 
         [0023]    A SiN protective cap  109  is formed over the fins  101 . The fins in the pFET channel region  107  can be formed exclusively of Si or optionally include an upper region  111  of the fins  101  formed of SiGe. As shown in  FIG. 1 , the fins  11  of the pFET region are narrower than the fins in the nFET region since the SiGe has a higher etch rate than Si alone. 
         [0024]    Adverting to  FIG. 2 , a SiN liner  201  is formed over the Si fins  101  and SiN caps  109 . The SiN liner  201  can be deposited by atomic layer deposition (ALD). As a result, a beneficial positive charge is created on the pFET channel region  107 , which can reduce punch through. 
         [0025]    Adverting to  FIG. 3 , a block mask is formed and includes a step of depositing an OPL  301  over the nFET and pFET channel regions  105  and  107  and an ARC  303 , such as a SiARC, is deposited over the OPL  301  in the pFET channel region  107 . As shown in  FIG. 4 , a dry etching step is performed to remove the OPL  301  in the nFET channel region  105 . Following the dry etching step, a RIE step is performed to remove the SiN liner  201  from the fins  101  in the nFET channel region  105 . An upper portion of the SiN caps  109  in the nFET region  105  is lost during the RIE step such that the height of the fins  101  in the nFET channel region is less than the height of the fins  101  in the pFET channel region  107 . As illustrated in  FIG. 5 , the ARC  303  is removed from the OPL  301  in the pFET channel region  107  by wet etching. In  FIG. 6 , the OPL  301  is stripped away by a chemical etching, leaving the SiN liner  201  intact over the fins  101  in the pFET channel region  107 . 
         [0026]    Adverting to  FIG. 7 , the fins  101  in the nFET channel region  105  are oxidized to form oxidized regions along the sides of the fins  101  and upper surface of the substrate  103 . Specifically, exposed regions of the fins  101  in the nFET region are treated with an in-situ steam generation (ISSG) process to form a 1 nanometer (nm) thick liner of silicon dioxide (SiO 2 )  701 . The fins  101  in the nFET channel region  105  are the same size as the fins  101  in the pFET channel region  107  following the ISSG process. The fins  101  in the nFET channel region  105  are reduced during the oxidation such that the size is the same as the fins  101  in the pFET channel region  107 . When the critical dimension (CD) of the fins  101  in the nFET region  105  is the same as the CD of the fins  101  in the pFET region  107 , no ISSG step is necessary. 
         [0027]    As illustrated in  FIG. 8 , a SiBCN liner  801  is deposited over the fins  101  in the nFET and pFET channel regions  105  and  107 . Boron doping on the fins  101  in the nFET channel region due to the deposition of the SiBCN liner  801  helps reduce punch through. The SiN liner  201  over the fins  101  in the pFET channel region  107  blocks the B diffusion from the SiBCN liner  801 . Adverting to  FIG. 9 , CVD of SiO 2  is used to fill the spacing between fins  101  in the nFET and pFET channel regions  105  and  107 . Following the CVD, a high temperature steam annealing step is performed to form a densified SiO 2  region  901  (dielectric layer) and oxidize the nFET and pFET channel regions  105  and  107 . The SiBCN liner  801  prevents oxide diffusion from the SiO 2  region  901  during the steam annealing in the nFET and pFET channel regions  105  and  107 . The SiN liner  201  on the fins  101  of the pFET channel region  107  provides an additional barrier on fins  101  of the pFET channel region  107 . With a thinner SiN cap  109  over the fins  101  of the nFET channel region, a more gap fill friendly region is provided. 
         [0028]    Adverting to  FIG. 10 , an oxide CMP is performed to remove the excess SiO 2  region  901  over the fins  101 . The CMP removes/planarizes the SiO 2  region  901  down to the upper portion of the SiBCN liner  801  over the fins  101  in the pFET channel region  107 . Due to the thinner SiN caps  109  in the nFET channel region  105 , a portion of the SiO 2  region  901  remains over the tops of the fins  101  in the nFET channel region  105 . In  FIG. 11 , a SiN CMP process is performed such that that the SiN caps  109  in the nFET channel region  105  are exposed. 
         [0029]    Next, an oxide recess is formed to remove the SiO 2  region  901  from regions between the fins  101  in the nFET and pFET channel regions  105  and  107 , as illustrate in  FIG. 12 . This oxide recess exposes the upper portions of the fins  101  which become channel regions of the finFET. In  FIG. 13 , the exposed upper portions of the fins are subjected to a hot phosphorous treatment to remove the SiN and SiBCN such that only Si fins are exposed above the SiO 2  region  901  in the nFET channel region  105 , and only the SiGe region  111  of the fins  101  in the pFET channel region  107  are exposed above the SiO 2  region  901 . Additional processing may continue for the fabrication of one or more gate structures on the substrate  103 . A gate structure (not shown for illustrative convenience) can be formed on and over the fins  101 . 
         [0030]    The embodiments of the present disclosure can achieve several technical effects including reduced punch through, since the SiBCN  801  in the nFET channel region  105  functions as a B implant source and prevents SiO 2  diffusion from a field oxide (FOX) region  901  during steam annealing, and elimination of the need for a PTS implant. In addition, the SiBCN  801  performs better than the BSG/PSG scheme which does not function as a diffusion barrier under very small fin pitch requiring flowable CVD (FCVD) and densification annealing. In the pFET channel region  107 , the SiN liner  201  provides a positive charge to reduce punch through, and no PTS implant is required. By eliminating the PTS implant for both the nFET and pFET channel regions  105  and  107 , the integration becomes simpler, and process costs are reduced. 
         [0031]    Devices formed in accordance with embodiments of the present disclosure enjoy utility in various industrial applications, e.g., microprocessors, smart-phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, and digital cameras. The present disclosure therefore enjoys industrial applicability in the manufacture of any of various types of highly integrated semiconductor devices having fins with a liner. 
         [0032]    In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.