Abstract:
The present invention provides an apparatus and a method for estimating at least one of timing, gain, and offset errors of a time-interleaved ADC. The apparatus has a first ADC, a second ADC, a converter, an estimator, and a compensator. The converter has a Fourier Transform converter and a calculator.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
   This application claims the benefit of U.S. Provisional Application No. 60/594,511, filed on Apr. 13, 2005 and entitled “TONE-CORRELATOR METHOD TO ESTIMATE TIMING/GAIN/OFFSET ERRORS FOR TIME-INTERLEAVED ADC”, the contents of which are incorporated herein by reference. 

   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to an analog to digital converter (ADC), and more particularly, to a correlation circuit for an ADC. 
   2. Description of the Prior Art 
   As communication systems advance quickly, ADCs with broad bandwidth and high resolution are required. Time-interleaved ADCs, a.k.a. parallel ADCs, are thereby introduced. This kind of ADC utilizes M parallel ADCs having a sampling frequency f s  and an n-bit resolution. Sample timings of these M ADCs are distributed uniformly within one period T=1/f s . In other words, assuming that the sample timings of the first ADC, ADC 0 , are (0, T, 2T, . . . ), the sample timings of the second ADC, ADC 1 , will be (T/M, T+T/M, 2T+T/M, . . . , and the sample timings of the (i+1) th  ADC, ADC i , will be (iT/M, 1T+iT/M, 2T+iT/M, . . . ). As a result, the bandwidth of the original ADC is expanded to M multiple and the n-bit resolution is maintained. 
   Some errors may occur due to mismatch among ADCs. These potential errors include timing error, gain error, and offset error. Any one of combination of the three errors may degrade the efficiency of the time-interleaved ADC. The timing error affects the efficiency most. Structure of unique sample and hold (S/H) circuit for all ADCs is usually adopted to reduce the timing error. This S/H circuit must be having a very high speed sampling frequency and very accurate circuit. 
   There are several other methods to estimate the above-mentioned errors. One of them is to input a test sine wave to time-interleaved ADC, and to individually analyze the phase and the amplitude of the output signal of each ADC to obtain information about the timing error and gain error. However, the frequency of the test sine wave is constrained to (1+s) f s , where −0.5&lt;s&lt;0.5, and the phase and the amplitude of the output signal can only be estimated in the time domain. Another method is to estimate the timing error of a test sine wave in the frequency domain. However, a highly complicated calculation of DFT/IDFT is necessary in the digital domain. A background compensation method has also been introduced. Before being received by the S/H circuit, an input signal is added to an analog ramp function signal having a period t s =1/Mf s . If the average (DC component) of the input signal is zero, the information of timing error will hide in the DC component of each ADC output due to the ramp function. This method assumes that the average of the input signals is zero and no offset error exists between ADCs. Still another method is based on a signal statistics principle. If a timing error occurs, a mean square difference between two adjacent ADCs includes information about the timing error. Although this method is a background compensation method and no extra analog signals are required, complicated calculation in the digital domain cannot be avoided. 
   SUMMARY OF THE INVENTION 
   The object of the present invention is therefore to provide a estimating circuit and the method for a time-interleaved ADC to solve the above-mentioned problems. 
   According to a claimed embodiment of the present invention, a method for correcting a time-interleaved analog-to-digital converter (ADC) comprising a first ADC and a second ADC is disclosed. The method includes utilizing the first ADC to sample an input signal with a predetermined sampling frequency to generate a first set of sampled data; utilizing the second ADC to sample the input signal with the predetermined sampling frequency to generate a second set of sampled data; respectively performing a Fourier Transform on the first and the second sets of sampled data to generate a first and a second complex numbers; generating an estimated value according to the first and the second complex numbers; and utilizing the estimated value to correct the second ADC. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  shows a time-interleaved ADC according to a first embodiment of the present invention. 
       FIG. 2  shows a time-interleaved ADC according to a second embodiment of the present invention. 
       FIG. 3  shows a time-interleaved ADC according to a third embodiment of the present invention. 
       FIG. 4  shows an inner circuit of the converting circuit. 
       FIG. 5  shows plot of the control signal ctl. 
       FIG. 6  shows the calculation unit shown in  FIG. 1 . 
       FIG. 7  shows the calculation unit shown in  FIG. 2 . 
       FIG. 8  shows the calculation unit shown in  FIG. 3 . 
       FIG. 9  shows a calculation unit for calculating a timing error and a gain error simultaneously. 
       FIG. 10  is a plot illustrating a down-converted signal sampled by an ADC and a down-sampler. 
   

   DETAILED DESCRIPTION 
     FIG. 1  shows a time-interleaved ADC according to a first embodiment of the present invention. It is assumed that M ADC  110  (ADC 0 , ADC 1 , . . . , ADC M−1 ) are included, and each has a sampling frequency of f s . Each ADC  110  receives an analog sine wave S from a signal generator  101 . The sine wave S has a frequency of f s /N, N being an integer, i.e., the sampling frequency of each ADC  110  is N multiple of the frequency of the sine wave S. Theoretically, the sampling timings of M ADC  110  should distribute uniformly within one period T=1/f s , i.e., the sampling timing difference between two adjacent ADCs is T/M. Moreover, practically, for the (i+1) th  ADC i , the relationship between the input signal x i  and the output y i  is expressed as follows (quantization error is neglected):
   y   i =(1+ a   i ) x   i   +b   i   
   wherein, a i  is the gain error of the (i+1) th  ADC i , and b i  is the offset error. The correction method disclosed in this invention observes the output signals of each ADC in digital domain, and then filters out unnecessary frequency components keeping only the specified frequency components. Information of timing error and gain error is respectively obtained by estimating phase and amplitude of the filtered output signals. In addition, offset error information can also be obtained by averaging the output signals of every ADC. 
   The frequency of the analog sine wave S is f s /N if a foreground compensation is applied. If a background compensation is applied the frequency is f s /2 to prevent the high-frequency aliasing components ((1+1/N)f s , (2+1/N)f s , . . . ) from disturbing the analog sine wave S. However, any existing frequency component of the input signal can be chosen as the analog sine wave S provided that the frequency component has sufficient power. 
   Each ADC  110  samples every frequency component of the analog sine wave S with respect to the phase of individual sampling timing. The (i+1) th  ADC i  obtains sampled data S i (n), n being the number of sampled data. The sampled data S i (n) is then received by the converting circuit  120 . The converting circuit  120  filters unnecessary frequency components, and analyzes the phase and the amplitude of the output signal of each ADC  100  with respect to the specific frequency component. If the normalized frequency of the specific frequency component is 1/N in the digital domain, the phase difference between two adjacent ADC  110  should be 2π/NM because the sampling timing of the M ADCs  110  are distributed uniformly. If the phase error caused by the timing error of the (i+1) th  ADC i  is assumed to be Δφ i , the phase difference between ADC i  and ADC 0  should be 
   
     
       
         
           
             
               
                 
                   φ 
                   i 
                 
                 = 
                 
                   
                     
                       
                         2 
                         ⁢ 
                         π 
                       
                       NM 
                     
                     ⁢ 
                     i 
                   
                   + 
                   
                     Δφ 
                     i 
                   
                 
               
             
             
               
                 Eq 
                 . 
                 
                     
                 
                 ⁢ 
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
   
   Therefore, the timing error in seconds of the (i+1) th  ADC i  is 
   
     
       
         
           
             
               
                 
                   dT 
                   i 
                 
                 = 
                 
                   
                     NT 
                     
                       2 
                       ⁢ 
                       π 
                     
                   
                   ⁢ 
                   
                     Δφ 
                     i 
                   
                 
               
             
             
               
                 Eq 
                 . 
                 
                     
                 
                 ⁢ 
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
   
   Similarly, the information of gain error of the (i+1) th  ADC i  corresponds to the amplitude difference between ADC i  and ADC 0 . 
   After filtering out unnecessary frequency components, the converting circuit  120  performs a Fast Fourier Transform (FFT) on the specific frequency component. Since the converting circuit  120  performs the FFT only on the specific component, therefore a single-point FFT is referred to hereafter in this embodiment. The FFT can be regarded as a band-pass filter with an extremely narrow bandwidth that allows only the observed frequency to pass, i.e. the specific frequency. As a result, when the converting circuit  120  performs the FFT on the analog sine wave S, all frequency components except the specific component are filtered out. The converting circuit  120  also generates the amplitude information and the phase information of the analog sine wave S. The FFT can avoid complicated calculation and therefore only the frequency of the analog sine wave f s /N is taken into consideration. Setting N=L/k, the formula for the FFT is expressed as: 
   
     
       
         
           
             
               
                 
                   
                     Z 
                     i 
                   
                   ⁡ 
                   
                     [ 
                     k 
                     ] 
                   
                 
                 = 
                 
                   
                     
                       ∑ 
                       
                         n 
                         = 
                         0 
                       
                       
                         L 
                         - 
                         1 
                       
                     
                     ⁢ 
                     
                       
                         
                           s 
                           i 
                         
                         ⁡ 
                         
                           ( 
                           n 
                           ) 
                         
                       
                       ⁢ 
                       
                         cos 
                         ⁡ 
                         
                           ( 
                           
                             
                               2 
                               ⁢ 
                               π 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               kn 
                             
                             L 
                           
                           ) 
                         
                       
                     
                   
                   + 
                   
                     j 
                     ⁢ 
                     
                       
                         ∑ 
                         
                           n 
                           = 
                           0 
                         
                         
                           L 
                           - 
                           1 
                         
                       
                       ⁢ 
                       
                         
                           
                             s 
                             i 
                           
                           ⁡ 
                           
                             ( 
                             n 
                             ) 
                           
                         
                         ⁢ 
                         
                           sin 
                           ⁡ 
                           
                             ( 
                             
                               
                                 2 
                                 ⁢ 
                                 π 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 kn 
                               
                               L 
                             
                             ) 
                           
                         
                       
                     
                   
                 
               
             
             
               
                 Eq 
                 . 
                 
                     
                 
                 ⁢ 
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
           
             
               
                 
                     
                 
                 ⁢ 
                 
                   = 
                   
                     
                       
                         X 
                         i 
                       
                       ⁡ 
                       
                         [ 
                         k 
                         ] 
                       
                     
                     + 
                     
                       
                         jY 
                         i 
                       
                       ⁡ 
                       
                         [ 
                         k 
                         ] 
                       
                     
                   
                 
               
             
             
               
                 Eq 
                 . 
                 
                     
                 
                 ⁢ 
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
   
   wherein the complex number Z i [k] represents the result derived from performing the FFT on the sampled data S i (n) of the (i+1) th  ADC i , L being the size of the FFT, and k being any integer between 1 and L/2−1. The size L has no special limitation, but is usually determined to be large enough to ensure a large signal to noise ratio (SNR). 
   The calculation unit  130  collects all complex numbers (Z 0 [k],Z 1 [k], . . . ,Z M−1 [k]) generated by the converting circuit  120  and thereby calculates the arguments (θ 0 , θ 1 , . . . , θ M−1 ) of each complex number. Each argument has information about the timing error of its corresponding ADC  110 . The calculation unit  130  further calculates timing errors of each ADC according to these arguments. If the first ADC 0  establishes the criteria, the timing error dT i  of the (i+1) th  ADC i  can be expressed as: 
   
     
       
         
           
             
               
                 
                   dT 
                   i 
                 
                 = 
                 
                   
                     NT 
                     
                       2 
                       ⁢ 
                       π 
                     
                   
                   ⁡ 
                   
                     [ 
                     
                       
                         
                           ( 
                           
                             
                               θ 
                               i 
                             
                             - 
                             
                               θ 
                               0 
                             
                           
                           ) 
                         
                         
                           mod 
                           ⁡ 
                           
                             ( 
                             
                               2 
                               ⁢ 
                               π 
                             
                             ) 
                           
                         
                       
                       - 
                       
                         
                           
                             2 
                             ⁢ 
                             π 
                           
                           NM 
                         
                         ⁢ 
                         i 
                       
                     
                     ] 
                   
                 
               
             
             
               
                 Eq 
                 . 
                 
                     
                 
                 ⁢ 
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
   
   As a result, the calculation unit  130  will output a number of M−1 timing errors (dT i ,dT 2 , . . . ,dT M−1 ) to the compensation unit  140 . The compensation unit  140  generates a plurality of compensation signals C Ti  according to the M−1 timing errors to respectively compensate ADC 1 ˜ADC M−1 . 
     FIG. 2  shows a correction circuit for a time-interleaved ADC according to a second embodiment of the present invention. The calculation unit  230  collects all complex numbers (Z 0 [k],Z 1 [k], . . . ,Z M−1 [k]) generated by the converting circuit  120  and thereby calculates the modulus (|Z 0 |, | 1 |, . . . , |Z M−1 |) of each complex number. Each modulus has information about the gain error of its corresponding ADC  110 . The calculation unit  230  further calculates gain errors of each ADC according to the modulus. If the first ADC 0  establishes the criteria, the gain error a i  of the (i+1) th  ADC i  can be expressed as: 
   
     
       
         
           
             
               
                 
                   a 
                   i 
                 
                 = 
                 
                   
                     
                        
                       
                         Z 
                         i 
                       
                        
                     
                     - 
                     
                        
                       
                         Z 
                         0 
                       
                        
                     
                   
                   
                      
                     
                       Z 
                       0 
                     
                      
                   
                 
               
             
             
               
                 Eq 
                 . 
                 
                     
                 
                 ⁢ 
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
   
   As a result, the calculation unit  230  will output a number of M−1 gain errors (a 1 ,a 2 , . . . ,a M−1 ) to the compensation unit  240 . The compensation unit  240  generates a plurality of compensation signals C ai  according to the M−1 gain errors to respectively compensate ADC 1 ˜ADC M−1 . Please note that in these two embodiments mentioned above, the criteria can be established utilizing any of the ADCs and is not limited to ADC 0 . 
     FIG. 3  shows a correction circuit for a time-interleaved ADC according to a third embodiment of the present invention. The third embodiment is similar to the first and the second embodiments. After sampling the analog sine wave S, each ADC  110  generates a set of sampled data. In this embodiment, each ADC  110  is coupled to a calculation unit  310 . The calculation unit  310  calculates the average value of every set of sampled data. That is, the calculation unit  310  calculates each set of sample data (S 0 (n), S 1 (n), . . . ,S M−1 (n)) to generate the corresponding average values (b 0 , b 1 , . . . ,b M−1 ). The compensation unit  320  receives these average values and takes a certain ADC, e.g., ADC 0 , as the criteria, the offset error B i  of the (i+1) th  ADC i  can be expressed as:
   B   i   =b   i   −b   0   Eq. (7) 
   As a result, the compensation unit  320  will output a plurality of compensation signals C Bi  according to the M−1 offset errors to correct offsets of ADC 1 ˜ADC M−1 . 
   The detailed circuitry of the converting circuit  120  shown in  FIGS. 1 and 2  is shown in  FIG. 4 . According to the FFT formula of Eq. (3), the sampled data S i (n) are respectively multiplied by 
               cos   ⁡     (       2   ⁢   π   ⁢           ⁢   n     N     )       ⁢           ⁢   and   ⁢           ⁢     sin   ⁡     (       2   ⁢   π   ⁢           ⁢   n     N     )         ,         
and then the products are accumulated. The control signal ctl is shown in  FIG. 5 . After every L data are processed (L is size of the FFT), the accumulated result is cleared; therefore the next round of accumulation will not be affected by the current result. The accumulated result is sampled by a down sampling circuit, and the real part (X i ) and the imaginary part (Y i ) of the complex number Z i  are thereby obtained. A combination of X i  and Y i  generates the complex number Z i =X i +jY i . To further simplify the circuitry, the value N can be set to be 4. Consequently, the multipliers
 
             cos   ⁡     (       2   ⁢   π   ⁢           ⁢   n     N     )       ⁢           ⁢   and   ⁢           ⁢     sin   ⁡     (       2   ⁢   π   ⁢           ⁢   n     N     )       ⁢           ⁢   become   ⁢           ⁢     cos   ⁡     (         2   ⁢   π     4     ⁢   n     )       ⁢           ⁢   and   ⁢           ⁢       cos   ⁡     (         2   ⁢   π     4     ⁢   n     )       .           
In short, the sampled data S i (n) are respectively multiplied by series [1, 0, −1, 0, 1, 0, . . . ] and [0, 1, 0, −1, 0, 1, . . . ]. The circuitry is thereby simplified.
 
   According to Eq. (5), the detailed circuitry of the calculation unit  130  is shown in  FIG. 6 . The argument calculation unit  610  calculates the argument θ i  of the complex number Z i . Then the argument θ i  is compared with an argument of a predetermined ADC, e.g., ADC 0 , and a theoretical phase difference, and is further multiplied by a ratio NT/2π. As a result, the timing error dT i  is obtained. 
   Similarly, According to Eq. (6), the detailed circuitry of the calculation unit  230  is shown in  FIG. 7 . The modulus calculation unit  710  calculates the modulus |Z i | of the complex number Z i . Then the modulus |Z i | is compared with a modulus of a predetermined ADC, e.g., ADC 0 . After normalization, the gain error a i  is obtained. 
   The detailed circuitry of the calculation unit  310  shown in  FIG. 3  is illustrated in  FIG. 8 . It is similar to the converting circuit  120  shown in  FIG. 4 . The sampled data S i (n) are accumulated. After L data are processed, the average of the result is calculated. The average value b i  is the offset of the (i+1) th  ADC i . 
     FIG. 9  shows a calculation circuit  900  that simultaneously calculates the timing error and the gain error to facilitate the operations of the calculation unit  130  and the calculation unit  230 . The complex number is multiplied by a vector e −j2πi/NM  and then multiplied by a complex conjugate, e.g.,  Z 0   , of a predetermined ADC, e.g., ADC 0 . A complex number Z i ′=Z i ·  Z 0   ·e −j2πi/NM  is therefore obtained. Consequently, the timing error dT i  and the gain error ai are respectively estimated by two calculation units  910  and  920 . The formulas utilized by the calculation units  910  and  920  are listed below: 
   
     
       
         
           
             
               
                 
                   a 
                   i 
                 
                 ≈ 
                 
                   
                     Re 
                     ⁢ 
                     
                       { 
                       
                         
                           Z 
                           i 
                           ′ 
                         
                         - 
                         
                           Z 
                           0 
                           ′ 
                         
                       
                       } 
                     
                   
                   
                     Z 
                     0 
                     ′ 
                   
                 
               
             
             
               
                 Eq 
                 . 
                 
                     
                 
                 ⁢ 
                 
                   ( 
                   8 
                   ) 
                 
               
             
           
           
             
               
                 
                   dT 
                   i 
                 
                 ≈ 
                 
                   
                     
                       Im 
                       ⁢ 
                       
                         { 
                         
                           Z 
                           i 
                           ′ 
                         
                         } 
                       
                       × 
                       N 
                     
                     
                       2 
                       ⁢ 
                       π 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       Re 
                       ⁢ 
                       
                         { 
                         
                           Z 
                           i 
                           ′ 
                         
                         } 
                       
                     
                   
                   × 
                   T 
                 
               
             
             
               
                 Eq 
                 . 
                 
                     
                 
                 ⁢ 
                 
                   ( 
                   9 
                   ) 
                 
               
             
           
         
       
     
   
   The first, the second, and the third embodiments described above are for timing error correction, gain error correction, and offset error correction respectively. Ideally, any two of them can be combined to correct two errors at one time. Furthermore, these three embodiments can be combined together to correct all three errors at the same time. 
   Please note that all formulas mentioned above can be transformed to other forms to simplify the calculation. 
   Moreover, to further reduce the complexity of calculation in the digital domain and to simplify the signal generator  101 , the output signal of the signal generator  101  is down converted by R in advance and then is sampled with an R-multiplied sampling frequency. The circuitry for accomplishing this operation is shown in  FIG. 10 . The output signal of the signal generator  101  is down converted by R. The low pass filter (LPF)  1010  filters out the aliasing components generated by the sampling process of the ADC  110  and ensures a high signal-to-noise ratio. The down sampling circuit  1020  down-samples the sampled data with R multiple. As a result, the sampled data S i (n) with the same number are obtained. Then the sampled data S i (n) are processed by the converting circuit  120  or the calculation unit  310 . 
   Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.