Abstract:
A first intermediate frequency amplifier stage which executes the amplitude limiting operation of a double-converting FM tuner employing the integrated circuit technology is constructed in the form of an integrated circuit. An output signal of the first intermediate frequency amplifier stage is put into a square pulse waveform on the basis of the amplitude limiting operation, and therefore has higher harmonic components of high frequencies. When the higher harmonic components are injected into a second mixer circuit in a second frequency converter circuit, various higher harmonic components which have frequencies higher than a second intermediate frequency appear at the output of the second mixer conduit. When the higher harmonic components at the output of the second mixer circuit are injected into an FM demodulator circuit, beat trouble is induced. The second frequency converter circuit is also constructed in the form of an integrated circuit, and filter means to pass the fundamental waves of a first intermediate frequency signal and to reject the higher harmonic frequency components thereof is connected between the output of the first intermediate frequency amlifier stage executing the amplitude limiting operation and the input of the second mixer circuit, whereby the beat trouble can be prevented.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to a double-converting FM tuner. 
     Heretofore, a double-converting FM tuner has been constructed of an antenna, a radio frequency amplifier stage, a first frequency converter circuit composed of a first mixer circuit and a first local oscillator circuit, a first intermediate frequency filter, a first intermediate frequency amplifier stage, a second frequency converter circuit composed of a second mixer circuit and a second local oscillator circuit, a second intermediate frequency filter, and a demodulator circuit. 
     As in the case of the superheterodyne system, the double-converting system is prone to cause beat troubles. This is particularly true where an output signal of the first intermediate frequency amplifier stage is limit-amplified which results in the square pulse output current thereof containing large quantities of higher harmonic components. This leads to the disadvantage that the l-th order higher harmonics of the output current of the first intermediate frequency amplifier stage and the m-th order higher harmonics in the output current of the second local oscillator circuit or the n-th order higher harmonics of the second intermediate frequency give rise to cross modulation in the demodulator circuit. These difficulties appear at the output of the demodulator circuit. (Letters l, m and n denote positive integers.) 
     Usually, the second intermediate frequency filter operates normally at frequencies up to several tens of MHz. For frequencies from several tens of MHz to several hundred MHz, however, a sufficient decay is not attained in the rejection region of the filter on account of the characteristics of circuit components, etc. Accordingly, to inject the output current of the first intermediate frequency amplifier stage containing the large quantities of higher harmonic components directly into the second mixer circuit results in more higher harmonic components than are generated in the second frequency converter circuit when a first intermediate frequency signal not containing such higher harmonic components is supplied. The higher harmonic components increase the quantity of spurious waves to be mixed into the demodulator circuit so that the beat trouble is prone to occur. It has been revealed by the inventor that this phenomenon becomes especially conspicuous when the frequency converter circuits and the demodulator circuit are assembled within an identical semiconductor integrated circuit. 
     SUMMARY OF THE INVENTION 
     This invention has for its object to provide a double-converting FM tuner utilizing the semiconductor integrated circuit technology in which higher harmonic components existant in the square pulse waveform output of a first intermediate frequency amplifier stage executing a limit-amplifying operation are prevented from being mixed into a demodulator. The resultant tuner is free from beat troubles. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 shows circuit blocks of a double-converting FM tuner embodying this invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Hereunder, a preferred embodiment of this invention will be described. 
     Referring to FIG. 1, numeral 1 designates an antenna, numeral 2 an RF (radio frequency) amplifier stage, numeral 3 a first mixer circuit, numeral 4 a first local oscillator circuit, numeral 5 a first IF (intermediate frequency) filter, numeral 6 a first IF amplifier stage, numeral 7 a second mixer circuit, numeral 8 a second local oscillator circuit, numeral 9 a second IF filter, numeral 10 a detector circuit, and numeral 11 an additional first IF filter which resonates with a first intermediate frequency. A first frequency converter circuit is constructed of the first mixer circuit 3 and the first local oscillator circuit 4, while a second frequency converter circuit is constructed of the second mixer circuit 7 and the second local oscillator circuit 8. Shown at 12 is a limiting amplifier circuit which limit-amplifies a signal voltage applied to the detector circuit 10. 
     The RF amplifier stage 2 subjects to voltage amplification an FM radio frequency signal which has been received by the antenna 1. The first mixer circuit 3 effects the frequency mixing between an amplified FM radio frequency output signal at the output of the RF amplifier stage 2 and a first local oscillation output signal at the output of the first local oscillator circuit 4, thereby to transmit a first intermediate frequency signal of 10.7 MHz to the first IF filter 5. Preferably, the first IF filter 5 is constructed of an intermediate frequency transformer and a ceramic filter, and it has a predetermined frequency band width. 
     The first IF amplifier stage 6 to which the first IF signal of 10.7 MHz is applied includes three stages of cascaded differential amplifier circuits 60, 61 and 62 and a voltage regulator 63. It is formed within a single silicon semiconductor substrate by the well-known techniques for manufacturing semiconductor integrated circuits. The first semiconductor integrated circuit which includes the first IF amplifier stage 6 is indicated by broken lines l 1 . The two differential inputs 600 and 601 of the first-stage differential amplifier circuit 60 are respectively connected to input terminals P 18  and P 19  of the first semiconductor integrated circuit, and are connected with each other through a resistor R 1 . The 601 input of the two differential inputs is A.C. grounded A.C.-wise by a capacitor C 1 . The two differential outputs 602 and 603 of the first-stage differential amplifier circuit 60 are respectively applied to the two differential inputs 610 and 611 of the second-stage differential amplifier circuit 61 through internal interconnections inside the first semiconductor integrated circuit. Likewise, the two differential outputs 612 and 613 of the second-stage differential amplifier circuit 61 are respectively applied to the two differential inputs 620 and 621 of the third-stage differential amplifier circuit 62 through internal interconnections inside the first semiconductor integrated circuit. Further, the two differential outputs 622 and 623 of the third-stage differential amplifier circuit 62 are respectively applied to output terminals P 20  and P 21  of the first semiconductor integrated circuit through internal interconnections inside this integrated circuit. 
     According to the principle of this invention, the additional first IF filter 11 is especially connected between the output terminal P 20  of the first IF amplifier stage 6 and an input terminal P 15  of the second frequency converter circuit. 
     As this first IF filter 11, there can be used a filter which passes the first intermediate frequency of 10.7 MHz therethrough and which rejects the higher harmonic frequency components of the first intermediate frequency, for example, a resonance circuit whose resonance frequency is the first intermediate frequency. 
     In order to avoid the undesirable RF signal crosstalk between the second frequency converter circuit or the detector circuit 10 and the first IF amplifier stage 6, according to the preferred embodiment of this invention, the detector circuit 10 and the second frequency converter circuit made up of the second mixer circuit 7 and the second local oscillator circuit 8 are formed within a second semiconductor integrated circuit which employs another silicon semiconductor substrate different from the silicon semiconductor substrate of the first semiconductor integrated circuit. The second semiconductor integrated circuit is indicated by broken lines l 2 . 
     The second mixer circuit 7 executes the frequency mixing between an amplified first IF signal of 10.7 MHz provided at the input terminal P 15  of the second semiconductor integrated circuit through the first IF filter 11 and a second local oscillation output signal of 8.735 MHz at an output 80 of the second local oscillator circuit 8, thereby to transmit a second intermediate frequency signal of 1.965 MHz to a terminal P 1  of the second semiconductor integrated circuit. The oscillation frequency of the second local oscillator circuit 8 is determined by capacitors C 5  and C 6  and inductors L 5  and L 6  of a frequency selector circuit 15 which is connected between terminals P 16  and P 17 . The second IF filter 9 which has a passing band width of 1 MHz-4 MHz is connected between the terminal P 1  and another terminal P 4 . 
     A second IF signal provided at the terminal P 4  has a substantially sinusoidal waveform. It is amplified by the limiting amplifier 12 formed within the second semiconductor integrated circuit and having a high voltage gain, with the result that it is converted into a square pulse waveform. The second IF signal in the square pulse waveform at the output of the limiting amplifier 12 is applied to the pulse count type FM detector 10 which is also formed within the second semiconductor integrated circuit. The pulse count type FM detector 10 is constructed of a trigger circuit 100, a monostable multivibrator 110, an inverter 120, a capacitor C 2  which is connected between an output terminal P 9  of the monostable multivibrator 110 and an input terminal P 10  of the inverter 120 outside the second integrated circuit, and a resistor R 2  which is connected between the terminal P 10  and a terminal P 11 . 
     The trigger circuit 100 transmits to the monostable multivibrator 110 a trigger pulse of narrow pulse width on the basis of the second IF signal in the square pulse waveform. The monostable multivibrator 110 is driven by the trigger pulse, and transmits to the inverter 120 a pulse signal having a fixed pulse width which is a decided by the time constant between the capacitor C 2  and the resistor R 2 . A square pulse signal of the fixed pulse width having pulse intervals corresponding to the FM modulation is provided at an output terminal P 8  of the inverter 120. By connecting appropriate smoothing means to the terminal P 8 , and FM demodulation output signal is obtained. 
     On the one hand, the overall voltage gain of the three stages of differential amplifier circuits 60, 61 and 62 constituting the first IF amplifier stage 6 is sufficiently high, so that the first IF signal applied to the terminal P 18 , having the sinusoidal waveform of 10.7 MHz, is sufficiently amplified by the first IF amplifier stage 6. The amplified first IF signal to be provided at the output terminals P 20  and P 21  is accordingly clipped in a square pulse waveform. Thus, the first IF amplifier stage 6 operates as an amplitude-limiting amplifier. Any undesired AM signal component contained in the received FM signal can be removed owing to the amplitude-limiting operation of the first IF amplifier stage 6. 
     However, the amplified first IF signal of 10.7 MHz in the square pulse waveform as obtained at the terminal P 20  has the fundamental wave component of 10.7 MHz and higher harmonic components of higher frequencies. 
     Thus, on the other hand, the first IF filter 11 which passes the first intermediate frequency of 10.7 MHz therethrough and which stops the passage of the higher harmonic frequencies is connected between the output terminal P 20  of the first IF amplifier stage 6 and the input terminal P 15  of the second frequency converter circuit. Therefore, the higher harmonic components in the output of the first IF amplifier stage, 6 which creates the beat trouble, are removed by the first IF filter 11, and the higher harmonic components to be injected into the detector circuit 10 can be sufficiently reduced so that cross modulation is prevented. 
     Further, in case where the FM demodulator circuit 10 is of the pulse count type, a large detection current responsive to the second IF signal flows through this demodulator circuit. In general, an internal interconnection inside a semiconductor integrated circuit is formed of an evaporated metallic thin film and therefore has an equivalent resistance value which is not negligible. In contrast, an external interconnection to be connected outside the semiconductor integrated circuit exhibits only an equivalent resistance of a negligibly small value because a metal wire of high conductivity can be utilized. 
     The large detection current flows through a supply voltage-feeding internal interconnection and a grounding internal interconnection for the FM demodulator circuit 10. In consequence, voltage drops which respond to the second IF signal of 1.965 MHz and which are not negligible appear in these internal interconnections inside the semiconductor integrated circuit. 
     If the supply voltage-feeding internal interconnection or grounding internal interconnection of the FM demodulator circuit 10 is connected in common with a supply voltage-feeding internal interconnection or grounding internal interconnection for the second frequency converter circuit by means of an internal interconnection inside the semiconductor integrated circuit, the voltage drop which is not negligible as stated above will be transmitted to the supply voltage-feeding internal interconnection or grounding internal interconnection of the second frequency converter circuit. 
     Further, if the supply voltage-feeding internal interconnection or grounding internal interconnection of the FM demodulator circuit 10 is connected in common with a supply voltage-feeding internal interconnection or grounding internal interconnection for the first IF amplifier stage 6 by means of an internal interconnection inside the semiconductor integrated circuit, the voltage drop which is not negligible as stated above will be transmitted to the internal interconnection quite similarly. 
     The transmissions of the voltage drops which respond to the second intermediate frequency of 1.965 MHz and which are not negligible will give rise to the cross modulation between the transmitted signal of 1.965 MHz and the first IF signal of 10.7 MHz inside the first IF amplifier stage 6, and will give rise to the composite cross modulation among the transmitted signal of 1.965 MHz, the first IF signal of 10.7 MHz and the second local oscillation signal of 8.735 MHz inside the second frequency converter circuit. These cross modulations will generate higher harmonic signal components of high frequencies which similarly form the cause of beat trouble, at the output terminal P 20  of the first IF amplifier stage 6 and the output terminal P 1  of the second mixer circuit 7. 
     According to the preferred embodiment of this invention, in order to avoid the cross modulations, the transmissions of the undesired voltage drops above described are prevented. More specifically, a supply voltage-feeding internal interconnection 102 and a grounding internal interconnection 103 for the FM demodulator circuit 10 and the limiting amplifier circuit 12 are respectively connected to a supply voltage-feed terminal P 12  and a ground terminal P 14  of the second semiconductor integrated circuit. The supply voltage-feed terminal P 12  and the ground terminal P 14  are respectively connected to a common power supply terminal 15 and the ground point GND through external interconnections. A voltage regulator 14 is arranged between the supply voltage-feed terminal P 12  and the supply voltage-feeding internal interconnection 102, and delivers to a terminal 141 an operating voltage which is substantially constant against fluctuations in a voltage V cc  supplied to the common power supply terminal 16. A ground terminal 143 of the voltage regulator 14 is also connected to the ground terminal P 14  of the second semiconductor integrated circuit through an internal interconnection. 
     A supply voltage-feeding internal interconnection 782 and a grounding internal interconnection 783 of the second frequency converter circuit, namely, the second mixer circuit 7 and the second local oscillator circuit 8 are respectively connected to another supply voltage feed terminal P 3  and another ground terminal P 2  of the second semiconductor integrated circuit. The ground terminal P 2  is connected to the ground point GND through an external interconnection. A voltage regulator 13 is arranged between the supply voltage-feeding terminal P 3  and the supply voltage-feeding internal interconnection 782, and delivers a substantially constant operating voltage to a terminal 131. A ground terminal 133 of this voltage regulator 13 is also connected to the ground terminal P 2  of the second semiconductor integrated circuit through an internal interconnection. 
     The first IF amplifier stage 6 is formed within the first semiconductor integrated circuit as stated above, and a supply voltage-feeding internal interconnection 64 and a grounding internal interconnection 65 thereof are respectively connected to a supply voltage-feed terminal P 22  and a ground terminal P 23  of the first semiconductor integrated circuit. The ground terminal P 23  is connected to the ground point GND through an external interconnection. A voltage regulator 63 is arranged between the supply voltage feed terminal P 22  and the supply voltage-feeding internal interconnection 64, and delivers a substantially constant operating voltage to a terminal 631 similarly to the above. A ground terminal 633 of the voltage regulator 63 is also connected to the ground terminal P 23  of the first semiconductor integrated circuit through an internal interconnection. 
     More preferably, a filter composed of an inductor L 3  and a capacitor C 3  and a filter composed of an inductor L 4  and a capacitor C 4  are respectively connected between the supply voltage-feed terminal P 12  and the supply voltage-feed terminal P 3  and between the former terminal P 12  and the supply voltage-feed terminal P 22 . Thus, the transmissions of the voltages responsive to the detection current previously stated can be further reduced.