Abstract:
A CMOS latch with improved immunity to soft errors resulting from energetic particle strikes is disclosed. In one embodiment two Schmitt triggers are cross-coupled to hold a logic state. The significant hysteresis of the Schmitt triggers improves the resistance of the latch to induced soft errors. In a further embodiment, the Schmitt triggers operate by providing feedback from the Schmitt trigger output that changes the effective impedance of both the pullup and pulldown networks of the Schmitt trigger thereby creating significant hysteresis. In another embodiment, the Schmitt triggers operate by providing feedback from the Schmitt trigger output that changes the effective impedance of only one of either the pullup or pulldown network of the Schmitt trigger thereby creating significant hysteresis.

Description:
FIELD OF THE INVENTION  
         [0001]    This invention relates generally to CMOS integrated circuits and more particularly to a circuit for storing a digital state that has improved resistance to soft errors.  
         BACKGROUND OF THE INVENTION  
         [0002]    Natural background radiation, such as alpha particles and neutrons, can corrupt data stored in memory elements producing what is referred to as “soft errors.”When a particle strikes a diffusion layer of a field-effect transistor (FET), it generates electron-hole pairs. Electrons generated by this strike may then be collected at a node causing it to discharge thereby changing the state of the memory element or latch. Circuits constructed in advanced semiconductor technologies, such as those using gate widths less than 0.25 microns, are more susceptible to these soft errors. Accordingly, to ensure the reliability of integrated circuits, including microprocessors, there is a need for an improved latch circuit that has improved resistance to radiation induced soft errors.  
         SUMMARY OF THE INVENTION  
         [0003]    A CMOS latch with improved immunity to soft errors resulting from energetic particle strikes is provided. In one embodiment two Schmitt triggers are cross-coupled to hold a logic state. The significant hysteresis of the Schmitt triggers improves the resistance of the latch to induced soft errors. In a further embodiment, the Schmitt triggers operate by providing feedback from the Schmitt trigger output that changes the effective impedance of both the pullup and pulldown networks of the Schmitt trigger thereby creating significant hysteresis. In another embodiment, the Schmitt triggers operate by providing feedback from the Schmitt trigger output that changes the effective impedance of only one of either the pullup or pulldown network of the Schmitt trigger thereby creating significant hysteresis. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0004]    [0004]FIG. 1 is a schematic diagram illustrating one embodiment of the present invention.  
         [0005]    [0005]FIG. 2 is a schematic diagram illustrating a second embodiment of the present invention.  
         [0006]    [0006]FIG. 3 is a schematic diagram illustrating a third embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0007]    [0007]FIG. 1 is a schematic diagram illustrating one embodiment of the present invention. In FIG. 1, a pass-gate  102  comprised of an NFET (n-channel field-effect transistor) is connected between an input node, IN, and a keeper and output node, OUT. Pass-gate  102  is controlled by a signal CK. The input to Schmitt trigger  104  is also connected to keeper node OUT. The output of Schmitt trigger  104  is connected to feedback node  108 . The input to Schmitt trigger  106  is connected to feedback node  108 . The output of Schmitt trigger  106  is connected to keeper node OUT.  
         [0008]    Pass-gate  102  either lets data flow through pass-gate  102  to setting the latch high or low, or pass-gate  102  blocks data from flowing allowing the feedback provided by Schmitt trigger  104  and  106  to hold keeper node OUT at either a high or low value. The Schmitt triggers  104  and  106  add hysteresis, when compared to conventional inverters, to the feedback path used to hold keeper node OUT at its value. This added hysteresis reduces the probability that a particle strike will change the value of the latch thereby making the latch of FIG. 1 more radiation resistant than a conventional CMOS latch.  
         [0009]    The replacement of one or more of the feedforward, feedback, or both inverters by Schmitt triggers may be done on other latch configurations or topologies. By utilizing Schmitt triggers to add hysteresis in these other latch configurations or topologies, these other configurations or topologies may have their resistance to radiation improved. For example, some latch designs use the feedback node  108  as an input to an output inverter instead of taking the keeper node and using it as the output node as shown in FIG. 1. By replacing one or more of the feedforward or feedback inverters in this latch design, the radiation resistance of this latch design may be improved. It is contemplated that the radiation resistance of any latch design may be improved in a manner consistent with the invention by replacing one or more inverters with Schmitt trigger.  
         [0010]    [0010]FIG. 2 is a schematic diagram illustrating a second embodiment of the present invention. In FIG. 2, a pass-gate  206  comprised of an NFET and a PFET (p-channel field-effect transistor) is connected between an input node, IN, and a keeper node IN 1 . Pass-gate  206  is controlled by a signal CK and a complement of CK, CKN that is generated from CK by inverter  208 . The input to Schmitt trigger  204  is connected to keeper node IN 1 . The output of Schmitt trigger  204  is connected to feedback node FB. The input to Schmitt trigger  202  is connected to feedback node FB. The output of Schmitt trigger  202  is connected to keeper node IN 1 . Keeper node IN 1  is also connected to the input of inverter  210 . The output of inverter  210  is connected to output node OUT.  
         [0011]    Schmitt trigger  204  is comprised of NFETs  212 ,  214 , and  234  and PFETs  216 ,  218 , and  236 . The gates of FETs  212 ,  214 ,  216 , and  218  are all connected to the input of Schmitt trigger  204 —keeper node IN 1 . The source of PFET  218  is connected to a positive supply voltage. The drain of PFET  218  is connected to node A 1 . Node A 1  is also connected to the sourced of PFETs  216  and  236 . The drain of PFET  216  is connected to the output of Schmitt trigger  204 —feedback node FB. The drain of PFET  236  is connected to a negative supply voltage. The gate of PFET  236 , the gate of NFET  234 , and the drain of NFET  214  are also connected to node FB. The source of NFET  214  is connected to node A 2 . The source of NFET  234  and the drain of NFET  212  are also connected to node A 2 . The source of NFET  212  is connected to a negative supply voltage. The drain of NFET  234  is connected to a positive supply voltage.  
         [0012]    Schmitt trigger  202  is comprised of NFETs  220 ,  222 ,  224  and  232  and PFETs  226 ,  228  and  230 . The gates of FETs  220 ,  222 ,  224 ,  226 , and  228  are connected to the input of Schmitt trigger  202 —feedback node FB. The source of PFET  228  is connected to a positive supply voltage. The drain of PFET  228  is connected to node B 1 . Node B 1  is also connected to the sourced of PFETs  226  and  230 . The drain of PFET  226  is connected to the output of Schmitt trigger  202 —keeper node IN 1 . The drain of PFET  230  is connected to a negative supply voltage. The gate of PFET  230 , the gate of NFET  232 , and the drain of NFET  224  are also connected to node IN 1 . The source of NFET  224  is connected to node B 3 . The gate of NFET  224  is connected to node CKN. The drain of NFET  222  is connected to node B 3 . The source of NFET  222  is connected to node B 2 . The source of NFET  232  and the drain of NFET  220  are also connected to node B 2 . The source of NFET  220  is connected to a negative supply voltage. The drain of NFET  232  is connected to a positive supply voltage.  
         [0013]    Pass-gate  206  either lets data flow through pass-gate  206  to setting the latch high or low, or pass-gate  206  blocks data from flowing allowing the feedback provided by Schmitt trigger  204  and  202  to hold keeper node IN 1  at either a high or low value. The Schmitt triggers  204  and  202  add hysteresis, when compared to conventional inverters, to the feedback path used to hold keeper node IN 1  at its value. This added hysteresis reduces the probability that a particle strike will change the value of the latch thereby making the latch of FIG. 2 more radiation resistant than a conventional CMOS latch. In the embodiment shown in FIG. 2, NFET  234  and PFET  236  are used to add hysteresis to Schmitt trigger  204 . Likewise, NFET  232  and PFET  230  add hysteresis to Schmitt trigger  202 . NFETs  232  and  234  operate to provide feedback from the output of Schmitt triggers  202  and  204 , respectively, that changes the effective impedance of the pulldown networks in Schmitt triggers  202  and  204 , respectively. Likewise, PFETs  230  and  236  operate to provide feedback from the output of Schmitt triggers  202  and  204 , respectively, that changes the effective impedance of the pullup networks in Schmitt triggers  202  and  204 , respectively. In another embodiment, one of more of NFETs  232  and  234  and/or PFETs  236  and  230  may be removed. These embodiments should cost less (because they may be fabricated using less area) and have shorter setup and hold times than the embodiment shown in FIG. 2. An example embodiment with NFETs  232  and  234  removed is shown in FIG. 3. The embodiment shown in FIG. 3 changes only the resistance ratio of the pullup network. However, a Schmitt trigger that only changes the resistance ratio of the pulldown network may also be constructed.  
         [0014]    [0014]FIG. 3 is a schematic diagram illustrating a third embodiment of the present invention. In FIG. 3, a pass-gate  306  comprised of an NFET and a PFET is connected between an input node, IN, and a keeper node IN 1 . Pass-gate  306  is controlled by a signal CK and a complement of CK, CKN that is generated from CK by inverter  308 . The input to Schmitt trigger  304  is connected to keeper node IN 1 . The output of Schmitt trigger  304  is connected to feedback node FB. The input to Schmitt trigger  302  is connected to feedback node FB. The output of Schmitt trigger  302  is connected to keeper node IN 1 . Keeper node IN 1  is also connected to the input of inverter  310 . The output of inverter  310  is connected to output node OUT.  
         [0015]    Schmitt trigger  304  is comprised of NFET  314  and PFETs  316 ,  318 , and  336 . The gates of FETs  314 ,  316 , and  318  are all connected to the input of Schmitt trigger  304 —keeper node IN 1 . The source of PFET  318  is connected to a positive supply voltage. The drain of PFET  318  is connected to node A 1 . Node A 1  is also connected to the source of PFETs  316  and  336 . The drain of PFET  316  is connected to the output of Schmitt trigger  304 —feedback node FB. The drain of PFET  336  is connected to a negative supply voltage. The gate of PFET  336  and the drain of NFET  314  are connected to node FB. The source of NFET  314  is connected to node a negative supply voltage.  
         [0016]    Schmitt trigger  202  is comprised of NFETs  322 , and  324  and PFETs  326 ,  328  and  330 . The gates of FETs  322 ,  326 , and  328  are connected to the input of Schmitt trigger  302 —feedback node FB. The source of PFET  328  is connected to a positive supply voltage. The drain of PFET  328  is connected to node B 1 . Node B 1  is also connected to the source of PFETs  326  and  330 . The drain of PFET  326  is connected to the output of Schmitt trigger  302 —keeper node IN 1 . The drain of PFET  330  is connected to a negative supply voltage. The gate of PFET  330  and the drain of NFET  324  are connected to node IN 1 . The source of NFET  324  is connected to node B 3 . The gate of NFET  324  is connected to node CKN. The drain of NFET  322  is connected to node B 3 . The source of NFET  322  is connected to a negative supply voltage.  
         [0017]    Pass-gate  306  either lets data flow through pass-gate  306  to setting the latch high or low, or pass-gate  306  blocks data from flowing allowing the feedback provided by Schmitt trigger  304  and  302  to hold keeper node IN 1  at either a high or low value. PFETs  330  and  336  operate to provide feedback from the output of Schmitt triggers  302  and  304 , respectively, that changes the effective impedance of the pullup networks in Schmitt triggers  302  and  304 , respectively. The Schmitt triggers  304  and  302  add hysteresis, when compared to conventional inverters, to the feedback path used to hold keeper node IN 1  at its value. This added hysteresis reduces the probability that a particle strike will change the value of the latch thereby making the latch of FIG. 3 more radiation resistant than a conventional CMOS latch but because it has fewer transistors it may be constructed in less area than the latch shown in FIG. 2. This reduces cost. Also, the embodiments that only change the effective impedance of one of either the pullup or pulldown networks tend to have shorter setup and hold times.