Abstract:
Serial data signal receiver circuitry for inclusion on a PLD includes a plurality of equalizer circuits that are connected in series and that are individually controllable so that collectively they can compensate for a wide range of possible input signal attenuation characteristics. Other circuit features may be connected in relation to the equalizer circuits to give the receiver circuitry other capabilities. For example, these other features may include various types of loop-back test circuits, controllable termination resistance, controllable common mode voltage, and a controllable threshold for detection of an input signal. Various aspects of control of the receiver circuitry may be programmable.

Description:
[0001]     This application claims the benefit of U.S. provisional patent application No. 60/705,689, filed Aug. 3, 2005, which is hereby incorporated by reference herein in its entirety. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     This invention relates to programmable logic devices (“PLDs”) and other integrated circuits of that general type (all generically referred to for convenience as PLDs). More particularly, the invention relates to high-speed serial data receiver circuitry for inclusion on PLDs.  
         [0003]     PLDs are intended as relatively general-purpose devices. A PLD can be programmed (configured) to meet any need within the range of needs that the PLD is designed to support. A PLD may be equipped with high-speed serial data communication circuitry, whereby the PLD can transmit serial data to and/or receive serial data from circuitry that is external to the PLD. In that case, it is desirable for the high-speed serial data communication circuitry of the PLD to be able to support various communication protocols that various users of the PLD product may wish to employ. It is also desirable for the PLD&#39;s high-speed serial data communication circuitry to be able to perform successfully in various circuit or system contexts. This invention provides high-speed serial data receiver circuitry that can be configured to meet a wide range of possible needs.  
       SUMMARY OF THE INVENTION  
       [0004]     Serial data signal receiver circuitry in accordance with the invention includes a plurality of equalizer circuits that are connected in series and that are individually controllable so that collectively they can compensate for any of a wide range of possible input signal attenuation characteristics. Other circuit features may be connected in relation to the equalizer circuits to give the receiver circuitry other capabilities. For example, these other features may include various types of loop-back test circuits, controllable termination resistance, controllable common mode voltage, and a controllable threshold for detection of an input signal. Various aspects of control of the receiver circuitry may be programmable.  
         [0005]     Further features of the invention, its nature and various advantages, will be more apparent from the accompanying drawings and the following detailed description. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0006]      FIG. 1  is a simplified graph of several signal attenuation characteristics that are useful in explaining certain aspects of the invention.  
         [0007]      FIG. 2  is a simplified schematic block diagram of an illustrative embodiment of circuitry in accordance with the invention.  
         [0008]      FIG. 3  is a simplified graph of several illustrative frequency response characteristics that are achievable in accordance with the invention.  
         [0009]      FIG. 4  is a more detailed, but still simplified, schematic block diagram of portions of what is shown in  FIG. 2 .  FIG. 4  is again for an illustrative embodiment of the invention.  
         [0010]      FIG. 5  is a simplified block diagram of an illustrative embodiment of a representative portion of the circuitry shown in  FIG. 4 .  
         [0011]      FIG. 6  is a simplified schematic block diagram of an illustrative embodiment of optional circuitry in accordance with the invention. 
     
    
     DETAILED DESCRIPTION  
       [0012]     Transceiver design becomes more complicated as the data rate keeps increasing. For example, increased data rates typically result in degradation of signal integrity across the transmission medium. The design of the signal receiver is very important to the task of recovering a poor quality signal from a lossy interconnect, especially at high frequencies. In the area of field-programmable gate arrays (“FPGAs” (another term for PLDs)) it is desirable for a receiver to be able to support a wide range of possible applications. The receivers of this invention address issues related to signal integrity and special features.  
         [0013]     With regard to signal integrity, on the transmitter side, pre-emphasis can be used to help “open the eye” of the signal at the receiver (see, for example, commonly assigned, co-pending, Tran et al. U.S. patent application Ser. No. ______, filed Feb. 1, 2006 (Attorney Docket 174/426 (A2184)) for transmitter circuitry that is capable of giving a transmitted signal pre-emphasis). However, two much pre-emphasis can cause cross-talk. Each PLD user&#39;s board design (e.g., printed circuit board or back-plane design) also has different characteristics. For example,  FIG. 1  plots just a few representative back-plane attenuation curves from typical applications. It will be noted that the pole location of each curve is not the same, and that different slopes are observed in different ranges of frequency.  
         [0014]     With regard to special features, it is desirable for many communication protocols to provide loss-of-signal detection. Also, the communication protocol known as PCI-E is an example of a protocol that requires a receiver to have an electrical idle capability.  
         [0015]      FIG. 2  shows an illustrative embodiment of high-speed serial data receiver circuitry  10  in accordance with the invention. For example, circuitry  10  may be designed to operate at data rates up to approximately 6 Gbps (giga-bits per second). It is emphasized that in a PLD context, receiver circuitry  10  is preferably able to operate at any frequency in a fairly wide range of frequencies, and that 6 Gbps is just one example of a data rate that may be in the operating range of the receiver. In other embodiments of the invention the operating range may be different and may not include 6 Gbps.  
         [0016]     As shown in  FIG. 2 , circuitry  10  includes equalization block  20 , signal detect block  30 , termination block  40 , common mode driver block  50 , serial loop-back buffer  60 , and diagnostic loop-back buffer  70 .  
         [0017]     The main function of equalization block  20 , which is preferably programmable to at least some degree, is to reduce demands on the larger receiver circuitry of the associated PLD. This larger receiver circuitry, which may include clock and data recovery (“CDR”) circuitry downstream from circuitry  10 , needs to convert the incoming serial data signal into digital signal levels without error. Examples of error sources are inter-symbol interference (“ISI”) and reduced signal-to-noise ratio (“SNR”), which are often characteristics of high-frequency signal attenuation. Equalizer  20  preferably does not require any initial training sequence.  FIG. 3  shows several examples of the many possible frequency responses of equalizer  20  over a wide range of frequencies. As  FIG. 3  shows, the gain of equalizer  20  is selectable to have any of many different possible levels, from a very low gain (which is useful in a short interconnect, chip-to-chip application) to a high gain (which may be required for a back-plane application with loss curves like those shown in  FIG. 1 ). The signals EQ_CTRL[n:0] provide setting selection for equalizer  20 , where n can be a number large enough to permit representation of as many as a few thousand different control values. Signals EQ_CTRL may come from programmable memory on the PLD (so-called configuration random access memory or CRAM). A possible alternative to CRAM control is mentioned later in this specification.  
         [0018]     To counteract poles of different back-planes having different locations, the zero location in circuitry  20  is flexible. Up to about 8 Gbps, a fourth-order function will curve fit the typical attenuation curve.  FIG. 4  therefore shows an illustrative embodiment of equalizer block  20  that includes four stages  110 ,  120 ,  130 , and  140  to introduce four zeros to cancel out the possibility of as many as four poles in the back-plane. A generalized depiction that can apply to any one of equalizer stages  110 ,  120 ,  130 , or  140  is shown in  FIG. 5 . This FIG. shows that each equalizer stage can have the following controllably variable parameters: (1) DC gain, (2) AC gain, (3) slope, (4) low frequency limit Wz, and (5) high frequency limit Wp. The values of these various parameters are determined by control input signals EQ_CTRL[m:0] and DC_CTRL[a:0]. Again, the EQ_CTRL and DC_CTRL signals may come from CRAM (or another possible alternative that is mentioned later).  
         [0019]      FIG. 4  also shows preferred locations for other blocks to connect to equalizer circuitry  20  to enhance performance by the distribution of load. For example,  FIG. 4  shows that the outputs of loop-back buffer  60  are preferably applied to the inputs of the last stage  140  of equalizer circuitry  20 . (The inputs to loop-back buffer  60  come from serial data transmitter circuitry on the PLD that includes circuitry  10 . The loop-back path through buffer  60  can be used to test the transmitter path circuitry of the PLD.) As another example,  FIG. 4  shows that the inputs of loop-back buffer  70  preferably come from the outputs of the final stage  140  of equalization circuitry  20 . (The outputs of loop-back buffer  70  are applied to transmitter circuitry on the PLD that includes circuitry  10 . This loop-back path can be used to send a signal back to the source of the serial data input to circuitry  10  to enable that source to test its link to circuitry  10 , as well as the ability of circuitry  10  to deal with the signal it has received.) As still another example,  FIG. 4  shows how the paths to the CDR circuitry and adaptive dispersion compensation engine (“ADCE”) circuitry  150  are preferably split. In particular, this is preferably done upstream from the final stage  140  of equalizer circuitry  20 , and with the addition of a dummy equalizer stage  160  in ADCE circuitry  150  to reduce/balance the load to the four stages  110 ,  120 ,  130 , and  140  of circuitry  20 . (ADCE circuitry  150  may be used in conjunction with the receiver circuitry to determine proper settings for the equalizer automatically, instead of “manually” controlling the EQ_CTRL[n:0] signals. Thus ADCE control of EQ_CTRL is a possible alternative to CRAM control of EQ_CTRL.  FIG. 6  (described below) shows an example of how this may be implemented on a PLD that includes circuitry  10 .) As shown in  FIG. 5 , circuitry  20  also has DC gain options that are preferably applied only to the first two stages  110  and  120  to reduce offset. Such offset may be due to process mismatch, layout-dependent offset, random offset, or the like. All stages  110 ,  120 ,  130 , and  140  may be the same or substantially the same (e.g., as shown in  FIG. 5 ), but the DC_CTRL for stages  130  and  140  may be hard-wired to 0.  
         [0020]     Another feature that circuitry  10  preferably includes is on-chip termination that can be calibrated to offset variation due to PVT (process, voltage, temperature). This feature is provided by variable resistors  42   a  and  42   b , which are connected in series between the two differential inputs to equalizer circuitry  20 . The combined value of resistors  42   a  and  42   b  can be selected to achieve a balance between accuracy of the termination impedance and the load on the input pins to enhance performance. For example, the signal(s) TERM_CTRL in  FIG. 2  may allow selection of a 100, 120, or 150 ohm differential between the inputs to equalizer circuitry  20 . In this example, each of resistors  42  is controllable to have resistance of 50, 60, or 75 ohms. The signal(s) TERM_CTRL may come from CRAM (similar to CRAM described earlier in this specification) to make the value of the termination resistance programmably selectable.  
         [0021]     Circuitry  10  also preferably provides a low impedance termination path to common mode voltage (i.e., at the node between resistors  42   a  and  42   b ). In addition, this voltage is preferably programmable for selection of the level required to support any of several communication protocols. Voltage source  50  is controlled by signal(s) VTT_CTRL to provide the desired common mode voltage offset from ground. The VTT_CTRL signal(s) may come from CRAM (again similar to CRAM described earlier in this specification).  
         [0022]     With regard to signal detect circuitry  30  in  FIGS. 2 and 4 , different communication protocols have different specifications for the permitted minimum differential input level. The control bit(s) SD_THRESH allow selection of different threshold levels for different specifications. Once again, SD_THRESH may come from CRAM (similar to CRAM described earlier) to make the minimum differential input level required by circuitry  30  programmable. The output signal of circuitry  30  indicates whether or not that required minimum differential input level is present. This output signal is applied to the physical coding sublayer (PCS) of the PLD, and possibly from there to other circuitry of the PLD.  
         [0023]     Signal detect circuitry  30  can be used to support an “electrical idle” mode. Circuitry  30  can flag entering into and exiting out of electrical idle state by detecting the presence or absence of a signal presented at the receiver input pin. If that signal is below a threshold (e.g., SD_THRESH), that means there is no signal or idle. If the signal is above the threshold, that means the associated transmitter is in transmitting state (i.e., out of idle).  
         [0024]     Various testability features that are preferably provided by circuitry  10  have already been mentioned, but will now be discussed further. A bypass mode of transmitter circuitry (not shown) on the PLD that includes circuitry  10  can be done through serial loop-back buffer  60 . It is also possible to bypass the CRD circuitry to check the quality of equalizer  20 . This is done through diagnostic loop-back buffer  70 .  
         [0025]      FIG. 6  illustrates the point that—if it is desired to provide such a feature on the PLD—the EQ_CTRL signals can come either from CRAM  210  on the PLD or from ADCE circuitry  150  on the PLD. Multiplexer (“mux”) circuitry  220  selects which of these two possible sources is used. The choice made by mux  220  may be programmably controlled by additional CRAM  230 .  
         [0026]     From the foregoing it will be appreciated that the serial data signal receiver architecture of this invention is capable of satisfying a wide range of applications. This architecture enhances performance while avoiding the overhead of carrying too many supporting features.