Abstract:
A layout pattern of an implant layer includes at least a linear region and at least a non-linear region. The linear region includes a plurality of first patterns to accommodate first dopants and the non-linear region includes a plurality of second patterns to accommodate the first dopants. The linear region abuts the non-linear region. Furthermore, a pattern density of the first patterns in the linear region is smaller than a pattern density of the second patterns in the non-linear region.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This is a continuation application of U.S. patent application Ser. No. 13/407,722, filed on Feb. 28, 2012, and all benefits of such earlier application are hereby claimed for this new continuation application. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a high voltage metal-oxide-semiconductor (hereinafter abbreviated as HV MOS) device and a layout patterned thereof, and more particularly, to a high voltage lateral double-diffused metal-oxide-semiconductor (HV-LDMOS) device and a layout patterned thereof. 
     2. Description of the Prior Art 
     Double-diffused MOS (DMOS) transistor devices have drawn much attention in power devices having high voltage capability. The conventional DMOS transistor devices are categorized into vertical double-diffused MOS (VDMOS) transistor device and lateral double-diffused MOS (LDMOS) transistor device. Having advantage of higher operational bandwidth, higher operational efficiency, and convenience to be integrated with other integrated circuit due to its planar structure, LDMOS transistor devices are prevalently used in high operational voltage environment such as CPU power supply, power management system, AC/DC converter, and high-power or high frequency (HF) band power amplifier. The essential feature of LDMOS transistor device is a lateral-diffused drift region with low dope concentration and large area. The drift region is used to alleviate the high voltage between the drain and the source, therefore LDMOS transistor device can have higher breakdown voltage. 
     Please refer to  FIG. 1 , which is a cross-sectional view of a conventional HV-LDMOS transistor device. As shown in  FIG. 1 , the conventional HV-LDMOS transistor device  10  having a P-type well  20 , a source  14  and a P-type heavily doped region  22  formed in the P-type well  20 , agate  16  and a drain  18  is formed on a semiconductor substrate  12 . The drain  18  is an N-type heavily doped region formed in an N-type well  30 , which is the drift region as mentioned above. The dope concentration and length of the drift region affects the breakdown voltage and the ON-resistance (R ON ) of the HV-LDMOS transistor device  10 . The gate  16  of the HV-LDMOS transistor device  10  is positioned on a gate dielectric layer  40  and extended to cover a portion of a field oxide layer  42 . 
     It is well-known that characteristics of low R ON  and high breakdown voltage are always required to the HV MOS transistor device. However, breakdown voltage and R ON  are conflicting parameters with a trade-off relationship. Therefore, a HV LDMOS transistor device that is able to realize high breakdown voltage and low R ON  is still in need. 
     SUMMARY OF THE INVENTION 
     According to the claimed invention, a layout pattern of a HV MOS transistor device is provided. The HV MOS transistor device includes a first doped region having a first conductivity type, a second doped region having the first conductivity type, and a non-continuous doped region positioned in between the first doped region and the second doped region. The non-continuous doped region includes a plurality of gaps formed therein. The non-continuous doped region further includes a second conductivity type complementary to the first conductivity type. 
     According to the claimed invention, a HV MOS transistor device is provided. The HV MOS transistor includes a substrate having an insulating layer formed thereon, a gate positioned on the substrate and covering a portion of the insulating layer, a drain region positioned in the substrate, a source region positioned in the substrate, and a non-continuous doped region positioned in between the source region and the drain region. The non-continuous doped region includes a plurality of gaps formed therein. The source region and the drain region include a first conductivity type, the non-continuous doped region includes a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. 
     According to the claimed invention, a layout pattern of an implant layer is further provided. The layout pattern includes at least a linear region and at least a non-linear region. The linear region includes a plurality of first patterns to accommodate first dopants and the non-linear region includes a plurality of second patterns to accommodate the first dopants. The linear region abuts the non-linear region. Furthermore, a pattern density of the first patterns in the linear region is smaller than a pattern density of the second patterns in the non-linear region. 
     According to the HV MOS transistor device and its layout pattern provided by the present invention, the non-continuous doped region is rendered to improve the breakdown voltage of the HV MOS transistor device. Furthermore, since the non-continuous doped region is interrupted by the gaps, the total area of doped portions of the non-continuous doped region is reduced. Consequently, R ON  is decreased efficaciously. Briefly speaking, the HV MOS transistor device and the layout pattern thereof provided by the present invention realize the expectation of high breakdown voltage and low R ON . 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a cross-sectional view of a conventional HV-LDMOS transistor device. 
       FIGS.  2  and  5 - 6  is a schematic drawing of a layout pattern of a HV MOS transistor device provided by a preferred embodiment of the present invention. 
         FIGS. 3-4  are cross-sectional views of the HV MOS transistor device take along A-A′ and B-B′ of  FIG. 2 , respectively. 
     
    
    
     DETAILED DESCRIPTION 
     Please refer to  FIGS. 2-6 ,  FIG. 2  is a schematic drawing of a layout pattern of a HV MOS transistor device provided by a preferred embodiment of the present invention, and  FIGS. 3-4  are cross-sectional views of the HV MOS transistor device take along A-A′ and B-B′ of  FIG. 2 , respectively. As shown in  FIGS. 2-4 , a HV MOS transistor device  100  provided by the preferred embodiment is positioned in a substrate  102 , such as a silicon substrate. The substrate  102  includes a first conductivity type. In the preferred embodiment, the first conductivity type is p-type. The HV MOS transistor device  100  further includes an insulating layer  104 . It is noteworthy that for clarifying spatial relationships between certain specific doped regions of the HV MOS transistor device  100 , the insulating layer  104  is omitted from  FIG. 2 . 
     Please refer to  FIGS. 2-6  again. The HV MOS transistor device  100  provided by the preferred embodiment further includes a deep well  106  having a second conductivity type. The second conductivity type and the first conductivity type are complementary to each other. Accordingly, the second conductivity type is n-type in the preferred embodiment. A drift region  108  and a high-voltage well region  110  (both shown in  FIGS. 3-4 ) are formed in the deep well  160 . The drift region  108  includes the second conductivity type while the high-voltage well region  110  includes the first conductivity type. In other words, the HV MOS transistor device  100  includes an n-type drift region  108  and a p-type high-voltage well region  110 . A first doped region  112  is formed in the n-type drift region  108  while a second doped region  114  and a third doped region  116  are formed in the high-voltage well region  110 . The first doped region  112  and the second doped region  114  include the second conductivity type and respectively serve as an n-type drain region  112  and an n-type source region  114  of the HV MOS transistor device  100 . The third doped region  116  includes the first conductivity type and serves as a p-type body region  116  of the HV MOS transistor device  100 . In addition, the body region  116  and the source region  114  are electrically connected as shown in  FIGS. 2-4 . 
     The HV MOS transistor device  100  also includes a gate  130 . However, the gate  130  is omitted from  FIG. 2  in order to clarify spatial relationships between certain specific doped regions of the HV MOS transistor device  100 . As shown in  FIG. 3  and  FIG. 4 , the gate  130  is positioned on the substrate  102  and covers a portion of the insulating layer  104 . 
     Please still refer to  FIGS. 2-4 . The HV MOS transistor device  100  provided by the preferred embodiment further includes a non-continuous doped region  120 . The non-continuous doped region  120  includes the first conductivity type and serves as a p-top region. As shown in  FIGS. 2-4 , the p-type non-continuous doped region  120  is positioned in between the n-drain region  112  and the n-source region  114 . The drain region  112 , the source region  114 , and the non-continuous doped region  120  formed in the deep well  106  are not only spaced apart from each other, but also electrically isolated from each other by the deep well  106 . As shown in  FIG. 2  and  FIG. 4 , the non-continuous doped region  120  includes a plurality of gaps  122  formed therein. The gaps  122  interrupt the p-type doped portions and thus to form the p-type non-continuous doped region  120 . A width of the gap  122  is smaller than or equal to 9 micrometers (μm). Furthermore, the insulating layer  104  covers the non-continuous doped region  120  and its gaps  122  entirely. 
     Please refer to  FIG. 2  again. According to the preferred embodiment, the p-type non-continuous doped region  120  being formed under the insulating layer  104  and complementary to the n-source region  114  and the n-drain region  112  increases the resistance of the HV MOS transistor device  100 . When high voltage signal (HV signal) passes through the p-type non-continuous doped region  120 , the voltage step-down ability of the HV MOS transistor device  100  is consequently improved and the acceptable lower voltage signal is obtained. In other words, by providing the p-type non-continuous doped region  120 , the breakdown voltage of the HV MOS transistor device  100  is efficaciously increased. 
     However, it is well known that R ON  is always undesirably increased in accompaniment of the increased breakdown voltage. Therefore the preferred embodiment provides the gaps interrupting in the p-type doped portions, and thus to form the p-type non-continuous doped region  120 . The gaps  122  are provided to lower the total area of doped area of the p-type non-continuous doped region  120  and to serve as an easy pathway for the electrons, therefore R ON  is efficaciously reduced. It is noteworthy that because high breakdown voltage and low R on  are conflicting parameters with a trade-off relationship, a ratio between a total area of the gaps  122  and a total area of the non-continuous doped region  120  is to be smaller than or equal to 20% according to the preferred embodiment, thus R ON  can be reduced while the expectation of high breakdown voltage is still met. 
     Please refer to  FIG. 5 . It is noteworthy that only the non-continuous doped region  120  and its gaps  122  are shown in  FIG. 5  in order to clarify the spatial relationship of the non-continuous doped region  120  and its gaps  122  in the layout pattern of the non-continuous doped region  120  while other elements are omitted. However, those skilled in the art would easily realize the relationships of those omitted elements according to the aforementioned descriptions and  FIGS. 2-4 . As shown in  FIG. 5 , the non-continuous doped region  120  includes an inner portion and an outer portion  142  defined therein according to the preferred embodiment. In detail, the non-continuous doped region  120  extends along the brim of the deep well  106  and has a racetrack or a comb shape. Also, the gaps  122  in the non-continuous doped region  120  are arranged to have a racetrack or a comb shape, accordingly. As shown in  FIG. 5 , a base, two outmost teeth of the comb, and proximal ends of each teeth of the comb are defined as the outer portion  142  while the inner teeth, and bases of each tooth are defined as the inner portion  140 . It is noteworthy that the gaps  122  positioned in the inner portion  140  include a first pattern density D 1 , the gaps  122  positioned in the outer portion  142  include a second pattern density D 2 , and the first pattern density D 1  is smaller than the second pattern density D 2 . For example, a ratio R 1  of the total area of the gaps  122  positioned in the inner portion  140  and the total area of the non-continuous doped region  120  is smaller than or equal to 15%, while a ratio R 2  of the total area of the gaps  122  positioned in the outer portion  142  and the total area of the non-continuous doped region  120  is smaller than or equal to 25%. Furthermore, the difference between the ratio R 1  and the ratio R 2  is, for example but not limited to, 7%. Because the dopant concentration in the n-type deep well  106  corresponding to the outer portion  142  (that is the brim of the deep well  106 ) is inherently lower than the dopant concentration in the n-type deep well  106  corresponding to inner portion  140  due to the nature of ion implantation process, the HV MOS transistor device  100  suffers higher R ON  corresponding to the outer portion  142 . Therefore the gaps  122  arranged in the outer portion  142  are provided to have the higher second pattern density D 2  according to the preferred embodiment. Since the total area of the gaps  122  arranged in the outer portion  142  is greater, R ON  of the HV MOS transistor device  100  corresponding to the outer portion  142  is reduced without lowering the breakdown voltage. 
     Please refer to  FIG. 6 . As mentioned above, only the non-continuous doped region  120  and its gaps  122  are shown in FIG.  6  in order to clarify the spatial relationship of the non-continuous doped region  120  and its gaps  122  in the layout pattern of the non-continuous doped region  120  while other elements are omitted. However, those skilled in the art would easily realize the relationships of those omitted elements according to the aforementioned descriptions and  FIGS. 2-4 . As shown in  FIG. 6 , the non-continuous doped region  120  includes a plurality of corner areas  150  and a plurality of straight-line areas  152  according to the preferred embodiment. As mentioned above, the non-continuous doped region  120  extends along the brim of the deep well  106  and has a comb shape. Accordingly, portions of the non-continuous doped region  120  having an arc profile are defined as the corner area  150  while portions of the non-continuous doped region  120  having the straight-line profile are defined as the straight-line areas  152 . It is noteworthy that the gaps  122  positioned in the corner areas  150  include a third pattern density D 3 , the gaps  122  positioned in the straight-line areas  152  includes a fourth pattern density D 4 , and the third pattern density D 3  is larger than the fourth pattern density D 4 . Because the electrical field corresponding to the corner areas  150  is always larger than the electrical field corresponding to the straight-line portions  152 , the HV MOS transistor device  100  suffers higher R ON  corresponding to the corner areas  150 . Therefore the gaps  122  arranged in the corner areas  150  are provided to have the higher third pattern density D 3  according to the preferred embodiment. Since the total area of the gaps  122  arranged in the corner areas  150  is greater, R ON  of the HV MOS transistor device  100  corresponding to the corner areas  150  is reduced without lowering the breakdown voltage. 
     According to the HV MOS transistor device and its layout pattern provided by the present invention, the non-continuous doped region is rendered to improve the breakdown voltage of the HV MOS transistor device. Furthermore, since the non-continuous doped region is interrupted by the gaps, the total area of doped portions of the non-continuous doped region is reduced. Consequently, R ON  is decreased efficaciously. Furthermore, the present invention further balances R ON  of the HV MOS transistor device without influencing the breakdown voltage by providing gaps having different pattern densities and sizes depending on dopant concentrations and electrical fields. Briefly speaking, the HV MOS transistor and the layout pattern thereof provided by the present invention realize the expectation of high breakdown voltage and low R ON . 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.