Abstract:
A method for controlling a switching voltage regulator that includes generating a feedback voltage that is proportional to the output voltage of the voltage regulator; generating a voltage proportional to the duty-cycle of the inductor charging and discharging phases as a function of the difference between the feedback voltage and a reference voltage; and adding a dominate pole and two zeros to the function used to generate the voltage proportional to the duty-cycle of the inductor charging and discharging phases.

Description:
BACKGROUND OF THE INVENTION  
       [0001]    A voltage regulator is a circuit that provides a precise output voltage under varying load conditions from an unknown and possibly varying input voltage. Many different types of voltage regulators have been developed, each with its own set of advantages. This particular application is directed at a particular class of voltage regulator known as inductor-based switching voltage regulators. The two most common types of inductor-based switching regulators are Boost (output voltage greater than input voltage) and Buck (output voltage less than input voltage) switching regulators. Both Boost and Buck switching regulators are very important for battery powered applications such as cellphones. 
         [0002]    As shown in  FIG. 1A , a traditional implementation for a Buck switching regulator includes a switch M 1  connected between an input voltage (VP in this case) and a node V X . A switch M 2  is connected between the node V X  and ground. An inductor L is connected between V X  and the output node (V OUT ) of the regulator. A filtering capacitor connects V OUT  to ground. The node V OUT  is also connected to a load represented by the resistor Rload. 
         [0003]    A control circuit (described below) turns switches M 1  and M 2  ON and OFF in a repeating pattern. M 1  is driven out of phase with M 2 . Thus, when M 1  is ON M 2  is OFF. This causes the Buck switching regulator to have two distinct operational phases. In the first phase, shown in  FIG. 1B , the switch M 1  is ON. During this phase, called the charging phase the inductor is connected between the battery and the output node V OUT . This causes current to flow from the battery to the load. In the process energy is stored in the inductor L in the form of a magnetic field. In the second, or discharge phase the switch M 1  is opened (see  FIG. 1C ). In this phase, the inductor is connected in series between ground and the load. Current supplied by the inductor&#39;s collapsing magnetic field flows to the output node V OUT  and the load. 
         [0004]    As shown in  FIG. 1D , a typical Boost converter includes all of the components just described. A slightly different topology is used in which the switch M 2  is placed between the inductor and the output node. The Boost converter uses a similar two phase pattern of switching for its two switches. 
         [0005]    SEPIC converters are another type of inductor-based switching regulators. SEPIC converters are more fully described in a copending U.S. patent application Ser. No. 11/933,402 entitled “High Voltage SEPIC Converter.” That disclosure is incorporated in this document by reference. 
         [0006]    To maintain its output at a constant voltage, switching regulators include control circuits that modulate the duty factor of their high and low-side switches. As shown in  FIG. 1A , the control circuit typically includes a resistive divider formed by resistors R 1  and R 2  as well as an error amplifier EA, comparator COMP and break-before-make circuit BBM. The resistive divider generates a feedback voltage FB proportion to the output of the regulator. The feedback voltage FB is one of the inputs to the error amplifier EA. The second error amplifier input is a reference voltage BG that is generated using any convenient technique as is well known in the relevant art. The error amplifier EA compares the feedback voltage FB to the reference voltage and multiplies the difference by a gain factor to generate an output voltage EAOUT. 
         [0007]    The error amplifier output EAOUT is one of the inputs to the comparator COMP. The second input to the comparator is a periodic ramp voltage RAMP. The output of the comparator (i.e., the comparison between the ramp voltage and the output of the error amplifier) is a periodic square wave signal CLKV. The square wave signal CLKV is passed to the break-before-make circuit. The BBM circuit generates a signal based on CLKV to drive the high-side switch and a complementary signal to drive the low-side switch. In general, it takes a finite amount of time to turn the high and low-side switches ON and OFF. For this reason, the act of turning a switch OFF is always done slightly in advance of the act of turning the other switch ON. This technique, known as break-before-make avoids the situation where both switches are ON at the same time and power is connected through the high and low-side switches to ground (a condition known as shoot through). 
         [0008]      FIG. 1E  shows the ramp voltage RAMP along with the error amplifier output EAOUT. The corresponding comparator output CLKV is also shown. As may be appreciated, the duty cycle of CLKV is defined by the intersection of RAMP and EAOUT.  FIG. 1E  also shows a higher error amplifier output (labeled EAOUT′ and the effect that it has on the duty cycle of the periodic square wave signal CLKV. This is the basic feedback mechanism for the Buck regulator of  FIG. 1A : decreases in the output voltage cause the feedback voltage FB to fall. This causes the error amplifier output EAOUT to increase. The increase in EAOUT causes CLKV to have an increased duty cycle. This increases the duty cycle of the high-side switch and decreases the duty cycle of the low-side switch. Thus, if the output voltage increases or decreases, the duty cycle of the high and low-side switches are adjusted in a way that compensates for the increased or decreased output. 
         [0009]    The control loop just described is an example of what is generally referred to as voltage mode control (i.e., regulator output is regulated as a function of output voltage). In this control loop, the gain of the error amplifier determines the accuracy of regulation. A high gain amplifier keeps the deviations of the output voltage relatively small and close to ideal. A lower gain amplifier allows larger deviations to occur. 
         [0010]    The control loop must maintain stability, that is to say, must not oscillate which would cause the output voltage to oscillate. Feedback theory provides criteria for this stability. If the gain of the control loop is plotted as a function of frequency, an element of the control loop must reduce the gain below one at some frequency. This frequency is called the gain-bandwidth product or unity gain frequency. 
         [0011]    A large GBW product control loop indicates that the control loop is fast and can respond to fast transients. For example, in modern microprocessors, the processor can turn on rapidly so that the supply current takes a large fast step in times approaching the switching speed of the microprocessor. A large GBW product allows the voltage regulator to respond quickly to such changes. (If the circuit does not have a large GBW product, then large output capacitors are needed to sustain the output voltage until the loop responds). 
         [0012]    Control theory says that the phase shift around the control loop must not be greater than 180 degrees at the unity gain frequency. In fact, the circuit is not really useable if the phase shift of the control loop is near 180 degrees. It is preferable to be near 90 degrees, but in many cases 140 to 130 degrees of phase shift is acceptable. 
         [0013]    In a voltage mode converter, the inductor—capacitor pair introduce a 180 degree phase shift by themselves at their resonant frequency: ½π*(L*C) 1/2 . As a result, any control loop must take this into account by removing about 90 degrees of phase shift starting at the resonant frequency. 
         [0014]    In the parlance of control loop theory, the removal of 90 degrees of phase shift is accomplished by adding a “zero” to the control loop. If 90 degrees of phase shift is added, a “pole” is added to the control loop. The LC filter of the buck converter adds a “double pole” at the resonant frequency, to get the 180 degree phase shift. 
         [0015]    If nothing were done except adding a wide band amplifier for control, the voltage mode converter would be unstable because of the double pole adding 180 degrees of phase shift at the unity gain frequency. For good compensation a zero must be added at the resonant frequency of the output filter to add back 90 degrees of phase shift. 
         [0016]    In the prior art, voltage mode compensation has been generally accomplished three ways as shown in  FIG. 2 . The first way is placing a capacitor, Cz, in the feedback loop. This adds a zero and a pole which are generally too close together in frequency for most cases we want to consider. This makes this technique helpful but not very useful. 
         [0017]    Another prior art is using the parasitic resistance, Resr, of the filter capacitor Cx as the zero forming element. For a 20 uf filter capacitor, and a 30 kHz zero, this yields an Resr of 0.26 ohms which is large (for most cases) and may produce large ripple. To get to a reasonable ESR, large values of capacitance must be used, but still the ripple is a problem. Generally tantalum or other electrolytic capacitors are needed for this type of compensation. Ceramic capacitors, in general, have too low an ESR to be effective. Tantalum capacitors are generally more expensive than ceramic. 
         [0018]    In  FIG. 2  a box is shown connecting the error amp output to the feedback node. This feedback network might be used to create a three pole, two zero circuit which can be effective to stabilize the voltage mode circuit. The resultant gain transfer curve is shown in  FIG. 3 . A dominant pole is introduced at about 30 Hz. At about 20 k Hz a double zero is introduced, just below the resonance of the LC circuit. At about the switching frequency of the regulator, about 1 MHz, another double pole is introduced which rolls the gain off to the unity gain point above 10 MHz. 
         [0019]    The error amplifier output and FB nodes are brought to an external compensation network where a dominant pole and two zeros are introduced. In order to make the system stable, a double pole must be introduced at a high frequency to roll the gain off to make the system stable. In this example, the gain bandwidth product is near 50 MHz for the amplifier. It can also be seen that the second zero&#39;s effectiveness is less than a decade. If the GBW product of the amplifier is reduced, the whole curve must be shifted to a lower frequency, which makes the regulator slower and uses larger external components. 
         [0020]    A third compensation scheme places a low pole in the compensation network such that the unity gain is reached well before the double pole of the output filter. This makes a very slow control loop. 
       SUMMARY OF THE INVENTION  
       [0021]    This disclosure describes an internal compensation network and associated compensation method for inductor-based switching regulators (see  FIG. 4 ). The compensation network adds a pole and two zeros to compensate high-frequency voltage mode operation. An example of an inductor-based switching regulator that uses the compensation network includes a high-side switch connected between an input supply (VN) and a node VX. The node VX is connected to a ground voltage (VN) by a low-side switch. An inductor connects the node VX to and output node. The output node is further connected to the ground voltage VN by and output or filter capacitor. A load is connected between the output node and the ground voltage in parallel with the output capacitor. 
         [0022]    A control circuit is used to drive the high and low-side switches in a repeating sequence that includes an inductor charging phase and an inductor discharging phase. During the inductor charging phase, the control switch activates the high-side switch to connect the node Vx to the input voltage. This causes current to flow from the input supply, through the inductor to the load. During the inductor discharging phase, the control switch activates the low-side switch (and deactivates the high-side switch). This connects the node Vx to ground. Current continues to flow to the load as the magnetic field of the inductor collapses. The control circuit modulates the duty cycle of the high and low-side switches (i.e., the relative duration of activation of the high and low-side switches) to regulate the voltage at the output node. 
         [0023]    To perform the required modulation, the control circuit uses a resistive divider is used to generate a feedback voltage FB that is proportional to the voltage difference between the output node and the ground voltage. 
         [0024]    The feedback voltage is passed, via a resistor Rf 1  to the positive input of an error amplifier. A node V 1  located between the resistor Rf 1  and the error amplifier is connected via a filter capacitor Cf 1  to ground. A reference voltage BG is passed, via a resistor R 4  to the negative input of the error amplifier. A node V 2  located between the resistor R 4  and the error amplifier is connected via a filter capacitor Cf 3  to ground. A compensation network is connected between the node V 2  and the output of the error amplifier. 
         [0025]    Within the compensation network, a series connection of a capacitor C 2  and a resistor R 3  connect the node V 2  to an internal node V 3 . The node V 3  is connected, by a series connection of the resistor R 1  and the capacitor C 1  to ground. 
         [0026]    A resistor R 2  connects the node V 3  to an internal node V 4 . The node V 4  is connected by a second filter capacitor Cf 2  to the ground voltage. The node V 4  is connected via a resistor Rf 2   a  to the output of the error amplifier. The node V 4  is also connected by a resistor Rfb 2  to the output node EAOUT of the compensation network. 
         [0027]    The output node EAOUT is connected an input of a comparator. The second input to the comparator is a periodic ramp voltage RAMP. The output of the comparator (i.e., the comparison between the ramp voltage and the output of the error amplifier) is a periodic square wave signal CLKV. The square wave signal CLKV is passed to the break-before-make circuit. The BBM circuit generates a signal based on CLKV to drive the high-side switch and a complementary signal to drive the low-side switch. 
         [0028]    As the switching regulator operates, the error amplifier generates a voltage proportional to the duty cycle of the high and low-side switches. The compensation network adds a dominate pole and two zeros to the gain product of the error amplifier to compensate high-frequency voltage mode operation. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0029]      FIG. 1A  is a block diagram of a prior art Buck switching regulator. 
           [0030]      FIG. 1B  is a block diagram showing the prior art Buck switching regulator of  FIG. 1  during the charge phase of operation. 
           [0031]      FIG. 1C  is a block diagram showing the prior art Buck switching regulator of  FIG. 1  during the discharge phase of operation. 
           [0032]      FIG. 1D  is a block diagram of a prior art Boost switching regulator. 
           [0033]      FIG. 1E  is graph showing the feedback and ramp voltages used to control typical prior art switching regulators. 
           [0034]      FIG. 2  is a block diagram of a prior art Buck switching regulator with a compensation network. 
           [0035]      FIG. 3  is a plot showing the gain transfer associated with prior art switching regulators. 
           [0036]      FIG. 4  is a block diagram of an inductor-based switching regulator that includes an embodiment of the compensation network of the present invention. 
           [0037]      FIG. 5  is a plot showing the LC filter response associated with the switching regulator of  FIG. 4 . 
           [0038]      FIG. 6  is a gain plot of the compensation network of  FIG. 4 . 
           [0039]      FIG. 7  shows the amplifier gain for the switching regulator of  FIG. 4  as well as the associated LC filter gain and the product of the amplifier gain and LC filter gain. 
           [0040]      FIG. 8A  is a block diagram of a simplified embodiment of the compensation network of the present invention. 
           [0041]      FIG. 8B  is a block diagram of an embodiment of the compensation network of the present invention. 
           [0042]      FIG. 9  is a Bode plot that has been generated for the local feedback circuit of the switching regulator of  FIG. 4 . 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0043]    This disclosure describes an internal compensation network for use in inductor-based switching regulators as well as a related compensation method and inductor-based switching regulators that use the compensation network and method. The compensation network adds a pole and two zeros to compensate high-frequency voltage mode operation.  FIG. 4  shows an example of an inductor-based switching regulator  400  that uses an implementation of the compensation network  402 . Switching regulator  400  includes a high-side switch MP 1  connected between an input supply (VN) and a node VX. The node VX is connected to a ground voltage (VN) by a low-side switch MN 1 . An inductor connects the node VX to and output node which is further connected to the ground voltage VN by an output capacitor. A load is connected between the output node and the ground voltage in parallel with the output capacitor. A resistive divider is used to generate a feedback voltage FB that is proportional to the voltage difference between the output node and the ground voltage. 
         [0044]    The feedback voltage FB is connected to the first input of an error amplifier to an error amplifier. A second input of the error amplifier is connected, via a resistor R 4  to the reference voltage BG. The output of the error amplifier is labeled EAOUT. A compensation network  404  connects the output of the error amplifier EAOUT to a node between the resistor R 4  and the error amplifier. 
         [0045]    The EAOUT voltage is connected an input of a comparator. The second input to the comparator is a periodic ramp voltage RAMP. The output of the comparator (i.e., the comparison between the ramp voltage and the output of the error amplifier) is a periodic square wave signal CLKV. The square wave signal CLKV is passed to the break-before-make circuit. The BBM circuit generates a signal based on CLKV to drive the high-side switch and a complementary signal to drive the low-side switch. 
         [0046]    Stability is a crucial aspect of the Buck converter of  FIG. 4 . At the heart of the problem is the LC filter response, as shown in  FIG. 5  with its double pole at the resonant frequency. It can be seen that it is a double pole roll-off of 40 db per decade starting at the resonant frequency of the filter. This means that there is a 180 degree phase shift in the response curve. If the amplifier had infinite bandwidth, the LC filter phase shift would mean that the system would be very ringy if not unstable. The peak is the result of the poles being near the imaginary axis. A small amount of series resistance, in the switches or the inductor, or losses in the inductor, will keep the peak within reasonable bounds. 
         [0047]    To compensate this circuit, a dominant pole is introduced to roll off the gain starting at low frequency. Then a first zero is introduced to cancel the effects of the dominant pole. A second zero must be overlaid on the double pole of the LC filter. This will compensate one of the double poles and allow the system to be stable. The gain plot of an amplifier compensation circuit with such a pole and two zeros is shown in  FIG. 6 . 
         [0000]    
       
         
               
             
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 LC Filter Parameters 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 L 
                 1 uH resonance 35.6 kHz 
               
               
                   
                 C 
                  20 uF 
               
               
                   
                 R 
                 0.2 ohm 
               
               
                   
                   
               
             
          
         
       
     
         [0000]    
       
         
               
             
               
               
               
             
           
               
                 TABLE 2 
               
               
                   
               
               
                 Poles and Zeros of the gain block 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 z1 
                 10 kHz 
               
               
                   
                 z2 
                 30 kHz 
               
               
                   
                 p1 
                 0.05 kHz dc gain 1000 
               
               
                   
                   
               
             
          
         
       
     
         [0048]      FIG. 7  shows the amplifier gain, the LC filter gain and their product. It can be seen that the system gain has been compensated by the second zero the amplifier. The problem to be solved is how to do this second zero while making the system stable. The line labeled “product” is the resultant. It crosses the zero DB line with 20 db per decade slope showing that the system can be made stable. 
         [0049]    To add the dominant pole and two zeros, a simplified version of the compensation network  402  is configured as shown in  FIG. 8A . Compensation network  402  includes a capacitor C 1 , and resistors R 3  and R 2  connected in series between the second input of the error amplifier and the error amplifier output. A capacitor C 2  is connected between ground and a node between the resistors R 3  and R 2 . 
         [0050]    As shown in more detail in  FIG. 8B , the compensation network is configured to include an error amplifier, three filter capacitors (Cf 1 , Cf 2  and Cf 3 ), two capacitors (C 1  and C 2 ), seven resistors Rf 1 , Rf 2   a,  Rf 2   b,  R 1 , R 2 , R 3 , R 4  and four internal nodes V 1 , V 2 , V 3 , V 4 . The resistor Rf 1  connects the feedback voltage to the internal node V 1 . The node V 1  is connected, in turn to the error amplifier and via the filter capacitor Cf 1  to the feedback voltage to the ground voltage. The capacitors Cf 1 , Cf 2  and Cf 3  are filter capacitors to filter out the switching frequency of MN 1  and MP 1 . Likewise, Rf 1 , Rf 2   a  and Rf 2   b  are the resistors which aid the filter capacitors to work. 
         [0051]    The resistor R 4  connects a reference voltage BG to the internal node V 2 . The reference voltage BG is generated using any convenient technique as is well known in the relevant art. The node V 1  is connected, in turn to the second input of the error amplifier and via the filter capacitor Cf 3  to the ground voltage. 
         [0052]    A series connection of the capacitor C 2  and the resistor R 3  connect the node V 2  to the internal node V 3 . The node V 3  is connected, by a series connection of the resistor R 1  and the capacitor C 1  to the ground voltage. 
         [0053]    The dominant pole of the amplifier is set by the miller multiplied capacitance of C 2  against the resistor in the reference circuit, R 4 . Typically this might be set at 50 Hz. As the frequency is increased, the impedance of C 2  becomes small compared to the resistors. This sets the minimum gain of the amplifier, the AC gain. The AC gain is set by the resistors R 2 , R 3  and R 4 , which is (R 3 +R 2 )/R 4 . 
         [0054]    The frequency of the first zero, Z 1 , is set by R 3 , R 2  and C 2 . It occurs when the resistance of R 3 +R 2  is greater than the impedance of capacitor C 2 . The gain flattens out to the AC gain. As the frequency increases, capacitor C 1  starts to be effective, shorting out the feedback signal to ground, so the gain of the amplifier starts to increase through the positive input. At some point, the whole signal is shorted out and the gain of the amplifier approaches the DC gain. 
         [0055]    This second zero, Z 2 , is set by the parallel impedance of R 3 ∥R 2  and C 1  which fully determines the compensation network. The feedback signal is uncoupled from the compensation network. 
         [0056]    In  FIG. 8C , a second implementation of the compensation network is shown and generally designated  402 ′. Compensation network  402 ′ includes an error amplifier, three filter capacitors (Cf 1 , Cf 2  and Cf 3 ), two capacitors (C 1  and C 2 ), seven resistors Rf 1 , Rf 2   a,  Rf 2   b,  R 1 , R 2 , R 3 , R 4  and four internal nodes V 1 , V 2 , V 3 , V 4 . The resistor Rf 1  connects the feedback voltage to the internal node V 1 . The node V 1  is connected, in turn to the error amplifier and via the filter capacitor Cf 1  to the feedback voltage to the ground voltage. The capacitors Cf 1 , Cf 2  and Cf 3  are filter capacitors to filter out the switching frequency of MN 1  and MP 1 . Likewise, Rf 1 , Rf 2   a  and Rf 2   b  are the resistors which aid the filter capacitors to work. 
         [0057]    The resistor R 4  connects a reference voltage BG to the internal node V 2 . The reference voltage BG is generated using any convenient technique as is well known in the relevant art. The node V 1  is connected, in turn to the second input of the error amplifier and via the filter capacitor Cf 3  to the ground voltage. 
         [0058]    A series connection of the capacitor C 2  and the resistor R 3  connect the node V 2  to the internal node V 3 . The node V 3  is connected, by a series connection of the resistor R 1  and the capacitor C 1  to the ground voltage. 
         [0059]    A resistor R 2  connects the node V 3  to the fourth internal node V 4 . The node V 4  is connected by the second filter capacitor Cf 2  to the ground voltage. The output of the error amplifier is connected by a resistor Rf 2   a  to the node V 3 . The node V 4  is connected by a resistor Rfb 2  to the output node EAOUT of the compensation network. 
         [0060]    It must be noted that the feedback signal comes into the positive input to the error amplifier and that the reference is attached to the negative input. For the loop to operate a 180 degree phase shift is introduced at the comparator in the next stage which inverts the sign of the signals. 
         [0061]    In this configuration the signal path is not utilized in the compensation network except as a filter for the switching frequency. All of the signal shaping is done in the feedback path which is not in the direct signal path. 
         [0062]    The DC gain is just the DC gain of the amplifier, itself, which can be seen by opening all of the capacitors in the feedback path. The dominant pole of the amplifier is set by the miller multiplied capacitance of C 2  against the resistor in the reference circuit, R 4 . Typically this might be set at 50 Hz. As the frequency is increased, the impedance of C 2  becomes small compared to the resistors. This sets the minimum gain of the amplifier, the AC gain. The AC gain is set by the resistors R 2 , R 3  and R 4 , which is (R 3 +R 2 )/R 4 . 
         [0063]    The frequency of the first zero, Z 1 , is set by R 3 , R 2  and C 2 . It occurs when the resistance of R 3 +R 2  is greater than the impedance of capacitor C 2 . The gain flattens out to the AC gain. As the frequency increases, capacitor C 1  starts to be effective, shorting out the feedback signal to ground, so the gain of the amplifier starts to increase through the positive input. At some point, the whole signal is shorted out and the gain of the amplifier approaches the DC gain. 
         [0064]    This second zero, Z 2 , is set by the parallel impedance of R 3 ∥R 2  and C 1  which fully determines the compensation network. The feedback signal is uncoupled from the compensation network. R 1  adds a high frequency pole which was added heuristically to improve performance. 
         [0065]    This circuit has been found to work well because at low frequency the feedback loop is open, no feedback, because of the capacitors being high impedance. At high frequency, the feedback circuit is again open, being shorted out by capacitor C 1 . If the feedback loop is open, then it can not oscillate. It will be noted that there is no sign of instability of the error amplifier in any simulations whether switching or linearized. 
         [0066]    To demonstrate unconditional stability a Bode plot was generated for the local feedback circuit. In order to do this, the loop must be broken. An analysis technique has been developed by Middlebrook to obtain accurate gain and phase response without breaking the loop. It requires two sources be introduced into the feedback loop, a voltage source and a current source. Two transfer ratios are measured from these two cases, Tv and Ti, which are then used to get the total transfer curve, the Bode plot, T as follows: 
         [0000]    
       
         
           
             T 
             = 
             
               
                 ( 
                 
                   
                     Ti 
                     * 
                     Tv 
                   
                   - 
                   1 
                 
                 ) 
               
               
                 ( 
                 
                   Ti 
                   + 
                   Tv 
                   + 
                   2 
                 
                 ) 
               
             
           
         
       
     
         [0067]    The results of this analysis, shown in  FIG. 9 , are that the local loop compensation circuit and error amplifier combination are unconditionally stable for these circuit elements. The dashed plot is gain in db and the phase is solid line. Aside from the fact that SPICE reflects phase at 180 degrees, it can be seen that the phase hovers around 180 degrees out to 100 Mhz. It can be seen that the gain reaches  1  over a range of frequencies, but the phase is always 180 degrees, or close, while the gain is near unity. There is only a small observation, that at 20 Mhz, there is a small disturbance in the phase, but the gain has dropped below unity at this point. 
         [0068]    This analysis confirms the observation that the transient simulation makes, that this circuit is very stable and exhibits no tendency to oscillate.