Abstract:
A process for forming land grid array semiconductor packages includes a leadframe that is supported by a substrate comprising mold compound. In some embodiments, at least one die is electrically coupled to the leadframe by bondwires. The package comprises a second mold compound to act as an encapsulant. An apparatus for forming a land grid array semiconductor package includes means for molding a leadframe, assembling thereon at least one semiconductor device, applying a second mold, and singulating to form individual devices. A land grid array package comprises a leadframe, a substrate for supporting the leadframe, at least one semiconductor device and a mold compound.

Description:
RELATED APPLICATIONS 
       [0001]    This application claims benefit of priority under 35 U.S.C. section 119(e) of co-pending U.S. Provisional Patent Application 60/875,162 filed Dec. 14, 2006, entitled MOLDED-LEADFRAME SUBSTRATE SEMICONDUCTOR PACKAGE and U.S. Provisional Patent Application 60/877,274 filed Dec. 26, 2006, entitled MOLDED-LEADFRAME SUBSTRATE SEMICONDUCTOR PACKAGE, which are both incorporated herein by reference. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The present invention is in the field of semiconductor packaging and is more specifically directed to package with heat transfer. 
       BACKGROUND 
       [0003]    The increasing demand for performance from electrical appliances has led to higher chip internal clock frequencies and parallelism, and has increased the need for higher bandwidth and lower latencies. For example, computer processor frequencies are predicted to reach 29 GHz by 2018, and off-chip signaling interface speeds are expected to exceed 56 Gb/s. Optimization of bandwidth, power, pin count, or number of wires and cost are the goals for high-speed interconnect design. The electrical performance of interconnects is restricted by noise and timing limitations of the silicon, package, board and cable. To that end, semiconductor packages must be made smaller, conforming more and more closely to the size of the die encapsulated within. However, as the size of the package shrinks to the size of the die itself, the size of the package becomes insufficient to support the number of leads generally required by current applications. Furthermore, these high speed devices generate significant heat which must be harvested or damage can occur. 
         [0004]    Chip Scale Packages (CSP) have emerged as the dominant package for such applications.  FIG. 1  shows an example of a CSP in current practice. More specifically, the package in  FIG. 1  is a Wafer Level Chip Scale Package  10  (WLCSP), commonly marketed by companies such as National Semiconductor Corporation as the Micro SMD and Maxim Integrated Products as the UCSP. Generally, solder bumps  11  are formed on processed and completed semiconductor wafers  12  before the wafers are sawn to form individual semiconductor device  13 . Although this has dramatically reduced package size and can be useful in some instances, it suffers from drawbacks which remove it from consideration for certain applications. First, the pitch between the solder bumps must be made wide enough to effectuate assembly of the device onto a printed circuit board in application. This requirement can cause manufacturers to have to artificially grow die sizes to meet the minimum pitch, thereby increasing cost. Second, the total I/O count of the device is generally constrained due to the decreased reliability at the high bump counts. At bump counts higher than 49, or a 7×7 array, reliability becomes critical and applications such as hand held devices, which require a high degree of reliability, no longer become a possible marketplace. Furthermore, semiconductor devices generating significant heat require cooling, and difficulties arise when attempting to cool a CSP since there is very little surface area to mount a heat sink or other cooling device onto. 
         [0005]    To overcome the issues mentioned above, the semiconductor industry has moved toward Ball Grid Array (BGA) packages. The BGA is descended from the pin grid array (PGA), which is a package with one face covered (or partly covered) with pins in a grid pattern. These pins are used to conduct electrical signals from the integrated circuit (IC) to the printed circuit board (PCB) it is placed on. In a BGA, the pins are replaced by balls of solder stuck to the bottom of the package. The device is placed on a PCB having copper pads in a pattern that matches the solder balls. The assembly is then heated, either in a reflow oven or by an infrared heater, causing the solder balls to melt. Surface tension causes the molten solder to hold the package in alignment with the circuit board, at the correct separation distance, while the solder cools and solidifies. The BGA is a solution to the problem of producing a miniature package for an IC with many hundreds of I/O. As pin grid arrays and dual-in-line (DIP) surface mount (SOIC) packages are produced with more and more pins, and with decreasing spacing between the pins, difficulties arose in the soldering process. As package pins got closer together, the danger of accidentally bridging adjacent pins with solder grew. BGAs do not have this problem, because the solder is factory-applied to the package in exactly the right amount. Alternatively, solder balls can be replaced by solder landing pads, forming a Land Grid Array (LGA) package. 
         [0006]      FIG. 2A  shows a cutaway image of a generic BGA package  20 . Generally, an IC  21  has bondpads  22  to which bondwires  23  are affixed. The IC  21  is mounted on a substrate  24 . In current practice, the substrate  24  is a laminate, such as polyimide. Generally, the substrate  24  is of a similar construction to a PCB. The substrate  24  has copper patterns  25  formed thereon. The bondwires  23  effectuate electrical contact between the IC  21  and the copper patterns  25 . The copper patterns  25  are electrically connected to solder balls  26  through via holes  27  in the substrate  24 . In most embodiments of BGA packages, the IC  21  is encapsulated by a mold compound  28 . Although BGA packages effectuate large I/O count devices in small areas, they are susceptible to moisture. Generally, moisture seeps into packages while awaiting assembly into a finished product, such as a computer. When the package is heated to solder the device into its end application, moisture trapped within the device turns into vapor and cannot escape quickly enough, causing the package to burst open. This phenomenon is known as the “popcorn” effect. What is needed is a semiconductor package that is robust to both structural stressors and moisture. 
       SUMMARY OF THE DISCLOSURE 
       [0007]    In one aspect of the invention, a process for forming a exposed die attach pad (EDAP) semiconductor package comprises at least partially encasing a first leadframe strip having at least one exposed die attach pad (DAP) in a first mold compound thereby forming a molded leadframe strip, mounting at least one semiconductor device on the molded leadframe strip, mounting bondwires on the at least one semiconductor device to effectuate electrical contact between the at least one semiconductor device and the at least one molded leadframe, at least partially encasing the molded leadframe strip, the at least one semiconductor device, and bondwires, and singulating the molded leadframe strip to form discrete EDAP packages. In some embodiments, The process further comprises coupling the first leadframe strip to a second leadframe strip by a soft metal. The soft metal comprises at least one of the following materials: gold, silver, lead, and tin. The first and second mold compounds are able to be identical or different compounds. 
         [0008]    In another aspect of the invention, an apparatus for forming an EDAP package comprises means for at least partially encasing a first leadframe strip having a plurality of die attach pads in a first mold compound thereby forming a molded leadframe strip, means for mounting at least one semiconductor device on the at least one molded leadframe strip, means for mounting bondwires on the at least one semiconductor device to effectuate electrical contact between the at least one semiconductor device and the molded leadframe, means for at least partially encasing the molded leadframe strip, the at least one semiconductor device, and bondwires in a second mold compound and means for singulating the molded leadframe strip to form discrete and grid array packages. In some embodiments, the apparatus further comprises an embossing surface for forming a step cavity into the molded leadframe strip for encapsulating the at least one semiconductor device. Optionally, the apparatus further comprises means for mounting a cap on the molded leadframe strip thereby fainting a full cavity for encapsulating the at least one semiconductor device. The cap comprises at least one of the following materials: glass, silicon, ceramic, metal, epoxy, and plastic. In some embodiments, the apparatus further comprises means for coupling the first leadframe to a second leadframe by a soft metal. The soft metal comprises at least one of the following materials: gold, silver, lead, and tin. The first and second mold compounds are able to be identical or different compounds. 
         [0009]    As another aspect of the invention, an exposed die attach pad package comprising a first leadframe, the leadframe having a die attach pad, a substrate for supporting the leadframe, at least one semiconductor die mounted on the leadframe, a plurality of bondwires to effectuate electrical contact between the leadframe and the at least one semiconductor die, and a second mold compound for at least partially encasing the first leadframe, at least one semiconductor die, and plurality of bondwires is disclosed. In some embodiments, the substrate comprises a first mold compound. Optionally, the semiconductor further comprises a step cavity or a cap for forming a full cavity. The cap is able to be comprised of glass, silicon, ceramic, or metal. In some embodiments, the semiconductor device further comprises a second mold compound for at least partially encasing the first leadframe, the substrate, the at least one semiconductor device and the plurality of wirebonds. Optionally, the semiconductor package further comprises a second leadframe coupled to the first leadframe by a soft metal. The soft metal is able to be comprised of at least one of the following materials: gold, silver, lead and tin. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The novel features of the invention are set forth in the appended claims. However, for purpose of explanation, several embodiments of the invention are set forth in the following figures. 
           [0011]      FIG. 1  is a prior art Chip Scale Package. 
           [0012]      FIG. 2  is a prior art Ball Grid Array package in cross section. 
           [0013]      FIG. 3  is a process for forming a molded leadframe per an embodiment of the current invention. 
           [0014]      FIG. 4A  is a process for fanning a molded leadframe per an embodiment of the current invention. 
           [0015]      FIG. 4B  is a process for forming a molded leadframe per an embodiment of the current invention. 
           [0016]      FIG. 5  is a process for forming individual packages per an embodiment of the current invention. 
           [0017]      FIG. 6A  is a semiconductor package per an embodiment of the current invention. 
           [0018]      FIG. 6B  is apparatus for realizing the package depicted in  FIG. 6A . 
           [0019]      FIG. 6C  is an alternate process for forming a package in  FIG. 6A . 
           [0020]      FIG. 6D  is the remainder of the process for forming the package  FIG. 6A . 
           [0021]      FIG. 6E  is an alternate apparatus for realizing the package depicted in  FIG. 6A . 
           [0022]      FIG. 7  is a process for forming an exposed die attach pad package. 
       
    
    
     DETAILED DESCRIPTION 
       [0023]    In the following description, numerous details and alternatives are set forth for purpose of explanation. However, one of ordinary skill in the art will realize that the invention can be practiced without the use of these specific details. In other instances, well-known structures and devices are shown in block diagram form in order not to obscure the description of the invention with unnecessary detail. 
         [0024]    In a first aspect of the invention, a process  300  for forming semiconductor packages is detailed in  FIG. 3 . A leadframe  301  is shown in cross section. In some embodiments, a top mold  302  and a bottom mold  303  are placed to effectuate the injection therein of a mold compound  304 . The top and bottom molds  302 ,  303  can be metal, ceramic, or any material having an appropriate thermal characteristic to withstand the temperatures of the mold compound  304  in its liquid state. It is commonly known by those of ordinary skill in the art of semiconductor device manufacturing that a wide variety of mold compounds  304  is able to be used, each having advantages, disadvantages, and characteristics appropriate for a given application. By way of example, in high temperature applications such as microprocessors which generate a significant amount of heat, a high thermal conductivity mold compound  304  is able to be used. What is formed is a molded lead frame  305 . Advantageously, the molded leadframe  305  will display enhanced rigidity and robust reliability characteristics. The use of a mold compound  304  further enhances encapsulation and protection from external moisture that standard PCB substrates such as polyimide or FR4 cannot provide. 
         [0025]    For more predictable molding results, carrier tape is able to be used effectuate the molding process.  FIG. 4A  details another embodiment of the invention. A process  400  includes applying tape  405  on its adhesive side to a leadframe  401 . The leadframe  401  is then placed in a top mold cavity  402  by the top side of the leadframe  401 . On the opposite side of the leadframe  401 , non-adhesive tape  406  is prepared in a tape loader  407  at the bottom mold  408 . Once the leadfame  401  is in place between a top mold  412  and a bottom bold  413 , mold compound  404  is injected and fills all empty cavities. When removed from the mold, a molded leadframe  410  is formed. Optionally, a de-gate/de-runner step removes excess mold compound  411 . 
         [0026]      FIG. 4B  shows alternate embodiments for the process detailed in  FIG. 4A . In some embodiments, the leadframe  401  is able to be placed between the top mold  412  and bottom mold  413  with adhesive tape  405  applied to the bottom.  FIG. 4C  shows another embodiment wherein the leadframe  401  is able to be placed between the top mold  412  and bottom mold  413  without the use of adhesive tape. Non adhesive tape  406  is able to be provided by a tape loader  407  on the bottom surface of the leadframe  401 . In another exemplary embodiment, two tape loaders  407  are provided to effectuate the molding of the leadframe  401 . It will be appreciated by those of ordinary skill in the art of semiconductor manufacturing that several embodiments exist to place a leadframe  401  between a top mold  412  and a bottom mold  413  and the embodiments discussed herein are written solely to be exemplary and non limiting. 
         [0027]      FIG. 5  shows a process  500  for the completion of the semiconductor packaging process. Semiconductor devices  501  are mounted on the molded leadframe strip  502 . In some embodiments, multiple semiconductor devices  501  are mounted in each individual position on the molded leadframe strip  502 . Such devices are known as multi chip modules (MCM). Bond-wires  503  are mounted on the semiconductor devices  501  to effectuate electrical contact between the molded leadframe strip  502  and the semiconductor devices  501 . In some embodiments where multiple semiconductor devices  501  are placed in each position, bondwires  503  can be placed to effectuate electrical contact between them as applications require. Next, a second mold compound  505  is applied to the molded leadframe strip  502 . The second mold  505  encases the semiconductor devices  501  and bondwires  503  to protect them from harsh outer environments. In some embodiments, the second mold compound  505  and the first mold compound described in  FIGS. 3 and 4  are the same. However, in other embodiments, the first and second mold compound  505  are able to be different to meed the demands of particular applications. By way of example, the semiconductor device  501  and the leadframe  401  in  FIG. 4  can have different coefficients of expansion in response to heat, and different mold compounds having different thermal characteristics such as thermal resistivity and thermal expansion can be used to offset the effects of the leadframe  401  expanding. The molded leadframe strip  502  are then singulated by saw blades  515  to form singulated semiconductor packages  520 ,  530  and  540 . The singulated devices  520   530  and  540  are generally tested, subjected to stress, and tested again to ensure reliability and to filter out non passing or non standard units. 
         [0028]    In some applications, it is advantageous for greater height clearance within the semiconductor package.  FIG. 6A  shows a singulated semiconductor package  600  in cross section. Within the package, a recessed area  601  is capable of receiving a thicker semiconductor die  602 , larger bondwires  603  or in certain embodiments multiple stacked die.  FIG. 6B  shows an exemplary surface  610  of the mold  412  or  413  shown in  FIG. 4B . Elevated protrusions  611  are placed to coincide with a leadframe strip to emboss a recessed area  601  into the leadframe. In an exemplary embodiment, adhesive tape  621  is applied to the back surface of the leadframe strip  622 . The leadframe is flipped over such that its top surface is embossed by the non adhesive tape  610  having the protrusions  611 . 
         [0029]      FIG. 6D  shows the leadframe strip  622  with a first mold compound  623  to form a molded leadframe  630  having recessed areas  601 . To fowl singulated packages, semiconductor devices  602  and bondwires  603  are affixed onto the molded leadframe  630 . The devices  602 , bondwires  603  and molded leadframe  630  are encased in a second mold compound  650 . The second mold compound  650  and the first mold compound  623  are able to be the same compound or different compounds depending on the application. Saw blades  655  then singulate the molded leadframe strip  630  into individual semiconductor packages  600 . 
         [0030]    An alternative surface is shown in  FIG. 6E . In certain applications, such as high temperature applications, thick leadframes are advantageous. To accommodate thick leadframes, the non adhesive tape  610  is able to have pre-formed holes  660  configured to receive protrusions  670  on a mold surface  675 . The mold surface  675  can be the surface of the top mold  412  or the bottom bold  413 . The mold is able to be formed of metal, ceramic, hard impact rubber, or any other suitable material. 
         [0031]    In a particular aspect of the invention, an exposed die attach pad (EDAP) package and a process for producing the same is disclosed.  FIG. 7  details a process  700  for forming singulated EDAP package devices  790 . A leadframe strip  701  is attached to adhesive tape  702 . Preferably, the leadframe strip  701  comprises a die attach pad (DAP)  722 . In application, the DAP is generally soldered to a PCB, there by effectuating efficient transfer and sinking of heat from the DAP  722 . It is commonly known in the art of board level assembly that a material having a low thermal resistivity, such as copper, is formed on to a PCB to make thermal contact with the exposed DAP when mounted. Also, exposed DAPs are commonly used for a robust electrical ground. In high current applications, it is advantageous to have a robust electrical ground for optimum performance. In some embodiments, the leadframe strip  701  is a half etched leadframe. Half etched leadframes are commonly used and understood in the art of semiconductor manufacturing and methods to achieve them need not be recounted. The leadframe strip  701  is molded by a first mold compound  703  by any of the processes detailed in  FIGS. 4 and 5 . The tape  702  is removed forming a molded leadframe strip  705 . Next, semiconductor devices  706  are affixed onto the molded leadframe strip onto each individual position. In some embodiments, multiple devices  706  can be placed in each position as applications require. In application, heat generated by the bondwires is efficiently sunk to a PCB via the DAP, since the DAP is preferably made of metal or another material having a low thermal resitivity. Bondwires  707  are affixed to effectuate electrical contact between the molded leadframe strip  705  and the devices  706 . The molded leadframe strip  705 , devices  706  and bondwires  707  are encased in a second mold compound  710 . The second  710  and the first  703  are able to be identical mold compounds or different mold compounds as applications require. The double molded leadframe strip  705  is singulated by saw blades  712  forming individual EDAP package devices  790 . These individual devices are then able to be tested, marked and bulk packaged for shipping and assembly. It will be apparent to those of ordinary skill in the art of semiconductor device assembly that although few leads  720  are shown, many dozens to hundreds of leads are able to be realized using the process described herein. Furthermore, flexibility in routing I/O is advantageous, since end users can have specific demands as to the locations of I/O on a package landing pattern. To that end, a second leadframe (not shown) is able to be used. A second leadframe is able to couple to the first leadframe by use of a soft metal. The second leadframe is able to be used to route the I/O to any pattern required by an application, allowing great flexibility in footprints and landing patterns. 
         [0032]    While the invention has been described with reference to numerous specific details, one of ordinary skill in the art will recognize that the invention can be embodied in other specific forms without departing from the spirit of the invention. Thus, one of ordinary skill in the art will understand that the invention is not to be limited by the foregoing illustrative details, but rather is to be defined by the appended claims.