Abstract:
An active pixel sensor cell array in which a partial transimpedance amplifier amplifies the output of each cell. The pixel sensor cell array comprises a plurality of pixel sensor cells and a second part of the amplifier. Each pixel sensor cell comprises a photo-sensitive element, a capacitor and a first part of an amplifier. The capacitor is coupled between a terminal of the photo-sensitive element and an output line of the cell. The capacitor is operable to provide a capacitive feedback in the pixel sensor cell. The second part of the amplifier is coupled to the output lines of a plurality of pixel sensor cells. The amplifier is configured to amplify an output signal from a cell.

Description:
CLAIM OF PRIORITY 
     This patent application claims priority under 35 USC §119(e) to co-assigned U.S. Provisional Patent Application Ser. No. 60/383,861, filed on May 28, 2002, which is incorporated by reference. 
    
    
     BACKGROUND 
     Charge-coupled devices (CCDs) have been the dominant form of conventional imaging circuits for detecting and converting a packet of light photons into an electrical signal that represents the intensity of the light in a particular pixel region of the image. Most commonly, CCDs use a photogate to detect and store the light energy as electrical charge, and a series of electrodes to transfer the collected charge serially to an output. 
     CCDs have many advantages for obtaining very high quality images. These include high sensitivity, high well capacity, near unity fill factors, low leakage currents and mature processes optimized for imaging. However, CCDs also suffer from some system shortcomings, such as limited readout rates, high power dissipation that increases linearly with read rates, limited linearity and difficulty in integrating signal processing electronics onto the imager focal plane. 
     To overcome these limitations, recent imaging arrays use active pixel sensor (APS) cells to convert the light photons into electrical charge. With APS, a conventional photodiode is typically combined with MOS Field Effect Transistors (MOSFETs), which provide amplification, readout and timing control. 
     SUMMARY 
     An active pixel sensor cell array may be implemented with no more fixed pattern noise than a conventional CCD imager without unacceptably increasing the pixel cell size. In one implementation, an active pixel sensor cell in an active pixel sensor cell array improves performance by simultaneously increasing full well capacity, improving signal linearity, isolating the signal from spurious substrate noise and improving array uniformity (i.e., reducing array non-uniformity). 
     In one aspect, an active pixel sensor cell array has a high gain amplifier with capacitive feedback that amplifies the output of each cell of the array. The amplifier may be a transimpedance or partial transimpedance amplifier. One part of the high gain amplifier is a current sink, which may be implemented outside of the cells and shared by all cells connected in a column of the array. Another part of the amplifier may be implemented within each cell itself. The output amplification circuitry (amplifier part) within each cell may comprise either PMOS or NMOS type transistors. In one implementation, the output amplification circuitry within each cell may comprise only PMOS type transistors. In one implementation, a single-ended, inverting amplifier (which may also be cascoded) is the amplifier of choice within the pixel cell, while NMOS load circuitry outside of the cells may be shared by all cells of a column. By using PMOS transistors for the amplifier part within each pixel sensor cell, an additional benefit of immunity to substrate noise is gained at a cost of a slightly lower response to red wavelengths. 
     The high-gain, inverting amplifier may effectively be an op amp. In one implementation, the op amp for each cell comprises PMOS transistors and at least one NMOS transistor. In one implementation, no NMOS transistor is included within the cell itself. 
     In another implementation, a differential, inverting amplifier (which may also be cascoded) is the amplifier of choice within the pixel cell, while NMOS load circuitry outside of the cells may be shared by all cells of a column. By using differential architecture for the amplifier part within each pixel sensor cell, with either NMOS or PMOS transistors, an additional benefit of immunity to substrate noise is gained at a cost of a slightly lower response to red wavelengths. 
     The high-gain, inverting amplifier may effectively be an op amp. The op amp for each cell may comprise PMOS transistors and at least one NMOS transistor. Alternatively, no NMOS transistor may be included within the cell itself. 
     The amplifier design may improve the imager array performance by reducing fixed pattern noise in the image during readout, decreasing the gain non-uniformity of the array, and providing better control of array gain. 
     The details of one or more implementations are set forth in the accompanying drawings and description. Other features and advantages will be apparent from the description, drawings and claims. 
    
    
     
       DESCRIPTION OF DRAWINGS 
         FIG. 1  is a schematic diagram of two CMOS active pixel sensor cells using a conventional source follower design. 
         FIG. 2  is a schematic diagram of a portion of an active pixel sensor array that comprises two CMOS active pixel sensor cells according to one implementation. 
         FIG. 3  is a schematic diagram of a variation of the  FIG. 2  circuitry. 
       Like reference symbols in the various drawings indicate like elements. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  is a schematic diagram of two identical CMOS active pixel sensor cells  10 ,  11  (also called “pixels” or “cells”) that use a conventional source follower design. The cells  10 ,  11  are connected along a column of an active pixel sensor cell array and to circuitry  20 . Circuitry  20  is configured to read all cells connected along the column. 
     The cell  10  includes a photodiode d 1  connected between ground and Node  1 , which is coupled to a buffer transistor N 1 . N 1  is an NMOS transistor with a drain connected to the power supply node (Node  6 ) maintained at potential Vdd, a source connected to Node  2  and a gate connected to Node  1 . 
     Cell  10  also includes a row select transistor N 2  and a reset transistor N 3 , which are both NMOS transistors. Transistor N 2  has a drain connected to Node  2 , a source connected to Node  4 , and a gate connected to Node  3 . The gate of transistor N 2  is controlled by a ROW SELECT voltage supplied to Node  3 . 
     As shown in  FIG. 1 , circuitry  20  contains SIGNAL SAMPLING, CONDITIONING AND PROCESSING CIRCUITRY  21 , whose input terminal is connected to Node  4 . This circuitry  21  includes amplifiers and converters that output digital data indicative of light intensity incident at each selected cell along the column during the sampling period when each cell is selected. 
     The operation of reading each cell (e.g., cell  10 ) begins by briefly pulsing the gate of the cell&#39;s reset transistor N 3  with a high level RESET voltage. This high level of the reset voltage (typically equal to Vdd, where Vdd is typically 3.3 volts in modern CMOS processes) resets the voltage on photodiode d 1  to an initial integration voltage to begin an image integration cycle. 
     Immediately after the reset, the initial integration voltage on photodiode d 1  (the voltage at Node  1 ) is VINI=VRESET−VTN 3 −VCLOCK, where VTN 3  is the threshold voltage of transistor N 3 , VRESET is the high level RESET voltage signal, and VCLOCK represents capacitive feedthrough noise from the pulsed RESET voltage. The initial voltage at Node  2  is VRESET−VTN 3 −VCLOCK−VTN 1 , where VTN 1  is the threshold voltage of the buffer transistor N 1 , which is functioning here as a source follower. 
     After the reset voltage has been pulsed, and the voltage on photodiode d 1  (Node  3 ) has been reset, the gate of transistor N 2  is pulsed with a high level ROW SELECT voltage signal. The high level of the ROW SELECT voltage causes the voltage of Node  2  to appear at Node  4 . The signal sampling, conditioning and processing circuitry  21  then amplifies, digitizes and stores the value of the initial integration voltage as it appears at Node  4 . 
     Next, for a controlled time period, photons are allowed to impinge on d 1 , which creates electron-hole pairs. Photodiode d 1  is designed to limit recombination between the newly formed electron-hole pairs. 
     As a result, the photogenerated holes are attracted to the ground terminal of photodiode d 1 , while the photogenerated electrons are attracted to the positive terminal of photodiode d 1 . Each additional electron reduces the voltage at Node  1 . At the end of this image collection cycle, a final integration voltage will be present at Node  1 : VF=VINI−VS=VRESET−VTN 3 −VCLOCK−VS, where VS represents the change in the voltage due to the absorbed photons. Similarly, the final integration voltage at node  2  is VRESET−VTN 3 −VCLOCK−VS−VTN 1 . 
     At the end of the image collection cycle, the gate of transistor N 2  is pulsed again with a high level ROW SELECT voltage signal to cause the voltage at Node  2  to appear at Node  4 . This action generates data indicative of the number of photons that have been collected during the image collection cycle. The circuitry  21  calculates the difference between the digitized final integration voltage taken at the end of the cycle and the digitized stored initial integration voltage taken at the start of the cycle. 
     After the final integration voltage has been latched by detection and calculation circuit  21 , the RESET voltage is again pulsed at node  5  to reset the voltage on photodiode d 1  to begin another image collection cycle. 
     One problem with active pixel sensor cells is that during typical operation, the reset voltage line and the row select voltage line have high levels for periods that are sufficiently long to introduce a substantial amount of 1/f noise into the cell. Such 1/f noise, which results from trapping and de-trapping of surface charges can be accurately modeled as variations in the threshold voltages of transistors N 1  and N 3 . Due to such noise, the voltage that represents the number of photons that are absorbed by photodiode d 1  during an image collection cycle is corrupted by V1/f, which is the contribution of the variances of the threshold voltages of N 1  and N 3 . This contribution is an error that limits the accuracy of the cell. 
     Another problem is active pixel sensor cell arrays that use a conventional source follower amplifier in each cell as in  FIG. 1  are also subject to fixed pattern noise due to systematic and random variations between cells. Such fixed pattern noise is due to many different sources of gain variation that cannot easily be corrected with post processing techniques, such as correlated double sampling. It has been proposed to implement a better amplifier within each cell that would be less susceptible to such gain variations from cell to cell by including a CMOS amplifier within each cell. Such a CMOS amplifier includes at least one complimentary transistor (PMOS for NMOS based cells and NMOS for PMOS based cells) as a current source load for the high gain. Unfortunately, it is not currently possible to integrate such a complimentary structure into a single pixel cell without increasing the pixel size to an unacceptable degree. 
     Conventional CCD imagers are typically subject to significantly less fixed pattern noise than active pixel sensor cell arrays that use the conventional source follower architecture. 
     Another problem is active pixel sensor cell arrays that use a conventional source follower amplifier in each cell suffer from low voltage output dynamic range. For example, for a 5-Volt supply on Vdd in  FIG. 1 , the typical output dynamic range for the source follower pixel is approximately 1 Volt. For a 3.3-V supply, the typical output dynamic range for the source follower pixel is approximately 0.7 V. And for a 2.5-V supply, the typical output dynamic range for the source follower pixel is less than 0.5 V. This output voltage limitation limits the effective number of photons that can be absorbed by the pixel, and thus limits its dynamic range to a very low number. 
       FIG. 2  is a schematic diagram of a portion of an active pixel sensor array  102  that comprises two active pixel sensor cells  100 ,  110  according to one implementation. The cells  100 ,  110  are connected along a column of the active pixel sensor cell array  102 . Circuitry  200  is connected to the column and is configured to read all cells of the column. The circuitry  200  may comprise transistors N 4  and NS and current sources I Load to read cells  100  and  110  and any other cells connected along the column. In  FIG. 2 , transistors P 1 , P 2  and P 3  are PMOS transistors, and transistors N 4  and N 5  are NMOS transistors. In other implementations, the array  102  may comprise other transistors in addition to or instead of P 1 , P 2 , P 3 , N 4  and N 5 . 
     The pixel sensor cell  100  comprises PMOS transistors P 1 , P 2  and P 3 , photodiode d 1  and an integration capacitor c 1 . In one implementation, the column along which the cells  100  and  110  are connected has only two column lines C 1  and C 2 . C 1  is coupled to the source of P 1  and photodiode d 1 . C 2  is coupled to the drains of P 2  and P 3 , as well as integration capacitor c 1 . Thus, in an integrated circuit implementation, no extra wires need to be fabricated for the new pixel sensor cells  100 ,  110  compared to the circuit shown in  FIG. 1 . Thus, no extra space is needed for the wiring of the circuitry of the new pixel sensor cells  100 ,  110  compared to the conventional structure in  FIG. 1 . In fact, in one implementation, the only difference in the component count in each pixel of  FIG. 2  may be the addition of integration capacitor c 1 . 
     The dashed portions of lines C 1  and C 2  indicate that identical cells may also be connected along the array column in addition to cells  100  and  110 . It is contemplated that the array  102  may include a plurality of additional columns and rows of cells that are not shown. Thus, signals ROW SELECT and ROW RESET may be provided simultaneously to all cells connected along the same row as cell  100  but in different columns of the array  102 . 
     Similarly, signals ROW SELECTn and ROW RESETn may be provided simultaneously to all cells connected along the same row as cell  110 . Signals ROW SELECTn and ROW RESETn may have the same function as signals ROW SELECT and ROW RESET respectively, but may be pulsed independently from signals ROW SELECT and ROW RESET. If a separate signal sampling and processing circuit  210  is provided for each column, one cell from each column can be simultaneously read with other cells in the same row. 
     In operation, the pixel readout cycle begins with both ROW SELECT and ROW RESET pulsed low. These two signals pulsed low simultaneously represent a reset function for the pixel  100 . Transistor P 2  connects Node  40  to Node  20 . This connects the high-gain, single-ended amplifier P 1 , P 2 , P 3  and c 1  within the pixel  100  with the shared current source load transistor N 4  outside the pixel. Transistor P 3  connects Node  10  with Node  40  and forces them to have the same voltage, which forces the voltage across capacitor c 1  to be zero. 
     Once the reset is accomplished, ROW RESET is then brought to a high state, which disconnects Node  10  from Node  40 . The voltage at Node  40  at that moment is V INI =V dd −V TP1 −V CLOCK , where V dd  is the voltage of the power supply, V TP1  is the threshold voltage of transistor P 1 , and V CLOCK  represents capacitive feedthrough signal from the pulsed reset voltage ROW RESET. 
     After the RESET voltage is pulsed, and the voltage on photodiode d 1  (Node  10 ) is reset, the gate of transistor P 2  is still low with the low level of row select voltage signal ROW SELECT. This condition continues the operation of the amplifier. The signal sampling and processing circuitry  210  then amplifies, digitizes and stores the value of the initial integration voltage as it appears at Node  40 . 
     Once the sampling and processing function is completed, ROW SELECT is pulsed high, which disconnects pixel  100  from the column output bus C 2 . At that moment, the voltage on Node  10  becomes V DINI =V dd −V TP1 +V CLOCK  where V dd  is the voltage of the power supply, V TP1  is the threshold voltage of transistor P 1 , and V CLOCK  represents capacitive feedthrough noise from the pulsed reset voltage ROW RESET. 
     Next, for a controlled time period, photons are allowed to impinge on photodiode d 1  and create electron-hole pairs. Photodiode d 1  is designed to limit recombination between the newly formed electron-hole pairs. As a result, the photogenerated electrons are attracted to the Vdd terminal of photodiode d 1 , while the photogenerated holes are attracted to the negative terminal of photodiode d 1 . Each additional hole increases the voltage at Node  10 . At the end of this image collection cycle, a final integration voltage will be present at Node  10 . The final integration voltage is V DF =V DINI +V S =V dd −V TP1 +V CLOCK +V S , where V S  represents the change in the voltage due to the absorbed photons. V S  is proportional to the number of holes that arrived at Node  1 . Following the formula of Voltage change=Charge change/Capacitance, then V S =Q in /C N1 , where C N1  is the total capacitance on Node  10 , including the diode capacitance, the capacitance of the gate of P 1  and any other parasitic capacitances of the metal and poly lines in the pixel  100 . 
     At the end of the image collection cycle, the gate of transistor P 2  is pulsed again with a low level ROW SELECT voltage signal. This signal again activates the amplifier in pixel  100 . Because the amplifier is an inverting, high-gain amplifier, Node  10  becomes a virtual ground when the amplifier is activated. Thus, the voltage at Node  10  very quickly goes from V DF  back to V DINI . The activated amplifier of pixel  100  now acts as a very high quality charge integrator. Since the amplifier is inverting, the voltage at Node  40  goes negative until it reaches V F =V INI −V Sc1 , where V Sc1 =V S *C N1 /c 1 , where V S  represents the change in the voltage due to the absorbed photons, C N1  is the total capacitance on Node  10 , and c 1  is the capacitance of the capacitor c 1  in pixel  100 . 
     Once the voltage V F  has settled on the column output line C 2  (Node  40 ), the signal sampling and processing circuitry  210  then amplifies, digitizes and stores the value of the final integrated voltage as it appears at Node  40 . Once the sampling and processing function is completed, ROW RESET is pulsed low again on Node  50 , which resets the photodiode d 1 . Then ROW SELECT is asserted high, which disconnects pixel  100  from the column output bus C 2  to begin another image collection cycle. 
     Once this process is complete, the ROW RESET and ROW SELECT cycle may be repeated on cell  110  and so on until the entire column of pixels is read out in turn and processed by the signal sampling and processing circuitry  210 . 
     By using the saved initial integration voltage V INI  and subtracting it from the final integrated voltage V F , the signal sampling and processing circuitry  210  is left with the voltage difference of V F −V INI =V Sc1 , where V Sc1 =V S *C N1 /c 1 , and V S =Q in /C N1 . By combining these two equations, it is clear that V Sc1 =C N1 /c 1 *Q in /C N1 =Q in /c 1 , while all the parasitic and poorly controlled stray capacitances in the pixel cancel themselves out. Thus, the output of the pixel  100  may depend only on the capacitance of capacitor c 1 , which may be controlled to a precision of about 1 in 1000. For example, 5 fF for low Dynamic Range and up to 15 fF for high Dynamic Range. Thus, the gain uniformity of the pixel array  102  may be controlled to approximately 0.1%, which may be limited only by the uniformity of c 1 . 
     The capacitive feedback in the pixel  100  of  FIG. 2  may result in stray insensitive gain resulting in lower gain variation across the array. 
     The PMOS pixel implementation of  FIG. 2  may achieve junction isolation between the PMOS pixel and the P-Substrate that may normally contain digital feedthrough noise. 
     No additional lines may be needed for the NMOS pixel implementation to provide ground connection to pixel substrate. This allows back thinning of the pixel array for high sensitivity. 
     An inverting amplifier configuration may increase the voltage dynamic range of the pixel by factor of two (×2). 
       FIG. 3  is a schematic diagram of a variation of the  FIG. 2  circuitry. These pixels  300  use a cascode signal for the row selection function. 
     A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made. For example, a different number of transistors may be implemented in the pixel  100  than the number of transistors shown in  FIG. 2 . As another example, the pixel  100  may comprise other components, such as NMOS transistors, in addition to or instead of the components shown in  FIG. 2 . 
     In another example, a different number of capacitors may be implemented in the pixel  100  than the number of capacitors shown in  FIG. 2  for variable gain and/or multiple gain settings. In addition, non-linear capacitive elements may be implemented in the pixel  100  of  FIG. 2  for gain compression. 
     Another implementation replaces diode D 1  in pixel  100  as shown in  FIG. 2  by other photo-sensitive elements such as a bipolar junction transistor (BJT) (either PNP or NPN polarity transistors). Additional implementation replaces diode D 1  in pixel  100  by a Photogate element. In another example, the diode D 1  can be further replaced by a deposited photo sensor on the top of the pixel. In addition, diode D 1  in pixel  100  can be replaced by a multiple charge collection photo sensitive elements. As another example, diode D 1  in pixel  100  can be replaced by a hybrid interconnected photo sensitive sensor on the top of the pixel. 
     Accordingly, other implementations are within the scope of the following claims.