Abstract:
Methods and apparatuses for manufacturing self-aligned integrated back contact heterojunction solar cells are provided. In some embodiments, systems for forming a solar cell on a substrate are provided, the systems comprising: a master shadow mask positioned adjacent to the substrate on a first side of the master shadow mask; a first blocking mask placed adjacent to a second side of the master shadow mask; and a deposition machine that deposits material on the substrate through holes in the master shadow mask and the first blocking mask.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application claims the benefit of U.S. Provisional Patent Application No. 61/977,383, filed Apr. 9, 2014, which is hereby incorporated by reference herein in its entirety. 
    
    
     STATEMENT REGARDING GOVERNMENT FUNDED RESEARCH 
     This invention was made with government support under Grant No. 1041895 awarded by the National Science Foundation. The government has certain rights in the invention. 
    
    
     TECHNICAL FIELD 
     The disclosed subject matter relates to methods and apparatuses for manufacturing self-aligned integrated back contact heterojunction solar cells. 
     BACKGROUND 
     It is known that solar cells with both emitter and base contacts on the rear surface of the solar cell&#39;s substrate provide high efficiency and simplify the interconnection of cells together into a module. However, manufacturing such cells is expensive due to the difficulty of placing the closely spaced emitter and base contacts on the cells&#39; substrates. Additionally, placing emitter/base metal on the cell&#39;s substrate requires carefully aligned photolithography and/or screen printed layers to prevent shorting and yield loss. 
     Accordingly, it is desirable to provide new methods and apparatuses for manufacturing self-aligned integrated back contact heterojunction solar cells. 
     SUMMARY 
     Methods and apparatuses for manufacturing self-aligned integrated back contact heterojunction solar cells are provided. In some embodiments, systems for forming a solar cell on a substrate are provided, the systems comprising: a master shadow mask positioned adjacent to the substrate on a first side of the master shadow mask; a first blocking mask placed adjacent to a second side of the master shadow mask; and a deposition machine that deposits material on the substrate through holes in the master shadow mask and the first blocking mask. 
     In some embodiments, methods for forming a solar cell on a substrate are provided, the methods comprising: positioning a master shadow mask adjacent to the substrate on a first side of the master shadow mask; placing a first blocking mask adjacent to a second side of the master shadow mask; and depositing material on the substrate through holes in the master shadow mask and the first blocking mask. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Various objects, features, and advantages of the disclosed subject matter can be more fully appreciated with reference to the following detailed description of the disclosed subject matter when considered in connection with the following drawings, in which like reference numerals identify like elements. 
         FIG. 1  shows an example of a process for manufacturing self-aligned integrated back contact heterojunction solar cells in accordance with some embodiments of the disclosed subject matter. 
         FIG. 2  shows examples of a master shadow mask and a blocking mask for manufacturing self-aligned integrated back contact heterojunction solar cells in accordance with some embodiments of the disclosed subject matter. 
         FIGS. 3-5  show cross-sectional views of an example of a solar cell during fabrication steps in accordance with some embodiments of the disclosed subject matter. 
         FIG. 6  shows a 3D view of an example of an alignment of a master shadow mask and a blocking mask using pins built into a wafer carrier in accordance with some embodiments. 
         FIG. 7  shows examples of large area masks in accordance with some embodiments of the disclosed subject matter. 
     
    
    
     DETAILED DESCRIPTION 
     In accordance with various embodiments, as described in more detail below, mechanisms, which can include methods and apparatuses, for manufacturing self-aligned integrated back contact heterojunction solar cells are provided. 
     These mechanisms can be used in conjunction with any suitable solar cell technologies. For example, in some embodiments, the mechanisms described herein can be used to form interdigitated p-type and n-type amorphous silicon (a-Si) strips and corresponding transparent conductive oxide (TCO) and metal layers for silicon heterojunction interdigitated back contact (SHJ-IBC) high efficiency solar cells using only a single alignment step and without using any resist patterning. 
     In some embodiments, the mechanisms described herein can use self-aligned shadow masks to replace more expensive pattern and etch or liftoff technologies. For example, the mechanisms described herein can use a master shadow mask with an overlying blocking mask to selectively generate self-aligned emitter and base structures without a critical or fine line patterning step. 
     In some embodiments, the mechanisms described herein can be used to deposit p-type and n-type a-Si layers, TCO layers, and metal layers through a stack of shadow masks, to form a low resistance tunnel junction between deposited p-type and n-type a-Si layers, and to form emitter and base contacts. 
     Turning to  FIG. 1 , an example of a process for manufacturing self-aligned integrated back contact heterojunction solar cells in accordance with some embodiments of the disclosed subject matter is shown. 
     As illustrated, process  100  can begin by preparing a substrate at  110 . In some embodiments, the substrate can be any suitable type, can contain any suitable material or combination of materials, and can be prepared using any suitable technique or combination of techniques. For example, the material of the substrate can be silicon (Si), germanium (Ge), germanium silicon (GeSi), silicon carbide (SiC), or any other suitable semiconductor material. As another example, the substrate can be an n-type or p-type substrate which can be doped with a corresponding type of impurity ions such as boron ions, gallium ions, indium ions, and/or various combinations of such ions. In a more particular example, as described below in connection with  FIG. 3 , the substrate can be a single side textured n-type Czochralski (CZ) silicon wafer  310 . 
     In some embodiments, process  100  can process the surfaces of the substrate for any suitable purposes such as cleaning and/or texture etching. For example, a surface field can be formed and surface passivation can be achieved by thermal oxidation. As another example, an amorphous silicon (a-Si) surface passivation technology can be used to apply a-Si layers as passivating layers in a-Si/silicon dioxide (SiO 2 ) nitride silicon (SiN x ) stacks to the surface of the substrate. In a more particular example, as described below in connection with  FIG. 3 , a stack of intrinsic amorphous silicon ((i)a-Si) and SiN x  can be formed to serve as a surface passivation coating and an antireflection coating, respectively, at the front surface of the substrate (the surface where the light enters), while a layer of (i)a-Si can be formed on the rear surface to provide a surface passivation coating. 
     Next, at  120 , process  100  can align a master shadow mask to the prepared substrate. In some embodiments, one or more shadow masks can be fabricated from any suitable material by any suitable technique. For example, a master shadow mask can be fabricated from a stainless steel sheet by laser cutting. As another example, a master shadow mask can be fabricated from ceramic material using a precision casting mold. In some embodiments, the master shadow mask can be loosely aligned and fixed to the rear of the prepared substrate in any suitable manner. For example, the master shadow mask can be attached by clamping. As another example, if a master shadow mask is fabricated by appropriate materials, it can be aligned by use of magnets. 
     At  130 , process  100  can determine whether one or more blocking masks are going to be aligned. In some embodiments, at  132 , in response to determining that one or more blocking masks are going to be aligned (“YES” at  130 ), process  100  can align the one or more blocking masks on top of the master shadow mask to cover selected openings in the master shadow mask. In some embodiments, a blocking mask can be attached to the master shadow mask in such a way that the blocking mask can be removed without disturbing the alignment between the master shadow mask and the substrate. 
     In some embodiments, process  100  can use any suitable method to increase the alignment tolerance. For example, process  100  can enlarge the openings in the blocking masks so that they are oversized compared to the openings in the master shadow mask in order to make the alignment easier. As another example, alignment crosses in the mask periphery can be used to improve alignment accuracy. As yet another example, the alignment on large areas can be done by optical cameras, which can be used to align screen printing patterns. 
     At  134 , process  100  can perform deposition with the combined master shadow mask and one or more blocking masks in place. In some embodiments, one or more deposition processes can be performed using any suitable technique such as physical vapor deposition, chemical vapor deposition, electrochemical deposition, molecular beam epitaxy, atomic layer deposition, etc. In some embodiments, a deposition process can transfer a material through openings of the stacked master shadow mask and one or more blocking masks onto the substrate to form a thin film. In a particular example, as described below in  FIG. 4 , a low temperature plasma-enhanced chemical vapor deposition (PECVD) process can deposit (p+) a-Si material through the openings  414  of the combined master shadow mask  210  and blocking mask  220  to form heterojunction  440 . 
     At  136 , process  100  can remove the outer layer blocking mask without disturbing the other mask(s). Next, if there is one or more blocking masks combined with the master shadow mask (“NO” at  138 ), process  100  can return to  134  to perform further deposition. Alternatively, if there is only the master shadow mask left (“YES” at  138 ), process  100  can return to  130  to determine whether another set of one or more blocking masks need to be aligned. 
     In some embodiments, in response to determining that no more blocking masks need to be aligned (“NO” at  130 ), process  100  can perform deposition with the master shadow mask at  140 . In some embodiments, a plurality of layers can by formed by multiple deposition processes. For example, as described below in  FIG. 5 , an (n+) a-Si layer, a transparent conductive oxide (TCO) layer, and a metal layer can be formed by depositing corresponding materials through the openings of the master shadow mask successively. Similarly, one or more deposition processes can be performed using any suitable technique. For example, an (n+) a-Si layer can be formed using a low temperature PECVD technique. As another example, metal can be deposited using physical vapor deposition (e.g., evaporation, sputtering, etc.) to provide highly conductive connections. 
     Next, at  150 , the master shadow mask can be removed and process  100  can determine if another deposition with another master shadow mask is going to be performed at  160 . For example, for improving reliability, an additional coating of dielectric protection (e.g., PECVD silicon nitride) may be added in some embodiments. In such an example, in response to determining that another master shadow mask needs to be aligned (“YES” at  160 ), process  100  can return to  120  to align another master shadow mask which can leave exposed metal regions for solder connections (for example) in the module. In some embodiments, if the determination at  160  is “NO”, process  100  can end. 
     It should be noted that the above steps of the flow diagram of  FIG. 1  can be executed or performed in any order or sequence not limited to the order and sequence shown and described in the figure. Also, some of the above steps of the flow diagram of  FIG. 1  can be executed or performed substantially simultaneously where appropriate or in parallel to reduce latency and processing times. Furthermore, it should be noted that  FIG. 1  is provided as an example only. At least some of the steps shown in the figure may be performed in a different order than represented, performed concurrently, or altogether omitted. 
     Turning to  FIG. 2 , an example  210  of a master shadow mask and an example  220  of a blocking mask in accordance with some embodiments of the disclosed subject matter are shown. In some embodiments, master shadow mask  210  and blocking mask  220  can be made from any suitable material or combination of materials. For example, one or more masks can be made of material stiff enough (e.g., various ceramic materials) for use in PECVD and sputtering chambers. As another example, one or more masks can be made from magnetic materials and can be held in place with small permanent magnet holders. In a more particular example, master shadow mask  210  and blocking mask  220  can be fabricated from 127 μm thick stainless steel sheets by laser cutting. 
     As illustrated in  FIG. 2 , the patterns of master shadow mask  210  and blocking mask  220  are shown in top view. As shown, master shadow mask  210  can have an approximately 100 μm-wide and 12-cm-long serpentine line which divides a rectangle opening in the four-border frame into two parts: n-type opening  212 ; and p-type opening  214 . As also shown, blocking mask  220  can have p-type opening  224 , and can block the region corresponding to the n-type opening  212  in the master shadow mask. In some embodiments, p-type opening  224  in the blocking mask  220  can be oversized compared to the p-type opening  214  in the master shadow mask to ease alignment. 
     In some embodiments, when making large area masks, for example, as illustrated in  FIG. 7 , serpentine line structure  711  in shadow mask  710  can be unstable and fragile. To solve this problem, any suitable manufacturing technique can be used to consolidate and/or enhance the patterned structures of large area masks. For example, bridges  722  can be used to support serpentine line structure  711 . As another example, teeth of comb structures  733  and  735  can be used to make an enhanced shadow mask  730  with serpentine line gap. 
       FIGS. 3-5  show cross-sectional views of an example of a solar cell during fabrication steps in accordance with some embodiments of the disclosed subject matter. 
     Referring to  FIG. 3 , a single side textured n-type crystal silicon solar substrate passivated with (i)a-Si and SiN x  anti reflection coating is shown in cross-sectional view in accordance with some embodiments. In some embodiment, an n-type single crystal silicon wafer  310  can be grown by the Czochralski process. In some embodiments, wafer  310  can be a pseudosquare in shape with 3-4 Ohm-cm resistivity and 120 μm thicknesses. 
     In some embodiments, wafer  310  can be textured in potassium hydroxide iso-Propyl alcohol (KOH-IPA) solution with the rear side protected by a SiNx layer. After a KOH cleaning, (i)a-Si passivation layers  320  can be formed by deposition on both sides of wafer  310  using a standard Applied Materials P-5000 cluster PECVD. Then, a SiNx layer  330  can be formed by deposition on the front side of wafer  310  to serve as an antireflection coating. 
     Next, referring to  FIG. 4 , deposition of a (p+) a-Si layer  440  through the stack of master shadow mask  210  and blocking mask  220  is shown in cross-sectional view in accordance with some embodiments. 
     Firstly, a master shadow mask  210  and a blocking mask  220  can be aligned adjacent to the rear surface of wafer  310 . In such an alignment, n-type opening  412  can be covered by blocking mask  220 , while p-type opening  414  can be exposed. 
     In some embodiments, master shadow mask  210  can taped to the rear side of wafer  310  by Kapton tape, while blocking mask  220  can be manually aligned and attached over the master shadow mask  210  by magnetic coupling with magnets located underneath wafer  310  on the carrier (not shown). In some other embodiments, as illustrated in  FIG. 6 , master shadow mask  210  and blocking mask  220  can be aligned using the pins  610  built into the wafer carrier  620 . 
     Then, a plasma-enhanced chemical vapor deposition (PECVD) process can deposit (p+) a-Si material through p-type opening  414  of the stack of master shadow mask  210  and blocking mask  220  to generate (p+) a-Si layer  440 , forming a p-tunnel junction contact (heterojunction). 
     Turning to  FIG. 5 , deposition of an (n+) a-Si layer  550 , a TCO layer  560 , and a metal layer  570  through master shadow mask  210  is shown in cross-sectional view in accordance with some embodiments. In some embodiments, after (p+) a-Si layer  440  is deposited, blocking mask  220  can be removed without disturbing master shadow mask  210 . Subsequently, (n+) a-Si layer  550  can be deposited by PECVD through n-type opening  412  and p-type opening  414  of master shadow mask  210 , forming a base contact in regions where no p+ layer  440  is present, and forming an emitter contact (tunnel junction contact) to p+ layer  440  where it is present. The thickness of (n+) a-Si layer  550  can be varied and related to the open-circuit voltage (Voc) and the fill factor (FF) optimization parameters. 
     Next, transparent conductive oxide (TCO) layer  560  and metal layer  570  can be respectively deposited through n-type opening  412  and p-type opening  414  of master shadow mask  210 . In some embodiments, TCO layer  560  and metal layer  570  can be deposited using any suitable physical vapor deposition (PVD) system such as a KDF  954  sputtering tool available from KDF Electronic &amp; Vacuum Services Inc. of Rockleigh, N.J. 
     Finally, although not shown in  FIG. 5 , master shadow mask  210  can be removed and a SiNx capping layer can be deposited on the entire rear surface to protect (i)a-Si exposed in the gaps between n-type and p-type strips. The cells then can be probed by punching through SiNx layer. For the cells to be interconnected in photovoltaic (PV) modules, SiNx can be, for example, opened locally at the interconnection islands by etching. In this case, the alignment tolerance can be on the order of millimeters. 
     The provision of the examples described herein (as well as clauses phrased as “such as,” “e.g.,” “including,” and the like) should not be interpreted as limiting the claimed subject matter to the specific examples; rather, the examples are intended to illustrate only some of many possible aspects. 
     Accordingly, methods and apparatuses for manufacturing self-aligned integrated back contact heterojunction solar cells are provided. 
     Although the disclosed subject matter has been described and illustrated in the foregoing illustrative embodiments, it is understood that the present disclosure has been made only by way of example, and that numerous changes in the details of embodiment of the disclosed subject matter can be made without departing from the spirit and scope of the disclosed subject matter, which is limited only by the claims that follow. Features of the disclosed embodiments can be combined and rearranged in various ways.