Abstract:
A Class AB amplifier ( 10 ) having a top booster section ( 14 ) and a bottom booster section ( 12 ) adapted to prevent crossover distortion, latchup, and provides high output voltage swing output. The amplifier  10  has a positive feedback loop including a current mirror comprising transistors (M 1,  M 2 ) that get activated during extreme sourcing conditions. The feedback loop provides the necessary biasing current to a biasing transistor (Q 9 ) of an output sinking transistor (Q 11 ) to allow high output sourcing current and high sinking current to prevent crossover distortion and latching. The output transistors (Q 8,  Q 9,  Q 10  and Q 11 ) of the amplifier ( 10 ) are all NPN-type transistors.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention is related to amplifiers circuits, and more particularly to Class AB amplifier circuits.  
         BACKGROUND OF THE INVENTION  
         [0002]    There are a variety of amplifiers circuits available to a circuit designer, with some of the widely known types being Class A, Class B and Class AB amplifiers. It is widely known that Class A amplifiers have high fidelity but have poor efficiency. Class B amplifiers are known to have high efficiency, but poor fidelity. Class AB output stages attempt to achieve a compromise between the two. Class AB amplifiers have a relatively high efficiency by quiescently biasing the amplifier with substantial current, enough to drive it up to a given low impedance load where the amplifier has a Class A operation. As the load impedance gets lower the Class AB amplifier starts diverting some portion of the quiescent current towards the base of the output transistors, thus unwantedly debiasing the critical circuitry driving the output transistors. At this point the amplifier is purely a Class B amplifier, whereby cross-over distortion is inevitable. At this point, the fidelity of the amplified signal rapidly degrades.  
           [0003]    The traditional Class AB bipolar junction transistor (BJT) output stage has the characteristics of very low quiescent power consumption with no resistive load, and a significantly larger sinking and sourcing current driving capability with a low impedance load. The traditional way that this is achieved is by quiescently biasing the amplifier in such a way that if a low impedance load is applied to the output, current once utilized to quiescently bias the amplifier is then re-diverted towards the base of the amplifier&#39;s output transistors, while the rest of the amplifier is left with enough current to maintain its critical circuitry “on”. However, if there is not enough quiescent current leftover when driving the given low impedance load, the critical circuitry in the amplifier will be “starved” in the effort to drive the given load, thus undesirably driving the transistors of the amplifiers critical circuitry into “cut off”. This exacerbates the effort that the amplifier has to do to bring the transistors back “on”, biased and ready for the next amplifier output transition. This results in crossover distortion due to the “off” time of those output transistors involved. This will be the case for both the rising and falling output transitions of the amplifier. For the existing approaches, amplifiers are specified to drive a minimum impedance load with a given crossover distortion, subjecting the amplifier to higher quiescent currents when lower impedance loads are required to be driven. Applying loads beyond these minimum impedance low limits will result in the considerable crossover distortion already mentioned.  
           [0004]    Another problem is that amplifiers having all NPN output stages are limited in output drive, which drive is based upon the amount of quiescent current that the designer establishes and accepts for the all NPN output stage, i.e., the amount of nominal current the circuit draws in a no load situation.  
           [0005]    There is desired an improved Class AB amplifier that has a fast and stable feedback mechanism to maintain its critical circuitry “on” during both sinking and sourcing conditions, and also which can achieve higher output currents with nominal quiescent current without the risk of circuit latchup.  
         SUMMARY OF THE INVENTION  
         [0006]    The present invention achieves technical advantages as a power efficient, all NPN, high output voltage swing Class AB output stage with self current compensation to critical circuitry for unlimited sinking and sourcing drive capability, while maintaining a crossover distortion free amplifier, this circuit achieving higher output currents with nominal quiescent current without the risk of circuit latchup. As a result, the architecture maintains high efficiency and high fidelity for almost any resistive load by keeping all the amplifier&#39;s critical circuitry “on”, independent of the load. The present invention provides a negative feedback, self-regenerative bias current OP Amp for sinking and sourcing modes, thereby providing unlimited driving capability, with improved circuitry to achieve nominal quiescent current without circuit latchup.  
           [0007]    In a first embodiment of the present invention, there is provided an all NPN output stage Class AB amplifier including a first current mirror providing additional positive feedback to the output transistors such that when the output transitions from a sourcing mode to a sinking mode, the critical output circuitry will remain “on” to prevent the output signal from crossover distortion, thus maintaining high fidelity.  
           [0008]    In a second embodiment of the present invention, there is provided additional circuitry in an all NPN output stage, allowing higher output currents to be provided in the sinking mode with a nominal quiescent current, the additional circuitry preventing latchup of the critical output circuitry while providing an improved current boosting scheme. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]    [0009]FIG. 1 is a schematic drawing of a preferred embodiment of the invention depicting a Class AB amplifier having an improved bottom booster section preventing crossover distortion in a sinking mode, and having an improved top booster section providing current boosting and preventing latchup; and  
         [0010]    [0010]FIG. 2 is a schematic diagram of an alternative Class AB output stage subject to latchup.  
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0011]    Referring now to FIG. 1, there is depicted a Class AB amplifier  10  having a bottom booster section  12  and an upper booster section  14 . The bottom booster  12  is composed of transistors M 1 , M 2 , Q 1 , Q 2 , Q 12  and Q 13 , and emitter degeneration resistors R 1  and R 3 . The top booster  14  consists of transistors M 3 , M 4 , Q 3 , Q 4 , Q 5 , Q 6 , Q 7 , emitter degeneration resistor R 2 , and diodes D 1 , D 2 , D 3  and D 4 . Amplifier  10  has output transistors Q 10  and Q 11 . Transistors Q 8  and Q 9  set the quiescent current to the amplifier&#39;s output transistors Q 10  and Q 11 . The current sources IQ 1 , IQ 2 , IQ 3  and IQ 4  set the quiescent current and the thresholds at which the top and bottom booster start operating. The amplifier&#39;s input signal is presented at the base of transistors Q 1  and Q 2 . The bottom booster  12  will be described in detail first, and followed by a detailed description of the upper booster  14 .  
         [0012]    Referring first to bottom booster  12 , the bottom booster  12  comprises a current mirror formed by transistors Q 1  and Q 2 , a current mirror formed by M 1  and M 2 , a diode connected transistor Q 12  with an emitter degeneration resistor R 1 , transistor Q 13  and an emitter degeneration resistor R 3 . Transistor Q 12  and emitter degeneration resistor RI set the quiescent current in transistors Q 1  and Q 2 . The current of transistor Q 2  is initially provided by the current source IQ 2 . Current source IQ 2  also provides the quiescent current to transistor Q 13 . The current conducted through transistor Q 1  is initially provided by a current mirror formed by PMOS transistors M 5  and M 6 , and is quiescently set by current IQ 4  and the collector current through transistor Q 4 . This current is set by the translinear loop formed by diodes D 1 , D 2 , D 3  and D 4 , and transistors Q 3 , Q 4 , Q 5  and Q 6 . A portion of the current from the PMOS transistors M 5  and M 6  mirror is diverted towards transistors Q 8  and Q 9  to provide the quiescent biasing to the output transistors Q 10  and Q 11 . Also, the collector current in transistor Q 4  is set to be very low during both quiescent and sinking conditions.  
         [0013]    Bottom booster  12  operates as follows. When the output voltage at output V out  transitions from high to low, depending on the amplifier&#39;s output load, the bottom output transistor Q 11  has to be able to pull current IL (Vout/Rload) out of the output load down to the VEE rail, assuming that the amplifier&#39;s load is to ground and the amplifier  10  has split power supplies with respect to ground. The current that transistor Q 11  pulls down will be limited in the first place by the current available to drive it&#39;s base, and secondly by the base current provided to transistors Q 1  and Q 2 . Notice that transistors Q 1  and Q 2  and output transistor Q 1  form a Darlington pair such that the output current sinking capability of amplifier  10  will be at least the base current provided to transistor Q 1  times hfe (Q 1 ) times hfe (Q 11 ). This second limitation is not significant, given that it is at least three orders of magnitude smaller than the output sinking capability of the amplifier  10  via transistor Q 11 , assuming the hfes of these transistors to be about 30. Notice, also, that quiescently there is an insignificant amount of base current provided to transistor Q 11 . This current comes from transistors Q 1  and Q 2 , and it is set mostly by the current sources IQ 2  and IQ 4 .  
         [0014]    Now, when there is a low impedance load at the amplifier&#39;s output V out , and the output is transitioning from sourcing into sinking mode, initially transistor Q 2  will get current from the current source IQ 2 . Once the current needed by Q 2  exceeds IQ 2 , the PMOS transistor M 2  will provide the extra needed current. This amount of extra current will then get mirrored onto transistor M 1  and will be fed back into transistor Q 1 , preventing it&#39;s saturation and thus providing the extra current needed to drive the output transistor Q 1 .  
         [0015]    Notice that the current through the rest of the amplifier  10  has not changed from what it is quiescently set as. So, as a result of this, so far the output sourcing transistor Q 10  and it&#39;s biasing diode have not changed from the quiescent operating point, thus maintaining the amplifier&#39;s critical circuitry “on.” Notice though, that in order to prevent biasing transistor Q 9  from saturating during sinking conditions, current needs to be supplied to transistor Q 9  whenever it needs it.  
         [0016]    In the prior art Class AB amplifiers, this current would typically come from the output load through resistor Rout. This current builds a DC voltage drop across resistor Rout that then gets imposed on the transistor Q 10  base-emitter junction, so that for extreme sinking conditions, the DC voltage drop across resistor Rout will eventually reverse bias the transistor Q 10  base-emitter junction, and turn output transistor Q 10  “off.” This, if not prevented, will cause the output signal to have cross over distortion, thus rapidly degrading the fidelity of the amplifier&#39;s output signal.  
         [0017]    Advantageously, according to the present invention, in order to prevent cutoff of output transistor Q 10 , the transistor Q 13  and its emitter degeneration resistor R 3  mirror the current in biasing transistor Q 9 . Notice that this extra current will be provided by transistor M 2 , which current will mirror into transistor M 1  that will replace current back to biasing transistor Q 9  through transistor Q 8 . Notice also that even though the current will increase through transistor Q 8 , the emitter degeneration resistor R 4  of transistor Q 9  keeps this current relatively small when compared with transistor Q 11  current. Also, due to the 1 to 10 ratioing, the current through output transistor Q 10  stays very small overall. The benefit of this topology, when compared with others available, is that it provides not just base current to the output transistors Q 10  and Q 11 , but also rebiases the critical circuitry of the amplifier  10  such that cross over distortion is fully prevented.  
         [0018]    Advantageously, when this bottom booster  12  is combined with the top booster  14 , that basically has the same function of this bottom booster, but gets activated during the sourcing condition, there is achieved a Class AB amplifier having almost infinite driving capability during both sinking and sourcing conditions, and extremely high fidelity typical of the Class A amplifier with a very minimal quiescent current, typical of the Class AB amplifier.  
         [0019]    Referring now to FIG. 2, there is shown an alternative top booster at  18  which will be described first. Transistors Q 4 ′, Q 5 ′, Q 6 ′, Q 3 ′ and Q 2 ′ form the quiescent current control loop for low amounts of current sunk into load, R 2 ′ has a small effect, and the quiescent current of the output is controlled by current I 2 ′ and the emitter area ratios of transistors Q 2 ′, Q 3 ′, Q 4 ′, Q 5 ′ and Q 6 ′.  
         [0020]    When sinking large currents, a voltage develops across resistor R 2 ′allowing the current in transistor Q 2 ′ to increase faster than the current in transistor Q 6 ′, this maintains bias current in the highside NPN transistor Q 1 ′ which in turn leads to low crossover distortion and good linearity.  
         [0021]    When sourcing current, transistor Q 2 ′ starts to turn off, along with transistors Q 3 ′, Q 4 ′, Q 5 ′, Q 6 ′, this allows more of current I 2 ′ to flow into the base of transistor Q 1 ′.  
         [0022]    On the limit, when transistor Q 2 ′, Q 3 ′, Q 4 ′, Q 5 ′ and Q 6 ′ are off, all of current  12 ′ flows into the base of transistor Q 1 ′ and the output can no longer source additional current. At low temperatures or for low values of beta, current I 2 ′ will need to be quite large if the output stage is needed to deliver large amounts of high-side output current.  
         [0023]    Referring now back to FIG. 1 top booster  14  provides an advantageous boosting scheme. Transistors M 3  and M 4  form one current mirror, and transistors M 5  and M 6  form another.  
         [0024]    Transistors Q 5 , Q 6 , M 3 , M 4  and Q 4  form a simple positive feedback loop. Transistor Q 5  measures the base current in transistor Q 6 , and then mirrors this current back round to the base of transistor Q 4 , essentially squaring the beta (β) of transistor Q 4  with the addition of some positive feedback.  
           IM 4 =IQ 1+ IQ 4 /Iβ   
         [0025]    This means that the current in transistor M 4  adjusts itself to ensure that it is equal to the base current of transistor Q 4  plus current IQ 1 . Any surplus current is sunk into transistor Q 7 .  
         [0026]    Since transistor Q 7  can sink away any surplus current, the circuit  10  can not latch. So, now the current of transistor M 3  adjusts itself to provide for the base current of output transistor Q 11  allowing the output stage to source much more current than it previously could. Transistor Q 3 , and diodes D 1 , D 2 , D 3  and D 4  prevent transistor Q 7  from saturating when sinking large amounts of current.  
         [0027]    Though the invention has been described with respect to a specific preferred embodiment, many variations and modifications will become apparent to those skilled in the art upon reading the present application. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the prior art to include all such variations and modifications.