Abstract:
A write driver system includes a logic circuit including first switching devices which receive input write signals and generate control signals. A plurality of predriver circuits includes second switching devices and generates drive signals based on the control signals. A write drive circuit includes third switching devices and generates write drive signals based on the drive signals. The third switching devices have higher threshold voltages than the first and second switching devices.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 11/511,138, filed on Aug. 28, 2006, which is a continuation of U.S. patent application Ser. No. 10/816,394 filed on Apr. 1, 2004. The disclosures of the above applications are incorporated herein by reference. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to data storage systems, and more particularly to a write driver system for a write head in a magnetic data storage system. 
     BACKGROUND OF THE INVENTION 
     Referring now to  FIG. 1 , an exemplary data storage device  20  is shown. A buffer  24  stores data that is associated with the control of a hard disk drive. The buffer  24  may employ SDRAM or other types of low latency memory. A processor  26  performs processing that is related to the operation of the hard disk drive. A hard disk controller (HDC)  30  communicates with the buffer  24 , the processor  26 , a host  34 , a spindle/voice coil motor (VCM) driver  36 , and/or a read/write channel circuit  40 . 
     During a write operation, the read/write channel circuit (or read channel circuit)  40  encodes the data to be written onto the storage medium. The read channel circuit  40  processes the signal for reliability and may include, for example error correction coding (ECC), run length limited coding (RLL), and the like. During read operations, the read channel circuit  40  converts an analog output from the medium to a digital signal. The converted signal is then detected and decoded by known techniques to recover the data written on the hard disk drive. 
     One or more hard drive platters  42  include a magnetic coating that stores magnetic fields. The platters  42  are rotated by a spindle motor that is schematically shown at  44 . Generally the spindle motor  44  rotates the hard drive platter  42  at a fixed speed during the read/write operations. One or more read/write arms  46  move relative to the platters  42  to read and/or write data to/from the hard drive platters  42 . The spindle/VCM driver  36  controls the spindle motor  44 , which rotates the platter  42 . The spindle/VCM driver  36  also generates control signals that position the read/write arm  46 , for example using a voice coil actuator, a stepper motor or any other suitable actuator. 
     A read/write device  48  is located near a distal end of the read/write arm  46 . The read/write device  48  includes a write element such as an inductor that generates a magnetic field. The read/write device  48  also includes a read element (such as a magneto-resistive (MR) sensor) that senses the magnetic fields on the platter  42 . A preamplifier (preamp) circuit  50  amplifies analog read/write signals. When reading data, the preamp circuit  50  amplifies low level signals from the read element and outputs the amplified signal to the read channel circuit  40 . While writing data, a write current that flows through the write element of the read/write device  48  is switched to produce a magnetic field having a positive polarity or negative polarity. The positive or negative polarity is stored by the hard drive platter  42  and is used to represent data. Data storage rates of these systems are proportional to a rate that the write driver circuit can change the direction of the write current through the write head. 
     SUMMARY OF THE INVENTION 
     A write driver system according to the present invention comprises a control circuit that includes first switching devices and that generates gate drive signals. A write driver circuit includes second switching devices that are controlled by the gate drive signals from the control circuit. The second switching devices have higher voltage thresholds than the first switching devices. The second switching devices have slower switching times than the first switching devices. 
     In other features, the write driver circuit generates a boost current followed by a write current when transitioning from one magnetic polarity to an opposite magnetic polarity during write operations. The control circuit includes a logic circuit that generates N control signals. N predriver circuits receive respective ones of the N control signals. 
     In other features, the gate drive signals are output by the N predriver circuits. The gate drive signals exceed the voltage thresholds of the first switching devices of the N predriver circuits and do not exceed the voltage thresholds of the second switching devices of the write driver circuit. At least one of the N predriver circuits includes a first inverter that has an input that receives one of the N control signals and an output. First, second and third latches have inputs that are capacitively coupled to the output of the first inverter. 
     In still other features, the at least one of the N predriver circuits further includes a second inverter that has an input coupled to the output of the first inverter and an output. A third inverter has an input coupled to the output of the second inverter. Fourth, fifth and sixth inverters have inputs that are coupled to outputs of the first, second and third latches and capacitively coupled to the output of the second inverter. 
     In still other features, the at least one of the N predriver circuits further includes first, second, third, fourth, fifth, sixth, seventh and eighth switches, each having a control terminal and first and second terminals. The control terminal of the first switch communicates with the output of the fourth inverter. The control terminal of the fourth switch communicates with the output of the third inverter. The control terminal of the fifth switch communicates with the output of the fifth inverter. The control terminal of the eighth switch communicates with the output of the sixth inverter. A voltage supply provides first and second positive voltage potentials, first and second negative voltage potentials and a reference potential. The first terminal of the first switch communicates with the first positive voltage potential. The first terminal of the second switch communicates with the second terminal of the first switch. The second terminal of the second switch communicates with the first terminal of the third switch. The second terminal of the third switch communicates with the first terminal of the fourth switch and the second terminal of the fourth switch communicates with the reference potential. 
     In still other features, the second terminal of the eighth switch communicates with the first negative voltage potential. The second terminal of the seventh switch communicates with the first terminal of the eighth switch. The first terminal of the seventh switch communicates with the second terminal of the sixth switch. The first terminal of the sixth switch communicates with the second terminal of the fifth switch and the first terminal of the fifth switch communicates with the reference potential. 
     In other features, the first, second and third inverters are biased by the second positive voltage potential and the reference potential. The first latch and the fourth inverter are biased by the first positive voltage potential and the second positive voltage potential. The second latch and the fifth inverter are biased by the second negative voltage potential and the reference potential. The third latch and the sixth inverter are biased by the first negative voltage potential and the second negative voltage potential. The first, second, fifth and sixth switches include PMOS transistors and the third, fourth, seventh and eighth switches include NMOS transistors. 
     In other features, a voltage supply provides first and second positive voltage potential and first and second negative voltage potentials. The write driver circuit selectively connects the first positive and negative voltage potentials across a write head during the boost stage and the second positive and negative voltage potentials across the write head during the write stage. First, second, third, and fourth switches are connected in series between the first positive voltage potential and the first negative voltage potential. Fifth, sixth, seventh, and eighth switches are connected in series between the first positive voltage potential and the first negative voltage potential. Ninth and eleventh switches have first terminals that receive the second positive voltage potential and second terminals that communicate with the first and second switches and the fifth and sixth switches. Tenth and twelfth switches have first terminals that receive the second negative voltage potential and second terminals that communicate with the third and fourth switches and the seventh and eighth switches. 
     Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein: 
         FIG. 1  is a functional block diagram of an exemplary data storage device according to the prior art; 
         FIG. 2A  is an electrical schematic of a simplified write driver circuit according to one embodiment of the present invention; 
         FIGS. 2B and 2C  are graphs showing exemplary write voltage waveforms and write current waveforms, respectively; 
         FIG. 3  is a functional block diagram illustrating a write driver system including a control circuit and a write drive circuit for a data storage system according to the present invention; 
         FIG. 4  is an electrical schematic of the write drive circuit of  FIG. 3  in further detail; 
         FIG. 5  is a more detailed functional block diagram of the control circuit of  FIG. 3 ; 
         FIG. 6  is a table illustrating ON/OFF states of the switching devices in the write drive circuit during boost and write current stages; and 
         FIG. 7  is an electrical schematic and functional block diagram of the predriver circuit of  FIG. 5 . 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The following description of the preferred embodiments is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. 
     Referring now to  FIGS. 2A ,  2 B and  2 C, an exemplary write drive circuit  60  in accordance with the present invention is shown. While the following description describes the write drive circuit  60  in conjunction with a write head  64  of a magnetic data storage device, it should be understood that the write driver circuit  60  may be useful in other data storage applications. 
     The write driver circuit  60  switches the direction of current I L  flowing through the write head  64  of a magnetic storage device. As shown in  FIG. 2C , the head current I L  may initially have a negative write current value −I W  for writing a magnetic field having one polarity onto a magnetic storage medium. The head current I L  may then transition to a positive boost current I B  to quickly reverse current flow in the write head  64 . The head current I L  may then decrease to a lower positive write current value I W  to write a magnetic field having an opposite polarity onto the magnetic storage medium. The head current I L  may then transition to a negative boost current value −I B  to quickly reverse current flow in the write head. Then, the head current I L  transitions to the negative write current value −I W  to write. As can be appreciated, the timing of the write current will vary from that shown in  FIGS. 2B and 2C . 
     The write driver circuit  60  that is shown in  FIG. 2A  has several advantages. The write driver circuit  60  maintains a common mode voltage level across the write head  64  with minimal fluctuation during operation. Further, the write driver circuit  60  operates in a voltage mode (i.e., the current through the write head  64  is controlled by controlling voltage potentials across the write head). The write driver circuit  60  has substantially constant output impedance at very high operating frequencies. The write head  64  sees an impedance that is predominantly resistive during operation. The write driver circuit  60  balances both differential and common mode resistance. The common mode and differential resistance is also independent of the magnitude of the write current. 
     Referring now to  FIG. 3 , a write driver system  68  according to the present invention includes a control circuit  70  and a write drive circuit  72 . The control circuit  70  is preferably implemented using low voltage switching devices that have relatively fast switching times. However, the write drive circuit  72  is preferably implemented using higher voltage switching devices having slower switching times. The higher voltage capacity of the switching devices in the write drive circuit  72  allows higher boost and write currents. The lower capacity/faster switching of the switching devices in the control circuit  70  enables fast switching and increased data density. For example, the low voltage switching devices may include transistors that experience voltage stress above 1.8V and the high voltage switching devices may include transistors that experience voltage stress above 3.6V. However, skilled artisans will appreciate that switching devices having other voltage stress levels may be used. 
     Referring now to  FIG. 4 , the write driver circuit  72  includes a write head  112  that has opposite ends that are connected to sub-circuits  114 A and  114 B, respectively. For purposes of illustration, the sub-circuit  114 A is described further below. Since the sub-circuits  114 A and  114 B are symmetric, the same reference numbers and/or other identification will be used followed by A to identify features of sub-circuit  114 A and B to identify features of sub-circuit  114 B. 
     The sub-circuit  114 A includes a switching device  116 A that is connected in series with a switching device  118 A between a voltage source V cc  and one side of the write head  112 . In particular, the switching device  118 A is coupled to node  120 , which is coupled through the write head  112  (including resistances R s ) to node  122  on the other side of the write head  112 . Switching device  116 A is connected in series with switching device  118 A through a node  124 A. A switching device  126 A is coupled between the node  124 A and a voltage source V H . 
     Similar to the upper left portion of the write driver circuit  72 , sub-circuit  114 A includes a switching device  128 A connected in series with a switching device  130 A between node  122  and a voltage source V ee . In particular, switching device  128 A is coupled to switching device  130 A through a node  132 A. A switching device  134 A is coupled between node  132 A and a voltage source V L . 
     Operation of switching devices  116 A,  116 B,  118 A,  118 B,  126 A and  126 B are controlled by control signals B L , B R , C L , C R , I WL  and I WR , respectively. Similarly, operation of switching devices  128 A,  128 B,  130 A,  130 B,  134 A and  134 B are controlled by control signals C L ′, C R ′, B L ′, B R ′, I WL ′ and I WR ′, respectively. The prime symbols denote that the waveforms of control signals C L ′, C R ′, B L ′, B R ′, I WL ′ and I WR ′ are compliments of the waveforms of control signals C L , C R , B L , B R , I WL  and I WR , respectively. 
     For the embodiment of the write driver circuit  72  shown in  FIG. 4 , voltage source V cc &gt;V H &gt;V L &gt;V ee . For example, V cc  may be 3.6V, V H  may be 1.8V, V L  may be −1.8V, and V ee  may be −3.6V, although other voltage levels may be used. By turning switching devices  116 A,  118 A,  128 A and  130 A on (while the other switching devices are off), a positive boost current I B  flows from voltage source V cc , through switching devices  116 A and  118 A, through the write head  112  from left to right in  FIG. 4  and through switching devices  128 A and  130 A to voltage source V ee . Thereafter, by turning switching devices  116 A and  130 A off and turning switching devices  126 A and  134 A on, a positive write current I W  flows from voltage source V H  through switches  126 A and  118 A, through the write head  112  from left to right in  FIG. 4  and through switches  128 A and  134 A to the voltage source V L . 
     Conversely, by turning on switching devices  116 B,  118 B,  128 B and  130 B (with the other switching devices turned off), a boost current flows from voltage source V cc , through switching devices  116 B and  118 B, through the write head  112  from right to left in  FIG. 4  and through switching devices  128 B and  130 B to the voltage source V ee . Thereafter, by turning off switching devices  116 B and  130 B and turning on switching devices  126 B and  134 B, a write current flows from the voltage source V H , through switching devices  126 B and  118 B, through the write head  112  from right to left in  FIG. 4  and through switching devices  128 B and  134 B to the voltage source V L . 
     Because the voltage potential provided between voltage sources V cc  and V ee  is greater than the voltage potential provided between voltage sources V H  and V L , the boost current I B  is greater than the write current I W , as shown in  FIG. 2C . 
     Referring now to  FIGS. 5 and 6 , the control circuit  70  is shown in further detail and includes a logic circuit  200  and predriver circuits  204 - 1 ,  204 - 2 , . . . ,  204 - 6  (collectively predriver circuits  204 ). The logic circuit  200  receives low voltage write signals and generates corresponding low voltage control signals for the predriver circuits  204 . The predriver circuits  204 , in turn, generate high voltage gate control voltages for the switching devices in the write drive circuit  72 . The predriver circuits  204  are also implemented using low voltage, high speed switching devices as will be described below. For example, the predriver circuit  204 - 1  generates complementary gate drive signals B L  and BC. Other predriver circuits  204 - 2 ,  204 - 3 , . . . , and  204 - 6  generate the other drive signals in  FIG. 4 . A truth table for the logic circuits is shown in  FIG. 6 . The truth table parallels the switching of the circuits that is described above. 
     In the embodiment of the write driver circuit  10  that is shown in  FIG. 4 , switching devices  116 A,  116 B,  118 A,  118 B,  134 A and  134 B are implemented as PMOS transistors. Conversely, switching devices  126 A,  126 B,  128 A,  128 B,  130 A and  130 B are implemented as NMOS transistors. It should be understood, however, that other types of transistors and/or switching devices may be employed without departing from the principles of the present invention. 
     Referring now to  FIG. 7 , one suitable predriver circuit  204  is shown. A low voltage write input is provided to an inverter  220 . An output of the inverter  220  is capacitively coupled to three latch circuits  222 ,  224 , and  226 . Latch  222  is biased by 1.8V and 3.6V, latch  224  is biased by 0 and −1.8V, and latch  226  is biased by −1.8V and −3.6V. In one embodiment, the latches include anti-parallel inverters. The output of latch  222  communicates with the gate input of a transistor  228  via an inverter  230 . Similarly, the output of latch  224  communicates with the gate input of a transistor  232  via an inverter  234 . The output of latch  226  communicates with a gate of a transistor  236  via an inverter  238 . The output of the inverter  220  also communicates with a gate of a transistor  240  via inverters  242  and  244 . The output signals V out1  and V out2  are taken between the transistors  246  and  248  and between the transistors  250  and  252 , respectively. For example, V out1 =B L  and V out2 =B L ′ in predriver circuit  204 - 1 . By employing low voltage devices with level shifting, the logic circuit of  FIG. 7  provides faster switching than a typical logic circuit employing high voltage devices. 
     Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the present invention can be implemented in a variety of forms. Therefore, while this invention has been described in connection with particular examples thereof, the true scope of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, the specification and the following claims.