Abstract:
A high-speed interface between a first network component and a second network component includes a positive voltage input (VINP) and a negative voltage input (VINN) for receiving an input data signal from the first network component; the positive voltage input (VINP) coupled to a negative output circuit (OUTN) and the negative voltage input (VINN) by a positive input bus and a negative input bus, the negative voltage input (VINN) also coupled to a positive output circuit (OUTP). Implementing the high-speed interface calls for applying a bias to the a positive input bus and a negative input bus to periodically multiplex a data signal, thus providing a common receiving path for functional data and wrap data of the data signal.

Description:
TRADEMARKS  
       [0001]     IBM® is a registered trademark of International Business Machines Corporation, Armonk, N.Y., U.S.A. Other names used herein may be registered trademarks, trademarks or product names of International Business Machines Corporation or other companies.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     This invention relates to high-speed interfaces for computer network systems.  
         [0004]     2. Description of the Background  
         [0005]     When designing a high-speed interface between network components, there is typically a need for wrapping data back through transmitter and receiver circuitry. The wrapping back of data provides for verifying functionality as a “built in self test” (BIST). Preferably, a wrap path operates at functional speeds so that as much of the functional path as possible is used with out a performance penalty. One existing (prior art) approach for implementing the wrap path is depicted in  FIG. 1 .  
         [0006]     Referring to  FIG. 1 , the illustration therein depicts prior art circuitry for verifying functionality of a high-speed interface implemented in a receive path  9 . In this embodiment, a wrap path  5  for a receiver  8  is a mirror of a functional data path  6 . The wrap path  5  is multiplexed in to the data path  6  after a second data receive stage. This design, or designs similar thereto, have typically been applied so that the data path  6  was not impaired by circuitry for the wrap path  5 . Unfortunately, such designs have at least one drawback in that the actual circuitry of the data path  6  is not used. A second drawback is realized by having a multiplexer  4  in the data path  6 , which causes added latency and jitter in a data signal.  
         [0007]     What is needed is a high-speed interface between network components that provides for wrapping back of data and for verifying functionality thereof. Preferably, the high-speed interface makes use of an existing data path to provide for accurate communication, without causing latency and jitter in the data signal.  
       SUMMARY OF THE INVENTION  
       [0008]     Disclosed is a high speed interface for communicating a data signal having functional data and wrap data between a first network component and a second network component, the interface including a positive voltage input (VINP) and a negative voltage input (VINN) for receiving an input data signal from the first network component; the positive voltage input (VINP) coupled to a negative output circuit (OUTN) and the negative voltage input (VINN) by a positive input bus and a negative input bus, the negative voltage input (VINN) also coupled to a positive output circuit (OUTP); the negative output circuit (OUTN) and the positive output circuit (OUTP) coupled to a common operating point; wherein a transmission gate in the negative output circuit (OUTN) provides a negative output data signal from the common operating point for the second network component and another transmission gate in the positive output circuit (OUTP) provides a positive output data signal from the common operating point for the second network component.  
         [0009]     Also disclosed is a method for providing a high-speed differential multiplexed data signal, the method for selecting a high speed interface for communicating between a first network component and a second network component a data signal having functional data and wrap data, the interface including a positive voltage input (VINP) and a negative voltage input (VINN) for receiving an input data signal from the first network component; the positive voltage input (VINP) coupled to a negative output circuit (OUTN) and the negative voltage input (VINN) by a positive input bus and a negative input bus, the negative voltage input (VINN) also coupled to a positive output circuit (OUTP); the negative output circuit (OUTN) and the positive output circuit (OUTP) coupled to a common operating point; wherein a transmission gate in the negative output circuit (OUTN) provides a negative output data signal from the common operating point for the second network component and another transmission gate in the positive output circuit (OUTP) provides a positive output data signal from the common operating point for the second network component; wherein a biasing positive field effect transistor (PFET) is coupled to the positive input bus and a biasing negative field effect transistor (NFET) is coupled to the negative input bus; applying a bias to at least one of the biasing PFET and the biasing NFET for periodically multiplexing the data signal.  
         [0010]     Further disclosed is a high speed interface for communicating a data signal having functional data and wrap data between a first network component and a second network component, the interface including a positive voltage input (VINP) coupled to a gate of a positive field effect transistor (PFET) and a gate of an negative field effect transistor (NFET) and a negative voltage input (VINN), coupled to a gate of another positive field effect transistor (PFET) and a gate of another negative field effect transistor (NFET); a negative output circuit (OUTP) comprising a plurality of NFET and a plurality of PFET and a positive output circuit (OUTP) comprising another plurality of NFET and another plurality of PFET; wherein one of a source and a drain of the PFET in the positive voltage input (VINP) is coupled to a coupling between the NFET in the plurality of NFET and one of a source and a drain of the NFET in the positive voltage input (VINP) is coupled to a coupling between the PFET in the plurality of PFET; wherein one of a source and a drain of the another PFET in the negative voltage input (VINN) is coupled to a coupling between the NFET in the another plurality of NFET and one of a source and a drain of the another NFET in the negative voltage input (VINN) is coupled to a coupling between the PFET in the another plurality of PFET, wherein, the remaining one of the source and the drain for the another PFET is coupled to the remaining one of the source and the drain for the PFET in the positive voltage input (VINP) to form a positive input bus and the remaining one of the source and the drain for the another NFET is coupled to the remaining one of the source and the drain for the NFET in the positive voltage input (VINP) to form a negative input bus; wherein a gate for each of the NFET and each of the PFET in the negative output circuit (OUTN) and the positive output circuit (OUTP) are coupled to a common operating point; wherein the negative output circuit (OUTN) comprises a transmission gate coupled to the common operating point and at least one NFET of the plurality and at least one PFET of the plurality and the positive output circuit (OUTP) comprises another transmission gate coupled to the common operating point and at least one NFET of the another plurality and at least one PFET of the another plurality; wherein one of a source and a drain for a positive bias device is coupled to the positive input bus and one of a source and a drain for a negative bias device is coupled to the negative input bus; and, wherein functional data and wrap data from the first network component is submitted to the positive voltage input (VINP) and the negative voltage input (VINN) and passed to the second network component via the negative output circuit (OUTP) and the positive output circuit (OUTP).  
         [0011]     Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.  
       TECHNICAL EFFECTS  
       [0012]     As a result of the summarized invention, technically we have achieved a solution which provides for a high-speed differential receiver having integrated multiplexer input. The receiver provides for receiving wrap data and functional data in a common path thus providing for improved speed, reduced latency and jitter as well as improved stability in an interface between a first network component and a second network component over prior art interfaces implementing a dual data path. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]     The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:  
         [0014]      FIG. 1  illustrates one example of a prior art high-speed interface having a wrap back path;  
         [0015]      FIG. 2  illustrates one example of a wrap back path in accordance with the teachings herein;  
         [0016]      FIG. 3  illustrates aspects of input and output signals for a high-speed interface; and,  
         [0017]      FIG. 4  illustrates one example of a modification to the circuit depicted in  FIG. 3 . 
     
    
       [0018]     The detailed description explains the preferred embodiments of the invention, together with advantages and features, by way of example with reference to the drawings.  
       DETAILED DESCRIPTION OF THE INVENTION  
       [0019]     Turning now to the drawings in greater detail, it will be seen that in  FIG. 2  there is a high-speed interface  10  according to the present invention. The high-speed interface  10  includes a multiplexing function  14  within the first stage of a receiver  18 . In this embodiment, the multiplexing function  14  is included within a first stage of the receiver  18 . Implementing a wrap path  15  in this fashion provides for using a data path  16  as the receive path  19 . This design eliminates the uncertainty of the prior art, which makes use of parallel paths. Further, by removing a traditional multiplexer  4  from the receive path  19  (the multiplexer  4  selecting which path is propogated to an output) a reduction in both latency and jitter is realized.  
         [0020]     In order to clearly distinguish aspects of data, as discussed herein, a data signal includes functional data  11  as well as wrap data  12 . The functional data  11  includes many types of data for communication through the high-speed interface  10 . Wrap data  12  includes the portion of data for wrapping back through the high-speed interface  10 , and typically provides for verifying functionality through a “built in self test” (BIST). One skilled in the art will recognize that in various instances functional data  11  and wrap data  12  may include various relationships such as being interchangeable or a subset of one or the other.  
         [0021]     In typical embodiments, the high-speed interface  10  makes use of field effect transistors (FETs). FETs include three terminals, or leads. The terminals include a drain, a source and a gate. FETs can switch signals of either polarity on the source terminal or the drain terminal if the signal amplitude is significantly less than the gate swing amplitude, as FET devices are typically symmetrical (about the source terminal and the drain terminal). This makes FETs suitable for a variety of switching tasks, including switching analog signals between paths (multiplexing).  
         [0022]      FIG. 3  provides a typical embodiment of a circuit implementing the high-speed interface  10 . In this embodiment, an input stage of the receiver  18  accommodates inputs of wrap data  12 . In  FIG. 3 , the input stage of the receiver  18  has a positive voltage input (VINP)  33  and a negative voltage input (VINN)  34 . In this embodiment, the VINP  33  includes a positive field effect transistor (PFET) TP 6  and a negative field effect transistor (NFET) TN 6 . A gate for each of TP 6  and TN 6  are coupled to receive a positive input signal. The VINN  34  similarly includes a positive field effect transistor (PFET) TP 7  and a negative field effect transistor (NFET) TN 7 . Also similarly, a gate for each of TP 7  and TN 7  are coupled to receive a negative input signal.  
         [0023]     In this exemplary circuit, a common operating point  30  is formed by a common coupling of a negative output circuit  31  and a positive output circuit  32 . In this illustration, the negative output circuit  31  includes positive field effect transistor (PFET) devices TP 1 , TP 2 , with negative field effect transistor (NFET) devices TN 1 , TN 2 , while the positive output side includes PFET devices TP 3 , TP 4  and NFET devices TN 3 , TN 4 . The common coupling is formed by the coupling of a gate for each of the PFET and the NFET in the negative output circuit  31  with each of the PFET and the NFET in the positive output circuit  32 .  
         [0024]     In this embodiment of the negative output circuit  31 , a coupling of one of a drain and a source for TN 1  to one of the drain and the source for TN 2  is made. The remaining lead of TN 2  (either one of the drain or the source) is coupled to an output node OUTN. Likewise, a coupling of one of a drain and a source for TP 1  to one of the drain and the source for TP 2  is made. The remaining lead of TP 2  (either one of the drain or the source) is coupled to an output node OUTN. The output node OUTN is coupled to the common operating point  30  by a transmission gate TG 1 .  
         [0025]     In this embodiment of the positive output circuit  32 , a coupling of one of a drain and a source for TN 3  to one of the drain and the source for TN 4  is made. The remaining lead of TN 4  (either one of the drain or the source) is coupled to an output node OUTP. Likewise, a coupling of one of a drain and a source for TP 3  to one of the drain and the source for TP 4  is made. The remaining lead of TP 4  (either one of the drain or the source) is coupled to an output node OUTP. The output node OUTP is coupled to the common operating point  30  by a transmission gate TG 2 .  
         [0026]     The output signals include a negative output signal through the output node OUTN and a positive output signal through the output node OUTP. The transmission gates TG 1  and TG 2  are coupled to the common operating point  30  and provide a feedback path  31  for the wrap data  12 .  
         [0027]     The positive voltage input  33  is coupled to the negative output circuit  31 . This coupling is realized, in part, by coupling one of a drain and a source for the PFET TP 6  to the coupling between TN 1  and TN 2 . The coupling is completed by coupling one of a drain and a source for the NFET TP 6  to the coupling between TP 1  and TP 2 .  
         [0028]     The negative voltage input  34  is coupled to the positive output circuit  32 . This coupling is realized, in part, by coupling one of a drain and a source for the PFET TP 7  to the coupling between TN 3  and TN 4 . The coupling is completed by coupling one of a drain and a source for the NFET TN 7  to the coupling between TP 3  and TP 4 .  
         [0029]     The positive voltage input  33  is also coupled to the negative voltage input  34  by a positive input bus  35  and a negative input bus  36 . To form the positive input bus  35 , a remaining lead (one of the source and the drain) for TP 6  is coupled to the remaining lead (one of the source and the drain) for TP 7 . Likewise, to form the negative input bus  36  the remaining lead (one of the source and the drain) for TN 6  is coupled to the remaining lead (one of the source and the drain) for TN 7 .  
         [0030]     Coupled to the positive input bus  35  and the negative input bus  36  are a PFET TP 5  and an NFET TN 5 , respectively. The bias devices TP 5  and TN 5  provide a current path to swing the output nodes OUTP and OUTN. The bias for PFET TP 5  is turned on by input EN_BAR and the bias for NFET TN 5  is turned on by input EN.  
         [0031]     It should be noted that the terms “positive voltage input,” “negative voltage input,” “negative output circuit,” “positive output circuit” “positive input bus,” and “negative input bus” are presented and defined merely for convenience of referencing and to lend an understanding to the teachings. These terms are not intended to limit aspects of the design or the teachings in any way and are only provided to introduce and better describe aspects of the high-speed interface  10 .  
         [0032]     The exemplary embodiment depicted in  FIG. 3  can be modified to provide a high-speed differential multiplexer. One exemplary modification calls for using the bias devices PFET TP 5  and NFET TN 5  to select a primary receive path (data path  16 ) and periodically disabling the bias devices to provide a wrap data path  15  as a second path. This modification provides one way to implement the logical built-in-self-test BIST function.  
         [0033]      FIG. 4  depicts an embodiment that is a modification to the circuit depicted in  FIG. 3 . In this embodiment, a second input path is provided to pass the wrap data  12 . In  FIG. 4 , the circuit for the high-speed interface  10  is represented by PFET TP 1  through PFET TP 7  and NFET TN 1  through NFET TN 7 .  
         [0034]     This embodiment includes WRAP_EN and WRAP_ENBAR inputs for selection of a primary data path (receive) from the positive voltage input signal (VINP) and the negative voltage input signal (VINN). Alternatively, the WRAP_EN and WRAP_ENBAR inputs are provided for logic wrap inputs WRAP_P and WRAP_N to propagate to OUTP and OUTN. In this embodiment, the WRAP_EN and WRAP_ENBAR inputs on devices PFETs TPW 2 , TPW 4  and NFETs TNW 2 , TNW 4  are placed between the wrap input devices PFETs TPW 1 , TPW 3  and NFETs TNW 1 , TNW 3  and the rest of the circuitry. This placement provides isolation of the wrap input and limits degradation or corruption of performance in the primary receive data path.  
         [0035]     Typically, the high-speed interface  10  is used as a high-speed differential receiver with an integrated multiplexer input.  
         [0036]     Although the exemplary embodiments depicted herein are illustrated as hardware implementations, it should be recognized that the capabilities of the present invention may be implemented in software, firmware, hardware or some combination thereof. As one example, one or more aspects of the present invention can be included in an article of manufacture (e.g., one or more computer program products) having, for instance, computer usable media. The media has embodied therein, for instance, computer readable program code means for providing and facilitating the capabilities of the present invention. The article of manufacture can be included as a part of a computer system or sold separately.  
         [0037]     Additionally, at least one program storage device readable by a machine, tangibly embodying at least one program of instructions executable by the machine to perform the capabilities of the present invention can be provided.  
         [0038]     The flow diagrams depicted herein are just examples. There may be many variations to these diagrams or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order, or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention.  
         [0039]     While the preferred embodiment to the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.