Abstract:
A flat panel display includes pixel electrodes, multiplexers and a gate driver. The gate driver has an amorphous silicon gate structure and includes a displacement temporary storage unit having a plurality of shift registers each with a power supply source and a clock terminal. One of a first voltage and a second voltage is selected and transmitted to the power supply source, and one of the first voltage and a clock signal is selected and transmitted to the clock terminal according to an off-controlling signal for causing the pixel electrodes connected to the shift registers to discharge.

Description:
[0001]    This application claims the benefit of Taiwan application Serial No. 96111106, filed Mar. 29, 2007, the entirety of which is incorporated herein by reference. 
       BACKGROUND 
       [0002]    The disclosure relates in general to a flat panel display, and more particularly, to a flat panel display, which uses a gate driving device manufactured by an amorphous silicon manufacturing process and can eliminate a residual image after the display is turned off. 
         [0003]    In the typical LCD architecture, a residual image is frequently seen on the display, e.g., a LCD panel, after the LCD panel is turned off and the residual image cannot disappear until several seconds have elapsed. This phenomenon interferes with the visual feeling of the user, and the display quality of the LCD panel is deteriorated with time. Taking a thin-film transistor (TFT) LCD as an example, one of the reasons causing the residual image to occur after the LCD is turned off is that the discharging speed of the pixel electrodes of the TFT-LCD is too slow. Thus, the charges cannot be quickly released and remain in the liquid crystal capacitors after the LCD is turned off, and cannot be completely discharged until a period of time has elapsed. 
         [0004]      FIG. 1  (Prior Art) is a schematic illustration showing a conventional LCD  10 . In the LCD  10 , a timing controller (not depicted in  FIG. 1 ) outputs data, wherein a source driver of a display array circuit is utilized to receive and write the data, and gate drivers  12   y  (y=1 to P, and P is a positive integer) are utilized to select a row for writing the data so that an output frame is displayed on a panel  16 . Then, when the LCD is turned off, a voltage detecting circuit  142  of a printed circuit board  14  detects that a received operation voltage VCC is lowered to a predetermined level (e.g., 0.7VCC), an off-controlling signal XAO is transformed from a high-level voltage H to a low-level voltage L and then outputted to the gate drivers  12   y  (y=1 to P). Thus, an output signal of each of the gate drivers  12   y  (y=1 to P) is transformed into the high-level voltage H to turn on TFTs of each pixel in the panel  16 .  FIG. 2  (Prior Art) shows signal waveforms in the LCD  10  of  FIG. 1 . Consequently, before the LCD is powered off, residual charges in a liquid crystal capacitor of each pixel can be rapidly discharged by the turned-on TFT and a data line electrically connected thereto. Thus, the time of completely discharging the residual charges can be shortened, thereby eliminating the phenomenon of the residual image when the LCD is turned off. 
         [0005]    However, the property of the TFT-LCD is that a light source mainly comes from a backside, and a glass substrate has to be used. Thus, when the application field is an active mode LCD, transistors serving as switches have to be formed on the glass substrate using the semiconductor manufacturing process. However, the melting point of the glass is about 660°C., and the glass substrate cannot be used in the frequently used IC manufacturing process, such as the monocrystalline silicon manufacturing process (the growing temperature is higher than 1000° C.). In order to overcome this drawback, an amorphous silicon (Amorphous Si) manufacturing process, in which the amorphous silicon can be easily deposited on a large area and can be well attached to the glass substrate, is frequently used.  FIG. 3  is a block diagram showing an amorphous silicon gate driver. As shown in  FIG. 3 , an amorphous silicon gate driver  300  has many shift registers  31   n  (n=1 to (N+1)). 
         [0006]      FIG. 4  is a circuit diagram showing a shift register  31   n  of  FIG. 3 , wherein n is a positive integer ranging from 1 to (N+1). As shown in  FIG. 3  and  FIG. 4  and compared with the gate drivers  12   y  (y=1 to P) of  FIG. 1 , the amorphous silicon gate driver  300  does not have the function of an off-controlling signal XAO (i.e., does not have the function of eliminating the residual image after the LCD is turned off). This is because the off-controlling signal XAO is a low-level voltage (about 0 to 3.3 volts) in the conventional LCD  10  and can be received by the shift register (not depicted in the drawing) in the gate drivers  12   y  (y=1 to P). In the amorphous silicon manufacturing process, however, the off-controlling signal XAO is a high-level voltage, which may reach as high as 20 volts, and cannot be received by the shift registers  31   x  (x=1 to (N+1)). So, the problem of the residual image after the LCD is turned off appears again if a gate driving device of the LCD is manufactured by the amorphous silicon manufacturing process. 
         [0007]    There is a need for a flat panel display, which can use a gate driving device manufactured by an amorphous silicon manufacturing process and can make all pixel electrodes discharge according to an off-controlling signal to eliminate a residual image when the flat panel display is turned off. 
       SUMMARY 
       [0008]    According to a first aspect of the present invention, a flat panel display including a plurality of pixel electrodes, a first multiplexer, a second multiplexer, a third multiplexer and a gate driver is provided. The first multiplexer is for receiving a high working voltage and a low working voltage and is controlled by an off-controlling signal to output an input low power voltage. The second multiplexer is for receiving the high working voltage and a zeroth clock signal and is controlled by the off-controlling signal to output a zeroth input clock signal. The third multiplexer is for receiving the high working voltage and a first clock signal and is controlled by the off-controlling signal to output a first input clock signal. The gate driver has (N+1) shift registers, wherein N is a positive integer. The gate driver is electrically connected to the pixel electrodes, and the n th  shift register includes a SR flip-flop, a first transistor and a second transistor. The SR flip-flop, which has a set terminal, a reset terminal, an output terminal and an inverting output terminal, and is electrically connected to the high working voltage and the low working voltage, wherein the set terminal is coupled to an (n−1) th  output signal of the (n−1) th  shift register, the reset terminal is coupled to an (n+1) th  output signal of the (n+1) th  shift register. The first transistor is formed on a glass substrate and has a control terminal coupled to the output terminal and a first terminal for receiving an M th  input clock signal, wherein M=1 if n is even and M=0 if n is odd. The second transistor is formed on the glass substrate. The second transistor has a control terminal coupled to the inverting output terminal, a first terminal, which is coupled to a second terminal of the first transistor and outputs an n th  output signal, and a second terminal coupled to the input low power voltage, wherein n is a positive integer ranging from 1 to (N+1). When the flat panel display is turned off, the off-controlling signal is transformed from a high-level voltage to a low-level voltage so that the input low power voltage outputted from the first multiplexer is transformed to the high working voltage, the zeroth input clock signal outputted from the second multiplexer is transformed to the high working voltage, the first input clock signal outputted from the third multiplexer is transformed to the high working voltage to make the first transistor or the second transistor turn on, and the n th  output signal outputs the high working voltage to make the pixel electrodes discharge. 
         [0009]    According to a second aspect of the present invention, a flat panel display having an amorphous silicon gate structure is provided. The flat panel display includes a plurality of pixel electrodes, a first multiplexer, a second multiplexer and a gate driver. The first multiplexer is for receiving a high working voltage and a low working voltage and is controlled by an off-controlling signal to output a power voltage. The second multiplexer is for receiving the low working voltage and an initial voltage and is controlled by the off-controlling signal to output a zeroth trigger signal. The gate driver has the amorphous silicon gate structure and (N+1) shift registers, wherein N is a positive integer. The gate driver is electrically connected to the pixel electrodes. The n th  shift register includes a SR flip-flop, a first transistor, a second transistor, a third transistor, a first capacitor, a second capacitor, a fourth transistor and a fifth transistor. The SR flip-flop has a set terminal, a reset terminal, an output terminal and an inverting output terminal and is electrically connected to the high working voltage and the low working voltage. The set terminal is coupled to an (n−1) th  trigger signal of the (n−1) th  shift register, and the reset terminal is coupled to an (n+1) th  output signal of the (n+1) th  shift register. The first transistor is formed on a glass substrate and has a control terminal coupled to the output terminal and a first terminal for receiving an M th  clock signal, wherein M=1 if n is even and M=0 if n is odd. The second transistor is formed on the glass substrate. The second transistor has a control terminal coupled to the inverting output terminal, a first terminal, which is coupled to a second terminal of the first transistor and outputs an n th  output signal, and a second terminal coupled to the power voltage. The third transistor is formed on the glass substrate. The third transistor has a first terminal coupled to the control terminal of the second transistor, and a second terminal coupled to a control terminal of the third transistor and coupled to the power voltage. The first capacitor is coupled to the first terminal of the second transistor and the control terminal of the second transistor. The second capacitor is coupled to the second terminal of the second transistor and the control terminal of the second transistor. The fourth transistor is formed on the glass substrate. The fourth transistor has a control terminal coupled to the output terminal, and a first terminal coupled to the M th  clock signal. The fifth transistor is formed on the glass substrate. The fifth transistor has a control terminal coupled to the inverting output terminal, a first terminal, which is coupled to a second terminal of the fourth transistor and outputs an n th  trigger signal, and a second terminal coupled to the low working voltage, wherein n is a positive integer ranging from 1 to (N+1). When the flat panel display is turned off, the off-controlling signal is transformed from a high-level voltage to a low-level voltage so that the power voltage outputted from the first multiplexer is transformed to the high working voltage to (i) make the second transistor turn on and output the n th  output signal at the high working voltage to make the pixel electrodes discharge and (ii) make the fifth transistor turn on so that the n th  trigger signal outputted from the fifth transistor is held on the low-level voltage. 
         [0010]    According to a third aspect of the present invention, a flat panel display including many pixel electrodes, a first multiplexer, a second multiplexer and a gate driver is further provided. The first multiplexer is for receiving a high working voltage and a low working voltage and is controlled by an off-controlling signal to output a power voltage. The second multiplexer is for receiving the high working voltage and the low working voltage and is controlled by the off-controlling signal to output a switch voltage. The gate driver has (N+1) shift registers, wherein N is a positive integer. The gate driver is electrically connected to the pixel electrodes. The n th  shift register includes a SR flip-flop, a first transistor, a second transistor, a third transistor, a first capacitor, a second capacitor, a fourth transistor and a fifth transistor. The SR flip-flop has a set terminal, a reset terminal, an output terminal and an inverting output terminal and is electrically connected to the high working voltage and the low working voltage. The reset terminal is coupled to an (n+1) th  output signal of the (n+1) th  shift register. The first transistor formed on a glass substrate has a control terminal coupled to the output terminal, and a first terminal for receiving an M th  clock signal, wherein M=1 if n is even and M=0 if n is odd. The second transistor formed on the glass substrate has a control terminal coupled to the inverting output terminal, a first terminal, which is coupled to a second terminal of the first transistor and outputs an n th  output signal, and a second terminal coupled to the power voltage. The third transistor formed on the glass substrate has a first terminal coupled to the control terminal of the second transistor, and a second terminal coupled to a control terminal of the third transistor and coupled to the power voltage. The first capacitor is coupled to the first terminal of the second transistor and the control terminal of the second transistor. The second capacitor is coupled to the second terminal of the second transistor and the control terminal of the second transistor. The fourth transistor formed on the has a control terminal coupled to the switch voltage, a first terminal coupled to the set terminal, and a second terminal coupled to an (n−1) th  output signal of the (n−1) th  shift register. The fifth transistor formed on the glass substrate has a control terminal coupled to the power voltage, a first terminal coupled to the first terminal of the fourth transistor, and a second terminal electrically connected to the low working voltage, wherein n is a positive integer ranging from 1 to (N+1). When the flat panel display is turned off, the off-controlling signal is transformed from a high-level voltage to a low-level voltage so that the power voltage outputted from the first multiplexer is transformed to the high working voltage and the switch voltage outputted from the second multiplexer is transformed to the low working voltage to make the second transistor turn on, and the n th  output signal outputs the high working voltage to make the pixel electrodes discharge. 
         [0011]    According to a fourth aspect of the present invention, a gate driving device for driving a plurality of pixel electrodes is provided. The gate driving device and the pixel electrodes are formed on a glass substrate. The gate driving device includes a displacement temporary storage unit, which comprises a plurality of shift registers each comprising a power supply source and a clock terminal. One of a first voltage and a second voltage is selected and transmitted to the power supply source, and one of the first voltage and a clock signal is selected and transmitted to the clock terminal according to an off-controlling signal for causing the pixel electrodes connected to said shift registers to discharge. 
         [0012]    Additional aspects and advantages of embodiments of the present invention are set forth in part in the description which follows, and in part are apparent from the description, or may be learned by practice of the disclosed embodiments. The aspects and advantages of the disclosed embodiments may also be realized and attained by the means of the instrumentalities and combinations particularly pointed out in the appended claims. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]    The disclosed embodiments are illustrated by way of example, and not by limitation, in the figures of the accompanying drawings, wherein elements having the same reference numeral designations represent like elements throughout. 
           [0014]      FIG. 1  is a schematic illustration showing a conventional LCD. 
           [0015]      FIG. 2  shows signal waveforms in the LCD  10  of  FIG. 1 . 
           [0016]      FIG. 3  is a block diagram showing an amorphous silicon gate driver. 
           [0017]      FIG. 4  is a circuit diagram showing a shift register  31   n  of  FIG. 3 . 
           [0018]      FIG. 5  is a schematic illustration showing a flat panel display according to a first embodiment of the invention. 
           [0019]      FIG. 6  is a block diagram showing a gate driver  52   y  in  FIG. 5 . 
           [0020]      FIG. 7  is a circuit diagram showing a shift register  52   yn  in  FIG. 6 . 
           [0021]      FIG. 8  is a timing chart showing timings of signals in the shift register  52   yn  of  FIG. 7 . 
           [0022]      FIG. 9  is a schematic illustration showing a flat panel display according to a second embodiment of the invention. 
           [0023]      FIG. 10  is a block diagram showing a gate driver  92   y  in  FIG. 9 . 
           [0024]      FIG. 11  is a circuit diagram showing a shift register  92   yn  in  FIG. 10 . 
           [0025]      FIG. 12  is a timing chart showing timings of signals in the shift register  92   yn  of  FIG. 11 . 
           [0026]      FIG. 13  is a schematic illustration showing a flat panel display according to a third embodiment of the invention. 
           [0027]      FIG. 14  is a block diagram showing a gate driver  132   y  in  FIG. 13 . 
           [0028]      FIG. 15  is a circuit diagram showing a shift register  132   yn  in  FIG. 14 . 
           [0029]      FIG. 16  is a timing chart showing timings of signals in the shift register  132   yn  of  FIG. 15 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0030]      FIG. 5  is a schematic illustration showing a flat panel display  50  according to a first embodiment of the invention. Referring to  FIG. 5 , the flat panel display  50  includes a plurality of pixel electrodes (not depicted) disposed on a panel  56 , a first multiplexer  511 , a second multiplexer  512 , a third multiplexer  513 , and gate drivers  52   y  (y=1 to P). The flat panel display  50  further includes a printed circuit board  54 , which has a voltage detecting circuit  542  for detecting a variation of an operation voltage VCC, and thus outputting an off-controlling signal XAO. For example, when the flat panel display  50  is turned off, the voltage detecting circuit  542  outputs the off-controlling signal XAO as a low-level voltage L when the operation voltage VCC is lowered, e.g., by 30%. 
         [0031]    In the flat panel display  50 , the first multiplexer  511  is for receiving a high working voltage VDD and a low working voltage VSS, and is controlled by the off-controlling signal XAO to output an input low power voltage VSSI. The second multiplexer  512  is for receiving the high working voltage VDD and a zeroth clock signal CK 0  and is controlled by the off-controlling signal XAO to output a zeroth input clock signal CK 0 I. The third multiplexer  513  is for receiving the high working voltage VDD and a first clock signal CK 1  and is controlled by the off-controlling signal XAO to output a first input clock signal CK 1 I.  FIG. 6  is a block diagram showing a gate driver  52   y  in  FIG. 5 . As shown in  FIG. 6 , each of the gate drivers  52   y  (y=1 to P) is an amorphous silicon gate driver and has transistors formed on a glass substrate to save the cost. The gate drivers  52   y  (y=1 to P) have (N+1) shift registers  52   yx  (x=1 to (N+1)), wherein N is a positive integer. The gate drivers  52   y  (y=1 to P) are respectively electrically connected to the pixel electrodes. In  FIG. 6 , STV is a control signal received from a timing controller (not shown) to trigger a start pulse to activate the first stage of the shift registers. 
         [0032]      FIG. 7  is a circuit diagram showing a shift register  52   yn  in  FIG. 6 . Referring to  FIG. 7 , the shift register  52   yn  includes a SR flip-flop  72 , a first transistor M 1  and a second transistor M 2 , wherein n is a positive integer ranging from 1 to (N+1). The SR flip-flop  72  has a set terminal ST, a reset terminal RT, an output terminal Q and an inverting output terminal QB, and is electrically connected to the high working voltage VDD and the low working voltage VSSI. The set terminal ST is coupled to an (n−1) th  output signal OUTn−1 of the (n−1) th  shift register, and the reset terminal RT is coupled to an (n+1) th  output signal OUTn+1 of the (n+1) th  shift register. 
         [0033]    The first transistor M 1  formed on the glass substrate has a control terminal coupled to the output terminal Q, and a first terminal for receiving an M th  input clock signal, wherein M=1 if n is even and M=0 if n is odd. That is, when the shift register  52   yn  is sorted as an odd-numbered shift register, it receives the zeroth input clock signal CK 0 I; and when the shift register  52   yn  is sorted as an even-numbered shift register, it receives the first input clock signal CK 1 I. The second transistor M 2  formed on the glass substrate has a control terminal coupled to the inverting output terminal QB, a first terminal, which is coupled to a second terminal of the first transistor M 1  and outputs an n th  output signal OUTn, and a second terminal coupled to the input low power voltage VSSI. 
         [0034]      FIG. 8  is a timing chart showing timings of signals in the shift register  52   yn  of  FIG. 7 . As shown in  FIG. 8 , when the flat panel display  50  is turned off (i.e., the operation voltage VCC is lowered, e.g., by 30%), the off-controlling signal XAO is transformed from a high-level voltage H to the low-level voltage L so that the input low power voltage VSSI outputted from the first multiplexer  511  is transformed to the high working voltage VDD, the zeroth input clock signal CK 0 I outputted from the second multiplexer  512  is transformed to the high working voltage VDD, and the first input clock signal CK 1 I outputted from the third multiplexer  513  is transformed to the high working voltage VDD to make one of the first transistor M 1  and the second transistor M 2  turn on, and the n th  output signal OUTn outputs the high working voltage VDD to make the pixel electrodes discharge. Thus, the residual image after the LCD is turned off may be eliminated. 
         [0035]      FIG. 9  is a schematic illustration showing a flat panel display  90  according to a second embodiment of the invention. Referring to  FIG. 9 , the flat panel display  90  includes a plurality of pixel electrodes (not depicted) disposed on a panel  96 , a first multiplexer  911 , a second multiplexer  912  and gate drivers  92   y  (y=1 to P). The flat panel display  90  further includes a printed circuit board  94 , which has a voltage detecting circuit  942  for detecting the variation of the operation voltage VCC and thus outputting the off-controlling signal XAO. For example, when the flat panel display  90  is turned off, the voltage detecting circuit  942  outputs the off-controlling signal XAO as the low-level voltage L when the operation voltage VCC is lowered, e.g., by 30%. 
         [0036]    In the flat panel display  90 , the first multiplexer  911  is for receiving the high working voltage VDD and the low working voltage VSS, and is controlled by the off-controlling signal XAO to output a power voltage PWR. The second multiplexer  912  is for receiving the low working voltage VSS and an initial voltage STV, and is controlled by the off-controlling signal XAO to output a zeroth trigger signal TR 0 .  FIG. 10  is a block diagram showing a gate driver  92   y  in  FIG. 9 . As shown in  FIG. 10 , each of the gate drivers  92   y  (y=1 to P) is the amorphous silicon gate driver, and has a transistor formed on the glass substrate to save the cost. The gate drivers  92   y  (y=1 to P) have (N+1) shift registers  92   yx  (x=1 to N), wherein N is a positive integer, and the gate drivers  92   y  (y=1 to P) are respectively electrically connected to the pixel electrodes. 
         [0037]      FIG. 11  is a circuit diagram showing a shift register  92   yn  in  FIG. 10 . Referring to  FIG. 11 , the shift register  92   yn  includes a SR flip-flop  1102 , a first transistor M 1 , a second transistor M 2 , a third transistor M 3 , a fourth transistor M 4  and a fifth transistor M 5 , wherein n is a positive integer ranging from 1 to (N+1). The SR flip-flop  1102  has a set terminal ST, a reset terminal RT, an output terminal Q and an inverting output terminal QB, and is electrically connected to the high working voltage VDD and the low working voltage VSS. The set terminal ST is coupled to an (n−1) th  trigger signal TRn−1 of the (n−1) th  shift register, and the reset terminal RT is coupled to an (n+1) th  output signal OUTn+1 of the (n+1) th  shift register. 
         [0038]    The first transistor M 1  formed on the glass substrate has a control terminal coupled to the output terminal Q, and a first terminal for receiving an M th  clock signal, wherein M=1 if n is even and M=0 if n is odd. That is, when the shift register  52   yn  is sorted as an odd-numbered shift register, it receives the zeroth clock signal CK 0 ; and when the shift register  52   yn  is sorted as an even-numbered shift register, it receives the first clock signal CK 1 . The second transistor M 2  formed on the glass substrate has a control terminal coupled to the inverting output terminal QB, a first terminal, which is coupled to a second terminal of the first transistor M 1  and outputs an n th  output signal OUTn, and a second terminal coupled to the power voltage PWR. The third transistor M 3  formed on the glass substrate has a first terminal coupled to the control terminal of the second transistor M 2 , and a second terminal coupled to a control terminal of the third transistor M 3  and coupled to the power voltage PWR. The third transistor M 3  substantially serves as a diode. 
         [0039]    A first capacitor C 1  is coupled to the first terminal of the second transistor M 2  and the control terminal of the second transistor M 2 . A second capacitor C 2  is coupled to the second terminal of the second transistor M 2  and the control terminal of the second transistor M 2 . The first capacitor C 1  and the second capacitor C 2  respectively hold constant level voltages with opposite phases. The fourth transistor M 4  formed on the glass substrate has a control terminal coupled to the output terminal Q, and a first terminal coupled to the M th  clock signal. The fifth transistor M 5  formed on the glass substrate has a control terminal coupled to the inverting output terminal QB, a first terminal, which is coupled to a second terminal of the fourth transistor M 4  and outputs an n th  trigger signal TRn, and a second terminal coupled to the low working voltage VSS. The fourth transistor M 4  and the fifth transistor M 5  substantially serve as a trigger circuit for triggering a next stage of shift register  92   yn+ 1. 
         [0040]      FIG. 12  is a timing chart showing timings of signals in the shift register  92   yn  of  FIG. 11 . As shown in  FIG. 12 , when the flat panel display  90  is turned off (i.e., the operation voltage VCC is lowered, e.g., by 30%), the off-controlling signal XAO is transformed from the high-level voltage H to the low-level voltage L so that the power voltage PWR outputted from the first multiplexer  911  is transformed to the high working voltage VDD and the zeroth trigger signal TR 0  (TR 0  is shown in  FIG. 9 ) outputted from the second multiplexer  912  is transformed to the low working voltage VSS to make the second transistor M 2  of the shift register  92   yn  turn on, and the n th  output signal OUTn outputs the high working voltage VDD to make the pixel electrodes discharge. Thus, the residual image after the LCD is turned off may be eliminated. 
         [0041]    In addition, when the flat panel display  90  is turned off, the power voltage PWR outputted from the first multiplexer  911  is transformed to the high working voltage VDD to make the fifth transistor M 5  turn on so that the n th  trigger signal TRn outputted from the fifth transistor is held on the low-level voltage L as the input for the next stage of shift register  92   yn+ 1. Thus, the inverting output terminal QB of the shift register  92   yn+ 1 holds the output of the high working voltage VDD. 
         [0042]      FIG. 13  is a schematic illustration showing a flat panel display  130  according to a third embodiment of the invention. Referring to  FIG. 13 , the flat panel display  130  includes a plurality of pixel electrodes (not depicted) disposed on a panel  136 , a first multiplexer  1311 , a second multiplexer  1312  and gate drivers  132   y  (y=1 to P). The flat panel display  130  further includes a printed circuit board  134 , which has a voltage detecting circuit  1342  for detecting the variation of the operation voltage VCC and thus outputting the off-controlling signal XAO. For example, when the flat panel display  130  is turned off, the voltage detecting circuit  1342  outputs the off-controlling signal XAO as the low-level voltage L when the operation voltage VCC is lowered, e.g., by 30%. 
         [0043]    In the flat panel display  130 , the first multiplexer  1311  is for receiving the high working voltage VDD and the low working voltage VSS and is controlled by the off-controlling signal XAO to output a power voltage PWR. The second multiplexer  1312  is for receiving the low working voltage VSS and the high working voltage VDD and is controlled by the off-controlling signal XAO to output a switch voltage SW.  FIG. 14  is a block diagram showing a gate driver  132   y  in  FIG. 13 . As shown in  FIG. 14 , each of the gate drivers  132   y  (y=1 to P) is the amorphous silicon gate driver and has transistors formed on the glass substrate to save the cost. The gate drivers  132   y  (y=1 to P) have (N+1) shift registers  132   yx  (x=1 to (N+1)), wherein N is a positive integer, and the gate drivers  132   y  (y=1 to P) are respectively electrically connected to the pixel electrodes. 
         [0044]      FIG. 15  is a circuit diagram showing a shift register  132   yn  in  FIG. 14 . Referring to  FIG. 15 , the shift register  132   yn  includes a SR flip-flop  1502 , a first transistor M 1 , a second transistor M 2 , a third transistor M 3 , a first capacitor C 1 , a second capacitor C 2 , a fourth transistor M 4  and a fifth transistor M 5 , wherein n is a positive integer ranging from 1 to (N+1). The SR flip-flop  1502  has a set terminal ST, a reset terminal RT, an output terminal Q and an inverting output terminal QB, and is electrically connected to the high working voltage VDD and the low working voltage VSS. The reset terminal RT is coupled to the (n+1) th  output signal OUTn+1 of the (n+1) th  shift register. 
         [0045]    The first transistor M 1  formed on the glass substrate has a control terminal coupled to the output terminal Q, and a first terminal for receiving an M th  clock signal, wherein M=1 if n is even and M=0 if n is odd. That is, when the shift register  132   yn  is sorted as an odd-numbered shift register, it receives the zeroth clock signal CK 0 ; and when the shift register  132   yn  is sorted as an even-numbered shift register, it receives the first clock signal CK 1 . The second transistor M 2  formed on the glass substrate has a control terminal coupled to the inverting output terminal QB, a first terminal, which is coupled to a second terminal of the first transistor M 1  and outputs an n th  output signal OUTn, and a second terminal coupled to the power voltage PWR. 
         [0046]    The third transistor M 3  formed on the glass substrate has a first terminal coupled to the control terminal of the second transistor M 2 , and a second terminal coupled to a control terminal of the third transistor M 3  and coupled to the power voltage PWR. The third transistor M 3  substantially serves as a diode. The first capacitor C 1  is coupled to the first terminal of the second transistor M 2  and the control terminal of the second transistor M 2 . The second capacitor C 2  is coupled to the second terminal of the second transistor M 2  and the control terminal of the second transistor M 2 . The first capacitor C 1  and the second capacitor C 2  respectively hold constant level voltages with opposite phases. 
         [0047]    The fourth transistor M 4  formed on the glass substrate has a control terminal coupled to the switch voltage SW, a first terminal coupled to the set terminal ST, and a second terminal coupled to the (n−1) th  output signal OUTn−1 of the (n−1) th  shift register. The fifth transistor M 5  formed on the glass substrate has a control terminal coupled to the power voltage PWR, a first terminal coupled to the first terminal of the fourth transistor M 4 , and a second terminal electrically connected to the low working voltage VSS. 
         [0048]      FIG. 16  is a timing chart showing timings of signals in the shift register  132   yn  of  FIG. 15 . As shown in  FIG. 16 , when the flat panel display  130  is turned off (i.e., the operation voltage VCC is lowered, e.g., by 30%), the off-controlling signal XAO is transformed from the high-level voltage H to the low-level voltage L so that the power voltage PWR outputted from the first multiplexer  1311  is transformed to the high working voltage VDD to make the second transistor M 2  turn on, and the n th  output signal OUTn outputs the high working voltage VDD to make the pixel electrodes discharge. Thus, the residual image after the LCD is turned off can be eliminated. In addition, the switch voltage SW outputted from the second multiplexer  1312  is transformed to the low working voltage VSS, the fourth transistor M 4  is turned off and the power voltage PWR makes the fifth transistor M 5  turn on. Thus, the set terminal ST is electrically connected to the low working voltage VSS, and a voltage level of the inverting output terminal QB is held on the high working voltage VDD. 
         [0049]    The flat panel display according to each embodiment of the invention can use a gate driving device manufactured by the amorphous silicon manufacturing process, and can make all the pixel electrodes discharge according to the off-controlling signal to eliminate the residual image generated when the flat panel display, e.g., a TFT LCD, is turned off. 
         [0050]    While the invention has been described by way of example and in terms of embodiments, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.