Abstract:
The present invention provides a Differential Signaling line driver including a pre-emphasis circuit, which boosts the output drive current without any delay whenever there is a transition in the input signal to the driver, using the input signal itself to provide the pre-emphasis through a current steering circuit that switches the direction of drive currents to provide a differential output signal. A delayed signal is then used to disable the pre-emphasis after a short period.

Description:
TECHNICAL FIELD OF THE INVENTION  
       [0001]     This invention relates to data transmission using Differential Signaling. In particular, this invention relates to a differential signaling driver that provides increased frequency response.  
       BACKGROUND OF THE INVENTION  
       [0002]     Low voltage differential signaling (LVDS) is used for high speed of data transmission with reduced noise and reduced electro-magnetic interference (EMI). Modern LVDS drivers are expected to operate at GHz frequencies. The range of the differential output voltage of the LVDS driver ranges from 250 mV to 450 mV.  
         [0003]     When a LVDS driver drives a heavy capacitive load such as a long cable or a high capacitance cable, its frequency of operation has to be decreased to get adequate output voltage differential that conforms to the specified range of 250 mV to 450 mV. To make the LVDS driver capable of operating at high frequency even for heavy capacitive loads, it is necessary to provide pre-emphasis circuitry. This pre-emphasis circuitry provides high driving capability to the LVDS driver at the time of switching, thereby significantly decreasing the charging time of the output load and making it possible to operate at high frequencies.  
         [0004]      FIG. 1  shows a low voltage differential signaling driver with pre-emphasis circuit in accordance with U.S. Pat. No. 6,281,715. LVDS driver  100  has a capability of providing output current ID 1 . The pre-emphasis circuit used with this driver provides an additional current ID 2  current at the time of switching making the driver capable of driving the heavy load at a faster signaling rate. The basic driver consists of a current source  10 , which is capable of sourcing current ID 1 . Four NMOS transistors N 1 -N 4  form a current steering circuit. The gates of these four NMOS transistors are controlled by two signals IN and IN˜(both of which are complementary to each other). Resistor  15  establishes a DC voltage to satisfy the high output voltage VOH and low output voltage VOL requirements. The drains of NMOS transistors N 3  and N 2  are connected to an output pad X. Similarly, the drains of N 1  and N 4  are connected to output pad Y. Pads X and Y form a differential pair. Both pads are connected to transmission lines (not shown here) and the far end of the transmission line (at the receiver end) is connected to a 100 ohm resistor  16 . PMOS transistor P 5  forms another current source having its source connected to the supply VDD and its gate voltage is controlled by a bias cell  30 . Bias cell  30  makes P 5  capable of sourcing current ID 2 . NMOS transistor N 5  acts as a current sink, having its source connected to ground and its gate voltage controlled by Bias cell  30 . Bias cell  30  makes N 5  capable of sinking current ID 2 . Transistors P 6  and N 6  are the control transistors, having their gates controlled by pre-emphasis pulse IXNOR. Pre-emphasis pulse IXNOR becomes high after each input transition. Inverter INV 4  generates the complementary signal IN˜. Inverters INV 1 -INV 3  with exclusive-NOR gate XNOR form the pre-emphasis pulse generator. Inverter INV 5  inverts the pre-emphasis pulse IXNOR. Transistors P 7 , N 7  and N 8  with resistor R 2  form bias cell  30 . This bias cell bias the PMOS P 5  as current source and NMOS N 5  as current sink.  
         [0005]     Let us consider the case when the input signal is at logic low, i.e. IN=0, so IN˜=1, a=0, b=1, IXNOR=0. Since IXNOR is low, NMOS N 6  and PMOS P 6  are switched off, so current ID 2  is not provided to the output driver  100 . In this case NMOS transistors N 1  and N 2  are on, and N 3  and N 4  are off, causing current ID 1  to flow through resistor  16  from Y to X, setting Y to VOH and X to VOL. Similarly when IN=1, IN˜=0, a=1, b=0, IXNOR=0, turning off pre-emphasis transistors N 6  and P 6  and providing no current to output driver  100 . Since IN=1 and IN˜=0, NMOS transistors N 3  and N 4  are on, and N 1  and N 2  are off. In this case current ID 1  flows through resistor  16  from X to Y, producing a voltage drop across resistor  16 . In this case X is at VOH and Y is at VOL. During DC operation only ID 1  produces the output voltage across the pads X and Y. The ID 1  current is capable of producing the appropriate differential output voltage (between 250 mV and 450 mV) across resistor  16  (Vod=ID 1 *RL).  
         [0006]     When input IN changes from ‘0’ to ‘1’, ‘a’ becomes ‘1’ immediately but ‘b’ is still at ‘1’ due to the delay provided by the delay chain of inverters INV 1 -INV 3 , resulting in a positive pre-emphasis pulse at IXNOR. This pre-emphasis pulse switches N 6  and P 6  ON and current ID 2  is supplied to output driver  100 . Since IN=1, IN˜=0, transistors N 3  and N 4  turn ON and allow current ID 1 +ID 2  to flow through output resistor  16  from X to Y. After the time delay of inverters INV 1 -INV 3 , ‘b’ becomes low, which makes pre-emphasis pulse IXNOR low, which turns off transistors N 6  and P 6 , cutting off the ID 2  current supply to output driver  100 .  
         [0007]     Similarly, when input IN changes from ‘1’ to ‘0’, ‘a’ becomes ‘0’ immediately but ‘b’ is still at ‘0’, which produces a positive pre-emphasis pulse at IXNOR. This pre-emphasis pulse switches N 6  and P 6  on and current ID 2  is supplied to output driver  100 . Since IN=0, IN˜=1, transistors N 1  and N 2  turn ON and allow current ID 1 +ID 2  to flow through output resistor  16  from Y to X. In this manner, the LVDS driver of  FIG. 1  provides an output current of ID 1 +ID 2  at the time of input signal transitions, making it possible to drive capacitive loads at high frequency. The pre-emphasis pulse generator consists of the inverters INV-INV 3  and XNOR gate XNOR.  
         [0008]     This design of pre-emphasis is however, not suitable for very high frequency operation. This limitation arises from the fact that the output of the pre-emphasis pulse IXNOR is delayed with respect to the input signal IN by a value equal to the propagation delay of the XNOR gate. In fact, in this arrangement, whatever the circuitry is used to generate the pre-emphasis pulse IXNOR will add some delay with respect to the input signal IN. For operating frequencies up to about 500 MHz this delay of the pre-emphasis circuit is not very significant and may be ignored. However, at higher frequencies of operation, the delay of this pre-emphasis circuit becomes significant. At a frequency of 1 GHz, the pulse period is 0.5 ns and even a small propagation delay of about 100 ps significantly derates the operation of LVDS driver when driving capacitive loads. As an example, assuming the pre-emphasis circuit shows the delay of 150 ps and the operating frequency of operation is 1 GHz, the pre-emphasis current ID 2  starts boosting the output driver  100  after 150 ps and has a total of 350 ps to provide this current. In this condition, the LVDS driver with pre-emphasis is not capable of providing the required swing at the output pads X and Y. To compensate for this swing one method is to increase the pre-emphasis current ID 2 , but this results in an unnecessary increase in the size of transistors P 5  and N 5 . Also this design of LVDS driver with pre-emphasis contains a Bias cell  30  that causes unnecessary power dissipation.  
       SUMMARY OF THE INVENTION  
       [0009]     To address the above-discussed deficiencies of the prior art, an object of this invention is to obviate the above drawbacks and provide a Differential Signaling driver with pre-emphasis that is capable of very high frequency operation.  
         [0010]     To achieve the said objective, this invention provides a Differential Signaling line driver including a pre-emphasis circuit, which boosts the output drive current without any delay whenever there is a transition in the input signal to the driver, using the input signal itself to provide the pre-emphasis through a current steering circuit that switches the direction of drive currents to provide a differential output signal. A delayed signal is then used to disable the pre-emphasis after a short period.  
         [0011]     Accordingly, the invention provides an improved differential signaling driver providing increased frequency response, comprising: 
        an output driver receiving the differential input signals and providing a differential output current to drive the load,     a delay stage for delaying the transitions of said differential input signal, and     a pre-emphasis stage directly driven by said differential input signals for providing an additional differential current in parallel with the output stage to boost the current to the load, said pre-emphasis stage being enabled at each transition of the input signals and disabled by the delayed transitions from the output of said delay stage.        
 
         [0015]     The output driver is a current steering circuit.  
         [0016]     The delay stage is a pair of delay chains, each comprising an even number of inverters connected in series.  
         [0017]     The pre-emphasis stage is a pair of inverters each driven by one of the complementary input signals, each inverter comprising complementary series connected switches controlled by the delayed version of the complementary input signal.  
         [0018]     The instant invention also provides a method for improving the frequency response of a differential signaling driver, comprising the steps of: 
        using the differential input signals to provide a differential output drive to the load,     delaying the transitions of the differential input signals,     enabling a boost current in parallel with said differential output drive, with each transition of the input differential signals, and     disabling said boost current with the delayed transitions of the input differential signals.        
 
         [0023]     Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; and the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0024]     The invention will now be explained with reference to the accompanying drawings, in which like reference numerals represent like parts, and in which:  
         [0025]      FIG. 1  shows the LVDS driver with pre-emphasis circuit according to the prior art.  
         [0026]      FIG. 2  shows the LVDS driver with pre-emphasis circuit according to the present invention.  
         [0027]      FIG. 3   a  and  FIG. 3   b  shows the timing diagram of the LVDS driver with pre-emphasis according to the present invention.  
         [0028]      FIG. 4  Shows the output waveform of the LVDS driver without pre-emphasis circuit.  
         [0029]      FIG. 5  shows the output waveform of the LVDS driver with pre-emphasis circuit.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0030]      FIGS. 2 through 5 , discussed below, and the various embodiments used to describe the principles of the present invention in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the invention. Those skilled in the art will understand that the principles of the present invention may be implemented in any suitably arranged image processing system.  
         [0031]      FIG. 2  shows the LVDS driver with pre-emphasis circuit according to the present invention. Block  100  is the output driver including current source  10  capable of sourcing current ID 1 . Resistor  15  sets high output voltage level VOH and low output voltage level VOL of the output differential signal. Four transistors P 1 , P 2 , N 1 , and N 2  form a current steering circuit. PMOS P 2  and NMOS N 1  of current steering circuit have their gates connected to one input signal IN 1  and their drains connected to the pad Y. PMOS transistor P 1  and NMOS transistor N 2  have their gates connected to the second input signal IN 2  and their drains connected to the pad X. Resistor  16  (RL=100 ohm) connected between X and Y is the resistor which is actually connected at the receiver end after transmission line (not shown here). IN 1  and IN 2  are the two complementary input signals. Block  50  and  60  are the pre-emphasis blocks having the same architecture and connected to the pads Y and X respectively. Block  50  consists of two PMOS transistors P 51  and P 52  connected in series between pad Y and supply voltage VDD. Two NMOS transistors N 51  and N 52  are connected in series between pad Y and ground. The gates of N 51  and P 51  are connected to input signal IN 1 . The gates of transistors P 52  and N 52  are controlled by the signal IN 2   13  delay, generated from delay element  30 . The second pre-emphasis block  60  consists of two PMOS transistors P 61  and P 62  connected in series between pad X and supply VDD. Two NMOS transistors N 61  and N 62  are connected in series between pad X and ground. The gates of transistors N 61  and P 61  are controlled by input signal IN 2  and the gates of P 62  and N 62  are controlled by signal IN 13  delay generated by delay element  20 . Delay elements  20  and  30  are used to produce delayed signals of IN 1  and IN 2 . Both the delay elements provide the same delay. The polarity of the output of the delay element is the same as its input signal. The delay element may consist of a chain of an even number of inverters (for examples four inverters in series). The maximum delay of the delay element must be less than the minimum pulse duration of the input signals (IN 1  or IN 2 ) i.e. maximum delay must be less than the half of the time period of the input signals. For example, if the maximum frequency of operation is 1 GHz (the time period of the input signals IN 1  and IN 2  is 1 ns with a 0.5 ns pulse width) the maximum delay of delay element can be 0.4 ns. For this period pre-emphasis block  50  and  60  need to have sufficient capability to drive the required capacitive load at a 1 GHz operating frequency.  
         [0032]      FIG. 3   a  and  FIG. 3   b  show the timing diagram of the input signal and delayed signal. In  FIG. 3   a  waveform  10  is the input IN 1  and waveform  20  is input IN 2 . Both the signals are complementary to each other. Waveform  30  of  FIG. 3   a  is the waveform of the delayed signal IN 2   13  delay. The delay provided by the delay element  30  is T. When IN 1  goes high at t 1  IN 2  goes low and IN 2   13  delay goes low at t 2  after a delay of T as shown. Similarly when IN 1  goes low at t 3 , IN 2  goes high and IN 2   13  delay goes high at t 4  after a delay of T. In  FIG. 3   b  waveform  50  is the waveform of IN 2 , waveform  60  is the waveform of IN 1  and waveform  70  is the waveform of signal IN 1   13  delay. Delay element  20  provides a delay of T to the input signal IN 1 .  
         [0033]     When at time t 1  input signal IN 1  rises from ‘0’ to ‘1’, IN 2  falls from ‘1’ to ‘0’. At this time t 1 , IN 1 =1, IN 2 =0. From  FIG. 3   a  and  FIG. 3   b  at time t 1 , IN 1   13  delay=0 and IN 2   13  delay=1. In block  100  of  FIG. 2 , transistors N 1  and P 1  are on and transistors P 2  and N 2  are off. This causes current ID 1  to flow from transistor P 1  through resistor  16  and transistor N 1  to resistor  15 . Pad X has high output voltage VOH and pad Y has low output voltage VOL. In pre-emphasis block  50 , at time t 1 , IN 1  and IN 2   13  delay are both ‘1’, turning on NMOS transistors N 51  and N 52  on thereby assisting pad Y to come to VOL level at a faster rate for high load at pad Y. Also at a time just before t 1 , IN 2   13  delay is ‘1’, so transistor N 52  is already on before IN 1  becomes ‘1’ and switches N 51  on. In the same manner, for pre-emphasis block  60 , at time t 1 , IN 2  is ‘0’ and IN 1   13  delay is ‘0’, which turns on PMOS transistors P 62  and P 61  and NMOS transistors N 61  and N 62  off. This assists pad X in reaching the VOH level at a faster rate. At time t 2 , IN 1  and IN 2  are ‘1’ and ‘0’ respectively, IN 1   13  delay changes its state from ‘0’ to ‘1’ and IN 2   13  delay changes its state from ‘1’ to ‘0’. Since at time t 2 , IN 2   13  delay becomes ‘0’, this switches off NMOS transistor N 52  and disables the sinking path for pad Y. For pre-emphasis block  50 , at t 2  P 52  is on but P 51  is off, so after time t 2  pre-emphasis block  50  is isolated from the output driver  100 . For block  60 , at time t 2 , IN 2  is 0 and IN 1   13  delay is ‘1’, which switches P 62  off and disables the sourcing path for pad X. For block  60 , at time t 2  N 61  is off. So after time t 2  pre-emphasis block  60  is isolated from output driver  100 .  
         [0034]     At time t 3 , IN 1  switches from ‘1’ to ‘0’ and IN 2  switches from ‘0’ to ‘1’ but IN 1   13  delay and IN 2   13  delay remain at their previous states. In output driver  100 , at time t 3 , P 2  and N 2  are on and P 1  and N 1  are off. Current ID 1  flows from transistor P 2  through resistor  16  (from Y to X), transistor N 2  and resistor  15  to ground. Pad Y will be at higher voltage than pad X. For pre-emphasis block  50 , at time t 3  (IN 1 =0 and IN 2   13  delay=0), P 51  and P 52  are on, N 51  and N 52  are off. Therefore block  50  attempts to pull the pad Y towards the higher voltage level thereby assisting output driver  100 . For pre-emphasis block  60  at time t 3 , IN 2 =1 and IN 1   13  delay= 1 , which switches N 61  and N 62  on and P 61  and P 62  are off. Block  60  tries to pull the pad X towards the lower voltage level. Since output driver  100  is also pulling the pad X towards lower voltage, the pre-emphasis circuit boosts it. In this manner, when there is a transition of IN 1  and IN 2  at t 3 , boosting is provided by pre-emphasis blocks  50  and  60 .  
         [0035]     At time t 4 , after the delay of T from t 3 , IN 1  and IN 2  have same signaling status as at t 3  but IN 1   13  delay changes from ‘1’ to ‘0’ and IN 2   13  delay changes from ‘0’ to ‘1’. So at time t 4  for block  50  IN 1 =0 and IN 2   13  delay=1, PMOS P 52  is off, PMOS P 51  is on, NMOS N 51  is off and NMOS N 52  is on. After time t 4 , block  50  stops pulling the pad Y towards the high voltage level and since the NMOS path is also off, block  50  is isolated from the output driver  100  after time t 4 . For block  60 , IN 2 =1 and IN 1   13  delay=0, N 62  is off N 61  is on, P 61  is off and P 62  is on. Again after time t 4  block  60  stops boosting the pad X towards the lower voltage level.  
         [0036]     In this manner, for each transition, pre-emphasis blocks  50  and  60  boost current to the pads Y and X respectively and after a time delay of T, blocks  50  and  60  are isolated from the respective pads. This time period T can be defined as the pre-emphasis period. The pre-emphasis period must be less than the minimum pulse duration (maximum operating frequency) of the input signal IN 1  and IN 2 .  
         [0037]     The main advantage of the LVDS driver with pre-emphasis circuit of the present invention is that it starts boosting the output current to the output as soon as input signal changes its state. Pre-emphasis blocks  50  and  60  are directly controlled by the input signals IN 1  and IN 2 . As shown in  FIG. 3   a  and  FIG. 3   b  the pre-emphasis period for the low to high transition of IN 1 , starts at time t 1  when IN 1  changes its state and it remains for time T upto t 2  which is less than the pulse duration of IN 1  (pulse duration for IN 1  is from time t 1  to t 3 ). For this period of time pre-emphasis blocks  50  and  60  need to have sufficient driving capability to drive the load. In the prior art, pre-emphasis current source transistor P 5  and current sink transistor N 5  have their gates connected to a bias voltage (which is an intermediate voltage, neither zero nor one) provided by the bias cell  30 . Higher sourcing and sinking capability in P 5  and N 5 , requires their sizes to be kept large. On the other hand, in the present the gates of all pre-emphasis transistors (P 51 - 52 , N 51 - 52 , P 61 - 62 , and N 61 - 62 ) are controlled by digital signal levels making it possible to provide the same drive capability with smaller transistors. Also no extra bias cell (as of bias cell  30  of  FIG. 1 ) is required.  
         [0038]     FIG. 4  shows the waveform at the output of block  100  without the pre-emphasis circuitry. This is the output wave form at 1 GHz frequency for 25 pf load. As it can be seen from the wave forms of X and Y, the output voltage difference is below the minimum limit (250 mV). For this particular example the output differential swing is around 72 mV. To get the required swing at output for this high capacitive load, the frequency of the operation would have to be reduced.  
         [0039]     FIG. 5  shows the waveform of the LVDS driver with the pre-emphasis circuitry of present invention. This is the waveform for 25 pf load and at 1 GHz operating frequency. The output differential swing in this case is around 260 mV confirming the capability of the LVDS driver of the present invention for driving high capacitive loads at high frequency.  
         [0040]     It will be apparent to those with ordinary skill in the art that the foregoing is merely illustrative intended to be exhaustive or limiting, having been presented by way of example only and that various modifications can be made within the scope of the above invention.  
         [0041]     Accordingly, this invention is not to be considered limited to the specific examples chosen for purposes of disclosure, but rather to cover all changes and modifications, which do not constitute departures from the permissible scope of the present invention. The invention is therefore not limited by the description contained herein or by the drawings, but only by the claims. It is intended that the present invention encompass such changes and modifications as fall within the scope of the appended claims.