Abstract:
A semiconductor package may include a packaging substrate, a first semiconductor chip on the packaging substrate, and a support plate on the packaging substrate. The support plate may be spaced apart from the first semiconductor chip in a direction parallel with respect to a surface of the packaging substrate. A second semiconductor chip may be provided on the first semiconductor chip and on the support plate so that the first semiconductor chip is between the second semiconductor chip and the packaging substrate and so that the support plate is between the second semiconductor chip and the packaging substrate. An adhesion layer may bond the second semiconductor chip to the first semiconductor chip and may bond the second semiconductor chip to the support plate. In addition, an electrical coupling may be provided between the first semiconductor chip and the packaging substrate.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2011-0088094 filed on Aug. 31, 2011, the disclosure of which is hereby incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Field 
         [0003]    Embodiments of inventive concepts relate to semiconductor packages having supporting plates and a plurality of semiconductor chips, and methods of forming the same. 
         [0004]    2. Description of Related Art 
         [0005]    Research into various methods of reducing the size of a semiconductor packages and mounting a plurality of semiconductor chips has been underway. 
       SUMMARY 
       [0006]    Embodiments of inventive concepts may provide a semiconductor package capable of shortening a signal transmission path, reducing size, and/or mounting a plurality of semiconductor chips. 
         [0007]    Problems to be resolved according to inventive concept may not be limited to the above, and other problems that are not described may be understood by one of ordinary skill in the art based on the following descriptions. 
         [0008]    In accordance with some aspects of inventive concepts, a semiconductor package may be provided. The semiconductor package may include a first semiconductor chip mounted on a substrate. At least one supporting plate may be mounted on the substrate and disposed on the same level as the first semiconductor chip. A first conductive connection may be disposed between the first semiconductor chip and the supporting plate, and may be configured to connect the first semiconductor chip to the substrate. A chip stack may be mounted on the supporting plate and the first semiconductor chip. The chip stack may have a plurality of second semiconductor chips, and first and second adhesion layers may be provided. The first adhesion layer may be formed between a lowermost second semiconductor chip of the plurality of second semiconductor chips and the supporting plate and between the lowermost second semiconductor chip and the first semiconductor chip. The second adhesion layer may be formed between the plurality of second semiconductor chips. The first adhesion layer may be thicker than the second adhesion layer. The first conductive connection may penetrate the inside of the first adhesion layer. 
         [0009]    In an applied embodiment, the first adhesion layer may have the same width as the lowermost second semiconductor chip. 
         [0010]    In another embodiment, the first adhesion layer may be in direct contact with the lowermost second semiconductor chip, the supporting plate, and the first semiconductor chip. 
         [0011]    In still another embodiment, the supporting plate may include a first supporting plate, and a second supporting plate separated from the first supporting plate. The first semiconductor chip may be disposed between the first and second supporting plates. 
         [0012]    In yet another embodiment, the supporting plate may be a dummy chip having the same vertical thickness as the first semiconductor chip. 
         [0013]    In yet another embodiment, top surfaces of the supporting plate and the first semiconductor chip may have substantially the same horizontal level. 
         [0014]    In yet another embodiment, a part of the plurality of second semiconductor chips may be sequentially offset-aligned in a first direction and may constitute a first chip stack. Another part of the plurality of second semiconductor chips may be sequentially offset-aligned on the first chip stack in a second direction different from the first direction and may constitute a second chip stack. 
         [0015]    In yet another embodiment, the first semiconductor chip may be a logic chip, and the plurality of second semiconductor chips may be memory chips. 
         [0016]    In yet another embodiment, a buffer chip may be mounted between the substrate and the chip stack. A second conductive connection may be configured to connect the buffer chip to the substrate. The second conductive connection may penetrate the inside of the first adhesion layer. 
         [0017]    In yet another embodiment, a passive device may be mounted on the same level as the supporting plate. 
         [0018]    In yet another embodiment, the first conductive connection may include a wire bonding. 
         [0019]    In accordance with another aspect of inventive concepts, a semiconductor package may be provided. The semiconductor package may include a first semiconductor chip mounted on a substrate. A first conductive connection may be configured to connect the first semiconductor chip to the substrate. At least one supporting plate may be mounted on the substrate and disposed on the same level as the first semiconductor chip. A chip stack may be mounted on the supporting plate and the first semiconductor chip. The chip stack may have a plurality of second semiconductor chips, a first adhesion layer and a second adhesion layer. A second conductive connection may be configured to sequentially connect the plurality of second semiconductor chips, and to connect a lowermost second semiconductor chip of the plurality of second semiconductor chips to the substrate. A second chip stack may be mounted on the first chip stack. The second chip stack may have a plurality of third semiconductor chips, a third adhesion layer, and a fourth adhesion layer. The first adhesion layer may be formed between the lowermost second semiconductor chip and the supporting plate and between the lowermost second semiconductor chip and the first semiconductor chip. The second adhesion layer may be formed between the plurality of second semiconductor chips. The third adhesion layer may be formed between an uppermost second semiconductor chip of the plurality of second semiconductor chips and a lowermost third semiconductor chip of the plurality of third semiconductor chips. The fourth adhesion layer may be formed between the plurality of third semiconductor chips. The third adhesion layer may be thicker than the second adhesion layer. The second conductive connection may penetrate the inside of the third adhesion layer. A sidewall of an uppermost semiconductor chip of the first chip stack may be vertically aligned with that of a lowermost semiconductor chip of the second chip stack. 
         [0020]    In another embodiment, the plurality of second semiconductor chips may be sequentially stacked, and sequentially offset-aligned in a first direction. The plurality of third semiconductor chips may be sequentially stacked, and sequentially offset-aligned in a second direction different from the first direction. 
         [0021]    In still another embodiment, the second conductive connection may be separated from the second adhesion layer. 
         [0022]    Details of other embodiments of inventive concepts are included in the detailed description and the drawings. 
         [0023]    In accordance with still other aspects of inventive concepts, a semiconductor package may include a packaging substrate, a first semiconductor chip on the packaging substrate, and a support plate on the packaging substrate. The support plate may be spaced apart from the first semiconductor chip in a direction parallel with respect to a surface of the packaging substrate. A second semiconductor chip may be provided on the first semiconductor chip and on the support plate so that the first semiconductor chip is between the second semiconductor chip and the packaging substrate and so that the support plate is between the second semiconductor chip and the packaging substrate. An adhesion layer may bond the second semiconductor chip to the first semiconductor chip and may bond the second semiconductor chip to the support plate. In addition, an electrical coupling may be provided between the first semiconductor chip and the packaging substrate, with at least a portion of the electrical coupling being physically located directly between second semiconductor chip and the packaging substrate in a direction perpendicular with respect to the surface of the packaging substrate. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0024]    The foregoing and other features and advantages of inventive concepts will be apparent from the more particular description of embodiments of inventive concepts, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating principles of inventive concepts. In the drawings: 
           [0025]      FIG. 1  is a cross-sectional view of a semiconductor package according to first embodiments of inventive concepts; 
           [0026]      FIG. 2A  is a partial enlarged view of portion E 1  of  FIG. 1 , and  FIG. 2B  is a partial enlarged view of portion E 2  of  FIG. 1 ; 
           [0027]      FIG. 2C  is a partial enlarged view of a semiconductor package according to an application of first embodiments; 
           [0028]      FIGS. 3 to 15  are layout diagrams and cross-sectional views of a semiconductor package according to second embodiments of inventive concepts; 
           [0029]      FIGS. 16 to 19  are cross-sectional views illustrating methods of forming a semiconductor package according to third embodiments of inventive concepts; 
           [0030]      FIGS. 20 and 21  are a layout diagram and a cross-sectional view of a card package according to fourth embodiments of inventive concepts; and 
           [0031]      FIGS. 22 and 23  are a perspective view and a system block diagram of an electronic device according to fifth embodiments of inventive concepts. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0032]    Various embodiments will now be described more fully with reference to the accompanying drawings in which some embodiments are shown. Inventive concepts may, however, be embodied in different forms and should not be construed as limited to embodiments set forth herein. Rather, these embodiments are provided so that this disclosure is thorough and complete and fully conveys the scope of inventive concepts to one skilled in the art. In the drawings, thicknesses of layers and regions may be exaggerated for clarity. Also, when a layer is referred to as “on” another layer or a substrate, it may be directly formed on another layer or the substrate or a third layer may be interposed therebetween. Like reference numerals designate like elements throughout the specification. 
         [0033]    It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of inventive concepts. 
         [0034]    Relative terms such as “below” or “above” or “upper” or “lower” may be used herein to describe a relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. 
         [0035]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of inventive concepts. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
         [0036]    Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which inventive concepts belong. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this disclosure and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
       First Embodiments  
       [0037]      FIG. 1  is a cross-sectional view of a semiconductor package according to first embodiments of inventive concepts,  FIG. 2A  is a partial enlarged view of portion E 1  of  FIG. 1 ,  FIG. 2B  is a partial enlarged view of portion E 2  of  FIG. 1 , and  FIG. 2C  is a partial enlarged view of a semiconductor package according to an application of first embodiments. 
         [0038]    Referring to  FIGS. 1 ,  2 A and  2 B, a first semiconductor chip  7  and a supporting plate  50  may be mounted on a substrate  3 . A chip stack  9  may be mounted on the first semiconductor chip  7  and the supporting plate  50 . An encapsulant  59  may be provided on the substrate  3  covering the first semiconductor chip  7 , the supporting plate  50 , and the chip stack  9 . 
         [0039]    A bottom surface of the substrate  3  may be covered with a lower solder resist  2 , and a top surface of the substrate  3  may be covered with an upper solder resist  4 . A first electrode finger(s)  31 , a second electrode finger(s)  33 , and a third electrode finger(s)  35  may be formed on the substrate  3  penetrating the upper solder resist  4 . A first adhesion layer  51  may be interposed between the substrate  3  and the supporting plate  50 . A second adhesion layer  53  may be interposed between the substrate  3  and the first semiconductor chip  7 . A first conductive connection(s)  41  may be formed between the first semiconductor chip  7  and the first electrode finger(s)  31 . The first conductive connection(s)  41  may include a bonding wire, a beam lead, a conductive tape, a conductive spacer, a through electrode, a solder ball, a solder bump, and/or a combination thereof. The first conductive connection(s)  41  may be a bonding wire. 
         [0040]    The first semiconductor chip  7  may be a logic chip such as a controller. The supporting plate  50  may have substantially the same vertical thickness as the first semiconductor chip  7 . The supporting plate  50  may be a dummy chip having a constitution similar to that of to the first semiconductor chip  7 . The first semiconductor chip  7  and the supporting plate  50  may be mounted on a same level. Top surfaces of the first semiconductor chip  7  and the supporting plate  50  may be disposed on substantially a same horizontal level. Stated in other words, top surfaces of the first semiconductor chip  7  and the supporting plate  50  may be substantially co-planar. 
         [0041]    The chip stack  9  may include a first chip stack  10  and a second chip stack  20  on the first chip stack  10 . The first chip stack  10  may include second to fifth semiconductor chips  11 ,  12 ,  13 , and  14 , and the second chip stack  20  may include sixth to ninth semiconductor chips  21 ,  22 ,  23 , and  24 . The second to ninth semiconductor chips  11 ,  12 ,  13 ,  14 ,  21 ,  22 ,  23 , and  24  may be memory chips. For example, each of the second to ninth semiconductor chips  11 ,  12 ,  13 ,  14 ,  21 ,  22 ,  23 , and  24  may include a non-volatile memory device such as a NAND flash memory. 
         [0042]    The second to fifth semiconductor chips  11 ,  12 ,  13 , and  14  may be stacked in a first cascade structure. That is, the second to fifth semiconductor chips  11 ,  12 ,  13 , and  14  may be sequentially offset-aligned. Each of the second to fifth semiconductor chips  11 ,  12 ,  13 , and  14  may have a greater width than the first semiconductor chip  7 . The semiconductor chip  11  may be bonded onto the supporting plate  50  and the first semiconductor chip  7  using a third adhesion layer  54  of a first thickness T 1 . A side surface of the second semiconductor chip  11  may be vertically aligned with that of the supporting plate  50 . The other side surface of the second semiconductor chip  11  may be aligned on the first semiconductor chip  7 . The third to fifth semiconductor chips  12  to  14  may be sequentially stacked on the second semiconductor chip  11  using a fourth adhesion layer(s)  55  of a second thickness T 2 . In this case, the third to fifth semiconductor chips  12  to  14  may be sequentially offset-aligned in a direction of a first side surface S 1  of the substrate  3 . 
         [0043]    The first thickness T 1  of the third adhesion layer  54  may be larger than the second thickness T 2  of the fourth adhesion layer(s)  55 . The first conductive connection(s)  41  may penetrate the inside of the third adhesion layer  54 . For example, when the first conductive connection(s)  41  is a bonding wire, a part of the bonding wire may partially penetrate or pass through the third adhesion layer  54 . 
         [0044]    When the first conductive connection(s)  41  penetrates or passes through the third adhesion layer  54 , an electrical connection may be made even though a top surface of the first semiconductor chip  7  is not exposed. Therefore, the first conductive connection(s)  41  may be formed between the supporting plate  50  and the first semiconductor chip  7 . As a result, the horizontal widths of the semiconductor packages according to inventive concepts may be reduced. Specifically, if the first conductive connection(s)  41  does not penetrate or pass through the third adhesion layer  54 , the first conductive connection(s)  41  may be formed on the outside of an area occupied by the chip stack  9  and/or outside of the first semiconductor chip  7 . However, since the first conductive connection(s)  41  may be capable of penetrating or passing through the third adhesion layer  54 , the first conductive connection(s)  41  may be formed between the first semiconductor chip  7  and the supporting plate  50 , i.e., within an area occupied by the chip stack  9 . Therefore, a horizontal width of an area occupied by the semiconductor package may be reduced by as much as an area occupied by the first conductive connection(s) 
         [0045]    The third adhesion layer  54  may have the same width as the second semiconductor chip  11 . The third adhesion layer  54  may be aligned with a surface of the second semiconductor chip  11 . The third adhesion layer  54  may be in direct contact with the second semiconductor chip  11 , the first semiconductor chip  7 , and the supporting plate  50 . 
         [0046]    The third adhesion layer  54  may be referred to as a direct adhesive film (DAF) or a film over wire (FOW). The fourth adhesion layer(s)  55  may be a material layer of the same type as the third adhesion layer  54 . In this case, the second thickness T 2  of the fourth adhesion layer(s)  55  may be smaller than the first thickness T 1  of the third adhesion layer  54 . In some embodiments, the fourth adhesion layer(s)  55  may be a different material layer from the third adhesion layer  54 . 
         [0047]    A second conductive connection(s)  43  may be formed between the first chip stack  10  and the second electrode finger(s)  33 . The second semiconductor chip  11  may be connected to the second electrode finger(s)  33  and the second to fifth semiconductor chips  11 ,  12 ,  13  and  14  may be connected to each other by the second conductive connection(s)  43 . As illustrated in the drawings, the second conductive connection(s)  43  may be sequentially in contact with the second to fifth semiconductor chips  11 ,  12 ,  13  and  14 , and one end of the second conductive connection(s)  43  may be in contact with the second electrode finger(s)  33 . The second conductive connection(s)  43  may be separated from the fourth adhesion layer(s)  55 . The second conductive connection(s)  43  may include a bonding wire(s), a beam lead(s), a conductive tape(s), a conductive spacer(s), a through electrode(s), a solder ball(s), a solder bump(s) and/or a combination thereof. Embodiments of  FIG. 1  are described on the assumption that the second conductive connection(s)  43  is a bonding wire. 
         [0048]    The sixth to ninth semiconductor chips  21 ,  22 ,  23  and  24  may be stacked in a second cascade structure. The sixth to ninth semiconductor chips  21 ,  22 ,  23  and  24  may be aligned in a different direction from the second to fifth semiconductor chips  11 ,  12 ,  13  and  14 . That is, the sixth to ninth semiconductor chips  21 ,  22 ,  23  and  24  may be sequentially offset-aligned in a different direction from the second to fifth semiconductor chips  11 ,  12 ,  13  and  14 . 
         [0049]    For example, the sixth semiconductor chip  21  may be bonded onto the fifth semiconductor chip  14  using a fifth adhesion layer  56  of a third thickness T 3 . The third thickness T 3  may be larger than the second thickness T 2 . The third thickness T 3  may be substantially the same as the first thickness T 1 . The sixth semiconductor chip  21  may be vertically aligned on the fifth semiconductor chip  14 . Side surfaces of the sixth semiconductor chip  21  and the fifth semiconductor chip  14  may be aligned along the same vertical line(s). The fifth adhesion layer  56  may be the same material layer as the third adhesion layer  54 . The second conductive connection(s)  43  may penetrate the inside of the fifth adhesion layer  56 . When the second conductive connection(s)  43  is a bonding wire, a part of the bonding wire may partially penetrate or pass through the fifth adhesion layer  56 . When the second conductive connection(s)  43  penetrates or passes through the inside of the fifth adhesion layer  56 , a horizontal width of the semiconductor package may be reduced. If the third thickness T 3  is not sufficient and/or the second conductive connection(s)  43  does not penetrate or pass through the inside of the fifth adhesion layer  54 , a semiconductor chip disposed at an uppermost part of the first chip stack  10 , (i.e., a part of a top surface of the fifth semiconductor chip  14 ) may need to be exposed for the purpose of an electrical connection to the second conductive connection(s)  43 . Therefore, in embodiments of inventive concepts, a side surfaces of the semiconductor chip  14  disposed at the uppermost part of the first chip stack  10  may be vertically aligned with that of the semiconductor chip  21  disposed at a lowermost part of the second chip stack  20 . That is, a horizontal width of the semiconductor package may be reduced by aligning the fifth and sixth semiconductor chips  14  and  21  so that a top surface of the semiconductor chip  14  is not exposed. 
         [0050]    The seventh to ninth semiconductor chips  22  to  24  may be sequentially bonded onto the sixth semiconductor chip  21  using sixth adhesion layer(s)  57 . The seventh to ninth semiconductor chips  22  to  24  may be sequentially offset-aligned on the sixth semiconductor chip  21  in a direction of a second side surface S 2  of the substrate  3  opposite the first side surface S 1 . The sixth adhesion layer(s)  57  may be formed of the same material layer formed to substantially the same thickness as the fourth adhesion layer(s)  55 . The fourth adhesion layer(s)  55  and the sixth adhesion layer(s)  57  may be the same material layer as the third adhesion layer  54 . 
         [0051]    A third conductive connection(s)  45  may be formed between the second chip stack  20  and the third electrode finger(s)  35 . The sixth semiconductor chip  21  may be connected to the third electrode finger(s)  35 , and the sixth to ninth semiconductor chips  21  to  24  may be connected to each other by the third conductive connection(s)  45 . As illustrated in  FIG. 1 , the third conductive connection(s)  45  may be sequentially in contact with the sixth to ninth semiconductor chips  21  to  24 , and one end of the third conductive connection(s)  45  may be in contact with the third electrode finger(s)  35 . The third conductive connection(s)  45  may be separated from the sixth adhesion layer(s)  57 . 
         [0052]    The third conductive connection(s)  45  may include a bonding wire(s), a beam lead(s), a conductive tape(s), a conductive spacer(s), a through electrode(s), a solder ball(s), a solder bump(s), and/or a combination thereof. Embodiments of  FIG. 1  are described on the assumption that the third conductive connection(s)  45  is a bonding wire. 
         [0053]    In addition, when the first conductive connection(s)  41  is formed between the supporting plate  50  and the first semiconductor chip  7 , the first conductive connection(s)  41  may not electrically or physically influence the third conductive connection(s)  45 . Therefore, the third conductive connection(s)  45  may be more electrically and/or physically stable, and may be simplified and may be formed with fewer restrictions. 
         [0054]    External terminals  5  penetrating the lower solder register  2  may be formed at a lower part of the substrate  3 . The first electrode finger(s)  31 , the second electrode finger(s)  33  and the third electrode finger(s)  35  may be electrically connected to respective ones of the external terminals  5  through the substrate  3 . The external terminals  5  may include solder balls, solder bumps, pin grid arrays, lead grid arrays, conductive tabs, and/or a combination thereof. 
         [0055]    In other embodiments, the substrate  3 , the first semiconductor chip  7 , the supporting plate  50 , the chip stack  9 , and the encapsulant  59  may be provided as a card-type package. In this case, the external terminals  5  may be omitted. 
         [0056]    In still other embodiments, the second to fifth semiconductor chips  11  to  14  and the sixth to ninth semiconductor chips  21  to  24  may be stacked on the supporting plate  50  and the first semiconductor chip  7  in a cascade, overhang or zigzag form, or in a combination form thereof. 
         [0057]    Referring to  FIG. 2C , the second semiconductor chip  11  may completely cover the first semiconductor chip  7 . 
         [0058]    As described above, a semiconductor package according to embodiments of inventive concepts may include a structure in which the second to fifth adhesion layers  11  to  14  and the sixth to ninth semiconductor chips  21  to  24  are stacked on the supporting plate  50  and the first semiconductor chip  7  using the third adhesion layer  54 , the fourth adhesion layer(s)  55 , the fifth adhesion layer  56  and the sixth adhesion layer(s)  57 . A part of the first conductive connection(s)  41  may partially penetrate or pass through the third adhesion layer  54 . The first conductive connection(s)  41  may be formed between the supporting plate  50  and the first semiconductor chip  7 . In this case, a horizontal width of the semiconductor package may be significantly reduced. Moreover, a part of the second conductive connection(s)  43  may partially penetrate or pass through the fifth adhesion layer  56 . The sixth semiconductor chip  21  may be vertically aligned on the fifth semiconductor chip  14 . In this case, a horizontal width of the semiconductor package may be reduced. Consequently, the semiconductor package may have an advantageous structure in terms of mounting of a plurality of semiconductor chips and reducing size. 
         [0059]    Also, the second to fifth semiconductor chips  11  to  14 , and/or the sixth to ninth semiconductor chips  21  to  24  may receive and/or transmit data from and to external devices via the first conductive connection(s)  41 , the second conductive connection(s)  43 , the third conductive connection(s)  45 , the first semiconductor chip  7 , and/or the substrate  3 . Accordingly, a signal transmission path of the semiconductor package may be significantly reduced compared to related art. Furthermore, a structure of the supporting plate  50 , the first semiconductor chip  7 , and the third adhesion layer  54  may improve structural stability of the second to ninth semiconductor chips  11 ,  12 ,  13 ,  14 ,  21 ,  22 ,  23  and  24 . 
       Second Embodiments  
       [0060]      FIGS. 3 to 8  are layout diagrams of a semiconductor package according to second embodiments of inventive concepts, and  FIGS. 9 to 15  are cross-sectional views of a semiconductor package according to second embodiments of inventive concepts. 
         [0061]    Referring to  FIG. 3 , a first semiconductor chip  7  may be disposed on substrate  3  to face a supporting plate  50 . The supporting plate  50  may be in the shape of a rectangle or bar. 
         [0062]    Referring to  FIGS. 4 to 6 , the supporting plate  50  may be in the shape of an L, a C, or a frame. 
         [0063]    Referring to  FIG. 7 , a first supporting plate  50 A, a second supporting plate  50 B, a third supporting plate  50 C, and a fourth supporting plate  50 D may be bonded onto a substrate  3 . The first supporting plate  50 A, the second supporting plate  50 B, the third supporting plate  50 C, and the fourth supporting plate  50 D may be aligned to surround the first semiconductor chip  7 . The first supporting plate  50 A, the second supporting plate  50 B, the third supporting plate  50 C, and the fourth supporting plate  50 D may have various sizes and shapes. 
         [0064]    Referring to  FIG. 8 , a supporting plate  50 , a first semiconductor chip  7 , a buffer chip  61  and a passive device  62  may be bonded onto a substrate  3 . The buffer chip  61  may be electrically connected to the substrate  3  using a fourth conductive connection(s)  42 . The supporting plate  50  may be modified into various sizes and shapes in response to disposition(s) of the first semiconductor chip  7 , the buffer chip  61 , and the passive device  62 . 
         [0065]    Referring to  FIG. 9 , a first supporting plate  50 A and a second supporting plate  50 B may be bonded onto a substrate  3  using a first adhesion layer(s)  51 . A first semiconductor chip  7  may be bonded onto the substrate  3  between the first supporting plate  50 A and the second supporting plate  50 B using a second adhesion layer  53 . A second semiconductor chip  11  may be mounted on the first supporting plate  50 A, the second supporting plate  50 B, and the first semiconductor chip  7  using a third adhesion layer  54 . A first conductive connection(s)  41  (penetrating the inside of the third adhesion layer  54 ) may connect to a first electrode finger(s)  3  of the first semiconductor chip  7 . 
         [0066]    Referring to  FIG. 10 , a first semiconductor chip  7 , a passive device  62 , and a supporting plate  50  may be mounted on a substrate  3 . The passive device  62  may be disposed between the first semiconductor chip  7  and the supporting plate  50 . Top surfaces of the first semiconductor chip  7 , the passive device  62 , and the supporting plate  50  may have substantially the same horizontal level. Stated in other words, top surfaces of the first semiconductor chip  7 , the passive device  62 , and the supporting plate  50  may be substantially co-planar. A second semiconductor chip  11  may be mounted on the first semiconductor chip  7 , the passive device  62  and the supporting plate  50  using a third adhesion layer  54 . The third adhesion layer  54  may be in contact with the second semiconductor chip  11 , the first semiconductor chip  7 , the passive device  62 , and the supporting plate  50 . The passive device  62  may include a chip capacitor, a chip resistor, and/or an inductor. As a chip capacitor, the passive device  62  may function as a decoupling capacitor. 
         [0067]    Referring to  FIG. 11 , a buffer chip  61  may be mounted between a substrate  3  and a chip stack  9 . For example, a first semiconductor chip  7 , the buffer chip  61 , and a supporting plate  50  may be mounted on the substrate  3 . The buffer chip  61  may be disposed between the first semiconductor chip  7 , and the supporting plate  50 . Top surfaces of the first semiconductor chip  7 , the buffer chip  61 , and the supporting plate  50  may have substantially the same horizontal level. Stated in other words, top surfaces of the first semiconductor chip  7 , the buffer chip  61 , and the supporting plate  50  may be substantially co-planar. The buffer chip  61  may be electrically connected to a fourth electrode finger(s)  32  formed on the substrate  3  by a fourth conductive connection(s)  42 . A second semiconductor chip  11  may be mounted on the first semiconductor chip  7 , the buffer chip  61 , and the supporting plate  50  using a third adhesion layer  54 . The third adhesion layer  54  may be in direct contact with the second semiconductor chip  11 , the first semiconductor chip  7 , the buffer chip  61 , and the supporting plate  50 . 
         [0068]    The fourth conductive connection(s)  42  may include a bonding wire(s), a beam lead(s), a conductive tape(s), a conductive spacer(s), a through electrode(s), a solder ball(s), a solder bump(s), and/or a combination thereof. In embodiments of  FIG. 12 , the fourth conductive connection(s)  42  may be a bonding wire(s). The fourth conductive connection(s)  42  may penetrate the inside of the third adhesion layer  54 . The buffer chip  61  may include a volatile memory device such as a DRAM or SRAM. 
         [0069]    A passive device  62  may be mounted on the substrate  3  adjacent to the first semiconductor chip  7 . The passive device  62  may be disposed between the first semiconductor chip  7  and a third electrode finger(s)  35 . 
         [0070]    In yet other embodiments, relative locations of the first semiconductor chip  7  and the buffer chip  61  may be changed. 
         [0071]    Referring to  FIG. 12 , a first semiconductor chip  7 , a buffer chip  61 , and a supporting plate  50  may be mounted on a substrate  3 . The first semiconductor chip  7  and the buffer chip  61  may be bonded onto the substrate  3  using a flip chip technique. For example, the first semiconductor chip  7  may be connected to a first electrode finger(s)  31 A formed on the substrate  3  using a first conductive connection(s)  41 A. A second adhesion layer  53 A may be formed between the first semiconductor chip  7  and the substrate  3 . The buffer chip  61  may be connected to a fourth electrode finger(s)  32 A formed on the substrate  3  using a fourth conductive connection  42 A. A seventh adhesion layer  52 A may be formed between the buffer chip  61  and the substrate  3 . 
         [0072]    The first conductive connection(s)  41 A and the fourth conductive connection(s)  42 A may be a solder ball(s) and/or a solder bump(s). The second adhesion layer  53 A and the seventh adhesion layer  52 A may include an under fill layer. 
         [0073]    A second semiconductor chip  11  may be mounted on the first semiconductor chip  7 , the buffer chip  61 , and the supporting plate  50  using a third adhesion layer  54 A. In this case, the third adhesion layer  54 A may be a material layer having substantially the same thickness as a fourth adhesion layer(s)  55 . 
         [0074]    A passive device  62  may be mounted on the substrate  3  between the first semiconductor chip  7  and a third electrode finger(s)  35 . 
         [0075]    Referring to  FIG. 13 , second to ninth semiconductor chips  11 ,  12 ,  13 ,  14 ,  21 ,  22 ,  23  and  24  may be mounted on the first semiconductor chip  7 , the buffer chip  61 , and the supporting plate  50  in an overhang structure. Stated in other words, the second to ninth semiconductor chips  11 ,  12 ,  13 ,  14 ,  21 ,  22 ,  23  and  24  may be sequentially and vertically stacked. The second semiconductor chip  11  may be bonded onto the first semiconductor chip  7 , the buffer chip  61 , and the supporting plate  50  using a third adhesion layer  54 . A fourth adhesion layer(s)  55  may be interposed between the second to ninth semiconductor chips  11 ,  12 ,  13 ,  14 ,  21 ,  22 ,  23  and  24 . The fourth adhesion layer(s)  55  may include the same material layer having substantially the same thickness as the third adhesion layer  54 . 
         [0076]    Each of the second to ninth semiconductor chips  11 ,  12 ,  13 ,  14 ,  21 ,  22 ,  23  and  24  may be connected to a second electrode finger(s)  33  and a third electrode finger(s)  35  using a second conductive connection(s)  43  and a third conductive connections)  45 . The second conductive connection(s)  43  and the third conductive connection(s)  45  may penetrate inside of the fourth adhesion layer(s)  55 . The second conductive connection(s)  43  may include a plurality of bonding wires, and the third conductive connection(s)  45  may include a plurality of bonding wires as well. In this case, each of the plurality of bonding wires may be in contact with the corresponding one of the second to ninth semiconductor chips  11 ,  12 ,  13 ,  14 ,  21 ,  22 ,  23  and  24 , and the second electrode finger(s)  33  or the third electrode finger(s)  35 . 
         [0077]    Referring to  FIG. 14 , the second to ninth semiconductor chips  11 ,  12 ,  13 ,  14 ,  21 ,  22 ,  23  and  24  may be mounted on the first semiconductor chip  7 , the buffer chip  61  and the supporting plate  50  in a zigzag structure. Each of the second to ninth semiconductor chips  11 ,  12 ,  13 ,  14 ,  21 ,  22 ,  23  and  24  may be connected to a second electrode finger(s)  33  or a third electrode finger(s)  35  using a second conductive connection(s)  43  or a third conductive connection(s)  45 . The second conductive connection(s)  43  and the third conductive connection(s)  45  may be separated from a fourth adhesion layer(s)  55 . The fourth adhesion layer(s)  55  may be thinner than the third adhesion layer  54 . 
         [0078]    Referring to  FIG. 15 , a first semiconductor chip  7  and a supporting plate  50  may be mounted on a substrate  3 . The first semiconductor chip  7  may include a first through electrode(s)  71 , and the supporting plate  50  may include a second through electrode(s)  73 . First solder balls  41 A may be formed between the first through electrode(s)  71  and first electrode finger(s)  31 A and between the second through electrode(s)  73  and a second electrode finger(s)  33 A. A first adhesion layer  51 A may be formed between the supporting plate  50  and the substrate  3 , and a second adhesion layer  53 A may be formed between the first semiconductor chip  7  and the substrate  3 . The first adhesion layer  51 A and the second adhesion layer  53 A may include an under fill layer. 
         [0079]    The second to ninth semiconductor chips  11 ,  12 ,  13 ,  14 ,  21 ,  22 ,  23  and  24  may be vertically stacked on the supporting plate  50  and the first semiconductor chip  7 . Each of the second to ninth semiconductor chips  11 ,  12 ,  13 ,  14 ,  21 ,  22 ,  23  and  24  may include third through electrodes  75 . Solder balls  72  may be formed on the third through electrodes  75 . The second to ninth semiconductor chips  11 ,  12 ,  13 ,  14 ,  21 ,  22 ,  23  and  24  may be in electrical contact with the first electrode finger(s)  31 A and the second electrode finger(s)  33 A via the third through electrodes  75 , the second solder balls  72 , the second through electrode(s)  73 , the first through electrode(s)  71 , and the first solder balls  41 A. 
       Third Embodiments  
       [0080]      FIGS. 16 to 19  are cross-sectional views illustrating methods of forming a semiconductor package according to third embodiments. 
         [0081]    Referring to  FIG. 16 , a first semiconductor chip  7  and a supporting plate  50  may be mounted on a substrate  3 . The first semiconductor chip  7  and the supporting plate  50  may be mounted on a same level. Top surfaces of the first semiconductor chip  7  and the supporting plate  50  may be exposed on substantially a same planar surface. Stated in other words, top surfaces of the first semiconductor chip  7  and the supporting plate  50  may be substantially co-planar. The supporting plate  50  may be bonded onto the substrate  3  using a first adhesion layer  51 . The first semiconductor chip  7  may be bonded onto the substrate  3  using a second adhesion layer  53 . 
         [0082]    The substrate  3  may be a rigid printed circuit board, a flexible printed circuit board or a rigid-flexible printed circuit board. A first electrode finger(s)  31 , a second electrode finger(s)  33  and a third electrode finger(s)  35  may be formed on a surface of the substrate  3 . A lower solder resist  2  covering a bottom surface of the substrate  3  may be formed, and an upper solder resist  4  covering a top surface of the substrate  3  and exposing the first electrode finger(s)  31 , the second electrode finger(s)  33 , and the third electrode finger(s)  35  may be formed. 
         [0083]    A first conductive connection(s)  41  may be formed between the first electrode finger(s)  31  and the first semiconductor chip(s)  7 . The first conductive connection(s)  41  may include a bonding wire(s), a beam lead(s), a conductive tape(s), a conductive spacer(s), a through electrode(s), a solder ball(s), a solder bump(s), and/or a combination thereof. In embodiments of  FIG. 16 , the first conductive connection(s)  41  may be a bonding wire(s). The bonding wire(s) may be a gold (Au) wire(s) or an aluminum (Al) wire(s). 
         [0084]    The supporting plate  50  may be a dummy chip having the same vertical thickness as the first semiconductor chip  7 . In other embodiments, the supporting plate  50  may include a printed circuit board, a metal plate, a plastic plate, and/or a semiconductor substrate. 
         [0085]    Referring to  FIG. 17 , a first chip stack  10  may be mounted on the supporting plate  50  and the first semiconductor chip  7 . The first chip stack  10  may include second to fifth semiconductor chips  11 ,  12 ,  13  and  14 . The second to fifth semiconductor chips  11  to  14  may be stacked in a first cascade structure. 
         [0086]    The second semiconductor chip  11  may be bonded onto the supporting plate  50  and the first semiconductor chip  7  using a third adhesion layer  54  of a first thickness T 1 . One side surface of the second semiconductor chip  11  may be vertically aligned with one side surface of the supporting plate  50 . The other side surface of the second semiconductor chip  11  may be aligned on the first semiconductor chip  7 . The third to fifth semiconductor chips  12  to  14  may be sequentially stacked on the second semiconductor chip  11  using a fourth adhesion layer(s)  55  of a second thickness T 2 . In this case, the third to fifth semiconductor chips  12  to  14  may be sequentially offset-aligned in the direction of the third electrode finger(s)  35 . 
         [0087]    The first thickness T 1  may be larger than the second thickness T 2 . The first conductive connection(s)  41  may penetrate the inside of the third adhesion layer  54 . For example, when the first conductive connection(s)  41  is a bonding wire(s), a part of the bonding wire(s) may partially penetrate or pass through the third adhesion layer  54 . The third adhesion layer  54  may be referred to as a direct adhesive film (DAF) or a film over wire (FOW). 
         [0088]    A second conductive connection(s)  43  may be formed between the first chip stack  10  and the second electrode finger(s)  33 . The second semiconductor chip  11  may be electrically connected to the second electrode finger(s)  33 , and the second to fifth semiconductor chips  11  to  14  may be connected to each other by the second conductive connection(s)  43 . As illustrated in  FIG. 17 , the second conductive connection(s)  43  may be sequentially connected to the second to fifth semiconductor chips  11  to  14 , and one end of the second conductive connection(s)  43  may be in contact with the second electrode finger(s)  33 . The second conductive connection(s)  43  may be a bonding wire(s). 
         [0089]    Referring to  FIG. 18 , a second chip stack  20  may be mounted on the first chip stack  10 . The first chip stack  10  and the second chip stack  20  may provide a chip stack  9 . The second chip stack  20  may include sixth to ninth semiconductor chips  21 ,  22 ,  23  and  24 . The sixth to ninth semiconductor chips  21  to  24  may be stacked in a second cascade structure. The sixth to ninth semiconductor chips  21  to  24  may be aligned in a direction that is different than a direction of alignment of the second to fifth semiconductor chips  11  to  14 . That is, the sixth to ninth semiconductor chips  21  to  24  may be sequentially offset-aligned in an opposite direction relative to an offset-alignment direction of the second to fifth semiconductor chips  11  to  14 . 
         [0090]    For example, the sixth semiconductor chip  21  may be bonded onto the fifth semiconductor chip  14  using a fifth adhesion layer  56  of a third thickness T 3 . The third thickness T 3  may be larger than the second thickness T 2 . The third thickness T 3  may be substantially the same as the first thickness T 1 . The sixth semiconductor chip  21  may be vertically aligned on the fifth semiconductor chip  14 . Respective side surfaces of the sixth semiconductor chip  21  and the fifth semiconductor chip  14  may be aligned on the same vertical line(s). The fifth adhesion layer  56  may be the same material layer as the third adhesion layer  54 . The second conductive connection(s)  43  may penetrate the inside of the fifth adhesion layer  56 . When the second conductive connection(s)  43  is a bonding wire(s), a part of the bonding wire(s) may partially penetrate or pass through the fifth adhesion layer  56 . 
         [0091]    The seventh to ninth semiconductor chips  22  to  24  may be bonded onto the sixth semiconductor chip  21  using a sixth adhesion layer(s)  57 . The seventh to ninth semiconductor chips  22  to  24  may be sequentially offset-aligned on the sixth semiconductor chip  21  in the direction of the second electrode finger(s)  33 . The sixth adhesion layer(s)  57  may be the same material layer having substantially the same thickness as the fourth adhesion layer(s)  55 . The fifth adhesion layer  56  and the sixth adhesion layer(s)  57  may be the same material layer as the third adhesion layer  54 . 
         [0092]    A third conductive connection(s)  45  may be formed between the second chip stack  20  and the third electrode finger(s)  35 . The sixth semiconductor chip  21  may be connected to the third electrode finger(s)  35 , and the sixth to ninth semiconductor chips  21  to  24  may be connected to each other by the third conductive connection(s)  45 . As illustrated in the drawing, the third conductive connection(s)  45  may be sequentially in contact with the sixth to ninth semiconductor chips  21  to  24 , and one end of the third conductive connection(s)  45  may be in contact with the third electrode finger(s)  35 . 
         [0093]    Referring to  FIG. 19 , an encapsulant  59  covering the entire surface of the substrate  3  may be formed. External terminals  5  may be formed on a back side surface of the substrate  3 . The encapsulant  59  may include a molding compound. The external terminals  5  may include solder balls, solder bumps, pin grid arrays, lead grid arrays, conductive tabs, and/or a combination thereof. In other embodiments, the external terminals  5  may be omitted. 
         [0094]    Then, the encapsulant  59  and the substrate  3  may be cut using a sawing process. As a result, a semiconductor package similar to that described with reference to  FIG. 1  may be formed. 
       Fourth Embodiments  
       [0095]      FIG. 20  is a layout diagram of a card package according to fourth embodiments of inventive concepts, and  FIG. 21  is a cross-sectional view of a card package according to the fourth embodiments of inventive concepts. 
         [0096]    Referring to  FIGS. 20 and 21 , a first semiconductor chip  7  and a supporting plate  50  may be mounted on a card substrate  113 . The first semiconductor chip  7  and the supporting plate  50  may be mounted on a same level. A chip stack  9  may be mounted on the first semiconductor chip  7  and the supporting plate  50 . An encapsulant  159  may be provided on the card substrate  113  covering the first semiconductor chip  7 , the supporting plate  50  and the chip stack  9 . 
         [0097]    The card substrate  113  may be covered with a lower solder resist  112  and an upper solder resist  114 . A first electrode finger(s)  31 , a second electrode finger(s)  33 , and a third electrode finger(s)  35  may be formed on the card substrate  113 . A first adhesion layer  51  may be interposed between the card substrate  113  and the supporting plate  50 . A second adhesion layer  53  may be interposed between the card substrate  113  and the first semiconductor chip  7 . A first conductive connection(s)  41  may be formed between the first semiconductor chip  7  and the first electrode finger(s)  31 . 
         [0098]    The chip stack  9  may include a first chip stack  10  and a second chip stack  20  on the first chip stack  10 . The first chip stack  10  may include second to fifth semiconductor chips  11 ,  12 ,  13 , and  14 , and the second chip stack  20  may include sixth to ninth semiconductor chips  21 ,  22 ,  23 , and  24 . The second semiconductor chip  11  may be bonded onto the supporting plate  50  and the first semiconductor chip  7  using a third adhesion layer  54 . The third to fifth semiconductor chips  12  to  14  may be sequentially stacked on the second semiconductor chip  11  using a fourth adhesion layer(s)  55 . The third adhesion layer  54  may be thicker than the fourth adhesion layer(s)  55 . The first conductive connection(s)  41  may penetrate or pass through the third adhesion layer  54 . The third adhesion layer  54  may be in contact with the second semiconductor chip  11 , the first semiconductor chip  7  and the supporting plate  50 . 
         [0099]    A second conductive connection(s)  43  may be formed between the first chip stack  10  and the second electrode finger(s)  33 . The second conductive connection(s)  43  may be separated from the fourth adhesion layer(s)  55 . The sixth semiconductor chip  21  may be bonded onto the fifth semiconductor chip  14  using a fifth adhesion layer  56 . The sixth semiconductor chip  21  may be vertically aligned with the fifth semiconductor chip  14 . The second conductive connection(s)  43  may penetrate or pass through the fifth adhesion layer  56 . The seventh to ninth semiconductor chips  22  to  24  may be bonded onto the sixth semiconductor chip  21  using a sixth adhesion layer(s)  57 . A third conductive connection(s)  45  may be formed between the second chip stack  20  and the third electrode finger(s)  35 . 
         [0100]    External terminals  125  may be formed on one side of the card substrate  113 . The first electrode finger(s)  31 , the second electrode finger(s)  33 , and the third electrode finger(s)  35  may be electrically connected to the external terminals  125 . Each of the external terminals  125  may include a conductive tab. 
         [0101]    As previously described, the structure of the supporting plate  50 , the first semiconductor chip  7  and third adhesion layer  54  may significantly improve the structural stability of the second to ninth semiconductor chips  11 ,  12 ,  13 ,  14 ,  21 ,  22 ,  23  and  24  relative to the related art. Accordingly, the card package of  FIGS. 20 and 21  may reduce a signal transmission path with a plurality of semiconductor chips mounted thereon. Moreover, the chip package of  FIGS. 20 and 21  may be relatively light, thin, short and compact. 
         [0102]    Furthermore, semiconductor packages described with reference to  FIGS. 1 to 19  and the methods of forming the same may be variously applied to a card package and methods of forming the same. 
       Fifth Embodiments  
       [0103]      FIGS. 22 and 23  are respectively a perspective view and a system block diagram of an electronic device according to fifth embodiments of inventive concepts. 
         [0104]    Referring to  FIG. 22 , the semiconductor package and the method of forming the same described with reference to  FIGS. 1 to 21  may be usefully applied to electronic systems such as a cellular phone  1900 , a netbook, a notebook, and/or a tablet PC. For example, a semiconductor package similar to that described with reference to  FIGS. 1 to 21  may be mounted on a main board in the cellular phone  1900 . Further, a semiconductor package similar to that described with reference to  FIGS. 1 to 21  may be provided as a memory expansion device such as an external memory card and combined with the cellular phone  1900 . 
         [0105]    Referring to  FIG. 23 , a semiconductor package similar to that described with reference to  FIGS. 1 to 21  may be applied to an electronic system  2100 . The electronic system  2100  may include a body  2110 , a microprocessor unit  2120 , a power unit  2130 , a function unit  2140 , and a display controller unit  2150 . The body  2110  may be a mother board formed of a printed circuit board (PCB). The microprocessor unit  2120 , the power unit  2130 , the function unit  2140 , and the display controller unit  2150  may be mounted on the body  2110 . A display unit  2160  may be disposed in or on the body  2110 . For example, the display unit  2160  may be disposed on the surface of the body  2110  to display an image processed by the display controller unit  2150 . 
         [0106]    The power unit  2130  may be supplied with a predetermined voltage from an external and/or internal battery (not shown), and the power unit  2130  may divide the received voltage into a required voltage level to supply the divided voltage to the microprocessor unit  2120 , the function unit  2140 , the display controller unit  2150 , etc. The microprocessor unit  2120  may receive a voltage from the power unit  2130  and may control the function unit  2140  and the display unit  2160 . The function unit  2140  may perform various functions of the electronic system  2100 . 
         [0107]    For example, when the electronic system  2100  is a cellular phone, the function unit  2140  may include components capable of performing cellular phone functions (including outputting an image to the display unit  2160 , outputting voice to a speaker, etc.), by dialing or communication with an external apparatus  2170 . When a camera is mounted, the system may function as a camera image processor. 
         [0108]    In an applied example embodiment, when the electronic system  2100  is connected to a memory card to provide capacity expansion, the function unit  2140  may be a memory card controller. The function unit  2140  may transmit or receive a signal to or from the external apparatus  2170  via a wired or wireless communication unit  2180 . When the electronic system  2100  uses a universal serial bus (USB) to provide function expansion, the function unit  2140  may function as an interface controller. Moreover, the function unit  2140  may include a mass storage device. 
         [0109]    A semiconductor package similar to that described with reference to  FIGS. 1 to 21  may be applied to the function unit  2140 . For example, the function unit  2140  may include the substrate  3 , the external terminals  5 , the supporting plate  50 , the chip stack  9 , and the third adhesion layer  54 . The external terminals  5  may be connected to the body  2110 . In this case, the electronic system  2100  may exhibit characteristics of being relatively light, thin, short and compact in spite of a plurality of semiconductor chips mounted therein, and a reduced signal transmission path may increase operation speeds. 
         [0110]    According to embodiments of inventive concepts, a semiconductor package in which a first semiconductor chip, a supporting plate, a adhesion layer and second to ninth semiconductor chips are mounted on a substrate can be provided. Accordingly, a semiconductor package that is structurally stable may reduce signal transmission paths, and may have a plurality of semiconductor chips mounted thereon. The package may be relatively light, thin, short and small. 
         [0111]    The foregoing is illustrative of embodiments and is not to be construed as limiting thereof. Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in embodiments without materially departing from the novel teachings and advantages. Accordingly, all such modifications are intended to be included within the scope of inventive concepts as defined in the claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function, and not only structural equivalents but also equivalent structures. Therefore, it is to be understood that the foregoing is illustrative of various embodiments and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims.