Abstract:
The present invention relates to a forward converter with self-driven synchronous rectifiers, which utilizes a secondary driving winding and a secondary driving circuit to drive the synchronous rectifiers in the secondary power loop. The secondary driving circuit, which is composed of a level shifter and a signal distributor, can shift the voltage waveform across the secondary driving winding by a predetermined level and distribute proper driving signals to the synchronous rectifiers to reduce the rectifier conduction loss. Specially, the channel of the freewheeling synchronous rectifier still can be turned on during the dead interval to further reduce the body diode conduction loss.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit under 35 U.S.C. 119(a)-(d), of Taiwan Application No. 96135431, filed Sep. 21, 2007, which is incorporated herein by reference in its entirety. 
     BACKGROUND OF THE INVENTION 
     1. Field of Invention 
     The present invention relates to a forward converter with self-driven synchronous rectifiers. 
     2. Related Art 
     A forward converter can be used to convert a high DC voltage source into multiple low DC voltage sources, where the master output is regulated by a closed-loop pulse width modulation (PWM) controller and slave outputs are regulated by secondary side post regulators (SSPR). 
       FIG. 1  is a block diagram illustrating the master output with synchronous rectifiers. The secondary power loop comprises a secondary power winding T s , a forward synchronous rectifier M f , a freewheeling synchronous rectifier M w , a power inductor L 1  and a filter capacitor C 1 . The closed-loop PWM controller comprises three blocks: (1) an error-amplifier circuit  1  samples the output voltage V 1  through a voltage divider and compares the output voltage sample with a reference voltage to generate an amplified error signal (voltage or current); (2) a control circuit  2  converts the amplified error signal into a PWM signal and (3) a drive circuit  3  converts the PWM signal into drive signals of M f  and M w . 
     The block diagrams of slave outputs with diode rectifiers are shown in  FIG. 2   a  and  FIG. 2   b . The secondary power loop comprises a secondary power winding T s2 , a secondary side post regulator (SSPR) S 1 , a forward diode rectifier D f , a freewheeling diode rectifier D w , a power inductor L 2  and a filter capacitor C 2 . S 1  can be placed at either the high-side ( FIG. 2   a ) or the low-side ( FIG. 2   b ). D f  can be placed at either the high-side or the low-side, depending on the materialization of S 1 . S 1  can be implemented with either a magnetic amplifier (MA) or a controlled switch (CS). If S 1  is implemented with a MA, D f  must be placed at the high-side and the switch controller  4  is a reset circuit. If S 1  is implemented with a CS, D f  can be placed at either the high-side or the low-side and the switch controller  4  is a drive circuit. S 1  blanks the leading edge of the voltage waveform across T s2  so that the average value of the voltage waveform across D w  equals the output voltage V 2 . The blanking effect of S 1  is illustrated with  FIG. 3 , where V L1  is the voltage across L 1  in  FIG. 1  and V L2  is the voltage across L 2  in either  FIG. 2   a  or  FIG. 2   b.    
     During the on-interval 0≦t≦T on , the voltage across T s  is positive with respect to its reference polarity; M f  is turned on but M w  is turned off; V L1  is positive with respect to its reference polarity; L 1  stores electric energy through T s , M f  and C 1 . During the blanking-interval 0≦t≦T blank , the voltage across T s2  is positive with respect to its reference polarity; S 1  is turned off; the voltage waveform across T s2  is blanked by S 1 ; no current flows through D f ; the continuous current of L 2  forces D w  to conduct; V L2  is negative with respect to its reference polarity; L 2  releases electric energy through D w  and C 2 . During the non-blanking interval T blank ≦t≦T on , the voltage across T s2  is positive with respect to its reference polarity; S 1  is turned on; the voltage waveform across T s2  is not blanked by S 1 ; the continuous current of L 2  commutates from D w  to D f ; V L2  is positive with respect to its reference polarity; L 2  stores electric energy through D f , T s2 , S 1  and C 2 . 
     During the reset-interval T on ≦t≦T on +T reset , the voltage across T s  is negative with respect to its reference polarity; M f  is turned off but M w  is turned on; V L1  is negative with respect to its reference polarity; L 1  releases electric energy through M w  and C 1 ; the voltage across T s2  is negative with respect to its reference polarity; S 1  is turned off; the continuous current of L 2  commutates D f  from to D w ; V L2  is negative with respect to its reference polarity; L 2  releases electric energy through D w  and C 2 . 
     During the dead-interval T on +T reset ≦t≦T s , the voltage across T s  is 0; M f  is turned off but M w  is still turned on; V L1  is negative with respect to its reference polarity; L 1  releases electric energy through M w  and C 1 ; the voltage across T s2  is 0; S 1  is turned off; D f  is turned off but D w  is turned on; V L2  is negative with respect to its reference polarity; L 2  releases electric energy through D w  and C 2 . 
     If the drive circuit  3  in  FIG. 1  is based on an integrated circuit (IC), M f  and M w  are referred to as IC-driven synchronous rectifiers. If it is based on a secondary driving winding, M f  and M w  are referred to as self-driven synchronous rectifiers. In general, a drive circuit based on an IC is more complicated and expensive than a drive circuit based on a secondary driving winding. As for slave outputs, D f  and D w  in either  FIG. 2   a  or  FIG. 2   b  suffer from higher rectifier conduction loss. Therefore, the present invention discloses a cost-effective approach to drive the self-driven synchronous rectifiers in the master output and slave outputs simultaneously. 
     SUMMARY OF THE INVENTION 
     For enhancing efficiency with low cost, the present invention is directed to a multiple-output forward converter with self-driven synchronous rectifiers. 
     In the master output, the drive circuit comprises a secondary driving winding, a level shifter (optional) and a signal distributor. The secondary driving winding induces a bipolar driving voltage from the forward transformer. The level shifter shifts the bipolar driving voltage by a predetermined level to a shifted bipolar driving voltage. The signal distributor distributes the (shifted) bipolar driving voltage to the gates of the forward and freewheeling synchronous rectifiers. 
     In slave outputs, the forward synchronous rectifier can be placed at either the high-side or the low-side. If the forward synchronous rectifier is placed at the high-side, it is self-driven by an additional secondary driving winding. If the forward synchronous rectifier is placed at the low-side, it can be self-driven by either an additional secondary driving winding or the driving voltage of the master forward synchronous rectifier. The freewheeling synchronous rectifier is self-driven by the driving voltage of the master freewheeling synchronous rectifier. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram illustrating the circuit of the master output of a conventional multiple-output forward converter with synchronous rectifiers. 
         FIG. 2   a  and  FIG. 2   b  are two block diagrams illustrating the alternative circuits of slave outputs of conventional multiple-output forward converters with diode rectifiers, wherein the SSPRs are placed at high-side and low-side respectively. 
         FIG. 3  is a time sequence diagram illustrating voltage waveforms across the power inductors of the master output and slave outputs of a conventional multiple-output forward converter. 
         FIG. 4  is a block diagram illustrating the schematic circuit of the master output of a multiple-output forward converter according to the present invention. 
         FIG. 5  is a diagram illustrating the practical circuit of the master output of a multiple-output forward converter according to the present invention. 
         FIG. 6  is a time sequence diagram illustrating voltage waveforms of the secondary drive winding, the gate of the forward synchronous rectifier and the gate of the freewheeling synchronous rectifier of the master output shown in  FIG. 5  within one switching period. 
         FIG. 7  is a block diagram illustrating the schematic circuit of the master output of a multiple-output forward converter with a level shifter according to the present invention. 
         FIG. 8  is a diagram illustrating the practical circuit of the master output of a multiple-output forward converter with a level shifter according to the present invention. 
         FIG. 9  is a time sequence diagram illustrating voltage waveforms of the secondary drive winding, the gate of the forward synchronous rectifier and the gate of the freewheeling synchronous rectifier of the master output shown in  FIG. 8  within one switching period. 
         FIG. 10   a  and  FIG. 10   b  are two block diagrams illustrating the alternative circuits of the slave outputs of multiple-output forward converters with additional driving circuits according to the present invention, wherein the SSPRs are placed at high-side and low-side respectively. 
         FIG. 11   a ,  FIG. 12   a  and  FIG. 13   a  are diagrams illustrating three alternative practical circuits of slave outputs of multiple-output forward converters with high-side SSPR according to the present invention shown in  FIG. 10   a.    
         FIG. 11   b ,  FIG. 12   b  and  FIG. 13   b  are diagrams illustrating three alternative practical circuits of slave outputs of multiple-output forward converters with low-side SSPR according to the present invention shown in  FIG. 10   b.    
         FIG. 14  is a time sequence diagram illustrating voltage waveforms of the secondary drive winding, the gate of the forward synchronous rectifier and the gate of the freewheeling synchronous rectifier of the slave outputs of multiple-output forward converters without a level shifter within one switching period according to the present invention. 
         FIG. 15  is a time sequence diagram illustrating voltage waveforms of the secondary drive winding, the gate of the forward synchronous rectifier and the gate of the freewheeling synchronous rectifier of the slave outputs of multiple-output forward converters with a level shifter within one switching period according to the present invention. 
         FIG. 16  is a diagram illustrating a practical circuit of the slave output of a multiple-output forward converter according to the present invention, wherein the SSPR is a controlled switch placed at low-side, and the drive voltages of the slave forward and freewheeling rectifiers come from those of the master forward and freewheeling rectifiers respectively. 
         FIG. 17   a  and  FIG. 17   b  are time sequence diagrams illustrating the gate voltage waveforms of the slave forward and freewheeling synchronous rectifiers of multiple-output forward converters without and with a level shifter respectively according to the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 4  is a block diagram illustrating a schematic circuit of the master output of a multiple-output forward converter according to the present invention. The forward transformer includes a primary power winding T 1 , a secondary power winding T 2  and a secondary driving winding T 3 . The two terminals of the primary winding T 1  are connected in series to an input voltage V i  through one or two primary switches (not shown). 
     The secondary power winding T 2 , connecting a master power loop  21 , includes a voltage output terminal (high voltage terminal) and a ground terminal (low voltage terminal) to provide a voltage V 1  for driving an external load circuit (not shown). A filter capacitor C 3  is connected between the voltage output terminal and the ground terminal. A power inductor L 3  is connected between the first terminal (marked with a dot) of the secondary power winding T 2  and the voltage output terminal. The dots of the primary and the secondary windings mean the same electric polarity. 
     The master power loop  21  includes a forward synchronous rectifier  211 , a freewheeling synchronous rectifier  212  and a power inductor L 3 . Each of the two synchronous rectifiers  211  and  212  includes a first terminal, a second terminal and a control terminal, where the control terminal receives a voltage signal to control the turn-on or turn-off of the channel between the first terminal and the second terminal. As shown in the figure, the first terminals of the two synchronous rectifiers  211  and  212  are respectively connected to the two terminals of the secondary power winding T 2 ; both of the second terminals of the two synchronous rectifiers  211  and  212  are connected to the common ground terminal Z M . 
     Next, a signal distributor  22  comprises a first output terminal, a second output terminal and a common connection terminal. The first output terminal and the second output terminal are respectively connected to the two terminals of the secondary driving winding T 3  as well as the control terminals of the two synchronous rectifiers  211  and  212 . The common connection terminal is connected to the common ground terminal Z M . 
     When the voltage across T 3  is positive with respect to its reference polarity, the first output terminal of the signal distributor  22  is connected with the common connection terminal; a positive voltage signal is distributed to the control terminal of the forward synchronous rectifier  211 ; the channel of the forward synchronous rectifier  211  is turned on. When the voltage across T 3  is negative with respect to its reference polarity, the second output terminal of the signal distributor  22  is connected with the common connection terminal; a positive voltage signal is distributed to the control terminal of the freewheeling synchronous rectifier  212 ; the channel of the freewheeling synchronous rectifier  212  is turned on. 
       FIG. 5  illustrates a practical circuit of the master output according to the embodiment in  FIG. 4 . As shown in the figure, two nMOSFET transistors M 1  and M 2  are respectively used as the forward synchronous rectifier  211  and the freewheeling synchronous rectifier  212  and referred to as a forward transistor M 1  and a freewheeling transistor M 2  respectively. In this example, gates, drains and sources of M 1  and M 2  respectively serve as the control terminals, the first terminals and the second terminals. 
     The signal distributor  22  includes two diodes D 1  and D 2 . The anodes of D 1  and D 2  are connected to each other and the common ground terminal Z M . The cathodes of D 1  and D 2  respectively serve as the first output terminal and the second output terminal and are connected to the gates of M 2  and M 1 . 
       FIG. 6  illustrates voltage waveforms of the secondary drive winding, the gate of the forward synchronous rectifier and the gate of the freewheeling synchronous rectifier within one switching period in the master output according to the embodiment in  FIG. 5 . 
     During the on-interval 0≦t≦T on , the voltage across T 3  is V s ; D 1  is turned on by a forward bias but D 2  is turned off by a reverse bias; the signal distributor  22  distributes a positive voltage V s  and a zero voltage 0 to the gates of M 1  and M 2 , respectively; L 3  stores electric energy through T 2 , M 1  and C 3 . 
     During the reset-interval T on ≦t≦T on +T reset , the voltage across T 3  is −V s ; D 2  is turned on by a forward bias but D 1  is turned off by a reverse bias; the signal distributor  22  distributes a positive voltage V s  and a zero voltage 0 to the gates of M 2  and M 1 , respectively; L 3  releases electric energy through M 2  and C 3 . 
     During the dead-interval T on +T reset ≦t≦T s , the voltage across T 3  is 0; both D 1  and D 2  are turned off; both M 1  and M 2  are turned off; the continuous current of L 3  forces the body diode of M 2  to conduct; L 3  release electric energy through the body diode of M 2  and C 3 . 
     It should be noted that the continuous current of L 3  flows through the body diode of M 2  during the dead-interval. This body diode conduction loss can be further reduced by introducing an additional level shifter  23  to the intermediate between the secondary driving winding T 3  and the signal distributor  22 , as shown in  FIG. 7 . 
     As shown in the figure, the level shifter  23  includes a first input terminal, a second input terminal, a first output terminal and a second output terminal. The first input terminal and the second input terminal of the level shifter  23  are respectively connected to both terminals of T 3 . The first output terminal and the second output terminal of the level shifter  23  are respectively connected to the first output terminal and the second output terminal of the signal distributor  22 . In the level shifter  23 , the second output terminal is identical to the second input terminal. 
       FIG. 8  illustrates a preferred circuit of the master output according to the embodiment in  FIG. 7 . As shown in the figure, the level shifter  23  comprises a second capacitor C 4 , a diode D 4  and a Zener diode ZD 4 . One terminal of C 4  serves as the first input terminal and the other terminal of C 4  serves as the first output terminal, which is also connected with the anode of D 4 . The anode of ZD 4  serves as the second input terminal as well as the second output terminal. The cathode of D 4  is connected with the cathode of ZD 4 . 
       FIG. 9  illustrates voltage waveforms of the secondary drive winding, the gate of the forward synchronous rectifier and the gate of the freewheeling synchronous rectifier within one switching period in the master output according to the embodiment in  FIG. 8 . The dashed line marks the output voltage waveform of the level shifter. 
     For simplicity, assume the capacitance of C 4  is large enough to maintain a nearly constant DC voltage across its two terminals within one switching period; the forward voltage drop of all diodes is V f =0; the breakdown voltage of ZD 4  is V z ; the voltage level shifted by the level shifter  23  is V r =V s −V z . 
     During the on-interval 0≦t≦T on , the voltage across T 3  is V s ; D 4  is turned on by a forward bias; ZD 4  breaks down; C 4  is recharged to a voltage V r ; D 1  is turned on by a forward bias but D 2  is turned off by a reverse bias; the signal distributor  22  distributes a positive voltage V z  and a zero voltage to the gates of M 1  and M 2 , respectively; L 3  stores electric energy through T 2 , M 1  and C 3 . 
     During the reset-interval T on ≦t≦T on +T reset , the voltage across T 3  is −V s ; both D 4  and ZD 4  are turned off; D 2  is turned on by a forward bias but D 1  is turned off by a reverse bias; the signal distributor  22  distributes a positive voltage 2V s −V z  and a zero voltage to the gates of M 2  and M 1 , respectively; L 3  releases electric energy through M 2  and C 3 . 
     During the dead-interval T on +T reset ≦t≦T s , the voltage across T 3  is 0; both D 4  and ZD 4  are turned off; D 2  is turned on by a forward bias but D 1  is turned off by a reverse bias; the signal distributor  22  distributes a positive voltage V s −V z  and a zero voltage to the gates of M 2  and M 1 , respectively; L 3  releases electric energy through M 2  and C 3 . 
     Table 1 lists the comparison between  FIG. 6  and  FIG. 9 : 
     
       
         
               
               
               
               
             
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
             
             
               
                   
                   
               
               
                   
                 on-interval 
                 reset-interval 
                 dead-interval 
               
             
          
           
               
                   
                 without level 
                 with level 
                 without level 
                   
                 without level 
                 with level 
               
               
                   
                 shifter 
                 shifter 
                 shifter 
                 with level shifter 
                 shifter 
                 shifter 
               
               
                   
                   
               
             
          
           
               
                 M 1   
                 V s   
                 V z   
                 0 
                 0 
                 0 
                 0 
               
               
                 M 2   
                 0 
                 0 
                 V s   
                 2V s  − V z   
                 0 
                 V s  − V z   
               
               
                   
               
             
          
         
       
     
     It can be clearly seen from Table 1 that the gate voltage of M 2  during the dead-interval in  FIG. 9  is V s −V z ; the continuous current of L 3  flows through the channel of M 2 . Therefore, the body diode conduction loss during the dead-interval in  FIG. 5  can be reduced by introducing an additional level shifter  23  to the intermediate between the secondary driving winding T 3  and the signal distributor  22  in  FIG. 8 . 
       FIG. 10   a  and  FIG. 10   b  illustrate two alternative schematic circuits of slave outputs of multiple-output forward converter with self-driven synchronous rectifiers according to an embodiment of the present invention, wherein the SSPRs S 2  can be placed at high-side or low-side, and the SSPR S 2  can be implemented with either a magnetic amplifier (MA) driven by a reset circuit or a controlled switch (CS) driven by an integrated circuit (IC) driver. If S 2  is implemented with a MA, the forward synchronous rectifier  311  is emphatically placed at the high-side and self-driven by an additional drive circuit  32  based on an additional secondary driving winding T 13 , and the switch controller  33  is a reset circuit. If S 2  is implemented with a CS, the forward synchronous rectifier  311  can be placed at the low-side or high-side and self-driven by the additional drive circuit  32 , and the switch controller  33  is an IC driver. Moreover, the slave forward synchronous rectifier  311  can be driven by the driving voltage of the master forward synchronous rectifier shown as  FIG. 16 . 
     The slave power loop includes a forward rectifier  311 , a freewheeling rectifier  312 , a power inductor L 5 , a SSPR S 2  and a slave filter capacitor C 5 . In the situation of high-side slave forward rectifier  311 , the slave forward rectifier  311 , the slave freewheeling rectifier  312  and the power inductor L 5  are connected at the common point Z s . The other terminal of the power inductor L 5  connected to an auxiliary voltage output terminal. The slave filter capacitor C 5  is connected between the auxiliary voltage output terminal and the ground terminal of the slave power loop for providing a slave output voltage V 2 . In the other situation (not shown) of low-side slave forward rectifier  311 , the slave forward rectifier  311  and the slave freewheeling rectifier  312  is connected at the common ground terminal, same as the common ground terminal Z m  of the master power loop. 
     If the forward rectifier  311  is driven by an additional drive circuit  32 , an additional secondary driving winding T 13  is used to drive the additional drive circuit  32 . 
       FIG. 11   a ,  FIG. 12   a  and  FIG. 13   a  are three alternative circuit diagrams of slave outputs according to the example of high-side SSPR S 2  shown in  FIG. 10   a , while  FIG. 11   b ,  FIG. 12   b  and  FIG. 13   b  are three alternative circuit diagrams of slave outputs according to the example of low-side SSPR S 2  shown  FIG. 10   b . The slave forward rectifier  311  and the slave freewheeling rectifier is implemented, but not limited, by nMOSFET transistors, noted a synchronous forward transistor M 7  and a synchronous freewheeling transistor M 8 . The drains, sources and gates of the forward transistor M 7  and the freewheeling transistor M 8  serve as the first terminals, second terminals and the control terminals of the slave forward rectifiers  311  and the freewheeling rectifiers  312  respectively, and the drains are connected at the common point Z s . 
     The examples respectively shown in  FIG. 11   a ,  FIG. 11   b ,  FIG. 12   a  and  FIG. 12   b  are unipolar driving mode, which means the driving voltage is always the same (direct). The examples respectively shown in  FIG. 13   a  and  FIG. 13   b  are bipolar driving mode, which means the driving voltage is alternative. 
     In the examples shown in  FIG. 11   a  and  FIG. 11   b , the drive circuit  32  includes a diode D 7  and an interlocked switch circuit. The interlocked switch circuit includes an NPN bipolar transistor Q 1 , a PNP bipolar transistor Q 2 , and two resistors R 1  and R 2 . Emitters of the transistors Q 1  and Q 2  are connected at a connection point, and the connection point is connected to the gate of the forward transistor M 7 . Bases of the two transistors Q 1  and Q 2  are connected at another point and the point is connected to the collectors of the transistors Q 1  and Q 2  through the resistors R 1  and R 2 , respectively. The collectors of the transistors Q 1  and Q 2  are connected to a cathode of the diode D 7  and the second terminal of the secondary driving winding T 13  respectively, and then the anode of the diode D 7  is connected to the first terminal of the secondary driving winding T 13 . 
     In the examples shown in  FIG. 12   a  and  FIG. 12   b , the drive circuit  32  includes two resistors R 3 , R 4  and an interlocked switch circuit. The interlocked switch circuit includes a diode D s  and a PNP bipolar transistor Q 3 , wherein the anode and the cathode of the diode D s  are connected to the base and emitter of Q 3 . The base of Q 3  is connected to the dotted terminal (first terminal) of the slave secondary driving winding T 13 . The collector and the emitter of Q 3  are connected to the second terminal of the slave secondary driving winding T 13  and the gate of the slave forward transistor M 7 . The resistor R 4  is connected between the collector and the emitter of the Q 3 . 
     Table 2 lists the polarities of the voltage across T 13  and the gate voltage of M 7  within one switching period according to the embodiments in  FIG. 11   a ,  FIG. 11   b ,  FIG. 12   a  and  FIG. 12   b : 
     
       
         
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
             
           
               
                   
                 TABLE 2 
               
             
             
               
                   
                   
               
               
                   
                 on-interval 
                   
                 reset-interval 
                   
                 dead-interval 
                   
               
             
          
           
               
                   
                 T 13   
                 M 7   
                 T 13   
                 M 7   
                 T 13   
                 M 7   
               
               
                   
                   
               
               
                   
                 + 
                 + 
                 − 
                 0 
                 0 
                 0 
               
               
                   
                   
               
             
          
         
       
     
     It can be seen from Table 2 that the gate voltage of M 7  is unipolar. 
     In the examples shown in  FIG. 13   a  and  FIG. 13   b , the drive circuit  32  merely includes two resistors R 1  and R 2  connected with each other, which are respectively connected to the first terminal and the second terminal of the secondary driving winding T 13 . The connection point of the resistors R 1  and R 2  is connected to the gate of the forward transistor M 7 , and the resistor R 2  is connected between the gate and the source of the forward transistor M 7 . 
     Table 3 lists the polarities of the voltage across T 13  and the gate voltage of M 7  within one switching period according to the embodiments in  FIG. 13   a  and  FIG. 13   b : 
     
       
         
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
             
           
               
                   
                 TABLE 3 
               
             
             
               
                   
                   
               
               
                   
                 on-interval 
                   
                 reset-interval 
                   
                 dead-interval 
                   
               
             
          
           
               
                   
                 T 13   
                 M 7   
                 T 13   
                 M 7   
                 T 13   
                 M 7   
               
               
                   
                   
               
               
                   
                 + 
                 + 
                 − 
                 − 
                 0 
                 0 
               
               
                   
                   
               
             
          
         
       
     
     It can be seen from Table 3 that the gate voltage of M 7  is bipolar. 
       FIG. 14  illustrates the time sequence of the voltage waveforms of the secondary drive winding T 13 , the gate of the synchronous forward transistor M 7  and the gate of the synchronous freewheeling transistor M 8  of the slave outputs of the examples shown in  FIG. 11   a ,  FIG. 11   b ,  FIG. 12   a  and  FIG. 12   b  accompanying with the master output of the example shown in  FIG. 5  within one switching period. 
     During the on-interval 0≦t≦T on , the voltage across T 13  is V s2 ; M 7  is turned on by a positive driving voltage V s2  but M 8  is turned off by a zero driving voltage. During the blanking-interval 0≦t≦T blank , the voltage across T 14  is positive with respect to its reference polarity; S 2  is turned off; the voltage waveform across T 14  is blanked by S 2 ; no current flows through the channel or body diode of M 7 ; the continuous current of L 5  forces the body diode of M 8  to conduct; L 5  releases electric energy through the body diode of M 8  and C 5 . During the non-blanking interval T blank ≦t≦T on , the voltage across T 14  is negative with respect to its reference polarity; S 2  is turned on; the voltage waveform across T 14  is not blanked by S 2 ; the continuous current of L 5  commutates from the body diode of M 8  to M 7 ; L 5  stores electric energy through M 7 , S 2 , T 14  and C 5 . 
     During the reset-interval T on ≦t≦T on +T reset , the voltage across T 13  is −V s2 ; M 7  is turned off by a zero driving voltage but M 8  is turned on by a positive driving voltage V s ; L 5  releases electric energy through M 8  and C 5 . 
     During the dead-interval T on +T reset ≦t≦T s , the voltage across T 13  is 0; both M 7  and M 8  are turned off; the continuous current of L 5  forces the body diode of M 8  to conduct; L 5  releases electric energy through the body diode of M 8  and C 5 . 
       FIG. 15  illustrates the time sequence of the voltage waveforms of the secondary drive winding T 13 , the gate of the synchronous forward transistor M 7  and the gate of the synchronous freewheeling transistor M 8  of the slave outputs of the examples shown in  FIG. 11   a ,  FIG. 11   b ,  FIG. 12   a  and  FIG. 12   b  accompanying with the master output of the example shown in  FIG. 8  within one switching period. 
     During the on-interval 0≦t≦T on , the voltage across T 13  is V s2 ; M 7  is turned on by a positive driving voltage V s2  but M 8  is turned off by a zero driving voltage. During the blanking-interval 0≦t≦T blank , L 5  releases electric energy through the body diode of M 8  and C 5 . During the non-blanking interval T blank ≦t≦T on , L 5  stores electric energy through M 7 , S 2 , T 14  and C 5 . 
     During the reset-interval T on ≦t≦T on +T reset , the voltage across T 13  is −V s2 ; M 7  is turned off by a zero driving voltage but M 8  is turned on by a positive driving voltage 2V s −V z ; L 5  releases electric energy through M 8  and C 5 . 
     During the dead-interval T on +T reset ≦t≦T s , the voltage across T 13  is 0; M 7  is turned off but M 8  is turned on by a positive driving voltage V s −V z ; L 5  releases electric energy through M 8  and C 5 . 
       FIG. 16  illustrates a circuit of slave outputs with a low-side SSPR S 2  and a low-side slave synchronous forward transistor M 7 , and the SSPR S 2  is a controlled switch. As shown, the example does not need a slave drive circuit. The slave synchronous forward transistor M 7  and the slave synchronous freewheeling transistor M 8  are driven by the driving voltages of the master synchronous forward transistor and the master synchronous freewheeling transistor. 
       FIG. 17   a  and  FIG. 17   b  illustrate the time sequence of the voltage waveforms of the gate of the slave synchronous forward transistor M 7  and the gate of the slave synchronous freewheeling transistor M 8  of the example shown in  FIG. 16  accompanying with the master output shown in  FIG. 5  and  FIG. 8  respectively within one switching period. During the on-interval 0≦t≦T on , M 7  is turned on by positive driving voltages V s  ( FIG. 17   a ) and V z  ( FIG. 17   b ) but M 8  is turned off by a zero driving voltage. During the reset-interval T on ≦t≦T on +T reset , M 7  is turned off by a zero driving voltage but M 8  is turned on by positive driving voltages V s  ( FIG. 17   a ) and 2V s −V z  ( FIG. 17   b ). During the dead-interval T on +T reset ≦t≦T s , M 7  is turned off but M 8  is turned off in the example shown in  FIG. 17   a , but is still turned on by a positive driving voltage V s −V z  in the example shown in  FIG. 17   b.    
     It should be noted that the forward transistor and the freewheeling transistor may be but not limited to an N-channel metal-oxide semiconductor field-effect transistor (N-channel MOSFET), a P metal-oxide semiconductor field-effect transistor (P-channel MOSFET), an N-channel junction field effect transistor (N-channel JFET) or a P-channel junction field effect transistor (P-channel JFET). 
     While the invention has been described in terms of what are presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.