Abstract:
A thin film transistor structure of a pixel is provided. In the present invention, a first metal layer serves as a gate electrode, and the gate electrode includes an extending gate electrode portion. A second metal layer includes a drain electrode partially and respectively overlapping the gate electrode and the gate electrode portion with the amorphous silicon layer interposed therebetween so as to form a first parasitic capacitor and a second parasitic capacitor. The total capacitance of the first parasitic capacitor and the second parasitic capacitor is invariable to withstand deviation caused by vibration of the machine in the photolithographic process, so that undesired effects in the liquid crystal display panel such as mura and flicker can be reduced.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation of International Application No. PCT/CN2009/072493 filed on Jun. 26, 2009. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a thin film transistor structure, and more particularly, to a thin film transistor structure of a pixel which can be applied to a lower substrate of a liquid crystal display panel. 
         [0004]    2. Description of the Prior Art 
         [0005]    Manufacturing processes of thin film transistor liquid crystal display (TFT LCD) panels include array processes and color filter processes, wherein required electrode substrates, which include voltage-controlled thin film transistors for transmitting signals, are formed in the array processes. Refer to  FIG. 1 , which is a schematic diagram illustrating a thin film transistor in the prior art. As shown in  FIG. 1 , a first metal layer  10  serves as a gate electrode  12 , and an amorphous silicon layer  14  is formed on the first metal layer  10  and partially overlaps the first metal layer  10 . A second metal layer  16  is disposed on the first metal layer  10 , and the second metal layer  16  includes a drain electrode  18 , a source electrode  20  and a data line  22 . The drain electrode  18  is T-shaped and extends to partially overlap the amorphous silicon layer  14 . The source electrode  20  is disposed on the amorphous silicon layer  14 , and the source electrode  20  is U-shaped and corresponds to the drain electrode  18 . Furthermore, the source electrode  20  is connected to the data line  22  which is transversely above the first metal layer  10 . In addition, a pixel electrode layer  24  is disposed on the drain electrode  18  and is electrically connected to the drain electrode  18  through a via hole  26 . 
         [0006]    When a photolithographic process of the array processes is performed, deviation may occur due to slight vibration of an exposure machine in a light exposure process. As shown in  FIG. 2 , the location of the drain electrode  18  shifts downwardly in the longitudinal direction with respect to that in  FIG. 1 . As an area of an overlapping region between the amorphous silicon layer  14  and the drain electrode  18  formed by the second metal layer  16  varies, a parasitic capacitor (Cgd) between the gate electrode  12  and the drain electrode  18  would vary. As a result, feed-through voltage of the pixel electrode which is caused by the parasitic capacitor would accordingly vary due to variance of the parasitic capacitor, and some undesired effects such as mura and flicker may occur in local regions of the liquid crystal display panel. 
         [0007]    Therefore, for the aforementioned problems, a thin film transistor structure is provided in the present invention to withstand deviation caused by vibration of the machine in the photolithographic process. 
       SUMMARY OF THE INVENTION 
       [0008]    It is therefore one of the objectives of the present invention to provide a thin film transistor structure to withstand deviation caused by vibration of the machine in the photolithographic process. Accordingly, the parasitic capacitor (C gd ) between the drain electrode and the gate electrode of the thin film transistor structure can be fixed, so that positive and negative voltages applied on the pixel electrode can be symmetrical and the voltage drop deviation of the direct current (DC) level can be reduced to minimum. 
         [0009]    It is another one of the objectives of the present invention to provide a thin film transistor structure to reduce undesired effects in the liquid crystal display panel such as mura and flicker, so that display quality of the liquid crystal display panel can be improved. 
         [0010]    To achieve the aforementioned objectives, a gate electrode is formed by a first metal layer in the thin film transistor structure of the present invention, and the gate electrode includes a gate electrode portion extending from the gate electrode. An insulating layer is disposed on the first metal layer, and an amorphous silicon layer is disposed on the insulating layer and is respectively disposed above the gate electrode and above the gate electrode portion. A second metal layer is disposed on the amorphous silicon layer, and the second metal layer includes a drain electrode and a source electrode. The source electrode is disposed on the amorphous silicon layer above the gate electrode. The drain electrode partially overlaps the amorphous silicon layer above the gate electrode and above the gate electrode portion respectively. A first parasitic capacitor is formed by a partially overlapping region between the drain electrode and the gate electrode with the amorphous silicon layer interposed therebetween, and a second parasitic capacitor is formed by a partially overlapping region between the drain electrode and the gate electrode portion with the amorphous silicon layer interposed therebetween. A total capacitance of the first parasitic capacitor and the second parasitic capacitor is invariable. 
         [0011]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]      FIG. 1  is a schematic diagram illustrating a thin film transistor structure in the prior art. 
           [0013]      FIG. 2  is a schematic diagram illustrating the occurrence of the deviation in a thin film transistor structure of the prior art. 
           [0014]      FIG. 3A  is a schematic cross-sectional view illustrating the structure of the present invention. 
           [0015]      FIG. 3B  is a schematic cross-sectional view illustrating the structure of the present invention taken along a sectional line A-A′. 
           [0016]      FIG. 4  is a schematic diagram illustrating the structural layout of the first preferred embodiment according to the present invention. 
           [0017]      FIG. 5  is a schematic diagram illustrating the occurrence of the deviation in the first preferred embodiment of the present invention. 
           [0018]      FIG. 6  is a schematic diagram illustrating the structural layout of the second preferred embodiment according to the present invention. 
           [0019]      FIG. 7  is a schematic diagram illustrating the occurrence of the deviation in the second preferred embodiment of the present invention. 
           [0020]      FIG. 8  is a schematic diagram illustrating the structural layout of the third preferred embodiment according to the present invention. 
           [0021]      FIG. 9  is a schematic diagram illustrating the occurrence of the deviation in the third preferred embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0022]    A thin film transistor structure is provided in the present invention. A gate electrode of a first metal layer in the thin film transistor structure includes an extending gate electrode portion. A drain electrode of a second metal layer partially overlaps the gate electrode and the gate electrode portion with an amorphous silicon layer interposed therebetween, so that the parasitic capacitor (C gd ) between the drain electrode and the gate electrode can be fixed when deviation in the photolithographic process occurs. Some preferred embodiments are utilized to illustrate the technical feature of the present invention as follows. 
         [0023]    Please refer to  FIG. 4 , and also refer to the cross-sectional view of the structure shown in  FIG. 3A  and the cross-sectional view of the structure taken along a sectional line A-A′ shown in  FIG. 3B . As shown in  FIG. 4 , a first metal layer  30  serves as a gate electrode  32 , and the gate electrode  32  includes an extending gate electrode portion  34 . The gate electrode portion  34  is L-shaped. An insulating layer  36  is disposed on the first metal layer  30 . An amorphous silicon layer  38  is formed on the insulating layer  36  and is respectively disposed on the gate electrode  32  and on the gate electrode portion  34 . A second metal layer  40  is formed on the amorphous silicon layer  38 , and the second metal layer  40  includes a drain electrode  42  and a source electrode  44 . The source electrode  44  is disposed on the amorphous silicon layer  38  of the gate electrode  32 , and the source electrode  44  is U-shaped with an opening facing up. One end of the drain electrode  42  longitudinally extends to the amorphous silicon layer  38  above the gate electrode  32  and corresponds to the center of the source electrode  44 . The drain electrode  42  partially overlaps the gate electrode  32  with the amorphous silicon layer  38  interposed therebetween to form a first parasitic capacitor (not shown in the figure). The drain electrode  42  further includes a drain electrode portion. The drain electrode portion transversely extends to the amorphous silicon layer  38  above the gate electrode portion  34 . The drain electrode  42  partially overlaps the gate electrode portion  34  with the amorphous silicon layer  38  interposed therebetween to form a second parasitic capacitor (not shown in the figure). The length of a partially overlapping region between the drain electrode  42  and the gate electrode  32  is equal to the length of a partially overlapping region between the drain electrode  42  and the gate electrode portion  34 . In addition, an insulating layer  36  is formed on the second metal layer  40 , and a via hole  48  is formed in the insulating layer  36  and corresponds to the location of the drain electrode  42  of the second metal layer  40 . Subsequently, a pixel electrode layer  46  is formed on the insulating layer  36 , and the pixel electrode layer  46  is electrically connected to the drain electrode  42  of the second metal layer  40  through the via hole  48 . Moreover, a scan line (not shown in the figure) and a data line  50  are respectively connected to the gate electrode  32  of the first metal layer  30  and the source electrode  42  of the second metal layer  40 . 
         [0024]    When deviation occurs due to vibration of the machine in the photolithographic process, as shown in  FIG. 5 , the location of the drain electrode  42  longitudinally shifts upwardly compared to that in  FIG. 4 . An area of a partially overlapping region between the drain electrode  42  and the gate electrode  32  with the amorphous silicon layer  38  interposed therebetween is decreased, and an area of a partially overlapping region between the drain electrode portion and the gate electrode portion  34  with the amorphous silicon layer  38  interposed therebetween is increased at the same time. Accordingly, the capacitance of the first parasitic capacitor decreases, and the capacitance of the second parasitic capacitor increases. The variance of the capacitance of the first parasitic capacitor and the second parasitic capacitor are the same. Due to the compensation, a total capacitance of the first parasitic capacitor and the second parasitic capacitor is invariable without being influenced by the deviation. Therefore, the parasitic capacitor (C gd ) between the drain electrode  42  and the gate electrode  32  can be fixed. 
         [0025]    As described above, in the first preferred embodiment, the drain electrode  42  respectively longitudinally extends above and overlaps the gate electrode  32  and transversely extends above and overlaps the gate electrode portion  34 , and the longitudinal deviation occurs. This embodiment can also withstand the variance of the parasitic capacitor caused by the transverse deviation of the drain electrode. In addition, the shapes and locations of the gate electrode  32 , the gate electrode portion  34 , the drain electrode  42 , and the source electrode  44  can be respectively altered. Refer to  FIG. 6  that is a schematic diagram illustrating the structural layout of the second preferred embodiment according to the present invention. As shown in  FIG. 6 , the gate electrode  32  of the first metal layer  30  includes a left-extended gate electrode portion  34 . One end of the drain electrode  42  transversely extends to the amorphous silicon layer  38  above the gate electrode and corresponds to a U-shaped source electrode  44  with an opening facing right. The drain electrode  42  partially overlaps the gate electrode  32  with the amorphous silicon layer  38  interposed therebetween to form a first parasitic capacitor (not shown in the figure). The other end of the drain electrode  42  includes a drain electrode portion transversely extending to the amorphous silicon layer  38  above the gate electrode portion  34  to form a second parasitic capacitor (not shown in the figure). The length of a partially overlapping region between the drain electrode  42  and the gate electrode  32  is equal to the length of a partially overlapping region between the drain electrode portion and the gate electrode portion  34 . Refer to  FIG. 7 , which is a schematic diagram illustrating the occurrence of the deviation in the second preferred embodiment of the present invention. As shown in  FIG. 7 , the drain electrode  42  transversely shifts toward the left. An area of a partially overlapping region between the drain electrode portion and the gate electrode portion  34  with the amorphous silicon layer  38  interposed therebetween is increased, and an area of a partially overlapping region between the drain electrode  42  and the gate electrode  32  with the amorphous silicon layer  38  interposed therebetween is decreased. Accordingly, the capacitance of the first parasitic capacitor decreases, and the capacitance of the second parasitic capacitor increases. Because the variance of the capacitance of the first parasitic capacitor and the second parasitic capacitor are the same, the total capacitance of the parasitic capacitor (C gd ) is relatively fixed. 
         [0026]    Refer to  FIG. 8 .  FIG. 8  is a schematic diagram illustrating the structural layout of the third preferred embodiment according to the present invention. As shown in  FIG. 8 , the shapes and locations of the gate electrode  32 , the gate electrode portion  34  are the same with that in the second embodiment. One end of the drain electrode  42  extends to the amorphous silicon layer  38  above the gate electrode  32 , and the end terminal is U-shaped with an opening facing down. The drain electrode  42  partially overlaps the gate electrode  32  with the amorphous silicon layer  38  interposed therebetween to form a first parasitic capacitor (not shown in the figure). Another end of the drain electrode  42  partially overlaps the gate electrode portion  34  with the amorphous silicon layer  38  interposed therebetween to form a second parasitic capacitor (not shown in the figure). The length of a partially overlapping region between the drain electrode  42  and the gate electrode  32  is equal to the length of a partially overlapping region between the drain electrode portion and the gate electrode portion  34 . The source electrode  44  is strip-shaped and corresponds to the center of the U-shaped drain electrode  42 . Refer to  FIG. 9  that is a schematic diagram illustrating the occurrence of the deviation in the third preferred embodiment of the present invention. As shown in  FIG. 9 , the drain electrode  42  transversely shifts. An area of a partially overlapping region between the non-U-shaped part of the drain electrode  42  and the gate electrode  32  with the amorphous silicon layer  38  interposed therebetween is decreased, and it can be compensated by an increased area of a partially overlapping region between the drain electrode  42  and the gate electrode portion  34  with the amorphous silicon layer  38  interposed therebetween. Accordingly, the total capacitance of the parasitic capacitor (C gd ) is relatively fixed. 
         [0027]    As illustrated by the aforementioned embodiments, in the present invention, the gate electrode portion  34  of the gate electrode  32  of the first metal layer  30  extends out to serve as the compensation of the gate electrode  32  to withstand the occurrence of deviation in the photolithographic process. Therefore, the parasitic capacitor (C gd ) formed between the gate electrode  32  and the drain electrode  42  of the second metal layer  40  is invariable when deviation occurs in the photolithographic process. 
         [0028]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.