Abstract:
A method includes a) receiving a design for a static random access memory (SRAM) array including an SRAM cell having a read port cell, the read port cell including first and second MOS transistors each having an initial threshold voltage (Vth); b) adjusting one of a gate channel width (Wg) or a gate channel length (Lg) of one of the first and second MOS transistors to modify the Vth of at least one of the first and second MOS transistors; c) simulating a response of the SRAM array, the simulation providing response data for the SRAM array including the Vth for the first and second MOS transistors; and d) iteratively repeating steps b) and c) until a desired Vth is achieved.

Description:
FIELD OF DISCLOSURE 
       [0001]    The disclosed method relates to integrated circuits. More specifically, the disclosed method relates to static random access memory (SRAM) circuits formed on a semiconductor substrate. 
       BACKGROUND 
       [0002]    Semiconductor memory devices are continually being designed to be made smaller, faster, and to require less power such that they may be incorporated in portable devices that run on battery power. SRAM is volatile memory widely used in laptop computers and personal digital assistants (PDAs) in which each memory cell includes a transistor-based bi-stable latch that is either in an ‘on’ state or an ‘off’ state. SRAM devices may include a matrix of thousands of individual memory cells fabricated in an integrated circuit (IC) chip. 
         [0003]      FIG. 1A  illustrates one example of an eight transistor (8T) SRAM cell  100 A. The 8T SRAM cell  100 A includes a cross-coupled inverter  102 A including PMOS transistors P 1 , P 2  and NMOS transistors N 1 , N 2 . NMOS transistor N 3  is coupled to a bit line (BL) and to node  104  of inverter  102 A. The gate of NMOS transistor N 3  is coupled to a write word line (WWL). NMOS transistor N 4  is coupled to inverter  102 A at node  106  and to a bit line bar (BLB). The gate of NMOS transistor N 4  is coupled to WWL. Read port transistor N 5 , which functions as a read pull-down (RPD) transistor, has its gate coupled to node  106  of inverter  102 A, its source coupled to ground, and its drain coupled to read port transistor N 6 , which functions as a read pass gate (RPG) transistor. The gate of read port transistor N 6  is coupled to a read word line (RWL), and the drain of the RPG transistor N 6  is coupled to the read bit line (RBL). 
         [0004]      FIGS. 1B and 1C  respectively illustrate a ten transistor (10T) SRAM cell  100 B and a twelve transistor (12T) SRAM cell  100 C. Each of 10T and 12T SRAM cells  100 B and  100 C include inverters  102 B and  102 C as well as read port cells  108 B and  108 C. Each of the read port cells  108 B,  108 C include an RPD transistor and an RPG transistor. 
         [0005]    In each of the SRAM cells  100 A,  100 B, and  100 C, the threshold voltage (V th ) of the RPG transistor is typically increased to minimize the subthreshold leakage current in order to reduce the overall power consumption of the SRAM array. The conventional method of increasing the V th  of the RPG transistor is by doping the channel of the RPG transistor. However, doping the channel of RPG transistor not only increases the number of processing steps for fabricating the SRAM, but it also results in an increase in the circuit footprint and the instability of the RPG transistor. For example,  FIGS. 2A and 2B  respectively illustrate cross-sectional and plan views of the RPG and RPD transistors in an SRAM cell, and  FIGS. 2C and 2D  respectively illustrate cross-sectional and plan views of the RPG and RPD transistors in an SRAM cell in which the V th  of the RPG transistor is higher than the V th  of the RPG transistor illustrated in  FIGS. 2A and 2B . In order to isolate the channels of the RPG and RPD transistors, a shallow trench isolation (STI) structure is disposed between the drain of the RPD transistor and the source of the RPG transistor such that only the V th  of the RPG transistor is increased. The addition of the STI structure increases the floor plan of the SRAM cell. 
         [0006]    In high-speed applications such as register files (RFs) and L1-caches, the V th  of a two read-port device is lowered in order to increase the operating speed of the devices. The reduced V th  increases the read-port current to reduce the access time, but this results in a significant increase in the leakage current. Consequently, a tradeoff is typically made between reducing the leakage current and increasing the speed of the transistors of the SRAM circuit. 
         [0007]    Accordingly, an improved system and method for reducing the leakage current of transistors in high-speed applications is desirable. 
       SUMMARY 
       [0008]    A method is disclosed that includes a) receiving a design for a static random access memory (SRAM) array including an SRAM cell having a read port cell, the read port cell including first and second MOS transistors each having an initial threshold voltage (V th ); b) adjusting one of a gate channel width (W g ) or a gate channel length (L g ) of one of the first and second MOS transistors to modify the V th  of at least one of the first and second MOS transistors; c) simulating a response of the SRAM array, the simulation providing response data for the SRAM array including the V th  for the first and second MOS transistors; and d) iteratively repeating steps b) and c) until a desired V th  is achieved. 
         [0009]    An electronic design automation (EDA) system is also disclosed. The EDA system includes a computer readable storage medium and a processor in signal communication with the computer readable storage medium. The processor is configured to receive a design for a static random access memory (SRAM) array including an SRAM cell having a read port cell with first and second MOS transistors. The processor is configured to calculate an initial threshold voltage (V th ) for each of the first and second MOS transistors and receive a second design for the SRAM array. The second design includes an SRAM cell having a read port cell with the first MOS transistor and a third MOS transistor. The third MOS transistor has at least one of a gate channel width (W g ) dimension or a gate channel length dimension (L g ) that differs from a W g  or an L g  dimension of the second MOS transistor. The processor is configured to simulate a response of the second design for the SRAM array and generate a data file representing a physical layout of the SRAM array on a semiconductor wafer. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]      FIG. 1A  is a schematic diagram of an eight transistor static random access memory (SRAM) cell. 
           [0011]      FIG. 1B  is a schematic diagram of a ten transistor SRAM cell. 
           [0012]      FIG. 1C  is a schematic diagram of a twelve transistor SRAM cell. 
           [0013]      FIG. 2A  is a cross-sectional view of the transistors of the read-port cell illustrated in  FIG. 1 . 
           [0014]      FIG. 2B  is a plan view of the transistors of the read-port cell of the SRAM cell illustrated in  FIGS. 1A-1C . 
           [0015]      FIG. 2C  is a cross-section view of a conventional method of increasing the threshold voltage (V th ) of one of the transistors in the read-port cell of the SRAM cell illustrated in  FIGS. 1A-1C . 
           [0016]      FIG. 2D  is a plan view of a conventional method of increasing the V th  of one of the transistors of the read-port cell of the SRAM cell illustrated in  FIGS. 1A-1C . 
           [0017]      FIG. 3  is a flow diagram of one example of a method of increasing the V th  of the read-port cell in high-speed SRAM. 
           [0018]      FIG. 4A  is a plan view of the transistors of a read port cell in an original layout. 
           [0019]      FIG. 4B  is a plan view of the transistors of the read port cell in accordance with  FIG. 4A  with the V th  of one of the transistors having been adjusted in accordance with the improved method. 
           [0020]      FIG. 4C  is a plan view of the transistors of the read port cell in accordance with  FIG. 4A  with the V th  of one of the transistors having been adjusted in accordance with an improved method. 
           [0021]      FIG. 5  is a graph showing current leakage versus access time for read port cells having various threshold voltages. 
           [0022]      FIG. 6  is a block diagram of a system for performing the method illustrated in  FIG. 3 . 
       
    
    
     DETAILED DESCRIPTION 
       [0023]    A method of increasing the threshold voltage (V th ) of the transistors of a read port cell of an SRAM circuit is disclosed to provide a decrease in subthreshold leakage while maintaining a high-operating speed in a small footprint. The method includes separately adjusting the V th  of the read-port cell by varying the gate-channel length (L g ) and/or the gate-channel width (W g ) while maintaining the dimensions of the other transistors in the SRAM array. 
         [0024]      FIG. 3  is a flow diagram of one example of a method for increasing the threshold voltage of transistors in high-speed SRAM applications. At block  302 , a circuit design for an SRAM array is received. The circuit design includes transistor data for the transistors of the SRAM array. The transistor data may include values for a channel width, channel length, and oxide thickness of the transistors to name a few. 
         [0025]    At block  304 , the V th  of each of the read port transistors is calculated based on the received transistor data. As will be understood by one skilled in the art, the V th  of the transistor may be based on a variety of characteristics of the transistor such as, for example, the oxide thickness, the permittivity of the silicon, and the gate channel width (W g ) and length (L g ). Equations 1 and 2 below show the relationship between V th  and the W g  and L g  of a transistor. 
         [0000]    
       
         
           
             
               
                 
                   
                     Δ 
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                       3 
                     
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                         s 
                       
                       
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                       ( 
                       
                         
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                         + 
                         
                           V 
                           SB 
                         
                       
                       ) 
                     
                   
                 
               
               
                 
                   Eq 
                   . 
                   
                       
                   
                    
                   1 
                 
               
             
             
               
                 
                   
                     Δ 
                      
                     
                         
                     
                      
                     
                       V 
                       
                         TH_L 
                         g 
                       
                     
                   
                   = 
                   
                     
                       - 
                       2 
                     
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                       β 
                       1 
                     
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                         s 
                       
                       
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                         [ 
                         
                           
                             ( 
                             
                               
                                 φ 
                                 0 
                               
                               + 
                               
                                 V 
                                 SB 
                               
                             
                             ) 
                           
                           + 
                           
                             
                               β 
                               2 
                             
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                               V 
                               DS 
                             
                           
                         
                         ] 
                       
                     
                   
                 
               
               
                 
                   Eq 
                   . 
                   
                       
                   
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                   2 
                 
               
             
           
         
       
     
       Where, 
       [0026]    t ox  is the oxide thickness; 
         [0027]    ε ox  is the permittivity of the oxide; 
         [0028]    ε s  is the permittivity of silicon; 
         [0029]    V SB  is the source-base voltage of the transistor; 
         [0030]    φ 0  is the surface potential; and 
         [0031]    β 1,2, and 3  are process dependent constants. 
         [0032]    The calculated V th  of the read port transistors may be stored in a computer readable storage medium at block  306 . At block  308 , at least one of W g  or L g  of one of the transistors of the read port cell is adjusted (e.g., increased or decreased) to adjust the V th  of the transistor. For example,  FIG. 4A  is a plan view of an initial layout of the RPG and RPD transistors of a read port cell  108 A- 108 C of an SRAM cell  100 A- 100 C in which the RPD transistor has a W g  of approximately 215 nm and an L g  of approximately 30 nm, and the RPG transistor has a W g  of approximately 200 nm and an L g  of approximately 32 nm.  FIG. 4B  illustrates a plan view of the RPG and RPD transistors of a read port cell  108 A- 108 C in which the L g  of the RPG transistor has been increased from 32 nm to 53 nm to increase the V th  of the RPG transistor.  FIG. 4C  is a plan view of the RPG and RPD transistors of a read port cell  108 A- 108 C in which the W g  of the RPG transistor is decreased from 200 nm to 8 nm to increase the V th  of the RPG transistor. One skilled in the art will understand that the W g  and L g  of the RPD transistors may be adjusted to have other dimensions depending on the operating conditions of the SRAM cell  100 . Additionally, W g  and L g  of the RPD transistors may also be adjusted to increase the V th  of the RPD transistors. The W g  and L g  of both the RPG and RPD transistors may be simultaneously adjusted to achieve the desired V th  of the transistors as will be understood by one skilled in the art. 
         [0033]    At block  310 , a simulation is performed for an SRAM array including SRAM cells  100 A- 100 C having read port cells  108 A- 108 C with at least one of the RPG transistor or the RPD transistor having a dimension of at least one of W g  or L g  being different from its initial dimension. The dimensions of the other transistors in the SRAM array are maintained. The simulation may be performed using a simulation program with integrated circuit emphasis (SPICE) that may be run on a system  600  as illustrated in  FIG. 6 . As shown in  FIG. 6 , the system  600  may include an electronic design automation tool  602  such as “IC COMPILER”™, sold by Synopsis, Inc. of Mountain View, Calif., having a router  604  such as “ZROUTE”™, also sold by Synopsis. Other EDA tools  602  may be used, such as, for example, the “VIRTUOSO” custom design platform or the Cadence “ENCOUNTER”® digital IC design platform along with the “VIRTUOSO” chip assembly router  604 , all sold by Cadence Design Systems, Inc. of San Jose, Calif. 
         [0034]    The EDA tool  602  is a special purpose computer formed by retrieving stored program instructions  622  from a computer readable storage mediums  614 ,  616  and executing the instructions on a general purpose processor  606 . Processor  606  may be any central processing unit (CPU), microprocessor, micro-controller, or computational device or circuit for executing instructions. Processor  606  may be configured to perform circuit simulations based on a plurality of data stored in the one or more computer readable storage mediums  614 ,  616 . 
         [0035]    The computer readable storage medium  614 ,  616  may include one or more of registers, a random access memory (RAM) and/or a more persistent memory, such as a ROM. Examples of RAM include, but are not limited to, SRAM or dynamic random-access memory (DRAM). A ROM may be implemented as a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), magnetic or optical storage media, as will be understood by one skilled in the art. 
         [0036]    System  600  may include a monitor  610  and a user interface or input device  612  such as, for example, a mouse, a touch screen, a microphone, a trackball, a keyboard, or like device through which a user may input design instructions and/or data. The one or more computer readable storage mediums  614 ,  616  may store data input by a user, design rules  620 , IC design and cell information  618 , and data files  626 , such as GDSII files, representing a physical layout of a circuit. Computer readable storage mediums  614 ,  616  may also store various transistor models in a variety of formats including, but not limited to, BSIM3, BSIM4, PSP, and HiSIM to name a few. 
         [0037]    EDA tool  602  may include a communication interface  608  allowing software and data to be transferred between EDA tool  602  and external devices. Example communications interfaces  608  include, but are not limited to, modems, Ethernet cards, wireless network cards, Personal Computer Memory Card International Association (PCMCIA) slots and cards, or the like. Software and data transferred via communications interface  608  may be in the form of signals, which may be electronic, electromagnetic, optical, or the like that are capable of being received by communications interface  608 . These signals may be provided to communications interface  108  via a communication path (e.g., channel), which may be implemented using wire, cable, fiber optics, a telephone line, a cellular link, a radio frequency (RF) link, to name a few. 
         [0038]    The router  604  is capable of receiving an identification of a plurality of circuit components to be included in an integrated circuit (IC) layout including a list of pairs of cells, macro blocks or I/O pads within the plurality of circuit components to be connected to each other. A set of design rules  620  may be used for a variety of technology nodes (e.g., technology greater than, less than, or equal to 32 nm). In some embodiments, the design rules  620  configure the router  604  to locate connecting lines and vias on a manufacturing grid. 
         [0039]    One or more plots of data may be displayed to a user of the system  600  on a monitor  612 . The plots may provide the user with a graphical representation of various circuit and device parameters including, but not limited to, the V th  of the RPG and RPD transistors, the operating frequency of the RPG and RPD transistors, the operating frequency of the SRAM cell  100 A- 100 C, and the leakage current to name a few. 
         [0040]    At decision block  312 , a determination is made as to whether the desired V th  for the read cell transistor(s) having the adjusted W g  and/or L g  has been achieved. The determination may be based on V th  as well as the operating frequency of the RPG and RPD transistors. If the V th  value is not acceptable, then the method proceeds to block  308  and the W g  and/or L g  of one or more of the RPG and RPD transistors may be adjusted as described above. If the V th  value is acceptable, then the method may proceed to block  314 . One of ordinary skill in the art will appreciate that the loop including steps  308 ,  310  and  312  may be executed any number of times, until a desired predetermined V th  is achieved. This iteration can be performed by a computer repeatedly determining the value of V th  for a plurality of different transistor adjustments, so that an acceptable transistor can be achieved on a first iteration on actual silicon. 
         [0041]    At block  314 , the masks for the SRAM array including the SRAM cells  100  having the read port cells  108 A- 108 C with the desired V th  are developed. The SRAM array may then be fabricated at block  316 . 
         [0042]    In other examples, following generation of a mask set and fabrication of a substrate including the tuned transistor, additional adjustments can be made using the method of  FIG. 3 , by inputting the design used in silicon as the input design in  FIG. 3 . 
         [0043]    The method  300  for adjusting the V th  for the transistors of a read port cell  108 A- 108 C in an SRAM cell  100 A- 100 C described above advantageously enables the leakage current to be minimized while maintaining a high operating frequency and without dramatically increasing the footprint compared to the channel doping as conventionally performed to increase the V th . The improved method described above also enables independent or simultaneous adjustment the V th  of the transistors of the read port cell while the dimensions for the other transistors of the SRAM array for the particular technology node for which the SRAM array is being designed may be maintained. Additionally, adjusting the V th  of the transistors of the read port cell by adjusting at least one of the L g  or W g  of one of the RPG or RPD transistors reduces the variation of the Vth, which is approximately proportional to square root of the quotient of the dopant concentration divided by the product of the L g  and W g . Accordingly, adjusting the V th  of at least one of the RPG and RPD transistors as described above will have a more consistent operation compared to a transistor having its V th  increased through the conventional method of doping the channel. 
         [0044]    Table 1 below lists the V th  for the RPG and RPD transistors, total circuit delay for an SRAM array, and the current leakage for the SRAM cell for an initial design, the conventional doping method of adjusting the V th  of the read port transistors, and the improved method of adjusting the V th  of the read port transistors. 
         [0000]    
       
         
               
               
               
               
             
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                   
                 Conventional 
                   
               
               
                   
                 Initial Design 
                 Doping Method 
                 Improved Method 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                 Read-Port Cell 
                 ΔV thRPG  = 0 mV 
                 ΔV thRPG  = 20 mV 
                 ΔV thRPG  = 20 mV 
               
               
                   
                 ΔV thRPD  = 0 mV 
                 ΔV thRPD  = 20 mV 
                 ΔV thRPD  = 0 mV 
               
               
                 Total Circuit 
                 80 ps 
                 85 ps 
                 81.5 ps 
               
               
                 Delay 
               
               
                 Current 
                 146.75 nA 
                 93.47 nA 
                 93.49 nA 
               
               
                 Leakage 
               
               
                   
               
             
          
         
       
     
         [0045]    As shown in Table 1, the improved method provides only a slight degradation in circuit delay (e.g., approximately two percent) compared to the conventional doping method, which experiences a delay of approximately six percent. Further, the method described above provides a current leakage that is almost identical to the reduced current leakage experienced by the conventional doping method.  FIG. 5  is a graphical representation of the data in Table 1. 
         [0046]    The present invention may be embodied in the form of computer-implemented processes and apparatus for practicing those processes. The present invention may also be embodied in the form of computer program code embodied in tangible machine readable storage media, such as random access memory (RAM), floppy diskettes, read only memories (ROMs), CD-ROMs, hard disk drives, flash memories, or any other machine-readable storage medium, wherein, when the computer program code is loaded into and executed by a computer, the computer becomes an apparatus for practicing the invention. The present invention may also be embodied in the form of computer program code loaded into and/or executed by a computer, such that, when the computer program code is loaded into and executed by a computer, the computer becomes an apparatus for practicing the invention. When implemented on a general-purpose processor, the computer program code segments configure the processor to create specific logic circuits. The invention may alternatively be embodied in a digital signal processor formed of application specific integrated circuits for performing a method according to the principles of the invention. 
         [0047]    Although the invention has been described in terms of exemplary embodiments, it is not limited thereto. Rather, the appended claims should be construed broadly, to include other variants and embodiments of the invention, which may be made by those skilled in the art without departing from the scope and range of equivalents of the invention. Delimiters used in the claims—such as ‘a)’ and ‘i)’—should not be taken as imputing any order to the claims, but rather are provided only to serve as visual cues to add in the parsing of the claims and as identifiers in the event that a particular portion of the claim is to be later referenced.