Abstract:
A method for manufacturing light emitting diodes includes steps: providing a substrate having an upper conductive layer and a lower conductive layer formed on a top face and bottom face thereof; dividing each of the upper conductive layer and the lower conductive layer into first areas and second areas; defining cavities in the substrate through the first areas of the upper conductive layer to expose the lower conductive layer; forming conductive posts within the substrate; forming an overlaying layer to connect the first areas of the upper and lower conductive layers; mounting chips on the overlaying layer within the cavities and electrically connecting each chip with an adjacent first area and post; forming an encapsulant on the substrate to cover the chips; and cutting the substrate into individual packages.

Description:
BACKGROUND 
     1. Technical Field 
     The present disclosure relates to a method for manufacturing light emitting diodes, and more particularly, to a method for manufacturing light emitting diodes having high heat dissipation performance. 
     2. Description of Related Art 
     As a new type of light source, LEDs are widely used in various applications. A typical LED includes a base, a pair of leads inserted into the base, a light emitting chip fixed on the base and electrically connected to the leads via wires, and an encapsulant attached on the base and sealing the light emitting chip. The base is often made of epoxy or silicon for insulation of the two leads of the LED. This LED is often made by molding an epoxy or silicon block on a patterned metal plate, and then fixing a plurality of light emitting chips on the block, bonding wires from the light emitting chips to the metal plate, molding a transparent material on the base to seal the light emitting chips, and cutting the block and metal plate to individual packages. 
     However, the LED manufactured by this method has a limited heat dissipation capability, since the epoxy or silicon base has a low heat conductivity. The operation of the LED is affected by accumulated heat within the LED. 
     What is needed, therefore, is a method for manufacturing light emitting diodes which can overcome the limitations described above. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Many aspects of the present disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views. 
         FIG. 1  shows a first process of manufacturing light emitting diodes in accordance with an embodiment of the present disclosure. 
         FIG. 2  shows a second process of manufacturing light emitting diodes in accordance with the embodiment of the present disclosure. 
         FIG. 3  shows a third process of manufacturing light emitting diodes in accordance with the embodiment of the present disclosure. 
         FIG. 4  is top view of a semi-finished product obtained from the third process of manufacturing light emitting diodes of  FIG. 3 . 
         FIG. 5  is a bottom view of the semi-finished product obtained from the third process of manufacturing light emitting diodes of  FIG. 3 . 
         FIG. 6  shows a fourth process of manufacturing light emitting diodes in accordance with the embodiment of the present disclosure. 
         FIG. 7  shows a fifth process of manufacturing light emitting chips in accordance with the embodiment of the present disclosure. 
         FIG. 8  shows a sixth process of manufacturing light emitting diodes in accordance with the embodiment of the present disclosure. 
         FIG. 9  shows a seventh process of manufacturing light emitting diodes in accordance with the embodiment of the present disclosure. 
         FIG. 10  shows an eighth process of manufacturing light emitting diodes in accordance with the embodiment of the present disclosure. 
         FIG. 11  shows a ninth process of manufacturing light emitting diodes in accordance with the embodiment of the present disclosure. 
         FIG. 12  shows a light emitting diode which has been manufactured after the processes of  FIGS. 1-11 . 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     A method for manufacturing light emitting diodes in accordance with an embodiment of the present disclosure is disclosed. The method mainly includes multiple steps as described below. 
     As shown in  FIG. 1 , a substrate  10  is provided. The substrate  10  may be made of epoxy, silicon, ceramic or other electrically insulating materials. The substrate  10  has a flat top face  12  and a flat bottom face  14  opposite to the top face  12 . 
     As shown in  FIG. 2 , an upper conductive layer  20  and a lower conductive layer  30  are formed on the top face  12  and the bottom face  14  of the base  10 , respectively. The upper conductive layer  20  and the lower conductive layer  30  are parallel to each other and both are made of metal such as copper, aluminum or silver. The upper conductive layer  20  and the lower conductive layer  30  may be formed by deposition, sputtering, adhering or other suitable methods. 
     As shown in  FIGS. 3-5 , then a plurality of grooves  200 ,  202 ,  204 ,  300 ,  302  are defined in the upper conductive layer  20  and the lower conductive layer  30  to expose parts of the top face  12  and bottom face  14  of the substrate  10 . The grooves  200 ,  202 ,  204  defined in the upper conductive layer  20  can be divided into two groups, wherein each group includes a first upper groove  200 , a second upper groove  202  and a third upper groove  204 . The first, second and third upper grooves  200 ,  202 ,  204  are all extended through the upper conductive layer  20  from a front side of the substrate  10  to an opposite rear side of the substrate  10 . The first upper groove  200  of each group has a width the same as that of the second upper groove  202 , and smaller than that of the third upper groove  204 . The upper conductive layer  20  is divided by the first and second upper grooves  200 ,  202  into two first upper areas  22  and two second upper areas  24  alternating with the first upper areas  22 . Each first upper area  22  is further divided by a corresponding third upper groove  204  into a first strip  220  and a second strip  222 . The first strip  220  has a width larger than that of the second strip  222 , and similar to that of the second upper area  24 . Each second upper area  24  is located between an adjacent first strip  220  and second strip  222 . A plurality of upper holes  206  are defined in each of the second upper areas  24 . The upper holes  206  in each second upper area  24  are arranged in a straight line. Each upper hole  206  is terminated at the top face  12  of the substrate  10 . 
     The grooves  300 ,  302  defined in the lower conductive layer  30  include first lower grooves  300  and second lower grooves  302  alternating with the first lower grooves  300 . The lower conductive layer  30  is divided by the first lower grooves  300  and second lower grooves  302  into two discrete first lower areas  32  and second lower areas  34  alternating with the first lower areas  32 . A plurality of lower holes  306  are defined in each of the second lower areas  34  and arranged along a straight line. The first lower grooves  300 , the second lower grooves  302 , the first lower areas  32 , the second lower areas  34  and the lower holes  306  are located corresponding to the first upper grooves  200 , the second upper grooves  202 , the first upper areas  22 , the second upper areas  24  and the upper holes  206 , respectively. 
     Also referring to  FIG. 6 , the substrate  10  is etched to form a plurality of cavities  100  and through holes  102 . Each cavity  100  is defined between adjacent first strip  220  and second strip  222 . Each cavity  100  is terminated at a top face of a corresponding first lower area  32  of the lower conductive layer  30  so that a top face of the first lower area  32  is exposed within the cavity  100 . Each cavity  100  has an inner diameter gradually decreasing from the top face  12  of the substrate  10  towards the bottom face  14  of the substrate  10 . Each through hole  102  extends from the top face  12  of the substrate  10  to the bottom face  14  of the substrate  10 . Each through hole  102  is aligned and communicates with a corresponding upper hole  206  and lower hole  306 . The cavities  100  and the through holes  102  can also be formed by drilling, laser or other suitable methods. 
     A conductive material is filled into the through holes  102  and the upper holes  206  and the lower holes  306  to form a plurality of conductive posts  40  within the substrate  10  as shown in  FIG. 7 . Each conductive post  40  mechanically and electrically connects a corresponding second upper area  24  and a second lower area  34  located just below the corresponding second upper area  24 . The conductive post  40  has a top face flush with that of the second upper area  24 , and a bottom face flush with that of the second lower area  34 . The conductive posts  40  may be formed by electro-plating metal into the through holes  102  or injecting conductive adhesive into the through holes  102 . 
     An overlaying layer  50  is further formed to cover the upper conductive layer  20  and the lower conductive layer  30  as shown in  FIG. 8 . The overlaying layer  50  has upper parts  52  each covering a top face and a lateral face of the first strip  220 , an inner circumferential face and a bottom face of the cavity  100  and a top face and a lateral face of the second strip  222  The bottom face of the cavity  100  is coincidental with the exposed top face of the first lower area  32 . The overlaying layer  50  further has lower parts  54  each covering two lateral faces and a bottom face of the first lower area  32 . The upper part  52  and the lower part  54  of the overlaying layer  50 , the first upper area  22  and the first lower area  32  cooperatively form a first lead. The overlaying layer  50  also has the other upper parts  56  each covering two lateral faces and a top face of the second upper area  24  and a top face of the conductive post  40 , and the other lower parts  58  each covering two lateral faces and a bottom face of the second lower area  34  and a bottom face of the conductive post  40 . The other upper part  56 , the other lower part  58 , the conductive post  40 , the second upper area  24  and the second lower area  34  cooperatively form a second lead. Each second lead is spaced from two adjacent first leads via the first upper groove  200 , the second upper groove  202 , the first lower groove  300  and the second lower groove  302 . The overlaying layer  50  may be formed by electro-plating or chemical-plating. 
     Also referring to  FIG. 9 , a plurality of light emitting chips  60  are mounted within the cavities  100 , respectively. Each light emitting chip  60  is fixed on a top face of a portion of the overlaying layer  50  within the cavity  100 . A pair of wires  70  electrically connect the light emitting chip  60  with the first lead and the second lead, wherein one wire  70  is bonded to a portion of the overlaying layer  50  corresponding to the first strip  220 , and the other wire  70  is bonded to a portion of the overlaying layer  50  corresponding to the second upper area  24 . The light emitting chip  60  may be made of GaN, InGaN, AlInGaN or other suitable materials. 
     An encapsulant  80  is molded on the substrate  10  to seal the light emitting chips  60  as shown in  FIG. 10 . The encapsulant  80  joins the overlaying layer  50  and fills the first upper grooves  200  and the second upper grooves  202 . The encapsulant  50  may be made of epoxy, silicon or other transparent materials. 
     The substrate  10  together with the encapsulant  80  are then cut into a plurality of individual LED packages through the second upper grooves  202  and the second lower grooves  302  as shown in  FIG. 11 .  FIG. 12  shows one of the LED packages having been manufactured. The LED includes one first lead, one second lead and one light emitting chip  60  electrically connected to the first lead and the second lead. The first lead and the second lead can be electrically coupled with a power source to activate the light emitting chip  60  to lighten. 
     Since the light emitting chip  60  is fixed on the overlaying layer  50  which is directly connected to the lower conductive layer  30 , the heat conducting pathway from the light emitting chip  60  to the outside of the LED is shorten and the heat can be rapidly conducted from the light emitting chip  60  to the outside of the LED through the overlaying layer  50  and the lower conductive layer  30 . 
     It is believed that the present disclosure and its advantages will be understood from the foregoing description, and it will be apparent that various changes may be made thereto without departing from the spirit and scope of the present disclosure or sacrificing all of its material advantages, the examples hereinbefore described merely being preferred or exemplary embodiments.