Abstract:
A method for the formation of buried cavities within a semiconductor body envisages the steps of: providing a wafer having a bulk region made of semiconductor material; digging, in the bulk region, trenches delimiting between them walls of semiconductor material; forming a closing layer for closing the trenches in the presence of a deoxidizing atmosphere so as to englobe the deoxidizing atmosphere within the trenches; and carrying out a thermal treatment such as to cause migration of the semiconductor material of the walls and to form a buried cavity. Furthermore, before the thermal treatment is carried out, a barrier layer that is substantially impermeable to hydrogen is formed on the closing layer on top of the trenches.

Description:
PRIORITY CLAIM  
       [0001]     This application claims priority from Italian patent application No. TO2005A 000478, filed Jul. 12, 2005, which is incorporated herein by reference.  
       TECHNICAL FIELD  
       [0002]     An embodiment of the present invention relates to a method for forming buried cavities within a semiconductor body.  
       BACKGROUND  
       [0003]     As is known, many devices based upon semiconductor technology are provided with cavities, such as chambers or channels, buried in a semiconductor body. In some cases, such as for example in pressure sensors, the cavities are sealed in a gas-tight way by deformable membranes. In this way, within the cavities themselves a constant reference pressure value is maintained at rest, whereas variations of the external pressure cause deformations of the membrane, which can be detected in various known ways. Typically, variations of the capacitive coupling are detected between the membrane and the underlying semiconductor body, or else piezoresistive circuit elements connected in a Wheatstone-bridge configuration are used. In other devices, such as microfluidic devices that can be used for example as chemical microreactors or for the fabrication of ink-jet printer heads, the cavities comprise microchannels forming a microfluidic circuit. In this case, the microfluidic circuit is generally accessible from the outside through openings so as to receive the fluids necessary for operation of the device.  
         [0004]     The formation of buried cavities or in any case of covered cavities in general raises some difficulties.  
         [0005]     In order to overcome said difficulties, use of thermal processes of annealing has been proposed, which enable buried cavities of arbitrary shape to be obtained starting from trenches dug in a semiconductor body, causing a migration of the surrounding atoms. According to the technique described in EP-A-1 324 382, which is incorporated by reference, a semiconductor body, made, for example, of silicon, is initially anisotropically etched in order to dig adjacent trenches, close to one another and separated by diaphragms. The trenches are then closed without being filled by growing an epitaxial layer. Alternatively, instead of the trenches separated by diaphragms, it is possible to define a honeycomb structure of silicon pillars at a small distance from one another.  
         [0006]     The epitaxial growth is performed in a deoxidizing environment rich in hydrogen, which remains trapped in the trenches (or in the interstices between the pillars) and is subsequently exploited in order to carry out an annealing step. In practice, the semiconductor body is heated to a pre-set temperature and for a pre-set time. Thanks to the deoxidizing atmosphere (rich in molecular hydrogen), the semiconductor material surrounding the cavity is subject to migration and tends to redistribute according to a minimum-energy configuration, maintaining in any case the order of the monocrystal. The diaphragms (or pillars) are thinned out progressively until they disappear altogether, and a single cavity is basically formed, closed by a portion of the epitaxial layer, which forms a suspended semiconductor membrane.  
         [0007]     The known techniques present limits however. In fact, it has been noted that, during annealing, the hydrogen contained within the cavities tends to be dispersed through the epitaxial layer, which is thinner and partially permeable. Mere heating of the semiconductor body is not, therefore, as a rule sufficient to complete migration and obtain buried cavities of the desired shape. In order to prevent impoverishment of the internal deoxidizing atmosphere that may render the treatment ineffective, the annealing is likewise carried out in a controlled environment. Special machinery is hence often necessary, capable of controlling the environmental concentrations of gaseous species (in particular, hydrogen), such as for example epitaxial reactors or hydrogen ovens.  
       SUMMARY  
       [0008]     An embodiment of the present invention is a method for forming buried cavities within a semiconductor body and a semiconductor body comprising buried cavities, which will enable one or more of the limitations described to be overcome. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]     For an understanding of the present invention, one or more embodiments thereof are now described purely by way of non-limiting example, with reference to the attached drawings.  
         [0010]      FIG. 1  shows a cross section through a wafer made of semiconductor material in an initial step of fabrication, according to a first embodiment of the present invention.  
         [0011]      FIG. 2  is a top view of the wafer of  FIG. 1  according to an embodiment of the invention.  
         [0012]      FIG. 3  is a cross-section of details of  FIG. 2 , at an enlarged scale according to an embodiment of the invention.  
         [0013]      FIGS. 4-10  show cross sections through the wafer of semiconductor material of  FIG. 1 , in subsequent steps of fabrication, in the case of fabrication of a pressure sensor of a capacitive type according to an embodiment of the invention.  
         [0014]      FIG. 11  shows a wafer of semiconductor material in an intermediate fabrication step, according to a second embodiment of the invention.  
         [0015]      FIG. 12  is a top plan view of a wafer of semiconductor material in an initial fabrication step, according to a third embodiment of the present invention.  
         [0016]      FIG. 13  shows a cross section through the wafer of  FIG. 12  in a subsequent fabrication steps, taken along the line XIII-XIII of  FIG. 12  according to an embodiment of the invention.  
         [0017]      FIGS. 14-16  show sections through the wafer of  FIG. 12  in subsequent fabrication steps, taken along the line XIV-XIV of  FIG. 12  according to an embodiment of the invention.  
         [0018]      FIGS. 17-20  show sections through the wafer of  FIGS. 12-16  in subsequent fabrication steps, taken along the line XVII-XVII of  FIG. 16  according to an embodiment of the invention. 
     
    
     DETAILED DESCRIPTION  
       [0019]     According to a first embodiment, the invention is exploited for providing a capacitive pressure sensor made of semiconductor material. This must not, however, be considered as in any way limiting the scope of the invention, in so far as embodiments of the invention can advantageously be exploited for the fabrication of devices of an altogether different type, incorporating buried cavities.  
         [0020]     The present process is based upon the process disclosed in EP-A-1 324 382 for manufacturing a SOI wafer, and, more precisely, refers to the second embodiment shown in  FIGS. 11-14  of said document.  
         [0021]      FIG. 1  shows a wafer  1  of semiconductor material, preferably monocrystalline silicon, comprising an N-type substrate  2 , designed to form the bulk of the device according to an embodiment of the invention. A mask  3  made of resist or of another sacrificial layer (visible in the enlarged detail of  FIG. 3 ) is formed on the top surface of the substrate  2 . The mask  3  has two circular areas, designated by  4   a  and  4   b  and hereinafter referred to as the sensor area and the reference area, in each of which a honeycomb lattice is defined, the two lattices being of different sizes.  
         [0022]     In particular, as appears in the enlarged detail of  FIG. 2 , the sensor area  4   a  has mask regions  5   a  with a hexagonal shape arranged close to one another (see also the cross-section of  FIG. 3 ), while the reference area  4   b  has mask regions  5   b  that are more widely spaced. For example, the distance t between opposite sides of the mask regions  5   a  and  5   b  may be 2 μm, the distance d 1  between sides facing adjacent mask regions  5   a  may be 1 μm, and the distance d 2  between sides facing adjacent mask regions  5   b  may be 2 μm.  
         [0023]     Using the mask  3 , trench etching of silicon of the substrate  2  is performed, so forming a sensor trench  6   a  and a reference trench  6   b  at the sensor area  4   a  and at the reference area  4   b , respectively. The channels of the sensor and reference trenches  6   a ,  6   b  have, for example, a depth of approximately 10 μm, are of different widths, as may be seen in  FIG. 3 , and delimit silicon columns  7   a  and  7   b , respectively, which are, for example, identical and have a shape corresponding to that of the mask regions  5   a  and  5   b.    
         [0024]     Next (see  FIG. 4 ), the mask  3  is removed and an epitaxial growth is performed in a deoxidizing environment (typically, in an atmosphere with a high concentration of hydrogen, preferably using trichlorosilane-SiHC 13 ). Consequently, an epitaxial layer  10  (shown only in  FIG. 4  and hereinafter not distinguished from the substrate  2 ) of an N type, grows on top of the silicon columns  7   a  and  7   b  and closes, at the top, the sensor and reference trenches  6   a ,  6   b , trapping the gas present therein (here, molecules of hydrogen H 2 ). The thickness of the epitaxial layer  10  is, for example, 9 μm.  
         [0025]     At the end of the epitaxial growth, a pad-oxide layer  50  is formed over the entire epitaxial layer  10 . For example, the pad-oxide layer  50  has a thickness of 80 nm. Then, a barrier layer  51  is deposited on top of the pad-oxide layer  50  by means of chemical vapor deposition (CVD). The thickness and material of the barrier layer  51  are such that the barrier layer  51  itself is substantially impermeable to molecular hydrogen H 2 , in particular at the temperature at which the subsequent annealing step, which will be described hereinafter, will be performed. In the embodiment illustrated herein, the barrier layer  51  is made of silicon nitride and has a thickness of between 80 nm and 200 nm and, preferably, of 140 nm.  
         [0026]     An annealing step is then carried out, for example for 12 hours at 1150° C. ( FIG. 5 ).  
         [0027]     As discussed in the aforementioned patent EP-A-1 324 382, the annealing step causes a migration of the silicon atoms, which tend to move into the lower-energy position. Consequently, at the sensor trench  6   a , where the columns  7   a  are arranged close together, the silicon atoms migrate completely and form a sensor cavity  11 , closed at the top by a membrane  13 . On account of the presence of the sensor cavity  11  (having, for example, a diameter of 600 μm, according to the pressure to be applied), the membrane  13  is flexible and can be deflected under external stresses.  
         [0028]     Instead, at the reference trench  6   b , where the columns  7   b  are arranged at a larger distance apart, the migration of silicon atoms causes only a thinning of the columns  7   b  themselves, hereinafter indicated as pillars  15 . In practice, a labyrinthine cavity  12  is formed, wider than the reference trench  6   b . Furthermore, the pillars  15  present in the labyrinthine cavity  12  prevent movement to the overlying region, hereinafter referred to as electrode region  14 .  
         [0029]     During the annealing step, the barrier layer  51  prevents completely or at least drastically reduces the leakage of hydrogen within the sensor trench  6   a  and the reference trench  6   b . Consequently, annealing can substantially be performed in any type of atmosphere.  
         [0030]     The crystallographic quality of the membrane  13  is excellent, as is evident from tests carried out.  
         [0031]     After complete removal of the barrier layer  51  and of the pad-oxide layer  50  (see  FIG. 6 ), the membrane  13  and the electrode region  14  are doped via implantation of P-type dopant species, for example boron. Next (see  FIG. 7 ), an access trench  20  is dug just in the electrode region  14 , from the surface of the wafer  1  as far as the labyrinthine cavity  12 . The access trench  20  preferably has the shape shown in  FIG. 7 , and hence extends, by stretches, in the proximity of the periphery of the area occupied by the labyrinthine cavity  12 .  
         [0032]     Thermal oxidation of the pillars  15  is then carried out so as to form an oxidized region  21  underneath the electrode region  14 . The necessary oxygen is fed to the labyrinthine cavity  12  through the access trench  20 . In this step, there is a gradual growth of the oxidized region  21  at the expense of the pillars  15  and of the silicon of the substrate  2  surrounding the access trench  20  and the labyrinthine cavity  12 . In particular, the pillars  15  are completely oxidized and increase in volume. As shown in  FIG. 8 , the labyrinthine cavity  12  and the access trench  20  are filled in part with thermal oxide, but remain partially open (remaining portions  12 ′ and  20 ′ of the labyrinthine cavity and of the access trench).  
         [0033]     Next (see  FIG. 9 ), the remaining portions  12 ′ and  20 ′ of the labyrinthine cavity and of the access trench are filled with insulating material  22 , for example TEOS, forming, as a whole, an insulating region  24 . In  FIG. 9 , for reasons of clarity of illustration, the demarcation line between the insulating material  22  and the oxidized region  21  is represented by a dashed line. As an alternative, the labyrinthine cavity  12 ′ can remain empty, thus avoiding the filling step.  
         [0034]     A P-type implantation, an N-type implantation and respective diffusion steps are then carried out in order to form P + -type contact regions  25   a ,  25   b  above the membrane  13  and the electrode region  14  as well as N + -type contact regions  25   c ,  25   d  above the substrate  2  (see  FIG. 10 ). The contact regions  25   c ,  25   d  preferably have an annular shape and extend, respectively, around the membrane  13  and around the electrode region  14 . Next, metal contacts  26   a ,  26   b ,  26   c  and  26   d  are formed and contact the contact regions  25   a  to  25   d , respectively.  
         [0035]     In practice, the structure of  FIG. 10  constitutes a sensor  40  including two capacitors, designated by C 1  and C 0 , which have: as first electrode the membrane  13  and the electrode region  14 , respectively; as second electrode, the bulk region underlying the membrane  13  and the bulk region underlying the electrode region  14 , respectively; and as dielectric, the sensor cavity  11  and the insulating region  24  (or the oxidized region  21  and the labyrinthine cavity  12 ′), respectively.  
         [0036]     The capacitor C 1  (referred to also as sensing capacitor) represents the element sensitive to the pressure that is applied on the membrane  13 , whilst the capacitor C 0  (reference capacitor) represents the reference element, which supplies the rest capacitance. Since the areas of the P/N junctions of the sensing capacitor C 1  and of the reference capacitor C 0  are equal, these capacitors have the same junction capacitance and the same leakage currents. In addition, the reference capacitor C 0  may undergo a trimming step at the wafer level, using one or more known capacitors arranged in parallel and using a one-time programmable (OTP) device.  
         [0037]     If so desired, prior to formation of the contact regions  25   a - 25   d , it is possible to create the electronic components making up the control circuitry, which can be integrated on the same chip of the pressure sensor.  
         [0038]     Finally, in a way not shown, the wafer  1  is cut into dies, each containing a sensing capacitor C 1  and a reference capacitor C 0  (as well as, if envisaged, the control circuitry), and the dies are encapsulated in such a way that the membrane  13  is accessible from the outside.  
         [0039]     Therefore, an embodiment of the invention advantageously enables the annealing step to be carried out in a conventional oven. In fact, the barrier layer prevents the hydrogen trapped in the buried cavities from being dispersed through the epitaxial layer, which is partially permeable. The hydrogen trapped is hence sufficient to complete migration of the silicon towards the minimum-energy configuration when the wafer is heated. The need to compensate for the dispersion by controlling also the concentration of hydrogen in the external atmosphere in which the annealing has taken place is thus overcome. Annealing can hence be carried out in a conventional oven, and it is not necessary to use special machinery, such as epitaxial reactors or hydrogen ovens. Such an embodiment is hence simple to implement and economically advantageous. In addition, the use of a conventional oxidation oven enables more accurate control of the temperature and hence also uniformity of the thicknesses both of the membrane and of the pillars. Said thicknesses are in fact linked to the amount of migration of the silicon, which depends directly upon the temperature during the annealing.  
         [0040]     According to a different embodiment, to which  FIG. 11  refers, the sensor trench  6   a  and the reference trench  6   b  are opened using a mask (not shown), which has two respective regions with honeycomb lattices that are the same as one another (consequently, the density of the columns  7   a  and their mutual distances in the sensor trench  6   a  and the density of the columns  57   b  and their mutual distances in the reference trench  6   b  are substantially the same). The pad-oxide layer  50  and the barrier layer  51  are deposited and then selectively removed on top of the reference trench  6   b . Residual portions  50   a ,  51   a  of the pad-oxide layer  50  and of the barrier layer  51  are instead left on top of the sensor trench  6   a.    
         [0041]     The subsequent annealing step is carried out in a non-deoxidizing environment. Consequently, the deoxidizing atmosphere necessary for migration is preserved only within the reference trench  6   a , which is protected by the residual portion  51   a  of the barrier layer  51 . The hydrogen initially present in the reference trench  6   b , instead, is dispersed progressively outwards through the epitaxial layer  10 , left uncovered, and hence the deoxidizing atmosphere degrades progressively. Consequently, migration of the silicon around the reference trench  6   b  is much slower than around the sensor trench  6   a  and tends to stop. In practice, when the cavity sensor  11  is finally formed, the columns  57   b  in the reference trench  6   b  are only partially thinned out and form the pillars  15 .  
         [0042]     In practice, the use of the barrier layer  51  selectively on top of the sensor trench  6   a  and not on top of the reference trench  6   b  enables differentiated structures to be obtained starting from identical initial configurations and using a single annealing step. In particular, equal mask regions can advantageously be used in order to open the sensor trench  6   a  and the reference trench  6   b.    
         [0043]     The method proceeds as described above with reference to  FIGS. 6-10 .  
         [0044]     In accordance to a third embodiment of the invention, illustrated in  FIGS. 12-19 , a microfluidic device for biochemical analyses, in particular for analysis of nucleic acids, is made.  
         [0045]     As shown in  FIG. 12 , a wafer  100  of semiconductor material, preferably monocrystalline silicon, comprises a substrate  102  of an N type, designed to form the bulk of the device. On the surface of the substrate  102  a resist mask  103  is formed, having a plurality of slits  104  parallel to one another and extending in a direction X. The slits  104  are set alongside one another and organized in groups on top of channel areas  105 , which have a shape elongated in the direction X and are in turn parallel to one another. In  FIG. 12 , six parallel channel areas  105  are shown, but their number can differ.  
         [0046]     As shown in  FIGS. 13 and 14 , the mask  103  is used to carry out a trench etch of the silicon of the substrate  102  and form a plurality of trenches  106 , through the slits  104 . The trenches  106  of each channel area  105  have the same size in the direction transverse to the direction X (for example, 1 μm) and have the same depth, for example, of approximately 10 μm. In addition, adjacent trenches  106  delimit, and are separated by, thin silicon diaphragms  107  (the thickness of the diaphragms  107  is approximately of the same order of magnitude as the size of the trenches  106  in a direction transverse to the direction X). In practice, in each channel area  105  the diaphragms  107  are arranged in a comb-like configuration, and the trenches  106  are evenly spaced apart from one another.  
         [0047]     Next (see  FIG. 15 ), the mask  103  is removed, and an epitaxial growth is performed in deoxidizing environment (typically, in an atmosphere having a high concentration of hydrogen, preferably using trichlorosilane-SiHCI 3 ). Consequently, an N-type epitaxial layer  110  grows on top of the silicon diaphragms  107  and closes the trenches  106  at the top, trapping the gas present (here, molecules of hydrogen H 2 ). The thickness of the epitaxial layer  110  is, for example, 10 μm.  
         [0048]     At the end of the epitaxial growth, a pad-oxide layer  150 , having, for example, a thickness of 80 nm, is deposited over the entire epitaxial layer  110 . Next, a barrier layer  151  is formed on top of the pad-oxide layer  150  by means of CVD. The thickness and material of the barrier layer  151  are such that the barrier layer  151  itself is substantially impermeable to molecular hydrogen H 2 , in particular at the temperature at which the subsequent annealing step, which will be described hereinafter, will be carried out. In the embodiment illustrated herein, the barrier layer  151  is made of silicon nitride and has a thickness of 140 nm.  
         [0049]     An annealing step is then performed, for example for 12 hours at 1150° C. ( FIGS. 16 and 17 ). On account of the migration of the silicon atoms towards the lower-energy configuration, the diaphragms  107  are first thinned out and then consumed totally. Consequently, the trenches  106  of each channel area  105  join to one another and form a respective microfluidic channel  115 , buried in the silicon (in the embodiment described herein, the buried microfluidic channels  115  number six—see  FIG. 16 ). In greater detail, the microfluidic channels  115  are dug in the substrate  102  and are coated by the epitaxial layer  110 , which serves as closing layer. The microfluidic channels  115  are moreover parallel and have a length that is substantially equal to the size of the channel areas  105  in the direction X. During the annealing step, the barrier layer  151  prevents leakage of hydrogen within the trenches  106 . Consequently, the annealing can be carried out substantially in any type of atmosphere.  
         [0050]     After complete removal of the barrier layer  151  (see  FIG. 18 ), through holes  114  are opened through the epitaxial layer  110 , at the centre with respect to the microfluidic channels  115 . By means of a slight thermal oxidation, a passivation layer  118  is then formed, which coats the surface of the microfluidic channels  115  completely. The through holes  114  re-close during the thermal oxidation, on account of the tendency of the oxide to grow both inside and outside the silicon. In this step, the thickness of the pad-oxide layer  150  increases slightly.  
         [0051]     Then, as shown in  FIG. 19 , made on the pad-oxide layer  150  are: heaters  120 , set bestriding the microfluidic channels  115  and at a uniform distance from one another; temperature sensors  121 , associated with respective heaters  120 ; and an array of detection electrodes  122 , in addition to connection lines (not illustrated herein). The heaters  120 , the temperature sensors  121 , and the electrodes  122  can be all made by depositing and delineating a single metal layer. Alternatively, the heaters  120  can be made of polycrystalline silicon. The array of electrodes  122  is formed in a detection region adjacent to the outlets  117  of the microfluidic channels  115 . In a subsequent step, the electrodes  122  are functionalized by grafting single-helix target DNA strands (probes), to be used as references during the analyses. After formation of the heaters  120 , of the temperature sensors  121  and of the array of electrodes  122 , a new trench etch of the wafer  100  is made to open inlets  116  and outlets  117  at opposite ends of the microfluidic channels  115 . In this step, a resist mask is used (not shown).  
         [0052]     Finally (see  FIG. 20 ), a structural layer  125  made of polymeric material, for example dry resist or SU-8, is deposited on the wafer  100  and then defined to form an inlet reservoir  127  and a detection chamber  128 . The inlet reservoir is made so as to enable access to the microfluidic channels  115  from the outside, through the inlets  116 . The detection chamber  128 , into which the outlets  117  of the microfluidic channels  115  open, is formed around the array of electrodes  122 .  
         [0053]     A microfluidic device  130  for analysis of nucleic acids is thus obtained. In particular, in the microfluidic device  130 , the inlet reservoir  127 , the buried microfluidic channels  115 , and the detection chamber  128  are in fluid coupling with one another by means of the inlets  116  and outlets  117 , and form a microfluidic circuit. A fluid containing for example DNA and appropriate reagents is introduced into the inlet reservoir  127  and made to advance in a known way along the buried microfluidic channels  115  so as to be processed. In the example described, a process of amplification by means of polymerase-chain chain reaction (PCR) is envisaged. At the end of the amplification process, the fluid is made to advance further as far as the detection chamber  128  in order to hybridize the functionalized array of electrodes  122  (i.e., having a target DNA strand grafted thereon), for recognition of the sequences present.  
         [0054]     Also in the fabrication of microfluidic devices, the barrier layer can be selectively removed on top of portions of the areas designed to house the channels, to obtain differentiated structures, such as channels of different cross sections or chambers, using a single annealing step.  
         [0055]     One or more sensors, such a those described above, or according to one or more embodiments of the invention may be incorporated into an electronic system.  
         [0056]     Finally, it is clear that numerous modifications and variations may be made to the process described and illustrated herein, without departing from the scope of the invention.