Abstract:
This application discloses semiconductor devices with sharp gate edges including 2D and 3D memory cells, High Electron Mobility Transistors and tri-gate transistors. Implementation of a gate with sharp edges may improve the read and write speed and reduce the program and erase voltages in memory cells. It may also improve the gate control over the channel in tri-gate transistors and HEMTs. Methods to fabricate such devices are also disclosed.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a divisional application of U.S. non-provisional application Ser. No. 14/327,559 filed on Jul. 9, 2014 which claims the benefits of U.S. provisional application No. 61/913,381, filed on Dec. 8, 2013. 
     
    
     STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
       [0002]    Not Applicable. 
       REFERENCE TO SEQUENCE LISTING, A TABLE, OR A COMPUTER PROGRAM LISTING COMPACT DISC APPENDIX 
       [0003]    Not Applicable. 
       BACKGROUND OF THE INVENTION 
       [0004]    Memory devices, HEMTs and FinFETs are key components in today&#39;s semiconductor industry. Improving the characteristics of these devices is critical to improve their performance. One of the issues of memory cells is the relatively high read and write voltages to program and erase the cell. This issue becomes more critical if a high-k dielectric were used in the gate charge trapping structure. These relatively large voltages are required so that the charges in the channel can overcome the dielectric barrier and tunnel into the charge trapping region under the gate and vise versa. Moreover, in FinFETs, HEMTs and Tri-gate transistors for example, scaling down the transistor dimensions may decrease the gate control over the channel. Implementation of this invention may provide faster read and write processes and lower read and write voltages for memory cells. It may also provide a better gate control over the channel in FinFETs, HEMTs and Tri-gate transistors 
       BRIEF SUMMARY OF THE INVENTION 
       [0005]    It is generally known that the electric field is stronger near the sharp edges of the biased conductors. If the gate of a memory cell is designed in a way such that at least one of its edges in contact with a dielectric has an angle of less than 88 degrees, a smaller gate voltage may be required to move the charges from the channel into the charge trapping layer underneath the gate (and vise versa) which may improve the read and write speed. In addition, in FinFETs, HEMTs and Tri-Gate transistors, for example, if sharp gate edges were implemented, a smaller change in the gate bias may be required to accumulate the charge in the channel under the gate and turn ON the device. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING 
         [0006]      FIG. 1  shows a prior art wherein a typical planar memory cell with Oxide/Nitride/Oxide charge trapping structure is depicted. 
           [0007]      FIG. 2  shows an example embodiment of implementation of the invention in a planar memory cell with Oxide/Nitride/Oxide charge trapping structure. 
           [0008]      FIG. 3  shows a prior art wherein a tri-gate memory cell with Oxide/Nitride/Oxide charge trapping structure is depicted. 
           [0009]      FIG. 4  shows an example embodiment of implementation of the invention in a memory cell having a Fin. 
           [0010]      FIG. 5  shows an example embodiment of implementation of the invention in a tri-gate memory cell. 
           [0011]      FIG. 6  shows the relative positions of the gate and Fin masks during a lithography mask alignment process in a conventional method to fabricate the device shown in  FIG. 3 . 
           [0012]      FIG. 7  shows the relative positions of the gate and Fin masks during a lithography mask alignment process in a method to fabricate the device shown in  FIG. 4 . 
           [0013]      FIG. 8  shows an example embodiment of implementation of the invention in a memory cell having a Fin. 
           [0014]      FIG. 9  shows a prior art where it depicts a part of a vertical channel NAND flash memory structure in which 3D memory cells are implemented in a 3D array of memory cells. 
           [0015]      FIG. 10  shows an example embodiment of implementation of the invention in a 3D memory cell implemented in a 3D array of memory cells where it depicts a part of an array of 3D NAND flash memory structure. 
           [0016]      FIG. 11  shows a prior art where it depicts a part of a vertical gate NAND flash memory in which 3D memory cells are implemented in a 3D array of memory cells. 
           [0017]      FIG. 12  shows an example embodiment of implementation of the invention in a 3D memory cell implemented in a 3D array of memory cells where it depicts a part of an array of 3D NAND flash memory structure. 
           [0018]      FIG. 13  shows an example embodiment of implementation of the invention where it depicts a part of an array of 3D NAND flash memory structure. 
           [0019]      FIG. 14  shows an example embodiment of implementation of invention in an AlGaN/GaN High Electron Mobility Transistor. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0020]    Different examples will be described in details that represent some example embodiments of the presented invention. However the technical and structural descriptions presented herein are representative for the purposes of describing the presented invention, the described invention may be embodied in many alternate forms and should not be limited to the example embodiments described herein. 
         [0021]    The described examples can be modified in various alternative forms. For example, the thickness and dimensions of the regions in drawings may be exaggerated for clarity. There is no intention to limit the invention to the particular forms disclosed. However, examples are used to describe the invention and to cover some modifications and alternatives within the scopes of the presented invention. 
         [0022]    The spatially relative terms used here such as “underneath”, “below” and “above” are for the ease of description and to show the relationship between an element and another one in the figures. If the device in the figure is turned over, elements described as “underneath” or “below” other elements would then be “above” other elements. Therefore, for example, the term “underneath” can represent an orientation which is below as well as above. If the device is rotated, the spatially relative terms used herein should be interpreted accordingly. 
         [0023]    Unless otherwise stated, variations of the shapes of the figures as a result of, for example, manufacturing techniques and tolerances are expected. For instance, a doped rectangle region with a specified doping concentration in illustrations may have rounded or curved features or gradient at its edges rather than an abrupt change from a region to another region. Therefore, the regions illustrated in figures are schematic and their shapes do not necessarily show the actual shape of the fabricated device. Unless otherwise stated, there is no intention to limit the invention to the values (such as dimensions, bias voltages and doping concentrations) used to describe the example embodiments. These values are selected to describe the related characteristics for a better understanding of the presented invention. Unless otherwise stated, the terms used herein have the same meaning as commonly understood by someone with ordinary skills in the invention field. 
         [0024]    Throughout this document, the whole device structure in provided example embodiments may not be presented for the sake of simplicity. This can be understood by someone with ordinary expertise in the field of invention. For example, when showing a transistor, the gate spacers may not be depicted. In such cases, any new or well-known designs for the un-shown parts are expected. Therefore, it should be understood that the provided example embodiments may just have illustrations that are mainly intended to show the scope of the invention and different designs of other parts of the device are expected. 
         [0025]    It is generally known that the electric field is stronger near the sharp edges of the biased conductors. If the gate of a memory cell is designed in a way such that at least one of its edges in contact with a dielectric has an angle less than 88 degrees, a smaller gate voltage may be required to move the charges from the channel into the charge trapping layer underneath the gate (and vise versa) which may improve the read and write speed. In addition, in FinFETs and Tri-Gate transistors, for example, if the sharp gate edges were implemented, a smaller change in the gate bias may be required to accumulate the charge in the channel under the gate and turn ON the device. 
         [0026]    An example embodiment of this invention is a memory cell having a non-insulating region, said memory cell has a gate which is not in physical contact with the said region, wherein at least one dielectric material is implemented in an area between the said gate and the said region, wherein at least two of gate surfaces intersect each other in a gate edge, wherein the said gate edge is in contact with a dielectric material in at least two points, wherein the said gate surfaces form an internal gate angle of less than 88 degrees, wherein dielectric charge trapping structures are implemented in an area between the said gate and the said region. 
         [0027]      FIG. 1  shows a prior art wherein a typical planar memory cell with Oxide/Nitride/Oxide charge trapping structure is depicted. Here,  1  is gate,  2  and  4  are oxide layers,  3  is a nitride charge trapping layer,  5  is the n+ source region,  6  is the n+ drain region and  7  is the p-type substrate. This figure depicts a memory cell having a non-insulating region  7 , said memory cell has a gate  1  which is not in physical contact with region  7 , wherein at least one dielectric material ( 2 ,  3  or  4 ) is implemented in an area between the said gate  1  and the said region  7 , wherein non of gate surfaces that intersect each other in a gate edge which is in contact with a dielectric material  2  in at least two points form an internal gate angle of less than 88 degrees. 
         [0028]      FIG. 2  shows an example embodiment of implementation of the invention in a planar memory cell with Oxide/Nitride/Oxide charge trapping structure. Here,  1  is gate,  2  and  4  are oxide layers,  3  is a nitride charge trapping layer,  5  is the n+ source region,  6  is the n+ drain region,  7  is the p-type substrate,  8  is the gate surface at the interface of the gate and oxide  2 ,  9  is a gate surface and  10  is a gate edge. This figure depicts a memory cell having a non-insulating region  7 , said memory cell has a gate  1  which is not in physical contact with the said region, wherein at least one dielectric material ( 2 ,  3  or  4 ) is implemented in an area between the said gate and the said region, wherein at least two of gate surfaces ( 8  and  9 ) intersect each other in a gate edge  10 , wherein the said gate edge is in contact with a dielectric material  2  in at least two points ( 11  and  12 ), wherein the said gate surfaces form an internal gate angle α of less than 88 degrees, wherein dielectric charge trapping structures ( 2 ,  3  and  4 ) are implemented in an area between the said gate and the said region. Here, an Oxide/Nitride/Oxide (ONO) stack ( 2 ,  3  and  4 ) is implemented in an area between the said gate and the said region, wherein the said nitride layer  3  acts as a charge trapping layer. 
         [0029]      FIG. 3  shows a prior art wherein a tri-gate memory cell with Oxide/Nitride/Oxide charge trapping structure is depicted. Here,  1  is substrate,  2  is a semiconductor Fin,  3  and  4  are insulators,  5  is gate,  6  and  8  are oxide layers and  7  is a nitride charge trapping layer. In an example embodiment, the portions of the Fin which are not underneath the gate can be n+ doped where one side can act as the source region and the other side can act as the drain region. This figure depicts a memory cell having a Fin  2 , wherein the said Fin is made of a non-insulating material, said device has a gate  5  which is not in physical contact with the said Fin, wherein non of gate surfaces that intersect each other in a gate edge which is in contact with a dielectric material  6  in at least two points form an internal gate angle of less than 88 degrees. 
         [0030]      FIG. 4  shows an example embodiment of implementation of the invention in a memory cell having a Fin. Here,  1  is substrate,  2  is a semiconductor Fin,  3  and  4  are insulators,  5  is gate,  6  and  8  are oxide layers,  7  is a nitride charge trapping layer,  9  is a gate surface which is at the interface of the gate  5  and dielectric  6 , and  10  is a sidewall surface of the gate. This figure depicts a memory cell having a Fin  2 , wherein the said Fin is made of a non-insulating material, said device has a gate  5  which is not in physical contact with the said Fin, wherein at least two of gate surfaces ( 9  and  10 ) intersect each other in a gate edge, wherein the said gate edge is in contact with a dielectric material  6  in at least two points ( 11  and  12 ), wherein the said gate surfaces form an internal gate angle α of less than 88 degrees. In an example embodiment, the portions of the Fin which are not underneath the gate can be n+ doped where one side can act as the source region and the other side can act as the drain region. In another example embodiment of the invention, instead of the Oxide/Nitride/Oxide layers ( 6 ,  7  and  8 ), a gate dielectric may be implemented and the device will be a FinFET or a tri-gate transistor. 
         [0031]      FIG. 5  shows an example embodiment of implementation of the invention in a tri-gate memory cell. Here,  1  is substrate,  2  is a semiconductor Fin,  3  and  4  are insulators,  5  is gate,  6  and  8  are oxide layers,  7  is a nitride charge trapping layer,  9  is a gate surface which is at the interface of the gate  5  and dielectric  6 , and  10  is a sidewall surface of the gate. In this figure, a first and a second plane are drawn perpendicular to the device substrate plane  19 , wherein the said first and second planes are parallel with respect to each other, wherein each of the said first and second planes are in contact with the said Fin in at least two points ( 15 ,  16 ,  17  and  14 ), wherein the said Fin  2  completely lies in between the said first and second planes, wherein a third and a fourth plane are drawn perpendicular to the device substrate plane  19 , wherein the said third and fourth planes are parallel with respect to each other, wherein each of the said third and fourth planes are in contact with the said gate in at least two points ( 11 ,  12 ,  13  and  14 ), wherein the said gate completely lies in between the said third and fourth planes, wherein the said first and third planes have an angle β of less than 88 degrees. In  FIG. 5 , α=β. 
         [0032]      FIG. 6  shows the relative positions of the gate and Fin masks during a lithography mask alignment process in a conventional method to fabricate the device shown in  FIG. 3 . In this method, a lithography gate mask is used to form the gate, a lithography Fin mask is used to form the Fin, wherein an edge  1  of an opening in the said Fin mask defines a sidewall of the said Fin, wherein an edge  2  of an opening in the said gate mask defines a sidewall of the said gate, wherein the said edge of the opening in the gate mask is positioned at an angle of 90 degrees relative to the position of the said edge of the opening in the Fin mask in a lithography mask alignment process. In  FIG. 6 , the opening in the Fin mask is shown by the solid lines and the opening of the gate mask is shown by dashed lines. 
         [0033]      FIG. 7  shows the relative positions of the gate and Fin masks during a lithography mask alignment process in a method to fabricate the device shown in  FIG. 4 . In this method, a lithography gate mask is used to form the said gate, wherein a lithography Fin mask is used to form the said Fin, wherein an edge  1  of an opening in the said Fin mask defines a sidewall of the said Fin, wherein an edge  2  of an opening in the said gate mask defines a sidewall of the said gate, wherein the said edge of the opening in the gate mask is positioned at an angle α of less than 88 degrees relative to the position of the said edge of the opening in the Fin mask in a lithography mask alignment process. In  FIG. 7 , the opening in the Fin mask is shown by the solid lines and the opening of the gate mask is shown by dashed lines. 
         [0034]      FIG. 8  shows an example embodiment of implementation of the invention in a memory cell having a Fin. Here,  1  is substrate,  2  is a semiconductor Fin,  3  and  4  are insulators,  5  is gate,  6  and  8  are oxide layers,  7  is a nitride charge trapping layer,  9  is a surface of the gate and  10  is a gate surface which is at the interface of the gate  5  and dielectric  6 . This figure depicts a memory cell having a Fin  2 , wherein the said Fin is made of a non-insulating material, said device has a gate  5  which is not in physical contact with the said Fin, wherein at least two of gate surfaces ( 9  and  10 ) intersect each other in a gate edge, wherein the said gate edge is in contact with a dielectric material  6  in at least two points ( 11  and  12 ), wherein the said gate surfaces form an internal gate angle of less than 88 degrees. In an example embodiment of the invention, instead of the Oxide/Nitride/Oxide layers ( 6 ,  7  and  8 ), a gate dielectric may be implemented and the device will be a FinFET or a tri-gate transistor. In other example embodiments, High-K dielectric materials may be implemented instead of layers  6 ,  7  and  8 . 
         [0035]    This invention can also be applied to a 3D memory cell having a non-insulating region wherein the said 3D memory cell has a gate which is not in physical contact with the said region, wherein at least one dielectric material is implemented in an area between the said gate and the said region, wherein at least two of gate surfaces intersect each other in a gate edge, wherein the said gate edge is in contact with a dielectric material in at least two points, wherein the said gate surfaces form an internal gate angle of less than 88 degrees. 
         [0036]    FIG.  9 . a  shows a prior art where it depicts a part of a vertical channel NAND flash memory structure in which 3D memory cells are implemented in a 3D array of memory cells. Here, the channel is made of a non-insulating material such as crystalline silicon or poly silicon. An Oxide-Nitride-Oxide (ONO) layer is implemented in between the channel and the gates. FIG.  9 . b  shows a view of FIG.  9 . a  from View-1 side, FIG.  9 . c  shows a view of FIG.  9 . a  from View-2 side and FIG.  9 . d  depicts a zoomed-in view of FIG.  9 . a  from View-3 side. An oxide may be implemented in the empty spaces between the gates (not shown in  FIG. 9 ). In this device, all gate surfaces that intersect each other in a gate edge that is in contact with a dielectric material in at least two points, form an internal gate angle of 90 degrees. Some other prior arts are described in U.S. Pat. No. 8,445,347, US 2009/0267128, US 2009/0310415 and US 2012/0032250. In all of these devices, all gate surfaces that intersect each other in a gate edge that is in contact with a dielectric material in at least two points, form an internal gate angle of 90 degrees. 
         [0037]      FIG. 10  shows an example embodiment of implementation of the invention in a 3D memory cell implemented in a 3D array of memory cells where it depicts a part of an array of 3D NAND flash memory structure. Here, the channel is made of a non-insulating material such as crystalline silicon or poly silicon. An Oxide-Nitride-Oxide (ONO) layer is implemented in between the channel and the gates. FIG.  10 . b  shows a view of FIG.  10 . a  from View-1 side, FIG.  10 . c  shows a view of FIG.  10 . a  from View-2 side and FIG.  10 . d  depicts a zoomed-in view of FIG.  10 . a  from View-3 side.  2  is a gate surface which is at the interface of the gate and the outer oxide of ONO and  1  is another gate surface. Here, at least two of gate surfaces ( 1  and  2 ) intersect each other in a gate edge, wherein the said gate edge is in contact with a dielectric material (the outer oxide of ONO) in at least two points, wherein the said gate surfaces form an internal gate angle of less than 88 degrees. An oxide may be implemented in the empty spaces between the gates (not shown in  FIG. 10 ). In other example embodiments, a high-k dielectric material may be implemented between the gate and ONO. 
         [0038]    FIG.  11 . a  shows a prior art where it depicts a part of a vertical gate NAND flash memory in which 3D memory cells are implemented in a 3D array of memory cells. Here, the channel is made of a non-insulating material such as crystalline silicon or poly silicon. An Oxide-Nitride-Oxide (ONO) layer is implemented in between the channel and the gates. FIG.  11 . b  shows a view of FIG.  11 . a  from View-1 side, FIG.  11 . c  shows a view of FIG.  11 . a  from View-2 side and FIG.  11 . d  depicts a zoomed-in view of FIG.  11 . a  from View-3 side. An oxide may be implemented in the empty spaces between the gates (not shown in  FIG. 11 ). In this device, all gate surfaces that intersect each other in a gate edge that is in contact with a dielectric material in at least two points, form an internal gate angle of 90 degrees. 
         [0039]      FIG. 12  shows an example embodiment of implementation of the invention in a 3D memory cell implemented in a 3D array of memory cells where it depicts a part of an array of 3D NAND flash memory structure. Here, the channel is made of a non-insulating material such as crystalline silicon or poly silicon. An Oxide-Nitride-Oxide (ONO) layer is implemented in between the channel and the gates. FIG.  12 . b  shows a view of FIG.  12 . a  from View-1 side, FIG.  12 . c  shows a view of FIG.  12 . a  from View-2 side and FIG.  12 . d  depicts a zoomed-in view of FIG.  12 . a  from View-3 side.  2  is a gate surface which is at the interface of the gate and the outer oxide of ONO and  1  is another gate surface. Here, at least two of gate surfaces ( 1  and  2 ) intersect each other in a gate edge, wherein the said gate edge is in contact with a dielectric material (the outer oxide of ONO) in at least two points, wherein the said gate surfaces form an internal gate angle of less than 88 degrees. An oxide may be implemented in the empty spaces between the gates (not shown in  FIG. 12 ). In other example embodiments, a high-k dielectric material may be implemented between the gate and ONO. 
         [0040]    This invention can also be implemented in a 3D memory cell with a non-insulating region wherein the said 3D memory cell is implemented in a 3D array of memory cells in a vertical gate 3D NAND flash memory structure. In this case, a first and a second plane can be drawn perpendicular to the device substrate plane, wherein the said first and second planes are parallel with respect to each other, wherein each of the said first and second planes are in contact with the said region in at least two points, wherein the said region completely lies in between the said first and second planes, wherein a third and a fourth plane can be drawn perpendicular to the device substrate plane, wherein the said third and fourth planes are parallel with respect to each other, wherein each of the said third and fourth planes are in contact with the said gate in at least two points, wherein the said gate completely lies in between the said third and fourth planes, wherein the said first and third planes have an angle of less than 88 degrees.  FIG. 13  shows an example embodiment where it depicts a part of an array of 3D NAND flash memory structure. Here, a 3D memory cell with a non-insulating region (channel  9 ) is implemented in a 3D array of memory cells in a vertical gate 3D NAND flash memory structure. In this case, a first and a second plane are drawn perpendicular to the device substrate plane, wherein the said first and second planes are parallel with respect to each other, wherein each of the said first and second planes are in contact with the said region  9  in at least two points ( 1 ,  2 ,  3  and  4 ), wherein the said region  9  completely lies in between the said first and second planes, wherein a third and a fourth plane are drawn perpendicular to the device substrate plane, wherein the said third and fourth planes are parallel with respect to each other, wherein each of the said third and fourth planes are in contact with the said gate in at least two points ( 5 ,  6 ,  7  and  8 ), wherein the said gate completely lies in between the said third and fourth planes, wherein the said first and third planes have an angle α of less than 88 degrees. In this figure,  10  is ONO. 
         [0041]    This invention can also be implemented in a semiconductor device with a gate, wherein the said device has a compound semiconductor material region. In this case, at least two of gate surfaces intersect each other in a gate edge, wherein the said gate edge is in contact with a gate dielectric or a compound semiconductor material in at least two points, wherein the said gate surfaces form an internal gate angle of less than 88 degrees.  FIG. 14  shows an example embodiment of implementation of the invention in an AlGaN/GaN High Electron Mobility Transistor (HEMT). In this figure,  1  is a gate,  2  is AlGaN,  3  is GaN,  4  is a source contact,  5  is a drain contact,  6  is a gate surface,  7  is a gate surface which is at the interface of the gate and AlGaN  2 , and  8  is a gate edge. This figure shows a semiconductor device with a gate  1 , wherein the said device has a compound semiconductor material region ( 2  or  3 ). In this device, at least two of gate surfaces ( 6  and  7 ) intersect each other in a gate edge  8 , wherein the said gate edge is in contact with a gate dielectric or a compound semiconductor material  2  in at least two points ( 9  and  10 ), wherein the said gate surfaces form an internal gate angle α of less than 88 degrees. In another example embodiment,  2  is AlGaAs and  3  is GaAs. In another example embodiment, a gate dielectric may be implemented in between the gate  1  and region  2 .