Abstract:
A surface mount area-array integrated circuit package is disclosed. The package consists of a package substrate having conductive vias and internal and external conductive traces, a semiconductor die electrically and mechanically connected to the top surface of package substrate, an area-array of conductive surface mount terminations electrically and mechanically connected to the bottom of the package substrate, and at least one adhesive mass. The at least one adhesive mass is located on the bottom of the package substrate and replaces the conductive terminations in the area(s) where the joint strain energy density is calculated to be the greatest. When mounted on a substrate, the at least one adhesive mass adheres the package to the substrate. Increased mechanical and electrical reliability is thus achieved.

Description:
FIELD OF THE INVENTION  
         [1]    1. This invention relates to integrated circuit packages in general, and specifically to surface mount area-array packages.  
         BACKGROUND OF THE INVENTION  
         [2]    2. Advances in the design of integrated circuit dies have created a demand for integrated circuit package designs which can accommodate a large number of interconnections between the package and the substrate without becoming excessively large. An important requirement of these high density integrated circuit package designs is that they maintain a low interconnection failure rate despite the large number of interconnections.  
           [3]    3. One such high density package design is a surface mount area-array package. This package does not employ formed metal leads. Instead, interconnection between the package and the substrate is provided by an array of metal alloy or electrically conductive polymer based compound terminations which form joints to mechanically and electrically connect the package and the substrate  
           [4]    4. One type of such package is a plastic ball grid array (PBGA) package. The substrate of the package is composed of a laminated glass fibre resin structure which has metal traces on the outside and between the laminated layers and vias to interconnect the traces. An integrated circuit die is positioned on top of or adjacent the top of the package substrate and electrically connected to the traces. Through the vias, these traces connect to solder balls typically arrayed in regular concentric rings, usually square in shape, upon the bottom of the PBGA package. The integrated circuit die and the top of the substrate are encapsulated in a molded plastic for mechanical and environmental protection. The PBGA package is mounted upon a substrate employing known procedures such as reflow.  
           [5]    5. It was known that the solder ball interconnections beneath the integrated circuit die were the first to fail in operation when the PBGA was mounted upon the most commonly used substrate, namely a printed circuit board (PCB) formed with a laminated glass fibre resin based material. A prior solution for attempting to increase electrical reliability was to remove the interconnections which were beneath the die, know in the art as depopulating solder balls. However, this decreases the number of solder ball joints attaching the package to the substrate. The mechanical problem created, of not having sufficient attachment of the package to the substrate, is particularly significant in chip-scale packages (CSP&#39;s). A CSP is any package in which the package is only slightly larger than the die.  
           [6]    6. In  Factors Influencing Fatigue Life of Area-Array Solder Joints , by R. Katchmar, E. Goulet and J. Laliberte, presented at 1996 ISHM in Minneapolis, the authors described a process by which they developed a formula for predicting the incremental spring stiffness ΔK i  of the i th  ring of solder balls from the centre of the package. As a result of applying this formula to PBGAs mounted on printed circuit boards, it was theorized that the solder balls under the die should be retained, rather than removed, in order to extend the life of the remaining solder ball connections. However, the formulas published in the paper contained errors; in particular, the formula for calculating ΔK i  was incorrect. Also, no practical solutions have been proposed and the paper is silent with regard to ceramic column grid array (CCGA) packages and CSP&#39;s.  
         SUMMARY OF THE INVENTION  
         [7]    7. It is an object of the present invention to provide an improved integrated circuit package and method of connecting an integrated circuit package to a substrate in which one or more of the disadvantages of the prior art is obviated or mitigated.  
           [8]    8. Therefore, the invention may be summarized according to a first broad aspect as an integrated circuit package for mounting on a substrate of local coefficient of thermal expansion α s  comprising: a package substrate of local coefficient of thermal expansion α pkg ; a semiconductor die mounted either on or adjacent a top surface of the package substrate and electrically connected thereto; an array of conductive surface mount terminations of finite thickness mounted on a bottom surface of the package substrate at least some of which are connected through the package substrate to the semiconductor die; the terminations being arranged in rings i around a neutral point of the package; each of the rings being a distance DNP i  from the neutral point of the package; each of the rings having a number of terminations n i ; each ring having a termination pitch P; the terminations having a modulus of elasticity E t  and a structural thickness h t ; the package having a modulus of elasticity E pkg  and a structural thickness h pkg ; successive rings having a change in the distance from the neutral point of the package ΔDNP; each of the rings cycling through a temperature range ΔT i  during operation; and at least one adhesive mass; the at least one adhesive mass being located on the bottom of the package substrate in the area(s) where the terminations when mounted upon the substrate to form joints would have highest joint strain energy density W Gi  as calculated by the equations  
             W   Gi   =k   i   {DNP   i (α s −α pkg ) i   ΔT   i } 2    
             k   i =1/4 n   i Σ(1 /ΔK   j ) j=1,i    
             ΔK   j =( P/ΔDNP ) j /{1/( Eh ) t +1/( Eh ) pkg } j    
           [9]    9. such that when mounted upon the substrate the at least one adhesive mass will co-operate with the package substrate and the substrate to adhere the package substrate and the substrate to each other.  
           [10]    10. According to another aspect of the present invention, there is provided an integrated circuit package for mounting on a substrate comprising: a package substrate; a semiconductor die mounted either on or adjacent a top surface of the package substrate and electrically connected thereto; an array of conductive surface mount terminations of finite thickness mounted on a bottom surface of the plastic package substrate at least some of which are connected through the package substrate to the semiconductor die; and at least one adhesive mass; the at least one adhesive mass being located on the bottom of the package substrate such that when mounted upon the substrate the at least one adhesive mass will co-operate with the package substrate and the substrate to adhere the package substrate and the substrate to each other.  
           [11]    11. According to a further aspect of the present invention, there is provided an integrated circuit package for mounting on a substrate comprising: a plastic package substrate having a coefficient of thermal expansion substantially the same as the coefficient of thermal expansion of the substrate; a semiconductor die mounted either on or adjacent a top surface of the plastic package substrate and electrically connected thereto; an array of conductive surface mount terminations of finite thickness mounted on a bottom surface of the plastic package substrate at least some of which are connected through the plastic package substrate to the semiconductor die; and an adhesive mass; the adhesive mass being located on the bottom of the plastic package substrate substantially beneath the semiconductor die such that when mounted upon the substrate the adhesive mass will co-operate with the plastic package substrate and the substrate to adhere the package substrate and the substrate to each other.  
           [12]    12. According to a further aspect of the present invention, there is provided an integrated circuit package for mounting on a substrate comprising: a ceramic package substrate having a coefficient of thermal expansion substantially lower than the coefficient of thermal expansion of the substrate; a semiconductor die mounted either on or adjacent a top surface of the ceramic package substrate and electrically connected thereto; an array of conductive surface mount terminations of finite thickness mounted on a bottom surface of the substrate at least some of which are connected through the substrate to the semiconductor die; a plurality of adhesive masses; the adhesive masses being located on the bottom of the ceramic package substrate at the corners of the ceramic package substrate such that when mounted upon the substrate the adhesive masses will cooperate with the ceramic package substrate and the substrate to adhere the ceramic package substrate and the substrate to each other.  
           [13]    13. According to yet another aspect, there is provided a method of mounting an integrated circuit package on a substrate for electrical connection of an array of conductive surface mount terminations on the package to the substrate comprising: applying an adhesive mass to a bottom surface of the package; aligning and attaching the array of conductive surface mount terminations and the adhesive mass to the substrate; and fixing the adhesive mass.  
           [14]    14. According to a still further aspect, there is provided a method of mounting on a substrate a plastic ball grid array package having a package substrate carrying a semiconductor die, the package substrate having a coefficient of thermal expansion substantially the same as the coefficient of thermal expansion of the substrate, the method comprising: providing the plastic ball grid array package with a plurality of solder balls on a bottom surface of the package substrate at locations other than under the semiconductor die; providing the plastic ball grid array package with a solderable pad on the bottom surface of the package substrate under the semiconductor die; providing the substrate with a solderable pad on a top surface under the area where the semiconductor die will be positioned; applying a solder mass, substantially equal in thickness to the solder balls, on the pad on the plastic ball grid array; applying a flux means to the substrate; aligning and placing the plastic ball grid array package on the substrate; and reflowing the solder.  
           [15]    15. According to another aspect, there is provided a method of mounting on a substrate a plastic ball grid array package having a package substrate carrying a semiconductor die, the package substrate having a coefficient of thermal expansion substantially the same as the coefficient of thermal expansion of the substrate, the method comprising: providing the plastic ball grid array package with a plurality of solder balls on a bottom surface of the package substrate at locations other than under the semiconductor die; applying a flux means to the substrate; aligning and placing the plastic ball grid array package on the substrate; reflowing the solder; injecting an adhesive plastic mass between the package substrate and the substrate under the area where the semiconductor die is located; curing the adhesive plastic mass.  
           [16]    16. According to another aspect, there is provided a method of mounting on a substrate a plastic ball grid array package having a package substrate carrying a semiconductor die, the package substrate having a coefficient of thermal expansion substantially the same as the coefficient of thermal expansion of the substrate, the method comprising: providing the plastic ball grid array package with a plurality of solder balls on a bottom surface of the package substrate; applying a flux means to the substrate; aligning and placing the plastic ball grid array package on the substrate; reflowing the solder; injecting an non-electrically conductive adhesive plastic mass between the package substrate and the substrate; curing the adhesive plastic mass.  
           [17]    17. According to a still further aspect, there is provided a method of mounting on a substrate a ceramic surface mount area-array package having a package substrate carrying a semiconductor die, the package substrate having a coefficient of thermal expansion substantially lower than the coefficient of thermal expansion of the substrate, the method comprising: providing the ceramic surface mount area-array package with an array of solderable surface mount terminations on a bottom surface of the package substrate at locations other than the corners of the package substrate; providing the ceramic surface mount area-array package with solderable pads on the bottom surface of the package substrate at the corners of the package substrate; providing the substrate with a solderable pads on a top surface under the area where the corners of the package substrate will be positioned; applying solder masses, substantially equal in thickness to the solderable surface mount terminations, on the pads on the ceramic ball grid array; applying a flux means to the substrate; aligning and placing the ceramic surface mount area-array package on the substrate; and reflowing the solder.  
           [18]    18. According to yet another aspect, there is provided a method of mounting on a substrate a ceramic surface mount area-array package having a package substrate carrying a semiconductor die, the package substrate having a coefficient of thermal expansion substantially lower than the coefficient of thermal expansion of the substrate, the method comprising: providing the ceramic surface mount area-array package with an array of solderable surface mount terminations on a bottom surface of the package substrate at locations other than the corners of the package substrate; applying a flux means to the substrate; aligning and placing the ceramic surface mount area-array package on the substrate; reflowing the solder; injecting adhesive plastic masses between the package substrate and the substrate under the areas where the corners of the package substrate will be positioned; curing the adhesive plastic masses.  
           [19]    19. According to yet another aspect, there is provided an integrated circuit package for mounting on a substrate comprising: a package substrate; a semiconductor die mounted either on or adjacent a top surface of the package substrate and electrically connected thereto; an array of conductive surface mount terminations of finite thickness mounted on a bottom surface of the package substrate at least some of which are connected through the package substrate to the semiconductor die; and at least one adhesive mass; the at least one adhesive mass being located on the bottom of the package substrate in the area(s) where the terminations when mounted upon the substrate to form joints would have highest joint strain energy density as calculated by numerical methods such that when mounted upon the substrate the at least one adhesive mass will co-operate with the package substrate and the substrate to adhere the package substrate and the substrate to each other.  
           [20]    20. An advantage of this invention is that it mechanically stabilizes the area-array package from handling and bending stresses of the substrate during installation.  
           [21]    21. Another advantage of this invention is that it makes the assembly more robust to heat-sink attachment forces.  
           [22]    22. Yet another advantage is that the invention provides for an alternative cooling path into the substrate, since it directly couples the device package to the substrate which may act as a heat sink.  
           [23]    23. A further advantage of this invention is that it increases the other solder joint fatigue life due to temperature cycling of environmental or equipment temperature.  
           [24]    24. Finally, the invention provides for easy manufacture as the solder mass is concurrently soldered or unsoldered with all other joints.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [25]    25. Preferred embodiments of this invention will now be described with reference to the attached drawings in which: FIG. 1 is a bottom view of a conventional PBGA package with the dimensions used in the strain energy calculations indicated. FIG. 2 is a perspective view of a PBGA package prior to mounting on a substrate in accordance with the present invention; FIG. 3 is a bottom view of a PBGA package of FIG. 2 prior to mounting on a substrate in accordance with the present invention; FIG. 4 is a cross-sectional view of the PBGA package of FIG. 2 mounted on a substrate in accordance with the present invention; FIGS.  5  and  6  are cross-sectional views of other PBGA embodiments of the present invention; and FIG. 7 is a cross-sectional view of a CCGA package mounted upon a substrate in accordance with the present invention.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [26]    26. This invention employs an adhesive mass to mechanically connect a surface mount area-array package and substrate in the locations where the joint strain energy density, if joints were present, would be greatest. Joint strain energy density W Gi  of a concentric ring of surface mount area-array joints is governed by the equation:  
           W   Gi   =k   i   {DNP   i (α s −α pkg ) i   ΔT   i } 2    
         [27]    27. where:  
         [28]    28. α s  is the local coefficient of thermal expansion of the substrate;  
         [29]    29. α pkg  is the local coefficient of thermal expansion of the package;  
         [30]    30. DNP i  is the distance to neutral point, i.e. point of no lateral displacements, of the joints; in a symmetrical package construction as shown in FIG. 1, the neutral point is generally the centre of the package (intersection of the centerlines identified by _) and the DNP i  is measured from there;  
         [31]    31. ΔT i  is the temperature excursion through which the i th  ring cycles;  
         [32]    32. i is the i th  ring of joints from the neutral point of the package;  
         [33]    33. k i  is the cumulative spring stiffness of the i th  ring of joints defined by  
           k   i =1/4 n   i Σ(1 /ΔK   j ) j=1,i    
         [34]    34. where:  
         [35]    35. n is the number of joints in the i th  ring  
         [36]    36. ΔK j  is the incremental spring stiffness for a single ring j defined by  
         Δ K   j =( P/ΔDNP ) j /{1/( Eh ) t +1/( Eh ) pkg } j    
         [37]    37. where:  
         [38]    38. P is the joint pitch within the ring, as shown in FIG. 1  
         [39]    39. ΔDNP is the change in the distance from the neutral point of the package between successive rings  
         [40]    40. E is the modulus of elasticity  
         [41]    41. h is the structural thickness  
         [42]    42. t  is the termination which forms a joint when mounted  
         [43]    43. pkg  is the package  
         [44]    44. Where the area-array package has an irregular array of joints, the neutral axis of the joints is no longer equivalent to the centroid of the package. In such cases, the location of the neutral axis must be determined before the above equation is applied. This calculation is known in the art and consists of first determining the package centroid by calculating the first moment of area of the package. Then calculating the neutral axis from the centroid as the first moment of the load carrying area. The distance to neutral point is measured from this neutral axis.  
         [45]    45. Although the preferred embodiment indicates use of the preceding equation, other numerical methods, e.g. finite element analysis, may be employed to determine the area of highest strain energy density.  
         [46]    46. When an area-array package is mounted upon a PCB, the location of maximum joint strain energy density has been calculated to be near the edge of the die in PBGA packages and at the corners of CCGA packages.  
         [47]    47. FIGS.  2  to  4  depict a package  10  which includes a package substrate  12  consisting of a laminated glass fibre resin structure containing a plurality of metal traces  11  and plated vias  13  interconnecting a top surface  14  of the package substrate  12  with a bottom surface  16 . As shown in FIG. 4, a semiconductor die  18  is connected to a central location of the top surface  14 . Although wire bonding is shown in FIG. 4, other suitable methods used in the art, e.g. flip-chip or tape automated bonding (TAB), can be used to connect the semiconductor die  18  to the package substrate  12 . The package further comprises a molded body  20 , preferably made of epoxy resin, molded onto the surface of the package substrate  12  by a conventional transfer molding process.  
         [48]    48. The upper molded body  20  surrounds the semiconductor die  18 . The bottom surface  16  of the package substrate  12  has an array of conductive surface mount terminations  24 , arranged as an array of solder balls attached to solderable pads  35 , for electrical connection of the package  10  to solderable pads  37  of a substrate  28 , such as a PCB. Because the coefficient of thermal expansion is the property of the substrate which effects the joint strain energy density (see the above equations) other substrates with a coefficient of thermal expansion similar to that of a PCB may also be used. Other surface mount array interconnection styles as known in the art may be used in place of the array of solder balls. When the package is designed by applying the maximum strain energy density calculation, no solder balls are located in the area beneath the die. Instead, according to the invention, an adhesive mass, preferably a mass of eutectic solder  26 , is located directly under the die.  
         [49]    49. Wetting and thus adhesion of the solder mass  26  to the top surface  30  of substrate  28  and the bottom surface  16  of the package substrate  12  may be achieved in any one of several ways. In the preferred embodiment, both the top surface  30  of the substrate  28  and the bottom surface  16  of the package substrate  12  are provided with aligning solderable pads  32  and  34  respectively of substantially the same dimensions as the solder mass. The solderable pads  32  and  34  may either consist of one large pad or a plurality of pads covering substantially all of that portion of the substrate top surface  30  and that portion of the package substrate bottom surface  16  vertically aligned with the semiconductor die  18  when assembled, i.e. lying directly under the die  18 . When the PBGA is mounted on substrate  28  using convention pick-and-place and reflow processes, the processing steps used to bond the solder balls to the substrate, the solder mass is also reflowed and the eutectic solder bonds to both the solderable pad  34  on the substrate  28  and the solderable pad  32  on the bottom  16  of the package substrate  12 .  
         [50]    50. A method for mounting a package  10  on a substrate  28  is thus to design a package  10  having a solderable pad  32  on the bottom surface  16  of the package substrate  12  and to design a substrate  28  having a solderable pad  34  on the top surface  30  of the substrate  28 . Then place a solder mass substantially equal to the thickness of the solder balls on the solderable pad  32 , e.g., either by printing solder paste or positioning a preformed metal alloy slug and tacking it in place as with the solder balls  24  on pads  35 . Finally, apply a flux means, e.g. solder paste or liquid flux or appropriate atmosphere, to the solderable pads  34  and  37  of the substrate  28 , align and place the package  10  on the substrate, and reflow in accordance with normal industry processes.  
         [51]    51. For enhanced thermal performance, the package substrate  12  may be provided with thermal vias  36  which thermally, but not electrically, connect the bottom surface of the die  18  with the solder mass  26 .  
         [52]    52.FIG. 5 shows another embodiment of the invention also utilizing a PBGA. In FIG. 5, rather than a solid mass of solder, individual solder balls  40  are arranged between the package  10  and the substrate  28 . These solder balls  40  are placed in closer proximity to each other than the solder balls  24  which are not positioned under the die  18 . Again, either one solderable pad or a plurality of solderable pads are provided to allow adhesion of the solder to the package bottom surface  16  and the substrate top surface  30 .  
         [53]    53.FIG. 6 shows another way of arraying the solder balls  24  and  40  to achieve a closer pitch under the die  18  by designing the substrate  28  and the PBGA package to accommodate a decreasing pitch of solder balls  24  and  40  from the perimeter of the package  42  to the centre of the package  44 .  
         [54]    54. Although the preferred embodiment indicates solder as the choice of adhesive mass  26 , other suitable adhesives such as a thixotropic epoxy based composite or a thixotropic polymer based composite may be employed. Such adhesives are injected through an orifice  29  in the substrate after the package  10  has been mounted on the substrate  28 . The adhesive is then cured using heat, moisture, ultra violet radiation, a catalyst or other curing means. Depending on their known adhesive properties relative to the solder balls, such materials may require that a solder mask or bare laminate and not solderable pads  32  and  34  be provided on the surfaces of the package and the substrate aligned with the die  18 . Also, the joints may be co-located with the adhesive in this configuration and be active where the adhesive is not electrically conductive.  
         [55]    55.FIG. 7 shows a CCGA package  10 ′. The structure of the CCGA package is essentially the same as the PBGA package described with reference to FIGS.  2  to  4  except that the package substrate  12 ′ is made of a ceramic material having a coefficient of thermal expansion substantially lower than that of the glass fibre resin structure of substrate  12 . Also, the semiconductor die  18  may by surrounded by a lid  46  rather then a molded body. In addition, solder balls are replaced with non-eutectic solder columns  24 ′ and the arrangement of the solder columns on the bottom surface  16  of the package is different. According to the invention, solder masses  47  are placed at the corners of the package and solder columns are arrayed under the remainder of the package. Processing of these solder masses is the same as the processing of the solder mass described with reference to the PBGA package.  
         [56]    56. As with the PBGA package, the solder masses may be replaced with other forms of adhesive such as a thixotropic epoxy or polymer based compound.  
         [57]    57. Although placing the adhesive mass in the area indicated by the maximum strain energy calculation is preferred, positioning the adhesive mass elsewhere will provide some mechanical improvement. Thus, the adhesive mass may be positioned elsewhere for mechanical attachment independent of applying the maximum strain energy density calculation.  
         [58]    58. Similarly, substrates with a coefficient of thermal expansion different from that of a PCB may be used with PBGAs and CCGAs but the advantage of placing the adhesive mass in the region of largest strain energy density may not be realized.  
         [59]    59. While the illustrated embodiments show the use of an adhesive mass primarily to improve the integrity of the mechanical connection between the package and the substrate, the adhesive mass could be used primarily for thermal management, i.e. to improve heat flow from the package to a heat sink. In such a case, the exact location of the adhesive mass may not be critical as improvement to mechanical stability is secondary. Of course, the adhesive mass would have to be a suitable highly thermally conductive material.  
         [60]    60. While the preferred embodiment, in addition to several alternative forms of the invention, has been described and illustrated, it will be apparent to one skilled in the art that further variations in the design may be made. The scope of the invention, therefore, is only to be limited by the claims appended hereto.