Abstract:
A CMOS-based voltage signal amplifier is particularly useful for amplifying signals from a single photodiode, or a small set of photodiodes, within a large photosensitive imaging device. When the imaging device reads out image signals from a large number of photodiodes, each amplifier is selected for operation only within a very brief time window when the particular photodiode associated therewith is reading out. The amplifier of the present design is suitable for rapid power-up and power-down when it is selected and deselected.

Description:
The following U.S. patent is hereby incorporated by reference: U.S. Pat. No. 5,493,423, “Resettable Pixel Amplifier for an Image Sensor Array”, assigned to the Assignee hereof. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to an image sensor array, such as found, for example, in digital scanners, copiers, and facsimile machines. More particularly, the present invention relates to a selectable amplifier which can be associated with at least one individual photosensor in such a sensor array. 
     BACKGROUND OF THE INVENTION 
     Image sensor arrays typically comprise a linear array of photosensors which scan an image-bearing document and convert the microscopic image areas viewed by each photosensor to image signal charges. Following an integration time, the image signal charges are amplified and transferred to a common output line or bus through successively actuated multiplexing transistors. 
     In the scanning process, bias and reset charges are applied to each photosensor (such as a photodiode) in a predetermined time sequence during each scan cycle. In a particular embodiment of such an image sensor array, a two-stage transfer circuit is provided for transferring the image signal charges from the photodiodes. A bias charge is applied to each photodiode through a bias charge injection transistor coupled to a node between the photodiode and the input to the transfer circuit. From the transfer circuit, the image-based charges are caused to pass through an amplifier circuit, one amplifier circuit being typically provided for each photodiode, or at least to each RGB-color triplet of color-sensitive photodiodes. 
     During a readout of the image signals along an array of photodiodes, it is desirable that the individual amplifiers associated with each photodiode be activated only long enough to amplify the image signal being read out from a particular single photodiode; when the particular photodiode is not reading out its image based charge at the moment, it is desirable that the associated amplifier be powered down temporarily. This power-down is desirable from the perspective of lowering the total power requirements of a silicon chip which may have several hundred photodiodes and associated amplifiers thereon, as well as for other reasons. 
     The present invention is thus directed to a design of an individually-selectable amplifier which can be associated with a single photodiode or other photosensor in an image sensor array. 
     DESCRIPTION OF THE PRIOR ART 
     Bazes, “Two Novel Fully Complementary Self-Biased CMOS Differential Amplifiers,”  IEEE Journal of Solid - State Circuits , Vol. 26, No. 2, Feb. 1991, pp. 165-168, discloses designs of differential amplifiers having fully complementary configurations and which are self-biased through negative feedback. U.S. Pat. Nos. 4,857,476 and 4,958,133 by the same author show related amplifier designs. 
     U.S. Pat. No. 5,493,423, incorporated by reference above, discloses an amplifier circuit which can be associated with an individual photosensor in an image sensor array. With each cycle of passing an image signal through an amplifier, a low standby current is applied to certain transistors within the amplifier until the next signal is to be output. Critical nodes within the amplifier are caused to settle to known charge-values before each image signal is passed therethrough. 
     SUMMARY OF THE INVENTION 
     According to one aspect of the present invention, there is provided an amplifier suitable for processing image signals. An input stage includes a first differential pair including two p-devices and a second differential pair, complementary to the first differential pair, including two n-devices. A first load device supplies current to the first differential pair and a second load device supplies current to the second differential pair, the first load device and the second load device being biased at a common bias node. Self-biasing circuitry generates a bias at the bias node. Means are provided for deselecting the amplifier in response to an external signal, the deselecting means including means for grounding the bias node and means for eliminating current in the self-biasing circuitry in response to the external signal. 
     According to another aspect of the present invention, there is provided a photosensitive apparatus, comprising a set of photosensors, each photosensor outputting a voltage signal relating to an intensity of light thereon; a set of amplifiers, each amplifier in the set of amplifiers being associated with a photosensor in the set of photosensors, for amplifying a voltage signal from the photosensor; and means for sending a deselection signal to any amplifier. Each amplifier includes an input stage, the input stage having a first differential pair including two p-devices and a second differential pair, complementary to the first differential pair, including two n-devices. A first load device supplies current to the first differential pair and a second load device supplies current to the second differential pair, the first load device and the second load device being biased at a common bias node. Self-biasing circuitry generates a bias at the bias node. Means are provided for deselecting the amplifier in response to the deselection signal, the deselecting means including means for grounding the bias node and means for eliminating current in the self-biasing circuitry in response to the deselection signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic view of am image scanning array having an array of photosensor cells, each cell having a photodiode with two-stage transfer circuit and amplifier for transferring image signal charges from the photodiodes to a common output bus; 
     FIG. 2 is a schematic diagram of a basic, non-selectable amplifier circuit, as could be used in the sensor array of FIG. 1; and 
     FIG. 3 is a schematic diagram of an amplifier circuit according to the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIG. 1, there is shown the image sensor array with two stage transfer, designated generally by the numeral  10 , of the type to which the present invention is directed. Image sensor array  10  includes a chip  12  of silicon with a plurality of photosites in the form of photodiodes  14  thereon. Photodiodes  14  are in closely spaced juxtaposition with one another on chip  12  in a linear array or row  16 . Several smaller arrays such as array  10  can be abutted together end to end with one another to form a longer array, i.e., a full width or contact array, with spacing between the photodiodes inside the chip thereby maintaining photodiode pitch across the entire full width of the composite array. 
     While photodiodes  14  are shown and described herein, other photosite types such as amorphous silicon or transparent electrode MOS type photosites may be envisioned. Further, while a one dimensional sensor array having a single row  16  of photodiodes  14  is shown and described herein, a two dimensional sensor array with plural rows of photodiodes may be contemplated. 
     Each photodiode  14  has a two stage transfer circuit  20  associated therewith which together with the photodiode and an amplifier  33  form a photosite cell  15  at the array front end. In each cell  15 , the image signal charge from the photodiode  14  is amplified to bring the image signal charge to a desired potential level prior to transferring the charge to a common video output line or bus  22 . Suitable shift register and logic circuitry  24  provides timing control signals ΦPIX (with an optional complement, ΦPIX) for connecting each pixel cell  15  to bus  22  in the proper timed sequence; a shift register such as  24  typically includes a set of stages therein, each stage in this embodiment being associated with one photosite cell  15 , and thus associated with one amplifier, as can be seen as the set of ΦPIX and ΦPIX lines emerging from shift register  24 . 
     Image sensor array  10  may for example be used to raster scan a document original, and in that application, the document original and sensor array  10  are moved or stepped relative to one another in a direction (i.e., the slow scan direction) that is normally perpendicular to the linear axis of array  10 . At the same time, the array scans the document original line by line in the direction (i.e., the fast scan direction) parallel to the linear axis of the tray. The image line being scanned is illuminated and focused onto the photodiodes  14 . During an integration period, a charge is developed to each photodiode proportional to the reflectance of the image area viewed by each photodiode. The image signal charges are thereafter transferred by two stage transfer circuits  20  via amplifier  33  to output bus  22  in a predetermined step by step timed sequence. 
     FIG. 2 is a schematic view of a design of amplifier which could be used as amplifier  33  in the context of the image sensor array of FIG.  1 . The amplifier shown in FIG. 2 is conceptually similar to the “very-wide-common-mode-range differential amplifier,” or VCDA, described in the article by Bazes referenced above. Both the FIG. 2 amplifier and the Bazes design represent a CMOS differential amplifier with wide input dynamic range, which is fully complementary and entirely self-biased. Both designs ultimately derive from a combination of two “folded-cascode” differential amplifiers, each the complement of the other, as described in Bazes. The design shown in FIG. 2 is particularly useful for providing a desirably linear unity-gain amplification from zero to VDD (full power supply range). 
     In overview, the basic amplifier of FIG. 2 functions as follows. The is amplifier, generally indicated as  33 , accepts an image-based voltage signal V input  and outputs a voltage signal V output . There is provided, at V input , a differential pair of p-devices M 1 A and M 1 B. The differential pair of p-devices M 1 A and M 1 B are combined as shown with a differential pair of n-devices, M 2 A and M 2 B. The p-devices M 1 A and M 1 B share a common current source, VDD 2 , while the emitters of the n-differential pair M 2 A and M 2 B share a common ground actuable through transistor M 4 . The n-differential pair M 2 A and M 2 B is useful for providing an output V output  in the range of 2-5 volts, while the p-differential pair M 1 A, M 1 B is useful for outputting voltages in the range of 0-3 volts. With reference to the claims here inbelow, the set of complementary CMOS transistor pairs M 1 A, M 1 B, M 2 A, and M 2 B forms a folded cascode amplifier in itself and represent the “input stage” for the overall amplifier  33 . The illustrated arrangement has a larger drain-source voltage drop on the input pairs, and thus has greater dynamic range, than ordinary single transistor pair differential amplifiers. 
     Voltage sources VDD 1  and VDD 3  form balanced rails providing summing current to the two kinds of differential pairs, while the transistors M 10  and M 11  proximate to voltage source VDD 4  form a push-pull output driver stage. (The various voltage sources in the schematic, VDD 1 -VDD 4  are in fact all the same voltage source, but are differently-numbered for reference purposes.) The line connecting V output  to the gate of device M 1 A &amp; M 2 A forms the feedback loop which causes the amplifier  33  to be a unity-gain amplifier. 
     As the input voltage V input  rises from a low to high voltage, the p-type input devices M 1 A, M 1 B switch from full conduction to no conduction and the n-type devices M 2 A, M 2 B switch from no conduction to full conduction currents. In other words, the n-channel devices are inactive in the region near ground and the p-channel devices are inactive in the region near VDD. Between these extremes, both pairs are active. In the region where both pairs are on, the transconductance of the input stage is twice as big as in the regions where only one pair (of n-devices or p-devices) is on. The transconductance is proportional to the square root of the saturation drain current of the device. This makes optimal frequency compensation very difficult, because the gain-bandwidth product of an amplifier is proportional to the transconductance of its input stage. 
     The bias current to the pairs of devices M 1 A, M 1 B and M 2 A and M 2 B in the input stage is supplied by load devices M 3  and M 4 . The currents through load devices M 3  and M 4  must be identical; any differences in currents through M 3  and M 4  devices would result in extreme shifts in amplifier-bias voltages. Therefore, external biasing of load device M 3  for the p-channel pair and load device M 4  for the n-channel pair is not desirable. The self-biasing scheme is created by connecting both M 3  and M 4  to a single internal bias node, indicated as V bias  in FIG.  2 . The self-biasing of the amplifier creates a negative-feedback loop that stabilizes the bias voltages for M 3  and M 4 . 
     The current paths are formed by M 3 , M 1 A, and M 8 A or M 3 , M 1 B, and M 8 B for the p-devices, and are formed by M 5 A, M 2 A, and M 4  or M 5 B, M 2 B and M 4  for the n-devices. Precise balancing of currents through the two paths is dependent on the ratios of the devices M 6 A to M 7 A (and M 6 B to M 7 B) as well as M 5 A to M 8 A (M 5 B to M 8 B). The cascode stage formed by devices M 5 A, M 6 A, M 7 A, and M 8 A on the biasing side, and the cascode stage formed by devices M 5 B, M 6 B, M 7 B, and M 8 B on the output side are identical and complementary to each other. Each cascode stage forms a summing circuit for the currents through transistors M 1 A and M 2 A (or M 1 B and M 2 B) of the input stage. With particular reference to the claims herein below, the cascode stage, formed by M 5 A-M 8 A represents the “self-biasing circuitry” for the self-biasing amplifier, and generate the bias on V bias . Voltage developed at the node V bias  is the self-biasing voltage needed to provide the balancing of currents through the input stage. 
     The cascode stage formed by M 5 B through M 8 B drives the output buffering stage. The output stage is formed by two common-source output transistors M 10  and M 11 . In order to provide a stable operation, capacitors CM 1  and CM 2  are used for frequency compensation. The output is fed back to the inputs of devices M 1 A and M 2 A of the differential amplifier. The input signal is connected to the gates of M 1 B and M 2 B as shown in FIG.  2 . The differential amplifier output is in phase with the input signal. 
     The load devices M 3  and M 4  are biased by node V bias , and therefore quiescent current in the input stage is always present. The quiescent power consumption by the circuit must be switched off in an application where one or more of these in an array of amplifiers are selected at a time and the others are in deselected mode or powered down. In order to eliminate the current within the amplifier  33  when the amplifier  33  is in a deselected mode, the biasing node V bias  needs to be grounded. Returning to FIG. 1, it is most desirable, from the standpoint of overall power consumption of the image sensor array  10  that individual amplifiers  33  be powered up for operation only in the narrow window of time during each readout in which the particular photodiode  14  associated with a single amplifier is transferring a signal therethrough. If a typical sensor array  10  on a single chip  12  includes approximately 250 photodiodes  14 , it will be evident that the overall duty cycle of any individual amplifier  33  will be quite short in proportion to the total time of operation of the image sensor array  10 . It is thus desirable to provide an amplifier design which preserves all of the desirable characteristics of, for example, the amplifier of FIG. 2, but which also is especially suitable for rapid power-up and power-down in the context of an image sensor array. 
     FIG. 3 is a schematic showing a preferred design of an amplifier incorporating the present invention. Comparing FIG. 2 to FIG. 3, it will be noted that the FIG. 3 schematic includes all of the elements of the FIG. 2 schematic, but in addition includes certain inputs which relate to whether the amplifier  33  is being selected at a particular moment. (The areas of difference between FIG.  2  and FIG. 3 are indicated by the dotted-line boxes in FIG. 3.) It will be noted that the FIG. 3 amplifier includes, in addition to the original inputs and outputs V input  and V output , inputs for selecting the amplifier  33  as a whole: as shown in FIG. 3, there are inputs ΦPIX and ΦPIX which are complements of each other. The inputs ΦPIX and ΦPIX are readily derived from the standard suitable shift register and logic circuitry  24  such as shown in FIG.  1 . 
     It will be noted, in comparing FIG. 2 to FIG. 3, that when an input ΦPIX is high, the schematic of FIG. 3 is identical to the circuit of FIG.  2 : when ΦPIX is high, the amplifier  33  is “selected” and operates as an amplifier. Significantly, when ΦPIX is low, and by definition when ΦPIX is high, the amplifier  33  is powered down. 
     Looking at the different areas in which a high value of ΦPIX (a “deselect” signal) affects the circuit of FIG. 3, it will first be noted that a high ΦPIX will disconnect the output from any downstream circuitry, as shown at area  50 . A high value of ΦPIX will also create a channel in transistor M 14 , which has the effect of shutting off all the n-devices M 8 A, M 4 , M 8 B (area  52 ). The activation of ΦPIX at area  54  effectively removes any path between the n- and p-devices within the amplifier  33 . Another portion of the schematic of FIG. 3 which differs from FIG. 2, area  56 , has an additional VDD input, VDD 5 , which causes the amplifier  33  to match the impedance of a new signal when the amplifier  33  is next selected. 
     The purpose of the additional inputs for deselecting and reselecting the amplifier  33  is to eliminate the current from the amplifier  33  when the amplifier  33  is in a deselected mode. To accomplish this effectively, two things must happen: (1) the biasing node V bias  needs to be grounded, and (2) the current in the self-biasing portion of the amplifier must have any residual current therein eliminated. 
     At deselection of amplifier  33 , the biasing node V bias  is grounded as follows. The pair of devices in area  54 , devices M 9 A and M 9 B, form a switch with two out of phase control clocks. Similarly, devices M 9 C and M 9 D at area  56  form a switch biased as shown to allow the current to flow through in each direction. The gates of devices M 9 D and M 9 C are connected to VDD 3  and ground, respectively, so that they are conducting at all times. When the amplifier  33  is deselected, devices M 9 A and M 9 B in area  54  are turned off, and device M 14  in area  52  is turned on by the clocks ΦPIX and ΦPIX. This operation pulls down the V bias  node to ground and shuts off all n-type devices of the input stage and the output buffer stage, and therefore no current is being drawn by the circuit. The only current drawn is the leakage current through the various n-devices and the CM 1 , CM 2  capacitors. 
     Further, as mentioned above, to deselect an amplifier  33  properly, the self-biasing circuitry must have all current eliminated therefrom. In the FIG. 3 embodiment, the self-biasing circuitry, which ultimately generates the bias on V bias , is represented by the cascode stages formed by transistors M 5 A-M 8 A and M 5 B-M 8 B. Current is eliminated in these stages by activation of transistor M 14  in area  52  by a high signal ΦPIX on the base thereon. This action, as shown, shuts off all n-devices M 7 A, M 8 A, M 7 B, M 8 B in the cascode stages, and causes any current in transistors M 5 A-M 8 A and M 5 B-M 8 B to be grounded out. In this context the actions of transistors M 9 A-M 9 D are added for range and symmetry reasons: when the amplifier  33  is active or selected, device M 14  in area  52  is turned off and devices M 9 A and M 9 B are turned on by their control clocks, allowing the bias to rise to the necessary DC bias level for devices M 3  and M 4 ; input signal V input  can then be observed at the output of the amplifier. 
     In the FIG. 3 embodiment, the same complementary clock signals are shown controlling both switches M 9 A, M 9 B and M 12 , M 13 . However each switch could be controlled by a separate pair of clock signals. Device M 9 B can be removed from the circuit if the linearity of the amplifier transfer characteristic is acceptable. The clocks used for driving M 9 A and M 14  must be of opposite polarity or be generated by any two non-overlapping clocks. 
     While the invention has been described in detail with reference to specific and preferred embodiments, it will be appreciated that various modifications and variations will be apparent. All such modifications and embodiments as may occur to one skilled in the art are intended to be within the scope of the appended claims.