Abstract:
Disclosed is a multilayer electronics packaging structure, especially for use in a multi chip module. By forming an overlap of signal conductors by the respective mesh conductors, an improved shielding effect is achieved and coupling between signal conductors is reduced. By increasing the via punch pitch such that multiple wiring channels are formed between adjacent vias, wirability is improved and the number of signal distribution layers may be reduced. The new structure thus shows improved electrical properties over the state-of-the-art structures, combined with a cost reduction of about 35%.

Description:
PRIOR FOREIGN APPLICATION 
     This application claims priority from German patent application number 99125461.6 filed Dec. 21, 1999, which is hereby incorporated herein by reference in its entirety. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a novel multilayer ceramic module structure. More specifically, it relates to the design of multilayer ceramic multichip modules. 
     2. Description of Related Art 
     As VLSI circuits become more dense, there is a need in the art to have semiconductor packaging structures that can take full advantage of the density and speed provided by state of the art VLSI devices. Present day modules made of ceramic, typically multilayered ceramic modules, are normally mounted onto cards or boards, with cards or boards combined together to form the central processing unit (CPU) of a computer. The multilayer ceramic (MLC) modules typically have VLSI chips mounted on the top surface. 
     Multilayer modules are used for the packaging of electronic components, especially integrated circuit chips. Both single chip modules (SCM) and multi chip modules (MCM) are widely used. The most common type of such modules is the multilayer ceramic packaging module. In this type of module the layers consist of a ceramic or glass-ceramic material. However, other types of thickfilm technologies are known, such as glass epoxy and teflon. 
     The basic technology of multilayer modules was first described by A. J. Blodgett and D. R. Barbour, “Thermal Conduction Module: A High-Performance Multilayer Ceramic Package”, IBM Journal of Research and Development 26 (1), pp. 30-36, January 1982, and by A. J. Blodgett, “Microelectronic Packaging”, Scientific American, 249 (1), pp. 86-96, January 1983. The technology of multilayer modules is also described in “Microelectronics Packaging Handbook”, edited by R. R. Tummala and E. J. Rymaszewski, New York, 1988, especially in Chapter 7 entitled “Ceramic Packaging”, pp. 455-522. 
     As integrated circuit speeds and packaging densities increase, the importance of the packaging technology becomes increasingly significant. For example, as devices approach gigahertz speed, inductance effects in the package become more significant. Such inductance effects may arise from switching, for example, and are particularly problematic in power and ground leads. Inductance effects in the package can cause ground bounce, signal cross-talk and the like. Increasing circuit size and speed also impact the heat dissipation ability of the package. 
     Especially VLSI and ULSI chips are designed for high performance applications and are thus limited by noise. The noise is caused by a high number of simultaneously switching off-chip drivers (OCD noise) and by a high number of simultaneously switching latches and the associated logic gates (logic noise). Both noise sources impact and restrict the on-chip and off-chip performance and jeopardize the signal integrity. Both noise sources generate noise due to line-to-line coupling and due to the collapse of the voltage-ground (GND) system. It is known in the art to use on-module capacitors to stabilize the power system. Thereby a major noise reduction is achieved. 
     A multilayer ceramic fabrication process involves the formation of the green or unfired ceramic layers or sheets, the formation of the conductive paste, the screening of the conductive paste onto the green ceramic sheets and the stacking, laminating and firing of ceramic sheets into the final multilayer ceramic structure. These general processes are known in the art and are, e.g., described in the publication entitled “A Fabrciation Technique for Multilayer Ceramic Module”, H. Kaiser et al, Solid State Technology, May 1972, pp. 5-40 and the U.S. Pat. No. 2,966,719 assigned to Park. 
     The ceramic green sheet is formed by weighing out the proper portions of the ceramic powder and glass frit, and blending the particles by ball or other milling techniques. The organic binder comprising the thermoplastic resin, plasticizer and solvents is then mixed and blended with the ceramic and glass powders on a ball mill. A slurry or slip is cast into a tape form by extruding or doctor blading. The cast sheet is then allowed to be dried of the solvent constituent in the binder system. After the tape is completely dried, it is then cut into working blanks or sheets; registration holes are formed in the blanks together with the via holes which are selectively punched in the working blanks. The via holes will eventually be filled with a conductive composition to allow for electrical connections from layer to layer in the multilayer ceramics structure. 
     FIGS. 1 a  to  1   c  describe the standard MCM-MLC technology. In FIG. 1 a  the wiring scheme is described. Between ground (GND) and voltage (V 1 ) mesh planes the signal distribution layers (X, Y), also called “X/Y wiring area” are located. FIG. 1 a  shows that on a given via pitch the signal and power vias (S, P) are punched through all multilayers of the MCM. The via punch pitch is defined by the manufacturing yield. As an example for today&#39;s MCM-MLC technologies, the via punch pitch is given as 450 μm. 
     The wiring directions of the two signal distribution layers X, Y are orthogonal to each other in order to minimize vertical coupling. Only one single signal line fits between the vias, therefore this wiring technology is also called 1L/CH (one line per channel) wiring technology. 
     In FIG. 1 b  the reference planes for voltage and GND are shown. They are needed to provide the DC current, the AC return current and to shield against vertical coupling from plane pair to plane pair (e.g., X 1 /Y 1  to X 2 /Y 2  to X n /Y n , wherein X 1  . . . X n  and Y 1  . . . Y n  are successive signal wiring layers). 
     Finally, FIG. 1 c  shows the total cross-section of an MCM with all layers. The layer sequence shows 7 fan-out layers (redistribution layers RD 1 -RD 7 ) on the top embedded in voltage and GND shield layers. The fan-out layers transform the dense chip footprint into a less dense via pattern which starts at the first plane pair (X 1 , Y 1 ). The redistribution layers are followed by 13 plane pairs (13 PP, X 1 /Y 1 , . . . , X 13 /Y 13 ) of signal wiring layers, which are again embedded in voltage and GND shield layers. The total MCM cross-section thereby consists of 62 layers of ceramic or glass ceramic. 
     Low-effective inductance (L eff ) is crucial for controlling package switching noise levels. The trend for VLSI is to place higher speed circuits at greater densities on a chip. The resultant need for more simultaneous switching mandates a better L eff . Even though L eff  will naturally reduce because of the lower on-chip impedances due to the higher circuit counts, it will still be necessary to augment this effect by placing high-frequency decoupling capacitors between associated voltage pins very close to each chip. 
     However, in view of either the layout of the wiring lines associated with the semiconductor chip or the physical dimensions of the discrete capacitor, the discrete capacitor cannot be positioned such that there is no voltage drop or noise at all. 
     FIG. 2 shows ground (GND) and voltage (V 1 ) mesh planes and two associated signal wiring layers (X, Y). Also shown are the mesh conductors M 1  and M 2  on the GND- and the V 1 -plane, as well as the signal conductors C 1  . . . C 4 , located on signal distribution layer Y. As can be seen from this figure, the width of the mesh-plane (M 1 , M 2 ) is identical to the width of the signal conductor (C 1 , C 2 ). Due to an incomplete shielding effect the inductive and capacitive coupling (L/C) between signal conductors C 1 , C 2  and C 3 , C 4  is increased. This holds true also for the coupling between vertical and diagonal neighbors (C 3 , C 4 →C 1 , C 2 ; cf. the arrows in FIG.  2 ). Thus, this structure generates an unbalanced and asymmetrical coupling at near end and far end. 
     Thus, there still exists a need in the art to provide a technology for the manufacturing of multilayered ceramic modules having an increased shielding effect as well as superior electrical properties compared to the state of the art structures. 
     SUMMARY OF THE INVENTION 
     The present invention relates to a method and apparatus to improve coupled noise characteristics and reduce the number of signal layers in a multilayer ceramic module (MCM). Toward this end, preferred embodiments of the present invention provide an increased via punch pitch, thus allowing two wiring channels between adjacent vias. The resultant increase in wirability allows a reduction in the number of signal layers, thereby reducing the total number of layers in the MCM. In addition, the preferred embodiments of the present invention provide voltage and ground mesh plane conductors which are wider than the signal conductors, thereby improving the coupled noise characteristics of the device. 
     It is therefore an object of the invention to provide a multilayer ceramic structure having superior electrical properties and an increased shielding effect combined with lower manufacturing costs due to reduction of layers. 
     These and other objects and advantages are achieved by the structure according to the appended claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of practice, together with further objects and advantages thereof, may be best understood by reference to the following description taken in connection with the accompanying drawings in which: 
     FIG. 1 a  shows in top and side view the wiring scheme of the state-of-the-art MCM-MLC technology; 
     FIG. 1 b  depicts in top and side view the reference planes for voltage and GND for the structure given in FIG. 1 a ; the cross section shows the GND and the voltage mesh planes with the X, Y wiring plane pair in between; 
     FIG. 1 c  shows the total cross-section of an MCM with all layers according to the structure given in FIGS. 1 a  and  1   b;    
     FIG. 2 depicts in top and side view ground (GND) and voltage (V 1 ) mesh planes and two associated signal wiring layers (X, Y) of the structure of FIGS. 1 a  to  1   c;    
     FIG. 3 a  shows in top and side view the wiring scheme of the MCM-MLC technology according to preferred embodiments of the present invention; 
     FIG. 3 b  depicts in top and side view the reference planes for voltage and GND for the structure given in FIG. 3 a ; the cross section shows the GND and the voltage mesh planes with the X, Y wiring plane pair in between, according to preferred embodiments of the present invention; 
     FIG. 3 c  shows the total cross-section of an MCM with all layers according to the structure given in FIGS. 3 a  and  3   b , according to preferred embodiments of the present invention; and 
     FIG. 4 depicts in a side view ground (GND) and voltage mesh planes and two associated signal wiring layers (X n , Y n  and X n+1 , Y n+1 ) of the structure of FIGS. 3 a  to  3   c , according to preferred embodiments of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIGS. 3 a  to  3   c  describe the novel MCM-MLC technology according to a preferred embodiment of the present invention. In FIG. 3 a  the wiring scheme is shown. It can be seen that the via pitch is now larger than the standard pitch in FIG. 1 a . The signal and power vias (S, P) are punched through all multilayers (MLC) of the MCM. This new via punch pitch is now defined to fit two signal lines between the vias. In the given example the via punch pitch is 675 μm. However, the invention is not restricted to this value. One of ordinary skill in the art will readily deduce from the present disclosure that any via punch pitch can be used, provided two signal lines may be placed between the vias, and further provided that a reasonable manufacturing yield is attainable, as derived from the 1L/CH ground rules (i.e., approximately 50% yield or greater). The via punch pitch shown in FIG. 3 a  is much more relaxed than the standard via pitch and the signal line width and spacing is used according to the standard groundrules. Thereby the yield is not impacted. Due to the increase of wiring channels the wiring capacity of the wiring layers increases by 30% (Table 1). 
     The two wiring layers are again orthogonal to each other as in the standard technology. As two signal lines fit between the vias, the wiring technology of the present invention is now called 2L/CH (two lines per channel) wiring technology. It should be noted that, if the electrical conditions, e.g., coupled noise, allow the wiring of more than two lines per channel, the wiring technology disclosed herein can also be applied to three or more lines per channel. 
     In FIG. 3 b  the reference planes for voltage and GND are shown. These are slightly wider mesh lines compared to the standard MCM technology. The use of wider mesh lines improves the shield characteristic with respect to vertical coupling from plane pair to plane pair, as well as within the same wiring layer. 
     FIG. 3 c  shows the significant layer reduction achieved by using the 2L/CH wiring technology of the present invention. The total number of layers is reduced in this example by 24 layers, from 62 layers to 38 layers, due to the improved wiring capacity of the novel 2L/CH MCM-MLC technology. 
     This significant layer reduction also leads to a reduction in manufacturing costs of about 35% or more. 
     
       
         
               
               
               
             
               
               
               
             
           
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 state of the art 
                   
               
               
                   
                 product 
                 novel product 
               
               
                   
                 1 L/CH wiring 
                 2 L/CH wiring 
               
               
                   
                 technology 
                 technology 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                 outline size 
                   64.3 × 64.3 mm 
                   64.3 × 64.3 mm 
               
               
                 channel area 
                 63.225 × 63.225 mm 
                 63.225 × 63.225 mm 
               
               
                 via channels 
                 140 × 140 
                 93 × 93 
               
               
                 wiring channels 
                 142 × 142 
                 189 × 189 
               
               
                 wiring capacity per 
                 8978 mm 
                 11950 mm 
               
               
                 layer per 
               
               
                 direction 
               
               
                 wiring capacity [%] 
                 100% 
                 130% 
               
               
                   
               
             
          
         
       
     
     FIG. 4 depicts ground (GND) and voltage mesh planes and two associated signal distribution layers (X n , Y n  and X n+1 , Y n+1 ) of the structure of FIGS. 3 a  to  3   c . As already mentioned, and in addition to the enlarged via punch pitch all signal conductors C 1  and C 2  are overlapped by mesh conductors M 1  and M 2 , respectively, by slightly increasing the width of the mesh plane so that the width of the mesh-plane (M 1 , M 2 ) is now wider than the width of the conductor (C 1 , C 2 ). This is achieved by using a respective screening mask having a greater mesh conductor width. The screening mask of the mesh planes is independent of the screening mask of the signal conductors. In the example given in FIG. 4 the overlap is about 10 μm. However, the invention is not restricted to this exact value but can be as small as 5 μm. Due to this overhang the shielding effect from conductor C 1  to conductor C 2  is improved and the coupling between direct neighbors is reduced. In addition, the shielding effect from conductors C 3 , C 4  and C 5  to conductor C 2  is improved and the coupling between vertical and diagonal neighbors is reduced. Thus, this structure generates a balanced and symmetrical coupling at near end (NE) and far end (FE). This effect is shown in Table 2. The electrical properties (NE and FE coupled noise values) are superior to the state of the art structure, although the wiring density is increased by about 30%. 
     
       
         
               
               
               
             
           
               
                 TABLE 2 
               
               
                   
               
               
                 coupled noise 
                 state of the art 
                 novel 
               
               
                 voltage 
                 1 L/CH technology 
                 2 L/CH technology 
               
               
                   
               
             
             
               
                 V fe   
                 260 mV 
                 180 mV 
               
               
                 V nesat   
                 120 mV 
                 180 mV 
               
               
                 @ 1.5 V 
               
               
                   
               
             
          
         
       
     
     The assumptions made in Table 2 are the following: 100 mm parallel lines, including via loading, 9 signal lines (1 quiet line (Q), 8 active (a) as depicted below), dV/dt=4 V/ns. 
     
       
         
               
               
               
               
               
             
           
               
                   
                   
               
             
             
               
                   
                 X1 
                 a 
                 a 
                 a 
               
               
                   
                 X2 
                 a 
                 Q 
                 a 
               
               
                   
                 X3 
                 a 
                 a 
                 a 
               
               
                   
                   
               
             
          
         
       
     
     Within a signal line arrangement 9 signal lines run 100 mm parallel in the same direction in three wiring layers (e.g., X 1 , X 2 , X 3  or Y 1 , Y 2 , Y 3 , . . . ). The center signal line (Q) is kept quiet and all surrounding lines are active (a) and switch simultaneously. The active lines have a slope of 4 V/ns. 
     The far end coupled noise voltage (V fe ) is significantly reduced as compared to the standard technology (260 mV→180 mV). The less critical near end noise voltage (V nesat ) is a little higher as compared to the state of the art technology (120 mV→180 mV). 
     In addition to the advantages already described, the novel 2L/CH MCM wiring technology of the present invention provides an additional advantage for the wiring of differential pairs. In the standard technology the adjacent wiring channels of the differential pairs must be kept free of wiring. In the novel MCM technology, however, this is not required anymore because of the closer coupling of adjacent tracks. Therefore, the wiring of differential pairs consumes less wiring channels as no neighbor channels have to be blocked. This results in a further enhancement of the wiring capacity. 
     A multilayer module according to the invention can be used to package the integrated circuit chips of a computer system. Such a computer system features improved reliability due to reduction of noise. Due to the higher and increased wiring capacity of 2L/CH, the line lengths in general become shorter. The cycle limiting net is shorter compared to the state of the art wiring technology. Therefore, a computer system using the present invention can be operated with faster clock frequencies. 
     While the invention has been described in detail herein in accord with certain preferred embodiments thereof, many modifications and changes therein may be effected by those skilled in the art. Accordingly, it is intended by the appended claims to cover all such modifications and changes as fall within the true spirit and scope of the invention.