Abstract:
A method of forming an integrated circuit structure comprises the steps of: providing a semiconductor substrate having a first side and a second side opposite the first side; forming a hole extending from the first side of the semiconductor substrate into the semiconductor substrate; filling the hole with conductive material; thinning the second side of the semiconductor substrate to a first predetermined thickness, so that the bottom of the hole does not protrude from the second side of the semiconductor substrate; and etching the second side of the semiconductor substrate to a second predetermined thickness, thereby exposing the bottom of the hole.

Description:
TECHNICAL FIELD 
     The present invention relates to an integrated circuit structure and a method of forming the same. More particularly, the present invention relates to an integrated circuit structure having a through-silicon via (TSV) and a method of forming the same. 
     BACKGROUND 
     Packaging technology for integrated circuit structures has been continuously developed to meet the demand toward miniaturization and mounting reliability. Recently, as the miniaturization and high functionality of electric and electronic products are required, various techniques have been disclosed in the art. 
     By using a stack of at least two chips, in the case of a memory device for example, it is possible to produce a product having a memory capacity which is twice as large as that obtainable through semiconductor integration processes. Also, a stack package provides advantages not only of an increase in memory capacity but also in regards to mounting density and mounting area utilization efficiency. Due to this fact, research and development of stack package technology has accelerated. 
     As an example of a stack package, a through-silicon via (TSV) has been disclosed in the art. The stack package using a TSV has a structure in which the TSV is disposed in a chip so that chips are physically and electrically connected with each other through the TSV. Generally, a TSV is formed by etching a vertical via through a substrate and filling the via with a conductive material, such as copper. To increase the transmission speed and for high-density fabrication, the thickness of a semiconductor wafer comprising multiple integrated circuit structures each having the TSV should be reduced efficiently. 
     However, in order to reduce the thickness of the wafer and form the TSV in the corresponding integrated circuit structure, the deposition of a silicon nitride (SiN) layer on the backside of the wafer and multiple chemical mechanical polishing (CMP) process are required in the prior art process, which is complex and expensive. An example is described in an article entitled “A 3D Stacked Memory Integrated on a Logic Device Using SMAFTI Technology” by Yoichiro Kurita, et al., ECTC 2007 Electronic Components and Technology Conference paper, pages 821 to 829. Therefore, there is a need to provide a novel TSV backside process to reduce manufacturing complexity and cost. 
     SUMMARY 
     An aspect of the present invention is to provide an integrated circuit structure having a through-silicon via and a method of forming the same. 
     According to one embodiment of the present invention, the method of forming an integrated circuit structure comprises the steps of providing a semiconductor substrate having a first side and a second side opposite the first side; forming a hole extending from the first side into the semiconductor substrate; filling the hole with conductive material; thinning the second side of the semiconductor substrate to a first predetermined thickness, so that the bottom of the hole does not protrude from the second side of the semiconductor substrate; and etching the second side of the semiconductor substrate to a second predetermined thickness, thereby exposing the bottom of the hole. 
     According to another embodiment of the present invention, the integrated circuit structure comprises a semiconductor substrate having a first side and a second side opposite the first side, a conductive via extending from the first side of the semiconductor substrate, a photosensitive dielectric layer with an opening formed on the second side of the semiconductor substrate, and a solder bump positioned in the opening and electrically connected to the conductive via. 
     The foregoing has outlined rather broadly the features of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features of the invention will be described hereinafter, and form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes as those of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the invention. 
         FIGS. 1 through 10  are cross-sectional views illustrating a method for forming an integrated circuit structure in accordance with one embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
       FIGS. 1 through 10  are cross-sectional views illustrating a method for forming an integrated circuit structure  10  in accordance with one embodiment of the present invention. Referring to  FIG. 1 , a semiconductor substrate  110  has a first side  110 A and a second side  110 B opposite the first side  110 A, and an inter-layer dielectric (ILD) layer  112  is formed on the first side  110 A of the semiconductor substrate  110 . The ILD layer  112  may be formed, for example, of a low-K dielectric material, such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG) or fluorinated silicate glass (FSG). One or more inter-metal dielectric (IMD) layers  114  are formed over the ILD layer  112  to interconnect electrical devices (not shown) to communicate with each other. The IMD layers  114  are preferably formed of a low-K dielectric material. In one embodiment of the present invention, photolithographic and etching processes are performed to form one or more holes  111  extending from the IMD layers  114  into the semiconductor substrate  110 . 
     Referring to  FIG. 2 , a dielectric layer  116  such as an oxide layer is formed along the sidewall and bottom surface of the hole  111  by a conventional deposition method and a conductive diffusion barrier layer  118  is then formed along the dielectric layer  116 . The conductive diffusion barrier layer  118  could be made of a material selected from the group consisting of TaN, Ta, TiN, Ti, Co, W, and a combination thereof. 
     Referring to  FIG. 3 , a protective layer  120 , such as a polyimide layer, may be formed and patterned over the surface of the diffusion barrier layer  118 . Subsequently, the hole  111  is filled with a conductive material, thereby forming a TSV  126 . The conductive material of the TSV  126  can be made of a material selected from the group consisting of copper, tungsten, aluminum, silver and a combination thereof. It should be noted that the ILD layer  112 , IMD layer  114 , and protective layer  120  are illustrated as being arranged successively for illustrative purposes only and that other arrangements may be utilized. 
     Referring to  FIG. 3 , a carrier  124  is attached to the integrated circuit structure  10  by using an adhesive  122 . The adhesive  122  may be any suitable adhesive, such as ultraviolet (UV) glue. Generally, the carrier  124  provides temporary mechanical and structural support during subsequent processing steps. In this manner, damage to the semiconductor substrate  110  can be reduced or prevented. In one embodiment of the present invention, the thickness d 1  of the semiconductor substrate  110  is originally between 700 μm and 800 μm, and the depth d 2  of the TSV  126  extending from the first side  110 A of the semiconductor substrate  110  is originally about 55 μm. 
       FIG. 4  illustrates a thinning process performed on the second side  110 B of the semiconductor substrate  110  in accordance with an embodiment of the present invention. The thinning process may be performed using a planarization process, such as a mechanical grinding process or a chemical mechanical polishing (CMP) process, and the thickness of the semiconductor substrate  110  is decreased to a first predetermined thickness d 3  after the process. In one embodiment of the present invention, after the thinning process, the new thickness d 3  of the semiconductor substrate  110  is, preferably, between 55.5 μm and 60 μm to prevent the bottom of the hole  111  (the dielectric layer  116 ) from exposing outside the second side  110 B of the semiconductor substrate  110 . 
     Referring to  FIG. 5 , according to one embodiment of the present invention, one or more wet etching processes are performed on the second side  110 B of the semiconductor substrate  110  after the thinning process, thereby leaving the bottom of the hole  111 , i.e., the dielectric layer  116  below the TSV  126  in this embodiment, protruding from the second side  110 B of the semiconductor substrate  110 . The wet etching process may be performed by solutions like KOH (potassium hydroxide), NaOH (sodium hydroxide), NH 4 OH (ammonia hydroxide), or TMAH (tetramethylammonia hydroxide). According to another embodiment of the present invention, one or more dry etching processes are performed on the semiconductor substrate  110  after the thinning process. Therefore, the second side  110 B of the semiconductor substrate  110  is etched by an anisotropic plasma etch using compounds such as HBr/O 2 , SF6/CL 2 , SF 6  plasma, or the likes. 
     Referring to  FIG. 6 , a photosensitive dielectric layer  132  is formed on the second side  110 B of the semiconductor substrate  110 . The photosensitive dielectric layer  132  can be made of a material selected from the group consisting of polybenzoxazoles (PBO), polybenzimidazoles, polyimides (PI), phenolic resins and a combination thereof. Subsequently, a lithographic process is performed by using UV radiation to expose a potion of the photosensitive dielectric layer  132  right below the TSV  126 . Depending on whether the photosensitive dielectric layer  132  is a negative tone or a positive tone photoresist, the unexposed portions or the exposed portions of the photosensitive dielectric layer  132  are then developed and removed using a solution such as TMAH, as shown in  FIG. 7 . 
       FIG. 8  illustrates an etching process to remove a portion of the dielectric layer  116  positioned below the TSV  126  in accordance with an embodiment of the present invention. After the etching process, a portion of the conductive diffusion barrier layer  118  is exposed and then a solder bump  134  can be formed to connect the exposed portion of the conductive diffusion barrier layer  118  below the TSV  126  for an external electrical connection as shown in  FIG. 9 . Therefore, the solder bump  134  is electrically connected to the conductive material in the hole  111 . Subsequently, other back-end-of-line (BEOL) processing techniques suitable for the particular application may be performed to complete the integrated circuit structure  10 . For example, the carrier  124  may be removed, an encapsulant may be formed, a dicing process may be performed to dice individual dies, wafer-level or die-level stacking, and the likes, may be performed depending on the application. 
     In one embodiment of the present invention, before the formation of the photosensitive dielectric layer  132 , a dielectric layer  130  is optionally formed on the second side  110 B of the semiconductor substrate  110  as shown in  FIG. 10 . Generally, the dielectric layer  130  provides a mechanism to prevent the diffusion of the conductive material in the TSV  126  and to compensate for the stress applied to the second side  110 B of the semiconductor substrate  110  during subsequent processing steps. According to one embodiment, the dielectric layer  130  is deposited by CVD or PECVD techniques, and the material can be selected from the group consisting of SiN, SiCN, SiCO, CN and a combination thereof. 
     Although the present invention have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof. 
     Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, to compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.