Abstract:
A new and improved semiconductor memory that facilitates machining of iterated circuits and solves the problems of the prior art such as the lengthy machining process, the compromised machining accuracy and the considerable time required for device evaluation is provided. A semiconductor memory  10  is provided with a plurality of output circuits  11  and a fuse circuit  12  connected to each of the output circuits. The fuse circuit outputs output signals N 1  and N 2  to the individual output circuits, the signal levels of which are fixed to either H level or L level depending upon whether or not fuses f 1  and f 2  in the fuse circuit are disconnected. The output circuits are each provided with an output buffer circuit unit  112  and a pre-driver circuit unit  111  that drives the output buffer circuit unit. The driving capability of the pre-driver circuit unit is determined by the output signal from the fuse circuit. By providing the fuses that can be easily disconnected with a laser beam, it becomes possible to adjacent the gate widths of the pre-drivers at the plurality of output circuit units all at once. As a result, the length of machining time can be reduced compared to that required in the prior art technology.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a semiconductor memory, and more specifically it relates to a semiconductor memory that enables dimensional adjustment by using a fuse which can be cut with a laser beam. 
     Circuits that constitute a semiconductor memory include circuits achieved by arraying a plurality of identically structured circuits (iterated circuits) such as an input/output circuit and a read amplifier circuit. As higher integration, further miniaturization and multiple-output structuring have been achieved in semiconductor memories in recent years, the use of iterated circuits in semiconductor memory has been on the rise. 
     PRIOR ART 
     An FIB (focused ion beam) apparatus is employed to machine an iterated circuit in the prior art. The FIB apparatus cuts wiring by taking advantage of the sputtering phenomenon that occurs when an ion beam is irradiated. For instance, the FIB apparatus is employed to adjust the width of the gate of a transistor that constitutes a pre-driver circuit for driving an output buffer circuit in the output circuit of a random access memory (RAM). 
     However, the number of iterated circuits in a semiconductor memory has been on the rise due to the higher integration, further miniaturization and multiple-output structuring achieved in the semiconductor memory in recent years. The increase in the number of machining areas resulting from the increase in the number of iterated circuits poses problems with respect to the machining process implemented by utilizing the FIB apparatus in the prior art in that the length of machining time is bound to increase, that the machining accuracy is compromised and that the device evaluation becomes a lengthy procedure. 
     SUMMARY OF THE INVENTION 
     An object of the present invention, which has been completed by addressing the problems of the semiconductor memory in the prior art discussed above, is to provide a new and improved semiconductor memory that facilitates machining of iterated circuits to solve the problems of the prior art such as the great length of time required for machining, the compromised machining accuracy and the lengthy device evaluation process. 
     Another object of the present invention is to provide a new and improved semiconductor memory that achieves a smaller layout area to minimize any increase within the chip area. 
     In order to achieve the objects described above, a first semiconductor memory according to the present invention is provided with a plurality of output circuits and a fuse circuit commonly connected to the output circuits. The fuse circuit outputs an output signal to each output circuit, the signal level of which is fixed to one signal level or another signal level depending upon whether or not a fuse in the circuit is disconnected, and the output circuits are each provided with an output buffer circuit unit and a pre-driver circuit unit that drives the output buffer circuit unit, with the driving capability of the pre-driver circuit unit determined by the output signal provided by the fuse circuit. 
     A second semiconductor memory according to the present invention is provided with a plurality of output circuits and a plurality of fuse circuits each connected to one of the output circuits. Each fuse circuit outputs an output signal to the corresponding output circuit, the signal level of which is fixed to one signal level or another signal level depending upon whether or not a fuse in the circuit is disconnected, and the output circuits are each provided with an output buffer circuit unit and a pre-driver circuit unit that drives the output buffer circuit unit, with the driving capability of the pre-driver circuit unit determined by the output signal provided by the corresponding fuse circuit. 
     A third semiconductor memory according to the present invention is provided with a plurality of amplifier circuits and a fuse circuit connected to the individual amplifier circuits. The fuse circuit outputs an output signal to each amplifier circuit, the signal level of which is fixed to one signal level or another signal level depending upon whether or not a fuse in the circuit is disconnected, with the amplifying capability of each amplifier circuit determined by the output signal provided by the fuse circuit. 
     A fourth semiconductor memory according to the present invention is provided with a plurality of amplifier circuits and a plurality of fuse circuits each connected to one of the amplifier circuits. Each fuse circuit outputs an output signal to the corresponding amplifier circuit, the signal level of which is fixed to one signal level or another signal level depending upon whether or not a fuse in the circuit is disconnected, with the amplifying capability of the amplifier circuit determined by the output signal provided by the fuse circuit. 
     A fifth semiconductor memory according to the present invention is provided with a plurality of delay circuits and a fuse circuit connected to the individual delay circuits. The fuse circuit outputs an output signal to each delay circuit, the signal level of which is fixed to one signal level or another signal level depending upon whether or not a fuse in the circuit is disconnected, with the delay time generated by each of the delay circuits determined by the output signal provided by the fuse circuit. 
     A sixth semiconductor memory according to the present invention is provided with a plurality of delay circuits and a plurality of fuse circuits each connected to one of the delay circuits. Each fuse circuit outputs an output signal to the corresponding delay circuit, the signal level of which is fixed to one signal level or another signal level depending upon whether or not a fuse in the circuit is disconnected, with the delay time generated by the delay circuit determined by the output signal provided by the fuse circuit. 
     A seventh semiconductor memory according to the present invention is provided with a plurality of input first-stage circuits and a fuse circuit connected to the individual input first-stage circuits. The fuse circuit outputs an output signal to each input first-stage circuit, the signal level of which is fixed to one signal level or another signal level depending upon whether or not a fuse in the circuit is disconnected, with the input voltage margin of the input first-stage circuit determined by the output signal provided by the fuse circuit. 
     An eighth semiconductor memory according to the present invention is provided with a plurality of input first-stage circuits and a plurality of fuse circuits each connected to one of the input first-stage circuits. Each fuse circuit outputs an output signal to the corresponding input first-stage circuit, the signal level of which is fixed to one signal level or another signal level depending upon whether or not a fuse in the circuit is disconnected, with the input voltage margin of the input first-stage circuit determined by the output signal provided by the fuse circuit. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other features of the invention and the concomitant advantages will be better understood and appreciated by persons skilled in the field to which the invention pertains in view of the following description given in conjunction with the accompanying drawings which illustrate preferred embodiments. 
     FIG. 1 illustrates the chip achieved in a first embodiment in its entirety; 
     FIG. 2 illustrates an output circuit adopted in first and second embodiments; 
     FIG. 3 illustrates a fuse circuit adopted in the first and second embodiments; 
     FIG. 4 illustrates the chip achieved in the second embodiment in its entirety; 
     FIG. 5 illustrates the chip achieved in a third embodiment in its entirety; 
     FIG. 6 illustrates an amplifier circuit adopted in third and fourth embodiments; 
     FIG. 7 illustrates a fuse circuit adopted in the third and fourth embodiments; 
     FIG. 8 illustrates the chip achieved in the fourth embodiment in its entirety; 
     FIG. 9 illustrates the chip achieved in a fifth embodiment in its entirety; 
     FIG. 10 illustrate a delay circuit adopted in fifth and sixth embodiments; 
     FIG. 11 illustrates a fuse circuit adopted in the fifth and sixth embodiments; 
     FIG. 12 illustrates the chip achieved in the sixth embodiment in its entirety; 
     FIG. 13 illustrates the chip achieved in a seventh embodiment in its entirety; 
     FIG. 14 illustrates an input first-stage circuit adopted in a seventh embodiment; 
     FIG. 15 illustrates a fuse circuit adopted in the seventh embodiment; 
     FIG. 16 illustrates the chip achieved in the eighth embodiment in its entirety; 
     FIG. 17 illustrates the chip achieved in a ninth embodiment in a its entirety; 
     FIG. 18 illustrates an output circuit adopted in a ninth embodiment; and 
     FIG. 19 illustrates a fuse circuit adopted in the ninth embodiment. 
     FIG. 20 illustrates the chip achieved in the tenth embodiment in its entirety; 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The following is a detailed explanation of the preferred embodiments of the semiconductor memory according to the present invention, given in reference to the attached drawings. It is to be noted that in the specification and the drawings, the same reference numbers are assigned to components achieving functions and structural features essentially identical to one another to preclude the necessity for repeated explanation thereof. In the following explanation, a P-channel MOS transistor is referred to as a PMOS transistor, an N-channel MOS transistor is referred to as an NMOS transistor. In addition, a P-channel MOS transistor and an N-channel MOS transistor are categorically referred to simply as MOS transistors. 
     (First Embodiment) 
     A semiconductor memory  10  in the first embodiment is explained in reference to FIGS.  1 ˜ 3 . The semiconductor memory  10  comprises a plurality of output circuits  11  and a fuse circuit  12  shared by the individual output circuits  11 , as illustrated in FIG.  1 . 
     As shown in FIG. 2, the output circuits  11  are each constituted of a pre-driver circuit unit  111  and an output buffer circuit unit  112 . The output buffer circuit unit  112  comprises a PMOS transistor PTr 5  for H level output and an NMOS transistor NTr 5  for L level output. The pre-driver circuit unit  111  comprises a first pre-driver portion  113  that drives the PMOS transistor PTr 5  in the output buffer circuit unit  112  at the following stage and a second pre-driver portion  114  that drives the NMOS transistor NTr 5  in the output buffer circuit unit  112  at the following stage. 
     The first pre-driver portion  113  is constituted of a PMOS transistor PTr 6 , an NMOS transistor NTr 7  and an NMOS transistor NTr 8  that are serially connected between the source terminal and the ground terminal and an NMOS transistor NTr 6  connected in parallel to the NMOS transistor NTr 8 . The gates of the PMOS transistor PTr 6 , the NMOS transistor NTr 8  and the NMOS transistor NTr 6  are connected to an input IN 1 . The gate of the NMOS transistor NTr 7  is connected to an output N 1  of a first fuse circuit unit  121 , which is to be detailed later. The drain of the PMOS transistor PTr 6  (the drain of the NMOS transistor NTr 7 ) and the drain of the NMOS transistor NTr 6  are connected to the gate of the PMOS transistor PTr 5  in the output buffer circuit unit  112  at the following stage. 
     Thus, in the first pre-driver portion  113 , the transistor that determines its driving capability is formed in a comb shape and part of the comb-shaped transistor is replaced by the MOS transistors PTr 6 , NTr 7  and NTr 8  that are serially connected. 
     The second pre-driver portion  114  is constituted of a PMOS transistor PTr 8 , a PMOS transistor PTr 9  and an NMOS transistor NTr 9  that are serially connected between the source terminal and the ground terminal and a PMOS transistor PTr 7  connected in parallel to the PMOS transistor PTr 8 . The gates of the PMOS transistor PTr 8 , the NMOS transistor NTr 9  and the PMOS transistor PTr 7  are connected to an input IN 2 . The gate of the PMOS transistor PTr 9  is connected to an output P 1  of a second fuse circuit  122 , which is to be detailed later. The drain of the PMOS transistor PTr 9  (the drain of the NMOS transistor NTr 9  and the drain of the PMOS transistor PTr 7 ) is connected to the gate of the NMOS transistor NTr 5  in the output buffer circuit unit  112  at the following stage. 
     Thus, in the second pre-driver portion  114 , the transistor that determines its driving capability is formed in a comb shape and part of the comb-shaped transistor is replaced by the MOS transistors PTr 8 , PTr 9  and NTr 9  that are serially connected. 
     As shown in FIG. 3, the fuse circuit  12  comprises the first fuse circuit unit  121  that is connected to the gate of the NMOS transistor NTr 7  in the first pre-driver circuit unit  113  and the second fuse circuit  122  connected to the gate of the PMOS transistor PTr 9  in the second pre-driver circuit unit  114 . 
     The first fuse circuit  121  is constituted of a PMOS transistor PTr 10 , a fuse f 1  and an NMOS transistor NTr 10  serially connected between the source terminal and the ground terminal, a PMOS transistor PTr 11  connected in parallel to the PMOS transistor PTr 10  and inverters INV 1 , INV 2  and INV 3  serially connected between a node located between the PMOS transistor PTr 10  and the fuse f 1  and the output N 1 . The gates of the PMOS transistor PTr 10  and the NMOS transistor NTr 10  are connected to an input ST. The gate of the PMOS transistor PTr 11  is connected to a node located between the inverters INV 1  and INV 2 . 
     The input ST is a signal whose signal level shifts from L level to H level when a specific length of time has elapsed after the power to the semiconductor memory  10  is set to ON, and it may be designed so that its level shifts when, for instance, 300 microsecond have elapsed. 
     The second fuse circuit  122  is constituted of a PMOS transistor PTr 13 , a fuse f 2  and an NMOS transistor NTr 11  serially connected between the source terminal and the ground terminal, a PMOS transistor PTr 14  connected in parallel to the PMOS transistor PTr 13  and inverters INV 4  and INV 5  serially connected between a node located between the PMOS transistor PTr 13  and the fuse f 2  and the output P 1 . The gates of the PMOS transistor PTr 13  and the NMOS transistor NTr 11  are connected to the input ST. The gate of the PMOS transistor Ptr 14  is connected to a node located between the inverters INV 4  and INV 5 . 
     The fuse circuit  12  described above achieves a circuit structure that enables control of the outputs P 1  and N 1  so that they output either H level or L level in conformance to whether or not the fuses f 1  and f 2  are disconnected. The following is an explanation of changes occurring in the operation in conformance to the connected/disconnected states of the fuses f 1  and f 2 . 
     First, a state in which neither the fuse f 1  or the fuse f 2  is disconnected is explained. When the specific length of time has elapsed after a power-up, the input ST of the fuse circuit  12  shifts to H level. In the first fuse circuit  121 , with the NMOS transistor NTr 10  whose source is connected to the ground terminal entering an ON state, the output N 1  shifts to H level via the fuse f 1  and the inverters INV 1 , INV 2  and INV 3 . In the second fuse circuit  122 , with the NMOS transistor NTr 11 , whose source is connected to the ground terminal entering an ON state, an output N 2  shifts to L level via the fuse f 2 , and the inverters INV 4  and INV 5 . 
     When the output N 1  is at H level and the output N 2  is at L level, the NMOS transistor NTr 7  in the first pre-driver circuit unit  113  becomes set to ON and the PMOS transistor PTr 9  in the second output circuit unit  112  becomes set to ON at the output circuit  11 . When the NMOS transistor NTr 7  in the first pre-driver circuit unit  113  is in an ON state, the PMOS transistor PTr 5  at the following stage is driven by the NMOS transistor NTr 6 , the NMOS transistor NTr 7  and the NMOS transistor NTr 8 . When the PMOS transistor PTr 9  in the second pre-driver circuit unit  114  is in an ON state, the NMOS transistor NTr 5  at the following stage is driven by the PMOS transistor PTr 7 , the PMOS transistor PTr 8  and the PMOS transistor PTr 9 . 
     Next, a state in which both the fuse f 1  and the fuse f 2  are disconnected is explained. Until the specific length of time elapses after a power-up, the input ST of the fuse circuit  12  remains at L level. In the first fuse circuit  121 , with the PMOS transistor PTr 10  whose source is connected to the source terminal entering an ON state, the output N 1  shifts to L level via the inverters INV 1 , INV 2  and INV 3 . At this time, the PMOS transistor PTr 11 , whose source is connected to the source terminal, too, is set to ON. In the second fuse circuit  122 , with the PMOS transistor PTr 13  whose source is connected to the source terminal entering an ON state, the output N 1  shifts to H level via the fuse f 2  and the inverters INV 4  and INV 5 . At this time, the PMOS transistor PTr 14 , whose source is connected to the source terminal, too, is set to ON. 
     When the output N 1  is at L level and the output N 2  is at H level, the NMOS transistor NTr 7  in the first pre-driver circuit unit  113  is set to OFF and the PMOS transistor PTr 9  in the second pre-driver circuit unit  114  is also set to OFF at the output circuits  11 . When the NMOS transistor NTr 7  in the pre-driver circuit unit  113  is in an OFF state, the PMOS transistor PTr 5  at the following stage is driven by the NMOS transistor NTr 6  alone. When the PMOS transistor PTr 9  in the second pre-driver circuit unit  114  is in an OFF state, the NMOS transistor NTr 5  at the following stage is driven by the PMOS transistor PTr 7  alone. 
     As explained above, in this embodiment, which is provided with the fuse circuit  12  having the fuse f 1  and the fuse f 2  that can be easily disconnected by a laser beam, the gate widths W of the pre-drivers at the plurality of output circuits can be adjusted all at once. Thus, the length of time required for the machining process can be reduced compared to that required in the prior art technology, in which the wiring is disconnected by employing an FIB apparatus. 
     (Second Embodiment) 
     A semiconductor memory  20  in the second embodiment is explained in reference to FIG.  4 . As shown in FIG. 4, the semiconductor memory  20  comprises a plurality of output circuits  11  and fuse circuits  12  each provided in correspondence to one of the output circuits  11 . It is to be noted that since the structural features and the operations achieved in the output circuits  11  and the fuse circuit  12  are identical to those achieved in the first embodiment, their explanation is omitted. 
     As described above, in the embodiment in which the fuse circuit  12  are provided each in correspondence to one of the output circuits  11 , the gate width W can be adjusted at each output circuit  11 . 
     (Third Embodiment) 
     A semiconductor memory  30  in the third embodiment is now explained in reference to FIGS.  5 ˜ 7 . As shown in FIG. 5, the semiconductor memory  30  comprises a plurality of amplifier circuit  31  and a fuse circuit  32  shared by the individual amplifier circuits  31 . 
     The amplifier circuit  31  are each constituted of a PMOS transistor PTr 21  and an NMOS transistor NTrl 7  serially connected between the source terminal and an NMOS transistor unit  311 , a PMOS transistor PTr 22  and an NMOS transistor NTrl 8  serially connected between the source terminal and the NMOS transistor unit  311 , a PMOS transistor PTr 24  and an NMOS transistor NTrl 9  serially connected between the source terminal and the NMOS transistor unit  311 , a PMOS transistor PTr 25  and an NMOS transistor NTr 20  serially connected between the source terminal and the NMOS transistor unit  311 , a PMOS transistor PTr 23  connected between the drain (a node “a”) of the PMOS transistor PTr 21  and the drain of the PMOS transistor PTr 22 , a PMOS transistor which PTr 26  connected between the PMOS transistor PTr 24  and the drain (a node “b”) of the PMOS transistor PTr 25  and a DB/DBb amplifier circuit  312  connected to the node “a” and the node “b”. 
     A signal SDB is input to the gates of the NMOS transistors NTr 17  and NTr 19 . A signal SDBb is input to the gates of the NMOS transistors NTr 18  and NTr 20 . It is to be noted that the signals SDB and SDBb are complementary to each other. 
     An amplifier equalize signal EQ is input to the gates of the PMOS transistors PTr 23  and PTr 26  and the DB/DBb amplifier circuit  312 . 
     In addition, an amplifier enable signal EN is input to the gates of the NMOS transistors NTr 21  and NTr 22  and the DB/DBb amplifier circuit  312 . 
     In each amplifier circuit  31 , its amplification speed is determined by the NMOS transistor unit  311  constituted of the NMOS transistors NTr 21 , NTr 22  and NTr 23 . Thus, the structure of the amplifier circuit  31  is achieved by forming the transistor that determines the amplifying capability in a comb shape and replacing part of the comb-shaped transistor with the MOS transistors NTr 22  and NTr 23  that are serially connected. 
     As illustrated in FIG. 6, the fuse circuit  32  is constituted of a PMOS transistor PTr 27 , a fuse f 3  and an NMOS transistor NTr 24  serially connected between the source terminal and the ground terminal, a PMOS transistor PTr 28  connected in parallel to the PMOS transistor PTr 27  and inverters INV 6 , INV 7  and INV 8  serially connected between a node located between the PMOS transistor PTr 27  and the fuse f 3  and an output N 2 . The gates of the PMOS transistor PTr 27  and the NMOS transistor NTr 27  are connected to an input ST. The input ST is a signal similar to that generated in the first embodiment. The gate of the PMOS transistor PTr 28  is connected to a node located between the inverters INV 6  and INV 7 . 
     The fuse circuit  32  described above achieves a circuit structure that enables control of the output N 2  so that it outputs either H level or L level in conformance to whether or not the fuse f 3  is disconnected. The following is an explanation of changes occurring in the operation in conformance to the connected/disconnected state of the fuse f 3 . 
     First, a state in which the fuse f 3  is not disconnected is explained. 
     When a specific length of time has elapsed after a power-up, the input ST of the fuse circuit  32  shifts to H level. In the fuse circuit  32 , with the NMOS transistor NTr 24 , whose source is connected to the ground terminal entering an ON state, the output N 2  shifts to H level via the fuse f 3  and the inverters INV 6 , INV 7  and INV 8 . When the output N 2  is at H level, the NMOS transistor NTr 23  is in an ON state at the amplifier circuit  31 . Thus, the capability of the NMOS transistor unit  311  which determines the amplification speed of the amplifier circuit  31  corresponds to the total of the capabilities of the NMOS transistors NTr 21 , NTr 22  and NTr 23 . 
     Next, a state in which the fuse f 3  is not disconnected is explained. 
     Until the specific length of time elapses after a power-up, the input ST at the fuse circuit  32  remains at the L level. In the fuse circuit  32 , with the PMOS transistor PTr 27  whose source is connected to the source terminal entering an ON state, the output N 2  shifts to L level via the inverters INV 6 , INV 7  and INV 8 . At this time, the PMOS transistor PTr 28  whose source is connected to the source terminal, too, is set to ON. When the output N 2  is at L level, the NMOS transistor NTr 23  is in an OFF state at the amplifier circuits  31 . Thus, the capability of the NMOS transistor unit  311  that determines the amplification speed of the amplifier circuit  31  corresponds to the. capability of the PMOS transistor PTr 21  alone. 
     As explained above, in this embodiment, by providing the fuse circuit  32  having the fuse f 3  that can be easily disconnected with a laser beam, the gate widths W of the NMOS transistor units that determine the amplification speeds of the amplifier circuits  31  within the chip can be changed all at once. Thus, the length of time required for machining can be reduced compared to that required in the prior art technology, in which wiring is disconnected by employing an FIB apparatus. 
     (Fourth Embodiment) 
     A semiconductor memory  40  in the fourth embodiment is explained in reference to FIG.  8 . As illustrated in FIG. 8, the semiconductor memory  40  comprises a plurality of amplifier circuit  31  and fuse circuits  32  each provided in correspondence to one of the amplifier circuits  31 . It is to be noted that since the structural features and operations achieved in the amplifier circuit  31  and the fuse circuit  32  are identical to those achieved in the third embodiment described earlier, their explanation is omitted. 
     As explained above, in this embodiment, by providing the fuse circuit  32  each in correspondence to one of the amplifier circuits  31 , the adjustment of the NMOS transistor unit that determines the amplification speed of each amplifier circuit  31  can be implemented at each amplifier circuit  31 . 
     (Fifth Embodiment) 
     A semiconductor memory  50  in the fifth embodiment is now explained in reference to FIGS.  9 ˜ 11 . As illustrated in FIG. 9, the semiconductor memory  50  comprises a plurality of delay circuits  51  and a fuse circuit  52  shared by the individual delay circuits  51 . 
     As illustrated in FIG. 10, the delay circuits  51  are each constituted of inverters INV 30 , INV 31 , INV 32  and IMV 33  serially connected between an input IN 11  and an output OUT 11 , a transfer gate TG 1  comprising an NMOS transistor NTr 50  and a PMOS transistor PTr 61 , a NAND circuit NAND  10 , inverters INV 34 , INV 35  and INV 36 , a NAND circuit NAND  11 , an inverter INV 37  and a PMOS transistor PTr 62  with the gate thereof connected to the gate of the NMOS transistor Ntr 50 , the source thereof connected to the source terminal and the drain thereof connected to the drain of the NMOS transistor NTr 50 . Other terminals at the NAND circuit NAND  10  and the NAND circuit NAND  11  are connected to the input IN 11 . 
     As described above, the transfer gate TG 1  is provided in the inverter chain constituted of the inverters INV 30 ˜INV 33  that are connected serially and the inverters INV 34 ˜INV 36 , and functions as a switch that adjusts the length of the inverter chain. 
     As illustrated in FIG. 11, the fuse circuit  52  comprises a PMOS PTr 62 , a fuse f 10  and an NMOS transistor NTr 51  that are connected serially between the source terminal and the ground terminal, a PMOS transistor PTr 63  connected in parallel to the PMOS transistor PTr 62  and inverters INV 39 , INV 40  and INV 41  serially connected between a node located between the PMOS transistor PTr 62  and the fuse f 10  and an output N 10 . The output of the inverter INV 40  is connected to another output P 10 . The gates of the PMOS transistor PTr 62  and the NMOS transistor NTr 51  are connected to an input ST. The input ST is a signal identical to that generated in the first embodiment. The gate of the PMOS transistor PTr 63  is connected to a node located between the inverters INV 39  and INV 40 . 
     The fuse circuit  52  described above achieves a circuit structure that enables control of the outputs N 10  and P 10  so that they output H level or L level depending upon whether or not the fuse f 10  is disconnected. The following is an explanation of changes occurring in the operation in conformance to the connected/disconnected state of the fuse f 10 . 
     First, a state in which the fuse f 10  is not disconnected is explained. 
     When a specific length of time has elapsed after a power-up, the input ST of the fuse circuit  52  shifts to H level. In the fuse circuit  52 , with the NMOS transistor NTr 51 , whose source is connected to the ground terminal entering an ON state, the output P 10  shifts to L level via the fuse f 10  and the inverters INV 39  and INV 40 , and the output N 10  shifts to H level via the inverter INV 41 . When the output P 10  is at L level and the output N 10  is at H level, the transfer gate TG 1  in the delay circuit  51  remains in an ON state at all times. Thus, the delay capability of the delay circuit  51  corresponds to the sum of the delay capabilities of the inverters INV 30 , INV 31 , INV 32  and INV 33 . 
     Next, a state in which the fuse f 10  is disconnected is explained. 
     The input ST is at L level after a power-up, and the PMOS transistor PTr 62  whose source is connected to the source terminal becomes set to ON. When the PMOS transistor PTr 62  enters an ON state, the PMOS transistor PTr 63  whose source is connected to the source terminal is set to ON via the inverter INV 39 . As a result, the output P 10  shifts to H level via the inverters INV 39  and INV 40 , and the output N 10  shifts to L level via the inverter INV 41 . Next, after the specific length of time has elapsed, the input ST shifts to H level to set the NMOS transistor Ntr 51  to ON. However, since the fuse f 10  is disconnected, the outputs N 10  and P 10  remain unaffected. When the output P 10  is at H level and the output N 10  shifts to L level, the transfer gate TG 1  in the delay circuit  51  remains in an OFF state at all times. Thus, the absence of delay at the inverters INV 30 , INV 31 , INV 32  and INV 33  results in a reduction in the delay time at the delay circuit  51 . 
     As explained above, in the embodiment, by providing the fuse circuit  52  having the fuse f 10  that can be easily disconnected with a laser beam, the lengths of inverter delays that determine that delay at the delay circuits can be changed all at once. As a result, a reduction in the machining time compared to that required in the prior art technology, which employs an FIB apparatus to disconnect wiring, is achieved. 
     (Sixth Embodiment) 
     A semiconductor memory  60  in the sixth embodiment is explained in reference to FIG.  12 . As illustrated in FIG. 12, the semiconductor memory  60  comprises a plurality of delay circuits  51  and fuse circuits  52  each provided in correspondence to one of the delay circuits  51 . It is to be noted that since the structural features and operations in the delay circuits  51  and the fuse circuit  52  are identical to those achieved in the fifth embodiment, their explanation is omitted. 
     As described above, in this embodiment, by providing the fuse circuit  52  each in correspondence to one of the delay circuits  51 , the delay capability can be adjusted at each delay circuit  51 . 
     (Seventh Embodiment) 
     A semiconductor memory  70  in the seventh embodiment is explained in reference to FIGS.  13 ˜ 15 . The semiconductor memory  70  comprises a plurality of input first-stage circuits  71  and a fuse circuit  72  shared by the individual input first-stage  71 , as illustrated in FIG.  13 . 
     As illustrated in FIG. 14, the input first-stage circuits  71  are each constituted of a PMOS transistor PTr 33 , a PMOS transistor PTr 34 , an NMOS transistor NTr 29  and an NMOS transistor NTr 30  serially connected between the source terminal and the ground terminal, a PMOS transistor PTr 35  and a PMOS transistor PTr 36  connected in parallel to the PMOS transistor PTr 34 , a PMOS transistor PTr 37  and a PMOS transistor PTr 38  connected in parallel to the PMOS transistor PTr 34  and an NMOS transistor NTr 28  and an inverter INV 10  serially connected between an input ST and an output OUT 4 . 
     An input IN 4  is connected to the individual gates of the PMOS transistor PTr 34 , the PMOS transistor PTr 35 , the PMOS transistor PTr 37  and the NMOS transistor NTr 30 . The input ST is connected to the individual gates of the PMOS transistor PTr 33  and the NMOS transistor NTr 28 . The gate of the NMOS transistor NTr 29  is connected to the source terminal. The gate of the PMOS transistor PTr 36  is connected to an output P 2  of a first fuse circuit unit  722  which is to be detailed later. The gate of the PMOS transistor PTr 38  is connected to an output P 3  of a second fuse circuit unit  722  which is to be detailed later. 
     At each input first-stage circuit  71 , the speed at which a node “e” connected to the output OUT 4  via the inverter INV 10  shifts to H level is determined by a PMOS transistor unit  711  constituted of the PMOS transistors PTr 34 , PTr 35 , PTr 36 , PTr 37  and PTr 38 . As described above, the input first-stage circuit  71  achieves a structure in which the transistor that determines the input voltage margin is formed in a comb shape and part of the comb-shaped transistor is replaced by the MOS transistors PTr 35  and PTr  36  that are serially connected or the MOS transistors PTr 37  and PTr 38  that are serially connected. 
     The fuse circuit  72  comprises the first fuse circuit  721  connected to the gate of the PMOS transistor PTr 38  and the second fuse circuit  722  connected to the gate of the PMOS transistor PTr 37 , as shown in FIG.  15 . 
     The first fuse circuit  721  is constituted of a PMOS transistor PTr 39 , a fuse f 4  and an NMOS transistor NTr 31  serially connected between the source terminal and the ground terminal, a PMOS transistor PTr 40  connected in parallel to the PMOS transistor PTr 39  and inverters INV 11  and INV 12  serially connected between a node located between the PMOS transistor PTr 39  and the f 4  and an output P 2 . The gates of the PMOS transistor PTr 39  and the NMOS transistor NTr 31  are connected to an input ST. The gate of the PMOS transistor PTr 40  is connected to a node located between the inverters INV 11  and INV 12 . The input ST is a signal identical to that generated in the first embodiment. 
     The second fuse circuit  722  is constituted of a PMOS transistor PTr 41 , a fuse f 5  and an NMOS transistor NTr 32  serially connected between the source terminal and the ground terminal, a PMOS transistor PTr 42  connected in parallel to the PMOS transistor PTr 41  and inverters INV 13 , INV 14  and INV 15  serially connected between a node located between the PMOS transistor PTr 41  and the fuse f 5  and an output P 3 . The gates of the PMOS transistor PTr 41  and the NMOS transistor NTr 32  are connected to the input ST. The gate of the PMOS transistor PTr 42  is connected to a node located between the inverters INV 13  and INV 14 . 
     The fuse circuit  72  described above achieves a circuit structure that enables control of the outputs P 2  and P 3  so that they output either H level or L level in conformance to whether or not the fuses f 4  and f 5  are disconnected. The following is an explanation of changes occurring in the operation in conformance to the connected/disconnected states of the fuses f 4  and f 5 . 
     First, a state in which neither the f 4  or the fuse f 5  is disconnected is explained. When the specific length of time has elapsed after a power-up, the input ST of the fuse circuit  72  shifts to H level. In the first fuse circuit  721 , with the NMOS transistor NTr 31 , whose source is connected to the ground terminal entering an ON state, the output P 2  shifts to L level via the f 4  and the inverters INV 11  and INV 12 . In the second fuse circuit  722 , with the NMOS transistor NTr 32 , whose source is connected to the ground terminal entering an ON state, the output P 3  shifts to H level via the fuse f 5  and the inverters INV 13 , INV 14  and INV 15 . When the output P 2  is at L level and the output P 3  is at H level, the PMOS transistor PTr 36  becomes set to ON and the PMOS transistor PTr 38  is set to OFF at the input first-stage circuit  71 . In this case, the capable of the PMOS transistor unit  711  that determines the speed at which the node “e” shifts to H level corresponds to the total of the capability of the PMOS transistor PTr 34  and the capability of the PMOS transistor PTr 35 . 
     Next, a state in which the fuse f 4  is disconnected but the fuse f 5  is not disconnected is explained. Until the specific length of time elapses after a power-up, the input ST at the fuse circuit  72  remains at L level. In the first fuse circuit  721 , with the PMOS transistor PTr 39  whose source is connected to the source terminal entering an ON state, the output P 2  shifts to H level via the inverters INV 11  and INV 12 . At this time, the PMOS transistor PTr 40 , which is connected to the source terminal, also enters an ON state. In the second fuse circuit  722 , the output P 3  shifts to H level as described above. When the output P 2  is at H level and the output P 3  is at H level, the PMOS transistor PTr 36  becomes set to OFF and the PMOS transistor PTr 38  also becomes set to OFF at the input first-stage circuit  71 . In this case, the capability of the PMOS transistor unit  711  that determines the speed with which the node “e” shifts to H level corresponds to the capability of the PMOS transistor PTr 34  alone. 
     Next, a state in which the f 4  is not disconnected but the fuse f 5  is disconnected is explained. As described earlier, the output P 2  shifts to L level in the first fuse circuit  721 . In addition, until the specific length of time elapses after a power-up, the input ST of the fuse circuit  72  remains at L level. In the second fuse circuit, with the PMOS transistor PTr 41  connected to the source terminal entering an ON state, the output P 4  shifts to L level via the inverters INV 13 , INV 14  and INV 15 . At this time, the PMOS transistor PTr 42 , which is connected to the source terminal, too, becomes set to ON. When the output P 2  is at L level and the output P 3  is at L level, the PMOS transistor PTr 36  becomes set to ON and the PMOS transistor PTr 38  also becomes set to ON at the input first-stage circuit  71 . In this case, the capability of the PMOS transistor unit  711  that determines the speed at which the node “e” shifts to H level corresponds to the total of the capabilities of the PMOS transistor Ptr 34 , the PMOS transistor PTr 35  and the PMOS transistor PTr 37 . 
     As explained above, in this embodiment, by providing the fuse circuit  72  having the fuse f 4  and the fuse f 5 , which can be easily disconnected by a laser beam, the gate widths W that determine the input voltage margins at the input first-stage circuits can be adjusted all at once. Thus, the length of machining time can be reduced compared to that required in the prior art technology that employs an FIB apparatus to disconnect wiring. 
     (Eighth Embodiment) 
     A semiconductor memory  80  in the eighth embodiment is explained in reference to FIG.  16 . As shown in FIG. 16, the semiconductor memory  80  comprises a plurality of input first-stage  71  and fuse circuits  72  each provided in correspondence to one of the input first-stage  71 . It is to be noted that since the structural features and the operations achieved in the input first-stage  71  and the fuse circuit  72  are identical to those achieved in the seventh embodiment, their explanation is omitted. 
     As described above, in the embodiment in which the fuse circuit  72  are provided each in correspondence to one of the input first-stage  71 , the gate width W can be adjusted at each input first-stage  71 . 
     (ninth Embodiment) 
     A semiconductor memory  90  in the ninth embodiment is explained in reference to FIGS.  17 ˜ 19 . The semiconductor memory  90  comprises a plurality of output circuits  81  and a fuse circuit  82  shared by the individual output circuits  81 , as illustrated in FIG.  17 . 
     As shown in FIG. 18, the output circuits  81  are each constituted of a pre-driver circuit unit  811  and an output buffer circuit unit  812 . The output buffer circuit unit  812  comprises a PMOS transistor PTr 49  for H level output and an NMOS transistor NTr 39  for L level output. The pre-driver circuit unit  811  comprises a first pre-driver portion  813  that drives the PMOS transistor PTr 49  in the output buffer circuit unit  812  at the following stage and a second predriver portion  814  that drives the NMOS transistor NTr 39  in the output buffer circuit unit  812  at the following stage. 
     The first pre-driver portion  813  is constituted of a PMOS transistor PTr 43  and an NMOS transistor NTr 33  that are serially connected between the source terminal and the ground terminal, an NMOS transistor NTr 34  connected in parallel to the NMOS transistor NTr 38 , a transfer gate TG 2  which is connected between an input IN 1  and the NMOS transistor  34  and comprises a PMOS transistor PTr 44  and an NMOS transistor NTr 35  and an NMOS transistor NTr 36  which is connected to the gate (a node “f”) of the NMOS transistor NTr 34 . The gate of the NMOS transistor NTr 35  is connected to an output N 3  of a first fuse circuit  821  which is to be detailed later. The gate of the NMOS transistor NTr 36  and the gate of the PMOS transistor PTr 44  are both connected to an output P 4  of the first fuse circuit  821  to be detailed later. 
     Thus, in the first pre-driver portion  813 , the transistor that determines its driving capability is formed in a comb shape and part of the comb-shaped transistor is replaced by the MOS transistors PTr 43  and NTr 33  that are serially connected. 
     In addition, the transfer gate TG 2 , which is connected to the gate (the node “f”) of the NMOS transistor NTr 34 , functions as a switch that sets ON/OFF the NMOS transistor NTr 34 . 
     The second pre-driver portion  814  is constituted of a PMOS transistor Ptr 46  and an NMOS transistor NTr 37  that are serially connected between the source terminal and the ground terminal and a PMOS transistor PTr 45  connected in parallel to the PMOS transistor PTr 46 , a transfer gate TG 3 , which is connected between an input IN 2  and the PMOS transistor Ptr 45  and comprises a PMOS transistor PTr 47  and an NMOS transistor NTr 38  and a PMOS transistor PTr 48  which is connected to the gate (a node “f”) of the PMOS transistor PTr 45 . The gate of the PMOS transistor PTr 47  is connected to an output P 5  of a second fuse circuit  822  which is to be detailed later. The gate of the PMOS transistor PTr 48  and the gate of the NMOS transistor NTr 38  are both connected to an output N 4  of the second fuse circuit  822  to be detailed later. 
     Thus, in the second pre-driver portion  814 , the transistor that determines its driving capability is formed in a comb shape and part of the comb-shaped transistor is replaced by the MOS transistors PTr 46  and NTr 37  that are serially connected. 
     In addition, the transfer gate TG 3 , which is connected to the gate (the node “g”) of the PMOS transistor PTr 45 , functions as a switch that sets ON/OFF the PMOS transistor PTr 45 . 
     As shown in FIG. 19, the fuse circuit  82  comprises the first fuse circuit  821  that is connected to the gates of the PMOS transistor PTr 44 , the NMOS transistor NTr 35  and the NMOS transistor NTr 36  in the first pre-driver portion  813  and the second fuse circuit  822  connected to the gates of the PMOS transistor PTr 47 , the NMOS transistor NTr 38  and the PMOS transistor PTr 48  in the second pre-driver driver portion  814 . 
     The first fuse circuit  821  is constituted of a PMOS transistor PTr 49 , a fuse f 6  and an NMOS transistor NTr 39  serially connected between the source terminal and the ground terminal, a PMOS transistor PTr 50  connected in parallel to the PMOS transistor PTr 49  and inverters INV 16 , INV 17  and INV 18  serially connected between a node located between the PMOS transistor PTr 49  and the fuse f 6  and the output N 3 . The gates of the PMOS transistor PTr 49  and the NMOS transistor NTr 39  are connected to an input ST. The gate of the PMOS transistor PTr 50  is connected to a node located between the inverters INV 16  and INV 17 . A node located between the inverters INV 17  and INV 18  is connected to the output P 4 . 
     The second fuse circuit  822  is constituted of a PMOS transistor PTr 51 , a fuse f 7  and an NMOS transistor NTr 40  serially connected between the source terminal and the ground terminal, a PMOS transistor PTr 52  connected in parallel to the PMOS transistor PTr 51  and inverters INV 19 , INV 20  and INV 21  serially connected between a node located between the PMOS transistor PTr 51  and the fuse f 7  and the output N 4 . The gates of the PMOS transistor PTr 51  and the NMOS transistor NTr 40  are connected to the input ST. The gate of the PMOS transistor PTr 52  is connected to a node located between the inverters INV 19  and INV 20 . A node located between the inverters INV 20  and INV 21  is connected to the output P 5 . 
     The fuse circuit  82  described above achieves a circuit structure that enables control of the outputs N 3 , P 4 , N 4  and P 5  so that they output either H level or L level in conformance to whether or not the fuses f 6  and f 7  are disconnected. The following is an explanation of changes occurring in the operation in conformance to the connected disconnected states of the fuses f 6  and f 7 . 
     First, a state in which neither the fuse f 6  or the fuse f 7  is disconnected is explained. When the specific length of time has elapsed after a power-up, the input ST of the fuse circuit  82  shifts to H level. In the first fuse circuit  821 , with the NMOS transistor NTr 39 , whose source is connected to the ground terminal entering an ON state, the output P 4  shifts to L level via the fuse f 6 , and the inverters INV 16  and INV 17  and also the output N 4  shutter shifts to H level via the inverter INV 18 . In the second fuse circuit  822 , with the NMOS transistor NTr 40 , whose source is connected to the ground terminal entering an ON state, the output P 5  shifts to L level via the fuse f 7  and the inverters INV 19  and INV 20  and also, the output N 4  shifts to H level via the inverter INV 21 . When the output N 3  is at H level, the output P 4  is at L level, the output N 4  is at H level and the output P 5  is at L level, the transfer gates TG 2  and TG 3  are set to ON and the NMOS transistor NTr 36  and the PMOS transistor PTr 48  are set to OFF at the output circuit  81 . In this case, the NMOS transistor NTr 34  and the PMOS transistor PTr 45  are set ON/OFF respectively in response to shifts occurring in the inputs IN 1  and IN 2 . 
     Next, a state in which the fuse f 6  is disconnected but the fuse f 7  is not disconnected is explained. Until the specific length of time elapses after a power-up, the input ST at the fuse circuit  82  remains at L level. In the first fuse circuit  821 , with the PMOS transistor PTr 49  whose source is connected to the source terminal entering an ON state, the output P 4  shifts to H level via the inverters INV 16  and INV 17  and also the output N 3  shifts to L level via the inverter INV 18 . In the second fuse circuit  822 , the output N 4  shifts to H level and the output P 5  shifts to L level as described above. When the output N 3  is at L level, the output P 4  is at H level, the output N 4  is at H level and the output P 5  is at L level, the transfer gate TG 2  is set to OFF, the transfer gate TG 3  is set to ON, the NMOS transistor NTr 36  is set to ON and the PMOS transistor PTr 48  is set to OFF at the output circuit  81 . In this case, since the node “f” is at L level at the first pre-driver portion  813 , the NMOS transistor NTr 34  remains in an OFF state in spite of the shift occurring in the input signal IN 1  and, as a result, the capability for driving the PMOS transistor PTr 49  of the pre-driver unit  812  at the following stage corresponds to the capability of the NMOS transistor NTr 33  alone. 
     Now, a state in which the fuse f 6  is not disconnected but the fuse f 7  is disconnected is explained. As explained earlier, the output N 3  shifts to H level and the output P 4  shifts to L level in the first fuse circuit  821 . In addition, until the specific length of time elapses after a power-up, the input ST at the fuse circuit  82  remains at L level. In the second fuse circuit  822 , with the PMOS transistor PTr 51  whose source is connected to the source terminal entering an ON state, the output P 5  shifts to H level via the inverters INV 19  and INV 20  and also, the output N 4  shifts to L level via the inverter INV 21 . When the output N 3  is at H level, the output P 4  is at L level, the output N 4  is at L level and the output P 5  is at H level, the transfer gate TG 2  is set to ON, the transfer gate TG 3  is set to OFF, the NMOS transistor NTr 36  is set to OFF and the PMOS transistor PTr 48  is set to ON at the output circuit  82 . In this case, since the node “g” is at H level at the second pre-driver portion  814 , the PMOS transistor PTr 45  remains in an OFF state in spite of the shift occurring in the input signal IN 2  and, as a result, the capability for driving the NMOS transistor NTr 39  of the pre-driver unit  812  at the following state corresponds to the capability of the PMOS transistor PTr 46  alone. 
     As explained above, in this embodiment, by providing the fuse circuit  82  having the fuses f 6  and f 7  that can be easily disconnected with a laser beam, the gate widths W of the pre-drivers at the output circuits within the chip can be adjusted all at once. Thus, the length of machining time can be reduced compared to that required in the prior art technology that employs an FIB apparatus to disconnect wiring. In this regard, it achieves an advantage identical to that achieved in the first embodiment. 
     However, while two transistors are serially connected at the pre-driver unit to be adjusted and, therefore, the layout area increases greatly if the gate width W at the pre-driver unit undergoing adjustment increases in the first embodiment, a layout area which is approximately only half of that accounted for by the pre-driver unit in the first embodiment is required even when the gate width W at the pre-driver unit increases in this embodiment. In addition, since the presence of the CMOS transfer gates does not result in a great increase in the layout area in the embodiment, the overall layout area can be minimized, thereby achieving an advantage of preventing an increase within the chip area. 
     While the invention has been particularly shown and described with respect to preferred embodiments of the semiconductor memory according to the present invention by referring to the attached drawings, the present invention is not limited to these examples and it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit, scope and teaching of the invention. 
     As explained above, according to the present invention, by providing a fuse circuit having a fuse that can be easily disconnected with a laser beam, the gate widths W of the pre-drivers at the output circuit units, the amplifier circuits, the delay circuits or the input first-stage circuits in a chip can be adjusted all at once. Thus, the length of machining time can be reduced compared to that required in the prior art technology that employs an FIB apparatus to disconnect wiring. In addition, the present invention, which minimizes the layout area is particularly effective in preventing an increase within the chip area. 
     (tenth Embodiment) 
     A semiconductor memory  100  in the tenth embodiment is explained in reference to FIG.  20 . As shown in FIG. 20, the semiconductor memory  100  comprises a plurality of output circuits  81  and fuse circuits  82  each provided in correspondence to one of the output circuits  81 . It is to be noted that since the structural features and the operations achieved in the output circuits  81  and the fuse circuit  82  are identical to those achieved in the ninth embodiment, their explanation is omitted. 
     As described above, in the embodiment in which the fuse circuit  82  are provided each in correspondence to one of the output circuits  81 , the gate width W can be adjusted at each output circuit  81 .