Abstract:
There is provided a charge domain filter device including a plurality of transconductors each of which converts an input voltage to a current and outputs the current and a filter unit that filters output signals from said plurality of transconductors by repeatedly charging and discharging a plurality of capacitors, wherein an impulse response of the charge domain filter device is obtained through convolution of a first impulse corresponding to a charge time length over which said capacitors are charged and a second impulse corresponding to each of said plurality of transconductors.

Description:
CROSS REFERENCE TO RELATED APPLICATION  
       [0001]     The present invention contains subject matter related to Japanese Patent Application No. JP 2006-187057 filed in the Japan Patent Office on Jul. 6, 2006, the entire contents of which being incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a filter device designed by charge domain operations (hereinafter, called a charge domain filter device).  
         [0004]     2. Description of the Related Art  
         [0005]     An SoC (system-on-chip) used in wireless communication, which is achieved by embedding an RF (radio frequency: high frequency) circuit and a digital circuit in a single CMOS (complementary metal oxide semiconductor) circuit chip, needs to allow the RE circuit to be provided as a compact unit and assure better energy efficiency in the RE circuit. In order to respond to these needs, the development of filtering and decimation technologies achieved through adoption of analog discrete-time signal processing technologies such as current mode sampling with a high-speed clock and switched capacitor circuits as disclosed in non-patent Reference Literature 1, is being actively pursued.  
         [0006]     In addition, a charge domain filter circuit that includes only a transconductor and a switch to form a SINC filter circuit, the frequency characteristics of which assume SINC function characteristics without utilizing an operational amplifier, has been proposed as disclosed in Nonpatent Reference Literature 2 or Nonpatent Reference Literature 3. Since the filter in such a charge domain filter circuit is constituted with a transconductor and a switch alone, an RF signal in the GHz band can be directly sampled or filtered with the charge domain filter circuit. The following is a description of a charge domain filter circuit forming a SINC filter circuit.  
         [0007]      FIG. 17  shows the structure adopted in a charge domain filter circuit forming a SINC filter circuit in the related art. As shown in FIG.  17 , a charge domain filter circuit  10  forming a SINC filter circuit, proposed in the related art, includes a transconductor  12 , a first switch  14 , a second switch  16 , a third switch  18 , and capacitors  20   a ,  20   b ,  20   c  and  20   d.    
         [0008]      FIG. 18  presents a timing chart of the clock signals applied to the charge domain filter circuit  10  shown in  FIG. 17 . Four clock signals Ø 1 , Ø 2 , Ø 3  and Ø 4  in  FIG. 18 , in different phases, are used to control the operations of the first switch  14 , the second switch  16  and the third switch  18  in the charge domain filter circuit  10 .  
         [0009]     The transconductor  12  outputs a current in proportion to the voltage of an input signal.  
         [0010]     A specific capacitor to be charged by applying the current output from the transconductor  12  is selected via the first switch  14 . In the charge domain filter circuit  10  shown in  FIG. 17 , the first switch  14  is switched to a specific terminal based upon the four types of clock signals Ø 1 , Ø 2 , Ø 3  and Ø 4  and the capacitor corresponding to the selected terminal is charged.  
         [0011]     A specific capacitor to be initialized by purging the residual charge is selected via the second switch  16 . The second switch  16  is switched to a specific terminal based upon the four types of clock signals Ø 1 , Ø 2 , Ø 3  and Ø 4  in the charge domain filter circuit  10  in  FIG. 17 . The capacitor corresponding to the terminal selected at the second switch  16  is grounded and initialized by purging the residual electrical charge so as to purge the capacitor of any residual charge attributable to a previous signal.  
         [0012]     A specific capacitor holding an electrical charge stored therein to be output to a circuit at a rear stage is selected via the third switch  18 . The third switch  18  is switched to a specific terminal based upon the four types of clock signals Ø 1 , Ø 2 , Ø 3  and Ø 4  and as the specific terminal is selected, the electrical charge stored at the corresponding capacitor is output to the circuit at the rear stage in the charge domain filter circuit  10  shown in  FIG. 17 .  
         [0013]     The terminals Ø 1 , Ø 2 , Ø 3  and Ø 4  at each of the switches, i.e., the first switch  14 , the second switch  16  and the third switch  18 , become connected when the corresponding clock signals Ø 1 , Ø 2 , Ø 3  and Ø 4  enter the ON state.  
         [0014]     The current output from the transconductor  12 , which is in proportion to the voltage of the input signal, is applied over the time length t to one of the capacitors, selected via the first switch  14 , is integrated at the capacitor over the time length t, and is stored as an electrical charge. Then, the charge stored at the selected capacitor is output to the circuit at the rear stage for sampling. For instance, as the first switch  14  is controlled with the clock signal Ø 1  and the first capacitor  20   a  is charged with the current output from the transconductor  12 , the third switch  18  is controlled with the clock signal Ø 2  to output the stored electrical charge to the circuit at the rear stage. Subsequently, the second switch is controlled with the clock signal Ø 4  to ground the first capacitor  20   a  and, as a result, the residual charge is released and the first capacitor becomes initialized.  
         [0015]     The capacitors  20   a ,  20   b ,  20   c  and  20   d  are each repeatedly engaged in sampling operations over time intervals t in response to the operations of the first switch  14 , the second switch  16  and the third switch  18 . Thus, the input signal is sampled with a rectangular time window t and since a notch occurs at a position corresponding to an integral multiple of 1/t due to the frequency characteristics, the charge domain filter circuit  10  is able to function as a SINC filter. For instance, assuming that t=1 ns, a notch occurs at 1 GHz (i.e., at a position corresponding to an integral multiple of 1/t) and the charge domain filter circuit  10  is able to function as a SINC filter achieving frequency characteristics such as those shown in  FIG. 19 .  
         [0016]     (Nonpatent Reference Literature 1) L. Richard Carley and Tamal Mukherjee, “High-Speed Low-Power Integrating CMOS Sample-and-Hold Amplifier Architecture,” Proceedings of IEEE 1995 Custom Integrated Circuits Conference, pp 543˜546, May 1995  
         [0017]     (Nonpatent Reference Literature 2) J. Yuan, “A Charge Sampling Mixer With Embedded Filter Function for Wireless Applications” proceedings of IEEE 2000 International Conference on Microwave and Millimeter Wave Technology, pp 315˜318, Sept. 2000  
         [0018]     (Nonpatent Reference Literature 3) A. Mirzaie, R. Bagheri, S. Cherazi and A. A. Abidi “A Second-Order Antialiasing Prefilter for an SDR Receiver”, Proceedings of IEEE 2005 Custom Integrated Circuits Conference, pp 629˜632, Sept. 2005  
       SUMMARY OF THE INVENTION  
       [0019]     However, the charge domain SINC filter circuits in the related art fail to achieve superior characteristics as low pass filters. For instance, assuming that the sampling cycle t of the SINC filter circuit in the related art shown in  FIG. 17  is 1 ns, a concern arises in that the second lobe over a frequency range of 1/t˜1/2t, i.e., over a range of 1 GHz˜2 GHz, may be as large as —13 dB.  
         [0020]     Higher-order filtering is difficult to be achieved without altering the sampling rate in a charge domain filter circuit. While the low-range component characteristics are improved in the method disclosed in Nonpatent Reference literature 3 with the frequency characteristics raised to the second power of the SINC, its application range is still very limited since, unlike an FIR (finite impulse response) filter, it does not allow the frequency characteristics to be adjusted freely.  
         [0021]     This means that a reconfigurable RF circuit cannot be designed and thus, if a plurality of wireless communication services with varying mean frequencies or varying bandwidths are to be used at a single terminal, the terminal will need to be equipped with filter circuits in a quantity matching the number of services to be subscribed to. This, in turn, poses a difficulty in scaling back the RF circuit and ultimately results in the overall device assuming a large scale configuration.  
         [0022]     Accordingly, the present invention, which has been completed by addressing the issues discussed above, provides a new and improved charge domain filter circuit that is able to efficiently pass a low-range component and, at the same time, allows the frequency characteristics thereof to be adjusted freely.  
         [0023]     According to an embodiment of the present invention, there is provided a charge domain filter device. The charge domain filter device includes a plurality of transconductors each of which converts an input voltage to a current and outputs the current a filter unit that filters output signals from the plurality of transconductors by repeatedly charging and discharging a plurality of capacitors. The charge domain filter device is characterized in that the charge domain filter device having an impulse response is obtained therein through convolution of a first impulse corresponding to the capacitor charge time length and a second impulse corresponding to each of the plurality of transconductors and that the first impulse is weighted.  
         [0024]     In the charge domain filter device adopting the structure described above, the input voltage is converted to a current value at each of the plurality of transconductors and the output signals from the transconductors are filtered at the filter unit. Since the impulse response of the charge domain filter device is obtained through convolution of the first impulse and the second impulse, the frequency characteristics can be adjusted freely by altering the charge time length and the weight applied to the transconductance.  
         [0025]     A signal obtained through convolution of the first impulse with the second impulse may be input to the filter unit, and such convolution may be achieved by slicing out the output currents from the plurality of transconductors with a plurality of rectangular windows assuming varying phases and then calculating the sum of the output currents. In this case, the impulse response corresponding to a specific weight applied to the transconductance is achieved by slicing out the output currents from the plurality of transconductors with the plurality of rectangular windows assuming varying phases and then calculating their sum. As a result, since the impulse response corresponding to the weight applied to the transconductance, achieved by calculating the sum of the output currents from the transconductors, can be varied, the frequency characteristics of the charge domain filter device can be adjusted.  
         [0026]     The convolution may be achieved by adding up the electrical charges at the capacitors sampled by the filter unit at varying phases. In such a structure, the impulse response corresponding to the charge time length can be achieved by calculating the sum of electrical charges sampled at different phases. As a result, since the impulse response corresponding to the charge time length, achieved by calculating the sum of the charges sampled at different phases, can be varied, the frequency characteristics of the charge domain filter device can be adjusted.  
         [0027]     The charge domain filter device may further include a switch unit disposed between the plurality of transconductors and the filter unit. The switch unit in such a charge domain filter device opens/closes a switch thereof with predetermined timing so as to control application of the output currents from the plurality of transconductors to the filter unit. Consequently, the charge domain filter device achieved in an embodiment of the present invention can be engaged in band pass charge sampling whereby signals are filtered over a specific bandwidth  
         [0028]     According to the embodiments of the present invention described above, a new and improved charge domain filter device, capable of efficiently passing the low-range component, which also allows the frequency characteristics thereof to be adjusted freely, can be provided. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0029]      FIG. 1  shows the charge domain filter circuit achieved in a first embodiment of the present invention;  
         [0030]      FIG. 2  is a chart of clock signals input to the charge domain filter circuit in the first embodiment of the present invention;  
         [0031]      FIG. 3  shows how an impulse response may be obtained in the charge domain filter circuit in the first embodiment of the present invention;  
         [0032]      FIG. 4  is a diagram of a frequency response that may be obtained in the charge domain filter circuit in the first embodiment of the present invention;  
         [0033]      FIG. 5  shows how an impulse response that may be obtained in the charge domain filter circuit in the first embodiment of the present invention;  
         [0034]      FIG. 6  is a diagram of the frequency response obtained in the charge domain filter circuit in conjunction with the impulse response in  FIG. 5 ;  
         [0035]      FIG. 7  shows the charge domain filter circuit achieved in a second embodiment of the present invention:  
         [0036]      FIG. 8  is a chart of clock signals input to the charge domain filter circuit in the second embodiment of the present invention;  
         [0037]      FIG. 9  shows an example of impulse response;  
         [0038]      FIG. 10  shows another example of impulse response;  
         [0039]      FIG. 11  is a diagram of the frequency response obtained in the charge domain filter circuit in conjunction with the impulse for spots in  FIG. 10 ;  
         [0040]      FIG. 12  shows yet another example of impulse response;  
         [0041]      FIG. 13  is a diagram of the frequency response obtained in the charge domain filter circuit in conjunction with the impulse response in  FIG. 12 ;  
         [0042]      FIG. 14  shows yet another example of impulse response;  
         [0043]      FIG. 15  is a diagram of the frequency response obtained in the charge domain filter circuit in conjunction with the impulse for spots in  FIG. 14 ;  
         [0044]      FIG. 16  shows the charge domain filter circuit achieved in the third embodiment of the present invention;  
         [0045]      FIG. 17  shows the structure adopted in a charge domain filter circuits forming a SINC filter circuit in the related art;  
         [0046]      FIG. 18  is a timing chart of clock signals applied to the charge domain filter circuit in the related art; and  
         [0047]      FIG. 19  is a diagram of the frequency characteristics of the charge domain filter circuit in the related art.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0048]     Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the appended drawings. Note that, in this specification and the appended drawings, structural elements that have substantially the same function and structure are denoted with the same reference numerals, and repeated explanation of these structural elements is omitted.  
       FIRST EMBODIMENT  
       [0049]     First, the charge domain filter circuit achieved in the first embodiment of the present invention is described.  
         [0050]      FIG. 1  shows the charge domain filter circuit achieved in the first embodiment of the present invention. As shown in  FIG. 1  the charge domain filter circuit  100  in the first embodiment of the present invention includes transconductors  102 ,  104 ,  106  and  108 , switches  110   a ,  110   b ,  110   c  and  110   d , adders  112   a  and  112   b  and a SINC filter circuit  120 .  
         [0051]     The SINC filter circuit  120  includes first switches  122   a  and  122   b , a second switch  124 , a third switch  126  and capacitors  128   a ,  128   b ,  128   c  and  128   d.    
         [0052]     The transconductors  102 ,  104 ,  106  and  108  each output a current in proportion to the voltage of an input signal. While four transconductors are used to constitute the charge domain filter circuit in the embodiment, the number of transconductors in a charge domain filter circuit embodying the present invention is not limited to four. In addition, the transconductors may assume transconductance values equal to one another or they may assume transconductance values different from one another. The following explanation is provided by assuming that the four transconductors all assume transconductance values equal to one another.  
         [0053]     Via the switches  110   a ,  110   b ,  110   c  and  110   d , the adder to which the output from a given transconductor is to be input is selected. At the switches  110   a ,  110   b ,  110   c  and  110   d , terminals are selected at using clock signals in different phases. While terminal changeovers at the individual switches are achieved by using eight types of clock signals with varying phases in the embodiment, the present invention may be adopted in conjunction with a different number of switches.  
         [0054]     The adders  112   a  and  112   b  each calculate the sum of the outputs from the transconductors and output the sum. The specific transconductors, the outputs of which are to be added together, are selected via the switches  110   a ,  110   b ,  110   c  and  110   d.    
         [0055]     The SINC filter circuit  120  filters a signal input thereto and provides the filtered output. The SINC filter circuit  120  executes the filtering operation by using two input signals.  
         [0056]     The first switches  122   a  and  122   b  are each used to select a capacitor to be charged. Either the capacitor  128   a  or the capacitor  128   c  is selected via the first switch  122   a , whereas either the capacitor  128   b  or the capacitor  128   d  is selected via the first switch  122   b . At the first switches  122   a  and  122   b  are switched to specific terminals based upon four types of clock signals with varying phases.  
         [0057]     A specific capacitor to undergo initialization is selected via the second switch  124 . The specific capacitor in the SINC filter circuit  120  to be initialized so as to purge the residual charge therein is selected through the second switch  124 . The second switch  124  is switched to a specified terminal based upon four types of clock signals in the charge domain filter circuit  100  in the first embodiment of the present invention. As the second switch  124  is connected to a given terminal, the capacitor connected to the selected terminal is initialized so as to purge the capacitor of any residual charge attributable to a previous signal.  
         [0058]     A specific capacitor holding an electrical charge to be output to a circuit at a rear stage is selected via the third switch  126 . One of the capacitors in the SINC filter circuit  120 , the electrical charge of which, having been stored therein is to be output to the circuit at the rear stage, is selected through the third switch  126 . The third switch is switched to connect with one of terminals based upon four types of clock signals and the electrical charge stored at the capacitor connected to the selected terminal is output to the circuit at the rear stage in the charge domain filter circuit  100  in the first embodiment of the present invention.  
         [0059]     Electrical charges are stored at the capacitors  128   a ,  128   b ,  128   c  and  128   d . The electrical charges are stored with currents output from the transconductors. It is desirable that the capacities of the capacitors  128   a ,  128   b ,  128   c  and  128   d  be equal to one another.  
         [0060]     Next, the operations executed in the charge domain filter circuit in the first embodiment of the present invention, adopting the structure described above, are explained  
         [0061]      FIG. 2  presents a chart of the clock signals input to the charge domain filter circuit in the first embodiment of the present invention. As shown in  FIG. 2 , 16 types of clock signals are input to the charge domain filter circuit in the first embodiment of the present invention. The following is an explanation of the clock signals input to the charge domain filter circuit in the first embodiment of the present invention.  
         [0062]     Clock signals Ø W0 , Ø W45 , Ø W90 , Ø W135 , Ø W180 , Ø W225 , Ø W270  and Ø W313  are input to the switches  110   a ,  110   b ,  110   c  and  110   d . The clock signals Ø W0  and Ø W180  are input to the switch  110   a , the clock signals Ø W45  and Ø W225  are input to the switch  110   b , the clock signals Ø W90  and Ø W270  are input to the switch  110   c  and the clock signals Ø W135  and Ø W315  arc input to the switch  110   d.    
         [0063]     The pairs of clock signals Ø W0  and Ø W180 , clock signals Ø 45  and Ø W225 , clock signals Ø W90  and Ø W270 , and clock signals Ø W135  and Ø W315  each maintain a specific ON/OFF relationship. Namely, while the clock signal is in the ON state, the clock signal Ø W180  sustains the OFF state. Likewise, while the clock signal Ø 45  is in the ON state, the clock signal Ø W225  sustains the OFF state, while the clock signal Ø W90  is in the ON state, the clock signal Ø W270  sustains the OFF state and while the clock signal Ø W135  is in the ON state, the clock signal Ø W315  sustains the OFF state.  
         [0064]     As two types of clock signals are input to each switch as described above, the terminals at the switch can be switched over from one to the other.  
         [0065]     The clock signals are input to the charge domain filter circuit achieved in the first embodiment of the present intention as described above. Next, the operations executed at the various units of the charge domain filter circuit, in response to the clock signals input to the charge domain filter circuit, are explained.  
         [0066]     The switch  110   a  connects with the terminal corresponding to the clock signal Ø W0  as the clock signal Ø W0  enters the ON state. Then, as the clock signal Ø W0 , having been in the ON state over a time length t, enters the OFF state and the clock signal Ø W180  enters the ON state, the switch  110   a  connects with the terminal corresponding to the clock signal Ø W180 .  
         [0067]     A specific terminal is selected at each of the other switches with two types of clock signals. Namely, the switch  110   b  connects with the terminal corresponding to the clock signal Ø W45  as the clock signal Ø W45  enters the ON state. Then, as the clock signal Ø W45 , having been in the ON state over a time length t, enters the OFF state and the clock signal Ø W225  enters the ON state, the switch  110   a  connects with the terminal corresponding to the clock signal Ø W225 .  
         [0068]     Likewise, the switch  110   c  connects with the terminal corresponding to the clock signal Ø W90  as the clock signal Ø W90  enters the ON state, whereas the switch  110   d  connects with the terminal corresponding to the clock signal Ø W135  as the clock signal Ø W135  enters the ON state. Then, as the clock signal Ø W90 , having been in the ON state over the time length t enters the OFF state and the clock signal Ø W270  enters the ON state, the switch  110   c  connects with the terminal corresponding to the clock signal Ø W270 . Likewise, as the clock signal Ø W135 , having been in the ON state over the time length t enters the OFF state and the clock signal Ø W135  enters the ON state, the switch  110   d  connects with the terminal corresponding to the clock signal Ø W270 .  
         [0069]     The outputs from the switches  110   a ,  110   b ,  110   c  and  110   d  are input to either the adder  112   a  or the adder  112   b . Namely, the signals to be added up our selected in correspondence to the ON/OFF state of the clock signals input to the individual switches.  
         [0070]     For instance, if the clock signals Ø W0 , Ø W45 , Ø W90  and Ø W135  are in the ON state, the outputs from the four transconductors are all input to the adder  112   a . If, on the other hand, the clock signals Ø W0 , Ø 45 , Ø W270  and Ø W315  are in the ON state, the outputs from the transconductors  102  and  104  are input to the adder  112   a  and the outputs from the transconductors  106  and  108  are input to the adder  112   b.    
         [0071]     Gm_phase  1  in  FIG. 2  indicates the relationship between the level of the signal output from the adder  112   a  and the time length, whereas Gm_phase  2  in  FIG. 2  indicates the relationship between the level of the signal output from the adder  112   b  and the time length. As Gm_phase  1  and Gm_phase  2  indicate, the outputs from the adders  112   a  and  112   b  change in stages over time.  
         [0072]     For instance, when the signals Ø W0 , Ø W45 , Ø W90  and Ø W135  are in the ON state, the outputs from the four transconductor are all input to the adder  112   a  and thus, Gm_phase  1  assumes the largest value. When the signals Ø W0 , Ø W45 , Ø W270  and Ø W315  are in the ON state, on the other hand, the outputs from the transconductors  102  and  104  are input to the adder  112   a  and the outputs from the transconductors  106  and  108  are input to the adder  112   b , allowing Gm_phase  1  and Gm_phase  2  to assume values equal to each other.  
         [0073]     By inputting the outputs from the adders  112   a  and  112   b , which change over time, to the SINC filter circuit  120  with predetermined timing, the frequency characteristics of the SINC filter circuit can be improved. The inputs to the SINC filter circuit  120  are controlled via the first switches  122   a  and  122   b  by using clock signal Ø C0 , Ø C90  Ø C180  and Ø C270 . Clock signals Ø C0  and Ø C180  are used in correspondence to each other, whereas the clock signals Ø C90 , and Ø C270  are used in correspondence to each other.  
         [0074]     As the clock signal Ø C0  shifts from the OFF state to the ON state, the first switch  122   a  is connected to the terminal corresponding to the clock signal Ø C0 . As a result the output from the adder  112   a  is input to the capacitor  128   a  and a electrical charge is stored at the capacitor  128   a.    
         [0075]     Since the output from the adder  112   a  changes in steps over time, the current input to the capacitor  128   a  also changes in steps over time.  
         [0076]     The clock signal Ø C0  having been in the ON state over a time length  2   t  then the shifts to the OFF state, and accordingly, the clock signal Ø C180  enters the ON state. The output from the adder  112   a  is thus input to the capacitor  128   c  and an electrical charge is stored at the capacitor  128   c . The current input to the capacitor  128   c , too, changes in stages as does the current input to the capacitor  128   a.    
         [0077]     When the clock signal Ø C180  has been held in the ON state over a time length  2   t , the clock signal Ø C180  shifts to the OFF state and the clock signal Ø C0  enters the ON state. As the clock signal Ø C0  and the clock signal Ø C180  are alternately switched to the ON/OFF states over cycles  2   t , as described above, the capacitor  128   a  and  128   c  are repeatedly charged.  
         [0078]     As the clock signal Ø C90  shifts from the OFF state to the ON state, the other first switch  122   b  is connected to the terminal corresponding to the clock signal Ø C90 . As a result, the output from the adder  112   b  is input to the capacitor  128   b  and an electrical charge is stored at the capacitor  128   b . Since the output from the adder  112   a , changes input steps over time, as does the output from the adder  112   a , the current input to the capacitor  128   b  also changes in steps over time.  
         [0079]     The clock signal Ø C90  having been in the ON state over the time length  2   t  then the shifts to the OFF state, and accordingly, the clock signal Ø C270  enters the ON state. The output from the adder  112   b  is thus input to the capacitor  128   d  and an electrical charge is stored at the capacitor  128   d . The current input to the capacitor  128   d , too, changes in stages as does the current input to the capacitor  128   b.    
         [0080]     The electrical charges having been stored at the capacitors  128   a ,  128   b ,  128   c  and  128   d  are output to the circuit at the rear stage via the third switch  126 . The charge output timing is controlled by using four clock signals Ø 1 , Ø 2 , Ø 3  and Ø 4 .  
         [0081]     For instance, after the clock signal Ø C0  shifts from the ON state to the OFF state, the clock signal Ø 1  shifts from the OFF state to the ON state, thereby connecting in the third switch  126  to the terminal corresponding to the clock signal Ø 1 . In response, the charge stored at the capacitor  128   a  is output to the circuit at the rear stage through the third switch  126 .  
         [0082]     The clock signal Ø 1  having been in the ON state over the time length t then shifts from the ON state to the OFF state. As the clock signal Ø 1  is turned off, the clock signal Ø 2  enters in ON state. As the clock signals Ø 2  shifts into the ON state, the third switch  126  is connected to the terminal corresponding to the clock, signal Ø 2 . In response, the charge stored at the capacitor  128   b  is output to the circuit at the rear stage through the third switch  126 .  
         [0083]     An electrical charge is stored at the capacitor  128   b  with the current output from the adder  112   b  when the first switch  122   b  is connected to the terminal corresponding to the clock signal Ø C90 . The clock signal Ø C90  shifts from the ON state to the OFF state with the timing with which the clock signal Ø 2  is switched from the OFF state to the ON state. Accordingly, as the clock signal Ø 2  shifts into the ON state, the electrical charge stored at the capacitor  128   b  in response to the switchover of the clock signal Ø C90  to the ON state is output to the circuit at the rear stage through the third switch  126 .  
         [0084]     The clock signal Ø 2  having been in the ON state over the time length t then shifts from the ON state to the OFF state. As the clock signal Ø 2  is turned off, the clock signal Ø 3  enters in ON state. As the clock signal Ø 3  shifts into the ON state, the third switch  126  is connected to the terminal corresponding to the clock signal Ø 3 . In response, the charge stored at the capacitor  128   c  is output to the circuit at the rear stage through the third switch  126 .  
         [0085]     An electrical charge is stored at the capacitor  128   c  with the current output from the adder  112   a  when the first switch  122   a  is connected to the terminal corresponding to the clock signal Ø C180 . The clock signal Ø C180  shifts from the ON state to the OFF state with the timing with which the clock signal Ø 3  is switched from the OFF state to the ON state. Accordingly, as the clock signal Ø 3  shifts into the ON state, the electrical charge stored at the capacitor  128   c  in response to the switchover of the clock signal Ø C180  to the ON state is output to the circuit at the rear stage through the third switch  126 .  
         [0086]     When the time length t elapses following the switchover of the clock signal the clock signal Ø 3  from the OFF state to the ON state, the clock signal Ø 3  shifts from the ON state to the OFF state. As the clock signal Ø 3  is turned off, the clock signal Ø 4  enters in ON state. As the clock signal Ø 4  shifts into the ON state, the third switch  126  is connected to the terminal corresponding to the clock signal Ø 4 . In response, the charge stared at the capacitor  128   d  is output to the circuit at the rear stage through the third switch  126 .  
         [0087]     An electrical charge is stored at the capacitor  128   d  with the current output from the adder  112   b  when the first switch  122   b  is connected to the terminal corresponding to the clock signal Ø C270 . The clock signal Ø 270  shifts from the ON state to the OFF state with the timing with which the clock signal Ø 4  is switched from the OFF state to the ON state. Accordingly, as the clock signal Ø 4  shifts into the ON state, the electrical charge stored at the capacitor  128   d  in response to the switchover of the clock signal Ø C270  to the ON state is output to the circuit at the rear stage through the third switch  126 .  
         [0088]     When the time length t elapses following the switchover of the clock signal Ø 4  from the OFF state to the ON state, the clock signal Ø 1  shifts from the ON state to the OFF state. As the clock signals Ø 1 ˜Ø 4  are repeatedly set to the ON/OFF states as described above, the electrical charges having been stored at the capacitors  128   a ,  128   b ,  128   c  and  128   d  are output to the circuit at the rear stage in sequence.  
         [0089]     The capacitors having output the electrical charges therein to the circuit at the rear stage thereof are each grounded so as to initialize it by purging any residual charge in the capacitor. The capacitors are initialized via the second switch  124 .  
         [0090]     When the clock signal Ø 1  shifts into the OFF state and the clock signal Ø 2  shifts into the ON state, the second switch  124  becomes connected to the terminal corresponding to the clock signal Ø 2 . As a result, the capacitor  128   a  is grounded via the second switch  124  and the residual charge in the capacitor  128   a  is discharged for initialization.  
         [0091]     As the clock signal Ø 2 , having been in the ON state over the time length t shifts from the ON state to the OFF state, the clock signal Ø 3  shifts from the OFF state to the ON state. In response to the switchover of the clock signal Ø 3  to the ON state, the second switch  124  is connected to the terminal corresponding to the clock signal Ø 3 . Thus, the capacitor  128   b  becomes grounded via the second switch  124  and the residual charge in the capacitor  128   b  is discharged for initialization.  
         [0092]     As the clock signal Ø 3 , having been in the ON state over the time length t shifts from the ON state to the OFF state the clock signal Ø 4  shifts from the OFF state to the ON state. In response to the switchover of the clock signal Ø 4  to the ON state, the second switch  124  is connected to the terminal corresponding to the clock signal Ø 4 . Thus, the capacitor  128   c  becomes grounded via the second switch  124  and the residual charge in the capacitor  128   c  is discharged for initialization.  
         [0093]     As the clock signal Ø 4 , having been in the ON state over the time length t shifts from the ON state the OFF state, the clock signal Ø 1  shifts from the OFF state to the ON state. In response to the switchover of the clock signal  527    1  to the ON state, the second switch  124  is connected to the terminal corresponding to the clock signal Ø 1 . Thus, the capacitor  128   d  becomes grounded via the second switch  124  and the residual charge in the capacitor  128   d  is discharged for initialization.  
         [0094]     As the clock signals Ø 1 ˜Ø 4  are alternately set to the ON/OFF states repeatedly, the residual charges in the capacitors  128   a ,  128   b ,  128   c  and  128   d  are discharged and the capacitors are thus initialized.  
         [0095]     As explained above, since the capacitors  128   a ,  128   b ,  128   c  and  128   d  are engaged in the charge, the output and the initialization in repeated sequence with the time cycles t, the sampling operation is continuously executed over time cycles t.  
         [0096]     Assuming that the operational sequence starting from the input to the operation at the adder  112   a  constitutes the operation of a single transconductor in the charge domain filter circuit  100  shown in  FIG. 1 , the change in the transconductance is represented by the staged triangular wave with a cycle  2   t , indicated as Gm_phase  1  in  FIG. 2 . Likewise, assuming that the operational sequence starting from the input to the operation at the adder  112   b  constitutes the operation of a single transconductor, the change in the transconductance is represented by the staged triangular wave with a cycle  2   t , indicated as Gm_phase  2  in  FIG. 2 , in a phase different from that of Gm_phase  1 . Accordingly, the continuous time signals sliced out over the triangular wave windows, are integrated at the SINC filter circuit  120  in the charge domain filter circuit  100 .  
         [0097]      FIGS. 3A and 3B  illustrate how impulse response is obtained in the charge domain filter circuit in the first embodiment of the present invention. As explained earlier, the continuous time signals sliced out over at the triangular wave windows are then integrated in the SINC filter circuit  120  in the charge domain filter circuit  100 . This operation is equivalent to the convolution resulting in the triangular wave impulse response shown in  FIG. 3B . In other words, that the charge domain filter circuit  100  operates as an FIR filter.  
         [0098]     The triangular wave impulse response shown in  FIG. 3B  is the result of convolution of the two rectangular impulse shown in  FIG. 3A . One of the rectangular impulses corresponds to the pulse width, whereas the other rectangular impulse correspond to the number of transconductors. Since the pulse width contains four clocks and four transconductors are used in the embodiment, the two rectangular impulses each include four impulse signals.  
         [0099]     Since the two rectangular impulses are convoluted, the frequency response in the charge domain filter circuit  100  manifests characteristics equal to SINC 2 .  FIG. 4  presents a diagram of the frequency response in the charge domain filter circuit  100  in the first embodiment of the present invention achieved by setting the sampling cycle t to 1 ns. As shown in  FIG. 4 , the frequency characteristics in the charge domain filter circuit  100  assume lower values over the second lobe in the frequency range of 1/t˜2/t i.e., in the frequency range of 1 GHz˜2 GHz, compared to the frequency characteristics observed in the SINC filter circuit in the related art shown in  FIG. 19 .  
         [0100]     The frequency characteristics in the charge domain filter circuit  100  achieved in the embodiment of the present invention can be altered by adjusting the levels of transconductance at the transconductors.  
         [0101]      FIGS. 5A and 5B  show how the impulse response in the charge domain circuit in the first embodiment of the present invention may be altered. For instance, if the transconductance at the transconductors  104  and  106  is double the transconductance at the transconductors  102  and  108 , a trapezoidal impulse is generated, as indicated by Gm in FIG.  5 A. Accordingly, the impulse response of the charge domain filter circuit  100  by varying the transconductance manifests as shown in  FIG. 5B , and the charge domain filter circuit  100  achieves frequency characteristics such as those shown in the graph presented in  FIG. 6  under these circumstances.  
         [0102]     As explained earlier, the frequency characteristics can be adjusted freely by weighting the transconductance in the charge domain filter circuit achieved in the first embodiment of the present invention.  
       SECOND EMBODIMENT  
       [0103]     An explanation is given above in reference to the first embodiment of the present invention on a charge domain filter circuit, the frequency characteristics of which can be adjusted freely by controlling the timing with which the currents output from the transconductors are added up. Now, in reference to the second embodiment of the present invention, a charge domain filter circuit, the frequency characteristics of which can be adjusted freely by controlling the timing with which the electrical charges output from SINC filter circuits are added up, is described.  
         [0104]      FIG. 7  illustrates the charge domain filter circuit achieved in the second embodiment of the present invention. The following is an explanation of the charge domain filter circuit achieved in the second embodiment of the present invention, given in reference to  FIG. 7 .  
         [0105]     As shown in  FIG. 7 , a charge domain filter circuit  200  in the second embodiment of the present invention includes transconductors  202 ,  204 ,  206  and  208  and SINC filter circuits  220 ,  240 ,  260  and  280 .  
         [0106]     The SINC filter circuit  220  includes a first switch  222 , a second switch  224 , a third switch  226  and capacitors  228   a ,  228   b ,  228   c  and  228   d . Likewise, the SINC filter circuit  240  includes a first switch  242 , a second switch  244 , a third switch  246  and capacitors  248   a ,  248   b ,  248   c  and  248   d , the SINC filter circuit  260  includes a first switch  262 , a second switch  264 , a third switch  266  and capacitors  268   a ,  268   b ,  268   c  and  268   d  hand the SINC filter circuit  280  includes a first switch  282 , a second switch  284 , a third switch  286  and capacitors  288   a ,  288   b ,  288   c  and  288   d.    
         [0107]     The transconductors  202 ,  204 ,  206  and  208  each output a current in proportion to the voltage of an input signal. While four transconductors are used to constitute the charge domain filter circuit in the embodiment, the number of transconductors in a charge domain filter circuit embodying the present invention is not limited to four. In addition, the transconductors may assume transconductance values equal to one another or they may assume transconductance values different from one another. The following explanation is provided by assuming that the four transconductors all assume transconductance values equal to one another.  
         [0108]     Capacitors to be electrically charged are selected via the first switches  222 ,  242 ,  262  and  282 . A specific capacitor among the capacitors  228   a ,  228   b ,  228   c  and  228   d  is selected through the first switch  222 . Likewise, a specific capacitor among the capacitors  248   a ,  248   b ,  248   c  and  248   d  is selected through the first switch  242 , a specific capacitor among the capacitors  268   a ,  268   b ,  268   c  and  268   d  is selected through the first switch  262  and a specific capacitor among the specific capacitors  288   a ,  288   b ,  288   c  and  288   d  is selected through the first switch  282 . It is assumed that the first switches  222 ,  242 ,  262  and  282  in the embodiment each include four terminals which are switched by using four clock signals assuming different phases.  
         [0109]     Capacitors to undergo initialization are selected via the second switches  224 ,  244 ,  264  and  284 . The capacitors in the SINC filter circuits  220 ,  240 ,  260  and  280 , which are to be initialized so as to rid them of any residual electrical charges, are selected through the second switches  224 ,  244 ,  264  and  284 . In the charge domain filter circuit  200  achieved in the embodiment, terminals are switched by using four types of clock signals and the capacitor connected to a selected terminal is initialized so as to purge the capacitor of the electrical charge attributable to a previous signal. It is to be noted that the present invention may be adopted in conjunction with second switches equipped with a different number of terminals.  
         [0110]     Capacitors from which the electrical charges are to be output are selected via the third switches  226 ,  246 ,  266  and  286 . The capacitors in the SINC filter circuits  220 ,  240 ,  260  and  280 , from which the electrical charges having been stored therein are to be output to the circuit at the rear stage, are selected through the third switches  226 ,  246 ,  266  and  286 . In the charge domain filter circuit  200  achieved in the embodiment, terminals are switched by using four types of clock signals and the electrical charge stored at the capacitor connected to a selected terminal is output to the circuit at the rear stage.  
         [0111]     It is to be noted that the present invention is not limited to the example described above with regard to the quantities of the various types of switches and the number of terminals included in each type of switch.  
         [0112]     Electrical charges are stored at the capacitors  228   a ,  228   b ,  228   c ,  228   d ,  248   a ,  248   b ,  248   c ,  248   d ,  268   a ,  268   b ,  268   c ,  268   d ,  288   a ,  288   b ,  288   c  and  288   d . It is desirable that all the capacitors have the same capacitance. It is to be noted that while each SINC filter circuit in the embodiment includes four capacitors, the quantity of capacitors to be included in each SINC filter circuit is not limited to four.  
         [0113]     Next, the operations executed in the charge domain filter circuit in the second embodiment of the present invention, adopting the structure described above, are explained.  
         [0114]      FIG. 8  presents a chart of the clock signals input to the charge domain filter circuit in the second embodiment of the present invention. Sixteen types of clock signals Ø 1 ˜Ø 16  are input to the charge domain filter circuit  200 .  
         [0115]     The first switch  222  is controlled based upon four types of clock signals Ø 1 , Ø 5 , Ø 9 , and Ø 13 . As the clock signal Ø 1  shifts from the OFF state to the ON state, the first switched  222  is connected to a terminal corresponding to the clock signal Ø 1 .  
         [0116]     As the first switch  222  is connected to the terminal corresponding to the clock signal Ø 1 , the current output from the transconductor  202  is input to the capacitor  228   a . The capacitor  228   a  is then electrically charged with the output current from the transconductor  202 .  
         [0117]     As the time length t elapses and the clock signal Ø 1  shifts from the ON state to the OFF state, the clock signal Ø 5  is switched from the OFF state to the ON state. In response to the switchover of the clock signal Ø 5  from the OFF state to the ON state, the first switch  222  is connected to the terminal corresponding to the clock signal  527    5 .  
         [0118]     As the first switch  222  is connected to the terminal corresponding to the clock signal Ø 5 , the current output from the transconductor  202  is input to the capacitor  228   b . The capacitor  228   b  is then electrically charged with the output current from the transconductor  202 .  
         [0119]     As the time length t elapses again and the clock signal Ø 5  shifts from the ON state to the OFF state, the clock signal Ø 9  is switched from the OFF state to the ON state. In response to the switchover of the clock signal Ø 9  from the OFF state to the ON state the first switch  222  is connected to the terminal corresponding to the clock signal Ø 9 .  
         [0120]     As the first switch  222  is connected to the terminal corresponding to the clock signal Ø 9 , the current output from the transconductor  202  is input to the capacitor  228   c . The capacitor  228   c  is then electrically charged with the output current from the transconductor  202 .  
         [0121]     As the time length t elapses yet again and the clock signal Ø 9  shifts from the ON state to the OFF state, the clock signal Ø 13  is switched from the OFF state to the ON state. In response to the switchover of the clock signal Ø 13  from the OFF state to the ON state, the first switch  222  is connected to the terminal corresponding to the clock signal Ø 13 .  
         [0122]     As the first switch  222  is connected to the terminal corresponding to the clock signal Ø 13 , the current output from the transconductor  202  is input to the capacitor  228   d . The capacitor  228   d  is then electrically charged with the output current from the transconductor  202 .  
         [0123]     As the time length t elapses yet again and the clock signal Ø 13  shifts from the ON state to the OFF state the clock signal Ø 1  is switched from the OFF state to the ON state. By alternately setting the clock signals Ø 1 , Ø 3 , Ø 9  and Ø 13  to the ON/OFF states repeatedly as described above, the first switch  222  is connected to different terminals so as to store electrical charges at the capacitors  228   a ,  228   b ,  228   c  and  228   d  in sequence with the output current from the transconductor  202 .  
         [0124]     As explained above, the individual capacitors in the SINC filter circuit  220  are electrically charged by repeatedly setting the four clock signals Ø 1 , Ø 5 , Ø 9 , and Ø 13  to the ON/OFF states. Likewise, the individual capacitors in the SINC filter circuits  240 ,  260  and  280  are electrically charged by repeatedly setting clock signals to the ON/OFF states. However, electrical charges are stored at the capacitors in the other SINC filter circuits by turning ON/OFF clock signals assuming phases different from those of the clock signals input to the first switch  222  in the SINC filter circuit  220 .  
         [0125]     For instance, four clock signals Ø 2 , Ø 6 , Ø 10 , and Ø 14  are input to the first switch  242  in the SINC filter circuit  240 . These clock signals assume phases offset by t/4 relative to the phases of the clock signals Ø 1 , Ø 5 , Ø 9 , and Ø 13  respectively, as shown in  FIG. 8 .  
         [0126]     In addition, clock signals Ø 3 , Ø 7 , Ø 11 , and Ø 15  are input to the first switch  262  in the SINC filter circuit  260 . These clock signals assume phases offset by t/2 relative to the phases of the clock signals Ø 1 , Ø 5 , Ø 9 , and Ø 13  respectively, as shown in  FIG. 8 . Clock signals Ø 4 , Ø 8 , Ø 12 , and Ø 16  are input to the first switch  282  in the SINC filter circuit  280 . These clock signals assume phases offset by 3t/4 relative to the phases of the clock signals Ø 1 , Ø 5 , Ø 9 , and Ø 13  respectively, as shown in  FIG. 8 .  
         [0127]     By inputting clock signals in different phases to the SINC filter circuits, the timing with which the capacitors in the individual SINC fitter circuits are charged can be shifted.  
         [0128]     The electrical charges stored at the capacitors are output to the circuit at the rear stage via the third switches  226 ,  246 ,  266  and  286 . Terminals at the third switches  226 ,  246 ,  266  and  286  are switched by turning ON/OFF four clock signals Ø 1 , Ø 5 , Ø 9 , and Ø 13  different phases so as to output the electrical charges stored at specific capacitors to the circuit at the rear stage. The clock signals Ø 1 , Ø 5 , Ø 9 , and Ø 13  used for the charge output are the same as the clock signals input to the first switch  222 .  
         [0129]     The electrical charge stored at the capacitor  228   a  with the output current from the transconductor  202  while clock signal Ø 1  is held in the ON state, is then output to the circuit at the rear stage as the clock signal Ø 5  is set to the ON state. Likewise, the charge at the capacitor  228   b , the charge at the capacitor  228   c  and the charge at the capacitor  228   d  are output to the circuit at the rear stage respectively when the clock signal Ø 13  is in the ON state, when the clock signal Ø 1  is in the ON state and when the clock signal Ø 5  is in the ON state.  
         [0130]     The charges stored at the capacitors in the SINC filter circuits  240 ,  260  and  280 , as well as the charges stored at the capacitors in the SINC filter circuit  220 , are output to the circuit at the rear stage. As are the terminals at the third switch  224  in the SINC filter circuit  220 , the terminals at the third switch  246  in the SINC filter circuit  240 , the terminals at the third switch  264  in the SINC filter circuit  260  and the terminals at the third switch  284  in the SINC filter circuit  280  are switched by turning ON/OFF the clock signals Ø 1 , Ø 5 , Ø 9 , and Ø 13 .  
         [0131]     While the capacitors  228   a ,  248   a ,  268   a  and  288   a  are charged in response to the inputs of the clock signals Ø 1 , Ø 2 , Ø 3 , and Ø 4  in different phases, the electrical charges stored at these capacitors are output simultaneously as the clock signal Ø 9  enters the ON state. Thus, the electrical charges stored at the capacitors  228   a ,  248   a ,  268   a  and  288   a  are added up and their sums output to the circuit at the rear stage.  
         [0132]     The capacitors in each of the other sets of capacitors, too, are charged in response to the inputs of clock signals in different phases but the stored charges are output to the circuit at the rear stage in response to the input of a single clock signal. While the capacitors  228   b ,  248   b ,  268   b  and  288   b  are charged in response to the inputs of the clock signals Ø 5 , Ø 6 , Ø 7 , and Ø 8  in different phases, the electrical charges stored at these capacitors are output simultaneously as the clock signal Ø 13  enters the ON state. While the capacitors  228   c ,  248   c ,  268   c  and  288   c  are charged in response to the inputs of the clock signals Ø 9 , Ø 10 , Ø 11 , and Ø 12  in different phases, the electrical charges stored at these capacitors are output simultaneously as the clock signal Ø 1  enters the ON state. Likewise, while the capacitors  228   d ,  248   d ,  268   d  and  288   d  are charged in response to the inputs of the clock signals Ø 13 , Ø 14 , Ø 15 , and Ø 16  in different phases, the electrical charges stored at these capacitors are output simultaneously as the clock signal Ø 5  enters the ON state.  
         [0133]     As the electrical charges in the individual capacitors are output to the circuit at the rear stage via the third switches  226 ,  246 ,  266  and  286 , any residual charges that may remain in the capacitors are purged so as to initialize the capacitors by grounding the capacitors. The capacitors are initialized via the second switches  224 ,  244 ,  264  and  284 . Terminals at the second switches are switched by turning ON/OFF four clock signals Ø 1 , Ø 5 , Ø 9 , and Ø 13  in different phrases.  
         [0134]     As the clock signal Ø 9  is turned off and the clock signal Ø 13  is turned on, the second switch  224  is connected to the terminal corresponding to the clock signal Ø 13 . As a result, the capacitor  228   a  becomes grounded via the second switch  224  and any residual electrical charge present in the capacitor  228   a  is discharged, thereby initializing the capacitor. When the clock signal Ø 9  is turned off and the clock signal Ø 13  is turned on, the other second switches  244 ,  264  and  284  are also connected to the terminals corresponding to the lock signal Ø 13 . Thus, residual electrical charges present air the capacitors  248   a ,  268   a  and  288   a  are discharged, thereby initializing the capacitors  248   a ,  268   a  and  288   a.    
         [0135]     As the clock signal Ø 13  having been in the ON state over the time length t is switched from the ON state to the OFF state, the clock signal Ø 1  is switched from the OFF state to the ON state. As the clock signal Ø 1  enters the ON state, the second switch  224  is connected to the terminal corresponding to the clock signal Ø 1 . As a result, the capacitor  228   b  is grounded via the second switch  224  and the residual charge present in the capacitor  228   b  is discharged, thereby initializing the capacitor  228   b . When the clock signal Ø 13  is turned off and the clock signal Ø 1  is turned on, the other second switches  224 ,  264  and  284  are also connected to the terminals corresponding to the clock signal Ø 1 , and the residual electrical charges still present in the capacitors  248   b ,  268   b  and  288   b  are discharged, thereby initializing the capacitors  248   b ,  268   b  and  288   b .  
         [0136]     As the clock signal Ø 1  having been in the ON state over the time length t is switched from the ON state to the OFF state, the clock signal Ø 5  is switched from the OFF state to the ON state. As the clock signal Ø 5  enters the ON state, the second switch  224  is connected to the terminal corresponding to the clock signal Ø 5 . As a result, the capacitor  228   c  is grounded via the second switch  224  and the residual charge present in the capacitor  228   c  is discharged, thereby initializing the capacitor  228   c . When the clock signal Ø 1  is turned off and the clock signal Ø 5  is turned on, the other second switches  224 ,  264  and  284  are also connected to the terminals corresponding to the clock signal Ø 5 , and the residual electrical charges still present in the capacitors  248   c ,  268   c  and  288   c  are discharged, thereby initializing the capacitors  248   c ,  268   c  and  288   c.    
         [0137]     As the clock signal Ø 3  having been in the ON state over the time length t is switched from the ON state to the OFF state, the clock signal Ø 9  is switched from the OFF state to the ON state. As the clock signal Ø 9  enters the ON state, the second switch  224  is connected to the terminal corresponding to the clock signal Ø 9 . As a result, the capacitor  228   d  is grounded via the second switch  224  and the residual charge present in the capacitor  228   d  is discharged, thereby initializing the capacitor  228   d . When the clock signal Ø 5  is turned off and the clock signal Ø 9  is turned on, the second switches  224 ,  264  and  284  are also connected to the terminals corresponding to the clock signal Ø 9 , and the residual electrical charges still present in the capacitors  248   d ,  268   d  and  288   d  are discharged, thereby initializing the capacitors  248   d ,  268   d  and  288   d.    
         [0138]     By repeatedly turning ON/OFF the clock signals Ø 1 , Ø 5 , Ø 9 , and Ø 13  as described above, the residual electrical charges in the capacitors  228   a ,  228   b ,  228   c  and  228   d  in the SINC filter circuit  220  are discharged, thereby initializing the individual capacitors. Likewise, the capacitors in the SINC filter circuits  240 ,  260  and  280  are initialized by inputting the clock signals Ø 1 , Ø 5 , Ø 9 , and Ø 13  to the second switches  244 ,  264  and  284  respectively.  
         [0139]     As described above, each capacitor is engaged in the charge, the output and the initialization without a break. Dump Ø 9  in  FIG. 8  indicates the change occurring in the overall quantity of electrical charge output to the circuit at the rear stage when the clock signal Ø 9  is input to the third switches  226 ,  246 ,  266  and  286 . The timing with which the capacitors  228   a ,  248   a ,  268   a  and  288   a , for instance, are electrically charged is controlled by using the clock signals Ø 1 ˜Ø 4 . Since the clock signals Ø 1 ˜Ø 4  in different phases, the overall quantity of the electrical charge output to the circuit at the rear stage in response to the input of the clock signal Ø 9  changes in steps over time. Accordingly, the total sum of the electrical charges having been stored at the capacitors  228   a ,  248   a ,  268   a  and  288   a  is equivalent to the results of an integration of continuous time signals sliced out with triangular wave windows as indicated by Dump Ø 9  in  FIG. 8 .  
         [0140]     Likewise, the total sum of the electrical charges having been stored at the capacitors  228   b ,  248   b ,  268   b  and  288   b  is equivalent to the results of an integration of continuous time signals sliced out with triangular wave windows as indicated by Dump Ø 13  in  FIG. 8 , the total sum of the electrical charges having been stored at the capacitors  228   c ,  248   c ,  268   c  and  288   c  is equivalent to the results of an integration of continuous time signals sliced out with a triangular wave window such as Dump Ø 1  in  FIG. 8 , and the total sum of the electrical charges having been stored at the capacitors  228   d ,  248   d ,  268   d  and  288   d  is equivalent to the results of air integration of continuous time signals sliced out with triangular wave windows as indicated by Dump Ø 5  in  FIG. 8 . Thus, the sampling operation and the filtering operation of the FIR filter are seamlessly executed based upon time intervals t.  
         [0141]     As in the charge domain filter circuit  100  in the first embodiment of the present invention, an impulse response of the charge domain filter circuit  200  is obtained as shown in  FIG. 7  through convolution of two rectangular impulses. The impulse response obtained in the charge domain filter circuit  200  is a triangular wave impulse response similar to that shown in  FIG. 3B . Thus, the charge domain filter circuit  200  is able to operate as an FIR filter and assuming that the sampling cycle t is 1 ns, the charge domain filter circuit  200  achieves frequency characteristics similar to those in the frequency response in the charge domain filter circuits  100  shown in  FIG. 4 .  
         [0142]     The frequency characteristics of the charge domain filter circuit  200  achieved in the second embodiment of the present invention, too, can be altered by adjusting the levels of transconductance at the transconductors.  
         [0143]     For instance, if the transconductance at the transconductors  204  and  206  are double the transconductance at the transconductors  202  and  208 , a trapezoidal impulse is generated, indicated as indicated by Gm in  FIG. 5A . Accordingly, the impulse response of the charge domain filter circuit  200  as does the impulse response in the charge domain filter circuit  100  in the first embodiment of the present invention. As a result, by varying the transconductance manifests as shown in  FIG. 5B , the charge domain filter circuit  200 , too, achieves frequency characteristics such as those shown in the graph presented in  FIG. 6 .  
         [0144]     Namely, the charge domain filter circuit in the second embodiment of the present invention, too, forms an FIR filter that allows the frequency characteristics thereof to be adjusted by varying the weight applied to the transconductance.  
         [0145]     As explained earlier, the frequency characteristics can be adjusted freely by weighting the transconductance in the charge domain filter circuit achieved in the second embodiment of the present invention.  
         [0146]     As explained above, an impulse response in an FIR filter can be obtained through convolution of weighted transconductance and rectangular windows used for electrical current integration. Accordingly, by adjusting the weight applied to the transconductance or altering the length of time over which clocks used to charge the capacitors remain in the ON state various forms of impulse response can be obtained in the FIR filer.  
       APPLICATION EXAMPLE 1  
       [0147]      FIGS. 9A and 9B  illustrate an example of impulse response. When the pulse width of the clocks used to charge the capacitors includes three clock and the charge domain filter circuit includes five transconductors, with three transconductors among them assuming a transconductance twice that of the remaining two, as shown in  FIG. 9A , the impulse response shown in  FIG. 9B  is obtained. The impulse response shown in  FIG. 9B  is identical to that shown in  FIG. 5B . Accordingly, assuming that the sampling cycle t is equal to 1 ns, the frequency characteristics achieved under these circumstances, too, are as indicated by the graph in  FIG. 6 .  
       APPLICATION EXAMPLE 2  
       [0148]      FIGS. 10A and 10B  illustrate another example of impulse response. When the pulse width of the clocks used to charge the capacitors includes five clocks and the charge domain filter circuit includes three transconductors all having equal transconductance, as shown in  FIG. 10A , the impulse response shown in  FIG. 10B  is obtained. Assuming that the sampling cycle t is equal to 1 ns, the frequency characteristics achieved under these circumstances are as indicated by the graph in  FIG. 1 .  
       APPLICATION EXAMPLE 3  
       [0149]      FIGS. 12A and 12B  illustrate yet another example of impulse response. When the pulse width of the clocks used to charge the capacitors includes four clocks and the charge domain filter circuit includes four transconductors with two transconductors among them having transconductance twice that of the remaining two transconductors, as shown in  FIG. 12A , the impulse response shown in  FIG. 12B  is obtained. Assuming that the sampling cycle t is equal to 1 ns, the frequency characteristics achieved under these circuit are as indicated by the graph in  FIG. 13 .  
       APPLICATION EXAMPLE 4  
       [0150]      FIGS. 14A and 14B  illustrate another example of impulse response. When the pulse width of the clocks used to charge the capacitors includes four clocks and the charge domain filter circuit includes four transconductors with one transconductor having transconductance with a polarity opposite from the polarity at the remaining three transconductors, as shown in  FIG. 14A , the impulse response shown in  FIG. 14B  is obtained. Assuming that the sampling cycle t is equal to 1 ns, the frequency characteristics achieved under these circumstances are as indicated by the graph in  FIG. 15 .  
         [0151]     By altering the pulse width of clocks used to charge the capacitors or the transconductance at the individual transconductors as described above, various frequency characteristics can be achieved. In other words, by adjusting the transconductance or the capacitor charge time in correspondence to the band of the signal to be passed through or specific purposes of use, a single circuit can be utilized to pass signals in varying bands, which, in turn, makes it possible to subscribe to a plurality of wireless communication services without having to increase the circuit scale.  
       THIRD EMBODIMENT  
       [0152]     Band pass charge sampling (BPCS; see Nonpatent Reference Literature 2) executed by utilizing the charge domain filter circuit achieved in the third embodiment of the present invention is explained as another application example of the present invention.  
         [0153]      FIG. 16  shows the charge domain filter circuit achieved in the third embodiment of the present invention. As shown in  FIG. 16 , the charge domain filter circuit  300  in the third embodiment of the present invention includes transconductors  302 ,  304 ,  306  and  308 , switches  310   a ,  310   b ,  310   c  and  310   d , adders  312   a  and  312   b , a SINC filter circuit  320 , a first switch unit  330  and a second switch unit  340 .  
         [0154]     The SINC filter circuit  32  includes first switches  322   a  and  322   b , a second switch  324 , a third switch  326  and capacitors  328   a ,  328   b ,  328   c  and  328   d . The first switch unit  330  includes switches  332   a  and  332   b , whereas the second switch unit  340  includes  342   a  and  342   b.    
         [0155]     The outputs from the transconductors to the SINC filter circuit  320  are controlled via the first switch unit  330  and the second switch unit  340 . More specifically, the outputs from the transconductors are controlled through the first switch unit  330 , whereas the outputs assuming phases that are the opposite of the phases in the outputs from the transconductors are controlled through the second switch unit  340 .  
         [0156]     Clock signals assuming phases that are opposite from each other are input to the first switch unit  330  and the second switch unit  340 . Namely, no clock signal input to the second switch unit  340  while a clock signals in the ON state is input to the first switch unit  330 , and the clock signal in the ON state is not input to the first switch unit  330  while a clock signal in the ON state is input to the second switch unit  340 .  
         [0157]     As the clock signals input to the first switch unit  330  and the second switch unit  340  are alternately turned on and off repeatedly, the outputs from the transconductors and outputs assuming phases the opposite of the phases of the outputs from the transconductors are alternately input to the SINC filter circuit  320 . Namely, frequency conversion is achieved by multiplying the clock signal input to the first switch unit  330  by the clock signal input to the second switch unit  340 . As a result, the charge domain filter circuit  300  functions as a filter circuit achieving filtering characteristics centered on a predetermined frequency.  
         [0158]     As explained above, the charge domain filter circuit in the third embodiment of the present invention can be utilized in band pass charge sampling centered on a specific frequency. As in the first embodiment and the second embodiment, the frequency characteristics of the charge domain filter circuit in the third embodiment can be adjusted freely by altering the transconductance value or the capacitor charge time. In other words, by adjusting the transconductance or the capacitor charge time in correspondence to the band of the signal to be passed through or specific purposes of use, a singe circuit can be utilized to pass signals in varying bands, which, turn, makes it possible to subscribe to a plurality of wireless communication services without having to increase the circuit scale.  
         [0159]     It should be understood by those skilled in the art that various modification, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.