Abstract:
A method and computer program product for use in a control system. The controller includes a first gain element configured to provide a first predetermined gain to an output error signal describing an error in the output of the control system; a compensator including a control loop including a storage element, the control loop receiving the output error signal, a second gain element configured to provide a second predetermined gain to the output of the control loop, and a detector configured to modify the contents of the storage element according to a predetermined adjustment value when a minimum predetermined excursion occurs in the output error signal; and a combiner configured to combine the outputs of the first and second gain elements to produce an output control signal for the control system.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. application Ser. No. 09/854,299, filed May 11, 2001 now U.S. Pat. No. 6,411,071, which is a continuation of U.S. application Ser. No. 09/753,120, filed Dec. 29, 2000 now abandoned, the entire contents of which are hereby incorporated by reference. 
    
    
     BACKGROUND 
     The present invention relates to control systems in general, and to voltage regulators in particular. 
     Voltage regulators, such as DC-to-DC converters, are used to provide stable voltage sources for electronic systems. Efficient DC-to-DC converters are particularly needed for battery management in low power devices, such as laptop computers and mobile phones. Switching voltage regulators (or simply “switching regulators”) are known to be an efficient type of DC-to-DC converter. A switching regulator generates an output voltage by converting an input DC voltage into a high frequency voltage, and filtering the high frequency voltage to generate the output DC voltage. 
     Conventional switching regulators include two switches. One switch is used to alternately couple and decouple an unregulated input DC voltage source, such as a battery, to a load, such as an integrated circuit The other switch is used to alternately couple and decouple the load to ground. An output filter, typically including an inductor and an output capacitor, is coupled between the switches and the load to filter the output of the switches and produce the output DC voltage. 
     The switches within the switching regulator are opened and closed according to commands from a closed-loop control system. Control systems within DC-to-DC converters, just like control systems generally within any electronic system, need to be stabilized. Care in the design of the control system in a DC-to-DC converter must account for variations of parameters such as the input voltage, filter inductor and capacitor values, switch resistances, printed circuit board parasitics, etc. Sometimes a simple scheme such as voltage feedback alone will stably control a power supply. In other situations, extra margin of stability and higher bandwidth are gained by using current mode control techniques. Still other schemes use hysteresis bands to decide how to control the switches. 
     In some cases, it is desired to add compensation to improve phase margin of a DC-to-DC regulator. Often phase margin can be improved by using a lag compensator, which lowers the overall bandwidth to boost phase at the crossover frequency. Unfortunately, with lowered bandwidth, DC-to-DC regulators take longer to respond to load current transients, resulting in larger output voltage deviations. As a result, many such systems use extra capacitance in the converter&#39;s output filter to improve transient response. However, using larger capacitors increases the cost of the regulator substantially. 
     Commercially-available hysteretic controllers trigger certain responses when the output voltage deviates too high, or too low. However, these controllers do not have a beneficial effect on nominal, steady-state performance while the voltage is within the hysteresis bands, and may add design difficulty due to their non-linear behavior. 
     SUMMARY 
     In one aspect, the invention is directed to a method and computer program product for use in a control system controller having a control loop that includes a storage element, the control loop receiving an output error signal describing an error in the output of the control system. It includes modifying the contents of the storage element according to a predetermined adjustment value when a minimum predetermined excursion occurs in the output error signal; providing a first predetermined gain to the output error signal; providing a second predetermined gain to the output of the control loop; and combining the outputs of the first and second gain elements to produce an output control signal. 
     Advantages that can be seen in implementations of the invention include one or more of the following. The compensator can add phase margin without requiring extra capacitance, can provide enhance stability during steady-state conditions, and does not degrade transient response. 
     The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features and advantages of the invention will become apparent from the description, the drawings, and the claims. 
    
    
     BRIEF DESCRIPTION OF DRAWINGS 
     FIG. 1 shows a switching regulator according to an embodiment of the present invention. 
     FIG. 2 shows a controller for a switching regulator according to one embodiment of the present invention. 
     FIG. 3 shows a controller for a switching regulator according to another embodiment of the present invention. 
     FIG. 4 shows a detector for a switching regulator controller according to an embodiment of the present invention. 
     FIG. 5 shows several contemporaneous waveforms that result from transients in the load of the switching regulator of FIG.  1 . 
     Like reference numbers and designations in the various drawings indicate like elements. 
    
    
     DETAILED DESCRIPTION 
     Referring to FIG. 1, a switching regulator  102  is coupled to an unregulated DC voltage source  104 , such as a battery, by an input terminal  106 . The switching regulator  102  is also coupled to a load  108 , such as an integrated circuit, by an output terminal  110 . The switching regulator  102  serves as a DC-to-DC converter between the input terminal  106  and the output terminal  110 . The switching regulator  102  includes a switching circuit  112  which serves as a power switch for alternately coupling and decoupling the input terminal  106  to an intermediate terminal  114 . In some applications, such as a buck converter topology, the switching circuit  112  couples the intermediate terminal  114  to ground when the intermediate terminal  114  is not coupled to the input terminal  106 . 
     The switching regulator also includes a controller  116  for controlling the operation of the switching circuit  112 . The controller  116  causes the switching circuit  112  to convert the substantially DC input voltage V IN  at the input terminal  106  into an intermediate voltage having a rectangular waveform at the intermediate terminal  114 . 
     The intermediate terminal  114  is coupled to the output terminal  110  by an output filter  118 . The output filter  118  converts the rectangular waveform at the intermediate terminal  114  to a substantially DC output voltage V OUT  at the output terminal  110 . The switching circuit  112  and the output filter  118  may have a buck converter topology, or another topology, such as a boost converter or buck-booster converter topology. 
     The output voltage is regulated, or maintained at a substantially constant level, by controller  116 . Controller  116 measures electrical properties of the output, such as output voltage and/or output current, and compares these properties to a control electrical property, such as voltage V REF  at terminal  120 . Based on this comparison, controller  116  provides a current command I COMMAND  to the switching circuit  112  at terminal  122 . 
     Switching circuit  112  operates its switches according to the current command I COMMAND . Switching circuit  112  can control its switches based not only on the current command, but also on the output current delivered by switching circuit  112  to output filter  118 . Other embodiments employ direct feedback without the use of current commands. 
     Controller  116  includes a control loop including a storage element that stores a nominal value under nominal conditions. However, under certain predetermined transient conditions, the contents of the storage element are modified as described in detail below. 
     In one embodiment, the storage element is loaded with a predetermined adjustment value under predetermined transient conditions. Referring to FIG. 2, controller  116  includes a combiner  202  that receives reference voltage V REF  at terminal  120  and output voltage V OUT  at terminal  110 , and produces an error voltage V ERR =V REF −V OUT  at terminal  222 . A gain element  204  applies a gain Gp to V ERR  to produce a current I PROP  at terminal  230  that is proportional to V ERR . 
     Controller  116  also includes a lag compensator that includes a control loop and a gain element  216  that applies a gain Gi to the output of the control loop to produce a current I INT  at terminal  228 . Combiner  218  adds currents I PROP  and I INT  to produce current command I COMMAND  at terminal  122 . 
     The control loop includes gain elements  206  and  208 , combiner  210 , delay element  212 , and storage element  214 . Gain element  206  applies a gain 1-Ki to V ERR , where Ki is the discrete time pole, in the Z-domain unit circle, of the lag compensator. Selection of an appropriate value for Ki will be apparent to one skilled in the relevant art. 
     Combiner  210  combines the output of gain elements  206  and  208 . Storage element  214  loads the output VNOM of combiner  210  at terminal  224  during nominal operation (that is, when excursions of V ERR  do not leave a predefined envelope). 
     However, when a minimum predetermined excursion occurs in output voltage V OUT , error voltage V ERR  leaves the predefined envelope. This event is detected by detector  220 , which asserts a LOAD signal at terminal  234  and a predetermined adjustment value V ADJ  at terminal  232 . The LOAD signal cauees storage element  214  to load predetermined adjustment value V ADJ  at terminal  232 , causing the predetermined adjustment value to appear at terminal  226  as the output Acc of storage element  214 . 
     In digital implementations, storage element  214  can be implemented as an accumulator. In analog implementations, storage element  214  can be implemented as an integrating capacitor. 
     In digital implementations, detector  220  can be implemented as an A/D converter to determine V OUT . The A/D converter is centered at analog reference voltage V REF , and outputs a monotonically increasing four bit reading versus V OUT  within the predetermined voltage envelope for V REF . Below or above that range, the A/D converter clips, or saturates. When the A/D converter saturates, it causes the storage element  214  (here, an accumulator) to preload the predetermined adjustment value. In other embodiments, A/D converters of widths other than four bits are used. 
     Delay element  212  applies a predetermined delay to the output of storage element  214 . Gain element  208  applies gain Ki to the output of delay element  212 . 
     In another embodiment, the contents of the storage element are incremented by a predetermined adjustment value under predetermined transient conditions. Referring to FIG. 3, the adjustment value V ADJ  is combined with Acc by combiner  302 . When detector  220  asserts the LOAD signal, the output of combiner  302  is loaded into storage element  214 , thereby incrementing the contents of storage element  214  by the predetermined adjustment value. 
     FIG. 4 is a functional block diagram of a detector  220  for a switching regulator controller according to an embodiment of the present invention. The detector includes comparison elements  406 A and  406 B associated with predetermined preload values  402 A and  402 B, respectively, and switches  404 A and  404 B, respectively. Each comparison element compares V ERR  to a predetermined voltage range. When V ERR  falls within a comparison element&#39;s range, the comparison element triggers a switch, thereby supplying a predetermined preload value as the adjustment voltage V ADJ . 
     In the embodiment of FIG. 4, detector  220  implements a single envelope bounded by thresholds n 1  and n 2 . When V ERR  falls below threshold n 1 , comparison element  406 A triggers switch  404 A, thereby supplying v 1  as adjustment value V ADJ  at terminal  224 . 
     When V ERR  exceeds threshold n 2 , comparison element  406 B triggers switch  404 B, thereby supplying voltage v 2  as adjustment value V ADJ  at terminal  224 . When either V ERR  falls below threshold n 1 , or when V ERR  exceeds threshold n 2 , OR gate  408  asserts LOAD signal at terminal  224 , thereby causing storage element  214  to load. 
     Under nominal operations V ERR  falls between thresholds n 1  and n 2 . Therefore no LOAD signal is generated. Consequently storage element simply loads V NOM  under nominal operations. 
     In one embodiment, detector  220  implements more than one predetermined envelope. The error voltage V ERR  is compared to a plurality of ranges, each associated with an envelope. Each range is associated with a predetermined preload value. When V ERR  falls within a particular range, the predetermined preload value associated with that range is supplied to storage element  114  as the predetermined adjustment value. 
     In general, the magnitude of the adjustment corresponds to the magnitude of the envelope. For example, when a small excursion in V ERR  occurs, a small adjustment value is supplied to storage element  214 . When a large excursion in V ERR  occurs, a large adjustment value is supplied to storage element  214 . 
     Selection of an appropriate adjustment values and thresholds will be apparent to one skilled in the relevant art. In general, the adjustment values should be chosen to quickly reduce the output error signal V ERR  to a desirable value. The threshold values should be chosen such that nominal operation of the control system is not unnecessarily disturbed. 
     The behavior of the lag compensator can be described in the time domain. The lag compensation appears as a change in the equation for the current command I COMMAND . Without lag compensation, 
     
       
         I COMMAND =GpV ERR   
       
     
     where Gp is the proportional gain and V ERR =V REF −V OUT  is the error term from the outer voltage loop. For the discrete-time lag compensation technique discussed above, there is an additional term GiAcc so that 
     
       
           I   COMMAND   =GpV   ERR   +Gi Acc 
       
     
     and 
     
       
         Acc[ n]=Ki *Acc[ n −1]+(1 −Ki ) V   ERR   
       
     
     where Acc is the output of the accumulator, which acts as storage element  214  in a discrete time implementation of the system. 
     The lag compensation pole is defined by Ki. The zero falls out from the combination of these equations in the increased order system, and will always be a higher frequency than the pole for non-zero Gi. The output Acc of the accumulator will reach in steady-state the value V ERR . Therefore in steady-state, 
     
       
         
           I 
           COMMAND 
           =GpV 
           ERR 
           +GiV 
           ERR 
         
       
     
     Thus the DC gain is now Gp+Gi. 
     FIG. 5 shows several contemporaneous waveforms that result from transients in the load of the switching voltage regulator described above with reference to FIG.  1 . An envelope is defined to limit excursions of V ERR  to a high of V HIGH  and a low of V LOW . From time t 1  to time t 4 , nominal operation is depicted (that is, V ERR  does not reach either limit V HIGH  or V LOW  of its envelope). 
     At time t 5 , a transient from zero load to full load occurs. In response, V OUT  decreases, and so V ERR  increases. The proportional part of the current command, I PROP , changes with V ERR . There is no delay between a V ERR  change and an I PROP  change. I INT , on the other hand, changes slowly due to the Ki pole. 
     At time t 6 , V ERR  reaches limit V HIGH  of its envelope. Before V ERR  reaches V HIGH , I INT  changes slowly with its Ki pole. However, once V ERR  reaches an envelope limit, controller  116  determines that a severe load transient has occurred. The controller  116  then step changes I INT  to a predetermined final value by preloading storage element  214 . The preloading adjusts the total current I COMMAND  to the value it would have reached given much more time. 
     Two hypothetical waveforms are shown for comparison with the I COMMAND  waveform. I COMMAND  is shown as a solid line. Waveform  504  depicts how I COMMAND  would behave without preloading. Waveform  502  depicts the ideal I COMMAND . 
     At time t 7 , a transient from full load to zero load occurs. In response, V OUT  increases, and so V ERR  decreases. The controller behaves in a manner similar to that described above for the zero load to full load case. 
     The invention has been described in terms of particular embodiments. Other embodiments are within the scope of the following claims. For example, the steps of the invention can be performed in a different order and still achieve desirable results. In addition, embodiments of the controller of the present invention can be used in control systems other than DC-to-DC converters. 
     The invention can be implemented in digital electronic circuitry, or in computer hardware, firmware, software, or in combinations of them. Apparatus of the invention can be implemented in a computer program product tangibly embodied in a machine-readable storage device for execution by a programmable processor; and method steps of the invention can be performed by a programmable processor executing a program of instructions to perform functions of the invention by operating on input data and generating output. The invention can be implemented advantageously in one or more computer programs that are executable on a programmable system including at least one programmable processor coupled to receive data and instructions from, and to transmit data and instructions to, a data storage system, at least one input device, and at least one output device. Each computer program can be implemented in a high-level procedural or object-oriented programming language, or in assembly or machine language if desired; and in any case, the language can be a compiled or interpreted language. Suitable processors include, by way of example, both general and special purpose microprocessors. Generally, a processor will receive instructions and data from a read-only memory and/or a random access memory. Generally, a computer will include one or more mass storage devices for storing data files; such devices include magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and optical disks. Storage devices suitable for tangibly embodying computer program instructions and data include all forms of non-volatile memory, including by way of example semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM disks. Any of the foregoing can be supplemented by, or incorporated in, ASICs (application-specific integrated circuits). 
     Embodiments of the controller of the present invention are not limited to lag compensators, but can also be practiced within other types of compensators, such as lead-lag compensators. Further, although the switching regulator is discussed in the context of a buck converter topology, embodiments of the invention are also applicable to other switching regulator topologies, such as a boost converter topology or a buck-boost converter topology.