Abstract:
It is an object of this disclosure to provide high productivity, low cost-of-ownership manufacturing equipment for the high volume production of photovoltaic (PV) solar cell device architecture. It is a further object of this disclosure to reduce material processing steps and material cost compared to existing technologies by using gas-phase source silicon. The present disclosure teaches the fabrication of a sacrificial substrate base layer that is compatible with a gas-phase substrate growth process. Porous silicon is used as the sacrificial layer in the present disclosure. Further, the present disclosure provides equipment to produce a sacrificial porous silicon PV cell-substrate base layer.

Description:
FIELD 
       [0001]    The present disclosure relates to solar cells and methods of manufacture. More specifically, the present disclosure relates to a high volume porous silicon process. 
       DESCRIPTION OF THE RELATED ART 
       [0002]    In the solar cell industry, known high-efficiency technologies usually use semiconductor-grade mono-crystalline silicon wafers, produced using extensive and costly process steps. 
         [0003]    Presently, and into the foreseeable future, the use of costly high-quality bulk mono-crystalline-Silicon (c-Si) will be the cost barrier preventing all competing high-efficiency c-Si technologies from reaching the critical “grid-parity” cost threshold. 
         [0004]    Existing technologies rely on a supply of semiconductor-grade substrates fabricated from expensive CZ or FZ mono-crystalline silicon ingots which are processed into substrates using a series of high-precision subtractive processes, such as ingot slicing, mechanical lapping, chemical etching and chemical-mechanical polishing. 
         [0005]    The inherent cost of semiconductor-grade silicon substrates may prevent competing c-Si PV technologies from reaching grid-parity costs because of the high degree of silicon cost combined with the extensive substrate preparation steps. 
       SUMMARY 
       [0006]    Therefore, it is an object of this disclosure to provide high productivity, low cost-of-ownership manufacturing equipment for the high-volume production of photovoltaic (PV) solar cell devices. 
         [0007]    The PV solar cell architecture of the present disclosure may deliver best-of-class efficiency, over 20%, while consuming a small fraction, as little as 15%, of source silicon material, at a much lower cost than that used in the production of present high-efficiency cells. 
         [0008]    It is a further object of this disclosure to reduce material processing steps and material cost compared to existing technologies by using gas-phase source silicon. 
         [0009]    The present disclosure achieves high efficiency and low cost by using the disclosed process to grow the PV cell substrate from gas-phase source silicon into a substantially finished shape with close to 100% source-material utilization. 
         [0010]    The presently disclosed substrate growth process allows the in-situ formation of three-dimensional structured substrates or two-dimensional substrates that may enhance efficiency through formation of highly effective light trapping PN junction structures. 
         [0011]    The present disclosure teaches the fabrication of a sacrificial substrate base layer that is compatible with a gas-phase substrate growth process. Porous silicon is used as the sacrificial layer in the present disclosure. 
         [0012]    Further, the present disclosure provides equipment to produce a sacrificial porous silicon PV cell-substrate base layer, which may assist in the fabrication of highly cost-effective and efficient mono-crystalline silicon PV solar cells. 
         [0013]    The porous silicon process uses electrochemical etching of the bulk silicon surface to produce a controlled thickness of a highly porous silicon layer or a stack of multiple porous silicon layers referred to as the porous silicon layer system. The porosity of the films may be controlled from 20% to 70% volumetric ratio of open porosity to silicon, and the thickness may be controlled from 0.2 μm to over 5 μm. 
         [0014]    The electrochemical reaction is similar to processes most often referred to as “anodization” in the metal finishing industry. The basic reaction is shown in  FIGS. 2 and 3 . 
         [0015]    The porous silicon layer system may provide two primary functions: 1) the porous silicon provides a sacrificial base on which the aforementioned gas-phase mono-crystalline silicon-cell substrate is grown, and 2) the porous silicon is removed after the growth of the mono-crystalline silicon-cell substrate, using a highly selective chemical etch process, a controlled mechanical process, or a combination of chemical and mechanical process, which results in the release of the cell substrate from the bulk-silicon wafer from which the porous silicon layer was originally formed. 
         [0016]    These and other advantages of the disclosed subject matter, as well as additional novel features, will be apparent from the description provided herein. The intent of this summary is not to be a comprehensive description of the subject matter, but rather to provide a short overview of some of the subject matter&#39;s functionality. Other systems, methods, features and advantages here provided will become apparent to one with skill in the art upon examination of the following FIGURES and detailed description. It is intended that all such additional systems, methods, features and advantages included within this description, be within the scope of the claims. 
     
    
     
       BRIEF DESCRIPTIONS OF THE DRAWINGS 
         [0017]    The features, nature, and advantages of the disclosed subject matter may become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference numerals indicate like features and wherein: 
           [0018]      FIG. 1  shows a cross-sectional view of an embodiment of a basic template, porous silicon layer, and substrate configuration; 
           [0019]      FIGS. 2 and 3  illustrate the anodization process; 
           [0020]      FIG. 4  provides photographs of a porous silicon layer or porous silicon layer system; 
           [0021]      FIG. 5  provides a photograph of a 3-D substrate; 
           [0022]      FIG. 6  provides an exemplary process for creating a 3-D thin film substrate; 
           [0023]      FIG. 7  provides cross-sectional view of a stationary immersion tank embodiment; 
           [0024]      FIG. 8  provides a top view of a stationary immersion tank embodiment; 
           [0025]      FIG. 9  provides an isometric view of a wafer pallet; 
           [0026]      FIG. 10  provides an isometric view of three wafer pallets; 
           [0027]      FIGS. 11A and 11B  provide top and cross-sectional views, respectively, of a palletized immersion tank; 
           [0028]      FIG. 12  provides an isometric view of a palletized immersion tank; 
           [0029]      FIG. 13  provides a cross-sectional view of two electrolytic chambers; 
           [0030]      FIG. 14  provides a cross-sectional view of a palletized immersion tank demonstrating electrolytic chambers; 
           [0031]      FIG. 15  provides an isometric view of a palletized immersion tank demonstrating electrolytic chambers; and 
           [0032]      FIG. 16  provides a cross-sectional view of an electrolytic cell and silicon wafer. 
       
    
    
     DETAILED DESCRIPTION 
       [0033]    The following description is not to be taken in a limiting sense, but is made for the purpose of describing the general principles of the present disclosure. The scope of the present disclosure should be determined with reference to the claims. Exemplary embodiments of the present disclosure are illustrated in the drawings, like numbers being used to refer to like and corresponding parts of the various drawings. 
         [0034]    The present disclosure presents a PV cell substrate fabrication process flow using porous silicon as a sacrificial layer. 
         [0035]    The system may produce porous silicon films with acceptable quality for supporting the manufacturing of PV cells.  FIGS. 1-6  relate generally to production of PV cells. 
         [0036]      FIG. 1  shows a step in the process of creating a solar cell using the sacrificial porous silicon release layer of the present disclosure. Bulk p-type silicon wafer  10  has had trenches  11  patterned into it, for example by deep reactive-ion etching (DRIE) or by chemical etching. Then porous silicon layer  12  was created in accordance with the teachings of the present disclosure. Finally, solar cell substrate  14  was epitaxially deposited on top of layer  12  from gas-phase source silicon. 
         [0037]      FIG. 2  shows a schematic view of an electrochemical cell for producing a layer of porous silicon through anodization. Wafer  20  is placed in electrolyte bath  22 , between anode  24  and cathode  26 . In one embodiment, electrolyte bath  22  may be HF/IPA. A porous silicon film is created on wafer frontside  28  as current is passed through the system; no porous silicon is formed on wafer backside  27 . As current runs through the system, hydrogen gas may be evolved at cathode  26  and wafer backside  27 ; oxygen gas may be evolved at anode  24  and wafer frontside  28 . 
         [0038]      FIG. 3  shows a graph  35  of the voltage drop at different points in the electrochemical cell of  FIG. 2 . Horizontal axis  30  shows the axial position in inches. Wafer  20  is at the origin, 0 inches on horizontal axis  30 . Vertical axis  32  shows the electrical potential in volts. Graph  35  shows that voltage drops exist at both electrodes, and at both surfaces of wafer  20 . 
         [0039]      FIG. 4  shows electron micrographs of porous silicon layers created in accordance with the present disclosure. 
         [0040]      FIG. 5  shows a finished solar cell substrate created by using a porous silicon sacrificial layer in accordance with the present disclosure. 
         [0041]      FIG. 6  illustrates a basic process flow for creating these cells. At step  61 , bulk p-type wafer  10  has undergone frontside lithography and DRIE. The lithography has left layer  71  of resist, and the DRIE has created trenches  11 . 
         [0042]    At step  62 , resist  71  has been stripped away from wafer  10 , and wafer  10  has been cleaned. Then a sacrificial layer system  12  of porous silicon has been grown on the frontside of wafer  10 . 
         [0043]    At step  63 , solar cell substrate  14  has been epitaxially deposited onto sacrificial layer system  12 . At step  64 , substrate  14  has been diced to the correct size (in one embodiment, five inches square), and its backside has been lapped (in one embodiment, to approximately 260 μm). 
         [0044]    At step  65 , sacrificial layer system  12  has been selectively etched, releasing substrate  14  from wafer  10 . 
         [0045]    The present disclosure is focused on the characterization of films treated with varying levels of porosity and annealing conditions relative to etch rate and compatibility with several etch chemistries. 
         [0046]    The present disclosure teaches a porous silicon process system used to develop a high quality porous silicon electro-etching process that can be scaled into high volume PV cell manufacturing and can deliver very high wafer throughputs, on the order of 1,500 to 2,000 substrates per hour. 
         [0047]    To accomplish these wafer throughputs, the present disclosure teaches transitioning from the present single-wafer, cylindrical, sealed electrolytic “chamber” configuration to an open-cell, unconfined or suitably confined multi-wafer immersion configuration for the silicon electro-etching process. This transition may enable high-throughput, low cost-of-ownership in-line conveyor style wafer handling and transport. 
         [0048]    Because the silicon wafer may have a higher resistance than the surrounding electrolyte, if a conduction path is available that does not pass through the wafer, current may flow through the electrolyte without affecting the wafer. It is thus an object of the present disclosure to eliminate such conduction paths that do not pass through the wafer. A wafer transport pallet that isolates electrochemical conduction paths other than through the silicon wafer may force the electrical field to pass only through the silicon wafer. 
         [0049]      FIG. 7  shows a cross-sectional view of an embodiment of a stationary immersion tank (in which the wafers do not move through the tank) designed for anodizing several wafers at once. A plurality of wafers  10  are submerged in an electrolyte, and electrodes  24  and  26  cause electrical current to flow through them. 
         [0050]      FIG. 8  shows a top view of a similar stationary immersion tank embodiment. As shown, the tank may be sized so that wafers  10  form a seal with its side walls  81  as well as the top and bottom (not shown). Such a design may reduce the conduction paths that do not pass through the wafers, forcing current to flow through the wafers. In the stationary immersion tank design shown in  FIGS. 7 and 8 , the electrode voltage may need to be drastically increased relative to the voltage needed to anodize a single wafer. Because the wafers are electrically connected in series, the electrode voltage may scale approximately linearly with the number of wafers in the tank. 
         [0051]    Palletized wafer handling may allow a higher rate of wafer throughput than the stationary immersion tank methods of  FIGS. 7 and 8  and other methods previously known in the art. The pallet of the present disclosure may be used both to transport the wafer through the immersion electro-etching process and also to provide electrochemical isolation between the positive and negative electrodes in the cell without the need to directly contact the frontside of the wafer being electro-etched. 
         [0052]    An embodiment  90  of a pallet according to the present disclosure is shown in  FIG. 9 . Pallet  90  includes a beveled circular opening  91  sized to fit the wafer. It also may include wheels  92  that fit into tracks and are used to guide the pallet on its path through the apparatus of the present disclosure. Pallet  90  may be made of a non-conductive material such as high-density polyethylene (HDPE). A plurality of pallets may be linked together, as shown in  FIG. 10 , for transport through a palletized immersion tank. 
         [0053]      FIGS. 11A and 11B  show views of one embodiment of a palletized immersion tank. In this embodiment, cathode  26  and anode (not shown) are elongated or suitably positioned electrodes to provide a uniform electric field across the wafer, extending along a substantial part of the length of the immersion tank. This configuration allows wafers to be anodized essentially continuously as they pass through the tank on pallets  90 . 
         [0054]      FIG. 12  shows a palletized immersion tank apparatus  100  including a plurality of pallets linked together in a loop and moving through a palletized immersion tank. Wheels  92  fit into tracks  94  on side plate  95  and a corresponding side plate (not shown) on the other side of the tank. Wafers may be automatically loaded onto the pallets before the pallets enter electrolyte  93  and automatically unloaded after they have passed through it and have emerged on the other side of the tank. A palletized immersion tank as shown in  FIG. 12  may allow silicon wafers to be treated serially as they pass through the electrolyte bath, thus enabling a high-throughput porous silicon system. 
         [0055]    The present disclosure includes a pallet-based wafer transport system, where the electrolytic cell is oriented vertically, with the wafer frontside facing upward and the wafer backside facing downward. The wafer transport pallets may be connected in-line and oriented perpendicular to the vertical electrolytic cell orientation. This may enable simple in-line wafer transport through the immersion electro-etching process system, while providing a compact spacing of electro-etching cells and a non-confined chamber design. 
         [0056]    The wafer transport pallet-based electrolytic cell design of the present disclosure may eliminate the reliance on circumferential seals applied directly to the front and back of a silicon wafer. The present disclosure relies on a circumferential seal to the silicon wafer backside combined with the pressure head of the electrolyte that is created by a column of electrolyte above the silicon wafer and pallet. Since the frontside seal is eliminated, electro-etching may span the entire front surface of the wafer, with no exclusion zones from the wafer center to around the wafer edge. Thus, this design may provide full wafer edge bevel wrap-around electro-etching due to the lack of a frontside wafer seal. This is an improvement over prior art electro-etching systems, which may have difficulty etching a wafer all the way to its edge. 
         [0057]      FIG. 13  shows a cross-sectional view of two electrolytic cells  150  that may be placed inside an immersion tank apparatus such as apparatus  100 . Cathodes  101  are shown at the top of the electrolytic cells, facing the frontside of wafers as wafers pass through the system. Anodes  102  are shown at the bottom of the electrolytic cells, facing the backside of the wafers. High velocity jets (not shown) or other optimized flow dynamics may be used to sweep away gas evolved at the cathodes and anodes during anodizing, to maintain a good electrical connection. 
         [0058]      FIG. 14  shows a schematic cross-sectional view of a palletized immersion tank incorporating a plurality of electrolytic cells  150 . A motor (not shown) conveys pallets  90  in a loop through the electrolyte and the plurality of cells  150 . Wafers may be loaded onto pallets at point  151 . From there, they pass through cells  150  in the process tank and are electro-etched. Electrolyte may be rinsed from the wafers in rinse tank  152 , which in some embodiments may contain deionized water. Wafers may then be unloaded at point  153  and further processed.  FIG. 15  shows an isometric view of the same embodiment. 
         [0059]      FIG. 16  shows another embodiment of an electrolytic cell in accordance with the present disclosure. The embodiment shown in  FIG. 16  does not necessarily rely on palletized wafer handling. 
         [0060]    Wafer  200  may be inserted into the electrolytic chamber by any suitable mechanism known in the art. For example, a robotic arm could be used to place the wafer in the chamber. 
         [0061]    Inside the chamber, the back side of wafer  200  may rest on a circumferential sealing mechanism. As shown in  FIG. 16 , one possible sealing mechanism is a lip of a diameter somewhat smaller than the diameter of wafer  200 . Lip  210  may be part of the chamber wall itself, or it may be, e.g., a ring inserted into the chamber and attached to the interior wall. 
         [0062]    As shown in  FIG. 16 , the present disclosure does not necessarily require palletized wafer handling to achieve its non-frontside-contact seal. A pressure differential between the electrolyte in the top of the chamber and the electrolyte in the bottom of the chamber may provide a seal between wafer  200  and lip  210  regardless of the presence or absence of a pallet. 
         [0063]    A silicon wafer electro-etching cell in which the silicon wafer has a three dimensional surface topography that forms a cavity or trench pattern may be used in the formation of crystalline silicon PV solar cell substrates. The silicon PV substrate may be formed on a layer of porous silicon using gas-phase deposition of silicon and then released from the fragile structure provided by the porous silicon layer. The porous silicon layer produced by this system is used as a release layer for the gas-phase deposited silicon substrate. The 3D patterned silicon wafer processed through this system is referred to in the FIGURES as a template. 
         [0064]    The silicon wafer template is the equivalent of a 3D reverse mold for the fabrication of 3D shaped silicon substrates. This pallet-based non-frontside-sealed electro-etching process cell design also has the advantage that frontside template topography does not interfere with the ability to produce a continuous, high-uniformity porous silicon layer, since there is no direct-contact frontside seal on the template wafer. 
         [0065]    The present disclosure includes an open electrolytic cell that applies a differential pressure (top vs. bottom) on a silicon wafer by confining a tall column of electrolyte on the frontside of the wafer and providing an electrolytic contact on the backside of the silicon wafer that applies little or no upward force to the wafer. This ensures a differential pressure load on the wafer, which compresses the seal between the wafer backside and the pallet top-edge. 
         [0066]    A non-confined silicon wafer electro-etching cell design may transport silicon wafers on pallets that are transported through a single or a series of electrolytic cells using a continuous conveyor system, or it may simply rely on a lip inside the electrolytic cells to support the wafer and ensure a uniform electric field across the entire wafer. 
         [0067]    The present disclosure provides an electro-etching system which consists of conveyorized transport of wafer-holding pallets, in which the pallets form an integral and critical functional component of the electrolytic cell and a means of sealing a silicon wafer solely from the backside of the wafer. This sealing allows the prevention of shadowing, blocking, and exclusion zones on the wafer frontside. The pallets also provide transport from wafer loading to wafer un-loading through the electro-etching system. The pallets are a component of some embodiments of the present disclosure, but they are not a necessary component of all embodiments. 
         [0068]    The transition from a single-wafer sealed cylindrical chamber in known systems to the newly presented in-line immersion configuration may result in a significant increase in the electrical field and an improved porous silicon distribution across the surface of the wafer in process. 
         [0069]    The pallet and conveyor based in-line immersion porous silicon electro-etching process system embodiment of the present disclosure is designed with several key components and design considerations, which may be varied in order to change the characteristics of the resulting system. Some of these design considerations include the following: electrode shape, size and spacing; electrode segmentation (multi-staged electrodes); electrode material; electrode current density; AC, DC, or pulsed current supply; wafer-to-electrode spacing; wafer configuration (topography, via holes, wafer thickness, wafer doping conditions, and surface treatments); wafer orientation within the wafer processing zone; wafer processing zone shape and size; wafer transport speed through the processing zone; reactant-gas extraction from the wafer in process (avoidance of gas bubbles and the resulting blocked electro-etching); electrolyte concentrations, flow rates, and flow direction; and electrolyte stability. 
         [0070]    The foregoing description of embodiments is provided to enable a person skilled in the art to make and use the disclosed subject matter. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without the use of the innovative faculty.