Abstract:
A neutral point clamped, multilevel level converter includes a DC voltage link; a first capacitor coupling one side of the DC link to a neutral point; a second capacitor coupling another side of the DC link to the neutral point; a plurality of phase legs, each phase leg including switches, each phase leg coupled to an AC node; a current sensor associated with each AC node; and a controller generating a PWM signal to control the switches, the controller generating a current zero sequence component in response to current sensed at each of the current sensors, the controller adjusting a modulation index signal in response to the current zero sequence component to produce the PWM signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a divisional of U.S. patent application Ser. No. 14/646,465, filed May 21, 2015, which is a U.S. National Stage Application of PCT/US2012/066200, filed Nov. 21, 2012, and all the benefits accruing therefrom under 35 U.S.C. §119, the contents of which in its entirety are herein incorporated by reference. 
     
    
     FIELD OF INVENTION 
       [0002]    The subject matter disclosed herein relates generally to the field of power conversion systems, and more particularly, to a neutral point clamped multilevel converter. 
       DESCRIPTION OF RELATED ART 
       [0003]    Neutral point clamped (NPC) multilevel converters are used to convert a DC signal to an AC signal and to convert an AC signal to a DC signal. One problem with neutral point clamped multilevel converters is neutral point (NP) voltage balancing. Correct operation of a three level NPC converter requires that the voltage across both dc-link capacitors be the same. This ensures that the voltage stress across each of the semiconductor devices is the same, uniformly spreading switching losses and improving reliability. The NP voltage balancing problem arises from the existence of a non-zero NP current. 
         [0004]    Existing NP voltage balancing techniques, without additional apparatus, are based on common mode voltage injection, resulting in very uneven thermal stress among different power semiconductor devices within the NPC converter. This results in overrating the semiconductor devices and/or limiting the operating range of the converter in order to stay within the thermal constraints of all devices. The thermal stress of a power semiconductor device can be measured with its junction-to-case temperature rise (ΔT jc ) under load. The maximum power throughput of a converter, as well as the expected lifetime of the devices, is limited by the highest ΔT jc , which is usually seen in the neutral diodes in the case of a three-level NPC converter. 
         [0005]    Existing pulse width modulation (PWM) schemes attempt to address drawbacks of NPC multilevel converters. Existing PWM schemes attempt to minimize switching losses in the NPC converter. These schemes result in undesired neutral point current and a ΔT jc  that is uneven among devices, with the highest thermal stress on the neutral diodes. Other PWM techniques can be used to minimize the NP current. Although the NP current is minimized, the neutral diodes are still subject to substantially more thermal stress than other devices. 
       BRIEF SUMMARY 
       [0006]    According to an exemplary embodiment of the invention, a neutral point clamped, multilevel level converter includes a DC voltage link; a first capacitor coupling one side of the DC link to a neutral point; a second capacitor coupling another side of the DC link to the neutral point; a plurality of phase legs, each phase leg including switches, each phase leg coupled to an AC node; a current sensor associated with each AC node; and a controller generating a PWM signal to control the switches, the controller generating a current zero sequence component in response to current sensed at each of the current sensors, the controller adjusting a modulation index signal in response to the current zero sequence component to produce the PWM signal. 
         [0007]    According to another exemplary embodiment of the invention a neutral point clamped, multilevel level converter includes a DC voltage link; a first capacitor coupling one side of the DC link to a neutral point; a second capacitor coupling another side of the DC link to the neutral point; a plurality of phase legs, each phase leg including devices, the devices including clamping diodes and switches, each phase leg coupled to an AC node; and a controller generating a PWM signal to control the switches, the controller providing one of thermal balance across the devices and neutral point current balance in response to a thermal balance enable signal. 
         [0008]    Other aspects, features, and techniques of embodiments of the invention will become more apparent from the following description taken in conjunction with the drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    Referring now to the drawings wherein like elements are numbered alike in the FIGURES: 
           [0010]      FIG. 1  is a schematic diagram of an NPC multilevel converter in an exemplary embodiment; 
           [0011]      FIG. 2  depicts a PWM control process in an exemplary embodiment; 
           [0012]      FIG. 3  depicts a PWM control process in another exemplary embodiment; and 
           [0013]      FIG. 4  depicts a balance regulator in an exemplary embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0014]      FIG. 1  is a schematic diagram of an NPC three phase, three level converter in an exemplary embodiment. The converter can operate in a generative mode or a regenerative mode. In generative mode, a DC signal from DC link  12  is converted to an AC signal. Two capacitors  18  are connected in series across the DC link  12 , with the capacitor junction being referred to as the neutral point (NP). Converter  10  generates a single phase AC signal at each of AC nodes A, B and C. Each leg  14  of the converter  10  generates one of the AC phases. As known in the art, switches Q are controlled by a controller  16  to generate AC waveforms. Each leg  14  includes clamping neutral diodes, D, to clamp the leg output to a neutral point NP. In regenerative mode, an AC signal on one or more of AC nodes A, B and C is converted to a DC signal and supplied to DC link  12 . In regenerative mode, switches Q are controlled by controller  16  to generate DC signal at DC link  12 . Switches Q may be transistors as known in the art. 
         [0015]    To reduce NP current, controller  16  generates at least one zero sequence component that is combined with a modulation index signal used to generate PWM signals for switches Q. Controller  16  monitors voltage over the capacitors  18  through voltage sensors  20 . Controller  16  monitors current at each AC node through current sensors  22 . The two voltage measurements and three current measurements are used to adjust the modulation index signal to reduce NP current. 
         [0016]      FIG. 2  depicts a PWM control process in an exemplary embodiment. The control process may be executed by controller  16 . Controller  16  may be implemented using a general-purpose microprocessor executing a computer program stored on a storage medium to perform the operations described herein. Alternatively, controller  16  may be implemented in hardware (e.g., ASIC, FPGA) or in a combination of hardware/software. 
         [0017]    As shown in  FIG. 2 , the current sensed at each AC node, Ia, Ib and Ic, is inverted at a respective inverter  30 . The minimum inverted current is subtracted from the maximum inverted current at current combiner  32 . The combined inverted current is scaled by a scaling factor, K scaling , at current scaler  34 . The output of current scaler  34  is a current zero sequence component. 
         [0018]    The voltage sensed across each capacitor  18  is inverted at a respective inverter  30 . The inverted voltages are subtracted at voltage combiner  36 . The combined inverted voltage is scaled by a balancing factor, K balancing , at voltage scaler  38 . The output of voltage scaler  38  is a voltage zero sequence component. 
         [0019]    The current zero sequence component and voltage zero sequence component are combined at combiner  40  to produce a combined zero sequence component. A multiplier  42  multiplies the combined zero sequence component by 1 or −1, depending on a direction of quadrature current, Iq. Selector  44  selects 1 if Iq is less than zero and selects −1 if Iq is greater than zero. In exemplary embodiments, Iq will be positive in generative mode and negative in regenerative mode. 
         [0020]    The combined zero sequence component is amplified at amplifier  46 . The output of amplifier  46  is provided to a combiner  48 , where they combined zero sequence component is added to a modulation index signal from a space vector modulation (SVM) unit  50 . The SVM unit  50  executes an algorithm to generate modulation index signals that are used by PWM unit  52  to control the duty cycle of PWM signals applied to switches Q. The combined zero sequence component is added to the modulation index signal prior to providing the modulation index signals to the PWM unit  52 . 
         [0021]    The process of  FIG. 2  reduces NP current by creating two separate zero sequence components (i.e., a current zero sequence component and a voltage zero sequence component), that are added or subtracted from the modulation index signal dependent upon whether the converter  10  is working in the generative or regenerative mode. 
         [0022]      FIG. 3  depicts a control process in exemplary embodiments for providing thermal balance across switches and balancing NP current. The process of  FIG. 3  may be implemented by controller  16 . An outer regulator  70  receives control commands and state feedback signals to generate direct (D) and quadrature (Q) current commands, i* d  and i* q . The control commands may be real and reactive power, DC-link voltage, etc., from an external control system. The state feedback signals may be real and reactive power, DC-link voltage, etc. 
         [0023]    The direct (D) and quadrature (Q) current commands, i* d  and i* q , are provided to direct-quadrature current regulator  72  which generates D-Q duty cycle commands based on the commanded direct current, i* d , commanded quadrature current, i* q , measured direct current, id, and measured quadrature current, i q . Direct-quadrature current regulator  72  generates a commanded quadrature duty cycle, D* q , and a commanded direct duty cycle, D*d. A duty cycle transform  74  converts the commanded quadrature duty cycle, D* q , and commanded direct duty cycle, D* d , into a commanded three phase duty cycle D* abc1 . Duty cycle transform  74  applies a DQ/ABC transformation as known in the art. The angle θ is the DQ/ABC rotational transformation angle. 
         [0024]    The commanded three phase duty cycle, D* abc1  is provided to a balance regulator  78 . An exemplary balance regulator  78  is depicted in  FIG. 4 . Balance regulator  78  provides either thermal balance or NP current balance. A thermal balance enable signal, ENBL th , is provided to the balance regulator  78 . The thermal balance enable signal, ENBL th , is used to select one of thermal balancing or NP current and voltage balancing. Feedback is provided to the balance regulator  78  as described in further detail with reference to  FIG. 4 . The output of balance regulator  78  is a balanced commanded three phase duty cycle, D* abc  provided to a PWM modulator  94 . 
         [0025]      FIG. 4  depicts a balance regulator  78  in an exemplary embodiment. Operation of the balance regulator  78  includes determining the state of the thermal balance enable signal, ENBL th , at comparator  80 . The thermal balance enable signal, ENBL th , may set or reset for each PWM cycle based on the expected thermal stress of all the devices (i.e., diodes and switches). For instance, thermal balance enable signal, ENBL th , is set when the expected ΔT jc  difference between the neutral diodes and other devices exceeds the preset threshold. The thermal balance enable signal, ENBL th , it is reset when the ΔT jc  difference is acceptable. The thermal balance enable signal, ENBL th , can be pre-programmed and/or determined dynamically based on the D* abc1  and feedback signals. For example, in traction applications such as elevators and escalators, where the driving cycle profiles are pre-defined in the controller software, the thermal balance enable signal, ENBL th , can be pre-programmed to enhance the benefits from the thermal balancing algorithm. 
         [0026]    If the thermal balance enable signal, ENBL th , is active (i.e. set), then a thermal balance regulator  82  is used to generate a thermal balanced, commanded three phase duty cycle D* abc . Thermal balance regulator  82  uses a bipolar modulator  84  to apply a bipolar modulation function. In the bipolar modulation mode, the phase output voltage level resides mostly at the positive and negative rails of DC link  12 , except for very small period at the NP during a dead-time. The dead-time is adopted to prevent shoot-through across the DC link  12  as well as to guarantee low dv/dt stress at the AC nodes, A, B, C. The bipolar modulation functions applied by bipolar modulator  84  to produce a thermal balanced, commanded three phase duty cycle D* abc  are shown in equation (1). In equation (1), upper arm refers to a pair of switches, Q, coupled between a positive DC voltage and an AC node and lower arm refers to a pair of switches, Q, coupled between a negative DC voltage and the AC node. 
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         [0027]    If the thermal balance enable signal, ENBL th , is inactive (i.e. reset) at comparator  80 , then NP balance regulator  86  is used to generate an NP balanced, commanded three phase duty cycle D* abc . Neutral point balance regulator  86  includes an NP bipolar modulator  88  that receives the commanded three phase duty cycle, D* abc1 , and system feedback. The feedback includes various operating information of the converter depending on the type of NP-balancing algorithm implemented. One exemplary NP-balancing algorithm is that shown in  FIG. 2 . In that case, the feedback includes the three-phase currents, Q-axis component of the current, and upper and lower DC bus voltages. Embodiments are not limited to the NP-balancing operations shown in  FIG. 2 , and the other NP-balancing operations may be implemented by the NP balance regulator  86 . The output of the neutral point balance regulator  86  is a neutral point balanced, commanded three phase duty cycle, D* abc . 
         [0028]    Referring back to  FIG. 3 , either the thermal balanced, commanded three phase duty cycle, D* abc , or the NP balanced, commanded three phase duty cycle, D* abc , is provided to a PWM modulator  94  to generate PWM signals to drive the converter  10 . 
         [0029]    Balance regulator  78  controls both the NP current and NP voltage allowing the DC-link capacitance values to be reduced. Additionally, balance regulator  78  distributes thermal stress more evenly among all devices (i.e., diodes D and switches Q), which translates into an increase in converter power throughput and/or an increase in expected device lifetime. These benefits are achieved without using higher rated devices or adding extra circuit components, with minimal additional computational power. 
         [0030]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. While the description of the present invention has been presented for purposes of illustration and description, it is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications, variations, alterations, substitutions, or equivalent arrangement not hereto described will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. Additionally, while the various embodiments of the invention have been described, it is to be understood that aspects of the invention may include only some of the described embodiments. Accordingly, the invention is not to be seen as being limited by the foregoing description, but is only limited by the scope of the appended claims.