Abstract:
In one embodiment, an apparatus includes a first supply voltage and a second supply voltage. Level shifter circuitry is configured as a first voltage battery to shift a first voltage and a second voltage battery to shift a second voltage. A first circuit receives the shifted first voltage and sets a third voltage, and receives the shifted second voltage and sets a fourth voltage. The shifted first voltage is greater than the first supply voltage and the shifted second voltage level is less than the second supply voltage. A second circuit sets a fifth voltage and a sixth voltage. The fifth voltage follows the third voltage and the sixth voltage following the fourth voltage.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     The present disclosure claims priority to U.S. Provisional App. No. 61/351,574 for “Novel High Speed Voltage Buffer for Switched Capacitor Data Converters” filed Jun. 4, 2010, which is incorporated herein by reference in its entirety for all purposes. 
    
    
     BACKGROUND 
     Particular embodiments generally relate to reference generators. 
     Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section. 
     High-speed data converters use internal reference buffers to provide references. For example, the references may be provided to an analog to digital converter (ADC).  FIG. 1  shows a conventional voltage reference buffer. Transistors M 1  and M 2  share a same current Id 1  to generate output voltages Vrp and Vrn. The gate voltages Vg 1  and Vg 2  of transistors M 1  and M 2 , respectively, are biased by a replica circuit (e.g., a transistor M 3 , a resistor R 2 , and a transistor M 4 ) such that output voltage Vrp is set at 1.3V and output voltage Vrn is set at 0.3V. 
     A resistor R 1  is adjusted to establish current Id 1  as (voltage Vrp−voltage Vrn)/resistance R 1 , where current Id 1  is directly related to the noise performance of the reference buffer. In operation, the voltage Vrp will go down at a moment when the reference voltage buffer is switched to sampling capacitors of the ADC. At this time, the current going through transistor M 1  increases and the equivalent output impedance drops to help bring voltage Vrp up. The mechanism for the negative output voltage Vrn is the same, except that the swing direction is in the opposite direction. 
     In some cases, gate voltages Vg 1  and Vg 2  may need to go beyond power supply voltages of Vdd and Vss because of the voltage levels of output voltages Vrp and Vrn, respectively. For example, gate voltage Vg 1  needs to be above the output voltage Vrp plus the threshold voltage of transistor M 1  and gate voltage Vg 2  needs to be below the output voltage Vrn plus the threshold voltage of transistor M 2 . 
     Positive and negative boosted voltages Vdd 2  and Vss 2  are generated to overcome the above problem. Voltages Vdd 2  and Vss 2  are used to supply the minimum required currents to set up the desired voltages Vg 1  and Vg 2 . Voltages Vdd 2  and Vss 2  may be generated on an integrated circuit (IC) chip that includes the voltage reference buffer. For example, a charge pump that includes a flying capacitor may be used to generate voltages Vdd 2  and Vss 2 . In this case, the flying capacitor takes up area on the chip. 
     Also, the current through transistors M 5  and M 8  may be about 100-200 μA. The current is delivered by the on-chip charge pump, which requires a certain size of flying capacitor. This increases the area used and also power consumption. A power supply ripple is also introduced that may reduce the accuracy of the voltage reference buffer. 
       FIG. 2  depicts a second conventional voltage reference buffer  200 . Reference buffer  200  uses two positive supply reference voltages Vdd 1  and Vdd 2 , and one ground voltage Vss. The negative reference voltage Srefn is delivered by a constant current sink. Bias currents through first and second transistor followers  25  and  26  are provided by first and second current transistors  29  and  30  in response to a bias voltage Vb. Transistor followers  25  and  26  convert first and second voltage signals at the gates of transistor followers  25  and  26  to first and second reference signals Srefp and Srefn. 
     When reference buffer  200  is coupled to dynamic charge sampling capacitors of an ADC, a transient voltage at voltage Srefn goes up at the moment when reference buffer  200  is switched to the sampling capacitors. Voltage Srefn is then pulled down by the constant current sink of transistor  30 , and not by positive feedback mechanism. Thus, the settling speed of voltage Srefn is limited by the constant current sink. Further, because the current sink through transistor  30  is constant, the constant current needs to be high such that enough current can be sinked to increase voltage Srefn. This increases the power used and also limits the amount of current that can be sunk. Also, a charge pump may be needed to generate the boosted positive supply voltage Vdd 1 , which increases the area used on the chip as described above. 
     SUMMARY 
     In one embodiment, an apparatus includes a first supply voltage and a second supply voltage. Level shifter circuitry is configured as a first voltage battery to shift a first voltage and a second voltage battery to shift a second voltage. A first circuit receives the shifted first voltage and sets a third voltage, and receives the shifted second voltage and sets a fourth voltage. The shifted first voltage is greater than the first supply voltage and the shifted second voltage level is less than the second supply voltage. A second circuit sets a fifth voltage and a sixth voltage. The fifth voltage follows the third voltage and the sixth voltage following the fourth voltage. 
     In one embodiment, the first circuit and the second circuit source current when the fifth voltage falls below a first level and the first circuit and the second circuit sink current when the sixth voltage rises above a second level. 
     In one embodiment, the first voltage battery and the second voltage battery provide a direct current (DC) shift. 
     In another embodiment, an apparatus includes a first supply voltage and a second supply voltage. A first amplifier receives i) a first reference voltage and ii) a first feedback voltage, and outputs a first comparison signal. A first level shifter is configured as a first voltage battery to shift a first comparison voltage determined from the first comparison signal. A first transistor receives the shifted first comparison voltage as a first gate voltage and sets the first feedback voltage. The first gate voltage is greater than the first supply voltage. A second transistor sets a first output voltage. The first output voltage follows the first feedback voltage. A second amplifier receives i) a second reference voltage and ii) a second feedback voltage, and outputs a second comparison signal. A second level shifter is configured as a second voltage battery to shift a second comparison voltage determined from the second comparison signal. A third transistor receives the shifted second comparison signal as a second gate voltage and sets the second feedback voltage. The second gate voltage is less than the second supply voltage. A fourth transistor sets a second output voltage. The second output voltage follows the second feedback voltage. 
     In one embodiment, the first level shifter and the second level shifter do not provide a constant current. 
     In one embodiment, the first voltage battery and the second voltage battery provide a direct current (DC) shift of the first comparison voltage and the second comparison voltage, respectively. 
     In another embodiment, a method includes shifting a first voltage using a first voltage battery; shifting a second voltage using a second voltage battery; receiving the shifted first voltage and setting a third voltage, wherein the shifted first voltage is greater than a first supply voltage; receiving the shifted first voltage and setting a fourth voltage, wherein the shifted second voltage is less than a second supply voltage; setting a fifth voltage based on the shifted first voltage, the fifth voltage following the third voltage; and setting a sixth voltage based on the shifted second voltage, the sixth voltage following the fourth voltage. 
     The following detailed description and accompanying drawings provide a more detailed understanding of the nature and advantages of the present invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a conventional voltage reference buffer. 
         FIG. 2  depicts a second conventional voltage reference buffer. 
         FIG. 3  depicts a voltage reference buffer according to one embodiment. 
         FIG. 4  depicts a more detailed example of the voltage reference buffer according to one embodiment. 
         FIG. 5   a  shows an example of a level shifter according to one embodiment. 
         FIG. 5   b  depicts signals Φ 1  and Φ 2  used to open and close switches of the level shifter according to one embodiment. 
         FIG. 6  depicts a simplified flowchart of a method for providing a feedback mechanism using voltage Vrp 0  according to one embodiment. 
         FIG. 7  depicts a simplified flowchart of a method for providing feedback for using voltage Vrn 0  according to one embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Described herein are techniques for a voltage reference buffer. In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of embodiments of the present invention. Particular embodiments as defined by the claims may include some or all of the features in these examples alone or in combination with other features described below, and may further include modifications and equivalents of the features and concepts described herein. 
       FIG. 3  depicts a voltage reference buffer  300  according to one embodiment. Voltage reference buffer  300  uses one positive supply Vdd and one negative supply ground Vss. In one embodiment, supplies Vdd and Vss are the only supplies used by voltage reference buffer  300  to generate output voltages Vrp and Vrn. Accordingly, an on-chip charge pump may not be needed to generate additional boosted supply voltages. This reduces the chip area and also power consumption. 
     Output voltages Vrp and Vrn are set by a current Id 1 . A resistor R 1  is adjusted to establish the current Id 1 . In operation, a first amplifier  304   a  receives a reference voltage Vrefp and a voltage Vrp 0 . Voltage Vrp 0  is received in a feedback loop from an output node Vrp 0 . A second amplifier  304   b  receives a second reference voltage Vrefn and a voltage Vrn 0 . Voltage Vrn 0  is received in a feedback loop from an output node Vrn 0 . Due to the feedback loop, voltages Vrp 0  and Vrn 0  track reference voltages Vrefp and Vrefn, respectively. Also, voltages Vrp and Vrn follow voltages Vrp 0  and Vrn 0 , respectively. 
     A level shifter  302   a  and a level shifter  302   b  are used to achieve the gate voltages Vg 1  and Vg 2  that are needed. This concept will be described in more detail below with respect to  FIG. 4 . Level shifters  302   a  and  302   b  may include voltage batteries. A first voltage battery Vbat 1  may increase a voltage level and a second voltage battery Vbat 2  may reduce a voltage level. A voltage battery may be a circuit that increases a direct current (DC) voltage. 
     An implementation of the voltage batteries will be described below. 
     In operation, amplifier  304   a  compares reference voltage Vrefp and voltage Vrp 0 , and outputs a comparison signal. Gain stage  306   a  may amplify the comparison signal to a voltage Vd 5 . Level shifter  302   a  may then shift the level of the voltage Vd 5  output by gain stage  306   a  to a gate voltage Vgs 1  that is input into a follower circuit  308   a . Gate voltage Vgs 1  is mirrored to follower circuit  310   a  as a gate voltage Vg 1 . 
     In the negative direction, amplifier  304   b  compares reference voltage Vrefn and voltage Vrn 0 , and outputs a comparison signal. Gain stage  306   b  may amplify the comparison signal to a voltage Vd 8 . Level shifter  302   b  may then shift the level of the voltage Vd 8  output by gain stage  306   b  to a gate voltage Vgs 2  that is input into a follower circuit  308   b . Gate voltage Vgs 2  is mirrored to follower circuit  310   b  as a gate voltage Vg 2 . 
     As will be discussed below, the gate voltage Vg 1  of a transistor (not shown) in follower circuit  310   a  may need to go beyond power supply voltage Vdd due to the voltage level at node Vrp. The similar case occurs for a gate voltage Vg 2  of a transistor (not shown) in follower circuit  310   b , but in the opposite direction. Level shifter  302   a  increases the voltage output by gain stage  306   a  when a voltage is needed that is beyond power supply voltage Vdd. Similarly, level shifter  302   b  decreases the voltage output by gain stage  306   b  when a voltage is needed that is below power supply voltage Vss. This allows the required current Id 1  to set up output voltages Vrp and Vrn. 
     In one embodiment, output voltages Vrp and Vrn are used as references in a digital video disk (DVD) player. For example, these reference voltages may be used for an analog-to-digital converter (ADC), such as a pipelined ADC or flash ADC in the DVD player. The reference voltages may be coupled to sampling capacitors in a sample and hold circuit of the ADC to charge the sampling capacitors to desired voltages. In other embodiments, voltage reference buffer may be used in other designs that include a switched capacitor. A first switch may be used to couple voltage Vrp to a first sampling capacitor and a second switch is used to couple voltage Vrn to a second sampling capacitor. The first and second switches are opened and closed. When the first or second switch transitions from an open to closed state, output voltages Vrp or Vrn may be affected. For example, the output voltage Vrp may go down or the output voltage Vrn may go up when voltage reference buffer  300  is coupled to sampling capacitors of the ADC. A feedback mechanism is used to maintain the output voltages Vrp and Vrn at their desired levels by sourcing current to increase voltage Vrp and by sinking current to decrease voltage Vrn. 
     In the feedback mechanism, the output of level shifter  302   a  produces a current Id 2  through resistor R 2 . This sets the voltages Vrp 0  and Vrn 0 . As discussed above, voltages Vrp 0  and Vrn 0  are fed back into amplifiers  304   a  and  304   b . The feedback is used to adjust the output voltages Vrp 0  and Vrn 0  such that they track the reference voltages Vrefp and Vrefn, respectively (e.g., 1.3V and 0.3V, respectively). Output voltages Vrn and Vrp also follow voltages Vrp 0  and Vrn 0 , respectively. For example, follower circuit  310   a  and follower circuit  310   b  are designed to follow follower circuit  308   a  and follower circuit  308   b . Thus, output voltages Vrp and Vrn may be adjusted according to the feedback using voltages Vrp 0  and Vrn 0 , when disturbances cause output voltages Vrp and Vrn to move. The feedback mechanism will be described in more detail below. 
       FIG. 4  depicts a more detailed example of voltage reference buffer  300  according to one embodiment. As shown, a transistor M 1  and a transistor M 2  are biased by gate voltages Vg 1  and Vg 2 , respectively. Transistors M 1  and M 2  share a same current Id 1  through resistor R 1 . Output voltages Vrp and Vrn are set based on the value of resistor R 1  and the current Id 1 . The output impedances at output nodes for voltages Vrp and Vrn are set by the transductance of transistors M 1  and M 2  (e.g., 1/gm1 and 1/gm2, respectively). The output impedances are low to reduce the noise of voltage reference buffer  300 . 
     Because of the level of output voltages Vrp and Vrn, gate voltages Vg 1  and Vg 2  may need to go beyond power supply voltage Vdd. This is because voltage Vrp plus the threshold voltage of transistor M 1  may require a voltage at the gate of transistor M 1  to be greater than Vdd. For transistor M 2 , voltage Vrn plus the threshold voltage of transistor M 2  may require a more negative voltage than Vss to keep transistor M 2  turned on. Accordingly, level shifters  302   a  and  302   b  are used to bias gate voltages Vg 1  and Vg 2 , respectively. This allows voltage reference buffer  300  to operate with one positive supply Vdd and one negative supply ground Vss. In one embodiment, an additional positive or negative supply other than supply Vdd and supply Vss is not needed to generate output voltages Vrp and Vrn. 
     In operation, a transistor M 5  and a transistor M 7  form gain stage  306   a . Transistor M 5  receives the output comparison signal of amplifier  304   a . The output comparison signal of amplifier  304   a  depends on the comparison of voltage Vrp 0  and reference voltage Vrefp. Transistor M 7  receives a bias voltage (bp) that sets a drain voltage Vd 5 . The drain voltage Vd 5  may be an amplified voltage of the output comparison signal from amplifier  304   a.    
     Level shifter  302   a  may then shift the drain voltage Vd 5 . For example, level shifter  302   a  provides a DC shift of drain voltage Vd 5 , which increases a gate voltage Vgs 1  at a gate of transistor M 3  and a gate voltage Vg 1  at the gate of transistor M 1 . The gate voltages Vgs 1  and Vg 1  are shifted such that transistors M 3  and M 1 , respectively, are sufficiently biased to have them turned on. For example, gate voltage Vgs 1  is greater than voltage Vrp 0  plus a threshold voltage of transistor M 3  and gate voltage Vg 1  is greater than voltage Vrp plus a threshold voltage of transistor M 1 . 
     For output voltage Vrn, a similar structure is provided but in the opposite swing direction. For example, a transistor M 8  receives the output comparison signal from an amplifier  304   b . Using a transistor M 6  that is biased by bias voltage bp, a voltage Vd 8  is set at the drains of transistors M 6  and M 8 . Level shifter  302   b  is configured to shift the voltage level of voltage Vd 8  down. The voltage is shifted down such that a gate voltage Vgs 2  at transistor M 4  and gate voltage Vg 2  at transistor M 2  are at a level such that transistors M 4  and M 2 , respectively, are turned on. For example, gate voltage Vgs 2  is less than voltage Vrn 0  plus a threshold voltage of transistor M 4  and gate voltage Vg 2  is less than voltage Vrn plus a threshold voltage of transistor M 2 . 
       FIG. 5   a  shows an example of level shifter  302   a  according to one embodiment. Level shifter  302   a  includes a capacitor Cb and a flying capacitor Cf that form a switched capacitor design. The switched capacitor design switches from coupling a voltage battery Vbat to flying capacitor Cf, and then coupling flying capacitor Cf to capacitor Cb. The couplings are controlled by switches  502   a  and  502   b , which are opened and closed according to signals Φ 1  and Φ 2  shown in  FIG. 5   b.    
     In an implementation, switches  502   a  are closed when signal Φ 1  is high (switches  502   b  are also open during this time because signal Φ 2  is low), and a charge from flying capacitor Cf is transferred to capacitor Cb. Capacitor Cb may be coupled between voltage Vd 5  and gate voltage Vgs 1 . The transfer of charge increased the gate voltage Vg 1  at transistor M 1 . When signal Φ 1  is low, switches  502   a  are opened. Also, signal Φ 2  is high, which closes switches  502   b , and couples voltage battery Vbat to flying capacitor Cf. This charges flying capacitor Cf. The process continues as switches  502   b  are opened and switches  502   a  are closed to transfer the charge as discussed above from flying capacitor Cf to capacitor Cb. Level shifter  302   b  may operate similarly except that the voltage polarities are reversed. 
     Level shifter  302   a  is inserted in between the gate of transistor M 3  and the drains of transistors M 5  and M 7  and thus, level shifter  302   a  does not supply any constant current. As a result, the flying capacitor Cf and capacitor Cb may use less area due to not having to supply constant current, such as less area than capacitors used in a charge pump described in  FIGS. 1  and  2 . Accordingly, the area of level shifter  302  may be small when compared to a convention on-chip charge pump. 
     The timing of signals Φ 1  and Φ 2  are set such that they do not generate a ripple during a sample and hold period while dynamically charging sampling capacitors in the ADC. For example, flying capacitor Cf may not be charging capacitor Cb when voltage reference buffer  300  is coupled to the sampling capacitors. Thus, the accuracy of voltage reference buffer  300  may be higher than the conventional reference buffers shown in  FIG. 1  and  FIG. 2 . 
     Also, the amount of current that can be sourced through transistors M 3  and M 1 , or sinked through transistors M 4  and M 2  is not limited. This also provides a low impedance at the output. 
     The feedback mechanism will now be described in more detail. As discussed above, voltages Vrp 0  and Vrn 0  track reference voltages Vrefp and Vrefn, respectively, due to the feedback mechanism. Also, voltages Vrp and Vrn follow voltage Vrp 0  and Vrn 0 , respectively.  FIG. 6  depicts a simplified flowchart  600  of a method for providing a feedback mechanism using voltage Vrp 0  according to one embodiment. At  602 , a voltage Vrp 0  goes low. For example, voltage Vrp 0  may decrease due to output node Vrp being coupled to the sampling capacitors of the ADC. 
     At  604 , voltage Vrp 0  is fed back into the positive terminal of amplifier  304   a . At  606 , the output comparison signal of amplifier  304   a  goes low because the voltage Vrp 0  is below reference voltage Vrefp. 
     At  608 , a voltage Vd 5  goes high at the drains of transistors M 7  and M 5 . At  610 , level shifter  302   a  also shifts the DC voltage level of voltage Vd 5  to increase voltage Vd 5 . This causes the gate voltage Vgs 1  of transistor M 3  to go high. At  612 , voltage Vrp 0  goes high when gate voltage Vgs 1  goes high. This increases the voltage at Vrp 0 . At  614 , output voltage Vrp follows voltage Vrp 0  and goes high. 
       FIG. 7  depicts a simplified flowchart  700  of a method for providing feedback for using voltage Vrn 0  according to one embodiment. At  702 , voltage Vrn 0  goes high. For example, voltage Vrn 0  may increase due to output node Vrn being coupled to the sampling capacitors of the ADC. At  704 , voltage Vrn 0  is fed back into the positive terminal of amplifier  304   b . When voltage Vrn 0  goes above reference voltage Vrefn, at  706 , the output comparison signal in amplifier  304   b  goes high. 
     At  708 , the drain voltage Vd 8  goes low at the drains of transistors M 6  and M 8 . At  710 , level shifter  302   b  shifts the voltage Vd 8  to a lower level. This causes gate voltage Vgs 2  to go low. At  712 , voltage Vrn 0  then goes low when gate voltage Vgs 2  goes low. At  714 , output voltage Vrn follows voltage Vrn 0  and goes low. 
     As used in the description herein and throughout the claims that follow, “a”, “an”, and “the” includes plural references unless the context clearly dictates otherwise. Also, as used in the description herein and throughout the claims that follow, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise. 
     The above description illustrates various embodiments of the present invention along with examples of how aspects of the present invention may be implemented. The above examples and embodiments should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the present invention as defined by the following claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations and equivalents may be employed without departing from the scope of the invention as defined by the claims.