Abstract:
A method for manufacturing a semiconductor device comprises: growing a carbon nano tube on a semiconductor substrate; forming an insulating film in the inside and the outside of the carbon nano tube; and forming a graphene on the surface of the insulating film, thereby securing a channel region corresponding to a region extended by the carbon nano tube to prevent a short channel effect. As a result, channel resistance is reduced to facilitate the manufacturing of the device that can be operated at a high speed. The carbon nano tube is applied to a semiconductor device of less than 30 nm so that a micro-sized semiconductor device can be manufactured regardless of limitation of exposure light sources.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    The priority of Korean patent application No. 10-2010-0020858 filed on Mar. 9, 2010, the disclosure of which is hereby incorporated in its entirety by reference, is claimed. 
       BACKGROUND OF THE INVENTION 
       [0002]    Embodiments of the present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device and a method for manufacturing the same that comprises a gate using a graphene. 
         [0003]    Many of today&#39;s electronic appliances include a semiconductor device. The semiconductor device includes electronic elements such as a transistor, a resistor and a capacitor. These electronic elements are designed to perform a partial function of the electronic device, and integrated on a semiconductor substrate. For example, electronic devices such as a computer or a digital camera include a memory chip for storing information and a processing chip for controlling information. The memory chip and the processing chip include electronic elements integrated on a semiconductor substrate. 
         [0004]    Semiconductor devices are required to be highly integrated in order to satisfy the consumer&#39;s demand for excellent performance and inexpensive price. As the integration of the semiconductor memory device has become higher, the design rule has been reduced so that a pattern of the semiconductor device becomes micro-sized. Due to limits in characteristics of silicon material and in the manufacturing process, high integration and high performance of the silicon-based semiconductor device are difficult. 
         [0005]    As a result, research on the next generation device has been made to overcome the limits of the silicon-based semiconductor device. For example, a nano structure such as a carbon nano tube (CNT) is applied in order to manufacture a micro-sized device with excellent performance. The carbon nano tube has a diameter in the tens of nano meters, thereby facilitating micronization of the device with high mobility, high electric conductivity, high thermal conductivity and strong mechanical intensity. This carbon nano tube has received much attention to overcome limits of the existing device. 
         [0006]    However, since there are problems in applying the carbon nano tube to the semiconductor device, it is difficult to obtain the semiconductor device applied with the carbon nano tube. For example, it is difficult to compose a carbon nano tube with reproducibility and handle the composed carbon nano tube. In order to manufacture a device using a carbon nano tube, a technique of aligning a carbon nano tube in a desired region of a substrate for manufacturing a device. Also, it is difficult to apply a carbon nano tube along with other nano structures in one device, which limits the manufacturing of various high performance devices. As a result, the development of techniques to manufacture a semiconductor device using a carbon nano tube is needed. 
         [0007]    Meanwhile, as the design rule of the semiconductor device is reduced, the corresponding channel length is also decreased, which results in a decrease of the channel length of cell transistors as a storage unit as well as transistors of a peripheral circuit. As a result, it is difficult to obtain a target of a threshold voltage (Vt) of a transistor required in a specific device by the existing plannar transistor structure. Although a technique using a three-dimensional gate has been developed in order to overcome the problem, a complicated technique is required to apply the three-dimensional gate, which results in defects. 
       BRIEF SUMMARY OF THE INVENTION 
       [0008]    Various embodiments of the invention are directed to preventing the short channel effect which results from reduction of the channel length due to high integration of the semiconductor device. 
         [0009]    According to an embodiment of the present invention, a semiconductor device comprises: a carbon nano tube grown on a substrate; an insulating film formed over an inner surface and an outer surface of the carbon nano tube; and a graphene formed over the surface of the insulating film. 
         [0010]    The carbon nano tube is vertically grown over the substrate. 
         [0011]    The insulating film includes a high-K dielectric material. 
         [0012]    The insulating film includes a zirconium oxide, a lead zirconium titanate (PZT) and a hafnium oxide. 
         [0013]    The insulating film includes an oxide film. 
         [0014]    The insulating film includes a nitride film. 
         [0015]    The insulating film includes a carbonized film. 
         [0016]    The graphene includes a mono layer. 
         [0017]    The graphene includes a multi layer. 
         [0018]    According to an embodiment of the present invention, a method for manufacturing a semiconductor device comprises: growing a carbon nano tube on a substrate; forming an insulating film over an inner surface and an outer surface of the carbon nano tube; and forming a graphene on the surface of the insulating film. 
         [0019]    The growing-a-carbon-nano-tube includes: forming a mask pattern to expose a portion of the substrate; increasing the surface energy of the substrate exposed by the mask pattern; and implanting a growth source into the exposed portion of substrate to grow the carbon-nano-tube vertically on the substrate. 
         [0020]    The increasing-the-surface-energy-of-the-semiconductor-substrate includes performing a plasma surface treatment using an inert gas on the exposed portion of the substrate by the mask pattern. 
         [0021]    The increasing-the-surface-energy-of-the-semiconductor-substrate includes forming a silicon oxide film on the semiconductor substrate. 
         [0022]    In the growing-a-carbon-nano-tube, the growth source includes one selected from the group consisting of carbon, hydrogen and combinations thereof. 
         [0023]    The implanting-a-growth-source in the growing-a-carbon-nano-tube is performed by a chemical vapor deposition (CVD) process including a plasma enhanced CVD (PECVD), a metal organic CVD (MOCVD), a low pressure CVD (LPCVD) or a high pressure CVD (HPCVD). 
         [0024]    The growth source in the growing-a-carbon-nano-tube includes CH 4 , C 2 H 6  and C 4 H 8  gases. 
         [0025]    The implanting-a-growth-source in the growing-a-carbon-nano-tube is performed at a temperature ranging from 200 to 1000° C. 
         [0026]    The forming-an-insulating-film is performed using a high-K dielectric material. 
         [0027]    The forming-an-insulating-film includes forming a zirconium oxide, a lead zirconium titanate (PZT) and a hafnium oxide. 
         [0028]    The insulating film includes an oxide film. 
         [0029]    The insulating film includes a nitride film. 
         [0030]    The insulating film includes a carbonized film. 
         [0031]    The forming-an-insulating-film is performed by an atomic layer deposition (ALD) process or a CVD process. 
         [0032]    The forming-a-graphene-on-the-surface-of-the-insulating-film includes: forming a catalyst layer on the surface of the insulating film; and implanting a growth source on the catalyst layer to grow the graphene. 
         [0033]    The forming-a-catalyst-layer is performed by a CVD process or an ALD process. 
         [0034]    The forming-a-catalyst-layer includes forming one selected from the group consisting of Fe, Ni, Co and combinations thereof. 
         [0035]    The implanting-a-growth-source-on-the-catalyst-layer-to-grow-the-graphene is performed using one selected from the group consisting of CH 4 , C 2 H 6  and C 4 H 8  gases, a hydrogen gas, an argon gas and combinations thereof. 
         [0036]    The growing-a-graphene is performed by a CVD process or an ALD process. 
         [0037]    According to another embodiment of the present invention, a semiconductor device comprises: a carbon nano tube pattern formed vertically on a substrate; an insulating pattern formed over the carbon nano tube; and a graphene pattern formed over the insulating film, wherein the carbon nano tube pattern, the insulating pattern, the graphene pattern define a vertical gate pattern on the substrate, the graphene pattern defining a gate electrode. 
         [0038]    The insulating pattern includes a first insulating pattern formed over an outer surface of the carbon nano tube pattern; and a second insulating pattern formed over an inner surface of the carbon nano tube pattern. 
         [0039]    The graphene pattern includes a first graphene pattern formed over the first insulating pattern, and a second graphene pattern formed over the second insulating pattern. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0040]      FIG. 1  is a plan view illustrating a semiconductor device according to an embodiment of the present invention. 
           [0041]      FIGS. 2   a  to  2   e  are cross-sectional diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0042]    The present invention will be described in detail with reference to the attached drawings. 
         [0043]      FIG. 1  is a plan view illustrating a semiconductor device according to an embodiment of the present invention. 
         [0044]    Referring to  FIG. 1 , a semiconductor device includes a carbon nano tube  110  grown on a semiconductor substrate  100 , an insulating film  120  (see  FIG. 2   c ) formed in the inside and the outside of the carbon nano tube  110 , and a graphene  130  formed on the surface of the insulating film. The carbon nano tube  110  represents a region where a channel is formed. The insulating film  120  represents a gate insulating film, and the graphene  130  represents a gate electrode. 
         [0045]    A plasma surface treatment using an inert gas is performed on the semiconductor substrate  100  to grow the carbon nano tube  110  under an atmosphere of carbon, hydrogen or a combination thereof. Since the carbon nano tube  110  is vertically grown, it can provide a structure that can be highly integrated in a narrow area, and easily fabricated free from the limitations accompanied with a conventional exposure process. 
         [0046]    The insulating film  120  includes a high-K dielectric material. More specifically, the insulating film  120  includes zirconium oxide, lead zirconium titanate (PZT), hafnium oxides like SiO 2 , SiON, SiO 2 /Si 3 N 4 , TaON, Ta 2 O 5 , Al 2 O 3 , HfO 2 , TiO 2 , SrTiO 3 , (Ba, Sr)TiO 3 , (Pb, Sr)TiO 3 , ZrO 2 , and any combination thereof. 
         [0047]    The insulating film  120  includes an oxide film, a nitride film, a carbonized film and the like. The graphene  130  includes a mono layer or a multi layer. The mono layer means a single layered carbon layer, and the multi layer means two or three layered carbon layer. 
         [0048]      FIGS. 2   a  to  2   e  are cross-sectional diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. 
         [0049]    Referring to  FIG. 2   a , a mask pattern  105  is formed on the semiconductor substrate  100 . The mask pattern  105  may use a photoresist pattern obtained by performing an exposing and developing process on a photoresist pattern. A plasma surface treatment using an inert gas is performed on the resultant structure including the mask pattern  105  to make the surface of the semiconductor substrate  100  exposed by the mask pattern  105  rough. The mask pattern  105  may be replaced with other materials than the photoresist film so long as the plasma surface treatment using the inert gas can be performed to increase the surface energy of the semiconductor substrate  100 . After the mask pattern  105  is formed, the plasma surface treatment using an inert gas is performed on the semiconductor substrate  100  exposed by the mask pattern  105  to increase the surface energy of the semiconductor substrate  100 , thereby facilitating vertical growth of the carbon nano tube in the area where the surface energy is increased. The method of increasing the surface energy of the semiconductor substrate  100  is not limited to the way of using the plasma surface treatment, but a method of forming a silicon oxide on the semiconductor substrate may be used instead. 
         [0050]    Referring to  FIG. 2   b , the carbon nano tube  110  is vertically grown on the upper portion of the semiconductor substrate  100  exposed by the mask pattern  105 , The carbon nano tube  110  is formed using a carbon-containing source for example, a source containing carbon, and hydrogen. 
         [0051]    The carbon nano tube  110  is vertically grown by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, furnace, a laser, plasma, vapor phase growth or electrolysis. More preferably, the vertical growth is performed by a plasma enhanced CVD (PECVD) process, a metal organic CVD (MOCVD) process, a low pressure CVD (LPCVD) process or a high pressure CVD (HPCVD) process. 
         [0052]    As a reaction gas, a carbon-including gas such as CH 4 , C 2 H 6  or C 4 H 8  gas can be employed. The vertical growth is performed at a temperature ranging from 200 to 1000° C. The carbon nano tube  110  serves as a channel. Since the carbon nano tube  110  has a width in the tens of nanos, a plurality of carbon nano tubes may be formed depending on design of the semiconductor device so that a fine width can be easily formed. Also, the carbon nano tube  110  is vertically grown to secure the channel length, thereby improving the characteristics of the semiconductor device. 
         [0053]    Referring to  FIG. 2   c , the insulating film  120  is formed on the substrate  100  and the inner surface and the outer surface of the gate-shaped carbon nano tube pattern  110 . The insulating film  120  includes a high-K dielectric material. For example, the insulating film  120  can be formed of zirconium oxide, lead zirconium titanate (PZT), hafnium oxides, SiON, SiO 2 /Si 3 N 4 , TaON, Ta 2 O 5 , Al 2 O 3 , HfO 2 , TiO 2 , SrTiO 3 , (Ba, Sr)TiO 3 , (Pb, Sr)TiO 3 , ZrO 2 , or a combination thereof. The insulating film  120  may include an oxide film, a nitride film or a carbonized film. The insulating film  120  is formed by an ALD process or a CVD process. The above deposition processes allows the insulating film  120  to be uniformly deposited on the inner surface and the outer surface of the carbon nano tube pattern  110 . The insulating film  120  may serve as a gate insulating film. 
         [0054]    Referring to  FIG. 2   d , a catalyst layer (not shown) is formed on the the first insulating film and the second insulating films  120  by an ALD process or a CVD process. The catalyst layer may be formed of Fe, Ni, Co or a combination thereof, preferably, a graphene layer. The graphene layer  130  is formed by a CVD process, a PVD process, an ALD process, furnace, electricity, laser or plasma using a carbon-containing source such as CH 4 , C 2 H 6  and C 4 H 8  gases along with hydrogen, argon gas etc. The graphene layer  130  can be formed of a mono layer or a multi layer. 
         [0055]    Referring to  FIG. 2   e , the graphene layer  130  and the insulating layer  120  are etched to form a gate structure. More specifically, the first insulating film  120  and the graphene  130  formed on the upper portion of the semiconductor substrate  100  are removed with the graphene  130  formed in a sidewall of the insulating film  120  formed in a sidewall of the carbon nano tube  110  as an etching mask. 
         [0056]    As described above, according to an embodiment of the present invention, a gate body is formed using a carbon nano tube, and an insulating film that serves as a gate insulating film is formed on the gate body. A graphene layer that serves as a gate electrode is grown in the insulating film. Since the carbon nano tube pattern  110  is formed in a gate-shape with a long length, a short channel effect can be prevented. Since the carbon nano tube has a low resistance, when it is employed, a semiconductor device operating at a high speed can be obtained. 
         [0057]    The above embodiments of the present invention are illustrative and not limitative. Various alternatives and equivalents are possible. The invention is not limited by the type of deposition, etching polishing, and patterning steps describe herein. Nor is the invention limited to any specific type of semiconductor device. For example, the present invention may be implemented in a dynamic random access memory (DRAM) device or non volatile memory device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.