Abstract:
To provide a bias circuit for gain control that can reduce gain variation at low-power output, facilitate setting of output power, and is unlikely to be affected by variation in element values and variations among products. Use in an HPA having three bias circuits serially-connected is assumed. Current of the third bias circuit is varied with a square-law characteristic. The square-law characteristic is amplified by a buffer amplifier including a linear amplifier and a peripheral circuit thereof. Output current of the third bias circuit varies depending on a current drivability coefficient of the diode-connected FET branched from the connection point between a constant current source and the linear amplifier. The output current of the third bias circuit is controlled by providing a circuit that draws a certain amount of current from the current flowing in the FET.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    The disclosure of Japanese Patent Application No. 2009-130299 filed on May 29, 2009 including the specification, drawings and abstract is incorporated herein by reference in its entirety. 
       BACKGROUND OF THE INVENTION 
       [0002]    The present invention relates to a method of suppressing variation of control voltage—output power characteristic of a multistage bias circuit with regard to high-frequency power of a wireless communication device, and particularly to a method of suppressing variations among products of control voltage—output power characteristic due to temperature variation or process variation. 
         [0003]    Traditionally, power amplification modules equipped with a variable gain function that makes the output power variable by changing the bias condition of a multistage power amplifier have been widely applied to portable wireless communication devices. One of the problems with the multistage power amplifier is drastic change of control voltage—output power characteristic nearby the threshold voltage of a transistor.  FIG. 1  illustrates an example of a conventional multistage power amplifier. 
         [0004]      FIG. 1  is a block diagram showing a three-stage bias circuit, which is an example of a conventional multistage power amplifier. In addition,  FIGS. 2(   a ) and  2 ( b ) are graphs representing the variation of bias voltage V apc , drain drive current I D1 , I D2  and I D3 , and the three-stage bias circuit P out  when controlled by the bias circuit of  FIG. 1 . Here, the bias voltage V apc , is a signal for feedback-controlling a high-frequency detection signal by comparing a transmission request signal and a detection signal. 
         [0005]    The three-stage bias circuit includes a first bias circuit  1 , a second bias circuit  2  and a third bias circuit  3 , which are serially-connected. Matching circuits are coupled between respective bias circuits and at the output side of the third bias circuit  3 . 
         [0006]    A current mirror circuit is applied to the first bias circuit  1 , the second bias circuit  2 , and the third bias circuit  3  of the three-stage bias circuit. The bias circuit of each stage is controlled by the electric current output from an APC (automatic power control circuit)  4 . 
         [0007]    The APC  4  is a control circuit that outputs control current I bias  to the bias circuit of each stage as appropriate, after voltage to current conversion of the input V apc . 
         [0008]      FIG. 2  ( a ) is a graph illustrating how the drain drive current I D  of each amplifier varies according to the control voltage V apc  added to the APC of the three-stage amplifier bias circuit, and  FIG. 2  ( b ) is a graph illustrating how the output P out  (in dbm) of the three-stage amplifier bias circuit varies according to the voltage V apc  added to the APC of the three-stage amplifier bias circuit. 
         [0009]    That is, the APC of the three-stage amplifier bias circuit performs a linear current control of the first and second stages from the start of control. On the other hand, a control that increases the drain drive current I D  later and more steeply than the first and second stages is performed on the third stage after a voltage exceeding a certain level has been added to the control voltage V apc  (see  FIG. 2  ( a )). 
         [0010]    Such a control brings about a steep variation at the start-up of the current because mutual conductance (gm) of an FET is proportional to the square root of the drain drive current I D , and the variation becomes approximately linear thereafter. By controlling the output P out  of the three-stage amplifier bias circuit in this linear section, it is possible to provide a high-frequency power amplification module having superior control characteristics. 
         [0011]    Japanese Patent Laid-Open No. 2001-102881 (Patent Document 1) discloses a method of providing a multistage, high-frequency power amplification module comprising a plurality of serially-connected MOSFETs, which smoothens the gradient of the linear section to improve control characteristics thereof. 
         [0012]    However, there remains a problem even if the control characteristics are improved by improving the linear section as disclosed in the patent document 1. 
         [0013]    In other words, there exist variations among products at the control in a section accompanied with a steep variation before reaching the linear section, that is, at the start-up.  FIGS. 3(   a ) and  3 ( b ) are graphs illustrating how the output P out  of the three-stage amplifier bias circuit varies due to variations among products.  FIG. 3  ( a ) is a graph illustrating how the drain drive current I D  of each amplifier varies according to the control voltage V apc  added to the APC of the three-stage amplifier bias circuit, and  FIG. 3  ( b ) is a graph illustrating how the output P out  of the three-stage amplifier bias circuit varies according to the voltage V apc  added to the APC of the three-stage amplifier bias circuit. 
         [0014]    As can be seen in  FIG. 3  ( a ), variations among products first occur in the drain drive current I D3  (I D3-1 , I D3-2 , I D3-3 ) of the third stage which is output from the APC. With this being the primary factor, errors may also be included in the output P out  of the three-stage amplifier bias circuit (see  FIG. 3  ( b ) P out-1 , P out-2 , P out-3 ). In other words, control becomes difficult due to overly high sensitivity to bias when setting the output power at a low power level using control bias without being able to sufficiently suppress gain variation. 
         [0015]    The present invention has been made in view of the above circumstances and provides a bias circuit for gain control that can reduce gain variation at low-power output, facilitate setting of output power, and is unlikely to be affected by variation in element values and variations among products. 
         [0016]    The other purposes and the new feature of the present invention will become clear from the description of the present specification and the accompanying drawings. 
       SUMMARY OF THE INVENTION 
       [0017]    The following explains briefly the outline of a typical invention among the inventions disclosed in the present application. 
         [0018]    A bias circuit according to a representative embodiment of the present invention includes a linear amplifier that amplifies current input from an input end; and a resistor coupled to a connection point between the input end and the linear amplifier and grounded via a diode-connected first FET, wherein the linear amplifier, together with a peripheral circuit thereof, composes a buffer amplifier including a threshold voltage offset, and the output of the buffer amplifier is coupled to the base terminal of a second FET. 
         [0019]    In the bias circuit, influence of undesired components of the bias circuit may be excluded by setting current drivability coefficients of the first FET and the second FET. 
         [0020]    In the bias circuit, part of current flowing from the connection point of the resistor and the first FET to the first FET may be drawn. 
         [0021]    In the bias circuit, a current mirror circuit may draw part of current flowing in the first FET. 
         [0022]    A high-power amplifier according to a representative embodiment of the present invention comprises a plurality of serially-connected bias circuits, wherein the bias circuit according to any one of claims  1  to  4  is used as the last-stage bias circuit of the serially-connected bias circuits. 
         [0023]    A portable information terminal using the high-power amplifier falls within the scope of the present invention. 
         [0024]    The following explains briefly the effect acquired by the typical invention among the inventions disclosed in the present application. 
         [0025]    By applying the bias circuit according to representative embodiment of the present invention to a three-stage bias circuit which is an example of multistage power amplifiers, it becomes possible to vary the voltage added to the third stage gate voltage at low output linearly, and not in a square root manner. Sensitivity to the bias voltage of the output power is thereby suppressed, facilitating output power control using the bias voltage. 
         [0026]    In addition, it becomes possible to reduce influence of device variation by modifying the current mirror circuit conventionally used in the bias circuit. Product yield can be improved thereby. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0027]      FIG. 1  is a block diagram illustrating a three-stage bias circuit, which is an example of a conventional multistage power amplifier; 
           [0028]      FIGS. 2(A) and 2(B)  are graphs illustrating variations of drain drive currents I D1 , I D2  and I D3 , and the three-stage bias circuit P out  against bias voltage V apc  when being controlled by the bias circuit of  FIG. 1 ; 
           [0029]      FIGS. 3(A) and 3(B)  are graphs illustrating how output P out  and drain drive current I D  of the three-stage amplifier bias circuit varies due to variations among products; 
           [0030]      FIG. 4  is a principle diagram of the third stage bias circuit according to a first embodiment of the present invention; 
           [0031]      FIG. 5  is a block diagram of a high-power amplifier (HPA) to which the principle of the bias circuit according to the first embodiment of the present invention is applied; 
           [0032]      FIG. 6  is a principle diagram of the third stage bias circuit according to a second embodiment of the present invention; 
           [0033]      FIG. 7  is a graph illustrating magnitude of each term of the current I D  when a=0.9 in the second embodiment of the present invention; 
           [0034]      FIG. 8  is a graph illustrating magnitude of each term of the current I D  when a=0.99 in the second embodiment of the present invention; 
           [0035]      FIG. 9  is a block diagram of a high-power amplifier (HPA) to which the principle of the bias circuit according to the second embodiment of the present invention is applied; 
           [0036]      FIG. 10  is a principle diagram of the third stage bias circuit according to a third embodiment of the present invention; 
           [0037]      FIG. 11  is a block diagram of a high-power amplifier (HPA) to which the principle of a bias circuit according to the third embodiment of the present invention is applied; and 
           [0038]      FIG. 12  is a block diagram of a power amplifier according to a fourth embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0039]    Embodiments of the present invention will be described below, referring to the drawings. 
       First Embodiment 
       [0040]      FIG. 4  is a principle diagram of the third stage bias circuit according to a first embodiment of the present invention. In addition,  FIG. 5  is a block diagram of a high-power amplifier (HPA) to which the principle of the bias circuit according to the first embodiment of the present invention is applied. A first bias circuit  1  and a second bias circuit  2  are not shown here because they provide bias using a current mirror circuit in a conventional manner. Although internal configuration of the APC  4 - 1  is described in detail, the basic configuration thereof is that assumed in the conventional APC  4 . 
         [0041]    The bias circuit according to this embodiment includes a constant current source  101 , an amplifier  102 , a diode-connected FET  103 , a resistor  104 , a resistor  105 , a resistor  106 , and an FET  107 . 
         [0042]    The constant current source  101  plays the role of controlling the control bias current I cont  to a constant current. 
         [0043]    The FET  103  is coupled to the connection point between the constant current source  101  and the amplifier  102  in a branched manner. The FET  103 , which is diode-connected, has a purpose of drawing a certain amount of the current flowing in the amplifier  102 . The FET  103  and the resistor  104  determine the electric potential V 1  at the connection point between the constant current source  101  and the amplifier  102 . The electric potential at the connection point between the FET  103  and the resistor  104  is denoted as V G1 . 
         [0044]    The amplifier  102  includes a high-frequency power amplifier and peripheral circuits thereof, which amplify the signal that drew the current from the output of the constant current source  101  using the FET  103  or the like. The amplifier  102  is a linear amplifier. 
         [0045]    The resistors  105  and  106  divide the voltage of the output of the amplifier  102 . Based on the electric potential of the connection point between the resistors  105  and  106 , the gate terminal of the FET  107  is controlled. The resistors  105  and  106  have a function of attenuating high frequency signals. 
         [0046]    A buffer amplifier  10  having a threshold offset includes the amplifier  102 , the diode-connected FET  103 , the resistor  104 , the resistor  105 , and the resistor  106 . 
         [0047]    The FET  107  has an RF amplification function that amplifies and outputs high frequency signals that are input to the gate. 
         [0048]    Using the principle diagram, how the third stage bias circuit works will be explained. 
         [0049]    V G1  in the circuit can be calculated by the following equation. 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     
                       G 
                        
                       
                           
                       
                        
                       1 
                     
                   
                   = 
                   
                     
                       
                         
                           I 
                           cont 
                         
                         
                           β 
                           1 
                         
                       
                     
                     + 
                     
                       V 
                       th 
                     
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                      
                     
                         
                     
                      
                     1 
                   
                   ] 
                 
               
             
           
         
       
     
         [0050]    In the above expression, I cont  denotes the current value from the constant current source, and β 1  denotes the current drivability coefficient of the FET  103 . In addition, V th  denotes the threshold voltage (temperature-dependent) of the FET  103 . 
         [0051]    Calculation of V G1  also provides the electric potential V 1  at the connection point between the constant current source  101  and the amplifier  102 . 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     1 
                   
                   = 
                   
                     
                       R 
                       × 
                       
                         I 
                         cont 
                       
                     
                     + 
                     
                       
                         
                           I 
                           cont 
                         
                         
                           β 
                           1 
                         
                       
                     
                     + 
                     
                       V 
                       th 
                     
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                      
                     
                         
                     
                      
                     2 
                   
                   ] 
                 
               
             
           
         
       
     
         [0052]    Here, R denotes the resistance value of the resistor  104 . 
         [0053]    The value of V 1  is directly applied to the gate of the FET  107  by the buffer amplifier  10  (shown in  FIG. 5  because peripheral circuits are included) including the amplifier  102  and others. Because V th  can be ignored, it can be expressed as follows. 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
                           V 
                           amp 
                         
                         = 
                         
                           
                             
                               ( 
                               
                                 R 
                                 × 
                                 
                                   I 
                                   cont 
                                 
                               
                               ) 
                             
                             2 
                           
                           + 
                           
                             2 
                             × 
                             R 
                             × 
                             
                               I 
                               cont 
                             
                             × 
                             
                               
                                 
                                   I 
                                   cont 
                                 
                                 
                                   β 
                                   1 
                                 
                               
                             
                           
                           + 
                           
                             
                               I 
                               cont 
                             
                             
                               β 
                               1 
                             
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                         
                           
                             
                               R 
                               2 
                             
                             × 
                             
                               I 
                               cont 
                               2 
                             
                           
                           + 
                           
                             2 
                             × 
                             R 
                             × 
                             
                               I 
                               cont 
                               
                                 3 
                                 2 
                               
                             
                             × 
                             
                               1 
                               
                                 
                                   β 
                                   1 
                                 
                               
                             
                           
                           + 
                           
                             
                               I 
                               cont 
                             
                             
                               β 
                               1 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                      
                     
                         
                     
                      
                     3 
                   
                   ] 
                 
               
             
           
         
       
     
         [0054]    Based on the foregoing, I D  can be calculated from the current drivability coefficient β 2  of the FET  107  as follows. 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                     D 
                   
                   = 
                   
                     
                       
                         β 
                         2 
                       
                       × 
                       
                         R 
                         2 
                       
                       × 
                       
                         I 
                         cont 
                         2 
                       
                     
                     + 
                     
                       
                         
                           2 
                           × 
                           
                             β 
                             2 
                           
                           × 
                           R 
                         
                         
                           
                             β 
                             1 
                           
                         
                       
                       × 
                       
                         I 
                         cont 
                         
                           3 
                           2 
                         
                       
                     
                     + 
                     
                       
                         
                           β 
                           2 
                         
                         
                           β 
                           1 
                         
                       
                       × 
                       
                         I 
                         cont 
                       
                     
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                      
                     
                         
                     
                      
                     4 
                   
                   ] 
                 
               
             
           
         
       
     
         [0055]    The above-mentioned β 1  and β 2  can be calculated by the expression of a general current drivability coefficient. 
         [0000]    
       
         
           
             
               
                 
                   β 
                   = 
                   
                     
                       C 
                       ox 
                     
                      
                     μ 
                      
                     
                       W 
                       I 
                     
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                      
                     
                         
                     
                      
                     5 
                   
                   ] 
                 
               
             
           
         
       
     
         [0056]    Here, C ox  denotes the oxidized film capacitance per unit area, μ denotes the electron mobility speed, W denotes the gate width, and I denotes the gate length. 
         [0057]    Further discussion of (Equation 4) will be provided below. 
         [0058]    In (Equation 4), the first term (β 2 ×R 2 ×I cont   2 ) is the square-law characteristic. The second and third terms express undesired terms (undesired components). The undesired components become dominant over I D  when I cont  is small, in other words, immediately after start-up of the constant current source  101  of the third bias circuit  3 - 1 , which is not desired. 
         [0059]    The inventors conceived a method of excluding such undesired components from (Equation 4), and derived the present invention. That is, undesired components can be reduced by increasing the current drivability coefficient β 1  of the FET  103  (=increase the size of the FET  103 ) to increase the denominator of the second and the third terms. 
         [0060]    In other words, the current drivability coefficient β 1  is increased by increasing each parameter in the numerator of (Equation 5) in the FET  103 , and decreasing the gate length I which is a parameter in the denominator. Undesired components can be excluded thereby. 
         [0061]    The high-power amplifier (HPA) of  FIG. 5  directly uses the above principle. Note that there may be a case in the followings where description is provided with the configuration of the output terminal side of  FIG. 4  omitted. The matching circuit is omitted in the present drawing. 
         [0062]    The APC  4 - 1  supplies I cont  according to the above (Equation 4). As for this supply, a current mirror circuit  14  in the APC  4 - 1  plays the role of the constant current source  101 . As has been already described above, this HPA has its characteristic in the third bias circuit  3 - 1 . Additionally, the third bias circuit  3 - 1  includes, on as-is basis, the content of the principle diagram shown in  FIG. 4 . 
         [0063]    The steepness of the gain against the control voltage of the third bias circuit  3 - 1  can be suppressed thereby. An ideal bias circuit can be provided by increasing the current drivability coefficient β 1  of the FET  103  in this manner. 
       Second Embodiment 
       [0064]    A second embodiment of the present invention will be described next. 
         [0065]    The object of the first embodiment is to exclude undesired components of the bias circuit by increasing the current drivability coefficient β 1  of the FET  103  as described above. Attention has been paid on its feasibility by increasing each parameter in the numerator and decreasing the parameter in the denominator of (Equation 5). 
         [0066]    However, these parameters depend on the physical size of devices such as the gate width W or the gate length I. Difficulty in design exists in that characteristic of the bias circuit largely depends on the physical size of the device. 
         [0067]    Therefore, it is an object of the second embodiment to exclude undesired components of the bias circuit without depending on device size. 
         [0068]      FIG. 6  is a principle diagram of the third stage bias circuit according to the second embodiment of the present invention. This drawing differs from  FIG. 4  in that an adjustment circuit  201  is included. 
         [0069]    The adjustment circuit  201  draws current which is proportional to the input current from the current flowing in the diode-connected FET  103 . Accordingly, the adjustment circuit  201  is coupled to the connection point between the diode-connected FET  103  and the resistor  104  in a branched manner. 
         [0070]    A specific configuration of the adjustment circuit  201  will be described below. 
         [0071]    The ratio of the drawn current to be drawn by the adjustment circuit  201  from the input current flowing in the FET  103  is defined as a (0&lt;a&lt;1). 
         [0072]    First, operation of the third stage bias circuit will be explained using the principle diagram, similarly as the first embodiment. 
         [0073]    V G1  in this circuit can be calculated by the following equation. 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     
                       G 
                        
                       
                           
                       
                        
                       1 
                     
                   
                   = 
                   
                     
                       
                         
                           
                             ( 
                             
                               1 
                               - 
                               α 
                             
                             ) 
                           
                           × 
                           
                             I 
                             cont 
                           
                         
                         
                           β 
                           1 
                         
                       
                     
                     + 
                     
                       V 
                       th 
                     
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                      
                     
                         
                     
                      
                     6 
                   
                   ] 
                 
               
             
           
         
       
     
         [0074]    When V G1  is calculated, the electric potential V 1  at the connection point between the constant current source  101  and the amplifier  102  can also be calculated, as with the first embodiment. 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     1 
                   
                   = 
                   
                     
                       R 
                       × 
                       
                         I 
                         cont 
                       
                     
                     + 
                     
                       
                         
                           
                             ( 
                             
                               1 
                               - 
                               α 
                             
                             ) 
                           
                           × 
                           
                             I 
                             cont 
                           
                         
                         
                           β 
                           1 
                         
                       
                     
                     + 
                     
                       V 
                       th 
                     
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                      
                     
                         
                     
                      
                     7 
                   
                   ] 
                 
               
             
           
         
       
     
         [0075]    In this case, the voltage applied to the gate terminal of the FET  107  is given as follows. 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
                           V 
                           amp 
                         
                         = 
                           
                          
                         
                           
                             
                               R 
                               2 
                             
                             × 
                             
                               I 
                               cont 
                               2 
                             
                           
                           + 
                           
                             2 
                             × 
                             R 
                             × 
                             
                               I 
                               cont 
                             
                             × 
                             
                               
                                 
                                   
                                     ( 
                                     
                                       1 
                                       - 
                                       α 
                                     
                                     ) 
                                   
                                   × 
                                   
                                     I 
                                     cont 
                                   
                                 
                                 
                                   β 
                                   1 
                                 
                               
                             
                           
                           + 
                         
                       
                     
                   
                   
                     
                       
                           
                          
                         
                           
                             
                               ( 
                               
                                 1 
                                 - 
                                 α 
                               
                               ) 
                             
                             × 
                             
                               I 
                               cont 
                             
                           
                           
                             β 
                             1 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                          
                         
                           
                             
                               R 
                               2 
                             
                             × 
                             
                               I 
                               cont 
                               2 
                             
                           
                           + 
                           
                             
                               2 
                               × 
                               R 
                               × 
                               
                                 
                                   ( 
                                   
                                     1 
                                     - 
                                     α 
                                   
                                   ) 
                                 
                               
                               × 
                               
                                 I 
                                 cont 
                                 
                                   3 
                                   2 
                                 
                               
                             
                             
                               
                                 β 
                                 1 
                               
                             
                           
                           + 
                           
                             
                               
                                 ( 
                                 
                                   1 
                                   - 
                                   α 
                                 
                                 ) 
                               
                               × 
                               
                                 I 
                                 cont 
                               
                             
                             
                               β 
                               1 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                      
                     
                         
                     
                      
                     8 
                   
                   ] 
                 
               
             
           
         
       
     
         [0076]    Based on the foregoing, I D  can be calculated as follows from the current drivability coefficient β 2  of the FET  107 . 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                     D 
                   
                   = 
                   
                     
                       
                         R 
                         2 
                       
                       × 
                       
                         β 
                         2 
                       
                       × 
                       
                         I 
                         cont 
                         2 
                       
                     
                     + 
                     
                       
                         
                           2 
                           × 
                           
                             β 
                             2 
                           
                           × 
                           R 
                           × 
                           
                             
                               ( 
                               
                                 1 
                                 - 
                                 α 
                               
                               ) 
                             
                           
                         
                         
                           
                             β 
                             1 
                           
                         
                       
                       × 
                       
                         I 
                         cont 
                         
                           3 
                           2 
                         
                       
                     
                     + 
                     
                       
                         
                           
                             β 
                             2 
                           
                           × 
                           
                             ( 
                             
                               1 
                               - 
                               α 
                             
                             ) 
                           
                         
                         
                           β 
                           1 
                         
                       
                       × 
                       
                         I 
                         cont 
                       
                     
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                      
                     
                         
                     
                      
                     9 
                   
                   ] 
                 
               
             
           
         
       
     
         [0077]    Also in the second embodiment, the first term of the right side is the ideal component, whereas the second and the third terms are undesired components. 
         [0078]    Now attention should be paid to variation of the entire bias circuit caused by the value of a of the adjustment circuit  201 . 
         [0079]      FIG. 7  is a graph illustrating magnitude of each term of the current I D  when a=0.9 in the second embodiment of the present invention, and  FIG. 8  is a graph illustrating magnitude of each term of the current I D  when a=0.99. 
         [0080]    In each drawing, three parameters I, I error , and I D  are described. I denotes the ideal component of the first term of the right side of (Equation 9). I error  denotes the sum of the second and the third terms of the right side of the same equation. I D  denotes I D  of the left side of (Equation 9). 
         [0081]    The smaller the numerator of the second and the third terms of (Equation 9), the smaller undesired components of I D  become. Therefore, it is obvious from  FIGS. 7 and 8  that a more ideal situation (first term) is realized as a approaches “1”. 
         [0082]      FIG. 9  is a block diagram of a high-power amplifier (HPA) to which the principle of the bias circuit according to the second embodiment of the present invention is applied. 
         [0083]    Comparing the HPA of this embodiment with that of the first embodiment, the APC  4 - 2  and the third bias circuit  3 - 2  are different. 
         [0084]    The third bias circuit  3 - 2  has two input terminals (here, the amplifier  102  drive voltage supply terminal is excluded) so that aI cont , as well as I cont  from the constant current source  101  (included in the APC  4 - 2 ) can be input. 
         [0085]    The third bias circuit  3 - 2  has a current mirror circuit  11  that processes the input aI cont . Using the current mirror circuit  11 , aI cont  can be drawn from the current flowing in the FET  103 . 
         [0086]    Furthermore, increase of processing speed can be expected by adding a phase compensation capacity  41  to the gate terminal of the FET included in the current mirror circuit  11 . Responsiveness in the time axis actually required for a power amplifier can be secured thereby. 
         [0087]    The APC  4 - 2  differs from the APC  4 - 1  in that the former outputs aI cont . The method of defining a uses pMOSFET 21  and pMOSFET 22  in the APC  4 - 2 . The gate widths of these pMOSFETs are made completely the same. The ratio of current mirrors coupled below pMOSFET 31  in the same APC  4 - 2  is set to be 1:1. Accordingly, a=1 holds because the subtracted current becomes equal to I cont . This causes the current to stop flowing in the FET  103 , and therefore the value of a is determined by narrowing the gate width of the left pMOS by several percents, or setting the current mirror ratio to 1:0.95 or the like. 
         [0088]    Influence of undesired components of the bias circuit can thereby be excluded without depending on the physical size of the device. 
       Third Embodiment 
       [0089]    A third embodiment of the present invention will be described next. 
         [0090]    In the second embodiment, undesired components of I D  are excluded by drawing the current flowing in the FET  103  by the adjustment circuit  201 . 
         [0091]    In contrast, undesired components are made constant in the third embodiment of the present invention by further drawing an offset current from the adjustment circuit  201 . It is an object to realize a more ideal square-law characteristic thereby. 
         [0092]      FIG. 10  is a principle diagram of the third stage bias circuit according to the third embodiment of the present invention. This drawing differs from  FIG. 6  in that the adjustment circuit  201  is replaced by an adjustment circuit  301 . 
         [0093]    The adjustment circuit  301  differs from the adjustment circuit  201  in that the input current and the drawn current are not controlled by the ratio, but by drawing current by a value obtained by subtracting a fixed offset value I offset  from I cont . 
         [0094]    Operation of the third stage bias circuit will be explained using this principle diagram. 
         [0095]    V G1  in the circuit can be calculated by the following equation. 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     
                       G 
                        
                       
                           
                       
                        
                       1 
                     
                   
                   = 
                   
                     
                       
                         
                           
                             
                               I 
                               cont 
                             
                             - 
                             
                               ( 
                               
                                 
                                   I 
                                   cont 
                                 
                                 - 
                                 
                                   I 
                                   offset 
                                 
                               
                               ) 
                             
                           
                           
                             β 
                             1 
                           
                         
                       
                       + 
                       
                         V 
                         th 
                       
                     
                     = 
                     
                       
                         
                           
                             I 
                             offset 
                           
                           
                             β 
                             1 
                           
                         
                       
                       + 
                       
                         V 
                         th 
                       
                     
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                      
                     
                         
                     
                      
                     10 
                   
                   ] 
                 
               
             
           
         
       
     
         [0096]    The electrical potential V 1  at the connection point between the constant current source  101  and the amplifier  102  can also be calculated from this. 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     1 
                   
                   = 
                   
                     
                       R 
                       × 
                       
                         I 
                         cont 
                       
                     
                     + 
                     
                       
                         
                           I 
                           offset 
                         
                         
                           β 
                           1 
                         
                       
                     
                     + 
                     
                       V 
                       th 
                     
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                      
                     
                         
                     
                      
                     11 
                   
                   ] 
                 
               
             
           
         
       
     
         [0097]    The voltage applied to the gate terminal of the FET  107  can be similarly calculated. 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
                           V 
                           amp 
                         
                         = 
                           
                          
                         
                           
                             
                               R 
                               2 
                             
                             × 
                             
                               I 
                               cont 
                               2 
                             
                           
                           + 
                           
                             2 
                             × 
                             R 
                             × 
                             
                               I 
                               cont 
                             
                             × 
                             
                               
                                 
                                   I 
                                   offset 
                                 
                                 
                                   β 
                                   1 
                                 
                               
                             
                           
                           + 
                           
                             
                               I 
                               offset 
                             
                             
                               β 
                               1 
                             
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                          
                         
                           
                             
                               R 
                               2 
                             
                             × 
                             
                               I 
                               cont 
                               2 
                             
                           
                           + 
                           
                             2 
                             × 
                             R 
                             × 
                             
                               
                                 
                                   I 
                                   cont 
                                 
                                 × 
                                 
                                   
                                     I 
                                     offset 
                                   
                                 
                               
                               
                                 
                                   β 
                                   1 
                                 
                               
                             
                           
                           + 
                           
                             
                               I 
                               offset 
                             
                             
                               β 
                               1 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                      
                     
                         
                     
                      
                     12 
                   
                   ] 
                 
               
             
           
         
       
     
         [0098]    I D  can be calculated from (Equation 12) and the current drivability coefficient β 2  of the FET  107  as follows. 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                     D 
                   
                   = 
                   
                     
                       
                         R 
                         2 
                       
                       × 
                       
                         β 
                         2 
                       
                       × 
                       
                         I 
                         cont 
                         2 
                       
                     
                     + 
                     
                       2 
                       × 
                       R 
                       × 
                       
                         β 
                         2 
                       
                       × 
                       
                         
                           
                             I 
                             cont 
                           
                           × 
                           
                             
                               I 
                               offset 
                             
                           
                         
                         
                           
                             β 
                             1 
                           
                         
                       
                     
                     + 
                     
                       
                         
                           β 
                           2 
                         
                         
                           β 
                           1 
                         
                       
                       × 
                       
                         I 
                         offset 
                       
                     
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                      
                     
                         
                     
                      
                     13 
                   
                   ] 
                 
               
             
           
         
       
     
         [0099]    As can be seen, although influence of the second term cannot be completely excluded because I cont  remains, influence of the second term can be minimized by the setting of I offset , and influence of the third term can also be handled. Handling of I offset  during the control improves significantly because I offset  is a constant. 
         [0100]    Now we consider how to implement this processing in the circuit. 
         [0101]      FIG. 11  is a block diagram of a high-power amplifier (HPA) to which the principle of the bias circuit according to the third embodiment of the present invention is applied. 
         [0102]    The APC  4 - 3  and the third bias circuit  3 - 3  are different in this embodiment. Addition of a constant current source  5  is also characteristic. 
         [0103]    The constant current source  5  plays the role of generating I Offset  that appears in the above (Equation 10) to (Equation 13). 
         [0104]    The third bias circuit  3 - 3  includes current mirror circuits  12  and  13  in order to realize the principle of  FIG. 10 . 
         [0105]    In the current mirror circuit  12 , I Offset  from the constant current source  5  is input to the constant current source side (where the gate and the drain are connected) of the current mirror circuit. Because the current of the other terminal (output terminal) is set to I Offset  by the current mirror circuit  12 , input of the current mirror circuit  13  can be reduced. 
         [0106]    I cont  generated in the APC  4 - 3  is input to the input terminal of the constant current source side (where the gate and the drain are coupled) of the current mirror circuit  13 . The terminal at the output side of the current mirror circuit  12  is also coupled to the connection terminal to which I cont  is input. Accordingly, the effective current that is input to the current mirror circuit  13  is given by I cont −I offset . Therefore, the current mirror circuit  13  can draw the current of I cont −I Offset  from a signal connected to the output terminal. 
         [0107]    (I cont −I Offset ) in the square root of (Equation 10) can thereby be generated so that this embodiment can be implemented. 
       Fourth Embodiment 
       [0108]    Finally, a case that applies the HPA according to the above-mentioned embodiment to a cellular phone will be described. 
         [0109]      FIG. 12  is a block diagram of a power amplifier according to a fourth embodiment of the present invention. 
         [0110]    The present power amplifier module is provided with two power amplifiers, namely, a Low Band in the 1 GHz band and a High Band in the 2 GHz band. In the drawing, the input terminal of the Low Band is TXin-Low Band, and the input terminal of the High Band is TXin-High Band. In addition, the High Band and the Low Band respectively have, within the antenna switch circuit, an LPF (Low Pass Filter) that removes the high harmonics, a switch that switches transmission and reception, and a diplexer circuit that integrates the signals of both the High Band and the Low Band. 
         [0111]    The input provided to these terminals is first amplified by one of the above HPAs including the first bias circuit  1 , the second bias circuit  2 , and the third bias circuit  3 . After amplification by the HPA, the input can be fed back to the control voltage V apc  of the power amplifier via a coupler  6 , a detector circuit  50 , and an error amplifier  51  to accurately output power to the output control voltage V ramp . 
         [0112]    Although the detector circuit  50  and the error amplifier  51  are illustrated to process both the Low Band and the High Band collectively, there is no problem with dividing the process into two. Accordingly, two inputs may be provided for the output control voltage V ramp  of the High Band and the output control voltage V ramp  of the Low Band. 
         [0113]    The HPA according to the present invention can thus be applied to a power amplifier. 
         [0114]    Although the invention made by the inventors has been specifically described based on its embodiments, the present invention is not limited to the foregoing embodiments and it is needless to say that a variety of modification is possible without deviating from its spirit. 
         [0115]    The present invention is expected to be applied to power amplifiers for portable information terminals. It is particularly expected that, through application of the present invention, a preferable bias circuit is provided to a power amplifier for GSM that controls the output using control voltage. 
         [0116]    However, application of bias circuits of the embodiments for purposes other than those described above is not prohibited. In addition, although it has been assumed in the foregoing description to serially-connect bias circuits in three stages, there is no problem with using a single bias circuit alone. There is also no problem with serially-connecting bias circuits in more stages.