Abstract:
A field effect transistor and a method of fabricating the field effect transistor. The field effect transistor includes: a silicon body, a perimeter of the silicon body abutting a dielectric isolation; a source and a drain formed in the body and on opposite sides of a channel formed in the body; and a gate dielectric layer between the body and an electrically conductive gate electrode, a bottom surface of the gate dielectric layer in direct physical contact with a top surface of the body and a bottom surface the gate electrode in direct physical contact with a top surface of the gate dielectric layer, the gate electrode having a first region having a first thickness and a second region having a second thickness, the first region extending along the top surface of the gate dielectric layer over the channel region, the second thickness greater than the first thickness.

Description:
[0001]    This application is a division of copending U.S. patent application Ser. No. 11/549,311 filed on Oct. 13, 2006. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The present invention relates to the field of semiconductor devices; more specifically, it relates to a field effect transistor having a thin gate electrode and a method for fabricating the field effect transistor. 
       BACKGROUND OF THE INVENTION 
       [0003]    As the field effect transistors (FETs) used in integrated circuits become ever smaller, it has been found that many parameters do not decrease (or scale) as the physical dimensions of the FET decrease. One of these parameters is the fringe capacitance between the source/drains of the FET and the gate electrode. As capacitance increases, FETs slow down. Since fringe capacitance does not scale, smaller FETs do not exhibit as much increase in speed as expected. Thus, to achieve continuing performance gain with decreasing FET dimensions there is a need for FET structures having reduced fringe capacitance. 
       SUMMARY OF THE INVENTION 
       [0004]    A first aspect of the present invention is a field effect transistor, comprising: a silicon body, a perimeter of the silicon body abutting a dielectric isolation; a source and a drain formed in the body and on opposite sides of a channel formed in the body; and a gate dielectric layer between the body and an electrically conductive gate electrode, a bottom surface of the gate dielectric layer in direct physical contact with a top surface of the body and a bottom surface the gate electrode in direct physical contact with a top surface of the gate dielectric layer, the gate electrode having a first region having a first thickness and a second region having a second thickness, the first region extending along the top surface of the gate dielectric layer over the channel region, the second thickness greater than the first thickness. 
         [0005]    A second aspect of the present invention is a method of fabricating a field effect transistor, comprising: forming a dielectric isolation along a perimeter of a region of a silicon layer to define a silicon body in the silicon layer; forming a gate dielectric layer in direct physical contact with a top surface of the silicon body; forming a gate dielectric layer on the silicon body, a bottom surface of the gate dielectric layer in direct physical contact with a top surface of the silicon body; and forming an electrically conductive gate electrode on the gate dielectric layer, bottom surface of the gate electrode in direct physical contact with a top surface of the gate dielectric layer, the gate electrode having a first region having a first thickness and a second region having a second thickness, the first region extending along the top surface of the gate dielectric layer over the channel region, the second thickness greater than the first thickness. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0006]    The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
           [0007]      FIGS. 1 through 7  are cross-sectional drawings illustrating fabrication of an FET according to a first embodiment of the present invention. 
           [0008]      FIG. 8A  is a cross-section through line  8 A- 8 A of  FIG. 8B  which is a top view of the FET of  FIGS. 1 through 7  after a further fabrication step; 
           [0009]      FIG. 9A  is a top view and  FIG. 9B  is a cross-section through line  9 B- 9 B of  FIG. 9A  of first alternative layout of an FET according to the first embodiment of the present invention; 
           [0010]      FIG. 10A  is a top view and  FIG. 10B  is a cross-section through line  10 B- 10 B of  FIG. 10A  of second alternative layout of an FET according to the first embodiment of the present invention; 
           [0011]      FIGS. 11 through 13  are cross-sectional drawings illustrating fabrication of an FET according to a second embodiment of the present invention; and 
           [0012]      FIG. 14A  is a cross-section through line  14 A- 14 A of  FIG. 14B , which is a top view of the FET of  FIGS. 11 through 13  after a further fabrication step. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0013]    All etch steps described infra, unless otherwise noted, may be performed using a reactive ion retch (RIE) process. 
         [0014]      FIGS. 1 through 7  are cross-sectional drawings illustrating fabrication of an FET according to a first embodiment of the present invention. In  FIG. 1 , a silicon-on-insulator (SOI) substrate includes a lower silicon layer  105 , a single-crystal upper silicon layer  110  and a buried oxide layer (BOX)  115  between the upper and lower silicon layers. Formed in upper silicon layer  110  is a shallow trench isolation  120  surrounding a single-crystal silicon body region  125 . Formed on a top surface SOI substrate  100  is a gate dielectric layer  130 . Formed on a top surface of gate dielectric layer  130  is a polysilicon layer  135 . 
         [0015]    Polysilicon layer  135  has a thickness of T 1 . In one example T 1  is between about 20 nm and about 100 nm. In one example gate dielectric layer  130  is silicon dioxide (Oxidized silicon), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO Y N X ) or combinations of layers thereof. In one example, gate dielectric layer  130  is a high K (dielectric constant) material, examples of which include, but are not limited to, metal oxides such as Ta 2 O 5 , BaTiO 3 , HfO 2 , ZrO 2 , Al 2 O 3 , or metal silicates such as HfSi x O y  or HfSi x O y N z  or combinations of layers thereof. A high K dielectric material has a relative permittivity above about 10. In one example, gate dielectric layer  130  is about 0.5 nm to 20 nm thick. 
         [0016]    In  FIG. 2 , a hardmask layer  140  is formed on top surface  145  of polysilicon layer  135  and an opening  150  formed in the hardmask layer exposing the top surface of the polysilicon layer. In one example, hardmask layer  140  is Si 3 N 4 . 
         [0017]    In  FIG. 3 , an oxidation of silicon layer  135  is performed to form a Oxidized silicon region  155  in opening  150 . The oxidation is controlled so as not consume all the polysilicon in opening  150 , but leave a thin polysilicon layer  160  over gate dielectric layer  130 . In one example T 2  is less than or equal to about 50 nm. In one example, T 2  is less than or equal to about 30 nm. 
         [0018]    In  FIG. 4 , polysilicon layer  135  (see  FIG. 3 ) and dielectric layer  140  are masked (using conventional photolithography to form a patterned photoresist mask) and then polysilicon layer  135  and dielectric layer  140 , but not gate dielectric layer  130 , are etched where not protected by the photoresist mask to define a first gate electrode precursor structure  166  comprising a thick polysilicon region  165 , thin polysilicon layer  160  and Oxidized silicon region  155 . Gate electrode precursor structure  166  that will define the lateral extents of the gate electrode of the FET being fabricated. A lateral direction is any direction parallel to top surface  150 . Thin polysilicon layer  160  completely overlaps STI  120  over a first pair of opposite sidewalls (sidewalls  167 A and  167 B) of body  125  but does not completely overlap STI  120  over a second pair of opposite sidewalls of body  125  (not shown in  FIG. 4 ). The first and second pairs of sidewalls are mutually perpendicular. Between each sidewall of the second pair of sidewalls and corresponding opposite sides of thin polysilicon layer  160  exist regions of body  125  not covered by thin polysilicon layer  160  and Oxidized silicon region  155 . It is in these regions of body  125  that the source/drains of the FET being fabricated will be formed. 
         [0019]    After the masking and etching, the photoresist mask is removed and spacers  170  are formed on the sidewalls of first gate electrode precursor structure  166  and source/drain ion implantations performed into regions of body  125  not protected by spacers  170 , or first gate electrode precursor structure  166 . Spacers  170  may be formed by deposition of a conformal material flowed by a directional RIE process. Spacers  170  consist of a dielectric material. Spacers  170  may comprise multiple independently formed spacers and multiple source/drain ion implantation steps may be performed, including source/drain extension implants and halo implants as commonly known in the art. 
         [0020]    Next, regions of gate dielectric layer  130  not protected by spacers  170  or first gate electrode precursor structure  166  are removed and a metal silicide layer formed on the source drains. In one example, the silicide layer comprises Pt, Ti, Co or Ni silicide. Metal silicides may be formed, by blanket deposition of a thin metal layer followed by heating to a temperature sufficient to cause a chemical reaction between the metal and any silicon layer in contact with the metal, followed by RIE or wet etching to remove any unreacted metal. 
         [0021]    In  FIG. 5 , a dielectric layer  175  is formed over spacers  175 , first gate electrode precursor structure  166  and exposed regions of substrate  100  and STI  120 . Then a chemical-mechanical-polish (CMP) is performed to expose first gate electrode precursor structure  166  using hardmask layer  140  (see  FIG. 4 ) as a polish stop. Next any remaining hardmask layer  140  is removed, by RIE or wet etching. In one example dielectric layer  175  comprises silicon dioxide (Oxidized silicon), silicon nitride (Si 3 N 4 ), silicon carbide (SiC), silicon oxy nitride (SiON), silicon oxy carbide (SiOC), organosilicate glass (SiCOH), plasma-enhanced silicon nitride (PSiN x ) or NBLok (SiC(N,H)) or combinations of layers thereof. 
         [0022]    In  FIG. 6 , Oxidized silicon region  155  (see  FIG. 5 ) is removed by RIE or wet etching to form a second gate electrode precursor structure  176  comprising thick polysilicon region  165  and thin polysilicon layer  160 . 
         [0023]    In  FIG. 7 , a gate electrode  177  is formed. Gate electrode  177  comprises a continuous metal silicide layer  180  and thick polysilicon region  165 . Thin polysilicon layer  160  (see  FIG. 6 ) has been totally consumed by the metal silicide formation process. A thin gate electrode region  178  of gate electrode  177  comprises a first region of metal silicide layer  180  in direct physical contact with gate dielectric layer  130  over body  125 . A raised gate electrode region  179  of gate electrode  177  comprises a second region of metal silicide layer  180  in direct contact with thick polysilicon region  165 . In one example, silicide layer  180  comprises Pt, Ti, Co or Ni silicide. Raised contact region  179  provides a surface higher than thin gate electrode region  178  (relative to the top surface of gate dielectric layer  130 ) in order to land a gate contact as illustrated in  FIG. 8A  and described infra. This prevents breakthrough of the gate contact into gate dielectric layer  130 . 
         [0024]    Silicide layer  180  and thus thin gate electrode region  178  of gate electrode  177  has a thickness of T 3  and raised gate electrode region  179  of gate electrode  177  has a thickness T 4 . In one example T 3  is less than or equal to about 40 nm. In one example, T 3  is less than or equal to about 20 nm. T 4  is always greater than T 3 . In one example T 4  is greater than or equal to about twice T 3 . Except for gate and source drain contacts; fabrication of an FET  182  is essentially complete. 
         [0025]      FIG. 8A  is a cross-section through line  8 A- 8 A of  FIG. 8B , which is a top view of the FET of  FIGS. 1 through 7  after a further fabrication step. In  FIG. 8A , a dielectric layer  185  is formed over dielectric layer  175  and FET  182  and a CMP performed to planarize dielectric layer  175 . In one example gate dielectric layer  175  comprises Oxidized silicon, Si 3 N 4 , SiO Y N X , a low K (dielectric constant) material, examples of which include but are not limited to hydrogen silsesquioxane polymer (HSQ), methyl silsesquioxane polymer (MSQ), SiLK™ (polyphenylene oligomer) manufactured by Dow Chemical, Midland, Tex., Black Diamond™ (methyl doped silica or SiO x (CH 3 ) y  or SiC x O y H y  or SiOCH) manufactured by Applied Materials, Santa Clara, Calif., organosilicate glass (SiCOH), and porous SiCOH and combinations of layers thereof. A low K dielectric material has a relative permittivity of about 2.4 or less. In one example, dielectric layer  175  is between about 300 nm and about 2,000 nm thick. 
         [0026]    Next an electrically conductive gate contact  190 A is formed from a top surface of dielectric layer down to at least metal silicide layer  180  over thick polysilicon region  165 , for example, by a damascene process. In one example, contact  190 A comprises W, Ta, tantalum nitride (TaN), Ti, titanium nitride (TiN) or combinations of layers thereof. Gate contact  190 A may extend into or through metal silicide layer  180  into thick polysilicon layer  165 . Advantageously, there is no gate contact to thin gate electrode region  178 , only a gate contact to raised gate electrode region  179 . In  FIG. 8B , dielectric layers  175  and  185  are omitted for clarity. In  FIG. 8B , source/drains  195 A and  195 B are formed on either side of gate electrode  177  and contacts  190 A and  190 B (similar to contact  190 A) are formed to source/drains  195 A and  195 B. FET  182  thus fabricated has a gate channel length L G  defined by the width of gate electrode  177  between source/drains  195 A and  195 B. There is also a physical channel length L PHYSICAL  that is defined as the distance between source/drains  195 A and  195 B. L G  is greater than or equal to L PHYSICAL  and depends upon how far source/drains  195 A and  195 B extend under gate electrode  177 . In one example, (referring back to  FIG. 7 ) T 3  divided by L G  is less than or equal to 1. In one example, L G  is equal to or greater than about 4 times T 3 . In one example, (referring back to  FIG. 7 ) T 3  divided by L PHYSICAL  is less than or equal to 1. In one example, L PHYSICAL  is equal to or greater than about 4 times T 3 . 
         [0027]    In  FIGS. 8A and 8B , raised gate electrode region  179  is completely formed over STI  120  and no portion of raised gate electrode region  179  overlaps body  125 . Only thin gate electrode region  178  extends over body  125 . The fringe capacitance is thus reduced because of thinness of thin gate electrode region  178  over body  125  of FET  182  compared to conventional FETs where a thick polysilicon layer would extend out over the silicon body of the conventional FET. 
         [0028]      FIG. 9A  is a top view and  FIG. 9B  is a cross-section through line  9 B- 9 B of  FIG. 9A  of first alternative layout of an FET according to the first embodiment of the present invention.  FIG. 9A  is similar to  FIG. 8B  and  FIG. 9B  is similar to  FIG. 8A  except that a region of raised gate electrode region  179  of an FET  182 A overlaps STI  120  and body  125 . This still results in reduced fringe capacitance compared to a conventional FET and allows a reduction is area of FET  182 A compared to FET  182  of  FIGS. 8A and 8B . 
         [0029]      FIG. 10A  is a top view and  FIG. 10B  is a cross-section through line  10 B- 10 B of  FIG. 10A  of second alternative layout of an FET according to the first embodiment of the present invention.  FIG. 10A  is similar to  FIG. 8B  and  FIG. 10B  is similar to  FIG. 8A  except that raised gate electrode region  179  of an FET  182 B is formed completely over body  125 . This still results in reduced fringe capacitance compared to a conventional FET and allows a reduction is area of FET  182 B compared to FET  182  of  FIGS. 8A and 8B  and FET  182 A of  FIGS. 9A and 9B . 
         [0030]      FIGS. 11 through 13  are cross-sectional drawings illustrating fabrication of an FET according to a second embodiment of the present invention.  FIG. 11  is similar to  FIG. 1  except polysilicon layer  135  of  FIG. 1  is replaced with a metal layer  200  having a thickness T 5 . In one example, metal layer  200  comprises Al, Ti, W, Ta, TiN, TaN or 
         [0031]    In  FIG. 12 , a mask  205  is formed on top surface  215  of metal layer  200  and a trench  215  partially etched into the metal layer. A thus thinned region  220  of metal layer  200  has a thickness T 6 . Mask  205  may be a patterned photoresist layer formed by conventional photolithographic techniques well know in the art or may be a patterned hardmask layer formed by conventional photolithographic and etching techniques well know in the art 
         [0032]    Referring to  FIGS. 11 and 12 , in one example T 5  is less than or equal to about 40 nm. In one example, T 6  is less than or equal to about 20 nm. T 5  is always greater than T 6 . In one example T 5  is greater than or equal to about twice T 6 . 
         [0033]    In  FIG. 13 , mask  205  of  FIG. 11  is removed, a blanket dielectric layer deposited over metal layer  200 , the blanket dielectric layer is masked (using conventional photolithography to form a patterned photoresist mask) and then the blanket dielectric layer and gate dielectric layer  130  are etched, where not protected by the photoresist mask, to define a gate electrode precursor structure  225  comprising a thick metal region  230 , a thin metal region  235  and a dielectric mask  240 . Gate electrode precursor structure  225  will define the lateral extents of the gate electrode of the FET being fabricated. Thin metal region  235  completely overlaps STI  120  over a first pair of opposite sidewalls (sidewalls  167 A and  167 B) of body  125  but does not completely overlap STI  120  over a second pair of opposite sidewalls of body  125  (not shown in  FIG. 13 ). The first and second pairs of sidewalls are mutually perpendicular. Between each sidewall of the second pair of sidewalls and corresponding opposite sides of thin metal region  235  exist regions of body  125  are not covered by thin metal region  235  and dielectric layer  240 . It is in these regions the source/drains of the FET being fabricated will be formed. 
         [0034]    Next, source/drains are formed and metal silicide layers formed on the source/drains as described supra. Formation of sidewall spacers is optional. 
         [0035]      FIG. 14A  is a cross-section through line  14 A- 14 A of  FIG. 14B , which is a top view of the FET of  FIGS. 11 through 13  after a further fabrication step. In  FIG. 14B , dielectric layers  175  and  185  are omitted for clarity. In  FIGS. 14A and 14B  dielectric layer  240  (see  FIG. 13 ) has been removed to form a gate electrode  245  comprising thick metal region  230  and thin metal region  235 . Dielectric layers  175  and  185  have been formed as well as contacts  190 A,  190 B and  190 C to form a FET  250 . 
         [0036]    FET  250  thus fabricated has a gate channel length L GM  defined by the width of gate electrode  245  between source/drains  195 A and  195 B. There is also a physical channel length L PHYSICAL  that has been described supra. L GM  is greater than or equal to L PHYSICAL  and depends upon how far source/drains  195 A and  195 B extend under gate electrode  245 . In one example, (referring back to  FIGS. 11 and 12 ) T 5  divided by L GM  is less than or equal to 1. In one example, L GM  is equal to or greater than about 4 times T 5 . In one example, (referring back to  FIGS. 11 and 12 ) T 5  divided by L PHYSICAL  is less than or equal to 1. In one example, L PHYSICAL  is equal to or greater than about 4 times T 5 . 
         [0037]    The alternatives layouts illustrated in  FIGS. 9A ,  9 B,  10 A and  10 B for the first embodiment of the present invention are equally applicable to the second embodiment of the present invention. 
         [0038]    Thus, the embodiments of the present invention provide FET structures having reduced fringe capacitance. 
         [0039]    The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.