Abstract:
A PLL device of a core logic chip includes a controlled delay circuit having a plurality of controlled delay lines interconnected in series and outputting therefrom a plurality of output clock signals in response to a reference clock signal; a phase detector for generating an adjusting signal according to a phase difference between the reference clock signal and the output clock signals; and a control circuit for asserting a plurality of control signals to the controlled delay lines, respectively, according to the adjusting signal in order to have the delay times of the output clock signals independently adjusted and outputted again by the controlled delay lines. The delay times of the output clock signals can be determined according to a distribution table and further tuned according to a circuitry and a layout of the core logic chip.

Description:
FIELD OF THE INVENTION 
   The present invention relates to a delay phase-locked loop (PLL) device and a clock signal generating method for use in a core logic chip. 
   BACKGROUND OF THE INVENTION 
   In a personal computer structure, in addition to the central unit processor (CPU), the core logic chip and the memory module have most effect on the data-processing performance. Please refer to  FIG. 1A  which is a schematic circuit block diagram showing the connection of a core logic chip and a memory module. With a double-date-rate (DDR) transmission specification, when the core logic chip  10  transmits a parallel data to the memory module  11 , a strobe signal and a parallel data signal TX_D are transmitted to the memory module  11  simultaneously for facilitating the memory module  11  to read the data. The associated signals described as above is shown in  FIG. 1B . Ideally, the rising edge or falling edge of each strobe signal is positioned right in the middle of a data bit of the parallel data signal TX_D, thereby assuring of correct data transmission. 
   In general, four output clock signals P 0 , P 1 , P 2  and P 3  with a phase difference of 90 degrees between every two adjacent signals, as shown in  FIG. 2A , are required. A delay phase-locked loop (PLL) device can be used to achieve this purpose. Referring to  FIG. 2B , the delay PLL device includes a controlled delay circuit  21 , a phase detector  22  and a control circuit  23 . The controlled delay circuit  21  consists of four delay lines  211 ,  212 ,  213  and  214 , each of which comprises a plurality of delay units (not shown). A reference clock signal CLK is transmitted through and processed by the four controlled delay lines  211 ,  212 ,  213  and  214  to generate the four output clock signals P 0 , P 1 , P 2  and P 3 . The four output clock signals have the phase difference of 90 degrees to each other. In order to keep in phase with the reference clock signal CLK, the output clock signal P 0  is transmitted to the phase detector  22  along with the reference clock signal CLK. If the phase detector  22  detects an earlier phase of the reference clock signal CLK than the output clock signal P 0 , a counting-down adjusting signal is asserted. On the contrary, i.e. the phase of the reference clock signal CLK is later than that of the output clock signal P 0 , a counting-up adjusting signal is asserted. Once either of the adjusting signals is transmitted to the control circuit  23 , a counted value CNT will be outputted to each of the controlled delay lines  211 ,  212 ,  213  and  214  by the control circuit  23  in response to the adjusting signal. The counted value represents the involving number n of delay units for each delay line. In other words, the delay time in each delay line can be controlled according to the counted value CNT. 
   For example, in the case that the phase of the reference clock signal CLK is earlier than that of the output clock signal P 0 , it means that the delay period effected by the controlled delay circuit  21  is too long. Thus the phase detector  22  asserts the counting-down adjusting signal, and the control circuit  23  outputs a counted value CNT=n−1 rather than CNT=n. In response to the reduced counted value, the delay period of each controlled delay line is simultaneously shortened, thereby adjusting the phase of the output clock signal. 
   The phases of the four output clock signals P 0 , P 1 , P 2  and P 3  are assured to be evenly distributed by 90-degree partition because the four controlled delay lines are imparted to the same counted value. Unfortunately, this will result in insufficient accuracy of signal delay because the phases are always adjusted by four delay units at one time. The insufficient accuracy may deteriorate the performance of the circuit particularly when the transmission rate is getting higher and higher. Further, in spite the parallel data signal TX_D initially generated by the source  101  according to the prior art is substantially perfect, the signals may be skewed or interfered to some extent when they have been outputted from the source  101  and forwarded to the I/O pad  102  via various transmission paths. Therefore, the strobe signal and parallel data signal outputted by the I/O pad  102  may have waveforms as shown in  FIG. 2C  rather than those shown  FIG. 1B . That is, the rising edge and falling edge of the strobe signal may deviate from the middle position of the parallel data signal TX_D. Accordingly, errors may happen for the memory module  11  to receive data. This problem may be even serious when the transmission rate is getting higher and higher. 
   SUMMARY OF THE INVENTION 
   A first aspect of the present invention relates to a delay phase-locked loop (PLL) device for generating a plurality of output clock signals with different phases in response to a reference clock signal. The delay PLL device includes a controlled delay circuit including a plurality of controlled delay lines interconnected in series and outputting therefrom a plurality of output clock signals; a phase detector electrically connected to an output end of the controlled delay circuit, and generating an adjusting signal according to a phase relation between the reference clock signal and one of the output clock signals; and a control circuit electrically connected to the phase detector and the controlled delay lines, and asserting a plurality of control signals to the controlled delay lines, respectively, in response to the adjusting signal in order to have the delay time of the output clock signals independently adjusted and outputted again by the controlled delay lines. 
   A second aspect of the present invention relates to a delay phase-locked loop (PLL) device for use in a core logic chip. The delay PLL device includes a controlled delay circuit including a plurality of controlled delay lines interconnected in series and outputting therefrom a plurality of output clock signals in response to a reference clock signal; a phase detector electrically connected to an output end of the controlled delay circuit, and generating an adjusting signal according to a phase relation between the reference clock signal and one of the output clock signals; and a control circuit electrically connected to the phase detector and the controlled delay lines, and asserting a plurality of control signals to the controlled delay lines, respectively, in response to the adjusting signal in order to have the delay time of the output clock signals independently adjusted and outputted again by the controlled delay lines. 
   A third aspect of the present invention relates to a clock signal generating method. The method comprises steps of: receiving a reference clock signal; phase-delaying the reference clock signal to obtain a plurality of output clock signals with different phases; generating an adjusting signal according to a phase relation between the reference clock signal and one of the output clock signals with different phases; and independently adjusting the delay time of the output clock signals and outputting the adjusted output clock signals. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention may best be understood through the following description with reference to the accompanying drawings, in which: 
       FIG. 1A  is a schematic circuit block diagram showing the connection of a core logic chip and a memory module; 
       FIG. 1B  is a schematic waveform diagram of strobe signal and TX_D signal according to double-data-rate (DDR) transmission specification; 
       FIG. 2A  is a schematic waveform diagram showing four output clock signals with a phase difference of 90 degrees between every two adjacent output clock signals; 
       FIG. 2B  is a schematic circuit block diagram showing a conventional delay PLL device; 
       FIG. 2C  is a schematic waveform diagram of strobe signal and TX_D signal according to double-date-rate (DDR) transmission specification by using a conventional method; 
       FIG. 3  is a schematic circuit block diagram showing a preferred embodiment of delay PLL device according to the present invention; and 
       FIG. 4  is a table for use in a clock signal generating method according to an embodiment of the present invention; 
       FIG. 5A  is a schematic diagram of a logic circuit for generating SEL-data and SEL-strobe signals; 
       FIG. 5B  is a schematic waveform diagram showing signals associated with the present invention; and 
       FIGS. 6A˜6C  are three examples for illustrating the clock signal generating method of the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
   The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only; it is not intended to be exhaustive or to be limited to the precise form disclosed. 
   Please refer to  FIG. 3 , which is a schematic circuit block diagram showing a preferred embodiment of delay PLL device according to the present invention. The delay PLL device includes a controlled delay circuit  31 , a phase detector  32  and a control circuit  33 . The controlled delay circuit  31  consists of four delay lines  311 ,  312 ,  313  and  314 , each of which comprises a plurality of delay units (not shown). A reference clock signal CLK is transmitted through and processed by the four controlled delay lines  311 ,  312 ,  313  and  314  to generate the four output clock signals P 1 , P 2 , P 3  and P 0 . In order to keep in phase with the reference clock signal CLK, the output clock signal P 0  is transmitted to the phase detector  32  along with the reference clock signal CLK. If the phase detector  32  detects an earlier phase of the reference clock signal CLK than the output clock signal P 0 , a counting-down adjusting signal is asserted. On the contrary, i.e. the phase of the reference clock signal CLK is later than that of the output clock signal P 0 , a counting-up adjusting signal is asserted. 
   In response to the adjusting signal from the phase detector  32 , the control circuit  33  outputs four counted values CNT 0 , CNT 1 , CNT 2  and CNT 3  to corresponding controlled delay lines  311 ,  312 ,  313  and  314  according to a distribution table. The counted values represent the involving numbers of delay units in the delay lines, respectively. 
   Please refer to  FIG. 4  which illustrates an example of the distribution table. For example, when the total number of delay units required for delaying a reference clock signal by one cycle is indicated by a positive integer “m”, where m=4n, it is apparent that all the counted values CNT 0 , CNT 1 , CNT 2  and CNT 3  are equal to “n”. If a counting-up adjusting signal is asserted and the counted value is changed from “m” to “m+1”, i.e. “4n+1”, then only the counted value CNT 2  is adjusted from “n” to “n+1”, and the other counted values CNT 0 , CNT 1  and CNT 3  remain equal to “n”. In another case that a counting-up adjusting signal is asserted and “m” becomes “m+2”, i.e. “4n+2”, both the counted values CNT 1  and CNT 3  are adjusted from “n” to “n+1”, and the other counted values CNT 0  and CNT 2  remain unchanged. Further, if a counting-up adjusting signal is asserted and “m” becomes “m+3”, i.e. “4n+3”, then three of the counted values, i.e. CNT 0 , CNT 1  and CNT 3 , are adjusted from “n” to “n+1”, and the other counted value CNT 2  is still equal to “n”. In other words, different counted values in lieu of the only “m+4” adjustment can be used to relatively precisely tune the delay situation. Similarly, when a counting-down adjusting signal is asserted, “m−1”, “m−2” and “m−3” in addition to “m−4” can be rendered according to the present invention. By this method, an optimal distribution can be obtained, as referring to FIG.  4 , wherein the symbols sum 0 , sum  1 , sum 2  and sum 3  represent the ideal delay situations for the four delay lines, and delta 0 , delta 1 , delta 2  and delta 3  represent the differences between real and ideal delay situations, respectively. 
   It is understood that the distribution table can be designed by the one skilled in the art according to the practical requirements. 
   The signals P 1 , P 2 , P 3  and P 0  generated by the delay PLL device according to the present invention are further processed by a logic circuit of  FIG. 5A  in order to obtain a SEL-data signal and a SEL-strobe signal. The logic circuit includes a first logic unit  51  and a second logic unit  52 . In the first logic unit  51 , the signals P 1  and P 3  are inverted by a first inverter  511  and a second inverter  512 . respectively. The inverted signal P 1  is then logically operated with the signal P 0  via an AND gate  521  to obtain a first logic output R 1  and the inverted signal P 3  is then logically operated with the signal P 2  via an AND gate  522  to obtain a second logic output S 1 . The logic outputs R 1  and S 1  serve as reset and set terminals of a first flip flop  531  to result in the SEL-data signal. Likewise, in the second logic unit  52 . the signals P 2  and P 0  are inverted by a third inverter  513  and a fourth inverter  514 . respectively. The inverted signal P 2  is then logically operated with the signal P 1  via an AND gate  523  to obtain a third logic output R 2  and the inverted signal P 0  is then logically operated with the signal P 3  via an AND gate  524  to obtain a fourth logic output S 2 . The logic outputs R 2  and S 2  serve as reset and set terminals of a second flip flop  532  to result in the SEL-strobe signal. The SEL-data signal and the SEL-strobe signal are then referred to generate required data and strobe signals, as shown in  FIG. 5B . It is to be noted that the SEL-data signal and the SEL-strobe signal are essentially dependent from the rising edges of the signals P 1 , P 2 , P 3  and P 0 . In other words, the duty cycles of the signals P 1 , P 2 , P 3  and P 0  have nothing to do with the generation of the data signal and the strobe signal any longer, and thus the deviation as shown in  FIG. 2C  can be ignored. 
   In addition, by use of independently controlled delay lines, the delay skew and interference of different levels resulting from different transmission paths can be adjusted. Examples are given as follows with reference to  FIGS. 6A˜6C . 
   In a first example, the delay time for the delay lines are independently adjusted in order to provide longer data set-up time. Referring to  FIG. 6A , the rising edges of the signals P 1 , P 2 , P 3  and P 0  are indicated by four downward arrows, respectively. Among the four signals, each of the first and the third ones is made to deviated from the quarter position. (90-degree distribution) by Δt by inputting the differences Δt 0 , Δt 1 , Δt 2  and Δt 3  in  FIG. 3  as Δt, −Δt, Δt and −Δt, respectively. Accordingly, the counted values become:
 
CNT0= m/ 4+Δ t 
 
CNT1= m/ 4−Δ t 
 
CNT2= m/ 4+Δ t;  and
 
CNT3= m/ 4−Δ t. 
 
Under this circumstance, the SEL-data signal, the SEL-strobe signal, the data signal and the strobe signal derived from the signals P 1 , P 2 , P 3  and P 0  will be also deviated from predetermined positions. The rising and falling edges of the strobe signal deviate from the middle of the data signal, and thus a longer set-up time of data is provided.
 
   Please refer to  FIG. 6B , a second example where the duty cycle of the strobe signal is changed from 50% is illustrated. In this example, the differences Δt 0 , Δt 1 , Δt 2  and Δt 3  in  FIG. 3  are inputted as 0, 0, Δt and −Δt, respectively. Accordingly, the counted values become:
 
CNT0= m/ 4
 
CNT1= m/ 4
 
CNT2= m/ 4+Δ t;  and
 
CNT3= m/ 4−Δ t. 
 
The third signal P 3  is deviated from the quarter position by Δt. As a result, it is apparent from  FIG. 6B  that the duty cycle of the strobe signal is not 50%.
 
   Please refer to  FIG. 6C , a third example where the duty cycle of the SEL-data signal is changed from 50% is illustrated. In this example, the differences Δt 0 , Δt 1 , Δt 2  and Δt 3  in  FIG. 3  are inputted as 0, −Δt, Δt and 0, respectively. Accordingly, the counted values become:
 
CNT0= m/ 4
 
CNT1= m/ 4−Δ t 
 
CNT2= m/ 4+Δ t;  and
 
CNT3= m/ 4.
 
The second signal P 2  is ahead of the quarter position by Δt. As a result, it is apparent from  FIG. 6C  that the duty cycle of the SEL-data signal is not 50%.
 
   According to the present invention, the delay lines  311 ,  312 ,  313  and  314  can be independently adjusted by inputting different time differences Δt 0 , Δt 1 , Δt 2  and Δt 3 . As for the adjustment of Δt 0 , Δt 1 , Δt 2  and Δt 3 , it can be implemented by precisely measuring the phase difference between each of the output clock signals and the reference clock signal CLK for each circuitry on the basis of the designs of the chipset and the main board. By this way, the time differences of the controlled delay lines, and thus the ideal delay distribution, i.e. the sum 0 , sum 1 , sum 2  and sum 3  in  FIG. 4 , can be determined. 
   By using the delay PLL device according to the present invention as a signal source, the data signal and strobe signal are modified from skew because the predicted different extents of skew resulting from passing through different transmission paths of the chip are adjusted in advance in the signal source. Therefore, the error possibility at the data-receiving end of the memory module can be efficiently diminished, so as to enhance the transmission rate. 
   The delay PLL device and the clock signal generating method according to the present invention can be applied to semiconductor circuit chips of various fields in addition to the core logic chip of a personal computer. 
   While the invention has been described in terms of what are presently considered to be the most practical and preferred embodiments, it is to be understood that the invention need not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.