Abstract:
An N-way Circular Phase Interpolator interpolates the N phases of a reference clock signal to generate a tunable clock. By using more than two phases for interpolation, high excess frequencies as well as high precision (i.e. small jitter) are achieved. The N-way Circular Phase Interpolator provides for analog filtering in the phase domain, which attenuates the out-of-band phase noises thus further reducing the output jitter.

Description:
FIELD OF INVENTION 
     The present invention relates to generation of clock signals in electronic circuits, and more particularly, to generation of clock signals having externally tunable phase and frequency. 
     DESCRIPTION OF THE RELATED ART 
     Many electronic systems, such as communication systems, require clock signals whose phase and frequency can be tuned externally. One such system is the Clock and Data Recovery (CDR) circuit. A CDR circuit recovers the embedded clock from a baseband non-return-to-zero (NRZ) or return-to-zero (RZ) data stream and generates a clean data stream (e.g., data that does not have timing jitter due to e.g. the limited bandwidth of the transmission channel). The clock recovery function of a CDR is typically performed with a Phase-Locked Loop (PLL) which requires a tunable clock signal, such as that generated by a Voltage-Controlled Oscillator (VCO). 
     However, VCOs are generally susceptible to noise, supply voltage, process parameter and temperature variations. Therefore, VCOs and PLLs incorporating VCOs exhibit undesirable characteristics when they are used, for example, in mixed-signal Integrated Circuits (ICs). 
     One well known class of circuits that reduces the above problems is the Delay-Locked Loop (DLLs). A DLL generates a clock signal that has the same frequency as that of a reference clock signal but whose phase may deviate from that of the reference clock by an amount that is within a pre-defined range. 
     However, many systems require plesiochronous clocks, i.e. clocks whose frequencies vary within a small range centered around a nominal value. For example, the 1000Base-X versions of the Gigabit Ethernet standard require a bit-rate deviation of less than 100 parts per million from the nominal bit rate of 1.25 Giga-bit per second. Such plesiochronous clocks cannot be generated by using DLLs. 
     One known method for generating a tunable plesiochronous clock signal is “phase picking”. According to this technique, a number of evenly spaced phases of a reference clock signal are first generated (e.g., 16 as shown in FIG.  1 ). The multiple phases required for this technique could be obtained, for example, by tapping a multi-stage ring oscillator (see  IEEE Journal of Solid State Circuits,  Vol. 25, No. 6, December 1990 “30- Mhz Hybrid Analog/Digital Clock Recovery Circuit in  2-μ m CMOS  by Beomsup Kim, David N. Helma, and Paul R. Gray”; and  IEEE Journal of Solid State Circuits,  Vol. 31, No. 12, December 1996  “A  0.8  μm CMOS  2.5  Gb/s oversampling Receiver and Transmitter for Serial Lines ” by Chih-Kong Ken Yang and Mark A. Horowitz”). Subsequently, the tuned clock signal is generated by dynamically tapping a particular phase. 
     In the phase picking technique, the frequency of the generated clock signal may be different from that of the reference clock signal. If the selected tap moves counter-clockwise, the frequency of the generated clock signal increases over that of the reference clock. If, on the other hand, the selected tap moves clockwise, the frequency of the generated clock signal becomes lower than that of the reference clock. 
     Often, the phase selection occurs at a lower rate than the frequency of the reference clock. Furthermore, it takes many updates to achieve an excess phase (i.e., the difference between the phase of the generated clock and that of the reference clock) of 2π. Consequently, the excess frequency (i.e., the difference between the frequency of the generated clock and that of the reference clock) generated as a result of the movement of the tapped phase is usually small compared to the reference clock frequency, making the phase-picking technique suitable for use in a plesiochronous environment. However, because it is difficult to obtain and distribute many phases of a clock signal, the phase picking technique does not lend itself to fine tuning of phase control. 
     One well known technique for overcoming the above-mentioned problems associated with the phase picking is the Circular Phase Interpolation (CPI) (see ISSCC Dig. Tech. Papers, pp. 160-161, February 1993,  “PLL design for a  500  MB/s Interface ” by M. Horowitz, et al.). FIG. 2 illustrates the four phases, namely I, Q, {overscore (I)} and {overscore (Q)}, which the CPI uses to generate a signal which has the desired phase. As seen from FIG. 2, the four shown phases are 90° apart. According to the CPI technique, the phase of any vector is a weighted sum of two of the above four phases. For example, the phase of vector X is a weighted sum of phases I and Q. Similarly, the phase of vector Y is a weighted sum of phases Q and {overscore (I)}. Consequently, by selecting the proper weights, a signal whose phase is a weighted sum of the above phases is obtained. 
     FIG. 3 shows a known Linear Phase Interpolator (LPI)  10  for linearly interpolating signals A and B, which are respectively represented by a pair of differential signals A + , A −  and B + , B − . In FIG. 3, output signal OUT is represented by differential signals OUT +  and OUT − . As seen from FIG. 3, LPI  10  applies weight signals I A  and I B  respectively to signals A and B to generate signal OUT. Phases θ A , θ B  and θ OUT , which are respectively represented by signals A, B, and OUT, are approximately linearly related, as shown below in equation (1):                θ   OUT     =       θ   fix     +       θ   A     ×       I   A     Io       +       θ   B     ×       I   B       I   O                   (   1   )                                
     where I o =I A +I B . 
     FIG. 4 shows a four phase CPI circuit  100 . CPI  100  includes LPI  10  (also shown in FIG.  3 ), multiplexer (MUX)  20 , Digital-to-analog (D-to-A) converters  30 ,  40 , and combinational logic  50 . Combinational logic  50  receives a digital control word consisting of 2+m bits. The two most significant bits (MSB) of the control word select from among the four phase signals I, Q, {overscore (I)}, {overscore (Q)}. The remaining m bits of the control word are applied to D-to-A converters  30  and  40  which convert the m bits into analog currents I A  and I B , representing the weights applied to the selected phases. Accordingly, the least significant bit (LSB) (i.e., the smallest phase step) corresponds to a phase 2π/2 2+m . MUX  20  receives the MSBs to select and thereby supply to LPI  10  the two signals A and B used for generating signal OUT. Note that a 2π phase, in radian units, is equivalent to a 360° phase, in degree units. 
     CPI  100  of FIG. 4 typically operates under the “unitary update” rule, which requires that each new digital control word differ from the previous one by either 0 or ±1 LSB in order to prevent glitches at the generated phase. In CPI  100 , when the generated phase moves from point X to point Y (see FIG.  2 ), the generated phase must cross phase Q. To provide the proper phase, input phase, signal I is blocked from reaching the output terminal of MUX  20 ; instead, input phase signal I is delivered to the output terminal of MUX  20 . Consequently, unless the weight applied to phase signal I is zero at the time of the input transition, a glitch appears at the generated signal OUT. To prevent the glitch from appearing, the unitary update rule must be met. 
     In order to reduce quantization error, which causes jitter in the phase, and to increase precision, smaller one-LSB steps are required. To achieve smaller steps, either one of the following techniques may be used: 1) increase the number of phase signals (i.e., phase signals I, {overscore (I)}, etc., which constitute the coarse phases); 2) add more bits to the interpolative control signal (i.e., add more bits to the m-bit interpolative control signal FINE of FIG.  4 ). However, both of the above techniques increase system complexity and power consumption. In addition, adding more bits for interpolative control places more stringent linearity requirements on the D-to-A converters  30 ,  40  and linear phase interpolator  10 . Moreover, as more bits are added to the control word to increase precision, because of the unitary update rule, a 2π phase rotation takes longer to complete, thereby affecting the speed of CPI  100 . Therefore, CPI  100  suffers from a trade-off between precision and speed of operation. 
     Therefore, both phase picking and circular phase interpolation techniques have limitations that restrict their use in many applications. 
     SUMMARY 
     An N-way Circular Phase Interpolator (CPI), in accordance with one embodiment of the present invention, generates a signal having the desired phase by generating a weighted sum of N phases of a reference clock. 
     In a three-way CPI (i.e., N is equal to 3), e.g. six phases of a reference clock are used to generate the desired phase. In other words, the three-way CPI divides the 2π phase of a reference clock into e.g. 6 equal phases of 0°, 60°, 120°, 180°, 240° and 300°, thereby creating 6 major phase regions. Each of the six major phase regions is further divided into two sub-regions thereby creating a total of 12 sub-regions. 
     To interpolate a phase, the CPI applies a weight to each of three phases in a phase group. The first and second of these phases form the phase region encompassing the interpolated phase. The third phase in the group is the nearest-neighbor phase to either the first phase or the second phase in the group. 
     Because only the first two phases in each phase group are used for interpolation, the weight associated with the third phase is zero. As the phase of the generated signal moves from one sub-region to the other sub-region within the same major phase region, the third phase changes from being the nearest-neighbor phase to the first phase in the group to the nearest-neighbor phase to the second phase in the group while maintaining a zero weight. When the generated phase eventually crosses the boundary of a major phase region, the three phases used for interpolation remain the same; however, the respective weights applied to the three phases change, thereby preventing glitches at the generated phase. 
     The three-way CPI employs a number of digital-to-analog signal converters to receive m bits, representing the weights applied to each phase in a group of three phases, and supplies the converted analog signals to low-pass analog filters. The analog filters apply the low-pass filtered weights to a linear phase interpolator (LPI). The LPI, in addition to receiving the low-pass filtered analog weights, also receives the three phase signals in a selected phase group and generates a weighted sum of the phase signals to determine the phase of the generated signal. 
     Advantageously, the three-way CPI is not limited by the unitary update rule and achieves faster phase changes. 
     The three-way CPI includes a multiplexer and a combinational logic circuit to implement the required logic functions of the CPI. 
     In a four-way CPI (i.e., N is equal to 4), e.g. eight phases of a reference clock are used to generate the desired phase. In other words, the four-way CPI divides the 2π phase of a reference clock into e.g. 8 equal phases of 0°, 45°, 93°, 135°, 180°, 225°, 270° and 315° to thereby generate the required phase. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows 16 phasors equally spaced along the 2π phase of a reference clock. 
     FIG. 2 shows the four major phases used to interpolate the phase of a generated signal, as known in the prior art. 
     FIG. 3 shows a schematic view of a two-way linear phase interpolator, as known in the prior art. 
     FIG. 4 shows a block diagram of a Circular Phase Interpolator employing four major phases and incorporating the linear phase interpolator of FIG. 3, as known in the prior art. 
     FIG. 5 shows a three-way circular phase interpolator, in accordance with one embodiment of the present invention. 
     FIG. 6 shows a schematic view of the linear phase interpolator of the three-way circular phase interpolator of FIG.  5 . 
     FIG. 7 shows the six major phases and the 12 sub-regions used in the three-way circular phase interpolator of FIG.  5 . 
     FIG. 8 shows a waveform of the input weight signals received by the linear phase interpolator of the three-way circular phase interpolator of FIG. 5 when the phase of the generated signal crosses a major phase. 
    
    
     DETAILED DESCRIPTION 
     FIG. 5 shows a three-way circular phase interpolator  200 , in accordance with one embodiment of the present invention. 
     Three-way circular phase interpolator  200  includes linear phase interpolator (LPI)  210 , multiplexer (MUX)  220 , Digital-to-analog (D-to-A) converters  230 ,  240 ,  250 , analog filters  260 ,  270 ,  280 , and combinational logic  290 . 
     MUX 220 receives the three-bit signal COARSE_SELECT and the most significant bit of the m-bit signal FINE_CONTROL at its input select terminals S 1  and S 2  respectively. The six signals θ 0 , θ 60 , θ 120 , θ 180 , θ 240  and θ 300  (hereinafter phase signals) are respectively 0°, 60°, 120°, 180°, 240° and 300° phase-shifted replicas of the reference clock. 
     Although in the description below of three-way circular phase interpolator  200 , the 2π phase is divided into six equal 60° phases, it is understood that the 2π phase may be divided into any integer numbers of phases (e.g., 8). 
     Phase signals θ 0 , θ 60 , θ 120 , θ 180 , θ 240  and θ 300  are respectively applied to input pins I 0 -I 5  of MUX  220  and each carry a pair of differential signals (not shown and commonly referred to in the context of differential signals as a plus and a minus signal). For example phase signal θ 0  includes signals θ +   0  and θ −   0 , which are differential. In some embodiments, if the voltage supply to CPI  200  is 5 volts, signals θ +   0  and θ −   0  may vary between 2 to 3 volts. In addition, when one of the differential signals (e.g., θ +   0 ) is at a high level (e.g., 3 volts), the other differential signal (e.g., θ −   0 ) is at a low level (e.g., 2 volts). Accordingly, LPI  210  of CPI  200  receives a pair of signals (not shown) for each of the phase signals θ A , θ B , and θ C . 
     MUX  220  has three output terminals O 0 , O 1  and O 2 . Depending on the value of the control signals applied to input terminals S 1  and S 2 , three of the six phase signals are supplied to output terminals O 0 , O 1 , and O 2  of MUX  220 . The output signals of MUX  220 , namely phase signals θ A , θ B  and θ C  are respectively applied to input terminals I 0 , I 1  and I 2  of LPI  210 . 
     Combinational logic circuit  290  receives a digital control word CTRL (not shown) consisting of the three-bit signal COARSE_SELECT and the m-bit signal FINE_CONTROL. Combinational logic  290  generates digital signals CTRL_A, CTRL_B and CTRL_C at its output terminals O 0 , O 1  and O 2 . The three bits of signal COARSE_SELECT form the most significant bits of the digital control word CTRL and the m bits of signal FINE_CONTROL form the least significant bits of the digital control word CTRL. 
     Digital signals CTRL_A, CTRL_B and CTRL_C—each of which have m bits (e.g. m may be equal to 6 in some embodiments)—are respectively converted to analog signals A_OUT, B_OUT and C —C OUT by D-to-A converters  230 ,  240  and  250 . Signals A_OUT, B_OUT and C_OUT are respectively applied to low-pass filters  260 ,  270  and  280 , each of which respectively passes the low frequency part of the signals applied thereto and, in response, generate signals I A , I B  and I C . Signals I A , I B  and I C  are the low-pass filtered analog weight signals which are respectively applied to input terminals I 3 , I 4  and I 5  of linear phase interpolator  210 . 
     FIG. 6 shows a schematic circuit of LPI  210 . LPI  210  includes three differential stages  212 ,  214  and  216 . Differential stage  212  receives signal θ A  (which includes differential signals θ A   +  and θ A   − ) from MUX  220  and signal I A  from filter  260 . Differential stage  214  receives signal θ B  (which includes differential signals θ B   +  and θ B   − ) from MUX  220  and signal I B  from filter 270. Differential stage 216 receives signal θ C  (which includes differential signals θ B   +  and θ B   − ) from MUX  220  and signal I C  from filter  280 . LPJ  210  generates signal θ OUT  which is also the output signal of the CPI  200 . The operation of CPI  200  is described next. 
     FIG. 7 is a phasor diagram of the six phases θ 0 , θ 60 , θ 120 , θ 180 , θ 240  and θ 300  of the reference clock as applied to MUX  220  of FIG.  5 . As seen in FIG. 7, the 2π phase is divided into 12 equal phase regions, each covering a 30° phase range. Starting from phase θ 0  and moving in the counter clock-wise direction, these regions are:  0   a ,  0   b ,  1   a ,  1   b ,  2   a ,  2   b ,  3   a ,  3   b ,  4   a ,  4   b ,  5   a  and  5   b . Therefore, a phasor in region  0   a , has a phase between 0° to 30°. Similarly, a phasor in region  3   b  has a phase between 210° and 240°. 
     Referring to FIG. 5, the phase signal θ OUT  generated by LPI  210  is approximately equal to:                θ   OUT     =       θ   fix     +       θ   A     ×       I   A       I   O         +       θ   B     ×       I   B       I   O         +       θ   C     ×       I   C       I   O                   (   1   )                                
     where θ fix  is a fixed phase delay and I O =I A +I B +I C    
     As seen in equation (1), in accordance with the present invention, phase signal θ OUT  is proportional to a weighted sum of the phase signals θ A , θ B , θ C . The weight applied to each of the phase signals θ A , θ B , θ C  is respectively equal to            I   A       I   O       ,       I   B       I   O       ,         I   C       I   O       .                            
     Advantageously, as shown below, the linearly interpolated phase signal θ OUT  is immune to glitches as phase signal θ OUT  moves past any of the six phase signals θ 0 , θ 60 , θ 120 , θ 180 , θ 240  and θ 300 . 
     The analog filtered signals I A , I B  and I C  are related to their respective digital signals CTRL_A, CTRL_B and CTRL_C by the following equations:                  I   A     =     CTRL_A   ×         I   O     N     ⊗     h        (   t   )                               I   B     =     CTRL_B   ×         I   O     N     ⊗     h        (   t   )                               I   C     =     CTRL_C   ×         I   O     N     ⊗     h        (   t   )                     (   2   )                                
     In equation (2), notation “{circle around (X)}” represents the well-known convolution operation. N is equal to 2 m , where m is the number of bits in signal FINE_CONTROL applied to input terminal I 1  of combinational logic  290 . 
     Additionally, in equation (2), h(t) represents the normalized impulse response of the analog filters  260 ,  270  and  280 . Therefore, ∫h(t)dt=1 for each of the analog filters  260 ,  270  and  280 . Furthermore, in equation (2) 
     
       
         I A +I B +I C =I O   
       
     
     and 
     
       
         CTRL_A+CTRL_B+CTRL_C= N =2 m .  (3) 
       
     
     Let the binary equivalent of the m least significant bits of the digital control word CTRL (i.e., the m bits forming signal FINE_CONTROL) be n, and let the 2′s complement of n be n′. Therefore, 
     
       
           n =mod(CTRL,  N ), 
       
     
     and 
     
       
         
           n′=N−n 
         
       
     
     Table I, shown below, lists for each of the sub-regions  0   a  through  5   b , the corresponding 3 bits of the signal COARSE_SELECT and the most significant bit (MSB) of signal FINE_CONTROL (collectively shown in Table I as a 4-bit signal SELECT) for selecting from among the input phase signals, θ 0 , θ 60 , θ 120 , θ 180 , θ 240  and θ 300 , applied to MUX  220 ; the phase of each of the selected phase signals θ A , θ B  and θ C , as well as the values of signals CTRL_A, CTRL_B and CTRL_C. 
     
       
         
               
               
               
               
               
               
               
               
             
           
               
                 TABLE I 
               
               
                   
               
               
                 Sub- 
                   
                   
                   
                   
                   
                   
                   
               
               
                 reg- 
                 SE- 
               
               
                 ion 
                 LECT 
                 θ A   
                 θ B   
                 θ C   
                 CTRL_A 
                 CTRL_B 
                 CTRL_C 
               
               
                   
               
             
             
               
                 0a 
                 0000 
                 θ 0   
                 θ 60   
                 θ 300   
                 n′ 
                 n 
                 0 
               
               
                 0b 
                 0001 
                 θ 0   
                 θ 60   
                 θ 120   
                 n′ 
                 n 
                 0 
               
               
                 1a 
                 0010 
                 θ 0   
                 θ 60   
                 θ 120   
                 0 
                 n′ 
                 n 
               
               
                 1b 
                 0011 
                 θ 180   
                 θ 60   
                 θ 120   
                 0 
                 n′ 
                 n 
               
               
                 2a 
                 0100 
                 θ 180   
                 θ 60   
                 θ 120   
                 n 
                 0 
                 n′ 
               
               
                 2b 
                 0101 
                 θ 180   
                 θ 240   
                 θ 120   
                 n 
                 0 
                 n′ 
               
               
                 3a 
                 0110 
                 θ 180   
                 θ 240   
                 θ 120   
                 n′ 
                 n 
                 0 
               
               
                 3a 
                 0111 
                 θ 180   
                 θ 240   
                 θ 300   
                 n′ 
                 n 
                 0 
               
               
                 4a 
                 1000 
                 θ 180   
                 θ 240   
                 θ 300   
                 0 
                 n′ 
                 n 
               
               
                 4b 
                 1001 
                 θ 0   
                 θ 240   
                 θ 300   
                 0 
                 n′ 
                 n 
               
               
                 5a 
                 1010 
                 θ 0   
                 θ 240   
                 θ 300   
                 n 
                 0 
                 n′ 
               
               
                 5b 
                 1011 
                 θ 0   
                 θ 60   
                 θ 300   
                 n 
                 0 
                 n′ 
               
               
                   
               
             
          
         
       
     
     Based on the above, if the phase is between 0 and 60 degrees, (i.e., between θ 0  and θ 60 ) signal CTRL is between 0 and N−1, and therefore, according to Table I: 
     
       
         CTRL_A= n′=N− CTRL 
       
     
     
       
         CTRL_B= n= CTRL 
       
     
     
       
         CTRL_C=0  (3) 
       
     
     If the phase is between 60° and 120°, signal CTRL is between N and 2N−1, and, therefore: 
     
       
         CTRL_A=0 
       
     
     
       
         CTRL_B= n′ =2 N −CTRL 
       
     
     
       
         CTRL_C= n =CTRL− N   (5) 
       
     
     According to table I, when the phase is between 0° and 60°, θ A  is equal to 0, θ B  is equal to π/3 and θ C  is equal to either −π/3 (region  0   a ) or to 2π/3 (region  0   b ). After substituting equation (4) into equation (2) and substituting the resulting expression into equation (1), it is seen that:                θ   OUT     =       θ   fix     +       π   3     ×       CTRL   N     ⊗     h        (   t   )                     (   6   )                                
     A similar results is achieved by substituting equation (5) into equation (2) and substituting the resulting expression into equation (1) if the phase is between 60° and 120°. Therefore, equation (6) is valid for all phases. 
     Therefore, as seen from equation (6), output phase signal θ OUT  is proportional to the convolution of the digital control word CTRL (except for the fixed term θ fix ) and the unit sample response h(t) of the analog filters. To further aid in understanding some of the advantages of the present invention, we provide the following example, which refers to FIG.  7  and Table I. 
     Assume that the phase of phasor w lies between 0 and 30 degrees in region  0   a , as shown in FIG.  7 . Therefore, according to Table I, the phase of signal w is determined by phases θ 0 , θ 60  and θ 300 . Note that phase θ 300  has a 60° phase difference with respect to phase θ 0  (i.e., θ 300  is a nearest-neighbor phase to θ 0 ). The weights applied to these phases for linear interpolation, i.e., CTRL_A, CTRL_B and CTRL_C are respectively equal to n′, n and 0. In other words, the weight applied to phase θ 300  is 0. As the phase moves from point w to point x (i.e., from region  0   a  to  0   b ), phase θ 300  (the nearest-neighbor signal to signal θ 0 ) is replaced with phase θ 120  (the nearest signal to signal θ 60 ), although the applied weight to phase θ 120  (i.e., Ctrl_C) remains zero. Next, as the phase moves from point x in sub-region  0   b  to point y in sub-region  1   a , (i.e., crosses the 60° phase), the same phases θ 0 , θ 60  and θ 120 , are used for interpolation, although the weights applied thereto, namely control signals CTRL_A, CTRL_B and CTRL_C, are changed to 0, n′ and n. Therefore, advantageously in accordance with the present invention, each output signal bit (i.e., θ A , θ B  or θ C ) of MUX  220  may change only when the weight of the input signal applied to that output signal bit is zero, thus inhibiting glitches at the generated phase. For example, output signal bit θ A  may change only when weight signal I A  is at zero. 
     FIG. 8 shows the transition in the value of weight signals I A , I B , and I C , respectively applied to phase signals θ 0 , θ 60  and θ 120 , as the phase of the generated signal moves from point x to point y. Due to the availability of the third input port, θ 120  is not replaced with θ 0 . Both θ 120  with θ 0  are coupled to LPI  210  at the same time. Therefore, the output signal θ OUT  of three-way circular phase interpolator  200  does not have glitches. The availability of a third input port also allows a gradual disappearance of contribution from phase signal θ 0 , and a gradual contribution from phase θ 120  by way of analog filtering. Advantageously, the present invention is not limited to the unitary update rule. 
     The analog filtering in the phase domain attenuates the out-of-band phase noises thus providing low output jitter. 
     The circular phase interpolator, in accordance with another embodiment of the present invention, uses phases available at four input ports to interpolate. FIG. 9 shows a phasor diagram which divides the 2π phase of the reference clock signal into eight phases of 0°, 45°, 90°, 135°, 1800, 225°, 270° and 315°. 
     Although in the description below of a four-way circular phase interpolator, the 2π phase is divided into 8 equal 45° phases, it is understood that the 2π phase may be divided into any integer number of phases (e.g. 10). 
     The associated control logic table of a four-way circular phase interpolator is shown in Table II below. 
     As seen from Table II, four phase signals θ A , θ B , θ C  and θ D  respectively receiving weights CTRL_A, CTRL_B, CTRL_C and CTRL_D are used for interpolation. Although four phases are included for interpolation, in a static condition (i.e., the control word is not changing), only the phases of two signals affect the interpolated result because the weights associated with the other two such phases are equal to 0. For example, in phase region  0 , CTRL A and CTRL_D are set to 0 and, therefore, do not affect the linearly interpolated phase. Accordingly, in region  0 , only phases θ B  and θ C  determine the phase of the generated signal. 
     
       
         
               
               
               
               
               
               
               
               
               
               
             
           
               
                   
               
               
                   
                 signal 
                   
                   
                   
                   
                   
                   
                   
                   
               
               
                 Phase 
                 COARSE —   
               
               
                 region 
                 SELECT 
                 θ A   
                 θ B   
                 θ C   
                 θ D   
                 CTRL_A 
                 CTRL_B 
                 CTRL_C 
                 CTRL_D 
               
               
                   
               
             
             
               
                 0 
                 000 
                 θ 315   
                 θ 0   
                 θ 45   
                 θ 90   
                 0 
                 n′ 
                 n 
                 0 
               
               
                 1 
                 001 
                 θ 135   
                 θ 0   
                 θ 45   
                 θ 90   
                 0 
                 0 
                 n′ 
                 n 
               
               
                 2 
                 010 
                 θ 135   
                 θ 180   
                 θ 45   
                 θ 90   
                 n 
                 0 
                 0 
                 n′ 
               
               
                 3 
                 011 
                 θ 135   
                 θ 180   
                 θ 225   
                 θ 90   
                 n′ 
                 n 
                 0 
                 0 
               
               
                 4 
                 100 
                 θ 135   
                 θ 180   
                 θ 225   
                 θ 270   
                 0 
                 n′ 
                 n 
                 0 
               
               
                 5 
                 101 
                 θ 315   
                 θ 180   
                 θ 225   
                 θ 270   
                 0 
                 0 
                 n′ 
                 n 
               
               
                 6 
                 110 
                 θ 315   
                 θ 0   
                 θ 225   
                 θ 270   
                 n 
                 0 
                 0 
                 n′ 
               
               
                 7 
                 111 
                 θ 315   
                 θ 0   
                 θ 45   
                 θ 270   
                 n′ 
                 n 
                 0 
                 0 
               
               
                   
               
             
          
         
       
     
     The exemplary embodiments of the invention disclosed above are illustrative and not limiting. Other embodiments of this invention are possible within the scope of the appended claims. 
     The invention is not limited by the number of input ports used to receive signals for interpolation. 
     The invention is not limited by the number of major phases that divide the 2π phase; nor is it limited by the type of circuitry used to implement the interpolation.