Abstract:
Relay circuitry for a power-over-network device is provided. The relay circuitry allows power-supplying network devices to identify and subsequently to supply power across a network connection to the power-over-network device, thereby eliminating the need for external power sources. The relay circuitry is operative using only the signals transmitted along a data line across the network connection. The relay circuitry is integrated together with switching circuitry on-chip on the power-over-network device. The relay circuitry and switching circuitry are further designed to propagate both the test signals and the subsequent data signals prior to and after the turning on of the power-over-network device, respectively, with minimal signal degradation.

Description:
BACKGROUND OF THE INVENTION 
   The present invention relates to circuitry for power-over-network devices, such as power-over-Ethernet (“POE”) devices, that are powered by a network data cable rather than a separate power source. More particularly, the present invention relates to integrated, on-chip relay circuitry for such network devices. 
   One recent advance with respect to Ethernet network technology has been in the development of power-over-Ethernet devices. As the name suggests, POE devices are powered solely by the Ethernet cable to which they are connected and therefore do not require power from an external AC power source. U.S. patent application Ser. No. 10/098,865, filed on Mar. 15, 2002, for example, describes systems and methods for detecting network devices such as POE devices that are connected to a network and for subsequently supplying power to those connected network devices via a separately connected power-supplying network device. Particularly, application Ser. No. 10/098,865 describes a technique for detecting the presence of a power-over-network device that is capable of being powered on through a network connection, in which the power-supplying device generates a series of test signals and checks whether an appropriate response is received. In order to provide the appropriate response to the power-supplying device, the power-over-network device may include filter circuitry for processing the test signals so that they may ultimately be recognized by the power-supplying device, in addition to relay circuitry that is in a closed-switch state during the detection period in order to relay the filtered test signals to the power-supplying device. Once the power-supplying network device detects a response from the power-on capable device, it then begins to supply power across the network link. Also at that time, the relay circuitry of the power-over-network device switches open and a separate switching circuitry switches closed so that the normal operation of the power-over-network device may commence. 
   Traditionally, the relay circuitry described above for such power-over-network devices are implemented off-chip and external from the rest of the device circuitry. One notable disadvantage caused by implementing the relay circuitry off-chip is the added cost of the circuitry due to a relative increase in the amount of required die. Therefore, in view of the foregoing, it would be desirable to design relay circuitry that is implemented on-chip with the other circuitry of a power-over-network device. It would further be desirable to design on-chip relay circuitry that is configured to relay the test signals transmitted by power-supplying devices without power and with minimal signal degradation so as to reduce the probability of failure during device detection and to thereby make the system more robust. It would be desirable to design on-chip relay circuitry that is integrated with the previously described switching circuitry in order to further increase the performance of and reduce the size and cost of the power-over-network device. 
   SUMMARY OF THE INVENTION 
   In accordance with the present invention, an integrated, on-chip relay circuitry and switching circuitry that is used in connection with detecting the presence of power-over-network devices such as POE devices and with subsequently supplying power to those devices is provided. The relay circuitry utilizes the test signals that are transmitted to and received by the power-over-network device to bring the relay circuitry to a closed-switch state with minimal signal loss and relatively little load capacitance. Specifically, the relay circuitry includes circuitry that is configured to store charge when the inputs are of one polarity, and to use the stored charged to drive the relay circuitry to a closed-switch state when the inputs are of the reverse polarity. The switching circuitry is configured to efficiently shut off the relay circuitry when power is supplied to the network device. 
   Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a simplified system-level diagram of an illustrative embodiment of a power-over-network device in which the relay circuitry and switching circuitry in accordance with the present invention is implemented; 
       FIG. 2  is another simplified placement-view diagram of an illustrative embodiment of the power-over-network device in accordance with the present invention; 
       FIG. 3  is a circuit diagram of an illustrative embodiment of the relay circuitry and switching circuitry portion of the power-over-network device in accordance with the present invention; 
       FIGS. 4A and 4B  are voltage-signal waveforms of the differential input signals that may be received by the circuitry of the present invention; and 
       FIG. 5  is an alternative circuit diagram of an illustrative embodiment of the relay circuitry and switching circuitry portion of the power-over-network device in accordance with the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1  shows an illustrative embodiment of a typical system in which the circuitry of the present invention is implemented. In  FIG. 1 , power-supplying network device  100  (such as a switch or a hub) is connected to an Ethernet network to which power-over-network device  102  (such as an Internet Protocol (“IP”) telephone) is connected. Although references are made herein to an Ethernet network, such references are merely the purpose of illustration, and it will therefore be understood that the present invention may be realized in other suitable types of networks. Specifically, in  FIG. 1 , power-supplying network device  100  includes power-sourcing equipment (“PSE”)  104  that is connected to the center taps in the primary side of each of power transformers  106  and  108 . As a result, the power provided by PSE  104  is supplied over Ethernet links  110  and  112  to the secondary sides of power transformers  114  and  116 , which are in turn connected to power-over-network device  102 . 
   The portion of power-over-network device  102  shown in  FIG. 1  includes identical interface circuitry  118  and  120 . Interface circuitry  118  is connected to interface circuitry  120  through filter  122  and relay circuitry  124  via differential lines  142 ,  144 ,  146 , and  148 . The differential output of the primary side of power transformer  114  is connected to switching circuitry  126  and to transceiver  138  of interface circuitry  118  comprising transmitter circuitry  128  and receiver circuitry  130 . Similarly, the differential output of the primary side of power transformer  116  is connected to switching circuitry  132  and to transceiver  140  of interface circuitry  120  comprising transmitter circuitry  134  and receiver circuitry  136 . As previously mentioned, during detection, test signal pulses generated by and transmitted from power-supplying network device  100  may be sent to interface circuitry  118  via Ethernet link  110  and relayed back by interface circuitry  120  via Ethernet link  112 . Alternatively, because the system operates bidirectionally, the test signals may be transmitted to interface circuitry  120  via link  112  and relayed back by interface circuitry  118  via link  110 . During this period, no power is supplied to power-over-network device  102 . Switching circuitry  126  and switching circuitry  132  are both in an open state, and relay circuitry  124  is in a closed state. Once power-supplying network device  100  detects the relayed test signals from power-over-network device  102 , however, power-supplying network device  100  begins supplying power to power-over-network device  102  across links  110  and  112 , and accordingly power-over-network device  102  begins operating in a normal, powered-on mode. Switching circuitry  126  and switching circuitry  132  are subsequently closed, and relay circuitry  124  is open. Interface circuitry  118  and interface circuitry  120  may operate substantially independently during normal operation. 
     FIG. 2  shows a placement-view diagram of the front-end interface portion of the power-over-network device  102  shown in  FIG. 1 . Specifically,  FIG. 2  shows that the circuitry forming transceiver  138  and  140  may form part of analog front end  200  of power-over-network device  102 . Furthermore, as shown in  FIG. 2 , switching circuitry  126  may, for example, be implemented using PMOS transistors  202  and  204 , and similarly switching circuitry  132  may be implemented using PMOS transistors  206  and  208 . PMOS transistors  202 - 208  as well as relay circuitry  124  may be implemented peripherally around analog front end  200 . Finally, as shown in  FIG. 2 , the signal outputs of the integrated circuit portions of power-over-network device  102  comprising PMOS transistors  202 - 208 , relay circuitry  124 , and transceivers  138  and  140  are padded with I/O pads. 
     FIG. 3  shows a circuit-level diagram of an embodiment of relay circuitry  124  and switching circuitry  300  of the present invention. As previously mentioned, the relay and switching circuitry shown in  FIG. 3  are integrated on the same on-chip device. Relay circuitry  124  is comprised of charge-pump circuits  302 ,  304 ,  306  and  308  and NMOS transistors  310  and  312 . 
   Although charge-pump circuits  302 ,  304 ,  306  and  308  are shown as identical circuits in  FIG. 3 , it will be appreciated that the charge-pump circuits used by the relay circuitry do not have to be identical circuits comprising the same circuit elements or circuit characteristics. 
   Looking at the arrangement of charge-pump circuits  302 ,  304 ,  306  and  308  more closely, it is seen that charge-pump circuits  302  and  304  are connected to the positive and negative differential lines on one side of the differential relay switch, and that charge-pump circuits  306  and  308  are connected to the positive and negative differential lines on the other side of the differential relay switch. (For clarity and consistency, it will be assumed that in  FIG. 3 , lines  314  and  318  correspond to the positive differential line of the system (e.g., lines  142  and  146  of  FIG. 1 ) and lines  316  and  320  correspond to the negative differential line of the system (e.g., lines  144  and  148  of  FIG. 1 ). However, due to the symmetry in the operation of the circuitry of the present invention, it will be understood that the positive and negative differential lines may be interchanged without any effect on the operation of the circuitry.) As previously mentioned, the purpose of connecting charge-pump circuits  302 ,  304 ,  306  and  308  to either side of the differential relay switch is to support bidirectional operation. Specifically, when data is received on lines  314  and  316 , charge-pump circuits  302  and  304  are activated as will be described below in order to allow the data to be relayed onto lines  318  and  320  with minimal signal loss. In particular, charge-pump circuit  302  is used to provide a sufficient amount of additional gate drive in turning on NMOS transistor  310 . Similarly, charge-pump circuit  304  is used to more greatly turn on NMOS transistor  312 . Conversely, when data is received on lines  318  and  320 , charge-pump circuits  306  and  308  are activated in order to allow the data to be relayed onto lines  314  and  316 . In particular, charge-pump circuit  306  assists in the turning on of NMOS transistor  310 , and charge-pump circuit  308  assists in the turning on of NMOS transistor  312 . 
   Since each of charge-pump circuits  302 ,  304 ,  306  and  308  are identical, the structure and operation of the charge-pump circuits  302 ,  304 ,  306  and  308  in the relay and switching circuitry will be discussed with respect to a single, arbitrarily chosen charge-pump circuit, charge-pump circuit  302 . Charge-pump circuit  302  is comprised of PMOS transistor  322 , capacitor  324 , and resistor  326 . As previously mentioned, the function of charge-pump circuit  302  is to provide sufficient gate drive to NMOS transistor  310 . To more clearly illustrate how this is achieved, reference is made to  FIGS. 4A and 4B , which show example differential input signals that may be received on lines  314  and  316 . However, since  FIG. 3  shows relay circuitry that is implemented bidirectionally, the input signals shown in  FIGS. 4A and 4B  may alternatively be received on lines  318  and  320 . In particular, the input signal waveforms in  FIGS. 4A and 4B  correspond to square waves each having a 1-volt (V) peak-to-peak voltage centered at 0V. It will be understood that these waveforms are merely exemplary and used only to demonstrate the behavior of charge pump circuit  302  during the different phases of the input signal. 
   During the first half-period of the input signals on lines  314  and  316  (i.e., the “charge” cycle, or when V 314 =+0.5 V and V 316 =−0.5 V), PMOS transistor  322  is turned on. As a result, the PMOS transistor  322  turns on, thereby allowing line  314  to charge node  328  to 0.5 V, and a charge of 1 V to be stored across capacitor  324 . It should be mentioned that the details about PMOS transistor  322  such as its impedance are not critical so long as PMOS transistor  322  is turned on sufficiently for a sufficient duration so that 1 V of charge develops across capacitor  324 . For example, it is not necessary for PMOS transistor  322  to be a low impedance device. The actual parameters of the PMOS transistor  322  will naturally vary according to variables such as the characteristics of the input signals on lines  314  and  316  and the size of capacitor  324 . 
   Subsequently, when the polarity of the input signals is reversed (i.e., during the “boost” cycle, or when V 314 =−0.5 V and V 316 =+0.5 V), PMOS transistor  322  shuts off. The combination of the voltage on line  314  and the 1 V stored on capacitor  324  drives node  328  up to approximately 1.5 V. In accordance with the invention, NMOS transistor  310  is designed such that the 1.5 V on node  328  causes NMOS transistor  310  to be turned on hard. It will be appreciated that turning on NMOS transistor  310  hard forces the transistor to operate in a low-impedance region of operation, thereby minimizing the signal loss across NMOS transistor  310  as signals on line  314  are relayed to line  318 . Moreover, turning on NMOS transistor  310  hard has the added benefits of reducing the required size of and lowering the parasitic (i.e., gate-to-source) capacitance of NMOS transistor  310 , thereby reducing the overall load of relay circuitry  124 . 
   As was mentioned, each of charge-pump circuits  304 ,  306  and  308  operate principally in the same manner as charge-pump circuit  302 . The only difference is that charge-pump circuits  304 ,  306  and  308  are connected differently and/or connected to different inputs. Specifically, given the input signal waveforms shown in  FIGS. 4A and 4B , the charge cycle of charge-pump circuit  304  occurs when the voltage on line  316  is +0.5 V and the voltage on line  314  is −0.5 V, and the boost cycle occurs when the voltage on line  316  is −0.5V and the voltage on line  314  is +0.5V. Therefore, it is seen that during the period when charge-pump circuit  302  is in the charge cycle, charge-pump circuit  304  is in the boost cycle, and vice-versa. Furthermore, as shown in  FIG. 3 , to support bidirectional operation, charge-pump circuits  306  and  308  similarly turn on NMOS transistors  310  and  312  based on the voltages on lines  318  and  320 . In general, it will be understood that relay circuitry  124  remains in a closed-switch state based on the switching action on the differential input signals (i.e., transitions from a logic 1 to a logic 0 and vice-versa). Thus, depending on the frequency with which the input signals on lines  314  and  316 , and/or lines  318  and  320  switch, properties of the various elements of relay circuitry  124  such as the transistor and capacitor sizing may be varied and tailored to the input signal pattern. 
   It will be understood that relay circuitry  124  is only operative when no power is applied to switching circuitry  300 . When power is applied on line  330  to switching circuitry  300  (e.g., via PSE  104  of power-supplying network device  100  through either one or both of power transformers  114  and  116 ), switching circuitry  300  is turned on, bringing the voltage on node  328  to ground and thereby turning off NMOS transistors  310  and  312  of relay circuitry  124 . In particular, switching circuitry  300  includes NMOS transistors  332  and  334 . When NMOS transistors  332  and  334  are turned on, the voltages on nodes  328  and  336  are pulled down to ground, as defined by the value of center-tap node  338 . Resistor  326  of charge-pump circuit  302  limits the current that flows across PMOS transistor  322  and that is therefore lost when power is supplied and forces switching circuitry  300  closed and relay circuitry  124  open (and the same is true of the corresponding resistors of charge-pump circuits  304 ,  306  and  308 ), so that the effect of pulling nodes  328  and  336  to ground has minimal impact on the input signals. The value of the resistors may be selected so that, for example, there is no more than 0.5% overall loss in the input signals due to the operation of switching circuitry  300 . 
   Although the relay and switching circuitry has been described up until now to be bidirectional, it will be understood that the circuitry of the present invention may alternatively be implemented to only support unidirectional operation.  FIG. 5 , for example, illustrates the relay and switching circuitry  500  of the present invention that is configured for unidirectional operation. Because the implementation of unidirectional relay and switching circuitry  500  is identical to that of the bidirectional implementation shown in  FIG. 3 , with the exception of the absence of charge pump circuits  306  and  308  in  FIG. 3  from  FIG. 5 , the operation of circuitry  500  will not be described. It will only be generally mentioned that circuitry  500  includes charge-pump circuits  502  and  504 , switching circuitry  506  and NMOS transistors  508  and  510 , and that a pair differential of input signals received on lines  512  and  514  (corresponding, e.g., to lines  142  and  144  of  FIG. 1 ) by unidirectional relay and switching circuitry  500  are relayed onto lines  516  and (corresponding, e.g., to lines  146  and  148  of  FIG. 1 ) only when NMOS transistors  508  and  510  are turned on (i.e., when power is not supplied via line  520  to switching circuitry  506 ). 
   It will be understood, therefore, that the foregoing is only illustrative of the principles of the invention, and that various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention, and that the present invention is limited only by the claims that follow.