Abstract:
In one or more embodiments, an apparatus and method for processing an analog signal into a digital signal includes an input current buffer circuit, a signal charge integration node, a dual function comparator, a step charge subtractor, a state latch, a coarse N-bit counter, an optional residue signal buffer and a residue signal M-bit time-to-digital (TDC) converter. The circuitry is free running, meaning that it is never reset. Instead, what is tracked for each frame is how much additional charge has been accumulated since the end of the previous integration period. Between each frame, the state of the counter and the amount of charge residing in the integration node are recorded. This information from the beginning and end of a given frame is differenced and to this is added the amount of charge indicated by the number of times the counter overflowed during the integration period.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the benefit of U.S. Provisional Application No. 61/884,601, filed 30 Sep. 2013. 
    
    
     STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
     This invention was made with Government support under SBIR contract No. HQ0147-12-C-7808 awarded by the Missile Defense Agency. The Government has certain SBIR Data rights in this invention. 
    
    
     TECHNICAL FIELD OF THE INVENTION 
     The teachings herein relate to a low power analog to digital conversion (ADC) that is particularly advantageous for use with sensors of an array. 
     BACKGROUND OF THE INVENTION 
     Advanced focal plane arrays (FPAs), such as infrared focal plane arrays (IRFPAs) utilize embedded ADCs on the read out integrated circuitry (ROIC) die. On-ROIC digital readout allows on-chip digital signal processing, increased dynamic range, and increased signal to noise ratio. On-ROIC ADC is often incorporated at one or more FPA outputs or at ROIC columns. More ADCs on the ROIC tend to provide increased digital resolution and reduced ADC power due to reduced digitization frequency. 
     One serious limitation of current ROIC technology is the difficulty of achieving very large charge capacity in small pixel pitch. Analog circuits do not scale well because voltages and capacitances are reduced and transistor noise increases for smaller technologies and sizes. There have been efforts to overcome these analog limitations by implementing an A/D converter in each pixel, but those we are aware of have significant problems with high noise, large power dissipation and require extremely expensive non-recurring costs for very small design rule CMOS tooling. The ADC per pixel concept (also referred to as a digital pixel sensor (DPS)) has increased difficulty of implementation in large format mega-pixel FPAs as pixel pitch is reduced (&lt;30 μm), ADC resolution increased (&gt;14-bits) and FPA frame rate is increased (&gt;60 Hz). 
     In-pixel ADC can be accomplished by counting charge packets integrated on C INT  from the detector current I det . In  FIG. 1A , prior art, the photocurrent, created by the illumination, discharges C INT  until V int  equals V th  (also referred to as V ref ), then the comparator commands the injection of Q 0  at the integration node and the counter is incremented by one. At the end of the integration time, the counter contains the number N. Since the LSB value of the A/D conversion is Q 0 , N·Q 0  has been detected. In  FIG. 1B , prior art, the charge packet reset is replaced by a voltage reset. The only difference between the two techniques is the way Q 0  is generated. In the “voltage reset” case,  FIG. 1B , Q 0 =C int ·ΔV=C int ·(Vo−V th ) and consequently the LSB is highly dependent on V th . This technique is thus very sensitive to the performance of the comparator but allows an efficient layout. In the “charge reset” case,  FIG. 1B , Q 0  is generated by a charge injector, thus it relaxes constraints on the comparator and on C INT  precision, providing the charge injector has good performance. 
     Both techniques, in  FIG. 1A  and  FIG. 1B , require a binary counter per pixel that can occupy a significant amount of the readout pixel area, especially for a large number of bits and small pixel pitch. The repeated voltage reset or charge reset of C INT  adds additional temporal noise. 
     A two-step ADC has been utilized to reduce in-pixel counter size and reduce ADC power.  FIG. 2  shows prior art where the first 11-bits are determined by a charge counting architecture at the pixel-level and the last 5-bits are determined by a column level ADC. As illustrated on  FIG. 2 , the pixel uses a pixel-level ADC technique that consists in counting charge packets so that, at the end of the integration time, the pixel counter contains a digital value proportional to the total integrated charge and the residue remains on the integration capacitance (C INT ). In  FIG. 2  the in-pixel comparator is used only for the 11-bit in-pixel ADC. Voltage reset on the integration node is utilized. The voltage reset of C INT  to Vdd adds additional reset noise (kTC INT ). 
       FIG. 3 , prior art, shows a two-step ADC where the most significant bits (MSBs) are determined in the pixel and the least significant bits (LSBs) are determined by digitization of the residual signal integrated on C INT . The LSB residual signal A/D conversion occurs external to the pixel. In  FIG. 3 , charge reset is utilized. A FET and first switch are disposed in series between a dump capacitor and the integration node. A second switch operates to discharge the dump capacitor, and an output of the comparator controls both switches in opposition. Upon command of the comparator circuitry, the integration capacitor transfers a fixed amount of charge into the dump capacitor through an injection FET with V g =V ref 2  operating in saturation. 
     In  FIG. 3 , the bottom of the dump capacitor may be connected to a special reference voltage, but ground can be used when layout constraints exist. The common potential V comm  may differ between the integrating and dump capacitors. Noise is added at the end of every charge dump event. 
     In a preferred embodiment, the circuit of  FIG. 3  operates in a 5-volt system, V ref1  is 3.3 volts, and V ref2  is 2.5 volts. The values of C int  and C dump  are chosen such that the voltage at the integration node V int  does not fall below 2.5 volts (V ref2 ). The repeated charge reset of C INT  adds additional reset noise (kTC dump ). 
     BRIEF SUMMARY OF THE INVENTION 
     The foregoing and other problems are overcome by methods and apparatus in accordance with embodiments of this invention. Therefore, it is considered that the embodiments provided herein are illustrative only, and are not to be considered limiting of the invention. 
     In one or more embodiments, an apparatus and method for processing an analog signal into a digital signal includes an optional input current buffer circuit, a signal charge integration node with integration capacitor, a dual function comparator, a step charge subtractor with associated step charge capacitor, a state latch, a coarse (MSB) N-bit counter, an optional residue signal buffer and a residue signal (LSB) M-bit time-to-digital converter. 
     The circuit is best described with reference to a node termed an integration node. An integration capacitor (C INT ) is connected to the integration node. The comparator has a first input connected to the integration node and a second input connected to a reference voltage V CMP  that is preferably supplied externally and independent of the voltage within the circuit deriving from an input signal. 
     A second capacitor is termed a step charge capacitor (C SC ), and has a first node connected to a step voltage clock ø STEP  and a second node connected to a step charge node. A step charge subtractor circuit is connected between the step charge node and integration node with an insolation transistor controlled by a voltage Vs. A state latch sends a signal to the state charge subtractor to subtract a fixed amount of charge from the integration node. The step clock voltage, ø STEP , is typically much larger than the ROIC analog supply voltage (˜3.3-5.0 volts). Large ø STEP  amplitude allows a significant reduction in C SC  capacitance for a fixed amount of step charge and a significant reduction in charge reset noise (related to kTC SC ). 
     In another aspect of the invention is a readout circuit. The readout circuit includes a detector input node for receiving a photocurrent generated by a radiation detector. The photocurrent represents the analog signal to be converted by the readout circuit, and refers to any current signal output by the various types of radiation detectors. The circuit further includes an optional detector buffer circuit and an integration capacitor, C INT , having a first node coupled to the input node, and a dual function comparator. The dual function comparator input is coupled to the node of the integrating capacitor to provide repeated readout of charge packets and a final reference signal. 
     The present invention additionally includes a method for converting an analog signal to a digital signal. The method includes inputting an analog current signal to an input node and comparing an electrical parameter at an integration node to a reference electrical parameter. The input node and the integration node are in series with one another. In a first comparator state, preferably where the voltage at the integration node is less than the reference voltage (V CMP ), the method includes charging a capacitor from the input node which accomplishes the integration. In a second comparator state, preferably where the voltage at the integration node is greater than the reference voltage (V CMP ) that charge stored on the capacitor is decremented, preferably by a fixed and precise amount into a step charge capacitor via an injection/isolation FET. The charge decrement accomplishes the subtraction. In the preferred embodiment, the parameter after the decrement, voltage at the integration node is once again lower than the reference voltage, and the comparator state reverts to the first state on the next clock edge. By counting the number of decrements, a large portion of the analog signal is converted to a digital signal. Counting the comparator state changes from first to second, from second to first, or both are each included within the term counting the number of decrements. 
     The present invention additionally includes a method for converting a residue analog signal to a digital signal. The comparator output is used for two functions: during the bulk of the integration period. First, it is used by the state control circuitry in conjunction with a static reference voltage on V CMP , to initiate step charge subtraction events. Second, while at the end of each integration period it is used, in conjunction with a ramped reference voltage on V CMP , to provide the capture of residue signal and send to the column located time-to-digital (TDC) circuitry. 
     The concept of this invention is also applied when the photo current is inverted. In this case, step charge circuit adds a fixed charge into the integration node once it goes sufficiently below the trip point of the comparator. 
     Other variations are disclosed that provide additional details that may remain within one or more particular embodiments. Further variations may become evident to those of ordinary skill in the art without departing from the described principles and claimed invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above set forth and other features of the invention are made more apparent in the ensuing Detailed Description of the Invention when read in conjunction with the attached Drawings, wherein: 
         FIG. 1A  depicts the basic architecture of a prior art ADC/pixel charge packet counting method with charge reset; 
         FIG. 1B  depicts the basic architecture of a prior art ADC/pixel charge packet counting method with voltage reset; 
         FIG. 2  depicts a prior art enhancement to the basic architecture, referred to as the two-step ADC using in-pixel charge packet counting with voltage reset and residual signal ADC at column; 
         FIG. 3  depicts a prior art enhancement to the basic architecture, referred to as the two-step ADC using in-pixel charge packet counting with charge reset and residual signal ADC at column; 
         FIG. 4  depicts a block diagram of a two-step ADC using charge packet counting with charge reset and residual ADC according to the teachings herein; 
         FIG. 5  depicts signal processing steps done at ROIC periphery or off ROIC 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Disclosed herein is a low power two-step ADC, such as one that may be used in a large imaging array. An exemplary embodiment is depicted in  FIG. 4 . A low power two-step ADC  100  is connected by a detector buffer circuit  2  or other signal conditioning circuitry to detection components, represented as a diode  1 . An input integration node  3  is a point at which current from the detector enters the circuit  100  substantially unchanged by the circuit  100 . An integrating capacitor  4 , a step charge subtractor  5  and a dual function comparator  6  are each connected in parallel to the integration node  3 . 
     The detector buffer circuit  2  isolates the detector from the charge integration node  3  which is dominated by capacitor C INT . In some cases, such as a detector with large reverse bias capability, a detector buffer circuit is not required and charge integration can occur directly on the detector capacitance. The most simple detector buffer circuit is am input transistor comprising a low noise PFET source follower that holds a constant voltage on the circuit side of the detector, as determined by VGG, provided the detector is biased sufficient above VGG to keep the detector active. Other buffer circuits can be utilized comprising CMOS or bipolar transistors. 
     The integration node  3  comprises an integration capacitor  4  (C INT ), and stray capacitance resulting from connections to the detector buffer circuit  2 , dual function comparator  6  and step charge subtractor  5 . As detector current flows from the detector buffer circuit (all discussions use conventional current flow), the voltage on the integration node  3  rises. The isolation transistor permits charge to be removed from the integration node by the step charge circuit while preventing charge from flowing onto the integration node as the step charge circuit is reset. When the voltage has risen sufficiently high for the comparator to sense it, a chain of events is initiated that results in one unit of step charge being subtracted from the integration node. An isolation transistor within the step charge subtractor  5  permits charge to be removed from the integration node  3  by the step charge circuit while preventing charge from flowing onto the integration node as the step charge circuit is reset. 
     A step charge capacitor (C SC )  8  is coupled to a step charge node  7  that is connected to the step charge subtractor  5 . The step charge subtractor analog circuitry is responsible for performing the step charge subtraction from the integration node  3 . The ø STEP  signal is a global square wave voltage that alternately pushes and pulls charge onto and off of node  7  in each pixel via each pixel&#39;s C SC  capacitor  8 . The amount of charge transferred is the product of the ø STEP  amplitude and the C SC  capacitance. On the downward transition of ø STEP , each pixel either wants to pull charge off its integration node or forego the opportunity to do so. Most of the time the pixel will want to pass up the opportunity and this occurs when the state control output signal, ‘Q’, is LO, which turns on the reset transistor within 5 clamping the node  7  to the digital supply and shutting off the isolation transistor, the forces the charge pulled through C SC  to come from the digital supply and not the integration node. Similarly, on the rising edge of ø STEP , the charge pushed through C 2  will be delivered to the digital supply and not pushed onto the integration node  3 . However, when ‘Q’ is HI, the reset transistor is turned off and charge is pulled from the integration node  3  on the falling edge of ø STEP . Prior to ø STEP  the next rising edge of ø STEP , the reset is reasserted by taking ‘Q’ LO again. 
     If the detector input signal exceeds the integration node charge capacity, as set by V CMP  in the comparator  6 , then the step-charge subtraction circuit will remove one step charge from the integration node. Each time this happens, there is an uncertainty in the amount of charge actually removed due to the thermal noise of the step capacitor. This noise, which is the square root of kTC, where k is Boltzmann&#39;s constant, T is the absolute temperature, and C is the step capacitor size (C SC ), is very low because the use of a low capacitance combined with a large ø STEP  amplitude. Since this uncertainty exists in each step charge subtraction that is carried out and since these errors are statistically independent, the accumulated error is the individual error multiplied by the square root of the number of step charge subtractions. The C SC  capacitor  8  is capable of withstanding a large voltage and can be fabricated from with metal-insulator-metal layers (MIM) in the integrated circuit process. A large push-pull voltage swing across C SC  allows a reduction in C SC  capacitance and resultant reduction in kTC noise compared to charge dump approaches using low analog supply voltages and MOS capacitors. 
     Comparator  6  is a dual function comparator used for both steps of the two-step ADC  100 . During coarse signal integration, the reference voltage, V CMP , is held constant. At the end of the frame, when it is necessary to measure the residual charge on the integration node  3 , a special comparison cycle is performed in which the comparison voltage is ramped downward from a voltage slightly higher than the normal value of V CMP . At the same time this ramp starts its descent, a Gray Code counter is launched in the ROIC chip periphery and the output distributed to all of the column buffers. When the comparator fires, the ‘td’ pixel output  9 , which is enabled only during this task, tells the column buffer to capture the present Gray Code counter state. Since each column buffer can only capture a single value at a time, and since the ‘td’ column line is shared by multiple rows, this process must be repeated for each row, with the caveat that the array can be parsed so half of the rows are read out the top and half read out the bottom, enabling two rows to be read out simultaneously. Additionally, if there is sufficient room for additional column lines and additional capture registers in the column buffers, then multiple rows can be read out simultaneously. 
     The state latch  10  is used to capture the knowledge that the integration node has risen above the comparator trip point and hold it until it has been properly acted upon. The storage element is an SRAM cell formed by two cross-coupled inverters. This simple latch can be reset by taking the Prst signal HI. To set the latch, both the comparator output and the write strobe (WS) input must be HI. 
     Once the latch is reset by stroking Prst HI, the comparator output is sampled by stroking the WS HI. If the latch is set, the ‘Q’ and ‘Qb’ outputs will act as a complementary clock pair to clock the pixel&#39;s ripple counter  11 . After WS returns LO, the ø STEP  voltage is ramped downward and, if the latch is set, one step charge is removed from the integration node. At this point, Prst is asserted again to clear the latch prior to rising transition of ø STEP . 
     The N-bit digital section  11  is shown in  FIG. 4 . To detect a counter overflow during integration, the most significant bit of the counter is periodically polled (read out) by the peripheral circuitry. In order not to miss an overflow, this polling must occur frequently enough to ensure that the MSB is read at least once between each pair of transitions. In order to facilitate a fast polling rate, the four column lines devoted to the counter output bits are rotated between the four bits every four rows. Thus, four rows can be read out simultaneously, with one row&#39;s MSB driven onto each of the four column lines. 
     During the end of frame readout, when it is necessary to read out the entire counter state, both the MSB and the lower-order bit lines are driven onto the column lines one row at a time. Because the lines are rotated through a complete cycle every four rows, either the peripheral circuitry on the chip or the off-chip software must reverse the rotation. Unless column header space is at a premium, performing this task on-chip is very straightforward and would make the management of this approach completely on-chip, thus not only simplifying the off-chip software, but making future changes to how these bits are read out of the array invisible beyond the chip boundary. 
     Because the counter accounts for the bulk of the transistors in the pixel, minimizing the transistor count and size associated with each stage is crucial to attaining a small pixel size. To this end, the design allows for non-resettable flip flops to be used. Furthermore, because each latch operates strictly within the confines of one pixel, buffering and internal clock generation can be eliminated through careful simulation. This permits normal D-type flip-flop to be trimmed from its normal 30-transistors to only 12. Another option is the use of a linear-feedback shift register (LSFR) using dynamic flip flops in place of the ripple counter. 
     The TDC (time-to-digital converter)  12  works by ramping a reference voltage across the range of voltages that the unknown voltage could be and measuring the time it takes for the reference voltage to match the unknown voltage. The time is measured by running a digital counter and capturing the count when the two voltages are equal. Because the value recorded is the difference between measurements taken at the end of one frame and the end of the next, the uncertainty in this value is +/−1 LSB. Since the TDC read noise does not depend on the integrated signal charge, it quickly becomes an insignificant noise source compared to the shot noise as the signal magnitude increases. 
     During each frame, the pixel is guided through a sequence built from a set of four states: 1) Counter Readout, 2) Counter Overflow Detection, 3) Step Charge Maintenance and 4) Residual Charge Readout. At the beginning of each frame, the state of each in-pixel counter is read out. After that, and for the bulk of the frame period, the pixel alternates performing Counter Overflow Detection and Step Charge Maintenance operations. At the very end of the frame period, a Residual Charge Readout is performed. To generate the image data for the present frame, the data read out during that frame must be combined with the residual charge value from the previous frame and the counter value that will be read out at the beginning of the following frame. Between each frame, the state of the counter and the amount of charge residing in the sub-integration well are recorded. This information from the beginning and end of a given frame is then differenced and to this is added the amount of charge indicated by the number of times the counter overflowed during the frame. 
     Processing the data output by the ROIC column is accomplished by the data path as shown in  FIG. 5 . When the step charge counter roll over value is combined with the step charge counter value it forms the total step charge count value. The total step charge value then can be compared to the previous frames total step charge value to arrive at the bases for the current frame signal upper bits. The TDC Gray code value is converted to binary by the ROIC. The TDC binary value forms the bases for the lower bits of the current frame signal value.