Abstract:
A demultiplexer includes an input terminal for providing an input signal, a plurality of output terminals for outputting the input signal, and a switching circuit coupled among the input terminal and the plurality of output terminals, and outputting the input signal selectively from the plurality of output terminals according to a plurality of control signals provided to a plurality of control terminals. For miniaturizing the demultiplexer, the switching circuit includes one or more switch elements connected between the input terminal and each of the output terminals in series, wherein at least two of the switch elements coupled to different output terminals are simultaneously switched in response to one control signal from the plurality of control terminals.

Description:
FIELD OF THE INVENTION 
     The present invention relates to a demultiplexer, and more particularly to a demultiplexer which selects a data output by way of time division. The present invention also relates to an electronic device such as a liquid crystal display using a demultiplexer. 
     BACKGROUND OF THE INVENTION 
     Nowadays, with the increasing demand on high resolution of LCD, there is a trend towards narrowing the frame of a display panel. 
     Generally, the analog voltage applied to an internal pixel for revealing contents to be displayed is provided by a source driver IC with an external image data input interface, which is disposed in the frame area on the glass substrate. The source driver IC includes a plurality of output terminals which are connected to the pixel array by way of, for example, metal-thin-film wiring on the glass substrate. 
     Typically, the number of wires extending from a side of the pixel array conforms to the number of pixels in a row. However, the number of output terminals of the source driver IC arranged in parallel is less than the number of pixels in a row due to the size of the output terminals. 
     Accordingly, a demultiplexer operating by time division is used, as disclosed in Japanese Laid Open Patent Publication No. 2007-334109, to distribute a less number of terminals of the source driver IC to a greater number of wires at a side of the array. 
       FIG. 9  illustrates a conventional demultiplexer, and  FIG. 10  exemplifies operations of the conventional demultiplexer, wherein  FIG. 10A  is a circuit diagram of the conventional demultiplexer, and  FIG. 10B  is a timing diagram of the conventional demultiplexer. 
     In the conventional demultiplexer  10  shown in  FIG. 9  and  FIG. 10 , switching units M 1 ˜M 7  disposed on output lines Lout 1 ˜Lout 7  are switched in response to control signals CNT 1 ˜CNT 7  supplied to control lines Lcnt 1 ˜Lcnt 7 . Accordingly, an input signal IN supplied to an input line Lin is selectively outputted via one of the output lines Lout 1 ˜Lout 7  as a corresponding one of the output signals Y 1 ˜Y 7 . The switching units M 1 ˜M 7 , for example, are implemented with n-channel field effect transistors. 
     As shown in  FIG. 10B , during a D 1  data period of the input signal IN supplied to the input line Lin, the control signal CNT 1  is at a high level while the control signals CNT 2 ˜CNT 7  are at a low level; during a D 2  data period of the input signal IN, the control signal CNT 2  is at a high level while the control signals CNT 1 , CNT 3 ˜CNT 7  are at a low level; during a D 3  data period of the input signal IN, the control signal CNT 3  is at a high level while the control signals CNT 1 , CNT 2 , CNT 4 ˜CNT 7  are at a low level; during a D 4  data period of the input signal IN, the control signal CNT 4  is at a high level while the control signals CNT 1 ˜CNT 3 , CNT 5 ˜CNT 7  are at a low level; during a D 5  data period of the input signal IN, the control signal CNT 5  is at a high level while the control signals CNT 1 ˜CNT 4 , CNT 6 , CNT 7  are at a low level; during a D 6  data period of the input signal IN, the control signal CNT 6  is at a high level while the control signals CNT 1 ˜CNT 5 , CNT 7  are at a low level; and during a D 7  data period of the input signal IN, the control signal CNT 7  is at a high level while the control signals CNT 1 ˜CNT 6  are at a low level. Therefore, the resulting output data with the output signal Y 1  is D 1 ; the resulting output data with the output signal Y 2  is D 2 ; the resulting output data with the output signal Y 3  is D 3 ; the resulting output data with the output signal Y 4  is D 4 ; the resulting output data with the output signal Y 5  is D 5 ; the resulting output data with the output signal Y 6  is D 6 ; and the resulting output data with the output signal Y 7  is D 7 . In other words, the input signal IN is selectively outputted through one of the output lines Lout 1 ˜Lout 7 . 
     For narrowing the frame of the LCD, it is necessary to limit the sizes of not only the source driver IC but also the layout size of the demultiplexer. The layout lines thus become as thin as a needle. 
     Furthermore, power saving is also an important issue for designing a display. For example, in the field of mobile phones, the recharging cycle of a battery is one of the issues that concerns an end user very much. 
     It is critical for a mobile phone to be power-efficient, but it is still necessary to reveal information such as current time, residual power of battery, etc. on the display even when the mobile phone is not working as being put through, navigating pages or checking emails. Therefore, the backlight of the display is turned off temporarily to save power and reflected external light is used for revealing the information. However, even if the mobile phone is operated under such a reflective mode, hundreds of microwatts of power is still consumed for standby recovery, and several to hundreds of watts of power is also consumed for telephonic communication. 
     In the above-mentioned reflective mode, a displaying method such as a conventional MIP (Memory in Pixel) technology is used to minimize power consumption, wherein the analog source driver IC is suspended for saving power while utilizing a memory circuit in a pixel to hold the displayed frame. 
     According to the MIP technology, data are stored in a one-bit (two-value) memory of each sub-pixel. By way of selectively combining one of two voltage levels and one of three elementary colors in each pixel, eight colors (8=2^3) can be realized. However, a typical source driver IC generally reveals each pixel with combinations selected from 64 voltage levels and 3 elementary colors, which results in about 262K colors (262,144=64^3). It is apparent that many colors are sacrificed in the MIP technology. 
     For solving such a problem, a multi-bit MIP technology is preferred. For example, if the memory in each sub-pixel is of six bits, the performance will be comparable to that of the typical source driver IC, i.e. 262K colors (262,144=(2^6)^3) for each pixel. Since a 6-bit memory is used in each sub-pixel but only one source line at a side of the array is provided for writing data to each sub-pixel, time division is required for distributing data to the memories of the sub-pixels with the aid of a demultiplexer. Due to the demand on high resolution, the size of each sub-pixel is limited to at most 100 microns. In other words, the demultiplexer has to be miniaturized to a certain extent. 
     SUMMARY OF THE INVENTION 
     Therefore, an object of the present invention is to provide a miniaturized demultiplexer with reduced numbers of terminals and wires. 
     Another object of the present invention is to provide an electronic device such as a liquid crystal display using a miniaturized demultiplexer. 
     The present invention relates to a demultiplexer, which includes an input terminal for providing an input signal; a plurality of output terminals for outputting the input signal; and a switching circuit connected between the input terminal and the output terminals for selectively outputting the input signal from the output terminals according to a plurality of control signals provided via corresponding control terminals. The switching circuit includes one or more switching elements serially connected between the input terminal and each of the output terminals, and simultaneously switching elements more than two switching elements thereof coupled to different ones of the output terminals according to a single one of the control signals. 
     The present invention also relates to a demultiplexer, which includes an input terminal; first to seventh output terminals; and first to twelfth switching elements connected between the input terminal and the first to seventh output terminals, and switched according to first to third control signals. The first to third switching elements are connected between the input terminal and the first output terminal in series; the fourth and fifth switching elements are connected between the input terminal and the second output terminal in series; the sixth and seventh switching elements are connected between the input terminal and the third output terminal in series; the eighth and ninth switching elements are connected between the input terminal and the fourth output terminal in series; the tenth switching elements is connected between the input terminal and the fifth output terminal in series; the eleventh switching elements is connected between the input terminal and the sixth output terminal in series; the twelfth switching elements is connected between the input terminal and the seventh output terminal in series; the first, fourth, eighth and tenth switching elements are switched according to the first control signal; the second, fifth, sixth and eleventh switching elements are switched according to the second control signal; and the third, seventh, ninth and twelfth switching elements are switched according to the third control signal. 
     The present invention further relates to an electronic device, which includes a demultiplexer according to the present invention and a functional member coupled to the output terminals of the demultiplexer. 
     The present invention further relates to a liquid crystal display, which includes a demultiplexer according to the present invention and an active matrix display member to be driven by the output signals of the demultiplexer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above contents of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which: 
         FIG. 1  is a circuit diagram illustrating a demultiplexer according to an embodiment of the present invention; 
         FIG. 2  is a plane view schematically showing a structure of the demultiplexer of  FIG. 1 ; 
         FIG. 3  is a cross-sectional view schematically showing a structure of the demultiplexer of  FIG. 1 ; 
         FIG. 4A˜FIG .  4 K are timing sequence diagrams of signals associated with the demultiplexer of  FIG. 1 ; 
         FIG. 5  is a schematic diagram showing components of a LCD according to an embodiment of the present invention; 
         FIG. 6  is a schematic diagram showing a structure of a display zone included in the LCD of  FIG. 5 ; 
         FIG. 7A  is an equivalent circuit diagram illustrating an embodiment of a demultiplexer included in the LCD of  FIG. 5 ; 
         FIG. 7B  is an equivalent circuit diagram illustrating an embodiment of a sub-pixel included in the LCD of  FIG. 5 ; 
         FIG. 8  is a circuit diagram illustrating an embodiment of a demultiplexer included in a sub-pixel with a MIP structure according to the present invention; 
         FIG. 9  is a plane view schematically showing a structure of the demultiplexer according to prior art; and 
         FIG. 10A  is a circuit diagram illustrating a demultiplexer of  FIG. 9 ; and 
         FIG. 10B  is a timing diagram of signals associated with the demultiplexer of  FIG. 9 . 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Please refer to  FIG. 1 ,  FIG. 2  and  FIG. 3  for illustrating a demultiplexer according to an embodiment of the present invention. 
     The demultiplexer  100  has an input terminal Tin and first to seventh output terminals Tout 1 ˜Tout 7 , and includes first to twelfth switching elements M 11 , M 12 , M 13 , M 21 , M 22 , M 31 , M 32 , M 41 , M 42 , M 51 , M 61  and M 71  disposed between the input terminal and the output terminals and selectively switched according to first to third control signals cnt 1 ˜cnt 3  supplied via first to third control terminals Tcnt 1 ˜Tcnt 3 . 
     The first to twelfth switching elements M 11 , M 12 , M 13 , M 21 , M 22 , M 31 , M 32 , M 41 , M 42 , M 51 , M 61  and M 71 , for example, can be implemented with n-channel field effect transistors. In the application to an LCD panel as exemplified in  FIG. 2  and  FIG. 3 , the switching elements are formed on an insulating substrate  101  such as glass. A channel layer  102  is formed of p-type semiconductor on the insulating substrate  101 . A wire L 11  is formed at one end of the channel layer  102  and connected to a wire Lin which is connected to the input terminal Tin. At the other end of the channel layer  102 , a wire L 21  is formed and connected to wires Lout which are connected to the output terminals Tout 1 ˜Tout 7 . Furthermore, a wire L 31  is formed above the channel layer  102  through an oxide film  103 . The wire L 31  is connected to any of the wires Lcnt which are connected to the control terminals Tcnt 1 ˜Tcnt 3 . The wires L 11 , L 21  and L 31 , for example, are formed of aluminum or other suitable conductive material. 
     It is to be noted that the switching elements M 11 , M 12 , M 13 , M 21 , M 22 , M 31 , M 32 , M 41 , M 42 , M 51 , M 61  and M 71  are not limited to n-channel field effect transistors, and can also be, for example, p-channel field effect transistors, bipolar transistors, etc. 
     The first to third switching elements M 11 , M 12  and M 13  are connected between the input terminal Tin and the first output terminal Tout 1  in series; the fourth and fifth switching elements M 21  and M 22  are connected between the input terminal Tin and the second output terminal Tout 2  in series; the sixth and seventh switching elements M 31  and M 32  are connected between the input terminal Tin and the third output terminal Tout 3  in series; the eighth and ninth switching elements M 41  and M 42  are connected between the input terminal Tin and the fourth output terminal Tout 4  in series; the tenth switching elements M 51  is connected between the input terminal Tin and the fifth output terminal Tout 5 ; the eleventh switching element M 61  is connected between the input terminal Tin and the sixth output terminal Tout 6 ; and the twelfth switching element M 71  is connected between the input terminal Tin and the seventh output terminal Tout 7 . 
     The first, fourth, eighth and tenth switching elements M 11 , M 21 , M 41  and M 51  are switched according to the first control signal cnt 1  supplied via the first control terminal Tcnt 1 ; the second, fifth, sixth and eleventh switching elements M 12 , M 22 , M 31  and M 61  are switched according to the second control signal cnt 2  supplied via the second control terminal Tcnt 2 ; and the third, seventh, ninth and twelfth switching elements M 13 , M 32 , M 42  and M 71  are switched according to the third control signal cnt 3  supplied via the third control terminal Tcnt 3 . 
     Now refer to  FIG. 4A˜FIG .  4 K which illustrate timing sequences of signals associated with the demultiplexer  100 , wherein  FIG. 4A  illustrates the timing sequence diagram of the input signal supplied via the input terminal Tin;  FIG. 4B  illustrates the timing sequence diagram of the first control signal cnt 1  supplied via the first control terminal Tcnt 1 ;  FIG. 4C  illustrates the timing sequence diagram of the second control signal cnt 2  supplied via the second control terminal Tcnt 2 ;  FIG. 4D  illustrates the timing sequence diagram of the third control signal cnt 3  supplied via the third control terminal Tcnt 3 ;  FIG. 4E  illustrates the timing sequence diagram of the first output signal Y 1  outputted via the first output terminal Tout 1 ;  FIG. 4F  illustrates the timing sequence diagram of the second output signal Y 2  outputted via the second output terminal Tout 2 ;  FIG. 4G  illustrates the timing sequence diagram of the third output signal Y 3  outputted via the third output terminal Tout 3 ;  FIG. 4H  illustrates the timing sequence diagram of the fourth output signal Y 4  outputted via the fourth output terminal Tout 4 ;  FIG. 4I  illustrates the timing sequence diagram of the fifth output signal Y 5  outputted via the fifth output terminal Tout 5 ;  FIG. 4J  illustrates the timing sequence diagram of the sixth output signal Y 1  outputted via the sixth output terminal Tout 6 ; and  FIG. 4K  illustrates the timing sequence diagram of the seventh output signal Y 7  outputted via the seventh output terminal Tout 7 . 
     As shown in  FIG. 4A , the level of the input signal supplied via the input terminal Tin changes to D 1 ˜D 7  in sequence every specified period of time Tx. As shown in  FIG. 4(B) ,  FIG. 4(C)  and  FIG. 4(D) , the first to third control signals cnt 1 ˜cnt 3  and the level of the input signal IN switch synchronously. In this embodiment, charge-holding elements, e.g. capacitive elements capable of holding capacitance, are connected to the first to seventh output terminals Tout 1 ˜Tout 7 . Hereinafter, the operation of the demultiplexer  100  is described in time division. 
     Within the period of time T 1 , the input signal IN is inputted as the level D 1  via the input terminal Tin. Meanwhile, the first to third control signals cnt 1 ˜cnt 3  are all at high levels, as shown in  FIG. 4(B)˜FIG .  4 (D). Since the first to third control signals cnt 1 ˜cnt 3  are all at high levels, the first to the twelfth switching elements M 11 , M 12 , M 13 , M 21 , M 22 , M 31 , M 32 , M 41 , M 42 , M 51 , M 61  and M 71  are all turned on. Accordingly, the output signals Y 1 ˜Y 7  outputted via the output terminals Tout 1 ˜Tout 7  are all at the level D 1 , as shown in  FIG. 4(E)˜FIG .  4 (K). 
     Within the period of time T 2 , the input signal IN is inputted as the level D 2  via the input terminal Tin. Meanwhile, the first and second control signals cnt 1  and cnt 2  are at high levels and the third control signal cnt 3  is at a low level, as shown in  FIG. 4(B)˜FIG .  4 (D). Accordingly, the first, second, fourth to sixth, eighth, tenth and eleventh switching elements M 11 , M 12 , M 21 , M 22 , M 31 , M 41 , M 51  and M 61  are turned on while the third, seventh, ninth and twelfth switching elements M 13 , M 32 , M 42  and M 71  are turned off so that the output terminals Tout 1 , Tout 3 , Tout 4  and Tout 7  are electrically disconnected from the input terminal Tin. Under this circumstance, the output signals Y 1 , Y 3 , Y 4  and Y 7  are kept at the level D 1 , as shown in  FIG. 4(E) ,  FIG. 4(G) ,  FIG. 4(H)  and  FIG. 4(K) , by the charge-holding elements coupled to corresponding output terminals. On the other hand, what is held by the charge-holding elements connected to the second, fifth and sixth output terminals Tout 2 , Tout 5  and Tout 6  becomes the level D 2 , as shown in  FIG. 4(F) ,  FIG. 4(I)  and  FIG. 4(J) , since the second, fifth and sixth output terminals Tout 2 , Tout 5  and Tout 6  are electrically connected to the input terminal Tin. 
     Within the period of time T 3 , the input signal IN is inputted as the level D 3  via the input terminal Tin. Meanwhile, the first and second control signals cnt 1  and cnt 2  are at high levels and the third control signal cnt 3  is at a low level, as shown in  FIG. 4(B)˜FIG .  4 (D). Accordingly, the first, fourth, eighth and tenth switching elements M 11 , M 21 , M 41  and M 51  are turned off while the second, third, fifth to seventh, ninth, eleventh and twelfth switching elements M 12 , M 13 , M 22 , M 31 , M 32 , M 42 , M 61  and M 71  are turned on so that the output terminals Tout 1 , Tout 2 , Tout 4  and Tout 5  are electrically disconnected from the input terminal Tin. Under this circumstance, the output signals Y 1  and Y 4  outputted from the output terminals Tout 1  and Tout 4  are kept at the level D 1 , as shown in  FIG. 4(E)  and  FIG. 4(H) , while the output signals Y 2  and Y 5  outputted from the output terminals Tout 2  and Tout 5  are kept at the level D 2 , as shown in  FIG. 4(F)  and  FIG. 4(I) . On the other hand, what is held by the charge-holding elements connected to the third, sixth and seventh output terminals Tout 3 , Tout 6  and Tout 7  becomes the level D 3 , as shown in  FIG. 4(G) ,  FIG. 4(J)  and  FIG. 4(K) , since the third, sixth and seventh output terminals Tout 3 , Tout 6  and Tout 7  are electrically connected to the input terminal Tin. 
     Within the period of time T 4 , the input signal IN is inputted as the level D 4  via the input terminal Tin. Meanwhile, the first and third control signals cnt 1  and cnt 3  are at high levels and the second control signal cnt 2  is at a low level, as shown in  FIG. 4(B)˜FIG .  4 (D). Accordingly, the second, fifth, sixth and eleventh switching elements M 12 , M 22 , M 31  and M 61  are turned off while the first, third, fourth, seventh to ninth, tenth and twelfth switching elements M 11 , M 13 , M 21 , M 32 , M 41 , M 42 , M 51  and M 71  are turned on so that the output terminals Tout 1 , Tout 2 , Tout 3  and Tout 6  are electrically disconnected from the input terminal Tin. Under this circumstance, the output signal Y 1  outputted from the output terminal Tout 1  is kept at the level D 1 , as shown in  FIG. 4(E) ; the output signal Y 2  outputted from the output terminal Tout 2  is kept at the level D 2 , as shown in  FIG. 4F ; and the output signals Y 3  and Y 6  outputted from the output terminals Tout 2  and Tout 6  are kept at the level D 3 , as shown in  FIG. 4(G)  and  FIG. 4(J) . On the other hand, what is held by the charge-holding elements connected to the fourth, fifth and seventh output terminals Tout 4 , Tout 5  and Tout 7  becomes the level D 4 , as shown in  FIG. 4H ,  FIG. 4I  and  FIG. 4K , since the fourth, fifth and seventh output terminals Tout 4 , Tout 5  and Tout 7  are electrically connected to the input terminal Tin. 
     Within the period of time T 5 , the input signal IN is inputted as the level D 5  via the input terminal Tin. Meanwhile, the first control signal cnt 1  is at a high level and the second and third control signals cnt 2  and cnt 3  are at low levels, as shown in  FIG. 4(B)˜FIG .  4 (D). Accordingly, the first, fourth, eighth and tenth switching elements M 11 , M 21 , M 41  and M 51  are turned off while the second, third, fifth to seventh, ninth, eleventh and twelfth switching elements M 12 , M 13 , M 22 , M 31 , M 32 , M 42 , M 61  and M 71  are turned on so that the output terminals Tout 1 ˜Tout 4 , Tout 6  and Tout 7  are electrically disconnected from the input terminal Tin. Under this circumstance, the output signal Y 1  outputted from the output terminal Tout 1  is kept at the level D 1 , as shown in  FIG. 4(E) ; the output signal Y 2  outputted from the output terminal Tout 2  is kept at the level D 2 , as shown in  FIG. 4(F) ; the output signals Y 3  and Y 6  outputted from the output terminals Tout 3  and Tout 6  are kept at the level D 3 , as shown in  FIG. 4(G)  and  FIG. 4(J) ; and the output signals Y 4  and Y 7  outputted from the output terminals Tout 4  and Tout 7  are kept at the level D 4 , as shown in  FIG. 4(H)  and  FIG. 4(K) . On the other hand, what is held by the charge-holding elements connected to the fifth output terminal Tout 5  becomes the level D 5 , as shown in  FIG. 4(I) , since the fifth output terminal Tout 5  is electrically connected to the input terminal Tin. 
     Within the period of time T 6 , the input signal IN is inputted as the level D 6  via the input terminal Tin. Meanwhile, the second control signal cnt 2  is at a high level and the first and third control signals cnt 1  and cnt 3  are at low levels, as shown in  FIG. 4(B)˜FIG .  4 (D). Accordingly, the second, fifth, sixth and eleventh switching elements M 12 , M 22 , M 31  and M 61  are turned off while the first, third, fourth, seventh to tenth and twelfth switching elements M 11 , M 13 , M 21 , M 32 , M 41 , M 42 , M 51  and M 71  are turned on so that the output terminals Tout 1 ˜Tout 5  and Tout 7  are electrically disconnected from the input terminal Tin. Under this circumstance, the output signal Y 1  outputted from the output terminal Tout 1  is kept at the level D 1 , as shown in  FIG. 4(E) ; the output signal Y 2  outputted from the output terminal Tout 2  is kept at the level D 2 , as shown in  FIG. 4(F) ; the output signal Y 3  outputted from the output terminal Tout 3  is kept at the level D 3 , as shown in  FIG. 4(G) ; the output signals Y 4  and Y 7  outputted from the output terminals Tout 4  and Tout 7  are kept at the level D 4 , as shown in  FIG. 4(H)  and  FIG. 4(K) ; and the output signal Y 5  outputted from the output terminal Tout 5  is kept at the level D 5 , as shown in  FIG. 4(I) . On the other hand, what is held by the charge-holding elements connected to the sixth output terminal Tout 6  becomes the level D 6 , as shown in  FIG. 4(J) , since the sixth output terminal Tout 6  is electrically connected to the input terminal Tin. 
     Within the period of time T 7 , the input signal IN is inputted as the level D 7  via the input terminal Tin. Meanwhile, the third control signal cnt 3  is at a high level and the first and second control signals cntl and cnt 2  are at low levels, as shown in  FIG. 4(B)˜FIG .  4 (D). Accordingly, the third, seventh, ninth and twelfth switching elements M 13 , M 32 , M 42  and M 71  are turned off while the first, second, fourth to sixth, eighth, tenth and eleventh switching elements M 11 , M 12 , M 21 , M 22 , M 31 , M 41 , M 51  and M 61  are turned on so that the output terminals Tout 1 ˜Tout 6  are electrically disconnected from the input terminal Tin. Under this circumstance, the output signal Y 1  outputted from the output terminal Tout 1  is kept at the level Dl, as shown in  FIG. 4(E) ; the output signal Y 2  outputted from the output terminal Tout 2  is kept at the level D 2 , as shown in  FIG. 4(F) ; the output signal Y 3  outputted from the output terminal Tout 3  is kept at the level D 3 , as shown in  FIG. 4(G) ; the output signal Y 4  outputted from the output terminal Tout 4  is kept at the level D 4 , as shown in  FIG. 4(H) ; the output signal Y 5  outputted from the output terminal Tout 5  is kept at the level D 5 , as shown in  FIG. 4(I) ; and the output signal Y 6  outputted from the output terminal Tout 6  is kept at the level D 6 , as shown in  FIG. 4(J) . On the other hand, what is held by the charge-holding elements connected to the seventh output terminal Tout 7  becomes the level D 7 , as shown in  FIG. 4(K) , since the seventh output terminal Tout 7  is electrically connected to the input terminal Tin. 
     Accordingly, the levels of the input signal are selectively outputted from the output terminals Tout 1 ˜Tout 7  as the output signals, wherein the level D 1  is outputted from the first output terminal Tout 1 ; the level D 2  is outputted from the second output terminal Tout 2 ; the level D 3  is outputted from the third output terminal Tout 3 ; the level D 4  is outputted from the fourth output terminal Tout 4 ; the level D 5  is outputted from the fifth output terminal Tout 5 ; the level D 6  is outputted from the sixth output terminal Tout 6 ; and the level D 7  is outputted from the seventh output terminal Tout 7 . 
     According to the above-described embodiment of the present invention, the number of control terminals can be reduced from seven to three and the number of wires can be reduced as well. Thereby, the demultiplexer and associated circuitry can be miniaturized. 
     In the above-described embodiment of a demultiplexer, the inclusion of one input terminal, three control terminals and seven output terminals is just for exemplification and simplification, and there is no such limitation to the demultiplexers according to the present invention. Preferably, however, a formula N=2 A −1 is complied with in general cases, where A is the number of control terminals and N is the number of output terminals. 
     Hereinafter, the application of a demultiplexer to an active-type LCD according to the present invention is exemplified.  FIG. 5  schematically illustrates components of the LCD. The LCD  200  includes a display area  212  disposed on a lower glass substrate  211 , and a gate driver IC  213 , a source driver IC  214 , a demultiplexer  215  and I/O circuit  216  disposed beside the display area  212 . 
       FIG. 6  schematically shows components of the display area  212 . In the display area  212 , matrices of pixel electrodes  221 , thin film transistors (TFT)  222 , gate lines  223  and data lines  224  are formed on the lower glass substrate  211 . Above the pixel electrodes  221 , thin film transistors (TFTs)  222 , gate lines  223  and data lines  224 , an alignment film  225  and an upper glass substrate  231  disposed above the alignment film  225  through a spacer layer (not shown) are provided. On almost the entire surface of the upper glass substrate  231  facing to the lower glass substrate  211 , a common electrode  232  and an alignment film  233  are formed. Furthermore, a liquid crystal material  241  is sealed in the space between the lower glass substrate  211  and the upper glass substrate  231 . 
     By way of selectively switching the TFTs  222 , voltages are supplied to selective pixel electrodes  221  from corresponding data lines  224 , and the directions of the liquid crystal molecules vary with the voltage difference between the pixel electrodes  221  and the common electrode  232  so as to change optical properties of the LCD for displaying pixels. 
     The gate driver IC  213  is coupled to the gates of the TFTs  222  for switching the TFTs  222 . The source driver IC  214  supplies driving voltages to sources of the TFTs  222  via the demultiplexer  215  which has a configuration similar to the demultiplexer  100  as shown in  FIG. 1˜FIG .  3 , thereby selectively supplying voltages to the data lines  224  based on the operations of the demultiplexer  215  as illustrated in  FIG. 4 . Meanwhile, six of the seven outputs of the demultiplexer  100  are used. 
       FIG. 7  illustrates equivalent circuits of parts of the LCD  200 , wherein  FIG. 7A  illustrates the demultiplexer  215  beside the display zone  212 , and  FIG. 7B  illustrates a sub-pixel  220  in the display zone  212 . 
     As shown in  FIG. 7A , the output of the source driver IC  214  is supplied to the input terminal Tin of the demultiplexer  215 . The output terminals Tout 1 ˜Tout 6  of the demultiplexer  215  are coupled to the data lines  224  and then led to the display area  212 . On the other hand, the output of the gate driver IC  213  is led to the display area  212  via gate lines  223 . 
     As shown in  FIG. 7B , the gate line  223  led to the display area  212  is connected to the gate of the TFT  222  disposed in the sub-pixel  220 ; the data line  224  led to the display area  212  is coupled to the source of the TFT  222  disposed in the sub-pixels  220 ; and the drain of the TFT  222  is coupled to the pixel electrode  221  and to an auxiliary capacitor line  226  via an auxiliary capacitor Cs. Furthermore,  FIG. 7B  shows that a liquid crystal capacitor Clc is formed in each sub-pixel  220  by clamping liquid crystal molecules  241  between the pixel electrode  221  and the common electrode  232 . 
     By using six of the seven outputs of the demultiplexer  100  of  FIG. 1  in the demultiplexer  215  of the LCD  200 , the number of control terminals can be reduced to miniaturize the demultiplexer and thus narrow the frame of the LCD  200 . 
     The demultiplexer according to the present invention is applicable to the MIP technology.  FIG. 8  illustrates an example of the application, wherein a sub-pixel  301  with a MIP structure includes a demultiplexer  302 , a memory unit  303 , and a sub-pixel capacitor  304 . 
     The demultiplexer  302  has a configuration similar to that of the demultiplexer  100  described above, and utilizes three control lines In 1 ˜In 3  and six of the seven outputs to store data in the memory unit  303  consisting of six storage elements MEM 1 ˜MEM 6 . Then the sub-pixel capacitor  304  is charged/discharged for displaying according to the 6-bit data stored in memory unit  303 . 
     From the above descriptions, it is understood that the use of the demultiplexer according to the present invention in the sub-pixel results in a reduced number of control lines for dealing with multi-bit data. Therefore, the area occupied by the demultiplexer in the sub-pixel is reduced so as to reduce the area of the sub-pixel. Meanwhile, the imaging effect of the LCD can be enhanced. 
     It is to be noted that the application of the demultiplexer according to the present invention is not limited to LCD. Instead, it can be used in any other suitable electronic device, e.g. a plasma display, EL display, a mobile phone, a digital camera, a personal digital assistant (PDA), a notebook computer, a desktop computer, a TV set, a global positioning system (GPS), a vehicular display, an aircraft display, a digital frame or a portable DVD player, with or without modification. The output terminals of the demultiplexer in the electronic device may be coupled to a functional member, e.g. a memory cell, an image sensor, a digital-to-analog converter or a display unit. 
     While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not to be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.