Abstract:
A differential comparator which outputs positive and/or negative logic signals to an output terminal according to the coincidence/non-coincidence of first and second input signal levels inputted to first and second input terminals, respectively, comprises an offset cancel function composed of an offset capacitor device provided on the differential comparator side of the first and second terminals, a first switch for short-circuiting the first and second input terminals in such a way as to form a closed loop including the offset capacitor device, and a second switch for short-circuiting both the connection point between the offset capacitor device and the differential comparator, and the output terminal.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2004-197329, filed in Month 07, 2004, the entire contents of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a differential comparator, an analog/digital conversion apparatus and an imaging apparatus, more particularly, to a technology effective when applied to the reading circuit of optical/electrical conversion signals in a complementary metal oxide semiconductor (CMOS) image sensor and the like.  
         [0004]     2. Description of the Related Art  
         [0005]     Attention is paid to a CMOS image sensor, for example, for the reason that the CMOS image sensor matches the manufacturing process, operating voltage and the like in surrounding image processing circuits, and that an imaging apparatus, an image processing circuit, a controller and the like can be easily integrated on one chip and the like, compared with, for example, a charge-coupled device (CCD) image sensor.  
         [0006]     Since this CMOS image sensor amplifies not only a photoelectric conversion device but also a conversion signal at each pixel level, the CMOS image sensor is resistant to noise in the transmission process of a photoelectric conversion signal. However, its fixed pattern noise due to the unevenness in a characteristic among amplifiers at each pixel level is a problem.  
         [0007]     For this reason, a configuration in which the same number of correlation double sampling (CDS) circuits and analog/digital conversion (ADC) circuits as the number of columns are disposed in series for each set of pixels in the column direction, of a plurality of pixels two-dimensionally arrayed in the orthogonal row and column directions, that is, a configuration in which the fixed pattern noise is reduced by a so-called column ADC method, is well known.  
         [0008]     As the column ADC of the CMOS image sensor, for example, Patent Reference 1 discloses a technology for realizing fine color control for each color by selectively outputting a different analog comparison reference voltage for a pixel column ADC provided for each color filter of three primary colors of light. Specifically, the accuracy of digital conversion is attempted to improve by short-circuiting the input/output of a chopper type comparator using an inverter and shifting the reference voltage by the same as the shifted value of a threshold voltage, due to the parasitic capacitance of a transistor constituting the relevant inverter.  
         [0009]     Patent Reference 2 discloses a technology for eliminating fixed pattern noise that can exist in pixels to improve image quality, by adding a capacitor on the ramp signal input side of a chopper type comparator in which an inverter is connected in double stages, storing offset voltage in the reset mode of a pixel and correcting the voltage of a ramp signal inputted in the counter mode by the offset voltage.  
         [0010]     Patent Reference 3 discloses a technology for realizing a stable analog/digital conversion characteristic by shifting the reference voltage of an inverter constituting an AD converter and controlling so that a signal outputted from a pixel and the reference voltage may be compared if the relevant reference voltage has a linear characteristic.  
         [0011]     Patent Reference 4 discloses a technology for preventing a direct current level from differing among a plurality of pixel reading signals to improve image quality, by providing a plurality of analog/digital converters, selecting the output of the plurality of analog/digital converters one after another, constituting a noise cancel (comparison) unit of a plurality of amplifiers composed of a differential amplifier and an inverter in a fixed imaging device for obtaining digital picture output and by providing amplifiers at the second stage and after with a clamp circuit.  
         [0012]     However, any of the above-mentioned technologies of Patent References 1 through 4 does not recognize the following technical problems caused when the comparator of the analog/digital converter is composed of only an inverter, or an inverter and a differential amplifier.  
         [0013]     Specifically,  FIG. 1  is a block diagram showing the configuration of a chopper type comparator, which is the reference technology of the present invention. The chopper type comparator using an inverter A 100  shown in  FIG. 1  stores an analog signal in C 100  when switches S 100  and S 100   x  are switched on, and compares the analog signal with reference voltage when S 100  and S 100   x  are turned off and S 200  is turned on to determine the analog signal. However, there is at a point B a parasitic capacitor (C 200 ), such as the gate capacitor of a transistor constituting the inverter A 100  or the like. Therefore, if the reference voltage is inputted for comparison, the potential at a point A, point B attempts to transit to the potential of the amount of charge stored in C 100  based on the potential at point A. However, since there is the parasitic capacitor C 200 , point B changes at a ratio between C 100  and C 200 , and the accuracy of analog/digital conversion degrades, which is a technical problem.  
         [0014]     Specifically, as shown in  FIG. 2 , in the inverter A 100  of the CMOS imaging sensor, a p type MOS transistor Q 100  and a n type MOS transistor Q 200  (threshold value V th ) are provided in series between power supply VDD and grounding, and their respective gates and voltage between their sources are used as input and output (OUT), respectively. However, the parasitic capacitor Q p  and Q n  of Q 100  and Q 200 , respectively, affect capacitor C 100  on the input side. Therefore, for example, when SW 100  and SW 200  are turned off and on, respectively, and when RampV is inputted, the respective gate potential Q 100  and Q 200  fluctuates at a ratio of V th −C 100  (ADC-RampV)/(C 100 +C p +C n ) and the accuracy of analog/digital conversion degrades.  
         [0015]     In a configuration using an inverter, the consumption current of the inverter is high. More particularly, in a configuration where a lot of ADC is provided for each column, like column ADC in the CMOS image sensor, the total consumption current of the imaging device becomes very high. As the countermeasure, it may be considered to increase the respective gate length of Q 100  and Q 200  to suppress the consumption current. However, this is not preferable, since the respective parasitic capacitance Q p  and Q n  becomes far larger due to the increase of each gate area. 
        Patent Reference 1: Japanese Patent Application Laid-open No. 2000-261602     Patent Reference 2: Japanese Patent Application Laid-open No. 2002-218324     Patent Reference 3: Japanese Patent Application Laid-open No. 2000-286706     Patent Reference 4: Japanese Patent Application Laid-open No. 2000-287137        
 
       SUMMARY OF THE INVENTION  
       [0020]     It is an object of the present invention to provide a differential comparator capable of realizing highly accurate analog/digital conversion with the lesser amount of consumption current.  
         [0021]     It is another object of the present invention to provide an analog/digital converter apparatus capable of realizing highly accurate analog/digital conversion with the lesser amount of consumption current.  
         [0022]     It is another object of the present invention to provide an imaging apparatus capable of outputting high quality picture data with the lesser amount of consumption current.  
         [0023]     The first aspect of the present invention is a differential comparator which outputs positive and/or negative logic signals to an output terminal according to the coincidence/non-coincidence of first and second input signal levels inputted to first and second input terminals, respectively.  
         [0024]     The differential comparator comprises an offset cancel function composed of an offset capacitor device provided on the differential comparator side of the first and second terminals, a first switch for short-circuiting the first and second input terminals in such a way as to form a closed loop including the offset capacitor device, and a second switch for short-circuiting both the connection point between the offset capacitor device and the differential comparator, and the output terminal.  
         [0025]     The second aspect of the present invention is an analog/digital converter apparatus which comprises a differential comparator which outputs positive and/or negative logic signal to an output terminal according to the coincidence/non-coincidence of the respective signal levels of an analog signal and a reference signal inputted to first and second input terminals, respectively, and a counter whose start and stoppage is controlled by the logic signal. The analog/digital converter apparatus outputs a value counted by a counter from when an analog signal is inputted as a trigger until the analog signal coincides with a reference signal.  
         [0026]     The differential comparator comprises an offset cancel function composed of an offset capacitor device provided on the differential comparator side of the first and second terminals, a first switch for short-circuiting the first and second input terminals in such a way as to form a closed loop including the offset capacitor device, and a second switch for short-circuiting both the connection point between the offset capacitor device and the differential comparator, and the output terminal.  
         [0027]     The third aspect of the present invention is an imaging apparatus which comprises reading circuits each composed of a pixel array, a plurality of pixel units of which, including an photoelectric conversion device are two-dimensionally arrayed in the row and column directions, and an analog/digital converter for converting an optical/electrical conversion signal outputted from each pixel unit into a digital signal.  
         [0028]     The analog/digital converter comprises a differential comparator which outputs positive and/or negative logic signal to an output terminal according to the coincidence/non-coincidence of the respective signal levels of the photoelectric conversion signal and reference signal inputted to first and second input terminals, respectively, and an offset cancel function composed of an offset capacitor device provided on the differential comparator side of the first and second terminals, a first switch for short-circuiting the first and second input terminals in such a way as to form a closed loop including the offset capacitor device, and a second switch for short-circuiting both the output terminal and the first input terminal provided with the offset capacitor device.  
         [0029]     According to the first and second aspects of the present invention, a capacitor device for signal is connected to the first input terminal to which an analog signal is inputted as a first input signal. At the same time an analog signal is inputted to this first input terminal, the first and second switches of the offset cancel function are closed, and the offset voltage of the differential comparator is stored in the offset capacitor device. Then, the first and second switches are opened. Then, when inputting a reference signal, such as a ramp waveform signal or the like, to the second input terminal as a second input signal and comparing the analog signal on the first input terminal with the reference signal, potential on the first input terminal side to which the analog signal stored in the capacitor device for signal is inputted is made constant by the offset voltage stored in the offset capacitor device. Therefore, the level of the inputted analog signal is not fluctuated by the parasitic capacitance or the like, unlike when using an inverter, and the analog signal can be accurately compared with the ramp waveform signal. Accordingly, the digitalization accuracy of an analog signal based on the relevant comparison can be improved.  
         [0030]     In the differential comparator, since the respective comparison operations of the first and second input terminals do not depend on the amount of current, consumption current can be suppressed without increasing parasitic capacitance, and accordingly, a highly accurate analog/digital conversion process can be performed with the less amount of consumption current.  
         [0031]     According to the third aspect of the present invention, by constituting an analog/digital converter provided for the optical/electrical conversion signal reading circuit of an imaging apparatus of a differential comparator and by providing an offset cancel function, the digitization process of photoelectric conversion signals can be performed using a reference signal, such as a ramp waveform signal or the like, and accordingly, obtained image quality can be improved.  
         [0032]     Since the differential comparator can suppress consumption current without increasing parasitic capacitance, the suppression effect of consumption current is great in a configuration where a lot of analog/digital converters are disposed, such as a case where analog/digital converters are provided for each column of a plurality of pixel units in the CMOS image sensor, as in column ADC. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0033]      FIG. 1  is a block diagram showing the configuration of a chopper type comparator which is the reference technology of the present invention;  
         [0034]      FIG. 2  is a circuit diagram showing the internal composition of the chopper type comparator which is the reference technology of the present invention;  
         [0035]      FIG. 3  is a block diagram showing one configuration of an analog/digital converter apparatus including the differential comparator which is one preferred embodiment of the present invention;  
         [0036]      FIG. 4  is a circuit diagram showing in detail the internal configuration of the analog/digital converter apparatus including the differential comparator which is one preferred embodiment of the present invention;  
         [0037]      FIG. 5  is a block diagram showing one entire configuration of an imaging apparatus including the analog/digital converter apparatus including the differential comparator which is one preferred embodiment of the present invention; and  
         [0038]      FIG. 6  is a timing chart showing one function of the imaging apparatus including the analog/digital converter apparatus which is one preferred embodiment of the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0039]     The preferred embodiment of the present invention is described below with reference to the drawings.  
         [0040]      FIG. 3  is a block diagram showing one configuration of an analog/digital converter apparatus including the differential comparator which is one preferred embodiment of the present invention.  FIG. 4  is a circuit diagram showing in detail its internal configuration.  FIG. 5  is a block diagram showing one entire configuration of an imaging apparatus including the analog/digital converter apparatus which is one preferred embodiment of the present invention.  
         [0041]     The preferred embodiment is described using a case where the present invention is applied to an imaging apparatus  10  composed of, for example, a CMOS image sensor.  
         [0042]     As shown in  FIG. 5 , the imaging apparatus  10  in this preferred embodiment comprises a pixel array  20  in which a plurality of pixel units  23  are two-dimensionally arrayed along each row  21  and each column  22 , a vertical scan circuit  31  and a horizontal scan circuit  32 .  
         [0043]     Each pixel unit  23  is composed of, for example, a photo diode as a photoelectric conversion device, a transistor for initializing this photo diode, amplifying an output signal and controlling its timing and the like. Each pixel unit  23  is covered with a color filter with one of the three primary colors of light and converts light with each color from optical to electrical.  
         [0044]     The vertical scan circuit  31  controls timing for selecting a plurality of pixel units of the pixel array  20  for each row. The horizontal scan circuit  32  controls timing for individually selecting each pixel unit  23  in the rows  21  for each column.  
         [0045]     In this preferred embodiment, a column CDS circuit  40 , a column AMP circuit  50 , a column ADC circuit  60  (analog/digital converter apparatus) and a latch circuit  70  are provided for each column  22  of the pixel unit  23 .  
         [0046]     The column CDS circuit  40  eliminates noise generated when resetting a photoelectric conversion device in the pixel unit from an optical/electrical conversion signal by a correlation double sampling technology.  
         [0047]     The column AMP circuit amplifies the optical/electrical conversion signal outputted from the column CDS circuit  40 .  
         [0048]     The column ADC circuit  60  digitizes the photoelectric conversion signal, using a ramp waveform signal RampV obtained from a ramp waveform generation circuit  51 , which is described later.  
         [0049]     The latch circuit  70  stores the photoelectric conversion signal after the digital conversion for each row  22  (pixel unit  23 ), and outputs the photoelectric conversion signal to a color processor  80  provided after it in synchronization with a horizontal scan signal outputted from the horizontal scan circuit  32 .  
         [0050]     The color processor  80  has a function to process the digital value of each photoelectric conversion signal of a pixel unit  23  corresponding to each color and to convert and output the photoelectric conversion signal into an image signal with an arbitrary standard, such as YUV, YCbCr, RGB or the like.  
         [0051]     As shown in  FIG. 3  as an example, the column ADC circuit  60  in this preferred embodiment comprises differential comparators  61  and  62  which are connected in double stages in order from the input side to the output side, and an inverter  69 , which is inserted and connected between the output side of the differential comparator  62  and the latch circuit  70 .  
         [0052]     The reference signal input terminal  61   a  of the differential comparator  61  is connected to the ramp waveform generation circuit  51  via a switch  68  (switch S 2 ) and a ramp waveform signal RampV is inputted.  
         [0053]     To the analog signal input terminal  61   b  of the differential comparator  61 , the photoelectric conversion signal  23   a  (ADC-in) is inputted from the pixel unit  23  via switch  67  (switch S 1   x ). For this analog signal input terminal  61   b , a capacitor device for signal  63  (capacitor device for signal C 3 ) is provided in order to store the voltage level of the photoelectric conversion signal  23   a.    
         [0054]     The output terminals  61   c  and  61   d  of the differential comparator disposed at the former stage are connected to the input terminals  62   a  and  62   b , respectively, of the differential comparator  62  disposed at the latter stage with the same positive/negative polarity.  
         [0055]     In this preferred embodiment, the differential comparator  61  comprises an offset cancel function composed of a switch  64  (switch S 1 ) (first switch) for controlling the short-circuiting of its reference signal input terminal  61   a  and the input terminal  62   b , a switch  65  (switch S 1 ) (second switch) for controlling the short-circuiting of the analog signal input terminal  61   b  and the output terminal  61   d  and a capacitor device  66  (capacitor device C 1 ) (offset capacitor device) provided between the short-circuit position of the switch  64  in the analog signal input terminal  61   b  and the short-circuit position of the switch  65 .  
         [0056]     Similarly, the differential comparator  62  disposed at the latter stage comprises an offset cancel function composed of the switch  64   a  (switch S 1 ) (first switch), the switch  65   a  (switch S 1 ) (second switch) and the capacitor device  66   a  (capacitor device C 2 )(offset capacitor device).  
         [0057]     As shown in  FIG. 4 , the differential comparator  61  comprises a pMOS transistor Q 1 , an nMOS transistor Q 2 , a pMOS transistor Q 3 , an nMOS transistor Q 4  and an nMOS transistor Q 5  for collecting and grounding these systems. The respective gates of the pMOS transistor Q 1  and pMOS transistor Q 3  of each system constitute a load resistance by being connected to the source side of the pMOS transistor Q 1 . To the gate of the nMOS transistor Q 2 , the analog signal input terminal  61   b  is connected. To the gate of the nMOS transistor Q 4 , the reference signal input terminal  61   a  is connected. The nMOS transistor Q 5  functions as a constant current source.  
         [0058]     One function of this preferred embodiment is described below with reference to the diagram shown in  FIG. 6  and the like.  
         [0059]     Firstly, in the pixel array  20 , each row  21  is selected by a vertical synchronous signal from the vertical scan circuit  31 , and the photoelectric conversion device of the pixel unit  23  in the relevant row  21  is reset. Then, each pixel unit  23  (column  22 ) in the relevant row  21  is read by a horizontal synchronous signal (column selection output signal) from the horizontal scan circuit  32  one after another.  
         [0060]     Then, reset noise and the like is eliminated from a photoelectric conversion signal  23   a  outputted from one pixel unit  23  (column  22 ) by the column CDS circuit  40 , and the photoelectric conversion signal  23   a  is amplified by the column AMP circuit  50 . Then, the photoelectric conversion signal  23   a  is inputted to the column ADC circuit  60  as ADC-in, and an analog/digital conversion process is applied to it to digitize it.  
         [0061]     Specifically, in the column ADC circuit  60 , the switches S 1  and S 1   x  are closed in synchronization with a column selection output signal, which is the input trigger of the photoelectric conversion signal  23   a , and charge corresponding to the potential level of the arriving photoelectric conversion signal  23   a  is stored in the capacitor device for signal C 3 . Simultaneously, since the input/output sides of the differential comparator  61  (or the differential comparator  62 ) are short-circuited by the switch S 1 , charge corresponding to the potential of the photoelectric conversion signal  23   a  based on the level of the threshold voltage (operation point) of the differential comparator  61  (or the differential comparator  62 ) is stored in the capacitor device C 1 . Thus, potential between points A and E shown in  FIG. 3  becomes the level of the photoelectric conversion signal  23   a  (ADC-in).  
         [0062]     Then, when opening the switches S 1  and S 1   x , closing the switch S 2  and inputting a ramp waveform signal RampV to the reference signal input terminal  61   a  from the ramp waveform generation circuit, the respective potential of points C and D on the output side is inverted to potential the reverse in the case where the photoelectric conversion signal  23   a  has been inputted using the level of ADC-in, and count is started in the counter  71  by the inversion output of the inverter  69 . Then, the moment a gradually decreasing ramp waveform signal RampV intersects with the voltage value of the photoelectric conversion signal  23   a  at point B, the respective potential between points C and E on the output sides of the differential comparators  61  and  62  is inverted, and the count value of the counter  71  is latched by the latch circuit  70  using the inversion output of the inverter  69 . This count value is obtained by converting the photoelectric conversion signal  23   a  into a digital value with prescribed bit width.  
         [0063]     Then, the digital data of the latch circuit  70  is outputted to and processed in the color processor in synchronization with a horizontal synchronous signal.  
         [0064]     As described above, according to the present invention, the threshold voltage, parasitic capacitance and the like of the differential comparator  61  is cancelled by closing the switch S 1  and storing the voltage of the photoelectric conversion signal  23   a  based on the threshold voltage of a transistor constituting the differential comparator  61  when closing the switch S 1   x  and inputting the photoelectric conversion signal  23   a . Therefore, potential point A is fixed. When opening the switches S 1  and S 1   x , closing the switch S 2 , and inputting a ramp waveform signal RampV for comparison, no potential fluctuation at point B is generated due to the charge fluctuation of the capacitor device C 1 , and the photoelectric conversion signal  23   a  can be precisely compared with the ramp waveform signal RampV.  
         [0065]     Accordingly, for example, no gradation, uneven color and the like of a photographed image is generated due to the uneven digital conversion of the photoelectric conversion signal  23   a , and the image quality of the imaging apparatus  10  can be improved.  
         [0066]     Since the differential comparator  61  is operated by the distribution of a specific current value determined by the nMOS transistor Q 5  shared by each input system of the pMOS transistor Q 1 , nMOS transistor Q 2 , pMOS transistor Q 3  and nMOS transistor Q 4 , there is no need to increase the current value to be controlled by the nMOS transistor Q 5 , and accordingly, consumption current can be suppressed. There is also neither need to increase the gate length of a transistor constituting the differential comparator  61  in order to control current nor parasitic capacitance increases.  
         [0067]     Since the column ADC circuit  60  is provided each row  22 , the number of column ADC circuits increases, for example, when the number or density of the pixel units in the pixel array  20  is increased in order to improve resolution. However, by suppressing the consumption current of each column ADC circuit, as in this preferred embodiment, a high-performance imaging apparatus  10  for outputting high-resolution pictures with high quality whose digitization accuracy in the column ADC circuit  60  is excellent can be realized with low consumption current (power).  
         [0068]     The present invention is not limited to the above-mentioned preferred embodiment, and its variations and modifications are also possible as long as the subject matter of the present invention is not deviated.  
         [0069]     According to the present invention, a differential comparator capable of realizing highly accurate analog/digital conversion with the lesser amount of consumption current can be provided.  
         [0070]     An analog/digital conversion apparatus capable of realizing highly accurate analog/digital conversion with the lesser amount of consumption current can also be provided.  
         [0071]     An imaging apparatus capable of outputting high-quality picture data with the lesser amount of consumption current can also be provided.