Abstract:
A method of forming a field effect transistor (FET) capacitor includes forming a channel region; forming a gate stack over the channel region; forming a first extension region on a first side of the gate stack, the first extension region being formed by implanting a first doping material at a first angle such that a shadow region exists on a second side of the gate stack; and forming a second extension region on the second side of the gate stack, the second extension region being formed by implanting a second doping material at a second angle such that a shadow region exists on the first side of the gate stack.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS AND PRIORITY CLAIM 
     This application is a Continuation of U.S. patent application Ser. No. 12/616,861, filed Nov. 12, 2009, the disclosure of which is incorporated by reference herein in its entirety. 
    
    
     BACKGROUND 
     The present invention relates to energy storage devices, and more specifically, to field effect transistor (FET) capacitors. 
     In silicon on insulator (SOI) technologies, creating a decoupling FET capacitor is a known process. Typically, creating a decoupling FET capacitor includes creating source and drain regions adjacent a channel. The source and drain are both typically doped in the same manner. For example, both the source and drain could be N+ doped or both are P+ doped. Such doping works fine for a unidirectional capacitor. 
     Building a capacitor, however, that would work in both bias directions is not straightforward. Such a capacitor would need to be able to store charge regardless of whether V dd  or a reference voltage (ground) is applied to the gate of the de-coupling capacitor. For a capacitor to work in accumulation mode in SOI, a body tie is required, and this would normally have problems with parasitic resistances and capacitances that would limit the operation. 
     SUMMARY 
     According to one embodiment of the present invention, a method of forming a field effect transistor (FET) capacitor is disclosed. The method includes forming a channel region; forming a gate stack over the channel region; forming a first extension region on a first side of the gate stack, the first extension region being formed by implanting a first doping material at a first angle such that a shadow region exists on a second side of the gate stack; and forming a second extension region on the second side of the gate stack, the second extension region being formed by implanting a second doping material at a second angle such that a shadow region exists on the first side of the gate stack. 
     According to one embodiment of the present invention, a method of forming a field effect transistor (FET) capacitor is disclosed. The method includes forming an initial workpiece including a substrate, a insulator and a silicon layer on top of the substrate, the silicon layer having an upper surface; forming a gate stack on the upper surface; orienting the workpiece relative to a dopant material source in a first orientation such that first shadow region exist on a first side of the gate stack; implanting a first dopant material at the first orientation; orienting the workpiece relative to a dopant material source in a second orientation such that second shadow region exist on a second side of the gate stack; and implanting a second dopant material at the second orientation. 
     According to one embodiment of the present invention, a field effect transistor (FET) capacitor is disclosed. The FET capacitor includes a gate stack, a drain on a first side of the gate stack and a source on a second side of the gate stack. The drain includes a first dopant material and the source includes a second dopant material different than the first dopant material. 
     Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the advantages and the features, refer to the description and to the drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which: 
         FIG. 1  shows a structure at one point in the process flow of forming a bi-directional capacitor according to one embodiment of the present invention; 
         FIG. 2  shows the structure of  FIG. 1  after a gate stack has been added; 
         FIG. 3  shows the structure of  FIG. 3  after a first extension region has been formed; 
         FIG. 4  shows the structure of  FIG. 4  after a second extension region has been formed on an opposite side of the gate stack than the first extension region; 
         FIG. 5  shows structure of  FIG. 4  after a spacer has been added around the gate stack and the first extension has been increased in size; and 
         FIG. 6  shows the structure of  FIG. 5  after the second extension has been increased in size. 
     
    
    
     DETAILED DESCRIPTION 
     One possible solution to the problems described above and which is disclosed herein is to alternate the carrier type in the diffusion regions in a FET capacitor array. That is, after the gate is formed, the source may be P+ doped and the drain N+ doped (or vice versa). Such a configuration would allow for high frequency switching because both accumulation and inversion have a particular diffusion region to draw either electrons or holes from. Without having both P+ and N+ regions, the FET capacitor would operate quickly in one voltage setting and slow in the other. As such, it may not be useful in a high frequency setting. 
     Such a solution, however, may require utilizing a non self-aligned blocking mask over the gate of the capacitor, which would limit how small the gate length of such a structure could be. In turn, the frequency response of the FET capacitor is a function of the gate length. This is because the carriers to form either an inversion layer or an accumulation layer must be supplied from either an N+ or P+ diffusion node and then propagate along the channel length. 
     Typically, doping diffusion nodes that form a source and drain is done in a vertical orientation. According to one embodiment, the doping is done at an angle and the gate itself forms the mask as it blocks the impingement of the doping molecules from either the source or drain as desired. Utilizing the gate as a mask in this manner allows for the creation of a self-aligned FET capacitor structure with alternating N+/P+ diffusion contacts. Since this structure is self-aligned, it may be scaled to shorter lengths and, thus, have higher frequency response. 
       FIG. 1  shows a structure  100  at one point in the process flow of forming a bi-directional capacitor according to one embodiment of the present invention. The structure  100  includes a substrate  102 . The substrate  102  may be formed of any material but, in one embodiment, is formed of silicon or a silicon based material. An insulating layer  104  is disposed on top of the substrate  102 . The insulating layer  104  may be formed of any electrical insulator. In one embodiment, the insulating layer  104  is formed of a nitride. In another embodiment, the insulating layer  104  is a Buried OXide (BOX) layer. 
     A silicon layer  106  is formed on top of the insulating layer  104 . The combination of the substrate  102 , the insulating layer  104  and the silicon layer  106 , form a typical silicon-on-insulator (SOI) structure. The use of an SOI structure in place of conventional silicon substrate in semiconductor manufacturing, especially microelectronics, reduces parasitic device capacitance and, thereby, improves performance. 
     The silicon layer  106  is divided into multiple active regions  110  by one or more isolation regions  108 . In one embodiment, the isolation regions  108  are shallow trench isolation (STI) regions. The number of isolation regions  108  is variable. As shown, there are two active regions, a first active region  110   a  and a second active region  110   b . Of course, the number of active regions  110  is variable. 
       FIG. 2  shows the structure of  FIG. 1  after a gate stack  202  over the active regions. Each gate stack  202  may include a dielectric layer  204 . In one embodiment, the dielectric layer  204  is a high-k dielectric. Each gate stack  202  may also include a gate  206  formed on top of the dielectric layer  204 . As shown, there are two gate stacks  202   a  and  202   b  but this number is not limiting. In one embodiment, the gate  206  is formed of a metal. Each gate stack  202  may also include a polysilicon layer  208  formed on top of the gate  206 . Each gate stack  202  may also include initial spacers  210  that protect the dielectric layer  204 , the gate  206  and the polysilicon layer  208  from future processing steps. Each gate stack  202  may a height, h. In one embodiment, h is the same for all of the gate stacks but this is not required. 
       FIG. 3  shows the structure (workpiece  300 ) of  FIG. 2  after a channel halo  112  formed therein has been formed below the gate stacks  202 . The channel halos  112  may be formed in a conventional manner. The channel halos  112  may be formed be formed as either N-type or P-type regions. As shown, each gate stack ( 202   a  and  202   b ) includes a halo  112   a  and  112   b , respectively, formed beneath it. 
     In addition, workpiece  300  includes a P-type extensions  302  formed on one side of one or more of the gate stacks  202 . In one embodiment, the implant material source (not shown) and the workpiece  300  are arranged such that the implant material delivered is not delivered directly down on an upper surface of the workpiece  300 . For example, the implant material may be directed as shown by first implant arrows  306 . 
     Because the implant arrows  306  are offset from vertical by an angle θ 1  a shadow region  304  is formed on a side of the gate stack  202  opposite the side contacted by incoming implant material. In this manner, the angle θ 1  and the height of the gate stack define a mask. These two variables may be finely tuned. In this example, the first implant arrows  306  indicate that a P-type material is being deposited. 
       FIG. 4  shows the structure (workpiece  400 ) of  FIG. 3  after an N-type extension  402  has been formed on one side of one or more of the gate stacks  202 . In one embodiment, the implant material source (not shown) and the workpiece  400  are arranged such that the implant material is not delivered directly down on an upper surface of the workpiece  400 . For example, the implant material may be directed as shown by second implant arrows  406 . Because the implant arrows are offset from vertical by an angle α a shadow region  404  is formed on a side of the gate stack  202  opposite the side contacted by incoming implant material. In this manner, the angle α 1  and the height of the gate stack define a mask. In this example, the first implant arrows  406  indicate that a N-type material is being deposited. In one embodiment, α 1  is an opposite and equal angle to θ 1  ( FIG. 3 ). 
       FIG. 5  shows the structure of  FIG. 4  after spacers  501  have been formed around the gate stacks  200 . The spacers  501  may, in one embodiment, may cover the P-type extensions  302  and the N-type extensions  304 . After the spacers are formed, the first implant material is again applied at second angle θ 2  to create a P region  502  that extends from an upper surface of the workpiece to the insulating layer  104 . For example, the implant material may be directed as shown by third implant arrows  506 . In one embodiment, θ 2  and θ 1  are equal but that is not required. 
       FIG. 6  shows the structure of  FIG. 5  the second implant material is again applied at angle α 2  to create an N region  602  that extends from an upper surface of the workpiece to the insulating layer  104 . For example, the implant material may be directed as shown by fourth implant arrows  606 . In one embodiment, α 2  and α 1  are equal but that is not required. In one embodiment, α 2  is an opposite and equal angle to θ 2  ( FIG. 5 ). 
     As discussed above, the incident angle of the implant material is shifted from the typical vertical orientation with respect to the workpiece. In one embodiment, the angle θ 1  may be 20 degrees. In one embodiment, the angles θ 1  and θ 2  may vary from 1 to 89 degrees. Similarly, in one embodiment, the angle α 1  may be 20 degrees. In one embodiment, the angles α 1  and α 2  may vary from 1 to 89 degrees. 
     It shall be understood that known silicide processes may be applied to the structure of  FIG. 6  to create contacts. These contacts may allow the resulting structure to be used as a bidirectional FET capacitor. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one ore more other features, integers, steps, operations, element components, and/or groups thereof. 
     The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated 
     The flow diagrams depicted herein are just one example. There may be many variations to this diagram or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention. 
     While the preferred embodiment to the invention had been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.