Abstract:
A flash memory device includes a write driver for driving a data line according to data to be written to a flash memory cell during a program period, a sense amplifier circuit for sensing and amplifying the data stored in the flash memory cell during a program verify period, and an isolation circuit for electrically isolating the sense amplifier circuit from the data line during an operation period of the write driver. Another embodiment includes a second isolation circuit adapted to isolating the write driver from the data line during the program verify period, reducing the load on the sense amplifier, and thus enhancing operating speed.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims the priority of Korean Patent Application No. 2003-83553, filed Nov. 24, 2003 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a memory device and, more particularly, to a flash memory device.  
         [0004]     2. Description of the Related Art  
         [0005]     Generally, a semiconductor integrated circuit device performs internal operations using an externally supplied power supply voltage. Further, the semiconductor integrated circuit device generates a higher voltage than the externally supplied power voltage therein, and performs the internal operations using the higher voltage. For example, in a semiconductor integrated circuit device using a higher voltage than 3.3V, a MOS transistor in an area of a circuit operating with a power supply voltage (hereinafter referred to as “low voltage circuit area”) has a high breakdown voltage level that allows the transistor to withstand a higher voltage generated therein. In this case, a circuit area operating with a high voltage (hereinafter referred to as “high voltage circuit area”) may be directly connected to the low voltage circuit area. Although the high voltage circuit area is directly connected to the low voltage circuit area, the MOS transistor of the low voltage circuit area does not reach breakdown by the high voltage from the high voltage circuit area. This is because the MOS transistor of the low voltage circuit area has a breakdown voltage even higher than the high voltage.  
         [0006]     As power supply voltages drop and the integration density of semiconductor integrated circuit devices increase, MOS transistors in a low voltage circuit area tend to be of low voltage, with a high current capacity, occupying a smaller area. Thus, breakdown voltages of these MOS transistors of the low voltage circuit area also decrease. In the case where the breakdown voltage of these low voltage transistors is lower than the high voltage used in the high voltage circuit area, these low voltage transistors in the low voltage circuit area may experience breakdown by the high voltage from the high voltage circuit area when the low voltage circuit area is directly connected to the high voltage circuit area.  
       SUMMARY OF THE INVENTION  
       [0007]     A feature of the present invention is to provide a flash memory device that prevents program failure caused by the breakdown of any low voltage transistor.  
         [0008]     Another feature of the present invention is to prevent the high voltage supplied to a bit line from dropping during a program operation.  
         [0009]     According to an aspect of the present invention, a semiconductor integrated circuit device comprises a high voltage circuit, a low voltage circuit, an internal circuit, and a first isolation circuit. The high voltage circuit operates with a high voltage, and the low voltage circuit operates with a low voltage. The internal circuit is connected to the high and low voltage circuits through a signal line. The first isolation circuit is coupled between the signal line and the low voltage circuit to electrically isolate the low voltage circuit from the signal line during an operation period of the high voltage circuit. The first isolation circuit includes a MOS transistor having a breakdown voltage higher than the high voltage. A higher voltage than the high voltage is applied to the gate of the MOS transistor during an operation period of the low voltage circuit.  
         [0010]     In an exemplary embodiment of the present invention, the semiconductor integrated circuit device further comprises a second isolation circuit that is coupled between the signal line and the high voltage circuit to electrically isolate the high voltage circuit from the signal line during the operation period of the low voltage circuit. The second isolation circuit includes a MOS transistor having a breakdown voltage higher than the high voltage. A higher voltage than the high voltage is applied to the gate of the MOS transistor during the operation period of the high voltage circuit.  
         [0011]     According to another aspect of the present invention, a flash memory device comprises a flash memory cell, a bit line connected to the flash memory cell, a switch circuit for connecting the bit line to a data line, a write driver for driving the bit line with a high voltage according to data to be stored in the flash memory cell, a first sense amplifier circuit for sensing data stored in the flash memory cell through the bit line, and a first isolation circuit for isolating a second sense amplifier circuit from the data line during an operation period of the write driver. The write driver is connected to the data line, and the second sense amplifier circuit is connected to the data line through the first insulation circuit. The first isolation circuit includes an NMOS transistor having a breakdown voltage higher than the high voltage. A higher voltage than the high voltage is applied to a gate of the NMOS transistor during an operation period of the write driver. The voltage applied to the gate of the NMOS transistor is a program voltage.  
         [0012]     In this embodiment, the flash memory device further comprises a second isolation circuit for isolating the write driver from the data line during an operation period of the sense amplifier circuit. The second isolation circuit includes an NMOS transistor having a breakdown voltage higher than the high voltage. A higher voltage than the high voltage is applied to a gate of the NMOS transistor during an operation period of the sense amplifier circuit. The voltage applied to the gate of the NMOS transistor is a program voltage.  
         [0013]     According to still another aspect of the present invention, a flash memory device comprises sectors each including local bit lines, a column selection circuit for selecting one of the sectors to connect bit lines of the selected sector to corresponding global bit lines respectively, a first switch circuit for connecting the global bit lines to data lines during program operation, a write driver circuit for driving the data lines with a high voltage according to data to be stored in the selected sector during the program operation, a sense amplifier circuit for sensing data stored in the selected sector through the data lines and the selected bit lines during a program verify operation, a second switch circuit coupled between the data lines and the sense amplifier circuit, and a control circuit for controlling the second switch circuit to isolate the sense amplifier circuit from the data lines during the program operation. Flash memory cells are connected in parallel to the respective local bit lines.  
         [0014]     In this embodiment, the second switch circuit includes NMOS transistors each being coupled between the data lines and the sense amplifier circuit and each of the NMOS transistors has a breakdown voltage higher than the high voltage.  
         [0015]     In this embodiment, a higher voltage than the high voltage is applied to the gates of the NMOS transistors during the program verify operation. The voltage applied to the gates of the respective NMOS transistors is a program voltage.  
         [0016]     Also, in this embodiment, the flash memory device further comprises a third switch circuit coupled between the data lines and the write driver circuit. The control circuit controls the third switch circuit to isolate the write driver circuit from the data lines during the program verify operation. The third switch circuit includes NMOS transistors coupled between the data lines and the write driver circuit and each of the NMOS transistors has a breakdown voltage higher than the high voltage.  
         [0017]     According to another aspect of the present invention, a flash memory device comprises sectors each including local bit lines, a column selection circuit for selecting one of the sectors to connect bit lines of the selected sector to corresponding global bit lines respectively, a first switch circuit for connecting the global bit lines to first data lines during a program operation, a second switch circuit for connecting the global bit lines to second data lines during a read operation, a write driver circuit for driving the data lines with a high voltage according to data to be stored in the selected sector during the program operation, a first sense amplifier circuit for sensing data stored in the selected sector through the first data lines and the selected bit lines during a program verify operation, a second sense amplifier circuit for sensing data stored in the selected sector through the second data lines and the selected bit lines during the read operation, a third switch circuit coupled between the data lines and the sense amplifier circuit, and a control circuit for controlling the third switch circuit to isolate the sense amplifier circuit from the first data lines during the program operation and controlling the fourth switch circuit to isolate the write driver from the first data lines during the program verify operation. Flash memory cells are connected in parallel to the respective local bit lines 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]     These and other objects and features of the present invention will become clear from the following description, taken in conjunction with the preferred embodiments with reference to the accompanying drawings in which:  
         [0019]      FIG. 1  is a block diagram of a flash memory device according to a first embodiment of the present invention;  
         [0020]      FIG. 2  is a circuit diagram of the sense amplifier circuit shown in  FIG. 1 ;  
         [0021]      FIG. 3  is a circuit diagram of the write driver circuit shown in  FIG. 1 ;  
         [0022]      FIG. 4  is a circuit diagram of the control circuit shown in  FIG. 1 ;  
         [0023]      FIG. 5  is a circuit diagram of the isolation circuit and the column selection circuit shown in  FIG. 1 ;  
         [0024]      FIG. 6  is a block diagram of a flash memory device according to a second embodiment of the present invention.  
         [0025]      FIG. 7  is a circuit diagram of the control circuit shown in  FIG. 6 ; and  
         [0026]      FIG. 8  is a circuit diagram of the isolation circuits and column selection circuits shown in  FIG. 6 . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0027]     In the  FIGS. 2-5  and  7 - 8  transistor symbols drawn with thick lines represent high voltage transistors having a high breakdown voltage. Otherwise the transistors have a low breakdown voltage, as described herein.  
         [0028]     Referring to  FIG. 1 , a flash memory device  100  according to the present invention includes a sector  110  for storing data information therein. A plurality of bit lines (or local bit lines) LBL 0 -LBLm are connected to the sector  110 . A plurality of flash memory cells (not shown) are connected in parallel to the respective bit lines. Each of the flash memory cells includes a floating gate transistor having a control gate, a floating gate, a source, and a drain. It will be understood that the flash memory device  100  is a NOR flash memory device but the spirit of the present invention is not limited thereto. A column decoder circuit  120  receives a column address and generates column selection signals YA, YBR, and YBW in response to flag signals READ and PGM from a program/read control circuit  130 . For example, the column decoder circuit  120  generates the column selection signals YA based on an input column address irrespective of the flag signal READ and PGM during a program/read operation. On the other hand, the column decoder circuit  120  generates the column selection signals YBR in response to activation of the flash signal READ (or during a read operation). The column decoder circuit  120  generates the column selection signals YBW in response to activation of the flag signal PGM (or during a program operation).  
         [0029]     A column selection circuit  140  selects a part of the bit lines LBL 0 -LBLm in response to the column selection signals YA from the column decoder circuit  120  and connects the selected bit lines to global bit lines GBL 0 -GBLn, respectively. A column selection circuit  150  selects a part of the global bit lines GBL 0 -GBLn in response to the column selection signals YBR outputted from the column decoder circuit  120  and connects the selected global bit lines to corresponding data lines DLRi, respectively. The column selection circuit  150  selects a part of the global bit lines GBL 0 -GBLn in response to the column selection signals YBW outputted from the column decoder circuit  120  and connects the selected global bit lines to corresponding data lines DLWi, respectively. Namely, the column selection circuit  150  connects the data lines DLRi to the selected global bit lines during the read operation and connects the data lines DLWi to the selected global bit lines during the program operation. In this embodiment, the data lines DLRi are used in the read operation and the data lines DLWi are used in the program operation.  
         [0030]     A sense amplifier circuit (SAR)  160  is connected to the data lines DLRi and includes sense amplifiers each corresponding to the data lines DLRi. The sense amplifier  160  senses data from flash memory cells of the selected local bit lines through the column selection circuits  140  and  150  during a read operation. In this embodiment, the sense amplifier circuit  160  operates only during the read operation. A write driver circuit (WD)  170  includes a plurality of write drivers that are connected to the data lines DLWi, respectively. The write driver circuit  170  operates in response to a main program signal MAINPGM from the program/read control circuit  130  and drives the data lines DLWi with a high voltage/ground voltage according to data to be stored in the sector  110 . It is well known that in a NAND flash memory device, a program operation is performed through program cycles which include a program period and a program verify period, respectively. In this case, the main program signal MAINPGM indicates a program period of each program cycle.  
         [0031]     The flash memory device  100  further includes a control circuit  180 , a sense amplifier circuit (SAW)  190 , and an isolation circuit  200 . The control circuit  180  controls the isolation circuit  200  such that the sense amplifier circuit  190  is electrically isolated from the data lines DLWi during an operation period of the write driver circuit  170 . The sense amplifier circuit  190  includes sense amplifiers each corresponding to the data lines DLWi and is used only during the program verify operation. A preferred embodiment of the sense amplifier circuit  190  is illustrated in  FIG. 2 . Since the layout area of the sense amplifier circuit  190  is large, the sense amplifier circuit  190  includes low voltage transistors that have a high current capacity and occupy a small area. The low voltage transistors are transistors each having a low breakdown voltage (e.g., 4V or lower).  
         [0032]     Returning to  FIG. 1 , the control circuit  180  generates a control signal nMAINPGM in response to the program/read control circuit  130 . For example, when a main program signal MAINPGM is activated, i.e., during an operation period (or program period) of the write driver circuit  170 , the control circuit  180  generates the control signal nMAINPGM to deactivate the isolation circuit  200 . That is, the sense amplifier circuit  190  is electrically isolated from the data lines DLWi during a non-operation period (or program verify period) of the write driver circuit  170 . In this embodiment, when the main program signal MAINPGM is deactivated, the control signal nMAINPGM has a high voltage HV 2  from a high voltage generation circuit  210 .  
         [0033]     In brief, when the write driver circuit  170  operates, the data lines DLWi are driven with a high voltage HV 1  (e.g., 5-6V) according to data to be written.  
         [0034]     In the case where the isolation circuit  200  does not exist, as in the old art, the high voltage applied to the data lines DLWi is directly applied to the sense amplifier circuit  190  acting as a low voltage circuit operating with a low voltage. That is, since the write driver circuit  170  and the sense amplifier circuit  190  share the data lines DLWi, MOS transistors (e.g., LM 11 , LM 12 , and LM 15  of  FIG. 2 ) constituting the sense amplifier circuit  190  experience breakdown by the high voltage HV 1  applied to the data lines DLWi. Thus the high voltage HV 1  applied to the data lines DLWi causes breakdown of the transistors, resulting in failure of the program operation.  
         [0035]     But in the case of the present invention, where the isolation circuit  200  is constructed between the data lines DLWi and the sense amplifier circuit  190 , the foregoing problem may be solved. Namely, the isolation circuit  200  is controlled by the control circuit  180  such that the sense amplifier circuit  190  is electrically isolated from the data lines DLWi during the operation period of the write driver circuit  170 . This means that the high voltage HV 1  on the data lines DLWi is not applied to the sense amplifier circuit  190  during the operation period (or program period) of the write driver circuit  170 . Therefore, it is possible to prevent a high voltage breakdown of the low voltage transistors from the sense amplifier circuit. As a result, the program operation may be normally carried out.  
         [0036]      FIG. 3  is a circuit diagram of the write driver circuit shown in  FIG. 1 . Although a write driver connected to only one data line (e.g., DLW 0 ) is illustrated in  FIG. 3 , write drivers respectively connected to the other data lines have the same configuration as shown in  FIG. 3 .  
         [0037]     Referring to  FIG. 3 , the write driver circuit  170  includes a PMOS transistor HM 1  and NMOS transistors HM 2  and HM 3 . The PMOS transistor HM 1  is coupled between a high voltage HV 1  and a data line DLW 0  and is controlled by a data signal nBLSEL 0 . The NMOS transistors HM 2  and HM 3  are serially coupled between the data line DWL 0  and a ground voltage VSS. The NMOS transistor HM 2  is controlled by a main program signal MAINPGM, and the NMOS transistor HM 3  is controlled by the data signal nBLSEL 0 . The data signal nBLSEL 0  indicates data to be programmed, and the main program MAINPGM indicates a program period.  
         [0038]     In this embodiment, the MOS transistors HM 1 , HM 2 , and HM 3  constituting the write driver circuit  170  are high voltage transistors each having a breakdown voltage (e.g., 9V or higher) higher than the high voltage HV 1 .  
         [0039]     In the circuit operation, the data line DLW 0  is maintained in a floating state while the program operation is not performed (i.e., when the main program signal MAINPGM is low). When the program operation is performed (i.e., the main program signal MAINPGM is high), the data line DLW 0  is driven with the high voltage HV 1  or the ground voltage VSS according to the data signal nBLSEL 0 . For example, when the data signal nBLSEL 0  is low, the write driver circuit  170  supplies the high voltage HV 1  to the data line DLW 0 . When the data signal nBLSEL 0  is high, the write driver circuit  170  supplies the ground voltage VSS to the data line DLW 0 .  
         [0040]     Referring to  FIG. 4 , the control circuit  180  outputs a control signal nMAINPGM of the ground voltage VSS when the main program signal MAINPGM is high. The control circuit  180  outputs a control signal nMAINPGM of a high voltage HV 2  when the main program signal MAINPGM is low. The control circuit  180  includes PMOS transistors HM 4 , HM 5 , and HM 8 , MOS transistors HM 6 , HM 7 , and HM 9 , and an inverter INV 4 , which are connected as shown in this figure. The control circuit  180  acts as a level shifter, and the MOS transistors HM 4 -HM 9  are high voltage transistors each having a breakdown voltage (e.g., 9V or higher) higher than the high voltage HV 1 . The high voltage HV 2  is supplied from the high voltage generation circuit  210 , as shown in  FIG. 1 , and is the voltage supplied to a wordline or higher voltage there than during a program operation.  
         [0041]      FIG. 5  is a circuit diagram of the isolation circuit and the row-column selection circuit shown in  FIG. 1 . Referring to  FIG. 5 , in the isolation circuit  200 , an NMOS transistor HM 10  connected to only one data line DLW 0  is illustrated. The NMOS transistor HM 10  of the isolation circuit  200  is coupled between the data line DLW 0  and the sense amplifier circuit  190  and is controlled by the control signal nMAINPGM from the control circuit  180 . The NMOS transistor HM 10  is a high voltage transistor having a breakdown voltage (e.g., 9V or higher) higher than the high voltage HV 1 . The data line DLW 0  is connected to the local bit line LBL 0  through NMOS transistors ST 1  and ST 2  when column selection signals YA and YBW are activated.  
         [0042]     When the control signal nMAINPGM has a low level of a ground voltage or during an operation period of the write driver circuit  170 , the NMOS transistor HM 10  of the isolation circuit  200  is turned off to electrically isolate the sense amplifier circuit  190  from the data line DWL 0 . During the operation period of the write driver circuit  170  (or while the program operation is performed), the sense amplifier circuit  190  is electrically isolated from the data line DLW 0 . Therefore, it is possible to prevent breakdown of the MOS transistors of the sense amplifier circuit  190  (e.g., MOS transistors LM 11 , LM 12 , and LM 15  of  FIG. 2 ) by the high voltage of the data line DLW 0 . As a result, program failure may be prevented.  
         [0043]     When the control signal nMAINPGM has a high level of the high voltage HV 2  or during a non-operation period (program verify period) of the write driver circuit  170 , the NMOS transistor HM 10  of the isolation circuit  200  is turned on. Thus, the sense amplifier circuit  190  senses a voltage (or cell current) of the data line DLW 0  connected to a flash memory cell MC through NMOS transistors ST 1  and ST 2 .  
         [0044]     A flash memory  300  device according to a second embodiment of the present invention is illustrated in  FIG. 6 . Referring to  FIG. 6 , the flash memory  300  is substantially identical to the flash memory device  100  shown in  FIG. 1  except that the flash memory device  300  further includes an isolation circuit  420 . The isolation circuit  420  electrically isolates the write driver circuit  370  from data lines DLWi in response to the control signal MAINPGM′ from the control circuit  380 , which means that input loading of the sense amplifier circuit  390  is reduced. Thus the sense amplifier circuit  390  performs a sensing operation at a higher speed.  
         [0045]     Referring to  FIG. 7 , the control circuit  380  outputs a control signal nMAINPGM of a ground voltage VSS and a control signal MAINPGM′ of a high voltage HV 2  when a main program signal MAINPGM is high. The control circuit  380  outputs a control signal nMAINPGM of the high voltage HV 2  and a control signal MAINPGM′ of the ground voltage VSS when the main program signal MAINPGM is low. The control signal includes PMOS transistors HM 11 , HM 12 , HM 15 , and HM 17 , NMOS transistors HM 13 , HM 14 , HM 16 , and HM 18 , and an inverter INV 5 , which are connected as shown in this figure. The control circuit acts as a level shifter, and the MOS transistors HM 11 -HM 18  are high voltage transistors each having a breakdown voltage (e.g., 9V or higher) higher than the high voltage HV 1 .  
         [0046]     Referring to  FIG. 8 , an NMOS transistor HM 19  of the isolation circuit  400  is coupled between the data line DLW 0  and the sense amplifier circuit  390  and is controlled by the control signal nMAINPGM from the control circuit  380 . An NMOS transistor HM 20  of the isolation circuit  420  is coupled between the data line DLW 0  and the write driver circuit  370  and is controlled by the control signal MAINPGM′ from a control circuit  380 . The NMOS transistors are high voltage transistors each having a breakdown voltage (e.g., 9V or higher) higher than a high voltage HV 1 . The data line DLW 0  is connected to a local bit line LBL 0  through the NMOS transistors ST 3  and ST 4  when column selection signals YA and YBW are high.  
         [0047]     During an operation period of the write driver circuit  370 , i.e., when the control signal nMAINPGM has a low level of the ground voltage and the control signal MAINPGM′ has a high level of the high voltage HV 2 , the NMOS transistor HM 19  of the isolation circuit  400  is turned off and the NMOS transistor HM 20  of the isolation circuit  420  is turned on. As the NMOS transistor HM 20  is turned on, the write driver circuit  370  drives the data line DLW 0  with the high voltage HV 1  or the ground voltage VSS according to data to be programmed. On the contrary, since the NMOS transistor HMl 9  is turned off, the sense amplifier circuit  390  is electrically isolated from the data line DLW 0 . During the operation period of the write driver circuit  370  (or while the program operation is performed), the sense amplifier circuit  390  is electrically isolated from the data line DLW 0 . Therefore, it is possible to prevent the MOS transistor of the sense amplifier circuit  390  (e.g., MOS transistors LM 11 , LM 12 , and LM 15  of  FIG. 2 ) from experiencing breakdown by the high voltage of the data line DLW 0 . As a result, a program failure caused by reduction of the high voltage of the data line DLW 0  is prevented.  
         [0048]     During the operation period of the sense amplifier circuit  390 , i.e., when the control signal MAINPGM′ has a low level of the ground voltage and the control signal nMAINPGM has a high level of the high voltage HV 2 , the NMOS transistor HM 19  of the isolation circuit  400  is turned on and the NMOS transistor HM 20  of the isolation circuit  420  is turned off. As the NMOS transistor HM 19  is turned on, the write driver circuit  370  is electrically isolated from the data line DLW 0 . In other words, during the operation period of the sense amplifier circuit  390  (while a program verify operation is performed), the write driver circuit  370  is electrically isolated from the data line DLW 0 . Therefore, input loading of the sense amplifier circuit  390  is reduced to enable the sense amplifier circuit  390  to perform the sensing operation at a higher speed.  
         [0049]     In summary, according to the present invention, a sense amplifier circuit for verifying a program constitutes a low voltage circuit operating with a low voltage, and a write driver circuit constitutes a high voltage circuit operating with a high voltage.  
         [0050]     When the write driver circuit operates, the sense amplifier circuit for verifying a program is electrically isolated from a data line to prevent MOS transistors of the sense amplifier circuit from experiencing breakdown by the high voltage of the data line. Thus, a program failure can be prevented. When the sense amplifier circuit operates, the write driver circuit is electrically isolated to reduce the loading applied to the sense amplifier circuit. Thus, the operation speed of the sense amplifier circuit can be enhanced.  
         [0051]     Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement, which is calculated to achieve the same purpose, may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.