Abstract:
A Content Addressable Memory (CAM) cell is disclosed having an physical implementation of transistors for improving the semiconductor substrate area utilization of the CAM cell and the CAM array. The CAM cell comprises a first and second memory circuit and a compare circuit. The compare circuit of six transistors formed over two active regions. The local interconnect between the compare circuit and the first memory circuit formed of a polysilicon region. The local interconnect between the compare circuit and the second memory circuit formed of polysilicon and conductive regions.

Description:
FIELD OF THE INVENTION 
     The present invention relates to content addressable memory (CAM) cell. More specifically, this invention relates to the structures and methods for improving area utilization of semiconductor substrate in a CAM cell. 
     BACKGROUND OF THE INVENTION 
     In the communication industry, there is often a need for determining associative relationships between a first data element and a second data element. To meet this need, a Content Addressable Memory (CAM) is used to make a comparison of an input data value and a stored data value in the CAM cell. For example, the input data value could be a packet header containing the address of a computer in a network of computers. The stored data values could be all the addresses of the computers within the network. A CAM cell array contained within a network router would determine whether there is an association between the address in the packet header and the addresses of the computers in the network. In determining the association, a search and comparison method must be performed between the address in the packet header and all the addresses in the network. This search and comparison method is both time and resource intensive using a traditional solutions consisting of RAM, CPU and software algorithm. Further, with large input data words such as 32 and 64 bits, the search and comparison method using traditional solutions is less efficient than a CAM cell array. Content Addressable Memories provide a solution for fast search and compare operations. 
     Generally a CAM cell is composed of a first memory circuit, a second memory circuit and a compare circuit. A CAM array is composed of individual CAM cells. Each CAM cell receives one bit of the input data word. The bit is compared to the data stored in the first memory circuit of the CAM cell. The second memory circuit of the CAM cell stores an enable value. The enable value is used to enable or disable a CAM cell in the CAM array during data comparison which allows a portion of the input data word to be enabled for comparison and another portion to be disabled for comparison during the match phase of the sequence. 
     There is a desire to reduce the semiconductor substrate area used by the CAM cell in order to provide an increase in performance and achieve improved packing density. The reduction in substrate area is determined by the placement, organization, and interconnections of the transistors of the CAM cell. 
     BRIEF SUMMARY OF THE INVENTION 
     Accordingly, an embodiment of the present invention provides a CAM cell comprising a first memory circuit, second memory circuit and a compare circuit. The first memory circuit comprises a six-transistor SRAM cell. The second memory circuit comprises a six-transistor SRAM cell. Of course, the memory circuits can be any acceptable memory circuits including flip-flops, EEPROM memory cells, cross-coupled invertors, NOR gates, or any other acceptable memory circuit. The compare circuit is a six-transistor structure organized in two parallel stacks of three transistors in one embodiment. Alternatively, a compare circuit having a five-transistor structure may be utilized having two parallel stacks each containing two transistors and a common fifth transistor. 
     The first memory circuit is coupled to a first word line, to a first bit line and to a second bit line. The first memory circuit stores a data value for comparing to an input data bit. The first memory circuit provides signals data-true and data-false to the compare circuit where the data signals are compared to first and second input data signals cf and ct. The second memory circuit is connected to a second word line, to the first bit line and to the second bit line. The second memory circuit stores a mask data value. The second memory circuit provides signal mask-true to the compare circuit to enable or disable the compare circuit. 
     According to an embodiment of the present invention, the interconnections of the transistors of the first and second memory circuits to the transistors of the compare circuit are comprised of regions of conductive material. 
     According to a first embodiment, the conductive material is polysilicon. In alternative embodiments, the conductive material is a metal layer, and can be any acceptable metal including aluminum, copper, tungsten, titanium polysilicides, or various combinations or alloys thereof. Of course, the type of conductive used can be changed within a cell from poly to a metal by the appropriate contacts, vias, and interconnections to provide a conductive path from the memory circuits to the appropriate nodes in the compare circuit. 
     An embodiment of the present invention provides a method of operating a CAM cell comprising the steps of storing data in the CAM cell; applying a signal to an enable line of the device wherein the enable line is a shared-gate structure, and thereby enabling the device; applying an input data; comparing the input data to the first data; and outputting a status change on a match signal line. 
     An embodiment of the present invention provides a method of operating a CAM cell wherein the step of storing further comprises the step of storing data in a first memory circuit and an enable value in a second memory circuit. To store data in the first memory circuit, a value is applied to a first word line; the data to a first bit line; the data complement to a second bit line; then storing a data value in a first memory circuit. An enable value is stored in a second memory circuit in a similar manner and is used to set an enable or disable terminal in the compare circuit. 
     In an embodiment of the present invention, a content addressable memory is formed in an integrated circuit having improved semiconductor substrate area utilization. 
     An embodiment of the present invention provides an improvement to the area utilization of the integrated circuit by reducing the layout area of the CAM cell, thus reducing the cost of manufacture. The embodiments of the present invention are applicable to binary and ternary CAM cells as well as four state CAM cells. 
     An advantage of the invention is that the CAM cell is fast in determining a match or no match decision when given a large data input word. 
     An advantage of the invention is a CAM cell with an improved organization of transistors that reduces the substrate area of the CAM cell and array. 
     An advantage of the invention is a CAM cell with an improved interconnection of transistors that is a small size for the CAM cell and array. 
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of first and second memory circuits and a compare circuit of a CAM cell according to one embodiment of the present invention. 
     FIG. 2 is an embodiment of a compare circuit of a CAM cell of FIG.  1 . 
     FIG. 3 is an embodiment of the transistor schematic connection of a CAM cell according to the present invention. 
     FIG. 4 is a top side plan view of the layout in silicon of a CAM cell illustrating active regions and polysilicon according to one embodiment. 
     FIG. 5 is a top side plan view of the layout in silicon of FIG. 5 also showing the additional layers of a CAM cell illustrating active metal and contacts. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 shows a first memory circuit  10 , a second memory circuit  20 , and a compare circuit  30  forming a CAM cell according to the present invention. The first and second memory circuits  10 ,  20  are used to store a data value and a mask value, respectively. The mask value is the enable or disable signal provided to the compare circuit  30 . The compare circuit  30  as shown in FIG. 1 is used to compare the stored data value in the first memory circuit  10  to input data signals cf and ct. When the second memory circuit  20  has stored an enable value, the true mask signal enables the compare circuit  30  to permit a comparison to occur and when a disable value has been stored, the true mask signal disables the compare circuit  30  so a comparison does not occur. The match line provides an output of the results of the comparison. When the compare circuit is enabled and there is a match between the stored data and the compare data, the match line state remains in the same state, staying high or staying low. When the compare circuit is enabled and there is not a match, the state of the match line is changed, going from high to low. If any one CAM cell of the many connected to Match line is not a match, the line will be pulled low. If p-channel transistors are used for the compare cell, the line will transition from high to low. The signal line  80  provides the interconnection from the first memory circuit  10  to the compare circuit  30  for the data-true signal. The signal line  82  provides the interconnection from the memory circuit  10  to the compare circuit  30  for data-false signal. The match-true data is provided on signal line  84  from the second memory circuit  20  to the compare circuit  30  and the match-false data is not output from the second memory circuit  20  because in this particular embodiment there is no use of the match-false signal in the compare circuit  30 . In an alternative design, the match-false signal may be used, however, in the particular design selected the compare circuit  30  is constructed to permit enabling or disabling of the cell based solely on the signal value of the match-true output from the second memory circuit  20  so that the match-false output is not needed. 
     FIG. 2 is an embodiment of the compare circuit  30  of FIG.  1 . In the embodiment of FIG. 2, six transistors are used, N 5 -N 10 , in order to provide the compare function of the compare circuit  30  of FIG.  1 . In this embodiment, as shown, all of the transistors are n-channel transistors and the description to follow with assume that n-channel transistors are used in the compare circuit. Alternative embodiments may use other transistor types. For example, p-channel transistors could be used for some, or all, of the transistors and the appropriate signal levels would be reversed for those p-channel transistors as well as the respective connections to ground and power as such is considered equivalent and easily accomplished by those of skill in the art. 
     In the embodiment of FIG. 3, the match-true signal line  84  is provided to two transistors, N 6  and N 9 , to provide the disable and enable function. When the match-true signal on line  84  is high, the compare circuit  30  is enabled with both transistors N 6  and N 9  turned on to permit the comparison to occur. On the other hand, when the signal on line  84  is low, the transistors N 6  and N 9  are disabled so that a comparison between the stored data and the compare data cannot occur. In this particular embodiment, the match disable transistors are positioned between the respective compare transistors and the data transistors so as to provide two separate series chains between the match line and ground line, both of which include a respective match disable transistor. This particular transistor structure thus provides completely independent and individualized path from the match data signal line to ground According to a preferred embodiment, the schematic of FIG. 3 is laid out in silicon as will now be illustrated with respect to FIGS. 3-5 
     FIG. 4 shows the detail electrical schematic of the CAM cell of FIG. 1 with the embodiment of the compare circuit of FIG. 3 being used. 
     The labels of the transistors N 5  through N 10  as shown in FIG. 3 are also shown in FIGS. 4 and 5, and are placed over the gate region of the respective transistor for convenience in reference, of course, the transistors also include the source and drains regions as well. The labels for the transistors N 1 -N 4 , P 1 -P 4 , and T 1 -T 4  of the first and second memory circuits  10  and  20  as shown in FIG. 3 are shown in FIGS. 4 and 5 also, and are placed over the gate region of the respective transistor for convenience, but also include the source and drain regions as well. 
     An embodiment of the schematic of the entire CAM cell is shown in FIG.  3 . The first memory circuit  10  is a data cell that stores the data value. The second memory circuit  20  is a mask cell that stores the mask value. The first memory circuit  10  comprises transistors P 1 , N 1 , T 4 , T 3 , N 2 , and P 2 . The second memory  20  cell comprises transistors N 4 , P 4 , T 1 , T 2 , N 3 , and P 3 . The compare circuit  30  comprises transistors N 5 -N 10 . 
     As shown in FIG. 3, the first memory circuit  10  is used to store a data value, and is thus labeled as a data circuit. The stored data value is then compared to an input data value by the compare circuit  30 . The first memory circuit  10  is electrically connected as a standard six-transistor, full CMOS SRAM cell. It has the following organization. The gate of the second pull-down transistor N 2  of the first memory circuit  10  is electrically coupled to the gate of the second pull-up transistor P 2 , to the drain region of the first pull-down transistor N 1 , to the drain region of the first pull-up transistor P 1 , to the drain region of the first pass transistor T 4  and to the gate of the data-false transistor N 8  of the compare circuit  30 , thereby defining the data-false df node  82 . The gate of the first pull-down transistor N 1  of the first memory circuit  10  is electrically coupled to the gate of the first pull-up transistor P 1 , to the drain region of the second pull-down transistor N 2 , to the drain region of the second pull-up transistor P 2 , to the drain region of the second pass transistor T 3  and to the gate of the data-true transistor N 5  of the compare circuit  30 , thereby defining the data-true dt node  80 . The first pass transistor T 4  of the first memory circuit  10  has a gate electrically coupled to a first word line signal WLD and has a source region electrically coupled to a false bit line signal BLF. The second pass transistor T 3  of the first memory circuit  10  has a gate electrically coupled to the first word line signal WLD and has a source region electrically coupled to a true bit line signal BLT. 
     As shown in FIG. 3, the second memory circuit  20  is used to store a mask value MT and is thus labeled as a mask circuit. The mask value MT of node  84  enables or disables the compare circuit  30 . The second memory circuit  20  is also a standard 6-transistor full CMOS SRAM cell. It has the following organization. The gate of the second pull-down transistor N 3  of the second memory circuit  20  is electrically coupled to the gate of the second pull-up transistor P 3 , to the drain region of the first pull-down transistor N 4 , to the drain region of the first pull-up transistor P 4 , and to the drain region of the first pass transistor T 1 , thereby defining the mask-false MF node. The gate of the first pull-down transistor N 4  of the second memory circuit  20  is electrically coupled to the gate of the first pull-up transistor P 4 , to the drain region of the second pull-down transistor N 3 , to the drain region of the second pull-up transistor P 3 , to the drain region of the second pass transistor T 2 , and to the gates of the first and second enable transistors N 6  and N 9  of the compare circuit  30 , thereby defining the mask-true MT node  84 . The first pass transistor T 1  of the second memory circuit  20  has a gate electrically coupled to the second word line signal WLM, and a source region electrically coupled to the false bit line signal BLF. The second pass transistor T 2  of the second memory circuit  20  has a gate electrically coupled to the second word line signal WLM, and a source region electrically coupled to the true bit line signal BLT. 
     In the embodiment just described, the memory circuits  10  and  20  are both SRAM memory circuits of the six-transistor type. In an alternative embodiment, they are SRAM memory circuits of the four-transistor type. Thus, a four-transistor memory circuit using two polysilicon load resistors as the load devices may be used in place of each of the respective six-transistor cells as described in FIG.  3 . In a further alternative embodiment, each of the memory circuits  10  and  20  is composed of another acceptable memory circuit. For example, they may be composed of an EEPROM, EPROM, ROM, flash memory circuit, or other acceptable volatile or nonvolatile memory circuit. Other types of data storage or organization may also be used including DRAMS, blown fuses, programmed ROMS, or other acceptable storage devices for the memory circuits  10  and  20 . The outputs of the respective memory circuits  10  and  20  shown in FIG. 1 are therefore provided to the compare circuit  30  as shown in FIG.  1  and regardless of the particular type, arrangement, or structure of the particular memory inside each of the respective cells. 
     As shown in FIG. 3, the compare circuit  30  is used to compare a stored data value provided by signals dt of interconnect  80  and df of interconnect  82  in the first memory circuit  10  to an input data value of signals cf and ct. In a preferred embodiment, the compare circuit  30  is organized as two parallel stacks of N-type transistors, N 5 -N 10 . The compare-false transistor N 7  has a gate electrically coupled to an input signal cf, a source region electrically coupled to the drain region of the first enable transistor N 6 , and a drain region electrically coupled to the MATCH signal. The compare-true transistor N 10 , has a gate electrically coupled to an input signal ct; a source region electrically coupled to the drain region of the second enable transistor N 9 , and a drain region electrically coupled to the MATCH signal. The first enable transistor N 6  has a source region electrically coupled to the drain region of the data-true transistor N 5 . The second enable transistor N 9  has a source region electrically coupled to the drain region of the data-false transistor N 8 . The organization of the transistors of the compare circuit has the advantage of reducing the substrate area utilization of the CAM cell. 
     As shown in FIGS. 4 and 5, the CAM cell can be laid out in silicon in a compact arrangement. The first memory circuit  10 , second memory circuit  20  and compare circuit  30  are shown as they would be laid out in silicon. Within these figures, the active area is shown in dark outline, the polysilicon is in crosshatch, metal  1  is in stipple, and contacts are shown with an X in a box. The compare circuit  30  includes a first active region  92  and a second active region  90 . In a preferred embodiment, both active regions  90  and  92  are N-type conductivity. The first active region  92  is formed below the gates of the compare-true transistor N 11 , the first enable transistor N 9 , and the data-false transistor N 8 . The first active region  92  is electrically connected to the MATCH signal at the drain region of transistor N 10 . The first active region is electrically connected to a first supply VSS at the source region of data-false transistor N 8  as shown in FIG.  6 . The second active region  90  is formed below the gates of compare-false transistor N 7 , the second enable transistor N 6 , and the data-true transistor N 5 . The second active region  90  is electrically connected to the MATCH signal at the drain region of transistor N 7 . The second active region  90  is electrically connected to the first supply VSS at the source region of data-true transistor N 5  as shown in FIG.  5 . The organization of the first and second active regions  92  and  90  has the advantage of reducing the substrate area utilization of the CAM cell. In an alternative embodiment the first and second active regions  92  and  90  are p-type conductivity. In an embodiment of the present invention as shown in FIGS. 4 and 5, the active regions of the first memory circuit are p-type conductivity regions  120 ,  122  and n-type conductivity regions  132 ,  130 . In addition, the active regions of the second memory circuit are p-type conductivity regions  124 ,  122  and n-type conductivity regions  132 ,  130 . 
     As shown in FIG. 4, the first supply VSS is electrically connected to the source region of first and second pull-down transistors N 1  and N 2  of the first memory circuit  10 , to the source region of the first and second pull-down transistors N 4  and N 3  of the second memory circuit  20 , to the source region of the data-true transistor N 5  and to the source region of the data-false transistor N 8 . A second supply VDD is electrically connected to the source region of the first and second pull-up transistors P 1  and P 2  of the first memory circuit  10  and to the source region of the first and second pull-up transistors P 4  and P 3  of the second memory circuit  20 . The interconnects  80 ,  82 ,  84  from the first and second memory circuits  10  and  20  to the compare circuit  30  are accomplished by regions formed of the polysilicon gate material, a conductive material or a combination of both materials. For example, the conductive material could be a metal such as aluminum, copper, or a second layer polysilicon region. The advantage of the interconnections is to reduce the area utilization of the CAM cell. 
     As shown in FIG. 4, the local interconnect  80  between the first memory circuit  10  and the compare circuit  30  is composed of a single strip of polysilicon that forms the gate of the first pull-down transistor N 1  of the first memory circuit  10 , the gate of the first pull-up transistor P 1  of the first memory circuit  10  and the gate of the data-true transistor N 5  of the compare circuit  30 . In an embodiment, this local interconnect is a region of polysilicon  80  as shown in FIG. 4 and 5. The polysilicon region  80  is a portion of the data-true node dt. The same conductive strip that forms the gate is also the interconnection strip, so that the entire strip is a single, common contiguous layer of material. 
     As shown in FIG. 4, the local interconnect  84 A is formed between gates of the first and second enable transistors N 6  and N 9  of the compare circuit  30 , this is also a single contiguous layer of material, thus providing considerable savings. The local interconnect  84 C is formed between the gates of the first pull-up and the first pull-down transistors P 4  and N 4  of the second memory circuit  20 , this is also a single contiguous layer of material, thus providing considerable savings. The local interconnect  84 B electrically couples interconnects  84 A to  84 C as shown in FIG.  5 . In one embodiment, the node MT is formed of a multi-layer interconnect comprising the local interconnects  84 A,  84 B and  84 C as shown in FIGS. 4 and 5. In a preferred embodiment, local interconnect  84 A comprises a polysilicon region; local interconnect  84 B comprises a conductive material such as aluminum or a second-layer polysilicon region; and local interconnect  84 C comprises a polysilicon region. 
     As shown in FIG. 4, the local interconnect  82 C forms the gate of the second pull-down transistor N 2  and the gate of the second pull-up transistor P 2 . The local interconnect  82 A forms the gate of the data-false transistor N 8  of the compare circuit  30 . As shown in FIG. 5, the local interconnect  82 B electrically couples the local interconnect  82 C to the interconnect  82 A. In a preferred embodiment, local interconnects  82 A,  82 B, and  82 C form the data-false node df as a multi-layer interconnect. The multi-layer interconnect comprises a region of metal  82 B, a region of polysilicon  82 A and a region of polysilicon  82 C as shown in FIG.  5 . 
     According to one embodiment of the present invention, the word line of the first memory circuit  10  is segmented within the memory circuit, as can be seen by viewing FIG.  4 . The word line has two portions, a first portion  94  and a second portion  102 . These word line portions are composed of the polysilicon gate material and are physically distinct and separate from each other. They are, of course, formed in the same layer by the deposition of a blank layer of polysilicon which is then patterned and etched to form all the polysilicon gates simultaneously using process techniques well known in the art. Generally, prior art SRAM memory circuits make use of a single contiguous unbroken strip of polysilicon to form the gate electrode for the two enable transistors T 3  and T 4  within the memory circuit. The embodiment of FIG. 5 makes a departure in this layout by having two separate pieces of polysilicon to form the respective gates for the two enable transistors. In the layout of the present invention, this is a space savings advantage over what would normally be assumed to be more efficient space usage. Additional space saving techniques are carried out in the layout of the embodiment of FIG.  5 . Namely, a single strip of polysilicon is used for the p- and n-channel transistors N 2  and P 2  along with a single contiguous strip of polysilicon being used for the gate electrodes and the data node connection from data-true through P 1 , N 1  to N 5  within the compare circuit. Thus, a single contiguous piece of polysilicon is used for the two transistors P 1  and N 1 . Similarly, the second memory circuit also uses a contiguous piece of polysilicon  84 C for the mask-true interconnect and for the gate electrodes P 4  and N 4 . A single piece of contiguous polysilicon is also used for the gate electrodes N 3 , P 3  and the mask-false connection  98 . Separate strips of polysilicon are also used for the gate electrodes T 1  and T 2 . A single contiguous strip of polysilicon is used for the two enable transistors within the compare circuit N 9  and N 6  which forms a common node of the mask-true connection  84 A. Furthermore, each of the respective nodes which are to be connected together are arranged physically adjacent to each other so as to make easy, close, and dense electrical connections to each other. For example, each of the electrical connections to data-false df are arranged in a generally straight horizontal line in proximity to each other so a single metal layer  82 B may be easily attached to electrically connect them, as shown in FIG.  6 . Similarly, each of the data-true nodes dt are electrically connected close to each other so that a single strip of metal  80 B may easily electrically connect them. The nodes in the mask cell  20  are also similarly arranged in proximity to each other. For example, all the nodes MT internal to the mask cell are arranged in proximity to each other so that a single metal layer  84 B may easily electrically connect all of the nodes. All the nodes MF are also arranged adjacent to each other, as can be seen in FIGS. 4 and 5, so that a single metal layer  83  may connect them all in a small amount of space. Accordingly, the layout of the first and second memory circuits, in association with the compare circuit, are arranged to use a very small amount of silicon substrate and provide a compact layout with tight densities. In alternative embodiments, of course, the word line of each memory circuit can be arranged differently, with the word lines being made of a common, contiguous strip of polysilicon as can other of the word lines or interconnections within the memory circuit. These alternative embodiments may therefore take a somewhat different layout form than that illustrated. 
     The operation of the CAM cell provides logical states match (logical high) and not-matched (logical low) on the MATCH line of FIG.  4 . The logical states produced by a comparison of the input data signals cf and ct to the memory data signals dt and df. The input data signals cf and ct are complemented prior to presentation to the compare circuit  30  in a known manner. The enable signal MT determines the status of the compare circuit  30  to produce a valid or invalid MATCH signal. Initially, the MATCH signal is set high. When the MATCH is high, a valid match between the stored data of the first memory circuit  10  and the input data is indicated. 
     In an embodiment of the CAM cell, the operation of the device has the following steps. A data value is stored in the first memory circuit  10 . A mask value is stored in the second memory circuit  20 . The comparison data is provided to the compare circuit  30 . The status of the MATCH signal is monitored for it to remain the same or change state. 
     The storing of a data value is carried out by applying a high signal to a first word line WLD; applying a first value to a bit line true BLT and a second value to a second bit line BLF; thereby storing a value in the first memory circuit  10  and setting the value of data-true signal dt that is applied to the compare circuit  30  as shown in FIG.  4 . The storing of a mask value comprises the steps of applying a value to a second word line WLM; applying a value to the bit line BLT and a second value to a second bit line BLF; thereby storing a mask value in the second memory circuit  20 , thereby setting the value of enable signal MT enables transistors N 6  and N 9  of the compare circuit  30 . At some time, the steps of applying values to input signals ct and cf of the compare transistors is carried out, thereby comparing the stored data value dt and df of the first memory circuit  10  to the applied input signal values, ct and cf. If a compare is desired, ct and cf will have opposite values, but if it is desired to perform a global block on the column, then both might be low, When both are low, no compare is done and the entire cell group is blocked out that receives the same ct and cf signals. A match is determined by sensing the status of the MATCH signal line. 
     The terms drain and source as used herein with respect to an MOS transistor refer to the two regions on either side of the channel of the MOS transistor in the general sense of the two separate regions. The actual identification of a region as the drain or the source may change from time to time depending on the operational characteristics and electrical connection of the transistor, as well as the voltages present at the different nodes. Accordingly, throughout the specification and in the claims the terms drain and source may be interchanged with respect to each other for a particular transistor depending upon its state and the value of the respective nodes. Thus, each of the terms are to be understood as broadly referring to an active region of the transistor and can alternatively refer to either the drain or the source based on the operating state of that particular transistor. 
     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.