Abstract:
A media player having variable pitch is disclosed. The player incorporates a memory buffer that is responsive to a user-designated pitch adjustment. The result is that a user can manually control and adjust the pitch of prerecorded CDs and MP3s or other digital media in an “on-the-fly” environment.

Description:
FIELD OF THE INVENTION 
     This invention relates generally to music players, and more specifically to a CD or MP3 player which allows a user to adjust the pitch of the music emanating therefrom. 
     BACKGROUND OF THE INVENTION 
     Not all CDs and MP3s are recorded at perfect pitch, nor do all media players play back at exactly the same frequency. A guitarist can easily adjust an instrument to account for minor deviations in pitch. However, a pianist cannot. Consequently, a CD player which allows a user to make both minor and major adjustments to the pitch is desired. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention that the rate of data read out from a buffer memory is varied, so as to effectuate a pitch change during playback of a CD or MP3 or other digital music file. The intervals at which data is written into the buffer memory are varied to effectuate a reproduction timing adjustment. With these features, the pitch of a CD or MP3 can be selectively changed without affecting the rotation control of the spindle motor. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a first embodiment of the present invention for playing CDs; 
         FIG. 2  shows a detailed view of portions of  FIG. 1 ; 
         FIG. 3  shows a detailed view of a first embodiment of the PLL of  FIG. 1 ; 
         FIG. 4  shows a detailed view of a second embodiment of the PLL of  FIG. 1 ; 
         FIG. 5  shows how data density varies based on user pitch adjustment; 
         FIG. 6  shows the time of how a frame of data is read; 
         FIG. 7  shows a detailed view of a third embodiment of the PLL of  FIG. 1 ; 
         FIG. 8  shows an .MP3 frame format as used within the present invention; 
         FIG. 9  shows a second embodiment of the present invention for playing .MP3 files; 
         FIG. 10  shows a third software embodiment of the present invention; 
         FIG. 11  shows a software embodiment of the PLL of  FIG. 10 ; and 
         FIG. 12  shows a flowchart explaining the PLL of  FIG. 12 . 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Before explaining the disclosed embodiment of the present invention in detail it is to be understood that the invention is not limited in its application to the details of the particular arrangement shown, since the invention is capable of other embodiments. Also, the terminology used herein is for the purpose of description and not of limitation. 
     As shown in  FIG. 1 , a CD console  140  has two pitch control buttons ‘+’ and ‘−’ for increasing (+) or decreasing (−) pitch speed of a CD. A system controller/CPU  116 , e.g. a microprocessor or CPU, controls the CD player  100 . The system controller  116  outputs drive control signals to a constant linear velocity (CLV) servo circuit  108 , a focus servo circuit  104 , and a feed servo circuit  107 . The CLV servo circuit  108  assures that the linear velocities of respective tracks of the CD remain constant, by carefully controlling the revolutions of a spindle motor  102 . 
     The focus servo circuit  104  detects a focus error from the state of laser beam reflection, and controls and drives the objective lens in an optical pickup  103  in the optical axis direction based on the detected focus error. The feed servo  107  controls a feed motor  106 , which moves the optical pickup  103  in the radial direction of the CD by detecting laser beam differences from the track center of the CD. The servo circuit  107  moves the optical pickup  103  for tracking appropriate tracks when laser beam differences fluctuate rapidly due to the eccentricity of the optical pickup  103 . Thus, the servo circuit  107  controls the optical pickup  103  to correctly irradiate laser beams to the track center of the CD. 
     During playback, the surface of the CD is irradiated by laser beams. The CD has extrusions called pits which contain digital signals. The optical pickup  103  detects the existence of these pits based on the luminous energies of the reflections of irradiated laser beams. The pickup  103  reads the existence, length, and positioning of those pits, and inputs that information to a data extractor  110 . 
     The musical data is stored read from the CD as a series of pulses. Since the widths of these pulses range from 3 to 11 clock cycles, when the pulses are differentiated sometimes discontinuous pulse series&#39; occur (unwanted). Accordingly, bit clocks within the musical data are extracted by converting the pulses into continuous pulse series using a phase locked loop (PLL)  126  for aligning and input clock with a reference clock, shown in  FIG. 1  adjoining the data extraction circuit  110 . 
     The following is a description of a typical CD frame format. A frame of a CD signal comprises 588 bits of data. The lead 24 bits in the respective frames are reserved for frame synchronizing signals. In CDs, each frame contains twelve (12) data words. Accordingly, to read or sample one frame takes time of 6/f s  (sec), where f s  is a sampling frequency. This time corresponds to a frequency of 7.35 KHz. Since a typical CD frame contains 588 bits of data, the bit clocks in CD reproduction signals are customarily set at 4.321 MHz (==7.35 KHz multiplied by 588) when the CD is played at the normal speed.  FIG. 6  shows the frequency correspondence between the recorded and reproduced signals of a CD according to the present invention. 
     Referring back to  FIG. 1 , the data extractor  110  extracts the above described bit clocks by digitizing the reproduction signals into binary values, and transmitting the bit clocks to a divider  109 , a frame synchronizer  111 , and a demodulator  112 . The data extractor  110  also outputs digitized reproduction signals to the frame synchronizer  111 , which detects a frame synchronization signal from the data extractor  110  and outputs the data being cut off at every frame to the demodulator  112  using the detected frame signal. 
     When the optical pickup  103  converts data from the pits on the CD into electric signals, if either of a logical “1” or “0” continues sufficiently long, the electrical signal can become like a DC signal, so that important bit spacing information is interrupted or misplaced. This in turn causes the focus servo circuit  104  to operate erroneously, which adversely affects the behavior of the optical pickup  103 . 
     To eliminate such a DC signal, a data conversion method called the EFM [Eight (8) to Fourteen (14) Modulation] is employed, whereby the 8-bit data recorded in a CD is converted to 14-bit digital data. This conversion is completed so as to avoid a potential long continuation of a logical 1 or 0. The EFM demodulator  112  demodulates EFM 14-bit data converted from the reproduction signals back to the original 8-bit data. 
     The 8-bit audio data is then inputted to a signal processing circuit  113  are inputted to the system controlling circuit  116 . The signal processing circuit  113  corrects their errors based on an error correction protocol called the CIRC (Cross Interleave Reed-Solomon Code). The signal processor  113  is responsive to the clock signals from the clock generator  118 , as well as to the controller/CPU  116 . The controller  116  manages the dataflow between the EFM demodulator  112  and signal processor  113 . In some cases the controller  116  manages the packaging of data frames coming out of the EFM demodulator  112  to the processor  113 . In other cases the controller  116  allows the demodulator  112  and processor  113  to communicate directly, and exchange high volumes of data in burst mode. 
     In  FIG. 2 , the clock generator  118  contains dividing circuits 1/16, ½, and ⅙ for sequentially dividing the oscillating frequencies of an oscillator  118  by integers. A clock of 44.1 KHz is used for reading in D/A conversion, while a clock of 7.35 KHz is used for the CLV servo circuit  108 . The above frequencies are changed according to variations in the pitch signal from the console  140 . 
     As shown in  FIG. 3 , a first embodiment of the PLL  126  comprises a phase comparator  124 , a voltage controlled oscillator (VCO)  125 , and a loop filter LF. Usually, the lock range of a PLL is in the magnitude of a few percent of the frequencies inputted to a phase comparator. When these input frequencies are changed, the frequencies outputted from the PLL are correspondingly changed also. Accordingly, the output frequency of the PLL  126  of the present invention can also be freely changed by changing the input frequency yet still remain locked. Accordingly, the CD reproduction speed can be freely changed (within a predetermined range) while the PLL  126  still remains locked. The frequency at which the PLL  126  operates is dependent upon the frequency of the VCO  312  and the loop filter  308 . To change the output frequency, these elements must be adjusted. However, adjusting these elements while the PLL  126  is operating can cause the phase lock to be lost for a short period of time. 
     Another problem particular to digital signal processing is the need to extract a digital clock from a data stream. Though the expected data rate of the data stream may be known, the actual data rate and signal quality received may vary significantly and in some cases may drop out altogether, such as when the CD player gets bumped. Factors that also could affect the frequency and quality of the data stream include imperfections in the detection and decoding equipment, among other things. 
     To address these problems,  FIG. 4  shows a second embodiment of the PLL  126 , having a high-speed phase comparator  402 , charge pump  404 , filter  406 , VCO  410 , and feedback divider  414 . The phase comparator  402  compares an input signal to a feedback signal from the feedback divider  414 . Depending on the phase difference between the input and reference clocks, the phase comparator  402  drives the charge pump  404 , the output of which is used to drive the VCO  410 . The VCO  410  receives a voltage and then outputs a signal with a frequency proportional to that voltage. The output of the VCO  410  is fed back through a feedback divider  414  to a phase comparator  402 . 
     Although  FIG. 2  shows frequency dividers within the clock generator  118 , the feedback divider  414  has a separate purpose. The divider  414  divides down the PLL output frequency to match the PLL input signal frequency so that their phases can be compared. The signal path through the feedback divider  414  to the phase comparator  402  creates the feedback that facilitates the PLL operations. Because the phase comparator  402  operates at high speed, the time where the output frequency is not locked is very short and does not impact performance. 
       FIG. 5  is timing chart showing some exemplary rates of operation of the CD player  100  of the present invention, wherein portions of musical data are selectively raised an octave and lowered an octave in pitch. This range is chosen because a doubling in frequency of a tone will raise that tone once octave, while halving a frequency of a tone will lower that tone one octave. Also, an explanation of the memory buffering performed by data extractor  110  and associated memory  110 R is made conceptually easier to understand by using examples of larger proportion. 
     In normal playback, data frame  1  is read out from the CD at a transfer rate of 1.4 Mb/s for example, and is written into the buffer memory  10  after demodulation. This data is then successively read out from the memory  10  at a transfer rate of 0.3 Mb/s. Then, the data, after sound expansion, is output as playback data signals at a transfer rate of 1.4 Mb/s. 
     However, for readout of the data frame  2 , the clock generator  118  supplies the data extractor  110  and sound expansion signal processor  113  with clock pulses having twice the frequency of normal reproduction. Thus, data is read out from the buffer memory  110 R at a transfer rate of 0.6 Mb/s instead of the normal unaltered mode of 0.3 Mb/s. The data is then output from the sound compression/expansion section  12  at a transfer rate of 2.8 Mb/s instead of the normal unaltered rate of 1.4 Mb/s as shown in  FIG. 5  by the data portion  2  being drawn fatter and thicker (signifying higher data density). In both cases the transfer rates are two times higher than the normal rate. The sampling frequency of read data portion  2  is 88.2 kHz, which is two times higher than the normal, and hence this portion  2  is drawn thicker and will be reproduced one octave higher in pitch. 
     The data extractor  110  monitors the changing data storage or accumulation amount (current data balance) in the buffer memory  110 R. When the data accumulation has progressed to reach near the last address in the memory  110 R, the data extractor  110  instructs readout of a next data portion. Before the data storage progresses to near the last address, the data extractor  110  causes the data readout process to wait or delay. Therefore, as the data is read out from the buffer memory  110 R two times faster than the normal rate, the data accumulation amount in the memory  110 R decreases more rapidly, so that the waiting time between data frames  2  and  3  becomes shorter than in normal audio playback. In other words, the data writing period in which the demodulated readout data from the CD is intermittently written into the buffer memory  110 R does not occur at the normal transfer rate of 1.4 Mb/s, but instead at 2.8 Mb/s. More specifically, the data writing period is shortened so that the writing time is greater than the waiting time in terms of write/wait duty ratio. Finally, in  FIG. 5  the normal pitch reproduction is resumed at data frame  3 . 
       FIG. 5  also shows playing back of digital musical data from a CD where that data is lowered in pitch. The operation for data frames  1 ,  3 , and  5  are the same as in normal non-adjusted reproduction. However, for data frame  4 , the clock generator  118  supplies the extractor  110  and sound expansion signal processor  113  with clock pulses having ½ frequency of normal reproduction. Thus, the data is read out from the buffer memory  110 R at a transfer rate of 0.15 Mb/s which is ½ the normal rate. Similarly, data is output from the sound expansion section signal processor  113  at a transfer rate of 0.7 Mb/s, which is also ½ the normal rate. The data frame  2  is 22.05 kHz which is also ½ the normal sampling frequency, hence this read data portion  2  is drawn thinner (lower data density) and will be reproduced in a pitch exactly one octave lower than the other portions. 
     In this example, because the data is read out from the buffer memory  110 R at ½ the normal rate, the data accumulation amount in the memory  110 R decreases more slowly than during normal reproduction, so that the waiting time between read data portions  2  and  3  becomes longer than in normal rate reproduction. Normally, the data writing period in which the demodulated readout data from a CD is intermittently written into the buffer memory  110 R at a transfer rate of 1.4 Mb/s. In this example however, the data writing period is lengthened so that the writing time is smaller than the waiting time in terms of the write/wait duty ratio. 
     The system  100  of the present invention can thus achieve pitch change by varying the rate at which data is read out from the CD and then written into the buffer memory  110 R. 
     As stated, conventional PLLs have some limitations. One limitation is that it is difficult to lock to the phase of an input signal having a frequency out of the range onto which a particular PLL is designed to lock, such as the wider frequencies to go up and down entire octaves described above. One solution to this problem is to add a frequency sweep circuit which forces the output frequency of the PLL to sweep across a broader frequency range in an attempt to direct the output PLL frequency to pass close enough to the frequency of the input waveform to enable the PLL to phase-lock. 
     Accordingly, a third variation of the PLL  126  is shown in  FIG. 7 , which shows a data stream arriving at the input of a phase compare  702 , which detects the phase difference between a reference clock and a feedback clock which also constitutes the output clock of the PLL  126 . The phase compare  702  outputs a phase difference signal representative of the phase difference between the reference and input clocks. The phase difference fed into a charge pump  704  and low pass filter block  706 . The charge pump  704  and low pass filter block  706  convert the digital phase difference signal into an analog phase difference signal through a D/A converter. The analog phase difference signal is then fed through a low pass filter to filter out high frequency noise. 
     A filtered analog phase difference signal is output from the charge pump  704  and low pass filter  706  in a feed-back loop to a self-sweeping autolock sub-circuit (“SSA”)  720 . The SSA  720  determines whether the PLL  126  has lost phase lock by calculating the value of the control voltage signal based on the phase difference signal. 
     Phase lock is lost by the PLL  126  when the frequency between the input and reference clocks exceeds a predetermined maximum frequency difference. The SSA  720  receives the control signal and identifies the phase difference between input and reference clocks. If the value of the control signal is outside the range of acceptable values, the SSA  720  determines that phase lock is absent. When phase lock is lost, the SSA  720  enters a mode in which it outputs a phase search signal which sweeps the input at a predetermined range of frequencies. In the absence of phase lock, the SSA  720  varies the control voltage signal in a sweeping manner across a predefined range of frequencies. The sweeping operation continues in a repetitive manner until phase lock is re-acquired. 
     The present invention also has an embodiment which can scale back the amount and granularity of frequency shifting that it performs, which is useful in those environments where only a minor amount of re-tuning is required. As stated earlier, the clock signal frequency of 7.35 KHz supplied to the CLV servo circuit  108  shown in  FIG. 2  is customarily used during CD playback. Each time one of the pitch control buttons on the console  140  is pressed, the system controlling circuit  116  outputs an adjusted pitch control signal so that the frequency of the clock signal generating circuit  118  changes by a semitone, i.e. in the ratio of 2 1/12  (˜=1.059) Hz. When the frequencies of the clock signal generating circuit  118  are changed, the frequencies of the bit clock signals signal processing circuit  113  are also changed by the same ratio, i.e. 2 1/12 . Thus, the pitches and the tempos of the digital musical data played out from the CD are similarly changed. Such frequency changes are realized by controlling the oscillator  118  with the user-selected pitch signal as shown in  FIG. 2 . The console  140  can also be equipped with options that allow a user to change tunings, such as from the recorded key (i.e. G) to go up one whole step (i.e. the key of A), or perhaps a half-step (G to G#), or perhaps a smaller deviation. Such an adjustability could be useful to musicians who are attempting to learn a song by playing along with that song, yet have difficulty quickly tuning their instrument to adjust for minor deviations in pitch that are a common problem among different media players. A piano is one example of such an instrument that cannot be easily re-tuned in any direction, although other instruments have this problem also. 
     The oscillator  118  can be made from a programmable silicon oscillator, or a ceramic oscillator capable of generating varying oscillating frequencies. Alternately, a software oscillator can be fabricated by taking a timer tick from the overall control microprocessor for the CD unit, or the mini operating system (O/S) loaded thereon. In the case of CD playback units mounted in a personal computer or workstation, the software oscillator can trigger from the timer tick from the O/S running on the computer CPU. Because the average PC runs at frequencies around 1 GHz yet as shown speeds for the present invention do not exceed 4.32 MHz ( FIGS. 1 and 2 ), sufficient bandwidth is available to facilitate accurate clock management as well as sophisticated error detection and correction of the musical data. 
     The playback mechanism of the present invention can work from .MP3 files as well as CDs. An exemplary .MP3 file format is shown in  FIG. 8 , in which an .MP3 file  90  has a header  91 , audio data  92 , and tag  93 . Within the header  91  there is stored codec information, bit rate, sampling frequency, channel mode, song name, artist name, and other content information. 
     Moreover, within the .MP3 file of  FIG. 8 , the audio data  92  is partitioned into packet form at to fit within the MPEG audio frame format. This format consists of a frame header  101  and its associate data  102 . The header  101  can also contain information regarding the length of the frame. 
     An exemplary MP3 playback system is shown in  FIG. 9 , wherein a system controller  116  decodes an MP3 data frame by extracting .MP3 frame data which it passes to a frame synchronizer  911 . The frame synchronizer  911  compares total data length and checksum among other things, to determine whether communication is being carried out successfully. A lot of components from  FIG. 1  are used similarly in  FIG. 9 , including the extractor  910 , generator  918 , synchronizer  911 , controller/CPU  916 , demodulator  912 , and signal processor  913 . 
       FIG. 10  shows a playback system  1000  of the present invention which is implemented partially in software. One example where this would be useful is with a CD or media player that can function within and is sometimes loaded within a Windows™ or other proprietary O/S or even an open-source O/S. In such a case, the playback system  1000  relies on the CD drive hardware only for managing the steady and unvarying rotation of the spindle motor. Within the .MP3 implementation the spindle motor hardware and logic is omitted. The rest of the data management, buffering, and PLL clock synchronizing is contained within the software module  1000  itself, as denoted by the dotted lines in  FIG. 10 . A lot of components from  FIG. 1  are used similarly in  FIG. 10 , including the extractor  1010 , generator  1018 , synchronizer  1011 , controller/CPU  1016 , demodulator  1012 , and signal processor  1013 . 
     The PLL  1026  is also be implemented in software, as shown in  FIG. 11 . The software implementation of a PLL  1026  allows flexibility in for detecting input signals which are out of expected frequency range, and for detecting failure states in which the PLL cannot properly track the input signal. Checking the counter value to determine if it deviates from previously read counter values by more than a predetermined amount is done to detect whether input signals are out of range. More complex range-checking tests can also be used. 
     As shown in  FIG. 11 , the software PLL  1026  comprises a summation counter  1104  which has a read module to periodically read a value from the phase counters  1  . . . n, and a comparison module to compare a current summation counter value to a last of the stored plurality of summation counter values. The software PLL  1026  also includes an error detector  1140  to disable further summation counter reading if the reference clock signal is lost. 
     In the event of such a loss, holdover at the last known valid clock frequency is implemented as follows. A set of most recent counter values is stored in fallback register  1120  by the CPU  1016 , for example the clock values passed to the D/A for the previous 10 seconds. When a clock signal is lost, the software PLL  1026  ignores further counter values, and slowly returns the D/A to the last valid value (so that an abrupt frequency shift at the output does not occur). This value is then kept fixed until a verifiably valid input is detected. Frequency accuracy is then a function only of the intrinsic performance of the VCO and the stability of the D/A output. Filtering algorithm modules responsive to the CPU  1016  can improve or eliminate high frequency jitter. 
     The behavior of the software PLL  1026  is shown in the flowchart diagram of  FIG. 12 . The first step performed by the software PLL  1026  is receiving a local clock signal (step  1202 ), and then splitting it into a plurality of phases ranging from 2 to n (step  1204 ). Once the local clock signal is thus split into the various phases, the rising and the falling edges of each of the phases are counted, each in its own counter (step  1206 ). 
     With the local clock signal split into multiple phases, the 14-bit counters ( FIG. 11 ) are used to count the rising and falling edges of each phase. On a predetermined schedule, the reference clock is latched into the summation counter  1104  on a predetermined schedule (step  1208 ). When this happens, the summation counter  1104  latches counter information from the 14-bit edge counters and sums them together (step  1210 ). This sum is indicative of the number of edges in the predetermined time period between latches of the reference clock, and is read by the CPU  1016  (block  1211 ). 
     In step  1212 , the newest counter value from the summation counter  1104  is compared with secondmost recent counter value from the summation counter. If the newest counter value is greater than the secondmost recent counter value, the local input clock is running faster than the reference clock. If the newest counter value is less than the secondmost recent counter value, the local clock is running slower than the reference clock. Over time, a recognizable non-random pattern of steadily increasing or decreasing counter values indicates that the local clock is drifting. 
     If a pattern of increasing or decreasing counter values is detected so that clock drifting is occurring, then local clock correction is accomplished in blocks  1214  or  1216  depending upon the direction of the clock drift. A software filter processes the values to determine the proper correction to meet precision clocking standards. Adjustment of the output clock to match the reference clock is accomplished once the proper correction has been determined. 
     However, one-time changes such as those due to high frequency jitter can also affect counter values. To largely eliminate high frequency jitter effects, the counter values read by the CPU can also be filtered through a low pass filter. 
     It is anticipated that various changes may be made in the arrangement and operation of the system of the present invention without departing from the spirit and scope of the invention, as defined by the following claims.