Abstract:
According to the present invention, there is provided an oscillating circuit comprising: an gate circuit coupled between a first electrical source and a second electrical source, the gate circuit outputting an oscillating signal from an output terminal in response to the standby signal; an switch circuit having an one end and an other end, the one end coupled to the output terminal of the gate circuit and the second terminal, the other end coupled to the first terminal, the switch circuit electrically connecting or disconnecting the first terminal and the second terminal in response to the standby signal.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an oscillating circuit having a function for outputting an oscillating signal by employing a crystal oscillating element or the like, or for outputting an oscillating signal in response to a clock signal supplied from outside. 
     2. Description of Related Art 
     A conventional crystal oscillating circuit has a crystal oscillator, a resisting means, a NOR gate, and inverter. One electrode of the crystal oscillator is coupled to a first terminal via a switch, while the other electrode of the crystal oscillator is coupled to a second terminal. The resisting means is coupled between the first terminal and the second terminal. The resisting means is composed of a p-channel type field-effect transistor (hereinafter referred to as “PMOS”) and an n-channel field-effect transistor (hereinafter referred to as “NMOS”), the PMOS and the NMOS being connected in parallel to each other between the first terminal and the second terminal. The gate of the PMOS is connected to a ground GND to which a ground potential is applied, while the gate of the NMOS is connected to a power source VDD to which a power potential is applied. The PMOS and the NMOS are always in a conducting state. One input terminal of the NOR gate is connected to the first terminal, the NOR gate being connected between the power source VDD and the ground GND. A standby signal STBY is applied to the other input terminal of the NOR gate. The output terminal of the NOR gate is connected to the second terminal. The inverter is connected to the output terminal of the NOR gate. 
     The operation of the conventional oscillating circuit will now be described. The standby signal STBY is a signal for setting a low power consumption mode. In the low power consumption mode, the standby signal STBY is set to H level indicative of “valid”, while in a normal operation mode, the standby signal STBY is set to L level indicative of “invalid”. If the switch is ON in the normal mode, i.e., if the standby signal STBY is L level, then oscillation by the crystal oscillator is performed. At this time, the crystal oscillator operates as a series resonance circuit having an intrinsic series resonance frequency f. The resisting means works as a feedback resistor. The NOR gate is operated as an inverting amplifier by the resisting means. If the series resonance frequency of the crystal oscillator is f, and the gain of the inverting amplifier is x1 or more, then the oscillation is maintained at the frequency f. In the low power consumption mode, i.e., when the standby signal STBY is H level, the NOR gate stops outputting the oscillation signal. The output terminal of the NOR gate is fixed at the ground potential. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to reduce the power consumed in an oscillating circuit. 
     To this end, according to the present invention, there is provided an oscillating circuit comprising: a first terminal; a second terminal, a gate circuit coupled between a first electrical source and a second electrical source, the gate circuit receiving a signal supplied to the first terminal and a standby signal, the gate circuit outputting an oscillating signal from an output terminal in response to the signal supplied to the first terminal when the standby signal has a first level, the gate circuit outputting no oscillating signal from the output terminal when the standby signal has a second level; and a switch circuit having one end coupled to the output terminal of the gate circuit and the second terminal, and the other end coupled to the first terminal, the switch circuit electrically connecting the first terminal and the second terminal when the standby signal has the first level, the switch circuit electrically disconnecting the first terminal and the second terminal when the standby signal has the second level; and an output circuit outputting a signal in response to a signal outputted from the output terminal of the gate circuit. 
     The present invention further includes various aspects that will be understood from the following embodiments set forth below. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of a crystal oscillating circuit of a first embodiment in accordance with the present invention. 
     FIG. 2 is a circuit diagram of a NOR gate shown in FIG.  1 . 
     FIG. 3 is a circuit diagram of a crystal oscillating circuit of a second embodiment in accordance with the present invention. 
     FIG. 4 is a circuit diagram of a crystal oscillating circuit of a third embodiment in accordance with the present invention. 
     FIG. 5 is a circuit diagram of a crystal oscillating circuit of a fourth embodiment in accordance with the present invention. 
     FIG. 6 is a circuit diagram of a three-state inverter in the fourth embodiment. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 1, the crystal oscillating circuit of a first embodiment will be described. 
     The crystal oscillating circuit has a crystal oscillator  11 , a switch  12 , a switch circuit  15 , a NOR gate  16 , and an inverter  17 . 
     One electrode of the crystal oscillator  11  is connected to a first terminal  13  via the switch  12 , while the other electrode of the crystal oscillator  11  is connected to a second terminal  14 . The switch circuit  15  is connected between the first terminal  13  and the second terminal  14 . The switch circuit  15  is composed of a PMOS  15   a , an NMOS  15   b , and an inverter  15   c . The PMOS  15   a  and the NMOS  15   b  are connected in parallel to each other between the first terminal  13  and the second terminal  14 . A standby signal is supplied to the gate of the PMOS  15   a . The gate of the NMOS  15   b  is connected to the output terminal of the inverter  15   c . The inverter  15   c  receives the standby signal. The gate of the NMOS  15   b  receives a signal obtained by inverting the standby signal by the inverter  15   c.    
     One input terminal of the NOR gate is connected to the first input terminal  13 , a standby signal STBY being supplied to the other input terminal of the NOR gate  16 . The NOR gate  16  is connected between a power source VDD to which a line voltage is applied and a ground GND to which a ground voltage is applied. The output terminal of the NOR gate  16  is connected to the second terminal  14 . The input terminal of an inverter  17  which is an output circuit is connected to the output terminal of the NOR gate. 
     The circuit configuration of the NOR gate  16  will now be described in conjunction with FIG.  2 . 
     In the NOR gate  16 , two NMOS&#39;s  6   c ,  6   d  are connected in parallel between an output terminal O 16  and the ground GND. Two PMOS&#39;s  6   a ,  6   b  are connected in series between the output terminal O 16  and the power source VDD. The standby signal STBY is supplied to the gates of the PMOS  6   a  and the NMOS  6   d , while a signal from the first terminal is supplied to the gates of the PMOS  6   b  and the NMOS  6   c.    
     The operation of the oscillating circuit of the first embodiment will now be described. 
     The standby signal STBY is a signal for setting the low power consumption mode. In the low power consumption mode, the standby signal STBY is set at the H level indicative of valid. In normal operation mode, the standby signal STBY is set at the L level indicative of invalid. 
     In the normal operation mode wherein the standby signal STBY is L level, if the switch  12  is ON, then the oscillation using the crystal oscillator  11  is carried out. Since the standby signal STBY is L level, the PMOS  15   a  and the NMOS  15   b  turn ON, placing the first terminal and the second terminal in conduction. The ON resistance of the PMOS  15   a  and the NMOS  15   b  works as feedback resistance. The NOR gate  16  and the switch circuit  15  constitute an inverting amplifier. This allows the crystal oscillating circuit to continue oscillation by using the crystal oscillator  11 . The inverter  17  sets the logic for the oscillating signal, which is output signal of the NOR gate  16 . The inverter  17  outputs the output signal of the inverter  17  to a circuit in the following stage. 
     The crystal oscillating circuit is able to receive a clock signal CLK from outside and output an oscillating signal to the circuit in the following stage. When the clock signal is received from outside, the switch  12  is turned OFF to isolate the first terminal from the crystal oscillator. The incoming clock signal CLK is supplied to the NOR gate  16  via the first terminal  13 . Depending upon the level of the clock signal CLK, the NOR gate  16  connects the output terminal O 16  to the power source VDD or the ground GND, then sets the voltage of the output terminal O 16  and outputs it. 
     In the low power consumption mode, wherein the standby signal STBY is set at the H level, the NOR gate connects the output terminal O 16  to the ground GND. This prevents an oscillating signal from being supplied to the circuit in the following stage even if the oscillation by the crystal oscillator  11  is being performed. Even when the clock signal CLK is being received from outside, no oscillating signal based on the clock signal CLK is supplied to the circuit in the following stage because the voltage of the output terminal O 16  is fixed. In other words, the low power consumption mode is set in the circuit in the following stage. 
     When the standby signal STBY is H level, the standby signal STBY at the H level is supplied to the gate of the PMOS  15   a , while a signal at the L level is supplied by the inverter  15   c  to the gate of the NMOS  15   b . Therefore, both the PMOS  15   a  and the NMOS  15   b  turn OFF, cutting off the conduction between the first terminal  13  and the second terminal  14 . As a result, even when, for example, the clock signal CLK supplied to the first terminal  13  is switched to the H level, no current flows from the first terminal  13  to the ground GND via the switch circuit  15  and the output terminal O 16 . 
     In the first embodiment, the switch circuit  15  is composed of the PMOS  15   a , the NMOS  15   b , and the inverter  15   c . Thus, the conduction between the first terminal and the second terminal is cut off when the standby signal STBY is switched to the H level to prevent current from flowing from the first terminal  13  to the ground GND via the switch circuit, permitting lower power consumption. 
     FIG. 3 is a circuit diagram of a crystal oscillating circuit of a second embodiment in accordance with the present invention. 
     In FIG. 3, the same components as those in FIG. 1 are assigned the same reference numerals. 
     The crystal oscillating circuit shown in FIG. 3 has a crystal oscillator  11 , a switch  12 , a switch circuit  25 , a NOR gate  16 , and inverter  17 . 
     One electrode of the crystal oscillator  11  is coupled to a first terminal  13  via the switch  12 , while the other electrode of the crystal oscillator  11  is coupled to a second terminal  14 . The switch circuit  25  is connected between the first terminal  13  and the second terminal  14 . The switch circuit  25  is constituted by a PMOS  25   a , the source and drain of the PMOS  25   a  being coupled to the first terminal  13  and the second terminal  14 , respectively. The gate of the PMOS  15   a  receives a standby signal. 
     One input terminal of the NOR gate  16  is connected to the first terminal  13 . A standby signal STBY is supplied to the other input terminal of the NOR gate  16 . The NOR gate  16  is connected between a power source VDD and a ground GND. The output terminal of the NOR gate  16  is connected to the second terminal  14 . The input terminal of the inverter  17 , which is an output circuit,, is connected to the output terminal of the NOR gate. 
     The operation of the crystal oscillating circuit of the second embodiment will now be described. 
     If the switch  12  is ON when the standby signal STBY is L level, then the oscillation using the crystal oscillator  11  is carried out. Since the standby signal STBY is L level, the PMOS  25   a  turns ON, placing the first terminal and the s second terminal in conduction. The ON resistance of the PMOS  25   a  works as feedback resistance. The NOR gate  16  and the switch circuit  25  constitute an inverting amplifier. This allows the crystal oscillating circuit to continue oscillation by using the crystal oscillator  11  as in the case of the first embodiment. The inverter  17  sets the logic for the oscillating signal, which is output signal of the NOR gate  16 . The inverter  17  outputs the output signal of the inverter  17  to a circuit in the following stage. 
     The crystal oscillating circuit is able to receive a clock signal CLK from outside and use it to output an oscillating signal to the circuit in the following stage as in the case of the first embodiment. 
     In the low power consumption mode, wherein the standby signal STBY is set to the H level, the NOR gate connects an output terminal O 16  to the ground GND. This prevents an oscillating signal from being supplied to the circuit in the following stage even if the oscillation by the crystal oscillator  11  is being performed. Even when the clock signal CLK is being received from outside, no oscillating signal based on the clock signal CLK is supplied to the circuit in the following stage because the voltage of the output terminal O 16  is fixed. In other words, the low power consumption mode is set in the circuit in the following stage. 
     When the standby signal STBY is H level, the standby signal STBY at the H level is supplied to the gate of the PMOS  25   a . Therefore, the PMOS  25   a  turns OFF, cutting off the conduction between the first terminal  13  and the second terminal  14 . As a result, even when, for example, the clock signal CLK supplied to the first terminal  13  is switched to the H level, no current flows from the first terminal  13  to the ground GND via the switch circuit  25  and the output terminal O 16 . 
     In the second embodiment, the switch circuit  25  is composed of the PMOS  25   a . Thus, the conduction between the first terminal and the second terminal is cut off when the standby signal STBY is switched to the H level to prevent current from flowing from the first terminal  13  to the ground GND via the switch circuit, permitting lower power consumption. 
     The switch circuit  25  of the second embodiment is composed of only the PMOS  25   a , allowing the circuit scale to be made smaller than that of the crystal oscillating circuit of the first embodiment. 
     FIG. 4 is a circuit diagram of a crystal oscillating circuit of a third embodiment in accordance with the present invention. 
     In FIG. 4, the same components as those in FIG. 3 are assigned the same reference numerals. 
     In the crystal oscillating circuit of the third embodiment, the switch circuit  25  of the crystal oscillating circuit in the second embodiment has been replaced by a switch circuit  35 . The crystal oscillating circuit of the third embodiment has the same configuration of the crystal oscillating circuit of the second embodiment except for the switch circuit. 
     The switch circuit  35  is composed of an NMOS  35   a  and inverter  35   b . The source and drain of the NMOS  35   a  are connected to a first terminal  13  and a second terminal  14 , respectively. 
     The gate of the NMOS  35   a  is connected to the output of an inverter  35   b  to which a standby signal is supplied. 
     The operation of the oscillating circuit of the third embodiment will now be described. 
     When a standby signal STBY is set to the L level indicative of invalid, the NMOS  35   a  turns ON. Hence, the crystal oscillating circuit of the third embodiment operates like the crystal oscillating circuit of the second embodiment . When the low power consumption mode is set and the standby signal STBY is switched to the H level, the NMOS  35   a  turns OFF. This cuts off a current path between the first terminal  13  and the second terminal  14 . In this state, therefore, even if a clock signal CLK is set to the H level, no current flows to a ground GND through the terminals  13  and  14 , and an output terminal O 16 . 
     In the third embodiment, the switch circuit  35  is composed of the NMOS  35   a  and the inverter  35   b . Thus, when the standby signal STBY is switched to the H level, the conduction between the first terminal and the second terminal is cut off to prevent current from flowing from the first terminal  13  to the ground GND via the switch circuit, permitting lower power consumption. Furthermore, since the switch circuit  35  of the third embodiment is composed only of the NMOS  35   a  and the inverter  35   b , its circuit scale can be made smaller than that of the crystal oscillating circuit of the first embodiment. 
     Referring now to FIG. 5, a crystal oscillating circuit of a fourth embodiment will be described. 
     The oscillating circuit has a crystal oscillator  11 , a switch  12 , a resisting means  45 , a NOR gate  16 , and a three-state inverter  46 . 
     One electrode of the crystal oscillator  11  is connected to a first terminal  13  via the switch  12 , while the other electrode of the crystal oscillator  11  is connected to a second terminal  14 . The resisting means  45  is connected between the first terminal  13  and the second terminal  14 . The resisting means  45  is composed of a PMOS  45   a  and an NMOS  45   b . The PMOS  45   a  and the NMOS  45   b  are connected in parallel to each other between the first terminal  13  and the second terminal  14 . The gate of the PMOS  45   a  is connected to a ground GND, while the gate of the NMOS  45   b  is connected to a power source VDD. 
     The input of the three-state inverter  46  is connected to the first terminal  13 . Connected to the output of the three-state inverter  46  is one input terminal of the NOR gate  16  and the second terminal  14 . A standby signal STBY is supplied to the other input terminal of the NOR gate  16 . The NOR gate  16  is connected between the power source VDD and the ground GND. 
     The circuit configuration of the three-state inverter will now be described in conjunction with FIG.  6 . 
     In the three-state inverter  46 , two NMOS&#39;s  46   c  and  46   d  are connected in series between an output terminal O 46  and the ground GND. Further, two PMOS&#39;s  46   a  and  46   b  are connected in series between the output terminal O 46  and the power source VDD. The gates of the PMOS  46   a  and the NMOS  46   d  receive a signal from the first terminal  13 , while the gate of the PMOS  46   b  receives the standby signal STBY. The gate of the NMOS  46   c  receives a signal obtained by inverting the standby signal by an inverter  46   e.    
     The operation of the oscillating circuit of the fourth embodiment will now be described. 
     If the switch  12  is ON in a normal operation mode, wherein the standby signal STBY is L level, then the oscillation using the crystal oscillator  11  is carried out. Since the standby signal STBY is L level, the PMOS  46   b  and the NMOS  46   c  turn ON. The ON resistance of the PMOS  45   a  and the NMOS  45   b  works as feedback resistance. The three-state inverter  46  and the resisting means  45  make up an inverting amplifier. This allows the crystal oscillating circuit to continue oscillation by using the crystal oscillator  11 . The NOR gate  16  sets the logic for the oscillating signal, which is output signal of the three-state inverter  46 . The NOR gate  16  outputs the output signal based on the output signal of the three-state inverter  46  to a circuit in the following stage. 
     The crystal oscillating circuit is able to receive a clock signal CLK from outside and output an oscillating signal to the circuit in the following stage. When the clock signal is received from outside, the switch  12  is turned OFF to isolate the first terminal  13  from the crystal oscillator  11 . The incoming clock signal CLK is supplied to the three-state inverter  46  via the first terminal  13 . Depending upon the level of the clock signal CLK, the three-state inverter  46  connects the output terminal O 46  to the power source VDD or the ground GND, then sets the voltage of the output terminal O 46  and outputs it. The NOR gate  16  outputs a signal based on the voltage of the output terminal O 46  of the three-state inverter. 
     In a low power consumption mode, wherein the standby signal STBY is H level, the PMOS  46   b  and the NMOS  46   c  of the three-state inverter  46  turn OFF. This isolates the output terminal O 46  from the ground GND and the power source VDD. Hence, even if the oscillation using the crystal oscillator  11  is being performed, the three-state inverter does not supply an oscillating signal to the NOR gate  16 . The NOR gate fixes its own output to the ground GND since the standby signal is L level. 
     Even if a clock signal CLK is being received from outside, the output terminal O 46  is isolated from the ground GND and the power source VDD. Further, since the output of the NOR gate  16  is fixed, no oscillating signal based on the clock signal is supplied to a circuit in the following stage. This means that the circuit in the following stage is set for the low power consumption mode. 
     If the standby signal STBY is switched to the H level, the PMOS  46   b  and the NMOS  46   c  turn OFF. At this time, the output terminal O 46  is cut off from the power source VDD and the ground GND. As a result, even if, for example, the clock signal CLK supplied to the first terminal  13  is switched to the H level, no current flows from the first terminal  13  to GND via the switch circuit  45  and the output terminal O 46 . 
     In the first through third embodiments, the MOS&#39;s have been used for the switch circuit; alternatively, however, bipolar transistors may be used instead. 
     In the fourth embodiment, an or gate may be used in place of the nor gate.