Abstract:
A sample and hold circuit including a capacitor is charged to a sample voltage from an open loop circuit such as a transistor circuit controlled by an input voltage. The sample voltage on the capacitor is converted to a digital signal via an ADC (Analog to Digital Converter). A digital correction circuit compensates for differences in voltage between the sample voltage on the capacitor and the input voltage based on properties of the open loop circuit and successive sample voltages on the capacitor. Consequently, nonlinearities can be compensated so that use of an open loop circuit or transistor circuit is less likely to negatively impact an overall accuracy of the ADC device.

Description:
RELATED APPLICATION(S) 
     This application claims the benefit of U.S. Provisional Application No. 60/287,394 filed on Apr. 30, 2001, the entire teachings of which are incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     Closed loop sample and hold circuits are often used in ADC (Analog-to-Digital Converter) circuits because of their high precision. In some cases, their precision is only limited by second-order effects related to switch non-linearities and buffer skewing. One notable drawback of using closed loop circuits in ADCs is their slow speed that results from the effects of feedback. 
     In contrast to closed loop circuits, open loop sample and hold circuits can be used in the fastest ADC circuits because of their ability to handle high speed signals (provide high input bandwidth) and reasonable power consumption. Open loop circuits typically employ at least one circuit in a feed-forward loop, in which non-linearities are not corrected by feedback. Thus, even though open loop circuits are fast, their use often results in additional circuit non-linearities that negatively impact the accuracy of a corresponding ADC device. 
     SUMMARY OF THE INVENTION 
     One aspect of the present invention is directed towards compensating open loop circuits in ADC devices. In an illustrative embodiment, a sample and hold circuit including a capacitor is charged to a sample voltage from an open loop circuit such as a transistor circuit controlled by an input voltage. The sample voltage on the capacitor is converted to a digital signal via an ADC (Analog to Digital Converter). A digital correction circuit compensates for differences in voltage between the sample voltage on the capacitor and the input voltage based on properties of the circuit and successive sample voltages on the capacitor. Consequently, nonlinearities can be corrected so that use of an open loop circuit or transistor circuit is less likely to negatively impact an overall accuracy of the ADC device. 
     In one application, the system for converting an analog input voltage includes multiple sample and hold circuits. For example, a first open loop sample and hold circuit can include a capacitor charged to a first sample voltage from a first transistor controlled by the input voltage. Additionally, a second open loop sample and hold circuit can include a capacitor charged to a second sample voltage from a second transistor also controlled by the input voltage. A digital correction circuit can compensate for non-linearities of at least one of the open loop circuits based on properties of the transistors and sample voltages on the capacitors at different times. More specifically, sample voltages on corresponding sample and hold circuits that track the input voltage can be converted at skewed sample times to compensate for non-linearities or device properties. 
     Each sample and hold circuit can include a current source to bias a transistor to produce a sample voltage on a corresponding capacitor. For example, an input voltage to be converted to a digital value can be applied to the base of a biased transistor. The output of the transistor, such as the emitter, can be coupled to charge the capacitor to a sample voltage. As discussed, the sample voltage on the capacitor can be fed to an ADC device for conversion. 
     A control circuit can be used to selectively couple the input voltage to the transistor and selectively activate a current source to bias the transistor. For example, the control circuit can control a switch that connects the input voltage to the transistor. Another switch can connect a current source to bias the transistor. Consequently, during a tracking mode, the input voltage can be coupled to the transistor to produce a sample voltage on the capacitor. During a hold mode, the capacitor stores the sample voltage and can be isolated from biasing and a potentially changing input voltage. 
     A digital correction circuit can correct for at least one non-linearity in an open loop circuit or transistor by accounting for an approximate current drawn by the capacitor as a result of a changing input voltage. One technique of correcting the non-linearities imparted by an open loop circuit is to approximate how much current is drawn by the capacitor during a charging period. Based on this information and other characteristics of the corresponding sample and hold circuit, the input voltage can be estimated. 
     In a specific application, the current drawn by the capacitor during a charge period can cause a voltage drop across the transistor depending on a changing input voltage. By calculating or approximating the current through the capacitor at the time of sampling, a corresponding portion of voltage drop between the input voltage and sample voltage caused by the current through the capacitor can be estimated. Accordingly, a precise value of the input voltage can be more accurately determined by compensating for the non-linearities of the open loop circuit. 
     The value of the input voltage at a particular time can be estimated using analog-to-digital conversions of sample voltages on the capacitor at two or more skewed sample times. For example, it is known that the sample voltage approximately tracks the input voltage as a consequence of the open loop circuit driving the capacitor. That is, the input voltage can drive an open loop gain circuit such as an emitter follower circuit to store a sample voltage on the capacitor. Values of multiple sample voltages on the capacitor can be used to identify how the input voltage changes over time. Based on how the sample voltage on the capacitor changes over time, the amount of current drawn by the capacitor and, hence, voltage drop across the transistor caused by a changing input voltage can be determined. 
     As previously discussed, multiple sample and hold circuits driven by a common input voltage can be implemented to accurately estimate the input voltage. A first sample voltage can be produced by a first open loop circuit and a second sample voltage can be produced by a second open loop circuit. A delay element to offset sample clocks of the first and second open loop circuits can be used to obtain corresponding time delayed sample voltages that are used to estimate an actual value of the input voltage. 
     The techniques according to the principles of the present invention are advantageous over the prior art. For example, an inherently fast open loop circuit such as a transistor in an emitter follower configuration can be used in a sample and hold circuit of an ADC device without foregoing overall converter accuracy. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. 
     FIG. 1 is a diagram of an open loop ADC circuit according to certain principles of the present invention. 
     FIG. 2 is a graph illustrating a sample voltage on a capacitor and how it tracks an input voltage according to certain principles of the present invention. 
     FIG. 3 is a graph illustrating correction of non-linearities of a circuit according to certain principles of the present invention. 
     FIG. 4 is a block diagram of an analog-to-digital converter device according to certain principles of the present invention. 
     FIG. 5 is a block diagram of an analog-to-digital converter device according to certain principles of the present invention. 
     FIG. 6 is a graph illustrating a technique of sampling an input voltage using multiple sample and hold circuits according to certain principles of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A description of preferred embodiments of the invention follows. 
     FIG. 1 is a circuit diagram of an ADC device according to certain principles of the present invention. In general, compensation techniques can be used to account for non-linearities in sample and hold circuit  110 . Although sample and hold circuit  110  is shown as an emitter follower circuit including transistor  140  and capacitor  160 , any suitable substitute circuit can be used in its place according to the principles of the present invention. 
     As shown, analog input signal  105 , V input , is fed into input buffer circuit  120 . An output of buffer circuit  120  is fed to switch  130 . Typically, the output of circuit  120  is a tracking voltage of V input . For example, when input buffer circuit  120  is set to unity gain, the output of buffer circuit  120  is equal to input voltage  105 . 
     During operation, switch  130  as well as switch  132  are selectively activated based on control signals from control circuit  135 . When sample and hold circuit  110  is in a tracking mode, both switches are set to a closed position so that input voltage  105  is applied to base of transistor  140  and current source  150  drives current through switch  132  to bias transistor  140 . 
     It should be noted that although transistor  140  is shown as a bipolar junction NPN transistor, any suitable transistor types such as analogous MOSFET (Metal Oxide Semiconductor Field Effect Transistor) devices and circuits can be substituted in place of transistor  140 . Of course, such a component or circuit substitution may require analogous modifications to sample and hold circuit  110 . 
     Current source  150  can be a constant current source so that transistor  140  operates in the forward-active mode when switch  132  is closed. Consequently, voltage V B  which is equal to V input  drives transistor  140  to produce a voltage on capacitor  160 . During the tracking mode, current source  150  biases transistor  140  to produces a sample voltage on capacitor  160 . Generally, the sample voltage on capacitor  160  is equal to the input voltage  105  less the voltage across the base/emitter of transistor  140 . 
     Control circuit  135  can turn off switches  130  and  132  to disconnect current source  150  and input voltage  105  from transistor  140 . In this “hold” mode, the voltage on capacitor  160  is a steady value and can be converted by ADC  180 . Output buffer circuit  170  couples the voltage on capacitor  160  to ADC  180  for conversions. The output of ADC  180  is fed to digital compensation circuit  190 . In general, according to certain principles of the present invention, techniques are used to compensate for properties of open loop sample and hold circuit  110 . For example, current drawn by capacitor  160  while in a tracking mode can result in a corresponding voltage drop across V BE , causing inaccurate ADC readings. 
     Additional current in excess of I SOURCE  from current source  150  flows through the emitter of transistor  140  when V input  changes over time. This current from emitter of transistor  140  is used to charge capacitor  160 . The current, I c , through capacitor  160  causes the difference voltage V BE  to vary depending on variations of the input voltage. Specific compensation or correction techniques will be discussed in more detail later in this specification. 
     Transistor  140  can exhibit dynamic nonlinearities in driving capacitor  160 , owing to the current dependence of the device base-emitter voltage V BE . As discussed, current source  150  can provide a fixed bias current I SOURCE , but capacitor  160  draws a portion of this current proportional to the rate of voltage change across capacitor  160  away from the emitter of transistor  140 . The resulting modulation of the base-emitter of transistor  140  can be mathematically characterized by the exponential (hence nonlinear) relationship:                I   emitter     =       I   s                 V   BE       V   T                   (eq.  1)                                
     where 
     I emitter =current through emitter of transistor  140 , 
     I S =transistor saturation current 
     V BE =Voltage across base-emitter 
     V T ≅thermal voltage constant of approximately 26 mV @ room temperature 
     Current through capacitor  160  causes nonlinearities in the final voltage across the capacitor after the sampling switch opens. These nonlinearities are not corrected by any closed loop feedback loops. Feedback loop  122  is sometimes implemented to ensure correct turn-off operation, and does not alter this situation. 
     Closed loop techniques can usually be applied to the input buffer circuit  120  because it does not need to drive a large load. In contrast, the output buffer drives the ADC input, which can be large relative to the sampling capacitance. It does so only with a constant sampled input and does not need to track a high bandwidth signal. Output buffer circuit  170  therefore can be a closed loop device also. 
     FIG. 2 is a graph of an input voltage versus time according to certain principles of the present invention. As shown, V B  (voltage of base on transistor  140 ) is effectively input voltage  105  when switch  130  is closed. V capacitor  represents input voltage  105  less the voltage drop, V BE , across base/emitter of transistor  140 . A portion of time period, T, is used to hold (designated t hold ) a sample voltage on capacitor  160  to convert the value to a digital output, while a balance of a time period is used to track (designated t track ) the input voltage  105  as previously discussed. 
     The voltage on capacitor  160  can be used to determine the value of input voltage  105 . More specifically, an actual value of input voltage  105  can be estimated by identifying the voltage on capacitor  160  and adding voltage drop V BE  caused by bias current, I S . 
     In general, the value of V BE  is effected by at least two currents. For example, when switches  130  and  132  are “on”, current source  150  draws a constant bias current I source  through the emitter of transistor  140 . Current i c  through capacitor  160  varies as a result of a changing input voltage  105  and also affects V BE  Thus, the current flowing through capacitor  160  affects the dynamics of the sample and hold circuit. As discussed, the variability of current through capacitor  160  can be estimated to compensate for a drop across V BE  according to the principles of the present invention. 
     FIG. 3 is a graph that more particularly illustrates a technique for estimating a current through a capacitor based on successive sample voltages. It is known that I c =           I   c     =     C                        v          t           ,                          
     which can be estimated using dV/dt illustrated by equation 2 at time t 2 . 
     The actual current through capacitor  160  at time t 2  can be estimated by drawing an imaginary line through time points t 1 , and t 2  of signal V capacitor . Specifically, the current through capacitor at time t 2  can be estimated based on the following equation:                  I   c          (     t   2     )       =         C                        V          t         ≅     C                     Δ                 V       Δ                 t           =     C                     [         V   capacitor          (     t   2     )       -       V   capacitor          (     t   1     )         ]         t   2     -     t   1                     (eq.  2)                                
     This estimated value of I c  can be substituted into the above equations to more precisely calculate the effective input voltage  105  at a given point in time. Note that I c (t)=0 only if V B  and thus V capacitor  is constant. 
     V B (t) is the voltage we wish to accurately measure. If we assume V BE  is constant, V BE  itself becomes an offset and is unimportant in terms of linearity effects. One aspect of the present invention is to measure deviations from this offset, not necessarily the absolute value of V BE  itself. 
     Let the nth sample of the emitter voltage measured be V E (n) and the previous and subsequent samples be V E (n−1) and V E (n+1) respectively, as shown in FIG. 2 for a representative waveform. We can also write:                I   emitter     =         I   SOURCE     +     I   c       =       I   s                 V   BE       V   T                     (eq.  3)                                
     Therefore,                V   BE     =         V   T          ln        (         I   SOURCE     +     I   c         I   s       )         =       V   B     -     V   E                 (eq.  4)                                
     and                  V   B     =       V   E     +       V   T          ln        (         I   SOURCE     +     I   c         I   s       )             ,           (eq.  5)                                
     where 
     V B =desired voltage of base to be determined 
     V L =measured voltage of emitter or capacitor 
     I SOURCE =bias current of source  150   
     I c =current through capacitor  160   
     I S =saturation current of transistor 
     Since I SOURCE  and I S  are known or can be calculated, we can calculate V B (n) accurately (and hence the deviation from the ideal          V   T          ln        (     I     I   s       )                              
     value) if we accurately knew                  I   c          (   n   )       =     C                          V   E            t                     for                 a                 given                 time                     t   n     .               (eq.  6)                                
     The computation can be done digitally as a post-processing operation. The implementation of the function in digital logic is well known. It can be done in many ways including look-up tables and power series approximations. The method depends on estimating I c (n). Two useful alternative equations for estimating I c  in the above equation are as follows:                  I   c          (   n   )       ≅     C                         V   E          (   n   )       -       V   E          (     n   -   1     )         T               (eq.  7)                                                I   c          (   n   )       ≅     C                         V   E          (     n   +   1     )       -       V   E          (     n   -   1     )           2      T                 (eq.  8)                                 
     It should be noted that higher order mathematical equations also can be used to approximate a the current going through the capacitor. 
     In general, the closer together are the timepoints referred to in the equation, and the closer they are to the nth timepoint, the more accurate the estimate of the derivative so long as the sampling period is considerably less than the input signal period. Using timepoint measurements to estimate the derivative of I c  may therefore be inappropriate in undersampled situations if high frequency measurements of the input are required. If the high frequency data is unimportant however, the ADC can still be made to reject it correctly. We make this observation on two grounds: first the value of V E  is low pass filtered by the sampling capacitor, and can be set to reject high frequency, and secondly the calculation of the current based on the values of V E  will then not include the rapidly changing components of the current. 
     FIG. 4 is a block diagram of an alternative ADC circuit embodiment. As shown, input voltage  105  is fed into respective sample and hold circuits  110 - 1  and  110 - 2 . Any suitable number of sample and hold circuits  110  can be used even though only two are shown. Typically, a single ADC will run at double the speed than a case when two separate ADCs are used as in FIG.  5 . 
     Referring again to FIG. 4, sample clock  402  is fed into sample and hold circuit  110 - 1  to control track and hold periods. Delay element  410  skews sample clock  402  by a skew time of t skew . Based on the delayed or skewed clock, sample and hold circuit  110 - 2  tracks and holds sampling of input voltage  105  a delayed amount of time. In one application, the skew time is smaller than a single system clock cycle. 
     Both outputs of sample and hold circuits  110 - 1  and  110 - 2  are fed to multiplexer  420 , which selectively connects sample voltages of corresponding capacitors to ADC  180  at skewed times. In general, use of multiple sample and hold circuits  110  allows input voltage  105  to be more closely tracked and sampled by a common ADC  180 . Consequently, errors imparted by ADC  180  cancel because a common ADC device is used to perform conversions. 
     Two slower or half-speed ADCs can be used but mismatch of circuits may result. This mismatch can be can be corrected using calibration techniques. 
     FIG. 5 is a block diagram of an ADC circuit including multiple ADC devices  180 - 1  and  180 - 2  instead of the multiplexer and single ADC  180  of FIG.  4 . Mismatch resulting from multiple ADC devices can be reduced using calibration techniques. 
     FIG. 6 illustrates a voltage versus time graph for sample and hold circuits according to certain principles of the present invention. 
     As shown, input voltage  105  is sampled at two skewed samples times namely, t 1  and t 1 +t skew . Each sample and hold circuit tracks the same input voltage but samples at different times. A more accurate estimate of current through capacitor  160  can be determined using the equation:            I   c2          (       t   1     +     t   skew       )       ≅         C   2          [         V   capacitor2          (       t   1     +     t   skew       )       -       V   capacitor1          (     t   1     )         ]         t   skew                              
     Generally, the estimated slope of V capacitor  more nearly reflects the actual slope of V capacitor  as t skew  goes to zero. Thus, multiple sample/hold circuits can be used to more accurately determine an actual value of the input voltage at a particular point in time. 
     As shown in FIG. 4, a single ADC at 2X speed can be used to perform conversions. 
     Based on the above equations, an approximated value of I c  can be substituted into equation 5 to determine a more accurate value of the input voltage. As mentioned, the other terms in the equation are known and can be measured. 
     In one application, the value of the input voltage is determined based on a difference voltage applied to a look-up table. For example, the voltage of the capacitor at two different sample times can be input to a lookup table, an output of which is the a digital sequence identifying a value of the input voltage. 
     In one embodiment, equation 1 is simply used to calculate V B  given the current, using conventional DSP (Digital Signal Processing) circuitry. 
     While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.