Abstract:
An improved method for forming a copper layer ( 100 ). After the copper seed layer ( 116 ) is formed, any oxidized copper ( 118 ) at the surface is electrochemically reduced back to copper rather than being dissolved. Copper ( 120 ) is then electrochemically deposited (ECD) over the intact seed layer ( 116 ).

Description:
FIELD OF THE INVENTION  
         [0001]    The invention is generally related to the field of forming copper interconnects in semiconductor devices and more specifically to electrochemically reducing the copper seed for reducing voids.  
         BACKGROUND OF THE INVENTION  
         [0002]    Copper (Cu) metallization is gaining momentum in replacing aluminum (Al), particularly for the 0.18 um technology node and beyond. Due to the difficulty in dry etching Cu, a damascene approach is widely used for Cu metallization. This requires the Cu metallization process to have a high gap fill capability. The sputtering process widely used for Al metallization is not applicable to Cu metallization due to its inherent limitation in step coverage. Chemical vapor deposition (CVD) used in tungsten (W) metallization is not preferred for Cu at this time due to issues with morphology, adhesion and the conformal nature (seam formation issue) of CVD Cu films. Currently, the only manufacturable process for depositing Cu for interconnect applications is electrochemical deposition (ECD), thanks to its bottom-up fill capability.  
           [0003]    Electrochemical deposition (ECD) is a process to produce solid phase product (such as thin films) by electrochemical reactions. Cu ECD is a process to make Cu thin film through electrochemical reduction of Cu ion, represented by the following electrochemical equation:  
           Cu ++ +2 e   − →Cu where e −  represents electron  
           [0004]    In order for ECD process to proceed, a copper seed layer is required to pass current and to serve as a nucleation layer. However, the surface condition of the copper seed layer is very difficult to control in a manufacturing environment with prior arts. A copper seed surface exposed to air can readily be oxidized, forming a surface copper oxide layer. The oxide layer degrades the seed-plated Cu interface. Cu oxide also can be dissolved in acidic plating solution. When the copper seed is thin (particularly near the bottom of small device features, such as via and trench), the oxidization and dissolution can cause discontinuity of the seed layer, the major cause of ECD via bottom void. This impacts negatively on via chain yield and device reliability. In addition to seed surface oxidation, Cu seed can also adsorb organic contaminants when exposed to the fab ambient, which degrades surface wettability that can also cause voids in Cu films.  
         SUMMARY OF THE INVENTION  
         [0005]    The invention is an improved method for forming a copper layer. After the copper seed layer is formed, any oxidized copper at the surface is electrochemically reduced back to copper rather than being dissolved. Copper is then electrochemically deposited (ECD) over the intact seed layer.  
           [0006]    An advantage of the invention is providing a method of forming a copper layer that minimizes the formation of voids.  
           [0007]    This and other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]    In the drawings:  
         [0009]    [0009]FIG. 1 is a cross-sectional diagram of a copper interconnect formed according to an embodiment of the invention;  
         [0010]    FIGS.  2 A- 2 D are cross-sectional diagrams of the copper interconnect of FIG. 1 at various stages of fabrication; and  
         [0011]    [0011]FIG. 3 is a graph of voltage versus time comparing air exposed copper to electrochemically reduced copper.  
     
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS  
       [0012]    The invention will now be described in conjunction with dual damascene copper interconnect process. It will be apparent to those of ordinary skill in the art having reference to the specification that the benefits of the invention may be applied to ECD copper in general where a reduction of the seed layer surface is desired.  
         [0013]    A dual damascene copper interconnect  100  formed according to the invention is shown in FIG. 1. Copper interconnect  100  is formed over semiconductor body  102 . Semiconductor body  102  typically has transistors and other devices (not shown) formed therein. Semiconductor body  102  may also include one or more additional metal interconnect layers  104 . Copper interconnect  100  comprises a lead portion formed within trench  108  and a via portion formed within via  106 . Via  106  extends from the bottom of trench  108  through interlevel dielectric (ILD)  110  to a lower metal interconnect layer  104 . Trench  108  is formed within intrametal dielectric (IMD)  112 . Various materials are known to be suitable for forming ILD  110  and IMD  112 . For example, fluorine-doped silicate glass (FSG), organo-silicate glass (OSG), or other low-k or ultra low-k dielectrics may be used.  
         [0014]    A barrier layer  114  is located between the copper interconnect  100  and the trench  108  and via  106  sidewalls. Barrier layer  114  prevents copper from diffusing into the ILD  110  and IMD  112 . Barrier layer  114  also provides adhesion between the copper and dielectric. Various barrier layers are known in the art. For example, refractory metals, refractory metal-nitrides, refractory metal-silicon-nitrides, or combinations thereof may be used.  
         [0015]    Voids in copper interconnect  100  are minimized or eliminated. Because the invention reduces the copper oxide at the surface of the seed layer (as discussed further below), the seed layer remains continuous. Discontinuities in the seed layer are responsible for the formation of voids in the ECD copper layer. Fewer discontinuities result in fewer voids.  
         [0016]    A method of fabricating copper interconnect  100  according to the invention will now be discussed with reference to FIGS.  2 A- 2 D. Referring to FIG. 2A, semiconductor body  102  is processed through the formation of one or more metal interconnect layers  104 . ILD  110  and IMD  112  are deposited over semiconductor body  102 . Suitable materials, such as FSG or OSG, for ILD  110  and IMD  112  are known in the art. Trench  108  is formed in IMD  112  and via  106  is formed in ILD  110 , using conventional processing.  
         [0017]    Barrier layer  114  is formed over IMD  112  including within trench  108  and via  106 . Barrier layer  114  functions as a diffusion barrier to prevent copper diffusion and as an adhesion layer. Transition metals and their nitrides are typically used for barriers. A transition metal-silicon nitride as well as combinations of transition metals, transition metal-nitrides and transition metal-silicon-nitrides may also be used.  
         [0018]    Still referring to FIG. 2A, a copper seed layer  116  is deposited over barrier layer  114 . Physical vapor deposition is traditionally used to form copper seed layer  116 . The copper seed layer  116  is needed to pass current and to serve as a nucleation layer for the copper ECD process.  
         [0019]    After deposition of the copper seed layer  116 , the wafer is transferred to the ECD tool. A copper seed surface exposed to air can readily be oxidized, forming surface copper oxide layer  118 , as shown in FIG. 2B. The oxide layer  118  degrades the seed-plated Cu interface. Cu oxide also can be dissolved in acidic plating solution. When the copper seed is thin (particularly near the bottom of small device features, such as via and trench), the oxidization and dissolution can cause discontinuity of the seed layer, the major cause of ECD via bottom void. Accordingly, after the deposition of a Cu seed layer, the wafer is transferred to an electrochemical cell with an electrolyte solution of high pH (&gt;/=4). The surface oxide layer is reduced electrochemically by applying cathodic current through the Cu seed layer. The result is shown in FIG. 2C The process can be expressed as follows:  
         CuO X   +Xe   −+XH   2 O→Cu+2 XOH   −  where e represents electron.  
         [0020]    Electrolyte solutions with high pH are used to prevent dissolution of the copper oxide layer before the reduction. The electrolytes can be chosen from the following list: H 3 BO 3 +(CH 3 ) 4 NOH, H 3 BO 3 +Na 2 B 4 O 7 , (NR 4 )(BF 4 ), (NR 4 )(PF 6 ), where R stands for alkyl group, or other stable electrolytes with pH&gt;4. The waveform and current (voltage) are controlled to make sure only the copper oxide is reduced and hydrogen evelution will not occur. This can be achieved by fixing the total coulomb for the process so the charge passed is only sufficient for copper oxide reduction. Voltage control is preferred in the electrochemical reduction process to ensure no hydrogen evolution occurs while the oxide reduction is complete. Depending on the electrolyte solution (pH numbers are different for different electrolyte solutions) used, a voltage in the range of −0.2 to −1.0V may be used, for example.  
         [0021]    After the electroreduction, the wafer is rinsed with deionized water and dried (by spinning and/or blowing an inert gas over the wafer). The rinse/dry process also helps remove surface organic contaminants, in addition to cleaning electrolyte residues. The wafer is then transferred under an inert ambient (such as N 2 ) to the plating cell. The plating cell is preferably in the same cluster tool as the electroreduction cell. Alternatively, it can be performed in a separate machine. The inert ambient is preferred to ensure the reduced surface is not significantly re-oxidized before the plating occurs. If the inert atmosphere cannot be achieved, this approach will still offer an advantage in minimizing the oxide thickness on copper seed.  
         [0022]    Once in the plating cell, a copper ECD process is performed. Various copper ECD processes are known in the art. In one example, a 3-step process is used. After placing the wafer in the plating solution, a current of approximately 0.75 Amps is passed through the seed layer for a time on the order of 15 secs. The current is then increased to around 3 Amps for approximately 60 seconds. Final plating occurs at a current of about 7.5Amps with the duration determined by the final desired thickness. A quick spin-rinse dry (SRD) is performed in the plating cell above the plating solution. The wafer is then transferred to the SRD cell and a post-ECD SRD is used to clean the plating residue. The resulting copper layer  120  is shown in FIG. 2D.  
         [0023]    After the ECD process, the copper layer  120  (which incorporates seed layer  116 ) and barrier layer  114  are chemically-mechanically polished to form copper interconnect  100 , as shown in FIG. 1. Processing may then continue to form additional metal interconnect layers and to package the device.  
         [0024]    [0024]FIG. 3 shows the results of a feasibility test. In this test, a typical copper seed wafer, with approximately 1400 Å of copper seed, was determined to have 22 Å of Cu 2 O and 1 Å of CuO on the surface by SERA resulting from exposure of the copper surface to the fab atmosphere. SERA is Sequential Electrochemical Reduction Analysis whereupon the copper oxides are determined by chronopotentiometry employing aqueous buffer solution. After electrochemical reduction of the copper oxides in inert atmosphere employing borate buffer, the SERA scan reveals no Cu 2 O or CuO. Thus, the copper oxides on the surface of a copper seed wafer can be reduced electrochemically under inert atmosphere to generate a pristine copper surface just prior to electrochemical deposition of copper. For the sample shown in FIG. 3, a sequential electrochemical reduction in the voltage range of −0.4 to −0.8V was used.  
         [0025]    While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. For example, the benefits of the invention may be applied to forming the first metal interconnect layer. It is therefore intended that the appended claims encompass any such modifications or embodiments.