Abstract:
A method for forming feature on a substrate includes forming at least one layer of a feature material on a substrate, patterning a photolithographic resist material on the at least one layer of the feature material, removing portions of the feature material to define a feature, depositing a masking material layer over the resist material and exposed regions of the substrate, modifying a portion of the substrate, and removing the masking material layer and the resist material.

Description:
BACKGROUND 
       [0001]    The present invention relates to field effect transistor devices, and more specifically, to methods for fabricating field effect transistor devices. 
         [0002]    Field effect transistor devices often include a gate stack disposed on a silicon substrate. Source and drain regions may be formed adjacent to the gate stack using ion implantation methods. High energy ion implantation methods are useful for implanting ions deeply in the source and drain regions, however high energy implantation methods may undesirably damage existing structures that have been formed on the substrate. 
       BRIEF SUMMARY 
       [0003]    According to one embodiment of the present invention, a method for forming feature on a substrate includes forming at least one layer of a feature material on a substrate, patterning a photolithographic resist material on the at least one layer of the feature material, removing portions of the feature material to define a feature, depositing a masking material layer over the resist material and exposed regions of the substrate, modifying a portion of the substrate, and removing the masking material layer and the resist material. 
         [0004]    According to another embodiment of the present invention, a method for forming a field effect transistor device includes forming layers of gate stack materials on a substrate, patterning a photolithographic resist material on the layers of gate stack materials, removing portions of the gate stack materials to define a gate stack, depositing a masking material layer over the resist material and exposed regions of the substrate, removing portions of the masking material layer to define a spacer, and implanting ions in the substrate. 
         [0005]    According to yet another embodiment of the present invention, a method for forming a field effect transistor device includes forming layers of gate stack materials on a substrate and over a source and drain extension portion disposed on the substrate, patterning a photolithographic resist material on the layers of gate stack materials, removing portions of the gate stack materials to define a gate stack, depositing a masking material layer over the resist material and exposed regions of the substrate and the source and drain extension portion, removing portions of the masking material layer to define a spacer, and implanting ions in the source and drain extension region. 
         [0006]    Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the advantages and the features, refer to the description and to the drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0007]    The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which: 
           [0008]      FIGS. 1-5  illustrate a side cut-away view of an exemplary method for fabricating a field effect transistor (FET) device, in which: 
           [0009]      FIG. 2  illustrates the resultant structure following the removal of portions of the gate material layer and the capping layer; 
           [0010]      FIG. 3  illustrates the deposition of a masking layer; 
           [0011]      FIG. 4A  illustrates the implantation of ions; 
           [0012]      FIG. 4B  illustrates the removal of portions of the substrate; and 
           [0013]      FIG. 5  illustrates the resultant structure following the removal of the masking layer and the resist material. 
           [0014]      FIGS. 6-9  illustrate an alternate exemplary method for forming a FET device, in which: 
           [0015]      FIG. 7  illustrates the resultant structure following the removal of portions of the masking layer; 
           [0016]      FIG. 8  illustrates the implantation of ions; 
           [0017]      FIG. 9  illustrates the resultant structure following the removal of the spacers and the resist material; 
           [0018]      FIGS. 10-14  illustrate a side cut-away view of an alternate exemplary method for forming a multi-gate field effect transistor device, in which: 
           [0019]      FIG. 10  illustrates a portion of a multi-gate field effect transistor device; 
           [0020]      FIG. 11  illustrates the deposition of a masking layer; 
           [0021]      FIG. 12  illustrates the resultant structure following the removal of portions of the masking layer; 
           [0022]      FIG. 13  illustrates the implantation of ions; and 
           [0023]      FIG. 14  illustrates the resultant structure following the removal of the spacers. 
       
    
    
     DETAILED DESCRIPTION 
       [0024]    Field effect transistor devices (FETs) include source and drain regions that may be formed by ion implantation methods following the formation of a gate stack on a substrate. High energy ion implantation methods increase the penetration of ions in features that are exposed to the ions. In this regard, a protective masking layer is applied over regions of the device such as the gate stack and proximal substrate to prevent ion implantation in undesirable regions. Forming a photoresist masking layer over a gate stack following the formation of the gate stack is problematic since precisely aligning a photoresist mask over the gate stack may be difficult. Thus, a method for self aligning a masking layer to protect a gate stack and portions of the source and drain regions during ion implantation is desired. 
         [0025]      FIGS. 1-4B  illustrate a side cut-away view of an exemplary method for fabricating a field effect transistor (FET) device. Referring to  FIG. 1 , a substrate  100  includes a first silicon layer  102 , a dielectric layer  104  disposed on the first silicon layer  102 , and a second silicon layer  106  disposed on the dielectric layer  104 . The substrate  100  of the illustrated embodiment is merely an example, any other type of substrate arrangement may be used in alternative embodiments. A gate material layer  108  is formed on the second silicon layer  106 , and a capping layer  110  is formed on the gate material layer  108 . The gate material layer  108  may include, for example, a gate oxide material (e.g., SIO 2 ) or another dielectric material. The capping layer  110  in the illustrated embodiment includes a polysilicon material. In alternate embodiments, any combination of gate material layers and capping layers may be formed to fabricate any type of gate (e.g., a metal oxide FET, or carbon based FET). A photolithographic resist material  112  is patterned on the capping layer  110 . 
         [0026]      FIG. 2  illustrates the resultant structure following the removal of portions of the gate material layer  108  and the capping layer  110  by an anisotropic etching process such as, for example, an reactive ion etching (RIE) process. The resultant structure includes exposed regions of the substrate  100  and a gate stack  202  feature. Though the illustrated embodiment includes the gate stack  202 , such an embodiment is merely an example. Alternate embodiments are not limited to gate stack structures, and may include, for example, any feature or structure that may be formed on the substrate  202 . In this regard, the gate stack  202  may represent a structure or feature such as a protuberance, projection, or protrusion formed on or in the substrate  202 . For illustrative purposes, such a structure or feature is represented as the gate stack  202 . 
         [0027]      FIG. 3  illustrates the deposition of a masking layer  302  that is formed over the exposed portions of the substrate  100  and over the gate stack  202  and resist material  112 . The masking layer  302  may be deposited using, for example, a spin-on deposition process. The masking layer  302  may include any suitable material including such as, for example, an anti-reflective coating (ARC) material such as, silicon nitride, silicon oxynitride or a combination of different layered materials. 
         [0028]      FIG. 4A  illustrates the implantation of ions (indicated by the arrows  401 ) to form a doped source region  402  and drain region  404  in the substrate  100 . The ions  401  have enough energy to penetrate the horizontal portions of the masking layer  302  (i.e., the portions of the masking layer arranged parallel to the substrate  100  surface) however, the ions  401  do not have enough energy to penetrate the vertical portions  406  of the masking layer  302  resulting in regions  408  of the substrate  100  that remains undoped by the ions  401 . Though the illustrated embodiment of  FIG. 4  illustrates the implantation of ions  401  into the substrate  100 , alternate exemplary embodiments may include, for example, removing portions of the masking layer  302  and the substrate  100  using an etching process such as RIE as shown in  FIG. 4B . 
         [0029]      FIG. 5  illustrates the resultant structure following the removal of the masking layer  302  and the resist material  112  (of  FIG. 4 ) using an etching process such as, for example, a RIE process. 
         [0030]      FIGS. 6-9  illustrate an alternate exemplary method for forming a FET device.  FIG. 6  illustrates a resultant structure similar to the structure described above in  FIG. 3  following the formation of the masking layer  302 . 
         [0031]      FIG. 7  illustrates the resultant structure following the removal of portions of the masking layer  302  that exposes portions of the substrate  100  and defines spacers  702 . The portions of the masking layer  302  may be removed by, an anisotropic etching process such as, for example a RIE process. 
         [0032]      FIG. 8  illustrates the implantation of ions (indicated by the arrows  401 ) to form a doped source region  402  and drain region  404  in the substrate  100 . The spacers  702  protect portions of the substrate  100  resulting in regions  408  of the substrate  100  that remain undoped by the ions  401 . 
         [0033]      FIG. 9  illustrates the resultant structure following the removal of the spacers  702  and the resist material  112  (of  FIG. 8 ) using an etching process such as, for example, a RIE process. 
         [0034]      FIGS. 10-14  illustrate a side cut-away view of an alternate exemplary method for forming a multi-gate field effect transistor (MUGFET) device. Referring to  FIG. 10 , the illustrated embodiment includes a substrate  1000  that includes a silicon layer  1002  and a dielectric layer  1004  disposed on the silicon layer  1002 . Extensions or fins  1006  are disposed on the substrate  1000 . A gate stack  1008  that includes a gate material  108  and a capping layer  110  has been patterned over the extensions  1006  following the patterning of photoresist material  1010  and an anisotropic etching process that removes portions of the gate material  108  and the capping layer  110  to define the gate stack  1008 . 
         [0035]      FIG. 11  illustrates the deposition of a masking layer  302  over the extensions  1006 , the substrate  1000 , the gate stack  1008  and the photoresist material  1010  using, for example, a spin-on deposition process similar to the process described above. 
         [0036]      FIG. 12  illustrates the resultant structure following the removal of portions of the masking layer  302  that defines spacers  1202 . The spacers  1202  are formed along side walls of the gate stack  1008 ; the photoresist material  1010 ; and over portions of the extensions  1006  adjacent to the gate stack  1008 . The portions of the masking layer  302  may be removed using, for example, an anisotropic etching process such as, a RIE process. 
         [0037]      FIG. 13  illustrates the implantation of ions (indicated by the arrows  401 ) to form a doped source region  1302  and drain region  1304  in the extensions  1006 . 
         [0038]      FIG. 14  illustrates the resultant structure following the removal of the spacers  1202  (of  FIG. 13 ). The resultant structure includes regions  1402  in the extensions  1304  that remained undoped by the ions  401  due to the spacers  1202 . 
         [0039]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one more other features, integers, steps, operations, element components, and/or groups thereof. 
         [0040]    The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated 
         [0041]    The flow diagrams depicted herein are just one example. There may be many variations to this diagram or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention. 
         [0042]    While the preferred embodiment to the invention had been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.