Abstract:
The present invention generally relates to the three-dimensional arrangement of memory cells. This 3D arrangement and orientation is made with macro cells that enable the programming, reading and/or querying of any memory cell in the 3D array without the need for overhead wiring or by utilizing a minimal amount of overhead wiring. The individual macro cells are electrically coupled together such that a single transistor on the substrate can be utilized to address multiple macro cells. In such an arrangement, all the auxiliary circuits for addressing memory elements are simplified thereby diminishing their integrated circuit area.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     Embodiments of the present invention generally relate to a phase change memory (PCM) cell and an arrangement thereof. 
     2. Description of the Related Art 
     PCM is a type of non-volatile memory technology. PCM is an emerging technology and a candidate for storage class memory (SCM) applications and a serious contender to dislodge NOR and NAND flash memory in solid state storage applications and, in the case of NAND flash, solid-state drives (SSDs). PCM functions based upon switching a memory cell, typically based on chalcogenides such as Ge 2 Sb 2 Te 5 , between two stable states, a crystalline state and an amorphous state, by heating the memory cell. To heat the memory cell, an electrical current flows through the PCM cell. For an effective memory device, numerous PCM cells will be present in an array. Each of the PCM cells needs to be addressed, programmed and read with low overhead electrical wiring. The PCM cell is the phase-change cell itself, and PCM device, as discussed herein, is the set of PCM cells plus accompanying heaters (represented by a resistor in the electrical diagrams). The PCM device is the memory element herein. 
     An array  100  of PCM cells is frequently arranged with a selecting transistor  102  in series with each memory cell  104  as shown in  FIG. 1A . Word lines (WL) and bitlines (BL) are arranged so that each memory cell  104  can be programmed or queried. A row of PCM cells is activated by a single word line WL and each one of the PCM cells  104  in that row will affect the bitline BL to which it is electrically connected according to the state of the PCM cells  104 , i.e. according to the PCM cells  104  being in their high (amorphous) or low (crystalline) resistance state. As shown in  FIG. 1A , a simple array  100  of PCM devices  106  is shown. The array  100  is a two dimensional array because the PCM devices  106  are all arranged along a common plane. 
     In an alternative design commonly named “cross-point”, shown in  FIG. 1B . Each interception of word lines WL in the x direction and bit lines BL in the y direction has a PCM device  106 , which includes the PCM cell  104  itself and its heater (represented by a resistor). Frequently, a selecting device is added in series with the PCM device. This selecting device can be a diode or a transistor. The selecting device, diode or transistor, added to the cross-point array  110 , or alternatively, used externally to the array of PCM cells may frequently become the limiting factor on how dense can the PCM array become. 
     When the selecting device is added to the cross-point array, there will be one selecting device per PCM device  106 . Current requirements of the PCM device  106  need to be met by the selecting device. In consequence, even when the PCM device  106  can be made small to the lithographic limit and occupy only 4F 2  of area, where F is the half-pitch critical dimension in a lithographic technology, the selecting device might require 30F 2  if it is a CMOS transistor or 10F 2  if it is a bipolar transistor. Optimized diodes, where efforts to make them very conductive might attend the current requirement of a PCM device using 4F 2  area and are therefore very frequently considered as selecting device in cross point memories using PCM or any memory device requiring significant currents for operation. 
     Unfortunately, using diodes makes it very difficult to extend the concept of cross-point array  110  from a two-dimensional (2D) array to a three-dimensional (3D) array. In a 3D array, addressing the PCM devices  106  that are in the middle of the array is difficult. 
     Therefore, there is a need for a PCM device that permits each PCM cell to be accessed individually while minimizing the use of the surface area of the substrate over which the PCM device is disposed as well as minimizing the overhead wiring utilized to address PCM cells in the middle of the PCM 3D array. 
     SUMMARY OF THE INVENTION 
     The present invention generally relates to PCM cells and arrangements thereof. Even though the descriptions use PCM devices, this is only used for illustrative purposes. Other memory devices, such as a tunnel magnetoresistance (TMR) memory device, can be used as well without departing from the spirit of this invention. In one embodiment, a three-dimensional memory array comprises a first macro cell and a second macro cell. The first macro cell comprises a first three-terminal selecting device, which could be a metal semiconductor field effect transistor (MESFET) or another three-terminal selecting device; a first electrical connector coupled to the first three-terminal selecting device, the first electrical connector extending along a first axis and a second axis perpendicular to the first axis; a second electrical connector coupled to the first three-terminal selecting device; a first memory cell coupled to the second electrical connector, the first memory cell disposed along the second axis; and a third electrical connector coupled to the first memory cell, the third electrical connector extending along the second axis and a third axis perpendicular to both the second axis and the first axis. The a second macro cell comprises a second three-terminal selecting device; a fourth electrical connector coupled to the second three-terminal selecting device, the fourth electrical connector extends along a fourth axis that is parallel to the first axis, the fourth electrical connector also extends along the second axis, the fourth electrical connector is electrically coupled to the first electrical connector; a fifth electrical connector coupled to the second three-terminal selecting device; a second memory cell coupled to the fifth electrical connector, the second memory cell disposed along the second axis; and a sixth electrical connector coupled to the second memory cell, the sixth electrical connector extending along the second axis and a fifth axis that is parallel to the third axis, the sixth electrical connector is electrically coupled to the third electrical connector. An electrically insulating spacer is coupled between the third electrical connector and the fourth electrical connector. 
     In another embodiment, a three-dimensional memory array comprises a first macro cell and a second macro cell. The first macro cell comprises a first three-terminal selecting device; a first electrical connector coupled to the first three-terminal selecting device, the first electrical connector extending along a first axis and a second axis perpendicular to the first axis; a second electrical connector coupled to the first three-terminal selecting device; a first memory cell coupled to the second electrical connector, the first memory cell disposed along the second axis; and a third electrical connector coupled to the first memory cell, the third electrical connector extending along the second axis and a third axis perpendicular to both the second axis and the first axis. The second macro cell comprises a second three-terminal selecting device; a fourth electrical connector coupled to the second three-terminal selecting device, the fourth electrical connector extends along the first axis and a fourth axis that is parallel to the second axis and the second electrical connector is electrically coupled to the first electrical connector; a fifth electrical connector coupled to the second three-terminal selecting device; a second memory cell coupled to the fifth electrical connector, the second memory cell disposed along the fourth axis; and a sixth electrical connector coupled to the second memory cell, the sixth electrical connector extending along the fourth axis and a fifth axis that is parallel to the third axis. 
     In another embodiment, a three-dimensional memory array comprises a first macro cell, a second macro cell, and a third macro cell. The first macro cell comprises a first three-terminal selecting device; a first electrical connector coupled to the first three-terminal selecting device, the first electrical connector extending along a first axis and a second axis perpendicular to the first axis; a second electrical connector coupled to the first three-terminal selecting device; a first memory cell coupled to second electrical connector, the first memory cell disposed along the second axis; and a third electrical connector coupled to the first memory cell, the third electrical connector extending along the second axis and a third axis perpendicular to both the second direction and the first direction. The second macro cell comprises a second three-terminal selecting device; a fourth electrical connector coupled to the second three-terminal selecting device, the fourth electrical connector extends along the second axis and a fourth axis parallel to the first axis, the fourth electrical connector is electrically coupled to the first electrical connector; a fifth electrical connector coupled to the second three-terminal selecting device; a second memory cell coupled to the fifth electrical connector, the second memory cell disposed along the second axis; and a sixth electrical connector coupled to the second memory cell, the sixth electrical connector extending along the second axis and a fifth axis parallel to the third axis, the sixth electrical connector is electrically coupled to the third electrical connector. The three-dimensional memory array also comprises a first electrically insulating spacer coupled between the third electrical connector and the fourth electrical connector. The third macro cell comprises a third three-terminal selecting device; a seventh electrical connector coupled to the third three-terminal selecting device, the seventh electrical connector extending along the first axis and a sixth axis parallel to the second axis, the seventh electrical connector is electrically coupled to the first electrical connector; an eighth electrical connector coupled to the third three-terminal selecting device; a third memory cell coupled to the eighth electrical connector, the third memory cell disposed along the sixth axis; and a ninth electrical connector coupled to the third memory cell, the ninth electrical connector extending along the sixth axis and a seventh axis parallel to the third axis. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments. 
         FIG. 1A  is a schematic isometric view of a prior art memory cell  100 . 
         FIG. 1B  is a schematic cross-sectional view of a prior art memory cell  110 . 
         FIG. 2  is an isometric illustration of a macro cell  200  for use in a PCM cell according to one embodiment. 
         FIG. 3  is an isometric view of a PCM-based building block array  300  having two macro cells  200 A,  200 B arranged side by side. 
         FIG. 4  is a schematic isometric view of a PCM-based memory building block array  400  having a plurality of macro cells  200 A- 200 D arranged side by side. 
         FIG. 5  is a schematic isometric view of a 3D PCM-based memory array  500  having a plurality of macro cells  200 A- 200 H. 
         FIGS. 6A-6D  are schematic isometric illustrations of a 3D PCM-based array  600  according to one embodiment. 
     
    
    
     To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation. 
     DETAILED DESCRIPTION 
     In the following, reference is made to embodiments of the invention. However, it should be understood that the invention is not limited to specific described embodiments. Instead, any combination of the following features and elements, whether related to different embodiments or not, is contemplated to implement and practice the invention. Furthermore, although embodiments of the invention may achieve advantages over other possible solutions and/or over the prior art, whether or not a particular advantage is achieved by a given embodiment is not limiting of the invention. Thus, the following aspects, features, embodiments and advantages are merely illustrative and are not considered elements or limitations of the appended claims except where explicitly recited in a claim(s). Likewise, reference to “the invention” shall not be construed as a generalization of any inventive subject matter disclosed herein and shall not be considered to be an element or limitation of the appended claims except where explicitly recited in a claim(s). 
     The present invention generally relates to a PCM cell and arrangements thereof. The PCM cell is used as illustrative purposes only. It is contemplated that other memory cells like tunnel magneto-resistive (TMR) cells, or other memory cell element where information is stored by its change of resistance, could be used without departing from the spirit of the invention. In the case of spin-transfer torque TMR, current for the switching of the cell need to be required in two directions, and such a requirement will also be attended by the invention in this patent application. A PCM-based building block as used herein is comprised of numerous macro cells.  FIG. 2  is an isometric illustration of a macro cell  200  according to one embodiment. The macro cell  200  includes an electrically insulating spacer  202  at the bottom of the macro cell  200  in order to electrically insulate the macro cell  200  from underlying conductive material, such as transistors or adjacent macro cells. Suitable materials that may be utilized for the electrically insulating spacer  202  include silicon dioxide, silicon nitride, and silicon oxynitride. 
     The macro cell  200  also includes a selecting three-terminal device  208 , which could be a MESFET. As will be discussed below, the three-terminal selecting device  208  will have its gate electrode if it is a MESFET coupled to a control device external to the three-dimensional array to deliver electrical voltage or current to the gate electrode of that three-terminal device  208 . The three-terminal device  208  is electrically coupled to a first electrical connector  206 . The first electrical connector extends along a first axis  216  as well as a second axis  218  that is perpendicular to the first axis  216 . As shown in  FIG. 2 , the three-terminal device  208  is coupled to the first electrical connector  206  along the second axis  218 . It should additionally be noted that the gate of the three-terminal device  208  extends along another axis  222  that is perpendicular to both the first axis  216  and the second axis  218 . The portion of the first electrical connector  206  that extends along the first axis  216  is utilized to provide electrical current to the source of the three-terminal device  208 . 
     Those skilled in the art will recognize that a MESFET can be a completely symmetric device and its source and drain terminals be defined only after voltage levels are applied. In such, a MESFET will support current flow in two directions through the memory cell element. 
     The macro cell  200  also includes a memory cell  212  that is disposed along the second axis  218  and electrically coupled to the three-terminal device  208  by a second electrical connector  210 . The second electrical connector  210  is coupled to both the drain of the three-terminal device  208 , if the three-terminal device  208  is a MESFET, as well as the memory element. The memory cell  212  is also coupled to a third electrical connector  214 . The third electrical connector  214  extends both along the second axis  218  and along a third axis  220  that is perpendicular to both the first axis  216  and the second axis  218 . Another electrically insulating spacer  204  is coupled to the third electrical connector  214  to electrically insulate the macro cell  200  from adjacent macro cells. 
     To address the macro cell  200 , electrical voltage or current is applied to three distinct locations of the macro cell  200 . First, electrical voltage or current is applied to the first electrical connector  206 . Second, electrical voltage or current is applied to the gate of the three-terminal device  208  if the three-terminal device  208  is a MESFET. Third, electrical voltage or current is applied to the third electrical connector  214 . When all three voltages or currents are applied to the same macro cell  200 , then the macro cell  200  is addressed such that data may be written or read from the memory cell  212 . Memory cell  212  in this illustrative description represents the PCM cell and its heater, but other memory cell elements could be used such as magnetoresitive memory elements or other variable resistance elements as well. 
       FIG. 3  is an isometric view of a PCM-based building block array  300  having two macro cells  200 A,  200 B arranged side by side. As can be seen from  FIG. 3 , each macro cell  200 A,  200 B contains electrically insulating spacers  202 ,  204 , first electrical connectors  206 , selecting three-terminal device  208 , second electrical connectors  210 , memory cells  212 , and third electrical connectors  214 . However, while the first electrical connector  206  of one of the macro cells  200 A extends along both the first axis  216  and the second axis  218 , the first electrical connector  206  of the other macro cell  200 B extends along the first axis  216  and another axis  302  that is parallel to the second axis  218  and perpendicular to the first axis  216 . Additionally, the third electrical connector  214  of one macro cell  200 B extends along an axis  304  that is parallel to the third axis  220 . Finally, the selecting three-terminal device  208  of one macro cell  200 B extends along an axis  306  that is parallel to the axis  222  that the three-terminal device  208  of the other macro cell  200 A extends along. 
     In addition to extending along the first axis  216 , the first electrical connectors  206  of both macro cells  200 A,  200 B are electrically connected together. Thus, when electrical current is applied to the first electrical connector  206  of one macro cell  200 A, electrical current is also applied to the first electrical connector  206  of the other macro cell  200 B. Additionally, when electrical current is applied to the first electrical connectors  206 , electrical current is also applied to the source of the three-terminal devices  208  of both macro cells  200 A,  200 B. 
       FIG. 4  is a schematic isometric view of a PCM-based memory building block array  400  having a plurality of macro cells  200 A- 200 D arranged side by side. Macro cells  200 A,  200 B are as discussed above with regards to  FIG. 3 , but two additional macro cells  200 C,  200 D have been added. Similar to macro cells  200 A,  200 B, macro cells  200 C,  200 D each have electrically insulating spacers  202 ,  204 , first electrical connectors  206 , three-terminal devices  208 , second electrical connectors  210 , memory cells  212 , and third electrical connectors  214 . However, the first electrical connectors  206  for macro cells  200 C,  200 D are along a different axis  402  as compared to the first axis  216  upon which the first electrical connectors  206  for macro cells  200 A,  200 B extend. Additionally, the first electrical connectors  206  for both macro cell  200 C and  200 D extend along axis  404 ,  406  that are parallel to axis  218 ,  302 . 
     The third electrical connectors  214  for macro cells  200 A,  200 D extend along a common axis  220  and are electrically connected together. The third electrical connectors  214  for macro cells  200 B,  200 C extend along a common axis  304  and are electrically connected together. However, the third electrical connectors  214  for macro cells  200 A,  200 D are not electrically connected to the third electrical connectors  214  for macro cells  200 B,  200 C. Additionally, the three-terminal devices  208  for macro cells  200 A,  200 D extend along a common axis, axis  222  and are electrically connected together. The three-terminal devices  208  for macro cells  200 B,  200 C extend along a common axis  306  and are electrically connected together. However, the three-terminal devices  208  for macro cells  200 A,  200 D are not electrically connected to the three-terminal devices  208  for macro cells  200 B,  200 C. 
     A PCM-based building block can be arranged in more than one plane so that a 3D PCM memory array is fabricated.  FIG. 5  is a schematic isometric view of a 3D PCM-based memory array  500  having a plurality of macro cells  200 A- 200 H. The array  500  shows the macro cells  200 A- 200 D rotated counterclockwise 90 degrees from the view shown in  FIG. 4 . Four additional macro cells  200 E- 200 H are shown, but the macro cells  200 E- 200 H are disposed over the macro cells  200 A- 200 D and are electrically isolated from macro cells  200 A- 200 D by electrically insulating spacers  204 . It is contemplated that additional macro cells could be formed above macro cells  200 E- 200 H and would be electrically isolated by electrically insulating spacers  502 . 
     As shown in  FIG. 5 , the first electrical connectors  206  for macro cells  200 E,  200 F extend along an axis  508  that is parallel to axis  216 . Additionally, the first electrical connectors  206  for macro cells  200 E,  200 F are electrically coupled to the first electrical connectors  206  for macro cells  200 A,  200 B by element  512 . It is to be understood that element  512  comprises electrically conductive material such as wiring that connects the first electrical connectors  206  to transistors in the substrate. The first electrical connector  206  for macro cell  200 E extends along axis  218 , and the first electrical connector  206  for macro cell  200 F extends along axis  302 . 
     As also shown in  FIG. 5 , the first electrical connectors  206  for macro cells  200 G,  200 H extend along an axis  510  that is parallel to axis  402 . Additionally, the first electrical connectors  206  for macro cells  200 G,  200 H are electrically coupled to the first electrical connectors  206  for macro cells  200 C,  200 D by element  514 . It is to be understood that element  514  comprises electrically conductive material such as wiring that connects the first electrical connectors  206  to transistors in the substrate. The first electrical connector  206  for macro cell  200 G extends along axis  404 , and the first electrical connector  206  for macro cell  200 H extends along axis  406 . 
     As also shown in  FIG. 5 , the third electrical connectors  214  for macro cells  200 F,  200 G extend along an axis  506  that is parallel to axis  304 . Additionally, the third electrical connectors  214  for macro cells  200 F,  200 G are electrically coupled to the third electrical connectors  214  for macro cells  200 B,  200 C by element  516 . It is to be understood that element  516  comprises electrically conductive material such as wiring that connects the third electrical connectors  214  to transistors in the substrate. The third electrical connector  214  for macro cell  200 F extends along axis  302 , and the third electrical connector  214  for macro cell  200 G extends along axis  404 . 
     It is to be understood that the third electrical connectors  214  for macro cells  200 E,  200 H extend along an axis that is parallel to axis  220 . Additionally, the third electrical connectors  214  for macro cells  200 E,  200 H are electrically coupled to the third electrical connectors  214  for macro cells  200 A,  200 D by element  518 . Element  518  comprises electrically conductive material such as wiring that connects the third electrical connectors  214  to transistors in the substrate. The third electrical connector  214  for macro cell  200 E extends along axis  218 , and the third electrical connector  206  for macro cell  200 H extends along axis  406 . 
     The three-terminal devices  208  of macro cells  200 F,  200 G extend along a common axis  504  that is parallel to axis  306  and are electrically coupled together. Similarly, MESFETs  208  of macro cells  200 E,  200 H extend along a common axis that is parallel to axis  222  and are electrically coupled together. 
       FIGS. 6A-6D  are schematic isometric illustrations of a 3D PCM-based array  600  according to one embodiment. In the embodiment shown, the PCM array  600  includes four separate levels of macro cells with a total of sixty-four macro cells per level. Within each level, there are eight rows  602  that extend in a first direction and eight rows  604  that extend in a second direction perpendicular to the first direction. Each of the rows  602  is coupled to a corresponding element that comprises electrically conductive material, such as wiring, to connect the third electrical connectors  214  to transistors in the substrate. While only two elements  516 ,  518  have been shown, it is to be understood that each row  602  has a corresponding element for electrical connection and that each element is connected to each third electrical connector  214  within the entire row  602 . Thus, eight elements would be present for the embodiment shown in  FIGS. 6A-6D , but for clarity, only elements  516 ,  518  have been shown. Additionally, it is understood that the third electrical connectors  214  within a common row  602  in one level are electrically connected to the third electrical connectors  214  within the same row that are on a different level. Similarly, each of the rows  604  is coupled to a corresponding element that comprises electrically conductive material, such as wiring, to connect the first electrical connectors  206  to transistors in the substrate. While only two elements  512 ,  514  have been shown, it is to be understood that each row  604  has a corresponding element for electrical connection and that each element is connected to each first electrical connector  206  within the entire row  604 . Thus, eight elements would be present for the embodiment shown in  FIGS. 6A-6D , but for clarity, only elements  512 ,  514  have been shown. Additionally, it is understood that the first electrical connectors  206  within a common row  604  in one level re electrically connected to the first electrical connectors  206  within the same row that are on a different level. 
     For the three-terminal devices  208 , all of the three-terminal devices  208  within a common level are electrically coupled together as shown in  FIGS. 6C and 6D . All of the three-terminal devices  208  within a given level electrically couple together with electrical connectors  606 A- 606 D, such as wiring, that spans across the level and then down to the substrate to provide electrical connection to a transistor. In the embodiment shown in  FIGS. 6A-6D , there are four levels and hence, only four electrical connections to the transistors on the substrate for the three-terminal devices  208 . By selecting one row  602 , one row  604  and one electrical connector  606 A- 606 D, a single macro cell  200  can be addressed. 
     For the embodiment shown in  FIGS. 6A-6D , the PCM array  600  is an 8×8×4 3D arrangement of macro cells, but it is contemplated that any electrically programmable/readable memory cell, as opposed to a PCM cell, may be arranged in such a manner. Each macro cell  200  is addressed by the interception of three planes. Therefore, the overhead wiring is minimal. For the footprint over the substrate, an additional 2FNx area (for the x-direction planes), 2FNy area (for the y-direction planes) and 4FNz area (for the z-direction planes), where F is the half pitch critical dimension for the lithography used, Nx, Ny and Nz are the number of cells in the x, y, and z dimensions, is all that is required for addressing any cell in the full 3D structure. Therefore, the number of memory cells grows with NxNyNz (i.e., N 3 ) whereas the footprint overhead for addressability is a linear function of Nx, Ny and Nz. 
     For the embodiment shown in  FIGS. 6A-6D , a total of 256 macro cells  200  are present, yet only  20  transistors are necessary on the substrate to address each macro cell  200  individually. Rather than providing three separate electrical connections to each macro cell, which would necessitate 768 transistors, the macro cells  200  can share transistors, yet be uniquely addressed. Because only  20  transistors are necessary on the substrate, the PCM array  600  utilizes a very small amount of substrate area outside of the footprint of the PCM array  600 . Additionally, no overhead wiring is necessary to address the macro cells  200  in the middle of the PCM array  600 . One can easily imagine that if 768 transistors were utilized, electrically connecting the 768 transistors to the macro cells  200  would be quite complex. Even if the macro cells  200  were stacked in a 3D arrangement, electrically connecting 768 transistors to the PCM array  600  would be much more complex than connecting 20 transistors external to the 3D memory cell array. Thus, the 3D PCM array arrangement disclosed herein provides a much less complex wiring strategy, utilizes fewer transistors, and has a smaller footprint over the substrate. 
     The PCM arrays disclosed herein are scalable 3D arrangements. It is to be understood that the description herein is not limited to PCMs, but rather is applicable to any memory with memory cell elements queried by current and it uses a small footprint even in the case where a high current 3D access (i.e., selecting) device capability is a requirement. The embodiments disclosed herein are scalable, yet have a low footprint overhead with regards to the 3D architectural arrangement of the cells. The wiring that is over the entire cell is minimal to query a macro cell in the middle of the 3D cell and thus diminishes the overhead contribution to the footprint of the device. 
     While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.