Abstract:
A reference output circuit for generating an output clock signal for driving signals off of an integrated circuit chip uses a switched terminated load in combination with an output buffer to generate a feedback clock signal, which is used, in combination with a reference input clock signal, to generate the output clock signal. The switched terminated load uses transistors having the same size as transistors in the output buffer. The switched terminated load draws the same DC current as the output buffer. As a result, the switched terminated load and the output buffer have the same electro-migration performance. Pull-up and pull-down MOS impedances of the switched terminated load are easily adjusted during switching periods of the switched terminated load. The design of the switched terminated load minimizes variations in the terminated load impedance due to MOS impedance variations.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to an output circuit of an integrated circuit device. More specifically, the present invention relates to a circuit and method for generating an output clock signal in an integrated circuit device. 
       RELATED ART 
       [0002]      FIG. 1  is a block diagram of a reference output circuit  100  of a conventional integrated circuit. Reference output circuit  100  includes reference output buffer  101 , terminated load module  102 , capacitor  103 , comparators  104 - 105  and delay locked loop (DLL) circuit  106 . Reference output buffer  101  includes output register/pre-driver circuit  115  and output driver module  120 . Output driver module  120 , in turn, includes pull-up circuit  111  (i.e., PMOS transistor  121 ), pull-down circuit  112  (i.e., NMOS transistor  122 ) and resistor  123 . Terminated load module  102  includes pull-up circuit  131  (i.e., PMOS transistor  141  and resistor  151 ) and pull-down circuit  132  (i.e., NMOS transistor  142  and resistor  152 ). 
         [0003]    Output register/pre-driver circuit  115  includes terminals for receiving complementary driver control signals D and D#, output enable signal OE, and complementary output clock signals O CLK  and O CLK #. In response, output register/pre-driver circuit  110  provides a pull-up signal (PU) to the gate of PMOS transistor  121  in pull-up circuit  111 , and a pull-down signal (PD) to the gate of NMOS transistor  122  in pull-down circuit  112 . 
         [0004]    Pull-up and pull-down circuits  111  and  112 , in turn, provide a feedback clock signal FB CLK , which is applied to the positive input terminal of comparator  104  via a feedback path that includes terminated load module  102  and capacitor  103 . This feedback path is typically hidden inside the integrated circuit package. Pull-up circuit  111  is configured to pull up the feedback clock signal FB CLK  toward a positive supply voltage V DD , and pull-down circuit  112  is configured to pull down the feedback clock signal FB CLK  toward a ground supply voltage. 
         [0005]    Comparator  104  compares the feedback clock signal FB CLK  with a DC reference voltage V REF  (which is applied to the negative input terminal of comparator  104 ). Similarly, comparator  105  compares an input reference clock signal I CLK  with the reference voltage V REF . The DC reference voltage V REF  is set to the cross-over point of the received clock signals FB CLK  and I CLK  (e.g., V DD/ 2). Thus, the outputs of comparators  104  and  105  switch in response to the changing states of the feedback clock signal FB CLK  and the input reference clock I CLK , respectively. 
         [0006]    The outputs of comparators  104  and  105  are provided to DLL circuit  106 . In response, DLL circuit  106  provides the output clock signal O CLK . DLL circuit  106  generates the output clock signal O CLK  by introducing a delay to the input reference clock signal I CLK , wherein the introduced delay is selected in response to the output signals provided by comparators  104  and  105 . More specifically, the delay introduced by DLL circuit  106  is selected to synchronize the feedback clock signal FB CLK  with the input reference clock signal I CLK . 
         [0007]      FIG. 2  is a waveform diagram illustrating various signals of reference output circuit  100 . The output enable signal OE is activated high, thereby enabling output register/pre-driver circuit  115 . Driver control signals D and D# are selected to have a logic high state and a logic low state, respectively. Under these conditions, output register/pre-driver  115  will control the pull-up control signal PU and the pull-down control signal PD in the following manner, in response to the output clock signal O CLK  (and the complementary output clock signal O CLK #). 
         [0008]    At time T 1 , the input reference clock signal I CLK  transitions from a logic ‘0’ state to a logic ‘1’ state (rising edge). DLL circuit  106  introduces a delay (d 1 —comparator delay) to the input reference clock signal I CLK , such that the output clock signal O CLK  transitions from a logic ‘0’ state to a logic ‘1’ state (rising edge) at time T 2 . Output register/pre-driver  115  drives the pull-up control signal PU and the pull-down control signal PD to logic ‘0’ values in response to the rising edge of the output clock signal O CLK . The short inherent delays that exist between the rising edge of the output clock signal O CLK  and the falling edges of the pull-up control signal PU and the pull-down control signal PD are not shown in  FIG. 2  for purposes of clarity. 
         [0009]    The logic ‘0’ states of the pull-up and pull-down control signals PU and PD cause PMOS transistor  121  to turn on and NMOS transistor  122  to turn off, thereby pulling up the feedback clock signal FB CLK  toward the V DD  supply voltage. Capacitor  103  and terminated load module  102  introduce a delay (d 2 ) to the rise of the feedback clock signal, such that the feedback clock signal transitions from a logic ‘0’ state to a logic ‘1’ state (rising edge) at time T 3 . As illustrated in  FIG. 2 , the delays d 1  and d 2  cause the rising edge of the feedback clock signal FB CLK  to be synchronized with the rising edge of the input reference clock signal I CLK  at time T 3 . 
         [0010]    The complementary output clock signal O CLK # is generated in a second reference output circuit (not shown) that is identical to reference output circuit  100 . This second reference output circuit generates the complementary output clock signal O CLK # (and a corresponding complementary feedback clock signal FB CLK #) in response to a complementary input reference clock signal I CLK # (which is the complement of the input reference clock signal I CLK ). 
         [0011]    The complementary output clock signal O CLK # is provided to output register/pre-driver  115 . As illustrated in  FIG. 2 , a rising edge of the complementary input clock signal I CLK # occurs at time T 4 , and a rising edge of the complementary output clock signal O CLK # follows at time T 5  (after a delay d 3 ). Output register/pre-driver  115  drives the pull-up control signal PU and the pull-down control signal PD to logic ‘1’ values in response to the rising edge of the complementary output clock signal O CLK #. Again, the short inherent delays between the rising edge of the complementary output clock signal O CLK # and the rising edges of the pull-up control signal PU and the pull-down control signal PD are not shown in  FIG. 2  for purposes of clarity. 
         [0012]    The logic ‘1’ states of the pull-up and pull-down control signals PU and PD cause PMOS pull-up transistor  121  to turn off and NMOS pull-down transistor  122  to turn on, thereby pulling down the feedback clock signal FB CLK  toward the ground supply voltage. Capacitor  103  and terminated load module  102  introduce a delay (d 4 ) to the fall of the feedback clock signal FB CLK , such that the feedback clock signal transitions from a logic ‘1’ state to a logic ‘0’ state (falling edge) at time T 6 . As illustrated in  FIG. 2 , the delays d 3  and d 4  cause the falling edge of the feedback clock signal FB CLK  to be synchronized with the rising edge of the complementary reference input clock signal I CLK # at time T 6 . 
         [0013]    If the polarity of the driver control signals D and D# are reversed, the polarity of the pull-up and pull-down control signals PU and PD would also be reversed. 
         [0014]    The purpose of reference output circuit  100  is to align the output signals that are driven off the integrated circuit chip with the input reference clock signal I CLK . To accomplish this purpose, reference output buffer  101  is designed to be identical to other output buffers (not shown) on the same integrated circuit. In addition, the feedback path from the output of reference output buffer  101  to the input of comparator  104  is designed to emulate the output paths of these other output buffers. That is, the feedback clock signal FB CLK  is designed to have the same switching time as the other outputs of the integrated circuit. 
         [0015]    By using the output clock signal O CLK  to control the other output buffers of the integrated circuit, the output signals provided by these other output buffers will also be synchronized with the input reference clock signal I CLK . 
         [0016]    The feedback path from the output of reference output buffer  101  to the input of comparator  104  is designed as follows. The capacitance C o  of output capacitor  103  is selected to match the capacitance (including the package capacitance) seen by a typical output buffer of the integrated circuit. Thus, the reference output buffer  101  sees the same capacitance as the other output buffers on the same integrated circuit. 
         [0017]    The feedback path from reference output buffer  101  to comparator  104  is further designed to implement impedance matching. In high speed applications, output impedance matching with input termination is used to minimize switching noise and signal reflection. Terminated load module  102  is therefore included in the feedback path to emulate output impedance matching with input termination. 
         [0018]    The on-resistance of pull-up circuit  111  and pull-down circuit  112  (as well as the on-resistances of the other output buffers on the integrated circuit) is controlled to be R, wherein R is user programmable (e.g., by coupling a resistor having a resistance equal to 5 R to a pin of the integrated circuit). To implement impedance matching, the input termination of an external load will have the same resistance R coupled to a voltage equal to the power supply voltage V DD  divided by two (V DD /2). To mimic this external load configuration, terminated load module  102  includes a pull-up circuit  131  coupled to a V DD  voltage supply terminal through a resistance of 2 R, and a pull-down circuit  132  coupled to a ground supply terminal through a resistance of 2 R. Pull-up circuit  131  is continuously enabled by applying a ground supply voltage (0 Volts) to the gate of PMOS transistor  141 . Similarly, pull-down circuit  132  is continuously enabled by applying the V DD  supply voltage to the gate of NMOS transistor  142 . When enabled, pull-up circuit  131  and pull-down circuit  132  are the equivalent of a circuit having a resistor with resistance R coupled to a voltage of V DD /2. 
         [0019]    Reference output circuit  100  implements a digital impedance matching scheme, wherein the resistance of the output buffer  101  is controlled by turning on a selected number of parallel output driver modules (not shown), identical to output driver module  120 . If the parallel output driver modules are identical, then the output resistance is equal to the resistance of one module divided by the number of turned on modules. Typically, a small number of parallel output driver modules with progressive fine resistance differences are used to increase the resolution of the output resistance. 
         [0020]    The output resistance of pull-up circuit  111  (i.e., R) is equal to the on-resistance of PMOS transistor  121  plus the resistance of resistor  123 . Similarly, the output resistance of pull-down circuit  112  (i.e., R) is equal to the on-resistance of NMOS transistor  122  plus the resistance of resistor  123 . The resistances of PMOS transistor  121 , NMOS transistor  122  and resistor  123  are designated R PM , R NM  and R 0 , respectively. Thus, the output resistance R of pull-up circuit  111  is equal to R PM +R 0 , and the output resistance R of pull-down circuit  112  is equal to R NM +R 0 . Resistances R PM  and R NM  are selected to be equal to the same resistance (R T ) in typical conditions. As a result, the output resistance R of output driver module  120  is equal to R 0 +R T . 
         [0021]    Although the MOS resistances R PM  and R NM  vary in response to the output voltage, the effect of these variations is minimized by making resistance R 0  much greater than R PM  and R NM . The parallel output driver modules that are enabled for pull-up and pull-down operations can be different to compensate for the different resistances exhibited by PMOS transistors and NMOS transistors. 
         [0022]    To implement impedance matching within terminated load module  102 , each of resistors  151  and  152  is given a resistance equal to 2 R 0 , PMOS transistor  141  is given an on-resistance equal to 2 R PM , and NMOS transistor  142  is given an on-resistance equal to 2 R NM . The on-resistance R PM  of PMOS transistor  121  is equal to K P /2 W P , where 2 W P  represents the channel width of PMOS transistor  121  and K P  is a constant that depends on technology, voltage and temperature. Assuming that PMOS transistors  121  and  141  have the same channel length, the on-resistance of PMOS transistor  141  is equal to K P /W P , wherein W P  represents the channel width of transistor  141 . Thus, making the channel of PMOS transistor  121  twice as wide as the channel of PMOS transistor  141  causes the on-resistance of PMOS transistor  141  to be twice the on-resistance of PMOS transistor  121 . NMOS transistors  122  and  142  are designed in the same manner as PMOS transistors  121  and  141 , such that the on-resistance of NMOS transistor  142  is twice the on-resistance of NMOS transistor  122 . 
         [0023]    Because resistance R PM  and resistance R NM  are equal (i.e., to resistance R T ), the equivalent resistance of terminated load module  102  is therefore equal to ½(2 R 0 +2 R T ) or R 0 +R T . Thus, the resistance of the terminated load module  102  is equal to the output resistance of output buffer module  120 . 
         [0024]    There are two main problems associated with reference output circuit  100 . First, the resistance R of output driver module  120  is continuously monitored and adjusted to account for voltage and temperature changes. Consequently, the resistance  2 R of terminated load module  102  must also be updated. However, the resistance of terminated load module  102  cannot be updated during the rising or falling transitions of the feedback clock signal FB CLK , because such updates would interfere with the timing accuracy of reference output circuit  100 , and therefore introduce clock jitter. Thus, the resistance of terminated load module  102  must be updated between transitions in the feedback clock signal FB CLK . This is typically accomplished by adjusting the resistance of terminated load module  102  one quarter cycle after each transition of the feedback clock signal FB CLK . This timing is accomplished using a quarter-cycle delay circuit, which undesirably adds complexity and increased layout area to reference output circuit  100 . 
         [0025]    Second, different electro-migration conditions will exist in output driver module  120  and terminated load module  102 . When the feedback clock signal FB CLK  has a logic “1” value, the DC currents flowing through pull-up circuit  111  and pull-down circuit  112  in output driver module  120  are (0.25)V DD /R and 0 Amps, respectively. Under these conditions, the DC currents flowing through pull-up circuit  131  and pull-down circuit  132  of terminated load circuit  102  are (0.125)V DD /R and (0.375)V DD /R Amps, respectively. Note that the logic high voltage of the feedback clock signal FB CLK  is equal to (0.75)V DD . 
         [0026]    Conversely, when the FB CLK  signal has a logic “0” value, the DC currents flowing through pull-up circuit  111  and pull-down circuit  112  in output driver module  120  are 0 and (0.25)V DD /R Amps, respectively. Under these conditions, the DC currents flowing through pull-up circuit  131  and pull-down circuit  132  of terminated load circuit  102  are (0.375)V DD /R and (0.125)V DD /R Amps, respectively. Note that the logic low voltage of the feedback clock signal FB CLK  is equal to (0.25)V DD . 
         [0027]    The average DC current flowing in pull-up circuit  111  and pull-down circuit  112  of the output driver module  120  is (0.125)V DD /R. In contrast, the average DC current flowing in pull-up circuit  131  and pull-down circuit  132  of terminated load module  102  is (0.25)V DD /R. Thus, the average current in terminated load module  102  is twice the average current in output driver module  120  for purposes of electro-migration consideration. 
         [0028]    For layout and parasitic matching, PMOS transistor  141  only has half the amount of contacts and metal vias present in PMOS transistor  121  (because the PMOS transistor  141  has half the channel width of PMOS transistor  121 ). Electro-migration performance of PMOS transistor  141  is therefore one quarter the electro-migration performance of PMOS transistor  121 . Additional contacts and metal vias may be added to PMOS transistor  141  to help equalize the electro-migration in output driver module  120  and terminated load module  102 . However, this would require PMOS transistor  121  to drastically increase in size to achieve a matched layout. Note that NMOS transistors  122  and  142  exhibit the same electro-migration issues as PMOS transistors  121  and  141 . 
         [0029]    It would therefore be desirable to have a reference output circuit that does not exhibit the electro-migration discrepancies associated with reference output circuit  100 . It would further be desirable to have a reference output circuit capable of adjusting the terminated load module at any time during a cycle of the feedback clock signal FB CLK . 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0030]      FIG. 1  is a circuit diagram of a conventional reference output circuit. 
           [0031]      FIG. 2  is a waveform diagram illustrating various signals of the conventional reference output circuit of  FIG. 1 . 
           [0032]      FIG. 3  is a circuit diagram of a reference output circuit in accordance with one embodiment of the present invention. 
           [0033]      FIG. 4  is a block diagram that illustrates the manner in which the pull-up and pull-down control signals are generated for a terminated load module of the reference output circuit of  FIG. 3 , in accordance with one embodiment of the present invention. 
           [0034]      FIG. 5  is a waveform diagram illustrating the pull-up and pull-down control signals generated by the circuitry of  FIG. 4 , in accordance with one embodiment of the present invention. 
           [0035]      FIGS. 6A and 6B  are circuit diagrams illustrating the configuration of a conventional output buffer module and a conventional terminated load module  102  during pull-down and pull-up conditions, respectively. 
           [0036]      FIG. 6C  is a series of circuit diagrams that illustrate the derivation of the charging resistance of the circuit of  FIG. 6B . 
           [0037]      FIGS. 7A ,  7 B and  7 C are circuit diagrams illustrating an output buffer module and a terminated load module of the present invention, wherein a feedback clock signal is in a logic low state ( FIG. 7A ), in a first switching configuration to a logic high state ( FIG. 7B ), and in a final switching configuration to the logic high state ( FIG. 7C ). 
           [0038]      FIG. 8  is a circuit diagram of a reference output circuit having a simplified terminated load module in accordance with another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0039]      FIG. 3  is a circuit diagram of a reference output circuit  300  in accordance with one embodiment of the present invention. Because reference output circuit  300  is similar to reference output circuit  100  ( FIG. 1 ), similar elements in  FIGS. 1 and 3  are labeled with similar reference numbers. Thus, reference output circuit  300  includes output buffer circuit  101 , comparators  104 - 105  and delay locked loop (DLL)  106 . Output buffer circuit  101  includes output register/pre-driver circuit  115  and output driver circuit  120 . Output driver circuit  120  includes pull-up circuit  111  (PMOS transistor  121 ), pull-down circuit  112  (NMOS transistor  122 ), and resistor  123 . As described above in connection with  FIG. 1 , PMOS pull-up transistor  121  has a channel width of 2 W P  and an on-resistance of R PM  (wherein R PM =K P /2 W P ). Similarly, NMOS pull-down transistor  122  has a channel width of 2 W N  and an on-resistance of R NM  (wherein R NM =K N /2 W N ). Resistor  123  has a resistance of R 0 . 
         [0040]    Capacitor  103  of reference output circuit  100  is replaced with capacitor  303  in reference output circuit  200 . Capacitor  303  has a capacitance of C X . In addition, the terminated load module  102  of reference output circuit  100  is replaced with terminated load module  302  in reference output circuit  300 . Terminated load module  302  includes pull-up circuit  331  (i.e., PMOS pull-up transistor  341  and resistor  351 ) and pull-down circuit  332  (i.e., NMOS pull-down transistor  342  and resistor  352 ). 
         [0041]    Within pull-up circuit  331 , PMOS transistor  341  is designed to be identical to the PMOS transistor  121  in output buffer module  120 . Consequently, PMOS pull-up transistor  341  has a channel width of 2 W P  and an on-resistance R PM =K P /2 W P , just like PMOS pull-up transistor  121 . Also within pull-up circuit  331 , resistor  351  is designed to have a resistance R X  so that the total pull-up resistance of pull-up circuit  331  is three times that of pull-up circuit  111 . That is, R X +R PM =3*(R O +R PM ). 
         [0042]    Similarly, within pull-down circuit  332 , NMOS transistor  342  is designed to be identical to the NMOS transistor  122  in output buffer module  120 . Consequently, NMOS pull-down transistor  342  has a channel width of 2 W N  and an on-resistance R NM =K N /2 W N , just like NMOS pull-down transistor  122 . Also within pull-down circuit  332 , resistor  352  is designed to have a resistance R Y , so that R Y +R NM =3*(R O +R NM ). 
         [0043]    Note that the MOS resistance of terminated load module  302  (i.e., K P /2 W P  and K N /2 W N ) is only half the MOS resistance of conventional terminated load module  102  (i.e., K P /W P  and K N /W N ). Also note that the total resistance of terminated load module  302  is increased to 3 R (from 2 R in terminated load module  102 ). Consequently, the change in the resistance of terminated load module  302  due to changes in the on-resistances of MOS transistors  341  and  342  is reduced by a factor of about three in the present invention. Hence the terminated load module  302  of the present invention matches better to a passive resistor, which is the object of impedance matching. 
         [0044]    Within terminated load module  302 , the gate of PMOS pull-up transistor  341  is driven by a pull-up control signal PU 1 , and the gate of NMOS pull-down transistor  342  is driven by a pull-down control signal PD 1 . The manner in which the pull-up and pull-down control signals PU 1  and PD 1  are generated is described in more detail below. However, it is important to note that the pull-up and pull-down control signals PU 1  and PD 1  are switched signals (i.e., signals that change logic states), as opposed with the fixed state control signals used to control conventional terminated load module  102 . 
         [0045]      FIG. 4  is a block diagram that illustrates the manner in which the pull-up and pull-down control signals PU 1  and PD 1  are generated. More specifically,  FIG. 4  illustrates output register/pre-driver  115  (which is described above in connection with  FIGS. 1 and 2 ), and output register/pre-driver  415 . In the described embodiment, output register/pre-drivers  115  and  415  are identical circuits. Output register pre-driver  415  generates the pull-up and pull-down control signals PU 1  and PD 1  in response to driver control signals D 1  and D 1 #, output enable signal OE 1 , output clock signal O CLK1  and complementary output clock signal O CLK1 #. 
         [0046]    Driver control signals D 1  and D 1 # have polarities that are the opposite of the polarities of driver control signals D and D#, respectively. In the illustrated embodiment, this is accomplished by routing the driver control signal D to output register/pre-driver  415  as the driver control signal D 1 #, and by routing the driver control signal D# to output register/pre-driver  415  as the driver control signal D 1 . The output enable signal OE 1  has the same polarity as the output enable signal OE. In the described embodiment, the output enable signal OE is simply routed as the output enable signal OE 1 . Output clock signals O CLK1  and O CLK1 # are delayed versions of the output clock signals O CLK  and O CLK #, respectively. Output clock signal O CLK  is routed through delay circuit  401  to create output clock signal O CLK1 . Similarly, output clock signal O CLK # is routed through delay circuit  402  to create output clock signal O CLK1 #. 
         [0047]      FIG. 5  is a waveform diagram illustrating the manner in which output register/pre-driver  415  generates the pull-up and pull-down control signals PU 1  and PD 1  in response to the above-described input signals.  FIG. 5  also illustrates the signals associated with output register/pre-driver  115  for reference purposes. Note that the signals associated with output register/pre-driver  115  (i.e., D, D#, OE, O CLK , O CLK #, PU and PD) are described above in connection with  FIG. 2 . As described in more detail below, terminated load module  302  is designed such that the feedback clock signal FB CLK1  of reference output circuit  300  is identical to the feedback clock signal FB CLK  of reference output circuit  100  ( FIG. 1 ). 
         [0048]    Turning now to  FIG. 5 , delay circuit  401  introduces a delay (d 401 ) to the output clock signal O CLK  to create the output clock signal O CLK1 . Thus, output clock signal O CLK  and O CLK1  exhibit rising edges at times T 2  and T 7 , respectively, wherein these times T 2  and T 7  are separated by delay d 401 . Output register/pre-driver circuit  415  drives the pull-up and pull-down signals PU 1  and PD 1  to logic high states in response to the rising edge of the delayed output clock signal O CLK1 . (The inherent delay of output register/pre-driver  415  is not illustrated in  FIG. 5  for purposes of clarity). Thus, the pull-up and pull-down signals PU 1  and PD 1  are each driven to a logic high state at time T 7 . 
         [0049]    Note that the pull-up and pull-down control signals PU 1  and PD 1  are driven high in response to a rising edge of the delayed output clock signal O CLK1 , while the pull-up and pull-down signals PU and PD are driven low in response to a rising edge of the output clock signal O CLK . The polarity of the PU/PD signals are opposite the polarity of the PU 1 /PD 1  signals because the driver control signals D/D# are opposite in polarity to the driver control signals D 1 /D 1 #, respectively. 
         [0050]    The delay d 401  introduced by delay circuit  401  is selected such that the pull-up and pull-down signals PU 1  and PD 1  do not transition to logic high states until after the feedback clock signal FB CLK1  has risen to at least 80 percent of the full FB CLK1  voltage swing (i.e., until after the feedback clock signal FB CLK1  has clearly ‘switched’ to a logic high state). As described in more detail below, the FB CLK1  signal transitions from a low voltage of (0.25)V DD  to a high voltage of (0.75)V DD . Thus, when the feedback clock signal FB CLK1  is transitioning to a logic high state, pull-up transistor  341  in terminated load circuit  302  remains on until the feedback clock signal FB CLK1  rises to at least (0.25+0.5*0.8)V DD . As a result, pull-up transistor  341  assists the transition of the feedback clock signal F BCLK1  to a logic high state. Stated another way, terminated load module  302  helps the output driver module  120  to pull up the voltage of the feedback clock signal FB CLK1  during the rising transition of the feedback clock signal FB CLK1 . 
         [0051]    After the feedback clock signal FB CLK1  has switched to the logic high state, the pull-up and pull-down signals PU 1  and PD 1  transition to logic high states at time T 7 , thereby turning on NMOS pull-down transistor  342  and turning off PMOS pull-up transistor  341 . At this time, the turned on NMOS pull-down transistor  342  in terminated load module  302  drives against the turned on PMOS pull-up transistor  121  in output buffer module  120 , thereby establishing a desired DC level (e.g., approximately (0.75)V DD ) for the feedback clock signal FB CLK1  prior to the next transition. 
         [0052]    Delay circuit  402  introduces a delay (d 402 ) to the complementary output clock signal O CLK # to create the delayed complementary output clock signal O CLK1 #. Thus, complementary output clock signals O CLK # and O CLK1 # exhibit rising edges at times T 5  and T 8 , respectively, wherein these times T 5  and T 8  are separated by delay d 402 . Output register/pre-driver  415  drives the pull-up and pull-down signals PU 1  and PD 1  to logic low states in response to the rising edge of the delayed output clock signal O CLK1 #. (The inherent delay of output register/pre-driver  415  is not illustrated in  FIG. 5  for purposes of clarity). Thus, the pull-up and pull-down signals PU 1  and PD 1  are each driven to a logic low state at time T 8 . 
         [0053]    The delay d 402  introduced by delay circuit  402  is selected such that the pull-up and pull-down signals PU 1  and PD 1  do not transition to logic low states until after the feedback clock signal FB CLK1 , has fallen to at 20 percent (or less) of the full FB CLK1  voltage swing (i.e., until after the feedback clock signal FB CLK1  has clearly ‘switched’ to a logic low state). Thus, when the feedback clock signal FB CLK1  is transitioning to a logic low state, pull-down transistor  342  in terminated load circuit  302  remains on until the feedback clock signal FB CLK1  falls to at least (0.25+0.5*0.2)V DD . As a result, pull-down transistor  342  assists the transition of the feedback clock signal FB CLK1  to a logic low state. Stated another way, terminated load module  302  helps the output driver module  120  to pull down the voltage of the feedback clock signal FB CLK1  during the falling transition of the feedback clock signal FB CLK1 . 
         [0054]    After the feedback clock signal FB CLK1  has switched to the logic low state, the pull-up and pull-down signals PU 1  and PD 1  transition to logic low states, thereby turning on PMOS pull-up transistor  341  and turning off NMOS pull-down transistor  342 . At this time, the turned on PMOS pull-up transistor  341  in terminated load module  302  drives against the turned on NMOS pull-down transistor  122  in output buffer module  120 , thereby establishing a desired DC level (e.g., approximately (0.25)V DD ) for the feedback clock signal FB CLK1  prior to the next transition. Selecting delays d 401  and d 402  in the above-described manner ensures reliable operation of comparator  104 . 
         [0055]    Using the switching terminated load module  302  in the above-described manner advantageously allows the impedance of terminated load module  302  to be updated during each clock cycle, without disrupting the FB CLK1  signal or requiring a quarter cycle delay. More specifically, the impedance of the pull-up circuit  331  can be updated during the portion of the clock cycle that this pull-up circuit  331  is turned off (i.e., between times T 7  and T 8 ). Similarly, the impedance of the pull-down circuit  332  can be updated during the portion of the clock cycle that this pull-down circuit  332  is turned off. In this manner, the present invention solves the problem associated with updating the impedance of the terminated load module  102  ( FIG. 1 ). 
         [0056]    To make the voltages of the feedback clock signal FB CLK1  consistent with feedback clock signal FB CLK , the logic high voltage of the FB CLK1  signal should be equal to (0.75)V DD  Volts, and the logic low voltage of the FB CLK1  signal should be equal to (0.25)V DD  Volts. To accomplish this, the resistances R X  and R Y  of resistors  351  and  552  are selected such that the effective DC resistance of the terminated load module  302  is equal to three times the effective DC resistance of output buffer module  120 . For example, the resistance R X  is selected such that R X +K P /2 W P =3×(R 0 +K P /2 W P ). This equation can be simplified as follows: 
         [0000]      R X =3 R 0 +3  K   P /2 W P   −K   P /2 W P    (1) 
         [0000]      R X =3 R 0 +2  K   P /2 W P    (2) 
         [0000]      R X =3 R 0   +K   P /W P    (3) 
         [0057]    Similarly, the resistance R Y  is selected such that R Y +K N /2 W N =3×(R 0 +K N /2 W N ). This equation can be simplified as follows: 
         [0000]      R Y =3 R 0 +3  K   N /2 W N   −K   N /2 W N    (4) 
         [0000]      R Y =3 R 0 +2  K   N /2 W N    (5) 
         [0000]      R Y =3 R 0   +K   N /W N    (6) 
         [0058]    To make the delay of the feedback clock signal FB CLK1  consistent with the delay of feedback clock signal FB CLK , the delay at the cross-over voltage of V DD /2 should be equal for both signals. To accomplish this, the voltage equations associated with rising edges of feedback clock signals FB CLK  and FB CLK1  should first be derived. The voltage of a charging series-connected resistive-capacitive (RC) circuit is defined by the following equation: 
         [0000]      V(t)=V SS +V N    (7) 
         [0059]    wherein V(t) represents the capacitor voltage at time (t), V SS  represents the steady state voltage of the RC circuit, and V N  represents the natural response of the RC circuit. The natural response V N  is equal to Ke −t/RC , where K is a constant. 
         [0060]      FIGS. 6A and 6B  illustrate output buffer module  120  and terminated load module  102  of output reference circuit  100  when the feedback clock signal FB CLK  is in a logic low state (0.25)V DD  and a logic high state (0.75)V DD , respectively. Output buffer module  120  transitions from the configuration of  FIG. 6A  to the configuration of  FIG. 6B  for a rising edge of the FB CLK  signal. Thus, the steady state voltage V SS  associated with the rising edge of the FB CLK  signal is equal to (0.75)V DD . 
         [0061]    Immediately after the configuration of output buffer module  120  switches from  FIG. 6A to 6B  (i.e., at time=0+), the voltage on capacitor  103  remains unchanged at (0.25)V DD . Thus, equation (7) can be rewritten as follows at time=0+. 
         [0000]      (0.25)V DD =(0.75)V DD   +Ke   −0/R1C1    (8) 
         [0062]    Because Ke −0/R1C1  is equal to K, equation (8) can be simplified as follows. 
         [0000]      (0.25)V DD =(0.75)V DD   +K    (9) 
         [0000]        K =(0.25)V DD −(0.75)V DD    (10) 
         [0000]        K =−(0.5)V DD    (11) 
         [0063]    Thus, the following equations apply to reference output circuit  100 . 
         [0000]      V FBCLK ( t )=(0.75)V DD −(0.5)V DD   e   −t/R1C1    (12) 
         [0000]      V FBCLK ( t )=V DD (0.75−0.5 e   −t/R1C1 )   (13) 
         [0064]    The capacitance C 1  is the total feedback capacitance of feedback clock signal FB CLK  (including the capacitance C 0  of capacitor  103  and any parasitic capacitances). The resistance R 1  is determined from the Thevenin equivalent of the charging circuit, which is derived in  FIG. 6C . As illustrated in  FIG. 6C , the parallel resistances R and 2 R are equivalent to a single resistance of (⅔)R (Step  1 ). The resulting circuit can be represented as two loops (Step  2 ). The Thevenin equivalent resistance seen by the charging capacitance C 1  is determined by shorting the V DD  voltage supply (Step  3 ). Finally, the parallel resistances of 2 R and (⅔)R are equivalent to a single resistance of ½ R (Step  4 ). Thus, the Thevenin equivalent resistance R 1  is equal to ½ R. Substituting into equation (13) provides the following equation. 
         [0000]      V FBCLK ( t )=V DD (0.75−0.5 e   −2t/RC1 )   (14) 
         [0065]    The same analysis will now be performed for reference output circuit  300 .  FIGS. 7A ,  7 B and  7 C are circuit diagrams illustrating output buffer module  120  and terminated load module  302  of output reference circuit  300  when the feedback clock signal FB CLK1  is in a logic low state (0.25V DD ), in a first switching configuration to a logic high state, and in the final switching configuration to the logic high state, respectively. 
         [0066]    Output buffer module  120  and terminated load module  302  transition from the configuration of  FIG. 7A  to the configuration of  FIG. 7B  for a rising edge of the FB CLK1  signal. Thus, the steady state voltage V SS  associated with the rising edge of the FB CLK1  signal is equal to V DD . (Note that the FB CLK1  signal transitions to a final voltage of 0.75V DD  after switching to the configuration of  FIG. 7C .) 
         [0067]    Immediately after the configuration of output buffer module  120  switches from  FIG. 7A to 7B  (i.e., at time=0+), the voltage on capacitor  303  remains unchanged at (0.25)V DD . Thus, equation (7) can be rewritten as follows at time=0+. 
         [0000]      (0.25)V DD =V DD   +Ke   −0/R2C2    (15) 
         [0068]    Because Ke −0/R2C2  is equal to K, equation (15) can be simplified as follows. 
         [0000]      (0.25)V DD =V DD   +K    (16) 
         [0000]        K =(0.25)V DD −V DD    (17) 
         [0000]        K =−(0.75)V DD    (18) 
         [0069]    Thus, the following equations apply to reference output circuit  300 . 
         [0000]      V FBCLK1 ( t )=V DD −0.75V DD   e   −t/R2C2    (19) 
         [0000]      V FBCLK1 ( t )=V DD (1−0.75 e   −t/R2C2 )   (20) 
         [0070]    The capacitance C 2  is the total feedback capacitance of feedback clock signal FB CLK1  (including the capacitance C X  of capacitor  303  and any parasitic capacitances). The charging resistance R 2  is determined by simplifying the charging circuit of  FIG. 7B . As illustrated in  FIG. 7B , the charging resistance is provided by parallel resistances R and 3 R. These parallel resistances are equivalent to a single resistance of ¾ R. The charging resistance R 2  is therefore equal to ¾ R. Substituting this charging resistance into equation (20) provides the following equation. 
         [0000]      V FBCLK1 ( t )=V DD (1−0.75 e   −4t/3RC2 )   (21) 
         [0071]    For reference output circuits  100  and  300  to have the same switching speed, the respective feedback clock signals FB CLK  and FB CLK1  should reach the switching voltage V DD /2 at the same time (t). In order to accomplish this, the capacitances C 1  and C 2  should be selected in the manner described below. The switching voltage V DD /2 can be substituted into equation (14) to create the following equation for reference output circuit  100 . 
         [0000]      V DD /2=V DD (0.75−0.5 e   −2t/RC1 )   (22) 
         [0072]    Equation (22) can be solved for the time ‘t’ as follows. 
         [0000]        1 / 2 =(0.75−0.5 e   −2t/RC1 )   (23) 
         [0000]      0.25=0.5 e   −2t/RC1    (24) 
         [0000]      0.5= e   −2t/RC1    (25) 
         [0000]      ln(0.5)=−2 t/RC 1   (26) 
         [0000]        t=− ½  RC 1 ln(0.5)   (27) 
         [0073]    Similarly, the switching voltage V DD /2 can be substituted into equation (20) to create the following equation for reference output circuit  300 . 
         [0000]      V DD /2=V DD (1−0.75 e   −4t/3RC2 )   (28) 
         [0074]    Equation (28) can be solved for the time ‘t’ as follows. 
         [0000]      ½=(1−0.75 e   −4t/3RC2 )   (29) 
         [0000]      0.5=0.75 e   −4t/3RC2    (30) 
         [0000]      ⅔ =e   −4t/3RC2    (31) 
         [0000]      ln(⅔)=−4 t/ 3 RC 2   (32) 
         [0000]        t= −¾  RC 2 ln(⅔)   (33) 
         [0075]    For the switching time t in equation (27) to equal the switching time t in equation (33), the following must be true. 
         [0000]      −½  RC 1 ln(0.5)=−¾  RC 2 ln(⅔)   (34) 
         [0000]      2( C 1)ln(0.5)=3( C 2)ln(⅔)   (35) 
         [0000]      −1.3863( C 1)=−1.2164( C 2)   (36) 
         [0000]        C 2=1.14( C 1)   (37) 
         [0076]    Thus, the switching time of output reference circuit  300  can be set equal to the switching time of output reference circuit  100  by adjusting the capacitance C X  of output reference circuit  300  such that the total feedback capacitance C 2  of feedback clock signals FB CLK1  is equal to 1.14 times the total feedback capacitance Cl of feedback clock signal FB CLK . Advantageously, the terminated load module  302  of the present invention does not slow down the switching of the feedback clock signal FB CLK1  with respect to the switching of feedback clock signal FB CLK . 
         [0077]      FIG. 8  is a circuit diagram of a reference output circuit  800  having a simplified terminated load module  802  in accordance with another embodiment of the present invention. Because reference output circuit  800  is similar to reference output circuit  300  ( FIG. 3 ), similar elements in  FIGS. 3 and 8  are labeled with similar reference numbers. Reference output circuit  800  includes a terminated load module  802  having a pull-up circuit  831  (i.e., PMOS pull-up transistor  341 ), a pull-down circuit  832  (i.e., NMOS pull-down transistor  342 ), and a single resistor  850 . As described above, the resistance value K P /W P  should be about the same as the resistance value K N /W N , so that the number of output driver modules being used can be kept to a minimum. If the resistance value K P /W P  is about the same as the resistance value K N /W N , then resistors  351  and  352  can be eliminated, and replaced with a single resistor  850 , as illustrated in  FIG. 8 . Resistor  850  has a resistance R XY , which is defined as follows in accordance with on embodiment of the present invention. 
         [0000]      R XY =3 R 0 +0.5( K   P /W P   +K   N /W N )   (38) 
         [0078]    Thus, the pull-up resistance (R P1 ) of terminated load module  802  (i.e., the resistance of terminated load module when PMOS pull-up transistor  341  is on and NMOS pull-down transistor  342  is off) can be defined as follows. 
         [0000]      R P1 =R XY   +K   P /2 W P    (39) 
         [0000]      R P1 =3 R 0 +0.5( K   P /W P   +K   N /W N )+ K   P /2 W P    (40) 
         [0000]      R P1 =3 R 0   +K   P /W P +0.5( K   N /W N )   (41) 
         [0079]    Similarly, the pull-down resistance (R N1 ) Of terminated load module  802  (i.e., the resistance of terminated load module when PMOS pull-up transistor  341  is off and NMOS pull-down transistor  342  is on) can be defined as follows. 
         [0000]      R N1 =R XY   +K   N /2 W N    (42) 
         [0000]      R N1 =3 R 0 +0.5( K   P /W P   +K   N /W N )+ K   N /2 W N    (43) 
         [0000]      R N1 =3 R 0   +K   N /W N +0.5( K   P /W P )   (44) 
         [0080]    For a terminated pull-up configuration (i.e., PMOS pull-up transistor  341  is on and NMOS pull-down transistor  342  is off), the resistance error is equal to: 
         [0000]    
       
         
           
             
               
                 
                   
                     
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                   49 
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         [0081]    Similarly, for a terminated pull-down configuration (i.e., PMOS pull-up transistor  341  is off and NMOS pull-down transistor  342  is on), the resistance error in percent is equal to: 
         [0000]    
       
         
           
             
               
                 
                   
                     
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                   ( 
                   53 
                   ) 
                 
               
             
             
               
                 
                   
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                       - 
                       
                         
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                         6 
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                   ( 
                   54 
                   ) 
                 
               
             
           
         
       
     
         [0082]    In one example, R 0  is 500 Ohms, K P /2 W P  is 100 Ohms, and K N /2 W N  is 90 Ohms, such that there is a 10 percent mismatch between K P /W P  and K N /W N . N P  represents the number of parallel output driver modules turned on to pull up the feedback clock signal FB CLK1 , and N N  represents the number of parallel output driver modules turned on to pull down the feedback clock signal FB CLK1 . In this example, R P  is equal to 600 Ohms (R 0 +K P /2 W P ); R N  is equal to 590 Ohms (R 0 +K N /2 W N ); R XY  is equal to 1690 Ohms (i.e., 3 R 0 +0.5 (K P /W P +K N /W N ); R P1  is equal to 1790 Ohms (i.e., R XY +K P /2 W P ) and RN1 is equal to 1780 Ohms (i.e., R XY +K N /2 W N ) (Assuming that the impedance matching must match a resistance of 50 Ohms, then the resistance (R) of the output buffer modules is equal to 50 Ohms (i.e., R P /N P =R N /N N =50 Ohms)). 
         [0083]    As described above, the pull-up resistance (R P1 ) of terminated load module  802  should be equal to three times the pull-up resistance (R P ) of the output buffer module  120 , or 1800 Ohms (i.e., 600 Ohms×3). The resistance error introduced by the simplified terminated load module  802  is therefore approximately −0.56 percent (i.e., (1790−1800)/1800). This result is consistent with equation (54) above. 
         [0084]    As described above, the pull-down resistance R N1  of terminated load module  802  should be equal to three times the pull-down resistance R N  of output buffer module  120 , or 1770 Ohms (i.e., 590 Ohms×3). The resistance error introduced by the simplified terminated load module  802  is therefore approximately +0.56 percent (i.e., (1780−1770)/1770). This result is consistent with equation (55). Advantageously, the resistance errors introduced by simplified terminated load module  802  are relatively small. 
         [0085]    In the above example, a fifteen percent change in the on-resistances of the MOS transistors  121  and  122  over the output voltage range will translate to a change of about 2.4 percent in the resistances R P  and R N . Similarly, a fifteen percent change in the on-resistances of MOS transistors  341  and  342  over the output voltage range will translate to a change of about 0.8 percent in the resistances R P1  and R N1 . 
         [0086]    In accordance with one embodiment of the present invention, the DC current flowing in output driver module  120  is equal to the DC current flowing in the terminated load module  802  (or terminated load module  302 ). Consequently, the electro-migration performance is the same in the output driver module  120  and the terminated load module  802  (or  302 ). Thus, the 4× electro-migration degradation present in terminated load module  102  is resolved by the present invention. In accordance with one embodiment, the resistance R XY  is constructed with multiple resistances R 0  connected in series, such that the resistance R XY  will have the same electro-migration performance as resistance R 0 . 
         [0087]    Although the present invention has been described in connection with various embodiments, it is understood that variations of these embodiments would be obvious to one of ordinary skill in the art. Thus, the present invention is limited only by the following claims.