Abstract:
A semiconductor memory device provided with an on-chip test circuit is disclosed. The on-chip test circuit includes a test write circuit for writing the same write data to at least two memory cells, simultaneously in a test mode, a selection circuit for simultaneously reading stored data from the above at least two memory cells and a comparison circuit for comparing data read from the at least two memory cells whose comparison output shows whether at least one of the at least two memory cells is bad, or all of the at least two memory cells are good.

Description:
This is a continuation of application Ser. No. 835,085, filed Feb. 28, 1986, now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device provided with an on-chip or built-in test circuit. 
     The capacity of semiconductor memories has been increasing remarkably, and memory having 256 kbit are currently manufactured. Also, many prototype one megabit dynamic memories have been announced. However, accompanied by the increase in memory capacity, the test time for testing memories also has been increased. 
     In order to determine whether a memory is good or not, it is necessary to check all the memory cells. The test of a memory is conducted by writing a predetermined one of binary logic data into each memory cell and reading stored data from each memory cell. If the predetermined one of binary logic data is read from one memory cell, this one memory cell is judged as a good cell. If a logic data other than the above predetermined logic data is read from one memory cell, then this one memory cell is judged as a default cell. This testing is conducted for all the memory cells. 
     The above kind of test must be performed under varying conditions of power supply voltge, timing of signals or the like. Thus, the test time has been increased largely in proportion to the capacity of memories. For example, a typical test time required for a 64-Kbit memory is 3.2 second, while the test times for a 256-Kbit memory and a 1-Mbit memory are 12.8 seconds and 51.2 seconds, respectively. The increase in test time also has increased the cost of manufacturing memories. 
     SUMMARY OF THE INVENTION 
     It is an object of the present to provide a memory with an on-chip test circuit for conducting a test of the memory at a high speed. 
     The memory of the present invention is of the type having a plurality of memory cells which are divided into a plurality of memory cell groups, a plurality of bus lines each provided for each one of the memory cell groups, and a plurality of selection circuits provided for the plurality of memory cell groups, each selection circuit selectively performing a transfer of data between one of the data lines of the associated memory cell group and the associated bus line. The memory features a test write circuit for simultaneously providing the same data to the plurality of bus lines for writing the same data to selected memory cells of the respective memory cell groups, and a comparison circuit for comparing data read from the selected memory cells of the respective memory cell groups. 
     According to the present invention, a plurality of memory cell groups are simultaneously subjected to writing of the same data and to reading of written data for test purposes. In this manner the total test time for a memory cell device can be significantly reduced. Furthermore, examination of the read-out data from the memory cells to be checked is conducted by simply comparing the read-out data from those cells. Accordingly, a high speed checking of the memory cells can be achieved by a simple circuit arrangement. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic block diagram showing a memory device according to a first embodiment of the present invention; 
     FIG. 2 is a schematic block diagram of a memory device according to a second embodiment of the present invention; 
     FIG. 3 is a schematic block diagram of a memory device according to a third embodiment of the present invention; and 
     FIG. 4 is a schematic block diagram of a memory device according to a fourth embodiment of the present invention: 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 shows a memory according to a first embodiment of the invention. A plurality of memory cells are arranged in two memory cell arrays 1 and 2 in a known manner. In each of the arrays 1 and 2, a plurality of word lines WL1, WL2 are arranged in rows and adapted to be selected by a row decoder DU in a row decoding section 3. Bit lines BL1 in the array 1 are selected by a column selection circuit 4-1 to be connected to a first bus line I/O 1, while bit lines BL2 in the array 2 are selected by a column selection circuit 4-2 to be connected to a second bus line I/O 2. A plurality memory cells MC are connected to word lines and bit lines in a known manner. In this arrangement, the decoder DU is used to select simultaneously both word lines WL1 and WL2 of the arrays 1 and 2. Also, the column selection circuits 4-1 and 4-2 operate simultaneously. 
     A data input terminal D IN  is connected to an input of a data-in buffer 7. An output circuit 6 includes a buffer BO whose output is connected to an output terminal D OUT . The output circuit 6 also includes a switch S4. The switch S4 connects the input of the buffer BO to a node CN when a test signal φ T  is not present in a normal operating mode, and to an output of an Exclusive-NOR circuit 9 when the test signal φ T  is present in a test mode. The Exclusive-NOR circuit has two inputs coupled to the bus lines I/O 1 and I/O 2, respectively. A write block selection circuit 8 includes a switch S1 connected between the bus line I/O 1 and the node CN and a switch S2 connected between the bus line I/O 2 and the node CN. In a normal write operation mode (φ T  is not present), one of the switches S1 and S2 assumes a conductive state according to a column address bit Yn, while both of the switches S1 and S4 are rendered conductive in response to the signal φ T  so that the same write data from the terminal D IN  is applied to both the bus lines I/O 1 and I/O 2 simultaneously. Then the write data on the bus lines I/O 1 and I/O 2 are transmitted to selected bit lines through the column selection circuits 4-1 and 4-2 to write the same data to selected memory cells in both arrays 1 and 2 in a write cycle in the test mode. A read block selection circuit 5 includes a switch S3 which connects one of the bus lines I/O 1 and I/O 2 to the node CN in response to the same column address bit Yn. 
     A read operation in the normal operating mode is explained first. A read-out data from a selected memory cell in the array 1 is outputted to the bus line I/O 1 via the circuit 4-1 while a read-out data from a selected memory cell in the array 2 is outputted to the bus line I/O 2 via the circuit 4-2. 
     Then, the switch S3 connects one of I/O 1 and I/O 2 to the node CN according to Yn so that a selected one of data on the bus lines I/O 1 and I/O 2 is transmitted to the node CN. In this instance the switch S4 connects the node CN to the input of BO, and hence the selected data on the node CN is outputted to the output terminal D OUT . The switch S3 does not connect either of I/O 1 and I/O 2 to the node CN. 
     When a write operation is conducted in the normal operation mode, the buffer 7 is enabled so that write data applied to D IN  is amplified and outputted to the node CN. In this instance, one of the switches S1 and S2 in the circuit 8 is rendered conductive according to the content of Yn so that the write data on the node CN is selectively transferred to one of I/O 1 and I/O 2 and then written into one of the arrays 1 and 2. 
     When a write operation is conducted in the test mode, both the switches S1 and S2 are made conductive in response to φ T , while the switch S4 connects the output of EX-NOR 9 to the input of BO. Under this condition, a predetermined data such as &#34;1&#34; applied to the terminal D IN  is simultaneously applied to both the bus lines I/O 1 and I/O 2 via the buffer 7 and the circuit 8. Then the data on the bus lines I/O 1 and I/O 2 are simultaneously written into selected memory cells of the arrays 1 and 2. Thus, writing of the same data of the two memory cells is achieved. 
     When a read operation, i.e. a judging operation in the test mode is conducted, the switches S1 and S2 are both non-conductive and the switch S4 is connected to the output of EX-NOR 9. The switch S3 separates I/O 1 and I/O 2 from the node CN. Read-out data from the arrays 1 and 2 are transferred to I/O 1 and I/O 2 via the column selection circuits 4-1 and 4-2, respectively. In the case where both of the selected memory cells in the arrays 1 and 2 are good, the same data is generated on both of I/O 1 and I/O 2. In this case the EX-NOR 9 generates a &#34;1&#34; level output which is then outputted to D OUT  via the switch S4 and BO. 
     On the contrary, in the case where one of the selected memory cell in the arrays 1 and 3 is bad, such bad memory cell cannot maintain the written data and produces another level of data. For example, when a selected memory cell in the array 1 is bad while a selected memory cell in the array 2 is good, different data are generated on the bus lines 1 and 2. Accordingly, EX-NOR circuit 9 generates a &#34;0&#34; output which is outputted via the switch S4 and the buffer BO to D OUT . Thus, either one of the selected cells in the arrays 1 and 2 is indicated to be bad by D OUT . In general, the possibility that both of the selected memory cells in the arrays 1 and 3 are bad is extremely small and almost negligible empirically. Therefore, there is not need to pay attention to such possibility in the test. Thus, a plurality of memory cells can be checked simultaneously by the invention. 
     Referring to FIG. 2, a second embodiment of the invention is explained. In FIG. 2, the portions corresponding to those in FIG. 1 are denoted by the same reference numerals. In this embodiment, in place of EX-NOR 9 in FIG. 1, an Exclusive-OR circuit 9&#39; and an AND gate 10 are employed. EX-OR 9&#39; generates a &#34;1&#34; output when data on I/O 1 and I/O 2 are different from each other and a &#34;0&#34; output when data an I/O 1 and I/O 2 are the same in logic level. The AND gate 10 generates a &#34;1&#34; output when both data on I/O 1 and I/O 2 are at logic &#34;1&#34; and a &#34;0&#34; output otherwise. 
     An output circuit 6&#39; renders D OUT  at a high impedance state, i.e. a floating state when the output of EX-OR 9&#39; is at &#34;1&#34; in level, and transmits the output of AND 10 when the output of EX-OR 9&#39; is at &#34;0&#34; in level. Accordingly, in the case where data on I/O 1 and I/O 2 are the same, the kind of the data can be known from the state of D OUT . 
     Referring to FIG. 3, a third embodiment of the present invention is described. 
     In FIG. 3, the portions corresponding to those in the previous embodiments are designated by the same numerals. 
     A true bus line I/O 1 and a complementary bus line I/O 1 are drawn from a column selection circuit 4-1, while a true bus line I/O 2 and a complementary bus line I/O 2 are drawn from a column selection circuit 4-2. Write circuits 8-1 and 8-2 are provided for the bus line pairs I/O 1, IO 1; I/O2, IO 2, respectively. The write circuits 8-1 and 8-2 receive true and complementary write data DI and DI generated by a buffer 7. A comparison circuit 9&#34; includes an Exclusive-OR circuit 22 having inputs coupled to I/O 1 and I/O 2, an Exclusive-OR circuit 23 having inputs coupled to I/O 1 and I/O 2, and an OR gate having inputs connected to the outputs of the EX-OR circuits 22 and 23. The output of the OR gate 24 is taken out as a signal φ TO . Read control circuits 5-1 and 5-2 receives data from the bus line pairs I/O 1, I/O 1; I/O 2, I/O 2 via data amplifiers 11-1 and 11-2, respectively. The read control circuits 5-1 and 5-2 operatively transfer the outputs of the amplifiers 11-1 and 11-2 to a pair of output bus lines OUT and OUT, respectively. A latch circuit 13 is provided to the lines OUT and OUT for holding data on OUT and OUT. An output circuit 6&#39; is a tri-state output circuit compound of field effect transistors Q 7  to Q 10 . A test mode detection circuit 15 includes a plurality of diode-connected field effect transistors Q 11a  to Q 11m  coupled between an external terminal TE and a ground potential. When a higher voltage above normal logic level range is applied, a certain potential is generated from a drain of the transistor Q 11j  which is applied to a driver 16 via inverters IV1 and IV2. When the higher voltage is applied to TE, the driver 16 produces a test signal φ TE  for placing the memory in a test mode. 
     One column address bit Yn is inputted to an address buffer 21 and latched by a latch circuit 25 in true (Yn) and complementary (YN) forms. A read block selection circuit 17 has field effect transistors Q 3  and Q 4 . The transistors Q 3  transmits a read enable signal φ RE  to the circuit 5-2 as a selection signal φ R  Yn thereby to enable the circuit when the true column address signal φ Yn  is true. The transistor Q 4  transmits φ RE  to the circuit 5-1 as φ Yn  in response to φ Yn . A write block selection circuit 12 includes field effect transistors for selectively transferring a write enable signal φ WE  to the circuits 8-2 and 8-1 in response to o Yn  and φ Yn  thereby to enable the circuits 8-2 and 8-1, respectively. A test write circuit 14 includes field effect transistors Q 5  and Q 6  which transfer φ WE  to both of the circuits 8-1 and 8-2 in response to the test signal φ TE  so that write data is transferred to both of bus line pairs I/O 1 I/O 1 and to I/O 2, I/O 2 simultaneously to achieve a write cycle in the test mode. 
     When the higher voltage is applied to TE, the test signal φ TE  is generated from the driver 16. When a write cycle is conducted, both of the write circuits 8-1 and 8-2 are enabled because φ WE  is applied thereto via the circuit 14. Thus, the same data is written into selected memory cells in the arrays 1 and 2 simultaneously. 
     When a read cycle is conducted in the test mode, data from selected memory cells in the arrays are taken-out to the bus line pairs I/O 1, I/O 1 and I/O 2, I/O 2, respectively, which are inputted to the comparison circuit 9&#34;. When both data read from the arrays 1 and 2 are the same, the signal φ TO  is at &#34;0&#34; level. Therefore, the transistors Q 7  and Q 8  are non-conductive. The above data is transferred to OUT and OUT via either of the circuits 5-1 and 5-2 and then outputted to D OUT . 
     On the contrary, when one of selected memory cells in the arrays 1 and 2 is bad while the other is good, data on the bus line pair I/O 1, I/O 1 and data on the bus line pair I/O 2, I/O 2 are different from each other. Accordingly, the comparison circuit 9&#34; produces a &#34;1&#34; level of 100  TO , which renders the transistors Q 7  and Q 8  conductive. Accordingly, both of the transistors Q 9  and Q 10  are rendered non-conducting. Thus, the output terminal D OUT  is set at a high impedance state. 
     In general, the possibility that both of the selected memory cells in the arrays 1 and 2 are bad is extremely small and almost negligible empirically. Therefore, there is not need to pay attention to such possibility in the test. 
     FIG. 4 shows a fourth embodiment of the invention. The portions corresponding to those in FIG. 3 are designated by the same reference numerals. 
     This embodiment is achieved by providing an inverter IV3 for generating a signal φ TO  complementary to the signal φ TO . Accordingly, the signal φ TO  assumes &#34;1&#34; level when read-out data on the bus line pairs I/O 1 and I/O 2, I/O 2 are the same. Specifically, data on I/O 1 and I/O 2 are the same, e.g. &#34;1,&#34; and data on I/O 1 and I/O 2 are the same, e.g. &#34;0&#34;. On the contrary, the signal φ TO  assumes a &#34;0&#34; logic level when data on the bus line pairs are different. Also, in this embodiment, in place of the transistors Q 7  and Q 8 , four transistors Q 11  to Q 14  are employed. The transistors Q 11  and Q 13  form a push-pull circuit for driving the gate potential of the transistor Q 9  while the transistors Q 12  and Q 14  form a push-pull circuit for driving the gate potential of the transistor Q 10  in complementary manner. 
     In a read operation in the test mode, when data on both the bus line pairs I/O 1, I/O 1 and I/O 2, I/O 2 are same, φ TO  and φ TO  assume &#34;0&#34; and &#34;1&#34; level, respectively. Accordingly, the transistors Q 13  and Q 12  are rendered conductive to make the gate potentials of the transistors Q 9  and Q 10  &#34;0&#34; and &#34;1&#34;,  respectively. Thus, a &#34;0&#34; level output is generated at D OUT . 
     In the case where data on the bus line pair I/O 1, I/O 1 and data on the bus line pair I/O 2, I/O 2 are different, the signals φ TO  and φ TE  assume &#34;1&#34; and &#34;0&#34; logic levels, respectively.  Thus, the transistors Q 11  and Q 14  are rendered conductive so that the transistor Q 9  becomes conductive and a &#34;1&#34; level output is generated at D OUT . 
     As has been described above, according to the present invention, a plurality of memory cells can be tested simultaneously and therefore a test time required for testing a whole memory device can be reduced significantly.