Abstract:
A method for testing a memory device having plural memory elements includes performing a succession of operations including: a) writing a test datum into the memory elements according to a first scanning sequence; b) accessing each memory element according to the first scanning sequence, reading a content thereof, comparing the read content to the test datum, and writing thereinto the test datum complement; c) accessing each memory element according to a second scanning sequence, reading a content thereof, comparing the read content to the test datum complement, and writing thereinto the test datum; d) accessing each memory element according to the second scanning sequence, reading a content thereof, comparing the read content to the test datum, writing thereinto the test datum complement, and reading again the content thereof and comparing the read content to the test datum complement.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to the field of memory integrated circuits (ICs), and more specifically to static random access memories (SRAMs), particularly SRAMs embedded in complex ICs such as systems on a chip (SOC).  
         [0003]     2. Description of the Related Art  
         [0004]     Memory ICs, and particularly embedded SRAMs, like all ICs, also need to be tested in such a way to ensure full functionality and, when possible, to improve the yield of their manufacturing processes. In fact, each produced memory device may be affected by a plurality of defects due to unavoidable manufacturing drawbacks caused by the process tolerances.  
         [0005]     The test of embedded SRAMs in SOC systems is object of continuous searches and investments, considering the high percentage of silicon area occupied by SRAMs in the entire electronic system. Nowadays, the increasing sizes of modern large-scale memories, and performances required in the field of memory cache subsystems, show the limits of the pre-existing approaches to test.  
         [0006]     The best way known in the art for testing an embedded SRAM is given by the so called Built-In Self Test (BIST) solutions which make use of “general purpose” memory test algorithms. Such general purpose memory test algorithms are in position to detect a complete set of possible faults that may occur in an integrated circuit. A description of the faults that may affect a semiconductor memory can be found in A. J. Van de Goor, “Testing Semiconductors Memories—Theory and Practice”, Wiley &amp; Sons, Chichester, UK, 1991.  
         [0007]     Nevertheless, considering the continuous need of increase in memory size and in memory access speed, the approach of implementing BIST circuits encompassing general purpose memory test algorithms is reaching the limits in terms of test time and efficiency due to the technological capabilities.  
         [0008]     In fact, such general purpose memory test algorithms are on one hand able to cover a complete set of faults, but on the other hand demand test times that are becoming longer and longer as a consequence of increased memories dimensions.  
         [0009]     A widely diffused general purpose memory test algorithm is the so called “Marinescu B”. The number of test operations performed by this algorithm for detecting all the possible faults that may occur in a memory device under test is given by: 
 
 N   oper   MB =17 *N*N   d , 
 
 where N represents the number of memory words of the memory device under test, and N d  is the number of different test patterns used during the test (the memory test algorithm is repeated per each pattern). According to this memory test algorithm, N d  depends on the memory parallelism, i.e., depends on the number of data bits N db  forming each memory word: 
 
 N   d =log 2 ( N   db )+1. 
 
         [0010]     The set of faults covered by general purpose memory test algorithms is derived from exclusively theoretical fault models that do not take into account the real physical implementation of the specific memory device under test.  
         [0011]     In view of the state of the art outlined in the foregoing, the inventors have faced the problem of how to improve the known BIST solutions for testing memory ICs, particularly ICs embedding SRAMs.  
       BRIEF SUMMARY OF THE INVENTION  
       [0012]     According to an embodiment of the invention, a method for testing a memory device is provided.  
         [0013]     The method for testing a memory device that includes an arrangement of a plurality of memory elements comprises a step for defining a first and a second scanning sequences for scanning the memory elements and a step for defining at least one test datum. The method further includes the performance of at least once a succession of operations including:  
         [0014]     a) writing the test datum into the plurality of memory elements, accessing thereto according to the first scanning sequence;  
         [0015]     b) accessing each memory element according to the first scanning sequence, reading a content thereof and comparing the read content to the test datum, and writing thereinto a complement of said test datum;  
         [0016]     c) accessing each memory element according to the second scanning sequence, reading a content thereof and comparing the read content to the complement of the test datum, and writing thereinto said test datum;  
         [0017]     d) accessing each memory element according to the second scanning sequence, reading a content thereof and comparing the read content to the test datum, writing thereinto said complement of the test datum, and reading again the content thereof and comparing the read content to the complement of the test datum. 
     
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS  
       [0018]     Further features and advantages of the present invention will be made clear by the following detailed description of a preferred embodiment thereof, provided purely by way of a non-limitative example, with reference to the attached drawings, wherein:  
         [0019]      FIG. 1  schematically illustrates a functional block view of a memory device;  
         [0020]      FIGS. 2A-2C  depict a schematic flow chart illustrating the steps of an 8N algorithm;  
         [0021]      FIGS. 3A and 3B  illustrate two example of increasing and decreasing address sequences;  
         [0022]      FIG. 4  schematically illustrates a possible BIST system implementation of the 8N algorithm;  
         [0023]      FIG. 5  provides a functional block view of a finite state machine implementing the 8N algorithm;  
         [0024]      FIG. 6  illustrates a state diagram showing the functioning sequence of a timing circuit;  
         [0025]      FIG. 7A  illustrates a circuital implementation of the timing circuit;  
         [0026]      FIG. 7B  illustrates a time diagram showing the temporal evolutions of the timing circuit;  
         [0027]      FIG. 8  shows a state diagram illustrating the functioning of an address counter included in the finite state machine implementing the 8N algorithm;  
         [0028]      FIG. 9  illustrates an exemplary circuital implementation of the address counter; and  
         [0029]      FIG. 10  illustrates a state diagram describing the functioning of an algorithm block included in the Finite State Machine implementing the 8N algorithm. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0030]     With reference to the drawings, in  FIG. 1 a  SRAM memory device  100  is illustrated in terms of the main functional blocks.  
         [0031]     The SRAM memory device  100  comprises a memory matrix  102  formed of a plurality of memory elements  104  in a two-dimensional arrangement of a plurality of rows  108  and of columns  110 . More particularly, according to an embodiment of the present invention, the memory matrix  102  includes an even number (four in the example shown in the Figure) of rows  108 , and a number of columns  110  that is a power of two (2 2 =4 in the example shown in the Figure). The SRAM memory device  100  further includes a word line WL for each row  108  of the matrix, and a plurality (e.g., 8 or 16) of bit line pairs BL, BLN for each column  110  of the matrix, wherein every pair of bit lines corresponds to a respective SRAM memory cell  106 , i.e., to one bit of a memory word (in the Figure, for the sake of clarity only one bit line pair per matrix column is depicted).  
         [0032]     Each memory element  104  includes a plurality of SRAM cells  106  (for example, constituted by six MOS transistors, as shown in the enlarged detail of the Figure) belonging to the same row  108  of the memory matrix  102 , in such a way to be able to store a memory word per memory element  104 . It has to be noted that, in an embodiment of the present invention, the plurality of bit line pairs associated with the generic matrix column may include as few as just one bit line pair: this refers to the case wherein each memory element  104  includes a single SRAM memory cell  106 , i.e., it refers to a SRAM memory device  100  with memory words constituted by only a single bit.  
         [0033]     Still according to an embodiment of the present invention, the bit lines BL, BLN of each pair are paralleled with a corresponding shield line  112  extending in between them, and kept at a fixed voltage value, for example the ground voltage. In a possible practical implementation, the bit lines and the shield lines are formed in a conductive material like aluminum.  
         [0034]     The SRAM device  100  further includes a row address decoder and row selection circuit  120 , that allows selecting one word line WL among the others of the memory matrix  102 , according to a row address RADD, that is a portion of a memory address ADD. Similarly, a column address decoder and column selection circuit  125  allows selecting a packet of, e.g., 8 or 16 of bit line pairs, corresponding to a single memory element  104 , according to a column address CADD, which is a portion of the address ADD. Schematically shown as a block  128  are conventional circuits for sensing and writing the SRAM cells  106  of the memory matrix  102 .  
         [0035]     Thanks to the presence of the shield lines  112  and of design and layout constraints used for implementing the memory matrix, it is possible to reduce the effective set of faults that may affect the memory to a subset of the above-mentioned complete set of faults; in particular, the faults in the subset can be covered by a memory test method implementing an algorithm according to an embodiment of the invention, that will be described later on.  
         [0036]     Such subset of faults refers to a fault model including the following faults (a more detailed description of the effective faults set will be provided later on):  
         [0037]     Stuck at Faults (SAF): Faults caused by circuital lines or nodes that become stuck at a logic value;  
         [0038]     Coupling Faults (CF): Faults caused by coupling effects between circuital lines or nodes;  
         [0039]     Address Faults (AF): Two or more addresses access a same memory word, or an address points to two or more memory words;  
         [0040]     Transition Faults (TF): A memory cell can not make certain kinds of state transition (e.g., it cannot switch from a stored “0” to a stored “1”, or vice versa);  
         [0041]     Stuck Open Faults (SOF): A cell can not be accessed;  
         [0042]     Unrestored Write Faults (UWF): Bit lines can not correctly recover to the right value after a write operation;  
         [0043]     Data Retention Faults (DRF): Memory cells loose stored data after a while;  
         [0044]     Write Through Faults (WTF): The state of input data affects reading operations.  
         [0045]     The memory test algorithm according to an embodiment of the present invention, hereinafter also referred to as “8N algorithm”, is described by the following pseudo-code:  
                                                           S1   XX = 000...00               S2              Write{XX}   [M0]           S3              Read{XX} - Write{ XX }   [M1]           S4              Read{ XX } - Write{XX}   [M2]           S5              Read{XX} - Write{ XX } - Read{ XX }   [M3]           S6   XX = 010...01           S7              Write{XX}   [M0]           S8              Read{XX} - Write{ XX }   [M1]           S9              Read{ XX } - Write{XX}   [M2]           S10              Read{XX} - Write{ XX } - Read{ XX }   [M3]                      
 
         [0046]     The 8N algorithm comprises a series of ten steps (S 1 , S 2 , . . . S 10 ). {XX} represents a binary data background word composed by a number of bits equal to the number of bits of the memory word stored in each memory element  104 , while { XX } represents the complement thereof (e.g., if {XX}={000 . . . 00}, then { XX }={111 . . . 11}).  
         [0047]     FIGS.  2 A-C show a flow chart diagram illustrating in more detail each step of the algorithm 8N.  
         [0048]     At the step S 1 , the 8N algorithm sets the value of the data background word {XX} equal to {000 . . . 00} (block  202 ), in such a way that the operations Write{XX}, Read{XX} carried out in the steps S 2 , S 3 , S 4 , S 5  are executed with data background words {XX} equal to {000 . . . 00}, and the operations Write{ XX }, Read{ XX } are executed with data background words {XX} equal to {111 . . . 11}.  
         [0049]     The 8N algorithm includes four different types of “march elements” M 0 , M 1 , M 2 , M 3 . A march element is a finite sequence of one or more test operations that are to be performed on every memory element  104  in the memory matrix  102  before moving on to the next memory element. All the memory elements  104  of the memory matrix  102  are subjected to these same test operations and are traversed according to a particular address sequence. The 8N algorithm includes two different address sequences: an increasing address sequence, denoted in the pseudo-code by the symbol “         ”, and a decreasing address sequence, denoted in the pseudo-code by the symbol “         ”.  
         [0050]     The increasing address sequence of the 8N algorithm in the case of a memory matrix having N addressable memory elements is (denoting the addresses ADD with their decimal value for the sake of simplicity): 
                 (0), (N/2), (1), (N/2+1), (2), (N/2+2), (3), (N/2+3) . . . , 
 
 while the decreasing address sequence is: 
             (N−1), (N/2−1), (N−2), (N/2−2), (N−3), (N/2−3), (N−4) . . .        
 
         [0053]     Using the aforementioned address sequences, it can be shown that both of the address sequences have the peculiarity of being constituted by the repetition of the following steps: two consecutives accesses to memory elements  104  belonging to a same column  110 , followed by two consecutives accesses to memory elements  104  belonging to an adjacent column  110 .  
         [0054]     Referring to  FIG. 3A , an example of increasing address sequence on the memory matrix  102  (having N=16 addressable memory elements  104 ) is shown. Denoting again the addresses ADD with their decimal value, the increasing address sequence is: 
                 (0), (8), (1), (9), (2), (10), (3), (11) . . .        
 
         [0056]     Referring now to  FIG. 3B , an example of decreasing address sequence on the same memory matrix  102  is shown. Denoting again the addresses ADD with their decimal value, the decreasing address sequence is: 
                 (15), (7), (14), (6), (13), (5), (12), (4) . . .        
 
         [0058]     At the step S 2 , the 8N algorithm starts the march element M 0 , initializing the address ADD to (0), i.e., to the address of the first memory element  104  (block  204 ). Successively, a writing operation Write{XX=000 . . . 00} is performed on such memory element  104  (block  206 ); then, if the address ADD is different from (N−1)(i.e., from the address ADD of the last memory element  104 ) (decision block  208 , exit branch N), such address ADD is incremented of a step according to the increasing address sequence (block  210 ), and a writing operation Write{XX=000 . . . 00} is performed on the new addressed memory element  104  (the flowchart jumps back to the block  206 ). Conversely, if the address ADD is equal to (N−1)(decision block  208 , exit branch Y), the 8N algorithm enters the step S 3 .  
         [0059]     At the step S 3 , the 8N algorithm starts the march element M 1 , initializing the address ADD to (0) (block  212 ). Successively, the word stored in the memory element  104  having the address equal to ADD is read and is compared with the word {000 . . . 00} (reading operation Read{XX=000 . . . 00}, block  214 ), and then a writing operation Write{ XX =111 . . . 11} is performed on the same memory element  104  (block  216 ). Consecutively, if the address ADD is different from (N−1) (block  218 , exit branch N), such address ADD is incremented of a step according to the increasing address sequence (block  218 ), and the reading and comparing operations Read{XX=000 . . . 00} with the writing operation Write{ XX =111 . . . 11} are performed on the new addressed memory element  104  (jump back to the block  214 ). Conversely, if the address ADD is equal to (N−1)(block  218 , exit branch Y), the 8N algorithm enters in the step S 4 .  
         [0060]     At the step S 4 , the 8N algorithm starts the march element M 2 . The word stored in the memory element  104  having the address equal to ADD is read and is compared with the word {111 . . . 11} (reading operation Read{ XX =111 . . . 11}, block  220 ), and then a writing operation Write{XX=000 . . . 00} is performed on the same memory element  104  (block  222 ). Consecutively, if the address ADD is different from (0) (block  224 , exit branch N), such address ADD is decremented of a step according to the decreasing address sequence (block  226 ), and the reading and comparing operations Read{ XX =111 . . . 11) with the writing operation Write{XX=000 . . . 00} are performed on the new addressed memory element  104  (the flowchart jumps back to the block  220 ). Conversely, if the address ADD is equal to (0)(block  224 , exit branch Y), the 8N algorithm enters in the step S 5 .  
         [0061]     At the step S 5 , the 8N algorithm starts the march element M 3 , initializing the address ADD to (N−1) (block  228 ). The word stored in the memory element  104  having the address equal to ADD is read and is compared with the word {000 . . . 00} (reading operation Read{XX=000 . . . 00}, block  230 ), and a writing operation Write{ XX =111 . . . 11} is performed on the same memory element  104  (block  232 ). Then, the word stored in the memory element  104  is read and is compared with the word {111 . . . 11} (reading operation Read{ XX =111 . . . 11}, block  234 ). Consecutively, if the address ADD is different from (0) (block  236 , exit branch N), such address ADD is decremented of a step according to the decreasing address sequence (block  238 ), and the reading and comparing operations Read{XX=000 . . . 00}, Read{ XX =111 . . . 11} with the writing operation Write{ XX =111 . . . 11} are performed on the new addressed memory element  104  (the flowchart jumps back to the block  230 ). Conversely, if the address ADD is equal to (0)(block  224 , exit branch Y), the 8N algorithm enters in the step S 6 .  
         [0062]     At the step S 6 , the value of the data background word {XX} is set equal to (010 . . . 10} (block  202 ), in such a way that the operations Write{XX}, Read{XX} carried out in the steps S 7 , S 8 , S 9 , S 10 , are executed with data background words {XX} equal to {010 . . . 10}, and the operations Write{ XX }, Read{ XX } are executed with data background words {XX} equal to {101 . . . 01}. Being the steps S 7 , S 8 , S 9 , S 10  identical to the steps S 2 , S 3 , S 4 , S 5 , except than in the data background word {XX} value, they will not be described in detail for the sake of conciseness.  
         [0063]     Referring again to aforementioned pseudo-code implementing the 8N algorithm, it is possible to calculate the total number of operations N 8N   oper  executed for testing a memory matrix  102  having N addressable memory elements. During the steps S 2 , S 3 , S 4 , S 5 , the algorithm 8N executes the marches M 0 , M 1 , M 2 , M 3 , thus executing eight operations (four writing operations and four reading operations) per memory element  104 . Moreover, during the steps S 7 , S 8 , S 9 , S 10  the algorithm 8N executes again the marches M 0 , M 1 , M 2 , M 3  with a different data background word ({XX}={010 . . . 10}), thus executing eight more operations. Consequently, the total number of operations N 8N   oper  executed by the 8N algorithm is: 
 
 N   8N   oper =8 *N*N   d =8 *N* 2=16 *N,  
 
 (the number of different test patterns used N d  is equal to 2, regardless of the width of the word). 
 
         [0064]     Therefore, compared to the known Marinescu B algorithm, which utilizes a very higher number of test operations N MB   oper , the 8N algorithm is drastically less complex, while being equally efficient, as is discussed hereinbelow.  
         [0065]     In the following there will be described with greater detail the subset of faults that the 8N algorithm can “cover”, i.e., the faults that can be detected by such algorithm. Unless otherwise specified, in the following classical memory fault definitions are used, as stated by A. J. Van de Goor in the cited reference.  
         [0066]     SAFs and TFs are covered since every SRAM cell  106  is read in both states, and after any possible state transition.  
         [0067]     Concerning SOFs, a SRAM cell  106  is said to be “stuck-open” if it is inaccessible, e.g., because its word line WL or its bit lines connections are broken. A read operation on a stuck-open SRAM cell  106  produces unpredictable outputs. SOFs may also present a sequential behavior if a sense amplifier included in the block  128  is such that it holds data of a previous read operation. During the march element M 3  all the SRAM cells are read successively in both states, so that SOFs with sequential behavior are detected. Furthermore, completely random outputs are statistically covered: since in M 3  consecutive read operations of opposite polarity are executed when an address is incremented to the next one, the probability that the fault is masked because expected outputs are accidentally produced is virtually zero.  
         [0068]     SRAM cells  106  can be affected by data losses, e.g., because a pull-up transistor is broken, thus causing a DRF. Such type of fault can be covered examining the dynamic behavior of each SRAM memory cell  106 . Such dynamic behavior is detected by inserting two pauses (e.g., of 10 ms) before M 2  and M 3 .  
         [0069]     Four subtypes of AFs are defined (see A. J. Van de Goor, 3.4), which correspond to cases where two or more addresses ADD access the same memory element  104  or an address ADD points to two or more memory elements  104 . All subtypes of such faults are covered in the 8N algorithm because in the march element M 1 , in combination with the march element M 2 , the condition that the following operations are included is satisfied (see A. J. Van de Goor, 3.5.2): 
                 Read{XX} . . . −Write{ XX }             Read{ XX } . . . −Write{XX}       
 
         [0072]     In SRAMs memories, AFs may cause one or more SRAM cells to become inaccessible (implying a SOF); in this case the full coverage of AFs requires that SOFs are also detected: as seen, the 8N algorithm can detect all SOFs and hence AF coverage is guaranteed.  
         [0073]     Inter-word state coupling faults (SCFs) (i.e., coupling faults among different memory elements  104 ) are covered because, for every SRAM cell  106  pair belonging to different memory elements  104  and for each state of said cell pair, both cells are read. The following table illustrates for a generic pair of cells (a) and (b), which one is read first, and in correspondence of which march elements, as a function of the state of the pair (cell(a) address lower than cell(b) address):  
                                       state (a)(b)   cell (a)   cell (b)                   00   M1   M3       01   M3   M3       10   M2   M1       11   M3   M2                  
 
         [0074]     Intra-word SCFs (i.e., coupling faults among SRAM cells  106  belonging to the same memory element  104 ) are conditionally covered. The two different data backgrounds {XX} used in the 8N algorithm cover only intra-word SCFs between bits of consecutive index (see A. J. Van de Goor, C.3).  
         [0075]     Nonetheless, thanks to the design and layout constraints used for implementing the memory matrix  102 , the 8N algorithm covers all realistic intra-word SCFs.  
         [0076]     In particular, if each SRAM cell is physically separated from cells of the same word, no SCFs may occur.  
         [0077]     Otherwise, if the above condition is unattainable due to topological constraints (e.g., no column multiplexing is provided), adjacent SRAM cells of the same word have consecutive indices, and so are intrinsically covered by using the two different data backgrounds {XX} employed in the 8N algorithm. Moreover, the data paths (i.e., read/write circuits and interconnects) of SRAM cells having nonconsecutive indices are physically separated, and thus they do not imply SCFs.  
         [0078]     A linked SCF (LSCF) is an SCF involving more than two cells. Assuming that N SCFL  is a number of coupling cells whose address is lower than the coupled cell, and N SCFH  is a number of coupling cells whose address is higher than the coupled cell, it can be shown that an LSCF is equivalent to a single SCF if at least one of the following conditions is verified (Mikitjuk, V. G., Yarmolik, V. N., van de Goor, A. J.: “RAM Testing Algorithms for Detection Multiple Linked Faults”, In Proc. Of the 1996 European Test Conference, Paris 1996.):  
         [0079]     1. the result of a reading operation on the coupled cell is a deterministic function of all coupling states;  
         [0080]     2. N SCFL =1 or N SCFH =1;  
         [0081]     3. N SCFL &gt;1, but all the coupling cells have the same effect on the coupled cell; and  
         [0082]     4. N SCFH &gt;1, but all the coupling cells have the same effect on the coupled cell  
         [0083]     If none of the above conditions is verified, the LSCF cannot be detected by a march test. It is instead needed a O(N 2 ) algorithm; however, while an LSCF is possible, its probability of occurrence is extremely low, particularly considering that coupled cells on a LSCF are generally all the cells in a column  110 .  
         [0084]     Inversion coupling faults (Cins) are irrelevant to the SRAMs field. Idem potent coupling effects (Cids) may affect SRAMs in the form of capacitive coupling between bit lines of SRAM cells  106  of the same row  108 . If the capacitive coupling is large enough, the transition to “0” of a bit line in a cell may cause the transition to “0” of a bit line of a neighboring cell, and corrupt the cell content. This is especially true during write operations, in which one of the two bit lines in the cell being written is pulled down to ground.  
         [0085]     Thanks to the abovementioned layout constraints, Cids are nullified by the memory design: 
        bit lines in every cell are paralleled with shield lines  112  that shield them from the capacitive coupling of the adjacent columns; and     in case of column multiplexing, the bit lines of non-addressed cells in a row  108  are clamped to Vdd (by precharge control circuits) throughout the read operations, thus providing a low-impedance path for the capacitive noise.        
 
         [0088]     Most memory design solutions implement both solutions above. At least one solution is implemented in all designs. Therefore, Cids is automatically not relevant.  
         [0089]     Furthermore, linked Cins or Cids (i.e., involving three or more SRAM cells) are even less relevant and will not be analyzed.  
         [0090]     Dynamic coupling faults (Cdyn), also known as “disturb fault”, imply that reading operations may induce faults by transition or coupling. This kind of fault is irrelevant to SRAMs, because reading operations imply very low bit line voltage swings, whose energy is too low to cause a change in the state of the coupled cell. Like Cids, Cdyns are in any case made irrelevant by design.  
         [0091]     The WTFs make the state of input data affect read operations. This type of fault may be caused by the presence of shorted write drivers. The 8N algorithm reads every SRAM memory cell in both states, when input data are at 0 and when they are at 1. This kind of test is possible also thanks to the inversion of memory cell input data during read operations in the march element M 3 . Consequently, WTF are covered.  
         [0092]     Due to the possible presence of stuck-open transistors, combinatorial logic in the address decoders  120 ,  125  may exhibit a sequential behavior. In this case, detecting the fault requires an initialization sequence for each address (see A. J. Van de Goor, B.4). The 8N algorithm does not cover SOAFs. However, the statistical significance of SOAFs has been empirically proven by the applicants to be very low on real designs.  
         [0093]     If a defect in a precharge circuit of a column  110  makes bit lines very slow to recover their steady state (particularly after a write), a subsequent read of opposite polarity on the same column may fail because the corresponding sense amplifier is unbalanced, implying thus an UWF.  
         [0094]     To detect UWFs, a generic test algorithm has to:  
         [0095]     sweep the memory address space by columns;  
         [0096]     run at the maximum memory operating speed;  
         [0097]     for every column, read 0 after writing 1, read 1 after writing 0.  
         [0098]     The 8N algorithm covers UWFs because M 1  and M 2  alternate read and write operations of opposite polarity with an address sequence that is by rows and columns, as previously explained.  
         [0099]     It has to be noted that it is possible implementing the 8N algorithm using only a single data background word {XX} (thus, halving the number of test operations required) provided that the memory matrix  102  has a particular structure, such that SRAM cells  106  belonging to a same memory element  104  are physically separated from each other, and no capacitive coupling is possible. However, this layout restriction is generally very difficult to satisfy and its implementation requires a column multiplexing. The use of the two data background words {XX=000 . . . 00}, {XX=010 . . . 10} allows fully testing memories which not necessarily have such a particular matrix structure.  
         [0100]     The 8N algorithm is an irredundant march memory test, since it contains the minimum required number of operations to cover all realistic faults. The number of operations required is fixed by the SCF&#39;s coverage, that is the fault type requiring the highest number of operations for the detection. In order to cover SCF faults at least eight reading operations are needed for each word.  
         [0101]     In the following table there is shown the evolution of the state of a generic couple of SRAM cells C a  and C b  during the progress of the steps S 2 , S 3 , S 4 , S 5  (that is, with data background word {XX} equal to {000 . . . 00}) of the 8N algorithm (“U” means “undefined”); the two SRAM cells C a  and C b  belong to different memory elements  104 , and the address ADD of the cell C a  is assumed to be lower than the address of the cell C b :  
                                               Operation on   Operation on           March       cell C a     cell C b     State C a     State C b     Element                   —   —   U   U   —       Write{xx}   —   {000...00}   U   M0       —   Write{xx}   {000...00}   {000...00}   M0       Read{xx}   —   {000...00}   {000...00}   M1       Write{ xx }   —   {111...11}   {000...00}   M1       —   Read{xx}   {111...11}   {000...00}   M1       —   Write{ xx }   {111...11}   {111...11}   M1       —   Read{ xx }   {111...11}   {111...11}   M2       —   Write{xx}   {111...11}   {000...00}   M2       Read{xx}   —   {111...11}   {000...00}   M2       Write{xx}   —   {000...00}   {000...00}   M2       —   Read{xx}   {000...00}   {000...00}   M3       —   Write{ xx }   {000...00}   {111...11}   M3       —   Read{ xx }   {000...00}   {111...11}   M3       Read{xx}   —   {000...00}   {111...11}   M3       Write{ xx }   —   {111...11}   {111...11}   M3       Read{ xx }   —   {111...11}   {111...11}   M3                  
 
         [0102]     Referring now to  FIG. 4 , a BIST system implementation of the 8N algorithm is illustrated. More particularly, an IC  400  including the memory device  100  comprises four finite states machines (FSMs) structured to execute the 8N algorithm on the SRAM memory device  100 . Furthermore, referring to  FIG. 4  and to the following Figures, for the sake of simplicity signals and corresponding physical lines carrying them are denoted with the same references.  
         [0103]     A master controller FSM  405 , whose purpose is to control three slave FSMs  410 ,  415 ,  420 , is connected thereto by means of two buses of lines, namely, a first bus BUS_START and a second bus BUS_DONE. Each slave FSM receives an operation start signal, from the master controller FSM  405  by means of a predetermined line of the bus BUS_START, and provides an operation end signal to master controller FSM  405  by means of a predetermined line of the bus BUS_DONE. The operation start signal is asserted by the master FSM  405  to cause such slave FSM to start its operation; the slave FSM asserts the respective operation end signal when it has accomplished its duty. More particularly, a timer FSM  410 , including counter circuits for the timing of the entire system, receives a signal START( 0 ) from the bus BUS_START and provides a signal DONE( 0 ) to the bus BUS_DONE. An 8N algorithm FSM  415 , implementing the 8N algorithm, receives a signal START( 1 ) from the bus BUS_START and provides a signal DONE( 1 ) to the bus BUS_DONE. Finally, a port test FSM  420 , implementing simple tests on the control ports of the memory device IC  400  (not shown in the Figure and not relevant for the understanding of the present invention), receives a signal START( 2 ) from the bus BUS_START and provides a signal DONE( 2 ) to the bus BUS_DONE. The memory device IC  400  further includes a multiplexer  425 , receiving at its input terminals two buses AL_OUT, PT_OUT provided by the 8N algorithm FSM  415  and by the port test FSM  420 , respectively. The multiplexer  425  selects one among said two buses AL_OUT, PT_OUT, by means of a control signal START( 3 ) taken from the bus BUS_START, and provides two output buses BMMI and BEXPD. More particularly, a BIST mode memory input bus BMMI is provided to an input of a further multiplexer  430 , while a BIST expected data bus BEXPD is provided to an input of a comparator block  435 . The multiplexer  430  receives as a further input a normal mode memory input bus NMMI, and selects one among the two bus lines BMMI, NMMI by means of a test signal TEST, connecting it to the SRAM memory device  100  inputs. The SRAM memory device  100  provides a memory output bus MOUT to a further input of the comparator block  435 . The comparator block  435  provides to the outside of the memory device IC  400  a signal OUT providing test result information.  
         [0104]     The memory device IC  400  can operate in two different modes, that is, in test mode, and in standard operation mode.  
         [0105]     During the standard functioning, the master controller FSM  405  is driven in such a way to deactivate the slave FSMs  410 , 415 , 420 . The signal TEST is driven in such a way that the multiplexer  430  selects the normal mode memory input bus NMMI, providing data, commands and addresses, coming from outside the memory, to the SRAM memory device  100 . In this way the SRAM memory device  100  is (possibly) utilized by a user or by another electronic device (possibly embedded in the same chip) for storing and/or reading information in its memory elements  104 .  
         [0106]     During the test functioning, triggered for example by the assertion of a signal denoted as START, the master controller FSM  405  activates the slave FSMs  410 , 415 , 420 . Moreover, the signal TEST is driven in such a way that the multiplexer  430  selects the BIST mode memory input bus BMMI, which is composed by control lines providing control signals for controlling the memory device, e.g., providing a read/write command, a group of lines providing memory elements addresses, and a further group of lines providing data to be written in the SRAM memory device  100  for testing it; consequently, the SRAM memory device  100  executes such received commands on the memory elements  104  that are addressed. Successively, the results of the operations carried out by the SRAM memory device  100  in response of the commands received (i.e., the (expectedly) modified data contents of the addressed memory elements  104 ) are provided to an input of the comparator block  435  by means of the memory output bus MOUT. Moreover, the comparator block  435  further receives by means of the BIST expected data bus BEXPD expected data that are to be compared with the data provided by the SRAM memory device  100 . If the SRAM memory device  100  has accomplished in a correct way the required operations on the addressed memory elements  104 , the expected data coincide with the data provided by the SRAM memory device  100  itself, so the comparator block  435  signals, by means of the OUT signal, that the addressed memory elements  104  do not present faults. Conversely, if a fault occurs, the data provided by the SRAM memory device  100  do not coincide with the expected data, and the comparator block  435  signals it to the outside by means of the OUT signal.  
         [0107]     All the data and the information necessary to execute the test on the SRAM memory device  100 , that is, the data, the addresses and the commands provided by the two buses BMMI and BEXPD, can be generated either by the 8N algorithm FSM  415  (and made available by means of the bus AL_OUT), or by the port test FSM  420  (and made available by means of the bus PT_OUT), depending on the value taken by the signal START( 3 ).  
         [0108]      FIG. 5  provides a more detailed view of the 8N algorithm FSM  415  (the specific structure and operation of the port test block is not relevant to the understanding of the invention embodiment herein considered).  
         [0109]     The 8N algorithm FSM  415  includes a timer block  505 , an address enable generator block  510 , an address counter  515  and an algorithm block  520 .  
         [0110]     The timer block  505 , whose purpose is the timing of the other circuital blocks included in the 8N algorithm FSM  415 , receives the signal START( 1 ) from the bus BUS_START, three signals L_ADD, M_ADD, H_ADD from the address counter  515  and provides a code STEP to the address enable generator  510 , a signal UP_DOWN to the address counter  515 , and a CONTINUE signal to the algorithm block  520 .  
         [0111]     The address enable generator  510  receives the code STEP from the timer block  505 , and commands the address counter  515  by means of an address enable signal ADD_EN, as will be explained in the following.  
         [0112]     The address counter  515 , receiving the signal UP_DOWN and the signal ADD_EN, generates the address ADD, and the signals L_ADD, M_ADD, H_ADD. The algorithm block  520 , that generates the commands and the data necessary for the test functioning according to the 8N algorithm, receives from the timer block  505  the signal CONTINUE. Said commands and data generated by the algorithm block  520  constitute, in concert with the address ADD, the bus AL_OUT that is provided to the multiplexer  425 . More particularly, the algorithm block  520  generates a write enable signal WEN 1 , an expected data word DATAEXP 1  and an input data word DATAWR 1 . The algorithm block  520  provides the signal DONE( 1 ) to the bus BUS_DONE.  
         [0113]     Furthermore, in the  FIG. 5  it is detailed also the bus PT_OUT, connecting the port test block  420  with the multiplexer  425 : it includes an address bus ADD 2 , a line carrying a write enable signal WEN 2 , a bus carrying an expected data word DATAEXP 2  and a further bus carrying an input data word DATAWR 2 . Finally, the BIST mode memory input bus BMMI is composed by an address bus ADDM, a line carrying a write enable signal WEN and a bus carrying an input data word DATAWR.  
         [0114]     When the signal START( 3 ) is driven in such a way to select the bus AL_OUT, the BIST expected data bus BEXPD receives the expected data word DATAEXP 1 , the address bus ADDM receives the address ADD, the input data word DATAWR assumes the value of the input data word DATAWR 1 , and the write enable signal WEN assumes the value of the write enable signal WEN 1 .  
         [0115]     Conversely, when the signal START( 3 ) is driven in such a way to select the bus PT_OUT, the BIST expected data bus BEXPD receives the expected data word DATAEXP 2 , the address bus ADDM receives the address ADD 2 , the input data word DATAWR assumes the value of the input data word DATAWR 2 , and the write enable signal WEN assumes the value of the write enable signal WEN 2 .  
         [0116]     When the signal START( 1 ) is driven to a high logic value, the 8N algorithm FSM  415  is activated by the timer block  505 , that begins to generate the code STEP and the digital signals UP_DOWN, CONTINUE as a function of the digital signals L_ADD, M_ADD, H_ADD.  
         [0117]     More particularly, STEP is a two bit code representing the “dimension” (i.e., the number of operations per word) of each march element M 0  . . . M 3 . For example, if the 8N algorithm FSM  415  is executing the march element M 0 , which includes a single operation (Write{XX}), the code STEP assumes the value “01”. If the 8N algorithm FSM  415  is executing the march element M 1  or the march element M 2 , including each one two operations (Read{XX} and Write{ XX }, or Read{ XX } and Write{XX}), the code STEP assumes the value “10”. If the 8N algorithm FSM  415  is executing the march element M 3 , which includes three operations (Read{XX}, Write{ XX } and Read{ XX }), the code STEP assumes the value “11”. Finally, if the 8N algorithm FSM  415  is in stand-by mode, that is, it is not executing any march element, the code STEP assumes the value “00”.  
         [0118]     The signal UP_DOWN provided to the address counter  515  is a one-bit signal whose logic value is necessary to discriminate the increasing address sequence (         ) from the decreasing address sequence (         ). For example, if the signal UP_DOWN is at the value “0”, the address counter  515  generates addresses according to an increasing address sequence; conversely, if the signal UP_DOWN is at the value “1”, the address counter  515  generates addresses following a decreasing address sequence.  
         [0119]     The signal CONTINUE is a one-bit signal that is provided to the algorithm block  520  in such a way to signal thereto when a transition from a march element to the subsequent one occurs. For example, the signal CONTINUE assumes the value “1” in occurrence of said transitions, otherwise it assumes the value “0”.  
         [0120]     The code STEP and the digital signals UP_DOWN and CONTINUE are generated by the timer block  505  depending on the address ADD evolution, observable by counting occurrences of “1”s in the digital signals L_ADD, M_ADD, H_ADD provided by the address counter  515 . Every time one among the signals L_ADD, M_ADD, H_ADD assumes a “1” value, an internal counter, not shown in the Figure, increments a counter value CNT. The signal L_ADD assumes a “1” value if the address ADD is equal to a predefined low value (in the example at issue, said low value corresponds to the lowest address (0)). The signal M_ADD assumes a “1” value if the address ADD is equal to a predefined intermediate value (in the example at issue, said intermediate value corresponds to the address (N/2)). The signal H_ADD assumes a “1” value if the address ADD is equal to a predefined high value (in the example at issue, said high value corresponds to the highest address (N−1)).  
         [0121]     Referring to  FIG. 6 , a state diagram  600  illustrating the generation sequence of the code STEP is shown. As long as the signal START( 1 ) is at “0” value, the code STEP assumes the value “00” (block  605 ). When the signal START( 1 ) assumes the “1” value, the code STEP assumes the value “01”, and maintains it until the value of the counter value CNT is different from “2” (block  610 ). When the counter value CNT equals the value “2”, the code STEP assumes the value “10”, and maintains it until the value of the counter value CNT is different from “14” (block  615 ). When the counter value CNT equals the value “14”, the code STEP assumes the value “11”, and maintains it until the value of the counter value CNT is different from “24” (block  620 ). When the counter value CNT assumes the value “24” the address sequence is finished, and then the code STEP reassumes the value “00”. The generation of the signals CONTINUE and UP_DOWN occurs in a similar way, and it is briefly explained by the two following tables:  
                                                                                 CNT   CONTINUE   CNT   UP_DOWN                                        7   1   2   1           14    1   8   1           0   1   14   1           ELSE   0   ELSE   0                      
 
         [0122]     The address enable generator block  510  provides to the address counter  515  the address enable signal ADD_EN. The purpose of said address enable signal ADD_EN is to enable the address counter  515  to increment (or decrement, depending by the value of the signal UP_DOWN) the address ADD, according to the utilized address sequence. More particularly, the address counter  515  executes the increment (or the decrement) when the address enable signal ADD_EN assumes the value “1”.  
         [0123]     Given that the occurrence of these address increments depends from the number of operations within the different march elements M 0  . . . M 3 , the address enable generator  510  generates the address enable signal ADD_EN depending on the code STEP, for example exploiting the circuit structure shown in  FIG. 7A . The address enable generator  510  includes a multiplexer  705  having four input terminals, a control terminal receiving the code STEP, and an output terminal providing the address enable signal ADD_EN. The first input terminal, that is selected when the code STEP is equal to “00”, is connected to a line stuck at “0”. The second input terminal, that is selected when the code STEP is equal to “01”, is connected to a line stuck at “1”. The third input terminal, that is selected when the code STEP is equal to “10”, is connected to an output terminal Q 1  of a toggle flip-flop  710  whose input terminal T 1  is stuck at “11” and its clock terminal receives a system clock signal CK. The fourth input terminal, that is selected when the code STEP is equal to “11”, is connected to an input terminal of an inverter gate  712 . An output terminal of the inverter gate  712  is connected to an input terminal T 1  of a further toggle flip-flop  714 , having a clock terminal receiving the system clock signal CK, and a complementary output terminal Qn 2  connected to an input terminal D 3  of a delay flip-flop  716 . Said delay flip-flop  716  has a clock terminal receiving the system clock signal CK, and a complementary output terminal Qn 3  connected to the input terminal of the inverter gate  712 .  
         [0124]     When the march element M 0  is selected (STEP=“01”), the address enable signal ADD_EN is stuck at the value “1”, thus enabling the address counter  515  to increment (or decrement) the address ADD at every clock leading edge of the system clock signal clock. Referring to  FIG. 7B , wherein a time diagram illustrates the temporal evolutions of the system clock signal CK, of the output terminal Q 1  and of the complementary output terminal Qn 3 , it can be noted that when the march element “M 1 ” or “M 2 ” is selected (STEP=“10”), the address enable signal ADD_EN changes value at every clock leading edge. In this way, the address counter  515  is enabled to increment (or decrement) the address ADD every two clock leading edges of the system clock signal clock, thus allowing the execution of two consecutive operations on the same address ADD. Finally, when the march element “M 3 ” is selected (STEP=“11”), the address enable signal ADD_EN assumes the “1” value every three clock leading edges, thus allowing the execution of three consecutive operations on the same address ADD.  
         [0125]     The address counter  515 , receiving from the address enable generator block  510  the signal ADD_EN, and from the timer block  505  the signal UP_DOWN, generates accordingly the address ADD and the signals H_ADD, M_ADD and L_ADD. Referring to  FIG. 8 , a state diagram  800  illustrating the functioning of the address counter  515  is shown. Since the 8N algorithm initiates with an increasing address sequence (signal UP_DOWN=0) that starts from the lowest address value (0), the address counter  515  sets the address ADD to (0) (block  805 ). When the signal ADD_EN assumes the value “1”, the address counter  515  increments the address ADD by (N/2) (state SUP 1 , block  808 ). When the signal ADD_EN assumes again the value “1”, the address counter  515  increments the previous address ADD by (1−N/2) (state SUP 2 , block  810 ). In correspondence of each successive occurrence of “1”s in the signal ADD_EN, the address counter  515  carries on an address increment on the address ADD, alternately by (N/2) (state SUP 1 , block  808 ) and (1−N/2) (state SUP 2 , block  810 ). This process continues until the address ADD assumes the highest value (N−1); in this way, the correct increasing address sequence (0), (N/2), (1), (N/2+1), (2), (N/2+2), (3), . . . , (N−1) is generated. If, when the address ADD assumes the highest value (N−1), the signal UP_DOWN remains at the “0” value, the address counter  515  restarts an increasing address sequence, resetting the address ADD to (0) (block  805 ).  
         [0126]     Conversely, if, when the address ADD assumes the highest value (N−1), the signal UP_DOWN assumes the “1” value, the address counter  515  starts a decreasing address sequence. Given that the first address of the decreasing address sequence is (N−1), i.e., it is equal to the last address of the previous increasing address sequence, the first time the signal ADD_EN assumes again the value “1”, it is not necessary to execute any increment operation (state S 0 , block  815 ). In correspondence of a following “1” in the signal ADD_EN, the address counter  515  increments the address ADD by (−N/2) (state SDOWN 1 , block  818 ). When the signal ADD_EN assumes again the value “1”, the address counter  515  increments the previous address ADD by (N/2−1) (state SDOWN 2 , block  820 ). In correspondence of each successive occurrence of “1”s in the signal ADD_EN, the address counter  515  carries on an address increment on the address ADD, alternately by (−N/2) (state SDOWN 1 , block  818 ) and (N/2−1) (state SDOWN 2 , block  820 ). This process continues until the address ADD assumes the lowest value (0); in this way, the correct decreasing address sequence (N−1), (N/2−1), (N−2), (N/2−2), (N−3), (N/2−3), . . . , (0) is generated. If, when the address ADD assumes the lowest value (0) the signal UP_DOWN remains at the “1” value, the address counter  515  restarts a decreasing address sequence, firstly resetting the address ADD to the value (N−1) (block  822 ); then, in correspondence of a following “1” in the signal ADD_EN, the abovementioned sequence of increments by (−N/2) and (N/2−1) is repeated.  
         [0127]     Conversely, if when the address ADD assumes the lowest value (0), the signal UP_DOWN assumes the “0” value, the address counter  515  starts a new increasing address sequence, necessary for repeating the test operations for a second time (e.g., when the data background word {XX} is changed). Given that the first address of the increasing address sequence is (0), i.e., it is equal to the last address of the previous decreasing address sequence, when the signals ADD_EN assumes again the value “1” for the first time, it is not necessary to execute any increment operation (state S 1 , block  824 ). In correspondence of a following “1” in the signal ADD_EN, the address counter  515  increments the address ADD by (N/2) (state SUP 1 , block  808 ), and so on.  
         [0128]     Referring now to  FIG. 9 , an exemplary circuital implementation of the address counter  515  is shown. The address counter  515  includes a local FSM  905 , whose purpose is to select a particular increment in such a way to generate the correct address sequence according to the values of the signals ADD_EN and UP_DOWN, as described previously. The local FSM  905  receives, in addition to the signals ADD_EN and UP_DOWN, the address ADD, a code (N−1) representing the binary value of the highest address value (N−1), and a code (0) representing the binary value of the lowest address value (0). Moreover, the local FSM  905  provides to the control terminal of a multiplexer  910  a code STATE, and to an address register  915  a code RESET. The possible values assumed by the code STATE correspond to the states SUP 1 , SUP 2 , SDOWN 1 , SDOWN 2 , S 0 , S 1  mentioned above.  
         [0129]     The multiplexer  910  receives at its input terminals six buses, each one carrying a fixed code word. More particularly, the first terminal receives a digital code (N/2) representing the binary value of the address (N/2), and is selected when the code STATE provided by the local FSM  905  is SUP 1 . The second terminal receives a digital code (1−N/2) representing the binary value of the address (1−N/2), and is selected when the code STATE provided by the local FSM  905  is SUP 2 . The third terminal receives the code (0), and is selected when the code STATE provided by the local FSM  905  is S 0 . The fourth terminal receives a digital code (−N/2) representing the binary value of the address (−N/2), and is selected when the code STATE provided by the local FSM  905  is SDOWN 1 . The fifth terminal receives a digital code (N/2−1) representing the binary value of the address (N/2−1), and is selected when the code STATE provided by the local FSM  905  is SDOWN 2 . Finally, the sixth terminal receives the code (0), and is selected when the code STATE provided by the local FSM  905  is S 1 . The multiplexer  910  further includes an output bus that is provided to an input of an adder block  920  required to execute the necessary address increment.  
         [0130]     The address register  915  includes a clock terminal receiving the system clock signal CK, an input terminal receiving a code NADD provided by the adder block  920 , an output terminal providing the address ADD, and a control terminal receiving the code RESET from the local FSM  905 .  
         [0131]     The adder block  920  comprises a first terminal receiving a code by the output terminal of the multiplexer  910 , a second terminal receiving the address ADD, and an output terminal providing the code NADD.  
         [0132]     The address counter  515  further includes three digital comparators  925 ,  930 ,  935  that generate the signals H_ADD, M_ADD and L_ADD exploited by the timer block  505 . More particularly, the comparator  925  includes a first input terminal receiving the code (N−1), a second input terminal receiving the address ADD, and an output terminal providing the signal H_ADD. The comparator  930  includes a first input terminal receiving the code (N/2), a second input terminal receiving the address ADD, and an output terminal providing the signal M_ADD. The comparator  935  includes a first input terminal receiving the code (0), a second input terminal receiving the address ADD, and an output terminal providing the signal L_ADD.  
         [0133]     The core of the address counter  515  is the local FSM  905 . The code STATE assumed time by time by the local FSM  905  is used to select the corresponding increment according to the state diagram  800 . Such selected increment is provided to the adder block  920 , that adds it to an address ADD stored previously in the address register  915 . The result of such operation, that is the code NADD, is then provided to the address register  915 , replacing the previous address ADD. In this way, the sequence of values assumed by the address ADD follows the address sequence controlled by the local FSM  905 . Moreover, the local FSM  905  can set the address ADD to (0) or to (N−1) by means of the code RESET, as requested by the functioning of the state diagram  800 .  
         [0134]     The signal H_ADD provided by the comparator  925  assumes the value “1” when the address ADD equals (N−1), the signal M_ADD provided by the comparator  930  assumes the value “1” when the address ADD equals (N/2), and the signal L_ADD provided by the comparator  935  assumes the value “1,” when the address ADD equals (0), otherwise, they assumes the value “0”.  
         [0135]     The algorithm block  520 , receiving from the timer block  505  the signal CONTINUE, generates accordingly the write enable signal WEN 1 , the expected data word DATAEXP 1 , and the input data word DATAWR 1 . Referring now to  FIG. 10 , a state diagram  1000  describing the functioning of such algorithm block  520  is illustrated. The algorithm block  520  includes a FSM machine with a dedicated state for each operation carried out in the 8N algorithm. Consequently, the state diagram  1000  includes eight different states, one state per operation. Furthermore, the evolution of the signal CONTINUE (i.e., its “1”s occurrences) scans the transitions among the different march elements M 0 , . . . , M 3 .  
         [0136]     Initially, the algorithm block  520  commands the operation Write{XX=000 . . . 00} (state  000 , block M 0 ), as stated by the march element M 0 . When the signal CONTINUE assumes the value “1”, the algorithm block  520  commands the operation Read{XX} (state  001 , block M 1   a ), and then commands the operation Write{ XX } (state  010 , block M 1   b ). Subsequently, the algorithm block  520  repeats these two operations until the signal CONTINUE assumes again the value “1”. These cyclic state transitions are due to the internal temporization of the algorithm block  520 . In this way, all the operations included in the march element M 1  are carried out. When the signal CONTINUE assumes again the value “1”, the algorithm block  520  commands the operation Read{ XX } (state  011 , block M 2   a ), and then it commands the operation Write{ XX } (state  100 , block M 2   b ). Subsequently, the algorithm block  520  repeats these two operations until the signal CONTINUE assumes again the value “1”. In this way, all the operations included in the march element M 2  are carried out. When the signal CONTINUE assumes again the value “1”, the algorithm block  520  commands the operation Read{XX} (state  101 , block M 3   a ), then it commands the operation Write{ XX }(state  110 , block M 3   b ), and then it commands the operation Read{ XX } (state  111 , block M 3   c ). Subsequently, the algorithm block  520  repeats these three operations until the signal CONTINUE assumes again the value “1”. In this way, all the operations included in the march element M 3  are carried out. When the signal CONTINUE assumes again the value “1”, a background flag BFLG assumes a value “1”, indicating that the subsequent operations are to be executed with the other data background word (i.e., {XX}={010 . . . 10}). Thus, the algorithm block  520  commands the operation Write{XX=010 . . . 10} (return to the state  000 , block M 0 ), and then it repeats all the other operations.  
         [0137]     In the following, a table illustrating the evolution of the algorithm block  520  FSM machine is shown.  
                                                                                 state   March                block   operation   S(2)   S(1)   S(0)   Element                       M0   Write{XX}   0   0   0   M0           M1a   Read{XX}   0   0   1   M1           M1b   Write{ XX }   0   1   0           M2a   Read{ XX }   0   1   1   M2           M2b   Write{XX}   1   0   0           M3a   Read{XX}   1   0   1   M3           M3b   Write{ XX }   1   1   0           M3c   Read{ XX }   1   1   1                      
 
 where S( 2 ), S( 1 ) and S( 0 ) are the three state bits denoting the different states of the state diagram  1000 . 
 
         [0138]     Referring again to the state diagram  1000  and to the previous table, it has to be noted that each state is codified in such a way to allow obtaining output signals from the state bits. Specifically, the state bit S( 0 ) corresponds to the write enable signal WEN 1  (WEN 1 =0 corresponds to a writing operation, WEN 1 =1 corresponds to a reading operation).  
         [0139]     The state bit S( 1 ) determines the expected data word DATAEXP 1 . More particularly, the expected data word DATAEXP 1  is equal to:  
         [0140]     .{000 . . . 00} if the state bit S( 1 ) is equal to “0” and the background flag BFLG is equal to “0”;  
         [0141]     .{111 . . . 11} if the state bit S( 1 ) is equal to “1” and the background flag BFLG is equal to “0”;  
         [0142]     .{010 . . . 10} if the state bit S( 1 ) is equal to “0” and the background flag BFLG is equal to “1”; and  
         [0143]     .{101 . . . 01} if the state bit S( 1 ) is equal to “1” and the background flag BFLG is equal to “1”.  
         [0144]     Furthermore, the input data word DATAWR 1  to be written into the memory element  104  is calculated by means of all the three state bits S( 2 ), S( 1 ), S( 0 ), and by means of the background flag BFLG, as is shown in the next table.  
                                               DATAWR1   S(2)   S(1)   S(0)   BFLG                   {000...00}   0   0   0   0       {000...00}   0   0   1   0       {111...11}   0   1   0   0       {111...11}   0   1   1   0       {000...00}   1   0   0   0       {111...11}   1   0   1   0       {111...11}   1   1   0   0       {000...00}   1   1   1   0       {010...10}   0   0   0   1       {010...10}   0   0   1   1       {101...01}   0   1   0   1       {101...01}   0   1   1   1       {010...10}   1   0   0   1       {101...01}   1   0   1   1       {101...01}   1   1   0   1       {010...10}   1   1   1   1                  
 
         [0145]     With reference to the previous table, it is possible showing that when the state bit S( 2 ) is equal to “0” (march elements M 0 , M 1 , and first part of M 2 ), the input data word DATAWR 1  is equal to the expected data word DATAEXP 1 . Conversely, when the state bit S( 2 ) is equal to “1” (the other part of march element M 2  and all the march element M 3 ), the input data word DATAWR 1  is equal to the expected data word DATAEXP 1  during writing operations (S( 0 )=0), otherwise (S(O)=1) it is the complement thereof. This particular inversion has been used because of the necessity to test WTFs during the march element M 3 .  
         [0146]     All of the above U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet, are incorporated herein by reference, in their entirety.  
         [0147]     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.