Abstract:
A video processing apparatus includes a video decoder and a video encoder to process video frames. The video decoder generates decompressed frames from first compressed video frames and write the decompressed frames to a memory, at least one of the decompressed frames being generated using information from a previously generated decompressed frame. The video encoder generates second compressed video frames from the decompressed frames without duplicating the decompressed frames.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims priority to U.S. provisional patent application Ser. No. 60/596,851, filed on Oct. 26, 2005, titled “Video codec and display system using shared memory space,” the contents of which are incorporated by reference. 
     
    
     BACKGROUND  
       [0002]     This description relates to memory sharing in video transcoding and displaying.  
         [0003]     A video transcoder is useful in decoding an encoded video (e.g., compressed video) and subsequently encoding the decoded video according to a different encoding scheme. A video includes a sequence of frames (also referred to as pictures), each frame including rows and columns of pixels. The transcoder may receive a first compressed video and generate a second compressed video, in which the second compressed video, for example, has a higher compression ratio and/or a lower resolution as compared to the first compressed video.  
         [0004]     In some examples, the first and second compressed videos have the same resolution (i.e., each frame in the first compressed video has the same number of columns and rows as each frame in the second compressed video) but have different bit rates (e.g., the first compressed video may have a bit rate of 150 to 300 kbps, whereas the second compressed video may have a bit rate of 30 to 150 kbps). For video that is compressed according to an MPEG standard, changing a quantization level can change the bit rate of the video without changing the resolution. Increasing the quantization level will cause more bits to be truncated during the encoding process, resulting in a compressed video having a lower bit rate and a lower image quality.  
         [0005]     In some examples, the first and second compressed videos having different resolutions. For example, the first compressed video can be a high definition television (HDTV) program having 1920×1080 resolution. If the user has a television with 1366×768 resolution, when he records the HDTV program for future viewing, it is useful to transcode the compressed 1920×1080 video to a compressed 1366×768 video to match the resolution of his television. By increasing the compression ratio and/or decreasing the resolution of a video, the user can reduce the bit rate of the compressed video so that more video programs can be stored in a given amount of storage.  
         [0006]     For some compression algorithms, such as MPEG-2 or MPEG-4, the order in which frames are displayed is different from the order in which the frames are encoded/decoded. The MPEG standard defines intra (I), unidirectional (P), and bi-directional (B) frames, in which the I frames are compressed without reference to the other frames, the P frames are compressed/decompressed using information from a previous I frame or P frame, and the B frames are compressed/decompressed using information from a previous I or P frame and a subsequent I or P frame. For example, the frames may be displayed according to a “display order”: I 0 , B 1 , B 2 , P 3 , B 4 , B 5 , P 6 , B 7 , B 8 , P 9 , B 10 , B 11 , etc., in which the frame I 0  is an I-frame that is displayed during time interval T 0 , the frame B 1  is a B-frame that is displayed during time interval T 1 , and so forth. On the other hand, the frames may be encoded/decoded according to an “encode order”: I 0 , P 3 , B 1 , B 2 , P 6 , B 4 , B 5 , P 9 , B 7 , B 8 , P 12 , B 10 , B 11 , etc., indicating that the frame P 3  is encoded/decoded before the frames B 1  and B 2 , even though the frames B 1  and B 2  are displayed before the frame P 3 . Because the encoding/decoding sequence is different from the display sequence, when a compressed video is transcoded so that it can be viewed on a display and recorded in a storage medium, several memory buffers are used to temporarily store frames during the decoding, displaying, and encoding processes.  
       SUMMARY  
       [0007]     In general, in one aspect, an apparatus includes a video decoder to generate decompressed frames from first compressed video frames and write the decompressed frames to a memory, at least one of the decompressed frames being generated using information from a previously generated decompressed frame, and a video encoder to generate second compressed video frames from the decompressed frames without duplicating the decompressed frames.  
         [0008]     Implementations may include one or more of the following features. The apparatus includes a display controller to control display of the decompressed frames without duplicating the decompressed frames. The apparatus includes a system controller to control the video decoder, the video encoder, and display controller to generate and display the second compressed video frames before the decompressed frames stored in the memory are overwritten by subsequent decompressed frames. The video encoder generates reconstructed frames that correspond to frames decompressed from the second compressed video, the video encoder storing the reconstructed frames in the memory. The apparatus includes a display controller to cause display of the reconstructed frames without duplicating the reconstructed frames. The apparatus includes a system controller to control the video decoder and the video encoder to generate the second compressed video frames before the decompressed frames stored in the memory are overwritten by subsequent decompressed frames. The decompressed frames include intra-frames (I-frames), forward predicted frames (P-frames), and bi-directional predicted frames (B-frames). When the decompressed frames are arranged in a display sequence, the decompressed frames include at least two consecutive B-frames. The video decoder and video encoder share the memory such that the memory at any given time stores no more than four decompressed frames written by the video decoder and two reconstructed frames written by the video encoder. In some examples, the video decoder and the video encoder share the memory such that the memory at any given time stores no more than six decompressed frames. In some examples, the video decoder and the video encoder share the memory such that the memory at any given time stores at most seven decompressed frames. The first compressed video and the second compressed video have different bit rates. The first compressed video and the second compressed video have different resolutions. The apparatus includes a descaler to generate lower resolution frames from higher resolution frames. The first compressed video includes a serial bit stream.  
         [0009]     In general, in another aspect, a video processing system includes a memory, a video decoder, a video encoder, a display controller, and a system controller. The video decoder generates decompressed frames that include intra-frames (I-frames), forward predicted frames (P-frames), and bi-directional predicted frames (B-frames) from first compressed video, the video decoder writing the decompressed frames to the memory, at least some of the decompressed frames being generated using information from previously decompressed frames. The video encoder generates second compressed video frames from the decompressed frames without duplicating the decompressed frames, the second compressed video frames having a different bit rate and/or different resolution as compared to the first compressed video frames. The display controller outputs a representation of the first compressed video frames to a display device without duplicating the frames stored in the memory. The system controller controls the video decoder, the video encoder, and the display controller.  
         [0010]     In general, in another aspect, an apparatus includes a decoding means for generating decoded frames from first encoded video frames using information from previously decoded frames, the decoding means writing the decoded frames to a memory, and an encoding means for generating second encoded video frames from the decoded frames without duplicating the decoded frames.  
         [0011]     Implementations may include one or more of the following features. The apparatus includes a display means for displaying representation of the decoded frames without duplicating frames stored in the memory. The decoded frames include intra-frames (I-frames), forward predicted frames (P-frames), and bidirectional predicted frames (B-frames).  
         [0012]     In general, in another aspect, an apparatus includes a video decoder to generate decompressed frames from first compressed video frames and write the decompressed frames to a memory, the first compressed video includes a sequence of compressed frames that are arranged according to a display sequence, and a video encoder to generate second compressed video frames from the decompressed frames without duplicating the decompressed frames.  
         [0013]     Implementations may include one or more of the following features. The apparatus includes a display controller to cause display of a representation of the decompressed frames without duplicating the decompressed frames. The decompressed frames include intra-frames (I-frames), forward predicted frames (P-frames), and bi-directional predicted frames (B-frames).  
         [0014]     In general, in another aspect, a method includes generating decompressed frames of a first compressed video using information from previously decompressed frames, writing the decompressed frames to a memory, and generating a second compressed video using the decompressed frames stored in the memory without duplicating the decompressed frames.  
         [0015]     Implementations may include one or more of the following features. The method includes controlling the generating of the decompressed frames and the generating of the second compressed video so that the decompressed frames are compressed before being overwritten by subsequent decompressed frames. The method includes displaying the decompressed frames without duplicating the decompressed frames. The method includes controlling the generating of the decompressed frames, the generating of the second compressed video, and the displaying so that the decompressed frames are compressed and displayed before being overwritten by subsequent decompressed frames. Generating the decompressed frames includes generating intra-frames (I-frames), forward predicted frames (P-frames), and bi-directional predicted frames (B-frames). When the decompressed frames are arranged in a display sequence, the sequence includes two consecutive B-frames. The writing and the encoding includes storing at most  6  decompressed frames in the memory. The writing and the encoding includes storing at most seven decompressed frames in the memory.  
         [0016]     In general, in another aspect, a method includes generating decompressed frames from a first compressed video includes a sequence of compressed frames that are arranged according to a display sequence, writing the decompressed frames to a memory, and generating a second compressed video from the decompressed frames without duplicating the decompressed frames.  
         [0017]     In general, in another aspect, a method includes decoding a first compressed video to generate decompressed frames, writing the decompressed frames to a memory, encoding the decompressed frames to generate a second compressed video, including generating reconstructed frames for use as references for encoding some of the decompressed frames, and writing the reconstructed frames in the memory, at least some of the reconstructed frames overwriting some of the decompressed frames.  
         [0018]     Implementations may include one or more of the following features. The second compressed video has a data rate that is different from the data rate of the first compressed video. The second compressed video has a resolution that is different from the resolution of the first compressed video. The method includes displaying the reconstructed frames without duplicating the reconstructed frames. The decoding includes decoding according to an MPEG standard.  
         [0019]     Among the advantages are one or more of the following: A smaller memory can be used for transcoding and displaying. As an example, video on a standard DVD (Digital Versatile Disc, which has a resolution of 720×480) may have a bit rate of about 150 kbits to 300 kbits per frame and video on a standard VCD (Video CD) may have a bit rate of about 30 kbits to 150 kbits per frame. When transcoding video on a DVD to video for a VCD, decompressed frames having a bit rate of about 4153.3 kbits per frame are temporarily stored in the memory. Using the techniques described here, the memory does not need to store more than six (or seven, depending on the application) decompressed frames at the same time. When processing an HDTV program having 1920×1080 resolution, using 12 bits to represent each pixel, each decompressed frame has about 24.9 Mbits. Thus, reducing the number of frames that need to be simultaneously stored in the memory during the decoding, encoding, and displaying processes can result in significant reduction in memory usage and cost. 
     
    
     DESCRIPTION OF DRAWINGS  
       [0020]      FIG. 1  is a schematic block diagram of a video controller.  
         [0021]      FIGS. 2A, 3A ,  4 A, and  5 A are diagrams of input/output signals.  
         [0022]      FIG. 2B  is a block diagram of a memory device.  
         [0023]      FIGS. 2C, 3B ,  4 B, and  5 B are timing charts.  
     
    
     DESCRIPTION  
       [0024]     Referring to  FIG. 1 , a video controller  10  includes a video codec  8 , a display controller  18 , and a memory device  22 . The video codec  8  includes a video decoder  12  and a video encoder  14 . The video controller  10  receives an input encoded video  26  and generates an output encoded video  30 . The videos  26  and  30  can be sent as, for example, serial bit streams. The input and output encoded videos  26  and  30  may have frames that are encoded differently, such as according to different compression algorithms having different compression ratios or different resolutions. The display controller  18  generates a video signal  27  for a display  28 . Each of the videos  26  and  30  includes a sequence of frames. During decoding, encoding, and displaying of the frames, certain frames are temporarily stored in the memory device  22 . The video decoder  12 , video encoder  14 , and the display controller  18  share the memory device  22  so that the number of frames that need to be simultaneously stored in the memory device  22  is fewer than for other systems. Thus, a smaller memory device  22  suffices.  
         [0025]     The video decoder  12 , video encoder  14 , and display controller  18  process the frames in a particular sequence such that the frames do not need to be duplicated or moved from one memory location to another during decoding, encoding, and displaying, thereby reducing the number of frames that need to be simultaneously stored in the memory. The particular processing sequence takes into account the format of the input encoded video  26  (e.g., whether the frames in the video  26  are in a display order or an encode order), the dependencies among the frames (e.g., B and P frames may depend on previous P and I frames), whether the frames are displayed at the same time that the frames are being encoded, and the type of frames to be displayed (e.g., decompressed or reconstructed frames).  
         [0026]     The video controller  10  also includes an audio encoder/decoder  16  that decodes and encodes audio signals, a memory controller  20  to control access to the memory device  22 , and a system controller  24  that coordinates operations of the video decoder  12 , video encoder  14 , audio encoder/decoder  16 , display controller  18 , and the memory controller  20 . The video controller  10  can be fabricated on a single integrated circuit or may include several integrated circuits and discrete components.  
         [0027]     The following describes six examples of using the video controller  10  to transcode (or encode) and display videos.  
       EXAMPLE 1  
       [0028]     Referring to  FIG. 2A , in example 1, the input encoded video  26  is a higher bit-rate compressed video, and the output encoded video  30  is a lower bit-rate compressed video. The encoded videos  26  and  30  have the same resolution. Both videos  26  and  30  have frames that are arranged in an encode order. The display controller  18  sends higher bit-rate decompressed frames arranged in the display order to the display  28 . The video controller  10  outputs a lower bit-rate compressed video  30  (e.g., for storage) at the same time that the display  28  shows a higher bit-rate decompressed video. The frames of the videos  26  and  30  can be encoded, for example, according to an MPEG standard.  
         [0029]     In this description, a “higher bit-rate compressed video” has a higher bit rate relative to a “lower bit-rate compressed video,” and a “higher bit-rate decompressed video” has a higher bit rate relative to a “lower bit-rate decompressed video.” The “higher bit-rate compressed video,” due to compression, can have a bit rate that is lower than the “lower bit-rate decompressed video.” The resolution of a compressed video refers to the resolution of the decompressed frames. A “higher resolution compressed video” can be decompressed to generate decompressed frames that have a higher resolution relative to decompressed frames derived from a “lower resolution compressed video.” 
         [0030]      FIG. 2B  shows memory buffers that are allocated in the memory device  22  for storing frames that are generated during the decoding, encoding, and displaying processes. The memory device  22  includes an input buffer  100 , a reconstructed encode reference  1  buffer  102 , a reconstructed encode reference  2  buffer  104 , an encode stage  1  buffer  106 , an encode stage  2  buffer  108 , an encode stage  3  buffer  110 , an encode stage  4  buffer  112 , an encode stage  5  buffer  114 , and an output buffer  116 .  
         [0031]     The input buffer  100  stores a higher bit-rate compressed frame, and the output buffer  116  stores a lower bit-rate compressed frame (e.g., for delivery to a storage device). The encode stage  1  buffer  106 , encode stage  2  buffer  108 , encode stage  3  buffer  110 , encode stage  4  buffer  112 , and encode stage  5  buffer  114  store higher bit-rate decompressed frames that are output from the video decoder  12 . The reconstructed encode reference  1  buffer  102  and the reconstructed encode reference  2  buffer  104  store lower bit-rate reconstructed frames that are generated by the video encoder  14 , and are used by the video encoder  14  during encoding of other frames. The video encoder may generate the lower bit rate decompressed frames by, for example, increasing a quantization level (truncating more bits) during encoding of the frames.  
         [0032]     The lower bit-rate reconstructed frames in buffers  102 ,  104  are decompressed frames. In this example, the reconstructed frames have the same resolution as the higher bit-rate decompressed frames.  
         [0033]      FIG. 2C  shows a time chart  140  indicating timing sequences in which the frames are stored in the buffers of the memory device  22  and shown on the display  28 . The frames are displayed in the order: I 0 , B 1 , B 2 , P 3 , B 4 , B 5 , P 6 , B 7 , B 8 , P 9 , B 10 , B 11 , P 12 , and so forth. Rows  120 ,  122 ,  124 ,  126 ,  128 ,  130 , to  132  indicate the contents of the buffers  102 ,  104 ,  106 ,  108 ,  110 ,  112 , and  114 , respectively. Row  134  indicates the time intervals at which the frames are encoded. Row  136  indicates the time intervals at which the frames are fetched by the display controller  18  and shown on the display  28 .  
         [0034]     In this example, the encode stage  5  buffer  114  is not used. The memory device  22  has a large enough capacity to accommodate the encode stage  5  buffer  114  for use in other examples (e.g., examples 5 and 6 described below).  
         [0035]     Each column (e.g.,  138 ) in the time chart  140  indicates the contents of the buffers, the frame that is encoded by the video encoder  14 , and the frame that is shown on the display  28  during a particular time interval T. As can be seen from the time chart  140 , each frame is accessed by only one of the video decoder  12 , the video encoder  14 , and the display controller  18  at any given time interval, so the video decoder  12 , the video encoder  14 , and the display controller  18  can share the frames stored in the memory buffers without conflict. Each frame in the memory device  22  is stored once without duplication.  
         [0036]     The following describes the processes performed by the video decoder  12 , the video encoder  14 , and the display controller  18  at various time intervals. Each time interval, such as T 0 , T 1 , T 2 , . . . , represents a frame period, which can be about 33.3 ms when the video is configured to have 30 frames per second.  
         [0037]     Before time interval TO (not shown in  FIG. 2C ), a higher bit-rate compressed I 0  frame is written to the input buffer  100 . Similarly, during time intervals T 0 , T 1 , T 2 , T 3 , T 4 , T 5 , T 6 , T 7 , T 8 , T 9 , T 10 , T 11 , T 12 , . . . , higher bit-rate compressed frames P 3 , B 1 , B 2 , P 6 , B 4 , B 5 , P 9 , B 7 , B 8 , P 12 , B 10 , B 11 , . . . , respectively, are written to the input buffer  100 .  
         [0038]     During time interval T 0 , the video decoder  12  retrieves the compressed I 0  frame from the input buffer  100 , decodes the compressed I 0  frame to generate a higher bit-rate decompressed frame I 0 , and writes the decompressed I 0  frame to the encode stage  1  buffer  106 .  
         [0039]     During time interval T 1 , the video decoder  12  retrieves the compressed P 3  frame from the input buffer  100 , decodes the compressed P 3  frame and generates a decompressed P 3  frame, and writes the decompressed P 3  frame to the encode stage  2  buffer  108 . The video encoder  14  retrieves the higher bit-rate decompressed I 0  frame from the buffer  106 , encodes the I 0  frame to generate a lower bit-rate reconstructed I 0 ′ frame and a lower bit-rate compressed I 0 ′ frame, writes the reconstructed I 0 ′ frame to the reconstructed reference  1  buffer  102 , and writes the compressed I 0 ′ frame to the output buffer  116 .  
         [0040]     During time interval T 2 , the video decoder  12  decodes the higher bit-rate compressed B 1  frame to generate a higher bit-rate decompressed B 1  frame, and writes the decompressed B 1  frame to the encode stage  3  buffer  110 . The video encoder  14  retrieves the decompressed P 3  frame from the buffer  108 , encodes the decompressed P 3  frame to generate a lower bit-rate reconstructed P 3 ′ frame and a lower resolution compressed P 3 ′ frame, writes the reconstructed P 3 ′ frame to the reconstructed reference  2  buffer  104 , and writes the compressed P 3 ′ frame to the output buffer  116 . The display controller  18  retrieves the higher bit-rate decompressed I 0  frame from the buffer  106  and causes the I 0  frame to be shown on the display  28 .  
         [0041]     During time interval T 3 , the video decoder  12  decodes the higher bit-rate compressed B 2  frame to generate a higher bit-rate decompressed B 2  frame, and writes the decompressed B 2  frame to the encode stage  4  buffer  112 . The video encoder  14  retrieves the decompressed B 1  frame from the buffer  110 , encodes the decompressed B 1  frame to generate a lower bit-rate compressed B 1 ′ frame, and writes the compressed B 1 ′ frame to the output buffer  116 . The display controller  18  retrieves the higher bit-rate decompressed B 1  frame from the buffer  110  and causes the BI frame to be shown on the display  28 .  
         [0042]     During time interval T 4 , the video decoder  12  decodes the higher bit-rate compressed P 6  frame to generate a higher bit-rate decompressed P 6  frame, and writes the decompressed P 6  frame to the encode stage  1  buffer  106 . The video encoder  14  retrieves the decompressed B 2  frame from the buffer  112 , encodes the decompressed B 2  frame to generate a lower bit-rate compressed B 2 ′ frame, and writes the compressed B 2 ′ frame to the output buffer  116 . The display controller  18  retrieves the higher bit-rate decompressed B 2  frame from the buffer  112  and causes the B 2  frame to be shown on the display  28 .  
         [0043]     During time interval T 5 , the video decoder  12  decodes a higher bit-rate compressed B 4  frame to generate a higher bit-rate decompressed B 4  frame, and writes the decompressed B 4  frame to the encode stage  3  buffer  110 . The video encoder  14  retrieves the decompressed P 6  frame from the buffer  106 , encodes the decompressed P 6  frame to generate a lower bit-rate reconstructed P 6 ′ frame and a lower bit-rate compressed P 6 ′ frame, writes the reconstructed P 6 ′ frame to the buffer  102 , and writes compressed P 6 ′ frame to the output buffer  116 . The display controller  18  retrieves the higher bit-rate decompressed P 3  frame from the buffer  108  and causes the P 3  frame to be shown on the display  28 .  
         [0044]     During time interval T 6 , the video decoder  12  decodes the higher bit-rate compressed B 5  frame to generate a higher bit-rate decompressed B 5  frame, and writes the decompressed B 5  frame to the encode stage  4  buffer  112 . The video encoder  14  retrieves the decompressed B 4  frame from the buffer  110 , encodes the decompressed B 4  frame to generate a lower bit-rate compressed B 4 ′ frame, and writes the compressed B 4 ′ frame to the output buffer  116 . The display controller  18  retrieves the higher bit-rate decompressed B 4  frame from the buffer  110  and causes the B 4  frame to be shown on the display  28 .  
         [0045]     During time interval T 7 , the video decoder  12  decodes the higher bit-rate compressed P 9  frame to generate a higher bit-rate decompressed P 9  frame, and writes the decompressed P 9  frame to the encode stage  2  buffer  108 . The video encoder  14  retrieves the decompressed B 5  frame from the buffer  112 , encodes the decompressed B 5  frame to generate a lower bit-rate compressed B 5 ′ frame, and writes the compressed B 5 ′ frame to the output buffer  116 . The display controller  18  retrieves the higher bit-rate decompressed B 5  frame from the buffer  112  and causes the B 5  frame to be shown on the display  28 .  
         [0046]     During time intervals T 8 , T 9 , T 10 , and so forth, the video controller  10  operates in a manner similar to those described above.  
         [0047]     The operation of the video decoder  12 , the video encoder  14 , and the display controller  18  is designed such that a first frame is overwritten by a second frame only after the first frame will no longer be used by the video decoder  12 , the video encoder  14 , or the display controller  18 . For example, during and after the time interval T 4 , the I 0  frame is not used by the video decoder  12 , the video encoder  14 , or the display controller  18 , so the I 0  frame in the encode stage  1  buffer  106  can be overwritten by the P 6  frame during T 4 . Similarly, during and after the time interval T 7 , the P 3  frame in the encode stage  2  buffer  108  is not used by the video decoder  12 , the video encoder  14 , or the display controller  18 , so the P 3  frame can be overwritten by the P 9  frame during T 7 .  
         [0048]     Because the B-frames are not referenced by any other frame, it is not necessary to store lower bit-rate reconstructed B′-frames in the memory device  22 .  
         [0049]     In example 1, the video decoder  12 , the video encoder  14 , and the display controller  18  share the memory  22  such that the memory  22  at any given time stores no more than four decompressed frames (in buffers  106 ,  108 ,  110 , and  112 ) written by the video decoder  12  and two reconstructed frames (in buffers  102  and  104 ) written by the video encoder  14 . Because the reconstructed frames are decompressed frames, the memory  22  at any given time stores no more than six decompressed frames.  
         [0050]     The operations of the video decoder  12 , the video encoder  14 , and the display controller  18  are coordinated by the system controller  24 . For example, the system controller  24  may adjust pointers used by the video decoder  12 , the video encoder  14 , and the display controller  18  to control which memory buffer is accessed by the video decoder  12 , the video encoder  14 , and the display controller  18 .  
       EXAMPLE 2  
       [0051]     In example 2, the lower bit-rate compressed video  30  has a lower resolution as compared to the higher bit-rate compressed video  26 . The compressed videos  26  and  30  may have the same or different compression ratios (e.g., quantization levels). For example, the input encoded video  26  can have 1920×1080 resolution, and the output encoded video  30  can have 1366×768 resolution. Both the encoded videos  26  and  30  have frames that are arranged in an encode order. The display controller  18  sends higher resolution frames arranged in the display order to the display  28 . Thus, the video controller  10  outputs a lower bit-rate compressed video  30  having a lower resolution at the same time that the display  28  shows the video in a higher resolution.  
         [0052]     The allocation of memory buffers in the memory device  22  for example 2 is similar to that of example 1, as shown in  FIG. 2B . The input buffer  100  stores a higher resolution compressed frame, and the output buffer  116  stores a lower resolution compressed frame generated by the video encoder  14 . The encode stage  1  buffer  106 , encode stage  2  buffer  108 , encode stage  3  buffer  110 , encode stage  4  buffer  112 , and encode stage  5  buffer  114  store higher resolution decompressed frames that are output from the video decoder  12 . The reconstructed encode reference  1  buffer  102  and the reconstructed encode reference  2  buffer  104  store lower resolution reconstructed frames that are used by the video encoder  14  during the encoding process to generate the lower resolution compressed frames. A descaler can generate the lower resolution reconstructed frames by using a descaling process. The descaler can be part of the video decoder  12  or the video encoder  14 . The descaler can also be a component independent of the video decoder  12  and the video encoder  14 . The encoding and the descaling of the frames can be performed at the same time.  
         [0053]     Timing sequences for example 2 is similar to that of example 1, as shown in  FIG. 2C . The processes performed by the video decoder  12 , the video encoder  14 , and the display controller  18  are similar to those described in example 1, except that the frames I 0 ′, B 1 ′, B 2 ′, P 3 ′, B 4 ′, B 5 ′, P 6 ′, B 7 ′, B 8 ′, P 9 ′, B 10 ′, B 11 ′, and P 12 ′ are lower resolution reconstructed frames, and I 0 , B 1 , B 2 , P 3 , B 4 , B 5 , P 6 , B 7 , B 8 , P 9 , B 10 , B 11 , and P 12  are higher resolution decompressed frames.  
         [0054]     Similar to example 1, in example 2, the video decoder  12 , the video encoder  14 , and the display controller share the memory  22  such that the memory  22  at any given time stores no more than six decompressed frames, including four decompressed frames written by the video decoder  12  and two reconstructed frames written by the video encoder  14 .  
       EXAMPLE 3  
       [0055]     Referring to  FIG. 3A , in example 3, similar to example 1, the input encoded video  26  is a higher bit-rate compressed video, and the output encoded video  30  is a lower bit-rate compressed video. The encoded videos  26  and  30  have the same resolution but different bit rates. Both the encoded videos  26  and  30  have frames that are arranged in an encode order. The frames of the videos  26  and  30  can be encoded, for example, according to an MPEG standard.  
         [0056]     In example 3, the display controller  18  sends lower bit-rate frames arranged in the display order to the display  28 . The video controller  10  outputs a lower bit-rate compressed video  30  at the same time that the display  28  shows a lower bit-rate decompressed video.  
         [0057]      FIG. 3B  shows a time chart  150  indicating timing sequences in which the frames are stored in the buffers of the memory device  22  and shown on the display  28 . In this example, the encode stage  5  buffer  114  is not used.  
         [0058]     As can be seen from the time chart  150 , each frame is accessed by only one of the video decoder  12 , the video encoder  14 , and the display controller  18  at any given time interval, so that the video decoder  12 , the video encoder  14 , and the display controller  18  can share the frames stored in the memory buffers without conflict. Each frame in the memory device  22  is stored once without duplication.  
         [0059]     The following describes the processes performed by the video decoder  12 , the video encoder  14 , and the display controller  18  at various time intervals.  
         [0060]     Before time interval T 0  (not shown in  FIG. 3B ), a higher bit-rate compressed I 0  frame is written to the input buffer  100 . Similarly, during time intervals T 0 , T 1 , T 2 , T 3 , T 4 , T 5 , T 6 , T 7 , T 8 , T 9 , T 10 , T 11 , T 12 , . . . , higher bit-rate compressed frames P 3 , B 1 , B 2 , P 6 , B 4 , B 5 , P 9 , B 7 , B 8 , P 12 , B 10 , B 11 , . . . , respectively, are written to the input buffer  100 .  
         [0061]     During time intervals T 0  and T 1 , the video decoder  12  and the video encoder  14  operate in a manner similar to those in example 1, as shown in  FIG. 2C .  
         [0062]     During time interval T 2 , the video decoder  12  and the video encoder  14  operate in a manner similar to those in example 1, as shown in  FIG. 2C . However, the display controller  18  does not cause any frame to be shown on the display  28  during T 2 .  
         [0063]     During time interval T 3 , the video decoder  12  decodes the higher bit-rate compressed B 2  frame to generate a higher bit-rate decompressed B 2  frame, and writes the decompressed B 2  frame to the encode stage  4  buffer  112 . The video encoder  14  retrieves the decompressed B 1  frame from the buffer  110 , encodes the decompressed B 1  frame to generate a lower bit-rate reconstructed B 1 ′ frame and a lower bit-rate compressed B 1 ′ frame, writes the reconstructed B 1 ′ frame to the buffer  110 , and writes the compressed B 1 ′ frame to the output buffer  116 . The display controller  18  retrieves the lower bit-rate reconstructed I 0 ′ frame from the buffer  102  and causes the I 0 ′ frame to be shown on the display  28 .  
         [0064]     The higher bit-rate decompressed frame B 1  and the lower bit-rate reconstructed frame B 1 ′ have the same resolution (i.e., the same number of columns and rows), so the decompressed frame B 1  and the reconstructed frame B 1 ′ have the same size (i.e., have the same number of bits). The decompressed frame B 1  and the reconstructed frame B 1 ′ may have different image qualities. For example, the reconstructed B 1 ′ frame may not be as sharp as the decompressed B 1  frame, and block artifacts in the reconstructed B 1 ′ frame may be more visible than in the decompressed B 1  frame.  
         [0065]     During time interval T 4 , the video decoder  12  decodes the higher bit-rate compressed P 6  frame to generate a higher bit-rate decompressed P 6  frame, and writes the decompressed P 6  frame to the buffer  106 . The video encoder  14  retrieves the decompressed B 2  frame from the buffer  112 , encodes the decompressed B 2  frame to generate a lower bit-rate reconstructed B 2 ′ frame and a lower bit-rate compressed B 2 ′ frame, writes the reconstructed B 2 ′ frame to the buffer  112 , and writes the compressed B 2 ′ frame to the output buffer  116 . The display controller  18  retrieves the lower bit-rate reconstructed B 1 ′ frame from the buffer  110  and causes the B 1 ′ frame to be shown on the display  28 .  
         [0066]     During time interval T 5 , the video decoder  12  decodes a higher bit-rate compressed B 4  frame to generate a higher bit-rate decompressed B 4  frame, and writes the decompressed B 4  frame to the encode stage  3  buffer  110 . The video encoder  14  retrieves the decompressed P 6  frame from the buffer  106 , encodes the decompressed P 6  frame to generate a lower bit-rate reconstructed P 6 ′ frame and a lower bit-rate compressed P 6 ′ frame, writes the reconstructed P 6 ′ frame to the buffer  102 , and writes compressed P 6 ′ frame to the output buffer  116 . The display controller  18  retrieves the lower bit-rate reconstructed B 2 ′ frame from the buffer  112  and causes the B 2 ′ frame to be shown on the display  28 .  
         [0067]     During time interval T 6 , the video decoder  12  decodes the higher bit-rate compressed B 5  frame to generate a higher bit-rate decompressed B 5  frame, and writes the decompressed B 5  frame to the encode stage  4  buffer  112 . The video encoder  14  retrieves the decompressed B 4  frame from the buffer  110 , encodes the decompressed B 4  frame to generate a lower bit-rate reconstructed B 4 ′ frame and a lower bit-rate compressed B 4 ′ frame, writes the reconstructed B 4 ′ frame to the buffer  110 , and writes the compressed B 4 ′ frame to the output buffer  116 . The display controller  18  retrieves the lower bit-rate reconstructed B 3 ′ frame from the buffer  110  and causes the B 3 ′ frame to be shown on the display  28 .  
         [0068]     During time interval T 7 , the video decoder  12  decodes the higher bit-rate compressed P 9  frame to generate a higher bit-rate decompressed P 9  frame, and writes the decompressed P 9  frame to the buffer  108 . The video encoder  14  retrieves the decompressed B 5  frame from the buffer  112 , encodes the decompressed B 5  frame to generate a lower bit-rate reconstructed B 5 ′ frame and a lower bit-rate compressed B 5 ′ frame, writes the reconstructed B 5 ′ frame to the buffer  112 , and writes the compressed B 5 ′ frame to the output buffer  116 . The display controller  18  retrieves the lower bit-rate reconstructed B 4 ′ frame from the buffer  110  and causes the B 4 ′ frame to be shown on the display  28 .  
         [0069]     During time intervals T 8 , T 9 , T 10 , and so forth, the video controller  10  operates in a manner similar to those described above.  
         [0070]     In example 3, similar to example 1, the operations of the video decoder  12 , video encoder  14 , and display controller  18  are designed such that a first frame is overwritten by a second frame only after the first frame will not be used by the video decoder  12 , the video encoder  14 , or the display controller  18 . The video decoder  12 , the video encoder  14 , and the display controller  18  share the memory  22  such that the memory  22  at any given time stores no more than six decompressed frames in buffers  102 ,  104 ,  106 ,  108 ,  110 , and  112 .  
       EXAMPLE 4  
       [0071]     In example 4, the lower bit-rate compressed video  30  has a lower resolution as compared to the higher bit-rate compressed video  26 . The compressed videos  26  and  30  may have the same or different compression ratios (e.g., quantization levels). For example, the input encoded video  26  can have 1920×1080 resolution, and the output encoded video  30  can have 1366×768 resolution. Both the encoded videos  26  and  30  have frames that are arranged in an encode order. The display controller  18  sends lower resolution frames arranged in the display order to the display  28 . Thus, the video controller  10  outputs a lower bit-rate compressed video  30  having a lower resolution at the same time that the display  28  shows the video in a lower resolution.  
         [0072]     The allocation of memory buffers in the memory device  22  for example 4 is similar to that of example 2, as shown in  FIG. 3B . The input buffer  100  stores a higher resolution compressed frame, and the output buffer  116  stores a lower resolution compressed frame generated by the video encoder  14 . A descaler may generate the lower resolution decompressed frames by using a de-scaling process. The encoding and the de-scaling of the frames may be performed at the same time.  
         [0073]     Timing sequences for example 4 is similar to those of example 3, as shown in  FIG. 3B . The processes performed by the video decoder  12 , the video encoder  14 , and the display controller  18  are similar to those described in example 3, except that the frames I 0 ′, B 1 ′, B 2 ′, P 3 ′, B 4 ′, B 5 ′, P 6 ′, B 7 ′, B 8 ′, P 9 ′, B 10 ′, B 11 ′, and P 12 ′ are lower resolution reconstructed frames, and I 0 , B 1 , B 2 , P 3 , B 4 , B 5 , P 6 , B 7 , B 8 , P 9 , B 10 , B 11 , and P 12  are higher resolution decompressed frames.  
         [0074]     Similar to example 3, in example 4, the video decoder  12 , the video encoder  14 , and the display controller  18  share the memory  22  such that the memory  22  at any given time stores no more than six decompressed frames in buffers  102 ,  104 ,  106 ,  108 ,  110 , and  112 .  
       EXAMPLE 5  
       [0075]     Referring to  FIG. 4A , in example 5, the input encoded video  26  is a compressed higher bit-rate video from a video source, such as a high definition video camcorder. The frames in the input video  26  are arranged in the display order and are compressed according to, e.g., digital video (DV) or JPEG format, which specifies that the compressed frames are all intra frames. The output encoded video  30  is a compressed lower bit-rate video in which the frames are arranged in the encode order. The frames of the output video  30  are encoded according to, e.g., an MPEG standard. The input video  26  includes I frames arranged in the display order, and the output video  30  includes I, B, and P frames arranged in the encode order. The videos  26  and  30  have the same resolution but different bit rates. The display controller  18  sends higher bit-rate frames to the display  28  in the display order.  
         [0076]      FIG. 4B  shows a time chart  160  indicating timing sequences in which the frames are stored in the buffers of the memory device  22  and shown on the display  28 . In this example, the encode stage  5  buffer  114  is used (as compared to examples 1-4 in which the buffer  114  is not used).  
         [0077]     As can be seen from the time chart  160 , each frame is accessed by only one of the video decoder  12 , the video encoder  14 , and the display controller  18  at any given time interval, so that the video decoder  12 , the video encoder  14 , and the display controller  18  can share the frames stored in the memory buffers without conflict. Each frame that is stored in the memory device  22  is stored once without duplication.  
         [0078]     The following describes the processes performed by the video decoder  12 , the video encoder  14 , and display controller  18  at various time intervals.  
         [0079]     Before time interval T 0  (not shown in  FIG. 4B ), a higher bit-rate encoded I 0  frame is written to the input buffer  100 . Similarly, during time intervals T 0 , T 1 , T 2 , T 3 , T 4 , T 5 , T 6 , T 7 , T 8 , T 9 , T 10 , T 11 , T 12 , . . . , higher bit-rate encoded frames I 1 , I 2 , I 3 , I 4 , I 5 , I 6 , I 7 , I 8 , I 9 , I 10 , I 11 , . . . , respectively, are written to the input buffer  100 .  
         [0080]     During time interval T 0 , the video decoder  12  decodes the encoded I 0  frame to generate a higher bit-rate decompressed I 0  frame, and writes the decompressed I 0  frame to the encode stage  1  buffer  106 .  
         [0081]     During time interval T 1 , the video decoder  12  decodes the encoded I 1  frame and generates a higher bit-rate decompressed I 1  frame, and writes the decompressed I 1  frame to the encode stage  3  buffer  110 .  
         [0082]     During time interval T 2 , the video decoder  12  decodes the encoded I 2  frame to generate a higher bit-rate decompressed I 2  frame, and writes the decompressed I 2  frame to the encode stage  4  buffer  112 . The video encoder  14  encodes the higher bit-rate decompressed I 0  frame to generate a lower bit-rate reconstructed I 0 ′ frame and a lower bit-rate compressed I 0 ′ frame, writes the reconstructed I 0 ′ frame to the reconstructed reference  1  buffer  102 , and writes the compressed I 0 ′ frame to the output buffer  116 .  
         [0083]     During time interval T 3 , the video decoder  12  decodes the encoded I 3  frame to generate a higher bit-rate decompressed I 3  frame, and writes the decompressed I 3  frame to the encode stage  2  buffer  108 . The video encoder  14  encodes the higher bit-rate decompressed I 3  frame to generate a lower bit-rate reconstructed P 3 ′ frame and a lower bit-rate compressed P 3 ′ frame, writes the reconstructed P 3 ′ frame to the buffer  104 , and writes the compressed P 3 ′ frame to the output buffer  116 . The display controller  18  retrieves the higher bit-rate decompressed I 0  frame from the buffer  106  and causes the I 0  frame to be shown on the display  28 .  
         [0084]     During time interval T 4 , the video decoder  12  decodes the encoded I 4  frame to generate a higher bit-rate decompressed I 4  frame, and writes the decompressed I 4  frame to the encode stage  5  buffer  114 . The video encoder  14  encodes the higher bit-rate decompressed I 1  frame to generate a lower bit-rate compressed B 1 ′ frame, and writes the compressed B 1 ′ frame to the output buffer  116 . The display controller  18  retrieves the higher bit-rate decompressed I 1  frame from the buffer  110  and causes the I 1  frame to be shown on the display  28 .  
         [0085]     During time interval T 5 , the video decoder  12  decodes the encoded I 5  frame to generate a higher bit-rate decompressed I 5  frame, and writes the decompressed I 5  frame to the encode stage  3  buffer  110 . The video encoder  14  encodes the decompressed I 2  frame to generate a lower bit-rate compressed B 2 ′ frame, and writes the compressed B 2 ′ frame to the output buffer  116 . The display controller  18  retrieves the higher bit-rate decompressed I 2  frame from the buffer  112  and causes the I 2  frame to be shown on the display  28 .  
         [0086]     During time interval T 6 , the video decoder  12  decodes the encoded I 6  frame to generate a higher bit-rate decompressed I 6  frame, and writes the decompressed I 6  frame to the encode stage  1  buffer  106 . The video encoder  14  encodes the decompressed  16  frame to generate a lower bit-rate reconstructed P 6 ′ frame and a lower bit-rate compressed P 6 ′ frame, writes the reconstructed P 6 ′ frame to the buffer  102 , and writes the compressed P 6 ′ frame to the output buffer  116 . The display controller  18  retrieves the higher bit-rate decompressed I 3  frame from the buffer  108  and causes the I 3  frame to be shown on the display  28 .  
         [0087]     During time interval T 7 , the video decoder  12  decodes the encoded I 7  frame to generate a higher bit-rate decompressed I 7  frame, and writes the decompressed I 7  frame to the encode stage  4  buffer  112 . The video encoder  14  encodes the decompressed I 4  frame to generate a lower bit-rate compressed B 4 ′ frame, and writes the compressed B 4 ′ frame to the output buffer  116 . The display controller  18  retrieves the higher bit-rate decompressed I 4  frame from the buffer  114  and causes the I 4  frame to be shown on the display  28 .  
         [0088]     During time intervals T 8 , T 9 , T 10 , and so forth, the video controller  10  operates in a manner similar to those described above.  
         [0089]     In example 5, the operations of the video decoder  12 , the video encoder  14 , and the display controller  18  are designed such that a first frame is overwritten by a second frame only after the first frame will not be used by the video decoder  12 , the video encoder  14 , or the display controller  18 . The video decoder  12 , the video encoder  14 , and the display controller  18  share the memory  22  such that the memory  22  at any given time stores no more than seven decompressed frames, including five decompressed frames (in buffers  106 ,  108 ,  110 ,  112 , and  114 ) written by the video decoder  12  and two reconstructed frames (in buffers  102  and  104 ) written by the video encoder  14 .  
       EXAMPLE 6  
       [0090]     In example 6, the lower bit-rate compressed video  30  has a lower resolution as compared to the higher bit-rate compressed video  26 . For example, the input encoded video  26  can have 1920× 1080  resolution, and the output encoded video  30  can have 1366×768 resolution. The encoded video  26  has frames that are arranged in a display order, whereas the encoded video  26  has frames that are arranged in an encode order. The display controller  18  sends higher resolution frames arranged in the display order to the display  28 . Thus, the video controller  10  outputs a lower bit-rate compressed video  30  having lower resolution at the same time that the display  28  shows the video in higher resolution.  
         [0091]     The allocation of memory buffers in the memory device  22  for example 6 is similar to that of example 5, as shown in  FIG. 4B . The input buffer  100  stores a higher resolution compressed frame, and the output buffer  116  stores a lower resolution compressed frame generated by the video encoder  14 . The encode stage  1  buffer  106 , encode stage  2  buffer  108 , encode stage  3  buffer  110 , encode stage  4  buffer  112 , and encode stage  5  buffer  114  store higher resolution decompressed frames that are output from the video decoder  12 . The reconstructed encode reference  1  buffer  102  and the reconstructed encode reference  2  buffer  104  store lower resolution reconstructed frames that are generated by the video encoder  14 , and used by the video encoder  14  during encoding of other frames. A descaler may generate the lower resolution reconstructed frames by using a descaling process. The encoding and the descaling of the frames may be performed at the same time.  
         [0092]     Timing sequences for example 6 is similar to that of example 5, as shown in  FIG. 4B . The processes performed by the video decoder  12 , the video encoder  14 , and the display controller  18  are similar to those described in example 5, except that the frames I 0 ′, B 1 ′, B 2 ′, P 3 ′, B 4 ′, B 5 ′, P 6 ′, B 7 ′, B 8 ′, P 9 ′, B 10 ′, B 11 ′, and P 12 ′ are lower resolution reconstructed frames, and I 0 , B 1 , B 2 , P 3 , B 4 , B 5 , P 6 , B 7 , B 8 , P 9 , B 10 , B 11 , and P 12  are higher resolution decompressed frames.  
         [0093]     Similar to example 5, in example 6, the video decoder  12 , the video encoder  14 , and the display controller  18  share the memory  22  such that the memory  22  at any given time stores no more than seven decompressed frames, including five decompressed frames (in buffers  106 ,  108 ,  110 ,  112 , and  114 ) written by the video decoder  12  and two reconstructed frames (in buffers  102  and  104 ) written by the video encoder  14 .  
       EXAMPLE 7  
       [0094]     Referring to  FIG. 5A , in example 7, similar to example 5, the input encoded video  26  is a compressed higher bit-rate video from a video source in which the frames are all intra frames and arranged in the display order. The output encoded video  30  is a compressed lower bit-rate video in which the frames are arranged in the encode order. The frames of the output video  30  may be encoded according to, e.g., an MPEG standard. The videos  26  and  30  have the same resolution. The difference between examples 5 and 7 is that, in example 7, the display controller  18  sends a lower bit-rate decompressed video  27  to the display  28  in the display order.  
         [0095]      FIG. 5B  shows a time chart  170  indicating timing sequences in which the frames are stored in the buffers of the memory device  22  and shown on the display  28 . In example 7, the reconstructed reference  1  buffer and  102  and the reconstructed reference  2  buffer  104  are not used (as compared to examples 1-6 in which the buffers  102  and  104  were not used). This is because the input video are all intra frames, so when encoding a frame I 0 , a reconstructed frame I 0 ′ can overwrite the frame I 0  because I 0  is not used in the decoding of subsequent frames. Thus, the encode stage  1  buffer  106  can be used to store the decoded frame I 0  and the reconstructed frame I 0 ′. Each frame that is stored in the memory device  22  is stored once without duplication.  
         [0096]     The following describes the processes performed by the video decoder  12 , video encoder  14 , and the display controller  18  at various time intervals.  
         [0097]     Before time interval T 0  (not shown in  FIG. 5B ), a higher bit-rate encoded I 0  frame is written to the input buffer  100 . Similarly, during time intervals T 0 , T 1 , T 2 , T 3 , T 4 , T 5 , T 6 , T 7 , T 8 , T 9 , T 10 , T 11 , T 12 , . . . , higher bit-rate encoded frames I 1 , I 2 , I 3 , I 4 , I 5 , I 6 , I 7 , I 8 , I 9 , I 10 , I 11 , . . . , respectively, are written to the input buffer  100 .  
         [0098]     During time interval T 0 , the video decoder  12  decodes the encoded I 0  frame to generate a higher bit-rate decompressed I 0  frame, and writes the decompressed I 0  frame to the encode stage  1  buffer  106 .  
         [0099]     During time interval T 1 , the video decoder  12  decodes the encoded I 1  frame and generates a higher bit-rate decompressed I 1  frame, and writes the decompressed I 1  frame to the encode stage  3  buffer  110 .  
         [0100]     During time interval T 2 , the video decoder  12  decodes the encoded I 2  frame to generate a higher bit-rate decompressed I 2  frame, and writes the decompressed I 2  frame to the encode stage  4  buffer  112 . The video encoder  14  encodes the higher bit-rate decompressed I 0  frame to generate a lower bit-rate reconstructed I 0 ′ frame and a lower bit-rate compressed I 0 ′ frame, writes the reconstructed I 0 ′ frame to the encode stage  1  buffer  106  (thereby overwriting the decompressed I 0  frame), and writes the compressed I 0 ′ frame to the output buffer  116 .  
         [0101]     During time interval T 3 , the video decoder  12  decodes the encoded I 3  frame to generate a higher bit-rate decompressed I 3  frame, and writes the decompressed I 3  frame to the encode stage  2  buffer  108 . In some examples, the video encoder  14  starts to encode the data in the buffer  108  after the video decoder  12  decodes a certain amount of data, so that during period T 3 , the buffer  108  is accessed by both the video decoder  12  and the video encoder  14 . The video encoder  14  encodes the higher bit-rate decompressed  13  frame to generate a lower bit-rate reconstructed P 3 ′ frame and a lower bit-rate compressed P 3 ′ frame, writes the reconstructed P 3 ′ frame to the buffer  108  (thereby overwriting the decompressed I 3  frame), and writes the compressed P 3 ′ frame to the output buffer  116 . The display controller  18  retrieves the lower bit-rate reconstructed I 0 ′ frame from the buffer  106  and causes the I 0 ′ frame to be shown on the display  28 .  
         [0102]     During time interval T 4 , the video decoder  12  decodes the encoded I 4  frame to generate a higher bit-rate decompressed I 4  frame, and writes the decompressed I 4  frame to the encode stage  5  buffer  114 . The video encoder  14  encodes the higher bit-rate decompressed B 1  frame to generate a lower bit-rate reconstructed B 1 ′ frame and a lower bit-rate compressed B 1 ′ frame, writes the reconstructed B 1 ′ frame to the buffer  110 , and writes the compressed B 1 ′ frame to the output buffer  116 . The display controller  18  retrieves the lower bit-rate reconstructed B 1 ′ frame from the buffer  110  and causes the B 1 ′ frame to be shown on the display  28 .  
         [0103]     During time interval T 5 , the video decoder  12  decodes the encoded I 5  frame to generate a higher bit-rate decompressed I 5  frame, and writes the decompressed I 5  frame to the encode stage  3  buffer  110 . The reconstructed B 1 ′frame can be overwritten because it has already been displayed during T 4 , and will not be used in the future. The video encoder  14  encodes the decompressed B 2  frame to generate a lower bit-rate reconstructed B 2 ′ frame and a lower bit-rate compressed B 2 ′ frame, writes the reconstructed B 2 ′ frame to the buffer  112 , and writes the compressed B 2 ′ frame to the output buffer  116 . The display controller  18  retrieves the lower bit-rate reconstructed B 2 ′ frame from the buffer  112  and causes the B 2 ′ frame to be shown on the display  28 .  
         [0104]     During time interval T 6 , the video decoder  12  decodes the encoded I 6  frame to generate a higher bit-rate decompressed I 6  frame, and writes the decompressed I 6  frame to the encode stage  1  buffer  106 . The video encoder  14  encodes the decompressed I 6  frame to generate a lower bit-rate reconstructed P 6 ′ frame and a lower bit-rate compressed P 6 ′ frame, writes the reconstructed P 6 ′ frame to the buffer  106  (overwriting the decompressed I 6  frame), and writes the compressed P 6 ′ frame to the output buffer  116 . The display controller  18  retrieves the lower bit-rate decompressed P 3 ′ frame from the buffer  108  and causes the P 3 ′ frame to be shown on the display  28 .  
         [0105]     During time interval T 7 , the video decoder  12  decodes the encoded I 7  frame to generate a higher bit-rate decompressed I 7  frame, and writes the decompressed I 7  frame to the encode stage  4  buffer  112 . The video encoder  14  encodes the decompressed I 4  frame to generate a lower bit-rate reconstructed B 4 ′ frame and a lower bit-rate compressed B 4 ′ frame, writes the reconstructed B 4 ′ frame to the buffer  114 , and writes the compressed B 4 ′ frame to the output buffer  116 . The display controller  18  retrieves the lower bit-rate decompressed B 4 ′ frame from the buffer  114  and causes the B 4 ′ frame to be shown on the display  28 .  
         [0106]     During time intervals T 8 , T 9 , T 10 , and so forth, the video controller  10  operates in a manner similar to those described above.  
         [0107]     In example 7, the operations of the video decoder  12 , video encoder  14 , and display controller  18  are designed such that a first frame is overwritten by a second frame only after the first frame will not be used by the video decoder  12 , the video encoder  14 , or the display controller  18 . The video decoder  12 , the video encoder  14 , and the display controller  18  share the memory  22  such that the memory  22  at any given time stores no more than five decompressed frames in buffers  106 ,  108 ,  110 ,  112 , and  114 .  
       EXAMPLE 8  
       [0108]     In example 8, the lower bit-rate compressed video  30  has a lower resolution as compared to the higher bit-rate compressed video  26 . For example, the input encoded video  26  can have 1920×1080 resolution, and the output encoded video  30  can have 1366×768 resolution. The encoded video  26  has frames that are arranged in a display order, whereas the encoded video  26  has frames that are arranged in an encode order. The display controller  18  sends lower resolution frames arranged in the display order to the display  28 . Thus, the video controller  10  outputs a lower bit-rate compressed video  30  having lower resolution at the same time that the display  28  shows the video in a lower resolution.  
         [0109]     The allocation of memory buffers in the memory device  22  for example 8 is similar to that of example 7, as shown in  FIG. 5B . The input buffer  100  stores a higher resolution compressed frame, and the output buffer  116  stores a lower resolution compressed frame generated by the video encoder  14 . The encode stage  1  buffer  106 , encode stage  2  buffer  108 , encode stage  3  buffer  110 , encode stage  4  buffer  112 , and encode stage  5  buffer  114  may store higher resolution decompressed frames and lower resolution reconstructed frames. A descaler may generate the lower resolution reconstructed frames by using a descaling process. The encoding and the descaling of the frames may be performed at the same time.  
         [0110]     Timing sequences for example 8 is similar to that of example 7, as shown in  FIG. 5B . The processes performed by the video decoder  12 , the video encoder  14 , and the display controller  18  are similar to those described in example 7, except that the frames I 0 ′, B 1 ′, B 2 ′, P 3 ′, B 4 ′, B 5 ′, P 6 ′, B 7 ′, B 8 ′, P 9 ′, B 10 ′, B 11 ′, and P 12 ′ are lower resolution reconstructed frames, and I 0 , I 1 , I 2 , I 3 , I 4 , I 5 , I 6 , I 7 , I 8 , I 9 , I 10 , I 11 , and I 12  are higher resolution decompressed frames.  
         [0111]     Similar to example 7, in example 8, the video decoder  12 , the video encoder  14 , and the display controller  18  share the memory  22  such that the memory  22  at any given time stores no more than five decompressed frames in buffers  106 ,  108 ,  110 ,  112 , and  114 .  
         [0112]     In examples 1-8 described above, the system controller  24  coordinates the operations of the video decoder  12 , the video encoder  14 , and the display controller  8  according to the formats of the input and output signals. The video controller  10  may include firmware that includes code for controlling the operations of various components. The firmware may include code to cause the display  28  to show menu options to allow a user to specify, for example, the input and output formats, whether to display higher or lower resolution video, and the resolution and the bit rate of the output encoded video  30 .  
       ALTERNATIVE EXAMPLES  
       [0113]     In the description above, the videos are encoded/decoded according to a JPEG, DV, or MPEG standard. The videos can also be encoded/decoded using other standards, such as International Telecommunications Union (ITU) H.261, H.263, or H.264 standard. The video controller  10  can be used to transcode a lower bit-rate video to a higher bit-rate video. The video controller  10  can be used to transcode a lower resolution video to a higher resolution video. If the video is not shown on a display, each of the time intervals T 0 , T 1 , T 2 , . . . , does not necessarily have to be equal to a frame period. The duration of the time intervals depend on the speed on decoding and encoding.  
         [0114]     The video controller  10  can be incorporated in, for example, a video recorder (which can store video programs to tapes, optical media, hard drives, or other non-volatile storage), a television or set-top box having a built-in mass storage, a portable video player/recorder, and a cell phone capable of playing/recording video.  
         [0115]     In examples 1-4, the memory device  22  can be made smaller by omitting the buffer  114 , which is not used. In examples 7 and 8, the memory device  22  can be made smaller by omitting the buffers  102  and  104 , which are not used. The display controller  18  may be omitted from the video controller  10  if the video is not shown on a display.  
         [0116]     Other examples are within the scope of the following claims.