Abstract:
A current mode multiplier circuit is provided based on the square root; voltage-current relationship of an MOS transistor. The circuit includes first, second and third MOS transistors with a common aspect ratio, and first and second current sources that respectively provide first and second input currents that represent first and second factors to be multiplied. The first and second MOS transistors produce first and second voltages as a function of the first and second input currents, and the third MOS transistor produces a third current as a function of the first and second voltages. In response to the third current, the circuit produces a product signal that represents a product of the first and second factors.

Description:
TECHNICAL FIELD OF THE INVENTION  
       [0001]     The invention relates generally to analog multipliers and, more particularly, to current mode multipliers.  
       BACKGROUND OF THE INVENTION  
       [0002]     Analog multipliers are useful components in various types of analog circuits. As analog circuit technology progresses, various circuit; characteristics have become more desirable and/or mandatory required. Examples of such characteristics include low circuit complexity, small circuit footprint, low supply voltage and high frequency operation.  
         [0003]     It is desirable in view of the foregoing to provide analog multipliers that exhibit one or more of the aforementioned exemplary characteristics.  
       SUMMARY OF THE INVENTION  
       [0004]     Exemplary embodiments of the invention provide a current mode multiplier circuit based on the square root voltage-current relationship of an MOS transistor. The circuit includes first, second and third MOS transistors with a common aspect ratio, and first and second current sources that respectively provide first and second input currents that represent first and second factors to be multiplied. The first and second MOS transistors produce first and second voltages as a function of the first and second input currents, and the third MOS transistor produces a third current as a function of the first and second voltages. In response to the third current, the circuit produces a product signal that represents a product of the first and second factors.  
         [0005]     Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document; the terms “include, and comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term “controller” means any device, system or part thereof that controls at least one operation. A controller may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with a controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0006]     For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numerals represent like parts;  
         [0007]      FIG. 1  diagrammatically illustrates a single quadrant square root current mode multiplier circuit according to exemplary embodiments of the invention;  
         [0008]      FIG. 2  illustrates a portion of  FIG. 1  in more detail;  
         [0009]      FIG. 3  diagrammatically illustrates a model which can be used to determine gain reduction in the multiplier circuits of  FIGS. 1 and 2 ;  
         [0010]      FIG. 4  diagrammatically illustrates a four quadrant square root current mode multiplier circuit according to exemplary embodiments of the invention;  
         [0011]      FIGS. 5A and 5B , taken together, illustrate a detailed implementation of the circuit of  FIG. 4 ;  
         [0012]      FIG. 6  illustrates in tabular format selected characteristics of various components illustrated in  FIGS. 5A and 5B ;  
         [0013]      FIGS. 7A and 7B , taken together, diagrammatically illustrate a mixer according to exemplary embodiments of the invention;  
         [0014]      FIG. 8 a  illustrates in tabular format selected characteristics of various components illustrated in  FIGS. 7A and 7B ; and  
         [0015]      FIGS. 9 and 10  graphically illustrate selected signals from  FIGS. 5A, 5B ,  7 A and  7 B.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0016]      FIGS. 1 through 10 , discussed herein, and the various embodiments used to describe the principles of the present invention in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the invention. Those skilled in the art will understand that the principles of the present invention may be implemented in any suitably arranged system.  
         [0017]     A four quadrant multiplier can be realized according to exemplary embodiments of the invention using the conditions: I b &gt;O, I b &gt;|I in1 |+|i in2 |, and the following series expansion:  
                     (       I   b     +     i     i   ⁢           ⁢   n   ⁢           ⁢   1       -     i     i   ⁢           ⁢   n   ⁢           ⁢   2         )     ·     (       I   b     -     i     i   ⁢           ⁢   n   ⁢           ⁢   1       +     i     i   ⁢           ⁢   n   ⁢           ⁢   2         )         -         (       I   b     +     i     i   ⁢           ⁢   n   ⁢           ⁢   1       +     i     i   ⁢           ⁢   n   ⁢           ⁢   2         )     ·     (       I   b     -     i     i   ⁢           ⁢   n   ⁢           ⁢   1       -     i     i   ⁢           ⁢   n   ⁢           ⁢   2         )           =       2   ·         i     i   ⁢           ⁢   n   ⁢           ⁢   1       ·     i     i   ⁢           ⁢   n   ⁢           ⁢   2           I   b         +         i     i   ⁢           ⁢   n   ⁢           ⁢   1       ·     i     i   ⁢           ⁢   n   ⁢           ⁢   2     3         I   b   3       +         i     i   ⁢           ⁢   n   ⁢           ⁢   1     3     ·     i     i   ⁢           ⁢   n   ⁢           ⁢   2           I   b   3       +     0   ⁢     (   7   )                 (   1   )             
 
         [0018]     I b  represents a bias current, i in1  and i in2  are the input signal currents (which represent the factors to be multiplied), and 0 (7) represents a truncation error of order 7. The wanted term is  
       2   ·           i     i   ⁢           ⁢   n   ⁢           ⁢   1       ·     i     i   ⁢           ⁢   n   ⁢           ⁢   2           I   b       .         
 
 Each square-root term on the left-hand side is generated by the output current of a one quadrant square root multiplier (1 QSRM). The difference current between two of these one quadrant Multipliers provides the desired multiplication result (product). 
 
         [0019]     A one quadrant square root multiplier (1 QSRM) circuit according to exemplary embodiments of the invention is shown in  FIG. 1 . The MOS transistors M 1 , M 2  and M 3  are assumed to operate in saturation. Transistors M 1  and M 2  are diode connected. The input signal currents i in1  and i in2 , and the bias current I b , are provided by respectively corresponding current sources. The currents i 1  and i 2  through M 1  and M 2  respectively are 
 
 i   1   =I   b   −i   in1   −i   in2    (2) 
 
 i   2   =I   b   +i   in1+ i in2  
 
         [0020]     All MOS transistors operate in saturation according to the square law characteristic of the MOS transistor. Furthermore, all MOS transistors have the same aspect ratio. The gate source voltages of M 1  and M 2  are:  
                 V     g   ⁢           ⁢   s   ⁢           ⁢   1       =       V   T     +         i   1     K           ⁢     
     ⁢       V     g   ⁢           ⁢   s   ⁢           ⁢   2       =       V   T     +         i   2     K                   (   3   )             
 
 wherein V T  is the threshold voltage and K is the transconductance factor. The gate source voltages V gs1  and V gs2  are averaged and applied to the gate of MOS transistor M 3 , such that:  
               V     g   ⁢           ⁢   s   ⁢           ⁢   3       =         V     g   ⁢           ⁢   s   ⁢           ⁢   1       +     V     g   ⁢           ⁢   s   ⁢           ⁢   2         2             (   4   )             
 
 The resulting drain current i 3  through M 3  is therefore:  
               i   3     =     K   ·       (         V     gs   ⁢           ⁢   1       2     +       V     g   ⁢           ⁢   s   ⁢           ⁢   2       2     -     V   T       )     2               (   5   )             
 
 Next, substitute for V gs1  and V gs2 :  
               i   3     =     K   ·       (         1   2     ⁢         i   1     K         +       1   2     ⁢         i   2     K           )     2               (   6   )             or                           i   3     =     K   ·       (         1   4     ⁢       i   1     K       +       1   4     ⁢       i   2     K       +       1   2     ⁢           i   2     ·     i   2         K   ·   K             )     .               (   7   )             
 
 Finally substitute for i 1  and i 2 :  
               i   3     =     (         1   2     ⁢     I   b       +       1   2     ⁢         (       I   b     -     i     i   ⁢           ⁢   n   ⁢           ⁢   1       -     i     i   ⁢           ⁢   n   ⁢           ⁢   2         )     ·     (       I   b     +     i     i   ⁢           ⁢   n   ⁢           ⁢   1       +     i     i   ⁢           ⁢   n   ⁢           ⁢   2         )             )             (   8   )             
 
         [0021]     The constant part I b  (i in1 =0, i in2 =0) is compensated for by the connection of the I b  current source at the drain of M 3 . The output current i 0  is equal to i 3 −I b , which is:  
               i   0     =         1   2     ⁢         (       I   b     -     i     i   ⁢           ⁢   n   ⁢           ⁢   1       -     i     i   ⁢           ⁢   n   ⁢           ⁢   2         )     ·     (       I   b     +     i     i   ⁢           ⁢   n   ⁢           ⁢   1       +     i     i   ⁢           ⁢   n   ⁢           ⁢   2         )           -       1   2     ⁢     I   b                 (   9   )             
 
 This is equal to half of one of the left hand side components of equation (1) minus a constant current I b /2. Note that i 0  does not contain a processing-dependent factor. 
 
         [0022]     According to equation (4), the average of the voltages V gs1  and V gs2  is applied at the gate of M 3 . Some embodiments do this is using two resistors. With resistors, a simple implementation of the 1 QSRM is possible, as shown in  FIG. 2 . By using equal resistor values (R 1 =R 2 ), equation (4) is implemented. The resistors R 1  and R 2  load the input current sources i in1  and i in2 . The resistors R 1  and R 2  reduce the gain of the multiplier and cause the gain to depend on the process. The gain reduction of the multiplier can be approximated using the simplified small signal model of  FIG. 3 . Only M 1  and M 2  are modeled. Nodes X 1  and X 2  in  FIG. 3  correspond to nodes X 1  and X 2  in  FIGS. 1 and 2 .  
         [0023]     According to the simple square law MOS model, the small signal transconductance gmx equals: 
 
 gmx= 2 ·√{square root over (I b K)}   (10) 
 
 This indicates that the transconductance is processing dependent, but controlled by the bias current Ib. The difference current id equals:  
             id   =       (       i     i   ⁢           ⁢   n   ⁢           ⁢   1       +     i     i   ⁢           ⁢   n   ⁢           ⁢   2         )     ·     (         1     g   ⁢           ⁢   m   ⁢           ⁢   1       +     1     gm   ⁢           ⁢   2             R   ⁢           ⁢   1     +     R   ⁢           ⁢   2     +     1     gm   ⁢           ⁢   1       +     1     gm   ⁢           ⁢   2           )               (   11   )             
 
 This difference current reduces the small signal drain-source current of M 1  and M 2  by a factor “r”:  
             r   =           (       i     i   ⁢           ⁢   n   ⁢           ⁢   1       +     i     i   ⁢           ⁢   n   ⁢           ⁢   2         )     -   id       (       i     i   ⁢           ⁢   n   ⁢           ⁢   1       +     i     i   ⁢           ⁢   n   ⁢           ⁢   2         )       =     (         R   ⁢           ⁢   1     +     R   ⁢           ⁢   2           R   ⁢           ⁢   1     +     R   ⁢           ⁢   2     +     1     g   ⁢           ⁢   m   ⁢           ⁢   1       +     1     g   ⁢           ⁢   m   ⁢           ⁢   2           )               (   12   )             
 
 This factor “r” can be kept close to 1 by choosing R 1  and R 2  as large as possible, and 1/gm1 and 1/gm2 as small as possible. 
 
         [0024]     A four quadrant multiplier (4 QM) can be constructed with 2 versions of 1 QSRM from  FIG. 2 . Exemplary embodiments of the resulting circuit 4 QM are shown in  FIG. 4 . All MOS transistors operate in saturation according to the square law characteristic of the MOS transistor. Furthermore, all MOS transistors have the same aspect ratio.  
         [0025]     The differential output current i o+ −i o− , as seen at the output stage, equals:  
                 i     0   +       -     i     0   -         =     (               1   2     ⁢         (       I   b     -     i     i   ⁢           ⁢   n   ⁢           ⁢   1       +     i     i   ⁢           ⁢   n   ⁢           ⁢   2         )     ·     (       I   b     +     i     i   ⁢           ⁢   n   ⁢           ⁢   1       -     i     i   ⁢           ⁢   n   ⁢           ⁢   2         )           -                 1   2     ⁢         (       I   b     -     i     i   ⁢           ⁢   n   ⁢           ⁢   1       -     i     i   ⁢           ⁢   n   ⁢           ⁢   2         )     ·     (       I   b     +     i     i   ⁢           ⁢   n   ⁢           ⁢   1       +     i     i   ⁢           ⁢   n   ⁢           ⁢   2         )                 )             (   13   )             
 
 The output current can be approximated by:  
                 i     0   +       -     i     0   -         ≅           i     i   ⁢           ⁢   n   ⁢           ⁢   1       ·     i     i   ⁢           ⁢   n   ⁢           ⁢   2           I   b       +         i     i   ⁢           ⁢   n   ⁢           ⁢   1       ·     i     i   ⁢           ⁢   n   ⁢           ⁢   2     3         2   ⁢     I   b   3         +         i     i   ⁢           ⁢   n   ⁢           ⁢   1     3     ·     i     i   ⁢           ⁢   n   ⁢           ⁢   2           2   ⁢     I   b   3         +       0   ⁢     (   7   )       2               (   14   )             
 
 In this equation (14), it is clear that the higher order unwanted terms can be minimized by increasing the bias current I b . 
 
         [0026]     The multiplier 4 QM of  FIG. 4  can be used at a very low supply voltage. In some embodiments, a minimum supply voltage of one gate-source voltage, e.g. V gs1 , at a current 2*I b  and one saturation voltage added for the current source I b  is sufficient for proper operation.  
         [0027]     The multiplier 4 QM of  FIG. 4  can be scaled to operate at very high frequencies. In a high frequency application, such as a mixer, only nodes X 1 , X 2 , X 4  and X 5  have to operate at the highest frequency. The nodes X 3 , and X 6 , and the output nodes Xo+ and Xo− operate at the much lower difference frequency. This means that the output: MOS transistors M 3  and M 6  can be scaled to maximize the low frequency output current. Furthermore, the bias current through MOS transistors M 3  and M 6  can be reduced, independently of MOS transistors M 1 , M 2 , M 4  and M 5 .  
         [0028]     The four quadrant current mode multiplier 4 QM can be used as a mixer. In a mixer, a high frequency input signal is converted to a low frequency output signal by multiplication with a signal at the difference frequency.  FIGS. 5A-10  illustrate exemplary embodiments of a mixer application of the four quadrant current mode multiplier 4 QM. Nodes that are common to both  FIGS. 5A and 5B  are designated therein as  51 ,  52 ,  53 ,  54  and  55 .  
         [0029]     A current of I(ibias_snk)=50 μA is applied at the input “ibias_snk” in  FIG. 5A , feeding the current mirror formed by MOS transistors M 28 , M 29  and M 30 . The output currents of M 29  and M 30  (50 μA) are fed to diode connected MOS transistors M 3  and M 31 -M 34 . M 3  in  FIG. 5A  forms a bias current mirror with MOS transistors M 2 , M 6 , M 11  and M 12  (see also  FIG. 5B ). The latter four MOS transistors are scaled up by a factor of 20 with respect to M 3 , and feed a 1 mA bias current to the respectively corresponding differential pairs  500 ,  501 ,  502  and  503 . MOS transistors M 31 -M 34  generate a cascode bias voltage for cascode MOS transistors M 35 , M 42 , M 40  and M 41  (see also  FIG. 5B ). This keeps the MOS transistors of the bias current mirror in saturation and increases the output impedance of the bias current sources.  
         [0030]     The differential pairs  501 - 504  (including MOS transistors M 0 , M 1 , M 4 , M 5  and M 36 -M 39 ) are used to convert the differential input voltages vin 1 p, vin 1 n and vin 2 p, vin 2 n to input currents (e.g. i in1 , and i in2  of  FIG. 4 ) appropriate for the current mode multiplier 4 QM. In some embodiments, the small signal conversion transconductance is gm in =6.8 mS.  
         [0031]     The MOS transistors of the circuits 1 QSRM in  FIGS. 5A and 5B  are scaled in some embodiments to achieve high frequency performance. The output current includes a common mode part and a differential part. The signal output current i o+ , i o− , as seen at the output stage, is differential. The unwanted common mode output current is compensated for by the common mode output regulation block  505 . In block  505 , the output common mode voltage is sensed with MOS transistor M 7  and M 8 . Feedback is implemented through output current source MOS transistors  506  and  507 . The output current through. MOS transistors M 15  and M 20  is scaled down in some embodiments to a factor of ¼. The multiplier equation (14) will then be realized by the approximation:  
                 i     0   +       -     i     0   -         ≅         i     i   ⁢           ⁢   n   ⁢           ⁢   1       ·     i     i   ⁢           ⁢   n   ⁢           ⁢   2           4   ⁢     I   b                 (   15   )             
 
         [0032]     Selected components of the multiplier 4 QM of  FIGS. 5A and 5B  are scaled according to  FIG. 6  in some embodiments.  
         [0033]     Referring to the exemplary mixer embodiments of  FIGS. 7A and 7B , nodes common to  FIGS. 7A and 7B  are shown therein as  71 ,  72 ,  73  and  74 . Voltage sources V 1  and V 2  generate high frequency input: signals. The voltage controlled voltage sources E 0  to E 3  convert the single ended input voltages vin 1  and vin 2  into differential voltages vin 1 p, vin 1 n and vin 2 p, vin 2 n. These are applied to the multiplier 4 QM. The common mode input voltage cmin is generated for voltage sources E 0 -E 3  by PC voltage source V 4 .  
         [0034]     The wanted differential current output signal i o+ , i o− , out of multiplier 4 QM is fed to an output stage that includes a current-to-voltage converter (I/V converter)  700  built around opamp  701  (see also  FIG. 7B ). In some embodiments, the conversion resistors are R 5 =R 6 =20 kohm, and C 0 -C 3  are 0.1 pF capacitors used to assure the stability of the I/V converter. Capacitors C 4  and C 5  are shown to represent load capacitance of the I/V converter.  FIG. 8  shows the sizing of selected components in  FIGS. 7A and 7B  according to some embodiments.  
         [0035]     When two input signals according to  FIG. 8  (vin 1  at fin1 and vin 2  at fin2) are applied to the multiplier, the differential output signal has ideally two frequency components, the sum and difference frequencies of the input signals, 1.01 GHz and 10 MHz respectively. The output signal at 10 MHz is the wanted component. The component at 1.01 GHz is filtered. Referring also to  FIGS. 5A and 5B , filtering time constants are formed by parallel resistance pairs R 1  and R 2  (R 3  and R 4 ) and the gate-source capacitance of the corresponding output MOS transistor M 15  (M 20 ). Further filtering is achieved by the I/V converter which in some embodiments has a bandwidth of 40 MHz.  
         [0036]      FIGS. 9 and 10  show selected signals from  FIGS. 5A, 5B ,  7 A and  7 E. The high frequency input signals vin 1 , vin 2  ( FIG. 7A ) and the internal multiplier node voltages on x 1 , x 2  and x 3  ( FIG. 5A ) are shown in  FIG. 9 . This shows that the multiplier compresses the input signals. The low ohmic nodes x 1  (x 4 ) and x 2  (x 5 ) make the circuit suitable for high frequency operation. On node x 3  (x 6 ), the low frequency signal component at 10 MHz is obvious. This indicates that node x 3  (x 6 ) is already a “low frequency” node. Due to scaling of the output MOS transistors M 15  and M 20  in some embodiments, the gate-source capacitances of these MOS transistors already filters most of the high frequency signal content on node x 3  (x 6 ).  
         [0037]      FIG. 10  shows the voltage on nodes vout and outp_a and outn_a of  FIG. 7B . The differential output voltage vout=outp_a−outn_a has a frequency of 10 MHZ, showing the mixing performance of the circuit. The amplitude of the output signal vout is 0.25 V.  
         [0038]     Although the present invention has been described with exemplary embodiments, various changes and modifications may be suggested to one skilled in the art. It is intended that the present invention encompass such changes and modifications as fall within the scope of the appended claims.