Abstract:
A method of generating a function within a logic design of a circuit, includes representing the function using an operator. The function has n operands, where n&gt;1. The method also includes presenting the function within a schematic representation of the logic design. Other features may include displaying a dialog box and inputting data that corresponds to the function.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]    This application claims priority from U.S. Provisional Application No. 60/315,852, filed Aug. 29, 2001, and titled “Visual Modeling and Design Capture Environment,” which is incorporated by reference. 
     
    
     
       TECHNICAL FIELD  
         [0002]    This invention relates to circuit simulation.  
         BACKGROUND  
         [0003]    Logic designs for circuits typically include either schematic design or text design. A schematic design shows a circuit design with logic elements as a two-dimensional diagram. Logic elements are either state elements (e.g., flip-flops, latches, etc.) or combinatorial elements (e.g., AND gates, NOR gates, etc.). State elements provide storage from one cycle of operation to the next cycle of operation. Combinatorial elements are used to perform operations on two or more signals.  
           [0004]    A textual representation describes the logic elements of a circuit using one-dimensional text lines. Textual representations are used in hardware description languages (HDLs) which allow designers to simulate logic designs prior to forming the logic on silicon. Examples of such languages include Verilog and Very High-Level Design Language (VHDL). Using these languages, a designer can write code to simulate a logic design and execute the code in order to determine if the logic design performs properly.  
           [0005]    Standard computer languages may also be used to simulate a logic design. One example of a standard computer language that may be used is C++. 
       
    
    
     DESCRIPTION OF THE DRAWINGS  
       [0006]    [0006]FIG. 1 is a flowchart showing a process for generating a logic design using programmable binary operators.  
         [0007]    [0007]FIG. 2 is a screenshot of a dialog box for generating a logic design having a binary operator.  
         [0008]    [0008]FIG. 3 is a schematic representation of a function generated from the dialog box in FIG. 2.  
         [0009]    [0009]FIG. 4 is a block diagram of a computer system on which the process of FIG. 1 may be performed.  
     
    
     DESCRIPTION  
       [0010]    Referring to FIG. 1, a process  10  is used in generating a logic design to generate a configurable binary operator gate by using programmable binary operators. The configurable binary operator gate is a generalized gate structure designed to model a user-defined function comprised of a binary operator acting on two operands. Thus, the gate structure can be designed to be an adder, a shifter, a comparator, an incrementor, etc.  
         [0011]    Process  10  may be implemented using a computer program running on a computer  50  (FIG. 4) or other type of machine, as described in more detail below. As explained below, by using binary operators, complex logic models can be presented to a user (not shown) that have a simple readable body element comprised of the gate structure and a software code representing the gate structure displayed within the gate structure.  
         [0012]    Referring to FIG. 2, process  10  accesses and displays ( 12 ) a dialog box  22  in response to a user input. The user may use any input/output (I/O) device to access and display ( 12 ) dialog box  22 . For example, design tools employing process  10  may reside on a personal computer and the tools may operate in a MS-Windows® environment. If the user determines that a function having a binary operator is needed in the design, the user pulls-down a menu (not shown) or right-clicks a mouse button to access dialog box  22 . In response, process  10  displays dialog box  22  is displayed on a computer monitor.  
         [0013]    Process  10  receives input ( 14 ) from dialog box  22 . In this regard, dialog box  22  may be a graphical user interface (GUI) into which the user inputs data to generate a gate structure (see, e.g., FIG. 3 described below). For example, using a mouse, the user may choose either a signal input or a constant input for a left operand  24  and for a right operand  28  by clicking on a circle  25  next to the desired choice. If a constant is chosen, dialog box  22  is highlighted indicating to the user a constant has been chosen. Using a keyboard, the user types-in a left pin name  26 , a right pin name  30 , and an output pin name  36 . The user further accesses a pull-down menu  32  to choose a desired binary operator. By clicking on “OK” button  34 , the user has provided the inputs from dialog box  22  to process  10 .  
         [0014]    Process  10  uses the binary operator selected from pull-down menu  32  to represent ( 16 ) the corresponding function. For example, if the binary operator chosen is “==”, a gate  40  (FIG. 3) representing a comparator function is displayed. Binary operator symbols can be a logical operator or a non-logical operator. The binary operator symbol “==” is a logical operator. Logical operators produce an output of either a ‘1’ or a ‘0’ or a bit width of 1. For non-logical operators (e.g., “+”, “&gt;&gt;”, etc.), the bit width of the output is equal to the bit width of each input. For example, if the function, a+b, is chosen and an input signal a is 4 bits wide and input signal b is a 4 bits wide, then the resulting output signal is 4 bits wide.  
         [0015]    Other functions can be represented by using the following binary operator symbols:  
                                       Binary Operator Symbols   Function   Notation                   +   Addition   a + b = c       −   Subtraction   a − b = c       *   Multiplication   a × b = c       /   Division   a ÷ b = c       %   Modulo   a modulo b       &amp;&amp;   Logical AND   a AND b       ∥   Logical OR   a OR b       &gt;&gt;   Shift Right   Take a and shift               right by b       &lt;&lt;   Shift Left   Take a and shift               left by b       &lt;   Less than   Is a &lt; b?       &lt;=   Less than or   Is a ≦ b?           equal       ==   Equal   Is a = b?       !=   Not equal   Is a ≠ b?       &gt;   Greater than   Is a &gt; b?       &gt;=   Greater than or   Is a ≧ b?           equal       ===   Three state   Is a = b?           equal       !==   Three state not   Is a ≠ b?           equal                  
 
         [0016]    Referring to FIGS. 2 and 3, process  10  displays ( 18 ) the function selected as a gate  40  using a Verilog code  42 . In other words, process  10  embeds a textual combinatorial data block into a two-dimensional schematic presentation. The information depicted in FIG. 2 is represented in FIG. 3, e.g., “a==b (?)” is the Verilog code for a comparator. In this example, input signal a is represented by “opA[3:0]” and input signal b is represented by “opB[3:0].” Also, input signal a and input signal b are each 4 bits wide. Process  10  automatically (i.e., without user intervention) generates an output signal “out” represented as “opOut[0:0],” as a one bit wide signal. Thus, process  10  reduces the need to have large libraries based on bit-width size by automatically calculating an appropriate bit-width size.  
         [0017]    [0017]FIG. 4 shows computer  50  for generating a logic design using process  10 . Computer  50  includes a processor  52 , a memory  54 , and a storage medium  56  (e.g., a hard disk). Storage medium  56  stores data  62  which defines a logic design, a graphics library  60  used in implementing the logic design, and machine-executable instructions  58 , which are executed by processor  52  out of memory  54  to perform process  10  on data  62 .  
         [0018]    Process  10 , however, is not limited to use with the hardware and software of FIG. 4; it may find applicability in any computing or processing environment. Process  10  may be implemented in hardware, software, or a combination of the two. Process  10  may be implemented in computer programs executing on programmable computers or other machines that each includes a processor, a storage medium readable by the processor (including volatile and non-volatile memory and/or storage elements), at least one input device, and one or more output devices. Program code may be applied to data entered using an input device, such as a mouse or a keyboard, to perform process  10  and to generate a simulation.  
         [0019]    Each such program may be implemented in a high level procedural or object-oriented programming language to communicate with a computer system. However, the programs can be implemented in assembly or machine language. The language may be a compiled or an interpreted language.  
         [0020]    Each computer program may be stored on an article of manufacture, such as a storage medium or device (e.g., CD-ROM, hard disk, or magnetic diskette), that is readable by a general or special purpose programmable machine for configuring and operating the machine when the storage medium or device is read by the machine to perform process  10 . Process  10  may also be implemented as a machine-readable storage medium, configured with a computer program, where, upon execution, instructions in the computer program cause the machine to operate in accordance with process  10 .  
         [0021]    The invention is not limited to the specific embodiments set forth above. Process  10  is not limited to using two operands. Process  10  can be used with k operands, where k&gt;1. Process  10  is not limited to binary operators but may be any x-state operators, where x≧2. Also, process  10  is not limited to embedding one-dimensional design into a two-dimensional design. Process can be any n-dimensional design embedded into a (n+m)-dimensional design, where n≧1 and m≧1. Process  10  is not limited to the computer languages set forth above, e.g., Verilog, C++, and VHDL. It may be implemented using any appropriate computer language. Process  10  is also not limited to the order set forth in FIG. 1. That is, the blocks of process  10  may be executed in a different order than that shown to produce an acceptable result.  
         [0022]    Other embodiments not described herein are also within the scope of the following claims.