Abstract:
Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes a data detector circuit, a detector mimicking circuit, and an error calculation circuit. The data detector circuit is operable to perform a data detection process on a first signal derived from a data input to yield a detected output. The data mimicking circuit is operable to process a second signal derived from the data input to yield a mimicked output. The error calculation circuit is operable to calculate a difference between the second signal and a third signal derived from the mimicked output to yield a feedback signal. The feedback signal is operable to modify the data input during a subsequent period.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for low latency loop processing. 
         [0002]    Various data processing circuits have been developed that include one or more loops. For example, a data processing circuit may receive a data signal that repeats at a defined frequency. In some cases, such loops are adjusting multiple modifiable parameters together. This can result in loop oscillation and/or improper loop operation. 
         [0003]    Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for data processing. 
       BRIEF SUMMARY OF THE INVENTION 
       [0004]    The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for low latency loop processing. 
         [0005]    Various embodiments of the present invention provide data processing circuits that include a data detector circuit, a detector mimicking circuit, and an error calculation circuit. The data detector circuit is operable to perform a data detection process on a first signal derived from a data input to yield a detected output. The data mimicking circuit is operable to process a second signal derived from the data input to yield a mimicked output. The error calculation circuit is operable to calculate a difference between the second signal and a third signal derived from the mimicked output to yield a feedback signal. The feedback signal is operable to modify the data input during a subsequent period. In some cases, the first signal and the second signal are the same signal. In various cases, the circuit further includes an analog to digital converter circuit and a digital filter. The analog to digital converter circuit is operable to convert the data input into a corresponding digital output. The digital filter is operable to filter the digital output and provide a filtered output. In such cases, the first signal is the filtered output, and the second signal may be either the digital output or the filtered output. In various instances of the aforementioned embodiments, the detector mimicking circuit includes circuitry to mitigate interference evident in a current bit that is related to at least one preceding bit in a bit stream. 
         [0006]    In some instances of the aforementioned embodiments, the error calculation circuit includes a transition frequency filter circuit operable to reduce the value of the feedback signal when a transition frequency is greater than a threshold. In some such instances, the value of the feedback signal is reduced to zero. In other instances of the aforementioned embodiments, the error calculation circuit includes a transition frequency filter circuit operable to reduce the value of the feedback signal when the mimicked output matches a defined pattern. In some such instances, the value of the feedback signal is reduced to zero. 
         [0007]    In some instances of the aforementioned embodiments, the detector mimicking circuit includes: a summation circuit, a comparator circuit, a delay circuit, and a multiplier circuit. The summation circuit is operable to sum the second signal with an interference value to yield a sum. The comparator circuit operable to receive the sum and to provide the mimicked output based at least in part on a value of the sum. The delay circuit is operable to delay the sum by a bit period to yield a delayed output. The multiplier circuit is operable to multiply the delayed output by an interference coefficient corresponding to a preceding bit period to yield the interference value. 
         [0008]    Other embodiments of the present invention provide methods for lowering feedback latency in a low frequency data detection circuit. The methods include providing a data detector circuit; providing a detector mimicking circuit; receiving a data input; performing a data detection process using the data detector circuit on a first signal derived from the data input to yield a detected output; performing a detector mimicking process using the detector mimicking circuit on a second signal derived from the data input to yield a mimicked output; calculating an error value as a difference between the second signal and a third signal derived from the mimicked output; generating a feedback signal based at least in part on the error value; and applying the feedback signal to modify the data input. In some cases, the first signal and the second signal are the same signal. In various cases, the methods further include performing an analog to digital conversion on the data input to yield a digital output; and performing a digital filtering of the digital output to yield a filtered output. In such cases, the first signal is the filtered output, and the second signal may be either the digital output or the filtered output. 
         [0009]    In one or more instances of the aforementioned embodiments, performing the detector mimicking process includes reducing interference evident in a current bit that is related to at least one preceding bit in a bit stream. In some instances of the aforementioned embodiments, the methods further include determining that a high frequency of transitions is evident in the mitigated output; and based at least in part on determining that a high frequency of transitions is evident in the mitigated output, reducing the error value. 
         [0010]    This summary provides only a general outline of some embodiments of the invention. Many other objects, features, advantages and other embodiments of the invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    A further understanding of the various embodiments of the present invention may be realized by reference to the figures which are described in remaining portions of the specification. In the figures, like reference numerals are used throughout several figures to refer to similar components. In some instances, a sub-label consisting of a lower case letter is associated with a reference numeral to denote one of multiple similar components. When reference is made to a reference numeral without specification to an existing sub-label, it is intended to refer to all such multiple similar components. 
           [0012]      FIG. 1  depicts an existing loop circuit including low frequency noise correction feedback; 
           [0013]      FIG. 2   a  shows a low latency loop circuit in accordance with one or more embodiments of the present invention; 
           [0014]      FIG. 2   b  depicts a detector mimicking circuit that may be used in relation to the low latency loop circuit of  FIG. 2   a  in accordance with some embodiments of the present invention; 
           [0015]      FIG. 3  depicts another low latency loop circuit including a high frequency transition detector circuit in accordance with various embodiments of the present invention; 
           [0016]      FIG. 4  is a flow diagram showing a method for low latency, low frequency loop processing in accordance with some embodiments of the present invention; 
           [0017]      FIG. 5  shows a storage system including a read channel circuit with a low latency, low frequency loop circuit in accordance with some embodiments of the present invention; and 
           [0018]      FIG. 6  depicts a wireless communication system including a receiver with a low latency, low frequency loop circuit in accordance with some embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0019]    The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for low latency loop processing. 
         [0020]    Turning to  FIG. 1 , an existing loop circuit  100  is shown that includes low frequency noise correction feedback. Loop circuit  100  includes a variable gain amplifier  110  that receives an analog input  105 . Variable gain amplifier  110  amplifies analog input  105  to yield an amplified output  115  that is provided to a summation circuit  120 . Summation circuit  120  subtracts a feedback signal  195  from amplified output  115  to yield a sum  125 . 
         [0021]    Sum  125  is provided to an analog to digital converter circuit  130  that converts the received signal into a series of digital samples  135  that are provided to a digital finite impulse response filter  140 . Digital finite impulse response filter  140  filters the received input and provides a corresponding filtered output  145  to both a detector circuit  150  and a summation circuit  170 . Detector circuit  170  performs a data detection process on the received input resulting in a detected output  155 . In performing the detection process, detector circuit  170  attempts to correct any errors in the received data input. 
         [0022]    Detected output  155  is provided to a partial response target circuit  160  that creates a partial response output  165  compatible with filtered output  145 . Summation circuit  170  subtracts partial response output  165  from filtered output  145  to yield an error value  175 . Error value  175  is provided to a loop filter circuit  180  that filters the received input and provides a filtered output  185  to a digital to analog converter circuit  190 . Digital to analog converter circuit  190  converts the received input to feedback signal  195 . 
         [0023]    In operation, the delay from when amplified output  115  is initially provided until a corresponding value for feedback signal  195  is available may too long. This latency can result in performance degradation or in the worst case scenario, inoperability. 
         [0024]    Various embodiments of the present invention provide for mitigating low frequency noise, while maintaining acceptable levels of feedback latency to preserve overall loop gain. For example, the low frequency noise may be around ( 1/1000)T. Such low frequency noise can have an adverse impact on system performance. In some cases, the feedback signal is generated based upon an output from a detector mimicking circuit that provides an output corresponding to that of a detector circuit, but with a substantially reduced latency. 
         [0025]    Turning to  FIG. 2   a , a low latency loop circuit  200  is shown in accordance with one or more embodiments of the present invention. Low latency loop circuit  200  includes a variable gain amplifier  210  that receives an analog input  205 . Variable gain amplifier  210  may be any circuit known in the art that is capable of amplifying a received signal by a gain that can be changed. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of circuits that may be used to implement variable gain amplifier  210 . Analog input  205  may be any analog signal carrying information to be processed. In some embodiments of the present invention, analog input  205  is derived from a storage medium. In other embodiments of the present invention, analog input  205  is derived from a transmission device. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of analog signals and/or sources thereof that may be used in relation to different embodiments of the present invention. Variable gain amplifier  210  amplifies analog input  205  to yield an amplified output  215  that is provided to a summation circuit  220 . Summation circuit  220  subtracts a feedback signal  298  from amplified output  215  to yield a sum  225 . 
         [0026]    Sum  225  is provided to an analog to digital converter circuit  230 . Analog to digital converter circuit  230  may be any circuit known in the art that is capable of converting an analog signal into a series of digital values representing the received analog signal. Analog to digital converter circuit  230  converts the received signal (sum  225 ) into a series of digital samples  235  that are provided to a digital finite impulse response filter  240 . Digital finite impulse response filter  240  may be any circuit known in the art for filtering a digital signal. Digital finite impulse response filter  240  filters the received input (digital samples  235 ) and provides a corresponding filtered output  245  to a detector circuit  250 . Detector circuit  250  may be any detector circuit known in the art including, but not limited to, a Viterbi algorithm detector circuit or a maximum a posteriori detector circuit. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of detector circuits that may be used in relation to different embodiments of the present invention. Detector circuit  250  performs a data detection process on the received input resulting in a detected output  255 . Detected output  255  may be provided to a downstream processor (not shown) that performs additional processing on the output. 
         [0027]    In addition, filtered output  245  and digital samples  235  are provided to a selector circuit  234 . Selector circuit  234  may be any circuit known in the art that is capable of selecting one or two inputs to be provided as an output signal. In one particular embodiment of the present invention, selector circuit  234  is a multiplexer circuit. Selector circuit  234  provides filtered output  245  as an output signal  236  when an output select input  232  is asserted as a logic ‘0’, and provides digital samples  235  as an output signal  236  when output select input  232  is asserted as a logic ‘1’. Output select input  232  may be a user programmable input, or may be hardwired to always select one input or the other. 
         [0028]    Output signal  236  is provided to a low latency detector mimicking circuit  260 . Low latency detector mimicking circuit  260  operates to provide a reasonable approximation of detected output  255  while not requiring the processing time of detector circuit  250 . Of note, low latency detector mimicking circuit  260  may not provide the accuracy of detector circuit  255 , but the effect of any errors is limited by the feedback loop. Low latency detector mimicking circuit  260  provides a mimicked output  265  to a partial response target circuit  270  that creates a partial response output  275  compatible with output signal  236 . A summation circuit  280  subtracts partial response output  275  from output signal  236  to yield an error value  285 . Error value  285  is provided to a high frequency transition filter circuit  288 . High frequency transition filter circuit  288  operates to set an output  290  equal to zero whenever high frequency transitions within mimicked output  265  are occurring, or equal to error value  285  at all other times. Error value  285  is thus effectively blocked from being included in the loop operation whenever mimicked output  265  is switching rapidly. When mimicked output  265  is switching at a relatively high frequency, it is likely that there are a large number of errors in the input data stream and that the output of low latency detector mimicking circuit  260  (i.e., mimicked output  265 ) is full of errors and largely unreliable. 
         [0029]    Output  290  is provided to a loop filter circuit  292  that filters the received input and provides a filtered output  294  to a digital to analog converter circuit  296 . Digital to analog converter circuit  296  converts the received input to feedback signal  298 . In operation, the delay from when amplified output  225  is initially provided until a corresponding value for feedback signal  298  is substantially less than the latency incurred when detected output  255  is used to form the error feedback signal. This reduction in latency allows for maintaining a desired level of loop gain. 
         [0030]    Turning to  FIG. 2   b , a detector mimicking circuit  700  is depicted that may be used in place of low latency detector mimicking circuit  260  of  FIG. 2   a  in accordance with some embodiments of the present invention. Detector mimicking circuit  700  includes a summation circuit  710  that receives an input signal  705 . Input signal  705  may be provided either as sum  225  or digital samples  235  depending upon the particular implementation. Summation circuit  710  subtracts an interference value  790  and an interference value  785  from input  705  to yield a sum  715 . Sum  715  is provided to a comparator circuit  720  where it is compared with a threshold value  730 . In some cases, threshold value  730  is a hardwired value of zero. Comparator circuit  720  provides a ‘+1’ as a mimicked output  740  when sum  715  is greater than or equal to threshold value  730 , and provides a ‘−1’ as a mimicked output  740  when sum  715  is less than threshold value  730 . Thus, comparator circuit  720  operates to “slice” the received input into a series of either ‘+1s’ or ‘−1s’. 
         [0031]    Mimicked output  740  is provided as an output, and also fed back through a first delay circuit  745  and a second delay circuit  755 . Two interference coefficients (T 1    780  and T 2    775 ) corresponding to respective delayed bit periods are multiplied by a respective delayed output. In particular, an interference coefficient  775  corresponds to an amount of interference caused by a bit directly preceding the current bit and is multiplied using a multiplier circuit  765  by a delayed output  750  from delay circuit  745 . An interference coefficient  780  corresponds to an amount of interference caused by a bit preceding the current bit by two periods and is multiplied using a multiplier circuit  795  by a delayed output  760  from delay circuit  755 . The output of multiplier circuit  765  is provided as interference value  785 , and the output of multiplier circuit  795  is provided as interference value  790 . 
         [0032]    In operation, detector mimicking circuit  700  receives input  705  that is either the input provided to a detector circuit or is a signal from which the input to the detector circuit is derived. Interference (i.e., interference value  785  and interference value  790 ) corresponding to two bit periods directly preceding the currently processing bit is subtracted from input  705 . The resulting sum  715  is then simplified by slicing it into either a ‘+1’ or a ‘−1’ which is provided as mimicked output  740 . 
         [0033]    Turning to  FIG. 3 , another low latency loop circuit  300  including a high frequency transition detector circuit is shown in accordance with various embodiments of the present invention. Low latency loop circuit  300  includes variable gain amplifier  210  that receives an analog input  205 . Variable gain amplifier  210  amplifies analog input  205  to yield amplified output  215  that is provided to summation circuit  220 . Summation circuit  220  subtracts feedback signal  298  from amplified output  215  to yield sum  225 . 
         [0034]    Sum  225  is provided to analog to digital converter circuit  230 . Analog to digital converter circuit  230  converts the received signal (sum  225 ) into a series of digital samples  235  that are provided to digital finite impulse response filter  240 . Digital finite impulse response filter  240  filters the received input (digital samples  235 ) and provides a corresponding filtered output  245  to detector circuit  250 . Detector circuit  250  performs a data detection process on the received input resulting in detected output  255 . Detected output  255  may be provided to a downstream processor that performs additional processing on the output. 
         [0035]    In addition, filtered output  245  is provided to low latency detector mimicking circuit  260 . Low latency detector mimicking circuit  260  operates to provide a reasonable approximation of detected output  255  while not requiring the processing time of detector circuit  250 . Of note, low latency detector mimicking circuit  260  may not provide the accuracy of detector circuit  255 , but the effect of any errors is limited by the feedback loop. Low latency detector mimicking circuit  260  provides mimicked output  265  to a partial response target circuit  270  that creates a partial response output  275  compatible with filtered output  245 . Summation circuit  280  subtracts partial response output  275  from filtered output  245  to yield an error value  285 . Error value  285  is provided to a multiplexer circuit  312  that provides either a zero value input  320  or error value  285  as a selector output  335  depending upon a selector signal  311  from a high frequency transition detector circuit  310 . 
         [0036]    High frequency transition detector circuit  310  determines whether a significant number of transitions have occurred over a given length of bits. The following pseudo code represents one implementation of the operation of high frequency transition detector circuit  310 . 
         [0000]                                                                                                                            TransitionCount = 0;           For (bit i = 0 to i = SeriesLength + 1)           {                if (bit[i] ≠ bit[i+1])           {                TransitionCount = TransitionCount +1;                }                i = i+1           }           If (TransitionCount &gt; Threshold)           {                Selector signal 311 = ‘1’;                }           Else           {                Selector signal 311 = ‘0’;                }                        
In the above implementation, the variable SeriesLength indicates the number of the most recent consecutive bits received from low latency detector mimicking circuit  260  that are used to make the determination. In one particular embodiment of the present invention, SeriesLength is six. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of lengths of bits that can be queried to make the determination in different embodiments of the present invention. The variable Threshold indicates the number of transitions within the investigated bits from low latency detector mimicking circuit  260  that have to switch before error value  285  is replaced by zero value  320 . In one particular embodiment of the present invention, the value of Threshold is five. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of values for Threshold that may be used in relation to different embodiments of the present invention.
 
         [0037]    Other embodiments of high frequency transition detector circuit  310  compares high frequency patterns with the most recently received bits from low latency detector mimicking circuit  260  to control assertion of selector signal  311 . The following pseudo code represents an example of such an implementation of high frequency transition detector circuit  310 . 
         [0000]                                                                If (mimicked output 265 = ‘−1, 1, −1, 1, −1, 1’ OR mimicked output       265 = ‘1, −1, 1, −1, 1, −1’)       {                Selector signal 311 = ‘1’;            }       Else       {                Selector signal 311 = ‘0’;            }                    
Based upon the disclosure provided herein one of ordinary skill in the art will recognize other implementations of high frequency transition detector circuit  310  that may be used in relation to different embodiments of the present invention.
 
         [0038]    Selector output  335  is provided to loop filter circuit  292  that filters the received input and provides a filtered output  294  to a digital to analog converter circuit  296 . Digital to analog converter circuit  296  converts the received input to feedback signal  298 . In operation, the delay from when amplified output  225  is initially provided until a corresponding value for feedback signal  298  is substantially less than the latency incurred when detected output  255  is used to form the error feedback signal. This reduction in latency allows for maintaining a desired level of loop gain. 
         [0039]    Turning to  FIG. 4 , a flow diagram  400  shows a method for low latency, low frequency loop processing in accordance with some embodiments of the present invention. Following flow diagram  400 , an analog input is received (block  405 ). The received analog input may be any analog signal carrying information to be processed. In some embodiments of the present invention, the analog input is derived from a storage medium. In other embodiments of the present invention, the analog input is derived from a transmission device. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of analog signals and/or sources thereof that may be used in relation to different embodiments of the present invention. A variable gain amplification is applied to the received analog input to yield an amplified output (block  410 ). 
         [0040]    An analog correction value (e.g., a feedback value) is subtracted from the amplified analog input to yield a sum (block  470 ), and an analog to digital conversion is applied to the sum yielding a series of digital samples (block  415 ). The digital samples are filtered to yield a filtered output (block  420 ). A data detection process is then applied to the filtered output that yields a detected output (block  425 ). The data detection process may be any data detection process known in the art including, but not limited to, a maximum a posteriori data detection process or a Viterbi algorithm data detection process. The result of the detection process is provided as a detected output to one or more upstream processing circuits (block  430 ). 
         [0041]    In addition, a low latency data detection mimicking process is applied to the filtered output to yield a mimicked detected output (block  440 ). The low latency detector mimicking process operates to provide a reasonable approximation of data detection process performed in block  425 , but in a shorter period of time. The low latency detector mimicking process may not provide the accuracy of the detection process, but the effect of any errors is limited by the feedback loop. 
         [0042]    The mimicked detected output is provided to a partial response target circuit where it is convolved with a target coefficient to yield a target output (block  445 ). The target output is then subtracted from the mimicked detected output to yield and error value (block  448 ). It is determined whether the mimicked detected output exhibits a high transition frequency (block  450 ). Such a determination may be made in accordance with the following pseudo code: 
         [0000]                                                                                                                            TransitionCount = 0;           For (bit i = 0 to i = SeriesLength + 1)           {                if (bit[i] ≠ bit[i+1])           {                TransitionCount = TransitionCount +1;                }                i = i+1           }           If (TransitionCount &gt; Threshold)           {                Selector signal 311 = ‘1’;                }           Else           {                Selector signal 311 = ‘0’;                }                        
In the above implementation, the variable SeriesLength indicates the number of the most recent consecutive bits provided as the mimicked detected output that are used to make the determination. In one particular embodiment of the present invention, SeriesLength is six. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of lengths of bits that can be queried to make the determination in different embodiments of the present invention. The variable Threshold indicates the number of transitions within the recent mimicked detected bits that have to switch before the resulting error value is replaced by zero value. In one particular embodiment of the present invention, the value of Threshold is five. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of values for Threshold that may be used in relation to different embodiments of the present invention.
 
         [0043]    Other embodiments of the present invention determine high frequency transitions by comparing a recently received set of bits from mimicked detected output with high frequency patterns. An example of such an approach is demonstrated in the pseudo code below: 
         [0000]    
       
         
               
               
             
               
               
             
               
               
             
               
               
             
               
               
             
           
               
                   
                   
               
             
             
               
                   
                 If (mimicked output = ‘010101’ OR mimicked output = ‘101010’) 
               
               
                   
                 { 
               
             
          
           
               
                   
                 Provide a Zero Value as the Output; 
               
             
          
           
               
                   
                 } 
               
               
                   
                 Else 
               
               
                   
                 { 
               
             
          
           
               
                   
                 Provide the Error Value as the Output; 
               
             
          
           
               
                   
                 } 
               
               
                   
                   
               
             
          
         
       
     
         [0044]    As suggested above, where a high frequency transition is detected (block  450 ), the previously calculated error value is replaced by a zero value (block  455 ). The error value is loop filtered to yield a filtered output (block  460 ), and a digital to analog conversion is applied to the filtered output to yield an analog correction value (block  465 ). 
         [0045]      FIG. 5  shows a storage system  500  including a read channel circuit  510  with a low latency, low frequency loop circuit in accordance with some embodiments of the present invention. Storage system  500  may be, for example, a hard disk drive. Storage system  500  also includes a preamplifier  570 , an interface controller  520 , a hard disk controller  566 , a motor controller  568 , a spindle motor  572 , a disk platter  578 , and a read/write head assembly  576 . Interface controller  520  controls addressing and timing of data to/from disk platter  578 . The data on disk platter  578  consists of groups of magnetic signals that may be detected by read/write head assembly  576  when the assembly is properly positioned over disk platter  578 . In one embodiment, disk platter  578  includes magnetic signals recorded in accordance with either a longitudinal or a perpendicular recording scheme. 
         [0046]    In a typical read operation, read/write head assembly  576  is accurately positioned by motor controller  568  over a desired data track on disk platter  578 . Motor controller  568  both positions read/write head assembly  576  in relation to disk platter  578  and drives spindle motor  572  by moving read/write head assembly to the proper data track on disk platter  578  under the direction of hard disk controller  566 . Spindle motor  572  spins disk platter  578  at a determined spin rate (RPMs). Once read/write head assembly  578  is positioned adjacent the proper data track, magnetic signals representing data on disk platter  578  are sensed by read/write head assembly  576  as disk platter  578  is rotated by spindle motor  572 . The sensed magnetic signals are provided as a continuous, minute analog signal representative of the magnetic data on disk platter  578 . This minute analog signal is transferred from read/write head assembly  576  to read channel circuit  510  via preamplifier  570 . Preamplifier  570  is operable to amplify the minute analog signals accessed from disk platter  578 . In turn, read channel circuit  510  decodes and digitizes the received analog signal to recreate the information originally written to disk platter  578 . This data is provided as read data  503  to a receiving circuit. As part of decoding the received information, read channel circuit  510  processes the received signal using a low latency DC loop circuit. Such a low latency DC loop circuit may be implemented consistent with that described above in relation to  FIGS. 2-3 . In some cases, the low latency, DC loop processing may be done consistent with the flow diagram discussed above in relation to  FIG. 4 . A write operation is substantially the opposite of the preceding read operation with write data  701  being provided to read channel circuit  510 . This data is then encoded and written to disk platter  578 . 
         [0047]    It should be noted that storage system  500  may be integrated into a larger storage system such as, for example, a RAID (redundant array of inexpensive disks or redundant array of independent disks) based storage system. It should also be noted that various functions or blocks of storage system  500  may be implemented in either software or firmware, while other functions or blocks are implemented in hardware. 
         [0048]    Turning to  FIG. 6 , a wireless communication system  600  including a receiver with a low latency, low frequency loop circuit is shown in accordance with some embodiments of the present invention. Communication system  600  includes a transmitter  610  that is operable to transmit encoded information via a transfer medium  630  as is known in the art. The encoded data is received from transfer medium  630  by receiver  620 . Receiver  620  incorporates a low latency DC loop circuit. Such a low latency DC loop circuit may be implemented consistent with that described above in relation to  FIGS. 2-3 . In some cases, the low latency, DC loop processing may be done consistent with the flow diagram discussed above in relation to  FIG. 4 . 
         [0049]    It should be noted that the various blocks discussed in the above application may be implemented in integrated circuits along with other functionality. Such integrated circuits may include all of the functions of a given block, system or circuit, or only a subset of the block, system or circuit. Further, elements of the blocks, systems or circuits may be implemented across multiple integrated circuits. Such integrated circuits may be any type of integrated circuit known in the art including, but are not limited to, a monolithic integrated circuit, a flip chip integrated circuit, a multichip module integrated circuit, and/or a mixed signal integrated circuit. It should also be noted that various functions of the blocks, systems or circuits discussed herein may be implemented in either software or firmware. In some such cases, the entire system, block or circuit may be implemented using its software or firmware equivalent. In other cases, the one part of a given system, block or circuit may be implemented in software or firmware, while other parts are implemented in hardware. 
         [0050]    In conclusion, the invention provides novel systems, devices, methods and arrangements for data processing. While detailed descriptions of one or more embodiments of the invention have been given above, various alternatives, modifications, and equivalents will be apparent to those skilled in the art without varying from the spirit of the invention. Therefore, the above description should not be taken as limiting the scope of the invention, which is defined by the appended claims.