Abstract:
An adjustable delay line includes a series of delay elements for adjusting the accumulative delay. Each element has a plurality of registers indicating to various devices within the delay element to be ‘on’ or ‘off’, thereby changing the time delay through the element. A master control indicates to the delay line whether to go faster (increment) or go slower (decrement). When one of these control signals is applied to the delay line, it is applied to half the elements, either the odd or the even numbered elements. Only one element will have its state changed by the increment or decrement control signal, and it will be the element for which the previous delay&#39;s corresponding element is already set or un-set depending upon the applicable case.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application is related to the subject matter disclosed in U.S. patent application Ser. No. 14/476,541 for: “LINEAR PROGRESSION DELAY REGISTER”, Attorney Docket Number UMI-602, assigned to the assignee hereof and filed on even date herewith, the disclosure of which is herein specifically incorporated by reference in its entirety. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    The present invention is related to a digital Delay-Locked Loop (DLL), and more specifically to an improved version of the adjustable delay portion of the DLL typically found in such circuits. 
         [0003]    Purely digital adjustable delay lines are typically controlled by counter-type circuits. If these delay lines adjust the delay based on temperature and/or voltage changes, they can exhibit glitches or possibly even run out of adjustable range if the delay line has been divided into course versus fine segments. Analog delay lines handle the adjustments better, but are known to have more issues with jitter as the delay is never actually stable, but rather constantly adjusting. This is especially true if the analog delay line has to be biased in such a way that large adjustments are to be required after initial lock due to expected temperature changes. 
         [0004]    Referring now to  FIG. 1 , a typical DLL  100  is shown including an adjustable delay line  102  for receiving a CLK clock input and for providing a delayed, locked clock signal at an OUTPUT output node. A fixed delay block  104  is coupled between the output of the adjustable delay line  102  and node  108 . A phase detect circuit  106  receives the CLK signal at a first input node, and the delay CLK signal at a second input node. The first and second input nodes of the phase detect circuit  106  are shown receiving respect clock pulses A and C, which is explained further below with respect to  FIG. 2 . The output of the phase detect circuit  106  is coupled to a control input of the adjustable delay line  102 . 
         [0005]    Referring now to  FIG. 2 , a timing diagram is shown including the two signal waveforms corresponding to the input CLK signal, and the delayed CLK signal at node  108 . Note in  FIG. 2  that the leading edge of the “C” CLK pulse is locked to the leading edge of the “A” pulse of the delayed CLK signal at node  108 . 
         [0006]    What is desired, therefore, is an improved adjustable delay line suitable for use in a DLL of the type shown in  FIG. 1  that does not have the problems associated with prior art digital and analog delay lines described above. 
       SUMMARY OF THE INVENTION 
       [0007]    According to an embodiment of the present invention, a series of delay elements are assembled for the purpose of adjusting the accumulative delay. Each element has a plurality of registers indicating to various devices within the delay element to be ‘on’ or ‘off’, thereby changing the time delay through the element. 
         [0008]    A master control, usually based on a phase detector of some sort, indicates to the delay line whether to go faster (increment) or go slower (decrement). When one of these control signals is applied to the delay line, it is applied to half the elements, either the odd or the even numbered elements. Only one element will have its state changed by the increment or decrement control signal, and it will be the element for which the previous delay&#39;s corresponding element is already set or un-set depending upon the applicable case. In the case of incrementing, the element that is currently un-set, but having a previous element set will change to a set state. In the case of decrementing, the element that is currently set, but having a previous element unset, will change to a un-set set state, i.e. it will be decremented. Each element has the same delay, and the amount of adjustment per element is also the same. This avoids glitches in the line when changing from different values of delay per stage at boundary conditions, a typical case when controlled by a counter. 
         [0009]    The physical placement of the elements can also be arranged such that adjacent elements in terms of programming are not physically adjacent. This keeps the signal that is propagating (typically a clock) from encountering a series of added delays and then a series of no delays. Having all the delays congregated in one area of the line can lead to signal distortion and even filtering in extreme cases. 
         [0010]    The series of delay elements can be easily reset in such a way that the ability to go fast and slower from that point is equal. Essentially, the number of ‘off’ registers is equal to the number of ‘on’ registers at the default starting condition. 
         [0011]    Alternating stages within the delay elements can also be controlled by a separate set of control signals so that the duty cycle of the signal propagating through the line can be modulated, not just the total delay. 
         [0012]    The adjustments of the delay line are purely digital, thus the deficiencies of the analog type delay lines are avoided. 
         [0013]    The digital adjustments are added in a linear fashion with the delay line, there is no control from a master counter indicating how much delay to add or subtract. When an adjustment is needed in the line, delay is added or subtracted within a single stage based on the state of the previous stage. 
         [0014]    Furthermore, control of the increment/decrement signals is each divided into an odd and even sub-type, thereby building in a master-slave relationship within all the delay registers so run-through is avoided. 
         [0015]    This delay line is easily reset. It can also be reset into a state so that going faster or slower from the reset starting point are equally feasible. This is necessary if temperature changes are expected from the initial lock point. 
         [0016]    Since a counter is not used, any number of delay stages can be utilized, it does not need to be a number that is 2 n , where n is an integer. 
         [0017]    The registers can also be arranged such that the delay is successively added to non-adjacent delay elements; this avoids the programmable delay being significantly larger within specific sections of the line which could lead to signal distortion. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0018]      FIG. 1  is a high-level schematic diagram of a DLL according to the prior art; 
           [0019]      FIG. 2  is a timing diagram showing a clock signal and a locked delayed clock signal associated with the DLL of  FIG. 1  according to the prior art; 
           [0020]      FIGS. 3A-3D  are high-level schematic diagrams of an adjustable delay line according to the present invention; 
           [0021]      FIG. 4  is a more detailed schematic diagram of a single adjustable delay line stage associated with the adjustable delay line of  FIGS. 3A-3D ; 
           [0022]      FIGS. 5-8  are more detailed schematic diagrams of latch circuits associated with the adjustable delay line of  FIGS. 3A-3D ; 
           [0023]      FIG. 9  is a timing diagram associated with the adjustable delay line of  FIGS. 3A-3D  showing a normal operational mode; 
           [0024]      FIG. 10  is a timing diagram associated with the adjustable delay line of  FIGS. 3A-3D  showing a reset operational mode; and 
           [0025]      FIG. 11  is a generalized temperature sensitive control circuit for generating linear temperature control signals for the adjustable delay line stage shown in  FIG. 4 ; and 
           [0026]      FIG. 12  is a schematic diagram of a DLL further comprising a feature for preventing the delay elements from being digitally controlled after an initial locking period. 
       
    
    
     DETAILED DESCRIPTION 
       [0027]    Digital DLLs are known to lock with precision based on the initial conditions, but are not good at adapting to changing conditions, particularly temperature changes. Known DLLs have counters and as they increment or decrement over the binary boundaries, glitches or oscillations can result in the phase detector. Analog DLLs adapt well to changing conditions, but are constantly adjusting so they have issues with jitter. 
         [0028]    An embodiment of the present invention solves the issue in two ways. Firstly, a second parallel control path is added to the delay loop so that temperature effects are adjusted separately from the normal phase detector adjusts. Control for this path is completely separate from the digital control and is analog based. Secondly, the digital portion of the adjustable delay loop is configured as a “Linear Progression Delay Register.” Each delay element is not controlled by a counter state, but rather is incremented or decremented based only on the state of the preceding register. Note the directions for incrementing and decrementing are different. 
         [0029]    Referring now to  FIGS. 3A-3D , the adjustable delay line  300  according to the present invention is shown including registers (dual delay cells)  302 ,  304 ,  306 ,  308 ,  310 ,  312 ,  314 , and  316 . Each register includes increment inputs INCA, INCB, INCC, and INCD. Each register includes decrement inputs DECA, DECB, DECC, and DECD. Each register includes signal inputs CLKIN, PRVA, PRVB, PRVC, and PRVD (left side of the register) and signal inputs NXTAB, NXTBB, NXTCB, and NXTDB (right side of the register). Each register includes signal outputs CLKOUT, A, B, C, and D (right side of the register) and signal outputs AB, BB, CB, and DB (left side of the register). The internal structure of each register is described in further detail below with respect to  FIGS. 4-8 . 
         [0030]    Control line INCA&lt;EVEN&gt; is coupled to the  INCA  input of registers  302 ,  304 ,  310 , and  312 . Control line INCA&lt;ODD&gt; is coupled to the INCA input of registers  306 ,  308 ,  314 , and  316 . Control line INCB&lt;EVEN&gt; is coupled to the INCB input of registers  302 ,  304 ,  310 , and  312 . Control line INCB&lt;ODD&gt; is coupled to the INCB input of registers  306 ,  308 ,  314 , and  316 . Control line INCC&lt;EVEN&gt; is coupled to the INCC input of registers  302 ,  304 ,  310 , and  312 . Control line INCC&lt;ODD&gt; is coupled to the INCC input of registers  306 ,  308 ,  314 , and  316 . Control line INCD&lt;EVEN&gt; is coupled to the INCD input of registers  302 ,  304 ,  310 , and  312 . Control line INCD&lt;ODD&gt; is coupled to the INCD input of registers  306 ,  308 ,  314 , and  316 . 
         [0031]    Control line DECA&lt;EVEN&gt; is coupled to the DECA input of registers  302 ,  304 ,  310 , and  314 . Control line DECA&lt;ODD&gt; is coupled to the DECA input of registers  306 ,  308 ,  314 , and  316 . Control line DECB&lt;EVEN&gt; is coupled to the DECB input of registers  302 ,  304 ,  310 , and  314 . Control line DECB&lt;ODD&gt; is coupled to the DECB input of registers  306 ,  308 ,  314 , and  316 . Control line DECC&lt;EVEN&gt; is coupled to the DECC input of registers  302 ,  304 ,  310 , and  314 . Control line DECC&lt;ODD&gt; is coupled to the DECC input of registers  306 ,  308 ,  314 , and  316 . Control line DECD&lt;EVEN&gt; is coupled to the DECD input of registers  302 ,  304 ,  310 , and  314 . Control line DECD&lt;ODD&gt; is coupled to the DECD input of registers  306 ,  308 ,  314 , and  316 . 
         [0032]    Except for the inputs of register  302  (the first register in the delay line) and the outputs of register  316  (the last register in the delay line) the coupling of registers  302 / 306 ,  306 / 310 ,  310 / 314 ,  314 / 304 ,  304 / 308 ,  308 / 312 ,  312 / 316  is now described. Output signal nodes A, B, C, and D in a first register are respectively coupled to signal input nodes PRVA, PRVB, PRVC, and PRVD in a second register. Output signal nodes AB, BB, CB, and DB in the second register are respectively coupled to signal input nodes NXTAB, NXTBB, NXTCB, and NXTDB in the first register. In register  302 , PRVA, PRVB, PRVC, and PRVD are coupled to VDD and AB, BB, CB, and DB are left open. In register  316 , NXTAB, NXTBB, NXTCB, and NXTDB are coupled to VDD and A, B, C, and D are left open. 
         [0033]    The clock signal for the delay line  300  shown in  FIGS. 3A-3D  is routed from the CLKOUT node of a first register to the CLKIN node of a second register in the following coupling of registers  302 / 304 ,  304 / 306 ,  306 / 308 ,  308 / 310 ,  310 / 312 ,  312 / 314 ,  314 / 316 . Note that register  302  initially receives the input clock signal at the CLKIN node, and the delayed clock signal is provided at the CLKOUT node of register  316 . 
         [0034]    Two separate increment controls (INCA&lt;EVEN&gt;, INCA&lt;ODD&gt;, for example) are used so the register automatically is configured as a master/slave and run-through is prevented. The same is true for the decrement control, two lines are used to make a master/slave configuration (DECA&lt;EVEN&gt;, DECA&lt;ODD&gt;, for example). It is important to note that when prompted to ‘increment,’ the increment control must alternate between Odd-Even stage increments. The same is true for decrement control. 
         [0035]    Another feature of the present invention is that the register does not increment in a truly linear fashion, but skips stages so ‘delay’ is not added in adjacent stages. Adding all the delay in adjacent stages, but none in other areas could lead to signal distortion resulting in duty cycle issues of no function at higher frequencies. This can be clearly seen by the physical layout of the registers  302 - 316  as is shown in  FIGS. 3A-3D . 
         [0036]    Any number of programmable delay stages can be used or added. A number that is a power of two ( 2   n ) is not necessary as is required in counter-controlled variable delay lines. 
         [0037]    Resetting is accomplished easily by forcing both increment control lines (INCA&lt;ODD&gt; and INCA&lt;EVEN&gt;, for example) high at the same time thus defeating the master/slave properties of the present invention and letting the desired state run (or progress) down the register chain. This is explained in further detail with respect to the timing diagram of  FIG. 10 . 
         [0038]    The implementation according to the present invention uses sixteen total delay stages. Delay is changed by modulating drive strength, essentially by adjusting pull-down and pull-up strength. 
         [0039]    Referring now to  FIG. 4 , two delay stages  400  and  402  are shown coupled together, forming a single register such as register  302  shown in  FIGS. 3A-3D . Delay stage  400  includes separate VC and VR temperature control nodes, not dependent upon a phase detector, received respectively by transistors M 17  and M 18 . In the embodiment shown in  FIG. 4 , the temperature controls are not actually used. Thus, the VC input is coupled to the VSS voltage supply, and the VR input is coupled to the VDD voltage supply. Temperature control of the register and the adjustable delay line is discussed in further detail below. Pull-up transistors include P-channel transistors M 25 , M 24 , and M 23 . The gate of transistor M 25  receives the VSS voltage, the gate of transistor M 24  receives the CB control signal, and the gate of transistor M 23  receives the DB control signal. Delay stage  400  also includes an inverter for receiving the input CLK signal and for providing an intermediate inverted CLK signal comprising P-channel transistor M 2  and N-channel transistor M 13 . Pull-down transistors include N-channel transistors M 6 , M 4 , and M 54 . The gate of transistor M 6  receives the VDD voltage, the gate of transistor M 4  receives the A control signal, and the gate of transistor M 54  receives the B control signal. The A, B, CB, and DB control signals are described in further detail below with respect to the latch circuits of  FIGS. 5-8 . 
         [0040]    Similarly, delay stage  402  includes separate VC and VR temperature control nodes, received respectively by transistors M 16  and M 19 . In the embodiment shown in  FIG. 4  the VC and VR controls are not actually used and are coupled to VSS and VDD, respectively. Pull-up transistors include P-channel transistors M 22 , M 14 , and M 21 . The gate of transistor M 22  receives the VSS voltage, the gate of transistor M 14  receives the BB control signal, and the gate of transistor M 21  receives the AB control signal. Delay stage  402  also includes an inverter for receiving the intermediate inverted CLK signal and for providing the output CLKOUT signal, comprising P-channel transistor M 15  and N-channel transistor M 12 . Pull-down transistors include N-channel transistors M 51 , M 52 , and M 53 . The gate of transistor M 51  receives the VDD voltage, the gate of transistor M 52  receives the C control signal, and the gate of transistor M 53  receives the D control signal. The C, D, BB, and AB control signals are described in further detail below with respect to the latch circuits of  FIGS. 5-8 . 
         [0041]    In the default state, in delay cell  400 , transistors M 24  and M 4  are ON, and transistors M 23  and M 54  are OFF. Similarly, the default state, in delay cell  402 , transistors M 14  and M 52  are ON, and transistors M 21  and M 53  are OFF. From the default state, transistor M 4  is turned off (as well as the equivalent transistor in successive registers if desired) to decrement (slow down) the delay line. (Transistor M 21  is switched in conjunction with the switching of transistor M 4 .) Similarly, from the default state transistor, M 54  is turned on (as well as the equivalent transistor in successive registers if desired) to increment (speed up) the delay line. (Transistor M 14  is switched in conjunction with the switching of transistor M 54 .) The CLK signal duty-cycle is adjusted by having the next stage use separate inputs (C and D) vs. (A and B) so that they control opposite edges of the clock being delayed. 
         [0042]    Delay line control requires a method for incrementing or decrementing the delay amount, while not having a traditional master/slave architecture. The delay line control is provided by a series of latches chained together such that each latch is dependent on the status of its neighboring latches in order to flip states. The latches are shown in  FIGS. 5 ,  6 ,  7 , and  8 . Thus, each of the registers shown in  FIGS. 3A-3D  includes delay cells  400  and  402 , and each of the latch circuits  500 ,  600 ,  700 , and  800  respectively shown in  FIGS. 5-8 . 
         [0043]    A first latch circuit  500  shown in  FIG. 5  comprises a latch including cross-coupled inverters  11  and  130  coupled between nodes AB and A. Cascoded N-channel transistors M 20  and M 36  are coupled between the AB node and ground. The gate of transistor M 20  is coupled to the INCA node, and the gate of transistor of M 36  is coupled to the PRVA node. Cascoded N-channel transistors M 37  and M 38  are coupled between the A node and ground. The gate of transistor M 37  is coupled to the DECA node, and the gate of transistor M 38  is coupled to the NXTAB node. 
         [0044]    A second latch circuit  600  shown in  FIG. 6  comprises a latch including cross-coupled inverters  127  and  131  coupled between nodes BB and B. Cascoded N-channel transistors M 41  and M 42  are coupled between the BB node and ground. The gate of transistor M 41  is coupled to the INCB node, and the gate of transistor of M 42  is coupled to the PRVB node. Cascoded N-channel transistors M 40  and M 39  are coupled between the B node and ground. The gate of transistor M 40  is coupled to the DECB node, and the gate of transistor M 39  is coupled to the NXTBB node. 
         [0045]    A third latch circuit  700  shown in  FIG. 7  comprises a latch including cross-coupled inverters  128  and  132  coupled between nodes CB and C. Cascoded N-channel transistors M 44  and M 43  are coupled between the CB node and ground. The gate of transistor M 44  is coupled to the INCC node, and the gate of transistor of M 43  is coupled to the PRVC node. Cascoded N-channel transistors M 45  and M 46  are coupled between the C node and ground. The gate of transistor M 45  is coupled to the DECO node, and the gate of transistor M 46  is coupled to the NXTCB node. 
         [0046]    A fourth latch circuit  800  shown in  FIG. 8  comprises a latch including cross-coupled inverters  129  and  133  coupled between nodes DB and D. Cascoded N-channel transistors M 48  and M 47  are coupled between the DB node and ground. The gate of transistor M 48  is coupled to the INCD node, and the gate of transistor of M 47  is coupled to the PRVD node. Cascoded N-channel transistors M 49  and M 50  are coupled between the D node and ground. The gate of transistor M 49  is coupled to the DECD node, and the gate of transistor M 46  is coupled to the NXTDB node. 
         [0047]    Timing diagrams  900  and  1000  are shown in  FIGS. 9 and 10 , which respectively describe a normal mode of operation, and a reset mode of operation. 
         [0048]    Referring now to  FIG. 9 , the normal operation mode timing diagram  900  is shown including the CLK input signal and the delayed CLK output signal. Also shown are the INCA&lt;EVEN&gt;, INCA&lt;ODD&gt;, DECA&lt;EVEN&gt;, and DECA&lt;ODD&gt; control signals. Also shown are A&lt;0&gt;, A&lt;1&gt;, A&lt;2&gt;, A&lt;3&gt;, and A&lt;4&gt;, which represent the different delay registers such as delay registers  302  and  304  shown in  FIGS. 3A-3D . 
         [0049]    At T 0  the Delayed CLK is behind the reference clock (CLK), and as the adjustment direction arrow shows, the INCA&lt;EVEN&gt; signal goes high to increment the A register chain and decrease the delay on the Delayed CLK. At T 1  the Delayed CLK is still behind the CLK, however, for this illustration, the adjustment controller has been set to a two clock filter, such that only after two consecutive times of being behind (or ahead) of the CLK will a correction be made. As a result of the filtering, which can be set to any amount, the correction is not performed at T 1 . At T 2  the Delayed clock is now matched with the CLK and no correction is needed. At T 3  the Delayed CLK is now ahead of CLK and so DECA&lt;ODD&gt; goes high to decrement the A register chain and increase the delay on Delayed CLK. At T 4  RESET has been asserted and the register chain goes into reset mode. 
         [0050]    Referring now to  FIG. 10 , the reset operation mode timing diagram  1000  is shown including the CLK input signal and the RESET signal. Also shown are the INCA&lt;EVEN&gt;, INCA&lt;ODD&gt;, DECA&lt;EVEN&gt;, and DECA&lt;ODD&gt; control signals. Also shown are A&lt;0&gt;, A&lt;1&gt;, A&lt;2&gt;, A&lt;3&gt;, and A&lt;4&gt;, as well as B&lt;0&gt;, B&lt;1&gt;, B&lt;2&gt;, B&lt;3&gt;, and B&lt;4&gt;, which also represent the different delay registers  302  and  304  shown in  FIGS. 3A-3D . 
         [0051]    At T 0  the system is in normal operation mode. At T 1  the (asynchronous) RESET signal is asserted high putting the chain into reset mode by setting INCA&lt;EVEN,ODD&gt; both high and DECB&lt;EVEN,ODD&gt; both high as well. When both EVEN and ODD of an increment or decrement are asserted at the same time the register chain ripples a ‘1’ through the chain if it was an increment or a ‘0’ if it was a decrement. At T 1  the A register chain ripples a ‘1’ because both INCA&#39;s are asserted, and the B register chain ripples a ‘0’ because both DECB&#39;s are asserted. At T 2  RESET is asserted low and the chain goes back into normal operation mode with the total delay in a balanced state allowing for equal amount of delay to be added or removed. 
         [0052]    In the present invention, the delay through the delay line is controlled by varying the power supply voltage. This is accomplished digitally via quantized steps. Having the delay line run at a different voltage than the main supply leads to timing errors due to level shifting and phase differences between the supplies. Having anything adjusted via quantized steps means there will be discrete shifts in the timing. The delay line of the present invention is constantly making slight analog adjustments so the any timing difference is not seen as a quantized difference. 
         [0053]    The delay line has two adjustment modes going on in parallel. The primary adjustment is digitally based and this is what is set on the initial locking of the delay line. The digital adjuster also continues to work throughout the operation of the delay line. The temperature adjuster continually works in the background and parallel to the main digital adjuster. This mitigates the issue of the delay starting and locking at one temperature, usually cold, and then having to run at a different temperature, usually hot, as the part continues into normal operation. If the main digital adjustment circuitry had to cover the initial locking, any frequency changes due to jitter, and the possible temperature shifts, the delay line would be too long and too many adjustment stages would be required. The longer the delay line, the greater the chance that error is introduced due to jitter within the line itself. 
         [0054]    Each leg within the basic delay element of the delay line has two adjustment modes in series. The first one being digitally controlled and responsive to a phase detector of some sort as has been previously described. The second one being only responsive to a temperature sensing circuit as is shown in  FIG. 11 .  FIG. 11  shows a temperature sensing and control circuit  1100 . The inputs to control circuit  1100  are the power supply voltages VDD and VSS, and are sensitive to the external temperature. The outputs of control circuit are the VC and VR temperature control voltages that are coupled to the VC and VR nodes shown in  FIG. 4 . Note that these nodes are coupled to VSS and VDD, respectively as these control nodes can be effectively disabled if not required, as many modern semiconductor processes are substantially temperature invariant. 
         [0055]    The programmable portion of the delay line which is set on initial locking as previously described may also contain this temperature compensation as is shown in  FIG. 11 . The result of which is very little delay change versus temperature throughout the entire delay line, not just the variable portion. 
         [0056]    In the embodiment of the present invention shown in  FIG. 4 , the voltage VR will change in response to temperature such that the delay will remain constant. VR is attached to the gate of an N-channel device within the delay elements. VC, which is attached to the gate of a p-channel device, may also change for added compensation range. 
         [0057]    Any number of circuits could be selected to generate the VR or VC control signal, such as any number of temperature sensitive circuits that are well known in the art. A general representative circuit  1100  is shown in  FIG. 11 . Some specific examples are solid state thermometers and bipolar transistor thermometers. 
         [0058]    In conclusion, a novel delay circuit for use in a DLL has been shown, which uses universal increment and decrement signals, is in conjunction with an even and odd signal. When incrementing the registers an increment signal is valid while the even/odd signal toggles. If the even signal is held valid and does not toggle with the odd signal then the register will not increment. The same is true for decrementing. As an increment occurs the registers then checks the status of the previous register, if it is not currently holding a logic ‘1’ then the register ignores the increment, while decrementing checks the status of the next latch. Each register is only dependent on its neighboring register allowing the addition or reduction in the amount of registers in the chain to be done on an individual basis. The ends of the delay chain are tied off to preset values. As the chain increments the number of logic 2&#39;s existent within the chain increases, while decrementing lowers that number. 
         [0059]    Referring now to  FIG. 12 , a block diagram of a DLL  1200  is shown including a feature for preventing the delay elements from being digitally controlled after an initial locking period. The block diagram includes an initial lock block  1202  and a linear progression/delay registers block  1208  coupled to the temperature control block  1204 . The CLK input signal (A) and the output (C) of block  1208  are received by the detect block  1206 . The output of detect block  1206  is fed back to block  1208 . The signal on node (C) is the output of the DLL  1200 . 
         [0060]    In  FIG. 12  the CLK signal goes into the initial lock block  1202 , which then turns on one of the switches  1210  to tap off from. One of 32 switches (only four are shown in  FIG. 12 ) will connect, tapping off from one point in the series of elements such that the input into the linear progression delay register sees only “x” (wherein “x” is less than 32) number of elements from the initial lock. The temperature control output (VR and VC) connects both to the linear progression delay registers and the initial lock. The phase detect output however only goes to the delay registers (this output is coupled to the INC and DEC inputs previously described). 
         [0061]    Although an embodiment of the present invention has been described for purposes of illustration, it should be understood that various changes, modifications and substitutions may be incorporated in the embodiment without departing from the spirit of the invention that is defined in the claims, which follow. For example, a single edge delay register such as only the “A” registers to control delay in only one element could be used. Skipping more than one element per increment/decrement is also contemplated. Many other variations of the INC and DEC signals are possible within the scope of the present invention.