Abstract:
The present invention proposes a circuit arrangement provided for five bit/six bit (=5 b/6 b) coding and decoding, an associated coding device as well as corresponding methods by means of which a high coded data transfer rate can be attained.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation of international (WO) patent application no. PCT/DE2013/200017, filed 27 May 2013, which claims the priority of German (DE) patent application no. 10 2012 104 573.9, filed 25 May 2012, the contents of each being hereby incorporated herein by reference. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The present invention principally relates to the technical field of optical and/or electrical, in particular serialised, signal connections; more specifically, the present invention relates to a circuit arrangement provided for five bit/six bit (=5 b/6 b) coding and decoding, an associated coding device as well as corresponding methods. 
       BACKGROUND OF THE INVENTION 
       [0003]    In order to obtain a D[irect]C[urrent]-balanced signal, coding and decoding methods of various bit widths are employed. The method best known is eight bit/ten bit (=8 b/10 b) coding and decoding. 8 b/10 b coding/decoding of this kind in most cases comprises a 5 b/6 b coding/decoding block and a 3 b/4 b coding/decoding block. 
         [0004]    The basis used for such 5 b/6 b blocks and for such 3 b/4 b block is, in the main, the instructions and the table by Albert X. Widmer (IBM Research Division). For the technological background we would like to draw your attention, as an example, to the prior art publication U.S. Pat. No. 6,911,921 B2 or the paper “8 B/10B Encoding and Decoding for High Speed Applications” published by Albert X. Widmer (IBM Research Division) on 21 Oct. 2004/3 Nov. 2004.  FIG. 1A  shows the 5 b/6 b coding table by Widmer. 
         [0005]    However, the circuit arrangements mentioned by Widmer and others are usable only up to certain bit rates, depending on the technology used, because with such conventional circuit arrangements the run times of many digital gates connected one behind the other add up. This prevents a high coded data transfer. 
       OBJECTS AND SUMMARY OF THE INVENTION 
       [0006]    Starting from the above-explained disadvantages and inadequacies as well as taking the outlined prior art into account the object of the present invention is to further develop a circuit arrangement provided for five bit/six bit (=5 b/6 b) coding or decoding, an associated coding device as well as corresponding methods in such a way that a high coded data transfer rate is achievable. 
         [0007]    This object is achieved by a circuit arrangement according to the invention with the herein described features, by a method according to the invention with the herein described features, by a coding device with the herein described features as well as by a coding method with the herein described features. Advantageous embodiments and expedient further developments of the present invention are described above and below. 
         [0008]    This object is achieved by a circuit arrangement for determining and providing
       a first information I 1− , that in a digital input word A B C D E comprising a first input bit A, a second input bit B, a third input bit C, a fourth input bit D and a fifth input bit E at most only one of the five input bits A, B, C, D, E comprises the value 1 (“high”),   a second information I 2 , that in the input word A B C D E exactly two of the five input bits A, B, C, D, E comprise the value 1 (“high”),   a third information I 3 , that in the input word A B C D E exactly three of the five input bits A, B, C, D, E comprise the value 1 (“high”) and   a fourth information I 4+ , that in the input word A B C D E at least four of the five input bits A, B, C, D, E comprise the value 1 (“high”),       
 
         [0013]    which circuit arrangement comprises:
       a first half-adder   with a first input port,   with a second input port,   with a master output port and   with a transfer output port,   a first full-adder   with a first input port,   with a second input port,   with a transfer input port,   with a master output port and   with a transfer output port,   a second half-adder   with a first input port,   with a second input port,   with a master output port and   with a transfer output port,   a second full-adder   with a first input port,   with a second input port,   with a transfer input port,   with a master output port and   with a transfer output port,   a NOR gate arranged downstream of the two half-adders as well as of the two full-adders   with a first input port,   with a second input port and   with an output port,   a first AND gate arranged downstream of the two half-adders as well as of the two full-adders   with an inverted or negated first input port,   with an inverted or negated second input port,   with a third input port and   with an output port,   a second AND gate arranged downstream of the half-adders as well as of the two full-adders   with an inverted or negated first input port,   with a second input port,   with a third input port and   with an output port as well as   a buffer member arranged downstream of the two half-adders as well as of the two full-adders   with an input port and   with an output port.       
 
         [0053]    This object is further achieved by an embodiment of the circuit arrangement according to the invention,
       wherein the first input bit A of the input word A B C D E can be applied to the first input port of the first half-adder,   wherein the second input bit B of the input word A B C D E can be applied to the second input port of the first half-adder,   wherein the third input bit C of the input word A B C D E can be applied to the first input port of the first full-adder,   wherein the fourth input bit D of the input word A B C D E can be applied to the second input port of the first full-adder and   wherein the fifth input bit E of the input word A B C D E can be applied to the transfer input port of the first full-adder.       
 
         [0059]    This object is further achieved by an embodiment of the circuit arrangement according to the invention,
       wherein the transfer output port of the first half-adder is connected with the first input port of the second full-adder,   wherein the master output port of the first half-adder is connected with the first input port of the second half-adder,   wherein the transfer output port of the first full-adder is connected with the second input port of the second full-adder,   wherein the master output port of the first full-adder is connected with the second input port of the second half-adder and   wherein the transfer output port of the second half-adder is connected with the transfer input port of the second full-adder.       
 
         [0065]    This object is further achieved by an embodiment of the circuit arrangement according to the invention,
       wherein the transfer output port of the second full-adder is connected with the first input port of the NOR gate,   wherein the master output port of the second full-adder is connected with the second input port of the NOR gate and   wherein the output port of the NOR gate provides the first information I 1− .       
 
         [0069]    This object is further achieved by an embodiment of the circuit arrangement according to the invention,
       wherein the transfer output port of the second full-adder is connected with the inverted or negated first input port of the first AND gate,   wherein the master output port of the second half-adder is connected with the inverted or negated second input port of the first AND gate,   wherein the master output port of the second full-adder is connected with the third input port of the first AND gate and   wherein the output port of the first AND gate provides the second information I 2 .       
 
         [0074]    This object is further achieved by an embodiment of the circuit arrangement according to the invention,
       wherein the transfer output port of the second full-adder is connected with the inverted or negated first input port of the second AND gate,   wherein the master output port of the second full-adder is connected with the second input port of the second AND gate,   wherein the master output port of the second half-adder is connected with the third input port of the second AND gate and   wherein the output port of the second AND gate provides the third information I 3 .       
 
         [0079]    This object is further achieved by an embodiment of the circuit arrangement according to the invention,
       wherein the transfer output port of the second full-adder is connected with the input port of the buffer member and   wherein the output port the buffer member provides the fourth information I 4+ .       
 
         [0082]    This object is further achieved by a method for determining and providing the first information I 1− , the second information I 2 , the third information I 3  and the fourth information I 4+  by means of the circuit arrangement. 
         [0083]    This object is further achieved by a coding device for encoding the input word A B C D E in a digital output word a b c d e i comprising a first output bit a, a second output bit b, a third output bit c, a fourth output bit d, a fifth output bit e and a sixth output bit i on the basis of the first information I 1− , the second information I 2 , the third information I 3  and the fourth information I 4+  provided by the circuit arrangement and/or by the method in accordance with the following coding assignment for the six output bits a, b, c, d, e, is 
         [0084]    a=A OR Set3; 
         [0085]    b=Set1 OR [B AND Set3_negiert]; 
         [0086]    c=C OR Set1 OR Set3 OR [1 IF ABCDE=00011]; 
         [0087]    d=D AND Set3_negiert; 
         [0088]    e=Set2 OR [E AND (1 IF ABCDE=00011)] OR [1 IF (I 1−  AND Set1_negiert)]; 
         [0089]    i=[1 IF ABCDE=11111] OR Set2 OR [1 IF (I 2  AND ABCDE=11100)], 
         [0090]    wherein Set1=(1 IF ABCDE=00000) OR (1 IF ABCDE=00001);
       Set1_negiert=(0 IF ABCDE=00000) OR (0 IF ABCDE=00001);   Set2=(1 IF ABCDE=11111) OR (1 IF ABCDE=00001);   Set3=(1 IF ABCDE=11111) OR (1 IF ABCDE=11110);   Set3_negiert=(0 IF ABCDE=11111) OR (0 IF ABCDE=11110).       
 
         [0095]    This object is further achieved by an embodiment of the coding device according to the invention, wherein a missing D[irect]C[urrent] balance or a missing direct current neutrality can be taken into account by means of at least one disparity DISP. 
         [0096]    This object is further achieved by an embodiment of the coding device according to the invention, wherein the disparity DISP is given by DISP=[I 1−  OR I 4+  OR ABCDE=11100 OR ABCDE=00011] XOR [ABCDE=11100 OR ABCDE=00001 OR ABCDE=11101 OR ABCDE=11011 OR [(A OR B) AND CDE=111]]. 
         [0097]    This object is further achieved by an embodiment of the coding device according to the invention, wherein the coding device
       is arranged downstream of the circuit arrangement and/or   is part of the circuit arrangement and/or   is constructed uniformly and/or in one piece with the circuit arrangement.       
 
         [0101]    This object is further achieved by a coding method for encoding the input word ABCDE into the output word a b c d e i by means of the coding device. 
         [0102]    This object is further achieved by a use of the circuit arrangement and/or of the method according to the invention when encoding five bit A, B, C, D, E wide digital signals into six bit a, b, c, d, e, i wide, D[irect]C[urrent]-balanced or direct-current-neutral transferable signals. 
         [0103]    This object is further achieved by an embodiment of the use according to the invention in serialised optical and/or electrical signal transfer and/or signal processing. 
         [0104]    According to the invention, using a five bit/six bit encoder architecture (5 b/6 b encoder architecture), a D[irect]C[urrent]-balanced optical and/or electrical, in particular serial data connection is provided. 
         [0105]    The present invention finally relates to the use of at least one circuit arrangement of the above-mentioned type and/or a method of the above-mentioned type for the coding of five-bit wide digital signals into six-bit wide D[irect]C[urrent] balanced or direct-current-neutral transferable signals, in particular in serialised optical and/or electrical signal transfer and/or signal processing. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0106]    As already discussed above, there are various possibilities for embodying and further developing the teaching of the present invention in an advantageous manner. For this purpose, on the one hand reference is made to the explanations above as well as to the dependent claims, and on the other hand further embodiments, features and advantages of the present invention are explained in greater detail below, inter alia by way of the exemplary embodiment illustrated by  FIG. 1B  to  FIG. 3F . 
           [0107]    It is shown in: 
           [0108]      FIG. 1A  an exemplary embodiment for an Albert X. Widmer (IBM Research Division) based 5 b/6 b coding table, by means of which five input bits can be converted into six output bits; 
           [0109]      FIG. 1B  an exemplary embodiment for an Albert X. Widmer (IBM Research Division) based 5 b/6 b coding table, which has been modified, in particular reduced, by means of which five input bits can be converted into six output bits and which can be put to use in the present invention; 
           [0110]      FIG. 2  in a conceptual schematic view an exemplary embodiment for a circuit arrangement according to the present invention which operates according to the method of the present invention; 
           [0111]      FIG. 3A  in a conceptual schematic view an exemplary embodiment for a first component of a 5 b/6 b coding device according to the present invention which operates according to the coding method of the present invention; 
           [0112]      FIG. 3B  in a conceptual schematic view an exemplary embodiment for a second component of a 5 b/6 b coding device according to the present invention which operates according to the coding method of the present invention; 
           [0113]      FIG. 3C  in a conceptual schematic view an exemplary embodiment for a third component of a 5 b/6 b coding device according to the present invention which operates according to the coding method of the present invention; 
           [0114]      FIG. 3D  in a conceptual schematic view an exemplary embodiment for a fourth component of a 5 b/6 b coding device according to the present invention which operates according to the coding method of the present invention; 
           [0115]      FIG. 3E  in a conceptual schematic view an exemplary embodiment for a fifth component of a 5 b/6 b coding device according to the present invention which operates according to the coding method of the present invention; and 
           [0116]      FIG. 3F  in a conceptual schematic view an exemplary embodiment for a sixth component of a 5 b/6 b coding device according to the present invention which operates according to the coding method of the present invention. 
       
    
    
       [0117]    Like or similar embodiments, elements or features are provided with identical reference numerals in  FIG. 1A  to  FIG. 3F . 
       DETAILED DESCRIPTION OF THE INVENTION 
       [0118]    By utilising certain circuit arrangements it is possible to achieve a data transfer which is increased when compared to the conventional Widmer 5 b/6 b coding table, for a five bit/six bit coding device (5 b/6 b encoder) according to the present invention, which operates according to the five bit/six bit coding method (5 b/6 b coding method) according to the present invention. 
         [0119]    In order to remain compatible with existing 5 b/6 b decoders the Widmer 5 b/6 b coding table of  FIG. 1A  is, albeit, regarded as a basis for this 5 b/6 b conversion, but it is used in a modified i.e. reduced form according to  FIG. 1B , wherein special signs such as K23 or K28 from  FIG. 1A  are disregarded. 
         [0120]    According to the embodiment shown in in  FIG. 2  initially a circuit arrangement Z is used for finding, i.e. for determining the number of zeros and the number of ones in the input word or input code word, wherein the input (code) word is a five-bit-wide digital signal. The circuit arrangement Z thus outputs the number of zeros and the number of ones present in the five-bit-wide input (code) word, wherein the five individual bits of these 5-bit-input (code) words are marked with the letters ABC D E in  FIG. 1B  and in  FIG. 2 . 
         [0121]    As shown in  FIG. 2  the circuit arrangement Z comprises, among others:
       a first half-adder HA 1     with a first input port x,   with a second input port y,   with a master output connection s and   with a transfer output port c out ,   a first full-adder FA 1     with a first input port x,   with a second input port y,   with a transfer input port c in ,   with a master output port s and   with a transfer output port c out ,   a second half-adder HA 2     with a first input port x,   with a second input port y,   with a master output port s and   with a transfer output port c out ,   a second full-adder FA 2     with a first input port x,   with a second input port y,   with a transfer output port c in ,   with a master output port s and   with a transfer output port c out .       
 
         [0144]    In this arrangement the half-adder HA 1 , HA 2  is a combinatorial circuit which is normally realised as a digital circuit. Each half-adder HA 1 , HA 2  allows two one-digit binary numbers to be added, wherefore each half-adder HA 1 , HA 2  comprises two inputs x, y. Each half-adder HA 1 , HA 2  comprises two outputs s, c out , i.e. a master output s for the result (=digital sum) of the two input signals and a transfer output c out  for the transfer or carry of the result according to the following truth table, which illustrates the mode of operation of the half-adder HA 1 , HA 2 : 
         [0145]    x=0, y=0→s=0, c out =0 
         [0146]    x=0, y=1→s=1, c out =0 
         [0147]    x=1, y=0→s=1, c out =0 
         [0148]    x=1, y=1→s=0, c out =1 
         [0149]    With regard to the mathematical function the half-adder HA 1 , HA 2  sets the master output s to 1, as soon as one of the two inputs x, y has a  1 . The transfer output c out  is set to one only if both inputs x, y have a 1. 
         [0150]    The full-adder FA 1 , FA 2  is a combinatorial circuit which is normally realised as a digital circuit. Each full-adder FA 1 , FA 2  allows three one-digit binary numbers to be added, wherefore one of the three inputs x, y, C in  is the transfer input C in . Each full-adder FA 1 , FA 2  comprises two outputs s, c out , i.e. a master output s for the lower-value digit of the result (=of the digital sum) of the three input signals and a transfer output c out  for the higher-value digit of the result, i.e. the transfer or carry of the result according to the following truth table, which illustrates the mode of operation of the full-adder FA 1 , FA 2  (the existence of the transfer input C in  as well as of the transfer output c out  allows overflow treatment in adding networks): 
         [0151]    x=0, y=0, c in =0→s=0, c out =0 
         [0152]    x=0, y=0, c in =1→s=1, c out =0 
         [0153]    x=0, y=1, c in =0→s=1, c out =0 
         [0154]    x=1, y=0, c in =0→s=1, c out =0 
         [0155]    x=0, y=1, c in =1→s=0, c out =1 
         [0156]    x=1, y=0, c in =1→s=0, c out =1 
         [0157]    x=1, y=1, c in =0→s=0, c out =1 
         [0158]    x=1, y=1, c in =1→s=1, c out =1 
         [0159]    With regard to the mathematical function the full-adder FA 1 , FA 2  sets the master output s to 1, as soon as one of the three inputs x, y, C in  has a 1. If two of the three inputs x, y, C in  have a 1, the transfer output c out  is set to 1. If all three inputs x, y, C in  have a 1, both outputs s and c out , i.e. both the master output s and the transfer output C out  are set to 1. 
         [0160]    According to  FIG. 2  the first bit A of the 5-bit input (code) word A B C D E is applied to the first input x of the first half-adder HA 1 . The second bit B of the 5-bit input (code) word A B C D E is applied to the second input y of the first half-adder HA 1 . 
         [0161]    Since the transfer output c out  of the first half-adder HA 1  is connected with the first input x of the second full-adder FA 2 , the transfer output signal of the first half-adder HA 1  is applied to the first input x of the second full-adder FA 2 . 
         [0162]    Since the master output s of the first half-adder HA 1  is connected with the first input x of the second full-adder FA 2 , the master output signal of the first half-adder HA 1  is applied to the first input x of the second half-adder HA 2 . 
         [0163]    The third bit C of the 5-bit input (code) word A B C D E is applied to the first input x of the first full-adder FA 1 . The fourth bit D of the 5-bit input (code) A B C D E is applied to the second input y of the first full-adder FA 1 . The fifth (last) bit E of the 5-bit input (code) word A B C D E is applied to the transfer input C in  of the first full-adder FA 1 . 
         [0164]    Since the transfer output c out  of the first full-adder FA 1  is connected with the second input y of the second full-adder FA 2 , the transfer output signal of the first full-adder FA 1  is applied to the second input y of the second full-adder FA 2 . 
         [0165]    Since the master output s of the first full-adder FA 1  is connected with the second input y of the second half-adder HA 2 , the master output signal of the first full-adder FA 1  is applied to the second input y of the second half-adder HA 2 . 
         [0166]    Since the transfer output c out  of the second half-adder HA 2  is connected with the transfer input C in  of the second full-adder FA 2 , the transfer output signal of the second half-adder HA 2  is applied to the transfer input C in  of the second full-adder FA 2 . 
         [0167]    As can further be seen in  FIG. 2 , the circuit arrangement Z comprises, among others:
       a NOR gate or NOR member NOR arranged downstream of the two half-adders HA 1 , HA 2  as well as of the two full-adders FA 1 , FA 2     with a first input port n 1 ,   with a second input port n 2  and   with an output port n out ,   a first AND gate or AND member AND 1  arranged downstream of the two half-adders HA 1 , HA 2  as well as of the two full-adders FA 1 , FA 2     with an inverted or negated first input port u 1 ,   with an inverted or negated second input port u 2 ,   with a third input port u 3  and   with an output port u out ,   a second AND gate or AND member AND 2  arranged downstream of the two half-adders HA 1 , HA 2  as well as of the two full-adders FA 1 , FA 2     with an inverted or negated first input port u 4 ,   with a second input port u 5 ,   with a third input port u 6  and   with an output port u out  as well as   a buffer member BUF provided for example for runtime compensation, arranged downstream of the two half-adders HA 1 , HA 2  as well as of the two full-adders FA 1 , FA 2     with an input port p in  and   with an output p out .       
 
         [0185]    This NOR gate or NOR member (=defined as an OR gate or OR member with inverted or negated output), these two AND gates or AND members AND 1 , AND 2  as well as this buffer member BUF are arranged downstream of the two half-adders HA 1 , HA 2  as well as of the two full-adders FA 1 , FA 2  as follows: 
         [0186]    Since the transfer output c out  of the second full-adder FA 2  is connected with the first input n 1  of the NOR member, the transfer output signal of the second full-adder FA 2  is applied to the first input n 1  of the NOR member. Since the master output s of the second full-adder FA 2  is connected with the second input n 2  of the NOR member, the master signal of the second full-adder FA 2  is applied to the second input n 2  of the NOR member. The output n out  of the NOR member supplies the information I 1− , that there is a one (=1) or less than a one (=1), in other words at most a one (=1) in the five-bit wide input (code) word A B C D E. 
         [0187]    Since the transfer output c out  of the second full-adder FA 2  is connected with the first input u 1  of the first AND member AND 1 , the transfer output signal of the second full-adder FA 2  is applied to the inverted or negated first input u 1  of the first AND member AND 1 . Since the master output s of the second half-adder HA 2  is connected with the inverted or negated second input u 2  of the first AND member AND 1 , the master signal of the second half-adder HA 2  is applied to the inverted or negated second input u 2  of the first AND member AND 1 . Since the master output s of the second full-adder FA 2  is connected with the third input u 3  of the first AND member AND 1 , the master signal of the second full-adder FA 2  is applied to the third input u 3  of the first AND member AND 1 . The output u out  of the first AND member AND 1  supplies the information I 2 , that there are two ones (=1) in the five-bit wide input (code) word A B C D E. 
         [0188]    Since the transfer output c out  of the second full-adder FA 2  is connected with the inverted or negated first input u 4  of the second AND member AND 2 , the transfer output signal of the second full-adder FA is applied to the inverted or negated first input u 4  of the second AND member AND 2 . Since the master output s of the second full-adder FA 2  is connected with the second input u 5  of the second AND member AND 2 , the master signal of the second full-adder FA 2  is applied to the second input u 5  of the second AND member AND 2 . Since the maser output s of the second half-Adder HA 2  is connected with the third input u 6  of the second AND member AND 2 , the master signal of the second half-adder HA 2  is applied to the third input u 6  of the second AND member AND 2 . The output u out  of the second AND member AND 2  supplies the information I 3 , that there are three ones (=1) in the five-bit wide input (code) word A B C D E. 
         [0189]    Since the transfer output c out  of the second full-adder FA 2  is connected with the input p in  of the buffer member BUF, the transfer output signal of the second full-adder FA 2  is applied to the input p in  of the buffer member BUF. The output p out  of the buffer member BUF supplies the information I 4+ , that there are four ones (=1) or more than four ones (=1), in other words at least four ones (=1), in the five-bit wide input (code) word A B C D E. 
         [0190]    The 32 5-bit input (code) words A B C D E are converted into 6-bit output words with the letters a, b, c, d, e i by means of the coding algorithm for the 5 b/6 b coding device according to the present invention, wherein in  FIG. 1B  the six individual bits of the 6-bit output words are marked with the letters a, b, c, d, e, i. 
         [0191]    To this end, as illustrated in the form of the coding scheme below, which is illustrated in  FIG. 3A  to  FIG. 3F , the 5 b/6 b coding device according to the present invention and the 5 b/6 b coding method according to the present invention access the information I 1− , information I 2 , information I 3 , information I 4+ provided by the circuit arrangement Z according to the present invention, wherein the circuit arrangement Z
       may be arranged upstream of the 5 b/6 b coding device and/or   may be part of the 5 b/6 b coding device and/or   may be constructed uniformly and/or in one piece with the 5 b/6 b coding device.       
 
         [0195]    In essence the 5 b/6 b coding method according to the present invention thus depicts incoming 5-bit words A B C D E via the exemplary coding table shown in  FIG. 1B  in the form of outgoing primary 6-bit symbols a b c d e i (=primary a b c d e i) as follows: 
         [0196]    a=A OR Set3. 
         [0197]    This coding instruction for the first bit a of the output symbol a b c d e i may be realised by means of logical switching elements shown by way of example in  FIG. 3A , which may represent a first component of the five bit/six bit coding device (5 b/6 b-coding device) according to the present invention. 
         [0198]    b=Set1 OR [B AND Set3_negiert]. 
         [0199]    This coding instruction for the second bit b of the output symbol a b c d e i may be realised by means of logical switching elements shown by way of example in  FIG. 3B , which may represent a second component of the five bit/six bit coding device (5 b/6 b-coding device) according to the present invention. 
         [0200]    c=C OR Set1 OR Set3 OR [1 IF ABCDE=00011]. 
         [0201]    This coding instruction for the third bit c of the output symbol a b c d e i may be realised by means of logical switching elements shown by way of example in  FIG. 3C , which may represent a third component of the five bit/six bit coding device (5 b/6 b-coding device) according to the present invention. 
         [0202]    d=D AND Set3_negiert. 
         [0203]    This coding instruction for the fourth bit d of the output symbol a b c d e i may be realised by means of logical switching elements shown by way of example in  FIG. 3D , which may represent a fourth component of the five bit/six bit coding device (5 b/6 b-coding device) according to the present invention. 
         [0204]    e=Set2 OR [E AND (1 IF ABCDE=00011)] OR [1 IF (I 1−  AND Set1_negiert)]. 
         [0205]    This coding instruction for the fifth bit e of the output symbol a b c d e i may be realised by means of logical switching elements shown by way of example in  FIG. 3E , which may represent a fifth component of the five bit/six bit coding device (5 b/6 b-coding device) according to the present invention. 
         [0206]    i=[1 IF ABCDE=11111] OR Set2 OR [1 IF (I 2  AND ABCDE=11100)]. 
         [0207]    This coding instruction for the sixth bit a of the output symbol a b c d e i may be realised by means of logical switching elements shown by way of example in  FIG. 3F , which may represent a sixth component of the five bit/six bit coding device (5 b/6 b-coding device) according to the present invention. 
         [0208]    In this arrangement 
         [0209]    Set1=(1 IF ABCDE=00000) OR (1 IF ABCDE=00001), 
         [0210]    and therefore 
         [0211]    Set1_negiert=(0 IF ABCDE=00000) OR (0 IF ABCDE=00001); 
         [0212]    Set2=(1 IF ABCDE=11111) OR (1 IF ABCDE=00001); 
         [0213]    Set3=(1 IF ABCDE=11111) OR (1 IF ABCDE=11110), 
         [0214]    and therefore 
         [0215]    Set3_negiert=(0 IF ABCDE=11111) OR (0 IF ABCDE=11110), 
         [0216]    wherein 
         [0217]    Set1_negiert may also be called Set1_invertiert and 
         [0218]    Set3_negiert may also be called Set3_invertiert. 
         [0219]    Using this primary coding algorithm for the 5 b/6 b-encoder according to the present invention, of the 32 input (code) words A B C D E to be transferred, a part is converted into the 6-bit output symbols or output words a b c d e i, which contain an identical number of zeros and ones, i.e. respectively three zeros and three ones, and which, as a result, can be balanced or D[irect]C[urrent] balanced or D[irect]C[urrent] neutral, i.e. can be transferred in a direct-current-neutral manner. 
         [0220]    Therefore, as an example, according to the coding table in  FIG. 1B  nineteen of the  32  5-bit input (code) words ABCDE to be transferred are converted into 6-bit output symbols a b c d e i which are transferable in a direct-current-neutral manner. 
         [0221]    The remain part of the  32  5-bit input (code) words ABCDE to be transferred are converted into 6-bit output symbols abode i, which do not contain an identical number of zeros and ones but
       either four zeros and two ones   or two zeros and four ones       
 
         [0224]    and are therefore called unbalanced or D[irect]C[urrent] unbalanced or not D[irect]C[urrent] neutral, i.e. taken on their own, would not be transferable in a direct-current-neutral manner. 
         [0225]    Therefore, as an example, according to the coding table in  FIG. 1B , thirteen of the  32  5-bit input (code) words ABCDE to be transferred are converted into 6-bit output symbols a b c d e i which are transferable in a manner which is not direct-current-neutral. Thus there are two possible output symbols or output words, i.e. primary a b c d e i and alternate a b c d e i according to  FIG. 1B  for these thirteen input symbols A B C D E. 
         [0226]    Whether
       the first or primary output symbol or output (code) word, i.e. primary a b c d e i, or   the second or alternative output symbol or output (code) word, i.e. alternate a b c d e i (=inverse or negation of the respective primary a b c d e i according to  FIG. 1B ),       
 
         [0229]    is used, depends on the respectively previously sent unbalanced output symbol. 
         [0230]    With regard to the second or alternative output symbol or output (code) word alternate a b c d e i the disparity DISP is taken into account which is formed as follows: 
         [0231]    DISP=[I 1−  OR I 4+  OR ABCDE=11100 OR ABCDE=00011] XOR [ABCDE=11100 OR ABCDE=00001 OR ABCDE=11101 OR ABCDE=11011 OR [(A OR B) AND CDE=111]]. 
         [0232]    From a circuit-technical point of view the XOR-instruction can be realised for example by an [e]X[clusive ]OR gate or [e]X[clusive ]OR member. 
         [0233]    Depending on the result of this ascertained disparity DISP
       either the first or primary output symbol or output (code) word (=primary a b c d e i)   or the second or alternative output symbol or output (code) word (=alternate a b c d e i)
 
is selected and used, in order to compensate for or balance the missing D[irect]C[urrent] balance or missing direct current neutrality.
       
 
         [0236]    By using the above-described coding algorithm for the 5 b/6 b encoder according to the present invention it is possible to achieve a higher coded data transfer than with conventional solutions. 
       LIST OF REFERENCE NUMERALS 
       [0000]    
       
         
           
             a first bit of the output code word or output word a b c d e i 
             A first input bit or input code word or input word A B C D E 
             AND 1  first AND gate or first AND member 
             AND 2  second AND gate or second AND member 
             b second input bit of the output code word or output word a b c d e i 
             B second input bit of the input code word or input word A B C D E 
             BUF buffer member 
             c third output bit of the output code word or output word a b c d e i 
             C third input bit of the input code word or input word A B C D E 
             c in  third input port or transfer input port of the full-adder FA 1 , FA 2   
             c out  transfer output port of the full-adder FA 1 , FA 2  or the half-adder HA 1 , HA 2   
             d fourth output bit of the output code word or output word a b c d e i 
             D fourth input bit of the input code word or input word A B C D E 
             DISP disparity 
             e fifth output bit of the output code word or output word a b c d e i 
             E fifth or last input bit of the input code word or input word A B C D E 
             FA 1  first full-adder 
             FA 2  second full-adder 
             HA 1  first half-adder 
             HA 2  second half-adder 
             i sixth or last output bit of the output code word or output word a b c d e i 
             I 1−  first information, that there is one one or no one in the input code word or input word A B C D E 
             I 2  second information, that there are two ones in the input code word or input word A B C D E 
             I 3  third information, that there are three ones in the input code word or input word A B C D E 
             I 4+  fourth information, that there are four ones or five ones in the input code word or input word A B C D E 
             NOR NOR gate or NOR member 
             n out  output port of the NOR gate or NOR member NOR 
             n 1  first input port of the NOR gate or NOR member NOR 
             n 2  second input port of the NOR gate or NOR member NOR 
             p in  input port of the buffer member BUF 
             p out  output port of the buffer member BUF 
             s master output port of the full-adder FA 1 , FA 2  or the half-adder HA 1 , HA 2   
             u 1  inverted or negated first input port of the first AND gate or AND member AND 1   
             u 2  inverted or negated second input port of the first AND gate or AND member AND 1   
             u 3  third input port of the first AND gate or AND member AND 1   
             u 4  inverted or negated first input port of the second AND gate or AND member AND 2   
             u 5  second input port of the second AND gate or AND member AND 2   
             u 6  third input port of the second AND gate or AND member AND 2   
             u out  output port of the first AND gate or AND member AND 1  or of the second AND gate or AND member AND 2   
             x first input port of the full-adder FA 1 , FA 2  or of the half-adder HA 1 , HA 2   
             y second input port of the full-adder FA 1 , FA 2  or of the half-adder HA 1 , HA 2   
             Z circuit arrangement 
           
         
       
     
         [0279]    While this invention has been described as having a preferred design, it is understood that it is capable of further modifications, and uses and/or adaptations of the invention and following in general the principle of the invention and including such departures from the present disclosure as come within the known or customary practice in the art to which the invention pertains, and as may be applied to the central features hereinbefore set forth, and fall within the scope of the invention.