Abstract:
The present invention discloses a circuit for eliminating speaker crackle during turning on or off a power amplifier and a method for the same, particularly to a circuit and method, wherein an input capacitor is used to pre-charge an output capacitor to reduce speaker crackle to an inaudible level during turning on or off a power amplifier. The present invention has a low cost and a simplified design without the penalty of bandwidth.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a circuit for eliminating speaker crackle during turning on or off power amplifier and a method for the same, particularly to a circuit and method, wherein a charging voltage of an input capacitor is used to pre-charge an output capacitor to reduce speaker crackle to an inaudible level during turning on or off a power amplifier. 
         [0003]    2. Description of the Related Art 
         [0004]    In the digital world nowadays, the usage of speaker is no less than any other electronic elements. Speakers are used in computers, televisions and many other multimedia devices. Moreover, some people do not hesitate to spend a lot in upgrading their speaker systems to achieve better audio quality. However, users often hear cracking noise during turning on or off their speaker-containing electronic devices. A long term speaker crackle may not only damage speakers but also hurt audition. 
         [0005]    In conventional methods for overcoming speaker crackle, the amplifier will not output audio signal until the voltages of related capacitors are stabilized. Refer to  FIG. 1  for a circuit of a conventional technology. When the power supply is turned on, the voltage of the power supply will rise from zero to Vcc. In this stage, the output capacitor Cout begins to be charged via two voltage-division resistors R. The equation of charging current is 
         [0000]        I =( Vcc/R ) e   −t/0.5RCout . 
         [0000]    wherein the initial value (the peak value) of the charging current is I peak =V cc /R, and the charging time constant is 0.5RC out . The charging resistance R is much greater than the resistance of speaker load; therefore, speaker load can be neglected in the preceding equation. 
         [0006]    In a common audio amplifier, the low frequency −3 db point is required to be less than 20 Hz. The relationship of the frequency of the low frequency −3 db point, speaker impedance and output capacitance Cout is f −3 db =1/(2πR spk C out ), wherein R spk  denotes speaker impedance. For a 4 ohm speaker, an output capacitance of 200 uF (C out =1/(2πR spk f −3 db )=1/(2π×4×20)=200 uF) is needed to meet the requirement of the low frequency −3 db point. Therefore, output capacitance has to reach as high as 2000 uF to solve the problem of bandwidth. 
         [0007]    For reducing the peak charging current I peak =V cc /R, R should be as great as possible. Suppose the voltage of the power supply is 5V. If the peak current is to be reduced to less than 1 mA, R=V cc /I peak =5V/1 mA=5 k ohms. The voltage equation of capacitor charging is 
         [0000]        V=Vcc/ 2(1 −e   −t/0.5RCout ). 
         [0008]    If the output capacitor Cout is to be charged to have a voltage of 99% of Vcc/2, 
         [0000]      ( V   cc /2)×99%= V   cc /2(1 −e   −t/0.5RCout ), i.e., 
         [0000]      (5V/2)×0.99=5V/2(1 −e   −t/0.5RCount ). 
       Thus, 
       [0009]    
       
         
           
             
               
                 
                   t 
                   = 
                   
                     
                       
                         - 
                         0.5 
                       
                        
                       
                         RC 
                         out 
                       
                       × 
                       
                         ln 
                          
                         
                           ( 
                           0.01 
                           ) 
                         
                       
                     
                     = 
                     
                       2.3 
                        
                       
                         RC 
                         out 
                       
                     
                   
                 
               
             
             
               
                 
                   = 
                   
                     2.3 
                     × 
                     5 
                      
                     k 
                      
                     
                         
                     
                      
                     ohms 
                     × 
                     2000 
                      
                     uF 
                   
                 
               
             
             
               
                 
                   = 
                   
                     23 
                      
                     
                         
                     
                      
                     
                       seconds 
                       . 
                     
                   
                 
               
             
           
         
       
     
         [0010]    Consequently, for reducing crackle current to less than 1 mA and reaching 99% of charging voltage, the waiting time must be longer than 23 seconds. However, a rational waiting time should be less than 3-5 seconds. Thus, crackle current will rise to 5-8 mA. Therefore, designers have to compromise between crackle volume and waiting time. 
         [0011]    After the waiting time or delay time, the output of the amplifier is turned on, and a voltage of Vcc/2 is sent to Cout. If the delay time is not long enough or Cout voltage is not close to Vcc/2, a second crackle will appear because the voltage of Vcc/2 output by the amplifier will create a great instant charging current to rapidly charge Cout to Vcc/2 compulsively. 
         [0012]    In addition to the charging crackle of the output capacitor, the input capacitor also has the problem of charging crackle. Refer to  FIG. 2  for a circuit of another conventional technology. The input capacitor Cin is also constrained by the −3 db requirement, wherein f −3 db =½πR in C in . In the schemes proposed by MAXIM Co. (MAX9715, page 8) and Philips Semiconductor (TDA 8932, page 16), the output stage of the amplifier is not turned on until the input charging circuit and the output charging circuit are stabilized. Similar to the abovementioned technology, such a method also requires a long waiting period. 
         [0013]    To solve the abovementioned problems, the present invention proposes a novel circuit for eliminating speaker crackle during turning on or off a power amplifier, wherein a charging voltage is used as an input signal, and whereby speaker crackle can be reduced without the penalty of bandwidth. 
       SUMMARY OF THE INVENTION 
       [0014]    The primary objective of the present invention is to provide a circuit for eliminating speaker crackle during turning on or off power amplifier and a method for the same, particularly a circuit and method, wherein a charging voltage of an input capacitor is used as an input signal to smooth pre-charge an output capacitor to reduce speaker crackle to an inaudible level during turning on or off a power amplifier. 
         [0015]    The circuit of the present invention comprises: a control unit, at least one switch, an amplifier and a low pass LC filter. The control unit detects the power supply voltage to determine actions and sends control signals to the switches and the amplifier according to circuit requirements. The switches receive the control signals to control the charging and discharging of the capacitors inside the circuit. The amplifier amplifies input signals or input voltage and outputs the amplified signals to the low pass LC filter. The filtered signals are sent to a speaker device. When the circuit is turned on, the control unit sends a control signal to the switch to let an input capacitor Cin begin to be charged. The charging signal is directly amplified to drive the speaker device. The charging voltage for the input capacitor is a gradually rising voltage, and the time constant is (Rs+Rin)×Cin. After being amplified by the amplifier, the gradually rising voltage becomes a gradually rising output voltage. The gradually rising output voltage smooth charges an output capacitor Cout. Thus, the smooth charging replaces a high-peak pre-charging, wherein I peak =Vcc/R. Then, the turn-on crackle is reduced. When the control unit detects a turn-off signal, the capacitor, which has been charged, is discharged by the discharge circuit inside the amplifier and then standby for a smooth charging in the next starting. 
         [0016]    In the case of an input resistor with 20K ohm, which is a typical value for most audio amplifiers, and an input capacitor with 1 uF, the −3 db frequency of the input circuit is 1/(2π×20 k×1 u)=8 Hz. In other words, only a small capacitor of 1 uF is enough to achieve an 8 Hz low frequency bandwidth. Generally, the frequency response of a speaker or the audition range of human ears is above 20 Hz. If the charging rate of the output capacitor is smaller than that a speaker can present or human ears can sense, no crackle can be perceived by users. Therefore, if a charging voltage is generated at a bandwidth of 8 Hz, the charging will not create audible crackle. Additionally, in such a charging method, musical signal can also be input even though the capacitors have not been charged to a pre-determined voltage. The charging curve of the input circuit is expressed by 
         [0000]        V=V   cc /2(1 −e   −t/RinCin ) 
         [0000]    Let Rin=20 k ohms and Cin=1 uF. Thus, the charging voltage at Vcc=5 volts is 
         [0000]    
       
         
           
             
               
                 
                   V 
                   = 
                   
                     
                       5 
                       / 
                       2 
                     
                      
                     
                       ( 
                       
                         1 
                         - 
                         
                            
                           
                             
                               
                                 - 
                                 t 
                               
                               / 
                               20 
                             
                              
                             kx 
                              
                             
                                 
                             
                              
                             1 
                              
                             
                                 
                             
                              
                             u 
                           
                         
                       
                       ) 
                     
                   
                 
               
             
             
               
                 
                   = 
                   
                     2.5 
                      
                     
                       ( 
                       
                         1 
                         - 
                         
                            
                           
                             
                               
                                 - 
                                 t 
                               
                               / 
                               20 
                             
                              
                             m 
                           
                         
                       
                       ) 
                     
                   
                 
               
             
           
         
       
     
         [0000]    If the capacitor is charged to have a voltage of 99% Vcc, 
         [0000]      5/2×99%=5/2(1 −e   −t/20 m ), and 
         [0000]      0.99=1 −e   −t/20 m . 
         [0000]    In other words, 
         [0000]    
       
         
           
             
               
                 
                   t 
                   = 
                   
                     
                       - 
                       20 
                     
                      
                     m 
                     × 
                     ln 
                      
                     
                         
                     
                      
                     0.01 
                   
                 
               
             
             
               
                 
                   = 
                   
                     0.092 
                      
                     
                         
                     
                      
                     
                       seconds 
                       . 
                     
                   
                 
               
             
           
         
       
     
         [0000]    In such a case, the difference between the charging voltage and Vcc/2 is 
         [0000]      5V/2−5V/2×99%=0.025V. 
         [0000]    Ordinarily, the voltage gain of a power amplifier is about 10×. Thus, 0.025V will be amplified into 0.25V. This small voltage is added upon music signal and it continues to reduce to zero voltage slowly. therefore, the quality of the music will not be affected at all. In the present invention, the waiting time is only 0.1 second and no second crackle is occurred. 
         [0017]    Below, the embodiments of the present invention are described in detail in cooperation with the attached drawings to make easily understood the objectives, technical contents, characteristics and accomplishments of the present invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0018]      FIG. 1  is a diagram schematically showing a circuit of a conventional technology; 
           [0019]      FIG. 2  is a diagram schematically showing a circuit of another conventional technology; 
           [0020]      FIG. 3  is a diagram schematically showing a circuit according to the present invention; and 
           [0021]      FIG. 4  is a timing diagram of a circuit according to the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0022]    The present invention proposes a circuit for eliminating speaker crackle during turning on or off a power amplifier and a method for the same, wherein a charging voltage of an input capacitor is used as an input signal to smooth pre-charge an output capacitor to reduce speaker crackle to an inaudible level. Please refer to  FIG. 3  for a circuit according to the present invention. The output terminal of a signal source  1  has a signal source resistor Rs  2 . The signal source resistor Rs  2  is coupled to a switch transistor NMOS 2   3  and an input capacitor Cin  4 . One terminal of the switch transistor NMOS 2   3  is coupled to the system ground; therefore, when the switch transistor NMOS 2   3  is turned on, the input signal is short-circuited to the system ground. Thus a speaker  11  does not receive any input signal. The input capacitor Cin  4  is coupled to a switch transistor NMOS 1   5  and an input resistor Rin  6 . One terminal of the switch transistor NMOS 1   5  is also coupled to the system ground; therefore, when the switch transistor NMOS 1   5  is turned on, the voltage of the input capacitor Cin  4  is also short-circuited to the system ground. The input resistor Rin  6  is coupled to the input terminal of an amplifier  7 . Both the switch transistors NMOS 2   3  and NMOS 1   5  are metal oxide semiconductors. The switch transistor NMOS 2   3 , the switch transistor NMOS 1   5  and the amplifier  7  are coupled to a control unit  8 . The control unit  8  detects the voltage of the power supply to determine actions and sends control signals to control the switch transistor NMOS 2   3 , the switch transistor NMOS 1   5  and the amplifier  7 . The output terminal of the amplifier  7  is coupled to a low pass LC filter  9 . The output terminal of the Low pass LC filter  9  is coupled to an output capacitor Cout  10 . The output capacitor Cout  10  is coupled to a speaker device  11 . To make the present invention easily understood, the present invention will be demonstrated with the voltage variations at Point A behind the input capacitor Cin  4 , Point B at the output terminal of the amplifier  7  and Point C at the output terminal of the low pass filter  9 . Please refer to  FIG. 4  for a timing diagram of the circuit shown in  FIG. 3 . Before the power supply is turned on, all signals are at a ground voltage. During the rising stage of the power supply voltage Vcc, i.e., during t 1 -t 2 , the voltages of control signals SW 1  and SW 2  also rise with the power supply voltage. Thus, the switch transistors NMOS 2   3  and NMOS 1   5  are at a turn-on state, and both ends of the input capacitor Cin  4  is at the ground voltage. When the power supply voltage Vcc rises to a given value at t 2 , SDNB signal is shifted from the ground voltage to a high level voltage and turns on the amplifier  7 . At the same time, the control signal SW 1  is shifted to the ground voltage and turns off the switch transistor NMOS 1   5 . Thus, the internal voltage of the amplifier  7  charges the input capacitor Cin  4  via the input resistor Rin  6 , and the voltage variation at Point A is shown in  FIG. 4 . The amplifier  7  outputs PWM (Pulse Width Modulation) signals to Point B in response to the voltage of Point A. At this stage (t 2  to t 3 ), as the power supply voltage Vcc is still rising, the amplitudes of the PWM signals are also increasing. Further, the voltage of Point A is a gradually rising voltage and has a small duty cycle on the PWM signals or the PWM has small pulse width. These two factors result in that the PWM signals at Point B have gradually rising amplitude and gradually increasing pulse widths. After passing through the low pass LC filter  9 , the signals of Point B become the signal of Point C, which is a gradually rising voltage signal and used to charge the output capacitor Cout  10 . After the charging is completed at t 3 , the control signal SW 2  is shifted from a high level voltage to the ground voltage and turns off the switch transistor NMOS 2   3 . Thus, the signals of the signal source  1  are transmitted to the amplifier  7  via the signal source resistor Rs  2  and the input resistor Rin  6 . At this stage, the entire circuit enters a normal operation state. As shown in  FIG. 4 , the timing t 3  does not necessarily coincide with the timing that the charging voltage of Point A has become stable. 
         [0023]    When the power supply is turned off, the power supply voltage Vcc begins to descend at the same time as from t 4  to t 5 , the amplifier  7  is driven by a lower working voltage and outputs signals with lower amplitudes at Point B. Thus, the voltage of Point C behind the low pass LC filter  9  is also decreasing. When the power supply voltage Vcc descends to a given value at t 4 , the SDNB signal is shifted from a high level voltage to a low level voltage to turn off the amplifier  7  and start the internal discharge circuit of the amplifier  7 . Then, Point B is discharged by the internal discharge circuit of the amplifier  7 . At the same time, the control signal SW 2  is shifted from a low level voltage to a high level voltage to turn on the switch transistor NMOS 2   3  and short-circuit the signals of the signal source  1  to the system ground via the signal source resistor Rs  2 . Thus, the input signal is no more transmitted to the amplifier  7 . At this stage, the power supply voltage Vcc has been a low voltage. Thus, the discharging current at Point B or Point C also becomes relatively smaller, and the speaker It will not generate turn-off crackle. At the same timing t 4 , the control signal SW 1  is also shifted from a low level voltage to a high level voltage and turns on the switch transistor NMOS 1   5 . Thus, Point A is rapidly discharged to the ground voltage for the next starting up. The turn-on of the switch transistor NMOS 1   5  results in that a low voltage is input to the amplifier  7 . However, the amplifier  7  has been closed at this time. Thus, the speaker  11  cannot generate crackle any more. At t 5 , the entire circuit is restored to the system ground and standby for restart. 
         [0024]    A class D power amplifier is used to exemplify the amplifier in the above description. However, the same principle can also apply to other types of power amplifiers, such as a class AB power amplifier. 
         [0025]    Those described above are only the preferred embodiments to exemplify the present invention but not to limit the scope of the present invention. Any equivalent modification or variation according to the shapes, structures, features and spirit disclosed in the specification is to be also included within the scope of the present invention.