Abstract:
A power semiconductor device package utilizes integral fluid conducting micro-channels, one or more inlet ports for supplying liquid coolant to the micro-channels, and one or more outlet ports for exhausting coolant that has passed through the micro-channels. The semiconductor device is mounted on a single or multi-layer circuit board having electrical and fluid interconnect features that mate with the electrical terminals and inlet and outlet ports of the device to define a self-contained and self-sealed micro-channel heat exchanger.

Description:
RELATED APPLICATIONS  
       [0001]     This is a continuation-in-part of co-pending U.S. patent application Ser. No.  10 /______ (Attorney Docket No. DP-310178), filed on May ______, 2004, and assigned to the assignee of the present invention. 
     
    
     TECHNICAL FIELD  
       [0002]     The present invention relates to fluid cooling of power electronics, and more particularly to power semiconductor device packages having integral fluid cooling channels.  
       BACKGROUND OF THE INVENTION  
       [0003]     Various types of cooling mechanisms can be used to remove waste heat from high power semiconductor devices such as power FETs and IGBTs. In cases where the waste heat and/or the ambient temperature are very high, the power devices can be mounted on a liquid-cooled heat exchanger or cold plate. The cold plate has internal fluid conducting channels and inlet and outlet pipes for coupling it to a cooling system including a fluid reservoir, a pump and an external heat exchanger. Due to limited thermal conduction between the power devices and the cold plate, the cold plate must be relatively large and the pump must be capable of producing high fluid flow. As a result, such cooling systems tend to be too large, too heavy and too expensive for many applications. Accordingly, what is needed is an easily-packaged, cost-effective way of cooling high power semiconductor devices.  
       SUMMARY OF THE INVENTION  
       [0004]     The present invention is directed to an improved power semiconductor device package having integral fluid conducting micro-channels, an inlet port for receiving liquid coolant, and an outlet port for exhausting coolant that has passed through the micro-channels. The device is mounted on a single or multi-layer circuit board having electrical and fluid interconnect features that mate with the electrical terminals and inlet and outlet ports of the device to define a self-contained and self-sealed micro-channel heat exchanger. Integral fluid cooling eliminates the thermal gap media such as pads or thermal grease between semiconductor devices and heat exchangers, resulting in lower thermal resistance and lower package cost. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0005]      FIGS. 1A-1B  depict a semiconductor chip according to this invention.  FIG. 1A  depicts an upper surface of the chip, while  FIG. 1B  depicts a lower surface of the chip.  
         [0006]      FIG. 2A  depicts an upper ceramic substrate that interfaces with the upper surface of the chip of  FIGS. 1A-1B .  
         [0007]      FIG. 2B  depicts a lower ceramic substrate that interfaces with the lower surface of the chip of  FIGS. 1A-1B .  
         [0008]      FIG. 3A  is a sectional diagram of a semiconductor power device package according to the present invention, including the semiconductor chip of  FIGS. 1A-1B , the upper and lower substrates of  FIGS. 2A-2B , and a single or multi-layer circuit board, taken along section lines A-A of  FIGS. 2A-2B .  
         [0009]      FIG. 3B  is a sectional view of the package of  FIG. 3A  taken along section lines B-B of  FIG. 3A .  
         [0010]      FIGS. 4A-4C  depict a first alternate mechanization of this invention.  FIG. 4A  depicts an upper surface of the circuit board,  FIG. 4B  is a sectional view of the circuit board taken along section lines C-C  FIG. 4A , and  FIG. 4C  is a cross-sectional diagram of the package mechanization taken along section lines C-C  FIG. 4A .  
         [0011]      FIGS. 5A-5B  depict a second alternate mechanization of this invention where micro-channels are formed in the upper substrate.  FIG. 5A  depicts an upper surface of the circuit board, and  FIG. 5B  is a cross-sectional diagram of the package mechanization taken along section lines D-D of  FIG. 5A .  
         [0012]      FIG. 6  depicts a third alternate mechanization this invention, where micro-channels are formed in the ceramic of the lower substrate of  FIG. 2B .  
         [0013]      FIG. 7  depicts a fourth alternate mechanization this invention, where micro-channels are formed in a metallization layer on the bottom of the lower substrate of  FIG. 2B .  
         [0014]      FIG. 8  depicts an application of the present invention to a semiconductor power device package in which a semiconductor chip is sealingly mounted to a metal substrate and over-molded with plastic. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0015]     In general, the present invention is directed to power semiconductor device packages including a power semiconductor device with integral fluid conducting micro-channels and a mating single or multi-layer substrate having features that define electrical and fluid interconnects with the semiconductor device. While the method of the present invention may be applied to various types of power semiconductor packages, it is primarily disclosed herein in the context of a power semiconductor package where a semiconductor chip is sandwiched between upper and lower substrates, and the lower substrate is mated to a single or multi-layer circuit board. The integral micro-channel cooling features of this invention may be formed in the semiconductor chip itself as shown in the embodiments of  FIGS. 1-4 , in the upper substrate as shown in the embodiment of  FIG. 5 , or in or on the bottom substrate as shown in the embodiments of  FIGS. 6-7 .  FIG. 8  depicts an alternate power semiconductor package in which a semiconductor chip is sealingly mounted to a substrate and over-molded with plastic; in this case, the integral micro-channel cooling features of this invention are formed in the semiconductor chip, as in the embodiments of  FIGS. 1-4 .  
         [0016]     Referring to  FIGS. 1A-1B ,  2 A- 2 B and  3 A- 3 B, the reference numeral  10  generally designates a three-terminal semiconductor chip such as a power field-effect transistor (FET). A first major surface of the chip  10  (referred to herein as the upper surface  10   a ) is depicted  FIG. 1A , while a second major surface of the chip  10  (referred to herein as the lower surface  10   b ) is depicted in  FIG. 1B . The upper surface  10   a  is generally planar and supports two solderable conductor pads  12   a ,  12   b . The pad  12   a  is internally connected to the FET source, while the pad  12   b  is internally connected to the FET gate. The lower surface  10   b  is partially recessed in inactive regions of the chip  10  by an etching or similar process to define a number of parallel micro-channels  14 . The un-recessed portions of the surface  10   b  include a marginal region  16   a  and a plurality of walls  16   b  between adjacent micro-channels  14 . The marginal region  16   a  and the ends of walls  16   b  lie in the same plane, and are covered with solderable conductor segments  18  that are each internally connected to the FET drain.  
         [0017]     The semiconductor chip  10  is sandwiched between a pair of ceramic substrates  20 ,  22  as best seen in  FIG. 3A . The substrate  20  contacts the upper major surface  10   a  of the chip  10  and is referred to herein as the upper substrate; its chip-contacting face  20   a  is depicted in  FIG. 2A . The substrate  22  contacts the lower major surface  10   b  of the chip  10  and is referred to herein as the lower substrate; its chip-contacting face  22   a  is depicted in  FIG. 2B .  
         [0018]     Referring to  FIG. 2A , the position of the chip  10  on the upper substrate  20  is designated by the phantom outline  24 . Three solderable conductor pads  26   a ,  26   b ,  26   c  are formed on the substrate face  20   a . The pad  26   a  overlaps the chip conductor pad  12   a , but not the chip conductor pad  12   b , and extends rightward beyond the outline  24  of chip  10  as viewed in  FIG. 2A , to facilitate connection of a first electrical terminal  28  to the FET source. The pad  26   b  overlaps the chip conductor pad  12   b , but not the chip conductor pad  12   a , and extends rightward beyond the outline  24  of chip  10  as viewed in  FIG. 2A , to facilitate connection of a second electrical terminal  30  to the FET gate. The pad  26   c  lies outside the outline  24  of chip  10 , and is soldered to the upper surface of a third electrical terminal  32 , as shown in  FIG. 3A .  
         [0019]     Referring to  FIG. 2B , the position of the chip  10  on the lower substrate  22  is designated by the phantom outline  34 . Three solderable conductor pads  36   a ,  36   b ,  36   c  are formed on the substrate face  22   a . The pad  36   a  overlaps the entire outline  34  of the chip  10 , and extends leftward beyond the outline  34  of chip  10  as viewed in  FIG. 2B , to facilitate connection of the third electrical terminal  32  to the FET drain. The pads  36   b  and  36   c  lie outside the outline  34  of chip  10 , and are respectively soldered to the lower surfaces of the first and second electrical terminals  28  and  30 , as shown in  FIGS. 3A-3B . Finally, the lower substrate  22  includes first and second rectangular openings  38 ,  40  that serve as cooling fluid ports, as explained below.  
         [0020]      FIGS. 3A and 3B  depict a complete power semiconductor device package  42  built around the chip  10  of  FIGS. 1A-1B . Referring to  FIG. 3A , the package  42  includes the chip  10 ; the upper and lower substrates  20 ,  22 ; the first, second and third terminals  28 ,  30 ,  32 ; and a single or multi-layer circuit board  44 . The conductor pads  12   a  and  12   b  of the chip  10  are respectively soldered to the conductor pads  26   a  and  26   b  of the upper substrate  20 , and the conductor pad segments  18  of the chip  10  are soldered to the conductor pad  36   a  of lower substrate  22 . The first terminal  28  is soldered on its upper face to the conductor pad  26   a  of upper substrate  20 , and on its lower face to the conductor pad  36   b  of lower substrate  22 ; in this way, the first terminal  28  is electrically coupled to the FET source. The second terminal  30  is soldered on its upper face to the conductor pad  26   b  of upper substrate  20 , and on its lower face to the conductor pad  36   c  of lower substrate  22 ; in this way, the second terminal  30  is electrically coupled to the FET gate. The third terminal  32  is soldered on its upper face to the conductor pad  26   c  of upper substrate  20 , and on its lower face to the conductor pad  36   a  of lower substrate  22 ; in this way, the third terminal  32  is electrically coupled to the FET drain. In a typical application, the terminals  28 ,  30 ,  32  are bent downward and pass through suitable openings in the circuit board  44  for attachment to a circuit board conductor, as indicated in  FIG. 3A . Of particular relevance to the present invention, the circuit board  44  is also provided with first and second rectangular fluid conduits  46  that correspond in shape and alignment with the first and second openings  38 ,  40  of lower substrate  22 . The lower substrate  22  is attached to the circuit board  44  with a sealant adhesive or solder  48  that prevents leakage of cooling fluid between the openings  38 ,  40  and the corresponding fluid conduits  46 .  
         [0021]     Referring to FIB  3 B, the location of the chip  10  with respect to the lower substrate  22  is such that the solder joint or conductive adhesive between substrate  22  and the marginal region  16   a  of chip  10  defines a fluid manifold  49  that encompasses the openings  38 ,  40  of substrate  22  and the walls  16   b  of chip  10 . Cooling fluid is supplied to the fluid manifold  49  through the substrate opening  38  (also referred to herein as inlet port  38 ) and a first fluid conduit  46  of circuit board  44  that is aligned with the opening  38 . The cooling fluid spreads out in the manifold  49 , passes through the micro-channels  14 , and is exhausted through the substrate opening  40  (also referred to herein as outlet port  40 ) and a second fluid conduit  46  of circuit board  44  that is aligned with the opening  40 . The fluid conduits  46  of circuit board  44  may be formed in several different ways, as described in related U.S. patent application Ser. No.  10 /______ (Attorney Docket No. DP-310178).  
         [0022]      FIGS. 4A-4C  depict a power semiconductor device package  50  incorporating several alternate design features. For example, the rectangular substrate openings  38 ,  40  of package  42  are replaced with a series of square or circular openings for improved coolant flow; the view of  FIG. 4C  depicts the inlet openings  38   a ,  38   b ,  38   c ,  38   d ,  38   e . Inlet and outlet fluid plenums below the substrate openings are formed by the combination of a braze alloy  52  printed on the bottom face of substrate  22  except in the vicinity of the substrate openings and a copper or aluminum plate  54  brazed to the braze alloy  52 . The alloy-free areas in the vicinity of the substrate openings define inlet and outlet plenums for interfacing the inlet and outlet conduits  58 ,  60  to the inlet and outlet openings in substrate  22 . As depicted in the view of  FIG. 4C , coolant is supplied to the inlet plenum  56  by a tubular supply conduit  58  that passes through an opening in plate  54 ; not shown in  FIG. 4C  is a tubular exhaust conduit  60  (see  FIG. 4A ) that similarly passes through an opening in plate  54  to exhaust coolant from the outlet plenum.  FIGS. 4A-4B  illustrate an interface between the plate  54  and the circuit board  44 . As indicated, the circuit board  44  is provided with metalized vias  62  for receiving the device terminals  28 - 32 , metalized rings  64  and  66  surrounding the conduits  58  and  60 , respectively, and a metalized ring  68  surrounding the rings  64 ,  66 . As seen in  FIG. 4C , the plate  54  is soldered to the circuit board  44  at metalized rings  64 - 68 , forming a perimeter mechanical support for the device and fluid seals around the conduits  58  and  60 .  
         [0023]      FIGS. 5A-5B  depict a power semiconductor device package  70  in which additional cooling is achieved by supplying coolant to a set of parallel micro-channels  72  formed on the inboard side of upper substrate  20  and surrounded by a fluid manifold  73 . The construction of the package  70  is similar to that of the package  50 , except that the substrates  20 ,  22  and plate  54  are widened as designated by the reference numeral  82  to accommodate an additional set of fluid conduits  74 ,  76  laterally outboard of the metalized ring  68  that supply fluid to, and exhaust fluid from, the fluid manifold  73 . As seen in  FIG. 5A , the circuit board  44  includes a pair of metalized rings  78 ,  80  surrounding the fluid conduits  74 ,  76 ; the plate  54  has a similar metallization pattern and set of openings, and the plate  54  is soldered to the circuit board  44  at metalized rings  78 ,  80 , forming fluid seals around the conduits  74 ,  76 . Since the fluid conduits  74 ,  76  are also laterally outboard of the IC chip  10  (the outline of which is designated by the reference numeral  34  in  FIG. 5A ) a pair of solderable annular spacers having the same thickness as the IC chip  10  are placed in vertical alignment with the fluid conduits  74 ,  76 , in the same plane as the IC chip  10 , and soldered to metalized rings formed on the upper and lower substrates  20 ,  22 . In  FIG. 5B , the spacer for the fluid conduit  76  is designated by the reference numeral  84 .  
         [0024]      FIG. 6  illustrates a further variation of the invention, where a set of parallel micro-channels  90  are formed in the lower substrate  22 . Liquid coolant can be supplied to and exhausted from the micro-channels  90  as described above in respect to  FIGS. 3B-5B . The micro-channels  90  may be formed by manufacturing the substrate  22  in upper and lower halves that are joined following or prior to formation of surface features that define the channels and fluid manifolds.  
         [0025]      FIG. 7  depicts a variant of the embodiment of  FIG. 6 , where set of parallel micro-channels  92  are formed a conductor layer  94  bonded to the lower substrate  22 . As with the embodiment of  FIG. 6 , liquid coolant can be supplied to and exhausted from the micro-channels  92  as described above in respect to  FIGS. 3B-5B . In this case, the micro-channels  92  may be formed by multi-step formation of the conductor layer  94 .  
         [0026]     Finally,  FIG. 8  illustrates the invention as applied to a so-called over-mold semiconductor package, where the IC chip  10  is mounted on a metal or ceramic substrate  96 , and a moldable plastic or resinous material  98  such as epoxy is molded over chip  10  and all but the bottom face of the substrate  96 . In this case, the substrate  96  can form one of the primary terminals of the IC chip  10 , and the other terminals are formed by one or more over-molded terminals  100  attached to the upper face of the IC chip  10  by a wirebond  102 , for example. A set of parallel micro-channels  104  are formed in the IC chip  10  as in the other embodiments, and a pair of fluid conduits  106  (one of which is shown in  FIG. 8 ) supply coolant fluid to and from the micro-channels  104  as described above.  
         [0027]     In summary, the present invention utilizes integral fluid conducting micro-channels to provide improved cooling in a power semiconductor device package. While described in reference to the illustrated embodiments, it is expected that numerous modifications and variations in addition to those mentioned herein will occur to those skilled in the art. For example, the layout and profile of the micro-channels may be different than shown herein, with corresponding changes in the size and configuration of the inlet and outlet ports, and so on. Accordingly, it is intended that the invention not be limited to the disclosed embodiment, but that it have the full scope permitted by the language of the following claims.