Abstract:
The invention relates to an image processing system for an x-ray installation or such like having at least one image source, a plurality of computing units for processing different algorithms, at least one non-volatile storage and a data sink, with the image source, the plurality of computing units, the non-volatile storage and the data sink each being physically connected to at least one control unit operating as a circuit module in a physical network, as a result of which a star-shaped logical topology can be configured by the control unit.

Description:
[0001]    This application claims priority of German application No. 10 2007 015 230.4 filed Mar. 29, 2007, which is incorporated by reference herein in its entirety. 
       FIELD OF THE INVENTION 
       [0002]    The present invention relates to an image processing system for an x-ray installation or suchlike. 
       BACKGROUND OF THE INVENTION 
       [0003]    In an x-ray system for angioplasty (angiography), a sequence of x-ray pulses is generated, with which the human body is radiated. In an image recording system (image amplifier, flat screen detector or suchlike) an ‘image’ is generated for each of these x-ray pulses using technical means, said image corresponding to the degree of x-ray absorption. Further sources for such image sequences can also originate from memory units or external signal sources (also other modalities such as MR, CT, ultrasound . . . ). In the further sequence, these digital x-ray images are processed in an image processing system (IPS), with different algorithms being used for image enhancement purposes. The images thus processed are in turn output in a temporal sequence on a monitor for diagnosis purposes. 
         [0004]    It is characteristic of an IPS that the frequency of the x-ray pulses is fixed or variable and typically moves in a range of between 1 to 60 images per second. A prerequisite for an IPS is that only a specific predetermined time span may elapse, the so-called latency of the IPS, from the image information arriving from the image recording system until this image is displayed on the monitor. 
         [0005]    An IPS further requires image data of the current examination to also be able to be simultaneously stored on a non-volatile storage (e.g. hard disk). At a later point in time, this image data can then be reprocessed by different algorithms of the IPS, if necessary also by algorithms other than those during the original recording, or in a different parameterization of the algorithms, with the original image repetition rates having in turn to be maintained. A further application also considers the reproduction at a higher or lower speed. 
         [0006]    A typical application is shown in  FIG. 1 , which illustrates an IPS as claimed in the prior art. An image source BQ allocates different algorithms to different computing units PE 1 , PE 2 . 1 , PE 2 . 2 , PE 3 . 1 , PE 3 . 2 , PE 4  as well as to a memory and finally to a data sink DS. 
         [0007]    The following difficulties arise with such an implementation of such an IPS shown in  FIG. 1 . 
         [0008]    The duration for the calculation of the individual algorithms may be very different. Differences of one or more decimal powers can easily exist in the required computing time between the individual algorithms. 
         [0009]    The overall computing power required to execute the algorithms is very high. This can generally no longer be achieved by one single processor. 
         [0010]    The division on a multiprocessor system is not a trivial matter. Due to the strict timing of the input image data, a rigidly clocked system is generally used, with the timing corresponding to the image sequence frequency and/or a multiple or fraction thereof. 
         [0011]    In different applications, the configuration of the processing chain can indicate clear differences, for instance when the data does not come from the image recording system (live) but instead from the non-volatile storage (replay). 
         [0012]    As a result of the high level of computing power required, a so-called “customer-specific circuit” (ASIC) is particularly suited to implementing the algorithm. The effort involved in designing such a circuit is enormously high and the production costs only depreciate with very high quantities. Such a circuit cannot be changed afterwards, for instance when an improved algorithm has been found. 
         [0013]    With the realization in a programmable logic module (FPGA), the depreciation of the costs is already achieved with a significantly lower quantity. The development costs are also considerably lower than with an ASIC. However, the expandability of the algorithms is significantly restricted by the predetermined number of available logic elements in an FPGA. The design of the logic is not very simple and is only controlled by specialists. 
         [0014]    The use of programmable processors (universal processor CPU or signal processor DSP) achieves a significant simplification. A number of processors, which process the image data, is typically used with an IPS. The necessary computing power is herewith achieved in that the overall task is distributed across several processors. A pipeline of processes is frequently established here, as is shown in  FIG. 1 . The known techniques for using several processors are the sequencing of processing steps and the division of data into several similarly-operating processing stages (striping), with the individual partial results being combined again by means of interleaving. 
         [0015]    The computing units PE 1 , PE 2 . 1 , . . . (Processing Elements) shown in  FIG. 1  can be different computing units, such as for instance ASIC, FPGA, DSPs, universal processors, microcontrollers, routers, periphery controllers and suchlike. In the previous methods of resolution, of which the arrangement shown in  FIG. 1  is an example, a specific topology of the data flow is established by physically connecting the individual PEs. The allocation of the algorithms to the computing units is carried out in a design phase, in which the topology, the computing power, the data transfer and the demand for latency of the individual stages as well as the overall processing have to be taken into account. The previous approaches have generally resulted in a direct mapping of the algorithms on assigned PEs, as is the case in the design shown in  FIG. 1 . This direct allocation is normally regarded as a ‘natural’ realization of the sequence of algorithms. Accordingly, the data paths are established and direct connections between the PEs are established. 
       SUMMARY OF THE INVENTION 
       [0016]    The object underlying the present invention is to improve an image processing system such that it can adjust significantly more flexibly to new algorithms, does not have higher latency and can be manufactured in a simpler fashion, thus rendering it more cost-effective. 
         [0017]    This object is achieved by the features of the independent claim. 
         [0018]    Features of preferred embodiments of the present invention are characterized in the dependent claims. 
         [0019]    The new approach of the present invention relates to an architecture of a “packet switched network”. The central element of this architecture is a module (“switch” module), which can route data streams from and to the connected users, with these data streams not inhibiting one another. The data streams are regarded as a temporal sequence of elementary units, the so-called data packets. Packet-switching “switches” can be established using different methods and protocols. Ethernet, InfiniBand or RapidIO are widespread for instance. It is essential here that a physical line is not connected between the users, with only the payload data being transmitted, but that the sender and receiver information and further management information is also added to each data packet, said information being necessary and/or useful in order to forward the packets from the sender to the receiver. This produces the physical topology of a star. 
         [0020]    By interconnecting several “switches”; a hierarchical star can also be established, with this being regarded as a simple star by the communication of the “switches” with one another. In this way, the same mechanism for data transfer is maintained by all the users involved. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0021]    The invention is described in more detail on the basis of the description of exemplary embodiments with reference to the drawings, in which; 
           [0022]      FIG. 1  shows the design of a conventional image processing system; 
           [0023]      FIG. 2  shows the star topology of a first exemplary embodiment of an image processing system according to the invention; 
           [0024]      FIG. 3  shows the topology of a second exemplary embodiment of the present invention; and 
           [0025]      FIG. 4  shows the topology of a third exemplary embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0026]    As  FIG. 2  shows, the individual components of the image processing system, i.e. the image source and/or image sources BQ(n), the computing units PE 1 , PE 2 . 1 , . . . , a memory S and a data sink and/or data sinks DS(n) are arranged around a control unit  5  in the manner of a star. In an initial configuration step, the desired logical topology is applied to the image sources, computing units, memories, and data sinks, i.e. the incoming and outgoing data streams of the user as well as the complexity of these streams are defined in the “switched network”. All data transfers ideally take place over this “switched network”, which typically has a very high switching capacity as a result of the simple task. 
         [0027]    The individual arithmetic units can also be seen as a “pool”, from which, depending on the application, the necessary units can be interconnected to one another by means of corresponding data streams. In this way, the arithmetic units are also adjusted to their respective tasks (algorithms) by the control unit. The “logical topology” of the processing stages is determined by this configuration process. With the solution according to the invention, the additional possibility is however created in that the allocation of the algorithms to the arithmetic units and the allocation of the data streams from application to application can be different. The image processing system according to the invention is a rigid structure, in which at the time of design, it has to be precisely determined which algorithms are to be used, which type and realization of the PEs is to be used (type, characteristics) and which interconnection of the PEs with one another is to be carried out. 
         [0028]    In accordance with the invention, the data streams are regarded as temporally changeable structures, which also require a temporally changeable interconnection of the PEs. The most important discriminator is the dynamic reconfiguration of the architecture of the image processing system according to the invention, with the aspects of the subsequent modular expandability and the evolution with the advancing development of the processing algorithms being a priority. 
         [0029]    The most important characteristic of the image processing system according to the invention is its configurability. Whereas with the previously proposed solutions, the physical topology and logical topology were identical, with the image processing system according to the invention, these can be different. The separation of the logical and physical configuration was hitherto not possible. 
         [0030]    It is also possible to design the logical topology differently as a function of the application, i.e. the architecture can be reconfigured dynamically. Whereas with the previous solutions, these different applications had to be known and taken into consideration during the design of the physical topology, another logical linking can now also be carried out at a later point in time. This can be necessary for instance if an algorithm is improved and now has to be distributed between more computing units as a result of the increasing demand for computing power. The “field upgrade” of the algorithms is herewith designed to be considerably more flexible. In particular, there is also the possibility with this architecture to add an additional algorithm to an existing chain of processing steps, said algorithm not having been provided within the original design. This is not possible with a rigid physical interconnection. In the image processing system according to the invention, this is enabled by a changed interconnection (routing) of the data streams in the switched network, i.e. in the control unit  5 . The image processing system according to the invention can be expanded in a modular fashion, also beyond the original intended use of the image processing system. If new or changed algorithms require an extensive redesign of the computing power, this can be carried out in a simple and modular fashion. If necessary, even the “hot-plug” is possible as a function of the selected switching technology, such as is known and common practice for instance with Ethernet-based networks. After the control unit has recognized these additional computing units, they are used if necessary. 
         [0031]      FIG. 3  shows a cascading of control units  5   a ,  5   b  and the modular design of a network as a second exemplary embodiment of the present invention. A control unit has a certain capacity, both in respect of the number of connectable users (number of ports), as well as in respect of the switching capacity (“packets per second” or “bits per second”). The realization of an image processing system based on this architecture need not be attuned to the possible maximum design, i.e. the number of ports, from the outset, but can however be extended under certain circumstances at a later point in time to include further control units. In this way, the switching capacity of the switches, i.e. of the control units, is to be noted and accounted for in the logical topology. As  FIG. 3  shows, a second control unit  5   b  is arranged downstream of the control unit  5   a , from which connections go to the individual computing units PE 2 . 1 , PE 2 . 2  . . . , to a further memory and to the data sink DS in a star-shaped fashion. 
         [0032]    In addition to the possibility of a direct connection (“point-to-point”), the control unit can also implement a duplication (“point-to-multipoint”, “multicast”, “broadcast”) of the data packets, with different receivers obtaining this duplicated data. The extraction of data streams from the internal connection can be used for different purposes, for instance for fault finding in the laboratory, for the purpose of monitoring in the field, or quite simply for differently further processing the same original data. The latter case may apply if a data stream for representation by means of video signals (BAS inter alia) or a recording on the VCR/DVD is to be calculated from the running image sequence, which is present in the higher local resolution, said data stream being required in another (lower) local resolution. The realization of this “T-piece” for extracting the data stream can be implemented in a simple fashion within the control unit, without affecting the primary transmitter or receiver of the data stream. No changes are then necessary for these components, since the overall interconnection and duplication of data is carried out in the control unit. 
         [0033]    In the case of a defective computing unit, a replacement unit which is potentially available can only be used in a simple fashion by changing the logical connections. Although in the case of a sudden failure of a unit, the current processing can probably not be continued without any interferences, the possibility still exists of reestablishing the entire processing topology by means of a standby module. The service time is herewith reduced and the availability of the installation is improved. Similar methods are known from RAID hard disk systems. The defective unit can be exchanged at a later point in time. 
         [0034]    The known realizations of “switched networks” even allow different logical networks to be realized on a physical network (“virtual private network”, VPN). In this way, the underlying control units already ensure that the VPNs are not able to inhibit one another. The defensive security is reliably provided in advance. Bandwidths can also be distributed to these VPNs. The functionality and safety is ensured by means of the configuration of the network, even if certain users do not adhere to specifications due to a malfunction for instance.  FIG. 4  shows an example of two logical networks in a physical network. The separation of the logical network is only to be established during the initial configuration and is then not to be taken further into consideration for the network user. 
         [0035]    Furthermore, with a “packet switched network” architecture, the logical interconnection of the data streams are adjusted to this, so that otherwise idle computing units can be used for other purposes. 
         [0036]    With a simple realization, a computing unit can also take over the function of a control unit module. In this case, the switching-functionality is thus not taken over by a dedicated module, but is instead implemented by the computing unit itself. It is characteristic of such an arrangement for the computing unit itself to then be equipped with several ports and for the switch functions to herewith be able to be realized. A separation of the switching and computing tasks is not imperative. Generalization of this concept also allows the direct connection of two computing units to be considered as such a network, provided the transmission is carried out in the form of switching-capable data packets. A large network is not necessarily needed to fulfill the definition of the present invention here. One example of such a degenerated network are the realizations of “PCI-Express”-based architectures (PCIe), with switching components present in the star point frequently being coupled very closely to one of the computing nodes (co-location) and thus taking over control functions. These realizations thus typically also show a relatively small growth with few network nodes. An expansion to larger network topologies then provides for the technology “PCIe advanced switching”, which compensates for the restriction to singular star topology and thereby enables larger networks. 
         [0037]    Finally, the ‘switched network’ architecture results in the new possibility that a computing unit which is not fully loaded takes over additional calculations, which do not accumulate in direct proximity. This is enabled by a further data stream being conveyed to the computing unit and the results being routed further via the control unit. The allocation of the algorithms is no longer related to the physical topology of the image processing system, as with the pipeline architecture as claimed in the prior art. 
         [0038]    The possibility of routing the data streams to the computing units allows new prospects with the expansion of the processing chain in the image processing system according to the invention to result. The possibility is herewith created of attaching parallel streams, which were not present in the original design of the image chain. The “switched network” architecture allows this in a simple fashion by means of configuration of the network and computing units. In particular, the injection (and if necessary the subsequent extraction) of data streams of a different origin is herewith also possible. Thus the fusion of data material from other modalities (e.g. magnetic resonance, computer tomography) can then be considered at a later point in time and does not have to be completely defined and released with the first design of the processing chain. These external data streams can pass through a completely different processing in order then to finally be related to the image data. These references can be produced by different indicators (e.g. time information, time stamps, local information, other features) and do not necessarily have to be carried out by the timing inherent in the image chain. In a rigid image pipeline system as claimed in the prior art, such a coupling is not possible. 
         [0039]    The afore-described preferred embodiments of the present invention can be combined with one another in any fashion. For instance, a computing unit in two VPNs of non-interrelated stages of the processing etc. can take over. The developer of an image processing system according to the invention can use all these possibilities taking into consideration the demands for fail-safety and throughput.