Abstract:
A wiring structure of a liquid crystal display (LCD) panel is provided. The wiring structure includes: a gate electrode layer, formed on a glass substrate; a first insulating layer, covering the glass substrate and partially formed on the gate electrode layer, such that at least one first opening is defined on the gate electrode layer; a source/drain electrode layer, formed on the first insulating layer, in which the source/drain electrode layer and the gate electrode layer are horizontally staggered; a second insulating layer, partially formed on the source/drain electrode layer, and defining at least one second opening on the source/drain electrode layer; and an indium tin oxide (ITO) layer, formed on the first opening, the second opening, and/or the second insulating layer. Thus, the high impedance of the ITO layer for connecting the gate electrode layer with the source/drain electrode layer is reduced.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims the benefit of Taiwan Patent Application No. 098131087, filed on Sep. 15, 2009, which is hereby incorporated by reference for all purposes as if fully set forth herein. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of Invention 
         [0003]    The present invention relates to a liquid crystal display (LCD) panel, and more particularly to a wiring structure of an LCD panel, which has a double metal layer structure and is capable of reducing wiring impedance. 
         [0004]    2. Related Art 
         [0005]    In currently known technologies, as for display devices employing a Chip On Film (COF) technology, the metal wiring employing the COF technology has a higher impedance than that of conventional devices using a printed wiring board (PWB) for signal transmission, so that when the COF wiring impedance is high, the mura problem of tape automated bonding (TAB) easily occurs, thereby affecting the quality of the panel. In order to reduce the wiring impedance, a double-layer metal wiring structure is used. 
         [0006]      FIG. 1  is a top view of a double-layer metal wiring structure in the prior art.  FIG. 2  is an equivalent circuit diagram of the double-layer metal wiring structure in the prior art.  FIG. 3A  is a cross-sectional view of the double-layer metal wiring structure in the prior art, taken along Line A-A.  FIG. 3B  is a cross-sectional view of the double-layer metal wiring structure in the prior art, taken along Line B-B. Referring to  FIGS. 1 ,  2 ,  3 A, and  3 B, since a signal needs to pass through a double-layer metal wiring structure  5  (formed on a glass substrate  50 ), the signal needs to be transmitted to a source/drain electrode layer  52  through an indium tin oxide (ITO) layer  54 , such that a gate electrode layer  51  and the source/drain electrode layer  52  can transmit the COF signals at the same time. Definitely, an insulating layer  53  is completely or partially formed between the gate electrode layer  51 , the source/drain electrode layer  52 , and the ITO layer  54 , so as to provide electrical insulation there-between. 
         [0007]    For example, in the double-layer metal wiring structure  5 , when a signal of a source integrated circuit (IC)  61  is transmitted by the gate electrode layer  51 , the signal needs to be transmitted to a gate IC  62  through an impedance R 1  of the ITO layer and the gate electrode layer, an impedance R 2  of the gate electrode layer, and the impedance R 1  of the gate electrode layer and the ITO layer, that is, along a direction represented by Arrow D; and when the signal is transmitted by the source/drain electrode layer  52 , the signal needs to be transmitted to the gate IC  62  through an impedance R 3  of the ITO layer, an impedance R 4  of the ITO layer and the source/drain electrode layer, an impedance R 5  of the source/drain electrode layer, the impedance R 4  of the source/drain electrode layer and the ITO layer, and the impedance R 3  of the ITO layer, that is, along a direction represented by Arrow C (as shown in  FIG. 2 ). 
         [0008]    Since the signal must be conducted to the double-layer metal, the ITO layer  54  is additionally used as a jump layer for conducting the signal on the gate electrode layer  51  to the source/drain electrode layer  52 , thereby transmitting the signal through the double-layer metal. 
         [0009]    However, since the ITO layer  54  has a high impedance, that is, the impedance of the ITO layer  54  is about 80 times of that of aluminum, the signal loss occurs when the signal on the gate electrode layer  51  is transmitted to the source/drain electrode layer  52 , resulting in that the original signal cannot be kept intact after being transmitted through the double-layer metal. 
       SUMMARY OF THE INVENTION 
       [0010]    To solve the above problem, an objective of the present invention is to provide a double-layer metal structure, in which a gate electrode layer and a source/drain electrode layer are horizontally staggered, so as to reduce the impedance when a signal passes through the double-layer metal structure, thereby solving the problem that the signal cannot be kept intact after being transmitted due to signal loss. 
         [0011]    Another objective of the present invention is to reduce the segmental difference between adjacent wiring structures. 
         [0012]    To achieve the above objective, the present invention provides a wiring structure of a liquid crystal display (LCD) panel, which comprises a gate electrode layer, formed on a glass substrate; a first insulating layer, covering the glass substrate and partially formed on the gate electrode layer, such that at least one first opening is formed on the gate electrode layer; a source/drain electrode layer, formed on the first insulating layer, wherein the source/drain electrode layer and the gate electrode layer are horizontally staggered; a second insulating layer, partially formed on the source/drain electrode layer, and defining at least one second opening on the source/drain electrode layer; and an indium tin oxide (ITO) layer, formed on the first opening of the gate electrode layer, the second opening of the source/drain electrode layer, and/or the second insulating layer. 
         [0013]    In the above mentioned wiring structure of an LCD panel, the first opening is further attached to an integrated circuit (IC) pad and the second opening is further attached to an integrated circuit (IC) pad. 
         [0014]    In the above mentioned wiring structure of an LCD panel, when the gate electrode layer is made of a metal material that is not readily oxidized, the ITO layer is only formed on the second opening of the source/drain electrode layer and the second insulating layer. 
         [0015]    In the above mentioned wiring structure of an LCD panel, when the source/drain electrode layer is made of a metal material that is not readily oxidized, the ITO layer is only formed on the first opening of the gate electrode layer and the second insulating layer. 
         [0016]    In the above mentioned wiring structure of an LCD panel, the ITO layer is partially formed on the first opening of the gate electrode layer and/or the second opening of the source/drain electrode layer. 
         [0017]    To achieve the above objective, the present invention provides a liquid crystal display (LCD) panel, which comprises: a glass substrate, having a display region and a wiring region; and a wiring structure, formed on the wiring region of the glass substrate, and the wiring structure comprises: 
         [0018]    a gate electrode layer, formed on the glass substrate; 
         [0019]    a first insulating layer, covering the glass substrate and partially formed on the gate electrode layer, such that at least one first opening is formed on the gate electrode layer; 
         [0020]    a source/drain electrode layer, formed on the first insulating layer, wherein the source/drain electrode layer and the gate electrode layer are horizontally staggered; 
         [0021]    a second insulating layer, partially formed on the source/drain electrode layer, and defining at least one second opening on the source/drain electrode layer; and 
         [0022]    an indium tin oxide (ITO) layer, formed on the first opening of the gate electrode layer, the second opening of the source/drain electrode layer, and/or the second insulating layer. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0023]      FIG. 1  is a top view of a double-layer metal wiring structure in the prior art; 
           [0024]      FIG. 2  is an equivalent circuit diagram of the double-layer metal wiring structure in the prior art; 
           [0025]      FIG. 3A  is a cross-sectional view of the double-layer metal wiring structure in the prior art, taken along Line A-A; 
           [0026]      FIG. 3B  is a cross-sectional view of the double-layer metal wiring structure in the prior art, taken along Line B-B; 
           [0027]      FIG. 4  is a top view of a basic structure of the present invention; 
           [0028]      FIG. 5A  is a cross-sectional view of the basic structure of the present invention taken along Line A′-A′; 
           [0029]      FIG. 5B  is a cross-sectional view of the basic structure of the present invention taken along Line B′-B′; 
           [0030]      FIG. 6A  is a top view of a first embodiment of the present invention; 
           [0031]      FIG. 6B  is an equivalent circuit diagram of the first embodiment of the present invention; 
           [0032]      FIG. 7  is a top view of a second embodiment of the present invention; 
           [0033]      FIG. 8  is a top view of a third embodiment of the present invention; 
           [0034]      FIG. 9  is a top view of a fourth embodiment of the present invention; and 
           [0035]      FIG. 10  is a top view of a fifth embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0036]      FIG. 4  is a top view of a basic structure of the present invention.  FIG. 5A  is a cross-sectional view of the basic structure of the present invention taken along Line A′-A′.  FIG. 5B  is a cross-sectional view of the basic structure of the present invention taken along Line B′-B′. Referring to  FIGS. 4 ,  5 A, and  5 B, an LCD panel  1  of the present invention has a glass substrate  2  and a wiring structure  3 . The glass substrate  2  has a display region  21  and a wiring region  22 . The wiring structure  3  is formed on the wiring region  22  of the glass substrate  2 . 
         [0037]    Taking a basic structure as an example, the wiring structure  3  includes a gate electrode layer  31 , a first insulating layer  32 , a source/drain electrode layer  33 , a second insulating layer  34 , and an ITO layer  35 . 
         [0038]    The gate electrode layer  31  is formed on the glass substrate  2 . In particular, the gate electrode layer  31  is formed on the wiring region  22  of the glass substrate  2 . The first insulating layer  32  covers the glass substrate  2 , and is partially formed on the gate electrode layer  31 , such that a first opening  311  is defined on the gate electrode layer  31 . The source/drain electrode layer  33  is formed on the first insulating layer  32 , and the source/drain electrode layer  33  and the gate electrode layer  31  are horizontally staggered without overlapping each other. The second insulating layer  34  is partially formed on the source/drain electrode layer  33 , and defines a second opening  331  on the source/drain electrode layer  33 . The ITO layer  35  is formed on the first opening  311  of the gate electrode layer  31 , the second opening  331  of the source/drain electrode layer  33 , and/or the second insulating layer  34 . The first opening  311  and the second opening  331  are configured to be attached to an integrated circuit (IC) pad. 
         [0039]    Since the wiring structure  3  is illustrated by taking the basic structure as an example, the numbers of the first opening  311  and the second opening  331  corresponding to the gate electrode layer  31  and the source/drain electrode layer  33  are not limited to one, but may be increased according to design requirements, and the positions of the gate electrode layer  31  and the source/drain electrode layer  33  relative to each other may also be changed. 
         [0040]    Embodiments are illustrated below by taking the total number of the first opening  311  and the second opening  331  being five as an example. 
         [0041]      FIG. 6A  is a top view of a first embodiment of the present invention.  FIG. 6B  is an equivalent circuit diagram of the first embodiment of the present invention. Referring to  FIGS. 6A and 6B , since an ordinary COF wiring structure mostly has more than two signal pins, the arrangement of the signal pins (that is, the first opening  311  and the second opening  331 ) in the horizontal direction is changed from the original arrangement of GE/GE/GE/GE/GE (GE represents a gate electrode layer  51 ) into a staggered arrangement GE/SD/GE/SD/GE (GE represents the gate electrode layer  51 , and SD represents the source/drain electrode layer  33 ) (taking the 5 PIN signal as an example), and outside the first opening  311  and the second opening  331 , the metal wiring is extended to the width of all signal pins, thereby achieving the signal transmission by the double-layer metal wiring. 
         [0042]    Since the signal in the first opening  311  and the second opening  331  is transmitted to the double-layer metal, the source/drain electrode layer  33  does not need to transmit the signal from the gate electrode layer  31  by additionally using the ITO layer  35  outside the first opening  311  and the second opening  331 . That is, as compared with the prior art (as shown in  FIGS. 1 and 2 ), in the double-layer metal wiring structure  3  of the present invention, when a signal of the source IC  61  is transmitted by the gate electrode layer  31 , the signal needs to be transmitted to the gate IC  62  through an impedance R 1  of the ITO layer and the gate electrode layer, an impedance R 2  of the gate electrode layer, the impedance R 1  of the gate electrode layer and the ITO layer, that is, along a direction represented by Arrow D′; however, when the signal is transmitted by the source/drain electrode layer  33 , the signal does not need to be transmitted through an impedance R 3  of the ITO layer first (as shown in  FIG. 2 ), but only needs to be transmitted to the gate IC  62  through an impedance R 4  of the ITO layer and the source/drain electrode layer, an impedance R 5  of the source/drain electrode layer, and the impedance R 4  of the source/drain electrode layer and the ITO layer, that is, along a direction represented by Arrow C′ (as shown in  FIG. 6B ), so as to reduce the signal loss caused by the high impedance of the ITO layer  35  (for example, the R 3  as shown in  FIG. 2 ). 
         [0043]      FIG. 7  is a top view of a second embodiment of the present invention. The signal pins (that is, the first opening  311  and the second opening  331 ) are configured in a form of GE/GE/GE/SD/SD, and pins of the same signal are configured for the gate electrode layer  31  and the source/drain electrode layer  33  half by half, that is, three first openings  311  are respectively disposed on three adjacent gate electrode layers  31 , and two second openings  331  are respectively disposed on two adjacent source/drain electrode layers  33 ; and outside the first openings  311  and the second openings  331 , the metal wiring is extended to the width of all signal pins, thereby achieving the signal transmission by the double-layer metal wiring. 
         [0044]    Likewise, since the signal in the first opening  311  and the second opening  331  is transmitted to the double-layer metal, the source/drain electrode layer  33  does not need to transmit the signal from the gate electrode layer  31  by additionally using the ITO layer  35  outside the first opening  311  and the second opening  331 , such that the signal loss caused by the high impedance of the ITO layer  35  (for example, the R 3  as shown in  FIG. 2 ) is reduced. 
         [0045]      FIG. 8  is a top view of a third embodiment of the present invention. The structure of this embodiment is approximately the same as that of the second embodiment. However, since metal pins (that is, the first opening  311  and the second opening  331 ) are configured for the gate electrode layer  31  and the source/drain electrode layer  33  half by half, a segmental difference may occur. Therefore, an adjacent portion between two wiring structures  3  is configured with the same metal pins, so as to reduce the influences caused by the segmental difference. Taking a power supply voltage (VSS) signal V 1  and a driving voltage (VDD) signal V 2  as an example, the left portion of the VSS is the pins of the gate electrode layer  31 , and the right portion thereof is the pins of the source/drain electrode layer  33 , so that the left portion of the VDD is configured with the pins of the same source/drain electrode layer  33 , and the right portion thereof is configured with the pins of the gate electrode layer  31 , and so on. Thus, the segmental difference generated between adjacent wiring structures is avoided. 
         [0046]      FIG. 9  is a top view of a fourth embodiment of the present invention.  FIG. 10  is a top view of a fifth embodiment of the present invention. The structure of the fourth embodiment is approximately the same as that of the second embodiment, and the structure of the fifth embodiment is approximately the same as that of the third embodiment. 
         [0047]    When the gate electrode layer  31  is made of a metal material that is not readily oxidized, that is, when the metal material of the gate electrode layer  31  (the structure on the right side of  FIG. 9 ) or the source/drain electrode layer  33  (the structure on the left side of  FIG. 9 ) is not readily oxidized, the ITO layer  35  is only formed on the second opening  331  of the source/drain electrode layer  33  and the second insulating layer  34 , so that it is unnecessary to cover the ITO layer  35  on the pins (that is, the first opening  311  and the second opening  331 ) (as shown in  FIG. 9 ). 
         [0048]    When the pins (that is, the first opening  311  and the second opening  331 ) do not need to be covered by the ITO layer  35 , that is, when the source/drain electrode layer  33  is made of a metal material that is not readily oxidized, an incomplete ITO layer  35  may be added, such that the ITO layer  35  is partially formed on the gate electrode layer  31  (the structure on the right side of  FIG. 10 ) or the source/drain electrode layer  33  (the structure on the left side of  FIG. 10 ). That is, the ITO layer  35  is merely formed on the first opening  311  of the gate electrode layer  31  and the second insulating layer  34 , so as to electrically connect the pins (that is, the first opening  311  and the second opening  331 ) (as shown in  FIG. 10 ). 
         [0049]    Therefore, through the illustration of the above structures and embodiments, the wiring structure of the present invention and the LCD panel using the wiring structure can reduce the impedance between the double-layer metal, so as to reduce the signal loss during the signal transmission, and avoid the segmental difference between adjacent wiring structures. 
         [0050]    It is of course to be understood that the embodiments described herein is merely illustrative of the principles of the invention and that a wide variety of modifications thereto may be effected by persons skilled in the art without departing from the spirit and scope of the invention as set forth in the following claims.