Abstract:
An integrated circuit comprises components for the basic functions of a timepiece and additional components for controlling the operation mode of the basic components. By properly controlling the operation mode of the basic components, the integrated circuit can be applied to two or more types of timepieces, thereby reducing the kinds of the integrated circuits that need to be prepared.

Description:
This is a continuation of application Ser. No. 617,487, filed Sept. 29, 1975 which is now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     This invention relates to an integrated circuit for use in electronic timepieces and more particularly to an integrated circuit applicable to various types of timepieces. 
     In the manufacture of electronic timepieces, the integrated circuit is usually designed to be utilized with only for a single type. Accordingly, it is necessary that the same number of types of timepiece of integrated circuits as types of timepiece be prepared. This results in many defects in the manufacture, handling, inspection and setting up, as well as increased cost of the timepiece. 
     SUMMARY OF THE INVENTION 
     It is a primary object of this invention to provide an integrated circuit which is applicable to various types of electronic timepieces. This means that the number of types of integrated circuits with respect to the number of types of the timepieces can be reduced. 
     According to this invention, the common use of the integrated circuit in various types of timepieces is accomplished by providing a plurality of terminals which are connected to a suitable control block in accordance with the particulars of the timepiece to which the integrated circuit is applied. 
    
    
     IN THE DRAWING 
     The drawing shows a circuit diagram of an integrated circuit embodying this invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In the drawing, the integrated circuit 100 embodying this invention includes; an oscillator circuit 12 with a crystal resonance element 11 an auxillary frequency divider 13 for dividing the frequency of the output from the oscillator circuit 12; a select gate 14 comprising a pair of AND-gates 141 and 142, an OR-gate 143 and an inverter 144; and a series of frequency dividers 15, 16 and 17 each of which includes a plurality of flip-flop circuits and together which form a main frequency divider means. 
     The output of the last stage divider 17 has a frequency of 1/60 Hz (one minute and is lead through select gates 18 and 20 and a shaping circuit 19 to the input of a flip-flop 21. The Q-output of the flip-flop 21 passes through an AND-gate 22 and the Q-output of the flip-flop through an AND-gate 23 while the AND-gates 22 and 23 are opened by the signal from the select gate 20. The output from the AND-gates 22 and 23 are taken out from terminals 26 and 27 through buffer circuits 24 and 25, respectively, for driving a pulse motor or counter so as to energize a suitable time display. In this embodiment the output of the divider 17 has a frequency of 1/60 Hz. 
     The output of the oscillator 12 is sent either directly or through the auxillary frequency divider 13 to the divider 15 in accordance with the state of the select gate 14. The divider 15 acts to produce a 1024 Hz signal which is then supplied to the next divider 16 from which two output signals with a frequency of 1 Hz (one second) and of 32 Hz, (1/32 second) respectively, are obtained, the 1 Hz signal being used in the divider 17 to produce 1/60 Hz signal. Either the 1 Hz signal or the 1/60 Hz signal is selected in accordance with the state of the select gate 18 and then is sent to the shaping circuit 19 where the signal is subjected to a wave form shaping to have the desired pulse width, i.e., 15.6 milliseconds by using the 32 Hz signal. The select gate 20 acts to select either the output of the shaping circuit 19 or the 1024 Hz signal and the output signal thereof is used as an input signal of the flip-flop 21. 
     The integrated circuit 100 described is designed for use in the timepiece with a pulse motor having a pair of input lines. For the purpose of conformity of the integrated circuit with such type of timepiece, a pair of output signals can be obtained from the terminals 26 and 27. The output circuit including the flip-flop 21, AND-gates 22 and 23 and buffer circuits 24 and 25 may be replaced with another type of circuit, the selection being done in accordance with the type of driving circuit for the time display. 
     The respective element and the connection thereof set forth as above are well known to those skilled in the art of electronic timepiece and the detailed description thereof may be omitted. 
     The select gate 18 comprises a pair of AND-gates 181 and 182, an OR-gate 183 and an inverter 184 and similarly the select gate 20 is composed of a pair of AND-gates 201 and 202, an OR-gate 203 and an inverter 204. The shaping circuit 19 may comprise a pair of NAND-gates 191 and 192 and an AND-gate 193. 
     For controlling the select gates 14, 18 and 20, there are provided a plurality of terminals indicated at 28, 29, 30, 31 and 32 in the drawing. The first terminal 28 is connected to one of the inputs of the AND gate 141 through the inverter 144 and to one of the inputs of the AND-gate 142 via a line 33. Similarly, the terminal 29 is connected to one of the inputs of the AND-gate 182 and the input of the inverter 184 of which output is connected to one of the input of the AND-gate 181 through a line 34. In the same manner the third terminal 30 is connected to the input of the inverter 204 through a line 35. 
     The fourth and fifth terminals 31 and 32 are connected to an AND-gate 36 through lines 37 and 38, respectively, the output of the AND-gate 36 being lead to one of the inputs of an OR-gate 39. The OR-gate 39 acts to supply the signal from the AND-gate 36 or the signal on the line 37 to the reset terminal of the flip-flop 21. An AND-gate 40 is provided in the line 38 and has a first input connected to the terminal 32 and a second input connected to the output of the select gate 20 via an inverter 41. The output signal of the AND-gate 40 is supplied to the reset terminal of the dividers 16 and 17 through a line 42. 
     The output of the first divider 15 having a frequency of, for example, 1024 Hz is supplied to the input of the AND-gate 202, the output 1 Hz (one second) of the second divider 16 to the AND-gate 182 and the output 1/60 Hz (one minute) of the third divider 17 to the AND-gate 181. Also, the output delivered from the intermediate stage of the divider 16 having a frequency of 32 Hz is connected to the NAND-gate 191. 
     Inverter rings 43, 44, 45 and 46 respectively connected to the lines 33, 34, 35 and 37 are used as a memory. 
     In the integrated circuit described, the output level of the AND-OR select gate 14 is determined in accordance with the logical level of the terminal 28. Namely, when the logical level at the terminal 28 is &#34;1,&#34; the AND-gate 142 is opened to transmit the output of the oscillator 12 to the divider 15. On the other hand, if the level at the terminal 28 is &#34;0,&#34; then the AND-gate 141 allows the output signal of the divider 13 to pass therethrough. Accordingly, it is possible to utilize a crystal oscillator with a resonance frequency either of 32 KHz or of 64 KHz as the element 11. 
     The terminal 29 is provided for selecting either the 1 Hz (one second) signal and 1/60 Hz signal by controlling the select gate 18. The AND-gate 181 is opened so as to select the 1/60 Hz signal when the logical level at the terminal 29 is &#34;0,&#34; while the AND-gate 182 is opened so as to select the 1 Hz signal when the logical level at the terminal 29 is &#34;1.&#34; The selected signal is used as an input of the shaping circuit 19. 
     The terminal 30 is used for an optional function such as for a timing circuit of a timepiece with a liquid crystal display. When the logical level at the terminal 30 is &#34;0,&#34; the AND-gate 201 is opened to allow the 1 Hz signal or 1/60 Hz signal to pass therethrough. when the level at the terminal 30 is &#34;1,&#34; however, the output of the divider 15 is lead to the flip-flop 21 through the AND-gate 202 and OR-gate 203. At this stage the flip-flop 21 has been reset by the signal supplied through the OR-gate 39, so that the output signal of the flip-flop 21 will appear only at the terminal 27. 
     The terminal 31 is for selecting the operation modes according to the preference of the user. During the period in which the level at the terminal 30 is kept &#34;0,&#34; if the level at the terminal 31 is &#34;0,&#34; the reset terminal of the flip-flop 21 is not supplied with a reset signal. While, when there is a level &#34;1&#34; at the terminal 31, the flip-flop 21 is reset. 
     Lastly, the terminal 32 is provided for resetting the dividers 16 and 17 and also the flip-flop 21 when at the level &#34;1.&#34; The AND-gate 40 acts to inhibit the reset signal from the terminal 32, while the output signal appears at the terminal 26 or 27. 
     In the following table shows the relationship between the level at the terminals 30, 31 and the state of the divider 16, 17 and the flip-flop 21. 
     
         ______________________________________    Level    Level    Dividers                              Flip-flopMode     at 31    at 32    16 and 17                              21______________________________________A        0        1        Reset   ResetB        0        0        Reset   Not ResetC        1        0 or 1           Reset______________________________________ 
    
     From the table, it will be clear that both of the dividers 16 and 17 and the flip-flop 21 are reset of &#34;Mode A,&#34; so that the signal would necessarily be given at the predetermined terminal 26 or 27 after one second from the release of the terminal 32. When the negative flip-flop is used as the flip-flop 21, the output definitely appears at the terminal 27. 
     In &#34;Mode B,&#34; the flip-flop 21 is kept at the same state as before the resetting operation, because the flip-flop is not reset, and the output is always given at the opposite terminal 26 or 27 to that which is given the output at the time of resetting, after one second. 
     Furthermore, in &#34;mode C,&#34; the flip-flop 21 is kept at the reset state and the output of the divider having a frequency of 1024 Hz will appear at the terminal 32. 
     In summary, the terminals 28 through 31 have the following functions: 
     Terminal 28: Selects the frequency-dividing ratio based on the crystal resonance element used. 
     Terminal 29: Selects either the second signal or minute signal as the output. 
     Terminal 30: Determines whether or not selecting a timing signal for liquid crystal display as the output. 
     Terminal 31: Turns over the resetting mode. 
     The above functions can be selected in any combination in accordance with the require in the manufacture of timepieces. 
     One of the important features of this invention is that, in addition to providing the components for the basic functions which include the crystal resonance element 11, oscillating circuit 12, dividers 13, 15, 16 and 17, shaping circuit 19 and output circuit, the invention provides AND-OR select gates and the control terminals therefor, as the components for the additional functions, thereby making it possible to utilize the integrated circuit with at least two types of timepieces. In fact, the integrated circuit described above can be utilized with at least nine types of timepiece. 
     The components for the additional functions comprise only an extremely small proportion of the total number of components of the timepiece, so that the increase in cost of the timepiece is negligibly small. In addition, the use of an integrated circuit applicable to various kinds of timepiece is of considerable merit in mass production, ease of inspection, administration and service after sale, and so forth.