Abstract:
A bootstrapped switch circuit capable of operating at input signals from far below the negative supply rail to far beyond the positive supply rail may include (a) a switch having a first terminal coupled to an input terminal, a second terminal coupled to an output terminal, and a control terminal; (b) a charge pump coupled to one or more clock signals and isolated from a timing circuit via a first capacitor and a second capacitor, the charge pump generating an output voltage; and (c) a logic circuit coupled to one or more clock signals and isolated from the timing control circuit via a third capacitor and a fourth capacitor, wherein the logic circuit provides a control signal to the control terminal of the switch that is derived from the output voltage of the charge pump.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     The present application relates to and claims priority of U.S. provisional patent application (“Co-pending Provisional Patent Application”), Ser. No. 61/894,764, entitled “Isolated Bootstrapped Switch,” filed on Oct. 23, 2013. The disclosure of the copending Provisional Patent Application is hereby incorporated by reference in its entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an input circuit for sampling an analog signal. In particular, the present invention relates to an input circuit for sampling an analog differential signal with a wide common mode range. 
     2. Discussion of the Related Art 
     In an analog-to-digital converter (ADC), it is higher desirable to have an input circuit that allows sampling a fully differential signal. It is particularly desirable when the input circuit can sample a differential analog signal with a magnitude that is greater than a diode drop, and performs that sampling over a large common mode range. 
       FIG. 1  shows a switching circuit that is disclosed in U.S. Pat. No. 8,022,679 (“the &#39;679 patent”), entitled “SYSTEMS AND METHODS FOR FAST SWITCH TURN ON APPROXIMATING IDEAL DIODE FUNCTION.” As shown in  FIG. 1 , the switching circuit of the &#39;679 patent is not fully capacitively isolated, and its charge pump is not referenced to a source terminal of the switch. Also, the switching circuit has neither a discriminator nor a voltage regulator to provide a well-controlled gate-to-source voltage (V GS ). Therefore, the switching circuit of the &#39;679 patent cannot operate below the ground reference and thus is not suitable for use in a sampling network for an ADC. 
       FIG. 2  shows a bootstrapped switch circuit disclosed in U.S. Pat. No. 7,176,742 (“the &#39;742 patent”), entitled “BOOTSTRAPPED SWITCH WITH AN INPUT DYNAMIC RANGE GREATER THAN SUPPLY VOLTAGE.” The bootstrapped switch circuit of the &#39;742 patent may be used for sampling an input signal that goes beyond the power supply voltages. However, this bootstrapped switch circuit is capable of accepting an input signal that exceeds the supply voltage on the positive side by a limited amount, as the several low voltage transistors in the bootstrapping circuit is unable to withstand higher voltage signals. As shown in  FIG. 2 , the bootstrapped switch circuit of the &#39;742 patent includes capacitor C 13  that is precharged by being first connected between supply voltages GND and VDD. The charged capacitor is then switched to being connected between the source and gate terminals of bootstrapped switch N 20 . For high input signals, precharged capacitor C 13  must swing up to the input signal. The parasitic capacitors in bootstrapped switch MMN 20  result in a signal-dependent V GS . 
       FIG. 3  shows a bipolar switch that is disclosed in U.S. Patent Application Publication 2013/009623 (“the &#39;623 publication”), entitled “FOUR-QUADRANT BOOTSTRAPPED SWITCH CIRCUIT.” The bipolar switch in the &#39;623 publication is operated by a floating voltage source. The switch of the &#39;623 publication cannot accept an input signal that can go beyond the supply voltages, as the floating voltage source is generated by current sources that operate between those supply voltages. 
     SUMMARY 
     According to one embodiment of the present invention, a bootstrapped switch circuit includes a capacitor that is charged by a charge pump and which is coupled to a source terminal of a bootstrapped switch. A potential difference across the capacitor operates a logic circuit that controls other switches which charge or discharge the gate-to-source capacitance of the bootstrapped switch. The logic circuit is fully capacitively isolated. In one implementation, the logic circuit includes a latch structure which detects whether or not the bootstrapped switch should be turned on or turned off. The logic circuit may include a voltage regulator that provides a constant gate-to-source voltage (V GS ). A constant V GS  provides a constant switch resistance. 
     According to one embodiment of the present invention, a bootstrapped switch circuit is coupled to a timing circuit that provides one or more clock signals, and has an input terminal and an output terminal. The bootstrapped switch circuit may include (a) a switch having a first terminal coupled to the input terminal, a second terminal coupled to the output terminal, and a control terminal; (b) a charge pump coupled to the clock signals and isolated from the timing circuit via a first capacitor and a second capacitor, the charge pump generating an output voltage; and (c) a logic circuit coupled to the clock signals and isolated from the timing control circuit via a third capacitor and a fourth capacitor, wherein the logic circuit provides a control signal to the control terminal of the switch that is derived from the output voltage of the charge pump. In one implementation, the switch in the bootstrapped switch circuit may be provided by either (a) a single transistor or (b) two transistors having their source terminals connected in common. The logic circuit may include a voltage regulator circuit that generates a regulated voltage from the output voltage of the charge pump. 
     In one implementation, the logic circuit may include a latch structure. The charge pump, the logic circuit and the switch are implemented by NMOS transistors formed in a P-well enclosed by a N-tub region in a semiconductor substrate. The voltage on the N-tub region may be actively switched between a reference voltage and the input signal, or left floating. 
     In one embodiment, the clock signals comprise one or more pairs of complementary, but non-overlapping periodical waveforms. 
     The bootstrapped switch of the present invention may be used in numerous applications, such as (a) a power meter referenced to ground reference GND, for monitoring positive and negative supplies, (b) an input common mode extension for a high-resolution ADC, and (c) a high-speed or high-resolution ADC, and (d) monitoring fuel cells that can reverse polarity. A bootstrapped switch circuit of the present invention may operate in a wide input signal range, and allows sampling signals that are far above supply voltage VDD or far below ground reference GND. The bootstrapped switch circuit provides isolated sampling of large differential input voltages from minus V DSMAX  to plus V DSMAX  specified for the bootstrapped switch. 
     The present invention is better understood upon consideration of the detailed description below in conjunction with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a switching circuit in the prior art. 
         FIG. 2  shows a prior art bootstrapped switch circuit. 
         FIG. 3  shows a prior art switch that operates with a floating voltage source. 
         FIG. 4  shows a sampling network with switching circuits, described in a copending patent application. 
         FIG. 5(   a ) is block diagram  100  of a bootstrapped switch circuit, showing source terminal OUT of bootstrapped switch S 1  being connected to charge pump CP, in accordance with one embodiment of the present invention. 
         FIG. 5(   b ) shows the waveforms of clock signals PHI 1  PHI 2 , PHIC 1  and PHIC 2 , according to one embodiment of the present invention. 
         FIG. 6  is a schematic diagram showing bootstrapped switching circuit  200 , which is one implementation of charge pump CP, CMOS logic circuit  101  and bootstrapped switch S 1  of  FIG. 5(   a ), in accordance with one embodiment of the present invention. 
         FIG. 7(   a ) is block diagram  300  showing an NMOS implementation of a bootstrapped switch circuit according to one embodiment of the present invention. 
         FIG. 7(   b ) illustrates a structure that implements NMOS transistors in an isolated voltage domain, in accordance with one embodiment of the present invention. 
         FIG. 8  is a block diagram  400  illustrating a bootstrapped switch circuit that is capable of bipolar operations, according to one embodiment of the present invention. 
         FIG. 9  shows schematic circuit  500  which implements the bootstrapped switch circuit of block diagram  300  of  FIG. 7(   a ), in accordance with one embodiment of the present invention. 
         FIG. 10  shows input sampling network  600  for fully differential isolated ADC  650 , in accordance with one embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       FIG. 4  shows a sampling network with switching circuits that is described in the present inventor&#39;s copending U.S. patent application Ser. No. 13/841,459, now U.S. Pat. No. 8,907,703, issued Dec. 9, 2014, entitled “ISOLATED HIGH VOLTAGE SAMPLING NETWORK.” The Copending Patent Application is hereby incorporated by reference in its entirety. In the Copending Patent Application, the sampling network uses ground-referenced charge pumps, and thus the switches in the sampling network are unable to establish a constant V GS  for a rapidly changing input signal. Also, PMOS transistors with their N-Wells connected to the input signal render the switches unable to operate below substrate potential because the open circuit in the diode to the p-substrate. The signal polarity comparator in  FIG. 4  is required to operate beyond the supply voltages. 
       FIG. 5(   a ) is block diagram  100  of a bootstrapped switch circuit, showing source terminal OUT of bootstrapped switch S 1  being connected to charge pump CP, in accordance with one embodiment of the present invention. As shown in  FIG. 5(   a ), charge pump CP generates a voltage difference to supply the operation of CMOS logic circuit  101 . In turn, CMOS logic circuit  101  controls the gate-to-source voltage (V GS ) of bootstrapped switch S 1 , which switches bootstrapped switch S 1  between conducting and non-conducting states. Bootstrapped switch S 1 , when in the conducting state, passes the input signal at drain terminal IN to source terminal OUT. Charge pump CP and CMOS logic circuit  101  are controlled by clock signals PHI 1  PHI 2 , PHIC 1  and PHIC 2 , respectively, which are provided by timing control unit  102  via capacitors. Other than these capacitor-coupled clock signals, bootstrapped switch S 1 , charge pump CP and CMOS logic circuit  101  are isolated from power supply voltages VDD and GND. Timing control unit  102  draws power from power supply voltages VDD and GND. 
       FIG. 5(   b ) shows the waveforms of clock signals PHI 1  PHI 2 , PHIC 1  and PHIC 2 , according to one embodiment of the present invention. As shown in  FIG. 5(   b ), clock signals PHI 1  and PHI 2  are substantially complementary and non-overlapping (i.e., having a time delay between the rising or falling edge of each clock signal and the immediately following rising or falling edge of the other signal). Clock signals PHIC 1  and PHIC 2  are similarly complementary and non-overlapping. 
       FIG. 6  is a schematic diagram showing bootstrapped switch circuit  200 , which is an implementation of charge pump CP, CMOS logic circuit  101  and bootstrapped switch S 1  of  FIG. 5(   a ), in accordance with one embodiment of the present invention. As shown in  FIG. 6 , in bootstrapped switch circuit  200 , charge pump CP includes NMOS transistors T 2 , T 3 , T 4 , and T 5  and capacitors C 1 , C 2  and C 3 . Clock signals PHI 1 D and PHI 2 D have substantially the same waveforms as clock signals PHI 1  and PHI 2  of  FIG. 5(   b ), which alternately charge capacitors C 1  and C 2 . In each clock cycle, the voltages across capacitors C 2  and C 1  charge capacitor C 3  through diode-configured NMOS transistors T 4  and T 5 , respectively, to generate a voltage difference between electrical node  1  and source terminal IN of bootstrapped switch S 1 . In bootstrapped switch circuit  200 , bootstrapped switch S 1  is implemented by NMOS transistor T 1 . CMOS logic circuit  101  is implemented by PMOS transistors T 7  and T 9 , NMOS transistors T 6  and T 8 , capacitors C 4  and C 5 , and resistors that are connected cross each of the gate terminals of NMOS transistors T 6  and T 8  and source terminal IN of bootstrapped switch S 1 . CMOS logic circuit  101  is implemented as a latch structure with a stored signal that is output at electrical node  2 . The stored signal is overwritten by the changing logic states of clock signals PHIC 1  and PHIC 2 . When ground-referenced clock signal PHIC 1  pushes capacitor C 4  to a high voltage state (relative to source terminal IN), NMOS transistor T 6  is turned on, thereby pulling electrical node  4  to the voltage at source terminal IN, and turning on PMOS transistor T 9 . Conducting PMOS transistor T 9  brings electrical node  2  to the voltage level of electrical node  1 . Alternatively, when ground-referenced clock signal PHIC 2  pushes capacitor C 5  to a high voltage state (relative to source terminal IN), NMOS transistor T 8  is turned on, thereby pulling electrical node  2  to the voltage at source terminal IN, while turning on PMOS transistor T 7  to bring electrical node  4  to the voltage level of electrode node  1  and switching off PMOS transistor T 9 . For an input signal at source terminal IN that is below substrate bias of PMOS transistors T 7  and T 9 , the bulk terminals of PMOS transistors T 7  and T 9  cannot be connected to electrical node  1  to avoid the parasitic diodes to substrate turning on. As the maximum bulk-to-source voltage of a small low voltage PMOS transistor is low, larger (but slower) high voltage PMOS transistors may be required for operations far below the substrate bias voltage. 
       FIG. 7(   a ) is block diagram  300  showing an NMOS implementation of a bootstrapped switch circuit according to one embodiment of the present invention. Generally, a CMOS logic circuit (e.g., circuit  200  of  FIG. 6)  includes both PMOS and NMOS transistors which allow the CMOS logic circuit to avoid static current consumption. As shown in  FIG. 7(   a ), block diagram  300  shows bootstrapped switch S 1  controlled by NMOS logic circuit  301  through NMOS transistors S 2  and S 3 . In this embodiment, only NMOS transistors are used in the isolated voltage domain, which includes charge pump NMOS CP, NMOS logic circuit  301 , NMOS regulator circuit  303 , and NMOS transistor S 2  and S 3 . Timing control unit  302  is capacitively coupled to the isolated voltage domain through clock signals PHI 1 , PH 12 , PHIC 1  and PHIC 2 .  FIG. 7(   b ) illustrates a structure for implementing NMOS transistors in such an isolated voltage domain, in accordance with one embodiment of the present invention. As shown in  FIG. 7(   b ), NMOS transistors may be formed in P-well  351 , which is provided in N-tub region  352 ; N-tub region  352  may be biased above ground potential, if an input signal that goes below ground potential is supported. When the input signal is above ground potential, the potential in N-tub region  352  should follow the input signal. N-tub  352  may be actively biased by switching the bias voltage in N-tub region  352  between a reference voltage (e.g. power supply voltage GND) and the input signal, so as to avoid currents through the parasitic diodes. Leaving N-tub region  352  floating is also possible to avoid excessive current through the parasitic diodes. 
     The absence of PMOS transistors in N-tub region  352  allows the bootstrapped switch circuit of block diagram  300  to sample input signals far below ground potential and far above power supply voltage VDD. NMOS regulator circuit  303  generates a precise voltage at its output terminals (i.e., referenced to the source terminal of NMOS switch S 3 ) by stepping down an output voltage of charge pump NMOS CP. The regulated output voltage is coupled by NMOS switch S 3  to the gate terminal of bootstrapped switch S 1 . NMOS logic circuit  301 , which is supplied by charge pump NMOS CP, may generate logic signals that exceed the output voltage of NMOS regulator circuit  303 , so as to properly turn on NMOS switches S 3  and S 2 . When NMOS switch S 3  is conducting, the gate terminal of bootstrapped switch S 1  is raised to an output voltage of NMOS regulator circuit  303 , thereby turning on bootstrapped switch S 1 . NMOS switch S 2  is turned on to discharge the parasitic gate-to-source capacitor of bootstrapped switch S 1 , thus turning off bootstrapped switch S 1 . 
       FIG. 8  is a block diagram  400  illustrating a bootstrapped switch circuit that is capable of bipolar operations, according to one embodiment of the present invention. As shown in  FIG. 8 , the bootstrapped switch circuit of block diagram  400  achieves bipolar operation by implementing bootstrapped switch S 1  as two NMOS transistors S 1   a  and S 1   b  that are connected source-to-source. In this configuration, the parasitic diodes of NMOS transistors S 1   a  and S 1   b  cannot be rendered conductive simultaneously. Thus, input terminal IN may be much higher or lower in potential as output terminal OUT, without turning on both parasitic diodes. Unlike charge pump NMOS CP, NMOS logic circuit  301 , NMOS regulator circuit  303  of  FIG. 7(   a ), charge pump CP, logic circuit  401  and regulator circuit  403  need not be implemented only by NMOS transistors. In  FIG. 8 , charge pump CP is connected to the source terminal common to both NMOS switches S 1   a  and S 1   b.    
       FIG. 9  shows schematic circuit  500  which implements the bootstrapped switch circuit of block diagram  300  of  FIG. 7(   a ), in accordance with one embodiment of the present invention. As shown in  FIG. 9 , bootstrapped switch circuit  500  does not include a PMOS transistor. Charge pump NMOS CP is implemented by NMOS transistors T 2 , T 3 , T 4  and T 5  and capacitor C 1 , C 2  and C 3  in substantially the same manner as FIG.  6 &#39;s charge pump CP is implemented in bootstrapped switch circuit  200 . Charge pump NMOS CP provides a voltage across capacitor C 3 . NMOS logic circuit  301  is implemented by a latch structure that includes NMOS transistors T 6 , T 7 , T 8  and T 9 , resistors R 1  and R 2 . NMOS transistors T 6  and T 9  are turned on through the voltages on capacitors C 4  and C 5 , which are provided from signal level transitions in clock signals PHIC 1  and PHIC 2 , respectively, resulting in the stored values at electrical nodes  4  and  3  being overwritten. Resistor R 3 , NMOS transistors T 10 , T 11 , and T 12  and capacitor C 6  form NMOS regulator circuit  303 , which maintains electrical node  1 _REG at three MOS diode drops higher than electrical node VX. When electrical node  3  goes high (relative to electrical node VX) and the voltage at electrode node  1  exceeds drain terminal  1 _REG of NMOS transistor T 13  by at least one threshold voltage, NMOS transistor T 13  becomes conducting, thereby connecting electrical node  1 _REG to electrical node  2 . When NMOS transistor T 14  is conducting (i.e., electrode node  4  is high relative to electrical node VX), the gate-to-source capacitances of NMOS transistors T 1   a  and T 1   b  are discharged, opening the connection between input terminal IN from output terminal OUT of bootstrapped switch S 1 . 
       FIG. 10  shows input sampling network  600  for fully differential isolated ADC  650 , in accordance with one embodiment of the present invention. As shown in  FIG. 10 , input sampling network  600  includes bootstrapped switches  601   a ,  601   b ,  601   c  and  601   d , each of which may be implemented by any bootstrapped switch circuit of the present invention, such as bootstrapped switch circuit  500  of  FIG. 9 . In  FIG. 10 , the bootstrapped switches are capacitively coupled to ADC  650 , but they can also alternatively be resistively coupled to ADC  650 . Input sampling network  600  can accurately sample positive and negative input voltages over an extended common mode range. According to one implementation, an input sampling circuit of the present invention (e.g., input sampling network  600 ) designed to a 0.6 BICMOS process may sample signals in a common mode range between −36V and +36V without requiring a negative supply voltage. For example, such a sampling network may sample large differential signals (e.g. ±6V, V DSMAX ) at a common mode voltage from −33V up to +33 to an ADC supplied between GND and 5V. 
     The above detailed description is provided to illustrate the specific embodiments of the present invention and is not limiting. Numerous variations and modifications within the scope of the present invention are possible. The present invention is set forth in the accompanying claims.