Abstract:
A high performance cathode ray tube (CRT) display monitor is capable of operating at a rate of 50,000 horizontal scans per second. The monitor receives vertical sync, horizontal blank, and video input signals. The vertical sync signal is supplied to an integrated circuit vertical deflection system which produces vertical deflection signals (for the vertical yoke) and vertical blank signals. The horizontal blank signal is supplied to an integrated circuit phase lock loop which includes a phase comparator and a voltage controlled oscillator (VCO). The output of the VCO is amplified to produce horizontal deflection signal pulses (for the horizontal yoke). The horizontal retrace signal pulses are supplied to a comparator input of the phase lock loop, and are compared with the horizontal blank signal. The output of the phase comparator is filtered by a low pass filter and supplied to the input of the VCO, thereby controlling the VCO to lock the horizontal deflection signal pulse frequency to the frequency of the horizontal blank input signal. The horizontal retrace signal pulses are also coupled through a transformer to the base of a transistor where they are summed with the vertical blank signals to control switching of the transistor and thus produce blanking signals for the CRT.

Description:
This is a continuation of application Ser. No. 154,504, filed May 29, 1980 now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to cathode ray tube (CRT) displays. In particular, the present invention is drive circuitry for driving a CRT at very high speeds. 
     2. Description of the Prior Art 
     Cathode ray tube (CRT) display monitors have found increasing use in various fields of information processing. Because CRT monitors can display full pages of readable information, there is an increasing demand for high performance CRT monitors for word processing, graphics, electronic document storage and retrieval, and other electronic information processing applications. 
     One important application of high performance CRT monitors is in word processing equipment. There is an increasing trend toward word processing equipment in which an entire page is displayed. This permits the operator to see an image of what will be printed, before it is printed. From a human engineering standpoint, a page image with black characters on a white background provides the operator with the best page image display possible, since it most closely approximates the appearance of the finished product. 
     Another important application of high resolution, high density CRT monitors is in computer based systems which provide facsimile (FAX) type displays. In this application the actual image of the page of paper, including photos, signatures, drawings, diagrams and handwritten messages, is displayed. The source of data may be a &#34;FAX&#34; machine, a video disk (or other laser based encoding-decoding equipment), a standard computer data base, or a high resolution camera. Operation of this equipment, however, is predicated upon the availability of high resolution, high density CRT monitors. 
     Another important application for high resolution, high density CRT monitors is in photocomposing systems. The very nature of the photocomposing task virtually demands a page image display as an integral part of the photocomposing system. 
     High resolution, high density CRT monitors have been developed in recent years which operate at horizontal scan rates which are much higher than the industry standard 15.75 KHz. These monitors include the Motorola M4408, the CPT Corporation HRD15 and the Video Monitors Inc. M15A60. 
     The Motorola M4408 is an interlaced unit having a horizontal scan rate of 34 kHz and a video bandwidth of 50 MHz. Since it is an interlaced unit, the M4408 requires a slow response yellow-green T19 phosphor, which limits its resolution and contrast. In addition, the M4408 is relatively bulky, complex and expensive. 
     The CPT Corporation HRD15 has a horizontal scan rate of 50 kHz and a video bandwidth of 100 MHz. While providing high performance, the CPT HRD15 is complex and expensive. 
     The Video Monitor M15A60 has a horizontal scan rate of 50 kHz and a video bandwidth of 85 MHz. While providing high performance, it is also relatively complex and expensive. 
     There is a continuing need for a high performance CRT monitor capable of operating at high scan rate with high resolution, while being less complex and expensive than the prior art high resolution, high density CRT monitors. 
     SUMMARY OF THE INVENTION 
     The present invention is a high performance CRT monitor which is simple and uses far fewer components than the prior art high performance CRT monitors. The CRT monitor of the present invention includes a vertical deflection circuit, which receives a vertical sync input signal and produces vertical deflection and vertical blank signals. 
     A horizontal blank signal is supplied to one input of a phase locked loop which includes a phase comparator and a voltage controlled oscillator (VCO). The horizontal blank signal is supplied to one input of the phase comparator, and a horizontal retrace signal is supplied to the other input of the phase comparator. The output of the phase comparator is a function of the comparison of the horizontal blank and horizontal retrace signals, and is filtered and supplied as a control voltage input to the VCO. The output of the VCO is amplified and supplied to the horizontal yoke as the horizontal drive signal. The horizontal retrace signal is also fed through a transformer and summed with the vertical blanking signal to produce the blanking signal applied to the CRT. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1A, 1B and 1C are a schematic diagram of a preferred embodiment of the CRT monitor of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In FIG. 1A, cathode ray tube 20 is shown. A 6.3 V AC signal is applied to cathode 22 and a 15-kV voltage is applied to anode 24 of CRT 20. A VIDEO CONTROL signal is applied to grid 26, a BLANKING signal is applied to grid 28, an INTENSITY control signal is applied to grid 30, and a FOCUS control signal is applied to grid 32. 
     Deflection signals provide scanning of the electron beam in the CRT and are applied to vertical yoke 34 shown in FIG. 1B and horizontal yoke 36 shown in FIG. 1C. 
     Input signals to the monitor drive circuitry are the 6.3 volt AC or DC signal, +5 volt DC and +50 volt DC input voltages, a VIDEO signal, a HBLANK (horizontal blank) signal, and a VERTSYNC (vertical sync) signal. 
     The +50 volt input voltage is supplied to input terminal 38 of power supply circuit 40. As shown in FIG. 1A, power supply circuit 40 includes a first regulator circuit which supplies a regulated +42 V voltage at terminal 42, and a second regulator circuit which supplies a regulated +24 V voltage at terminal 44. The first regulator circuit is connected to input terminal 38, and includes voltage regulator 46, fuse 48, capacitors C1-C4, resistors R1-R3, potentiometer P1 and diode D1. The second regulator circuit is connected to terminal 42, and includes voltage regulator 50, capacitors C5-C8, resistors R4-R6, and diode D2. 
     The +24 V voltage is supplied to high voltage unit 52, which produces a -100 volt voltage and a 15 KV voltage which is applied to anode 24 of CRT 20. 
     FIG. 1B shows the vertical deflection circuitry of the CRT monitor. The VERTSYNC signal, which is a TTL compatible signal, is received at terminal 54 by an input circuit formed by resistors R7 and R8 and buffer 56. In the preferred embodiment of the invention, buffer 56 is a high speed Schottky TTL Schmitt trigger which receives the VERTSYNC signal, trims the signal, and supplies it to the SYNC input of vertical deflection circuit 58. In the preferred embodiment of the invention shown in FIG. 1B, vertical deflection circuit 58 is a TDA 1170 integrated circuit TV vertical deflection system. 
     Deflection circuit 58, together with capacitors C9-C19, resistors R9-R20, potentiometers P2-P4, and diode D3 provide the vertical deflection drive signal to vertical yoke 34 and the vertical blanking signal (VBLANK). 
     The horizontal deflection is provided by the circuit shown in FIG. 1C. The horizontal blanking signal (HBLANK), which signal is a 50 kHz TTL compatible signal, is supplied at input terminal 60 to an input circuit including resistors R21 and R22, buffer 62, and capacitor C20. Buffer 62 is a high-speed Schottky TTL Schmitt trigger. 
     The HBLANK signal is supplied from the input circuit to the SIGNAL IN input of an integrated circuit phase locked loop 64. In the preferred embodiments of the present invention, phase locked loop 64 is a CMOS micropower phase locked loop such as the 4046 manufactured by a number of companies including RCA and Fairchild. Phase locked loop 64 includes a phase comparator and a voltage control oscillator (VCO). The phase comparator compares the HBLANK signal supplied at the SIGNAL IN input with a comparison signal supplied at the COMP IN input. The output of the phase comparator is supplied from the PH COMP II OUT output, through a low pass filter circuit including resistors R23 and R24 and capacitor C21 to the VCO IN input. Capacitor C22 is connected to the C1 A  and C1 B  terminals of phase locked loop 64. The demodulator output of phase locked loop 64 is connected through resistor R24 to ground, and the R1 terminal is connected through resistor R26 to ground. Terminal R2 of phase locked loop 64 is connected through resistor R27 and potentiometer P5 to ground. The V SS  and ZENER terminals are connected directly to ground. A +12 V reference voltage is supplied to the V DD  input of phase locked loop 64 by a circuit including resistor R28, capacitors C23 and C24, and Zener diode VR1, which is preferably a 12 volt Zener diode. 
     The output of phase locked loop 64 is supplied at the VCO OUT output, and is a square wave output signal having a frequency of 50 kHz (i.e. the frequency of the HBLANK signal). The VCO output signal is supplied to a first amplifying circuit which includes VMOS transistor Q1, capacitors C25 and C26, VMOS protection resistor R29 and current limiting resistor R30, and transformer T1. When the VCO output signal goes high, it turns on VMOS transistor Q1, which shunts VMOS protection resistor R29 and capacitor C25. The turning on of transistor Q1 causes current to be drawn from the +24 V supply, through current limiting resistor R30 and primary winding 66 of transformer T1, and then through the source-drain current path of transistor Q1. VMOS transistor Q1 is a voltage controllable nonlinear resistance, and therefore the drive signal induced in secondary winding 68 is a 50% duty pulse having a linear leading edge. This induces a signal in secondary winding 68 of transformer T1. In a preferred embodiment, primary winding 66 has fifty turns, while secondary winding 68 has ten turns. This causes a step down in voltage and a step up in current in secondary winding 68. 
     Secondary winding 68 of transformer T1 has one terminal connected to ground, and its other terminal connected to a second amplifying circuit which produces the horizontal deflection signal. The second amplifying circuit includes a high voltage, high gain monolithic Darlington amplifier transistor Q2, second transformer T2, capacitors C27-C31, current limiting resistor R31, and diode D4. As shown in FIGS. 1A and 1C, the base of transistor Q2 is connected to secondary winding 68, the emitter of transistor Q2 is connected to ground, and the collector of transistor Q1 is connected through line 70, primary winding 72 of transformer T2, and current limiting resistor R31 to the +42 volt supply. When transistor Q2 turns on, current flows through resistor R31, primary winding 72, and through line 70 to the collector-emitter current path of Q2. This causes a voltage spike (the horizontal deflection signal) to be generated which is applied to horizontal yoke 36. The leading edge of the voltage spike is linear, thereby creating a linear horizontal scan. 
     In FIG. 1C, protective diode D4 and capacitors C27 and C28 are connected between the collector and emitter of transistor Q1. Transistor Q2 and diode D4 are preferably located in the same integrated circuit, as indicated by the dashed outline. Horizontal yoke 36 has one terminal 36a connected to the collector of Q2, and its other terminal 36b connected through yoke coupling capacitors C29 and C30 to ground. 
     The collector of transistor Q2 is also connected by a circuit including resistors R32 and R33 and capacitor C32 to the COMP IN input of phase locked loop 64. Zener diode VR2, which is preferably a 10 volt Zener diode, is connected between the COMP IN input and ground, and limits the signal supplied to the COMP IN input to a maximum voltage of 10 volts. This protects the CMOS circuitry of phase locked loop 64 against high voltages induced at the collector of transistor Q2. 
     It can be seen, therefore, that the VCO output signal from phase locked loop 64 is converted to the horizontal deflection signal, and is then fed back to the COMP IN input of phase locked loop 64. The horizontal deflection signal, therefore, is locked onto the HBLANK signal, which is supplied at the SIGNAL IN input. In the preferred embodiment, in which the HBLANK signal has a frequency of 50 kHz, the horizontal deflection signal and the collector of transistor Q2 will be locked to a frequency of 50 kHz, and the leading edge of horizontal retrace pulse at the collector of Q2 will be phase locked to the leading edge of the HBLANK signal. The locking of phase of the leading edge of blanking pulse to the leading edges of retrace pulse produced at transistor Q2 negates changes in storage time of transistor Q2 or turn-off time variations over time and operating temperature. 
     The horizontal retrace signal present in primary winding 72 of transformer T2, induces a horizontal blanking signal in secondary winding 74 of transformer T2. This signal is fed through capacitors C33 and C34 and resistor R34 to the base of transistor Q3. The horizontal blanking signal at the base of Q3 is summed with the vertical blanking signal of VBLANK which is supplied through capacitor C35 and resistor R35 to the base of Q3. 
     The summed horizontal and vertical blanking signals at the base of transistor Q3 cause transistor Q3 to produce the BLANKING signal supplied to grid terminal 28 of CRT 20. The emitter of Q3 is connected to ground, while the collector is connected through resistor R36 to the +42 volt supply. Protective diode D5 is connected between the base and emitter of Q3. The collector of Q3 is also connected through capacitor C36 to terminal 28. Terminal 28 is also connected to a -100 V supply voltage from the high voltage unit 52 through a circuit including diodes D6 and D7, resistors R37 and R38, and capacitor C37. As a result of the VBLANK signal and the horizontal blanking signal supplied through transformer T2, Q3 turns on each time either a horizontal blanking or a vertical blanking signal is produced. This causes an additional -42 V to be applied to grid terminal 28 of CRT 20 causing the display to be blanked independent of state of video drive signal. Diodes D7 and C37 serve to hold grid terminal 28 negative and when power is removed from circuits keeping CRT 20 in cutoff and preventing CRT phosphor from burning due to an undeflected beam. 
     FIG. 1A also shows a video circuit, which supplies the VIDEO CONTROL signal to video grid terminal 26 of CRT 20. The embodiment shown in FIG. 1A is a black-and-white video circuit, with no gray scale. It should be understood, however, that the present invention is equally applicable to CRT monitors in which the video circuit provides gray scale. 
     The VIDEO input signal, which is a TTL compatible signal, is received at input terminal 76 of an input circuit including resistors R39 and R40, buffer 78, resistors R41 and R42, capacitor C38, and diode D8. The input circuit supplies the VIDEO input signal to the base of transistor Q4. The emitter of Q4 is connected to ground, while the collector of Q4 is connected to the video grid terminal 26 of CRT 20. 
     The voltage at the collector of Q4, when Q4 is turned off, is established by a circuit including capacitors C39-C42, resistors R43 and R44, diodes D9, D10 and D11, potentiometer P6, inductor L1, and voltage regulator 80. A pair of Zener diodes VR3 and VR4 are connected between the junction of resistors R37 and R38 and the output of voltage regulator 80. Potentiometer P6 adjusts the regulated output voltage from voltage regulator 80, and thereby adjusts the video contrast by varying video drive voltage and negative cutoff voltage via Zener diodes VR3 and VR4. Additionally the operating point or &#34;ON&#34; point of the display is ground or &#34;ZERO&#34; volts when Q4 is on. The manner of adjusting contrast is an improvement over standard techniques in that the adjustment potentiometer P6 does not carry video signals and no degradation of video results especially when remote adjustment is desired. 
     The monitor of the present invention also includes intensity and focus control potentiometers P7 and P8, which are connected to intensity control grid 30 and focus control grid 32, respectively. Voltage is supplied to potentiometers P7 and P8 for the INTENSITY and FOCUS control signals through a voltage multiplier circuit which is connected to the collector of transistor Q2 through line 82, and which includes diodes D12 and capacitors C43. 
     Table I is a list of components used in a preferred embodiment of the present invention. 
     
                       TABLE 1______________________________________C1                27 μ fC2                0.1 μ fC3                0.1 μ fC4                0.1 μ fC5                0.1 μ fC6                250 μ fC7                0.1 μ fC8                0.1 μ fC9                470 μ fC10               0.1 μ fC11               0.1 μ fC12               470 μ fC13               47pfC14               470 μ fC15               22 μ fC16               0.1 μ fC17               0.1 μ fC18               0.1 μ fC19               0.1 μ fC20               0.01 μ fC21               220pfC33               1000pfC23               10 μ fC24               0.1 μ fC25               0.001 μ fC26               18 μ fC27               0.0068 μ fC28               0.015 μ fC29               2.2 μ fC30               2.2 μ fC31               18 μ fC32               47pfC33               0.01 μ fC34               220pfC35               1 μ fC36               0.01 μ fC37               1fC38               220pfC39               4.7 μ fC40               0.1 μ fC41               0.1 μ fC42               4.7 μ fC43               0.1 μ f (each)R1                4.7K to 10KR2                243 ohmR3                698K ohmR4                3 ohmR5                4.53KR6                243 ohmR7                220 ohmR8                330 ohmR9                1 ohmR10               220KR11               20KR12               20KR14               5.62KR15               1 ohmR16               47.5KR17               10KR18               150KR19               100KR20               226KR21               220 ohmR22               330 ohmR23               4.7KR24               220KR25               47KR26               499KR27               41.2K             242.2KR28               1KR29               1KR30               560 ohmR31               1 ohmR32               47KR33               10KR34               10KR35               10KR36               10KR37               1MR38               2KR39               220 ohmR40               330 ohmR41               220 ohmR42               330 ohmR43               243 ohmR44               220 ohmPotentiometer P1  2KP2                100KP3                100KP4                50KP5                10KP6                5KP7                2.5MP8                2.5MTransistor Q1     VMP2Q2                MJ1005Q3                2N3725Q4                2N3725Diode D1          1N4004D2                1N4004D3                1N4004D4                MJ10005D5                1N4148D6                1N4004D7                1N4004D8                1N4148D9                1N4004D10               1N4148D11               1N4004D12               1N4007 (all)Zener Diode VR1   12V break downVR2               10VVR3               47VVR4               12VTransformer T1 primary winding  50 Turns secondary winding             10 TurnsTransformer T2 primary winding  200 Turns secondary winding             5 TurnsInductor L1       10 μ HVoltage Regulator 46             LM317HVVoltage Regulator 50             LM317HVVoltage Regulator 80             LM317HVCathode Ray Tube  15 inch diagonal             110° deflection             P110 PhosphorBuffer 56         74LS14Buffer 62         74LS14Buffer 78         74SO4Vertical Deflection System 58        TDA1170Phase Locked Loop 64             4046 Phase Locked LoopFuse 48           2 AmpHigh Voltage Unit 52             Erie 25BPS150______________________________________ 
    
     The preferred embodiment of the present invention using the components of Table I is a high performance CRT monitor which is very compact, lightweight and simple in construction. In the preferred embodiment shown in FIGS. 1A-1C all of the circuitry is preferably mounted on a single circuit board, and the entire monitor occupies only about 0.8 cubic feet volume. As a result, it can be fit into a small cabinet, yet is easily serviced since all of the circuitry is on a single circuit board. 
     The high performance CRT monitor of the present invention, as described in FIGS. 1A-1C and using the components of Table I, produces a horizontal scanning rate of between 49.5 to 50.5 kHz with a pulse width of 1 to 3 μs. The vertical scanning rate is 60 Hz (refresh rate) with a pulse width of 170-250 μs. The video response has a rise/fall pulse time of less than 4 ns with a nominal bandwidth of 100MHz. Horizontal synchronization is 20 to 20.5 μs, vertical synchronization is 15.8 to 21.3 ms, horizontal retrace is 5 μs, and vertical retrace is 666 μs. 
     The monitor of the present invention, therefore, provides a data matrix of 800×720 individual points (pixels) which allows a very high density of information to be displayed. Using a 5×7 dot matrix per character, eighty-eight lines of data with one hundred characters per line can be displayed. If a 7×9 matrix is used, seventy-two lines with eighty characters to the line are produced. The bandwidth of the video amplifier used in the monitor of the present invention provides much better resolution of each pixel than common CRT monitors. 
     Because the horizontal scan rate of the monitor is 50 kHz, which is over three times the common 15.75 kHz TV rate, the entire eight hundred line display is refreshed at 60 Hz. This refresh rate allows faster, more precise, lower energy phosphors to be used, which eliminate the &#34;blooming&#34; of the slower, higher energy phosphors. This also eliminates the &#34;shadowing&#34; effect of the slower phosphors which persists after the data has erased. With the 60 Hz refresh of the present invention, system designers utilizing the monitor can avoid troublesome designs required for refreshing alternate raster lines on alternate passes down the screen, and the troublesome timing problems associated with this interlacing technique. 
     The power requirements of the CRT monitor of the present invention are low. Only about 35 watts input power are required. As a result, heat generation is far less than other high performance CRT monitors. 
     The monitor exhibits very low linear distortion-less than three percent. Sharp corner focus is exhibited. 
     Although the specific preferred embodiment of the present invention discussed above operates at a nominal scan rate of 50 kHz, the present invention is applicable to higher scan rates as well. Similarly, although the specific cathode ray tube described as a fifteen inch diagonal, larger cathode ray tubes also may be used in conjunction with the present invention. 
     In conclusion, the present invention is a high performance CRT monitor which achieves high performance without requiring undue complexity and large numbers of electrical components. In the preferred embodiments of the present invention, all of the circuitry for driving the entire CRT display monitor fits a single printed circuit board. This permits an extremely compact, lightweight, and reliable unit. 
     Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention.