Abstract:
A circuit ( 43 ) generates one or more signals to be delayed by a corresponding time intervals. Tapped delay lines ( 40 ) are coupled to the signals, each tapped delay line including a plurality of delay elements ( 42 ) and having a plurality of exit points (E) through which said signal may propagate. A test circuit ( 20 ) determines a delay associated with a delay element in the circuit and selects one of said exit points of each of said tapped delay lines based on said delay.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     Not Applicable 
     STATEMENT OF FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
     Not Applicable 
     BACKGROUND OF THE INVENTION 
     1. Technical Field 
     This invention relates in general to electronic circuits and, more particularly, to circuits using delay lines. 
     2. Description of the Related Art 
     In complex electronic circuits, it is not uncommon to for circuit designers to use one or more delay lines in order to adjust the relationship between signals such that multiple signals are aligned within a predetermined time window. 
     A problem with using delay lines to align signals concerns the multiple factors that have bearing on the amount of delay provided by the delay line. First, fabrication variations will cause delay lines from chip to chip to vary. Second, operating temperature, voltage and other environmental variations can affect the delay provided by the delay lines. Accordingly, a delay line having variations at one extreme can have a significantly greater delay than a delay line at the opposite extreme. 
     A circuit designer can ameliorate some variations by careful design. Commonly, delay lines are designed such that the delayed signals will be aligned at the middle of a time window under nominal conditions to provide as much leeway on either side of nominal as possible. Further, improved processing techniques can reduce variations between chips. However, as circuits are designed to operate at higher and higher speeds, the tolerance for variations is greatly reduced and the precautions described above have less chance of success. 
     Accordingly, a need has arisen for a highly accurate delay line. 
     BRIEF SUMMARY OF THE INVENTION 
     A circuit generates one or more signals to be delayed. Tapped delay lines are coupled to the signals, each tapped delay line including a plurality of delay elements and having a plurality of exit points through which said signal may propagate. A test circuit determines a delay associated with a delay element in the circuit and selects one of said exit points of each of said tapped delay lines based on said delay. 
     The present invention provides significant advantages over the prior art. First, a high degree of accuracy can be maintained in delaying signals to align within a given time window by using actual data during operation of the circuit. Second, the accuracy can be maintained despite changing environmental conditions. Third, the addition of the test circuitry adds only a minimal amount of additional devices to a circuit. 
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
     For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
     FIG. 1 illustrates a prior art delay circuit; 
     FIG. 2 illustrates a delay element test circuit; 
     FIG. 3 illustrates an exemplary delay element test circuit; and 
     FIG. 4 illustrates a circuit using the delay element test circuit of FIG. 2 to control the delay to one or more signals. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention is best understood in relation to FIGS. 1-4 of the drawings, like numerals being used for like elements of the various drawings. 
     FIG. 1 illustrates a prior art circuit  10  using one or more delay lines to control the propagation signals through the circuit. In FIG. 1, a plurality of signals S 1 , S 2 , . . . S n , are received by respective delay lines  12  (individually referenced as delay circuits  12   1  through  12   n , having corresponding nominal delays, d 1 , d 2 , . . . d n . The output signals from each of the delay circuits are designated as dS 1 , dS 2 , . . . dS n . 
     In operation, the delays associated with each of the delay lines  12  can vary due to processing and environmental factors. Thus, especially in high frequency circuits, the output signals, dS 1 , dS 2 , . . . dS n , may not align as desired. 
     FIG. 2 illustrates a block diagram of a delay element test circuit  20 . The test circuit  20  comprises a plurality of m delay stages  22  (individually referenced as delay stages  22   1  through  22   m ) connected in series, each delay stage  22  formed of a plurality of delay elements  24 . The number of delay elements  24  in a stage  22  may vary from stage to stage. Each element in a delay stage could be, for example, a pair of inverters. The outputs (Y 1  through Y m ) of each delay stage are coupled to one bit of a latch  26  or other memory circuit. 
     In operation, a test signal T is input the first of the series connected delay stages  22 . For purpose of illustration, it will be assumed that T transitions from a low logic value to a high value upon the leading edge of a clock signal CLK and, further, that a low signal has previously propagated through all of the series connected delay stages  24 . Test signal T is high for at least one full clock period. 
     At the next leading edge of CLK, the outputs of the delay stages  22  are stored in latch  26 . At this point, if test signal T has propagated through a delay stage  22 , the output of that delay stage will be a “1”. On the other hand, if the test signal has not propagated through a test stage, the output of that test stage will be a “0”. Accordingly, the latch contains a value indicative of the speed through which the test signal propagates through the delay elements and, hence, the actual delay provided by each delay element. 
     The number of stages  22  and the number of delay elements  24  used in a given stage  22  can be tailored to the accuracy required in a given implementation. 
     FIG. 3 illustrates an exemplary test circuit  30  to demonstrate the operation of the test circuit. The first stage  22   1  has twenty six delay elements  24 , second stage  22   2  has six delay elements  24 , third stage  22   3  has eight delay elements  24 , and fourth stage  22   4  has fourteen delay elements  24 . 
     Assuming an 8 ns clock signal and an expected delay range of 0.1 to 0.35 ns per delay element, the propagation through the test circuit  30  provides the results shown in Table 1. 
     
       
         
               
             
               
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 Results 
               
             
          
           
               
                   
                   
                 Delay per 
                 Approximate % of 
               
               
                   
                 Y 1-4   
                 element (ns) 
                 expected range 
               
               
                   
                   
               
               
                   
                 0000 
                 &gt;0.31 
                 &gt;80%   
               
               
                   
                 1000 
                 &lt;=0.31, &gt;0.25 
                 80% 
               
               
                   
                 1100 
                 &lt;=0.25, &gt;0.20 
                 60% 
               
               
                   
                 1110 
                 &lt;=0.20, &gt;0.15 
                 40% 
               
               
                   
                 1111 
                 &lt;=0.15, 
                 20% 
               
               
                   
                   
               
             
          
         
       
     
     It should be noted that the values for Y 1-4  shown in Table 1 are the only valid results. Any other values are invalid and should be ignored. 
     Based on the value in latch  26 , one or more delay lines can be accurately controlled to provide an expected delay within an acceptable threshold. Since the fabrication and environmental conditions are generally fairly constant for an entire chip, one test circuit  20  can be used to control all delay lines for the chip. In certain cases, it may be desirable to use more than one test circuit  20 . 
     FIG. 4 illustrates a test circuit  20  controlling a delay line  40 . A tapped delay line  40  comprises a plurality of serially connected stages  42 , referenced individually as stages  42   1  through  42   m . Tapped delay lines are known in the prior art and are used for providing a varying degree of delay to a signal. A signal S from circuitry  43  is applied to the first stage  42   1 . The outputs E 1  through E m  of the respective stages  42   1  through  42   m  are coupled to a multiplexer  44 . The latch  26  of delay element test circuit  20  is coupled to converter  46 , which generates a binary value based on the highest order “1” value from latch  26 . The output of converter  46  is coupled to the control port of multiplexer  44  (alternatively, converter  46  could be incorporated into the control circuitry of multiplexer  44  ). 
     In operation, the result of each test performed by delay element test circuit  26  controls the number of stages  42  of the tapped delay line  40  through which signal S travels. If the test circuit  26  indicates that the delay elements in the circuit have a have a higher than nominal delay, then the multiplexer  44  will pass the output of a delay stage  42  that is early in the line  40 . If the test circuit  26  indicates that the delay elements have a shorter than nominal delay, then the multiplexer  44  will pass the output of a delay stage  42  that is late in the line  40 . If the test circuit indicates that the delay elements have a nominal delay, then the multiplexer  44  will pas the output of a delay stage  42  that is in the middle of the line  40 . 
     During the operation of a circuit, environmental conditions can change the delay through delay elements in the delay lines  40  of a circuit. The test circuitry  26  can perform a test at predetermined intervals, or upon other events (such as alarms from a temperature sensor), and dynamically change the number of stages  42  through which a signal passes, providing accurate delays through the delay lines  40  despite changing enivironmental conditions. As the value in latch  26  changes, the number of stages through which a signal passes is automatically changed, maintaining a stable amount of delay. 
     As in the case of the test circuit, the tapped delay lines  40  can have any number of stages  42  and the number of delay elements in each stage can be tailored to a given implementation. The number of stages  42  and the delay of each stage can be tailored to the particular implementation to provide the needed accuracy. 
     The present invention provides significant advantages over the prior art. First, a high degree of accuracy can be maintained in delaying signals to align within a given time window. Second, the accuracy can be maintained despite changing environmental conditions. Third, the addition of the test circuitry adds only a minimal amount of additional devices to a circuit. 
     Although the Detailed Description of the invention has been directed to certain exemplary embodiments, various modifications of these embodiments, as well as alternative embodiments, will be suggested to those skilled in the art. The invention encompasses any modifications or alternative embodiments that fall within the scope of the claims.