Abstract:
A power-on-reset circuit for delivering a power-on-reset pulse when a supply voltage ramps up from zero to a predetermined voltage includes a pull-down circuit portion for connecting an output node of the power-on-reset circuit to ground when the supply voltage reaches a predetermined upper threshold voltage and a pull-up circuit portion for connecting the output node to the supply voltage when the supply voltage reaches a predetermined upper threshold voltage. The pull-up circuit portion includes a transistor whose gate is polarized by a reference voltage taken at the terminals of a precision resistance traversed by a current delivered by a current generator, where the current is preferably a band-gap current proportional to the temperature of the circuit. The power-on-reset circuit is particularly suitable for microprocessors.

Description:
BACKGROUND OF THE INVENTION 
     1. Technical Field 
     The present invention relates to a circuit for resetting when a supply voltage appears, generally called “Power-On-Reset” circuit or “POR” circuit in the Anglo-Saxon terminology. 
     2. Description of the Related Art 
     When powered on, most of the programmed or programmable type logic circuits, in particular microprocessors, must be set in a zero state or RESET state in order to assure that their constitutive elements do not present undetermined logic states. The POR circuits, provided for this, deliver RESET signal when the supply voltage rises and reaches a first switching threshold V th1 , and release the RESET signal when the voltage reaches a second switching threshold V th2 . According to the chosen convention, the active value of the RESET signal may be 1 or 0. The release of the RESET signal corresponds to its setting to 0 in the first case and to its setting to 1 in the second case. 
     A difficulty in the design of a POR circuit, in particular in CMOS technology, is to obtain a release threshold V th2  of the RESET signal which is constant and little sensitive to the sizes of the MOS transistors, in particular the ratio W/L between the width W and the length L of the gate of the transistors. This ratio is indeed likely to vary unintentionally, from a circuit to another, because of tolerances of the manufacturing method. 
     Another difficulty is to obtain a release threshold V th2  of the RESET signal which is little sensitive to the temperature of the circuit. 
     FIG. 1 shows the electrical diagram of a conventional circuit POR1 supplied by a voltage V DD . In this diagram, the references of the PMOS transistors begin with a letter “P” and the references of the NMOS transistors begin with a letter “N”. The NMOS transistors have a threshold voltage V TN  and the PMOS transistors have a threshold voltage V TP . 
     The circuit POR 1  comprises a polarisation stage comprising, arranged in series, a ballast transistor PM 1  (comparable to a resistance) and a diode transistor NM 2 , transistor PM 1  having its gate connected to ground and transistor NM 2  having its gate fed back to its drain. The mid-point of the transistors PM 1 , NM 2  delivers a voltage V 1  applied to the gates of two other transistors PM 3 , NM 4  arranged in series, forming a switching stage. The mid-point of transistors PM 3 , NM 4  delivers an output voltage V 2  of the circuit POR 1 . The active state of the RESET signal being here by convention a logical “1”, the output voltage V 2  is applied to the input of an inverting gate INV 1  formed by two other transistors PM 5 , NM 6 , whose output delivers the RESET signal. 
     When the voltage V DD  appears, the voltage V 1  copies the voltage V DD  as long as the diode transistor NM 2  is OFF. The first switching threshold V th1  is reached when the voltage V DD  becomes equal to the threshold voltage V TN . The diode transistor NM 2  and the transistor NM 4  turn ON, the voltage V 2  passes to 0 (ground GND) and the RESET signal passes to 1. 
     The second switching threshold V th2 , or release threshold of the RESET signal, is reached by the voltage V DD  when the source-gate voltage V SG  of transistor PM 3  becomes equal to its threshold voltage V TP , the transistor PM 3  turning ON. The voltage V1 at the terminals of the diode transistor NM 2  being at this moment equal to: 
     
       
         V 1 =V TN   +ri   (1) 
       
     
     r being the series resistance of transistor NM 2  and i the current passing through it, the switching threshold V th2  is thus equal to: 
     
       
         V DD =V th2 =V TP +V 1 =V TP +V TN   +ri   (2) 
       
     
     In practice, the threshold voltages V TN  and V TP  are in the order of 0.8 V, and the voltage ri is in the order of 0.6 V. The switching threshold V th1  is thus in the order of 0.8 V and the switching threshold V th2  is in the order of 2,2 V at ambient temperature. As it can be seen in FIG. 2, the voltage of 0.8 V corresponds to a logic “1” of the RESET signal at a moment when this signal is set to 1 and the voltage of 2,2 V corresponds to a logic “1” of the RESET signal at a moment when it is brought back to 0 by the turning ON of transistor PM 3 . 
     The relation (2) shows that the switching threshold V th2  depends on the threshold voltages V TN  and V TP , as well as on the resistance r of the diode transistor NM 2  and the current i flowing through the polarization stage. However, the threshold voltages V TP  or V TN  of MOS transistors are sensitive to temperature and increase when temperature decreases. Also, the resistance r of diode transistor NM 2  depends on the ratio W/L of the gate of transistor NM 2  and the current i depends on the ratio W/L of the gate of the ballast transistor PM 1 , which determines the electric resistance of this transistor. 
     The switching threshold V th2  is thus sensitive to the ratio W/L of the gates of the switching stage transistors and to the temperature of the circuit. 
     The present invention is directed to overcome this drawback. 
     SUMMARY OF THE INVENTION 
     More particularly, a first object of the present invention is to provide a POR circuit which presents a switching threshold V th2  not much sensitive to the ratio W/L of the gates of the MOS transistors. 
     A second object of the present invention is to provide a POR circuit which presents a switching threshold V th2  not much sensitive to variations of temperature. 
     The foregoing objects are achieved as is now described. To that effect, the present invention provides a circuit for delivering a logic signal at the appearance of a supply voltage, comprising means for connecting an output node of the circuit to ground when the supply voltage reaches a first switching threshold, and means for connecting the output node to the supply voltage when the supply voltage reaches a second switching threshold, wherein the means for connecting the output node to the supply voltage comprise a switching transistor whose gate is polarized by a reference voltage taken at the terminals of a first precision resistance traversed by a current delivered by a current generator. 
     The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
     FIG. 1 previously described, depicts the electrical diagram of a conventional circuit POR 1 ; 
     FIG. 2 previously described, depicts the conventional is form of a resetting signal RESET; 
     FIG. 3 depicts the electrical diagram of a circuit POR 2  according to the invention, supplied by a voltage V DD  and arranged to deliver a resetting signal RESET at its power-on, in accordance with a preferred embodiment of the present invention; 
     FIGS. 4A to  4 D illustrate the operation of the circuit POR 2  and show electric signals appearing at the power-on of the circuit, in accordance with a preferred embodiment of the present invention; 
     FIG. 5 shows the electrical diagram of an element of the circuit POR 2 , in accordance with a preferred embodiment of the present invention; and 
     FIG. 6 shows an alternative embodiment of a switching stage of the circuit POR 2 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     According to one embodiment, the current generator delivers a current varying proportionally to temperature according to a law which is inverse of the variation law according to temperature of the threshold voltage of the switching transistor. 
     According to one embodiment, the switching transistor is a PMOS transistor. 
     According to one embodiment, the means for connecting the output node to the supply voltage comprise two transistors arranged in series receiving the reference voltage on their gates. 
     According to one embodiment, the means for connecting the output node to the supply voltage comprises a diode transistor arranged in series with the switching transistor. 
     According to one embodiment, the current generator comprises a first branch comprising a first diode, a second branch comprising a second diode arranged in series with a second precision resistance, a third branch comprising the first precision resistance, transistors arranged so that the three branches are traversed by an identical current, and transistors arranged so that the voltage appearing at the terminals of the group formed by the second precision resistance and the second diode is equal to the voltage appearing at the terminals of the first diode. 
     According to one embodiment, the means for connecting the output node to ground comprises a transistor whose gate is polarized by a diode voltage delivered by a polarization stage comprising, arranged in series, a ballast transistor, a switch transistor whose gate is polarized by the supply voltage, and a diode transistor, the diode voltage being taken between the ballast transistor and the switch transistor. 
     According to one embodiment, the circuit comprises an output inverting gate for inverting the output signal of the switching stage. 
     The present invention also relates to an integrated circuit, in particular a microprocessor, comprising a circuit of the above described type for delivering a resetting signal at its power-on. 
     With reference now to the figures, and in particular with reference to FIG. 3 the circuit POR 2  comprises a polarization stage S 1  and a switching stage S 2  The polarization stage S 1  delivers a voltage V S1  applied to the switching stage S 2  The switching stage S 2  delivers an output voltage V S2  which may be used as the RESET signal or may be applied to the input of a gate INV 1  whose output delivers the RESET signal, as shown in FIG.  3 . 
     The polarization stage S 1  comprises a ballast transistor PM 10 , a switch transistor NM 11  and a diode transistor NM 12 . The switching stage S 2  comprises a diode transistor PM 13 , a switch transistor PM 14  and a transistor NM 15 . The connections between these elements are described in table 1, last page of the description, in reference to various interconnection nodes n 1  to n 5  shown in FIG.  3 . 
     In a per se conventional manner, transistor NM 15  ensures the passage to 0 (GND) of the output voltage V S2 , and transistor PM 14  ensures the passage to 1 (V DD ) of the voltage V S2 , when transistor PM 13  is ON. To avoid short-circuits between the voltage V DD  and the ground GND, the ratio W/L (width over length) of the gate of transistor NM 15  is chosen small enough in order that transistor NM 15  presents a high serial resistance. Furthermore, the gates of the transistors NM 11 , PM 13  and PM 14  present a significant W/L ratio to achieve a small serial resistance. 
     According to the invention, the voltage V S1  delivered by the polarization stage S 1  is not used for polarizing the gate of transistor PM 14  and is only applied to the gate of transistor NM 15 . The gate of transistor PM 14  is polarized by a reference voltage V KT  taken at the terminals of a precision resistance R 1 , for example a resistance made of polysilicon or doped single crystal silicon, traversed by a current I KT  delivered by a current generator IGEN. 
     Thus, transistor PM 14  is ON when its source-drain voltage V SD  is above or equal to the sum of its threshold voltage V TP  and of voltage V KT . The diode transistor PM 13  is ON when its source-drain voltage V SD  is above or equal to its threshold voltage V TP . 
     FIGS. 4A to  4 D illustrate the operation of the circuit POR 2 . FIG. 4A shows the aspect of the supply voltage V DD  at power-on, substantially in the form of a ramp. FIG. 4B shows the aspect of the voltage V S1 . FIG. 4C shows the aspect of the reference voltage V KT  and FIG. 4D shows the RESET signal. As a numerical example, it will be considered that the threshold voltages V Tp  and V TN  of the NMOS and PMOS transistors are identical and equal to 0.8 V, and that the reference voltage V KT  is equal to 0.6 V. 
     At power-on, the voltage V S1  copies the voltage V DD  as long as said voltage is not equal to 2V TN . At a moment T 1 , the voltage V S1  reaches a first switching threshold V th1  equal to 
     
       
         V th1 =V TN   (3) 
       
     
     Transistor NM 15  turns ON, the output voltage V S2  passes to 0 and the RESET signal passes to 1, the logic “1” being equal to the voltage V DD , that is 0.8 V at this moment. The first switching threshold V th1  of the circuit POR 2  is thus equal to the one of the conventional circuit POR 1  described in the preamble. 
     At a moment T2, the voltage V S1  is equal to 2V TN . The switch transistor NM 11  closes and the diode transistor NM 12  turns ON. Transistor NM 11  presenting a small serial resistance, the voltage V S1  drops abruptly, following the conventional relation: 
     
       
         V S1 =V TN   +ri   ( 4))   
       
     
     This relation is identical to the relation (1) described in the preamble, r being the serial resistance of the diode transistor NM 12  and i the current flowing through. It will thus be appreciated that the providing of the switch transistor NM 11  in the polarization stage S 1  is an optional characteristic allowing the achievement of a more abrupt slope of the voltage V S1  near the voltage V TN , for a more distinct switching of the transistor NM 15 . The drop of the voltage V S1  which then occurs, due to the small serial resistance of transistor NM 11 , allows the limitation of the current consumption in the transistor NM 15 . 
     At a moment T 3 , the supply voltage V DD  reaches a second switching threshold V th2  equal to: 
     
       
         V th2 =2V TP +V KT   (5) 
       
     
     The transistors PM 13  and PM 14  turn ON and the output voltage V s2  becomes equal to the voltage V DD , for example 2.2 V. The RESET signal passes to 0 at the output of the gate INV 1 , as it can be seen in FIG.  4 D. 
     The relation (5) shows that the switching threshold V th2  of the circuit POR 2  according to the invention only depends on the threshold voltage V TP  of the transistors PM 13  and PM 14  and on the reference voltage V KT .The latter appears progressively between the moment T 1  and the moment T 2 , as it can be seen in FIG. 4C, and stabilizes before the moment T 3  at its reference value, for example 0.6 V. 
     In other terms, the threshold V th2  is independent of the voltage V S1  and of the W/L ratio of the gates of the transistors of the polarization stage S 1 . The first object of the invention is thus achieved. 
     The second object of the invention, which relates to the stability in temperature of the switching threshold V th2 , is achieved by the providing of a current generator IGEN delivering a current called “band-gap” current following a relation of the type: 
     
       
           I   KT   =KT   (6) 
       
     
     T being the temperature of the circuit and K a constant. The resistance R 1  and the constant K are chosen so that the increase of the threshold voltages V TP  due to the decrease of the temperature T is greatly compensated by a corresponding decrease of the reference voltage V KT , so that the switching threshold V th2  is substantially constant whatever the temperature of the circuit may be. 
     FIG. 5 shows an embodiment of the generator IGEN, comprising three branches S 3 , S 4 , S 5  supplied by the voltage V DD . The branch S 3  comprises, arranged in series, a transistor PM 20 , a transistor NM 21  and a diode D 1  at whose terminals a voltage V D1  appears. The diode D 1  is formed by N parallel PNP transistors having the reference TA i , i ranging from 1 to N, arranged in diodes (having their base connected to their collector). The branch S 4  comprises, arranged in series, a transistor PM 22 , a transistor NM 23 , a precision resistance R 2  at whose terminals a voltage V R2  appears, and a diode D 2  at whose terminals a voltage V D2  appears. The diode D 2  is formed by M parallel PNP transistors having the reference TB i , i ranging from 1 to M, arranged in diodes. The branch S 5  comprises, arranged in series, a transistor PM 24 , a transistor NM 25  driven by the RESET signal, and the precision resistance R 1 , already mentioned. The connections between these elements are described in table 2, last page of the description, with reference to the interconnection nodes n 5  to n 11  shown in FIG.  5 . 
     The generator IGEN operates as follows. The transistors PM 20 , PM 22 , PM 24  are arranged in current mirrors and the three branches S 3 , S 4 , S 5  are traversed by the same current I KT . The transistors NM 21  and NM 23  have their gates connected together and provide the equality of voltage V D1  and voltage V R  at the terminals of resistance R 2  and diode D 2 , so that: 
     
       
         V D1 −V D2 =V R −V D2 =(V D2 +V R2 )−V D2 =V R2   (7) 
       
     
     The current I KT  being identical in the diodes D 1  and D 2 , it follows that: 
     
       
           I   KT   =N I   D1i   ==M I   D2i   (8) 
       
     
     I D1i  and I D2i  being the currents flowing through each of the N and M elementary diodes forming the diodes D 1  and D 2 . 
     The current flowing through a diode being given by the general relation: 
     
       
           I =Is exp. ( q  V/ /kT )  (9) 
       
     
     the following equality is deduced: 
     
       
           I   KT   =N  Is exp. ( q  V D1   /kT )= M  Is exp. ( q  V D2   /kT )  (10) 
       
     
     from where it results that: 
     
       
         V D1 −V D2 =( kT/q )ln( M/N )  (11) 
       
     
     The combination of the relations (7) and (11) gives the current I KT  and the voltage V KT  as a function of the resistance R 2 : 
     
       
           I   KT =(1 /R   2 )( kT/q )ln( M/N )  (12) 
       
     
     
       
           V   KT =( R   1 / R   2 )( kT/q )ln( M/N )  (13) 
       
     
     The constant K mentioned above is thus equal to: 
       K =(1 /R   2 )( k/q )ln( M/N )  (14) 
     and may be adjusted by means of the parameters N, M and resistance R 2 . 
     In FIG. 5, the transistor NM 25  is an optional element of the generator IGEN and allows, after the passage of the second threshold V th2 , the forcing to zero of the voltage V KT  and the locking of the RESET signal. 
     It will be readily apparent to the person skilled in the art that the circuit POR 2  according to the invention is likely to have various alternatives and embodiments, in particular regarding the generator IGEN and the design of the switching stage S 2  As an example, FIG. 6 shows an embodiment S 2 ′ of the switching stage where the gates of the transistors PM 13  and PM 14  are both biased by the reference voltage V KT , the switching threshold V th2  being in this case equal to: 
     
       
         V th2 =2(V TP +V KT )  (15) 
       
     
     each transistor PM 13 , PM 14  having to receive, between its source and its drain, a voltage equal to (V TP +V KT ) for switching from the state OFF to the state ON. 
     
       
         
               
             
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 structure of the circuit POR2 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 Transistors 
                 Gate (G) 
                 Drain (D) 
                 Source (S) 
               
               
                   
               
               
                 PM 10   
                 ground (GNL) 
                 node n1 
                 voltage V DD   
               
               
                 NM 11   
                 voltage V DD   
                 node n1 
                 node n2 
               
               
                 NM 12   
                 node n2 
                 node n2 
                 ground (GND) 
               
               
                 PM 13   
                 node n4 
                 node n4 
                 voltage V DD   
               
               
                 PM 14   
                 node n5 
                 node n3 
                 node n4 
               
               
                 NM 15   
                 node n1 
                 node n3 
                 node GND 
               
               
                   
                 (voltage V S1 ) 
                 (voltage V S2 ) 
               
               
                   
               
               
                 Other elements 
                 Input 
                 Output 
                 Supply voltage 
               
               
                   
               
               
                 gate INV1 
                 node n3 
                 delivers the 
                 V DD   
               
               
                   
                 (voltage V S2 ) 
                 signal RESET 
               
               
                 generator IGEN 
                 V DD   
                 node n5 
                 V DD   
               
               
                   
                   
                 (delivers I KT ) 
               
               
                 resistance R1 
                 node n5 
                 ground (GND) 
                 I KT   
               
               
                   
                 (delivers V KT ) 
               
               
                   
               
             
          
         
       
     
     
       
         
               
             
               
               
               
               
             
           
               
                 TABLE 2 
               
               
                   
               
               
                 structure of the generator IGEN 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 MOS 
                 Gate (G) 
                 Drain (D) 
                 Source (S) 
               
               
                 transistors 
               
               
                   
               
               
                 PM 20   
                 n6 
                 n7 
                 V DD   
               
               
                 NM 21   
                 n7 
                 n7 
                 n8 
               
               
                 PM 22   
                 n6 
                 n6 
                 VDD 
               
               
                 NM 23   
                 n7 
                 n6 
                 n9 
               
               
                 PM 24   
                 n6 
                 n11 
                 V DD   
               
               
                 NM 25   
                 receives the 
                 n11 
                 n5 
               
               
                   
                 signal RESET 
               
               
                   
               
               
                 PNP 
                 Base 
                 Emitter 
                 Collector 
               
               
                 Transistors 
               
               
                   
               
               
                 TA i  (i = 1 to N) 
                 ground (GND) 
                 n8 
                 GND 
               
               
                 TB i  (i = 1 to M) 
                 ground (GND) 
                 n10 
                 GND 
               
               
                   
               
               
                 Resistances 
                 input 
                 output 
               
               
                   
               
               
                 Resistance R1 
                 n5 
                 ground (GND) 
               
               
                   
                 (delivers V KT ) 
               
               
                 Resistance R2 
                 n9 
                 n10 
               
               
                   
               
             
          
         
       
     
     It is important to note that while the present invention has been described in the context of a fully functional data processing system and/or network, those skilled in the art will appreciate that the mechanism of the present invention is capable of being distributed in the form of a computer usable medium of instructions in a variety of forms, and that the present invention applies equally regardless of the particular type of signal bearing medium used to actually carry out the distribution. Examples of computer usable mediums include: nonvolatile, hard-coded type mediums such as read only memories (ROMs) or erasable, electrically programmable read only memories (EEPROMs), recordable type mediums such as floppy disks, hard disk drives and CD-ROMs, and transmission type mediums such as digital and analog communication links. 
     While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.