Abstract:
A retrograde and periphery well structure for a CMOS imager is disclosed which improves the quantum efficiency and signal-to-noise ratio of the photosensing portion imager. The retrograde well comprises a doped region with a vertically graded dopant concentration that is lowest at the substrate surface, and highest at the bottom of the well. A single retrograde well may have a single pixel sensor cell, multiple pixel sensor cells, or even an entire array of pixel sensor cells formed therein. The highly concentrated region at the bottom of the retrograde well repels signal carriers from the photosensor so that they are not lost to the substrate, and prevents noise carriers from the substrate from diffusing up into the photosensor. The periphery well contains peripheral logic circuitry for the imager. By providing retrograde and peripheral wells, circuitry in each can be optimized. Also disclosed are methods for forming the retrograde and peripheral well.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]    This application is a continuation-in-part of U.S. application Ser. No. 09/334,261 filed Jun. 16, 1999 (attorney docket number M4065.0107), entitled “Retrograde Well Structure For A CMOS Imager” the disclosure of which is incorporated by reference herein. 
     
    
     
       FIELD OF THE INVENTION  
         [0002]    The present invention relates generally to improved semiconductor imaging devices and in particular to a silicon imaging device that can be fabricated using a standard CMOS process.  
         BACKGROUND OF THE INVENTION  
         [0003]    There are a number of different types of semiconductor-based imagers, including charge coupled devices (CCDs), photodiode arrays, charge injection devices and hybrid focal plane arrays. CCD technology is often employed for image acquisition and enjoys a number of advantages which makes it the incumbent technology, particularly for small size imaging applications. CCDs are capable of large formats with small pixel size and they employ low noise charge domain processing techniques.  
           [0004]    However, CCD imagers also suffer from a number of disadvantages. For example, they are susceptible to radiation damage, they exhibit destructive read-out over time, they require good light shielding to avoid image smear and they have a high power dissipation for large arrays. Additionally, while offering high performance, CCD arrays are difficult to integrate with CMOS processing in part due to a different processing technology and to their high capacitances, complicating the integration of on-chip drive and signal processing electronics with the CCD array. While there have been some attempts to integrate on-chip signal processing with CCD arrays, these attempts have not been entirely successful. CCDs also must transfer an image by line charge transfers from pixel to pixel, requiring that the entire array be read out into a memory before individual pixels or groups of pixels can be accessed and processed. This takes time. CCDs may also suffer from incomplete charge transfer from pixel to pixel which results in image smear.  
           [0005]    Because of the inherent limitations in CCD technology, there is an interest in CMOS imagers for possible use as low cost imaging devices. A fully compatible CMOS sensor technology enabling a higher level of integration of an image array with associated processing circuits would be beneficial to many digital applications such as, for example, in cameras, scanners, machine vision systems, vehicle navigation systems, video telephones, computer input devices, surveillance systems, auto focus systems, star trackers, motion detection systems, image stabilization systems and data compression systems for high-definition television.  
           [0006]    The advantages of CMOS imagers over CCD imagers are that CMOS imagers have a low voltage operation and low power consumption; CMOS imagers are compatible with integrated on-chip electronics (control logic and timing, image processing, and signal conditioning such as A/D conversion); CMOS imagers allow random access to the image data; and CMOS imagers have lower fabrication costs as compared with the conventional CCD because standard CMOS processing techniques can be used. Additionally, low power consumption is achieved for CMOS imagers because only one row of pixels at a time needs to be active during the readout and there is no charge transfer (and associated switching) from pixel to pixel during image acquisition. On-chip integration of electronics is particularly advantageous because of the potential to perform many signal conditioning functions in the digital domain (versus analog signal processing) as well as to achieve a reduction in system size and cost.  
           [0007]    A CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including either a photogate, photoconductor or a photodiode overlying a substrate for accumulating photo-generated charge in the underlying portion of the substrate. A readout circuit is connected to each pixel cell and includes at least an output field effect transistor formed in the substrate and a charge transfer section formed on the substrate adjacent the photogate, photoconductor or photodiode having a sensing node, typically a floating diffusion node, connected to the gate of an output transistor. The imager may include at least one electronic device such as a transistor for transferring charge from the underlying portion of the substrate to the floating diffusion node and one device, also typically a transistor, for resetting the node to a predetermined charge level prior to charge transference.  
           [0008]    In a CMOS imager, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) transfer of charge to the floating diffusion node accompanied by charge amplification; (4) resetting the floating diffusion node to a known state before the transfer of charge to it; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge. Photo charge may be amplified when it moves from the initial charge accumulation region to the floating diffusion node. The charge at the floating diffusion node is typically converted to a pixel output voltage by a source follower output transistor. The photosensitive element of a CMOS imager pixel is typically either a depleted p-n junction photodiode or a field induced depletion region beneath a photogate. For photodiodes, image lag can be eliminated by completely depleting the photodiode upon readout.  
           [0009]    CMOS imagers of the type discussed above are generally known as discussed, for example, in Nixon et al., “256×256 CMOS Active Pixel Sensor Camera-on-a-Chip,” IEEE Journal of Solid-State Circuits, Vol. 31(12), pp.2046-2050 (1996); Mendis et al., “CMOS Active Pixel Image Sensors,” IEEE Transactions on Electron Devices, Vol. 41(3), pp. 452-453 (1994), as well as U.S. Pat. No. 5,708,263 and U.S. Pat. No. 5,471,515, which are herein incorporated by reference.  
           [0010]    To provide context for the invention, an exemplary CMOS imaging circuit is described below with reference to FIG. 1. The circuit described below, for example, includes a photogate for accumulating photo-generated charge in an underlying portion of the substrate. It should be understood that the CMOS imager may include a photodiode or other image to charge converting device, in lieu of a photogate, as the initial accumulator for photo-generated charge.  
           [0011]    Reference is now made to FIG. 1 which shows a simplified circuit for a pixel of an exemplary CMOS imager using a photogate and having a pixel photodetector circuit  14  and a readout circuit  60 . It should be understood that while FIG. 1 shows the circuitry for operation of a single pixel, that in practical use there will be an M×N array of pixels arranged in rows and columns with the pixels of the array accessed using row and column select circuitry, as described in more detail below.  
           [0012]    The photodetector circuit  14  is shown in part as a cross-sectional view of a semiconductor substrate  16  typically a p-type silicon, having a surface well of p-type material  20 . An optional layer  18  of p-type material may be used if desired, but is not required. Substrate  16  may be formed of, for example, Si, SiGe, Ge, or GaAs. Typically the entire substrate  16  is p-type doped silicon substrate and may contain a surface p-well  20  (with layer  18  omitted), but many other options are possible, such as, for example p on p− substrates, p on p+ substrates, p-wells in n-type substrates or the like. The terms wafer or substrate used in the description includes any semiconductor-based structure having an exposed surface in which to form the circuit structure used in the invention. Wafer and substrate are to be understood as including silicon-on-insulator (SOI) technology, silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a wafer or substrate in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure or foundation.  
           [0013]    An insulating layer  22  such as, for example, silicon dioxide is formed on the upper surface of p-well  20 . The p-type layer may be a p-well formed in substrate  16 . A photogate  24  thin enough to pass radiant energy or of a material which passes radiant energy is formed on the insulating layer  22 . The photogate  24  receives an applied control signal PG which causes the initial accumulation of pixel charges in n+ region  26 . The n+ type region  26 , adjacent one side of photogate  24 , is formed in the upper surface of p-well  20 . A transfer gate  28  is formed on insulating layer  22  between n+ type region  26  and a second n+ type region  30  M formed in p-well  20 . The n+ regions  26  and  30  and transfer gate  28  form a charge transfer transistor  29  which is controlled by a transfer signal TX. The n+ region  30  is typically called a floating diffusion region. It is also a node for passing charge accumulated thereat to the gate of a source follower transistor  36  described below.  
           [0014]    A reset gate  32  is also formed on insulating layer  22  adjacent and between n+ type region  30  and another n+ region  34  which is also formed in p-well  20 . The reset gate  32  and n+ regions  30  and  34  form a reset transistor  31  which is controlled by a reset signal RST. The n+ type region  34  is coupled to voltage source V DD , e.g., 5 volts. The transfer and reset transistors  29 ,  31  are n-channel transistors as described in this implementation of a CMOS imager circuit in a p-well. It should be understood that it is possible to implement a CMOS imager in an n-well in which case each of the transistors would be p-channel transistors. It should also be noted that while FIG. 1 shows the use of a transfer gate  28  and associated transistor  29 , this structure provides advantages, but is not required.  
           [0015]    Photodetector circuit  14  also includes two additional n-channel transistors, source follower transistor  36  and row select transistor  38 . Transistors  36 ,  38  are coupled in series, source to drain, with the source of transistor  36  also coupled over lead  40  to voltage source V DD  and the drain of transistor  38  coupled to a lead  42 . The drain of row select transistor  38  is connected via conductor  42  to the drains of similar row select transistors for other pixels in a given pixel row. A load transistor  39  is also coupled between the drain of transistor  38  and a voltage source V SS , e.g. 0 volts. Transistor  39  is kept on by a signal V LN  applied to its gate.  
           [0016]    The imager includes a readout circuit  60  which includes a signal sample and hold (S/H) circuit including a S/H n-channel field effect transistor  62  and a signal storage capacitor  64  connected to the source follower transistor  36  through row transistor  38 . The other side of the capacitor  64  is connected to a source voltage V SS . The upper side of the capacitor  64  is also connected to the gate of a p-channel output transistor  66 . The drain of the output transistor  66  is connected through a column select transistor  68  to a signal sample output node V OUTS  and through a load transistor  70  to the voltage supply V DD . A signal called “signal sample and hold” (SHS) briefly turns on the S/H transistor  62  after the charge accumulated beneath the photogate electrode  24  has been transferred to the floating diffusion node  30  and from there to the source follower transistor  36  and through row select transistor  38  to line  42 , so that the capacitor  64  stores a voltage representing the amount of charge previously accumulated beneath the photogate electrode  24 .  
           [0017]    The readout circuit  60  also includes a reset sample and hold (S/H) circuit including a S/H transistor  72  and a signal storage capacitor  74  connected through the S/H transistor  72  and through the row select transistor  38  to the source of the source follower transistor  36 . The other side of the capacitor  74  is connected to the source voltage V SS . The upper side of the capacitor  74  is also connected to the gate of a p-channel output transistor  76 . The drain of the output transistor  76  is connected through a p-channel column select transistor  78  to a reset sample output node V OUTR a nd through a load transistor  80  to the supply voltage V DD . A signal called “reset sample and hold” (SHR) briefly turns on the S/H transistor  72  immediately after the reset signal RST has caused reset transistor  31  to turn on and reset the potential of the floating diffusion node  30 , so that the capacitor  74  stores the voltage to which the floating diffusion node  30  has been reset.  
           [0018]    The readout circuit  60  provides correlated sampling of the potential of the floating diffusion node  30 , first of the reset charge applied to node  30  by reset transistor  31  and then of the stored charge from the photogate  24 . The two samplings of the diffusion node  30  charges produce respective output voltages V OUTR  and V OUTS  of the readout circuit  60 . These voltages are then subtracted (V OUTS −V OUTD ) by subtractor  82  to provide an output signal terminal  81  which is an image signal independent of pixel to pixel variations caused by fabrication variations in the reset voltage transistor  31  which might cause pixel to pixel variations in the output signal.  
           [0019]    [0019]FIG. 2 illustrates a block diagram for a CMOS imager having a pixel array  200  with each pixel cell being constructed in the manner shown by element  14  of FIG. 1. FIG. 4 shows a 2×2 portion of pixel array  200 . Pixel array  200  comprises a plurality of pixels arranged in a predetermined number of columns and rows. The pixels of each row in array  200  are all turned on at the same time by a row select line, e.g., line  86 , and the pixels of each column are selectively output by a column select line, e.g., line  42 . A plurality of rows and column lines are provided for the entire array  200 . The row lines are selectively activated by the row driver  210  in response to row address decoder  220  and the column select lines are selectively activated by the column driver  260  in response to column address decoder  270 . Thus, a row and column address is provided for each pixel. The CMOS imager is operated by the control circuit  250  which controls address decoders  220 ,  270  for selecting the appropriate row and column lines for pixel readout, and row and column driver circuitry  210 ,  260  which apply driving voltage to the drive transistors of the selected row and column lines.  
           [0020]    [0020]FIG. 3 shows a simplified timing diagram for the signals used to transfer charge out of photodetector circuit  14  of the FIG. 1 CMOS imager. The photogate signal PG is nominally set to 5V and pulsed from 5V to 0V during integration. The reset signal RST is nominally set at 2.5V. As can be seen from the figure, the process is begun at time t 0  by briefly pulsing reset voltage RST to 5V. The RST voltage, which is applied to the gate  32  of reset transistor  31 , causes transistor  31  to turn on and the floating diffusion node  30  to charge to the V DD  voltage present at n+ region  34  (less the voltage drop V TH  of transistor  31 ). This resets the floating diffusion node  30  to a predetermined voltage (V DD −V TH ). The charge on floating diffusion node  30  is applied to the gate of the source follower transistor  36  to control the current passing through transistor  38 , which has been turned on by a row select (ROW) signal, and load transistor  39 . This current is translated into a voltage on line  42  which is next sampled by providing a SHR signal to the S/H transistor  72  which charges capacitor  74  with the source follower transistor output voltage on line  42  representing the reset charge present at floating diffusion node  30 . The PG signal is next pulsed to  0  volts, causing charge to be collected in n+ region  26 .  
           [0021]    A transfer gate voltage TX, similar to the reset pulse RST, is then applied to transfer gate  28  of transistor  29  to cause the charge in n+ region  26  to transfer to floating diffusion node  30 . It should be understood that for the case of a photogate, the transfer gate voltage TX may be pulsed or held to a fixed DC potential. For the implementation of a photodiode with a transfer gate, the transfer gate voltage TX must be pulsed. The new output voltage on line  42  generated by source follower transistor  36  current is then sampled onto capacitor  64  by enabling the sample and hold switch  62  by signal SHS. The column select signal is next applied to transistors  68  and  70  and the respective charges stored in capacitors  64  and  74  are subtracted in subtractor  82  to provide a pixel output signal at terminal  81 . It should also be noted that CMOS imagers may dispense with the transfer gate  28  and associated transistor  29 , or retain these structures while biasing the transfer transistor  29  to an always “on” state.  
           [0022]    The operation of the charge collection of the CMOS imager is known in the art and is described in several publications such as Mendis et al., “Progress in CMOS Active Pixel Image Sensors,” SPIE Vol. 2172, pp. 19-29 (1994); Mendis et al., “CMOS Active Pixel Image Sensors for Highly Integrated Imaging Systems,” IEEE Journal of Solid State Circuits, Vol. 32(2) (1997); and Eric R. Fossum, “CMOS Image Sensors: Electronic Camera on a Chip,” IEDM Vol. 95, pp. 17-25 (1995) as well as other publications. These references are incorporated herein by reference.  
           [0023]    Quantum efficiency is a problem in some imager applications due to the diffusion of signal carriers out of the photosite and into the substrate, where they become effectively lost. The loss of signal carriers results in decreased signal strength, increased cross talk, and the reading of an improper value for the adjacent pixels.  
           [0024]    There is needed, therefore, an improved pixel sensor cell for use in an imager that exhibits improved quantum efficiency, a better signal-to-noise ratio, and reduced cross talk. A method of fabricating a pixel sensor cell exhibiting these improvements is also needed.  
         SUMMARY OF THE INVENTION  
         [0025]    The present invention provides a pixel sensor cell formed in a retrograde well in a semiconductor substrate having improved quantum efficiency, an improved signal-to-noise ratio, and reduced cross talk. The retrograde well comprises a doped region with a vertically graded dopant concentration that is lowest at or near the substrate surface, and highest at the bottom of the well. The retrograde well would have an entire array of pixels formed therein, and may also have peripheral circuitry formed therein. If the peripheral circuitry is formed in the retrograde well, the well may have a different dopant profile in the peripheral region than in the array region. The highly concentrated region at the bottom of the retrograde well reflects signal carriers back to the photosensor so that they are not lost to the substrate. Also provided are methods for forming a pixel sensor cell in the retrograde well of the present invention.  
           [0026]    The present invention also relates to a pixel sensor cell formed in a retrograde well in a semiconductor substrate together with imager periphery formed in an adjacent shallow periphery well. The retrograde well comprises a doped region with a vertically graded dopant concentration that is lowest at or near the substrate surface, and highest at the bottom of the well. The retrograde well would have an entire array of pixels formed therein. The shallow periphery well would have peripheral circuitry formed therein. The shallow periphery well has a different dopant profile than the retrograde well in the array region. The shallow periphery well has a highly concentrated region at the surface of the substrate which then gradually diminishes into the substrate.  
           [0027]    Additional advantages and features of the present invention will be apparent from the following detailed description and drawings which illustrate preferred embodiments of the invention.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0028]    [0028]FIG. 1 is a representative circuit of a CMOS imager.  
         [0029]    [0029]FIG. 2 is a block diagram of a CMOS pixel sensor chip.  
         [0030]    [0030]FIG. 3 is a representative timing diagram for the CMOS imager.  
         [0031]    [0031]FIG. 4 is a representative pixel layout showing a 2×2 pixel layout.  
         [0032]    [0032]FIG. 5 is a cross-sectional view of two pixel sensor cells according to a first structural embodiment of the present invention.  
         [0033]    [0033]FIG. 6 is a graph depicting the dopant concentration as a function of the depth of the retrograde well.  
         [0034]    [0034]FIG. 7 is a cross-sectional view of a semiconductor wafer undergoing the process of a first process embodiment of the invention.  
         [0035]    [0035]FIG. 8 shows the wafer of FIG. 7 at a processing step subsequent to that shown in FIG. 7.  
         [0036]    [0036]FIG. 9 is a cross-sectional view of a semiconductor wafer undergoing the process of a second process embodiment of the invention.  
         [0037]    [0037]FIG. 10 shows the wafer of FIG. 9 at a processing step subsequent to that shown in FIG. 9.  
         [0038]    [0038]FIG. 11 is a cross-sectional view of two pixel sensor cells according to second structural embodiment of the present invention.  
         [0039]    [0039]FIG. 12 is a graph depicting the dopant concentration as a function of the depth of the periphery well.  
         [0040]    [0040]FIG. 13 is a cross-sectional view of a semiconductor wafer undergoing the process of a third process embodiment of the invention.  
         [0041]    [0041]FIG. 14 shows the wafer of FIG. 13 at a processing step subsequent to that shown in FIG. 13.  
         [0042]    [0042]FIG. 15 is an illustration of a computer system having a CMOS imager according to the present invention. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0043]    In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These to embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized, and that structural, logical and electrical changes may be made without departing from the spirit and scope of the present invention.  
         [0044]    The terms “wafer” and “substrate” are to be understood as including silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a “wafer” or “substrate” in the following description, previous process steps may have been utilized to form regions, junctions or material layers in or on the base semiconductor structure or foundation. In addition, the semiconductor need not be silicon-based, but could be based on silicon-germanium, germanium, or gallium arsenide. For exemplary purposes an imager formed of n-channel devices in a retrograde p-well is illustrated and described, but it should be understood that the invention is not limited thereto, and may include other combinations such as an imager formed of p-channel devices in a retrograde n-well.  
         [0045]    The term “pixel” refers to a picture element unit cell containing a photosensor and transistors for converting electromagnetic radiation to an electrical signal. For purposes of illustration, a representative pixel is illustrated in the figures and description herein, and typically fabrication of all pixels in an imager will proceed simultaneously in a similar fashion. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.  
         [0046]    The structure of pixel cells  14  formed in retrograde wells  20  of the first structured embodiment are shown in more detail in FIG. 5. A pixel cell  14  may be formed in a substrate  16  having a retrograde layer or well  20  of a first conductivity type, which for exemplary purposes is treated as p-type. The retrograde well  20  has a vertically graded dopant concentration that is lowest at or near the substrate surface, and highest at the bottom of the well, as is shown in FIG. 6. The dopant concentration at the top of the retrograde well  20  is within the range of about 5×10 14  to about 1×10 17  atoms per cm 3 , and is preferably within the range of about 1×10 15  to about 5×10 16  atoms per cm 3 , and most preferably is about 5×10 15  atoms per cm 3 . At the bottom of the retrograde well  20 , the dopant concentration is within the range of about 1×10 16  to about 2×10 18  atoms per cm 3 , and is preferably within the range of about 5×10 16  to about 1×10 18  atoms per cm 3 , and most preferably is about 3×10 17  atoms per cm 3 . A single retrograde well  20  as depicted in FIG. 5, spans all pixels in the array of pixels. At the surface, there may be V t , adjusting dopants that may cause the dopant concentration to also rise immediately adjacent to the surface to set the transistor V t s.  
         [0047]    A second retrograde well (not shown) may be formed in the substrate  16 , and may have peripheral circuitry, such as, e.g., logic circuitry, formed therein. This second well may be doped similarly or differently from the first retrograde well  20 , for example, the first retrograde well  20  may be doped to a first dopant level such as about 3×10 17  atoms per cm 3  at the bottom of the well and the second well may be doped to a second dopant level such as 5×10 16  at the bottom of the well. At the surface in this second retrograde well, there may additionally be implants to control the V t s of the transistors in this second well.  
         [0048]    The pixel cell  14  includes: a photogate  24 , a transfer gate  28  for transfer transistor  29 , and a reset transistor gate  32  for the reset transistor  31 . In addition, the photosensitive element in the pixel cell  14  is shown to be a photogate  24 , but other photosensitive elements such as a photodiode or a photoconductor could be used. The source follower transistor and the row select transistor are shown schematically in FIG. 5. The transfer gate  28  and the reset gate  32  include a gate oxide layer  106  on the retrograde well  20 , and a conductive layer  108  of doped polysilicon, tungsten, or other suitable material over the gate oxide layer  106 . An insulating cap layer  110  of, for example, silicon dioxide, silicon nitride, or ONO (oxide-nitride-oxide), may be formed if desired; also a more conductive layer such as a silicide layer (not shown) may be used between the conductive layer  108  and the cap  110  of the transfer gate stack  28 , source follower gate, row select gate, and reset gate stack  32 , if desired. Insulating sidewalls  112  are also formed on the sides of the gate stacks  28 ,  32 . These sidewalls may be formed of, for example, silicon dioxide or silicon nitride or ONO. The transfer gate  28  is not required but may advantageously be included. The photogate  24  is a semitransparent conductor and is shown as an overlapping gate. A second gate oxide  105  is provided over the retrograde well and under the photogate.  
         [0049]    Underlying the photogate  24  and gate oxide layer  105  is a doped region  26  called the photosite, where photogenerated charges are stored. In between the reset transistor gate  32  and the transfer gate  28  is a doped region  30  that is the source for the reset transistor  31 , and on the other side of the reset transistor gate  32  is a doped region  34  that acts as a drain for the reset transistor  31 . The doped regions  26 ,  30 ,  34  are doped to a second conductivity type, which for exemplary purposes is treated as n-type. The second doped region  30  is a floating diffusion region, sometimes also referred to as a floating diffusion node, and it serves as the source for the reset transistor  31 . The third doped region  34  is the drain of the reset transistor  31 , and is also connected to voltage source Vdd.  
         [0050]    As shown in FIG. 5, as light radiation  12  in the form of photons strikes the photosite  26 , photo-energy is converted to electrical signals, i.e., carriers  120 , which are stored in the photosite  26 . The absorption of light creates electron-hole pairs. For the case of an n-doped photosite in a p-well, it is the electrons that are stored. For the case of a p-doped photosite in an n-well, it is the holes that are stored. In the exemplary pixel cell  14  having n-channel devices formed in a p-type retrograde well  20 , the carriers  120  stored in the photosite  26  are electrons. The retrograde well  20  acts to reduce carrier loss to the substrate  16  by forming a concentration gradient that modifies the band diagram and serves to reflect electrons back towards the photosite  26 , thereby increasing quantum efficiency of the pixel  14 .  
         [0051]    The retrograde well  20  is manufactured through a process in a first process embodiment of the invention described as follows, and illustrated by FIGS. 7 and 8. Referring now to FIG. 7, a substrate  16 , which may be any of the types of substrates described above, is provided. Retrograde well  20  is then formed by suitable means such as blanket ion implantation of the entire wafer. The retrograde well  20  may also be implanted at a later stage of the process such as after field oxide formation. The implant may be patterned so that the array well and the periphery logic well could have different doping profiles.  
         [0052]    Ion implantation is performed by placing the substrate  16  in an ion implanter, and implanting appropriate dopant ions into the substrate  16  at an energy of 100 keV to 5 MeV to form retrograde wells  20  having a dopant concentration that is lowest at or near the surface, and highest at the bottom of the well. The dopant concentration at the top of the retrograde well  20  is within the range of about 5×10 14  to about 1×10 17  atoms per cm 3 , and is preferably within the range of about 1×10 15  to about 5×10 16  atoms per cm 3 , and most preferably is about 5×10 15  atoms per cm 3 . At the bottom of the retrograde well  20 , the dopant concentration is within the range of about 1×10 16  to about 2×10 18  atoms per cm 3 , and is preferably within the range of about 5×10 16  to about 1×10 18  atoms per cm 3 , and most preferably is about 3×10 17  atoms per cm 3 . If the retrograde well is to be a p-type well, a p-type dopant, such as boron, is implanted, and if the well  20  is to be an n-type well, an n-type dopant, such as arsenic, antimony, or phosphorous is implanted. The resultant structure is shown in FIG. 8. Multiple high energy implants may be used to tailor the profile of the retrograde well  20 . Additionally, there may be V t  adjusting implants near the surface to set the V t s of the transistors in the well. For simplicity, FIG. 6 does not show any V t  adjusting implants near the surface that could cause the dopant concentration immediately adjacent to the surface to elevate.  
         [0053]    Referring now to FIGS. 9 and 10, which illustrate a second process embodiment of the invention, field oxide regions  114  may be formed around the pixel cell  14  prior to the formation of the retrograde well  20 . The field oxide regions are formed by any known technique such as thermal oxidation of the underlying silicon in a LOCOS process or by etching trenches and filling them with oxide in an STI process. Following field oxide  114  formation, the retrograde wells  20  may then be formed by blanket implantation as shown in FIG. 10 or by masked implantation (not shown).  
         [0054]    Subsequent to formation of the retrograde well  20 , by either of the processes described above, the devices of the pixel sensor cell  14 , including the photogate  24 , the transfer gate  28 , reset transistor  31 , the source follower  36  and the row select transistor  38 , all shown in FIG. 5, are formed by well-known methods. Doped regions  26 ,  30 , and  34  are formed in the retrograde well  20 , and are doped to a second conductivity type, which for exemplary purposes will be considered to be n-type. The doping level of the doped regions  26 ,  30 ,  34  may vary but should be higher than the doping level at the top of the retrograde well  20 , and greater than 5×10 16  atoms per cm 3 . If desired, multiple masks and resists may be used to dope these regions to different levels. Doped region  26  may be variably doped, such as either n+ or n− for an n-channel device. Doped region  34  should be strongly doped, i.e., for an n-channel device, the doped region  34  will be doped as n+. Doped region  30  is typically strongly doped (n+), and would not be lightly doped (n−) unless a buried contact is also used.  
         [0055]    The pixel sensor cell  14  is essentially complete at this stage, and conventional processing methods may be used to form contacts and wiring to connect gate lines and other connections in the pixel cell  14 . For example, the entire surface may then be covered with a passivation layer of, e.g., silicon dioxide, BSG, PSG, or BPSG, which is CMP planarized and etched to provide contact holes, which are then metallized to provide contacts to the photogate, reset gate, and transfer gate. Conventional multiple layers of conductors and insulators may also be used to interconnect the structures in the manner shown in FIG. 1.  
         [0056]    Reference is now made to FIG. 11. The structure of pixel cells  314  formed in retrograde wells  320  and logic circuitry  360  formed in periphery wells  350  of a second structural embodiment are shown in more detail in FIG. 11. A pixel cell  314  may be formed in a substrate  316  having a retrograde layer or well  320  of a first conductivity type, which for exemplary purposes is treated as p-type. The retrograde well  320  has a vertically graded dopant concentration that is lowest at or near the substrate surface, and highest at the bottom of the well, as is shown in FIG. 6. The dopant concentration at the top of the retrograde well  320  is within the range of about 5×10 14  to about 1×10 17  atoms per cm 3 , and is preferably within the range of about 1×10 15  to about 5×10 16  atoms per cm 3 , and most preferably is about 5×10 15  atoms per cm 3 . At the bottom of the retrograde well  320 , the dopant concentration is within the range of about 1×10 16  to about 2×10 18  atoms per cm 3 , and is preferably within the range of about 5×10 16  to about 1×10 18  atoms per cm 3 , and most preferably is about 3×10 17  atoms per cm 3 .  
         [0057]    A periphery well  350  is formed in the substrate  316 , and may have peripheral circuitry, such as, e.g., logic circuitry, formed therein. The periphery well  350  is doped differently from the retrograde well  320 . For example, the periphery well may be doped to a first dopant level from about 1×10 16  to about 2×10 18  atoms per cm 3  at the top of said retrograde well, preferably from about 5×10 16  to about 1×10 18 , most preferably from about 3×10 17  atoms per cm 3 . A representative doping concentration for the periphery well  350  is shown in FIG. 12. For simplicity, FIG. 12 does not show any V t  adjusting implants near the surface that could cause the dopant concentration immediately adjacent to the surface to elevate. As can be seen by comparing FIGS. 6 and 12, while the doping concentration of the retrograde well increases with depth to a certain point, the doping concentration of the periphery well decreases with depth. Moreover, as illustrated in FIG. 11, the retrograde well extends deeper into the substrate than does the periphery well. The retrograde well  320  and periphery well  350  are shown in FIG. 11 as being separated by field oxide regions  310 .  
         [0058]    The pixel cell  314  includes: a photogate  324 , a transfer transistor  328 , and a reset transistor  332 . In addition, the photosensitive element in the pixel cell  314  is shown to be a photogate  324 , but other photosensitive elements such as a photodiode or a photoconductor could be used. The source follower transistor and the row select transistor are not shown but are schematically arranged the same as transistors  36  and  38  shown in FIG. 5. The transfer transistor  328  and the reset transistor  332  include a gate oxide layer  327  and a conductive layer  329  of doped polysilicon, tungsten, or other suitable material over the gate oxide layer as described above with reference to FIG. 5. An insulating cap layer  331  of, for example, silicon dioxide, silicon nitride, or ONO (oxide-nitride-oxide), may be formed if desired; also a more conductive layer such as a silicide layer (not shown) may be used between the conductive layer and the cap of the transfer transistor  328  and reset transistor  332 , if desired. Insulating sidewalls  333  are also formed on the sides of the transistor gate stacks  328 ,  332 . These sidewalls may be formed of, for example, silicon dioxide or silicon nitride or ONO. The transfer transistor is not required but may advantageously be included. The photogate  324  is a semitransparent conductor and is shown as an overlapping gate.  
         [0059]    Underlying the photogate  324  is an oxide layer  335  and below that a doped region  326  which acts as the photosite, where photogenerated charges are stored. In between the reset transistor  332  and the transfer transistor  328  is a doped region  330  that is the source for the reset transistor  332 , and on the other side of the reset transistor gate  332  is a doped region  334  that acts as a drain for the reset transistor  332 . The doped regions  326 ,  330 ,  334  are doped to a second conductivity type, which for exemplary purposes is treated as n-type. The second doped region  330  is the floating diffusion region, sometimes also referred to as a floating diffusion node, and it serves as the source for the reset transistor  332 . The third doped region  334  is the drain of the reset transistor  332 , and is also connected to voltage source Vdd. The line  339  is a conductor which connects to a source follower and row select transistor in the manner illustrated in FIG. 5.  
         [0060]    The retrograde well  320  acts to reduce carrier loss to the substrate  316  by forming a concentration gradient that modifies the band diagram and serves to reflect electrons back towards the photosite  326 , thereby increasing quantum efficiency of the pixel  314 .  
         [0061]    The periphery well  350  may include periphery and logic circuitry. The periphery circuit is depicted as readout transistor circuit  360  in FIG. 11, however, it should be understood that readout circuit may include periphery and logic circuitry such as, for example, a signal sample and hold (S/H) circuit and a reset sample and hold circuit. The signal sample and hold circuit may include a S/H n-channel field effect transistor and a signal storage capacitor, and load transistor, as shown in FIG. 1 and described above. The reset sample and hold (S/H) circuit may include a S/H transistor, a signal storage capacitor, p-channel output transistor, p-channel column select transistor, load transistor or any other similar transistor, as shown in FIG. 1 and described above.  
         [0062]    The substrate including retrograde and periphery wells  320 ,  350  is manufactured through a process in a third process embodiment described as follows, and illustrated by FIGS. 13 and 14. Referring now to FIG. 13, a substrate  316 , which may be any of the types of substrates described above, is provided. Retrograde well  320  is then formed by suitable means such as blanket ion implantation of the entire wafer, with or without masking. FIG. 13 shows a masked ion implantation. The retrograde well  320  may be implanted at a later stage of the process such as after field oxide formation or after implantation of the periphery well.  
         [0063]    Ion implantation for well  320  is performed by placing the substrate  316  in an ion implanter, and implanting appropriate dopant ions into the substrate  316  at an energy of 100 keV to 5 MeV to form retrograde wells  320  having a dopant concentration that is lowest at or near the surface, and highest at the bottom of the well. The dopant concentration at the top of the retrograde well  320  is within the range of about 5×10 14  to about 1×10 17  atoms per cm 3 , and is preferably within the range of about 1×10 15  to about 5×10 16  atoms per cm 3 , and most preferably is about 5×10 15  atoms per cm 3 . At the bottom of the retrograde well  20 , the dopant concentration is within the range of about 1×10 16  to about 2×10 18  atoms per cm 3 , and is preferably within the range of about 5×10 16  to about 1×10 18  atoms per cm 3 , and most preferably is about 3×10 17  atoms per cm 3 . If the retrograde well is to be a p-type well, a p-type dopant, such as boron, is implanted, and if the well  320  is to be an n-type well, an n-type dopant, such as arsenic, antimony, or phosphorous is implanted.  
         [0064]    Reference is now made to FIG. 14. Periphery well  350  is then formed by suitable means such as masked blanket ion implantation of the entire wafer. The periphery well  350  may be implanted at a later stage of the process such as after field oxide formation or before the implantation of retrograde well  320 .  
         [0065]    Ion implantation is performed by placing the substrate  316  in an ion implanter, and implanting appropriate dopant ions into the substrate  316  at an energy of 100 keV to 5 MeV to form periphery well  350  having a dopant concentration that is highest at the surface, and decreases asymptotically to the bottom of the well. The dopant concentration at the top of the periphery well  350  is within the range of dopant concentration is within the range of about 1×10 16  to about 2×10 18  atoms per cm 3 , and is preferably within the range of about 5×10 16  to about 1×10 18  atoms per cm 3 , and most preferably is about 3×10 17  atoms per cm 3 . If the periphery well  350  is to be a p-type well, a p-type dopant, such as boron, is implanted, and if the periphery well  350  is to be an n-type well, an n-type dopant, such as arsenic, antimony, or phosphorous is implanted.  
         [0066]    The pixel sensor cell  314  is then subjected to conventional processing methods to form other elements, contacts, wiring to connect gate lines and the like to arrive at the structure generally shown in FIG. 1.  
         [0067]    A typical processor based system which includes a CMOS imager device according to the present invention is illustrated generally at  400  in FIG. 15. A processor based system is exemplary of a system having digital circuits which could include CMOS imager devices. Without being limiting, such a system could include a computer system, camera system, scanner, machine vision system, vehicle navigation system, video telephone, surveillance system, auto focus system, star tracker system, motion detection system, image stabilization system and data compression system for high-definition television, all of which can utilize the present invention.  
         [0068]    A processor system, such as a computer system, for example generally comprises a central processing unit (CPU)  444 , e.g., a microprocessor, that communicates with an input/output (I/O) device  446  over a bus  452 . The CMOS imager  442  also communicates with the system over bus  452 . The computer system  400  also includes random access memory (RAM)  448 , and, in the case of a computer system may include peripheral devices such as a floppy disk drive  454  and a compact disk (CD) ROM drive  456  which also communicate with CPU  444  over the bus  452 . CMOS imager  442  is preferably constructed as an integrated circuit which includes pixels containing a photosensor such as a photogate or photodiode formed in a retrograde well, as previously described with respect to FIGS. 5 through 14. The CMOS imager  442  may be combined with a processor, such as a CPU, digital signal processor or microprocessor, with or without memory storage in a single integrated circuit, or may be on a different chip than the processor.  
         [0069]    As can be seen by the embodiments described herein, the present invention encompasses a pixel sensor cell formed in a retrograde well. The pixel sensor cell has improved quantum efficiency and an improved signal-to-noise ratio due to the presence of a doping gradient induced electric field created in the bottom eof the retrograde well which reflects signal carriers back to the photosensitive node. By reflecting photogenerated carriers back to the storage node the retrograde p-well also reduces the number of carriers diffusing to adjacent pixels and so also reduces cross talk.  
         [0070]    It should again be noted that although the invention has been described with specific reference to CMOS imaging circuits having a photogate and a floating diffusion region, the invention has broader applicability and may be used in any CMOS imaging apparatus. Similarly, the process described above is but one method of many that could be used. The above description and drawings illustrate preferred embodiments which achieve the objects, features and advantages of the present invention. It is not intended that the present invention be limited to the illustrated embodiments. Any modification of the present invention which comes within the spirit and scope of the following claims should be considered part of the present invention.