Abstract:
A method for preventing snap-back in a circuit including at least one MOS transistor having a parasitic bipolar transistor associated with it includes coupling a circuit node including at least one source/drain node of the at least one MOS transistor to a bias-voltage circuit and enabling the bias-voltage circuit to supply a potential to the at least one source/drain node of the at least on MOS transistor, the potential having a magnitude selected to prevent the parasitic bipolar transistor from turning on.

Description:
BACKGROUND 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to integrated circuit technology. 
         [0003]    2. The Prior Art 
         [0004]    Snap back has been a problem in integrated circuits when voltage exceeding the junction breakdown of transistor devices is present in an integrated circuit. This problem is presently dealt with by providing guard ring structures as is known in the art. Guard ring structures only minimize but do not eliminate the snap back. 
         [0005]    In circuits such as non-volatile memory, high voltage P-channel and N-channel MOS transistor devices are used to form latch circuits to store write data. The high voltage N-channel device is leaky, resulting in standby current flowing during standby. This also causes the latch circuit to flip states during high voltage operation, resulting in data corruption. 
         [0006]    The flipping stage and data corruption in the high-voltage latch circuits are caused by snap back of the high-voltage N-channel or P-Channel device during high voltage operation. When the drain of the high-voltage N-channel device is at the breakdown voltage of the N-channel device, breakdown occurs causing a large current to flow into the substrate. The parasitic NPN bipolar device at the bottom of the high-voltage N-channel device can be triggered on by the large substrate current. As the parasitic NPN transistor turns on, a low-impedance path exists at the logic “1” node to ground, pulling down the voltage and causing the latch circuit to flip from a “1” state to a “0” state at the node. A similar situation can occur in PMOS structures, in which a parasitic PNP transistor can pull a low-voltage node to a high state. 
       BRIEF DESCRIPTION OF THE INVENTION 
       [0007]    Apparatus and methods for preventing snap back in integrated circuits are disclosed. The common source connections of high-voltage latches are connected to a source node that is placed at a potential such that snap-back of the transistors in the high-voltage latches is prevented. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWING FIGURES 
         [0008]      FIG. 1  is a schematic diagram of an exemplary apparatus for preventing snap back in integrated circuits in accordance with the present invention. 
           [0009]      FIG. 2  is a schematic diagram showing an illustrative bias control circuit suitable for use in the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0010]    Persons of ordinary skill in the art will realize that the following description of the present invention is illustrative only and not in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons. 
         [0011]    According to an illustrative example of an apparatus according to the present invention, as shown in  FIG. 1 , a first inverter  10  includes a P-channel MOS transistor  12  connected in series with an N-channel MOS transistor  14  between a high-voltage source V HV  (shown at reference numeral  16 ), for example 16V, and a source node  18 . The gates of transistors  12  and  14  are coupled together. A second inverter  20  includes a P-channel MOS transistor  22  connected in series with an N-channel MOS transistor  24  between the high-voltage source  16  and the source node  18 . The gates of transistors  22  and  24  are coupled together. Transistors  12 ,  14 ,  22 , and  24  are high-voltage transistors, that is, transistors designed to have breakdown voltages higher than the VDD voltage supplied to the integrated circuit. An illustrative example of such high voltage transistors are programming transistors in memory integrated circuits. The common drain node of transistors  12  and  14  is connected to the gates of transistors  22  and  24 , and the common drain node of transistors  22  and  24  is connected to the gates of transistors  12  and  14 . 
         [0012]    The gates of transistors  22  and  24  are connected to the drain of an N-channel reset transistor  26 . The source of N-channel reset transistor  26  is grounded and its gate is coupled to a Reset line  28 . The gates of transistors  22  and  24  are also connected to a Data In line  30  through an N-channel data-load transistor  32 . The gate of N-channel data-load transistor  32  is coupled to a Data Load line  34 . 
         [0013]    A high voltage N-channel latch-enable transistor  36  is connected between the common source connection of N-channel MOS transistors  14  and  22  of the write data latch circuits and ground. During standby, N-channel MOS latch-enable transistor  36  is turned off to eliminate the standby current. During write data loading, N-channel MOS latch-enable transistor  36  is turned on to enable latch operation. The gate of N-channel MOS latch-enable transistor  36  is coupled to a latch-enable line  38 . 
         [0014]    A bias circuit  40  generating a bias voltage V b  is also connected to the common source connection of N-channel MOS transistors  14  and  24  of the write data latch circuits. During standby and write data loading, the bias circuit will be turned off using the bias control line  42 . During high voltage operation, this bias circuit will be turned on, raising the ground node of the write data latch circuit to a bias voltage V b  such that the V DS  of the N-channel MOS transistors  14  and  24  is set to be below the snap-back voltage, and such that the V DS  of the P-channel MOS transistors  12  and  22  is set to be bellow the snap-back voltage. The bias voltage V b  must also be high enough so that V DS  of N-channel MOS transistors  14  and  24  will be at a value where the circuit will still operate. In one example, the bias voltage V b  is about 2V where V HV  is 16V, V DS  of N-channel MOS transistors  14  and  24  is 14V. Under these conditions there is no snap back because the snap back voltage would be 16V and the first and second inverters of  FIG. 1  are still operating. The turn-on timing for the bias circuit is also important in that turning it on too early may cause the inverters to malfunction and turning it on too late may allow snap-back to occur prior to it being turned on. 
         [0015]    Because the ground node (the common source connection of N-channel MOS transistors  14  and  22 ) of the write data latch circuit is at the voltage V b , it is difficult for the parasitic NPN bipolar devices associated with those transistors to turn on and snap back will not take place. No logic-state flipping will occur and thus no data corruption will occur. 
         [0016]    The high voltage generating circuit that generates V HV  is configured to output a high voltage (such as 16V) during high voltage operation, will output V DD  during write data loading, and will output ground during standby, thus eliminating current flow during standby. Persons of ordinary skill in the art will understand that configuring such a high-voltage circuit for a particular integrated circuit is a matter of routine circuit design. 
         [0017]    Referring now to  FIG. 2 , an exemplary bias circuit  40  is shown that may be employed to generate the bias voltage V b  to apply to the common source node  18  comprising the connection of N-channel MOS transistors  14  and  24  of the write data latch circuits. Bias circuit  40  employs four transistors, including P-channel MOS transistor  44 , P-channel MOS transistor  46 , N-channel MOS transistor  48 , and N-channel MOS transistor  50 , connected in series between low-voltage supply V CC  and ground. The gates of P-channel MOS transistor  46  and N-channel MOS transistor  48  are connected together to the common drain connections of P-channel MOS transistor  46  and N-channel MOS transistor  48 , and to the output at the common source node  18 . The gate of N-channel MOS transistor  50  is connected together to bias control signal line  42  and the gate of P-channel MOS transistor  44  is connected together to bias control signal line  42  through inverter  52 . 
         [0018]    When the voltage at bias control signal line  42  is low, N-channel MOS transistor  50  is turned off because its gate is at a low voltage. P-channel MOS transistor  44  is also turned off because its gate is at a high voltage through inverter  52 . Under these conditions, source node  18  is floating. When the voltage at bias control signal line  42  is high, N-channel MOS transistor  50  is turned on because its gate is at a high voltage. P-channel MOS transistor  44  is also turned on because its gate is at a low voltage through inverter  52 . Under these conditions, source node  18  is biased at a voltage such as about 2V through diode-connected transistors  46  and  48 . 
         [0019]    There are several advantages of the present invention over the use of guard rings. The present invention eliminates the snap back for both the P-channel and N-channel MOS transistors of the inverters while the use of guard rings only minimizes the snap back. 
         [0020]    While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims.