Abstract:
A diagnosis device including a storage unit configured to store first circuit configuration information, a circuit unit configured to configure a first plurality of circuits based on the first circuit configuration information and a second plurality of circuits based on second circuit configuration information, and a processor configured to update the first circuit configuration information to the second circuit configuration information and configured to diagnose all circuits newly added by the second circuit configuration information of the second plurality of circuits.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2013-246802, filed on Nov. 28, 2013, the entire contents of which are incorporated herein by reference. 
       FIELD 
       [0002]    The embodiments discussed herein are related to a diagnosis device, a control method of a diagnosis device, and a recording medium. 
       BACKGROUND 
       [0003]    A field programmable gate array (FPGA) is an integrated circuit in which the circuit configuration information can be changed by a user after it is manufactured and is now used in a variety of devices. 
         [0004]      FIG. 1  is a configuration diagram before an update of a conventional system. 
         [0005]    A system  101  includes a micro processing unit (MPU)  111 , a memory  121 , an MPU flash memory (FMEM)  131 , an FPGA FMEM  141 , an FPGA  151 , control devices  161 - i  (i=1 to m), and a communication unit  171 . 
         [0006]    The MPU FMEM  131  stores a firm package  132 . 
         [0007]    The firm package  132  includes MPU firmware  133  and FPGA data  135 . 
         [0008]    The MPU firmware  133  is a program that gives instructions to perform an updating of the firm package  132 , reconfiguration of the FPGA  151 , etc. 
         [0009]    The FPGA data  135  is information on circuits to be configured within the FPGA  151 . 
         [0010]    The FPGA FMEM  141  stores FPGA data  142 . 
         [0011]    The MPU  111  copies the FPGA data  135  within the MPU FMEM  131  to the FPGA FMEM  141 . The FPGA data copied to the FPGA FMEM  141  is represented as the FPGA data  142 . In other words, the contents of the FPGA data  135  and those of the FPGA data  142  are the same. 
         [0012]    When the MPU  111  gives instructions to perform reconfiguration to the FPGA  151 , the FPGA  151  reads the FPGA data  142  and configures circuits within the FPGA  151  based on the FPGA data  142 . 
         [0013]    When circuits are configured within the FPGA  151  based on the FPGA data  142  before an update, old circuits  181 - 1  to  181 - n  are configured. Hereinafter, the old circuits  181 - 1  to  181 - n  are represented as old circuits  1  to n, respectively. 
         [0014]    The old circuits  1  to n are circuits that operate by normal system operation, such as control of the control device  161 . 
         [0015]    Further, within the FPGA  151 , failures of elements (failed portions  1  and  2 ) exist in an area not used by the old circuits  1  to n. 
         [0016]    The failed portions  1  and  2  exist in the area not used by the old circuits  1  to n, and therefore, the old circuits  1  to n operate normally. 
         [0017]    In the case where the FPGA  151  is updated, the MPU  111  receives the new firm package  132  via the communication unit  171  and stores it in the MPU FMEM  131  and thus updates the firm package  132 . Then, the MPU  111  reads the FPGA data  135 , stores the FPGA data  142  in the FPGA FMEM  141 , and reconfigures the FPGA  151 . 
         [0018]      FIG. 2  is a diagram illustrating a configuration after an update of the conventional system, and a diagnosis range. 
         [0019]    When the FPGA  151  is reconfigured by using the FPGA data  142  after an update, within the FPGA  151 , the old circuits  1  to n and new circuits  191 - 1  and  191 - 2  are configured. Hereinafter, the new circuits  191 - 1  and  191 - 2  are represented as new circuits  1  and  2 , respectively. 
         [0020]    The old circuits  1  to n are the same as the old circuits  1  to n already configured before an update. However, before an update, the old circuit  1  and the old circuit  2  were connected, but after an update, the old circuit  1  and the old circuit  2  are not connected and the old circuits  1  and  2  connect with the new circuit  1 . 
         [0021]    In contrast to the FPGA  151  before an update, the new circuits  1  and  2  are added to the FPGA  151  after an update. 
         [0022]    The new circuit  1  connects with the old circuits  1  and  2  and the new circuit  2 . 
         [0023]    The new circuit  1  is a circuit that operates at the time of normal operation of the system  101 . 
         [0024]    The new circuit  2  operates only under specific conditions and does not operate at the time of normal operation of the system  101 . 
         [0025]    It is assumed that the new circuit  1  is configured in the area including the failed portion  1  and the new circuit  2  is configured in the area including the failed portion  2 . In this case, the new circuits  1  and  2  will malfunction. 
         [0026]    In the system  101  in which the above-described update is performed, the operation of the FPGA  151  is checked by checking the whole of the system  101  for the communication behavior during normal operation. 
         [0027]    In this case, the range of the communication behavior check includes the old circuits  1  to n and the new circuit  1  that operate by normal operation. 
         [0028]    In other words, whether there is an error is checked by causing the old circuits  1  to n and the new circuit  1  to perform normal operation. 
         [0029]    The new circuit  1  is a circuit that operates by normal operation of the system  101 , and therefore, if there is a failed portion in the area where the new circuit  1  is configured, it is possible to detect a failure from an error in the new circuit  1 . In this case, it is preferable to replace the FPGA  151  with another during the maintenance work in which the above-mentioned update etc. is performed. 
         [0030]    On the other hand, in the operation check during normal operation, the new circuit  2  that operates only under specific conditions is not included in the range of the operation check. 
         [0031]    Consequently, even if a failed portion is included in the new circuit  2 , it is not possible to detect a failure in the new circuit  2  by the conventional operation check. 
         [0032]    The failure in the new circuit  2  is detected in the case where the new circuit  2  operates while the system is in operation after the maintenance work has been completed. Because of this, in the case where a failed portion is included in the new circuit  2 , it is needed to stop the system  101  again and to replace the FPGA  151  with another. 
         [0033]    As above, in the operation check at the time of the conventional update, not all the circuits within the FPGA are checked and a failure in the FPGA is detected while the system is in operation after the maintenance work has been completed, and therefore, there is a problem such that reliability of the system is degraded. 
         [0034]    If all the elements within the FPGA are diagnosed before shipment of the system, normal operation is guaranteed for any circuit configuration. However, creating such a test program will generate an enormous number of development processes and cost. Furthermore, the documents such as Japanese Laid-open Patent Publication No. 2008-52389, Japanese Laid-open Patent Publication No. 2009-44473, etc. are well known. 
       SUMMARY 
       [0035]    According to an aspect of the embodiments, a diagnosis device includes a storage unit, a circuit unit, and a processor. 
         [0036]    The storage unit stores first circuit configuration information. 
         [0037]    The circuit unit configures a first plurality of circuits based on the first circuit configuration information and a second plurality of circuits based on second circuit configuration information. 
         [0038]    The processor updates the first circuit configuration information to the second circuit configuration information and diagnoses all the circuits newly added by the second circuit configuration information of the second plurality of circuits. 
         [0039]    The object and advantages of the embodiments will be realized and attained by means of the elements and combinations particularly pointed out in the claims. 
         [0040]    It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the embodiments, as claimed. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0041]      FIG. 1  is a configuration diagram before an update of a conventional system; 
           [0042]      FIG. 2  is a diagram illustrating a configuration after an update of the conventional system and a diagnosis range; 
           [0043]      FIG. 3  is a configuration diagram before an update of a system according to a first embodiment; 
           [0044]      FIG. 4  is a configuration diagram after an update of the system according to the first embodiment; 
           [0045]      FIG. 5  is a diagram illustrating a diagnosis range in a diagnosis method according to the first embodiment; 
           [0046]      FIG. 6  is a flowchart of the diagnosis method according to the first embodiment; 
           [0047]      FIG. 7  is a configuration diagram before an update of a system according to a second embodiment; 
           [0048]      FIG. 8  is a configuration diagram at the time of diagnosis after an update of the system according to the second embodiment; 
           [0049]      FIG. 9  is a diagram illustrating a diagnosis range in a diagnosis method according to the second embodiment; 
           [0050]      FIG. 10  is a flowchart of the diagnosis method according to the second embodiment; 
           [0051]      FIG. 11  is a configuration diagram after diagnosis after an update of the system according to the second embodiment; 
           [0052]      FIG. 12  is a configuration diagram before an update of a system according to a third embodiment; 
           [0053]      FIG. 13  is a configuration diagram at the time of the first diagnosis after an update of the system according to the third embodiment; 
           [0054]      FIG. 14  is a configuration diagram at the time of the second diagnosis after an update of the system according to the third embodiment; 
           [0055]      FIG. 15  is a flowchart of a diagnosis method according to the third embodiment; and 
           [0056]      FIG. 16  is a configuration diagram of an information processing apparatus (computer). 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0057]    Hereinafter, embodiments are explained with reference to drawings. 
       First Embodiment 
       [0058]      FIG. 3  is a configuration diagram before an update of a system according to a first embodiment. 
         [0059]    A system  1101  includes an MPU  1111 , a memory  1121 , an MPU flash memory (FMEM)  1131 , an FPGA FMEM  1141 , an FPGA  1151 , control devices  1161 - i  (i=1 to m), and a communication unit  1171 . 
         [0060]    The system  1101  is, for example, a computer, such as a system board and a server. 
         [0061]    The MPU  1111  is a processing device that performs an updating of a firm package and diagnosis of the FPGA. The MPU  1111  performs an updating of a firm package  1132  and diagnosis of the FPGA  1151  by executing MPU firmware and FPGA diagnosis programs read onto the memory  1121 . 
         [0062]    The memory  1121  is a storage device that temporarily stores data and programs used in the system  1101 . The memory  1121  is, for example, a random access memory (RAM). 
         [0063]    The MPU FMEM  1131  stores the firm package  1132 . The MPU FMEM  1131  is, for example, a nonvolatile memory. 
         [0064]    The firm package  1132  includes MPU firmware  1133  and FPGA data  1135 . 
         [0065]    The MPU firmware  1133  is a program that gives instructions to perform an updating of the firm package  1132 , reconfiguration of the FPGA  1151 , etc. 
         [0066]    The FPGA data  1135  is information on circuits to be configured within the FPGA  1151 . The FPGA data  1135  includes information on the structures of the circuits to be configured within the FPGA  1151 , the positions of the circuits, the connection relationship between the circuits, etc. 
         [0067]    The FPGA FMEM  1141  stores FPGA data  1142 . The FPGA FMEM  1141  is, for example, a nonvolatile memory. 
         [0068]    The FPGA data  1142  is information on circuits to be configured within the FPGA  1151 . The FPGA data  1142  is generated by the MPU  1111  copying the FPGA data  1135 . Consequently, the contents of the FPGA data  1142  and those of the FPGA data  1135  are the same. 
         [0069]    The FPGA  1151  configures circuits inside the FPGA  1151  based on the FPGA data  1142 . The FPGA  1151  has a bridge function to establish communication between the MPU  1111  and the control device  1161 . The FPGA  1151  is an example of the circuit unit. 
         [0070]    In the first embodiment, old circuits  1181 - 1  to  1181 - n  are configured based on the FPGA data  1142  before an update. Hereinafter, the old circuits  1181 - 1  to  1181 - n  are represented as the old circuits  1  to n, respectively. 
         [0071]    The old circuit  1  connects with the old circuit  2  and the MPU  1111 . 
         [0072]    The old circuit  2  connects with the old circuit  1  and the old circuit  3 . 
         [0073]    The old circuit  3  connects with the old circuit  2  and the control devices  1161 - 1  to  1161 - m.    
         [0074]    The control device  1161  is a device controlled by the MPU  1111  via the FPGA  1151 . 
         [0075]    The communication unit  1171  connects with a network, such as a local area network (LAN), and performs transmission and reception of data with an external device connected via the network. 
         [0076]      FIG. 4  is a configuration diagram after an update of the system according to the first embodiment. 
         [0077]    In the case where the FPGA  1151  is updated, the MPU  1111  receives the new firm package  1132  via the communication unit  1171  and stores it in the MPU FMEM  1131  and thus updates the firm package  1132 . Then, the MPU  1111  reads the FPGA data  1135 , stores the FPGA data  1142  in the FPGA FMEM  1141 , and reconfigures the FPGA  1151 . 
         [0078]      FIG. 4  is a configuration diagram when the FPGA  1151  is reconfigured with the updated FPGA data  1135  after an update of the FPGA data  1135 . 
         [0079]    The firm package  1132  after an update includes the MPU firmware  1133 , the FPGA data  1135 , and an FPGA diagnosis program  1137 . 
         [0080]    The FPGA diagnosis program  1137  is a program that performs diagnosis of the FPGA  1151 . 
         [0081]    The FPGA diagnosis program  1137  only performs diagnosis of all the circuits (new circuits) added by an update and the circuits needed for the operation of the new circuits. 
         [0082]    In the FPGA diagnosis program  1137 , circuits to be diagnosed, diagnosis processing, etc., are set in advance. 
         [0083]    In the FPGA  1151 , the old circuits  1181 - 1  to  1181 - n  and new circuits  1191 - 1  and  1191 - 2  are configured based on the FPGA data  1142  after an update. Hereinafter, the old circuits  1181 - 1  to  1181 - n  are represented as the old circuits  1  to n, respectively, and the new circuits  1191 - 1  and  1191 - 2  as new circuits  1  and  2 , respectively. 
         [0084]    The old circuits  1  to n are the circuits already configured within the FPGA  1151 , also in the FPGA  1151  before an update. 
         [0085]    The new circuits  1  and  2  are circuits newly added in the FPGA  1151  after an update, in contrast to the FPGA  1151  before an update. 
         [0086]    The old circuit  1  connects with the new circuit  1  and the MPU  1111 . 
         [0087]    The old circuit  2  connects with the new circuit  1  and the old circuit  3 . 
         [0088]    The old circuit  3  connects with the old circuit  2  and the control devices  1161 - 1  to  1161 - m.    
         [0089]    The new circuit  1  connects with the old circuits  1  and  2  and the new circuit  2 . The new circuit  1  is a circuit that operates at the time of normal operation of the system  1101 . 
         [0090]    The new circuit  2  connects with the new circuit  1 . The new circuit  2  operates only under specific conditions and does not operate at the time of normal operation of the system  1101 . 
         [0091]    The old circuits  1  to  3  are circuits needed for the operation of the new circuits  1  and  2 . The circuit needed for the operation of the new circuit is a circuit that operates (is used) at the time of the operation of the new circuit. The circuit needed for the operation of the new circuit is, for example, a circuit that generates data used by the new circuit at the time of the operation and outputs the data to the new circuit, relays data input from another circuit to the new circuit, etc. 
         [0092]    The old circuits  4  to n are circuits not needed for the operation of the new circuits  1  and  2 . In other words, it is possible for the new circuits  1  and  2  to operate normally even if the circuits  4  to n are not in operation. 
         [0093]      FIG. 5  is a diagram illustrating a diagnosis range in a diagnosis method according to the first embodiment. 
         [0094]    In the first embodiment, the FPGA diagnosis program  1137  only performs diagnosis of all the circuits (new circuits) added by an update and the circuits needed for the operation of the new circuits. The circuit needed for the operation of the new circuit is a circuit that operates (is used) at the time of the operation of the new circuit. 
         [0095]    The FPGA diagnosis program  1137  does not perform diagnosis of the circuits not needed for the operation of the added circuits. 
         [0096]    In other words, in the system  1101  in  FIG. 4 , the FPGA diagnosis program  1137  only performs diagnosis of the new circuits  1  and  2  and the old circuits  1  to  3 . The FPGA diagnosis program  1137  does not perform diagnosis of the old circuits  4  to n. Because of this, it is possible to reduce the diagnosis time and to reduce the time during which the system  1101  is not in operation. 
         [0097]      FIG. 6  is a flowchart of diagnosis processing according to the first embodiment. 
         [0098]    The FPGA  1151  has already been reconfigured based on the FPGA data  1142  and the configuration is that before the update illustrated in  FIG. 3 . 
         [0099]    Further, it is assumed that the MPU  1111  has executed the MPU firmware  1133 . 
         [0100]    At step S 1501 , the MPU  1111  receives the firm package  1132  via the communication unit  1171  from an external device connected with the system  1101  via the network and writes the firm package  1132  to the MPU FMEM  1131 . 
         [0101]    At step S 1502 , the MPU  1111  reads the FPGA data  1135 , serves as a bus master via a serial bus  1201 , and writes it to the FPGA FMEM  1141 . The FPGA data written to the FPGA FMEM  1141  as described above is represented as the FPGA data  1142 . 
         [0102]    At step S 1503 , the MPU  1111  gives instructions to perform reconfiguration to the FPGA  1151 . Upon receipt of the instructions, the FPGA  1151  performs reconfiguration. In detail, the FPGA  1151  reads the FPGA data  1142  and configures the old circuits  1  to n and the new circuits  1  and  2  based on the FPGA data  1142 . It may also be possible for the FPGA  1151  to receive the FPGA data  1135  from the MPU FMEM  1131  via the MPU  1111  and to configure the old circuits  1  to n and the new circuits  1  and  2  based on the FPGA data  1135 . In such a case, the processing to write the FPGA data  1135  to the FPGA FMEM  1141  at step S 1502  may be omitted. 
         [0103]    At step S 1504 , the MPU  1111  executes the FPGA diagnosis program  1137 . By means of the FPGA diagnosis program  1137 , the MPU  1111  diagnoses the new circuits  1  and  2  and the old circuits  1  to  3 . In the diagnosis processing, for example, predetermined commands and data are input to a circuit to be diagnosed and whether or not the circuit operates normally is checked. In the case where the circuit to be diagnosed operates anomalously when the predetermined commands and data are input to the circuit to be diagnosed, an error is detected. 
         [0104]    At step S 1505 , in the case where the diagnosis is completed normally (i.e., when no error is detected in the new circuits  1  and  2  and the old circuits  1  to  3 ), the processing is exited, and in the case where the diagnosis is not completed normally (i.e., when an error is detected in any of the new circuits  1  and  2  and the old circuits  1  to  3 ), the control proceeds to step S 1506 . 
         [0105]    At step S 1506 , the MPU  1111  makes a notification of a failure. For example, the MPU  1111  produces a display to the effect that an error is detected on a display unit (not illustrated) of the system  1101  or notifies an external device connected with the system  1101  via the network of the error. 
         [0106]    According to the system of the first embodiment, by diagnosing all the circuits newly added by an update, an error due to a potential failure is no longer detected while the system is in operation and reliability of the system is improved. 
         [0107]    Further, according to the system of the first embodiment, by reducing the diagnosis time by limiting the diagnosis range, it is possible to reduce the time during which the system is not in operation. 
       Second Embodiment 
       [0108]      FIG. 7  is a configuration diagram before an update of a system according to a second embodiment. 
         [0109]    A system  2101  includes an MPU  2111 , a memory  2121 , and MPU flash memory (FMEM)  2131 , an FPGA FMEM  2141 , an FPGA  2151 , control devices  2161 - i  (i=1 to and a communication unit  2171 . 
         [0110]    The system  2101  is, for example, a computer, such as a system board or a server. 
         [0111]    The MPU FMEM  2131  stores a firm package  2132 . The MPU FMEM  2131  is, for example, a nonvolatile memory. 
         [0112]    The firm package  2132  includes MPU firmware  2133  and FPGA data (normal version)  2135 . 
         [0113]    The MPU firmware  2133  is a program that gives instructions to perform an updating of the firm package  2132 , reconfiguration of the FPGA  2151 , etc. 
         [0114]    The FPGA data  2135  is information on circuits to be configured within the FPGA  2151 . The FPGA data  2135  includes information on the structures of the circuits to be configured within the FPGA  2151 , the positions of the circuits, the connection relationship between the circuits, etc. 
         [0115]    The MPU  2111 , the memory  2121 , the control devices  2161 - i , and the communication unit  2171  have the same functions as those of the MPU  1111 , the memory  1121 , the control devices  1161 - i , and the communication unit  1171  of the first embodiment, respectively, and therefore, explanation is omitted. 
         [0116]    The FPGA FMEM  2141  stores FPGA data (normal version)  2143 . The FPGA FMEM  2141  is, for example, a nonvolatile memory. 
         [0117]    The FPGA data  2143  (normal version) is information on circuits to be configured within the FPGA  2151 . The FPGA data  2143  (normal version) is generated by the MPU  2111  copying the FPGA data (normal version)  2135 . Consequently, the contents of the FPGA data (normal version)  2143  and those of the FPGA data (normal version)  2135  are the same. 
         [0118]    The FPGA  2151  configures circuits inside the FPGA  2151  based on the FPGA data (normal version)  2143 . The FPGA  2151  has abridge function to establish communication between the MPU  2111  and the control device  2161 . The FPGA  2151  is an example of the circuit unit. 
         [0119]    In the second embodiment, based on the FPGA data (normal version)  2143  before an update, old circuits  2181 - 1  to  2181 - n  are configured. Hereinafter, the old circuits  2181 - 1  to  2181 - n  are represented as the old circuits  1  to n, respectively. 
         [0120]    The old circuits  2181 - 1  to  2181 - n  have the same functions and configurations as those of the old circuits  1181 - 1  to  1181 - n  before an update of the first embodiment, respectively, and therefore, explanation is omitted. 
         [0121]      FIG. 8  is a configuration diagram at the time of diagnosis after an update of the system according to the second embodiment. 
         [0122]    In the case where the FPGA  2151  is updated, the MPU  2111  receives the new firm package  2132  via the communication unit  2171  and stores it in the MPU FMEM  2131  and thus updates the firm package  2132 . Then, the MPU  2111  reads FPGA data (diagnosis version)  2136 , stores FPGA data (diagnosis version)  2142  in the FPGA FMEM  2141 , and reconfigures the FPGA  2151 . 
         [0123]      FIG. 8  is a configuration diagram in which the FPGA  2151  is reconfigured with the updated FPGA data (diagnosis version)  2136  after an update of the firm package  2132 . 
         [0124]    The firm package  2132  after an update includes the MPU firmware  2133 , the FPGA data (normal version)  2135 , the FPGA data (diagnosis version)  2136 , and an FPGA diagnosis program  2137 . 
         [0125]    The MPU firmware  2133  is a program that gives instructions to perform an updating of the firm package  2132 , reconfiguration of the FPGA  2151 , etc. 
         [0126]    The FPGA data (normal version)  2135  is information on circuits to be configured within the FPGA  2151 . The FPGA data  2135  (normal version) includes information on the structures of the circuits to be configured within the FPGA  2151 , the positions of the circuits, the connection relationship between the circuits, etc. 
         [0127]    The FPGA data (diagnosis version)  2136  is information on circuits to be configured within the FPGA  2151 . The FPGA data  2136  (diagnosis version) includes information on the structures of the circuits to be configured within the FPGA  2151 , the positions of the circuits, the connection relationship between the circuits, etc. 
         [0128]    The FPGA diagnosis program  2137  is a program that gives instructions to start diagnosis to a dedicated built-in self test (BIST) circuit  2193  configured to perform diagnosis of the FPGA  2151 , receives notification to the effect that the diagnosis has been completed, receives notification to the effect that an error has been detected, etc. 
         [0129]    The FPGA FMEM  2141  stores the FPGA data (diagnosis version)  2142 . The FPGA FMEM  2141  is, for example, a nonvolatile memory. 
         [0130]    The FPGA data  2142  (diagnosis version) is information on circuits to be configured within the FPGA  2151 . The FPGA data  2142  (diagnosis version) is generated by the MPU  2111  copying the FPGA data (diagnosis version)  2136 . Consequently, the contents of the FPGA data (diagnosis version)  2142  and those of the FPGA data (diagnosis version)  2136  are the same. 
         [0131]    The FPGA  2151  configures circuits inside the FPGA  2151  based on the FPGA data (diagnosis version)  2142 . 
         [0132]    In the second embodiment, based on the FPGA data (diagnosis version)  2142  after an update, the old circuits  2181 - 1 ,  2181 - 2 , and  2181 - 5  to  2181 - n , a new circuit  2191 - 1 , a dedicated pseudo circuit  2192 , and the dedicated BIST circuit  2193  are configured. Hereinafter, the old circuits  2181 - 1 ,  2181 - 2 , and  2181 - 5  to  2181 - n  are represented as the old circuits  1 ,  2 , and  5  to n, respectively, and the new circuit  2191 - 1  as the new circuit  1 . 
         [0133]    The old circuit  1  connects with the new circuit  1  and the MPU  2111 . 
         [0134]    The old circuit  2  connects with the new circuit  1  and the dedicated pseudo circuit  2192 . 
         [0135]    The old circuits  1 ,  2 , and  5  to n are the circuits already configured within the FPGA  2151 , also in the FPGA  2151  before an update. 
         [0136]    The new circuit  1  is a circuit newly added in the FPGA  2151  after an update, in contrast to the FPGA  2151  before an update in  FIG. 7 . 
         [0137]    The dedicated pseudo circuit  2192  connects with the old circuit  2 . 
         [0138]    The dedicated pseudo circuit  2192  is configured in the area where the old circuit  3  having the interface with the control devices  2161 - 1  to  2161 - m  was configured in the FPGA  2151  before an update. 
         [0139]    The dedicated pseudo circuit  2192  has the functions of the old circuit  3  and the interface function equivalent to that of the control devices  2161 - 1  to  2161 - m.    
         [0140]    The dedicated pseudo circuit  2192  includes pseudo circuits  2194 - 1  to  2194 - m . Hereinafter, the pseudo circuits  2194 - 1  to  2194 - m  are represented as pseudo circuits  1  to m, respectively. 
         [0141]    The pseudo circuits  1  to m perform an interface operation equivalent to that of the control devices  2161 - 1  to  2161 - m . In other words, the pseudo circuits  1  to m perform an operation equivalent to the response of the control devices  2161 - 1  to  2161 -m in the case where the control devices  2161 - 1  to  2161 - m  are accessed. 
         [0142]    For example, when making an attempt to access the control devices  2161 - 1  to  2161 - m  at the time of diagnosis of the new circuit  1 , the dedicated pseudo circuit  2192  performs a response equivalent to that in the case where the pseudo circuits  1  to m access the control devices  2161 - 1  to  2161 - m  without accessing the control devices  2161 - 1  to  2161 - m.    
         [0143]    In other words, the pseudo circuits  1  to m perform an operation equivalent to the response of the control devices  2161 - 1  to  2161 - m  when accessing the control devices  2161 - 1  to  2161 - m  via the old circuit  3 . 
         [0144]    Consequently, from the MPU  2111 , the old circuits  1  and  2 , the new circuit  1 , and the dedicated BIST circuit  2193 , it seems as if the old circuit  3  is configured in place of the dedicated pseudo circuit  2192  within the FPGA  2151  and the old circuit  3  is connected with the control devices  2161 - 1  to  2161 - m . Consequently, it is possible to perform diagnosis equivalent to that in the case where the old circuit  3  is connected with the control devices  2161 - 1  to  2161 - m  in the FPGA  2151  in  FIG. 8 . 
         [0145]    The dedicated BIST circuit  2193  is a circuit configured to perform diagnosis of the FPGA  2151 . It is possible for the dedicated BIST circuit  2193  configured by hardware to perform diagnosis at a speed higher than that at which the MPU  1111  in the first embodiment performs diagnosis of the FPGA  1151  by executing the diagnosis program  1137 . 
         [0146]    The dedicated BIST circuit  2193  is configured in the area where the old circuit  4  existed in the FPGA  2151  before an update. 
         [0147]    The area where the dedicated BIST circuit  2193  is configured is not limited to the area where the old circuit  4  existed before an update, and may be any area as long as the new circuit  1  and the circuits that operate (are used) at the time of the operation of the new circuit are not affected. 
         [0148]    The new circuit  1  connects with the old circuit  1  and the old circuit  2 . The new circuit  1  is a circuit that operates at the time of normal operation of the system  2101 . 
         [0149]    Further, the old circuits  1  to  3  are the circuits needed for the operation of the new circuit  1 . The circuit needed for the operation of the new circuit is a circuit that operates (is used) at the time of the operation of the new circuit. The circuit needed for the operation of the new circuit is a circuit that generates data used by the new circuit at the time of the operation and outputs the data to the new circuit, relays data input from another circuit to the new circuit, etc. 
         [0150]    The old circuits  5  to n are the circuits not needed for the operation of the new circuit  1 . In other words, it is possible for the new circuit  1  to perform normal operation even if the circuits  5  to n are not in operation. 
         [0151]      FIG. 9  is a diagram illustrating a diagnosis range in a diagnosis method according to the second embodiment. 
         [0152]    In the second embodiment, the dedicated BIST circuit  2193  only performs diagnosis of all the circuits (new circuits) added by an update except for itself and the circuits needed for the operation of the new circuits. The circuit needed for the operation of the new circuit is a circuit that operates (is used) at the time of the operation of the new circuit. 
         [0153]    Further, the dedicated BIST circuit  2193  does not perform diagnosis of the circuits not needed for the operation of the added circuits. 
         [0154]    In other words, in the system  2101  in  FIG. 8 , the dedicated BIST circuit  2193  only performs diagnosis of the new circuit  1 , the old circuits  1  and  2 , and the dedicated pseudo circuit  2192 . The dedicated BIST circuit  2193  does not perform diagnosis of the old circuits  5  to n. Because of this, it is possible to reduce the diagnosis time and to reduce the time during which the system  2101  is not in operation. 
         [0155]    Further, by using the dedicated pseudo circuit  2192 , the control device  2161  is not caused to operate, and therefore, it is possible to reduce the diagnosis time. 
         [0156]      FIG. 10  is a flowchart of the diagnosis method according to the second embodiment. 
         [0157]    The FPGA  2151  has already been reconfigured based on the FPGA data (normal version)  2143  and the configuration is that before an update illustrated in  FIG. 7 . 
         [0158]    Further, it is assumed that the MPU  2111  has executed the MPU firmware  2133 . 
         [0159]    At step S 2501 , the MPU  2111  receives the firm package  2132  via the communication unit  2171  from an external device connected with the system  2101  via the network and writes the firm package  2132  to the MPU FMEM  2131 . 
         [0160]    At step S 2502 , the MPU  2111  reads the FPGA data (diagnosis version)  2136 , serves as a bus master via a serial bus  2201 , and writes this to the FPGA FMEM  2141 . The FPGA data (diagnosis version) written to the FPGA FMEM  2141  as described above is represented as the FPGA data  2142 . 
         [0161]    At step S 2503 , the MPU  2111  gives instructions to perform reconfiguration to the FPGA  2151 . Upon receipt of the instructions, the FPGA  2151  performs reconfiguration. In detail, the FPGA  2151  reads the FPGA data (diagnosis version)  2142  and configures the old circuits  1  and  2 , the new circuit  1 , the dedicated pseudo circuit  2192 , and the dedicated BIST circuit  2193  based on the FPGA data (diagnosis version)  2142 . Further, it may also be possible for the FPGA  2151  to receive the FPGA data (diagnosis version)  2136  from the MPU FMEM  2131  via the MPU  2111  and to configure the old circuits  1  and  2 , the new circuit  1 , the dedicated pseudo circuit  2192 , and the dedicated BIST circuit  2193  based on the FPGA data (diagnosis version)  2136 . In such a case, the processing to write the FPGA data (diagnosis version)  2136  to the FPGA FMEM  2141  at step S 2502  may be omitted. 
         [0162]    At step S 2504 , the MPU  2111  executes the FPGA diagnosis program  2137 . When executing the FPGA diagnosis program  2137 , the MPU  2111  gives instructions to start diagnosis to the dedicated BIST circuit  2193 . 
         [0163]    The dedicated BIST circuit  2193  having received the instructions diagnoses the new circuit  1 , the old circuits  1  and  2 , and the dedicated pseudo circuit  2192 . In the diagnosis processing, predetermined commands and data are input to a circuit to be diagnosed and whether or not the circuit operates normally is checked. 
         [0164]    At step S 2505 , in the case where the diagnosis is completed normally, the dedicated BIST circuit  2193  notifies the MPU  2111  that the diagnosis has been completed, and the control proceeds to step S 2506 . In the case where the diagnosis is not completed normally (i.e., when an error is detected in any of the new circuit  1 , the old circuits  1  and  2 , and the dedicated pseudo circuit  2192 ), the dedicated BIST circuit  2193  notifies the MPU  2111  that an error has been detected, and the control proceeds to step S 2508 . 
         [0165]    At step S 2506 , the MPU  2111  reads the FPGA data (normal version)  2135 , serves as a bus master via the serial bus  2201 , and writes it to the FPGA FMEM  2141 . The FPGA data (normal version) written to the FPGA FMEM  2141  is represented as the FPGA data (normal version)  2143 . 
         [0166]    At step S 2507 , the MPU  2111  gives instructions to perform reconfiguration to the FPGA  2151 . Upon receipt of the instructions, the FPGA  2151  performs reconfiguration. In detail, the FPGA  2151  reads the FPGA data (normal version)  2143  and configures circuits based on the FPGA data (normal version)  2143 . Due to this, the FPGA  2151  as illustrated in  FIG. 11  is configured. Further, it may also be possible for the FPGA  2151  to receive the FPGA data (normal version)  2135  from the MPU FMEM  2131  via the MPU  2111  and to configure circuits based on the FPGA data (normal version)  2135 . In such a case, the processing to write the FPGA data (normal version)  2136  to the FPGA FMEM  2141  at step S 2506  may be omitted. 
         [0167]      FIG. 11  is a configuration diagram after the diagnosis after an update of the system according to the second embodiment. 
         [0168]    In the FPGA  2151  in  FIG. 11 , based on the FPGA data (normal version)  2143 , the old circuits  2181 - 1  to  2181 - n  and the new circuit  2191 - 1  are configured. Hereinafter, the old circuits  2181 - 1  to  2181 - n  are represented as the old circuits  1  to n, respectively, and the new circuit  2191 - 1  as the new circuit  1 . 
         [0169]    The old circuits  1  to n are the circuits that are already configured within the FPGA  2151 , also in the FPGA  2151  before an update. 
         [0170]    The new circuit  1  is a circuit newly added in the FPGA  2151  after an update, in contrast to the FPGA  2151  before an update in  FIG. 7 . Further, the new circuit  1  is the same circuit as the new circuit  1  at the time of the diagnosis in  FIG. 8 . 
         [0171]    Returning to  FIG. 10 , at step S 2508 , the MPU  2111  makes a notification of a failure. For example, the MPU  2111  produces a display to the effect that an error is detected on the display unit (not illustrated) of the system  2101  or notifies an external device connected with the system  2101  via the network of the error. 
         [0172]    According to the system of the second embodiment, by diagnosing all the circuits that are newly added by an update, an error due to the potential failure is no longer detected while the system is in operation, and therefore, reliability of the system is improved. 
         [0173]    According to the system of the second embodiment, by configuring the BIST circuit that performs diagnosis within the FPGA and by the BIST circuit performing diagnosis, it is possible to reduce the diagnosis time. 
         [0174]    In the case where it takes a very long time to operate the control device, the time taken by the diagnosis of the FPGA also increases, and therefore, there is a problem such that the time during which the maintenance of the system is not performed increases considerably. 
         [0175]    According to the system of the second embodiment, it is possible to reduce the diagnosis time by not allowing the control device to operate during the time of diagnosis and by using a dedicated pseudo circuit that performs an operation equivalent to the interface operation of the control device. 
       Third Embodiment 
       [0176]      FIG. 12  is a configuration diagram before an update of a system according to a third embodiment. 
         [0177]    A system  3101  includes an MPU  3111 , a memory  3121 , an MPU flash memory (FMEM)  3131 , an FPGA FMEM  3141 , an FPGA  3151 , control devices  3161 - i  (i=1 to m), and a communication unit  3171 . 
         [0178]    The MPU  3111 , the memory  3121 , the control devices  3161 - i , and the communication unit  3171  have the same functions and configurations as those of the MPU  1111 , the memory  1121 , the control devices  1161 - i , and the communication unit  1171  of the first embodiment, respectively, and therefore, explanation is omitted. 
         [0179]    The MPU FMEM  3131  stores a firm package  3132 . The firm package  3132  includes MPU firmware  3133  and FPGA data  3134 . 
         [0180]    The MPU FMEM  3131 , the MPU firmware  3133 , and the FPGA data  3134  have the same functions and configurations as those of the MPU FMEM  1131 , the MPU firmware  1133 , and the FPGA data  1134  of the first embodiment, respectively, and therefore, explanation is omitted. 
         [0181]    The FPGA FMEM  3141  stores FPGA data  3144 . The FPGA FMEM  3141  is, for example, a nonvolatile memory. 
         [0182]    The FPGA data  3144  is information on circuits to be configured within the FPGA  3151 . The FPGA data  3144  is generated by the MPU  3111  copying the FPGA data  3141 . Consequently, the contents of the FPGA data  3144  and those of the FPGA data  3134  are the same. 
         [0183]    The FPGA  3151  configures circuits inside the FPGA  3151  based on the FPGA data  3144 . The FPGA  3151  has a bridge function to establish communication between the MPU  3111  and the control device  3161 . The FPGA  3151  is an example of the circuit unit. 
         [0184]    In the third embodiment, based on the FPGA data  3144  before an update, old circuits  3181 - 1  to  3181 - n  are configured. Hereinafter, the old circuits  3181 - 1  to  3181 - n  are represented as the old circuits  1  to n, respectively. 
         [0185]    The old circuits  3181 - 1  to  3181 - n  have the same functions and configurations as those of the old circuits  1181 - 1  to  1181 - n  before an update of the first embodiment, respectively, and therefore, explanation is omitted. 
         [0186]      FIG. 13  is a configuration diagram at the time of the first diagnosis after an update of the system according to the third embodiment. 
         [0187]    In the case where the FPGA  3151  is updated, the MPU  3111  receives the new firm package  3132  via the communication unit  3171  and stores it in the MPU FMEM  3131  and thus updates the firm package  3132 . Then, the MPU  3111  reads FPGA data (area 0  version)  3135 , stores FPGA data (area 0  version)  3142  in the FPGA FMEM  3141 , and reconfigures the FPGA  3151 . 
         [0188]    The firm package  3132  after an update includes the MPU firmware  3133 , the FPGA data (area 0  version)  3135 , FPGA data (area 1  version)  3136 , and an FPGA diagnosis program  3137 . 
         [0189]    The MPU firmware  3133  is a program that gives instructions to perform an updating of the firm package  3132 , reconfiguration of the FPGA  3151 , etc. 
         [0190]    The FPGA data (area 0  version)  3135  is information on circuits to be configured within the FPGA  3151 . The FPGA data (area 0  version)  3135  includes information on the structures of the circuits to be configured within the FPGA  3151 , the positions of the circuits, the relationship between the circuits, etc. 
         [0191]    The FPGA data (area 1  version)  3136  is information on circuits to be configured within the FPGA  3151 . The FPGA data (area 1  version)  3136  includes information on the structures of the circuits to be configured within the FPGA  3151 , the positions of the circuits, the relationship between the circuits, etc. 
         [0192]    The FPGA diagnosis program  3137  is a program that performs diagnosis of the FPGA  3151 . 
         [0193]    The FPGA diagnosis program  3137  only performs diagnosis of all the circuits (new circuits) added by an update and the circuits needed for the operation of the new circuits. 
         [0194]    In the FPGA diagnosis program  3137 , circuits to be diagnosed, diagnosis processing, etc., are set in advance. 
         [0195]    The FPGA FMEM  3141  stores the FPGA data (area 0  version)  3142 . 
         [0196]    FPGA data (area 0  version)  3142  is information on circuits to be configured within the FPGA  3151 . The FPGA data (area 0  version)  3142  is generated by the MPU  3111  copying the FPGA data (area 0  version)  3135 . Consequently, the contents of the FPGA data (area 0  version)  3142  and those of the FPGA data (area 0  version)  3135  are the same. 
         [0197]    In the FPGA  3151 , based on the FPGA data (area 0  version)  3142 , the old circuits  3181 - 1  to  3181 - n  and a new circuit (area 0  version)  3191 - 1  are configured. Hereinafter, the old circuits  3181 - 1  to  3181 - n  are represented as the old circuits  1  to n, respectively, and the new circuit  3191 - 1  as the new circuit  1  (area 0  version). 
         [0198]    The old circuits  1  to n are the circuits already configured within the FPGA  3151  also in the FPGA  3151  before an update. 
         [0199]    The new circuit  1  (area 0  version) is a circuit newly added in the FPGA  3151  after an update, in contrast to the FPGA  3151  before an update. 
         [0200]    The old circuit  1  connects with the new circuit  1  (area 0  version) and the MPU  3111 . 
         [0201]    The old circuit  2  connects with the new circuit  1  (area 0  version) and the old circuit  3 . 
         [0202]    The old circuit  3  connects with the old circuit  2  and the control devices  3161 - 1  to  3161 - m.    
         [0203]    The new circuit  1  (area 0  version) connects with the old circuits  1  and  2 . The new circuit  1  is a circuit that operates at the time of normal operation of the system  3101 . 
         [0204]    The new circuit  1  (area 0  version) is configured in an area area 0  within the FPGA  3151 . 
         [0205]    The old circuits  1  to  3  are the circuits needed for the operation of the new circuit  1  (area 0  version). The circuit needed for the operation of the new circuit is a circuit that operates (is used) at the time of the operation of the new circuit. The circuit needed for the operation of the new circuit is, for example, a circuit that generates data used by the new circuit at the time of the operation and outputs the data to the new circuit, relays data input from another circuit to the new circuit, etc. 
         [0206]    The old circuits  4  to n are the circuits not needed for the operation of the new circuit  1  (area 0  version). In other words, it is possible for the new circuit  1  (area 0  version) to operate normally even if the circuits  4  to n are not in operation. 
         [0207]    In the case where the FPGA diagnosis program  3137  detects an error in the new circuit  1  (area 0  version) configured in the area 0  within the FPGA  3151 , the MPU  3111  reads the FPGA data (area 1  version)  3136 , stores the FPGA data (area 1  version)  3143  in the FPGA FMEM  3141 , and reconfigures the FPGA  3151 . Then, the FPGA diagnosis program  3137  diagnoses the FPGA  3151  again. 
         [0208]      FIG. 14  is a configuration diagram at the time of the second diagnosis after an update of the system according to the third embodiment. 
         [0209]    The FPGA FMEM  3141  stores the FPGA data (area 1  version)  3143 . 
         [0210]    The FPGA data (area 1  version)  3143  is information on circuits to be configured within the FPGA  3151 . The FPGA data (area 1  version)  3143  is generated by the MPU  3111  copying the FPGA data (area 1  version)  3136 . Consequently, the contents of the FPGA data (area 1  version)  3143  and those of the FPGA data (area 1  version)  3136  are the same. 
         [0211]    The FPGA data (area 1  version)  3136  includes information on configuring a new circuit (area 1  version)  3192 - 1  having the same function as that of the new circuit (area 0  version)  3191 - 1  in an area different from the area in which the new circuit (area 0  version)  3191 - 1  is configured. 
         [0212]    In the FPGA  3151 , based on the FPGA data (area 1  version)  3143 , the old circuits  3181 - 1  to  3181 - n  and the new circuit (area 1  version)  3192 - 1  are configured. Hereinafter, the old circuits  3181 - 1  to  3181 - n  are represented as the old circuits  1  to n, respectively, and the new circuit  3192 - 1  as the new circuit  1  (area 1  version). 
         [0213]    The old circuits  1  to n are the circuits already configured within the FPGA  3151 , also in the FPGA  3151  at the time of the first diagnosis in  FIG. 13 . 
         [0214]    The new circuit  1  (area 1  version) is a circuit newly added in the FPGA  3151  after an update, in contrast to the FPGA  3151  before an update in  FIG. 12 . 
         [0215]    The old circuit  1  connects with the new circuit  1  (area 1  version) and the MPU  3111 . 
         [0216]    The old circuit  2  connects with the new circuit  1  (area 1  version) and the old circuit  3 . 
         [0217]    The old circuit  3  connects with the old circuit  2  and the control devices  3161 - 1  to  3161 - m.    
         [0218]    The new circuit  1  (area 1  version) connects with the old circuits  1  and  2 . The new circuit  1  is a circuit that operates at the time of normal operation of the system  3101 . 
         [0219]    The new circuit  1  (area 1  version) is configured in an area area 1  within the FPGA  3151 . The area area 1  is an area different from the area area 0 . 
         [0220]    The function of the new circuit  1  (area 1  version) is the same as that of the new circuit  1  (area 0  version). 
         [0221]    The old circuits  1  to  3  are the circuits needed for the operation of the new circuit  1  (area 1  version). The circuit needed for the operation of the new circuit is a circuit that operates (is used) at the time of the operation of the new circuit. The circuit needed for the operation of the new circuit is, for example, a circuit that generates data used by the new circuit at the time of the operation and outputs the data to the new circuit, relays data input from another circuit to the new circuit, etc. 
         [0222]    The old circuits  4  to n are the circuits not needed for the operation of the new circuit  1  (area 1  version). In other words, it is possible for the new circuit  1  (area 1  version) to operate normally even if the circuits  4  to n are not in operation. 
         [0223]      FIG. 15  is a flowchart of a diagnosis method according to the third embodiment. 
         [0224]    The FPGA  3151  has already been reconfigured based on the FPGA data  3142  and the configuration is that before an update illustrated in  FIG. 12 . 
         [0225]    It is assumed that the MPU  3111  has executed the MPU firmware  3133 . 
         [0226]    At step S 3501 , the MPU  3111  receives the firm package  3132  via the communication unit  3171  from an external device connected with the system  3101  via the network and writes the firm package  3132  to the MPU FMEM  3131 . 
         [0227]    At step S 3502 , the MPU  3111  reads the FPGA data (area 0  version)  3135 , serves as a bus master via a serial bus  3201 , and writes it to the FPGA FMEM  3141 . The FPGA data (area 0  version) written to the FPGA FMEM  3141  as described above is represented as the FPGA data  3142 . 
         [0228]    At step S 3503 , the MPU  3111  gives instructions to perform reconfiguration to the FPGA  3151 . Upon receipt of the instructions, the FPGA  3151  performs reconfiguration. In detail, the FPGA  3151  reads the FPGA data (area 0  version)  3142  and configures the old circuits  1  to n and the new circuit  1  (area 0  version) based on the FPGA data (area 0  version)  3142 . As described above, the new circuit  1  (area 0  version) is configured in the area area 0  within the FPGA  3151 . It may also be possible for the FPGA  3151  to receive the FPGA data (area 0  version)  3135  from the MPU FMEM  3131  via the MPU  3111  and to configure the old circuits  1  to n and the new circuit  1  (area 0  version) based on the FPGA data (area 0  version)  3135 . In such a case, the processing to write the FPGA data (area 0  version)  3135  to the FPGA FMEM  3141  at step S 3502  may be omitted. 
         [0229]    At step S 3504 , the MPU  3111  executes the FPGA diagnosis program  3137 . By means of the FPGA diagnosis program  3137 , the MPU  3111  diagnoses the new circuit  1  (area 0  version) and the old circuits  1  to  3 . In the diagnosis processing, for example, predetermined commands and data are input to a circuit to be diagnosed and whether or not the circuit operates normally is checked. 
         [0230]    At step S 3505 , in the case where the diagnosis is completed normally, the processing is exited and in the case where the diagnosis is not completed normally (i.e., in the case where an error is detected in any of the new circuit  1  (area 0  version) and the old circuits  1  to  3 ), the control proceeds to step S 3506 . 
         [0231]    At step S 3506 , the MPU  3111  reads the FPGA data (area 1  version)  3136 , serves as a bus master via the serial bus  3201 , and writes it to the FPGA FMEM  3141 . The FPGA data (area 1  version) written to the FPGA FMEM  3141  as described above is represented as the FPGA data  3143 . 
         [0232]    At step S 3507 , the MPU  3111  gives instructions to perform reconfiguration to the FPGA  3151 . Upon receipt of the instructions, the FPGA  3151  performs reconfiguration. In detail, the FPGA  3151  reads the FPGA data (area 1  version)  3143  and configures the old circuits  1  to n and the new circuit  1  (area 1  version) based on the FPGA data (area 1  version)  3143 . As described above, the new circuit  1  (area 1  version) is configured in the area area 1  of the FPGA  3151 . It may also be possible for the FPGA  3151  to receive the FPGA data (area 1  version)  3136  from the MPU FMEM  3131  and to configure the old circuits  1  to n and the new circuit  1  (area 1  version) based on the FPGA data (area 0  version)  3136 . In such a case, the processing to write the FPGA data (area 1  version)  3136  to the FPGA FMEM  3141  at step S 3506  may be omitted. 
         [0233]    At step S 3508 , the MPU  3111  executes the FPGA diagnosis program  3137  again. By means of the FPGA diagnosis program  3137 , the MPU  3111  diagnoses the new circuit  1  (area 1  version) and the old circuits  1  to  3 . 
         [0234]    At step S 3509 , in the case where the diagnosis is completed normally, the processing is exited and in the case where the diagnosis is not completed normally (i.e., in the case where an error is detected in any of the new circuit  1  (area 1  version) and the old circuits  1  to  3 ), the control proceeds to step S 3510 . 
         [0235]    At step S 3510 , the MPU  3111  makes a notification of a failure. For example, the MPU  3111  produces a display to the effect that an error is detected on the display unit (not illustrated) of the system  3101  or notifies an external device connected with the system  3101  via the network of the error. 
         [0236]    According to the system of the third embodiment, by diagnosing all the circuits newly added by an update, an error due to the potential failure is no longer detected while the system is in operation, and therefore, reliability of the system is improved. 
         [0237]    In the case where the potential failures occur concentratedly in a certain portion in the manufacturing process of the FPGA, if an updating is performed in a number of systems, the failure of the FPGA is detected in the number of systems and there is a possibility that the parts for maintenance will run short. 
         [0238]    According to the system of the third embodiment, in the case where a failure is detected by diagnosis, it is possible to do without replacement of the FPGAs by configuring a new circuit again in another area to avoid the failure. 
         [0239]    According to the system of the third embodiment, it is possible to avoid the risk that parts for maintenance will run short and to reduce the amount of maintenance work by avoiding potential failures without increasing the circuit use rate of the FPGA. 
         [0240]      FIG. 16  is a configuration diagram of an information processing apparatus (computer). 
         [0241]    The systems  1101 ,  2101 , and  3101  of the embodiments are implemented by, for example, an information processing apparatus  1  as illustrated in  FIG. 16 . 
         [0242]    The information processing apparatus  1  includes a central processing unit (CPU)  2 , a memory  3 , an input unit  4 , an output unit  5 , a storage unit  6 , a recording medium drive unit  7 , and a network connection unit  8 , and these units are connected to one another by a bus  9 . 
         [0243]    The CPU  2  is a central processing unit that controls the whole of the information processing apparatus  1 . The CPU  2  corresponds to the MPUs  1111 ,  2111 , and  3111 . 
         [0244]    The memory  3  is a memory, such as a read only memory (ROM) or a random access memory (RAM), which temporarily stores a program or data stored in the storage unit  6  (or a portable recording medium  10 ) when the program is executed. The CPU  2  performs the above-described various kinds of processing by executing programs by using the memory  3 . 
         [0245]    In this case, the program code itself read from the portable recording medium  10  etc. implements the function of the embodiments. 
         [0246]    The input unit  4  is, for example, a keyboard, a mouse, a touch panel, etc. 
         [0247]    The output unit  5  is, for example, a display, a printer, etc. 
         [0248]    The storage unit  6  is, for example, a magnetic disk device, an optical disk device, a tape device, a nonvolatile memory, etc. The information processing apparatus  1  saves the above-described programs and data in the storage unit  6  and reads them onto the memory  3  for use in accordance with necessity. 
         [0249]    The storage unit  6  corresponds to the MPU FMEMs  1131 ,  2131 , and  3131  and the FPGA FMEMs  1141 ,  2141 , and  3141 . 
         [0250]    The recording medium drive unit  7  drives the portable recording medium  10  and accesses the contents recorded therein. As the portable recording medium, any computer-readable recording medium, such as a memory card, a flexible disk, a compact disk read only memory (CD-ROM), an optical disk, and a magneto-optical disk, can be used. A user stores the above-described programs and data in the portable recording medium  10  and reads them onto the memory  3  for use in accordance with necessity. 
         [0251]    The network connection unit  8  is connected to a communication network, such as a LAN and a WAN, and carries out data conversion accompanying communication. The network connection unit  8  corresponds to the communication units  1171 ,  2172 , and  3171 . 
         [0252]    An FPGA  11  configures circuits inside thereof based on the FPGA data. The FPGA  11  corresponds to the FPGAs  1151 ,  2151 , and  3151 . 
         [0253]    All examples and conditional language provided herein are intended for pedagogical purposes to aiding the reader in understanding the invention and the concepts contributed by the inventor to further the art, and are not to be construed as being limitations to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although one or more embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.