Abstract:
Missing code linearity in an A to D converter is corrected by associating each of the bits of a raw ADC output with a correction code for that bit.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of the U.S. Provisional Application No. 60/061,652, filed Oct. 10, 1997, which is incorporated herein by reference. 
    
    
     BACKGROUND 
     A common error in an A to D converter comes from inaccurate relationship among the sizes of the capacitors used in the conversion. For example, a scaled capacitor network uses relative capacitor sizes which are scaled according to the relation of ½ n , where n is between 0 and the maximum number of bits desired. FIG. 1A shows some capacitors, with the relative sizes of 1, ½, ¼ . . . {fraction (1/32)}. A differential nonlinearity (“DNL”) error is caused by inaccuracies in the capacitances of these scaled capacitors. This differential nonlinearity can cause missing codes. 
     For example, the effect is shown with reference to FIG.  1 B. In FIG. 1B, increasing the voltage one increment beyond the voltage  150  that produces the code 01111111, yields a jump to code 1000011. This means that the codes between 01111111 and 1000011 are never used. These “missing codes” result in granularity of the A/D converter and also effectively reduce the dynamic ranges of the converter since fewer codes are available for use. 
     It has been suggested to correct this error using a look-up table for each value. However, this requires a large amount of memory. 
     SUMMARY 
     The present system describes a technique of correcting and compensating for this systematic error. This is done by assigning a limited universe of correction factors. Each correction factor depends on states of certain bits of the code. 
     A first embodiment assigns a correction factor to each bit of a code and adds them. 
     A second embodiment assigns correction factors to certain sets of most significant bits. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1A and 1B show effects in A to D converters; 
     FIG. 2 shows a correction circuit; and 
     FIG. 3 shows a second correction circuit with prestored information. 
    
    
     DETAILED DESCRIPTION 
     The inventor postulates that fringe effects in these capacitors are largely responsible for the errors. These fringe effects include fringe capacitance effects shown generally as  110  in FIG.  1 A. The larger capacitors typically include larger errors. 
     The inventor recognized that systems of this type, which use a scaled capacitor network, have errors that are visible at the interface between the different bits. For example, the error described above occurs at the transition between the code 01111111 and what should be the next code—10000000. (See FIG. 1B) These errors were found to be based on the number of bits of the code that are active. 
     The inventor therefore realized that the nonlinearity could be corrected based on the active bits. 
     According to this embodiment, illustrated an initial A to D conversion is made by A to D converter  200 . The output bits are analyzed to determine which bits include “1”s. Each “1” represents an associated error amount. These error amounts can be determined empirically. For example, a “1” in the most significant bit indicates that the output will include an error factor e 1 . In the example discussed above, the error e 1 is equivalent to the amount of the two lowest bits 00000011. The other error factors shown as e 2 , e 3 , e 4 , and e 5  can be similarly determined. 
     The embodiment, which corrects these errors, is shown in the circuit of FIG. 2. A pipelined set of value holding elements  204 ,  206 ,  208 ,  210 ,  212  are each associated with an error e n . Each element is enabled by a “1” in their corresponding bits. Each element, when enabled, provides the offset to adder  215 , to add or subtract the desired offset from the ADC output  202 . 
     For example, when there is a “1” in the MSB, e 1  is subtracted. Each subtracting operation is enabled by a “1” in a corresponding A to D converter output bit. Therefore, if the two most significant output bits are active, the A to D converter is corrected by the amount equivalent to (e 1 +e 2 ). 
     FIG. 2 preferably uses a digital adder  215  to carry out the addition. The value holding elements can be adders, memory locations or other structure. The system as shown can be used for a 5-bit system, or, more preferably, for the most significant 5 bits of an 8-bit system. 
     A second embodiment is shown in FIG.  3 . This circuit uses a decoder  300  for analyzing the major bits. The output enables a sum of errors to be output as a single additive value. The output is added/subtracted to the ADC output  202  by subtractor  310 . The architecture for correcting DNL in three most significant bits is shown in FIG.  3 . This system does not correct all bit errors, just the most significant errors. 
     The decoder outputs enable a pre-stored value representing a sum of errors to be added in adder  310 . The sum of errors stored in  305  can be memory cells or partial sum adders, for example. This value can be subtracted from the ADC output  202  in real time, or one clock delay later. 
     Other embodiments are within the enclosed invention.