Abstract:
A memory system and corresponding method of wear-leveling are provided, the system including a controller, a random access memory in signal communication with the controller, and another memory in signal communication with the controller, the other memory comprising a plurality of groups, each group comprising a plurality of first erase units or blocks and a plurality of second blocks, wherein the controller exchanges a first block from a group with a second block in response to at least one block erase count within the group; and the method including receiving a command having a logical address, converting the logical address into a logical block number, determining a group number for a group that includes the converted logical block number, and checking whether group information comprising block erase counts for the group is loaded into random access memory, and if not, loading the group information into random access memory.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims foreign priority under 35 U.S.C. §119 to Korean Patent Application No. P2007-0058417 (Atty. Dkt. ID-200702-033), filed on Jun. 14, 2007, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. 
       BACKGROUND OF THE INVENTION 
       [0002]    The present disclosure generally relates to data storage systems using flash memory technologies. More specifically, the present disclosure relates to controlling flash memory systems to substantially extend their useful lifetime or endurance. 
         [0003]    Flash memory is typically divided into several blocks, each of which is individually erasable. All flash memory cells within a block are typically erased together. Flash memory cells each have a limited useful lifetime in terms of the number of times that they can be reprogrammed or erased. This limitation may often be due to electrons becoming trapped in the respective gate and tunnel dielectric layers during repetitive programming. Repeated erasure of a block tends to wear out the cells in the block leading to a reduced capability to distinguish between the erased state and the programmed state, and resulting in a longer time required to erase the block. 
         [0004]    The ability of a Flash memory device to withstand wear is often called “endurance”. The endurance may be specified in terms of the minimum or the average number of times that each Flash block may be erased without encountering significant failures. Endurance numbers are currently in the range of hundreds of thousands of cycles in the case of single level cell (“SLC”) devices, and in the range of tens of thousands of cycles in the case of multi level cell (“MLC”) devices. Repeated and frequent writes to a single block, or to a small number of blocks, will bring the onset of failures sooner and end the useful lifetime of the flash device more quickly. 
         [0005]    Wear-leveling is a class of techniques, typically implemented in firmware, for balancing the erase counts of physical blocks to better utilize the expected lifetime of NAND flash devices, for example. If the write operations can be more evenly distributed among all blocks of the device, each block will experience closer to the maximum number of erases that it can endure before other blocks exceed the maximum. Thus, the onset of failures may be substantially delayed, thereby increasing the useful lifetime and endurance of the Flash memory device. 
       SUMMARY OF THE INVENTION 
       [0006]    These and other issues are addressed by a system and method for flash memory wear-leveling. Exemplary embodiments are provided. 
         [0007]    An exemplary memory system with wear-leveling includes a wear-leveling controller, a random access memory in signal communication with the controller, and another memory in signal communication with the controller, the other memory comprising a plurality of groups, each group comprising a plurality of first erase units or blocks and a plurality of second blocks, wherein the controller exchanges a first block from a group with a second block in response to at least one block erase count within the group. 
         [0008]    An exemplary method of wear-leveling a memory device includes receiving a command having a logical address, converting the logical address into a logical block number, determining a group number for a group that includes the converted logical block number, and checking whether group information comprising block erase counts for the group is loaded into random access memory, and if not, loading the group information into random access memory. 
         [0009]    Another exemplary method of wear-leveling a memory device includes dividing a first region of the device into a plurality of groups wherein each group comprises a plurality of erase units or blocks, calculating a group erase count for each group in response to at least one block erase count from the group, and replacing a block in one group in response to a comparison of the calculated group erase counts. 
         [0010]    The present disclosure will be further understood from the following description of exemplary embodiments, which is to be read in connection with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    The present disclosure provides a system and related method for flash memory wear-leveling in accordance with the following exemplary figures, in which: 
           [0012]      FIG. 1  shows a schematic block diagram for a flash memory system; 
           [0013]      FIG. 2  shows a schematic block diagram for a flash memory controller; 
           [0014]      FIG. 3  shows a schematic block diagram for a wear-leveling flash memory controller with data block to data block interchange; 
           [0015]      FIG. 4  shows a schematic block diagram for a wear-leveling flash memory controller with data block to free block interchange; 
           [0016]      FIG. 5  shows a schematic block diagram for a wear-leveling flash memory that maintains erase counts for memory blocks in spare areas of the respective memory blocks; 
           [0017]      FIG. 6  shows a schematic block diagram for a wear-leveling flash memory that maintains erase counts for memory blocks in separate meta blocks; 
           [0018]      FIG. 7  shows a schematic block diagram for a wear-leveling flash memory controller that performs wear-leveling between free blocks and data blocks in accordance with an exemplary embodiment of the present disclosure; 
           [0019]      FIG. 8  shows a schematic flow diagram for a wear-leveling flash memory control where group counts are calculated and swapping is performed when the number of merge operations exceeds a predetermined number in accordance with an exemplary embodiment of the present disclosure; 
           [0020]      FIG. 9  shows a schematic flow diagram for a wear-leveling flash memory control where group counts are always calculated after write operations, and swapping is performed when a variance between the minimum free block erase count and the minimum data block erase count exceeds a predetermined number in accordance with an exemplary embodiment of the present disclosure; and 
           [0021]      FIG. 10  shows a schematic block diagram for a flash card memory system in accordance with an exemplary embodiment of the present disclosure. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0022]    As shown in  FIG. 1 , a flash memory system is indicated generally by the reference numeral  100 . The flash memory system  100  includes a processor  116 , a flash memory  110  in signal communication with the processor, a read-only memory (“ROM”)  112  in signal communication with the processor, and a random access memory (“RAM”)  114  in signal communication with the processor. The ROM  112 , for example, may include program steps executable by the processor  116  for providing read and write commands to read data from and write data to the flash memory  110  or the RAM  114 . The flash memory  110  may include a wear-leveling controller to perform read and write operations in the flash memory in response to the commands. Alternately, the processor  116  may implement a wear-leveling control, such as a firmware control from the ROM  112 , for example. The read and write operations responsive to the commands are performed in the flash memory  110  in accordance with wear-leveling embodiments of the present disclosure. In addition, the ROM  112  and the RAM  114  may store related data structures and/or application program steps executable by the processor  116 . 
         [0023]    Turning to  FIG. 2 , a flash memory controller is indicated generally by the reference numeral  200 . The controller  200  includes a logical address unit  210  connected to a mapping table  220 , which, in turn, is connected to a memory bank  230 . The mapping table  220  includes a number of logical to physical entries. In this example, logical addresses 0, 1, 2, 3 . . . 10 are mapped to physical addresses  100 ,  110 ,  120 ,  130  . . .  200 , respectively. The memory bank  230  includes a number of physical memory blocks having physical addresses  100 ,  110 ,  120 ,  130  . . .  200 . Each physical memory block has an associated erase count (“EC”). In this example, the physical memory blocks at physical addresses  100 ,  110 ,  120 ,  130  . . .  200  have erase counts of 8000, 5000, 3000, 1000 . . . 500, respectively. 
         [0024]    In operation, the controller  200  accesses a physical address (e.g., Block  100 ) in the memory bank  230  corresponding to a logical address (e.g., “0”) from the mapping table  220 , and writes data received from a host to the block at that physical address. Irrespective of the frequency in use or erase count of each block, data is unconditionally written into a block initially assigned in the mapping table. In many cases, only a few blocks are used frequently and worn. 
         [0025]    Turning now to  FIG. 3 , a flash memory controller with active wear-leveling and data block to data block interchange is indicated generally by the reference numeral  300 . The controller  300  includes a logical address unit  310  connected to a mapping table  320 , which, in turn, is connected to a memory bank  330 . The mapping table  320  includes a number of logical to physical entries. In this example, logical addresses 0, 1, 2, 3 . . . 10 are mapped to physical addresses  200 ,  110 ,  120 ,  130  . . .  100 , respectively. The memory bank  330  includes a number of physical memory blocks having physical addresses  100 ,  110 ,  120 ,  130  . . .  200 . Each physical memory block has an associated erase count (“EC”). In this example, the physical memory blocks at physical addresses  100 ,  110 ,  120 ,  130  . . .  200  have erase counts of 8000, 5000, 3000, 1000 . . . 500, respectively. 
         [0026]    In operation, the controller  300  performs a remapping process so that the variation in the number of writes or erase counts of each block will not exceed a predetermined number. The mapping table  320  maps original logical addresses to updated physical addresses. In this example, the physical addresses associated with logical addresses 0 and 10 are exchanged. That is, logical address 0 becomes associated with physical block  200 , which has a current erase count of 500, while logical address 10 becomes associated with physical block  100 , which has a current erase count of 8000. Thus, the blocks are used more evenly and endurance is improved. 
         [0027]    As shown in  FIG. 4 , a flash memory controller with active wear-leveling and data block to free block interchange is indicated generally by the reference numeral  400 . The controller  400  includes a logical address unit  410  connected to a mapping table  420 , which, in turn, is connected to a memory bank  430 . The mapping table  420  includes a number of logical to physical entries. In this example, logical addresses 0, 1, 2, 3 . . . 10 are mapped to physical addresses  200 ,  110 ,  120 ,  130  . . .  300 , respectively. The memory bank  430  includes a number of physical memory blocks having physical addresses  100 ,  110 ,  120 ,  130  . . .  200 ,  300 . Each physical memory block has an associated erase count (“EC”). In this example, the physical memory blocks at physical addresses  100 ,  110 ,  120 ,  130  . . .  200 ,  300  have erase counts of 8000, 5000, 3000, 1000 . . . 500, 0, respectively. 
         [0028]    In operation, the controller  400  performs a remapping process so that the variation in the number of writes or erase counts of each block will not exceed a predetermined number. The mapping table  420  maps original logical addresses to updated physical addresses. In this example, the physical address associated with logical address 10 is updated to that of block  300 , and then the physical address associated with logical address 0 is updated to that of block  200 . That is, logical address 0 becomes associated with physical block  200 , which has a current erase count of 500, while logical address 10 becomes associated with physical block  300 , which has a current erase count of 0. Therefore, the blocks are used more evenly and endurance is improved. 
         [0029]    Turning to  FIG. 5 , a wear-leveling flash memory is indicated generally by the reference numeral  500 . The wear-leveling flash memory may include data blocks  510  each having a spare area  511 , free or log blocks  512 , and reserved blocks  514 . The data blocks are used to store data. The free blocks are initially unused. The log blocks are drawn from the free blocks and used to store updates to data blocks. The wear-leveling flash memory  500  maintains erase counts for memory blocks in the spare areas  511  of the respective data blocks  510 . That is, a controller may record the number of erases that each block has experienced, or its erase count, in the spare areas of the respective blocks. An address translator within the controller may receive a logical address from a host, and translate the logical address into a physical address, which indicates an actual location of the flash memory in which data will be stored. Thus, remapping is performed to balance the frequency of use or erase counts for the memory blocks. 
         [0030]    In operation of the flash memory  500 , erase counts are stored in spare areas  511  of the data blocks  510 . Referring back to the controller  400  of  FIG. 4 , for example, data stored in a memory block having a minimum erase count (e.g., Block  200 ) is moved to a current spare block (e.g., Block  300 ). Data stored in a memory block having a maximum erase count (e.g., Block  100 ) is moved to a memory block having a minimum erase count (e.g., Block  200 ). Data in a memory block having a maximum erase count (e.g., Block  100 ) is assigned to new spare block. The new spare block (e.g., Block  100 ) is not used until erase counts of other blocks are larger than that of this block. When the new spare block is used, the address mapping or translation table is updated accordingly. 
         [0031]    Turning now to  FIG. 6 , a flash memory with wear-leveling is indicated generally by the reference numeral  600 . The wear-leveling flash memory may include data blocks  610 , free or log blocks  612 , reserved blocks  614  and meta blocks  616 . The data blocks are currently used to store data. The free blocks are initially unused. The log blocks are drawn from the free blocks and used to store updates to data blocks or updates to meta blocks, and the meta blocks may be used to store logical to physical mapping information. In addition, the wear-leveling flash memory  600  maintains erase counts for memory blocks in the meta blocks  616 . That is, the wear-leveling flash memory  600  maintains erase counts for data blocks in the separate meta blocks. Thus, the wear-leveling flash memory  600  does not need to store erase counts in spare areas of the data blocks, for example, and need not individually access each data block merely to determine its stored erase count. Accessing multiple erase counts stored in a meta block is faster and more efficient, for example. 
         [0032]    In operation of a 4G NAND Flash Memory that is composed of 4,096 blocks, for example, erase counts of each block may be stored in meta blocks rather than in a spare region of each block. When data is received, the controller assigns a free block to a log block according to a logical address of the data, and writes the received data into the log block. 
         [0033]    If no free blocks remain, a merge operation is performed. The merge operation merges valid data of a log block and a data block corresponding to the log block, and generates new free blocks. Free or log blocks and meta blocks are the most frequently updated. A wear-leveling technique is performed between the free blocks and data blocks, and between the meta blocks and free blocks. 
         [0034]    For a basic free block wear-leveling, erase counts of all data blocks are compared to each other. A search of the meta data for the maximum and/or minimum erase counts of all data blocks is performed. In addition, a high-density static random access memory (“SRAM”) may be used for scanning erase counts of all data blocks more quickly. Controllers may include about 20 KB of SRAM. In a 4G NAND Flash Memory with 4,096 blocks, 16 KB of SRAM may be used to expeditiously compare the erase counts. SRAM may also store other data, such as a mapping table. A careful balance of SRAM usage should be maintained in order to minimize degradation of controller performance due to comparisons of erase counts for all data blocks in this basic free block wear-leveling. 
         [0035]    As shown in  FIG. 7 , a wear-leveling flash memory controller is indicated generally by the reference numeral  700 . The flash memory controller  700  performs wear-leveling between free blocks and data blocks in accordance with an exemplary embodiment of the present disclosure. The exemplary flash memory controller  700  includes first through fourth memory block groups  710 ,  720 ,  730  and  740 , respectively. Each memory block group includes a plurality of memory blocks, each having a logical address. A group count is associated with each group. 
         [0036]    In this exemplary embodiment, the logical addresses of the memory blocks are interlaced among the groups. An algorithm for grouping the memory blocks determines the group number as the block number modulo the total number of groups. With four groups, for example, the block number may be determined as the block number modulo  4 . 
         [0037]    Thus, when the modulo remainder is zero, the block is grouped into the 0 th  group, here Group  710 . When the modulo remainder is one, the block is grouped into the 1 st  group, here Group  720 . When the modulo remainder is two, the block is grouped into the 2 nd  group, here Group  730 . When the modulo remainder is three, the block is grouped into the 3 rd  group, here Group  740 . Thus, group  710  includes the memory blocks having logical addresses 0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40 . . . ; Group  720  includes the memory blocks having logical addresses 1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41 . . . ; Group  730  includes the memory blocks having logical addresses 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42 . . . ; and Group  740  includes the memory blocks having logical addresses 3, 7, 11, 15, 19, 23, 27, 31, 35, 39, 43 . . . . Here, Group  710  has an associated Group Count of 200; Group  720  has an associated Group Count of 300; Group  730  has an associated Group Count of 500; and Group  740  has an associated Group Count of 100. 
         [0038]    The flash memory controller  700  further includes log blocks  750  and free blocks  760 . Any free block may be exchanged with any physical block indicated by a logical address in any of the groups. In addition, any log block may be associated with any logical address. 
         [0039]    In operation of the wear-leveling flash memory controller  700 , a Group Count is calculated for each group. The Group Count may be the maximum erase count for any block in the group, for example. In this exemplary case, the group having the minimum Group Count is selected, such as the group  740  having a Group Count  742  of 100. Next, this group is scanned to determine the minimum erase count for any block in the group. Here, the physical block  744  associated with logical address #15 has the minimum erase count of 3. The free block having a maximum erase count of all free blocks, such as the free block  760  that has an erase count of 32, is swapped with the block  744 , which has the minimum erase count in group  740 . In a wear-leveling scheme between free blocks and data blocks, for example, data blocks are divided into several groups, such as four groups in the example above. The free block wear-leveling includes calculating erase counts for blocks within groups, saving the maximum erase count of all data blocks within a group as the group count for that group, selecting the data block having the minimum erase count of data blocks in that group having the minimum group count, and swapping the free block with the maximum erase count of the free blocks for the selected data block. Thus, only the erase counts in the group with the minimum group count are scanned. 
         [0040]    In alternate embodiments, the data blocks may include standard data, meta data, and/or log data. In further embodiments, a group count may be defined as the minimum erase count in a group, as the average erase count in a group, or the like rather than as the maximum erase count in the group as in the current exemplary embodiment. In one alternate embodiment, a meta block wear-leveling control is considered. This is a wear-leveling scheme between meta blocks and free blocks. The meta block wear-leveling may be performed whenever writing data. The number of meta blocks may be smaller than the number of data blocks. 
         [0041]    If the number of meta blocks is much smaller than the number of data blocks, the time for comparing erase counts of meta blocks may be relatively fast. Thus, the grouping scheme may not be needed. 
         [0042]    In operation of the alternate meta block wear-leveling, the method includes finding the meta block with the maximum erase count of all of the meta blocks, finding a free block with the minimum erase count of all of the free blocks, and swapping the found meta block for the found free block. 
         [0043]    Turning to  FIG. 8 , a free block wear-leveling flash memory control is indicated generally by the reference numeral  800 . In the control  800 , group counts are calculated and swapping is performed when the number of merge operations exceeds a predetermined number. The control  800  includes a start block  810  that passes control to a function block  812 . The function block  812  converts a logical address to a logical block number, and passes control to a function block  814 . The function block  814  determines a group number corresponding to the logical block number, and passes control to a decision block  816 . The decision block  816  determines whether the group information is loaded into SRAM, and if so, passes control to function block  820 . If not, control passes control to function block  818 , which loads the group information into SRAM, and then passes to function block  820 . Function block  820  determines the physical block address corresponding to the logical block number, and passes control to a decision block  822 . 
         [0044]    The decision block  822 , in turn, determines whether a log block corresponding to the same logical block address already exists, and if so, passes control to a function block  824 , which writes the data to a log block and passes control to a decision block  834 . If not, the decision block  822  passes control to a decision block  826 , which determines whether any free blocks currently exist, and if so, passes control to a function block  832 , which writes data to the free block and passes control to the decision block  834 . If not, the decision block  826  passes control to a function block  828 , which performs a merge operation. The function block  828 , in turn, passes control to a function block  830 , which writes data to a new free block, and passes control to the decision block  834 . 
         [0045]    The decision block  834  determines whether the number of merge operations is greater than a predetermined number, and if not, control passes to an end block  842 . If so, control passes to a function block  836 , which calculates a group count. The function block  836 , in turn, passes control to a function block  838 , which selects a data block with a minimum erase count from a group with a minimum group count. The function block  838  passes control to a function block  840 , which swaps a free block with having a maximum erase count for the selected data block. The function block  840  passes control to the end block  842 . Thus, group counts are calculated and swapping is performed when the number of merge operations is determined at decision block  834  to exceed a predetermined number. Turning now to  FIG. 9 , another free block wear-leveling flash memory control is indicated generally by the reference numeral  900 . In the control  900 , group counts are always calculated after write operations, and swapping is performed when a variance between the minimum free block erase count and the minimum data block erase count exceeds a predetermined number. The control  900  includes a start block  910  that passes control to a function block  912 . The function block  912  converts a logical address to a logical block number, and passes control to a function block  914 . The function block  914  determines a group number corresponding to the logical block number, and passes control to a decision block  916 . The decision block  916  determines whether the group information is loaded into SRAM, and if so, passes control to function block  920 . If not, control passes to function block  918 , which loads the group information into SRAM, and then passes control to function block  920 . Function block  920  determines the physical block address corresponding to the logical block number, and passes control to a decision block  922 . 
         [0046]    The decision block  922 , in turn, determines whether a log block corresponding to the same logical block address already exists, and if so, passes control to a function block  924 , which writes the data to a log block and passes control to a function block  932 . If not, the decision block  922  passes control to a decision block  926 , which determines whether any free blocks currently exist, and if so, passes control to the function block  932 , which calculates the group count and passes control to a function block  934 . If not, the decision block  926  passes control to a function block  928 , which performs a merge operation. The function block  928 , in turn, passes control to a function block  930 , which generates a new free block and passes control to the function block  932 . 
         [0047]    The function block  934  selects a data block having a minimum erase count from a group having a minimum group count, and passes control to a decision clock  936 . The decision block  936  determines whether the minimum free block erase count minus the selected minimum data block erase count is greater than a predetermined number. If so, control passes to a function block  938 . If not, control passes to a function block  940 . The function block  938  swaps the free block for the data block, and passes control to the function block  940 . The function block  940  writes data to the free block, and passes control to an end block  942 . 
         [0048]    Thus, in the control  900 , group counts are always calculated after a write operation. Swapping is performed when the variance between the minimum free block erase count and the minimum data block erase count is determined at decision block  936  to exceed a predetermined number. 
         [0049]    As shown in  FIG. 10 , a flash card memory system with wear-leveling is indicated generally by the reference numeral  1000 . The flash card system includes a host  1010  and a flash card  1020 . The flash card  1020  includes a controller  1030  and a flash memory  1040 . The controller  1030  includes a host interface  1031  in signal communication between the host  1010  and a bus  1032 ; a flash interface  1033  in signal communication between the bus  1032  and the flash memory  1040 ; a buffer memory  1035 , such as SRAM, in signal communication with the bus  1032 ; a processor or CPU  1037  in signal communication with the bus  1032 ; and a read-only memory (“ROM”), such as mask ROM, in signal communication with the bus  1032 . 
         [0050]    In operation of the system  1000 , firmware for wear-leveling may be stored in the ROM  1039  or in the flash memory  1040 , for example. The erase count of each block is loaded to buffer memory  1035  from meta blocks within the flash memory  1040 , and sorted by the CPU  1037 . 
         [0051]    Although illustrative embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the present disclosure is not limited to those precise embodiments, and that various other changes and modifications may be effected therein by those of ordinary skill in the pertinent art without departing from the scope or spirit of the present disclosure. All such changes and modifications are intended to be included within the scope of the present disclosure as set forth in the appended claims.