Abstract:
A wafer-scale assembly circuit including a plurality of metal interconnect layers, where each metal layer includes patterned metal portions and where at least some of the patterned metal portions are RF signal lines. The circuit further includes at least one benzocyclobutene layer provided between two metal interconnect layers that includes at least one trench via formed around a perimeter of the benzocyclobutene layer at a circuit sealing ring, where the trench via provides a hermetic seal at the sealing ring. The benzocyclobutene layer also includes a plurality of stabilizing post vias formed through the benzocyclobutene layer adjacent to the trench via proximate to the sealing ring and extending around the perimeter of the benzocyclobutene layer, where the stabilizing vias operate to prevent the benzocyclobutene layer from shrinking in size.

Description:
BACKGROUND 
     1. Field of the Disclosure 
     This invention relates generally to wafer-scale assembly (WSA) circuits that include benzocyclobutene (BCB) layers and, more particular, to WSA circuits that include BCB layers, and trench vias and a checkerboard pattern of vias through the BCB layers at a sealing ring edge of the layer to provide a hermetic seal and prevent BCB layer shrinkage. 
     2. Discussion of the Related Art 
     It is known in the art to provide wafer-level packages for integrated circuits, such as monolithic millimeter-wave integrated circuits (MMIC), formed on substrate wafers. In one wafer-level packaging design, a cover wafer is formed to the substrate wafer by a sealing ring so as to provide a hermetically sealed cavity in which the integrated circuit is provided. During wafer-scale assembly (WSA), many integrated circuits are formed on the substrate wafer and covered by a single cover wafer, where each integrated circuit is surrounded by a separate sealing ring. The cover wafer and the substrate are then diced between the sealing rings to separate the packages for each separate integrated circuit. The dicing process typically uses a saw that cuts the cover wafer between the packages where a portion of the cover wafer is removed. The substrate wafer is then cut between the packages. For certain wafer-level packaging designs, vias are provided through the substrate wafer that make electrical contact with signal lines and ground lines electrically coupled to the integrated circuit within the cavity. 
     As is well understood by those skilled in the art, integrated circuit design and WSA packaging allow for many circuit components to be fabricated in a small area. Some of these designs employ stacked metal interconnect layers where several interconnect layers are fabricated on top of each other. It has been proposed in the art to use a BCB layer to separate interconnect layers to increase device performance. The BCB layer is an insulated layer that prevents DC current from traveling from one interconnect layer to another interconnect layer, but allows RF signals to propagate therethrough, which may benefit certain circuit designs where signal line cross talk is desirable. As the number of interconnect layers increases, the complexity of the circuit can increase so that more powerful devices can be provided in a smaller hermetically sealed environment. Particularly, high frequency RF lines can cross over each other if there is a BCB layer between them that prevents a DC short between the lines. By depositing a BCB layer on an interconnect layer on either the substrate wafer or the cover wafer, another interconnect layer can be formed on the BCB layer and be electrically isolated therefrom. Metal vias would be fabricated through the BCB layers to allow interconnections between the various interconnect layers. 
     The increase in the number of interconnect layers in a WSA circuit enables new types of WSA circuit designs to be implemented, which would otherwise not be possible with standard MMIC or WSA MMIC devices. The insertion of RF shielding between interconnect layers in the vertical direction helps enable these new circuit designs to be realized. Unshielded RF coupling in the vertical direction also enables such designs. The RF shield is a metal layer that prevents both RF and DC signals from traveling from one interconnect layer to another. 
     The various interconnect layers extend to a sealing ring at an outer edge of the WSA package. However, BCB is not a hermetic material and includes a large amount of tensile stress. In order to provide the hermetic seal at the edge of the sealing ring where the BCB layers are located, an etch would need to be provided that was then filled with a metal via between the interconnect layers on opposite sides of the BCB layer so that hermetic seal of the ring can be established. However, when such a BCB via is formed at the sealing location of the ring, the tensile strength of the BCB material causes it to pull away from the metal, which affects device integrity. More particularly, the etch for the sealing vias in the BCB layers causes the BCB layer to shrink, which may disturb connect vias through the BCB layer at other locations in the assembly. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is an exploded perspective view of a wafer-scale assembly circuit including a wafer portion having a plurality of interconnect layers and a cover portion having a plurality of interconnect layers; 
         FIG. 2  is a broken-away perspective view of a portion of the wafer portion of the wafer-scale assembly shown in  FIG. 1 ; 
         FIG. 3  is a cut-away, perspective, outside view of the wafer portion of the wafer-scale assembly shown in  FIG. 1 ; 
         FIG. 4  is a cut-away, perspective, inside view of the wafer portion of the wafer-scale assembly shown in  FIG. 1 ; and 
         FIG. 5  is a cut-away, perspective, outside view of the wafer portion of the wafer-scale assembly shown in  FIG. 1 . 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     The following discussion of the embodiments of the invention directed to a wafer-scale assembly including a plurality of interconnect layers and BCB layers is merely exemplary in nature, and is in no way intended to limit the invention or its applications or uses. 
       FIG. 1  is an exploded perspective view of a WSA circuit  10  including a wafer portion  12  fabricated on a substrate wafer  14  and a cover portion  16  fabricated on a cover wafer  18 . As is well understood by those skilled in the art, during wafer level fabrication, the various layers are formed on the substrate wafer  14  and the various layers are fabricated on the cover wafer  18  where many circuits to be hermetically sealed within a package are simultaneously fabricated on the wafers  14  and  18 . The wafers  14  and  18  with the several circuits are positioned relative to each other and a sealing step is performed where sealing layers of a sealing ring are sealed together so that the circuit  10  is provided within a sealed cavity between the substrate wafer  14  and the cover wafer  18 . A dicing process is then performed to separate the individual packages so that each separate circuit is separated from the overall substrate wafer  14  and the cover wafer  18  as individual packages. Only one of the packages is shown in  FIG. 1 . 
     The wafer portion  12  includes a plurality of metal interconnect layers fabricated on the substrate wafer  14 , as will be discussed in detail below. These layers include a first metal interconnect layer  20  deposited on the substrate wafer  14 , a second metal interconnect layer  22  deposited on the first metal layer  20 , a first BCB layer  24  deposited on the second metal layer  22 , a third metal interconnect layer  26  deposited on the first BCB layer  24 , a second BCB layer  28  deposited on the third metal layer  26 , a fourth metal interconnect layer  30  deposited on the second BCB layer  28 , and an inter-cavity interconnect (ICIC) layer  32  deposited on the fourth metal layer  30 . The BCB layers  24  and  28  are not shown within the sealing ring area so that other layers and elements can be seen. The cover wafer portion  16  includes the same layers deposited in the same manner in the same order. This illustration only shows signal traces and other metalized areas, such as shields, that may be necessary for a particular circuit to provide the various interconnects. The actual device components, such as MMIC devices, are not shown and would likely be on the layer directly on the wafer  14  or  18  either adjacent to or within the first metal layer  20 . 
       FIG. 2  is a blown-up part of the wafer portion  12 , and shows that the fourth metal layer  30  includes a plurality of RF signal lines  40 , the third metal layer  26  includes a plurality of RF signal lines  42 , the second metal layer  22  includes a plurality of RF signal lines  44  and the first metal layer  20  includes metal contacts  46 . The BCB layers  24  and  28  have been removed from this view for clarity purposes. The various RF lines are electrically coupled through the BCB layers  24  and  28  by metal vias. Particularly, vias  50  are shown formed through the second BCB layer  28  and vias  52  are shown through the first BCB layer  24 . The second metal layer  22  also includes RF metal shields  48 . When the cover wafer portion  16  is formed to the substrate wafer portion  12 , the ICIC layers  32  are heated so that they seal together so that a cavity within the WSA circuit is hermitically sealed. The combination of the various metal layers, BCB layers and ICIC layers form a sealing ring at their outer edges. 
     As discussed above, the BCB layers  24  and  28  are not hermetic, and therefore a sealing area needs to be provided at an outer edge of the BCB layers  24  and  28  to maintain the hermetic seal.  FIG. 3  is a cut-away, perspective, outside view of the substrate wafer portion  12  showing the various layers discussed above. In this view, the BCB layers  24  and  28  are again not specifically shown so that vias discussed in detail below can be seen.  FIG. 3  shows an outside trench via  60  that extends through the BCB layer  24  and is operable to provide a sealing wall that helps provide a hermitic seal at the sealing ring. Likewise,  FIG. 3  shows an outside trench via  62  through the BCB layer  28  that also helps provide the hermetic ring seal at the sealing ring. As will be understood by those skilled in the art, the trench vias  60  and  62  are formed through the BCB layers  24  and  28  where the BCB layers  24  and  28  are etched to define a trench in which the metal that forms the trench vias  60  and  62  is deposited. Therefore, a portion of the BCB layers  24  and  28  would be outside of the trench vias  60  and  62 , respectively, where if those layers  24  and  28  were not removed from the view shown in  FIG. 3 , the trench vias  60  and  62  would not be seen. 
     An inside trench via  64  (see  FIG. 5 ) is provided adjacent to and spaced from the outside trench via  60  where a portion of the BCB layer  24  would be provided therebetween. Likewise, an inside trench via (not shown) is provided adjacent to and spaced from the outside trench via  62 , where a portion of the BCB layer  28  would be provided between these vias. In this embodiment, there are two trench vias formed through each of the BCB layers  24  and  28  that provide the hermitic seal at these layers. This is by way of a non-limiting example in that any suitable number of trench vias can be included to provide the desired hermetic seal, which may depend on the particular material being used in the trench vias, the width of the trench vias, etc. 
       FIG. 4  is a cut-away, perspective, inside view of the substrate wafer portion  12 . As discussed above, the BCB material tends to shrink as a result of its relatively high tensile strength when the trench vias are formed, which may cause circuit misalignment at other locations in the circuit  10 . In order to overcome this problem, the present invention proposes providing a checkerboard pattern of vias  68  adjacent to the inside via  64  where the checkerboard pattern of vias  68  includes a plurality of post vias  70  formed in rows, as shown. The post vias  70  are formed in a periodic pattern through the BCB layer  24  so that they act as anchoring points at the sealing ring of the WSA circuit  10  to prevent the BCB layer  24  from shrinking when the trench vias  60  and  64  are formed. The post vias  70  can have any suitable diameter and be spaced apart in any suitable spacing pattern to provide this desired result. Likewise, a checkerboard pattern of vias  72  is provided in the BCB layer  28  that includes post vias  74  for this purpose. 
       FIG. 5  illustrates a portion of the substrate wafer portion  12  during the fabrication of the WSA circuit  10 . The first metal layer  20  and the second metal layer  22  have been deposited and patterned, and the BCB layer  24 , although not specifically shown again for clarity purposes, has been patterned and etched to provide the openings where the trench vias  60  and  64  will be deposited and the post vias  70  for the checker-board pattern of vias  68  will be deposited along the sealing ring. The metal that forms the trench vias  60  and  64  is actually deposited within the openings etched in the BCB layer  24  during the metal deposition process for the third metal layer  26 . The trench vias and the checkerboard pattern of vias  72  formed in the BCB layer  28  are formed in the same manner where the deposition of the fourth metal layer  30  provides the metal that actually forms the trench vias and the checkerboard pattern of vias  72  in the BCB layer  28 . 
     In this non-limiting embodiment, corner areas  76  of the sealing ring include an extended seal area where more of the post vias  70  are provided. Particularly, along the edge of the sealing ring, four rows of the post vias  70  are provided, whereas up to eight rows of the post vias  70  are formed in the corner area  76 . 
     The foregoing discussion discloses and describes merely exemplary embodiments. One skilled in the art will readily recognize from such discussion, and from the accompanying drawings and claims, that various changes, modifications and variations can be made therein without departing from the spirit and scope of the disclosure as defined in the following claims.