Abstract:
A semiconductor substrate includes a wafer including an element area and a non-element area delineating the element area, a first layered structure situated in the element area, a first insulating film covering the first layered structure, and exhibiting a first etching rate with respect to an etching recipe, a second insulating film covering the first layered structure covered by the first insulating film in the element area, and exhibiting a second etching rate with respect to the etching recipe, the second etching rate being greater than the first etching rate, and a second layered structure situated in the non-element area, wherein the second layered structure includes at least a portion of the first layered structure.

Description:
This application is a divisional of application Ser. No. 11/507,536, filed on Aug. 22, 2006, which is a divisional of application Ser. No. 10/914,332, filed on Aug. 10, 2004, now U.S. Pat. No. 7,115,994 issued Oct. 3, 2006, which is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2004-080770, filed on Mar. 19, 2004, the entire contents of which are incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention generally relates to a semiconductor device, and more particularly to a semiconductor substrate, a semiconductor device having a ferroelectric film and method for fabricating the semiconductor device. 
     2. Description of the Related Art 
     A semiconductor memory device such as DRAM and SRAM is widely used as a high speed main memory device in an information processing devices such as a computer. However, since this memory device is a volatile memory device, the information stored therein will be lost once the power is turned off. Meanwhile, a non-volatile magnetic disk device is used as a large size auxiliary memory device for storing programs and data. 
     The magnetic disk device has problems such as, having a large size, being mechanically vulnerable, consuming a large amount of electricity, and having a slow access speed when reading/writing information. In recent years, as another non-volatile auxiliary memory device, an EEPROM or a flash memory, which stores information by applying voltage to a floating gate electrode, is widely used. The flash memory is particularly expected to be used as a large capacity memory device matching to the magnetic disk device since the flash memory has a similar cell structure that allows formation with high integrated density. 
     However, since information is written by applying hot electron to a floating gate electrode via a tunnel insulating film, the EEPROM or flash memory has problems such as requiring time for writing information and deteriorating the tunnel insulating film from repetitive writing/erasing of information. Such deteriorated tunnel insulating film causes writing and erasing operation to become unsteady. 
     As another memory device, a ferroelectric memory device (hereinafter referred to as “FeRAM”), which stores information by intrinsic polarization of a ferroelectric film, is proposed. Similar to the DRAM, the FeRAM has each memory cell transistor of the FeRam structured as a single MOSFET, in which the dielectrics in the memory cell capacitor is replaced with ferroelectric material such as PZT (Pb (Zr, Ti) O 3 ), PLZT (Pb (Zr, Ti, La)O 3 ), SBT (SrBi 2 Ta 2 O 3 ), or SBTN (SrBi2 (Ta, Nb)2O3). Thus structured, integration of high integrated density can be obtained. Since the FeRAM controls intrinsic polarization of a ferroelectric capacitor by impressing of electric field, writing speed is no less than 1000 times faster than that of the EEPROM or the flash memory which write information by applying hot electron, and also reduces electric power consumption to approximately 1/10. In addition, since the FeRAM requires no tunnel oxide film, the FeRAM can attain a longer longevity, and perform re-writing operations one hundred thousand times more than the flash memory. 
       FIG. 1  shows a conventional FeRAM  20 . 
     In  FIG. 1 , the FeRAM  20  is formed on a P-type or N-type Si substrate  21 , in which the Si substrate  21  is defined by a field insulating film  22  and includes a P-type well  21 A and an N-type well  21 B. A gate electrode  24 A, having a polycide structure, is formed above the P-type well  21 A via a gate insulating film  23 A. Further, a gate electrode  24 B, also having a polycide structure, is formed above the N-type well  21 B via a gate insulating film  23 B. In the P-type well  21 A, N-type diffusion areas  21   a ,  21   b  are formed on both sides of the gate electrode  24 A. In the N-type well  21 B, P-type diffusion areas  21   c ,  21   d  are formed on both sides of the gate electrode  24 B. Outside the active area, the gate electrode  24 A extends over a field oxide film (element separation film)  22 , and forms a part of an FeRAm word line (WL). 
     Each of the gate electrodes  24 A,  24 B has a side wall insulating film. Above the Si substrate  21 , an SiON cover film  25  is formed in a manner covering the field insulating film  22 , in which the SiON cover film  25  is formed into a thickness of approximately 200 nm by a CVD method. 
     A SiO 2  layer-interposed insulating film  26  is formed in a manner covering the cover film  25 , in which the SiO 2  layer-interposed insulating film  26  is formed into a thickness of approximately 1 μm by a CVD method employing TEOS gas. The surface of the layer-interposed insulating film  26  planarized by a CMP method. 
     A ferroelectric capacitor is formed above the planarized layer-interposed insulating film  26 , in which the ferroelectric capacitor has a lower electrode  27 , a ferroelectric capacitor insulating film  28 , and an upper electrode  29  orderly stacked above each other. The lower electrode  27  is formed of a Ti film with a thickness of 10-30 nm (more preferably, approximately 20 nm) and a Pt film with a thickness of 100-300 nm (more preferably, approximately 175 nm). The ferroelectric capacitor insulating film  28  is a film of PZT ((Pb (Zr, Ti) O 3 ) or PZLT ((Pb, La) (Zr, Ti) O 3 ) with a thickness of 100-300 nm (more preferably, approximately 240 nm). The upper electrode  29 , disposed above the ferroelectric capacitor insulating film  28 , is a film of IrOx with a thickness of 100-300 nm (more preferably, 200 nm). Further, the Ti film and the Pt film are formed, typically, by sputtering. The ferroelectric capacitor insulating film  28 , typically after sputtering, is crystallized by rapid thermal processing in a oxygen atmosphere of 725° C. for 20 seconds. It is preferable to add Ca and Sr to the ferroelectric capacitor insulating film  28 . Further, the ferroelectric capacitor insulating film  28  can not only be formed by a sputtering method, but alternatively formed by a spin-on method, a sol-gel method, a MOD (metal organic deposition) method, or a MOCVD method. As alternatives for using a PZT film or a PLZT film as the ferroelectric capacitor insulating film  28 , an SBT (SrBi 2  (Ta, Nb) 2  O 9 ) film, or a BTO (Bi 4 Ti 2 O 12 ) film may, for example, be used. Furthermore, by using a high dielectric film (e.g. a BST ((Ba, Sr)TiO 3 ) film, or a STO (SrTiO3) film) as an alternative for the ferroelectric capacitor insulating film  28 , a DRAM can be formed. Further, the IrOx film of the upper electrode  29  is typically formed by sputtering. A Pt film or an SRO (SrRuO 3 ) film may be used as alternatives for the IrOx film. 
     In a case where the ferroelectric capacitor is exposed to a reducing atmosphere, particularly to hydrogen, during a semiconductor process, the ferroelectric capacitor insulating film  28  is easily deoxidized, thereby resulting to severe deterioration of electric property. Therefore, the ferroelectric capacitor insulating film  28  is covered by an encapsulation layer  330 A formed of Al 2 O 3 , in which the encapsulation layer  330 A is formed with a thickness of approximately 50 nm by employing a sputtering method. Further, the encapsulation layer  330 A is covered by another encapsulation layer  330  also formed of Al 2 O 3 , in which the other encapsulation layer  330  is formed with a thickness of approximately 20 nm. The other encapsulation layer  330  serves as a barrier layer for preventing hydrogen from entering. 
     An SiO2 layer-interposed insulating film  30  is formed on the encapsulation layer  330  by a CVD method (more preferably, a Plasma CVD (P-CVD) method) using, for example, SiH 4 , a polysilane compound such as Si 2 F 6 , Si 3 F 8 , Si 2 F 3 Cl, SiF 4 , or TEOS, in which the SiO2 layer-interposed insulating film  30  is formed above the upper electrode  29  with a thickness of approximately 400 nm. Contact holes  30 A,  30 B are formed in the layer-interposed insulating film  30  for exposing the upper and lower electrodes  29 ,  27 , respectively. Further, contact holes  30 C,  30 D,  30 E, and  30 F are disposed in the layer-interposed insulating film  26  for exposing the diffusion areas  21   a ,  21   b ,  21   c , and  21   d , respectively. A contact hole  30 G is formed in the layer-interposed insulating film  30  for exposing the word line patter WL formed on the element separation film  22 . 
     In the conventional FeRAM  20  shown in  FIG. 1 , contacting films  31 A and  31 B, formed of conductive nitride material (e.g. TiN) with a thickness of approximately 50 nm, are respectively formed in the contact holes  30 A and  30 B in a manner directly contacting the inner wall surfaces of the contact holes  30 A and  30 B, or directly contacting the surfaces of the exposed upper or lower electrodes  29 ,  27 . By applying a CVD method using a mixed gas of WF 6 , Ar, and H 2 , a conductive plug (W plug)  32 A, formed of W, is formed on the contacting film  31 A of the contact hole  30 A, and a conductive plug (W plug)  32 B, also formed of W, is formed on the contacting film  31 B of the contact hole  30 B. 
     In a likewise manner, contacting films  31 C- 31 G are formed at the inner wall surfaces of the contact holes  30 C- 30 G, and W plugs  32 C- 32 G are formed on the contacting films  31 C- 31 G. 
     Further, wiring patterns  33 A- 33 F, formed of A1, are disposed on the layer-interposed insulating film  30  in correspondence with the W plugs  32 A- 32 G. The wiring patterns  33 A- 33 F are covered by a further layer-interposed insulating film  34  formed of SiO 2 , in which the layer-interposed insulating film  34  is formed by a P-CVD method using, for example, SiH 4 , a polysilane compound such as Si 2 F 6 , Si 3 F 8 , Si 2 F 3 Cl, SiF 4 , or TEOS, similar as the layer-interposed insulating film  30 . 
     Further, a protective film  35 , formed of SiO2, is formed on the layer-interposed insulating film  34  with a thickness of 100 nm or more by using a P-CVD method. The protective film  35  serves to cover exposed slits (cavities) formed after a planarizing process (CMP) executed after the formation of the layer-interposed insulating film  34 . 
     Further, contact holes  35 A,  35 B are formed in a manner piercing the protective film  35  and the layer-interposed insulating film  34  for exposing the wiring patterns  33 A and  33 F, respectively. Further, W plugs  37 A,  37 B are formed on the inners wall surface of the contact holes  35 A,  35 B via contacting films (TiN contacting layers)  36 A,  36 B. 
     Further, wiring patterns  38 A,  38 B, formed of A1 or A1 alloy, are formed on the protective film  35  in a manner contacting the W plugs  37 A,  37 B. In forming the wiring patterns  38 A,  38 B, the contacting films  36 A,  36 B are disposed extending between the wiring patterns  38 A,  38 B and the protective film  35  in a manner covering the inner wall surfaces of the contact holes  35 A,  35 B. 
     Further, a layer-interposed insulating film  39 , formed in a manner similar to that of layer-interposed insulating film  30  and  34 , is disposed covering the wiring patterns  38 A,  38 B. Further, a protective film  40 , similar to the protective film  35 , is formed on the layer-interposed insulating film  39 . Then, wiring patterns  41 A- 41 E including a bit line (BL) pattern is formed on the protective film  40 . 
     The FeRAM  20  shown in  FIG. 1  is fabricated according to the steps shown in  FIGS. 2A-2F . 
     In the step shown in  FIG. 2A , the Si substrate  21  is provided with diffusion areas  21   a - 21   d  and is mounted with polycide gate electrodes  24   a ,  24 B. The SiO2 layer-interposed insulating film  26  is formed with a thickness of approximately 1 μm on the Si substrate  21  in a manner covering the polycide gate electrodes  24 A,  24 B by using the P-CVD method with TEOS. Further, the SiO2 layer-interposed insulating film  26  is planarized with the CMP method. Then, on the planarized layer-interposed insulating film  26 , the Ti film and the Pt film are orderly deposited with a thickness of 20 nm and 175 nm, respectively. Then, on the deposited film, the PLZT film (preferably added with Ca and Sr) is formed with a thickness of 240 nm by sputtering. Thereby, the ferroelectric film is obtained. The PLZT film (ferroelectric film) is crystallized by being subjected to rapid thermal processing in an oxygen atmosphere of 725° C. for 20 seconds at a heating rate of 125° C./second. After the ferroelectric film is crystallized, the IrOx film with a thickness of 200 nm is formed on the ferroelectric film by the sputtering method. 
     Then, the upper electrode  29  is formed by patterning the IrOx film with resist (resist process). After the resist process, the ferroelectric film is thermally processed again in an oxygen atmosphere of 650° C. for 60 minutes, to thereby compensate for the deficit of oxygen in the ferroelectric film during the processes of sputtering and patterning the IrOx film. 
     Then, a resist pattern is formed in a manner covering the upper electrodes. Using the resist pattern as a mask, the ferroelectric film is patterned, to thereby obtain the ferroelectric capacitor insulating film  28 . After the ferroelectric capacitor insulating film  28  is formed, the ferroelectric film is thermally processed in a nitrogen atmosphere, so as to dehydrate the inside of the layer-interposed insulating film  26 . 
     Further, the Al 2 O 3  film is sputtered to the Pt/Ti layer in normal temperature in a manner covering the ferroelectric capacitor insulating film  28  and the upper electrode  29 . Thereby, the encapsulation layer  330 A is obtained for protecting the ferroelectric capacitor insulating film  28  from H2. After the encapsulation layer  330 A is formed, a thermal process is executed in an oxygen atmosphere of 550° C. for 60 minutes so that the film quality of the encapsulation layer  330 A can be enhanced. 
     Then, a resist pattern is formed on the encapsulation layer  330 A. Using the resist pattern on the encapsulation layer  330 A as a mask, the Pt/Ti layer is patterned, to thereby obtain the lower electrode  27 . 
     Further, after the resist used for obtaining the lower electrode  27  is removed, and executing a thermal process of 350° C. for 30 minutes, the Al 2 O 3  film is sputtered on the layer-interposed insulating film  26 . Thereby, another encapsulation layer  330  (second encapsulation layer) is formed in a manner covering the encapsulation layer  330 A. 
     Further, a thermal process of 650° C. is executed for 30 minutes after the formation of the encapsulation layer  330  so that the damage created in the ferroelectric capacitor insulating film  28  can be relieved. Further, the layer-interposed insulating film  30 , having a thickness of approximately 1200 nm, is formed on the encapsulation layer  330  by a P-CVD method using, for example, SiH 4 , a polysilane compound such as Si 2 F 6 , Si 3 F 8 , Si 2 F 3 Cl, SiF 4 . Alternatively, the layer-interposed insulating film  30  may also be formed by using TEOS. A thermal excitation CVD method or a laser excitation CVD method may be employed as alternatives of the P-CVD method. Then, the layer-interposed insulating film  30  is polished and planarized by the CMP method until having a thickness of approximately 400 nm (measured from the surface of the upper electrode  29 ). 
     Next, in the step shown in  FIG. 2B , the layer-interposed insulating film  30  is dehydrated by using N 2  plasma or N 2 O plasma. Then, in a resist process using CHF3 and a mixed gas of CF4 and Ar, the contact holes  30 A and  30 B are formed in the layer-interposed insulating film  30  in a manner penetrating the encapsulation layers  330  and  330 A and allowing the upper electrode  29  and the lower electrode  27  to be exposed. Then, in this state, a thermal process is executed in an oxygen atmosphere at 60° C. for 60 minutes. This enables recovery in film quality of the ferroelectric capacitor insulating film  28  deteriorated during the formation of the contact holes  30 A and  30 B. 
     In the step shown in  FIG. 2C , resist pattern R having aperture portions corresponding to contact holes  30 C- 30 F is applied to the structure shown in  FIG. 2B . Using the resist pattern R as a mask, the layer-interposed insulating films  30  and  26  are patterned to form the contact holes  30 C- 30 F, thereby exposing the diffusion areas  21   a - 21   d . Since the formation of contact hole G (see  FIG. 1 ) is simple, a detail description thereof is omitted. 
     In the step shown in  FIG. 2D , the resist pattern R is removed, and a pre-treating process of Ar plasma etching is executed. Then, the TiN film  31  is sputtered to the layer-interposed insulating film  30  in a manner continuingly covering the inner wall surface and bottom surface of the contact hole  31 A and the inner wall surface and bottom surface of the contact hole  31 B. The TiN film is formed with a thickness of approximately 50 nm. The TiN film contacts the exposed part of the upper electrode  29  at the bottom surface of the contact hole  30 A, and contacts the exposed part of the lower electrode  27  at the bottom surface of the contact hole  30 B. Further, the TiN film also contacts the exposed parts of the diffusion areas  21   a - 21   d  at the contact holes  30 C- 30 F. 
     In the step shown in  FIG. 2E , the W layer  32  is deposited on the TiN film  31  by a CVD method using WF 6 , Ar, and H 2  in a manner filling the contact holes  30 C- 30 F. 
     Although H 2  is used in the CVD method in the step shown in  FIG. 2E , the H2 will not reach the ferroelectric film  28  since the ferroelectric capacitor containing the ferroelectric film  28  is overlappingly covered by the encapsulation layers  330 ,  330 A and the TiN film  31 . Therefore, the property of the ferroelectric capacitor can be prevented from being deteriorated by deoxidization. 
     In the step shown in  FIG. 2F , the W layer  32  on the layer-interposed insulating film  30  is polished/removed by a CMP method. As a result, W plugs  32 A- 32 F, formed from the portions of the W layer remaining in the contact holes  30 A- 30 F, are obtained. In addition, as a result of the use of the CMP method, the TiN film on the layer-interposed insulating film  30  is planarized, to thereby obtain TiN patterns  31 A- 31 F corresponding to the contact holes  30 A- 30 F. 
     Among the W plugs  32 A- 32 F, although the W plug  32 A, formed of IrOx, contacts the upper electrode  29  via the TiN pattern  31 A, the TiN pattern  31 A does not react to conductive oxides such as IrOx. Therefore, no increase of contact resistance will occur. 
     Then, by performing a typical procedure of forming a multi-layer wiring structure to the structure shown in  FIG. 2F , the FeRAM shown in  FIG. 1  is obtained. 
     With the above-described conventional FeRAM  20  using the Al 2 O 3  encapsulation layers  330 ,  330 A as hydrogen barriers, the thickness of the encapsulation layers  330 ,  330 A are required to be increased for effectively preventing entry of hydrogen and maintaining the electric property of the ferroelectric capacitor in a case where the size of the ferroelectric capacitor is reduced in correspondence with size-reduction of the FeRAM  20 . Accordingly, in recent FeRAMs, the Al 2 O 3  encapsulation layer  330 A is provided with an increased thickness of, for example, 50 nm, and the Al 2 O 3  encapsulation layer  330  is provided with an increased thickness of, for example, 100 nm. 
     However, in using the FeRAM  20  having encapsulation layers  330 ,  330 A with increased thicknesses, corrosion or peeling may occur at an alignment mark situated at a scribe line. Furthermore, alignment becomes difficult, particularly, during the formation of the contact holes  30 A,  30 B in the step shown in  FIG. 2B , and particles are created, thereby resulting to a considerable yield loss in fabricating the FeRAM. 
     SUMMARY OF THE INVENTION 
     It is a general object of the present invention to provide a semiconductor substrate and method for fabricating a semiconductor device that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art. 
     Features and advantages of the present invention will be set forth in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a semiconductor substrate and method for fabricating a semiconductor device particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention. 
     To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a semiconductor substrate including: a wafer including an element area and a non-element area delineating the element area; a first layered structure situated in the element area; a first insulating film covering the first layered structure, and exhibiting a first etching rate with respect to an etching recipe; a second insulating film covering the first layered structure covered by the first insulating film in the element area, and exhibiting a second etching rate with respect to the etching recipe, the second etching rate being greater than the first etching rate; and a second layered structure situated in the non-element area; wherein the second layered structure includes at least a portion of the first layered structure. 
     In the semiconductor substrate according to an embodiment of the present invention, the second insulating film may include a first aperture portion penetrating the first insulating film in a manner exposing the first layered structure, a first conductive pattern disposed in the first aperture portion, a second aperture portion exposing the second layered structure, and a second conductive pattern disposed in the second aperture portion. 
     In the semiconductor substrate according to an embodiment of the present invention, the second layered structure may be in contact with the second insulating film. 
     In the semiconductor substrate according to an embodiment of the present invention, the second layered structure may have a same layer structure as the first layered structure. 
     In the semiconductor substrate according to an embodiment of the present invention, the second layered structure may be formed as a first alignment mark, wherein the second layered structure may have a second alignment mark formed in correspondence with the first alignment mark. 
     In the semiconductor substrate according to an embodiment of the present invention, the first insulating film may be a film for preventing hydrogen from entering the etching recipe. 
     In the semiconductor substrate according to an embodiment of the present invention, the first insulating film may contain Al 2 O 3 . 
     In the semiconductor substrate according to an embodiment of the present invention, the first layered structure may be a capacitor structure including a lower electrode, a ferroelectric film situated on the lower electrode, and an upper electrode situated on the upper electrode. 
     In the semiconductor substrate according to an embodiment of the present invention, the second layered structure may include a first layer corresponding to the lower electrode, the first layer being formed with a material same as that of the lower electrode and a thickness same as that of the lower electrode, a second layer corresponding to the ferroelectric film, the second layer being situated on the first layer, and being formed with a material same as that of the ferroelectric film and a thickness same as that of the ferroelectric film, and a third layer corresponding to the upper electrode, the third layer being situated on the second layer, and being formed with a material same as that of the upper electrode and a thickness same as that of the upper electrode. 
     In the semiconductor substrate according to an embodiment of the present invention, the non-element area may be a scribe line formed on the wafer for delineating the element area. 
     Furthermore, the present invention provides a semiconductor device including a wafer including an element area and a non-element area delineating the element area; a first layered structure situated in the element area; a first insulating film covering the first layered structure, and exhibiting a first etching rate with respect to an etching recipe; a second insulating film covering the first layered structure covered by the first insulating film in the element area, and exhibiting a second etching rate with respect to the etching recipe, the second etching rate being greater than the first etching rate; and a second layered structure situated in the non-element area; wherein the second layered structure includes at least a portion of the first layered structure. 
     Furthermore, the present invention provides a method of fabricating a semiconductor device including the steps of: forming a first layered structure on a base layer in an element area of a wafer, the element area being delineated by a non-element area; covering the first layered structure with a first insulating film that exhibits a first etching rate with respect to an etching recipe; covering the first layered structure, being covered by the first insulating film, with a second insulating film that exhibits a second etching rate with respect to the etching recipe, the second etching rate being greater than the first etching rate; forming a first aperture portion in the second insulating film in a manner exposing the first layered structure; forming a conductive plug in the first aperture portion; forming a second layered structure in the non-element area simultaneously with the step of forming the first layered structure, the second layered structure including at least a portion of the first layered structure; forming a second aperture portion simultaneously with the step of forming the first aperture portion in a manner exposing the second layered structure; and forming a conductive pattern simultaneously with the step of forming the conductive plug in the second aperture portion. 
     In the method of fabricating a semiconductor device according to an embodiment of the present invention, the method may further include a step of determining an alignment between the second layered structure and the conductive pattern. 
     In the method of fabricating a semiconductor device according to an embodiment of the present invention, the first layered structure may include a ferroelectric film. 
     In the method of fabricating a semiconductor device according to an embodiment of the present invention, the first insulating film may be a film for preventing hydrogen from entering the etching recipe. 
     In the method of fabricating a semiconductor device according to an embodiment of the present invention, the first insulating film may contain Al 2 O 3 . 
     In the method of fabricating a semiconductor device according to an embodiment of the present invention, the non-element area may be a scribe line formed on the wafer, wherein the wafer is diced along the scribe line. 
     Accordingly, with the present invention, even when a considerable amount of time is used in etching the first insulating film for forming the first aperture portion in the element area, the second layered structure prevents the second aperture portion in the non-element area from being formed too deep to an extent reaching the semiconductor substrate (layer). This may be applied to a case where, for example, the first conductive pattern is formed in the second insulating film in a manner penetrating the first insulating film and contacting the first layered structure, at the same time of forming the second conductive pattern in the non-element area as a mark pattern. Therefore, even when a conductive pattern is formed in the first and second aperture portions by a CVD method using, WF 6  material gas, for example, the gas would not contact the semiconductor substrate. Accordingly, corrosive gas generated by material gas contacting to the semiconductor substrate can be prevented. As a result, a clear-defined (satisfactorily-shaped) conductive pattern can be formed in the second aperture portion. Furthermore, since generation of corrosive gas can be prevented, generation of undesired particles can be effectively restrained, to thereby improve fabrication yield of the semiconductor device. 
     With the present invention, the second layered structure and the second conductive pattern in the non-element area can be utilized as alignment patterns, to thereby obtain a precise alignment with respect to the first layered structure and the first conductive pattern. 
     With the present invention, the first layered structure is restricted by the first insulating film by forming the second layered structure in a manner contacting the second insulating film. As a result, etching process time can be reduced for forming, for example, via holes or contact holes reaching to levels below the first layered structure owing to the presence of the first insulating film. 
     With the present invention, increase in the steps (processes) for fabrication can be prevented since the second layered structure is formed with a same layer structure as the first layered structure. 
     With the present invention, alignment with respect to the first layered structure and the first conductive pattern can be positively detected (determined). Furthermore, the second layered structure can be utilized as a first alignment mark. 
     With the present invention, the first insulating film can prevent hydrogen from entering. Furthermore, by employing a film containing Al 2 O 3  as the first insulating film, the first layered structure can be protected from hydrogen and a deoxidizing atmosphere containing hydrogen. 
     With the present invention, a ferroelectric memory can be formed in the element area. With the present invention no additional process in fabrication, since the first and second layered structures are formed having corresponding layers of same material and corresponding layers with same thickness. 
     With the present invention, the element area can be efficiently used by employing the scribe line as the non-element area. 
     Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic drawing showing a structure of a conventional FeRAM; 
         FIGS. 2A-2F  are schematic diagrams showing the steps of fabricating the FeRAM shown in  FIG. 1 ; 
         FIGS. 3A-3F  are schematic diagrams for explaining the principle of the present invention; 
         FIGS. 4A-4B  are schematic diagrams showing a structure of a semiconductor wafer according to a first embodiment of the present invention; 
         FIG. 5  is a schematic diagram showing a structure of a FeRAM formed in the semiconductor wafer shown in  FIGS. 4A-4B ; 
         FIGS. 6A-6I  are schematic diagrams showing the steps of fabricating the semiconductor wafer including the FeRAM shown in  FIG. 5 ; 
         FIG. 7  is a schematic diagram showing a structure of a wafer including an FeRAM according to a second embodiment of the present invention; and 
         FIG. 8  is a schematic diagram showing a structure of an FeRAM according to a third embodiment of the present invention. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In the following, embodiments of the present invention regarding a semiconductor substrate and method for fabricating a semiconductor device will be described with reference to the accompanying drawings. 
     [Principle] 
       FIGS. 3A-3F  are explanatory drawings for explaining a mechanism of corrosion or peeling occurring at an alignment mark of the FeRAM  20  shown in  FIG. 1 . In  FIGS. 3A-3F , like components are denoted by like numerals as of those shown in  FIGS. 1  and  2 A- 2 F and will not be further explained. 
       FIGS. 3A-3F  are drawings showing the steps of  FIGS. 2A and 2B  in more detail. 
     In  FIG. 3A , the FeRAM  20  shown in  FIG. 1  is formed at a cell area (element area)  21 C of the substrate  21 . The cell area  21 C is defined by a scribe area  21 D. 
     follows: 
     In the step shown in  FIG. 3A , a conductive film  270  corresponding to the lower electrode  27 , a ferroelectric film corresponding to the ferroelectric capacitor insulating film  28 , and another conductive film corresponding to the upper electrode  29  are orderly formed on the layer-interposed insulating film  26  in the cell area  21 C. By patterning the films with resist, the ferroelectric capacitor insulating film  28  and the upper electrode  29  is formed on the conductive film  270 . Furthermore, the Al 2 O 3  pattern (encapsulation layer)  330 A is formed on the conductive film  270  in a manner covering the ferroelectric capacitor insulating film  28 , the upper electrode, and an area of the conductive film at which the lower electrode  27  is to be formed. 
     In the step shown in  FIG. 3B , the conductive film  270  is patterned. As a result, the lower electrode  27  is formed in the cell area  21 C, and an alignment mark pattern  27 M is formed in the scribe area  21 D. 
     In the step shown in  FIG. 3C , the Al 2 O 3  film  330  is uniformly formed on the structure shown in  FIG. 3B . In the step shown in  FIG. 3C , the Al 2 O 3  film  330  covers the alignment pattern  27 M in the scribe area  21 D. 
     As shown in  FIG. 3C , the Al 2 O 3  film  330  covers not only the alignment mark pattern  27 , but the entire layer-interposed insulating film  26  of the substrate  21 . The existence of the Al 2 O 3  film  330  covering the entire layer-interposed insulating film  26 , for example, reduces process efficiency in the formation of contact holes  30 C- 30 F deeply penetrated to the substrate surface as shown in  FIG. 2C . Therefore, in the step shown in  FIG. 3D , the Al 2 O 3  film  330  is patterned, to thereby allow the Al 2 O 3  film  330  to remain only on the lower electrode  27  of the ferroelectric capacitor. In addition, the alignment mark pattern  27 M in the scribe area  21 D is exposed (see  FIG. 3D ) as a result of the patterning. 
     In the step shown in  FIG. 3D , the layer-interposed insulating film  30  is formed on the layer-interposed insulating film  26  in a manner covering the ferroelectric capacitor in the cell area  21 C and the alignment mark pattern  27 M in the scribe area  21 D. 
     In the step shown in  FIG. 3E , the contact holes  30 A and  30 B are formed in the layer-interposed insulating film  30  based on the alignment mark pattern  27 M, in a manner exposing the upper electrode  29  and the lower electrode  27 , respectively. Further, in the scribe area  21 D, aperture portions  30   m  are formed according to another alignment mark pattern (sub-pattern) corresponding to the alignment mark pattern  27 M (main pattern). In  FIG. 3E , the barrier film is not shown for the purpose of simplification. 
     In the step shown in  FIG. 3E , the etching process for forming the contact holes  30 A,  30 B require a considerable amount of time since the apertures of the contact holes  30 A,  30 B are required to penetrate the Al 2 O 3  films  330  and  330 A. Particularly with recent FeRAMs, in which the ferroelectric capacitor is size-reduced in correspondence with size-reduction of the element, the Al 2 O 3  films  330  and  330 A are formed with increased thicknesses due to a greater need to prevent hydrogen from entering (for example, the Al 2 O 3  film  330  formed with a thickness of 100 nm, Al 2 O 3  film  330 A formed with a thickness of 50 nm). As a result, an extensive amount of time is required in the step shown in  FIG. 6E . 
     However, as the time in performing the step shown in  FIG. 6E  becomes longer, the aperture portion  30   m  in the scribe area  21 D becomes remarkably deeper, thereby penetrating the layer-interposed insulating film  26 , and further reaching the silicon substrate  21 . It is to be noted that there is no Al 2 O 3  film disposed beneath the aperture portion  30   m  in the scribe area  21 D. 
     Accordingly, in a case where the aperture portion  30   m  reaches the silicon substrate  21  as shown in  FIG. 3F  (corresponding to  FIG. 2F ), a reaction generated between a portion of the silicon substrate  21  exposed by the aperture portion  30  and a gas containing F such as WF 6  used in the CVD process, in which W is filled in the contact holes  30 A,  30 B, and the aperture portion  30  for forming the contact plugs  32 A,  32 B, and the alignment mark (sub-mark)  32 M. For example, a reaction of
 
WF 6 +Si→W+SiF 6  
 
creates a corrosive reactive gas of SiF 6 .
 
     The corrosive reactive gas causes irregularity at the side wall surface of the mark pattern  32 M, thereby creating gaps and peeled portions. Furthermore, the alignment precision, which is based on the distance δ between the main mark pattern  27 M and the sub-mark pattern  32 M, is reduced. In addition, alignment precision for alignment processes performed afterwards may also be adversely affected. Furthermore, particles may scatter onto the substrate surface, thereby resulting to yield loss in fabricating the FeRAM. 
     First Embodiment 
       FIGS. 4A and 4B  show a semiconductor wafer  401  formed with an FeRAM  400  according to a first embodiment of the present invention, in which the semiconductor wafer  401  formed with the FeRAM  400  is able to solve the above-described problems.  FIG. 4A  is an overall view of the semiconductor wafer  401 , and  FIG. 4B  is a partial enlarged plane view of the semiconductor wafer  401  shown in  FIG. 4A . 
     With reference to  FIGS. 4A and 4B , numerous scribe areas  401 S are disposed on the semiconductor wafer  401  in a grid-like manner. The scribe areas  401 S define element areas (cell areas)  401 A- 401 I arranged in a grid-like manner on the semiconductor wafer  401 . Further, alignment mark patterns  401 M are disposed on the scribe areas  401 S in the proximity of respective element areas  401 A- 401 I. Further, each element area  401 A- 401 I is formed with an FeRAM including a ferroelectric capacitor. 
       FIG. 5  is a cross-sectional view showing a structure of the FeRAM of the element area  401 A. 
     The FeRAM shown in  FIG. 5  has a structure similar to that of the FeRAM shown in  FIG. 1 . 
     In  FIG. 5 , the FeRAM  120  is formed on a P-type or N-type Si substrate  121 , in which the Si substrate  121  is defined by a field insulating film  122  and includes a P-type well  21 A and an N-type well  121 B. A gate electrode  124 A, having a polycide structure, is formed above the P-type well  121 A via a gate insulating film  123 A. Further, a gate electrode  124 B, also having a polycide structure, is formed above the N-type well  121 B via a gate insulating film  123 B. In the P-type well  121 A, N-type diffusion areas  121   a ,  121   b  are formed on both sides of the gate electrode  124 A. In the N-type well  121 B, P-type diffusion areas  121   c ,  121   d  are formed on both sides of the gate electrode  124 B. Outside the active area, the gate electrode  124 A extends over a field oxide film (element separation film)  122 , and forms a part of an FeRAM word line (WL). 
     Each of the gate electrodes  124 A,  124 B has a side wall insulating film. Above the Si substrate  121 , an SiON cover film  125  is formed in a manner covering the field insulating film  122 , in which the SiON cover film  125  is formed into a thickness of approximately 200 nm by a CVD method. 
     A SiO 2  layer-interposed insulating film  126  is formed in a manner covering the cover film  125 , in which the SiO 2  layer-interposed insulating film  126  is formed into a thickness of approximately 1 μm by a CVD method employing TEOS gas. The surface of the layer-interposed insulating film  126  planarized by a CMP method. 
     A ferroelectric capacitor is formed above the planarized layer-interposed insulating film  126 , in which the ferroelectric capacitor has a lower electrode  127 , a ferroelectric capacitor insulating film  128 , and an upper electrode  129  orderly stacked above each other. The lower electrode  127  is formed of a Ti film with a thickness of 10-30 nm (more preferably, approximately 20 nm) and a Pt film with a thickness of 100-300 nm (more preferably, approximately 175 nm). The ferroelectric capacitor insulating film  128  is a film of PZT ((Pb (Zr, Ti) O 3 ) or PZLT ((Pb, La) (Zr, Ti)O 3 ) with a thickness of 100-300 nm (more preferably, approximately 240 nm). The upper electrode  129 , disposed above the ferroelectric capacitor insulating film  128 , is a film of IrOx with a thickness of 100-300 nm (more preferably, 200 nm). Further, the Ti film and the Pt film are formed, typically, by sputtering. The ferroelectric capacitor insulating film  128 , typically after sputtering, is crystallized by rapid thermal processing in a oxygen atmosphere of 725° C. for 20 seconds. It is preferable to add Ca and Sr to the ferroelectric capacitor insulating film  128 . Further, the ferroelectric capacitor insulating film  128  can not only be formed by a sputtering method, but alternatively formed by a spin-on method, a sol-gel method, a MOD (metal organic deposition) method, or a MOCVD method. As alternatives for using a PZT film or a PLZT film as the ferroelectric capacitor insulating film  128 , an SBT (SrBi 2  (Ta, Nb) 2 O 9 ) film, or a BTO (Bi 4 Ti 2 O 12 ) film may, for example, be used. Furthermore, by using a high dielectric film (e.g. a BST ((Ba, Sr)TiO 3 ) film, or a STO (SrTiO 3 ) film) as an alternative for the ferroelectric capacitor insulating film  128 , a DRAM can be formed. Further, the IrOx film of the upper electrode  129  is typically formed by sputtering. A Pt film or an SRO (SrRuO 3 ) film may be used as alternatives for the IrOx film. 
     In a case where the ferroelectric capacitor is exposed to a reducing atmosphere, particularly to hydrogen, during a semiconductor process, the ferroelectric capacitor insulating film  128  is easily deoxidized, thereby resulting to severe deterioration of electric property. Therefore, the ferroelectric capacitor insulating film  128  is covered by an encapsulation layer  430 A formed of Al 2 O 3 , in which the encapsulation layer  430 A is formed with a thickness of approximately 50 nm by employing a sputtering method. Further, the encapsulation layer  430 A is covered by another encapsulation layer  430  also formed of Al 2 O 3 , in which the other encapsulation layer  430  is formed with a thickness of approximately 20 nm. The other encapsulation layer  430  serves as a barrier layer for preventing hydrogen from entering. 
     An SiO 2  layer-interposed insulating film  130  is formed on the encapsulation layer  430  by a CVD method (more preferably, a Plasma CVD (P-CVD) method) using, for example, SiH 4 , a polysilane compound such as Si 2 F 6 , Si 3 F 8 , Si 2 F 3 Cl, SiF 4 , or TEOS, in which the SiO 2  layer-interposed insulating film  130  is formed above the upper electrode  129  with a thickness of approximately 400 nm. Contact holes  130 A,  130 B are formed in the layer-interposed insulating film  130  for exposing the upper and lower electrodes  129 ,  127 , respectively. Further, contact holes  130 C,  130 D,  130 E, and  130 F are disposed in the layer-interposed insulating film  126  for exposing the diffusion areas  121   a ,  121   b ,  121   c , and  121   d , respectively. A contact hole  130 G is formed in the layer-interposed insulating film  130  for exposing the word line patter WL formed on the element separation film  122 . 
     In the conventional FeRAM  20  shown in  FIG. 1 , contacting films  131 A and  131 B, formed of conductive nitride material (e.g. TiN) with a thickness of approximately 50 nm, are respectively formed in the contact holes  130 A and  130 B in a manner directly contacting the inner wall surfaces of the contact holes  130 A and  130 B, or directly contacting the surfaces of the exposed upper or lower electrodes  129 ,  127 . By applying a CVD method using a mixed gas of WF 6 , Ar, and H 2 , a conductive plug (W plug)  132 A, formed of W, is formed on the contacting film  131 A of the contact hole  130 A, and a conductive plug (W plug)  132 B, also formed of W, is formed on the contacting film  131 B of the contact hole  130 B. 
     In a likewise manner, contacting films  131 C- 131 G are formed at the inner wall surfaces of the contact holes  130 C- 130 G, and W plugs  132 C- 132 G are formed on the contacting films  131 C- 131 G. 
     Further, wiring patterns  133 A- 133 F, formed of A1, are disposed on the layer-interposed insulating film  130  in correspondence with the W plugs  132 A- 132 G. The wiring patterns  133 A- 133 F are covered by a further layer-interposed insulating film  134  formed of SiO 2 , in which the layer-interposed insulating film  134  is formed by a P-CVD method using, for example, SiH 4 , a polysilane compound such as Si 2 F 6 , Si 3 F 8 , Si 2 F 3 Cl, SiF 4 , or TEOS, similar as the layer-interposed insulating film  130 . 
     Further, a protective film  135 , formed of SiO 2 , is formed on the layer-interposed insulating film  134  with a thickness of 100 nm or more by using a P-CVD method. The protective film  135  serves to cover exposed slits (cavities) formed after a planarizing process (CMP) executed after the formation of the layer-interposed insulating film  134 . 
     Further, contact holes  135 A,  135 B are formed in a manner piercing the protective film  135  and the layer-interposed insulating film  134  for exposing the wiring patterns  133 A and  133 F, respectively. Further, W plugs  137 A,  137 B are formed on the inners wall surface of the contact holes  135 A,  135 B via contacting films (TiN contacting layers)  136 A,  136 B. 
     Further, wiring patterns  138 A,  138 B, formed of A1 or A1 alloy, are formed on the protective film  135  in a manner contacting the W plugs  137 A,  137 B. In forming the wiring patterns  138 A,  138 B, the contacting films  136 A,  136 B are disposed extending between the wiring patterns  138 A,  138 B and the protective film  135  in a manner covering the inner wall surfaces of the contact holes  135 A,  135 B. 
     Further, a layer-interposed insulating film  139 , formed in a manner similar to that of layer-interposed insulating film  130  and  134 , is disposed covering the wiring patterns  138 A,  138 B. Further, a protective film  140 , similar to the protective film  135 , is formed on the layer-interposed insulating film  139 . Then, wiring patterns  141 A- 141 E including a bit line (BL) pattern is formed on the protective film  140 . 
     Since the fabrication process of the FeRAM  120  shown in  FIG. 5  is similar to that shown in  FIGS. 2A-2F , further description thereof is omitted. 
     Next, among the fabrication processes (steps) of the FeRAM  120 , a formation process of the ferroelectric capacitor and the Al2O3 films  430 ,  430 A covering the capacitor id described along with a formation process of an alignment mark of the scribe area(s)  401 S with reference to  FIGS. 6A-6F . 
     In the step shown in  FIG. 6A , the layer-interposed insulating film  126  is disposed on the silicon substrate  121  corresponding to the silicon wafer  401  shown in  FIG. 5 . The conductive layer  127 A for forming the lower electrode  127 , the ferroelectric film  128 A for forming the ferroelectric capacitor insulating film  128 , and the conductive layer  129 A for forming the upper electrode  129  is disposed on the layer-interposed insulating film  126  in a manner uniformly covering the element area  401 A and the scribe area  401 S. The ferroelectric capacitor insulating film  128  and the upper electrode  129  are formed on the conductive layer  127 A in the element area  401 A by patterning, in order, the conductive film  129 A and the ferroelectric film  128 A in the step shown in  FIG. 6B . 
     In the step shown in  FIG. 6B , the ferroelectric film  129 A in the scribe area  401 S is patterned to thereby obtain a conductive pattern  129 B simultaneously with the formation of the electrode  129 , in which the conductive pattern  129 B has a composition and a thickness that are the same as those of the upper electrode  129 . Further, by patterning the ferroelectric film  128 A in the scribe area  401 S, a ferroelectric pattern  128 B is formed below the conductive pattern  129 B simultaneously with the formation of the ferroelectric capacitor insulating film  128 . Further, the structure shown in  FIG. 6B  is thermally processed in an oxygen atmosphere for compensating a deficit of oxygen inducted in the ferroelectric capacitor insulating film  128 . In the step of  FIG. 6B , a same mask is used for patterning both the upper electrode  129  and the conductive pattern  129 B, and a same mask is used for patterning both the ferroelectric capacitor insulating film  128  and the ferroelectric pattern  128 B. 
     In the step shown in  FIG. 6C , an Al 2 O 3  film  430 N forming the encapsulation layer  430 A is formed, for example, with a thickness of 50 nm in a manner uniformly covering the element area  401 A and the scribe area  401 S. In the step shown in  FIG. 6D , the Al 2 O 3  film  430 N is patterned in a manner allowing Al 2 O 3  film  430 N to remain only in the area at which the ferroelectric capacitor is formed. Thereby, the encapsulation layer  430 A is formed. 
     In the step shown in  FIG. 6E , the lower electrode  127  is formed by patterning the conductive film  127 A. Accordingly, a ferroelectric capacitor FC including the lower electrode  127  is obtained in the element area  401 A. At the same time of the formation of the lower electrode  127 , a conductive pattern  127 B is formed in the scribe area  401 S. Accordingly, an alignment mark pattern  127 M, formed of the conductive pattern  127 B, the ferroelectric pattern  128 B, and the conductive pattern  129 B, is obtained in the scribe area  401 S. In the step of  FIG. 6E , a same mask is used for patterning both the lower electrode  127  and the conductive pattern  127 B. 
     In the step shown in  FIG. 6F , an Al 2 O 3  film  430 M corresponding to the encapsulation layer  430  is formed, for example, with a thickness of 100 nm in a manner uniformly covering the element area  401 A and the scribe area  401 S. In the step shown in  FIG. 6G , the encapsulation layer (second encapsulation layer)  430  is formed by patterning the Al 2 O 3  film  430 M in a manner allowing the encapsulation layer  430  to cover the ferroelectric capacitor FC via the Al 2 O 3  encapsulation layer  430 A. As a result of the step of  FIG. 6G , the alignment mark pattern  127 M, which is covered by the Al 2 O 3  film  430 M in the step of  FIG. 6F , becomes exposed. Further, in the step shown in  FIG. 6G , the layer-interposed insulating film  130  is formed on the layer-interposed insulating film  126 . 
     In the step shown in  FIG. 6H , a mask alignment process is performed based on the alignment mark pattern  127 M. Then, in accordance with the mask alignment, a photolithography process and a dry-etching process are performed, in which contact holes  130 A,  130 B are formed in the layer-interposed insulating film  130  in the element area  401 A in a manner penetrating the encapsulation layers  430 ,  430 A, and exposing the upper electrode  129  and the lower electrode  127 , respectively. By using the same mask, the aperture portion (alignment aperture portion)  130   m , which exposes the conductive pattern  129 B of the alignment mark pattern  127 M, is formed in the scribe area  401 S at the same time of the formation of the contact holes  130 A,  130 B. The dry-etching process in the step of  FIG. 6H  is performed by using, for example, an ICP type high density plasma etching apparatus. 
     In the step shown in  FIG. 6H , although a considerable amount of etching time may still be required for penetrating the encapsulation layers  430 ,  430 A, and the alignment aperture portion  130   m  may still be excessively etched to some extent, the rate of etching the alignment aperture portion  130   m  can be reduced once the alignment mark pattern  127 M becomes exposed. This owes to the alignment mark pattern  127 M, which has the same structure as the ferroelectric capacitor, being disposed below the alignment aperture portion  130   m . Therefore, unlike the step shown in  FIG. 3E , the alignment aperture portion  130   m  will not entirely penetrate the layer-interposed insulating film  126  and reach the silicon substrate  121 . 
     In the step shown in  FIG. 6H , the mask alignment process for forming the contact holes  130 A,  130 B are performed by using the alignment aperture portion  130   m  and the alignment mark pattern  127 M in a resist process. This enables the contact holes  130 A and  130 B to be accurately aligned with respect to the ferroelectric capacitor FC. 
     In the step shown in  FIG. 6I , a TiN film, serving as contact layer, is deposited to the structure shown in  FIG. 6H  by sputtering. Further, the W film is deposited thereon by a CVD method using a vapor WF 6  material. Thereby, the contact holes  130 A,  130 B and the alignment aperture portion  130   m  is filled with the W film via the TiN contact film. Further, unnecessary TiN film and W film remaining on the layer-interposed insulating film  130  is removed by a CMP method. Consequently, a structure shown in  FIG. 6I  is obtained, wherein the contact hole  130 A is filled by the W plug  132 A via the TiN contact film  131 A, the contact hole  130 B is filled by the W plug  132 B via the TiN contact film  131 B, and the alignment aperture portion  130   m  is filled by the W pattern  132 M via the TiN contact film  132 N. Here, the alignment mark pattern  127 M serves as a main mark pattern, and the W pattern  132 M serves as a sub mark pattern. 
     Since mask alignment is performed using the alignment aperture portion  130   m  and the alignment mark pattern  127 M in the step shown in  FIG. 6H , the state of alignment of, for example, the structure shown in  FIG. 6I , can be monitored by measuring the distance between the main mark pattern  127 M and the sub mark pattern  132 M. 
     As described above, the mark pattern  127 M stops excessive penetration of the aperture portion  130   m  and prevents the aperture portion  130   m  from reaching the silicon substrate  121  in the dry-etching process for forming the contact holes  130 A,  130 B, as shown in  FIG. 6H . Accordingly, even when tungsten is employed for filling the contact holes  130 A,  130 B, a WF6 gas, for example, used in a CVD method will not contact the silicon substrate  121 , and generation of a corrosive gas such as SiF 6  can be prevented. 
     In the step shown in  FIG. 6I , by forming the alignment pattern  132 M having a well-defined edge, and using the alignment pattern  132 M as a main pattern, a subsequent wiring pattern can be further formed to the structure shown in  FIG. 6I . 
     In addition, since the present invention prevents generation of corrosive gas, peeling in the mark pattern  132 M can be prevented. Accordingly, the generation of particles, which lead to yield loss of the semiconductor device, can be prevented. 
     Further, the subsequent wiring pattern is applied on the structure shown in  FIG. 6I  to form a multilayer wiring structure. Last, the silicon wafer  401  (see  FIG. 4A ), forming the silicon substrate  121 , is diced along the scribe areas  401 S, to thereby allow each of the element areas  401 A- 401 I to separate as semiconductor integrated circuit chips. 
     Although the first embodiment of the present invention is described using the element area  401 A shown in  FIG. 4B , the description applies to the other element areas  401 B- 401 I. 
     Second Embodiment 
       FIG. 7  is a cross-sectional view showing a wafer including a semiconductor device according to a second embodiment of the present invention. Like components are denoted by like numerals as of those in the first embodiment and will not be further explained. 
     In the second embodiment, the conductive pattern  129 B disposed at an upper-most portion of the alignment pattern  127 M in the scribe area  401 S is removed, to thereby obtain an alignment pattern  127 M having stack layers of the conductive pattern  127 B and the ferroelectric pattern  128 B. 
     Similar to advantages of the first embodiment, the structure of the second embodiment prevents the alignment aperture portion  130   m  from penetrating the ferroelectric pattern  128 B and the lower pattern  127 B and advancing into the layer-interposed insulating layer  126  during the etching process as shown in  FIG. 6H . 
     Third Embodiment 
       FIG. 8  is a cross-sectional view showing a wafer including a semiconductor device according to a third embodiment of the present invention. Like components are denoted by like numerals as of those in the above-described embodiments and will not be further explained. 
     In  FIG. 8 , the alignment pattern  127 M is formed not in a scribe area, but in an unused part of the element area  401 A. 
     Thus structured, a more accurate alignment can be performed since the alignment mark pattern  127 M is formed in the vicinity of the ferroelectric capacitor. 
     Furthermore, with the third embodiment shown in  FIG. 8 , the alignment mark pattern  127 M may be used as a ferroelectric capacitor according to necessity. 
     In addition, the present invention is not to be limited in use for fabrication of FeRAMs. The present invention may be effectively applied to a typical fabrication process of a semiconductor device, in which there is a difference in etching speed (etching rate) between different layers of a predetermined etching recipe. 
     Further, the present invention is not limited to these embodiments, but various variations and modifications may be made without departing from the scope of the present invention. 
     The present application is based on Japanese priority application No. 2004-080770 filed on Mar. 19, 2004 with the Japanese Patent Office, the entire contents of which are hereby incorporated by reference.