Abstract:
An analog to digital converter that comprises a successive approximation register (SAR) having an n bit binary output, a first capacitor array connected to receive some of the bits of the binary output, a second capacitor array connected to receive the remaining bits of the binary output, and a comparator including an output connected to the SAR. The first and second capacitor arrays each have an analog output indicative of the charge stored by capacitors of that array. The comparator includes a pair of inputs, one of which is connected to the analog output of the first capacitor array and the other of which is connected to the analog output of the second capacitor array.

Description:
STATEMENT REGARDING FEDERALLY-SPONSORED RESEARCH 
     This invention was made with government support under EEC9986866 awarded by the National Science Foundation. The government has certain rights in the invention. 
    
    
     TECHNICAL FIELD 
     This invention relates generally to analog to digital converters (ADCs) and, more particularly, to ADCs of the type that operate using a successive approximation register (SAR), comparator, and capacitor array. 
     BACKGROUND OF THE INVENTION 
     Recently, multichannel neural interface systems have been implemented to monitor neural activities. For the comprehensive analysis of neural activities, it is desirable to realize simultaneous real-time monitoring of multiple sites in 3D electrode arrays with 64 channels or more. Typically, neural activities such as spike contain most of their information in the bandwidth below 10 kHz with maximum amplitude of ±500 μV. In these microsystems, the neural signals should be amplified and converted into digital signals to be transmitted to wired/wireless communication channels between the implanted system and the external world. Simultaneous access of multiple sites should be done in a manner that utilizes analog-to-digital converters (ADC) having good noise immunity in a small form factor at low power. 
     A successive approximation register (SAR) ADC is one of the suitable candidates for neural interface applications due to its simplicity, low power consumption, and reasonable resolution. With a gain of 60 dB prior to the ADC, the quantization noise is required to be less than 5 mVrms which can be achieved by 8 bit or higher resolution capability of ADC.  FIG. 1  shows a conventional 8 bit SAR ADC structure which typically consists of three parts: capacitor array (for sample and hold and DAC), comparator, and successive approximation register (SAR). For relatively lower resolution ADCs (&lt;6 b), the comparator and SAR consume most of the power. However, as the resolution of ADCs increases, the power consumption required for charging and discharging the capacitor array becomes significant. Also, the total capacitance required for DAC increases exponentially proportional to the number of bits. In the high resolution ADCs, the capacitor array takes most of the area and power consumption. It becomes more important to reduce the total capacitance and area as the number of bits required in ADC increases and multiple implementations of ADCs is needed. You-Kuang et al. reported an effective switching method to reduce the power. However, this switching technique can reduce only half of the power in conventional capacitor arrays. Yang et al. proposed an energy-efficient ADC with a small form factor. However, a relatively complex algorithm may be needed for practical use in neural microsystems. 
     SUMMARY OF THE INVENTION 
     In accordance with one embodiment of the invention, there is provided an analog to digital converter that comprises a successive approximation register (SAR) having an n bit binary output, a first capacitor array connected to receive some of the bits of the binary output, a second capacitor array connected to receive the remaining bits of the binary output, and a comparator including an output connected to the SAR. The first and second capacitor arrays each have an analog output indicative of the charge stored by capacitors of that array. The comparator includes a pair of inputs, one of which is connected to the analog output of the first capacitor array and the other of which is connected to the analog output of the second capacitor array. 
     In accordance with another embodiment of the invention, there is provided an analog to digital converter that comprises a successive approximation register (SAR) having an n-bit binary output that includes a most significant bit (MSB) and a least significant bit (LSB), a comparator, and a plurality of n binary weighted capacitors each of which is associated with one of the bits of the binary output. The binary weighted capacitors include a first capacitor having a unit capacitance C associated with the LSB and one or more other capacitors each of which is associated with one of the other bits of the binary output. Each of the other capacitors has a capacitance value equal to 2 i ×C where i and n are integers and 0≦i≦n/2. 
     In accordance with yet another embodiment of the invention, there is provided an analog to digital converter that comprises: 
     an analog voltage input that receives an inputted analog voltage to be converted to digital form; 
     a reference voltage input that receives a reference voltage; 
     a successive approximation register (SAR) having an n-bit binary output including a most significant bit (MSB) and a least significant bit (LSB); 
     a comparator having inverting and non-inverting inputs and an output that is connected to the SAR; 
     a first capacitor array comprising an upper digital to analog converter (DAC) having an m-bit binary input, wherein m and n are positive integers with m&lt;n, and wherein each of the m-bits is connected to a corresponding bit of the SAR&#39;s binary output including one of the m-bits being connected to the LSB; 
     a second capacitor array comprising a lower DAC having an n-m bit binary input, wherein each of the n-m bits is connected to a corresponding bit of the SAR&#39;s binary output including one of the n-m bits being connected to the MSB; 
     wherein the first and second capacitor arrays each have an analog output that is connected to a different one of the inputs of the comparator. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Preferred exemplary embodiments of the invention will hereinafter be described in conjunction with the appended drawings, wherein like designations denote like elements, and wherein: 
         FIG. 1  is a schematic diagram of a conventional SAR ADC; 
         FIG. 2  is a schematic diagram of a dual capacitor array SAR ADC constructed in accordance with an embodiment of the present invention; 
         FIG. 3  depicts 4 bit SAR ADC operation examples for (a) a conventional SAR ADC and (b) a dual capacitor array SAR ADC constructed in accordance with an embodiment of the present invention; 
         FIG. 4  is a schematic of the comparator of the ADC of  FIG. 2 ; 
         FIGS. 5(   a )- 5 ( c ) are schematics of exemplary dual capacitor arrays showing switch operation during various phases of the successive approximation routine; 
         FIG. 6  is a microphotograph of fabricated ADCs; 
         FIG. 7  is a comparative graph of power consumption with respect to the ADC resolution; 
         FIG. 8  are graphs of the measured (a) DNL and (b) INL of the ADC of  FIG. 2 ; 
         FIG. 9  is an FFT plot of the measured digital output codes for an input frequency of 8046.875 Hz using the ADC of  FIG. 2 ; and 
         FIG. 10  are comparative graphs of the measured dynamic characteristics with different sampling frequency for the ADC of  FIG. 2 . 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Disclosed herein is an area-efficient 8 bit SAR ADC using dual capacitor arrays that permits a reduction in the required capacitor array area by a factor of 2 (n/2)−1  compared to the conventional approaches. This feature can not only reduce the total chip area but also the power consumption by reducing the power required for charging/discharging the capacitor array relative to that of prior ADCs. 
     The use of two smaller capacitor arrays instead of one much larger one is accomplished by utilizing a circuit in which the successive approximation iterations are carried out on both sides of comparator inputs using dual capacitor arrays rather than only on one side.  FIG. 2  depicts an exemplary embodiment  20  wherein an 8 bit DAC is implemented using two 4 bit capacitor arrays  22 ,  24 , an SAR  25 , and a comparator  26 . In the illustrated embodiment, the capacitor arrays  22 ,  24  have the same construction, but can be different in other embodiments. The upper DAC  22  is connected to the non-inverting input of the comparator  26  and is used to quantize the upper (most significant) 4 bits, while the lower DAC  24  is connected to the inverting input and does lower (least significant) 4 bits. An advantage of the dual capacitor arrays  22 ,  24  is the reduction of the total capacitance and area for DAC capacitors by a factor of: 
                 Reduction   ⁢           ⁢   Factor     =     2       n   2     -   1         ,         
where n is the number of bits. For example, for 8 and 10 bit resolutions, the reduction factors become 8 and 16, respectively. And the power consumed by the combined capacitor array would be reduced by the same reduction factor. This advantage is more effective for higher resolution ADCs. By applying this technique, one can effectively implement the ADCs within a given area and power budget. This feature can be used to easily equip a neural interface system with a simultaneous real-time monitor capability of the multiple neural activities.
 
       FIG. 3(   a ) shows an example of 4 bit ADC operations in conventional SAR ADC and  FIG. 3(   b ) shows the same operation using a dual capacitor array ADC  30 . Basic operations of the 4 bit SAR ADC can be divided into two steps: sample/hold and four iterations of successive approximations. During each approximation step, V in  can be expressed as: 
                 V   in     ⁡     [   n   ]       =         V   in     ⁡     [     n   -   1     ]       +       Vref     2     n   +   1         ⁢     (     1   -       (     -   1     )         D   o     ⁡     [   n   ]           )               
If the V in [n] is smaller than V ref , the comparator output is 1, and the SAR sets the output b n =1 and generates the control signal to make V in [n] be V in [n−1]+V ref /2 n . If the V in  is greater than V ref , the output is b n =0, and the V in  stays from previous step. The red line shows V in  from each steps. By repeating this step four times, the signal can be quantized into a 4 bit resolution.
 
     As shown  FIG. 3(   a ), the conventional ADC is performing the approximation in the one input node of the comparator while the other input side is fixed to reference. On the other hand, the dual capacitor array ADC  30  of  FIG. 3(   b ) uses both sides (signal side:  2  bit and reference side:  2  bit) to perform the approximation. During the first two steps, the upper DAC  32  is operated to approximate V ref  to V in  as shown by the upper V ref  line in  FIG. 3(   b ). Successively, during the following two steps, V in  is approximated to V ref  using the lower DAC  34 . After four steps, the example signal is digitized as 1010. For the same resolution, the  FIG. 3(   b ) ADC  30  requires only half (=1/reduction factor=½ (n/2)−1 ) the area in the capacitor array and consumes half the power as compared to the conventional ADC of  FIG. 3(   a ). As indicated in  FIGS. 2 and 3(   b ), to carry out the successive approximation using the dual capacitor arrays, each of the circuits  20 ,  30  utilize not only the V ref , but also an additional reference voltage V ref /2 n/2 , which can be provided (generated) internally or externally. 
       FIG. 4  shows the schematic diagram of the comparator  26 . Due to smaller capacitance in the dual capacitor arrays  22 ,  24 , the regenerative comparator may cause kickback effect during the regenerative phase. This coupling effect between input and output may severely deteriorate the performance of ADC. To suppress this phenomenon, a buffer stage  42  with gain of 10 is introduced prior to the regenerative comparator  44 . The difference between two inputs (V in  and V ref ) is sampled and amplified through the buffer stage  42  and then forwarded to the regenerative stage  44  during reset phase. In the positive rising edge of V Latch  when regenerative phase starts, the difference is amplified and eventually the polarity of the difference is determined. The dual capacitor array ADC can use two identical capacitor arrays that are located on both input nodes of the comparator. This configuration helps to suppress the comparator offset which may come from the charge injection from the reset switches or any unexpected possible leakage path. 
     As shown in  FIG. 5(   a ), to implement both upper and lower DACs, two identical capacitor arrays  22 ,  24  have been implemented using MIM capacitors, where a unit capacitance is given as 100 fF. Total capacitance for the area-efficient 8 bit ADC is 2×2 4 ×C=32 C where C is the unit capacitance of array corresponding to the least significant bit. The two 4 bit capacitor arrays are identical except that the lower (least significant bits) DAC  24  has an additional switch  28  to sample and hold the signal during the comparison.  FIG. 5(   a ) shows the ADC switch position during the reset/track phase of the overall successive approximation routine.  FIG. 5(   b ) shows the sample phase and  FIG. 5(   c ) shows the comparison phase. 
       FIG. 6  is a photograph of fabricated conventional and dual capacitor array ADCs. This figure depicts an example of the chip area savings obtainable using the present invention. These devices were fabricated using a 0.25 μm 1P5M CMOS process. To evaluate the proposed ADC, both ADCs were measured and characterized. The total active area of the dual capacitor array ADC is 0.035 mm 2 , while the conventional ADC occupies 0.196 mm 2 . Performance of the ADCs is summarized in Table 1. The fabricated ADCs have the resolution of 8 bit with the sampling frequency of 20 kS/s. The total power consumption of the dual capacitor array ADC is 680 nW at 1.8V (Analog) and 2.5V (digital) supply. The comparator consumes most of power (˜498 nW), and the proposed capacitor array consumes 92 nW from 1.2 V input range, while the conventional capacitor array consumes ˜737 nW, which is eight times higher and even higher than the comparator. 
     
       
         
               
               
               
             
           
               
                   
                 TABLE I 
               
               
                   
                   
               
               
                   
                 Parameter 
                 Measured 
               
               
                   
                   
               
             
             
               
                   
                 Technology 
                 0.25 μm 1P5M CMOS 
               
               
                   
                 Supply Voltage 
                 1.8 V (Analog)/2.5 V (Digital) 
               
               
                   
                 Sampling Frequency 
                 20 kS/s 
               
               
                   
                 Power Consumption 
                 680 nW 
               
               
                   
                 INL 
                 &lt;±0.5 LSB 
               
               
                   
                 DNL 
                 &lt;±0.5 LSB 
               
               
                   
                 SNDR 
                 42.82 ± 0.47 dB 
               
               
                   
                 SFDR 
                 57.90 ± 2.82 dB 
               
               
                   
                 THD 
                 −53.58 ± 2.15 dB 
               
               
                   
                 Resolution/ENOB 
                 8 bits/6.65 ± 0.07 bits 
               
               
                   
                 Figure of Merit 
                 0.34 pJ/conversion 
               
               
                   
                 Area 
                 0.035 mm 2   
               
               
                   
                   
               
             
          
         
       
     
     An estimated power consumption as a function of resolutions in ADC is shown in  FIG. 7 . The total power consumption increases with resolution. Especially, the power consumption by the conventional capacitor array becomes significant when the resolution is above 7 bit, and increases even exponentially with resolution (2 n ). On the other hand, the power consumption of the dual capacitor array slowly increases by a factor of 2 n/2 , and consumes much less power. Even in 10 bit resolution, the power consumption of the dual capacitor array stays below that of the comparator. 
       FIG. 8  shows the measurement results of differential nonlinearity (DNL) and integral nonlinearity (INL). The measured INL and DNL are both below ±0.5 LSB. 
     The measured 8 bits digital output codes are analyzed using the FFT from the input signal of 8046.875 Hz and 256 samples shown in  FIG. 9 . The measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 42.82±0.47 dB and 57.90±2.82 dB, respectively. Total harmonic distortion (THD) and effective number of bit (ENOB) are −53.58±2.15 dB and 6.65±0.07 bits, respectively. 
     The dynamic characteristics of the ADC with different sampling frequencies was also measured to test leakage. Leakage can be significant in small capacitor arrays at low sampling frequency (&lt;1 kS/s) such as EEG or ECoG applications. The results are shown in  FIG. 10 . The performance of the dual capacitor array ADC remains constant with the range of the various sampling frequencies (625 Hz˜20 kHz) indicating leakage is not a serious issue with the small capacitance array bank. 
     It is to be understood that the foregoing description is of one or more preferred exemplary embodiments of the invention. The invention is not limited to the particular embodiment(s) disclosed herein, but rather is defined solely by the claims below. Furthermore, the statements contained in the foregoing description relate to particular embodiments and are not to be construed as limitations on the scope of the invention or on the definition of terms used in the claims, except where a term or phrase is expressly defined above. Various other embodiments and various changes and modifications to the disclosed embodiment(s) will become apparent to those skilled in the art. All such other embodiments, changes, and modifications are intended to come within the scope of the appended claims. 
     As used in this specification and claims, the terms “for example,” “for instance,” and “such as,” and the verbs “comprising,” “having,” “including,” and their other verb forms, when used in conjunction with a listing of one or more components or other items, are each to be construed as open-ended, meaning that the listing is not to be considered as excluding other, additional components or items. Other terms are to be construed using their broadest reasonable meaning unless they are used in a context that requires a different interpretation.