Abstract:
An ultra-large scale integrated (ULSI) circuit includes MOSFETs which have a gate conductor with dopants distributed in a box-like distribution. The dopants also achieve high electrical activation. The MOSFETs utilize gate structures with heavily doped polysilicon material or heavily doped polysilicon and germanium material. The polysilicon and polysilicon and germanium materials are manufactured by utilizing amorphous semiconductor layers. Excimer laser annealing is utilized to activate the dopants and to provide a box-like dopant profile.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is related to U.S. patent application Ser. No. 09/187,881, filed on an even date herewith by Yu, entitled “Heavily-Doped Polysilicon/Germanium Thin Film Formed by Laser Annealing.” U.S. Pat. No. 6,127,216. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates generally to an integrated circuit (IC) and the fabrication of an integrated circuit. More particularly, the present invention relates to an integrated circuit having gate electrode material which is highly activated. 
     BACKGROUND OF THE INVENTION 
     Ultra-large scale integrated (ULSI) circuits generally include a multitude of transistors, such as, more than one million transistors and even several million transistors on a substrate. The transistors are generally metal oxide semiconductor field effect transistors (MOSFETs), which include a gate conductor disposed between a source region and a drain region. The gate conductor is provided over a thin gate oxide material. 
     Generally, the gate conductor is a polysilicon or polysilicon/ germanium (Si x Ge (1−x) ) material that controls charge carriers in a channel region between the drain and the source to turn the transistor on and off. The transistors can be N-channel MOSFETs or P-channel MOSFETs. 
     The polysilicon and polysilicon/germanium gate materials are heavily doped (e.g., P+ or N+) to increase their conductivity. According to conventional processes, the dopant implant projection is positioned at one-half the depth of the gate material (i.e., gate electrode) thickness to reduce the possibility of dopant diffusion through the thin gate oxide into the channel. Dopant diffusion through the thin gate oxide can adversely affect the predictability of the design and the operability of the circuit. 
     In conventional processes, dopant distribution in the gate material has a Gaussian-like profile (i.e., the dopant concentration is greatest in the center of the gate material). Accordingly, the dopant concentration near the gate electrode/gate oxide interface is relatively low. The relatively low dopant concentration near the gate electrode and gate oxide interface is referred to as “gate-depletion effect” and is a major problem in complementary MOS (CMOS) processes which manufacture small scale transistors. 
     Conventional processes for fabricating transistors have a limited thermal budget so shallow junctions can be effectively formed. Shallow junctions are necessary for appropriate transistor size in ULSI circuits. Dopant implanted into the gate material is often not sufficiently activated due to the limited thermal budget. The low electrically activated dopant concentration near the gate material/gate oxide interface, combined with the gate depletion effect, causes higher resistance in the polysilicon or polysilicon/germanium gate material. The higher resistance results in a greater voltage drop between the center of the gate electrode/gate oxide. The greater voltage drop causes a loss of effective voltage bias, which in turn degrades MOSFET drive current and speed, and which also increases the power consumed by the transistor. 
     Thus, there is a need for a process that can manufacture a gate conductor having a box-like dopant profile and achieve high dopant activation. Further still, there is a need for a gate conductor that has a relatively low thermal budget and is not susceptible to gate-depletion effect. Further still, there is a need for a polysilicon/germanium gate conductor that can be efficiently manufactured. 
     SUMMARY OF THE INVENTION 
     The present invention relates to a method of manufacturing an integrated circuit. The method includes providing an amorphous semiconductor layer over a dielectric layer, doping the amorphous semiconductor layer, providing a silicide layer over the amorphous semiconductor layer, and annealing the amorphous semiconductor layer to form a crystallized semiconductor layer. Dopants are distributed in the crystallized semiconductor layer in a box-like profile. 
     The present invention also relates to a method of manufacturing an ultra-large scale integrated circuit including field effect transistors disposed on a semiconductor substrate. Each of the transistors has a gate structure with a gate conductor having a box-like dopant profile. The method includes steps of providing an amorphous silicon layer over a dielectric layer disposed over the substrate, doping the amorphous silicon layer, providing a silicide layer over the amorphous silicon layer, etching the dielectric layer, the amorphous silicon layer, and the silicide layer to form preliminary gate structures, providing nitride spacers for the preliminary gate structures, and laser annealing the amorphous semiconductor layer. 
     The present invention even further relates to a method of providing a gate structure with a gate conductor having a box-like dopant profile. The method includes providing an amorphous layer over a gate dielectric layer disposed over a substrate, doping the amorphous layer, providing a silicide layer over the amorphous layer, selectively etching the gate dielectric layer, the amorphous layer, and the metal semiconductor layer to form a gate stack, providing spacers for the gate stack, and laser annealing the amorphous layer. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will hereafter be described with reference to the accompanying drawings, wherein like numerals denote like elements, and: 
     FIG. 1 is a cross-sectional view of a portion of an integrated circuit in accordance with an exemplary embodiment of the present invention; 
     FIG. 2 is a cross-sectional view of the portion of the integrated circuit illustrated in FIG. 1, showing a gate dopant implant step; 
     FIG. 3 is a cross-sectional view of the portion of the integrated circuit illustrated in FIG. 1, showing a silicide deposition step; and 
     FIG. 4 is a cross-sectional view of the portion of the integrated circuit illustrated in FIG. 1, showing a gate stack etching step. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     With reference to FIG. 1, a portion  10  of an integrated circuit (IC) or chip includes a transistor  12 . Portion  10  is preferably part of an ultra-large-scale integrated (ULSI) circuit having 1,000,000 or more transistors. Portion  10  is manufactured as part of the IC on a semiconductor wafer, such as, a silicon wafer. 
     Transistor  12  is disposed on a substrate  16  that is preferably silicon. Alternatively, substrate  16  can be any suitable semiconductor material. Transistor  12  includes a gate stack  18 , which includes sidewall spacers  22 , a gate dielectric  24 , a metal semiconductor layer  26 , and a polysilicon layer  28 . 
     Spacers  22  and dielectric  24  can be silicon dioxide, nitride, or other insulating material. Spacers  22  are preferably nitride (Si 3 N 4 ) formed by depositing a nitride layer and selectively etching the nitride layer. The nitride layer can be deposited by chemical vapor deposition (CVD). Dielectric  24  is preferably a thermally grown 2-5 nm layer of silicon dioxide. Alternatively, dielectric  24  can be other insulative materials, such as, nitride. 
     Transistor  12  also includes a drain  30 , a source  32 , and a channel  34 . Channel  34  of transistor  12  is disposed underneath dielectric  24  and between source  32  and drain  30 . Transistor  12  can be an N-channel or a P-channel transistor. 
     Metal semiconductor or silicide layer  26  is preferably a silicide layer that is approximately 100-500 namometers (nm) thick. Layer  26  is preferably directly deposited or sputtered tungsten silicide (WSi x ), where x is between 1 and 2. Layer  26  can be any type of silicide. 
     Polysilicon layer  28  is preferably 100-200 nm thick. Layer  28  preferably has a box-like dopant distribution where dopant is relatively highly dense near the gate electrode/gate oxide interface (between layers  28  and  24 ). Additionally, high dopant activation has been achieved in layer  28 . Layer  28  can be amorphous or polysilicon a silicon/germanium layer (Si x Ge (1−x ), a amorphous or polyoxide germanium layer, or other semiconductor layer. 
     With reference to FIGS. 1-4, the fabrication of portion  10  is described below as follows. In FIG. 2, dielectric layer  24  is thermally grown as a very thin oxide on top of substrate  16 , which is silicon. Layer  28  is deposited on top of layer  24  as a 100-200 nm layer. Layer  28  can be deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD). 
     Layer  28  is preferably deposited in a low-temperature CVD (LTCVD) process as amorphous silicon, at a temperature below 500° C. After layer  28  is deposited, a gate dopant ion implant process is utilized to provide a chosen dopant into layer  28 . The dopant is represented by the symbol x in FIGS. 2 and 3. The dopant can be arsenic, phosphorous, boron, boron diflouride, indium, or other dopant. Layer  28  can be doped in a ion implantation process, a diffusion process, or other method for providing dopants into layer  28 . 
     With reference to FIG. 3, layer  26  is deposited or sputtered on top of layer  28  as a 150 nm metal semiconductor (a silicide) film. Preferably, layer  26  is deposited directly as a tungsten silicide (WSi x ) by a CVD process. Alternatively, layer  26  can be any type of a refractory metal and silicon combination, such as, a cobalt silicide, or other silicide material. Alternatively, layer  26  can be deposited as a silicon layer and  2  refractory metal layer and then transformed to a silicide in a conventional silicidation process. 
     With reference to FIG. 4, layers  24 ,  26 , and  28  are etched to form a portion of gate stack  18  on substrate  16 . Layers  24 ,  26 , and  28  can be formed by a photolithography and etching process. Layers  24  and  28  can be etched by dry-etching, wet-etching, or other removal technique. 
     With reference to FIG. 1, a nitride layer is provided over gate stack  18  and selectively etched to leave spacers  22 . Spacers  22  are preferably provided adjacent layers  26  and  28 . After spacers  22  are formed, portion  10  is thermally annealed to melt layer  28  from an amorphous silicon layer to a polysilicon layer. After melting, layer  28  is recrystallized as a polysilicon layer. Preferably, portion  10  is thermally annealed by an excimer laser process that heats layer  28  to over 800° C. Advantageously, gate stack  18  is fabricated without any gate-rounding effect during the melting of layer  28  because layer  26  and spacers  22  provide a fixed container for the melting of layer  28 . 
     After recrystallization of layer  28 , the dopant profile along the vertical direction is box-like due to the melting of layer  28 . Accordingly, dopant density near the gate electrode/gate oxide interface (between layer  24  and layer  28 ) is higher than can be obtained from conventional ion implantation methods. In addition, high dopant activation is achieved by melting layer  28 . 
     Alternatively, layer  28  can be an amorphous germanium layer or a combination of an amorphous germanium layer and an amorphous silicon layer that is recrystallized as a polycrystalline or as a polysilicon/germanium layer, respectively. In such a technique, gate stack  18  can have a gate conductor that includes a germ mm layer. The germanium layer could be deposited by low pressure CVD. In another alternative, layer  28  can be implanted with germanium via an ion implantation technique. For example, layer  28  can be a Si x Ge (1−x)  layer, where x is between 0 and 1. 
     It is understood that while the detailed drawings, specific examples, and particular values given provide a preferred exemplary embodiment of the present invention, the preferred exemplary embodiment is for the purpose of illustration only. The method and apparatus of the invention is not limited to the precise details and conditions disclosed. For example, although particular polysilicon and silicide gate structures are described, other types can be utilized. Various changes may be made to the details disclosed without departing from the spirit of the invention, which is defined by the following claims.