Abstract:
A folded cascode differential amplifier includes a high-voltage input stage and a low-voltage output stage. The input stage is formed from high-voltage MOS transistors, two of which constitute a differential pair. The output stage is formed from low-voltage MOS transistors, some of which constitute a current mirror circuit connected to the differential pair. The output stage also includes at least one transistor that amplifies a voltage produced in the current mirror circuit to generate an output voltage signal. The high-voltage MOS transistors have higher breakdown voltages than the low-voltage MOS transistors. Incorporation of both types of transistors into a single amplifier reduces the necessary number of transistors and the necessary number of bias voltages.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a folded cascode differential amplifier having both high-voltage and low-voltage transistors, and to a semiconductor device including the amplifier and its bias circuit. 
     2. Description of the Related Art 
     Differential amplifiers used in liquid crystal displays, for example, have inputs that may vary over a wide common-mode voltage range, even though the differential input voltage range is comparatively small and the output voltage range may be even smaller. A conventional differential amplifier of this type employs two folded cascode differential amplifiers, using one as an input stage and the other as an output stage. The input amplifier has high-voltage transistors and operates on a relatively high power supply voltage. The output amplifier has low-voltage transistors and operates on a relatively low power supply voltage. 
     Since each of the two folded cascode differential amplifiers has a large number of transistors, one problem with this conventional two-stage design is that it takes up considerable space. A further problem is large output error, due to inaccurate matching of resistance ratios and to offset inaccuracies. Further details will be given in the detailed description of the invention. 
     Other examples of amplifiers used in liquid crystal displays can be found in, for example, Japanese Patent Application Publications No. 2009-070211, 2007-148428, and 2005-025596. 
     SUMMARY OF THE INVENTION 
     An object of the invention is to reduce the size of a differential amplifier having a high-voltage input stage and a low-voltage output stage. 
     Another object of the invention is to improve the accuracy of a differential amplifier having a high-voltage input stage and a low-voltage output stage. 
     The invention provides a novel folded cascode differential amplifier that includes an input stage operating on a first power supply voltage and an output stage operating on a lower second power supply voltage. 
     The input stage is formed from a first plurality of metal-oxide-semiconductor (MOS) transistors, two of which constitute a differential pair that receive respective input voltage signals. The output stage is formed from a second plurality of MOS transistors, some of which constitute a current mirror circuit connected to the differential pair. The second plurality of MOS transistors also includes at least one transistor forming an amplifying circuit that amplifies a voltage produced in the current mirror circuit to generate an output voltage signal. 
     The first plurality of MOS transistors have higher breakdown voltages than the second plurality of MOS transistors. 
     The incorporation of transistors with both comparatively high and comparatively low breakdown voltages into a single folded cascode differential amplifier, instead of having separate high-voltage and low-voltage folded cascode differential amplifiers, saves space by reducing the total number of transistors required. 
     Accuracy is improved because the reduced number of transistors reduces error due to manufacturing variability, and because there are fewer external resistor connections to be made, reducing error due to imprecise resistance values. 
     The invention also provides a semiconductor device including the novel folded cascode differential amplifier and a bias circuit. The bias circuit includes a constant current source, a current mirror circuit powered by the first power supply voltage, and a current mirror circuit powered by the second power supply voltage. The size of the bias circuit is comparatively small because there are comparatively few transistors to be biased in the novel folded cascode differential amplifier. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       In the attached drawings: 
         FIG. 1  is a simple schematic circuit diagram of a novel semiconductor device including a differential amplifier and its bias circuit; 
         FIG. 2  is a schematic circuit diagram of the bias circuit in  FIG. 1  in a first embodiment of the invention; 
         FIG. 3  is a schematic circuit diagram of the differential amplifier in  FIG. 1  in the first embodiment; 
         FIG. 4  is a schematic circuit diagram of the bias circuit in  FIG. 1  in a second embodiment of the invention; 
         FIG. 5  is a schematic circuit diagram of the differential amplifier in  FIG. 1  in the second embodiment; 
         FIG. 6  is a simple schematic circuit diagram of a conventional semiconductor device including two differential amplifiers and their bias circuit; 
         FIG. 7  is a simple schematic circuit diagram indicating the ranges of the input voltages to the first differential amplifier in  FIG. 6 ; 
         FIG. 8  is a graph showing exemplary input and output voltages in  FIG. 6 ; 
         FIG. 9  is a schematic circuit diagram of the bias circuit in  FIG. 6 ; 
         FIG. 10  is a schematic circuit diagram of the high-voltage differential amplifier in  FIG. 6 ; and 
         FIG. 11  is a schematic circuit diagram of the low-voltage differential amplifier in  FIG. 6 . 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Embodiments of the invention will now be described with reference to the attached drawings, in which like elements are indicated by like reference characters. The description will refer to high-voltage and low-voltage p-channel metal-oxide-semiconductor (PMOS) and n-channel metal-oxide-semiconductor (NMOS) transistors. The terms high-voltage and low-voltage are relative, meaning that a high-voltage transistor is able to withstand source-drain, gate-drain, and source-gate voltages that would cause breakdown in a low-voltage transistor. In the drawings, HVMOS is used to designate high-voltage MOS transistors and LVMOS is used to designate low-voltage MOS transistors. 
     Folded cascode differential amplifiers will sometimes be referred to simply as differential amplifiers. 
     First Embodiment 
     Referring to  FIG. 1 , a first embodiment of the invention is a semiconductor device  10  including a bias circuit  12 , a folded cascode differential amplifier  14 , and resistors R 11 , R 12 , R 13 , R 14 . Exemplary resistance values of the resistors are twelve megohms (12 MΩ) for R 11  and R 13 , and 6 MΩ for R 12  and R 14 . 
     An input voltage VINU 1  is supplied through resistor R 11  to a node connected to the non-inverting input terminal of the differential amplifier  14  and, through resistor R 12 , to ground. An input voltage VIND 1  is supplied through resistor R 13  to a node connected to the inverting input terminal of the differential amplifier  14  and, through resistor R 14 , to the output terminal of the differential amplifier  14 . With the exemplary resistance values shown, these connections force the differential amplifier  14  to generate an output voltage OUT 1  equal to half the difference between VINU 1  and VIND 1 . For example, if VINU 1  exceeds VIND 1  by six volts (6 V), the output voltage OUT 1  is 3 V with respect to ground. 
     The differential amplifier  14  operates on two power supply voltages: 80 V and 5 V. The bias circuit  12  supplies the differential amplifier  14  with five bias voltages BIAS_H 1 _P 1 , BIAS_H 2 _P 1 , BIAS_L 2 _P 1 , BIAS_L 1 _N 1 , BIAS_L 2 _N 1 . 
     Referring to  FIG. 2 , the bias circuit  12  has a high-voltage (HVMOS) section  20 , a low-voltage (LVMOS) section  22 , and a constant current source  23 . The constant current source  23  generates a constant one-hundred nanoampere (100 nA) current from the 5-V power supply. The high-voltage section  20  is configured as a current mirror circuit that uses the 100-nA current and the 80-V power supply to generate bias voltages BIAS_H 1 _P 1  and BIAS_H 2 _P 1 . The high-voltage section  20  also supplies a current to the low-voltage section  22 . The low-voltage section  22 , which is likewise configured as a current mirror, uses the supplied current and the 5-V power supply to generate bias voltages BIAS_L 2 _P 1 , BIAS_L 1 _N 1 , and BIAS_L 2 _N 1 . 
     The high-voltage section  20  includes high-voltage PMOS transistors HP 1 , HP 2  and high-voltage NMOS transistors HN 1 , HN 2 , HN 3 , HN 4 . The source terminals of the PMOS transistors HP 1 , HP 2  are connected to the 80-V power supply. The source terminals of the NMOS transistors HN 1 , HN 2 , HN 3 , HN 4  are connected to ground. The drain terminal of transistor HN 1  receives the 100-nA current from the constant current source  23 . The gate terminals of transistors HN 1 , HN 2 , HN 3 , HN 4  are all connected to the drain terminal of transistor HN 1 , so that transistors HN 2 , HN 3 , and HN 4  conduct currents that mirror the 100-nA current conducted by transistor HN 1 . The drain terminal of transistor HN 2  is connected to the drain and gate terminals of transistor HP 1  at a node from which bias voltage BIAS_H 2 _P 1  is taken. The drain terminal of transistor HN 3  is connected to the drain and gate terminals of transistor HP 2  at a node from which bias voltage BIAS_H 1 _P 1  is taken. 
     The low-voltage section  22  includes low-voltage PMOS transistors LP 1 , LP 2 , LP 3  and low-voltage NMOS transistors LN 1 , LN 2 . The source terminals of the PMOS transistors LP 1 , LP 2 , LP 3  are connected to the 5-V power supply. The source terminals of the NMOS transistors LN 1 , LN 2  are connected to ground. The drain terminal of transistor LP 1  is connected to the drain terminal of high-voltage NMOS transistor HN 4  in the high-voltage section  20 . The gate terminals of transistors LP 1 , LP 2 , LP 3  are all connected to the drain terminal of transistor LP 1  at a node from which bias voltage BIAS_L 2 _P 1  is taken. Transistors LP 2  and LP 3  conduct currents that mirror the current conducted by transistors LP 1  and HN 1 , which in turn mirrors the 100-nA current output by the constant current source  23 . The drain terminal of transistor LP 2  is connected to the drain and gate terminals of transistor LN 1  at a node from which bias voltage BIAS_L 1 _N 1  is taken. The drain terminal of transistor LP 3  is connected to the drain and gate terminals of transistor LN 2  at a node from which bias voltage BIAS_L 2 _N 1  is taken. 
     Referring to  FIG. 3 , the differential amplifier  14  has a folded cascode configuration including an input stage  30  and an output stage  32 . The input stage  30  includes a differential pair  34  that detects the difference between input voltages INP_H 1  and INN_H 1 . The output stage  32  includes a current mirror section  35 , a constant current source section  36 , and an amplifying section  38 . The current mirror section  35  and constant current source section  36  form a single current mirror circuit. 
     The input stage  30  includes high-voltage PMOS transistors HP 3 , HP 4 , HP 5 , HP 6 . Transistors HP 3  and HP 4  are connected in a cascode configuration: the source terminal of transistor HP 3  is connected to the 80-V power supply; the gate terminal of transistor HP 3  receives bias voltage BIAS_H 1 _P 1 ; the drain terminal of transistor HP 3  is connected to the source terminal of transistor HP 4 ; the gate terminal of transistor HP 3  receives bias voltage BIAS_H 2 _P 1 ; the drain terminal of transistor HP 3  is connected to the source terminals of transistors HP 5  and HP 6 , which form the differential pair  34 . An input voltage INN_H 1  is supplied to the gate terminal of transistor HP 5 , which forms the inverting input terminal of the differential amplifier  14 . An input voltage INP_H 1  is supplied to the gate terminal of transistor HP 6 , which forms the non-inverting input terminal of the differential amplifier  14 . The drain terminals of transistors HP 5  and HP 6  are connected to the constant current source section  36  in the output stage  32  by interconnecting lines denoted node_A and node_B. 
     The output stage  32  includes low-voltage PMOS transistors LP 4 , LP 5 , LP 6 , LP 7  forming the current mirror section  35 , low-voltage NMOS transistors LN 3 , LN 4 , LN 5 , LN 6 , LN 7  forming the constant current source section  36 , and a single low-voltage PMOS transistor LP 8  forming the amplifying section  38 . The 5-V supply voltage is supplied to the source terminals of PMOS transistors LP 4 , LP 5 , LP 8 . The source terminals of NMOS transistors LN 5 , LN 6 , LN 7  are connected to ground. Transistors LP 4 , LP 6 , LN 3 , LN 5  are connected in series in this order between the 5-V power supply and ground. Similarly, transistors LP 5 , LP 7 , LN 4 , LN 6  are connected in series in this order between the 5-V power supply and ground. Transistors LP 8  and LN 7  are also connected in series between the 5-V power supply and ground, their drain terminals both being connected to the output node of the folded cascode differential amplifier  14 , from which the output voltage OUT 1  is taken. The gate terminals of transistors LP 4  and LP 5  are connected to the drain terminal of transistor LP 6 . The gate terminals of transistors LP 6  and LP 7  receive bias voltage BIAS_L 2 _P 1 . The gate terminals of transistors LN 3  and LN 4  receive bias voltage BIAS_L 2 _N 1 . The gate terminals of transistors LN 5 , LN 6 , and LN 7  receive bias voltage BIAS_L 1 _N 1 . The gate terminal of transistor LP 8  is connected to the drain terminal of transistor LP 7 . 
     Node_A and node_B are connected to intermediate points in the constant current source section  36 . Specifically, node_A is connected to the source of transistor LN 3  and the drain of transistor LN 5 , and node_B is connected to the source of transistor LN 4  and the drain of transistor LN 6 . The voltages at node_A and node_B are therefore both kept relatively low. For example, when the difference between the input voltages INP_H 1  and INN_H 1  is 6 V, the voltages at node_A and node_B are less than about 0.3 V. The interconnections between the high-voltage input stage  30  and low-voltage output stage  32  accordingly pose no risk of voltage breakdown in the output stage  32 . 
     The circuits in  FIGS. 2 and 3  require a total of twenty-five transistors, of which ten are high-voltage transistors. Only four of the high-voltage transistors are disposed in the folded cascode differential amplifier  14 , all in the input stage  30 . 
     The bias circuit  12  has to generate only five bias voltages, and requires only six high-voltage transistors. 
     These resistor counts compare quite favorably with the resistor counts of the conventional differential amplifier circuit and bias circuit described below. 
     The theory of operation of folded cascode differential amplifiers and bias circuits of the general type shown in  FIGS. 2 and 3  is well known, so a detailed description of the operation will be omitted. 
     Second Embodiment 
     The second embodiment differs from the first embodiment in the internal circuit configuration of the folded cascode differential amplifier and the bias circuit. 
     Referring to  FIG. 4 , the bias circuit  42  in the second embodiment includes the same low-voltage section  22  as in the first embodiment but has a different high-voltage section  50 , an additional low-voltage mirror section  52 , an additional low-voltage cascode section  54 , and two constant current sources  23 A,  23 B instead of one. 
     The high-voltage section  50  includes the same transistors HP 1 , HP 2 , HN 1 , HN 2 , HN 3 , HN 4  as in the first embodiment, interconnected in the same way except that the gate terminal of transistor HP 2  is connected to the drain terminal of transistor HP 1  instead of to the drain terminal of transistor HP 2 . In addition, the high-voltage section  50  has another high-voltage NMOS transistor HN 0 . Transistor HN 0  has its source terminal connected to ground and its gate terminal connected to its drain terminal, which receives a 100-nA current from constant current source  23 A. The gate and drain terminals of transistor HN 0  are also connected to the drain terminal of transistor HN 1 , which receives a 100-nA current from constant current source  23 B. 
     The low-voltage mirror section  52  includes NMOS transistors MN 1 , MN 2 , MN 3 , MN 4  that form a current mirror connected in cascode with the current mirror in the high-voltage section  50 . The source terminals of NMOS transistors MN 1 , MN 2 , MN 3 , MN 4  are connected to ground, their gate terminals are connected to the drain terminal of transistor HN 1 , and their drain terminals are connected to the source terminals of the corresponding high-voltage NMOS transistors HN 1 , HN 2 , HN 3 , HN 4 . 
     The low-voltage cascode section  54  includes a single low-voltage PMOS transistor MP 1  that is connected in cascode with high-voltage PMOS transistor HP 2 . This cascode PMOS transistor MP 1  has its source terminal connected to the 80-V power supply, its gate terminal connected to the drain terminal of transistor HP 2 , and its drain terminal connected to the source terminal of transistor HP 2 . Bias voltage BIAS_H 1 _P 1  is taken from the drain of transistor HP 2  as in the first embodiment. 
     Referring to  FIG. 5 , the folded cascode differential amplifier  44  in the second embodiment has the same output stage  32  as in the first embodiment, a modified input stage  60 , and an additional low-voltage cascode section  62 . The low-voltage cascode section  62  includes a low-voltage PMOS transistor MP 2  that replaces high-voltage PMOS transistor HP 3  in the first embodiment. Transistor MP 2  has its source connected to the 80-V power supply and its drain connected to the source terminal of transistor HP 4 , and receives bias voltage BIAS_H 1 _P 1  at its gate terminal. 
     Aside from the replacement of high-voltage PMOS transistor HP 3  by low-voltage PMOS transistor MP 2 , the input stage  60  is identical to the input stage in the first embodiment. 
     The cascode connections of the additional low-voltage transistors MP 1 , MP 2 , MN 1 , MN 2 , MN 3 , MN 4  ensure that their source-drain, gate-drain, and gate-source voltages do not greatly exceed their threshold voltages. Accordingly, voltage breakdown does not occur, even though these transistors are on current paths leading from the 80-V power supply to ground. 
     The second embodiment operates in the same way as the first embodiment (details omitted). 
     The substitution of low-voltage transistor PMOS transistor MP 2  for high-voltage PMOS transistor HP 3  in the second embodiment reduces the layout space of the differential amplifier  44 , and improves the offset characteristic of the differential amplifier  44  by improving the accuracy of the current mirror circuit in the output stage  32 . 
     The additional low-voltage transistors added to the bias circuit  42  in the second embodiment improve the accuracy of the bias voltages, without requiring as much layout space as would be necessary if high-voltage cascode transistors were used. 
     The breakdown voltage of low-voltage transistor MP 2  in the differential amplifier  44  in the second embodiment is preferably the same as the breakdown voltages of the transistors in the output stage  32 . Similarly, the breakdown voltages of the additional low-voltage transistors MP 1 , MN 1 , MN 2 , MN 3 , MN 4  in the bias circuit  42  are preferably the same as the breakdown voltages of the transistors in the low-voltage section  22 . If necessary, however, transistors with higher breakdown voltages may be used in the low-voltage mirror section  52  and low-voltage cascode sections  54 ,  62 , provided these breakdown voltages are lower than the breakdown voltages of the high-voltage transistors. 
     For comparison, the above-mentioned conventional circuit with two folded cascode differential amplifiers will now be described. 
     Referring to  FIG. 6 , the conventional differential amplifier  110  includes a bias circuit  112 , resistors R 1  to R 8 , a high-voltage differential amplifier  114  operating on an 80-V power supply, and a low-voltage differential amplifier  115  operating on a 5-V power supply. The low-voltage differential amplifier  115  consists entirely of low-voltage transistors, the high-voltage differential amplifier  114  consists entirely of high-voltage transistors, and the bias circuit  112  includes both high-voltage and low-voltage transistors. The bias circuit  112  supplies four bias voltages BIAS_H 1 _P, BIAS_H 2 _P, BIAS_H 1 _N, BIAS_H 2 _N to the high-voltage differential amplifier  114  and four bias voltages BIAS_L 1 _P, BIAS_L 2 _P, BIAS_L 1 _N, BIAS_L 2 _N to the low-voltage differential amplifier  115 . 
     As in the embodiments described above, this conventional circuit receives a pair of input voltages VINU and VIND and generates an output voltage-equal to half their difference.  FIG. 7  represents the source of the input voltages VINU, VIND as a pair of variable voltage sources, one of which generates a differential voltage Vin of from 0 V to 7 V, the other of which generates a common-mode voltage Vcom of from 0 to 73 V. These voltage sources are connected so that Vcom is the voltage between the VIND input terminal and ground and Vin is the voltage between the VINU and VIND input terminals. 
     Resistors R 1 -R 4  are connected to the high-voltage differential amplifier  114 , and resistors R 5 -R 8  to the low-voltage differential amplifier  115 , in the configuration described in the first embodiment. The output amp 1 _out of the high-voltage differential amplifier  114  is supplied through resistor R 5  to the non-inverting input terminal of the low-voltage differential amplifier  115 . The inverting input terminal of the low-voltage differential amplifier  115  is connected through resistor R 7  to ground. The resistance values are 12 MΩ for R 1  and R 3 , 8 MΩ for R 2  and R 4 , 4 MΩ for R 5  and R 7 , and 3 MΩ for R 6  and R 8 . These resistance values cause differential amplifier  114  to operate with ⅔ gain ( 8/12 gain) and differential amplifier  115  to operate with ¾ gain, so that the output voltage (OUT) is equal to the differential input voltage Vin multiplied by ½. 
     The two-stage amplification process is illustrated in  FIG. 8  for the case in which the differential input voltage Vin is 6 V. As the common-mode input voltage Vcom is stepped from 0 V to 72 V, the high-voltage differential amplifier  114  consistently produces an output voltage (amp 1 _out) of 4 V, and the low-voltage differential amplifier  115  consistently produces an output voltage (OUT) of 3 V. 
     Referring to  FIG. 9 , the conventional bias circuit  112  includes a constant current source  123  that generates a 100-nA current, a high-voltage section  120  that operates on the 80-V power supply, and a low-voltage section  122  that operates on the 5-V power supply. The circuit configurations of the high-voltage section  120  and low-voltage section  122  are generally similar to the circuit configurations of the high-voltage section  20  and low-voltage section  22  in the first embodiment, but since eight bias voltages must be generated, more transistors are required. The high-voltage section  120  includes six high-voltage PMOS transistors and five high-voltage NMOS transistors. The low-voltage section  122  includes four low-voltage PMOS transistors and two low-voltage NMOS transistors. 
     Referring to  FIG. 10 , the high-voltage differential amplifier  114  has the same folded cascode circuit configuration as the differential amplifier  14  in the first embodiment except that since all of its constituent transistors are high-voltage transistors, only four bias voltages are necessary. In all, the high-voltage differential amplifier  114  includes nine high-voltage PMOS transistors and five high-voltage NMOS transistors. 
     Referring to  FIG. 11 , the low-voltage differential amplifier  115  has the same circuit configuration as the high-voltage differential amplifier  114  except that all of its constituent transistors are low-voltage transistors. Four more bias voltages are necessary. 
     Taken together, the circuits in  FIGS. 9 to 11  include a total of twenty-five high-voltage transistors and twenty low-voltage transistors. This is considerably more than the total of ten high-voltage transistors and fifteen low-voltage transistors used by the bias circuit  12  and differential amplifier  14  in the first embodiment, and also compares unfavorably with the ten high-voltage transistors and twenty-one low-voltage transistors found in the second embodiment. In particular, the use of more than twice as many high-voltage transistors makes the conventional differential amplifier  110  much larger than the differential amplifier  10  in the first and second embodiments. 
     A further advantage of the circuits in the first and second embodiments is that they require only half as many resistors as the conventional circuit. Besides saving space, this reduction in the resistor count improves the precision of the output voltage by reducing opportunities for resistance value error. 
     The reduced number of transistors also improves the precision of the output, by reducing the likelihood of error due to mismatched transistor characteristics. 
     The invention is not limited to the embodiments described above. Those skilled in the art will recognize that numerous variations are possible within the scope of the invention, which is defined in the appended claims.