Abstract:
Supervisory audio tones received from a mobile telephone unit are converted from analog to digital form. The tone is then converted to a complex number by bifurcating the tone path and multiplying one path by a sine function and the other path by a cosine function. The complex numbers are accumulated and the frequencies where significant power exists is found using the discrete Fourier transform. If the power at an assigned frequency exceeds a threshold, the corresponding supervisory audio tone is declared to have been detected.

Description:
TECHNICAL FIELD 
     This invention relates to cellular mobile radio telephone systems and, in particular, to rapid and reliable detection of audio control tones in the presence of severe signal-to-noise conditions. 
     BACKGROUND OF THE INVENTION 
     Volume 58, number 1 of The Bell System Technical Journal, published in January 1979 by the American Telephone and Telegraph Company, discloses through several articles therein the Advanced Mobile Phone Service, a cellular mobile radio telephone system. At page 23 therein, it is stated that when a system is first installed, cell sites are omnidirectional in the horizontal plane. As initial systems grow into mature systems, however, omnidirectional antennas will be augmented by three 120-degree sector antennas called alpha, beta and gamma: each voice channel in a cell site being transmitted and received over one of the three antennas. 
     As stated at page 47 of the aforesaid Journal, supervision is the process of detecting customer intiated changes in the switch-hook state of a telephone. In order to avoid false supervision caused by co-channel interference, from the reuse of channels, the aforesaid cellular system uses a combination of a signaling tone (ST) burst and a continuous out-of-band, supervisory audio tone (SAT). Three SAT&#39;s are set aside at 5970, 6000, and 6030 Hz; any one is used at a given cell site. A mobile unit receives a SAT from a cell site and returns it to the cell site. It is important for the cell site to compute reliably the SAT returned from the mobile unit within a predetermined period. This invention teaches the rapid and accurate computation of the SAT from a variety of sources concurrently. 
     SUMMARY OF THE INVENTION 
     In accordance with the illustrative embodiment of the present invention, if a received supervisory audio tone (SAT) associated with a channel in a cellular mobile radio system is above a threshold, then a decoder confirms detection of the corresponding SAT. More particularly, the SAT which is received from a mobile unit is converted from analog to digital form and appropriately limited for noise immunity. The SAT is bifurcated into two paths. The tone in one path is multiplied by a cosine function of time to derive the real component of a complex number and the tone in the other path is multiplied by a sine function to derive the imaginary component of the complex number. A series of the real components of the generated complex numbers is accumulated in an inphase data accumulator and the corresponding imaginary components of the complex numbers are accumulated in a (quad) quadrature phase accumulator. By combining the real and imaginary components and performing a discrete Fourier transform (DFT) on the complex numbers, the power of the received signal at the frequencies of interest is found rapidly and within a predetermined period. The value at the assigned SAT frequency is then compared with a threshold. If the threshold is exceeded, the SAT at the given frequency is delcared to have been detected. 
     An advantage of the present invention is that it provides reliable detection of SAT in a fading channel. The prior art typically relied on phase lock loops which become unlocked during fades or other types of signal interruption. Similarly, methods based on analog filters were excessively sensitive to tolerances and the like in view of the excessively high selectively, or Q, required. 
     A further advantage of the present invention as disclosed is that the digital nature of the implementation allows it to be effectively multiplexed, by sampling received signals discontinuously over several antenna faces thus encountering a type of interruption, or by sampling continuously with apparent concurrency over several discrete channels. For example, in the implementation described in this application, distinct parallel equipment including receivers, for each antenna face, would be required if the signal detection were done by phase lock loops. 
     A further advantage of the present invention is that by nature of the digital implementation under stored program control, parameters of the detection process such as selectivity may be dynamically altered in real time. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a block diagram of apparatus implementing the present invention; 
     FIG. 2 is a graph of the expression √Fr 2  +Fi 2  ; 
     FIG. 3 is a graph of the expression |Fr|+|Fi|; 
     FIG. 4 is a line drawing showing the various computations to be done within a predetermined period to determine a supervisory audio tone; 
     FIGS. 5 through 9 are flow charts showing the various steps in the computation of supervisory audio tones; and 
     FIG. 10 is a block diagram of another apparatus implementation of the present invention. 
    
    
     DETAILED DESCRIPTION 
     Referring to FIG. 1, there is shown apparatus for receiving and detecting the presence of supervisory audio tones (SAT&#39;s) from a mobile unit. More particularly, omnidirectional antenna 10, and directional antennas 12, 14 and 16 receive signals from a mobile telephone unit (not shown). Although only four antennas are described, it is clear that this number may be changed. As stated in the background of this application, omnidirectional antennas are used to receive signals from all directions. But when a system grows, the omnidirectional antenna configuration is augmented by three directional antennas: alpha, beta, and gamma; each antenna serving a separate region of angular width 120 degrees. Switch 18 switches each of the aforesaid antennas in turn to receiver 20. After being filtered by element 21, analog signals are converted to digital signals in converter 22. A crystal oscillator 24 drives a binary counter 26 which provides clock signals at different synchronous subrates to the various elements and will not be described in detail because such technology is well known. 
     The digital signal from converter 22 is fed to a read only memory (ROM) 30 comprising limiter 32 for reducing spurious signals. Limiter 32 is a return to zero limiter of the type disclosed in a patent application having Ser. No. 497,228, filed May 23, 1983 by D. J. Thomson, one of the inventors of the present application which is now U.S. Pat. No. 4,596,024, issued on June 17, 1986. 
     The frequency of the received signal is extracted by conceptually feeding the output from limiter 32 to two multiplication circuits 34 and 36. Circuit 34 has two inputs: the output from limiter 32 and sin (ω c  t), where ω c  =2πf c  and f c  is the frequency of the center SAT (6,000 Hz). Likewise, circuit 36 has two inputs: the output from limiter 32 and cos (ω c  t). The output signals from circuit 34 are numerically integrated in element 42 of quadrature accumulator 40 and the output signals from circuit 36 are likewise numerically integrated in element 44 of data accumulator 46. The aforesaid signals from the multiplier circuits 34 and 36 are integrated over an interval from 0 to T (approximately one millisecond). That is, the first integrator 42, in cooperation with processor 50 performs a discrete approximation to the analog operation: ##EQU1## and the second integrator 44, again cooperating with processor 50, likewise performs a discrete approximation to the analog operation: ##EQU2## 
     Each integral is over T seconds and is repeated every T k  seconds. In the preferred embodiment the integration time T is approximately one millisecond and the time between integrations, T k , is (66.6 over 8) milliseconds. Each of these integrals over T seconds comprises twelve subintegrals which are computed in hardware accumulators 42 and 44. The output signals from accumulators 42 and 44 are combined by processor 50 in the manner described hereinbelow. Each of these subintegrals comprise sixty-four samples and extend for one half-cycle of the 6 KHz signal, that is, for 1/12,000 of a second. Equivalently, each subintegral formed by summing sixty-four consecutive output signals from multipliers 34 and 36 at a spacing of 1/64×12,000 of a second, that is, 1.302 microseconds, and so have a duration of T/12 seconds. Twelve consecutive half-cycle results are combined in a manner described below to give the approximation to the integrals in equations (1) and (2). The two integrals of the sine and cosine products are combined to provide a complex number, as described hereinabove. These operations are repeated N times (N=8 in the preferred embodiment) to provide N complex numbers which are stored in buffer storage unit 52 of processor 50. 
     Next, a discrete Fourier transform (DFT) is done on the complex numbers in unit 54 of processor 50. The method of DFT is a well known process and may be found for example beginning at page 162 of a book entitled, &#34;Digital Processing of Signals&#34; by B. Gold and C. M. Rader, published by the McGraw-Hill Book Company. The DFT step yields N complext numbers. To determine the frequency of SAT, s(t), the frequency corresponding to the maximum F(i) is chosen for 0&lt;=i&lt;=N-1. Thereafter, in circuit 56, if the amplitude at the assigned frequency exceeds a threshold, a determination is made that the corresponding SAT has been detected. The method of calculating the maximum F(i) follows hereinbelow. The method is clearly not restricted to a single frequency and, for example, multiple SAT&#39;s could be assigned and amplitude and/or phase relations between them determined in a manner similar to that described herein. 
     The use of equations (1) and (2) for calculating the frequency of s(t) is explained by the reasoning hereinbelow. Consider the integral ##EQU3## where, T=the period of integration; 
     
         f(t)=e.sup.j(ω.sbsp.c.sup.+ω.sbsp.0.sup.)t+jθ(4); 
    
     ω c  =center frequency; and 
     ω o  =offset frequency. 
     Thus, ##EQU4## so that T, as defined above, acts as a scaling factor; the greater the T, the greater the sensitivity and selectivity; ##EQU5## is a phase factor and is ignored in this frequency analysis; and ##EQU6## is a distortion factor. For a narrow channel, the distortion factor is approximately one, so that it can be neglected. 
     Thus, 
     
         z.sub.n ≈Ae.sup.jω.sbsp.o.sup.nT.sbsp.k      (6) 
    
     where, A is a complex constant. Because e j ω.sbsp.c t  =cos ω c  t+j sin ω c  t, then z n  can be evaluated by computing two integrals: ##EQU7## 
     If this is repeated N times, N complex numbers can be obtained which correspond to N discrete points of Ae j ω.sbsp.o t , where each point is separated in time by T k  ; that is: ##EQU8## 
     The remaining problem is to determine ω o  by performing a DFT on the sequence of N complex points: 
     
         x.sub.0 +jy.sub.0 =z.sub.0, z.sub.1, z.sub.2, . . . , z.sub.N-1. 
    
     As stated hereinabove, it is necessary to determine the maximum value of F(i). Values of F(i) are obtained by performing a DFT on the sequence of complex points which are described hereinbelow. The magnitude of F(i) is determined from the expression: ##EQU9## From computer simulation, it has been found that an effective approximation is: 
     
         |real F(i)|+|imag F(i)|(11) 
    
     A comparison of a graph for equation (10), shown in FIG. 2, and a graph for equation (11), shown in FIG. 3, justifies the aforesaid approximation. The broader flattened peaks in FIG. 3 are advantageous in that mobile units have finite frequency tolerance. 
     The steps taken by processor 50 in computing the complex numbers received from quadrature accumulator 40 is shown in FIGS. 5 through 9. These steps are sufficiently detailed and are not repeated here. The goal is to determine eight complex numbers. The real component corresponds to the cos (ωt) component and the imaginary part corresponds to the sin (ωt) component. Each complex number is determined by entering numbers, the aforementioned subintegrals, from both data accumulator 40 and from quadrature accumulator 46 twelve times into corresponding processor registers. Each time a number is entered from aforesaid accumulators, it is either added to or subtracted from a running sum which is maintained in two corresponding processor data and quadrature registers. 
     Subtraction or addition is invoked depending upon whether an even or an odd half cycle is occurring. A lookup table located in an integrated circuit comprising the multiplier circuits 34 and 36 has half cycle information. In order to obtain information spanning a whole cycle, it is necessary to invert the sign of data from alternate half cycles. The use of lookup tables is well known and will not be further described. 
     After the eight numbers have been determined as stated hereinabove, a DFT is done. The following method is used: ##EQU10## where, x(k) corresponds to the real part of the kth number; 
     y(k) corresponds to the imaginary part of the kth number; 
     FR(n) corresponds to the real part of the nth Fourier coefficient; and 
     FI(n) corresponds to the imaginary part of the nth Fourier coefficient. 
     These steps are derived from the definition of the DFT: ##EQU11## In this definition, n is taken mod N. That is, n=0 and n=N correspond as do the pairs n=-1 and n=N-1, n=-2 and n=N-2, and the like. For example, when N=8, n=-2 and n=6 are equivalent. Thus, the FR(6) and FI(6) of equations (16) and (17), respectively, supply the information required for m=-2 in equation (32), hereinbelow. 
     In the preferred embodiment there are only three SAT&#39;s to be computed: 5,970 Hz; 6,000 Hz; and 6,030 Hz. Therefore, there are only three Fourier coefficients to be calculated: corresponding to the 6,000 Hz SAT 
     
         FR(0)+jFI(0)                                               (19); 
    
     corresponding to the 6,030 Hz SAT 
     
         FR(2)+jFI(2)                                               (20); 
    
     and corresponding to the 5,970 Hz SAT 
     
         FR(6)+jFI(6)                                               (21). 
    
     Because of the aforesaid approximation, the following expressions are evaluated: 
     
         |FR(0)|+|FI(0)|        (22); 
    
     
         |FR(2)|+|FI(2)|        (23); 
    
     and 
     
         |FR(6)|+|FI(6)|        (24)). 
    
     If any of these sums exceeds a threshold, the corresponding SAT is determined to be present. 
     After the decision has been made in circuit 56 as stated hereinabove, the output is sent over path 57 to a cell site controller (not shown). After the decision has been made for the omnidirectional antenna, the aforesaid steps are repeated for each of the three directional antennas. Note, however, that this does not imply that measurements and decisions for four antennas requires four times the time required for one. Using the referred values of T=1 mS and T k  =66.6/8=≈8 mS. one can perform measurements on the omni antenna for 1 mS, then switch immediately to the α face. Allowing about one mS for the receiver IF filter to settle from the change in level, one then makes the 1 mS integration on the α face. Continuing thus through β and γ one completes the cycle and is ready to begin the subsequent integration on the omni face with a delay of T k  about 8 mS from the previous integration. Thus, the total measurement time for all four antennas requires only 7  mS more than the time needed for a single antenna. 
     Each SAT must be detected within a period L given by the expression: 
     
         M/Δf                                                 (25) 
    
     where 
     Δf=30 Hz, the frequency difference between two SAT&#39;s; and 
     M=2, an integer. 
     Substituting the values for M and Δf and simplifying, the value of 66.6 milliseconds for L is obtained. Thus, the SAT measurements must be done within a period, approximately sixty-seven milliseconds. The computations can be done either concurrently or subsequently, as required. This can be understood by referring to FIG. 4. 
     Each of the aforesaid complex numbered samples is maintained as thirty-two bits; sixteen bits by way of the real part and sixteen bits by way of the imaginary part. The real part x k  is given by ##EQU12## the imaginary part y k  is given by ##EQU13## where, p nk  is the nth sample from data accumulator 46, and q nk  is the nth sample from the quadrature accumulator 40 during the kth time interval. Each of the p&#39;s and q&#39;s is the sum of sixty-four products of s(t) with cosine computed in data accumulator 46 and sixty-four products of s(t) with sine computed in quadrature accumulator 40 over the same half cycle of the 6 KHz clock. 
     The DFT is defined by the expression: ##EQU14## The frequencies, f m , of z m  is given by the expression: ##EQU15## Simplifying, the frequencies are: for m=-2, f m  =5,970 Hz; 
     for m=0, f m  =6,000 Hz; and 
     for m=2, f m  =6,030 Hz. 
     If any of the z m  corresponding to each of these f m  frequencies is larger than a threshold, then the corresponding SAT is declared to be present. 
     A listing of the computer programs for the aforesaid steps is included in an appendix to this application. 
     Referring to FIG. 10, there is shown apparatus for concurrently monitoring SAT on a plurality of active voice channels. In this embodiment, separate receivers exist for each channel and are not switched at the antennas so that there is not the problem of waiting for receiver settling time as in the previously described embodiment. Thus, there are a plurality of channel receivers 102, 104, 106 . . . 108, each sampled sequentially and repetitively. 
     High speed analog multiplexor 110 is placed advantageously at the output of each receiver and interleaved samples taken for each channel at a rate, typically, 48 KHz. The output from multiplexor 110 is fed to an analog-to-digital converter, such as element 22 in FIG. 1, the rest of the circuit remaining the same. 
     The data and quad accumulators are partitioned according to the original signal source or channel and serve as multiplexed integrators serving multiple channels. By replacing the single latch in the accumulator with one for each channel being monitored and switching latches synchronously with the channel multiplexor one may have effectively T=T k  on all channels with the attendant gain in sensitivity. 
     Subsequent data and quadrature processing proceeds concurrently for all channels. By interleaving the individual channel samples, all channels may be processed in parallel and results for all channels will be available at the same time in individual buffers for each channel. 
     In addition to its use in mobile radio telephony, the aforesaid method of signal detection can be used in related fields where signal detection in the presence of noise is a major consideration.