Abstract:
A new inverter-based fully-differential amplifier is provided including one or more common-mode feedback transistors coupled to each inverter, which transistors operate in the liner region. Accordingly, due to the fully-differential nature of the new inverter-based fully-differential amplifier, the amplifier provides an improved Power Supply Rejection Ratio (PSRR), provides a reduced sensitivity to supply voltage and process or part variations, and does not require an auto-zeroing technique to be utilized, which ultimately saves power, all while utilizing the low-voltage and low-power advantages of an inverter-based design.

Description:
RELATED APPLICATION(S) 
       [0001]    This application claims the benefit of European Patent Application No. 13290056.4, filed Mar. 13, 2013, the contents of which are incorporated by reference as if fully rewritten herein. 
       TECHNICAL FIELD 
       [0002]    This invention relates generally to differential amplifiers. 
       BACKGROUND 
       [0003]    Differential amplifiers, as understood in the art, are commonly used building blocks in analog circuits. A known technique involving differential amplifiers is to use an inverter as a low-voltage rail-to-rail amplifier. However, this known technique provides only a pseudo-differential amplifier (rather than fully-differential). Because of this, previous inverter-based pseudo-differential amplifiers are sensitive to supply voltage variations and process or part variations, which can result in poor Power Supply Rejection Ratio (PSRR) and other added noise on the output. 
       SUMMARY 
       [0004]    Generally speaking and pursuant to these various approaches, a new inverter-based fully-differential amplifier is provided. The inverter-based differential amplifier includes one or more common-mode feedback transistors coupled to each inverter that operates in the linear mode. Accordingly, the inverter-based differential amplifier becomes fully differential so as to provide an improved PSRR, reduced sensitivity to supply voltage and process or part variations, and does not require an auto-zeroing technique to be utilized, which ultimately reduces complexity, silicon surface area, and power usage. These and other benefits may become clearer upon making a thorough review and study of the following detailed description. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]      FIG. 1  is a high-level circuit diagram of an example implementation of a prior art inverter-based pseudo-differential amplifier; 
           [0006]      FIG. 2 . illustrates a circuit diagram of an example new inverter-based fully-differential amplifier in accordance with various approaches; 
           [0007]      FIG. 3  illustrates an multiple-stage version of the new inverter-based fully-differential amplifier of  FIG. 2  in accordance various approaches; 
           [0008]      FIG. 4  illustrates a common mode signal amplifier in accordance with various approaches; 
           [0009]      FIG. 5  illustrates an example version of the high-level circuit diagram of  FIG. 1  modified to use the new inverter-based fully-differential amplifier in accordance with at least one approach. 
       
    
    
       [0010]    Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions and/or relative positioning of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of the present invention. Also, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments. It will further be appreciated that certain actions and/or steps may be described or depicted in a particular order of occurrence while those skilled in the art will understand that such specificity with respect to sequence is not actually required. It will also be understood that the terms and expressions used herein have the ordinary technical meaning as is accorded to such terms and expressions by persons skilled in the technical field as set forth above except where different specific meanings have otherwise been set forth herein. 
       DETAILED DESCRIPTION 
       [0011]    Referring now to the drawings,  FIG. 1  illustrates an example high-level circuit diagram of an implementation of a prior art inverter-based pseudo-differential amplifier. In this prior art example, a first inverter  102  and a second inverter  104  are used in a pseudo-differential configuration in an example switched-capacitor delta-sigma modulator to implement the functionality of an Operational Transconductance Amplifier (OTA). In such a configuration, the inverters  102 ,  104  operate as low-voltage rail-to-rail amplifiers, which provides for a low-power and low-voltage pseudo-differential amplifier. Such a configuration has been presented by Youngcheol Chae in his paper “Low Voltage, Low Power, Inverter-Based Switched-Capacitor Delta-Sigma Modulator” published the IEEE Journal of Solid-State Circuits, February 2009, volume 44, issue 2, pages: 458-472, the contents of which are incorporated herein by reference. 
         [0012]    This example switched-capacitor integrator (used, for instance, with sigma-delta modulation) involves a two-phased (φ1 and (φ2) approach to load a differential input voltage (i.e., V IP  and V IM ) on to sampling capacitors C s    106  during phase φ1 through operation of switches  108  and  110 . During phase φ2, the charge in sampling capacitors C s    106  is then placed onto the input of each inverter  102 ,  104  by opening switches  108  and  110  and closing switch  112 . Capacitor C c    114  is used for auto-zeroing to create a virtual ground (V G ) and to accommodate sampling offset. Switch  116  operates to reconnect the integrator feedback capacitor C I    118  to the input of the inverter  102 ,  104  during phase (φ2 to complete the process. To implement this pseudo-differential approach, an auto-zeroing switch  120  is utilized to zero-out the inverter  102 ,  104  during each phase φ1. Auto-zeroing is required in this pseudo-differential architecture to help remove offset between the differential inputs V IP  and VI M  through operation of switches  110  to remove any offset at the virtual ground V G , and switches  120  to sample the offset. Further, to help remove offset, the capacitors and switches in sub-circuits  122  are added to help maintain a mid-point voltage on the input. 
         [0013]    The particulars of this example configuration are not required to fully understand the operation of the inverter-based pseudo-differential amplifier or the new inverter-based fully-differential amplifier  200 . However, auto-zeroing switches  110 ,  116 ,  120  and capacitors  114 ,  122  are required by the inverter-based pseudo-differential amplifier because single input inverters are used. These switches and capacitors increase the complexity and silicon surface area required. Further, such a configuration is not actually fully differential and thus is sensitive to supply voltage variations and process or part variations, which results in poor Power Supply Rejection Ratio (PSRR) and other added noise on an output. 
         [0014]    To resolve the issues identified above, a new inverter-based fully-differential amplifier is provided  200 .  FIG. 2  illustrates a circuit diagram of the new inverter-based fully-differential amplifier  200  in accordance with various approaches. By one approach, the amplifier  200  is a class-AB rail-to-rail low-voltage amplifier, though the teachings disclosed herein may be readily applicable to other classes of amplifiers. The amplifier  200  may be further configured to operate as an operational transconductance amplifier (OTA). The amplifier  200  includes a first inverter  202  configured to receive a first half of a differential input signal (i.e., IN M ) and a second inverter  204  configured to receive a second half of the differential input signal (i.e., IN p ). By one approach, the inverters  202 ,  204  are CMOS inverters each including an n-channel CMOS transistor  206 ,  208  and a p-channel CMOS transistor  210 ,  212 . The drains of the transistors  206 ,  210  of the first inverter  202  are coupled together to form the inverter output OUT P , while the drains of the transistors  208 ,  212  of the second inverter  204  are coupled together to form the inverter output OUT M . The outputs OUT P  and OUT M  together comprise a fully differential output signal. The sources of the p-channel transistors  210 ,  212  form the positive supplies of the inverters  202 ,  204  and the sources of the n-channel transistors  206 ,  208  form the negative supplies of the inverters  202 ,  204 . The gates of the p-channel transistor  210  and n-channel transistor  206  of the first inverter  202  are both coupled to one half of the input signal (i.e., IN m ) and the gates of the p-channel transistor  212  and n-channel transistor  208  of the second inverter  204  are both coupled to the other half of the input signal (i.e., IN P ). By one approach, the substrates of the p-channel transistors  210 ,  212  are coupled to a positive power supply (i.e., AVDD) and the substrates of the n-channel transistors  206 ,  208  are coupled to a negative power supply (i.e., AVSS). This configuration allows for rail-to-rail operation on the output with each output signal OUT M  and OUT P  being opposite to its respective input signal IN M  and IN P  (i.e., “inverted”). The output signals OUT M  and OUT P  are each currents that relate to an approximate inverse of the respective half of the input signals IN M  and IN P . 
         [0015]    The amplifier  200  also includes a first p-channel transistor  214  and a first n-channel transistor  216 , each coupled to the first inverter  202 , and a second p-channel transistor  218  and a second n-channel transistor  220 , each coupled to the second inverter  204 . Each of the first and second p- and n-channel transistors  214 ,  216 ,  218 ,  220  is configured to operate in a linear mode or linear region and to operate as a common-mode feedback control for each inverter  202 ,  204 . By using this linear mode common-mode feedback control, the amplifier  200  is configured to control a common-mode signal on the output signals OUT M  and OUT P . By one approach, each of these additional transistors  214 ,  216 ,  218 ,  220  are CMOS transistors, though other transistor topologies are possible. 
         [0016]    In one example, the transistors  214 ,  216 ,  218 ,  220  are coupled to the first and second inverter  202 ,  204  as follows. The first p-channel transistor  214  is configured such that its drain is operatively coupled to the positive supply of the first inverter  202  (i.e., the source of the p-channel transistor  210  of the first inverter  202 ), its gate to the output signal OUT P , and its source to a positive power supply (i.e., AVDD). The second p-channel transistor  218  is similarly configured such that its drain is operatively coupled to the positive supply of the second inverter  204  (i.e., the source of the p-channel transistor  212  of the first inverter), its gate to the output signal OUT M , and its source to the positive power supply. The first n-channel transistor  216  is configured such that its drain is operatively coupled to the negative supply of the first inverter  202  (i.e., the source of the n-channel transistor  206  of the first inverter  202 ), its gate to the output signal OUT P , and its source to a negative power supply (i.e., AVSS). The second n-channel transistor  220  is similarly configured such that its drain is operatively coupled to the negative supply of the second inverter  204  (i.e., the source of the n-channel transistor  208  of the second inverter  204 ), its gate to the output signal OUT M , and its source to the negative power supply. 
         [0017]    By another approach, the positive supplies of the first and second inverters  202 ,  204  are coupled together to form a positive node  222  and the negative supplies of the first and second inverters  202 ,  204  are coupled to form a negative node  224 . This coupling effectuates the fully-differential aspect of the amplifier  200 . The amplifier  200  effectuates linear mode common-mode feedback control to these nodes  222 ,  224  through the first and second p- and n-channel transistors  214 ,  216 ,  218 ,  220  to control the common-mode signal on the differential outputs OUT P  and OUT M . To do this, the amplifier  200  is configured to adjust an effective resistance between the positive node  222  and the positive voltage power supply with the first and second p-channel transistors  214 ,  218  and to adjust an effective resistance between the negative node  224  and the negative voltage power supply with the first and second n-channel transistors  216 ,  220 . 
         [0018]    So configured, an inverter-based fully-differential amplifier  200  is provided. The fully-differential aspect of the amplifier  200  allows for a high Common Mode Rejection Ratio (CMRR) for rejection of common mode noise, high Power Supply Rejection Ration (PSRR), and very low sensitivity to process or part variations. With non-fully-differential amplifiers, such as the pseudo-differential amplifiers shown in  FIG. 1 , the open ended outputs do not reject these common mode elements as well. For example, if some noise exists on one input to the pseudo-differential amplifier, or parts or processing are not exactly symmetric for each side of the signal chain, then this noise or non-symmetry can manifest itself as noise on the output signals. However, with the fully-differential amplifier  200 , this noise will be rejected at a much higher rejection rate. For example, the disclosed inverter-based fully-differential amplifier  200  may produce a PSRR greater than approximately 40 dB without the use of non-auto-zeroing techniques. 
         [0019]    It may be desirable in some instances to achieve a higher gain than may be output by a single stage of the inverter-based fully-differential amplifier  200 . A single stage may be capable of producing a gain of approximately 50-60 dB. However, if these teachings are repeated for a second stage amplifier, output gain can increase to as much as 80 dB or more. 
         [0020]    Referring now to  FIG. 3 , a multi-stage version  300  of the inverter-based fully-differential amplifier  200  is illustrated in accordance with various approaches. The first half and the second half of the previously described inverter-based fully-differential amplifier  200  are shown as before in  FIG. 2 . Together, these halves comprise the first stage  200  of the illustrated multi-stage amplifier  300  (here illustrated as having two stages). By at least one approach, the second stage  302  of the multi-stage amplifier  300  is simply a repeated version of first stage  200  with a select few modifications. For example, the second stage  302  includes a third inverter  304  and a fourth inverter  306 , which, like the first and second inverters  202 ,  204  of the first stage  200 , receive an input differential signal and output the second stage output differential signal. In this instance, the input signal to the second stage is the output signal of the first stage  200  (with the third inverter  304  receiving the OUT P  signal and the fourth inverter  306  receiving the OUT M  signal). The output signal of the second stage  302  is a fully differential signal OUT P2  and OUT M2 . 
         [0021]    Like the first stage  200 , the second stage amplifier  302  includes third and fourth p-channel and n-channel transistors  308 ,  310 ,  312 ,  314 , each of which is configured to operate in the linear region. As before, these transistors  308 ,  310 ,  312 ,  314 , and the transistors of the third and fourth inverters  304 ,  306 , are CMOS transistors by at least one approach. The third p-channel transistor  308  is configured such that its drain is operatively coupled to the positive supply of the third inverter  304 , its gate to the output signal OUT M2 , and its source to the positive power supply. The fourth p-channel transistor  310  is similarly configured such that its drain is operatively coupled to the positive supply of the fourth inverter  306 , its gate to the output signal OUT P2 , and its source to the positive power supply. The third n-channel transistor  312  is configured such that its drain is operatively coupled to the negative supply of the third inverter  304 , its gate to the output signal OUT M2 , and its source to the negative power supply. The fourth n-channel transistor  314  is similarly configured such that its drain is operatively coupled to the negative supply of the fourth inverter  306 , its gate to the output signal OUT P2 , and its source to the negative power supply. 
         [0022]    Also like the first stage  200 , by at least one approach, the positive supplies of the third and fourth inverters  304 ,  306  are coupled together to form a second positive node  316  and the negative supplies of the third and fourth inverters  304 ,  306  are coupled to form a second negative node  318 . The effective resistance between the second positive node  316  and the positive voltage supply can be adjusted by the third and fourth p-channel transistors  308 ,  310  operating parallel to each other and in the linear region. The effective resistance between the second negative node  318  and the negative voltage supply can be adjusted by the third and fourth n-channel transistors  312 ,  314  also operating parallel to each other and in the linear region. 
         [0023]    By another approach, the third and fourth p-channel transistors  308 ,  310  receive a common mode signal at their respective gates instead of the second stage output signal (OUT P2  and OUT M2 ). As is shown in  FIG. 4 , by one approach, the common mode signal is generated by a common mode amplifier  402  (such as an op amp) receiving on one input an ideal or desired common mode signal (such as a V MID  signal, representing the ideal middle signal of the outputs OUT P2  and OUT M2 , possibly through a resistor  403 , and possibly tied to ground through resistor  410 ) and receiving on the other input an average of the actual outputs of the second stage amplifier OUT P2  and OUT M2 . The average may be achieved by adding the two signals OUT P2  and OUT M2  through one or more resistors  404 ,  406 . The common mode amplifier  402  then amplifies the actual common mode signal that exists on the second stage output OUT P2  and OUT M2  by amplifying the difference between the average of the second stage outputs OUT P2  and OUT M2  and the ideal desired common mode signal (possibly with feedback resistor  408 ). Returning to  FIG. 3 , the third and fourth p-channel transistors  308 ,  310  then use this common mode signal to improve the CMRR of the multi-stage amplifier  300  with improved accuracy and speed over the common mode signal. By another approach, the third and fourth n-channel transistors  312 ,  314  receive the common mode signal at their respective gates instead of the second stage output signal (OUT P2  and OUT M2 ). 
         [0024]    Continuing with  FIG. 3 , by some approaches, the second stage output signal OUT M2  is coupled to the first stage output signal OUT P  and the second stage output signal OUT P2  is coupled to the first stage output signal OUT M  through one or more compensation capacitive components (i.e., capacitors  320  and  322 ) and/or resistive components (i.e., resistors  324  and  326 ) to ensure the stability of the multi-stage amplifier  300  by avoiding unwanted oscillation. 
         [0025]    With this multi-stage inverter-based fully-differential amplifier  300 , gain as high as 80 dB can be attained while maintaining the higher CMRR and PSRR as well as reduced sensitivity to process and part variations. Moreover, these teachings are highly scalable and can be employed using additional amplification stages, including a third stage, a fourth stage, or even further stages. Further, these teachings can be utilized with various other amplification stages and in various other configurations not discussed here. 
         [0026]    Turning now to  FIG. 5 , a version of the example high-level circuit diagram of  FIG. 1  is shown and modified to use the new inverter-based fully-differential amplifier  200  in accordance with at least one approach. The circuit of  FIG. 5 , like  FIG. 1 , shows the new inverter-based fully-differential amplifier  200  being used in an example switched-capacitor integrator configuration  500 , such as a sigma-delta modulator, to implement the functionality of an Operational Transconductance Amplifier. However, because the new amplifier  200  is fully-differential, unlike the example shown in  FIG. 1 , the new amplifier  200  does not require the use of the auto-zeroing switches  120  nor of the switches and capacitors of the sub-circuit  122  in this example configuration  500 . It should be noted, however, that the new amplifier  200  can still accommodate the use of auto-zeroing switches  120 , which may improve some of the performance aspects, but they are not required unlike the example from  FIG. 1 . Further, these teachings are highly versatile and can be utilized in many different designs, including Digital-to-Analog Converter (DAC) circuits, reference voltage circuits, filters, or any other circuit that may benefit from the use of a low-voltage and low-lower inverter-based fully-differential amplifier  200  as has been disclosed. 
         [0027]    Those skilled in the art will recognize that a wide variety of modifications, alterations, and combinations can be made with respect to the above described embodiments without departing from the scope of the invention, and that such modifications, alterations, and combinations are to be viewed as being within the ambit of the inventive concept.