Abstract:
An output stage provides increased current sourcing capability through a technique of local positive feedback. Current through a transistor MP 2  is mirrored by the output current source I OUT  that is desired to be increased. Without positive feedback, the gate of MN 2  would be fixed by MP 1  and MN 1 , and when input voltage V IN  decreases by an incremental voltage ΔV, the resulting current increase would distribute an increased voltage not only across MP 2&#39; s V GS  but also in the V GS  of another transistor MN 2 ; therefore, undesirably, not all of the ΔV voltage change is mirrored in I OUT . However, if positive feedback such as MP 5  is provided, the feedback dynamically increases the voltage at the gate of MN 2 . The increased voltage of MN 2&#39; s gate essentially provides more voltage “headroom” for MP 2  and MN 2 , and allows current through MP 2  to increase with any voltage decrease in V IN . Through current mirroring, the increased current through MP 2  ultimately results in the desired higher maximum output current source I OUT . This increase in output current sourcing is achieved with a minimal additional circuitry—a single transistor, MP5. The feedback is local (internal to the output stage), so that loop delay is minimal and response is fast. Further, because of improved DC gain within the output stage, the increased maximum I OUT  is achieved without compromising other circuit parameters such as power supply rejection ratio (PSRR).

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The invention generally relates to output stages of electronic components. More particularly, the invention relates to output stages in which increased current sourcing capability is desired.  
           [0003]    2. Related Art  
           [0004]    [0004]FIG. 1 depicts a conventional output stage that is suitable for use as an output buffer in, for example, Class AB amplifiers. While possessing favorable power supply rejection ratio (PSRR) performance, rail-to-rail output swing, and current sinking capability, the FIG. 1 circuit has relatively weak current sourcing capability (I OUT  is undesirably small).  
           [0005]    Due to current mirroring phenomena in the FIG. 1 configuration, the maximum output source current I OUT  is ultimately determined by how much gate-to-source voltage (V GS ) can be applied to the MP 2  sink. Assuming that all transistors in FIG. 1 are ideal and the same size, MN 3  conducts I B  when V IN  is equal to V B , a bias voltage applied to MP 1 . When V IN  swings an incremental voltage amount ΔV below V B , current through MP 2  increases accordingly. In the illustrated configuration, this MP 2  current increment is mirrored to MP 4 .  
           [0006]    Unfortunately, only part of the input change ΔV in V IN  is reflected as an increment in V GS  for MP 2 . Because the gate-to-source voltage V GS  for MN 2  (connected above MP 2 ) is fixed by the gate&#39;s connection to the gate of MN, part of the ΔV is “absorbed” by V GS  of MN 2  to account for the current increment. Thus, because the maximum output source current I OUT  is ultimately determined by how much gate-to-source voltage (V GS ) can be applied to the MP 2  sink, I OUT  does not adequately increase with ΔV variations in V IN , resulting in undesirably small maximum output source current I OUT .  
           [0007]    Accordingly, there is a need in the art to provide increased current sourcing capability of circuits such as that illustrated in FIG. 1, preferably with minimal additional circuitry and without compromising other operational features of the circuit.  
         SUMMARY  
         [0008]    Accordingly, there is provided an output stage for providing an increased current source output. The output stage has a first circuit element that carries a first current that varies in accordance with an input voltage and a feedback voltage that includes a first voltage across the first circuit element. The output stage also has a positive feedback arrangement that dynamically increases the feedback voltage in response to an increase in at least the first current, to supplement an increase in the first current beyond that caused by a change in the input voltage alone. The output stage also has a second circuit element that provides the increased current source output as a mirror of the first current. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]    A more complete appreciation of the described embodiments is better understood by reference to the following Detailed Description considered in connection with the accompanying drawings, in which like reference numerals refer to identical or corresponding parts throughout, and in which:  
         [0010]    [0010]FIG. 1 illustrates a conventional circuit displaying inadequate output current sourcing capability (I OUT );  
         [0011]    [0011]FIG. 2 illustrates one embodiment of a circuit that provides improved output current sourcing capability (maximum I OUT ) through use of positive feedback in the form of a MOSFET MP 5 ;  
         [0012]    [0012]FIGS. 3A and 3B respectively illustrate a test circuit diagram and related output source currents while using drivers according to the embodiment of FIG. 2 (AMP_A, top curve, indicated by “×” points) and according to the Background Art circuit of FIG. 1 (AMP_B, bottom curve, indicated by “+” points);  
         [0013]    [0013]FIGS. 4A and 4B respectively illustrate a test circuit diagram and related power supply rejection ratios (PSRRs) using drivers according to the embodiment of FIG. 2 (AMP_A, bottom curve, indicated by “×” points) and according to the Background Art circuit of FIG. 1 (AMP_B, top curve, indicated by “+” points); and  
         [0014]    [0014]FIG. 5 is a simplified schematic diagram illustrating an amplifier  500  that includes an output stage  520  that may be implemented according to the circuit of FIG. 2. 
     
    
     DETAILED DESCRIPTION  
       [0015]    In describing embodiments illustrated in the drawings, specific terminology is employed for the sake of clarity. However, the invention is not intended to be limited to the specific terminology so selected, and it is to be understood that each specific element includes all technical equivalents that operate in a similar manner to accomplish a similar purpose. Various terms that are used in this specification are to be given their broadest reasonable interpretation when used in interpreting the claims.  
         [0016]    Moreover, features and procedures whose implementations are well known to those skilled in the art are omitted for brevity. For example, design and implementation of basic electronic circuit elements such as current sources, voltage sources, and MOSFETs, lies within the ability of those skilled in the art, and accordingly any detailed discussion thereof may be omitted.  
         [0017]    [0017]FIG. 2 illustrates one embodiment of a circuit that provides improved maximum output current sourcing capability (maximum I OUT ) through use of positive feedback. The improved capability is achieved with minimal additional circuitry, while avoiding adverse impact on other circuit performance parameters such as, for example, power supply rejection ratio performance.  
         [0018]    Referring more specifically to FIG. 2, various elements are shown connected between DC voltage source VDD and ground (which may be a relative ground). In the illustrated embodiment, elements whose designators begin with “MP” (MP 1 , MP 2 , MP 3 , MP 4 ) are implemented as p-channel MOSFETs, and elements whose designators begin with “MN” (MN 1 , MN 2 , MN 3 ) are implemented as n-channel MOSFETs. Of course, alterations and variations of this implementation, such as use of JFETs, or use of transistors of different channel conductivity types (n versus p), and variation of voltage supply and supply arrangements, lie within the contemplation of the invention.  
         [0019]    First, a current source IB 2 , driven by VDD, drives the drain of MOSFET MN 1 . MN 1 &#39;s source drives the source of MOSFET MP 1  and MN 1 &#39;s gate is tied to its drain. The drain of MP 1  is connected to ground, while its gate receives a bias voltage V B .  
         [0020]    Second, MP 3 &#39;s source is connected to VDD, and its gate and drain are connected to the drain of MN 2 . MN 2 &#39;s gate is connected to the gate (and drain) of MN 1  at a central node, and MN 2 &#39;s source is connected to the source of MP 2 . MP 2 &#39;s drain is connected to ground, and its gate is driven by an input voltage V IN .  
         [0021]    Third, MP 4 &#39;s source is connected to VDD, and its gate is connected to the gate of MP 3 . MP 4 &#39;s drain drives the overall output of the output stage, sourcing a current I OUT  MP 4 &#39;s drain is also connected to the drain of MN 3 , whose gate is connected to V IN  and whose source is connected to ground.  
         [0022]    The topological connection of the current source, MN 1 , MN 2 , MN 3 , MP 1 , MP 2 , MP 3  and MP 4  parallels that of the Background Art circuit of FIG. 1. However, positive feedback provides the FIG. 2 embodiment with operational characteristics superior to those of Background Art circuit of FIG. 1.  
         [0023]    Specifically, in the illustrated embodiment, an additional MOSFET MP 5  is connected as a positive feedback element between MP 3 /MP 4  and the central node between MN 1  and MN 2 . More specifically, MP 5 &#39;s source is connected to VDD, the gate of MP 5  is connected to the gates of MP 3  and MP 4 , and the drain of MP 5  is connected to the gate (and drain) of MN 1  and to the gate of MN 2 . The operation of positive feedback element MP 5  in the context of the circuit of FIG. 2 is better understood with reference to the following discussion.  
         [0024]    To improve the current sourcing capability over that of the circuit in FIG. 1, more “headroom” is required for MP 2  and MN 2 . As used herein, “headroom” means the maximum possible voltages across MP 2  and MN 2 . It is desirable to increase these voltages so that they are not as limited as they are in FIG. 1.  
         [0025]    To improve the headroom for MP 2 , the gate voltage of MN 2  is dynamically biased in real time. In this implementation, an active feedback (from MP 3  to MP 5 ) is provided in the circuit in FIG. 2. To simplify the explanation, it is assumed that the sizes of all transistors are the same, except for MP 5 . If IB 2  is arbitrarily set to a portion of IB 1  (FIG. 1), and recognizing the current mirroring properties of the circuit from MP 3  to MN 3 , MP 5  can always be sized to satisfy the condition:  
         
       I 
       MP5 
       +I 
       B2 
       =I 
       MP3 
       =I 
       B1  
     
         [0026]    When V IN  swings an incremental amount ΔV below V B , the current increment is mirrored to reference transistors MP 1  and MN 1 . The current increment forces V GS  of both MP 1  and MN 1  to increase. The gate voltage common to MN 1  and MN 2  increases, thus creating the desired extra “headroom” for MN 2  and MP 2 , hence more V GS  overdrive for both transistors, a basis for ultimately increasing maximum I OUT .  
         [0027]    The feedback through MP 5  is local (internal to the output stage), so that loop delay is minimal and response is fast.  
         [0028]    The maximum achievable sourcing current I OUT  is limited by the supply when the gate of MN 2  is pulled up to the supply rail by the positive feedback MP 5 . The output stage illustrated in FIG. 2 is stable as long as MP 5  is kept smaller than MP 3 , so that the gain of the positive feedback is less than one.  
         [0029]    To verify correct operation of the embodiment of FIG. 2 as compared to the Background Art circuit of FIG. 1, first and second amplifiers designed with TI 0.35 micron CMOS technology with Class AB output stages were simulated with SPICE. The first amplifier AMP_A was implemented with the feedback arrangement of FIG. 2, with feedback current being 75% of the biasing current for reference transistor MP 3 . The second amplifier AMP_B was implemented according to the Background Art circuit of FIG. 1 (without feedback).  
         [0030]    During a first simulation (see FIG. 3A), both amplifiers were set up as unity gain buffers. The output of each amplifier was clamped at 0.6 V, and the input V IN  of each buffer was swept from DC 0.1 V to 1.0 V. The simulation results are shown in FIG. 3B. Although the two amplifiers had identical output voltage, the first amplifier (shown as AMP_A according to the embodiment of FIG. 2) was able to source almost three times more current (shown with points “×” in FIG. 3B) than the second amplifier (shown as AMP_B according to the circuit of FIG. 1 and shown with points “+”). Thus, with the additional active feedback provided in the embodiment of FIG. 2, it has been shown that output stage current sourcing capability is significantly improved.  
         [0031]    [0031]FIG. 4A illustrates an additional simulation setup to determine power supply rejection ratio (PSRR) performance, the simulation result comparison being shown in FIG. 4B. The plots in FIG. 4B are the frequency responses from a small signal analysis simulation, in which the horizontal axis is the frequency of an input (in this case, power supply voltage ripple), and in which the plots represent the ratio of the output to the input at various frequencies. The first amplifier (AMP_A, bottom curve, “×” points) performs better than the second amplifier (AMP_B, top curve, “+” points) because the DC gain of the output stage of the first amplifier is enhanced by the local positive feedback. Improved DC gain results in better PSRR. Thus, the increased maximum source current (I OUT , FIG. 3B) provided by output stages constructed in accordance with the teachings of FIG. 2 is not achieved through compromise of other circuit parameters such as power supply rejection ratio (FIG. 4B). Indeed, PSRR is one additional parameter that is actually improved by addition of positive feedback.  
         [0032]    [0032]FIG. 5 is a simplified schematic diagram illustrating an amplifier  500  that includes a non-inverting input  502 , an inverting input  504 , and an output  506 . Amplifier  500  includes amplifier circuitry  510  that may be conventional in design. However, amplifier  500  has an output stage  520  that may be implemented according to the circuit of FIG. 2. Like the circuit of FIG. 2, output stage  520  has a signal input V IN , a bias input V B , and an output sourcing an output current I OUT  Amplifier  500  may be any suitable amplifier, such as a Class AB amplifier. It may be implemented as the output stage of any larger circuit such as a digital-to-analog converter (DAC).  
         [0033]    From the foregoing, it will be apparent to those skilled in the art that a variety of circuits, apparatus, arrangements, methods, and the like, are provided.  
         [0034]    For example, there is provided an output stage for providing an increased current source output. The output stage has a first circuit element (MP 2 ) that carries a first current that varies in accordance with an input voltage (VIN) and a feedback voltage (gate of MN 2 ) that includes a first voltage across the first circuit element (MP 2 ). The output stage also has a positive feedback arrangement (MP 5 ) that dynamically increases the feedback voltage (gate of MN 2 ) in response to an increase in at least the first current (through MP 2 ), to supplement an increase in the first current beyond that caused by a change in the input voltage alone. The output stage also has a second circuit element (MP 4 ) that provides the increased current source output as a mirror of the first current.  
         [0035]    The first circuit element (MP 2 ) may be a first transistor having a gate that receives the input voltage, the positive feedback arrangement may include a feedback transistor (MP 5 ) having a gate that is connected to a gate of a further transistor (MP 3 ) that carries the first current, and the second circuit element (MP 4 ) may be a second transistor that carries the increased current source output (I OUT ) as a mirror of the first current through the first transistor (MP 2 ).  
         [0036]    The further transistor (MP 3 ) that is a p-channel MOSFET, an n-channel MOSFET (MN 2 ) that receives the feedback voltage, and the first transistor (MP 2 ) that is a p-channel MOSFET, may be connected in series between a voltage source and ground. The second circuit element (MP 4 ) that is a p-channel MOSFET having a gate connected to the further transistor (MP 3 ), and an n-channel MOSFET (MN 3 ) having a gate connected to the gate of the first circuit element (MP 2 ), may be connected in series between the voltage source and the ground.  
         [0037]    The output stage may also have an n-channel reference MOSFET (MN 1 ) having a gate that receives the feedback voltage, as well as a p-channel reference MOSFET (MP 1 ), connected between the n-channel reference MOSFET and ground, and having a gate that receives a bias reference voltage.  
         [0038]    Also provided is a method of providing an increased current source output (I OUT ) from an output stage having a first circuit element (MP 2 ) that carries a first current that varies in accordance with an input voltage (VIN), and a second circuit element (MP 4 ) that provides the increased current source output as a mirror of the first current. The method involves using a positive feedback arrangement (MP 5 ), dynamically increasing a feedback voltage (gate of MN 2 ) that includes a first voltage across the first circuit element (MP 2 ), in response to an increase in at least the first current (through MP 2 ), so as to supplement an increase in the first current beyond that caused by a change in the input voltage alone, so that the current source output (I OUT ) as a mirror of the first current (through MP 2 ) also increases beyond an increase caused by a change in the input voltage alone.  
         [0039]    The step of dynamically increasing the feedback voltage may include connecting a gate voltage of a further transistor (MP 3 ) that carries the first current, to a gate of a feedback transistor (MP 5 ) in the positive feedback arrangement, so that the feedback transistor increases the first voltage across the first circuit element and supplements the increase in the first current beyond that caused by the change in the input voltage alone.  
         [0040]    Also provided is an arrangement for providing an increased current source output (I OUT ) from an output stage having a first circuit element (MP 2 ) that carries a first current that varies in accordance with an input voltage (VIN), and a second circuit element (MP 4 ) that provides the increased current source output as a mirror of the first current. The arrangement includes a positive feedback arrangement (MP 5 ) configured to dynamically increase a feedback voltage (gate of MN 2 ) that includes a first voltage across the first circuit element (MP 2 ), in response to an increase in at least the first current (through MP 2 ), so as to supplement an increase in the first current beyond that caused by a change in the input voltage alone, so that the current source output (I OUT ) as a mirror of the first current (through MP 2 ) also increases beyond an increase caused by a change in the input voltage alone.  
         [0041]    The positive feedback arrangement may include a feedback transistor (MP 5 ) having a gate connected to receive a gate voltage of a further transistor (MP 3 ) that carries the first current, and configured to increase the first voltage across the first circuit element (MP 2 ) and supplement the increase in the first current (through MP 2 ) beyond that caused by the change in the input voltage alone.  
         [0042]    Also provided is an output stage for providing an increased current source output. The output stage has, in series, a current source, a first transistor (MN 1 ) having a gate connected to a central node (gates of MN 1 , MN 2 ), and a second transistor (MP 1 ) having a gate that receives a bias voltage. The output stage also has, in series, a reference transistor (MP 3 ), a third transistor (MN 2 ) having a gate connected to the central node (gates of MN 1 , MN 2 ), and a fourth transistor (MP 2 ) carrying a first current and having a gate receiving an input voltage. The output stage further has, in series, a current sourcing transistor (MP 4 ) having a gate connected to the gate of the reference transistor, and a current sinking transistor (MN 3 ) having a gate connected to the input voltage. The output stage additionally has a feedback transistor (MP 5 ) that dynamically increases a feedback voltage at the central node (gates of MN 1 , MN 2 ) in response to an increase in at least the first current (through MP 2 ), to supplement an increase in the first current beyond that caused by a change in the input voltage alone, so that the current sourcing transistor (MP 4 ) provides the increased current source output as a mirror of the first current.  
         [0043]    Also provided is an amplifier having the output stage described above.  
         [0044]    The foregoing embodiments are merely examples and are not to be construed as limiting the invention. The description of the embodiments is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the above teachings. For example, the choice of transistors other than MOSFETs, or of different conductivity types, or of different circuit configurations, lie within the scope of the present invention. It is therefore to be understood that within the scope of the appended claims and their equivalents, the invention may be practiced otherwise than as specifically described herein.