Abstract:
A column of ternary content addressable memory (TCAM) cells includes a bit line pair that is twisted at a location at or near the center of the column. Data is written to (and read from) TCAM cells located above the twist location with a first bit line polarity. Data is written to (and read from) TCAM cells located below the twist location with a second bit line polarity, opposite the first bit line polarity. As a result, read leakage currents introduced by TCAM cells storing ‘Don&#39;t Care’ values are reduced.

Description:
FIELD OF THE INVENTION 
     The present invention relates to ternary content addressable memory (TCAM) cells. More specifically, the present invention relates an improved read structure for a column of TCAM cells. 
     RELATED ART 
       FIG. 1  is a circuit diagram of a conventional ternary content addressable memory (TCAM) cell  100 . As defined herein, a TCAM cell is capable of storing three logic values, including a logic ‘1’ value, a logic ‘0’ value and a ‘Don&#39;t Care’ value. TCAM cell  100  includes static random access memory (SRAM) cells  101 - 102  and match logic  103 . SRAM cell  101  includes PMOS transistors  111 - 112  and NMOS transistors  113 - 114 , which are configured to form a latch circuit  110 , and NMOS transistors  115 - 116 , which provide access to latch circuit  110 . Similarly, SRAM cell  102  includes PMOS transistors  121 - 122  and NMOS transistors  123 - 124 , which are configured to form a latch circuit  120 , and NMOS transistors  125 - 126 , which provide access to latch circuit  120 . Match logic  103  includes NMOS transistors  131 - 134  and match line ML, which are connected as illustrated. 
     Data is written to SRAM cell  101  by applying a data value on complementary bit lines B/B# and activating the word line signal WL 1 . Similarly, data is written to SRAM cell  102  by applying a data value to complementary bit lines B/B# and activating the word line signal WL 2 . The data value written to SRAM cell  101  is stored on nodes X and X′ of latch circuit  110 . Similarly, the data value written to SRAM cell  102  is stored on nodes Y and Y′ of latch circuit  120 . Thus, a logic ‘1’ data value written to SRAM cell  101  will result in node X being pulled up to a positive supply voltage (V DD ) through PMOS transistor  111 , and node X′ being pulled down to ground through NMOS transistor  114 . Conversely, a logic ‘0’ data value written to SRAM cell  101  will result in node X being pulled down to ground through NMOS transistor  113 , and node X′ being pulled up to the V DD  supply voltage through PMOS transistor  112 . SRAM cell  102  stores data in the same manner as SRAM cell  101  (i.e., Y=V DD , Y′=0 represents logic ‘1’; and Y=0, Y′=V DD  represents logic ‘0’.) 
     The data values stored by SRAM cells  101  and  102  specify the data value stored by TCAM cell  100 . For example, when SRAM cell  101  stores a logic ‘1’ data value and SRAM cell  102  stores a logic ‘0’ data value, TCAM cell  100  stores a logic ‘1’ data value. Conversely, when SRAM cell  101  stores a logic ‘0’ data value and SRAM cell  102  stores a logic ‘1’ data value, TCAM cell  100  stores a logic ‘0’ data value. When SRAM cells  101  and  102  both store a logic ‘0’ data value, TCAM cell  100  stores a ‘Don&#39;t Care’ value. An invalid state exists if SRAM cells  101  and  102  both store a logic ‘1’ data value. That is, SRAM cells  101  and  102  do not store logic ‘1’ data values at the same time during the normal operation of TCAM cell  100 . 
     The data values stored by SRAM cells  101  and  102  are provided to match logic  103 . More specifically, nodes X and Y of SRAM cells  101  and  102  are connected to the gates of NMOS transistors  131  and  132 , respectively. A search operation is performed by TCAM cell  100  as follows. The match line ML is initially precharged to a logic high voltage. A search value is then applied to complementary search lines S/S#. A search value of ‘0’ is applied by pulling down the search line S to a logic low voltage and pulling up the complementary search line S# to a logic high voltage. Conversely, a search value of ‘1’ is applied by pulling up the search line S to a logic high voltage and pulling down the complementary search line S# to a logic low voltage. 
     If the data stored by TCAM cell  100  matches the applied search value, or the TCAM cell  100  stores a ‘Don&#39;t 
     Care’ value, then the match line ML will remain in the precharged state. That is, at least one of the transistors  131  and  133  will be turned off, and at least one of the transistors  132  and  134  will also be turned off, thereby preventing the match line ML from discharging to ground. However, if the data stored by TCAM cell  100  does not match the applied search value, the match line ML is discharged, thereby indicating a non-match condition. Under these conditions, either transistors  131  and  133  will be turned on, or transistors  132  and  134  will be turned on, thereby providing a discharge path from the match line ML to ground. 
     The data stored in TCAM cell  100  is read by reading the contents of SRAM cells  101  and  102 . A read operation is performed to SRAM cell  101  in the following manner. Bit lines B and B# are pre-charged to the V DD  supply voltage, and a logic high read voltage (e.g., V DD ) is applied to the corresponding word line WL 1 . Under these conditions, NMOS access transistors  115 - 116  turn on, thereby coupling nodes X and X′ to bit lines B and B#, respectively. One of these nodes X or X′ is pulled down toward the ground supply voltage, depending on the data value stored by SRAM cell  101 . For example, if a logic ‘1’ data value is stored by SRAM cell  101 , then NMOS transistor  114  is turned on, thereby pulling the voltage on node X′ down toward the ground supply voltage. Under these conditions, the voltage of the complementary bit line B# will be pulled down toward ground through the conductive path that exists through turned on NMOS transistors  114  and  116 . Note that the low voltage on node X′ turns on PMOS transistor  111  and turns off NMOS transistor  113 , such that the pre-charged bit line B is not pulled down toward the ground supply voltage. The voltage difference between bit lines B and B# is sensed to identify the state of the data value stored by SRAM cell  101 . 
     While SRAM cell  101  is being read, a logic low voltage (e.g., ground) is applied to the word line WL 2 , such that the NMOS access transistors  125 - 126  of SRAM cell  102  are turned off. However, one of the nodes Y or Y′ of SRAM cell  102  will be pulled down toward the ground supply voltage, depending on the data value stored by SRAM cell  102 . For example, if a logic ‘0’ data value is stored by SRAM cell  102 , then NMOS transistor  123  is turned on, thereby pulling the voltage on node Y down toward the ground supply voltage. Under these conditions, a small leakage current will exist through NMOS access transistor  125 , wherein this small leakage current will tend to pull the voltage on the corresponding bit line B down toward the ground supply voltage. However, this small leakage current, by itself, is not sufficient to disrupt the read operation to SRAM cell  101 . As process technologies result in smaller devices, transistor leakage currents increase. If enough leakage current is introduced, (e.g., by other CAM cells coupled to bit lines B and B#), the voltage difference developed between bit lines B and B# may become too small to reliably read the contents of the SRAM cell  101 . 
       FIG. 2  is a block diagram illustrating a conventional column  201  of 500 TCAM cells  200   0 ,  200   1 ,  200   2 , . . .  200   499 , each of which is identical to TCAM cell  100 . Note that only portions of TCAM cells  200   0 - 200   499  are illustrated for purposes of clarity. In the illustrated example, TCAM cell  200   0  stores a logic ‘1’ data value (i.e., X=V DD , X′=0, Y=0, Y′=V DD ), and each of the other CAM cells  200   1 - 200   499  in the column stores a ‘Don&#39;t Care’ value (i.e., X=0, X′=V DD , Y=0, Y′=V DD ). This pattern represents the worst case conditions for a read operation to the SRAM cell  101  of TCAM cell  200   0 . As described above, a read operation to SRAM cell  101  will cause node X′ to pull down the voltage on the complementary bit line B#. However, the leakage currents associated with the other 999 SRAM cells in column  201  will tend to pull down the voltage on the bit line B. As a result, the voltage difference between bit lines B and B# may be relatively small, thereby rendering the read result unreliable. In addition, the read speed may be slow, as a relatively long time is required for a maximum voltage difference to be developed and sensed on the bit lines B and B#. To obtain an acceptable read speed, the column may need to be made shorter. However, by making the column shorter, a larger number of columns is necessary to maintain the same capacity. This undesirably results in an increase in layout area due to the additional accessing circuits required to access the additional columns. 
     It would therefore be desirable to have an improved TCAM column structure that mitigates the above-described problems. 
     SUMMARY 
     Accordingly, the present invention provides a TCAM column structure that includes a plurality of TCAM cells arranged in a column. A bit line pair is connected to each of the TCAM cells in the column, wherein data is written to and read from the TCAM cells on the bit line pair. The bit line pair is twisted at a location at (or near) the middle of the column, such that an equal (or approximately equal) number of TCAM cells are located above and below the bit line twist location. 
     Data is written to (and read from) the TCAM cells located above the twist location with a first bit line polarity. Data is written to (and read from) the TCAM cells located below the twist location with a second bit line polarity, opposite the first bit line polarity. As a result, ‘Don&#39;t Care’ values stored in TCAM cells located above the twist location will introduce leakage current on a first bit line of the bit line pair during read operations, and ‘Don&#39;t Care’ values stored in TCAM cells located below the twist location will introduce leakage current on a second bit line of the bit line pair during read operations. Consequently, the read leakage current introduced by a TCAM cell that stores a ‘Don&#39;t Care’ value and is located above the twist location is offset by the read leakage current introduced by a TCAM cell that stores a ‘Don&#39;t Care’ value and is located below the twist location. Thus, the worst case condition for read operations exists when one half of the TCAM cells in the column store ‘Don&#39;t Care’ values. 
     The present invention will be more fully understood in view of the following description and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a circuit diagram of a conventional ternary content addressable memory cell. 
         FIG. 2  is a block diagram of a conventional column of ternary content addressable memory cells. 
         FIG. 3  is a block diagram of a column of ternary content addressable memory cells in accordance with one embodiment of the present invention. 
         FIG. 4  is a block diagram of write control logic that recognizes and applies first and second bit line polarities during write operations, in accordance with one embodiment of the present invention. 
         FIG. 5  is a block diagram of read control logic that recognizes and applies first and second bit line polarities during read operations, in accordance with one embodiment of the present invention. 
         FIG. 6  is a circuit diagram of a column of TCAM cells in accordance with an alternate embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 3  is a block diagram illustrating a column  301  of N TCAM cells  300   0 - 300   (N−1) , each of which is identical to TCAM cell  100  ( FIG. 1 ). Similar elements in  FIGS. 1 and 3  are labeled with similar reference numbers. Thus, each TCAM cell  300   z  includes corresponding SRAM cells  101 - 102  and match logic  103 . Note that word lines are not shown in  FIG. 3  for purposes of clarity. Within  FIG. 3 , the storage nodes of each TCAM cell  300   z  are labeled XZ, XZ′, YZ and YZ′, wherein Z includes the integers from 0 to N−1, inclusive. For example, TCAM cell  300   0  includes storage nodes X 0 , X 0 ′, Y 0  and Y 0 ′. 
     The SRAM cells within TCAM cells  300   0 - 300   (N−1)  are connected to a complementary bit line pair, which includes bit lines B and B#. In accordance with one embodiment of the present invention, bit lines B and B# are twisted at a location  302  between the top and bottom of the column  301 . That is, for TCAM cells above twist location  302 , the storage nodes XZ and YZ are coupled to bit line B through the corresponding access transistors  115  and  125 , and the storage nodes XZ′ and YZ′ are coupled to the complementary bit line B# through the corresponding access transistors  116  and  126 . However, for TCAM cells below twist location  302 , the storage nodes XZ′ and YZ′ are coupled to bit line B through the corresponding access transistors  116  and  126 , and the storage nodes XZ and YZ are coupled to the complementary bit line B# through the corresponding access transistors  115  and  125 . 
     In the illustrated example, bit lines B and B# are twisted at the half-way point of the column  301 , such that TCAM cells  300   0 - 300   (N/2−1)  are located above the twist location  302 , and TCAM cells  300   (N/2) - 300   (N−1)  are located below the twist location  302 . In other embodiments, twist location  302  may be located at other positions along column  301 . As described in more detail below, twisting the bit lines B/B# advantageously minimizes the adverse affect of leakage current on read operations within column  301 . 
     The match logic  103  within each of TCAM cells  300   0 - 300   (N−1)  is coupled to a complementary search line pair, which includes search line S and complementary search line S#. It is important to note that the search lines S and S# are not twisted in the present embodiment. Search operations are performed in the same manner described above in connection with  FIG. 1 . 
     Column  301  is operated as follows in accordance with one embodiment of the present invention. TCAM cells  300   0 - 300   (N/2−1) , which are located above the bit line twist location  302  (e.g., in the top half of column  301 ), are written with a first bit line polarity. Conversely, TCAM cells  300   (N/2) - 300   (N−1) , which are located below the bit line twist location  302  (i.e., in the bottom half of column  301 ) are written with a second bit line polarity, opposite the first bit line polarity. 
     In accordance with one embodiment, the first bit line polarity is defined by the following example. To write a logic ‘1’ value to the SRAM cells  101 - 102  within upper TCAM cells  300   0 - 300   (N/2−1) , a logic high voltage (V DD ) is applied to bit line B and a logic low voltage (0 Volts) is applied to complementary bit line B# (and the corresponding word line is activated). Conversely, to write a logic ‘0’ value to the SRAM cells  101 - 102  within upper TCAM cells  300   0 - 300   (N/2−1) , a logic low voltage (0 Volts) is applied to bit line B and a logic high voltage (V DD ) is applied to complementary bit line B# (and the corresponding word line is activated). Thus, in the example illustrated by  FIG. 3 , SRAM cell  101  of TCAM cell  300   0  stores a logic ‘1’ data value (i.e., X 0 =V DD  and X 0 ′=0), and SRAM cell  102  of TCAM cell  300   0  stores a logic ‘0’ data value (i.e., Y 0 =0 and Y 0 ′=V DD ). 
     In accordance with the present embodiment, the second bit line polarity is defined by the following example. To write a logic ‘1’ value to the SRAM cells  101 - 102  within lower TCAM cells  300   (N/2) - 300   (N−1) , a logic low voltage (0 Volts) is applied to bit line B, and a logic high voltage (V DD ) is applied to complementary bit line B# (and the corresponding word line is activated). Conversely, to write a logic ‘0’ value to the SRAM cells  101 - 102  within lower TCAM cells  300   (N/2) - 300   (N−1) , a logic high voltage (V DD ) is applied to bit line B and a logic low voltage (0 Volts) is applied to complementary bit line B# (and the corresponding word line is activated). Thus, in the example illustrated by  FIG. 3 , SRAM cell  101  of TCAM cell  300   (N/2)  stores a logic ‘1’ data value (i.e., X(N/2)=V DD  and X(N/2)′=0), and SRAM cell  102  of TCAM cell  300   (N/2)  stores a logic ‘0’ data value (i.e., Y(N/2)=0 and Y(N/2)′=V DD ). 
     A logic ‘1’ data value is written within each of the TCAM cells  300   0 - 300   (N−1)  by writing a logic ‘1’ value to the corresponding SRAM cell  101  and writing a logic ‘0’ value to the corresponding SRAM cell  102 . Thus, in the example illustrated by  FIG. 3 , TCAM cells  300   0  and  300   (N/2)  each store a logic ‘1’ data value. 
     Conversely, a logic ‘0’ data value is written within each of the TCAM cells  300   0 - 300   (N−1)  by writing a logic ‘0’ value to the corresponding SRAM cell  101  and writing a logic ‘1’ value to the corresponding SRAM cell  102 . Thus, in the example illustrated by  FIG. 3 , TCAM cell  300   (N−1)  stores a logic ‘0’ data value. 
     A ‘don&#39;t care’ value is written within each of the TCAM cells  300   0 - 300   (N−1)  by writing a logic ‘0’ value to the corresponding SRAM cells  101  and  102 . Thus, in the example illustrated by  FIG. 3 , TCAM cell  300   (N/2−1)  stores a ‘Don&#39;t Care’ value. 
       FIG. 4  is a block diagram of write control logic  400  that recognizes and applies the above-described first and second bit line polarities during write operations, in accordance with one embodiment of the present invention. Write control logic  400  includes exclusive OR circuit  401  and write driver  402 . Exclusive OR circuit  401  receives the write data value DIN to be written to the TCAM cell in column  301 . Exclusive OR circuit  401  also receives the most significant bit (MSB) of the corresponding write address (W_ADDR). The MSB of the write address indicates whether the write operation will be performed to a TCAM cell in the upper half of the column  301 , above the twist location  302  (i.e., W_ADDR[MSB]=0), or a TCAM cell in the lower half of the column  301 , below the twist location  302  (i.e., W_ADDR[MSB]=1). If the write operation is to be performed to a TCAM cell in the upper half of the column  301 , exclusive OR circuit  402  provides the write data value DIN to write driver  401  as the write data signal W_DATA. However, if the write operation is to be performed to a TCAM cell in the lower half of the column  301 , exclusive OR circuit  402  provides the inverse of the write data value DIN to write driver  401  as the write data signal W_DATA. Write driver  401  drives the bit lines B and B#, such that the bit line B is driven to a voltage that represents the same logic state as the write data signal W_DATA, and the complementary bit line B# is driven to a voltage that represents the opposite logic state. In this manner, write control logic  400  maintains the first and second bit line polarities described above. 
     The TCAM cells in column  301  are read as follows in accordance with one embodiment of the present invention. TCAM cells  300   0 - 300   (N/2−1) , which are located above the bit line twist location  302  (e.g., in the top half of column  301 ), are read with the first bit line polarity. Conversely, TCAM cells  300   (N/2) - 300   (N−1) , which are located below the bit line twist location  302  (i.e., in the bottom half of column  301 ) are read with the second bit line polarity. 
     To identify the state of a TCAM cell, each of the associated SRAM cells  101  and  102  is read. Each SRAM cell is read in the following manner. Bit lines B/B# are initially precharged to a logic high voltage (V DD ), and the access transistors of the corresponding SRAM cell are turned on by activating the corresponding word line. Under these conditions, the one of the storage nodes of the SRAM cell will pull the corresponding bit line down toward ground, and the other one of the storage nodes of the SRAM cell will pull the corresponding bit line up toward V DD . As a result, a voltage difference is created across the bit line pair B/B#. This voltage difference is detected by a sense amplifier (not shown). 
     In accordance with the present embodiment, if the TCAM cell being read is above the bit line twist location  302  (i.e., in the upper half of column  301 ), then the first bit line polarity is used to identify the read data value. That is, a logic high voltage on bit line B and a logic low voltage on complementary bit line B# is recognized and reported as a logic ‘1’ data value; and a logic low voltage on bit line B and a logic high voltage on complementary bit line B# is recognized and reported as a logic ‘0’ data value. 
     Conversely, if the TCAM cell being read is below the bit line twist location  302  (i.e., in the lower half of column  301 ), then the second bit line polarity is used to identify the read data value. That is, a logic high voltage on bit line B and a logic low voltage on complementary bit line B# is recognized and reported as a logic ‘0’ data value; and a logic low voltage on bit line B and a logic high voltage on complementary bit line B# is recognized and reported as a logic ‘1’ data value. 
       FIG. 5  is a block diagram of read control logic  500  that recognizes and applies the above-described first and second bit line polarities during read operations, in accordance with one embodiment of the present invention. Read control logic  500  includes sense amplifier  501 , which amplifies the voltage difference between the bit lines B/B# during a read operation. Sense amplifier  501  provides a read data signal (R_DATA) having the logic state represented by the voltage developed on bit line B. The read data signal R_DATA is provided to exclusive OR circuit  502 , along with the most significant bit (MSB) of the corresponding read address (R_ADDR). The MSB of the read address indicates whether the read operation is performed from a TCAM cell in the upper half of the column  301 , above the twist location  302  (i.e., R_ADDR[MSB]=0), or a TCAM cell in the lower half of the column  301 , below the twist location  302  (i.e., R_ADDR[MSB]=1). If the read operation was performed from a TCAM cell in the upper half of the column  301 , exclusive OR circuit  502  provides the read data signal R_DATA as the read data value DOUT. However, if the read operation was performed from a TCAM cell in the lower half of the column  301 , exclusive OR circuit  502  provides the inverse of the read data signal R_DATA as the read data value DOUT. In this manner, read control logic  500  maintains the first and second bit line polarities described above. 
     In the present embodiment, worst case read conditions will exist when one of the TCAM cells in a first half of the column  301  stores a logic ‘1’ data value, the remaining TCAM cells in the same half of the column  301  store ‘Don&#39;t Care’ values, and the TCAM cells in the other half of the column  301  do not store ‘Don&#39;t Care’ values. Under these conditions, the leakage current during the read operation is equal to the leakage current through N−1 SRAM cells (compared to 2N−1 SRAM cells in the prior art TCAM column structure of  FIG. 2 ). 
     For example, assume that there are 500 TCAM cells in column  301 . Worst case read conditions would exist, for example, if TCAM cell  300   0  stores a logic ‘1’ data value (as illustrated in  FIG. 3 ), TCAM cells  300   1 - 300   249  store ‘Don&#39;t Care’ values (as illustrated by TCAM cell  300   (N/2−1)  in  FIG. 3 ), and TCAM cells  300   250 - 300   499  store logic ‘1’ data values (as illustrated by TCAM cell  300   (N/2)  in  FIG. 3 ) and/or logic ‘0’ data values (as illustrated by TCAM cell  300   (N−1)  in  FIG. 3 ). Under these conditions, a read operation to SRAM cell  101  of TCAM cell  300   0  will result in node X 0 ′ pulling bit line B# down toward ground. However, the leakage current through the SRAM cell  102  within TCAM cell  300   0 , and the leakage currents through all of the SRAM cells  101 - 102  within TCAM cells  300   1 - 300   249  will tend to pull down the voltage on bit line B. That is, each of the SRAM cells  101 - 102  in the upper half of the column  301  (except for the SRAM cell being read) will contribute to the total leakage current. 
     However, the leakage currents through the SRAM cells  101 - 102  within TCAM cells  300   250 - 300   499  in the lower half of the column  301  will be equally split between bit lines B and B#, such that the net effect of these leakage currents does not affect the voltage difference developed across bit lines B and B#. For example, within TCAM cell  300   250 , SRAM cell  101  will have a leakage current through transistor  116  that tends to pull down the voltage on bit line B, while SRAM cell  102  will have an opposing leakage current through transistor  125  that tends to pull down the voltage on complementary bit line B#. 
     Note that if the TCAM cells  300   250 - 300   499  in the lower half of column  301  were written with ‘Don&#39;t Care’ values, the associated leakage currents would tend to pull down the voltage on complementary bit line B#, thereby substantially offsetting the leakage currents associated with TCAM cells  300   0 - 300   249 , which tend to pull down the voltage on bit line B. 
     Also note that it is invalid to write logic ‘1’ values to both of the SRAM cells  101 - 102  in TCAM cells  300   250 - 300   499 , thereby eliminating the worst case read conditions of the prior art. 
       FIG. 6  is a circuit diagram of a column  601  of TCAM cells  300   0 - 300   (N/2-1) ,  600   (N/2) - 600   (N−1)  in accordance with an alternate embodiment of the present invention. TCAM cells  300   0 - 300   (N/2−1)  have been described above in connection with  FIG. 3 . TCAM cells  600   (N/2) - 600   (N−1)  are similar to TCAM cells  300   (N/2) - 300   (N−1) , and are therefore labeled with similar reference numbers. However, TCAM cells  600   (N/2) - 600   (N−1)  are mirror images of TCAM cells  300   (N/2) - 300   (N−1) . In this embodiment, neither search lines S and S# nor bit lines B and B# are twisted. Read and write operations to TCAM cells  300   0 - 300   (N/2−1)  (which are located above location  302 ) are performed with the first bit line polarity, and read and write operations to TCAM cells  600   (N/2) - 600   (N−1)  (which are located below location  302 ) are performed with the second bit line polarity. In the illustrated example, TCAM cell  600   (N/2)  stores a logic ‘0’ data value (i.e., X(N/2)=0, X(N/2)′=V DD , Y(N/2)=V DD , Y(N/2)′=0), and TCAM cell  600   (N−1)  stores a ‘don&#39;t’ care° value (i.e., X(N−1)=0, X(N−1)′=V DD , Y(N−1)=0, Y(N−1)′=V DD ). Column  601  exhibits the same worst case read conditions as column  301 . 
     Although the present invention has been described in connection with various embodiments, it is understood that variations of these embodiments would be obvious to one of ordinary skill in the art. For example, although the present invention has been described in accordance with a column of TCAM cells, it is understood that the teachings of the present disclosure can be extended to multiple columns (i.e., an array) of TCAM cells. Moreover, although the present invention has been described in connection with bit lines that are twisted one time within a column, it is understood that bit lines may be twisted multiple times within a column (while implementing the teachings of the present invention for each additional bit line twist) to offset cross-talk noise from neighboring columns in other embodiments. Thus, the present invention is limited only by the following claims.