Abstract:
A differential amplifier circuit includes a first differential transistor pair, a second differential transistor pair, an adder section and an amplifying unit. The first differential transistor pair receives first and second input signals and an output signal as a third input signal, and the second differential transistor pair receives the first and second input signals and the output signal as a fourth input signal. The adder section adds first output signals from the first differential transistor pair and second output signals from the second differential transistor pair, and the amplifying unit amplifies an addition resultant signal from the adder section to output to the first and second differential transistor pairs.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a differential amplifier. More specifically, the present invention is directed to a differential amplifier used in an amplifying circuit of an LCD driver for driving a capacitive load.  
         [0003]     2. Description of the Related Art  
         [0004]     Nowadays, there is a trend that higher gradation is strongly required in a TFT-LCD (Thin-Film Transistor Liquid Crystal Display) field. That is to say, conventionally, 260,000-color display (64 gradation levels in 6 bits) sufficiently satisfied requirements of the TFT-LCD field. However, currently, 16,780,000-color display (256 gradation levels in 8 bits) is requested in the TFT-LCD field. Moreover, display of 1,024 gradation levels in 10 bits is requested depending on fields. For instance, such a higher gradation display is requested for X-ray image display in a medical field and TV display field. When such a higher gradation display is achieved, an LCD driver circuit becomes more complicated. For example, such a LCD driver is disclosed in Japanese Laid Open Patent Application (JP-P2001-34234A). In this LCD driver, furthermore, a chip area of the driver circuit is increased, resulting in higher cost.  
         [0005]      FIG. 1  is a block diagram showing a partial circuit of a conventional LCD driver in which operational amplifiers having two non-inversion inputs are used. Referring now to  FIG. 1 , the conventional LCD driver is composed of a latch address selector  101 , a latch circuit  102 , n (n is an integer more than 1) decoders  103 , and n operational amplifiers  104 . Each of these operational amplifiers  104  has two non-inversion inputs, and constitutes a voltage follower circuit.  
         [0006]     Input data D 0  to D 8  corresponding to 8-bit display data are supplied to the latch circuit  102 . Outputs of the latch circuit  102  are supplied to the respective decoders  103 . Each of these decoders  103  has two voltage output terminals (Vin 1  and Vin 2 ). Voltage outputs (Vin 1 /Vin 2 ) from the two voltage output terminals of each decoder  103  are supplied to a corresponding one of the operational amplifiers  104 . In this circuit, 8-bit 256-gradation voltages are not supplied to one decoder  103 , but 129-gradation (=256/2+1) voltages are supplied to the decoder  103 . A voltage between the adjacent two voltages is interpolated by the operational amplifiers  104 , and 8-bit 256-gradation voltages are outputted as a final output from the operational amplifiers  104 .  
         [0007]      FIG. 2  is a diagram showing a specific circuit arrangement of one operational amplifier  104  having two non-inversion inputs shown in  FIG. 1 . Referring to  FIG. 2 , in the operational amplifier  104 , two MOS transistors on an input side are grouped, and one output (Vout) is generated to the two input voltages (Vin 1 , Vin 2 ). The output voltage (Vout) is V 2  in case where the input voltages (Vin 1  and Vin 2 ) are equal to a same gradation voltage (for instance, Vin 1 =Vin 2 =V 2 ). In case where the input voltages (Vin 1  and Vin 2 ) are adjacent gradation voltages (for instance, Vin 1 =V 0  and Vin 2 =V 2 ), the output (Vout) is substantially equal to an intermediate voltage V 1  obtained by combining V 0  with V 2 .  
         [0008]     In the 2-input amplifier employed in the conventional driver circuit as shown in  FIG. 2 , when a difference between the two input voltages Vin 1  and Vin 2  is relatively small, the output voltage (Vout) is obtained as follows: 
 
 Vout =( Vin   1 + Vin   2 )/2. 
 
 However, when a difference between the two input voltages becomes large, a deviation from (Vin 1 +Vin 2 )/2 becomes larger. 
 
         [0009]     Thus, a high precision driver circuit is desirable without requiring a complex circuit arrangement.  
         [0010]     In conjunction with the above description, an interpolation type D-A converter is disclosed in Japanese Laid Open Patent Application (JP-P2001-313568A, see  FIG. 10  of this conventional example). This conventional example is used for a TFT LCD driver which is composed of a reference voltage generation circuit which generates a plurality of reference voltages. At least one decoding switch receives the plurality of reference voltages from the reference voltage generation circuit and selects two of the plurality of reference voltages based on a plurality of high bits of a digital image signal. A routing switch is connected with the decoding switch and generates first and second reference voltages based a plurality of low bits of the digital image signal. An interpolation buffer is connected with the routing switch and generates an interpolation analog signal based on the first and second reference voltages.  
         [0011]     Also, a driver circuit is disclosed in Japanese Laid Open Patent Application (JP-P2001-343948A). In this conventional example, a gradation voltage generating circuit generates a plurality of gradation voltages which are different in voltage level from each other. A decoder decodes an input data and selects first and second gradation voltages from the plurality of gradation voltages based on the decoding result. An amplifier generates a drive voltage based on the first and second gradation voltages. The amplifier is composed of a first transistor for a differential pair, a second transistor connected with the first transistor for the differential pair, a third transistor connected in parallel to the second transistor, and a switch circuit. The switch circuit carries out a switching operation in a predetermined period between a first state in which the first gradation voltage is transferred to the first transistor and the second gradation voltage is transferred to the second transistor, and a second state in which the second gradation voltage is transferred to the first transistor and the first gradation voltage is transferred to the second transistor.  
       SUMMARY OF THE INVENTION  
       [0012]     An object of the present invention is to provide a high-precision LCD driver circuit with a simple circuit arrangement.  
         [0013]     Another object of the present invention is to provide an operational amplifier having two input terminals, and capable of correctly outputting an averaged voltage of two different voltages which are supplied to the two input terminals.  
         [0014]     In an aspect of the present invention, a differential amplifier circuit includes a first differential transistor pair, a second differential transistor pair, an adder section and an amplifying unit. The first differential transistor pair receives first and second input signals and an output signal as a third input signal, and the second differential transistor pair receives the first and second input signals and the output signal as a fourth input signal. The adder section adds first output signals from the first differential transistor pair and second output signals from the second differential transistor pair, and the amplifying unit amplifies an addition resultant signal from the adder section to output to the first and second differential transistor pairs.  
         [0015]     Here, the first differential transistor pair may include first and second P-channel transistors having sources which are commonly connected, gates which respectively receive the first and second input signals, and drains which are commonly connected; and third and fourth P-channel transistors having sources which are commonly connected with the sources of the first and second P-channel transistors, gates which commonly receive the output signal, and drains which are commonly connected. The second differential transistor pair may include fifth and sixth N-channel transistors having source which are commonly connected, gates which respectively receive the first and second input signals, and drains which are commonly connected; and seventh and eighth N-channel transistors having sources which are commonly connected with the sources of the fifth and sixth N-channel transistors, gates which commonly receive the output signal, and drains which are commonly connected. The first output signals are respectively outputted from the drains of the first and second P-channel transistors and the drains of the third and fourth P-channel transistors, and the second output signals are respectively outputted from the drains of the fifth and sixth N-channel transistors and the drains of the seventh and eighth N-channel transistors.  
         [0016]     In this case, the adder section may include first to third current mirror circuit. The first current mirror circuit is connected with the first differential transistor pair to receive the first output signals; and the second current mirror circuit is connected with the second differential transistor pair and outputs one of the second output signals to one of transistors of the first current mirror circuit. The third current mirror circuit is connected with the second differential transistor pair and outputs the other of the second output signals to the other of the transistors of the first current mirror circuit.  
         [0017]     Also, the differential amplifier may further include first and second constant current sources. In this case, the first and second P-channel transistors are connected in parallel to each other and the sources of the first and second P-channel transistors are connected with the first constant current source, and the drains of the first and second P-channel transistors are commonly connected with one of transistors of the first current mirror circuit to output one of the first output signals to the one transistor of the first current mirror circuit. The third and fourth P-channel transistors are connected in parallel to each other and the sources of the third and fourth transistors are connected with the first constant current source, and the drains of the third and fourth transistors are commonly connected with the other of transistors of the first current mirror circuit to output the other of the first output signals to the other transistor of the first current mirror circuit. The fifth and sixth N-channel transistors are connected in parallel to each other and the source of the fifth and sixth N-channel transistors are connected with the second constant current source, and the drains of the fifth and sixth N-channel transistors are commonly connected with one of transistors of the second current mirror circuit. The seventh and eighth N-channel transistors are connected in parallel to each other and the sources of the seventh and eighth N-channel transistors are connected with the second constant current source, and the drains of the seventh and eighth N-channel transistors are commonly connected with one of transistors of the third current mirror circuit. One of the second output signals is supplied from the other transistor of the second current mirror circuit to the other transistor of the first current mirror circuit, and the other of the second output signals is supplied from the other transistor of the third current mirror circuit to the one transistor of the first current mirror circuit.  
         [0018]     Also, the adder section may include fourth and fifth current mirror circuits and a floating constant current source section. The fourth current mirror circuit receives the second output signals, and the fifth current mirror circuit receives the first output signals. The floating constant current source section is connected between the fourth and fifth current mirror circuits. The amplifying unit is driven based on a third output signal from the fourth current mirror circuit and a fourth output signal from the fifth current mirror circuit to output the addition resultant signal.  
         [0019]     In this case, each of the fourth and fifth current mirror circuits may be of a cascode connection type.  
         [0020]     Also, the floating constant current source section may include a first current source section which comprises a P-channel MOS transistor and an N-channel MOS transistor which are connected in parallel and is connected between one side of the fourth current mirror circuit and one side of the fifth current mirror circuit; and a second current source section which comprises a P-channel MOS transistor and an N-channel MOS transistor which are connected in parallel and is connected between the other side of the fourth current mirror circuit and the other side of the fifth current mirror circuit.  
         [0021]     Also, the amplifying unit may include a P-channel MOS transistor and an N-channel MOS transistor which are connected in series. The P-channel MOS transistor and the N-channel MOS transistor of the output stage circuit receive as the addition resultant signal, the third output signal from the fourth current mirror circuit and the fourth output signal from the fifth current mirror circuit respectively, and the output signal is outputted from a node between the P-channel MOS transistor and the N-channel MOS transistor of the output stage circuit.  
         [0022]     Also, the floating constant current source section may include a first current source section which comprises a P-channel MOS transistor and an N-channel MOS transistor which are connected in parallel and is connected between one side of the fourth current mirror circuit and one side of the fifth current mirror circuit.  
         [0023]     In this case, the amplifying unit may include a P-channel MOS transistor and an N-channel MOS transistor which are connected in series. The P-channel MOS transistor and the N-channel MOS transistor of the output stage circuit receive as the addition resultant signal, the third output signal from the fourth current mirror circuit and the fourth output signal from the fifth current mirror circuit respectively, and the output signal is outputted from a node between the P-channel MOS transistor and the N-channel MOS transistor of the output stage circuit.  
         [0024]     Also, a mobility of each of the first to fourth P-channel MOS transistors is μ P , and a mobility of each of the fifth to eighth N-channel MOS transistors is μ N , a ratio of a gate width W of each of the first to fourth P-channel MOS transistors to a gate length L thereof is:  
         W   L     ⁢     |   P         
 
 a ratio of a gate width W of each of the fifth to eighth N-channel MOS transistors to a gate length L thereof is:  
         W   L     ⁢     |   N         
 
 when a gate oxide film capacitance per unit area of each of the first to fourth P-channel MOS transistors and the fifth to eighth N-channel MOS transistors is C 0 , β P  and β N  indicated by the following equations satisfy a relation of β P =β N :  
               β   P     =       W   L     ⁢     |   P     ⁢       μ   P     ⁢     C   o                       β   N     =       W   L     ⁢     |   N     ⁢       μ   N     ⁢     C   o                   
 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0025]      FIG. 1  is a schematic block diagram showing the circuit arrangement of a conventional LCD source driver;  
         [0026]      FIG. 2  is a diagram showing an example of a specific circuit of a conventional amplifier employed in the LCD source driver;  
         [0027]      FIG. 3  is a circuit diagram showing a two-input amplifier according to a first embodiment of the present invention;  
         [0028]      FIG. 4  is a diagram showing an example of a specific circuit of a differential stage employed in the 2-input amplifier of  FIG. 3 ;  
         [0029]      FIG. 5  is a diagram showing another example of a specific circuit of the differential stage employed in the 2-input amplifier of  FIG. 3 ;  
         [0030]      FIG. 6  is a diagram showing an input/output characteristic of the 2-input amplifier shown in  FIG. 4 ;  
         [0031]      FIG. 7  is a diagram showing an input/output characteristic of the 2-input amplifier shown in  FIG. 5 ;  
         [0032]      FIG. 8  is a diagram showing an input/output characteristic of the 2-input amplifier shown in  FIG. 3 ;  
         [0033]      FIG. 9  is a circuit diagram showing a two-input amplifier according to a second embodiment of the present invention;  
         [0034]      FIG. 10  is a circuit diagram showing a specific circuit of a current adder circuit employed in the 2-input amplifier of  FIG. 9 ; and  
         [0035]      FIG. 11  is a circuit diagram showing another specific circuit of the current adder circuit employed in the 2-input amplifier of  FIG. 9 . 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0036]     Hereinafter, a differential amplifier of the present invention will be described in detail with reference to the attached drawings.  
       First Embodiment  
       [0037]      FIG. 3  is a diagram showing a circuit arrangement of an equivalent circuit of an operational amplifier having two inputs.  FIG. 4  is a circuit diagram showing a specific circuit arrangement of a PMOS (P-channel MOS) transistor differential amplifier contained in the equivalent circuit shown in  FIG. 3 .  FIG. 5  is a circuit diagram showing another specific circuit arrangement of an NMOS (N-channel MOS) transistor differential amplifier contained in the equivalent circuit shown in  FIG. 3 .  
         [0038]     The operational amplifier shown in  FIG. 3  is constituted by combining the PMOS transistor differential amplifier shown in  FIG. 4  and the NMOS transistor differential amplifier shown in  FIG. 5 . In order to easily understand the present invention, the circuit arrangement and operation of each of the PMOS transistor differential amplifier and the NMOS transistor differential amplifier will be described. Further, an equivalent circuit arranged by combining the NMOS transistor differential amplifier and the PMOS transistor differential amplifier will be described.  
         [0039]     Referring to  FIG. 4 , the PMOS transistor differential amplifier is composed of a source type constant current source CC 2 , PMOS transistors M 1  to M 4  and NMOS transistors MS and M 6 , and an amplifying unit A 1 . The PMOS transistor M 1  has the gate as a first input terminal, and the PMOS transistor M 3  has the gate as a second input terminal. The PMOS transistor M 2  has the gate as an inversion input terminal, and the PMOS transistor M 4  has the gate as the inversion input terminal. The NMOS transistor M 5  and the NMOS transistor M 6  constitute a current mirror circuit functioning as an active load, and an input of the amplifying unit A 1  is connected to an output of the active load. Furthermore, the gates of the PMOS transistor M 2  and PMOS transistor M 4  are connected with the output of the amplifying unit A 1  to constitute a voltage follower connection.  
         [0040]     More specifically, one terminal of the constant current source CC 2  is connected to a power supply voltage V DD , and this constant current source CC 2  supplies a current IR. The other terminal of the constant current source CC 2  is connected to the sources of the PMOS transistor M 3  and M 1 . A first input voltage V 1  and a second input voltage V 2  are applied to the gate of the PMOS transistor M 3 , and the gate of the PMOS transistor M 1 , respectively. The drain of the PMOS transistor M 3  and the drain of the PMOS transistor M 1  are connected to the drain of the NMOS transistor M 5 . The NMOS transistor M 5  constitutes a current mirror in combination with the NMOS transistor M 6 . The characteristics of the NMOS transistor M 5  are supposed to be identical to those of the NMOS transistor M 6 . The source of the NMOS transistor M 5  and the source of the NMOS transistor M 6  are connected to a ground voltage. The gate of the NMOS transistor M 5  and the gate of the NMOS transistor M 6  are connected to each other, and are further connected to the drain of the NMOS transistor M 5 . The drain of the NMOS transistor M 6  is connected to the drain of the PMOS transistor M 2  and the drain of the PMOS transistor M 4 . The source of the PMOS transistor M 2  and the source of the PMOS transistor M 4  are connected to the constant current source CC 2 . The gate of the PMOS transistor M 2  and the gate of the PMOS transistor M 4  are connected to the output of the amplifying unit A 1  as an output V O .  
         [0041]     Characteristics of the PMOS transistor M 2  and the PMOS transistor M 4  are supposed to be substantially same to those of the PMOS transistor M 3  and the PMOS transistor M 1 . The output voltage V O  of the PMOS transistor differential amplifier having such a circuit arrangement is in a range of the voltage V 1  and the voltage (V 1 +V 2 ). When the constant current source CC 2  flows the current I R , the PMOS transistor M 1  and the PMOS transistor M 3  flow a current I 2P  and a current I 3P  corresponding to the first input voltage V 1  and the second input voltage V 2 , respectively. A summation of the current I 2P  and the current I 3P  is equivalent to a current I R /2 and flows through the NMOS transistor M 5 . Since the NMOS transistor M 5  and the NMOS transistor M 6  have the same characteristics and constitute the current mirror circuit, the current I R /2 flows through the NMOS transistor M 6 . The constant current source CC 2  supplies the current I R /2 to the source of the PMOS transistor M 2  and the source of the PMOS transistor M 4 . If the PMOS transistor M 2  and the PMOS transistor M 4  have the same characteristics, a current I 1P  flows through the PMOS transistor M 2  and the PMOS transistor M 4 . Also, if the summation between the current flowing through the PMOS transistor M 2  and the current flowing through the PMOS transistor M 4  is coincident with the summation between the current flowing through the PMOS transistor M 3  and the current flowing through the PMOS transistor M 1 , the current I 1  is coincident with an averaged current between the current I 2  and the current I 3 . If the characteristics of the PMOS transistor M 2  and the PMOS transistor M 4  are coincident with the characteristics of the PMOS transistor M 3  and the PMOS transistor M 1 , the voltage at the gates of the PMOS transistor M 2  and M 4  is substantially equal to the averaged voltage between the first input voltage V 1  and the second voltage V 2 , namely, the in-phase voltage ((V 1 +V 2 )/2).  
         [0042]     Assuming now that a voltage which is applied to one non-inversion input terminal is equal to V 1  and another voltage which is applied to the other non-inversion input terminal is equal to V 2 , the in-phase voltage is correctly analyzed. In this case, a voltage V 0  which is finally outputted can be expressed as follows. That is, when  
               β   =       W   L     ⁢   μ   ⁢           ⁢     C   o         ,           (   1   )             
 
 where μ is a mobility in an MOS transistor, W is a gate width of the MOS transistor, L is a gate length of the MOS transistor is L, CO is a gate oxide film capacitance, the finally outputted voltage V 0  is expressed by the following equation (2):  
               V   o     =           V   1     +     V   2       2     +           -   2     ⁢         2   ⁢     I   1       β         +           (     2   ⁢         2   ⁢     I   1       β         )     2     -       (       V   1     -     V   2       )     2           2               (   2   )             
 
 where I 1  is the current flowing through each of the PMOS transistor M 2  and the PMOS transistor M 4 . 
 
         [0043]     Referring to  FIG. 5 , similarly to the PMOS transistor differential amplifier shown in  FIG. 4 , the NMOS transistor differential amplifier is provided with a constant current source CC 1  for supplying a current I R , NMOS transistors M 7  to M 10 , and PMOS transistors M 11  and M 12 .  
         [0044]     One terminal of the constant current source CC 1  is connected to the ground voltage, and the constant current source CC 1  supplies the current IR to the ground terminal. The other terminal of the constant current source CC 1  is connected to the sources of the NMOS transistors M 9  to M 10 . A first input voltage V 1  and a second input voltage V 2  are applied to the gate of the NMOS transistor M 9  and the gate of the NMOS transistor M 7 , respectively. The drain of the NMOS transistor M 9  and the drain of the NMOS transistor M 7  are connected to the drain of the PMOS transistor M 11 . The PMOS transistor M 11  constitutes a current mirror circuit together with the PMOS transistor M 12 . The characteristics of the PMOS transistor M 11  are supposed to be identical to those of the PMOS transistor M 12 . The source of the PMOS transistor M 11  and the source of the PMOS transistor M 12  are connected to the power supply voltage V DD . The gate of the PMOS transistor M 11  and the gate of the PMOS transistor M 12  are connected to each other, and are further connected to the drain of the PMOS transistor M 11 . The drain of the PMOS transistor M 12  is connected to the drain of the NMOS transistor M 8  and the drain of the NMOS transistor M 10 . The source of the NMOS transistor M 8  and the source of the NMOS transistor M 10  are connected to the constant current source CC 1 . An input of the amplifying unit A 1  is connected with the drain of the PMOS transistor M 12 , and an output of the amplifying unit A 1  is connected to the gate of the NMOS transistor M 8  and the gate of the NMOS transistor M 10  which are held to a same output voltage V O .  
         [0045]     The characteristics of the NMOS transistor M 7  to M 10  are supposed to be substantially identical to each other, and the characteristics of the PMOS transistor M 11  are supposed to be substantially identical to those of the PMOS transistor M 12 . In this case, the output voltage V O  of the NMOS transistor differential amplifier having such a circuit arrangement is substantially equal to an averaged voltage between the first input voltage V 1  and the second input voltage V 2 , namely an in-phase voltage ((V 1 +V 2 )/2). The NMOS transistor M 9  and the NMOS transistor M 7  flow a current I 2N  and a current I 3N  corresponding to the first input voltage V 1  and the second input voltage V 2 , respectively. A current I R /2 equal to a summation of the current I 2N  and the current I 3N  flows through the PMOS transistor M 11 . Since the PMOS transistor M 11  and the PMOS transistor M 12  constitute the current mirror circuit, the current I R /2 equal to that of the current flowing through the PMOS transistor M 11  flows through the NMOS transistor M 8  and the NMOS transistor M 10 . Since the NMOS transistor M 8  and the NMOS transistor M 10  have the same characteristics, a currents I 1N  flows through the NMOS transistor M 8  and the NMOS transistor M 10 . Since a summation between the current flowing through the NMOS transistor M 8  and the current flowing through the NMOS transistor M 10  is coincident with a summation between the current flowing through the NMOS transistor M 9  and the current flowing through the NMOS transistor M 7 , the current I 1N  is coincident with an averaged current between the current I 2N  and the current I 3N . Further, since the characteristics of the NMOS transistor M 8  and the NMOS transistor M 10  are coincident with the characteristics of the NMOS transistor M 9  and the NMOS transistor M 7 , the voltage at the gates of the NMOS transistor M 8  and M 10  is substantially equal to the averaged voltage of the first input voltage V 1  and the second voltage V 2 , namely, the in-phase voltage ((V 1 +V 2 )/2).  
         [0046]     In other words, assuming now that a voltage which is applied to one non-inversion input terminal is equal to V 1  and another voltage which is applied to the other non-inversion input terminal is equal to V 2 , a voltage V 0  which is finally outputted from the NMOS transistor differential amplifier shown in  FIG. 5  is expressed by the following equation (3):  
               V   o     =           V   1     +     V   2       2     +         2   ⁢         2   ⁢     I   1       β         -           (     2   ⁢         2   ⁢     I   1       β         )     2     -       (       V   1     -     V   2       )     2           2               (   3   )             
 
 where β is expressed by the following equation (1), like the PMOS transistor differential amplifier:  
             β   =       W   L     ⁢   μ   ⁢           ⁢     C   o               (   1   )             
 
 where I 1  is a current which flows through each of the NMOS transistor M 8  and the NMOS transistor M 10 . 
 
         [0047]      FIG. 6  is a diagram graphically showing an actual input/output characteristic of the PMOS transistor differential amplifier. Referring to FIG.  6 , the output voltage V O  of the PMOS transistor differential amplifier with the two inputs is nearly equal to: 
   V   O =( V   1   +V   2 )/2.  
 When a difference between the two inputted voltages V 1  and V 2  is relatively small. However, when a difference between the two inputted voltages V 1 and V   2  becomes large, an error of the output voltage V O  from (V 1 +V 2 )/2 becomes large. 
 
         [0048]      FIG. 7  is a diagram graphically showing an actual input/output characteristic of the NMOS transistor differential amplifier. Referring to  FIG. 7 , the output voltage V O  of the NMOS transistor differential amplifier with the two inputs is nearly equal to: 
   V   O =( V   1   +V   2 )/2.  
 When a difference between the tow inputted voltages V 1  and V 2  is relatively small. However, when a difference between the two inputted voltages V 1  and V 2  becomes large, an error of the output voltage V O  from (V 1 +V 2 )/2 becomes large. 
 
         [0049]     Furthermore, when the input/output characteristic of  FIG. 6  is compared with that of  FIG. 7 , it could be seen that polarities of errors are opposite to each other, when the difference between input voltages V 1  and V 2  becomes large in the PMOS transistor differential amplifier and the NMOS transistor differential amplifier.  
         [0050]     Referring now to  FIG. 3 , an input stage constitutes a differential amplifier having two non-inversion inputs. The differential amplifying circuit shown in  FIG. 3  is composed of a PMOS transistor differential stage having a circuit arrangement similar to that of the above-described PMOS transistor differential amplifier, and an N differential stage having a circuit arrangement similar to that of the above-explained NMOS transistor differential amplifier, between which the amplifying unit A 1  is shared.  
         [0051]     The PMOS transistor differential stage is formed from the constant current source CC 1 , the four PMOS transistors M 1  to M 4  and the two NMOS transistors M 5  and M 6 . The sources of the four PMOS transistors M 1  to M 4  are commonly connected to each other, and the constant current source CC 1  is inserted between the power supply voltage V DD  and the drains of the four PMOS transistors. The drains of the PMOS transistors M 1  and M 3  are commonly connected to each other, and the drains of the PMOS transistors M 2  and M 4  are commonly connected to each other. The NMOS transistors M 5  and M 6  constitute the current mirror circuit and functions as the active load.  
         [0052]     The NMOS transistor differential stage is formed from the constant current source CC 2 , the four NMOS transistors M 7  to M 10  and the first and second current mirror circuits CM 1  and CM 2 . Each of the first and second current mirror circuits CM 1  and CM 2  is formed from the PMOS transistors M 11  and M 12 . The output of the PMOS transistor M 11  in the first current mirror circuit is connected with the NMOS transistors M 7  and M 9 , and the output of the PMOS transistor M 12  is connected with drain of the NMOS transistor M 6 . Also, the output of the PMOS transistor M 11  in the second current mirror circuit is connected with the NMOS transistors M 8  and M 10 , and the output of the PMOS transistor M 12  is connected with drain of the NMOS transistor M 5 . The sources of the four NMOS transistors M 7  to M 10  are commonly connected to each other, and the constant current source CC 2  is inserted between the ground voltage and the drains of the four NMOS transistors. The sources of the NMOS transistors M 7  and M 9  are commonly connected to each other, and the sources of the NMOS transistors M 8  and M 10  are commonly connected to each other. In the N differential stage, the current mirror circuit CM 1  and the current mirror circuit CM 2  are provided in place of the current mirror circuit M 11  and M 12 . The current mirror circuit CM 1  supplies the current I R /2 from one output to the NMOS transistors M 7  and M 9 , and the other output is connected to the drain of the NMOS transistor M 6 . Also, the current mirror circuit CM 2  supplies the current I R /2 from one output to the NMOS transistors M 8  and M 10 , and the other output is connected to the drain of the NMOS transistor M 5 .  
         [0053]     Furthermore, the output of the amplifying unit A 1  is connected with the gate of the NMOS transistor M 8  and the gate of the NMOS transistor M 10  commonly and with the gate of the PMOS transistor M 2  and the gate of the PMOS transistor M 4  commonly, so as to constitute a voltage follower connection. The gate of the NMOS transistor M 9  and the gate of the PMOS transistor M 3  as a first input terminal are commonly connected with the first input voltage V 1 , and the gate of the NMOS transistor M 7  and the gate of the PMOS transistor M 1  as a second input terminal are commonly connected with the second input voltage V 2 .  
         [0054]     The gate of the NMOS transistor M 5  is connected to the gate of the NMOS transistor M 6 , and the gate of the NMOS transistor M 5  is connected to the drain of the NMOS transistor M 5 . The sources of the NMOS transistors M 5  and M 6  are connected to the ground terminal GND. The drain of the NMOS transistor M 5  is connected to the drains of the PMOS transistor M 1  and M 3  and the current mirror circuit CM 2 . The drain of the NMOS transistor M 6  is connected to the drains of the NMOS transistor M 2  and M 4 , the input of the amplifying unit A 1  and the current mirror circuit CM 1 .  
         [0055]     Assuming now that the voltage at the common source of the PMOS transistor differential stage is V MP , and the voltage at the common source of the NMOS transistor differential stage is V MN , a calculation is carried out. With reference to  FIG. 3 , assuming now that the current flowing through each of the PMOS transistor M 2  and the PMOS transistor M 4  is I 1P , the current flowing through the PMOS transistor M 3  is I 2P , and the current flowing through the PMOS transistor M 1  is I 3P , the current  4 I 1P  flows through the PMOS transistor differential stage and is expressed by the following equation (4): 
 
 4   I   1P = 2   I   P +I 2P +I 3P   (4) 
 
 Also, assuming now that the current flowing through each of the NMOS transistor M 8  and the NMOS transistor M 10  is I 1N , the current flowing through the NMOS transistor M 9  is I 2N , and the current flowing through the NMOS transistor M 7  is I 3N , the current  4 I 1N  flows through the NMOS transistor differential stage and is expressed by the following equation (5): 
 
 4   I   1N = 2   I   1N   +I   2N   +I   3N   (5) 
 
 In this case, since the currents flowing through the active load are equal to each other, the following equation (6) is given: 
 
 I   2P   +I   3P + 2   I   1N   =I   2N   +I   3N + 2 I 1P   (6). 
 
 At this time, assuming that a mobility in a PMOS transistor is μ P , a mobility in an NMOS transistor is μ N , and a ratio of a gate width W of the PMOS transistor to a gate length L thereof is:  
         W   L     ⁢     |   P         
 
 and a ratio of the gate width W of the NMOS transistor to the gate length L thereof is  
         W   L     ⁢     ❘   N         
 
 the following calculation is carried out by employing β P  and β N  which are expressed by the following equations (7) and (8) when a gate oxide film capacitance per a unit area of each of the PMOS and NMOS transistors is equal to CO;  
                 β   P     =       W   L     ⁢     |   P     ⁢       μ   P     ⁢     C   o           ,           (   7   )                 β   N     =       W   L     ⁢     |   N     ⁢       μ   N     ⁢       C   o     .                 (   8   )             
 
 Based upon a relation between a gate-to-drain voltage and a drain current, it is assumed that a common source-to-node voltage in the PMOS transistor differential stage is V MP , and a common source-to-node voltage in the NMOS transistor differential stage is V MN . Also, assuming now that a threshold voltage of the PMOS transistor is V TP  and a threshold voltage of the NMOS transistor is V TN , currents which flow through the respective transistors are expressed as follows:  
                 I     1   ⁢   P       =         β   P     2     ⁢       (       V   MP     -     V   o     -     V   TP       )     2         ,           (   9   )             
 
                 I     2   ⁢   P       =         β   P     2     ⁢       (       V   MP     -     V   1     -     V   TP       )     2         ,           (   10   )                   I     3   ⁢   P       =         β   P     2     ⁢       (       V   MP     -     V   2     -     V   TP       )     2         ,           (   11   )                   I     1   ⁢   N       =         β   N     2     ⁢       (       V   o     -     V   MN     -     V   TN       )     2         ,           (   12   )                   I     2   ⁢   N       =         β   N     2     ⁢       (       V   1     -     V   MN     -     V   TN       )     2         ,           (   13   )                 I     3   ⁢   N       =         β   N     2     ⁢         (       V   2     -     V   MN     -     V   TN       )     2     .               (   14   )             
 
 If the above-described equations (9) to (14) are substituted for the above-explained equation (6), the following equation (15) is given:  
                         β   P     2     ⁢       ⁢     {         (       V   MP     -     V   1     -     V   TP       )     2     +       (       V   MP     -     V   2     -     V   TP       )     2       }       +                   ⁢         β   N     ⁡     (       V   o     -     V   MN     -     V   TN       )       2                 =       ⁢           β   N     2     ⁢     {         (       V   1     -     V   MN     -     V   TN       )     2     +       (       V   2     -     V   MN     -     V   TN       )     2       }       +                     ⁢           β   P     ⁡     (       V   MP     -     V   o     -     V   TP       )       2     .                   (   15   )             
 
 In this case, based upon a relation between the gate-to-source voltage V GS  and the drain currents (I 1P , I 1N ), the following equation can be satisfied in the PMOS channel differential stage:  
           V   MP     -     V   TP       =           2   ⁢     I     1   ⁢   P           β   P         +     V   o           
 
 In other words, the following equal (16) can be satisfied:  
               V   GS     =         V   MP     -     V   o       =           2   ⁢     I     1   ⁢   P           β   P         +       V   TP     .                 (   16   )             
 
 Similarly, the following equation can be satisfied in the NMOS channel differential stage:  
         V   GS     =         V   o     -     V   MN       =           2   ⁢     I     1   ⁢   N           β   N         +       V   TN     .             
 
 In other words, the following equation (17) can be satisfied:  
                 -     V   MN       -     V   TN       =           2   ⁢     I     1   ⁢   N           β   N         -       V   o     .               (   17   )             
 
 If these equations (16) and (17) are substituted for the above-mentioned equation (15), the following equation (18) is obtained:  
                         β   P     ⁢       (           2   ⁢     I     1   ⁢   p           β   P         +     V   o     -     V   1       )     2     +         β   P     ⁡     (           2   ⁢     I     1   ⁢   P           β   P         +     V   o     -     V   2       )       2     +                   ⁢     2   ⁢     β   N     ⁢       2   ⁢     I     1   ⁢   N           β   N                     =       ⁢           β   N     ⁡     (       V   1     +         2   ⁢     I     1   ⁢   N           β     N   o           -     V   o       )       2     +         β   N     ⁡     (       V   2     +         2   ⁢     I     1   ⁢   P           β   P         -     V   o       )       2     +                     ⁢     2   ⁢     β   P     ⁢         2   ⁢     I     1   ⁢   P           β   P       .                     (   18   )             
 
         [0056]     When this equation (18) is expanded, the following equation (19) is obtained: 
 
2{square root}{square root over (2β P   I   1P )}(2 V   o   −V   1   −V   2 )+β P {( V   o   −V   1 ) 2 +( V   0   −V   2 ) 2 }=2{square root}{square root over (2β N   I   1N )}( V   1   +V   2 −2 V   O )+β N {( V   1   −V   O ) 2 +( V   2   −V   O ) 2 }  (19). 
 
 In this equation (19), if β P =β N , namely,  
                 W   L     ⁢     ❘   P     ⁢       μ   P     ⁢     C   o         =       W   L     ⁢     ❘   N     ⁢       μ   N     ⁢     C   o                         W   L     ⁢     ❘   P     ⁢     μ   P       =       W   L     ⁢     ❘   N     ⁢     μ   N                 
 
 then the following equation can be satisfied under the condition that β P =β N =β: 
 
2{square root}{square root over (2β)}(2 V   o   −V   1   −V   2 ({square root}{square root over ( I   1P )}+{square root}{square root over ( I   IN )})+β{( V   o   −V   1 ) 2 +( V   o   −V   2 ) 2 }−β{( V   1   −V   o ) 2 +( V   2   −V   o ) 2 }=0. 
 
 When this equation is solved, the following equation is given as follows: 
 
2 V   O   −V   1   −V   2 =0 
 
 In other words, V 0  is expressed by the following equation (20):  
               V   o     =           V   1     +     V   2       2     .             (   20   )             
 
 As a consequence, in accordance with the differential amplifier described in this first embodiment, the desirable half voltage of the two input voltages can be outputted irrespective of the current flowing through the PMOS transistor differential stage and the current through the NMOS transistor differential stage. 
 
         [0057]      FIG. 8  is a diagram graphically showing the input/output characteristic of the differential amplifier shown in  FIG. 3 . With reference to  FIG. 8 , it could be readily understood that even when a difference between the first input voltage V 1  and the second input voltage V 2  becomes large, the voltage of (V 1 +V 2 )/2 is outputted as the output voltage V 0  of the differential amplifier with the two inputs of this first embodiment.  
         [0058]     Also, if β P  is not equal to β N , the following equation can be satisfied: 
 
2({square root}{square root over (2β P   I   1P )}−{square root}{square root over (2β N   I   1N )})(2 V   o   −V   1   −V   2 )=β P {2 V   o   2 −2 V   o ( V   1   +V   2 )+ V   1   2   +V   2   2 }−β N {2 V   o   2   −V   o ( V   1   +V   2 )+ V   1   2   +V   2   2 }=0 
 
 When a left side of this equation is expanded, an equation (21) is obtained: 
 
2(β P −β N ) V   o   2 −2 V   o {(β P −β N )( V   1   +V   2 )−2({square root}{square root over (2β P   I   1P )}−{square root}{square root over (2β N   I   1N )})}+(β P −β N )( V   1   2   +V   2   2 )−2({square root}{square root over (2β P   I   1P )}−{square root}{square root over (2β N   I   1N )})( V   1   +V   2 )β0  (21). 
 
 When this equation (21) is solved with respect to V o , the following equation (22) is obtained as follows:  
                     V   o     =       ⁢           V   1     +     V   2       2     -         (         2   ⁢           ⁢     β   P     ⁢     I     1   ⁢   P           -       2   ⁢           ⁢     β   N     ⁢     I     1   ⁢   N             )       (       β   P     -     β   N       )       ±                       ⁢             16   ⁢       (         2   ⁢           ⁢     β   P     ⁢     I     1   ⁢   P           -       2   ⁢           ⁢     β   N     ⁢     I     1   ⁢   N             )     2       -     4   ⁢       (       β   P     -     β   N       )     2     ⁢       (       V   1     -     V   2       )     2             4   ⁢     (       β   P     -     β   N       )         .                   (   22   )             
 
         [0059]     In this equation, based upon the condition of V 1 =V 2 =V 0  under V 1 =V 2 , symbol “plus or minus” becomes plus (+) in the above-explained equation (22). As a consequence, this equation (22) is transformed into the following equation (23):  
                     V   o     =       ⁢           V   1     +     V   2       2     -       (         2   ⁢           ⁢     β   P     ⁢     I     1   ⁢   P           -       2   ⁢           ⁢     β   N     ⁢     I     1   ⁢   N             )       (       β   P     -     β   N       )       +                     ⁢             16   ⁢       (         2   ⁢           ⁢     β   P     ⁢     I     1   ⁢   P           -       2   ⁢           ⁢     β   N     ⁢     I     1   ⁢   N             )     2       -     4   ⁢       (       β   P     -     β   N       )     2     ⁢       (       V   1     -     V   2       )     2             4   ⁢     (       β   P     -     β   N       )         .                   (   23   )             
 
 This equation (23) expresses an equation when the NMOS transistor differential stage and the PMOS transistor differential stage are not balanced, and the second term and the third term constitute an error from a desirable value. 
 
         [0060]     As indicated in the above-described equation (23), by using the differential amplifying circuit of this first embodiment, the precision of the averaged voltage of the 2-input amplifier can be considerably improved even when β P  is not equal to β N .  
       Second Embodiment  
       [0061]      FIG. 9  is a diagram showing the circuit arrangement of a differential amplifier according to the second embodiment of the present invention. Referring now to  FIG. 9 , the differential amplifier of the second embodiment is formed from the 2-input PMOS transistor differential stage, the 2-input NMOS transistor differential stage, a current adder circuit and an amplifying unit A 2 . The 2-input PMOS transistor differential stage is composed of the constant current source CC 2  and the PMOS transistors M 1  to M 4 , like the PMOS transistor differential stage in the first embodiment. Also, the 2-input NMOS transistor differential stage is composed of the constant current source CC 1  and the NMOS transistors M 7  to M 10 , like the NMOS transistor differential stage in the first embodiment. The current adder circuit adds the outputs of the NMOS transistor differential stage and the outputs of the PMOS transistor differential stage, and outputs the addition result to the amplifying unit A 2 . The output of the amplifying unit A 2  is commonly connected to the PMOS transistors M 2  and M 4  and the NMOS transistors M 8  and M 10  so as to construct a voltage follower.  
         [0062]      FIG. 10  is a specific circuit diagram of the current adder circuit. Referring now to  FIG. 10 , the current adder circuit contains a fourth current mirror circuit connected to a positive power supply voltage V DD2 , a fifth current mirror circuit connected to the ground terminal GND, first and second floating constant current sources between the fourth and fifth current mirror circuit. In this case, the power supply voltage is V DD2  but may be V DD .  
         [0063]     The fourth current mirror circuit is a current mirror circuit of a low-voltage cascode connection. The fourth current mirror circuit contains PMOS transistors M 21  to M 24 . The sources of the PMOS transistors M 21  and M 22  are connected to the positive power supply V DD2 . The gate of the PMOS transistor M 21  is connected to the gate of the PMOS transistor M 22 , and the gate of the PMOS transistor M 23  is connected to the gate of the PMOS transistor M 24 . The drain of the PMOS transistor M 21  is connected with the source of the PMOS transistor M 23 , and the drain of the PMOS transistor M 22  is connected with the source of the PMOS transistor M 24 . The drain of the PMOS transistor M 23  is connected with the gate of the PMOS transistor M 21 . The gates of the PMOS transistors M 23  and M 24  are connected to a bias terminal BP 2 . The source of the PMOS transistor M 23  and the source of the PMOS transistor M 24  are connected to a common node of the drains of the NMOS transistors M 7  and M 9  and to a common node of the drains of the NMOS transistors M 8  and M 10 , respectively. The bias signal BP 2  and the following bias signal BN 2  are respectively set to a low level and a high level during the amplification.  
         [0064]     The fifth current mirror circuit is a current mirror circuit of a low-voltage cascode connection. The fifth current mirror circuit contains NMOS transistors M 25  to M 28 . The sources of the NMOS transistors M 25  and M 26  are connected to the ground voltage GND. The gate of the NMOS transistor M 25  is connected to the gate of the NMOS transistor M 26 , and the gate of the PMOS transistor M 27  is connected to the gate of the NMOS transistor M 28 . The drain of the NMOS transistor M 25  is connected with the source of the NMOS transistor M 27 , and the drain of the NMOS transistor M 26  is connected with the source of the NMOS transistor M 28 . The drain of the NMOS transistor M 27  is connected with the gate of the NMOS transistor M 25 . The gates of the NMOS transistors M 27  and M 28  are connected to a bias terminal BN 2 . The source of the NMOS transistor M 27  and the source of the NMOS transistor M 28  are connected to a common node of the drains of the PMOS transistors M 2  and M 4  and to a common node of the drains of the PMOS transistors M 1  and M 3 , respectively.  
         [0065]     The first floating constant current source contains a PMOS transistor M 30  and an NMOS transistor M 29  which are connected in parallel. The source of the PMOS transistor M 30  and the drain of the NMOS transistor M 29  are connected to the drain of the PMOS transistor M 23 . Also, the drain of the PMOS transistor M 30  and the source of the NMOS transistor M 29  are connected to the drain of the NMOS transistor M 27 . The gate of the PMOS transistor M 30  and the gate of the NMOS transistor M 29  are connected to bias terminals BP 3  and BN 3 , respectively. As a result, a constant current flows from the fourth current mirror circuit to the fifth current mirror circuit based on signals on the bias terminals BP 3  and BN 3 .  
         [0066]     The second floating constant current source contains a PMOS transistor M 32  and an NMOS transistor M 31  which are connected in parallel. The source of the PMOS transistor M 32  and the drain of the NMOS transistor M 31  are connected to the drain of the PMOS transistor M 24 . Also, the drain of the PMOS transistor M 32  and the source of the NMOS transistor M 31  are connected to the drain of the NMOS transistor M 28 . The gate of the PMOS transistor M 32  and the gate of the NMOS transistor M 31  are connected to the bias terminals BP 3  and BN 3 , respectively. As a result, a constant current flows from the fourth current mirror circuit to the fifth current mirror circuit based on signals on the bias terminals BP 3  and BN 3 .  
         [0067]     In this current adder circuit, a node between the drain of the PMOS transistor M 21  and the source of the PMOS transistor M 23  commonly connected to each other, and a node between the drain of the PMOS transistor M 22  and the source of the PMOS transistor M 24  function as a positive current adding terminal. Also, a node between the drain of the NMOS transistor M 25  and the source of the NMOS transistor M 27  commonly connected to each other, and a node between the drain of the NMOS transistor M 26  and the source of the NMOS transistor M 28  function as a negative current adding terminal. A series circuit of capacitors C 1  and C 2  is connected between the drain of the PMOS transistor M 22  and the drain of the NMOS transistor M 28 . A node between the capacitors C 1  and C 2  is connected with an output terminal OUT.  
         [0068]     An output stage circuit as the amplifying unit A 2  contains a PMOS transistor M 33  and an NMOS transistor M 34  which are connected in series. The source of the PMOS M 33  is connected to the positive power source terminal V DD2 , and the source of the NMOS transistor M 34  is connected to the negative power source terminal GND. The gate of the NMOS transistor M 33  is connected to the drain of the PMOS transistor M 24  as the output of the fourth current mirror circuit, and the gate of the NMOS transistor M 34  is connected to the drain of the NMOS transistor M 28  as the output of the fifth current mirror circuit. A node between the PMOS transistor M 33  and the NMOS transistor M 34  is connected with the output terminal OUT. The output stage circuit constitutes a so-called an AB class output circuit, and an idling current is determined based upon a voltage between the above-described bias terminals BP 3  and BN 3 .  
         [0069]     In this current adder circuit, signals of transistors which are connected to respective current adding terminals are added to each other, and an adding result is outputted to an output terminal OUT. Since the differential amplifier shown in  FIG. 9  is provided with the current adder circuit shown in  FIG. 10 , input currents are not added to each other in the active load, but are separately processed.  
         [0070]     In the second embodiment, the following calculation is carried out, assuming now that a voltage at the common sources of the PMOS transistor differential stage is V MP , and a voltage at the common sources of the NMOS transistor differential stage is V MN . 
 
 4   I   1P = 2   I   1P   +I   2 P+ I   3P   (4) 
 
 4   I   1N = 2   I   2N   +I   3N   (5) 
 
 Since the current flowing through the active loads are equal to each other, the following equations (24) and (25) can be obtained: 
 
 I   2P   +I   3P = 2   I   1N   (24) 
 
 I   2N   +I   3N = 2   I   1P   (25) 
 
 Even if the left side of the equation (25) is added to the right side of the equation (24), and the right side of the equation (25) is added to the left side of the equation (24), the following equation (26) can be satisfied: 
 
 I   2P   +I   3P + 2   I   1N   =I   2N   +I   3N + 2   I   1P   (26) 
 
         [0071]     It could be understood that this equation (26) is completely the same as the equation (6) of the differential amplifier (namely, differential amplifier which adds the N-channel output to the P-channel output in the active load) in the first embodiment. Therefore, the calculation results become equal to each other. In other words, the differential amplifier shown in  FIG. 9  outputs a desirable half voltage of the two input voltages.  
         [0072]     Moreover, since the circuit arrangement of the present invention is employed, an input Rail-to-rail can be realized. In  FIG. 9 , in order to realize the input Rail-to-rail as the entire characteristic of the differential amplifier, the circuit arrangement of the current adder circuit is important. This reason will now be described with reference to  FIG. 9 . First of all, in order to realize the input Rail-to-rail, all of the input stage transistors M 1  to M 4 , or all of other transistors M 7  to M 10  are required to enter into a pentode region (namely, saturation region). This is because of the following reason. That is, if these transistors M 1  to M 4 , or M 7  to M 10  enters into a triode region, the output resistance of the transistor is extremely lowered, and the mutual conductance gm of the transistor is also lowered, so that these transistors cannot carry out the normal differential stage transistor operation. A condition when an MOS transistor enters into the pentode region (saturation region) is expressed by the following equation (27), assuming now that a drain-to-source voltage is V DS , a gate-to-source voltage is V GS , and a threshold voltage is V T : 
 
 V   DS   &gt;V   GS   −VT   (27). 
 
         [0073]     In this case, the condition under which the PMOS transistors M 1  to M 4  enters into the pentode region (saturation region) when the input voltage becomes the minimum voltage of GND (zero volt) is the gate voltage of GND (zero volt), since the source voltages of these PMOS transistor become equal to V GS . On the other hand, assuming now that a drain voltage is equal to V D , the source-to-drain voltage V DS  is given by the following equation (28): 
 
 V   DS   =V   GS   −V   D   (28). 
 
 Based upon the conditions defined by the above-described equation (27) and equation (28), the current adder circuit needs to be designed in such a manner that the following equation can be satisfied: 
 
 V   GS   −V   D   &gt;V   GS   −V   T , 
 
 namely, 
 
V D &lt;V T   (29). 
 
 The voltage V D  is a voltage of a node to which the drains of the MOS transistors M 1  and M 3 , or the drains of the MOS transistors M 2  and M 4  are connected. Based upon this condition and the above-described equation (29), the input voltage of the current adder circuit must be set lower than or equal to VT. Now, as a specific value, since a threshold voltage VT of a general transistor is approximately 0.7 V, the input voltage of the current adder circuit needs to be lower than or equal to approximately 0.7 V in accordance with the equation (29). 
 
         [0074]     Similarly, the condition under which the NMOS transistors M 7  to M 10  enters into the pentode region (saturation region) when the input voltage is equal to the maximum potential of V DD  is the gate voltages of V DD . Therefore, the source voltages of these NMOS transistors become equal to V DD −V GS  at this time. On the other hand, assuming now that the drain voltage is equal to V D , the source-to-drain voltage V DS  is given by the following equation (30): 
 
 V   DS   =V   D −( V   DD   −V   GS )  (30) 
 
 Based upon the conditions defined by the above-described equation (27) and equation (30), the current adder circuit is required to be designed in such a manner that the following equation can be satisfied: 
 
 V   D   −V   DD   +V   GS   &gt;V   GS   −V   T  
 
 namely, 
 
 V   DD   −V   D   &lt;V   T   (31). 
 
 The drain voltage V D  is a terminal voltage of a node to which the drains of the NMOS transistors M 7  and M 9 , or the drains of the NMOS transistors M 8  and M 10  are connected. Based upon this condition and the above-described equation (31), the input voltage of the current adder circuit must be set higher than or equal to V DD −V T . Now, as specific value, the input voltage is required to be set higher than or equal to approximately (V DD −0.7V). The current adder circuit of  FIG. 9  is required to be designed in such a manner that the above-explained conditions can be satisfied. It should be noted that one example of the current adder circuits capable of satisfying the conditions is the circuit arrangement of the current adder circuit shown in  FIG. 10 . 
 
         [0075]     Next, the reason why this current adder circuit of  FIG. 10  can satisfy the above-described conditions will now be explained. The input terminal voltage of the current adder circuit when the input voltage is equal to GND (zero volt) is drain voltages V D(M25/M26)  of the NMOS transistors M 25  and M 26 . Assuming now that the terminal voltage of the bias terminal BN 2  is V BN2  and the gate-to-source voltage of each of the NMOS transistors M 27  and M 28  is V GS(M27/M28) , this drain voltage V D(M25/M26)  is given by the following equation (32): 
 
 V   D(M25/M26)   =V   BN2   −V   GS(M27/M28)   (32). 
 
 In this case, this terminal voltage V BN2  of the bias terminal BN 2  is generated by the gate-to-source voltage of the MOS transistor in a general design. Therefore, the above -equation (32) is modified as follows: 
 
 V   D(M25/M26)   =V   GS   −V   GS(M27/M28) &lt;0.7  V   (33). 
 
 As a consequence, this equation (33) can satisfy the above conditions. Similarly, when the input voltage is the maximum potential of V DD , the above-described conditions can be satisfied. Thus, if such a circuit arrangement is employed, the input Rail-to-rail can be realized. As a result, the use efficiency of the power supply can be increased, and the low voltage and the low power consumption can be realized. 
 
         [0076]      FIG. 11  is a diagram showing another specific circuit of the current adder circuit. Referring now to  FIG. 11 , this current adder circuit will be described. The current adder circuit shown in  FIG. 11  is composed of a sixth current mirror circuit connected to the positive power supply, a seventh current mirror circuit connected to the ground terminal GND, and a third floating constant current source. This sixth current mirror circuit is composed of PMOS transistors M 41  and M 42 . The gate of the PMOS transistor M 41  is connected to the gate of the PMOS transistor M 42 , and the drain of the PMOS transistor M 41 . Also, the sources of the PMOS transistors M 41  and M 42  are connected to the positive power supply voltage V DD2 . The drains of the PMOS transistor M 41  and M 42  are connected to a node of the drains of the NMOS transistors M 7  and M 9  and a node of the drains of the NMOS transistors M 8  and M 10 , respectively.  
         [0077]     This seventh current mirror circuit is composed of NMOS transistors M 43  and M 44 . The gate of the NMOS transistor M 43  is connected to the gate of the NMOS transistor M 44 , and the drain of the NMOS transistor M 43 . Also, the sources of the NMOS transistors M 43  and M 44  are connected to the ground voltage GND. The drains of the NMOS transistor M 43  and M 44  are connected to a node of the drains of the PMOS transistors M 2  and M 4  and a node of the drains of the PMOS transistors M 1  and M 3 , respectively.  
         [0078]     The third floating constant current source is composed of a PMOS transistor M 52  and an NMOS transistor M 51  which are connected in parallel. The source of the PMOS transistor M 52  and the drain of the NMOS transistor M 51  are commonly connected to the drain of the NMOS transistor M 44 . Also, the source of the PMOS transistor M 52  and the drain of the NMOS transistor M 51  are commonly connected to the drain of the PMOS transistor M 42 . The gate of the PMOS transistor M 52  and the gate of the NMOS transistor M 51  are connected with bias terminals BP 3  and BN 3 , respectively.  
         [0079]     A series circuit of a constant current source CC 3 , capacitors C 1  and C 2 , and a constant current source CC 4  is provided between the positive power supply voltage V DD2  and the ground voltage GND. A node between the constant current source CC 3  and the capacitor C 1  is connected with the drain of the PMOS transistor M 42 . Also, a node between the constant current source CC 4  and the capacitor C 2  is connected with the drain of the NMOS transistor M 44 . A node between the capacitors C 1  and C 2  is connected with an output terminal OUT.  
         [0080]     An output stage circuit is composed of a PMOS transistor M 53  and an NMOS transistor M 54  which are connected in series between the power supply voltage V DD2  and the ground voltage GND. The gate of the PMOS transistor M 53  is connected to the drain of the PMOS transistor M 42  and the node between the constant current source CC 3  and the capacitor C 1 . Also, the gate of the NMOS transistor M 54  is connected to the drain of the NMOS transistor M 44  and the node between the constant current source CC 4  and the capacitor C 2 . A node between the PMOS transistor M 53  and the NMOS transistor M 54  is connected with the output terminal OUT. This output stage circuit constitutes a so-called AB class output circuit, and an idling current is determined based upon a voltage between the bias terminals BP 3  and BN 3 . The constant current source CC 3  flows a same current as the constant current source CC 4  flows, and may be same as a current flowing through the third floating constant current source.  
         [0081]     In this current adder circuit shown in  FIG. 11 , current consumption becomes small, as compared with that of the current adder circuit of  FIG. 10 . The reason is in that the first floating constant current source of MOS transistors M 29  and M 30  can be omitted in the current adder circuit in  FIG. 11  as well as the current flowing through the current path of the transistors M 51 /M 52  can be reduced to a minimum current value in a design.  
         [0082]     As described above, in accordance with the present invention, the NMOS transistor differential amplifier and the PMOS transistor differential amplifier are combined with each other so as to cancel the errors in the respective differential amplifiers. As a result, when the two different input voltages V 1  and V 2  are supplied to the two input terminals, the averaged voltage, namely, (V 1 +V 2 )/2) can be correctly outputted.