Abstract:
A reconfigurable context-based operation instruction set processor for use in a processing system capable of executing a first instruction set. The reconfigurable context-based operation instruction set processor comprises: 1) a reconfigurable data path comprising a plurality of reconfigurable functional blocks; and 2) a programmable finite state machine capable of controlling the reconfigurable data path. The programmable finite state machine is capable of executing a first plurality of context-related instructions that are a first subset of the first instruction set.

Description:
CROSS-REFERENCE TO RELATED APPLICATION AND CLAIM OF PRIORITY 
   The present invention is related to that disclosed in U.S. Provisional Patent No. 60/653,968, filed Feb. 17, 2005, entitled “Context-Based Operation Reconfigurable Instruction Set Processor”. U.S. Provisional Patent No. 60/653,968 is assigned to the assignee of the present application. The subject matter disclosed in U.S. Provisional Patent No. 60/653,968 is hereby incorporated by reference into the present disclosure as if fully set forth herein. The present application hereby claims priority under 35 U.S.C. §119(e) to U.S. Provisional Patent No. 60/653,968. 

   TECHNICAL FIELD OF THE INVENTION 
   The present invention relates generally to data processors and, more specifically, to a data processor that uses reconfigurable instruction set hardware. 
   BACKGROUND OF THE INVENTION 
   Data processors are used in nearly every type of modern electronic device, including consumer electronics, industrial machinery, scientific apparatuses and communication networks. However, the performance and degree of complexity of the data processors (or microprocessors) used in different applications may vary widely. The speed and power requirements of a particular application are important in determining the type of data processor used. 
   The type of data processor used is particularly important in software-defined radio (SDR) implementations. An SDR device uses reconfigurable hardware that may be programmed over the air to operate under different wireless protocols. For example, an SDR transceiver in a wireless laptop computer may be configured by a first software load to operate in an IEEE-802.11x wireless network and may be reconfigured by a second software load to operate in a CDMA2000 wireless network. 
   There are six main types of data processors in common use: 1) digital signal processors, 2) reduced instruction set computers, 3) complex instruction set computers, 4) field programmable gate arrays, 5) application specific integrated circuits, and 6) application specific instruction set processors. Each of these types of data processors has particular advantages and particular disadvantages. 
   A digital signal processor (DSP) is a general-purpose processor optimized to efficiently execute digital signal processing operations, such as a Multiply-Accumulate operation for finite impulse response (FIR) filtering and Fast Fourier Transform (FFT) operations. A DSP implements many sophisticated addressing modes to cover many of the DSP calculation requirements, such as bit reverse addressing mode for FFT, index addressing for FIFO devices, and the like. Examples of DSPs include: 1) the MOTOROLA 56000, 56300, SC81xx, and MRC6011 processors; 2) the TEXAS INSTRUMENTS (TI) C55, C6203, C6416, and C67xx processors; 3) the ADI SHARC and TIGERSHARC processors; and 4) the MORPHO MS1-64 Reconfigurable DSP. 
   A reduced instruction set computer (RISC) is a general purpose processor (GPP) that mainly targets control applications, such as media access control (MAC) applications. The main advantage of the RISC machine is its simplicity. As its name, a RISC processor has small instruction set, which provides more code density as well as faster change-of-flow reaction. Examples of RISC devices include: 1) ARM processors (e.g., ARM926, ARM1136J); 2) MIPS processors (e.g., MIPS32, MIPS64); 3) the IBM POWERPC 405 and 750FX processor; and 4) the MOTOROLA POWERPC 603 processor. 
   A complex instruction set computer (CISC) device is a general purpose processor (GPP) targeted to the general purpose applications ranging from multimedia applications to PC applications. Examples of CISC processors include: 1) the INTEL PENTIUM processor; and 2) the MOTOROLA 68000 processor. 
   The field programmable gate array (FPGA) is a reconfigurable hardware device based on an array of hardware cells connected through long busses and local busses. FPGA devices are quite commonly used in wireless network base station applications and prototypes. Examples of FPGA devices include: 1) the XILINX VIRTEX IV device; and 2) the ALTERNA STRATIX II device. 
   An application specific integrated circuit (ASIC) is a hardware device specially designed for a specific application. An ASIC is usually very power efficient. ASIC devices are used in many wireless devices (i.e., cell phones, etc.). An application specific instruction set processor (ASIP) is an enhanced version of an ASIC device that adds more programmability to the ASIC hardware. 
   Each of the above-described processors has certain advantages and suffers from particular disadvantages. Digital signal processors are the most flexible type of processor, from a software point of view, in order to meet software-defined radio (SDR) requirements. However, DSP devices do not have enough MIPS performance and bit manipulation architecture to meet 3G and 4G bit-rate processing requirements. RISC processors target control applications, but are inadequate beyond baseband applications for wireless network implementations. CISC processors may have the flexibility and the MIPS performance to process baseband applications, but their poor power efficiency makes them unsuitable for handset power restrictions. FPGA devices, like CISC processors, may meet the required MIPS performance, but their poor power efficiency makes them unsuitable for handset designs. 
   ASIC devices are well matched to the power and cost restrictions of handset designs. However, their flexibility is too limited to make them suitable for SDR implementations. ASIP devices achieve greater flexibility than ASIC devices by adding more programmability to the application specific hardware and by introducing instruction-set processors to the hardware. However, since ASIPs are general-purpose devices, their processor core efficiency depends on the application being processed. The more control code in the application, the less efficient the ASIP will be. This results in poor performance and higher power consumption. 
   Additional disadvantages of the prior art processors are scalability and modularity. The software-defined radio (SDR) approach was created in order to minimize cost (design time, TTM) and power consumption and to maximize flexibility. The prior art processor implementations fail to provide an optimized combination of scalability and modularity. 
   Therefore, there is a need in the art for an improved data processor design for use in a wide variety of applications. In particular, there is a need for an improved data processor design for use in software-defined radio (SDR) wireless devices. 
   SUMMARY OF THE INVENTION 
   To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide a reconfigurable context-based operation instruction set processor for use in a processing system capable of executing a first instruction set. According to an advantageous embodiment of the present invention, the reconfigurable context-based operation instruction set processor comprises: 1) a reconfigurable data path comprising a plurality of reconfigurable functional blocks; and 2) a programmable finite state machine capable of controlling the reconfigurable data path. The programmable finite state machine is capable of executing a first plurality of context-related instructions that are a first subset of the first instruction set. 
   According to one embodiment of the present invention, the reconfigurable data path is configured by reconfiguration bits received from an external controller in the processing system. 
   According to another embodiment of the present invention, the programmable finite state machine is programmed by reconfiguration bits received from the external controller. 
   According to still another embodiment of the present invention, the reconfigurable context-based operation instruction set processor further comprises a program memory coupled to the programmable finite state machine, wherein the program memory is capable of storing the first plurality of context-related instructions for retrieval and execution by the programmable finite state machine. 
   According to yet another embodiment of the present invention, the first plurality of context-related instructions are stored in the program memory by the external controller. 
   According to a further embodiment of the present invention, the reconfigurable context-based operation instruction set processor may be disabled by the external controller during a time period in which a second reconfigurable context-based operation instruction set processor associated with the processing system is operating. 
   According to a still further embodiment of the present invention, the second reconfigurable context-based operation instruction set processor is capable of executing a second plurality of context-related instructions that are a second subset of the first instruction set. 
   According to a yet further embodiment of the present invention, the processing system comprises a software-defined radio device. 
   Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term “controller” means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numerals represent like parts: 
       FIG. 1  is a block diagram of a conventional data processor according to an exemplary embodiment of the prior art; 
       FIG. 2  illustrates a finite state machine (FSM) table for a data processor; 
       FIG. 3  is a bubble diagram corresponding to the finite state machine table in  FIG. 2 ; 
       FIG. 4  is a bubble diagram showing context-based groupings of states in the finite state machine table in  FIG. 2  according to an exemplary embodiment of the present invention; 
       FIG. 5  is a high-level block diagram of a context-based operation reconfigurable instruction set processor according to an exemplary embodiment of the present invention; and 
       FIG. 6  is a high-level block diagram of a reconfigurable processing system comprising a plurality of context-based operation reconfigurable instruction set processors according to an exemplary embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIGS. 1 through 6 , discussed below, and the various embodiments used to describe the principles of the present invention in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the invention. Those skilled in the art will understand that the principles of the present invention may be implemented in any suitably arranged processing system. 
     FIG. 1  is a high-level block diagram of conventional data processor  100  according to an exemplary embodiment of the prior art.  FIG. 1  depicts a general implementation of an application in hardware and software. Data processor  100  comprises memory  110  and control circuitry  120 . Control circuitry  120  further comprises mixed control finite state machine (FSM) circuitry and datapath circuitry. Memory  110  further comprises N memory blocks, including exemplary memory blocks  111 - 113 , which are arbitrarily labeled Memory  1 , Memory  2 , and Memory N. 
   Any data processor application may be regarded as a set of datapaths controlled and scheduled by a finite state machine (FSM), as  FIG. 1  shows. A finite state machine receives input events and, in response, transitions between states and/or generates outputs. The FSM decides to which states to transition based on the current state and the received input events. 
     FIG. 2  illustrates finite state machine (FSM) table  200  for an exemplary data processor. FSM table  200  depicts the next state transitions performed by a FSM based on the current state (i.e., one of states S 1 -S 10 ) and the received input event (i.e., one of events E 1 -E 7 ). Initially, the FSM is in state S 1 . The column for state S 1  indicates the state transitions for state S 1  in response to events E 1 -E 4 . 
   In response to event E 1  received during state S 1 , the FSM transitions from state S 1  to state S 9 . In response to event E 2  received during state S 1 , the FSM transitions from state S 1  to state S 2 . In response to event E 3  received during state S 1 , the FSM transitions from state S 1  to state S 2 . In response to event E 4  received during state S 1 , the FSM transitions from state S 1  to state S 10 . 
   As  FIG. 2  makes clear, there are many holes in the FSM table  200  for which no values are given. For example, for state S 1 , no values are given for events E 5 -E 7 . In prior art data processors, those holes, although they do not contribute to the flow of the finite state machine, must be provided for, otherwise the finite state machine will not work correctly. In the prior art data processors, the finite state machines cannot be further optimized to eliminate these holes. 
     FIG. 3  illustrates bubble diagram  300 , which corresponds to the finite state machine table in  FIG. 2 . Each of states S 1 -S 10  is represented by a bubble and events E 1 -E 7  cause transitions between states. These transitions are represented by the arrowed lines connecting the state bubbles. The arrowhead determines the direction of the transition. 
   It is noted that in bubble diagram  300 , it is possible to groups states according to contexts of execution units.  FIG. 4  illustrates bubble diagram  400 , in which states of the finite state machine table in  FIG. 2  that are related to the same context are grouped together according to the principles of the present invention. The groupings of states form contexts C 0 , C 1 , C 2 , C 3  and C 4 . 
   Each of the groupings of states in  FIG. 4  may be used to create a context-based operation reconfigurable instruction set processor (CRISP) according to the principles of the present invention. Each of contexts C 0 -C 4  comprises a minimum number of input events and a set of probable operations. Each context also has its own data path, which may comprise parallel execution units while the instruction set execution may be either in a VLIW, SIMD, microcode or other known implementation manner to increase the overall performance. 
     FIG. 5  is a high-level block diagram of context-based operation reconfigurable instruction set processor (CRISP)  500 , according to an exemplary embodiment of the present invention. CRISP  500  comprises memory  510 , programmable data path circuitry  520 , programmable finite state machine  530 , and optional program memory  540 . CRISP  500  is designed to implement only a subset of context-related instructions from  FIG. 4  in an optimum manner. Each of the contexts C 0 -C 4  in  FIG. 4  may be implemented by a separate CRISP similar to CRISP  500 . Context-based operation reconfigurable instruction set processor (CRISP)  500  defines the generic hardware block that usually consists of higher level hardware processor blocks. The principle advantage to CRISP  500  is that CRISP  500  breaks down the required application into two main domains, a control domain and a data path domain, and optimize each domain separately. By implementing a data processor application, such as a mobile station handset (e.g., cell phone, wireless laptop), using CRISP  500 , the present invention at least partially overcomes the flexibility vs. power problems that adversely affect conventional data processor applications. 
   The control domain is implemented by programmable finite state machine  530 , which may comprise a DSP, an MCU or another prior art device. Programmable FSM  530  is configured by reconfiguration bits received from an external controller (not shown). Programmable FSM  530  may execute a program stored in associated optional program memory  540 . The program may be stored in program memory  540  via the DATA line from an external controller (not shown). Memory  510  is used to store application data used by data path circuitry  520 . 
   Programmable data path circuitry  520  is divided into a set of building blocks that perform particular functions (e.g., registers, multiplexers, multipliers, and the like). Each of building blocks is both reconfigurable and programmable to allow maximum flexibility. The criteria for dividing programmable data path circuitry  520  into functional blocks depends on the level of reconfigurability and programmability required for a particular application. 
   Since each of the contexts C 0 -C 4  in  FIG. 4  is implemented by a separate CRISP  500  that works independently of other CRISPs, the present invention provides an efficient power management scheme that is able to shut down a CRISP when the CRISP is not required to execute. This assures that only the CRISPs that are needed at a given time are active, while other idle CRISPs do not consume any significant power. 
   A CRISP according to the principles of the present invention may be targeted to many applications, such as, but not limited to, baseband applications in wireless devices and multimedia applications. In many applications, these contexts may be loosely-coupled independent contexts that may run concurrently with either minimum or no dependencies. 
     FIG. 6  is a high-level block diagram of reconfigurable processing system  600  according to an exemplary embodiment of the present invention. Reconfigurable processing system  600  comprises N context-based operation reconfigurable instruction set processors (CRISPs), including exemplary CRISPs  500   a ,  500   b , and  500   c , which are arbitrarily labeled CRISP  1 , CRISP  2  and CRISP N. Reconfigurable processing system  600  further comprises real-time sequencer  610 , sequence program memory  620 , programmable interconnect fabric  630 , and buffers  640  and  645 . 
   Reconfiguration bits may be loaded into CRISPs  500   a ,  500   b , and  500   c  from the CONTROL line via real-time sequencer  610  and buffer  640 . A control program may also be loaded into sequence program memory  620  from the CONTROL line via buffer  640 . Real-time sequencer sequences the contexts to be executed by each one of CRISPs  500   a - c  by retrieving program instructions from program memory  620  and sending reconfiguration bits to CRISPs  500   a - c . In an exemplary embodiment, real-time sequencer  610  may comprise a stack processor, which is suitable to operate as a real-time scheduler due to its low latency and simplicity. 
   Reconfigurable interconnect fabric  630  provides connectively between each one of CRISPs  500   a - c  and an external DATA bus via bi-directional buffer  645 . In an exemplary embodiment of the present invention, each one of CRISPs  500   a - c  may act as a master of reconfigurable interconnect fabric  630  and may initiate address access. The bus arbiter for reconfigurable interconnect fabric  630  may be internal to real-time sequencer  610 . 
   In an exemplary embodiment, reconfigurable processing system  600  may be, for example, a cell phone or a similar wireless device, or a data processor for use in a laptop computer. In a wireless device embodiment implemented according to a software-defined radio (SDR) principles, each one of CRISPs  500   a - c  is responsible for executing a subset of context-related instructions that are associated with a particular reconfigurable function. For example, CRISP  500   a  may be configured to execute context-related instructions that process CDMA baseband signals or OFDMA baseband signals. CRISP  500   b  may be configured to execute context-related instructions that act as a memory controller. CRISP  500   c  may be configured to execute context-related instructions that perform MPEG-4 processing for multimedia applications. 
   A CRISP according to the principles of the present invention provides a new way of implementing reconfigurable hardware acceleration techniques. The present invention provides reconfigurability and programmability with minimum sacrifice on power efficiency. Since the CRISPs are largely independent and may be run simultaneously, the present invention has the performance advantage of parallelism without incurring the full power penalty associated with running parallel operations. The loose coupling and independence of CRISPs allows them to be configured for different systems and functions that may be shut down separately. 
   Although the present invention has been described with an exemplary embodiment, various changes and modifications may be suggested to one skilled in the art. It is intended that the present invention encompass such changes and modifications as fall within the scope of the appended claims.