Abstract:
A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.

Description:
CROSS REFERENCE TO RELATED APPLICATION(S) 
       [0001]    This continuation application claims priority to U.S. patent application Ser. No. 15/050,678, filed Feb. 23, 2016, which application is hereby incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    The present embodiments relate to a memory circuit with leakage compensation of unselected memory cells. 
         [0003]    Shrinking semiconductor integrated circuit feature sizes have placed increasing challenges on semiconductor integrated circuit design. In particular, minimum feature sizes of high density memory cells are frequently less than corresponding feature sizes of peripheral circuits. As a result, leakage current in unselected memory cells (I LEAK ) may adversely affect correct sensing of a selected memory cell on a common bit line. This is particularly true of nonvolatile memories such as Flash EEPROM and ROM memories. However, this undesirable leakage current may also adversely affect standby current of volatile SRAM memories. Moreover, undesirable leakage current may compromise operation of both embedded memories in System on Chip (SoC) applications as well as stand-alone memories. Thus, there is a need to reduce leakage current in unselected memory cells for both nonvolatile and volatile memory systems. Accordingly, embodiments of the present invention described below are directed toward this and other improvements over the prior art. 
       BRIEF SUMMARY OF THE INVENTION 
       [0004]    In a first embodiment of the present invention, there is disclosed a memory array having a word line and a bit line. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line 
         [0005]    In a second embodiment of the present invention, there is disclosed a plurality of memory cells. Each memory cell has a first terminal, a second terminal, and a control terminal arranged to control current flow between the respective first and second terminals. A plurality of bit lines are connected to first terminals of respective memory cells. A bias circuit is arranged to apply a supply voltage to the second terminals of the memory cells in a first mode of operation and to apply a bias voltage different from the supply voltage to the second terminals in a second mode of operation. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING 
         [0006]      FIG. 1  is a diagram of an exemplary memory circuit according to the present invention; 
           [0007]      FIG. 2  is a simplified circuit diagram of memory blocks  106  and  108  of  FIG. 1 ; 
           [0008]      FIG. 3  is a circuit diagram of source line (SL) bias circuits  104  and  110  of  FIG. 1  coupled to respective memory blocks  106  and  108 ; 
           [0009]      FIG. 4  is a circuit diagram showing operation of memory sector  102  of  FIG. 1  during a memory read operation according to the present invention; and 
           [0010]      FIG. 5  is a timing diagram showing operation of memory sector  102  of  FIG. 4  during the memory read operation. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0011]    Referring to  FIG. 1 , there is a diagram of an exemplary memory circuit  100  according to the present invention. The memory circuit, often referred to as a macro, may be used for a System on a Chip (SoC), embedded memory, or stand alone memory applications. The diagram shows four memory sectors  102 ,  120 ,  130 , and  140 . Additional memory sectors may be included as indicated by ellipses. Each memory sector is substantially the same, so only memory sector  102  will be described in detail. In the following discussion, the same reference numerals are used to describe substantially the same circuit elements. Memory sector  102  includes memory blocks  106  and  108  and respective source line bias circuits  104  and  110  as will be described in detail. Each memory block includes N word lines (WL) and M bit lines (BL), where N and M are positive integers. Each word line corresponds to a respective row of memory cells, and each bit line corresponds to a respective column of memory cells. The choice of N and M depends on the memory requirements for a particular application. For example, N may be 256, 512, or other value and may include additional rows of memory cells for redundancy. Correspondingly M may be 256, 512, 1024, or other value and may include other columns of memory cells for redundancy or parity bits for error correction (ECC) memory. For example, N may be 256 or 512 and M may 2304, where 256 columns are dedicated to ECC parity bits 
         [0012]    The memory circuit of  FIG. 1  also includes row decode and drive circuit  114  to select appropriate word lines in response to applied address signals. A source line (SL) decode circuit  116  decodes applied address signals to control source line bias circuits  104  and  110  and may include corresponding control logic. High voltage drive circuit  118  decodes and applies high voltage signals to selected control gates (CG) and erase gates (EG) for programming and erasing memory cells of blocks  106  and  108 . Circuit  112  applies write drive (WRDRIVE) signals to write date to the memory cells. Circuit  112  also includes an 8:1 multiplex circuit to selectively couple a local bit line (LBL) signal to a global bit line (GBL). The global bit line is selectively coupled to a sense amplifier in circuit  122  by global bit line multiplexer GMUX. After amplification, data signals are subsequently multiplexed by a read multiplex (RMUX) circuit to input/output (I/O) terminals of the SoC. 
         [0013]    Referring next to  FIG. 2 , there is a simplified circuit diagram of memory blocks  106  and  108  of  FIG. 1 . Block  106  is coupled to receive word lines WL 0  through WL N/2-1  and control gate leads CG 0  through CG N/2-1 . Block  106  is also coupled to receive bit lines BL 0  through BL M-1 . Block  106  includes a memory cell formed at each intersection of a respective word line and bit line such as the memory cell formed by transistors  200  and  202  and the memory cell formed by transistors  204  and  206 . Transistor  202  provides access to floating gate transistor  202 . Likewise, transistor  204  provides access to floating gate transistor  206 . Transistors  202  and  206  have control gates coupled to receive signals CG 0  and CG N/2-1 , respectively. Transistors  202  and  206  also have respective floating erase gates (EG) indicated by dashed lines as is known in the art. The source of each floating gate transistor of block  106  is coupled to source line SL 104  from SL BIAS circuit  104 . 
         [0014]    Block  108  is similar to block  106  and is coupled to receive word lines WL N/2  through WL N-1  and control gate leads CG N/2  through CG N-1 . Block  108  is also coupled to receive bit lines BL 0  through BL M-1 , which are shared with block  106 . A memory cell is formed at each intersection of a respective word line and bit line of block  108  such as the memory cell formed by transistors  208  and  210  and the memory cell formed by transistors  212  and  214 . Transistor  208  provides access to floating gate transistor  210 . Likewise, transistor  212  provides access to floating gate transistor  214 . Transistors  210  and  214  have control gates coupled to receive signals CG N/2  and CG N-1 , respectively. Transistors  210  and  214  also have respective floating erase gates (EG) indicated by dashed lines as is known in the art. The source of each floating gate transistor of block  108  is coupled to source line SL 110  from SL BIAS circuit  110 . 
         [0015]    Turning now to  FIG. 3 , there is a circuit diagram of source line (SL) bias circuits  104  and  110  of  FIG. 1  coupled to respective memory blocks  106  and  108 . In the following discussion, transistor sizes are provided as width/length (W/L) in units of micrometers by way of explanation. One of ordinary skill in the art will understand that these transistor sizes are only provided by way of example and may vary with different values of N and M ( FIG. 1 ). SL bias circuit  104  includes n-channel transistor  300  (3.9/0.4) connected in series with n-channel transistor  302  (1.95/0.07) between supply voltage leads VDD (horizontal line) and VSS (small triangle). SL bias circuit  104  also includes n-channel transistor  304  (3.0/0.07) connected in series with n-channel transistor  306  (1.0/1.0) between source line SL 104  and supply voltage lead VSS. A common terminal  301  of transistors  300  and  302  is connected to a common terminal of transistors  304  and  306 . SL bias circuit  110  is similar to SL bias circuit  104  and includes n-channel transistor  310  (3.9/0.4) connected in series with n-channel transistor  312  (1.95/0.07) between supply voltage leads VDD and VSS. SL bias circuit  110  also includes n-channel transistor  314  (3.0/0.07) connected in series with n-channel transistor  316  (1.0/1.0) between source line SL 110  and supply voltage lead VSS. A common terminal  311  of transistors  310  and  312  is connected to a common terminal of transistors  314  and  316 . 
         [0016]    Operation of SL bias circuit  104  is similar to operation of SL bias circuit  110 , so only operation of SL bias circuit  104  will be described in detail. Transistor  300  is coupled to receive control signal VSF 104 , and transistor  302  is coupled to receive complementary control signal VSF 104 _OFF. When memory sector  102  is not accessed, control signals VSF 104  and VSF 104 _OFF are low and high, respectively. Thus, transistor  300  is off, transistor  302  is on, and lead  301  is driven to supply voltage VSS. Control signal VRD_BUF is held high, so transistors  304  and  306  are both on, and transistor  304  drives SL 104  to supply voltage VSS at lead  301 . In the same manner, control signals VSF 110  and VSF 110 _OFF are low and high, respectively, and transistor  314  drives SL 110  to supply voltage VSS at lead  311 . 
         [0017]    When a memory cell of block  108  is accessed in a read mode, control signals VSF 110  and VSF 110 _OFF remain low and high, respectively, and SL 110  remains at supply voltage VSS. Control signals VSF 104  and VSF 104 _OFF, however, transition to high and low levels, respectively. Thus, transistor  300  is on and transistor  302  is off. Transistor  300  acts as a source follower and drives lead  301  to an n-channel transistor threshold voltage below supply voltage VDD (VDD−Vtn). Control signal VRD_BUF remains high, so transistors  304  and  306  are both on. Thus, transistor  304  drives SL 104  to VDD−Vtn. Transistor  306  is a relatively high resistance transistor and acts as a bleeder or keeper device to assure lead  301  does not rise above VDD−Vtn. 
         [0018]    SL bias circuits of the present invention are highly advantageous for several reasons. First, access time to a memory cell in block  108  is not compromised, since SL 110  is held at supply voltage VSS during a read operation. Second, SL 104  is raised to VDD−Vtn when the memory cell in block  108  is accessed. Thus, memory cells in block  106  connected to the same bit line as the accessed memory cell of block  108  have greatly reduced leakage current. A typical read current of an erased memory cell is approximately 25 μA. The present inventors have determined that leakage of unselected memory cells on a selected bit line of the prior art, however, may be as much as 16 μA/kbit. This excessive leakage current adversely affects the signal-to-noise ratio (SNR) of data from an accessed memory cell. By further investigation, the present inventors have determined that raising a source line of unselected memory cells on a selected bit line by as little as 200 mV above supply voltage VSS will reduce leakage current by approximately two orders of magnitude (100×), thereby greatly improving the SNR of the accessed memory cell. Third, source follower transistor  300  quickly drives lead  301  to VDD−Vtn, so leakage current is reduced prior to sensing data from the accessed memory cell. Fourth, transistor  302  assures that lead  301  will not rise to a level greater than VDD−Vtn to adversely affect reliability. Finally, the SL bias circuits of the present invention produce no static power dissipation. Moreover, SL bias circuits such as SL bias circuit  104  may include several circuits such as transistors  300  through  306 , wherein each individual SL bias circuit is decoded by appropriate column address signals. Thus, source line capacitance driven by each SL bias circuit may be limited to memory cells of a few respective bit lines of a respective sector. 
         [0019]    Turning now to  FIG. 4 , is a circuit diagram showing operation of memory sector  102  of  FIG. 1  during a memory read operation according to the present invention. Operation of the circuit will be explained with reference to the timing diagram of  FIG. 5  for a read operation of the memory cell at the intersection of WL 0  and BL 0 . In the following discussion, transistors  400  and  402  represent all lumped memory cells in block  106  connected to BL 0 . Transistors  404  and  406  represent all lumped memory cells in block  108  connected to BL 0 . Initially, VSF 104  and VSF 110  are low (0.0 V) and VSF 104 _OFF and VSF 110 _OFF are high (1.2 V). VRD_BUF is high (3.0 V), so transistors  304 ,  306 ,  314 , and  316  are on. Source lines SL 104  and SL 110 , therefore, are held at VSS (0.0 V) by transistors  304  and  314 , respectively. At time t 0 , VSF 110  goes high (1.2 V), and VSF 110 _OFF goes low (0.0 V). As previously discussed, this drives SL 110  to VDD−Vtn (0.6 V). As a result, current I LEAK  through memory cell  404 / 406  is substantially zero. At time t 1 , word line WL 0  goes high (1.3 V) and turns on access transistor  200  ( FIG. 2 ). As a result, current I READ  flows through memory cell  200 / 202 , and current I LEAK ×(N/2−1) flows through the unselected memory cells of block  106  connected to bit line BL 0 . For large N, therefore, leakage current due to unselected memory cells connected to bit line BL 0  is advantageously reduced by half. Bit line BL 0  is selectively coupled to one input terminal of sense amplifier  412  by local bit line multiplex circuit  408  and global bit line multiplex circuit  410 . Reference current source  414  is coupled to the other input terminal of sense amplifier  412 . Sense amplifier  412  is initially precharged high, so the differential current at the input terminals produces a differential input voltage. At time t 2 , sense amplifier enable signal SAEN goes high (1.2 V) to amplify the difference voltage. Read multiplex circuit  416  selectively applies the amplified difference voltage (DATA) to output circuit  122 . 
         [0020]    As previously discussed, SL bias circuits of the present invention substantially improve the SNR at the sense amplifier. For example, if there are 256 memory cells on BL 0  (N=256), in each of blocks  106  and  108 , leakage current is reduced from 8 μA to 4 μA through BL 0 . Read current remains approximately 25 μA, so net current at the sense amplifier is 21 μA rather than 17 μA. This is a 24% improvement in signal strength at the sense amplifier. Of course, further SNR improvement is possible by increasing the number of blocks per sector, thereby increasing the number of source lines per bit line. For example, if there are four blocks in a sector with 128 memory cells on each source line, leakage current is reduced from 8 μA to 2 μA through BL 0 . Read current remains approximately 25 μA, so net current at the sense amplifier is 23 μA rather than 17 μA. This is a 35% improvement in signal strength at the sense amplifier. 
         [0021]    Still further, while numerous examples have thus been provided, one skilled in the art should recognize that various modifications, substitutions, or alterations may be made to the described embodiments while still falling with the inventive scope as defined by the following claims. For example, other circuit components may be used to increase the source line voltage of unselected memory cells on a selected bit line. Moreover, embodiments of the present invention are equally applicable to other memory circuits such as read only memory (ROM) circuits. Embodiments of the present invention may also be applied to static random access memory (SRAM) circuits or various logic circuits to reduce standby current. Other combinations will be readily apparent to one of ordinary skill in the art having access to the instant specification.