Abstract:
A data buffer stores both latest and past output data of respective stages. A coefficient buffer stores all coefficients required for each filter processing operation. In first filter processing, a filtering apparatus applies a product-sum operation to input data based on required data read from the data buffer and coefficient buffer. In succeeding filter processing, the filtering apparatus applies a product-sum operation to an output obtained in immediately preceding processing based on required data read from the data buffer and coefficient buffer.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The entire disclosure of Japanese Patent Application No. 2006-091507 including the specification, claims, drawings and abstract is incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a filtering apparatus that can apply multistage filter processing to input data. 
         [0004]    2. Description of the Related Art 
         [0005]    Various filters are conventionally used for various circuits. For example, an audio apparatus includes equalizers for multiple frequency bands to enable a user to individually adjust the intensity of an audio signal in each frequency band. The filtering characteristics of the respective filters can be differentiated for the corresponding frequency bands. Therefore, an audio signal having desired frequency characteristics can be obtained. 
         [0006]    If a filtering apparatus processes a digital audio signal, a digital analog converter (DAC) is required to apply conventional analog processing to digital audio data, and the circuit scale tends to become larger. Therefore, a digital filter can be preferably used to apply digital signal processing to digital audio data, as discussed in JP 2003-179466 A. 
         [0007]    If a frequency band is finely divided for multiple equalizers; e.g., when the frequency band is divided into eight bands, a total of eight filtering circuits are required. As a result, the circuit scale becomes larger. 
         [0008]    If a filtering apparatus includes a digital signal processor (DSP) that can perform software processing, the circuit scale will become larger for the DSP. 
       SUMMARY OF THE INVENTION 
       [0009]    The present invention can realize multistage filter processing using a single filter that can selectively provide set values and coefficients. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and, together with the description, serve to explain the principles of the invention, in which: 
           [0011]      FIG. 1  illustrates a filtering apparatus according an embodiment of the present invention; 
           [0012]      FIG. 2  illustrates a circuit arrangement for a filtering apparatus according to an embodiment of the present invention; 
           [0013]      FIG. 3  illustrates a filtering apparatus according an embodiment of the present invention; and 
           [0014]      FIG. 4  illustrates a filtering apparatus according an embodiment of the present invention. 
       
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0015]    Embodiments of the present invention will be described with reference to the drawings. 
         [0016]      FIG. 1  is an equivalent circuit illustrating equalizer processing performed by a filtering apparatus according an embodiment of the present invention. 
         [0017]    A multiplier  10 - 1  multiplies an input signal DIN (e.g., a PCM signal) by a coefficient a 01 . An adder  12 - 1  receives an output of the multiplier  10 - 1 . A delay circuit  14 - 1  stores a previous value (Z 10   −1 ) of the input signal DIN (i.e., 1-clock delayed input signal DIN). Furthermore, a delay circuit  16 - 1  stores a previous output (Z 20   −1 ) of the delay circuit  14 - 1  (i.e., 2-clock delayed input signal DIN). A multiplier  18 - 1  multiplies an output of the delay circuit  14 - 1  by a coefficient all. A multiplier  20 - 1  multiplies an output of the delay circuit  16 - 1  by a coefficient a 21 . The adder  12 - 1  receives an output of the multiplier  18 - 1  and an output of the multiplier  20 - 1 . Accordingly, the output Z 10   −1  of the delay circuit  14 - 1  is equal to the 1-clock delayed input signal DIN. The output Z 20   −1  of the delay circuit  16 - 1  is equal to the 2-clock delayed input signal DIN. 
         [0018]    A delay circuit  22 - 1  stores a previous output value (Z 11   −1 ) of the adder  12 - 1  (i.e., 1-clock delayed output of the adder  12 - 1 ). Furthermore, a delay circuit  24 - 1  stores a previous output value (Z 21   −1 ) of the delay circuit  22 - 1  (i.e., 2-clock delayed output of the adder  12 - 1 ). A multiplier  26 - 1  multiplies an output of the delay circuit  22 - 1  by a coefficient b 11 . A multiplier  28 - 1  multiplies an output of the delay circuit  24 - 1  by a coefficient b 21 . The adder  12 - 1  receives an output of the multiplier  26 - 1  and an output of the multiplier  28 - 1 . Accordingly, the output Z 11   −1  of the delay circuit  22 - 1  is equal to the 1-clock delayed output of the adder  12 - 1 . The output Z 21   −1  of the delay circuit  24 - 1  is equal to the 2-clock delayed output of the adder  12 - 1 . 
         [0019]    Through the above-described processing, the adder  12 - 1  produces an output signal of a 1st-stage equalizer EQ1 and supplies the produced signal to a 2nd-stage equalizer EQ2. 
         [0020]    Similar processing is performed in each of succeeding stages. Each equalizer inputs an output signal of the adder in the immediate preceding equalizer. In general, an input signal of n-th stage equalizer EQn is equal to an output signal of the adder  12 - n  in an immediate preceding equalizer EQn-1, where n is a number assigned to an equalizer EQn. 
         [0021]    Namely, an equalizer EQn inputs an output DOUT EQn-1 (0) of an immediately preceding equalizer EQn-1. In the immediately preceding equalizer EQn-1, two delay circuits  22 -( n− 1) and  24 -( n− 1) are provided at the output side. The delay circuit  22 -( n− 1) sets DOUT EQn-1 (−1) which is equal to a 1-clock delayed input signal, and the delay circuit  24 -( n− 1) sets DOUT EQn-1 (−2) which is equal to a 2-clock delayed input signal. In the equalizer EQn, the delay circuit  22 - n  sets DOUT EQn (−1) which is equal to a 1-clock delayed output signal and the delay circuit  24 - n  sets DOUT EQn (−2) which is equal to a 2-clock delayed output signal. 
         [0022]    The filtering apparatus of the present embodiment performs the following calculations for first to fourth equalizers illustrated in  FIG. 1 . 
         [0023]    The first-stage equalizer produces an output DOUT EQ1 =(DIN·a 01 )+(Z 10   −1 ·a 11 )+(Z 20   −1 ·a 21 )+(Z 11   −1 ·b 11 )+(Z 21   −1 ·b 21 ), where Z 10   −1  is equal to a 1-clock delayed DIN, Z 20   −1  is equal to a 2-clock delayed DIN, Z 11   −1  is equal to a 1-clock delayed DOUT EQ1 , and Z 21   −1  is equal to a 2-clock delayed DOUT EQ1 . 
         [0024]    The second-stage equalizer produces an output DOUT EQ2 =(DOUT EQ1 ·a 02 )+(Z 11   −1 ·a 12 )+(Z 21   −1 ·a 22 )+(Z 12   −1 ·b 12 )+(Z 22   −1 ·b 22 ), where Z 11   −1  is equal to a 1-clock delayed DOUT EQ1 , Z 21   −1  is equal to a 2-clock delayed DOUT EQ1 , Z 12   −1  is equal to a 1-clock delayed DOUT EQ2 , and Z 22   −1  is equal to 2-clock delayed DOUT EQ2 . 
         [0025]    The third-stage equalizer produces an output DOUT EQ3 =(DOUT EQ2 ·a 03 )+(Z 12   −1 ·a 13 )+(Z 22   −1 ·a 23 )+(Z 13   −1 ·b 13 )+(Z 23   −1 ·b 23 ), where Z 12   1  is equal to a 1-clock delayed DOUT EQ2 , Z 22   1  is equal to a 2-clock delayed DOUT EQ2 , Z 13   −1  is equal to a 1-clock delayed DOUT EQ3 , and Z 23   −1  is equal to a 2-clock delayed DOUT EQ3 . 
         [0026]    The fourth-stage equalizer produces an output DOUT EQ4 =(DOUT EQ3 ·a 04 )+(Z 13   −1 ·a 14 )+(Z 23   −1 ·a 24 )+(Z 14   −1 ·b 14 )+(Z 24   −1 ·b 24 ), where Z 13   −1  is equal to a 1-clock delayed DOUT EQ3 , Z 23   −1  is equal to a 2-clock delayed DOUT EQ3 , Z 14   −1  is equal to a 1-clock delayed DOUT EQ4 , and Z 24   −1  is equal to a 2-clock delayed DOUT EQ4 . 
         [0027]    The present embodiment does not use four equalizers to realize the filter processing illustrated in  FIG. 1 . Rather, the present embodiment uses only one equalizer to successively perform the aforementioned processing for the first to fourth equalizers. 
         [0028]      FIG. 2  illustrates an arrangement of a filtering apparatus according to a preferred embodiment. A data buffer  30  inputs an input signal DIN. The data buffer  30  stores input and output data in the preceding processing as well as previous input and output data stored in the delay circuits. 
         [0029]    For example, the 1st-stage processing requires DIN, Z 10   −1 , Z 20   −1 , Z 11   −1 , and Z 21   −1 . When a present DIN is DIN(0), an output DOUT EQ1 (0) can be calculated if DIN(−1), DIN(−2), DOUT EQ1 (−1), and DOUT EQ1 (−2) are known. Hence, the data buffer  30  stores present and preceding input and output signals for the equalizers of respective stages. Thus, the data buffer  30  can store Z 10   −1 , Z 20   −1 , Z 11   −1 , and Z 21   −1  for the 1st-stage equalizer. 
         [0030]    Furthermore, a coefficient buffer  32  stores coefficients a 0n , a 1n , a 2n , b 1n , and b 2n  (n=1 to 4 according to the example illustrated in  FIG. 2 ) for each-stage equalizer. 
         [0031]    An output of the data buffer  30  and an output of the coefficient buffer  32  are supplied to a multiplier  34 . For example, in the first filter processing, the data buffer  30  outputs DIN and the coefficient buffer  32  outputs a coefficient a 01 . The multiplier  34  produces an output (DIN·a 01 ). A flip-flop circuit  36  can input the output (DIN·a 01 ) of the multiplier  34  in synchronism with a clock signal CLK. 
         [0032]    An output of the flip-flop circuit  36  is supplied to an adder  38 . An output of the adder  38  can be supplied to an input terminal of the adder  38  via a multiplexer  40  and a flip-flop circuit  42  that can input a signal in synchronism with a clock signal CLK. The multiplexer  40  can select “0” or an output of the adder  38  according to an adder input control signal. Accordingly, if the multiplexer  40  selects an output of the adder  38 , the output of the adder  38  can be added to a new output of the multiplier  34 . 
         [0033]    In other words, the filtering apparatus according to the present embodiment can perform an accumulative calculation by successively adding the output of the adder  38  to a new output of the multiplier  34 . Hence, the data buffer  30  successively outputs DIN, Z 10   −1 , Z 20   −1 , Z 11   −1 , and Z 21   −1 , while the coefficient buffer  32  successively outputs a 01 , a 11 , a 21 , b 11 , and b 21 . Through the above-described sequential multiplicative and additive processing, the adder  38  can produce an output DOUT EQ1 =(DIN·a 01 )+(Z 10   −1 ·a 11 )+(Z 20   −1 ·a 21 )+(Z 11   −1 ·b 11 )+(Z 21   −1 ·b 21 ) at the fourth output timing. 
         [0034]    When the above-described calculation processing for the first equalizer is completed, the obtained DOUT EQ1  is supplied to the data buffer  30 . Then, the second filter processing is performed to calculate DOUT EQ2 . More specifically, the data buffer  30  successively outputs DOUT EQ1 , Z 11   −1 , Z 21   −1 , Z 12   −1 , and Z 22   −1  and the coefficient buffer  32  successively output a 02 , a 12 , a 22 , b 12 , and b 22 . Through the above-described multiplicative and additive processing, the adder  38  can produce an output DOUT EQ2 =(DOUT EQ1 ·a 02 )+(Z 11   −1 ·a 12 )+(Z 21   −1 ·a 22 )+(Z 12   −1 ·b 12 )+(Z 22   −1 ·b 22 ). The obtained DOUT EQ2  is stored in the data buffer  30 . 
         [0035]    Furthermore, in the third filter processing, the filtering apparatus according to the present embodiment can produce an output DOUT EQ3 =(DOUT EQ2 ·a 03 )+(Z 12   −1 ·a 13 )+(Z 22   −1 ·a 23 )+(Z 13   −1 ·b 13 )+(Z 23   −1 ·b 23 ). The obtained DOUT EQ3  is stored in the data buffer  30 . In the fourth filter processing, the filtering apparatus according to the present embodiment can produce an output DOUT EQ4 =(DOUT EQ3 ·a 04 )+(Z 13   −1 ·a 14 )+(Z 23   −1 ·a 24 )+(Z 14   1 ·b 14 )+(Z 24   −1 ·b 24 ). The obtained DOUT EQ4  is stored in the data buffer  30 . Thus, the filtering apparatus finally produces an output equal to DOUT EQ4 . 
         [0036]    A flip-flop circuit  46  can input an output of the adder  38  via a multiplexer  44  in synchronism with a clock signal CLK. The multiplexer  44  selects an output of the adder  38  or an output of the flip-flop circuit  46  based on a data output control signal. The data output control signal is controlled so that the multiplexer  44  can select an output of the adder  38  at the timing the above-described sequential filter processing for first to fourth equalizers. Accordingly, the filtering apparatus illustrated in  FIG. 2  can successively produce DOUT EQ4  from the flip-flop circuit  44  each time the four-stage filter processing is completed. 
         [0037]      FIG. 3  illustrates hardware elements required for single filter processing according to an embodiment of the present invention, which is comparable to the arrangement illustrated in  FIG. 1 . 
         [0038]    According to the arrangement illustrated in  FIG. 3 , data DIN is input to a multiplexer  50 . An output of an adder  12  is also input to the multiplexer  50 . The multiplexer  50  selects DIN in the first filter processing (n=1) and selects an output of the adder  12  in the succeeding filter processing (n&gt;1); i.e., DOUT EQ1  in the second filter processing, DOUT EQ2  in the third filter processing, and DOUT EQ3  in the fourth filter processing. 
         [0039]    The adder  12  can produce an output via a gate  52  which opens only in the final (i.e., fourth) filter processing (n=4). Therefore, the filtering apparatus according to the present embodiment can produce an output DOUT EQ4  from the gate  52  through the fourth-stage filter processing. If necessary, the circuit can produce DOUT EQ1 , or DOUT EQ2 , or DOUT EQ3  from the gate  52 . 
         [0040]    Delay circuits  14 ,  16 ,  22 , and  24  are capable of arbitrarily shifting set values. More specifically, the set values in the delay circuits  14  and  22  are Z 10   −1  and Z 11   −1  in the first filter processing, Z 11   −1  and Z 12   −1  in the second filter processing, Z 12   −1  and Z 13   −1  in the third filter processing, and Z 13   −1  and Z 14   −1  in the fourth filter processing. Hence, as illustrated in  FIG. 3 , the filtering apparatus according to the present embodiment includes a barrel shifter that can successively shift the values Z 10   −1 , Z 11   −1 , Z 12   −1 , Z 13   −1 , and Z 14   −1  which are prepared beforehand. 
         [0041]    The set values in the delay circuits  16  and  24  are Z 20   −1  and Z 21   −1  in the first filter processing, Z 21   −1  and Z 22   −1  in the second filter processing, Z 22   −1  and Z 23   −1  in the third filter processing, and Z 23   −1  and Z 24   −1  in the fourth filter processing. Hence, as illustrated in  FIG. 3 , the filtering apparatus according to the present embodiment includes a barrel shifter that can successively shift the values Z 20   −1 , Z 21   −1 , Z 22   −1 , Z 23   −1 , and Z 24   −1  which are prepared beforehand. 
         [0042]    The values Z 10   −1 , Z 11   −1 , Z 12   −1 , Z 13   −1 , and Z 14   −1  are obtained in the immediately preceding processing, where Z 10   −1  is equal to input data DIN(−1), Z 11   −1  is equal to an output DOUT EQ1 (−1) of the 1st-stage equalizer, Z 12   −1  is equal to an output DOUT EQ2 (−1) of the 2nd-stage equalizer, Z 13   −1  is equal to an output DOUT EQ3 (−1) of the 3rd-stage equalizer, and Z 14   −1  is equal to an output DOUT EQ4 (−1) of the 4th-stage equalizer. 
         [0043]    The values Z 20   −1 , Z 21   −1 , Z 22   −1 , Z 23   −1 , and Z 24   −1  are obtained in processing preceding the immediately preceding processing, where Z 20   −1  is equal to input data DIN(−2), Z 21   −1  is equal to an output DOUT EQ1 (−2) of the 1st-stage equalizer, Z 22   −1  is equal to an output DOUT EQ2 (−2) of the 2nd-stage equalizer, Z 23   −1  is equal to an output DOUT EQ3 (−2) of the 3rd-stage equalizer, and Z 24   −1  is equal to an output DOUT EQ4 (−2) of the 4th-stage equalizer. 
         [0044]    Furthermore, multipliers  18 ,  20 ,  26 , and  28  can successively switch the coefficients multiplied to the set values of the delay circuits. Preferably, the barrel shifters shift the set values two more times at the timing the four-stage filter processing is accomplished, because the contents of the delay circuits can be returned to their initial values. Subsequently, the set values of the delay circuits in the upper barrel shifter can be shifted to the delay circuits in the lower barrel shifter. 
         [0045]    As apparent from the foregoing description, the 4-stage filtering processing requires calculations based on input data DIN in the present processing, input data in immediately preceding processing and one more preceding processing, and output DOUT EQN  (n=1 to 4) of respective stages calculated in the immediately preceding processing and the one more preceding processing. These data are stored in the barrel shifters that can shift the values in predetermined sequences for the filtering calculations of respective stages. 
         [0046]    Upon completion of one round of multistage filter processing including calculations for first to fourth equalizers, the input data in the present processing and the outputs of four stages are input to Z 10   −1 , Z 11   −1 , Z 12   −1 , Z 13   −1 , and Z 14   −1 . Then, the values having been stored in the Z 10   −1 , Z 11   −1 , Z 12   −1 , Z 13   −1 , and Z 14   −1  are shifted to Z 20   −1 , Z 21   −1 , Z 22   −1 , Z 23   −1 , and Z 24   −1 , respectively. 
         [0047]      FIG. 4  illustrates another arrangement of a filtering apparatus capable of functioning in the same manner as the circuit illustrated in  FIG. 3 . According to the arrangement illustrated in  FIG. 4 , data DIN is input to an adder  60 . A multiplier  62  multiplies an output of the adder  60  by a predetermined coefficient. Then, an output of the multiplier  62  is input to an adder  64 . The adder  64  produces a filtered output. 
         [0048]    A delay circuit  66  receives an output of the adder  60 . Another delay circuit  68  receives an output of the delay circuit  66 . An output of the delay circuit  66  is returned to the adder  60  via a multiplier  70 . Furthermore, an output of the delay circuit  66  is supplied to the adder  64  via a multiplier  74 . An output of the delay circuit  68  is returned via a multiplier  72  to the adder  60 . Furthermore, an output of the delay circuit  68  is supplied to the adder  64  via a multiplier  76 . 
         [0049]    The circuit illustrated in  FIG. 4  can realize filter processing similar to the processing realized by the circuit illustrated in  FIG. 3 . As described above, the present embodiment can successively perform filter processing for respective stages by using an output of the adder  64  as an input for succeeding filter processing. In the filter processing for each stage, the present embodiment successively changes the coefficients of the delay circuits  66  and  68  and the multipliers  70 ,  72 ,  74 , and  76 . According to the example illustrated in  FIG. 4 , a selection signal SEL is supplied to the delay circuits  66  and  68  and the multipliers  70 ,  72 ,  74 , and  76  to select the coefficients and data.