Abstract:
The invention relates to a device for calculating FSM bits by means of which the signals sent from two antennas of a base station are influenced with reference to their phase difference and/or their amplitudes. The FSM bits are calculated with the aid of two estimated channel impulse responses. The device is present in hard-wired form.

Description:
RELATED APPLICATION 
     This application is a national stage application of International Application No. PCT/DE03/01036 filed Mar. 28, 2003, which is entitled “DEVICE FOR CALCULATING FSM BITS IN THE UMTS STANDARD”, which was not published in English, and claims priority to German Patent Application Serial No. 102 17 853.4, which was filed on Apr. 22, 2002, which is hereby incorporated by reference in its entirety. 
     FIELD OF THE INVENTION 
     The invention relates to a device with the aid of which it is possible to calculate the FSM bits that determine the antenna weightings of a base station; particularly in the UMTS standard. 
     BACKGROUND OF THE INVENTION 
     In the case of a mobile radio system that comprises a base station with two antennas and a mobile radio subscriber, a fixed phase relationship is set up between the two transmission channels, which are to be assigned in each case to one of the antennas of the base station. In the UMTS (Universal Mobile Telecommunications System) standard, a so-called CLTD (Closed Loop Mode Transmit Diversity) function can be used to influence the relationship of the signals emitted by two antennas in order thereby to achieve constructive interference of the two transmission channels. The CLTD function can be operated in a mode 1 and a mode 2. The phase of one of the two antennas can be varied in mode 1. The phase of the other antenna remains fixed. The overall result is to vary the phase relationship between the two antennas. In addition to the variation, known from mode 1, in the phase relationship, mode 2 provides a variation in the amplitudes of the signals emitted from the antennas. The amplitudes of both antennas can be varied in mode 2. 
     The CLTD function is described in the 3GPP TS 25.214 UMTS specification. This specification is referenced repeatedly below. All data refer in this case to the V4.2.0 (2001-09) version. 
     FSM (Feedback Signalling Message) data words that are transmitted to the base station are formed in the mobile radio terminal from estimated channel impulse responses by means of the CLTD function. The channel impulse responses of both channels are always used in this case for an FSM data word. The FSM data words include information specific to the base station and relating to the optimum phase relationship and, if appropriate, relating to the optimum amplitudes of the signals to be emitted from the two antennas. 
     Two antenna weightings w 1  and w 2  that are applied to the signals which are to be emitted from the two antennas are formed in the base station from an FSM data word. The antenna weightings w 1  and w 2  are complex and have the following form:
 
 w   1 =α 1   +jβ   1   (1)
 
 w   2 =α 2   +jβ   2   (2)
 
     Two diversity components are evaluated by multiplying the signals to be emitted by the antenna weightings w 1  and w 2 . In this case, the antenna weightings w 1  and w 2  are selected with the aim of maximizing per slot the energy received by the mobile radio terminal while taking account of the weight quantization prescribed in the UMTS standard. This is equivalent to maximizing a proportionality factor P that is given by the following equation: 
     
       
         
           
             
               
                 
                   P 
                   = 
                   
                     
                       
                         
                           
                             w 
                             → 
                           
                           H 
                         
                         ⁡ 
                         
                           [ 
                           
                             
                               
                                 
                                   H 
                                   11 
                                 
                               
                               
                                 
                                   H 
                                   12 
                                 
                               
                             
                             
                               
                                 
                                   H 
                                   21 
                                 
                               
                               
                                 
                                   H 
                                   22 
                                 
                               
                             
                           
                           ] 
                         
                       
                       ⁢ 
                       
                         w 
                         → 
                       
                     
                     = 
                     
                       
                         
                           
                             w 
                             → 
                           
                           H 
                         
                         ⁡ 
                         
                           ( 
                           
                             
                               ∑ 
                               
                                 m 
                                 = 
                                 1 
                               
                               M 
                             
                             ⁢ 
                             
                               
                                 H 
                                 m 
                                 H 
                               
                               ⁢ 
                               
                                 H 
                                 m 
                               
                             
                           
                           ) 
                         
                       
                       ⁢ 
                       
                         w 
                         → 
                       
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
     Here, the index m denotes the respective base station m (m=1, . . . , M). Furthermore, it holds for the matrix H m  and the vector w that:
 
H m =[{right arrow over (h)} m,1 ,{right arrow over (h)} m,2 ]  (4)
 
{right arrow over (w)}=[w 1 ,w 2 ] T   (5)
 
     The indices 1 and 2 relate to two antennas i of a base station m. {right arrow over (h)} m,i  are complex (N m ×1) vectors that stand for the channel impulse responses estimated by the channel estimator with a channel depth N m . Each vector {right arrow over (h)} m,i  is to be associated with one of the antennas i of the base station m. It is to be assumed without loss of generality for the following considerations that only one base station m is sending (M=1). The index m is therefore omitted below, thus simplifying equation (4):
 
H=[{right arrow over (h)} 1 ,{right arrow over (h)} 2 ]  (6)
 
With i, j=1, 2, it holds for the elements H ij  of the matrix from equation (3) that:
 
     
       
         
           
             
               
                 
                   
                     
                       H 
                       
                         i 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         j 
                       
                     
                     = 
                     
                       
                         
                           
                             h 
                             → 
                           
                           i 
                           H 
                         
                         ⁢ 
                         
                           
                             h 
                             → 
                           
                           j 
                         
                       
                       = 
                       
                         
                            
                           
                             H 
                             
                               i 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               j 
                             
                           
                            
                         
                         ⁢ 
                         
                           ⅇ 
                           
                             jφ 
                             
                               H 
                               
                                 i 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 j 
                               
                             
                           
                         
                       
                     
                   
                   , 
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
           
         
       
     
     |H ij | specifying a modulus and φ H     ij    phase angle. 
     Consequently, the technical problem to be solved includes a determination of the antenna weightings w 1  and w 2  per slot in such a way that the proportionality factor P is maximized for given estimated channel impulse responses {right arrow over (h)} i =[h i,1 , . . . , h i,n , . . . , h i,N ] T . The boundary conditions for the value ranges of the antenna weightings w 1  and w 2  are to be observed in this process. 
     The following boundary conditions hold for the antenna weightings w 1  and w 2  in mode 1 of the CLTD function: 
     
       
         
           
             
               
                 
                   
                     w 
                     1 
                   
                   = 
                   
                     1 
                     
                       2 
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
             
               
                 
                   
                     w 
                     2 
                   
                   = 
                   
                     
                       1 
                       
                         2 
                       
                     
                     ⁢ 
                     
                       ⅇ 
                       
                         j 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         
                           φ 
                           2 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   9 
                   ) 
                 
               
             
             
               
                 
                   
                     φ 
                     2 
                   
                   ∈ 
                   
                     { 
                     
                       0 
                       , 
                       
                         π 
                         2 
                       
                       , 
                       π 
                       , 
                       
                         - 
                         
                           π 
                           2 
                         
                       
                     
                     } 
                   
                 
               
               
                 
                   ( 
                   10 
                   ) 
                 
               
             
           
         
       
     
     In this case, the phase angle φ 2 (s) is a function of the slot index s (s=1, 2, . . . , S). More detailed explanations of this are to be found in section 7.2 of the 3GPP TS 25.214 V4.2.0 UMTS specification. 
     The following boundary conditions hold for the antenna weightings w 1  and w 2  in mode 2 of the CLTD function: 
     
       
         
           
             
               
                 
                   
                     w 
                     1 
                   
                   = 
                   
                     
                       E 
                       1 
                     
                   
                 
               
               
                 
                   ( 
                   11 
                   ) 
                 
               
             
             
               
                 
                   
                     w 
                     2 
                   
                   = 
                   
                     
                       
                         E 
                         2 
                       
                     
                     ⁢ 
                     
                       ⅇ 
                       
                         j 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         
                           φ 
                           2 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   12 
                   ) 
                 
               
             
             
               
                 
                   
                     E 
                     1 
                   
                   , 
                   
                     
                       E 
                       2 
                     
                     ∈ 
                     
                       { 
                       
                         0.2 
                         , 
                         0.8 
                       
                       } 
                     
                   
                 
               
               
                 
                   ( 
                   13 
                   ) 
                 
               
             
             
               
                 
                   
                     
                       E 
                       1 
                     
                     + 
                     
                       E 
                       2 
                     
                   
                   = 
                   1 
                 
               
               
                 
                   ( 
                   14 
                   ) 
                 
               
             
             
               
                 
                   
                     φ 
                     2 
                   
                   ∈ 
                   
                     { 
                     
                       0 
                       , 
                       
                         π 
                         4 
                       
                       , 
                       
                         π 
                         2 
                       
                       , 
                       
                         
                           3 
                           ⁢ 
                           π 
                         
                         4 
                       
                       , 
                       π 
                       , 
                       
                         - 
                         
                           π 
                           4 
                         
                       
                       , 
                       
                         - 
                         
                           π 
                           2 
                         
                       
                       , 
                       
                         - 
                         
                           
                             3 
                             ⁢ 
                             π 
                           
                           4 
                         
                       
                     
                     } 
                   
                 
               
               
                 
                   ( 
                   15 
                   ) 
                 
               
             
           
         
       
     
     Here, the amplitudes E 1 (s) and E 2 (s) as well as the phase angle φ 2 (s) are functions of the slot index s (s=1, 2, . . . , S). Mode 2 is described in more detail in section 7.3 of the 3GPP TS 25.214 V4.2.0 UMTS specification. 
     To date, the optimum values for the phase angle φ 2 (s) and, if appropriate, for the amplitudes E 1 (s) and E 2 (s) have been determined as a function of the mode and slot index s by parameterizing equation (3) or by substituting the values in question. In this process, it is necessary in mode 1 to make a selection from only two phase angle values per slot. By contrast, it is necessary in mode 2 to evaluate 16 combinations of amplitude and phase angle. This problem has been solved to date by means of a digital signal processor because of the structure of the calculating algorithm. In this process, the digital signal processor generates on the output side an FSM data word which consists of FSM bits and includes information relating to the optimum values for the phase angle φ 2 (s) and, if appropriate, for the amplitudes E 1 (s) and E 2 (s). 
     SUMMARY OF THE INVENTION 
     It is an object of the invention to create a device with the aid of which FSM bits can be determined as a function of the mode and slot index in a particularly efficient fashion. A corresponding method for calculating the FSM bits is also to be specified. 
     The device according to the invention serves for calculating FSM bits by means of which the signals sent from two antennas of a base station are influenced with reference to their phase difference and/or their amplitudes. The FSM bits are calculated with the aid of two estimated channel impulse responses. In this process, a channel impulse response is related in each case to the channel belonging to one of the antennas. An essential idea of the invention resides in the fact that the device is hard-wired. It is therefore present as a hardware circuit. 
     Owing to the hardware design of the device according to the invention, the latter can carry out the required calculations substantially more efficiently than a digital signal processor. Furthermore, the device according to the invention is more favorable in terms of outlay than a digital signal processor. 
     The device forms a complex phasor from components of the two channel impulse responses and then generates an FSM bit by means of rotation and projection of the phasor and, in particular, of a threshold value decision. In particular, the channel coefficients, which are combined in a channel impulse response for each channel, can be complex. It is then also possible for the real or imaginary part of a channel coefficient to form a component of a channel impulse response. 
     The device advantageously has inputs, control inputs and an output. Components of the two channel impulse responses are applied to the inputs, and control signals are applied to the control inputs. This permits the device to calculate the FSM bit as a function of the components of the two channel impulse responses and the control signals. The FSM bit can be tapped at the output of the device. 
     A preferred refinement of the invention provides that the device includes a logic unit and a processing unit that is connected downstream of the logic unit. 
     The logic unit preferably has an equal number of inputs and outputs. The components of the two channel impulse responses are present at the inputs of the logic unit. The inputs of the logic unit are connected to the outputs of the logic unit as a function of at least one control signal. 
     In accordance with a further preferred refinement of the invention, a multiplier stage, an adder, a weighting stage, an accumulator and a threshold value decision unit are arranged in series in the processing unit. 
     It can preferably be provided in this case that the multiplier stage includes two multipliers that in each case multiply by one another two values supplied by the logic unit. For this purpose, the inputs of the multipliers are connected in each case to two outputs of the logic unit. The multiplication results for the two multipliers are added by the adder. 
     The sum formed by the adder is advantageously multiplied by a weighting factor in the weighting stage. The weighting factor results from a control signal that is present at the weighting stage. 
     A particularly preferred refinement of the invention is characterized in that the control signals are stored in the form of control bits in a read-only memory. This measure permits a calculating speed of the FSM bits that is higher by comparison with a digital signal processor. 
     The device according to the invention is, furthermore, designed with particular preference for the UMTS standard. 
     In the case of a device operating according to the UMTS standard, the control signals are preferably a function both of the slot number of the FSM bit whose calculation is pending at this instant, and of the CLTD mode. Owing to this refinement, the device is designed with sufficient flexibility to be able to carry out different types of calculations for all combinations of slot number and CLTD mode. 
     In accordance with a preferred refinement of the invention, the values of the control signals are a function of whether the slot number is an even or odd number. 
     The device according to the invention can be implemented with particular advantage in the associated mobile radio terminal. 
     FSM bits are calculated by means of the method according to the invention using two estimated channel impulse responses. In a first method step, a complex phasor is produced from components of the two channel impulse responses. In a second method step, this phasor is used to calculate an FSM bit by means of rotation, projection and, in particular, a threshold value decision. The method according to the invention is distinguished by a particularly efficient and quick calculation of the FSM bit. 
    
    
     
       BRIEF DESCRIPTIONS OF THE DRAWINGS 
       The invention is explained below in more detail by way of example with reference to the drawings, in which: 
         FIG. 1  shows a schematic block diagram of an exemplary embodiment of the device according to the invention; 
         FIG. 2  shows a diagram of the mode of operation of the device according to the invention in the plane of complex numbers for mode 1; and 
         FIG. 3  shows a diagram of the mode of operation of the device according to the invention in the plane of complex numbers for mode 2. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A circuit  1  is illustrated in  FIG. 1  as an exemplary embodiment for the device according to the invention. The circuit  1  comprises logic units  2  and  3 , multipliers  4  and  5 , an adder  6 , a weighting unit  7 , an accumulator  8  and a threshold value decision unit  9 . 
     The logic unit  2  has inputs In 1 , In 2 , In 3  and In 4 , configuration inputs Config 1  and Config 2  and outputs Out 1 , Out 2 , Out 3  and Out 4 . The inputs In 1 , In 2 , In 3  and In 4  of the logic unit  2  are simultaneously inputs of the circuit  1 . The logic unit  3  has inputs In 5  and In 6 , configuration inputs Config 3 , Config 4  and Config 5  and outputs Out 5  and Out 6 . The multipliers  4  and  5  and the adder  6  each have two inputs and one output. The weighting unit  7 , the accumulator  8  and the threshold value decision unit  9  respectively comprise an input and an output. Furthermore, the weighting unit  7  includes a configuration input Config 6 . The output of the threshold value decision unit  9  constitutes the output of the circuit  1 . 
     The output Out 3  of the logic unit  2  is connected to the input In 5  of the logic unit  3 . The output Out 4  of the logic unit  2  is connected to the input In 6  of the logic unit  3 . 
     One input of the multiplier  4  is coupled to the output Out 1  of the logic unit  2 . The second input of the multiplier  4  is coupled to the output Out 5  of the logic unit  3 . 
     One input of the multiplier  5  is coupled to the output Out 2  of the logic unit  2 . The second input of the multiplier  5  is coupled to the output Out 6  of the logic unit  3 . 
     The outputs of the multipliers  4  and  5  feed the inputs of the adder  6 . Connected downstream of the adder  6  are the weighting unit  7 , the accumulator  8  and the threshold value decision unit  9  in the prescribed sequence. 
     The circuit  1  is integrated in this case in a mobile radio terminal operating in accordance with the UMTS standard, and serves for generating FSM bits. The FSM bits are subsequently transmitted to the associated base station in which antenna weightings are produced from the FSM bits. 
     The base station has two antennas. Consequently, complex channel coefficients h i,n  with a channel depth N are calculated by a channel estimator for two channels i (i=1, 2; n=1, 2, . . . , N). The channel coefficients h i,n  are combined for each channel i to form an N-component vector as channel impulse response {right arrow over (h)} i =[h i,1 , . . . , h i,n , . . . , h i,N ] T . During the duration of a slot s, the real and imaginary parts of the channel coefficients h 1,n  and h 2,n  are present at the inputs In 1 , In 2 , In 3  and In 4  of the circuit  1 . The configuration bits C 1,k (s), C 2,k (s), . . . , C 6,k (s) are present at the configuration inputs Config  1 , Config  2 , . . . , Config  6 . In accordance with the 3GPP TS 25.214 V4.2.0 UMTS specification, the slot index s runs from 1 to 15. The clock index k-runs through the integral values from 1 to 2N. The path index n and the clock index k are in the ratio 1:2. This means that a channel coefficient h i,n  is present two system clocks for processing on the circuit  1 . 
     The mode of operation of the circuit  1  is as follows. The logic units  2  and  3  connect their inputs In 1 , . . . , In 6  to their outputs Out 1 , . . . , Out 6  as a function of the configuration bits C 1,k (s), . . . , C 5,k (s). This produces a complex number a k +jb k  at the outputs Out 1  and Out 2 , a complex number c k +jd k  at the outputs Out 3  and Out 4 , and a complex number e k +jf k  at the outputs Out 5  and Out 6 . On the output side, the multipliers  4  and  5  produce real numbers A k  and B k , respectively, the adder  6  produces a real number S k , and the weighting unit  7  produces a real number R k  as a function of the configuration bit C 6,k (s). The accumulator  8  accumulates over twice the channel depth 2N, and produces a variable X(s) on the output side. The threshold value decision unit  9  uses the variable X(s) to generate an FSM bit FSM(s) with the aid of the following distinction between cases:
 
 X ( s )&lt;0             FSM ( s )=0  (16)
 
 X ( s )≧0           FSM ( s )=1  (16)

     The following Table 1 gives the precise mode of operation of the circuit  1 : 
     
       
         
               
               
               
               
             
               
               
               
               
               
               
             
               
               
               
               
             
           
               
                   
               
             
             
               
                   
                   
                   
                 C 1,k (s), 
               
               
                 No. 
                 a k  + jb k   
                 c k  + jd k   
                 C 2,k (s) 
               
               
                   
               
               
                 1. 
                 k even: Re{h 1,n (s)} + 
                 k even: Re{h 2,n (s)} + 
                 1, 1 
               
               
                   
                 jIm{h 1,n (s)} 
                 jIm{h 2,n (s)} 
               
               
                   
                 k odd: 0 
                 k odd: 0 
                 X 
               
               
                 2. 
                 k even: Re{h 1,n (s)} + 
                 k even: Re{h 2,n (s)} + 
                 1, 1 
               
               
                   
                 jIm{h 1,n (s)} 
                 jIm{h 2,n (s)} 
               
               
                   
                 k odd: 0 
                 k odd: 0 
                 X 
               
               
                 3. 
                 Re{h 1,n (s)} + 
                 Re{h 2,n (s)} + 
                 1, 1 
               
               
                   
                 jIm{h 1,n (s)} 
                 jIm{h 2,n (s)} 
               
               
                 4. 
                 Re{h 1,n (s)} + 
                 Re{h 2,n (s)} + 
                 1, 1 
               
               
                   
                 jIm{h 1,n (s)} 
                 jIm{h 2,n (s)} 
               
               
                 5. 
                 Re{h 1,n (s)} + 
                 Re{h 2,n (s)} + 
                 1, 1 
               
               
                   
                 jIm{h 1,n (s)} 
                 jIm{h 2,n (s)} 
               
               
                 6. 
                 Re{h 1,n (s)} + 
                 Re{h 2,n (s)} + 
                 1, 1 
               
               
                   
                 jIm{h 1,n (s)} 
                 jIm{h 2,n (s)} 
               
               
                 7. 
                 Re{h 1,n (s)} + 
                 Re{h 2,n (s)} + 
                 1, 1 
               
               
                   
                 jIm{h 1,n (s)} 
                 jIm{h 2,n (s)} 
               
               
                 8. 
                 Re{h 1,n (s)} + 
                 Re{h 2,n (s)} + 
                 1, 1 
               
               
                   
                 jIm{h 1,n (s)} 
                 jIm{h 2,n (s)} 
               
               
                 9. 
                 k even: Re{h 1,n (s)} + 
                 k even: Re{h 1,n (s)} + 
                 1, 0 
               
               
                   
                 jIm{h 1,n (s)} 
                 jIm{h 1,n (s)} 
               
               
                   
                 k odd: Re{h 2,n (s)} + 
                 k odd: Re{h 2,n (s)} + 
                 0, 1 
               
               
                   
                 jIm{h 2,n (s)} 
                 jIm{h 2,n (s)} 
               
               
                   
               
             
          
           
               
                 No. 
                 e k  + jf k   
                 C 3,k (s), C 4,k (s), C 5,k (s) 
                 A k   
                 B k   
                 S k   
               
               
                   
               
               
                 1. 
                 k even: c k  + jd k   
                 1, 1, 1 
                 a k e k   
                 b k f k   
                 A k  + B k   
               
               
                   
                 k odd: 0 
                 X 
               
               
                 2. 
                 k even: −d k  + jc k   
                 0, 0, 1 
                 a k e k   
                 b k f k   
                 A k  + B k   
               
               
                   
                 k odd: 0 
                 X 
               
               
                 3. 
                 k even: c k  + jd k   
                 1, 1, 1 
                 a k e k   
                 b k f k   
                 A k  + B k   
               
               
                   
                 k odd: −d k  + jc k   
                 0, 0, 1 
               
               
                 4. 
                 k even: c k  + jd k   
                 1, 1, 1 
                 a k e k   
                 b k f k   
                 A k  + B k   
               
               
                   
                 k odd: d k  − jc k   
                 1, 1, 0 
               
               
                 5. 
                 k even: −c k  − jd k   
                 1, 0, 0 
                 a k e k   
                 b k f k   
                 A k  + B k   
               
               
                   
                 k odd: −d k  + jc k   
                 0, 0, 1 
               
               
                 6. 
                 k even: c k  + jd k   
                 1, 1, 1 
                 a k e k   
                 b k f k   
                 A k  + B k   
               
               
                   
                 k odd: −d k  + jc k   
                 0, 0, 1 
               
               
                 7. 
                 k even: c k  + jd k   
                 1, 1, 1 
                 a k e k   
                 b k f k   
                 A k  + B k   
               
               
                   
                 k odd: d k  − jc k   
                 0, 1, 0 
               
               
                 8. 
                 k even: −c k  − jd k   
                 1, 0, 0 
                 a k e k   
                 b k f k   
                 A k  + B k   
               
               
                   
                 k odd: d k  − jc k   
                 0, 1, 0 
               
               
                 9. 
                 k even: c k  + jd k   
                 1, 1, 1 
                 a k e k   
                 b k f k   
                 A k  + B k   
               
               
                   
                 k odd: −c k  − jd k   
                 1, 0, 0 
               
               
                   
               
             
          
           
               
                 No. 
                 R k   
                 C 6,k (s) 
                 X (s) 
               
               
                   
               
               
                 1. 
                 k even: 1 · S k   
                 1 
                 Re{H 21 (s)} 
               
               
                   
                 k odd: 0 
                 X 
               
               
                 2. 
                 k even: 1 · S k   
                 1 
                 Im{H 21 (s)} 
               
               
                   
                 k odd: 0 
                 X 
               
               
                 3. 
                 k even: tan(π/8) · S k   
                 0 
                 Im{H 21 (s) · exp(jπ/8)/cos(π/8)} 
               
               
                   
                 k odd: 1 · S k   
                 1 
               
               
                 4. 
                 k even: 1 · S k   
                 1 
                 Re{H 21 (s) · exp(jπ/8)/cos(π/8)} 
               
               
                   
                 k odd: tan(π/8) · S k   
                 0 
               
               
                 5. 
                 k even: tan(π/8) · S k   
                 0 
                 Im{H 21 (s) · exp(−jπ/8)/cos(π/8)} 
               
               
                   
                 k odd:: 1 · S k   
                 1 
               
               
                 6. 
                 k even: 1 · S k   
                 1 
                 Re{H 21 (s) · exp(−jπ/8)/cos(π/8)} 
               
               
                   
                 k odd: tan(π/8) · S k   
                 0 
               
               
                 7. 
                 k even: tan(π/8) · S k   
                 0 
                 −Im{H 21 (s) · exp(−jπ/8)/cos(π/8)} 
               
               
                   
                 k odd:: 1 · S k   
                 1 
               
               
                 8. 
                 k even: 1 · S k   
                 1 
                 −Re{H 21 (s) · exp(−jπ/8)/cos(π/8)} 
               
               
                   
                 k odd: tan(π/8) · S k   
                 0 
               
               
                 9. 
                 k even: 1 · S k   
                 1 
                 |H 11 (s)| 2  − |H 22 (s)| 2   
               
               
                   
                 k odd: 1 · S k   
                 1 
               
               
                   
               
             
          
         
       
     
     The three blocks of Table 1 set forth one below the other are to be understood such that each row of a block is continued in the corresponding row of the subsequent block. 
     The stipulations which produce the configuration bits C 1,k (s), C 2,k (s), . . . , C 6,k (s) can be read off from Table 1. 
     For C 1,k (s)=1 and C 2,k (s)=1, the inputs In 1 , . . . , In 4  of the logic unit  2  are connected to the outputs Out 1 , . . . , Out 4  respectively situated opposite them in  FIG. 1 . For C 1,k (s)=0, the inputs In 1  and In 2  are applied to the outputs Out 3  and Out 4 , respectively. For C 2,k (s)=0, the inputs In 3  and In 4  are applied to the outputs Out 1  and Out 2 , respectively. 
     The configuration bit C 3,k (s) decides on the assignment of the outputs Out 5  and Out 6  of the logic unit  3  to the inputs In 5  and In 6 . For C 3,k (s)=1, the input In 5  is applied to the output Out 5 , and the input In 6  is applied to the output Out 6 . For C 3,k (s)=0, the input In 5  is applied to the output Out 6 , and the input In 6  is applied to the output Out 5 . 
     The configuration bits C 4,k (s) and C 5,k (s) determine the signs of the outputs Out 5  and Out 6 , respectively. For C 4,k (s)=1 and C 5,k (s)=1, the outputs Out 5  and Out 6  have a positive sign, while for C 4,k (s)=0 and C 5,k (s)=0 the signs of the outputs Out 5  and Out 6  are negative. 
     The configuration bit C 6,k (s) decides on the weighting that is applied to the number S k  in the weighting unit  7 . For C 6,k (s)=1, the number S k  remains unchanged, while for C 6,k (s)=0 the number S k  is multiplied by the factor tan(π/8). 
     A value “X” in Table 1 for one of the conguration bits C 1,k (s), . . . , C 6,k (s) means that the block is not clocked and therefore does not produce a new output. 
     In order to be able to apply Table 1, a need further exists to stipulate the row of Table 1 that is to be considered. Such a row specification is provided by Table 2, which is set forth below and forms a relationship between the combination of CLTD mode and slot index s with the row numbers of Table 1. 
     
       
         
               
               
               
             
           
               
                   
                   
               
               
                   
                 CLTD mode/slot 
                   
               
               
                   
                 combination 
                 No. from Table 1 
               
               
                   
                   
               
             
             
               
                   
                 Mode 1 
                 1 
               
               
                   
                 s even 
               
               
                   
                 Mode 2 
                 2 
               
               
                   
                 s odd 
               
               
                   
                 Mode 2 
                 3 
               
               
                   
                 s modulo 4 = 0 
               
               
                   
                 Mode 2 
                 4 
               
               
                   
                 s modulo 4 = 1 
               
               
                   
                 Mode 2 
                 5 or 6 or 7 or 8 
               
               
                   
                 s modulo 4 = 2 
               
               
                   
                 Mode 2 
                 9 
               
               
                   
                 s modulo 4 = 3 
               
               
                   
                   
               
             
          
         
       
     
     Given s modulo 4=2, in mode 2 a selection is made between the row numbers 5, 6, 7 or 8 of Table 1 as a function of the results of FSM(s−1) and FSM(s−2). The corresponding assignments can be read off at the entries of Table 3, which is set forth below. 
     
       
         
               
               
               
             
               
               
               
             
           
               
                   
               
               
                 FSM (s − 2) 
                 FSM (s − 1) 
                 No. from Table 1 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 0 
                 0 
                 7 
               
               
                 0 
                 1 
                 8 
               
               
                 1 
                 0 
                 6 
               
               
                 1 
                 1 
                 5 
               
               
                   
               
             
          
         
       
     
     Note that in accordance with 3GPP TS 25.214 V4.2.0 UMTS specification, in mode 1 one FSM data word consists of an FSM bit FSM(s), and in mode 2 it consists of four FSM bits FSM(s). Consequently, in mode 1 with progressive slot index s Nos. 1 and 2 from Table 1 are used alternately for configuring circuit  1 . In mode 2, rows Nos. 3, 4, 5 to 8 and 9 are selected on the basis of the four FSM bits FSM(s) of the FSM data word with a periodicity of 4 with reference to the slot index s. 
     The entries in Tables 1 and 2 are preferably stored in a read-only memory and therefore need not be calculated during processing. 
     The relationships on which the entries in Tables 1 and 2 are based are explained below. 
     For all CLTD mode/slot combinations, the calculation of an FSM bit FSM(s) can be reduced to merely considering one or two elements Hij of the matrix from equation (3). The elements Hij are subjected to the same processing in order to calculate an FSM bit FSM(s). This processing consists essentially of rotations and projections. 
     The matrix element H 21 =|H 21 |e jφ     H     21  is considered for CLTD mode/slot combinations in which the FSM bit FSM(s) pronounces on the phase angle φ 2 . The derivation of equation (3) in terms of the phase angle φ 2  leads to the maximum value of the proportionality factor P for both CLTD modes and for φ 2 =φ H     21   . 
     The matrix elements H 11  and H 22  are considered for CLTD mode/slot combinations in which the FSM bit FSM(s) pronounces on the moduli of the antenna weightings w 1  and w 2 . Taking account of the stipulations of the 3GPP TS 25.214 V4.2.0 UMTS specification, in accordance with which the amplitudes E 1 (s) and E 2 (s) can assume only two values, this requires only that the difference |H 11 | 2 −|H 22 | 2  be evaluated. 
     The specific processing operations for different CLTD mode/slot combinations differ from one another, in particular, in the rotation of the complex phasor, given by the matrix element H 21 , in the plane of complex numbers, and in its projection onto the real or imaginary axis. The respective processing operation is controlled by means of the configuration bits C 1,k (s), . . . , C 6,k (s). The 9 possible processing cases of circuit  1  are listed in Table 1. 
     The constellations in the plane of complex numbers that have to be evaluated in mode 1 are illustrated in  FIG. 2 . 
     Section 7.2 of the 3GPP TS 25.214 V4.2.0 UMTS specification stipulates that during normal operation of the CLTD function in mode 1, that is to say outwith an initialization or a so-called compressed mode, it is necessary to evaluate for an even slot index s whether the complex phasor H 21  in  FIG. 2  lies in the bright complex half plane, that is to say in the 1 st  or 4 th  quadrant, or in the dark complex half plane, that is to say in the 2 nd  or 3 rd  quadrant. It is necessary to evaluate for an odd slot index s whether the complex phasor H 21  lies in the stippled complex half plane, that is to say in the 1 st  or 2 nd  quadrant, or in the dashed complex half plane, that is to say in the 3 rd  or 4 th  quadrant. Given the progressive slot index s, both tasks are accomplished by the alternate use of rows Nos. 1 and 2 from Table 1. 
     The constellations in the plane of complex numbers that have to be evaluated in mode 2 are illustrated in  FIG. 3 . 
     Here, as well, the circuit  1  is to be described in the normal operating mode of the CLTD function in mode 2, that is to say outwith a so-called end of frame adjustment, an initialization or a compressed mode. It is described below how the four FSM bits FSM(s) of the FSM data word are obtained for a phasor H 21  with |H 11 |&gt;|H 22 | in the plane of complex numbers in the angular segment between π/8 and 3π/8. This phasor H 21  is depicted in  FIG. 3 . 
     Row No. 3 from Table 1 is to be applied for s=0 in mode 2 according to Table 2. In accordance with row No. 3 from Table 1, it is necessary to investigate whether the term Im{H 21 (s)·e jπ/8 /cos(π/8)} specifying the variable X(s) is positive or negative. This term clearly specifies that the phasor H 21  is rotated counterclockwise by the angle π/8 in the plane of complex numbers because of the multiplication by the factor e jπ/8 , is stretched by the factor 1/cos(π/8), and is subsequently projected onto the imaginary axis. An investigation is thereupon conducted as to whether this projection lies on the positive or the negative half straight line of the imaginary axis. In the plane of complex numbers, the operations described can be replaced by a threshold value decision. It is necessary for this purpose to investigate whether the phasor H 21  lies above or below the straight line A depicted in  FIG. 3 . The straight line A is rotated clockwise by the angle π/8 in relation to the real axis, and thereby compensates the counterclockwise rotation of the phasor H 21  by the angle π/8. In the present case, the phasor H 21  lies above the straight line A, and so the FSM bit FSM( 0 ) assumes the value 1. 
     The rotation by the angle π/8 or −π/8 is taken into account in the circuit  1  by using the weightings  1  and tan(π/8) in the weighting unit  7 . In this case, the phasor H 21  is stretched by the factor 1/cos(π/8), but this is not significant for the statement relating to the angle. 
     For s=1, row No. 4 from Table 1 is used in mode 2 according to Table 2 for the purpose of calculating the FSM bit FSM( 1 ). It is therefore necessary here to consider the term Re{H 21 (s)·e jπ/8 /cos(π/8)}. In a corresponding way to the procedure in the case of s=0, it is necessary in this case to investigate on which side of the straight line B depicted in  FIG. 3  the phasor H 21  lies. The straight line B results from a clockwise rotation of the real axis by an angle of π/8. A value of 1 results in this case for the FSM bit FSM( 1 ). 
     According to row No. 5 from Table 1, for s=2 an evaluation must take place with reference to the straight line C depicted in  FIG. 3 . The straight line C is rotated clockwise by the angle π/8 with reference to the imaginary axis. A value of 1 results for the FSM bit FSM( 2 ). 
     Row No. 9 from Table 1 is used for s=3. This leads to a value of 1 for the FSM bit FSM( 3 ). In total, the FSM data word resulting from the phasor H 21  is 1111. 
     Various possible positions of the phasor H 21  are marked by crosses by way of example in  FIG. 3 . The FSM data words associated with these positions are noted next to them. 
     
       
         
               
             
               
               
               
             
           
               
                   
               
               
                 List of reference symbols 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 1 
                 Circuit 
               
               
                   
                 2 
                 Logic unit 
               
               
                   
                 3 
                 Logic unit 
               
               
                   
                 4 
                 Multiplier 
               
               
                   
                 5 
                 Multiplier 
               
               
                   
                 6 
                 Adder 
               
               
                   
                 7 
                 Weighting unit 
               
               
                   
                 8 
                 Accumulator 
               
               
                   
                 9 
                 Threshold value decision unit 
               
               
                   
                 In1, . . . , In6 
                 Inputs 
               
               
                   
                 Config1, . . . , Config6 
                 Configuration inputs 
               
               
                   
                 Out1, . . . , Out6 
                 Outputs 
               
               
                   
                 h i,n (s) 
                 Channel coefficients 
               
               
                   
                 Re{h 1,n (s)}, 
                 Real parts of channel 
               
               
                   
                 Re{h 2,n (s)} 
                 coefficients 
               
               
                   
                 Im{h 1,n (s)}, 
                 Imaginary parts of channel 
               
               
                   
                 Im{h 2,n (s)} 
                 coefficients 
               
               
                   
                 FSM (s) 
                 FSM bit 
               
               
                   
                 C 1,k (s), C 2,k (s), . . . , C 6,k (s) 
                 Configuration bits 
               
               
                   
                 i 
                 Channel (i = 1, 2) 
               
               
                   
                 s 
                 Slot index (s = 1, . . . , 15) 
               
               
                   
                 n 
                 Path index (n = 1, . . . , N) 
               
               
                   
                 k 
                 Clock index (k = 1, . . . , 2N) 
               
               
                   
                 a k , c k , e k   
                 Real parts 
               
               
                   
                 b k , d k , f k   
                 Imaginary parts 
               
               
                   
                 a k  + jb k , c k  + jd k , e k  + jf k   
                 Complex numbers 
               
               
                   
                 A k , B k , S k , R k   
                 Numbers 
               
               
                   
                 X (s) 
                 Variable 
               
               
                   
                 H 21   
                 Complex phasor 
               
               
                   
                 A, B, C 
                 Straight lines