Abstract:
A circuit for maintaining the threshold voltages of transistors implemented in a dynamic CMOS circuit. A plurality of transistors have source drain connections connected between the body contacts of transistors in the dynamic CMOS circuits, and the constant voltage potential. When operating the dynamic CMOS circuit in the precharge phase, the body of each of the CMOS circuit transistors is maintained at the constant voltage potential. During the evaluate phase, the body potential is permitted to float to its precharge state. The initial reference level voltage established during a precharge phase maintains the transistor gate-source threshold voltage at a constant value, eliminating both bipolar effects and history effects which accompanying a changing body potential.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to electronic circuits implemented in SOI CMOS. Specifically, dynamic CMOS circuits are described where each circuit device has a threshold voltage which is controlled to reduce threshold variations. 
     CMOS circuits may be implemented as partial depletion SOI circuits which constitute logic circuits for producing a voltage on a node characterizing the logical combination of logic input signals. A clock signal controls two phases of operation, a precharge phase in which the node is set to the logical value which is a function of input conditions, and an evaluate stage wherein an output voltage representing the logic value is produced. 
     In partially depleted SOI CMOS circuit implementations, certain bipolar effects and history effects are experienced. The bipolar effects occur when a device connected to the charge node assumes a body potential which can result in bipolar current conduction during the evaluate phase, changing the node voltage and otherwise destroying data represented by the node voltage. History effects represent changes in the data propagation delay of the circuit which are significantly influenced by the change in transistor gate to source voltage thresholds. The gate to source voltage thresholds change as the device body voltage increases during the precharge phase. As the SOI body voltage of an NFET increases, the threshold voltage for the device decreases, varying the switching point. The change in threshold not only produces a change in device delay, it also produces changes in noise immunity. As the threshold voltage decreases the noise immunity for the device correspondingly decreases. 
     The present invention is directed to a circuit which inhibits charging of the transistor body potential in dynamic circuit applications, particularly in the partial depletion SOI CMOS environment. 
     SUMMARY OF THE INVENTION 
     A dynamic CMOS circuit is provided which produces a voltage on a charged node representing a logical function applied to input logic signals. The dynamic circuit is clocked with a clock input signal to establish a logical output for the circuit. The input transistors of the circuit which receive the logic input signals have a body contact which is connected to a voltage potential through a switching transistor so that during the precharge phase, the body potential of the input transistors is maintained at a constant reference voltage level. When the circuit enters the evaluate stage, the switching transistor is rendered into a non-conducting condition, and the body potential is permitted to float from its preestablished voltage level, and the node is charged to a value representing the logical function applied to the input signal conditions. 
     By pre-establishing a reference voltage level Vss on the body contact, the threshold voltage for the device remains substantially constant, and the delays through the circuit are stabilized. Additionally, by maintaining the body contact potential at a known level near the source potential, bipolar effects are minimized which would otherwise effect the node potential and corrupt the data represented by the node voltage. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates the change of the gate-source threshold voltage V t  with respect to changes in the body to gate potential of a SOI CMOS transistor; 
     FIG. 2 is a section view of a SOI CMOS transistor which is subject to bipolar effects due to a body voltage which exceeds a source or drain voltage; 
     FIG. 3 illustrates a prior art dynamic CMOS circuit; 
     FIG. 4 illustrates one example of a dynamic CMOS circuit in accordance with a preferred embodiment having transistors which have a substantially constant threshold voltage V t ; and 
     FIG. 5 illustrates a second example of a dynamic CMOS circuit in accordance with a second embodiment of the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     SOI CMOS transistors operating in a partial depletion mode have a body-source threshold voltage characteristic V t , shown in FIG. 1, which decreases with an increasing voltage on the body of the transistor relative to the transistor source. The figure represents the change in threshold voltage for devices which operate in the bulk region when the body potential is tied to the substrate potential, and in the SOI region when the body voltage is isolated from the source. As illustrated, when the device is in the SOT configuration, the body potential floats above the source potential. When the transistor is off the voltage for rendering the transistor conductive is less than the threshold voltage when the transistor is conducting. 
     FIG. 2 is a cross-section showing a transistor implemented as a partial depletion SOI CMOS device. An insulated gate  11  controls current at the surface of the body  12  which is in contact with a buried oxide body  13 . If the body  12  potential increases, to a point where the voltage exceeds the source  16  potential, bipolar effects are encountered and a current flows through the device even though the gate  11  is at a voltage which would normally not permit conduction through the diffusion channel  12 . The net result of the bipolar effects can be a forward current flowing through a transistor which is supposed to be in a non-conductive state. If the device is connected to an output node, the charge on the node will decrease, destroying the data represented by the node potential. 
     Bipolar effects are evident in a typical dynamic CMOS circuit shown in FIG.  3 . Referring now to FIG. 3, a prior art OR gate is shown implemented in partial depletion CMOS. First and second input transistors  22  and  23  are connected to a node  25  which will charge to a potential representing a logical function of an input on the gates to transistor  22  or  23  during an evaluate phase. During the evaluate phase of the clock input signal, transistor  24  conducts, transistor  26  is non-conducting, and the node  25  assumes a charge depending on the logic state A or B applied to the gates of transistors  22  and  23 . A foot transistor  24  pulls the sources of transistors  22  and  23  to ground. Transistor  21  is a half latch and inverter  27  inverts the potential appearing at output node  25 . 
     During the precharge phase, the low clock input signal renders transistor  26  ON and transistor  24  non-conducting. Node  25  is brought to potential Vcc as p-transistor  26  is rendered conducting. The sources for transistors  22  and  23  may also reach Vcc since transistor  24  is OFF during the precharge phase. The result is that the body potential of transistors  22  and  23  may charge to a voltage Vcc, lowering the threshold V t  as illustrated in FIG. 1, from 0.5 volts to 0.3 volts. As a result, the circuit is more sensitive to noise during the evaluation phase, when the clock input signal goes to logic 1 state, and transistor  26  is turned OFF, transistor  24  is turned ON, and node  25  assumes a potential depending on whether one or the other or both of transistors  22 ,  23  are conducting due to a logic state I on at least one of inputs A and B. 
     Additionally, the body potential on transistors  22  and  23  may cause the aforesaid bipolar events, where conduction occurs within devices  22  and  23  when the devices are supposed to be in a non-conductive state due to a logic input of zero applied to each of the gates of transistors  22  and  23 . In this state, node  25  will discharge to an incorrect voltage which is lower than Vcc during the precharge phase. 
     The charge on the transistor body may also vary the threshold voltage V t  over time, producing a corresponding change in the device delay representing history effects. 
     In accordance with a first embodiment of the invention, a solution to the foregoing problems which occur in dynamic CMOS circuits as a result of the body potential on transistor devices, is shown more particularly in FIG.  4 . The circuit of FIG. 4 is an OR circuit for performing the same logic function as that of FIG.  3 . The OR circuit comprises the same circuit elements with the addition of two switching transistors  28  and  29 . Switching transistors  28  and  29  connect the body potential of the input transistors  22  and  23  to a bias voltage Vss. Vss is selected to be lower than Vcc, and may in some embodiments be the ground terminal of supply Vcc. Switching transistors  28  and  29  have gate connections connected to a second clock input C 2 . Clock C 2  is substantially the complement of clock C 1 , so that during the precharge phase, the body potential of input transistors  22  and  23  is brought to the voltage level Vss. During the evaluate phase body potential of transistor  22  and  23  is permitted to float. 
     Thus, during the precharge phase when node  25  is brought to potential Vcc, the body potential of transistors  22 . and  23  are maintained at, Vss. During the evaluate phase of clock signal C 1 , the body of transistors  22 ,  23  has been precharged to Vss, and the gate-source threshold voltage V t  for input transistors  22  and  23  resets to a known value. The constant threshold voltage V t  produces a constant delay through the circuit, reducing the history effects which occur when the body potential is permitted to change over time. 
     The foregoing embodiment contemplates returning the body potential for the input transistors  22  and  23  to a constant potential Vss. In some applications, it may only be necessary to provide a single switching device for controlling the body potential of a single transistor connected to the node to avoid the foregoing bipolar effects. 
     One such application is an AND gate shown more particularly in FIG.  5 . The AND gate of FIG. 5 receives logic inputs A and B on inputs to N-type transistors  36  and  37 . A pull up P-type transistor  38  forms with input transistors  36  and  37  a node  35 . An inverter circuit comprising inverter  43  and pull up transistor  42  inverts the voltage appearing at node  35 , and produces an output signal representing the logic states of inputs A and B. 
     The dynamic CMOS AND gate of FIG. 5 operates in response to the clock pulse Cl, so that during a precharge phase, node  35  is charged to a voltage level Vcc. 
     Additionally, a complementary clock signal C 2  is supplied to a switching transistor  40 , for maintaining the body of transistor  36  at the potential Vss during the precharge phase. 
     During an evaluate phase of the clock signal, transistor  38  is rendered conductive, and node  35  assumes a state depending on the logic inputs A and B. Since the body potential of transistor  36  has been set to Vss, bipolar effects are eliminated for transistor  36 . As remaining input transistor  37  is not connected to the node  35 , it is not necessary in this application to provide for lowering its body potential to Vss in order to protect node  35  from discharge due to bipolar effects. 
     However, in order to maintain constant voltage thresholds for transistors  36  and  37 , a second switching transistor  41  may be provided to maintain the body potential of transistor  37  at the level Vss. 
     The foregoing description of the invention illustrates and describes the present invention. Additionally, the disclosure shows and describes only the preferred embodiments of the invention, but as aforementioned, it is to be understood that the invention is capable of use in various other combinations, modifications, and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein, commensurate with the above teachings, and/or the skill or knowledge of the relevant art. The embodiments described hereinabove are further intended to explain best modes known of practicing the invention and to enable others skilled in the art to utilize the invention in such, or other, embodiments and with the various modifications required by the particular applications or uses of the invention. Accordingly, the description is not intended to limit the invention to the form disclosed herein. Also, it is intended that the appended claims be construed to include alternative embodiments.