Abstract:
A method and system are described for reducing a thermo-optic effect in silicon photonics. In described embodiments, the system comprises a silicon photonic device with a silicon core that includes a cladding layer comprising titanium adjacent to the silicon core. In described embodiments, the method comprises providing a silicon core and depositing a cladding layer adjacent to the silicon photonic core, wherein the cladding layer comprises titanium.

Description:
RELATED APPLICATION 
     This application claims priority under 35 U.S.C. §119 to U.S. Provisional Application No. 61/985,166, entitled “Athermal Silicon Photonics with CMOS Compatibility,” by Sung-Joo Ben Yoo, filed 28 Apr. 2014, the contents of which are herein incorporated by reference in their entirety. 
    
    
     BACKGROUND 
     Field 
     The described embodiments relate to photonic structures with reduced thermal variation of optical parameters. More specifically, the described embodiments relate to silicon photonic structures with a reduced thermo-optic effect. 
     Related Art 
     Silicon photonics have been used in an increasing variety of applications, including waveguides, modulators, resonators, and lasers. In many of these applications, the functioning of the silicon photonic devices may depend on the index of refraction of the silicon. However, the index of refraction of silicon varies with temperature due to the thermo-optic effect, and the amount that the index of refraction varies with temperature is called the thermo-optic coefficient (“TOC”). Since many silicon photonic devices may be used in environments that have temperature variations during their operation, the TOC of silicon may result in the optical properties of silicon photonic devices varying with temperature to an extent that their operation is adversely impacted. 
     Active temperature stabilization techniques to control the temperature of silicon photonic devices have been used to limit the temperature variation and thus reduce the impact of the TOC of silicon on the functioning of many of these devices. However, active temperature stabilization may be difficult to implement for some devices, and if implemented may be energy-inefficient. 
     Passive compensation for the TOC of silicon has been implemented using polymer cladding materials such as Poly-Methyl-Meth-Acrylate (PMMA) with a negative TOC to compensate for the positive TOC of the silicon in some photonic devices. However, such polymer materials may not be compatible with the processes typically used in the fabrication of complementary metal-oxide semiconductor (CMOS) devices, and therefore these polymers may not be able to be readily incorporated into existing CMOS fabrication processes. Additionally, these polymers may absorb water, become chemically unstable, be mechanically weak, and/or undergo photo-degradation and, therefore, may often be undesirable for use in silicon photonic devices. 
     SUMMARY 
     Disclosed embodiments describe a silicon photonic device comprising a silicon core and a cladding layer comprising titanium adjacent to the silicon core. 
     In some embodiments, the cladding layer comprises amorphous titanium dioxide. 
     In some embodiments, the silicon photonic device comprises a waveguide, and over a bandwidth of the silicon photonic device for a mode of the waveguide, a ratio of a fraction of a total power of the mode in the core to a fraction of the total power of the mode in the cladding is in the range from 90% to 110% of negative one times a ratio between a thermo-optic coefficient of the cladding to a thermo-optic coefficient of the core. 
     In some embodiments, a loss in the cladding layer for a wavelength of operation of the silicon photonic device is less than or equal to 7 dB/cm. 
     In some embodiments, the silicon photonic device comprises a waveguide. 
     In some embodiments, the silicon photonic device comprises an arrayed waveguide grating. 
     In some embodiments, the silicon photonic device comprises a Mach-Zehnder interferometer. 
     In some embodiments, the silicon photonic device comprises a modulator. 
     In some embodiments, the silicon photonic device comprises a resonator. 
     In some embodiments, the silicon photonic device comprises a laser. 
     Disclosed embodiments also provide a method of preparing a silicon photonic device comprising providing a silicon core and depositing a cladding layer adjacent to the silicon core, wherein the cladding layer comprises titanium. 
     In some embodiments, the silicon photonic device includes a substrate, and during the step of depositing the cladding layer an average temperature of the substrate is less than or equal to 20° C. 
     In some embodiments, the step of depositing the cladding layer comprises depositing the cladding layer at a rate of less than or equal to 5 nm/minute. 
     In some embodiments, the step of depositing the cladding layer comprises depositing the cladding layer using RF magnetron reactive sputtering. 
     In some embodiments, after the step of depositing the cladding layer, the method further includes annealing the silicon photonic device at a temperature of less than or equal to 550° C. 
     In some embodiments, depositing the cladding layer includes depositing the cladding layer using sputtering with an oxygen flow rate in the range from 6% to 24% of a total gas flow rate during the sputtering. 
     In some embodiments, depositing the cladding layer includes depositing the cladding layer using sputtering with an oxygen flow rate in the range from 12% to 18% of a total gas flow rate during the sputtering. 
    
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
         FIG. 1  presents a block diagram illustrating a silicon photonic device in accordance with described embodiments. 
         FIG. 2  presents a block diagram illustrating another silicon photonic device in accordance with described embodiments. 
         FIG. 3  presents a flowchart illustrating a process for fabricating a cladding layer on a silicon photonic device in accordance with described embodiments. 
         FIG. 4  presents a flowchart illustrating a process for depositing a cladding layer on a silicon photonic device in accordance with described embodiments. 
     
    
    
     In the figures, like reference numerals refer to the same figure elements. 
     DETAILED DESCRIPTION 
     The following description is presented to enable any person skilled in the art to make and use the described embodiments, and is provided in the context of a particular application and its requirements. Various modifications to the described embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the described embodiments. Thus, the described embodiments are not limited to the embodiments shown, but are to be accorded the widest scope consistent with the principles and features disclosed herein. 
     The following detailed description should be read with reference to the drawings in which similar elements in different drawings may be numbered the same. The drawings, which are not necessarily to scale, depict illustrative embodiments and are not intended to limit the scope of the invention. 
     In the following description, we refer to “some embodiments.” Note that “some embodiments” may describe a subset of all of the possible embodiments, but does not always specify the same subset of embodiments. The recitation of numerical ranges by endpoints includes all numbers within that range (e.g., 3 to 5 includes 3, 3.2, 4, 4.70, and 5). 
       FIG. 1  depicts a silicon photonic device with a reduced thermo-optic effect in accordance with embodiments. Silicon photonic device  102  includes substrate  104  with undercladding layer  106 , silicon core  108 , and overcladding layer  110 . Silicon core  108  has height  112  and width  114 , and overcladding layer  110  has thickness  116 , undercladding layer  106  has thickness  118 , and substrate  104  has thickness  120 . 
     Note that  FIG. 1  depicts a cross section of silicon photonic device  102  perpendicular to the direction of travel of photons in silicon photonic device  102 . In some embodiments silicon photonic device  102  may comprise a waveguide, an arrayed waveguide grating (AWG), a ring modulator, a Mach-Zehnder interferometer, a resonator, or a laser, and in some of these embodiments, silicon core  108  may be replaced by a ridged silicon core. 
     Substrate  104  may be any substrate for use with a silicon photonic device and may be or include a silicon wafer. In some embodiments, thickness  120  of substrate  104  may be 500 microns or more. Undercladding layer  106  is a layer that is electrically insulating and in some embodiments may be a layer of silicon dioxide. In some embodiments in which undercladding layer  106  is a silicon dioxide layer, it may also be called a buried oxide (BOX) layer. In some embodiments, undercladding layer  106  may have a thickness of approximately 2 microns. 
     Overcladding layer  110  is comprised of titanium dioxide and may include titanium dioxide in crystalline (mono- or poly-crystalline), and/or amorphous structure and may include multiple amorphous and crystalline regions. The crystalline portions may include anatase, rutile, and/or brookite crystalline forms. In some embodiments, overcladding layer  110  is comprised of amorphous titanium dioxide. In some embodiments, thickness  116  of overcladding layer  110  may be 2 microns. 
     During operation of silicon photonic device  102 , photons of a desired wavelength or band of wavelengths may be transmitted in a mode of silicon photonic device  102 . The effective index of refraction for photons in the mode may be expressed as:
 
 n   eff =Γ core   n   core +Γ underclad   n   underclad +Γ overclad   n   overclad    (1)
 
where Γ core , Γ underclad , and Γ overclad  are the percentage of power of the mode that is within silicon core  108 , undercladding layer  106 , and overcladding layer  110  respectively, and n core , n underclad , and n overclad  are the index of refraction for photons in the mode due to silicon core  108 , undercladding layer  106 , and overcladding layer  110  respectively. Note that Γ core , Γ underclad , and Γ overclad  may also be referred to, respectively, as the core, undercladding and overcladding confinement factors.
 
     The effective thermo-optic coefficient (TOC) for a photon in a mode of silicon photonic device  102  can then be found by taking the derivative of equation 1 above with respect to temperature while assuming that the change in the core confinement factor, undercladding confinement factor and overcladding confinement factor with temperature is negligible. The derivative of equation 1 with respect to temperature (T) is: 
     
       
         
           
             
               
                 
                   
                     
                       ∂ 
                       
                         n 
                         eff 
                       
                     
                     
                       ∂ 
                       T 
                     
                   
                   = 
                   
                     
                       
                         Γ 
                         core 
                       
                       ⁢ 
                       
                         
                           ∂ 
                           
                             n 
                             core 
                           
                         
                         
                           ∂ 
                           T 
                         
                       
                     
                     + 
                     
                       
                         Γ 
                         underclad 
                       
                       ⁢ 
                       
                         
                           ∂ 
                           
                             n 
                             underclad 
                           
                         
                         
                           ∂ 
                           T 
                         
                       
                     
                     + 
                     
                       
                         Γ 
                         overclad 
                       
                       ⁢ 
                       
                         
                           ∂ 
                           
                             n 
                             overclad 
                           
                         
                         
                           ∂ 
                           T 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
     In some embodiments equation 2 may be simplified if the rate of change of the index of refraction of undercladding layer  106  with respect to temperature (TOC undeclared ) can be ignored compared to the rate of change of the index of refraction of the silicon core  108  with respect to temperature (TOC core ) and rate of change of the index of refraction of the overcladding layer  110  with respect to temperature (TOC overclad ). In some embodiments, in which undercladding layer  106  is comprised of silicon dioxide, and overcladding layer  110  is comprised of titanium dioxide, since the TOC of silicon dioxide is approximately 10 −5  while the TOC of silicon is approximately 1.8×10 −9  and the TOC of titanium dioxide is approximately −2×10 −4 , the TOC of undercladding layer  106  can be ignored compared to the TOCs of silicon core  108  and overcladding layer  110 . In these embodiments, equation 2 may be simplified to: 
                       ∂     n   eff         ∂   T       ≈         Γ   core     ⁢       ∂     n   core         ∂   T         +       Γ   overclad     ⁢       ∂     n   overclad         ∂   T                   (   3   )               
Then, to determine the conditions to achieve operation of silicon photonic device  102  with reduced thermo-optic effects, the effective TOC is set equal to zero. Equation 3 can then be rearranged to:
 
     
       
         
           
             
               
                 
                   
                     
                       Γ 
                       
                         overc 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         lad 
                       
                     
                     
                       Γ 
                       core 
                     
                   
                   ≈ 
                   
                     - 
                     
                       
                         TOC 
                         core 
                       
                       
                         TOC 
                         overclad 
                       
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
     As shown by equation 4, the thermo-optic effect may be reduced by configuring silicon photonic device  102  so that the ratio of the overcladding confinement factor to the core confinement factor is within a desired amount of negative one times the ratio between the thermo-optic coefficient of the core and the thermo-optic coefficient of the overcladding. In some embodiments, the ratio of Γ overclad  to Γ core  is in the range from 90% to 110% of negative one times the ratio of TOC core  to T overclad . Note that, due to the negative sign on the right-hand side of equation 4, for the wavelength(s) of operation of silicon photonic device  102 , the TOC of silicon core  108  for the mode must have an opposite sign to the TOC of overcladding layer  110  for the mode. Thus, since the TOC of silicon, the material that silicon core  108  comprises, is positive, the TOC of the material of overcladding layer  110  must be negative. Cladding materials that may be used in addition to titanium dioxide may include, but are not limited to, a group 4 element from the periodic table, including an oxide of a group 4 element, such as hafnium dioxide. 
     In some embodiments, the core confinement factor (Γ core ) and the overcladding confinement factor (Γ overclad ) may be adjusted to desired values or within desired ranges by adjusting the shape and/or dimensions of silicon core  108  based on the indices of refraction of the silicon core  108 , undercladding layer  106  and overcladding layer  110  at the desired wavelength or wavelength range(s) of operation. For example, when silicon photonic device  102  is operated in a wavelength range from 1500 nm to 1600 nm, undercladding layer  106  is comprised of silicon dioxide, overcladding layer  110  is comprised of amorphous silicon dioxide, height  112  of silicon core  108  may be between 200 nm and 250 nm and width  114  may be between 250 nm and 500 nm, thickness  116  may be 2 microns, and thickness  118  may be 2 microns. Note that in some embodiments thickness  116  and thickness  118  may be selected so that the portions of the desired mode(s) of silicon photonic device  102  that extend outside of overcladding layer  110  and undercladding layer  106  are negligible. 
     In some embodiments, silicon core  108  need not have a rectangular cross section, and may be any desired shape, including but not limited to a trapezoid, a triangle, a circle, an oval, or any other shape that can support a mode including a rib-type waveguide, and may have a tapered, stepped, or otherwise varying shape and/or cross section along the direction of propagation of the mode. Additionally, note that in some embodiments, undercladding layer  106  may also be comprised of an element from group 4 of the periodic table including an oxide of a group 4 element, and may be comprised of the same material as overcladding layer  110 , including titanium dioxide. 
       FIG. 2  depicts a silicon photonic device in accordance with embodiments. Silicon photonic device  202  comprises a modulator and includes substrate  104  with undercladding layer  106 , silicon core  204 , overcladding layer  206 , insulating layers  208 A and  208 B, and metal contacts  210 A and  210 B connected, respectively, to doped regions  212 A and  212 B. 
     Silicon core  204  is part of a ridged waveguide with width  214 , height  216  and thickness  218 . Overcladding layer  206  may be comprised of the same material(s) as overcladding layer  110 , including crystalline and/or amorphous titanium dioxide. Insulating layers  208 A and  208 B are electrically insulating and may be comprised of silicon dioxide. Metal contacts  210 A and  210 B may be any metal that can conduct an electric current and may be comprised of aluminum. 
     Note that the desired width  214  and height  216  of silicon core  204  may be determined using a process similar to that used to determine width  114  and height  112  of silicon core  108 . For example, in embodiments in which undercladding layer  106  is comprised of silicon dioxide, and overcladding layer  206  is comprised of titanium dioxide, for a wavelength range from 1500 nm to 1600 nm, width  214  may be between 250 nm to 500 nm and height  216  may be between 200 nm and 250 nm. Thickness  218  may be from 20 nm to 50 nm. 
     Modulator  202  may be fabricated using conventional silicon photonic fabrication techniques that are also compatible with CMOS fabrication processes. An example of the fabrication techniques that may be used can be found in U.S. Provisional Application No. 61/985,166. The process used to fabricate a cladding layer such as overcladding layer  110  or overcladding layer  206  is discussed below. 
       FIG. 3  presents a flowchart illustrating a process for the fabrication of a cladding layer on a silicon photonic device such as silicon photonic device  102  or silicon photonic device  202 , in accordance with embodiments. The process of  FIG. 3  begins at step  302  with a silicon photonic device such as silicon photonic device  102  without overcladding layer  110  or silicon photonic device  202  without overcladding layer  206 . At step  304  the overcladding layer is deposited on the silicon photonic device. Step  304  will be discussed in more detail below with reference to  FIG. 4 . At step  306  the silicon photonic device may be annealed if necessary. In some embodiments in which the overcladding layer comprises amorphous titanium dioxide and the silicon photonic device must be annealed, such as may be the case if the silicon photonic device includes metal contacts that require annealing, the silicon photonic device may be annealed at temperatures of up to 550° C. for up to 1 hour without substantially altering the structure of the titanium dioxide. In some embodiments, the annealing process may be conducted in a nitrogen atmosphere and have a ramp rate of up to 25° C./min. 
     In some embodiments, the overcladding layer applied in step  304  is comprised of a material, such as titanium dioxide, that includes one or more of the following properties: it is used in conventional CMOS processing, it is compatible with CMOS processing, and/or it is compatible with typical back-end-of-the-line (BEOL) CMOS processes. In some embodiments, compatibility with BEOL CMOS processes includes but is not limited to having a sufficient temperature stability to withstand BEOL CMOS processes, including processing at temperatures of less than or equal to 450° C. Furthermore in some embodiments, the process used to deposit the overcladding layer in step  304  comprises a process commonly used in CMOS foundries and may include but is not limited to RF magnetron sputtering. Additionally, in some embodiments, the process used to apply the overcladding layer in step  304  has a deposition rate greater than or equal to 1 nm/min. 
       FIG. 4  presents a flowchart illustrating a process for depositing a cladding layer such as overcladding layer  110  or overcladding layer  206  in accordance with embodiments. The process begins with a silicon photonic device, such as silicon photonic device  102  or silicon photonic device  202 , or any other silicon photonic device it is desired to apply a cladding layer to in accordance with embodiments. In step  402 , the silicon photonic device is provided in a state so that is ready to receive the cladding layer. Preparations may include, but are not limited to, masking of portions of the device to be protect from the cladding layer coating, or that otherwise should remain uncoated. The silicon photonic device is placed, or may already be, in a process chamber such as might be used as part of a conventional RF magnetron reactive sputtering process during CMOS processing 
     In step  404  oxygen gas and argon gas are introduced into the chamber using two gas mass flow controllers running in a master-slave configuration, in a fixed flow ratio with 12% oxygen content. In some embodiments, the oxygen flow rate ratio may be set to be in the range from 9% to 15%, 12% to 18%, or 6% to 24%. At step  406 , while the gas is flowing into the chamber, the total process chamber pressure is maintained at 2×10 −3  Torr. 
     In step  408 , a 99.995% pure, 3-inch diameter titanium target is rotated at 5 rpm. At step  410 , if necessary, the substrate of the silicon photonic device is actively cooled to maintain a temperature at or below 20° C. In some embodiments, the temperature of the silicon photonic device, and specifically the cladding layer being applied, may be a function of the rate of deposition of the cladding layer. Active cooling may not be needed in embodiments in which the deposition rate of the cladding layer is slow enough. In some embodiments, a deposition rate of less than or equal to 5 nm/minute may not require active cooling of the silicon photonic device during the process of depositing the cladding layer. 
     In step  412 , titanium is sputtered from the target onto the silicon photonic device using RF magnetron reactive sputtering physical vapor deposition at an RF power of 360 watts. At step  414 , the sputtering process is stopped when the desired cladding layer thickness is reached. In some embodiments, the process described above result in a titanium dioxide layer that is predominantly in the amorphous state. 
     In some embodiments, varying one or more of the process parameters, such as operating with a substrate temperature of above 20° C., may result in a cladding layer that has a substantial enough crystalline content so that propagation losses (e.g., due to scattering at crystalline grain boundaries) for one or more desired modes of the silicon photonic device are unacceptable. For example, operating under the condition described in  FIG. 4 , but with oxygen flow rate ratios of 12% and 18% was found to result in an amorphous structure for a titanium dioxide overcladding layer with a trace amount of anatase phase crystalline structure, while an oxygen flow rate ratio of 24% resulted in an amorphous structure with a trace amount of rutile phase crystalline structure. Operating at an oxygen flow rate of 6% or less was found to result in a cladding layer with titanium that had not been fully oxidized. Additionally, other parameters of the cladding, such as index of refraction, thermo-optic coefficient, and surface roughness, may be impacted by varying one or more of the parameters of the process in  FIG. 4 . 
     In some embodiments, the cladding layer may comprise a crystalline or polycrystalline structure. For example, an overcladding layer such as overcladding layer  110  or overcladding layer  206  may be or include amorphous titanium dioxide with one or more crystalline or poly-crystalline structures within the desired mode(s) of the silicon photonic device. In some embodiments, for an overcladding layer comprised of amorphous titanium dioxide and crystalline titanium dioxide, if for an x-ray rocking curve of the silicon photonic device, fewer than 5% of the total number of counts from the overcladding layer are due crystalline structure, then the optical loss due scattering may be less than or equal to 7 dB/cm. In some embodiments, the overcladding layer may be predominantly or entirely a single crystal of titanium dioxide for the portion of the overcladding layer that is within the desired mode(s) of the silicon photonic device if the overcladding layer has a loss below a desired value and the requirements for the reduction of the thermo-optic effect, such as mode confinement and TOC for equation 4 are met. 
     Note that in some embodiments other deposition processes may be used instead of or in addition to RF reactive sputtering, including but not limited to atomic layer deposition and any other physical layer deposition processes, including electron beam PVD, evaporative deposition, and pulsed laser deposition. In some embodiments, any process that is compatible with the silicon photonic device and can generate a cladding layer such as a titanium dioxide cladding layer that satisfies equation 4 and has an acceptable loss may be used. 
     The foregoing descriptions of embodiments have been presented only for purposes of illustration and description. They are not intended to be exhaustive or to limit the embodiments to the forms disclosed. Accordingly, many modifications and variations will be apparent to practitioners skilled in the art. Additionally, the above disclosure is not intended to limit the embodiments. The scope of the embodiments is defined by the appended claims.