Abstract:
A circuit module includes a duplexer and a circuit substrate. A first signal path connects a first external electrode to a second external electrode. A second signal path connects a third external electrode to a fourth external electrode. A third signal path connects a fifth external electrode to a sixth external electrode. A first ground path connects a seventh external electrode to an eighth external electrode. A second ground path is connected to a ninth external electrode and is capacitively coupled to the second signal path.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to circuit module substrates, and more particularly, to circuit modules including a duplexer mounted thereon. 
     2. Description of the Related Art 
     Known examples of existing circuit modules include an antenna switch module disclosed in Japanese Unexamined Patent Application Publication No. 2006-295530. In this antenna switch module, a first reception signal and a second reception signal which have been received through an antenna and which are based on different communication systems are separated. The separated first and second reception signals are transmitted within a multilayer dielectric medium. 
     With the antenna switch module disclosed in Japanese Unexamined Patent Application Publication No. 2006-295530, there is a need for reducing undesirable interference generated between the first and second reception signals. 
     SUMMARY OF THE INVENTION 
     Preferred embodiments of the present invention reduce undesirable interference generated among a plurality of types of signals in a circuit module on which a duplexer that separates a plurality of types of signal is mounted. 
     A circuit module according to a first preferred embodiment of the present invention is a circuit module that includes a duplexer and a circuit substrate on which the duplexer is mounted. The duplexer includes a duplexer main body; first, second and third external electrodes and a plurality of duplexer ground external electrodes provided on the duplexer main body; a first filter that outputs a signal input at the first external electrode to the second external electrode; a second filter that outputs a signal input at the third external electrode to the first external electrode; a ground conductor that is connected to the duplexer ground external electrodes and that is maintained at a ground potential. The circuit substrate includes a substrate main body; fourth, fifth and sixth external electrodes and a plurality of substrate top surface ground external electrodes that are provided on the substrate main body and that are respectively connected to the first, second and third external electrodes and the plurality of the duplexer ground external electrodes; seventh, eighth and ninth external electrodes and a substrate bottom surface ground external electrode provided on the substrate main body; a first signal path that connects the fourth external electrode to the seventh external electrode, a second signal path that connects the fifth external electrode to the eighth external electrode, and a third signal path that connects the sixth external electrode to the ninth external electrode; a first ground path that connects a portion of the plurality of the substrate top surface ground external electrodes to the substrate bottom surface ground external electrode; and a second ground path that is connected to the substrate top surface ground external electrode which is not connected to the substrate bottom surface ground external electrode and that is electromagnetically coupled to the second signal path or the third signal path. 
     A circuit module according to a second preferred embodiment of the present invention is a circuit module that includes a duplexer and a circuit substrate on which the duplexer is mounted. The duplexer includes a duplexer main body; first, second and third external electrodes and a plurality of duplexer ground external electrodes provided on the duplexer main body; a first filter that outputs a signal input at the first external electrode to the second external electrode; a second filter that outputs a signal input at the third external electrode to the first external electrode; a ground conductor that is connected to the duplexer ground external electrodes and that is maintained at a ground potential. The circuit substrate includes a substrate main body; fourth, fifth and sixth external electrodes and a plurality of substrate top surface ground external electrodes that are provided on the substrate main body and that are respectively connected to the first, second and third external electrodes and the plurality of the duplexer ground external electrodes; seventh, eighth and ninth external electrodes and a substrate bottom surface ground external electrode provided on the substrate main body; a first signal path that connects the fourth external electrode to the seventh external electrode, a second signal path that connects the fifth external electrode to the eighth external electrode, and a third signal path that connects the sixth external electrode to the ninth external electrode; a first ground path that connects a portion of the plurality of the substrate top surface ground external electrodes to the substrate bottom surface ground external electrode; and a second ground path that is connected to the substrate top surface ground external electrode which is not connected to the substrate bottom surface ground external electrode and that is coupled to the second signal path or the third signal path through a phase unit. 
     According to various preferred embodiments of the present invention, in a circuit module on which a duplexer that separates a plurality of types of signal is mounted, undesirable interference generated among the plurality of types of signal is significantly reduced and prevented. 
     The above and other elements, features, steps, characteristics and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments with reference to the attached drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A and 1B  are external perspective views of a circuit module. 
         FIG. 2  is a circuit diagram of a circuit module. 
         FIG. 3  is an exploded view of a circuit substrate of a circuit module. 
         FIG. 4  is a graph illustrating pass band characteristics for a reception signal. 
         FIG. 5  is a graph illustrating pass band characteristics for a transmission signal. 
         FIG. 6  is a graph illustrating isolation characteristics. 
         FIG. 7  is a magnified view of the graph illustrated in  FIG. 6 . 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Hereinafter, circuit modules according to preferred embodiments of the present invention will be described with reference to the drawings. 
     First, the configuration of a circuit module is described with reference to the drawings.  FIGS. 1A and 1B  are external perspective views of a circuit module  1 .  FIG. 1A  is a diagram of the circuit module  1  viewed from above, and  FIG. 1B  is a diagram of the circuit module  1  viewed from below.  FIG. 2  is a circuit diagram of the circuit module  1 .  FIG. 3  is an exploded view of a circuit substrate  10  of the circuit module  1 . 
     Hereinafter, the stacking direction of the circuit substrate  10  is defined as the z-axis direction. When the circuit substrate  10  is viewed in plan from the z-axis direction, a direction in which the long sides of the circuit substrate  10  extend is defined as the x-axis direction. When the circuit substrate  10  is viewed in plan from the z-axis direction, a direction in which the short sides of the circuit substrate  10  extend is defined as the y-axis direction. The x-axis direction, y-axis direction, and z-axis direction are orthogonal to one another. 
     The circuit module  1 , which is preferably mounted on a mother board of a communication apparatus, such as a cellular phone, for example, is preferably used as a component of a transmitter/receiver circuit of a cellular phone. The circuit module  1  includes the circuit substrate  10  and a duplexer  110 , as illustrated in  FIGS. 1A and 1B . 
     First, the configuration of the duplexer  110  is described. Referring to  FIGS. 1A ,  1 B and  2 , the duplexer  110  includes a main body  112 , external electrodes  114  ( 114   a  to  114   e ), SAW filters  120   a  and  120   b  (not illustrated in  FIGS. 1A and 1B ), and a ground electrode  122  (not illustrated in  FIGS. 1A and 1B ). 
     The main body  112  preferably is a multilayer body shaped like a rectangular or substantially rectangular parallelepiped, for example. For example, the main body  112  has a configuration in which, for example, the plurality of SAW filters  120   a  and  120   b , each including a comb electrode provided on, for example, a crystal substrate, are mounted on a base substrate preferably formed by stacking insulator layers made of a ceramic such as alumina and are covered by a resin or a metal cap. Referring to  FIGS. 1A and 1B , the external electrodes  114  are provided on a main surface of the main body  112  on the negative z-axis direction side and are preferably arranged in three rows and three columns, for example. The external electrode  114   a  is provided in the second row and the third column. The external electrode  114   b  is provided in the first row and the first column. The external electrode  114   c  is provided in the third row and the first column. The external electrode  114   d  is provided in the third row and the third column. The external electrodes  114   e  are five external electrodes  114  other than the external electrodes  114   a  to  114   d.    
     Referring to  FIG. 2 , the external electrode  114   a  is connected to the external electrodes  114   b  and  114   c  by signal paths SL 11  to SL 13 . In more detail, the signal path SL 11  is connected to the external electrode  114   a . The signal paths SL 12  and SL 13  are connected to the signal path SL 11  so as to branch from the signal path SL 11  as two branch paths. The external electrodes  114   b  and  114   c  are respectively connected to the signal paths SL 12  and SL 13 . 
     The SAW filters  120   a  and  120   b , which are filters with pass bands of different frequency bands, are housed in the main body  112 . In more detail, the SAW filter  120   a  is provided on the signal path SL 12 , as illustrated in  FIG. 2 , and is a filter whose pass band is the frequency band (for example, 2.15 GHz) of a reception signal. The SAW filter  120   a  outputs to the external electrode  114   b  only high-frequency signals in the frequency band of a reception signal among high-frequency signals input at the external electrode  114   a . The SAW filter  120   b  is provided on the signal path SL 13 , as illustrated in  FIG. 2 , and is a filter whose pass band is the frequency band (for example, 1.95 GHz) of a transmission signal. The SAW filter  120   b  outputs to the external electrode  114   a  high-frequency signals in the frequency band of a transmission signal among high-frequency signals input at the external electrode  114   c.    
     The ground electrode  122  is connected to the external electrodes  114   d  and  114   e . The ground electrode  122  is maintained at the ground potential through the external electrodes  114   e.    
     The configuration of the circuit substrate  10  will now be described. Referring to  FIGS. 1A ,  1 B and  FIG. 3 , the circuit substrate  10  includes a substrate main body  12  and external electrodes  14  ( 14   a  to  14   e ) and  16  ( 16   a  to  16   f ). 
     The substrate main body  12  preferably is a multilayer body shaped like a rectangular or substantially rectangular parallelepiped, for example, and has a configuration in which insulator layers  18  ( 18   a  to  18   i ) are stacked, as illustrated in  FIG. 3 . Hereinafter, a main surface of the substrate main body on the positive z-axis direction side is defined as a main surface S 1 , and a main surface of the substrate main body  12  on the negative z-axis direction side is defined as a main surface S 2 . Further, a side of the main surface S 1  on the negative y-axis direction side is defined as a side L 1 , a side of the main surface S 1  on the negative x-axis direction side is defined as a side L 2 , a side of the main surface S 1  on the positive x-axis direction side is defined as a side L 3 , and a side of the main surface S 1  on the positive y-axis direction side is defined as a side L 4 . A side of the main surface S 2  on the negative y-axis direction side is defined as a side L 5 , a side of the main surface S 2  on the negative x-axis direction side is defined as a side L 6 , a side of the main surface S 2  on the positive x-axis direction side is defined as a side L 7 , and a side of the main surface S 2  on the positive y-axis direction side is defined as a side L 8 . Further, in the substrate main body  12 , a region thereof where the duplexer  110  is mounted when viewed in plan from the z-axis direction (direction of a line normal to the main surface S 1 ) is defined as a mounting region R. 
     The insulator layers  18  are preferably formed of, for example, a ceramic and are rectangular or substantially rectangular, as illustrated in  FIG. 3 . The insulator layers  18   a  to  18   i  are stacked in such a manner as to be arranged in this order from the negative z-axis direction side to the positive z-axis direction side. Hereinafter, surfaces of the insulator layers  18  on the positive z-axis direction side are called top surfaces, and surfaces of the insulator layers  18  on the negative z-axis direction side are called bottom surfaces. The main surface S 1  of the substrate main body  12  is defined by the top surface of the insulator layer  18   i , and the main surface S 2  of the substrate main body  12  is defined by the bottom surface of the insulator layer  18   a.    
     Referring to  FIG. 1A ,  1 B and  FIG. 3 , the external electrodes  14  are provided on the main surface S 1  (i.e., the top surface of the insulator layer  18   i ) of the substrate main body  12 , and are preferably arranged in three rows and three columns, for example, so as to correspond to the external electrodes  114 . The external electrode  14   a  is provided in the second row and the third column. The external electrode  14   b  is provided in the first row and the first column. The external electrode  14   c  is provided in the third row and the first column. The external electrode  14   d  is provided in the third row and the third column. The external electrodes  14   e  preferably are five external electrodes  14  other than the external electrodes  14   a  to  14   d . As a result, when the duplexer  110  is mounted on the circuit substrate  10 , the external electrodes  14   a  to  14   e  are respectively connected to the external electrodes  114   a  to  114   e . Hence, the external electrodes  14   a  to  14   e  are arranged within the mounting region R when viewed in plan from the z-axis direction, as illustrated in  FIGS. 1A ,  1 B and  FIG. 3 . 
     Referring to  FIGS. 1A and 1B , the external electrodes  16  are provided on the main surface S 2  (i.e., the bottom surface of the insulator layer  18   a ) of the substrate main body  12 , and are arranged at the center of the main surface S 2  and along the periphery of the main surface S 2 . In more detail, the external electrode  16   a  is arranged so as to be nearest to the side L 8  among the sides L 5  to L 8 , as illustrated in  FIG. 3 . In the present preferred embodiment, the external electrode  16   a  is provided near the middle point of the side L 8 . Referring to  FIG. 3 , the external electrode  16   b  is arranged so as to be nearest to the side L 7  among the sides L 5  to L 8 . In the present preferred embodiment, the external electrode  16   b  is arranged near and on the positive y-axis direction side of the middle point of the side L 7 , among the sides L 5  to L 8 , as illustrated in  FIG. 3 . Referring to  FIG. 3 , the external electrode  16   c  is arranged so as to be nearest to the side L 6  among the sides L 5  to L 8 . In the present preferred embodiment, the external electrode  16   c  is arranged near the positive y-axis direction side end of the side L 6 . 
     Referring to  FIG. 3 , the external electrode  16   f  is arranged at the center of the main surface S 2 , and has a larger area than the external electrodes  16   a  to  16   e . Referring to  FIG. 3 , the external electrodes  16   d  and  16   e  are arranged along the periphery of the main surface S 2  together with the external electrodes  16   a  to  16   c . Hence, the external electrodes  16   a  to  16   e  are not overlapped by the mounting region R when viewed in plan from the z-axis direction. Note that regarding the external electrodes  16   d  and  16   e , only representative ones are denoted by the reference symbols in  FIGS. 1A ,  1 B and  FIG. 3  to avoid making the figures complex. 
     The internal configuration of the circuit substrate  10  will now be described. Referring to  FIG. 3 , the circuit substrate  10  includes wiring conductors  20  ( 20   a  to  20   c ),  24  ( 24   a ,  24   b , and  24   c ), ground conductors  22  ( 22   a  and  22   b ), capacitor conductors  26  ( 26   a  and  26   b ), and via hole conductors v (v 1  to v 41 ). 
     Referring to  FIG. 3 , the ground conductors  22   a  and  22   b  are respectively provided on the bottom surfaces of the insulator layers  18   b  and  18   f  and, hence, are housed in the substrate main body  12 . The ground conductors  22   a  and  22   b  cover substantially the entire bottom surfaces of the insulator layers  18   b  and  18   f  and, hence, are overlapped by the mounting region R so as to include the mounting region R when viewed in plan from the z-axis direction. However, the peripheries of the ground conductors  22   a  and  22   b  are located slightly within the peripheries of the insulator layers  18   b  and  18   f , and are not in contact with the peripheries of the insulator layers  18   b  and  18   f . Further, cutouts g 1  to g 6  are provided at the peripheries of the ground conductors  22   a  and  22   b . In addition, a hole h is provided in the ground conductor  22   b.    
     The via hole conductors v 1  to v 9  and the wiring conductor  20   a  define a signal path SL 1  (refer to  FIG. 2 ) that connects the external electrode  14   a  to the external electrode  16   a . Referring to  FIG. 3 , the via hole conductors v 7  to v 9  extend through the insulator layers  18   g  to  18   i  in the z-axis direction, and are connected to one another, thereby defining a single via hole conductor. The via hole conductor v 9  is connected to the external electrode  14   a . Hence, the via hole conductors v 7  to v 9  are located within the mounting region R when viewed in plan from the z-axis direction. 
     Referring to  FIG. 3 , the wiring conductor  20   a  is a line conductor provided on the bottom surface of the insulator layer  18   g . One end of the wiring conductor  20   a  is connected to the via hole conductor v 7 . Hence, the one end of the wiring conductor  20   a  is located within the mounting region R when viewed in plan from the z-axis direction. The other end of the wiring conductor  20   a  overlaps the external electrode  16   a  when viewed in plan from the z-axis direction. Hence, the other end of the wiring conductor  20   a  is located outside of the mounting region R when viewed in plan from the z-axis direction. Further, the other end of the wiring conductor  20   a  is located nearest to the side L 4  among the sides L 1  to L 4 . In this manner, the wiring conductor  20   a  extends from within the mounting region R to the outside of the mounting region R between the main surface S 1  and the ground conductor  22   b  when viewed in plan from the z-axis direction. 
     Referring to  FIG. 3 , the via hole conductors v 1  to v 6  extend through the insulator layers  18   a  to  18   f , and are connected to one another, thereby defining a single via hole conductor. The via hole conductor v 1  is connected to the external electrode  16   a . Hence the via hole conductors v 1  to v 6  are located outside of the mounting region R when viewed in plan from the z-axis direction. Further, the via hole conductor v 6  is connected to the other end of the wiring conductor  20   a . Hence, the via hole conductors v 1  to v 6  are located nearest to the side L 4  among the sides L 1  to L 4  when viewed in plan from the z-axis direction. Hence, the via hole conductors v 1  to v 6  connect the wiring conductor  20   a  to the external electrode  16   a  outside of the mounting region R when viewed in plan from the z-axis direction. 
     Further, the via hole conductors v 2  and v 6  respectively pass through the cutouts g 1  and g 4  provided in the ground conductors  22   a  and  22   b . Hence, the via hole conductors v 1  to v 6  are not connected to the ground conductors  22   a  and  22   b.    
     Referring to  FIG. 2  and  FIG. 3 , the signal path SL 1  configured as described above connects the external electrode  14   a  to the external electrode  16   a . Further, when viewed in plan from the z-axis direction, the signal path SL 1  extends from within the mounting region R to the outside of the mounting region R between the main surface S 1  and the ground conductor  22   b , extends through the outside of the mounting region R, and is connected to the external electrode  16   a.    
     The via hole conductors v 10  to v 18  and the wiring conductor  20   b  define a signal path SL 2  (refer to  FIG. 2 ) that connects the external electrode  14   b  to the external electrode  16   b . Referring to  FIG. 3 , the via hole conductors v 16  to v 18  extend through the insulator layers  18   g  to  18   i  in the z-axis direction, and are connected to one another, thereby defining a single via hole conductor. The via hole conductor v 18  is connected to the external electrode  14   b . Hence, the via hole conductors v 16  to v 18  are located within the mounting region R when viewed in plan from the z-axis direction. 
     Referring to  FIG. 3 , the wiring conductor  20   b  is a line conductor provided on the bottom surface of the insulator layer  18   g . One end of the wiring conductor  20   b  is connected to the via hole conductor v 6 . Hence, the one end of the wiring conductor  20   b  is located within the mounting region R when viewed in plan from the z-axis direction. The other end of the wiring conductor  20   b  overlaps the external electrode  16   b  when viewed in plan from the z-axis direction. Hence, the other end of the wiring conductor  20   b  is located outside of the mounting region R when viewed in plan from the z-axis direction. Further the other end of the wiring conductor  20   b  is located nearest to the side L 3  among the sides L 1  to L 4  when viewed in plan from the z-axis direction. In this manner, the wiring conductor  20   b  extends from within the mounting region R to the outside of the mounting region R between the main surface S 1  and the ground conductor  22   b  when viewed in plan from the z-axis direction. 
     Referring to  FIG. 3 , the via hole conductors v 10  to v 15  extend through the insulator layers  18   a  to  18   f  in the z-axis direction, and are connected to one another, thereby defining a single via hole conductor. The via hole conductor v 10  is connected to the external electrode  16   b . Hence, the via hole conductors v 10  to v 15  are located outside of the mounting region R when viewed in plan from the z-axis direction. Further, the via hole conductor v 15  is connected to the other end of the wiring conductor  20   b . Hence, the via hole conductors v 10  to v 15  are provided nearest to the side L 3  among the sides L 1  to L 4  when viewed in plan from the z-axis direction. Hence, the via hole conductors v 10  to v 15  connect the wiring conductor  20   b  to the external electrode  16   b  outside of the mounting region R. 
     Further, the via hole conductors v 11  and v 15  respectively pass through the cutouts g 2  and g 5  provided in the ground conductors  22   a  and  22   b . Hence, the via hole conductors v 10  to v 15  are not connected to the ground conductors  22   a  and  22   b.    
     Referring to  FIG. 2  and  FIG. 3 , the signal path SL 2  configured as described above connects the external electrode  14   b  to the external electrode  16   b . Further, when viewed in plan from the z-axis direction, the signal path SL 2  extends from within the mounting region R to the outside of the mounting region R between the main surface S 1  and the ground conductor  22   b , extends through the outside of the mounting region R, and is connected to the external electrode  16   b.    
     The via hole conductors v 19  to v 27  and the wiring conductor  20   c  define a signal path SL 3  (refer to  FIG. 2 ) that connects the external electrode  14   c  to the external electrode  16   c . Referring to  FIG. 3 , the via hole conductors v 25  to v 27  extend through the insulator layers  18   g  to  18   i  in the z-axis direction, and are connected to one another, thereby defining a single via hole conductor. The via hole conductor v 27  is connected to the external electrode  14   c . Hence, the via hole conductors v 25  to v 27  are located within the mounting region R when viewed in plan from the z-axis direction. 
     Referring to  FIG. 3 , the wiring conductor  20   c  is a line conductor provided on the bottom surface of the insulator layer  18   g . One end of the wiring conductor  20   c  is connected to the via hole conductor v 25 . Hence, the one end of the wiring conductor  20   c  is located within the mounting region R when viewed in plan from the z-axis direction. The other end of the wiring conductor  20   c  overlaps the external electrode  16   c  when viewed in plan from the z-axis direction. Hence, the other end of the wiring conductor  20   c  is located outside of the mounting region R when viewed in plan from the z-axis direction. Further the other end of the wiring conductor  20   c  is located nearest to the side L 2  among the sides L 1  to L 4  when viewed in plan from the z-axis direction. In this manner, the wiring conductor  20   c  extends from within the mounting region R to the outside of the mounting region R between the main surface S 1  and the ground conductor  22   b  when viewed in plan from the z-axis direction. 
     Referring to  FIG. 3 , the via hole conductors v 19  to v 24  extend through the insulator layers  18   a  to  18   f  in the z-axis direction, and are connected to one another, thereby defining a single via hole conductor. The via hole conductor v 19  is connected to the external electrode  16   c . Hence, the via hole conductors v 19  to v 24  are located outside of the mounting region R when viewed in plan from the z-axis direction. Further, the via hole conductor v 24  is connected to the other end of the wiring conductor  20   c . Hence, the via hole conductors v 19  to v 24  are provided nearest to the side L 2  among the sides L 1  to L 4  when viewed in plan from the z-axis direction. Hence, the via hole conductors v 19  to v 24  connect the wiring conductor  20   c  to the external electrode  16   c  outside of the mounting region R. 
     Further, the via hole conductors v 20  and v 24  respectively pass through the cutouts g 3  and g 6  provided in the ground conductors  22   ba  and  22   b . Hence, the via hole conductors v 19  to v 24  are not connected to the ground conductors  22   a  and  22   b.    
     Referring to  FIG. 2  and  FIG. 3 , the signal path SL 3  configured as described above connects the external electrode  14   c  to the external electrode  16   c . Further, when viewed in plan from the z-axis direction, the signal path SL 3  extends from within the mounting region R to the outside of the mounting region R between the main surface S 1  and the ground conductor  22   b , extends through the outside of the mounting region R, and is connected to the external electrode  16   c.    
     The via hole conductors v 33  to v 41  and the ground conductors  22   a  and  22   b  define a ground path GL 1  (refer to  FIG. 2 ) that connects the external electrode  14   e  to the external electrode  16   d . Referring to  FIG. 3 , the via hole conductor v 33  extends through the insulator layer  18   a  in the z-axis direction, and the via hole conductor v 33  connects the external electrode  16   d  to the ground conductor  22   a . The via hole conductor v 33  is located outside of the mounting region R when viewed in plan from the z-axis direction. Note that in  FIG. 3  only the representative via hole conductor v 33  is denoted by the reference symbol to avoid making the figure complex. 
     Referring to  FIG. 3 , the via hole conductors v 34  to v 37  extend through the insulator layers  18   b  to  18   e  in the z-axis direction, and are connected to one another, thereby defining a single via hole conductor. The via hole conductors v 34  to v 37  connect the ground conductor  22   a  to the ground conductor  22   b . Further, the via hole conductors v 34  to v 37  are located outside of the mounting region R when viewed in plan from the z-axis direction. Note that in  FIG. 3  only the representative via hole conductors v 34  to v 37  are denoted by the reference symbols to avoid making the figure complex. 
     Referring to  FIG. 3 , the via hole conductors v 38  to v 41  extend through the insulator layers  18   f  to  18   i  in the z-axis direction, and are connected to one another, thereby defining a single via hole conductor. The via hole conductors v 38  to v 41  connect the ground conductor  22   b  to the external electrodes  14   e . Further, the via hole conductors v 38  to v 41  are provided within the mounting region R when viewed in plan from the z-axis direction. Note that in  FIG. 3  only the representative via hole conductors v 38  to v 41  are denoted by the reference symbols to avoid making the figure complex. 
     The ground path GL 1  arranged as described above, connects the external electrode  14   e  to the external electrode  16   d  as illustrated in  FIG. 2  and  FIG. 3 . Here, the external electrodes  14   e  are connected to the external electrodes  114   e  as illustrated in  FIGS. 1A ,  1 B and  FIG. 2 . The external electrodes  114   e  are connected to the ground electrode  122  of the duplexer  110 . The external electrode  114   d , in addition to the external electrodes  114   e , is also connected to the ground electrode  122 . The external electrode  114   d  is connected to the external electrode  14   d . Hence, the ground path GL 1  connects the external electrode  14   e , which is part of the external electrode  14   d  and the external electrodes  14   e  electrically connected to the ground electrode  122 , to the external electrode  16   d.    
     The circuit module  1  has a configuration that reduces undesirable interference generated between a transmission signal and a reception signal. Hereinafter, this configuration will be described. 
     The wiring conductor  24   a  and the capacitor conductor  26   a  are provided on the bottom surface of the insulator layer  18   c . The capacitor conductor  26   a  preferably is a rectangular or substantially rectangular conductor and defines one electrode of a capacitor C illustrated in  FIG. 2 . The wiring conductor  24   a  is a line conductor. One end of the wiring conductor  24   a  is connected to the via hole conductor v 12 . The other end of the wiring conductor  24   a  is connected to the capacitor conductor  26   a . As described above, the via hole conductor v 12  defines a portion of the signal path SL 2 . Hence, the one electrode (the capacitor conductor  26   a ) of the capacitor C is connected to the signal path SL 2  as illustrated in  FIG. 2 . 
     The wiring conductors  24   b  and  24   c , the capacitor conductor  26   b , and the via hole conductors v 28  to v 32  define a ground path GL 2  (refer to  FIG. 2 ), which is connected to the external electrode  14   d . Referring to  FIG. 3 , the via hole conductors v 28  and v 29  extend through the insulator layers  18   e  and  18   f  in the z-axis direction and are connected to one another, thereby defining a single via hole conductor. Note that the ground conductor  22   b  has the hole h provided therein, and the via hole conductor v 29  extends through the hole h. Hence, the via hole conductors v 28  and v 29  are insulated from the ground conductor  22   b.    
     Referring to  FIG. 3 , the wiring conductor  24   c  is a line conductor provided on the bottom surface of the insulator layer  18   g . One end of the wiring conductor  24   c  is connected to the via hole conductor v 29 . The other end of the wiring conductor  24   c  is overlapped by the external electrode  14   d  when viewed in plan from the z-axis direction. The via hole conductors v 30  to v 32  extend through the insulator layers  18   g  and  18   i  and are connected to one another, thereby defining a single via hole conductor. The via hole conductor v 30  is connected to the other end of the wiring conductor  24   c . The via hole conductor v 32  is connected to the external electrode  14   d.    
     The capacitor conductor  26   b  preferably is a rectangular or substantially rectangular conductor and defines the other electrode of the capacitor C illustrated in  FIG. 2 . Hence the capacitor conductor  26   b  overlaps the capacitor conductor  26   a  when viewed in plan from the z-axis direction. The wiring conductor  24   b  is a line conductor. One end of the wiring conductor  24   b  is connected to the via hole conductor v 28 . The other end of the wiring conductor  24   b  is connected to the capacitor conductor  26   b.    
     Referring to  FIG. 2  and  FIG. 3 , the ground path GL 2  configured as described above is connected to the external electrode  14   d , which is not connected to the external electrodes  16 , and is capacitively coupled to the signal path SL 2 . 
     In the circuit module  1  configured as described above, a reception signal is input at the external electrode  16   a . The reception signal passes through the SAW filter  120   a , and is output to the outside of the circuit module  1  through the external electrode  16   b . Here, the SAW filter  120   b  has a pass band that is the frequency band of a transmission signal and does not have a pass band that is the frequency band of a reception signal. Hence, the reception signal input at the external electrode  16   a  cannot pass through the SAW filter  120   b  and, hence, is not output from the external electrode  16   c.    
     A transmission signal is input at the external electrode  16   c . The transmission signal passes through the SAW filter  120   b  and is output to the outside of the circuit module  1  through the external electrode  16   a . Here, the SAW filter  120   a  has a pass band that is the frequency band of a reception signal and does not have a pass band that is the frequency band of a transmission signal. Hence, the transmission signal which has passed the SAW filter  120   b  cannot pass through the SAW filter  120   a  and, hence, is not output from the external electrode  16   b.    
     The circuit module  1  described above significantly reduces and prevents undesirable interference generated between a transmission signal and a reception signal. In more detail, as illustrated in  FIG. 2  and  FIG. 3 , the ground path GL 2  connected to the ground electrode  122  of the duplexer  110  is capacitively coupled through the capacitor C to the signal path SL 2  over which a reception signal is transmitted. As a result, undesirable interference generated between a transmission signal and a reception signal is significantly reduced and prevented. The inventor of the present invention performed computer simulation described below to confirm the advantageous effects of the circuit substrate  10  according to a preferred embodiment of the present invention. 
     First, a model of the circuit module  1  was created as a first model. Here, the capacitance of the capacitor C was set to 0.97 pF, for example. Further, a model of the circuit module  1  without the capacitor C was created as a second model. Then, by inputting a transmission signal and a reception signal to the first model and the second model, pass band characteristics (pass band characteristics for a reception signal) between the external electrodes  16   a  and  16   b , pass band characteristics (pass band characteristics for a transmission signal) between the external electrodes  16   a  and  16   c , and pass band characteristics (isolation characteristics) between the external electrodes  16   b  and  16   c  were determined.  FIG. 4  is a graph illustrating the pass band characteristics for a reception signal.  FIG. 5  is a graph illustrating the pass band characteristics for a transmission signal.  FIG. 6  is a graph illustrating the isolation characteristics.  FIG. 7  is a magnified view of the graph illustrated in  FIG. 6 . In  FIG. 4  to  FIG. 7 , the vertical axis represents insertion loss, and the horizontal axis represents frequency. 
       FIG. 4  and  FIG. 5  show that the pass band for a transmission signal is different from the pass band for a reception signal. In other words, it can be seen that the circuit module  1  functions as a duplexer. Further, as can be seen from the graphs of the isolation characteristics illustrated in  FIG. 6  and  FIG. 7 , the insertion loss in the first model is larger than that in the second model. This shows that the first model achieves better isolation characteristics between the external electrodes  16   b  and  16   c  than the second model. Hence, it can be seen that undesirable interference generated between a transmission signal and a reception signal can be significantly reduced in the first model more than in the second model. 
     Further, the circuit substrate  10  can significantly reduce undesirable interference generated between a transmission signal and a reception signal also due to the following reason. Specifically, in the circuit substrate  10 , the ground conductors  22   a  and  22   b  are overlapped by the mounting region R so as to include the mounting region R when viewed in plan from the z-axis direction, as illustrated in  FIG. 3 . Further, when viewed in plan from the z-axis direction, the signal paths SL 1  to SL 3  extend to the outside of the mounting region R between the main surface S 1  and the ground conductor  22   b , extend through the outside of the mounting region R, and are connected to the external electrodes  16   a  and  16   c . Hence, when viewed in plan from the z-axis direction, the ground conductors  22   a  and  22   b  exist between any two of the signal path SL 1 , the signal path SL 2 , and the signal path SL 3 . The ground conductors  22   a  and  22   b  are maintained at the ground potential. As a result, undesirable interference generated between a transmission signal and a reception signal in the signal paths SL 1  to SL 3  can be reduced. 
     Further, undesirable interference generated between a transmission signal and a reception signal can be reduced in the circuit module  1  also due to the following reason. In detail, in the circuit module  1 , the via hole conductors v 1  to v 6  of the signal path SL 1  are located nearest to the side L 4  among the sides L 1  to L 4 , the via hole conductors v 10  to v 15  of the signal path SL 2  are located nearest to the side L 3  among the sides L 1  to L 4 , and the via hole conductors v 19  to v 24  of the signal path SL 3  are located nearest to the side L 2  among the sides L 1  to L 4 . Hence, the via hole conductors v 1  to v 6 , the via hole conductors v 10  to v 15 , and the via hole conductors v 19  to v 24  are close to different sides. In other words, the via hole conductors v 1  to v 6 , the via hole conductors v 10  to v 15 , and the via hole conductors v 19  to v 24  are arranged so as to be spaced apart from one another. As a result, undesirable interference generated between a transmission signal and a reception signal can be significantly reduced and prevented reduced in the signal paths SL 1  to SL 3 . 
     Further, referring to  FIG. 3 , the via hole conductors v 2 , v 11 , and v 20 , which respectively extend through the insides of the cutouts g 1  to g 3  of the ground conductor  22   a , are surrounded by the ground conductor  22   a . The ground conductor  22   a  is maintained at the ground potential. Hence, undesirable interference generated between a transmission signal and a reception signal can be significantly reduced and prevented in the signal paths SL 1  to SL 3 . 
     The circuit module  1  configured as described above is not limited to the preferred embodiment described above. Hence, the circuit module  1  can be modified within the scope of the present invention. 
     Although the signal path SL 2  preferably is capacitively coupled to the ground path GL 2  in the circuit module  1  as described above, the signal path SL 1  may be capacitively coupled to the ground path GL 2 , for example. 
     Although the signal path SL 2  preferably is capacitively coupled to the ground path GL 2  in the circuit module  1  as described above, these elements need only be electromagnetically coupled to each other. Hence, the signal path SL 2  may be magnetically coupled to the ground path GL 2 , for example. 
     In the circuit module  1 , the signal path SL 2  may be connected to the ground path GL 2  through a phase unit instead of being electromagnetically coupled to the ground path GL 2 . A phase unit has a configuration in which a wiring electrode is provided instead of the capacitor C illustrated in  FIG. 2  and the phase is changed by adjusting the electrode length of the wiring electrode. The phase of the phase unit is, for example, 71.3° or 74.8°. Further, a balanced filter including a balanced-unbalanced conversion function may be used as the reception filter. 
     Note that the ground conductors  22   a  and  22   b  need not be provided. 
     Note that one end of the ground electrode  122  is connected to only the external electrodes  114   e  and  114   d  and the other end of the ground electrode  122  is not connected to any component, as illustrated in  FIG. 2 . However, the other end of the ground electrode  122  may be connected to a component within the duplexer  110  or, for example, connected to the ground terminal of the SAW filter  120   a  or  120   b.    
     Although the single ground electrode  122  preferably is provided for the external electrodes  114   e  and  114   d , the ground electrode  122  may be provided for each of the external electrodes  114   e  and  114   d , for example. Further, the ground electrode  122  need only be a conductor that is maintained at the ground potential, and may be a line conductor defining the wiring or a planar conductor with a comparatively large area. 
     Preferred embodiments of the present invention are useful in a circuit substrate and, in particular, are advantageous in that undesirable interference generated among a plurality of types of signal is significantly reduced and prevented. 
     While preferred embodiments of the present invention have been described above, it is to be understood that variations and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the present invention. The scope of the present invention, therefore, is to be determined solely by the following claims.