Abstract:
A power switching device which is used to receive plenty of input voltage and output a switch voltage is provided. The device comprises a first switching unit, a second switching unit, and a self-bias unit. The power switching device outputs a switch voltage according to the outputs of the first switching unit and the second switching unit. The self-bias unit outputs a reference voltage to the second switching unit. The first switching unit outputs a first input voltage as the switch voltage according to a first enable signal. The second switching unit outputs a second input voltage as the switch voltage according to the reference voltage and a second enable signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims the priority benefit of Taiwan application serial no. 95106967, filed on Mar. 2, 2006. All disclosure of the Taiwan application is incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of Invention  
         [0003]     The present invention relates to a power switch device. More particularly, the present invention relates to a power switch device with a self-biasing circuit.  
         [0004]     2. Description of Related Art  
         [0005]     With the high demand on portable electronic devices, power management is an important issue for maintaining operation time. Generally, the portable electronic device integrates a lot of components and those components may be powered by different power sources.  
         [0006]      FIG. 1  shows a conventional power switch device including switches S 11  and S 12 . First terminals of the switches S 11  and S 12  receive input voltages Vin 11  and Vin 12  respectively. Second terminals of the switches S 11  and S 12  are coupled together for outputting a power source Vpp 1 . Two non-overlapping enable signals SEN 11  and SEN 12  are used for controlling the voltage switch. The switch S 11  is turned on under control of the enable signal SEN 11  while at the same time the switch S 12  is turned off under control of the enable signal SEN 12 ; and the switch S 11  is turned off under control of the enable signal SEN 11  while at the same time the switch S 12  is turned on under control of the enable signal SEN 12 . When the switch S 11  is turned on and the switch S 12  is turned off, the power source Vpp 1  takes in the input voltage Vin  11 . Similarly, when the switch S 12  is turned on and the switch S 11  is turned off, the power source Vpp 1  takes in the input voltage Vin 12 . The power source Vpp 1  is switched as either of the input voltages Vin 11  and Vin 12 . Therefore, under control of the enable signal SEN 11  and SEN 12 , the conventional power switch device supplies the power source Vpp 1  with different voltage values.  
         [0007]     However, if the power source Vpp 1  is used in a high voltage application, the power switch device has to be manufactured by high voltage manufacturing process. For example, if the power source Vpp 1  is switched as either one of 1.8V and 7V, a high voltage manufacturing process suitable for 7V power source is applied to make the power switch device. But the resultant power switch device by high voltage manufacturing process has large circuit size and severe power consumption.  
       SUMMARY OF THE INVENTION  
       [0008]     One of the aspects of the invention is to provide a power switch device for supplying a power source taking in high and low input voltages and the power switch may be made by a low voltage manufacturing process.  
         [0009]     Another aspect of the invention is to provide a power switch device for supplying a power source taking in high and low input voltages and the power switch may have compact circuit size and low power consumption.  
         [0010]     For the above and other aspects, the invention provides a power switch device, including a first switch circuit, a self-biasing circuit and a second switch circuit. The power switch device generates an output voltage based on outputs of the first and the second switch circuits. When the first switch circuit outputs the output voltage, the first switch circuit takes the first input voltage as the output voltage under control of a first enable signal. When the second switch circuit outputs the output voltage, the second switch circuit takes the second input voltage as the output voltage under control of a second enable signal.  
         [0011]     The self-biasing circuit includes two resistors and two switches, wherein the switches both include a single N-type MOSFET. When the first and the second enable signals control conduction states of the first and the second switch circuits, the first enable signal also controls the switch inside the self-biasing circuit, so that a reference voltage generated from the self-biasing circuit makes a switch, receiving the reference voltage, inside the second switch circuit turned on.  
         [0012]     In the invention, the power switch device is manufactured by low voltage manufacturing process. Therefore, the power switch device has small circuit layout and low power consumption.  
         [0013]     It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.  
         [0015]      FIG. 1  shows a conventional power switch device.  
         [0016]      FIG. 2  shows a power switch device according to an embodiment of the present invention.  
         [0017]      FIG. 3  shows details of the power switch device according to the embodiment of the present invention.  
         [0018]      FIG. 4  shows a signal timing diagram for the power switch device according to the embodiment of the present invention.  
         [0019]      FIGS. 5 and 6  show operations of the power switch device under different modes. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0020]     Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.  
         [0021]      FIG. 2  shows a power switch device according to an embodiment of the present invention. As shown in  FIG. 2 , the power switch device includes a first switch circuit  201 , a second switch circuit  202  and a self-biasing circuit  203 . The first switch circuit  201  and the second switch circuit  202  respectively receive input voltages Vin 21  and Vin 22 . Output terminals of the first switch circuit  201  and the second switch circuit  202  are coupled to each other. The self-biasing circuit  203  is coupled to the second switch circuit  202  for supplying a reference voltage VREF to the second switch circuit  202 . An enable signal SEN 21  is used for controlling the first switch circuit  201  and the self-biasing circuit  203 . The second switch circuit  202  is controlled according to another enable signal SEN 22  and the reference voltage VREF. The enable signals SEN 21  and SEN 22  are non-overlapping or reversed with each other. An output voltage Vpp 2  is generated based on outputs of the first switch circuit  201  and the second switch circuit  202 .  
         [0022]      FIG. 3  shows details of the power switch device according to the embodiment of the present invention. As shown in  FIG. 3 , the first switch circuit  201  includes switches S 23  and S 24 . The second switch circuit  202  includes switches S 21  and S 22 . The self-biasing circuit  203  includes resistors R 31  and R 32  and switches S 25  and S 26 . Each of the switches S 21 , S 22  and S 23  includes a single P-type MOSFET and each of the switches S 24 , S 25  and S 26  includes a single N-type MOSFET.  
         [0023]     The switch S 21  includes: a first terminal (source terminal) coupled to the input voltage Vin 22 , a second terminal (drain terminal) coupled to a first terminal of the switch S 22  and a third terminal (gate terminal) coupled to the reference voltage VREF. Conduction state of the switch S 21  is under control of the reference voltage VREF. The switch S 22  includes: the first terminal (source terminal) coupled to the second terminal of the switch S 21 , a second terminal (drain terminal) coupled to a second terminal of the switch S 24  for outputting the output voltage Vpp 2  and a third terminal (gate terminal) coupled to the enable signal SEN 22 . Conduction state of the switch S 22  is under control of the enable signal SEN 22 . The switch S 23  includes: the first terminal (source terminal) coupled to the input voltage Vin 21 , a second terminal (drain terminal) coupled to a first terminal of the switch S 24  for outputting the output voltage Vpp 2  and a third terminal (gate terminal) coupled to the enable signal SEN 21 . Conduction state of the switch S 23  is under control of the enable signal SEN 21 . The switch S 24  includes: the first terminal (drain terminal) coupled to the second terminal of the switch S 23 , the second terminal (source terminal) coupled to the second terminal of the switch S 22  for outputting the output voltage Vpp 2  and a third terminal (gate terminal) coupled to the operation voltage VDD. Conduction state of the switch S 24  is under control of the operation voltage VDD. The switch S 25  includes: a first terminal (drain terminal) coupled to a second terminal of the resistor R 32 , a second terminal (source terminal) coupled to a first terminal of the switch S 26  and a third terminal (gate terminal) coupled to the operation voltage VDD. Conduction state of the switch S 25  is under control of the operation voltage VDD. The switch S 26  includes: the first terminal (drain terminal) coupled to the second terminal of the switch S 25 , a second terminal (source terminal) being grounded and a third terminal (gate terminal) coupled to the enable signal SEN 21 . Conduction state of the switch S 26  is under control of the enable signal SEN 21 .  
         [0024]     The resistor R 31  includes a first terminal coupled to the input voltage Vin 22  and a second terminal coupled to a first terminal of the resistor R 32  for outputting the reference voltage VREF. The resistor R 32  includes a first terminal coupled to the second terminal of the resistor R 31  for outputting the reference voltage VREF and the second terminal coupled to the first terminal of the switch S 25 .  
         [0025]     The connection node between the switches S 23  and S 24  is referred as a node N 1 . The connection node between the switches S 21  and S 22  is referred as a node N 2 . The connection node between the switch S 25  and the resistor R 23  is referred as a node N 3 . The connection node between the switches S 25  and S 26  is referred as a node N 4 .  
         [0026]      FIG. 4  shows a signal timing diagram for the power switch device according to the embodiment of the present invention. Here, the operation voltage VDD, the input voltages Vin 21  and Vin 22  are 5V, 1.8V and 7V, respectively.  FIG. 5  shows operations of the power switch device when the enable signal SEN 21  and SEN 22  are logic low (0V) and logic high (5V) respectively. Because the gate voltages of the switches S 25  and S 26  are VDD (5V) and logic low (0V) respectively, from the showing of the node voltages VN 3  and VN 4 , the gate-to-source voltages (VGS) of the switches S 25  and S 26  are lower than the threshold voltage, so the switches S 25  and S 26  are both turned off. Because of turn off of the switches S 25  and S 26 , no current is flowed in the self-biasing circuit  203  and the reference voltage VREF is equal to the input voltage Vin 22  (7V). Because the reference voltage VREF and the enable signal SEN 22  are 7V and logic high (5V) respectively, the switches S 21  and S 22  of the second switch circuit  202  are turned off and the output voltage Vpp 2  is based on the output voltage from the first switch circuit  201 . In the first switch circuit  201 , the logic low (0V) enable signal SEN 21  is coupled to the gate terminal of the switch S 23  (a P-type MOSFET) and the logic high (5V) VDD is coupled to the gate terminal of the switch S 24  (an N-type MOSFET), so the switches S 23  and S 24  are both turned on. The output voltage from the first switch circuit  201  is equal to Vin 21  (1.8V), which means the output voltage Vpp 2  is also 1.8V. In this case, the conduction states of the switches S 21 ˜S 24  is also known from the node voltage VN 1  and VN 2  in  FIG. 4 .  
         [0027]     On the contrary, when the enable signals SEN 21  and SEN 22  are logic high (5V) and logic low (0V), the conduction states of the switches S 21 ˜S 26  is shown in  FIG. 6 . From the showing of the node voltages VN 3  and VN 4 , the gate-to-source voltages of the switches S 25  and S 26  are higher than the threshold voltage, so the switches S 25  and S 26  are both turned on. Because the switches S 25  and S 26  are both turned on, the input voltage Vin 22  is dropped on the resistors R 31  and R 32 . The reference voltage VREF is generated from a voltage division on the input voltage Vin 22  by the resistors R 31  and R 32 . In the embodiment, in order to make the switch S 21  on when the output voltage Vpp 2  is output from the second switch circuit  202 , the resistance ratio of the resistors R 31  and R 32  is shown in equation (1), which means the source-to-gate voltage VSG 21  of the switch S 21  is higher than the threshold voltage (V TH ) but lower than the operation voltage VDD (5V). 
 
| V   TH   |&lt;V   SG21   &lt;VDD   (1) 
 
         [0028]     Therefore, because VSG 21  is higher than the threshold voltage and the enable signal SEN 22  is logic low (0V), the switches S 21  and S 22  of the second switch circuit  202  are both turned on. In this case, the switches S 23  and S 24  are both turned off because the enable signal SEN 21  is logic high (5V) and the gate voltage of the switch S 24  is logic high (5V). So, the output voltage Vpp 2  is generated from the second switch circuit  202 , i.e. the output voltage Vpp 2  is equal to Vin 22  (7V). Under this case, the conduction states of the switches S 21 ˜S 24  is also known from the node voltage VN 1  and VN 2  in  FIG. 4 .  
         [0029]     The power switch device is produced by a manufacturing process suitable for the operation voltage VDD of 5V, for making the output voltage Vpp 2  being switched as either one of 1.8V and 7V. By fine tuning the resistance values of the resistors R 31  and R 32  under the criteria of the equation (1), the allowable ranges of the operation voltage VDD and the output voltage Vpp 2  are changed. The second switch circuit  202 , especially, the switch S 21 , for receiving VREF (in the case of being 7V), may be manufactured by a 5V manufacturing process if the switch S 21  still meets the equation (1). For example, if the power switch device is used for generating the output voltage Vpp 2  switched as either one of 2.5V and 8V, by tuning resistance values of the resistors R 31  and R 32  within the criteria of the equation (1), the switch S 21  of the second switch circuit  202 , receiving a high voltage (8V) at its gate terminal, still can be manufactured by a 5V manufacturing process, rather than a 8V manufacturing process, because the resultant P-type MOSFET (the switch S 21 ) can stand for 8V at its gate terminal and most importantly, its V SG  is still lower than VDD (5V).  
         [0030]     The embodiment of the invention may be appropriately applied as a power supply circuit for a memory, such as a flash memory. For example, when the flash memory is under programming mode, a high power supply (for example, 7V), used for programming the flash memory, is generated from the second switch circuit  202 . When the flash memory is under normal mode, a low power supply (for example, 1.8V), used for powering the flash memory, is generated from the first switch circuit  201 .  
         [0031]     In this embodiment, the voltage division is carried out by the resistors R 31  and R 32  for generating the reference voltage VREF. Serially connected diodes or MOSFETs can be used to replace the resistors R 31  and R 32  for dividing the input voltage Vin 22  into the reference voltage VREF.  
         [0032]     In the invention, the power switch device is manufactured by low voltage manufacturing process. Therefore, the power switch device has small circuit layout and low power consumption.  
         [0033]     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing descriptions, it is intended that the present invention covers modifications and variations of this invention if they fall within the scope of the following claims and their equivalents.