Abstract:
A data storage apparatus includes a command processor that receives write commands and data blocks from a host, the write commands comprising block ID&#39;s (BID) corresponding to data blocks; storage resources including semiconductor memory and mass storage; a data manager that selects storage resources and allocates selected resources to block ID&#39;s; a translation table to map a storage resource to the allocated block ID, and storage resources that are selected after receipt of the write command. A method is further provided for increasing performance in a storage device comprising a plurality of storage resources, transferring data to a storage resource that is available to transfer the data.

Description:
BACKGROUND 
     The use of data storage devices has become ubiquitous in homes as well as businesses. Demand for higher performance as well as flexibility and expandability provides a challenging environment with currently available solutions. Home applications require user friendly attachment and simple expansion for increasing storage capacity and/or performance. Add-on storage, such as external desktop drives, network attached drives, and portable hard drives are widely used for storage of home entertainment, photos, and home office applications. Home entertainment such as Digital Video Recorders (DVR), expanders, and media players push data storage requirements and performance speeds higher. 
     As the demands for expandability and higher performance grow, communications channels have increased their speed and in some cases outpaced the ability of storage devices to provide all the performance that might otherwise be achieved. 
     Newer communication channels have advanced to be able to communicate in two directions at the same time, for example, writing data and reading data simultaneously over a single connection. In home entertainment applications such as DVR&#39;s this is useful, for example, when recording one program while watching another program at the same time. 
     Current storage solutions that incorporate storage devices, such Hard Disk Drives (HDD), Solid State Drives (SSD), or semiconductor memories may limit performance or expandability since they are limited by the underlying devices they contain. 
     The products that incorporate underlying storage devices, or attach to storage devices are called bridges. 
     Bridges may be stand alone devices incorporating underlying storage, such as a DVR or desktop storage used for direct attachment to a computer. In some cases, the bridge is provided and the user provides data storage to be attached to the bridge. Some bridges incorporate storage and also allow for additional external storage. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a block diagram of an embodiment of the invention. 
         FIG. 2  illustrates a flow chart of an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  illustrates a block diagram of an embodiment of the invention. A bridge  100  comprises a command processor  110  for connection to a host  10 ; a data manager  140 , a buffer manager  130 , semiconductor memory  120 , resource manager  150 , and connections to any number of Mass Storage (MS) devices as exemplified by MS devices  181 - 84 . 
     Bridge  100  is operatively connected to a host  10 . The host  10  may be, for example, a desktop computer, a server, a notebook computer, or an application specific controller. Any apparatus that is capable of sending commands and data to the bridge  100  is hereinafter referred to as a host. 
     In one embodiment, the interface between the host  10  and the bridge  100  may be a Universal Serial Bus interface, commonly referred to as a USB interface. The USB interface also may be referred to as USB-1, USB-2, or USB-3, and future revisions may be expected. Universal Serial Bus is specified by the Universal Serial Bus Specification, version 2.0 released Apr. 27, 2000, and version 3.0 dated Nov. 12, 2008; available from the USB Implementers Forum, Inc., at www.USB.org. 
     Other standards are also available for hardware and software connection between computers or other hosts and peripherals, such as bridge  100 . Some widely adopted examples include AT Attachment (ATA), also known as AT Attachment-8-Parallel Transport (ATA8-APT), Serial Attached SCSI (SAS), or Serial ATA (SATA or eSATA), or USB Attached SCSI (UAS) communication interfaces. Specifications for these standards are readily available. Other wired or wireless interfaces may also connect host  10  and bridge  100 . 
     In some embodiments, the command processor  110  includes a disk drive controller or standard peripheral interface controller capable of performing the operations required of the interface between the host  10  and the bridge  100 . Interface controllers are used, for example, in disk drives and USB devices; and numerous embodiments exist. Any command processor embodiment that performs the host interface protocol and able to send and receive data into a buffer will work with the invention. Embodiments that support full duplex operation require that read path  30  and write path  40  be capable of transferring data simultaneously. For example, USB-3 supports full duplex operation. 
     In the embodiment shown in  FIG. 1 , the command processor  110  receives commands through a command interface  20 , writes data thorough write path  40 , and reads data through read path  30 . Although shown as separate interfaces to simplify explanation, the paths  20 ,  30 , and  40  may be shared. In some embodiments, commands or write data may both be sent on the same path  40 ; and status or read data on the same path  30 . Similarly, all communications such as commands and data may be exchanged across a bidirectional path  20 . 
     In embodiments of the invention, the MS devices  181 - 84  may be non-volatile (NV) memory, for example, a hard disk drive (HDD), a solid state drive (SSD), or a mix of types. In other embodiments, there may be as few as one, or a large number of MS devices. 
     In some embodiments, the semiconductor memory  120  may be volatile memory, NV memory, combinations of the same, or the like. 
     The semiconductor memory  120  may be divided into a read buffer  121  and a write buffer  122 . In some embodiments, the read buffer  120  and write buffer  121  are capable of operating to allow simultaneous transfer of read data from the read buffer  121  to the command processor  110  via path  112  and then to the host via path  130 ; and write data from the host via  40  to the command processor  110  and then to the write buffer  122  via path  114 . This simultaneous transfer capability allows for full duplex operation with the host. In some embodiments of the invention, the host may be writing data from one command and reading another command simultaneously. 
     In the embodiment of the invention shown in  FIG. 1 , it is not required that the MS devices  181 - 84  be able to support full duplex operations. The data manager  140  coordinates the transfers between the MS devices and buffers  121  and  122  independently of the transfers between the command processor  110  and the buffers  121  and  122 . 
     References hereinafter to buffers may include the read buffer  121 , write buffer  122 , or both buffers operating independently or in combination. 
     The data manager  140  may comprise any suitable control means. In some embodiments, the data manager  140  may comprise a microcontroller or microprocessor, program memory, and application programs. The data manager may also include the capability to control data movements between the command processor  110  and the buffers, and from the buffers to the resource manager  150 . Data transfers may also be accomplished in cooperation with a buffer manager  130 , which automates data transfers between the command processor  110  and the resource manager  150 . In one embodiment, the buffer manager  130  may be a Direct Memory Access (DMA) controller. DMA controllers are well known in the art and provide high performance with low microprocessor overhead. 
     Data from the host  10  will have a Block Identification (BID), assigned by the host  10 , typically provided as part of the host read or write command. Data associated with a BID is referred to as BID data. Data from the host is stored in buffer locations with a Buffer Memory Address (BMA). The BMA may be provided by the data manager  140 . A BID to BMA translation may be saved in any suitable manner, for example, a lookup table  160 . In some embodiments, the BID may comprise one or more of the following types: 
     logical block address (LBA); 
     physical block address; 
     indirect address; 
     file name; 
     file length; and 
     object oriented storage description. 
     In some embodiments of  FIG. 1 , to the extent that the semiconductor memory  120  can provide the needed data storage capacity, the command processor  110 , data manager  140  and associated lookup table  160 , buffer manager  130 , and semiconductor memory  120  comprise a complete functional storage device capable of operating in full duplex mode with the host  10 . 
     In some embodiments of  FIG. 1 , when a read command is received from the host  10  requesting data previously written to a write buffer  122 , the data in the write buffer  122  may be transferred directly from the write buffer  122  to the command processor  110 . 
     Write buffer  122  and read buffer  121  may be separate memories, parts of partitioned memory, or locations in memory that are allocated as needed. The data manager  140  and buffer manager  130  can allocate semiconductor memory  120  to be used as write or read buffers and move write data from path  114 , and read data to path  112  as needed to implement the commands. 
     In some embodiments, the designation of semiconductor memory resources allocated to write buffer or read buffer may be switched, allowing data in a write buffer portion to be designated as a read buffer portion, and data in a read buffer portion to be designated as a write buffer portion. 
     In another embodiment, if a host read command is received requesting data previously written to write buffer  122 , the data in the write buffer  122  may be transferred to the read buffer  121  before being transferred to the command processor  110 . The data transfer may be accomplished by data manager  140  and buffer manager  130 . 
     In further embodiments of the invention, an intermediate buffer may be provided. When a read command is received requesting data previously written to write buffer  122 , the data in the write buffer  122  may be transferred to the intermediate buffer and then from the intermediate buffer to read buffer  121  prior to being transferred to the command processor. The intermediate buffer may be accomplished by the buffer manager  130  as another memory, as registers, or as a combination of input/output reads and writes from the buffers, using methods well known in the art. 
     Resource manager  150  may be a controller that acts as a host to the MS devices  181 - 84 . The resource manager  150  receives instructions from data manger  140  via path  141 , and data from semiconductor memory  120 . Write data destined for a MS device  181 - 84  from write buffer  122  is through path  126 . Read data from a MS device is through path  124  to read buffer  121 . Since separate paths are provided, data may be written to, and read from the resource manager simultaneously. 
     In some embodiments, write data from write buffer may be transferred via path  126  through the resource manager and written to a first MS device, for example MS device  181  through path  151 . Simultaneously, read data may be read from a second MS device, for example MS device  182  through path  152 , and transferred through the resource manager  150  via path  124  to read buffer  121 . 
     Data transfers may also be accomplished in cooperation with a buffer manager  130 , which automates data transfers between the command processor  110  and the resource manager  150 . Commands and control may also be provided to the resource manager through path  141 . Simultaneous read and write transfers may be accomplished, therefore, with any of the MS devices  181 - 84  through their respective paths  151 - 54 . 
     In other embodiments, resource manager  150  may act as a bus master capable of fetching data from and sending data to the semiconductor memory  120 . Instructions from data manager  140  may provide instructions to the resource manager  150 , and the resource manager  150  may act to control the data transfers allowed by data manager  140 . Embodiments of DMA transfers with bus masters are well known in the art. 
     When transfer of data from the buffer to the MS device  181 - 84  is desired, the data manager will locate the data using the BID to BMA translation table  160 . The data manager  140  will assign a Mass Storage Address (MSA) to the data. The MSA will identify a physical MS device, for example, one of MS devices  181 - 84 , and the BID within the MS device to be allocated. The host&#39;s BID will be mapped to the MSA and maintained in a BID-MSA translation table  170 . 
     In some embodiments in accordance with  FIG. 1 , the data manager maintains at least two translation tables, (1) BID to BMA, and (2) BID to MSA, wherein the MSA comprises the host BID and the MS device identification. The MSA is not limited to only this information, and may also include other information such as metadata, without departing from the invention. 
     The MS devices  181 - 84  are resources of the bridge  100 , not of the host  10 . The manner of assigning MSA locations to BID data may therefore be performed independently from host activity and BID assignments, and the host  10  may not be aware of which physical MS device contains its BID data. 
     This mechanism of making the MS devices  181 - 84  resources of the bridge  100  allows for allocation of MS resources in the most efficient or best performing manner. 
     Data transfers between the MS resources and the semiconductor memory  120  are independent of the transfers between the semiconductor memory  120  and the command processor  110 . 
     In embodiments of the present disclosure, the host  10  can maintain full duplex operation with the data contained in the buffer. When the MS devices are only half duplex, one device can be writing and another reading thereby supporting full duplex data transfers to the buffers and thereby to the command processor  110  and the host  10 . 
     Typically, if a host needs to write half-duplex storage that is busy reading data, then the performance will be limited by the storage device&#39;s half duplex limitation. The host would need to wait to write the data. 
     The following description describes some embodiments of the invention that overcome the half duplex limitation of the MS devices. 
     Because the data manager  140  assigns the physical location where the host BID data will be written and then provides a translation for future operations, the data manager  140  may select the MS device  181 - 84  that is most convenient. In some embodiments of the invention, it is not necessary for a specific BID to be written to a specific MS device, or even the same MS device as it was previously written. The data manager can simply update the BID to MSA translation table  170  when writing blocks of data. 
     In an example of such an embodiment, a specific MS device may be busy transferring read data to the buffer, and the host has commanded a write to a BID that is contained on the busy device. The data manager  140  then selects another MS device that is not busy, writes the BID data to the selected MS device, and updates the BID to MSA translation table  170 . Updating this table also effectively frees the memory of the busy MS device that previously stored this data, as it will now be listed as free in the table. The performance between the MS devices and the buffer can be effectively doubled, even though no single MS device supports full duplex operation. 
     The bridge  100 , having the ability to assign BID data to any MS device, even a different device than previously assigned, allows the Bridge  100  to perform as a full duplex device across the host interface (paths  20 ,  30 ,  40 ) providing doubled performance by using two MS devices operating in half duplex mode. This is permitted even though read and write operations are addressing BID&#39;s contained on the same mass storage device, because BID&#39;s being written will be relocated to another device that is able to transfer data. 
     In some embodiments, additional MS devices may be added at any time to increase the capacity and/or the performance. This capability is accomplished by the data manager extending the BID to MSA translation table  170  to include the new MS devices. 
       FIG. 2  illustrates a flow chart of an operation following the embodiment shown in  FIG. 1 . In this example, write commands are performed as full duplex, even though reads may be occurring on any of the MS devices simultaneously. 
     Starting in block  200 , a command is received from the host  10  by the bridge  100 . At block  210 , the bridge determines that the command is a write command. At block  220 , the data manager  140  assigns a BMA in the semiconductor memory  120  and write buffer  122 . The assigned BMA is added to the translation table  160 . 
     In block  230 , the command processor  110 , data manager  140 , and buffer manager  130  transfer the data from the host  10  via path  40 , through the command processor  110 , and to the write buffer  122  via path  114 . 
     In block  240  a decision is made by the data manager  140  to move the data from the semiconductor memory  120  to mass storage. The data manager  140  assigns a MS device, in this example, MS device  181 , in block  250 . In block  260 , the data manager determines whether the MS device  181  is available to transfer data by inquiry to resource manager  150 . The MS device  181  may be unavailable because it is busy with another activity, for example, reading or writing. The MS device  181  may also be unavailable because it is out of capacity. Other reasons may include, for example, that the MS device  181  is off-line, in maintenance, undergoing environmental disturbance, or any other reason that data transfers are not possible or delayed. 
     If the selected MS device, (MS device  181  in this example) is not available, the data manager  140  selects another MS device (for example, MS device  182 ) in block  265  and returns to block  250  where the data manager  140  assigns the data to the alternate device. Returning then to block  260 , the resource manager  150  determines if the alternate MS device  182  is available. If it is available, the process advances to block  270 , and if it not available, the selection process in steps  250 ,  260 ,  265  and back to  250  repeat until an available device is found. 
     In block  270 , if MS device  182  is available to transfer data, the data manger  140 , buffer manager  130 , and resource manger  150  move the data from write buffer  122  via path  126  through the resource manager to path  152 , and onto MS device  182 . The data manager  140  also updates the BID-MSA translation table  170  (block  270 ). This update effectively frees the originally assigned data sectors of MS device  181 , as the translation table  170  would then indicate that the host some other host BID can be or is assigned to that location. 
     The data transfers in the foregoing example are simultaneously reading data from MS device  181  and writing data to MS device  182 . Although previously the BID may have been written on MS device  181 , it now resides on MS device  182 . 
     The embodiment of the invention illustrated in  FIGS. 1-2  also provide the ability to interrupt writes to a MS device if that MS device is needed for reading, and continuing the writes on another MS device that is available to take the data, thereby maintaining a full duplex mode of operation. In this embodiment, a write operation that is in progress to an MS device can be interrupted and a read operation started. The interrupted write operation may then be continued on another MS device from where it left off. In another embodiment, the write operation may be aborted and started from the beginning on another MS device. In a further embodiment, a duplicate command may be issued to another MS device that is available to take write data. 
     In  FIG. 2 , the path  280  from block  270  to block  260  illustrates an embodiment for interrupting a write process on an MS device and continuing on another MS device. During the movement of data in block  270 , the resource manager  150  may determine that the data movement to the selected MS device should be interrupted and continued on another device. By taking path  280 , a selection process will again take place. In some embodiments, selection process may occur on a periodic basis during the data movement, such as every block, upon a multiple count of blocks, or upon a convenient point for interruption. By following this process, the write operation can be interrupted and continued repeatedly on different MS devices, thereby maintaining high performance write throughput without sacrificing read performance. 
     In the embodiment of the invention illustrated in  FIGS. 1-2 , there is no fixed association of the host assigned BID and the MSA. The host may provide a BID that is comprised of 24 bits of address, and the bridge may allocate them in a larger space, for example MSA comprising 28 bits. This provides an advantageous opportunity to write BID data into any device that is available to transfer data, as illustrated in  FIG. 2 . 
     In another embodiment, the host may provide a BID that is comprised of 32 bits and the bridge may allocate them into an MSA comprising, for example, 28 bits. As long as the host does not exceed the capacity of the bridge and its MS devices, the data can be reliably retrieved. This provides an advantage for a host to allocate addresses independently of the limitation of the MS devices addressing capability, and expansion of the storage added only when needed, and independently of the BID range. 
     Although the foregoing has been described in terms of certain embodiments, other embodiments will be apparent to those of ordinary skill in the art from the disclosure herein. For example, in an alternative embodiment, operations may be performed concurrently, rather than sequentially, thereby improving performance. In another embodiment, data transfers may be performed in a hardware implementation and executed automatically without processor involvement. In some embodiments, the storage devices may be separate devices, or logical units of a single device. Alternatives to embody the invention in combinations of hardware and/or software running on a processor, or as a hardware implementation that is reconfigurable to operate in multiple modes would be design choices apparent to those of ordinary skill in the art. As a consequence, the system and method of the present invention may be embodied as software which provides such programming, such as a set of instructions and/or metadata embodied within a computer readable medium. The described embodiments have been presented by way of example only and are not intended to limit the scope of the disclosure. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms without departing from the spirit thereof. Thus, the invention is not limited by any preferred embodiments, but is defined by reference to the appended claims.