Abstract:
The present invention provides a precision current source wherein a reference current level is established by the inter-dependent operation of three current stages. The first stage provides first and second current paths and functions to mirror the current level through the first and second current paths. A second stage, coupled to the first and second current paths, defines a first current/voltage relationship at respective points in the first and second current paths. A third stage, also coupled to the first and second current paths, defines a second current/voltage relationship again at the respective points in the first and second current paths. In accordance with the present invention, the first and second current/voltage relationships are chosen to be mutually solvable for a discrete, non-zero pairing of voltage and current levels, thereby establishing a reference current level at the defined current set point.

Description:
FIELD OF INVENTION 
     The present invention is generally related to precision current sources, sinks, amplifiers, mirrors and other similar analog circuits that operate to provide a precise current reference. In particular, the present invention is related to a precision current source of monolithic construction that employs a resistorless design to achieve precision operation independent of fabrication process and operating temperature variations within a wide range of source voltages, including voltages below six volts. 
     BACKGROUND OF THE INVENTION 
     The class of analog circuits conventionally referred to as current sources typically includes current sources, sinks and current mirror amplifiers. Current sources are most commonly used to provide a reference current flow that serves as the basis for current driving other analog circuits. 
     In a simple current source of conventional design, a resistor is used to set the reference current level through one leg of a current mirror configured pair of transistors. While the appeal of such a simple circuit is obvious, and indeed, the circuit is more than adequate as a current source in many applications, the presence of the resistor essentially precludes its possible operation as a precision current source. Although the distinction between precision and ordinary current source designs is rather empirical, a precision current source is generally regarded as one whose reference current changes by less the 5000 parts per million (ppm) per degree centigrade over its specified operating temperature range. Current sources utilizing resistors typically fail to qualify as precision current sources due to the substantially temperature dependent value of their resistors. The value of a P-type resistor fabricated in a monolithic substrate will often vary by one or more percent per degree centigrade. 
     A somewhat related drawback to utilizing resistor-based current source designs, particularly in monolithically fabricated analog circuits, is the wide variance in resistive values realized as a result of normal fabrication process variation. Often there is a desire to be able to produce analog circuits of common design with closely matched operating characteristics. Expected, but difficult to eliminate, parameter fluctuations between processing runs of a monolithic analog circuit typically show up as significant variations in the value of the resistors formed. Consequently, the reference current-levels between circuits of identical design or both will vary unpredictably when separately fabricated in different processing runs or on different substrates, or both. 
     An alternative to current sources employing resistors is achieved with current source designs utilizing a series connected field effect transistor (FET) and a Zener diode voltage reference. The FET is placed in the primary leg of a current mirror and the Zener diode placed so as to be reversed biased in the second leg of the current leg. The gate of the FET is coupled to the base of the Zener diode. Consequently, the break-over voltage threshold of the Zener diode and the particular selected gate/source voltage-to-channel current relationship of the FET functions to constrain the level of current flow through the primary current mirror leg. 
     Zener diode design current sources have the advantage of not employing a true resistor. The temperature dependent characteristics of the resistively operated FET are such that precision operation of the current source is readily obtainable. However, the break-over voltage of the Zener diode is itself fairly temperature sensitive and highly dependent on fabrication parameters. Further, the required usage of a Zener diode alone places a substantial practical limitation on the usage of Zener diode type current sources in circuits of monolithic implementation. Zener diodes are difficult to fabricate with break-over voltages of less than 6.2 volts on a monolithic substrate in common with other active devices due to the very high impurity doping densities required. Consequently, regulated operation of the current source is generally not possible at source voltages of less than about 6 volts. 
     SUMMARY OF THE INVENTION 
     Therefore, a purpose of the present invention is to provide a precision current source that is operable over a wide range of supply voltages including voltages below 6 volts. 
     The present invention provides a precision current source wherein a reference current level is established by the inter-dependent operation of three current stages. The first stage provides first and second current paths and functions to proportionally mirror a current level through the first and second current paths. A second stage, coupled to the first and second current paths, defines a first current/voltage relationship at respective points in the first and second current paths. A third stage, also coupled to the first and second current paths, defines a second current/voltage relationship again at the respective points in the first and second current paths. In accordance with the present invention, the first and second current/voltage relationships are chosen to be mutually solvable for a discrete, non-zero pairing of voltage and current levels, thereby establishing a reference current level at the mutual relationship defined current set-point. 
     Thus, an advantage of the present invention is that it provides a current source design that is resistorless and without reliance on the use of a Zener diode. Consequently, the current source of the present invention readily achieves precision operating characteristics extending uniformly over a operating source potential difference range of approximately 2.5 to over 20 volts. 
     Another advantage of the present invention is that the current set point is generally insensitive to process variations between monolithic fabrication manufacturing runs or as a result of fabrication on separate substrates. The current set-point is a product of the relative active device parameters of a fabricated monolithic circuit embodying the present invention rather than any absolute fabricated value, such as that of a resistor or the break-over threshold voltage or a Zener diode. 
     A further advantage of the present invention is that the current source may be readily fabricated on a monolithic substrate in conjunction with the simultaneous fabrication of other active analog circuits or circuit components including complimentary metal oxide semiconductor (CMOS) FETs. 
     A still further advantage of the present invention is that it possesses a simple design that introduces no significant fabrication or usage complexities into the design of a monolithic analog device by virtue of its presence. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other attendant advantages of the present invention will become appreciated as the same becomes better understood by reference to the following detailed description of the invention when considered in conjunction with the accompanying drawings, wherein like reference numerals designate like parts throughout the figures thereof, and wherein: 
     FIG. 1 is a circuit schematic of a preferred precision current source of the present invention; 
     FIG. 2 is a graphic illustration of the paired current/voltage relationships utilized to establish a current set point in accordance with the present invention; 
     FIG. 3 is a circuit schematic of a precision current source of the present invention including bootstrap and high source voltage limiting circuit additions; and 
     FIG. 4 is a cross-sectional view of the preferred fabrication detail of the bipolar transistor stage of a preferred embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIG. 1, a precision current source, generally indicated by the reference numeral 10 and representing a preferred embodiment of the present invention, is shown. The current source 10, as shown, is capable of operating between +V and -V source voltages applied at terminals 18, 20 with a potential difference in the range about 2.5 to 20 volts. The current source 10 establishes two current paths between the source voltage terminals 18, 20. These two paths are generally indicated by the arrows I 1  and I 2 . In this preferred embodiment of the present invention, the current source 10 includes a current mirror stage 12, a source follower stage 14 and an emitter follower stage 16 and any number of reference current driver (as shown, current-sink configured) transistors 44, 48. The current mirror stage 12 includes a pair of N-channel FETs 22, 24 whose source terminals are commonly connected to the -V source terminal 20. The gate terminals of the transistors 22, 24 are coupled in common to the drain terminal of the transistor 24. The width (W) and length (L) dimensions of the channel regions of the transistors 22, 24 are preferably chosen to be the same to minimize the impact of any sizing mismatch on precision operation. Alternately, the ratio of the transistor dimensions may be varied from a value of one by a scaling factor &#34;γ&#34;. The gate to source voltage potential, V gs , of the transistor 24 directly depends on the magnitude of the current flow I 2 . The gate voltage thus applied to transistor 22 forces the magnitude of the current I 1  through transistor 22 such that I 1  =γI 2 . 
     The source follower stage 14 and emitter follower stage 16 operate inter-dependently to establish a current set-point for the parallel currents I 1  and I 2 . The source follower stage 14 includes a P-channel FET 30 whose drain terminal 28 is connected to the drain terminal of current mirror transistor 22 and a second P-channel FET 32 whose drain terminal is connected to the drain and base terminals 26 of the current mirror transistor 24. The gate contacts of the transistors 30, 32 are commonly connected to the drain terminal 28 of the transistor 30 to complete the source follower stage 14. In the preferred embodiment of the present invention, the active channel region width-to-length ratio of transistor 32 differs from that of transistor 30 by a factor of &#34;1/n&#34;, where &#34;n&#34; is a positive number greater than γ. Since the current relationship I 1  =γI 2  is established by the current mirror stage 12, the difference in width-to-length ratios of the transistors 30, 32 is reflected in a difference in the gate to source voltages of the transistors 30, 32 at their source terminals 34, 36. That is, the difference in current densities forced by the fixed relation I 1  =γI 2  and the difference in channel dimensions forces a proportional difference in the gate-to-source voltages of the transistors 34, 36. The inter-dependence of the ratio of width-to-length, the currents I 1  and I 2 , and the gate-to-source voltages of the transistors 20, 32 defines the source follower stage 14 voltage/current relationship. 
     The emitter follower stage 16 includes 2 bipolar NPN transistors 38, 40 diode connected to the +V source terminal 18. The emitters of the transistors 38, 40 are respectively connected to the source terminals 34, 36 of the source follower stage 14 transistors 30, 32. In accordance with the present invention, the emitter area of the transistor 40 is a factor &#34;m&#34; greater than that of the transistor 38, where &#34;m&#34; is again a positive value greater than one. Given again that the magnitude of the currents I 1  and I 2  are set by the current mirror stage 12, the factor &#34;m&#34; difference in emitter area, and therefore the current density through the emitters, is reflected by the transistors 38, 40 as a difference in the base-to-emitter voltage between the two transistors 38, 40. The inter-dependence of the active area scaling factor &#34;m&#34;, the currents I 1  and I 2 , and the base-to-emitter voltages of the transistors 38, 40 defines the emitter follower stage 16 voltage/current relationship. 
     Referring now to FIG. 2, the first quadrant current/voltage (IV) relationships defined by ideal FET 32 and bipolar 40 transistors of the source follower and emitter follower stages 14, 16 are shown. The fundamental difference in the current/voltage relationships shown arises from the fact the source follower stage 14 utilizes a FET device while the emitter follower stage 16 utilizes a bipolar device. In accordance with the present invention, the selection of the scaling factors &#34;γ&#34;, &#34;1/n&#34; and &#34;m&#34; will define a discrete non-zero value of the current I 2  where the ΔV be  of the emitter follower stage 16 equals the ΔV gs  of the source follower stage 14. That is, though the current mirror stage 12 forces I 1  =γI 2 , it is the relative current/voltage relationships of the transistors of the source follower and emitter follower stages 14, 16 that establish the magnitude of the currents I 1 , I 2  based on the values of &#34;m&#34; and &#34;1/n&#34;. Additionally, the fact that the temperature coefficients of the P-channel FETs and NPN bipolar transistors are of complementary polarity inherently tends to minimize changes in the current set-point due to temperature induced variations in the current density verses gate-to-source and base-to-emitter voltage drop characteristics of the transistors. 
     In greater detail, the loop equation for the loop defined by transistors 30, 32, 40 and 38 of FIG. 1 (for γ=1) is given by Equation 1: ##EQU1## where the V be1  and V be2  are the base to emitter voltages of transistors 38 and 40, V Tp1  and V Tp2  are the threshold voltages of the P-channel transistors 30 and 32, &#34;I&#34; is the magnitude of the currents I 1  =I 2 , and β=μC ox  is the gain factor of the FET transistors 30 and 32. ##EQU2## or more simply: 
     
         -ΔV.sub.Tp -ΔV.sub.be +ΔV.sub.gs =0      Eq. 3 
    
     where 
     ΔV be  =(V be1  -V be2 ), 
     ΔV Tp  =(V Tp1  -V Tp2 ), and 
     ΔV gs  =(V gs32  -V gs30 ). 
     The value of ΔV be  can be determined from the standard bipolar transistor current/voltage relationship given by Equation 4: ##EQU3## where I s  the saturation current of the bipolar transistor. Solving for the base to emitter voltage, V be , yields Equation 5: 
     
         V.sub.be =(kT/q)Ln(I/I.sub.s)                              Eq. 5 
    
     Therefore, the difference in the base to emitter voltage of the bipolar transistor 38 with respect to that of the bipolar transistor 40 is given by Equations 6 and 7: ##EQU4## 
     Substituting ΔV be  into Equation 2 yields Equation 8: ##EQU5## where the scaling values &#34;n&#34; and &#34;m&#34; are both greater than one. Solving Equation 8 for current ultimately yields Equation 11: ##EQU6## Without the assumption that γ=1, Equation 11 becomes: ##EQU7## 
     As can be seen from Equations 11 and 12, any pairing of the values of &#34;n&#34; and &#34;m&#34; (&#34;m&#34; greater than 1; &#34;n&#34; greater than &#34;γ&#34;) for a value &#34;γ&#34; will correspond to a discrete value of the current I. The values of &#34;γ&#34;, &#34;m&#34; and &#34;n&#34; can therefore be chosen to define a desired current set point for the current sink 10. 
     Referring again to the graph of FIG. 2, and considering that the device current/voltage relationships for the bipolar and FET transistors 40, 32 may not be ideal, a second current set point will likely occur at or near a current value of zero. The value of such a near-zero current set point will also be dependent on the paired values of &#34;m&#34; and &#34;n&#34; and the value of &#34;γ&#34;. Operation of the current source 10 at such an undesired current set point may be avoided by appropriately manufacturing or otherwise biasing the transistors 30, 32, 38, 40 such that this undesired current set point occurs in the second, third or fourth quadrants of the mutual current/voltage relationships defined by the transistors 30, 32, 38, 40. 
     Referring now to FIG. 3, an alternate embodiment of the present invention, modified to ensure proper current set point operation and a higher degree of precision operation at high source voltage potential differences, is shown. The current source, generally indicated by the reference numeral 52, includes a power-on boot-strap circuit, generally indicated by the reference numeral 54. The boot-strap circuit 54 includes a FET 60 whose drain gate and source are connected to the +V source terminal 18, through a resistor 64 to the +V source terminal 18 and to the commonly connected gate/drain of the current source transistor 24, respectively. The drain terminal 50 of the current sink configured transistor 48 is also connected to the gate of the FET 60. 
     In operation, the boot-strap circuit 54 insures that a non-zero current is passed by the transistor 24 beginning with the application of the +V source potential to the current source 52. A zero-reference current implies that the current sink configured transistor 48 will be off allowing the FET 60 to be turned on as a consequence of the resistive pull up of its gate to the +V source potential. The current passed through the FET 60 is forced through transistor 24. Consequently, the reference current through the current mirror stage 12, and therefore the current source 52, will quickly snap to the current value required for the ΔV be  of transistors 38, 40 to match the ΔV gs  of transistors 30, 32. The value of the resistor 64 is chosen such that the reference current drawn by the current sink transistor 48 is sufficient to completely turn off FET 60. 
     The supplementary circuitry generally indicated by the reference numerals 56, 58 is utilized to minimize loss of precision in the operation of the current sink 52 at high source voltage potential differences due to a channel length modulation effect in transistors 22 and 32. Briefly considering again the current source 10 of FIG. 1, the drain voltage potential of transistor 22 will increase as the source voltage potential is increased. This results in from the increase in current through transistor 22 its finite output impedance. The transistor 24 is not significantly affected due to its common drain to gate connection. Therefore, there will be an increasing mismatch in the current I 1  and I 2  through the transistors 22, 24 with increases in the source voltage potential difference. 
     The addition of a transistor 76 serially connected between transistors 30 and 32 clamps the voltage potential at the drain of transistor 22 at a maximum value controlled by the break-over voltage of a Zener diode 72 connected between the gate terminal 70 of the transistor 76 and the -V source voltage potential 20. In the preferred embodiment of the current source 52, the current through the Zener diode 72 is precisely regulated by reflecting the reference current of the current source 52 through a current mirror formed by transistor 66, 68 as established by the current sink configured transistor 74. That is, given that the current sink transistor 74 is generally identical to the current mirror transistors 22, 24, the current sink configured transistor 74 will draw current equal to the reference current through the first leg of the current mirror formed by the transistor 66, 68. A mirrored current equal to the reference current is therefore passed through the transistor 68 to the gate of the clamping transistor 76 and through the Zener diode 72. 
     In operation, the voltage potential at the gate 70 of the clamping transistor 76 will rise with increasing source voltage potential until the Zener break-over voltage is reached. Thereafter, the gate voltage of the clamp transistor 76 and the drain voltage of the transistor 22 are clamped at the values of V z  and V z  -V gs , respectively. In the preferred embodiment of the current source 52, the break-over voltage of the Zener diode 72 is 6.2 volts. Lower Zener break-over voltages are not generally needed since the occurrence of channel width modulation in transistor 22 is negligible for source to drain voltage potentials of less than 6.2 volts -V gs  of transistor 76. 
     The clamp circuit 50 performs essentially the same function as the clamp circuit 56. However, the clamping function is performed with respect to the drain to source voltage, V DS , of the transistor 32. A clamping transistor 78 is provided in series between the transistors 24 and 32. The gate of the clamp transistor 78 is connected through a Zener diode 78 to the source voltage potential and to the drain of a current sink configured transistor 44. Assuming that the current sink configured transistor 44 is essentially identical to the current source mirror transistors 22, 24, the current sink configured transistor 44 will try to sink a current equivalent to the reference current serially through the Zener diode 82. For all source potential voltages less than about the break-over voltage of the Zener diode 82, the clamp transistor 78 will remain on (i.e., conductive). As the source voltage increases further, Zener diode 82 will conduct a current equal to the reference current and the gate voltage potential of the clamp transistor 78 will rise to the +V source potential less the break-over voltage V z  of the Zener diode 82. Therefore, the drain voltage potential of the transistor 32 is clamped at a value of +V-V z  plus the V gs  of the clamp transistor 78. In the preferred embodiment of the current source 52, the break-over voltage V z  of the Zener diode 82 is 6.2 volts. Thus, the change in current through the transistor 32 as a consequence of channel length modulation with increasing source voltages is limited to a negligible value. 
     The insensitivity of the present invention to fabrication related variations in the development of the reference current &#34;I&#34; can be readily demonstrated by considering the impact on the current &#34;I&#34; described by Equation 11 due to a change in the parameters of significance. Equations 13-16 relate variance in the current &#34;I&#34; (assuming &#34;γ&#34;=1) to variances in the P-channel FET channel scaling factor &#34;n&#34;, the voltage threshold of the P-channel FETs, the voltage threshold of the N-channel FETs, the N-channel width-to-length ratio, and the bipolar transistor active emitter area scaling factor &#34;m&#34;. ##EQU8## 
     Equations 13 and 15 indicate that large values are preferred for the scaling factors &#34;n&#34;, and &#34;m&#34;. Equations 14 and 15 illustrate that the present invention is relatively insensitive to small FET threshold shifts. Finally, Equation 16 indicates that the present invention is also fairly insensitive to mismatch of the bipolar transistors. However, mismatch in the width-to-length ratios of the current mirror transistors will be amplified as a consequence of the source and emitter follower stages operating as current amplifiers. Therefore, it is preferable in the present invention to choose the width-to-length ratios of the current mirror transistors such that I 1  equals I 2 . 
     The change in the current I with respect to temperature variations can also be determined from Equation 11. Taking the derivative of the current I with respect to temperature yields: ##EQU9## 
     Therefore, the temperature coefficient of the present invention can be stated as Equation 20: 
     
         T.sub.C =(2/T)+(1/β)(dβ/dT)                      Eq. 20 
    
     EXAMPLE 
     Circuits embodying the present invention has been fabricated and tested. First and second identical arrays of the circuit were fabricated on separate substrates, though processed in the same fabrication run. The circuits fabricated are substantially the same as the embodiment of the present invention shown in FIG. 3. The circuit parameters used are as follows (dimensions are in micrometers): 
     Scaling Factors: 
     &#34;m&#34;=100 
     &#34;n&#34;=2 
     &#34;γ&#34;=1 
     Dimensions: 
     Q 1  (W/L) n  : (60/15) 
     Q 2  (W/L) n  : (60/15) 
     Q 3  (W/L) p  : (380/30) 
     Q 4  (W/L) p  : (190/30) 
     Worst case parameter value estimates: 
     (Δm/m): 1% 
     (Δn/n): 1% 
     Δ(V TP1  -V TP2 ): 5 mV p1 (V TP1  -V TP2 ): 25 mV 
     ΔV TN  : 5 mV 
     V gs  -V T  : 0.4 V 
     Δ(W/L) n  /(W/L) n  : 1% 
     (∂β/β: -27% (25° to 85° C.) 
     Computed errors: 
     
         ______________________________________ Error source            ##STR1##                     Eq. #______________________________________ ##STR2##        3.4%     13ΔV.sub.TP 6.9%     14ΔV.sub.TN 10.0%    15 ##STR3##        0.43%    16______________________________________ 
    
     Computed operating current set-point: ##EQU10## Computed Temperature Coefficient (T=25° to 85° C.): 
     
         Tc=2211ppm/°C.                                      Eq. 20 
    
     The difference between the mean operating set-point current values measured for circuits fabricated on the two substrates was measured to be about 1.3% typical. The temperature coefficient over an operating temperature range of 25° to 125° C. was measured to be approximately 1800 ppm/°C. 
     Thus, a precision resistorless current source relying on the mutual inter-dependence of two differing voltage/current relationships represented as two stages of the current source and a third stage current mirror that together establish a precise current set point substantially independent of a supply voltage difference that can vary from approximately 2.5 volts to above 20 volts has been described. 
     The foregoing disclosure and discussion of the present invention provides a broad teaching of the principles of the present invention such that many modifications and variations of the present invention will be readily apparent to persons of average skill in the art. One such modification is the substitution of PNP for NPN bipolar transistors, P-channel for N-channel transistors and N-channel for P-channel transistors such that the present invention, operating from reversed polarity source potentials, operates in a current source mode rather than as a current sink. It is therefore to be understood that, within the scope of the appended claims, the invention may be practiced otherwise than as specifically described.