Abstract:
A step-down switching voltage regulator may operate in PFM mode based on peak current sense without requiring an external diode. The regulator may comprise a PMOS transistor and an NMOS transistor whose drains are coupled to a common output node and whose sources are coupled to high and low supply voltages, respectively, configured to develop a current in an inductor and generate an output voltage. A control circuit, coupled to the respective gates of the PMOS transistor and the NMOS transistor, may sense the current in the inductor (I L ), sense an attenuated version of the output voltage (VFB), and sense the polarity of the voltage (VX) developed at the common output node. The control circuit may turn on the PMOS transistor when the VFB falls below a reference voltage and VX remains positive with respect to the low supply voltage, and may turn off the PMOS transistor when I L  reaches a specified value or when VFB exceeds the reference voltage. The control circuit may also turn on the NMOS transistor after the PMOS transistor is turned off and VX becomes negative with respect to the low supply voltage, and may turn off the NMOS transistor when VX becomes positive with respect to the low supply voltage.

Description:
[0001]     This application claims benefit of priority of U.S. provisional application Ser. No. 60/595,236 titled “Pulse-Frequency Mode DC-DC Converter Circuit”, filed Jun. 17, 2005. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     This invention relates to power converters in computer systems and digital systems, and more particularly to designing a DC-to-DC voltage converter.  
         [0004]     2. Description of the Related Art  
         [0005]     DC-to-DC conversion is often performed by having switching power regulators, or step-down regulators, converting a higher voltage (e.g. 12V) to a lower value as required by one or more load devices. A common architecture features distribution of the higher voltage to multiple power regulators, each producing a different (or possibly the same) voltage to one or more loads. Switching power regulators often use two or more power transistors to convert energy at one voltage to another voltage. One common example of such a power regulator, commonly called a “Buck regulator”, implemented with MOS devices is shown in  FIG. 1 . Buck regulator  100  may be configured to operate in the PWM mode, switching a P-channel device  108  and an N-channel device  110  in order to produce a square-wave at their common node LX. The produced square-wave can be smoothed out using an LC circuit comprising inductor  112  and capacitor  114  to produce the desired voltage, Vout. A control loop, comprised of an error amplifier  116  and a Control Logic block  102  can be configured to control the duty-cycle of the output square-wave, thereby controlling switching P-channel device  108  and N-channel device  110 , and hence the resulting value of Vout. In general, transistors  108  and  110  are controlled such that they do not conduct current at the same time. Typically, when transistor  108  is turned on (Vg_P is logic 0), transistor  110  is turned off (Vg_N is logic 0), and when transistor  108  is turned off (Vg_P is logic 1), transistor  100  is turned on (Vg_N is logic 1). I L  represents the load current flowing in inductor  112 .  
         [0006]     In addition to operating in PWM mode, Buck regulator  100 , and other regulators, may also be configured to operate in PFM (pulse-frequency mode—also known as skip mode). One example of a synchronous buck regulator that can operate in both modes is the Micrel MIC2177.  FIG. 2  shows a simplified functional diagram of the MIC2177 configured to operate in PFM. During PFM operation of regulator circuit  200  the output P-channel device  120  is turned on at a frequency and duty cycle that is a function of VIN, VOUT, and the value L 1  of inductor  122 . While in PFM, the N-channel device  121  coupled to P-channel device  120  is kept turned off to optimize efficiency by reducing gate charge dissipation. VOUT is regulated by skipping switching cycles that turn on P-channel device  120 . Comparator  126  regulates VOUT by controlling when regulator circuit  200  skips cycles. It compares the voltage at node FB (VFB) to the reference voltage (VREF) and has 10 mV of hysteresis to prevent oscillations in the control loop. When VFB is less than VREF−5 mV, the output of comparator  126  is logic 1, allowing P-channel device  120  to turn on. Conversely, when VFB is greater than VREF+5 mV, P-channel device  120  is turned off. Although regulator circuit  200  operates in PFM, it requires external “catch” diode  124  for its operation, which increases the cost of building a regulator using regulator circuit  200 .  
         [0007]     Many other problems and disadvantages of the prior art will become apparent to one skilled in the art after comparing such prior art with the present invention as described herein.  
       SUMMARY OF THE INVENTION  
       [0008]     In one set of embodiments, a switching power regulator for performing DC-to-DC (DC-DC) conversion may operate in pulse-frequency mode (PFM) based on peak current sense to regulate the load current with a variable frequency to achieve high efficiency at wide load variation without requiring an external diode component.  
         [0009]     A PFM DC-DC voltage regulator may include an inductor and a load capacitor both coupled to a node configured as the regulator voltage output V out . A voltage divider circuit comprising two resistors may be configured to provide an attenuated, or divided down, version of V out  at a second node (FB). The regulator may include two power transistors—a PMOS device and an NMOS device whose channels (drain terminals) may be coupled in series at a node (LX) between a supply voltage AVDD and a signal reference voltage AVSS—, an inverter configured to drive the gate of the PMOS device, an inverter configured to drive the gate of the NMOS device, and control circuitry for controlling the PMOS and NMOS devices. The control circuitry may include a zero-crossing comparator, a skip-mode comparator, a peak-current comparator, and additional logic circuitry comprising a one-shot pulse generator, a delay element, and respective SR latches for controlling the gate of each corresponding transistor.  
         [0010]     In one set of embodiments, the skip-mode comparator may sense V out  and control the switching of the output power transistors to ramp the output voltage between a specified value V out , ±5%. If the value of V out  falls below the ‘high’ threshold of the skip-mode comparator, the PMOS transistor may be turned on. The PMOS transistor may remain turned on until V out  reaches the ‘high’ threshold of the skip-mode comparator or until the peak load (or inductor) current exceeds a specified current level set for PFM. Once the PMOS transistor is turned off, an SR latch whose output is configured to partially control the gate of the NMOS device may be set until the inductor current ramps to zero. The zero-crossing comparator may be configured to sense what the polarity of the voltage at node LX is with respect to AVSS. When the voltage at node LX switches from a negative value to a positive value with respect to AVSS, the NMOS transistor may be turned off to prevent simultaneous reverse current flow in the inductor. When the value of V out  falls below the ‘high’ threshold of the skip-mode comparator, the PMOS transistor may be turned on again, and the entire switching cycle (PMOS/NMOS) may be repeated—to store charge on the capacitor—until V out  reaches the desired level corresponding to the ‘high’ threshold of the skip-mode comparator. At that point the NMOS device may be briefly turned on to ramp the current in the inductor to zero, following which the PMOS transistor and the NMOS transistor may both be turned off to enter an extremely low power mode.  
         [0011]     Should the load current increase when, as a result of operating in PFM, V out  falls below the ‘low’ threshold of the skip mode comparator, the power regulator may automatically transition into fixed-frequency PWM mode. During PFM operation, the PMOS transistor may be turned on at a frequency and duty cycle (for PWM) that is a function of the power regulator input voltage, the power regulator output voltage, and the value of the inductor, and the NMOS transistor may be kept off to optimize efficiency by reducing gate charge dissipation. The output voltage of the power regulator may therefore be regulated by skipping switching cycles that turn on the PMOS transistor.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]     The foregoing, as well as other objects, features, and advantages of this invention may be more completely understood by reference to the following detailed description when read together with the accompanying drawings in which:  
         [0013]      FIG. 1  shows one embodiment of a PWM mode DC-to-DC converter circuit according to prior art;  
         [0014]      FIG. 2  is a simplified functional diagram of the Micrel MIC 2177  switching DC-to-DC power converter configured to operate in PFM according to prior art;  
         [0015]      FIG. 3  is a timing diagram of voltage signals Vg_P, Vg_N, and Vx, and inductor current I L  observed during high current load operation of a DC-to-DC converter;  
         [0016]      FIG. 4  is a timing diagram of inductor current I L  observed during light current load operation of a DC-to-DC converter, with the inductor operating in a continuous conduction mode (CCM) by reversing the polarity of I L ;  
         [0017]      FIG. 5  is a timing diagram of inductor current IL observed during light current load operation of a DC-to-DC converter, with the inductor operating in a discontinuous conduction mode (DCM);  
         [0018]      FIG. 6  shows the inductor current I L  waveform during variable frequency pulse-frequency mode (PFM) operation;  
         [0019]      FIG. 7  shows the inductor current I L  waveform during maximum load/frequency PFM operation; and  
         [0020]      FIG. 8  is a circuit diagram of a PFM DC-to-DC voltage regulator configured according to one embodiment of the present invention. 
     
    
       [0021]     While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention as defined by the appended claims. Note, the headings are for organizational purposes only and are not meant to be used to limit or interpret the description or claims. Furthermore, note that the word “may” is used throughout this application in a permissive sense (i.e., having the potential to, being able to), not a mandatory sense (i.e., must).” 
       DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0022]     Referring again to  FIG. 1 , operation of a synchronous buck converter may be further examined.  FIG. 3  shows voltage waveforms Vg_P  202 , Vg_N  204 , and Vx  206  (voltage at node LX), as well as inductor current I L    208  and corresponding load current I Load  as observed during high current load operation of synchronous buck converter  100 . When Vg_P  202  is logic low, transistor  108  is turned on. When Vg_N is logic high, transistor  110  is turned on. The deadtime delay t dead  indicates the time period when both transistors are turned off. As shown in  FIG. 3 , the average inductor current (i.e. the average of I L ) is essentially equal to the DC load current provided by converter  100 , indicated in  FIG. 3  as I Load .  FIG. 4  shows a timing diagram of the inductor current (and correspondingly the DC load current) observed during light current load operation of converter  100 . As seen in  FIG. 4 , when I Load  is less than half the magnitude of the peak-to-peak ripple of current I L , the entire I L  waveform  208  may be shifted down, shown as I L  waveform  308  in  FIG. 4 . It should be noted that in an asynchronous buck converter, during light current load operation, inductor current I L  may go to zero due to the effects of a the rectifier diode that may be coupled across the load, resulting in inductor  112  operating in discontinuous conduction mode (DCM). In converter  100 , during light current load operation, inductor  112  may operate in a continuous conduction mode (CCM) by reversing the polarity of inductor current I L , as illustrated in I L  waveform  308  in  FIG. 4 .  
         [0023]     CCM operation at light current loads may be undesirable, as the reversal of the polarity of the inductor current I L  may contribute to conduction losses—because of the inductor current flowing from capacitor  114  to ground—without contributing to the output load current (I Load ). DCM in a synchronous regulator during low current load operation may be achieved by disabling N-channel device  110  at the zero-crossing point of the inductor current I L . The resulting inductor current I L  waveform  408  is shown in  FIG. 5 . As a result of N-channel device  110  being turned off at the zero-crossing point, inductor  112  does not conduct reverse current, hence I L    408  only flows in one direction. In other words, in DCM the inductor current I L  may remain positive. However, during low current load operation in DCM, the duty cycle of the inductor current I L  may be significantly lower than during CCM, which may affect the efficiency of power regulator  100 .  
         [0024]     In contrast to PWM mode, the PFM low power mode is based on the idea of reducing the switching frequency proportionally to the load current I Load . By making the switching frequency proportional to the load current, high efficiency may be maintained over a wide range of load currents.  FIG. 6  shows the PFM waveforms as relating, for example, to the operation of regulator circuit  200  shown in  FIG. 2 . Waveforms  500  and  502  indicate when P-channel device  120  and N-channel device  121  are turned on, respectively. Waveform  504  is the inductor current that may be conducted by inductor  122 . If t p  and t n  represent the on times for P-channel device  120  and N-channel device  121 , respectively, then:  
                 t   p     =       LI   peak         V     i   ⁢           ⁢   n       -     V   out           ,           ⁢   and           (   1   )                   t   n     =       LI   peak       V   out         ,           (   2   )             
 
 where L is the inductance of inductor  122 , V in  is the input voltage to regulator circuit  200  (referring to  FIG. 2 ), V out  is the output voltage of regulator circuit  200  (again, referring to  FIG. 2 ), and I peak  is the peak value of current I L  conducted by inductor  122 . Consequently, I Load  may be expressed as:  
                 I   Load     =       1   2     ⁢         I   peak     ⁡     (       t   p     +     t   n       )       ·     f   s           ,           (   3   )             
 
 where f s  is the switching frequency defined as:  
               f   s     =       1       t   p     +     t   n         .             (   4   )             
 
 Combining equations 1-4, the switching frequency may be written as:  
               f   s     =         2   ⁢     V   o     ⁢     I   Load         LI   peak   2       ⁢       (     1   -       V   o       V   i         )     .               (   5   )             
 
 As equation 5 indicates, the switching frequency is proportional to the load current. The output voltage ripple in PFM may therefore be expressed as:  
                   (     2   ⁢   Δ   ⁢           ⁢   V     )     ≈       1     2   ⁢   C       ⁢       I   peak     ⁡     (       t   p     +     t   n       )           =         LI   peak   2       2   ⁢   C       ·       V     i   ⁢           ⁢   n           V   out     ⁡     (       V   out     -     V     i   ⁢           ⁢   n         )             ,           (   6   )             
 
 indicating a higher voltage ripple than what may be observed in PWM mode. 
 
         [0025]     Turning now to  FIG. 7 , the PFM waveforms as relating, for example, to the operation of regulator circuit  200  during maximum load current/frequency operation are shown. Waveforms  600  and  602  indicate when P-channel device  120  and N-channel device  121  are turned on, respectively. Waveform  604  is the inductor current that may be conducted by inductor  122 . The maximum load current may be expressed as:  
                 I     Load_max   ,   PFM       =       1   2     ⁢     I   peak         ,           (   7   )             
 
 with the corresponding switching frequency:  
               f   s     =         2   ⁢     V   out         LI   peak       ⁢       (     1   -       V   out       V       i   ⁢           ⁢   n     ⁢                   )     .               (   8   )             
 
 The conduction losses in PMOS device  120 , NMOS device  121  and inductor  122  during PFM operation may be expressed as: 
 
 P   Cond     —     PFM   =R   on     —     p   i   p     —     RMS   2   +R   on     —     n   i   n     —     RMS   2   +R   L   I   L     —     RMS   2 ,   (9) 
 
 where R on     —     p  and R on     —     n  correspond to the on resistances of PMOS device  120  and NMOS device, respectively, i p     —     RMS  and i n     —     RMS  correspond to the RMS currents conducted by PMOS device  120  and NMOS device, respectively, R L  corresponds to the impedance of inductor  122 , and I L     —     RMS  corresponds to the RMS current conducted by inductor  122 . Equation 9 may be re-written in terms of V in , V out , and I peak :  
               P   Cond_PFM     =         LI   peak   3     3     ⁢       (         R   on_p         V   in     -     V   out         +       R   on_n       V   out       +         R   L     ⁢     V     i   ⁢           ⁢   n             (       V     i   ⁢           ⁢   n       -     V   out       )     ⁢     V   out           )     ·       f   s     .                 (   10   )             
 
 Combining equations 10 and 5, the conduction losses may be expressed as:  
                 P     Cond   ,   PFM       =       2   3     ⁢     I   Load     ⁢       I   peak     ⁡     [         R   on_p     ·       V   out       V     i   ⁢           ⁢   n           +       R   on_n     ⁡     (     1   -       V   out       V       i   ⁢           ⁢   n     ⁢                   )       +     R   L       ]           ,           (   11   )             
 
 indicating that the conduction losses during PFM operation may be directly proportional to the load current. 
 
         [0026]      FIG. 8  is a partial circuit diagram of a PFM DC-to-DC voltage regulator  800  configured according to one embodiment of the present invention. Regulator  800  may include an inductor  806  and a load capacitor  808  both coupled to node  860 , which may be configured as the output of regulator  800 , generating output voltage V out . A voltage divider circuit comprising resistors  810  and  812  may be configured to provide an attenuated, or divided down, version of V out  at node  842 . Regulator  800  may also include two power transistors, PMOS device  802  and NMOS device  804 , whose channels (drain terminals) may be coupled in series between supply voltage AVDD and signal reference voltage AVSS (which may be ground in one set of embodiments), inverter  862  configured to drive the gate of PMOS device  802 , inverter  864  configured to drive the gate of NMOS device  804 , and control circuitry for controlling PMOS device  802  and NMOS device  804 . The control circuitry for PMOS device  802  and NMOS device  804  may include comparator  818  (zero-crossing comparator), comparator  820  (skip-mode comparator), comparator  816  (I peak  comparator), and additional logic circuitry comprising one-shot pulse generator  826 , delay element  828 , and control latches  822  and  824 , as well as logic gates  832 ,  830 , and  834 . Alternate embodiments using transistor devices other than PMOS device  802  and NMOS device  804  are possible and are contemplated.  
         [0027]     According to one mode of operation of regulator  800 , comparator  820  may sense V out  (via node  842 ), and control the switching of output devices  802  and  804  to ramp the output voltage between specified value V out ±a specified margin, which may be 5% in one set of embodiments. If V out  falls below the “high” threshold of comparator  820 , PMOS device  802  may be turned on. PMOS device  802  may remain turned on until V out  reaches the “high” threshold of comparator  820  or until the peak current I peak  exceeds a specified current level set for PFM (I PFM ). In one set of embodiments, I PFM  may be set to equal I Load +I PK . Once PMOS device  802  is turned off, SR latch  824  may be set (turned on) until the inductor current (conducted by inductor  806 ) ramps to zero. Comparator  818  may be configured to sense the polarity of the voltage developed at node  866 , in effect detecting an NMOS zero-current condition. When the voltage at node  866  switches from a negative value to a positive value, NMOS device  804  may be turned off to prevent simultaneous reverse current flow in inductor  806 . When the value V out  falls below the “high” threshold of comparator  820 , PMOS device  802  may be turned on again, and the entire switching cycle (PMOS/NMOS) may be repeated—to store charge on capacitor  808 —until V out  reaches the desired “high” level corresponding to the “high” threshold of comparator  820 . At that point NMOS device  804  may be briefly turned on to ramp the current in inductor  806  to zero, following which PMOS device  802  and NMOS device  804  may both be turned off to enter an extremely low power mode.  
         [0028]     Should the load current increase when, as a result of operating in PFM, V out  falls below the “low” threshold of comparator  820 —about 50 mV below the nominal voltage in one set of embodiments—regulator  800  may automatically transition into fixed-frequency PWM mode. It should be noted that additional circuit elements may be required for the fixed-frequency PWM operating mode of regulator  800 , and that such additional components are not shown in  FIG. 8  in order to better highlight the PFM operation of regulator  800 . Such additional circuit components and their operation in the context of the PWM operating mode of power regulators is well known to those skilled in the art. As previously mentioned, during PFM operation PMOS device  802  may be turned on at a frequency and duty cycle (for PWM) that is a function of V in , V out , and the value of inductor  806 , and NMOS device  804  may be kept off to optimize efficiency by reducing gate charge dissipation. V out  may therefore be regulated by skipping switching cycles that turn on PMOS device  802 .  
         [0029]     The PFM operation of regulator  800  according to one embodiment will now be discussed in more detail. Beginning with an initial state in which PMOS device  802  and NMOS device  804  are turned off, the voltage at node  866 , which may be roughly equivalent to V out , will be greater than zero, resulting in output  846  of comparator  818  being asserted (that is, being logic high). Consequently, capacitor  808  may discharge, and V out  may drop down from its nominal value. The divided voltage at node  842  may fall below the value of reference voltage  848 , resulting in output  844  of comparator  820  being logic high. With outputs  844  and  846  both being logic high, the output of NAND gate  830  will be logic high, enabling one-shot pulse generator  826  to generate a trigger pulse at output  850 , which may reset output Q 1  of SR latch  822  to logic low, thereby turning on PMOS device  802  and causing current I L  in inductor  806  to increase linearly until it reaches a pre-set current limit (for example, I PFM  as previously shown, which may be 80 mA in one set of embodiments). Current-sense block  814 —coupled to node  866 —may operate to sense I L , and generate a corresponding voltage value at output  854 .  
         [0030]     When current I L  in inductor  806  increases and reaches the pre-set current limit, output  840  of comparator  816  may assert in response to output  854  of current-sense block  814 , setting output Q 1  of SR latch  822  to logic high, thereby turning off PMOS device  802 . There is a deadtime during which both PMOS device  802  and NMOS device  804  are turned off, forcing the body-diode of NMOS device  804  to turn on (forward-biased) and pick up current I L  from inductor  806 . Accordingly, the voltage at node  866  may swing below ground (−0.6V in one set of embodiments), resulting in output  846  of comparator  818  going to logic low, providing a logic low input to input S 2  of SR latch  824 . The inverted output of SR latch  822  may also be coupled to delay element  828 , which may operate to keep input S 2  of SR latch  824  at logic high for a specified additional delay period, such that input S 2  of SR latch  824  is still high for a brief period after the voltage at node  866  falls below ground, even though output Q 1  of SR latch  822  is now at logic high. The high S 2  input and low R 2  input of SR latch  824  may combine to set output Q 2  of SR latch  824  to logic high. With output Q 1  of SR latch  822  and output Q 2  of SR latch  824  both being logic high, NMOS device  804  may be turned on to ramp down inductor current I L  to zero. When I L  crosses zero, reversing its direction, the voltage at node  866  may switch from a negative value to a positive value, setting output  846  of comparator  818  to logic high, which in turn may reset output Q 2  of SR latch  824  to logic low. In addition, when the voltage at node  842  is still lower than reference voltage  848 , output signal  844  of comparator  820  will be at logic high, which, combined with input R 2  of SR latch  824  going to logic high, will result in the output of AND gate  830  triggering one-shot pulse generator  826 , thereby resetting output Q 1  of SR latch  822  to logic low. This may result in PMOS device  802  being turned on, beginning another switching cycle.  
         [0031]     When inductor current I L  reaches ground, comparator  818  may operate to turn off NMOS device  804 . There may be some noise present at ground as the comparator switches NMOS device  804  on and off. SR latch  824  may be used to control the gate of NMOS device  804  to turn NMOS device  804  off. As the voltage at node  856  goes to logic high to turn off PMOS device  802 , the output of delay element  828  may remain at logic high for a specified delay period before going to logic low. Once both inputs S 2  and R 2  of SR latch  824  at logic low, output Q 2  of SR latch  824  may still hold its current value, leaving NMOS device turned on. If the voltage at node  842  is higher than reference voltage  848 , (that is, capacitor  808  is fully charged), then PMOS reset  844  may be logic low, and when NMOS device  804  is turned off because input R 2  of SR latch  824  is logic high, the combination of PMOS reset  844  being logic low and input R 2  of SR latch  824  being logic high results in the input of one-shot pulse generator  826  remaining logic low and not resetting SR latch  822 , thereby not turning on PMOS device  802 . Therefore, when V out  is fully restored (that is, the voltage at node  842  is greater than reference voltage  848 ), PMOS device  802  and NMOS device  804  may both be turned off.  
         [0032]     In general, comparator  820  may regulate V out  by controlling when regulator  800  skips cycles, comparing the voltage at node  842  to reference voltage  848 , with built in hysteresis, which may be 20 mV in one set of embodiments, to prevent oscillation in the feedback control loop. When the voltage at node  842  is less than reference voltage  848  minus a preset value (10 mV in one set of embodiments), output  844  of comparator  820  (in essence, PMOS reset signal  844 ) may be at logic high, turning on PMOS device  802  as discussed above. Conversely, when the voltage at node  842  is greater than reference voltage  848 , PMOS device  802  may be turned off.  
         [0033]     The control of PMOS device  802  may be thus be summarized as follows. Through OR gate  832 , PMOS device  802  may be turned off if either or both of two conditions are met. The first condition is met when the current (I L ) sensed by current-sense block  814  reaches the I peak  limit, and the second condition is met when the voltage at node  842  exceeds the value of reference voltage  848 . Through AND gate  830 , PMOS device  802  may be turned on if both of two conditions are met. The first condition is met when the voltage at node  842  falls below the value of reference voltage  848 , and the second condition is met when the voltage at node  866  exceeds ground level.  
         [0034]     Although the embodiments above have been described in considerable detail, other versions are possible. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications. Note the section headings used herein are for organizational purposes only and are not meant to limit the description provided herein or the claims attached hereto.