Abstract:
An image processing method for processing an input image is provided. The image processing method includes: performing a plurality of first imaging processing operations on the input image to generate a first image; and performing a plurality of second imaging processing operations on the first image. Each of the first imaging processing operations is along a first direction, and the plurality of first imaging processing operations include a first scaling operation for increasing resolution. Each of the second imaging processing operations is along a second direction different from the first direction, and the plurality of second imaging processing operations include a second scaling operation for increasing resolution.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation application of and claims the priority benefit of U.S. application Ser. No. 14/035,966, filed on Sep. 25, 2013, now allowed, which is a continuation application of and claims the priority benefit of U.S. application Ser. No. 12/719,012, filed on Mar. 8, 2010. The prior application Ser. No. 12/719,012 claims the priority benefit of Taiwan application serial no. 98119588, filed on Jun. 11, 2009. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification. 
    
    
     BACKGROUND OF THE DISCLOSURE 
     1. Field of Disclosure 
     The disclosure relates to an image processing method. More particularly, the disclosure relates to an image processing method that can scale and sharpen images. 
     2. Description of Related Art 
     The advancements in the manufacturing process have made high resolution monitors become more and more popular. High resolution monitors can display more image details clearly. Taking a monitor compatible with the High Definition Multimedia Interface (HDMI) standard, the monitor can display images with a 1920×1080 resolution. Those images with the resolution of 1920×1080 are frequently referred to as High Definition (HD) images. 
     However, most TV programs can only provide images with a resolution of 320×240. Similarly, DVD programs can only provide images with a resolution of 720×480, which is referred to as Stand Definition (SD). When a monitor having a high resolution (e.g. HD) is used to display a TV program or a DVD program, the monitor has to enlarge the images of the program. Because the enlarged images will have relatively obscure object borders, observers will discern deteriorations in the quality of the enlarged images. Therefore, image sharpening is usually performed upon the enlarged images to enhance the sharpness of the enlarged images. 
     Please refer to  FIG. 1 , which is a block diagram of an image processing circuit  10  of the related art. The image processing circuit  10  is used to enlarge and sharpen an input image I IN  to generate a sharpened image I S . The image processing circuit  10  includes a scaling circuit  12  and a sharpness circuit  14 . The scaling circuit  12  enlarges the input image I IN  to generate an enlarged image I P . Then, the sharpness circuit  14  sharpens the enlarged image I P  to generate the sharpened image I S . 
     For simplicity of illustration, when this text indicates that an image has a resolution of U×V, it means that the horizontal resolution of the image is U pixels, and the vertical resolution of the image is V pixels. For example, assume that the resolution of the input image I IN  is 720×480. The horizontal resolution of the input image I IN  is 720 pixels, and the vertical resolution of the input image I IN  is 480 pixels. Please note that each of the aforementioned pixels can consist of either a single sub-pixel or a plurality of sub-pixels. Each of the sub-pixels represents a specific color, such as red, green, or blue. 
     Please refer to  FIG. 2 , which is a diagram illustrating the input image the enlarged image I P , and the sharpened image I S  of  FIG. 1 . Assume that the input image I IN  with the resolution of 720×480 is to be converted into the sharpened image I S  with the resolution of 1920×1080. The scaling circuit  12  first enlarges the input image I IN  to generate the enlarged image I P  with the resolution of 1920×1080. Next, the sharpness circuit  14  sharpens the enlarged image I P  to generate the sharpened image I S  with the resolution of 1920×1080. 
     When the resolution of the sharpened image I S  increases, to maintain the quality of the sharpened image I S , the sharpness circuit  14  must have more taps. However, if the sharpness circuit  14  has more taps, the line buffers  18  must also have larger storage capacities. For example, assume that (1) the input image I IN  with the resolution of 720×480 is to be converted into the sharpened image I S  with the resolution of 1920×1080; (2) the sharpness circuit  14  performs a 7-tap sharpening; (3) each pixel has three sub-pixels corresponding to colors red, green, and blue; and (4) each sub-pixel has 256 (i.e. 2 8 ) gray levels. To facilitate the 7-tap sharpening, the image processing circuit  10  should have at least 6 line buffers  18 , each of which should be capable of storing at least 5760 (i.e. 1920×3) bytes. 
     SUMMARY OF THE DISCLOSURE 
     Accordingly, the disclosure provides an image processing method for performing vertical scaling, vertical sharpening, horizontal scaling, and horizontal sharpening on an image in turn. The vertical sharpening of the method can be performed with more taps without requiring line buffers of longer data lengths. 
     The disclosure provides an image processing method for processing an input image. The image processing method includes: performing a plurality of first imaging processing operations on the input image to generate a first image; and performing a plurality of second imaging processing operations on the first image. Each of the first imaging processing operations is along a first direction, and the plurality of first imaging processing operations include a first scaling operation for increasing resolution along the first direction. Each of the second imaging processing operations is along a second direction different from the first direction, and the plurality of second imaging processing operations include a second scaling operation for increasing resolution along the second direction. 
     According to an embodiment of the disclosure, the plurality of first image processing operations further include a sharpening operation along the first direction after the first scaling operation. 
     According to an embodiment of the disclosure, the plurality of second image processing operations further include a sharpening operation along the second direction after the second scaling operation. 
     According to an embodiment of the disclosure, the plurality of first image processing operations further include a first sharpening operation along the first direction after the first scaling operation, and the plurality of second image processing operations further include a second sharpening operation along the second direction after the second scaling operation. 
     According to an embodiment of the disclosure, the first direction is a vertical direction, and the second direction is a horizontal direction. 
     According to an embodiment of the disclosure, the image processing method further includes: temporally storing the pixel values of one or more pixel rows of the enlarged image into one or more line-buffers after the first scaling operation is performed to generate an enlarged image accordingly. 
     According to an embodiment, the image scaling is divided into a vertical scaling and a horizontal scaling, and the image sharpening is divided into a vertical sharpening and a horizontal sharpening. The vertical sharpening is performed after the vertical scaling and before the horizontal scaling. Therefore, the image processing circuit of the disclosure can use one or more line buffers with a shorter data length to perform the vertical sharpening. The image processing circuit can perform the vertical sharpening with more taps without requiring line buffers of longer data lengths. 
     In order to the make the aforementioned and other objects, features and advantages of the disclosure comprehensible, embodiments accompanied with figures are described in detail below. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the disclosure as claimed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. 
         FIG. 1  is a block diagram of an image processing circuit of the related art. 
         FIG. 2  is a diagram illustrating the input image, the enlarged image, and the sharpened image shown in  FIG. 1 . 
         FIG. 3  is a block diagram of an image processing circuit according to an embodiment of the disclosure. 
         FIG. 4  is a diagram illustrating the images generated by the image processing circuit of  FIG. 3  while processing the input image. 
         FIG. 5  is a diagram illustrating how the first sharpness circuit of  FIG. 3  vertically sharpens the first enlarged image to generate the first sharpened image. 
         FIG. 6  is a diagram illustrating the status of the line buffers and the first sharpened image after the first sharpness circuit has finished calculating the pixel value of a pixel of the first sharpened image. 
         FIG. 7  is a diagram illustrating how the second sharpness circuit of  FIG. 3  horizontally sharpens the second enlarged image to generate the second sharpened image. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     The term “coupling/coupled” used in this specification (including claims) may refer to any direct or indirect connection means. For example, “a first device is coupled to a second device” should be interpreted as “the first device is directly connected to the second device” or “the first device is indirectly connected to the second device through other devices or connection means.” Moreover, wherever appropriate in the drawings and embodiments, elements/components/steps with the same reference numerals rethe same or similar parts. Elements/components/steps with the same reference numerals or names in different embodiments may be cross-referenced. 
     Please refer to  FIG. 3  and  FIG. 4 .  FIG. 3  is a block diagram of an image processing circuit  100  according to an embodiment of the disclosure.  FIG. 4  is a diagram illustrating the images generated by the image processing circuit  100  of  FIG. 3  while processing an input image I IN . The image processing circuit  100  processes the input image I IN  to generate an output image that is not only enlarged but also sharpened. The image processing circuit  100  includes a first scaling circuit  102 , a first sharpness circuit  104 , a second scaling circuit  106 , and second sharpness circuit  108 . The following example illustrates not only the image processing circuit  100  but also an embodiment of an image processing method of the disclosure. In the following example, it is assumed that the input image I IN  with a resolution of 720×480 is to be converted into a second sharpened image I S2  with a resolution of 1920×1080. Please note that these exemplary resolutions are not necessary limitations of the disclosure. For example, the image processing circuit  100  can also be used to convert an input image I IN  with a resolution of 320×240 into a second sharpened image I S2  with a resolution of 720×480 or 1920×1080. 
     The first scaling circuit  102  enlarges the input image I IN  to generate a first enlarged image I P1 . Specifically, the first scaling circuit  102  enlarges the input image I IN  along a first direction to generate the first enlarged image I P1 . In this embodiment, the first direction is the vertical direction. In other words, the first scaling circuit  102  vertically enlarges the input image I IN  to generate the first enlarged image I P1 , which has a vertical resolution larger than that of the input image I IN . In the example shown in  FIG. 4 , the input image I IN  has a resolution of 720×480. After the vertical scaling, the first enlarged image I P1  has a resolution of 720×1080. Specifically, the vertical resolution of the first enlarged image I P1  is larger than the vertical resolution of the input image I IN , the horizontal resolution of the first enlarged image I P1  is equal to the horizontal resolution of the input image I IN . 
     In this embodiment, the first scaling circuit  102  interpolates one or more than one row of pixels into each two adjacent rows of the input image I IN . Please note that interpolation is not a necessary limitation of the disclosure. Other image scaling method can also be used with the disclosure to enlarge the input image I IN  to generate the first enlarged image I P1 . 
     In this embodiment, the image processing circuit  100  further includes a buffer  101 . The buffer  101  is coupled to the first scaling circuit  102  and the first sharpness circuit  104 . The buffer  101  temporally stores the pixel values of a part of pixels on the first enlarged image I P1 . In this embodiment, the buffer  101  includes a plurality of line buffers  110   a - 110   f . The line buffers  110   a - 110   f  are coupled to the first scaling circuit  102 . The line buffers  110   a - 110   f  temporally stores the pixel values of a plurality of pixel rows of the first enlarged image I P1 . The first sharpness circuit  104  can fetch the temporally stored pixel values for subsequent image processing. In addition, in this embodiment, the data length of each of the line buffers  110   a - 110   f  is equal to the data volume of the pixel values of a pixel row of the first enlarged image I P1 . Since in this example the resolution of the first enlarged image I P1  is 720×480, there are 480 pixel rows in the first enlarged image I P1 , each of the pixel rows has 720 pixels. In the circumstances, the data length of each of the line buffers  110   a - 110   f  can be equal to the data volume of the pixel values of 720 pixels. Specifically, assume that each pixel has three colors, including red, green, and blue, and each of the colors has 256 (i.e. 2 8 ) gray levels. The data volume of the pixel values of each pixel will be 3 bytes. The data length of each of the line buffers  110   a - 110   f  can be 2160 (i.e. 720×3) bytes. Please note that the exemplary data lengths of the line buffers  110   a - 110   f  do not constitute a necessary limitation of the disclosure. 
     Please refer to  FIG. 3  and  FIG. 4 . The first sharpness circuit  104  is coupled to the line buffers  110   a - 110   f . The first sharpness circuit  104  performs a vertical sharpness procedure, which is also referred to as a first sharpness procedure, on the first enlarged image I P1  to generate a first sharpened image I S1 . The resolution of the first sharpened image I S1  is equal to the resolution of the first enlarged image I P1 . In the example shown in  FIG. 4 , because the resolution of the first enlarged image I P1  is 720×1080, the resolution of the first sharpened image I S1  is also 720×1080. In addition, the pixel values of each pixel of the first enlarged image I P1  will be temporally stored into the line buffers  110   a - 110   f  in turn. When vertically sharpening the first enlarged image I P1 , the first sharpness circuit  104  fetches the pixel values of the required pixels of the first enlarged image I P1  from the line buffers  110   a - 110   f  to calculate the pixel values of each pixel of the first sharpened image I S1 . 
     The second scaling circuit  106  is coupled to the first sharpness circuit  104 . In this embodiment, the second scaling circuit  106  enlarges the first sharpened image I S1  along a second direction to generate a second enlarged image I P2 . In this embodiment, the second direction is the horizontal direction, which is perpendicular to the aforementioned first direction. In other words, the second scaling circuit  106  horizontally enlarges the first sharpened image I S1  to generate the second enlarged image I P2 , the horizontal resolution of which is larger than the horizontal resolution of the first sharpened image I S1 . In the example shown in  FIG. 4 , the resolution of the first sharpened image I S1  is 720×1080, the resolution of the second enlarged image I P2  is 1920×1080. Specifically, the horizontal resolution of the second enlarged image I P2  is larger than the horizontal resolution of the first sharpened image I S1 , the vertical resolution of the second enlarged image I P2  is equal to the vertical resolution of the first sharpened image I S1 . 
     In this embodiment, the second scaling circuit  106  interpolates one or more than one pixel column into each two adjacent pixel columns of the first sharpened image I S1 . Please note that interpolation is not a necessary limitation of the disclosure. Other image scaling method can also be used with the disclosure to enlarge the first sharpened image I S1  to generate the second enlarged image I P2 . 
     The second sharpness circuit  108  is coupled to the second scaling circuit  106 . The second sharpness circuit  108  performs a horizontal sharpness procedure, which is also referred to as a second sharpness procedure, on the second enlarged image I P2  to generate the second sharpened image I S2 . The resolution of the second sharpened image I S2  is equal to the resolution of the second enlarged image I P2 . In the example shown in  FIG. 4 , because the resolution of the second enlarged image I P2  is 1920×1080, the resolution of the second sharpened image I S2  is also 1920×1080. 
     In this embodiment, the image processing circuit  100  has six line buffers  110   a - 110   f , which temporally store the pixel values of six pixel rows of the first enlarged image I P1 . Accordingly, the first sharpness circuit  104  can performs a 7-tap vertical sharpening on the first enlarged image I P1 . In addition, in this embodiment, the data length of each of the line buffers  110   a - 110   f  is equal to 2160 bytes. In contrast to the image processing circuit  10  of  FIG. 1 , the image processing method of the disclosure permits a vertical sharpening of the same number of taps by using line buffers of shorter data lengths. Therefore, the image processing circuit of the disclosure has a lower manufacturing cost. If the image processing circuit of the disclosure uses line buffers having the same, rather than shorter, data lengths, the image processing circuit of the disclosure can performs a vertical sharpening of more taps. 
     Please refer to  FIG. 5 , which is a diagram illustrating how the first sharpness circuit of  FIG. 3  vertically sharpens the first enlarged image to generate the first sharpened image. As mentioned, the buffers  110   a - 110   f  temporally stores the pixel values of a plurality of pixel rows of the first enlarged image I P1 . The stored pixel values are to be used by the first sharpness circuit  104 . As indicated by  FIG. 5 , each of the six line buffers  110   a - 110   f  temporally stores the pixel values of pixels  112  of a pixel row of the first enlarged image I P1 . Since in this embodiment the resolution of the first sharpened image I S1  is 720×1080, the first sharpened image I S1  has 1080 pixel rows of pixels  122 . The data length of each of the line buffers  110   a - 110   f  is equal to the data volume of all the pixels  122  in a single pixel row  120 . In other words, each of the line buffers  110   a - 110   f  can store the pixel values of 720 pixels. 
     When vertically sharpening the first enlarged image I P1 , the first sharpness circuit  104  fetches from the line buffers  110   a - 110   f  the pixel values of a plurality of pixels in a single pixel column of the first enlarged image I P1 . Based on the fetched pixel values, the first sharpness circuit  104  calculates the pixel value of a corresponding pixel of the first sharpened image I S1 . Furthermore, when the first scaling circuit  102  is generating the first enlarged image I P1 , the first sharpness circuit  104  can simultaneously calculates the pixel values of some pixels of the first sharpened image I S1  according to the already-generated pixel values of a part of pixels of the first enlarged image I P1 . Please refer to  FIG. 5 , pixel P 4 ′ is the one that the first sharpness circuit  104  is processing. The pixels  122  ahead of the pixel P 4 ′, which are represented by circles of real-lines, are the pixels that have been processed by the first sharpness circuit  104  already. The pixels  122  behind the pixel P 4 ′, which are represented by circles of dotted-lines, are the pixels that are going to be processed by the first sharpness circuit  104 . The first sharpness circuit  104  calculates the pixels values of the pixels  122  of the first sharpened image I S1  according to the pixel values stored in the line buffers on the go. For example, the first sharpness circuit  104  calculates the pixel value of the pixel P 4 ′ according to the pixel value of the pixel P 7  and the pixel values of the pixels P 1 , P 2 , P 3 , P 4 , P 5 , and P 6  stored in the line buffers  110   a - 110   f , respectively. The pixel P 7  is the pixel just generated by the first scaling circuit  102 . The locations of the pixels P 1 , P 2 , P 3 , and P 4  on the first enlarged image I P1  corresponds to the locations of the pixels P 1 ′, P 2 ′, P 3 ′, and P 4 ′ on the first sharpened image I S1 . In addition, the pixels P 1 , P 2 , P 3 , P 4 , P 5 , P 6 , and P 7  locate on the same column of the first enlarged image I P1 . 
     In this embodiment, the line buffers  110   a - 110   f  are first-in first-out (FIFO) buffers. In other words, the earliest stored pixel values will be first replaced by the pixel values newly generated by the first scaling circuit  102 . Please refer to  FIG. 6  and  FIG. 5 .  FIG. 6  is a diagram illustrating the status of the line buffers  110   a - 110   f  and the first sharpened image I S1  after the first sharpness circuit has finished calculating the pixel value of the pixel P 4 ′. As is shown in  FIG. 6 , the space of the line buffer  110   a  originally stored the pixel value of the pixel P 1  will be used to store the pixel value of the pixel P 7 . In other words, after the pixel value of the pixel P 4 ′ are calculated, the pixel value of the pixel P 1  will be replaced by the pixel value of the pixel P 7 . Afterward, the first sharpness circuit  104  proceeds to calculate the pixel values of the pixels  122  behind the pixel P 4 ′. For example, to calculate the pixel value of the pixel P B ′, the first sharpness circuit  104  uses the pixel value of the pixel P E  and the pixel value of the pixel P 8 , P 9 , P A , P B , P C , and P D  stored in the line buffers  110   a - 110   f.  The pixel P E  is the pixel just generated by the first scaling circuit  102 . The location of the pixel P B′  on the first sharpened image I S1  corresponds to the location of the pixel P B  on the first enlarged image I P1 . In addition, the pixels P 8 , P 9 , P A , P B , P C , P D , and P E  locate on the same pixel column of the first enlarged image I P1 . 
     As mentioned, when vertically sharpening the first enlarged image, the first sharpness circuit  104  fetches the pixel values of a plurality of pixels on a single pixel column of the first enlarged image I P1  from the line buffers  110   a - 110   f . According to the fetched pixel values, the first sharpness circuit  104  calculates the pixel value of a corresponding pixel of the first sharpened image I S1 . In other words, the first sharpness circuit  104  calculates the pixel values of the pixels  122  on the first pixel column of the first sharpened image I S1  according to the pixel values of the pixels  112  on the first pixel column of the first enlarged image I P1 . The first sharpness circuit  104  calculates the pixel values of the pixels  122  on the second pixel column of the first sharpened image I S1  according to the pixel values of the pixels  112  on the second pixel column of the first enlarged image I P1 . And so on. 
     In the aforementioned embodiment, the first sharpness circuit  104  calculated the pixel value of a corresponding pixel of the first sharpened image I S1  according to the pixel value of the pixel just generated by the first scaling circuit  102  and the pixel values stored in the line buffers  110   a - 110   f . In another embodiment of the disclosure, the image processing circuit  100  can include another line buffer in addition to the line buffers  110   a - 110   f . The additional line buffer temporally stores the pixel values of another row of pixels  112  of the first enlarged image I P1 . With the additional line buffer, the first sharpness circuit  104  can calculate the pixel value of a corresponding pixel of the first sharpened image I S1  according to the pixel values temporally stored in the line buffers  110   a - 110   f  and the pixel values temporally stored in the additional line buffer. 
     In addition, the first sharpness circuit  104  can perform a vertical sharpening of 6 taps or of other numbers of taps. The number of line buffers utilized by the image processing circuit  100  is determined according to the maximum number of taps of sharpening the first sharpness circuit  104  can perform. Because the image processing circuit  100  of this embodiment has 6 line buffers  110   a - 110   f , the first sharpness circuit  104  can perform a 7-tap vertical sharpening. If the image processing circuit  100  has only 4 of the 6 line buffers  110   a - 110   f , the first sharpness circuit  104  can perform a 5-tap vertical sharpening. In short, in an embodiment of the disclosure, the maximum number of sharpening taps the first sharpness circuit  104  can perform is greater than the number of line buffers by one. Please note that 4 or 6 line buffers are not a necessary limitation of the disclosure. In fact, the image processing circuit  100  can have any number of line buffers. 
     Please refer to  FIG. 7 , which is a diagram illustrating how the second sharpness circuit of  FIG. 3  horizontally sharpens the second enlarged image I P2  to generate the second sharpened image I S2 . As mentioned, the resolution of the second enlarged image I P2  is equal to the resolution of the second sharpened image I S2 . Assume that the resolutions of the second enlarged image I P2  and the second sharpened image I S2  are both 1920×1080. A plurality of pixels  132  on the second enlarged image I P2  form 1080 pixel rows  130 . A plurality of pixels  142  on the second sharpened image I S2  form 1080 pixel rows  140 . Each pixel row  130  or  140  includes 1920 pixels. 
     While the second scaling circuit  106  is generating the second enlarged image I P2 , the second sharpness circuit  108  can calculate the pixel values of a part of pixels on the second sharpened image I S2  according to the already generated pixel values of a part of pixels on the second enlarged image I P2 . As is shown in  FIG. 7 , the pixel P e ′ is the one that the second sharpness circuit  108  is processing. The pixels  142  ahead of the pixel P e ′, which are represented by circles of real-lines, are the pixels that have been processed by the second sharpness circuit  108  already. The pixels  142  behind the pixel P e ′, which are represented by circles of dotted-lines, are the pixels that are going to be processed by the second sharpness circuit  108 . When horizontally sharpening the second enlarged image I P2 , the second sharpness circuit  108  calculates the pixel values of a pixel  142  on a pixel row  140  of the second sharpened image I S2  according to the pixel values of a plurality of pixels  132  on the same pixel row  130  of the second enlarged image I P2 . For example, the second sharpness circuit  108  calculates the pixel vales of the pixels  142  on the first pixel row  140  of the second sharpened image I S2  according to the pixel vales of the pixels  132  on the first pixel row  130  of the second enlarged image I P2 . The second sharpness circuit  108  calculates the pixel vales of the pixels  142  on the second pixel row  140  of the second sharpened image I S2  according to the pixel vales of the pixels  132  on the second pixel row  130  of the second enlarged image I P2 . And so on. 
     Assume that the second sharpness circuit  108  performs a 7-tap horizontal sharpening on the second enlarged image I P2 . To calculate the pixel values of a pixel on the second sharpened image I S2 , the second sharpness circuit  108  has to use the pixel values of 7 pixels  132  on the same pixel row of the second enlarged image I P2 . As is shown in  FIG. 7 , the second sharpness circuit  108  selects some pixels  132  from a processing window  134  to perform the 7-tap horizontal sharpening. Normally, the processing window  134  includes 7 pixels  132  on the same pixel row  130 . Among the 7 pixels  132 , the pixel  132  that locates in the middle of the processing window  134  corresponding to the pixel  142  that the second sharpness circuit  108  is currently processing. For example, when the second sharpness circuit  108  is calculating the pixel value of the pixel P e ′ on the second sharpened image I S2 , the 7 pixels within the processing window  134  are P b , P c , P d , P e , P f , P g , and P h . The pixels P b , P c , P d , P e , P f , P g , and P h  are on the same pixel row  130 . At this moment, the second sharpness circuit  108  calculates the pixel value of the pixel P e ′ according to the pixel values of the pixels P b , P c , P d , P e , P f , P g , and P h  within the processing window  134 . The locations of the pixels P d , P e , and P f  on the second enlarged image I P2  correspond to the locations of the pixels P d ′, P e ′, and P f ′ on the second sharpened image I S2 , respectively. In addition, the pixel value of the pixel P d ′ is calculated according to the pixel values of the pixels P a , P b , P c , P d , P e , P f , and P g ; the pixel value of the pixel P f ′ is calculated according to the pixel values of the pixels P c , P d , P e , P f , P g , P h , and P i . 
     While the second sharpness circuit  108  is horizontally sharpening the second enlarged image I P2 , the processing window  134  moves from left to right within the same pixel row  130 . After the second sharpness circuit  108  finishes calculating all the pixel values on a pixel row  140 , the processing window  134  moves to the leftest part of the next pixel row  140 . While the second sharpness circuit  108  is processing the pixels  142  on the two sides of a pixel row  140 , the processing window  134  extends beyond the second sharpened image I S2 . The number of pixels lie within the processing window  134  will be between 4 and 6, which is less than 7. Even when the pixels lie within the processing window  134  is less than 7, the second sharpness circuit  108  still calculates the pixel values of the pixels  142  on the two sides of a pixel row  140  according to the pixel values of the pixels  132  lie within the processing window  134 . 
     In the above embodiment, the second sharpness circuit  108  performs a 7-tap horizontal sharpening. However, this is not a necessary limitation of the disclosure. The second sharpness circuit  108  can perform a horizontal sharpening of any number of taps. The number of pixels covered by the processing window  134  can be adjusted according to the number of taps. For example, if the second sharpness circuit  108  performs a 9-tap horizontal sharpening, the processing window  134  can cover 9 pixels  132 . 
     Please refer to  FIG. 3 . The image processing circuit  100  not only can enlarge and sharpen images, but also can sharpen without enlarging images. For example, if the resolution of the input image I IN  is already 1920×1080, rather than enlarging the input image I IN , the first scaling circuit  102  can directly send the input image I IN  to the line buffers  110   a - 110   f . The first sharpness circuit  104  vertically sharpens the input image I IN  according to the data stored in the line buffers  110   a - 110   f  to generate the first sharpened image I S1 . Then, rather than enlarging the first sharpened image I S1 , the second scaling circuit  106  can directly send the first sharpened image I S1  to the second sharpness circuit  108 . The second sharpness circuit  108  horizontally sharpens the first sharpened image I S1  to generate the second sharpened image I S2 . Please note that while the first sharpness circuit  104  is vertically sharpening the input image I IN , each three line buffers  110   a - 110   c  and  110   d - 110   f  will store the pixel values of a pixel row of the first sharpened image I S1 . Specifically, the data volume of a pixel row of the 1920×1080 input image I IN  is 5760 (i.e. 1920×3) bytes. Because the data length of each of the line buffers  110   a - 110   f  is 2160 (i.e. 720×3) bytes, three line buffers will be required to store the pixel values of a pixel row of the first sharpened image I S1 . The six line buffers  110   a - 110   f  can store the pixel values of two pixel rows of the first sharpened image I S1 . In the circumstances, the first scaling circuit  102  can perform a 3-tap vertical sharpening on the 1920×1080 input image I IN . 
     The disclosure divides the image scaling into a vertical scaling and a horizontal scaling, and divides the image sharpening into a vertical sharpening and a horizontal sharpening. The vertical sharpening is performed after the vertical scaling and before the horizontal scaling. Therefore, the image processing circuit of the disclosure can use line buffers with shorter data lengths to perform the vertical sharpening. The vertical sharpening of the disclosure can be performed with more taps without requiring line buffers of longer data lengths. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations of this disclosure provided they fall within the scope of the following claims and their equivalents.