Abstract:
A method of safeguarding program parts which are critical to safety against inadvertent execution is described. In this method, at least one program part is executed in a predetermined chronological sequence. At a certain time in the execution, a pattern is generated. At least at one later time, a check is then performed to determine whether the pattern is present. If the pattern is not present, the execution of the respective program part is terminated. A memory device for executing such a method is also described.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to a method of safeguarding program parts which are critical to safety, and to a memory device for implementing the method.  
         BACKGROUND INFORMATION  
         [0002]    The software used in controllers and motor vehicles, for example, is becoming increasingly more complex because of constantly rising demands made on such software. This and the increasingly differentiated boundary conditions have led to a characterization of a wide variety of operating states of the software system.  
           [0003]    It is problematic that some of these operating states are highly incompatible with one another. If program parts which are assigned to different operating states are stored at the same memory locations, inadvertent execution of a program part in the wrong operating state may lead to a condition that is critical to safety.  
           [0004]    One example of this is the existence of an endless loop, which may be appropriate in anticipation of an external shutdown but should never be executed in the normal program sequence. During execution of such program parts, basic monitoring mechanisms such as a hardware or software watchdog are shut down or at least rendered ineffective.  
           [0005]    It is no longer possible today to guarantee complete avoidance of the existence of such program structures. Therefore, these program parts must be protected virtually 100% against inadvertent execution.  
           [0006]    Methods of preventing inadvertent alteration of memory contents, in particular the contents of flash EEPROM memories are widespread.  
           [0007]    German Published Patent Application No. 196 16 053 describes a method of operating a controller having a programmable memory device. The memory device is programmed by successive execution of a plurality of memory programming control operations.  
           [0008]    This should largely prevent in a simple manner interference-triggered, interference-influenced deletion and/or overwriting of data stored in the programmable memory device.  
           [0009]    This is achieved by providing a check step which determines whether all the selected individual or several memory programming control operations to be carried out by then have been executed, and by a decision step in which a decision is made, taking account the result of the check, as to whether the programming operation is to be continued as intended with the execution of additional memory programming control operations.  
           [0010]    It is, thus, possible to ascertain at any desired time whether the control operations to be carried out by then have in fact been carried out.  
           [0011]    European Published Patent Application No. 923 081 describes methods of writing to and erasing a flash EEPROM.  
           [0012]    In this method, a programming voltage or deletion voltage  35  corresponds to a read voltage. To differentiate the programming or erase voltage from the read voltage, the programming or deletion algorithms are to be processed in a specific sequence using specific addresses and specific data. The programming and deletion algorithms are shifted to a volatile memory allocated logically to the flash EEPROM.  
           [0013]    This achieves an increased security of the memory information stored in this flash EEPROM with respect to accidental overwriting or deletion.  
           [0014]    This prevents inadvertent overwriting or deletion of stored content caused by accidental exposure of the flash EEPROM to an electromagnetic discharge, programming errors, hardware defects and/or voltage pulses.  
           [0015]    In addition, an embodiment is also described in which the address information and data information needed for processing the programming and deletion algorithms is made available only by an external programming device.  
           [0016]    There are no known comparable methods of protecting any desired safety-critical program parts, however.  
         SUMMARY OF THE INVENTION  
         [0017]    It is the aim of the method according to the present invention to safeguard program parts, which are critical to safety, against inadvertent execution. In this method, a program having at least one program part is executed in a predetermined chronological sequence. At a certain time in the execution, a pattern is generated and a check is performed at least at one later point in time to determine whether the pattern is present. If the pattern is not present, the execution of the respective program part is terminated.  
           [0018]    The pattern may be a single bit which is set, or a bit pattern.  
           [0019]    The pattern is preferably generated in a volatile memory, e.g., a RAM module. This ensures that a pattern generated in a previous program run will have been deleted again after a program start.  
           [0020]    In the method according to the present invention, it is important that in the execution of safety-critical program parts, a check is performed at least at one point in time to determine whether a pattern is present. If the pattern is not present, e.g., because the program has jumped to the safety-critical area because of a mistake in the program pointer, execution of the program part is terminated.  
           [0021]    The memory device according to the present invention for execution of the method according to the present invention is divided into one or more sectors. A program part is stored in each sector. The program part(s) is (are) executable in a predetermined chronological sequence. The memory device according to the present invention is characterized in that an arrangement is provided for causing a pattern to be generated in execution of the program part at a certain point in time and at least one other arrangement is provided which causes a check to be performed at a later point in time to determine whether the pattern is present.  
           [0022]    The program stored in the memory device is processed by a microprocessor.  
           [0023]    It is advantageous for the pattern generation to be performed at the earliest possible point in time.  
           [0024]    In addition, a program routine which causes the processor to be reset may be provided in the memory device. In the case of a defective run through the program, the program pointer skips this program routine. However, if the program pointer jumps because of an error in the program routine, the processor is reset.  
           [0025]    Suitable data media such as EEPROMs, flash memories, as well as CD ROMs, diskettes or hard drives may be used as the memory device for executing the method according to the present invention. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0026]    [0026]FIG. 1 is a schematic diagram showing a conventional memory device.  
         [0027]    [0027]FIG. 2 is a schematic diagram showing an embodiment of the memory device according to the present invention.  
         [0028]    [0028]FIG. 3 is a flow chart showing the sequence of an embodiment of the method according to the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0029]    [0029]FIG. 1 shows a schematic diagram of a conventional memory device  10 . Memory device  10  has a first area  11  and a second sector  12 . An arrow  13  indicates the direction of execution. A first program part  14  is contained in first sector  11  and a second program part  15  is contained in second sector  12 . In addition, data is stored in a data field  16  in second sector  12 .  
         [0030]    The second program part  15  which is provided in memory device  10  contain safety-critical routines and execution of these routines at a certain time (i.e., in a certain operating mode) is avoided.  
         [0031]    First program part  14  and second program part  15  are designed so that second program part  15  is called up directly by first program part  14  or at least there is a fixed causal linkage between the two.  
         [0032]    [0032]FIG. 1 shows a first critical area  17  and a second critical area  18 . Critical areas  17 ,  18  include the parts of the memory into which inadvertent jumping of the program pointer could result in complete execution of safety-critical second program part  15 .  
         [0033]    Reasons for the extent of the critical area include:  
         [0034]    1. If the program pointer jumps to first program part  14 , this results directly or indirectly in further execution of second program part  15  and thus the safety-critical routines.  
         [0035]    2. If the program pointer jumps to data field  16 , this first results in execution of inoperative commands (data as op code) but it need not necessarily result in resetting of the processor. Therefore, there is the possibility that the program pointer might continue running up to the area of executable second program part  15 , and thus the safety-critical routines might be executed.  
         [0036]    3. If the program pointer jumps directly into second program part  15 , this results in complete execution of the safety-critical routines. This may result in execution of an endless loop here, for example. To prevent this, the following procedure is used according to the present invention.  
         [0037]    [0037]FIG. 2 shows a memory device according to the present invention, diagramed schematically with reference number  20 .  
         [0038]    Memory device  20  according to the present invention has a first sector  21  and a second sector  22 . An arrow  23  illustrates the direction of execution. A first program part  24  is provided in first area  21 , and a second program part  25  is provided in second area  22 . The second program part contains safety-critical routines.  
         [0039]    In addition, second sector  22  includes a data field  26 .  
         [0040]    In first sector  21 , a first arrangement  27  is provided, causing a pattern to be generated. First arrangement  27  may be, for example, a program routine which sets a bit or a bit pattern.  
         [0041]    Accordingly, an arrangement  28  which performs a pattern check is provided in second sector  22 . Second arrangement  28  may be, for example, a program routine which checks on whether the corresponding bit or bit pattern has been set.  
         [0042]    In addition, a program routine  29  which causes a reset of the processor is also shown in second sector  22 .  
         [0043]    In the case of memory device  20  according to the present invention, measures are thus taken, as explained below, to prevent inadvertent execution of safety-critical second program part  25 .  
         [0044]    First, at the beginning of first program part  24 , a pattern which is required for execution of second program part  25  is generated in the volatile RAM by first arrangement  27 . If the program pointer jumps to first sector  21  behind first arrangement  27 , initially this results directly or indirectly in further execution of second program part  25 . However, execution of second program part  25  is terminated because of the absence of the pattern, which is ascertained via the check performed by arrangement  28 . Inadvertent generation of the pattern is possible only if the program pointer jumps to the program sequence before execution of the pattern generation by first arrangement  27 .  
         [0045]    Thus, it is advantageous for the first arrangement  27  to generate the pattern at the earliest possible point in time in the program execution.  
         [0046]    Furthermore, the command for resetting the processor is stored at the physical beginning of second sector  22  where safety-critical second program part  25  is located. If the program pointer jumps to data field  26 , this first results in execution of inoperative commands (data as op code), as in the unprotected case, but then it need not necessarily result in resetting of the processor. Therefore, there is also the possibility that the program pointer will continue to run. On reaching program routine  29 , the processor is then automatically reset, and further execution of safety-critical second program part  25  is prevented.  
         [0047]    In the case of a faulty program run, the program pointer jumps out of first sector  21  into second sector  22  behind program routine  29 .  
         [0048]    In addition, if the program pointer jumps directly into second sector  22 , this results in execution of the following safety-critical second program part  25  until the next stored check of the required pattern. Since no pattern has been generated at position  27  in sector  21 , the execution of safety-critical second program part  25  at this position is terminated.  
         [0049]    Fields  30  and  31  illustrate the critical area which has been reduced considerably in comparison with critical fields  17  and  18  from FIG. 1. Fields  32  and  33  show the protected area, and field  34  indicates the area protected from repeated execution.  
         [0050]    If external boundary conditions (e.g., states of hardware components) are checked when the pattern is checked and when the pattern is generated, then it is possible to achieve 100% prevention of inadvertent execution of second program part  25  by a jump into this first sector  21 .  
         [0051]    For example, if execution of first program part  24  and second program part  25  depend on an external condition, then this condition, e.g., a voltage value, is additionally checked once again.  
         [0052]    [0052]FIG. 3 illustrates the sequence of an embodiment of the method according to the present invention in a flow chart.  
         [0053]    Execution of the program begins with a step  40 . The program pointer jumps into first area  27 .  
         [0054]    In a step  41 , a pattern is generated. First program part  24  which is stored in first sector  21  is executed. After the end of this program part, the program pointer jumps to second sector  22  in step  42 .  
         [0055]    In step  43 , second program part  25  in second sector  22  is executed, and, in addition, a check is performed at various times to determine whether the pattern generated in first sector  21  has been stored in the RAM. If this is not the case, program is terminated in step  44 . If there is a pattern, as is the case in an error-free program run, the program is executed further in step  45 .  
         [0056]    With the help of the method according to the present invention, the probability of inadvertent execution of the safety-critical program parts and the resulting malfunction of the controller may be reduced to a great extent, i.e., by orders of magnitude.  
         [0057]    The method described here is suitable, above all, for preventing the execution of program parts which are critical to safety which are carried out cyclically. Cyclic execution may be prevented by storing a single check of the relevant pattern.  
         [0058]    Program parts which are critical to safety, even given a single execution, may also be broken down into the smallest possible parts by performing repeated checks.