Abstract:
Redundant chip sections held in standby are substituted for chip sections that are at risk of over heating based on certain sensor signals. When these signals are received operations of the chip section at risk IS transferred to a redundant chip section and the chip section at risk is shut down. After the original chip section has cooled, it becomes available as a replacement chip section itself. The sensor signals may be based on temperature values, elapsed operation time, and number or rate of operations within a chip section.

Description:
FIELD OF THE INVENTION 
     The present invention relates to the field of thermal management of semiconductor devices; more specifically, it relates to a technique of reusable redundant circuitry to prevent overheating of semiconductor devices. 
     BACKGROUND OF THE INVENTION 
     Semiconductor devices, especially microprocessor and other fast logic circuits, dissipate large amounts of heat during operation. Thermal management of such devices has been traditionally managed using heat sinks or other related thermal transfer solutions. A different class of solutions attacks the problem from within the chip itself. 
     Turning to the prior art, U.S. Pat. No 5,206,778 to Flynn et. al., teaches an on chip temperature sensing circuit that may be used by a thermal management system that may shut down some chip circuits. This patent is hereby incorporated by reference. 
     U.S. Pat. No. 5,451,892 to Baily, describes a thermal sensor circuit that controls the frequency of the CPU clock in a microprocessor in response to an increase in temperature above a first limit, and return to normal frequency in response to a decrease below a second limit. Though the chip is kept from overheating, for significant periods of time the chip is operating at lower speeds which would be a disadvantage in many situations. 
     Following along the same lines, U.S. Pat. No. 5,590,061 to Hollowell et. al. teaches turning off a portion of the chip in response to an increase in temperature above a first point and turning it back on in response to a decrease in temperature. Though the chip is kept from overheating, for significant periods of time portions of the chip are not operating which would be a disadvantage in many situations. 
     The present invention provides an on chip thermal management system that does not have significant impacts to the performance of the chip. 
     SUMMARY OF THE INVENTION 
     The present invention includes redundant chip sections held in standby that may be substituted for chip sections that are at risk of over heating based on certain sensor signals. When these signals are received operations of the chip section at risk transferred to a redundant chip section and the chip section at risk is shut down. After the original chip section has cooled, it becomes available as a replacement chip section itself. Therefore it is an object of the present invention to provide a semiconductor device with reusable redundant chip sections switchable among themselves. 
     Three methods of controlling the heat using different sensor signals are taught. According to the first method temperature sensing is used to activate and deactivate chip sections on as needed basis. In the second method a simple interval timer is used to sequentially activate and deactivate the various chip sections and in the third method, a transaction counter is used to count the number or rate of transactions within a section and to activate and deactivate chip sections on a as needed need basis. Accordingly, it is another object of the present invention to provide switching of chip sections to be based on temperature sensing, interval timing or transaction counting. 
     It is a still further object of the invention to provide a multi-chip application which includes identical redundant chips held in standby that may be substituted for chips that are at risk of over heating based on temperature sensing, interval timing, or transaction counting. 
    
    
     BRIEF DESCRIPTION OF DRAWINGS 
     The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
     FIG. 1 is a block diagram according to the present invention using two chip sections and a temperature sensor to determine when switching should occur between the chip sections; 
     FIG. 2 is a block diagram of the present invention using multiple chip sections and temperature sensors to determine switching among the chip sections; 
     FIG. 3 is a block diagram of the invention using two chip sections and an interval timer to determine when switching should occur between the chip sections; 
     FIG. 4 is a block diagram of the invention using multiple chip sections and an interval timer to determine switching among the chip sections; 
     FIG. 5 is a block diagram of the invention using two chip sections with a transaction counter to determine switching between chip sections; 
     FIG. 6 is a block diagram of the invention using multiple chip sections and transaction 
     FIGS. 7 a ,  7   b  and  7   c  are representations of data registers in two chip sections illustrating register update; 
     FIG. 8 is a state machine transition diagram of the present invention; 
     FIG. 9 is a schematic of a two chip section register update using scan chains; 
     FIG. 10 a schematic of a multiple chip section register update using scan chains; 
     FIG. 11 is a schematic representation of chip section register update using I/O mapping and MUXing; 
     FIG. 12 is a schematic representation of chip section register update using I/O mapping with a tristate bus; and 
     FIG.  13 . is a diagram showing the present invention applied to multiple chips. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A technique to prevent thermal failures in semiconductor devices using temperature sensors in accordance with the present invention is illustrated in FIGS. 1 and 2. FIG. 1 shows a schematic using two identical chip sections  10 A and  10 B having circuits that perform the identical function that may be subject to thermal failure due to heavy duty cycles such as microprocessor chips. However when the present invention is utilized only one of the sections is active and being utilized while the other is inactive and in a standby mode ready to replace the active section at any given time. If chip section  10 A is active and temperature sensor  12 A senses a preset temperature level, a sensor signal  14 A is sent to control logic circuit  30 . In response to the sensor signal  14 A the control logic circuit  30  turns off enable signal  34 A which will stop any new operations to occur in chin section  10 A. When chip section  10 A has conpleted all current operations, a finish signal  16 A is sent to the control logic circuit  30 . Control logic circuit  30  also sends a start signal  32  to data transfer circuit  22  allowing transferring of data through buses  20 A and  20 B to chip section  10 B. Such data transfer can occur either after chip section  10 A shuts down or during normal operations as described below. Control logic circuit  30  also sends a set signal  38  to I/O switching logic circuits  44  which will stop the I/O signals  50  from chip  10 A from being received by  110  function circuit  40  and allowing I/O signals  50  from chip  10 B to be received by I/O function circuits  40 . Then a ready signal  42  is sent back from I/O switching logic circuits  44  to the control logic circuit  30 . Control logic circuit  30  also sends disable signal  36  to prevent pass thru of I/O signal  50  thru I/O function circuit  40 . When the data transfer is finished, a complete signal  26  is returned to control logic circuit  30 , enable signal  35  is sent to I/O function circuit  40 , and enable signal  34 B is turned on to chip section  10 B at which point all operations that had been performed by chip section  10 A are now performed by chip section  10 B and chip section  10 A is allowed to cool. Later, when temperature sensor  12 B reaches a preset temperature level, sensor signal  14 B is sent to control logic circuit  30  and the switching process described above is reversed. Thus original chip section  10 A will then be reused as will chip section  10 B at some future time when chip section  10 A again reaches the preset temperature. 
     In some cases the time to overheat may exceed the time necessary to cool down the chip section so multiple chip sections would be required. In which case, a first section may be running, a second section may be cooling and a third section is in standby mode to replace the first section. It is also possible for the cool down time to be much shorter than the heat up time, but multiple chip sections may be desirable for performance reasons, and may share portions of a single or multiple replacement chip sections. Basic operation would be similar, but more complex control functions would be required. 
     FIG. 2 is a schematic illustrating multiple identical chip sections  110  having circuits that perform the identical functions that may be subject to thermal failure and a least one of the sections that is not in use would be in a standby mode ready to take over operations from the active chip section. The number of chip sections required is based on a calculation or model made of the chip section circuits under design or field operating conditions. Temperature sensors  112  monitor the temperature of each of the sections and temperature level sensor signal  114  is sent to control logic circuits  130  in the event any one of the section&#39;s temperature exceeds a preset limit. In response to the sensor signal  114  control logic circuit  130  turns off the enable signal  134  to the active chip section. When that chip section has completed current operations a finish signal  116  is sent to the control logic circuit  130  which sends a start signal  132  to the data transfer circuit  122  allowing the transfer of data through buses  120  to the chip section which is in the standby mode. This data transfer may occur after the active chip section shuts down or can be done continuously as described below. Control logic circuit  130  also sends a set signal  138  to I/O switching logic circuits  144  which stop I/O signals  150  from the active chip section being received by I/O function circuit  140  and allowing I/O signals  150  from chip the standby chip section to be received by I/O function circuits  140 . Ready signal  142  is received back from I/O switching logic circuit  144 . Control logic  130  also sends disable signal  136  to prevent pass thru of I/O signal  150  from the active chip section thru I/O function circuits  140 . When data transfer is accomplished a complete signal  126  is returned to control logic circuit  130 , and an enable signal  135  is sent to I/O function circuits  140 , and an enable signal  134  is turned onto the appropriate standby chip section  110 . All operations that had been performed by the active chip section are now performed by the standby section and the active chip section is allowed to cool. After cooling the active chip section itself is available for use as a replacement for any of the other chip sections and is placed in a standby mode. 
     In another embodiment of the present invention, interval timing is used to initiate the switching from an active chip section to a standby chip section which is illustrated in FIGS. 3 and 4. The schematic diagram shown in FIG. 3 is similar to that shown in FIG. 1 where like numerals are used to identify like elements. However, it is noted that temperature sensors  12 A and  12 B have been replaced by an interval timer  60  which sends switch signal  62  to control logic  30  after a preset time has elapsed. This time is based on a calculation or an empirical model of the chip sections  10 A and  10 B circuits under design or experimental operating conditions such that an active chip section is shut down when it is anticipated to be running at an elevated temperature and replaced by a standby chip section. 
     Likewise the schematic diagram of the system shown in FIG. 4 is similar to the one shown in FIG.  2 . Again the temperature sensors  112  have been replaced with interval timer  160  which sends switch signal  162  to control logic  130  after a preset time has elapsed. Both the number of chip sections time or rate is based on a calculation or empirical model made of the-chip section circuits under design or experimental operating conditions. The switching would be sequential, based on the longest running section to be replaced. Reset or initialization would require initial offsets in counters for each section in the control logic. 
     In another embodiment of the present invention transaction counting is used to initiate the switching between an active chip section to a standby chip section as illustrated in FIGS. 5 and 6. The schematic diagram shown in FIG. 5 is similar in operation as shown and described in connection with FIG.  1 . It is noted that temperature sensors  12 A and  12 B have been replaced with transaction timers  70 A and  70 B which send switch signals  72 A and  72 B respectively to control logic  30  after a preset number of circuit operations have occurred or a preset number of operations in a preset unit of time have occurred in the active chip section. The number of chip sections, number or rate of operations, and nature of operations monitored is based on calculation and modeling of the chip circuit sections  10 A and  10 B under assumed design or experimental operating conditions. In this manner an active chip section which has executed a number of transactions and is operating at an elevated temperature will be turned off and replaced by a standby chip section. 
     Similarly the schematic diagram shown in FIG. 5 is similar in operation as described in connection with FIG.  2 . However, the temperature sensors  112  have been replaced with transaction counters  170  which sends switch signals  172  to control logic  130  after a preset number of circuit operations have occurred in the active chip section or a preset number of operations in a preset unit of time have occurred. The number of chip sections, number or rate of operations, and nature of operations monitored is based on calculation and modeling of the chip circuit sections  110  under assumed design or experimental operating conditions. The switching between chip sections would thereby be handled based on optimum conditions to avoid any single chip section from becoming over heated. 
     It would be possible to transfer all data from active to standby chip sections when the switching occurs. However, a more efficient technique to transfer data between the chip sections may be considered which is illustrated in FIGS. 7A through 7C. Referring to FIG. 7A, a first chip section  201  contains m number of data registers  203 . Each data register  203  contains n number of data bits  205  and update “u” bit  207 . Second chip section  202  contains m number of data registers  204 . Each data register  204  contains n number of data bits  206  and update bit  208 . The number, size and organization of the two sets of data registers are identical. In FIG. 7A both sets of registers are shown in an initial or reset state. 
     In FIG. 7B chip section  201  is active and chip section  202  is designated as the standby section. When the data bits in any register in any group is changed the update bit is marked. Upon transfer of data from one chip section to another chip section only the registers with update fields marked are transferred. After the transfer the update fields in the active section  201  are cleared. Chip section  202  may then become the active chip section and chip section  201  will become the standby section. After transfer both chip sections registers contain the same data. 
     FIG. 7C shows activity has occurred in active chip section  202 . Upon transfer of data back to chip section  201  making it the active chip section, only registers with update fields marked are transferred. After the transfer the update fields from section  202  are then cleared and both chip sections registers contain the same data. The “X” in the data bits shown in FIGS. 7B and 7C indicate a data bit changed at any time since initialization or reset. 
     The method for transferring data described above is extendible to sets of three or more data registers in three or more chip sections. As a further enhancement it is contemplated that during the running state a controller may be included which would be able to scan through the update bits and on a first-in-first-out basis write out the contents of the marked data registers to the corresponding data registers in the next available chip section while clearing the marked update bits at the same time. This would be more efficient and greatly speed up switching time between active and standby chip sections. 
     FIG. 8 illustrates a state machine transition diagram for each chip section according to the present invention. Running state operation  210 , optional finish state operation  211  and transfer state operation  212  are shown. Since three states are possible two bits  221  and  222  are used to describe the active state. The active chip section starts in a running state  210 , and upon receiving a sense transfer signal  215  which may be from temperature sensor, transaction counter, or timing device, the control logic circuits will create a drop enable signal  216 . The active chip section will then complete its last operation, go into an optional finish state  211 , which prevents any new functions, and wait for I/O operations  217  to complete. Upon completion of the I/O operations a finish signal is sent to the control logic circuits and the active chip section will go into a wait for transfer state  212  so that this chip section is now off-line. To activate a chip section, the data transfer operations  218  must be completed whereby a scan chain or I/O mapping is accomplished and the chip section may again enter running or active state  210 . 
     The control of data transfers from the registers of one chip section to another may be accomplished using a scan chain as illustrated in FIG. 9 for two chip sections. MUX  231  on chip section  230  can receive scan in data  236  from within chip section  230  and scan out data  247  from chip section  240 . MUX  241  on chip section  240  can receive scan in data  246  from within chip section  240  and scan out data  237  from chip section  230 . Turning on the enable  235  allows data in register  243  to be read into register  233 , other wise the data read into register  233  is from scan in data  236 . Turning on the enable  245  allows data in register  233  to be read into register  243 , other wise the data read into register  243  is from scan in data  246 . Both enables cannot be on at the same time. The chip section being replaced is scanned out and the chip section being activated is scanned in. The rate of scanning of bits  232  and  242  in registers  233  and  243  respectively is controlled by clock signals  234 , taking n clock signals. 
     FIG. 10 illustrates a technique for scan chain method for multiple m chip sections. The first and last of m sections is shown. MUX  251  on the first chip section  250  can receive scan in data  256  from within chip section  250  and scan out data  259  from chip sections  2  thru m. MUX  261  on the m chip section  260  can receive scan in data  266  from within chip section  260  and scan out data  269  from chip sections  1  thru m−1. Select signal  255  on chip section  250 , and select signals  265  on chip section  260  will be generated by the control logic to transfer data from and to the appropriate chip sections. The rate of scanning by clock signals  254 , taking n clock signals. 
     An I/O map with MUXing method for transferring data between chip sections is illustrated in FIG.  11 . Data in each chip section is grouped into one or more data groups. The first group  270  and last group  280  is shown. Each data group has m data registers  271  and  281  respectively and each register has m data bits  272  and  282  respectively. The output from each bit is presented to MUX  276  and  286  respectively which can select the same bit address from all registers in the group. Since a large number of registers may exist and the MuXing means is required to select only one group at a time, a select n signal  275  and  285  respectively is provided. In this way, a transfer of data may be made from one chip section to another. The output from the MUX for each group  277  and  287  respectively is coupled to MUX  290 . A group update bit  273  and  283  respectively is used to create the select  291  for MUX  290 . 
     The control system sometimes referred to as the state machine as in connection with FIG. 8 is used to constantly monitor the activity of the active chip section and the standby section. The control system may then effectively use the I/O map to transfer the contents of the last active chip section to the next active chip section using the select signals and MUX operation described above. 
     FIG. 12 illustrates a form of I/O mapping for data transfer between sections using a tristate driven bus. Multiple register groups  295  each having a bit addressable write enable  296 A and a bit addressable read enable  296 B, are wired in parallel to bidirectional data bus  297 . The enables are selected by control logic  30 . 
     In a tristate driven bus the control logic will control which register to be MUXed out. Since a large number of registers can exist, a tristate bus is required to select one group at a time. In this manner, a transfer of data can be accomplished from one section of the chip to the other. The control logic tracks the active chip section and standby chip section. The control logic uses I/O mapping to thereby transfer the contents of the last active to the next active machine with the write enables the output drive of the selected register which is tied together onto a tristate bus. In operation, the control system enables the read port of the next active section registers which then loads the data from the common tristate bus. 
     The present invention as so far been described with all chip sections on the same chip. It is also possible to apply the invention to multiple chips having identical functions. FIG. 13 illustrates a multi-chip module where each chip section is now a separate chip, and the data transfer circuits, control logic circuits, and I/O switching logic and function circuits are on a separate control chip. Multi-chip module  300  has a plurality of logic chips  310  which may be switched from active to standby mode and control chip  320  is disposed thereon. Control chip  320  provides control logic, data transfer between chips I/O switching between chips, and some off-chip I/O functions. Each logic chip  310  is coupled to control chip  320  by data bus  330 , I/O bus  340  and control signal lines  322 . The techniques for switching between active to standby sections of a chip described above may be applied to multiple chips. For example, each chip can be equipped with a temperature sensing circuit to determine when to switch between an active chip to a standby chip. Alternatively each chip could have a transaction counting circuit to determine when to switch between an active chip to a standby chip. Alternatively, a timer circuit on the control chip could be used to determine when to switch between an active chip to a standby chip. 
     The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.