Abstract:
To provide a photoelectric conversion device with low noise at low cost. The photoelectric conversion device includes: a plurality of photoelectric conversion circuits whose output potentials change according to an amount of incident light; a plurality of reset circuits each connected to an output of each of the photoelectric conversion circuits; a plurality of amplification circuits for amplifying the output potentials of the photoelectric conversion circuits, the amplification circuits each being connected to the output of each of the photoelectric conversion circuits; a plurality of signal read circuits for reading the outputs from the amplification circuits; and a plurality of holding circuits for temporarily holding the read outputs from the amplification circuits.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a photoelectric conversion device for converting an optical signal into an electric signal, and more particularly, to an image sensor IC which is a photoelectric conversion device to be applied to an image reader such as a facsimile machine or an image scanner, and a contact image sensor having one or more of the image sensor IC.  
         [0003]     2. Description of the Related Art  
         [0004]     Up to now, improvements have been made on a photoelectric conversion device in terms of enhancement of sensitivity and a reduction of random noise.  
         [0005]     In order to eliminate reset noise by virtue of a circuit, as shown in  FIG. 15 , there has been an attempt to offset the reset noise by disposing a noise signal holding circuit.  
         [0006]     However, according to such the conventional photoelectric conversion device, the noise signal holding circuits must be provided as many as light receiving elements, which increases a chip area. Also, in order to enhance the sensitivity of the light receiving elements, it is necessary to increase the amplification factor of a downstream signal processor circuit. However, thermal noise of the circuits other than the reset circuit is also amplified at the same time. Therefore, it is difficult to obtain the high sensitivity/noise ratio. In particular, the signal processor circuit must operate at a high-frequency read frequency, normally at the frequency of 5 MHz or higher. In this case, the noise of a high frequency band is also amplified, making it difficult to attain the high sensitivity/noise ratio.  
       SUMMARY OF THE INVENTION  
       [0007]     In order to solve the above-mentioned problems, the present invention provides a photoelectric conversion device, including: a plurality of photoelectric conversion circuits whose output potentials change according to an amount of incident light; a plurality of reset circuits each connected to an output of each of the photoelectric conversion circuits; a plurality of amplification circuits for amplifying the output potentials of the photoelectric conversion circuits, the amplification circuits each being connected to the outputs of the respective photoelectric conversion circuits; a plurality of signal read circuits for reading the outputs from the amplification circuits; and a plurality of holding circuits for temporarily holding the read outputs from the amplification circuits, in which the plurality of amplification circuits is noninverting amplification circuits.  
         [0008]     Further, each of the noninverting amplification circuits includes: an operational amplifier; a capacitor disposed between an input terminal of the operational amplifier and a fixed potential; a capacitor disposed between the input terminal of the operational amplifier and an output of the operational amplifier; and a switch circuit disposed between the input terminal of the operational amplifier and the output of the operational amplifier, in which the signal read circuits are turned on when the switch circuit is turned off.  
         [0009]     Also, in a photoelectric conversion device for sequentially reading output signals from plural photoelectric conversion circuits to a common signal line, the common signal line is reset to a given potential, a predetermined potential is common to the potential of a reference voltage terminal, the photoelectric conversion device incorporates a signal processor circuit having the common signal line inputted thereto, and a reference voltage of the signal processor circuit is electrically connected to a reference voltage terminal.  
         [0010]     Also, an image sensor includes the plurality of photoelectric conversion devices, in which the reference voltage terminals are electrically connected to one another.  
         [0011]     Also, a photoelectric conversion device for sequentially reading output signals from a plurality of photoelectric conversion circuits to a common signal line, in which the common signal line is reset to a given potential in a posterior half of a period during which signals are read from respective light receiving elements, the photoelectric conversion device incorporates a signal processing circuit having the common signal line inputted thereto, the signal processing circuit includes a clamp circuit, and the clamp circuit is fixed to the given potential in the posterior half of the period during which the signals are read from respective light receiving elements.  
         [0012]     According to the photoelectric conversion device, the signal is amplified by plural amplifier circuits which are connected to the outputs of the photoelectric conversion circuits and amplify the output potentials of the photoelectric conversion circuits, while the operating speed of the amplifier circuits remains low. Accordingly, the noise of a high frequency band can be cut out, and the signal can be amplified with low noise. In addition, the amplification factor of the signal processor circuit that requires the high speed operation can be set to be low because the signal is amplified upstream, which makes it possible to reduce the noise of the output signal. From the above fact, it is possible to obtain the photoelectric conversion device with the high sensitivity/noise ratio at low cost, without using the noise signal holding circuit. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]     In the accompanying drawings:  
         [0014]      FIG. 1  is a schematic diagram showing an image sensor IC according to an embodiment of the present invention;  
         [0015]      FIG. 2  is a schematic diagram showing a contact image sensor according to an embodiment of the present invention;  
         [0016]      FIG. 3  is a schematic circuit diagram showing a photoelectric conversion block according to a first embodiment of the present invention;  
         [0017]      FIG. 4  is a schematic circuit diagram showing a photoelectric conversion block according to a second embodiment of the present invention;  
         [0018]      FIG. 5  is a structural diagram showing a photoelectric conversion block and a signal processor circuit according to an embodiment of the present invention;  
         [0019]      FIG. 6  is a block diagram showing a signal processor circuit according to an embodiment of the present invention;  
         [0020]      FIG. 7  is a circuit diagram showing a sample and hold circuit according to an embodiment of the present invention;  
         [0021]      FIG. 8  is a circuit diagram showing a buffer circuit according to an embodiment of the present invention;  
         [0022]      FIG. 9  is a circuit diagram showing an amplifier circuit according to an embodiment of the present invention;  
         [0023]      FIG. 10  is a circuit diagram showing a subtractor according to an embodiment of the present invention;  
         [0024]      FIG. 11  is a circuit diagram showing a clamp circuit according to an embodiment of the present invention;  
         [0025]      FIG. 12  is a timing chart showing a method of operation of the photoelectric conversion block and the signal processor circuit according to the first embodiment of the present invention;  
         [0026]      FIG. 13  is a timing chart showing a method of operation of the photoelectric conversion block and the signal processor circuit according to the second embodiment of the present invention;  
         [0027]      FIG. 14  is a timing chart showing a method of operation of the photoelectric conversion block and the signal processor circuit according to a third embodiment of the present invention; and  
         [0028]      FIG. 15  is a circuit diagram and a timing chart according to a conventional photoelectric conversion device. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0029]     Now, a description will be given in more detail of preferred embodiments of the present invention with reference to the accompanying drawings.  
       First Embodiment  
       [0030]      FIG. 1  is a schematic diagram showing an image sensor IC constituting a photoelectric conversion device of the present invention. The image sensor IC  41  is constructed of a signal processor circuit  42 , a photoelectric conversion block  43 , a reference voltage terminal  46 , and a signal. Output terminal  47 . Two common signal lines of the photoelectric conversion block  43  are inputted to the signal processor circuit  42 , and an output of the photoelectric conversion circuit  42  is connected to the signal output terminal  47 . Those two common signal lines are reset to a voltage of the reference voltage terminal  46  by two reset switches  9  and  10 . The reference voltage terminal  46  is connected to the sources of the two reset switches  9  and  10 , a reference voltage VREF of the signal processor circuit  42 , and a reset voltage Vreset of the photoelectric conversion block  43 . The reset voltage Vreset of the photoelectric conversion block  43  may be a voltage source inside of the IC.  
         [0031]      FIG. 2 , is a schematic diagram showing a contact image sensor composed of the image sensor IC  41  shown in  FIG. 1 . The contact image sensor is constructed of three image sensors IC  41 . The signal output terminals  47  of all of the image sensors IC  41  are connected to one another externally. Also, the reference voltage terminals  46  of all of the image sensors IC  41  are connected to one another externally, and a capacitor  48  is connected between the reference voltage terminals  46  and a ground (GND). The capacitor  48  is disposed in order to stabilize the potential of the reference voltage terminals  46 , and has a capacity of about 1 uF to 100 uF. Also, a voltage may be supplied to the reference voltage terminals  46  from an external voltage source which is connected to a VREF terminal of  FIG. 2 , or may be supplied from voltage sources inside of the image sensors IC.  
         [0032]     The potentials of the respective reference voltage terminals  46  are stabilized by the capacitor  48 , which also makes the potentials of all of the chips to be equal. As a result, the reset of the common signal lines and the operation of the signal processor circuit  42  can be stabilized.  
         [0033]      FIG. 6  is a block diagram showing the signal processor circuit  42  according to an embodiment of the present invention. Signals inputted to input terminals VIN 1  and VIN 2  are inputted to a subtractor  24  through buffer amplifiers  22  and  23 , respectively. An output of the subtractor  24  is inputted to a clamp circuit  25 . The subtractor  24  and the clamp circuit  25  may have the reference voltage common to each other, and are connected to a VREF terminal. An output of the clamp circuit  25  is inputted to a buffer amplifier  26 . The buffer amplifier  26  may be replaced with an amplifier circuit. In addition, the reference voltage of the amplifier circuit may be made common to that of the VREF terminal. An output of the buffer amplifier  26  is inputted to a sample and hold circuit  27 . An output of the sample and hold circuit  27  is inputted to a buffer amplifier  28 . An output of the buffer amplifier  28  is inputted to a transmission gate  29 . An output of the transmission gate  29  is connected to an output terminal VOUT 2 . The transmission gate  29  may be unnecessary depending on a purpose of use.  
         [0034]      FIG. 7  is a circuit diagram showing a sample and hold circuit according to an embodiment of the present invention, which can be used for the sample and hold circuit  27 . The sample and hold circuit is constructed of a transmission gate  30 , a dummy switch  31 , and a capacitor C 1 . In the sample and hold circuit, the transistor sizes of an NMOS and a PMOS of the transmission gate  30  are made identical with each other and the gate areas of the transistors of an NMOS and PMOS of the dummy switch  31  are made half of the gate area of the transistor of the transmission gate to thereby offset the noises of pulses of OSH and OSHX, which is inversion of OSH, with each other.  
         [0035]      FIG. 8  is a circuit diagram showing a buffer amplifier according to an embodiment of the present invention, which is constructed of an operational amplifier  32 . This circuit can be applied to the buffer amplifiers  22 ,  23 ,  26 , and  28 . The buffer amplifiers may be formed of source follower amplifiers.  
         [0036]      FIG. 9  is a circuit diagram showing an amplifier circuit according to an embodiment of the present invention, which is constructed of an operational amplifier  32  and a resistor. Using this circuit instead of the buffer amplifier  26  makes it possible to increase the amplification factor of the signal processor circuit.  
         [0037]      FIG. 10  is a circuit diagram showing a subtractor according to an embodiment of the present invention, which is constructed of an operational amplifier  32  and a resistor. In this circuit, a voltage obtained by subtracting the voltage of INM from the voltage of INP is multiplied by a gain that is determined by the ratio of the resistors, and then outputted with reference to the voltage of VREF. When the terminals are reversed to be inputted to INP and INM, the output can be inverted with reference to the voltage of VREF.  
         [0038]      FIG. 11  is a circuit diagram showing a clamp circuit according to an embodiment of the present invention, which can be used for the clamp circuit  25 . The clamp circuit is constructed of a transmission gate  30 , a dummy switch  31 , and a capacitor  33 . The clamp circuit, the transistor sizes of an NMOS and a PMOS of the transmission gate  30  are made identical with each other and the gate areas of the transistors of an NMOS and PMOS of the dummy switch  31  are made half of the gate area of the transistor of the transmission gate to thereby offset the noises of pulses of ΦCLAMP and ΦCLAMPX, which is inversion of ΦCLAMP, with each other.  
         [0039]      FIG. 3  is a schematic circuit diagram showing one of the photoelectric conversion blocks An included in the photoelectric conversion block  43  according to the first embodiment of the present invention. The photoelectric conversion block  43  according to the embodiment of the present invention has photoelectric conversion blocks An (blocks within a frame) shown in  FIG. 5 , the number of which corresponds to the number of pixels, and represented by N. Each of the photoelectric conversion blocks An includes read switches  16  and  17  that are connected to common signal lines BITS and BITR. The photoelectric conversion block An indicates a photoelectric conversion block of an n-th bit.  FIG. 5  is a structural diagram showing the photoelectric conversion block  43  and the signal processor circuit  42 .  
         [0040]     This circuit includes: a photodiode  1  that is a photoelectric conversion circuit; transfer switches  14 ,  15 ,  16 , and  17  that form a signal read circuit; a reset switch  2  that is a reset circuit; a noninverting amplifier that is constructed of resistors  4 ,  5  and an operational amplifier  3 ; a capacitor  12  that holds an optical signal, a capacitor  13  that holds a reference signal that is a reference of the photoelectric conversion circuit; common signal lines BITS and BITR; common signal line reset switches  9  and  10 ; and a signal processor circuit  42 . The capacitances CS and CR of the capacitors  12  and  13  are normally set to the same magnitude.  
         [0041]     As shown in  FIG. 5 , one of the terminals of the reset switch  2  is connected to a Vreset terminal, which is common to all of the photoelectric conversion blocks An.  
         [0042]     The photoelectric conversion block and the signal processor circuit can be formed on one semiconductor substrate.  
         [0043]      FIG. 12  is a timing chart showing a method of operation of the photoelectric conversion block  43  and the signal processor circuit  42  according to an embodiment of the present invention. In the operation of the image sensor IC  41  according to the present invention, the initialization of all of the photoelectric conversion blocks An and the photoelectric charge storage operation are conducted simultaneously at certain timings. A photo generation carrier Qp of an n-th bit stored by the photoelectric charge storage operation at a first timing TS 1  are assumed to be Qp 1 n. At a second timing TS 2 , all the photoelectric conversion blocks An store new photo generation carriers Qp 2 n, and at the same time, the photo generation carriers Qp 1 n of from the first bit to the final bit which are stored at the first timing TS 1  are sequentially outputted one by one from an image sensor IC 41  through the signal processor circuit  42 . In other words, OR, ORIN, and DSIN in  FIG. 12  are operated at the same time with respect to all the photoelectric conversion blocks An (hereinafter the photoelectric conversion block may be called “bit”). On the other hand, OSCH is different in the timing that is operated by the bit, and is indicated with (n).  
         [0044]     First, the operation of the photoelectric conversion block of the n-th bit will be described.  
         [0045]     When an initialization switch  2  is turned on by a pulse R 1  of OR, an output terminal Vdi of the photodiode  1  is fixed to the reference voltage Vreset, and when the initialization switch  2  is turned off, the output terminal Vdi becomes a value obtained by adding an off noise Voff to the voltage Vreset of Vdi. Immediately after the initialization switch  2  is turned off, a transfer switch  15  is turned on by a pulse of the position of R 1  of ΦRIN, and a reference signal after initialization of the photodiode  1  is read to the capacitor  13 . The voltage V(REF) is represented as follows when the offset of the operational amplifier  3  is ignored, and the reset voltage is set to Vreset: 
 
 V ( REF )= V RESET− V off( R 1+ R 2)/ R 2 
 
 where the resistances of the resistors  4  and  5  are R 1  and R 2 , respectively. 
 
         [0046]     Next, in the photoelectric charge storage operation at the first timing TS 1 , the photoelectric charges that have been captured by the photodiode  1  are stored. The photoelectric charges are stored in the photodiode  1 , and the potential of Vdi changes according to the amount of photoelectric charges. The storage period is from the end of the pulse R 1  of ΦR to the end of the pulse S 1  of ΦSIN in a succeeding cycle, which corresponds to a period of the first timing TS 1  shown in  FIG. 12 , and the same periods are set for all of the bits.  
         [0047]     The transfer switch  14  is turned on by the pulse Si of OSIN to read the output voltage corresponding to the photo generation carriers Qp that are obtained after the photoelectric charges captured by the photodiode  1  are stored. The output voltage is read to the capacitor  12 .  
         [0048]     When it is assumed that a variable of the potential of Vdi during TS 1  is ΔVdi, the voltage V(SIG) that is read to the capacitor  12  is represented as follows:  
               V   ⁡     (   SIG   )       =     VRESET   -     Voff   ⁢           ⁢       (       R   ⁢           ⁢   1     +     R   ⁢           ⁢   2       )     /   R     ⁢           ⁢   1     -     Δ   ⁢           ⁢   Vdi   ⁢           ⁢       (       R   ⁢           ⁢   1     +     R   ⁢           ⁢   2       )     /   R     ⁢           ⁢   1                   =       V   ⁡     (   REF   )       -     Δ   ⁢           ⁢   Vdi   ⁢           ⁢       (       R   ⁢           ⁢   1     +     R   ⁢           ⁢   2       )     /   R     ⁢           ⁢   1                 
 
 That is, a change in the potential of the photodiode  1  can be obtained by timing (R 1 +R 2 )/R 1 . The amplification factor of the noninverting amplifier is normally set to about 2 times to 20 times. 
 
         [0049]     Also, a high period of ΦR, ΦRIN, and ΦSIN that can be set to a relatively long period of time allows the through rate of the noninverting amplifier to be set to be small. For this reason, the components of the high band of noises of the noninverting amplifier do not affect the output. Accordingly, the noises can be reduced.  
         [0050]     Subsequently, a succeeding storage operation is repeated after repeating the initialization, prior to the photoelectric charge storage operation at the second timing TS 2 .  
         [0051]     Then, the operation of reading the reference signal and the optical signal will be described. The transfer switches  16  and  17  are turned on by the pulse of ΦSCH(n) at the same time during the storage period of TS 2  in  FIG. 12  to read the optical signal and the reference signal which have been held by the capacitors  12  and  13 , to the common signal line BITS and the common signal line BITR, respectively.  
         [0052]     A difference between the optical signal and the reference signal is taken in the signal processor circuit  42  described below, so that voltage difference caused by light can be taken.  
         [0053]     Then, during a posterior half of the pulse of ΦSCH(n), the common signal line reset switches  9  and  10  are turned on by the pulse of DSR to initialize the common signal line BITS and the common signal line BITR to the voltage of Vreset 2 . As shown in  FIG. 2 , when Vreset 2  is connected to VREF, the common signal line BITS and the common signal line BITR are initialized to the voltage of VREF. At this time, VREF is stabilized by an external large capacitor  48 , which allows the common signal line BITS and the common signal line BITR to be surely initialized to a constant voltage of VREF.  
         [0054]     Subsequently, when the transfer switches  16  and  17  of the subsequent bit are turned on by ΦSCH(n+1) after turning off the transfer switches  16  and  17  of the n-th bit by ΦSCH (n), the optical signal and the reference signal of the subsequent bit start to be read.  
         [0055]     In the following description, for convenience, a first half of the high period of ΦSCH(n) during which the optical signal and the reference signal are read to the common signal line BITS and the common signal line BITR is referred to as anterior half period, and a latter half period of the high period of ΦSCH(n) during which the common signal line BITS and the common signal line BITR are initialized to the voltage of VREF is referred to as posterior half period.  
         [0056]     Next, the operation of the signal processor circuit  42  will be described. The VIN 1  terminal and the VIN 2  terminal are connected with the common signal line BITS and the common signal line BITR, respectively. During the anterior half period, the optical signal and the reference signal are inputted to the subtractor through the buffer amplifiers  22  and  23 . During the posterior half period, the voltage of VREF is inputted to the subtractor through the buffer amplifiers  22  and  23 . Accordingly, in the anterior half period, the output of the subtractor becomes a level resulting from adding a VREF level to a level obtained by multiplying the difference between the optical signal and the reference signal by the gain times. In the posterior half period, the output of the subtractor becomes a level of VREF. Also, the levels in both of the anterior half period and the posterior half periodare effected by the offset of the buffer amplifiers  22 ,  23 , and the subtractor  24 .  
         [0057]     A clamp pulse ΦCLAMP is so added as to be on in the posterior half period and off in the anterior half period. As a result, an output of the clamp circuit  25  is clamped to a VREF level each time in the posterior half period. Accordingly, the output of the clamp circuit  25  in the anterior half period becomes a level resulting from adding the VREF level to a level obtained by subtracting the posterior half output of the bit which is one bit before the anterior half output of the subtractor. As a result, the output of the clamp circuit in the anterior half period becomes a level resulting from adding VREF to the level obtained by multiplying a difference between the optical signal and the reference signal by the gain. These levels are not effected by the offset of the buffer amplifiers  22 ,  23 , and the subtractor  24 .  
         [0058]     The sample and hold pulse OSH is so added to turn on in the anterior half period and to turn off in the posterior half period. Accordingly, the output in the anterior half period of the output after clamping is sampled and held in the posterior half period. Therefore, it is possible to maintain the output level for a long period of time.  
       Second Embodiment  
       [0059]      FIG. 4  is a schematic circuit diagram showing a photoelectric conversion block An according to another embodiment of the present invention. Different from the photoelectric conversion block An shown in  FIG. 3 , the resistors  4  and  5  are replaced with capacitors  6  and  7 , and a switch  8  is inserted between the input and the output of the operational amplifier  3 . One terminal of the capacitor  6  is set to a ground (GND), but may be set to another potential if the potential is fixed. Other structures are identical with those in  FIG. 3 .  
         [0060]     In the first embodiment, in order to reduce the current consumption, it is necessary to set the resistances R 1  and R 2  to be higher. To achieve this, a high resistant polysilicon is required, which increases the costs of the process. However, in the second embodiment, the high resistors are replaced with the capacitors to reduce the costs of the process.  
         [0061]      FIG. 13  is a timing chart showing a method of operation of the photoelectric conversion block  43  and the signal processor circuit  42  according to the second embodiment of the present invention.  
         [0062]     First, the operation of the n-th bit photoelectric conversion block will be described.  
         [0063]     The initialization switch  2  and the switch  8  are turned on by the pulses R 1  of ΦR and ΦSW to structure the operational amplifier  3  as a voltage follower amplifier. Accordingly, the output terminal Vdi of the photodiode  1  is fixed to the reference voltage Vreset, and the output of the operational amplifier  3  also becomes the reference voltage Vreset.  
         [0064]     Subsequently, when the initialization switch  2  is turned off, the voltage becomes a value resulting from adding the off noise Voff to the voltage Vreset of Vdi. Then, the switch  8  is turned off.  
         [0065]     Immediately after the switch  8  is turned off, the transfer switch  15  is turned on by the pulse of the position of R 1  of GRIN to read the reference signal after the photodiode  1  has been initialized, to the capacitor  13 . When the influences of the offset of the operational amplifier  3  and the off noise of the switch  8  are ignored, and the reset voltage is Vreset, the voltage V(REF) is represented as follows: 
 
 V ( REF )= V RESET− V off( C 1+ C 2)/ C 2 
 
 where the capacitances of the capacitors  6  and  7  are C 1  and C 2 , respectively. 
 
         [0066]     Next, in the photoelectric charge storage operation at the first timing TS 1 , the photoelectric charges that have been captured by the photodiode  1  are stored. The photoelectric charges are stored in the photodiode  1 , and the potential of Vdi changes according to the amount of photoelectric charges. The storage period is from the end of the pulse R 1  of ΦR to the end of the pulse S 1  of ΦSIN in a succeeding cycle, which corresponds to a period of the first timing TS 1  shown in  FIG. 12 , and the same periods are set for all of the bits.  
         [0067]     The transfer switch  14  is turned on by the pulse S 1  of ΦSIN to read the output voltage according to the photo generation carriers Qp that are obtained after the photoelectric charges captured by the photodiode  1  are stored. The output voltage is read to the capacitor  12 .  
         [0068]     When it is assumed that a variable of the potential of Vdi during TS 1  is ΔVdi, the voltage V(SIG) that is read to the capacitor  12  is represented as follows:  
               V   ⁡     (   SIG   )       =     VRESET   -     Voff   ⁢           ⁢       (       C   ⁢           ⁢   1     +     C   ⁢           ⁢   2       )     /   R     ⁢           ⁢   1     -     Δ   ⁢           ⁢   Vdi   ⁢           ⁢       (       C   ⁢           ⁢   1     +     C   ⁢           ⁢   2       )     /   C     ⁢           ⁢   1                   =       V   ⁡     (   REF   )       -     Δ   ⁢           ⁢   Vdi   ⁢           ⁢       (       C   ⁢           ⁢   1     +     C   ⁢           ⁢   2       )     /   C     ⁢           ⁢   1                 
 
 Subsequently, the succeeding storage operation is repeated after the initialization is repeated, prior to the photoelectric charge storage operation at a second timing TS 2 . 
 
         [0069]     The reading operation of the reference signal and the optical signal and the subsequent operation are identical with those in the first embodiment, and their description will be omitted.  
       Third Embodiment  
       [0070]      FIG. 14  is a timing chart showing another operating method according to a second embodiment. Different from the second embodiment, when the switch  8  turns off due to ΦSW, the switch  15  is in an on state by ΦRIN.  
         [0071]     The noise of the switch  8  and the noise of the operational amplifier  3  are sampled and held to a terminal between the capacitors  6  and  8  when the switch  8  turns off, thereby causing the noises in the output. However, when the switch  8  turns off, the load capacitor of the VO terminal in  FIG. 4  is increased, thereby making it possible to reduce the influence of those noises. Other operations are identical with those in the second embodiment.  
         [0072]     In the above-mentioned embodiments, while the photodiode is conducting the storage operation in the TS 2  period, it is possible to read the optical signal that has been stored in the previous storage period TS 1 . Accordingly, the LEDs of three colors of RGB are sequentially lighted to thereby read color image data. For example, it is possible that the red LED is lighted in the TS 1  period to read the red component, the green LED is lighted in the TS 2  period to read the green component, and the blue LED is lighted in the next TS 2  period to read the blue component. In this case, the red optical signal is read within the TS 2  period.  
         [0073]     In the above description of the image sensor according to the present invention, the signal processor circuit  42  may not be incorporated in the IC.  
         [0074]     The above description was mainly given of a linear image sensor IC, but the structures of  FIGS. 3 and 4  can be applied to the area image sensor IC.  
         [0075]     In the above description, the present invention is not limited to the above embodiments, but can be variously modified within a scope that does not deviate from the concept of the present invention.