Abstract:
A computer system and method for generating a hardware description language source code file with embedded microcode segments for describing control logic of a complex digital system. A macro file is defined, comprising source code written in the hardware description language and a macro name associated with a segment of the source microcode in the macro file. A skeleton file is defined, comprising source code written in the hardware description language and including a reference to the macro name. The skeleton file is combined with the segment of the source microcode from the macro file at the reference to the macro name using a preprocessor to form a final source code file. Preferably, each microcode segment is encapsulated between a pair of comment statements expressed in the hardware description language. The comment statements identify macro names that are used for specifying a location within a hardware description language source code file at which the encapsulated microcode statement will be instantiated. This protocol enables the designer to preserve the attributes of the microcode while using the advantages of a hardware description language programming framework.

Description:
BACKGROUND OF THE INVENTION 
     A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. 
     This invention relates generally to complex digital system design and more particularly to building a hardware description language representation of control logic for a complex digital system. 
     The behavior of electronic digital circuitry is dictated by control logic. The control logic in a simple digital system, such as a counter, can be mathematically defined and is relatively straightforward to design. Conversely, the control logic in a complex digital system, such as a microprocessor, must express a multitude of finite logic states and the amount of information conveyed is often too extensive for a human designer to comfortably comprehend. Consequently, computer-assisted design tools are often used to assist with the control logic design for complex digital systems and can also be used to simulate and test the intended behavior of the digital circuitry prior to actual synthesis into an integrated circuit. 
     One method of control logic design involves expressing the control logic as microcode which is burned or programmed into a read-only memory device, a gate array, a programmable logic device or similar logic block. During use of such a device, an address is input to the microcoded logic block which outputs the contents stored at that address, or a function of those contents, as control signals. Due to its similarity to a traditional computer program, microcode is easy to define and maintain. However, microcode is difficult to simulate and test using the computer-assisted design tools and is hard to synthesize into compact and fast logic blocks. 
     Another method of control logic design involves describing the control logic in a hardware description language, such as the Very High Speed Integrated Circuits Hardware Description Language (VHDL). With this design method, the structure and behavior of the circuit are specified in a source code file written in a hardware description language. The control logic can then be simulated and tested using the appropriate software packages and can be automatically synthesized into an electronic circuit. However, large control blocks, such as for microprocessor control, require a lengthy source code file and often contain a large amount of repeated code. The size of the source code file and the degree of code repetition make it difficult to maintain and develop complex digital systems using this method. 
     Therefore, there is a need for an apparatus and method for facilitating control logic design for a complex digital system using a hardware description language representation while avoiding the creation of a single monolithic hardware description language source code file containing repetitious segments of microcode. 
     SUMMARY OF THE INVENTION 
     It is, therefore, an object of the present invention to simplify the computer-aided design of digital logic circuitry, thereby avoiding the drawbacks of conventional microcode and circuit design by using a hardware description language. According to the invention, this is accomplished by encapsulating and manipulating microcode segments in a hardware description language format and by shortening the length and simplifying the structure of the hardware description language source code files used in specifying the control logic of the complex digital system. 
     The invention is a computer system and method for building a hardware description language representation of control logic for a complex digital system. A segment of microcode for expressing an operation performed by the complex digital system is represented in hardware description language source code. A macro definition is constructed by associating a macro name with the segment of microcode and stored in a macro file in the computer system. An interface to the complex digital system and a structure for the control logic for the complex digital system, including a reference to the macro name, are represented in hardware description language source code and stored in a skeleton file in the computer system. A final output file is formed by locating the reference to the macro name, obtaining the macro definition and replacing the macro name with the segment of microcode and stored in the computer system. 
     Using this computer system and method, an existing, production complex digital system has been completely redesigned by a team of designers with less experience and half the number as the original design team but in half of the time. 
     Preferably, each microcode segment is encapsulated between a pair of comment statements expressed in the hardware description language. The comment statements identify macro names that are used for specifying a location within a hardware description language source code file at which the encapsulated microcode statement will be instantiated. This protocol enables the designer to preserve the attributes of the microcode while using the advantages of a hardware description language programming framework. 
    
    
     The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention which proceeds with reference to the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a functional block diagram showing a computer system for designing control logic for a complex digital system represented in a hardware description language and constructed in accordance with the present invention. 
     FIG. 2 is a flow diagram of a method for generating a hardware description language source code file for describing control logic of a complex digital system in accordance with the present invention. 
     FIG. 3 is a flow diagram describing the operation of the preprocessor of FIG. 2. 
     FIG. 4 is a flow diagram of a routine for processing a data array in the process shown in FIG. 3. 
     FIG. 5 is a flow diagram of a routine for substituting a macro instantiation with a macro definition in the subprocess shown in FIG. 4. 
    
    
     The APPENDIX is a listing of pertinent portions of code for a preprocessor program for use in implementing the present invention. 
     DETAILED DESCRIPTION 
     Referring to FIG. 1, a functional block diagram of a computer system 10 for designing control logic for a complex digital system represented in a hardware description language, constructed in accordance with the present invention, is shown. An example of a complex digital system is a microprocessor characterized by a very large number of logic gates, representing a large finite state machine, and programmability. A simpler example is a decoder which converts or decodes a logic signal consisting of a small number of binary inputs into a wider control word. 
     In the described embodiment, a preprocessor 14 is employed and consists of a computer program running on a programmed digital computer system equipped with a central processing unit, a memory for storing hardware description language source code and other files, and a user input and output interface which includes an input device, such as a keyboard, and a display device, such as a monitor. A Sun Workstation, manufactured by Sun Microsystems, Mountain View, Calif., is employed to execute the preprocessor 14, although the preprocessor 14 can be ported to other similarly configured hardware platforms or networks. 
     In the computer system 10, a design specification 11 for describing the behavioral characteristics and structure of a target complex digital system is drafted by a designer. The design specification 11 breaks down the control logic into smaller blocks for representing individual electronic circuits or subsystems which form a part of the larger electronic system and which control the operation of other electronic subsystems included in the overall target design. The design specification 11 is used as a model for defining a skeleton file 12 and a plurality of macro files 13. These files are source code files expressed in a hardware description language for embodying the design specification 11 in a format usable with computer-assisted design tools. The skeleton file 12 and macro files 13 contain macro instantiations and corresponding macro definitions. A macro instantiation is simply a reference to a macro name located at a place in the source code file at which a segment of prestored microcode is to be substituted. A macro definition associates the macro name with a particular segment of microcode and is possibly stored in a different source code file. The structure of these files, including macro instantiations and macro definitions, is described further below. 
     A preprocessor 14 combines the skeleton file 12 with one or more of the macro files 13 to form output file 15. The preprocessor 14 processes or conditions the source code before it is passed onto a compiler 16, hence the term preprocessor. The operation of the preprocessor 14 is described with reference to FIG. 3 et seq. 
     The skeleton file 12, macro files 13 and output file 15 are stored in the memory. The output file 15 is a description of the complete control logic for the complex digital system expressed in a hardware description language with macro instantiations removed by the preprocessor 14. The output file 15 can be reviewed by a designer on a display device on the workstation or computer terminal 18. Alternatively, the output file 15 can be compiled by the hardware description language compiler 16 to generate either an appropriate input format for a simulator/tester 17 or a net list 19 for describing the complex digital system as a series of logic gates. The simulator/tester 17 can be used by the designer to simulate and test the structure and behavior of the complex digital system, the results of which can be viewed on computer terminal 18. Alternatively, a synthesizer 20 can be used by the designer, using the net list 19 as inputs, to create an integrated circuit layout to be used to fabricate an actual physical electronic circuit chip 21. 
     The design specification 11 is broken down into smaller pieces with the skeleton file 12 generally providing an overall template for the structure of the complex digital system and the macro files 13 containing macro definitions. These are only general guidelines and the actual decision as to where to store structure or macro definitions is up to the designer. However, one design strategy is to collect macros containing segments of microcode for similar functions, such as addition or moves, into a single macro file 13. 
     Assuming the usual case, the skeleton file 12 is basically a template of the basic construction of the control logic for the complex digital system. For example, the skeleton file 12 for a decoder can be structured as follows: 
     
         ______________________________________entity DECODER isport (INSTR      : in bit.sub.-- vector(7 downto 0);MUCODE     : out bit.sub.-- vector(47 downto 0)end DECODER;architecture RTL of DECODER isINSERT MUCODE DEFINITIONSbeginDEC.sub.-- PROC: process(INSTR)beginINSERT MUCODE DEFAULTSif INSTR(OP.sub.-- CODE.sub.-- RANGE) = OP.sub.-- CODE thenif (INSTR(SRC.sub.-- MODE) = SRC.sub.-- IMMEDIATE) thenINSERT ADD IMMEDIATEelsif (INSTR(SRC.sub.-- MODE = SRC.sub.-- REGISTER) thenINSERT ADD REGISTERelsif . . ....end if;elsif INSTR(OP.sub.-- CODE.sub.-- RANGE) = MOV.sub.-- OPCODE thenif . . ....end if;end process DEC.sub.-- PROC;end RTL;______________________________________ 
    
     At a minimum, the skeleton file 12 contains a definition of the interface between the complex digital system and the outside world (&#34;entity DECODER is . . . &#34;) and the body or architecture of the complex digital system (&#34;architecture RTL of DECODER is . . . &#34;). One form of specifying the architecture is to include a conditional statement (&#34;if INSTR(OP --  CODE --  RANGE) . . . &#34;), sometimes quite lengthy, defining the behavioral characteristics of the complex digital system. In the described embodiment, a conditional statement is compiled using a special compiler for the Very High Speed Integrated Circuits Hardware Description Language (VHDL). 
     Within the architecture, three sections of code are commonly defined: definitions, defaults and connections. In the present example, these sections are defined using macro instantiations as further explained below, to simplify and shorten the length of the skeleton file 12, thereby making the skeleton file 12 easier to maintain and work with. Alternatively, these sections can be defined as hardware description language source code directly in either the skeleton file 12 or macro files 13. The definitions section (&#34;-- INSERT MUCODE DEFINITIONS&#34;) defines microcode fields to which signal values are assigned during the operation of the complex digital system or for reserving memory space or assigning temporary storage for a signal behavior observed during simulation. The defaults section (&#34;-- INSERT MUCODE DEFAULTS&#34;) assigns a signal value to each of the microcode fields defined in the definitions section. The default values are used in the event that no signal changes are effected to the microcode fields during the operation of the complex digital system. It is critical that all microcode fields are assigned a default value. The connections section (&#34;-- INSERT MUCODE CONNECTIONS&#34;) specifies the logical connections between each of the signals as used during simulation. Each microcode field is &#34;connected&#34; to an outgoing microcode word. It is critical that all microcode fields be specified. 
     In each of the macro files 13, one or more macro definitions are maintained. Macro definitions can also be maintained in the skeleton file 12, but the main purpose of the macro files 13 is to store macro definitions whereas the skeleton file 12 is primarily for storing a template of the complex digital system&#39;s structure. The macro files 13 can be used, for example, to store macro definitions for related control logic operations as instruction groups, such as arithmetic, move, branch and program control, bit manipulation, multiplication or special instruction groups. In addition, one of the macro files 13 can be designated a &#34;master&#34; macro file for storing the macro definitions for the definitions, defaults or connections sections. 
     The skeleton file 12 and macro files 13 can contain references to macro names for identifying a location in the hardware description language source code at which a segment of microcode will be substituted during preprocessing by the preprocessor 14. Each such macro reference is known as a macro instantiation. As described below and shown in FIG. 3 et seq., the preprocessor 14 first locates a macro instantiation, obtains the associated macro definition from the skeleton file 12 or one of the macro files 13 and outputs the corresponding segment of microcode in place of the macro instantiation to the output file 15. In the described embodiment, a macro instantiation is defined as a VHDL comment and is of the form: 
     -- INSERT MUCODE macro --  name 
     wherein -- INSERT MUCODE macro --  name marks a macro instantiation and macro --  name is the name of the macro. A similar methodology employing comment statements can be used for other hardware description language implementations. For instance, in Verilog HDL, the leading characters for comments are &#34;//&#34;. It is critical that the body of the macro definition substituted in place of the macro instantiation be consistent with the location in the hardware description language source code into which it is substituted. For instance, the use of undefined microcode fields must be avoided. 
     A macro definition consists of a macro name associated with a segment of microcode. Macro definitions can be nested. Each macro definition can contain other macro instantiations and a given macro can be used an unlimited number of times. Macro recursion, that is, a macro that contains an instantiation of itself or instantiates another macro ultimately leading to instantiation of itself, is not permitted. In the described embodiment, a macro definition is defined as a pair of VHDL comments which encapsulate or &#34;sandwich&#34; the microcode segment and is of the form: 
     -- START MUCODE macro --  name 
     &lt;segment of microcode&gt; 
     -- END MUCODE macro --  name 
     wherein -- START MUCODE macro --  name marks the start of a macro definition, -- END MUCODE macro --  name marks the end of a macro definition, macro --  name is the name of the macro and &lt;segment of microcode&gt; represents the microcode segment to be substituted in place of a macro instantiation. 
     Referring to FIG. 2, a flow diagram of a method for generating a hardware description language source code file 15 for describing the control logic of the complex digital system and in accordance with the present invention is shown. Its purpose is to build the necessary input hardware description language files and combine them into a final hardware description language output file. The method involves performing three basic steps. First, one or more of the macro files 13, as described above, are &#34;built,&#34; that is, written in a hardware description language and stored as a file in a computer system (block 30). Second, a skeleton file 12, as described above, is built (block 31). Finally, the preprocessor program 14, whose operation is described in FIG. 3 et seq., is executed to combine the skeleton file 12 with the one or more macro files 13 to form the output file 15 (block 32). 
     Referring to FIG. 3, a flow diagram describing the operation of the preprocessor 14 (block 32) is shown. Its purpose is to read in the skeleton file 12 and macro files 13 and combine them to form the output file 15. First, all lines of hardware description language source code, including comments, program text and definitions, are read from the skeleton file 12 and macro files 13 and stored into an internal data array in the computer memory (block 40). Second, a data processing routine, as further described below and shown in FIG. 4 et seq., is called to process the data array line-by-line to form the output file 15 (block 41). Upon the completion of preprocessing, the output file 15 contains a complete hardware description language description of the control logic for the complex digital system with all macro instantiations replaced by segments of microcode. 
     The source code for the preprocessor 14 for the described embodiment is included as the APPENDIX to this specification. It is written in the PERL programming language, although any general purpose programming language, such as the C programming language, is equally suitable. The preprocessor 14 accepts as inputs a skeleton file 12 and macro files 13 written in VHDL and outputs a output file 15 also written in VHDL, although other hardware description languages, such as Verilog HDL, are equally acceptable. In the described embodiment, the preprocessor 14 is invoked by specifying a program name followed by a list of the names of the macro files 13, the name of the skeleton file 12 and the name of the output file 15. 
     Referring to FIG. 4, a flow diagram of the routine for processing the data array (block 41 in FIG. 3) is shown. Its purpose is to analyze each line of data stored in the data array and to filter out macro definitions and instantiations. A first line of data is obtained from the data array (block 50). The control loop (blocks 51-58) begins. If the line of data represents the start of a macro definition (block 51), the next line of data is repeatedly read from the data array (block 52) until the end of the macro definition is encountered (block 53). Otherwise, if the start of a macro definition was not encountered (block 51), yet the line of data instead represents a macro instantiation (block 54), a routine for substituting the macro instantiation with a macro definition, as further described below in FIG. 5, is called, passing the macro name as an input argument (block 55). If the start of a macro definition is not encountered (block 51) and the line of data is not a macro instantiation (block 54), the line of data is printed out to the output file 15 (block 56). In this manner, macro definitions and instantiations are filtered out from the output file 15. The next line of data is obtained from the data array (block 57). If the end of the data array has not been encountered (block 58), execution continues at the top of the control loop (blocks 51-58) to begin processing the next line of data. Otherwise, if the end of the data array has been encountered (block 58), the routine returns. 
     Referring to FIG. 5, a flow diagram for the routine for substituting a macro instantiation with a macro definition (block 55 in FIG. 4) is shown. Its purpose is to substitute each macro instantiation encountered with an associated segment of microcode. The first line of data is obtained from the data array (block 60). The first control loop (blocks 61-65) begins. If the line of data is the start of a macro definition (block 61) and the macro name passed as an argument from the calling routine matches the name of the macro definition (block 62), the next line of data is obtained from the data array (block 63). Otherwise, if the line of data is not the start of a macro definition (block 61), the next line of data is obtained from the data array (block 72) and execution continues at the top of the first control loop (blocks 61-65). 
     If the line of data is the start of a macro definition (block 61), yet the macro name does not match the name of the instantiation (block 62), the next line of data is repeatedly read from the data array (block 64) until the end of the macro definition with a macro name that matches the name of the instantiation is encountered (block 65). Once the matching end of the macro definition is encountered (block 65), the next line of data is read from the data array (block 72) and execution resumes at the top of the first control loop (block 61-65). If the macro name matches the name of the instantiation (block 62), the second control loop (blocks 66-69) begins and the next line of data is read from the data array (block 63). If the next line of data is itself the start of a macro definition (block 66), a nested macro definition has been encountered and the next line of data is repeatedly read from the data array (block 67) until the matching end of the macro definition is encountered (block 68). Once the end of the macro definition is encountered (block 68), the next line of data is read from the data array (block 63) and execution continues at the top of the second control loop (blocks 66-69). If the start of a macro definition is not encountered (block 66), yet a macro instantiation is encountered (block 69), a nested macro instantiation has been encountered and the present routine is recursively called for processing the macro instantiation, passing the macro name as an input argument (block 55). Otherwise, if a macro instantiation is not encountered (block 69), yet the end of a macro definition has not been encountered (block 70), the routine is still within the body of the macro definition and the current line of data is printed out to the output file 15 (block 71). Otherwise, if the end of the macro definition has been encountered (block 70), the routine returns. 
     By employing encapsulated segments of microcode, a designer can fine tune the operation of each segment without the added complication of searching through a large hardware description language source code file to make changes in every occurrence of the microcode segment. During the design process, the designer initially writes a skeleton file and macro files in a hardware description language containing macro instantiations and macro definitions. These are submitted to the preprocessor which replaces all macro instantiations with a microcode segment from the corresponding macro definition to form a final output hardware description language source code file. The designer can revise the skeleton and macro files and iteratively resubmit them to the preprocessor until a satisfactory representation of the control logic for the complex system has been realized. 
     Having described and illustrated the principles of the invention in a preferred embodiment thereof, it should be apparent that the invention can be modified in arrangement and detail without departing from such principles. I claim all modifications and variations coming within the spirit and scope of the following claims. 
     
         __________________________________________________________________________APPENDIX: Preprocessor: PERL source code*******************************************#!/usr/local/bin/perl -w# Copy argument list into filename array# Read files intoline arrayif ($#ARGV == -1) {@DATA = &lt;STDIN&gt;;else {$i = 0;foreach $F(@ARGV) {# print STDERR $F, &#34;\n&#34;;open (FILE, $F) || die &#34;Cannot open file&#34;, $F,&#34;\n&#34;;while (&lt;FILE&gt;) {$DATA[$i] = $.sub.-- ;$i ++;}}}# $VHDL = &#34;VHDL&#34;;# open($VHDL, &#34;&gt;foo.vhd&#34;) || die &#34;Can&#39;t open VHDLoutput file.\n&#34;;$VHDL = &#34;STDOUT&#34;;$NEXT = 0;foreach $L (@DATA) {# First strip out unwanted macro definitions from outputif ($L =˜ /-- END/) {if ($NEST &gt; 0) {$NEST --;}}elsif ($L =˜ /-- START/) {$NEST ++;}elsif ($NEST &gt; 0) {}elsif ($L =˜ /([ ]*)-- INSERT (.*)/) {#Substitute this line with the appropriate code block#from the instructions file$BLANK.sub.-- LEADER = $1;#First extract the string to look for in the DATA array$SEARCH.sub.-- FOR = $2;#print STDERR $SEARCH.sub.-- FOR, &#34;\n&#34;;$RVAL = &amp;substitute ($SEARCH.sub.-- FOR, $BLANK.sub.-- LEADER);if ($RVAL != 0) {print STDERR &#34;ERROR: Could not find &lt;&#34;, $SEARCH.sub.-- FOR,&#34;&gt;\n&#34;}}else {print $VHDL $L;}sub substitute {# Search the DATA array for the macro called $SEARCH.sub.-- FOR,# and print in in the output streamlocal (@ARGS) = @.sub.-- ;local ($SEARCH.sub.-- FOR) = $ARGS[0];local ($BLANK.sub.-- LEADER) = $ARGS[1];local ($RVAL) = 0;* For each line of the lines arraylocal ($IX) = 0;while ($IX &lt;= $#DATA) {$LINE = $DATA[$IX];# Looking for --STARTif ($LINE =˜/-- START (.*)/ {# print STDERR &#34;&lt;&#34;, $1, &#34;&gt;&#34;;   # print STDERR &#34;Found a START\nLooking for &lt;&#34;,$SEARCH.sub.-- FOR, &#34;&gt;\n&#34;;if ($1 eq $SEARCH.sub.-- FOR) {   # print STDERR &#34;Found&#34;, $SEARCH.sub.-- FOR, &#34;\n&#34;;   print $VHDL $BLANK.sub.-- LEADER; print $VHDL $LINE;   # Found start of block we are looking for   #Now copy block until &#34;-- END&#34; is seen   while (1) {     # If a nested INSERT statement, call SUBSTITUTEfunction recursively     #else, just echo line     $IX ++;     $LINE = $DATA[$IX];     if ($LINE =˜ /([ ]*)-- INSERT (.*)/) {       local($NEW.sub.-- BLANK.sub.-- LEADER) = $BLANK.sub.--       LEADER.$1;       local($NEW.sub.-- SEARCH.sub.-- FOR) = $2;         # print STDERR &#34;calling substituterecursively!\n&#34;;        $RVAL = &amp;substitute($NEW.sub.-- SEARCH.sub.-- FOR,$NEW.sub.-- BLANK.sub.-- LEADER);       if ($RVAL != 0) {        print STDERR &#34;ERROR: Could not find &lt;&#34;,$NEW.sub.-- SEARCH.sub.-- FOR, &#34;&gt;, overall line\n&#34;       }     }     elsif ($LINE =˜ /-- START/) {       print STDERR &#34;Error in input data, overallline &#34;, $IX, &#34;\n.&#34;;       return 1;     }     else {      # This line strips out leading blanks in themacro definition       # $LINE =˜ s/[ ]*(.*)/\1/;         print $VHDL $BLANK.sub.-- LEADER; print $VHDL$LINE;       if ($LINE =˜ /-- END/) {         return 0;       }     }   }}}$IX ++;}return 1;}__________________________________________________________________________