Abstract:
A transmitter may comprise a first domain translation circuit, a first PAPR suppression circuit, and a descriptor generation circuit. The first domain translation circuit may convert a plurality of frequency-domain symbols of a first OFDM symbol to a corresponding plurality of first time-domain signals. The first PAPR suppression circuit may group the plurality of first time-domain signals into a plurality of sub-bands of the first time-domain. The first PAPR suppression circuit may invert one or more of the sub-bands of the first time-domain signals according to a value of a first descriptor. The descriptor generation circuit may determine the value of the first descriptor using an iterative process in which each iteration comprises random selection of a value of the first descriptor, determination of a PAPR of the first OFDM symbol processed using the randomly-selected value, and determination of whether said PAPR meets one or more determined criteria.

Description:
PRIORITY CLAIM 
     This application claims priority to the following application(s), each of which is hereby incorporated herein by reference: 
     U.S. provisional patent application 61/805,013 titled “Peak to Average Power Ratio Suppression” filed on Mar. 25, 2013. 
    
    
     TECHNICAL FIELD 
     Certain embodiments of the invention relate to electronic communications. More specifically, certain embodiments of the invention relate to a peak to average power ratio suppression. 
     BACKGROUND 
     High peak to average power ratios can have negative impacts on the cost and operation of electronic receivers. Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings. 
     BRIEF SUMMARY OF THE INVENTION 
     A system and/or method is provided for peak to average power ratio suppression, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims. 
     These and other advantages, aspects and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings. 
    
    
     
       BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS 
         FIG. 1  is a diagram illustrating an example transmitter operable to perform peak to average power ratio (PAPR) suppression. 
         FIG. 2  is a flowchart illustrating an example process for PAPR suppression. 
         FIG. 3  is a diagram illustrating example circuitry of the transmitter of  FIG. 1 . 
         FIG. 4  is a diagram illustrating an example transmitter operable to perform PAPR suppression while concurrently generating and transmitting multiple OFDM symbols in parallel. 
         FIG. 5A  is a diagram illustrating a first PAPR suppression technique for PAPR suppression of an example sequence of symbols generated by the transmitter of  FIG. 4   
         FIG. 5B  is a diagram illustrating example circuitry of the transmitter of  FIG. 4 . 
         FIG. 5C  is a diagram illustrating an example combining of time-overlapping symbols output by two OFDM circuits operating in parallel. 
         FIG. 5D  is a flowchart describing operation of the first PAPR suppression technique for the symbols shown in  FIG. 5A . 
         FIG. 5E  is a flowchart describing a generalized version of the first PAPR suppression technique for PAPR suppression in systems having two or more OFDM circuits operating in parallel. 
         FIG. 6A  is a diagram illustrating a second PAPR suppression technique for PAPR suppression of an example sequence of symbols generated by the transmitter of  FIG. 4   
         FIG. 6B  is a flowchart describing operation of the second PAPR suppression technique for the symbols shown in  FIG. 6A . 
         FIG. 6C  is a flowchart describing a generalized version of the second PAPR suppression technique for PAPR suppression in systems having two or more OFDM circuits operating in parallel. 
         FIG. 7  is a diagram illustrating an example transmitter having two OFDM circuits generating two OFDM symbol streams in parallel and suppressing total PAPR by manipulating the second OFDM symbol stream. 
         FIG. 8A  is a diagram illustrating a third PAPR suppression technique for PAPR suppression of an example sequence of symbols generated by the transmitter of  FIG. 7 . 
         FIG. 8B  is a flowchart describing operation of the third PAPR suppression technique for the symbols shown in  FIG. 8A . 
         FIG. 9  is a diagram illustrating an example transmitter operable to perform peak to average power ratio (PAPR) suppression for single-carrier transmissions. 
         FIG. 10  is a flowchart illustrating operation of the transmitter of  FIG. 9 . 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     As utilized herein the terms “circuits” and “circuitry” refer to physical electronic components (i.e. hardware) and any software and/or firmware (“code”) which may configure the hardware, be executed by the hardware, and or otherwise be associated with the hardware. As used herein, for example, a particular processor and memory may comprise a first “circuit” when executing a first one or more lines of code and may comprise a second “circuit” when executing a second one or more lines of code. As utilized herein, “and/or” means any one or more of the items in the list joined by “and/or”. As an example, “x and/or y” means any element of the three-element set {(x), (y), (x, y)}. As another example, “x, y, and/or z” means any element of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. As utilized herein, circuitry is “operable” to perform a function whenever the circuitry comprises the necessary hardware and code (if any is necessary) to perform the function, regardless of whether performance of the function is disabled, or not enabled, by some user-configurable setting. 
       FIG. 1  is a diagram illustrating an example transmitter operable to perform peak to average power ratio (PAPR) suppression. The example transmitter comprises system on chip (SoC)  102 , orthogonal frequency division multiplexing (OFDM) circuit  104 , IFFT circuit  106 , sub-band processing circuit  108 , digital-to-analog converter (DAC)  110 , front-end circuit ( 112 ), and inversion descriptor generation circuit  114 . In the example implementation, the circuit  114  comprises an IFFT circuit  120 , control logic circuit  122 , random number generator circuit  124 , sub-band inverting and combining circuit  126 , PAPR calculation circuit  128 , and memory  130 . 
     A bitstream output by the system on chip (SoC)  102  is input to the OFDM circuit  104  which maps the bitstream to J*K QAM symbols corresponding to J*K OFDM subcarriers (a frequency-domain representation of an OFDM symbol). Along the main signal path (including  106 ,  108 ,  110 , and  112 ), the subcarriers are grouped into K sub-bands of J subcarriers each. Each of the K sub-bands is input to IFFT circuit  106 , which may perform a full-resolution (e.g., X bits) IFFT that operates on that sub-band. Thus, in an example implementation, the output of the IFFT  106  is K time-domain signals. 
     The sub-band processing circuit  108  may invert one or more of the K signals, and then sum the K signals (possibly with one or more of them having been inverted) such that the peak-to-average-power ratio (PAPR) of the summation is below a determined threshold. Which of the K signals are inverted by the circuit  108  may be dictated by an inversion descriptor generated by circuit  114 . 
     The result of the summation may be output as signal  109 , and may then be converted to analog by DAC  110  and, subsequently, processed (e.g., upconverted and amplified) by the front end circuit  112  for transmission onto a channel (wired, wireless, or optical). 
     Although, various implementations are described herein using J*K subcarriers uniformly distributed among K sub-bands, in other implementations the subcarriers may be non-uniformly distributed among the sub-bands (i.e., each of the K sub-bands may have any number of subcarriers which may be different from any other of the sub-bands). Furthermore, subcarriers grouped into a particular subband need not be adjacent to one another. For example, subcarriers that are spaced apart in frequency may be grouped into a common sub-band because the subcarriers share certain characteristics in the frequency domain and/or in the time domain. 
       FIG. 2  is a flowchart illustrating an example process for PAPR suppression. The process begins with block  202  in which the inversion descriptor generation circuit  114  receives an OFDM symbol output by the OFDM circuit  104 . 
     In block  204 , the circuit  114  combines each set of J subcarriers into one of K sub-bands. In block  206 , the IFFT circuit  120  generates K time-domain signals from the K sub-bands. In an example implementation, the IFFT  120  may operate similarly to the IFFT  106  but perhaps at a lower-resolution than the IFFT circuit  106  such that conversions performed by the IFFT circuit  106  are fast and/or consume less power than conversions performed by the IFFT  106 . This may be acceptable because less precision is needed for the IFFT circuit  129  as compared to the IFFT circuit  106 . 
     In block  208 , a variable ‘m’ is initialized/reset (e.g., set to zero). 
     In block  210 , a descriptor is generated based on the value of ‘m.’ In an example implementation, ‘m’ may be a seed value provided to random number generator circuit  124  such that the descriptor is a random value. In another implementation, the descriptor may be selected non-randomly based on information about the system (e.g., based on statistics collected based on previous descriptors used for previous OFDM symbols). In such an implementation ‘m’ may be, for example, an index of a look-up table. 
     In block  212 , the circuit  126  inverts one or more of the K signals generated in block  206  according to the descriptor generated in block  210 . 
     In block  214 , the circuit  126  sums the K signals. 
     In block  216 , the circuit  128  measures the PAPR of the sum generated in block  214 . 
     In block  218 , the control logic  122  determines whether the PAPR measured in block  216  is above a determined threshold. If not, the descriptor is output to circuit  108  to be used for processing the OFDM symbol. If so, then the process goes to block  220  where m is modified (e.g., incremented by 1 or a random value). 
       FIG. 3  is a diagram illustrating example circuitry of the transmitter of  FIG. 1 . In  FIG. 3 , a 0  to a kj-1  represent the K*J subcarrier values corresponding to the frequency domain representation of the OFDM symbol input to circuit  114 . Each group of J subcarriers is converted to one of K time-domain signals  302   0 - 302   K-1 . One or more of the signals  302   0 - 302   K-1  are then inverted according to the inversion descriptor. The resulting output is signals  304   0 - 304   K-1 , where each signal  304   k  (0≦k≦K) may be the same as, or inverted relative to, the corresponding signal  302   k . The signals  304   0 - 304   K-1  are summed via combining circuit  126 , resulting in signal  308 . Circuit  128  then calculates the PAPR of the sum signal  308 . If the PAPR is too high, a different inversion descriptor is tried until a suitable one is found or until a timeout. 
       FIG. 4  is a diagram illustrating an example transmitter operable to perform PAPR suppression while concurrently generating and transmitting multiple OFDM symbols in parallel. The example transmitter  400  comprises the SoC  102 , two instances of OFDM circuit  104  (labeled as  104   a  and  104   b ), two instances of IFFT circuit  106  (labeled as  106   a  and  106   b ), two instances of sub-band processing circuit  108  (labeled as  108   a  and  108   b ), a combiner circuit  402 , the DAC  110 , the front-end  112 , and inversion descriptor generation circuit  214 . 
     The inversion descriptor generation circuit  214  is similar to the circuit  114  but comprises two instances of IFFT circuit  120  (labeled  120   a  and  120   b ), two instances of inversion and combining circuit  126  (labeled  126   a  and  126   b ), a combiner  132 , and is operable to generate multiple inversion descriptors corresponding to the multiple OFDM symbol paths. The two descriptors may, for example, be determined as described below in one or more of  FIGS. 5A-8B . 
       FIG. 5A  is a diagram illustrating a first PAPR suppression technique for PAPR suppression of an example sequence of symbols generated by the transmitter of  FIG. 4 . The symbol sequence comprises two parallel symbol streams from the circuits  104   a  and  104   b . At time T 3 , the only symbol that has been received by circuit  214  is symbol A 0 , and the circuit  214  generates an A_descriptor value to be used for processing A 0 . At time T 4 , symbol B 1  is received at circuit  214 , the overlapping portions of A 0  and B 1  are combined (e.g., as shown in  FIG. 5C ), and then circuit  214  generates a B_descriptor value to be used for processing symbol B 1 . At time T 5 , symbol A 2  is received at circuit  214 , the overlapping portions of A 2  and B 1  are combined similar to how A 0  and B 1  were combined at time T 4 , and then the circuit  214  generates an A_descriptor value to be used for processing symbol A 1 . This process continues for the symbols B 3 , A 4 , B 5 , and A 6  at times T 5 , T 6 , T 7 , and T 8 . 
       FIG. 5B  is a diagram illustrating example circuitry of the transmitter of  FIG. 4 . When a symbol from  104 A is ready, it is converted to a time-domain representation by circuit  420   a  and latched into a register  502  (e.g., part of memory  430 ). The most recently-received symbol, latched in a register  504  (e.g., part of memory  430 ), is shifted by the amount of time since it was received from  104 B. The inversion descriptor previously determined for the most-recently-received symbol from  104 B is applied, by circuit  108   b , to the shifted symbol in register  504 . Various values of A_Descriptor are then tried in combination with the previously-determined value of B_descriptor until PAPR below a threshold is achieved or a timeout occurs. That is, a first value of A_Descriptor is applied to the contents of register  502  via circuit  126 A, the previously-determined value of B_Descriptor is applied, via circuit  126   b , to the contents of register  504 , then the outputs of  126   a  and  126   b  are combined via circuit  132  and register  506  to generate signals C[k] (0≦k≦K) which are then combined via circuit  132  to generate signal  507 . The PAPR of signal  507  is then measured. If the PAPR of signal  507  is too high, then a different value of A_Descriptor is selected, and the process just described repeats. The process may repeat until a value of A_Descriptor that achieves PAPR is found or until a timeout occurs. If the timeout occurs, the A_descriptor that achieved the best PAPR of the ones tried may be selected for use. The generation of signal  507  for the example symbols A 2  and B 1  is further described below with reference to  FIG. 5D   
       FIG. 5C  is a diagram illustrating an example combining of time-overlapping symbols output by two OFDM circuits  104   a  and  104   b  operating in parallel. In  FIG. 5C , A 0  comprises four samples of each of three subcarriers, and B 1  comprises five samples of each of three subcarriers (the first subscript indicates symbol index, the second subscript indicates subcarrier index, and the third subscript indicates sample index). 
       FIG. 5D  is a flowchart describing operation of the first PAPR suppression technique for the example symbols shown in  FIG. 5A . The process begins with block  520  in which symbol A 2  ( FIG. 5A ) is received by circuit  214 . 
     In block  522 , IFFT circuit  120 A converts A 2  to time-domain representation A 2 ′. 
     In block  524 , IFFT circuit  120 B converts B 1  to time-domain representation B 1 ′. 
     In block  526 , a previously-determined (e.g., during an iteration of the process shown in  FIG. 5D  for symbol B  1 ) B_Descriptor is applied to B  1 ′ to generate B 1 ″. 
     In block  530 , a variable ‘m’ is initialized/reset (e.g., set to zero). 
     In block  532 , A_Descriptor is set to a value that corresponds to m. For example, m may be a random seed fed to random number generator  124  or may be an index of a lookup table stored in memory  130 . 
     In block  534 , time-overlapping portions of A 2 ″ and B 1 ″ are combined resulting in signals C[1:K]. 
     In block  536 , the signals C[1:K] are combined to generate signal  507  and the PAPR of signal  507  is measured. 
     In block  538 , it is determined whether the PAPR measured in block  536  is above a determined threshold. If not, the process proceeds to block  528 , a new value of m is selected (e.g., m is incremented), and blocks  532  through  538  are repeated until the PAPR is below the threshold or a timeout. If the PAPR is below the threshold, then the process advances to block  540 . 
     In block  540 , the current value of A_Descriptor (determined in block  532 ) is used by IFFT circuit  108   a  for processing symbol A 2 . 
     In block  542 , symbol B 3  is received by circuit  214  from OFDM circuit  104   b.    
     In block  544 , IFFT circuit  120   b  converts B 3 ′ to time-domain representation B 3 ″. 
     In block  546 , the variable ‘m’ is initialized/reset (e.g., set to zero). 
     In block  550 , B_Descriptor is set to a value that corresponds to m. For example, m may be a random seed fed to random number generator  124  or may be an index of a lookup table stored in memory  130 . 
     In block  552 , time-overlapping portions of B 3 ″ and A 2 ″ are combined resulting in signals C[1:K]. 
     In block  554 , the signals C[1:K] are combined to generate signal  507  and the PAPR of signal  507  is measured. 
     In block  556 , it is determined whether the PAPR measured in block  554  is above a determined threshold. If not, the process proceeds to block  548 , a new value of m is selected (e.g., m is incremented), and blocks  532  through  538  are repeated until the PAPR is below the threshold or a timeout. If the PAPR is below the threshold, then the process advances to block  540 . 
     In block  558 , the current value of B_Descriptor (determined in block  532 ) is used by IFFT circuit  108   a  for processing symbol B 3 . 
       FIG. 5E  is a generalized flowchart the first PAPR suppression technique for PAPR suppression in systems having two or more OFDM circuits operating in parallel. The process starts in block  560  where symbol index i is zero. 
     In block  562 , the circuit  214  waits for Symbol Si, where S is the OFDM path identifier (e.g., A or B in  FIG. 5A ). 
     In block  564 , symbol Si is received by circuit  214 . 
     In block  566 , Si is converted to time domain representation Si′. 
     In block  568 , previously-determined inversion descriptor(s) are applied to signal(s) corresponding to earlier-received symbol(s) that time-overlap symbol Si′ (if any such symbols exist). 
     In block  571 , a variable ‘m’ is initialized/reset (e.g., set to zero). 
     In block  572 , a value of S_Descriptor is set to a value corresponding to m. 
     In block  573 , the value of S_Descriptor set in block  572  is used to process Si′ to generate Si″. 
     In block  574 , Si″ is combined with the time-overlapping portions of the time-overlapping symbols (if any). The combining results in signals C[1:K]. 
     In block  576 , the signals C[1:K] are combined to generate signal  507  and the PAPR of signal  507  is measured. 
     In block  578 , it is determined whether the PAPR measured in block  576  is above a determined threshold. If not, the process proceeds to block  570 , a new value of m is selected (e.g., m is incremented), and blocks  572  through  578  are repeated until the PAPR is below the threshold or a timeout. If the PAPR is below the threshold, then the process advances to block  580 . 
     In block  580 , the current value of S_Descriptor (determined in block  572 ) is used by IFFT circuit  108   a  for processing symbol Si. 
     In block  582 , i increments and the process returns to block  562 . 
       FIG. 6A  is a diagram illustrating a second PAPR suppression technique for PAPR suppression of an example sequence of symbols generated by the transmitter of  FIG. 4 . In  FIG. 6A , symbols are buffered until all other time-overlapping symbols have been received, and then PAPR suppression is performed. Example operations using this technique are described in  FIGS. 6B and 6C . 
       FIG. 6B  is a flowchart describing operation of the second PAPR suppression technique for the symbols shown in  FIG. 6A . The process begins with block  602  in which circuit  214  receive symbol A 0  from OFDM circuit  104   a  and generates time domain representation A 0 ′ via circuit  120   a.    
     In block  604 , the circuit  214  iteratively determines a value of A_Descriptor for symbol A 0  that achieves a PAPR below a determined threshold. 
     In block  606 , the value of A_Descriptor determined in block  604  is used by circuit  108   a  for generating A 0 ″. 
     In block  608 , circuit  214  receives symbol B 1  from OFDM circuit  104   b  and generates time domain representation B 1 ′ via circuit  120   b.    
     In block  610 , circuit  214  receives symbol A 2  from OFDM circuit  104   a  and generates time domain representation A 2 ′ via circuit  120   a.    
     In block  612 , the circuit  214  iteratively determines a value of A_Descriptor for symbol A 2  that achieves a PAPR below a determined threshold. 
     In block  614 , the value of A_Descriptor determined in block  612  is used by circuit  108   a  for generating A 2 ″. 
     In block  616 , time-over-lapping portions of A 0 ″, A 2 ″, and B 1 ′ are combined. 
     In block  618 , the circuit  214  iteratively determines a value of B_Descriptor that achieves a PAPR below a determined threshold for the combination generated in block  616 . 
     In block  620 , the value of B_Descriptor determined in block  612  is used by circuit  108   b  for generating B 1 ″. 
     In block  622 , circuit  214  receives symbol B 3  from OFDM circuit  104   b  and generates time domain representation B 3 ′ via circuit  120   b.    
     In block  624 , circuit  214  receives symbol A 4  from OFDM circuit  104   a  and generates time domain representation A 4 ″ via circuit  120   a.    
     In block  626 , the circuit  214  iteratively determines a value of A_Descriptor that achieves a PAPR below a determined threshold for the symbol A 4 . 
     In block  628 , the value of A_Descriptor determined in block  626  is used by circuit  108   a  for generating A 4 ″. 
     In block  630 , time-over-lapping portions of A 2 ″, A 4 ″, and B 3 ′ are combined. 
     In block  632 , the circuit  214  iteratively determines a value of B_Descriptor that achieves a PAPR below a determined threshold for the combination generated in block  630 . 
     In block  634 , the value of B_Descriptor determined in block  632  is used by circuit  108   b  for generating B 3 ″. 
     In block  636 , circuit  214  receives symbol B 5  from OFDM circuit  104   b  and generates time domain representation B 5 ′ via circuit  120   b.    
     In block  638 , circuit  214  receives symbol A 6  from OFDM circuit  104   a  and generates time domain representation A 6 ′ via circuit  120   a.    
     In block  640 , the circuit  214  iteratively determines a value of A_Descriptor that achieves a PAPR below a determined threshold for A 6 . 
     In block  642 , the value of A_Descriptor determined in block  640  is used by circuit  108   a  for generating A 6 ″. 
     In block  644 , time-over-lapping portions of A 4 ″, A 6 ″, and B 5 ′ are combined. 
     In block  646 , the circuit  214  iteratively determines a value of B_Descriptor that achieves a PAPR below a determined threshold for the combination generated in block  644 . 
     In block  648 , the value of B_Descriptor determined in block  646  is used by circuit  108   b  for generating B 5 ″. 
       FIG. 6C  is a flowchart describing a generalized version of the second PAPR suppression technique for PAPR suppression in systems having two or more OFDM circuits operating in parallel. The process begins in block  660  when circuit  214  receives a symbol from a first of multiple OFDM circuits (e.g., from  104   a  or  104   b ). 
     In block  662 , a descriptor to sufficiently suppress PAPR of the symbol received in the most recent iteration of block  660  is determined without regard to whether any symbols from other OFDM circuit(s) overlap in time with it. The determined descriptor is then used by a respective one of multiple sub-band processing circuits to generate a PAPR-suppressed symbol. 
     In block  664 , the PAPR-suppressed symbol generated in block  662  is stored in the transmitter (e.g., in memory  130 ). 
     In block  666 , it is determined whether there are any symbols received or being received via a second of the OFDM circuits that time-overlap with the first symbol. If not, then in block  668  the PAPR suppressed symbol generated in block  664  is transmitted and the process returns to block  660 . If so, then the process advances to block  670 . 
     In block  670 , it is determined whether the time-overlapping symbol(s) have been completely received via the second of the OFDM circuits. If the time-overlapping symbols have not yet been completely received, then the process returns to block  660 . If the time-overlapping symbol(s) have been completely received, then the process advances to block  672 . 
     In block  672 , the PAPR-suppressed symbol generated in block  664  is combined with the over-lapping portions of the unsuppressed, time-overlapping symbol(s). 
     In block  674 , a descriptor to sufficiently suppress PAPR of the combination of symbols generated in block  672  is determined. The determined descriptor is then used by respective one(s) of the multiple sub-band processing circuits to generate PAPR-suppressed symbol(s). 
       FIG. 7  is a diagram illustrating an example transmitter having two OFDM circuits generating two OFDM symbol streams in parallel and suppressing total PAPR by manipulating the second OFDM symbol stream. In the transmitter of  FIG. 7 , the circuit  314  is similar to the circuit  214 , but only generates one inversion descriptor. In this regard, applying the inversion to only one of the two OFDM symbol streams may sufficiently reduce the PAPR of the signal  403  output by the combiner  402 . 
       FIG. 8A  is a diagram illustrating a third PAPR suppression technique for PAPR suppression of an example sequence of symbols generated by the transmitter of  FIG. 7 . Example operations using this technique are described in  FIG. 8B . 
       FIG. 8B  is a flowchart describing operation of the third PAPR suppression technique for the symbols shown in  FIG. 8A . The process begins in block  802  in which the circuit  214  receives symbol A 0  and converts it to time-domain representation A 0 ′. 
     In block  804 , circuit  214  receives symbol B 1  and converts it to time-domain representation B 1 ′. 
     In block  806 , circuit  214  receives symbol A 2  and converts it to time-domain representation A 2 ′. 
     In block  808 , circuit  214  combines overlapping portions of A 0 ′, A 2 ′, and B 1 ′. 
     In block  810 , circuit  214  iteratively determines a value of B_Descriptor for the symbol combination generated in block  808 . 
     In block  812 , the descriptor determined in block  810  is used to generate B 1 ″. 
     In block  814 , circuit  214  receives symbol B 3  and converts it to time-domain representation B 3 ′. 
     In block  816 , circuit  214  receives symbol A 4  and converts it to time-domain representation A 4 ′. 
     In block  818 , circuit  214  combines overlapping portions of A 2 ′, A 4 ′, and B 3 ′. 
     In block  820 , circuit  214  iteratively determines a value of B_Descriptor for the symbol combination generated in block  818 . 
     In block  822 , the descriptor determined in block  820  is used to generate B 3 ″. 
     In block  824 , circuit  214  receives symbol A 6  and converts it to time-domain representation A 6 ′. 
     In block  826 , circuit  214  receives symbol B 5  and converts it to time-domain representation B 5 ′. 
     In block  828 , circuit  214  combines overlapping portions of A 4 ′, A 6 ′, and B 5 ′. 
     In block  830 , circuit  214  iteratively determines a value of B_Descriptor for the symbol combination generated in block  828 . 
     In block  832 , the descriptor determined in block  820  is used to generate B 5 ″. 
       FIG. 9  is a diagram illustrating an example transmitter operable to perform peak to average power ratio (PAPR) suppression for single-carrier transmissions. Shown are the SoC  102 , a symbol ordering and/or inverting circuit  904 , an ordering and/or inversion descriptor generation circuit  906 , and single-carrier modulator and front-end circuit  908 . The ordering/inversion descriptor generation circuit  906  comprises a sequence generation circuit  912 , low-cost single-carrier modulator and front-end circuits  914   1 - 914   M , PAPR calculation circuit  916 , control logic  918 , and memory  920 . 
     The sequence generation circuit  903  is operable to receive N (an integer) symbols of signal  903  and generate P (an integer between 1 and S N , where S is the number of possible symbol values) sequences. The value of P for any particular implementation of transmitter  900  may be selected to balance size and power consumption and PAPR improvement (both of which increase as P increases). Each of the P sequences may be a different ordering of the N symbols, with each ordering corresponding to a particular descriptor value. Additionally, or alternatively, each of the P sequences may have a different subset of the N symbols inverted, with each combination of inverted and non-inverted symbols corresponding to a particular descriptor value. Inverting a symbol may correspond to applying a 180 degree phase shift to the symbol. In various implementations, however, a different known/deterministic phase shift may be applied to the subset of symbols that correspond to the particular descriptor to be used. In an implementation where P&lt;S N  (i.e., not every possibly sequence is tried), the P descriptor values may be chosen randomly. Alternatively, the P descriptor values may be chosen algorithmically based, for example, on characteristics of the current N symbols and/or the previous N symbols. 
     Each low-cost modulation and front-end circuit  913  may be a low-cost version of circuit  908 . For example, each front-end circuit  913  may perform the same functions as circuit  908  but with lower resolution. As another example, each front-end circuit  913  may be structurally similar to circuit  908  but with less restrictive design and performance constraints which correspond to a lower cost component. 
     The PAPR calculation circuit  907  is operable to measure the PAPR of each of sequences  915   1 - 915   P . 
     Operation of the transmitter  900  is described with reference to the flowchart of  FIG. 10 . 
     In block  1004 , after start step  1002 , N symbols are output by SOC  102  as signal  903 . 
     In block  1006 , Circuit  912  generates P sequences of the N symbols, each output as one of  913   1 - 913   L . 
     In block  1008 , each sequence output in block  1006  is processed by a respective one of circuits  914   1 - 914   P . The processing in block  1008  may include, for example, upconversion and pulse shape filtering (e.g., using a root raised cosine filter) and result in signals  915   1 - 915   P . The filters performing the filtering may be configured (e.g., initial conditions, tap coefficients, etc.) based on signal  909  from previous N symbols. In this regard, since the transmit filters have ‘memory’ (i.e., processing of current bits or symbols depends on previous bits or symbols), then prior to processing the current N symbols, the filters of the P- 1  paths which were not selected as best for the previous N symbols need to be initialized to the condition of the filter of the path that was the selected path for the previous N symbols. 
     In block  1010 , Circuit  916  measures the PAPR of each of 915 1 - 915   P  and determines  915   p  (1≦p≦P) has best the PAPR for the current N symbols. 
     In block  1012 , circuit  916  outputs, as signal  907 , the descriptor value used by  914   p  for the current N symbols. Circuit  916  also initializes the filters of each of circuits  914   1 - 914   P  to match the current state of the filter of 914 p . 
     In block  1014 , circuit  904  generates the sequence corresponding to the descriptor received as signal  907  and outputs it as signal  905 . In an example implementation, the descriptor (or some other indication of the selected sequence) may be inserted into the transmission and/or transmitted via a control channel for use by a receiver. 
     In block  1016 , circuit  908  modulates the signal  905  onto a carrier and outputs the modulated signal onto a channel via a pulse shaping filter (e.g., a root raise cosine filter). 
     In accordance with various example implementations of this disclosure, a transmitter (e.g.,  100  or  900 ) may processing a to-be-transmitted signal (e.g.,  105  or  903 ) using a first value of a descriptor to generate a first processed signal (e.g.,  915   1  of  FIG. 9  or the result of a block  214  for m=1 in  FIG. 2 ), and may process the to-be-transmitted signal using a second value of the descriptor to generate a second processed signal (e.g.,  915   2  in  FIG. 9  or the result of a block  214  for m=1 in  FIG. 2 ). The transmitter may determine (e.g., via circuit  128  or  916 ) a peak-to-average-power ratio (PAPR) of the first processed signal and a PAPR of the second processed signal. The transmitter may select the first value of the descriptor for transmitting the to-be-transmitted signal if the PAPR of the first processed signal is less than the PAPR of the second processed signal, and select the second value of the descriptor for transmitting the to-be-transmitted signal if the PAPR of the second processed signal is less than the PAPR of the first processed signal. The processing of the to-be-transmitted signal (e.g., in circuit  906 ) using the first value of the descriptor may comprises re-ordering symbols of the to-be-transmitted signal according to the first value of the descriptor. The processing of the to-be-transmitted signal (e.g., in circuit  906 ) using the second value of the descriptor may comprise re-ordering symbols of the to-be-transmitted signal according to the second value of the descriptor. The processing of the to-be-transmitted signal (e.g., in circuit  114  or  906 ) using the first value of the descriptor may comprise inverting symbols of the to-be-transmitted signal according to the first value of the descriptor. The processing of the to-be-transmitted signal (e.g., in circuit  114  or  906 ) using the second value of the descriptor may comprise inverting symbols of the to-be-transmitted signal according to the second value of the descriptor. 
     Other embodiments of the invention may provide a non-transitory computer readable medium and/or storage medium, and/or a non-transitory machine readable medium and/or storage medium, having stored thereon, a machine code and/or a computer program having at least one code section executable by a machine and/or a computer, thereby causing the machine and/or computer to perform the processes as described herein. 
     Accordingly, the present invention may be realized in hardware, software, or a combination of hardware and software. The present invention may be realized in a centralized fashion in at least one computing system, or in a distributed fashion where different elements are spread across several interconnected computing systems. Any kind of computing system or other apparatus adapted for carrying out the methods described herein is suited. A typical combination of hardware and software may be a general-purpose computing system with a program or other code that, when being loaded and executed, controls the computing system such that it carries out the methods described herein. Another typical implementation may comprise an application specific integrated circuit or chip. 
     The present invention may also be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein, and which when loaded in a computer system is able to carry out these methods. Computer program in the present context means any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following: a) conversion to another language, code or notation; b) reproduction in a different material form. 
     While the present invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present invention without departing from its scope. Therefore, it is intended that the present invention not be limited to the particular embodiment disclosed, but that the present invention will include all embodiments falling within the scope of the appended claims.