Abstract:
An apparatus and method is presented for a DRAM memory cell array exhibiting improved alignment tolerance for bit line contact formation and utilizing closely-spaced double-sided stacked capacitors for increased overall feature density on the circuit die. The use of a sacrificial insulating layer, an etch-stop insulating layer, and insulating spacers surrounding the bit line contact plug permits wet etching of the sacrificial layer to enable double-sided capacitors to be formed close together. In the resulting structure, only the bit line contact plug and insulating sidewall spacers separates adjacent capacitors and hence DRAM cells can be more tightly packed on the circuit die. Another aspect of the invention is improved alignment tolerance of the bit line contact plug. Because the bit line contact plug is formed prior to the double-sided capacitors, and then the double sided capacitors are formed to occupy all of the space laterally surrounding the bit line contact plug and its insulating spacers, mask alignment errors are less likely to affect this arrangement.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of The Invention  
           [0002]    The present invention relates to the field of integrated circuits and, more particularly, to an apparatus and method of forming a DRAM cell array with a reduced overall stack height and better alignment tolerance between DRAM container cells and bit line contacts.  
           [0003]    2. Description of The Related Art  
           [0004]    Modern integrated circuit designers often must confront and solve the problem of space limitations on the circuit die. Because the use and popularity of memory devices, such as dynamic random access memory (DRAM) circuits, has expanded dramatically in recent years, memory circuit manufacturers have been under pressure to increase memory capacity and performance without increasing the space occupied by the circuit.  
           [0005]    For example, DRAM memory circuits are manufactured by replicating millions of identical circuit elements, known as DRAM cells, on a single semiconductor wafer. A DRAM cell is an addressable location that can store one bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit components: a storage capacitor and an access field effect transistor.  
           [0006]    [0006]FIG. 10 illustrates a portion of a DRAM memory circuit containing two neighboring DRAM cells  100 . For each cell, one plate of the storage capacitor  140  is connected to a reference voltage and the other plate is connected to the drain of the access field effect transistor  120 . The gate of the access field effect transistor  120  is connected to the word line  180 . The source of the field effect transistor  120  is connected to the bit line  160 . The word line thus controls access to the storage capacitor  140  by allowing or preventing the logic signal (“0” or “1”) on the bit line  160  to be written to or read from the storage capacitor  140 .  
           [0007]    The manufacturing of a DRAM cell includes the fabrication of a transistor, a capacitor, and contacts to the bit line, the word line, and the reference voltage. DRAM manufacturing is a highly competitive business. There is continuous pressure to decrease the size of individual cells and increase memory cell density to allow more memory to be squeezed onto a single memory chip. However, it is necessary to maintain a sufficiently high storage capacitance to maintain a charge at the refresh rates currently in use even as cell size continues to shrink. This requirement has led DRAM manufacturers to turn to three dimensional capacitor designs, including stacked capacitors. Stacked capacitors are capacitors which are stacked, or placed, over the access transistor in a semiconductor device. For reasons including ease of fabrication and increased capacitance) most manufacturers of DRAMs larger than 4 Megabits use stacked capacitors. Therefore, the invention will be discussed in connection with stacked capacitors but should not be understood to be limited thereto. For example, use of the invention in trench or planar capacitors is also possible.  
           [0008]    One widely used type of stacked capacitor is known as a container capacitor, shown in FIG. 11. One embodiment of a container capacitor is shaped like an upstanding tube (cylinder) having an oval or circular cross section. FIG. 11 illustrates a top view of a portion of a DRAM memory circuit from which the upper layers have been removed to reveal container capacitors  114  arranged around a bit line contact  62 . Six container capacitors are shown in FIG. 11, each of which has been labeled with separate reference designations A to F.  
           [0009]    To increase density, the bit line contact  62  is shared by neighboring container capacitors  114 , including those labeled A and B. The wall of each container capacitor consists of two plates  82 ,  94  of conductive material such as doped polycrystalline silicon (referred to herein as polysilicon or poly) separated by a dielectric layer  92 . The bottom end of the tube is closed, with the inner wall (lower plate  82 ) in contact with either the drain of the access transistor or a plug which itself is in contact with the drain. The other end of the tube is open (the tube is filled with an insulative material  102  later in the fabrication process). The sidewall and closed end of the tube form a container; hence the name “container capacitor.” 
           [0010]    The container capacitors in FIG. 11 are double-sided, meaning the lower plate  82  is surrounded on two sides by the upper plate  94 , which is connected to a reference voltage on the periphery (not shown). The use of double-sided capacitors further increases the storage capacitance of the DRAM memory cell, reducing the required depth of the container, but their use requires more lateral space for the second side of the upper plate. Lateral space is at a premium due to the need to increase circuit density while preserving isolation of the capacitor plates from the bit line contact. It would be desirable to develop a technique which improves alignment tolerance of the bit line contacts so that double-sided container capacitors could be squeezed closer together.  
           [0011]    Additional space savings on the circuit die are required in order to satisfy the demand on DRAM manufacturers for increased capacity memory circuits. In order to remain competitive, DRAM manufacturers need a circuit design that conserves space on the circuit die but does not require unusually expensive or unconventional processing techniques. Therefore, there is a strong need for an increased-density stacked capacitor memory array design exhibiting improved alignment tolerance, utilizing three-dimensional double-sided capacitors and capable of formation by conventional wafer processing and manufacturing techniques.  
         SUMMARY OF THE INVENTION  
         [0012]    The present invention provides an apparatus and method of forming a DRAM memory cell array exhibiting improved alignment tolerance for bit line contact formation and utilizing closely-spaced double-sided stacked capacitors for increased overall feature density on the circuit die.  
           [0013]    The above and other features and advantages of the invention are achieved by providing a method of forming a semiconductor device including:  
           [0014]    (a) forming an insulating layer on a semiconductor assembly composed of a plurality of gates and a plurality of conductive plugs formed between the gates;  
           [0015]    (b) etching a plurality of holes or contact openings in the insulating layer to expose only selected plugs (‘bit-line plugs’);  
           [0016]    (c) forming insulating spacers on the sidewalls of the contact openings;  
           [0017]    (d) forming conductive bit line contact plugs in the contact openings between the insulating spacers;  
           [0018]    (e) etching additional contact openings in the insulating layer laterally adjacent the bit line contact plugs and forming double-sided capacitors in the additional contact openings, removing the remainder of the insulating layer with wet etch techniques during capacitor formation; and  
           [0019]    (f) forming a conductive bit line in contact with the bit line contact plugs.  
           [0020]    In the present invention, the use of insulating spacers surrounding the bit line contact plug, and a wet etch that selectively stops at those spacers, permits the double-sided capacitors to be formed close together. Only the previously-formed bit line plug and insulating sidewall spacers separates adjacent capacitors from the bit line contact and hence DRAM cells can be more tightly packed on the circuit die.  
           [0021]    Another aspect of the invention is improved alignment tolerance of the bit line contact plug. Because the bit line contact plug is formed prior to the double-sided capacitors, and then the double sided capacitors are formed to occupy all of the space laterally surrounding the bit line contact plug and its insulating spacers, mask alignment errors that plagued prior art devices (with after-formed bit line contact plugs) are less likely to affect this arrangement.  
           [0022]    Furthermore, the present invention provides these and other advantages solely using processing techniques conventionally employed in the manufacture of semiconductor devices. No unusually expensive or cumbersome steps are required in the method of the present invention, resulting in improved device performance without substantially increased cost. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0023]    The foregoing and other advantages and features of the invention will become more apparent from the detailed description of the preferred embodiments of the invention given below with reference to the accompanying drawings in which:  
         [0024]    [0024]FIG. 1 is a fragmentary vertical cross-sectional view of a DRAM cell array formed in accordance with the present invention at an early stage of formation;  
         [0025]    [0025]FIG. 2 is a fragmentary vertical cross sectional view of the array of FIG. 1 at a later stage of formation;  
         [0026]    [0026]FIG. 3 is a fragmentary vertical cross sectional view of the array of FIG. 2 at a later stage of formation;  
         [0027]    [0027]FIG. 4 is a fragmentary vertical cross sectional view of the array of FIG. 3 at a later stage of formation;  
         [0028]    [0028]FIG. 5 is a fragmentary vertical cross sectional view of the array of FIG. 4 at a later stage of formation;  
         [0029]    [0029]FIG. 6 is a fragmentary vertical cross sectional view of the array of FIG. 5 at a later stage of formation;  
         [0030]    [0030]FIG. 7 is a fragmentary vertical cross sectional view of the array of FIG. 6 at a later stage of formation;  
         [0031]    [0031]FIG. 8 is a fragmentary vertical cross sectional view of the array of FIG. 7 at a later stage of formation;  
         [0032]    [0032]FIG. 9 is a fragmentary vertical cross sectional view of the array of FIG. 8 at a later stage of formation;  
         [0033]    [0033]FIG. 10 is a fragmentary schematic diagram of a DRAM circuit topology formed in accordance with the present invention;  
         [0034]    [0034]FIG. 11 is fragmentary top view of a DRAM cell array formed in accordance with the present invention; and  
         [0035]    [0035]FIG. 12 is a processor-based system including a semiconductor device formed in accordance with the present invention.  
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0036]    DRAM memory circuits are currently the most popular type of memory circuit used in the main memory of processor-based systems. Therefore, the invention will be discussed in connection with DRAM memory circuits. However, the invention has broader applicability and is not limited to DRAM memory circuits. It may be used in any other type of memory circuit, such as an SRAM (static random access memory), as well as in any other circuit in which electrical contacts are formed in close proximity to, and intended to be insulated from, other circuit devices.  
         [0037]    Also, the terms “wafer” and “substrate” are used interchangeably and are to be understood as including silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a “wafer” or “substrate” in the following description, previous process steps may have been utilized to form regions or junctions in the base semiconductor structure or foundation.  
         [0038]    No particular order is required for the method steps described below, with the exception of those logically requiring the results of prior steps, for example, in FIG. 3, formation of insulating spacers  54  on the sidewalls of bit line contact via  56  logically requires the prior formation of the bit line contact via  56 . Otherwise, enumerated steps are provided below in an exemplary order which may be altered, for example, in FIG. 2, formation of gate structures  14  and plugs  34 ,  38  may be rearranged using masking and etching steps as is known in the art.  
         [0039]    [0039]FIG. 1 shows a DRAM cell array  10  at an early stage of formation. The method of the present invention commences with the formation of gate structures  14  on substrate  12 . Each gate structure  14  includes gate oxide layer  18 , access gate  22 , sidewall spacers  16  and gate top insulator  24 . FIG. 1 shows four identical gate structures  14  with an area adjacent and between each pair of gate structures  14  in which the substrate  12  is exposed.  
         [0040]    Substrate  12  and gate structures  14  are formed using techniques well known in the art, including material deposition, masking, etching, doping, or any combination of these or other known techniques. Also, the material composition of the substrate  12  and gate structures  14  are not limited to any particular combination, and may be formed from a wide variety of materials known in the art. For instance, the access gate  22  may be formed from conductive polysilicon, the gate oxide layer  18  and sidewall spacers  16  may be formed from an oxide of silicon or silicon nitride, gate top insulator  24  may be formed from silicon nitride or tetraethylorthosilicate (TEOS), and substrate  12  may be formed from a single-crystal silicon wafer.  
         [0041]    Referring to FIG. 2, the method continues with the deposition of a first thick insulating layer  32  on the gate structures  14  and substrate  12 . This is followed by chemical/mechanical planarization (CMP) of the insulating layer  32  and deposition on it of a first etch-stop insulating layer  36 . Photolithographic techniques well known in the art are then used to define and etch first vias in the insulating layers  32 ,  36  to expose the surface of the substrate  12  between the gate structures  14 . Conductive plugs are formed in the first vias to produce cell plugs  34  and bit line plug  38  in electrical contact with the substrate  12 . A CMP step is again used to planarize and remove excess conductive plug material. The resulting structure at this stage is shown in FIG. 2.  
         [0042]    First thick insulating layer  32  is preferably formed from borophosphosilicate glass (BPSG), and first etch-stop insulating layer  36  is preferably formed from Si 3 N 4  (silicon nitride). However, any combination of insulating materials known in the art to permit selective etching of layer  32  with etch-stop at layer  36  may be used. Also, conductive plugs  34 ,  38  are preferably formed from polysilicon doped with impurities to enhance conductivity, but may be formed from any conductive material compatible with later processing steps.  
         [0043]    Referring to FIG. 3, a second thick insulating layer  52  is formed on the planarized etch-stop insulating layer  36  and plugs  34 ,  38 , and a bit line contact via  56  is patterned and etched in the insulating layer  52 . Insulating spacers  54 , also known as insulated sidewalls  54 , are then formed by depositing an insulating material (different from the material of insulating layer  52 ) and etching it back to form spacers  54  on the sidewalls of bit line contact via  56 .  
         [0044]    Second thick insulating layer  52  is preferably formed from BPSG, and insulating spacers  54  are preferably formed from silicon nitride, although any combination of materials for which insulating spacers  54  act as an etch-stop for wet-etching of insulating layer  52  may be used.  
         [0045]    Referring to FIG. 4, the method of the present invention continues with formation of the bit line contact plug  62  in bit line contact via  56  between insulating spacers  54 . Bit line contact plug  62  is preferably formed from conductively-doped polysilicon (poly), although tungsten (W) may also be used, depending on processing-steps subsequent to the method of the present invention and well known in the art which may require the use of either W or poly. A CMP or etch step may be used at this point to remove excess conductive material and obtain a planar surface of insulating layer  52 .  
         [0046]    Referring to FIG. 5, container cell vias  72  are patterned and etched in second thick insulating layer  52  in areas laterally adjacent said bit line contact plug  62 . Container cell vias  72  must be formed deep enough to expose cell plugs  34 ., but not so wide as to remove insulating spacers  54 .  
         [0047]    Referring to FIG. 6, the method continues with the formation of lower capacitor plates  82  in container cell vias  72 . Lower capacitor plates  82  may be deposited or grown according to techniques of formation known in the art. Lower capacitor plates  82  are preferably formed from conductively-doped polysilicon, but may be formed from any conductive material compatible with later processing steps. A CMP or etch step is used at this point to remove excess conductive material from insulating layer  52  and bit line contact plug  62 .  
         [0048]    Referring to FIG. 7, the method of the present invention continues with wet etching of second thick insulating layer  52 . This wet etch step is so conducted as to selectively stop at first etch-stop insulating layer  36 , insulating spacers  54 , and bit line contact plug  62 . By wet-etching and selectively stopping at layer  36 , spacers  54  and bit line contact plug  62 , insulating layer  52  can be entirely removed, in particular from the tight areas between insulating spacers  54  and lower capacitor plates  82  on either side of bit line contact plug  62 . Insulating layer  52  is thus used as a sacrificial layer.  
         [0049]    Referring to FIG. 8, the method continues with the formation of thin dielectric layer  92  on lower capacitor plates  82 , followed by formation of upper capacitor plates  94  on dielectric layer  92 . Upper capacitor plates  94  are electrically connected in the periphery (not shown) to reference voltage Vr, as depicted in FIG. 10. In particular, the upper plates  94  and dielectric layer  92  are formed in the tight areas between the lower plates  82  and the insulating spacers  54  such that only the spacers  54  and the dielectric layer  92  separates the upper plates  94  from the bit line contact plug  62 . Also, as shown in FIG. 8, only the spacer  54 , dielectric layer  92  and the upper plate  94  separates the bit line contact plug  62  from the lower plate  82 . This arrangement allows the DRAM circuit elements to be squeezed much closer together, saving space on the integrated circuit die.  
         [0050]    Still referring to FIG. 8, the area over the bit line contact plug  62  is then patterned and the upper capacitor plate and dielectric layer  92  etched to expose contact plug  62  and prevent a short circuit between the capacitor components (plates  82 ,  94  and dielectric layer  92 ) and the bit line contact plug. The portion etched is shown as etch region  122  in FIG. 11.  
         [0051]    Dielectric layer  92  is preferably formed from a nitride film using rapid thermal nitridation (RTN), although various other methods and materials may be used as is known in the art. Upper capacitor plates  94  may be deposited or grown according to techniques of formation known in the art and are preferably formed from conductively-doped polysilicon, but may be formed from any conductive material compatible with later processing steps.  
         [0052]    Referring to FIG. 9, a third thick insulating layer  102  is formed on at least upper capacitor plate  94  and bit line contact plug  62 . A CMP or etch may be used to planarize the array  10 . Then a bit line contact via is patterned and etched in insulating layer  102  and bit line contact  106  is formed in the via. A bit line  104  may be formed concurrently or during later processing steps for electrical connection in the periphery to adjacent devices (not shown).  
         [0053]    Third thick insulating layer  102  is preferably deposited BPSG, but other insulating materials and methods of formation may be used as is known in the art. The bit line contact  106  and bit line  104  are preferably formed from metal deposited concurrently, but may be formed from other conductive materials using various methods. In FIG. 9, section lines “XI-XI” designate the cross-section for which FIG. 11 shows a top view.  
         [0054]    Likewise, section lines “IX-IX” in FIG. 11 designate the cross section for which FIG. 9 shows a side view. FIG. 11 illustrates six adjacent container capacitors  114 , labeled A-F. The memory cells with capacitors labeled A and B are each accessed through bit line contact plug  62 . Each container capacitor  114  is an oval-shaped, double-sided capacitor and includes upper plate  94  on two sides of lower plate  82 , the plates  94 ,  82  being separated by thin dielectric layer  92 . In the middle of each capacitor  114  is a portion of third thick insulating layer  102 .  
         [0055]    As shown in FIG. 11, bit line contact plug  62  is formed within and surrounded by insulating spacer  54 . Etch region  122  is also shown illustrating the portion of upper plate  94  and dielectric layer  92  removed to expose bit line contact plug  62  for later electrical connection to the bit line  104  (see FIG. 8 and accompanying text).  
         [0056]    It is important to understand that upper capacitor plate  94 , like the rest of each container cell  114 , is three-dimensional. Although in FIG. 9 it appears that a portion of upper plate  94  is not electrically connected to the remainder of upper plate  94 , it is shown in FIG. 11 that only a small portion of upper plate  94  is removed in an area proximate to the bit line contact plug  62 . The portion of upper plate  94  in question is shown double hatched in FIG. 11 for container cell A. The portion of upper plate  94  shown disconnected in FIG. 9 is actually connected in the three-dimensional pathway extending along the outside perimeter of upper plate  94 , shown hatched in FIG. 11 for container cell A.  
         [0057]    [0057]FIG. 11 illustrates how the method of the present invention permits upper capacitor plates  94  to be formed immediately adjacent insulating spacers  54  formed on the sidewalls surrounding bit line contact plug  62 . This arrangement permits circuit features to be formed closer together, conserving space on the circuit die. In addition, double-sided capacitors are formed, reducing the depth required to form container cells of a given capacitance and resulting in a decrease of the overall stack depth.  
         [0058]    [0058]FIG. 12 illustrates a processor-based system  200 , e.g. a computer system, according to one embodiment of the present invention. The processor-based system  200  comprises a CPU (central processing unit)  204 , a memory circuit  206 , and an I/O (input/output) device  202 . The memory circuit  206  contains a DRAM memory circuit including semiconductor devices constructed in accordance with the present invention. Memory other than DRAM may be used. Also, the CPU  204  may itself be an integrated processor which utilizes semiconductor devices constructed in accordance with the present invention, and both processor  204  and memory circuit  206  may be integrated on a single circuit chip.  
         [0059]    While the invention has been described in detail in connection with the preferred embodiments known at the time, it should be readily understood that the invention is not limited to such disclosed embodiments. Rather, the invention can be modified to incorporate any number of variations, alterations, substitutions or equivalent arrangements not heretofore described, but which are commensurate with the spirit and scope of the invention. Accordingly, the invention is not to be seen as limited by the foregoing description, but is only limited by the scope of the appended claims.