Abstract:
A laterally-diffused metal oxide semiconductor (LDMOS) device and method of manufacturing the same are provided. The LDMOS device can include a drift region, a source region and a drain region spaced a predetermined interval apart from each other in the drift region, a field insulating layer formed in the drift region between the source region and the drain region, and a first P-TOP region formed under the field insulating layer. The LDMOS device can further include a gate polysilicon covering a portion of the field insulating layer, a gate electrode formed on the gate polysilicon, and a contact line penetrating the gate electrode, the gate polysilicon, and the field insulating layer.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the benefit under 35 U.S.C. §119 of Korean Patent Application No. 10-2013-0026150, filed Mar. 12, 2013, which is hereby incorporated by reference in its entirety. 
     BACKGROUND 
     A laterally-diffused metal oxide semiconductor (LDMOS) transistor is a power device for high voltage, which has fast switching speed, high input impedance, low power consumption, and compatibility with a complementary metal oxide semiconductor (CMOS) process. Such a transistor is widely used for various power devices, including display driving integrated circuits (ICs), power converters, motor controllers, and power devices for cars. In the case of a power device, on-resistance (R on ) and breakdown voltage are important factors that have a significant impact on the performance of the device. Various techniques to maintain R on  and increase breakdown simultaneously have been suggested. 
     An LDMOS device can be used as a power device to drive a light-emitting diode (LED) device. In order to do so, it should maintain high breakdown and have low R on  simultaneously. To accomplish this, it is necessary to apply a Double Reduced Surface Field (RESULF) stacking a PTOP layer to a high voltage N WELL (HVNWELL). 
       FIG. 1  is a layout view of a general semiconductor device, for example, an LDMOS device.  FIG. 2  is a cross-sectional view taken along line A-A′ of  FIG. 1  in the case of a related art power semiconductor device. 
     Referring to  FIG. 2 , a configuration of a related art LDMOS transistor includes an N-type doped deep well  2  and a P-type doped deep P well  3  in a P-type doped semiconductor substrate  1 . A field insulating layer  42  having length W is formed on the surface of the N well  2 , an N well  5  is formed in an open region at one side of the field insulating layer  42 , and a drain region  24  doped with a high concentration N+ impurity is formed in the surface of the N well  5 . A first P-TOP region  25  is formed in the deep N well  2  to form a RESULF structure. 
     Also, a P well  4  including inside portions of the deep P well  3  and the deep N well  2  is formed, and a second P-TOP region  12  including inside portions of the P well  4  and the deep N well  2  is formed. A source contact region  14  doped with a high concentration P+ impurity is formed in the surface of the second P-TOP region  12 , and then, a source region  13  doped with a high concentration N+ impurity is formed in the second P-TOP region  12  adjacent to the source contact region  14 . Then, a gate polysilicon  30  covering portions of the second P-TOP region  12  and the field insulating layer  42  is formed, and the gate polysilicon  30  is connected to an upper gate electrode  15  through wiring. 
     In an LDMOS device including a floating first P-TOP region of such a structure, since charges (i.e., electrons and holes) moved by an electric field are accumulated in the first P-TOP region, breakdown voltage decreases, so that it is necessary to change into a P-TOP structure that can be grounded in order to provide manufacturing process stability. 
       FIG. 3  is a cross-sectional view of an LDMOS device having a grounded P-TOP structure. 
     Referring to  FIG. 3 , the pitch of the first P-TOP region  25  is increased by a predetermined length, compared to that of the device shown in  FIG. 2 . Also, a high concentration P+ conductive connection region  18  is formed on the top surface of the increased first P-TOP region  25  to be connected to an upper ground line  19 , and an extended gate polysilicon  30   a  and a gate electrode  15   a  are additionally formed. 
     In order to form the above structure, an additional space for expanding an existing gate poly is required. This increases a half pitch of a PTOP region and thus R on  increases. Therefore, the operating characteristics of an LDMOS device are affected. 
     BRIEF SUMMARY 
     Embodiments of the subject invention provide a semiconductor device, and a method of fabricating the same, with a structure that maintains high breakdown voltage without increasing a pitch compared to a related art semiconductor device and allows a P-TOP region to be grounded. 
     In an embodiment, a laterally-diffused metal oxide semiconductor (LDMOS) device can include: a drift region; a source region and a drain region spaced a predetermined interval apart from each other in the drift region; a field insulating layer formed in the drift region between the source region and the drain region; a first P-TOP region formed under the field insulating layer; a gate polysilicon covering a portion of the field insulating layer, a gate electrode formed on the gate polysilicon; and a contact line penetrating the gate electrode, the gate polysilicon, and the field insulating layer. 
     In another embodiment, a method of fabricating an LDMOS device can include: forming a drift region; forming a source region and a drain region, which are spaced a predetermined interval apart from each other, in the drift region; forming a first P-TOP region by ion-implanting a second conductive high concentration impurity in the drift region; forming a field insulating layer on the first P-TOP region; forming a gate polysilicon covering a portion of the field insulating layer; forming a source electrode, a drain electrode, and a gate electrode, which are connected to the source region, the drain region, and the gate polysilicon, respectively; forming a contact line by etching the gate electrode, the gate polysilicon, and the field insulating layer; and forming a high concentration second conductive connection region in a surface of the first P-TOP region exposed to the field insulating layer after the etching process. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a plan view of a semiconductor device including a laterally-diffused metal oxide semiconductor (LDMOS) device. 
         FIG. 2  is a cross-sectional view taken along line A-A′ of  FIG. 1  according to a related art device. 
         FIG. 3  is a cross-sectional view taken along line A-A′ of  FIG. 1  according to a related art device. 
         FIG. 4  is a cross-sectional view taken along line A-A′ of  FIG. 1  according to an embodiment of the subject invention. 
         FIG. 5  is a plan view of region B of  FIG. 1  according to an embodiment of the subject invention. 
         FIG. 6  is a plan view of region C of  FIG. 5 . 
     
    
    
     DETAILED DESCRIPTION 
     Reference will now be made in detail to the embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. 
     When the terms “on” or “over” are used herein, when referring to layers, regions, patterns, or structures, it is understood that the layer, region, pattern, or structure can be directly on another layer or structure, or intervening layers, regions, patterns, or structures may also be present. When the terms “under” or “below” are used herein, when referring to layers, regions, patterns, or structures, it is understood that the layer, region, pattern, or structure can be directly under the other layer or structure, or intervening layers, regions, patterns, or structures may also be present. 
       FIG. 4  is a cross-sectional view taken along line A-A′ of  FIG. 1  according to an embodiment of the present invention. 
     Referring to  FIG. 4 , a configuration of a laterally-diffused metal oxide semiconductor (LDMOS) transistor can include an N-type doped deep well  2  and a P-type doped deep P well  3  in a P-type doped semiconductor substrate  1 . Though a P-type semiconductor is shown for exemplary purposes, embodiments are not limited thereto. For example, an N-type semiconductor substrate can be used. A field insulating layer  42  can be formed on the surface of the N well  2 . In an embodiment, a local oxidation of silicon (LOCOS) process can be used to form the field insulating layer  42 , though embodiments are not limited thereto. An N well  5  can be formed in an open region at one side of the field insulating layer  42 , and a drain region  24  (e.g., doped with a high concentration N+ impurity) can be formed in the surface of the N well  5 . 
     A first P-TOP region  25  can be formed in the deep N well  2 . Oxidation heat (e.g., during a LOCOS process for forming the field insulating layer  42 ) can cause the first P-TOP region  42  to diffuse below the field insulating layer  42 . 
     A P well  4  can be formed and can include inside portions of the deep P well  3  and the deep N well  2 . A second P-TOP region  12  can be formed and can include inside portions of the P well  4  and the deep N well  2 . A source contact region  14  (e.g., doped with a high concentration P+ impurity) can be formed in the surface of the second P-TOP region  12 , and a source region  13  (e.g., doped with a high concentration N+ impurity) can be formed in the second P-TOP region  12  adjacent to the source contact region  14 . In an embodiment, the source region  13  can be formed after the source contact region  14  is formed. 
     The source region  13  and the drain region  24  can be separated at both sides by the field insulating layer  42 . A portion adjacent to the source region  13  and overlapping a gate insulating layer and a gate polysilicon  30  in a top region of the second P-TOP region  12  can become a channel region. 
     In an embodiment, the gate insulating layer and the gate polysilicon  30  can be sequentially stacked on the channel region, and the source region  13  and the drain region  24  can be electrically connected to the source electrode  20  and the drain electrode  21 , respectively (e.g., through wiring). The gate polysilicon  30  can be connected to the gate electrode  15  (e.g., through wiring). 
     The first P-TOP region  25  can be a region allowing a double reduced surface field (RESULF) effect, where electrons and holes moved by an electric field can be accumulated to reduce breakdown voltage. 
     Thus, according to embodiments of the present invention, a semiconductor device can maintain high breakdown voltage and obtain manufacturing stability by grounding the first P-TOP region  25  to remove accumulated electrons or holes without increasing the length W of the field insulating layer compared to the related art LDMOS transistor shown in  FIG. 2 . 
     Referring again to  FIG. 4 , in an embodiment, in order to expose the first P-TOP region  42 , a process for etching the field insulating layer  42 , the gate polysilicon  30 , and the gate electrode  15  on the top can be performed. A hard mask pattern (not shown) can be formed on the gate electrode  15 , and the gate electrode  15 , the gate polysilicon  30 , and the field insulating layer  42  can be sequentially etched along the hard mask pattern, so as to expose the field insulating layer  42 . 
     A contact line  17  can be formed by sequentially etching the gate electrode  15 , the gate polysilicon  30 , and the field insulating layer  42 . The contact line  17  can penetrate the gate electrode  15 , the gate polysilicon  30 , and the field insulating layer  42 . A high concentration second conductive connection region  18  (e.g., doped with a high concentration of impurities of a second conducive type) can be formed on the exposed surface of the first P-TOP region  25 . The high concentration second conductive connection region  18  can be formed after the contact line is formed. The high concentration second conductive connection region  18  can be connected to a ground line  19  through the exposed contact line  17  to be grounded. The specific form of the contact line  17  shown in  FIG. 4  is for exemplary purposes, and embodiments are not limited thereto. 
       FIG. 5  is a plan view illustrating a layout of region B in the semiconductor device of  FIG. 1 . 
     Referring to  FIG. 5 , first P-TOP regions  25  can be symmetric to each other based on a source region. A bar type contact line  17  can be formed in a gate polysilicon  30  covering one side of the first P-TOP region  25 . 
     The contact line  17  can be obtained by etching a region where the field insulating layer  42  and the gate polysilicon  30  are stacked together, and can be formed with various layouts during a process for forming a hard mask pattern. 
       FIG. 6  is a plan view of region C of  FIG. 5 . 
     Referring to  FIG. 6 , the first P-TOP region  25 , the field insulating layer  42 , the gate polysilicon  30 , the gate electrode  18 , and a source region can be stacked. In an embodiment, the high concentration second conductive connection region  18  in the first P-TOP region  25  can be formed by etching the field insulating layer  42  having the gate polysilicon  30 . 
     The high concentration second conductive connection region  18  can be connected to a wire through a contact line. The wire can be connected to an upper ground line to form a structure in which the first P-TOP region  25  is grounded. In an embodiment, the form of the contact line  17  can include bar type regions  17   a  and  17   b , and each bar type region  17   a  and  17   b  can include a plurality of wires. Though such a configuration is shown for exemplary purposes, embodiments are not limited thereto. For example, each contact line for one wire connection can be formed. That is, the contact line  17  can be formed with a plurality of hole types. 
     Though components have been described as P-type, N-type, N+, and P+, embodiments are not limited thereto. For example, each N well or deep N well can be P well or deep P well, respectively, and vice versa. 
     According to embodiments of the present invention, an LDMOS device can be manufactured such that a P-TOP region is grounded without an additional process and without increasing the pitch of a semiconductor device. 
     Additionally, due to no increase of a pitch of a semiconductor device, the LDMOS device can be used for a power device, maintaining high breakdown voltage without increasing on-resistance (R on ). 
     Although embodiments have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. More particularly, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art. 
     Any reference in this specification to “one embodiment,” “an embodiment,” “example embodiment,” etc., means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with any embodiment, it is submitted that it is within the purview of one skilled in the art to effect such feature, structure, or characteristic in connection with other ones of the embodiments.