Abstract:
In order to reduce the effects of discontinuities at the edge of a picture and reduce erosion of the usable picture area caused by a filtering or interpolation operation, the edges of the picture are extrapolated prior to such an operation. This may be achieved by a circuit which receives an input line of active pixel data; forms from the input line a delayed line of the active pixel data; produces at least one additional start pixel data derived from a pixel data at or adjacent the start of the input line; produces at least one additional end pixel data derived from a pixel data at or adjacent the end of the input line; and forms an output sequence of pixel data by selecting for the output sequence the additional start pixel data, then at least part of the delayed line, and then the additional end pixel data. This circuit therefore performs zero-order (repeat) extrapolation at the beginning and end of each line. Other circuits are also described for extrapolating lines at or adjacent the start and end of each frame, and for performing a first- or higher-order extrapolation.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to digital video signal processing and in particular to an apparatus and to a method for processing a digital video signal. 
     2. Description of the Prior Art 
     Video processing operations such as filtering and interpolation use the values of a plurality, for example a patch, of input pixels to form an output pixel value. For example, a simple 4×4 `area filter` generates the value of an output pixel by averaging the values of the input pixels in a 4×4 patch. At the edges of a picture, there is normally a sharp transition from, or into, blanking at black level. This is usually a highly aliased transition, which causes filters, interpolators and the like to `ring` and produce strange effects at the edge of the picture. Even if the profile of the edge transition is anti-aliased, for example with a transition over say 3 to 5 pixels, so as to try to prevent ringing, there will still be a spread of the edge effects which will erode the usable picture area. 
     The active acquisition area of a high-definition SMPTE 240M standard digital video frame is 1920 pixels (horizontally) by 1035 pixels (vertically), but in view of the above-mentioned problems some have recommended that the usable production and distribution area of the frame should be cropped so that the production and distribution area is reduced to, say, 1888 pixels by 1017 pixels. (Although embodiments of the invention will be described below in relation to one type of high-definition video signal, it should be noted that the invention is equally applicable to other high-definition and to conventional-definition signals.) 
     OBJECT AND SUMMARY OF THE INVENTION 
     An object of the present invention is to reduce the effects of discontinuities at the edge of the picture and reduce erosion of the usable picture area, preferably so that a production and distribution picture area can be used which is the same pixel size as the acquisition picture area. 
     In accordance with one aspect of the present invention, there is provided an apparatus for processing a digital video signal, comprising: (a) means for receiving an input sequence of units of active pixel data; (b) means for forming from the input sequence a delayed sequence of units of the active pixel data; (c) means for producing at least one additional start pixel data unit derived from at least one unit at or adjacent the start of the input sequence; (d) means for producing at least one additional end pixel data unit derived from at least one unit at or adjacent the end of the input sequence; and (e) control means for forming an output sequence of pixel data units by selecting for the output sequence the additional start pixel data unit(s), then at least part of the delayed sequence, and then the additional end pixel data unit(s). Thus, as a simple example, the apparatus can be considered as extending the picture into the blanking area. Consequently, the extended picture can be processed, for example filtered or interpolated, with any undesirable edge effects remaining predominantly in the extended region, and after all such processing the extended region can be ignored, leaving a picture of the original pixel size. 
     Each unit of pixel data may be a single pixel, with each sequence of units being a line of pixels, thus extending the picture area at the ends of the lines. In this case, the delayed sequence forming means may simply and conveniently comprise a shift register. With one form of extrapolation into the extended region, at least one of the additional pixel producing means may comprise a latch controlled by the control means, so that the value of such an additional pixel is a repeated pixel value, the same as the value of a pixel at or adjacent the start/end of the line. Alternatively, improved results may be obtained if at least one of the additional pixel producing means comprises means for determining the horizontal pixel value gradient at or adjacent the start/end (as the case may be) of the input line, and means for extrapolating from the value of a selected pixel at or adjacent the line start/end to the value of the or each respective additional pixel in accordance with the determined gradient and the pixel spacing of the additional pixel from the selected pixel. Even better results may be obtained, but requiring more sophisticated circuitry, if at least one of the additional pixel producing means comprises means for determining the coefficients of an nth order polynomial representing the values of selected pixels at and adjacent, or adjacent, the start/end (as the case may be) of the input line, and means for extrapolating the value of the or each additional pixel in accordance with the determined coefficients and the pixel spacing of the additional pixel from the selected pixels. 
     Alternatively, each unit of pixel data may be a single line of pixels, with each sequence of units being a frame of lines, thus extending the picture area above and below the first and last lines, respectively. In this case, the delayed sequence forming means may simply and conveniently comprise a line delay. With one form of extrapolation into the extended region, at least one of the additional line producing means comprises a line delay and a multiplexer controlled by the control means and connected such that the input to the line delay is selected from the input/delayed line (as the case may be) and the output line from the line delay, so that such an additional line is a repeated line. Alternatively, improved results may be obtained if at least one of the additional line producing means comprises means for determining for each pixel in the first/last line (as the case may be) of the input frame, or a line adjacent thereto, the vertical pixel value gradient at, or adjacent, the start/end of the input frame, and means for extrapolating from the value of that pixel to the value of the respective pixel in the or each additional line in accordance with the determined gradient and the pixel spacing of the additional pixel from that pixel. In this case, the gradient determining means may simply and conveniently comprise at least one line delay and subtractor for determining the difference between the values of corresponding pixels in a pair of lines at or adjacent the start/end (as the case may be) of the input frame, and at least one recirculating line store for storing those difference values. In this case, the extrapolating means may simply and conveniently include a recirculating line store for storing the values of the pixels in one of said lines at or adjacent the start/end (as the case may be) of the input frame, and an adder and multiplier for adding to the stored pixel values a multiple of the respective said difference depending on the spacing of the additional line from said one line. Even better results may be obtained, but requiring more sophisticated circuitry, if at least one of the additional line producing means comprises means for determining for each pixel in one line which is the first/last line (as the case may be), or a line adjacent thereto, the coefficients of an nth order polynomial representing the pixel values at or adjacent the start/end (as the case may be) of the input frame, and means for extrapolating the value of the or each additional pixel in accordance with the determined coefficients and the pixel spacing of the additional pixel from said one line. 
     A side edge extending apparatus and a top and bottom edge extending apparatus as described above may be cascaded to produce an extended region all around the frame. In this case, preferably the top and bottom edge extender comes before the side edge extender because shorter line delays will be required than if the side edge extender comes first. 
     Especially in the case where a start or end transition of the input sequence is anti-aliased, it is desirable not to use the pixel data units of the anti-aliased transition for extrapolation. Accordingly, the additional end pixel data unit producing means may be arranged to ignore at least the first and/or at least the last unit of the input sequence. Whether or not there is an anti-aliased transition in the input sequence, the apparatus may further comprise means for processing the output sequence to provide an anti-aliased transition in the pixel data units at the start and/or the end of the output sequence. 
     In accordance with a second aspect of the present invention, there is provided a method of processing a digital video signal in which an input frame has a predetermined number of active pixels, comprising the steps of: (a) forming from the input frame a first intermediate frame having a larger number of active pixels than the input frame by extrapolating the values of pixels of the input frame at or adjacent at least one edge of the input frame; (b) processing the first intermediate frame to form a second intermediate frame in which the value of each pixel is derived from the values of the pixels in a respective patch of pixels in the first intermediate frame; and (c) outputting the second intermediate frame or a portion thereof as an output frame having the same number of active pixels as the input frame. Thus, the extended first intermediate frame is formed, and processing of the first intermediate frame to form the second intermediate frame may introduce undesirable edge effects, but the affected edges can be cropped in forming the output frame. 
     The values of pixels at or adjacent both the left and right edges and/or both the top and bottom edges of the input frame may be extrapolated in forming the first intermediate frame. 
     The extrapolation at or adjacent at least one edge of the input frame may simply be a zero-order extrapolation, such that the value of each extrapolated pixel is equal to the value of a respective pixel at or adjacent the respective edge of the input frame. More complexly, but producing better results, the extrapolation at or adjacent at least one edge of the input frame may be a first-order extrapolation, such that the value of each extrapolated pixel is derived from the values of at least two respective pixels in the input frame and is a linear function of the pixel spacing of that pixel from the respective two pixels. More sophisticatedly, the extrapolation at or adjacent at least one edge of the input frame may be an nth-order extrapolation, such that the value of each extrapolated pixel is derived from the values of at least n respective pixels in the input frame and is an nth order function of the pixel spacing of that pixel from the respective n pixels. 
     Other objects, features and advantages of the present invention will become apparent upon consideration of the following detailed description of a preferred embodiment thereof, especially when considered with the accompanying drawings in which like reference numerals are employed to designate the same or similar components in the different figures. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1A and 1B illustrate how a patch of input pixels (FIG. 1A) relates to a filtered output pixel (FIG. 1B); 
     FIGS. 2A and 2B illustrate how an input line (FIG. 2A) with sharp, highly-aliased edge transitions can result in an output line (FIG. 2B) with progressive edge transitions and ringing; 
     FIGS. 3A and 3B illustrate how an input line (FIG. 3A) with anti-aliased edge transitions can result in an output line (FIG. 3B) with more greatly spread edge transitions which erode the usable active picture area; 
     FIG. 4 illustrates the difference between an acquired picture area and the usable production and distribution area which has previously been proposed; 
     FIGS. 5A to 5D illustrate how an input line (FIG. 5A) with sharp, highly-aliased edge transitions can be processed using edge pixel repeat extrapolation (FIG. 5B) in a first embodiment of the invention, using first order extrapolation (FIG. 5C) in a second embodiment of the invention, and using higher order extrapolation (FIG. 5D) in a third embodiment of the invention; 
     FIG. 6 is a block diagram of an apparatus of the first embodiment for horizontal extrapolation; 
     FIG. 7 is a block diagram of an apparatus of the first embodiment for vertical extrapolation; 
     FIG. 8 is a block diagram of an apparatus of the second embodiment for horizontal extrapolation; and 
     FIG. 9 is a block diagram of an apparatus of the second embodiment for vertical extrapolation. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIG. 1, a video processing operation such as filtering or interpolation uses the values of a patch 10 of input pixels to form the value of an output pixel 12. At the edges of a picture, there is normally a sharp transition from, or into, blanking at black level. This is usually a highly aliased transition as indicated 14 in FIG. 2A, which causes filters, interpolators and the like to `ring` and produce strange effects at the edge of the picture, as indicated 16 in FIG. 2B. Some of these effects are lost, because they are outside the active line width L, or active frame height, but some of these effects within the active line width L, or frame height, are included in the output picture. Even if the profile of the edge transition is anti-aliased, as indicated 18 in FIG. 3A with an edge transition period T 1 , so as to try to prevent ringing, there will be a spread of the edge effects to a greater edge transition period T 2 , as shown in FIG. 3B, which will erode the usable picture area. 
     The active acquisition area of an SMPTE 240M standard digital video frame is 1920 pixels (horizontally) by 1035 pixels (vertically), as indicated A in FIG. 4, but in view of the above-mentioned problems some have recommended that the usable production and distribution area of the frame should be cropped by a border sixteen pixels wide at the left and right and nine pixels high at top and bottom so that the production and distribution area is reduced to 1888 pixels by 1017 pixels, as indicated P in FIG. 4. 
     The three embodiments of the present invention described in detail below use `upstream` signal conditioning which effectively extends the picture area into the blanking area. In the first embodiment, this is accomplished by extending the data value of each pixel at the edge of the frame into the blanking area, as illustrated in FIG. 5B. In the second embodiment, it is accomplished by a first order extrapolation, that is to say the gradients of the pixel data values at and adjacent the edge of the frame are determined and used in linear extrapolation into the blanking area, as illustrated in FIG. 5C. The third embodiment is similar to the second embodiment, except that higher order extrapolation, such as quadratic or cubic, is used, as illustrated in FIG. 5D. 
     Considering the first embodiment, FIG. 6 shows an apparatus for extrapolating the frame widthwise. The digital video signal is input at 20 to a line-start latch 22 and an N (say sixteen) element shift register 24, the output of which is input to a line-end latch 26. The outputs of the two latches 22, 26 are input to respective inputs of a two-way multiplexer 28, the output of which passes through an output latch 30 to the output at 32. A pixel clock signal φ P  is used to clock the shift register 24, output latch 30 and a control circuit 34. The control circuit produces a line-start clock signal φ S  and a line-end clock signal φ E  which clock the respective latches 22, 26, and also a control signal C 1  for the multiplexer 28, all timed so as to cause the apparatus to operate as follows. 
     In a line of pixel data P 1  to P 1920 , the first pixel data P 1  is latched in the line-start latch 22 while the first N (16) pixel data P 1  to P N  fill the shift register 24. During this time, the multiplexer 28 selects the line-start latch 22 so that the first pixel data P 1  is output at 32N (16) times. The multiplexer 28 then selects the line-end latch 26, which passes the pixel data P 1  to P 1920  which are being clocked through the shift register 24, so that the pixel data P 1  to P 1920  are output at 32. The line-end latches the last pixel data P 1920 , which is then output a further N (16) times at 32. Thus, pixel data P 1 , P 2 , . . . , P 1920  are input to the apparatus at 20, and pixel data P 1  N+1 (17) times, P 2 , P 3 , . . . , P 1919 , and P 1920  N+1 (17) times are output at 32. 
     FIG. 7 shows the apparatus of the first embodiment for extrapolating the frame heightwise. The FIG. 7 apparatus is somewhat similar to that of FIG. 6, and the reference numerals for elements which perform a similar function are indicated with a prime (&#39;). The main differences are that the shift register 24 of FIG. 6 is replaced by a cascade of N (say 9) line delays 36 1  to 36 N , and the line-start and line-end latches 22, 26 are each replaced by a two-way multiplexer 38, 40 outputting to a line delay 42, 44, with the output of the line delay 42, 44 feeding back to an input of the multiplexer 38, 40. The line delays 36 1  to 36 N , output latch 30&#39;, and control circuit 34&#39; are clocked by the pixel clock signal φ P , and the control circuit supplies control signals C 2 , C 3 , C 4  to the multiplexers 38, 40, 28&#39;, respectively, all timed so as to cause the apparatus to operate as follows. 
     In a frame of lines L 1  to L 1035 , each of pixel data P 1  to P 1920 , the first line L 1  is clocked into the line delay 42 via the multiplexer 38 and is then recirculated via the multiplexer 38 while the first N (9) lines L 1  to L N  fill the cascade of line delays 36 1  to 36 N  and then the first line L 1  fills the line delay 44 via the multiplexer 40. During this time, the multiplexer 28&#39; selects the line delay 42 so that the first line L 1  is output at 32&#39; N (9) times. The multiplexer 28&#39; then selects the line delay 44, which passes the lines L 1  to L 1035  which are being clocked through the cascade of line delays 36 1  to 36 N , so that the lines L 1  to L 1035  are output at 32&#39;. After the last line L 1035  has been fed into the line delay 44, the multiplexer 40 recirculates the line, which is then output a further N (9) times at 32&#39;. Thus, lines L 1 , L 2 , . . . , L 1035  are input to the apparatus at  20&#39;, and lines L 1  N+1 (10) times, L 2 , L 3 , . . . , L 1034 , and L 1035  N+1 (10) times are output at 32&#39;. 
     The apparatuses of FIGS. 6 and 7 may be cascaded in order both to extend the lines lengthwise and to extend the frame heightwise. If the FIG. 7 apparatus follows the FIG. 6 apparatus, then the line delays need to be able to accommodate the extended lines of 1920+2N (1952) pixels. Therefore it is preferable that the FIG. 7 apparatus precedes the FIG. 6 apparatus so that the line delays need a capacity of only 1920 pixels. 
     Turning now to the second embodiment, FIG. 8 shows an apparatus for extrapolating the frame widthwise. The digital video signal is input at 50 to a line-start differencing circuit 52 and an N (say sixteen) element shift register 54, the output of which is fed to a line-end differencing circuit 56 and via a compensating delay circuit 58 to a two-way output multiplexer 60. The line-start differencing circuit 52 includes a register 62 which outputs to a two-way pixel value multiplexer 64 and a subtractor 66 which receives the input pixel to the circuit 52 at its positive input and the preceding pixel (delayed by the register 62) at its negative input, the output of the subtractor 66 being fed to a two-way difference value multiplexer 68. Conversely, the line-end differencing circuit 56 includes a register 70 which outputs to the positive input of a subtractor 72. The input to the circuit 56 is also fed to the negative input of the subtractor 72 and to the other input of the pixel value multiplexer 64. The output of the subtractor is fed to the other input of the difference value multiplexer 68. The pixel value multiplexer outputs via a pixel value latch 74 to the positive input of a subtractor 76, whereas the difference value multiplexer 68 outputs via a difference value latch 78 to one input of a multiplexer 80. The other input of the multiplier is supplied by an up/down counter 82, and the output of the multiplier 80 is supplied as the negative input of the subtractor 76. The output of the subtractor 76 is supplied via a register 84 to the other input of the output multiplexer 60, which supplies the output of the apparatus via an output register 86. The shift register 54, compensating delay circuit 58, registers 62, 70, 84, 86, up/down counter 82, and a control circuit are clocked by a pixel clock signal φ P , and the control circuit 88 supplies control signals: C 5  to the pixel value and difference value multiplexers 64, 68 and the up/down counter 82; C 6  to the pixel value and difference value latches 74, 78; and C 7  to the output multiplexer 60, all timed to cause the apparatus to operate as follows. 
     In a line of pixel data P 1  to P 1920 , the first pixel data P 1  is registered in the register 62 and is applied to the negative input of the subtractor 66. The second pixel data P 2  is applied to the positive input of the subtractor 66, and the line start gradient Δ S  equal to the P 2  -P 1  is fed via the difference value multiplexer 68 to be latched in the difference value latch 78, while at the same time the first pixel data is fed via the pixel value multiplexer 64 to be latched in the pixel value latch 74. The up/down counter is initially loaded with the value N (16), and therefore the multiplier 80 produces a value NΔ S . The subtractor 76 therefore produces a value P 1  -NΔ S , which is output via the register 84, output multiplexer 60 and output register 86. With the next pixel clock cycle, the output of the counter 82 has been decremented to N-1, and therefore the value of the output pixel is P 1  -(N-1)Δ S . This process continues until the Nth pixel is output with a value P 1  -Δ S , by which time the input pixels have worked their way through the shift register 54 and the compensating delay circuit 58. The output multiplexer 60 then selects the output of the compensating delay circuit 58, so that the pixel data P 1 , P 2 , . . . , P 1920  are output. Prior to the end of this, and at the stage when the end pixel data P 1920  is output from the shift register 54, it is applied to the negative input of the subtractor 72, whilst the penultimate pixel data P 1919  registered in the register 70 is applied to the positive input of the subtractor 72. The line end gradient Δ e  equal to P 1919  -P 1920  is output from the subtractor 72 and fed via the difference value multiplexer 68 to be latched in the difference value latch 78, while the end pixel data P 1920  is fed via the pixel value multiplexer 64 to be latched in the pixel value latch 74. The up/down counter is loaded with the value 1, and therefore the multiplier 80 produces a value Δ e . The subtractor 76 therefore produces a value P 1920  -Δ e , which is output via the register 84, output multiplexer 60 and output register 86 immediately after the pixel data P 1920  from the compensating delay circuit has been output. At the line end, the counter is incremented, rather than decremented, and therefore with the next pixel clock cycle, the output of the counter 82 has been incremented to 2, and therefore the value of the output pixel is P 1920  -2Δ e . This process continues until the Nth pixel is output with a value P 1920  -NΔ e . Thus, pixel data P 1 , P 2 , . . . , P 1920  are input to the apparatus at 50, and pixel data P 1  -NΔ S , P 1  -(N-1)Δ S , . . . , P 1  -Δ S , P 1 , P 2 , P 3 , . . . , P 1919 , P 1920 , P 1920  -Δ e , P 1920  -2Δ e , . . . , and P 1920  -NΔ e  are output at 32. 
     FIG. 9 shows the apparatus of the second embodiment for extrapolating the frame heightwise. The FIG. 9 apparatus is somewhat similar to that of FIG. 8, and the reference numerals for elements which perform a similar function are indicated with a prime (&#39;). The main differences are that: the shift register 54 of FIG. 8 is replaced by a cascade of N (say 9) line delays 90 1  to 90 N  ; the registers 62, 70 of FIG. 8 are replaced by respective line delays 62&#39;, 70&#39;; and the pixel value and difference value latches 74, 78 are each replaced by respective recirculating line stores 74&#39;, 78&#39;. The line delays 90 1  to 90 N , 62&#39;, 70&#39;, recirculating line stores 74&#39;, 78&#39;, registers 84&#39;, 86&#39;, compensating delay circuit 58&#39; and control circuit 88&#39; are clocked by the pixel clock signal φ p , and the control circuit 88&#39; supplies control signals: C 8  to the pixel value and difference value multiplexers 64&#39;, 68&#39; and up/down counter 82&#39;; C 9  to the recirculating line stores 74&#39;, 78&#39;; and C 10  to the output multiplexer 60&#39;. The control circuit also supplies a line clock signal φ L  to the up/down counter 82&#39; so that the counter increments or decrements with lines, rather than pixels as in the FIG. 8 apparatus. 
     The difference in operation between the FIG. 9 and FIG. 8 apparatuses is analogous to the difference in operation between the FIG. 7 and FIG. 6 apparatuses. 
     In a frame of lines, each of 1920 pixels, the first line is clocked into the line delays 62&#39; and 90 1  and each pixel is applied to the negative input of the subtractor 66&#39;. The corresponding pixels of the second line are applied to the positive input of the subtractor 66&#39;, and the frame start gradients for the 1920 pairs of pixels are fed via the difference value multiplexer 68&#39; to be recirculated in the difference value recirculating line store 78&#39;, while at the same time the pixel data of the first line is fed via the pixel value multiplexer 64&#39; to be latched in the pixel value recirculating line store 74&#39;. The up/down counter is initially loaded with the value N (9), and therefore the multiplier 80&#39; produces a line of values for the 1920 pixels in the line, each equal to N times the respective gradient. The subtractor 76&#39; therefore produces a line of values, each differing from the value of the respective pixel in the first line by N times the respective gradient, which are output via the register 84&#39;, output multiplexer 60&#39; and output register 86&#39;. With the next pixel clock cycle, the output of the counter 82 has been decremented to N-1, and therefore the value of the output pixel is (N-1) times the respective gradients is used. This process continues until the Nth line is output, by which time the input lines have worked their way through the line delays 90 1  to 90 N  and the compensating delay circuit 58&#39;. The output multiplexer 60&#39; then selects the output of the compensating delay circuit 58&#39;, so that 1035 lines are output. Prior to the end of this, and at the stage when the end line of pixel data in the input frame is output from the last line delay 90 N , the pixel data of that line are applied to the negative input of the subtractor 72&#39;, whilst pixel data of the penultimate line are output from the line delay 70&#39; and applied to the positive input of the subtractor 72&#39;. The frame end gradients are output from the subtractor 72&#39; and fed via the difference value multiplexer 68&#39; to be recirculated in the difference value recirculating line store 78&#39;, while the pixel data of the last line are fed via the pixel value multiplexer 64&#39; to be recirculated in the pixel value recirculating line store 74&#39;. The up/down counter is loaded with the value 1, and therefore the multiplier 80&#39; produces a line of gradients. The subtractor 76&#39; therefore produces a line of values, differing from the values of the respective pixels in the last line by the respective gradients, which are output via the register 84&#39;, output multiplexer 60&#39; and output register 86&#39;, immediately after the last line of pixel data from the compensating delay circuit has been output. At the line end, the counter is incremented, rather than decremented, and therefore with the next line clock cycle, the output of the counter 82 has been incremented to 2, and therefore the value of the output pixels differ from the values of the respective pixels in the last line by twice the respective gradients. This process continues until the Nth line is output with values differing from the respective end line values by N times the respective gradients. Thus, the top and bottom of the frame are linearly extrapolated. 
     As in the case of the FIGS. 6 and 7 apparatuses, the apparatuses of FIGS. 8 and 9 may be cascaded in order both to extend the lines lengthwise and to extend the frame heightwise, and it is preferable that the FIG. 9 apparatus precedes the FIG. 8 apparatus, again so that the line delays need a capacity of only 1920 pixels. Also, the apparatuses of the two embodiments may be mixed, for example by using the zero-order frame height extrapolator of FIG. 7 followed by the first-order frame width extrapolator of FIG. 8. 
     In a third embodiment of the invention, a 2- or higher-order extrapolation is performed to extend the frame width and/or frame height. For example, considering extrapolation at the beginning of a line, the values of the first three pixels are applied to an arrangement of arithmetic circuits or a table to determine the coefficients of a quadratic representing those values, and those coefficients are then used by a further arrangement of circuits to extrapolate the values of the additional pixels. 
     In the embodiments described above, extrapolation is carried out from the pixels at the edge of the frame. In the case where the input frame has an anti-aliased edge transition border, the control signals supplied by the control circuits 34, 34&#39;, 88, 88&#39; may be varied so that the input pixels in the transition border are ignored, and so that extrapolation is carried out from pixels inset for example by 3 or 5 pixel spacings from the edge of the input frame so as to expand the frame to its original size or to a greater size. 
     After the frames output from the output latch 30, 30&#39; or the output register 86, 86&#39; of the apparatus described above have been further processed (for example by filtering in a filter 92 (shown in FIG. 6) or by interpolation), the additional pixels formed by the above apparatuses may be ignored to produce a final frame of the original size. Additionally, an anti-aliasing process may be applied to the pixels at and adjacent the edge of the final frame in a known manner, for example using a cosine-squared or ramp profile. 
     Having described a preferred embodiment of the invention with reference to the accompanying drawings, it is to be understood that the invention is not limited to the precise embodiment and that various changes and modification thereof may be effected by one skilled in the art without departing from the spirit or scope of the invention as defined in the appended claims.