Abstract:
A disk controller for coupling a disk drive to a host includes an interface controller and a buffer memory. The interface controller is configured to interface the disk drive to the host using a NAND flash memory interface having a 14-line bus. The interface controller includes a flash controller configured to emulate data transfer protocols of the disk drive, including interpreting flash commands received from the host via the 14-line bus of the NAND flash memory interface, and generating control signals to control the disk drive. The control signals are generated based on the interpreted flash commands. The buffer memory is configured to store data received from the host and the disk drive.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. Non-Provisional patent application Ser. No. 11/322,447, filed Dec. 29, 2005, which claims the benefit of U.S. Provisional Application Nos. 60/678,249, filed May 5, 2005 and 60/748,421, filed Dec. 7, 2005, which are incorporated herein in their entirety by reference. 
    
    
     FIELD OF THE INVENTION 
     This disclosure relates to a method and apparatus for connecting different types of data storage interfaces. In particular, the disclosure relates to emulating data transfer protocols of a disk drive over a flash memory interface. 
     BACKGROUND 
     Flash memory is a non-volatile memory that enables data programming and deleting in a system after the system is deployed in the field. Due to the compact size of flash memory, it is commonly used in many consumer devices, such as digital camera, cellular phone, personal digital assistant (PDA), MP3 player, audio recorder, laptop computer, television set-top box, etc. Many such consumer devices are designed to accept flash memory devices and so have a specific flash memory interface, such as a flash memory connector or slot, in which flash memory devices may be inserted. This interface controls the data flow between the host device and the flash memory. 
     However, the amount of data that can be stored through the flash memory interface is limited to the capacity of the flash memory device. A currently available flash memory may be able to store up to about one gigabyte (1 GB) of data, which is significantly lower than a currently available disk drive that may be able to store a few hundred gigabytes of data. Therefore, there is a need for an apparatus and method to couple a disk drive to a host device having a flash memory interface. 
     SUMMARY 
     In accordance with this disclosure, an interface controller is provided that allows connection of such a disk drive to a host slot or interface that is intended to accept flash memory. In one embodiment, an interface controller for coupling a disk drive to a host includes a flash memory interface having interface signal lines in communication with the interface controller and the host, a buffer memory to store data received from the host and from the disk drive, a flash controller to emulate data transfer protocols of the disk drive using the interface signal lines over the flash memory interface, and a memory wrapper in communication with the interface controller and a buffer manager where the memory wrapper controls the buffering memory according to data transfer rates of the host and the disk drive. 
     Conversions between the disk drive data and command formats and the host flash memory interface data and commands are performed by the interface. Thereby the disk drive appears to the host to be a flash memory and can be addressed and accessed as if it were a flash memory. The host system is typically of the type described above, such as digital cameras, portable music systems such as MP3 players, personal digital assistance, cellular telephones, laptop computers, personal digital assistance, etc. Hence the disclosed interface controller allows transmission of data stored to/from the disk drive via one or more standard industry input/output interfaces to the host system which typically includes a flash memory type interface. 
     The disclosed interface controller may be compatible on the host side with one or more of a variety of industry standard flash memory interfaces such as SD/MMC, SD, MMC, HS-MMC, SD/HS-MMC, and Memory Stick, but this is not limiting. On the disk drive side, the controller or interface may be compatible with one or more industry standard disk drive interfaces such as ATA, CE-ATA, and IDE and others as desired. The disclosed interface controller supports data transfers to and from the disk drive, whether the host is operating at a faster or slower data transfer rate than the disk drive. Therefore typically a buffer (storage) is included in or associated with the disclosed interface controller. The disclosed interface controller supports both random (single logical block) read or write operations as well as sequential (multiple logical block) read or write operations. Moreover, the sequential read or write operation may be open-ended in terms of the number of logical blocks transferred. Control features are provided in the disclosed interface controller for the disk drive such as servo control, disk formatting, error correction and read channel processing as part of a disk drive controller. The buffer referred to above may be on a separate integrated circuit or may be incorporated on the same integrated circuit as the interface. There also may be provided a connection from the disclosed interface controller to a separate flash memory for additional storage. 
     Also contemplated is a method of coupling a host to a disk drive (such as a hard disk drive or optical disk drive) via a flash memory interface so that the disk drive, in combination with the interface, appears to the host as being a flash memory. In one embodiment, a method for coupling a disk drive to a host includes coupling interface signals from an interface controller to the host via a flash memory interface and coupling the interface controller to a buffer memory for storing data received from the host and from the disk drive. The method further includes emulating data transfer protocols of the disk drive using the interface signals over the flash memory interface, and controlling the buffering memory according to data transfer rates of the host and the disk drive. 
     Also contemplated is a system including the host, a disk drive such as an optical or magnetic (hard) disk drive, and means for connecting the two, where the means for connecting couples to a flash memory interface provided by the host. In one embodiment, a system for coupling a disk drive to a host includes means for interfacing to the host via a flash memory interface, means for storing data received from the host and from the disk drive, means for emulating data transfer protocols of the disk drive using the interface signals over the flash memory interface, and means for controlling the buffering memory according to data transfer rates of the host and the disk drive. 
     Hence, the means for coupling a disk drive to a host includes an interface controller which presents to the host as being a flash memory. The interface controller includes logic for emulating data transfer protocols of the disk drive using the interface signals over the flash memory interface and storing data and/or commands so as to present same in a form suitable for standard disk drive interfaces to the disk drive. 
     Also contemplated are systems, including the host, the disclosed interface controller, and the disk drive, all incorporated in a single electronic device such as digital camera, cellular phone, personal digital assistant (PDA), MP3 player, audio recorder, laptop computer, television set-top box, etc. The interface controller in certain embodiments may be implemented as an integrated circuit separated from the host and from the disk drive circuitry. In other embodiments, it may be combined with either the host or the disk drive circuitry. Yet in other embodiments, the disclosed interface controller may be implemented as a separate integrated circuit which is on a card adapted to connect to a standard flash memory interface slot on the host system. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The aforementioned features and advantages of the invention as well as additional features and advantages thereof will be more clearly understandable after reading detailed descriptions of embodiments of the invention in conjunction with the following drawings. 
         FIG. 1A  is a block diagram of a disk drive controller incorporating a flash memory and disk drive interface controller according to an embodiment of the present invention. 
         FIG. 1B  shows a block diagram of the interface controller of  FIG. 1A  according to an embodiment of the present invention. 
         FIGS. 2A ,  2 B,  2 C,  2 D and  2 E show timing waveforms for various commands of the interface controller of  FIG. 1A . 
         FIGS. 3A and 3B  illustrate graphically the buffering of the interface controller of  FIG. 1A  for a read operation. 
         FIGS. 3C and 3D  show further buffering of the interface of  FIG. 1A  for a write operation. 
         FIG. 4A  shows a list of commands a host uses for communication to the disclosed interface controller according to an embodiment of the present invention. 
         FIG. 4B  shows exemplary interface signals and corresponding terminal assignments between the present controller and the host so that the present controller appears to the host to be a NAND flash memory. 
         FIG. 5  is an illustrative block diagram of a hard disk drive (HDD) system that includes the disclosed interface controller circuitry in accordance with an embodiment of the invention. 
         FIG. 6  is an illustrative block diagram of a cellular phone system that includes the disclosed interface controller circuitry in accordance with an embodiment of the invention. 
         FIG. 7  is an illustrative block diagram of a media player that includes the disclosed interface controller circuitry in accordance with an embodiment of the invention. 
         FIG. 8  is an illustrative block diagram of a digital versatile disk (DVD) drive that includes the disclosed interface controller circuitry in accordance with an embodiment of the invention. 
         FIG. 9  is an illustrative block diagram of a high definition television (HDTV) that includes the disclosed interface controller circuitry in accordance with an embodiment of the invention. 
         FIG. 10  is an illustrative block diagram of vehicle control systems that includes the disclosed interface controller circuitry in accordance with an embodiment of the invention. 
         FIG. 11  is an illustrative block diagram of a set top box that includes the disclosed interface controller circuitry in accordance with an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     The following descriptions are presented to enable any person skilled in the art to make and use the invention. Descriptions of specific embodiments and applications are provided only as examples. Various modifications and combinations of the examples described herein will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other examples and applications without departing from the spirit and scope of the invention. Thus, the present invention is not intended to be limited to the examples described and shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein. 
     Some portions of the detailed description which follows are presented in terms of procedures, steps, logic blocks, processing, and other symbolic representations of operations on data bits that can be performed on computer memory. A procedure, computer executed step, logic block, process, etc., are here conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps are those utilizing physical manipulations of physical quantities. These quantities can take the form of electrical, magnetic, or radio signals capable of being stored, transferred, combined, compared, and otherwise manipulated in a computer system. These signals may be referred to at times as bits, values, elements, symbols, characters, terms, numbers, or the like. Each step may be performed by hardware, software, firmware, or combinations thereof. 
       FIG. 1A  is a block diagram of a disk drive controller incorporating a flash memory and disk drive interface controller according to an embodiment of the present invention. As shown in  FIG. 1A , the disk drive controller  100  couples between a host  102  and a disk drive  104 . The disk drive  104  typically has advanced technology attachment (ATA), consumer electronics ATA (CE-ATA), or integrated drive electronics (IDE) type interface. Also coupled to the disk drive controller  100  is an auxiliary flash memory  106 , which stores firmware code for the disk drive controller. In this case, the host  102 , while shown as a single block, typically includes as relevant components an industry standard flash memory slot (connector) of the type for connecting to commercially available flash memory devices, which in turn is connected to a standard flash memory controller in the host. This slot typically conforms to one of the standard types, for instance, MMC (Multi Media Card), SD™ (Secure Digital), SD™/MMC which is a combination of SD™ and MMC, HS-MMC (High Speed-MMC), SD™/HS-MMC which is a combination of SD™ and HS-MMC, and Memory Stick. This list is not limiting. Throughout the disclosure, the abbreviations MP3, SRAM, DRAM, and WLAN denote MPEG-1 Audio Layer 3, static random access memory, dynamic random access memory, and wireless local area network respectively. 
     A typical application is a portable computer or consumer electronic device such as MP3 music player or cellular telephone handset that has one application processor that connects to an embedded flash memory through a NAND flash memory interface. In accordance with this disclosure, rather than a flash memory, a hard disk drive or other type of disk drive is provided replacing the flash memory and using its interface signals. The disclosed method provides a flash memory-like interface for a disk drive, which makes it easier to incorporate a disk drive in such a host system which normally only accepts flash memory. One advantage of a disk drive over flash memory as a storage device is far greater storage capacity for a particular cost. 
     In  FIG. 1A , the primary data storage is provided by the disk drive  104 . Advantageously, only minimum changes in the host  102  flash memory controller firmware and software need be made to incorporate the disk drive using the disclosed interface controller. Also, minimum command overhead is provided. Advantageously, there is open-ended data transfer for any particular read or write operation, in terms of the number of logic blocks transferred between the host and the disk drive. Also, no sector count of the disk drive need be provided by the host. 
     In certain embodiments the disk drive  104  may be referred to by an industry as a small form factor (SFF) hard disk drive, which typically has a physical size of 650×15×70 mm. A typical data transfer rate of such SSF hard disk drive is 25 megabytes per second. 
     The functions of the disk drive controller  100  of  FIG. 1A  are further explained below. The disk drive controller  100  includes an interface controller  110 , which presents to the host system  102  as a flash memory controller with a 14-line bus having the signal designations shown in  FIG. 4B  and discussed below. The interface controller  110  also performs the functions of host command interpretation and data flow control between the host  102  and a buffer manager  112 . The buffer manager circuit  112  controls, via a memory controller  116 , the actual buffer (memory), which may be an SRAM or DRAM buffer  118  that may be included as part of the same chip as interface controller  100  or be on a separate chip. The buffer manager provides buffering features that are described further below. 
     The buffer manager  112  is also connected to a processor Interface/Servo and ID-Less/Defect Manager (MPIF/SAIL/DM) circuit  122 , which performs the functions of track format generation and defect management. The MPIF/SAIL/DM circuit  122  in turn connects to the Advanced High Performance Bus (AHB)  126 . Connected to the AHB bus  126  is a line cache  128 , and a processor  130 ; a Tightly Coupled Memory (TCM)  134  is associated with the processor  130 . The processor  130  may be implemented by an embedded processor or by an external microprocessor. The purpose of the line cache  128  is to reduce code execution latency. It may be coupled to an external flash memory  106 . 
     The remaining blocks in the disk drive controller  100  perform functions to support a disk drive and include the servo controller  140 , the disk formatter and error correction circuit  142 , and the read channel circuitry  144 , which connects to the pre-amplification circuit in the disk drive  104 . 
     The signals used between the host  102  and the interface controller  110  are shown in  FIG. 4B . This contemplates a 14-line parallel bus with 8 lines (0-7) carrying the bi-directional in/out (I/O) data. The remaining lines carry the commands CLE, ALE, /CE, /RE, /WE and R/B respectively. 
       FIG. 1B  shows a block diagram of the interface controller of  FIG. 1A  according to an embodiment of the present invention. The interface controller  110  includes a flash controller (Flash_ctl) block  150 , a flash register (Flash_reg) block  152 , a flash FIFO wrapper (Flash_fifo_wrapper) block  154 , and a flash system synchronization (Flash_sys_syn) block  156 . 
     The flash register block  152  is used for register access. It stores commands programmed by the processor  130  and the host  102 . A flash state machine (not shown) in the flash controller  150  decodes the incoming command from the host  102  and provides the controls for the disk drive controller  100 . The flash FIFO wrapper  154  includes a FIFO, which may be implemented by a 32×32 bi-directional asynchronous FIFO. It generates data and control signals for transferring data to and receiving data from the buffer manager  112  via the buffer manager interface (BM IF). The transfer direction of the FIFO may be controlled by the commands stored in the flash register  152 . The flash system synchronization block  156  synchronizes control signals between the interface controller and the buffer manager interface. It also generates a counter clear pulse (clk2_clr) for the flash FIFO wrapper  154 . 
       FIGS. 2A-2E  show timing waveforms for the signals on signal lines of the interface controller of  FIG. 1A  according to embodiments of the present invention.  FIG. 2A  shows the timing waveforms for a random read process whereby a single logical block is read from the disk drive to the host. Note that these timing waveforms embody relatively minor modifications from those timing waveforms of the same commands as used with a standard NAND flash memory controller. The signals themselves are the standard NAND flash memory signals but the timing is somewhat modified here to accommodate the disk drive which is of course the source/sink of the data rather than a NAND flash memory. Note that in the ATA specification, typically one logical block is one sector of disk drive data. Hence, the random read of  FIG. 2A  typically represents one logical block of data to be read from the disk drive. 
       FIG. 2B  in contrast shows timing waveforms for a sequential read where a number of logical blocks are read from the disk drive in one operation. In the case of the sequential read, the reading continues until reading is disabled by de-assertion of the RE command. As shown in the I/O waveform of  FIG. 2B , there are two sectors of data being transferred, sector  0  and sector  1 . Note that such sequential reads are typically not provided in the usual NAND flash memory interface since NAND flash memory typically cannot support sequential reads or writes. Also shown in the I/O waveform of  FIG. 2B  is the return of the status by the device indicated by one byte of data following command 70h. 
       FIG. 2C  shows the timing waveforms for the same commands for a random write operation, which is the writing of a single logical block to the disk drive.  FIG. 2D  shows timing waveforms for the sequential write operation, which is the writing of multiple logical blocks in one operation. Note that the R/B signal is used to indicate the buffer status for flow control over the interface.  FIG. 2E  shows the timing waveforms for a non-data command, for instance, Standby Immediate, Flush Cache EXT, etc. 
     The disk drive controller  100  of  FIG. 1A  includes data buffering supported by SRAM or DRAM buffer  118 , memory controller  116 , and buffer manager  112 . Buffering is useful here because typically the host controller and the disk drive may not read/write at the same data rates. Because the data transfer is open-ended in terms of length, a read look-ahead is typically implemented in disk drive firmware to ensure continuous data flow and maximum interface throughput. For a fast host, which reads or writes data faster than the disk drive reads or writes data respectively, the host transfer rate is faster than the disk data rate. Hence maximum interface throughput may be achieved for a read operation and buffer usage is typically small. This is illustrated graphically in  FIG. 3A  where block  302  indicates the spin-up of the disk drive, the loading of the disk drive read head, the seeking of the disk drive head, and the reading of data. The R/B signal at this point is de-asserted (level 0), indicating to the host that data is not ready. In block  304 , as soon as one single sector is read from the disk and is available in the buffer, the R/B signal is asserted (level 1), indicating to the host that data is ready for transfer. In block  306 , the buffer is empty after the host finishes one sector read. The buffer may continue to be empty until a new sector is read from the disk and the R/B signal is de-asserted during this period. In block  308 , a new sector is read and again the R/B signal is asserted. The conditions in blocks  306  and  308  may repeat until all sectors requested by the host are read from the disk. In block  310 , the disk returns to its standby/spin-down mode and is no longer active. 
       FIG. 3B  shows the associated buffer handling of a read operation for a “slow host.” A slow host means that the host system transfer data rate is slower than that of the disk data rate. In this case, a read look-ahead method is employed in order to buffer the data as much as the buffer memory capacity  118  permits. To maximize power saving, the SOC (System-on-Chip) and preamplifier of the disk drive can be put in an idle mode until the data in buffer  118  buffer has been completely consumed. With reference to the  FIG. 3B , in block  312 , the disk drive is in its spin-up, load, seek and read mode with the R/B command de-asserted as in  FIG. 3A . The next block  314  is similar to that of block  304  in  FIG. 3A . The block  316  results in an idle state, wherein sectors are being transferred from the buffer to the host while the drive is in idle mode. At this point the R/B signal is asserted. Missing revolution may happen at this time due to buffer-full status. In block  318 , N-n sectors of data remain in the buffer to be transferred to the disk drive and the disk drive is still in the idle state until all data in the buffer have been consumed. At this point the R/B signal is still being asserted. In block  320 , the disk drive returns to its standby/spin-down mode. 
       FIG. 3C  shows the buffer handling for a write operation with a fast host. A fast host means the host is operating faster than the disk drive in terms of data transfer. In this case, maximum efficiency is obtained without the disk drive missing any revolutions, that is it is operating at all times in terms of transferring data. In this case the host system, being the faster of the two entities, is throttled down (reduced in terms of data transfer rate) by the R/B signal when the buffer  118  in the interface is full. Other blocks shown in  FIG. 3C  are self-explanatory with reference to  FIGS. 3A and 3B . 
       FIG. 3D  shows the buffer handling for a write operation for a slow host where missing disk drive revolutions will occur. In this case the write performance degradation is caused by the slowness of the host relative to the data transfer rate of the disk drive regardless of what interface is used. The blocks in  FIG. 3D  are self-explanatory with reference to the previous figures. 
       FIG. 4A  shows a set of internal commands for one embodiment of the disclosed interface controller. As shown in this case, there are five commands in the leftmost column. The value of the command in the first cycle and the second cycle are shown in the next two columns. The rightmost column in  FIG. 4A  shows what these commands refer to in terms of read and write operations. The values in the first cycle and the second cycle refer to the command code used by the host and correspond to the values in the timing waveforms. Note that some commands are only one cycle long and some other commands are two cycles long. These commands are latched in by the interface controller  110  of  FIG. 1A , and are interpreted by firmware running on the processor  130 . The commands used by the host are not limited to this list shown in  FIG. 4A . Since these commands may be emulated from traditional ATA commands, any ATA command may be constructed in the similar manner but with a different command code. The interface controller  130  not only provides connectivity between a host and a disk drive via a NAND flash memory interface, it also provides means to pass ATA commands from the host to the disk drive. 
     These commands map to task file registers used in the ATA commands for the ATA industry standard disk drive specification. In the case of the disclosed interface controller, the sector count used in the ATA task file registers is not present or needed. The Logical Block Address (LBA) Low command in ATA maps to, in the present case, LBA 0 . 
     The ATA LBA Mid command maps to, in this case, LBA 1 . The ATA LBA High command maps to LBA 2 . The LBA Low Ext command maps to LBA 3 . The Command Register in ATA maps to the first cycle command code (e.g., 25h). The ATA Status Register maps to I/O  0  that is returned by the device immediately following the second cycle command code of 70h. 
     Note that in one embodiment of the present invention, the logical block address is 32 bits long, which allows addressing of up to 2 terabytes of storage capacity in the disk drive. In addition, the command structure consumes less of the system bandwidth than in the ATA interfaces, and there is no performance degradation if the host is faster in terms of data transfer rate than the disk drive. 
       FIG. 5  is an illustrative block diagram of a hard disk drive (HDD) system  500  that includes the disclosed interface controller circuitry in accordance with an embodiment of the invention. The disclosed interface controller circuitry (not shown) may be included in either or both signal processing and/or control circuitry  521 .  FIG. 1B  illustrates example of uses of the disclosed interface controller circuitry applicable to the control circuitry  521 . In some implementations, the signal processing and/or control circuitry  521  and/or other circuits (not shown) in the disk drive may process data, perform coding and/or encryption, perform calculations, and/or format data that is output to and/or received from a (magnetic) storage medium  533 . 
     The disk drive may communicate with a host device  523  such as a computer, mobile computing devices such as personal digital assistants, cellular phones, media or MP3 players and the like, and/or other devices via one or more wired or wireless communication links. The disk drive may be connected to memory  529  such as random access memory (RAM), low latency nonvolatile memory such as flash memory, read only memory (ROM) and/or other suitable electronic data storage. Moreover, the signal processing and/or control circuits  521  may be implemented as a system-on-chip (SOC), and the memory  529  may be disposed on or off such SOC. The disk drive  500  may comprise a motor controller  526  that controls a spindle motor  540  and an actuator arm controller  552  that controls movement of an actuator arm  534 . The actuator arm  534  may include a read/write (R/W) head  532  that writes/reads data to/from the storage medium  533 . A preamp  531  may output write data to the R/W head  532 . The preamp  531  may also output data read by the R/W head  532  to the signal processing and/or control circuitry  521 . 
       FIG. 6  is an illustrative block diagram of a cellular phone system  650  that includes the disclosed interface controller circuitry in accordance with an embodiment of the invention. The cellular phone  650  includes a cellular antenna  651 . Signal processing and/or control circuits  652  communicate with a WLAN interface and/or memory  666  or mass data storage  664  of the cellular phone  650 . In some implementations, the cellular phone  650  includes a microphone  656 , an audio output  658  such as a speaker and/or audio output jack, a display  660  and/or an input device  662  such as a keypad, pointing device, voice actuation and/or other input device. The mass data storage  664  includes the disclosed interface controller circuitry (not shown).  FIG. 1B  illustrates example of uses of the disclosed interface controller circuitry applicable to the control of mass data storage  664 . 
     More particularly, the cellular phone  650  may communicate with mass data storage  664  that stores data in a nonvolatile manner such as optical and/or magnetic storage devices for example hard disk drives (HDD) and/or DVDs. At least one HDD may have the configuration shown in  FIG. 5  and/or at least one DVD player may have the general configuration shown in  FIG. 8 . The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8 inches. The cellular phone  650  may be connected to memory  666  such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. The cellular phone  650  also may support connections with a WLAN via a WLAN network interface  668 . 
       FIG. 7  is an illustrative block diagram of a media player  700  that includes the disclosed interface controller circuitry in accordance with an embodiment of the invention. In one embodiment the media player may comprise an MP3 player, for example. The media player  700  may communicate with mass data storage  710  that stores data such as compressed audio and/or video content in a nonvolatile manner. In some implementations, the compressed audio files include files that are compliant with MP3 format or other suitable compressed audio and/or video formats. The mass data storage may include optical and/or magnetic storage devices for example hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown in  FIG. 5  and/or at least one DVD may have the general configuration shown in  FIG. 8 . The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8 inches. The media player  700  may be connected to memory  714  such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. The media player  700  also may support connections with a WLAN via a WLAN network interface  716 . Still other implementations in addition to those described above are contemplated. 
     Signal processing and/or control circuits  704  communicate with a WLAN interface  716  and/or mass data storage  710  and/or memory  714  of the media player  700 . The mass data storage  710  includes the disclosed interface controller circuitry (not shown).  FIG. 1B  illustrates example of uses of the disclosed interface controller circuitry applicable to the mass data storage  710 . In some implementations, the media player  700  includes a display  707  and/or a user input  708  such as a keypad, touchpad and the like. In some implementations, the media player  700  may employ a graphical user interface (GUI) that typically employs menus, drop down menus, icons and/or a point-and-click interface via the display  707  and/or user input  708 . The media player  700  further includes an audio output  709  such as a speaker and/or audio output jack. The signal processing and/or control circuits  704  and/or other circuits (not shown) of the media player  700  may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other media player function. 
       FIG. 8  is an illustrative block diagram of a digital versatile disk (DVD) drive  800  that includes the disclosed interface controller circuitry in accordance with an embodiment of the invention. The disclosed interface controller circuitry may be implemented in either or both signal processing and/or control circuits,  812 , mass data storage  818  and/or a power supply  813 . The signal processing and/or control circuit  812  and/or other circuits (not shown) in the DVD  800  may process data, perform coding and/or encryption, perform calculations, and/or format data that is read from and/or data written to an optical storage medium  816 . In some implementations, the signal processing and/or control circuit  812  and/or other circuits (not shown) in the DVD  800  can also perform other functions such as encoding and/or decoding and/or any other signal processing functions associated with a DVD drive. 
     The DVD drive  800  may communicate with an output device (not shown) such as a computer, television or other device via one or more wired or wireless communication links  817 . The DVD  800  may communicate with mass data storage  818  that stores data in a nonvolatile manner. The mass data storage  818  may include a hard disk drive (HDD). The HDD may have the configuration shown in  FIG. 5 . The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8 inches. The DVD  800  may be connected to memory  819  such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. 
       FIG. 9  is an illustrative block diagram of a high definition television (HDTV)  900  that includes the disclosed interface controller circuitry in accordance with an embodiment of the invention. The disclosed interface controller circuitry may be implemented in either or both signal processing and/or control circuits,  922 , a WLAN interface  929 , mass data storage  927  and/or a power supply  923 . The HDTV  900  receives HDTV input signals in either a wired or wireless format and generates HDTV output signals for a display  926 . In some implementations, signal processing circuit and/or control circuit  900  and/or other circuits (not shown) of the HDTV  900  may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other type of HDTV processing that may be required. 
     The HDTV  900  may communicate with mass data storage  927  that stores data in a nonvolatile manner such as optical and/or magnetic storage devices. At least one HDD may have the configuration shown in  FIG. 5  and/or at least one DVD may have the configuration shown in  FIG. 8 . The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8 inches. The HDTV  900  may be connected to memory  928  such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. The HDTV  900  also may support connections with a WLAN via a WLAN network interface  929 . 
       FIG. 10  is an illustrative block diagram of a vehicle  1000  including control systems that include the disclosed interface controller circuitry in accordance with an embodiment of the invention. In some implementations a powertrain control system  1032  receives power from a power supply  1033 , inputs from one or more sensors  1036  such as temperature sensors, pressure sensors, rotational sensors, airflow sensors and/or any other suitable sensors and/or that generates one or more output control signals  1038  such as engine operating parameters, transmission operating parameters, and/or other control signals. 
     Other control systems  1040  of the vehicle  1000  may likewise receive signals from input sensors  1042  and/or output control signals to one or more output devices  1044 . In some implementations, the control system  1040  may be part of an anti-lock braking system (ABS), a navigation system, a telematics system, a vehicle telematics system, a lane departure system, an adaptive cruise control system, a vehicle entertainment system such as a stereo, DVD, compact disc and the like. Still other implementations are contemplated. 
     The powertrain control system  1032  may communicate with mass data storage  1046  that stores data in a nonvolatile manner. The mass data storage  1046  may include optical and/or magnetic storage devices for example hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown in  FIG. 5  and/or at least one DVD may have the configuration shown in  FIG. 8 . The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8 inches. The powertrain control system  1032  may be connected to memory  1047  such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. The powertrain control system  1032  also may support connections with a WLAN via a WLAN network interface  1048 . The control system  1040  may also include mass data storage, memory and/or a WLAN interface (all not shown). 
       FIG. 11  is an illustrative block diagram of a set top box  1100  that includes the disclosed interface controller circuitry in accordance with an embodiment of the invention. The disclosed interface controller circuitry may be implemented in either or both signal processing and/or control circuits  1184 , a WLAN interface  1196 , mass data storage  1190  and/or a power supply  1183 . The set top box  1100  receives signals from a source  1181  such as a broadband source and outputs standard and/or high definition audio/video signals suitable for a display  1188  such as a television and/or monitor and/or other video and/or audio output devices. The signal processing and/or control circuits  1184  and/or other circuits (not shown) of the set top box  1100  may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other set top box function. 
     The set top box  1100  may communicate with mass data storage  1190  that stores data in a nonvolatile manner. The mass data storage  1190  may include optical and/or magnetic storage devices for example hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown in  FIG. 5  and/or at least one DVD may have the configuration shown in  FIG. 8 . The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8 inches. The set top box  1100  may be connected to memory  1194  such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. The set top box  1100  also may support connections with a WLAN via a WLAN network interface  1196 . 
     One skilled in the relevant art will recognize that many possible modifications and combinations of the disclosed embodiments may be used, while still employing the same basic underlying mechanisms and methodologies. The foregoing description, for purposes of explanation, has been written with references to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described to explain the principles of the invention and their practical applications, and to enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated.