Abstract:
This invention is a cost efficient network arrangement for a space switching network for high voltage applications. This arrangement minimizes the number of control signal leads for a multistage switching network. If a switching network has N stages, then the present invention provides for performing the space switching operation with N+1 control signal leads. The present space switch arrangement may also be employed for conventional non-high voltage space switching applications.

Description:
BACKGROUND OF THE INVENTION 
     The present invention pertains to an electromechanical space switching network and more particularly to an arrangement for minimizing the number of control leads required to operate a multistage network. 
     Modern switching systems typically incorporate fully electronic time and space switching networks in their design and implementation. Examples of such switching systems include the GTD-5 EAX monufactured by GTE Communication Systems Corporation and No. 5 ESS manufactured by Western Electric. 
     All switching systems require a network, which is capable of switching relatively high voltages for such functions as subscriber line ringing and coin control functions. These networks are auxiliary networks and not part of the voice or data switching path. These auxiliary networks are line or service circuit concentrator networks. With currently existing technology, use of fully electronic networks to switch high voltages is costly and, therefore, of little use in modern switching systems. 
     Conventional electromechanical switching network components and techniques are not always compatible with these modern switching systems designs. Furthermore, these conventional electromechanical switching networks require a number of control leads in order to operate the network. Any reduction in the number of control leads results in more efficient packaging of printed circuit boards. Also, network control is made simpler by the reduction of control signals. 
     SUMMARY OF THE INVENTION 
     The present invention is an electromechanical space switching network for high voltage applications of switching networks. The space switching network includes a generator for producing a number of control signals. The switching network also includes a number of switching matrices. The switching matrices are sequentially connected, so that, a path may be established from an inlet of a first switching matrix to a particular outlet of the last switching matrix, via each of the sequentially connected matrices. 
     Each of the switching matrices includes a number of horizontal switching elements, such as, horizontal control leads and horizontal signal leads. In addition, each switching matrix includes a number of vertical switching elements, such as, vertical control leads and vertical signal leads. 
     An electromechanical switch is connected between a horizontal and a vertical signal lead for each switching matrix. Further, a solid state controller is connected between each horizontal and each vertical control lead. 
     The solid state controller operates in response to a vertical and a horizontal control signal to produce a path closure signal. The electromechanical switch operates in response to the path closure signal to establish a physical connection of the horizontal and vertical signal leads. For each of the sequentially connected matrices, the vertical control lead of one switching matrix is the horizontal control lead of the next adjacent sequential switching matrix. Ihis scheme alternates for each of the switching matrices in the switching network. 
     In the space switching network, each of the space switching matrices is simultaneously operated in response to the control signals to establish a physical path via the horizontal and vertical signal leads from the inlet of the first switching matrix through each switching matrix to the outlet of the last switching matrix. 
    
    
     A BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a crosspoint configuration utilized in the switching network embodying the present invention. 
     FIG. 2 is a schematic diagram showing the implementation of a multiple stage switching network of the present invention. 
     FIG. 3 is a block diagram of the control portion for the switching network embodying the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIG. 1, a crosspoint connection for a space switching network is shown. As diagrammatically pictured, two elements are provided at the intersection of each horizontal line and each vertical line of a space switching network. The first element is a crosspoint switching element X, which when activated establishes a signal path between a particular horizontal signal lead and a particular vertical signal lead. The crosspoint switching element X may comprise ferreed, relay device or other metallic contact device. These electromechanical crosspoints are used to switch high voltage signals such as, subscriber line ringing or coin control functions. This network configuration may also be applied to voice or data networks. For a voice or data network application, the signal switching element or electromechanical crosspoint would be replaced with an electronic crosspoint. This electronic crosspoint wculd sufficiently handle the relatively low voltages associated with voice and data transmission. 
     The second element required to complete a signal switching path is the control memory M. The control memory element M operates in response to two control signals, a horizontal control lead and a vertical control lead. In response to the simultaneous occurrence of both the vertical and horizontal control lead signals, the control memory element M produces the switching element control signal, which is transmitted to the signal switching element X. Therefore, in order to complete a connection through a stage of space switching matrix, a vertical and a horizontal control lead signal is supplied to the appropriate control memory element M in order to activate its corresponding signal switching element X to establish a path between a corresponding horizontal signal lead and a vertical signal lead. 
     The signal switching element X may comprise an electromechanical crosspoint, such as, a miniature single winding DIP (dual in-line package) relay or a ferreed type. 
     Referring to FIG. 2, a four stage space switching network is shown. The switching matrices A through D are represented by the intersection of horizontal and vertical lines. A four stage space switching network is shown, although, the present invention would be applicable to a space switching network with any number of switching stages. 
     Each space switching matrix requires two signals in order to select a path through the matrix. These two signals are a horizo-ntal control signal and a vertical control signal. In a conventinal space switching network, control signals are usually independently generated for each matrix stage. Therefore, a four stage network as shown in FIG. 2 would require eight control signals, a vertical control signal and a horizontal control signal for each of the four stages. In the present invention, N switching matrices may be operated with N plus 1 control signals. For example, the four stage switching network, shown in FIG. 2, may be operated with five control signals. 
     For drawing simplicity only one matrix of each matrix stage is shown. In an actual network configuration, each stage would include several switching matrices. For example, the A matrix should would be connected to several other B matrices (not shown); in addition to the connection to the particular B matrix shown in FIG. 2. This is true for each matrix stage. These interconnections between the matrix stages are called links and the interconnection pattern is called the fabric of the network. 
     Each intersection of the network matrix horizontals and verticals comprises a network switching element as shown in FIG. 1. The signal switching element for this configuration is a crosspoint. The control memory element in the configuration in FIG. 1 is a D-type latch, as shown in FIG. 2. 
     To establish a connection through the space switching network shown in FIG. 2, a path must be established from an A Horizontal through the A, B, C and D matrices to a D vertical lead. In order to establish the sample network connection shown in FIG. 2 in dark solid and dashed lines, an active data signal is provided to the AB and CD leads; while, a clock signal is applied to the A horizontal, BC and D vertical leads. The A horizontal signal, which is a clock signal, is connected to the A matrix as a horizontal control signal. The AB signal, which is a data signal, is connected to the A matrix as a vertical control signal and is connected to the B matrix as a horizontal control signal (shown in the heavy dashed lines of FIG. 2). 
     The switching element at the intersection of the A horizontal signal (shown in the heavy solid line) of matrix A with the AB lead will be operated and a signal path will be established from the horizontal input to the A matrix (shown in heavy solid line) through the AB vertical signaling lead to the B matrix (shown in heavy dashed lines). The configuration of the D-type latch for the A matrix and C matrix is shown in lower left portion of the sketches of these matrices. The connection of the D-type latches for the B and D matrices is shown in the lower right portion of FIG. 2. 
     In the A matrix, the vertical data control signal, shown in dashed lines, is connected to the D input of the latch; and, the horizontal clock control signal is connected to the clock input of the latch. When these two control signals are active, the crosspoint associated with the latch is closed and connects a signal path through the A matrix. 
     Coincident with the operation of the A matrix, the AB (data) signal, which is also the horizontal control signal of the B matrix, operates along with the BC (clock) signal, which is a vertical control signal of the B matrix, to switch a path through the B matrix. As a result, the D-type latch at the intersection of these two control signals is enabled and operates its corresponding B matrix crosspoint. The crosspoint establishes the connection from the A matrix through the B matrix via the dashed heavy line and the heavy solid line shown as the BC signal to the C matrix. The heavy solid and dashed lines indicate both the control signals and the signal leads, as previously shown in FIG. 1. 
     Simultaneously with the connection of the A matrix and B matrix, a connection is made from the B matrix to the C matrix. The BC signal, which was used as a vertical control signal for the B matrix, is applied to the C matrix as a horizontal control signal (shown in heavy solid line). The CD signal (shown in heavy dotted line) is the vertical control signal for selection in the C matrix. The D-type latch at the intersection of the BC and CD signals is as shown in the lower left portion of FIG. 2. The CD signal is connected to the D input of the latch. When this latch is activated, the corresponding crosspoint to which it is connected is operated to establish the path shown through the C matrix. 
     Simultaneously with the establishment of paths through the A, B and C matrices, the final path through the D matrix is established. The CD signal which was applied as a vertical control signal to the C matrix, is applied as a horizontal control signal to the D matrix (shown in heavy dotted line). The vertical control signal for the D matrix is the D vertical signal shown in solid dark line. The latch at the intersection of these two signals in the D matrix is as shown in the lower right portion of FIG. 2. The D vertical signal is connected to the clock input of the associated latch; and, the CD signal is connected as the data input of the latch. When an active signal is present on the CD and D vertical leads, the latch is operated and its associated crosspoint produces a path from the C matrix along the CD horizontal to the D vertical and out of the D matrix. As a result, a path is established through the A, B, C and D matrices. 
     When an active signal or logic 1 is present on the data lead of the D-type latch, together with the application of the clock signal, the latch is operated to store the active signal. As a result, the crosspoint is operated and remains operated for as long as the latch remains set. Each of latches may all simultaneously be reset by applying inactive or logic 0 signal in the presence of the appropriate clock pulses. 
     The AB signal is a vertical control signal in the A matrix and a horizontal control signal in the B matrix. The AB signal is the data signal applied to the data input of each D-type latch along a particular vertical of the A matrix. Each successive space switching matrix will alternate the use of a clock signal to fulfill the roll of a vertical control signal in one matrix and a horizontal control signal in the next adjacent matrix. For example, the BC signal performs these functions for the B and C matrices respectively. The shared signal for C and D matrices will be a data signal, the CD signal. Addition of subsequent matrices to this configuration would be accomplished by alternately sharing data and clock signals as shown in FIG. 2. 
     Referring to FIG. 3, the control logic which produces the required data and clock control signals is shown. Processor 10, which may be implemented with the microprocessor, is connected to network terminal and link map 20. Network terminal and link map 20 indicates whether particular network links are busy or idle. This indication is accomplished by setting a particular bit or resetting a particular bit corresponding to each network link. In addition, processor 10 also includes other local memory for storing the prooessor&#39;s operating program. 
     The processor scans the network terminal and link map 20 for a combination of idle network links with which to connect a path through the network matrices. When a particular network path has been selected by the processor 10, each bit which indicates the busy/idle status of a particular link is marked busy, set to logic 1. 
     Processor 10 is further connected to I/O port 40, which transmits control data. The I/O ports 30 and 40 are connected to the parameter registers 50. Each of the parameter registers 51 through 56 is connected to both I/O port 30 and I/O port 40. One parameter register is required for each category of network fabric parameters. 
     Each parameter register is a multiple bit register. The size of each parameter register is determined by the number of variables within a given parameter type. The width or size of the A horizontal parameter register 51 is N1. This corresponds to the number of inlets per A matrix. Each of the A matrices in the switching network has the same number of inlets. A matrix parameter register 52 is wide enough to contain the number of A matrices in the switching network, N2. Similarly, B matrix 53, C matrix 54 and D matrix 55 parameter registers are of sufficient size to indicate the nunber of , C and D matrices, N3, N4 and N5 respectively. In addition, D vertical parameter register 56 is of sufficient to contain the number of outlets per D matrix, N6. 
     In order to establish a particular path through the network, processor 10 selects an idle path by scanning network terminal and link map 20. When an idle path is found, processor &#39; 10 transmits the identity of each inle and outlet via I/O port 30 to the respective parameter registers 51 through 56. A bit is set in each parameter register 51 through 56 corresponding to the particular path which is selected. 
     In order to derive the horizontal and vertical control signals shown in FIG. 2, the outputs of the parameter registers 50 are gated through clock signal gates 60 and data signal gates 80. Parameter registers 51 and 52 are connected to a number of AND gates represented by AND gate 61. In order to derive control signals for each A horizontal, one AND gate, 61, must be enabled. The nuxber of A horizontal AND gates 61 is calculated by multiplying the size of the A horizontal parameter register 51 times the size of the A matrix parameter register 52 or N1 times N2. For example, if there are four inlets per A matrix equal to N1, and sixteen A matrices equal to N2, then, it is required that 64 A horizontal AND gates 61 be connected to the parameter registers 51 and 52. The connection of the parameter registers 51 and 52 to the AND gates 61 is in a matrix fashion so that one AND gate 61 will respond when a particular inlet represented by parameter register 51 and a particular matrix represented by parameter register 52 is selected. 
     Similarly the number of AND gates 62, which are connected to parameter register 53 and 54, is found by multiplying N3 times N4. The number of AND gates 63 is found by multiplying N5 times N6, which corresponds to the number of D matrices 
     When the proper clock signal gates 61, 62 and 63 are, selected which represent the particular A horizontal, BC link and D outlet respectively, these gates are enabled at the appropriate time. This is accomplished by AND gate 70, which gates the network clock with a signal transmitted via I/O port 40 by processor 10. As a result of processor 10 transmitting the enabling signal and the coincidence of this enabling signal with the network clock, the appropriate ones of AND gate 61, 62 and 63 are enabled to operate the corresponding D-type latches of the network. 
     A similar operation exists for deriving the data control signals by data signal gates 80, as did for deriving the clock control signals by clock signal gates 60. The number of AND gates represented by AND gate 81 is equal to N2, the number A matrices, multiplied by N3, the number B matrices. This is the number of AB links. For example, if the number of A matrices is 16 and the number of B matrices is 4, there would be 64 AND gates 81 which is the number of AB links. Parameter registers 51 and 52 are connected to data signal gates 81 in a matrix fashion so that one gate is selected for the concurrence of the parameter registers 52 and 53. Similarly, AND 82 are connected parameter registers 54 and 55. The number of AND gates 82 is equal to the number of C matrices, N4, multiplied by the number of D matrices, N5. 
     Simultaneously with enabling the clock signal gates 60, processor 10 via I/O port 40 operates the data signal gates 81 and 82, to generate the AB and CD data signals. The AB and CD data signals serve to operate the D-type latches at the intersection of the various verticals and horizontals of the network matrices, as indicated above. 
     When the path through the space switching matrix is required to be disconnected, processor 10 again operates all parameter registers 50, but indicates a logic 0 for each of the data signal gates 80. The clock signal gates 60 are operated the same as for establishing the connection. As a result, on the next clock cycle, each of the D-type latches which was set, now has a logic 0 clocked in at data and becomes reset. In addition, the corresponding crosspoint is released and the connecting path opened. 
     Although the preferred embodiment of the invention has been illustrated, and that form described in detail, it will be readily apparent to those skilled in the art that various modifications may be made therein without departing from the spirit of the invention or from the scope of the appended claims.