Abstract:
A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block further has input and output stages, as well as a loopback function, to allow the block to be configured for various digital signal processing operations.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This claims the benefit of copending, commonly-assigned U.S. Provisional Patent Applications Nos. 60/772,197 and 60/789,535, filed Feb. 9, 2006 and Apr. 4, 2006, respectively, each of which is hereby incorporated by reference herein in its respective entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     This invention relates to programmable logic devices (PLDs), and, more particularly, to specialized processing blocks which may be included in such devices. 
     As applications for which PLDs are used increase in complexity, it has become more common to design PLDs to include specialized processing blocks in addition to blocks of generic programmable logic resources. Such specialized processing blocks may include a concentration of circuitry on a PLD that has been partly or fully hardwired to perform one or more specific tasks, such as a logical or a mathematical operation. A specialized processing block may also contain one or more specialized structures, such as an array of configurable memory elements. Examples of structures that are commonly implemented in such specialized processing blocks include: multipliers, arithmetic logic units (ALUs), barrel-shifters, various memory elements (such as FIFO/LIFO/SIPO/RAM/ROM/CAM blocks and register files), AND/NAND/OR/NOR arrays, etc., or combinations thereof. 
     One particularly useful type of specialized processing block that has been provided on PLDs is a digital signal processing (DSP) block, which may be used to process, e.g., audio signals. Such blocks are frequently also referred to as multiply-accumulate (“MAC”) blocks, because they include structures to perform multiplication operations, and sums and/or accumulations of multiplication operations. 
     For example, a PLD sold by Altera Corporation, of San Jose, Calif., under the name STRATIX® II includes DSP blocks, each of which includes four 18-by-18 multipliers. Each of those DSP blocks also includes adders and registers, as well as programmable connectors (e.g., multiplexers) that allow the various components to be configured in different ways. In each such block, the multipliers can be configured not only as four individual 18-by-18 multipliers, but also as four smaller multipliers, or as one larger (36-by-36) multiplier. In addition, one 18-by-18 complex multiplication (which decomposes into two 18-by-18 multiplication operations for each of the real and imaginary parts) can be performed. In order to support four 18-by-18 multiplication operations, the block has 4×(18+18)=144 inputs. Similarly, the output of an 18-by-18 multiplication is 36 bits wide, so to support the output of four such multiplication operations, the block also has 36×4=144 outputs. 
     However, those inputs and outputs may not be used in every mode in which the DSP block can operate. For example, if the DSP block is configured as a finite impulse response (FIR) filter, with 18-bit data and coefficients, each block may be used to perform the summation of four 18-by-18 multiplications to form a 4-tap sub-block of a longer FIR filter. In this case, the number of inputs is 4×(18+18)=144 lines, but the output is only 38 bits wide even though the DSP block is able to support 144 output lines. Similarly, in a 36-by-36 bit multiplication, all four internal multipliers are used but only (36+36)=72 input lines and 72 output lines are used (even thought there are 144 input lines and 144 output lines). Hence, in that configuration the input lines are not used fully even though the core of the DSP block is fully used. 
     Input/output (I/O) drivers and lines can consume significant device area. Indeed, in a DSP block of the aforementioned STRATIX® II PLD, I/O resources consume approximately 50% of the DSP block area. And yet, as discussed above, they are not always used. At the same time, they cannot be eliminated because all of the potential configurations of the block have to be supported. 
     It would be desirable to be able to reduce the area of a PLD consumed by a specialized processing block such as a DSP block without losing functionality of the block. 
     SUMMARY OF THE INVENTION 
     The present invention relates to specialized processing blocks for PLDs wherein the specialized processing blocks have reduced area without losing functionality. According to one aspect of the invention, the specialized processing block preferably includes a plurality of fundamental processing units instead of discrete multipliers. Each fundamental processing unit preferably includes the equivalent of at least two multipliers and logic to sum the partial products of all of the at least two multipliers. As a result, the sums of the all of the multiplications are computed in a single step, rather than summing the partial products of each multiplier to form individual products and then summing those products. Such a fundamental processing unit can be constructed with an area smaller than that of the individual multipliers and adders. If a single multiplication is required to be performed, one of the multipliers in the fundamental processing unit is used, while the inputs to the other(s) are zeroed out. Nevertheless, because the provision of the fundamental processing unit reduces the area of the specialized processing block, efficiency is improved. 
     In a preferred embodiment, the fundamental processing unit includes the equivalent of two 18-by-18 multipliers and one adder so that it can output the sum of the two multiplication operations. While each of the 18-by-18 multipliers can be configured for a smaller multiplication operation (e.g., 9-by-9 or 12-by-12), the integrated nature of the fundamental processing unit means that the individual multiplier outputs are not accessible. Only the sum is available for use by the remainder of the specialized processing block. Therefore, to obtain the result of a single non-complex multiplication that is 18 bits-by-18 bits or smaller, an entire fundamental processing unit must be used. The second multiplier, which cannot be disengaged, simply has its inputs zeroed. 
     The specialized processing block according to the invention preferably also has one or more additional adders for additional processing of the output of the fundamental processing unit, as well as optional pipeline registers and a flexible output stage. Therefore the specialized processing block preferably can be configured for various forms of filtering and other digital signal processing operations. In addition, the specialized processing block preferably also has the capability to feed back at least one of its outputs as an input, which is useful in adaptive filtering operations, and to chain both inputs and outputs to additional specialized processing blocks. 
     Therefore, in accordance with the present invention, there is provided a specialized processing block for a programmable logic device. The specialized processing block preferably includes a plurality of fundamental processing units, each of the fundamental processing units including a plurality of multipliers and circuitry for adding in one operation partial products produced by all of the plurality of multipliers. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other objects and advantages of the invention will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which: 
         FIG. 1  is a high-level diagram of one preferred embodiment of a specialized processing block in accordance with the present invention; 
         FIG. 2  is a functional diagram of the specialized processing block of  FIG. 1 ; 
         FIG. 3  is a block diagram of a preferred embodiment of a fundamental processing unit for a specialized processing block in accordance with the present invention; 
         FIG. 4  is a preferred embodiment of an output stage of a specialized processing block in accordance with the present invention 
         FIG. 5  is a functional diagram of a specialized processing block in accordance with the present invention configured as a finite impulse response filter; 
         FIG. 6  is a functional diagram of a specialized processing block in accordance with the present invention configured for arithmetic shifting; 
         FIG. 7  is a preferred embodiment of an output stage of a specialized processing block in accordance with the present invention configured for logical shifting; 
         FIG. 8  is a functional diagram of a specialized processing block in accordance with the present invention configured for rotation; 
         FIG. 9  is a functional diagram of a specialized processing block in accordance with the preferred invention configured as a barrel shifter; and 
         FIG. 10  is a simplified block diagram of an illustrative system employing a programmable logic device incorporating the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The invention will now be described with reference to  FIGS. 1-9 . 
       FIG. 1  shows a high-level diagram of one preferred embodiment 10 of a specialized processing block according to the invention, while  FIG. 2  is a functional diagram of the same embodiment 10. 
     As seen in  FIG. 1 , specialized processing block  10  includes optional input pre-MUX stage  11 , optional input register stage  12 , optional input multiplexing stage  13 , multiplication stage  14 , optional pipeline register stage  15  and adder/output stage  16 . 
     The function of input pre-MUX stage  11 , if provided, is to format the regular inputs, loopback inputs and cascade inputs (see below) into a form suitable for registering. 
     Regular inputs do not require any specific formatting. Cascade inputs may be a one-register delayed version of a previous input, and therefore may need formatting accordingly. However, such formatting also can be done in programmable logic of the programmable logic device of which specialized processing block  10  is a part, so if formatting of cascade inputs is the only pre-MUX function required, input pre-MUX stage  11  can be omitted or, if provided, bypassed. The loopback input  17  may be arranged so that it is always connected to a particular multiplier or group of multipliers. The formatting performed by input pre-MUX stage  11  may include the direction of particular inputs to particular bit locations depending on the function to be performed by specialized processing block  10 . The formatting may be carried out in one embodiment according to a stored table identifying the various possible operations (e.g., simple or complex multiplications of various sizes, shifting operations, rotation operations, etc.) and specifying the corresponding formatting required. 
     The output of input pre-MUX stage  11 , if provided, may be registered by optional input register stage  12 . If there in no input pre-MUX stage  11 , then the input register function, if needed, can be performed in the programmable logic portion of the programmable logic device of which block  10  is a part. Therefore, input register stage  12  is considered optional. Input register stage  12 , even if provided, preferably can be optionally bypassed in cases where unregistered outputs are needed or desired. 
     Input multiplexing stage  13 , if provided, takes registered or unregistered inputs from input pre-MUX stage  11  and inputs potentially from elsewhere in the programmable logic device and formats the data for the different operational modes. In that respect it is similar to input pre-MUX stage  11 , and therefore frequently if one of input pre-MUX stage  11  and input multiplexing stage  13  is provided, the other will not be provided. 
     As one example of the type of formatting performed by input pre-MUX stage  11  or input multiplexing stage  13 , consider an 18-by-18 complex multiplication in which:
 
Real Result=Re[( a+jb )×( c+jd )]=( ac−bd )
 
Imag Result=Im[( a+jb )×( c+jd )]=( ad+bc )
 
This complex operation requires four 18-by-18 multiplications and hence eight 18-bit inputs, but because there are only four unique 18-bit shared inputs, input multiplexing stage  13  will take the inputs a, b, c and d and perform the necessary duplication so those four inputs are properly routed to the correct multiplier inputs for each of the real and imaginary calculations. Similarly, for 9- and 12-bit mode operations, input pre-MUX stage  11  and/or input multiplexing stage  13  ensures correct alignments of the input bits in order to obtain correct results.
 
     Multiplication stage  14  preferably includes a plurality of fundamental processing units as described above. In a preferred embodiment, each specialized processing block  10  (see  FIG. 2 ) includes four fundamental processing units  30 , meaning that it can perform up to eight multiplications in groups of two multiplications that are summed together. In that embodiment, the fundamental processing units in specialized processing block  10  preferably are grouped into identical half-blocks, so that each half-block in its own right can be considered a specialized processing block within the invention. 
     Each fundamental processing unit preferably includes the functionality for a sum of two 18-by-18 multiplications. The fundamental processing units preferably are all identical, but in some embodiments, it is possible to provide a negation function on only some inputs of some multipliers, as maybe required for, e.g., complex multiplication where, as is apparent above, subtraction may be required. Alternatively, the negation function may be provided in the adder portion of the fundamental processing unit, so that one or more adders can also perform subtraction. 
     The structure of a preferred embodiment of a fundamental processing unit is shown in  FIG. 3 . Each fundamental processing unit  30  preferably supports a sum of two 18-by-18 multiplications and preferably includes two partial product generators  31 , two ten-vector-to-two-vector compressors  32 , a 4-to-2 compressor  33 , and two carry-propagate adders  34 . Adders  34  preferably include one 30-bit adder  340  and one 24-bit adder  341 , which are selectably connectable by a control signal  342 . For smaller multiplications such as 9-by-9 or 12-by-12, only 24 bits are required, so the two adders can be disconnected to allow two independent multiplications. For larger multiplications such as 18-by-18, the two adders  34  should be linked as a single adder. 
     Each partial product generator  31  preferably creates nine 20-bit Booth-encoded vectors (Booth-encoding is a known technique that can reduce the number of partial products), as well as a 17-bit unsigned carry vector (negative partial products are in ones-complement format, with the associated carry-in bit in the carry vector). An additional 19-bit signed partial product may be generated in the case of unsigned multipliers (which preferably will always be zero for signed multipliers). Although preferably up to 11 vectors may be generated, the carry bits preferably can be combined with the partial product vectors, requiring only 10 vectors to be compressed. 
     The partial products preferably are compressed down to two 39-bit vectors (36 bits plus sign extension bits). Any sign extensions should be preserved properly past the 36-bit 18-by-18 multiplier boundary, so that any sign extensions can be valid up to the 72-bit 36-by-36 multiplier boundary (in a case where two fundamental processing units are combined to implement a 36-by-36 multiplication as described below). After compression, the results preferably are processed in mux-and-shift circuitry  35 , which preferably include combinatorial logic where any sign-extension, zero-filling or shifting of the results before addition, as may be required depending on the operation being performed, can be accomplished prior to final combination of the results in 4-to-2 compressor  33  and carry-propagate adders  34 . For each of circuits  350 ,  351 , the inputs preferably are two 39-bit vectors for a total of 78 input bits, while the outputs preferably are two 54-bit vectors for a total of 108 bits. The extra thirty bits are the result of sign extension, zero-filling, and or shifting. Multiplexer  352  indicates a selection between sign extended or zero-filled results. The four 54-bit vectors are input to compressor  33  which outputs two 54-bit vectors, which are added in adders  34  to produce a 54-bit output. 
     As discussed above, because the partial products from both multipliers are added at once, the two multipliers of a fundamental processing unit cannot be used for two independent multiplications, but a single multiplication can be carried out by zeroing the inputs of the second multiplier. 
     For smaller multiplications, independent subset multipliers (9-by-9 and 12-by-12 cases) may be handled as follows: 
     For two 9-by-9 multiplications, the first 9-by-9 multiplication preferably is calculated using the most significant bits (MSBs) of the first multiplier (on the left in  FIG. 3 ), and the second 9-by-9 multiplication preferably is calculated using the least significant bits (LSBs) of the second multiplier (on the right in  FIG. 3 ). The MSBs of the right multiplier are filled with the sign extensions of the corresponding values, as appropriate. The outputs of the left multiplier (sum and carry vectors) are left-shifted by 18 bits. The two multiplier outputs preferably are then compressed together and the two resulting final vectors are then added with the two adders  34 , which are not connected for this operation. The first 9-by-9 result preferably will be output on the MSBs of the left 30-bit) adder  340 , while the second 9-by-9 result preferably will be output on the LSBs of the right (24-bit) adder  341 . 
     Independent 12-by-12 multiplications can be calculated in a manner similar to a 9-by-9 multiplication, using the MSB/LSB method. 
     In both cases, preferably the right multiplier outputs are zeroed above 24 bits to prevent any interference with the independent left multiplier result. 
     In the case of summed multiplications, regardless of the precision, all inputs preferably are shifted to occupy the MSBs of the multipliers used, and the output vectors preferably are not shifted. The output vectors, however, preferably are fully sign-extended, so that sign-extension out of the adders  34  can be used for the full width of the accumulator (below). 
     Preferably, for complex multiplications and other operations that require subtraction of products, the adder inputs can be negated (effectively making the adder an adder/subtractor). Alternatively, however, one or more of the multipliers can be provided with the ability to selectively negate its output vectors, by inverting the input (ones&#39; complement), and adding the multiplicand to the result. The multiplicand addition can be performed in the compression of the partial products, so that the negation can be implemented before adders  34 . 
     Pipeline register stage  15 , which preferably may be bypassed at the user&#39;s option, preferably allows outputs of multiplication stage  14  to be registered prior to further addition or accumulation or other processing. 
     Adder/output stage  16  preferably selectively shifts, adds, accumulates, or registers its inputs, or any combination of the above. Its inputs preferably are the outputs of the two fundamental processing units in specialized processing block  10 . As seen in  FIG. 4 , those two inputs  40 ,  41  are input to respective register/shifter units  42 ,  43 , which optionally may shift or sign extend inputs  40 ,  41 . In a preferred embodiment, each of inputs  40 ,  41  is a 54-bit vector, which is shifted or sign-extended to create a respective 72-bit vector. 
     The outputs of units  42 ,  43  preferably are input to a 3:2 compressor  44 , along, preferably, with the output  45  of stage  16  itself. This feedback provides an accumulation function to specialized processing block  10 . Preferably, the fed-back output  45  passes through multiplexer  46 , which can alternatively select a zero (e.g., ground) input when accumulation is not necessary or desired. 
     The outputs of compressor  44  are provided (through appropriate multiplexers as described below) to two adders  47 ,  48 , which may be chained together under programmable control, depending on the use to which they are to be put, as described below. The outputs of adders  47 ,  48  preferably may be registered in registers  49 ,  400  or not, as determined by multiplexers  401 ,  402 . Registered or not, outputs  47 ,  48  preferably make up the output vector of specialized processing block  10 . As an alternative path, multiplexers  403 ,  404 ,  405  allow adders  47 ,  48  to be bypassed where the outputs of fundamental processing units  30  are to be output without further processing. 
     In the case, described above, where each fundamental processing unit  30  can perform a sum of two 18-by-18 multiplications, two fundamental processing units  30  can perform a 36-by-36 multiplication, which, as is well known, can be decomposed into four 18-by-18 multiplications. In such a case, two compressed 72-bit vectors preferably are output by compressor  44  and preferably are added together by the two 44-bit adders  47 ,  48 , which are programmably connected together for this mode by AND gate  406 . The upper 16 bits may be ignored in this mode. 
     In other modes with narrower outputs, where adders  47 ,  48  need not be connected together, adders  47 ,  48  optionally may be arranged to chain the output of specialized processing block  10  with the similar output of another specialized processing block  10 . To facilitate such a mode, the output of register  400 , for example, may be fed to 4:2 multiplexer  407 , which provides two inputs to adder  47 . Another input to multiplexer  407  may be chain-in input  408  from another specialized processing block  10 , which may be provided via chain-out output  409  from register  49  of that other specialized processing block  10 . 
     Thus, in chaining mode, 44-bit adder  48  may be used to add together the results within one of specialized processing blocks  10 —configured, e.g., as a single multiplier, a sum of multipliers, or an accumulator.—with the results of the previous block. By using multiplexer  407  to select as inputs to adder  47  the output of adder  48  and the output of another specialized processing block  10 , the output of the current specialized processing block  10  can be the chained sum of the outputs of the current and previous specialized processing blocks  10 . If the chaining mode is used, only a 44-bit accumulator is available, which will still give a 6-bit to 8-bit guard band, depending on the number of multipliers. However, as is apparent, the chaining mode is not available for the 36-bit mode, in which both adders  47 ,  48  are needed to obtain the result of a single specialized processing block  10 . 
     The output paths may be slightly different depending on the mode of operation. Thus, multiplexers  401 ,  402  allow selection of registered or unregistered outputs of adders  47 ,  48 . It will be appreciated, however, that, as shown, registered outputs preferably are used in cascade or chained mode. 
     In addition, at least one output may be looped back, as at  17 , to an input of specialized processing block  10 . Such a loopback feature may be used, for example, if specialized processing block  10  is programmably configured for adaptive filtering. Although multiple loopbacks may be provided, in a preferred embodiment, one loopback  17  to single multiplier or group of multipliers is provided. 
     The specialized processing block  10  of the present invention may be programmably configured as a long chain finite impulse response (FIR) filter. As shown in  FIG. 5 , four fundamental processing units  30  are configured as part of such a FIR filter  50 . As discussed above, this may be considered to be either one or two specialized processing blocks  10 . As shown, each of adders  48  is used to add the results of four multiplications, with adders  47  used in the chaining or cascade mode described above to add together the outputs of adders  48  (as well, possibly, as the outputs of adders  48  of other specialized processing blocks  10 ) to form a long FIR filter. The coefficients of the FIR filter are input at  51 , while the data to be filtered are input via register chain  52 , preferably formed in one of input pre-MUX stage  11 , input register stage  12  or input multiplexing stage  13 . To account for delay introduced by the output cascade chain, at least one extra delay  53  (e.g., in the form of an extra register) preferably is provided in input cascade chain  52 . Preferably, the number of delays corresponds to the number of adders  47  or, more particularly, output registers  400  for which delays  53  compensate. Generally, this would amount to one delay  53  for each pair of fundamental processing units  30 . Further FIR filter implementations are described in copending, commonly-assigned U.S. patent application Ser. No. 11/447,370, filed concurrently herewith, which is hereby incorporated by reference herein in its entirety. 
     In addition to implementing a FIR filter, the specialized processing block  10  of the present invention may be programmably configured as a barrel shifter. Specifically, by using the 36-by-36 multiplier mode, a 32-bit vector can be arithmetically or logically shifted to the left or to the right. Such a shift by N bits may be accomplished by multiplying the vector to be shifted by a second vector of equal length, all of whose bits are 0 except for the Nth least significant bit, which is 1. 
     If the vector to be shifted is sign-extended to 36 bits and the second vector is padded with zeroes to 36 bits, the result is an arithmetic shift, and whether the shift is to the left or to the right depends on whether the result is taken, respectively, from the 32 most significant bits of the 64-bit result, or the 32 least significant bits.  FIG. 6  shows such a shifting operation. 
     Similarly, if both vectors are padded with zeroes to 36 bits, the result is a logical shift, and whether the shift is to the left or to the right depends on whether the result is taken, respectively, from the 32 most significant bits of the 64-bit result, or the 32 least significant bits.  FIG. 7  shows such a shifting operation. 
     In addition, if both vectors are padded with zeroes to 36 bits, and the 32 most significant bits of the 64-bit result are ORed with the 32 least significant bits, the result is a rotation of the N most significant bits of the first vector to the N least significant bits of the result, as shown in  FIG. 8 . 
       FIG. 9  shows how the arithmetic and logical shifting, and rotation, can be performed using the 36-by-36 multiplier mode  90  to perform the 32-by-32 multiplication as described above, an OR gate  91  whose inputs are the two 32-bit halves of the 64-bit result, and a three-input multiplexer  92 , operating according to the following table: 
                                                     A   B   MUX   Result                           Signed   Unsigned   00   Arithmetic shift left           Signed   Unsigned   01   Arithmetic shift right           Unsigned   Unsigned   00   Logical shift left           Unsigned   Unsigned   01   Logical shift right           Unsigned   Unsigned   10   Rotation                        
It should be noted that the arithmetic shift left and the logical shift left produce the same result and thus those cases are redundant. Put another way, a signed input is really needed only for the arithmetic shift right.
 
     Thus it is seen that a specialized processing block for a programmable logic device, based on a plurality of fundamental processing units, has been provided. 
     A PLD  100  incorporating such circuitry according to the present invention may be used in many kinds of electronic devices. One possible use is in a data processing system  900  shown in  FIG. 10 . Data processing system  900  may include one or more of the following components: a processor  901 ; memory  902 ; I/O circuitry  903 ; and peripheral devices  904 . These components are coupled together by a system bus  905  and are populated on a circuit board  906  which is contained in an end-user system  907 . 
     System  900  can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any other application where the advantage of using programmable or reprogrammable logic is desirable. PLD  100  can be used to perform a variety of different logic functions. For example, PLD  100  can be configured as a processor or controller that works in cooperation with processor  901 . PLD  100  may also be used as an arbiter for arbitrating access to a shared resources in system  900 . In yet another example, PLD  100  can be configured as an interface between processor  901  and one of the other components in system  900 . It should be noted that system  900  is only exemplary, and that the true scope and spirit of the invention should be indicated by the following claims. 
     Various technologies can be used to implement PLDs  90  as described above and incorporating this invention. 
     It will be understood that the foregoing is only illustrative of the principles of the invention, and that various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention. For example, the various elements of this invention can be provided on a PLD in any desired number and/or arrangement. One skilled in the art will appreciate that the present invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims that follow.