Abstract:
A thin film transistor and a method for manufacturing the same capable of reducing a change in a threshold voltage of the thin film transistor formed on a flexible substrate. The thin film transistor includes: a substrate, the substrate being flexible; a buffer layer having a low dielectric constant from about 1.2 to about 4.0 and formed on the substrate; a semiconductor layer formed on the buffer layer; a gate electrode; first insulation layer formed between the gate electrode and the semiconductor layer; a second insulation layer formed on the semiconductor layer and the gate electrode; and a source/drain electrode electrically connected to the semiconductor layer through a contact hole formed in the second insulation layer. Therefore, the thin film transistor can reduce a change in its threshold voltage, thereby reducing changes in brightness, gray scale, contrast, etc., of light-emitting devices using the thin film transistor.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims priority to and the benefit of Korean Patent Application No. 10-2005-0040464, filed on May 16, 2005, in the Korean Intellectual Property Office, the entire content of which is incorporated herein by reference.  
       BACKGROUND  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a thin film transistor and a method for manufacturing the same, and more particularly to a thin film transistor and a method for manufacturing the same which are capable of reducing a change in a threshold voltage of the thin film transistor by forming a buffer layer with a low dielectric constant.  
         [0004]     2. Discussion of Related Art  
         [0005]     In general, in order to form a thin film transistor on a flexible substrate, that is, on a metal thin film made of stainless steel, titanium (Ti), etc., an insulation buffer layer must be provided between the metal thin film and the thin film transistor. A thin film transistor having a buffer layer formed on a metal thin film has electrical and structural characteristics similar to a system on insulator (SOI) transistor. In the thin film transistor having the buffer layer form on the metal thin film, a semiconductor layer constituting the thin film transistor is made of low temperature polysilicon (LTPS) obtained by heating and crystallizing an amorphous silicon layer at a low temperature.  
         [0006]     In the thin film transistor with the structure described above, that is, in the thin film transistor having the semiconductor layer made of the low temperature polysilicon formed on the metal thin film, a threshold voltage of the thin film transistor can be controlled through a circuit design by effectively utilizing a bias signal (for example, current, voltage, etc.) which is applied to the thin film transistor. In this case, in order to stabilize the operation of the thin film transistor, that is, in order to obtain an optimal result when an arbitrary signal is processed, a direct current (DC) voltage or a predetermined signal can be added to the arbitrary signal to be processed.  
         [0007]     However, when a DC voltage or a predetermined signal is applied to the thin film transistor with the structure described above, the threshold voltage of the thin film transistor can be changed. Also, if an unintended voltage is applied to the metal thin film or if unexpected charges are accumulated on the metal thin film due to static electricity, etc., the threshold voltage of the thin film transistor may become different from a reference design value recommended when the thin film transistor is initially designed. Furthermore, if the threshold voltage of the thin film transistor becomes different from the reference design value, color coordinates to be displayed on a screen of a display apparatus utilizing the thin film transistor are changed, and accordingly gray scale and contrast are also changed.  
         [0008]     Therefore, in order to solve the above-described problems, the present invention provides a thin film transistor and a method for manufacturing the same which are capable of significantly reducing an electrical characteristic change of the thin film transistor, by in advance preventing an electrical characteristic change (for example, a change in a threshold voltage) of the thin film transistor from occurring when an unintended voltage is temporarily or momentarily applied to the thin film transistor.  
       SUMMARY OF THE INVENTION  
       [0009]     According to an embodiment of the present invention, there is provided a thin film transistor including: a substrate, the substrate being flexible; a buffer layer having a low dielectric constant from about 1.2 to 4.0 and formed on the substrate; a semiconductor layer formed on the buffer layer; a gate electrode; a first insulation layer formed between the gate electrode and the semiconductor layer; a second insulation layer formed on the semiconductor layer and the gate electrode; and a source/drain electrode electrically connected to the semiconductor layer through a contact hole formed in the second insulation layer.  
         [0010]     In one embodiment, the low dielectric constant is greater than  1 . 2  and less than  3 , and/or the buffer layer includes SiOC, Xerogels (nanoporous dielectric), Silsesquioxanes (SOG), and/or SiOF. The buffer layer has a thickness between about 0.3 and 10 μm. Also, the thin film transistor further includes a diffusion prevention layer formed between the substrate and the buffer layer. The diffusion prevention layer includes tin (Sn).  
         [0011]     The thin film transistor further includes a third insulation layer formed on the substrate, the substrate being between the third insulation layer and buffer layer, and/or the third insulation layer includes SiO 2  and/or SiN x . The substrate includes a metal thin film. The metal thin film includes stainless steel (sus) and/or titanium (Ti).  
         [0012]     According to another embodiment of the present invention, there is provided a method for manufacturing a thin film transistor, the method including: forming a buffer layer having a low dielectric constant between about 1.2 to 4.0 on a substrate, the substrate being flexible; forming a semiconductor layer on the buffer layer; forming a first insulation layer on the semiconductor layer; applying a metal layer on the first insulation layer to form a gate electrode; forming a second insulation layer on the semiconductor layer and the gate electrode; and electrically connecting a source/drain electrode to the semiconductor layer through a contact hole formed in the second insulation layer.  
         [0013]     In one embodiment, the thin film transistor manufacturing method further includes forming a diffusion prevention layer between the substrate and the semiconductor layer. The thin film transistor manufacturing method further includes simultaneously patterning the first insulation layer and the metal layer formed on the first insulation layer. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]     The accompanying drawings, together with the specification, illustrate exemplary embodiments of the present invention, and, together with the description, serve to explain the principles of the present invention.  
         [0015]      FIG. 1  is a cross-sectional view of a thin film transistor according to a first embodiment of the present invention.  
         [0016]      FIG. 2  is a cross-sectional view of a thin film transistor according to a second embodiment of the present invention.  
         [0017]      FIG. 3  is a cross-sectional view of a thin film transistor according to a third embodiment of the present invention.  
         [0018]      FIG. 4  is a cross-sectional view of a thin film transistor according to a fourth embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0019]     In the following detailed description, certain exemplary embodiments of the present invention are shown and described, by way of illustration. As those skilled in the art would recognize, the described exemplary embodiments may be modified in various ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, rather than restrictive.  
         [0020]      FIG. 1  is a cross-sectional view of a thin film transistor  100  according to a first embodiment of the present invention. Referring to  FIG. 1 , the thin film transistor  100  includes a substrate  110 , a buffer layer  120 , a semiconductor layer  130 , a first insulation film  140 , a gate electrode  150   a , a second insulation film  160 , and a source/drain electrode  150   b.    
         [0021]     In more detail, the buffer layer  120  is formed on the substrate  110 , the semiconductor layer  130  is formed on the buffer layer  120 , the first insulation film  140  is formed on the semiconductor layer  130 , and the gate electrode  150   a  is formed on the first insulation film  140 . The second insulation film  160  is formed on the semiconductor layer  130  and the gate electrode  150   a , and the source/drain electrode  150   b  is formed on the second insulation film  160 , wherein the source/drain electrode  150   b  is electrically connected to the semiconductor layer  130  through contact holes  160   a  formed in the second insulation film  160 .  
         [0022]     Hereinafter, components constituting the thin film transistor  100  and the order in which the components are formed will be described in more detail with reference to  FIG. 1 . First, the substrate  110  (hereinafter, referred to as a metal thin film  110 ), which is a flexible substrate, is formed using a metal layer to have a predetermined thickness. Here, the metal thin film  110  is made of stainless steel (steel special use stainless (sus)), titanium (Ti), etc. In the above-described structure having the substrate  110  formed as the metal thin film, in order to minimize the amount of charges induced in a channel area  130   a  of the semiconductor layer  130  when a bias signal is applied to the substrate  110 , the charging capacity of the buffer layer  120  formed between the semiconductor layer  130  and the metal thin film  110  should be minimized.  
         [0023]     In more detail, to reduce the amount of charges charged in the buffer layer  120  by the bias signal applied to the metal thin film  110 , the buffer layer  120  formed on the substrate  110  is made of a material with a relatively low dielectric constant (i.e., lower than a dielectric constant of a conventional buffer layer). In one embodiment, the buffer layer  120  is made of a material with a dielectric constant that is between 1.2 and 4 (or greater than 1.2 but less than 3).  
         [0024]     In the present embodiment, the buffer layer  120  is formed with a low dielectric constant material, such as SiOC, Xerogels (nanoporous dielectric), Silsesquioxanes (SOG), SiOF and so on. Here, the buffer layer  120  is applied with a predetermined thickness between about 0.3 μm and about 10 μm (in one embodiment, between 0.5 and 5 μm) on the metal thin film  110 .  
         [0025]     The semiconductor layer  130 , which is made of an applied amorphous silicon layer (not shown) transmuted into a polysilicon layer through one of various crystallization methods, is formed on the buffer layer  120 . In order to transmute the amorphous silicon layer into the polysilicon layer, an excimer laser method, etc., can be used. In this case, a low temperature polysilicon (LTPS) layer is formed. In more detail, the semiconductor layer  130  is formed by patterning a polysilicon layer formed by a crystallization process. The formed semiconductor layer  130  includes a channel area  130   a  and a source/drain area  130   b.    
         [0026]     The first insulation film  140  is formed on the semiconductor layer  130 , and the gate electrode  150   a  is formed by applying a metal layer on the first insulation film  140  and then patterning the metal layer. At this time, the first insulation film  140  and the metal layer forming the gate electrode  150   a  can be individually patterned according to the order in which they are stacked, or can be simultaneously patterned. After the gate electrode  150   a  is formed, the second insulation film  160  is formed on the entire surfaces of the buffer layer  120 , the semiconductor layer  130 , and the gate electrode  15     0   a. The second insulation film  160  is made of SiO 2 , SiN x , etc. A plurality of contact holes  160   a  for exposing the semiconductor layer  130  are formed in the second insulation film  160 , and the source/drain electrode  150   b  is formed on the second insulation film  160  in which the contact holes  160   a  are formed so that the source/drain electrode  150   b  is electrically connected to the semiconductor layer  130 .  
         [0027]     As described above in the first embodiment, when a voltage is applied to the metal thin film  110  made of stainless steel (sus), titanium (Ti), etc., a charging capacity between the metal thin film  110  and the semiconductor layer  130  can be minimized by the buffer layer  120  formed with a low dielectric constant material. Accordingly, an electrical characteristic change of the thin film transistor  100  can be minimized.  
         [0028]      FIG. 2  is a cross-sectional view of a thin film transistor  200  according to a second embodiment of the present invention. In order to avoid repeating the same descriptions, detailed descriptions for structures (or components) that are substantially the same as those of the first embodiment shown in  FIG. 1  are not provided again.  
         [0029]     Referring to  FIG. 2 , a diffusion prevention layer  215  is formed on a substrate  210  of the thin film transistor  200  according to the second embodiment of the present invention, and a buffer layer  220  is formed on the diffusion prevention layer  215 . A semiconductor layer  230  is formed on the buffer layer  220 , a first insulation film  240  and a gate electrode  250   a  are formed on the semiconductor layer  230 , and a second insulation film  260 , in which a plurality of contact holes  260   a  are formed, is formed on the gate electrode  250   a  and the semiconductor layer  230 . A source/drain electrode  250   b , which is electrically connected to the semiconductor layer  230  through the contact holes  260   a , is formed on the second insulation film  260 .  
         [0030]     In the second embodiment of the present invention, the substrate  210  is formed as a metal thin film made of stainless steel, titanium (Ti), etc. In addition, the buffer layer  220  can be formed with a thickness between about 0.3 μm and about 10 μm, and, in one embodiment, between 0.5 and 5 μm, using a dielectric material with a low dielectric constant. In one embodiment, the buffer layer  220  is made of a dielectric material with a dielectric constant that is between 1.2 and 4, such as SiOC, Xerogels (nanoporous dielectric), Silsesquioxanes (SOG), SiOF and so on.  
         [0031]     Also, in the second embodiment, the diffusion prevention layer  215  is formed between the substrate  210  and the buffer layer  220 . The diffusion prevention layer  215  is provided to block impurities from being diffused into different layers of the thin film transistor  200  when an amorphous silicon layer (not shown) formed on the substrate  210  is transmuted into a polysilicon layer using one of various crystallization methods, for example, an excimer laser method. Further, the diffusion prevention layer  215  prevents external impurities from flowing into the buffer layer  220  or the semiconductor layer  230  through the substrate  210 . Here, the diffusion prevention layer  215  can be formed with a material such as tin (Sn) and so on.  
         [0032]      FIG. 3  is a cross-sectional view of a thin film transistor  300  according to a third embodiment of the present invention. For the thin film transistor  300 , detailed descriptions for the structures (or components) that are substantially the same as those disclosed in the first and second embodiments of  FIGS. 1 and 2  are not provided again.  
         [0033]     Referring to  FIG. 3 , the thin film transistor  300  includes a substrate  310 , a buffer layer  320 , a semiconductor layer  330 , a first insulation film  340 , a gate electrode  350   a , a second insulation film  360 , a source/drain electrode  350   b , and a third insulation film  370  formed on the lower surface of the substrate  310 .  
         [0034]     In the third embodiment, the substrate  310  is formed as a flexible metal thin film made of stainless steel, titanium (Ti), etc. In addition, the buffer layer  320  can be formed with a predetermined thickness between 0.3 and 10 μm (or between 0.5 and 5 μm) using a material with a low dielectric constant. In one embodiment, the buffer layer  320  is made of a material with a dielectric constant that is between 1.2 and 4, for example, SiOC, SiOF, Xerogels (nanoporous dielectric), Silsesquioxanes (SOG), etc.  
         [0035]     Specifically, in the third embodiment, the third insulation film  370  is formed on the lower surface of the substrate  310 . The third insulation film  370  is made of SiO 2 , SiN x , etc., and is used to block an unexpected external voltage, external noise, etc., from being applied to the lower surface of the substrate  310  which is a metal thin film.  
         [0036]      FIG. 4  is a cross-sectional view of a thin film transistor  400  according to a fourth embodiment of the present invention. In order to avoid repeating the same descriptions, detailed descriptions for the same structures (or components) that are substantially the same as those disclosed in the first through third embodiments of  FIGS. 1 through 3  are not provided again.  
         [0037]     Referring to  FIG. 4 , the thin film transistor  400  includes a substrate  410 , a diffusion prevention layer  415  formed on the substrate  410 , a buffer layer  420  formed on the diffusion prevention layer  415 , a semiconductor layer  430  formed on the buffer layer  420 , a first insulation film  440  formed on the semiconductor layer  430 , a gate electrode  450   a  formed on the first insulation film  440 , a second insulation film  460  formed on the gate electrode  450   a  and the semiconductor layer  430 , a source/drain electrode  460   b  electrically connected to the semiconductor layer  430  through contact holes  460   a  formed in the second insulation film  460 , and a third insulation film  470  formed on the lower surface of the substrate  410 .  
         [0038]     In the fourth embodiment, the substrate  410  is formed as a flexible metal thin film, and, specifically, is made of stainless steel, titanium (Ti), etc. The buffer layer  420  is applied on the substrate  410 , using a material with a relatively low dielectric constant (low-k). In one embodiment, the buffer layer  420  is made of a material with a dielectric constant that is between 1.2 and 4, such as SiOC, SiOF, Xerogels (nanoporous dielectric), Silsesquioxanes (SOG) and so on. The buffer layer  420  can be formed with a predetermined thickness between 0.3 and 10 μm. Similar to the above-described first through third embodiments, the reason for forming the buffer layer  420  with a low dielectric constant material is to suppress charges that are charged in the buffer layer  420  through the substrate  410  due to static electricity, etc., and to minimize the amount of charges which may be charged in the substrate  410 .  
         [0039]     Also, the diffusion prevention layer  415  is formed between the substrate  410  and the buffer layer  420 . The diffusion prevention layer  415  is provided to block impurities from being diffused into the substrate  410 , and/or to prevent external impurities from inflowing into the buffer layer  420  or the semiconductor layer  430  through the metal thin film  410 , when an amorphous silicon layer is crystallized into a polysilicon layer to form the semiconductor layer  430 . The diffusion prevention layer  415  is formed with tin (Sn), etc. The third insulation film  470  is formed on the lower surface of the substrate  410 , using SiO 2 , SiN x , etc. The third insulation film  470  is provided to block in advance an unintended external voltage, external noise, etc., from inflowing into the lower surface of the substrate  410  which is formed as a metal thin film.  
         [0040]     As described above in the second through fourth embodiments, even when an unintended external voltage, external noise, etc., are applied to a substrate which is formed as a metal thin film made of stainless steel, etc., a charging capacity between the metal thin film and a semiconductor layer can be minimized due to a buffer layer with a low dielectric constant formed between the metal thin film and the semiconductor layer. Also, due to a diffusion prevention layer and/or a third insulation film formed on the substrate, it is possible in advance to block external noise, impurities, etc., from inflowing into main components of a thin film transistor including a semiconductor layer.  
         [0041]     In the first through fourth embodiments described above, by forming a buffer layer with a low dielectric constant between a metal thin film and a semiconductor layer, a charging capacity between the metal thin film and the semiconductor layer is limited. Along with this, the charging capacity can be further limited by adjusting the thickness of the buffer layer.  
         [0042]     As described above, according to the present invention, by in advance blocking an electrical characteristic change (for example, a change in a threshold voltage) of a thin film transistor from occurring when an unintended external voltage is temporarily or momentarily applied, the electrical characteristic change of the thin film transistor can be significantly reduced.  
         [0043]     While the invention has been described in connection with certain exemplary embodiments, it is to be understood by those skilled in the art that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications included within the spirit and scope of the appended claims and equivalents thereof.