Abstract:
An integrated power converter and a method of operation thereof. The integrated power converter, having an energy storage device, includes: (1) a conditioning circuit coupled to the energy storage device and having a control switch for affecting a voltage across the energy storage device, (2) an asymmetrical half-bridge power circuit coupled to the energy storage device and having first and second power switches capable of being alternately activated to conduct current from the energy storage device to an output thereof and (3) a controller for controlling activation of both the control switch and the first and second power switches as a function of a characteristic of the output thereby to enhance a regulation of the output.

Description:
TECHNICAL FIELD OF THE INVENTION 
     The present invention is directed, in general, to power supplies and, more specifically, to an integrated power converter and a method of operation thereof. 
     BACKGROUND OF THE INVENTION 
     Developing highly-efficient power supplies, especially in combination with the ever-increasing constraints of high power density, is a continuing goal in power electronics. A switched-mode power converter or switched-mode converter is a frequently employed component of a power supply that converts an input voltage waveform into a specified output voltage waveform. There are several types of switched-mode converters including, for instance, an asymmetrical half-bridge power converter. 
     A conventional asymmetrical DC/DC half-bridge power converter (&#34;half-bridge converter&#34;) includes two (2) power-switching transistors coupled to a control circuit, at least one input/output isolation transformer, a rectifier and a low-pass filter. The half-bridge converter generally operates as follows. The first and second power-switching transistors alternately conduct current in a complimentary manner to convert an input DC voltage into an AC voltage to be impressed across the isolation transformer. The rectifier, then, rectifies the voltage and the low-pass filter smooths and filters the rectified voltage for delivery to a load being supplied by the half-bridge converter. 
     The control circuit monitors the output voltage of the half-bridge converter and adjusts the duty cycle of the power-switching transistors to ultimately control the output voltage of the half-bridge converter. This degree of control provides a mechanism to maintain the output voltage at a relatively consistent level despite relative fluctuations in the input voltage and the load at the output. 
     In off-line power supply applications, a high power factor is frequently required. While a power factor of unity (i.e., 1.0) is the ultimate goal, a lesser power factor is in some cases considered acceptable in the related field. Therefore, in applications employing a DC/DC power converter or DC/DC converter (e.g., the half-bridge converter), a power factor correcting power converter on the front-end of the DC/DC converter may also be necessary to provide an acceptable power factor for the power supply. 
     A non-isolated boost power converter or boost converter, operating in a continuous conduction mode of operation or in a discontinuous conduction mode of operation with the appropriate control circuitry, may serve as the front-end power converter (i.e., front-end converter) to the half-bridge converter. A conventional boost converter includes an inductor and switching device coupled to an input voltage source of the boost converter. The switching device is then coupled to a diode and a capacitor. The load is connected in parallel to the capacitor. The control circuitry adjusts a duty cycle of the switching device to maintain the output voltage to the load within design parameters; the control circuity also controls the switching device and as a result achieves an instantaneous input current from an AC input in proportion to the instantaneous input voltage. The output voltage of the boost converter is always greater than the input voltage. When the switching device is on, the diode is reverse biased and the input voltage supplies energy to the inductor. When the switching device is off, the output stage receives energy from the inductor and the input voltage source. The boost power factor correcting converter, therefore, provides an acceptable power factor while providing a regulated voltage to the DC/DC converter coupled thereto. 
     While the front-end converters for power factor correction provide a viable solution in power supplies employing DC/DC converters (e.g., the half-bridge converter), the design may be improved for the following reasons. First, the power supply employs two separate power stages, with independent control, to satisfy power conversion to the load. As a result, the overall efficiency of the power supply is reduced because of the inherent inefficiencies associated with two separate and distinctly controlled converter stages in the power supply. Second, employing a boost converter, or other converter topologies, to serve as a power factor corrector adds additional complexity to the power supply. For instance, the boost converter includes a separate control circuit that takes up space and adds complexity to the front-end of the half-bridge converter. With the ever increasing goal of increasing the power density of the power supply, the separate front-end converter detracts from, rather than facilitates, the simplicity of the power supply. 
     Accordingly, what is needed in the art is an integrated power converter with power circuitry and controller that provides a well-regulated output with a sufficiently fast feedback loop for good transient response and, at the same time, provides a high power factor for a power supply employing the integrated power converter to advantage. 
     SUMMARY OF THE INVENTION 
     To address the above-discussed deficiencies of the prior art, the present invention provides an integrated power converter and a method of operation thereof. 
     The integrated power converter, having an energy storage device, includes: (1) a conditioning circuit coupled to the energy storage device and having a control switch for affecting a voltage across the energy storage device, (2) an asymmetrical half-bridge power circuit coupled to the energy storage device and having first and second power switches capable of being alternately activated to conduct current from the energy storage device to an output thereof and (3) a controller for controlling activation of both the control switch and the first and second power switches as a function of a characteristic of the output thereby to enhance a regulation of the output. 
     The present invention provides the advantages of two-stage power converters into an integrated power converter or integrated converter. More specifically, the integrated converter provides power factor correction (e.g., approaching unity power factor) at the input, while at the same time, maintaining a suitable voltage across the energy storage device (coupled between the conditioning circuit and the asymmetrical half-bridge power circuit or half-bridge power circuit) and a well-regulated output to a load coupled to the integrated converter. The integrated converter performs the above-referenced functions with simplicity by employing a single controller and by eliminating additional power mesh components and control circuitry replete in the prior art. The integrated converter produces additional benefits as hereinafter described. For instance, the conditioning circuit may provide protection against input inrush currents prevalent during start-up of a power supply (i.e., soft-start capability). Additionally, the integrated converter provides fast transient response and low output ripple due to a wide frequency band supportable by the controller feedback loop. 
     For the purposes of the present invention, the following terms are broadly defined as follows. A conditioning circuit generally refers to a circuit that conditions an input source for use by a subsequent circuit or system. For instance, the conditioning circuit of the present invention, without limitation, conditions the input source to, or provides, near unity power factor for the integrated converter. In conjunction therewith, the conditioning circuit affects a voltage across the energy storage device. The term, affects, should be construed in its broadest sense to include even indirect results therefrom. For instance, as described below, the control switch of the present invention facilitates the operation of the conditioning circuit to maintain an energy level of the energy storage device thereby varying the voltage, within a acceptable range, thereacross. 
     In an alternative embodiment of the present invention, the conditioning circuit includes an inductor capable of storing energy from an input source (e.g., an AC input source) during a first switching interval or first interval. The inductor is further capable of delivering energy to the energy storage device during a second switching interval or second interval. The inductor operates in a discontinuous conduction mode of operation to achieve power factor correction. In a related embodiment, the controller activates the control switch and the first power switch during the first interval for a duty cycle (D), the control switch providing a first conductive path between the input source and the inductor during the first interval. The controller further activates the second power switch during the second interval for a duty cycle (1-D), the control switch providing a second conductive path between the inductor and the energy storage device during the second interval. 
     The controller, therefore, monitors the output of the half-bridge power circuit and activates the switches in a complementary manner to suitably regulate the output voltage. The control switch and first power switch operate synchronously (i.e., in the same phase) to store energy in the inductor, while at the same time, delivering the previously stored energy from the energy storage device to the output of the integrated converter. In the alternate cycle, the second power switch conducts while the control switch and first power switch are non-conducting. During this interval, the energy from the inductor is transferred to the energy storage device. Again, as a result of the above-described operation, the voltage across the energy storage device is maintained within an acceptable range to optimize the operation of the integrated converter. 
     In an alternative embodiment of the present invention, the conditioning circuit includes a diode. The diode (e.g., a free-wheeling diode) assists in creating the second conductive path for the transfer energy from the inductor to the energy storage device during the second interval of operation. One of ordinary skill in the related art should be aware of the operation and advantages associated with diodes. 
     In an alternative embodiment of the present invention, the control switch and the first and second power switches are each field effect transistors (&#34;FETs&#34;). Switches, such as FETs, are employed in switched-mode power converters (as described herein) because of inherent characteristics of the power converters, such as zero-voltage switching, that augment the overall operation of the power conversion devices. One of ordinary skill in the pertinent art should understand that other switching devices are well within the scope of the present invention. 
     In an alternative embodiment of the present invention, the energy storage device includes a capacitive device. The capacitive device is charged and discharged in order to maintain the operation of the integrated converter. One of ordinary skill in the pertinent art should understand that other energy storage devices are well within the scope of the present invention. 
     In an alternative embodiment, the converter includes a delay circuit, coupled to the controller, for delaying activation of the control switch. The delay circuit, therefore, regulates the voltage across the energy storage device against variations in the load and fluctuations at the input of the integrated converter. The regulated voltage across the energy storage device allows further optimization of the half-bridge power circuit for enhanced performance while maintaining the overall simplicity of the integrated converter. 
     In another aspect of the present invention, the integrated converter is employed in a power supply. The power supply includes: (1) an input for receiving an input AC voltage, (2) an input low-pass filter, coupled to the input, for filtering the input AC voltage, (3) an input rectifier, coupled to the input low-pass filter, for rectifying the input AC voltage and (4) the integrated converter, constructed according to the principles of the present invention, for supplying a well-regulated output voltage to a load coupled thereto. In addition to the power switches, the half-bridge power circuit of the integrated converter generally includes an isolation transformer to provide galvanic primary to secondary isolation for the power supply. In a related embodiment, the half-bridge power circuit also includes an output rectifier and low-pass filter to provide a clean rectified voltage to the load being supplied by the power supply. 
     The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
     FIG. 1 illustrates a representative power supply incorporating an integrated power converter in accordance with the principles of the present invention; 
     FIG. 2 illustrates timing diagrams of the power supply of FIG. 1; 
     FIGS. 3A, 3B illustrate alternative embodiments of power supplies each incorporating an integrated power converter in accordance with the principles of the present invention; 
     FIG. 4 illustrates the power supply of FIG. 1 incorporating a delay circuit according to the principles of the present invention; 
     FIG. 5 illustrates timing diagrams of the power supply of FIG. 4; and 
     FIG. 6 illustrates one embodiment of the delay circuit of FIG. 4 according to the principles of the present invention. 
    
    
     DETAILED DESCRIPTION 
     Referring initially to FIG. 1, illustrated is representative power supply 100 incorporating an integrated power converter or integrated converter 105 in accordance with the principles of the present invention. The integrated converter 105 includes an asymmetrical half-bridge power circuit (&#34;half-bridge power circuit&#34;) 110, a controller 130 (presented within the half-bridge power circuit 110 in the illustrated embodiment) and a conditioning circuit or buck cell 160. The half-bridge power circuit 110 includes power switches 115, 120, an isolation transformer 125, an output rectifier (e.g., diodes 127, 129 in the illustrated embodiment) and an output low-pass filter (e.g., inductor 132 and capacitor 134 in the illustrated embodiment). The power supply 100 further includes an input low-pass filter  e.g., an electromagnetic interference (&#34;EMI&#34;) filter! 135, an input AC full-bridge rectifier or input rectifier 140 and bulk capacitor 180. 
     The buck cell 160 (including a power switch 165, freewheeling diode 170 and inductor 175) is coupled between the input rectifier 140 and bulk capacitor 180. The bulk capacitor 180, as hereinafter described, is charged by the operation of the integrated converter. More specifically, during a first switching interval or first interval the inductor 175 is charged with energy. During a second switching interval or second interval, the energy in the inductor 175 is transferred to the bulk capacitor 180. 
     The operation of the half-bridge power circuit 110 is generally known to those of ordinary skill in the art and, thus, a detailed description will not be provided. Typically, the half-bridge power circuit 110 is a voltage fed DC-to-DC power converter or DC/DC converter that is able to operate over a certain range of DC input voltages, E b  min to E b  max. The input current of the half-bridge power circuit 110, averaged over a switching cycle, at a given load, is inversely related to the DC input bus voltage E b  (e.g., for lower DC input voltages, the half-bridge power circuit 110 typically draws greater input currents). In the integrated converter 105 of the present invention, however, the instantaneous input AC current is proportional to the instantaneous input AC voltage thereby providing a high power factor. The input characteristic of the power supply 100 incorporating the integrated converter 105 emulates a resistor with respect to the AC utility line connected to input terminals 101, 102 (while also maintaining a well-regulated DC voltage at output terminals 103, 104) thereby realizing a power factor near unity. 
     In operation, the AC line voltage is coupled to the input rectifier 140 through the input terminals 101, 102 and input low-pass filter 135. The switching operation of the power switch 165 of the buck cell 160 and the power switches 115, 120 of the integrated converter 105 simultaneously controls two power conversion processes. The first power conversion process is the conversion of AC line voltage, rectified by the input rectifier 140, into a DC bus voltage developed across the bulk capacitor 180. The second power conversion process, accomplished by the half-bridge power circuit 110, is the conversion of the DC bus voltage across bulk capacitor 180 into isolated and well-regulated DC voltage at the output terminals 103, 104. 
     The power switches 115, 120 operate in a complementary manner with duty cycles of D and 1-D, respectively. In a preferred embodiment, the controller 130 is a pulse-width-modulator circuit operative (capable of producing two complimentary power trains D and 1-D) to monitor the DC voltage at the output terminals 103, 104 and adjust the duty cycle D as necessary to maintain precise regulation of the DC voltage. Pulse-width-modulator control circuits are well known to those of ordinary skill in the art. The power switch 165 of the buck cell 160 is also controlled by the controller 130 of the half-bridge power circuit 110 and is operated synchronously (i.e., in phase with) with the power switch 115. 
     The first power conversion process (i.e. the conversion of AC line voltage into a DC bus voltage developed across bulk capacitor 180) is accomplished, in part, during the part of the switching cycle when both the power switch 165 and the power switch 115 are driven on by the controller 130. When both the power switch 165 and the power switch 115 are on, the inductor 175 is charged with energy by a current flowing from the input terminals 101, 102, through the input low-pass filter 135, input rectifier 140 and the power switches 165, 115. In a complementary part of the cycle (i.e. when the power switches 165, 115 are off and the power switch 120 is on), the stored energy in the inductor 175 is delivered into the bulk capacitor 180 through the freewheeling diode 170 and the power switch 120. 
     The second power conversion process occurs simultaneously with the first part of the first power conversion process (i.e., during the period when the power switches 165 and 115 are on and the power switch 120 is off). When the power switch 115 is on, energy stored in the bulk capacitor 180 causes a current to flow through the primary winding of the transformer 125 of the half-bridge power circuit 110. The method employed by the half-bridge power circuit 110 to convert the energy stored in the bulk capacitor 180 into a DC voltage at the output terminals 103, 104 of the power supply 100 is generally known to those of ordinary skilled in the art and, therefore, will not be described. 
     Turning now to FIG. 2, illustrated are timing diagrams of the power supply 100 of FIG. 1. The following waveforms will be described with continuing reference to FIG. 1. More specifically, a pulse train 215 illustrates a control signal, generated by the controller 130, that is applied to the gates of the power switches 115 and 165. A pulse train 220 illustrates a control signal, generated by the controller 130, that is applied to the gate of the power switch 120. Finally, a waveform 230 illustrates a current through the inductor 175. 
     Those of ordinary skill in the art will recognize that the reference in the curves to the letter &#34;T&#34; represents a reciprocal of the switching frequency of the power supply 100; the reference to the letter &#34;D&#34;, in the curves, represents a duty cycle of the power switches. As previously described and demonstrated by the pulse trains 215 and 220, the power switches 115, 120 operate in a complementary manner with duty cycles of D and 1-D, respectively; the power switch 165 of the buck cell 160 is operated synchronously (i.e., in phase with) with the power switch 115. Thus, when both the power switch 165 and the power switch 115 are on, the inductor 175 is charged by a current having a waveform illustrated by a region 231 of the waveform 230. In the complementary part of the cycle (i.e. when the power switches 165, 115 are off and the power switch 120 is on), the energy stored in the inductor 175 is delivered into the bulk capacitor 180 as illustrated by a region 232 of the waveform 230. The process of charging the inductor 175 and thereafter discharging the inductor 175 into the bulk capacitor 180 is repeated every switching cycle. 
     To achieve a power factor approaching unity at the input terminals 101, 102, the inductor 175 operates in a discontinuous conduction mode of operation. Therefore, those of skill in the art will recognize that the value of the inductor 175 should be chosen according to the formula: ##EQU1## where L is the value of the inductor 175, F o  is the switching frequency of the power supply 100, and I m  is the peak inductor current. The value of L should be selected to insure that, for a given range of input voltages and a load across the output terminals 103, 104, the current through the inductor 175 decreases to zero when the inductor 175 discharges all of its energy into the bulk capacitor 180. This &#34;discontinuous conduction mode&#34; of the inductor 175 is illustrated by the waveform 230, where it can be seen that the current of the inductor 175 has a value of zero in a region 233. Satisfaction of the above equation ensures that the current through the inductor 175 ceases flowing before the power switch 120 turns off. 
     A further preferable condition for the proper operation of the power supply 100 is that the voltage E b  across the bulk capacitor (i.e., the voltage at the input voltage of the half-bridge power circuit 110) should be maintained between E b  min and E b  max As those of ordinary skill in the art will recognize, the voltage E b  may be properly maintained by adhering to the following equations: ##EQU2## where: V ac  min and V ac  max the preferred minimum and maximum RMS voltages provided at the input terminals 101, 102, 
     V out  and I out  are the preferred output voltage and current available at the output terminals 103, 104, respectively, 
     L is the value of the inductor 175, 
     F o  is the converter switching frequency, 
     D min  and D max  are the minimum and maximum duty cycles within the preferred operating range, and 
     W dc  (D max ) and W dc  (D min ) are regulating characteristics of the power conversion topology selected for use in the power supply 100. 
     Those of skill in the art will readily appreciate the utility of equations (2), (3), (4), and (5), in selecting the parameters of the power supply 100 to achieve a desired range of operation. 
     Turning now to FIGS. 3A and 3B, illustrated are alternative embodiments of power supplies 300A, 300B incorporating an integrated converter 310, 320, respectively, in accordance with the principles of the present invention. The power supplies 300A, 300B are analogous to the power supply 100 of FIG. 1, with the exception of the particular circuit topology for a half-bridge power circuit 330, 340 employed therein. Those of ordinary skill in the art should understand that the half-bridge power circuits 110, 330, 340 of FIGS. 1, 3A, 3B, respectively, operate in a similar manner and are each operative to be employed in accordance with the principles of the present invention. 
     For an analysis of the operation of analogous half-bridge power circuits in power converters, the readers attention is directed to: (1) U.S. Pat. No. 5,305,191 to Loftus, issued on Apr. 19, 1994, entitled &#34;Drive Circuit for Zero-Voltage Switching Power Converter with Controlled Power Switch Turn-On,&#34; (2) U.S. Pat. No. 5,274,543 to Loftus, issued on Dec. 28, 1993, entitled &#34;Zero-Voltage Switching Power Converter with Lossless Synchronous Rectifier Gate Drive&#34; and (3) U.S. Pat. No. 5,268,830 to Loftus, issued on Dec. 7, 1993, entitled &#34;Drive Circuit for Power Switches of a Zero-Voltage Switching Power Converter,&#34; all commonly assigned with the present invention and herein incorporated by reference. In conjunction therewith, the integrated converters 310, 320 operate analogously to the integrated converter 105 described with respect to FIG. 1. 
     Turning now to FIG. 4, illustrated is the power supply 100 of FIG. 1 incorporating a delay circuit 410 according to the principles of the present invention. The power supply 100 is further improved by introducing a controlled time delay between turning on the power switch 115 and turning on the power switch 165. The delay circuit 410 is equally applicable to the half-bridge power circuits 330, 340 presented with respect to FIGS. 3A, 3B. Additionally, the delay circuit 410 is also applicable in other power supply topologies including, without limitation, pulse width modulator forward converters, bridge converters and single-ended forward converters with an active clamp. While the delay circuit 410 will hereinafter be described, including a function and related advantages, with respect to the half-bridge power circuit 110, one of ordinary skill in the pertinent art should understand that the delay circuit 410 provides analogous benefits to the other power supply topologies employing the delay circuit 410 to advantage. 
     The purpose of introducing the delay circuit 410 is to provide enhanced regulation of the DC bus voltage E b  (across the bulk capacitor 180). The capability of regulating the DC bus voltage E b  against changes in the load connected to the output terminals 103, 104 and variations in the AC utility voltage coupled to the input terminals 101, 102 allows optimization of the half-bridge power circuit 110. The regulation is achieved by slowly modulating the amount of energy stored in the inductor 175 and thereafter delivered into the bulk capacitor 180. Through tight regulation of the DC bus voltage E b , the design of the half-bridge power circuit 110 can be further optimized for greater efficiency, simplicity, and lower component costs (e.g., lower voltage rated switching devices). 
     Turning now to FIG. 5, illustrated are timing diagrams of the power supply 100 of FIG. 4. The following waveforms will be described with continuing reference to FIG. 4. More specifically, a pulse train 515 illustrates a control signal, generated by the controller 130, that is applied to the gate of the power switch 115. A pulse train 520 illustrates a control signal, generated by the controller 130, that is applied to the gate of the power switch 120. A pulse train 525 illustrates a control signal, generated by the controller 130, that is delayed by the delay circuit 410 and then applied to the gate of the power switch 165. Finally, a waveform 530 illustrates the resultant waveform for a current through the inductor 175. 
     Those of ordinary skill in the art will recognize that the reference in the waveforms to the letter &#34;T&#34; represents a reciprocal of the switching frequency of the power supply 100; the reference to the letter &#34;D&#34;, in the waveforms, represents a duty cycle of the power switches. As previously described (see description with respect to FIG. 2) and now demonstrated by the pulse trains 515, 520, the power switches 115, 120 operate in a complementary manner with duty cycles of D and 1-D, respectively. In contrast to the operation of the power supply 100, however, the power switch 165 of the power supply 100 with the delay circuit 410 is not operated synchronously (i.e., in phase with) with the power switch 115. As demonstrated in the pulse train 525 of FIG. 5, the turn-on time for the power switch 165 is delayed from the turn-on time for the power switch 115. Thus, the duty cycle of the power switch 165, and thereby the charging time for the inductor 175, is decreased. 
     When both the power switch 165 and the power switch 115 are on, the inductor 175 is charged by a current having a waveform illustrated by a region 531 of the waveform 530. In the complementary part of the cycle (i.e., when the power switches 165, 115 are off and the power switch 120 is on), the energy stored in the inductor 175 is delivered into the bulk capacitor 180 as illustrated by a region 532 of the waveform 530. The process of charging the inductor 175 and thereafter discharging the inductor 175 into the bulk capacitor 180 is repeated every switching cycle. 
     Turning now to FIG. 6, illustrated is one embodiment of the delay circuit 410 of FIG. 4 according to the principles of the present invention. A delay circuit generally operates as follows. The delay circuit 410, coupled to the bulk capacitor 180, generally monitors the DC bus voltage E b . The voltage E b  across the bulk capacitor 180 is scaled by a voltage divider including a pair of resistors 610, 620. The voltage divider ratio across the resistors 610, 620 has a value of K D . The scaled value of E b  is then amplified by an amplifier 640, having a gain of K, yielding a voltage at the output of the amplifier 640 substantially equal to K·K D  ·E b . 
     The delay circuit 410 is also coupled to a control signal line 670 on which a sawtooth signal associated with the controller 130 is present. This signal is compared by the comparator 650 with the signal at the output of the amplifier 640. The output signal thereby generated by the comparator 650 is a pulse train having a duration of T minus some value substantially equal to a desired time delay, t delay . 
     The delay circuit 410 is further coupled to a control signal line 680 on which the controller 130 generates an appropriate drive signal for the power switch 115. This drive signal consists of a pulse train having a duration substantially equal to D·T. A logic gate 660 of the delay circuit 410 compares the drive signal for the power switch 115 on the control signal line 680 with the output signal generated by the comparator 650 to produce a drive signal for the power switch 165 on the control signal line 675. The drive signal for the power switch 165 has a duration substantially equal to D·T minus t delay . Thus, as previously described, the delayed turn-on of the power switch 165 will decrease the charging of the inductor 175. By decreasing the charging of the inductor 175, less energy is subsequently transferred to the bulk capacitor 180, thereby regulating the DC bus voltage E b  as a function of the time delay, t delay , generated by the delay circuit 410. 
     Those of ordinary skill in the art will recognize that the delay circuit 410 is equally applicable to other asymmetrical half-bridge power conversion circuits (e.g., the half-bridge power circuits 330, 340 illustrated in the power supplies 300A, 300B of FIGS. 3A, 3B, respectively). Moreover, the delay circuit 410 is presented for illustrative purposes only and other delay circuit topologies are well within the scope of the present invention. 
     Although the present invention has been described in detail, those skilled in the art should understand that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the invention in its broadest form.