Abstract:
A method of storing and accessing two data bits in a single ferroelectric FET includes selectively polarizing two distinct ferroelectric regions in the same gate dielectric layer separated by a non-ferroelectric dielectric region. A first ferroelectric region is sandwiched between the substrate and the gate terminal in the region of the source and is polarized in one of two states to form a first data bit within the FET. A second ferroelectric region is sandwiched between the substrate and the gate terminal in the region of the drain and is polarized in one of two states to form a second data bit within the FET. Detection of the first data bit is accomplished by selectively applying a read bias to the FET terminals, a first current resulting when a first state is stored and a second current resulting when a second state is stored. The polarization of the second data bit is accomplished by reversing the source and drain voltages.

Description:
FIELD OF THE INVENTION  
         [0001]    The invention disclosed relates generally to memory cells, and more particularly to ferroelectric nonvolatile memory cells.  
         BACKGROUND OF THE INVENTION  
         [0002]    Ferroelectric transistors are structurally identical to metal-oxide-silicon field effect transistor (MOSFET) devices with the gate oxide layer replaced by a ferroelectric material layer  12 , as shown in FIG. 1. The polarization state of the ferroelectric material layer  12  gives rise to an electric field, which shifts the turn-on threshold voltage of the device  10 . Transistors known in the prior art often include a non-ferroelectric dielectric layer  16  between the ferroelectric material and the silicon substrate  18 , as shown in the device  14  of FIG. 2. This dielectric layer  16  generally has several purposes at the silicon/ferroelectric interface including avoidance of uncontrolled growth of silicon dioxide, avoidance of high electric fields at the interface, separating the ferroelectric materials from the silicon, avoidance of crystal lattice structure mismatch between the silicon and the ferroelectric materials, and keeping hydrogen away from the ferroelectric materials. Such a dielectric layer  16  is sometimes also placed between the top electrode layer  20  and the ferroelectric layer  12  for the same reasons. These devices, such as devices  10  and  14  and variants thereof, are utilized in arrays of rows and columns to form one-transistor (“1T”) non-volatile ferroelectric memories.  
           [0003]    When a voltage greater than a coercive voltage is applied across the ferroelectric material, the ferroelectric material polarizes in the direction aligning with the electric field. When the applied voltage is removed, the polarization state is preserved. When a voltage greater than the coercive voltage is applied to the ferroelectric material in the opposite direction, the polarization in the ferroelectric material reverses. When that electric field is removed, the reversed polarization state remains in the material. The electric field generated by the polarization offsets the natural turn-on threshold of the transistors, effectively shifting the turn-on thresholds of the transistors. By applying known voltages less than the coercive voltage on the terminals of the transistor, the state of the polarization within the ferroelectric material can be detected without altering the stored polarization states, a method known in the prior art as non-destructive read-out.  
           [0004]    These devices are generally electrically connected in an array of rows and columns with common row signals and column signals to form a memory array. A common figure of merit to establish manufacturing costs of these memory arrays is the area utilized per data bit. When utilized in an array of this type, many prior art configurations require additional transistors to provide for the selection of a single device within the array.  
           [0005]    What is desired, therefore, is a minimum area ferroelectric non-volatile memory cell structure and a method of biasing such that a single one-transistor memory cell capable of storing two data bits can be written to and accessed without disturbing other cells within an array.  
         SUMMARY OF THE INVENTION  
         [0006]    According to principles of the present invention, a novel apparatus and method of storing and accessing two bits in a single ferroelectric FET (field effect transistor) exhibiting hysteresis, each FET having gate, source, and drain, terminals and a substrate is disclosed. Ferroelectric material sandwiched between the substrate and the gate terminal in the region of the source is polarized in one of two states to form a first data bit within the FET. Ferroelectric material sandwiched between the substrate and the gate terminal in the region of the drain is polarized in one of two states to form a second data bit within the FET. Non-ferroelectric dielectric is sandwiched between the substrate and the gate terminals in regions between the ferroelectric material in the source region and the ferroelectric material in the drain region. The polarization of the ferroelectric material in the source region changes the threshold voltage of the FET regardless of the polarization state in the drain region. Accordingly, the detection of the first data bit, determined by the polarization state of the material in the source region, is accomplished by applying a read bias to the FET terminals, a first current resulting when a first state is stored and a second current resulting when a second state is stored. The polarization of the second data bit is accomplished by reversing the source and drain voltages. The FETs are electrically connected in an array of rows and columns, the gates of the FETs in a common row connected by a common word line, the sources of the FETs in a common column sharing a common bit line, the drains of the FETs in a common column sharing a common bit line, and the substrate of all FETs sharing a common substrate. Appropriate write voltage biasing of the word lines, bit lines, and substrate provides means for polarizing a single ferroelectric region of a single FET within the array, while leaving the polarization of all other ferroelectric regions unchanged. Appropriate read voltage biasing of the word lines, bit lines, and substrate provides means for detection of the polarization state of a single ferroelectric region of a single FET within the array, a first bit line current determining a first state and a second bit line current determining a second state.  
           [0007]    The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention, which proceeds with reference to the accompanying drawings. 
       
    
    
     DESCRIPTION OF THE DRAWINGS  
       [0008]    [0008]FIG. 1 is a cross section of a ferroelectric transistor as known in the prior art.  
         [0009]    [0009]FIG. 2 is a cross section of a ferroelectric transistor with a bottom buffer layer as is known in the prior art.  
         [0010]    [0010]FIG. 3 is a cross sectional view illustrating the structure of a ferroelectric FET according to one embodiment of the present invention.  
         [0011]    [0011]FIG. 4 illustrates the structure of a ferroelectric FET according to a second embodiment of the present invention wherein the n-type source and drain regions partially or fully overlap the ferroelectric regions.  
         [0012]    [0012]FIG. 5 illustrates a third embodiment wherein the buffer layers below the ferroelectric regions are made of different materials and have a different thickness than the dielectric between the ferroelectric regions.  
         [0013]    [0013]FIG. 6 illustrates a fourth embodiment wherein the top buffer layer is formed between the gate electrode and the top dielectric layer.  
         [0014]    [0014]FIG. 7 illustrates a fifth embodiment wherein the top buffer layers are formed over the ferroelectric regions.  
         [0015]    [0015]FIG. 8 illustrates an example of the applied voltages to the ferroelectric transistor structure in order to polarize a left ferroelectric region to one state.  
         [0016]    [0016]FIG. 9 illustrates an example of a read bias of the ferroelectric FET wherein one n-type region acts as a source.  
         [0017]    [0017]FIG. 10 illustrates an example of a bias that polarizes the ferroelectric material in a left region to a “high state”.  
         [0018]    [0018]FIG. 11 illustrates an example of a read bias of the ferroelectric FET wherein an n-type region acts as a source when the ferroelectric material of region is polarized in the high state.  
         [0019]    [0019]FIG. 12 illustrates an example of the applied voltages to the ferroelectric transistor structure in order to polarize right ferroelectric region to a “low state”.  
         [0020]    [0020]FIG. 13 illustrates an example of a read bias of the ferroelectric FET wherein an n-type region acts as a source.  
         [0021]    [0021]FIG. 14 illustrates an example of a bias that polarizes the ferroelectric material in a right region to a “high state”.  
         [0022]    [0022]FIG. 15 illustrates an example of a read bias of the ferroelectric FET wherein an n-type region acts as a source.  
         [0023]    [0023]FIG. 16 is a plan view diagram illustrating the ferroelectric FET structures placed and electrically connected in rows and columns to form a memory array.  
         [0024]    [0024]FIG. 17 illustrates another embodiment wherein the ferroelectric material is removed between the word lines.  
         [0025]    [0025]FIG. 18 is a schematic diagram illustrating the connection of ferroelectric FETs connected in rows and columns to form a memory array.  
         [0026]    [0026]FIG. 19 is a schematic diagram indicating a bias on the columns and rows to polarize the left ferroelectric region of an FET to a low state according to the present invention.  
         [0027]    [0027]FIG. 20 is a schematic diagram indicating a bias on the columns and rows to polarize the left ferroelectric region of an FET to a high state according to the present invention.  
         [0028]    [0028]FIG. 21 is a schematic diagram indicating a bias on the columns and rows to read the polarized state of the left ferroelectric region of an FET according to the present invention.  
         [0029]    [0029]FIG. 22 illustrates the biasing in order to read the polarization of the right ferroelectric region of an FET according to the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0030]    The present invention discloses a ferroelectric transistor structure exhibiting hysteresis wherein two storage bits are stored in a single device. FIG. 3 is a cross sectional view illustrating the structure of a ferroelectric FET according to one embodiment of the present invention. In a first embodiment, n-type silicon regions  101  and  102  are formed within p-type silicon substrate  100 , the region between them disposing the channel region  103 . A dielectric buffer layer  104  is formed on the channel region  103 . Ferroelectric regions  105  and  106  are formed on dielectric buffer layer  104  in the vicinity of source  101  and drain  102 , and a non-ferroelectric gate oxide layer  107  is formed between these ferroelectric regions  105  and  106 . A gate electrode layer  108  is formed on top of dielectric layer  107  and ferroelectric regions  105  and  106 . In operation, ferroelectric region  105  stores one bit and ferroelectric region  106  stores another bit.  
         [0031]    Ferroelectric regions  105  and  106  can be formed using a sidewall processing technique. The non-ferroelectric gate dielectric  107  is deposited on the buffer layer  104  and patterned, followed by a deposition of a ferroelectric layer. The ferroelectric layer is then planarized using techniques such as chemical mechanical polishing (CMP), thereby removing the ferroelectric material from the top of non-ferroelectric dielectric gate oxide layer  107  but leaving the ferroelectric material on the sides of dielectric gate oxide  107  layer, forming ferroelectric regions  105  and  106  on the sides of dielectric gate oxide layer  107 . The ferroelectric material utilized can be any material exhibiting hysteresis, including ferroelectrics with low dielectric constants and materials having the general formula Al x Mn y O z  where x, y, z vary from 0.1 to 10 and A is a rare earth selected from a group consisting of Ce, Pr, Nd, Pm, Sm, Eu, GD, Th, Dy, Ho, Er, Tm, Yb, Lu, Y or Sc. Ferroelectric materials with low dielectric constants increase the component of voltage across the ferroelectric layer when a voltage is applied across a structure consisting of buffer dielectric layers and ferroelectric layers. Such materials can be produced by any of a variety of methods including sputtering, spin-on gels, and MOCVD (metal-oxide-chemical-vapor-deposition).  
         [0032]    Materials used as the dielectric layer include silicon nitride, silicon dioxide, thermally grown silicon dioxide, and dielectric materials with high dielectric constants. Buffer dielectric materials with high dielectric constants increase the component of voltage across the ferroelectric layer when a voltage is applied across a structure consisting of buffer dielectric layers and ferroelectric layers. More than one material can be layered to form the dielectric layer such as a silicon nitride layer overlying a silicon dioxide layer. Such materials can be formed by any of a variety of methods including ALD (atomic layer deposition), sputtering, and MOCVD.  
         [0033]    Materials used as the electrode layer include metals, doped polysilicon, and metal silicides.  
         [0034]    [0034]FIG. 4 illustrates a second embodiment wherein the n-type region of source  101  and  102  partially or fully overlaps ferroelectric regions  106  and  105 , respectively.  
         [0035]    The substrate is a CMOS compatible silicon substrate or a silicon-on-insulator substrate or the like.  
         [0036]    [0036]FIG. 5 illustrates a third embodiment wherein buffer layer  118  and  119  under ferroelectric regions  105  and  106 , respectively, are formed with a different material and a different thickness from buffer layer  110  under non-ferroelectric gate oxide  107 .  
         [0037]    [0037]FIG. 6 illustrates a fourth embodiment wherein top buffer layer  111  is formed between the gate electrode  108  and the layer consisting of ferroelectric region  105 , gate oxide layer  107 , and ferroelectric region  106 . In this embodiment, this top buffer layer serves to reduce high electric fields at the gate electrode/ferroelectric interface, to contain the ferroelectric materials within an encapsulated region, to reduce leakage currents, and to keep hydrogen away from the ferroelectric materials.  
         [0038]    [0038]FIG. 7 illustrates a fifth embodiment wherein top buffer layers  113  and  112  are formed over ferroelectric regions  105  and  106 , respectively. In this embodiment, no buffer layer is formed between gate electrode layer  108  and the bottom oxide layer  110 .  
         [0039]    [0039]FIG. 8 illustrates an example of the voltages applied to the ferroelectric transistor structure in order to polarize left ferroelectric region  106  to one state, herein referred to as the “low state”. A voltage of +1.5V is applied to the gate electrode −1.5V is applied to n-type region  101 , 0V is applied to n-type region  102 , and −1.5V is applied to substrate  100 , thereby avoiding a forward bias condition between n-type region  101  and substrate  100 . The applied voltage between n-type region  101  and electrode  108  determines the electric field strength on ferroelectric region  106 , while the applied voltage between n-type region  102  and electrode  108  determines the field strength on ferroelectric region  105 . For the purposes of illustration, the coercive voltage is assumed to be 2V. Accordingly, the polarization of ferroelectric region  105  remains unchanged since the applied voltage between n-type region  102  and electrode  108  is 1.5V, less than the coercive voltage. The voltage between n-type region  101  and electrode  108  is 3V, greater than the coercive voltage. It is assumed for the purposes of illustration that voltage drops across bottom buffer layer  104  and the top buffer layer, if there is one, are sufficiently small due to appropriate dielectric constants and thicknesses in order to produce at least a coercive voltage across ferroelectric region  106 . Accordingly, ferroelectric region  106  polarizes to a low state.  
         [0040]    When the applied voltages are removed, the ferroelectric polarization remains. Since ferroelectric region  106  is in the vicinity of n-type region  101 , the electric field affects the turn-on threshold voltage when n-type region  101  is operated as the source of the transistor. The direction of the electric field produced when ferroelectric region  106  is polarized to the “low state” causes the turn-on threshold to be lower than if that same region were not polarized. For the purposes of illustration, the threshold voltage corresponding to the low state is 0.5V.  
         [0041]    [0041]FIG. 9 illustrates an example of a read bias of the ferroelectric FET wherein n-type region  101  acts as a source. A voltage of 1.0V is applied to gate electrode  108 , 0V to n-type region  101  thereby acting as the source, 1.0V to n-type region  102  thereby acting as a drain, and 0V to substrate  100 . Assuming that ferroelectric region  106  is polarized to the low state, the turn-on threshold of the FET is 0.5V. The polarization of the ferroelectric material in region  105  does not affect the threshold voltage since the channel is pinched off in this region, and carriers are injected from the point of pinch-off to the depletion region around the drain. Therefore a current flows from source  101  to drain  102  in this device.  
         [0042]    [0042]FIG. 10 illustrates an example of a bias that polarizes the ferroelectric material in region  106  to a “high state”. A voltage of −1.5V is applied to the gate electrode, +1.5V is applied to n-type region  101 , 0V is applied to n-type region  102 , and 0V is applied to substrate  100 . The applied voltage between n-type region  101  and electrode  108  is higher than the coercive voltage, and the electric field is in the direction to polarize the ferroelectric material to a “high state”. For purposes of illustration, the threshold voltage corresponding to the high state is 1.5V.  
         [0043]    [0043]FIG. 11 illustrates an example of a read bias of the ferroelectric FET wherein n-type region  101  acts as a source when the ferroelectric material of region  106  is polarized in the high state. A voltage of 1.0V is applied to gate electrode  108 , 0V to n-type region  101  thereby acting as the source, 1.0V to n-type region  102  thereby acting as a drain, and 0V to substrate  100 . For the sake of illustration, it is assumed that when the ferroelectric region  106  is polarized to the high state, the turn-on threshold of the FET is 1.5V. The polarization of the ferroelectric material in region  105  does not affect the threshold voltage since the channel in this region is depleted. Since the turn-on threshold voltage is higher than the gate-to-source voltage, no current flows through this device.  
         [0044]    [0044]FIG. 12 illustrates an example of the voltages applied to the ferroelectric transistor structure in order to polarize right ferroelectric region  105  to the “low state”. A voltage of +1.5V is applied to the gate electrode, 0V is applied to n-type region  101 , −1.5V is applied to n-type region  102 , and −1.5V is applied to substrate  100 , thereby avoiding a forward bias condition between n-type region  102  and substrate  100 . The applied voltage between n-type region  102  and electrode  108  is greater than the coercive voltage, while the voltage between n-type region  101  and gate electrode  108  is less than the coercive voltage. Accordingly, the polarization of ferroelectric region  106  remains unchanged since the applied voltage between n-type region  101  and electrode  108  is 1.5V, less than the coercive voltage. The voltage between n-type region  102  and electrode  108  is 3V, greater than the coercive voltage. It is assumed for the purposes of illustration that voltage drops across bottom buffer layer  104  and the top buffer layer  108 , if there is one, are sufficiently small to allow at least a coercive voltage across ferroelectric region  105 . Accordingly, ferroelectric region  105  is polarized to the low state.  
         [0045]    [0045]FIG. 13 illustrates an example of a read bias of the ferroelectric FET wherein n-type region  102  acts as a source. A voltage of 1.0V is applied to gate electrode  108 , 0V to n-type region  102  thereby acting as the source, 1.0V to n-type region  101  thereby acting as a drain, and 0V to substrate  100 . Assuming that ferroelectric region  105  is polarized to the low state, the turn-on threshold of the FET is 0.5V. The polarization of the ferroelectric material in region  106  does not affect the threshold voltage since the channel in this region is depleted. Therefore a current flows from source  102  to drain  101  in this device.  
         [0046]    [0046]FIG. 14 illustrates an example of a bias that polarizes the ferroelectric material in region  105  to a high state. A voltage of −1.5V is applied to the gate electrode, 0V is applied to n-type region  101 , +1.5V is applied to n-type region  102 , and 0V is applied to substrate  100 . The applied voltage between n-type region  102  and electrode  108  is higher than the coercive voltage; the electric field is the direction to polarize the ferroelectric material to a high state, corresponding to a turn-on threshold of 1.5V.  
         [0047]    [0047]FIG. 15 illustrates an example of a read bias of the ferroelectric FET wherein n-type region  102  acts as a source and the ferroelectric region  105  is polarized to the high state. A voltage of 1.0V is applied to gate electrode  108 , 0V to n-type region  102  thereby acting as the source, 1.0V to n-type region  101  thereby acting as a drain, and 0V to substrate  100 . Assuming that ferroelectric region  105  is polarized to the high state, the turn-on threshold of the FET is 1.5V. The polarization of the ferroelectric material in region  106  does not affect the threshold voltage since the channel in this region is depleted. Therefore, no current flows between source  102  to drain  101  in this device.  
         [0048]    Optionally, the voltages used to polarize the ferroelectric regions  105  and  106  can be made significantly larger in magnitude than the voltages used to read the data state. For example, the voltages used to polarize the ferroelectric material might be 5V, while the peak read voltages used are 1V. Successive voltages applied to the device during the read, though less than the coercive voltage, nevertheless may alter the polarization of some ferroelectric materials. By using voltages for read that are low relative to the polarization voltage, potential disturbs to the polarization state that might result are minimized.  
         [0049]    [0049]FIG. 16 is a plan view diagram illustrating the ferroelectric FET structures placed and electrically connected in rows and columns to form a memory array. Gate electrodes of FETs in any given row of the array are connected with a word line. In one embodiment, the word line consists of a strip of conductive thin film  140  or  141  across the array, consisting of any conductive material including platinum, aluminum, polysilicon, and silicides. The source and drains of FETs in any given column of the array are electrically connected. In one embodiment, sources of FETs in a given column are connected with strips of n-type material formed in a p-type substrate, such as diffused bit line  122  of FIG. 16. Drains are similarly connected with diffused bit line  123 . The ferroelectric material is formed on the inside edges of the word line where the bit line intersects the word line. For example, ferroelectric material  133  and  134  are formed along the inside edge of bit line  122  and  123 , respectively. This ferroelectric material may overlap, partially overlap, or underlap the diffused bit line. The region  150  of FIG. 16 is a single cell within the memory array, each terminal marked with the same numbers as used in the cross sectional diagram of FIG. 15. Bit line  122  and bit line  123  under word line  140  form n-type region source/drain  101  and source/drain  102 , respectively. The region between source/drain  101  and  102  disposes the channel region  103 . Above channel  103  is the gate electrode  108 . Ferroelectric regions  105  and  106  in the memory cell are formed where bit line  122  and  123  intersect word line  140 , respectively.  
         [0050]    [0050]FIG. 17 illustrates another embodiment wherein the ferroelectric material is not removed between the word lines. The ferroelectric material without an overlying word line is electrically inactive since the ferroelectric material in those areas has no top electrode.  
         [0051]    [0051]FIG. 18 is a schematic diagram illustrating the connection of ferroelectric FETs connected in rows and columns to form a memory array. The diagram shows word line  140  connecting the gates of FETs  160  and  161 , and word line  141  connecting the gates of FETs  162  and  163 . Columns  120  and  121  connects the sources and drains of FETs  160  and  162 . Columns  122  and  123  connect the sources and drains of FETs  161  and  163 .  
         [0052]    [0052]FIG. 19 is a schematic diagram indicating a bias on the columns and rows to polarize the left ferroelectric region of FET  161  to a low state. A voltage of −1.5V is applied to the selected bit line  122 , and +1.5V on selected word line  140 . A voltage of −1.5V is applied to the substrate to avoid the n-type regions forward biasing to the substrate. More than a coercive voltage is thereby applied across left ferroelectric region of FET  161 , polarizing it to a low state. 0V is applied to unselected word lines and bit lines, thereby applying less than a coercive voltage to right ferroelectric region of FET  161 , and so this polarization stays unchanged. This same bias is applied to the left and right ferroelectric regions of FETs along the selected word line on deselected bit lines, for example FET  160  of FIG. 19. FET  163  illustrates that less than a coercive voltage is also applied to an FET on a deselected word line but selected bit line. FET  162  is an example of an FET bias on a deselected word line and deselected bit lines. In this case, no electric field is applied across the ferroelectric regions of the device, thereby leaving the polarization unchanged.  
         [0053]    [0053]FIG. 20 is a schematic diagram indicating a bias on the columns and rows to polarize the left ferroelectric region of FET  161  to a high state. A voltage of +1.5V is applied to the selected bit line  122 , and −1.5V on selected word line  140 . The substrate is biased to 0V More than a coercive voltage is thereby applied across left ferroelectric region of FET  161 , polarizing it to a high state. 0V is applied to unselected word lines and bit lines, thereby applying less than a coercive voltage to right ferroelectric region of FET  161 , and so this polarization stays unchanged. This same bias is applied to the left and right ferroelectric regions of FETs along the selected word line on deselected bit lines, for example FET  160  of FIG. 20. FET  163  illustrates that less than a coercive voltage is also applied to an FET on a deselected word line but selected bit line. FET  162  is an example of an FET bias on a deselected word line and deselected bit lines. In this case, no electric field is applied across the ferroelectric regions of the device, thereby leaving the polarization unchanged.  
         [0054]    [0054]FIG. 21 is a schematic diagram indicating a bias on the columns and rows to read the polarized state of left ferroelectric region of FET  161 . A voltage of +1.0V is applied to selected word line  140 . 0V is applied to the bit line connected to the left n-type region of FET  161 , that n-type region thereby acting as the source. The gate-to-source voltage is therefore 1.0V. 1.0V is applied to the other n-type region of FET  161 , thereby acting as the drain. If the high state is stored on the left ferroelectric, FET  161  remains off since the turn-on threshold of FET  161  would then be 1.5V, higher than the applied gate-to-source voltage. If a low state is stored in the left ferroelectric, FET  161  turns on since the turn-on threshold of the FET is 0.5V, less than the gate-to-source voltage.  
         [0055]    No current flows through any other device in the array. The FETs along the selected word line, such as FET  160 , have 0V on both the source and drain. The FETs along the unselected word line, such as FETs  162  and  163 , have 0V on the gate.  
         [0056]    [0056]FIG. 22 illustrates the biasing in order to read the polarization of the right ferroelectric region of FET  161 . Biasing is identical to FIG. 21, except that the voltages on bit line  122  and  123  are reversed. Now the right n-type region acts as source of FET  161 . Measuring the resulting current determines the polarization state, high current corresponding to a low state and low current corresponding to a high state.  
         [0057]    The foregoing description is only illustrative of the invention. Various alternatives and modifications can be devised by those skilled in the art without departing from the invention. In particular, though reference to a ferroelectric FET formed on a P-type silicon substrate and N-type source and drain regions has been made, the ferroelectric FET can also be formed on N-type substrate with P-type source and drain regions. Though mention is made of a single dielectric buffer layer, this layer could be composed of multiple layers without departing from the invention. Though specific bias voltages are described in the foregoing description, other voltage values can be utilized without departing from the present invention. Accordingly, the present invention embraces all such alternatives, modifications, and variances that fall within the scope of the appended claims.