Abstract:
A 3D IC device including: a first semiconductor layer including first mono-crystallized transistors, where the first mono-crystallized transistors are interconnected by at least one metal layer including aluminum or copper; a second layer including second mono-crystallized transistors and overlaying the at least one metal layer, where the at least one metal layer is in-between the first semiconductor layer and the second layer; a global power grid to distribute power to the device overlaying the second layer; and a local power grid to distribute power to the first mono-crystallized transistors, where the global power grid is connected to the local power grid by a plurality of through second layer vias, and where the vias have a radius of less than 150 nm.

Description:
[0001]    This application is a continuation-in-part of U.S. patent application Ser. No. 13/623,756, filed on Sep. 20, 2012, which is a continuation of U.S. patent application Ser. No. 13/635,436, filed on Sep. 16, 2012, now U.S. Pat. No. 8,642,416 issued on Feb. 4, 2014, which is a national stage application into the USPTO of PCT/US2011/042071 of international filing date Jun. 28, 2011. The contents of the foregoing applications are incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The invention relates to the general field of Integrated Circuit (IC) devices and fabrication methods, and more particularly to multilayer or Three Dimensional Integrated Circuit (3D-IC) devices. 
         [0004]    2. Discussion of Background Art 
         [0005]    Over the past 40 years, one has seen a dramatic increase in functionality and performance of Integrated Circuits (ICs). This has largely been due to the phenomenon of “scaling” i.e. component sizes within ICs have been reduced (“scaled”) with every successive generation of technology. There are two main classes of components in Complementary Metal Oxide Semiconductor (CMOS) ICs, namely transistors and wires. With “scaling”, transistor performance and density typically improve and this has contributed to the previously-mentioned increases in IC performance and functionality. However, wires (interconnects) that connect together transistors degrade in performance with “scaling”. The situation today may be that wires dominate performance, functionality and power consumption of ICs. 
         [0006]    3D stacking of semiconductor chips may be one avenue to tackle issues with wires. By arranging transistors in 3 dimensions instead of 2 dimensions (as was the case in the 1990s), one can place transistors in ICs closer to each other. This reduces wire lengths and keeps wiring delay low. However, there are many barriers to practical implementation of 3D stacked chips. These include:
       Constructing transistors in ICs typically require high temperatures (higher than ˜700° C.) while wiring levels are constructed at low temperatures (lower than ˜400° C.). Copper or Aluminum wiring levels, in fact, can get damaged when exposed to temperatures higher than ˜400° C. If one would like to arrange transistors in 3 dimensions along with wires, it has the challenge described below. For example, let us consider a 2 layer stack of transistors and wires i.e. Bottom Transistor Layer, above it Bottom Wiring Layer, above it Top Transistor Layer and above it Top Wiring Layer. When the Top Transistor Layer may be constructed using Temperatures higher than 700° C., it can damage the Bottom Wiring Layer.   Due to the above mentioned problem with forming transistor layers above wiring layers at temperatures lower than 400° C., the semiconductor industry has largely explored alternative architectures for 3D stacking. In these alternative architectures, Bottom Transistor Layers, Bottom Wiring Layers and Contacts to the Top Layer are constructed on one silicon wafer. Top Transistor Layers, Top Wiring Layers and Contacts to the Bottom Layer are constructed on another silicon wafer. These two wafers are bonded to each other and contacts are aligned, bonded and connected to each other as well. Unfortunately, the size of Contacts to the other Layer may be large and the number of these Contacts may be small. In fact, prototypes of 3D stacked chips today utilize as few as 10,000 connections between two layers, compared to billions of connections within a layer. This low connectivity between layers may be because of two reasons: (i) Landing pad size needs to be relatively large due to alignment issues during wafer bonding. These could be due to many reasons, including bowing of wafers to be bonded to each other, thermal expansion differences between the two wafers, and lithographic or placement misalignment. This misalignment between two wafers limits the minimum contact landing pad area for electrical connection between two layers; (ii) The contact size needs to be relatively large. Forming contacts to another stacked wafer typically involves having a Through-Silicon Via (TSV) on a chip. Etching deep holes in silicon with small lateral dimensions and filling them with metal to form TSVs may be not easy. This places a restriction on lateral dimensions of TSVs, which in turn impacts TSV density and contact density to another stacked layer. Therefore, connectivity between two wafers may be limited.       
 
         [0009]    It may be highly desirable to circumvent these issues and build 3D stacked semiconductor chips with a high-density of connections between layers. To achieve this goal, it may be sufficient that one of three requirements must be met: (1) A technology to construct high-performance transistors with processing temperatures below ˜400° C.; (2) A technology where standard transistors are fabricated in a pattern, which allows for high density connectivity despite the misalignment between the two bonded wafers; and (3) A chip architecture where process temperature increase beyond 400° C. for the transistors in the top layer does not degrade the characteristics or reliability of the bottom transistors and wiring appreciably. This patent application describes approaches to address options (1), (2) and (3) in the detailed description section. In the rest of this section, background art that has previously tried to address options (1), (2) and (3) will be described. 
         [0010]    U.S. Pat. No. 7,052,941 from Sang-Yun Lee (“S-Y Lee”) describes methods to construct vertical transistors above wiring layers at less than 400° C. In these single crystal Si transistors, current flow in the transistor&#39;s channel region may be in the vertical direction. Unfortunately, however, almost all semiconductor devices in the market today (logic, DRAM, flash memory) utilize horizontal (or planar) transistors due to their many advantages, and it may be difficult to convince the industry to move to vertical transistor technology. 
         [0011]    A paper from IBM at the Intl. Electron Devices Meeting in 2005 describes a method to construct transistors for the top stacked layer of a 2 chip 3D stack on a separate wafer. This paper is “Enabling SOI-Based Assembly Technology for Three-Dimensional (3D) Integrated Circuits (ICs),”  IEDM Tech. Digest , p. 363 (2005) by A. W. Topol, D. C. La Tulipe, L. Shi, et al. (“Topol”). A process flow may be utilized to transfer this top transistor layer atop the bottom wiring and transistor layers at temperatures less than 400° C. Unfortunately, since transistors are fully formed prior to bonding, this scheme suffers from misalignment issues. While Topol describes techniques to reduce misalignment errors in the above paper, the techniques of Topol still suffer from misalignment errors that limit contact dimensions between two chips in the stack to &gt;130 nm. 
         [0012]    The textbook “Integrated Interconnect Technologies for 3D Nanoelectronic Systems” by Bakir and Meindl (“Bakir”) describes a 3D stacked DRAM concept with horizontal (i.e. planar) transistors. Silicon for stacked transistors may be produced using selective epitaxy technology or laser recrystallization Unfortunately, however, these technologies have higher defect density compared to standard single crystal silicon. This higher defect density degrades transistor performance. 
         [0013]    In the NAND flash memory industry, several organizations have attempted to construct 3D stacked memory. These attempts predominantly use transistors constructed with poly-Si or selective epi technology as well as charge-trap concepts. References that describe these attempts to 3D stacked memory include “Integrated Interconnect Technologies for 3D Nanoelectronic Systems”, Artech House, 2009 by Bakir and Meindl (“Bakir”), “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory”, Symp. VLSI Technology Tech. Dig. pp. 14-15, 2007 by H. Tanaka, M. Kido, K. Yahashi, et al. (“Tanaka”), “A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device,” Symposium on VLSI Technology, 2010 by W. Kim, S Choi, et al. (“W. Kim”), “A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device,” Symposium on VLSI Technology, 2010 by Hang-Ting Lue, et al. (“Lue”) and “Sub-50 nm Dual-Gate Thin-Film Transistors for Monolithic 3-D Flash”, IEEE Trans. Elect. Dev., vol. 56, pp. 2703-2710, November 2009 by A. J. Walker (“Walker”). An architecture and technology that utilizes single crystal Silicon using epi growth is described in “A Stacked SONOS Technology, Up to 4 Levels and 6 nm Crystalline Nanowires, with Gate-All-Around or Independent Gates (φFlash), Suitable for Full 3D Integration”, International Electron Devices Meeting, 2009 by A. Hubert, et al (“Hubert”). However, the approach described by Hubert has some challenges including the use of difficult-to-manufacture nanowire transistors, higher defect densities due to formation of Si and SiGe layers atop each other, high temperature processing for long times, and difficult manufacturing. 
         [0014]    It is clear based on the background art mentioned above that invention of novel technologies for 3D stacked chips will be useful. 
         [0015]    Three dimensional integrated circuits are known in the art, though the field may be in its infancy with a dearth of commercial products. Many manufacturers sell multiple standard two dimensional integrated circuit (2DIC) devices in a single package known as a Multi-Chip Modules (MCM) or Multi-Chip Packages (MCP). Often these 2DICs are laid out horizontally in a single layer, like the Core 2 Quad microprocessor MCMs available from Intel Corporation of Santa Clara, Calif. In other products, the standard 2DICs are stacked vertically in the same MCP like in many of the moviNAND flash memory devices available from Samsung Electronics of Seoul, South Korea like the illustration shown in  FIG. 81C . None of these products are true 3DICs. 
         [0016]    Devices where multiple layers of silicon or some other semiconductor (where each layer comprises active devices and local interconnect like a standard 2DIC) are bonded together with Through Silicon Via (TSV) technology to form a true 3D IC have been reported in the literature in the form of abstract analysis of such structures as well as devices constructed doing basic research and development in this area.  FIG. 81A  illustrates an example in which Through Silicon Vias are constructed continuing vertically through all the layers creating a global interlayer connection.  FIG. 81B  provides an illustration of a 3D IC system in which a Through Silicon Via  8104  may be placed at the same relative location on the top and bottom of all the 3D IC layers creating a standard vertical interface between the layers. 
         [0017]    Constructing future 3DICs may require new architectures and new ways of thinking. In particular, yield and reliability of extremely complex three dimensional systems will have to be addressed, particularly given the yield and reliability difficulties encountered in complex Application Specific Integrated Circuits (ASIC) built in recent deep submicron process generations. 
         [0018]    Fortunately, current testing techniques will likely prove applicable to 3D IC manufacturing, though they will be applied in very different ways.  FIG. 100  illustrates a prior art set scan architecture in a 2D IC ASIC  10000 . The ASIC functionality may be present in logic clouds  10020 ,  10022 ,  10024  and  10026  which are interspersed with sequential cells like, for example, pluralities of flip flops indicated at  10012 ,  10014  and  10016 . The ASIC  10000  also has input pads  10030  and output pads  10040 . The flip flops are typically provided with circuitry to allow them to function as a shift register in a test mode. In  FIG. 100  the flip flops form a scan register chain where pluralities of flip flops  10012 ,  10014  and  10016  are coupled together in series with Scan Test Controller  10010 . One scan chain may be shown in  FIG. 100 , but in a practical design comprising millions of flip flops many sub-chains will be used. 
         [0019]    In the test architecture of  FIG. 100 , test vectors are shifted into the scan chain in a test mode. Then the part may be placed into operating mode for one or more clock cycles, after which the contents of the flip flops are shifted out and compared with the expected results. This provides an excellent way to isolate errors and diagnose problems, though the number of test vectors in a practical design can be very large and an external tester may be often required. 
         [0020]      FIG. 101  shows a prior art boundary scan architecture in exemplary ASIC  10100 . The part functionality may be shown in logic function block  10110 . The part also has a variety of input/output cells  10120 , each comprising a bond pad  10122 , an input buffer  10124 , and a tri-state output buffer  10126 . Boundary Scan Register Chains  10132  and  10134  are shown coupled in series with Scan Test Control block  10130 . This architecture operates in a similar manner as the set scan architecture of  FIG. 100 . Test vectors are shifted in, the part may be clocked, and the results are then shifted out to compare with expected results. Typically, set scan and boundary scan are used together in the same ASIC to provide complete test coverage. 
         [0021]      FIG. 102  shows a prior art Built-In Self Test (BIST) architecture for testing a logic block  10200  which comprises a core block function  10210  (what is being tested), inputs  10212 , outputs  10214 , a BIST Controller  10220 , an input Linear Feedback Shift Register (LFSR)  10222 , and an output Cyclical Redundancy Check (CRC) circuit  10224 . Under control of BIST Controller  10220 , LFSR  10222  and CRC  10224  are seeded (set to a known starting value), the logic block  10200  may be clocked a predetermined number of times with LFSR  10222  presenting pseudo-random test vectors to the inputs of Block Function  10210  and CRC  10224  monitoring the outputs of Block Function  10210 . After the predetermined number of clocks, the contents of CRC  10224  are compared to the expected value (or “signature”). If the signature matches, logic block  10200  passes the test and may be deemed good. This sort of testing may be good for fast “go” or “no go” testing as it may be self-contained to the block being tested and does not require storing a large number of test vectors or use of an external tester. BIST, set scan, and boundary scan techniques are often combined in complementary ways on the same ASIC. A detailed discussion of the theory of LSFRs and CRCs can be found in Digital Systems Testing and Testable Design, by Abramovici, Breuer and Friedman, Computer Science Press, 1990, pp 432-447. 
         [0022]    Another prior art technique that may be applicable to the yield and reliability of 3DICs is Triple Modular Redundancy. This may be a technique where the circuitry may be instantiated in a design in triplicate and the results are compared. Because two or three of the circuit outputs are always assumed in agreement (as may be the case assuming single error and binary signals) voting circuitry (or majority-of-three or MAJ3) takes that as the result. While primarily a technique used for noise suppression in high reliability or radiation tolerant systems in military, aerospace and space applications, it also can be used as a way of masking errors in faulty circuits since if any two of three replicated circuits are functional the system will behave as if it may be fully functional. A discussion of the radiation tolerant aspects of Triple Modular Redundancy systems, Single Event Effects (SEE), Single Event Upsets (SEU) and Single Event Transients (SET) can be found in U.S. Patent Application Publication 2009/0204933 to Rezgui (“Rezgui”). 
         [0023]    Over the past 40 years, there has been a dramatic increase in functionality and performance of Integrated Circuits (ICs). This has largely been due to the phenomenon of “scaling”; i.e., component sizes within ICs have been reduced (“scaled”) with every successive generation of technology. There are two main classes of components in Complementary Metal Oxide Semiconductor (CMOS) ICs, namely transistors and wires. With “scaling”, transistor performance and density typically improve and this has contributed to the previously-mentioned increases in IC performance and functionality. However, wires (interconnects) that connect together transistors degrade in performance with “scaling”. The situation today may be that wires dominate performance, functionality and power consumption of ICs. 
         [0024]    3D stacking of semiconductor devices or chips may be one avenue to tackle the issues with wires. By arranging transistors in 3 dimensions instead of 2 dimensions (as was the case in the 1990s), the transistors in ICs can be placed closer to each other. This reduces wire lengths and keeps wiring delay low. 
         [0025]    There are many techniques to construct 3D stacked integrated circuits or chips including: 
         [0026]    Through-silicon via (TSV) technology: Multiple layers of transistors (with or without wiring levels) can be constructed separately. Following this, they can be bonded to each other and connected to each other with through-silicon vias (TSVs). 
         [0027]    Monolithic 3D technology: With this approach, multiple layers of transistors and wires can be monolithically constructed. Some monolithic 3D and 3DIC approaches are described in U.S. Pat. Nos. 8,273,610, 8,557,632, 8,298,875, 8,642,416, 8,362,482, 8,378,715, 8,379,458, 8,450,804, 8,574,929, 8,581,349, 8,642,416, 8,687,399, 8,742,476, 8,674,470, 8,803,206, 8,902,663, 8,994,404, 9,021,414, 9,023,688, 9,030,858; US patent publications 2011/0092030 and 2013/0020707; and pending U.S. patent application Ser. Nos. 13/836,080, 62/077,280, 62/042,229, 13/803,437, 61/932,617, 14/607,077, 14/642,724, 62/139,636, 62/149,651, and 62/198,126. The entire contents of the foregoing patents, publications, and applications are incorporated herein by reference. 
         [0028]    Electro-Optics: There is also work done for integrated monolithic 3D including layers of different crystals, such as U.S. Pat. No. 8,283,215, U.S. Pat. Nos. 8,163,581, 8,753,913, 8,823,122, and U.S. patent application Ser. Nos. 13/274,161 and 14/461,539. The entire contents of the foregoing patents, publications, and applications are incorporated herein by reference. 
         [0029]    Irrespective of the technique used to construct 3D stacked integrated circuits or chips, heat removal may be a serious issue for this technology. For example, when a layer of circuits with power density P may be stacked atop another layer with power density P, the net power density may be 2P. Removing the heat produced due to this power density may be a significant challenge. In addition, many heat producing regions in 3D stacked integrated circuits or chips have a high thermal resistance to the heat sink, and this makes heat removal even more difficult. 
         [0030]    Several solutions have been proposed to tackle this issue of heat removal in 3D stacked integrated circuits and chips. These are described in the following paragraphs. 
         [0031]    Many publications have suggested passing liquid coolant through multiple device layers of a 3D-IC to remove heat. This is described in “Microchannel Cooled 3D Integrated Systems”, Proc. Intl Interconnect Technology Conference, 2008 by D. C. Sekar, et al and “Forced Convective Interlayer Cooling in Vertically Integrated Packages,” Proc. Intersoc. Conference on Thermal Management (ITHERM), 2008 by T. Brunschweiler, et al. 
         [0032]    Thermal vias have been suggested as techniques to transfer heat from stacked device layers to the heat sink. Use of power and ground vias for thermal conduction in 3D-ICs has also been suggested. These techniques are described in “Allocating Power Ground Vias in 3D ICs for Simultaneous Power and Thermal Integrity” ACM Transactions on Design Automation of Electronic Systems (TODAES), May 2009 by Hao Yu, Joanna Ho and Lei He. 
         [0033]    Other techniques to remove heat from 3D Integrated Circuits and Chips will be beneficial. 
       SUMMARY 
       [0034]    In one aspect, a 3D IC device comprising: a first semiconductor layer comprising first mono-crystallized transistors, wherein said first mono-crystallized transistors are interconnected by at least one metal layer comprising aluminum or copper; a second layer comprising second mono-crystallized transistors and overlaying said at least one metal layer, wherein said at least one metal layer is in-between said first semiconductor layer and said second layer; a global power grid to distribute power to said device overlaying said second layer; and a local power grid to distribute power to said first mono-crystallized transistors, wherein said global power grid is connected to said local power grid by a plurality of through second layer vias, and wherein said vias have a radius of less than 150 nm. 
         [0035]    In another aspect, a 3D IC device comprising: a first semiconductor layer comprising first mono-crystallized transistors, wherein said first mono-crystallized transistors are interconnected by a plurality of metal layers comprising aluminum or copper; a second layer comprising second mono-crystallized transistors and overlaying said plurality of metal layers; a plurality of thermally conductive paths from said second mono-crystallized transistors to an external surface of said device, wherein said plurality of metal layers is disposed between said first semiconductor layer and said second layer, and wherein said first mono-crystallized transistor channels comprise a first atomic material, and said second mono-crystallized transistor channels comprise a second atomic material, wherein said first atomic material is substantially different from said second atomic material. 
         [0036]    In another aspect, a 3D IC device comprising: a first semiconductor layer comprising first mono-crystallized transistors, wherein said first mono-crystallized transistors are interconnected by a plurality of metal layers comprising aluminum or copper; and a second layer comprising second mono-crystallized transistors and overlaying said plurality of metal layers, wherein said plurality of metal layers is in-between said first semiconductor layer and said second layer, and wherein said second mono-crystallized transistors comprise a silicided source and drain. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0037]    Various embodiments of the invention will be understood and appreciated more fully from the following detailed description, taken in conjunction with the drawings in which: 
           [0038]      FIG. 1A-1E  shows a description of Ge or III-V semiconductor Layer Transfer Flow using Ion-Cut; 
           [0039]      FIG. 2A-2K  illustrates constructing chips with nMOS and pMOS devices on either side of the wafer; 
           [0040]      FIG. 3  illustrates constructing transistors with front gates and back gates on either side of the semiconductor layer; 
           [0041]      FIG. 4A-41  illustrate a process flow that forms silicide regions before layer transfer; 
           [0042]      FIG. 5A-5E  illustrates a technique to construct 3D stacked trench MOSFETs; 
           [0043]      FIG. 6A-6C  illustrates a technique to construct dopant segregated transistors compatible with 3D stacking; 
           [0044]      FIG. 7  is a drawing illustration of a 3D integrated circuit; 
           [0045]      FIG. 8  is a drawing illustration of another 3D integrated circuit; 
           [0046]      FIG. 9  is a drawing illustration of the power distribution network of a 3D integrated circuit; 
           [0047]      FIG. 10  is a drawing illustration of a NAND gate; 
           [0048]      FIG. 11  is a drawing illustration of the thermal contact concept; 
           [0049]      FIG. 12  is a drawing illustration of various types of thermal contacts; 
           [0050]      FIG. 13  is a drawing illustration of another type of thermal contact; 
           [0051]      FIG. 14  illustrates the use of heat spreaders in 3D stacked device layers; 
           [0052]      FIG. 15  is a drawing illustration of a technique to remove heat more effectively from silicon-on-insulator (SOI) circuits; 
           [0053]      FIG. 16  is a drawing illustration of an alternative technique to remove heat more effectively from silicon-on-insulator (SOI) circuits; and 
           [0054]      FIG. 17  is a drawing illustration of a 3D-IC with thermally conductive material on the sides. 
       
    
    
     DETAILED DESCRIPTION 
       [0055]    Embodiments of the invention are now described with reference to  FIGS. 1-17 , it being appreciated that the figures illustrate the subject matter not to scale or to measure. Many figures describe process flows for building devices. These process flows, which are essentially a sequence of steps for building a device, have many structures, numerals and labels that are common between two or more adjacent steps. In such cases, some labels, numerals and structures used for a certain step&#39;s figure may have been described in previous steps&#39; figures. 
         [0056]    Embodiments of the invention are now described with reference to the drawing figures. Persons of ordinary skill in the art will appreciate that the description and figures illustrate rather than limit the invention and that in general the figures are not drawn to scale for clarity of presentation. Such skilled persons will also realize that many more embodiments are possible by applying the inventive principles contained herein and that such embodiments fall within the scope of the invention which is not to be limited except by the spirit of the appended claims. 
         [0057]      FIG. 5A-E  depicts a process flow for constructing 3D stacked logic circuits and chips using trench MOSFETs. These types of devices are typically used in power semiconductor applications. These devices can also be utilized for forming 3D stacked circuits and chips with no process steps performed at greater than about 400° C. (after wafer to wafer bonding). The process flow in  FIG. 5A-E  may include several steps in the following sequence: 
         [0000]    Step (A): The bottom layer of the 2 chip 3D stack may be processed with transistors and wires. This is indicated in the figure as bottom layer of transistors and wires  502 . Above this, a silicon dioxide layer  504  may be deposited.  FIG. 5A  illustrates the structure after Step (A).
 
Step (B): Using the procedure similar to the one shown in  FIG. 11A-F  of incorporated by reference parent application, a p− Si layer  505 , two n+ Si regions  503  and  507  and a silicide region  598  may be transferred atop the structure shown after Step (A).  501  represents a silicon oxide region.  FIG. 5B  illustrates the structure after Step (B).
 
Step (C): The stack shown after Step (B) may be patterned lithographically and etched such that silicon and silicide regions may be present only in regions where transistors and contacts are to be formed. Using a shallow trench isolation (STI) process, isolation regions in between transistor regions may be formed.  FIG. 5C  illustrates the structure after Step (C). n+ Si regions after this step are indicated as n+ Si  508  and  596  and p− Si regions after this step are indicated as p− Si region  506 . Oxide regions are indicated as Oxide  514 . Silicide regions after this step are indicated as  594 .
 
Step (D): Using litho and etch, a trench may be formed by etching away the n+ Si region  508  and p− Si region  506  (from  FIG. 5C ) where gates need to be formed. The angle of the etch may be varied such that either a U shaped trench or a V shaped trench may be formed. A chemical dry etch process is described in “The breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor(RCAT) for 88 nm feature size and beyond,”  VLSI Technology,  2003.  Digest of Technical Papers.  2003  Symposium on , vol., no., pp. 11-12, 10-12 Jun. 2003 by Kim, J Y; Lee, C S; Kim, S. E., et al. (“J. Y. Kim”). A variation of this process from J. Y. Kim can be utilized for rounding corners, removing damaged silicon, etc. after the etch. Furthermore, Silicon Dioxide can be formed using a plasma-enhanced thermal oxidation process, this oxide can be etched-back as well to reduce damage from etching silicon.  FIG. 5D  illustrates the structure after Step (D). n+ Si regions after this step are indicated as  509 ,  592  and  595  and p− Si regions after this step are indicated as p− Si regions  511 .
 
Step (E): The gate dielectric material and the gate electrode material may be deposited, following which a CMP process may be utilized for planarization. The gate dielectric material could be hafnium oxide. Alternatively, silicon dioxide can be used. Other types of gate dielectric materials such as Zirconium oxide can be utilized as well. The gate electrode material could be Titanium Nitride. Alternatively, other materials such as TaN, W, Ru, TiAlN, polysilicon could be used. Litho and etch may be conducted to leave the gate dielectric material  510  and the gate electrode material  512  only in regions where gates are to be formed.  FIG. 5E  illustrates the structure after Step (E). In the transistor shown in  FIG. 5E , n+ Si regions  509  and  592  may be drain regions of the MOSFET, p− Si regions  511  may be channel regions and n+ Si region  595  may be a source region of the MOSFET. Alternatively, n+ Si regions  509  and  592  may be source regions of the MOSFET and n+ Si region  595  may be a drain region of the MOSFET. Following this, rest of the process flow continues, with contact and wiring layers being formed.
 
         [0058]    It may be apparent based on the process flow shown in  FIG. 5A-E  that no process step at greater than about 400° C. may be required after stacking the top layer of transistors above the bottom layer of transistors and wires. While the process flow shown in  FIG. 5A-E  gives several steps involved in forming a trench MOSFET for 3D stacked circuits and chips, it is conceivable to one skilled in the art that changes to the process can be made. 
         [0059]      FIGS. 1A-E  depict layer transfer of a Germanium or a III-V semiconductor layer to form part of a 3D integrated circuit or chip or system. These layers could be utilized for forming optical components or form forming better quality (higher-performance or lower-power) transistors.  FIG. 1A-E  describes an ion-cut flow for layer transferring a single crystal Germanium or III-V semiconductor layer  107  atop any generic bottom layer  102 . The bottom layer  102  can be a single crystal silicon layer or some other semiconductor layer. Alternatively, it can be a wafer having transistors with wiring layers above it. This process of ion-cut based layer transfer may include several steps as described in the following sequence: 
         [0000]    Step (A): A silicon dioxide layer  104  may be deposited above the generic bottom layer  102 .  FIG. 1A  illustrates the structure after Step (A).
 
Step (B): The layer to be transferred atop the bottom layer (top layer of doped germanium or III-V semiconductor  106 ) may be processed and a compatible oxide layer  108  may be deposited above it.  FIG. 1B  illustrates the structure after Step (B).
 
Step (C): Hydrogen may be implanted into the Top layer doped Germanium or III-V semiconductor  106  at a certain depth  110 . Alternatively, another atomic species such as helium can be (co-)implanted.  FIG. 1C  illustrates the structure after Step (C).
 
Step (D): The top layer wafer shown after Step (C) may be flipped and bonded atop the bottom layer wafer using oxide-to-oxide bonding.  FIG. 1D  illustrates the structure after Step (D).
 
Step (E): A cleave operation may be performed at the hydrogen plane  110  using an anneal or a mechanical force. Following this, a Chemical-Mechanical-Polish (CMP) may be done.  FIG. 1E  illustrates the structure after Step (E).
 
         [0060]    Section 1 described the formation of 3D stacked semiconductor circuits and chips with sub-400° C. processing temperatures to build transistors and high density of vertical connections. In this section an alternative method may be explained, in which a transistor may be built with any replacement gate (or gate-last) scheme that may be utilized widely in the industry. This method allows for high temperatures (above about 400° C.) to build the transistors. This method utilizes a combination of three concepts:
       Replacement gate (or gate-last) high k/metal gate fabrication   Face-up layer transfer using a carrier wafer   Misalignment tolerance techniques that utilize regular or repeating layouts. In these repeating layouts, transistors could be arranged in substantially parallel bands.
 
A very high density of vertical connections may be possible with this method. Single crystal silicon (or mono-crystalline silicon) layers that are transferred may be less than about 2 um thick, or could even be thinner than about 0.4 um or about 0.2 um. This replacement gate process may also be called a gate replacement process.
       
 
         [0064]    An interesting alternative may be available when using the carrier wafer flow described in  FIG. 46A-G  of the incorporated parent application. In this flow we can use the two sides of the transferred layer to build NMOS, a ‘p-type transistor’, on one side and PMOS, an ‘n-type transistor’ on the other side. Timing properly the replacement gate step such flow could enable full performance transistors properly aligned to each other. As illustrated in  FIG. 2A , an SOI (Silicon On Insulator) donor wafer  200  may be processed in the normal state of the art high k metal gate gate-last manner with adjusted thermal cycles to compensate for later thermal processing up to the step prior to where CMP exposure of the polysilicon dummy gates  204  takes place.  FIG. 2A  illustrates a cross section of the SOI donor wafer  200 , the buried oxide (BOX)  201 , the thin silicon layer  202  of the SOI wafer, the isolation  203  between transistors, the polysilicon dummy gates  204  and gate oxide  205  of n-type CMOS transistors with dummy gates, their associated source and drains  206  for NMOS, NMOS channel regions  207 , and the NMOS interlayer dielectric (ILD)  208 . Alternatively, the PMOS device may be constructed at this stage. This completes the first phase of transistor formation. At this step, or alternatively just after a CMP of NMOS ILD  208  to expose the polysilicon dummy gates  204  or to planarize the NMOS ILD  208  and not expose the polysilicon dummy gates  204 , an implant of an atomic species  210 , such as H+, may be done to prepare the cleaving plane  212  in the bulk of the donor substrate, as illustrated in  FIG. 2B . The SOI donor wafer  200  may be now permanently bonded to a carrier wafer  220  that has been prepared with an oxide layer  216  for oxide to oxide bonding to the donor wafer surface  214  as illustrated in  FIG. 2C . The details have been described previously. The SOI donor wafer  200  may then be cleaved at the cleaving plane  212  and may be thinned by chemical mechanical polishing (CMP) thus forming donor wafer layer  200 ′, and surface  222  may be prepared for transistor formation. The donor wafer layer  200 ′ at surface  222  may be processed in the normal state of the art gate last processing to form the PMOS transistors with dummy gates. During processing the wafer may be flipped so that surface  222  may be on top, but for illustrative purposes this is not shown in the subsequent  FIGS. 2E-G .  FIG. 2E  illustrates the cross section with the buried oxide (BOX)  201 , the now thin silicon donor wafer layer  200 ′ of the SOI substrate, the isolation  233  between transistors, the polysilicon dummy gates  234  and gate oxide  235  of p-type CMOS dummy gates, their associated source and drains  236  for PMOS, PMOS channel regions  237 , and the PMOS interlayer dielectric (ILD)  238 . The PMOS transistors may be precisely aligned at state of the art tolerances to the NMOS transistors due to the shared substrate donor wafer layer  200 ′ possessing the same alignment marks. At this step, or alternatively just after a CMP of PMOS ILD  238  to expose the PMOS polysilicon dummy gates or to planarize the PMOS ILD  238  and not expose the dummy gates, the wafer could be put into high temperature cycle to activate both the dopants in the NMOS and the PMOS source drain regions. Then an implant of an atomic species  287 , such as H+, may prepare the cleaving plane  221  in the bulk of the carrier wafer  220  for layer transfer suitability, as illustrated in  FIG. 2F . The PMOS transistors are now ready for normal state of the art gate-last transistor formation completion. As illustrated in  FIG. 2G , the PMOS ILD  238  may be chemical mechanically polished to expose the top of the polysilicon dummy gates  234 . The polysilicon dummy gates  234  may then be removed by etch and the PMOS hi-k gate dielectric  240  and the PMOS specific work function metal gate  241  may be deposited. An aluminum fill  242  may be performed on the PMOS gates and the metal CMP&#39;ed. A dielectric layer  239  may be deposited and the normal gate  243  and source/drain  244  contact formation and metallization. The PMOS layer to NMOS layer via  247  and metallization may be partially formed as illustrated in  FIG. 2G  and an oxide layer  248  may be deposited to prepare for bonding. The carrier wafer and two sided n/p layer may be then permanently bonded to bottom wafer having transistors and wires  299  with associated metal landing strip  250  as illustrated in  FIG. 2H . The wires may be composed of metals, such as, for example, copper or aluminum, and may be utilized to interconnect the transistors of the bottom wafer. The carrier wafer  220  may then be cleaved at the cleaving plane  221  and may be thinned by chemical mechanical polishing (CMP) to oxide layer  216  as illustrated in  FIG. 2I . The NMOS transistors are now ready for normal state of the art gate-last transistor formation completion. As illustrated in  FIG. 2J , the oxide layer  216  and the NMOS ILD  208  may be chemical mechanically polished to expose the top of the NMOS polysilicon dummy gates  204 . The NMOS polysilicon dummy gates  204  may then be removed by etch and the NMOS hi-k gate dielectric  260  and the NMOS specific work function metal gate  261  may be deposited. An aluminum fill  262  may be performed on the NMOS gates and the metal CMP&#39;ed. A dielectric layer  269  may be deposited and the normal gate  263  and source/drain  264  contact formation and metallization. The NMOS layer to PMOS layer via  267  to connect to  247  and metallization may be formed. As illustrated in  FIG. 2K , the layer-to-layer contacts  272  to the landing pads in the base wafer are now made. This same contact etch could be used to make the connections  273  between the NMOS and PMOS layer as well, instead of using the two step ( 247  and  267 ) method in  FIG. 2H . 
         [0065]    Using procedures similar to  FIG. 2A-K , it may be possible to construct structures such as  FIG. 3  where a transistor may be constructed with front gate  302  and back gate  304 . The back gate could be utilized for many purposes such as threshold voltage control, reduction of variability, increase of drive current and other purposes. 
         [0066]    Various approaches described in Section 2 could be utilized for constructing a 3D stacked gate-array with a repeating layout, where the repeating component in the layout may be a look-up table (LUT) implementation. For example, a 4 input look-up table could be utilized. This look-up table could be customized with a SRAM-based solution. Alternatively, a via-based solution could be used. Alternatively, a non-volatile memory based solution could be used. The approaches described in Section 1 could alternatively be utilized for constructing the 3D stacked gate array, where the repeating component may be a look-up table implementation. 
         [0067]    To improve the contact resistance of very small scaled contacts, the semiconductor industry employs various metal silicides, such as, for example, cobalt silicide, titanium silicide, tantalum silicide, and nickel silicide. The current advanced CMOS processes, such as, for example, 45 nm, 32 nm, and 22 nm nodes, employ nickel silicides to improve deep submicron source and drain contact resistances. Background information on silicides utilized for contact resistance reduction can be found in “NiSi Salicide Technology for Scaled CMOS,” H. Iwai, et. al., Microelectronic Engineering, 60 (2002), pp 157-169; “Nickel vs. Cobalt Silicide integration for sub-50 nm CMOS”, B. Froment, et. al., IMEC ESS Circuits, 2003; and “65 and 45-nm Devices—an Overview”, D. James, Semicon West, July 2008, ctr_024377. To achieve the lowest nickel silicide contact and source/drain resistances, the nickel on silicon could lead to heating up to about 450° C. 
         [0068]    Thus it may be desirable to enable low resistances for process flows in this document where the post layer transfer temperature exposures must remain under approximately 400° C. due to metallization, such as, for example, copper and aluminum, and low-k dielectrics present. The example process flow forms a Recessed Channel Array Transistor (RCAT), but this or similar flows may be applied to other process flows and devices, such as, for example, S-RCAT, JLT, V-groove, JFET, bipolar, and replacement gate flows. 
         [0069]    A planar n-channel Recessed Channel Array Transistor (RCAT) with metal silicide source &amp; drain contacts suitable for a 3D IC may be constructed. As illustrated in  FIG. 4A , a P− substrate donor wafer  402  may be processed to include wafer sized layers of N+ doping  404 , and P− doping  401  across the wafer. The N+ doped layer  404  may be formed by ion implantation and thermal anneal. In addition, P− doped layer  401  may have additional ion implantation and anneal processing to provide a different dopant level than P− substrate donor wafer  402 . P− doped layer  401  may also have graded P− doping to mitigate transistor performance issues, such as, for example, short channel effects, after the RCAT is formed. The layer stack may alternatively be formed by successive epitaxially deposited doped silicon layers of P− doping  5901  and N+ doping  5904 , or by a combination of epitaxy and implantation. Annealing of implants and doping may utilize optical annealing techniques or types of Rapid Thermal Anneal (RTA or spike). 
         [0070]    As illustrated in  FIG. 4B , a silicon reactive metal, such as, for example, Nickel or Cobalt, may be deposited onto N+ doped layer  404  and annealed, utilizing anneal techniques such as, for example, RTA, thermal, or optical, thus forming metal silicide layer  406 . The top surface of P− doped layer  401  may be prepared for oxide wafer bonding with a deposition of an oxide to form oxide layer  408 . 
         [0071]    As illustrated in  FIG. 4C , a layer transfer demarcation plane (shown as dashed line)  499  may be formed by hydrogen implantation or other methods as previously described. 
         [0072]    As illustrated in  FIG. 4D  donor wafer  402  with layer transfer demarcation plane  499 , P− doped layer  401 , N+ doped layer  404 , metal silicide layer  406 , and oxide layer  408  may be temporarily bonded to carrier or holder substrate  412  with a low temperature process that may facilitate a low temperature release. The carrier or holder substrate  412  may be a glass substrate to enable state of the art optical alignment with the acceptor wafer. A temporary bond between the carrier or holder substrate  412  and the donor wafer  402  may be made with a polymeric material, such as, for example, polyimide DuPont HD3007, which can be released at a later step by laser ablation, Ultra-Violet radiation exposure, or thermal decomposition, shown as adhesive layer  414 . Alternatively, a temporary bond may be made with uni-polar or bi-polar electrostatic technology such as, for example, the Apache tool from Beam Services Inc. 
         [0073]    As illustrated in  FIG. 4E , the portion of the donor wafer  402  that is below the layer transfer demarcation plane  499  may be removed by cleaving or other processes as previously described, such as, for example, ion-cut or other methods may controllably remove portions up to approximately the layer transfer demarcation plane  499 . The remaining donor wafer P− doped layer  401  may be thinned by chemical mechanical polishing (CMP) so that the P− layer  416  may be formed to the desired thickness. Oxide layer  418  may be deposited on the exposed surface of P− layer  416 . 
         [0074]    As illustrated in  FIG. 4F , both the donor wafer  402  and acceptor wafer  410  may be prepared for wafer bonding as previously described and then low temperature (less than approximately 400° C.) aligned and oxide to oxide bonded. Acceptor wafer  410 , as described previously, may compromise, for example, transistors, circuitry, metal, such as, for example, aluminum or copper, interconnect wiring, and thru layer via metal interconnect strips or pads. The carrier or holder substrate  412  may then be released using a low temperature process such as, for example, laser ablation. Oxide layer  418 , P− layer  416 , N+ doped layer  404 , metal silicide layer  406 , and oxide layer  408  have been layer transferred to acceptor wafer  410 . The top surface of oxide layer  408  may be chemically or mechanically polished. Now RCAT transistors are formed with low temperature (less than approximately 400° C.) processing and aligned to the acceptor wafer  410  alignment marks (not shown). 
         [0075]    As illustrated in  FIG. 4G , the transistor isolation regions  422  may be formed by mask defining and then plasma/RIE etching oxide layer  408 , metal silicide layer  406 , N+ doped layer  404 , and P− layer  416  to the top of oxide layer  418 . Then a low-temperature gap fill oxide may be deposited and chemically mechanically polished, with the oxide remaining in isolation regions  422 . Then the recessed channel  423  may be mask defined and etched. The recessed channel surfaces and edges may be smoothed by wet chemical or plasma/RIE etching techniques to mitigate high field effects. These process steps form oxide regions  424 , metal silicide source and drain regions  426 , N+ source and drain regions  428  and P− channel region  430 . 
         [0076]    As illustrated in  FIG. 4H , a gate dielectric  432  may be formed and a gate metal material may be deposited. The gate dielectric  432  may be an atomic layer deposited (ALD) gate dielectric that is paired with a work function specific gate metal in the industry standard high k metal gate process schemes described previously. Or the gate dielectric  432  may be formed with a low temperature oxide deposition or low temperature microwave plasma oxidation of the silicon surfaces and then a gate material such as, for example, tungsten or aluminum may be deposited. Then the gate material may be chemically mechanically polished, and the gate area defined by masking and etching, thus forming gate electrode  434 . 
         [0077]    As illustrated in  FIG. 4I , a low temperature thick oxide  438  is deposited and source, gate, and drain contacts, and thru layer via (not shown) openings are masked and etched preparing the transistors to be connected via metallization. Thus gate contact  442  connects to gate electrode  434 , and source &amp; drain contacts  436  connect to metal silicide source and drain regions  426 . 
         [0078]    Persons of ordinary skill in the art will appreciate that the illustrations in  FIGS. 4A through 41  are exemplary only and are not drawn to scale. Such skilled persons will further appreciate that many variations are possible such as, for example, the temporary carrier substrate may be replaced by a carrier wafer and a permanently bonded carrier wafer flow may be employed. Many other modifications within the scope of the invention will suggest themselves to such skilled persons after reading this specification. Thus the invention is to be limited only by the appended claims. 
         [0079]    While the “silicide-before-layer-transfer” process flow described in  FIG. 4A-I  can be used for many sub-400° C. 3D stacking applications, alternative approaches exist. Silicon forms silicides with many materials such as nickel, cobalt, platinum, titanium, manganese, and other materials that form silicides with silicon. By alloying two materials, one of which has a silicidation temperature greater than about 400° C. and one of which has a silicidation temperature less than about 400° C., in a certain ratio, the silicidation temperature of the alloy can be reduced to below about 400° C. For example, nickel silicide has a silicidation temperature of 400-450° C., while platinum silicide has a silicidation temperature of about 300° C. By depositing an alloy of Nickel and Platinum (in a certain ratio) on a silicon region and then annealing to form a silicide, one could lower the silicidation temperature to less than about 400° C. Another example could be deposition of an alloy of Nickel and Palladium (in a certain ratio) on a silicon region and then annealing to form a silicide, one could lower the silicidation temperature to less than about 400° C. As mentioned below, Nickel Silicide forms at about 400-450° C., while Palladium Silicide forms at around 250° C. By forming a mixture of these two silicides, silicidation temperature may be lowered to less than about 400° C. 
         [0080]    Strained silicon regions may be formed at less than about 400° C. by depositing dielectric strain-inducing layers around recessed channel devices and junction-less transistors in STI regions, in pre-metal dielectric regions, in contact etch stop layers and also in other regions around these transistors. 
         [0081]    An alternate method to obtain low temperature 3D compatible CMOS transistors residing in the same device layer of silicon is illustrated in  FIG. 6A-C . As illustrated in  FIG. 6A , a layer of p− mono-crystalline silicon  602  may be transferred onto a bottom layer of transistors and wires  600  utilizing previously described layer transfer techniques. A doped and activated layer may be formed in or on the silicon wafer to create p− mono-crystalline silicon layer  602  by processes such as, for example, implant and RTA or furnace activation, or epitaxial deposition and activation. As illustrated in  FIG. 6C , n-type well regions  604  and p-type well regions  606  may be formed by conventional lithographic and ion implantation techniques. An oxide layer  608  may be grown or deposited prior to or after the lithographic and ion implantation steps. The dopants may be activated with a short wavelength optical anneal, such as a 550 nm laser anneal system manufactured by Applied Materials, that will not heat up the bottom layer of transistors and wires  600  beyond approximately 400° C., the temperature at which damage to the barrier metals containing the copper wiring of bottom layer of transistors and wires  600  may occur. At this step in the process flow, there is very little structure pattern in the top layer of silicon, which allows the effective use of the shorter wavelength optical annealing systems, which are prone to pattern sensitivity issues thereby creating uneven heating. As illustrated in  FIG. 6C , shallow trench regions  624  may be formed, and conventional CMOS transistor formation methods with dopant segregation techniques, including those previously described, may be utilized to construct CMOS transistors, including n-silicon regions  614 , P+ silicon regions  628 , silicide regions  626 , PMOS gate stacks  634 , p-silicon regions  616 , N+ silicon regions  620 , silicide regions  622 , and NMOS gate stacks  632 . 
         [0082]    Persons of ordinary skill in the art will appreciate that the low temperature 3D compatible CMOS transistor formation method and techniques described in  FIG. 6  may also utilize tungsten wiring for the bottom layer of transistors and wires  600  thereby increasing the temperature tolerance of the optical annealing utilized in  FIG. 6B or 6C . Moreover, absorber layers, such as amorphous carbon, reflective layers, such as aluminum, or Brewster angle adjustments to the optical annealing may be utilized to optimize the implant activation and minimize the heating of lower device layers. Further, shallow trench regions  624  may be formed prior to the optical annealing or ion-implantation steps. Furthermore, channel implants may be performed prior to the optical annealing so that transistor characteristics may be more tightly controlled. Moreover, one or more of the transistor channels may be undoped by layer transferring an undoped layer of mono-crystalline silicon in place of the layer of p− mono-crystalline silicon  602 . Further, the source and drain implants may be performed prior to the optical anneals. Moreover, the methods utilized in  FIG. 6  may be applied to create other types of transistors, such as junction-less transistors or recessed channel transistors. Further, the  FIG. 6  methods may be applied in conjunction with the hydrogen plasma activation techniques previously described in this document. Thus the invention is to be limited only by the appended claims. 
         [0083]      FIG. 7  illustrates a 3D integrated circuit. Two mono-crystalline silicon layers,  704  and  716  are shown. Silicon layer  716  could be thinned down from its original thickness, and its thickness could be in the range of approximately 1 um to approximately 50 um. Silicon layer  704  may include transistors which could have gate electrode region  714 , gate dielectric region  712 , and shallow trench isolation (STI) regions  710 . Silicon layer  716  may include transistors which could have gate electrode region  734 , gate dielectric region  732 , and shallow trench isolation (STI) regions  730 . A through-silicon via (TSV)  718  could be present and may have a surrounding dielectric region  720 . Wiring layers for silicon layer  704  are indicated as  708  and wiring dielectric is indicated as  706 . Wiring layers for silicon layer  716  are indicated as  738  and wiring dielectric is indicated as  736 . The heat removal apparatus, which could include a heat spreader and a heat sink, is indicated as  702 . The heat removal problem for the 3D integrated circuit shown in  FIG. 7  is immediately apparent. The silicon layer  716  is far away from the heat removal apparatus  702 , and it is difficult to transfer heat between silicon layer  716  and heat removal apparatus  702 . Furthermore, wiring dielectric regions  706  do not conduct heat well, and this increases the thermal resistance between silicon layer  716  and heat removal apparatus  702 . 
         [0084]      FIG. 8  illustrates a 3D integrated circuit that could be constructed, for example, using techniques described in U.S. patent application Ser. No. 12/900,379 (now U.S. Pat. No. 8,395,191) and U.S. patent application Ser. No. 12/904,119 (now U.S. Pat. No. 8,476,145). Two mono-crystalline silicon layers,  804  and  816  are shown. Silicon layer  816  could be thinned down from its original thickness, and its thickness could be in the range of approximately 3 nm to approximately 1 um. Silicon layer  804  may include transistors which could have gate electrode region  814 , gate dielectric region  812 , and shallow trench isolation (STI) regions  810 . Silicon layer  816  may include transistors which could have gate electrode region  834 , gate dielectric region  832 , and shallow trench isolation (STI) regions  822 . It can be observed that the STI regions  822  can go right through to the bottom of silicon layer  816  and provide good electrical isolation. This, however, can cause challenges for heat removal from the STI surrounded transistors since STI regions  822  are typically insulators that do not conduct heat well. Therefore, the heat spreading capabilities of silicon layer  816  with STI regions  822  are low. A through-layer via (TLV)  818  could be present and may include its dielectric region  820 . Wiring layers for silicon layer  804  are indicated as  808  and wiring dielectric is indicated as  806 . Wiring layers for silicon layer  816  are indicated as  838  and wiring dielectric is indicated as  836 . The heat removal apparatus, which could include a heat spreader and a heat sink, is indicated as  802 . The heat removal problem for the 3D integrated circuit shown in  FIG. 8  is immediately apparent. The silicon layer  816  is far away from the heat removal apparatus  802 , and it is difficult to transfer heat between silicon layer  816  and heat removal apparatus  802 . Furthermore, wiring dielectric regions  806  do not conduct heat well, and this increases the thermal resistance between silicon layer  816  and heat removal apparatus  802 . The heat removal challenge is further exacerbated by the poor heat spreading properties of silicon layer  816  with STI regions  822 . 
         [0085]      FIG. 9  and  FIG. 10  illustrate how the power or ground distribution network of a 3D integrated circuit could assist heat removal.  FIG. 9  illustrates an exemplary power distribution network or structure of the 3D integrated circuit. The 3D integrated circuit, could, for example, be constructed with two silicon layers  904  and  916 . The heat removal apparatus  902  could include a heat spreader and a heat sink. The power distribution network or structure could consist of a global power grid  910  that takes the supply voltage (denoted as VDD) from power pads and transfers it to local power grids  908  and  906 , which then transfer the supply voltage to logic cells or gates such as  914  and  915 . Vias  918  and  912 , such as the previously described TSV or TLV, could be used to transfer the supply voltage from the global power grid  910  to local power grids  908  and  906 . The 3D integrated circuit could have a similar distribution networks, such as for ground and other supply voltages, as well. Typically, many contacts are made between the supply and ground distribution networks and silicon layer  904 . Due to this, there could exist a low thermal resistance between the power/ground distribution network and the heat removal apparatus  902 . Since power/ground distribution networks are typically constructed of conductive metals and could have low effective electrical resistance, they could have a low thermal resistance as well. Each logic cell or gate on the 3D integrated circuit (such as, for example  914 ) is typically connected to VDD and ground, and therefore could have contacts to the power and ground distribution network. These contacts could help transfer heat efficiently (i.e. with low thermal resistance) from each logic cell or gate on the 3D integrated circuit (such as, for example  914 ) to the heat removal apparatus  902  through the power/ground distribution network and the silicon layer  904 . 
         [0086]      FIG. 10  illustrates an exemplary NAND gate  1020  or logic cell and shows how all portions of this logic cell or gate could be located with low thermal resistance to the VDD or ground (GND) contacts. The NAND gate  1020  could consist of two pMOS transistors  1002  and two nMOS transistors  1004 . The layout of the NAND gate  1020  is indicated in  1022 . Various regions of the layout include metal regions  1006 , poly regions  1008 , n type silicon regions  1010 , p type silicon regions  1012 , contact regions  1014 , and oxide regions  1024 . pMOS transistors in the layout are indicated as  1016  and nMOS transistors in the layout are indicated as  1018 . It can be observed that all parts of the exemplary NAND gate  1020  could have low thermal resistance to VDD or GND contacts since they are physically very close to them. Thus, all transistors in the NAND gate  1020  can be maintained at desirable temperatures if the VDD or ground contacts are maintained at desirable temperatures. 
         [0087]    While the previous paragraph described how an existing power distribution network or structure can transfer heat efficiently from logic cells or gates in 3D-ICs to their heat sink, many techniques to enhance this heat transfer capability will be described hereafter in this patent application. These embodiments of the invention can provide several benefits, including lower thermal resistance and the ability to cool higher power 3D-ICs. These techniques are valid for different implementations of 3D-ICs, including monolithic 3D-ICs and TSV-based 3D-ICs. 
         [0088]      FIG. 11  describes an embodiment of the invention, where the concept of thermal contacts is described. Two mono-crystalline silicon layers,  1104  and  1116  may have transistors. Silicon layer  1116  could be thinned down from its original thickness, and its thickness could be in the range of approximately 3 nm to approximately 1 um. Mono-crystalline silicon layer  1104  could have STI regions  1110 , gate dielectric regions  1112 , gate electrode regions  1114  and several other regions required for transistors (not shown). Mono-crystalline silicon layer  1116  could have STI regions  1130 , gate dielectric regions  1132 , gate electrode regions  1134  and several other regions required for transistors (not shown). Heat removal apparatus  1102  may include, for example, heat spreaders and heat sinks. In the example shown in  FIG. 11 , mono-crystalline silicon layer  1104  is closer to the heat removal apparatus  1102  than other mono-crystalline silicon layers such as  1116 . Dielectric regions  1106  and  1146  could be used to insulate wiring regions such as  1122  and  1142  respectively. Through-layer vias for power delivery  1118  and their associated dielectric regions  1120  are shown. A thermal contact  1124  can be used that connects the local power distribution network or structure, which may include wiring layers  1142  used for transistors in the silicon layer  1104 , to the silicon layer  1104 . Thermal junction region  1126  can be either a doped or undoped region of silicon, and further details of thermal junction region  1126  will be given in  FIG. 12 . The thermal contact such as  1124  can be preferably placed close to the corresponding through-layer via for power delivery  1118 ; this helps transfer heat efficiently from the through-layer via for power delivery  1118  to thermal junction region  1126  and silicon layer  1104  and ultimately to the heat removal apparatus  1102 . For example, the thermal contact  1124  could be located within approximately 2 um distance of the through-layer via for power delivery  1118  in the X-Y plane (the through-layer via direction is considered the Z plane in  FIG. 11 ). While the thermal contact such as  1124  is described above as being between the power distribution network or structure and the silicon layer closest to the heat removal apparatus, it could also be between the ground distribution network and the silicon layer closest to the heat sink. Furthermore, more than one thermal contact  1124  can be placed close to the through-layer via for power delivery  1118 . These thermal contacts can improve heat transfer from transistors located in higher layers of silicon such as  1116  to the heat removal apparatus  1102 . While mono-crystalline silicon has been mentioned as the transistor material in this paragraph, other options are possible including, for example, poly-crystalline silicon, mono-crystalline germanium, mono-crystalline III-V semiconductors, graphene, and various other semiconductor materials with which devices, such as transistors, may be constructed within. 
         [0089]      FIG. 12  describes an embodiment of the invention, where various implementations of thermal junctions and associated thermal contacts are illustrated. P-wells in CMOS integrated circuits are typically biased to ground and N-wells are typically biased to the supply voltage VDD. Thermal contacts and junctions may be formed differently. A thermal contact  1204  between the power (VDD) distribution network and a P-well  1202  can be implemented as shown in N+ in P-well thermal junction and contact example  1208 , where an n+ doped region thermal junction  1206  is formed in the P-well region at the base of the thermal contact  1204 . The n+ doped region thermal junction  1206  ensures a reverse biased p-n junction can be formed in N+ in P-well thermal junction and contact example  1208  and makes the thermal contact viable (i.e. not highly conductive) from an electrical perspective. The thermal contact  1204  could be formed of a conductive material such as copper, aluminum or some other material. A thermal contact  1214  between the ground (GND) distribution network and a P-well  1212  can be implemented as shown in P+ in P-well thermal junction and contact example  1218 , where a p+ doped region thermal junction  1216  may be formed in the P-well region at the base of the thermal contact  1214 . The p+ doped region thermal junction  1216  makes the thermal contact viable (i.e. not highly conductive) from an electrical perspective. The p+ doped region thermal junction  1216  and the P-well  1212  would typically be biased at ground potential. A thermal contact  1224  between the power (VDD) distribution network and an N-well  1222  can be implemented as shown in N+ in N-well thermal junction and contact example  1228 , where an n+ doped region thermal junction  1226  may be formed in the N-well region at the base of the thermal contact  1224 . The n+ doped region thermal junction  1226  makes the thermal contact viable (i.e. not highly conductive) from an electrical perspective. Both the n+ doped region thermal junction  1226  and the N-well  1222  would typically be biased at VDD potential. A thermal contact  1234  between the ground (GND) distribution network and an N-well  1232  can be implemented as shown in P+ in N-well thermal junction and contact example  1238 , where a p+ doped region thermal junction  1236  may be formed in the N-well region at the base of the thermal contact  1234 . The p+ doped region thermal junction  1236  makes the thermal contact viable (i.e. not highly conductive) from an electrical perspective due to the reverse biased p-n junction formed in P+ in N-well thermal junction and contact example  1238 . Note that the thermal contacts are designed to conduct negligible electricity, and the current flowing through them is several orders of magnitude lower than the current flowing through a transistor when it is switching. Therefore, the thermal contacts can be considered to be designed to conduct heat and conduct negligible (or no) electricity. 
         [0090]      FIG. 13  describes an embodiment of the invention, where an additional type of thermal contact structure is illustrated. The embodiment shown in  FIG. 13  could also function as a decoupling capacitor to mitigate power supply noise. It could consist of a thermal contact  1304 , an electrode  1310 , a dielectric  1306  and P-well  1302 . The dielectric  1306  may be electrically insulating, and could be optimized to have high thermal conductivity. Dielectric  1306  could be formed of materials, such as, for example, hafnium oxide, silicon dioxide, other high k dielectrics, carbon, carbon based material, or various other dielectric materials with electrical conductivity below about 1 nano-amp per square micron. 
         [0091]    A thermal connection may be defined as the combination of a thermal contact and a thermal junction. The thermal connections illustrated in  FIG. 12 ,  FIG. 13  and other figures in this patent application may be designed into a chip to remove heat (conduct heat), and may be designed to not conduct electricity. Essentially, a semiconductor device comprising power distribution wires is described wherein some of said wires have a thermal connection designed to conduct heat to the semiconductor layer but the wires do not substantially conduct electricity through the thermal connection to the semiconductor layer. 
         [0092]    Thermal contacts similar to those illustrated in  FIG. 12  and  FIG. 13  can be used in the white spaces of a design, i.e. locations of a design where logic gates or other useful functionality are not present. These thermal contacts connect white-space silicon regions to power and/or ground distribution networks. Thermal resistance to the heat removal apparatus can be reduced with this approach. Connections between silicon regions and power/ground distribution networks can be used for various device layers in the 3D stack, and need not be restricted to the device layer closest to the heat removal apparatus. A Schottky contact or diode may also be utilized for a thermal contact and thermal junction. 
         [0093]      FIG. 14  illustrates an embodiment of this invention, which can provide enhanced heat removal from 3D-ICs by integrating heat spreader layers or regions in stacked device layers. Two mono-crystalline silicon layers,  1404  and  1416  are shown. Silicon layer  1416  could be thinned from its original thickness, and its thickness could be in the range of approximately 3 nm to approximately 1 um. Silicon layer  1404  may include gate electrode region  1414 , gate dielectric region  1412 , and shallow trench isolation (STI) regions  1410 . Silicon layer  1416  may include gate electrode region  1434 , gate dielectric region  1432 , and shallow trench isolation (STI) regions  1422 . A through-layer via (TLV)  1418  could be present and may have a dielectric region  1420 . Wiring layers for silicon layer  1404  are indicated as  1408  and wiring dielectric is indicated as  1406 . Wiring layers for silicon layer  1416  are indicated as  1438  and wiring dielectric is indicated as  1436 . The heat removal apparatus, which could include a heat spreader and a heat sink, is indicated as  1402 . It can be observed that the STI regions  1422  can go right through to the bottom of silicon layer  1416  and provide good electrical isolation. This, however, can cause challenges for heat removal from the STI surrounded transistors since STI regions  1422  are typically insulators that do not conduct heat well. The buried oxide layer  1424  typically does not conduct heat well either. To tackle heat removal issues with the structure shown in  FIG. 14 , a heat spreader  1426  can be integrated into the 3D stack by methods, such as, deposition of a heat spreader layer and subsequent etching into regions. The heat spreader  1426  material may include, for example, copper, aluminum, graphene, diamond, carbon or any other material with a high thermal conductivity (defined as greater than 100 W/m-K). While the heat spreader concept for 3D-ICs is described with an architecture similar to  FIG. 8 , similar heat spreader concepts could be used for architectures similar to  FIG. 7 , and also for other 3D IC architectures. 
         [0094]      FIG. 15  illustrates an embodiment of the invention that describes a technique that could reduce heat-up of transistors fabricated on silicon-on-insulator (SOI) substrates. SOI substrates have a buried oxide (BOX) between the silicon transistor regions and the heat sink. This BOX region has a high thermal resistance, and makes heat transfer from transistor regions to the heat sink difficult. In  FIGS. 15, 1536, 1548 and 1556  could represent regions of an insulator, such as silicon dioxide,  1546  could represent regions of n+ silicon,  1540  could represent regions of p− silicon,  1552  could represent a gate dielectric region for a nMOS transistor,  1554  could represent a gate electrode region for a nMOS transistor,  1544  could represent copper wiring regions and  1504  could represent a highly doped silicon region. One of the key difficulties of silicon-on-insulator (SOI) substrates is the low heat transfer from transistor regions to the heat removal apparatus  1502  through the buried oxide layer  1536  that has low thermal conductivity. The ground contact  1562  of the nMOS transistor shown in  FIG. 15  can be connected to the ground distribution network  1564  which in turn can be connected with a low thermal resistance connection  1550  to highly doped silicon region  1504  and thus to heat removal apparatus  1502 . This enables low thermal conductivity between the transistor shown in  FIG. 15  and the heat removal apparatus  1502 . While  FIG. 15  described how heat could be transferred between an MOS transistor and the heat removal apparatus, similar approaches can also be used for pMOS transistors. 
         [0095]      FIG. 16  illustrates an embodiment of the invention that describes a technique that could reduce heat-up of transistors fabricated on silicon-on-insulator (SOI) substrates. In  FIGS. 16, 1636, 1648 and 1656  could represent regions of an insulator, such as silicon dioxide,  1646  could represent regions of n+ silicon,  1640  could represent regions of p-silicon,  1652  could represent a gate dielectric region for a nMOS transistor,  1654  could represent a gate electrode region for a nMOS transistor,  1644  could represent copper wiring regions and  1604  could represent a doped silicon region. One of the key difficulties of silicon-on-insulator (SOI) substrates is the low heat transfer from transistor regions to the heat removal apparatus  1602  through the buried oxide layer  1636  that has low thermal conductivity. The ground contact  1662  of the nMOS transistor shown in  FIG. 16  can be connected to the ground distribution network  1664  which in turn can be connected with a low thermal resistance connection  1650  to doped silicon region  1604  through an implanted and activated region  1610 . The implanted and activated region  1610  could be such that thermal contacts similar to those in  FIG. 12  can be formed. This could enable low thermal conductivity between the transistor shown in  FIG. 16  and the heat removal apparatus  1602 . While  FIG. 16  described how heat could be transferred between a nMOS transistor and the heat removal apparatus, similar approaches can also be used for pMOS transistors. 
         [0096]      FIG. 17  illustrates an embodiment of this invention that could have heat spreading regions located on the sides of 3D-ICs. The 3D integrated circuit shown in  FIG. 17  could be potentially constructed using techniques described in U.S. patent application Ser. No. 12/900,379 (now U.S. Pat. No. 8,395,191) and U.S. patent application Ser. No. 12/904,119 (now U.S. Pat. No. 8,476,145). Two mono-crystalline silicon layers,  1704  and  1716  are shown. Silicon layer  1716  could be thinned down from its original thickness, and its thickness could be in the range of approximately 3 nm to approximately 1 um. Silicon layer  1704  may include transistors which could have gate electrode region  1714 , gate dielectric region  1712 , and shallow trench isolation (STI) regions  1710 . Silicon layer  1716  may include transistors which could have gate electrode region  1734 , gate dielectric region  1732 , and shallow trench isolation (STI) regions  1722 . It can be observed that the STI regions  1722  can go right through to the bottom of silicon layer  1716  and provide good electrical isolation. A through-layer via (TLV)  1718  could be present and may include its dielectric region  1720 . Wiring layers for silicon layer  1704  are indicated as  1708  and wiring dielectric is indicated as  1706 . Wiring layers for silicon layer  1716  are indicated as  1738  and wiring dielectric is indicated as  1736 . The heat removal apparatus, which could include a heat spreader and a heat sink, is indicated as  1702 . Thermally conductive material  1740  could be present at the sides of the 3D-IC shown in  FIG. 17 . Thus, a thermally conductive heat spreading region could be located on the sidewalls of a 3D-IC. The thermally conductive material  1740  could be a dielectric such as, for example, insulating carbon, diamond, diamond like carbon (DLC), and various other materials that provide better thermal conductivity than silicon dioxide. Essentially, these materials could have thermal conductivity higher than about 0.6 W/m-K. One possible scheme that could be used for forming these regions could involve depositing and planarizing the thermally conductive material  1740  at locations on or close to the dicing regions, such as potential dicing scribe lines, of a 3D-IC after an etch process. The wafer could then be diced. Although this embodiment of the invention is described with  FIG. 17 , one could combine the concept of having thermally conductive material regions on the sidewalls of 3D-ICs with ideas shown in other figures of this patent application, such as, for example, the concept of having lateral heat spreaders shown in  FIG. 14 . 
         [0097]    While concepts in this patent application have been described with respect to 3D-ICs with two stacked device layers, those of ordinary skill in the art will appreciate that it can be valid for 3D-ICs with more than two stacked device layers. 
         [0098]    Some embodiments of the invention may include alternative techniques to build IC (Integrated Circuit) devices including techniques and methods to construct 3D IC systems. Some embodiments of the invention may enable device solutions with far less power consumption than prior art. These device solutions could be very useful for the growing application of mobile electronic devices and mobile systems such as mobile phones, smart phone, cameras and the like. For example, incorporating the 3D IC semiconductor devices according to some embodiments of the invention within these mobile electronic devices and mobile systems could provide superior mobile units that could operate much more efficiently and for a much longer time than with prior art technology. The 3D IC techniques and the methods to build devices according to various embodiments of the invention could empower the mobile smart system to win in the market place, as they provide unique advantages for aspects that are very important for ‘smart’ mobile devices, such as, low size and volume, low power, versatile technologies and feature integration, low cost, self-repair, high memory density, high performance. These advantages would not be achieved without the use of some embodiment of the invention. 
         [0099]    3D ICs according to some embodiments of the invention could also enable electronic and semiconductor devices with much a higher performance due to the shorter interconnect as well as semiconductor devices with far more complexity via multiple levels of logic and providing the ability to repair or use redundancy. The achievable complexity of the semiconductor devices according to some embodiments of the invention could far exceed what was practical with the prior art technology. These advantages could lead to more powerful computer systems and improved systems that have embedded computers. 
         [0100]    Some embodiments of the invention may also enable the design of state of the art electronic systems at a greatly reduced non-recurring engineering (NRE) cost by the use of high density 3D FPGAs or various forms of 3D array base ICs with reduced custom masks as been described previously. 
         [0101]    These systems could be deployed in many products and in many market segments. Reduction of the NRE may enable new product family or application development and deployment early in the product lifecycle by lowering the risk of upfront investment prior to a market being developed. The above advantages may also be provided by various mixes such as reduced NRE using generic masks for layers of logic and other generic mask for layers of memories and building a very complex system using the repair technology to overcome the inherent yield limitation. Another form of mix could be building a 3D FPGA and add on it 3D layers of customizable logic and memory so the end system could have field programmable logic on top of the factory customized logic. In fact there are many ways to mix the many innovative elements to form 3D IC to support the need of an end system, including using multiple devices wherein more than one device incorporates elements of the invention. An end system could benefits from memory device utilizing the invention 3D memory together with high performance 3D FPGA together with high density 3D logic and so forth. Using devices that use one or multiple elements of the invention would allow for better performance and or lower power and other advantages resulting from the inventions to provide the end system with a competitive edge. Such end system could be electronic based products or other type of systems that include some level of embedded electronics, such as, for example, cars, remote controlled vehicles, etc. 
         [0102]    It will also be appreciated by persons of ordinary skill in the art that the invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the invention includes both combinations and sub-combinations of the various features described hereinabove as well as modifications and variations which would occur to such skilled persons upon reading the foregoing description. Thus the invention is to be limited only by the appended claims.