Abstract:
An embedded type multifunctional integrated structure and a method for manufacturing the same are disclosed. The present invention utilizes the concept of multi-layer design to integrated more than two passive components on a component structure that would be adhered to a substrate. Hence, the embedded type multifunctional integrated structure has an OCP function, an OVP function, an anti-EMI function, and an anti-ESD function at the same time. Therefore, the present invention effectively integrated two or more than one passive components in order to increase function of the embedded type multifunctional integrated structure. Moreover, the present invention effectively reduces the size of the passive components on a PCB and reduces the number of solder joints.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a multifunctional integrated structure and a method for manufacturing the same, and particularly relates to an embedded type multifunctional integrated structure and a method for manufacturing the same. 
         [0003]    2. Description of the Related Art 
         [0004]    For future electronic product, the electronic product design tends to achieve the functions of light, thin, short, and small. Moreover, the size of the passive components is larger than that of other electronic components in the electronic product. Hence, if the passive components can be effectively integrated together, the electronic product can achieve the functions of light, thin, short, and small easily. 
         [0005]    However, each pass component only has a single function in the prior design. Hence, when a designer needs to use many different functions for protecting the electronic product, the designer only can place many pass components with a single function in the electronic product. Therefore, the method of the prior art wastes cost and occupies many space of the electronic product. 
       SUMMARY OF THE INVENTION 
       [0006]    One particular aspect of the present invention is to provide an embedded type multifunctional integrated structure and a method for manufacturing the same. The present invention utilizes the concept of multi-layer design to integrated more than two passive components on a component structure that would be adhered to a substrate. Hence, the embedded type multifunctional integrated structure has an OCP (Over-Current Protection) function, an OVP (Over-Voltage Protection) function, an anti-EMI (anti-Electromagnetic Interference) function, and an anti-ESD (anti-Electrostatic Discharge) function at the same time. Therefore, the present invention effectively integrated two or more than one passive components in order to increase function of the embedded type multifunctional integrated structure. Moreover, the present invention effectively reduces the size of the passive components on a PCB and reduces the number of solder joints. 
         [0007]    In order to achieve the above-mentioned aspects, the present invention provides an embedded type multifunctional integrated structure, including: a top cover insulating layer, a over-current protection layer, a middle insulating layer, a multifunctional protection layer, a bottom cover insulating layer, and a lateral conductive unit. 
         [0008]    Moreover, the top cover insulating layer has at least one first power input portion. The over-current protection layer is disposed under the top cover insulating layer, and the over-current protection layer has a second power input portion and a second power output portion. The middle insulating layer is disposed under the over-current protection layer, and the middle insulating layer has an opening. The multifunctional protection layer is disposed under the middle insulating layer. The multifunctional protection layer has a third power input portion, a third power output portion, and a multifunctional chip unit electrically connected between the third power input portion and the third power output portion, and the multifunctional chip unit is received in the opening of the middle insulating layer. The bottom cover insulating layer is disposed under the multifunctional protection layer, and the bottom cover insulating layer has a fourth power output portion and a fifth power output portion. 
         [0009]    Furthermore, the lateral conductive unit has a first lateral conductive layer, a second lateral conductive layer, and a third lateral conductive layer insulated from each other. Each lateral conductive layer from top to bottom is formed on lateral sides of the top cover insulating layer, the over-current protection layer, the middle insulating layer, the multifunctional protection layer, and the bottom cover insulating layer in sequence. In addition, the first power input portion and the second power input portion are electrically connected with each other via the first lateral conductive layer. The second power output portion, the third power input portion and the fourth power output portion are electrically connected with each other via the second lateral conductive layer. The third power output portion and the fifth power output portion are electrically connected with each other via the third lateral conductive layer. 
         [0010]    In order to achieve the above-mentioned aspects, the present invention provides a method for manufacturing an embedded type multifunctional integrated structure, including: providing a top cover insulating layer that has at least one first power input portion; providing a over-current protection layer that has a second power input portion and a second power output portion; providing a middle insulating layer that has an opening; providing a multifunctional protection layer that has a third power input portion, a third power output portion, and a multifunctional chip unit electrically connected between the third power input portion and the third power output portion, and the multifunctional chip unit being received in the opening of the middle insulating layer; and providing a bottom cover insulating layer that has a fourth power output portion and a fifth power output portion. 
         [0011]    The method further includes making the top cover insulating layer, the over-current protection layer, the middle insulating layer, the multifunctional protection layer, and the bottom cover insulating layer stacked together in sequence; and forming a first lateral conductive layer, a second lateral conductive layer, and a third lateral conductive layer that are insulated from each other. Each lateral conductive layer from top to bottom is formed on lateral sides of the top cover insulating layer, the over-current protection layer, the middle insulating layer, the multifunctional protection layer, and the bottom cover insulating layer in sequence. The first power input portion and the second power input portion are electrically connected with each other via the first lateral conductive layer. The second power output portion, the third power input portion and the fourth power output portion are electrically connected with each other via the second lateral conductive layer. The third power output portion and the fifth power output portion are electrically connected with each other via the third lateral conductive layer. 
         [0012]    It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. Other advantages and features of the invention will be apparent from the following description, drawings and claims. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]    The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawings, in which: 
           [0014]      FIG. 1A  is a perspective, exploded view of an embedded type multifunctional integrated structure according to the first embodiment of the present; 
           [0015]      FIG. 1B  is a reversed, perspective view of an over-current protection layer according to the first embodiment of the present; 
           [0016]      FIG. 1C  is a reversed, perspective view of a bottom cover insulating layer according to the first embodiment of the present; 
           [0017]      FIG. 1D  is a perspective, assembled view of an embedded type multifunctional integrated structure according to the first embodiment of the present; 
           [0018]      FIG. 2A  is a perspective view of an over-current protection layer according to the second embodiment of the present; 
           [0019]      FIG. 2B  is a reversed, perspective view of an over-current protection layer according to the second embodiment of the present; 
           [0020]      FIG. 3A  is a perspective view of a multifunctional protection layer according to the third embodiment of the present; 
           [0021]      FIG. 3B  is a reversed, perspective view of a multifunctional protection layer according to the third embodiment of the present; 
           [0022]      FIG. 4A  is a perspective view of a first arrangement of a multifunctional chip unit according to the present; 
           [0023]      FIG. 4B  is a perspective view of a second arrangement of a multifunctional chip unit according to the present; 
           [0024]      FIG. 4C  is a perspective view of a third arrangement of a multifunctional chip unit according to the present; 
           [0025]      FIG. 5  is a flowchart of a method for manufacturing an embedded type multifunctional integrated structure according to the present; and 
           [0026]      FIG. 6  is a perspective view of a stacked structure with five layers according to the present invention (before many embedded type multifunctional integrated structure are cut from the stacked structure). 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0027]    Referring to  FIGS. 1A to 1D ,  FIG. 1A  shows a perspective, exploded view of an embedded type multifunctional integrated structure according to the first embodiment of the present;  FIG. 1B  shows a reversed, perspective view of an over-current protection layer according to the first embodiment of the present;  FIG. 1C  shows a reversed, perspective view of a bottom cover insulating layer according to the first embodiment of the present;  FIG. 1D  shows a perspective, assembled view of an embedded type multifunctional integrated structure according to the first embodiment of the present. 
         [0028]    Referring to above-mentioned figures, the first embodiment of the present invention provides an embedded type multifunctional integrated structure that includes a top cover insulating layer  1 , a over-current protection layer  2 , a middle insulating layer M, a multifunctional protection layer  3 , a bottom cover insulating layer  4 , and a lateral conductive unit  5 . Moreover, the top cover insulating layer  1 , the over-current protection layer  2 , the middle insulating layer M, the multifunctional protection layer  3 , and the bottom cover insulating layer  4  are stacked together in sequence. The lateral conductive unit  5  has a first lateral conductive layer  51 , a second lateral conductive layer  52 , and a third lateral conductive layer  53  insulated from each other. 
         [0029]    In addition, the top cover insulating layer  1  has a first half hole  10   a  formed on a lateral side thereof, and a second half hole  10   b  and a third half hole  10   c  respectively formed on an opposite lateral side thereof. The top cover insulating layer  1  has at least one first power input portion  11  electrically connected with the first lateral conductive layer  51 , at least one first power output portion  12  electrically connected with the second lateral conductive layer  52 , and at least one grounding portion  13  electrically connected with the third lateral conductive layer  53 . Moreover, the at least one first power input portion  11  is formed on a lateral side of a top surface of the top cover insulating layer  1 , and the at least one first power output portion  12  and the at least one grounding portion  13  are formed on an opposite lateral side of the top surface of the top cover insulating layer  1 . 
         [0030]    Furthermore, the over-current protection layer  2  is disposed under the top cover insulating layer  1 . The over-current protection layer  2  has a first half hole  20   a  formed on a lateral side thereof, and a second half hole  20   b  and a third half hole  20   c  respectively formed on an opposite lateral side thereof. In addition, the over-current protection layer  2  is composed of a first electrode layer  2 A, a second electrode layer  2 B, and a positive temperature coefficient material layer  2 C that is disposed between the first electrode layer  2 A and the second electrode layer  2 B. The positive temperature coefficient material layer  2 C can be a PPTC (Polymer Positive Temperature Coefficient) material layer, a resistance material layer, a capacitance material layer, or an inductance material layer. 
         [0031]    In addition, referring to  FIG. 1B , the over-current protection layer  2  has a second power input portion  21  and a second power output portion  22 . The second power input portion  21  is one side of the second electrode layer  2 B, and the second power output portion  22  is one side of the first electrode layer  2 A. The first electrode layer  2 A has a first insulating portion S 1  insulated from the first lateral conductive layer  51  and a second insulating portion S 2  insulated from the third lateral conductive layer  53 . The second electrode layer  2 B has a third insulating portion S 3  insulated from the second lateral conductive layer  52  and the third lateral conductive layer  53 . Hence, the first electrode layer  2 A and the second electrode layer  2 B are insulated from the third lateral conductive layer  53  via the second insulating portion S 2  and the third insulating portion S 3 , respectively. 
         [0032]    Moreover, the middle insulating layer M is disposed under the over-current protection layer  2 , and the middle insulating layer M has an opening M 10 . The middle insulating layer M has a first half hole Ma formed on a lateral side thereof, and a second half hole Mb and a third half hole Mc respectively formed on an opposite lateral side thereof. 
         [0033]    Furthermore, the multifunctional protection layer  3  is disposed under the middle insulating layer M. The multifunctional protection layer  3  has a first half hole  30   a  formed on a lateral side thereof, and a second half hole  30   b  and a third half hole  30   c  respectively formed on an opposite lateral side thereof. The multifunctional protection layer  3  has a third power input portion  31 , a third power output portion  32 , and a multifunctional chip unit  33  electrically connected between the third power input portion  31  and the third power output portion  32 . 
         [0034]    In addition, the multifunctional chip unit  33  is received in the opening M 10  of the middle insulating layer M. In this embodiment, the third power input portion  31  and the third power output portion  32  are formed on a top surface of the multifunctional protection layer  3 . Furthermore, the multifunctional chip unit  33  can be a functional chip such as an OVP (Over-Voltage Protection) chip, an anti-EMI (anti-Electromagnetic Interference) chip, or an anti-ESD (anti-Electrostatic Discharge) chip. 
         [0035]    Moreover, the bottom cover insulating layer  4  is disposed under the multifunctional protection layer  3 . The bottom cover insulating layer  4  has a first half hole  40   a  formed on a lateral side thereof, and a second half hole  40   b  and a third half hole  40   c  respectively formed on an opposite lateral side thereof. In addition, referring to  FIG. 1C , the bottom cover insulating layer  4  has a fourth power output portion  41  and a fifth power output portion  42 . The fourth power output portion  41  and the fifth power output portion  42  are formed on a bottom surface of the bottom cover insulating layer  4 . 
         [0036]    Furthermore, referring to  FIG. 1D , each lateral conductive layer ( 51 ,  51  or  53 ) from top to bottom is formed on lateral sides of the top cover insulating layer  1 , the over-current protection layer  2 , the middle insulating layer M, the multifunctional protection layer  3 , and the bottom cover insulating layer  4  in sequence. The first lateral conductive layer  51  is a power input side Vin, the second lateral conductive layer  52  is a power output side Vout, and the third lateral conductive layer  53  is a grounding side G. 
         [0037]    In addition, the first half hole  10   a  of the top cover insulating layer  1 , the first half hole  20   a  of the over-current protection layer  2 , the first half hole Ma of the middle insulating layer M, the first half hole  30   a  of the multifunctional protection layer  3 , and the first half hole  40   a  of the bottom cover insulating layer  4  are stacked together to form a first lateral penetrating groove  61 . The second half hole  10   b  of the top cover insulating layer  1 , the second half hole  20   b  of the over-current protection layer  2 , the second half hole Mb of the middle insulating layer M, the second half hole  30   b  of the multifunctional protection layer  3 , and the second half hole  40   b  of the bottom cover insulating layer  4  are stacked together to form a first lateral penetrating groove  62 . 
         [0038]    The third half hole  10   c  of the top cover insulating layer  1 , the third half hole  20   c  of the over-current protection layer  2 , the third half hole Mc of the middle insulating layer M, the third half hole  30   c  of the multifunctional protection layer  3 , and the third half hole  40   c  of the bottom cover insulating layer  4  are stacked together to form a first lateral penetrating groove  63 . 
         [0039]    Therefore, the first lateral penetrating groove  61  is composed of the first half hole ( 10   a ,  20   a , Ma,  30   a ,  40   a ) that are respectively formed on the same sides of the top cover insulating layer  1 , the over-current protection layer  2 , the middle insulating layer M, the multifunctional protection layer  3 , and the bottom cover insulating layer  4 . The second lateral penetrating groove  62  is composed of the second half hole ( 10   b ,  20   b , Mb,  30   b ,  40   b ) that are respectively formed on the same opposite sides of the top cover insulating layer  1 , the over-current protection layer  2 , the middle insulating layer M, the multifunctional protection layer  3 , and the bottom cover insulating layer  4 . The third lateral penetrating groove  63  is composed of the third half hole ( 10   c ,  20   c , Mc,  30   c ,  40   c ) that are respectively formed on the same opposite sides of the top cover insulating layer  1 , the over-current protection layer  2 , the middle insulating layer M, the multifunctional protection layer  3 , and the bottom cover insulating layer  4 . 
         [0040]    Moreover, the first lateral penetrating groove  61 , the second lateral penetrating groove  62 , and the third lateral penetrating groove  63  separated from each other are combined to formed a lateral penetrating groove unit  6 . In addition, the first lateral conductive layer  51  is formed on an inner surface of the first lateral penetrating groove  61 , the second lateral conductive layer  52  is formed on an inner surface of the second lateral penetrating groove  62 , and the third lateral conductive layer  53  is formed on an inner surface of the third lateral penetrating groove  63 . 
         [0041]    Hence, the first power input portion  11  and the second power input portion  21  are electrically connected with each other via the first lateral conductive layer  51 . The second power output portion  22 , the third power input portion  31  and the fourth power output portion  41  are electrically connected with each other via the second lateral conductive layer  52 . The third power output portion  32  and the fifth power output portion  42  are electrically connected with each other via the third lateral conductive layer  53 . 
         [0042]    Referring to  FIGS. 1A to 1C , the arrows mean the direction of current in the above-mentioned figures. The main path of the current in each layer from the top cover insulating layer  1  to the bottom cover insulating layer  4  is shown as follows: 
         [0043]    First layer (the top cover insulating layer  1 ): The current flows from the first power input portion  11  of the top cover insulating layer  1  to the second power input portion  21  via the first lateral conductive layer  51 . 
         [0044]    Second layer (the over-current protection layer  2 ): The current flows through the second electrode layer  2 B, the positive temperature coefficient material layer  2 C, and the first electrode layer  2 A in sequence and flows from the second power input portion  21  to the second power output portion  22 . Hence, the present invention has the function of OCP (Over-Current Protection) due to the material property of the positive temperature coefficient material layer  2 C. 
         [0045]    Third layer (the middle insulating layer M): The current flows from the second power output portion  22  to the third power input portion  31  of the multifunctional protection layer  3  via the second lateral conductive layer  52 . 
         [0046]    Fourth layer (the multifunctional protection layer  3 ): The flowing direction of the current is determined according to the setting of the multifunctional chip unit  33 . Hence, the normal current flows to next layer directly. The abnormal current flows from the third power input portion  31  to the third power output portion  32  through the multifunctional chip unit  33 . For example, the multifunctional chip unit  33  is an OVP (Over-Voltage Protection) chip and the voltage load of the OVP chip is 5 volt. Hence, when the current is smaller than 5 volt, the current is outputted normally; when the current is larger than 5 volt, the current is transmitted to the grounding side through the OVP chip. 
         [0047]    Fifth layer (the bottom cover insulating layer  4 ): The normal current flows from the third power input portion  31  to the fourth power output portion  41  of the bottom cover insulating layer  4  via the second lateral conductive layer  52 . The abnormal current flows from the third power output portion  32  to the fifth power output portion  42  of the bottom cover insulating layer  4 , and then is transmitted to the grounding side. 
         [0048]    Referring to  FIGS. 2A and 2B ,  FIG. 2A  shows a perspective view of an over-current protection layer according to the second embodiment of the present;  FIG. 2B  shows a reversed, perspective view of an over-current protection layer according to the second embodiment of the present. 
         [0049]    Referring to the above-mentioned figures, the second power input portion  21 ′ is one side of the first electrode layer  2 A′, and the second power output portion  22 ′ is one side of the second electrode layer  2 B′. The first electrode layer  2 A′ has third insulating portion S 3 ′ insulated from the second lateral conductive layer  52 ′ and the third lateral conductive layer  53 ′. The second electrode layer  2 B′ has a first insulating portion S 1 ′ insulated from the first lateral conductive layer  51 ′ and a second insulating portion S 2 ′ insulated from the third lateral conductive layer  53 ′. Hence, the first electrode layer  2 A′ and the second electrode layer  2 B′ are insulated from the third lateral conductive layer  53 ′ via the third insulating portion S 3 ′ and the second insulating portion S 2 ′, respectively. 
         [0050]    Therefore, the current path of second layer (the over-current protection layer  2 ′) of the second embodiment is that the current flows through the first electrode layer  2 A′, the positive temperature coefficient material layer  2 C′, and the second electrode layer  2 B′ in sequence and flows from the second power input portion  21 ′ to the second power output portion  22 ′. 
         [0051]    Referring to  FIGS. 3A and 3B ,  FIG. 3A  shows a perspective view of a multifunctional protection layer according to the third embodiment of the present;  FIG. 3B  shows a reversed, perspective view of a multifunctional protection layer according to the third embodiment of the present. The third power input portion  31 ′, the third power output portion  32 ′, and the multifunctional chip unit  33 ′ are formed on a bottom surface of the multifunctional protection layer  3 ′. In addition, the bottom cover insulating layer  4 ′ has an opening  40 ′ for receiving the multifunctional chip unit  33 ′. 
         [0052]    Furthermore, the present invention can combine the first embodiment and the third embodiment, so the third power input portion  31 , the third power output portion  32 , and the multifunctional chip unit  33  are formed on the top surface of the multifunctional protection layer  3  (as shown in the first embodiment), and the third power input portion  31 ′, the third power output portion  32 ′, and the multifunctional chip unit  33 ′ are formed on the bottom surface of the multifunctional protection layer  3 ′ (as shown in the third embodiment). In other words, the two third power input portions can be respectively formed on a top surface and a bottom surface of the multifunctional protection layer, and the two third power output portions can be respectively formed on a top surface and a bottom surface of the multifunctional protection layer. 
         [0053]      FIG. 4A  is a perspective view of a first arrangement of a multifunctional chip unit according to the present. The multifunctional chip unit  33 A is composed of a plurality of functional chips ( 33   a   1 ,  33   a   2 ,  33   a   3 ) such as an OVP (Over-Voltage Protection) chip, an anti-EMI (anti-Electromagnetic Interference) chip, and an anti-ESD (anti-Electrostatic Discharge) chip. Moreover, the functional chips ( 33   a   1 ,  33   a   2 ,  33   a   3 ) are parallelly and electrically connected between the third power input portion  31  and the third power output portion  32 . 
         [0054]      FIG. 4B  shows a perspective view of a second arrangement of a multifunctional chip unit according to the present. The multifunctional chip unit  33 B is composed of a plurality of functional chips ( 33   b   1 ,  33   b   2 ) that can be any selected from the group consisting of an OVP (Over-Voltage Protection) chip, an anti-EMI (anti-Electromagnetic Interference) chip, and an anti-ESD (anti-Electrostatic Discharge) chip. Moreover, the functional chips ( 33   b   1 ,  33   b   2 ) are seriesly and electrically connected between the third power input portion  31  and the third power output portion  32 . 
         [0055]      FIG. 4C  shows a perspective view of a third arrangement of a multifunctional chip unit according to the present. The multifunctional chip unit  33 C is composed of a plurality of functional chips ( 33   c   1 ,  33   c   2 ,  33   c   3 ,  33   c   4 ) that can be any selected from the group consisting of an OVP (Over-Voltage Protection) chip, an anti-EMI (anti-Electromagnetic Interference) chip, and an anti-ESD (anti-Electrostatic Discharge) chip. Moreover, the functional chips ( 33   c   1 ,  33   c   2 ,  33   c   3 ,  33   c   4 ) are parallelly, seriesly and electrically connected between the third power input portion  31  and the third power output portion  32 . 
         [0056]      FIG. 5  shows a flowchart of a method for manufacturing an embedded type multifunctional integrated structure according to the present. The method for manufacturing the embedded type multifunctional integrated structure includes: 
         [0057]    Step S 100  is providing a top cover insulating layer that has at least one first power input portion. 
         [0058]    Step S 102  is providing a over-current protection layer that has a second power input portion and a second power output portion; 
         [0059]    Step S 104  is providing a middle insulating layer that has an opening; 
         [0060]    Step S 106  is providing a multifunctional protection layer that has a third power input portion, a third power output portion, and a multifunctional chip unit electrically connected between the third power input portion and the third power output portion, and the multifunctional chip unit being received in the opening of the middle insulating layer; 
         [0061]    Step S 108  is providing a bottom cover insulating layer that has a fourth power output portion and a fifth power output portion; 
         [0062]    Step S 110  is making the top cover insulating layer, the over-current protection layer, the middle insulating layer, the multifunctional protection layer, and the bottom cover insulating layer stacked together in sequence; and 
         [0063]    Step S 112  is forming a first lateral conductive layer, a second lateral conductive layer, and a third lateral conductive layer that are insulated from each other; each lateral conductive layer from top to bottom being formed on lateral sides of the top cover insulating layer, the over-current protection layer, the middle insulating layer, the multifunctional protection layer, and the bottom cover insulating layer in sequence. Therefore, the first power input portion and the second power input portion is electrically connected with each other via the first lateral conductive layer; the second power output portion, the third power input portion and the fourth power output portion is electrically connected with each other via the second lateral conductive layer; the third power output portion and the fifth power output portion is electrically connected with each other via the third lateral conductive layer. 
         [0064]    Moreover, before the step of forming the three lateral conductive layers (S 112 ), the method further comprising forming a first lateral penetrating groove, a second lateral penetrating groove, and a third lateral penetrating groove that are separated from each other. Each lateral penetrating groove is formed via drilling or punching the top cover insulating layer, the over-current protection layer, the middle insulating layer, the multifunctional protection layer, and the bottom cover insulating layer in sequence. The first lateral conductive layer is formed on an inner surface of the first lateral penetrating groove, the second lateral conductive layer is formed on an inner surface of the second lateral penetrating groove, and the third lateral conductive layer is formed on an inner surface of the third lateral penetrating groove. 
         [0065]      FIG. 6  shows a perspective view of a stacked structure with five layers according to the present invention (before many embedded type multifunctional integrated structure are cut from the stacked structure). Each top cover insulating layer  1 , each over-current protection layer  2 , each middle insulating layer M, each multifunctional protection layer  3 , and each bottom cover insulating layer  4  are drilled or punched in sequence to form a plurality of penetrating holes H. Many conductive layers from top to bottom are respectively coated on inner surfaces of the penetrating holes H of each top cover insulating layer  1 , each over-current protection layer  2 , each middle insulating layer M, each multifunctional protection layer  3 , and each bottom cover insulating layer  4 . Finally, each embedded type multifunctional integrated structure P (as shown in  FIG. 1D ) is cut from the stacked structure. Hence, the present invention can manufacture many embedded type multifunctional integrated structure P at the same time. 
         [0066]    Although the present invention has been described with reference to the preferred best molds thereof, it will be understood that the invention is not limited to the details thereof. Various substitutions and modifications have been suggested in the foregoing description, and others will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims.