Abstract:
In one embodiment, a buried-channel transistor is fabricated by masking a portion of an active region adjacent to a trench and implanting a dopant in an exposed portion of the active region to adjust a threshold voltage of the transistor. By masking a portion of the active region, the dopant is substantially prevented from getting in a region near an edge of the trench. Among other advantages, this results in reduced leakage current.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates generally to integrated circuits, and more particularly to integrated circuit fabrication processes and structures.  
           [0003]    2. Description of the Background Art  
           [0004]    Integrated circuits fabricated using complementary metal oxide semiconductor (CMOS) technology have traditionally employed a single N+ doped polysilicon gate material for both N-channel metal oxide semiconductor (NMOS) and P-channel metal oxide semiconductor (PMOS) transistors. Due to the work function of N+ polysilicon, this results in a surface-channel NMOS transistor and a buried-channel PMOS transistor. The surface-channel NMOS transistor typically has good short-channel characteristics and can be scaled to gate dimensions of 0.1 um and below. The buried-channel PMOS transistor typically has poor short-channel characteristics and, as a result, is designed with a larger threshold voltage than the surface-channel NMOS transistor to limit sub-threshold leakage current. Thus, the threshold voltage of a PMOS transistor is typically about 0.2V larger than the threshold voltage of an NMOS transistor of the same gate length in order to produce the same off-state leakage current. For integrated circuits using supply voltages of 3.3V or higher, the larger threshold voltage of the buried-channel PMOS is generally not a problem and good performance can be achieved. However, as the supply voltage scales below 3.3V, the higher threshold voltage starts to have a significant effect on performance.  
           [0005]    To improve PMOS transistor performance, a so-called “dual gate” approach may be used to fabricate CMOS integrated circuits requiring supply voltages of 2.5V and below. The dual gate approach involves the use of N+ doped polysilicon gate for the NMOS transistor and P+ doped polysilicon gate for the PMOS transistor. The use of P+ polysilicon produces a surface-channel PMOS transistor that improves short-channel characteristics and enables the threshold voltage of the PMOS transistor to be reduced to about the same value as the NMOS transistor. Unfortunately, the dual gate approach is not feasible in some applications. For example, the dual gate approach is not typically implemented in CMOS memory applications due to constraints imposed by the memory cell architecture and requirements. As a result, many memory applications have continued to use a single N+ doped polysilicon gate material for both NMOS and PMOS transistors even as power supply voltages have scaled down to 1.8V.  
           [0006]    From the foregoing, a technique for improving the performance of buried-channel transistors is highly desirable.  
         SUMMARY  
         [0007]    In one embodiment, a buried-channel transistor is fabricated by masking a portion of an active region adjacent to a trench and implanting a dopant in an exposed portion of the active region to adjust a threshold voltage of the transistor. By masking a portion of the active region, the dopant is substantially prevented from getting in a region near an edge of the trench. Among other advantages, this results in reduced leakage current.  
           [0008]    These and other features of the present invention will be readily apparent to persons of ordinary skill in the art upon reading the entirety of this disclosure, which includes the accompanying drawings and claims. 
       
    
    
     DESCRIPTION OF THE DRAWINGS  
       [0009]    [0009]FIG. 1 schematically shows a top view of a section of a substrate.  
         [0010]    [0010]FIGS. 2A and 2B schematically show side cross-sectional views of the substrate of FIG. 1.  
         [0011]    [0011]FIGS. 3A and 3B schematically show the sample of FIGS. 2A and 2B after implantation steps.  
         [0012]    [0012]FIG. 4 schematically shows a top view of an implant mask.  
         [0013]    [0013]FIG. 5 schematically shows a top view of a transistor.  
         [0014]    [0014]FIGS. 6A and 6B schematically show side cross-sectional views of the transistor of FIG. 5.  
         [0015]    [0015]FIG. 7 schematically shows a top view of a section of a substrate where a transistor will be fabricated in accordance with an embodiment of the present invention.  
         [0016]    [0016]FIGS. 8A and 8B schematically show side cross-sectional views of the substrate of FIG. 7.  
         [0017]    [0017]FIGS. 9A and 9B show the sample of FIGS. 8A and 8B after implantation steps in accordance with an embodiment of the present invention.  
         [0018]    [0018]FIG. 10 schematically shows a top view of an implant mask in accordance with an embodiment of the present invention.  
         [0019]    [0019]FIGS. 11A and 11B show side cross-sectional views of the sample of FIGS. 9A and 9B after a buried-channel implantation step in accordance with an embodiment of the present invention.  
         [0020]    [0020]FIG. 12 schematically shows a top view of an implant mask in accordance with an embodiment of the present invention.  
         [0021]    [0021]FIG. 13 schematically shows a top view of a transistor in accordance with an embodiment of the present invention.  
         [0022]    [0022]FIGS. 14A and 14B schematically show side cross-sectional views of the transistor of FIG. 13.  
         [0023]    [0023]FIGS. 15 and 16 show plots of experimental results. 
     
    
       [0024]    The use of the same reference label in different drawings indicates the same or like components. Drawings are not necessarily to scale unless otherwise noted.  
       DETAILED DESCRIPTION  
       [0025]    In the present disclosure, numerous specific details are provided such as examples of materials, process steps, and structures to provide a thorough understanding of embodiments of the invention. Persons of ordinary skill in the art will recognize, however, that the invention can be practiced without one or more of the specific details. In other instances, well known details are not shown or described to avoid obscuring aspects of the invention.  
         [0026]    The present invention relates to buried-channel transistors. Although the present invention will be described using a trench-isolated buried-channel PMOS transistor as an example, it should be noted that embodiments of the present invention may be employed in the fabrication of buried-channel transistors in general.  
         [0027]    [0027]FIG. 1 schematically shows a top view of a section of a substrate, which may comprise homogenous silicon, epitaxial silicon, or silicon on insulator (SOI). In FIG. 1, an active region  102  defines an area of the substrate where a transistor (e.g., transistor  550  shown in FIG. 5) will be formed. Dimension D 104  represents the width of active region  102 . Active region  102  may be surrounded by shallow trench isolation structures to separate the subsequently formed transistor in active region  102  from other transistors.  
         [0028]    [0028]FIG. 2, which consists of FIGS. 2A and 2B, schematically shows side cross-sectional views of the substrate of FIG. 1. FIG. 2A schematically shows a side cross-sectional view taken at section A-A of FIG. 1, while FIG. 2B shows a side cross-sectional view taken at section B-B. In FIG. 2, the substrate is labeled as substrate  201 . Trenches  202 , which may be shallow trench isolation structures, may be conventionally formed in substrate  201 . An implant screen oxide may be formed over active region  102  prior to subsequent implantation steps discussed below.  
         [0029]    [0029]FIG. 3, which consists of FIGS. 3A and 3B, schematically shows the sample of FIG. 2 after an N-well implant (NWI), an anti-punchthrough implant (APTI), and a buried-channel implant (BCI). FIG. 3A is from the perspective of FIG. 2A, while FIG. 3B is from the perspective of FIG. 2B.  
         [0030]    The N-well implant forms an N-well  303  and a transistor channel by implanting an N-type dopant, such as phosphorus or arsenic, in substrate  201 . The N-well implant is performed at relatively high energy to form an N-well  303  with a depth typically between about 0.5 μm and 2.0 μm and concentration between about 2.0×10 16  cm −3  and 2.0×10 18  cm −3 .  
         [0031]    The anti-punchthrough implant forms an anti-punchthrough region  304  by implanting an N-type dopant, such as phosphorus, arsenic, or antimony, in substrate  201 . The anti-punchthrough implant helps control punchthrough and short-channel effects. The anti-punchthrough implant results in an anti-punchthrough region  304  with a depth typically between about 0.1 μm and 0.4 μm and a peak concentration typically between about 2.0×10 16  cm −3  and 2.0×10 18  cm −3 .  
         [0032]    The buried-channel implant forms a buried-channel region  305  by implanting a P-type dopant, such as boron or indium, in substrate  201 . For example, a P-type dopant may be implanted using boron difluoride as a precursor. The buried-channel implant is performed to adjust the threshold voltage of the transistor. The buried-channel implant results in a buried-channel region  305  with a depth typically between about 0.02 μm and 0.10 μm and a peak concentration typically between about 2.0×10 16  cm −3  and 2.0×10 18  cm −3 .  
         [0033]    [0033]FIG. 4 schematically shows a top view of an implant mask  404  over active region  102 . In FIG. 4, the area inside the borders of mask  404  represents an opening in the mask. That is, mask  404  exposes active region  102  and surrounding regions. Mask  404 , which may be a photoresist mask, is typically formed over substrate  201  as a mask for the N-well, anti-punchthrough, and buried-channel implants of FIG. 3. Thus, the just mentioned implants are performed in active region  102  and surrounding regions. Dimension D 104  is shown in FIG. 4 for reference purposes. Mask  404  may be stripped after the N-well, anti-punchthrough, and buried-channel implants.  
         [0034]    After the implant steps, a drain, a source, a gate, and associated transistor structures may then be conventionally formed in the sample of FIG. 3. FIG. 5 schematically shows a top view of a transistor  550  formed in active region  102 . Dimension D 104  and mask  404  are depicted in FIG. 5 for references purposes. FIG. 6, which consists of FIGS. 6A and 6B, schematically shows side cross-sectional views of transistor  550 . FIG. 6A shows a side cross-sectional view of transistor  550  taken at section D-D of FIG. 5, while FIG. 6B shows a side cross-sectional view of transistor  550  taken at section C-C.  
         [0035]    Referring to FIGS. 5 and 6, transistor  550  includes a source  501 , a drain  502 , and a gate  503 . Not specifically labeled is the channel of transistor  550 , which is a region under gate  503  and between source  501  and drain  502 . In this example, transistor  550  is a trench-isolated buried-channel PMOS transistor. A complementary NMOS transistor is not shown for clarity of illustration.  
         [0036]    Source  501  and drain  502  may be conventionally formed P-type regions with source and drain extensions, respectively. A metal  504  may be coupled to source  501  by one or more plugs  507  (i.e.,  507 A,  507 B, . . . ). Similarly, a metal  505  may be coupled to drain  502  by one or more plugs  506  (i.e.,  506 A,  506 B, . . . ). Not all of plugs  506  and  507  are labeled in FIG. 5 for clarity of illustration. As shown in FIG. 6B, a metal  510  may be coupled to gate  503  by a plug  508 . Plugs  506 ,  507 , and  508  may be of an electrically conductive material such as tungsten, for example. Plugs  506 ,  507 , and  508  are in vias formed through a dielectric layer  603 , which may be a layer of silicon dioxide.  
         [0037]    Referring to FIG. 6B, the use of a mask  404  that exposes active region  102  and surrounding regions to the buried-channel implant results in buried-channel region  305  directly abutting edges of trenches  202 . In the present disclosure, an edge of an isolation trench is also referred to as an “isolation edge”. Dashed areas  605  show where buried-channel region  305  directly abuts edges of trenches  202 . The inventor believes that parasitic transistor behavior may occur in dashed areas  605  because of a phenomena commonly known as “inverse narrow-width effect.” Inverse narrow-width effect results in a lower threshold voltage for narrow transistors than for wide transistors. That is, inverse narrow-width effect may result in the lowering of the threshold voltage of transistor  550  as dimension D 104  is reduced. As it relates to the present invention, the inventors believe that inverse narrow-width effect results in parasitic transistors in dashed areas  605 , effectively having three transistors in active region  102 . This results in parasitic leakage current along the edge of a trench  202 . The parasitic leakage current, referred to as “isolation edge leakage current”, can dominate the overall leakage current as the width of the channel of transistor  550  is reduced. Isolation edge leakage current is also a significant problem in low-leakage devices such as static random access memory (SRAM) devices.  
         [0038]    One possible approach to the isolation edge leakage current problem is to increase the threshold voltage of all transistors in a device so that the leakage current of the narrowest transistor in the device is acceptable. However, this approach will degrade the performance of wide transistors in the device. Another possible approach to the isolation edge leakage current problem is to implant a dopant, such as an N-type dopant in the case of a PMOS transistor, into the sidewall of a trench before the trench is filled with oxide. Depending on the process employed by the device manufacturer, this approach may require at least three additional steps in the trench formation process namely, mask patterning, implant, and resist strip.  
         [0039]    FIGS.  7 - 14  schematically illustrate the fabrication of a buried-channel transistor in accordance with an embodiment of the present invention. Beginning in FIG. 7, there is schematically shown a top view of a section of a substrate, which is labeled as “substrate 801” in subsequent figures (e.g., see FIG. 8A). Substrate  801  may comprise homogenous silicon, epitaxial silicon, or silicon on insulator, for example. In FIG. 7, an active region  702  defines an area of substrate  801  where a transistor (e.g., transistor  1350  of FIG. 13) will be formed. Dimension D 704  represents the width of active region  702 , and thus is proportional to the width of the transistor channel formed therein. Active region  702  may be surrounded by shallow trench isolation structures to separate the subsequently formed transistor in active region  702  from other transistors.  
         [0040]    [0040]FIG. 8, which consists for FIGS. 8A and 8B, schematically shows side cross-sectional views of substrate  801 . FIG. 8A schematically shows a side cross-sectional view taken at section E-E of FIG. 7, while FIG. 8B schematically shows a side cross-sectional view taken at section F-F. Trenches  802  may be shallow trench isolation structures conventionally formed in substrate  801 , and may be filled with silicon dioxide. An implant screen oxide may be formed over active region  702  prior to subsequent implantation steps discussed below.  
         [0041]    In the following discussion, well known steps that are not necessary to the understanding of the invention have been omitted for clarity of illustration. For example, as is well known, a thermal anneal step may be performed after an implant step to electrically activate implanted dopants. The thermal anneal step may be performed right after the implant, or at a later processing step. Additionally well known masking steps that are not necessary to the understanding of the invention are not described for clarity of illustration.  
         [0042]    [0042]FIG. 9, which consists of FIGS. 9A and 9B, shows the sample of FIG. 8 after an N-well implant, an anti-punchthrough implant, and a first buried-channel implant (BCI-1). FIG. 9A is from the perspective of FIG. 8A, while FIG. 9B is from the perspective of FIG. 8B.  
         [0043]    An N-well implant may be performed on the sample of FIG. 8 to form an N-well  903  and a transistor channel in substrate  801 . Examples of N-type dopants that may be implanted in substrate  801  to form N-well  903  include phosphorous and arsenic. The N-well implant may be performed at relatively high energy to form an N-well  903  with a depth between about 0.5 μm and 2.0 μm and concentration between about 2.0×10 16  cm −3  and 2.0×10 18  cm −3 .  
         [0044]    An anti-punchthrough implant may be performed on the sample of FIG. 8 by implanting an N-type dopant, such as phosphorus, arsenic, or antimony, in substrate  801 . The anti-punchthrough implant helps control punchthrough and short-channel effects. The anti-punchthrough implant results in an anti-punchthrough region  904  with a depth between about 0.1 μm and 0.4 μm and a peak concentration between about 2.0×10 16  cm −3  and 2.0×10 18  cm −3 .  
         [0045]    In accordance with an embodiment of the present invention, a buried-channel implant for adjusting the threshold voltage of a transistor may be split into two steps. A first buried-channel implant may be performed in substrate  801  using the same implant mask (e.g., mask  1014  of FIG. 10) as that used for the N-well and anti-punchthrough implants. After the first buried-channel implant, a second buried-channel implant may be performed using a different implant mask. The mask for the second buried-channel implant preferably blocks a region near an isolation edge (e.g., see mask  1214  of FIG. 12).  
         [0046]    A first buried-channel implant may be performed by implanting a P-type dopant in substrate  801 . Examples of P-type dopants that may be used in the first buried-channel implant include boron and indium. The first buried-channel implant may create a profile in the channel with a depth between about 0.02 μm and 0.10 μm and a peak concentration between about 2.0×10 16  cm −3  and 2.0×10 18  cm −3 . The first buried-channel implant adjusts the threshold voltage of the transistor being formed in active region  702 .  
         [0047]    [0047]FIG. 10 schematically shows a top view of an implant mask  1014  over active region  702 . In FIG. 10, the area inside the borders of mask  1014  represents an opening in the mask. Mask  1014  may be used as a mask for the N-well implant, anti-punchthrough implant, and first buried-channel implant of FIG. 9. Thus, the just mentioned implants are performed in active region  702  and surrounding regions. Dimension D 704  is shown in FIG. 10 for reference purposes. Mask  1014 , which may be a photoresist mask, may be stripped after the N-well implant, anti-punchthrough implant, and first buried-channel implant.  
         [0048]    [0048]FIG. 11, which consists of FIGS. 11A and 11B, shows side cross-sectional views of the sample of FIG. 9 after a second buried-channel implant (BCI-2). FIG. 11A is from the perspective of FIG. 9A, while FIG. 11B is from the perspective of FIG. 9B. The second buried-channel implant may be performed by implanting a P-type dopant, such as boron or indium, in substrate  801  using an implant mask  1214 . For example, a P-type dopant may be implanted using boron difluoride as a precursor. The second buried-channel implant further adjusts the threshold voltage of the transistor to be formed in active region  702 . The second buried-channel implant results in a buriedchannel region  1105  with a depth between about 0.02 μm and 0.10 μm and a peak concentration between about 2.0×10 16  cm −3  and 2.0×10 18  cm −3 .  
         [0049]    [0049]FIG. 12 schematically shows a top view of implant mask  1214  over active region  702 . In FIG. 12, the area inside the borders of mask  1214  represents an opening in the mask. Mask  1214 , which may be a photoresist mask, may be used as a mask for the second buried-channel implant of FIG. 11. Dimension D 704  is shown in FIG. 12 for reference purposes. As can be appreciated, the design of mask  1214  should take into account the effects of misalignment, feature size variation of mask  1214  and a trench  802 , lateral implant straggle, and lateral diffusion.  
         [0050]    As shown in FIG. 11B and FIG. 12, mask  1214  blocks portions of active region  702  near an edge of a trench  802 . This prevents the second buried-channel implant from getting into regions near an edge of a trench  802 , thereby preventing the formation of a parasitic transistor near the isolation edge. As a result, isolation edge leakage current is reduced. As shown in FIG. 11B, the resulting buried-channel region  1105  after the second buried-channel implant does not directly abut an edge of a trench  802  along the length of active region  702 .  
         [0051]    As shown in FIG. 11A and FIG. 12, regions along the width of active region  702  (i.e., along dimension  704 ) do not necessarily have to be covered by mask  1214  to reduce isolation edge leakage current.  
         [0052]    In FIG. 12, a dimension D 1202  (i.e., D 1202 A or D 1202 B) represents the distance between an edge of an opening of mask  1214  and an edge of a trench  802 . A dimension D 1202  is also depicted in FIG. 11B. In one embodiment, a dimension D 1202  is about 0.28 μm. A dimension D 1202  may also be between about 0.1 μm and 0.5 μm. A dimension D 1202  may also be varied to meet the needs of specific applications.  
         [0053]    Mask  1214  may be stripped from the sample of FIG. 11 after the second buried-channel implant. Thereafter, a drain, a source, a gate, and associated transistor structures may be conventionally formed in the sample of FIG. 11.  
         [0054]    [0054]FIG. 13 schematically shows a top view of a transistor  1350  formed in active region  702  in accordance with an embodiment of the present invention. Dimension D 704 , a dimension D 1202 , and mask  1214  are depicted in FIG. 13 for reference purposes. FIG. 14, which consists of FIGS. 14A and 14B, schematically shows side cross-sectional views of transistor  1350 . FIG. 14A shows a side cross-sectional view of transistor  1350  taken at section G-G of FIG. 13, while FIG. 14B shows a side cross-sectional view of transistor  1350  taken at section H-H.  
         [0055]    Referring to FIGS. 13 and 14, transistor  1350  includes a source  1301 , a drain  1302 , and a gate  1303 . Not specifically labeled is the channel of transistor  1350 , which is a region under gate  1303  and between source  1301  and drain  1302 . In this example, transistor  1350  is a trench-isolated buried-channel PMOS transistor. A complementary NMOS transistor, which may have been fabricated concurrently with transistor  1350  using conventional CMOS processing, is not shown for clarity of illustration.  
         [0056]    Source  1301  and drain  1302  may be conventionally formed P-type regions with source and drain extensions, respectively. A metal  1304  may be coupled to source  1301  by one or more plugs  1307  (i.e.,  1307 A,  1307 B, . . . ). Similarly, a metal  1305  may be coupled to drain  1302  by one or more plugs  1306  (i.e.,  1306 A,  1306 B, . . . ). Not all of plugs  1306  and  1307  are labeled in FIG. 13 for clarity of illustration. As shown in FIG. 14B, a metal  1310  may be coupled to gate  1303  by a plug  1308 . Plugs  1306 , 1307 , and  1308  may be of an electrically conductive material such as tungsten, for example. Plugs  1306 ,  1307 , and  1308  are in vias formed through a dielectric layer  1403 , which may be a layer of silicon dioxide.  
         [0057]    Still referring to FIG. 14B, gate  1303  may comprise a dielectric  1311  of silicon nitride and a gate material  1312  of polysilicon. Below gate material  1312  may be a thin oxide layer (not shown). Spacers  407  may also be formed on the sidewalls of gate  1303 . Spacers  407  may be of silicon nitride, for example. The length of gate  1303  is depicted in FIG. 13 as dimension D 1362 .  
         [0058]    Comparing dashed areas  1405  of FIG. 14B with dashed areas  605  of FIG. 6B, note that buried-channel region  1105  does not directly abut an edge of a trench  802  along the length of active region  702 . This helps minimize parasitic transistor behavior in dashed areas  1405 , thereby reducing isolation edge leakage current.  
         [0059]    As can be appreciated by those of ordinary skill in the art reading the present disclosure, the just described technique for fabricating a buried-channel transistor with reduced isolation edge leakage current may be employed to fabricate different types of devices with buried-channel transistors. For example, a buried-channel transistor that only receives the first buried-channel implant step will have a relatively high threshold voltage and will still exhibit inverse narrow-width effects, while another buried-channel, relatively narrow transistor in the same device may receive both the first and second buried-channel implants to have a relatively low threshold voltage and reduced isolation edge leakage current. This approach provides more flexibility to the circuit designer as she can selectively choose transistors that need the low leakage current. As another example, a single buried-channel implant that is blocked from isolation edges (using a mask  1214  of FIG. 12, for example) may be used to fabricate all buried-channel transistors in a device. This will allow all relatively narrow buried-channel transistors in the device to have reduced isolation edge leakage current.  
         [0060]    Four different types of PMOS transistors were fabricated in one experiment. The characteristics of each type of PMOS transistor employed in the experiment are listed in Table 1.  
       TABLE 1  
       [0061]    [0061]                                         TABLE 1                                   Blocked Isolation Edge   Width/Length (μm)                                    Type-1   NO   25/0.4       Type-2   YES   25/0.4       Type-3   NO    4/0.4       Type-4   YES    4/0.4                    
         [0062]    All of the PMOS transistors in the experiment received a two-step buried-channel implant. In Table 1, the “Blocked Isolation Edge” column indicates whether the PMOS transistor received a second buried-channel implant (i.e., BCI-2) where the isolation edge is blocked (e.g., see FIG. 11B). As shown in Table 1, Type-1 and Type-3 PMOS transistors did not receive a second buried-channel implant where the isolation edge is blocked. The Type-2 and Type-4 PMOS transistors received a second buried-channel implant with blocked isolation edge. For the Type-2 and Type-4 PMOS transistors, the distance between an edge of an opening of the blocking implant mask and an edge of the isolation trench (e.g., see dimension D 1202  of FIG. 12) is about 0.28 μm.  
         [0063]    The “width/length” column shows the width of the active region of the PMOS transistor (e.g., see dimension D 704  of FIG. 13) and the length of its gate (e.g., see dimension D 1362  of FIG. 13). For example, a Type-1 PMOS transistor did not receive a buried-channel implant with blocked isolation edge, has an active region width of 25 μm, and has a gate length of 0.4 μm. The Type-1 and Type-2 PMOS transistors represent wide transistors, while the Type-3 and Type-4 PMOS transistors represent narrow transistors.  
         [0064]    [0064]FIG. 15 shows plots of experimental results for the Type-1 and Type-2 PMOS transistors. In FIG. 15, the horizontal axis represents gate voltage in volts, while the vertical axis represents drain current in amps. The results of FIG. 15 were obtained using the source as a voltage potential reference. Also in FIG. 15:  
         [0065]    (a) plot  1512  is for a Type-1 PMOS transistor with a drain voltage of −1.95 volts;  
         [0066]    (b) plot  1513  is for a Type-2 PMOS transistor with a drain voltage of −1.95 volts;  
         [0067]    (c) plot  1522  is for a Type-1 PMOS transistor with a drain voltage of −0.1 volt; and  
         [0068]    (d) plot  1523  is for a Type-2 PMOS transistor with a drain voltage of −0.1 volt.  
         [0069]    Comparing plot  1512  to plot  1513  and plot  1522  to plot  1523 , blocking the isolation edge for the buried-channel implant results in reduced leakage current (see the resulting drain current) even for relatively wide transistors. This result holds true even as the magnitude of the drain voltage is decreased from 1.95 volts to 0.1 volts.  
         [0070]    [0070]FIG. 16 shows plots of experimental results for the Type-3 and Type-4 PMOS transistors. In FIG. 16, the horizontal axis represents gate voltage in volts, while the vertical axis represents drain current in amps. The results of FIG. 16 were obtained using the source as a voltage potential reference. Also in FIG. 16:  
         [0071]    (a) plot  1612  is for a Type-3 PMOS transistor with a drain voltage of −1.95 volts;  
         [0072]    (b) plot  1613  is for a Type-4 PMOS transistor with a drain voltage of −1.95 volts;  
         [0073]    (c) plot  1622  is for a Type-3 PMOS transistor with a drain voltage of −0.1 volt; and  
         [0074]    (d) plot  1623  is for a Type-4 PMOS transistor with a drain voltage of −0.1 volt.  
         [0075]    Comparing plot  1612  to plot  1613  and plot  1622  to plot  1623 , blocking the isolation edge for the buried-channel implant results in reduced leakage current (see the resulting drain current) even more so for relatively narrow transistors than for relatively wide transistors. This result holds true even as the magnitude of the drain voltage is decreased from 1.95 volts to 0.1 volts.  
         [0076]    Table 2 below summarizes the leakage current (I OFF ) at V GS =0V (i.e., gate-source voltage of zero volt) and V DS =−1.95V (i.e., drain-source voltage of −1.95 volts), and saturation current (I DSAT ) at V GS =V DS =−1.8V for the four types of PMOS transistors evaluated in the experiment. As shown in Table 2, performing a buried-channel implant with blocked isolation edge results in reduced leakage current even for relatively wide transistors. For relatively narrow transistors, blocking the isolation edge for the buried-channel implant may result in significant reduction in leakage current.  
       TABLE 2  
       [0077]    [0077]                                                 TABLE 2                                   Blocked Isolation                   Edge   I OFF  (pA/μm)   I DSAT  (μA/μm)                                    Type-1 (wide)   No   −0.43   −73.3       Type-2 (wide)   Yes   −0.19   −73.8       Type-3 (narrow)   No   −9.05   −82.0       Type-4 (narrow)   Yes   −0.35   −74.9                    
         [0078]    While specific embodiments of the present invention have been provided, it is to be understood that these embodiments are for illustration purposes and not limiting. Many additional embodiments will be apparent to persons of ordinary skill in the art reading this disclosure. For example, for any of the implant steps described above, a single implant may be replaced by a sequence of implants using various species, energies, and doses to optimize the resulting implant profile. The sequence of masking and implant steps may also be varied. Thus, the present invention is limited only by the following claims.