Abstract:
A method of forming a semiconductor device includes: forming a pattern having trenches on a semiconductor substrate; forming a semiconductor layer on the semiconductor device that fills the trenches; planarizing the semiconductor layer using a first planarization process without exposing the pattern; performing an epitaxy growth process on the first planarized semiconductor layer to form a crystalline semiconductor layer; and planarizing the crystalline semiconductor layer until the pattern is exposed to form a crystalline semiconductor pattern.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 of Korean Patent Application No. 2007-16450, filed on Feb. 16, 2007, the entire contents of which are hereby incorporated by reference. 
       FIELD OF THE INVENTION 
       [0002]    The present invention disclosed herein relates to methods of forming semiconductor devices, for example, to methods of forming semiconductor devices including a device isolation layer. 
       BACKGROUND 
       [0003]    An example of a process of forming a device isolation layer is a shallow trench isolation (STI) process. The STI process includes etching a semiconductor substrate to form a trench, filling the trench with an insulating layer, and planarizing the insulating layer to fill the trench. As semiconductor devices become increasingly integrated, the aspect ratio of a trench can increase. As the aspect ratio of the trench increases, it can be difficult to fill the trench with an insulating layer. For example, in the case of flash memory devices, it can be difficult to fill the trench having a high aspect ratio only with a high density plasma (HDP) layer or an undoped silicate glass (USG) layer. To address this difficulty, a hybrid gap-fill structure having multiple layers including a spin-on glass (SOG) layer and the HDP layer has been introduced. However, the complexity of the hybrid gap-fill structure can increase cost. 
         [0004]    In the meantime, semiconductor devices are often required to be highly integrated to meet users&#39; demand for excellent performance at a low price. For this, a semiconductor device having a multilayer structure, for example, a flash memory device having a multilayer structure, has been introduced. The flash memory device having a multilayer structure may include a semiconductor substrate, a device isolation layer on the semiconductor substrate to define an active region, a tunnel-oxide layer on the active region, a floating gate electrode, a gate interlayer insulating layer, a control gate electrode, a top semiconductor layer, and a device isolation layer on the top semiconductor layer to define an active region. A process of forming a trench device isolation layer is performed to form a device isolation layer in the top semiconductor layer. In the process of forming a trench device isolation layer, the USG layer or the SOG layer may be used to fill a trench having a high aspect ratio. In the case of using the USG layer or the SOG layer, the process of forming a trench device isolation layer may include an annealing process at a high temperature. The annealing process at a high temperature may affect a tunnel oxide layer previously formed on the bottom portion of the top semiconductor layer. For example, the quality of the tunnel oxide layer may be degraded due to hot temperature stress (HTS). Thus, it can be difficult to apply the process of forming a trench device isolation layer to a semiconductor device having a multilayer structure. Moreover, since the process of forming a trench device isolation layer may include a number of processes, devices formed under the top semiconductor layer may be degraded. 
       SUMMARY OF THE INVENTION 
       [0005]    Exemplary embodiments of the present invention provide a method of forming a semiconductor device including: forming a pattern having trenches on a semiconductor substrate; forming a semiconductor layer on the semiconductor device that fills the trenches; planarizing the semiconductor layer using a first planarization process without exposing the pattern; performing an epitaxy growth process on the first planarized semiconductor layer to form a crystalline semiconductor layer; and planarizing the crystalline semiconductor layer until the pattern is exposed to form a crystalline semiconductor pattern. 
     
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
         [0006]    The accompanying figures are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present invention and, together with the description, serve to explain principles of the present invention. In the figures: 
           [0007]      FIGS. 1   a  through  1   f  are cross-sectional views illustrating a method of forming a semiconductor device in accordance with a first embodiment of the present invention. 
           [0008]      FIGS. 2   a  through  2   e  are cross-sectional views illustrating a method of forming a semiconductor device in accordance with a second embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0009]    Embodiments of the present invention will now be described more fully with reference to the accompanying drawings. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. 
         [0010]    It will be understood that, although the terms “first”, “second”, “third” etc. may be used herein to describe various components, materials, etc., the components, materials, etc. should not be limited by these terms. These terms are only used to distinguish one portion from another portion. It will also be understood that when an element such as a layer, region or substrate is referred to as being “on” or “onto” another element, it may be directly on the other element or intervening elements or layers may also be present. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. For example, the term “a conductive layer and/or an insulating layer” may include a conductive layer, an insulating layer, or a combination layer of a conductive layer and an insulating layer. 
         [0011]      FIGS. 1   a  through  1   f  are cross-sectional views illustrating a method of forming a semiconductor device in accordance with a first embodiment of the present invention. 
         [0012]    Referring to  FIG. 1   a,  an insulating layer  102  is formed on a semiconductor substrate  100 . The semiconductor substrate  100  may include a single crystalline silicon or a top semiconductor layer on the single crystalline silicon. A plurality of bottom semiconductor layers (not shown) may be between the single crystalline silicon and the top semiconductor layer. A tunnel insulating layer, a floating gate electrode, a floating interlayer insulating layer, and a control gate electrode may be formed on the bottom semiconductor layer. 
         [0013]    The semiconductor substrate  100  may include a first region (I) and a second region (II). The first region (I) may be a cell region. The second region (II) may be a peripheral region and/or a test element group (TEG) region. 
         [0014]    The insulating layer  102  may be a silicon oxide layer. The silicon oxide layer may include a low temperature silicon oxide (LTO) layer, a medium temperature silicon oxide (MTO) layer, or a high density plasma (HDP) silicon oxide layer. The insulating layer  102  may have a thickness of approximately 1000 angstroms to approximately 5000 angstroms. 
         [0015]    Referring to  FIG. 1   b,  the insulating layer  102  is patterned to form insulating patterns  102   a  and  102   b.  The insulating pattern  102   a  includes trenches  103   a  exposing the semiconductor substrate  100  in the first region I and the insulating pattern  102   b  includes trenches  103   b  exposing the semiconductor substrate  100  in the second region (II). Width of trench  103   b  in the second region (II) may be wider than width of trench  103   a  in the first region I. The widths of trenches  103   a,    103   b  may be defined as the distance between facing inside walls of the trenches. The insulating patterns  102   a  and  102   b  may be a device isolation layer for device isolation. 
         [0016]    Referring to  FIG. 1   c,  a semiconductor layer  104  is formed on the semiconductor substrate  100  to fill the trenches  103   a  of the first region I and the trenches  103   b  of the second region (II). The semiconductor layer  104  may be an amorphous silicon layer or a polysilicon layer. 
         [0017]    Referring to  FIG. 1   d,  the semiconductor layer  104  is planarized until the insulating pattern  102   a  and  102   b  is exposed, to form a first planarized semiconductor layer  104   a  and  104   b  in the first region (I) and second region (II), respectively. This first planarization process may be a chemical mechanical polishing (CMP) process. Since the width of the trench  103   b  of the second region (II) is wide, a dishing phenomenon may occur in the first planarized semiconductor layer  104   b.  The thickness of the center portion of the first planarized semiconductor layer  104   b  of the second region (II) may be less than that of outer portions of the first planarized semiconductor layer  104   b  adjacent to the insulating pattern  102   b  of the second region (II). 
         [0018]    Referring to  FIG. 1   e,  an epitaxy growth process is performed to the first planarized semiconductor layers  104   a  and  104   b  to form crystalline semiconductor layers  106   a  and  106   b.  The epitaxy growth process may be a laser epitaxy growth (LEG) process. The crystalline semiconductor layers  106   a  and  106   b  may include single crystalline silicon. 
         [0019]    The crystalline semiconductor layers  106   a  and  106   b  may include raised portions p and r that have hemispherical shapes. The raised portions p and r having hemispherical shapes may be formed when amorphous silicon is melted by a laser beam used in the laser epitaxy growth (LEG) process and solidified to become crystalline silicon. As shown, the raised portion r in the second region (II) protrudes from the top surface of the insulating pattern  102   b  of the second region (II). Portions of the raised portion p in the first region (I) adjacent to the insulating pattern  102   a  in the first region (I) may be lower than the top surface of the insulating pattern  102   a  of the first region (I). 
         [0020]    Referring to  FIG. 1   f,  the crystalline semiconducting layers  106   a  and  106   b  are planarized to form crystalline semiconductor patterns  107   a  and  107   b.  This second planarization process may be a chemical mechanical polishing (CMP) process. The crystalline semiconductor patterns  107   a  and  107   b  may be active regions. A tunnel insulating layer, a floating gate electrode, a floating interlayer insulating layer, and a control gate electrode may be formed on the crystalline semiconductor pattern  107   a  in the first region (I). A high voltage transistor and/or a low voltage transistor may be formed on the crystalline semiconductor pattern  107   b  of the second region (II). 
         [0021]    The crystalline semiconductor patterns  107   a  and  107   b  may have flat top surfaces since the crystalline semiconductor patterns  107   a  and  107   b  may be used as active regions. Since the raised portion p in the first region (I) adjacent to the insulating pattern  102   a  of the first region (I) may have formed lower than the top surface of the insulating pattern  102   a  in the first region (I), the raised portion p in the first region (I) and the top surface of the insulating pattern  102   a  of the first region (I) may be planarized simultaneously so that the crystalline semiconductor patterns  107   a  and  107   b  have flat top surfaces. As a result, the CMP process may require a long process time. The CMP process time may be over 200 seconds. 
         [0022]    Since the width of the trench  103   b  in the second region (II) is wide, a dishing effect may occur on the planarized crystalline semiconductor layer  107   b.  Moreover, since the CMP process may require a long process time, the dishing effect may be increased. Consequently, the thickness at the center of the planarized crystalline semiconductor layer  107   b  of the second region (II) may be less than that of portions of the planarized crystalline semiconductor layer  107   b  adjacent to the insulating pattern  102   b  in the second region (II). The thickness of the crystalline semiconductor pattern  107   b  in the second region (II) may be small depending on the degree of the planarization of the top surface of the insulating pattern  102   b.    
         [0023]    According to the first embodiment of the present invention, an insulating layer for device isolation is formed unlike certain conventional device isolation processes. The problem of filling a trench having a high aspect ratio with an insulating layer and degradation of performance of the devices formed under the top semiconductor layer may be reduced (e.g., solved). 
         [0024]      FIGS. 2   a  through  2   e  are cross-sectional views illustrating a method of forming a semiconductor device in accordance with a second embodiment of the present invention. 
         [0025]    Referring to  FIG. 2   a,  an insulating layer  202  is formed on a semiconductor substrate  200 . The semiconductor substrate  200  may include single crystalline silicon or a top semiconductor layer on the single crystalline silicon. A plurality of bottom semiconductor layers (not shown) may be formed between the single crystalline silicon and the top semiconductor layer. A tunnel insulating layer, a floating gate electrode, a floating interlayer insulating layer, and a control gate electrode may be formed on the bottom semiconductor layers. 
         [0026]    The semiconductor substrate  200  may include a first region (I) and a second region (II). The first region (I) may be a cell region. The second region (II) may be a peripheral region and/or a test element group (TEG). 
         [0027]    The insulating layer  202  may be a silicon oxide layer. The silicon oxide layer may include a low temperature silicon oxide (LTD) layer, a medium temperature silicon oxide (MTO) layer, or a high density plasma (HDP) silicon oxide layer. The insulating layer  102  may have a thickness of approximately 1000 angstroms to approximately 5000 angstroms. 
         [0028]    Referring to  FIG. 2   b,  the insulating layer  202  is patterned to form insulating patterns  202   a  and  202   b.  The insulating pattern  202   a  includes trenches  203   a  that expose the semiconductor substrate  200  in the first region I, and the insulating pattern  202   b  includes trenches  203   b  that expose the semiconductor substrate  200  in the second region (II). The width of trench  203   b  in the second region (II) may be wider than the width of trench  203   a  in the first region I. The widths of the trenches may be defined as the distance between facing inside walls of the trenches. The insulating patterns  202   a  and  202   b  may be a device isolation layer for device isolation. 
         [0029]    In some embodiments, an etch stop layer (not shown) may be formed on the semiconductor substrate  200  before the insulating pattern  202   a  and  202   b  is formed. The etch stop layer may be a silicon nitride layer. When the etch stop layer is a silicon nitride layer, a buffer layer (not shown) may be formed between the semiconductor substrate  200  and the etch stop layer. The buffer layer may be a silicon oxide layer. After the insulating layer  202   a  is formed, a liner layer (not shown) layer may be conformally formed on the trenches  203   a  of the first region (I). The liner layer may be a silicon nitride layer. The liner layer can be anisotropically etched to form a liner pattern on a sidewall of the trench  203   a  in the first region (I). 
         [0030]    Referring to  FIG. 2   c,  a semiconductor layer  204  is formed to fill the trenches  203   a  in the first region I and the trenches  203   b  in the second region (II). The semiconductor layer  204  may be an amorphous silicon layer or a polysilicon layer. 
         [0031]    Referring to  FIG. 2   d,  the semiconductor layer  204  is planarized, but without exposing the insulating pattern  202   a.  This first planarization process may be a chemical mechanical polishing (CMP) process. The distance between a top surface of the first planarized semiconductor layer  204   a  and the insulating layer  202   a  can be several hundreds of angstroms, for example, approximately 500 angstroms. 
         [0032]    Since the width of the trenches  203   b  in the second region (II) can be wider than that of the trenches  203   a  in the second region (I), a dishing effect may occur on the first planarized semiconductor layer  204   b.  But since the top surface of the first planarized semiconductor layers  204   a  and  204   b  is higher than the insulating patterns  202   a  and  202   b,  unlike the first embodiment of the present invention, the dishing effect caused by the first planarization process may affect any dishing effect caused by a subsequent second planarization process less. 
         [0033]    Referring to  FIG. 2   e,  an epitaxy growth process is performed on the first planarized semiconductor layers  204   a  and  204   b  to form a crystalline semiconductor layer  206   a  and  206   b.  The epitaxy growth process may be a laser epitaxy growth (LEG) process. The crystalline semiconductor layer  206   a  and  206   b  may include single crystalline silicon. The crystalline semiconductor layer  206   a  and  206   b  may have an etching selectivity with respect to the insulating pattern  202   a  and  202   b.    
         [0034]    The crystalline semiconductor layer  206   a  and  206   b  may include raised portions P and R. The raised portions P and R may be formed when amorphous silicon is melted by a laser beam used in the laser epitaxy growth (LEG) process and solidified to become crystalline silicon. The crystalline semiconductor layer  206   a  of the first region (I) may include raised portions having triangular shapes on the insulating pattern  202   a.  The crystalline semiconductor layer  206   b  of the second region (II) may include raised portions having hemispherical shapes on the insulating pattern  202   b.    
         [0035]    Referring to  FIG. 2   f,  the crystalline semiconductor layer  206   a  and  206   b  is planarized until the insulating pattern  202   a  and  202   b  is exposed to form a crystalline semiconductor pattern  207   a  and  207   b.  This second planarization process may be a chemical mechanical polishing (CMP) process. The CMP process time may be approximately 40 seconds. The second planarization process may include a slurry having silica. The solid powder concentration and acidity of the slurry can be approximately 0.01-20 wt % and approximately 8 to approximately 12, respectively. The slurry may further include an organic compound material, such as an amine. The crystalline semiconductor pattern  207   a  and  207   b  may be an active region. A tunnel insulating layer, a floating gate electrode, a floating interlayer insulating layer, and a control gate electrode may be formed on the crystalline semiconductor pattern  207   a  of the first region (I). A high voltage transistor and/or a low voltage transistor may be formed on the crystalline semiconductor pattern  207   b  of the second region (II). 
         [0036]    In some embodiments, a dishing effect may occur on the crystalline semiconductor pattern  207   b  of the second region (II), for example, due to the second planarization process. Unlike the first embodiment of the present invention, the crystalline semiconductor layers  206   a  and  206   b  may have the top surface higher than that of the insulating patterns  202   a  and  202   b.  As a result, the insulating pattern  202   a  is not required to be additionally planarized so that the crystalline semiconductor pattern  207   a  has a flat top surface. A second planarization process time may be reduced. The dishing effect in the crystalline semiconductor pattern  207   b  of the second region (II) caused by the second planarization process may be reduced. Also, since the crystalline semiconductor layers  206   a  and  206   b  may be planarized down to only the top surface of the insulating patterns  202   a  and  202   b,  an appropriate thickness for the device isolation and/or the active region may be maintained. Consequently, the crystalline semiconductor patterns  207   a  and  207   b  may have a flat top surface and maintain an appropriate thickness.