Abstract:
A method of controlling ferroelectric characteristics of integrated circuit device components includes forming a ferroelectrically controllable dielectric layer over a substrate; and forming a stress exerting structure proximate the ferroelectrically controllable dielectric layer such that a substantially uniaxial strain is induced in the ferroelectrically controllable dielectric layer by the stress exerting structure; wherein the ferroelectrically controllable dielectric layer comprises one or more of: a ferroelectric oxide layer and a normally non-ferroelectric material layer that does not exhibit ferroelectric properties in the absence of an applied stress.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a divisional of U.S. patent application Ser. No. 12/753,270, filed Apr. 2, 2010, now U.S. Pat. No. 8,389,300, the disclosure of which is incorporated by reference herein in its entirety. 
    
    
     BACKGROUND 
     The present invention relates generally to semiconductor devices and, more particularly, to controlling ferroelectricity in dielectric films by process-induced strain therein. 
     Integrated ferroelectrics have many current or potential future uses in microelectronics, including, for example, ferroelectric field effect transistor (FET) memory, ferroelectric metal-insulator-metal (MIM) capacitor memory, and ultra low-power/voltage complementary metal oxide semiconductor (CMOS) logic, to name a few. 
     At present, there are few good candidate ferroelectric materials for such applications, due to a large number of requirements (e.g., a ferroelectric transition temperature (T c ) well above room temperature, high remanent polarization, good retention, low fatigue, etc.). One such production-worthy material is lead zirconate titanate (Pb[Zr x Ti 1-x ]O 3  0&lt;x&lt;1, or PZT by its chemical formula). PZT is a ceramic material with a perovskite crystal structure that shows substantial ferroelectricity, i.e., generation of spontaneous electric polarization (electric dipoles) in the presence of an electric field. However, one disadvantage of using PZT in microelectronic applications is the introduction of lead (Pb) into the manufacturing line, which creates environmental concerns. Also, PZT exhibits a considerable loss of switchable polarization with cumulative switching cycles. 
     Another such ferroelectric material is SrBi 2 Ta 2 O 9  or SBT. One disadvantage associated with SBT (in addition to the complexity of the composition of SBT, having three metal ions) relates to process control concerns, such as high processing temperatures. Other potential ferroelectric candidates have too low a transition temperature, T c , or too low a spontaneous or remanent polarization, P r , for some applications. For example, BaTiO 3  has a T c  of about 120° C., which is too close to room temperature for applications at room temperature. 
     Consequently, other approaches have focused on significantly enhancing and/or tuning T c  or P r  in ferroelectric materials through the introduction of biaxial strain. Biaxial strain in ferroelectric thin films has thus far been achieved experimentally by coherent epitaxy of the ferroelectric material on a substrate (e.g., oxide) with low lattice mismatch. For example, biaxial strain in BaTiO 3  thin films (achieved by coherent epitaxy on scandate substrates such as DyScO 3  or GdScO 3 ) can result in a ferroelectric transition temperature T c  nearly 500° C. higher and a remanent polarization P r  at least 250% higher than in bulk BaTiO 3  single crystals. In this case, the strain is biaxial and compressive. In addition, biaxial strain may also be achieved in other ferroelectrics such as PbTiO 3  or BiFeO 3  via epitaxy. Yet other approaches have focused on inducing ferroelectricity in normally non-ferroelectric materials through the introduction of biaxial strain. For example, biaxial strain in SrTiO 3  films (achieved by coherent epitaxy on scandate substrates such as DyScO 3  or GdScO 3 ) can result in ferroelectricity at room temperature. 
     However, the biaxial strain of ferroelectrics via epitaxy has its own limitations. For example, direct epitaxy on silicon requires molecular beam epitaxy (MBE) deposition for high quality epitaxy. Here, the strain cannot be tuned, and once a critical thickness is achieved the strain is relaxed. Thus, the modulated ferroelectric properties can be obtained only for a limited thickness range. Moreover, direct epitaxy of a ferroelectric oxide such as BaTiO 3  on Si leads to high leakage currents due to a negative or very small band offset with respect to the silicon conduction band. 
     SUMMARY 
     In an exemplary embodiment, a method of controlling ferroelectric characteristics of integrated circuit device components includes forming a ferroelectrically controllable dielectric layer over a substrate; and forming a stress exerting structure proximate the ferroelectrically controllable dielectric layer such that a substantially uniaxial strain is induced in the ferroelectrically controllable dielectric layer by the stress exerting structure; wherein the ferroelectrically controllable dielectric layer comprises one or more of: a ferroelectric oxide layer and a normally non-ferroelectric material layer that does not exhibit ferroelectric properties in the absence of an applied stress. 
     In another embodiment, a ferroelectric field effect transistor (FET) device includes a ferroelectrically controllable gate dielectric layer disposed between a gate electrode and a substrate; and a stress exerting structure formed proximate the ferroelectrically controllable dielectric layer such that a substantially uniaxial strain is induced in the ferroelectrically controllable dielectric layer by the stress exerting structure; wherein the ferroelectrically controllable gate dielectric layer comprises one or more of: a ferroelectric oxide layer and a normally non-ferroelectric material layer that does not exhibit ferroelectric properties in the absence of an applied stress. 
     In still another embodiment, a ferroelectric metal-insulator-metal (MIM) capacitor includes a lower electrode layer formed over a substrate; a capacitor dielectric layer including a ferroelectrically controllable dielectric layer formed over the lower electrode; an upper electrode layer formed over the ferroelectrically controllable dielectric layer; and a stress exerting structure formed proximate the ferroelectrically controllable dielectric layer such that a substantially uniaxial strain is induced in the ferroelectrically controllable dielectric layer; wherein the ferroelectrically controllable gate dielectric layer comprises one or more of: a ferroelectric oxide layer and a normally non-ferroelectric material layer that does not exhibit ferroelectric properties in the absence of an applied stress. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       Referring to the exemplary drawings wherein like elements are numbered alike in the several Figures: 
         FIG. 1  is a cross-sectional view of an FET having a gate dielectric layer that is ferroelectrically controllable by strain engineering, in accordance with an embodiment of the invention; 
         FIG. 2  illustrates the formation of epitaxial source and drain regions providing a substantially uniaxial strain on the ferroelectrically controllable gate dielectric layer of the FET of  FIG. 1 ; 
         FIG. 3  illustrates the formation of a compressive nitride stress layer over an FET having a gate dielectric layer that is ferroelectrically controllable by strain engineering, in accordance with another embodiment of the invention; 
         FIG. 4  illustrates the formation of a tensile nitride stress layer over an FET having a gate dielectric layer that is ferroelectrically controllable by strain engineering, in accordance with another embodiment of the invention; and 
         FIGS. 5(   a ) through  5 ( d ) are a series of cross-sectional views illustrating the formation of a MIM capacitor having a dielectric layer that is ferroelectrically controllable by strain engineering, in accordance with another embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     Disclosed herein are methods and structures for controlling ferroelectricity in dielectric films by process-induced strain of the film. Certain exemplary embodiments are used to induce ferroelectricity, wherein a normally non-ferroelectric material when not strained, such as SrTiO 3  or CaMnO 3  for example, becomes ferroelectric when strained. Other exemplary embodiments tune the existing ferroelectricity of dielectric films, wherein the properties (T c , P r ) of ferroelectrics in their processed state are modulated, thus widening the spectrum of possible materials (such as BaTiO 3 , for example) that may be used in microelectronic applications, as well as to improve the performance of existing ferroelectric devices (such as PZT based devices, for example). 
     In the embodiments described herein, ferroelectrically controllable materials, such as normally non-ferroelectric materials or ferroelectric materials, initially deposited on silicon or other types of semiconductor substrates (e.g., silicon-on-insulator (SOI), Ge, III/V, etc.) are strained substantially uniaxially by CMOS-type techniques. “Substantially uniaxially,” as used herein, describes a strain introduced in one direction of a surface, such as an x-direction or a y-direction. This is in contrast to, for example, a biaxial strained film that has strain introduced in two directions (x-y) along its surface. It should be understood, however, that “substantially unaxially” may also describe strain primarily along one axis (e.g., the x-axis) with some minimal, “de minimis,” or non-zero strain component along the other axis. In addition, “CMOS-type” techniques as described herein may include, for example, source/drain silicon germanium (SiGe) regions adjacent a silicon channel region, nitride liner formation, and combinations thereof. 
     In any case, no epitaxy of the dielectric film is required, and both compressive and tensile strain (uniaxial) can be achieved (using silicon nitride), and the level of strain can be modulated thus significantly modulating T c  and P r . Implementation of process-induced strain in ferroelectric oxides can thus be achieved through integration schemes common in chip technology, currently employed for enhancing mobility in the transistor channel. Practical embodiments of tuned ferroelectric dielectric films by process-induced strain include, but are not limited to, FETs and MIM capacitors. 
     Referring initially to  FIG. 1 , there is shown a cross-sectional view of an FET  100  formed in a substrate  102 , such as silicon or SOI for example. The transistor, formed between shallow trench isolation (STI) regions  104 , includes a patterned gate electrode  106 , sidewall spacers  108  adjacent the gate electrode  106 , and a gate dielectric layer  110  between the gate electrode  106  and the substrate  102 . Here, a conventional material for the gate dielectric layer  110  (such as silicon dioxide, for example) is replaced by a dielectric stack containing a ferroelectrically controllable layer. Again, a ferroelectrically controllable layer may be a layer such as a ferroelectric material or a normally non-ferroelectric material that exhibits ferroelectric properties upon application of an external stress thereto. Non-limiting examples of a ferroelectrically controllable layer included within the gate dielectric layer  110  include BaTiO 3 , PZT, SBT, SrTiO 3  (STO), Ba 1-x Sr x TiO 3  (BST), PbTiO 3 , CaMnO 3  and BiFeO 3 . 
     In the case of bulk SrTiO 3 , oxygen rotation is responsible for a non-polar, antiferrodistortive ground state. Both ferroelectric and antiferrodistortive distortions can coexist under appropriate strain, and the change in the coupling between these instabilities can be such that it leads to a new ground state (i.e., ferroelectric). As such, there is no obvious fundamental reason why uniaxial stress (resulting in a uniaxial strain or possibly in a more complex strain distribution) would not result in a change in the ground state of such strongly correlated complex oxide. 
     Although the gate dielectric layer  110  illustrated in  FIG. 1  is depicted as being patterned with gate electrode such that the spacers  108  also abut the sidewalls of the gate dielectric layer  110 , it is also contemplated that the gate dielectric layer  110  could be separately patterned with respect to the gate electrode  110  such that (for example) the spacers  108  are disposed atop the gate dielectric layer  110 . In addition to the ferroelectrically controllable layer, the dielectric layer  110  may also include one or more buffer layers between the ferroelectrically controllable layer and the substrate  102 . Moreover, the dielectric layer  110  shown in  FIG. 1  may also include one or more additional dielectric layers disposed between the ferroelectrically controllable layer and the gate electrode  110 , and/or the substrate  102 . 
     As will also be noted from  FIG. 1 , the source and drain regions  112  have been removed such as by etching to make way for epitaxial growth of a different semiconductor material, such as silicon germanium (SiGe) or carbon-doped silicon (Si:C). The epitaxial material  114  is illustrated in  FIG. 2 . As a result, a uniaxial compressive or tensile strain is induced on not only the channel region of the transistor below the gate dielectric layer  110 , but also in the gate dielectric layer  110  itself. For example, where the epitaxial material  114  is SiGe, the induced uniaxial strain is compressive. Alternatively, if the epitaxial material  114  is Si:C, for example, the induced uniaxial strain is tensile. Thereby, the epitaxially induced stress on the gate dielectric layer  110  induces and/or modulates the ferroelectric properties of the gate dielectric layer  110 . In still a further contemplated embodiment, the source and drain regions  112  may be provided with embedded stress exerting semiconductor material through the use of dopant implantation into silicon. 
     In addition to, or in lieu of, an epitaxial source/drain stress exerting semiconductor material, other uniaxial stress/strain techniques can also be used to induce/modulate ferroelectric properties of dielectric layers. As shown in  FIG. 3 , the substrate  102  of the FET  100  is doped with a suitable dopant material to form source and drain regions  116  (as well as source/drain extension regions beneath the gate). That is, in the embodiment of  FIG. 3 , a stress is not generated from the source/drain semiconductor material. Instead, a nitride liner  118  (e.g., silicon nitride) is formed over the FET  100 . In the example depicted, the nitride layer  118  is a compressive nitride layer, in that it provides a uniaxial compressive stress on both the channel region of the substrate  102  and the gate dielectric layer  110 . In addition to inducing/modulating ferroelectric properties in the gate dielectric layer  110 , as discussed above, the compressive nitride layer  118  is also used to enhance carrier mobility in PMOS FET devices. 
     By way of comparison,  FIG. 4  illustrates the FET  100  with a tensile nitride liner  120  that generates a uniaxial tensile stress on both the channel region of the substrate  102  and the gate dielectric layer  110 . In addition to inducing/modulating ferroelectric properties in the gate dielectric layer  110 , as discussed above, the tensile nitride layer  120  is also used to enhance carrier mobility in NMOS FET devices. 
     Referring generally now to  FIGS. 5(   a ) through  5 ( d ), there is shown a series of cross-sectional views illustrating the formation of a MIM capacitor having a ferroelectrically controllable dielectric layer, in accordance with another embodiment of the invention. In  FIG. 5(   a ), a substrate  502  has a lower electrode layer  504 , a capacitor dielectric layer  506  including ferroelectrically controllable layer and an upper electrode layer  508  formed thereon in sequence as a stack. As is the case for the FET embodiments, the ferroelectrically controllable layer includes a ferroelectric layer or a normally non-ferro electric layer that exhibits ferroelectric properties upon application of an external stress thereto. Any suitable conductive materials may be used for the lower and upper electrode layers  504 ,  508 , including for example, platinum, iridium, ruthenium, titanium, titanium nitride, tantalum, tantalum nitride, iridium oxide, ruthenium oxide, copper, tungsten, or compounds thereof. 
     Similar to the FET embodiment, the capacitor dielectric layer  506  of the MIM capacitor, in addition to the ferroelectrically controllable layer, may also include one or more buffer layers and/or one or more additional dielectric layers disposed between the ferroelectrically controllable layer and the lower and upper electrode layers  504 ,  508 . 
     In  FIG. 5(   b ), the lower electrode layer  504 , ferroelectrically controllable layer  506  and upper electrode layer  508  are etched to a desired shape, followed by formation of a nitride stress layer  510  over the resulting capacitor stack, as shown in  FIG. 5(   c ). The nitride stress layer  510  may be made to be either tensile or compressive, as indicated by the arrows. As a result, ferroelectric properties of MIM capacitor are induced/modulated due to the uniaxial stress/strain. Finally, in  FIG. 5(   d ), an insulating layer (e.g., silicon dioxide)  512  is formed over the stressed ferroelectric MIM capacitor for further device processing. 
     While the invention has been described with reference to a preferred embodiment or embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims.