Abstract:
A temperature-compensated output buffer circuit is disclosed, which includes a pull-up circuit including a first pull-up transistor for providing a first pull-up output signal responsive to a pull-up input signal, and a supplemental pull-up circuit in parallel with the first pull-up transistor. The supplemental pull-up circuit is configured to generate a supplemental pull-up output signal with the first pull-up output signal and the supplemental pull-up output signal forming a pull-up output signal. The output buffer further includes a pull-down circuit, including a first pull-down transistor for providing a first pull-down output signal and a supplemental pull-down circuit in parallel with the first pull-down transistor. The supplemental pull-down circuit is configured to generate a supplemental pull-down output signal with the pull-up output signal and the pull-down output signal coupled to form an output buffer output signal. Methods of operation, memory devices, semiconductor substrates and electronic systems embodying the invention are also disclosed.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     Field of the Invention: The present invention relates generally to buffer circuits and, more particularly, to buffer circuits that compensate for environmental temperature changes.  
         [0002]     State of the Art: Electronic products are generally comprised of a plurality of integrated circuits which are coupled to or interfaced with other integrated circuits according to various bus structures or other data interfaces. Interface specifications for coupling integrated circuits with one another specify performance parameters such as voltage and current levels required for digital signals to be accurately and reliably exchanged between two or more integrated circuits. Integrated circuits complying with the interface specifications compatibly exchange information through the use of output buffer circuits which present identifiable logic conditions such as logic low and logic high signal states. Additionally, output buffer circuits provide a mechanism for compatibly interfacing different logic families of integrated circuits.  
         [0003]     An example of an output buffer circuit is illustrated with reference to  FIG. 1 . Generally, an output buffer circuit  10  uses an external voltage level, VCCQ, as a source for generating a logic high signal state. While technological advances result in a generally decreasing signal level for VCCQ, typical voltage ranges may include 1.8 volts to 5.5 volts. Output buffer circuits  10  generally use a lower voltage reference, VSSQ, which may be defined as a lesser positive or negative voltage level and more commonly utilizes a system potential reference or ground as a current sink to implement a logic low signal state. A typical output buffer circuit  10  generally includes complementary transistor devices, one of which is a p-channel pull-up transistor  12  with a source connected to VCCQ and a drain connected to an output terminal  14 . Output buffer circuit  10  further includes as another complementary transistor device an n-channel pull-down transistor  16  whose drain is connected to output terminal  14  with the source terminal connected to VSSQ.  
         [0004]     Operationally, a transistor, such as transistors  12  and  16 , when implemented as a metal-oxide semiconductor (MOS) transistor, behave as a constant current source when the drain-to-source voltage is greater than or equal to the difference between the threshold voltage and the gate-to-source voltage is in the saturation region. The MOS device when in the linear region behaves like a resistor when the drain-to-source voltage is less than the difference between the threshold voltage and the gate-to-source voltage.  
         [0005]     Each of the transistors  12 ,  16 , includes a gate input  18 ,  20  coupled to the respective input signals: pull-up signal and pull-down signal, which controls each transistor  12 ,  16  at the gate input  18 ,  20 . To generate a logic high signal state on output terminal  14 , a pull-up transistor  12  is turned on by logic at gate input  18  while a pull-down transistor  16  is turned off at gate input  20 . Accordingly, switching the output to a high logic state enables current to flow from VCCQ to output terminal  14  via pull-up transistor  12  while pull-down transistor  16  assumes a high impedence state. Similarly, a logic low signal state at output terminal  14  is output when the pull-up transistor  12  is turned off, thus generating a high impedance state between output terminal  14  and VCCQ. In such a high impedence state between VCCQ and output terminal  14 , current does not flow from VCCQ to output terminal  14 . Additionally, pull-down transistor  16  is turned on at gate input  20  allowing current to pass from output terminal  14  to VSSQ, generally implemented as a ground potential. In such a configuration, upper buffer circuit  10  functions as a sink for current at output terminal  14 . The gate inputs  18 ,  20  of pull-up transistor  12  and pull-down transistor  16  are typically coupled to receive a control signal having a logic level that activates one of the transistors and deactivates another one of the transistors.  
         [0006]     An output buffer circuit finds application in a semiconductor memory system such as those commonly used in computer or computer-related applications. A typical memory may be used to store data which may be utilized or processed by other integrated circuits, such as a microprocessor, which couples with the memory system. As memory system designs advance, faster transition times or data rates become factors in the implementation of interfacing specifications requiring advances in interfacing aspects such as output buffer circuits. As performance and transition times increase, environmental conditions, including temperature variations, introduce variations in the performance of the memory systems. For output buffer circuits implemented in semiconductor devices, it is common for the output buffer circuit to diminish in current drive capacity in response to increases in temperature. The reduction in current drive capability results in reduced operating speeds as signal transitions exhibited at an output terminal of an output buffer circuit transition at a much slower rate. Therefore, since the output buffer circuit transitions at a slower rate, the overall memory system exhibits an overall reduction in performance.  
         [0007]     Therefore, because the variations in environmental conditions associated with integrated circuits incorporating output buffer circuits result in unacceptable variations in logic level transition rates, there is a need for an improved output buffer circuit and methodology for accommodating variations in temperature conditions for high data rate devices.  
       BRIEF SUMMARY OF THE INVENTION  
       [0008]     The present invention in several embodiments is directed to a temperature-compensated output buffer including a method, circuit and system. In one embodiment of the present invention, an output buffer includes a pull-up circuit including a first pull-up transistor for providing a first pull-up output signal responsive to a pull-up input signal, and a supplemental pull-up circuit in parallel with the first pull-up transistor. The supplemental pull-up circuit is configured to generate a supplemental pull-up output signal with the first pull-up output signal, and the supplemental pull-up output signal coupled to form a pull-up output signal. The output buffer further includes a pull-down circuit, including a first pull-down transistor for providing a first pull-down output signal responsive to a pull-down input signal and a supplemental pull-down circuit in parallel with the first pull-down transistor. The supplemental pull-down circuit is configured to generate a supplemental pull-down output signal with the pull-up output signal and the pull-down output signal coupled to form an output buffer output signal.  
         [0009]     In another embodiment of the present invention, a memory device is provided which includes an array of memory cells, a plurality of data lines for access to the memory cells and an output buffer coupled between the array of memory cells and the plurality of data lines. The output buffer includes at least one output buffer circuit further including a supplemental pull-up circuit configured in parallel with a first pull-up transistor, with the supplemental pull-up circuit being responsive to a supplemental pull-up control signal variable over a temperature range. The output buffer further includes a supplemental pull-down circuit configured in parallel with a first pull-down transistor. The supplemental pull-down circuit being responsive to a supplemental pull-down control signal variable over a temperature range.  
         [0010]     In yet another embodiment of the present invention, a semiconductor substrate on which is fabricated a semiconductor memory device is provided. The substrate includes an array of memory cells, a plurality of data lines for access to the memory cells and an output buffer coupled between the array of memory cells and the plurality of data lines. The output buffer includes at least one output buffer circuit including a supplemental pull-up circuit configured in parallel with a first pull-up transistor. The supplemental pull-up circuit being responsive to a supplemental pull-up control signal which is variable over a temperature range. The output buffer further includes a supplemental pull-down circuit configured in parallel with a first pull-down transistor. The supplemental pull-down circuit being responsive to a supplemental pull-down control signal variable over a temperature range.  
         [0011]     In yet a further embodiment of the present invention, a method of providing a data output signal includes generating a first pull-up output signal in response to a first pull-up input signal. A supplemental pull-up output signal is generated which is responsive to a supplemental pull-up control signal with the supplemental pull-up control signal being variable with temperature variations. A first pull-down output signal is generated in response to a first pull-down input signal with a supplemental pull-down output signal being generated in response to a supplemental pull-down control signal, the supplemental pull-down control signal varying with temperature variations. The first pull-up output signal and the supplemental pull-up output signal are combined to form a pull-up output signal with the first pull-down output signal and the supplemental pull-down output signal to form a pull-down output signal.  
         [0012]     In yet an additional embodiment of the present invention, an electronic system comprising an input device, an output device, a memory device, and a processor device coupled to the input, output, and memory devices, at least one of the input, output, memory, and processor devices including a semiconductor memory is provided. The system includes an array of memory cells, a plurality of data lines for access to the memory cells and an output buffer coupled between the array of memory cells and the plurality of data lines. The output buffer includes at least one output buffer circuit comprising a supplemental pull-up circuit responsive to a supplemental pull-up control signal variable over a temperature range and a supplemental pull-down circuit responsive to a supplemental pull-down control signal variable over a temperature range.  
     
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS  
       [0013]     In the drawings, which illustrate what is currently considered to be the best mode for carrying out the invention:  
         [0014]      FIG. 1  is a circuit diagram of an output buffer circuit, in accordance with the prior art;  
         [0015]      FIG. 2  is a circuit diagram of an output buffer circuit including temperature compensating circuitry, in accordance with an embodiment of the present invention;  
         [0016]      FIG. 3  is a circuit diagram of an output buffer circuit including temperature compensating circuitry, in accordance with another embodiment of the present invention;  
         [0017]      FIG. 4  is a circuit diagram of a biasing circuit configured for generating biasing signals variable with varying temperature for coupling with an output buffer circuit, in accordance with an embodiment of the present invention;  
         [0018]      FIG. 5  illustrates an exemplary performance plot of an output buffer, in accordance with one or more embodiments of the present invention;  
         [0019]      FIG. 6  illustrates a block diagram of an output buffer incorporating a discrete biasing circuit, in accordance with an embodiment of the present invention;  
         [0020]      FIG. 7  is a block diagram of a memory system containing one or more integrated circuits having one or more output buffers, in accordance with an embodiment of the present invention;  
         [0021]      FIG. 8  is a block diagram of a system containing a memory device, according to an embodiment of the present invention; and  
         [0022]      FIG. 9  is a view of a bulk semiconductor substrate in the form of a semiconductor wafer including one or more integrated circuits having one or more output buffers associated therewith, in accordance with an embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0023]      FIG. 2  illustrates an exemplary output buffer circuit, in accordance with an embodiment of the present invention. An output buffer circuit  30  includes a first pull-up transistor  32  coupled between a supply voltage, VCCQ, and an output terminal  34  for providing at least a partial sourcing of current to output terminal  34  when activated by a pull-up signal at gate input  36 . While first pull-up transistor  32  may generally provide adequate pull-up sourcing of current to output terminal  34 , the performance of first pull-up transistor  32 , if configured individually, would reflect variations in sourcing current as exhibited at output terminal  34  over variations in temperature. To compensate for such sourcing variations over temperature, a supplemental pull-up circuit  38  is coupled in a parallel configuration with first pull-up transistor  32 . In one exemplary embodiment, supplemental pull-up circuit  38  includes a second pull-up transistor  40  and a third pull-up transistor  42 . Second pull-up transistor  40  includes a gate input  44  which is driven by a temperature compensating bias signal, PUP_bias. An exemplary circuit for generating the PUP_bias signal is discussed below with reference to  FIG. 4 . Third pull-up transistor  42  of supplemental pull-up circuit  38  includes a gate input  46  coupled to a pull-up signal, PUP.  
         [0024]     Output buffer circuit  30  further includes a first pull-down transistor  48  coupled between a voltage, VSSQ, and the output terminal  34  for providing at least a partial sinking of current from output terminal  34  when activated by a pull-down signal at gate input  50 . While first pull-down transistor  48  may generally provide adequate pull-down sinking of current from output terminal  34 , the performance of first pull-down transistor  48 , if configured individually, would reflect variations in sinking current, as exhibited at output terminal  34 , over variations in temperature. To compensate for such current sinking variations over temperature, a supplemental pull-down circuit  52  is coupled in a parallel configuration with first pull-down transistor  48 . In one exemplary embodiment, supplemental pull-down circuit  52  includes a second pull-down transistor  54  and a third pull-down transistor  56 . Second pull-down transistor  54  is coupled to a lower potential voltage, VSSQ, and is controlled on gate input  58  by a biasing signal, PDN_bias, which accommodates variations in sinking current associated with variations in temperature. A specific formation of PDN_bias signal is illustrated below with reference to  FIG. 4 . Third pull-down transistor  56  is coupled in a series configuration with second pull-down transistor  54 . Third pull-down transistor  56  is controlled at a gate input  60  by a pull-down signal, PDN, and in conjunction with the activation of second pull-down transistor  54 , augments the pull-down or sinking performance of first transistor  48 .  
         [0025]      FIG. 3  illustrates an exemplary output buffer circuit, in accordance with another embodiment of the present invention. An output buffer circuit  70  includes a first pull-up transistor  72  coupled between a supply voltage, VCCQ, and an output terminal  74  for providing at least a partial sourcing of current to output terminal  74  when activated by a pull-up signal at gate input  76 . While first pull-up transistor  72  may generally provide adequate pull-up sourcing of current to output terminal  74 , the performance of first pull-up transistor  72 , if configured individually, would reflect variations in sourcing current over variations in temperature as exhibited at output terminal  74 .  
         [0026]     To compensate for such sourcing variations over temperature, a supplemental pull-up circuit  78  is coupled in a parallel configuration with first pull-up transistor  72 . In one exemplary embodiment, supplemental pull-up circuit  78  includes a second pull-up transistor  80  which is coupled in parallel with first pull-up transistor  72 . Second pull-up transistor  80  is controlled at a gate input  82  which is further coupled to a third pull-up transistor  84  coupled between gate input  82  of second pull-up transistor  80  and a supply voltage, VCCQ. A gate input  86  of third pull-up transistor  84  is controlled by a pull-up signal, PUP, as passed through a first buffer  88 . Gate input  82  of second pull-up transistor  80  is also controlled by a fourth transistor  90  which is controlled at a gate input  92  by a pull-up signal, PUP. Fourth transistor  90  is coupled between gate input  82  of second pull-up transistor  80  and a second buffer  94  which is further coupled to a pull-up bias signal, PUP_bias, which is generated as described with reference to  FIG. 4 .  
         [0027]     Output buffer circuit  70  further includes a first pull-down transistor  152  coupled between a supply voltage, VSSQ, and an output terminal  74  for providing at least a partial sinking of current from output terminal  74  when activated by a pull-down signal at gate input  156 . While first pull-down transistor  152  may generally provide adequate pull-down sinking of current from output terminal  74 , the performance of first pull-down transistor  152 , if configured individually, would reflect variations in sinking current as exhibited at output terminal  74  over variations in temperature.  
         [0028]     To compensate for such sinking variations over temperature, a supplemental pull-down circuit  158  is coupled in a parallel configuration with first pull-down transistor  152 . In one exemplary embodiment, supplemental pull-down circuit  158  includes a second pull-down transistor  160  which is coupled in parallel with first pull-down transistor  152 . Second pull-down transistor  160  is controlled at a gate input  162  which is further coupled to a third pull-down transistor  164  coupled between gate input  162  of second pull-down transistor  160  and a reference voltage, VSSQ. A gate input  166  of third pull-down transistor  164  is controlled by a pull-down signal, PDN, as passed through a third buffer  168 . Gate input  162  of second pull-down transistor  160  is also controlled by a fourth transistor  170  which is controlled at a gate input  172  by a pull-down signal, PDN. Fourth transistor  170  is coupled between gate input  162  of second pull-down transistor  160  and a fourth buffer  174  which is further coupled to a pull-down bias signal, PDN_bias, which is generated as described with reference to  FIG. 4 .  
         [0029]      FIG. 4  is a schematic diagram of a biasing circuit, in accordance with an embodiment of the present invention. A biasing circuit  100  provides biasing control signals to output buffer circuits to facilitate temperature compensation for reducing the variations in logic level transitions associated with temperature as exhibited on the respective output terminals of the corresponding output buffer circuits described herein. Biasing circuit  100 , in conjunction with output buffer circuits, form an output buffer for interfacing an output of an integrated circuit with an input of another integrated circuit. Biasing circuit  100  generates a PDN_bias signal  102  exhibited in the form of a voltage which, in one embodiment, exhibits a positive temperature coefficient (PTAT). Biasing circuit  100  further generates a constant PUP_bias signal  104  which exhibits a complementary temperature coefficient (CTAT).  
         [0030]     Biasing circuit  100  comprises five individual circuit legs, each illustrated as passing respective currents I 1  through I 5 . The circuit legs passing currents I 1  and I 2  include transistors  106 ,  108 , which are coupled together with a differential amplifier  116  configured to operate by maintaining potential V 1  at location  126  at an equivalent potential as potential V 2  at location  128 . In order to maintain the equivalents in potential, differential amplifier  116  outputs a signal which drives each of the respective transistors  106 ,  108 ,  110  and  112 . The other respective components, namely D 1    130 , R 1    18  and D 2    132  form a temperature sensitive circuit which results in variations on the output of differential amplifier  116  which drives the other respective circuit legs.  
         [0031]     Biasing circuit  100  further comprises a circuit leg comprised of transistor  110  and resistor R 2    120  passing therethrough a current I 3 . This reference leg generates PDN_bias signal  102  which, in the present circuit, is implemented as a positive temperature coefficient (PTAT) which varies according to the temperature sensitivity of the circuits associated with the circuit legs passing the currents I 1  and I 2 .  
         [0032]     The remaining circuit legs passing currents I 4  and I 5  are implemented to include a transistor  112  coupled to transistors  122  and  124  configured in a current mirror arrangement which, in conjunction with resistor R 3    114 , form a complementary bias signal, PUP bias signal  104 , which in the present example is implemented as a complementary to absolute temperature (CTAT) reference.  
         [0033]     Biasing circuit  100  is configured as a low voltage temperature compensation bias voltage generating circuit, in accordance with an embodiment of the present invention. Biasing circuit  100  generates a constant PDN_bias voltage and a PUP_bias voltage according to the equations listed below. While a specific implementation is listed below, other variations for generating bias voltages are also contemplated within the scope of the present invention. In accordance with the illustrated embodiment, it is assumed that current I 1  and I 2  are attempted to be maintained the same through the use of a differential amplifier  116  which attempts to maintain V 1  equal to V 2 . From such an assumption, PDN_bias may be calculated as: 
 
 V   PDN   di —   bias   =n*V   T *1 nK*L.  
 
 With regard to the above equation, n is the emission coefficient (i.e., relative to the doping profile which in one exemplary process is approximately 1.0). Furthermore, V T  is the thermal voltage (i.e., which in one exemplary embodiment is about 25.4 mV at room temperature). The temperature coefficient of V PDN     —   bias is derivable by the following equations: 
 
 d ( V   PDN bias)/ dT=n* 1 nK*L*dV   T   /dT  
 
 dV   T   /dT  is a constant=0.085 mV/C. By picking  K= 8,  L= 17, using  n =1, we get 
 
 V   PDN     —   bias=898 mV at 25 C  d ( V   PDN     —   bias)/ dT= 3 mV/C 
 
         [0034]     For one conventional integrated circuit specification, a typical temperature range as specified is from 0 to 85° C. In one exemplary implementation, the voltage change between V 1  and V 2  is about 255 mV, which results in about ⅓ of the default value. From the above equations, it is shown that V PDN     —   bias and the d(V PDN     —   bias)/dT is not related to the resistor value or the transistor characteristics. Therefore, biasing circuit  100  is insensitive to process variations.  
         [0035]      FIG. 5  illustrates an exemplary performance plot of an output buffer, in accordance with one or more embodiments of the present invention. In plot  200 , variations in temperature are illustrated along the horizontal axis while variations in the voltage signals are illustrated using the vertical axis. According to the plot of  FIG. 5 , an output terminal of the output buffer circuit, when implemented in accordance with the prior art, exhibits variations in voltage across temperature as exhibited in curve  204  which exhibits a variation across the temperature range of approximately 2.77 ohms as exhibited at the output impedence of the output buffer DQ_out. When the biasing circuit  100  is employed in conjunction with one of the embodiments of the output buffer circuit to form an output buffer, variations in the output resistance across the temperature range results in a curve  210  having a variation  212  of approximately 0.29 ohms. An exemplary plot of the PDN_bias signal as utilized by the output buffer circuits, illustrates a range of approximately 257 mV which changes from about 0.79V to 1.05V within the 0 to 85° C. range.  
         [0036]      FIG. 6  is a block diagram of an output buffer, in accordance with an embodiment of the present invention. An output buffer  250  is configured to add and remove incremental discrete amounts of drive to an output terminal of an output buffer. Output buffer  250  includes a discrete biasing circuit  252  configured to output discrete control signals with varying levels of discrete resolution. By way of example and not limitation, three discrete supplemental control signals  254 ,  256 ,  258  are illustrated as originating from discrete biasing circuit  252  and are representative of discrete control signals corresponding to detected variations in temperature. Output buffer  250  further includes an output buffer circuit  260  which generates the respective drive levels for an output terminal  262 . Output buffer circuit  260  includes an output driver  264  which may be implemented according to first pull-up and pull-down transistors  32 ,  48  of  FIG. 2 . Output buffer circuit  260  further includes supplemental circuits  266  which, in one embodiment, may be implemented as a series of augmenting pull-up and pull-down circuit legs. In one embodiment, a default number of driver legs may be employed and is illustrated as default drive  268  corresponding to an identified ambient condition of operation for output buffer  250 . When lower temperatures are detected, a portion of the drive may be removed as illustrated by remove drive  270 . Similarly, when an increased temperature level is detected, additional legs or additional drive may be added to the output driver through the activation of an add drive  272 .  
         [0037]      FIG. 7  is a block diagram of a memory system containing one or more integrated circuits having one or more output buffers incorporated therein, in accordance with an embodiment of the present invention. Memory system  220  contains one or more memory modules  222  and a memory controller  224 . Each memory module  222  includes at least one memory device  226 . Memory controller  224  provides and controls a bidirectional interface between memory system  220  and an external system bus  228 . Memory system  220  accepts a command signal from the external bus  228  and relays it to one or more memory modules  222  on a command link  230 . Memory system  220  provides for data input and data output between the one or more memory modules  222  and external system bus  228  on data links  232 . At least one of the memory devices  226  includes the output buffer comprised of an output buffer circuit and a biasing circuit, as discussed with reference to the various embodiments of the present invention.  
         [0038]      FIG. 8  is a block diagram of a system containing a memory device, according to an embodiment of the present invention. Electronic system  240  contains a processor  242  and a memory system  244  housed in a computer unit  246 . Memory system  244  includes a memory device that includes the output buffer which is further comprised of an output buffer circuit and a biasing circuit, in accordance with the various embodiments of the present invention discussed herein. Electronic system  240  optionally includes user interface devices  234 , a monitor  236 , a printer  238  and a bulk storage device  248 . It will be appreciated that other components are often associated with electronic system  240 . It will be further appreciated that the processor  242  and memory  244 , can be on a single system or device.  
         [0039]     With regard to  FIG. 9 , memory devices of the type described herein are generally fabricated as on a bulk semiconductor substrate such as a wafer or other substrate, in the form of a silicon on insulator (SOD) substrate, including by way of example a silicon on glass (SOG) substrate, a silicon on sapphire (SOS) substrate and a silicon on ceramic (SOC) substrate a variety of semiconductor devices having integrated circuits fabricated thereon as shown in  FIG. 9 . The integrated circuits are  272  supported by a substrate  270 . Identical integrated circuits are typically replicated  272  many times on each bulks substrate and are further processed into separate semiconductor devices as is known by those of ordinary skill in the art.  
         [0040]     Although the foregoing description contains many specifics, these are not to be construed as limiting the scope of the present invention, but merely as providing certain exemplary embodiments. Similarly, other embodiments of the invention may be devised which do not depart from the spirit or scope of the present invention. The scope of the invention is, therefore, indicated and limited only by the appended claims and their legal equivalents, rather than by the foregoing description. All additions, deletions, and modifications to the invention, as disclosed herein, which fall within the meaning and scope of the claims, are encompassed by the present invention.