Abstract:
The present invention provides a means for optimization and re-use of hardware in the implementation of Viterbi and Turbo Decoders using carry save arithmetic. Successful provision for each target application requires that two main issues be confronted. These are: merging the computation of summation terms (a2−b2+c2) with (x2+y2+z2); and (a3+b3−c3) with (x3+y3+z3); implementing an efficient method of computing (a4−b4−c4); and merging this computation with (x4+y4+z4). The invention solves both of these issues and successfully merges the Viterbi instructions with a complete reuse of the hardware that is required for the implementation of Turbo instructions. The hardware required by both classes of instructions is optimized by efficiently employing carry save arithmetic.

Description:
TECHNICAL FIELD OF THE INVENTION 
       [0001]    The technical field of this invention is forward error correction. 
       BACKGROUND OF THE INVENTION 
       [0002]    Receivers capturing data can do so more efficiently if the data has been encoded allowing forward error correction. The Viterbi decoder uses the Viterbi algorithm for decoding a bitstream that has been encoded using Forward Error Correction based on a Convolutional code. The Viterbi algorithm is highly resource-consuming, but it does provide maximum likelihood decoding. 
         [0003]    Viterbi decoders employ Trellis decoding to estimate the most likely sequence of events that lead to a particular state. U.S. patent application Ser. No. 12/496,538 filed Feb. 1, 2009 entitled “METHOD AND APPARATUS FOR CODING RELATING TO FORWARD LOOP” describes faster decoding in Viterbi decoders by employing 2 bits of the Trellis decoding to be performed using DSP instructions called R4ACS Radix-4 Add Compare Select (RACS4) and Radix-4 Add Compare Decision (RACD). This invention deals with the implementation of this class of DSP instructions. 
         [0004]    Turbo codes are a type of forward error correction code with powerful capabilities. These codes are becoming widely used in many applications such as wireless handsets, wireless base stations, hard disk drives, wireless LANs, satellites, and digital television. A brief overview of Turbo decoders is summarized below. 
         [0005]    A functional block diagram of a turbo decoder is shown in  FIG. 1 . This iterative decoder generates soft decisions from a maximum-a-posteriori (MAP) block using the probabilities represented by a-posteriori feedback terms A 0    110  and A 1    109 . Each iteration requires the execution of two MAP decodes to generate two sets of extrinsic information. The first MAP decoder  102  uses the non-interleaved data as its input and the second MAP decoder  103  uses the interleaved data from the interleaver block  101 . 
         [0006]    The MAP decoders  102  and  103  compute the extrinsic information as: 
         [0000]    
       
         
           
             
               
                 
                   
                     W 
                     n 
                   
                   = 
                   
                     log 
                      
                     
                       
                         Pr 
                          
                         
                           ( 
                           
                             
                               x 
                               n 
                             
                             = 
                             
                               1 
                               | 
                               
                                 R 
                                 1 
                                 n 
                               
                             
                           
                           ) 
                         
                       
                       
                         Pr 
                          
                         
                           ( 
                           
                             
                               x 
                               n 
                             
                             = 
                             
                               0 
                               | 
                               
                                 R 
                                 1 
                                 n 
                               
                             
                           
                           ) 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where: R 1   n =(R 0 ,R 1 , . . . R n−1 ) denotes the received symbols. The MAP decoders also compute the a posteriori probabilities: 
         [0000]    
       
         
           
             
               
                 
                   
                     Pr 
                      
                     
                       ( 
                       
                         
                           x 
                           n 
                         
                         = 
                         
                           i 
                           | 
                           
                             R 
                             1 
                             n 
                           
                         
                       
                       ) 
                     
                   
                   = 
                   
                     
                       1 
                       
                         Pr 
                          
                         
                           ( 
                           
                             R 
                             1 
                             n 
                           
                           ) 
                         
                       
                     
                      
                     Σ 
                      
                     
                         
                     
                      
                     
                       Pr 
                        
                       
                         ( 
                         
                           
                             
                               x 
                               n 
                             
                             = 
                             i 
                           
                           , 
                           
                             
                               S 
                               n 
                             
                             = 
                             
                               m 
                               ′ 
                             
                           
                           , 
                           
                             
                               S 
                               
                                 n 
                                 - 
                                 1 
                               
                             
                             = 
                             m 
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
         [0000]    Here S n  refers to the state at time n in the trellis of the constituent convolutional code. 
         [0007]    The terms in the summation can be expressed in the form 
         [0000]        Pr ( x   n   =i,S   n   =m′,S   n−1   =m )=α n−1 ( m )γ n   i ( m,m ′)β n ( m ′)  (3)
 
         [0000]    where the quantity 
         [0000]      γ n   i ( m,m ′)= Pr ( S   n   =m′,x   n   =i,R   n   |S   n−1   =m )  (4)
 
         [0000]    is called the branch metric, and 
         [0000]      α n ( m ′)= Pr ·( S   n   =m′,R   1   n )  (5)
 
         [0000]    is called the forward (or alpha) state metric, and 
         [0000]      β( m ′)= Pr ( R   n+1   n   |S   n   =m′ )  (6)
 
         [0000]    is called the backward (or beta) state metric. 
         [0008]    The branch metric depends upon the systematic, parity, and extrinsic symbols. The extrinsic symbols for a given MAP decoder are provided by the other MAP decoder at inputs  109  and  110 . The alpha and beta state metrics are computed recursively by forward and backward recursions given by 
         [0000]      α n ( m ′)=α n−1 ( m )γ n   i ( m,m ′)  (7)
 
         [0000]    and 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       β 
                       
                         n 
                         - 
                         1 
                       
                     
                      
                     
                       ( 
                       m 
                       ) 
                     
                   
                   = 
                   
                     
                       Σ 
                       
                         
                           m 
                           ′ 
                         
                         , 
                         i 
                       
                     
                      
                     
                       
                         β 
                         n 
                       
                        
                       
                         ( 
                         
                           m 
                           ′ 
                         
                         ) 
                       
                     
                      
                     
                       
                         γ 
                         n 
                         ′ 
                       
                        
                       
                         ( 
                         
                           
                             m 
                             ′ 
                           
                           , 
                           m 
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
           
         
       
     
         [0000]    The slicer  107  completes the re-assembling of the output bit stream x 0  . . . x n−1    108 . 
         [0009]    The block diagram of the MAP decoder is shown in  FIG. 2 . The subscripts r and f present the direction, reverse and forward, respectively, of the sequence of the data inputs for the recursive blocks beta and alpha. Input bit streams  210 - 212  and  213 - 215  are labeled as parameters X n,r , P n,r , A n,r  and X n,f , P n,f , A n,f  respectively. Feedback streams are labeled α n,f  and β n,r . 
         [0010]    Both the alpha state metric block  202  and beta state metric block  203  calculate state metrics. Both start at a known location in the trellis, the zero state. The encoder starts the block of n information bits (frame size n=5114) at the zero state and after n cycles through the trellis ends at some unknown state. 
         [0011]    The mapping of this task of computing the branch metrics and adding to the previous state metrics, to a class of DSP instructions (T4MAX/T2MAX) is outside the scope of this invention. The current invention deals with the efficient implementation of this class of DSP instructions. 
         [0012]    One of the main sources of latency in computer arithmetic is the propagation of carries in the computation of a sum of two or more numbers. This is a well-studied area, which is not explored here except to note that the best algorithms for addition require a number of logic levels equal to: 
         [0000]      levels=2+log 2 *(width)  (9)
 
         [0000]    where: width is the number of bits representing the numbers to be added. 
         [0013]      FIG. 3  illustrates the three-to-two carry save circuit  302 , otherwise known as the 3:2 CSA circuit, which takes three inputs  301  ( a, b  and  c ) and produces two outputs  303  (S and C 0 ). This circuit has the property that when S and C 0  are added together, they produce the same result as adding a+b+c. This process is often referred to as compressing the three numbers down to two numbers. The 3:2 CSA is sometimes referred to as a 3:2 compressor. 
         [0014]    The three inputs can be any three bits, while the two outputs are the sum S and carry C 0  resulting from the addition of these three bits. These are computed based on the following logical equations: 
         [0000]        S=a⊕b⊕c   (10)
 
         [0000]        C   0 =( a*b )+( b*c )+( c*a )  (11)
 
         [0015]    The main advantage of using the 3:2 circuit is that equations (10) and (11) can typically be computed with a logic depth of no greater than 2. Thus it allows for faster computation of the sum of three numbers by preventing the carry from propagating. Therefore, given three numbers which need to be added together, rather than sequentially computing a+b=x, and then x+c, with a resulting delay 
         [0000]      delay=2*(2+log 2 *(width))  (12A)
 
         [0000]    one can process a+b+c through a 3:2 CSA compressor followed by an adder to achieve a total delay of: 
         [0000]      delay=4+log 2 *(width)  (12B)
 
         [0000]    The savings in the number of logic level delays becomes even more pronounced when the width of the operands involved is large. 
       SUMMARY OF THE INVENTION 
       [0016]    The present invention makes possible the optimization and re-use of hardware in the implementation of R4ACS Radix-4 Add Compare Select (RACS4) and Radix-4 Add Compare Decision (RACD) both classes of instructions for Viterbi decoders and T4MAX/T2MAX Turbo decoders using carry save arithmetic. Successful provision for these instructions requires merging the computation of summation terms and implementing an efficient method of computing. 
         [0017]    The invention solves these issues and merges the R4ACS/R4ACD instructions with a complete reuse of the hardware that is required for the implementation of T2MAX/T4MAX instructions. The hardware required by both classes of instructions is optimized by efficiently employing carry save arithmetic. 
         [0018]    The merged hardware includes a configurable three input arithmetic logic unit that can perform four arithmetic operations used by the max instructions. This invention uses 2&#39;s complement arithmetic and selective inversion to perform the four arithmetic operations a+b+c, a+b−c. a−b+c and a−b−c. These computations are used on inner terms of a max4 operation to facilitate circuit reuse in performing the operations in WiMAX radix-4 turbo decoders. A preferred embodiment employs carry-save adders in the three input arithmetic logic unit. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0019]    These and other aspects of this invention are illustrated in the drawings, in which: 
           [0020]      FIG. 1  illustrates the high-level block diagram of a Turbo decoder (Prior Art); 
           [0021]      FIG. 2  illustrates the high-level block diagram of a MAP decoder (Prior Art); 
           [0022]      FIG. 3  illustrates the basic Carry Save Adder employed (Prior Art); 
           [0023]      FIG. 4  illustrates the general approach of computing terms in Viterbi/Turbo instructions (Prior Art); 
           [0024]      FIG. 5  illustrates the optimization and reuse of hardware across Viterbi/Turbo instructions using carry-save addition according to this invention; 
           [0025]      FIG. 6  illustrates using the three input arithmetic logic unit illustrated in  FIG. 5  in forming the MAX4 function; 
           [0026]      FIG. 7  illustrates using the three input arithmetic logic unit illustrated in  FIG. 5  in forming the MINST function; and 
           [0027]      FIG. 8  illustrates an alternate embodiment to that illustrated in  FIG. 7  for forming the output z. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0028]    R4ACS/R4ACD instructions used for implementing Viterbi decoding involve the following arithmetic computation: 
         [0000]        R =max4*( a 1+ b 1+ c 1, a 2+ b 2− c 2, a 3− b 3+ c 3, a 4− b 4− c 4)  (13)
 
         [0029]    T2MAX/T4MAX Instructions used for Turbo decoders involve instructions requiring the following arithmetic computation: 
         [0000]        R =max4*( x 1+ y 1+ z 1, x 2+ y 2+ z 2, x 3+ y 3+ z 3, x 4+ y 4+ z 4)  (14)
 
         [0000]    where: each of the terms compared can be N bits wide in general. 
         [0030]    The following are the main issues in merging the two classes of instructions; merging the computation of summation terms (a2+b2−c2), (x2+y2+z2), (a3−b3+c3) and (x3+y3+z3); implementing an efficient method of computing for (a4−b4−c4); and merging this computation with (x4+y4+z4). 
         [0031]    The present invention solves both of these issues and successfully merges the two classes of instructions. Furthermore, our invention optimizes the hardware required by both classes of instructions by efficiently employing carry save arithmetic. 
         [0032]      FIG. 4  illustrates the general approach for computing terms in the different instruction classes according to the prior art. The general approach toward computing each of the N bit wide terms for the instructions is to use two N-bit wide 2&#39;s complement adders  401  and  402  by using the associative property of addition. 
         [0033]    The first term a  411  is 2&#39;s complement value and is a direct input to 2&#39;s complement adder  401  used to generate an intermediate result S  409 . The second term b  412  passes through multiplexer  403 , which generates b or the complement of b and passes the result to input  408  of adder  401 . The third term c  413  is passes through multiplexer  404  to generate c or the complement of c and passes the result to input  407  of adder  401 . Adder  402  with inputs  407  and  409  generates the final result y  410 . The signals selb  405  and selc  406  control the 2:1 multiplexers  403  and  404  respectively. The signals cin 1   414  and cin 2   415  are the carry-in values to the least significant bit positions of the respective adder circuits. By appropriately setting the values of these signals as shown in Table 1, one can generate any of the four terms required by the Viterbi instructions. 
         [0000]                                    TABLE 1               selb   selc   cin1   cin2   y                   0   0   0   0   a + b + c       0   1   0   1   a + b − c       1   0   1   0   a − b + c       1   1   1   1   a − b − c                    
These settings are based on the following simple Boolean equation for computing the 2&#39;s complement:
 
         [0000]      − x =(˜ x )+1  (15)
 
         [0000]    where: ˜x is the bit-wise complement of an N bit wide signal x; and −x is its additive inverse. 
         [0034]    However, the approach of  FIG. 4 , while conceptually simple results in unacceptable worst-case delay. The present invention illustrated in  FIG. 5  yields optimized delay results. The signals b and c are sent through multiplexer  500  controlled by selb signal  517  and multiplexer  507  controlled by selc signal  518  respectively to CSA 3:2 circuits  501  through  506 . Note CSA 3:2 circuits  501  through  506  represent the appropriate number of carry save adder circuits for the implemented data width. Signal a passes directly to the CSA 3:2 circuits  501  through  506 . These CSA 3:2 circuits generate sum  515  and carry  514  terms for each bit of the data width. These are input to the 2&#39;s complement adder  508  to generate the final result y consisting of sum output  516  and carry output  520 . The signal cin 2  is the carry input to the least significant bit (LSB) of the final 2&#39;s complement adder  508 . Table 2 shows the values of the input selb, selc, cin 1  and cin 2  use generate the four terms required by the Viterbi instructions. 
         [0000]    
       
         
               
               
               
               
               
             
           
               
                 TABLE 2 
               
               
                   
               
               
                 selb 
                 selc 
                 cin1 
                 cin2 
                 y 
               
               
                   
               
             
             
               
                 0 
                 0 
                 0 
                 0 
                 a + b + c 
               
               
                 0 
                 1 
                 0 
                 1 
                 a + b − c 
               
               
                 1 
                 0 
                 0 
                 1 
                 a − b + c 
               
               
                 1 
                 1 
                 1 
                 1 
                 a − b − c 
               
               
                   
               
             
          
         
       
     
         [0035]    The basic idea behind the generation of the first three terms in this approach is similar to the implementation in  FIG. 4 . The key difference is in the generation of the fourth term. This is achieved by rewriting the logic equation for this term as follows: 
         [0000]        a−b−c=a +((˜ b )+1)+((˜ c )+1)  (16)
 
         [0000]    The signal cin 2  can be set to provide the binary 1 that is required for generating the 2&#39;s complement of one of the inputs. The N-bit wide carry vector k generated by the 3:2 CSA circuits needs to be shifted to the left by one, prior to combining with the sum vector m, based on arithmetic weight. This leaves the carry bit from the 3:2 CSA circuit in the lowest bit position as an unused input. The signal cin 1  is used to drive this input to add in the extra binary 1 that is required to generate the 2&#39;s complement for the other input. Thus all four terms required by the Viterbi instructions can be obtained using the hardware described in  FIG. 5 . 
         [0036]    The total area consumed by the N 3:2 Carry Save circuits is typically much less than the N-bit wide adder that they replace, if one had chosen a carry-look-ahead or parallel-prefix adder which is optimized for performance. On the other hand, if one chooses an adder architecture based on chip area considerations (e.g. a ripple-carry adder), the delay through a 3:2 Carry Save circuit is much smaller in comparison. More important, this delay is constant and is independent of the width N of the operands involved, leading to even greater efficiency of this approach with regards to area and performance, as the width N of the operands increases. 
         [0037]      FIG. 6  illustrates using the three input arithmetic logic unit illustrated in either  FIG. 4  or  5  in forming the MAX4 function discussed above. Three inputs a, b and c are supplied to three input ALU  610 . As noted above the MAX4 function requires computation of a1+b1+c1, a2+b2−c2, a3−b3+c3 and a4−b4−c4. The four sets of operands (a1,b1,c1), (a2,b2,c2), (a3,b3,c3) and (a4,b4,c4) are sequentially supplied to the respective a, b and c inputs of three input ALU  610 . These four operations are controlled as noted above to achieve the desired arithmetic combinations producing four results Result 1 , Result 2 , Result 3  and Result 4  stored in respective registers of register set  620 . In a final operation the four results Result 1 , Result 2 , Result 3  and Result 4  are supplied to maximum block  630 . Maximum block  630  selects the maximum of the four results Result 1 , Result 2 , Result 3  and Result 4  for output. This is the result R of equation (14). 
         [0038]    The implementation of the MAX* computation function (such as noted above) in WiMAX CTC/3GPP radix-4 decoders is hardware intensive. Likewise, the hardware requirements in the implementation of certain low density parity check (LDPC) functions can be quite large. When designing circuits that implement both functions, it advantageous to minimize and efficiently reuse hardware in order to limit overall area and power requirements. This invention allows efficient reuse of the hardware required to implement both the MAX* and LDPC functions. Typically, the MAX* computation in the WiMAX decoders requires the following arithmetic computation: 
         [0000]    1. result_max4=max4 (a 0 +b 0 +c 0 ,a 1 +b 1 −c 1 ,a 2 −b 2 +c 2 ,a 3 −b 3 −c 3 );
 
2. correction=maxabsdiff4(a 0 +b 0 +c 0 ,a 1 +b 1 −c 1 ,a 2 −b 2 +c 2 ,a 3 −b 3 −c 3 );
 
3. if ((correction&gt;&gt;threshold)&gt;0)
       then correction=0,   else correction=value;
 
4. result=result_max4+correction;
       
 
         [0041]    The MINST implementation for LDPC functions requires the following computation: 
         [0000]    1. If x&lt;y
       then min=x,   else min=y;
 
2. If (min&lt;0)
   then min=0;
 
3. If x&lt;0
   then a=0,   else a=x;
 
4. If y&lt;0
   then b=0,   else b=y;
 
5. sum=a+b;
 
6. dif=a−b;
 
7. if ((sum&lt;threshold) AND (sum&gt;−threshold))
   then offset 1 =value,   else offset 1 =0;
 
8. if ((dif&lt;threshold) AND (dif&gt;−threshold))
   then offset 2 =value,   else offset 2 =0;
 
9. z=min+offset 1 −offset 2 ;
       
 
         [0053]    These two functions appear to be different since the nature of comparison of the threshold operands in the MINST is different from the computation of the terms in the max4 function of the MAX* function. This ordinarily implies that the hardware required to implement them cannot be shared. This invention further describes a manner for sharing hardware to implement these two functions. 
         [0054]    The invention involves the following simple transformation to the MINST computation. The MINST function can be rewritten as: 
         [0000]    1. If x&lt;y
       then min=x,   else min=y;
 
2. if (min&lt;0)
   then min=0;
 
3. If x&lt;0
   then a=0,   else a=x′
 
4. If y&lt;0
   then b=0,   else b=y;
 
5. sum=a+b;
 
6. dif=a−b;
 
7 if ((a+b−threshold&lt;0) AND (a+b+threshold&gt;0))
   then offset 1 =value,   else offset 1 =0;
 
8. if ((a−b−threshold&lt;0) AND (a−b+threshold&gt;0))
   then offset 2 =value,   else offset 2 =0;
 
9. z=min+offset 1 −offset 2 ;
 
This transforms the inner decisions in the range determinations of steps 7 and 8 into three input arithmetic operations with a compare to zero. Thus each term for the threshold comparison now resembles one of the three input arithmetic operations used in the max4 function almost exactly. The compare to zero portion of each inner decision is indicated by the three input ALU carry output  520 . Much of the hardware required to implement these two functions can now be shared. This is an important area and power saving since each of the terms involved in this computation can be N bits wide in general.
       
 
         [0066]      FIG. 7  illustrates using the three input arithmetic logic unit illustrated in either  FIG. 4  or  5  in forming the MINST function discussed above. Three inputs a, b and c are supplied to three input ALU  610 . As noted above the MINST function requires computation of a+b−threshold, a+b+threshold, a−b−threshold and a−b+threshold. The operands a, b and threshold are sequentially supplied to respective inputs of three input ALU  610 . These four operations are controlled as noted above to achieve the desired arithmetic combinations. The compare to zero desired results come from the corresponding carry output  520 . Register set  620  stores the corresponding outputs Carry 1 , Carry 2 , Carry 3  and carry 4  stored in respective registers. 
         [0067]    Circuit  730  completes the range comparisons of steps 7 and 8. AND gate  731  forms the AND function of step 7 from the Carry 1  and Carry 2  values. Multiplexer  732  completes the “If . . . then . . . else” operation of step 7 by selecting value for offset 1  if the range condition is satisfied and selecting 0 otherwise. AND gate  735  forms the AND function of step 8 from the Carry 3  and Carry 4  values. Multiplexer  736  completes the “If . . . then . . . else” operation of step 8 by selecting value for offset 2  if the range condition is satisfied and selecting 0 otherwise. 
         [0068]    The calculation of min in steps 1 and 2 is not on the critical path and thus can be done separately. Final ALU  740  performs the operation z=min+offset 1 −offset 2  of step 9. This could be preformed by a further pass through three input ALU  610  or two passes through a normal two input ALU. 
         [0069]    The final arithmetic operation (z=min+offset 1 −offset 2 ) may be further simplified. Each of offset 1  and offset 2  can individually be “0” or “value” depending upon the respective range determinations. Their difference (offset 1 −offset 2 ) is thus either be “0”, “value” or “−value”. Table 3 list these conditions. 
         [0000]                                        TABLE 3                       Ranges   offset1   offset2   z                           sum in range;   value   value   min           difference in range           sum in range;   value   0   min + value           difference out of range           sum out of range;   0   value   min − value           difference in range           sum out of range;   0   0   min           difference out of range                          FIG. 8  illustrates an alternate embodiment of this invention for forming the output z. Circuit  737  is an alternate to circuit  730 . Circuit  737  includes AND gate  731  and AND gate  735  receiving respective Carry signals from register set  620  as previously illustrated in  FIG. 7 . AND gate  731  generates a sum range output indicating whether the sum a+b is within the range of step 7. AND gate  735  generates a difference range output indicating whether the difference a−b is within the range of step 8. Table 3 logic  810  controls multiplexers  821  and  822 . One input of multiplexer  821  is “0.” A second input of multiplexer  821  is value. Depending on the signal received at the control input multiplexer  821  supplies either “0” or value to its output. The selected output of multiplexer  821  supplies an inverting input and a non-inverting input of multiplexer  822 . Table 4 lists the results of the selections of multiplexers  821  and  822  as controlled by Table 3 logic  810 .
 
         [0000]                                        TABLE 4                           Multiplexer   Multiplexer               Ranges   821 output   822 output   Carry                           sum in range;   0   0   0           difference in range           sum in range;   value     value   0           difference out of range           sum out of range;   value   ~value   1           difference in range           sum out of range;   0   0   0           difference out of range                        
Multiplexer  822  takes advantage of 2&#39;s complement arithmetic and equation (15) to execute the subtraction by inversion and injection of a carry into ALU  830 . ALU  830  performs the addition of min to form the result z.
 
         [0070]    The major advantage of this embodiment of the invention is that rearranging the inner calculations of the range decisions of steps 7 and 8 permits reuse of three input ALU  610  for performing the MINST function. 
         [0071]    Compared to other solutions to the same problem, this solution offers better performance than other solutions requiring comparable chip area. In addition, reduced chip area can be achieved when compared with other solutions offering comparable performance. The solution offers efficient performance while keeping area requirements low. These benefits are further enhanced as the size of the operands involved increases, leading to greater scalability of this approach.