Abstract:
A substrate frame includes an insulative board ( 10   a ) having a pair of ear portions ( 13 ) extending along its longitudinal edges; a plurality of wiring substrate regions ( 11 ) arranged on the insulative board ( 10   a ) between the ear portions ( 13 ) at predetermined intervals; and a plurality of slits ( 15 ) provided between the wiring substrate regions so as to extend across the ear portions ( 13 ) or a plurality grooves ( 18 ) around the wiring substrate regions ( 11 ).

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a substrate frame for connecting to external terminals the electrodes of semiconductor chips mounted on the substrate frame and a method of making semiconductor devices using the substrate frame. 
     2. Description of the Related Art 
     Japanese patent application Kokai No. 11-87386 discloses such a semiconductor device as shown in  FIGS. 2(   a ) and  2 ( b ), wherein a semiconductor chip  2  is mounted on the first surface of a wiring substrate  1  with a conductive or insulative adhesive  3 , with the circuit forming surface facing up. A plurality of pads or connecting electrodes  1   a  and their wirings (not shown) are formed on the first surface of the wiring substrate  1 . The pads  1   a  are exposed but the wirings and the other area are covered by a solder resist. A plurality of wires  4  connect the pads  1   a  and the pads  2   a  of the semiconductor chip  2 . The semiconductor chip  2 , the adhesive  3 , and the wires  4  are covered by a resin such as epoxy resin. 
     A plurality of pads and their wirings are formed on the second surface opposed to the first surface of the wiring substrate  1 . Similarly to the first surface, the pads are exposed but the wirings and the other area are covered by a solder resist. A plurality of external terminals or solder balls  6  are joined to the pads on the second surface. It is understood that the wirings on the first and second surfaces are connected via through-holes. 
     How to make such a semiconductor device will be described. 
     As shown in  FIG. 2(   c ), a substrate frame  10  is prepared by bonding a pair of copper foils on opposite surfaces of an insulating board and forming a row of wiring substrate regions  11  at predetermined intervals on each surface. On each wiring substrate, both the surfaces are etched to form wiring patterns that include pads on the first and second surfaces of a wiring substrate  1  ( FIG. 2(   a )) and through holes provided at predetermined locations for connecting the wiring patterns on the first and second surfaces. A nickel-gold (NiAu) electrolytic plating is applied to the interiors of the through holes for connecting the wiring patters and to the pads for increasing the bonding property with the wires  4  and the solder balls  6 . A solder resist is applied to the wiring patterns and the other area but the pads. 
     A plurality of slits  12  are provided between the wiring substrate regions  11  and have a length less than that of the wiring substrate regions  11 . A plurality of slits  14  are provided in the ear portions  13  of the substrate frame  10  and have a length less that that of the wiring substrate regions  11 . These slits  12  and  14  are formed by a router process. A semiconductor chip  2  is bonded to a central mounting area  11   a  of the wiring substrate region  11  with a bond  3 . Then, the pads  1   a  of the wiring substrate region  11  and the pads  2   a  of the semiconductor chip  2  are connected with wires  4 . Then, the semiconductor chip  2 , the bond  3 , and the wires  4  within a package area  11   b  are enclosed with a resinous mass  5 . A plurality of solder balls  6  are joined to the pads on the second surface of the wiring substrate region  11 . Finally, the ear portions at the four corners of the wiring substrate region  11  are punched off to provide individual semiconductor devices. 
     However, the conventional semiconductor device suffers from the following disadvantages. 
     A pair of lead patters are formed between the wiring substrate region  11  and the ear portion  13  of the substrate frame  10  for electroplating the wiring pattern. The punching at the four corners of the wiring substrate region  11  can damage the cut face, lowering the reliability. The punching may be replaced by cutting the four corners with a rotary saw. The saw cutting, however, requires cutting in the vertical and lateral directions, lowering the productivity, especially, of large BGA. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the invention to provide a substrate frame having the improved productivity. 
     According to the invention there is provided a substrate frame including an insulative board having a pair of ear portions extending along its longitudinal edges; a plurality of wiring substrate regions arranged on the insulative board between the ear portions at predetermined intervals; and a plurality of slits provided between the wiring substrate regions and extending across the ear portions or grooves around the wiring substrate regions. 
     The slits between the wiring substrate regions extend across the ear portions of the substrate frame so that the individual semiconductor devices can be separated by cutting the ear portions in only one direction or punching the grooves without any damage to the cut faces, thereby maximizing the productivity. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a plan view of a substrate frame according to the first embodiment of the invention; 
         FIG. 2(   a ) is a perspective view of a conventional semiconductor device; 
         FIG. 2(   b ) is a sectional view taken along line A—A of  FIG. 2(   a ); 
         FIG. 2(   c ) is a plan view of a substrate frame for the semiconductor device; 
         FIG. 3(   a ) is a plan view of a substrate frame according to the second embodiment of the invention; 
         FIG. 3(   b ) is a sectional view taken along line B—B of  FIG. 3(   a ). 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     First Embodiment 
     In  FIG. 1 , a substrate frame  10 A is provided to replace the substrate frame  10  in  FIG. 2(   c ). Similarly to the substrate frame  10 , this frame  10 A is made by bonding a pair of copper foils to opposite surfaces of an insulative board and forming a row of wiring substrate regions  11  at predetermined intervals on each surface. The opposite surfaces of each wiring substrate region  11  are etched to form wiring patterns that include pads  1   a  and  1   b  on the first and second surfaces of the wiring substrate  1  and through-holes provided at predetermined locations for connecting the wiring patterns on the first and second surfaces. The interiors of the through-holes are plated to connect the wiring patterns but a nickel-gold electrolytic plating is applied to the pads  1   a  and  1   b  to increase the bonding property with the wires and solder balls. A solder resist is coated on the wiring patterns and the other area except for the pads  1   a  and  1   b.    
     A plurality of slits  15  are provided between the wiring substrate regions  11  of the substrate frame  10 A and have a length greater than that of the wiring substrate regions  11 , extending across the ear portions  13  of the substrate frame  10 A. Thus, the slits  15  separate the adjacent wiring substrate regions  11 . These slits  15  are made by a router process. 
     How to make semiconductor devices with the substrate frame  10 A will be described below. 
     A plurality of semiconductor chips  2  are bonded to the central mounting areas  11   a  of wiring substrate regions  11  with a bond  3  ( FIG. 2(   a )). Then, the pads  1   a  of a wiring substrate region  11  and the pads  2   a  of a semiconductor chip  2  are connected with bonding wires  4 . Then, the semiconductor chip  2 , the bond  3 , and the wires  4  within a package area  11   b  are enclosed with a resinous mass  5 . The solder balls  6  are joined to the pads  1   b  on the second surface of the wiring substrate region  11 . Then, the ear portions  13  of the substrate frame  10 A are cut off with a rotary saw to provide individual semiconductor devices. 
     As has been described above, the wiring substrate regions  11  of the substrate frame  10 A are separated completely by the slits  15 . Thus, it is possible to provide individual semiconductor devices by cutting in only one direction without damage to the cut surface. 
     Second Embodiment 
     In  FIG. 3(   a ), a substrate frame  10 B is used to replace the substrate frame  10  of  FIG. 2(   c ). Similarly to the substrate frame  10 , this substrate frame  10 B is made by bonding a pair of copper foils to opposite surfaces of an insulative board  10   a  to form a both sided substrate and forming thereon a row of wiring substrate regions  11  at predetermined intervals. The copper foils  10   b  of the both sided substrate are etched to form wiring patterns that include pads  1   a  and  1   b  on the first and second surfaces of the wiring substrate  1  and through-holes at predetermined locations for connecting the wiring patterns on the first and second surfaces. The interiors of the through-holes are plated to connect the wiring patterns electrically. 
     Then, a solder resist  10   c  is coated over the wiring patterns and the other areas except for the pads  1   a  and  1   b , to which a nickel-gold electrolytic plating is applied to increase the bonding property with the wire and the solder balls. A plurality of slits  17  are formed between the wiring substrate regions  11  by a router process to reduce the processing stress. A groove  18  is provided around each wiring substrate region  11  by removing the copper foil  10   b  and the solder resist  10   c  in a predetermined width. 
     How to make semiconductor devices with the substrate frame  10 B will be described below. 
     (1) A both sided substrate is prepared by bonding a pair of copper foils  10   b  to opposite surfaces of an insulative board  10   a . The copper foils  10   c  on the opposite sides are etched by the photolithographic technology to form wiring patterns that include wiring substrate regions  11  provided at predetermined intervals. The wiring patterns also include pads  1   a  and  1   b , and lead patterns for. electrolytic plating. 
     (2) A plurality of through-holes are provided to connect the wiring patterns on the opposite sides of the wiring substrate  1 . A plurality of holes  16  are provided in the ear portions  13  for transportation. A solder resist  10   c  is coated to the area other than the pads  1   a  and  1   b  and the grooves  18 , and a nickel-gold electrolytic plating is applied to the pads  1   a  and  1   b.    
     (3) The area other than the groove  18  is covered with an etching mask, and the wiring patter at the groove  18  (part of the lead pattern for electrolytic plating) is removed by etching. 
     (4) The etching mask is removed, and slits  17  are formed between the wiring substrate regions  11  by the router process to complete the substrate frame  10 B. 
     (5) A semiconductor chip  2  is bonded with a bond  3  to a central mounting area  11   a  of the wiring substrate region  11 , and the pads  1   a  of the wiring substrate region  11  and the pad  2   a  of the semiconductor chip  2  are connected with wires  4 . 
     (6) The semiconductor chip  2 , the bond  3 , and the wires  4  within a package area  11   b  are enclosed with a resin  5 . Solder balls  6  are joined to the pads  1   b  on the second surface of the wiring substrate region  11 . 
     (7) The grooves  18  of the wiring substrate regions  11  are punched with a metal mold to provide individual semiconductor devices. 
     As has been described above, the substrate frame  10 B has the grooves  18  from which the wiring patterns have been removed so that individual semiconductor devices are separated without any damage to the cut surfaces merely by punching the grooves  18 . 
     The substrate frame  10 A or  10 B may be applied to a multi-layer substrate having three or more wiring layers. The wire bonding between the wiring substrate  1  and the semiconductor chip  2  may be replaced by the flip chip bonding.