Abstract:
The present invention discloses a circuit and a method for generating an internal clock signal, where the internal clock signal generation circuit includes a first delay portion for delaying an external clock signal by a first delay time, divides for dividing an output signal from the first delay portion, a first signal generator for generating a first signal with a pulse width equivalent to a skew monitor time by delaying an output signal from the divider by a second delay time and by combining the output signal from the divider with a signal delayed by the second delay time, a second signal generater for generating a second signal with a pulse width equivalent to a third delay time at a falling or rising edge of the output signal from the first delay portion, a time/digital signal converter for converting the skew monitor time equavalent to the pulse width of the first signal into first and second digital signals in response to the first signal, and a digital signal/time converter for reproducing the skew monitor time by inputting the first and the second digital signals in response to the second signal and generating the internal clock signal being delayed by a fourth delay time from the skew monitor time reproduced.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to internal clock signal generation circuits, and more particularly to a circuit and method that can produce an internal clock signal correctly in synchronization with an external clock signal. 
     2. Description of Related Art 
     When a system with a semiconductor memory device is operated at high speed, it is important to take into account a skew between a clock signal that the semiconductor memory device externally receives and data output from the semiconductor memory device, in order to correctly transfer the data output from the semiconductor memory device to an external processing device. 
     Typically, the semiconductor memory device includes an internal clock generation circuit to generate an internal clock signal in synchronization with an external clock signal, thereby minimizing the skew. The internal clock generation circuit typically includes a phase-locked loop circuit and a delay-locked loop circuit. 
     Unfortunately, the phase-locked loop circuit requires several hundred clock signals; and the delay-locked loop circuit is serially connected to a plurality of unit delay circuits comprising each of a pair of inverters, resulting in increased layout area and complexity of the circuit. 
     SUMMARY OF THE INVENTION 
     An advantage of the present invention is to provide a circuit and method that can produce an internal clock signal correctly in synchronization with an external clock signal without using a plurality of unit delay circuits, thereby simplifying the structure of the circuit. 
     To achieve this advantage of the present invention, an internal clock signal generation circuit comprises a first delay means for delaying an external clock signal by a first delay time; a divider for dividing an output signal from the first delay means; a first signal generation means for producing a first signal with a pulse width equivalent to a skew monitor time, by delaying an output signal from the divider by a second delay time (e.g., the first delay time+a third delay time+a fourth delay time) and by combining the output signal from the divider with a signal delayed by the second delay time; a second signal generation means for producing a second signal with a pulse width equivalent to the third delay time at a falling (or rising) edge of the output signal from the first delay means; a time/digital signal converter means for converting the skew monitor time equivalent to the pulse width of the first signal into a first and a second digital signals in response to the first signal; and a digital signal/time converter means for reproducing the skew monitor time by inputting the first and second digital signals in response to the second signal, and outputting an internal clock signal being delayed by the fourth delay time from the skew monitor time reproduced. 
     Furthermore, the time/digital signal converter comprises a first ring oscillator for generating in response to the first signal n number of first pulse signals, the first ring oscillator including n number of first inverting circuits serially connected; a transmitter for outputting in response to a falling (or rising) edge of the first signal the n number of the first pulse signals; a phase detector for detecting phases of the n number of the first pulse signals to produce the first digital signal; and a first counter for counting in response to a falling (or rising) edge of a n th  pulse signal of the n number of the first pulse signals to produce the second digital signal. 
     The digital signal/time converter comprises a set/reset signal generation means that produces a set signal, if the first digital signal is at an even state, and produces a reset signal, if the first digital signal is at an odd state; a second ring oscillator for generating in response to the second signal and the set signal n number of second pulse signals being oscillated with a first type, and for generating in response to the second signal and the reset signal the n number of the second pulse signals being oscillated with a second type, the second ring oscillator including n number of second inverting circuits connected in series; a select control signal generation means for producing n number of control signals to output selectively a corresponding pulse signal of the second pulse signals for the case where the first digital signal is produced by detecting rising (or falling) edges of a 1 st  pulse signal to the n th  pulse signal of the first pulse signals, and output selectively a (corresponding order+1) th  pulse signal of the second pulse signals for the case where the first digital signal is produced by detecting falling (or rising) edges of the 1 st  pulse signal to the n th  pulse signal of the first pulse signals; a selection means for selecting one pulse signal of the n number of the second pulse signals output from the second ring oscillator in response to the n number of the control signals; a second counter for counting in response to an output signal from the selection means; and a comparison means for comparing an output signal of the first counter with an output signal of the second counter, and delaying and outputting the output signal of the selection means by the fourth delay time, if the output signal of the first counter is equal to the output signal of the second counter. 
     To achieve a further advantage of the present invention, a method for generating an internal clock signal comprises generating a first clock signal by delaying an external clock signal by a first delay time; generating a second clock signal by dividing the first clock signal; generating a third clock signal by delaying the second clock signal by a second delay time (the first delay time+a third delay time+a fourth delay time), and generating a first signal with a pulse width equivalent to a skew monitor time in combination with the second clock signal and the third clock signal; generating a second signal with a pulse width equivalent to the third delay time at a falling (or rising) edge of the first clock signal; converting the skew monitor time equivalent to the pulse width of the first signal into a first and a second a digital signals in response to the first signal; and reproducing the skew monitor time by inputting the first and the second digital signals in response to the second signal, and generating the internal clock signal being delayed by the fourth delay time from the skew monitor time reproduced. 
     Preferably, the time/digital signal converting comprises generating n number of first pulse signals being oscillated in response to the first signal; outputting the n number of the first pulse signals in response to a falling (or rising) edge of the first signal; and detecting phases of the n number of the first pulse signals to produce the first digital signal, and counting in response to a falling (or rising) edge of a n th  pulse signal of the n number of the first pulse signals to produce the second digital signal. 
     Preferably, the digital signal/time converting comprises producing a set signal, if the first digital signal is at an even state, and producing a reset signal, if the first digital signal is at an odd state; outputting selectively a corresponding pulse signal of the second pulse signals for the case where the first digital signal is produced by detecting rising (falling) edges from a 1 st  pulse signal to the n th  pulse signal of the first pulse signals, and outputting selectively a (corresponding number+1) th  pulse signal of the second pulse signals for the case where the first digital signal is produced by detecting falling (or rising) edges from the 1 st  pulse signal to the n th  pulse signal of the first pulse signals; generating n number of the second pulse signals being oscillated with a first type in response to the second signal and the set signal, and generating the n number of the second pulse signals being oscillated with a second type in response to the second signal and the reset signal; selecting one pulse signal of the n number of the second pulse signals in response to n number of control signals to output a selected output signal; counting in response to the selected output signal to produce a third digital signal; and comparing the second digital signal with the third digital signal, and delaying and outputting the selected output signal by the fourth delay time, if the second digital signal is equal to the third digital signal. 
     Other aspects, features and advantages of the present invention are disclosed in the detailed description that follows. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numerals designate like elements, and in which: 
     FIG. 1 shows a block diagram of an internal clock signal generation circuit according to an embodiment of the present invention; 
     FIG. 2 shows a block diagram representing a structure of a time/digital signal converter and a digital signal/time converter of FIG. 1; 
     FIG. 3 shows a block diagram representing a structure of the time/digital signal converter and the digital signal/time converter according to the embodiment of FIG. 2; 
     FIG. 4 shows a detailed circuit diagram of a ring oscillator according to the embodiment of FIG. 2; 
     FIG. 5 shows a detailed circuit diagram of another ring oscillator according to the embodiment of FIG. 2; 
     FIGS. 6 through 11 are timing charts for explaining the operation of the internal clock signal generation circuit according to the present invention; and 
     FIG. 12 shows a block diagram of the time/digital signal converter and the digital signal/time converter of FIG. 2 according to another embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Preferred embodiments of the present invention will now be described with reference to the accompanying drawings. Like reference numerals in the drawings designate like elements. 
     As shown in FIG. 1, a block diagram of an internal clock signal generation circuit according to an embodiment of the present invention is indicated generally by the reference numeral  100 . The internal clock signal generation circuit  100  includes a first delay circuit  10 , a divider  12 , a pulse generation circuit  14  including a second delay circuit  14 - 1  and an AND gate  14 - 2 , a pulse generation circuit  16 , a time/digital signal converter  18  and a digital signal/time converter  20 . 
     The first delay circuit  10  delays an external clock signal ECLK by a first delay time d 1  to produce a clock signal RCLK. The divider  12  divides the clock signal RCLK by 2 to produce a clock signal DCLK. The second delay circuit  14 - 1  delays the clock signal DCLK by a delay time tD to produce a clock signal dCLK. The delay time tD is set to time d 1 +d 2 +d 3 . The AND gate  14 - 2  receives the clock signal DCLK and the clock signal dCLK to output a signal E 1  with the pulse width of time(tM=tC−tD, tC indicates a period of the external clock signal ECLK). The time tM indicates a skew monitor delay time. The pulse generation circuit  16  generates a negative pulse signal E 2  with the pulse width of the time d 2  at the rising edge of the clock signal RCLK. The time/digital signal converter  18  receives the signal E 1  to convert the skew monitor delay time tM into digital signals r and m. The digital signal r is a value for fine delay, and the digital signal m is a value for coarse delay. The digital signal/time converter  20  receives the signal E 2  and the digital signals r and m to convert the digital signals r and m into the skew monitor delay time tM in response to the signal E 2  and generates an internal clock signal ICLK. In other words, the digital signal/time converter  20  reproduces the skew monitor delay time tM at the rising edge of the signal E 2  using the digital signals r and m and then produces the internal clock signal ICLK being delayed by the delay time d 3  from the skew monitor delay time reproduced. 
     Turning to FIG. 2, a block diagram representing a structure of the time/digital signal converter and the digital signal/time converter of FIG. 1 is indicated generally by the reference numeral  200 . In the converter pair  200 , a time/digital signal converter  18  comprises a ring oscillator  30 , a transmitter  32 , a phase detector  34 , and a first counter  36 . The digital signal/time converter  20  comprises a ring oscillator  38 , a selector, a comparator  42 , a set/reset signal generation circuit  44 , a select control signal generation circuit  46 , and a second counter  48 . 
     In operation of the converter pair  200 , the ring oscillator  30  produces a plurality of pulse signals S 1  through Sn in response to the signal E 1 . The transmitter  32  transmits the pulse signals S 1  through Sn as signals P 1  through Pn at the falling edge of the signal E 1 . The phase detector  34  outputs 2n number of the digital signals r on phases of the signals P 1  through Pn, i.e. the phase detector  34  detects signals Pn and Pn+1 at the rising edge of the pulse signal Sn and detects inverted signals PnB and P(n+1)B at the falling edge of the pulse signal Sn. The first counter  36  counts in response to the falling edge of the pulse signal Sn to output the digital signal m. The skew monitor delay time tM is decided by the digital signal m. If a signal propagation delay time each of the inverters in the ring oscillator is tpd, the skew monitor time tM is (2 nm +r)×tpd. Also, the term 2n×tpd is a period t 0  of the signals S 1  through Sn which are produced by the ring oscillator  30 . The ring oscillator  38  is fixed to the same initial state as the signals S 1  through Sn in response to the signal E 2  of a LOW (“L”) level and a reset signal R of a HIGH (“H”) level, and generates pulse signals VS 1  through VSn toggling with the same delay time as the signals S 1  through Sn in response to the signal E 2  of the “H” level. The ring oscillator  38  also fixes the initial states of the pulse signals VS 1  through VS(n−1) at the “H” level and the initial state of the pulse signal VBn at the “L” level in response to the signal E 2  of the “L” level and a set signal S of a “H” level, and generates the pulse signals VS 1  through VSn toggling after being delayed from the initial state by time ntpd and tpd through (n−1)tpd in response to the signal E 2  of the “H” level. At this time, the ring oscillator  38  generates the pulse signals VS 1  through VSn with the same period and duty cycle as the ring oscillator  30 . The set/reset signal generation circuit  44  produces the set signal S, when the digital signal r is produced by detecting the inverted signals PnB and P(n+1)B at the falling edge of the pulse signal Sn, and produces the reset signal R, when the digital signal r is produced by detecting the signals Pn and Pn+1 at the rising edge of the pulse signal Sn. The select control signal generation circuit  46  produces control signals C 1  through Cn to output selectively the corresponding pulse signals VS 1  through VSn in case that the digital signal r is produced by detecting the rising edges of the pulse signals S 1  through Sn, and produces the control signals C 1  through Cn to output selectively the corresponding pulse signals VS 2  through VSn and VS 1  in case that the digital signal r is produced by detecting the falling edges of the pulse signals S 1  through Sn. The selector  40  selects one of the signals VS 1  through VSn in response to the control signals C 1  through Cn to output a signal SOUT. The second counter  48  counts in response to the signal SOUT to output a signal Vm. The comparator  42  compares the signal Vm with the digital signal m, and if the signal Vm is equal to the digital signal m, inputs the signal SOUT to output the internal clock signal ICLK. The comparator  42  receives the signal SOUT that is delayed by the skew monitor delay time tM in response to the signal E 2  and delays it by the delay time d 3  to generate the internal clock signal ICLK. 
     Turning now to FIG. 3, a block diagram representing a structure of the time/digital signal converter and the digital signal/time converter according to an embodiment of FIG. 2 is indicated generally by the reference numeral  300 . Here, the ring oscillator includes inverters I 1 , I 1  and I 3 . The transmitter  32  includes flip-flops F/F 1 , F/F 2  and F/F 3 . In addition, the ring oscillator  38  includes inverters I 4 , I 5  and I 6 . The selector  40  includes multiplexers MUX 1 , MUX 2  and MUX 3 . 
     In operation of the converter pair  300 , the ring oscillator  30  produces the pulse signals S 1 , S 2  and S 3  in response to the signal E 1 . At this time, the inverters I 1 , I 2  and I 3  in the oscillator  30  have same delay time each other. The first counter  36  counts in response to the falling edge of the pulse signal S 3  to produce the digital signal m. The flip flops F/F 1 , F/F 2  and F/F 3  receive the pulse signals S 1 , S 2  and S 3  in response to the falling edge of the signal E 1  to generate the signals P 1 , P 2  and P 3 , respectively. The phase detector  34  produces six digital signals r “000001”, “000010”, “000100”, “001000”, “010000”, “100000” according to the phases of the signals P 1 , P 2  and P 3 . In other words, when the phase of the signals P 1 , P 2  and P 3  input to the phase detector  34  are “H” level, “H” level, and “L” level, respectively, the digital signal r is “000001. When the phases of the signals P 1 , P 2  and P 3  are “H” level, “L” level and “L” level, the digital signal r is “000010”. When the phases of the signals are “H” level, “L” level and “H” level, the digital signal r is “000100”. When the phases of the signals are “L” level, “L” level and “H” level, the digital signal r is “001000”. When the phases of the signals are “L” level, “H” level and “H” level, the digital signal r is “010000” and when the phases of the signals are “L” level, “H” level and “L” level, the digital signal r is “100000”. At this time, the produced digital signal r is irrespective of a 3-bit signal representing six different kinds of signals. The ring oscillator  38  generates the pulse signals VS 1 , VS 2  and VS 3  in response to the signal E 2 . At this time, the inverters I 4 , I 5  and I 6  in the ring oscillator  38  have the same delay time as the inverters I 1 , I 2  and I 3  in the ring oscillator  30 . The set/reset generation circuit  44  generates the set signal S, when the digital signal r is “000010”, “001000”, “100000”, and generates the reset signal R, when the digital signal r is “000001”, “000100”, “010000”. The select control signal generation circuit  46  generates the control signal C 1 , when the digital r is “100000”, “000001”, generates the control signal C 3 , when the digital signal r is “000010”, “000100”, and generates the control signal C 2 , when the digital signal r is “001000”, “010000”. The multiplexers MUX 1 , MUX 2  and MUX 3  output a signal SOUT by selecting one of the signals VS 1 , VS 2  and VS 3  in response to the control signals C 1 , C 2  and C 3 . The second counter  48  counts in response to the signal SOUT to output the signal Vm. The comparator  42  compares the signal Vm with the signal m, and if the signal Vm is equal to the signal m, receives the signal SOUT to produce the internal clock signal ICLK. 
     As shown in FIG. 4, a detailed circuit of the ring oscillator  30  according to an embodiment of FIG. 2 is indicated generally by the reference numeral  400 . The ring oscillator  400  includes an inverter I 1  including an inverter I 7 , PMOS transistors P 1 , P 2  and P 3  and NMOS transistors N 1 , N 2  and N 3 , an inverter I 2  including PMOS transistors P 4 , P 5  and P 6  and NMOS transistors N 4 , N 5  and N 6 , and an inverter I 3  including PMOS transistors P 7 , P 8  and P 9  and NMOS transistors N 7 , N 8  and N 9 . 
     The operation for each of the blocks of the oscillator  400  will now be described in detail. When the signal E 1  of the “L” level is input to the inverter I 7 , the invert I 7  generates a signal E 1 B of the “H” level. Accordingly, the PMOS transistors P 1  and P 4  and NMOS transistors N 2  and N 5  are OFF, and the NMOS transistor N 3  and PMOS transistor P 6  are ON. The inverter I 1  generates the signal S 1  of the “L” level, and the inverter I 2  generates the signal S 2  of the “H” level. And, the inverter I 3  inverts the signal S 2  of the “H” level to output the signal S 3  of the “L” level. In other words, when the signal E 1  of the “L” level is input to the inverter I 7 , the signals S 1 , S 2  and S 3  are fixed to the “L” level, the “H” level, and the “L” level, respectively. 
     When the signal E 1  of the H level is input to the inverter I 7 , the inverter I 7  produces the signal E 1 B of the “L” level. Accordingly, the PMOS transistors P 1  and P 4  and NMOS transistors N 2  and N 5  are ON, and the NMOS transistor N 3  and PMOS transistor P 6  are OFF. Thus, the operation of the inverters I 1  and I 2  will be enabled. So, the inverter I 1  inverts and delays the signal S 3  to output the signal S 1  and the inverter I 2  inverts and delays the signal S 1  to output the signal S 2 , and the inverter I 3  inverts and delays the signal S 2  to output the signal S 3 . Accordingly, when the delay time each of the inverters I 1 , I 2  and I 3  is equal to the time td, if the signal E 1  of the H level is provided, the inverters I 1 , I 2  and I 3  produce the pulse signals S 1 , S 2  and S 3  with the duty cycle of 50% and the period of 6td. The pulse signals S 1 , S 2 , S 3  are individually the signals toggling in order with the delay time td from the rising edge of the signal E 1 . 
     Turning to FIG. 5, a detailed circuit of a ring oscillator  38  according to the embodiment of FIG. 2, constituted of the same elements as those of the ring oscillator  400  of FIG. 4, is indicated generally by the reference numeral  500 . The ring oscillator  500  differs from the ring oscillator  400  in that an inverted set signal SB is input to a gate of the PMOS transistor P 3  and the reset signal R is input to a gate of the NMOS transistor N 3  in the ring oscillator  38 . 
     In operation of the circuit  500 , when the signal E 2  of the L level is input to an inverter I 8 , the inverter I 8  produces a signal E 2 B of the “H” level. Accordingly, the PMOS transistors P 1  and P 4  and NMOS transistors N 2  and N 5  are OFF, and the PMOS transistor P 6  is ON. At this time, if the inverted set signal SB and the reset signal R are at the “H” level, the PMOS transistor P 3  is OFF and the NMOS transistor N 3  is ON, thereby producing the signal VS 1  of the “L” level. Also, the PMOS transistor P 6  is ON to produce the signal VS 2  of the “H” level. The inverter I 6  inverts and delays the signal VS 2  of the “H” level to produce the signal VS 3  of the “L” level. In other words, the signals VS 1 , VS 2  and VS 3  are individually fixed to the “L” level, “H” level and “L” level. On the contrary, if the inverted set signal SB and the reset signal R are at the “L” level, the signals VS 1 , VS 2  and VS 3  are individually fixed to the “H” level, the “H” level and the “L” level. 
     When the signals VS 1 , VS 2  and VS 3  are individually fixed to the “L” level, the “H” level and the “L” level, if the signal E 2  is driven to an “H” level and the inverted set signal of the “H” level and the rest signal R of the “L” level are produced, the PMOS transistors P 1  and P 4  and the NMOS transistors N 2  and N 5  are ON and the PMOS transistors P 3  and P 6  and the NMOS transistors N 3  are OFF. The inverter I 4  inverts and delays the signal VS 3  to generate the signal VS 1 , the inverter I 5  inverts and delays the signal VS 1  to generate the signal VS 2 , and the inverter I 6  inverts and delays the signal VS 2  to generate the signal VS 3 . Accordingly, when the delay time each of the inverters I 4 , I 5  and I 6  is equal to the time td, if the signal E 2  of the “H” level is provided, the inverters I 4 , I 5  and I 6  produce the pulse signals VS 1 , VS 2  and VS 3  with the duty cycle of 50% and the period of  6 td. The pulse signals VS 1 , VS 2  and VS 3  are the signals toggling in order with the delay time td, after the signal E 2  is driven to the “H” level. 
     Conversely, when the signals VS 1 , VS 2  and VS 3  are individually fixed to the “H” level, the “H” level and the “L” level, if the signal E 2  is driven to the “H” level, and if the inverted set signal SB of the “”H” level and the reset signal R of the “L” level is produced, the inverter I 4  inverts and delays the signal VS 3  to produce the signal VS 1 , the inverter I 5  inverts and delays the signal VS 1  to produce the signal VS 2 , and the inverter I 6  inverts and delays the signal VS 2  to produce the signal VS 3 . Accordingly, when the delay time each of the inverters I 4 , I 5  and I 6  is equal to the time td, if the signal E 2  of the “H” level is provided, the inverters I 4 , I 5  and I 6  produce the pulse signals VS 2 , VS 3 , and VS 1  with the duty cycle of 50% and the period of  6 td. At this time, the pulse signals VS 1 , VS 2  and VS 3  are the signals toggling in order with the delay time  3 td, after the signal E 2  is driven to the “H” level. 
     FIGS. 6 through 11 show timing charts for explaining the operation of the internal clock signal generation circuit according to embodiments of the present invention, indicated generally by the reference numerals  600 ,  700 ,  800 ,  900 ,  1000  and  1100 , respectively. 
     Referring back to FIG.  1  and FIG. 3, operation of the circuits  100  and  300  will now be described with respect to the timing charts. 
     As shown in FIG. 6, the operation of the internal clock signal generation circuit according to the present invention will be described with reference to the timing chart  600 . 
     The first delay circuit  10  delays the external clock signal ECLK by the first delay time d 1 . The divider  12  divides the signal RCLK by 2 to produce the signal DCLK. The second delay circuit  14  delays the signal DCLK by the second delay time (tD=d 1 +d 2 +d 3 ). An AND gate  14 - 2  receives the signal DCLK and the signal dCLK to produce the signal E 1  with the pulse width of the skew monitor delay time (tM=tC−tD, where tC indicates a period of the external clock signal ECLK). The pulse generation circuit  10  generates the negative pulse signal E 2  with the pulse width of the time d 2  at the rising edge of the signal RCLK. The ring oscillator  30  generates the pulse signals S 1 , S 2  and S 3  toggling in the response to the signal E 1  of the “H” level. The flip-flops F/F 1 , F/F 2  and F/F 3  transmit the signals S 1 , S 2  and S 3  of the “L” level, the “H” level and the “L” level at the falling edge of the signal E 1 . The phase detector  34  outputs the digital signal r of “100000”. The first counter  36  counts in response to the falling edge of the pulse signal S 3  to produce the digital signal m of “10”. At this time, the produced digital signals r and m are the digital values for the skew monitor delay time tM. The set/reset signal generation circuit  44  generates the reset signal R and the inverted set signal SB maintaining the “L” level during the time period of the signal E 2  of the “L” level, if the digital signal r of “100000” is input to the circuit  44 . The select control signal generation circuit  46  inputs the digital signal r of “100000” to generate the control signal C 1  of the “H” level and the control signals C 2  and C 3  of the “L” level. The ring oscillator  38  generates the pulse signals VS 1 , VS 2  and VS 3  toggling in response to the signal E 2  of the “H” level. At this time, the produced pulse signals VS 1 , VS 2  and VS 3  are respectively fixed to the “H” level, the “H” level and the “L” level in response to the signal E 2  of the “L” level and the inverted signal SB of the “L” level, and are toggling after being delayed by the times 3tpd, tpd and 2tpd from the rising edge of the signal E 2  in response to the signal E 2  of the “H” level and the inverted signal SB of the “H” level. The multiplexer MUX 1  inputs the pulse signal VS 1  to produce the signal SOUT in response to the control signal C 1 . The second counter  48  counts in response to the rising edge of the signal SOUT. The comparator  42  compares an output signal of the first counter with an output signal of the second counter  48 , and if the output signal of the first counter  36  is equal to the output signal of the second counter  48 , produces the signal SOUT as the internal output signal ICLK. At this time, the comparator  42  delays the signal SOUT by the delay time d 3  to produce the internal clock signal ICLK. Accordingly, the internal clock generation circuit can produce the internal clock signal ICLK correctly in synchronization with the external clock signal ECLK. 
     Turning to FIG. 7, operation of the circuits  100  and  300  of FIGS. 1 and 3, respectively, will now be described with respect to the timing chart  700 , which shows a case where the skew monitor time tM is greater than the skew monitor time tM of FIG.  6 . 
     In this case, the time/digital signal converter  18  operates to generate the digital signal r of “000001” and the digital signal m of “10” at the falling edge of the signal E 1 . The set/reset signal generation circuit  44  inputs the digital signal r of “000001” to generate the inverted set signal SB of the “L” level and the reset signal R of the “L” level. The ring oscillator  38  generates the pulse signals VS 1 , VS 2  and VS 3  toggling in the response to the signal E 2  of the “H” level. At this time, the generated pulse signals VS 1 , VS 2  and VS 3  are respectively fixed to the “L” level, the “H” level and the “L” level in response to the signal E 2  of the “L” level and the reset signal R of the “H” level, and are toggling after being delayed by each of the times tpd, 2tpd and 30tpd from the rising edge of the signal E 2  in response to the signal E 2  of the “H” level and the reset signal R of the “L” level. The select control signal generation circuit  46  inputs the digital signal r of “000001” to generate the control signal C 1  of the “H” level and the control signals C 2  and C 3  of the “L” level. Accordingly, the multiplexer MUX 1  inputs the pulse signal VS 1  to produce the signal SOUT in response to the control signal C 1 . The second counter  48  counts in response to the rising edge of the signal SOUT. The comparator  42  compares the digital signal m with the signal Vm, and if the digital signal m is equal to the signal Vm, delays the signal SOUT by the delay time d 3  to produce the internal clock signal ICLK. 
     Turning now to FIG. 8, operation of the circuits  100  and  300  of FIGS. 1 and 3, respectively, will now be described with respect to the timing chart  800 , which shows a case where the skew monitor time tM is greater than the skew monitor time tM of the timing chart of FIG.  7 . 
     In this case, the time/digital signal converter  18  generates the digital signal r of “000010” and the digital signal m of “10”. The ring oscillator  38  generates the pulse signals VS 1 , VS 2  and VS 3  toggling in the response to the signal E 2  of the “L” level and the inverted set signal SB of the “L” level. At this time, the generated pulse signals VS 1 , VS 2  and VS 3  have the same toggling as the pulse signals VS 1 , VS 2  and VS 3  of the timing chart of FIG.  6 . The select control signal generation circuit  46  inputs the digital signal r of “000010” to generate the control signal C 3  of the “H” level and the control signals C 1  and C 2  of the “L” level. Accordingly, the multiplexer MUX 3  inputs the pulse signal VS 3  to produce the signal SOUT in response to the control signal C 3 . The second counter  48  counts in response to the signal SOUT. The comparator  42  compares the digital signal m with the signal Vm, and if the digital signal m is equal to the signal Vm, delays the signal SOUT by the delay time d 3  to produce the internal clock signal ICLK. Accordingly, the internal clock generation circuit can produce the internal clock signal ICLK correctly in synchronization with the external clock signal ECLK. 
     Turning now to FIGS. 9 through 11, a detailed explanation of the timing charts  900 ,  1000  and  1100  is omitted due to the similarity to the description already provided. Thus, the operation in these cases will be understood and appreciated by those of ordinary skill in the pertinent art by referring to the explanation for the timing charts  600 ,  700  and  800  of FIGS.  6  through FIG. 8, respectively. 
     As described above, the internal clock generation circuit shown for the circuit  300  of FIG. 3 has a construction such that the time/digital signal converter  18  and the digital signal/time converter  20  include the counter and the ring oscillator having three inverters, respectively. 
     As shown in FIG. 12, a block diagram of the time/digital signal converter and the digital signal/time converter according to another embodiment of FIG. 2 is indicated generally by the reference numeral  1200 . 
     In the converter circuit  1200 , the ring oscillator  30  includes inverters I 9  through I 13 , the transmitter  32  includes flip-flops F/F 1  through F/F 5 , the ring oscillator  38  includes inverters I 14  through I 18 , and the selector  40  includes multiplexers MUX 1  through MUX 5 . In operation, The ring oscillator  30  produces pulse signals S 1  through S 5  in response to the signal E 1 . At this time, the inverters I 9  through I 13  in the ring oscillator  30  have the same delay time. The counter  36  counts in response to the falling edge of the pulse signal S 3  to produce the digital signal m. The flip-flops F/F 1  through F/F 5  input the pulse signals S 1  through S 5  to generate signals P 1  through P 5  at the falling edge in the signal E 1 , respectively. The phase detector  34  generates ten digital signals r, “0000000001”, “0000000010” . . . , “1000000000” according to the phases of the signals P 1  through P 5 . In other words, if the phases of the signals P 1  through P 5  input to the phase detector  34  is “H” level, “H” level, “L” level, “H” level and “L” level, the phase detector  34  generates the digital signal r of “0000000001”. If the phases of the signals P 1  through P 5  input to the phase detector  34  is “H” level, “L” level, “L” level, “H” level and “L” level, the phase detector  34  generates the digital signal r of “0000000010”. If the phases of the signals P 1  through P 5  input to the phase detector  34  is “L” level, “H” level, “L” level, “H” level and “L” level, the phase detector  34  generates the digital signal r of “1000000000”. The ring oscillator  38  generates the pulse signals VS 1 , VS 2 , VS 3 , VS 4  and VS 5  in response to the signal E 2 . At this time, the inverters I 14  through I 18  in the ring oscillator  38  have the same delay time as the inverters ( 9  through I 13  in the ring oscillator  30 . The set/reset signal generation circuit  44  generates a set signal S, if the even bit signal of the digital signal r is “1”, and generates a reset signal R, if the odd bit signal of the digital signal r is “1”. The select control signal generation circuit  46  generates the control signal C 1 , if the 1 st  bit signal and the 10 th  bit signal of the digital signal r are “1”, generates the control signal C 3 , if the 2 nd  bit signal and the 3 rd  bit signal of the digital signals r are “1”, generates the control signal C 5 , if the 4 th  bit signal and the 5 th  bit signal of the digital signal r are “1”, generates the control signal C 2 , if the 6 th  bit signal and the 7 th  bit signal of the digital signal r are “1”, and generates the control signal C 4 , if the 8 th  bit signal and the 9 th  bit signal of the digital signal r are “1”. The multiplexers MUX 1  through MUX 5  select one of the signals VS 1 , VS 2 , VS 3 , VS 4  and VS 5  in response to the control signals C 1  through C 5  to generate the output signal SOUT. The second counter  48  counts in response to the signal SOUT to output the signal Vm. The comparator  42  compares the digital signal m with the signal Vm, and if the digital signal m is equal to the signal Vm, delays the signal SOUT by the delay time d 3  to produce the internal clock signal ICLK. 
     The timing chart of the internal clock signal generation circuit in FIG. 12 is not shown. But, using the same method as indicated for the timing charts of FIGS.  6  through FIG. 11, the internal clock signal generation circuit can produce the internal clock signal ICLK correctly in synchronization with the external clock signal ICLK. 
     As described above, the internal clock generation circuit according to the embodiment of the present invention shown in the circuit  1200  has a construction such that the time/digital signal converter  18  and the digital signal/time converter  20  include the counter and the ring oscillator having five inverters, respectively. In other words, the internal clock generation circuit does not include a plurality of unit delay circuit each having two inverters connected in series, but can produce the internal clock signal correctly in synchronization with the external clock signal with the construction of the circuit as shown. 
     Correspondingly, the ring oscillator in the internal clock signal generation circuit of FIG. 12 comprises two more inverters in comparison with the ring oscillator of FIG. 3, but may simply configure the counter, because the value of the digital signal m becomes small in case that the skew monitor time is set to the same. 
     According to the present invention, the internal clock signal generation circuit is constructed by the counter and the ring oscillator having relatively few inverters, thereby simplifying the structure of the circuit and reducing the layout dimensions. 
     Further, the internal clock signal generation circuit of the present invention is configured to produce the internal clock signal correctly in synchronization with the external clock signal with a simplified circuit structure. 
     While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those of ordinary skill in the pertinent art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention, as set forth in the appended claims.