Abstract:
The present invention relates to a non-volatile memory device on a substrate layer comprising semiconductor source and drain regions, a semiconductor channel region, a charge storage stack and a control gate; the channel region being fin-shaped having two sidewall portions and a top portion, and extending between the source region and the drain region; the charge storage stack being positioned between the source and drain regions and extending over the fin-shaped channel, substantially perpendicularly to the length direction of the fin-shaped channel; the control gate being in contact with the charge storage stack, wherein—an access gate is provided adjacent to one sidewall portion and separated therefrom by an intermediate gate oxide layer, and—the charge storage stack contacts the fin-shaped channel on the other sidewall portion and is separated from the channel by the intermediate gate oxide layer.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to a double gate non-volatile memory device. 
         [0002]    Also, the present invention relates to a method of manufacturing such a memory device. 
       BACKGROUND OF THE INVENTION 
       [0003]    For reasons of scaling, the use of planar MOSFET structures in device generations with a 65 nm design rule and smaller is becoming more and more complicated due to so-called short channel effects. 
         [0004]    An improvement of device characteristics can be obtained by application of a finFET structure. In a finFET, on top of an insulating layer a (relatively narrow) silicon line (a fin) is created between a source region and a drain region to serve as a channel. Next, a line-shaped control gate is created which crosses the fin. The control gate, which is separated from the fin by a thin gate oxide film surrounds (in cross-section) both the sidewalls and the top of the fin, which allows for a relatively large field effect by the gate on the fin channel. 
         [0005]    For Flash memory, an application of a finFET structure as described above has been disclosed in U.S. Pat. No. 6,768,158. Between the control gate and the fin material a charge trapping layer stack is positioned. Here, the charge trapping stack layers follow the profile of the fin along both the sidewalls and the top of the fin. The control gate layer follows the profile of the charge trapping stack layers. The charge trapping layer stack comprises either a poly-silicon floating gate or a layer stack of silicon dioxide-silicon nitride-silicon dioxide for trapping charge. Under the control of the control gate, carriers can be transported from the channel to the charge trapping layer to write (or program) data in the Flash memory cell. The mechanism for such a transport of charge depends on the type of charge trapping layer stack: for a poly-silicon floating gate transport takes place by hot carrier injection or by direct tunneling, for a silicon nitride layer by direct tunneling of carriers. 
         [0006]    Also, a mechanism for a reversed action to erase the data (charge) from the charge trapping layer is available. Further, a sensing or reading action is available which is used for detecting whether charge is stored in the charge trapping layer. The structure of the non-volatile memory element as disclosed has the disadvantage that data retention, i.e., retention of charge, in the charge trapping layer stack is adversely affected by the above-mentioned method of sensing the charge (reading the stored data). In the finFET of U.S. Pat. No. 6,768,158, sensing the charge is done by the same control gate that is used for storing charge. By comparison with a threshold voltage it can be determined what data is stored (e.g., a bit value 0 or 1). Disadvantageously, this sensing action involves biasing of the control gate, which stimulates stored charge to leak away from the charge trapping layer. 
       SUMMARY OF THE INVENTION 
       [0007]    It is an object of the present invention to provide a double gate non-volatile memory device in which data retention due to sensing is strongly reduced. 
         [0008]    The present invention relates to a non-volatile memory device on a substrate layer comprising semiconductor source and drain regions, a semiconductor channel region, a charge storage stack and a control gate; 
         [0009]    the channel region being fin-shaped having two sidewall portions and a top portion, and extending between the source region and the drain region; 
         [0010]    the charge storage stack being positioned between the source and drain regions and extending over the fin-shaped channel, substantially perpendicularly to the length direction of the fin-shaped channel; 
         [0011]    the control gate being in contact with the charge storage stack, wherein 
         [0012]    an access gate is provided adjacent to one sidewall portion and is separated therefrom by an intermediate gate oxide layer, and 
         [0013]    the charge storage stack contacts the fin-shaped channel on the other sidewall portion and is separated from the channel by the intermediate gate oxide layer. 
         [0014]    Advantageously, by providing an access gate on one side of the fin and a control gate on the other side, the sensing functionality can be separated from the programming functionality. The exposure of the charge trapping layer to the biasing voltage during sensing is thus removed, which enhances the data retention significantly. 
         [0015]    The present invention relates to a method of manufacturing a non-volatile memory device on a substrate layer; the method comprising: 
         [0016]    forming semiconductor source and drain regions; 
         [0017]    forming a semiconductor channel region, the channel region being fin-shaped having two sidewall portions and a top portion, and extending between the source region and the drain region; 
         [0018]    forming a gate oxide layer covering the sidewalls and the top portion of the fin; 
         [0019]    forming a charge storage stack, the charge storage stack being positioned between the source and drain regions and extending over the fin-shaped channel, substantially perpendicularly to the length direction of the fin-shaped channel, and 
         [0020]    forming a control gate, the control gate being in contact with the charge storage stack, wherein the method further comprises 
         [0021]    forming an access gate adjacent to one sidewall portion and separated from the channel by an intermediate gate oxide layer, and 
         [0022]    forming the charge storage stack adjacent to the other sidewall portion for contacting the fin-shaped channel on the other sidewall portion, said charge storage stack being separated from the channel by the intermediate gate oxide layer. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0023]    For the purpose of teaching of the invention, preferred embodiments of the devices and method of the invention are described below. It will be appreciated by the person skilled in the art that other alternative and equivalent embodiments of the invention can be conceived and reduced to practice without departing from the true spirit of the invention, the scope of the invention being limited only by the appended claims. 
           [0024]      FIG. 1  shows a layout of a finFET structure in a perspective view; 
           [0025]      FIG. 2  shows a first cross-sectional view of the finFET structure of  FIG. 1 ; 
           [0026]      FIG. 3  shows a schematic cross-sectional view of a finFET structure according to the present invention; 
           [0027]      FIG. 4  shows a schematic cross-sectional view of a finFET structure according to the present invention; 
           [0028]      FIG. 5  shows a schematic cross-sectional view of a first embodiment of a finFET structure according to the present invention, and 
           [0029]      FIG. 6  shows a schematic cross-sectional view of a second embodiment of a finFET structure according to the present invention. 
       
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
       [0030]      FIG. 1  shows a layout of a finFET structure in a perspective view. 
         [0031]    A finFET structure  1  is located on an insulating layer  2 , for example a silicon dioxide layer or a BOX (Buried Oxide) layer of a SOI wafer (SOI: silicon on insulator). 
         [0032]    The finFET structure  1  comprises source and drain regions  3  and a (relatively narrow) line or fin  4  which is located between the source and drain regions and interconnects them. Source, drain and fin regions  3 ,  4  consist of silicon semiconductor material. The fin region  4  has a substantially rectangular cross-section with two sidewall portions  4   a ,  4   b  and a top portion  4   c . Source, drain and fin regions  3 ,  4  are defined and created by lithographic processing technology. 
         [0033]    Typically, the height of the fin  4  is between 30 and 100 nm, the width of the fin  4  is typically equal to or less than its height. The length of the fin  4  is typically 70-100 nm. 
         [0034]    A gate  5  is positioned on the insulating layer  2  between the source and drain regions  3  and extends over the fin  4  along the Y direction, substantially perpendicularly to the length direction X of the fin  4 . The gate  5  is separated from the fin  4  by a gate oxide layer (not shown). 
         [0035]    The gate  5  can be created by a deposition process after which a suitable pattern is defined by lithography in which a suitable mask is defined by lithography. 
         [0036]    In this example the gate  5  is shown as a thin line-shaped layer, but it may appear as plate-shaped, depending on its height (direction Z) in comparison to the height of the fin  4 . 
         [0037]    The gate material can be any suitable material: a doped semiconductor (such as poly-silicon) or a metal. 
         [0038]      FIG. 2  shows a cross-sectional view of the finFET structure of  FIG. 1 . The cross-section is taken along the length direction X of the fin  4 . Entities with the same reference number refer to identical entities as shown in the preceding Figure. 
         [0039]      FIG. 3  shows a schematic cross-sectional view of a finFET structure according to the present invention. The cross-section shows the fin  4  on top of the insulating layer  2 . The gate  5  covers, by means of its vertical parts  5   a ,  5   b , the sidewall portions  4   a ,  4   b  of the fin  4  and, by means of its horizontal top part  5   c , the top portion  4   c  of the fin  4 . 
         [0040]    As described above with reference to  FIG. 1 , the gate  5  is separated from the fin  4  by a gate oxide layer  6 . The gate oxide layer covers the sidewalls  4   a ,  4   b  of the fin  4  and top gate portion  6   c  covers the top  4   c  of the fin  4 . The gate oxide layer  6  can be formed by a suitable oxide growth process or by a deposition process to form a high-K material layer acting as gate isolation layer  6 . 
         [0041]      FIG. 4  shows a schematic cross-sectional view of a finFET structure according to the present invention. 
         [0042]    In a next step to form the finFET structure according to the present invention, the horizontal top part  5   c  of the gate  5  is removed by a chemical-mechanical polishing (CMP) process or an etch-back process. 
         [0043]    The finFET structure now comprises a dual gate structure with a first vertical gate  5   a  and a second vertical gate  5   b.    
         [0044]    As will be explained below, during the removal of the top part  5   c  of the gate  5 , the top gate part  6   c  of the gate oxide layer  6  is typically also removed, but may be preserved, if necessary. 
         [0045]      FIG. 5  shows a schematic cross-sectional view of a first embodiment of a finFET structure according to the present invention. 
         [0046]    In a further step, one of the vertical gates  5   a ,  5   b  is removed, for example the second vertical gate  5   b.    
         [0047]    First, a suitable first mask is defined on top of the finFET structure to cover the top of the fin  4  and the vertical gate  5   a  that is to remain. If required, a thin oxide layer (not shown) may be provided on the top region of the fin  4  before applying the first mask. 
         [0048]    Subsequently, the second vertical gate  5   b  not covered by the first mask and the gate oxide layer  6  on the sidewall  4   b  of the fin  4  adjacent to the second vertical gate  5   b  are removed by a dry or wet etching process. After this step a first dielectric layer  7  is formed on the exposed sidewall  4   b  of the fin  4  by a process for selective growth of silicon dioxide. 
         [0049]    Then, a first layer of poly-silicon is deposited in a blanket mode. By etch-back (dry etching) of the poly-silicon layer, a spacer  8  of poly-silicon is formed which is adjacent to fin  4  (but separated from it by the first dielectric  7 ). 
         [0050]    Then, a second dielectric layer  9  is deposited in blanket mode. Again, by etch-back (dry etching) of the second dielectric layer, a spacer  9  of second dielectric material is formed which is adjacent to the poly-silicon spacer  8 . 
         [0051]    Preferably, the first dielectric layer, the first layer of poly-Si and the second dielectric layer are deposited and patterned while the first mask to cover the top of the fin  4  and the vertical gate  5   a , is still present. 
         [0052]    Finally, a control gate layer  10  is deposited (in blanket mode). Again, the gate material can be any suitable material: a doped semiconductor or a metal. 
         [0053]    A second mask is defined to remove the control gate  10  above the finFET structure. By etching, the control gate  10  is defined. The control gate  10  is now adjacent to the second dielectric spacer  9 . If still present, the mask to cover the top of the fin  4  and the vertical gate  5   a , can be simultaneously removed using the second mask. 
         [0054]    Thus, a finFET structure with an access gate  5   a , a channel  4 , a floating gate stack  7 ,  8 ,  9  and a control gate  10  is formed. The floating gate stack  7 ,  8 ,  9  comprises a set of layers which are parallel to the plane of the sidewall  4   b , the set of layers being the first dielectric  7 , the poly-silicon charge storage layer  8  and the second dielectric  9 . 
         [0055]    The first dielectric  7  is positioned directly adjacent to the sidewall  4   b  of the fin  4 . Next, the poly-silicon charge storage layer  8  is positioned adjacent to the first dielectric  7 . Finally, the second dielectric  9  is positioned adjacent to the charge storage layer  8 . 
         [0056]    Typically, in the first embodiment the height of the finFET structure is about equal to, or somewhat less than, the thickness of the silicon top layer of the SOI wafer, i.e. between about 30 and about 150 nm. The access gate  5   a  typically has a thickness of about 50 nm (on the sidewall). The gate oxide layer  6  has a thickness of a few nm, say between 1 and 8 nm. The width of the fin (channel)  4  is between about 10 and about 50 nm. The thickness of the first dielectric  7  is between about 4 and about 10 nm. The thickness of the floating gate  8  is about 50 nm or higher. The thickness of the second dielectric  9  is between about 10 and about 20 nm. Finally, the thickness of the control gate (on the sidewall) is about 50 nm or higher. 
         [0057]      FIG. 6  shows a schematic cross-sectional view of a second embodiment of a finFET structure according to the present invention. 
         [0058]    In the second embodiment the finFET comprises an ONO charge trapping stack of a first silicon dioxide layer, a silicon nitride layer and a second silicon dioxide layer. 
         [0059]    The ONO charge trapping stack is formed in a similar way as the floating gate stack of the first embodiment. The floating gate  8  is replaced by a silicon nitride spacer  11  by depositing a silicon nitride layer in blanket mode and subsequently an etch-back to form the spacer shape. 
         [0060]    Then, a third dielectric layer is deposited in blanket mode. Again, by dry etching of the third dielectric layer, a spacer  12  of dielectric material is formed which is adjacent to the poly-silicon spacer  11 . As described below, the thickness of the third dielectric  12  in the second embodiment will typically be less than that of the third dielectric in the first embodiment. 
         [0061]    Preferably, the second dielectric, the silicon nitride layer and the second dielectric layer are deposited and patterned while the first mask to cover the top of the fin  4  and the vertical gate  5   a , is still present. 
         [0062]    Next, a control gate layer  13  is formed in a similar way as the control gate  10  of the first embodiment. Again, the gate material can be any suitable material: a doped semiconductor or a metal. 
         [0063]    All other steps to form the finFET structure according to the second embodiment are similar to the steps discussed with reference to  FIG. 5 . 
         [0064]    Thus, a finFET structure with an access gate  5   a , a channel  4 , an ONO charge trapping stack  7 ,  11 ,  12  and a control gate  13  is formed. The ONO charge trapping stack comprises a set of layers which are parallel to the plane of the sidewall  4   b , the set of layers being the first dielectric layer  7 , the silicon nitride layer  11  for charge storage and the second gate dielectric  12 . 
         [0065]    The first dielectric  7  is positioned directly adjacent to the sidewall  4   b  of the fin  4 . Next, the silicon nitride layer  11  is positioned adjacent to the first dielectric  7 . Finally, the second dielectric  12  is positioned adjacent to the silicon nitride layer  11 . 
         [0066]    Typically, in the second embodiment the height of the finFET structure is about equal to, or somewhat less than, the thickness of the silicon top layer of the SOI wafer, say between about 30 and about 150 nm. The access gate  5   a  typically has a thickness of at least 60 nm (on the sidewall). The gate oxide layer  6  has a thickness of a few nm, say between 1 and 8 nm. The width of the fin (channel)  4  is between about 10 and about 50 nm. The thickness of the second gate dielectric  7  is about 2 nm. The thickness of the silicon nitride  11  is about 4 to 7 nm. The thickness of the second dielectric  9  is between about 4 and about 10 nm. Finally, the thickness of the control gate is about 60 nm or more (on the sidewall). 
         [0067]    It is noted that, as shown in  FIG. 4 , during the removal of the top part  5   c  of the gate  5 , the top part of the gate oxide layer  6  is typically also removed, but, if necessary (for example, for reasons relating to processing), the top part of the gate oxide layer  6  may be preserved. In the case of a non-volatile memory device which comprises an ONO charge trapping stack, the top gate part  6   c  of the gate oxide layer  6  is preferably removed to avoid formation of the ONO stack on the top part  4   c  of the fin  4 . In the case of a non-volatile memory device comprising a floating gate, i.e. the first embodiment, the top gate part  6   c  may remain on top of the fin  4 .