Abstract:
A semiconductor integrated circuit includes a plurality of data output pins, a data processing circuit to generate output signals responsive to an input signal, and an output selection circuit with at least a normal mode and a test mode. A first group of output signals are provided to a first group of data output pins in a first test cycle of the test mode. And a second group of output signals are provided to a second group of data output pins during a second test cycle of the test mode. The semiconductor integrated circuit can be tested by means of a test device having less test pins than the output pins of the semiconductor integrated circuit under test.

Description:
RELATED APPLICATION INFORMATION  
       [0001]     This application claims priority from Korean application number 2003-16587, filed Mar. 17, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference in its entirety.  
       FIELD OF THE INVENTION  
       [0002]     The present invention relates to a semiconductor integrated circuit and, more particularly, to a semiconductor integrated circuit having a number of data output pins capable of selectively providing output signals and a test method thereof.  
       BACKGROUND OF THE INVENTION  
       [0003]      FIG. 1  is a diagram of a typical thin film transistor liquid crystal display (TFT-LCD) module  1 . The TFT-LCD module  1  includes a liquid crystal display (LCD) panel  5 , a drive circuit  2 , and a backlight  7 . The drive circuit  2  has a plurality of gate driver integrated circuits (ICs)  6 A- 6 B and source driver ICs  6 C- 6 E for driving a LCD panel  5 . A plurality of printed circuit boards (PCBs) receive a variety of circuit components such as a timing controller (not shown). The LCD panel  5  is liquid crystal inserted between two glass substrates. The LCD panel  5  enables the transmission of white light, from the backlight  7 , to a given pixel in order to express color images. Each pixel has a pixel signal voltage generated by the driving circuit  2  that determines where the LCD transmits the light. The backlight  7  has a lamp  8  and a reflex plate  9 . The backlight  7  generates white light with the lamp  8  acting as the light source.  
         [0004]     As is well known in the art, the LCD panel  5  includes gate lines and source lines which are intersected in a lattice shape. A pixel is the intersection of a gate line and a data line. For example, an LCD panel for a VGA (video graphics array) mode includes 640×480 pixels and an LCD panel for an XGA (extended graphics array) mode includes 1024×768 pixels. To drive a number of pixels, a gate driver IC, e.g.,  6 A, and a source driver IC, e.g.,  6 C, have a number of output pins. The number of these output pins is related to the resolution of the LCD panel  5  that the IC services. Since an IC cannot have innumerable output pins, the LCD module  1  uses a plurality of serially connected ICs. For example, since the LCD panel for the VGA mode has 640 source lines, a source driver IC  6 C having 320 output pins must be serially connected to a second source driver IC  6 B with 320 out pins.  
         [0005]     A semiconductor IC is, generally, tested by assigning test pins to all of the input and output pins, and then connecting the test pins to an appropriate test device. With the advent and development of high definition LCD panels, the number of output pins installed to the drive circuit  2  is increasing and therefore the distance between pins is decreasing. This leads to a difficulty in testing the drive circuit  2  because of the increasing number of test pins needed on an appropriate test device to properly test the drive circuit  2 .  
       SUMMARY OF THE INVENTION  
       [0006]     A feature of the present invention is to provide a semiconductor integrated circuit capable of selectively providing output signals to test semiconductor integrated circuits by means of a test device having less pins than the semiconductor integrated circuits it tests.  
         [0007]     Another feature of the present invention is to provide a test method of a semiconductor integrated circuit by means of a test device having less pins than the semiconductor integrated circuits it tests.  
         [0008]     According to an aspect of the present invention, a semiconductor integrated circuit includes a plurality of data output pins, a data processing circuit to generate output signals responsive to an input signal, and an output selection circuit with at least a normal mode and a test mode. A first group of output signals are provided to a first group of data output pins in a first test cycle of the test mode. And a second group of output signals are provided to a second group of data output pins during a second test cycle of the test mode.  
         [0009]     In an embodiment, the test cycles of the output selection circuit are repeated during the test mode.  
         [0010]     In an embodiment, the output selection circuit repeats the first and second test cycles during testing.  
         [0011]     In an embodiment, the output selection circuit sends ith output signals (i being a positive integer) to ith data output pins during the first cycle of the test mode. And the output selection circuit sends (i+1)th output signals to ith output pins during the second test cycle of the test mode.  
         [0012]     In an embodiment, the output selection circuit sends ith output signals (i being a positive integer) to (i+1)th data output pins during the first cycle of the test mode. And the output selection circuit sends the (i+1)th output signals to (i+1)th output pins during the second test cycle of the test mode.  
         [0013]     In an embodiment, the output selection circuit sends first to (N/2)th output signals (N being an integer) to first to (N/2)th data output pins during the first cycle of the test mode. And the output selection circuit sends ((N/2)+1)th to Nth output signals to first to (N/2)th output pins during a second test cycle of the test mode.  
         [0014]     In an embodiment, the output selection circuit sends the first to (N/2)th output signals (N being a integer) to the ((N/2)+1)th to Nth data output pins during the first cycle of the test mode. And the output selection circuit sends the ((N/2)+1)th to Nth output signals to the ((N/2)+1)th to Nth output pins during the second test cycle of the test mode.  
         [0015]     According to another embodiment, a method for outputting data during a test mode of a semiconductor integrated circuit having a plurality of data output pins is provided. The method includes sending some output signals to a first group of the data output pins and sending remaining output signals to the first group of the data output pins.  
         [0016]     In an embodiment, the sending some output signals and the sending remaining output signals are repeated during a test mode.  
         [0017]     In an embodiment, the sending some output signals includes sending ith output signals (i being a positive integer) are sent to ith data output pins.  
         [0018]     In an embodiment, i is a positive odd integer.  
         [0019]     In an embodiment, the sending remaining output signals includes sending (i+1)th output signals (i being a positive integer) to ith data output pins.  
         [0020]     In an embodiment, the sending some output signals includes sending first to (N/2)th output signals (N being a positive integer) to first to N/2th data output pins.  
         [0021]     In an embodiment, the sending remaining output signals includes sending ((N/2)+1)th to Nth output signals are sent to the first to (N/2)th data output pins.  
         [0022]     In an embodiment, the sending some output signals includes sending first to (N/2)th output signals (N being a positive integer) to the ((N/2)+1)th to Nth data output pins.  
         [0023]     In an embodiment, the sending remaining output signals includes sending ((N/2)+1)th to Nth output signals to the ((N/2)+1)th to Nth data output pins. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0024]      FIG. 1  is a block diagram of a typical TFT-LCD module.  
         [0025]      FIG. 2  is a block diagram of internal circuits of a source driver IC according to an embodiment of the present invention.  
         [0026]      FIG. 3  is a flowchart of controlling multiplexers in the source driver IC shown in  FIG. 2 .  
         [0027]      FIG. 4A  and  FIG. 4B  show data output paths for the IC  100  shown in  FIG. 2 .  
         [0028]      FIG. 5  is a block diagram of a source driver IC according to another embodiment of the present invention.  
         [0029]      FIG. 6  is a flowchart of controlling a switching circuit according to another embodiment of the present invention.  
         [0030]      FIG. 7A  and  FIG. 7B  show data output paths for an IC  100  shown in  FIG. 5 . 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0031]     The construction of internal circuits of a source driver IC according to an embodiment of the present invention is illustrated in  FIG. 2 . Referring to  FIG. 2 , a source driver IC  100  includes data registers  10 _ 1 ˜ 10 _n, multiplexers  20 _ 1 ˜ 20 _n/ 2 ,  50 _ 1 ˜ 50 _n/ 2 , and  70 _ 1 ˜ 70 _n/ 2 , level shifters  30 _ 1 ˜ 30 _n, N-decoders  40 _ 1 ,  40 _ 3 , . . . , and  40 _n- 1 , P-decoders  40 _ 2 ,  40 _ 4 , . . . , and  40 _n, amplifiers  60 _ 1 ˜ 61 _n, and data output pins P 1 ˜Pn.  
         [0032]     The data registers  10 _ 1 ˜ 10 _n receive and store RGB data signals D 1 ˜Dn from a host controller (not shown). The multiplexers  20 _ 1 ˜ 20 _n/ 2  are each connected to the adjacent two data registers  10 _ 1 ˜ 10 _n, where they receive data signals D 1 ˜Dn stored in the connected data registers  10 _ 1 ˜ 10 _n and provide those data signals D 1 ˜Dn to the level shifters  30 _ 1 ˜ 30 _n. For example, the multiplexer  20 _ 1  transfers the data signals stored in the data registers  10 _ 1  and  10 _ 2  to the level shifters  30 _ 1  and  30 _ 2 , respectively. In this case, the transfer direction is periodically varied. Namely, in a first period, the multiplexer  20 _ 1  transfers the data stored in the data register  10 _ 1  to the level shifter  30 _ 1  and transfers the data stored in the data register  10 _ 2  to the level shifter  30 _ 2 . In a second period, the multiplexer  20 _ 1  transfers the data stored in the data register  10 _ 1  to the level shifter  30 _ 2  and transfers the data stored in the data register  10 _ 2  to the level shifter  30 _ 1 . The other multiplexers  20 _ 2 ˜ 20 _n/ 2  operates the same as the multiplexer  20 _ 1 . The level shifters  30 _ 1 ˜ 30 _n increase the voltage level of data signals transferred from corresponding multiplexers  20 _ 1 ˜ 20 _n/ 2  to a voltage level that is suitable for driving a pixel in device, e.g., an LCD.  
         [0033]     The N-decoders  40 _ 1 ,  40 _ 3 , . . . , and  40 _n- 1  and the P-decoders  40 _ 2 ,  40 _ 4 , . . . , and  40 _n decode a data signal having a voltage level increased by corresponding level shifters  30 _ 1 ˜ 30 _n. That is, the N-decoders  40 _ 1 ,  40 _ 3 , . . . , and  40 _n- 1  selectively outputs one of externally provided gray voltages according to the voltage level of the data signal transferred from the corresponding level shifters  30 _ 1 ,  30 _ 3 , . . . , and  30 _n- 1 . The P-decoders  40 _ 2 ,  40 _ 4 , . . . , and  40 _n selectively outputs one of externally provided gray voltages according to the voltage level of the data signal transferred from the corresponding level shifters  30 _ 2 ,  30 _ 4 , . . . , and  30 _n.  
         [0034]     The data stored in the data registers  10 _ 1  and  10 _ 2  are cross provided to the level shifters  30 _ 1  and  30 _ 2  because the level of a data signal must be periodically inverted to prevent the degradation of a liquid crystal. For example, gray voltages provided to the N-decoders  40 _ 1 ,  40 _ 3 , . . . , and  40 _n- 1  range from 0V to 7V, and gray voltages provided to the P-decoders  40 _ 2 ,  40 _ 4 , . . . , and  40 _n range from 8V to 15V. During the first cycle, externally provided data signals D 1 , D 3 , . . . , and Dn- 1  are decoded to one of the gray voltage ranging from 0V to 7V by the N-decoders  40 _ 1 ,  40 _ 3 , . . . , and  40 _n- 1 , and the data signals D 2 , D 4 , . . . , and Dn are decoded to one of the gray voltage ranging from 8V to 15V by the P-decoders  40 _ 2 ,  40 _ 4 , . . . , and  40 _n. During the second cycle, externally provided data signals D 1 , D 3 , . . . , and Dn- 1  are decoded to one of the gray voltage ranging from 8V to 15V by the P-decoders  40 _ 2 ,  40 _ 4 , . . . , and  40 _n, and the data signals D 2 , D 4 , . . . , and Dn are decoded to one of the gray voltage ranging from 0V to 7V by the N-decoders  40 _ 1 ,  40 _ 3 , . . . , and  40 _n- 1 .  
         [0035]     The multiplexers  50 _ 1 ˜ 50 _n/ 2  are each connected to one N-decoder and one P-decoder and transfer gray voltage, provided from the connected decoders, to the amplifiers  60 _ 1 ˜ 60 _n. The multiplexers  50 _ 1 ˜ 50 _n/ 2  align with the multiplexers  20 _ 1 ˜ 20 _n/ 2 . For example, if multiplexer  20 _ 1  transfers the data signal D 1  stored in the data register  10 _ 1  to the level shifter  30 _ 1  and provides the data signal D 2  stored in the data register  10 _ 2  to the level shifter  30 _ 2 , the multiplexer  50 _ 1  transfers a signal outputted from the N-decoder  40 _ 1  to the amplifier  60 _ 1  and transfers a signal outputted from the P-decoder  40 _ 2  to the amplifier  60 _ 2 . The operation of the other multiplexers  50 _ 2 ˜ 50 _n/ 2  is identical with that of the multiplexer  50 _ 1  and will not be explained in further detail.  
         [0036]     Source driving signals S 1 ˜Sn from the amplifiers  60 _ 1 ˜ 60 _n are provided to a pixel of a corresponding LCD panel (not shown) through data output pins P 1 ˜Pn and multiplexers  70 _ 1 ˜ 70 _n/ 2 . Multiplexers  70 _ 1 ˜ 70 _n/ 2  are each coupled between two amplifiers  60 _ 1 ˜ 60 _n and the data output pins P 1 ˜Pn. In a normal mode, the source driving signals S 1 ˜Sn are provided to the LCD panel through the data output pins P 1 -Pn. But during a test mode, the source driver circuit IC  100  selectively outputs the source driving signals S 1 ˜Sn to a limited number of data output pins P 1 ˜P_n.  
         [0037]     Referring now to  FIG. 3 , which illustrates the data output operations in normal and test modes using a flowchart of controlling the multiplexers  70 _ 1 ˜ 70 _n/ 2  in the source driver IC  100  of  FIG. 2 . Multiplexers  70 _ 1 ˜ 70 _n/ 2  operate in response to a test mode signal TM. The test mode signal TM has a low level (i.e., logic “0”) in a normal mode and has a high level (i.e., logic “1”) in a test mode.  
         [0038]     At box S 110 , the multiplexers  70 _ 1 ˜ 70 _n/ 2  determine whether the test mode signal TM indicates a test mode. If the test mode signal TM indicates the normal mode, i.e., low level, this routine proceeds to box S 150 .  
         [0039]     At box S 150 , source driving signals S 1 ˜Sn, from the amplifiers  60 _ 1 ˜ 60 _n, are sent to their corresponding output pins P 1 ˜Pn, via the multiplexers  70 _ 1 ˜ 70 _n/ 2 . For example, the source driving signal S 1 , from the amplifier  60 _ 1 , is sent to output pin P 1  through multiplexer  70 _ 1 , and the source driving signal S 2 , from the amplifier  60 _ 2 , is sent to output pin P 2  through the multiplexer  70 _ 1 .  
         [0040]     When the test mode signal TM indicates the test mode by, e.g., being at a high level, this routine proceeds to box S 120 . At box S 120 , the first test cycle, a group of source signals (e.g., odd-numbered source signals) S 1 , S 3 , . . . , and Sn- 1 , from a group of amplifiers (e.g., odd-numbered amplifiers)  60 _ 1 ,  60 _ 3 , . . . , and  60 _n- 1 , are sent to a group of output pins (e.g., odd-numbered output pins) P 1 , P 3 , . . . , and Pn- 1  through the multiplexers  70 _ 1 ˜ 70 _n/ 2 . That is, during the first test cycle, multiplexers  70 _ 1 ˜ 70 _n/ 2  output the odd-numbered source driving signals S 1 , S 3 , . . . , and Sn- 1  to the odd-numbered output pins P 1 , P 3 , . . . , and Pn- 1 .  
         [0041]     At box S 130 , the second test cycle, the other group of source signals (e.g., even-numbered source signals) S 2 , S 4 , . . . , and Sn, from the other group of amplifiers (e.g., even-numbered amplifiers)  60 _ 2 ,  60 _ 4  . . . , and  60 _n, are sent to the group of the output pins (e.g., odd-numbered output pins) P 1 , P 3 , . . . , and Pn- 1  through the multiplexers  70 _ 1 ˜ 70 _n/ 2 . That is, during the second test cycle, the multiplexers  70 _ 1 ˜ 70 _n/ 2  output the even-numbered source driving signals S 2 , S 4 , . . . , and Sn to the odd-numbered output pins P 1 , P 3 , . . . , and Pn- 1 .  
         [0042]     Test pins T 1 ˜Tn/ 2  of the test device  200  are connected to corresponding pins, among a group of output pins (e.g., odd-numbered pins) P 1 , P 3 , . . . , and Pn- 1 , respectively. During the first test cycle the odd-numbered source driving signals S 1 , S 3 , . . . , and Sn- 1  of the source driver IC  100  are transferred to the test device  200  through the odd-numbered output pins P 1 , P 3 , . . . , and Pn- 1  and the test pins T 1 ˜Tn/ 2 . During the second test cycle, the even-numbered source driving signals S 2 , S 4 , . . . , and Sn of the source driver IC  100  are transferred to the test device  200  through the odd-numbered output pins P 1 , P 3 , . . . , and Pn- 1  and the test pins T 1 -Tn/ 2 .  
         [0043]     At box S 140 , it is determined whether the test mode is completed. When the test mode signal TM transitions to a low level, the multiplexers  70 _ 1 ˜ 70 _n/ 2  determines the test mode is completed. When the test mode signal TM is maintained at a high level, the multiplexers returns to box S 120 . According to the present invention, the test device  200  having n/ 2  input pins is used to test a semiconductor integrated circuit having n output pins.  
         [0044]     Referring now to  FIG. 4A  and  FIG. 4B , where the test mode data output paths of the source driver IC  100  are illustrated. The data output path of  FIG. 4A  is a test mode path where a group of odd data signals D 1 , D 3 , . . . , and Dn- 1 , provided from a host controller, are respectively decoded by N-decoders  40 _ 1 ,  40 _ 3 , . . . , and  40 _n- 1  and the other group of even data signals D 2 , D 4 , . . . , and Dn are respectively decoded by P-decoders  40 _ 2 ,  40 _ 4 , . . . , and  40 _n. The decoded data signals, which are now referred to as source driving signals S 1 ˜Sn, are then sent to output pins P 1 , P 3 , . . . , and Pn. The data output path of  FIG. 4B  is a test mode path where when a group of odd data signals D 1 , D 3 , . . . , and Dn- 1  provided from a host controller are respectively decoded by P-decoders  40 _ 2 ,  40 _ 4 , . . . , and  40 _n and the other group of even data signals D 2 , D 4 , . . . , and Dn are respectively decoded by N-decoders  40 _ 1 ,  40 _ 3 , . . . , and  40 _n- 1 . The decoded data signals, which are now referred to as source driving signals S 1 ˜Sn, are then sent to output pins P 1 , P 3 , . . . , and Pn. In  FIG. 4A  and  FIG. 4B , a solid line denotes a data path during a first test cycle and a dotted line denotes a data path during a second test cycle.  
         [0045]     Referring now to  FIG. 5 , a source driver IC according to another embodiment of the present invention is shown. Unlike the source driver IC  100  of  FIG. 2 , the source driver IC  300  of  FIG. 5  includes a switching circuit  80  instead of multiplexers  70 _ 1 ˜ 70 _n- 1 . In  FIG. 5  and  FIG. 2 , the same numerals denote the same components.  
         [0046]     The switching circuit  80  includes n/ 2  switches SW 1 ˜SWn/ 2  that operate in response to a test mode signal TM. As described above, the test mode signal TM has a low level in a normal mode and has a high level in a test mode. The stationary side of the switches SW 1 ˜SWn/ 2  is connected to output pins P 1 ˜Pn/ 2 , respectively. The alternating side of the switches SW 1 ˜SWn/ 2  is either connected to output terminals of a group of amplifiers  60 _ 1 ˜ 60 _n/ 2  or the output terminals of the other group of amplifiers  60 _n/ 2 + 1 ˜ 60 _n, depending upon the mode of operation. In a normal mode, the alternating side of the switches SW 1 ˜SWn/ 2  is connected to output terminals of a group of amplifiers  60 _ 1 ˜ 60 _n/ 2 . In a test mode, the alternating side of the switches SW 1 -SWn/ 2  is connected to the output terminals of the group of the amplifiers  60 _ 1 ˜ 60 _n/ 2  during a fist test cycle and are connected to output terminals of the other group of the amplifiers  60 _n/ 2 + 1 ˜ 60 _n during a second test cycle.  
         [0047]      FIG. 6  is a flowchart of controlling the switching circuit  80  of  FIG. 5 . Referring to  FIG. 6 , at box S 310 , the switching circuit  80  determines whether the test mode signal TM indicates a test mode. If the test mode signal TM indicates a normal mode, this routine proceeds to box S 350  where the alternating side of the switches SW 1 ˜SWn/ 2  is connected to output terminals of a group of amplifiers  60 _ 1 ˜ 60 _n/ 2 . Thus, a group of source driver signals S 1 ˜Sn/ 2 , from the group of the amplifiers  60 _ 1 ˜ 60 _n/ 2 , are sent to the output pins P 1 ˜Pn/ 2  through the switches SW 1 ˜SWn/ 2 . The other group of source driving signals Sn/ 2 + 1 ˜Sn, from the other group of amplifiers  60 _n/ 2 + 1 ˜ 60 _n, are sent to output pins Pn/ 2 + 1 ˜Pn.  
         [0048]     If the test mode signal TM indicates a test mode, this routine proceeds to box S 320  in which a first test cycle starts. During the first test cycle, the alternating side of the switches SW 1 ˜SWn/ 2  is connected to the output terminals of the group of the amplifiers  60 _ 1 ˜ 60 _n/ 2 . Thus, a group of source driving signals S 1 ˜Sn/ 2 , from the group of the amplifiers  60 _ 1 ˜ 60 _n/ 2 , are sent to the output pins P 1 ˜Pn/ 2  through the switches SW 1 ˜SWn/ 2 .  
         [0049]     At box S 330 , a second test cycle starts. During the second test cycle, the alternating side of the switches SW 1 ˜SWn/ 2  is connected to the output terminals of the other group of the amplifiers  60 _n/ 2 + 1 ˜ 60 _n. Thus, the other group of the source driving signals Sn/ 2 + 1 ˜Sn, from the other group of the amplifiers  60 _n 2 + 1 ˜ 60 n, are sent to the output pins P 1 ˜Pn/ 2 .  
         [0050]     The test pins T 1 ˜Tn/ 2  of the test device  200  are connected to the group of the output pins P 1 ˜Pn/ 2 , respectively. Thus, during the first test cycle, the group of the source driving signals S 1 ˜Sn/ 2  of the source driver IC  300  are transferred to the test device  200  through the group of the output pins P 1 ˜Pn/ 2  and the test pins T 1 ˜Tn/ 2 . During the second test cycle, the other group of the source driving signal Sn/ 2 + 1 ˜Sn of the source driver IC  300  are transferred to the test device  200  through the group of the output pins P 1 ˜Pn/ 2 .  
         [0051]     At box S 340 , the switching circuit  80  determines that the test mode is completed when the test mode signal TM transitions to a low level. When the test mode signal TM is maintained at a high level, the routine returns to box S 320 . According to the present invention, the test device  200  having n/ 2  input pins is used to test a semiconductor integrated circuit having n output pins.  
         [0052]      FIG. 7A  and  FIG. 7B  illustrate the test mode data output paths. The data output path of  FIG. 7A  is a data output path where the odd-numbered data signals D 1 , D 3 , . . . , and Dn- 1 , provided from a host controller, are decoded by N-decoders  40 _ 1 ,  40 _ 3 , . . . , and  40 _n- 1  and even-numbered data signals D 2 , D 4 , . . . , and Dn are decoded by P-decoders  402 ,  40 _ 4 , . . . , and  40 _n, respectively. During the first test cycle, the decoded data signals provided from the N-decoders  40 _ 1 ,  40 _ 3 , . . . , and  40 _n/ 2 - 1  and P-decoders  40 _ 2 ,  40 _ 4 , . . . , and  40 _n/ 2  are sent to output pins P 1 ˜Pn/ 2 . During the second cycle, the decoded data signals provided from the odd N-decoders  40 _n/ 2 + 1 ˜ 40 _n- 1  and even P-decoders  40 _n/ 2 + 240 _n/ 2  are sent to output pins P 1 ˜Pn/ 2 . The data output path of  FIG. 7B  is a data output path where when odd-numbered data signals D 1 , D 3 , . . . , and Dn- 1  provided from a host controller are respectively decoded by P-decoders and even-numbered data signals D 2 , D 4 , . . . , and Dn are respectively decoded by N-decoders, data signals provided from a host decoder are sent to output pins P 1 ˜Pn/ 2 , in two cycles as illustrated above. In  FIG. 7A  and  FIG. 7B , a solid line denotes a data path during a first test cycle and a dotted line denotes a data path during a second test period.  
         [0053]     As we explain above, a test device having n/ 2  test pins is used to test a semiconductor integrated circuit having n output pins. The invention, however, is not limited to only having two distinct test cycles, which send n/ 2  output signals from half of the output pins to the n/ 2  test pins each cycle. Numerous test cycles may be implemented, where, for each test cycle (T), the minimum number of test pins required in a test device is equal to n/T. Therefore, as the number of test cycles increases the number of test pins needed decreases. It is, therefore, possible to easily fabricate the test device and at a low cost. A test device having the same number of input pins as a semiconductor integrated circuit can test two semiconductor integrated circuits at the same time.  
         [0054]     Other modifications and variations to the invention will be apparent to a person skilled in the art from the foregoing disclosure. Thus, while only certain embodiment of the invention has been specifically described herein, it will be apparent that numerous modifications may be made thereto without departing from the spirit and scope of the invention.