Abstract:
The present invention relates to a folded differential amplifier having very high output impedance capable of being operated at frequencies of the order of gigahertz.

Description:
FIELD OF THE INVENTION 
     The present invention relates to a high frequency differential amplifier. 
     1. Background to the Invention 
     Existing prior art low voltage differential stage receiver input output cells that condition, that is, which square up, low voltage differential high frequency signals, such as, for example, 622 MHz, are presently required to provide some form of hysteresis to prevent inadvertent output switching caused by either (a) a momentary high impedance state of the input signals, that is, floating inputs, or (b) packaging of effects such as ringing and signal overlap. The gain required for signal squaring at 622 MHz is substantial when implemented using a 0.18 micron CMOS process. It will be appreciated that the provision of the required hysteresis requires a corresponding increase in gain margin. Since, under worst-case conditions, the 622 MHz output is only just realisable using conventional circuit techniques, the minimum hysteresis value is at best only present under typical to worst-case conditions, if at all. 
     It is an object of the present invention at least to mitigate the above problems of the prior art. 
     2. Summary of the Invention 
     Accordingly, an embodiment of the present invention provides an amplifier comprising an input stage having at least one signal input terminal and a biasing arrangement arranged to bias the at least one signal input terminal, an output stage comprising a pair of FET transistors arranged such that the gates thereof are biased using a common mode gate bias voltage derived from a resistor divider formed between the output terminals of the pair of FET transistors. 
     Advantageously, embodiments of the present invention increase, and preferably maximise, the hysteresis above a level of 25 mV under all operating conditions. 
     It will be appreciated that such a hysteresis requires extra gain to give the required margin. 
     In an embodiment, if a 40 mV (±20 mV) hysteresis is required, it will be appreciated that the effective minimum differential input signal amplitude value for the circuit without hysteresis changes from the ±100 mV specified level to ±80 mV, ie the circuit gain needs to be appropriately increased. This embodiment achieves a 40 mV hysteresis. 
     Embodiments of the present invention allow the realisation of a high output impedance differential amplifier that is operable at high clocking speeds or that can process high frequency signals. This is in contrast to conventional output stages that use diode configured FETs that produce relatively low output impedances and which also suffer from the switching limitations imposed by the gates capacitances. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings in which: 
     FIG. 1 illustrates an embodiment of a high speed differential amplifier; and 
     FIGS. 2 and 3 show schematically the operation of the embodiment shown in FIG.  1 . 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 shows a differential amplifier according to a first embodiment. The differential amplifier  100  comprises a differential input stage  102  having two PMOS FETs P 2  and P 3  as inputs. The differential input stage  100  additionally comprises a current source  104 . The current source is implemented using a suitably biased pMOS FET P 1 . Preferably, the bias voltage applied to the pMOS current source  104  provides a current of 150 μA x3. 
     It will be appreciated that the pMOS FETs P 2  and P 3  forming the inputs of the differential input stage  102  are matching pairs. The drains of the PMOS FETs P 2  and P 3  forming the input stage  102  are coupled to a further current source  106 , that is, to a current source of an output stage  108 . The further current source  106  comprises four nMOS FETs N 1  to N 4 . The nMOS FETs N 1  to N 4  are arranged in series, between power lines  110  and  112 , with an output driver stage  114 . The further current source  106  is arranged such that nMOS FETs N 1  and N 3  are in series, PMOS FETs N 2  and N 4  are in series and nMOS FETs N 1  and N 3  are in parallel with nMOS FETs N 2  and N 4 . A resistor R 1  is coupled between two nodes A and B formed by the series arrangements of nMOS FETs N 1  and N 3  and nMOS FETs N 2  and N 4 . 
     The output driver stage  114  comprises fourth and fifth pMOS FETS P 4  and P 5 . The gates of the pMOS FETS P 4  and P 5  are coupled to the mid-point of a resistive arrangement, that is, a resister divider formed by two resistors R 2  and R 3  of equal value, R. The outputs  116  and  118  of the output driver stage  114  are taken from the drains of the first and second PMOS FETs P 4  and P 5 . In a preferred embodiment, it should also be noted that the first and second pMOS FETs P 4  and P 5  of the output driver stage  114  are matched. 
     Although the first embodiment utilises values of R 2  and R 3  that are equal, asymmetrical values of R 2  and R 3  could be used to compensate for asymmetry in the succeeding stages. 
     The operation of the circuit will now be described with reference to FIG. 2, which shows a schematic version of the first embodiment. Referring to the circuit  200  of FIG. 2, it can be appreciated that the current sources formed by pMOS FET P 1  and nMOS FETs N 1  to N 4  have been replaced by schematic current sources producing respective currents. The first current source, formed by PMOS FET P 1 , produces a constant current I P     1   . The output stage  108  current sources, that is, nMOS FETs N 1  and N 2 , also produce constant currents I N     1    and I N     2   . However, the current sources realised by nMOS FETs N 3  and N 4  are arranged to produce variable currents I N     3    and I N     4    . The “variable” current sources follow as a consequence of the current through P 2  and P 3  from current source I P     1    acting on nodes A and B and thus altering the VGS values of N 3  and N 4 , ie, the currents entering these nodes must equal the currents leaving them (Kirchoff&#39;s current law). This arrangement is known as a folded differential amplifier stage. 
     The output voltages V op-p  and V op-n  that appear at output terminals  116  and  118  are given by the following equations: 
     
       
         V op-p =I N     4   *R 
       
     
     
       
         V op-n =I N3 *R 
       
     
     The maximum amplitude swing, V out , between the output terminals  116  and  118  is given by the following: 
     
       
           V   OUT =( I   N     1     *R )−([ I   N     1     −I   P     1     ]*R ) 
       
     
     which gives 
     
       
         V OUT=I   P     1   *R 
       
     
     since I N     1   =I N     2   . 
     The common mode bias voltage for the gates of the output PMOS devices P 4  and P 5  is derived from the resistor divider formed across the differential outputs  116  and  118 . This ensures that the gates receive the correct bias voltage levels according to output currents generated and associated noise components, that is, switching or substrate noise. 
     It will be appreciated that an advantage of this circuit is that the output loads have a high impedance with negligible (diffusion) capacitance for the same current drive as a conventional pair of diode configured PMOS output drivers which maximise voltage gain. 
     Further aspects of the operation of the first embodiment are shown in FIG.  3 . Assuming that the first current source P 1  produces a current of 150 μA x3, which will represent the normalised current, that is, x 1  represents 150 μA, x 4  represents 600 μA. Assume also that the current sources N 1  to N 4  produce respective x 4  currents, the DC bias voltage of the output voltage, V out , will be given by 
     
       
           V   TP =[( x 4−( x 1.5)]/ g   m =( x 2.5)/ g   m   
       
     
     and the maximum amplitude swing of V out  is given by R*(x3), assuming R&lt;&lt;g ds  of P 4  and P 5 , 
     where g m  is the transconductance and g ds  is the channel length modulation effect. 
     The reader&#39;s attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference. 
     All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive. 
     Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features. 
     The invention is not restricted to the details of any foregoing embodiments. The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.