Abstract:
An embodiment of the invention relates to a device for memorisation of a memory bit, provided with a bistable circuit with complementary first and second read/write terminals, wherein the device comprises an initialization input connected to said bistable circuit, said input being designed to go into a first state controlling a pre-load phase of said bistable circuit and following said preload phase, to go into a second state controlling setting up of said memory bit and its complement at said read/write terminals.

Description:
PRIORITY CLAIM  
       [0001]     This application claims priority from French patent application No. 0601292 filed Feb. 14, 2006, which is incorporated herein by reference.  
       TECHNICAL FIELD  
       [0002]     An embodiment of this invention relates to the field of non-volatile memories in general and to the structure of memory cells of this type in particular.  
       BACKGROUND  
       [0003]      FIG. 1  illustrates an example memory cell structure according to the state of the art. This memory cell comprises a bistable circuit  1  based on transistors made using the CMOS technology. This bistable circuit is typically composed of two cross coupled inverters Inv 1  and Inv 2 , each inverter then forming a storage node and having complementary read/write terminals Q and Qb. Each storage node Inv 1  and Inv 2  is composed of an nMos transistor N 1  and N 2  respectively, and a pMos transistor P 1  and P 2  respectively.  
         [0004]     The pMos transistor of each storage node is programmable, such that the threshold voltage of one pMos can be offset from the threshold voltage of the other pMos, and consequently the threshold voltage of one inverter can be offset from the threshold voltage of the other. The two inverters having different threshold voltages, when the cell is loaded, one of the two inverters is thus designed to switch more quickly than the other so that, depending on the state of programming, the required logical information 1 or 0 can be picked up on terminal Q, and the complementary logical state is then reached on terminal Qb.  
         [0005]     For example, consider the case in which the pMos transistor P 1  of inverter Inv 1  is programmed such that its threshold voltage Vth 1  is greater than the threshold voltage Vth 2  of the pMos transistor P 2  of the inverter Inv 2  (in this case we are referring to the absolute value, as is the case for the entire description given below). In this configuration, a reset phase is carried out when the voltage is applied, during which the two pMos transistors P 1  and P 2  are made conducting while the two nMos transistors N 1  and N 2  are blocked. However, considering that the threshold voltage Vth 1  is chosen to be greater than the threshold voltage Vth 2 , the transistor P 2  is faster and will change over before the other pMos transistor such that terminal Q will change to “0” when the power supply Vdd is stabilized, while at the same time the complementary logical state “1” is reached on terminal Qb.  
         [0006]     Similarly, if we choose Vth 1 &lt;Vth 2  after the pre-load phase as the power supply Vdd is increasing, the logical states “1” and “0” are reached on terminals Q and Qb respectively.  
         [0007]     In this configuration, the memory cell is necessarily initialized during the power supply increase phase. Such an operation implies that some specific constraints have to be taken into account during the power supply increase phase, particularly concerning the power supply voltage set-up time. If the increase in the power supply voltage is too fast, the behaviour of the cell may be severely disturbed, so that the cell can even be initialized in the inverse manner to what is normally expected. Therefore, one operating mode of such memory cell implies a fairly slow increase in the power supply voltage, of the order of a few milliseconds.  
         [0008]     Furthermore, another constraint to be taken into account relates to the size of transistors involved in these cells. More precisely, fairly large transistors have to be provided to overcome undesirable effects related to mismatches. Repeatability problems in the transistor manufacturing process can mean that MOS transistors designed to be strictly identical, actually have different characteristics, for example in terms of their gate length. By choosing large transistors, the variation of the gate length as a function of the total length then becomes too small to influence operation.  
         [0009]     But although this choice makes the assembly more robust, it is made at the detriment of other necessities and particularly security, because due to their size, these memory cells are then easily identifiable within a circuit. They can then be unsuitable for some security applications.  
       SUMMARY  
       [0010]     Therefore, one or more embodiments of this invention are intended to solve one or more of these disadvantages. An embodiment of the invention thus applies to a device for memorizing a memory bit comprising a bistable circuit with first and second complementary read/write terminals, wherein the device comprises an initialization input connected to said bistable circuit, said input being designed to go into a first state controlling a pre-load phase of said bistable circuit, and following said preload phase, to go into a second state controlling set-up of said memory bit and its complement at said read/write terminals.  
         [0011]     The bistable circuit used for the memorisation device according to an embodiment of the invention comprises:  
         [0012]     first and second transistors connected between the ground and the first and second terminals respectively, the gates of which are connected to said first and second terminals respectively;  
         [0013]     third and fourth transistors connected between the first and second terminals respectively and a power supply source, the gates of which are connected to the second and first terminals respectively.  
         [0014]     The first and second transistors may be of the nMos type and the third and fourth transistors may be of the pMos type.  
         [0015]     According to a first embodiment, the device comprises:  
         [0016]     fifth and sixth transistors, connected between the ground and between the second and first terminals respectively, the gates of which are connected to the initialization input of said device;  
         [0017]     seventh and eighth transistors connected between the first and second terminals and the third and fourth transistors respectively, the gates of which are connected to said initialization input of said device.  
         [0018]     According to one variant of this first embodiment, the seventh and eighth transistors are connected alternately respectively between the third and fourth transistors and the power supply source respectively, their gate being connected to the initialization input of said device.  
         [0019]     Advantageously, according to this first embodiment, the pairs of third and seventh transistors and of fourth and eighth transistors have different threshold voltages, said memory bit being set up as a function of the offset between said threshold voltages of said pairs.  
         [0020]     According to a second embodiment, the device comprises:  
         [0021]     fifth and sixth transistors connected between the first and second transistors respectively and between the first and second terminals respectively, the gates of which are connected to the initialization input of said device;  
         [0022]     seventh and eighth transistors connected between the first and second terminals respectively and the power supply source and the gates of which are connected to said initialization input of said device.  
         [0023]     According to one variant of this second embodiment, the fifth and sixth transistors are connected alternately between the first and second transistors respectively and the ground, their gate being connected to the reset input of said device.  
         [0024]     Advantageously, according to this second embodiment, the pairs of first and fifth transistors and second and sixth transistors have different threshold voltages, said memory bit being set up as a function of the offset between said threshold voltages of said pairs.  
         [0025]     The fifth and sixth transistors may be of the nMos type and the seventh and eighth transistors may be of the pMOs type. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0026]     These and other characteristics and advantages of one or more embodiments of this invention will become clearer after reading the following description given as an illustrative and non-limitative example and with reference to the appended figures, wherein:  
         [0027]      FIG. 1 , already described, illustrates a memory cell according to the state of the art based on the combination of two cross-coupled CMOS inverters with different threshold voltages forming a bistable circuit that can be used in a memorisation device according to an embodiment of the invention;  
         [0028]      FIG. 2  is a representation of a first embodiment of a memorisation device;  
         [0029]      FIG. 3  describes details of the structure of the memorisation device according to the first embodiment;  
         [0030]      FIG. 4  presents a variant of the structure illustrated in  FIG. 3 ;  
         [0031]      FIG. 5  is a representation of a second embodiment of the memorisation device;  
         [0032]      FIG. 6  describes details of the structure of the memorisation device according to the second embodiment;  
         [0033]      FIG. 7  presents a variant of the structure illustrated in  FIG. 6 ;  
         [0034]      FIG. 8  illustrates a time diagram describing operation of the memory cell according to the first embodiment. 
     
    
     DETAILED DESCRIPTION  
       [0035]     A device is proposed for memorisation of a memory bit, provided with a bistable circuit with complementary read/write terminals, according to an embodiment of the invention. This memorisation device thus has a structure similar to the structure already described with reference to  FIG. 1 , except that a specific input is designed to be connected to the memorisation device, thus advantageously enabling the memorisation device to be initialized independently of the power supply increase.  
         [0036]     Examples of such memorization devices are illustrated in  FIG. 2  and subsequent figures.  
         [0037]      FIG. 2  illustrates a first embodiment of the invention. Therefore, the memorization device comprises a bistable circuit  1  with two complementary terminals Q and Qb. This figure illustrates memorization device with two standard NOR gates, NOR 1  and NOR 2  respectively. The outputs Q and Qb of each of the gates NOR 1  and NOR 2  are looped back onto the first input of gate NOR 2  and gate NOR 1  respectively.  
         [0038]     A specific input RS is then provided to initialize the device and is applied to the second input of each of the gates NOR 1  and NOR 2 . Such a circuit then has two stable states and its operation will be described more specifically with reference to  FIG. 3 , illustrating the implementation of the logical functions in  FIG. 2  using the CMOS technology.  
         [0039]     In particular, the structure of the bistable  1  may be as illustrated on  FIG. 1 . Thus elements in  FIG. 3  in common with elements in  FIG. 1  have the same references.  
         [0040]     The memorisation device according to this embodiment then includes the nMos transistors N 3  and N 4  in addition to the elements already described, connected between the ground and between terminals Qb and Q respectively of the bistable circuit. The gates of these transistors N 3  and N 4  are connected to the input RS.  
         [0041]     pMos transistors P 3  and P 4  are also provided. They are connected between terminals Q and Qb respectively, and between the pMos transistors P 1  and P 2  of each inverter Inv 1  and Inv 2  respectively. The gates of transistors P 3  and P 4  are each also connected to the initialization input RS.  
         [0042]      FIG. 8  illustrates the time diagrams of the signals on the RS input and on terminals Q and Qb of the device. Therefore, the RS input allows to initialize the device. Thus, when the input RS is set to the logical state “1”, the two pMos transistors P 3  and P 4  are cut off while the two nMos transistors N 3  and N 4  are conducting. The terminals Q and Qb are then in the logical state “0”.  
         [0043]     The polarity of input RS is modified later, so as to change it to the low logical state “0”. The two pMos transistors P 3  and P 4  then become conducting while the nMos transistors N 3  and N 4  are cut off. The terminals Q and Qb are no longer dependent on the RS control and will vary depending on the state of the four pMos transistors P 1 , P 2 , P 3  and P 4  of the inverters Inv 1  and Inv 2 , similarly as explained above with reference to  FIG. 1 .  
         [0044]     Thus, in an example in which the threshold voltage Vth 1  chosen for each of the transistors in the pair of transistors P 1  and P 3  of the inverter Inv 1  is greater than the threshold voltage Vth 2  chosen for each of the transistors in the pair of transistors P 2  and P 4  of the inverter Inv 2 , the final logical state “0” is reached on the terminal Q and the terminal Qb is set-up in the complementary logical state “1” as illustrated in  FIG. 8 , with Vdd equal to 1 volt.  
         [0045]     On the contrary, if the threshold voltage Vth 1  of the pair of transistors P 1  and P 3  of the inverter Inv 1  is chosen to be less than then threshold voltage Vth 2  of the pair of transistors P 2  and P 4  of the inverter Inv 2 , the final logical state “1” is reached on the terminal Q and the terminal Qb is equal to “0”.  
         [0046]     Therefore, in its first state, the input RS can be used to initialize the terminals Q and Qb independently of the rise of the power supply Vdd, by preloading them to “0” and once the power supply is fixed, the input RS is put into a second logical state to control setting up the final logical states at terminals Q and Qb, using the conventional configuration of the two inverters in  FIG. 1  coupled with different threshold voltages.  
         [0047]      FIG. 4  presents a variant of the structure illustrated in  FIG. 3 , in which the two pMos transistor P 3  and P 4  controlled by the input RS are arranged differently. In this variant, the two pMos transistors P 3  and P 4  are then connected between the pMos transistor P 1  and P 2  respectively and the power supply source Vdd. Operation remains identical to operation described with reference to the structure in  FIG. 3 .  
         [0048]      FIG. 5  shows a second embodiment of the memorisation device. This figure illustrates the memorisation device with two standard NAND gates, NAND 1  and NAND 2  respectively. The Q and Qb outputs of each of the gates NAND 1  and NAND 2  are looped back onto a first input of gate NAND 2  and gate NAND 1  respectively.  
         [0049]     The common input RS designed to initialize the device is then applied to the second input of each of the gates NAND 1  and NAND 2 . Operation will now be described with reference to  FIG. 6 , illustrating implementation of the logical functions in  FIG. 5  using the CMOS technology.  
         [0050]     Starting from the bistable circuit already described in  FIG. 1 , the nMos transistor N 3  in this embodiment is connected between the nMos transistor N 1  of the inverter Inv 1  and terminal Q, and the nMos transistor N 4  is connected between the nMos transistor N 2  of the inverter Inv 2  and terminal Qb. The gates of these transistors N 3  and N 4  are connected to the input RS.  
         [0051]     The pMos transistors P 3  and P 4  are connected between terminals Q and Qb and the power supply source Vdd respectively. Each of the gates of transistors P 3  and P 4  are also connected to the input RS.  
         [0052]     In this configuration, instead of pre-loading the terminals Q and Qb to the logical state “0” as in the previous embodiment, they are preloaded to Vdd.  
         [0053]     To achieve this, the input RS is placed in the logical state “0” for the preloading phase. Therefore the two nMos transistors N 3  and N 4  are cut off, while the two pMos transistors P 3  and P 4  are conducting, putting the terminals Q and Qb in the logical state “1”.  
         [0054]     Then, secondly, the polarity of the input RS is modified to be put in the logical state “1”. The two pMos transistors P 3  and P 4  are then cut off, while the NMOS transistors N 3  and N 4  become conducting. Therefore, the terminals Q and Qb are no longer dependent on the RS control and will change conventionally depending on the state of the four nMos transistors NI, N 2 , N 3  and N 4  of the inverters Inv 1  and Inv 2 . The threshold voltages of the nMOS transistors are adjusted for the circuit with the NAND gate.  
         [0055]     Thus, in an example in which the threshold voltage Vth 1  chosen for each of the transistors in the pair of transistors N 1  and N 3  of the inverter Inv 1  is greater than the threshold voltage Vth 2  chosen for each of the transistors in the pair of transistors N 2  and N 4  of the inverter Inv 2 , the final logical state “1” is reached on the terminal Q and the terminal Qb is set-up in the complementary logical state “0”.  
         [0056]     On the other hand, if the threshold voltage Vth 1  of the transistors N 1  and N 3  of the inverter Inv 1  is chosen to be less than the threshold voltage Vth 2  of the transistors N 2  and N 4  of the inverter Inv 2 , the final logical state “0” is reached on the terminal Q and the terminal Qb is set-up in the complementary state “1”.  
         [0057]      FIG. 7  shows a variant of the structure illustrated on  FIG. 6 , in which the two nMos transistors N 3  and N 4  controlled by the input RS are arranged differently. In this variant, the two nMos transistors N 3  and N 4  are then connected between the transistors N 1  and N 2  and the ground respectively. Operation remains exactly the same as described with reference to the structure in  FIG. 6 .  
         [0058]     Due to the input RS, the preloading phase of terminals Q and Qb is done independently of the power supply rise, guaranteeing that the memory cell initialization will not be disturbed by the power supply set-up conditions and particularly by its rate of increase.  
         [0059]     Moreover, because only standard cells are used such as logical NOR gates or logical NAND gates, the memorisation device is difficult to identify when it is integrated in a circuit, which is particularly advantageous in the context of security applications.  
         [0060]     A cell may be programmed at the mask layout level. More particularly, the pMOS (or nMOS) transistors of the inverters are designed to be of a different type (one with a standard threshold voltage and the other with a high threshold voltage).  
         [0061]     Programming may also be done in the manufacturing process, by modifying the threshold voltage of the pMos (or nMos) transistor of one of the inverters, for example with equipment used for an ebeam type implantation.  
         [0062]     An integrated circuit, such as a memory, that includes one or more of the circuits of  FIGS. 2-7  may be incorporated into a system, e.g., a computer system, cell-phone system, and automobile system.  
         [0063]     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention.