Abstract:
Multi-level inverter introducing a new topology wherein standard IGBTs can be employed in place of common emitter IGBTs, wherein switching and conduction losses are minimized and wherein the number of implemented levels can be easily increased with the addition of a minimum number of components.

Description:
TECHNICAL FIELD OF THE INVENTION 
       [0001]    The present invention relates to the general technical field of power inverters and in particular to the technical field of multi-level inverters comprising three or more voltage levels. 
       STATE OF THE ART 
       [0002]    Multilevel inverter technology has emerged as a very important alternative in the area of high-power medium-voltage energy control. 
         [0003]    Voltage source multi-level inverters (comprising three or more voltage levels) are generally used to get a better approximation of the voltage waveform on the AC side of the inverter. As an important side benefit, they provide important improvements in terms of reducing the switches power losses and reducing the THD (Total Harmonic Distortion) of the output current and output voltage. 
         [0004]    Multilevel inverters, in general, are adapted to provide an output waveform that exhibits multiple steps at several voltage levels. Therefore, multilevel inverters can be adapted to produce a quasi-sinusoidal wave by having split-rail direct current inputs at two voltages, or positive and negative inputs with a central ground. As an example, a three level inverter, with two DC input voltages and a ground reference point, generally operates in a way to connect the inverter output terminals in sequence between the positive rail and ground, the positive rail and the negative rail, the ground rail and the negative rail and then both to the ground rail, so that a stepped waveform is generated at the inverter output. 
         [0005]    Multilevel inverters thus operate in a way to vary gradually three or more voltage levels in order to approximate stepped forms which are controlled to implement a sort of Pulse Amplitude Modulation. In addition, Pulse Width Modulation is implemented to control the transition between two voltage levels in the vicinity of the level changes. Thus, the multi-level inverter can decrease the number of commutations and therefore decrease harmonic frequency components, reducing switching losses. The resulting low harmonic frequency components in the current output from the multi-level inverter is advantageous in that, for grid-tied inverters supplied by photovoltaic panels, it allows to meet the stringent constraints on the THD of the AC current delivered to the AC grid. 
         [0006]    The main topologies of state-of-the-art multi-level voltage-source inverters are generally known as Neutral Point Clamped (NPC), Cascaded H-Bridge (CHB), Flying Capacitors (FCs) and Multi Point Clamped (MPC). 
         [0007]    The Multi Point Topology is a clamped topology wherein diodes or other electronic switching devices are used to clamp the dc bus voltages so as to achieve steps in the output voltage. 
         [0008]    In general, for a N level clamped inverter, when N is sufficiently high, the number of clamping devices and the number of switching devices will increase and make the system impracticable to implement. If the inverter runs under pulse width modulation (PWM) and diodes are used as clamping devices, the diode reverse recovery of these clamping diodes may become a major design challenge. 
         [0009]    An overview about state-of-the-art multi-level voltage inverters is provided in U.S. Pat. No. 4,467,407 wherein several multi-level topologies are described and commented. 
         [0010]    An example of Multi Point Clamped inverter of the prior art is depicted in  FIG. 1  illustrating a four-level DC-AC converter with an LC output inverter wherein the switching devices are made with IGBTs provided with antiparallel diodes in order to have all the inverter branches allowing bidirectional current. 
         [0011]    The ON/OFF state of the IGBTs of the circuit defines the voltage level on the AC side in that the switching devices Q 1  and Q 2  (associated to driving signals C and 
         [0012]    An respectively) and the switching devices Q 3  and Q 4  (associated to driving signals Bn and D respectively) are adapted to connect the negative terminal of DC voltage V− and the positive terminal of DC voltage source V+ with the load on AC side, the switching device Q 5  (associated to driving signal A) is adapted to connect the positive terminal of the voltage source V 4 + to the load and the switching device Q 6  (associated to driving signal B) is adapted to connect the negative terminal of the voltage source V 4 − to the load. 
         [0013]    The state of IGBTs is chosen as a function of AC output voltage. Three operative conditions occur depending on the level of output AC voltage Vout: 
         [0014]    1) V−&lt;Vout&lt;V+; 2) Vout&gt;V+and 3) Vout&lt;V−. 
         [0015]    Accordingly, the inverter modulation algorithm requires only three independent driving PWM signal, A, B and D.  FIG. 2  illustrates said driving PWM signal referenced to the voltage of the input voltage mid-point M. Driving signal C (complementary of driving signal D) is applied to the gate of the switch Q 1 , driving signal An (complementary of driving signal A) is applied to the gate of the switch Q 2 , driving signal Bn (complementary of driving signal B) is applied to the gate of the switch Q 3 , driving signal D is applied to the gate of the switch Q 4 , driving signal A is applied to the gate of the switch Q 5  and driving signal B is applied to the gate of the switch Q 6 . 
         [0016]    During the time interval wherein V−&lt;Vout&lt;V+, driving signals A and B are constantly OFF and therefore driving signals An and Bn are constantly ON. Driving signals C and D oscillates between ON and OFF levels and provide, on the AC side, a voltage waveform oscillating between the voltage values V− and V+. The DC-AC converter works like a standard two level inverter.  FIG. 3  illustrates the current paths of the inverter circuit when driving signal C is ON and driving signal D is OFF (and vice versa) and cos φ equals 1 or 0, wherein φ is the phase shift between voltage and current waveforms. 
         [0017]    When the output voltage Vout is higher than V+, driving signals C and Bn are constantly ON and therefore driving signals D and B are constantly OFF. Driving signals A and An oscillates between ON and OFF levels and provide, on the AC side, a voltage waveform oscillating between the voltage values V+ and V 4 +.  FIG. 4  illustrates the current paths of the inverter circuit when driving signal A is ON and driving signal An is OFF (and vice versa) and cos φ equals 1 or 0, wherein φ is the phase shift between voltage and current waveforms. 
         [0018]    When the output voltage Vout is lower than V−, driving signals C and A are constantly OFF and therefore driving signals D and An are constantly ON. Driving signals B and Bn oscillates between ON and OFF levels and provide, on the AC side, a voltage waveform oscillating between the voltage values V− and V 4 −.  FIG. 5  illustrates the current paths of the inverter circuit when driving signal B is ON and driving signal Bn is OFF (and vice versa) and cos φ equals 1 or 0, wherein φ is the phase shift between voltage and current waveforms. 
         [0019]    The multi-level inverters of the kind described above normally employ IGBTs as power switches due to their feature of combining the simple gate-drive characteristics of the MOSFETs with the high-current and low-saturation-voltage capability of bipolar transistors that allows these devices to achieve a maximum switching frequency well greater than 100 kHz with unmatched reliability and ruggedness. 
         [0020]    The main drawback of the multi-level inverter topology described above is the need of common emitter IGBTs which, at present, are not common among the main power semiconductor suppliers. A second important drawback of the multi-level inverter topology described above is the need of IGBTs with a voltage rating higher than the working DC bulk voltage. The higher the voltage rating the lower the overall efficiency due to the fact that, in general, both switching and conduction losses increase. Higher voltage rating IGBTs have higher VCEsat (and therefore higher conduction losses) and higher turn off and turn on times (and therefore higher switching losses). 
         [0021]    The multi-level inverter according to the present invention aims at solving the above problems of the state of the art introducing a new topology wherein standard IGBTs can be employed in place of common emitter IGBTs, wherein switching and conduction losses are minimized and wherein the number of implemented levels can be easily increased with the addition of a minimum number of components. 
     
    
     
         [0022]    Further objects and features of the present invention will be understood from the following detailed description of preferred, but non-exclusive, embodiments of the multi-level inverter according to the invention, when taken in conjunction with the accompanying drawings in which like reference numerals designate like parts and wherein: 
           [0023]      FIG. 1  shows a four-level Multi Point Clamped inverter of the state of the art with an LC output; 
           [0024]      FIG. 2  shows the driving PWM signal for the switches of the four-level Multi Point Clamped inverter circuit of  FIG. 1 ; 
           [0025]      FIG. 3  shows the current paths of the Multi Point Clamped inverter circuit of  FIG. 1  in a first operating condition; 
           [0026]      FIG. 4  shows the current paths of the Multi Point Clamped inverter circuit of  FIG. 1  in a second operating condition; 
           [0027]      FIG. 5  shows the current paths of the Multi Point Clamped inverter circuit of  FIG. 1  in a third operating condition; 
           [0028]      FIG. 6  shows the four-level Multi Point Clamped inverter according to the present invention with an LC output; 
           [0029]      FIG. 7  shows the five-level Multi Point Clamped inverter according to the present invention with an LC output; 
           [0030]      FIG. 8  shows the driving PWM signal for the switches of the four-level Multi Point Clamped inverter circuit of  FIG. 6 ; 
           [0031]      FIG. 9  shows the current paths of the Multi Point Clamped inverter circuit of  FIG. 6  in a first operating condition; 
           [0032]      FIG. 10  shows the current paths of the Multi Point Clamped inverter circuit of  FIG. 6  in a second operating condition; 
           [0033]      FIG. 11  shows the current paths of the Multi Point Clamped inverter circuit of  FIG. 6  in a third operating condition; 
           [0034]      FIG. 12  shows the driving PWM signal for the switches of the five-level Multi Point Clamped inverter circuit of  FIG. 7 ; 
           [0035]      FIG. 13  shows the current paths of the Multi Point Clamped inverter circuit of  FIG. 7  in a first operating condition; 
           [0036]      FIG. 14  shows the current paths of the Multi Point Clamped inverter circuit of  FIG. 7  in a second operating condition. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0037]    The multi-level inverter according to the present invention comprises: an input power source including a plurality of DC power supplies connected in series with same polarities; a plurality of terminals for taking desired DC voltage levels from said input power source, said terminals being electrically connected to each end of said DC power supplies and comprising a voltage reference, or ground, terminal; a plurality of switch blocks each comprising at least one input terminal and at least one output terminal, each switch block including, in turn, a plurality of on/off switches having open modes and short-circuit modes and input terminals and output terminals; a load having load terminals to be connected to the output terminals of said switch blocks. 
         [0038]    With reference to enclosed  FIG. 6 , a first preferred embodiment of the multi-level inverter according to the present invention is illustrated, comprising a four-level Multi Point Clamped single phase inverter, associated to an input power source including a plurality of DC power supplies serially interconnected with same polarities. Said input power source may comprise an input capacitor bank comprising a plurality of capacitors connected in series between the terminals of a single DC input bulk voltage, in order to split said DC input bulk voltage in a plurality of DC voltage levels referred to the voltage of the mid-point M which is taken as reference voltage or zero voltage. Alternatively, said input power source may comprise a plurality of batteries connected in series and adapted to provide a plurality of DC voltage levels referred to the voltage of said mid-point M. 
         [0039]    In the example illustrate in  FIG. 6 , the DC voltage levels of said input power source comprise: a higher positive voltage V 4 +, a lower positive voltage V+, a lower negative voltage V− and a higher negative voltage V 4 −. 
         [0040]    The four-level Multi Point Clamped inverter according to the first preferred embodiment of the present invention comprises a plurality of switch blocks including:input switch blocks  10  having first input terminals  13 ,  14 ,  15 ,  16 , each coupled to a different one of said voltage level terminals, and first output terminals  19 ,  20 ; and output switch blocks  11  having second input terminals  17 ,  18 , each one coupled to a different one of said first output terminalsl 9 ,  20  of said input switch blocks  10 , and second output terminals  21 , each one coupled to a different one of said load terminals. 
         [0041]    Each one of said switch blocks preferably comprises a couple of switches, an upper switch and a lower switch, arranged as half-bridges with the emitter of the upper switch electrically connected to the collector of the lower switch at a center point, said center point being the output terminal of each one of said switch blocks, the collector of the upper switch and the emitter of the lower switch being the input terminals of each one of said switch blocks. Other arrangements may be chosen for said switch blocks like, for instance, full bridge topology, wherein said switch blocks include four switches each. Said switches may advantageously and preferably comprise semiconductor switches. 
         [0042]    In greater detail and with reference to  FIG. 6 , said input switch blocks  10  may include a first and a second switch block. Said first and second switch blocks may include two switches connected as a half-bridges. 
         [0043]    Thus, said first switch block may comprise the switches Q 10  and Q 11  arranged as a half bridge with the emitter of Q 10  electrically connected to the collector of Q 11  at the center point of said half-bridge, said center point being connected to the output terminal of said first switch block. 
         [0044]    Said second switch block may comprise the switches Q 12  and Q 13  arranged as a half bridge with the emitter of Q 12  electrically connected to the collector of Q 13  at the center point of said half-bridge, said center point being connected to the output terminal of said second switch block. 
         [0045]    Said output switch blocks  11  may include a third switch block. Said third switch block may include the switches Q 14  and Q 15  arranged as a half bridge, with the emitter of Q 14  electrically connected to the collector of Q 15  at the center point of said half-bridge, said center point being connected to the output terminal of said third switch block. 
         [0046]    The collector of the upper switch Q 10  of said first switch block is connected to the higher positive voltage V 4 + terminal, the emitter of the lower switch Q 11  of said first switch block is connected to the lower negative voltage V− voltage terminal; the collector of the upper switch Q 12  of said second switch block is connected to the lower positive voltage V+ terminal, the emitter of the lower switch Q 13  of said second switch block is connected to the higher negative voltage V 4 − terminal; the collector of the upper switch Q 14  of said third switch block is connected to the center point of said first switch block, the emitter of said third switch block is connected to the center point of said second switch block. The center point of said third switch block is connected to the load terminal and provides said load with an AC voltage referred to the voltage of the mid-point M. The load can be an AC single-phase distribution network or any load requiring single-phase AC supply. 
         [0047]    Preferably, an LC filter is connected between the center point of said third switch block and the load in order to provide suppression of unwanted EMI noise generated by the inverter. 
         [0048]    The topology described above and illustrated in  FIG. 6  can be easily multiplied by three to be implemented as four-level Multi Point Clamped three-phase inverter, wherein said input switch blocks  10  and said output switch blocks  11  are in number of three and the output terminals of said output switch blocks  11  are each coupled to a different one of the three phase grid terminals and said mid-point M is coupled to the neutral terminal. Same considerations apply to multi-phase systems in general. 
         [0049]    As in the multi-level inverter circuits of the state of the art, the ON/OFF state of the switches of the multi-level inverter circuit according to the present invention defines the voltage level on the AC output side. 
         [0050]    The state of switches is chosen as a function of AC output voltage. Three operative conditions occur depending on the level of output AC voltage Vout: 
         [0051]    1) V−&lt;Vout&lt;V+; 2) Vout&gt;V+and 3) Vout&lt;V−. 
         [0052]    Accordingly, the inverter modulation algorithm requires only three independent driving PWM signal, A, B and C.  FIG. 8  illustrates said driving PWM signal referenced to the voltage of the input voltage mid-point M. Driving signal A is applied to the control gate of the switch Q 10 , driving signal C is applied to the gate of the switch Q 11 , driving signal Cn (complementary of driving signal C) is applied to the gate of the switch Q 12 , driving signal B is applied to the gate of the switch Q 13 , driving signal Bn (complementary of driving signal B) is applied to the gate of the switch Q 14  and driving signal An (complementary of driving signal A) is applied to the gate of the switch Q 15 . 
         [0053]    During the time interval wherein V−&lt;Vout&lt;V+, driving signals A and B are constantly OFF and therefore driving signals An and Bn are constantly ON. Driving signals C and Cn oscillates between ON and OFF levels and provide, on the AC side, a voltage waveform oscillating between the voltage values V− and V+. The DC-AC converter works like a standard two level inverter.  FIG. 9  illustrates the current paths of the inverter circuit when driving signal Cn is ON and driving signal C is OFF (and vice versa) and cos φ equals 1 or 0, wherein φ is the phase shift between voltage and current waveforms. 
         [0054]    When the output voltage Vout is higher than V+, driving signals Cn and Bn are constantly ON and therefore driving signals C and B are constantly OFF. Driving signals A and An oscillates between ON and OFF levels and provide, on the AC side, a voltage waveform oscillating between the voltage values V+ and V 4 +.  FIG. 10  illustrates the current paths of the inverter circuit when driving signal A is ON and driving signal An is OFF (and vice versa) and cos φ equals 1 or 0, wherein φ is the phase shift between voltage and current waveforms. 
         [0055]    When the output voltage Vout is lower than V−, driving signals Cn and A are constantly OFF and therefore driving signals C and An are constantly ON. Driving signals B and Bn oscillates between ON and OFF levels and provide, on the AC side, a voltage waveform oscillating between the voltage values V− and V 4 −.  FIG. 11  illustrates the current paths of the inverter circuit when driving signal B is ON and driving signal Bn is OFF (and vice versa) and cos φ equals 1 or 0, wherein φ is the phase shift between voltage and current waveforms. 
         [0056]    Said semiconductor switches preferably comprise standard IGBTs provided with antiparallel diode. Standard IGBTs can be employed, in place of common emitter IGBTs, and with a voltage rating lower than the input DC bulk voltage thus reducing cost and improving overall electrical efficiency. 
         [0057]    Furthermore, IGBTs as power switches combine the simple gate-drive characteristics of the MOSFETs with the high-current and low-saturation-voltage capability of bipolar transistors that allow IGBTs to achieve a maximum switching frequency well greater than 100 kHz with very high reliability and ruggedness. 
         [0058]    Three multi-level inverter according to the present invention and in particular the four-level inverter described above can easily be connected to supply three-phase AC loads or three-phase AC grids. The output terminals of each output switch block  11  will be electrically connected to one phase terminal of the AC load or the three-phase AC grids; the neutral terminal, if present, will be connected to said mid-point M, therefore assuming reference, or ground, voltage. 
         [0059]    With reference to enclosed  FIG. 7 , a preferred embodiment of the five-level Multi Point Clamped inverter according to the present invention is shown. Said five-level Multi Point Clamped inverter can be easily derived from the four-level Multi Point Clamped inverter described above, by simply adding further output switch blocks 12 . 
         [0060]    Said further output switch blocks  12  may include a fourth switch block comprising a couple of switches Q 16 , Q 17 , arranged with the emitters (or the collectors) electrically connected together, the collector (or the emitter) of the first switch Q 16  being the input terminal  22  of said fourth switch block and electrically connected to said mid-point M, and the collector (or the emitter) of the second switch Q 17  being the output terminal  23  of said fourth switch block and electrically connected to the load terminal and to said center point of said third switch block. 
         [0061]    Advantageously, a common emitter (or common collector) module and in particular a common emitter (or common collector) IGBT module can be employed comprising the switches Q 16  and Q 17  described above. 
         [0062]    The topology described above and illustrated in  FIG. 7  can be easily multiplied by three to be implemented as five-level Multi Point Clamped three-phase inverter, wherein said input switch blocks  10 , said output switch blocks  11  and said further output switch blocks  12  are in number of three and the output terminals of said output switch blocks  11  are each coupled to a different one of the three phase grid terminals and said mid-point M is coupled to the neutral terminal. Same considerations apply to multi-phase systems in general. 
         [0063]    The five-level Multi Point Clamped inverter according to the present invention preferably employs the same modulation control described above for the four level topology. 
         [0064]    Four operative conditions occur depending on the level of output AC voltage Vout: 
         [0065]    1) 0&lt;Vout&lt;V+; 2) V−&lt;Vout&lt;0; 3) Vout&gt;V+and 4) Vout&lt;V−. 
         [0066]    In this case four independent PWM control signals are necessary, A, B, C and D, together with their complementary signals An, Bn, Cn and Dn. In operating conditions 1) and 2), the five-level Multi Point Clamped inverter according to the present invention works like a three levels—active neutral point clamped inverter. In fact the output voltages oscillate between the values V+ and 0V in operating condition 1) and between V− and 0V in operating condition 2). Operating conditions 3) and 4) correspond to operating conditions 2) and 3), previously discussed regarding the four-level Multi Point Clamped inverter according to the present invention the current paths of which are depicted in  FIGS. 10 and 11 . 
         [0067]      FIG. 12  illustrates said driving PWM signal referenced to the voltage of the input voltage mid-point M. Driving signal A is applied to the gate of the switch Q 10 , driving signal D is applied to the gate of the switch Q 11 , driving signal C is applied to the gate of the switch Q 12 , driving signal B is applied to the gate of the switch Q 13 , driving signal Bn (complementary of driving signal B) is applied to the gate of the switch Q 14 , driving signal An (complementary of driving signal A) is applied to the gate of the switch Q 15 , driving signal Dn (complementary of driving signal D) is applied to the gate of the switch Q 16  and driving signal Cn (complementary of driving signal C) is applied to the gate of the switch Q 17 . 
         [0068]    During the time interval wherein 0&lt;Vout&lt;V+, driving signals A, B and D are constantly OFF and therefore driving signals An, Bn and Dn are constantly ON. Driving signals C and Cn oscillates between ON and OFF levels and provide, on the AC side, a voltage waveform oscillating between the voltage values 0 and V+.  FIG. 13  illustrates the current paths of the inverter circuit when driving signal C is ON and driving signal Cn is OFF (and vice versa) and cos φ equals 1 or 0, wherein φ is the phase shift between voltage and current waveforms. 
         [0069]    When the output voltage Vout is within 0 and V−, the switches A, B and C are constantly OFF while the switches An, Bn and Cn are constantly ON. Driving signals D and Dn provide, on the AC side, an voltage waveform oscillating within the voltage values 0 and V−.  FIG. 14  illustrates the current paths of the inverter circuit when driving signal D is ON and driving signal Dn is OFF (and vice versa) and cos φ equals 1 or 0, wherein φ is the phase shift between voltage and current waveforms. 
         [0070]    The remaining two operating conditions are the same as described above for the four-level inverter according to the present invention. 
         [0071]    When the output voltage Vout is higher than V+, driving signals C, Bn and Dn are constantly ON, driving signals Cn, B and D are constantly OFF. The branch comprising switches Q 16  and Q 17  is not conducting current. Driving signals A and An oscillates between ON and OFF levels and provide, on the AC side, a voltage waveform oscillating between the voltage values V+ and V 4 +.  FIG. 10  illustrates the current paths of the inverter circuit when driving signal A is ON and driving signal An is OFF (and vice versa) and cos φ equals 1 or 0, wherein φ is the phase shift between voltage and current waveforms. 
         [0072]    When the output voltage Vout is lower than V−, driving signals C, A and Dn are constantly OFF, driving signals Cn, An and D are constantly ON. Driving signals B and Bn oscillates between ON and OFF levels and provide, on the AC side, a voltage waveform oscillating between the voltage values V− and V 4 −.  FIG. 11  illustrates the current paths of the inverter circuit when driving signal B is ON and driving signal Bn is OFF (and vice versa) and cos φ equals 1 or 0, wherein φ is the phase shift between voltage and current waveforms. 
         [0073]    Preferably, the multi-level inverters according to the present invention employ 
         [0074]    IGBTs as power switches due to their feature of combining the simple gate-drive characteristics of the MOSFETs with the high-current and low-saturation-voltage capability of bipolar transistors that allows these devices to achieve a maximum switching frequency well greater than 100 kHz with very high reliability and ruggedness. 
         [0075]    Three multi-level inverter according to the present invention and in particular the four-level inverter described above can easily be connected to supply three-phase AC loads or three-phase AC grids. The output terminals of each output switch block  11  and further output switch block  12  will be electrically connected to one phase terminal of the AC load or the three-phase AC grids; the neutral terminal, if present, will be connected to said mid-point M, therefore assuming reference, or ground, voltage.