Abstract:
High speed synchronous counters are constrained to operate within certain speeds due to delays inherent in the counter configurations. By utilizing look-ahead carries, that is, producing carry signals in anticipation of when they might be required, much of the delay can be eliminated. Speed performance can be further improved by fashioning the look-ahead carry system from programmable gate arrays, where non-standard logic structures can be created.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a high speed synchronous counting system and to a process for increasing the speed capabilities of synchronous counters. 
     2. Description of Related Art 
     Until now, high speed synchronous counter configurations contained inherent delays which limited the speed at which the counters could operate. Some of these delays have been reduced through the use of a look-ahead carry signal which produces a carry signal one clock pulse before it is needed. However, even employing the one clock early look-ahead carries, the delay has only been reduced to a minimum of one gate delay. Typically, this translates to a guaranteed operating rate of 26 MHz using 70 MHz flip-flops. 
     High speed counters may be implemented by using gallium arsenide (GaAs) logic or high speed gate arrays. However, these are costly alternatives, compared to using slower, less expensive parts configured to provide increased speed performance. 
     SUMMARY OF THE INVENTION 
     This invention relates to a high speed synchronous counter system comprised of a plurality of electronic gates and flip flops interconnected to define a binary counter, means for generating look-ahead carry signals, means for supplying the look-ahead carry signals to desired gates and flip flops at desired times, and means for supplying the clock signals to desired flip flops. 
     Synchronous counters are comprised of a series of registers configured through the interconnection of electronic gates and flip flops. In operation, each of the registers contain a binary digit, which together represent the number of pulses counted. The speed at which the counters can perform is determined, in large part, by the speed at which the components of the counters can react. Typical delays encountered include gate delays (the time it takes an electronic gate to react), flip flop delays (the time it takes a flip flop to change to the desired output), interconnect delays (the time it takes the signal to travel between components), and set-up delays (the time an input signal to a flip flop must be held while waiting for the clock pulse). Each of these delays encountered in producing a carry signal reduces the speed performance of the counter. 
     In general, a carry signal is generated when the count contained in a particular group of registers has reached the limit of that group of registers (e.g., each digit is a one so the registers are &#34;full&#34;). The carry signal generated indicates to the next group of registers that one count is to be added. At the next clock pulse, one count is added to the contents of the next group of registers and the first group of registers is reset to zero. 
     Where the carry signal is not generated until the group of registers is full, the speed of the counter is constrained by the time it takes for the counter to execute the carry and reset the appropriate registers before it can resume counting. Therefore, to the extent that the carry signal can be generated before it is needed, and be applied at precisely the time required, this delay is avoided and the speed performance of the counter can be improved. 
     Look-ahead carries accomplish this by anticipating the need for the carry signal. In one preferred embodiment, the system begins to generate a look-ahead carry signal two clock pulses before it is required. In another preferred embodiment, the look-ahead carry signal is generated three clock pulses before it is required. As a result, delays inherent in the carry signal generating means occur prior to the time that the carry signal is needed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a simplified schematic diagram of a first embodiment of an configuration using flip flops and gates, which begins to generate look-ahead carry signals two clock pulses early. 
     FIGS. 2 and 2a are a complete schematic diagram of the first embodiment, incorporating the look-ahead carry signal generating means shown in FIG. 1. FIGS. 2 and 2a illustrate the configuration in a binary coded decimal (BCD) counter. 
     FIG. 3 shows a simplified schematic diagram of a second embodiment, which begins to generate look-ahead carry signals three clock pulses early. 
     FIGS. 4 and 4a are a complete schematic diagram of the second embodiment, incorporating the look-ahead carry signal generating means shown in FIG. 3. Specifically, FIGS. 4 and 4a illustrate a zero gate delay counter configuration. 
     FIG. 5 shows a timing diagram for the second embodiment illustrated in FIGS. 3 and 4 of the zero gate delay counter. 
     FIG. 6 illustrates the various delays in the system and how they are eliminated in the second embodiment, illustrated in FIGS. 3 and 4. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In preferred embodiments, a synchronous counter contains N registers, where register R 0  contains the least significant bit (LSB) of the count and register R N  contains the most signicant bit (MSB). The first four registers (R 3  through R 0 ) are grouped. A carry signal is required when these four registers are full. 
     In a first preferred embodiment, the counter registers are divided into groups of four, beginning with the register containing the LSB. Therefore, a carry signal 
     is applied to the second group of registers (R 7  through R 4 ) when the first group (R 3  through R 0 ) is full. 
     FIG. 1 illustrates a system 2 for a generating look-ahead carry signal two clock pulses before it is required. In the first preferred embodiment, the outputs of registers R 3  through R 1  4 and the inverse of the output of register R 0  6 are input to a first AND gate 8. The output of the first AND gate 8 is provided to a first D-type flip flop 10 and a second AND gate 12. In addition to the output of the first AND gate 8, the clock signal of the synchronous counter 13 is also applied to the first D-type flip flop 10. 
     When the first AND gate 8 goes high (i.e., when registers R 3 ,R 2 ,R 1 ,R 0  contain 1,1,1,0, respectively), the output of the first D-type flip flop 10 switches from low to high on the following clock pulse. By applying the output signal from the D-type flip flop 10 to the clock enable inputs of the second group of registers (R 7  through R 4 ) 14, one count (the carry) will be added to the contents of the second group of registers upon the arrival of the next clock pulse. The counter will reset the first group of registers to zero. 
     In preferred embodiments, carry signals are also required when the subsequent groups of registers become full. For example, a carry signal is required when the first and second groups of registers become full, thereby adding one count (the carry) to a third group of registers. 
     In the first embodiment, the carry signal for the third group of registers is, as with the carry signal for the second group of registers, generated two clock pulses before it is needed. The outputs of the second group of registers (R 7  through R 4 ) 13 are input to a second AND gate 12 along with the output from the first AND gate 8. Thus, when registers R 3 ,R 2 ,R 1 ,R 0  contain 1,1,1,0, respectively, and registers R 7  through R 4  contain all ones, the output of the second AND gate 12 will be high. This signal is input to a second D-type flip flop 16, whose output switches from low to high at the next clock pulse. By applying the output signal from the second D-type flip flop 16 to the clock enable inputs of the third group of registers (R 11  through R 8 ), one count (the carry) will be added to the contents of the third group of registers upon the arrival of the following clock pulse. The counter will reset the first and second groups of registers to zero. 
     FIGS. 2 and 2a show a complete schematic diagram for a 14-bit synchronous binary coded decimal (BCD) counter 18 utilizing the look-ahead carry created two clock pulses early. It was implemented using a 70 MHz Xilinx Logic Cell Array. The worst case delay through the counter would be 31 ns, yielding a worst case performance of 32 MHz and a nominal measured performance of 53 MHz. 
     Five component delays comprise the sum total worst case delay of 31 ns in the first preferred embodiment. The first of these delays is the delay inherent in register R 0  (worst case, 8 ns); the second delay is the interconnect between register R 0  and the first AND gate 8 (worst case, 2 ns); the third delay is the gate delay associated with the first AND gate 8 (worst case, 8 ns); the fourth delay is the interconnect between the output of the first AND gate 8 and the input of the second AND gate 12 (worst case, 5 ns); and the fifth delay is the setup time of the combination of the second AND gate 12 and the second D-type flip flop 16 (worst case, 8). Thus, the total worst case delay of this configuration is 31 ns, translating to a worst case performance of 32 MHz. 
     In the first preferred embodiment, illustrated in FIGS. 1 and 2 (with 2a), the carry signal was generated two clock pulses before it was needed, thereby eliminating some of the delay in providing the carry signal at the desired time. In a second preferred embodiment, a different configuration generates the look-ahead carry signal three clock pulses before it is needed, thereby eliminating even further the delay in providing the carry signal at the desired time. 
     The second preferred embodiment, shown in FIGS. 3 and 4 with 4a, is a configuration 20 wherein the carry signal is generated three clock pulses early. As in the first embodiment, the counter registers are divided into groups of four, beginning with the register containing the LSB. As before, a carry signal is required for the second group of registers (R 7  through R 4 ) when the first group (R 3  through R 0 ) is full. Likewise, a carry signal is required for the third group of registers (R 11  through R 8 ) when the first and second groups are full, and so on. 
     In the second preferred embodiment, the outputs of R 3 , R 2 , and R 0  22 and the inverse of the output of register R 1  24 are input to a first AND gate 26. The output of the first AND gate 26 is provided to a first D-type flip flop 28. In addition to the output from the first AND gate 26, the clock signal to the synchronous counter is also supplied to the first D-type flip flop 28. When the first AND gate 26 goes high (i.e., when registers R 3 ,R 2 ,R 1 ,R 0  contain 1,1,0,1, respectively), the output of the first D-type flip flop 28 switches from low to high on the following clock pulse. 
     The output of the first D-type flip flop 28 is provided to a second D-type flip flop 30. In addition to the output from the first D-type flip flop 28, the clock signal to the synchronous counter is also supplied to the the second D-type flip flop 30. Thus, at the following clock pulse, the output 32 of the second D-type flip flop 30 will switch from low to high, at which time the contents of registers R 3  through R 0  will be full. The output of the second D-type flip flop is applied to the clock enable inputs of a second group of registers (R 7  through R 4 ) 32. Therefore, at the next clock pulse, one count (the carry) will be added to the contents of the second group of registers. The counter will reset the first group of registers to zero. 
     A second AND gate 34, in concert with a third D-type flip flop 36, generates the carry signal to be provided to a third group of registers when registers R 7  through R 0  are full. The inputs to the second AND gate 34 include the output from the first D-type flip flop 28 and the outputs from the second group of registers, R 7  through R 4  38. Thus, when the output from the first D-type flip flop 28 goes high (i.e., the clock pulse after the first AND gate goes high), and registers R 7  through R 4  contain all ones, the output of the second AND gate 34 will go high. The output of the second AND gate 34 is input to the third D-type flip flop 36. In addition to the output of the second AND gate 34, the clock signal to the synchronous counter is also supplied to the the third D-type flip flop 36. Thus, the output of the third D-type flip flop 36 switches to high at the next clock pulse. By applying the output signal from the third D-type flip flop 36 to the clock enable inputs of the third group of registers (R 11  through R 8 ), one count (the carry) will be added to the contents of the third group of registers upon the arrival of the following clock pulse. In addition, the first and second groups of registers will be reset to zero. This is depicted in FIGS. 4 and 4a, which show a complete schematic diagram for a 12-bit synchronous binary counter 40 utilizing the look-ahead carry created three clock pulses early. 
     Also illustrated in FIG. 3 is a third preferred embodiment where the first AND gate 26 and the first D-type flip flop 28 are combined into a single logic structure 39 by utilizing a programmable logic array, such as the Xilinx Logic Cell Array. The worst case delay for this configuration would be 23 ns (versus 31 ns in the first preferred embodiment), yielding a worst case performance of 44 MHz and a nominal measured performance of 82 MHz (versus 32 MHz and 53 Mhz, respectively, in the first preferred embodiment). 
     Three component delays comprise the sum total worst case delay of 23 ns in the third preferred embodiment. The first of these delays is the delay inherent in register R 0  (worst case, 8 ns). The second delay is the greater of five delays, including: 1) the interconnect delay between register R 0  and the first AND gate 26 (worst case, 2 ns); 2) the interconnect delay between the first D-type flip flop 28 and the second D-type flip flop 30 (worst case, 1 ns); 3) the interconnect delay between the output of the second D-type flip flop 30 and the clock enable inputs of the second group of registers 32 (worst case, 7 ns); 4) the interconnect delay between the output of the first D-type flip flop 28 and the input of the second AND gate 34 (worst case, 1 ns); and 5) the interconnect delay between the output of the third D-type flip flop 36 and the registers (worst case, 7 ns). The third delay is the setup time of the single logic structure 39 comprising the first AND gate 26 and the first D-type flip flop 28 (worst case, 8). Thus, the total worst case delay of this configuration is 23 ns, translating to a worst case performance of 44 MHz. 
     A timing diagram 42 for the second preferred embodiment creating the carry signal three clock pulses early is shown in FIG. 5. The line labeled CARRY IN 44 shows the output of the first AND gate 26. The line labeled CARRY OUT 45 shows the output of the first D-type flip flop 28. The line labeled C3 46 shows the output 32 of the second D-type flip flop 30. In particular, the timing diagram shows the stages of the carry signal generation detailed through clock pulses 14, 15 and 16 (in which the carry signal is applied to the second group of registers) and again through clock pulses 254, 255 and 256 (in which the carry signal is applied to the third group of registers). 
     FIG. 6 illustrates the speed improvement realized by beginning the carry signal generation three clock pulses before it is required The delays under the old wide AND gate configuration, where the carry signal was not generated ahead of time, 50 versus the second preferred embodiment (new configuration), where the carry signal is generated three clock pulses ahead of time, 52 are shown. 
     While preferred embodiments of the present invention have been described and illustrated, various modifications will be apparent to those skilled in the art and it is intended to include all such modifications and variations within the scope of the appended claims.