Abstract:
A transmitter apparatus and method for reducing PAPR in an OFDM system. The transmitter apparatus performs a masking process on an input signal block using a plurality of mask sequences in an OFDM system, and selects a specific sequence having a lowest PAPR among IFFT-processed results. The apparatus includes a single IFFT for performing an IFFT process on the received signal block, and generating an IFFT-processed sequence; a plurality of shift registers for storing individual bits of the IFFT-processed sequence, cyclically shifting them, and generating the cyclically-shifted bits; a plurality of multiplier groups for multiplying coefficients determined by corresponding mask sequences by the output bits of the shift registers; and a plurality of adders corresponding to the plurality of multiplier groups for adding the multiplied results of the multiplier groups, thereby reducing system complexity and production costs.

Description:
PRIORITY  
         [0001]    This application claims priority to an application entitled “APPARATUS AND METHOD FOR REDUCING PEAK-TO-AVERAGE POWER RATIO IN ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING SYSTEM”, filed in the Korean Intellectual Property Office on Feb. 13, 2003, and assigned Serial No. 2003-9141, the contents of which are hereby incorporated by reference.  
         BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates generally to an OFDM (Orthogonal Frequency Division Multiplexing) communication system, and more particularly to an apparatus and method for reducing system complexity using an SLM (Selected Mapping) scheme to reduce a PAPR (Peak-to-Average Power Ratio).  
           [0004]    2. Description of the Related Art  
           [0005]    Conventionally, an OFDM communication system has been defined as an effective digital signal transmission scheme for loading a desired signal to be transmitted on a plurality of sub-band frequencies having carriers that are orthogonal to each other, and transmitting the desired signal loaded on the sub-band frequencies, such that uses an available frequency band at maximum efficiency and can effectively cope with burst errors generable by a fading operation. The OFDM scheme enables a frequency-selective fading phenomenon to approximate a frequency non-selective channel from the viewpoint of individual sub-channels to easily compensate for a serious frequency-selective fading phenomenon using a simple frequency area single-tap equalizer. The OFDM scheme inserts a cyclic prefix that is longer than a length of a multi-path channel delay spread into neighbor symbol blocks to remove interblock interference and interchannel interference, and is appropriate for a high-speed data transmission scheme using an IFFT (Inverse Fast Fourier Transformer) and an FFT (Fast Fourier Transformer).  
           [0006]    The sub-band signal used in the OFDM scheme is modulated by the IFFT so that an amplitude of the modulated signal proportional to the number of the sub-bands is displayed in the form of a Gaussian Distribution according to the Central Limit Theorem. Therefore, a transmission signal has disadvantages in that it encounters very high PAPR characteristics along with serious nonlinear distortion, which is worse than that of a single carrier transmission scheme due to nonlinear saturation characteristics of a high-power amplifier used for creating sufficient transmission power in wireless communication environments, resulting in limited performance of the OFDM scheme. Therefore, many developers have conducted intensive research into a variety of solutions for solving the aforementioned problems.  
           [0007]    The SLM scheme is a representative solution for reducing the PAPR, which creates U information series independent from each other to indicate the same entry information bit, selects the lowest PAPR among the U information series, and transmits the selected lowest PAPR. The U information series multiply the entry information bit by U mask sequences each having a predetermined length of N, and generate the multiplied result. The SLM scheme abruptly increases the number of calculations needed for an optimum PAPR as the number U of phase series increases, whereas it can maintain a data transfer rate. The SLM scheme uses U IFFTs, which are parallel to each other, to prevent a transmission time from being delayed, resulting in increased complexity of a transmitter.  
           [0008]    [0008]FIG. 1 is a block diagram illustrating a transmitter for use in an OFDM communication system for use with a conventional SLM scheme. Referring to FIG. 1, an information bit configured in the form of a binary signal is applied to a channel encoder  100  as an input signal. The channel encoder  100  encodes the received information bit to generate coded symbols, and the coded symbols are applied to a mapper  110 . The mapper  110  maps the received coded symbols with a single signal contained in a signal constellation. The mapping-processed output signals generated from the mapper  110  collect N signals according to the input magnitude N of the IFFT  140 , and form a single signal block. The signal block branches to U branches, and the branched result is applied to a plurality of multipliers  130 ,  132 , and  134 . A mask generator  120  generates U independent mask sequences M 1 , M 2 , . . . , M u  each having the length of N, and the U mask sequences M 1 , M 2 , . . . , M u  are transmitted to the multipliers  130 ,  132 , and  134 , respectively.  
           [0009]    The multipliers  130 ,  132 , and  134  adapt the signal block and the mask sequences M 1 , M 2 , . . . , M u , as their input signals, respectively. Therefore, the multipliers  130 ,  132 , and  134  perform the multiplication of two input signals, i.e., the signal block and one of the mask sequences M 1 , M 2 , . . . , M u . The output signals of the multipliers  130 ,  132 , and  134  are IFFT-processed by the IFFTs  140 ,  142 , and  144 , respectively, such that the IFFTs  140 ,  142 , and  144  output signal sequences S 1 , S 2 , . . . , S u , respectively A selector  150  receives the signal sequences S 8 , S 2 , . . . , S u , calculates individual PAPRs of the received signal sequences S 1 , S 2 , . . . , S u , selects a single signal sequence having the lowest PAPR among the received signal sequences S 1 , S 2 , . . . , S u , and transmits the selected signal sequence as a transmission signal.  
           [0010]    As described above, the SLM scheme selects a signal block having the lowest PAPR among U signal blocks generated by the same information bit, and transmits the selected signal block in such a way that it can effectively reduce the PAPR. The higher the number U of signal blocks, the lower the PAPR. However, as illustrated in FIG. 1, the SLM uses U parallel IFFTs to prevent a transmission time from being delayed. As a result, the higher the number U of signal blocks, the higher the complexity and cost of production of a transmitter system.  
         SUMMARY OF THE INVENTION  
         [0011]    Therefore, the present invention has been designed in view of the above problems, and it is an object of the present invention to provide an apparatus and method for reducing system complexity and a cost of production of an OFDM communication system based on an SLM scheme.  
           [0012]    It is another object of the present invention to provide an apparatus and method for reducing the number of IFFTs needed to reduce a PAPR in the OFDM communication system based on the SLM scheme.  
           [0013]    It is yet another object of the present invention to provide an apparatus and method for reducing the PAPR by sharing a single IFFT in the OFDM communication system based on the SLM scheme.  
           [0014]    In accordance with one aspect of the present invention, the above and other objects are accomplished by an SLM (Selected Mapping) apparatus for converting a signal block including a plurality of signals corresponding to a plurality of sub-carriers contained in a frequency domain for use in a transmitter of an OFDM (Orthogonal Frequency Division Multiplexing) communication system into a plurality of signal sequences contained in a time domain, and selecting one signal sequence having the lowest PAPR (Peak-to-Average Power Ratio) among the converted signal sequences. The SLM apparatus comprises: a single IFFT (Inverse Fast Fourier Transformer) for receiving the signal block contained in the frequency domain, performing an Inverse Fast Fourier Transform process on the signals of the signal block, and generating a conversion sequence symbol having a plurality of samples; a shift register for storing the samples of the conversion sequence symbol generated from the IFFT, wherein the shift register contains a plurality of memories serially connected to each other to store individual samples and acts as a cyclic shift register for connecting an output terminal of the last memory among the memories to an input terminal of a first memory among the memories such that a first input sample among the samples is applied to the first memory when it is generated from the last memory; a plurality of multiplier groups each composed of multipliers, wherein the multipliers are each connected to output terminals of the memories, receive a plurality of mask coefficient groups each composed of mask coefficients for generating a plurality of signal sequences containing a signal sequence having the lowest PAPR, and multiply output values of the plurality of memories by another received mask coefficient group among the received plurality of mask coefficient groups whenever the samples of the shift register are circulated; and a plurality of adder groups each having an adder for adding up output values of the multipliers contained in each multiplier group.  
           [0015]    In accordance with another aspect of the present invention, there is provided an SLM (Selected Mapping) method for converting a signal block including a plurality of signals corresponding to a plurality of sub-carriers contained in a frequency domain for use in a transmitter of an OFDM (Orthogonal Frequency Division Multiplexing) communication system into a plurality of signal sequences contained in a time domain, and selecting one signal sequence having the lowest PAPR (Peak-to-Average Power Ratio) among the converted signal sequences. The SLM method comprises the steps of: a) receiving the signal block contained in the frequency domain, performing an Inverse Fast Fourier Transform (IFFT) process on the signals of the signal block, and generating a conversion sequence symbol having a plurality of samples; b) storing the samples of the IFFT-processed conversion sequence symbol in a shift register, wherein the shift register contains a plurality of memories serially connected to each other to store individual samples and acts as a cyclic shift register for connecting an output terminal of the last memory among the memories to an input terminal of a first memory among the memories such that a first input sample among the samples is applied to the first memory when it is generated from the last memory; c) connecting a plurality of multiplier groups each composed of multipliers to output terminals of the memories, controlling the multipliers to receive a plurality of mask coefficient groups each composed of mask coefficients for generating a plurality of signal sequences containing a signal sequence having the lowest PAPR, and controlling the multipliers to multiply output values of the plurality of memories by another received mask coefficient group among the received plurality of mask coefficient groups whenever the samples of the shift register are circulated; and d) adding up output values of the multipliers contained in each multiplier group.  
           [0016]    In accordance with yet another aspect of the present invention, there is provided a transmitter apparatus for converting a signal block including a plurality of signals corresponding to a plurality of sub-carriers contained in a frequency domain for use in a transmitter of an OFDM (Orthogonal Frequency Division Multiplexing) communication system into a plurality of signal sequences contained in a time domain, selecting one signal sequence having the lowest PAPR (Peak-to-Average Power Ratio) among the converted signal sequences, and transmitting the selected signal sequence. The transmitter apparatus comprises: a single IFFT (Inverse Fast Fourier Transformer) for receiving the signal block contained in the frequency domain, performing an Inverse Fast Fourier Transform process on the signals of the signal block, and generating a conversion sequence symbol having a plurality of samples; a mask operator for receiving a plurality of mask coefficient groups generating a plurality of signal sequences containing a signal sequence having the lowest PAPR, multiplying the plurality of samples by another received mask coefficient group among the received plurality of mask coefficient groups whenever the plurality of samples generated from the IFFT are circulated, and generating a plurality of masking-processed sequences; and a selector for selecting a specific sequence having the lowest PAPR among the masking-processed sequences generated from the mask operator, and transmitting the selected sequence.  
           [0017]    In accordance with yet another aspect of the present invention, there is provided a data transmission method for converting a signal block including a plurality of signals corresponding to a plurality of sub-carriers contained in a frequency domain for use in a transmitter of an OFDM (Orthogonal Frequency Division Multiplexing) communication system into a plurality of signal sequences contained in a time domain, selecting one signal sequence having the lowest PAPR (Peak-to-Average Power Ratio) among the converted signal sequences, and transmitting the selected signal sequence. The method comprises the steps of: a) receiving the signal block contained in the frequency domain, performing an Inverse Fast Fourier Transform (IFFT) process on the signals of the signal block, and generating a conversion sequence symbol having a plurality of samples; b) receiving a plurality of mask coefficient groups generating a plurality of signal sequences containing a signal sequence having the lowest PAPR, multiplying the plurality of samples by another received mask coefficient group among the plurality of received mask coefficient groups whenever the plurality of samples generated from the IFFT are circulated, and generating a plurality of masking-processed sequences; and c) selecting a specific sequence having the lowest PAPR among the masking-processed sequences of the step (b), and transmitting the selected sequence. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]    The above and other objects, features, and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:  
         [0019]    [0019]FIG. 1 is a block diagram illustrating a transmitter for use in a conventional OFDM communication system based on an SLM scheme;  
         [0020]    [0020]FIG. 2 is a block diagram illustrating a transmitter for use in an OFDM communication system in accordance with a preferred embodiment of the present invention;  
         [0021]    [0021]FIG. 3 is a detailed block diagram illustrating a mask operator illustrated in FIG. 2 in accordance with a preferred embodiment of the present invention; and  
         [0022]    [0022]FIG. 4 is a detailed block diagram illustrating a mask operator for use in a specific case denoted by U=2 in accordance with a preferred embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0023]    Preferred embodiments of the present invention will be described in detail herein below with reference to the annexed drawings. In the drawings, the same or similar elements are denoted by the same reference numerals even though they are depicted in different drawings. Further, in the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.  
         [0024]    The present invention implements an SLM (Selected Mapping) scheme based on only one IFFT (Inverse Fast Fourier Transformer) using shift registers in the OFDM communication system, resulting in a reduced PAPR (Peal-to-Average Power Ratio).  
         [0025]    [0025]FIG. 2 is a block diagram illustrating a transmitter for use in the OFDM communication system in accordance with a preferred embodiment of the present invention. Referring to FIG. 2, an information bit is configured in the form of a binary signal, and is applied to a channel encoder  200  as an input signal. The channel encoder  200  encodes the received information bit to generate coded symbols, which are applied to a mapper  210  as input signals. The mapper  210  maps the received coded symbols with a predetermined signal contained in a signal constellation. The mapping-processed output signals generated from the mapper  210  collect N signals according to the input magnitude N of the IFFT  220 , and form a single signal block.  
         [0026]    The IFFT  220  performs an IFFT (Inverse Fast Fourier Transform) operation upon receipt of the signal block, and transmits a sequence generated by the IFFT operation to the mask operator  240 . In this case, each IFFT-processed output point of the IFFT  220  is called a sample. The sequence applied to the mask operator  240  is generated by converting parallel output samples of the IFFT  220  into serial samples.  
         [0027]    The mask operator  240  receives information of U mask sequences M 1 , M 2 , . . . , M u  from the mask generator  230 , performs a mask operation on the sequence received from the IFFT  220 , and outputs signal sequences S 1 , S 2 , . . . , S u . The selector  250  receives the signal sequences S 1 , S 2 , . . . , S u  from the mask operator  240 , calculates individual PAPRs of the received signal sequences S 1 , S 2 , . . . , S u , selects one having the lowest PAPR among the signal sequences S 1 , S 2 , . . . , S u , and transmits the selected signal sequence as a transmission signal.  
         [0028]    The mask operator  240  contained in the aforementioned OFDM transmitter must be designed to enable the output signal sequences S 1 , S 2 , . . . , S u  to be equal to those of output signal sequences of the IFFTs  140 ,  142 , and  144 . Prior to describing detailed internal structure and operations of the mask operator  240 , a mask operation of the multiplier  130  of FIG. 1 and operations of the IFFT  140  of FIG. 1 will be described using matrix and vector concepts.  
         [0029]    Referring to FIG. 1, a signal block X of the output magnitude N of the mapper  110  is represented by the following Equation 1:  
           X =( x   0   , x   1   , x   2   , x   3   , . . . , x   N−1 ) T    [Equation 1] 
         [0030]    where, A T  is a transpose matrix.  
         [0031]    An i-th mask sequence M i  generated from the mask generator  120 , which is multiplied by the signal block X, is represented by the following Equation 2 configured in the form of a diagonal matrix:  
               M   i     =     [           m     i   ,   0           0       0       0       …       0           0         m     i   ,   1           0       0       …       0           0       0         m     i   ,   2           0       …       0           0       0       0         m     i   ,   3           …       0           ⋮       ⋮       ⋮       ⋮       ⋰       ⋮           0       0       0       0       …         m     i   ,     N   -   1               ]             [     Equation                 2     ]                               
 
         [0032]    When using a predetermined condition of W=e j(2π/N)  according to Fourier Transform techniques well known in the art of communication technology, an IFFT matrix Q −1  and an FFT matrix Q can be represented by the following Equation 3:  
               Q     -   1       =           [     Equation                 3     ]                 1   N     [                      W     0   ·   0             W     0   ·   1             W     0   ·   2             W     0   ·   3           …         W     0   ·     (     N   -   1     )                   W     1   ·   0             W     1   ·   1             W     1   ·   2             W     1   ·   3           …         W     1   ·     (     N   -   1     )                   W     2   ·   0             W     2   ·   1             W     2   ·   2             W     2   ·   3           …         W     2   ·     (     N   -   1     )                   W     3   ·   0             W     3   ·   1             W     3   ·   2             W     3   ·   3           …         W     3   ·     (     N   -   1     )                 ⋮       ⋮       ⋮       ⋮       ⋰       ⋮             W       (     N   -   1     )     ·   0             W       (     N   -   1     )     ·   1             W       (     N   -   1     )     ·   2             W       (     N   -   1     )     ·   3           …         W       (     N   -   1     )     ·     (     N   -   1     )                          ]                           Q   =                           [                      W       -   0     ·   0             W       -   0     ·   1             W       -   0     ·   2             W       -   0     ·   3           …         W       -   0     ·     (     N   -   1     )                   W       -   1     ·   0             W       -   1     ·   1             W       -   1     ·   2             W       -   1     ·   3           …         W       -   1     ·     (     N   -   1     )                   W       -   2     ·   0             W       -   2     ·   1             W       -   2     ·   2             W       -   2     ·   3           …         W       -   2     ·     (     N   -   1     )                   W       -   3     ·   0             W       -   3     ·   1             W       -   3     ·   2             W       -   3     ·   3           …         W       -   3     ·     (     N   -   1     )                 ⋮       ⋮       ⋮       ⋮       ⋰       ⋮             W       -     (     N   -   1     )       ·   0             W       -     (     N   -   1     )       ·   1             W       -     (       -   N     -   1     )       ·   2             W       -     (     N   -   1     )       ·   3           …         W       -     (     N   -   1     )       ·     (     N   -   1     )                          ]                                           
 
         [0033]    Therefore, the i-th IFFT&#39;s output signal sequence S i =[s 0  s 1  s 2  s 3  . . . S N−1 ] T  generated by the i-th mask sequence Mi is represented by the following Equation 4:  
           S   i   =Q   −1   ·M   i   ·X    [Equation 4] 
         [0034]    For the convenience of description, the subscript ‘i’ will herein be omitted and the sequences are denoted by M and S in the present invention, so that the Equation 4 will also be represented by the following Equation 5:  
                   S   =       Q     -   1       ·   M   ·   X                 =       Q     -   1       ·   M   ·     (     Q   ·     Q     -   1         )     ·   X                 =       (       Q     -   1       ·   M   ·   Q     )     ·     Q     -   1       ·   X                   [     Equation                 5     ]                               
 
         [0035]    In order to acquire the matrix (Q −1 ·M·Q) shown in Equation 5, two vectors W P  and m can be represented by Equation 6:  
           W   P =( W   P−0   , W   P−1   , W   P−2   , W   P−3   , . . . , W   P·(N−1) )  
           m =( m   0   , m   1   , m   2   , m   3   , . . . , m   N−1 )   [Equation 6] 
         [0036]    The product x·y of every element of two vectors (W p , m) and its inner or dot product &lt;x,y&gt; are represented by Equation 7:  
                     x   ·   y     ≡     (         x   0     ·     y   0       ,       x   1     ·     y   1       ,       x   2     ·     y   2       ,       x   3     ·     y   3       ,   …              ,       x     N   -   1       ·     y     N   -   1           )                   &lt;   x     ,     y   &gt;   ≡       ∑     n   =   0       N   -   1              x   n     ·     y   n                         [     Equation                 7     ]                               
 
         [0037]    Therefore, the aforementioned definition of Equation 7 can also be represented by Equation 8:  
                 W   p     ·     W   q       =       (       W     p   ·   0       ,     W     p   ·   1       ,     W     p   ·   2       ,   …              ,     W     p   ·     (     N   -   1     )           )     ·             [     Equation                 8     ]                            (       W     q   ·   0       ,     W     q   ·   1       ,     W     q   ·   2       ,   …              ,     W     q   ·     (     N   -   1     )           )                                          =     (         W     p   ·   0       ·     W     q   ·   0         ,       W     p   ·   1       ·     W     q   ·   1         ,       W     p   ·   2       ·     W     q   ·   2         ,   …              ,                                              W       (     p   +   q     )     ·     (     N   -   1     )         )                                        =     (       W       (     p   +   q     )     ·   0       ,     W       (     p   +   q     )     ·   1       ,     W       (     p   +   q     )     ·   2       ,   …              ,                                              W       (     p   +   q     )     ·     (     N   -   1     )         )                                        =     W     (     p   +   q     )                                   &lt;     x   ·   z       ,     y   &gt;=       ∑     n   =   0       N   -   1              (       x   n     ·     z   n       )     ·     y   n                                                =       ∑     n   =   0       N   -   1              x   n     ·     (       z   n     ·     y   n       )                                                  =     &lt;   x       ,       z   ·   y     &gt;                                               
 
         [0038]    In the case of defining the matrix C using the above defined concepts under a predetermined condition C=Q −1 ·M·Q, the matrix C can be represented by Equation 9 below.  
                   C   =       Q     -   1       ·   M   ·   Q                              =         1   N          [           W   0               W   1               W   2               W   3             ⋮             W     (     N   -   1     )             ]       ·     [           m   0         0       0       0       …       0           0         m   1         0       0       …       0           0       0         m   2         0       …       0           0       0       0         m   3         …       0           ⋮       ⋮       ⋮       ⋮       ⋰       ⋮           0       0       0       0       …         m     N   -   1             ]     ·     [           W   0   T           W     -   1     T           W     -   2     T           W     -   3     T         …         W     -     (     N   -   1     )       T           ]                                  =         1   N          [           m   ·     W   0                 m   ·     W   1                 m   ·     W   2                 m   ·     W   3               ⋮             m   ·     W     (     N   -   1     )               ]       ·     [           W   0   T           W     -   1     T           W     -   2     T           W     -   3     T         …         W     -     (     N   -   1     )       T           ]                                  =       1   N          [             &lt;     m   ·     W   0         ,       W   0     &gt;               &lt;     m   ·     W   0         ,       W     -   1       &gt;               &lt;     m   ·     W   0         ,       W     -   2       &gt;           …           &lt;     m   ·     W   0         ,       W     -     (     N   -   1     )         &gt;                   &lt;     m   ·     W   1         ,       W   0     &gt;               &lt;     m   ·     W   1         ,       W     -   1       &gt;               &lt;     m   ·     W   1         ,       W     -   2       &gt;           …           &lt;     m   ·     W   1         ,       W     -     (     N   -   1     )         &gt;                   &lt;     m   ·     W   2         ,       W   0     &gt;               &lt;     m   ·     W   2         ,       W     -   1       &gt;               &lt;     m   ·     W   2         ,       W     -   2       &gt;           …           &lt;     m   ·     W   2         ,       W     -     (     N   -   1     )         &gt;               ⋮       ⋮       ⋮       ⋰       ⋮               &lt;     m   ·     W     (     N   -   1     )           ,       W   0     &gt;               &lt;     m   ·     W     (     N   -   1     )           ,       W     -   1       &gt;               &lt;     m   ·     W     (     N   -   1     )           ,       W     -   2       &gt;           …           &lt;     m   ·     W     (     N   -   1     )           ,       W     -     (     N   -   1     )         &gt;             ]                                  =       1   N          [             &lt;   m     ,         W   0     ·     W   0       &gt;               &lt;   m     ,         W   0     ·     W     -   1         &gt;               &lt;   m     ,         W   0     ·     W     -   2         &gt;           …           &lt;   m     ,         W   0     ·     W     -     (     N   -   1     )           &gt;                   &lt;   m     ,         W   1     ·     W   0       &gt;               &lt;   m     ,         W   1     ·     W     -   1         &gt;               &lt;   m     ,         W   1     ·     W     -   2         &gt;           …           &lt;   m     ,         W   1     ·     W     -     (     N   -   1     )           &gt;                   &lt;   m     ,         W   2     ·     W   0       &gt;               &lt;   m     ,         W   2     ·     W     -   1         &gt;               &lt;   m     ,         W   2     ·     W     -   2         &gt;           …           &lt;   m     ,         W   2     ·     W     -     (     N   -   1     )           &gt;               ⋮       ⋮       ⋮       ⋰       ⋮               &lt;   m     ,         W     (     N   -   1     )       ·     W   0       &gt;               &lt;   m     ,         W     (     N   -   1     )       ·     W     -   1         &gt;               &lt;   m     ,         W     (     N   -   1     )       ·     W     -   2         &gt;           …           &lt;   m     ,         W     (     N   -   1     )       ·     W     -     (     N   -   1     )           &gt;             ]                                  =       1   N          [             &lt;   m     ,       W   0     &gt;               &lt;   m     ,       W     -   1       &gt;               &lt;   m     ,       W     -   2       &gt;           …           &lt;   m     ,       W     -     (     N   -   1     )         &gt;                   &lt;   m     ,       W   1     &gt;               &lt;   m     ,       W   0     &gt;               &lt;   m     ,       W     -   1       &gt;           …           &lt;   m     ,       W     -     (     N   -   2     )         &gt;                   &lt;   m     ,       W   2     &gt;               &lt;   m     ,       W   1     &gt;               &lt;   m     ,       W   0     &gt;           …           &lt;   m     ,       W     -     (     N   -   3     )         &gt;               ⋮       ⋮       ⋮       ⋰       ⋮               &lt;   m     ,       W     (     N   -   1     )       &gt;               &lt;   m     ,       W     (     N   -   2     )       &gt;               &lt;   m     ,       W     (     N   -   3     )       &gt;           …           &lt;   m     ,       W   0     &gt;             ]                                  =       1   N          [             &lt;   m     ,       W   0     &gt;               &lt;   m     ,       W     (     N   -   1     )       &gt;               &lt;   m     ,       W     (     N   -   2     )       &gt;           …           &lt;   m     ,       W   1     &gt;                   &lt;   m     ,       W   1     &gt;               &lt;   m     ,       W   0     &gt;               &lt;   m     ,       W     (     N   -   1     )       &gt;           …           &lt;   m     ,       W   2     &gt;                   &lt;   m     ,       W   2     &gt;               &lt;   m     ,       W   1     &gt;               &lt;   m     ,       W   0     &gt;           …           &lt;   m     ,       W   3     &gt;               ⋮       ⋮       ⋮       ⋰       ⋮               &lt;   m     ,       W     (     N   -   1     )       &gt;               &lt;   m     ,       W     (     N   -   2     )       &gt;               &lt;   m     ,       W     (     N   -   3     )       &gt;           …           &lt;   m     ,       W   0     &gt;             ]                       [     Equation                 9     ]                               
 
         [0039]    When using a predetermined condition  
           c   i     =       1   N     &lt;   m       ,       W   i     &gt;     ,                         
 
         [0040]    the matrix C can be configured in the form of cyclic series as shown in Equation 10:  
             C   =     [           c   0           c     N   -   1             c     N   -   2             c     N   -   3             c     N   -   4           …         c   1               c   1           c   0           c     N   -   1             c     N   -   2             c     N   -   3           …         c   2               c   2           c   1           c   0           c     N   -   1             c     N   -   2           …         c   3               c   3           c   2           c   1           c   0           c     n   -   1           …         c   4               c   4           c   3           c   2           c   1           c   0         …         c   5             ⋮       ⋮       ⋮       ⋮       ⋮       ⋰       ⋮             c     N   -   1             c     N   -   2             c     N   -   3             c     N   -   4             c     N   -   5           …         c   0           ]             [     Equation                 10     ]                               
 
         [0041]    To summarize the above-described operation procedures, the operation procedures can also be represented as Equation 11:  
           S=Q   −1   ·M·X=C·Q   −1   X    [Equation 11] 
         [0042]    Based on Equation 11 above, the mask operation to be executed by the mask operator  240  illustrated in FIG. 2 is defined as the matrix C. More specifically, the result of a predetermined operation, where the signal block X is multiplied by the mask sequence M and then passes through the IFFT Q −1 , of the transmitter illustrated FIG. 1 is equal to that of a predetermined operation, where the signal block X passes through the IFFT  220  Q −1  and then the mask operator  240  performs a mask operation denoted by the matrix C, of the transmitter illustrated in FIG. 2. The matrix C will hereinafter be called a mask operation matrix.  
         [0043]    The mask sequences M 1 , M 2 , . . . , M u  generated from the mask generator  230  are pre-engaged between the transmitter and the receiver, and remain unchanged after the lapse of a communication initialization time, so that N coefficients C 0 , C 1 , . . . , C N−1  needed for the mask operation of the mask operator  240  are determined by only one operation at the communication initialization time according to the mask sequences M 1 , M 2 , . . . , M u , and need not perform additional operations while communicating with other devices. More specifically, the n-th coefficient C n  is determined by Equation 12:  
                 c   n     =       1   N     &lt;   m       ,       W   n     &gt;=       1   N            ∑     i   =   0       N   -   1              m   i     ·            j        (     2                   π   /   N       )       ·   i   ·   n                       [     Equation                 12     ]                               
 
         [0044]    Because the mask operation matrix C is a cyclic matrix, the mask operator  240  can be configured in the form of a simple structure using shift registers determined by elements of the first row of the mask operation matrix C. FIG. 3 is a detailed block diagram illustrating the mask operator  240  illustrated in FIG. 2 in accordance with a preferred embodiment of the present invention. Internal components and operations will hereinafter be described with reference to FIG. 3.  
         [0045]    Referring to FIG. 3, the mask operator  240  includes a shift register group including N shift registers  260 ,  262 ,  264 ,  266 , and  268  for storing individual bits of an input sequence having a predetermined size of N, U groups of multipliers, each including N multipliers  270 ,  272 ,  274 ,  276 ,  278 , and N multipliers  280 ,  282 ,  284 ,  286 ,  288  in order to perform U mask operations, and U adders  290  and  292  to perform U mask operations.  
         [0046]    Provided that a predetermined sequence generated by allowing an output signal block X=(x 0 , x 1 , x 2 , x 3 , . . . , x N−1 ) T  of the mapper  210  to pass through the IFFT  220  is set to ‘A’, ‘A’ can be represented by Equation 13:  
           A=Q   −1   X =( a   0   , a   1   , a   2   , a   3   , . . . , a   N−1 ) T    [Equation 13] 
         [0047]    The shift registers  260 ,  262 ,  264 ,  266 , and  268  are initialized to individual bits a 0 , a 1 , a 2 , a 3 , . . . ,a N−1  of the input sequence A. In this case, provided that the output sequence of the mask operator  240  for the mask sequence M 1  is denoted by S 1 =(s 1.0 , s 1.1 , s 1.2 , S 1.3 , . . . S 1.N−1 ) T , a matrix representation of the mask operator  240  for the mask sequence M 1  in association with individual input values can be represented by Equation 14:  
           C   1   =Q   −1   M   1   Q    [Equation 14] 
         [0048]    The multipliers  270 ,  272 ,  274 ,  276 , and  278  multiply first row values c 1.0 , c 1.N−1 , c 1.N−2 , c 1.N−3 , . . . , c 1.1  of the matrix C 1  by output values of the shift registers  260 ,  262 ,  264 ,  266 , and  268 , respectively. The mask operator  240  is operated with N stages associated with one input sequence A.  
         [0049]    S 1  generation operations of the first, multiplier group and the first adder  290  for use in the mask operator  240  will hereinafter be described.  
         [0050]    The multiplier  270  multiplies the output value a 0  of the shift register  260  by c 1.0 , and the multiplied result is transmitted to the adder  290 . The multiplier  272  multiplies the output value a 1  of the shift register  262  by C 1,N−1 , and the multiplied result is transmitted to the adder  290 . The multiplier  274  multiplies the output value a 2  of the shift register  264  by c 1,N−2 , and the multiplied result is transmitted to the adder  290 . The multiplier  276  multiplies the output value a 3  of the shift register  266  by C 1,N−3 , and the multiplied result is transmitted to the adder  290 . Similarly, the last multiplier  278  multiplies the output value a N−1  of the last shift register  268  by c 1.1 , and the multiplied result is transmitted to the adder  290 .  
         [0051]    The adder  290  adds up the multiplied results of the first multiplier group, and outputs the added result as the first element S 1.0  of the output sequence S 1 . The first element S 1.0  can be represented by the following Equation 15:  
           S   1.0   =a   0   ·c   1.0   +a   1   ·c   1,N−1   +a   2   ·c   1,N−2   +a   3   ·c   1,N−3   + . . . +a   N−1   ·c   1,1    Equation 15] 
         [0052]    Subsequently, values stored in the shift register group  294  are shifted to the left at the same time so that the shift registers  260 ,  262 ,  264 ,  266 , and  268  contain values a 1 , a 2 , a 3 , . . . ,a N−1 , a 0 , respectively.  
         [0053]    Next, the multiplier  270  multiplies the output value a 1  of the shift register  260  by c 1.0 , and the multiplied result is transmitted to the adder  290 . The multiplier  272  multiplies the output value a 2  of the shift register  262  by c 1,N−1 , and the multiplied result is transmitted to the adder  290 . The multiplier  274  multiplies the output value a 3  of the shift register  264  by c 1,N−2 , and the multiplied result is transmitted to the adder  290 . The multiplier  276  multiplies the output value a 4  of the shift register  266  by c 1,N−3 , and the multiplied result is transmitted to the adder  290 . Similarly, the last multiplier  278  multiplies the output value a 0  of the last shift register  268  by c 1.1 , and the multiplied result is transmitted to the adder  290 .  
         [0054]    The adder  290  adds up the multiplied results of the first multiplier group, and outputs the added result as the second element s 1.1  of the output sequence S 1 . The second element s 1.1  can be represented by the following Equation 16:  
           s   1.1   =a   1   ·c   1.0   +a   2   ·c   1,N−1   +a   3   ·c   1,N−2   +a   4   ·c   1,N−3   + . . . +a   0   ·c   1.1    [Equation 16] 
         [0055]    The above-described operations of the shift register group, i.e., the first multiplier group, and the first adder  290  are repeated N times so that the values of the shift register group are completely circulated. In the case of the last shift operation, the shift registers  260 ,  262 ,  264 ,  266 , and  268  of the shift register group  240  contain values a N−1 , a 0 , a 1 , a 2 , . . . ,a N−2 , respectively.  
         [0056]    Accordingly, the multiplier  270  multiplies the output value a N−1  of the shift register  260  by c 1.0 , and the multiplied result is transmitted to the adder  290 . The multiplier  272  multiplies the output value a 0  of the shift register  262  by c 1,N−1 , and the multiplied result is transmitted to the adder  290 . The multiplier  274  multiplies the output value a 1  of the shift register  264  by c 1,N−2 , and the multiplied result is transmitted to the adder  290 . The multiplier  276  multiplies the output value a 2  of the shift register  266  by c 1,N−3 , and the multiplied result is transmitted to the adder  290 . Further, the last multiplier  278  multiplies the output value a N−2  of the last shift register  268  by c 1.1 , and the multiplied result is transmitted to the adder  290 .  
         [0057]    The adder  290  adds up the multiplied results of the first multiplier group, and outputs the added result as the N-th element s 1,N−1  of the output sequence S 1 . The N-th element s 1,N−1  can be represented by Equation 17:  
           S   1,N−1   =a   N−1   ·c   1.0   +a   0   ·c   1,N−1   +a   1   ·c   1,N−2   +a   2   ·c   1,N−3   + . . . +a   N−2   ·c   1.1    [Equation 17] 
         [0058]    As a result, the adder  290  can output all the N elements of the output signal sequence S 1 .  
         [0059]    The above-described operations for acquiring the output signal sequence S 1  using the mask sequence M 1  can equally be applied to the process for acquiring the output signal sequences S 2 , S 3 , . . . , S u  using the U−1 mask sequences M 2 , M 3 , . . . , M u .  
         [0060]    Operations for acquiring the last output sequence S u  in association with the last mask sequence M u  will hereinafter be described. In this case, the last output sequence S u  can be represented by Equation 18:  
           S   U =( S   U.0   , S   U.1   , S   U.2   , S   U.3   , . . . , S   U.N−1 ) T    [Equation 18] 
         [0061]    A plurality of multipliers  280 ,  282 ,  284 ,  286 , and  288  for use in the last multiplier group multiply the first row values C U,0 , C U,N−1 , C U,N−2 , C U,N−3 , . . . , C U,1  of the mask operation matrix C U =Q −1 M U Q for the last mask sequence M U  by output values of the shift register group, respectively. Thereafter, if the shift operation, the multiplication operation, and the addition operation are each repeated N times, the last adder  292  finally outputs the output signal sequence S U  having N elements.  
         [0062]    Using the above-described operations, the mask operator  240  outputs desired output signal sequences S 1 , S 2 , S 3 , . . . , S U  parallel to each other.  
         [0063]    [0063]FIG. 4 is an exemplary block diagram illustrating the mask operator  240  using shift registers in accordance with a preferred embodiment of the present invention. More specifically, FIG. 4 illustrates a simple configuration for generating two output signal sequences in association with an input sequence composed of 8 bits. Further, it is assumed that a predetermined condition denoted by N=8 and U=2 is applied to FIG. 4. The mask generator  230  illustrated in FIG. 2 generates two mask sequences M 1  and M 2 , and the mask operator  240  generates two output signal sequences S 1  and S 2  using the output sequence of the IFFT  220  and the mask sequences.  
         [0064]    Referring to FIG. 4, the mask operator  240  includes eight shift registers  300 ,  301 ,  302 ,  303 ,  304 ,  305 ,  306 , and  307 , first multipliers  310 ,  311 ,  312 ,  313 ,  314 ,  315 ,  316 , and  317  for the first output signal sequence S 1 , second multipliers  330 ,  331 ,  332 ,  333 ,  334 ,  335 ,  336 , and  337  for the second output signal sequence S 2 , a first added  320  and a second adder  340 .  
         [0065]    The input sequence A of the mask operator  240  can be represented by Equation 19:  
           A=Q− 1     X =( a   0   , a   1   , a   2   , a   3   , . . . , a   7 ) T    [Equation 19] 
         [0066]    where X is an input signal of the IFFT  220 .  
         [0067]    The first multipliers  310 - 317  multiply individual input signals by the first row values C 1.0 , C 1.7 , C 1.6 , C 1.5 , . . . , C 1.1  of the mask operation matrix C 1  for the first mask sequence M 1 , respectively. The first adder  320  adds up the multiplied results received from the first multipliers  310 ˜ 317 , and outputs the first output signal sequence S 1 . The second multipliers  330 ˜ 337  multiply individual input signals by the first row values C 2.0 , C 2.7 , C 2.6 , C 2.5 , . . . , C 2.1  of the mask operation matrix C 2  for the second mask sequence M 2 , respectively. The second adder  340  adds up the multiplied results received from the second multipliers  330 ˜ 337 , and outputs the second output signal sequence S 2 , so that the first and second output signal sequences S 1  and S 2  can be represented by the following Equation 20:  
           S   1 =(s 1.0   , s   1.1   , s   1.2   , s   1.3   , . . . , s   1.7 ) T    
           S   2 =(s 2.0   , s   2.1   , s   2.2   , s   2.3   , . . . , s   2.7 ) T    [Equation 20] 
         [0068]    In more detail, the mask operator  240  repeats eight operations for one input sequence A.  
         [0069]    The shift registers  300 ˜ 307  are initialized to individual bits a 0 , a 1 , a 2 , a 3 , . . . ,a 7 , respectively The first multiplier  310  multiplies the output value a 0  of the shift register  300  by c 1.0 , and the multiplied result is transmitted to the first adder  320 . The first multiplier  311  multiplies the output value, a 1  of the shift register  301  by c 1.7 , and the multiplied result is transmitted to the first adder  320 . The first multiplier  312  multiplies the output value a 2  of the shift register  302  by c 1.6 , and the multiplied result is transmitted to the first adder  320 . The first multiplier  313  multiplies the output value a 3  of the shift register  303  by c 1.5 , and the multiplied result is transmitted to the first adder  320 . The first multiplier  314  multiplies the output value a 4  of the shift register  304  by c 1.4 , and the multiplied result is transmitted to the first adder  320 . The first multiplier  315  multiplies the output value a 5  of the shift register  305  by c 1.3 , and the multiplied result is transmitted to the first adder  320 . The first multiplier  316  multiplies the output value a 6  of the shift register  306  by c 1.2 , and the multiplied result is transmitted to the first adder  320 . The first multiplier  317  multiplies the output value a 7  of the shift register  307  by c 1.1 , and the multiplied result is transmitted to the first adder  320 .  
         [0070]    The first adder  320  adds up the multiplied results of the first multipliers  310 ˜ 317 , and outputs the added result-as the first element s 1.0  of the first output signal sequence S 1 . The first element s 1.0  can be represented as follows:  
           s   1.0   =a   0   ·c   1.0   +a   1   ·c   1.7   +a   2   ·c   1.6   +a   3   ·c   1.5   + . . . +a   7   ·c   1.1    [Equation 21] 
         [0071]    The second multiplier  330  multiplies the output value a 0  of the shift register  300  by c 2.0 , and the multiplied result is transmitted to the second adder  340 . The second multiplier  331  multiplies the output value a, of the shift register  301  by c 2.7 , and the multiplied result is transmitted to the second adder  340 . The second multiplier  332  multiplies the output value a 2  of the shift register  302  by c 2.6 , and the multiplied result is transmitted to the second adder  340 . The second multiplier  333  multiplies the output value a 3  of the shift register  303  by c 2.5 , and the multiplied result is transmitted to the second adder  340 . The second multiplier  334  multiplies the output value a 4  of the shift register  304  by c 2.4 , and the multiplied result is transmitted to the second adder  340 . The second multiplier  335  multiplies the output value a 5  of the shift register  305  by c 2.3 , and the multiplied result is transmitted to the second adder  340 . The second multiplier  336  multiplies the output value a 6  of the shift register  306  by c 2.2 , and the multiplied result is transmitted to the second adder  340 . The second multiplier  337  multiplies the output value a 7  of the shift register  307  by c 2.1 , and the multiplied result is transmitted to the second adder  340 .  
         [0072]    The second adder  340  adds up the multiplied, results of the second multipliers  330 ˜ 337 , and outputs the added result as the first element s 2.0  of the second output signal sequence S 2 . The first element s 2.0  can be represented by Equation 22:  
           s   2.0   =a   0   ·c   2.0   +a   1   ·c   2.7   +a   2   ·c   2.6   +a   3   ·c   2.5   ·+ . . . +a   7   ·c   2.1    Equation 22] 
         [0073]    Subsequently, individual values stored in the shift registers  300 ˜ 307  are shifted to the left at the same time so that the shift registers  300 ˜ 307  contain values a 1 , a 2 , a 3 , . . . ,a 7 , a 0 , respectively. The above-described multipliers and adders perform the above operations on the shifted values, resulting in the second elements S 1.1  and S 2.1  of the first and second output signal sequences S 1  and S 2 .  
         [0074]    For repeating the aforementioned operation 8 times, the last output signal sequences S 1  and S 2  can be represented by Equation 23:  
         S 1   : s   1.0   =a   0   ·c   1.0   +a   1   ·c   1.7   +a   2   ·c   1.6   +a   3   ·c   1.5   +a   4   ·c   1.4   +a   5   ·c   1.3   +a   6   ·c   1.2   +a   7   ·c   1.1    s   1.1   =a   1   ·c   1.0   +a   2   ·c   1.7   +a   3   ·c   1.6   +a   4   ·c   1.5   +a   5   ·c   1.4   +a   6   ·c   1.3   +a   7   ·c   1.2   +a   0   ·c   1.1    s   1.2   =a   2   ·c   1.0   +a   3   ·c   1.7   +a   4   ·c   1.6   +a   5   ·c   1.5   +a   6   ·c   1.4   +a   7   ·c   1.3   +a   0   ·c   1.2   +a   1   ·c   1.1    s   1.3   =a   3   ·c   1.0   +a   4   ·c   1.7   +a   5   ·c   1.6   +a   6   ·c   1.5   +a   7   ·c   1.4   +a   0   ·c   1.3   +a   1   ·c   1.2   +a   2   ·c   1.1    s   1.4   =a   4   ·c   1.0   +a   5   ·c   1.7   +a   6   ·C   1.6   +a   7   ·c   1.5   +a   0   ·c   1.4   +a   1   ·c   1.3   +a   2   ·c   1.2   +a   3   ·c   1.1    s   1.5   =a   5   ·c   1.0   +a   6   ·c   1.7   +a   7   ·c   1.6   +a   0   ·c   1.5   +a   1   ·c   1.4   +a   2   ·c   1.3   +a   3   ·c   1.2   +a   4   ·c   1.1    s   1.6   =a   6   ·c   1.0   +a   7   ·c   1.7   +a   0   ·c   1.6   +a   1   ·c   1.5   +a   2   ·c   1.4   +a   3   ·c   1.3   +a   4   ·c   1.2   +a   5   ·c   1.1    s   1.7   =a   7   ·c   1.0   +a   0   ·c   1.7   +a   1   ·c   1.6   +a   2   ·c   1.5   +a   3   ·c   1.4   +a   4   ·c   1.3   +a   5   ·c   1.2   +a   6   ·c   1.1    S   2   : s   2.0   =a   0   ·c   2.0   +a   1   ·c   2.7   +a   2   ·c   2.6   +a   3   ·c   2.5   +a   4   ·c   2.4   +a   5   ·c   2.3   +a   6   ·c   2.2   +a   7   ·c   2.1    s   2.1   =a   1   ·c   2.0   +a   2   ·c   2.7   +a   3   ·c   2.6   +a   4   ·c   2.5   +a   5   ·c   2.4   +a   6   ·c   2.3   +a   7   ·c   2.2   +a   0   ·c   2.1    s   2.2   =a   2   ·c   2.0   +a   3   ·c   2.7   +a   4   ·c   2.6   +a   5   ·c   2.5   +a   6   ·c   2.4   +a   7   ·c   2.3   +a   0   ·c   2.2   +a   1   ·c   2.1    s   2.3   =a   3   ·c   2.0   +a   4   ·c   2.7   +a   5   ·c   2.6   +a   6   ·c   2.5   +a   7   ·c   2.4   +a   0   ·c   2.3   +a   1   ·c   2.2   +a   2   ·c   2.1    s   2.4   =a   4   ·c   2.0   +a   5   ·c   2.7   +a   6   ·c   2.6   +a   7   ·c   2.5   +a   0   ·c   2.4   +a   1   ·c   2.3   +a   2   ·c   2.2   +a   1   ·c   2.1    s   2.5   =a   5   ·c   2.0   +a   6   ·c   2.7   +a   7   ·c   2.6   +a   0   ·c   2.5   +a   1   ·c   2.4   +a   2   ·c   2.3   +a   3   ·c   2.2   +a   4   ·c   2.1    s   2.6   =a   6   ·c   2.0   +a   7   ·c   2.7   +a   0   ·c   2.6   +a   1   ·c   2.5   +a   2   ·c   2.4   +a   3   ·c   2.3   +a   4   ·c   2.2   +a   5   ·c   2.1    s   2.7   =a   7   ·c   2.0   +a   0   ·c   2.7   +a   1   ·c   2.6   +a   2   ·c   2.5   +a   3   ·c   2.4   +a   4   ·c   2.3   +a   5   ·c   2.2   +a   6   ·c   2.1    
         [0075]    Further, the first and second output signal sequences can be represented by Equation 24:  
                     S   1     =       (       s     1   ,   0       ,     s     1   ,   1       ,     s     1   ,   2       ,     s     1   ,   3       ,   …              ,     s     1   ,   7         )     T                              =       [             c     1   ,   0            c     1   ,   7            c     1   ,   6            c     1   ,   5            c     1   ,   4            c     1   ,   3            c     1   ,   2            c     1   ,   1                     c     1   ,   1            c     1   ,   0            c     1   ,   7            c     1   ,   6            c     1   ,   5            c     1   ,   4            c     1   ,   3            c     1   ,   2                     c     1   ,   2            c     1   ,   1            c     1   ,   0            c     1   ,   7            c     1   ,   6            c     1   ,   5            c     1   ,   4            c     1   ,   3                     c     1   ,   3            c     1   ,   2            c     1   ,   1            c     1   ,   0            c     1   ,   7            c     1   ,   6            c     1   ,   5            c     1   ,   4                     c     1   ,   4            c     1   ,   3            c     1   ,   2            c     1   ,   1            c     1   ,   0            c     1   ,   7            c     1   ,   6            c     1   ,   5                     c     1   ,   5            c     1   ,   4            c     1   ,   3            c     1   ,   2            c     1   ,   1            c     1   ,   0            c     1   ,   7            c     1   ,   6                     c     1   ,   6            c     1   ,   5            c     1   ,   4            c     1   ,   3            c     1   ,   2            c     1   ,   1            c     1   ,   0            c     1   ,   7                     c     1   ,   7            c     1   ,   6            c     1   ,   5            c     1   ,   4            c     1   ,   3            c     1   ,   2            c     1   ,   1            c     1   ,   0               ]     ·     [           a   0               a   1               a   2               a   3               a   4               a   5               a   6               a   7           ]                       S   1     =       (       s     2   ,   0       ,     s     2   ,   1       ,     s     2   ,   2       ,     s     2   ,   3       ,   …              ,     s     2   ,   7         )     T                              =       [             c     2   ,   0            c     2   ,   7            c     2   ,   6            c     2   ,   5            c     2   ,   4            c     2   ,   3            c     2   ,   2            c     2   ,   1                     c     2   ,   1            c     2   ,   0            c     2   ,   7            c     2   ,   6            c     2   ,   5            c     2   ,   4            c     2   ,   3            c     2   ,   2                     c     2   ,   2            c     2   ,   1            c     2   ,   0            c     2   ,   7            c     2   ,   6            c     2   ,   5            c     2   ,   4            c     2   ,   3                     c     2   ,   3            c     2   ,   2            c     2   ,   1            c     2   ,   0            c     2   ,   7            c     2   ,   6            c     2   ,   5            c     2   ,   4                     c     2   ,   4            c     2   ,   3            c     2   ,   2            c     2   ,   1            c     2   ,   0            c     2   ,   7            c     2   ,   6            c     2   ,   5                     c     2   ,   5            c     2   ,   4            c     2   ,   3            c     2   ,   2            c     2   ,   1            c     2   ,   0            c     2   ,   7            c     2   ,   6                     c     2   ,   6            c     2   ,   5            c     2   ,   4            c     2   ,   3            c     2   ,   2            c     2   ,   1            c     2   ,   0            c     2   ,   7                     c     2   ,   7            c     2   ,   6            c     2   ,   5            c     2   ,   4            c     2   ,   3            c     2   ,   2            c     2   ,   1            c     2   ,   0               ]     ·     [           a   0               a   1               a   2               a   3               a   4               a   5               a   6               a   7           ]                       [     Equation                 24     ]                               
 
         [0076]    As is apparent from the description above, the present invention controls an OFDM communication system to share only one IFFT using shift registers, instead of using U IFFTs parallel to each other, to reduce a PAPR using an SLM scheme, resulting in reduction of complexity and cost of production of the OFDM transmitter system.  
         [0077]    Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.