Abstract:
An apparatus having an input transmission line, a plurality of amplifiers and an output transmission line is disclosed. The input transmission line may include a plurality of first inductors configured to receive an input voltage. The amplifiers may be configured to generate a plurality of intermediate currents by amplifying a plurality of intermediate voltages at a plurality of first nodes between the first inductors. The output transmission line generally includes a plurality of second inductors configured to generate an output current at an output node by combining the intermediate currents. Each of a plurality of second nodes connected to the second inductors may transfer a plurality of the intermediate currents. Each of the second inductors generally has a different one of a plurality of inductance values.

Description:
This application relates to U.S. Provisional Application No. 61/825,633, filed May 21, 2013, which is hereby incorporated by reference in its entirety. 
     FIELD OF THE INVENTION 
     The present invention relates to high-frequency amplifiers generally and, more particularly, to a method and/or apparatus for implementing a distributed transconductance amplifier. 
     BACKGROUND OF THE INVENTION 
     Distributed amplifiers are commonly employed for ultra-broad bandwidth applications. The amplifiers achieve a broad bandwidth by absorbing parasitic elements of transistors into lowpass artificial input and output transmission lines with shunt capacitances mainly provided by the transistors and series inductors added by a designer. Common designs typically have a transistor per “section” and the amplified current from each section adds in phase at the output of the amplifiers. 
     Referring to  FIG. 1 , a diagram of a conventional uniform distributed amplifier  90  is shown. Distributions in the amplifier  90  are uniform with series inductances, shunt capacitances, and transistors of uniform size in each section. Termination resistors are used on both the input lines and the output lines to flatten gain and present favorable impedances. On the input side, a bias voltage is often applied to the input transmission line through the input termination resistor because the current criterion is low and so a negligible voltage drop is created through the resistor. A conventional bias injection method on the output side uses large inductive bias chokes on the output line—either integrated, external, or a combination of both. The conventional methods are effective, but external inductors are expensive and occupy very large circuit board area in cases where the amplifier extends to low frequencies. With uniform distributed amplifiers, the bias voltage on the output transmission line can also be applied through the output termination resistor if the current is relatively low, but cannot be implemented where no output line termination resistor is available. 
     It would be desirable to implement distributed transconductance amplifiers. 
     SUMMARY OF THE INVENTION 
     The present invention concerns an apparatus having an input transmission line, a plurality of amplifiers and an output transmission line. The input transmission line may include a plurality of first inductors configured to receive an input voltage. The amplifiers may be configured to generate a plurality of intermediate currents by amplifying a plurality of intermediate voltages at a plurality of first nodes between the first inductors. The output transmission line generally includes a plurality of second inductors configured to generate an output current at an output node by combining the intermediate currents. Each of a plurality of second nodes connected to the second inductors may transfer a plurality of the intermediate currents. Each of the second inductors generally has a different one of a plurality of inductance values. 
     The objects, features and advantages of the present invention include providing a distributed transconductance amplifier that may (i) provide broadband current into low impedance loads, (ii) provide high transconductance, (iii) occupy small die area, (iv) include bias injection circuits and/or (v) be implemented as an integrated circuit. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
         FIG. 1  is a diagram of a conventional uniform distributed amplifier; 
         FIG. 2  is a block diagram of an apparatus in accordance with a preferred embodiment of the present invention; 
         FIG. 3  is a block diagram of the apparatus with active loads; 
         FIG. 4  is a block diagram of the apparatus with four sections; 
         FIG. 5  is a block diagram of the apparatus with six sections; 
         FIG. 6  is a block diagram of the apparatus with eight sections; 
         FIG. 7  is a graph of simulated transconductance curves; 
         FIG. 8  is schematics of several example implementations of the active loads; and 
         FIG. 9  is a schematic of an example implementation of an active load circuit. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Embodiments of the present invention generally relate to non-uniform distributed amplifiers for transconductance applications. Transconductance amplification may amplify and convert an input voltage into an output current delivered into a load. The distributed amplifiers generally comprise multiple (e.g., four or more) non-uniform sections distributed between an input transmission line and an output transmission line. An impedance of the input transmission line may range from a few ohms (e.g., 5 ohms—Ω) to dozens of ohms (e.g., 50Ω) or more (e.g., 200Ω). An impedance of the output transmission line generally ranges from a few ohms (e.g., 10Ω) to multiple ohms (e.g., 50Ω). The amplifiers may include paired transistor outputs and one or more active current sources. The active current sources may be fabricated concurrently with the transistors and attached at the output nodes of the transistors to provide bias currents. The active bias circuits may be inserted at one or more nodes of the output transmission line such that current source shunt capacitances, such as an output shunt capacitance of each amplifier transistor, are absorbed into the output transmission line of the distributed amplifier. 
     Referring to  FIG. 2 , a block diagram of an apparatus  100  is shown in accordance with a preferred embodiment of the present invention. The apparatus (or circuit, device, component or integrated circuit)  100  may implement a non-uniform distributed transconductance amplifier. The circuit  100  generally comprises an input node (or port)  102 , multiple inductors  104   a - 104   n , a termination resistor (or impedance)  106   a , one or more blocks (or circuits)  108   a - 108   d , one or more blocks (or circuits)  109   a - 109   d , one or more blocks (or circuits)  110   a - 110   b , one or more blocks (or circuits)  111   a - 111   d , a power source (or supply)  112 , multiple inductors  114   a - 114   b , an output node (or port)  116  and one or more blocks (or circuits)  117   a - 117   b . The inductors  104   a - 104   n  and the resistor  106   a  may be connected in series to form an input transmission line  107 . The inductors  114   a - 114   b  may be connected in series to form an output transmission line  115 . The elements  104   a  to  117   b  may be implemented in hardware. 
     A signal (e.g., IN) may be received at the input node  102 . The signal IN generally conveys an input voltage to be amplified by the circuit  100 . The signal IN may be routed through the inductors  104   a - 104   n  and the resistor  106   a . Multiple intermediate signals (e.g., Va to Vd) may be created along the input transmission line  107  at each node between the inductors  104   a - 104   n . Each intermediate signal Va to Vd may be a voltage received by a respective circuit  108   a - 108   d . Each circuit  108   a - 108   d  may generate a signal (e.g., Ia to Id). The signals Ia to Id may be current signals. Each current Ia to Id may be a transconductance amplified version of the respective voltages Va to Vd. 
     The currents Ia and Ib may be conveyed through a node at one end of the inductor  114   a . The currents Ic and Id may be conveyed through a node at an end of the inductor  114   a  connected to the inductor  114   b . A signal (e.g., OUT) may be generated at the output node  116  based on the currents Ia to Id. The signal OUT may be an output current delivered to a load connected to the output node  116 . A supply voltage (e.g., VD) may be generated by the power source  112  and presented to the circuits  110   a  and  110   b . The circuits  110   a - 110   b  may provide constant and/or variable bias currents from the power source  112  to the circuits  108   a - 108   d.    
     Each inductor  104   a  and  104   n  may have a fixed inductance value (e.g., 0.2 nanohenrys—nH). The other inductors  104   b - 104   d  may have a different fixed inductance value (e.g., 0.4 nH or twice that of  104   a  and  104   n ). Other inductance values for the inductors  104   a - 104   n  may be implemented to meet the criteria of a particular application (e.g., 0.1 to 1 nH). The resistor  106   a  may have a fixed resistance (e.g., 50Ω). Other resistance values (e.g., 5 to 200Ω) may be implemented to meet the criteria of a particular application. 
     Each circuit  108   a - 108   d  may be implemented as a distributed section. The circuits  108   a - 108   d  are generally operational to generate the currents Ia to Id by transconductance amplification of the corresponding voltages Va to Vd. The circuits  108   a - 108   d  are shown represented in the figure as voltage controlled current sources with transconductance values (e.g., 50 milliSiemens—mS). Each circuit  108   a - 108   d  may have an input parasitic capacitance  109   a - 109   d  (e.g., 0.16 picofarads—pF) connected to a corresponding node of the input transmission line  107 . Each circuit  108   a - 108   d  may have an output parasitic shunt capacitance  111   a - 111   d  (e.g., 0.02 pF) connected to the corresponding node of the output transmission line  115 . Other transconductance values (e.g., 0.01 to 0.5 Siemens), input parasitic capacitance values (e.g., 0.05 to 0.5 pF) and/or other output parasitic capacitance values (e.g., 0.01 to 0.1 pF) may be implemented to meet the criteria of a particular application. 
     Each circuit  110   a - 110   b  may implement an active bias (or active load) circuit. The circuits  110   a - 110   b  may be scaled in size and are generally operational to provide fixed bias currents and/or variable bias currents from the power source  112  to the circuits  108   a - 108   d . The circuits  110   a - 110   b  are shown represented as current sources with parasitic shunt capacitances  117   a - 117   b  (e.g., 0.19 pF and 0.39 pF, respectively). Other parasitic shunt capacitance values (e.g., 0.05 to 0.7 pF) may be implemented to meet the criteria of a particular application). The circuits  110   a - 110   b  may insert the bias currents at one or more of the output nodes of the circuits  108   a - 108   d  such that the current source shunt capacitances, like the output shunt capacitance of the circuits  108   a - 108   d , are absorbed into the output transmission line  115  of the circuit  100 . The circuits  110   a - 110   b  may be fabricated coincidentally with the circuits  108   a - 108   d  to minimize cost and die (or circuit board) area. 
     The inductor  114   a  may have a fixed inductance value (e.g., 0.2 nH). The inductor  114   b  may have a different fixed inductance value (e.g., 0.062 nH). Other inductance values (e.g., 0.01 to 0.5 nH) for the inductors  114   a - 114   b  may be implemented to meet the criteria of a particular application. The inductance values are generally “tapered” as seen moving toward the output node  116 . The taper results in smaller inductance values closer to the output node  116  and larger inductance values further from the output node  116 . The taper may also results in larger capacitance values closer to the output node  116  and smaller capacitance values further from the output node  116 . The tapered impedance values along the output transmission line  115  generally cancel a given current traveling away from the output node  116 . Therefore, the output transmission line  115  may lack a termination resistance connected to the inductor  114   a  due to the cancellation of the current. 
     The circuit  100  generally provides distributed amplifier circuits  108   a - 108   d  used as broadband transconductance amplifiers. The circuits  108   a - 108   d  may be connected to the tapered impedances along the output transmission line  115  with the series inductors (e.g.,  114   a - 114   b ) and the shunt capacitors (e.g.,  117   a - 117   b ) of varying values. By way of example, the tapered output transmission line  115  may have a characteristic impedance of 40 ohms at the node where the inductor  114   a  connects to the circuits  108   a - 108   b  and 10 ohms at the output node  116 . Other impedances may be implemented to meet the criteria of a particular application. The circuit  100  may include paired output transistor connections (e.g., the circuit  108   a  paired with the circuit  108   b  and the circuit  108   c  paired with the circuit  108   d ). The paired connections may simplify a design of the output transmission line  115 . The topology generally includes the tapered impedances, paired transistor outputs and active bias circuits. 
     Pairing the circuits  108   a - 108   d  at the connections to the output transmission line  115  generally results in a phase delta between the two output currents (e.g., Ia+Ib and Ic+Id) that change a transfer characteristic of a sum of the two sections. The modified transfer characteristic generally adds a factor that may be a reciprocal of the natural frequency dependent impedance variation along the input transmission line  107  caused by the lumped series inductor/shunt capacitor topology. A net benefit may be a flatter gain over a broader bandwidth than common designs. The output transmission line  115  of the circuit  100  is shown with two inductors and two capacitors. The design generally represents a reduction in loss and size with no degradation in gain or bandwidth compared with the common (non-paired) designs. 
     Referring to  FIG. 3 , a block diagram of an apparatus  120  is shown. The apparatus (or circuit, device, component or integrated circuit)  120  may implement a non-uniform distributed transconductance amplifier. The circuit  120  may be a variation of the circuit  100 . The circuit  120  generally comprises the input node  102 , the inductors  104   a - 104   n , the termination resistor  106   a , the circuits  108   a - 108   d , multiple blocks (or circuits)  110   a - 110   d , the power source  112 , multiple inductors  114   c - 114   e , the output node  116  and multiple blocks (or circuits)  117   c - 117   f . The inductors  104   a - 104   n  and the resistor  106   a  may be connected in series to form an input transmission line. The inductors  114   c - 114   e  may be connected in series to form an output transmission line. The elements  104   a  to  117   f  may be implemented in hardware. 
     The signal IN may be received at the input node  102 . The signal IN may be routed through the inductors  104   a - 104   n  and the resistor  106   a . The intermediate signals Va to Vd may be created along the input transmission line at each node between the inductors  104   a - 104   n . Each intermediate signal Va to Vd may be received by a respective circuit  108   a - 108   d . The circuits  108   a - 108   d  may generate the corresponding currents Ia-Id. Each current Ia to Id may be a transconductance amplified version of a respective voltage Va to Vd. 
     The current Ia may be conveyed through a node at one end of the inductor  114   c . The current Ib may be conveyed through a node that connects the inductors  114   c  and  114   d . A node between the inductors  114   d  and  114   e  may convey the current IC. The current Id may be conveyed through a node at an end of the inductor  114   e  that is connected to the output node  116 . The signal OUT may be generated at the output node  116  based on the currents Ia to Id. The supply voltage VD may be generated by the power source  112  and presented to the circuits  110   a - 110   d . The circuits  110   a - 110   d  may provide constant and/or variable bias currents from the power source  112  to the circuits  108   a - 108   d . The circuits  110   a - 110   d  are shown represented as current sources with parasitic shunt capacitances  117   c - 117   f  (e.g., 0.18 pF, 0.38 pF, 0.58 pF and 0.38 pF, respectively). Other parasitic shunt capacitance values (e.g., 0.05 to 0.7 pF) may be implemented to meet the criteria of a particular application). 
     The circuits  108   a - 108   d  are shown represented in the figure as voltage controlled current sources with transconductance values (e.g., 50 mS). Other transconductance values (e.g., 0.01 to 0.5 Siemens) may be implemented to meet the criteria of a particular application. 
     The inductor  114   c  may have a fixed inductance value (e.g., 0.32 nH). The inductor  114   d  may have a different fixed inductance value (e.g., 0.16 nH). The inductor  114   e  may have yet a different inductance value (e.g., 0.107 nH). Other inductance values (e.g., 0.1 to 1 nH) for the inductors  114   c - 114   e  may be implemented to meet the criteria of a particular application. The inductance values are generally “tapered” as seen moving toward the output node  116 . The taper results in smaller inductance values closer to the output node  116  and larger inductance values further from the output node  116 . The taper may also result in larger capacitance values closer to the output node  116  and smaller capacitance values further from the output node  116 . The tapered impedance values along the output transmission line generally cancel a given current traveling away from the output node  116 . Therefore, the output transmission line may lack a termination resistance connected to the inductor  114   a  due to the cancellation of the current. 
     Referring to  FIG. 4 , a block diagram of an apparatus  130  is shown. The apparatus (or circuit, device, component or integrated circuit)  130  may implement a non-uniform distributed transconductance amplifier. The circuit  130  may be a variation of the circuit  100  and/or the circuit  120 . The circuit  130  generally comprises the input node  102 , the inductors  104   a - 104   n , a termination resistor (or impedance)  106   b , the circuits  108   a - 108   d , the power source  112 , the inductors  114   a - 114   b , the output node  116  and the capacitors  117   a - 117   b . The inductors  104   a - 104   n  and the resistor  106   b  may be connected in series to form the input transmission line. The inductors  114   a - 114   b  may be connected in series to form the output transmission line. The elements  104   a  to  117   b  may be implemented in hardware. 
     The pair of capacitors  117   a - 117   b  (e.g., 0.19 pF and 0.39 pF) may be connected to the nodes of the output transmission lines in the same locations where the circuits  110   a - 110   b  connect in the circuit  100 . The capacitors generally provide the same capacitance values as the parasitic shunt capacitors in the circuits  110   a - 110   b . The capacitors may connect the output nodes to a signal ground. Other capacitance values (e.g., 0.01 to 0.7 pF) may be implemented to meet the criteria of a particular application. The resistor  106   b  may have a fixed resistance (e.g., 50Ω). Other resistance values (e.g., 5 to 200Ω) may be implemented to meet the criteria of a particular application. 
     Referring to  FIG. 5 , a block diagram of an apparatus  140  is shown. The apparatus (or circuit, device, component or integrated circuit)  140  may implement a non-uniform distributed transconductance amplifier. The circuit  140  may be a variation of the circuits  100 ,  120  and/or  130 . The non-uniform distribution technique may be applied to amplifiers with more sections (e.g., six sections), as shown in the apparatus  140 . 
     The circuit  140  generally comprises the input node  102 , the inductors  104   a - 104   n , a termination resistor (or impedance)  106   c , multiple blocks (or circuits)  108   a - 108   f , multiple inductors  114   g - 114   i , the output node  116  and multiple blocks (or circuits)  117   g - 117   i . The inductors  104   a - 104   n  and the resistor  106   c  may be connected in series to form the input transmission line. The inductors  114   g - 114   i  may be connected in series to form the output transmission line. The elements  104   a  to  117   i  may be implemented in hardware. Multiple (e.g., three) capacitors  117   g - 1171  (e.g., 0.066 pF, 0.226 pF and 0.316 pF, respectively) may be connected between the nodes of the output transmission line and the signal ground. Other capacitance values (e.g., 0.01 to 1 pF) may be implemented to meet the criteria of a particular application. 
     The signal IN may be received at the input node  102 . The signal IN may be routed through the inductors  104   a - 104   n  and the resistor  106   c . Multiple intermediate signals (e.g., Va to Vf) may be created along the input transmission line at each node between the inductors  104   a - 104   n . Each intermediate signal Va to Vf may be a voltage received by a respective circuit  108   a - 108   f . The circuits  108   a - 108   f  may generate the corresponding currents Ia to If. Each current Ia to If may be a transconductance amplified version of a respective voltage Va to Vf. 
     The currents Ia and Ib may be conveyed through a node at an end of the inductor  114   g . The currents Ic and Id may be conveyed through a node at an end of the inductor  114   g  connected to the inductor  114   h . The currents Ie and If are generally conveyed through a node at an end of the inductor  114   h  connected to the inductor  114   i . The signal OUT may be generated at the output node  116  based on the currents Ia to If. 
     Each inductor  104   a  and  104   n  may have a fixed inductance value (e.g., 0.2 nH). The other inductors  104   b - 104   f  may have a different fixed inductance value (e.g., 0.4 nH). Other inductance values (e.g., 0.1 to 1 nH) for the inductors  104   a - 104   n  may be implemented to meet the criteria of a particular application. In some embodiments, the inductor (e.g.,  114   i ) connected directly to the output node  116  may be eliminated (e.g., zero inductance). The resistor  106   c  may have a fixed resistance (e.g., 50Ω). Other resistance values (e.g., 5 to 200Ω) may be implemented to meet the criteria of a particular application. 
     Each circuit  108   a - 108   f  may be implemented as a distributed section. The circuits  108   a - 108   f  are generally operational to generate the currents Ia to If by transconductance amplification of the corresponding voltages Va to Vf. The circuits  108   a - 108   f  are represented in the figure as voltage controlled current sources with transconductance values (e.g., 50 mS). Each circuit  108   a - 108   f  may have the input parasitic capacitance (e.g., 0.16 pF) connected to a corresponding node of the input transmission line. Each circuit  108   a - 108   f  may have the output parasitic shunt capacitance (e.g., 0.02 pF) connected to a corresponding node of the output transmission line. Other transconductance values (e.g., 0.01 to 0.5 Siemens), input parasitic capacitance values (e.g., 0.05 to 0.5 pF) and/or other output parasitic capacitance values (e.g., 0.01 to 0.1 pF) may be implemented to meet the criteria of a particular application. The six circuits  108   a - 108   h  may form three pairs (e.g.,  108   a - 108   b ,  108   c - 108   d  and  108   e - 108   f ) that correspond to three of the nodes of the output transmission line. 
     The inductor  114   g  may have a fixed inductance value (e.g., 0.46 nH). The inductor  114   h  may have a different fixed inductance value (e.g., 0.16 nH). The inductor  114   i  may have yet a different inductance value (e.g., 0.068 nH). Other inductance values (e.g., 0.01 to 0.5 nH) for the inductors  114   g - 114   i  may be implemented to meet the criteria of a particular application. The inductance values are generally “tapered” as seen moving toward the output node  116 . The taper results in smaller inductance values closer to the output node  116  and larger inductance values further from the output node  116 . The taper may also results in larger capacitance values closer to the output node  116  and smaller capacitance values further from the output node  116 . The tapered impedance values along the output transmission line generally cancel a given current traveling away from the output node  116 . Therefore, the output transmission line may lack a termination resistance connected to the inductor  114   a  due to the cancellation of the current. 
     Referring to  FIG. 6 , a block diagram of an apparatus  150  is shown. The apparatus (or circuit, device, component or integrated circuit)  150  may implement a non-uniform distributed transconductance amplifier. The circuit  150  may be a variation of the circuits  100 ,  120 ,  130  and/or  140 . The distribution technique may be applied to amplifiers with more sections (e.g., eight sections), as shown in the apparatus  150 . 
     The circuit  150  generally comprises the input node  102 , the inductors  104   a - 104   n , the termination resistor  106   a , multiple blocks (or circuits)  108   a - 108   h , multiple inductors  114   j - 114   m , the output node  116  and multiple blocks (or circuits)  117   j - 117   m . The inductors  104   a - 104   n  and the resistor  106   a  may be connected in series to form the input transmission line. The inductors  114   j - 114   m  may be connected in series to form the output transmission line. The elements  104   a  to  114   m  may be implemented in hardware. Multiple (e.g., four) capacitors  117   j - 117   m  (e.g., 0.032 pF, 0.21 pF, 0.36 pF and 0.49 pF, respectively) may be connected between the nodes of the output transmission lines and the signal ground. Other capacitance values (e.g., 0.01 to 0.7 pF) may be implemented to meet the criteria of a particular application. 
     Each inductor  104   a  and  104   n  may have a fixed inductance value (e.g., 0.2 nH). The inductors  104   b - 104   f  may have a different fixed inductance value (e.g., 0.4 nH). Other inductance values (e.g., 0.1 to 1 nH) for the inductors  104   a - 104   n  may be implemented to meet the criteria of a particular application. 
     Each circuit  108   a - 108   h  may be implemented as a distribution section. The circuits  108   a - 108   h  are generally operational to generate the currents Ia to Ih by transconductance amplification of the corresponding voltages Va to Vh. The circuits  108   a - 108   h  are represented in the figure as voltage controlled current sources with transconductance values (e.g., 50 mS). Each circuit  108   a - 108   h  may have the input parasitic capacitance (e.g., 0.16 pF) connected to a corresponding node of the input transmission line. Each circuit  108   a - 108   h  may have the output parasitic shunt capacitance (e.g., 0.02 pF) connected to a corresponding node of the output transmission line. Other transconductance values (e.g., 0.01 to 0.5 Siemens), input parasitic capacitance values (e.g., 0.05 to 0.5 pF) and/or other output parasitic capacitance values (e.g., 0.01 to 0.1 pF) may be implemented to meet the criteria of a particular application. The eight circuits  108   a - 108   h  may form four pairs (e.g.,  108   a - 108   b ,  108   c - 108   d ,  108   e - 108   f  and  108   g - 108   h ) that correspond to four of the nodes of the output transmission line. 
     The inductor  114   j  may have a fixed inductance value (e.g., 0.80 nH). The inductor  114   k  may have a different fixed inductance value (e.g., 0.27 nH). The inductor  114   l  may have yet a different inductance value (e.g., 0.15 nH). The inductor  114   m  generally has a different inductance value (e.g., 0.079 nH). Other inductance values (e.g., 0.01 to 0.5 nH) for the inductors  114   j - 114   m  may be implemented to meet the criteria of a particular application. The inductance values are generally “tapered” as seen moving toward the output node  116 . The taper results in smaller inductance values closer to the output node  116  and larger inductance values further from the output node  116 . The taper may also results in larger capacitance values closer to the output node  116  and smaller capacitance values further from the output node  116 . The tapered impedance values along the output transmission line generally cancel a given current traveling away from the output node  116 . Therefore, the output transmission line may lack a termination resistance connected to the inductor  114   j  due to the cancellation of the current. 
     Referring to  FIG. 7 , a graph  160  of simulated transconductance curves is shown. Each curve  162 - 170  generally presents the transconductance (e.g., in units of Siemens) of a corresponding circuit  90 ,  100 ,  140  and  150  over a frequency range (e.g., 0.1 to 50.1 gigahertz GHz). The simulations are made using the typical values of transconductance, capacitance, inductance, and resistance that have been presented. The curve  162  may represent a transconductance amplifier (e.g., the amplifier  90 ) having four constant (or uniform) sections. The curve  164  generally represents a transconductance amplifier having four tapered sections. 
     The curve  166  generally represents a transconductance amplifier (e.g., the circuit  100 ) having four paired tapered sections. The curve  166  shows an improvement in gain and bandwidth over the curves  162  and  164  up to a frequency of approximately 35 GHz. 
     The curve  168  generally represents a transconductance amplifier (e.g., the circuit  140 ) having six paired tapered sections. The curve  168  shows an improvement in gain over the curves  162 ,  164  and  166  up to a frequency of approximately 35 GHz. 
     The curve  170  generally represents a transconductance amplifier (e.g., the circuit  150 ) having eight paired tapered sections. The curve  170  shows an improvement in gain over the curves  162 ,  164 ,  166  and  168  up to a frequency of approximately 35 GHz. 
     Beyond the added bandwidth of paired section outputs, an additional benefit is generally realized when the connections of the paired sections are applied to non-uniform distributed amplifiers. The circuit  100  may have no changes to the input transmission line, a number of transistors, or an output impedance relative to the circuit  120 . However, a range of the impedance tapering is generally reducible from 4:1 down to 2.95:1. Furthermore, fewer passive elements with lower total values may be used in the design. The total inductance in the output transmission line of the circuit  100  may be reduced from 0.59 nH down to 0.26 nH compared with the circuit  120 , while the total shunt capacitance is reduced from 1.6 pF down to 0.66 pF, representing 56% and 59% reductions, respectively. The reductions generally provide advantages of reduced circuit area and reduced loss in addition to the enhanced bandwidth. 
     Referring to  FIG. 8 , schematics of several example implementations of the active loads are shown. The active load circuit elements (e.g., the circuits  110   a - 110   d ) may be constructed with multiple transistor types (e.g., field effect transistors, bipolar transistors, high-electron mobility transistors, etc.) in multiple technologies (e.g., silicon, gallium arsenide, silicon germanium, etc.) An example implementation may be a block (or circuit)  172  having an N-channel depletion mode field effect transistor with a gate tied to a source. Another example implementation may be a block (or circuit)  174  having a bipolar transistor with a resistor connected to a base. A further example implementation may be a block (or circuit)  176  having a field effect transistor with the gate connected to the source via a capacitor. The circuits  172 - 176  generally operate as current sources with a finite output resistance and a parasitic shunt capacitance. Because the capacitances are absorbed into the output transmission line, the parasitic capacitances do not limit a bandwidth of the amplifier and may be extended to an arbitrarily low frequency (e.g., a few hundred kilohertz) and an arbitrary high frequency (e.g., tens of gigahertz) with a proper choice of support passives like capacitors and inductors. 
     Referring to  FIG. 9 , a schematic of an example implementation of a circuit  110   n  is shown. The circuit  110   n  may be representative of one or more of the active loads represented by the circuits  110   a - 110   d . The circuit  110   n  generally comprises a block (or circuit)  117   n , one or more blocks (or circuits)  182   a - 182   h , one or more blocks (or circuits)  184   a - 184   h  and a block (or circuit)  186 . The signal VD may be received by a node of each circuit  182   a - 182   h . A bias signal (e.g., VBIAS) may be received by a node of the circuit  186 . The signal VBIAS generally provides a bias voltage that is used to control the amount of current passing through the circuits  182   a - 182   h . An output current signal (e.g., I) may be generated by a combination of the circuits  182   a - 182   h . The signal I is generally applied to a node of the output transmission line  115 . 
     Each circuit  182   a - 182   h  may be implemented as a transistor. The transistors  192   a - 182   h  are generally wired in parallel between a drain node that receives the signal VD and a source node that presents the signal I. In some embodiments, the transistors  182   a - 182   h  may be implemented as N-channel depletion mode field effect transistors. Other transistor technologies may be implemented to meet the criteria of a particular application. 
     Each circuit  184   a - 184   h  may be implemented as a resistive element (e.g., a resistor). Each resistor  184   a - 184   h  is connected between the circuit  186  and a respective gate of the circuits  182   a - 182   h . In some embodiments, the resistors  184   a - 184   h  each have a resistance (e.g., 50Ω). Other resistor values (e.g., 2 to 200Ω) may be implemented to meet the criteria of a particular application. 
     The circuit  186  may be implemented as a resistive element (e.g., a resistor). The resistor  186  generally limits an amount of current drawn by the gates of the transistors  182   a - 182   h.    
     The circuit  117   n  may be implemented as a capacitive element (e.g., a capacitor). The capacitor  117   n  generally provides an AC bypass for the voltage signals presented to the transistor gates. The capacitor  117   n  generally AC couples the gate bias voltage to the source voltage of the transistors  182   a - 182   h . The capacitor  117   n  may be representative of the capacitors  117   a  to  117   m.    
     The capacitor  117   n  may help ensure proper operation of the gate-source junctions of the transistors  182   a - 182   h . To avoid stability issues at high frequencies, the resistors  184   a - 184   h  are connected to each gate to de-Q the AC bypass and minimize any connection inductance caused by lines (or traces) to the transistor gates. In some embodiments, one end of the capacitor  117   n  is connected with short metal lines to each individual resistor  184   a - 184   h . The other end of the capacitor  117   n  may be connected with short metal lines to each individual source of the transistors  182   a - 182   h . As illustrated, multiple (e.g.,  8 ) transistors/resistor sets may be implemented. Other numbers of transistors/resistor sets may be implemented to meet the criteria of a particular application. 
     In some embodiments (e.g.,  FIGS. 2-6 ,  8  and  9 ), the active loads may be inserted at all section output nodes (as shown) or mixed with passive compensation, such as simple shunt capacitors, at the nodes. Varying shunt capacitances on the output transmission line may be implemented with active bias circuits of varying size. The transistors of the active loads, represented as voltage controlled current sources with input and output capacitances, may be implemented with many different technologies and with many different transistor configurations. 
     The distributed amplifiers may be designed with similar impedances at the input node and the output node (typically 50Ω). Furthermore, the distributed amplifiers provide broadband current into lower impedance loads for applications including, but not limited to, laser diode drivers and power amplifiers. The integrated transconductance amplifiers generally provide high transconductance, occupy small die area and/or include bias injection circuits. 
     The functions and structures illustrated in the diagrams of  FIGS. 1-6 ,  8  and  9  may be designed, modeled and simulated using one or more of a conventional general purpose processor, digital computer, microprocessor, microcontroller and/or similar computational machines, programmed according to the teachings of the present specification, as will be apparent to those skilled in the relevant art(s). Appropriate software, firmware, coding, routines, instructions, opcodes, microcode, and/or program modules may readily be prepared by skilled programmers based on the teachings of the present disclosure, as will also be apparent to those skilled in the relevant art(s). The software is generally executed from a medium or several media by one or more of the processors. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the invention.