Abstract:
A digital to analog converter having a pair of resistor strings. A first one of the resistor strings is adapted for coupling across a voltage supply. Resistors in the first resistor string produce voltages in response to current fed thereto from the voltage supply. A first switching network couples a voltage produced across a selected one of resistors in the first string across the second resistor string. The resistors in the second resistor string produce voltages in response to current passing from the first resistor string to the second resistor string through the first switching network. That is, the second resistor string is unbuffered from the first resistor string. A second switching network couples a selected one of the voltages produced at a selected one of the resistors in the second resistor string to an output. The resistance across the second resistor string is larger than the resistance of the selected one of the resistors in the first resistor string thereby reducing the loading effect of the second resistor string without requiring buffer amplifiers between the pair of resistor strings. In a preferred embodiment of the invention the resistances of the second mentioned string and the switching networks are selected to produce a step change of substantially one LSB, where LSB is the least significant bit of a digital word converted by the converter.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates generally to digital to analog converters (DACs) and more particularly to resistor string type DACs adapted for integrated circuit fabrication. 
     As is known in the art, DACs have been used in a wide variety of applications to convert an N-bit digital word into a corresponding analog signal. One such DAC includes a string of 2 N  resistors having substantially the same resistance serially connected across a reference voltage. Thus, the resistor string divides the reference voltage among the resistors in the string. A switching network is provided for coupling the voltage at one of the resistors to an output to produce the converted voltage. While such DAC is suitable for applications where N is relatively small, when N is large, for example, where N is in the order of twelve, 4,096 resistors, 4,096 switches, and 4,096 control lines are required thereby resulting in a relatively large number of elements to be fabricated on an integrated circuit chip. 
     One technique suggested to reduce the number of elements is to use a segmented converter. In a segmented converter, a first stage uses a resistor string for converting a group of higher order bits of the N-bit digital word and a second stage decodes the remaining, lower order bits. A non-linear converter of that general type is shown in an article by Gryzbowski et al., entitled &#34;Non-liner Functions from D/A Converters&#34;, Electronic Engineering 1971, pgs. 48-51. The converter disclosed in that article is designed for operation with relay switching and is not readily adapted to modern semiconductor technology. Another segmented converter is described in U.S. Pat. No. 3,997,892, issued December 1976, inventor Susset. The segmented converter described in U.S. Pat. No. 4,543,560 includes a resistor string for both the first and second stages with buffer amplifiers between the stages to prevent the second stage resistor string from loading the first resistor string. 
     Still another type of segmented converters is described in U.S. Pat. No. 4,338,591 issued Jul. 6, 1982, inventor Michael G. Tuthill, assigned to the same assignee as the present invention. Here, a resistor string is used for the first stage, an R-2R DAC is used for the second stage and buffer amplifiers are used between the first and second stages to reduce the effect of loading by the second stage on the first stage. The voltage produced across a selected one of the resistors in the first resistor string is fed across the second resistor string through the buffer amplifiers. 
     A third type of segmented DAC is described in U.S. Pat. No. 5,495,245, issued Feb. 27, 1996, inventor James J. Ashe, assigned to the same assignee as the present invention. The DAC described therein includes a pair of first stage resistor strings coupled to a second resistor string through a first switching network. A pair of reference voltages are coupled to the pair of resistor strings. The first switching network operates such that a voltage produced at a selected one of the resistors in one of the pair of first stage resistor strings and a voltage produced at a selected one of the resistors in the other one of the pair of first resistor strings are coupled across the second stage resistor string. A second switching network couples an output at a selected one of the resistors in the second resistor string to an output of the DAC. Buffer amplifiers are not included between the pair of first stage resistor strings and the second stage resistor string. Two arrangements are described. In one arrangement, the first switching network responds to the MSBs and the second switching network responds to the LSBs. In the other arrangement, the first switching network responds to the LSBs and the second switching network responds to the MSBs. In former arrangement, each resistor in the pair of resistor strings has a value 2 N  R, where R is the resistance of each of the 2 N/2  resistors in the second resistor string. In the latter arrangement, each resistor in the second resistor string has a value 2 N/2  R, where R is the resistance of each resistor in the pair of first resistor strings. In both arrangements, the entire current passing between the pair of reference voltages passes through the resistors. Therefore, while such arrangements are useful in many applications the relatively high number of resistors which are required in both the first and second pairs of resistor strings thereby requiring relative large chip surface area for their fabrication. 
     SUMMARY OF THE INVENTION 
     In accordance with the invention a digital to analog converter is provided having a pair of resistor strings. A first one of the resistor strings is adapted for coupling across a voltage supply. The resistors in the first resistor string produce voltages in response to current fed thereto from the voltage supply. The second string of resistors has a plurality of, only m, resistors of substantially equal resistance serially coupled between a pair of second resistor string input terminals, where m is an odd integer. A first switching network has a pair of switch output terminals connected to the second resistor string input terminals. The first switching network is adapted to couple terminals of a selected one of the resistors in the first string to the pair of switch output terminals. The resistors in the second resistor string produce voltages in response to current passing between the first resistor string and the second resistor string through the first switching network. A second switching network is adapted to couple a selected one of the voltages produced at a terminal of a selected one of the resistors in the second resistor string to an output of the converter. The resistance across the second resistor string is larger than the resistance of the selected one of the resistors in the first resistor string. 
     In a preferred embodiment of the invention the resistances of the second mentioned string and resistance of the first switching network, are selected to produce a step change of substantially one LSB at the converter output, where LSB is the least significant bit of a digital word converted by the converter, when the first switching network switches from coupling one of the selected first resistors to the pair of output terminals to coupling the one of the first resistors successively serially coupled to the selected first resistors to the output terminals thereof. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     Other features of the invention, as well as the invention itself, will become more readily apparent with reference to the following detailed description taken together with the following drawings, in which: 
     FIG. 1 is a schematic diagram of a four bit digital to analog converter (DAC) according to the invention; 
     FIG. 2 is a table showing the relationship between the four bit digital words fed to the DAC of FIG. 1 and open/closed positions of switches used in such DAC; 
     FIG. 3 is a schematic diagram of the DAC of FIG. 1 when such DAC is fed a digital word having its two most significant bits 00 and a table showing the relationship between the two least significant bits of such digital word and open/closed positions of switches used in such DAC; 
     FIG. 4 is a schematic diagram of the DAC of FIG. 1 when such DAC is fed a digital word having it&#39;s two most significant bits 01 and a table showing the relationship between the two least significant bits of such digital word and open/closed positions of switches used in such DAC; 
     FIG. 5 is a schematic diagram of the DAC of FIG. 1 when such DAC is fed a digital word having its two most significant bits 10 and a table showing the relationship between the two least significant bits of such digital word and open/closed positions of switches used in such DAC; 
     FIG. 6 is a schematic diagram of the DAC of FIG. 1 when such DAC is fed a digital word having its two most significant bits 11 and a table showing the relationship between the two least significant bits of such digital word and open/closed positions of switches used in such DAC; 
     FIG. 7 is a schematic diagram of a twelve bit digital to analog converter (DAC) according to the invention; 
     FIG. 8 is a table showing the relationship between the six most significant bits of the twelve bit digital words fed to the DAC of FIG. 7 and open/closed positions of switches used in such DAC; 
     FIG. 9 is a table showing the relationship between the seven least significant bits of the twelve bit digital words fed to the DAC of FIG. 7 and open/closed positions of switches used in such DAC; 
     FIG. 10 is a schematic diagram of the DAC of FIG. 1 when the most significant bits of the digital word fed thereto is 10 as in FIG. 5 and showing the effect of non-zero resistance of switches when such switches are in a closed (i.e., conducting condition); and 
     FIG. 11 is a schematic diagram of the DAC of FIG. 7 when the six most significant bits of the digital word fed thereto are 000001 and showing the effect of non-zero resistance of switches when such switches are in a closed (i.e., conducting condition). 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring now to FIG. 1, a DAC 10 is shown to adapted to convert an N bit, here N=4, digital word, I 4  I 3  I 2  I 1 , (where bit I 1  is the least significant bit (LSB) and I 4  is the most significant bit (MSB)) into a corresponding analog signal, V o , at output terminal 11. The DAC 10 includes a pair of resistor strings 12, 14. Resistor string 12 is adapted for coupling across a voltage supply 15. The voltage supply 15 produces a voltage, +V, at terminal 16 relative to ground potential at terminal 18. The first resistor string has a plurality of, here 2 N/2 , (i.e., 4) resistors Ra1-Ra4, serially connected between terminals 16 and 18, as shown. The resistance of each one of the resistors Ra1-Ra4 is here R 1  ohms. It is noted that resistors Ra1, Ra2, Ra3 and Ra4 have: resistor ra1 terminals T 0 , T 1  ; resistor ra2 terminal T 1 , T 2  ; resistor Ra3 terminals T 2  and T 3  ; and, resistor Ra4 terminals T 3  and T 4 , respectively, as shown. Resistor Ra4 terminal T 4  is connected to terminal 16 and resistor Ra1 terminal T 0  is connected to input terminal 18, as shown. The resistors Ra1-Ra4 in the resistor string 12 produce voltages at the terminals T 1  -T 3  in response to current fed thereto from the voltage supply 15. 
     The second resistor string 14 has a plurality of, only 2 N/2  -1, here three resistors Rb1, Rb2, and Rb3 of substantially equal resistance, here a resistance of R 2  ohms, serially coupled between a pair of second resistor string 14 input terminals 26, 28, as shown. (It is noted that 2 N/2  -1) is an odd integer.) Resistors Rb1, Rb2 and Rb3 have: resistor Rb1 terminals Q1, Q2, resistor Rb2 has resistor terminals Q2, Q3, and resistor Rb3 has resistor terminals Q3, Q4, respectively, as shown. Terminal Q 1  is connected to input terminal 28 and terminal Q 4  is connected to input terminal 26. 
     A first switching network 34 has a pair of switch output terminals 36, 38 connected to the second resistor string 14 input terminals 26, 28, respectively, as shown. The first switching network 34 includes a plurality of, here 2 N/2  +1, here five, switches SM 0 , SM 1 , SM 2 , SM 3  and SM 4 . The inputs of switches SM 0 , SM 1 , SM 2 , SM 3  and SM 4  are connected to terminals T 0 , T 1 , T 2 , T 3  and T 4 , respectively, as shown. The outputs of switches SM 0 , SM 2 , and SM 4  are connected switch output terminal 38, as shown. The outputs of switches SM 1  and SM 3  are connected to switch output terminal 36, as shown. The &#34;on&#34; (i.e., closed)/&#34;off&#34; (i.e., open) condition of the switches SM 0 , SM 1 , SM 2 , SM 3  and SM 4  is controlled by binary (i.e., logic) signals on control lines C 0 , C 1 , C 2 , C 3  and C 4 , respectively, as indicated. The binary signals on control lines C 0 , C 1 , C 2 , C 3  and C 4 , are produced by a Most Significant Bit (MSB) decoder section 40. The MSB decoder section 40 produces the binary signals on control lines C 0  -C 4  in response to the two most significant bits, I 4 , I 3  of the four bit digital word I 4  I 3  I 2  I 1  being converted to an analog signal by DAC 10. The relationship between the bits on lines I 4  and I 3  and the open/closed condition of the switches SM 0 , SM 1 , SM 2 , SM 3  is shown in FIG. 2. The MSB decoder section 40 here uses Gray code decoding. 
     A second switching network 42 has an output terminal 11 which provides the output, V o , for the DAC 10 (i.e., the converted analog signal). The second switching network 42 includes a plurality of, 2 N/2 , here four, switches SL 0 , SL 1 , SL 2 , and SL 3 . The inputs of switches SL 0 , SL 1 , SL 2 , and SL 3  are connected to terminals Q 1 , Q 2 , Q 3 , and Q 4 , respectively, as shown. The outputs of switches SL 0 , SL 1 , SL 2  and SL 3  are connected to DAC 10 output terminal 11, as shown. The &#34;on&#34; (i.e., closed)/&#34;off&#34; (i.e., open) condition of the switches SL 0 , SL 1 , SL 2 , and SL 3  is controlled by binary (i.e., logic) signals on control lines D 0 , D 1 , D 2 , and D 3 , respectively, as indicated. The binary signals on control lines D 0 , D 1 , D 2 , and D 3 , are produced by a Least Significant Bit (LSB) decoder section 46. The LSB decoder section 46 includes an LSB decoder 48 and a multiplexer 50. The LSB decoder section 46 is fed by the two least significant bits I 2 , I 1  and the digital word being converted by the DAC 10 and the next highest order bit, i.e., bit I 3  of such digital word. 
     More particularly, the LSB decoder 48 is fed by the two least significant bits I 2  and I 1  and, in response to such bits, produces binary signals at output terminals A 0 , A 1 , A 2  and A 3 . The output terminals A 0 , A 1 , A 2  and A 3  are connected to two sets of inputs to the multiplexer 50 (i.e., set of inputs A and set of inputs B. The multiplexer 50 has output terminals D 0 , D 1 , D 2  and D 3 . In response to the binary signal of bit I 3  one of the two input sets A or B is selectively coupled to the output terminals D 0 , D 1 , D 2  and D 3 . More particularly, when the binary signal of bit I 3  is logic 0, the output terminals A 0 , A 1 , A 2  and A 3  become coupled to output terminals D 0 , D 1 , D 2  and D 3 , respectively, as indicated by the solid lines 52 shown in multiplexer 50. When the binary signal of bit I 3  is logic 1, the output terminals A 3 , A 2 , A 1  and A 0  become coupled to output terminals D 3 , D 2 , D 1  and D 0 , respectively, as indicated by the dotted lines 54 shown in multiplexer 50 after passing through inverters 51 3 , 51 2 , 51 1 , 51 0 , respectively, as shown. Thus, the LSB decoder section 46 produces the binary signals on control lines D 0  -D 3  in response to the three least significant bits, I 3 , I 2 , I 1  of the four bit digital word I 4  I 3  I 2  I 1  being converted in an analog signal by DAC 10. The relationship between the bits on lines I 3 , I 2  and I 1  and the open/closed condition of the switches SL 0 , SL 1 , SL 2 , SL 3  is shown in FIG. 2. 
     It is first noted that the first switching network 34 is adapted to couple terminals of a selected one of the resistors Ra1-Ra4 in the first resistor string 12 to the pair of switch output terminals 36, 38. The resistors Rb1-Rb4 in the second resistor 14 string produce voltages at the terminals Q 1  -Q 4  in response to current passing between the first resistor string 12 and the second resistor string 14 through the first switching network 34. The second switching network 42 is adapted to couple a selected one of the voltages produced at a resistor terminal Q 1  -Q 4  of a selected one of the resistors Rb1-Rb3 in the second resistor string 14 to the output terminal 11 of the converter 10. 
     In operation, consider as a first example, a condition where two most significant bits (i.e., I 4  I 3 ) of the digital word, I 4  I 3  I 2  I 1 , fed to the decoder section 40 are 00. From FIG. 2, switches SM 0  and SM 1  are closed while switches SM 2 , SM 3  and SM 4  are open, as shown in FIG. 3. Thus, the terminals T 1  and T 0  are coupled to terminals 36, 38, respectively, through switches SM 1 , SM 0 , respectively, as shown. In this example, the resistance R 1  equals the resistance R 2 . Further, assume an ideal case where the resistance of each of the switches SM 1 , SM 0  is zero. The resistance between terminals T 0  and T 1  is: 
     
         R.sub.p =R.sub.1 [3R.sub.2 ]/[R.sub.1 +3R.sub.2 ]. 
    
     Thus, if R 1  =R 2 , R p  =3R 1  /4. The voltage at terminal T 0  is ground (i.e., zero volts). The voltage at terminal T 1  is: 
     
         V[R.sub.p ]/[3R.sub.1 +R.sub.p ]. 
    
     Thus, if R 1  =R 2 , the voltage at terminal T 1  is 3 V/15. 
     To put it another way, the first resistor string 12 divides the voltage V among the 2 N/2  (i.e., here four) resistors Ra1-Ra2 N/2  (i.e., here Ra1-Ra4) in combination with the loading effect of a second resistor string 14 and the resistance of the first switching network 12. 
     When the digital word I 4  I 3  I 2  I 1  being converted is 0000 (i.e., bits I 2  and I 1  are also both logic 0), an output voltage V o  is produced at output terminal 11 of 0 volts because switch SL 0  is closed (and all other switches SL 1 , SL 2  and SL 3  are open). When the digital word I 4  I 3  I 2  I 1  being converted is 0001 (i.e., bits I 2  is logic 0 and bit I 1  is logic 1) the output voltage V o  produced at output terminal 11 is V/15 because: The voltage at terminal T D  is zero; The voltage at terminal T A  is 3 V/15; Switch SL 1  is closed; and all other switches SL 0 , SL 2  and SL 3  are open. When the digital word I 4  I 3  I 2  I 1  being converted is 0010 (i.e., bit I 2  is logic 1 and bit I 1  is logic 0), an output voltage V o  is produced at output terminal 11 of 2[V/15] volts because switch SL 0  is closed (and all other switches SL 1 , SL 2  and SL 0  are open). When the digital word I 4  I 3  I 2  I 1  being converted is 0011 (i.e., bits I 1  and I 2  are both logic 1) the output voltage V o  produced at output terminal 11 is 3[V/15] because switch SL 3  is closed (and all other switches SL 0 , SL 1  and SL 2  are open). 
     Considering now a condition where two most significant bits (i.e., I 4  I 3 ) of the digital word, I 4  I 3  I 2  I 1 , fed to the decoder sections 40, 46 are 01 (i.e., I 3  =1 and I 4  =0). From FIG. 2, switches SM 1  and SM 2  are closed while switches SM 0 , SM 3  and SM 4  are open, as shown in FIG. 4. Thus, the terminals T 2  and T 1  are connected to terminals 36, 38, respectively, through switches SM 2 , SM 1 , respectively, as shown. As noted above, here the resistance R 1  equals the resistance R 2 . Further, again assuming an ideal case where the resistance of each of the switches SM 2 , SM 1  is zero. The voltage at terminal T 1  will be 4 V/15 and the voltage at terminal T 2  will be 7 V/15. (It is noted that the voltage at terminal T 1  has changed a step of V/15 (i.e., one LSB) from the 3 V/15 volt condition at terminal T 1  in the configuration shown in FIG. 3 to now 4 V/15). 
     When the digital word I 4  I 3  I 2  I 1  being converted is 0100 (i.e., bits I 2  and I 1  are also both logic 0), an output voltage V o  is produced at output terminal 11 of 4[V/15] volts because switch SL 3  is closed (and all other switches SL 0 , SL 2  and SL 3  are open). When the digital word I 4  I 3  I 2  I 1  being converted is 0101 (i.e., bits I 2  is logic 0 and bit I 1  is logic 1) the output voltage V o  produced at output terminal 11 is 5[V/15] because switch SL 2  is closed (and all other switches SL 0 , SL 1  and SL 3  are open). When the digital word I 4  I 3  I 2  I 1  being converted is 0110 (i.e., bit I 2  is logic 1 and bit I 1  is logic 0), an output voltage V o  is produced at output terminal 11 of 6[V/15] volts because switch SL 1  is closed (and all other switches SL 0 , SL 2  and SL 3  are open). When the digital word I 4  I 3  I 2  I 1  being converted is 0111 (i.e., bits I 1  and I 2  are both logic 1) the output voltage V o  produced at output terminal 11 is 7[V/15] because switch SL 0  is closed (and all other switches SL 1 , SL 2  and SL 3  are open). 
     When the two most significant bits (i.e., I 4  I 3 ) of the digital word, I 4  I 3  I 2  I 1 , fed to the decoder section 40, 46 are 10 (i.e., I 4  =1 and I 3  =0) . From FIG. 2, switches SM 2  and SM 3  are closed while switches SM 0 , SM 1  and SM 4  are open, as shown in FIG. 5. Thus, the terminals T 2  and T 3  are connected to terminals 38, 36, respectively, through closed switches SM 2 , SM 3 , respectively, as shown. Assume an ideal case where the resistance of each of the switches SM 2 , SM 3  is zero. The voltage at terminal T 2  will be 8 V/15 and the voltage at terminal T 3  will be 11 V/15. (It is noted that the voltage at terminal T 2  has changed a step of V/15 (i.e., one LSB) from the 7 V/15 volt condition at terminal T 2  in the configuration shown in FIG. 4 to the 8 V/15 condition in FIG. 5). 
     When the digital word I 4  I 3  I 2  I 1  being converted is 1000 (i.e., bits I 2  and I 1  are also both logic 0), an output voltage V o  is produced at output terminal 11 of 8[V/15] volts because switch SL 0  is closed (and all other switches SL 1 , SL 2  and SL 3  are open). When the digital word I 4  I 3  I 2  I 1  being converted is 1001 (i.e., bits I 2  is logic 0 and bit I 1  is logic 1) the output voltage V o  produced at output terminal 11 is 9[V/15] because switch SL 1  is closed (and all other switches SL 0 , SL 2  and SL 3  are open). When the digital word I 4  I 3  I 2  I 1  being converted is 1010 (i.e., bit I 2  is logic 1 and bit I 1  is logic 0), an output voltage V o  is produced at output terminal 11 of 10[V/15] volts because switch SL 2  is closed (and all other switches SL 0 , SL 1  and SL 3  are open). When the digital word I 4  I 3  I 2  I 1  being converted is 1011 (i.e., bits I 1  and I 2  are both logic 1) the output voltage V o  produced at output terminal 11 is 11[V/15] because switch SL 3  is closed (and all other switches SL 0 , SL 1  and SL 2  are open). 
     When the two most significant bits (i.e., I 4  I 3 ) of the digital word, I 4  I 3  I 2  I 1  fed to the decoder section 40, 46 are 11. From FIG. 2, switches SM 4  and SM 3  are closed while switches SM 0 , SM 1  and SM 2  are open, as shown in FIG. 6. Thus, the terminals T 3  and T 4  are connected to terminals 36, 38, respectively, through switches SM 3 , SM 4 , respectively, as shown. As noted above, here the resistance R 1  equals the resistance R 2 . Further, again assume an ideal case where the resistance of each of the switches SM 3 , SM 4  is zero. The voltage at terminal T 3  will be 12 V/15 and the voltage at terminal T 4  will be V. (It is noted that the voltage at terminal T 3  has changed a step of V/15 (i.e., one LSB) from the 11 V/15 volt condition at terminal T 3  in the configuration shown in FIG. 5 to the 12 V/15 condition in FIG. 5. 
     When the digital word I 4  I 3  I 2  I 1  being converted is 1100 (i.e., bits I 2  and I 1  are also both logic 0), an output voltage V o  is produced at output terminal 11 of 12[V/15] volts because switch SL 3  is closed (and all other switches SL 0 , SL 1  and SL 2  are open) . When the digital word I 4  I 3  I 2  I 1  being converted is 1101 (i.e., bits I 2  is logic 0 and bit I 1  is logic 1) the output voltage V o  produced at output terminal 11 is 13[V/15] because switch SL 2  is closed (and all other switches SL 0 , SL 1  and SL 3  are open). When the digital word I 4  I 3  I 2  I 1  being converted is 1110 (i.e., bit I 2  is logic 1 and bit I 1  is logic 0), an output voltage V o  is produced at output terminal 11 of 14[V/15] volts because switch SL 1  is closed (and all other switches SL 0 , SL 2  and SL 3  are open). When the digital word I 4  I 3  I 2  I 1  being converted is 1111 (i.e., bits I 2  and I 2  are both logic 1) the output voltage V o  produced at output terminal 11 is 15[V/15]=V because switch SL 0  is closed (and all other switches SL 1 , SL 2  and SL 3  are open) 
     Thus, it is noted that when the N=4 bit digital word I 4  I 3  I 2  I 1  changes (i.e., increases or decreases) by one least significant bit, the output voltage, V o , at terminal 11 changes (i.e, increases or decreases) a step of one LSB (i.e., the output at terminal 11 changes V/[2 N  -1]=V/15. 
     It is noted that if the desired range of the output voltage at terminal 11 is to be from zero to 15[V/16], an additional resistor (i.e., a gain setting resistor) of, in the example above, of R 1  /4 is inserted serially between the terminal 16 and the terminal T 4  in FIG. 1. With such an additional resistor, the relationship between the bits of the input digital word I 4  I 3  I 2  I 1  and the output voltage is as follows: 
     
         ______________________________________I.sub.4 I.sub.3 I.sub.2 I.sub.1      Output Voltage, V.sub.0 (volts)______________________________________0000       00001       V/160010        2 [V/16]0011        3 [V/16]0100        4 [V/16]0101        5 [V/16]0110        6 [V/16]0111        7 [V/16]1000        8 [V/16]1001        9 [V/16]1010       10 [V/16]1011       11 [V/16]1100       12 [V/16]1101       13 [V/16]1110       14 [V/16]1111       15 [V/16]______________________________________ 
    
     Thus, with the additional resistor, when the N=4 bit digital word I 4  I 3  I 2  I 1  changes (i.e., increases or decreases) by one least significant bit, the output voltage, V 0 , at terminal 11 changes (i.e., increases or decreases) an LSB step (i.e., changes V/[2 N  ]=V/16). 
     Referring now to FIG. 7, an N=12 bit DAC 10&#39; is shown to adapted to convert a twelve bit digital word, I&#39; 12  I&#39; 11  . . . I&#39; 2  I&#39; 1 , (where bit I&#39; 1  is the least significant bit (LSB) and I&#39; 12  is the most significant bit (MSB)) into a corresponding analog signal, V o  &#39;, at output terminal 11&#39;. The DAC 10&#39; includes a pair of resistor strings 12&#39;, 14&#39;. Resistor string 12&#39; is adapted for coupling across a voltage supply 15. The voltage supply 15 produces a voltage, +V, at terminal 16 relative to ground potential at terminal 18. The first resistor string 12&#39; has a plurality of, here 2 N/2 , i.e., 64 resistors R&#39;a1-R&#39;a[2 N/2  ], (i.e., R&#39;a1-R&#39;a64 serially connected between terminals 16 and 18, as shown. The resistance of each one of the resistors R&#39;a1-R&#39;a64 is here R&#39; 1  ohms. It is noted that resistors Ra&#39;1 . . . R&#39;a&#39;64 have: resistor Ra&#39;1 terminals T&#39; 0 , T&#39; 1  ; . . . and resistor R&#39;a64 terminals T&#39; 63  and T&#39; 64 , respectively, as shown. Resistor R&#39;al terminal T&#39; 0  is connected to terminal 18 and resistor R&#39;a64 terminal T&#39; 64  is connected to terminal 16, as shown. The resistors R&#39;1-R&#39;64 in the resistor string 12&#39; produce voltages in response to current fed thereto from the voltage supply 15. 
     The second resistor string 14&#39; has a plurality of, only 2 N/2  -1, here 63 resistors R&#39;b1, R&#39;b2, . . . R&#39;b63 of substantially equal resistance, here a resistance of R&#39; 2  ohms, serially coupled between a pair of second resistor string 14&#39; input terminals 26&#39;, 28&#39;, as shown. Further, it is again noted that if the number of bits of the digital word being converted is N, the number of resistors in the first resistor string 14&#39; is 2 N/2  and the number of resistors in the second resistor string 14&#39; is 2 N/2  -1. 
     Resistors R&#39;b1, . . . R&#39;b63 have: resistor R&#39;b1 terminals Q&#39; 1 , Q&#39; 2  . . . resistor R&#39;b63 terminals Q&#39; 63 , Q&#39; 64 , respectively, as shown. 
     A first switching network 34&#39; has a pair of switch output terminals 36&#39;, 38&#39; connected to the second resistor string 14&#39; input terminals 26&#39;, 28&#39;, respectively, as shown. The first switching network 34&#39; includes a plurality of, here 2 N/2  +1 (i.e., sixty-five) switches SM&#39; 0 , SM&#39; 1 , SM&#39; 2 , SM&#39; 3  . . . and SM&#39; 64 . The inputs of switches SM&#39; 0 , SM&#39; 1 , SM&#39; 2 , . . . SM&#39; 63  and SM&#39; 64  are connected to terminals T&#39; 0 , T&#39; 1 , T&#39; 2 , T&#39; 3  . . . and T&#39; 64 , respectively, as shown. The outputs of switches SM&#39; 0 , SM&#39; 2 , . . . and SM&#39; 64  are connected switch output terminal 38&#39;, as shown. The outputs of switches SM&#39; 1 , SM 3 , . . . SM&#39; 63  are connected to switch output terminal 36&#39;, as shown. The &#34;on&#34; (i.e., closed)/&#34;off&#34; (i.e., open) condition of the switches SM&#39; 0 , SM&#39; 1 , SM&#39; 2 , SM&#39; 3 , . . . and SM&#39; 64  is controlled by binary (i.e., logic) signals on control lines C&#39; 0 , C &#39;1 , C&#39; 2 , C&#39; 3 , . . . and C&#39; 64 , respectively, as indicated. The binary signals on control lines C&#39; 0 , C&#39; 1 , C&#39; 2 , C&#39; 3  . . . and C&#39; 64 , are produced by a Most Significant Bit (MSB) decoder section 40&#39;. The MSB decoder section 40&#39; produces the binary signals on control lines C&#39; 0  -C&#39; 64  in response to the N/2 (i.e., six) most significant bits, I&#39; 12  . . . I&#39; 7  of the twelve bit digital word I&#39; 12  . . . I&#39; 1  being converted in an analog signal by DAC 10&#39;. The relationship between the bits on lines I&#39; 12  . . . I&#39; 7  and the open/closed condition of the switches SM&#39; 0 , SM&#39; 1 , SM&#39; 2 , SM&#39; 3 ., . . . SM&#39; 64  is shown in FIG. 8. The MSB decoder 40&#39; here uses Gray code decoding. That is, the digital data on bit lines I&#39; 12  -I&#39; 7  is Gray encoded to reduce the decoder implementation. 
     A second switching network 42&#39; has an output terminal 11&#39; which provides the output, V o , for the DAC 10&#39; (i.e., the converted analog signal). The second switching network 42&#39; includes a plurality of, here 2 N/2  (i.e., sixty-four), switches SL&#39; 0 , SL&#39; 1 , SL&#39; 2 , . . . SL&#39; 62  and SL&#39; 63 . The inputs of switches SL&#39; 0 , SL&#39; 1 , SL&#39; 2 , . . . SL&#39; 62  and SL&#39; 63  are connected to terminals Q&#39; 1 , Q&#39; 2 , Q&#39; 3 , . . . Q&#39; 63  and Q&#39; 64 , respectively, as shown. The outputs of switches SL&#39; 0 , SL&#39; 1 , . . . and SL&#39; 63  are connected to DAC 10&#39; output terminal 11&#39;, as shown. The &#34;on&#34; (i.e., closed)/&#34;off&#34; (i.e., open) condition of the switches SL&#39; 0 , SL&#39; 1 , SL&#39; 2 , . . . and SL&#39; 63  is controlled by binary (i.e., logic) signals on control lines D&#39; 0 , D&#39; 1 , D&#39; 2 , . . . and D&#39; 63 , respectively, as indicated. The binary signals on control lines D&#39; 0 , D&#39; 1 , D&#39; 2 , . . . and D&#39; 63 , are produced by a Least Significant Bit (LSB) decoder section 46&#39;. The LSB decoder section 46&#39; includes an LSB decoder 48&#39; and a multiplexer 50&#39;. The LSB decoder section 46&#39; is fed by the N/2 (i.e., six) least significant bits I&#39; 6  . . . I&#39; 1  of the digital word being converted by the DAC 10&#39; and the next highest order bit, i.e., [N/2]+1 bit I&#39; 7  of such digital word. 
     More particularly, the LSB decoder 48&#39; is fed by the six least significant bits I&#39; 6  . . . I&#39; 1  and, in response to such bits, produces binary signals at output terminals A&#39; 0 , A&#39; 1 , A&#39; 3 , . . . and A&#39; 63 . The output terminals A&#39; 0 , A&#39; 1 , A&#39; 2 , . . . and A&#39; 63  are connected to two sets of inputs to the multiplexer 50&#39; (i.e., set of inputs A&#39; and set of inputs B&#39;). The multiplexer 50&#39; has output terminals D&#39; 0 , D&#39; 1 , D&#39; 2 , . . . and D&#39; 63 . In response to the binary signal; of bit I&#39; 7  one of the two input sets A&#39; or B&#39; is selectively coupled to the output terminals D&#39; 0 , D&#39; 1 , D&#39; 2 , . . . and D&#39; 63 . More particularly, when the binary signal of bit I&#39; 7  is logic 0, the output terminals A&#39; 0 , A&#39; 1 , A&#39; 2 , . . . and A&#39; 63  become coupled to output terminals D&#39; 0 , D&#39; 1 , D&#39; 2  and . . . D&#39; 63 , respectively, in a manner similar to that discussed in connection with FIG. 1 for DAC 10. When the binary signal of bit I&#39; 7  is logic 1, the output terminals A&#39; 63 , . . . , A&#39; 2 , A&#39; 1  and A&#39; 0  become coupled to output terminals D&#39; 63 , D&#39; 62 , D&#39; 61 , . . . and D&#39; 0 , respectively, after passing through inverters 51&#39; 63 , . . . 51&#39; 0 , respectively, as shown, in a manner similar to that discussed in connection with DAC 10 in FIG. 1. Thus, the LSB decoder section 46&#39; produces the binary signals on control lines D&#39; 0  -D&#39; 63  in response to the seven least significant bits, I&#39; 7 , I&#39; 6 , . . . I&#39; 1  of the twelve bit digital word I&#39; 12  . . . I&#39; 3  I&#39; 2  I&#39; 1  being converted in an analog signal by DAC 10&#39;. The relationship between the bits on lines I&#39; 12  . . . I&#39; 2  I&#39; 1  and the open/closed condition of the switches SL&#39; 0 , SL&#39; 1 , SL&#39; 2 , . . . SL&#39; 63  is shown in FIG. 9. (It is noted that only one of the switches SL&#39; 0  -SL&#39; 63  is closed for a digital word fed to the DAC 10&#39;. 
     It is first noted that the first switching network 34&#39; is adapted to couple terminals of a selected one of the resistors R&#39;a1-R&#39;a64 in the first resistor string 12&#39; to the pair of switch output terminals 36&#39;, 38&#39;. The resistors R&#39;b1-R&#39;b63 in the second resistor 14&#39; string produce voltages at the terminals Q&#39; 1  -Q&#39; 64  in response to current passing between the first resistor string 12&#39; and the second resistor string 14&#39; through the first switching network 34&#39;. The second switching network 42&#39; is adapted to couple a selected one of the voltages produced at a resistor terminal Q&#39; 1  -Q&#39; 64  of a selected one of the resistors R&#39;b1-R&#39;b63 in the second resistor string 14&#39; to the output terminal 11&#39; of the converter 10&#39;. 
     The operation of the DAC 10&#39; is thus similar to DAC 10 described above in connection FIG. 1. Here, the resistance, r&#39; p  across a pair of successive terminals T&#39; 0  -T&#39; 64  (e.g., the resistance between terminals T&#39; 2 , T&#39; 3 ) is: R&#39; p  =R&#39; 1  [63R&#39; 2  ]/[R&#39; 1  +63R&#39; 2  ]; assuming that the &#34;on&#34; resistance of each of the switches SM&#39; 0  -SM&#39; 64  is zero. It R&#39; 1  =R&#39; 2 , r p  =63R&#39; 1  /64. Thus, a little thought will make it apparent as the digital word I&#39; 12  . . . I&#39; 1  changes (i.e., increases or decreases) by one least significant bit, the output voltage V o  at terminal 11&#39; will change (i.e., increase or decrease) one LSB (i.e., the output voltage V o  changes by V/[2 N  -1]=V/4095). Further, with an additional resistor connected serially between terminal 16 and terminal T&#39; 64  of R&#39; 1  /2 N/2  ohms=R&#39; 1  /64 ohms, as the digital word I&#39; 12  . . . I&#39; 1  changes (i.e., increases or decrease) by one least significant bit, the output voltage V o  at terminal 11&#39; will change (i.e., increase or decrease) one LSB (i.e., the output changes V/[2 N  ]=V/4096). 
     Referring now to FIG. 10, the effect of a non-zero resistance for the switches SM 0  -SM 4  of the DAC 10 shown in FIG. 1 will be discussed. Here, the switches SM 0  -SM 4  are CMOS switches each having an &#34;on&#34;,or conducting resistance of R ON . Thus, consider the example where switched SM 2  and SM 3  are &#34;on&#34; (i.e., conducting), and all other switches SM 0 , SM 1 , SM 4  are &#34;off&#34; (i.e., non-conducting). When the second resistor string 14&#39; is connected in parallel with a selected one of the resistors Ra1 to Ra2 N/2 , where here N=4, here in this example across resistor Ra3, the effective resistance across the terminals T 2 , T 3  of the selected one of the resistors Ra3 is R 1  [(2 N/2  -1) R 2  +2R ON  ]/(R 1  +(2 N/2  -1)R 2  +2R ON ) By selecting R 2  =R 1  +2R ON  a step change of substantially one LSB is produced at the DAC 10 output 11, when a one bit change is made in the least significant bit of a digital word I N  I N-1  . . . I 1  being converted by the DAC 10. Also, a one LSB voltage step is experienced at a terminal 36, 38 when the first switching network 34 switches from coupling one of the first resistors in section 14 to the pair of output terminals 36, 38 to coupling the next successively serially coupled one of the resistors in network 12 to the pair of output terminals 36, 38. That is, if, for example, the first switching network 34 has selected resistor Ra2 and then switches to select resistor Ra3, the voltage at terminal 38 changes by substantially one LSB at the DAC 10 output 11, if the relationship between R 1 , R 2 , and R ON  is, then R 2  =R 1  +2R ON . 
     Referring now to the effect of a non-zero resistance for the switches SM&#39; 0  -SM&#39; 64  of the DAC 10&#39; shown in FIG. 11 will be discussed. Here, the switches SM&#39; 0  -SM&#39; 64  are CMOS switches each having an &#34;on&#34;,or conducting resistance of R&#39; ON . Thus, considering the example where switched SM&#39; 1  and SM&#39; 2  are &#34;on&#34; (i.e., conducting), and all other switches SM&#39; 0 , SM&#39; 3 , . . . SM&#39; 64  are &#34;off&#34; (i.e., non-conducting), if the relationship between R&#39; 1 , R&#39; 2 . and R&#39; ON  is, then R&#39; 2  =R&#39; 1  +2R&#39; ON . When the second resistor string 14&#39; is connected in parallel with a selected one of the resistors Ra1 to Ra2 N/2 , the effective resistance across the terminals T&#39; 2 , T&#39; 3  of the selected one of the resistors R&#39;a3 is R&#39; 1  [(2 N/2  -1)R&#39; 2  +2R&#39; ON  ]/(R&#39; 1  +(2 N/2  -1)R&#39; 2  +2R&#39; ON ). By selecting R&#39; 2  =R&#39; 1  +2R&#39; ON  a step change of substantially one LSB is produced at the DAC 10&#39; output 11&#39;, when a one bit change is made in the least significant bit of a digital word I&#39; N  I&#39; N-1  . . . I&#39; 1  being converted by the DAC 10&#39;. Also, a voltage step of less than one LSB is experienced at a terminal T&#39; 1  -T&#39; 63  when the first switching network 34&#39; switches from coupling one of the first resistors in section 14&#39; to the pair of output terminals 36&#39;, 38&#39; to coupling the next successively serially coupled one of the resistors in network 12&#39; to the pair of output terminals 36&#39;, 38&#39;. That is, if, for example, the first switching network 34&#39; (FIG. 7) has selected resistor R&#39;a2 and then switches to select resistor R&#39;a3, the voltage at terminal T&#39; 2  changes by substantially (i.e., a little less than) one LSB at the DAC 10&#39; output 11&#39;, if the relationship between R&#39; 1 , R&#39; 2 , and R&#39; ON  is, then R&#39; 2  =R&#39; 1  +2R&#39; ON . 
     Other embodiments are within the spirit and scope of the appended claims. For example, due to manufacturing variances and second order non-ideal conditions, the nominal values of R&#39; 1 , R&#39; 2 , and R&#39; ON  may be adjusted to give optimum results. Monte Carlo analysis or other statistical analysis may be used to perform this optimization. Further, various technologies may be used for the switches, such as CMOS transmission gates, one MOS transistor type (e.g., NMOS or PMOS), either of the above with a single, or plurality of, series resistors on one or both sides of the switch. Still further, two parallel resistor strings may be used.