Abstract:
A stereo demodulator system includes first and second differential amplifiers differentially responding to a first form of a stereo signal and at least a pair of differentially connected transistors serially connected to the output circuit of the first differential amplifier and responding to a second signal related to the first signal. A current mirror circuit is provided from the output circuit of the second differential amplifier to the pair of differentially connected transistors to produce a mixed output signal at the output terminal of the pair of transistors to separate the stereo signal into component signals. An offset current compensator is provided to avoid producing an offset current in the mixed output signal.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to a stereo demodulator system and is directed particularly to a differential amplifier with an offset current compensator for use in an integrated circuit embodying such a system. 
     2. Description of the Prior Art 
     In my co-pending application Ser. No. 731,018 entitled &#34;MPX Stereo Signal Demodulator&#34; filed Oct. 8, 1976 and assigned to the same assignee as the present case, and which issued as U.S. Pat. No. 4,049,918, I proposed a system that would reduce the offset current of a stereo signal to within a several tens of μA(micro ampere). However, it is desirable to reduce the offset current still more in the case of a multiplex (MPX) stereo signal demodulator that includes a muting circuit. An offset current amounting to about 10 μA or more would produce a rather large noise when the muting circuit was switched ON and OFF. 
     SUMMARY OF THE INVENTION 
     Accordingly, an object of the present invention is to provide a stereo demodulator which is free from the defects encountered in the prior art. 
     Another object of the invention is to provide a stereo demodulator system which is suitable for use with an MPX stereo demodulator formed as an integrated circuit. 
     The invention is incorporated in a stereo demodulator system provided with first and second differential amplifiers and a first signal input circuit for applying one form of a stereo signal, such as the standard composite stereo signal transmitted on frequency-modulated (FM) stations, as an input signal to first and second differential amplifiers. The system also includes fifth and sixth transistors, the collector-emitter circuits thereof being connected in series with the collectors of the transistors making up the first differential amplifier, and a second signal related to the first signal, as, for example, a subcarrier modulated with a stereo difference signal, is applied to the fifth and sixth transistors. A current mirror circuit having input and output terminals is connected in a serial circuit path between the collector of the third transistor and the collectors of the fifth and sixth transistors, and a signal output circuit is connected to at least one of the collectors of the fifth and sixth transistors. 
     In accordance with the invention, a current compensating circuit is connected between the input terminal of the current mirror circuit and the collector of one of the transistors making up the second differential amplifier so as to compensate for the base current components of the fifth and sixth transistors. 
     Other objects, features, and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings in which the like elements are marked with the like references. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of an MPX stereo demodulator; 
     FIG. 2 is an equivalent circuit to that shown in FIG. 1 used for explaining the demodulation theory of the circuit shown in FIG. 1; and 
     FIGS. 3 and 4 are circuit diagrams showing examples of the stereo demodulator system according to the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Before describing the invention, an example of an MPX stereo demodulator circuit disclosed in my co-pending application U.S. Ser. No. 731,018 (U.S. Pat. No. 4,049,918) will be described with reference to FIG. 1. The circuit includes an input terminal 1 to which a composite stereo signal is applied, input terminals 2a and 2b to which a subcarrier signal of 38 KHz is applied, output terminals 3L and 3R from which stereo demodulated output signal may be obtained as left and right audio signals, and a voltage source terminal 4 to which a power supply source having a voltage of +B is connected. First and second differential amplifier circuits 6 and 7 are connected to receive the composite stereo signal as applied from the terminal 1. In addition, a multiplier circuit 10, which is formed of third and fourth differential amplifier circuits 8 and 9, is included. The subcarrier signal and the composite stereo signal from the first differential amplifier 6 are applied to the circuit 10 to be multiplied together. FIG. 1 also includes a current relay, or current mirror circuit 23. 
     The first differential amplifier 6 is formed of amplifying transistors Q 1 , Q 2  and a constant current circuit having at least one transistor Q 3 . The emitters of amplification transistors Q 1  and Q 2  are connected together through a resistor 36 for improving the linearity of operation of the differential amplifier 6. In this embodiment the constant current circuit includes transistors Q 3a  and Q 3b  whose collectors are connected to the emitters of transistors Q 1  and Q 2  and whose emitters are grounded through resistors 43 and 44, respectively. 
     The second differential amplifier 7 is much like the first and is formed of amplifying transistors Q 4  and Q 5  and a constant current circuit including at least one transistor Q 6 . The emitters of amplification transistors Q 4  and Q 5  are connected together through a resistor 37, the resistance value of which is selected to have the same resistance as the resistor 36, for improving the linearity of operation of the differential amplifier 7. In the embodiment shown the constant current transistor Q 6  actually consists of transistors Q 6a  and Q 6b , the collectors of which are connected to the emitters of transistors Q 4  and Q 5  and the emitters of which are grounded through resistors 45 and 46. The resistance values of the resistors 45 and 46 are chosen to be the same as those of resistors 43 and 44, respectively. 
     As described above, the multiplier circuit 10 consists of third and fourth differential amplifiers 8 and 9. The third differential amplifier 8 is formed of a pair of amplifying transistors Q 7  and Q 8 , while the fourth differential amplifier 9 is formed of a pair of amplifying transistors Q 9  and Q 10 . The third and fourth differential amplifiers 8 and 9 have the subcarrier signal of 38 KHz supplied to them as a balanced input signal via the input terminals 2a and 2b, respectively. The multiplier 10 is connected in series with the collectors of the transistors Q 1  and Q 2  of the first differential amplifier 6. The collectors of the transistors Q 7  and Q 9  are connected through a load resistor 20 to a voltage source E 3 , while the collectors of the transistors Q 8  and Q 10  are connected through a load resistor 21 to voltage source E 3 . The resistance value of the resistor 20 is the same as that of the resistor 21. The left audio signal output terminal 3L extends from the connection point between the collectors of the transistors Q 7  and Q 9 , while the right audio signal output terminal 3R extends from the connection point between the collectors of the transistors Q 8  and Q 10 . 
     The current relay, or current mirror, circuit 23 includes a transistor Q 11  having its emitter-collector circuit connected in series with the emitter-collector circuit of each of the transistors Q 7  and Q 9 , and a transistor Q 12  having its emitter-collector circuit connected in series with the emitter-collector circuit of the transistor Q 10 . The current mirror circuit also includes transistors Q 13  and Q 14 , which are connected to the collector of the transistor Q 4  of the second differential amplifier 7. More specifically, the collectors of the transistors Q 7  and Q 9  are connected to the collector of the transistor Q 11 , the emitter of which is connected to the voltage supply terminal 4 through an emitter resistor 38 for current feedback, and the collectors of the transistors Q 8  and Q 10  are connected to the collector of the transistor Q 12 , the emitter of which is also connected to the voltage supply terminal 4 through an emitter resistor 39 for current feedback. The collector of the transistor Q 4  is connected to the collector of transistor Q 14  and to the base of transistor Q 13 , and the emitter of transistor Q 14  is connected to the voltage supply terminal 4 through an emitter resistor 40 for current feedback. The collector of the transistor Q 13  is grounded, and the emitter of the transistor Q 13  is connected to the base of the transistor Q 14  and to the bases of the transistors Q 11  and Q 12 . In this case, the resistors 38, 39, and 40 are selected to have equal resistances. Thus, the current based upon the composite stereo signal flowing through the collector-emitter path of transistor Q 14  is relayed to the transistors Q 11  and Q 12 , respectively. 
     A bias voltage source E, which supplies a constant voltage in this embodiment, is connected to the bases of the transistors Q 1 , Q 2 , Q 4  and Q 5  of the first and second differential amplifiers 6 and 7 through resistors 15, 16, 17 and 18, which are selected to have equal resistance values. The base of transistor Q 1  is connected to the base of transistor Q 4   through a resistor 41 that has the same resistance value as that of the resistors 39 and 40. The composite stereo signal is applied via the input terminal 1 to the base of the transistor Q 2  of the first differential amplifier 6 and to the base of the transistor Q 5  of the second differential amplifier 7 through a variable resistor 5 for separation control and a terminal P, respectively. The terminal P and the common connection point between the base of the transistor Q 2  and the resistor 16 are terminals of an integrated circuit that includes the differential amplifiers 6-9, and the variable resistor 5 thus need be connected to the integrated circuit through only the single additional input terminal P. 
     Bias voltage for constant current transistors Q 3a , Q 3b  and Q 6a , Q 6b  of first and second differential amplifiers 6 and 7, respectively, is provided by way of a circuit connected between the terminal 4 and ground and consisting of a switch SW for muting control, a resistor 30, the collector-emitter path of a transistor Q 15 , and a resistor 42, connected in series, and a transistor Q 16 , the base and emitter of which are connected to the collector and base, respectively, of the transistor Q 15  and the collector of which is connected to the connection point between the resistor 30 and the switch SW. The base of the transistor Q 15  is also connected directly to the bases of transistors Q 3a , Q 3b , Q 6a  and Q 6b , and the resistors 42, 43, 44, 45 and 46 are all selected to have equal resistances. Thus, a current relay circuit 50 is composed of the transistors Q 15 , Q 16 , Q 3a , Q 3b , Q 6a  and Q 6b  and the resistors 42, 43, 44, 45 and 46. 
     The circuit shown in FIG. 1 is to be understood as being used in conjunction with a circuit (not shown) that detects the amplitude of the frequency signal from an FM intermediate frequency amplifier circuit and produces an output signal when the level of the detected signal is lower than a predetermined level. Amplitude detection circuits so connected are well-known. The output signal from the amplitude detection circuit is applied as a muting control signal to the switch SW, which is, in fact, a semiconductor switching element rather than a manual switch, to control the same, i.e., to make it non-conductive in the absence of an intermediate frequency signal of sufficient amplitude. 
     In the circuit shown in FIG. 1, each of the transistors Q 1 , Q 2 , Q 3a , Q 3b , Q 4 , Q 5 , Q 6a , Q 6b , Q 7 , Q 8 , Q 9  and Q 10  are NPN-type transistors having the same characteristics, each of the transistors Q 11 , Q 12  and Q 14  are PNP-type transistors having the same characteristics, and transistor Q 13  is a PNP-type (vertical) transistor. The circuit shown in FIG. 1 can be made as an integrated circuit except the variable resistor 5 and the capacitor connecting terminal 1 to the resistor 5. 
     The operation of the circuit shown in FIG. 1 will be now described with reference to FIG. 2 which shows an equivalent circuit of FIG. 1. In FIG. 2, the parts corresponding to those of FIG. 1 are marked with the same reference numerals. 
     In FIG. 2, each of the current sources 27 and 28 of multiplied output signals -(R-L) and -(L-R) includes a direct current I 2  from the multiplier circuit 10, and each of the current sources 25 and 26 of the main audio signal (R+L) contained in the composite stereo signal includes a direct current I 1  from the second differential amplifier 7. The left audio signal is obtained at the output terminal 3L by adding the currents from current sources 26 and 28, while the right audio signal is obtained at the output terminal 3R by adding the currents from current sources 25 and 27. 
     In general, the gain of a differential amplifier circuit is determined by the product of the mutual conductance thereof and the load resistance, and the mutual conductance depends upon the constant current of its constant current circuit. Thus, the gain of the differential amplifier reduces as the constant current reduces. 
     When the level of a received signal is sufficiently high, the switch SW is closed, or made conductive, and hence a predetermined direct current flows through the constant current transistors Q 3a , Q 3b  and Q 6a , Q 6b  of the first and second differential amplifiers 6 and 7. Thus, these differential amplifiers operate normally, allowing the stereo demodulated output signal, i.e., left and right audio signals, to be obtained at the output terminals 3L and 3R, respectively. 
     On the other hand, when the level of a received signal is lower than the predetermined level, the switch SW is made non-conductive and the voltage of the source E 1  becomes zero. This causes the constant current transistors Q 3a , Q 3b  and Q 6a , Q 6b  of the first and second differential amplifiers 6 and 7 to be non-conductive so that the current flowing through them becomes zero. Accordingly, no stereo demodulated output signals can be obtained at the output terminals 3L and 3R, which means that the muting operation is in effect. 
     If the separation control resistor 5 is varied, the amplitude of the composite stereo signal, especially its main audio components, which are fed to the second differential amplifier 7, can be varied. Thus, separation control can be achieved. In this case, since the base potentials of transistors Q 2  and Q 5  of first and second differential amplifiers 6 and 7, to which the composite stereo signal is supplied, are entirely equal, no direct current flows through the resistor 5 and hence the DC level of the stereo modulated output signals obtained at output terminals 3L and 3R are not changed by variating the resistor 5. 
     The DC operation of the circuit shown in FIG. 1 will now be described. If the voltage +B at the power supply terminal 4 and the resistance values of resistors 30 and 42 are determined, a direct current I 0  flowing through resistor 30 when switch SW is conductive is determined. If the base current of transistors Q 3a , Q 3b , Q 6a  and Q 6b  are neglected, their DC collector currents coincide with their DC emitter currents I 01 , I 02 , I 03  and I 04 , respectively. 
     A DC collector current I 2 , which will flow through transistors Q 7  and Q 9  or Q 8  and Q 10  of the multiplier circuit 10, is expressed by the following equation (1) when there is no 38 KHz subcarrier signal applied to the input terminals 2a and 2b: ##EQU1## where h FE  represents the current amplification factor of each of the NPN-type transistors connected in emitter-grounded configuration. 
     A collector current I 3  of the transistor Q 4 , which is the direct current flowing through the input terminal 23 i  of the current mirror 23, is expressed by the following equantion(2). ##EQU2## 
     Further, if it is assumed that the current amplification factor of the transistors Q 11 , Q 12  and Q 14  connected in the emitter-grounded configuration is taken as h&#39; FE  and that of the transistor Q 13  as h&#34; FE , the ratio between the collector current (direct current) I 1  of the transistors Q 11 , Q 12  and the direct collector current I 3  of the transistor Q 4  can be expressed as follows: ##EQU3## 
     If, in the expression (3), ##EQU4## then 
     
         I.sub.1 = I.sub.3                                          (5) 
    
     further, if the value of I 3  in expression (2) is substituted for I 3  in expression (3), the current I 1  can be expressed as follows: ##EQU5## 
     Accordingly, the offset current I 1  - I 2  between the two output terminals 3L and 3R is expressed as follows: ##EQU6## 
     A principal object of the present invention is to make the above offset current as small as possible. To this end the following three methods can be considered: 
     (1) The values of I 01 , I 02 , and I 03  may be chosen to make 
     
         I.sub.01 = I.sub.02 = I.sub.03 or I.sub.03 = 1/2 (I.sub.01 + I.sub.02); 
    
     the term h&#34; FE  · h&#34; FE  may be selected to be large so as to make ##EQU7## and 
     (3) The base currents of the transistors Q 7 , Q 8 , Q 9  and Q 10  may be corrected. 
     If it is assumed that I 01  = I 02  = I 03  = I&#39; 0  and if it is also assumed that ##EQU8## the expression (7) can be rewritten as follows: ##EQU9## 
     Assuming that I&#39; 0  is 1.0 mA(milli-ampere) and h FE  is 100 in the equation (8), the offset current I 1  - I 2  becomes about 9.7 μA(micro-ampere). 
     However, an offset current of 9.7 μA will cause a noise voltage to be generated at the output terminals 3L and 3R every time the switch SW is made opened and closed. If the noise voltage can be reduced to less than about 20 to 30 V p-p , it may be tolerable. By way of example, if the resistance of the resistors 20 and 21 is 3.3K the offset current must be reduced to less than 1.5 μA. Unfortunately, the value 9.7 A is considerably higher than 1.5 μA. Accordingly, method (3) must be employed in addition to methods (1) and (2). 
     Thus, making the offset current as small as possible, which is a main object of this invention, is attained by employing method (3). 
     An example of the differential amplifier circuit according to the present invention will be hereinafter described with reference to FIG. 3. Since the example of the invention shown in FIG. 3 is made by partially improving the MPX stereo demodulating circuit shown in FIG. 1, the parts of FIG. 3 corresponding to those of FIG. 1 are marked with the same reference numerals and symbols and their description will be largely omitted for the sake of brevity. 
     In the example of the invention shown in FIG. 3, a fifth differential amplifier circuit 51 is provided and is supplied with the output signal from the second differential amplifier 7. The output signal of the fifth differential amplifier is supplied to the current mirror circuit 23 through an input terminal 23 i  of the circuit 23. The fifth differential amplifier circuit 51 consists of a pair of NPN-type transistors Q 17  and Q 18 , each of which has the same characteristics as the previously-mentioned NPN-type transistors. The transistors Q 17  and Q 18  have their collectors connected together to the collector of transistor Q 14 , their emitters connected together to the collector of transistor Q 4 , and their bases connected to the input terminals 2a and 2b, respectively. The common connection of the collectors of the transistors Q 14 , Q 17 , and Q 18  is also the input terminal 23 i . 
     In the circuit of the invention shown in FIG. 3, the current I 3  can be expressed in correspondence with equation (2) as follows: ##EQU10## 
     Hence, the current I 1  of this example can be expressed in correspondence with the equation (6) as follows: ##EQU11## 
     Thus, the offset current I 1  - I 2  of this example can be expressed as follows: ##EQU12## 
     In the expression (7&#39;), if it is assumed that 
     
         I.sub.01 = I.sub.02 = I.sub.03 = I&#39;.sub.0 
    
     and ##EQU13## the offset current I 1  - I 2  becomes substantially equal to zero. 
     In the example of the invention shown in FIG. 3, the compensating circuit includes two transistors Q 17  and Q 18  connected together to form the differential amplifier 51. However, one of the transistors Q 17  and Q 18  could be omitted, as illustrated in the embodiment shown in FIG. 4. In this example, only transistor Q 17  is used in the compensating circuit. The base of the transistor Q 17  is connected directly to a direct voltage source E 4 , which is provided for 38KHz subcarrier signal sources 48a and 48b, which are of opposite phase. Further, in the embodiment shown in FIG. 4, NPN-type transistors Q 3  and Q 6  which have the same characteristics as the transistors Q 3a , Q 3b , Q 6b  are used in place of the latter. The collector of the transistor Q 3  is connected through resistors 36a and 36b, which are of equal resistance, to the emitters of the transistors Q 1  and Q 2 , respectively, and the emitter of the transistor Q 3  is grounded through the resistor 43. The collector of the transistor Q 6   is connected through the resistors 37a and 37b, which have the same resistance, to the emitters of the transistors Q 4  and Q 5 , respectively, and the emitter of the transistor Q 6  is grounded through the resistor 45. 
     According to the present invention, as described above, a circuit in which the desired advantages are obtained comprises first differential amplifier 6, the second differential amplifier 7, a combining differential amplifier circuit formed of a third and a fourth differential ampliers 8 and 9 and supplied with the output signal from the first differential amplifier 6, and the current relay, or mirror, circuit 23. The current mirror circuit 23 has its input terminal 23 i  connected to the output circuit of the second differential amplifier 7 and its output terminals, which are the collectors of the transistors Q 11  and Q 12 , connected to the collectors of the transistors Q 7 , Q 9  and Q 8 , Q 10 , respectively, so that the current mirror 23 is serially connected, that is, connected in series in the signal path from the output circuit of the second differential amplifier 7 to the collectors of the transistors Q 7  -Q 10 . The current mirror 23 thus provides an output signal to the output terminals of the third and fourth differential amplifiers to be added to the output signal of the third and fourth differential amplifiers. At least one transistor Q 17  (FIG. 4) or a pair of transistors Q 17  and Q 18  (FIG. 3) connected to form the fifth differential amplifier circuit 51, is supplied with the output signal of the second differential amplifier 7, and the output of the fifth differential amplifier circuit is applied to the current relay circuit 23 to adjust the current in the current relay circuit 23 in the sense to compensate for the base-emitter current in the transistors Q 7  -Q 10 , and thereby to reduce the offset current between the two output terminals 3L and 3R. 
     It will be apparent that many modifications and variations could be effected by one skilled in the art without departing from the spirit of the present invention so that the scope of the invention should be determined by the following claims only.