Abstract:
A semiconductor device has a semiconductor substrate, an insulating layer formed on the semiconductor substrate, a wiring formed in the insulating layer and an antifuse including first and second connecting portions coupled to the wiring. The anti fuse has a space provided between the first connecting portion and the second connecting portion and insulating the first connecting portion from the second connecting portion. The first connecting portion and the second connecting portion may be coupled by a conductive material disposed in the space.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2006-346474, filed Dec. 22, 2006, the entire contents of which are incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    This invention relates to semiconductor devises and methods of manufacturing semiconductor devices, particularly semiconductor devices having an antifuse and methods of manufacturing the same. 
         [0004]    2. Description of the Related Art 
         [0005]    A conventional semiconductor device having antifuses is known. An antifuse changes a connection state from an insulated state by applying voltage thereto. 
         [0006]    A conventional semiconductor device has a semiconductor substrate, an insulated layer formed on the semiconductor substrate, a lower wiring layer formed on the insulated layer, an amorphous semiconductor layer for antifuse formed on the lower wiring layer, an inter-layer dielectric formed on the insulated layer and the and the amorphous semiconductor layer and having a contact hole which reaches to the amorphous semiconductor layer, and an upper wiring layer formed on the inter-layer dielectric connected to the amorphous semiconductor layer through the contact hole. 
         [0007]    According to the semiconductor device, Joule heat is generated by applying voltage between the upper wiring layer and the lower wiring layer. A part of the amorphous semiconductor layer can thereby be changed into a polycrystal, the resistance thereby lowered, and the upper wiring layer and the lower wiring layer thereby electrically connected. 
         [0008]    However, when an element domain is near the antifuse domain, there is a possibility that the element domain (for example, gate insulating film etc.) may be damaged by applying voltage between the upper wiring layer and the lower layer wiring layer. 
       BRIEF SUMMARY OF THE INVENTION 
       [0009]    Accordingly to one aspect of the present invention, there is provided a semiconductor device including a semiconductor substrate, a insulating layer formed on the semiconductor substrate, a wiring formed in the insulating layer, and an antifuse including first and second connecting portions coupled to the wiring the antifuse having an space between the first connecting portion and the second connecting portion, the space having a width insulating the first connecting portion from the second connecting portion, the first connecting portion and the second connecting portion configured to be coupled by a conductive material disposed in the space. 
         [0010]    A semiconductor device according to an another aspect of the present invention includes a semiconductor substrate, a insulating layer formed on the semiconductor substrate, a wiring formed in the insulating layer, a first antifuse including first and second connecting portions coupled to the wiring, the first connecting portion and the second connecting portion coupled by a conductive material, and a second antifuse including third and fourth connecting portions coupled to the wiring, the second antifuse having a space between the third connecting portion and the fourth connecting portion, the space having a width insulating the third connecting portion from the fourth connecting portion. 
         [0011]    A method of fabricating a semiconductor device according to an another aspect of the present invention includes preparing a semiconductor substrate, a insulating layer formed on the semiconductor substrate, a wiring formed in the insulating layer and a antifuse including a first connecting portion and a second connecting portion, the antifuse having a space, between the first connecting portion and the second connecting portion, and disposing a conductive material in the space so as to couple the first connecting portion to the second connecting portion. 
         [0012]    A semiconductor device according to an another aspect of the present invention includes a semiconductor substrate, an insulating layer formed on the semiconductor substrate, a wiring formed in the insulating layer, a first antifuse including first and second connecting portions coupled to the wiring, the first connecting portion and the second connecting portion coupled by a conductive material, and a second antifuse including third and fourth connecting portions coupled to the wiring, the second antifuse having an space between the third connecting portion and the fourth connecting portion, the space having a width insulating the third connecting portion from the fourth connecting portion, wherein the conductive material is a ball bump, the first antifuse is coupled to a normal circuit, and the second antifuse is coupled to a defective circuit. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING 
         [0013]    A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein: 
           [0014]      FIG. 1  is a top view of an antifuse region in a semiconductor device according to a first embodiment of the invention. 
           [0015]      FIG. 2  is a sectional view of the semiconductor device taken along line A-A of  FIG. 1  according to a first embodiment of the invention. 
           [0016]      FIG. 3A  is a sectional view illustrating a method of making the semiconductor device according to a first embodiment of the invention. 
           [0017]      FIG. 3B  is a sectional view illustrating a method of making the semiconductor device according to a first embodiment of the invention. 
           [0018]      FIG. 3C  is a sectional view illustrating a method of making the semiconductor device according to a first embodiment of the invention. 
           [0019]      FIG. 4  is a top view of an antifuse region in a semiconductor device according to a second embodiment of the invention. 
           [0020]      FIG. 5  is a sectional view of the semiconductor device taken along line B-B of  FIG. 4  according to a second embodiment of the invention. 
           [0021]      FIG. 6A  is a sectional view illustrating a method of making the semiconductor device according to a second embodiment of the invention. 
           [0022]      FIG. 6B  is a sectional view illustrating a method of making the semiconductor device according to a second embodiment of the invention. 
           [0023]      FIG. 6C  is a sectional view illustrating a method of making the semiconductor device according to a second embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0024]    Various other objects, features and attendant advantages of the present invention will be more fully appreciated as the same becomes better understood from the following detailed description when considered in connection with the accompanying drawings in which like reference characters designate like or corresponding parts throughout the several views and more particularly to  FIG. 1  thereof. 
       First Embodiment 
       [0025]    Referring now to  FIG. 1 , semiconductor device  1  has two or more antifuses  3 . As shown in  FIGS. 1 and 2 , each antifuse  3  is formed in protection insulating film  4 , and has an exposed the surface in antifuse domain  2 . Each antifuse  3  is connected to wiring  5  formed in interlayer insulating film  6 , respectively. 
         [0026]    Antifuse  3  is made of two wiring elements (wiring elements on either side in  FIG. 1 ) electrically opened by space  3   a  in antifuse domain  2 . Among these, spaces  3   a  of specific antifuses  3  (first, third and fourth antifuses  3  from the top in  FIG. 1 ) are buried by ball bump  3   b , and the two wirings of these antifuses  3  are electrically connected. For example, first third, and fourth antifuses  3  from the top in  FIG. 1  are connected to a circuit which operates normally, and the second antifuse  3 , which is not connected by a ball bump  3   b , is connected to a defective circuit. 
         [0027]    Antifuse  3  is made of conductive material, such as aluminum. Wiring  5  is made of conductive material, such as Cu. 
         [0028]    As a ball bump  3   b , conductive materials such as solder, Au, Cu and an alloy containing these or the like can be used. In addition, the melting point of ball bump  3   b  may be more than 240 degrees (° C.). The melting point is chosen sufficiently high because there is a possibility of melting by a heating process (for example, a heating process for activating impurity ions implanted into a transistor domain) if the melting point is too low. The ball bump  3   b  may have other features than as specifically shown, for example a shape of a board, may be used. 
         [0029]    As a protection insulating film  4 , insulating materials such as TEOS (Tetraethoxysilane), SiN, and polyimide or the like can be used Especially, hygroscopic low material, such as TEOS and SiN, is desirable. 
         [0030]    As interlayer insulating film  6 , a low insulating material of specific inductive capacity, such as methyl siloxane, can be used. 
         [0031]    A process for forming ball bump  3   b  in antifuse domain  2  of semiconductor device  1  is next explained. Here, as a result of operating test of two or more circuits on semiconductor device  1 , it is supposed that, the circuit which is connected to second antifuse  3  on  FIG. 1  is defective, and the circuit which is connected to the other antifuse  3  is normal. Then, a ball bump  3   b  is not connected to the second antifuse  3  which is connected to a defective circuit and ball bumps  3   b  are connected to remaining antifuses  3  which are connected to a normal circuit 
         [0032]    First as shown in  FIG. 3A , a semiconductor device  1  in which ball bumps  3   b  are not formed is prepared. 
         [0033]    Next, as shown in  FIG. 3B , ball bump  3   b  is formed in space  3   a  of antifuse  3  which is connected to normal circuit in antifuse domain  2 . 
         [0034]    Next, as shown in  FIG. 3C , ball bump  3   b  is at least partially melted by heating, and antifuse  3  is thereby electrically connected. 
         [0035]    In addition, as alternative methods of connecting ball bump  3   b  and antifuse  3   a  method of thermo compression of ball bump  3   b  by a bonding head, and a method of heat-treating after forming ball bump  3   b  by an ink-jet method can be used. 
         [0036]    In this embodiment although the method of connecting ball bump  3   b  to antifuse  3  which is connected to a normal circuit, and not connecting ball bump  3   b  to antifuse  3  which is connected to a defective circuit is used, ball bump  3   b  may be removed from antifuse  3  which is connected to a defective circuit after ball bumps  3   b  previously are connected to all antifuses  3 . In this case, in the heat treatment process for melting ball bump  3   b , for example, a ball bump  3   b  can be selectively removed by a solder sucker and a solder wick. 
         [0037]    In this embodiment, since antifuses can be electrically connected by ball bumps without applying voltage, surrounding elements are not damaged by applied voltage. Therefore, it is possible to arrange an element domain near an antifuse domain, to contribute to a miniaturization of a semiconductor device. 
       Second Embodiment 
       [0038]    A difference between the first embodiment and a second embodiment is that the connection end of the antifuse is melted without using a ball bump and the antifuse is connected. This is described in the following discussion, wherein the explanation of same components in first embodiment is omitted. 
         [0039]    As shown in  FIG. 4  and  FIG. 5 , semiconductor device  10  has two or more antifuses  7 . Each antifuse  7  is formed in protection insulating film  4 . Each antifuse  7  has an exposed surface in antifuse domain  2 . Moreover, each antifuse  7  is connected to wiring  5  formed in interlayer insulating film  6 , respectively. 
         [0040]    Antifuse  7  includes of two wiring elements (wiring elements on either side in  FIG. 4 ) electrically insulated by space  7   a  in antifuse domain  2 . Among these, space  7   a  is occupied by connecting part  7   b  of specific antifuses  7  (1st, 3rd and 4th antifuses  7  from the top in  FIG. 4 ), and the two wirings are connected. For example, the 1 st, 3rd and 4th antifuses  7  from the top in  FIG. 4  are connected to circuits which operate normally, and the 2nd antifuse  7  is connected to a defective circuit. 
         [0041]    Antifuse  7  is made of a conductive material such as solder, etc., by which connecting end  7   c  located on both sides of space  7   a  can be melted by irradiation of laser light. The melting point of ball bump  3   b  may be more than 240 degrees (° C.). Once again, the melting point must be sufficiently high to avoid melting which might otherwise occur in a subsequent heating process (for example, a heating process for activating impurity ions implanted into a transistor domain) if a melting point is too low. 
         [0042]    Wiring  5  is made of conductive material, such as Cu. 
         [0043]    As protection insulating film  4 , insulating materials such as TEOS (Tetraethoxysilane), SiN, and polyimide or the like can be used. Especially, hygroscopic low material, such as TEOS and SiN, is desirable. 
         [0044]    As the interlayer insulating film  6 , low insulating material of specific inductive capacity, such as methyl siloxane, can be used. 
         [0045]    Next, the process which connects antifuse  7  through connecting part  7   b  is explained. Here, as a result of operating test of two or more circuits on semiconductor device  10 , it is supposed that, the circuit which is connected to the 2nd antifuse  7  from the top of  FIG. 4  is defective, and the circuits which are connected to other antifuses  7  are normal. Then, each antifuse  7  which is connected to a normal circuit is connected via connecting part  7   b , and the 2nd antifuse  7  from the top of  FIG. 4  which is connected to defective circuit is not connected. 
         [0046]    As shown in  FIG. 6A , semiconductor device  10  which has antifuse  7  insulated by space  7   a  is prepared. 
         [0047]    As shown in  FIG. 6B , using laser etc., connecting end  7   c  of antifuse  7  which is connected to the normal circuit is heated locally in antifuse domain  2 , and is melted. 
         [0048]    As shown in  FIG. 6C , when connecting end  7   c  continues to be heated, connecting end  7   c  begins to melt, and space  7   a  is occupied by connecting part  7   b . Thereby, antifuse  7  is connected. 
         [0049]    In addition, since laser light is used for heating connecting end  7   c  of antifuse  7 , laser light does not reach to the lower layer of antifuse  7 , so that there is no possibility that the lower layer of antifuse  7  may be damaged. 
         [0050]    Moreover, either side of connecting end  7   c  is melted, so that space  7   a  may be occupied. In this case, at least melted connection end  7   c  may just is made of a conductive material which can be melted by irradiation of laser etc. 
         [0051]    According to second embodiment of this invention, since the wiring which is connected to antifuse can be connected without applying voltage like the first embodiment, surrounding elements etc. are not damaged by applied voltage. Therefore, it is possible to arrange an element domain around an antifuse domain, so as to contribute to miniaturization of the semiconductor device. Moreover, the process which forms the ball bump which is connected to the antifuse can be omitted in comparison with first embodiment. 
         [0052]    In addition, this invention is not at all limited to the details of the embodiment above described, and this invention can otherwise be practiced within the main point of this invention. 
         [0053]    While the invention is subject to various modifications and alternative forms, specific embodiments thereof are shown by way of embodiment in the drawings and the accompanying detailed description. It should be understood that the drawings and detailed description are not intended to limit the invention to the particular embodiments which are described. This disclosure is instead intended to cover all modifications, equivalents and alternatives falling within the scope of the present invention as defined by the appended claims.