Abstract:
A system for enabling communications between a first circuit block and a second circuit block of a processing system is described. The system has a plurality of registers for storing data from the first block. A steering circuit enables data to be written to one of the plurality of registers depending on the value of a write pointer signal. The data is only written to one the registers selected by the write pointer signal if that register is empty. The system also has a multiplexer to read the data from one of the plurality of registers in response to a read pointer signal. The data is only read from one of the registers selected by the read pointer signal if that register is full. The write and read pointers are each advanced so as to select the register to be written or read in a circular fashion.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention generally relates to communications in a processor, such as a graphics processor, and more particularly to a system and method of performing communications between logic blocks in the processor at high speeds.  
         DESCRIPTION OF THE RELATED ART  
         [0002]    As the speed of graphics engines increases from about 200 MHz to above 200 MHz, the need for more efficient communication between logic blocks has become more important. Referring to FIG. 1, typically two logic blocks in a graphics processor would communicate using simple AVL and ACK signaling. Specifically, if block  0  wanted to know if block  1  was available, then block  0  would send an AVL signal and wait for an ACK response to indicate that block  1  was ready. The ACK signal was generated by logically ‘ANDing’ the AVL signal with the results of the engine availability logic  14 .  
           [0003]    However, there is a delay associated with the receipt of the ACK signal. The delay is equal to:  
           ACK delay =AVL delay +wire delay (block 0 to block 1) +logic delay of engine availability logic+wire delay (block 1 to block 0)    
           [0004]    Accordingly, the delays in the AVL signal logic and the engine availability logic, as well as the wire delays between block  0  and block  1  add up to the total delay in the system. Therefore, the timing delay for the ACK signal (i.e., ACK delay ) may cause the whole system to slow down operations.  
           [0005]    Referring to FIG. 2, the situation is made worse when other blocks are cascaded together. For instance, in FIG. 2, block  0  is accessing block  1  which in turn is accessing block  2 . The total delay to process the ACK signal is:  
           ACK delay =AVL delay +wire delay (block 0 to block 1) +logic delay of engine availability logic block  1 +wire delay (block 1 to block 2)+logic delay of engine availability logic block 2+wire delay   (block 2 to block 1) +wire delay (block 1 to block 0)    
           [0006]    Therefore, it can be seen that, as multiple blocks are cascaded, the timing delay is made worse.  
           [0007]    It is possible to add a register between the two blocks in order to decrease the timing delay. Specifically, referring to FIG. 3, block  1  includes a register  16  for storing data and the AVL status. The data and the AVL signal are clocked into the register  16  using the CLK signal. Block  1  further includes additional logic  18  for determining whether the AVL signal is present and the engine availability logic  14  is ready. By storing the data and AVL signal in the register  16 , it is possible to increase speed of the system by avoiding the wire delays. Yet, by only using one register  16 , data can only be clocked into the system after processing of the ACK signal. Furthermore, if there is a long timing delay in the engine availability logic  14 , then there can still be a delay between block  0  and block  1 .  
           [0008]    Therefore, there is a need for a system and method which efficiently generates a handshaking signal between logic blocks, such as those in a graphics processor.  
         BRIEF SUMMARY OF THE INVENTION  
         [0009]    A method, in accordance with the present invention, includes a method of transferring data between clocked logic blocks. If a first condition is true, the first condition being that data is available from a first logic block and one of a plurality of registers is empty and selected by a write pointer signal, then the empty register selected by the write pointer signal is written to and the write pointer signal is advanced to a next register in circular order. If a second condition is true, the second condition being that a second logic block is capable of accepting data and one of the plurality of registers is full and selected by a read pointer signal, then the full register selected by the read pointer signal is read from and the read pointer signal is advanced to a next register in circular order. In one embodiment, there are two registers, the write and read pointers are each one bit and the write and read pointers are advanced by toggling the respective bits.  
           [0010]    A system, in accordance with the present invention, for transferring data between clocked logic blocks includes a first logic block, a plurality of data registers, a steering circuit, a plurality of binary status flags, a second logic block, a multiplexer, and a handshake control circuit. The first logic block receives a clock signal and generates a block available signal when data is available to be transferred from the first logic block on the clock signal. The plurality of data registers are each configured to hold data received from the first logic block. The steering circuit is configured to couple the data from the first logic block to one of the plurality of data registers based on a write pointer signal. The plurality of binary status flags, where each flag is associated with one of the plurality of data registers, and are configured to indicate whether the associated one of the plurality of data registers is full with first logic block data. The second logic block receives the clock signal and generates an engine available signal when data is available to be accepted by the second logic block on the clock signal. The multiplexer is configured to couple the data from one of the plurality of data registers to the second logic block based on a read pointer signal, and the handshake control circuit receives the clock signal, the block available signal, and the engine available signal, the plurality of status flags and generates the read pointer and the write pointer signals, where the read pointer signal has a value derived from a first condition signal which is a function of the block available signal, the read pointer signal and the plurality of status flags, and the write pointer signal has a value derived from a second condition signal which is a function of the engine available signal, the write pointer signal and the plurality of status flags. In one embodiment, there are two registers, and two binary status flags.  
           [0011]    One advantage of the present invention is that data can be transferred between clocked logic blocks quickly and efficiently, with minimum delay when the blocks are available to be transferred or accepted, but waits if the blocks are not available to be transferred or accepted.  
           [0012]    Another advantage is that waiting for blocks to be available for transfer or acceptance does not adversely impact the speed of the transfer when the blocks are available. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]    These as well as other features of the present invention will become more apparent upon reference to the drawings wherein:  
         [0014]    [0014]FIGS. 1-3 are block diagrams illustrating prior art communications in graphic processors; and  
         [0015]    [0015]FIG. 4 is a system having blocks between which communications in accordance with the present invention are implemented;  
         [0016]    [0016]FIG. 5 is a timing diagram illustrating the handshake operation;  
         [0017]    [0017]FIG. 6 is an embodiment of a portion of the handshaking circuitry;  
         [0018]    [0018]FIG. 7 shows an embodiment, in accordance with the present invention, in which three registers are used to transfer data between blocks;  
         [0019]    [0019]FIG. 8A shows a state machine for advancing a multi-bit write pointer signal; and  
         [0020]    [0020]FIG. 8B shows a state machine for advancing a multi-bit read pointer signal. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0021]    [0021]FIG. 4 shows an embodiment of a transfer logic system in which data is transferred from block  0  (BLK 0 ) to block  1  (BLK 1 ), in accordance with the present invention. A FIFO  410  provides the BLK 0  data. The FIFO block  410  provides an AVL signal and receives an ACK signal. Steering logic (i.e., encoder)  420  receives a ping_wr signal to select either register  0  or register  1  for writing. Associated with register  0  is val 0  and with register  1  is val 1 , which are used to indicate whether the respective registers contain new (un-transferred) BLK 0  data. The outputs of register  0 , register  1 , and the flags val 0  and val 1  are sent to a 2:1 multiplexer  430  which is controlled by a ping_rd signal, to select one of the registers. The encoder, registers, multiplexer, round robin selector  440  and thread controller  450  act as BLK 1 .  
         [0022]    In FIG. 4, the ACK signal indicates whether there is room in one of the registers to accept an entry, the ping_wr signal for pointing to either register  0  or register  1  for writing, a status signal val 0  that indicates when register  0  is empty, val 1  that indicates when register  1  is empty, and the ping_rd signal that points to register  0  or register  1  for reading. The Boolean equation for the ACK signal is  
           ACK= (˜ ping   —   wr  &amp;  ˜val 0)+( ping   —   wr  &amp;  ˜val 1).  
         [0023]    An advantage of the present invention is that the time delay for BLK 0  to receive the ACK signal is short, the delay being the logic delay of ((˜ping_wr &amp; —val 0 )+(ping_wr &amp; ˜val 1 ))+(wire delay from BLK 1  to BLK 0 ). This permits the system to operate at very high frequencies. For example, if the logic delay plus wiring delay is 1 nanoseconds, then the system can operate at about 1 GHz.  
         [0024]    The conditions for writing register  0  are that ping_wr is 0 and val 0  is 0 and data is available (AVL is true). This indicates that register  0  is the target register for the write and that the register is empty. The conditions for writing register  1  are that ping_wr is 1 and val 1  is 0 and data is available (AVL is true). This indicates that register  1  is the target register for the write and that the register is empty. These two conditions are joined and ‘AND’ed with the AVL signal to form a cs_ping_wr signal,  
           cs   —   ping   —   wr= ((˜ ping   —   wr  &amp;  ˜val 0)+( ping   —   wr  &amp;  ˜val 1)) &amp;  AVL.    
         [0025]    The conditions for reading register  0  are that ping_rd is 0 and val 0  is 1. This indicates that register  0  is the target register for the read and that the register is full. The conditions for reading register  1  are that ping_rd is 1 and val 1  is 1 indicating that register  1  is the target register for the read and that the register is full. These two conditions are joined and ‘AND’ed with an engine_available signal (which indicates when the engine is available) to form a cs_ping_rd signal,  
           cs   —   ping   —   rd= (( ping   —   rd  &amp;  val 0)+( ping   —   rd  &amp;  val 1)) &amp; ( engine   —   available ).  
         [0026]    Other helpful, related signals are ping_read_data_avl,  
           ping   —   read   —   data   —   avl= ((˜ ping   —   rd  &amp;  val 0)+( ping   —   rd  &amp;  val 1)), and  R   —   ACK   —   BLK 0 =BLK 0 —   AVL  &amp;  BLK 1 —   ACK.    
         [0027]    The first of these signals indicates the availability of read data, without regard to the engine availability logic, and the second indicates that BLK 0  has data and has received an acknowledge from BLK 1 .  
         [0028]    Generating the ping_rd and ping_wr signals must be done with minimum delay to improve the performance of the handshaking operation. The ping wr signal is initially set to zero, pointing to register  0 . When a write occurs to register  0 , causing register  0  to be full, then ping_wr must change to a 1 to point to register  1 . When register  1  is written, causing register 1 to be full, then ping_wr must change to a 0. If neither register can be written, because both are already full, then ping_wr must not change state. These conditions are summarized by the following equation,  
         ping —wr :=ping_wr ⊕ cs_ping_wr,  
         [0029]    where cs_ping_wr=AVL &amp; ACK, the symbol ⊕ indicates the XOR operation, and the symbol :=indicates that ping_wr changes on the clock edge. Similarly the equation for ping_rd is  
         ping_rd:=ping_rd ⊕ cs_ping_rd.  
         [0030]    Referring now to FIG. 5, the timing diagram, and assuming initially that both register  0  and register  1  are empty (val 0 =0 and val 1 =0) and a block is available (BLK 0 _AVL=1), then cs_ping_wr is a 1. This signal, cs_ping_wr, can be considered a “control input” to the XOR gate, such that when cs_ping_wr is a 0, the ping_wr signal passes through the gate unchanged, but when cs_ping_wr is a 1, the ping_wr signal is inverted. Thus, if ping_wr is 0, pointing to register  0 , then register  0  is written on the next clock edge, clock edge  1 . On this same edge, val 0  becomes 1, and ping_wr is inverted to become 1.  
         [0031]    If data from BLK 0  is still available, now register  1  can be written. On clock edge  2 , register  1  is written with data, and because cs_ping_wr is 1, ping wr is inverted again, via the XOR gate, to become 0. At this point both registers are full, causing cs_ping_wr to become zero on clock edge  2 , which holds the ping_wr signal in its current state, pointing to register  0 .  
         [0032]    When, in the above operations, on clock edge  1 , register  0  is written and val 0  becomes 1, the signal cs_ping_rd becomes true. Assuming that ping_rd is 0, pointing to register  0 , conditions are present to read register  0  on clock edge  2 . This occurs, thus emptying register  0 , setting val 0  to 0, and ping_rd to 1 so that it points to register  1 . Because register  1  is full, val 1  is 1, and cs_ping_rd is still true, register  1  is read on clock edge  3 , which causes ping_rd to become 0, and cs_ping_rd to become 0.  
         [0033]    Continuing with the timing diagram, on clock edge  4  data from BLK 0  becomes available and cs_ping_wr becomes 1. The signal ping_wr is pointing to register  0 , which is empty.  
         [0034]    On clock edge  5 , register  0  is written with the BLK 0  data, cs_ping_wr becomes 0, and ping_wr becomes 1, pointing to register  1 . With cs_ping_wr at a 0, the ping_wr signal is held at 1, awaiting data to become available.  
         [0035]    On clock edge  6 , the data is read from register  0 , and val 0  becomes 0. The signal ping_rd now points to register  1  and the read logic waits for register  1  to become full.  
         [0036]    On clock edge  7 , data becomes available, and on clock  8 , is entered into register 1 . Clock edge  8  also causes, the ping_wr signal to become 0, and val 1  to become 1. Thus, data is now available to be read, but the engine_available signal is 0, indicating that the read logic is not able to take the data. This is indicated by ping_read_data_avl being 1, but cs_ping_rd being 0.  
         [0037]    On clock edge  9 , because data is available from BLK 0 , and register  0  is empty, data is written into register  0  and val 0  becomes 1. At this point both registers are full.  
         [0038]    On clock edge  10 , the engine_available signal becomes 1, indicating that the data can be taken by the read logic. On this edge, cs_ping_rd becomes 1 as well. The signal ping_rd has maintained its state pointing to register  1  while the engine_available signal was 0, because cs_ping_rd was 0.  
         [0039]    On clock edge  11 , the data is read from register  1 , causing val 1  to become 0, and ping_rd to become 0.  
         [0040]    On clock edge  12 , data is read from register  0 , causing val 0  to become 0, and ping_rd to become 1. Now both registers are empty.  
         [0041]    On clock edge  13 , new data becomes available from BLK 0  and cs_ping_wr becomes 1.  
         [0042]    On clock edge  14 , the new data is entered into register  1 , because ping_wr has been kept at a 1, after having written register  0  on clock edge  9 . Also on this edge, val 1  becomes 1, ping_read_data_avl and cs_ping_rd both become 1 and ping_wr becomes 0.  
         [0043]    On clock edge  15 , data is read from register  1 , val 1  becomes 0, ping_rd becomes 0, pointing to register  0 , and both ping read data_avl and cs_ping_rd become 0. At this point both registers are empty. Also, on this edge, data becomes available from BLK  0 .  
         [0044]    On clock edge  16 , data is entered into register  0 , val 0  becomes 1, ping_wr becomes 1, and both cs_ping_rd and ping_read_data_avl become 1.  
         [0045]    On clock edge  17 , data is read from register  0 , val 0  become 0, both ping read_data_avl and cs_ping_rd become 0, and ping_rd becomes 1. Also, on clock edge  17 , data becomes available from BLK 0 .  
         [0046]    On clock edge  18 , data is entered into register  1 , val 1  becomes 1, and both cs_ping_rd and ping_read_data_avl become 1. Data is read on the next edge.  
         [0047]    In summary, the shortest time from data being available in a register to the time it is read is one clock period. However, the logic gracefully handles the case when data is not available or data cannot be taken by the read logic without upsetting the best case timing.  
         [0048]    In one embodiment the ping_wr signal and ping_rd signal are each derived from a flip-flop (here, as a simple illustration, a D-type flip-flop is used) and an XOR gate, as show in FIG. 6. For the ping_rd signal, the XOR gate  610  receives the Q-output of the D flip-flop  620  and the cs_ping_rd signal. The output of the XOR gate  610  is connected to the D input of the flip-flop  620 , which is clocked by the system clock, clk. For the ping_wr signal, the XOR gate  630  receives the Q-output of the D flip-flop  640  and the cs_ping_wr signal. The output of the XOR gate  630  is connected to the D input of the flip-flop  640  which is clocked by the system clock, clk.  
         [0049]    Although the present invention has been described in considerable detail with reference to certain preferred versions thereof, other versions are possible. For example, another version shown in FIG. 7, employs three registers, register  0 , register  1  and register  2 , and three valid bits, val 0 , val 1 , and val 2 , in the transfer of data between BLK 0  and BLK 1 . The registers are selected by the ping_wr signal, which is now a signal having two bits. The encoder in FIG. 7 decodes the ping_wr signal to generate the wr 0 , wr 1  and wr 2  signals, which select the respective registers, register  0 , register 1 , and register  2 . In one alternative, the ping_wr signal has states b&#39; 00 , b&#39; 01 , and b&#39; 10 , state b&#39; 00  decoded to select register  0 , state b&#39; 01  decoded to select register  1  and state b&#39; 10  decoded to select register  2 , thus adhering to selecting the registers in circular order. In another alternative, Grey codes can be used to minimize the decoding.  
         [0050]    The multiplexer in FIG. 7 receives the ping_rd signal which is now also two bits. The different states of the ping_rd signal are decoded in the multiplexer to select one of the registers. In this version, the ping_rd signal is a two bit signal, which has values b&#39; 00 , b&#39; 01  and b&#39; 10 . When ping_rd is b&#39; 00 , the first register is selected, when ping rd is b&#39; 01 , the second register is selected and when ping_rd is b&#39; 10 , the third register is selected, thus adhering to selecting the registers in circular order. Again, Grey coding can be used to minimized the amount of decoding needed.  
         [0051]    The ping_wr signal changes state when the cs_ping_wr signal is true and a clock edge occurs, according to the following algorithm,  
                                                                                                                                   {if(RESET)                ping_wr = ‘00’                else if(cs_ping_wr &amp; ping_wr = = ‘00’)                ping_wr = ‘01’                else if(cs_ping_wr &amp; ping_wr = = ‘01’)                ping_wr = ‘10’                else if(cs_ping_wr &amp; ping_wr = = ‘10’)                ping_wr = ‘00’                }                      
 
         [0052]    This is illustrated as a state machine for ping_wr in FIG. 8A. Also, the cs_ping_wr=(((ping_wr==b&#39; 00 ‘) &amp; ˜val 0 )+((ping_wr==b&#39; 01 &#39;) &amp; ˜val 1 )+((ping_wr==b&#39; 10 &#39;) &amp; ˜val 2 )) &amp; AVL  
         [0053]    The ping_rd signal is implemented in a similar fashion and is shown in the state machine in FIG. 8B. The cs_ping_rd signal is (((ping_rd==b&#39; 00 &#39;) &amp; val 0 )+((ping_rd==b&#39; 01 &#39;) &amp; val 1 )+((ping_rd==b&#39; 10 &#39;) &amp; val 2 )) &amp; (engine_available). Similar adjustments are made to the other signals. Thus, one of skill in the art can see that the present invention is extensible to any number of registers with the appropriate adjustments. Therefore, the spirit and scope of the appended claims should not be limited to the description of the preferred versions contained herein.