Abstract:
A direct conversion receiver and a DC offset cancellation method are provided. An RF module receives a transmission signal to generate an RF signal. A mixer converts the RF signal to a mixer output comprising baseband and imaginary parts. A filter module filters out the imaginary part of the mixer output and adjusts gain of the baseband part to generate a baseband signal. A calibrator performs a calibration to determine a mismatch value of the mixer. A static DC offset canceller provides a constant offset compensation according to the mismatch value; wherein the mismatch value is used to minimize component mismatching effects of the mixer.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a direct conversion receiver, and in particular, to DC offset cancellation in a direct conversion receiver. 
     2. Description of the Related Art 
       FIG. 1   a  shows a conventional direct conversion receiver with mismatch calibration. An RF signal is received through an antenna  102 , and the RF module  104  performs a preliminary adjustment such as low noise amplification (LNA) and bandpass filtering. The mixer  106  then down converts the RF signal to a baseband signal, and the filtering module  108  performs a post adjustment such as low pass filtering (LPF) and programmable gain amplification (PGA) to generate a quality baseband signal before sending to the analog to digital converter (ADC)  110 . DC offset is a common issue induced in direct conversion receivers, degrading down conversion performance. In some cases, a calibrator  112  is provided to calibrate component imbalances in the mixer  106 . The calibrator  112  may be coupled to the mixer  106 , adjusting component mismatches such as resistor imbalance according to DC offset measured from the output of mixer  106  or the filtering module  108 . 
       FIG. 1   b  shows a conventional mixer with an adjustable differential loading pair  120 . As known, DC offset of a mixer  106  is induced from component imbalances possibly occurring in the first switch  126 , second switch  128 , and the transconductance stage  130 . The differential loading pair  120  comprises a first resistor  122  and second resistor  124 , with at least one an adjustable resistor. The mismatch of differential loading pair  120  can be adjusted to minimize the induced DC offset, inducing an optimal mixer output. Thus, the calibrator  112  operates in a calibration mode to adjust the first resistor  122  or second resistor  124  through an adjustment value #adj. When a specific resistor imbalance is found to correspond to the optimal mixer output, the calibrator  112  configures the differential loading pair  120  with that specific resistor imbalance value, and the direct conversion receiver switches to a normal mode, operating with the adjusted mixer  106 . When the direct conversion receiver operates in the normal mode, the calibrator  112  is turned off or removed. Typically, the calibrator  112  is only provided in the manufacturing stage to characterize every mixer  106  in the product line, and each mixer  106  may be configured with different adjustment value #adj in the calibration due to component differences. With a calibrated mixer  106 , a down conversion receiver can operate with optimum performance. 
       FIGS. 2   a  and  2   b  show various implementations of the filtering module  108 . In  FIG. 2   a , three DC offset cancellation (DCOC) loops are shown. The filter  204  and the first DC offset canceller  200  form a first DCOC loop, the filter  212 , amplifier  214  and second DC offset canceller  210  form a second DCOC loop, and the amplifier  222  and third DC offset canceller  220  form a third DCOC loop. Conventionally, the DC offsets are cancelled stage by stage, each consuming a predetermined convergence time. There are various implementations of the DC offset cancellers  200 ,  210  and  220 . The DC offset cancellers  200 ,  210  and  220  may be implemented in analog or digital form, and the convergence speed may be fast or slow.  FIG. 2   b  shows another known implementation of filtering module  108 . The DC offset canceller  230  forms a DCOC loop with amplifier  232 , filter  234  and filter  236  while the DC offset canceller  240  detects and cancels DC offset of the amplifier  242 . Typically, the DC offset cancellers  200  to  240  perform DC offset cancellation by measuring DC offsets from output ends of their loops, and generating compensations to the input of their input ends. 
     IEEE paper “Characterization of IIP2 and DC-Offsets in Transconductance Mixers”, disclose how IIP2 can be calculated as functions of load resistor imbalance and duty cycle mismatch, and the resistor imbalance is tuned to optimize the IIP2 of a mixer. The mixer output tuned by the resistor imbalance may comprise a DC offset comprising static and dynamic parts: 
     
       
         
           
             
               
                 
                   
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     Where ΔA RF  is amplitude difference of the RF signals V RF+  and V RF− ; g m  is conductivity of the components in first switch  126  and second switch  128 , and Δg m  is their mismatch; Δη is duty cycle mismatch of the local oscillation signals V LO+  and V LO− , ΔR is the resistor imbalance of the first resistor  122  and second resistor  124 . By calibrating the mixer  106  with calibrator  112 , the dynamic part can be eliminated by assigning the resistor imbalance ΔR to a specific value, however, the static part still remains and is sent to the filtering module  108 . 
     
       
         
           
             
               
                 
                   
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     BRIEF SUMMARY OF INVENTION 
     An exemplary embodiment of a direct conversion receiver is provided. An RF module receives a transmission signal to generate an RF signal. A mixer converts the RF signal to a mixer output comprising baseband and imaginary parts. A filter module filters out the imaginary part of the mixer output and adjusts gain of the baseband part to generate a baseband signal. A calibrator performs a calibration to determine a mismatch value of the mixer. A static DC offset canceller provides a constant offset compensation according to the mismatch value; and the mismatch value is used to minimize component mismatching effects of the mixer. 
     When the calibrator performs the calibration, the static DC offset canceller is turned off. When the calibrator finishes the calibration and obtains the mismatch value, the calibrator is turned off and the static DC offset canceller is turned on. 
     The calibrator performs the calibration by recursively adjusting a component mismatch of the mixer, and measuring a DC offset of the baseband signal induced by the component mismatch. The value of component mismatch is stored as the mismatch value when a minimum DC offset is induced thereby. The mixer comprises a differential loading pair adjustable by the calibrator, and the component mismatch is a resistor mismatch of the differential load pair. The mismatch value is the optimum resistor mismatch that minimizes component mismatching effects of the mixer. 
     When the mismatch value is applied to the mixer, a static DC offset is induced on the mixer output. The static DC offset canceller directly provides a compensation to eliminate the static DC offset based on the mismatch value. 
     The invention also provides a DC offset cancellation method implemented by the described direct conversion receiver. A detailed description is given in the following embodiments with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1   a  shows a conventional direct conversion receiver with mismatch calibration; 
         FIG. 1   b  shows a conventional mixer with an adjustable differential loading pair; 
         FIGS. 2   a  and  2   b  show various implementations of the filtering stages; 
         FIG. 3  shows an embodiment of a direct conversion receiver; and 
         FIG. 4  is a flowchart of a DC offset cancellation method according to an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF INVENTION 
     The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
       FIG. 3  shows an embodiment of a direct conversion receiver. Like in  FIG. 1   a , an RF signal is received through an antenna  102 , and the RF module  104  performs a preliminary adjustment such as low noise amplification (LNA) and bandpass filtering. The mixer  106  then down converts the RF signal to a baseband signal, and the filtering module  108  performs a post adjustment such as low pass filtering (LPF) and programmable gain amplification (PGA) to generate a quality baseband signal before sending to the analog to digital converter  110 . 
     In the embodiment, a static DC offset canceller  302  is provided, coupled to the output of mixer  106 . The static DC offset canceller  302  is designed to compensate the static part of the DC offset induced by the resistor imbalance ΔR of the first resistor  122  and second resistor  124  as shown in equation (3). In this way, the DCOC loops in the filtering module  108  shown in  FIGS. 2   a  and  2   b  are not burdened by the effects of resistor imbalance ΔR, thus performance is improved. As described, the mixer  106  is calibrated by the calibrator  112  with an adjustment value #adj. The differential loading pair  120  in  FIG. 1   b  may comprise a binary weighted resistor providing equivalent resistance in response to the adjustment value #adj. The adjustment value #adj may be stored in the mixer  106  after calibration, and when the direct conversion receiver operates in normal mode, the mixer  106  and static DC offset canceller  302  can read the adjustment value #adj to perform corresponding compensations. 
     The calibration may be performed only one time when manufacturing the mixer  106 . When the calibrator  112  performs the calibration, the static DC offset canceller  302  is turned off, and other DC offset cancellers in the filtering module  108  as shown in  FIGS. 2   a  and  2   b , may also be disabled while calibrating. 
     A calibration process can be performed as follows. A DC offset (VDC_ 0 ) is detected when no RF signal is received by the RF module  104 . VDC_ 0  can be calculated by formula (3) (V DC     —     static ). Take GSM for example, if a wanted signal is 900 MHz, blocker signals (894 MHz and 906 MHz) are used in a calibration mode to test what an induced DC offset will be at the output of the filtering module  108 . That is, a test is performed to see how a blocker signal can affect the DC offset at the output of the filtering module  108 . 
     Then, a blocker signal (906 MHz) is sent and received by the RF module  104 . A DC offset (VDC_ 1 ) is detected again. VDC_ 1  can be calculated by formula (1) (V DC ). That is, VDC_ 1  includes V DC     —     static  and V DC     —     dynamic . By subtracting VDC_ 0  from VDC_ 1 , V DC     —     dynamic  can be obtained. 
     Many trial adjustment value #adj can be used to adjust ΔR. For each trial adjustment value #adj, V DC     —     dynamic  can be obtained by the above-mentioned method. Among the measured results corresponding to the trial adjustment value #adj, an optimum V DC     —     dynamic  may be found (that is, V DC     —     dynamic =0), and the corresponding adjustment value #adj is taken as the calibration result. 
     When the calibrator  112  finishes the calibration and obtains the optimum adjustment value #adj, the calibrator  112  is turned off since it is no longer necessary, and the DCOC loops in the filtering module  108  as well as the static DC offset canceller  302 , are turned on for normal operation. 
     As shown in  FIG. 1   b , the mixer  106  comprises a differential loading pair  120  adjustable by the calibrator. The embodiment adjusts a resistor mismatch of the differential loading pair  120  by the adjustment value #adj. Thus, the optimum adjustment value #adj renders an optimum resistor mismatch that minimizes other component mismatching effects of the mixer. Specifically, the dynamic part of the DC offset as described in formula (2) can be eliminated through this calibration, and only the static part of the DC offset as shown in formula (3) is output. 
     As the mixer  106  operates in normal mode with the optimum adjustment value #adj applied, a static part of DC offset as formula (3) is induced on the mixer  106  output. The DC offset as formula (3) can be increased or decreased because ΔR has been changed by the adjustment value #adj. The static DC offset canceller  302  is enabled in normal mode, directly providing a compensation to eliminate the static part of DC offset based on the resistor imbalance ΔR of the differential loading pair  120 . Specifically, the static DC offset canceller  302  generates a complementary DC offset having same magnitude of formula (3) to cancel the static part of DC offset. With the calibrated mixer  106  and the static DC offset canceller  302 , the input of filtering module  108  can be optimized to a zero DC offset signal. 
     In the embodiment, the static DC offset canceller  302  may be a single block unit, or implemented by combination with conventional DCOC loops. For example, the filtering module  108  may comprise an integrated unit  304  connected to the output of mixer. The integrated unit  304  may be a low pass filter (LPF) or a programmable gain amplifier (PGA), inducing additional component dependent DC offsets. The static DC offset canceller  302  may form a DCOC loop with the integrated unit  304 , simultaneously eliminating the additional component dependent DC offsets induced by the integrated unit  304  and the static DC offset induced by the mixer  106 . Furthermore, the DC offset canceller  230  in  FIG. 2   b  may be modified to include the function of the static DC offset canceller  302 . In an alternative case, the constant offset compensation may not be limited to be identical to the static part of DC offset as formula (3). Since the scale of adjustable resistor in the differential loading pair  120  is a known parameter, the possible range of resistor imbalance ΔR is also a bounded value. If the DC offset canceller  230  is modified to include the constant offset compensation, the constant offset may be selected to be an average of the possible range of resistor imbalance ΔR. Over a period of convergence time, the modified DC offset canceller  230  will converge to automatically balance the DC offset in its DCOC loop. If the DC offset canceller  230  is originally a slow convergence unit, including the constant offset compensation can increase its convergence performance. 
     In general, the embodiment allows any variation of the DCOC loop to eliminate the static DC offset at the input end of filtering module  108  before it is amplified in the stages thereafter. Furthermore, the DC offset canceller  302  or the variations can be digital signal processing circuits in the embodiment. 
       FIG. 4  is a flowchart of a DC offset cancellation method according to an embodiment of the invention. Steps  402 ,  404  and  406  are calibration mode, and steps  408  and  410  are normal mode. In step  402 , the calibrator  112  recursively delivers various trial adjustment values #adj to the mixer  106 . In step  404 , the DC offset induced by the mixer  106  is measured by the calibrator  112 . In step  406 , the calibrator  112  determines whether an optimum DC offset is found (that is, V DC     —     dynamic =0). If not, the calibration loops to step  402 . If an optimum DC offset corresponding to an adjustment value #adj is found, the mixer  106  records the adjustment value #adj as a calibration mode, and the calibrator  112  is turned off or removed. When the direct conversion receiver operates in normal mode, a wanted RF signal is converted to a mixer output by the mixer  106 . In step  408 , since the mixer  106  is calibrated, dynamic part of the DC offset as shown in formula (2) is eliminated. However, a static part as formula (3) is induced due to the resistor imbalance generated by the calibration. In step  410 , the static DC offset canceller  302  is enabled to eliminate static part of the DC offset. 
     While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.