Abstract:
An integrated circuit includes transistors in rows and columns providing an array, conductive lines in columns across the array, and resistivity changing material elements contacting the conductive lines and self-aligned to the conductive lines. The integrated circuit includes electrodes contacting the resistivity changing material elements, each electrode self-aligned to a conductive line and coupled to one side of a source-drain path of a transistor.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This Divisional application claims the benefit of Utility patent application Ser. No. 11/366,370, filed on Mar. 2, 2006, and which is herein incorporated by reference. 
     
    
     BACKGROUND 
       [0002]    One type of non-volatile memory is resistive memory. Resistive memory utilizes the resistance value of a memory element to store one or more bits of data. For example, a memory element programmed to have a high resistance value may represent a logic “1” data bit value, and a memory element programmed to have a low resistance value may represent a logic “0” data bit value. The resistance value of the memory element is switched electrically by applying a voltage pulse or a current pulse to the memory element. One type of resistive memory is phase change memory. Phase change memory uses a phase change material for the resistive memory element. 
         [0003]    Phase change memories are based on phase change materials that exhibit at least two different states. Phase change material may be used in memory cells to store bits of data. The states of phase change material may be referred to as amorphous and crystalline states. The states may be distinguished because the amorphous state generally exhibits higher resistivity than does the crystalline state. Generally, the amorphous state involves a more disordered atomic structure, while the crystalline state involves a more ordered lattice. Some phase change materials exhibit more than one crystalline state, e.g. a face-centered cubic (FCC) state and a hexagonal closest packing (HCP) state. These two crystalline states have different resistivities and may be used to store bits of data. 
         [0004]    Phase change in the phase change materials may be induced reversibly. In this way, the memory may change from the amorphous state to the crystalline state and from the crystalline state to the amorphous state in response to temperature changes. The temperature changes to the phase change material may be achieved in a variety of ways. For example, a laser can be directed to the phase change material, current may be driven through the phase change material, or current can be fed through a resistive heater adjacent the phase change material. In any of these methods, controllable heating of the phase change material causes controllable phase change within the phase change material. 
         [0005]    A phase change memory including a memory array having a plurality of memory cells that are made of phase change material may be programmed to store data utilizing the memory states of the phase change material. One way to read and write data in such a phase change memory device is to control a current and/or a voltage pulse that is applied to the phase change material. The level of current and/or voltage generally corresponds to the temperature induced within the phase change material in each memory cell. 
         [0006]    For data storage applications, reducing the physical memory cell size is a continuing goal. Reducing the physical memory cell size increases the storage density of the memory and reduces the cost of the memory. To reduce the physical memory cell size, the memory cell layout should be lithography friendly. In addition, since interface resistances between metal and active material within memory cells contributes considerably to the overall resistance for small areas, the interface areas should be well controlled. Finally, the memory cell layout should have mechanical stability to improve the chemical mechanical planarization (CMP) process window to enable greater yields. 
         [0007]    For these and other reasons, there is a need for the present invention. 
       SUMMARY 
       [0008]    One embodiment of the present invention provides a memory. The memory includes transistors in rows and columns providing an array, conductive lines in columns across the array, and phase change elements contacting the conductive lines and self-aligned to the conductive lines. The memory includes bottom electrodes contacting the phase change elements, each bottom electrode self-aligned to a conductive line and coupled to one side of a source-drain path of a transistor. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. 
           [0010]      FIG. 1  is a diagram illustrating one embodiment of an array of phase change memory cells. 
           [0011]      FIG. 2A  illustrates a cross-sectional view of one embodiment of an array of phase change memory cells. 
           [0012]      FIG. 2B  illustrates a perpendicular cross-sectional view of the array of phase change memory cells illustrated in  FIG. 2A . 
           [0013]      FIG. 2C  illustrates a top view of the array of phase change memory cells illustrated in  FIG. 2A . 
           [0014]      FIG. 3A  illustrates a cross-sectional view of one embodiment of a preprocessed wafer. 
           [0015]      FIG. 3B  illustrates a perpendicular cross-sectional view of the preprocessed wafer illustrated in  FIG. 3A . 
           [0016]      FIG. 3C  illustrates a top cross-sectional view of the preprocessed wafer illustrated in  FIG. 3A . 
           [0017]      FIG. 3D  illustrates a top view of the preprocessed wafer illustrated in  FIG. 3A . 
           [0018]      FIG. 4  illustrates a cross-sectional view of one embodiment of the preprocessed wafer, a first electrode material layer, and a first phase change material layer. 
           [0019]      FIG. 5  illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first electrode material layer, and first phase change material layer after etching. 
           [0020]      FIG. 6A  illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first electrode material layer, first phase change material layer, and a dielectric material layer. 
           [0021]      FIG. 6B  illustrates a perpendicular cross-sectional view of the wafer illustrated in  FIG. 6A . 
           [0022]      FIG. 6C  illustrates a top view of the wafer illustrated in  FIG. 6A . 
           [0023]      FIG. 7A  illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first electrode material layer, first phase change material layer, dielectric material layer, a second phase change material layer, and a second electrode material layer. 
           [0024]      FIG. 7B  illustrates a perpendicular cross-sectional view of the wafer illustrated in  FIG. 7A . 
           [0025]      FIG. 8A  illustrates a cross-sectional view of one embodiment of the preprocessed wafer, bottom electrodes, first phase change material layer, a second phase change material layer, and bit lines after etching. 
           [0026]      FIG. 8B  illustrates a perpendicular cross-sectional view of the wafer illustrated in  FIG. 8A . 
           [0027]      FIG. 8C  illustrates a top view of the wafer illustrated in  FIG. 8A . 
           [0028]      FIG. 9A  illustrates a cross-sectional view of one embodiment of a preprocessed wafer. 
           [0029]      FIG. 9B  illustrates a perpendicular cross-sectional view of the preprocessed wafer illustrated in  FIG. 9A . 
           [0030]      FIG. 9C  illustrates a top cross-sectional view of the preprocessed wafer illustrated in  FIG. 9A . 
           [0031]      FIG. 9D  illustrates a top view of the preprocessed wafer illustrated in  FIG. 9A . 
           [0032]      FIG. 10  illustrates a cross-sectional view of one embodiment of the preprocessed wafer, a first electrode material layer, and a hardmask material layer. 
           [0033]      FIG. 11  illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first electrode material layer, and hardmask material layer after etching. 
           [0034]      FIG. 12  illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first electrode material layer, hardmask material layer, and a dielectric material layer. 
           [0035]      FIG. 13A  illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first electrode material layer, and dielectric material layer after removing the hardmask. 
           [0036]      FIG. 13B  illustrates a perpendicular cross-sectional view of the wafer illustrated in  FIG. 13A . 
           [0037]      FIG. 13C  illustrates a top view of the wafer illustrated in  FIG. 13A . 
           [0038]      FIG. 14A  illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first electrode material layer, dielectric material layer, a phase change material layer, and a second electrode material layer. 
           [0039]      FIG. 14B  illustrates a perpendicular cross-sectional view of the wafer illustrated in  FIG. 14A . 
           [0040]      FIG. 15A  illustrates a cross-sectional view of one embodiment of the preprocessed wafer, bottom electrodes, dielectric material layer, a phase change material layer, and bit lines after etching. 
           [0041]      FIG. 15B  illustrates a perpendicular cross-sectional view of the wafer illustrated in  FIG. 15A . 
           [0042]      FIG. 15C  illustrates a top view of the wafer illustrated in  FIG. 15A . 
           [0043]      FIG. 16A  illustrates a cross-sectional view of another embodiment of an array of phase change memory cells. 
           [0044]      FIG. 16B  illustrates a perpendicular cross-sectional view of the array of phase change memory cells illustrated in  FIG. 16A . 
           [0045]      FIG. 16C  illustrates a top view of the array of phase change memory cells illustrated in  FIG. 16A . 
           [0046]      FIG. 17A  illustrates a cross-sectional view of one embodiment of a preprocessed wafer. 
           [0047]      FIG. 17B  illustrates a perpendicular cross-sectional view of the preprocessed wafer illustrated in  FIG. 17A . 
           [0048]      FIG. 17C  illustrates a top cross-sectional view of the preprocessed wafer illustrated in  FIG. 17A . 
           [0049]      FIG. 17D  illustrates a top view of the preprocessed wafer illustrated in  FIG. 17A . 
           [0050]      FIG. 18  illustrates a cross-sectional view of one embodiment of the preprocessed wafer, a first electrode material layer, and a phase change material layer. 
           [0051]      FIG. 19  illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first electrode material, and phase change material layer after etching. 
           [0052]      FIG. 20A  illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first electrode material layer, phase change material layer, and a dielectric material layer. 
           [0053]      FIG. 20B  illustrates a perpendicular cross-sectional view of the wafer illustrated in  FIG. 20A . 
           [0054]      FIG. 20C  illustrates a top view of the wafer illustrated in  FIG. 20A . 
           [0055]      FIG. 21A  illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first electrode material layer, phase change material layer, dielectric material layer, and a second electrode material layer. 
           [0056]      FIG. 21B  illustrates a perpendicular cross-sectional view of the wafer illustrated in  FIG. 21A . 
           [0057]      FIG. 22A  illustrates a cross-sectional view of one embodiment of the preprocessed wafer, bottom electrodes, phase change elements, and bit lines after etching. 
           [0058]      FIG. 22B  illustrates a perpendicular cross-sectional view of the wafer illustrated in  FIG. 22A . 
           [0059]      FIG. 22C  illustrates a top view of the wafer illustrated in  FIG. 22A . 
           [0060]      FIG. 23A  illustrates a cross-sectional view of another embodiment of an array of phase change memory cells. 
           [0061]      FIG. 23B  illustrates a perpendicular cross-sectional view of the array of phase change memory cells illustrated in  FIG. 23A . 
           [0062]      FIG. 23C  illustrates a top view of the array of phase change memory cells illustrated in  FIG. 23A . 
           [0063]      FIG. 24A  illustrates a cross-sectional view of one embodiment of a preprocessed wafer. 
           [0064]      FIG. 24B  illustrates a perpendicular cross-sectional view of the preprocessed wafer illustrated in  FIG. 24A . 
           [0065]      FIG. 24C  illustrates a top cross-sectional view of the preprocessed wafer illustrated in  FIG. 24A . 
           [0066]      FIG. 24D  illustrates a top view of the preprocessed wafer illustrated in  FIG. 24A . 
           [0067]      FIG. 25  illustrates a cross-sectional view of one embodiment of the preprocessed wafer, a first electrode material layer, a phase change material layer, and a second electrode material layer. 
           [0068]      FIG. 26  illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first electrode material layer, phase change material layer, and second electrode material layer after etching. 
           [0069]      FIG. 27A  illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first electrode material layer, phase change material layer, second electrode material layer, and a dielectric material layer. 
           [0070]      FIG. 27B  illustrates a perpendicular cross-sectional view of the wafer illustrated in  FIG. 27A . 
           [0071]      FIG. 27C  illustrates a top view of the wafer illustrated in  FIG. 27A . 
           [0072]      FIG. 28A  illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first electrode material layer, phase change material layer, second electrode material layer, dielectric material layer, and a third electrode material layer. 
           [0073]      FIG. 28B  illustrates a perpendicular cross-sectional view of the wafer illustrated in  FIG. 28A . 
           [0074]      FIG. 29A  illustrates a cross-sectional view of one embodiment of the preprocessed wafer, bottom electrodes, phase change material elements, top electrodes, dielectric material layer, and bit lines after etching. 
           [0075]      FIG. 29B  illustrates a perpendicular cross-sectional view of the wafer illustrated in  FIG. 29A . 
           [0076]      FIG. 29C  illustrates a top view of the wafer illustrated in  FIG. 29A . 
       
    
    
     DETAILED DESCRIPTION 
       [0077]    In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. 
         [0078]      FIG. 1  is a diagram illustrating one embodiment of an array of phase-change memory cells  100 . Memory array  100  is fabricated using line lithography and self-aligned processing to minimize critical lithography steps. In addition, the interface resistance between metal and active material is overlay-insensitive and by maximizing the interface areas, parasitic resistances are minimized. Memory array  100  does not have any isolated, small patterns such that the chemical mechanical planarization (CMP) process window is improved and mechanical stability is improved. 
         [0079]    Memory array  100  includes a plurality of phase-change memory cells  104   a - 104   d  (collectively referred to as phase-change memory cells  104 ), a plurality of bit lines (BLs)  112   a - 112   b  (collectively referred to as bit lines  112 ), a plurality of word lines (WLs)  110   a - 110   b  (collectively referred to as word lines  110 ), and a plurality of ground lines (GLs)  114   a - 114   b  (collectively referred to as ground lines  114 ). 
         [0080]    As used herein, the term “electrically coupled” is not meant to mean that the elements must be directly coupled together and intervening elements may be provided between the “electrically coupled” elements. 
         [0081]    Each phase-change memory cell  104  is electrically coupled to a word line  110 , a bit line  112 , and a ground line  114 . For example, phase-change memory cell  104   a  is electrically coupled to bit line  112   a , word line  110   a , and ground line  114   a , and phase-change memory cell  104   b  is electrically coupled to bit line  112   a , word line  110   b , and ground line  114   b . Phase-change memory cell  104   c  is electrically coupled to bit line  112   b , word line  110   a , and ground line  114   a , and phase-change memory cell  104   d  is electrically coupled to bit line  112   b , word line  110   b , and ground line  114   b.    
         [0082]    Each phase-change memory cell  104  includes a phase-change element  106  and a transistor  108 . While transistor  108  is a field-effect transistor (FET) in the illustrated embodiment, in other embodiments, transistor  108  can be another suitable device such as a bipolar transistor or a 3D transistor structure. Phase-change memory cell  104   a  includes phase-change element  106   a  and transistor  108   a . One side of phase-change element  106   a  is electrically coupled to bit line  112   a , and the other side of phase-change element  106   a  is electrically coupled to one side of the source-drain path of transistor  108   a . The other side of the source-drain path of transistor  108   a  is electrically coupled to ground line  114   a . The gate of transistor  108   a  is electrically coupled to word line  110   a . Phase-change memory cell  104   b  includes phase-change element  106   b  and transistor  108   b . One side of phase-change element  106   b  is electrically coupled to bit line  112   a , and the other side of phase-change element  106   b  is electrically coupled to one side of the source-drain path of transistor  108   b . The other side of the source-drain path of transistor  108   b  is electrically coupled to ground line  114   b . The gate of transistor  108   b  is electrically coupled to word line  110   b.    
         [0083]    Phase-change memory cell  104   c  includes phase-change element  106   c  and transistor  108   c . One side of phase-change element  106   c  is electrically coupled to bit line  112   b  and the other side of phase-change element  106   c  is electrically coupled to one side of the source-drain path of transistor  108   c . The other side of the source-drain path of transistor  108   c  is electrically coupled to ground line  114   a . The gate of transistor  108   c  is electrically coupled to word line  110   a . Phase-change memory cell  104   d  includes phase-change element  106   d  and transistor  108   d . One side of phase-change element  106   d  is electrically coupled to bit line  112   b  and the other side of phase-change element  106   d  is electrically coupled to one side of the source-drain path of transistor  108   d . The other side of the source-drain path of transistor  108   d  is electrically coupled to ground line  114   b . The gate of transistor  108   d  is electrically coupled to word line  110   b.    
         [0084]    In another embodiment, each phase-change element  106  is electrically coupled to a ground line  114  and each transistor  108  is electrically coupled to a bit line  112 . For example, for phase-change memory cell  104   a , one side of phase-change element  106   a  is electrically coupled to ground line  114   a . The other side of phase-change element  106   a  is electrically coupled to one side of the source-drain path of transistor  108   a . The other side of the source-drain path of transistor  108   a  is electrically coupled to bit line  112   a . In general, the ground lines  114  have a lower potential than the bit lines  112 . 
         [0085]    Each phase-change element  106  comprises a phase-change material that may be made up of a variety of materials in accordance with the present invention. Generally, chalcogenide alloys that contain one or more elements from group VI of the periodic table are useful as such materials. In one embodiment, the phase-change material of phase-change element  106  is made up of a chalcogenide compound material, such as GeSbTe, SbTe, GeTe or AgInSbTe. In another embodiment, the phase-change material is chalcogen free, such as GeSb, GaSb, InSb, or GeGaInSb. In other embodiments, the phase-change material is made up of any suitable material including one or more of the elements Ge, Sb, Te, Ga, As, In, Se, and S. 
         [0086]    During a set operation of phase-change memory cell  104   a , a set current or voltage pulse is selectively enabled and sent through bit line  112   a  to phase-change element  106   a  thereby heating it above it&#39;s crystallization temperature (but usually below it&#39;s melting temperature) with word line  110   a  selected to activate transistor  108   a . In this way, phase-change element  106   a  reaches its crystalline state during this set operation. During a reset operation of phase-change memory cell  104   a , a reset current or voltage pulse is selectively enabled to bit line  112   a  and sent to phase-change material element  106   a . The reset current or voltage quickly heats phase-change element  106   a  above its melting temperature. After the current or voltage pulse is turned off, the phase-change element  106   a  quickly quench cools into the amorphous state. Phase-change memory cells  104   b - 104   d  and other phase-change memory cells  104  in memory array  100  are set and reset similarly to phase-change memory cell  104   a  using a similar current or voltage pulse. 
         [0087]      FIG. 2A  illustrates a cross-sectional view of one embodiment of an array of phase change memory cells  200   a .  FIG. 2B  illustrates a perpendicular cross-sectional view of array of phase change memory cells  200   a  illustrated in  FIG. 2A .  FIG. 2C  illustrates a top view of array of phase change memory cells  200   a  illustrated in  FIG. 2A . In one embodiment, array of phase change memory cells  100  is similar to array of phase change memory cells  200   a . Array of phase change memory cells  200   a  includes substrate  212 , transistors  108 , word lines  110 , first contacts  206 , second contacts  208 , ground lines  114 , bottom electrodes  240 , dielectric material  204 ,  210 , and  216 , shallow trench isolation (STI)  214 , inter level dielectric (ILD)  215 , phase change material  107 , and bits lines  112 . Metal wiring (not shown) follows after the bit line level. 
         [0088]    Transistors  108  for selecting storage locations  105  in phase change material  107  are formed in substrate  212  in rows and columns. The gates of transistors  108  are electrically coupled to word lines  110 . Dielectric material  210  is deposited over transistors  108  and word lines  110 . First contacts  206  electrically couple one side of the source-drain path of each transistor  108  to a ground line  114 . Second contacts  208  electrically couple the other side of the source-drain path of each transistor  108  to a bottom electrode  240 . Each bottom electrode  240  is electrically coupled to a storage location  105 , which is a part of phase change material  107 . Each line of phase change material  107  is electrically coupled to a bit line  112 . Bit lines  112  are perpendicular to word lines  110  and ground lines  114 . Dielectric material  204  insulates ground lines  114  above first contacts  206 . Dielectric material  216  insulates bits lines  112 , lines of phase change material  107 , and bottom electrodes  240  from adjacent bit lines  112 , lines of phase change material  107 , and bottom electrodes  240 . STI  214  insulates transistors  108  from adjacent transistors  108 , and ILD  215  insulates second contacts  208  from adjacent second contacts  208 . 
         [0089]    Lines of phase change material  107 , which include storage locations  105 , and bottom electrodes  240  are self-aligned to bit lines  112 . The self-alignment minimizes critical lithography steps in the fabrication of array of phase change memory cells  200   a . In addition, with self-alignment the interface resistances between bottom electrodes  240  and phase change material  107  and between phase change material  107  and bit lines  112  is overlay insensitive and parasitic resistances are minimized. 
         [0090]    In one embodiment, array of phase change memory cells  200   a  is scalable to 8F 2  for dual gate memory cells, where “F” is the minimum feature size, or to 6F 2  for single gate memory cells. In the embodiment for single gate memory cells, an active gate of a transistor  108  between every two adjacent memory cells is replaced with an isolation gate (i.e., the transistor is not used as a switch; rather it is always turned off). A first embodiment of a method for fabricating array of phase change memory cells  200   a  is described and illustrated with reference to the following  FIGS. 3A-8C . A second embodiment of a method for fabricating array of phase change memory cells  200   a  is described and illustrated with reference to the following  FIGS. 9A-15C . 
         [0091]      FIG. 3A  illustrates a cross-sectional view of one embodiment of a preprocessed wafer  218 .  FIG. 3B  illustrates a perpendicular cross-sectional view of preprocessed wafer  218  illustrated in  FIG. 3A .  FIG. 3C  illustrates a top cross-sectional view of preprocessed wafer  218  illustrated in  FIG. 3A .  FIG. 3D  illustrates a top view of preprocessed wafer  218  illustrated in  FIG. 3A . Preprocessed wafer  218  includes substrate  212 , transistors  108 , word lines  110 , first contacts  206 , second contacts  208 , ground lines  114 , STI  214 , ILD  215 , and dielectric material  210 . 
         [0092]    Transistors  108  are formed in substrate  212  in rows and columns. The gates of transistors  108  are electrically coupled to word lines  110 . Dielectric material  210  is deposited over transistors  108  and word lines  110 . First contacts  206  electrically couple one side of the source-drain path of each transistor  108  to a ground line  114 . Second contacts  208  are electrically coupled to the other side of the source-drain path of each transistor  108 . STI  214  insulates transistors  108  from adjacent transistors  108 , and ILD  215  insulates second contacts  208  from adjacent second contacts  208 . 
         [0093]    First contacts  206  and second contacts  208  are contact plugs, such as W plugs, Cu plugs, or other suitable conducting material plugs. Word lines  110  comprise doped poly-Si, W, TiN, NiSi, CoSi, TiSi, WSiW, or another suitable material. Ground lines  114  comprise W, Al, Cu, or other suitable material. Dielectric material  210  comprises SiN or other suitable material that enables a borderless contact formation process for first contacts  206  and second contacts  208 . STI  214  and ILD  215  comprise SiO 2 , fluorinated silica glass (FSG), boro-phosphorous silicate glass (BPSG), boro-silicate glass (BSG), or other suitable dielectric material. Word lines  110  are parallel to ground lines  114 . Word lines  110  and ground lines  114  are perpendicular to STI  214  and ILD  215 . 
         [0094]      FIG. 4  illustrates a cross-sectional view of one embodiment of preprocessed wafer  218 , a first electrode material layer  240   a , and a first phase change material layer  107   a . Electrode material, such as TiN, TaN, W, Al, Cu, TiSiN, TaSiN, or other suitable electrode material, is deposited over preprocessed wafer  218  to provide first electrode material layer  240   a . First electrode material layer  240   a  is deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), metal organic chemical vapor deposition (MOCVD), plasma vapor deposition (PVD), jet vapor deposition (JVP), or other suitable deposition technique. 
         [0095]    Phase change material, such as a chalcogenide compound material or other suitable phase change material, is deposited over first electrode material layer  240   a  to provide first phase change material layer  107   a . First phase change material layer  107   a  is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique. In one embodiment, an optional hardmask material layer is deposited over first phase change material layer  107   a.    
         [0096]      FIG. 5  illustrates a cross-sectional view of one embodiment of preprocessed wafer  218 , first electrode material layer  240   b , and first phase change material layer  107   b  after etching first phase change material layer  107   a  and first electrode material layer  240   a . First phase change material layer  107   a  and first electrode material layer  240   a  are etched to provide first phase change material layer  107   b  and first electrode material layer  240   b , which is self-aligned to first phase change material layer  107   b . Line lithography is used to pattern lines of first phase change material  107   b  and first electrode material  240   b  contacting second contacts  208 . The line lithography does not need to be precisely centered over second contacts  208  as long as a portion of first electrode material  240   b  contacts second contacts  208 . In this way, the line lithography is less critical yet the desired memory cell size is obtained. 
         [0097]    In the embodiment where a hardmask material layer is deposited over first phase change material layer  107   a , the hardmask material layer, first phase change material layer  107   a , and first electrode material layer  240   a  are etched to provide an etched hardmask material layer, first phase change material layer  107   b , which is self-aligned to the etched hardmask material layer, and first electrode material layer  240   b , which is self-aligned to first phase change material layer  107   b.    
         [0098]      FIG. 6A  illustrates a cross-sectional view of one embodiment of preprocessed wafer  218 , first electrode material layer  240   b , first phase change material layer  107   b , and a dielectric material layer  204   a .  FIG. 6B  illustrates a perpendicular cross-sectional view of the wafer illustrated in  FIG. 6A , and  FIG. 6C  illustrates a top view of the wafer illustrated in  FIG. 6A . Dielectric material, such as SiO 2 , FSG, BPSG, BSG, or other suitable dielectric material, is deposited over exposed portions of first phase change material layer  107   b , first electrode material layer  240   b , and preprocessed wafer  218 . The dielectric material layer is deposited using CVD, ALD, MOCVD, PVD, JVP, high-density plasma (HDP), or other suitable deposition technique. The dielectric material layer is planarized to expose first phase change material layer  107   b  and provide dielectric material layer  204   a . The dielectric material layer is planarized using CMP or another suitable planarization technique. In the embodiment where an etched hardmask material layer is over first phase change material layer  107   b , the dielectric material layer is planarized to expose the hardmask material. The hardmask material is then removed using a wet etch or other suitable technique. 
         [0099]      FIG. 7A  illustrates a cross-sectional view of one embodiment of preprocessed wafer  218 , first electrode material layer  240   b , first phase change material layer  107   b , dielectric material layer  204   a , a second phase change material layer  107   c , and a second electrode material layer  113   a .  FIG. 7B  illustrates a perpendicular cross-sectional view of the wafer illustrated in  FIG. 7A . Phase change material, such as a chalcogenide compound material or other suitable phase change material, is deposited over first phase change material layer  107   b  and dielectric material layer  204   a  to provide second phase change material layer  107   c . Second phase change material layer  107   c  is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique. 
         [0100]    Electrode material, such as TiN, TaN, W, Al, Cu, TiSiN, TaSiN, or other suitable electrode material, is deposited over second phase change material layer  107   c  to provide second electrode material layer  113   a . Second electrode material layer  113   a  is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique. 
         [0101]      FIG. 8A  illustrates a cross-sectional view of one embodiment of preprocessed wafer  218 , bottom electrodes  240 , first phase change material layer  107   d , dielectric material layer  204 , second phase change material layer  107   e , and bit lines  112  after etching second electrode material layer  113   a , second phase change material layer  107   c , first phase change material layer  107   b , dielectric material layer  204   a , and first electrode material layer  240   b .  FIG. 8B  illustrates a perpendicular cross-sectional view of the wafer illustrated in  FIG. 8A , and  FIG. 8C  illustrates a top view of the wafer illustrated in  FIG. 8A . Second electrode material layer  113   a , second phase change material layer  107   c , first phase change material layer  107   b , dielectric material layer  204   a , and first electrode material layer  240   b  are etched to provide bit lines  112 , second phase change material layer  107   e , which is self-aligned to bit lines  112 , first phase change material layer  107   d , which is self-aligned to bit lines  112 , bottom electrodes  240 , which are self-aligned to bit lines  112 , and dielectric material layer  204 . Line lithography is used to pattern bit lines  112  and lines of second phase change material  107   e  perpendicular to lines of phase change material  107   b  such that each bottom electrode  240  contacts a second contact  208 . The line lithography does not need to be precisely centered over second contacts  208  as long as a portion of each bottom electrode  240  contacts a second contact  208 . In this way, the line lithography is less critical yet the desired memory cell size is obtained. 
         [0102]    Dielectric material, such as SiO 2 , FSG, BPSG, BSG, or other suitable dielectric material, is deposited over exposed portions of bit lines  112 , second phase change material layer  107   e , first phase change material layer  107   d , dielectric material layer  204 , bottom electrodes  240 , and preprocessed wafer  218 . The dielectric material layer is deposited using CVD, ALD, MOCVD, PVD, JVP, HDP, or other suitable deposition technique. The dielectric material layer is planarized to expose bit lines  112  and provide dielectric material layer  216 . The dielectric material layer is planarized using CMP or another suitable planarization technique to provide array of phase change memory cells  200   a  illustrated in  FIGS. 2A-2C . 
         [0103]      FIG. 9A  illustrates a cross-sectional view of one embodiment of a preprocessed wafer  218 .  FIG. 9B  illustrates a perpendicular cross-sectional view of preprocessed wafer  218  illustrated in  FIG. 9A .  FIG. 9C  illustrates a top cross-sectional view of preprocessed wafer  218  illustrated in  FIG. 9A . 
         [0104]      FIG. 9D  illustrates a top view of preprocessed wafer  218  illustrated in  FIG. 9A . Preprocessed wafer  218  includes substrate  212 , transistors  108 , word lines  110 , first contacts  206 , second contacts  208 , ground lines  114 , STI  214 , ILD  215 , and dielectric material  210 . 
         [0105]    Transistors  108  are formed in substrate  212  in rows and columns. The gates of transistors  108  are electrically coupled to word lines  110 . Dielectric material  210  is deposited over transistors  108  and word lines  110 . First contacts  206  electrically couple one side of the source-drain path of each transistor  108  to a ground line  114 . Second contacts  208  are electrically coupled to the other side of the source-drain path of each transistor  108 . STI  214  insulates transistors  108  from adjacent transistors  108 , and ILD  215  insulates second contacts  208  from adjacent second contacts  208 . 
         [0106]    First contacts  206  and second contacts  208  are contact plugs, such as W plugs, Cu plugs, or other suitable conducting material plugs. Word lines  110  comprise doped poly-Si, W, TiN, NiSi, CoSi, TiSi, WSiW, or another suitable material. Ground lines  114  comprise W, Al, Cu, or other suitable material. Dielectric material  210  comprises SiN or other suitable material that enables a borderless contact formation process for first contacts  206  and second contacts  208 . STI  214  and ILD  215  comprise SiO 2 , fluorinated silica glass (FSG), boro-phosphorous silicate glass (BPSG), boro-silicate glass (BSG), or other suitable dielectric material. Word lines  110  are parallel to ground lines  114 . Word lines  110  and ground lines  114  are perpendicular to STI  214  and ILD  215 . 
         [0107]      FIG. 10  illustrates a cross-sectional view of one embodiment of preprocessed wafer  218 , a first electrode material layer  240   a , and a hardmask material layer  242   a . Electrode material, such as TiN, TaN, W, Al, Cu, TiSiN, TaSiN, or other suitable electrode material, is deposited over preprocessed wafer  218  to provide first electrode material layer  240   a . First electrode material layer  240   a  is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique. 
         [0108]    Hardmask material, such as SiO 2 , SiN, SiON, C, or other suitable hardmask material is deposited over first electrode material layer  240   a  to provide hardmask material layer  242   a . Hardmask material layer  242   a  is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique 
         [0109]      FIG. 11  illustrates a cross-sectional view of one embodiment of preprocessed wafer  218 , first electrode material layer  240   b , and hardmask material layer  242   b  after etching hardmask material layer  242   a  and first electrode material layer  240   a . Hardmask material layer  242   a  and first electrode material layer  240   a  are etched to provide hardmask material layer  242   b  and first electrode material layer  240   b , which is self-aligned to hardmask material layer  242   b . Line lithography is used to pattern lines of hardmask material  242   b  and first electrode material  240   b  contacting second contacts  208 . The line lithography does not need to be precisely centered over second contacts  208  as long as a portion of first electrode material  240   b  contacts second contacts  208 . In this way, the line lithography is less critical yet the desired memory cell size is obtained. 
         [0110]      FIG. 12  illustrates a cross-sectional view of one embodiment of preprocessed wafer  218 , first electrode material layer  240   b , hardmask material layer  242   b , and a dielectric material layer  204   a . Dielectric material, such as SiO 2 , FSG, BPSG, BSG, or other suitable dielectric material, is deposited over exposed portions of hardmask material layer  242   b , first electrode material layer  240   b , and preprocessed wafer  218 . The dielectric material layer is deposited using CVD, ALD, MOCVD, PVD, JVP, HDP, or other suitable deposition technique. The dielectric material layer is planarized to expose hardmask material layer  242   b  and provide dielectric material layer  204   a . The dielectric material layer is planarized using CMP or another suitable planarization technique. 
         [0111]      FIG. 13A  illustrates a cross-sectional view of one embodiment of preprocessed wafer  218 , first electrode material layer  240   b , and dielectric material layer  204   a  after removing hardmask material layer  242   b .  FIG. 13B  illustrates a perpendicular cross-sectional view of the wafer illustrated in  FIG. 13A , and  FIG. 13C  illustrates a top view of the wafer illustrated in  FIG. 13A . Hardmask material layer  242   b  is removed using a wet etch or other suitable technique to expose first electrode material layer  240   b.    
         [0112]      FIG. 14A  illustrates a cross-sectional view of one embodiment of preprocessed wafer  218 , first electrode material layer  240   b , dielectric material layer  204   a , a phase change material layer  107   a , and a second electrode material layer  113   a .  FIG. 14B  illustrates a perpendicular cross-sectional view of the wafer illustrated in  FIG. 14A . Phase change material, such as a chalcogenide compound material or other suitable phase change material, is deposited over first electrode material layer  240   b  and dielectric material layer  204   a  to provide phase change material layer  107   a . Phase change material layer  107   a  is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique. 
         [0113]    Electrode material, such as TiN, TaN, W, Al, Cu, TiSiN, TaSiN, or other suitable electrode material, is deposited over phase change material layer  107   a  to provide second electrode material layer  113   a . Second electrode material layer  113   a  is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique. 
         [0114]      FIG. 15A  illustrates a cross-sectional view of one embodiment of preprocessed wafer  218 , bottom electrodes  240 , dielectric material layer  204 , phase change material layer  107 , and bit lines  112  after etching second electrode material layer  113   a , phase change material layer  107   a , dielectric material layer  204   a , and first electrode material layer  240   b .  FIG. 15B  illustrates a perpendicular cross-sectional view of the wafer illustrated in  FIG. 15A , and  FIG. 15C  illustrates a top view of the wafer illustrated in  FIG. 15A . Second electrode material layer  113   a , phase change material layer  107   a , dielectric material layer  204   a , and first electrode material layer  240   b  are etched to provide bit lines  112 , phase change material layer  107 , which is self-aligned to bit lines  112 , bottom electrodes  240 , which are self-aligned to bit lines  112 , and dielectric material layer  204 . Line lithography is used to pattern bit lines  112  and lines of phase change material  107  perpendicular to lines of first electrode material  240   b  such that each bottom electrode  240  contacts a second contact  208 . The line lithography does not need to be precisely centered over second contacts  208  as long as a portion of each bottom electrode  240  contacts a second contact  208 . In this way, the line lithography is less critical yet the desired memory cell size is obtained. 
         [0115]    Dielectric material, such as SiO 2 , FSG, BPSG, BSG, or other suitable dielectric material, is deposited over exposed portions of bit lines  112 , phase change material layer  107 , dielectric material layer  204 , bottom electrodes  240 , and preprocessed wafer  218 . The dielectric material layer is deposited using CVD, ALD, MOCVD, PVD, JVP, HDP, or other suitable deposition technique. The dielectric material layer is planarized to expose bit lines  112  and provide dielectric material layer  216 . The dielectric material layer is planarized using CMP or another suitable planarization technique to provide array of phase change memory cells  200   a  illustrated in  FIGS. 2A-2C . 
         [0116]      FIG. 16A  illustrates a cross-sectional view of another embodiment of an array of phase change memory cells  200   b .  FIG. 16B  illustrates a perpendicular cross-sectional view of array of phase change memory cells  200   b  illustrated in  FIG. 16A .  FIG. 16C  illustrates a top view of array of phase change memory cells  200   b  illustrated in  FIG. 16A . In one embodiment, array of phase change memory cells  100  is similar to array of phase change memory cells  200   b . Array of phase change memory cells  200   b  includes substrate  212 , transistors  108 , word lines  110 , first contacts  206 , second contacts  208 , ground lines  114 , bottom electrodes  240 , dielectric material  204 ,  210 , and  216 , STI  214 , ILD  215 , phase change elements  106 , and bits lines  112 . Metal wiring (not shown) follows after the bit line level. 
         [0117]    Transistors  108  for selecting phase change elements  106  are formed in substrate  212  in rows and columns. The gates of transistors  108  are electrically coupled to word lines  110 . Dielectric material  210  is deposited over transistors  108  and word lines  110 . First contacts  206  electrically couple one side of the source-drain path of each transistor  108  to a ground line  114 . Second contacts  208  electrically couple the other side of the source-drain path of each transistor  108  to a bottom electrode  240 . Each bottom electrode  240  is electrically coupled to a phase change element  106 . Each phase change element  106  is electrically coupled to a bit line  112 . Bit lines  112  are perpendicular to word lines  110  and ground lines  114 . Dielectric material  204  insulates ground lines  114  above first contacts  206 . Dielectric material  216  insulates bits lines  112 , phase change elements  106 , and bottom electrodes  240  from adjacent bit lines  112 , phase change elements  106 , and bottom electrodes  240 . STI  214  insulates transistors  108  from adjacent transistors  108 , and ILD  215  insulates second contacts  208  from adjacent second contacts  208 . 
         [0118]    Phase change elements  106  and bottom electrodes  240  are self-aligned to bit lines  112 . The self-alignment minimizes critical lithography steps in the fabrication of array of phase change memory cells  200   b . In addition, with self-alignment the interface resistances between bottom electrodes  240  and phase change elements  106  and between phase change elements  106  and bit lines  112  is overlay insensitive and parasitic resistances are minimized. 
         [0119]    In one embodiment, array of phase change memory cells  200   b  is scalable to 8F 2  for dual gate memory cells, where “F” is the minimum feature size, or to 6F 2  for single gate memory cells. In the embodiment for single gate memory cells, an active gate of a transistor  108  between every two adjacent memory cells is replaced with an isolation gate. One embodiment of a method for fabricating array of phase change memory cells  200   b  is described and illustrated with reference to the following  FIGS. 17A-22C . 
         [0120]      FIG. 17A  illustrates a cross-sectional view of one embodiment of a preprocessed wafer  218 .  FIG. 17B  illustrates a perpendicular cross-sectional view of preprocessed wafer  218  illustrated in  FIG. 17A .  FIG. 17C  illustrates a top cross-sectional view of preprocessed wafer  218  illustrated in  FIG. 17A . 
         [0121]      FIG. 17D  illustrates a top view of preprocessed wafer  218  illustrated in  FIG. 17A . Preprocessed wafer  218  includes substrate  212 , transistors  108 , word lines  110 , first contacts  206 , second contacts  208 , ground lines  114 , STI  214 , ILD  215 , and dielectric material  210 . 
         [0122]    Transistors  108  are formed in substrate  212  in rows and columns. The gates of transistors  108  are electrically coupled to word lines  110 . Dielectric material  210  is deposited over transistors  108  and word lines  110 . First contacts  206  electrically couple one side of the source-drain path of each transistor  108  to a ground line  114 . Second contacts  208  are electrically coupled to the other side of the source-drain path of each transistor  108 . STI  214  insulates transistors  108  from adjacent transistors  108 , and ILD  215  insulates second contacts  208  from adjacent second contacts  208 . 
         [0123]    First contacts  206  and second contacts  208  are contact plugs, such as W plugs, Cu plugs, or other suitable conducting material plugs. Word lines  110  comprise doped poly-Si, W, TiN, NiSi, CoSi, TiSi, WSi x , or another suitable material. Ground lines  114  comprise W, Al, Cu, or other suitable material. Dielectric material  210  comprises SiN or other suitable material that enables a borderless contact formation process for first contacts  206  and second contacts  208 . STI  214  and ILD  215  comprise SiO 2 , FSG, BPSG, BSG, or other suitable dielectric material. Word lines  110  are parallel to ground lines  114 . Word lines  110  and ground lines  114  are perpendicular to STI  214  and ILD  215 . 
         [0124]      FIG. 18  illustrates a cross-sectional view of one embodiment of preprocessed wafer  218 , a first electrode material layer  240   a , and a phase change material layer  107   a . Electrode material, such as TiN, TaN, W, Al, Cu, TiSiN, TaSiN, or other suitable electrode material, is deposited over preprocessed wafer  218  to provide first electrode material layer  240   a . First electrode material layer  240   a  is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique. 
         [0125]    Phase change material, such as a chalcogenide compound material or other suitable phase change material, is deposited over first electrode material layer  240   a  to provide phase change material layer  107   a . Phase change material layer  107   a  is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique. In one embodiment, an optional hardmask material layer is deposited over phase change material layer  107   a.    
         [0126]      FIG. 19  illustrates a cross-sectional view of one embodiment of preprocessed wafer  218 , first electrode material layer  240   b , and phase change material layer  107   b  after etching phase change material layer  107   a  and first electrode material layer  240   a . Phase change material layer  107   a  and first electrode material layer  240   a  are etched to provide phase change material layer  107   b  and first electrode material layer  240   b , which is self-aligned to phase change material layer  107   b . Line lithography is used to pattern lines of phase change material  107   b  and first electrode material  240   b  contacting second contacts  208 . The line lithography does not need to be precisely centered over second contacts  208  as long as a portion of first electrode material  240   b  contacts second contacts  208 . In this way, the line lithography is less critical yet the desired memory cell size is obtained. 
         [0127]    In the embodiment where a hardmask material layer is deposited over phase change material layer  107   a , the hardmask material layer, phase change material layer  107   a , and first electrode material layer  240   a  are etched to provide an etched hardmask material layer, first phase change material layer  107   b , which is self-aligned to the etched hardmask material layer, and first electrode material layer  240   b , which is self-aligned to first phase change material layer  107   b.    
         [0128]      FIG. 20A  illustrates a cross-sectional view of one embodiment of preprocessed wafer  218 , first electrode material layer  240   b , phase change material layer  107   b , and a dielectric material layer  204   a .  FIG. 20B  illustrates a perpendicular cross-sectional view of the wafer illustrated in  FIG. 20A , and  FIG. 20C  illustrates a top view of the wafer illustrated in  FIG. 20A . Dielectric material, such as SiO 2 , FSG, BPSG, BSG, or other suitable dielectric material, is deposited over exposed portions of phase change material layer  107   b , first electrode material layer  240   b , and preprocessed wafer  218 . The dielectric material layer is deposited using CVD, ALD, MOCVD, PVD, JVP, HDP, or other suitable deposition technique. The dielectric material layer is planarized to expose phase change material layer  107   b  and provide dielectric material layer  204   a . The dielectric material layer is planarized using CMP or another suitable planarization technique. In the embodiment where an etched hardmask material layer is over phase change material layer  107   b , the dielectric material layer is planarized to expose the hardmask material. The planarized dielectric material layer is optionally recess etched such that the top of the dielectric material layer is aligned with the top of phase change material layer  107   b . The hardmask material is then removed using a wet etch or other suitable technique. 
         [0129]      FIG. 21A  illustrates a cross-sectional view of one embodiment of preprocessed wafer  218 , first electrode material layer  240   b , phase change material layer  107   b , dielectric material layer  204   a , and a second electrode material layer  113   a .  FIG. 21B  illustrates a perpendicular cross-sectional view of the wafer illustrated in  FIG. 21A . Electrode material, such as TiN, TaN, W, Al, Cu, TiSiN, TaSiN, or other suitable electrode material, is deposited over phase change material layer  107   b  and dielectric material layer  204   a  to provide second electrode material layer  113   a . Second electrode material layer  113   a  is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique. 
         [0130]      FIG. 22A  illustrates a cross-sectional view of one embodiment of preprocessed wafer  218 , bottom electrodes  240 , phase change elements  106 , dielectric material layer  204 , and bit lines  112  after etching second electrode material layer  113   a , phase change material layer  107   b , dielectric material layer  204   a , and first electrode material layer  240   b .  FIG. 22B  illustrates a perpendicular cross-sectional view of the wafer illustrated in  FIG. 22A , and  FIG. 22C  illustrates a top view of the wafer illustrated in  FIG. 22A . Second electrode material layer  113   a , phase change material layer  107   b , dielectric material layer  204   a , and first electrode material layer  240   b  are etched to provide bit lines  112 , phase change elements  106 , which are self-aligned to bit lines  112 , bottom electrodes  240 , which are self-aligned to bit lines  112 , and dielectric material layer  204 . Line lithography is used to pattern bit lines  112  perpendicular to lines of first electrode material  240   b  such that each bottom electrode  240  contacts a second contact  208 . The line lithography does not need to be precisely centered over second contacts  208  as long as a portion of each bottom electrode  240  contacts a second contact  208 . In this way, the line lithography is less critical yet the desired memory cell size is obtained. 
         [0131]    Dielectric material, such as SiO 2 , FSG, BPSG, BSG, or other suitable dielectric material, is deposited over exposed portions of bit lines  112 , phase change elements  106 , dielectric material layer  204 , bottom electrodes  240 , and preprocessed wafer  218 . The dielectric material layer is deposited using CVD, ALD, MOCVD, PVD, JVP, HDP, or other suitable deposition technique. The dielectric material layer is planarized to expose bit lines  112  and provide dielectric material layer  216 . The dielectric material layer is planarized using CMP or another suitable planarization technique to provide array of phase change memory cells  200   b  illustrated in  FIGS. 16A-16C . 
         [0132]      FIG. 23A  illustrates a cross-sectional view of another embodiment of an array of phase change memory cells  200   c .  FIG. 23B  illustrates a perpendicular cross-sectional view of array of phase change memory cells  200   c  illustrated in  FIG. 23A .  FIG. 23C  illustrates a top view of array of phase change memory cells  200   c  illustrated in  FIG. 23A . In one embodiment, array of phase change memory cells  100  is similar to array of phase change memory cells  200   c . Array of phase change memory cells  200   c  includes substrate  212 , transistors  108 , word lines  110 , first contacts  206 , second contacts  208 , ground lines  114 , bottom electrodes  240 , dielectric material  204 ,  210 , and  216 , STI  214 , ILD  215 , phase change elements  106 , top electrodes  250 , and bits lines  112 . Metal wiring (not shown) follows after the bit line level. 
         [0133]    Transistors  108  for selecting phase change elements  106  are formed in substrate  212  in row and columns. The gates of transistors  108  are electrically coupled to word lines  110 . Dielectric material  210  is deposited over transistors  108  and word lines  110 . First contacts  206  electrically couple one side of the source-drain path of each transistor  108  to a ground line  114 . Second contacts  208  electrically couple the other side of the source-drain path of each transistor  108  to a bottom electrode  240 . Each bottom electrode  240  is electrically coupled to a phase change element  106 . Each phase change element  106  is electrically coupled to a top electrode  250 . Each top electrode  250  is electrically coupled to a bit line  112 . Bit lines  112  are perpendicular to word lines  110  and ground lines  114 . Dielectric material  204  insulates ground lines  114  above first contacts  206 . Dielectric material  216  insulates bits lines  112 , top electrodes  250 , phase change elements  106 , and bottom electrodes  240  from adjacent bit lines  112 , top electrodes  250 , phase change elements  106 , and bottom electrodes  240 . STI  214  insulates transistors  108  from adjacent transistors  108 , and ILD  215  insulates second contacts  208  from adjacent second contacts  208 . 
         [0134]    Top electrodes  250 , phase change elements  106 , and bottom electrodes  240  are self-aligned to bit lines  112 . The self-alignment minimizes critical lithography steps in the fabrication of array of phase change memory cells  200   c . In addition, with self-alignment the interface resistances between bottom electrodes  240  and phase change elements  106  and between phase change elements  106  and top electrodes  250  is overlay insensitive and parasitic resistances are minimized. 
         [0135]    In one embodiment, array of phase change memory cells  200   c  is scalable to 8F 2  for dual gate memory cells, where “F” is the minimum feature size, or to 6F 2  for single gate memory cells. In the embodiment for single gate memory cells, an active gate of a transistor  108  between every two adjacent memory cells is replaced with an isolation gate. One embodiment of a method for fabricating array of phase change memory cells  200   c  is described and illustrated with reference to the following  FIGS. 24A-29C . 
         [0136]      FIG. 24A  illustrates a cross-sectional view of one embodiment of a preprocessed wafer  218 .  FIG. 24B  illustrates a perpendicular cross-sectional view of preprocessed wafer  218  illustrated in  FIG. 24A .  FIG. 24C  illustrates a top cross-sectional view of preprocessed wafer  218  illustrated in  FIG. 24A .  FIG. 24D  illustrates a top view of preprocessed wafer  218  illustrated in  FIG. 24A . Preprocessed wafer  218  includes substrate  212 , transistors  108 , word lines  110 , first contacts  206 , second contacts  208 , ground lines  114 , STI  214 , ILD  215 , and dielectric material  210 . 
         [0137]    Transistors  108  are formed in substrate  212  in rows and columns. The gates of transistors  108  are electrically coupled to word lines  110 . Dielectric material  210  is deposited over transistors  108  and word lines  110 . First contacts  206  electrically couple one side of the source-drain path of each transistor  108  to a ground line  114 . Second contacts  208  are electrically coupled to the other side of the source-drain path of each transistor  108 . STI  214  insulates transistors  108  from adjacent transistors  108 , and ILD  215  insulates second contacts  208  from adjacent second contacts  208 . 
         [0138]    First contacts  206  and second contacts  208  are contact plugs, such as W plugs, Cu plugs, or other suitable conducting material plugs. Word lines  110  comprise doped poly-Si, W, TiN, NiSi, CoSi, TiSi, WSi x , or another suitable material. Ground lines  114  comprise W, Al, Cu, or other suitable material. Dielectric material  210  comprises SiN or other suitable material that enables a borderless contact formation process for first contacts  206  and second contacts  208 . STI  214  and ILD  215  comprise SiO 2 , FSG, BPSG, BSG, or other suitable dielectric material. Word lines  110  are parallel to ground lines  114 . Word lines  110  and ground lines  114  are perpendicular to STI  214  and ILD  215 . 
         [0139]      FIG. 25  illustrates a cross-sectional view of one embodiment of preprocessed wafer  218 , a first electrode material layer  240   a , a phase change material layer  107   a , and a second electrode material layer  250   a . Electrode material, such as TiN, TaN, W, Al, Cu, TiSiN, TaSiN, or other suitable electrode material, is deposited over preprocessed wafer  218  to provide first electrode material layer  240   a . First electrode material layer  240   a  is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique. 
         [0140]    Phase change material, such as a chalcogenide compound material or other suitable phase change material, is deposited over first electrode material layer  240   a  to provide phase change material layer  107   a . Phase change material layer  107   a  is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique. 
         [0141]    Electrode material, such as TiN, TaN, W, Al, Cu, TiSiN, TaSiN, or other suitable electrode material, is deposited over phase change material  107   a  to provide second electrode material layer  250   a . Second electrode material layer  250   a  is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique. In one embodiment, an optional hardmask material layer is deposited over second electrode material layer  250   a.    
         [0142]      FIG. 26  illustrates a cross-sectional view of one embodiment of preprocessed wafer  218 , first electrode material layer  240   b , phase change material layer  107   b , and second electrode material layer  250   b  after etching second electrode material layer  250   a , phase change material layer  107   a , and first electrode material layer  240   a . Second electrode material layer  250   a , phase change material layer  107   a , and first electrode material layer  240   a  are etched to provide second electrode material layer  250   b , phase change material layer  107   b , which is self-aligned to second electrode material layer  250   b , and first electrode material layer  240   b , which is self-aligned to phase change material layer  107   b . Line lithography is used to pattern lines of second electrode material  250   b , phase change material  107   b , and first electrode material  240   b  contacting second contacts  208 . The line lithography does not need to be precisely centered over second contacts  208  as long as a portion of first electrode material  240   b  contacts second contacts  208 . In this way, the line lithography is less critical yet the desired memory cell size is obtained. 
         [0143]    In the embodiment where a hardmask material layer is deposited over second electrode material layer  250   a , the hardmask material layer, second electrode material layer  250   a , phase change material layer  107   a , and first electrode material layer  240   a  are etched to provide an etched hardmask material layer, second electrode material layer  250   b , which is self-aligned to the etched hardmask material layer, first phase change material layer  107   b , which is self-aligned to second electrode material layer  250   b , and first electrode material layer  240   b , which is self-aligned to first phase change material layer  107   b.    
         [0144]      FIG. 27A  illustrates a cross-sectional view of one embodiment of preprocessed wafer  218 , first electrode material layer  240   b , phase change material layer  107   b , second electrode material layer  250   b , and a dielectric material layer  204   a .  FIG. 27B  illustrates a perpendicular cross-sectional view of the wafer illustrated in  FIG. 27A , and  FIG. 27C  illustrates a top view of the wafer illustrated in  FIG. 27A . Dielectric material, such as SiO 2 , FSG, BPSG, BSG, or other suitable dielectric material, is deposited over exposed portions of second electrode material layer  250   b , phase change material layer  107   b , first electrode material layer  240   b , and preprocessed wafer  218 . The dielectric material layer is deposited using CVD, ALD, MOCVD, PVD, JVP, HDP, or other suitable deposition technique. The dielectric material layer is planarized to expose second electrode material layer  250   b  and provide dielectric material layer  204   a . The dielectric material layer is planarized using CMP or another suitable planarization technique. In the embodiment where an etched hardmask material layer is over second electrode material layer  250   b , the dielectric material layer is planarized to expose the hardmask material. The hardmask material is then removed using a wet etch or other suitable technique. 
         [0145]      FIG. 28A  illustrates a cross-sectional view of one embodiment of preprocessed wafer  218 , first electrode material layer  240   b , phase change material layer  107   b , second electrode material layer  250   b , dielectric material layer  204   a , and a third electrode material layer  113   a .  FIG. 28B  illustrates a perpendicular cross-sectional view of the wafer illustrated in  FIG. 28A . Electrode material, such as TiN, TaN, W, Al, Cu, TiSiN, TaSiN, or other suitable electrode material, is deposited over second electrode material layer  250   b  and dielectric material layer  204   a  to provide third electrode material layer  113   a . Third electrode material layer  113   a  is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique. 
         [0146]      FIG. 29A  illustrates a cross-sectional view of one embodiment of preprocessed wafer  218 , bottom electrodes  240 , phase change elements  106 , top electrodes  250 , dielectric material layer  204 , and bit lines  112  after etching third electrode material layer  113   a , second electrode material layer  250   a , phase change material layer  107   b , dielectric material layer  204   a , and first electrode material layer  240   b .  FIG. 29B  illustrates a perpendicular cross-sectional view of the wafer illustrated in  FIG. 29A , and  FIG. 29C  illustrates a top view of the wafer illustrated in  FIG. 29A . Third electrode material layer  113   a , second electrode material layer  250   b , phase change material layer  107   b , dielectric material layer  204   a , and first electrode material layer  240   b  are etched to provide bit lines  112 , top electrodes  250 , which are self-aligned to bit lines  112 , phase change elements  106 , which are self-aligned to bit lines  112 , bottom electrodes  240 , which are self-aligned to bit lines  112 , and dielectric material layer  204 . Line lithography is used to pattern bit lines  112  perpendicular to lines of first electrode material  240   b  such that each bottom electrode  240  contacts a second contact  208 . The line lithography does not need to be precisely centered over second contacts  208  as long as a portion of each bottom electrode  240  contacts a second contact  208 . In this way, the line lithography is less critical yet the desired memory cell size is obtained. 
         [0147]    Dielectric material, such as SiO 2 , FSG, BPSG, BSG, or other suitable dielectric material, is deposited over exposed portions of bit lines  112 , top electrodes  250 , phase change elements  106 , dielectric material layer  204 , bottom electrodes  240 , and preprocessed wafer  218 . The dielectric material layer is deposited using CVD, ALD, MOCVD, PVD, JVP, HDP, or other suitable deposition technique. The dielectric material layer is planarized to expose bit lines  112  and provide dielectric material layer  216 . The dielectric material layer is planarized using CMP or another suitable planarization technique to provide array of phase change memory cells  200   c  illustrated in  FIGS. 23A-23C . 
         [0148]    Embodiments of the present invention provide an array of phase change memory cells fabricated using line lithography and self-aligned processing to minimize critical lithography steps. In addition, interface resistances between metal and active material in the array is overlay-insensitive and by maximizing the interface areas, parasitic resistances are minimized. The array of phase change memory cells has an improved chemical mechanical planarization (CMP) process window and improved mechanical stability during fabrication. 
         [0149]    Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.