Abstract:
A sidelobe canceller for a transducer arrangement such as an antenna or sonar transducer uses a main transducer and one or more auxiliary transducers. The auxiliary received signals are weighted by FIR filters or by multipliers, and the weighted auxiliary signals are summed, and the summed, weighted auxiliary signals are subtracted from the main signal to produce the desired low-sidelobe main signal. The weighting signals are generated in conventional manner from intermediate weighted signals. The intermediate weighting signals are produced by a reduced-hardware arrangement. When FIR filters are used, the signals being multiplied by weights include mutually delayed samples.

Description:
BACKGROUND OF THE INVENTION 
   This invention relates to sidelobe cancellers for sensing systems such as radar and sonar, and more particularly to improved weight determination arrangements which reduce redundant processes and thereby allow higher operating speed, reduced or simplified weight determination hardware, or both. 
     FIG. 1  is a simplified block diagram of a radar system in accordance with the invention. In  FIG. 1 , a first or main antenna  10  is coupled by a diplexer  12  to a transmitter (TX)  14  and to a receiver  16 . Main antenna  10  produces a receive “beam” designated as  18 , which includes a main lobe  20 , and also includes a plurality of sidelobes  22  by which energy may be received from directions other than the main lobe. Representative first and second ancillary or auxiliary antennas  24   a  . . .  24   n  are located near main antenna  10 , and respond generally to signal from the direction of the main lobe and from other directions. Each auxiliary antenna  24   a  . . .  24   n  is coupled to an individual receiver, illustrated as receivers  28   a  . . . .  28   m . The receivers amplify, frequency convert, and perform analog-to-digital conversion, and other known functions as may be required to produce signals representative of amplitude and phase. The received signals from main receiver  16  are coupled to a delay (D)  30 , and to the noninverting (+) input port of a summing circuit  32 . The received signals from receivers  28   a  . . .  28   m  are applied to input ports of finite impulse response (FIR) filters  34   a  . . . .  34   p  associated with the receivers. 
   The received signals from auxiliary receivers  28   a  . . .  28   m  of  FIG. 1   a  are also applied over buses  29   a  . . .  29   s  to a plurality of delay lines illustrated as blocks  38   a  . . .  38   r . Representative delay line  38   a  is illustrated in  FIG. 1   c , and uses a cascade of delay elements represented as shift registers (S)  138   a ,  138   b , and  138   c  to produce four time-sequential samples of the received signals on output data paths a 1 , a 2 , a 3 , a 4  of a of bus  39   a  for application to weighting signal generator  40  of  FIG. 1   a . Weighting signal generator  40  processes the a 1  . . . a 4  sequential signal samples from delay  38   a , the u 1  . . . u 4  sequential signal samples from delay  38   r , other sets of sequential signal samples from other ones of the delays  38  (not illustrated), and the single delayed main signal sample from delay  30 , to produce intermediate weighting signals on data paths  36   a  . . . .  36   g . The intermediate weighting signals on paths  36   a  . . .  36   p  are processed in processor  50  to form weighting coefficients. The weighting coefficients are applied over buses  35   a  . . .  35   q  to FIR filters  34   a  . . .  34   p . FIR filters  34   a  . . .  34   p  filter the complex received signals received over paths  29   a  . . .  29   s  from receivers  28   a  . . .  28   m  under the control of weighting signals, received over buses  35   a  . . . .  35   q  from weighting signal processor  50 . The FIR filters filter the auxiliary signals originating from auxiliary antennas  24   a  . . .  24   n . The filtered auxiliary signals are applied from FIR filters  34   a  . . .  34   p  to a summing (Σ) circuit illustrated as a block  42 . The summed, filtered auxiliary signals are applied from summing circuit  42  to the inverting (−) input of summing circuit  32 , where they are subtracted from the main signal to produce on data path  52  the desired signal, which represents the main lobe signals in which the unwanted signals arriving from directions other than that of main lobe  20  as suppressed. 
     FIG. 1   b  illustrates details of representative FIR filter  34   a  of  FIG. 1   a . In  FIG. 1   b , each FIR filter includes a tapped delay line, multipliers and a summer which together provide frequency response shaping to improve cancellation performance. In  FIG. 1   b , a tapped delay  134  includes shift registers  110 ,  112  and  114 , which delay the signal from receiver  28   a  of  FIG. 1   a . A set of four multipliers  120 ,  122 ,  124  and  126  is coupled to receive mutually delayed signal samples from delay line  134 . Each multiplier receives an independent weighting coefficient over bus  36   a  from weighting signal processor  50 . As a result, the same signal sample moves in sequence from multiplier to multiplier within FIR filter  34   a  of  FIG. 1   b . More specifically, each undelayed sample arriving on path  17  is applied to multiplier  120  or multiplication by a first weighting coefficient. At the next clock cycle, shift register  110  stores the sample and makes it available to multiplier  122 , and a new sample arrives at the input of shift register  110  and is applied to multiplier  120 . During succeeding clock cycles, the original sample moves from shift register to shift register within delay line  134 , being applied in succession to input ports of multipliers  120 ,  122 ,  124  and  126 , and being multiplied therein by one of the weighting coefficients. At any moment, the sum signal generated at the output of summing circuit  128  of  FIG. 1   b  is the sum of a plurality of time-sequential samples of the received auxiliary signals, each multiplied by a different one of the weighting coefficients (although one or more of the weighting coefficients may happen to have the same value). 
     FIG. 2   a  is a simplified block diagram of a radar system similar to that of  FIG. 1   a , but in which simple multipliers are used instead of FIR filters. Elements of  FIG. 2   a  corresponding to those of  FIG. 1   a  are designated by the same reference numerals. In  FIG. 2   a , weighting signal generator  240  has fewer input ports than weighting signal generator  40  of  FIG. 1   a , and consequently has fewer levels of calculation, but is otherwise identical. The intermediate weighting signals produced by weighting signal generator  240  of  FIG. 2   c  are applied over data paths  236   a  . . .  236   q  processor  50 , which generates the desired weighting coefficients for application to multipliers  234   a  . . .  234   p  for multiplying the auxiliary received signals. The multiplied auxiliary received signals are applied to summing circuit  42 , and the summed, weighted auxiliary signals are subtracted from the main signal in summing circuit  32 . 
     FIG. 2   b  is a simplified block diagram of intermediate weighting signal generator  240  of  FIG. 2   a . Weight generator  240  of  FIG. 2   b  is illustrated for the case in which a single input signal or vector x 5  originating from main antenna  10  of  FIG. 2   b  is received by way of receiver  16 , together with four auxiliary signals x 1 , x 2 , x 3  and x 4  originating from auxiliary antennas  28   a  . . .  28   m . The arrangement of  FIG. 2   b  is similar to, but not identical with that described at Chapter 4 in the  Doctoral Dissertation in Electrical Engineering  entitled,  “Time and Order Recursive Multichannel Adaptive Filtering Techniques ,” by Stanley Man Fung Yuen, presented to the faculties of the University of Pennsylvania in 1988. 
   It should initially be noted that the structure of weighting signal generator  240  of  FIG. 2   b  can be used to directly generate the desired main signal free of the signals from unwanted directions. This is accomplished by, in the structure of  FIG. 2   b , taking signal x 5  to be the main signal, and x 1 –x 4  to be the auxiliary signals. In the arrangement of  FIG. 2   b , the main signal x 5  is ultimately decorrelated or orthogonalized with the x 1 , x 2 , x 3  and x 4  vectors. The x 1 , x 2  . . . x 5  signals are applied to a first row of processors including processors designated A and B, described further in relation to  FIG. 2   c . The outputs from Row  1  are residues q 2   1  to q 5   1 , which are used as inputs to the next row of decorrelators. Each residue q represents an input vector x decorrelated or orthogonalized from one or more of the other vectors x. For example, q 2   1  produced by B processor  212   1,2  represents vector x 2  decorrelated from vector x 1 . Similarly, residue q 3   2  produced at the output of B processor  212   2,3  represents vector x 3  decorrelated from vectors x 1  and x 2 . This iterative process continues until the last residue is obtained, which in this case is q 5   4 , which is the residue of the main signal vector X 5  which has made orthogonal to the remainder of the input vectors x 1  . . . . x 4 . Residue q 5   4  is made available on a path  208  of  FIG. 2   a  and may be directly applied to further processing and display devices (not illustrated) rather than the difference signal from data path  52 . 
   For the simple, illustrative case of  FIG. 2   b , taking the desired signal from conductor  208  may be appropriate. However, as mentioned below, it may be desirable to use weighting signals generated as intermediate products in the structure of  FIG. 2   b  to produce the weighting signals for multipliers  234   a – 234   p  of  FIG. 2   a . As part of their operation, each B processor produces an intermediate weighting coefficient l xy , where subscript x describes the row, and subscript y describes the column. 
   More particularly, in  FIG. 2   b , the x 1  auxiliary signal is applied as an input to A processor  210   1 , and to an input port of each of B processors  212   1,2 ,  212   1,3 ,  212   1,4  and  212   1,5 . Auxiliary signal x 2  is applied to another input port of B processor  212   1,2 , auxiliary signal x 3  is applied to another input port of B processor  212   1,3 , and auxiliary signal x 4  is applied to another input port of B processor  212   1,4 . Main signal x 5  is applied to another input port of B processor  212   1,5 . A processor  210   1  and B processors  212   1,2  . . .  212   1,5  are included within a first row (Row  1 ) of generator  240 . In Row  1 , the processed output of A processor  210   1 , which is designated L 1,1 , is applied to further input ports of each of B processors  212   1,2 ,  212   1,3 ,  212   1,4  and  212   1,5  of Row  1 . The B processors of Row  1  of  FIG. 2   a  produce intermediate weighting coefficients l and residues q. The residue produced by main B processor  212   1,5  is designated q 5   1 , which is applied to an input of a B processor  212   2,5  of Row  2 . Processor  212   1,2  of Row  1  produces a residue designated q 2   1  which is applied to the input of an A processor  210   2  of Row  2 , and to inputs of B processors  212   2,3 ,  212   2,4 ,  212   2,5  of Row  2 . The residue produced by Row  1  B processor  212   1,3  is designated q 3   1 , which is applied to an input port of Row  2  B processor  212   2,3 . The output signal produced by Row  1  B processor  212   1,4  is designated q 4   1 , and is applied to an input port of Row  2  B processor  212   2,4 . 
   In Row  2  of  FIG. 2   b , the output signal of A processor  210   2 , which is designated L 2,2 , is applied to input ports of B processors  212   2,3 ,  212   2,4 ,  212   2,5 . The Row  2  B processors  212   2,3 ,  212   2,4 , and  212   2,5  each produce a residue. These residues are designated q 3   2 , q 4   2 , and q 5   2 , respectively. In  FIG. 2   b , residue q 3   2  produced by B processor  212   2,3  of Row  2  is applied to the input port of A processor  210   3  of Row  3 , and to input ports of B processors  212   3,4  and  212   3,5  of Row  3 . Residue q 4   2  produced by B processor  212   2,4  of Row  2  is applied to an input port of B processor  212   3,4  of Row  3 . Residue q 5   2  produced by B processor  212   2,5  of Row  2  is applied to an input port of B processor  212   3,5  of Row  3 . Also within Row  3 , the output, designated L 3,3  produced by A processor  210   3  is applied to further input ports of B processors  212   3,4  and  212   3,5 . B processors  212   3,4  and  212   3,5  of Row  3  produce residues q 4   3  and q 5   3 , respectively. 
   The q 4   3  residue produced by B processor  212   3,4  of Row  3  of  FIG. 2   b  is applied to the input port of A processor  210   4  of Row  4 , and to B processor  212   4,5 . The q 5   3  residue produced by B processor  212   3,5  of Row  3  is applied to another input of B processor  212   4,5  of Row  4 . Also in Row  4 , the output signal, designated L 4,4 , of A processor  210   4  is applied to an input port of B processor  212   4,5 . B processor  212   4,5  produces the final desired residue q 5   4 , which is the residue of the main signal vector x 5  which has been made orthogonal to the rest of the input vectors. 
   As so far described, the arrangement of  FIG. 2   b  generates the desired orthogonalized main signal. When the process of cancellation must be applied to large numbers of range cells, the above-described method may not be efficient, and may introduce speed limitations. 
   An alternative method for using the structure of  FIG. 2   b  in the radar system of  FIG. 2   a  is to ignore the signal on data path  208 , and use only a subset of the range cells to generate weighting signals in the arrangement of  FIG. 2   a , which are then applied to the multipliers of  FIG. 2   a  for all range cells. To generate the weights in this manner, sets of intermediate weighting coefficients designated generally as  1  are derived from weighting signal generator  240  of  FIG. 2   b . An intermediate weighting coefficient designated  1   xy  is generated in each B processor during generation of the residues, where subscript x represents the row in which the B processor is located, and subscript y represents the column. These intermediate weighting coefficients are extracted in sets at each row of the structure of  FIG. 2   b , and are further processed in processor  50  to produce the weights which are applied to multipliers  234   a  . . .  234   p  of  FIG. 2   a . The processing required in processing block  50  of  FIG. 2   b  to form the weighting coefficients from the intermediate weight coefficients for application to multipliers  234   a  . . .  234   p  is well known in the art and is described in, for example, the aforementioned Yuen dissertation. This technique uses some of the range cells to produce weighting coefficients which are applied to the signals of all the range cells, thereby reducing the amount of processing. 
     FIG. 2   c  illustrates details of the A and B processors of  FIG. 2   b . More particularly, for definiteness,  FIG. 2   c  illustrates representative A processor  210   1  of  FIG. 2   b , and B processor  212   1,2 . 
   In  FIG. 2   c , the x 1  auxiliary signal is applied in batches to a first input port of a summing multiplier (XΣ)  222  of a processor  210   1,1  and to a processing block  220  designated by an asterisk (*) for taking the complex conjugate of input signal x 1 . The complex conjugate is applied to a second input port of summing multiplier  222 . Such processing circuits are well known in the art, and are described, for example, in U.S. Pat. No. 4,941,117 issued Jul. 10, 1990 in the name of Yuen. The output signal L 1,1 , produced by A processor  210   1  of  FIG. 2   c  is applied to an input port  233  of B processor  212   1,2 , together with the x 1  auxiliary signal applied to input port  232  and the x 2  auxiliary signal applied to input port  231 . 
   In B processor  212   1,2  of  FIG. 2   c , the x 1  signal applied to input port  232  is applied to a delay circuit or buffer  240  and to a complex conjugate processor  238 , which produces the complex conjugate of x 1  and applies it to an input port of summing multiplier  258 . The x 2  auxiliary signal input is applied to an input of a delay or buffer circuit  244 , and to a second input of summing multiplier  258 . Summing multiplier  258  takes the sum of products, and applies the result to the input of a dividing (÷) circuit  246 , where the signal from summing multiplier  258  is divided by the L 1,1  signal applied to input port  233  of B processor  212   1,2 . The divided signal, designated l 1,2  is applied to a multiplier  242 , where it is multiplied by the delayed x 1  signal from buffer  240 , to produce a signal which is applied to the inverting (−n) input port of a summing circuit  248 . The non-inverting input port of summing circuit  248  receives delayed x 2  signal from buffer  244 , and combines it with the output of multiplier  242  to produce at an output port  254  of B processor  212   1,2  a residue signal q 2   1  for application to other processors as described in conjunction with  FIG. 2   b . The divided signal l 1,2  produced at the output of dividing circuit  246  is the desired intermediate weighting signal produced by B processor  212   1,2 . Each of the other B processors of Row  1  of weighting signal generator  240  of  FIG. 2   b  produces its own intermediate weighting coefficient, and taken together, the four weighting coefficients l 1,2 , l 1,3 , l 1,4  and l 1,5  produced by the B processors of Row  1  constitute one set of intermediate weighting coefficients. 
   Similarly, the three intermediate weighting coefficients l 2,y  of Row  2  of  FIG. 2   b  are extracted as one set, the two l 3,y  of Row  3  constitute one set, and the set of Row  4  includes the single intermediate weighting coefficient l 4,5 . 
   The system of  FIGS. 2   a ,  2   b  and  2   c  produces both the desired orthogonalized residue signals q, and the intermediate weighting coefficients l x,y , which can also be used to produce weighting signals for generating orthogonalized signals. Thus, the arrangement produces more information than the minimum required to produce the desired result. It would be desirable to reduce the amount of processing to produce the desired weight signals. 
   A further inefficiency exists when the scheme of  FIGS. 2   b  and  2   c  is used in an arrangement such as that of  FIG. 1   a . When used to process sets of auxiliary signals such as a 1  . . . a 4 ; . . . ;u 1  . . . u 4 ; of  FIG. 1   a , the processing arrangement of  FIG. 2   b  treats all its inputs as independent, even though the signals of any set of inputs (e.g. a 1  . . . a 4 ) are merely mutually delayed from each other, as described below in conjunction with  FIG. 5 . Thus, in the context of  FIG. 1   a , a weighting signal generator  40  operating as described in conjunction with  FIG. 2   b  performs more than the minimum amount of processing. In such a case, the input signals to weighting signal generator  240  of  FIG. 2   b  may be processed to take advantage of the time relationship of the signals in the shift registers of the FIR filters. 
   SUMMARY OF THE INVENTION 
   A sidelobe signal canceler receives input signals from a main transducer and from one or more auxiliary transducers, which may be antennas or sonic or other transducers, and produces correlation signals among the various input signals. An intermediate weighting signal generator produces intermediate weighting signals from the correlation signals for application to a weighting signal generator. The weighting signal generator produces weighting signals for application to weighting signal FIR filters or simple multipliers, in which the received auxiliary signals are each multiplied by one or more weights, to produce weighted signals. The weighted auxiliary signals are summed, and the sum is subtracted from the main signal to eliminate sidelobe signals. 
   In an embodiment in which weighting is performed by means of an FIR filter, the auxiliary signals being weighted are delayed in the filter to produce sequential samples. The intermediate weighting signal generator in that embodiment may include a plurality of correlator arrays, each receiving the main and auxiliary signals. Each correlator array performs correlations among the signals applied thereto (and delayed versions thereof) and a different one of the applied signals, to produce a plurality of correlation signals, some of which are autocorrelation signals. Another embodiment simplifies the FIR filter to a simple multiplier. This embodiment includes ranks of correlators which receive input signals from the main transducer and from the auxiliary transducers. Within each rank, one correlator receives a particular auxiliary signal at both inputs, and acts as autocorrelator. Also within each rank, the particular auxiliary signal is applied as one input to all other correlators, and either the main signal or one of the other auxiliary signals is applied as the other input, to produce ranks of correlation signals. Corresponding ranks of associated processors include a row of dividers in each rank, and in ranks other than the first rank also include rows of C and D processors. At least one C processor of each rank receives the autocorrelation coefficient from the corresponding rank of correlators, and the D processors of one row of each rank receive the other correlation coefficients from the corresponding rank of correlators. Outputs of C and D processors of each rank other than the first rank are applied to inputs of dividers for directly producing intermediate weighting functions. The intermediate weighting functions are further processed, and applied to multipliers or FIR filters which process the auxiliary signals to produce weighted auxiliary signals. The weighted auxiliary signals are summed, and the sum is subtracted from the main signal to eliminate sidelobe signals. 

   
     DESCRIPTION OF THE DRAWING 
       FIG. 1   a  is a simplified block diagram of a radar system including delays and FIR filters,  FIG. 1   b  is a simplified block diagram of an FIR filter of  FIG. 1   a , and  FIG. 1   c  is a simplified block diagram of a delay of  FIG. 1   a;    
       FIG. 2   a  is a simplified block diagram of a system similar to that of  FIG. 1   a , in which multipliers are substituted for the FIR filters, and in which center delays are dispensed with,  FIG. 2   b  is a simplified block diagram of a weighting signal generator which may be used in the arrangements of  FIGS. 1   a  and  2   a , and  FIG. 2   c  is a simplified block diagram of processors of  FIG. 2   b;    
       FIG. 3   a  is a simplified diagram of an array of correlators in accordance with the invention, which may be used as part of an apparatus for generating intermediate weighting signals in the arrangements of  FIG. 1   a  or  2   a , and  FIGS. 3   b  and  3   c  together are a simplified block diagram of an array of processors used in conjunction with the correlators of  FIG. 3   a  to form the apparatus which generates intermediate weighting signals; 
       FIG. 4  is a skeletonized diagram illustrating the locations of correlators which may perform superfluous correlations in the arrangement of  FIG. 3   a  or  4  when the received signal samples are mutually delayed relative to each other; and 
       FIG. 5  is a simplified block diagram of a radar system with sidelobe cancellation, similar to that of  FIG. 1   a , in which the delay elements are incorporated into the correlators, whereby each of multiple sets of received signals includes mutually delayed samples; 
       FIG. 6   a  is a simplified block diagram of the correlator arrangement of  FIG. 4 , and  FIG. 6   b  is a simplified block diagram illustrating a portion of the correlator arrangement of  FIG. 6   a.    
   

   DESCRIPTION OF THE INVENTION 
   In  FIG. 3   a , a plurality of correlators are arranged in ranks and columns, with decreasing numbers of correlators in lower ranks. As illustrated in  FIG. 3   a , highest Rank  1  includes five correlators  310   1,1 ,  310   1,2 ,  310   1,3 ,  310   1,4  and  310   1,5 . The correlators of Ranks  2 ,  3  and  4  are similarly designated, with the first subscript representing the correlator&#39;s Rank and the second subscript designating the column. 
   Received, delayed auxiliary signal vector x 1  is applied to both input ports of correlator  310   1,1  of  FIG. 3   a , and to one input port of each of the other correlators  310   1,y  of Rank  1 . Delayed main signal vector x 5  is applied to an input port of correlator  310   1,5 , and to an input port of each of the other correlators  310   2,5 ,  310   3,5 , and  310   4,5  of column  5 . Received, delayed, auxiliary signal x 2  is applied to an input port of correlator  310   1,2  of Rank  1 , to both input ports of correlator  310   2,2 , and to one input port of each of the other correlators  310   2,y  of Rank  2 . Received, delayed, auxiliary signal x 3  is applied to an input port of correlators  310   1,3  of Rank  1 , and correlator  310   2,3  of Rank  2 , to both input ports of correlator  310   3,3  of Rank  3 , and to an input port of each of the other correlators  310   3,4  and  310   3,5  of Rank  3 . Delayed, received input signal x 4  is applied to an input port of correlators  310   1,4 ,  310   2,4  and  310   3,4  of Ranks  1 ,  2  and  3 , respectively, to both input ports of correlators  310   4,4  of Rank  4 , and to an input port of the remaining correlator of Rank  4 , namely correlator  310   4,5 . Each of the correlators produces a signal h x,y  representing the correlation of the two input signals; in the cases of correlators  310   1,1 ,  310   2,2 ,  310   3,3 , and  310   4,4  which receive the same signal at both input ports, the correlation output signals are autocorrelation signals. The correlation signals h x,y  produced by the array of correlators of  FIG. 3   a  are made available to the structure of  FIGS. 3   b  and  3   c.    
     FIG. 3   d  is a simplified block diagram of a representative correlator  310  of  FIG. 3   a . In  FIG. 3   d , a first input signal path  398  is coupled to a circuit  390  designated by an asterisk (*), which represents a circuit for generating the complex conjugate of the input signal. the complex conjugate is applied from circuit  390  to an input of a summing multiplier (xΣ)  392 , and the signal from input data path  396  is applied to the second input of summing multiplier  392 . The output signal from summing multiplier  392  is the sum of the product of the signal applied to path  396  multiplied by the complex conjugate of the signal applied to data path  398 . 
   In  FIGS. 3   b  and  3   c , dividing processors  312 , “C” processors  314 , and “D” processors  316 , are arrayed in Ranks  1 ,  2 ,  3 ,  4  and  5 . Within each rank, processors  312 ,  314  and  316  are arranged in rows. The number of rows increases with increasing rank; Rank  1  has only one row, Rank  2  has two rows, Rank  3  has three rows, and Rank  4  has four rows. The number of columns of processors within a row decreases with increasing rank. Row  1  of Rank  1  contains four processors, Row  2  of Rank  2  contains three divider processors, and Row  3  of Rank  3  contains two processors. Within each Rank, the last row is a row of divider processors  312 . Thus, Rank  1  has only one row, and that row is a row of divider processors  312 . Rank  2  has two rows, the second or last of which is a row of divider processors  312 , and Rank  3  has 3 rows, the last row of which is a row of dividers. The desired intermediate weighting coefficients (l x,y ) are produced in sets at the outputs of the last row of processors, namely the row of divider processors, of each rank. Thus, Rank  1  as illustrated in  FIG. 3   b  produces a set of four intermediate weighting coefficients l 1,2 , l 1,3 , l 1,4  and l 1,5 , while Rank  4  ( FIG. 3   c ) produces a set of one intermediate weighting coefficients, namely intermediate weighting coefficient l 4,5 . 
   More specifically, in  FIG. 3   b , divider processor  312   1,1  receives h 11  and h 12  signals, and divides h 12  by h 11  to produce l 1,2 , which is applied to an input port  2  of a C processors  314   2,1,1 , which is described in more detail below. In the designation  314   2,1,1 , the first subscript designates the Rank, the second subscript designates the column, and the third subscript denotes the row which the processor occupies within the rank. Thus, C processor  314   2,1,1  is in the second rank, first column, and occupies a portion of the first row within the second rank. C processor  314   2,1,1  receives h 22  at its input port  3  from a correlator of Rank  1  of  FIG. 3   a , and also receives h 11 , redesignated as L 1,1 , at its input port  1 . C processor  314   2,1,1  includes output ports designated  1  and  2 . Output port  1  of C processor  314   2,1,1  is connected to input ports  1  of each of D processors  316   2,2,1 ,  316   2,3,1 , and  316   2,4,1 . 
   Input port  2  of each D processor  316   2,2,1 ,  316   2,3,1  and  316   2,4,1  of Row  1  of Rank  2  of  FIG. 3   b  is connected to the corresponding divider processor  312   1,2 ,  312   1,3 ,  312   1,4 , respectively, of the previous rank, to receive the intermediate weighting coefficients l 1,3 , l 1,4  and l 1,5 , respectively, produced thereby. Each D processor  316   2,2,1 ,  316   2,3,1  and  316   2,4,1 , of Row  1  of Rank  2  also has its input port  3  coupled to receive h 23 , h 24  and h 25 , respectively, from Rank  2  of the correlators of  FIG. 3   a . The outputs from D processors  316   2,2,1 ,  316   2,3,1  and  316   2,4,1  are applied to input ports of divider processors  312   2,2,2 ,  312   2,3,2  and  312   2,4,2 , respectively, and D processor output signal in each divider processors is divided by a L 1,2  signal produced on conductor  320  by output port  2  of C processor  314   2,1,1 . Divider processors  312   2,2,2 ,  312   2,3,2  and  312   2,4,2  of  FIG. 3   b  produce the set of desired intermediate weighting coefficients l 23 , l 24  and l 25  for application to processor  50  of  FIG. 1   a , and which are also applied as inputs to the C and D processors of Row  1  of Rank  3  of  FIG. 3   b.    
   Processor Rank  3  of  FIG. 3   c  includes three rows. The first row includes C processor  314   3,2,1  and D processors  316   3,3,1  and  316   3,4,1 . C processor  314   3,2,1  of Rank  3 , Row  1  receives at its input port  1  the L 1,2  signal from output port  2  of C processor  314   2,1,1 , by way of path  320 . C processor  314   3,2,1  also receives at its input port  2  the l 23  intermediate weighting coefficient from divider processor  312   2,2,2 , and receives correlation coefficient h 33  at its input port  3 . The output port  1  signal from C processor  314   3,2,1  is applied in common to input ports  1  of Row  1 , Rank  3  D processors  316   3,3,1  and  316   3,4,1 . Input ports  2  of Row  1 , Rank  3  D processor  316   3,3,1  and  316   3,4,1  receive l 24  and l 25 , respectively, from the divider processors  312  of the next higher rank, namely Rank  2 . Input ports  3  of Rank  3 , Row  1  D processors  316   3,3,1  and  316   3,4,1  receive correlation coefficients h 34  and h 35 , respectively, from Rank  3  of the correlators of  FIG. 3   a.    
   Row  2  of Rank  3  of  FIG. 3   b  includes one C processor and two D processors, the same as Row  1 . C processor  314   3,2,2  of Rank  3  receives the L 1,1  signal from path  318  at its input port  1 , the l 1,3  intermediate weighting coefficient from divider processor  312   1,2  at its input port  2 , and the output port  2  signal from Row  1  C processor  314   3,2,1  at its input port  3 . The output port  1  signal is applied in common to input ports  1  of Row  2  D processors  316   3,3,2  and  316   3,4,2 . Input port  3  of D processor  316   3,3,2  receives signal from the output port of D processor  316   3,3,1  in the previous row, and input port  3  of D processor  316   3,4,2  receives signal from the output port of D processor  316   3,4,1 . 
   Row  3  of Rank  3  of  FIG. 3   b  includes divider processors  312   3,3,3  and  312   3,4,3 , which receive signal from the output ports of D processors  316   3,3,2  and  316   3,4,2  of Row  2 , and which also receive divisor signals from output port  2  of C processors  314   3,2,2  of Row  2 . Divider processors  312   3,3,3  and  312   3,4,3  of Row  3  of Rank  3  together produce the set of intermediate weighting coefficients l 34  and l 35 , which are made available to processor  50  of  FIG. 1   a , and which are also applied to input ports  2  of C processor  314   4,3,1  and D processor  316   4,4,1 , respectively, which are located in Row  1  of Rank  4 . C processor  314   4,3,1  also receives at its input port  1  the signal from output port  2  of C processor  314   3,2,2 , and at its input port  3  the h 44  correlation coefficient from Rank  4  of  FIG. 3   a . The signal at output port  1  of C processor  314   4,3,1  of Row  1  of Rank  4  is applied to input port  1  of Row  1  D processor  316   4,4,1 . Input port  2  of D processor  316   4,4,1  receives the l 35  intermediate weighting coefficient from divider processor  312   3,4,3 , and input port  3  receives correlation coefficient h 45  from correlator Rank  4  of  FIG. 3   a.    
   The signal from output port  2  of Row  1 , Rank  4  C processor  314   4,3,1  of  FIG. 3   c  is applied to input port  3  of Rank  4 , Row  2  C processor  314   4,3,2 , and the output signal from Row  1  D processor  316   4,4,1  is applied to input port  3  of Row  2  D processor  316   4,4,2 . Input port  1  of Row  2  C processor  314   4,3,2  receives L 1,2  signal from output port  2  of C processor  314   2,1,1  of  FIG. 3   b , and input port  2  of Row  2  C processor  314   4,3,2  receives, by way of path  326 , the l 24  intermediate weighting coefficient from Row  2  Rank  2  divider processor  312   2,3,2 . Input port  1  of Row  2 , Rank  4  D processor  316   4,4,2  is coupled to receive signal from output port  1  of Row  2  C processor  314   4,3,2 , input port  2  of Row  2 , Rank  4  D processor  316   4,4,2  is coupled to receive, by way of path  332 , the l 25  intermediate weighting coefficient from Row  2 , Rank  2  divider  312   2,4,2 , and input port  3  of Row  2 , Rank  4  D processor  316   4,4,2  is coupled to the output port of Row  1  D processor  316   4,4,1 . 
   In Rank  4 , Row  3  of  FIG. 3   c , C processor  314   4,3,3  has its input port  1  coupled, by way of path  318 , to receive the L 1,1  signal, its input port  2  coupled, by way of path  324 , to receive intermediate weighting coefficient l 14  from Rank  1  divider  312   13 , and its input port  3  coupled to the output port  2  of Rank  3 , Row  2  C processor  314   4,3,2 . Also in Rank  4 , Row  3  of  FIG. 3   c , D processor  316   4,4,3  has its input port  1  coupled to output port  1  of C processor  314   4,3,3 , to input port  2  coupled, by way of path  330 , to receive intermediate weighting coefficient l 15  from Rank  1  divider processor  312   14 , and its input port  3  coupled to the output of Rank  4 , Row  2  D processor  316   4,4,2 . 
   In Row  4  of Rank  4  of  FIG. 3   c , divider processor  312   4,4,4  divides the output of Row  3  D processor  316   4,4,3  by the output port  2  signal of C processor  314   4,3,3 , to produce intermediate weighting coefficient l 45 . As mentioned, the intermediate weighting coefficients are coupled in sets from the divider processors of  FIGS. 3   b  and  3   c  to processor  50  of  FIG. 1  to produce the final weighting coefficients as described in the aforementioned Yuen dissertation. 
     FIG. 3   e  is a simplified block diagram illustrating details of the C and D processors of  FIGS. 3   b  and  3   c . For definiteness, C processor  314   2,1,1  and D processor  316   2,2,1  of  FIG. 3   b  are shown. In  FIG. 3   e , C processor  314   2,1,1  includes a first multiplier  386 , which receives correlation coefficient h 12  at its first input port. A second multiplier  388  receives at its first input port, the complex conjugate (*) of h 12  from a circuit  387 . Multiplier  388  also receives L 1,1 , signal (which is renamed autocorrelation coefficient h 11 ) at its second input port, and produces a product, which is applied to the second input port of multiplier  386 , and which is also coupled by way of first output port (O 1 ) of C processor  314   2,1,1  to the first input port (I 1 ) of D processor  316   2,2,1 . The output signal from multiplier  386  of C processor  314   2,1,1  of  FIG. 3   e  is applied to an inverting (−) input port of a summing circuit  384 , and autocorrelation coefficient h 22  is from input port I 3  applied to its noninverting (+) input port. The sum signal produced at the output port of summing circuit  384  is made available at output port  2  (O 2 ) of C processor  314   2,1,1  and is coupled onto path  320 . 
   D processor  316   2,2,1  of  FIG. 3   e  includes a multiplier  378  which has a first input port I 1  coupled to receive signal from output port O 1  of C processor  314   2,1,1 , and a second input port I 2  coupled to receive intermediate weighting coefficient l 1,3 . Multiplier  378  produces product signals, which are applied to the inverting input port of a summing circuit  376 , which also receives at its noninverting input port the h 23  correlation coefficients applied to input port I 3 . Summing circuit  376  produces sum signals for application by way of data path  361  to divider processor  312   2,2,2  of  FIG. 3   b.    
   The arrangement of  FIGS. 3   a ,  3   b ,  3   c ,  3   d  and  3   e  reduces the number of computations required to produce the desired intermediate weighting coefficients by comparison with the arrangement of  FIGS. 2   b  and  2   c . In the case of ten input vectors, each with a length of 100 range cells, the improved arrangement requires 576 multiplies and 468 additions, compared with 4500 and 4500. This saving results from not calculating residues. 
   In some cases, it may be desired to determine intermediate weighting coefficients for a system such as that of  FIGS. 1   a ,  1   b  and  1   c , using the correlation array of  FIG. 3   a . In a case such as that of  FIG. 1   a , some of the input vectors to the correlator array are time-shifted versions of the same input signal. Suppose, for example, that  FIG. 4  is a simplified or skeletonized representation of the correlator array, in this case similar to that of array  240   a  of  FIG. 3   a , but including a larger number of correlators. In  FIG. 4 , each correlator of the array is illustrated by a circle  410 . Along the top of the array, the input signals are designated A 1n , A 1n-1  . . . A 1n-3 , A 2n , A 2n-1  . . . A 2n-3 , A 3n , A 3n-1 , A 3n-2  . . . A 3n-3 , and the main signal ML, where A 1n , A 2n , A 3n , and ML are independent signals, and where the other input signals are delayed versions thereof. In  FIG. 4 , open circles  410 , such as the circle representing correlator  410   1,1 , represent those correlations which must be performed, and those circles  410  marked with crosses, such as the circle representing correlator  410   2,3 , represent supernumerary or duplicative correlations. 
   As illustrated in the array of  FIG. 4 , the correlations necessary to the required correlations form distinct patterns or structures, and these structures are surrounded by rectangles for emphasis. The desired end result of the correlation portion of the formation of the intermediate weighting signals is the correlation of each independent input signal with each other independent input signal. Thus, the currently applied signal A 1n  is autocorrelated in correlator  410   1,1 . Since the signal at any moment is not necessarily the same as the signal at the next moment, even in the same channel, the current signal must also be correlated with the older or delayed signal in the same channel, which corresponds to correlations represented by correlators  410   11 ,  410   12 , and  410   13 . Independent signal A 1n  must also be correlated with independent signal A 2n  (correlator  410   1,5 ) and with the signals A 2n-1  . . . A 2n-3  delayed therefrom (correlators  410   1,6 ,  410   1,7  and  410   1,8 ), and also with independent signal A 3n  and its delayed versions A 3n-1 , A 3n-2 , and A 3n-3 , which is accomplished in correlators  410   1,9 ,  410   1,10 ,  410   1,11  and  410   1,12 , and finally, independent input signal A 1n  is correlated with the main signal in correlator  410   1,13 . Thus, the correlations of input signal A 1n  with all other input signals are performed in the upper row of correlators of  FIG. 4 , and those correlators are therefore surrounded by a horizontally oriented box  412  to indicate their relationship. 
   In  FIG. 4 , autocorrelator  410   2,2  is not needed because the correlation of input signal A 1n-1  with itself is the same as the autocorrelation of input signal A 1n  with itself, which is performed in correlator  410   1,1 . Thus, a cross appears in correlator  410   2,2 . indicating that it is not necessary. Similarly, autocorrelators  410   3,3 ,  410   4,4 ,  410   6,6 , . . .  410   12,12  are not necessary and are therefore designated by crosses. 
   The correlations performed by correlators  410   2,3 ,  410   2,4  and  410   3,4  of  FIG. 4  are likewise redundant, because they are the correlations of mutually delayed samples of the input signal, which are already available from the correlators of block  412 . The correlators of vertically-oriented block  414  of  FIG. 4 , namely  410   1,5 ,  410   2,5 ,  410   3,5 ,  410   4,5  and  410   5,5 , represent the necessary correlations of independent signal A 2n  with itself, and with all the signals related to input signal A 1n  and its delayed versions. The correlators of horizontally-oriented block  516  correspond, in a way, with the correlators of the upper row (of block  410 ), in that they represent the correlation of independent signal A 2 , with itself (correlator  410   5,5 ) and with all other signals to the right. Following the same pattern, a vertical block  418  surrounds those correlators producing required correlations between independent input signal A 3n  and all input signals to its left, and a horizontal block  420  surrounds those correlators producing required correlations between independent input signal A 3n  and all signals to its right. Lastly, a vertically oriented block  422  surrounds all those correlators required for correlating main input signal ML with all the signals to its left. As illustrated in  FIG. 4 , 45 correlators (those without a cross designation) out of 90 are actually required, and an additional 45 (those designated by crosses) are not necessary and may be dispensed with. 
     FIG. 5  is a simplified block diagram of a radar beamformer or sidelobe canceller, simplified according to an aspect of the invention by eliminating the redundancies identified in  FIG. 4 . Those elements of  FIG. 5  corresponding to elements of  FIG. 1   a  are designated by like reference numerals. In  FIG. 5 , the received signals produced by receivers  28   a  . . . .  28   m  are applied over paths  29   a  . . .  29   s  to inputs of a correlator block  510 , which is illustrated in more detail in  FIGS. 6   a  and  6   b . Correlator block  510  of  FIG. 5  produces the correlation coefficients (the h&#39;s) required for application to intermediate weighting signal generator  512  of  FIG. 5 , which in turn produces the intermediate weighting signals (the l&#39;s) for application to processor  50 . 
   Correlator block  510  of  FIG. 5  performs the correlations required to produce h 1,1 , h 1,2 , h 1,3  . . . h 1,13 , from a plurality of independent received signals arriving over paths  29   a  . . .  29   s , but which, for each independent signal, requires mutual delays. 
     FIG. 6   a  is a simplified block diagram of correlator  510  of  FIG. 5 . In  FIG. 6   a , elements corresponding to those of  FIG. 5  are designated by like reference numerals. As illustrated in  FIG. 6   a , correlator  510  of  FIG. 5  is broken into a plurality of correlator arrays or sections  514   a ,  514   b ,  514   c , and  514   d , each of which includes a plurality of input ports  1 ,  2 ,  3 ,  4  and  5 . Also illustrated in  FIG. 6   a  are four input data paths  31 ,  29   s ,  29   b  and  29   a , carrying the ML, and A 1n , A 2n , and A 3n  signals, respectively. 
   In  FIG. 6   a , signals A 1n  arriving on data path  29   s  are applied to input ports  1  of each of correlator arrays  514   a ,  514   b ,  514   c  and  514   d , and are also applied to input port  5  of correlator array  514   a . Signals A 2n  arriving on data path  29   b  are applied to input ports  2  of each of the four correlator arrays  514 , and to input port  5  of correlator array  514   b . Signals A 3n  arriving on data path  29   a  are applied to input ports  4  of each of the four correlator arrays  514 , and to input port  5  of correlator array  514   c . ML signals arriving on data path  31  are applied to input ports  4  of each of the four correlator arrays  514 , and to input port  5  of correlator array  514   d . The signal applied to input port  5  of a correlator array  514  determines which autocorrelation coefficient is produced. For example, correlator array  514   a  produces the autocorrelation of A 1n . As described below, each correlator array  514  produces the desired correlation coefficients h. More particularly, correlator array  514   a  of  FIG. 5  produces h 1,1 , the autocorrelation of signals A 1n  applied to its input port  5 , and also produces cross-correlations between A 1n  and each of A 2n , A 3n  and ML. Correlator array  514   d  produces h 1,13 *, the complex conjugate of the desired autocorrelation of signal ML, as well as the complex conjugates of the desired cross-correlations between ML and each of A 1n , A 2n  and A 3n . Correlator arrays  514   b  and  514   c  each produce an intermixture of the desired correlation coefficients and the complex conjugates thereof. When a correlator array of  FIG. 6   a  produces the desired (auto) correlation coefficient directly, it is coupled directly, as by data paths  318  and  398  at the outputs of correlator array  514   a , for use by the processor of  FIGS. 3   b  and  3   c . When a correlator array  514  of  FIG. 6   a  produces the complex conjugate of the desired correlation coefficient, it is coupled to the processor of  FIGS. 3   b  and  3   c  by way of a further complex conjugate operator, a plurality of which are represented by three complex conjugate operator blocks  516   x ,  516   y  and  516   z  in  FIG. 6   a.    
     FIG. 6   b  illustrates details of one embodiment of a correlator array  514  of  FIG. 6   a . For definiteness,  FIG. 6   b  represents correlator array  514   a  of  FIG. 6   a , and elements of  FIG. 6   b  corresponding to those of  FIG. 6   a  are designated by like reference numerals. In  FIG. 6   b , correlator array  514   a  includes subsets of correlators designated  600   1 ,  600   2 ,  600   3 , . . .  600   N ,  600   ML . Each correlator set  600   X  (except set  600   ML ) includes a plurality of shift registers forming a tapped delay line, and a plurality of summing multipliers, one of which is associated with each tap. Each correlator set  600   X  is also associated with a complex conjugate (*) circuit  690 , which therefore forms part of each of each subset of correlators. In  FIG. 6   b , signals A 1n  arriving over path  29   s  are applied by way of port  5  to complex conjugate circuit  690  for generating the complex conjugate (*) of the current A 1n  signal on a path  688 , and the A 1n  signal is also applied by way of port  1  and a tap  699   a  to a delay element in the form of a shift register (S)  638   a , which is part of correlator subset  600   1 . The A 1n  signal at tap  699   a  is applied to a XΣ  692   a  together with the * signal from circuit  690 , to produce autocorrelation coefficient h 11 . The delayed output from S  638   a  is applied by way of a tap  699   b  to the inputs of a XΣ  692   b  and an S  638   b . Summing multiplier  692   b  produces correlation signal h 12 . The twice-delayed signal from S  638   b  is made available at tap  699   c  to a further S  638   c  and to XΣ  692   c . Summing multiplier  692   c  produces h 13  from the * signal on path  688  and the delayed signal at tap  699   c . the thrice-delayed signal from S  638   c  is applied by way of tap  699   d  to XΣ  692   d  together with * signal from path  688 , to produce h 14 . Thus, correlator subset  600   1 , produces h 11 , h 12 , h 13  and h 14 . 
   Similarly, independent received signal A 2n  is applied over data path  29   b  and port  2 , and by way of a tap  699   e  to inputs of a XΣ  692   e  and an S  638   d  of correlator subset  600   2 . Summing multiplier  692   e  also receives the * signal, and produces h 15 . The delayed output signal from S 638   d  passes in succession through S  638   e  and S  638   f , and is made available at taps  699   f ,  699   g  and  699   h  to XΣ  692   f ,  692   g  and  692   h , for generating h 16 , h 17  and h 18 . The remainder of the structure will be apparent from the above description, except that main signal ML is applied over data path  31  to a first input of a summing multiplier  691 , together with the * signal from circuit  690 , to produce correlation coefficient h 1,13 . Correlator subset  600   ML  therefore includes only xΣ  691 . 
   Comparison of  FIGS. 6   a  and  6   b  shows that the only difference in operation among correlator arrays  514   a, b, c  and  d  aries from the application of a different one of input signals A 1n , A 2n , A 3n  and ML to input port  5 . When signals A 2n  are applied to input port  5  instead of signals A 1n , the cross-correlations of signals A 1n  with A 2n  are produced as complex conjugates of the desired cross-correlations, while the autocorrelation of signals A 2n , and the cross-correlations of signals A 2  with A 3n  and with ML are produced directly. Thus, the cross-correlations of signals A 1n  with A 2n  are passed through a complex conjugate circuit such as  516  of  FIG. 6   a  before being applied to a processor for generating intermediate weighting signals. When signal A 3  is applied to input port  5 , the cross-correlations of signals A 1n  and A 2n  with A 3 , are produced as complex conjugates, and the autocorrelations of signals A 3n , and the cross-correlation of signals A 3n  with ML, are produced directly. When signals ML are applied to input port  5 , all the h s  are produced as complex conjugates of the desired h s . As mentioned, when the signal produced at an output port of a correlator array  514  of  FIG. 6   b  is the complex conjugate of the desired signal, a complex conjugate operation (blocks  516  of  FIG. 6   a ) produces the desired signal. 
   Other embodiments of the invention will be apparent to those skilled in the art. In particular, processing may be accomplished in analog or digital form, or an intermixture thereof. Also, while three shift registers  638  and four taps  699  are illustrated in  FIG. 6   b  for processing each independent auxiliary signal, more or fewer delays may be used, to provide the desired number of correlation coefficients, as needed for the various FIR filters in  FIG. 6   a . The number of stages may be different from filter to filter.