Abstract:
The invention provides a circuit substrate structure and a method for manufacturing thereof. The circuit substrate structure includes a substrate, a pixel array layer, a display unit, a peripheral circuit layer, at least one integrated circuit chip, a flexible printed circuit board, at least one flattening material layer and a passivation layer. In the circuit substrate structure, the flattening material layer is positioned on the peripheral circuit layer, and possesses at least one opening corresponded to and around the integrated circuit chip. By positioning the flattening material layer, the circuit substrate structure possesses a flat surface, and prevents producing air bubbles, so as to enhance the reliability of the display device.

Description:
RELATED APPLICATIONS 
     This application claims priority to Taiwanese Application Serial Number 102100947 filed Jan. 10, 2013, which is herein incorporated by reference. 
     BACKGROUND 
     Technical Field 
     The present disclosure relates to a circuit substrate structure, and more particularly, to a circuit substrate structure having a flattening material layer. 
     Description of Related Art 
       FIG. 1  is a sectional view of a traditional circuit substrate structure  100 , which includes a substrate  110 , a pixel array layer  120 , a display unit  130  an integrated circuit chip  140 , a flexible printed circuit board  150 , a passivation layer  160  and a sealant  170 . 
     In  FIG. 1 , the pixel array layer  120  is positioned on the substrate  110 , and has a display area (not shown) and a non-display area (not shown). The display area  130  is positioned on the display area of the pixel array layer  120 . The integrated circuit chip  140  and the flexible printed circuit board  150  are positioned on the non-display area of the pixel array layer  120 , and electrically connected to each other through the pixel array layer  120 . The passivation layer  160  covers the display unit  130 . Then the sealant  170  is infiltrated by capillary action into the space between the passivation layer  160  and the pixel array layer  120 , and cured by heating. 
     However, in a traditional display device, the sealant  170  is originally in liquid form without a fixed shape, so that the surface of the non-display area of the display area is not even. Besides, since the structure of the traditional display device has a difference in height forming several blind angles, the sealant  170  fails to uniformly infiltrate thereinto and thus generate several bubbles  180 . The bubbles  180 , after the heat-curing step of the sealant  170 , are expanded to lift off the passivation layer  160  and the display unit  130 , so as to deteriorate the reliability of the display device. Therefore, there is a need for an improved circuit substrate structure and a method of manufacturing the same, so as to solve the problems met in the art. 
     SUMMARY 
     The present disclosure provides a circuit substrate structure having a flattening material layer and a method for manufacturing thereof, so as to solve the problems of the prior art and achieve the purpose of flattening the display device. 
     One embodiment of the present disclosure is to provide a circuit substrate structure. The circuit substrate structure comprises a substrate, a pixel array layer, a display unit, a peripheral circuit layer, at least one integrated circuit chip, a flexible printed circuit board, at least on flattening material layer and a passivation layer. The substrate has a display area and a non-display area. The pixel array layer is positioned on the display area of the substrate. The display unit is positioned on the pixel array layer. The peripheral circuit layer is positioned on the non-display area of the substrate, and electrically connected to the pixel array layer. The integrated circuit chip is positioned on the peripheral circuit layer, and electrically connected to the pixel array layer. The flexible printed circuit board is positioned on the peripheral circuit layer, and electrically connected to the integrated circuit chip, the pixel array layer or the combinations thereof. The flattening material layer is positioned on the peripheral circuit layer, and covers a portion of the flexible printed circuit board. Wherein the flattening material layer has at least one opening which corresponds to and surrounds the integrated circuit chip. The passivation layer is positioned on and covers the display unit and the flattening material layer. 
     Another embodiment of the present disclosure is to provide a method for manufacturing the circuit substrate structure. The method for manufacturing the circuit substrate structure comprises providing a substrate having a display area and a non-display area, forming a pixel array layer on the display area of the substrate, forming a display unit on the pixel array layer, forming a peripheral circuit layer, on the non-display area of the substrate, forming at least one integrated circuit chip, on the peripheral circuit layer, forming a flexible printed circuit board on the peripheral circuit board, forming at least one flattening material layer on the peripheral circuit layer, and forming a passivation layer on the display unit and the flattening material layer. In which, the peripheral circuit layer is electrically connected to the pixel array layer. The integrated circuit chip is electrically connected to the pixel array layer. The flexible printed circuit board is electrically connected to the integrated circuit chip, the pixel array layer or the combinations thereof. The flattening material layer covers a portion of the flexible printed circuit board, and has at least one opening corresponding to and surrounding the integrated circuit chip. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a sectional view of a traditional circuit substrate structure  100 ; 
         FIG. 2A  is a three dimensional view of a circuit substrate structure  200   a  according to one embodiment of the present disclosure; 
         FIG. 2B  is an exploded view of the circuit substrate structure  200   a  of  FIG. 2A ; 
         FIG. 2C  is a sectional view of the circuit substrate structure  200   a  taken along the line A-A′ of  FIG. 2A ; 
         FIG. 2D  is a sectional view of a circuit substrate structure  200   b  according to one embodiment of the present disclosure; 
         FIG. 3A to 3G  are sectional views of making a circuit substrate structure  300   a  according to one embodiment of the present disclosure; and 
         FIG. 3H to 3I  are sectional views of making a circuit substrate structure  300   b  according to one embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The embodiments of the circuit substrate structure and the method for manufacturing the same of the present disclosure are discussed in detail below, but not limited the scope of the present disclosure. The same symbols or numbers are used to the same or similar portion in the drawings or the description. And the applications of the present disclosure are not limited by the following embodiments and examples which the person in the art can apply in the related field. 
       FIG. 2A  is a three dimensional view of a circuit substrate structure  200   a  according to an embodiment of the present disclosure, and  FIG. 2B  is an exploded view of the circuit substrate structure  200   a  of  FIG. 2A . The circuit substrate structure  200   a  comprises a substrate  210 , a pixel array layer  220 , a display unit  230 , a peripheral circuit layer  240 , at least one integrated circuit chip  250 , a flexible printed circuit board  260 , at least one flattening material layer  270   a  and a passivation layer  280 . 
     In  FIGS. 2A and 2B , the substrate  210  has a display area  211  and a non-display area  212 . And the pixel array layer  220  and the display unit  230  is positioned sequentially on the display area  211  of the substrate  210 . According to one example of the present disclosure, the material of the substrate  210  comprises glass, hard plastics or flexible plastics. According to one example of the present disclosure, the pixel array layer  220  comprises a thin-film transistor layer. According to one example of the present disclosure, the display unit  230  comprises a front panel, a liquid crystal display medium layer, or a light-emitting diode display medium layer. The front panel includes an E-paper medium layer, such as electrophoretic display medium layer. 
     The peripheral circuit layer  240  is positioned on the non-display area  212  of the substrate  210 , and electrically connected to the pixel array layer  220 . The integrated circuit chip  250 , the flexible printed circuit board  260  and the flattening material layer  270   a  are positioned on the peripheral circuit layer  240 . According to one example of the present disclosure, the peripheral circuit layer  240  comprises a thin-film transistor layer or a conductive circuit layer. According to one example of the present disclosure, the integrated circuit chip  250  comprises a driving circuit chip. 
     The flattening material layer  270   a  covers a portion of the flexible printed circuit board  260 , and has at least one opening  271   a . Each opening  271   a  corresponds to and surrounds the integrated circuit chip  250 . Then, the passivation layer  280  is positioned on and covers the display unit  230  and the flattening material layer  270   a . According to one example of the present disclosure, the material of the passivation layer  280  comprises flexible plastics. 
       FIG. 2C  is a sectional view of the circuit substrate structure  200   a  taken along the line A-A′ of  FIG. 2A . In  FIG. 2C , the flattening material layer  270   a  is positioned on the peripheral circuit layer  250 , and the integrated circuit chip  250  is in the opening  271   a . Besides, the flattening material layer  270   a  is contacted tightly with the neighboring display unit  230 , and the passivation layer  280  can directly cover the flattening material layer  270   a  and the display unit  230  without filling a sealant. 
       FIG. 2D  is a sectional view of a circuit substrate structure  200   b  according to one embodiment of the present disclosure. In  FIG. 2D , a flattening material layer  270   b  is positioned on the peripheral circuit layer  250 , and the integrated circuit chip  250  is in a opening  271   b . The flattening material layer  270   b  is not contacted with the display unit  230 , and a sealant  290  is positioned between the flattening material layer  270   b  and the display unit  230 . According to one example of the present disclosure, the sealant  290  is positioned between the flattening material layer and the display unit, and in the opening  291   b  of the flattening material layer  270   b . According to one example of the present disclosure, the sealant  290  is heat curing adhesive, optical light-sensitive adhesive or after-light-sensitive heat curing adhesive. According to one example of the present disclosure, the flattening material layer  270   b  covers more than 50% of the non-display area  212  of the substrate  210 . 
     According to one example of the present disclosure, the coefficient of linear thermal expansion of the flattening material layer  270   a  or  270   b  is less than 70×10 −6 /K. According to one example of the present disclosure, the material of the flattening material layer  270   a  or  270   b  comprises glass, polyethylene terephthalate (PET), polyethylene naphthalene dicarboxylate (PEN), polymethyl methacrylate (PMMA), polycarbonate (PC), polystyrene (PS), or the combinations thereof. According to one example of the present disclosure, the thickness of the flattening material layer  270   a  or  270   b  is the same as the thickness of the display unit  230 . According to one example of the present disclosure, the thickness of the flattening material layer  270   a  or  270   b  is larger than or equal to the integrated circuit chip  250 . 
       FIG. 3A to 3G  are sectional views of making the circuit substrate structure  300   a  according to one embodiment of the present disclosure. In  FIG. 3A , a substrate  310  is provided and has a display area  311  and a non-display area  312 . Then, a pixel array layer  320  is formed on the display area  311  of the substrate  310 , shown as  FIG. 3B . In  FIG. 3C , a display unit  330  is formed on the pixel array layer  320 . 
     In  FIG. 3D , a peripheral circuit layer  340  is formed on the non-display area  312  of the substrate  310 , in which the peripheral circuit layer  340  is electrically connected to the pixel array layer  320 . Then at east one integrated circuit chip  350  and a flexible printed circuit board  360  is formed on the peripheral circuit layer  340 , shown as  FIG. 3E . 
     In  FIG. 3F , a flattening material layer  370   a  is formed on the peripheral circuit layer  340  and contacted tightly with the neighboring display unit  330 , and covers a portion of the flexible printed circuit board  360 . The flattening material layer  370   a  has at least one opening  371   a , and the opening  371   a  corresponds to and surrounds the integrated circuit chip  350 . According to one example of the present disclosure, the flattening material layer  370   a  can be used to protect the integrated circuit chip  350 . 
     In  FIG. 3G , a passivation layer  380  is formed on and covers the display unit  330  and the flattening material layer  370   a , so as to form the circuit substrate structure  300   a . Because the flattening material layer  370   a  is tightly contacted with the display unit  330  without a gap, there is no need to fill with a sealant. The passivation layer  380  can cover directly the display unit  330  and the flattening material layer  370   a , and the circuit substrate structure  300   a  having flattening surface is provided. Thus, the step of optical or heat curing of the sealant is negligible, so as to reduce the manufacturing cost and prevent from the destruction of the heat treatment process on the display unit. 
     Noteworthy, because the flattening material layer  370   a  is tightly contacted with the display unit  330  without a gap, the circuit substrate structure  300   a  cannot occur the bubble issue as the prior art. According to one example of the present disclosure, the circuit substrate structure  300   a  can be applied to a display device. 
       FIG. 3H to 3I  are sectional views of making a circuit substrate structure  300   b  according to one embodiment of the present disclosure.  FIG. 3H  is followed by the structure shown in  FIG. 3E . In  FIG. 3H , a flattening material layer  370   b  is formed on the peripheral circuit layer  340 , and covers a portion of the flexible printed circuit board  360 . The flattening material layer  370   b  has at least one opening  371   b , and the opening  371   b  corresponds to and surrounds the integrated circuit chip  350 . A sealant  390  is formed between the flattening material layer  370   b  and the display unit  330 , and in the opening  371   b  of the flattening material layer  370   b . According to one example of the present disclosure, the sealant  390  is formed only between the flattening material layer  370   b  and the display unit  330 . According to one example of the present disclosure, the flattening material layer  370   b  can be used to protect the integrated circuit chip  350 . 
     In  FIG. 3I , a passivation layer  380  is formed on and covers the display unit  330  and the flattening material layer  370   b , so as to form the circuit substrate structure  300   b . And then the circuit substrate structure  300   b  should be performed the optical or heat curing step of the sealant  390 , so as to provide a circuit substrate structure  300   b  having flattening surface. According to one example of the present disclosure, the circuit substrate structure  300   b  can be applied to a display device. 
     Unlike to the traditional process, the method for manufacturing the circuit substrate structure  300   b  as one example of the present disclosure is firstly forming the sealant  390  between the flattening material layer  370   b  and the display unit  330 , and then covering the passivation layer  380 . This helps to avoid blind angle generated due to a height difference in the circuit substrate structure, and bubbles formed in the sealant filling. Besides, the method provided in the present disclosure can efficiently solve the bubble issue generated in the art. 
     It is noteworthy that the usage amount and area of the sealant, according to the embodiments of the present disclosure, can be significantly reduced by adding the flattening material layer into the circuit substrate structure, so as to achieve the purpose of flattening the surface of the circuit substrate structure. On the other hand, the method provided in the present disclosure can also solve the bubble issue generated in the circuit substrate structure. According to the example of the present disclosure, the steps of filling sealant and optical or heat curing can be completely omitted in the process of manufacturing the circuit substrate structure, so as to reduce the product cost and prevent the display device from the destruction after the heat-treatment. 
     Although embodiments of the present disclosure and their advantages have been described in detail, they are not used to limit the present disclosure. It should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the present disclosure. Therefore, the protecting scope of the present disclosure should be defined as the following claims.