Abstract:
The invention provides a stacked wafer structure with decreased failures. In one embodiment, there is a barrier layer deposited on exposed surfaces of conductors that extend across a distance between first and second device structures. The barrier layer may prevent diffusion and electromigration of the conductor material, which may decrease incidences of shorts and voids in the stacked wafer structure.

Description:
BACKGROUND 
     1. Field of the Invention 
     This invention relates to stacked wafer integrated circuits, and more particularly to use of a barrier layer on patterned connecting structures to prevent diffusion and electromigration. 
     2. Background of the Invention 
     Stacked integrated circuits have conductors extending between bonded wafers. These conductors can have exposed surfaces which can lead to reliability problems.  FIG. 1  is a side cross section view of an example conventional stacked integrated circuit  100  that illustrates such problems. The stacked integrated circuit  100  has a first device structure  102 . The first device structure  102  includes a substrate layer  104  and an oxide layer  106 . Copper conductors  108  extend from the oxide layer  106  of the first device structure  102  to a second device structure  110 . The conductors  108  have exposed surfaces  112  because the first and second device structures  102 ,  110  are spaced a distance  114  apart. Because the conductors  108  have exposed surfaces  112 , and because copper can diffuse through oxide easily, issues such as copper diffusion and electromigration may occur. This can lead to shorting of the stacked integrated circuit  100  or voids in the conductors  108 . Either of these problems can cause the stacked integrated circuit  100  to malfunction. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The various embodiments of the invention are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which: 
         FIG. 1  is a side cross section view of an example conventional stacked integrated circuit that illustrates reliability problems. 
         FIG. 2  is a side cross section view of an embodiment of a stacked integrated circuit according to one embodiment of the present invention. 
         FIG. 3  is a flow chart that illustrates how the barrier layer may be formed according to one embodiment. 
         FIG. 4  shows two device structures connected together by conductors. 
         FIG. 5  illustrates one way in which a device structure may be exposed to a solution. 
         FIG. 6  illustrates another way in which a device structure may be exposed to a solution. 
         FIG. 7  illustrates yet another way in which a device structure may be exposed to a solution. 
         FIGS. 8   a  and  8   b  are cross section side views of first and second device structures illustrating how the barrier layer may be applied to surfaces of the conductors prior to bonding the first and second device structures together. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 2  is a side cross section view of an embodiment of a stacked integrated circuit  200  according to one embodiment of the present invention. The stacked integrated circuit  200  may include a first device structure  202 . The first device structure  202  may be an integrated circuit that includes one or more layers, which may include patterned materials and devices in various embodiments. In an embodiment, the first device structure  202  may include a substrate layer  204  and an oxide layer  206  formed over the substrate layer  204 . In the illustrated embodiment, the oxide layer  206  is at a top surface of the first device structure  202 . 
     Patterned conductors  208  may be formed connected to the first device structure  202 , and may be considered as part of the first device structure  202  or separate from the first device structure  202 . In an embodiment, these conductors  208  may be copper pillars that extend above the top surface of the first device structure  202 , and also extend below the top surface of the first device structure  202  into the oxide layer  206 . In other embodiments, the conductors  208  may extend from the top surface of the first device structure  202  without extending into the oxide layer  206 , may be located differently, be different shapes, and/or made from different materials. 
     A second device structure  210  may be bonded to the conductors  208 . The second device structure  210  may be an integrated circuit that includes one or multiple layers, which may include patterned materials and devices in various embodiments. The second device structure  210  may have conductors  208  that extend from the second device structure  210 . These conductors  208  extending from the second device structure  210  may be considered as part of the second device structure  210  or separate from the second device structure  210 . 
     The first and second device structures  202 ,  210  may be connected by the conductors  208 , structurally and/or electrically. The conductors  208  also space the first and second device structures  202 ,  210  a distance  214  apart. This distance  214  means there is a gap between the first and second device structures  202 ,  210 . The conductors  208  cross this gap. The distance  214  between the first and second device structures  202 ,  210  may range from about 50 nm to about 500 nm. Both the first and second device structures  202 ,  210  may have conductors extending from the respective device structures  202 ,  210 . The conductors  208  of the first device structure  202  may be bonded to conductors  208  of the second device structure  210  to connect the first and second device structures  202 ,  210 . Other ways to connect the first and second device structures  202 ,  210  may also be used. 
     The conductors  208  may have surfaces  212  that extend between the first and second device layers  202 ,  210 . There may be a barrier layer  216  that substantially covers the surfaces  212  of the conductors  208 . The barrier layer  216  may be a layer of cobalt, or other materials may also be used. This barrier layer  216  substantially prevents the surfaces  212  of the conductors  208  from being exposed in the distance  214  between the first and second device structures  202 ,  210 . While in an embodiment, the conductors  208  are a copper to copper bonded structure, the conductors  208  may also be a copper to tin bonded structure, a silicon-to-gallium arsenide bonded structure, or another structure that would otherwise be exposed without the barrier layer  216 . The barrier layer  216  acts as a diffusion barrier. 
     The stacked integrated circuit  200  of  FIG. 2  may be connected to other devices. For example, the stacked integrated circuit  200  may be packaged and connected to a circuit board. The circuit board may connect the stacked integrated circuit  200  to other components. The stacked integrated circuit  200 , circuit board, and other components may together form a computer system, with input and output devices, a processor, and memory. 
       FIG. 3  is a flow chart  300  that illustrates how the barrier layer  216  may be formed according to one embodiment. One or more of the device structures, such as the first or second device structures  202 ,  210 , are formed  302 . Referring now to  FIG. 4 , a cross section view of formed  302  device structures  202 ,  210  is illustrated.  FIG. 4  shows two device structures  202 ,  210  connected together by conductors  208 . In other embodiments, a single device structure  202  or  210  with conductors  208  extending from the device structure  202  or  210  may be formed  302 . As seen in  FIG. 4 , the conductors  208  have exposed surfaces  212  in the distance  214  between the device structures  202 ,  210 . 
     Returning to  FIG. 3 , the one or more conductors  208  between the device structures may be exposed  304  to a solution. This solution may contain one or more materials (cobalt in one embodiment) that may form the barrier layer  216 . When exposed to the solution, materials in the solution may be deposited on the conductors  208  to form the barrier layer  216 . In an embodiment, the solution may be an electroless plating bath and the materials deposited on the conductors  208  via electroless plating. Such a bath may include cobalt ions in embodiments where the barrier layer  216  comprises cobalt. With such cobalt-containing solutions, the cobalt within the solution may be selectively deposited on the surfaces  212  of the conductors  208 , such as exposed copper conductor  208  surfaces  212 , by electroless deposition to form the barrier layer  216 . 
     Referring now to  FIG. 5 , one way in which the conductors  208  of one or more device structures may be exposed  304  to a solution is illustrated. In  FIG. 5 , a container  502  contains solution  504 . Device structures  202  and  210  may be dipped partially or completely into the solution  504  in the container. The solution  504  may then come into contact with the surfaces  212  of the conductors  208  so that cobalt or another material in the solution  504  may be deposited on the conductors  208  to form the barrier layers  216  shown in  FIG. 2 . Capillary action or pressure may aid the solution in reaching the surfaces  212  of the conductors  208 . 
     Referring now to  FIG. 6 , another way in which the conductors  208  of one or more device structures may be exposed  304  to a solution is illustrated. In  FIG. 6 , a syringe  602  is used to apply solution  604  near the surfaces  212  of the conductors  208 . A syringe  602  may be a device that is capable of applying solution at a selected position. This selected position may be a position near the surfaces  212  of the conductors  208 , so that the solution may come into contact with the surfaces  212  to form the barrier layer  216  on the surfaces. Use of such a syringe  602  may be useful, for example, if the distance  214  between the first and second device structures  202 ,  210  is so small that the solution might not reach the surfaces  212  when using the exposure method illustrated in  FIG. 5 . 
     Referring now to  FIG. 7 , yet another way in which the conductors  208  of one or more device structures may be exposed  304  to a solution is illustrated. In  FIG. 7 , supercritical CO 2    702  may be used to carry the solution to the surfaces  212  of the conductors  208 . The solution itself may be in an aerosol form and carried to the surfaces  212  by the supercritical CO 2    702  flowing to the surfaces  212 , or may be in another form to be brought to the surfaces by the supercritical CO 2    702 . The supercritical CO 2    702  can penetrate small spaces and may be useful, for example, if the distance  214  between the first and second device structures  202 ,  210  is so small that the solution might not reach the surfaces  212  when using the exposure method illustrated in  FIG. 5 . Other methods to expose  304  the surfaces  212  of the conductors  208  of device structures  202 ,  210  to the solution, such a flow of substances different from supercritical CO 2    702  carrying the solution, may also be used. 
     Returning to  FIG. 3 , excess solution may be removed  306 . This may happen after the barrier layer  216  has been formed. A flow of gas or liquid past the device structures  202 ,  210  may be used to remove  306  excess solution. For example, a flow of supercritical CO 2  may be used to remove  306  excess solution. Other methods may be used as well. 
       FIGS. 8   a  and  8   b  are cross section side views of first and second device structures  202 ,  210  illustrating how the barrier layer  216  may be applied to surfaces  212  of the conductors  208  prior to bonding the first and second device structures  202 ,  210  together.  FIG. 8   a  is a cross section side view that illustrates a first device structure  202  that is not bonded to the second device structure  210 . The barrier layer  216  has been formed on the conductors  208  of the first device structure  202 , so that the surfaces  212  of the conductors  208  are substantially covered. The barrier layer  216  may be formed as described with respect to  FIGS. 3 through 7 , above. A barrier layer  216  may similarly be formed on conductors  208  of a second device structure  210  as well.  FIG. 8   b  is a cross section side view that illustrates the first and second device structures  202 ,  210  bonded together, where the barrier layer  216  has been formed on the conductors of one or both of the first and second device structures  202 ,  210  prior to bonding. In such a case, there may be part of the barrier layer  216  between the conductors  208  of the first and second device structures  202 ,  210 . Alternatively, the barrier layer  216  may be removed from part of the conductor  208  prior to bonding. 
     The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. This description and the claims following include terms, such as left, right, over, under, upper, lower, first, second, etc. that are used for descriptive purposes only and are not to be construed as limiting. The embodiments of a device or article described herein can be manufactured, used, or shipped in a number of positions and orientations. Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above teaching. Persons skilled in the art will recognize various equivalent combinations and substitutions for various components shown in the Figures. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.