Abstract:
A block correlation table includes block addresses of unusable block portions in an irreversibly writeable memory and includes addresses of associated substitute block portions in the irreversibly writeable memory. A request for data stored at a logical address is received from a host processor. A physical address in the irreversibly writeable memory is calculated from the logical address using a fixed mathematical relation. The physical address is compared with the block addresses in the block correlation table. When the physical address does not match any of the block addresses in the table, the irreversibly writeable memory is referenced to read data stored at the physical address, and when the physical address matches one of the block addresses in the table, the irreversibly writeable memory is referenced to read data stored at the address of its associated substitute block portion. The read data is transmitted to the host processor.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is a continuation of U.S. application Ser. No. 10/149,552, filed Oct. 1, 2002, the disclosure of which is incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     The present invention relates to a data managing method for a memory apparatus using an irreversibly write memory.  
         [0003]     In a system that uses an electrically erasable memory, with a precondition that data stored therein is rewritten, for a process that correlates logical information and physical information, physical information corresponding to all logical information is required. In addition, as another precondition, a process that correlates logical information and physical information using a redundant portion peculiar to such an electrically erasable memory is required. Moreover, since such an electrically erasable memory has a verify function that verifies written data by itself, it is not necessary to externally verify data.  
         [0004]     Unlike with an electrically erasable memory, an irreversibly write memory of which data can be written one time is known. This memory is called a write once type memory or OTP (One Time Programmable ROM). Normally, an irreversibly write memory is non-volatile. In other words, once data is written to an irreversibly write memory, the data cannot be erased. Thus, after the power of an irreversibly write memory is turned off, data stored therein is retained.  
         [0005]     When a data managing method for an electrically erasable memory is applied for the forgoing irreversibly write memory, the irreversibly write memory may not be effectively controlled. In addition, a correlation table for logical information and physical information results in a decrease of the memory capacity that the user can use.  
         [0006]     It is therefore desirable to provide a data managing method that can be suitably and effectively applied to an irreversibly writeable memory.  
       SUMMARY OF THE INVENTION  
       [0007]     In accordance with the invention, a method is provided for managing data stored in a memory apparatus having an irreversibly writeable memory. The method includes receiving a request from a host processor for data stored at a logical address; calculating a physical address in the irreversibly writeable memory from the logical address using a fixed mathematical relation; providing a block correlation table that includes block addresses of only unusable block portions in the irreversibly writeable memory and addresses of substitute block portions in the irreversibly writeable memory each associated with a specific one of the block addresses of the unusable block portions; comparing the physical address with the block addresses in the block correlation table; referencing the irreversibly writeable memory to read data stored at the physical address when the physical address does not match any of the block addresses in the block correlation table and referencing the irreversibly writeable memory to read data stored at the address of its associated substitute block portion when the physical address matches one of the block addresses in the block correlation table; and transmitting the read data to the host processor. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]      FIG. 1  is a block diagram showing an example of a system structure of a memory apparatus according to the present invention.  
         [0009]      FIG. 2  is a block diagram showing another example of the system structure of the memory apparatus according to the present invention.  
         [0010]      FIG. 3  is a schematic diagram for explaining an example of an unusable block correlation table.  
         [0011]      FIG. 4  is a schematic diagram for explaining another example of the unusable block correlation table.  
         [0012]      FIG. 5  is a flow chart showing an example of a referencing process for the unusable block correlation table.  
         [0013]      FIG. 6  is a flow chart showing another example of the referencing process of the unusable block correlation table.  
         [0014]      FIG. 7  is a schematic diagram showing an example of mapping reference information.  
         [0015]      FIG. 8  is a schematic diagram showing another example of mapping reference information.  
         [0016]      FIG. 9  is a flow chart showing an example of a read requesting process with logical information.  
         [0017]      FIG. 10  is a flow chart showing another example of the read requesting process with logical information.  
         [0018]      FIG. 11  is a flow chart showing an example of the read requesting process with physical information in the case that the unusable block correlation table is referenced by the memory apparatus.  
         [0019]      FIG. 12  is a flow chart showing an example of the read requesting process with physical information in the case that the unusable block correlation table is referenced by a host system.  
         [0020]      FIG. 13  is a flow chart showing an example of the read requesting process with physical information in the case that a cell number is calculated and the unusable block correlation table is referenced by the memory apparatus.  
         [0021]      FIG. 14  is a flow chart showing an example of the read requesting process with physical information in the case that a cell number is calculated by the memory apparatus and the unusable block correlation table is referenced by the host system.  
         [0022]      FIG. 15  is a flow chart showing an example of the read requesting process with physical information in the case that the unusable block correlation table is referenced by the memory apparatus.  
         [0023]      FIG. 16  is a flow chart showing an example of the read requesting process with physical information in the case that the unusable block correlation table is referenced by the host system.  
         [0024]      FIG. 17  is a flow chart showing an example of a verify process that determines whether or not a write error takes place and a process that adds the content of the unusable block correlation table.  
     
    
     DETAILED DESCRIPTION  
       [0025]     Next, with reference to the accompanying drawings, an embodiment of the present invention will be described.  FIG. 1  shows the structure of the system according to the embodiment of the present invention. A host system  40  and a memory apparatus  1  are connected through communication paths  31  and  41 . The memory apparatus  1  is a card shaped device that is removable from the host system  40 . The memory apparatus  1  has a communicating portion  30  that communicates with the host system  40 .  
         [0026]     The memory apparatus  1  has a data processing portion  20  and a memory portion  50 . The memory portion  50  is an irreversibly write memory that is called OTP and of which data can be written one time. The memory apparatus  1  is also a non-volatile semiconductor memory. In other words, data that has been written to the memory portion  50  cannot be erased. After the power of the memory apparatus  1  is turned off, the stored data is retained. In the memory portion  50 , data is read and written in a predetermined data unit. The memory portion  50  has a boot area from which data is initially read by the host system when the memory is attached thereto. A variety of types of information such as attribute information are pre-recorded in the boot area.  
         [0027]     The data processing portion  20  and the communicating portion  30  are connected through internal buses  21  and  32 . Likewise, the data processing portion  20  and the memory portion  50  are connected through internal buses  22  and  51 . The data processing portion  20  can access memory management information  10  through internal buses  13 ,  23 , and  14 . The memory management information  10  contains an unusable block correlation table  11  and mapping reference information  12 .  
         [0028]     A memory apparatus  1 ′ shown in  FIG. 2  has a memory portion  56 . The memory portion  56  has a plurality of memory cells each of which is an irreversibly write memory. Internal data buses  22  and  51  are disposed between a memory portion  56  and a data processing portion  20 . In this example, memory management information  10  is stored in a non-volatile memory. In this case, the memory management information  10  may be stored in a memory integrated with a memory portion  50 . Alternatively, the memory management information  10  may be stored in the memory portion  50 ,  56 .  
         [0029]     The host system  40  can write data to the memory portion  50 ,  56  of the memory apparatus  1 ,  1 ′ and read data therefrom. An example of the host system  40  is a personal computer. Another example of the host system  40  is a digital electronic camera. A photographed picture is written to the memory apparatus  1 ,  1 ′. In addition, a picture is read from the memory apparatus  1 ,  1 ′. Another example of the host system  40  is an audio recording/reproducing apparatus. In this case, compressed audio data is written to the memory apparatus  1 ,  1 ′. In addition, compressed audio data is read from the memory apparatus  1 ,  1 ′.  
         [0030]      FIG. 3  shows an example of the unusable block correlation table  11  of the memory apparatus  1  that has one memory portion  50 . The table  11  has an unusable block number portion  60  and a substitute block number portion  61 . The unusable block number portion  60  contains k unusable block numbers in succession. The substitute block number portion  61  contains substitute block numbers corresponding to unusable block numbers.  FIG. 4  shows an unusable block correlation table  11  of the memory apparatus  1 ′ shown in  FIG. 2 . The unusable block correlation table  11  of the memory apparatus  1 ′ has an unusable block portion  62  and a substitute block number portion  63 . The unusable block portion  62  contains unusable block numbers in succession. The substitute block number portion  63  contains substitute block numbers in succession. In addition, each of the unusable block portion  62  and the substitute block number portion  63  contain cell numbers that distinguish a plurality of memory cells.  
         [0031]     The unusable block correlation table  11  is created by the data processing portion  20 . In the memory apparatus  1  shown in  FIG. 1 , when the data processing portion  20  recognizes any unusable physical block in the memory portion  50 , the data processing portion  20  sets the block number thereof to the unusable block number portion  60  through the internal bus  13 , designates a substitute usable block number, and sets the designated block number to the substitute block number portion  61 .  
         [0032]     In the memory apparatus  1 ′ shown in  FIG. 2 , when the data processing portion  20  recognizes any unusable physical block in the memory portion  56 , the data processing portion  20  sets the block number and the cell number thereof to the unusable block number portion  62 , designates a substitute usable block number and a cell number, and sets the designated block number and cell number to the substitute block number portion  63 . In the memory apparatus  1 ′ shown in  FIG. 2 , each cell may has an unusable block correlation table. In this case, the table is structured as shown in  FIG. 3 .  
         [0033]     Next, with reference to  FIG. 5 , a method for referencing the unusable block correlation table created in the forgoing manner will be described. At step S 1 , the physical block number to be processed is designated as N phy . At step S 2 , i is initialized. At step S 3 , it is determined whether or not the i-th unusable block matches the physical block number N phy . When they do not match, the flow advances to step S 4 . At step S 4 , i is incremented. At step S 5 , it is determined whether or not i is equal to or larger than (k−1). At steps S 3 , S 4 , and S 5 , it is determined whether or not the physical block number N phy  is an unusable block number.  
         [0034]     When the determined result at step S 3  represents that the physical block number N phy  matches the i-th unusable block, the flow advances to step S 6 . At step S 6 , an i-th substitute block is used instead of the physical block number N phy . Thereafter, the process is completed. In contrast, when the determined result at step S 5  represents that i is equal to or larger than (k−1), the flow advances to step S 7 . At step S 7 , the physical block number N phy  is not an unusable block, but a usable block. Thereafter, the process is completed.  
         [0035]     When physical block numbers or logical information of the unusable block correlation table are sorted in the ascending order or descending order, the process that references the unusable block correlation table can be performed at high speed.  FIG. 6  is a flow chart showing a high speed referencing process accomplished by sorting physical block numbers in the ascending order.  
         [0036]     At step S 11 , a physical block number N phy  is designated as an object to be processed. At step S 12 , i is initialized. At step S 13 , it is determined whether or not an i-th unusable block matches the physical block number N phy . When they do not match, the flow advances to step S 14 . At step S 14 , it is determined whether or not the physical block number N phy  is equal to or smaller than the i-th unusable block.  
         [0037]     When the determined result at step S 14  represents that the physical block number N phy  is neither equal to nor smaller than the i-th unusable block, the flow advances to step S 15 . At step S 15 , i is incremented. At step S 16 , it is determined whether or not i is equal to or larger than (k−1) At steps S 13 , S 14 , S 15 , and S 16 , it is determined whether or not the physical block number N phy  is an unusable block number.  
         [0038]     When the determined result at step S 13  represents that the physical block number N phy  matches the i-th unusable block, the flow advances to step S 17 . At step S 17 , an i-th substitute block is used instead of the physical block number N phy . Thereafter, the process is completed. When the determined result at step S 14  represents that the physical block number N phy  is equal to or smaller than the i-th unusable block, the flow advances to step S 18 . At step S 18 , the physical block number N phy  is not an unusable block, but a usable block. Thereafter, the process is completed. When the determined result at step S 16  represents that i is equal to or larger than (k−1), the flow advances to step S 18 . At step S 18 , the physical block number N phy  can be used. Thereafter, the process is completed.  
         [0039]     In the process shown in  FIG. 6 , at step S 14 , it is determined whether or not the physical block number N phy  is equal to or smaller than an i-th unusable block. Since unusable blocks have been sorted in the ascending order, if the relation is satisfied, it can be determined that the physical block number N phy  can be used without need to check the rest of the table. Thus, the process can be performed at high speed.  
         [0040]     Next, the mapping reference information  12  of the memory apparatus  1  and  1 ′ will be described. The mapping reference information  12  contains information necessary for converting logical information into physical information.  FIG. 7  shows the mapping reference information  12  of the memory apparatus  1 . The mapping reference information  12  is composed of a logical-physical conversion criterion  15  and a logical-physical conversion multiplier  16 . The logical-physical conversion criterion  15  is in reality 0, +2, or the like. The logical-physical conversion multiplier  16  is in reality 4, ½, or the like.  
         [0041]      FIG. 8  shows the mapping reference information  12  of the memory apparatus  1 ′. As with the mapping reference information  12  of the memory apparatus  1 , the mapping reference information  12  of the memory apparatus  1 ′ has a logical-physical conversion criterion  15  and a logical-physical conversion multiplier  16 . In addition, the mapping reference information  12  of the memory apparatus  1 ′ has a physical block number  17  corresponding to the number of cells of the memory portion. The physical block number  17  is in reality  512 ,  1024 , or the like.  
         [0042]     The content of the mapping reference information  12  is set when the memory apparatus  1 ,  1 ′ is structured. When the logical information unit is the same as the physical information unit and logical address  0  matches physical block number  0  in the memory apparatus  1 , the logical-physical conversion criterion  15  and the logical-physical conversion multiplier  16  of the mapping reference information  12  are set to “0” and “1”, respectively. When the logical information unit is twice as large as the physical information unit and logical address  0  corresponds to physical block numbers  4  and  5  in the memory apparatus  1 , the logical-physical conversion criterion  15  and the logical-physical conversion multiplier  16  of the mapping reference information  12  are set to “4” and “2”, respectively. When the logical information unit is ¼ times as small as the physical information unit and logical addresses  0 ,  1 ,  2 , and  3  correspond to physical block number  3  in the memory apparatus  1 , the logical-physical conversion criterion  15  and the logical-physical conversion multiplier  16  of the mapping reference information  12  are set to “3” and “¼”, respectively.  
         [0043]     When the logical information unit is the same as the physical information unit thereof, the number of physical blocks per cell of the memory portion is 1024, and logical address  0  corresponds to physical block number  2  in the memory apparatus  1 ′, the logical-physical conversion criterion  15 , the logical-physical conversion multiplier  16 , and the physical block number  17  per cell of the mapping reference information  12  are set to “2”, “1”, and “1024”, respectively.  
         [0044]     With the forgoing mapping reference information  12 , a converting process from logical information into physical information is performed. In the system that uses the memory apparatus  1  shown in  FIG. 1 , an equation that calculates the physical block number N phy  with the logical address N log  is expressed as follows. 
 
 N   phy   =N   log   ×N   MUL   +N   BASE  
 
 where N BASE  is a designated value of the logical-physical conversion criterion  15  and N MUL  is a designated value of the logical-physical conversion multiplier  16 . 
 
         [0045]     In the system that uses the memory apparatus  1 ′ shown in  FIG. 2 , an equation that calculates the physical block number N phy  and the memory cell number N cell  with the logical address N log  can be expressed as follows. 
 
 N   phy =( N   log   ×N   MUL   +N   BASE )%  N   BLKNUM  
        (% represents an operation that obtains the remainder.) 
 
 N   cell =( N   log   ×N   MUL   +N   BASE )÷ N   BLKNUM  
 
 where N BASE  is a designated value of the logical-physical conversion criterion  15 , N MUL  is a designated value of the logical-physical conversion multiplier  16 , and N BLKNUM  is a designated value per cell. 
       
 
         [0047]     The forgoing converting process from logical information into physical information is performed by the data processing portion  20 . Alternatively, the converting process may be performed by the host system  40 . In this case, as an initializing process, the host system  40  should read and retain the content of the memory management information  10  from the memory apparatus  1 ,  1 ′.  
         [0048]      FIG. 9  is a flow chart showing the data reading process with the logical information N log  in the case that the process that converts logical information into physical information is performed by the data processing portion  20  of the system shown in  FIG. 1 . At step S 21 , a data read request for the logical address N log  is supplied from the host system  40  to the memory apparatus  1 . The data processing portion  20  receives the read request through the communicating portion  30  (at step S 22 ).  
         [0049]     At step S 23 , the data processing portion  20  calculates the physical block number N phy  corresponding to the logical address N log  and the designated values N BASE  and N MUL  of the mapping reference information  12 . At step S 24 , the data processing portion  20  determines that the physical block number N phy  is not an unusable block with reference to the unusable block correlation table  11 . This process corresponds to the process shown in  FIG. 5  or  FIG. 6 . At step S 25 , it is determined whether or not the physical block number N phy  is an unusable block. When the physical block number N phy  is an unusable block, the flow advances to step S 26 . At step S 26 , a substitute block number is used instead of the physical block number N phy .  
         [0050]     At step S 27 , the physical block number N phy  is read from the memory portion  50 . The read data is denoted by DATA (N phy ) DATA (N phy ) is supplied to the data processing portion  20  (at step S 28 ). DATA (N phy ) is supplied from the data processing portion  20  to the communicating portion  30  (at step S 29 ). The communicating portion  30  supplies the read data DATA (N phy ) to the host system  40  (at step S 30 ).  
         [0051]      FIG. 10  is a flow chart showing the data read process with the logical information N log  in the case that the process that converts logical information into physical information is performed by the data processing portion  20  of the system shown in  FIG. 2 . Steps S 21 , S 22 , and S 23  shown in  FIG. 9  correspond to steps S 31 , S 32 , and S 33  shown in  FIG. 10 , respectively. At step S 33 , the data processing portion  20  calculates the physical block number N phy  and the cell number N cell  corresponding to the logical address N log  and the designated values N BASE , N MUL , and N BLKNUM  of the mapping reference information  12 .  
         [0052]     Steps S 24 , S 25 , S 26 , S 27 , S 28 , S 29 , and S 30  shown in  FIG. 9  correspond to steps S 34 , S 35 , S 36 , S 37 , S 38 , S 39 , and S 40  shown in  FIG. 10 , respectively. In  FIG. 10 , since the memory portion  56  is composed of a plurality of memory cells, the cell number N cell  that designates a cell is used in addition to the physical block number N phy .  
         [0053]      FIG. 11  is a flow chart showing the data reading process with the logical information N log  in the case that the process that converts logical information into physical information is performed by the host system  40  in the system shown in  FIG. 1 . As an initializing process, the host system  40  supplies a read request for the mapping reference information  12  to the memory apparatus  1 . The memory apparatus  1  supplies the mapping reference information  12  to the host system  40 . The host system  40  converts a logical address into the physical block number N phy  corresponding to the mapping reference information  12 . Thus, at step S 41 , the host system  40  supplies a data read request for the physical block number N phy  to the memory apparatus  1 . The data processing portion  20  receives the read request through the communicating portion  30  (at step S 42 ).  
         [0054]     At step S 43 , the data processing portion  20  determines that the physical block number N phy  is not an unusable block with reference to the unusable block correlation table  11 . At step S 44 , it is determined whether or not the physical block number N phy  is an unusable block. When the physical block number N phy  is an unusable block, the flow advances to step S 45 . At step S 45 , a substitute block number is used instead of the physical block number N phy .  
         [0055]     At step S 46 , the physical block number N phy  is read from the memory portion  50 . The read data is denoted by DATA (N phy ) DATA (N phy ) is supplied to the data processing portion  20  (at step S 47 ). The data processing portion  20  supplies DATA (N phy ) to the communicating portion  30  (at step S 48 ). The communicating portion  30  supplies the read data DATA (N phy ) to the host system  40  (at step S 49 ).  
         [0056]      FIG. 12  is a flow chart showing the data reading process with the logical information N log  in the case that the process that converts logical information into physical information is performed by the host system  40  in the system shown in  FIG. 1 . In the process shown in  FIG. 12 , the host system  40  converts a logical address into the physical block number N phy . In addition, the host system  40  performs a referencing process for the unusable block correlation table obtained from the memory apparatus  1 . Thus, the referencing process for the unusable block correlation table shown in  FIG. 11  (at steps S 43 , S 44 , and S 45 ) is not required in  FIG. 12 . Except for this point, the process shown in  FIG. 12  is the same as the process shown in  FIG. 11 . For simplicity, in  FIG. 12 , similar steps to those in  FIG. 11  are denoted by similar reference numerals and their description will be omitted.  
         [0057]      FIG. 13  is a flow chart showing a data reading process with physical information N Globalphy  supplied from the host system  40  in the system shown in  FIG. 2 . N Globalphy  is a value of which the physical information N phy  and N cell  are added as a numeric value. At step S 51 , the host system  40  supplies a data read request for physical information N Globalphy  to the memory apparatus  1 . The data processing portion  20  receives the read request through the communicating portion  30  (at step S 52 ).  
         [0058]     At step S 53 , the data processing portion  20  calculates physical information N phy  and N cell  corresponding to N Globalphy  and designated values N BASE , N MUL  and N BLKNUM  of the mapping reference information  12 . At step S 54 , the data processing portion  20  determines that the physical information N phy , N cell  is not an unusable block with reference to the unusable block correlation table  11 . At step S 55 , it is determined whether or not N phy , N cell  is an unusable block. When N phy , N cell  is an unusable block, the flow advances to step S 56 . At step S 56 , a substitute block number is used instead of N phy , N cell .  
         [0059]     At step S 57 , physical information N phy , N cell  is read from the memory portion  56 . The read data is denoted by DATA (N cell N phy ). DATA (N cell , N phy ) is supplied to the data processing portion  20  (at step S 58 ). The data processing portion  20  supplies DATA (N cell , N phy ) to the communicating portion  30  (at step S 59 ). The communicating portion  30  supplies the read data DATA (N cell , N phy ) to the host system  40  (at step S 60 ).  
         [0060]      FIG. 14  is a flow chart showing a data reading process with physical information N Globalphy  supplied from the host system  40  in the system shown in  FIG. 2 . In the process shown in  FIG. 14 , the host system  40  performs a referencing process for the unusable block correlation table. Thus, in the process shown in  FIG. 14 , the referencing process for the unusable block correlation table (at steps S 54 , S 55 , and S 56 ) shown in  FIG. 13  is not required. Except for this point, the process shown in  FIG. 15  is the same as the process shown in  FIG. 13 . For simplicity, in  FIG. 14 , similar steps to those in  FIG. 13  are denoted by similar reference numerals and their description will be omitted.  
         [0061]      FIG. 15  is a flow chart showing a data reading process with physical information N cell , N phy  supplied from the host system  40  in the system shown in  FIG. 2 . At step S 61 , the host system  40  supplies a data read request for physical information N cell , N phy  to the memory apparatus  1 . In the process shown in  FIG. 13 , physical information N Globalphy  is used. In contrast, in the process shown in  FIG. 15 , the host system  40  calculates physical information N cell , N phy  that represents a cell number and a block number. This physical information is supplied to the memory apparatus  1 . Thus, step S 53  at which N cell , N phy  are calculated shown in  FIG. 13  is not required. Except for this point, the process shown in  FIG. 15  is the same as the process shown in  FIG. 13 . For simplicity, in  FIG. 15 , similar steps to those in  FIG. 13  are denoted by similar reference numerals and their description will be omitted.  
         [0062]      FIG. 16  is a flow chart showing a data reading process with physical information N cell , N phy  supplied from the host system  40  in the system shown in  FIG. 2 . In the process shown in  FIG. 16 , the host system  40  performs a referencing process for the unusable block correlation table. Thus, in the process shown in  FIG. 16 , the referencing process for the unusable block correlation table shown in  FIG. 15  (at steps S 54 , S 55 , and S 56 ) is not required. Except for this point, the process shown in  FIG. 16  is the same as the process shown in  FIG. 15 . For simplicity, in  FIG. 16 , similar steps to those in  FIG. 15  are denoted by similar reference numerals and their description will be omitted.  
         [0063]      FIG. 17  is a flow chart for explaining a function that performs a verifying process that verifies whether or not a writing process requested by the host system  40  has been correctly completed. At step S 71 , the data processing portion  20  performs a writing process for the physical block number N phy  to the memory portion  50 . The writing process is performed in the same manner as the forgoing reading process. At step S 72 , the writing process starts. At step S 73 , the data processing portion  20  waits until the writing process is completed.  
         [0064]     Immediately after the writing process is completed, the reading process is performed with the physical block number N phy  (at step S 74 ). The read data is denoted by DATA R  (N phy ) At step S 75 , DATA R  (N phy ) is compared with DATA W  (N phy ) (write data). When they match, assuming that the writing process has been normally completed, the process is completed (at step S 76 ).  
         [0065]     When the determined result at step S 75  represents that the read data matches the write data, it is determined that the writing process has not been normally performed. At step S 77 , the physical block number N phy  is added to the unusable block correlation table. At step S 78 , the data processing portion  20  decides a substitute block corresponding to the physical block number N phy . At step S 79 , the substitute block is designated as a content of the unusable block correlation table. At step S 80 , the physical block number N phy  is substituted with the designated substituted block number. Thereafter, the flow returns to step S 71 .  
         [0066]     It should be noted that the present invention is not limited to the forgoing embodiment. In other words, without departing from the spirit of the present invention, various modifications and applications of the forgoing embodiment are available. For example, when the contents of the unusable block correlation table have been sorted in the ascending order, it is determined whether or not a physical block number of a block to be processed is larger (smaller) than ½ of the maximum physical block number. Corresponding to the determined result, the determination order of whether or not an objective block is an unusable block may be selected. In other words, the ascending order or descending order is selected.  
         [0067]     According to the present invention, since the correlation table does not contain logical information and physical information for all blocks, the storage capacity of the irreversibly write memory open to the user can be increased. In addition, according to the present invention, since a conversion between logical information and physical information can be performed by a calculation, even if mapping information is lost, data can be accessed to some extent.