Abstract:
A method of manufacturing semiconductor devices includes forming an interlayer insulation film over a semiconductor substrate, the substrate having a first gate structure for a memory cell and a second gate structure for a control transistor, the interlayer insulation film overlying the first and second gate structures; annealing the interlayer insulation film; etching the interlayer insulation film to form a contact hole to expose a conductive region associated with the second gate structure; and forming an oxide film over a surface of the interlayer insulation film and over a surface of the contact hole using ozone.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     The present invention relates to a method of manufacturing semiconductor devices, and more particularly, to a method of manufacturing semiconductor devices, in which an interlayer insulation film is etched to form a contact.  
         [0002]     As the level of integration of semiconductor devices is increased, an interlayer insulation film for insulating a lower structure, e.g., a lower cell or a transistor, and an upper wiring structure is formed using O 3 -TEOS having a better gap-fill characteristic than that of an existing Chemical Vapor Deposition (CVD) method. The interlayer insulation film formed of O 3 -TEOS is densified by a subsequent annealing process.  
         [0003]     The densification by the anneal process, however, becomes less toward the bottom of the interlayer insulation film. Therefore, in the process of etching the interlayer insulation film to form the contact, a portion of the interlayer insulation film, which has not been densified, at the bottom of the interlayer insulation film is exposed and is therefore lost during a cleaning process to remove the etch remnants, resulting in a contact hole whose lower side is wider than its upper side is formed. A subsequent plug material may not completely fill into the contact hole.  
       BRIEF SUMMARY OF THE INVENTION  
       [0004]     An emobodiment of the present invention provides a method of manufacturing semiconductor devices, in which the bottom of an interlayer insulation formed of O 3 -TEOS can be prevented from being removed during a cleaning process when the interlayer insulation film is etched to form a contact.  
         [0005]     A method of manufacturing semiconductor devices according to the present invention includes the steps of forming an interlayer insulation film using O 3 -TEOS on a semiconductor substrate having a predetermined structure formed therein, performing an anneal process to densify the interlayer insulation film, etching a predetermined region of the interlayer insulation film to form a contact through which a predetermined region of the semiconductor substrate is exposed, and forming an oxide film on a surface of the interlayer insulation film performing a surface process using ozone.  
         [0006]     A method of manufacturing semiconductor devices according to the present invention includes the steps of forming a first interlayer insulation film using O 3 -TEOS on a semiconductor substrate having a predetermined structure formed therein, performing an anneal process to densify the first interlayer insulation film, forming a second interlayer insulation film on the first interlayer insulation film, etching predetermined regions of the first and second interlayer insulation films to form a contact through which a predetermined region of the semiconductor substrate is exposed, and forming an oxide film on a surface of the first and second interlayer insulation films by performing a surface process using ozone.  
         [0007]     The anneal process may be performed at a temperature of 700 to 900° C. in nitrogen (N 2 ) ambient for 30 to 60 minutes. The surface process using ozone may be performed at a temperature of 500 to 700° C. The oxide film may be formed to a thickness of 30 to 50 Å. The method may further include the step of performing a cleaning process of removing etch remnants when the contact is formed after the surface process using ozone is performed. The cleaning process may be performed using chemicals including one or more of the following: H 2 SO 4 , H 2 O 2 , NH 4 OH, HF and NH 4 F. The second interlayer insulation film may be formed using a tetraethoxysilane (TEOS) oxide film or a High Density Plasma (HDP) oxide film. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]      FIGS. 1   a  to  1   c  are sectional views of semiconductor devices for illustrating a method of manufacturing the semiconductor devices according to an embodiment of the present invention; and  
         [0009]      FIGS. 2   a  to  2   c  are sectional views of semiconductor devices for illustrating a method of manufacturing the semiconductor devices according to another embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0010]     The present invention will now be described in connection with preferred embodiments with reference to the accompanying drawings.  
         [0011]      FIGS. 1   a  to  1   c  are sectional views of semiconductor devices for illustrating a method of manufacturing the semiconductor devices according to an embodiment of the present invention.  FIG. 1  is a sectional view for illustrating a method of forming a drain contact of a NAND flash memory device. This method can be applied to a source contact in the same manner.  
         [0012]     Referring to  FIG. 1   a , a tunnel oxide film  102 , a first conduction layer  103 , a dielectric film  104 , a second conduction layer  105  and a hard mask film  106  are sequentially formed on a semiconductor substrate  101  in which a cell region A, a select transistor region B and a peripheral region C are partitioned by a predetermined process. Photolithography and etch processes using a predetermined mask is then performed to form a stack gate  100  in which a floating gate and a control gate are stacked in the cell region A and a gate  200  in which first and second conduction layers  103 ,  105  are stacked in the select transistor region B. A gate  300  in which first and second conduction layers  103 ,  105  are stacked is also formed in the peripheral region C.  
         [0013]     The stack gate  100  of the cell region A, the gate  200  of the select transistor region B and the gate  300  of the peripheral region C are formed by the same process in the present embodiment, but are used differently as a memory cell or control transistors. In other words, a first voltage is applied to the control gate in the stack gate  100  of the cell region A, so that the stack gate operates as a memory cell. A second voltage is applied to the first and second conduction layers  103 ,  105  of the gate  200  and the gate  300 , so that the gate  200  and the gate  300  operate as the control transistors. In another embodiment, the gates  200  and  310  are applied with different voltages.  
         [0014]     An insulation film  107  is formed and then undergoes blanket etch to be provided between the gates  100  of the cell region A. Spacers are formed on sidewalls of the gates  200 ,  300  of the select transistor region B and the peripheral region C. An ion implant process is then performed to form a source region (not shown) and a drain region  108 . A buffer oxide film  109  and a nitride film  110  for a self-aligned contact etch process are then formed on the entire structure.  
         [0015]     Referring to  FIG. 1   b , an interlayer insulation film  111  is formed of O 3 -TEOS on the entire structure. An anneal process is performed at a temperature of 700 to 900° C. under a nitrogen (N 2 ) atmosphere for 30 to 60 minutes in order to densify or harden the interlayer insulation film  111 . After a photoresist film (not shown) is formed on the entire structure, a drain contact hole  112  is formed to expose the drain  108 . The contact hole  112  is formed by a photolithography process.  
         [0016]     Referring to  FIG. 1   c , the photoresist film (not shown) is removed using plasma generated from oxygen. A surface process using ozone is then performed to form an oxide film  113  on a surface of the interlayer insulation film  111 . The surface process using ozone is performed at a temperature of 500 to 700° C., so that the oxide film  113  is formed to a thickness of 30 to 50 Å. A cleaning process is carried out to remove polymer residue remaining on the substrate after the photoresist film has been removed. The cleaning process is performed using chemicals including one or more of the following: H 2 SO 4 , H 2 O 2 , NH 4 OH, HF and NH 4 F. The oxide film  113  prevents the bottom of the interlayer insulation film  111 , that may not have been sufficiently hardened, from being removed. As a result, a plug material may completely filled into the contact hole  112  more easily.  
         [0017]      FIGS. 2   a  to  2   c  are sectional views of semiconductor devices for illustrating a method of manufacturing the semiconductor devices according to another embodiment of the present invention.  FIG. 2  is a sectional view for illustrating a method of forming a drain contact of a NAND flash memory device. This method can be applied to a source contact in the same manner.  
         [0018]     Referring to  FIG. 2   a , a tunnel oxide film  202 , a first conduction layer  203 , a dielectric film  204 , a second conduction layer  205  and a hard mask film  106  are sequentially formed on a semiconductor substrate  201  in which a cell region A, a select transistor region B and a peripheral region C are partitioned by a predetermined process. Photolithography and etch processes using a predetermined mask is then performed to form-stack gates  100  in which a floating gate  203  and a control gate  205  are stacked in the cell region A. A gate  200  in which first and second conduction layers  203 ,  205  are stacked in the select transistor region B is formed. A gate  300  in which first and second conduction layers  203 ,  205  are stacked is formed in the peripheral region C.  
         [0019]     The stack gate  100  of the cell region A, the gate  200  of the select transistor region B and the gate  300  of the peripheral region C are formed by the same process, but are used for different purposes. In other words, a first voltage is applied to the control gate in the stack gate  100 , so that the stack gate operates as a memory cell to store data. A second voltage is applied to both the first and second conduction layers  203 ,  205  of the gate  200  to use them as part of a control transistor. Similarly, the gate  300  is used as a control transistor. A third voltage is applied to both of the layers  203 ,  205  of the gate  300 . The second and third voltages may be different or the same.  
         [0020]     An insulating film is provided between gates  100  of the cell region A. After spacers  207  are formed on sidewalls of the gates  200 ,  300 , an ion implant process is performed to form a source region (not shown) and a drain region  208 . A buffer oxide film  209  and a nitride film  210  for a self-aligned contact etch process are then formed on the entire structure.  
         [0021]     Referring to  FIG. 2   b , a first interlayer insulation film  211  is formed of O 3 -TEOS (tetraethoxysilane) on the entire structure. An anneal process is performed at a temperature of 700 to 900° C. in nitrogen (N 2 ) ambient for 30 to 60 minutes in order to densify the first interlayer insulation film  211 . A second interlayer insulation film  212  is then formed on the first interlayer insulation film  211 . The film  212  may be formed of a TEOS oxide film or a High Density Plasma (HDP) oxide film. After a photoresist film (not shown) is formed on the entire structure, a drain contact hole  213  is formed by a photolithography process to expose the drain  208 .  
         [0022]     Referring to  FIG. 2   c , the photoresist film (not shown) is removed using plasma generated from oxygen. A surface process using ozone is then performed to form an oxide film  214  on surfaces of the first and second interlayer insulation films  211 ,  212 . The oxide film  214  lines or coats the contact hole  203 . The surface process using ozone can be performed at a temperature of 500 to 700° C. so that the oxide film  214  is formed to a thickness of 30 to 50 Å. A cleaning process is carried out to remove polymer residue remaining on the substrate after the photoresist film has been removed. The cleaning process is performed using one or more of the following chemicals: H 2 SO 4 , H 2 O 2 , NH 4 OH, HF and NH 4 F. Since the first interlayer insulation film  211  can be removed faster than the second interlayer insulation film  212  during the cleaning step, the bottom of the first interlayer insulation film  211  may be removed too much. This would result in a trench or hole that has a wider lower portion, which would result in difficulty in filling the trench or hole. The oxide film  214  helps with this problem by lining the trench or hole. Also, the film  214  helps in preventing excessive removal of the lower part of the first insulation film  211  that results from the lower part not being sufficiently hardened during the annealing.  
         [0023]     As described above, according to the present invention, since a bottom of an interlayer insulation film formed of O 3 -TEOS may not have hardened sufficiently, the lower part of the trench/contact hole may be removed too much during a cleaning process. An oxide film formed by a surface process using ozone is formed or coated on the surface of the trenches to prevent excessive loss of material at the lower part of the trench. Therefore, the present invention helps in preventing voids that may result when the trench is not completely filled with a plug material.  
         [0024]     Although the foregoing description has been made with reference to the preferred embodiments, it is to be understood that changes and modifications of the above embodiments may be made by the ordinary skilled in the art without departing from the spirit and scope of the present invention.