Abstract:
A method of forming contacts for an interconnection element, includes (a) joining a conductive element to an interconnection element having multiple wiring layers, (b) patterning the conductive element to form conductive pins, and (c) electrically interconnecting the conductive pins with conductive features of the interconnection element. A multiple wiring layer interconnection element having an exposed pin interface, includes an interconnection element having multiple wiring layers separated by at least one dielectric layer, the wiring layers including a plurality of conductive features exposed at a first face of the interconnection element, a plurality of conductive pins protruding in a direction away from the first face, and metal features electrically interconnecting the conductive features with the conductive pins.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    The present invention relates generally to interconnecting microelectronic devices and supporting interconnection elements, especially multilayer wiring elements. 
         [0002]    In the flip-chip mounting technique, the front or contact-bearing surface of a microelectronic device is mounted face-down to an interconnection element such as a chip carrier or other interconnection element, e.g., substrate. Each contact on the device is joined by a solder bond to the corresponding contact pad on the substrate, as by positioning solder balls on the substrate or device, juxtaposing the device with the substrate in the front-face-down orientation and momentarily reflowing the solder. The flip-chip technique yields a compact assembly, which occupies an area of the substrate no larger than the area of the chip itself. 
         [0003]    However, thermal stress presents significant challenges to the design of flip-chip assemblies. The solder bonds between the device contacts and the supporting substrate are substantially rigid. Changes in the relative sizes of the device and the supporting substrate due to thermal expansion and contraction in service create substantial stresses in these rigid bonds, which in turn can lead to fatigue failure of the bonds. Moreover, it is difficult to test the chip before attaching it to the substrate, and hence difficult to maintain the required outgoing quality level in the finished assembly, particularly where the assembly includes numerous chips. 
         [0004]    As the number of interconnections per microelectronic device increases, the issue of interconnection planarity continues to grow as well. If the interconnections are not planar with respect to each other, it is likely that many of the interconnections will not electrically contact their juxtaposed contact pads on a supporting substrate, such as a standard printed wiring board. Therefore, a method of making coplanar pins on existing multilayer interconnection elements is desired. 
       SUMMARY OF THE INVENTION 
       [0005]    In an embodiment of the present invention, a method of forming contacts for an interconnection element, includes (a) joining a conductive element to an interconnection element having multiple wiring layers, (b) patterning the conductive element to form conductive pins, and (c) electrically interconnecting the conductive pins with conductive features of the interconnection element. 
         [0006]    In another embodiment of the present invention, a multiple wiring layer interconnection element having an exposed pin interface, includes an interconnection element having multiple wiring layers separated by at least one dielectric layer, the wiring layers including a plurality of conductive features exposed at a first face of the interconnection element, a plurality of conductive pins protruding in a direction away from the first face, and metal features electrically interconnecting the conductive features with the conductive pins. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]      FIGS. 1A-1E  illustrate an embodiment of a method of assembling an electronic interconnect of the present invention. 
           [0008]      FIGS. 2A-2E  illustrate another embodiment of a method of assembling an electronic interconnect of the present invention. 
           [0009]      FIG. 3  schematically illustrates a side view of microelectronic pins. 
           [0010]      FIG. 4  schematically illustrates a top view of microelectronic pins. 
           [0011]      FIGS. 5A-5B  schematically illustrate a side view of microelectronic pins. 
           [0012]      FIGS. 6A-6E  illustrate another embodiment of a method of assembling an electronic interconnect of the present invention. 
           [0013]      FIGS. 7A-7C  illustrate an embodiment of an assembly of the invention joined to other electronic structures. 
       
    
    
     DETAILED DESCRIPTION 
       [0014]    A method of making coplanar pins on existing multilayer interconnection elements is herein described. A multilayer interconnection element  10  is shown in  FIG. 1 , having dielectric portions  12  and conductive portions  14 . The conductive portions may be in the form of wires, bond pads or the like. 
         [0015]    The multilayer interconnection element  10  may be formed of a single metal substrate or a multilayer substrate with dielectric such as polyimide, ceramic, FR4, BT resin and the like. The multilayer interconnection element  10  may also be an interconnection element with multiple wiring layers or the like. Reference is also made to U.S. Pat. No. 6,528,784 which discusses the manufacture of a multilayer interconnection element, which is hereby incorporated by reference. 
         [0016]    In one embodiment of the present invention, a metallic layer  16  is laminated onto the multilayer interconnection element  10  using an adhesive  18  as illustrated in  FIG. 1B . The metallic layer  16  may be any suitable metal as known in the art. For example, the metal may be any conductive metal, such as copper. Thereafter, the metallic layer  16  may be used to form microelectronic contacts or pins  20  as shown in  FIG. 1C . 
         [0017]    The microelectronic pins  20  may be formed as known in the art. For example, the microelectronic pins  20  may be formed by photolithographically patterning a resist layer on metallic layer  16  and transferring the resist patterns to the metallic layer  16  by etching. 
         [0018]    Once the microelectronic pins  20  are formed, where the adhesive layer  18  acts as an etch stop layer, the adhesive  18  may have portions removed from it to permit electrical connections to be formed between the microelectronic pins  20  and the conductive portions  14  of the multilayer interconnection element  10 , as shown in  FIG. 1D . The adhesive  18  may be selectively removed using photolithographic techniques or the like, as known in the art. 
         [0019]    Then, as shown in  FIG. 1E , electrical connections  22  are formed adjacent the portions removed from the adhesive  18 . For example, sputtering, also known as physical vapor deposition, or electroless plating may be followed by photolithographic patterning or laser drilling to define locations of the connections. Once the electrical connections  22  have been formed, they may be electroplated to increase their thickness to an amount desired. This then results in electrical connections  22  being formed between the multilayer interconnection element  10  and the microelectronic pins  20 . Lastly, a protective dielectric layer or film  24  ( FIG. 1E ) may be deposited onto the multilayer interconnection element  10  covering the electrical connections  22  and lower portions of the microelectronic pins  20  to form the assembly  50  is not damaged. This protective layer  24  can also assist in maintaining co-planarity of the top surfaces  40  of the microelectronic pins  20  because the dielectric protective layer  24  reduces flexure when the assembly  50  is handled because it holds the pins  20  in a stiff fashion. Example protective layer materials include a solder mask or the like. 
         [0020]    In another embodiment of the present invention, a multilayer interconnection element  10  is illustrated as shown in  FIG. 2A . Thereafter, as shown in  FIG. 2B , a layered metallic structure  26  is joined to the multilayer interconnection element  10  using an adhesive  18 . The layered metallic structure  26  may include a first metallic layer  28 , an etch stop layer  30  and a second metallic layer  32 . The first metallic layer  28 , preferably, has a greater thickness than the second metallic layer  32 . Although a trimetal structure is illustrated, the layered metallic structure  26  may include any number of layers. 
         [0021]    Microelectronic pins  20  may be formed from the first metallic layer  28 , as shown in  FIG. 2C  using techniques such as photolithographic patterning, or the like. However, the etch-stop layer remains. 
         [0022]    A method of fabricating the pins  20  will now be described with reference to the following figures. As shown in  FIG. 3 , a plurality of conductive pins  200  are formed to protrude above a surface of a continuous metal wiring layer  210 . The pins  200  can be formed by a variety of different processes. Exemplary processes are described in U.S. Pat. No. 6,884,709, as well as in the U.S. Provisional Application entitled, “Chip Capacitor Embedded PWB” having Ser. No. 60/875,730 and a file date of Jan. 11, 2007, the disclosures of which are incorporated by reference herein. 
         [0023]    In one such process, an exposed metal layer of a multi-layer metal structure is etched in accordance with a photolithographically patterned photoresist layer to form pins  200 , the etching process stopping on an interior metal layer  220  of the structure. The interior metal layer  220  includes one or more metals different from that of the exposed metal layer, the interior metal layer  220  being of such composition that it is not attacked by the etchant used to etch the exposed metal layer. For example, the metal layer from which the pins  200  are etched can consist essentially of copper, the continuous metal layer  210  can also consist essentially of copper, and the interior metal layer  220  can consist essentially of nickel. Nickel provides good selectivity relative to copper to avoid the nickel layer from being attacked when the metal layer is etched to form pins  200 . 
         [0024]    After forming the pins  200 , a different etchant is then applied to remove the exposed interior metal layer  220  by a process which is selective to the underlying metal layer  210 . Alternatively, another way that the pins  200  can be formed is by electroplating, in which pins are formed by plating a metal onto a base metal layer  210  through openings patterned in a dielectric layer such as a photoresist layer. 
         [0025]    As indicated in plan view in  FIG. 4 , the pins can have a variety of different shapes and sizes. For example, when viewed from the top, the pins can have a shape which is circular  300 , square or rectangular  310 , or oval shape  320 . When pins have a star shape, it may allow them to compress more easily or less easily than when other shapes are used. The height of the pins  200  above the plane of the underlying metal layer typically ranges between about 15 microns (μm) and about 250 microns (μm) and the width ranges for the tip of the pins is about 30 microns and above. 
         [0026]      FIGS. 5A and 5B  illustrate exemplary alternative structures that the pins can take. For example, as illustrated in  FIG. 5A , a pin  400  is formed by etching a first metal layer selective to an etch stop metal layer  420  which overlies a base metal layer  440 , the pin  400  being coated with a second metal layer  410 . The second metal layer can include the same metal as the first metal layer, one or more other metals, or a combination of a metal included in the first metal layer with another metal. In a particular embodiment, the second metal layer  410  includes a metal such as gold which is resistant to corrosion and which may also facilitate the formation of a diffusion bond between the second metal layer and a metal layer of another feature in contact therewith. In another particular embodiment, the second metal layer includes a low melting temperature metal such as tin or a low melting temperature metal alloy such as solder or a eutectic composition. Additional examples of one or more metals usable as a second metal layer include nickel, aluminum or nickel/gold. 
         [0027]    As illustrated in  FIG. 5B , only the tip of a conductive pin  450  may be coated with a second metal layer  460 , and the body of the conductive pin may contact the adhesive layer  470  directly, without an intervening etch stop layer. 
         [0028]    Thereafter, as shown in  FIG. 2D , portions of the etch stop layer  30 , the second metallic layer  32  and the adhesive  18  may be removed. The etch stop layer  30 , the second metallic layer  32  and the adhesive  18  may be removed either simultaneously or sequentially, as desired. Removal of these layers permits electrically connecting the microelectronic pins  20  with the conductive portions  14  of the multilayer interconnection element  10 , as stated herein. Lastly, a protective dielectric layer  24  such as described above ( FIG. 1E ) may then be deposited atop the completed structure. 
         [0029]    In yet another embodiment of the present invention, as illustrated in  FIGS. 6A-6E  a layered metallic structure  26  may be joined to a multilayer interconnection element  10  using an adhesive  18 . However, prior to this step, the second metallic layer  32  has portions removed therefrom, such that when the layered metallic structure  26  is attached to the multilayer interconnection element  10  using the adhesive, some of the adhesive may then rise into the removed portions of the second metallic layer  32 , as shown in  FIGS. 6B and 6C . Thus, the second metallic layer  32  may already be patterned prior to affixing the layered metallic structure  26  to the multilayer interconnection element  10 . 
         [0030]    Thereafter, microelectronic pins  20  are formed in a manner as stated previously. Next, portions of the etch stop layer  30  and the adhesive  18  are removed as shown in  FIG. 6D . Then, electrical connections  22  are formed which electrically connect the microelectronic pins  20  with the conductive portions  14  of the multilayer interconnection element  10 . Lastly, a protective layer  24  may be deposited to form the assembly  50 . 
         [0031]    The methods and structures described herein are advantageous for flip-chip mounting of a chip, having a land grid array (“LGA”) or ball grid array (“BGA”), to the exposed pin interface such as that shown in  FIG. 7A . A chip may also be mounted to the assembly  50  on a side opposite the microelectronic pins  20 , as shown in  FIG. 7B . Further, the methods and structures are also advantageous for flip chip or wire bond microcontacts as shown in  FIG. 7C . The finished assembly may be a circuit panel or may be a circuit panel joined to a chip. Further, the finished assembly may be meant for interconnection to another circuit panel or a chip. 
         [0032]    Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.