Abstract:
A gigabit ethernet line driver includes a transmitter having both transmitter and active hybrid outputs. The transmitter consists of a plurality of transmitter clusters each connected to both the transmitter and active hybrid outputs. Each transmitter cluster includes a plurality of transmitter cells consisting of a driver cell and digital to analog converter connected to driver cell. A hybrid circuit connects between the transmitter outputs and receiver inputs for separating a receiver signal from the transmitter signal responsive to a tuning signal. The hybrid circuit includes first and second resistor strings connected between the receiver inputs and the transmitter outputs, the first and second resistor strings each having many resistors with taps on each of the resistors; corresponding transistor switches connecting the taps of each of the first and second resistor strings to the hybrid inputs; and a circuit that selects a pair of the plurality of transistor switches connecting to a particular tap in response to the tuning signal such that a current to compensate for a transmitted signal is provided at the receiver inputs.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     This application is a continuation of United States Application for patent Ser. No. 10/299,273 filed Nov. 19, 2002, the disclosure of which is hereby incorporated by reference. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Technical Field of the Invention  
         [0003]     The present invention relates to ethernets, and more particularly, to gigabit ethernet line drivers.  
         [0004]     2. Description of the Related Art  
         [0005]     Ethernet standards 10BASE-T and 100BASE-TX have become dominant in Local Area Networks (LAN) applications due to the low cost and wide use of transmission media based on unshielded twisted pair cable (UTP). The development of these standards has resulted in an emerging 1000BASE-T standard, which provides a significantly higher data transmission rate. The higher transmission rate has been achieved not only by doubling the number of cables of the transmission lines, but by also implementing a full duplex transmission mode with multi-level signaling.  
         [0006]     Compared to the above-mentioned standards these features have dramatically changed the parameter requirements of the receiver and the transmitter. The multilevel signaling requires substantially more linear performance and lower noise generation from both the transmitter and the receiver. Full duplex operation requires an accurate hybrid to separate the received signal from the transmitted one at the input of the receiver. The hybrid output still contains some leftovers from the transmitted signal as well as additional signals reflected from different parts of the cable and cross talk signals coming from other cables. All these signals known as echoes are usually removed from the received signal by a DSP echo canceller incorporated in the receive path of the transceiver. The effective operation of the echo canceller depends on the level of non-linear distortions and noise generated in the analog portion of the transmit and receive path of the transceiver. Hence not only the hybrid should be added to the analog blocks used in the earlier standards, but the parameters of the existing blocks need to be substantially improved to be suitable for 1000BASE-T standard.  
         [0007]     One possible solution is presented in U.S. Pat. No. 6,259,745. The driver is made of a plurality of switchable current Digital-to-Analog converter (DAC) cells. In order to reduce the high frequency noise generated by the combination of the current switches and the parasitic inductance and capacitance of the chip package and the transformer, the driver output should be filtered. Because the driver produces a significant current, and the input impedance of the transformer connected to the transmission line together with the matching resistance is just a few tens of Ohms, the capacitance of the driver output filter must be very large and is not well suited for location in the transceiver chip. The hybrid is created as a smaller replica driver, which produces a current proportional to the current of the driver. The hybrid current is applied to a pair of resistors connected to the driver outputs. This partially cancels the transmitted signal voltage at the receiver input. In this architecture, the hybrid is controlled by the same digital input and clock used in the driver portion of the transceiver. To get a good compensation of the transmitted signal the hybrid output filter should be well matched with the output filter of the driver.  
         [0008]     A different solution is proposed by Roo, et al. “A CMOS Transceiver Analog Front-End fro Gigabit Ethernet Over CAT-5 Cables,” 2001 IEEE International Solid-State Circuit Conference, Session  19 , Digest of Technical Papers, page 310 (2001). In this driver, a DAC is coupled to the transformer through a current mirror with a substantial current gain. This enables the use of smaller filter capacitors on the DAC output. The active hybrid transistors have their gates connected to the same current mirror and better match the hybrid frequency response with the one of the driver. However, because of the nonlinear behavior of the MOS transistor transconductance, the charge accumulated at the filter capacitors together with the gate capacitors of the transistors introduces substantial distortions into the dynamic behavior of the transmitted signal. The trajectories of the driver output are not quite proportional for the signals of different amplitude. This can be considered as non-linear distortions. Although the gates of the hybrid transistors are connected to the gates of the driver transistors, the distortions of the transmitted signal leak into the receive path because of an imperfect match of the hybrid and driver. It creates a problem for a DSP echo canceller to remove this part of the echo. Because the canceller is usually a linear device, the distortions lift up the noise level and reduce the signal to noise ratio.  
         [0009]     To reduce the non-linear distortions in the driver, the driver output transistor transconductance linearity must be improved. It can be done by increasing the operating current and introducing degenerating resistors to the MOS transistors source nodes. This leads to substantial loss of the power efficiency of the driver. Thus, there is a need for a power efficient driver with low-level, non-linear distortions for 1000BASE-T application.  
       SUMMARY OF THE INVENTION  
       [0010]     In an embodiment of the invention, a circuit comprises: a transmitter having both transmitter and active hybrid outputs; a hybrid circuit connected between transmitter outputs and receiver inputs for separating a receiver signal from a transmitter signal responsive to a tuning signal; and a hybrid tuner for providing the tuning signal. The hybrid circuit comprises: first and second resistor strings connected between the receiver inputs and the transmitter outputs, the first and second resistor strings each comprising a plurality of resistors with taps on each of the resistors; a plurality of transistor switches connecting the taps of each of the first and second resistor strings to the hybrid inputs; and a circuit that selects a pair of the plurality of transistor switches connecting to a particular tap in response to the tuning signal such that a current to compensate for a transmitted signal is provided at the receiver inputs.  
         [0011]     In another embodiment, a circuit comprises: a hybrid circuit for connection to both transmitter outputs and active hybrid outputs for separating a receiver signal from a transmitted signal responsive to a tuning signal, and a hybrid tuner for providing the tuning signal. The hybrid circuit comprises: first and second resistor strings connected between receiver inputs and the transmitter outputs, the first and second resistor strings comprising a plurality of resistors; a plurality of transistor switches connecting the taps of each of the first and second resistor strings to the hybrid inputs; and a circuit that selects a pair of the plurality of transistor switches connecting to a particular tap in response to the tuning signal such that a current to compensate for a transmitted signal is provided at the receiver inputs.  
         [0012]     In another embodiment, a circuit comprises: a first analog differential input receiving a transmitter output signal; a second analog differential input receiving an active hybrid output signal; and an analog differential output. A hybrid circuit is coupled between the first and second analog differential inputs and the analog differential output. The hybrid circuit comprises: a first resistor string including a plurality of first taps and coupled between a positive node of the first analog differential input and a positive node of the analog differential output; a second resistor string including a plurality of second taps and coupled between a negative node of the first analog differential input and a negative node of the analog differential output; a plurality of first transistors, each first transistor coupling one of the first taps to a positive node of the second analog differential input; a plurality of second transistors, each second transistor coupling one of the second taps to a negative node of the second analog differential input; and a circuit for selectively activating one first transistor and one second transistor in response to a received hybrid tuning signal. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]     A more complete understanding of the system and method of the present invention may be obtained by reference to the following Detailed Description when taken in conjunction with the accompanying Drawings wherein:  
         [0014]      FIG. 1  is a block diagram of a driver and hybrid having true linearity according to the present invention;  
         [0015]      FIG. 2  is a block diagram of a transmitter decoder;  
         [0016]      FIG. 3  is a block diagram of a transmitter;  
         [0017]      FIG. 4  is a block diagram of a transmitter cell cluster used in 1000BASE-T 100BASE-TX, and 10BASE-T modes;  
         [0018]      FIG. 5  is a block diagram of a transmitter cell of a cluster as illustrated in  FIG. 4 ;  
         [0019]      FIG. 6  illustrates a 10BASE-T least significant bit transmitter cell;  
         [0020]      FIG. 7  illustrates a simplified basic circuit diagram of a current driver cell;  
         [0021]      FIG. 8  illustrates a first embodiment of a hybrid;  
         [0022]      FIG. 9  is a block diagram of a decoder for use with the hybrid of  FIG. 8 ;  
         [0023]      FIG. 10  illustrates a further embodiment of a hybrid;  
         [0024]      FIG. 11  is a block diagram of a hybrid tuning block;  
         [0025]      FIG. 12  is a block diagram of a reversible counter;  
         [0026]      FIG. 13  is a block diagram of an up/down counter cell;  
         [0027]      FIG. 14  is a block diagram of a delay line;  
         [0028]      FIG. 15  is a schematic of a comparator used with the first embodiment of the hybrid illustrated in  FIG. 8 ;  
         [0029]      FIG. 16  is a schematic diagram of a comparator used with the second embodiment of the hybrid illustrated in  FIG. 10 ; and  
         [0030]      FIG. 17  is a circuit diagram of a bias generator. 
     
    
     DETAILED DESCRIPTION  
       [0031]     Referring to the drawings and more particularly  FIG. 1 , there is illustrated a block diagram of a driver and hybrid with improved linearity according to the present invention. The device includes a decoder  10 , which converts input data bits  15 ,  20  into a temperature code used in the D/A converter of the transmitter  30 . Multi-phase clock  35  and sign representing bits  40  are directly connected to the transmitter  30 . The output of the transmitter  30  is connected to transformer  50 . The secondary coil of the transformer  50  is connected to a twisted pair cable  55 . The other end  60  of the twisted pair cable  55  is to connect to a similar transceiver (not shown). The outputs of the transmitter  30  are connected to active hybrid  65 , which separates the signal received from the cable  55  from the signal generated by the transmitter  30 . The hybrid  65  contains resistors tuned by the digital output  70  of hybrid tuner  75 . This is necessary because in a standard digital semiconductor CMOS process, the resistors usually do not have sufficient precision. The output of the hybrid tuner block  75  can be frozen by input  80  to avoid glitches in the hybrid  65  performance during the active transmit/receive mode. Bias generator  85  produces bias voltages for the other blocks or the driver. The bias generator  85  receives a stable reference voltage  90  from a band gap reference generator, which is not shown.  
         [0032]     The block-diagram of transmitter decoder  10  is shown in  FIG. 2 . The decoder  10  contains circuitry  220  for converting a three bit code B&lt;0:2&gt; into an eight bit thermometer code output OU&lt;2:9&gt; used by the most significant bit part of the transmitter  30 , and a 10BASE-T least significant bit decoder portion  222 , which just inverts the input bits B&lt;10:11&gt;. The decoder  10  generates the code, which controls only the absolute value of the signal transmitted by the transmitter  30 . The sign bits are applied to the transmitter  30  directly.  
         [0033]     The transmitter  30  block diagram is shown in  FIG. 3 . The transmitter  30  contains a plurality of transmitter clusters  100 ,  105 . Transmitter cluster  100  is active when the transmitter  30  is generating a positive output, and transmitter cluster  105  is active if the output is negative. The number of transmitter clusters  100 ,  105  is equal to the number of voltage steps generated by the transmitter  30  in a 1000BASE mode of operation. The transmitted clusters  100 ,  105  are organized in a unary type architecture to improve the linearity of the transmitted signal. All clusters are connected to the same hybrid output nodes  110 . The transmitter  30  also contains additional sets of least significant 10BASE-T driver cells  115 ,  120 . They are necessary to produce a smooth sine-like waveform required in this standard. All clusters  100 ,  105  and cells  115 ,  120  are connected to the same transmitter output nodes  125 .  
         [0034]     The block-diagram of a transmitter cell cluster  100 ,  105  used in 1000BASE-T and 100BASE-TX modes is shown in  FIG. 4 . The cluster  100 ,  105  contains three identical transmitter cells  117  receiving the same data bit  130 . The cells  117  are controlled by individual clock phases  135 . This is done to achieve the required 1000BASE-T standard wave shape. All cells  125  are connected to the same transmitter output nodes  125  and the same hybrid output node  110 .  
         [0035]     The block-diagram of a transmitter cell  117  of the cluster  100 ,  105  is shown in  FIG. 5 . The cell  117  contains Digital-to-Analog Converter (DAC) portion  150  and current mirror driver portion  155 . The DAC portion  150  consists of a DC current source  160  connected to the constant bias voltages PBIAS1 and PBIAS2, and current switch  165  controlled by D-latch  170 . Driver portion  155  of the cell  117  consists of two identical current mirror driver cells  180 . 10BASE-T least significant bit transmitter cell, shown in  FIG. 6 , is built in a similar way. This cell does not have hybrid outputs, which are not used in 10BASE-T standard. As well as this cell needs only a single clock phase used in 10BASE-T mode A simplified basic circuit diagram of current mirror driver cell  180  is shown in  FIG. 7 . The driver cell  180  has a current mirror architecture with current input  185  and two current outputs  190  and  195 . The cell  180  contains input current path  200  connected to current input  185 , hybrid current path  205  connected to output  190  and transmitter current path  210  connected to output  195 . The current gain of the transmitter portion of the mirror is substantially higher than one. Path  210  contains two portions:  210   a  is always active;  210   b  is enabled only in 10BASE-T mode by signal  215  to increase the current gain of the driver in this mode.  
         [0036]     The main difference of the transmitter  30  described from the one used in the first prior art example is that each individual transmitter cell  117  of the clusters  100 ,  105  contains a DAC  150  portion and a current mirror driver portion  155 , which in turn contains both driver and active hybrid current paths  205 ,  210 . The described structure enables the transmitted signal to be filtered at the driver input and save substantial chip area. Because the hybrid signal path  205  is controlled by exactly the same filtered input voltage as the driver path  210 , good high frequency hybrid-driver matching can be achieved.  
         [0037]     The difference from the second prior art example is each driver cell  180  still consists of a current mirror driver  155  with the driver path and hybrid replica path with inherent dynamic non-linear distortions, this does not affect the non-linear distortions of the transmitter-hybrid operation. This is because the trajectories of the transmitter output signal are the same in all the transmitter clusters. If it necessary to transmit a signal with higher amplitude, a larger number of identical transmitter clusters are involved. Thus, the trajectories are always proportional and are not dependent on the signal amplitude. The non-linear distortion of the transmitter and hybrid will be only determined by the accuracy of the identical transmitter clusters matching.  
         [0038]     One possible embodiment of the hybrid  65  is presented in  FIG. 8 . The hybrid  65  contains two resistor strings  225  and  230  connected between differential transmitters outputs and hybrid outputs connected to the receiver input. The taps of the resistor string  225 ,  230  are connected to the differential hybrid inputs (these inputs are connected to the hybrid output of the transmitter) through transistor switches  235 . Only one pair of the switches  235  can be simultaneously selected by decoder  240 . The input of the decoder  240  is generated by the hybrid tuning block  75  shown in  FIG. 11 . This block  75  chooses the switch  235  in such a way that the part of the resistor strings  225  and  230  located to the left from the chosen tap has a predetermined value of resistance. In this case, the current coming from the hybrid output of the transmitter  30  will provide the best compensation of the transmitted signal at the receiver input. The decoder block-diagram is shown in  FIG. 9 . It decodes a three bit input code into eight output signals.  
         [0039]     Another possible embodiment of the hybrid  65  is shown in  FIG. 10 . The hybrid  65  contains a pair of resistors  245  coupling the transmitter output with the receiver. In this embodiment instead of adjustable resistors, the value of the compensation current is adjustable. This is done by activating appropriate paths in current mirror slave transistors  250  and  255  receiving the bias voltage from master transistors  260  and  265  of the current mirror. The control bits ADJB&lt;0:2&gt; are generated to match the compensation gain of the current mirror to the actual value of the resistors  245 . Although the current mirror may introduce some dynamic distortions to the signal, the value is substantially smaller than the one that can be possibly produced by the current mirror driver. This is because the current mirror gain in this case is smaller than one. As well as due to small current consumption of the hybrid compared to driver, the operating current of the hybrid current mirror can be substantially increased without affecting the power efficiency.  
         [0040]     The hybrid tuner  75  block diagram is shown in  FIG. 11 . The hybrid tuner  75  contains comparator  275  and reversible counter  280 . The comparator  275  receives two input currents from the bias generator  85  ( FIG. 1 ). One current “CURREF” is temperature and is process independent. The other “CURRINT” is generated using a stable reference voltage and internal for the chip resistors. Thus, this current value is reverse proportional to the chip resistor&#39;s actual value. The comparator  275  receives the tuning bits ADJ&lt;0:2&gt; from the counter  280 . If the code of the bits corresponds to the best matching of the hybrid  65 , both outputs of the comparator are low. If the bits should be changed, the comparator  275  produces either “GOUP” or “GODOWN” for the counter  280  according to the direction for the code to be changed. The reversible counter  280  changes its output until the comparator  275  conditions are satisfied.  
         [0041]     The reversible counter  280  block diagram is shown in  FIG. 12 . The reversible counter  280  contains delay  285 , which together with NOR gate  290  composes a ring oscillator; RS-latch  295 , stores the direction of the count; and set of the counter cells  300 . If both signals “GOUP” and “GODOWN” are low, the ring oscillator  300  is disabled. The counter output in this case remains unchanged. If either of the inputs goes “HIGH”, the ring oscillator  300  is enabled. The clock cycles are counted either upward or downward until both inputs return to “LOW.” The block diagrams of the up/down counter cell  280  and delay line  285  are shown in  FIGS. 13 and 14  respectively.  
         [0042]     The schematic of the comparator  275  used for the first embodiment of the hybrid  65  ( FIG. 8 ) is shown in  FIG. 15 . The comparator  275  contains a replica of the hybrid resistor string  305  with switches  310  connected to the resistor taps. The switches  310  are controlled by a decoder  315  similar to decoder  240  ( FIG. 9 ). The selected switch applies a process independent current generated by current mirror  320  to the respective part of the resistor string  305 . A process dependent current generated by current mirror  335  is applied to resistor  315  to create a reference voltage drop across the resistor. Transconductor cell  330  converts the voltage difference between the reference resistor  315  and the resistor string  305  in its output current applied to the current comparator  342 . The limits of the comparator are set by current sources  340   a  and  340   b . If the transconductor current exceeds the limit, either “GOUP” or “GODOWN” goes “HIGH”.  
         [0043]     The schematic of the comparator  275  used for the second embodiment of the hybrid  65  ( FIG. 10 ) is shown in  FIG. 16 . The comparator  275  contains a replica  350  of a hybrid cell. The replica  350  (presents the slave side) and master transistor  355  composes a current mirror, which receives a reference process independent current “CURREF”. A process dependent current “CURRINT” is applied to the drain node of replica  350 . Tile current difference is applied to current comparator  360 , which was described above.  
         [0044]     The bias generator  85  circuit diagram is shown in  FIG. 17 . The bias generator  85  contains two similar portions: portion  400 , which is responsible for generation of the process independent reference voltages and currents; and portion  405  responsible for generation of the process dependent current. They contain external precise resistor  410 , connected to an n external pin of the chip, and internal process dependent resistor  415 . Each portion  400 ,  405  contains an operational amplifier  420  connected in a loop with a current source  425  and to the respective resistor  410 ,  415 . The loop maintains the voltage drop across the resistor  430  equal to the input reference voltage. Hence, the output currents of the portions  400 ,  405  are reverse proportional to the respective resistor values. At the same time portion  400  generates the bias voltages used by other blocks of the transceiver.  
         [0045]     The previous description is of a preferred embodiment for implementing the invention, and the scope of the invention should not necessarily be limited by this description. The scope of the present invention is instead defined by the following claims.