Abstract:
A display having variable resolution includes a plurality of discrete light emitting elements arranged in an array. Intervals between elements are quantized into a plurality of levels representing information to be displayed. Selected light emitting elements disposed about the levels are energized by a signal having a duty cycle varied in response to displayable information having a magnitude within a particular one of the plurality of levels.

Description:
BACKGROUND AND SUMMARY OF THE INVENTION 
     Visual displays in the form of arrays are useful in displaying quantized information in analog form. Typically an n element array quantizes a full-scale value V f  into n discrete values. If a j th  element is illuminated where j is less than or equal to n, a reading of j/n .sup.. V f  is signified. The resolution of this form of display is ±50% divided by n - 1 of the full-scale value. To increase the resolution of prior devices, it is necessary to increase the number n thereby requiring more elements. The invention is an improved display wherein resolution is increased without increasing the number of elements in the display. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a histogram display made in accordance with the invention having a single level of quantization between elements of the array. 
     FIG. 2 is a display made in accordance with the invention having four levels of quantization between elements of the array. 
     FIG. 3A is a block diagram of the preferred embodiment of a two-level quantizer made in accordance with the invention. 
     FIG. 3B is a coincidence select scan matrix illustrating the preferred manner of coupling the counters to display elements of an array. 
     FIG. 3C is a timing diagram illustrating the output of the DIVIDE BY TWO COUNTER shown in FIG. 3A for differing initial states of the DIVIDE BY TWO COUNTER. 
     FIG. 3D illustrates the output of the DIVIDE BY TWO counter shown in FIG. 3A for differing initial states with reference to the output of pulse source 2, stop signal 3 and reset 12. 
     FIG. 4 is a block diagram of a four level quantizer for use with the display of FIG. 2. 
     FIG. 5 illustrates the output 15 of the DIVIDE BY FOUR COUNTER 14 shown in FIG. 4 for differing initial states of COUNTER 14 with reference to reset signal 12, clock signal 13 and stop signal 3. 
     FIG. 6 is a block diagram of a quantizer producing a selected number of levels of quantization between elements. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIG. 1, there is shown a histogram display having a level of quantization halfway between elements k and k + 1. Assuming V f  is the full-scale value and referring to array drawing (a) of FIG. 1, a reading of k/n .sup.. v.sub. f is signified in the drawing by a shaded k element. The shaded k element in the figure represents a fully illuminated display element. For information corresponding to a quantization exactly halfway between elements k and k + 1, each element k and k + 1 is simultaneously illuminated with a 50% duty cycle as illustrated by cross hatched elements in Figure array drawing (b) of FIG. 1. The reading of FIG. 1b corresponds to a value equal to V f  /n .sup.. (k + 1/2). Referring to array drawing (c) of FIG. 1, there is shown a display corresponding to a value V f  /n .sup.. (k + 1). Array drawing (d) of FIG. 1 represents a bar graph version of a value corresponding to V f  /n .sup.. (k + 1/2). By allowing two elements to be illuminated in an apparent simultaneous manner to a viewer, an extra level of quantization exactly halfway between elements k and k + 1 is provided. 2n discrete levels of quantization is thereby provided with n display elements. This is a substantial improvement in read-out accuracy with no increase in n. 
     Referring to FIG. 2, there is shown a display made in accordance with the invention having 4 levels of quantization between elements of the array. Array drawing (a) of FIG. 2 corresponds to a reading of V f  /n .sup.. k. Array drawing (b) of FIG. 2 illustrates a k element having a 75% duty cycle and a k + 1 element having a 25% duty cycle corresponding to an indicated value of V f  /n .sup.. (k + 1/4). Array drawing (c) of FIG. 2 illustrates a k element and a k + 1 element each being illuminated with a 50% duty cycle and corresponding to a reading of V f  /n .sup.. (k + 1/2). Array drawing (d) of FIG. 2 illustrates a k element having a 25% duty cycle and a (k + 1) element having a 75% duty cycle corresponding to a reading of V f  /n .sup.. (k + 3/4). Array drawing (e) of FIG. 2 illustrates a k + 1 element having a 100% duty cycle corresponding to an indicated value of V f  /n .sup.. (k + 1). Array drawing (f) of FIG. 2 represents a bar graph version of array drawing (b) of FIG. 2 wherein elements 1 through k are driven with a duty cycle of 100% and the k + 1 element is driven with a duty cycle of 50% corresponding to an indicated value of V f  /n .sup.. (k + 1/4). The accuracy and resolution of the display shown in FIG. 2 is increased to a value of ±50% ÷ 4(n-of full-scale. An increase in resolution of four is achieved without increasing the number n of elements in the display. 
     The number of quantizations between elements can be increased to a selected number P. The accuracy of a general n element display with P quantized levels between elements has a read-out accuracy of ±50% divided by P .sup.. (n-1) of the full-scale value. Any desired accuracy is achieved with a proper choice of n ≧ 2 and P. For practical purposes the preferred embodiment uses P = 4 or other small integer and varies n to adjust to a desired full-scale accuracy. 
     Referring to FIG. 3A, there is shown a two level quantizer for driving a display 1. An A-D converter or other pulse source 2 in combination with an AND-gate 4 responsive to a stop signal 3, for example, produces a number of pulses proportional to a desired value to be displayed. Gate 4 applies pulses to a divide by 2 counter 6. Divide by 2 counter 6 applies its output to a first ring counter 8 of length I. 
     A ring counter of length I is easily implemented with cycle, digital logic in a manner shown, for example, by Richards in Digital Design, or the like. The first counter 8 drives elements of display 1 and drives a second ring counter 10 as shown in length J. A linear array of FIG. 1 is preferably driven in from a coincidence select matrix scan as shown, for example, in FIG. 3B wherein the elements of the linear array are designated, for example, as 1, 2, 3, through n where n = i .sup.. j and the coincidence select matrix is configured as shown in FIG. 3B. Upon the start of a measurement cycle, the first ring counter 8 of length I and the second ring counter 10 of length J are reset to their initial counting states by applying a reset signal 12 to counters 8 and 10. The function of these counters is to drive display 1 in the coincidence select matrix scan as depicted in FIG. 3b. Divide by 2 counter 6 is not reset. 
     Referring to FIG. 3c, the output 7 of counter 6 is in either of two states, low or high, as shown at points 7 and 7&#39; respectively in FIG. 3c. The numbers shown in FIG. 3c refer to corresponding element positions within the matrix of FIG. 3b. If counter 6 is in an initial low state, a first clock pulse of clock signal 13 causes the output 7 of counter 6 to go high. A second clock pulse causes it to go low. If a stop signal 3 is applied to gate 4 after an odd number of clock pulses, regardless of the initial counting state of counter 6, the output 7 of counter 6 is in a complement of its initial state. An odd number of k clock pulses, for example, results in a measurement cycle wherein the (k + 1)/2 element is lit with a 50% duty cycle. On the next measurement cycle, element [(k + 1)/2 + 1] is lit with a 50% duty cycle. To a viewer the resulting display appears to have both elements illuminated with equal brightness. 
     Referring to FIG. 3D, a timing diagram is shown wherein stop signal 3 occurs after an even number of clock pulses is produced by source 2. The numbers shown refer to corresponding element positions within the matrix of FIG. 3b. Regardless of the initial counting state of counter 6, counter 6 stops in its original counting state after an even number of pulses. The (k/2 + 1) element is illuminated on a 100% duty cycle if k even pulses pass before the stop signal 3. 
     The 2 level quantizer operation of FIGS. 3A-3D may be summarized as follows. For the following number of pulses passed by gate 4 before application of stop signal 3: 
     if K MOD 2 = 0 only element (k/2 + 1) with a 100% duty cycle is illuminated; 
     if k MOD 2 = 1 elements [(k + 1)/2 + 1]; and 
     [(k + 1)/2] are illuminated, each with a 50% duty cycle. 
     Referring to FIG. 4, a four level quantizer is shown. The quantizer is similar in structure to that described above except that counter 6 has been replaced with a divide by 4 counter 14. Referring to FIG. 4 and timing sequences D through G of FIG. 5, it is seen that regardless of the initial counting state of divide by 4 counter 14, the quantizer interpolates to four levels between elements of a display as shown in FIG. 2. Thus, if K clock pulses are passed before the stop signal: 
     for k MOD 4 =  0, only element (k/4 + 1) is illuminated and with a 100% duty cycle; 
     for k MOD 4 =  1, elements [(k + 3)/4] and [(k + 3)/4 + 1] are illuminated and with 75% and 25% duty cycles respectively; 
     for k MOD 4 =  2, elements [(k + 2)/4] and [(k + 2)/4 + 1] are illuminated, each with a 50% duty cycle; and 
     for k MOD 4 =  3, elements [(k + 1)/4] and [(k + 1)/4 + 1] are illuminated with 25% and 75% duty cycles respectively. 
     Referring to timing diagram C of FIG. 5 and a stop signal 3 occurring at times 40, 42, 44, and 46 is shown. Element 6 is illuminated for a stop signal 3 occurring at 40, elements 7, 6, 6, 6 for a stop signal 3 occurring at 42, elements 7 and 6 for a stop signal 3 occurring at 44, and elements 7, 7, 7, and 6 for a stop signal 3 occurring at 46 as illustrated in timing diagrams D through G of FIG. 5. 
     Referring to FIG. 6, there is shown a generalized quantizer providing a selected number of interpolation levels between elements, wherein the selected number of levels is symmetric or even. The quantizer is similar in structure to the quantizers discussed above with the difference being that counters 6 and 7 of the previously described embodiments have been replaced with a counter 9 which is a divide by P counter, P being an even number. Thus, if k clock pulses are passed before the stop signal: 
     for k MOD P = 0, only element [k/P + 1] is illuminated and with a 100% duty cycle; 
     for k MOD P = 1, elements [(k + P - 1)/P] and [(k + P - 1)/P + 1] are illuminated with 100(P-1)%/P and 100%/P duty cycles respectively; 
     for k MOD P = 2, elements [(k + P - 2)/P] and [(k + P - 2)/P + 1] are illuminated with 100(P-2)%/P and (2)100%/P duty cycles respectively; 
     for k MOD P = P/2, elements [(k + P - P/2)/P] and [(k + P - P/2)P + 1] are illuminated, each at 50% duty cycle; and 
     for k MOD P = P-1, elements [(k + P - (P - 1)/P] and [(k + P - (P - 1))/P + 1] are illuminated with 100[P-(P-1)]%/P and (P-1)100%/P duty cycles respectively. 
     Other preferred embodiments include a display wherein display elements vary their light absorption or light transmissibility or other optical characteristics in response to driving signals having varying duty cycles as described hereinabove. Acoustically tuned optical light filters positioned to receive light and disposed in an array and driven by acoustic generators coupled to counters 8 and 10, for example, is another preferred embodiment made in accordance with the invention.