Abstract:
The present invention relates to a signal transferring system. The signal transferring system includes a first and second layout paths, and a first and second circuits. Lengths of the first and second layout paths are different. The first and second circuits are used for transmitting and receiving at least two signals respectively. In addition, one of the first circuit and the second circuit includes a compensation circuit for adjusting transmission time of one of the at least two transferred signals or adjusting reception time of one of the at least two transferred signals such that the at least two transferred signals reach a second circuit through the first and the second layout paths at substantially the same time.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a signal transferring system and method thereof, and more particularly to a signal transferring system with unequal transferring paths and method thereof. 
   2. Description of the Prior Art 
   The constantly increasing system operating frequency of electronic apparatuses has resulted in many challenges when designing an interface between electronic apparatuses. For example, the input/output interface of a DDR SDRAM (Double Data Rate SDRAM) has to operate at a high speed (i.e. ≧100 MHz) clock, in which two data bits should be read in a single clock cycle. In other words, one data bit is read in the rising edge and the other data bit is read in the falling edge of the clock. Therefore, the reading time of one data bit is relatively short. Accordingly, the phases of the clock and data have to be locked precisely in order to read the data accurately. Furthermore, the input/output interface of the memory is required to utilize the pulse of a data strobe signal for sampling the 8 bits/16 bits data (DQ), therefore the layout lengths for the data signal and the relative data strobe signal on the circuit board have to be the same. Larger amounts of layout numbers, higher data transmitting speed, and more complicated operation of the circuit system will increase the difficulty of designing the circuit board. Furthermore, for the sake of equalizing the delay time of each layout path, the layout on the circuit board should be designed to have the shortest possible lengths and smallest possible area. The transmission line effect that emerges when operating at a high data speed will affect the normal operation of the electronic apparatus. Moreover, because the data of the DDR memory is transmitted at very high speeds, (8 bits/16 bits at a time), the power/ground bouncing noise that emerges at the input/output pad of the memory controller will seriously damage the signal accuracy of the analog circuit within the SoC (System on Chip) device, such as a digital to analog converter. 
   SUMMARY OF THE INVENTION 
   Therefore, one of the objectives of the present invention is to provide a signal transferring system with unequal transmission paths and a method thereof to solve the above-mentioned layout problems caused by the large amounts of layout numbers, high data transmitting speed, and complicated operation of the circuit system. 
   According to an embodiment of the present invention, a signal transferring system is provided. The signal transferring system comprises a first and second layout paths, a first and second circuits, wherein the first and second layout paths are coupled between the first circuit and the second circuit, and a length of the first layout path is different from a length of the second layout path. The first circuit is used for transmitting at least two transferred signals; and the second circuit is used for receiving the at least two transferred signals. One of the first circuit and the second circuit comprises a compensation circuit, wherein the compensation circuit is used for adjusting transmission time of one of the at least two transferred signals or adjusting reception time of one of the at least two transferred signals such that the at least two transferred signals reach a second circuit through the first and the second layout paths at substantially the same time. 
   According to another embodiment of the present invention, an apparatus for transferring at least two transferred signal system is provided. The apparatus comprises: a first terminal, a second terminal, an interface, and a compensation circuit. The first and second terminals are respectively coupled to a first and second layout paths for transferring the at least two transferred signal, wherein a length of the first layout path is different from that of the second layout path. The interface is coupled to the first and the second terminals for receiving or outputting the at least two transferred signals. The compensation circuit is coupled to the interface for adjusting transmission time of one of the at least two transferred signals or adjusting reception time of one of the at least two transferred signals such that the at least two transferred signals reach a second circuit through the first and the second layout paths at substantially the same time. 
   The first transmission path has a first length, for transmitting a first transmitting signal; and the second transmission path has a second length, for transmitting a second transmitting signal, the first length being different from the second length; and a transmitting circuit is coupled to the first transmission path and the second transmission path. The transmitting circuit comprises: a first buffer for driving the first transmitting signal to the first transmission path; and a second buffer for driving the second transmitting signal to the second transmission path; wherein the time when the first buffer drives the first transmitting signal and the time when the second buffer drives the second transmitting signal are not the same, thereby allowing the first transmitting signal and the second transmitting signal to reach a receiving circuit at substantially the same time. 
   According to another embodiment of the present invention, a method for transferring first and second transferred signals is provided. The method comprises: providing first and second terminals, respectively coupled to first and second layout paths, to transfer the first and second transferred signals, wherein a length of the first layout path is different from that of the second layout path; and adjusting transmission time of at least one of the first and second transferred signals or adjusting reception time of at least one of the first and second transferred signals by a compensation circuit such that the at least two transferred signals reach a second circuit through the first and the second layout paths at substantially the same time. 
   These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a diagram illustrating the signal transferring system according to a first embodiment of the present invention. 
       FIG. 2  is a diagram illustrating the signal transferring system according to a second embodiment of the present invention. 
       FIG. 3  is a flow chart of the signal transferring method according to the first embodiment of the present invention. 
       FIG. 4  is a flow chart of the signal transferring method according to the second embodiment of the present invention. 
   

   DETAILED DESCRIPTION 
   Please refer to  FIG. 1 .  FIG. 1  is a diagram illustrating a signal transferring system  100  according to an embodiment of the present invention. The transferring system  100  comprises a first transmission path  102 , a second transmission path  104 , a receiving circuit  106 , and a transmitting circuit  108 , wherein the receiving circuit  106  is coupled to the first transmission path  102  and the second transmission path  104 . In this embodiment, the first transmission path  102  has a first length L 1  for transmitting a first transmitting signal S 1 , the second transmission path  104  has a second length L 2  for transmitting a second transmitting signal S 2 , and the first length L 1  is smaller than the second length L 2 . Please note that, for brevity, there are only two transmission paths shown in  FIG. 1 ; however, this is not a limitation of the present invention. For example, when the receiving circuit  106  is a double data rate II (DDRII) memory, there will be 16 transmission paths coupled between the receiving circuit  106  and the transmitting circuit  108  (e.g., a memory controller of the DDR memory). 
   In  FIG. 1 , the receiving circuit  106  is coupled to the first and the second transmission paths  102 ,  104 , and receives the first and the second transmitting signals S 1 , S 2 . The transmitting circuit  108  comprises a transmission interface  1082 , a logic circuit  1084 , and a delay module  1086 . The transmission interface  1082  is coupled to the first and the second transmission paths  102 ,  104  for outputting the first and the second transmitting signals S 1 , S 2 . The logic circuit  1084  is utilized for generating a first output signal S 3  and a second output signal S 4 . The delay module  1086  is utilized for delaying at least one of the first and second output signals S 3 , S 4  by a first delay amount t 1  to generate the first and the second transmitting signals S 1 , S 2 , in which the first and the second transmitting signals S 1 , S 2  correspond to the first and second output signals S 3 , S 4  respectively. This is to ensure the first and the second transmitting signals S 1 , S 2  reach the receiving circuit  106  at substantially the same time. In this embodiment, the delay module  1086  comprises a first delay unit  1088  for providing the first delay amount t 1  (stored in a first register R 1 ) to delay the first output signal S 3  and then generate the first transmitting signal S 1 , and a second delay unit  1089  for providing a second delay amount t 2  (stored in a second register R 2 ) to delay the second output signal S 4  and then generate the second transmitting signal S 2 . In other words, the delay unit delays a transferred signal according to the delay amount stored in a corresponding register. 
   Furthermore, an enable control circuit  1090  generates a first enable clock CK 1  and a second enable clock CK 2  for respectively controlling the buffers  1092 ,  1094  of the transmission interface  1082 , and the buffers  1092 ,  1094  to drive the first and the second transmitting signals S 1 , S 2  into the first and the second transmission paths  102 ,  104  respectively. 
   Please note that the first delay amount t 1  and the second delay amount t 2  should be designed so the first and the second transmitting signals S 1 , S 2  reach the receiving circuit  106  at substantially the same time. Additionally, at least one of the first delay amount t 1  and the second delay amount t 2  is programmable/adjustable. In another embodiment, the second delay unit  1089  in  FIG. 1  can be eliminated, as long as the first and the second transmitting signals S 1 , S 2  can also reach the receiving circuit  106  at substantially the same time. 
   In this embodiment, the first transmission path  102  and the second transmission path  104  are the layout paths on the PCB board, and the receiving circuit  106  and the transmitting circuit  108  are installed on the PCB board; however this is not a limitation of the present invention. 
   The objective of the delay module  1086  is to calibrate the arriving times of the first and the second transmitting signals S 1 , S 2 , although those skilled in this art can easily modify the embodiment of the present invention to obtain the above-mentioned objectives. For example, setting the transmitting time of a specific transmission path as a reference time, then delaying the signals of the other transmission paths with corresponding delay amounts by the reference time for calibration also belongs to the scope of the present invention. 
   For example, if the transmitting times of the first and the second transmitting signals S 1 , S 2  on the first and the second transmission paths  102 ,  104  are t 5 , t 6  respectively, then the second delay unit  1089  in the delay module  1086  delays the second output signal S 4  of the second transmission path  104  having a longer length of L 2  by a shorter second delay amount t 2 ; and the first delay unit  1088  delays the first output signal S 3  of the first transmission path  102  having a shorter length of L 1  by a longer first delay amount t 1 . Please refer to  FIG. 1  again. The delayed first and second output signals S 3 , S 4  reach the transmission interface  1082  at different times (e.g. t 3  and t 4 ), wherein t 3 =t 0 +t 1 , t 4 =t 0 +t 2 . Simultaneously, the enable clock control circuit  1090  controls the first enable clock CK 1  and the second enable clock CK 2  to turn on the buffers  1092 , 1094  in the transmission interface  1082  at time t 3  and t 4 , respectively, and drive the first and the second output signal S 3 , S 4  into the first and the second transmission paths  102 ,  104  to become the first and the second transmitting signals S 1 , S 2  respectively. Because the first and the second transmission paths  102 ,  104  have different lengths of L 1  and L 2 , therefore the first and the second transmitting times t 5 , t 6  of the first and the second transmitting signals S 1 , S 2  on the first and the second transmission paths  102 ,  104  are different. However, if t 1 +t 5 =t 2 +t 6 , then the first and the second transmitting signals S 1 , S 2  will reach the receiving circuit  106  concurrently. In other words, the first and the second output signals S 3 , S 4  generated by the logic circuit  1084  will reach the receiving circuit  106  concurrently if t 1 +t 5 =t 2 +t 6 , even though the first and the second transmission paths  102 ,  104  have different lengths of L 1  and L 2 . In this embodiment, the combination of the enable clock control circuit  1090  and the delay module  1086  serves as a compensation circuit for adjusting transmission time of at least one of two transferred signals. 
   In other hand, the embodiment of the present invention not only reduces the layout area between the receiving circuit  106  and the transmitting circuit  108  but also discloses that the first enable clock CK 1  and the second enable clock CK 2  will activate the buffers  1092 ,  1094  in the transmission interface  1082  at different times (t 3  and t 4 ), meaning that the first and the second transmitting signals S 1 , S 2  are generated at different times in the transmission interface  1082 . Accordingly, the power/ground bouncing noise of each of the input/output pad (IO pad) of the transmission interface  1082  can be reduced. In other words, the noise generated by the embodiment of the present invention can be reduced. 
   Furthermore, the present invention can be applied in a receiving circuit. Please refer to  FIG. 2 .  FIG. 2  is a diagram illustrating a signal transmitting system  200  according to the second embodiment of the present invention. In this embodiment, the receiving module  206  comprises a transmission interface  2062  having buffers  2072  and  2074 , a receiving circuit  2064 , and a delay module  2066  having first and second delay units  2068  and  2069  and first and second registers R 1 ′ and R 2 ′ storing delay amounts t 1 ′ and t 2 ′ referenced by the first and second delay units  2068  and  2069 . Additionally, at least one of the first delay amount t 1 ′ and the second delay amount t 2 ′ is programmable/adjustable. In order to describe the present invention in more detail, a transmitting circuit  208  is further coupled to the first transmission path L 1 ′ and the second transmission path L 2 ′. The delay module  2066  has a similar configuration and operation to the delay module  1086  of  FIG. 1 ; and the enable clock control circuit  2070  has a similar configuration and operation to the enable clock control circuit  1090  of the  FIG. 1 , and details are therefore omitted here for brevity. It should be noted that the combination of the enable clock control circuit  2070  and the delay module  2066  serves as a compensation circuit for adjusting reception time of at least one of the transferred signals. 
   Please note that, in the above-mentioned first embodiment, only the transmitting circuit  108  has the delay module  1086  installed, and in the second embodiment, the delay module  2066  is installed on the receiving module  206 . However, in another embodiment, if a circuit device is designed to have the functions of transmitting and receiving, then the above-mentioned mechanism that calibrates the signal receiving time at the receiving circuit  106  and the mechanism that calibrates the signal receiving time at the logical circuit  1084  can be integrated into the circuit device. 
   Please refer to  FIG. 3 .  FIG. 3  is a flow chart of the signal transferring method according to a first embodiment of the present invention. Because the signal transferring method of the present invention is implemented by the signal transferring system  100  of  FIG. 1 , detailed description is omitted here for brevity. The objectives of step  310  to step  312  are to calibrate the receiving times of the first and second transmitting signals S 1 , S 2  at the receiving circuit  106  respectively. 
   Please refer to  FIG. 4 .  FIG. 4  is a flow chart of the signal transferring method according to a second embodiment of the present invention. Because the signal transferring method of the present invention is implemented by the signal transferring system  200  of  FIG. 2 , detailed description is omitted here for brevity. The objectives of step  412  to step  414  are to calibrate the receiving times of the first and second inputting signals S 3 ′, S 4 ′ at the receiving circuit  2064  respectively. The inputting signals S 3 ′, S 4 ′ respectively correspond to transmitting signals S 1 ′, S 2 ′ outputted from the transmitting circuit  208 . 
   Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.