Abstract:
An improved charge pump design useful in low power applications derives an alternative voltage from a supply voltage. The design can be constructed using PMOS manufactured according to standard processes such that triple well manufacturing processes are not required. The design can incorporate control gate circuitry to increase efficiency and decrease degradation due to the threshold voltage of the transistors used.

Description:
TECHNICAL FIELD 
       [0001]    This invention relates to electrical circuits. 
       BACKGROUND 
       [0002]    Charge pump circuits are used to provide a voltage that is higher than the voltage of a power supply or to reverse its polarity. Charge pumps are commonly used in memory devices, such as a flash memory and Electrically Erasable Programmable Read-Only Memory (EEPROM). Charge pump circuits are also used in other devices to increase dynamic range and simplify design. 
         [0003]    One common charge pump design is a Dickson charge pump.  FIG. 1  shows an example of a Dickson charge pump  100 . Each stage of the Dickson charge pump  100  is made of a capacitor and a n-channel metal-oxide-semiconductor field-effect (NMOS) transistor N 1 , N 2 , N 3 , N 4 , or N 5  acting as a diode. The transistors have their bulk connected to the ground. Each of the NMOS transistors N 2 , N 3 , N 4 , N 5  connects a drain terminal and gate terminal together to a stage capacitor C 1 , C 2 , C 3 , C 4 , respectively. As shown, the source terminals of the NMOS transistors N 1 , N 2 , N 3 , N 4  are connected to the stage capacitor of the next stage. Two inverted phase clock Φ and Φ′ are used. The maximum gain per stage is VDD-VT, where VT is the threshold voltage of the NMOS devices. 
         [0004]    As the supply voltage VDD decreases with advanced technologies, the pumping efficiency of such charge pump is decreased. Moreover, the body effect increases the threshold voltage of the NMOS devices. As the drop between the NMOS source and bulk increases, the number of stages that can be cascaded is limited. Another drawback of such structure is that thick oxide, high voltage transistors are necessary to sustain a large drop between the gate and the bulk in a reliable way. This prevents the design of such a circuit using thin oxide, low voltage standard devices that can sustain a maximum drop of VDD. 
       SUMMARY 
       [0005]    This specification describes technologies related to charge pump circuits. 
         [0006]    In general, one aspect of the subject matter described in this specification can be embodied in circuits that include a first and second half pump stages including p-type devices. In implementations, the half pump stages can be assembled to create a multi-stage charge pump device. The use of control gate phase inputs can increase gate voltages of transistors in the circuit to enhance a switching performance of the transistors by reducing degradation in performance due to a threshold voltage of the transistors. The design provides an efficient, low voltage, charge pump that can be constructed with standard components. 
     
    
     
       DESCRIPTION OF DRAWINGS 
         [0007]      FIG. 1  is a schematic diagram showing an example of a Dickson charge pump. 
           [0008]      FIG. 2  is a schematic diagram showing an example of a pump stage of a charge pump. 
           [0009]      FIG. 3  is a schematic diagram showing an example of a N-stage charge pump. 
           [0010]      FIG. 4  is a graph showing an example of phase inputs for the N-stage charge pump. 
           [0011]    Like reference symbols in the various drawings indicate like elements. 
       
    
    
     DETAILED DESCRIPTION 
       [0012]    Example Charge Pump Stage 
         [0013]    Low voltage p-type metal-oxide-semiconductor field-effect transistor (PMOS) devices can be used to realize transistor switches in charge pump circuits.  FIG. 2  shows an example of a charge pump stage  200  that includes PMOS switches P 1 , P 2 , P 3 , P 4 . In some examples, the charge pump stage  200  operates while maintaining a maximum voltage drop across any one transistor equal to or less than a supply voltage VDD. In some implementations, the charge pump stage  200  can operate with a low supply voltage. For example, VDD may be less than 1.2 V. 
         [0014]    The charge pump stage  200  includes two half pump stages  210   a ,  210   b . The half pump stage  210   a  includes the PMOS transistors P 1  and P 2 , and a control gate capacitor Cc 1 . The half pump stage  210   b  includes the PMOS transistors P 3  and P 4 , and a control gate capacitor Cc 2 . Cc 1  and Cc 2  can supply a boost voltage (e.g., 2 VDD) to the gate terminals of P 1  and P 3 , respectively. Using the boost voltage, P 1  and P 3  can mitigate gain degradation due to the threshold voltages of P 1  and P 3 . 
         [0015]    The charge pump stage  200  includes phase inputs Φ 1 , Φ 2 , and Φ 4 . In each phase of operation, the charge pump stage  200  receives a different combination of voltage inputs at the phase inputs Φ 1 , Φ 2 , and Φ 4 . Some example combinations are described below with reference to  FIG. 4 . In implementations, the phase inputs Φ 1 , Φ 2 , and Φ 4  can be coupled to an external device, such as a controller circuit. The controller circuit can determine voltage levels at various nodes (e.g., V 1 , V 2 , Vi, etc.) in the charge pump stage  200 . Based on the voltage level, the controller circuit can, for example, select a phase of operation and generate the input voltages corresponding to the selected phase of operation at the phase inputs Φ 1 , Φ 2 , and Φ 4 . In some examples, each of the phase inputs Φ 1 , Φ 2 , and Φ 4  are connected to a clock generator. For example, a clock generator can generate repetitive signals to the phase inputs Φ 1 , Φ 2 , and Φ 4  to operate the charge pump stage  200 . The charge pump stage  200  includes two transfer capacitors Ct and a capacitor Ci. Ci can be used to stabilize voltage at a node Vi. 
         [0016]    In operation, the charge pump stage  200  transfers charge from a node V 1  to a node V 2  based on the phase inputs Φ 1 , Φ 2 , and Φ 4 . As an illustrative example, the nodes V 1 , V 2 , Vc 1 , Vc 2 , and Vi may be initialized to VDD. In a first phase of operation, Φ 1  and Φ 4  are set to approximately VDD and Φ 2  is set substantially close to 0 V. Due to capacitor coupling at V 1 , the voltage at V 1  is set to VDD+ΔV. In some implementations, Ct has a high capacitance so that ΔV is substantially close to VDD. Similarly, the voltage at V 2  is set to VDD−ΔV due to capacitor coupling at V 2 . In some examples, the voltage at Vi is maintained at VDD in this phase. Therefore, a voltage drop on the drain-source of the PMOS transistors P 1 , P 2 , P 3 , P 4  can be maintained at or below VDD. Because the voltage drop is maintained at or below VDD, the PMOS transistors P 1 , P 2 , P 3 , and P 4  can be, in some examples, low voltage standard PMOS that are manufactured using thin oxide layers. In this phase, P 1  is turned on and a charge transfer occurs between Ct and Ci. After the charge transfer, the voltage at V 1  decreases to VDD+Vt, where Vt is a threshold voltage of the PMOS devices used. 
         [0017]    At this point, Φ 4  is set to 0 V and the charge pump stage  200  begins a second phase of operation. Due to capacitor coupling of Cc 1  and Cc 2 , the voltages at the nodes Vc 1  and Vc 2  are decreased to VDD−ΔV c1,2 . For example, a magnitude of ΔV c1,2  may depend on the capacitance of Cc 1  and Cc 2 . Because Vc 1  and Vc 2  are decreased, P 1  and P 3  are turned on. Therefore, a charge transfer occurs between the two Ct. In this phase, the gate-source voltage of P 1  and P 3  is around VDD to reduce degradation effects in the switching transistors P 1  and P 3  due to threshold voltages. 
         [0018]    Example Charge Pump 
         [0019]    Based on predetermined parameters, a number of charge pump stages  200  can be cascaded together to generate a desired output voltage. For example, a flash memory device may specify an output voltage of 11 V with an input voltage of 1 V. To meet the example voltage specification, ten charge pump stages  200  can be cascaded to generate a voltage close to 11 V (e.g., 10.88 V). 
         [0020]      FIG. 3  is a schematic diagram showing an example of a charge pump  300  having N charge pump stages  200 . In this example, the charge pump  300  receives supply voltage VDD and supplies output voltage at Vout. With N stages, the charge pump  300  can supply the output voltage at around (N+1)·VDD. The node Vout is coupled to a capacitor Cout in order to accumulate charges from previous stages. 
         [0021]    The charge pump  300  operates based on received voltages at phase inputs Φ 1 , Φ 2 , Φ 3 , and Φ 4 . As shown, each of the charge pump stages  200  includes the phase inputs Φ 1  and Φ 2 . Each of the charge pump stages  200  also includes the phase input Φ 3  or the phase input Φ 4 . In the depicted example, the charge pump stage  200  uses the phase input Φ 3  if the previous charge pump stage  200  uses the phase input Φ 4 . The charge pump stage  200  uses the phase input Φ 4  if the previous charge pump stage  200  uses the phase input Φ 3 .  FIG. 4  shows a graph  400  of example phase inputs Φ 1 , Φ 2 , Φ 3 , and Φ 4  used to operate the charge pump  300 . 
         [0022]    Example Phase Inputs 
         [0023]    As shown in  FIG. 4 , the phase inputs Φ 1 , Φ 2  are inverted phase clocks. In some implementations, the phase inputs Φ 1 , Φ 2  can have a fixed frequency controlled by a controller. The phases Φ 1 , Φ 2  can be generated by a clock circuit and an inverter circuit. The phase inputs Φ 3 , Φ 4  can be controlled by a controller or a feedback circuit to boost the gate voltages of P 1  and P 3  in the pump stages  200 . The phases Φ 3 , Φ 4  can also be supplied by clock circuits having predefined duty cycles and frequencies. 
         [0024]    By supplying a boosted voltage at the gate terminals of P 1  and P 3 , the charge pump  300  can avoid gain degradation and improve efficiency. Additionally, the charge pump  300  can be implemented using low voltage PMOS devices by limiting the voltage drop in the PMOS devices to be less than or equal to VDD. 
         [0025]    In some implementations, the charge pump stage  200  uses the same or substantially the same structure as a Dickson charge pump with advanced switches that allow for an efficient charge transfer principle and good parasitic effects. Using PMOS devices in the charge pump stage  200 , the charge pump  300  can be implemented using low voltage devices because the voltage drop in the transistors can be maintained at or below VDD. P 2  and P 4  can refresh the nodes Vc 1  and Vc 2 , respectively, in each clock cycle of the phase inputs Φ 1 , Φ 2 . 
         [0026]    Using standard devices, the cost for manufacturing the charge pump stage  200  is reduced as compared to alternative charge pump designs. For example, no triple well fabrication is required to manufacture the charge pump stage  200 . 
         [0027]    A number of implementations of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other implementations are within the scope of the following claims.