Abstract:
The present invention relates to a method for fabricating a semiconductor device with a landing plug contact structure. The method includes the steps of: forming a plurality of gate structures on a substrate; sequentially forming a first spacer and a second spacer on sidewalls of each gate structure; forming a plurality of landing plug contacts in a predetermined regions created between the gate structures; and forming a passivation layer on a resulting substrate structure including the first and the second spacers, the landing plug contacts and the gate structures. Particularly, the passivation layer which serves to prevent hydrogen ions from diffusing into a channel region is obtained by doping an N-type dopant capable of capturing hydrogen ions. The passivation layer is also obtained by forming a nitride layer capable of preventing the diffusion of hydrogen ions.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to a method for fabricating a semiconductor device; and, more particularly, to a method for a semiconductor device having a landing plug contact structure.  
       DESCRIPTION OF RELATED ARTS  
       [0002]     As a semiconductor device has been highly integrated, a distance between conductive structures has been conversely decreased, and as a result, a margin for a contact formation process has been also decreased. Therefore, a landing plug contact structure has been widely used to secure a sufficient contact process margin.  
         [0003]     A landing plug contact formation process is a technique for securing an overlay margin during a subsequent contact formation process by burying polysilicon precedently between gate structures in which a bit line contact and a storage node contact are formed.  
         [0004]      FIG. 1  is a cross-sectional view of a dynamic random access memory (DRAM) device in which a plurality of landing plug contacts are formed. Hereinafter, a conventional DRAM fabrication process will be described.  
         [0005]     As shown, a device isolation layer  11  is formed in a substrate  10 , thereby defining an active region, and a gate oxide layer  13  and a gate conductive material  14  including polysilicon and/or a metal are sequentially formed on the substrate  10 . A nitride layer  15  for forming a gate hard mask is then formed on the gate conductive material  14 .  
         [0006]     Subsequently, the nitride layer  15  is patterned by performing a photolithography process with use of a mask for use in a gate structure. The patterned nitride layer  15  is then used as an etch mask to pattern the gate conductive material  14  and the gate oxide layer  13 . From these sequential steps, a plurality of gate structures G are formed.  
         [0007]     Afterwards, an ion implantation of a low concentration for forming a source/drain junction is performed to exposed portions of the active region by using each gate structure G as an ion implantation mask. Then, a dual spacer S including a buffer oxide layer and a nitride layer is formed on sidewalls of each gate structure G. Herein, a first part of the spacer S based on the buffer oxide layer will be referred to as an oxide-based spacer denoted with a reference numeral  16 , while a second part of the spacer S based on the nitride layer will be referred to as a nitride-based spacer denoted with a reference numeral  17 . After the formation of the dual spacer S, another ion implantation of a high concentration is performed to form source/drain junctions  12 .  
         [0008]     An inter-layer insulation layer  18  is formed on the above resulting substrate structure and is then etched by employing a photolithography process with use of a T-shaped mask or an I-shaped mask both for forming a landing plug contact (LPC). Thereafter, a polysilicon layer for use in a LPC is formed on an entire surface of the above constructed substrate structure. A chemical mechanical polishing (CMP) process for planarizing the polysilicon layer is carried out until the patterned nitride layer  15  is exposed, thereby forming a plurality of LPCs  19 . Although not illustrated, another inter-layer insulation layer is formed on the planarized substrate structure, and a typical bit line formation process and a capacitor formation process are sequentially performed.  
         [0009]     Generally, nitride is used as a material for forming a spacer on sidewalls of a gate structure. However, because of stress generated from the nitride itself, there are problems such as a hot carrier effect in cell transistors and decrease in currents in a cell region. For these reasons, the buffer oxide layer is specifically employed as a spacer material in order to solve the above problems induced by the use of nitride.  
         [0010]     Meanwhile, high density plasma (HDP) oxide is commonly used as an inter-layer insulation material for providing an electrical insulation between a bit line and a gate electrode, i.e., a word line. However, this use of HDP oxide also causes a problem that hydrogen ions generated from a source gas used during depositing the HDP oxide layer diffuse into a channel region of a bottom part of a gate structure and deactivate a doped dopant, e.g., boron. If the dopant in the channel region becomes deactivated, a degree of decrement in threshold voltage (V t ) in a cell region varies locally depending on a degree of the deactivation. As a result of this variable descending threshold voltage, uniformity of the threshold D voltage is deteriorated, further causing problems that a transistor characteristic such as a punch-through breakdown voltage (Bvds) becomes degraded and saturation currents of a drain (I dsat ) decrease.  
         [0011]     Meanwhile, instead of using the HDP oxide, it is possible to apply another material for forming an inter-layer insulation layer. Since a source gas for depositing most of oxide materials contains hydrogen, it may be fundamentally difficult to prevent generation of hydrogen ions although there is a slight variation in degrees of the hydrogen ion generation.  
       SUMMARY OF THE INVENTION  
       [0012]     It is, therefore, an object of the present invention to provide a method for fabricating a semiconductor device capable of preventing hydrogen ions from diffusing into a channel region during formation of an inter-layer insulation layer proceeding after a landing plug contact formation process.  
         [0013]     In accordance with an aspect of the present invention, there is provided a method for fabricating a semiconductor device, including the steps of: forming a plurality of gate structures on a substrate; sequentially forming a first spacer and a second spacer on sidewalls of each gate structure; forming a plurality of landing plug contacts in a predetermined regions created between the gate structures; and forming a passivation layer on a resulting substrate structure including the first and the second spacers, the landing plug contacts, the gate structures and the substrate.  
         [0014]     In accordance with another aspect of the present invention, there is provided a method for fabricating a semiconductor device, including the steps of: forming a plurality of gate structures on a substrate; sequentially forming a first spacer and a second spacer on sidewalls of each gate structure; forming a plurality of landing plug contacts in a predetermined regions created between the gate structures; and doping an N-type dopant to a resulting substrate structure including the first and the second spacers, the landing plug contacts, the gate structures, and the substrate.  
         [0015]     In accordance with further another aspect of the present invention, there is provided a method for fabricating a semiconductor device, including the steps of: forming a plurality of gate structures on a substrate; sequentially forming a first spacer and a second spacer on sidewalls of each gate structure; forming a plurality of landing plug contacts in a predetermined regions created between the gate structures; and forming a capping nitride layer on a resulting substrate structure including the first and the second spacers, the landing plug contacts, the gate structures, and the substrate. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]     The above and other objects and features of the present invention will become better understood with respect to the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which:  
         [0017]      FIG. 1  is a cross-sectional view of a conventional dynamic random access memory (DRAM) device in which a plurality of landing plug contacts is formed;  
         [0018]      FIGS. 2A and 2B  are cross-sectional views illustrating a method for fabricating a DRAM device in accordance with a first embodiment of the present invention; and  
         [0019]      FIGS. 3A and 3B  are cross-sectional views illustrating a method for fabricating a DRAM device in accordance with a second embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0020]     A method for fabricating a semiconductor device having a landing plug contact structure in accordance with preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, which is set forth hereinafter.  
         [0021]      FIGS. 2A and 2B  are cross-sectional views illustrating a method for fabricating a dynamic random access memory (DRAM) device in accordance with a first embodiment of the present invention.  
         [0022]     Referring to  FIG. 2A , a device isolation layer  21  is formed in a substrate  20 , thereby defining an active region. A gate oxide layer  23  and a conductive material  24  including polysilicon and/or a metal for use in a gate structure are sequentially formed on the substrate  20 . A nitride layer  25  for forming a hard mask is formed on top of the conductive material  24 .  
         [0023]     Subsequently, the nitride layer  25  is patterned by performing a photolithography process with use of a mask for forming a gate structure. The patterned nitride layer  25  is then used as an etch mask to pattern the conductive material  24  and the gate oxide layer  23 . From these sequential steps, a plurality of gate structures G are formed.  
         [0024]     Next, an ion implantation of a low concentration for forming a source/drain junction is performed to exposed portions of the active region by using each gate structure G as an ion implantation mask. Afterwards, a dual spacer S including a buffer oxide layer and a nitride layer is formed on sidewalls of the gate structures G. Herein, a first part of the dual spacer S based on the buffer oxide layer will be referred to as an oxide-based spacer denoted with a reference numeral  26 , while a second part of the dual spacer S based on the nitride layer will be referred to as a nitride-based spacer denoted with a reference numeral  27 . Subsequent to the formation of the dual spacer S, another ion implantation of a high concentration is performed to form source/drain junctions  22 .  
         [0025]     After the serial ion implantation processes, an inter-layer insulation layer  28  is formed on the above constructed substrate structure and is then etched by employing a photolithography process using a T-shaped mask or an I-shaped mask for forming a landing plug contact (LPC). A polysilicon layer for use in a LPC is formed on an entire surface of the above resulting substrate structure and is then subjected to a chemical mechanical polishing (CMP) process for planarizing the above structure. Herein, the CMP process continues until the patterned nitride layer  25  is exposed, and from this CMP process, a plurality of LPCs  29  are formed.  
         [0026]     Referring to  FIG. 2B , a passivation layer  30  is formed by ion implanting a high concentration of an N-type dopant to an entire surface of the substrate structure. At this time, phosphorus (P) and arsenic (As) are examples of the N-type dopant. Also, it is preferable to apply implantation energy ranging from approximately 2 KeV to approximately 50 KeV and implantation dose ranging from approximately 1×10 15  ions/cm 2  to approximately 1×10 16  ions/cm 2 . Thereafter, although not illustrated, another inter-layer insulation layer is formed on the passivation layer  30 , and a typical bit line formation process and a capacitor formation process are carried out.  
         [0027]     In accordance with the first embodiment of the present invention, the passivation layer  30  doped with a high concentration of the N-type dopant capable of capturing hydrogen ions is formed on top of the oxide-based spacer  26  through which the hydrogen ions generated during the formation of said another inter-layer insulation layer diffuse. Because of the existence of the passivation layer  30 , it is possible to prevent hydrogen ions from diffusing into a channel region.  
         [0028]      FIGS. 3A and 3B  are cross-sectional views illustrating a method for fabricating a DRAM device in accordance with a second embodiment of the present invention.  
         [0029]     Referring to  FIG. 3A , a device isolation layer  41  is formed in a substrate  40 , thereby defining an active region. A gate oxide layer  43  and a conductive material  44  including polysilicon and/or a metal for use in a gate structure are sequentially formed on the above resulting substrate structure. A nitride layer  45  for forming a hard mask is formed on top of the conductive material  44 .  
         [0030]     Subsequently, the nitride layer  45  is patterned by performing a photolithography process with use of a mask for forming a gate structure. The patterned nitride layer  45  is then used as an etch mask to pattern the conductive material  44  and the gate oxide layer  43 . From these sequential steps, a plurality of gate structures G are formed.  
         [0031]     Next, an ion implantation of a low concentration for forming a source/drain junction is performed to exposed portions of the active region by using each gate structure G as an ion implantation mask. Then, a dual spacer S including a buffer oxide layer and a nitride layer is formed on sidewalls of the gate structures G. Herein, a first part of the dual spacer S based on the buffer oxide layer will be referred to as an oxide-based spacer denoted with a reference numeral  46 , while a second part of the dual spacer S based on the nitride layer will be referred to as a nitride-based spacer denoted with a reference numeral  47 . After the formation of the dual spacer S, another ion implantation of a high concentration is performed to form source/drain junctions  42 .  
         [0032]     Subsequent to the serial ion implantation processes, an inter-layer insulation layer  48  is formed on the above constructed substrate structure and is then etched by employing a photolithography process with use of a T-shaped mask or an I-shaped mask for forming a landing plug contact (LPC). A polysilicon layer for use in a LPC is formed on an entire surface of the above resulting substrate structure and is then subjected to a chemical mechanical polishing (CMP) process for planarizing the above substrate structure. Herein, the CMP process continues until the patterned nitride layer  45  is exposed, and from this CMP process, a plurality of LPCs  49  are formed.  
         [0033]     Referring to  FIG. 3B , a capping nitride layer  50  is deposited on the planarized substrate structure until a thickness of the capping nitride layer  50  ranges from approximately 50 Å to approximately 500 Å. At this time, the capping nitride layer  50  is preferably formed by employing a low pressure chemical vapor deposition (LPCVD) method or a plasma enhanced chemical vapor deposition (PECVD) method. However, in addition to this preferable use of the LPCVD method or the PECVD method, it is still possible to employ a nitridation method which makes a surface of the substrate  40  nitrided through a conventional nitridation process.  
         [0034]     Although not illustrated, another inter-layer insulation layer is formed on the capping nitride layer  50 , and a typical bit line formation process and a capacitor formation process are carried out.  
         [0035]     In accordance with the second embodiment, it is possible to prevent hydrogen ions from diffusing into a channel region since the capping nitride layer  50  capable of preventing diffusion of hydrogen ions is formed on the oxide-based spacer  46  through which the hydrogen ions generated during the formation of said another inter-layer insulation layer diffuse.  
         [0036]     Table 1 provided below shows various device characteristics obtained in cases of employing the conventional method, the first embodiment implemented under the condition of using a dopant of  31 P, implantation energy of approximately 20 KeV and implantation dose of approximately 5×10 15  ions/cm 2  and the second embodiment implemented by employing approximately 100 Å of the capping nitride layer.  
                                                         TABLE 1                           Conventional   First   Second           Method   embodiment   embodiment                                Threshold voltage   0.66   V   0.89   V   0.88   V       (V t )       in cell region       Saturation   29   μA   36   μA   34   μA       currents of drain       (I dsat )       punch-through   2.0   V   3.8   V   3.6   V       breakdown voltage       (Bvds)                  
 
         [0037]     As shown in Table 1, compared with the conventional method, those device characteristics such as the threshold voltage (V t ) in a cell region, the saturation currents of a drain (I dsat ) and a punch-through breakdown voltage (Bvds) are improved in the first embodiment and the second embodiment.  
         [0038]     Especially, in accordance with the first and the second embodiments, it is possible to prevent hydrogen ions generated during the formation of the inter-layer insulation layer performed after the LPC formation process from diffusing into a channel region. As a result of this effect, it is further possible to improve characteristics of a semiconductor device.  
         [0039]     Although the first and the second embodiments of the present invention exemplify the ion implantation of the N-type dopant, the first and the second embodiments of the present invention can be applied to a plasma treatment or a phosphine (PH 3 ) gas doping process which is a widely employed surface treatment technique in addition to the ion implantation process. Herein, in case of employing the plasma treatment, an N-type dopant containing gas can be used a plasma source.  
         [0040]     In addition, although the first and the second embodiments exemplify the DRAM fabrication process, these first and the second embodiments can be applied to other processes for fabricating a semiconductor device having a LPC structure.  
         [0041]     The present application contains subject matter related to the Korean patent application No. KR 2004-0047263, filed in the Korean Patent Office on Jun. 23, 2004, the entire contents of which being incorporated herein by reference.  
         [0042]     While the present invention has been described with respect to certain preferred embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.