Abstract:
A digital-to-analog convertor divides an input digital signal into a least significant bit group and a most significant bit group. The most significant bit group is converted using pulse amplitude modulation and the least significant bit group is converted using pulse width modulation, in which the pulse widths are varied symmetrically about predetermined time points within a conversion period in order to improve the linearity of the pulse width modulation conversion.

Description:
This is a continuation of application Ser. No. 06/663,147, filed 10-22-84, now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a digital-to-analog converting syste employed in various digital processing systems such as PCM (Pulse-Code Modulation) record players. More particularly, the invention concerns a digital-to-analog converting system, which can digital-to analog convert Pulse Amplitude Modulation (PAM) waves and Pulse Width Modulation (PWM) waves. 
     2. Description of the Prior art 
     Heretofore, digital-to-analog (D/A) converting systems, which can convert a digital signal with each bit having a fixed weight, e.g., simple binary codes and binarized decimal codes, into an analog signal, are well known in the art. These digital-to-analog converting systems include one, in which the digital signal noted above is converted to a PAM or PWM wave corresponding to digital data given by the weight of each bit and the PAM or PWM wave thus obtained is interpolated through a low-pass filter to obtain the analog signal. 
     With a D/A converting system which is based on a system of converting a digital signal to a PAM wave (hereinafter referred to as PAM system), principally a conversion characteristic having satisfactory linearity can be obtained. This D/A converting system, however, requires highly precise resistance adder and current adder accurately corresponding to the weight of each bit of the input digital signal. If the resolution is to be increased, therefore, increase of the circuit scale is inevitable, and also the entire circuit must be constructed with a high precision. With a D/A converting system which is based on a system of converting a digital signal to a PWM wave (hereinafter referred to as PWM system), the output pulse width may be controlled by a counter according to the input digital signal, so that the circuit construction that is required is simple. However, the conversion characteristic is principally non-linear and involves conversion errors. Also, it is necessary to increase the operation frequency of the counter according to the resolution. 
     FIG. 1 shows analog signals obtained through the PAM system conversion and analog signals obtained through the PWM system conversion. As is seen from the Figure, the PAM pulses and PWM pulses that are produced from digital signal by respective systems have equal areas. With the PWM pulses, with which the duty ratio with respect to the conversion period T varies, unlike the PAM pulses with which the duty ratio remains fixed, the linearity of analog signal that is obtained by smoothing the pulses through a predetermined low-pass filter is deteriorated. 
     More particularly, the digital-to-analog conversion characteristic of the PWM system is not linear but is gently curved as shown in FIG. 2. The non-linearity of the PWM system conversion characteristic varies according to the frequency of the analog signal obtained. The distortion due to the non-linearity is increased with increasing analog signal frequency and also with increasing maximum PWM wave pulse width in one conversion period T. 
     The distortion due to conversion in the PWM system noted above may be reduced by increasing the operation frequency of a counter that controls the pulse width of the PWM wave and thereby reducing the pulse width of the PWM wave representing one LSB of data. By reducing the pulse width of one LSB, however, the signal level of the analog signal that is obtained through interpolation of the PWM wave through a low-pass filter is reduced to reduce the ratio between the maximum output level and zero signal level, i.e., the dynamic range of signal. 
     In case where D/A conversion with a resolution of N bits is performed by the PWM system, the pulse width τ 0  representing one LSB of PWM pulses where the maximum pulse width is τ max  is given as ##EQU1## Where a 16-bit PCM audio D/A converter is employed, for instance, with a maximum pulse width τ max  of 10 μsec., i.e., approximately one-half of a sampling period of 22 μsec., the pulse width τ 0  representing one LSB has to be ##EQU2## In order to control the pulse width of the PWM pulses in this case with a counter, it is necessary to operate the counter at a clock frequency f CLK  of ##EQU3## However, even with an ordinary high speed counter based on ECL (Emitter-Coupled Logic), the practical upper limit of the operation frequency is of the order of 100 MHz. Therefore, it has been very difficult to realize a high resolution D/A converting system based on the PWM system. 
     When D/A conversion with a resolution of N bits is to be realized with a PAM system employing current adders, for instance, N current sources which are provided with highly precise weights are required for each bit. 
     SUMMARY OF THE INVENTION 
     There is provided a digital-to-analog converting system according to the present invention, in which N-bit input digital data is divided into at least n H  higher order bits and n L  lower order bits, the n H  higher order bit data are converted to Pulse Amplitude Modulation wave, the n L  lower order bit data are converted to Pulse Width Modulation wave, and the PAM and PWM waves thus obtained are added together in a timed relation to each other to obtain an output. 
     An object of the present invention is to provide a digital-to-analog converting system, which can solve the problems discussed above with a novel structure which makes effective use of the merits of both the PWM and PAM systems to obtain a high resolution of D/A conversion. 
     Another object of the present invention is to permit D/A conversion on the basis of the PWM system with a reduction of the operation frequency of the PWM wave pulse width control counter to a practical frequency. 
     A further object of the present invention is to improve the linearity of the D/A conversion characteristic by reducing the conversion error due to the PWM system, thereby ensuring a broad dynamic range and reducing the distortion of the analog signal to be obtained without deterioration of the distortion factor of the output analog signal. 
     The above-mentioned and other objects and features of the invention will become apparent from the following detailed description taken in conjunction with the drawings which indicate embodiments of the invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a waveform diagram showing PAM and PWM waves usually used for D/A conversion; 
     FIG. 2 is a graph showing conversion characteristics of D/A conversion using PAM and PWM waves, respectively; 
     FIG. 3 is a schematic representation of a first embodiment of the digital-to-analog converting system according to the present invention; 
     FIG. 4 is a schematic representation of an example of PWM control section employed in the same embodiment; 
     FIG. 5 is a time chart for explaining the operation of the same embodiment; 
     FIG. 6 is a waveform diagram showing an example of pulse widths of PAM wave representing one LSB of higher order n H  -bit data and PWM wave representing one LSB of the lower order nL-bit data; 
     FIG. 7 is a waveform diagram showing an example of PWM wave output obtained through additive combination of individual PWM waves in the same embodiment; 
     FIG. 8 is a characteristic graph showing the linearity of PWM wave in the same embodiment; 
     FIG. 9 is a graph showing an D/A conversion characteristic obtained with the same embodiment; 
     FIG. 10 is a schematic representation of a second embodiment of the digital-to-analog converting system according to the present invention; 
     FIG. 11 is a waveform diagram showing an example of pulse widths of PWM wave representing one LSB of higher order n l1  -bit data and PWM wave representing one LSB of lower order n l2  -bit data in the same embodiment; 
     FIG. 12 is a waveform diagram showing an example of PWM wave output obtained through additive combination of individual PWM waves in the same embodiment; 
     FIG. 13 is a schematic representation of a different example of PWM control section employed in the first embodiment; 
     FIG. 14 is a time chart illustrating the operation of the same example; 
     FIG. 15 is a characteristic graph showing the linearity of PWM wave obtained in the same example; 
     FIG. 16 is a schematic representation of a third embodiment of the digital-to-analog converting system according to the present invention; 
     FIG. 17 is a time chart for explaining the operation of the same embodiment; 
     FIG. 18 is a waveform diagram showing the PAM wave obtained through conversion of higher order n H  bit data in the same embodiment; 
     FIG. 19 is a waveform diagram showing an example of resultant pulses obtained through additive combination of PAM and PWM waves in the same embodiment; 
     FIG. 20 is a graph showing the D/A conversion characteristic obtained in the same embodiment; 
     FIG. 21 is a schematic representation of a fourth embodiment of the digital-to-analog converting system according to the present invention; 
     FIG. 22 is a time chart illustrating the operation of the same embodiment; 
     FIG. 23 is a waveform diagram showing the PWM wave obtained from a modulating section in the same embodiment; and 
     FIG. 24 is a graph showing the D/A conversion characteristic of the same embodiment. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Now, one embodiment of the digital-to-analog converting system according to the present invention will be described in detail. 
     A first embodiment of the present invention is shown in the block diagram of FIG. 3. N-bit serial data D IN  which is obtained through quantization of an analog signal for every sampling period T S , is supplied to a data input terminal 1. In this embodiment, 7-bit data is supplied as the serial data D IN  to the data input terminal 1. 
     This serial data DIN is supplied from the data input terminal 1 to a serial-to-parallel (S/P) converter 2 for conversion to parallel data D P . 
     The N-bit (i.e., 7-bit) parallel data D P  consisting of bits D 0  to D 6  obtained from the S/P converter 2, is divided into MSB side n H  -bit (i.e., 3-bit) data D H  consisting of higher order bits D 0  to D 2  with greater weights and LSB side n L  -bit (i.e., 4-bit) data D L  consisting of lower order bits D 3  to D 6  with smaller weights. The higher order n H  -bit data D H  is supplied to a PAM control section 3, while the lower order n L  -bit data D L  is supplied to a PWM control section 4. 
     In this embodiment, the PWM control section 4 is supplied with one-bit data D S  of logic level &#34;1&#34; supplied to a secondary data input terminal 5. It adds the one-bit data D S  to the higher order bit D S  side of the lower order bit data D L  to obtain 5-bit data D F  consisting of bits D S  and D 3  to D 6 , and decodes this data to obtain a laterally symmetrical PWM wave. 
     The PWM control section 4 may have a construction as shown in FIG. 4. 
     As is shown, the PWM control section 4 includes a (n L  +1)-bit, i.e., 5-bit, counter 42, a complement circuit 43, a first coincidence detection circuit 44, a second coincidence detection circuit 45, and a R-S flip-flop 46. The counter 42 counts clock pulses φ CLK  at a clock frequency f CLK  supplied to a clock input terminal 41. The complement circuit 43 provides 2&#39;s complement data D F  to the 5-bit data D F  consisting of bits D S  and D 3  to D 6  supplied from the secondary data input terminal 5 and S/P converter 2. The first coincidence detection circuit 44 compares the 5-bit data D F  and count output data D C  consisting of bits Q 5  to Q 1  provided from the counter 42 to effect coincidence detection. The second coincidence detection circuit 45 compares the 2&#39;s complement data D F  and count output data D C  to effect coincidence detection. The R-S flip-flop 46 is reset by a coincidence detection output of the first coincidence detection circuit 44 and set by a coincidence detection output of the second coincidence detection circuit 45. 
     The complement circuit 43 provides 2&#39;s complement data D F  as shown in Table 1 below to the 5-bit data D F  consisting of the one-bit data D S  and lower order n L  -bit data. 
     
                       TABLE 1______________________________________Operation of complement circuitLower order n.sub.L -bitdata of bits D.sub.3 to D.sub.6         5-bit data D.sub.F                    Complement data D.sub.F______________________________________0001          10001      011110010          10010      011100011          10011      011010100          10100      011000101          10101      010110110          10110      010100111          10111      010011000          11000      010001001          11001      001111010          11010      001101011          11011      001011100          11100      001001101          11101      000111110          11110      000101111          11111      00001______________________________________ 
    
     The counter 42 counting clock pulses φ CLK  provides the count output data DC consisting of bits Q 5  to Q 1  at timings t 0  to t 32  as shown in FIG. 5. 
     The first conincidence detection circuit 44 comparing the count output data D C  and 5-bit data D F , resets the R-S flip-flop 46 with its coincidence detection output provided at timings t 17 , t 18 , . . . , t 31  for each bit of the 5-bit data DF. The second coincidence detection circuit 45 comparing the count output data D C  and complement data D F  ; sets the R-S flip-flop 46 with its coincidence detection output provided at timings t 15 , t 14 , . . . , t 1  for each of the complement data D F . 
     The R-S flip-flop 46 operated by the outputs of the coincidence detection circuits 44 and 45, provides a PWM control signal SPWM as shown in FIG. 5, with the pulse width varying symmetrically with respect to the timing t 16  according to the lower order n L  -bit data D L . 
     The PAM control section 3 produces a PAM control signal S PAM  which is timed to the PWM control signal S PWM  provided from the PWM control section 4 according to the higher order n H  -bit data D H  consisting of bits D 0  to D 2 , the PAM control signal S PAM  being supplied to a modulating section 10. 
     The modulating section 10 includes constant current sources 14 to 16 and 18, an operational amplifier 20 and feedback resistor 22. The constant current sources 14 to 16 are respectively connected to n H  switches 11 to 13 which are controlled for switching by the PAM control signal SPAM provided from the PAM control section 3. The constant current source 18 is connected to a switch 17 which is controlled for switching by the PWM control signal S PWM  provided from the PWM control section 4. The operational amplifier 20 has an inversion input terminal 19 which can be connected to the constant current sources 14 to 16 and 18 through the switches 11 to 13 and 18. The feedback resistor 22 is connected between an output terminal 21 and inversion input terminal of the operational amplifier 20. The non-inversion input terminal of the operational amplifier 20 is grounded. 
     The switches 11 to 13 controlled for switching by the PAM control signal S PAM , i.e., the higher order n H  -bit data D H , produce a PAM wave PAM H  having a peak level h H  which is determined by current levels I 1  to I 3  (I 1  =4I 0 , I 2  =2I 0 , I 3  =I 0 ) of the respective constant current sources 14 to 16 provided with weights selected by the switching operation. The PAM wave PAM H  is supplied to the operational amplifier 20. The switch 17 for switching according to the PWM control signal SPWM, the pulse width of which is varied according to the lower order n L  -bit data D L , produces a PWM wave PWM L  having a peak level h L  which is determined by the current level I 4  of the constant current source. 18. The PWM wave P WML  is supplied to the operational amplifier 20. 
     The current level I 4  of the constant current source 18 for forming the PWM wave PWM L , is set equal to the current level I 0  of the constant current source 16 for the PAM. In this embodiment, the continuity between the PAM and PWM waves PAM H  and PWM L  is ensured with the pulse width of the PAM wave PAM H  set such that the area S H  of the PAM wave PAM H  representing one LSB of the n H  higher order bits is equal to an area SS LF  which is 2 nL  times the area S L  of the PWM wave PWM L  representing one LSB of the n L  lower order bits. 
     To meet the condition SH=S LFS , the current level I 4  of the constant current source 18 for the PWM and the pulse width τ H  of the PAM wave PAM H  may be set as ##EQU4## where τ 0  is the pulse width of one LSB of the PWM wave PWM L . 
     The operational amplifier 20 additively combines the PAM and PWM waves PAM H  and PWM L  formed by the switching operation of the switches 11 to 13 and 17 to produce resultant pulses P OUT  as shown in FIG. 7. 
     The PWM wave PWM L  supplied to the operational amplifier 20 is symmetrical with respect to the center t.sub.φ  of one conversion period T, so that it coincides with the PAM wave in full scale (FS) without including any error due to FM compohents. In addition, the energy is concentrated in the center t.sub.φ. Thus, the error due to the non-linearity of conversion characteristic of conversion through interpolation by the low-pass filter to the analog signal is small as shown in FIG. 8. Thus, the resultant pulses P OUT  obtained by addition of the PWM and PAM waves PWM L  and PAM H  in timed relation to each other, provide, when converted through interpolation by the low-pass filter to the analog signal, a D/A conversion characteristic having excellent linearity shown in FIG. 9. 
     Further, in this embodiment the N-bit digital data is divided into higher order n H  bits and lower order n L  bits, and the lower order n L  -bit data is converted to the PWM wave. Thus, it is possible to reduce the operation frequency of the pulse width control counter used for the formation of the PWM wave. 
     While in the above embodiment the N-bit input digital data is divided into the higher order n H  bits and lower order n L  bits, in case where the input digital data to be D/A converted has a large number N of bits, it is possible to divide the input digital data to three or more divisions. 
     FIG. 10 shows a different embodiment, in which the lower order n L  -bit data is further divided into n l1  -bit data and n l2  -bit data to be converted to respective PWA waves PWM l1  and PWM l2 . 
     In this second embodiment, a S/P converter 25 converts N-bit (i.e., 11-bit) serial data D IN  consisting of bits D 0  to D 10  supplied from the data input terminal 10 to parallel data D P  consisting of bits D 0  to D 10 . Of this data, the higher order n H  -bit (i.e., 3-bit) data D H  consisting of bits D 0  to D 2  is supplied to a PAM control section 30. The lower order n L  -bit (i.e., 8-bit) data D L  consisting of D 3  to D 10  is divided into n l2  -bit (i.e., 4-bit) data and n l2  -bit (i.e., 4-bit) data. The n l1  -bit data D l1  consisting of bits D 3  to D 6  is supplied to a first PWM control section 40A, and the n l2  -bit data D l2  consisting of bits D 7  to D 10  is supplied to a second PWM control section 40B. 
     The first and second PWM control sections 40A and 40B may have the same construction as that described before in connection with FIG. 4. The PAM control section 30 is also the same as in the preceding embodiment. 
     A modulating section 100 includes, in addition to the components described before in connection with the preceding embodiment, a PWM switch 27 controlled for switching by a PWM control signal S PWMB  supplied from the second PWM control section 40B and a constant current source 28 connected to the switch 27. 
     The current level I 4  of the constant current source 18 connected to the switch 17 controlled for switching by the PWM control signal S PWMA  from the first PWM control section 40A and the current level i 4  of the constant current terminal 28 connected to the switch 27 controlled for switching by the PWM control signal S PWMB  from the second PWM control section 40B, are set according to the ratio τ l1  τ l2  of the pulse width τ l1  representing one LSB of the n l1  -bit data D l1  and the pulse width τ l2  of one LSB of the n l2  -bit data D l2  such that the peak values h l1  and h l2  of the PWM waves PWM l1  and PWM l2  are related as ##EQU5## 
     As shown in FIG. 11, the time integral value S l1  of the higher order one LSB is 
     
         S.sub.l1 =h.sub.l1 ×τ.sub.l1 
    
     while the time integral value S l2  of the lower order one LSB is 
     
         S.sub.l2 =h.sub.l2 ×τ.sub.l2 
    
     Thus, S l1  is set to S l1  =2 nl2  ·S l2  to accurately represent the lower order n L  -bit digital data D L  by the PWM wave. 
     The operational amplifier 20 additively combines the PAM and PWM waves PAM H , PWM l1  and PWM l2  that are formed by the switching operation of the switches 11 to 13, 17 and 27 to produce resultant pulses P OUT  as shown in FIG. 12. 
     With the arrangement of this embodiment, in which the lower order n L  -bit data in the N-bit input digital data is divided into n l1  -bit data and n l2  -bit data for conversion to respective PWM waves PWM l1  and PWM l2 , it is possible to further reduce the operation frequency of the counter necessary for forming the PWM wave compared to that in the previous first embodiment. 
     For example, when the lower order n L  -bit data converted to the PWM waves PWM l1  and PWM l2  consists of 16 bits (with n l1  =n l2  =8-bit), if the maximum pulse width in one conversion period T is τ maxl1  =τmax l2  =10 μsec., the pulse widths τ l1  and τ l2  necessary for one LSB are ##EQU6## 
     The clock frequencies f CLKl1  and f CLKl2  used for the PWM control sections 40A and 40B are thus ##EQU7## 
     There is no need of setting the pulse width τ l1  representing one LSB of the n l1  -bit data D l1  and pulse width τ l2  representing one LSB of the n l2  -bit data D l2 . For example, the counters may be operated by setting f CLKZl1  =2f CLKl2  and the pulse widths τ l1  and τ l2  are set such that τ l1  :τ l2  =1:2 for additively combining the PWM waves PWM l1  and PWM l2  with the PAM wave PAM H . 
     FIG. 13 shows a block diagram showing a different example of the PWM control section 4 in the first embodiment shown in FIG. 3. 
     In an example shown in FIG. 13, of the input digital data DIN the lower order n L  -bit (i.e., 3-bit) data D L  consisting of bits D L0  to D L2  are converted to PWM wave PWM OUT . 
     The PWM control section in this embodiment includes a 5-bit counter 142 for counting clock pulses φ CLK  supplied at frequency f CLK  to a clock input terminal 141 and first to fourth coincidence detection circuits 151 to 154 for effecting coincidence detection with respect to the lower order 4-bit data D CL  consisting of bits Q 4  to Q 1  of the 5-bit count output data D C  consisting of bits Q 5  to Q 1  provided for timings t 0 , t 1 , t 2 , . . . shown in FIG. 14 through the counting of clock pulses φ CLK  by the counter 142. 
     The first coincidence detection circuit 151 receives the lower order n L  -bit data D L  consisting of bits D L0  to D L2  and also a one-bit data D S1  of logic level &#34;0&#34; supplied from a first secondary data input terminal 121. It compares for coincidence detection 4-bit data D X  consisting of bits D S1  and D L0  to D L2 , which is obtained by adding the one-bit data D S1  to the MSB side of the lower order n L  -bit data D L , and the count output data D CL  consisting of bits Q 4  to Q 1  from the counter 142. The coincidence detection output obtained from the first coincidence detection circuit 151 is supplied as reset pulse to a first flip-flop 161. 
     The second coincidence detection circuit 152 receives 2&#39;s complement data the 4-bit data D x  consisting of the one-bit data D S1  and lower order n L  -bit data D L  supplied from a first complement circuit 131. It compares for coincidence detection the complement data D X  and count output data D CL . The coincidence detection output obtained from the second coincidence detection circuit 152 is supplied as set pulse to a second flip-flop 162. 
     The third coincidence detection circuit 153 receives the lower order n L  -bit data D L  and one-bit data D S2  of logic level &#34;1&#34; supplied from the second secondary data input terminal 122. It compares for coincidence detection 4-bit data D Y  consisting of bits D S2  and D L0  to D L2  obtained by addition of the one-bit data D S2  to the MSB side of the lower order n L  -bit data D L  and count output data D CL  consisting of bits Q 4  to Q 1  from the counter 142. The coincidence detection output obtained from the third coincidence detection circuit 153 is supplied as reset pulse to a third flip-flop 163. 
     The fourth coincidence detection circuit 154 receives 2&#39;s complement data D y  to 4-bit data D Y  obtained by addition of the one-bit data D S2  of logic level &#34;1&#34; to the lower order n L  -bit data D L  supplied from a second complement circuit 132. It compares for coincidence detection the complement data D y  and count output data D CL . The coincidence detection output obtained from the fourth coincidence detection circuit 154 is supplied as set pulse to the third flip-flop 163. 
     The first flip-flop 161 receives the fourth bit data Q 4  from the counter 142 supplied as set pulse through an inverter 171, and it is set by the set pulse at timing t 0  (tl6) shown in FIG. 14. When the first flip-flop 161 is reset by the coincidence detection output obtained from the first coincidence detection circuit 151, it produces a first control pulse P 1  that falls at each of timings t 1  (t 17 ), t2 (t 18 ), . . . t 7  (t 23 ) according to the lower order n L  -bit data D L  consisting of bits D L1  to D L3 . 
     The second flip-flop 162 receives a reset pulse from the inverter 171. It is set by the coincidence detection output obtained from the second coincidence detection circuit 152 at each of timings t 15  (t 31 ), t 14  (t 30 ), . . ., t 9  (t 25 ) according to the lower order n L  -bit data D L , and is reset at timing t 16  (t 32 ) by the reset pulse, whereby it provides a second control pulse P 2  as shown in FIG. 14. 
     The control pulses P 1  and P 2  obtained from the first and second flip-flops 161 and 162 are supplied to a first AND gate 191 through a first OR gate 181. 
     The third flip-flop 163 is set by the coincidence detection output obtained from the fourth coincidence detection circuit 154 at each of timings (t 7 ) t 23 , (t 6 ) t 22 , . . . , (t 1 ) t 17  according to the lower order n L  -bit data D L , and is reset by the coincidence detection output obtained from the third coincidence detection circuit 153 at each of timings (t 9 ) t 25 , (t 10 ) t 26 , . . . , (t 15 ) t 31  according to the lower order n L  -bit data D L , whereby it provides a third control pulse P 3  as shown in FIG. 14. The third control pulse P 3  is supplied to a second AND gate 192. 
     The MSB data Q 5  from the counter 142 is supplied as gate control pulse through the inverter 172 to the first AND gate 191. Thus, the AND gate 191 is held enabled for a period Ta from the instant t 0  to the instant t 16  to permit the first and second control pulses P 1  and P 2  to be supplied to the second OR gate 182. The MSB data Q 5  from the counter 142 is also supplied as gate control pulse to the second AND gate 192. The second AND gate 192 is thus held enabled for a period Tb from the instant t 16  to the instant t 32  to permit the third control pulse P 3  to be supplied to the second OR gate 182. 
     The OR gate 182 permits during a first period Ta first and second control pulses P 1  and P 2  with the pulse width thereof varying symmetrically with respect to a timing t 8  according to the lower order n L  -bit data D L  and also permits during a second period Tb third control pulse P 3  with the pulse width thereof varying symmetrically with respect to a timing t 24 , as shown in FIG. 14. A PWM control signal S PWM0  which is the resultant of the first to third control pulses P 1  to P 3  is supplied to the modulating section 10 in the previous first embodiment. 
     In the modulating section 10 the fourth switch 18 is controlled for switching by the PWM control signal S PWM0 , whereby two different PWM waves PWM 1  and PWM 2  of different pulse width variations and with the pulse width thereof varying symmetrically with respect to the timings t 8  and t 24  according to the lower order n L  -bit data D L  are provided each once in one conversion period T, the former wave during the first period Ta and the latter wave during the second period Tb. 
     The PWM wave PWM 1  provided from the modulating section 10 during the first period Ta, is formed from the first and second control pulses P 1  and P 2  with the pulse widths thereof varying symmetrically with respect to the timing t 8 . Since the energy of this wave is dispersed symmetrically with respect to the timing t 8 , the conversion thereof through interpolation by the low-pass filter into the analog signal is obtained with a conversion characteristic as shown by a phantom plot in FIG. 15, with the instantaneous conversion output level being lower than the instantaneous output level of the PAM wave between OFS and FS (full scale) and coinciding with the PAM wave instantaneous output level in the OFS and FS. The energy of the PWM wave PWM2 provided during the second period Tb, is symmetrical with respect to and concentrated on the timing t 24 , so that a conversion characteristic as shown by a dashed plot in FIG. 15 can be obtained. 
     With the two different PWM waves PWM 1  and PWM 2  of different pulse width variations provided during the respective first and second periods Ta and Tb in one conversion period T as in the above example, the conversion errors due to the PWM waves PWM 1  and PWM 2  can be cancelled to o.btain excellent linearity of the D/A conversion. 
     Although in the above example the two different PWM waves are provided each once during one conversion period T, it is possible to provide the individual PWM waves alternately repeatedly a plurality of times in one conversion period T. 
     FIG. 16 is a block diagram showing a third embodiment of the present invention. N-bit serial data which is obtained through quantization of the analog signal for every sampling period T S , is supplied to a data input terminal 201. In this embodiment, 5-bit serial data D S  consisting of bits D 0  to D 4  is supplied to the data input terminal 201. 
     The serial data D S  is supplied from the data input terminal 201 to a serial-to-parallel (S/P) converter 202 for conversion to parallel data D P  consisting of bits D 0  to D 4 . 
     The parallel data D P  obtained from the S/P converter 202, is supplied to a modulation control section 200. 
     The modulation control section 200 includes a 4-bit counter 212, which counts clock pulses φCLK at frequency f CLK  supplied from a clock input terminal 211, and first and second 4-bit shift registers 213 and 214, which operate with 1/2 4  frequency division output pulses P S  from the counter 212 as clock. 
     The MSB outputs Q 13   and Q 23  of the shift registers 213 and 214 are supplied back to the respective serial data input terminals, and these shift registers shift 4-bit data cyclically with the frequency division output pulse P S  from the counter 212 as clock. 
     Of the N-bit parallel data DP consisting of bits D 0  to D 4  obtained from the S/P converter 202, the MSB side higher order n H  -bit (i.e., 2-bit) data D H  consisting of bits D 0  and D 1  of great weights is converted through a PAM decoder 215 to 4-bit data D PAM  consisting of bits d 0  to d 3 , which is supplied to the first shift register 213. 
     The PAM decoder 215 converts the higher order n H  -bit data D H  consisting of bits D 0  and D 1  such that 
     
         d.sub.0 =0 
    
     
         d.sub.1 =D.sub.0 +D.sub.1 
    
     
         d.sub.2 =(D.sub.0 +D.sub.1)·D.sub.1 
    
     and 
     
         d.sub.3 =D.sub.0 ·D.sub.1 
    
     It may consist of OR and AND gates. The 4-bit data D PAM  consisting of bits d 0  to d 3  obtained from the PAM decoder 215 is loaded as parallel data in the first shift register 213 for every one sampling period T S , and is cyclically shifted therethrough for each timing of appearance of the frequency division output pulse P S  as shown in FIG. 17. 
     The first shift register 213 supplies a first control data S A  consisting of 4 bits cyclically shifting the 4-bit data DPAM consisting of bits d 0  to d 3  to a switching control circuit 216. 
     The 4-bit data consisting of bits &#34;1, 0, 0, 0&#34; from a data input circuit 217 is loaded as parallel data in the second shift register 214 for every one sampling period T S . The second shift register 214 cyclically shifts the 4-bit data at every timing of the frequency division output pulse P S  as shown in FIG. 17 to provide second control data S B  of 4 bits, whereby the control data is supplied to the switching control circuit 216. 
     The 4-bit control data S A  and S B  provided from the shift registers 213 and 214 are supplied through NOR gates 218 to 221 to produce third control data S C  which is supplied to the switching control circuit 216. 
     The modulation control section 200 also includes first and second coincidence detection circuits 222 and 223 which executes coincidence detection with respect to the 4-bit count output data D C  consisting of bits Q 4  to Q 1  provided at every timings t 0 , t 1 , T 2 , . . . as shown in FIG. 17 through the counting of clock pulses φ CLK  by the counter 212. 
     The first coincidence detection circuit 222 receives the LSB side lower order n L  -bit (i.e., 3-bit) data D L  consisting of bits D 2  to D 4  of small weights in the N-bit parallel data D P  obtained from the S/P converter 202 and also receives one-bit data D S  of logic level &#34;1&#34; supplied from a secondary data input terminal 224. It compares for coincidence detection 4-bit data D X  consisting of bits D S  and D 2  to D 4  obtained through addition of the one-bit data D S  to the MSB side of the lower order n L  -bit data D L  consisting of bits D 2  to D 4  and count output data D C  consisting of bits Q 4  to Q 1  from the counter 212. The coincidence detection output obtained from the first coincidence detection circuit 222 is supplied as reset pulse to a flip-flop 226. 
     The second coincidence detection circuit 223 receives the complement data D X  of the 4-bit data D X  as the result of addition of the one-bit data D S  to the lower order n L  -bit data D L  consisting of bits D 2  to D 4  supplied from a complement circuit 225, and it compares for coincidence detection the complement data D X  and count output data D C . The coincidence detection output of the second coincidence detection circuit 223 is supplied as set pulse to the flip-flop 226. 
     The coincidence detection circuits 222 and 223 may each consist of four EX.OR gates and one NOR gate. 
     The flip-flop 226, which is triggered by the coincidence detection outputs of the first and second coincidence detection circuits 222 and 223, provides the PWM control signal S PWM , the pulse width τ of which varies with respect to timings t 8 , t 24 , t 40  and t 56  as shown in FIG. 17 according to the lower order n L  -bit data D L  consisting of bits D 2  to D 4 . The timings t 8 , t 24 , t 40  and t 56  are found at the center of respective periods Ta, Tb, Tc and Td which are uniform divisions of one conversion period T. 
     In this embodiment, a modulating section 230 which is controlled by the modulation control section 200 of the above construction, includes 2 nH , i.e., 4, constant current sources 231 to 234. 
     The constant current sources 231 to 234 are respectively connected to movable contacts S 1  to S 4  of four three-contact selection switches 235 to 238. The selection switches 235 to 238 have their first fixed contacts A 1  to A 4  connected to a inversion input terminal of an operational amplifier 240, while their second fixed contacts B 1  to B 4  connected to the inversion input terminal noted above through a PWM switch 239 and their third fixed contacts C 1  to C 4  to ground. 
     The operational amplifier 240 has its noninversion input terminal connected to ground and its output terminal 241 is connected to its inversion input terminal through a feedback resistor 242. 
     The PWM switch 239 is controlled for switching by the PWM control signal S PWM  provided from the flip-flop 226 of the modulation control section 200. 
     The four selection switches 235 to 238 are controlled for switching by the switching control signal S SW  provided from the switching control circuit 216 of the modulation control section 200. 
     More specifically, the first selection switch 235 is controlled by the switching control signal S SW  such that its movable contact S 1  is connected to the first fixed contact A 1  when the MSB output Q 13  of the first shift register 213 of the modulation control section 200 is at logic level &#34;1&#34;, is connected to the second fixed contact B 1  when the MSB output Q 23  of the second shift register 214 is at logic level &#34;1&#34; and is connected to the third fixed contact C 1  when both the MSB outputs Q 13  and Q 23  are at logic level &#34;0&#34;. The second to fourth selection switches 236 to 238, like the first selection switch 235, are switched according to the logic level of the outputs of the shift registers 213 and 214. 
     The four selection switches 235 to 238 successively select the four constant current sources 231 to 234 in numbers corresponding to the higher order n H  -bit data D H  consisting of bits D 0  and D 1  for every time sections Ta, Tb, Tc and Td shown in the time chart of FIG. 17 according to the first control data S A  provided from the first shift register 213, thus forming a PAM wave PAM 0  consisting of four PAM pulses as shown in FIG. 18. This PAM wave PAM 0  is supplied to the operational amplifier 240. 
     The four selection switches 235 to 238 selectively connect the four constant current sources 231 to 234 successively to the PWM switch 239 for every individual time sections Ta, Tb, Tc and Td according to the second control data S B  provided from the second shift register 214. The PWM switch 239, which is controlled for switching by the PWM control signal S PWM , forms the PWM wave PWM 0  consisting of four PWM pulses. The PWM wave PWM 0  is supplied to the operational amplifier 240. 
     The operational amplifier 240 additively combines the PAM and PWM waves PAM 0  and PWM 0  which are formed a plurality of times in one conversion period T by the switching operation of the switches 235 to 239 to produce resultant pulses P OUT  as shown in FIG. 19. 
     With this embodiment of the above construction, the lower order n L  -bit data D L  of the N-bit input digital data is converted to the PWM wave PWM 0  consisting of four PWM pulses with the pulse width τ thereof varying symmetrically with respect to the timings corresponding to the center of the time periods Ta, Tb, Tc and Td as uniform divisions of one conversion period T. Since the PWM wave PWM 0  consists of four PWM pulses provided symmetrically with the same pulse width τ and successively with a uniform delay time in one conversion period T, when it is converted through interpolation by the low-pass filter to the analog signal, the signal level can be increased to an extent corresponding to the number of provided pulses without increasing the distortion factor. 
     The higher order n H  -bit data of the N-bit input digital data is converted to the PAM wave PAM 0  timed to the PWM wave PWM 0  and consisting of four PAM pulses with pulse width thereof corresponding to the respective time periods Ta, Tb, Tc and Td. The interpulse interval between consequentive pulses of the PAM wave PAM 0  may be set to any suitable value but is preferably shorter for reducing the aperture effect. 
     In this embodiment the PAM and PWM waves PAM 0  and PWM 0  are formed with successive selection of the constant current sources 231 to 234 in the modulating section 230 in one conversion period T, so that the peak value of the resultant wave may be represented by the average value of the current levels I 1  to I 4  of the constant current sources 231 to 234. Thus, it is possible to ensure satisfactory linearity of the conversion characteristics of the PWM and PAM waves PWM 0  and PAM 0  without need of substantial high precision of the constant current sources 231 to 234, thus permitting ready monolithic IC implementation. 
     The resultant pulses P OUT  obtained through additive combination of the PAM and PWM waves PAM 0  and PWM 0  have a waveform which is symmetrical with respect to the center t.sub.φ  of the period T, so that no error due to FM components is contained. Thus, the error due to the non-linearity of the conversion characteristic of conversion to the analog signal through interpolation through the low-pass filter is small, as shown in FIG. 20. 
     FIG. 21 is a block diagram showing a fourth embodiment of the present invention. The N-bit serial data D IN  which is obtained by quantizing the analog signal for every sampling period T S  is supplied to a data input terminal 301. In this embodiment, the 3-bit serial data D IN  consisting of bits D 0  to D 2  is supplied to the data input terminal 301. 
     The serial data D IN  is supplied the data input terminal 301 to a serial-to-parallel (S/P) converter 302 for conversion to parallel data D P  consisting of bits D 0  to D 2 , which is supplied to the modulation control section 300. 
     The modulation control section 300 in this embodiment includes a 4-bit counter 304 for counting clock pulses φ CLK  at frequency f CLK  supplied from a clock input terminal 303. By counting clock pulses φ CLK  the counter 304 supplies lower order 3-bit data D CL  consisting of bits Q 3  to Q 1  in 4-bit count output data D C  consisting of bits Q 3  to Q 1  obtained at every timings t 0 , t 1 , . . ., as shown in FIG. 22, to a first gate circuit 310 and also to first to fourth coincidence detection circuits 331 to 334. 
     The first gate circuit 310 includes an inverter 311 and NOR gates 312 and 313. When the 3-bit data D CL  is provided from the counter 304, the NOR gate 312 provides a first gate output signal S G1  which is expressed as 
     
         S.sub.G1 Q.sub.1 +Q.sub.2 +Q.sub.3 
    
     while the other NOR gate 313 provides a second gate output signal SG 2  which is expressed as 
     
         S.sub.G2 =Q.sub.1 +Q.sub.2 +Q.sub.3 
    
     The first gate output signal S G1  provided from the first gate circuit 310 is supplied through an OR gate 341 to a set input terminal of a first flip-flop 351 and is also supplied through an OR gate 342 to a reset input terminal of a second flip-flop 352. The second gate output signal S G2  provided from the first gate circuit 310 is supplied to a second gate circuit 320, and is also supplied to a set input terminal of a third flip-flop 353 and also to a reset input terminal of a fourth flip-flop 354. 
     The second gate circuit 320 receives the MBS data Q 4  from the counter 304 and also carry output data C from an adder 305. It includes an inverter 321 and AND gates 322 and 323. The AND gate 322 provides a third gate output signal S G3  which is expressed as 
     
         S.sub.G3 =S.sub.G2 ·C·Q.sub.4 
    
     while the other AND gate 323 provides a fourth gate output signal S G4  which is expressed as 
     
         S.sub.G4 =S.sub.G2 ·C·Q.sub.4 
    
     The third gate output signal S G3  produced from the second gate circuit 320 is supplied through the OR gate 341 to the set input terminal of the first flip-flop 351 and is also supplied through the OR gate 343 to the set input terminal of the second flip-flop 352. The fourth gate output signal S G4  produced from the second gate circuit 320 is supplied through the OR gate 344 to the reset input terminal of the first flip-flop 351 and is also through the OR gate 342 to the reset input terminal of the second flip-flop 352. 
     The adder 305 adds data &#34;1, 0, 0&#34; to the N-bit (i.e., 3-bit) parallel data D P  consisting of bits D 0  to D 2  obtained from the S/P converter 302 and supplies the carry output data C to the second gate circuit 320. Also, it supplies the sum output data D A  consisting of bits D 0+1 , D 1  and D 2  to the first coincidence detection circuit 310 and also to a first complement circuit 306. The first complement circuit 306 produces the complement data D A  to the sum output data D A  and supplies the complement data D A  to the second coincidence detection circuit 332. The operation o the adder 305 and first complement circuit 306 is illustrated in Table 2 below. 
     
                       TABLE 2______________________________________      Carry output                  Sum ouput ComplementParallel data D.sub.p      C           data D.sub.A                            data D.sub.A______________________________________0    0      1      0         1   0   1   0    1    10    1      0      0         1   1   0   0    1    00    1      1      0         1   1   1   0    0    11    0      0      1         0   0   0   0    0    01    0      1      1         0   0   1   1    1    11    1      0      1         0   1   0   1    1    01    1      1      1         0   1   1   1    0    1______________________________________ 
    
     The N-bit (i.e., 3-bit) parallel data D P  consisting of bits D 0  to D 2  obtained from the S/P converter 302 is also supplied to the third coincidence detection circuit and also to a second complement circuit 307. The second complement circuit 307 produces 2&#39;s complement data D P  to the parallel data D P  consisting of bits D 0  to D 2 , the complement data D P  supplied to the fourth coincidence detection circuit 334. 
     The first coincidence detection circuit 331 compares for coincidence detection the count output data D C  from the counter 304 and sum output data D A  from the adder 305 and supplies the coincidence detection signal DP 1  through the OR gate 344 to the reset input terminal of the first flip-flop 351. The second coincidence detection circuit 332 compares the count output data D C  and complement data D A  to the first complement circuit 306 and supplies the coincidence detection signal DP 2  through the OR gate 343 to the set input terminal of the second flip-flop 352. The third coincidence detection circuit 333 compares the count output data D C  and parallel data D P  of the S/P converter 302 and supplies the coincidence detection signal DP 3  to the reset input terminal of the third flip-flop 353. The fourth coincidence detection circuit 334 compares the count output data D C  and complement data D P  the second complement circuit 307 and supplies the coincidence detection signal DP 4  to the set input terminal of the fourth flip-flop 354. 
     The first to fourth flip-flops 351 to 354 are triggered at the timing of rising of each of the signals supplied to the set and reset input terminals to provide first to fourth pulse width control signals S P1  to S P4  through AND gates 361 to 364. 
     The MSB output Q 4  of the counter 304 is supplied as gate control signal through an inverter 360 to the AND gates 361 to 364, so that these AND gates are held enabled only during the first half section T A  of one conversion period T, during which the MSB output Q 4  is logic level &#34;0&#34;. 
     As the first flip-flop 351 is set at the timing t 4  of rising of the first gate output signal S G1  and reset at the timing of rising of the first coincidence detection signal DP 1 , the pulse width τ 1  of the first pulse width control signal S P1  which is provided from the first flip-flop 351 through the AND gate 361 is varied according to the parallel data D P  as shown in FIG. 4. 
     As the second flip-flop 352 is set at the timing of rising of the second coincidence detection signal DP 2  and reset at the timing t 4  of rising of the first gate output signal S G1 , the pulse width τ 2  of the second pulse width control signal S P2  which is provided from the second flip-flop 352 through the AND gate 362 is varied symmetrically with the first pulse width control signal S P1  with respect to the timing t 4 . Further, for the third and fourth pulse width control signals S P3  and S P4 , the pulse width τ 3  of the third pulse width control signal S P3  is varied successively, from the timing t 8  of rising of the second gate output signal S G2  through t 7 , t 6 , . . ., t 1  according to the parallel data D p  as shown in FIG. 22. 
     The first to fourth pulse width control signals S P1  to S P4  are supplied to a modulating section 370. 
     The modulating section 370 includes first to fourth switches 371 to 374, which are controlled for switching by the first to fourth pulse width control signals S P1  to S P4 , first to fourth constant current sources 381 to 384 connected to the respective switches 371 to 374, an operational amplifier 390 with an inversion input terminal thereof connected to the constant current sources 381 to 384 through the respective switches 371 to 374, and a feedback resistor 395 connected between an output terminal 391 and inversion input terminal of the operational amplifier 390. A non-inversion input terminal of the operational amplifier 390 is connected to ground. 
     The first to fourth switches 371 to 374 are controlled for switching according to the first to fourth pulse width control signals S P1  to S p4  to form four different PWM waves PWM 1  to PWM 4  of different pulse width variations according to the parallel data D P . These PWM waves are supplied to the inversion input terminal of the operational amplifier 390. 
     The operational amplifier 390 additively combines the PWM waves PWM 1  to PWM 4  to produce the PWM wave PWM OUT  which is symmetrical in one conversion period T, as shown in FIG. 23. 
     The PWM wave PWM OUT  obtained from the modulating section 370 corresponds to a PAM wave, the pulse width of which coincides with the maximum pulse width τ max  in one-fourth FS (full scale), one-half FS, three-fourth FS and FS, and which does not contain any PWM components. Thus, when the PWM wave PWM OUT  is converted to the analog signal through interpolation through the low-pass filter, a conversion characteristic which coincides with the conversion characteristic of the PWM wave in the one-fourth FS, one-half FS, three-fourth FS and FS as shown in FIG. 24. The PWM wave PWM OUT  is also symmetrical waveform, and its energy is dispersed from the center timing t 4  in OFS to one-fourth FS and one-half FS to three-fourth FS and is concentrated in one-fourth FS to one-half FS and three-fourth FS to FS. Thus, a conversion characteristic in which the direction of error due to non-linearity is reversed for every one-fourth FS as shown in FIG. 24 can be obtained. In addition, the practical peak level h of the PWM wave PWM OUT  is determined by the average value of the current levels I 1  to I 4  of the constant current sources 381 to 384, so that satisfactory linearity of the conversion characteristic can be obtained without need of high precision of the constant current sources 381 to 384. Thus, the embodiment is suited for monolithic IC implementation. 
     While in the above embodiment the linearity of the conversion characteristic can be ensured in one-fourth FS, one-half FS, three-fourth FS and FS through additive combination of the four different PWM waves PWM 1  to PWM 4  using the four contact current sources 381 to 384, it is possible by using M contact current sources to obtain a resultant PWM wave corresponding to PAM wave for every FS/M. 
     As has been made apparent from the above embodiments, with the digital-to-analog converting system according to the present invention the N-bit input digital data is divided at least two data, i.e., higher order n H  bits and lower order n L  bits for conversion to respective PAM and PWM waves to be combined together. Thus, the operation frequency of the counter used for the PWM wave pulse width control can be reduced to permit the D/A conversion of high resolution to be performed at a practical operation frequency. In addition, since the individual PWM waves are additively combined in a timed relation to one another in one conversion period, the D/A conversion which is free from errors due to FM components and having excellent linearity, can be performed over a wide dynamic range. Thus, the intended ends of the present invention can be fully attained.