Abstract:
A ferroelectric capacitor includes a lower electrode, a ferroelectric film provided over the lower electrode and having a perovskite-type structure and an upper electrode provided over the ferroelectric film. The ferroelectric film includes a first ferroelectric film part having a first crystal system and formed along at least one interface with at least one of the lower electrode and the upper electrode and a second ferroelectric film part having a second crystal system that is different from the first crystal system.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor device and particularly relates to a semiconductor device having a ferroelectric capacitor. 
     Semiconductor memory devices such as DRAMs and SRAMs are widely used as high-speed main memory devices for information processing devices such as computers. However, such semiconductor memory devices are volatile in nature and thus information stored thereon is lost when the power supply is turned off. Non-volatile magnetic disk devices are commonly used as large-scale auxiliary storage devices for storing programs and data. 
     However, magnetic disk devices are bulky, vulnerable to mechanical shocks and have a large consumption power. A further drawback of magnetic devices is a slow access speed during information read/write operations. In order to obviate such drawbacks, recently, EEPROMs or flash memories that store information by accumulating electric charges on floating gate electrodes are often used as non-volatile auxiliary storage devices. Particularly, flash memories have a cell structure similar to DRAMs and can be formed at a large integration density. Therefore, flash memories are becoming of an interest as large-scale memory devices that are comparable to magnetic disk devices. 
     In the EEPROM or a flash memory, information is written by injecting hot electrons into floating gate electrodes via a tunnel insulation film. Such memory devices have drawbacks that a writing operation is time consuming and that the tunnel insulation films deteriorate due to repeatedly performed information write/erase operations. 
     In order to obviate such drawbacks, a ferroelectric memory device (hereinafter referred to as FeRAM) has been proposed that stores information in the form of spontaneous polarization. Such FeRAM has a structure similar to that of the DRAM in that each memory cell transistor is provided as a single MOSFET. Further, a dielectric film in the memory cell capacitor is replaced by a ferroelectric material such as PZT (Pb(Zr,Ti)O 3 ) or PLZT ((Pb,La) (Zr,Ti)O 3 ) and further by SBT(SrBi 2 Ta 2 O 3 ). The FeRAM is capable of being integrated at a high integration density. 
     The ferroelectric semiconductor memory device controls the spontaneous polarization of the ferroelectric capacitor by applying electric fields, so that a writing speed becomes faster by a factor of 1000 or more as compared to an EEPROM or a flash-memory in which information is written by injecting hot electrons into the floating gate through the tunneling insulation film. Further, the FeRAM is advantageous in that the power consumption is reduced to about {fraction (1/10)} that of an EEPROM or a flash-memory. Further, since a tunneling insulation film is not required, the FeRAM has an increased lifetime and can perform writing operations of about one hundred thousand times that of a flash-memory device. 
     2. Description of the Related Art 
       FIG. 1  shows the construction of a conventional FeRAM  10 . 
     As shown in  FIG. 1 , the FeRAM  10  is constructed on a p-type Si-substrate  11  and is formed on a p-type well  11 A having an active region defined by a field oxide film  12 . In the active region, a gate electrode  13  is formed in correspondence to a word line of the FeRAM via a gate oxide film that is not shown in the figure. Further, n + -type diffusion regions  11 B and  11 C are formed in the substrate  11  on both sides of the gate electrode  13  to serve as a source region and a drain region, respectively, of the memory cell transistor. A channel region is formed in the p-type well  11 A at a position between the diffusion regions  11 B and  11 C. 
     The gate electrode  13  is covered by a CVD oxide film  14  that covers the surface of the Si substrate  11  in correspondence to the active regions. A ferroelectric capacitor C including a lower electrode  15 , a ferroelectric film  16  such as a PZT film formed on the lower electrode  16  and an upper electrode  17  formed on the ferroelectric film  16  is formed on the CVD oxide film  14 . The ferroelectric capacitor C is covered with an insulation film  18  such as a CVD oxide film. The upper electrode  17  is electrically connected to the diffusion region  11 B via a local interconnection pattern  19 A that contacts the upper electrode  17  at a contact hole  18 A formed in the insulation film  18  and contacts the diffusion region IIB at a contact hole  18 B formed in the insulation films  18  and  14 . 
     Further, via a contact hole  18 C formed in the insulation films  18  and  14 , the diffusion region  11 C is electrically connected to an electrode  19 B that forms a bit-line of the FeRAM  10 . The entire surface of the thus-formed FeRAM  10  is protected by a protection insulation film  20 . 
     In a conventional ferroelectric capacitor, the lower electrode  15  is often made of a Ti/Pt stacked film and the ferroelectric film  16  provided on the lower electrode  15  is made of a PZT film. For such a ferroelectric capacitor, the Pt film forming the lower electrode  15  is mainly formed of Pt polycrystals oriented in the &lt;111&gt; direction. Therefore the orientation of the ferroelectric film  16  formed on the Ti/Pt stacked film is dominated by the orientation of the lower electrode and, as a result, is mainly oriented in the &lt;111&gt; direction. That is to say, it is known that such a ferroelectric capacitor has a so-called (111) orientation (see J. Appl. Phys, vol. 70, No. 1, 1991, pp. 382-388). 
       FIG. 2  is a schematic diagram showing a structure of a ferroelectric capacitor C of the related art. 
     Referring to  FIG. 2 , the ferroelectric capacitor insulation film  16  has a micro-structure of columnar PZT crystals extending from the lower electrode  15  to the upper electrode  17  with each columnar PZT crystals being oriented in the &lt;111&gt; direction. It is known that the PZT crystal belongs to a tetragonal system and has spontaneous polarization in the &lt;001&gt; direction. In such columnar crystals oriented in the &lt;111&gt; direction, the direction of polarization will be inclined against a direction of electric field connecting the upper and lower electrodes  15  and  17 , as shown by arrows in FIG.  2 . 
       FIG. 3  is a graph showing electric characteristics of such a ferroelectric capacitor. In  FIG. 3 , the vertical axis represents polarization and the horizontal axis represents an applied voltage. In  FIG. 3 , white circles indicate electric characteristics for ferroelectric capacitor of  FIG. 2 , when PZT crystals are oriented in the &lt;111&gt; direction. Black circles indicate, electric characteristics for the ferroelectric capacitor of  FIG. 2 , when PZT crystals are oriented in the &lt;001&gt; direction. 
     As can be seen in  FIG. 3 , the ferroelectric capacitor clearly presents, for either case, hysteresis properties that are specific to ferroelectric materials. As is readily understood, the ferroelectric capaciter has a greater remanent polarization and a better retention property when the PZT crystals in the capacitor insulation film  16  are oriented in a direction of applied electric field, or the &lt;001&gt; direction, as compared to a case where they are oriented in a direction inclined against the applied electric field, or the &lt;111&gt; direction. 
     When such a ferroelectric capacitor is used as the capacitor C for the FeRAM shown in  FIG. 1 , information can be retained in the form of remanent polarization of the capacitor C. The state of polarization of such a ferroelectric capacitor can be read out at the bit-line  19 B via a transistor having the diffusion regions  11 B,  11 C and the gate electrode  13 . Also, during a writing operation or an erasing operation, a predetermined writing voltage is applied to the bit-line  19 B to turn on the transistor so as to apply a voltage between the electrodes  15  and  17  of the ferroelectric capacitor C, that is sufficient for reversing the polarization property of FIG.  3 . 
     With such a ferroelectric capacitor, as shown in  FIG. 4 , a phenomenon called fatigue or deterioration of retention property occurs in which the value of remanent polarization Pr, that is to say, the retention property decreases with time. Also, it is known that a phenomenon called an imprint deficiency occurs when “1” or “0” is repeatedly written. Such imprint deficiency can be seen from  FIG. 5 , in which it is shown that the coercive voltage Vc of  FIG. 3  shifts with time. 
       FIG. 6  is a diagram showing a retention property of a ferroelectric capacitor using a ferroelectric film of PZT polycrystals oriented in the &lt;111&gt; direction in comparison to a retention property of a ferroelectric capacitor using a ferroelectric film of PZT polycrystals oriented in the &lt;001&gt; direction. 
     Referring to  FIG. 6 , it can be seen that a fatigue clearly occurs for the ferroelectric capacitor using the ferroelectric film of PZT polycrystals oriented in the &lt;111&gt; direction. On the contrary, it can be seen that hardly any fatigue occurs for the ferroelectric capacitor using the ferroelectric film of PZT polycrystals oriented in the &lt;001&gt; direction. It may be understood that for the ferroelectric film of PZT polycrystals oriented in the &lt;111&gt; direction, when directions of polarization are different between a pair of neighboring domains, strain is accumulated in a domain wall, and a defect due to the strain causes deterioration of the retention property of the ferroelectric film. For the ferroelectric capacitor using the ferroelectric film of PZT polycrystals oriented in the &lt;001&gt; direction, directions of polarization are parallel between neighboring domains and therefore no such accumulation of strain occurs in the domain wall. 
       FIG. 7  is a graph showing an amount of coercive voltage shift for the same ferroelectric capacitor. 
     Referring to  FIG. 7 , it can be seen that the coercive voltage shift occurs for the case where the PZT film is oriented in the &lt;001&gt; direction in a similar manner to the case where the PZT film is oriented in the &lt;111&gt; direction. Based on a recognition that the deterioration with time of the polarization hardly occurs for the PZT film oriented in the &lt;001&gt; direction shown in  FIG. 6 , it can be assumed that any shift of the coercive voltage Vc occurring in the PZT film is not due to the strain in the domain wall shown in  FIG. 2  or deterioration of the PZT film itself. Such deterioration of an imprint property can be assumed as being due to electric charges accumulated near a boundary surface between the PZT film  16  and the upper electrode  17  or the lower electrode  15  adjacent thereto. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is a general object of the present invention to provide a novel and useful ferroelectric capacitor and a semiconductor device that can obviate the drawbacks described above. 
     It is another and more specific object of the present invention to provide a ferroelectric capacitor and a semiconductor device having improved retention and imprint properties. 
     In order to achieve the above objects, a ferroelectric capacitor is provided that includes:
         a lower electrode;   a ferroelectric film provided over the lower electrode and having a perovskite-type structure; and   an upper electrode provided over the ferroelectric film,   the ferroelectric film including a first ferroelectric film part having a first crystal system and formed along at least one interface with at least one of the lower electrode and the upper electrode and a second ferroelectric film part having a second crystal system that is different from the first crystal system.       

     According to the present invention, a ferroelectric capacitor using a perovskite-type ferroelectric film belonging to a tetragonal system and oriented in the &lt;001&gt; direction is provided with a perovskite-type ferroelectric layer belonging to a rhombohedral system along at least one interface with at least one of the upper and lower electrodes. Thus, a retention property and a fatigue property of the ferroelectric capacitor is improved and the imprint deficiency can be reduced. 
     PZT is a material having a composition that can be generally represented as Pb(Zr 1−x , Ti x )O 3 , where x is a composition parameter and a solid-solution is formed between PbZrO 3  end member and PbTiO 3  end member. In such a system, phases belonging to some different systems appear depending on the composition of the solid-solution. 
       FIG. 8  is a simplified phase-equilibrium diagram of PZT. In  FIG. 8 , the vertical axis represents temperature and the horizontal axis represents a composition parameter x. 
     Referring to  FIG. 8 , it can be seen that with a composition x≈0.48 being taken as a boundary, a phase belonging to the tetragonal system appears on the side where Ti is rich and a phase belonging to the rhombohedral system appears on the side where Zr is rich. For a composition near the PbZrO 3  end member, a phase belonging to the orthorhombic system appears. 
     The phase belonging to the tetragonal system and the phase belonging to the rhombohedral system are both ferroelectric phases having spontaneous polarizations shown by arrows in FIG.  8 . On the contrary, the PbZrO 3  phase belonging to the orthorhombic system does not show a ferroelectric property. 
     During a basic research for the present invention, the inventors have created a ferroelectric capacitor having a capacitor insulation film that is formed using not only the PZT film belonging to the tetragonal system but also a PZT film belonging to the rhombohedral system and have examined an imprint property of such a ferroelectric capacitor. 
       FIG. 9  is a graph similar to that of FIG.  7  and shows a result of examination of imprint property for a ferroelectric capacitor in which PZT film of various crystal phases is used as a capacitor insulation film  16 . The results shown in  FIG. 7  are superimposed on a graph of FIG.  9 . 
     Referring to  FIG. 9 , it can be seen that in case where the PZT film belonging to the rhombohedral system oriented in the &lt;100&gt; direction, or, (100) oriented is used as the above-mentioned ferroelectric film  16 , an amount of shift of the coercive voltage Vc becomes very small so that the amount of shift of voltage is only about −0.1 V for data retention of about 1000 hours. 
     It is to be noted that, for the PZT film belonging to the rhombohedral system, a value of remanent polarization is small and therefore a retention property is also lower as compared to the PZT film belonging to the tetragonal system. Accordingly, it can be understood that if such a film having a good imprint property is formed at the upper and lower electrode interfaces, respectively, it is possible to prevent deterioration of the imprint property due to charge accumulation near the electrode interface. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a cross-sectional diagram showing a FeRAM of the related art. 
         FIG. 2  is a schematic diagram showing a structure of a ferroelectric capacitor of the related art. 
         FIG. 3  is a graph showing electric characteristic of a ferroelectric capacitor of the related art. 
         FIG. 4  is a diagram for explaining a fatigue produced in the ferroelectric capacitor. 
         FIG. 5  is a diagram explaining an imprint deficiency produced in the ferroelectric capacitor. 
         FIG. 6  is a graph showing an electric property of the ferroelectric capacitor of the related art. 
         FIG. 7  is a diagram used for explaining a drawback of the ferroelectric capacitor of the related art. 
         FIG. 8  is a simplified phase equilibrium diagram of the PZT system material. 
         FIG. 9  is a diagram for explaining a principle of the present invention. 
         FIG. 10  is a schematic diagram showing a structure of a ferroelectric capacitor of a first embodiment of the present invention. 
         FIGS. 11A through 11D  are diagrams showing various steps of a fabrication process of ferroelectric capacitors of a second and a third embodiment of the present invention. 
         FIGS. 12A through 12C  are diagrams showing various steps of fabricating FeRAM according to the fourth embodiment of the present invention. 
         FIGS. 13D through 13F  are diagrams showing further various steps of fabricating FeRAM according to the fourth embodiment of the present invention. 
         FIGS. 14G through 14I  are diagrams showing further various steps of fabricating FeRAM according to the fourth embodiment of the present invention. 
         FIGS. 15J through 15L  are diagrams showing further various steps of fabricating FeRAM according to the fourth embodiment of the present invention. 
         FIGS. 16M through 16O  are diagrams showing further various steps of fabricating FeRAM according to the fourth embodiment of the present invention. 
         FIGS. 17P through 17R  are diagrams showing further various steps of fabricating FeRAM according to the fourth embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In the following, principles and embodiments of the present invention will be described with reference to the accompanying drawings. 
     A first embodiment of the present invention will be described with reference to  FIG. 10  that shows a ferroelectric capacitor  30  of a first embodiment of the present invention. 
     Referring to  FIG. 10 , a ferroelectric capacitor  30  is formed on a Si substrate  31  via a SiO 2  film  32 . The ferroelectric capacitor  30  includes a lower electrode  33 , a PZT film  34  formed on the lower electrode  33  and an upper electrode  35  formed on the PZT film  34 . The lower film  33  is a Pt film that is mainly oriented in the &lt;100&gt; direction and has a thickness of typically about 100 nm. 
     The PZT film  34  includes a PZT film part  34 A formed at an interface with the lower electrode  33 , a PZT film part  34 B provided on the PZT film part  34 A and a PZT film part  34 C provided on the PZT film part  34 B at an interface with the upper electrode  35 . The PZT film part  34 A has a thickness of about 20 nm and is formed of PZT crystals belonging to the rhombohedral system. The PZT film part  34 B has a thickness of about 180 nm and is formed of PZT crystals belonging to the tetragonal system. The PZT film part  34 C has a thickness of about 20 nm and is formed of PZT crystals belonging to the rhombohedral system. The PZT film part  34 A has a composition Pb 1.05 (Zr 0.70 Ti 0.30 )O 3  and is mainly oriented in the &lt;100&gt; direction in accordance with the direction of orientation of the lower electrode  33 . 
     Also, the PZT film part  34 B formed on the PZT film part  34 A has a composition Pb 1.05 (Zr 0.45 Ti 0.55 )O 3  and is mainly oriented in the &lt;100&gt; direction. Further, the PZT film part  34 C formed on the PZT film part  34 B is mainly oriented in the &lt;100&gt; direction as in the case of the PZT film part  34 A and has a composition Pb 1.05 (Zr 0.70 Ti 0.30 )O 3 . 
     With the ferroelectric capacitor  30  having such a structure, a major part of the PZT film  34  is the PZT film part  34 B belonging to the tetragonal system oriented in the &lt;001&gt; direction. Therefore, the ferroelectric capacitor  30  has a large remanent polarization and an improved retention property. Also, with such a ferroelectric capacitor, the PZT film parts  34 A and  34 C belonging to the rhombohedral system are provided at the interfaces with the upper and lower electrodes  33  and  35 . Accordingly, it is understood that the shift of the coercive voltage caused by an accumulation of electric charges at the interfaces with the electrodes is reduced. 
     It is to be noted that the above-mentioned PZT film parts  34 A and  34 C are not limited to the phase of the rhombohedral system but may also belong to the orthorhombic system shown in the phase equilibrium diagram of FIG.  8 . 
     Further, the PZT film parts  34 A and  34 C belonging to the rhombohedral system need not be formed on both interfaces with the electrodes but the same effect may be obtained with either one of the PZT film parts. 
     Also, any one of the PZT film parts  34 A through  34 C may be a PLZT film including La and its composition is expressed as (Pb, La) (Zr, Ti)O 3 . Further, the above-mentioned PZT film parts  34 A through  34 C may contain Sr or Ca. 
     Referring to the phase equilibrium diagram shown in  FIG. 8 , it can be seen that the PZT film parts  34 A and  34 C belonging to the rhombohedral system are obtained by setting the composition parameter x in Pb(Zr 1−x , Ti x )O 3  to a value less than about 0.48 and the PZT film part  34 B can be obtained by setting the composition parameter x to a value greater than or equal to about 0.48. 
     Referring to  FIGS. 11A through 11D , a process of fabricating the ferroelectric capacitor  30  of  FIG. 10  will be described as a second embodiment of the present invention. 
     Referring to  FIG. 11A , the Si substrate  31  provided with the SiO 2  film  32  is subjected to a sputtering process in an Ar atmosphere such that a Pt film serving as the lower electrode  33  is deposited with a thickness of about 200 nm. During the sputtering process, O 2  may be introduced in the sputtering atmosphere by an amount that is about 20% of the sputtering atmosphere, such that the produced Pt film is an ordinary film oriented in the normal &lt;111&gt; direction but may be a film oriented in the &lt;100&gt; direction. See, for example, M. H. Kim, et al., J. Mater. Res. Soc. Vol. 14, No. 3 (1999), pp. 634-637. 
     In a step shown in  FIG. 11B , a sol-gel solution of 2 weight % with a Pb:Zr:Ti ratio of 105:70:30 is applied on the structure shown in FIG.  11 A and dried. Then, the structure undergoes a rapid heating process for 60 seconds at 700° C. in an oxygen atmosphere. Thus, the PZT film part  34 A of PZT crystals belonging to the rhombohedral system oriented in the &lt;100&gt; direction and having a composition expressed as Pb 1.05 (Zr 0.70 Ti 0.30 )O 3  is formed with a thickness of about 20 nm. 
     Then, in a step shown in  FIG. 11C , a sol-gel solution of 15 weight % with a Pb:Zr:Ti ratio of 105:45:55 is applied on the structure shown in FIG.  11 B and dried. Then, the structure undergoes a rapid heating process for 60 seconds at 700° C. in an oxygen atmosphere. Thus, on the PZT film part  34 A, the PZT film part  34 B of PZT crystals belonging to the tetragonal system oriented in the &lt;001&gt; direction and having a composition expressed as Pb 1.05 (Zr 0.45 Ti 0.55 )O 3  is formed with a thickness of about 180 nm. 
     Further, in a step shown in  FIG. 11D , the PZT film part  34 C of rhombohedral system is formed with a step similar to the step of fabricating the above-mentioned PZT film part  34 A. Further,a Pt upper electrode  35  is formed on the PZT film part  34 C by a normal sputtering process. Thus, the above-mentioned ferroelectric capacitor  30  is obtained. 
     For comparison, a ferroelectric capacitor having a PZT film oriented in the &lt;111&gt; direction as the PZT film has been formed by a similar process. It is found that for the ferroelectric capacitor  30  formed in accordance with the present embodiment, a value of the remanent polarization Pr is increased by a factor of 1.5 of the comparative ferroelectric capacitor. This may be because the PZT film  34 B in the capacitor insulation film  34  is oriented in the &lt;001&gt; direction. 
     Data retaining property has been tested with an accelerated test at 150° C. for 160 hours. The result showed that for the comparative ferroelectric capacitor, the remanent polarization Pr decreased by as much as about 25%, whereas for the ferroelectric capacitor of the present invention, the decrease of the remanent polarization Pr is less than 5%. 
     Further, as for the shift of the coercive voltage, it has been shown that the amount of shift of the coercive voltage Vc is less than 0.1 V for the ferroelectric capacitor  30  of the present embodiment that is substantially improved as compared to the comparative ferroelectric capacitor having a 0.43 V shift of the coercive voltage. 
     Accordingly, with the ferroelectric capacitor  30  of the present embodiment, the electric property is improved as compared to the ferroelectric capacitor of the related art that used the PZT film oriented in the &lt;111&gt; direction. 
     It is to be noted that in the present embodiment, the PZT film is formed on the Pt electrode oriented in the &lt;100&gt; direction, but the PZT film may also be formed on an ordinary Pt electrode having an (111) orientation that is oriented in the &lt;111&gt; direction. 
     In the present embodiment, the PZT film may be formed by a sputtering process. 
     In such a case, an amorphous PZT film with a Ti composition x being less than 0.48 (x&lt;0.48) is crystallized by a rapid heating process in an oxygen atmosphere to form the PZT film  34 A belonging to the rhombohedral system. Then, an amorphous PZT film of a Ti composition x being greater than or equal to 0.48 (0.48≦x) is formed by a sputtering process. The amorphous PZT film is crystallized in an oxygen atmosphere to form a PZT film  34 A belonging to the tetragonal system. In a manner similar to the above-mentioned PZT film  34 A, the PZT film  34 C belonging to the rhombohedral system is formed by sputtering and rapid heating processes. 
     It is to be noted that the above-described PZT films  34 A,  34 B and  34 C may be formed by a CVD method. 
     Referring again to  FIGS. 11A through 11D , a method of fabricating a ferroelectric capacitor of a third embodiment of the present invention will be described, wherein the PZT films  34 A,  34 B and  34 C are formed by a CVD process. 
     In the present embodiment, the step of  FIG. 11A  is the same as the previous embodiment. A Pt film oriented in the &lt;100&gt; direction is formed as the lower electrode  33  on the SiO 2  film  32  covering the Si substrate  31 . 
     Then, in the step shown in  FIG. 11B , a sample of the structure shown in  FIG. 11A  is introduced into a processing container of a CVD apparatus (not shown). An internal pressure of the processing container is set to a range between 130 and 1300 Pa and the temperature of the substrate under process is set to a range between 500 to 600° C. 
     Under such a condition, Pb(DPM) 2 , Zr(DMHD) 4  and Ti(iPrO) 2 (DPM) 2  diluted with THF are introduced into the processing container as Pb, Zr and Ti vapor phase materials with a flow ratio of 1:0.56:0.46. A carrier gas containing for example Ar or He and an oxidation gas such as O 2  gas are also introduced into the processing container. Thus, the PZT film part  34 A of the rhombohedral system is grown on the Pt film  33  with a thickness of about 20 nm. 
     Then, in the step shown in  FIG. 11C , the flow ratio of the above-mentioned vapor phase material is altered to 1:0.55:0.55. Thus, the PZT film part  34 B of the tetragonal system is grown the PZT film part  34 A  33  with a thickness of about 180 nm. 
     Finally, in the step shown in  FIG. 11D , the flow ratio of the above-mentioned vapor phase material set to a value equal to the case of  FIG. 11B , so as to grow the PZT film part  34 C on the PZT film part  34 B. 
     It is to be noted that in addition to Pb(DPM) 2 (Pb(C 11 H 19 O 2 ) 2 ) described above, Pb(C 5 H 7 O 2 ) 2  and Pb(C 11 H 19 O 2 )2(C 10 H 22 O 5 ) can be used as the vapor phase material of Pb. Similarly, in addition to Zr(DMHD) 4  described above, Zr(DPM) 4  and Zr(tBuO)(DPM) 3  can be used as the vapor phase material of Zr. Further, in addition to Ti(iPrO) 2 (DPM) 2  described above, Ti(i-PrO) 2 (DMHD) 2  and Ti(t-AmylO) 2 (DMHD) 2  can be used as the vapor phase material of Ti. 
     Referring to  FIGS. 12A through 17R , a process of fabricating an FeRAM according to the fourth embodiment of the present invention will be described. 
     Referring to  FIG. 12A , a p-type well  41 A and an n-type well  41 B are formed on a p-type or an n-type Si substrate  41 . Further, field oxide films  42  defining respective active regions are provided on the Si substrate  41  in the wells  41 A and  41 B. 
     Gate oxide films  43  are formed on the active regions of the p-type well  41 A and the n-type well  41 B. For the p-type well  41 A, a p-type polysilicon gate electrode  44 A is formed on the gate oxide film  32  and for the n-type well  41 B, an n-type polysilicon gate electrode  44 B is formed on the gate oxide film  43 . Also, in an example shown in the figure, polysilicon interconnection patterns  44 C and  44 D extend on the field oxide films  42  in a manner similar to the polysilicon gate electrodes  44 A and  44 B. 
     Also in a structure shown in  FIG. 12A , n-type impurities are ion implanted into the active region of the p-type well  41 A using the gate electrode  44 A and side wall insulation films on both sides of the gate electrode  44 A as a self-aligning mask so as to form n-type diffusion regions  41   a  and  41   b . Similarly, p-type impurities are ion implanted into the active region of the n-type well  41 B using the gate electrode  44 B and side wall insulation films on both sides of the gate electrode  44 B as a self-aligning mask so as to form p-type diffusion regions  41   c  and  41   d.    
     The process so far is nothing but an ordinary CMOS process. 
     Next, in a step shown in  FIG. 12B , a SiON film  45  having a thickness of about 200 nm is deposited by performing a CVD process on the structure shown in FIG.  12 B. Further, a SiO 2  film  46  having a thickness of about 1000 nm is deposited thereon. 
     In a step shown in  FIG. 12C , the SiO 2  film  46  is polished and planarized by a CMP (chemical mechanical polishing) process with the SiON film  45  being used as a stopper. In a step shown in  FIG. 13D , contact holes  46 A to  46 D are formed through the planarized SiO 2  film  36  such that the diffusion regions  41   a ,  41   b ,  41   c  and  41   d  are exposed, respectively. In an example shown in the figures, the SiO 2  film  46  is further provided with a contact hole  46 E that exposes the connection pattern  44 C. 
     Next, in the step of  FIG. 13E , a W layer  47  is deposited on the structure of  FIG. 13D  so as to fill the contact holes  46 A to  46 E. Further, in a step shown in  FIG. 13F , the W layer  47  thus deposited is subjected to a CMP process with the SiO 2  film  46  being used as a stopper. As a result of the polishing process, there are formed W plugs  47 A to  47 E in correspondence to the contact holes  46 A to  46 E, respectively. 
     Next, in the step of  FIG. 14G , an oxidization stopper film  48  of SiON and an SiO 2  film  49  are deposited consecutively on the structure of  FIG. 13F  respectively with the thicknesses of 100 nm and 130 nm, respectively, followed by a heating process at 650° C. for 30 minutes conducted in an N 2  atmosphere such that a sufficient degassing process is performed. 
     Next, in the step of  FIG. 14H , a Ti film  50  and a Pt film  51  are deposited consecutively on the SiO 2  film  49  with respective thicknesses of 20 nm and 175 nm by a sputtering process. The Ti film  50  and the Pt film  51  thereon constitute a lower electrode layer. It is preferable that the sputtering process of the Pt film  51  is conducted in an Ar gas with 20% O 2  gas being added thereto. 
     In a step shown in  FIG. 14H , after depositing the Pt film  41 , the PZT or PLZT film  52  is deposited with a thickness of about 220 nm in the CVD apparatus. In the present embodiment, deposition of the PZT or PLZT film  52  is performed by firstly depositing a PZT or PLZT film belonging to the rhombohedral system with a Ti composition x being less than 0.48 (x&lt;0.48) with a thickness of about 20 nm, then depositing a PZT or PLZT film belonging to the tetragonal system with a Ti composition x being greater than or equal to 0.48 (0.48≦x) with a thickness of about 180 nm and further depositing a PZT or PLZT film belonging to the rhombohedral system with a Ti composition x being less than 0.48 (x&lt;0.48) with a thickness of about 20 nm. Either a sol-gel process or a sputtering process may be performed for deposition of the PZT film or the PLZT film. 
     Further, in a step shown in  FIG. 14H , the substrate  41  is returned to the sputtering apparatus after the above-mentioned rapid thermal processing step. Therein, a Pt film, an IrO 2  film or an SrRuO 3  film is deposited on the ferroelectric film  52  with a thickness of about 200 nm to form the upper electrode layer  53 . 
     Then, in a step shown in  FIG. 14I , a resist pattern is formed on the upper electrode layer  53  and the upper electrode layer  53  is dry-etched using the resist pattern as a mask, such that an upper electrode pattern  53 A is formed on the ferroelectric film  52  in correspondence with the upper electrode layer  53 . Further, in a step shown in  FIG. 14I , after forming the upper electrode pattern  53 A, an annealing process is conducted in an O 2  atmosphere for 60 minutes at 650° C. so as to remove any damage caused in the ferroelectric film  52  during a sputtering or patterning process of the upper electrode layer  53 . 
     In a step shown in  FIG. 15J , a resist pattern corresponding to a capacitor insulating layer pattern of the desired ferroelectric capacitor is formed on the ferroelectric film  52 . Then, the ferroelectric film  52  is dry-etched using the resist pattern as a mask to form a capacitor insulation film pattern  52 A. Further, a sputtering process is conducted under the same condition as for the ferroelectric capacitor layer  52  such that an encapping layer  52  of the same material as the ferroelectric capacitor layer  52  is deposited that has a thickness of about 20 nm, and in the O 2  atmosphere, a rapid heating process is performed for 60 seconds at 700° C. The encapping layer  52 B protects the ferroelectric film  52 A from reduction. 
     Then, in a step shown in  FIG. 15K , a resist pattern corresponding to the desired lower electrode pattern is formed on the lower electrode layer  51 , or, the encapping layer  52 B, and the encapping layer  52 B and underlying lower electrode layers  50 ,  51  are dry-etched using the resist pattern as a mask to form a lower electrode  51 A. Further, in a step shown in  FIG. 15K , after patterning the lower electrode pattern  51 A, the resist pattern is removed and a heating process is conducted in the O 2  atmosphere for 60 minutes at 650° C. so as to remove damages caused in the ferroelectric film  52 A during the dry-etching process. 
     Further, in a process shown in  FIG. 15L , an SiO 2  film  54  is deposited on the structure shown in  FIG. 15K  by the CVD process with a thickness of typically about 200 nm. Further, an SOG film  55  is deposited thereon to reduce the level difference at stepped parts. The SiO 2  film  54  and the SOG film  55  form an interlayer insulation film  56 . 
     Then, in a step shown in  FIG. 16M , a contact hole  56 A that exposes the upper electrode pattern  53 A and a contact hole  56 B that exposes the lower electrode pattern  51 A are formed in the interlayer insulation film  56 . In a step shown in  FIG. 16N , contact holes  56 C and  56 D that expose the W plugs  47 B and  47 D, respectively, are formed through the interlayer insulation film  56  and the underlying SiO 2  film  49  and SiON anti-oxidation film  48 . In a process shown in  FIG. 16M , after dry-etching the contact holes  56 A and  56 B, a heating process is conducted in an O 2  atmosphere for 60 minutes at 550° C., so as to remove any damage caused during the dry-etching process. 
     Further, in a step shown in  FIG. 160 , a local interconnection pattern  57 A that electrically connects the contact hole  56 A and the contact hole  56 C is formed by a TiN film and a similar local interconnection patterns  57 B and  57 C are also formed on the contact holes  56 B and  56 D. 
     Further, in a process shown in  FIG. 17P , an SiO 2  film  58  is formed on the structure shown in FIG.  16 O. In a step shown in  FIG. 17Q , contact holes  58 A,  58 B and  58 C that expose the W plug  47 A, the local interconnection pattern  57 B and the W plug  47 C, respectively, are formed in the SiO 2  film  58 . 
     Further, in a process shown in  FIG. 17R , electrodes  59 A,  59 B and  59 C are formed in correspondence with the contact holes  58 A,  58 B and  58 C. 
     In the above-described steps, the steps of forming an interlayer insulation film and a local interconnection pattern may be repeated to form a multi-level metallization structure. 
     Further, the present invention is not limited to these embodiments, and variations and modifications may be made without departing from the scope of the present invention. 
     The present application is based on Japanese priority application No.2001-334576 filed on Nov. 1, 2001, the entire contents of which are hereby incorporated by reference.