Abstract:
The present invention provides an anti-reflection films for lithographic application on polysilicon containing substrate. A structure for improving lithography patterning in an integrated circuit comprises a polysilicon layer, a diaphanous layer located above the polysilicon layer, an anti-reflection layer located above the diaphanous layer, and then a photoresist layer located above the anti-reflection layer for patterning the integrated circuit pattern. The anti-reflection layer is preferably oxynitride.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to anti-reflection films for lithographic application, especially for polysilicon containing substrate. 
     2. Description of the Prior Art 
     Microcircuit fabrication requires that precisely controlled quantities of impurities be introduced into tiny regions of the silicon substrate. Subsequently, these regions must be interconnected to create components and VLSI circuits. The patterns that define such regions are created by a photolithographic process. As semiconductor devices become more highly integrated, the line width of VLSI circuits typically becomes scaled down. The semiconductor industry&#39;s drive toward integrated circuits with ever decreasing geometries, coupled with its pervasive use of highly reflective materials, such as polysilicon, aluminum, and metal suicides, has led to increased photolithographic patterning problems. Unexpected reflections from these underlying materials, during the photoresist-patterning step, result in the photoresist pattern being distorted. 
     This problem is further compounded when the photolithographic process is in the ultraviolet (UV) or deep ultraviolet (DUV) wavelength range. The patterns formed in the photoresist are easily compromised by the effects of uncontrolled reflections from the underlying materials due to the increased optical metallic nature of the underlying reflective materials at these wavelengths. Therefore, the fabrication of advanced integrated circuits with submicron geometries is limited. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide anti-reflection films for lithographic application on polysilicon containing substrate. 
     In one embodiment of the present invention, a structure for improving lithography patterning in an integrated circuit comprises a polysilicon layer, an optional diaphanous layer located above the polysilicon layer, an anti-reflection layer located above the diaphanous layer, and then a photoresist layer located above the diaphanous layer for patterning integrated circuit pattern. The anti-reflection layer is preferably oxynitride. 
     The method for forming a structure for improving lithography patterning in an integrated circuit comprises the steps of: providing a polysilicon layer, optionally forming a diaphanous layer over the polysilicon layer, forming an anti-reflection layer over the diaphanous layer, forming a photoresist layer on the anti-reflection layer, and then exposing a portion of the photoresist layer to electromagnetic radiation having a wavelength of less than 440 nanometers. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a cross section view of a first embodiment of the present invention; and 
     FIG. 2 is a cross section view of a second embodiment of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The present invention will be described in detail with reference to the drawings. The purpose of the present invention is to provide an anti-reflection film for lithographic application, especially for polysilicon containing substrate. The precise optical characteristics of the anti-reflection film, preferably formed of oxynitride (SiN x O y ), is dependent upon the recipe of the process for forming the oxynitride film. For example, the gas flow rate of SiH 4 , N 2 O, the deposition pressure, gas spacing (the distance between showerhead and susceptor), and the power of the plasma all affect the optical characteristics of the oxynitride film. 
     FIG. 1 shows a cross section view of a first embodiment of the present invention. A polysilicon layer  104  is formed on a substrate  102 . As can be appreciated by those skilled in the art, the formation of the polysilicon layer  104  atop the substrate  102  is often an intermediate step in the formation of integrated circuit. Specifically, the polysilicon layer  104  is typically used as a conductive layer. 
     An anti-reflection layer  108 , composed of oxynitride (SiN x O y ), is then formed on the polysilicon layer  104 . In this preferred embodiment, the oxynitride (SiN x O y ) is deposited by plasma-enhanced CVD method. Using SiH 4  and N 2 O as reactants, the flow rate of SiH 4  is approximately 35 to 75 sccm, the flow rate of N 2 O is approximately 75 to 115 sccm, the gas spacing is 375 to 490 mils, the deposition pressure is approximately 3.0 to 7.0 torr, and the power of plasma is at a range of 90 to 140 watt. Under these conditions, the resultant oxynitride (SiN x O y ) film has a refractive index in a range of 1.85 to 2.35, extinction coefficient in a range of 0.35 to 0.85, and a thickness in a range of 300 to 850 angstroms. The forgoing are the preferred ranges for the oxynitride film, and are measured at wavelength of 248 nanometers. It can be appreciated by those skilled in the art that the precise recipe for forming the oxynitride film may be varied, as long as the parameters of refractive index, extinction coefficient, and thickness are within the ranges set forth above. 
     Next, a photoresist layer is formed on the anti-reflection layer  108 . After formation, the photoresist layer is then patterned using conventional photolithographic techniques and this results in the formation of integrated circuit pattern  110   a.  Integrated circuit pattern  110   a  is preferably formed using electromagnetic radiation having an exposure wavelength of less than 440 nanometers. In this embodiment, the reflectivity of the underlying polysilicon layer  104  is in a range of 0.1 to 0.3 with the use of the oxynitride layer. 
     FIG. 2 shows a cross section view of a second embodiment of the present invention. A polysilicon layer  204  is formed on a substrate  202 . Next, a LPTEOS layer  206 , or any oxide layer including PSG or BPSG, is formed on the polysilicon layer  204  with a thickness of approximately 1000 to 8000 angstroms. Further, in this embodiment, the LPTEOS layer  206  is used as a buffer layer to prevent outdiffusion of dopants. Since the polysilicon layer  204  is often used as a gate of a MOSFET, a conductor of a capacitor, or a contact materials, the outdiffusion of doping materials is minimized by the deposition of the LPTEOS layer  206 . The deposition of LPTEOS also reduces the oxynitride thickness for the minimum reflectivity in the subsequent process. 
     An anti-reflection layer  210 , composed of oxynitride (SiN x O y ), is then formed on the oxide layer  206 . In this preferred embodiment, the oxynitride (SiN x O y ) is deposited by plasma-enhanced CVD method. Using SiH 4  and N 2 O as reactants, the flow rate of SiH 4  is approximately 35 to 75 sccm, the flow rate of N 2 O is approximately 75 to 115 sccm, the gas spacing is 375 to 490 mils, the deposition pressure is approximately 3.0 to 7.0 torr, and the power of plasma is about 90 to 140 watt. Under these conditions, the resultant oxynitride (SiN x O y ) film has a refractive index in a range of 1.85 to 2.35, extinction coefficient in a range of 0.35 to 0.85, and a thickness in a range of 230 to 700 angstroms. It can be appreciated by those skilled in the art that the precise recipe for forming the oxynitride film may be varied, as long as the parameters of refractive index, extinction coefficient, and thickness are within the ranges set forth above. 
     A photoresist layer is then formed on the anti-reflection layer  210 . After formation, the photoresist layer is then patterned using conventional photolithographic techniques and this results in the formation of integrated circuit pattern  212   a.  Integrated circuit pattern  212   a  is preferably formed using electromagnetic radiation having an exposure wavelength less than 440 nanometers. In this embodiment, the reflectivity is at a range of 0.1 to 0.3 with the use of the oxynitride layer  210 . 
     As is understood by a person skilled in the art, the foregoing preferred embodiments of the present invention are illustrations of the present invention rather than limiting of the present invention. It is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structure.