Abstract:
A FIFO circuit with a reduced number of buffers connected to output ports and thereby lowering parasitic capacitance. The FIFO circuit includes an input register for storing data therein supplied from a plurality of input ports. A shifter rearranges the data supplied from the input register and a shift register stores therein and shifts the data supplied from the shifter. A selector circuit selects either the data from the input register or the data from the shift register such that valid data fill places from a least significant side of the output ports. A control circuit controls the input register, the shift register, the shifter, and the selector circuit.

Description:
FIELD OF THE INVENTION 
     The present invention generally relates to FIFO circuits, and particularly relates to a FIFO circuit that serves as a data buffer to absorb data-speed changes between a data-supply side and a data-reception side. 
     BACKGROUND OF THE INVENTION 
     Conventionally, FIFO (first-in first-out) circuits are used as a buffer placed between a module for supplying data and a module for receiving data, and absorb data-speed changes between a data-supply side and a data-reception side, thereby achieving efficient data transmission. 
     A super scalar scheme is a technology that enhances performance of data processing units using FIFO circuits. This scheme achieves parallel processing of instructions. A FIFO circuit is used as a buffer that efficiently feeds instructions to a pipeline. In this configuration, the FIFO circuit is provided with extended ports in order to allow simultaneous access to a plurality of instructions to the extent commensurate with the degree of parallelism. A port is defined as a unit that permits simultaneous reading/writing of one memory cell. 
     In a data processing unit capable of simultaneous processing of four instructions, a FIFO circuit having four ports for data writing and four ports for data reading may be provided in an instruction fetch unit at a start of a pipeline. In this configuration, the FIFO circuit accumulates a stream of instructions that stalled at an instruction generation unit as they wait for available resources of the data processing unit, and serves to compensate for a gap created when an instruction cache fails to hit an instruction. 
     Japanese Patent Laid-open Application No.5-314758 discloses a FIFO circuit. This FIFO circuit includes a shift register that accumulates data received from a prior stage in synchronism with an input clock S 1 , a counter circuit that counts up in response to the input clock S 1  and counts down in response to an output clock, and an output selecting circuit that selects a stage of the shift register that corresponds to the count of the counter circuit and outputs an output of the selected stage. 
     This FIFO circuit has one input port and one output port. If a plurality of input ports and output ports are provided, a circuit configuration as shown in FIG. 1 may be conceived. 
     FIG. 1 is a circuit diagram of a FIFO circuit used in the super scalar scheme. In the figure, DI 0  through DI 3  denote input ports. Instruction data coming to the input port are supplied to shift registers  10  through  13 , respectively. Here, the shift registers  10  through  13  have a two-stage configuration. 
     The first stage of the shift register  10  is connected to output ports D 0  through D 3  via respective tri-state buffers provided in a selector circuit  14 . The second stage is connected to the output port D 0  via one tri-state buffer. The first stage of the shift register  11  is connected to the output ports D 0  through D 3  via respective tri-state buffers provided in the selector circuit  14 . The second stage is connected to the output ports D 0  and D 1  via respective tri-state buffers. 
     The first stage of the shift register  12  is connected to the output ports D 0  through D 3  via respective tri-state buffers provided in the selector circuit  14 . The second stage is connected to the output ports D 0 , D 1 , and D 2  via respective tri-state buffers. The first and second stages of the shift register  13  are each connected to the output ports D 0  through D 3  via respective tri-state buffers provided in the selector circuit  14 . 
     A control circuit  15  controls valid data positions of the shift registers  10  through  13 . Further., the control circuit  15  generates control signals EF 0  through EF 3  and FF 0  through FF 3  in accordance with input-request-number signals (number of data items) SI 0  through SI 3  and output-request number signals (number of data items) SO 0  through SO 3  as well as in accordance with the valid data positions. The control signals are used for controlling the tri-state buffers in the selector circuit  14 , so that a number of data items, corresponding to the output-request number, are output from the output ports D 0  through D 3 . Here, data is output from the output port D 0  when the output-request number is 1 and data is output from the output ports D 0  and D 1  when the output-request number is 2. By the same token, the output ports D 0  through D 2  output data when the output-request number is 3. 
     In the FIFO circuit of the related art, the output port D 0  is connected to eight tri-state buffers of the selector circuit  14 , and the output port D 1  is connected to seven tri-state buffers of the selector circuit  14 . Further, the output port D 2  is connected to six tri-state buffers of the selector circuit  14 , and the output port D 3  is connected to five tri-state buffers of the selector circuit  14 . 
     The greater the number of tri-state buffers connected to an output port, the greater the load, thus preventing high-speed operation. In an integrated circuit, signal transmission is affected by using high and low levels of signal-line potential as signal information. A voltage difference V is achieved by accumulating (or discharging) charge Q on a signal line having a capacitance C. In this case, these parameters are related as: 
     
       
           Q=CV   (1)  
       
     
     Charge Q is represented by an average electrical current Iave and time t as follows. 
     
       
           Q=Iavet   (2)  
       
     
     From the equations (1) and (2), the following relation is obtained. 
     
       
           dt=CdV/Iave   (3)  
       
     
     The equation (3) indicates that a time delay dt is related to a product of a parasitic capacitance C and a turn-on resistance of a transistor that is equal to a voltage difference dV divided by the average current Iave. Improvement in operational speed of integrated circuits has been attained by lowering the parasitic capacitance C via miniaturization of circuits, by lowering the voltage difference dV via use of a lower power voltage, and by increasing the average current Iave via use of low-resistance wiring material such as copper. The parasitic capacitance C is greatly affected by a technology used for manufacturing the integrated circuit and a structure of equal-voltage nodes. The larger the wires or the larger the number of connected transistors, the greater the parasitic capacitance C that needs to be charged or discharged. 
     As previously described, the FIFO circuit of the related art has a large number of tri-state buffers and thus a large number of transistors connected to each of the output ports D 0  through D 3 . As a result, it has a large parasitic capacitance C, which hinders high-speed operation. 
     Accordingly, the present invention is aimed at providing a FIFO circuit capable of high-speed operation by reducing the number of buffers connected to output ports and thereby lowering parasitic capacitance. 
     SUMMARY OF THE INVENTION 
     The invention is directed to a FIFO circuit having a plurality of input ports permitting parallel access thereto and a plurality of output ports. 
     The FIFO circuit has an input register which stores data supplied from the plurality of input ports. A shifter rearranges the data supplied from input register and a shift register stores and shifts the data supplied from the shifter. A selector circuit selects either the data supplied from the input register or the data supplied from the shift register such that valid data fill places of the output ports from a least significant side of the output ports. A control circuit manages the valid data of the input register and the shift register and controls the input register, shift register and selector circuit. 
     In this manner, the shifter rearranges the data supplied from the input register so as to shift the data inside the shift register. As a result, the present invention can reduce the number of buffers connecting the input register and the shift register to the plurality of output ports in the selector circuit, thereby lowering the parasitic capacitance of each output port so as to achieve high-speed operation. 
     Another embodiment is directed to a FIFO circuit having a plurality of input ports permitting parallel access thereto and a plurality of output ports. This FIFO circuit includes an input register which stores data supplied from the plurality of input ports. An intermediate register and a multiplexer that selects either the data supplied from the input register or data supplied from the intermediate register and supplies the selected data to the intermediate register. The intermediate register stores the data supplied from the multiplexer and feeds back the stored data to the multiplexer. A selector circuit selects either the data supplied from the input register or the data supplied from the shift register such that valid data fill places of the output ports from a least significant side of the output ports. A control circuit manages the valid data of the input register and the intermediate register, and controls the input register, multiplexer, intermediate register, and the selector circuit. 
     In this manner, the multiplexer rearranges data supplied from the input register and the intermediate register. Therefore, the present invention can reduce the number of buffers connecting the input register and the shift register to the plurality of output ports in the selector circuit. Thus lowering the parasitic capacitance of each output port so as to achieve high-speed operation. 
     Another embodiment is directed to a FIFO circuit, wherein the control circuit receives a requested number of input data items and a requested number of output data items from the exterior of the FIFO circuit. In this configuration, the control circuit refers to the requested numbers of data input items and data output items as well as the valid data positions of the input register and the intermediate register. Based on this information, the control circuit ensures that valid data fills the places of the output ports from the least significant side of the output ports. 
     The control circuit can receive an indication of valid data input and a requested number of output data items from the exterior of the FIFO circuit. In this configuration, the control circuit refers to the indication of valid data input, the requested number of data output items, and the valid data positions of the input register and the intermediate register and based on this information, can control that the valid data fill the places of the output ports from the least significant side of the output ports. 
     Another embodiment is directed to a FIFO circuit having a plurality of input ports permitting parallel access thereto and a plurality of output ports. This FIFO circuit includes an intermediate register and an input register which stores data supplied from the plurality of input ports. A multiplexer selects one of the data supplied from the plurality of input ports, the data supplied from said input register, data supplied from said intermediate register, and supplies the selected data to said intermediate register such that valid data fill places from a least significant side. The intermediate register stores the data supplied from the multiplexer and feeds back the stored data to the multiplexer. A selector circuit selects either the data supplied from the input register or the data supplied from the intermediate register such that the valid data fill places of the output ports from a least significant side of the output ports. A control circuit receives a requested number of data output items from the exterior of the FIFO circuit, manages the valid data of the input register and the intermediate register, and controls the input register, the multiplexer, the intermediate register, and the selector circuit. 
     In this manner, the multiplexer rearranges data supplied from the plurality of input ports as well as the input register and the intermediate register. Therefore, the present invention can reduce the number of buffers connecting the input register and the shift register to the plurality of output ports in the selector circuit, thereby lowering a parasitic capacitance of each output port. 
     The control circuit can include a pointer that indicates a register position where data is to be output first. In this configuration, the pointer indicates a data position in the input register where the data of this data position is to be output first according to a prescribed order of data output. Even when the previous input data remains in the input register because the intermediate register is full and when the next data is stored at a data position that is designated for earlier output before the data position indicated by the pointer, no mistake will be made to output the next data ahead of the pointer indicated data. This allows the next data to be entered before the input register becomes fully empty. This configuration can make efficient use of the input register, thereby making is possible to reduce the number of registers in the input register and allowing the circuit to be smaller in terms of area size. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram showing an example of a related-art FIFO circuit used in the super scalar scheme. 
     FIG. 2 is a block diagram of a first exemplary embodiment of a FIFO circuit used in the super scalar scheme according to the present invention. 
     FIGS. 3A-3F shows control-logic tables used by the control circuit  26 . 
     FIGS. 4A-4F shows control-logic tables used by the control circuit  26 . 
     FIG. 5 is a timing chart for explaining the operation of the FIFO circuit of the present invention. 
     FIG. 6 is a block diagram of a second exemplary embodiment of a FIFO circuit according to the present invention. 
     FIG. 7 is a block diagram of a third exemplary embodiment of a FIFO circuit according to the present invention. 
     FIG. 8 is a block diagram of an exemplary embodiment of the control circuit  47 . 
     FIG. 9 is a timing chart for explaining operation of the FIFO circuit of the present invention. 
     FIG. 10 is a block diagram of a fourth exemplary embodiment of a FIFO circuit according to the present invention. 
     FIG. 11 is a block diagram of an exemplary embodiment of the control circuit  77 . 
     FIGS. 12A-12E show control-logic tables used by the control circuit  77 . 
     FIGS. 13A-13E show control-logic tables used by the control circuit  77 . 
     FIG. 14 is a block diagram of a fifth exemplary embodiment of a FIFO circuit according to the present invention. 
     FIG. 15 is a block diagram of an exemplary embodiment of the control circuit  87 . 
     FIGS. 16A-16F show control-logic tables used by the control circuit  87 . 
     FIGS. 17A-17F show control-logic tables used by the control circuit  87 . 
     FIGS. 18A-18F show control-logic tables used by the control circuit  87 . 
     FIGS. 19A-19F show control-logic tables used by the control circuit  87 . 
     FIG. 20 is a timing chart for explaining operation of the FIFO circuit of the present invention. 
    
    
     DETAILED DESCRIPTION 
     FIG. 2 is a block diagram of a first embodiment of a FIFO circuit used in the super scalar scheme according to the present invention. In the figure, instruction data coming to the input ports DI 0  through DI 3  are supplied to registers R 5  through R 8 , respectively. The registers R 5  through R 8  together form an input register  18 , and each have a one-stage configuration. 
     The register R 5  is connected to a shifter  20 , and is connected to the output ports D 0  through D 3  via respective tri-state buffers B 1  through B 4  provided in a selector circuit  22 . The register R 6  is connected to the shifter  20 , and is connected to the output ports D 1  through D 3  via respective tri-state buffers B 5  through B 7  provided in the selector circuit  22 . 
     The register R 7  is connected to the shifter  20 , and is connected to the output ports D 2  and D 3  via respective tri-state buffers B 8  and B 9  provided in the selector circuit  22 . The register RB is connected to the shifter  20 , and is connected to the output port D 3  via a tri-state buffer B 10  provided in the selector circuit  22 . 
     The shifter  20  receives instruction data from the registers R 5  through R 8 , and supplies the instruction data to registers R 1  through R 4  after shifting the data or without any shifting of data. 
     The registers R 1  through R 4  together form a shift register  24 . Each of the registers R 1  through R 4  are connected to the output ports D 0  through D 3  respectively, via respective tri-state buffers B 1  through B 14  provided in the selector circuit  22 . 
     A control circuit  26  has an internal status (valid data positions) thereof initialized by a reset signal RST provided from an external source, and controls valid data positions of the registers R 1  through R 8 . Further, the control circuit  26  attends to various control functions such as control of writing of data in the registers R 5  through R 8 , control the shift operation of shifter  20 , control the shift operation of shift register  24 , and control the outputting operation of tri-state buffers B 1  through B 14  of selector circuit  22  based on input-request-number signals (number of data items) SI 0  through SI 3  and output-request-number signals (number of data items) SO 0  through SO 3  as well as based on the valid data positions. Through these controls, a number of data items, corresponding to the output-request number are output from the output ports D 0  through D 3 . Further, the control circuit  26  generates empty flags EFO through EF 3  and full flags FF 0  through FF 3 . 
     Here, data is output from the output port D 0  when the output-request number is 1, and data is output from the output ports D 0  and D 1  when the output-request number is 2. By the same token, the output ports D 0  through D 2  output data when the output-request number is 3, and the output ports D 0  through D 3  output data when the output-request number is 4. 
     Input instruction data is stored in the input register  18 . The instruction data of the input register  18  is stored in the shift register  24  such that the shifter  20  arranges the instruction data of the input register  18  after the valid instruction data of the shift register  24  in order to maintain correct data-output order between the current instruction data and the previous instruction data. When the shift register  24  becomes full, part of the instruction data having late data-output order is left in the shifter  20 . The instruction data is output to an exterior via the shift register  24  and the selector circuit  22  in the data-output order. 
     When the number of instruction data items stored in the shift register  24  is smaller than the number of the output ports, the instruction data stored in the input register  18  needs to be directed to the output ports by bypassing the shift register  24 . The selector circuit  22  selects instruction data from the input register  18  as many as the number of data items lacking in the shift register  24 , and outputs the selected instruction data while maintaining data continuity with the instruction data of the shift register  24 . 
     FIGS. 3A-3F and FIGS. 4A-4F show control-logic tables of the control circuit  26 . 
     FIG. 3A shows a control-logic table in the case of a mode #0 or a mode #4. The mode #0 corresponds to a case in which the number of valid data items is zero, and the registers R 1  through R 8  do not hold valid data. The mode #4 corresponds to a case in which the number of valid data items is 4, and the registers R 5  through R 8  hold valid instruction data. 
     The control-logic table has rows thereof corresponding to various output-request numbers S 0 . Entries in each row represent register numbers or input-port numbers that serve as data sources to supply instruction data. At the top of the table, register numbers and output-port numbers are shown, indicating data destination to receive the instruction data. As a short notation, register numbers 1 through 8 represent registers R 1  through R 8 , respectively. 
     The first row shows a case in which the output-request number SO (SO 0  through SO 3 ) is zero. In this row, a set of four entries in the field second from the left indicates that data of the registers R 5  through R 8  are supplied to and stored in the registers R 1  through R 4 , respectively. A set of four entries in the field third from the left indicates that instruction data of the input ports DI 0  through DI 3  are supplied to and stored in the registers R 5  through R 8 , respectively. A set of four entries in the field fourth from the left indicates that data of the registers R 5  through R 8  are supplied to and output from the output ports D 0  through D 3 , respectively. The rightmost field shows that the full flags FF that are zero are output. This means that the full flags FF 0  through FF 3  are all zero, so that the registers R 5  through R 8  all have no instruction data left therein. 
     The second row shows a case in which the output-request number SO (SO 0  through SO 3 ) is 1. This row indicates that data of the registers R 6 , R 7 , R 8 , and R 4  are supplied to and stored in the registers R 1  through R 4 , respectively, and that instruction data of the input ports DI 0  through DI 3  are supplied to and stored in the registers R 5  through R 8 , respectively. Further, it is indicated that data of the registers R 5  through R 8  are supplied to and output from the output ports D 0  through D 3 , respectively, and that the full flags FF being zero are output. 
     The third row shows a case in which the output-request number SO (SO 0  through SO 3 ) is 2. This row indicates that data of the registers R 7 , R 8 , R 3 , and R 4  are supplied to and stored in the registers R 1  through R 4 , respectively, and instruction data of the input ports DI 0  through DI 3  are supplied to and stored in the registers R 5  through R 8 , respectively. Further, it is indicated that data of registers R 5  through R 8  are supplied to and output from the output ports D 0  through D 3 , respectively, and that the full flags FF being zero are output. 
     The fourth row shows a case in which the output-request number SO (SO 0  through SO 3 ) is 3. This row indicates that data of the registers R 8 , R 2 , R 3 , and R 4  are supplied to and stored in registers R 1  through R 4 , respectively, and that instruction data of the input ports DI 0  through DI 3  are supplied to and stored in the registers R 5  through R 8 , respectively. Further, it is indicated that data of the registers R 5  through R 8  are supplied to and output from the output ports D 0  through D 3 , respectively, and that the full flags FF being zero are output. 
     The fifth row shows a case in which the output-request number SO (SO 0  through SO 3 ) is 4. This row indicates that data of the registers R 1 , R 2 , R 3 , and R 4  are supplied to and stored in the registers R 1  through R 4 , respectively, and that instruction data of the input ports DI 0  through DI 3  are supplied to and stored in the registers R 5  through R 8 , respectively. Further, the data of registers R 5  through R 8  are supplied to and output from the output ports D 0  through D 3 , respectively, and that the full flags FF being zero are output. 
     FIG. 3B shows a control-logic table in the case of a mode #1. The mode #1 corresponds to a case in which the number of valid data items is 1, and the register R 1  holds valid instruction data. The first row shows a case in which the output-request number SO (SO 0  through SO 3 ) is zero. This row indicates that data of the registers R 1 , R 5 , R 6 , and R 7  are supplied to and stored in the registers R 1  through R 4 , respectively, and that instruction data of the input ports DI 0  through DI 3  are supplied to and stored in the registers R 5  through R 8 , respectively. Also, it is indicated that data of the registers R 1 , R 5 , R 6 , and R 7  are supplied to and output from the output ports D 0  through D 3 , respectively, and that the full flags FF being zero are output. 
     The second row shows a case in which the output-request number SO (SO 0  through SO 3 ) is 1. This row indicates that data of the registers R 5 , R 6 , R 7 , and RB are supplied to and stored in the registers R 1  through R 4 , respectively, and that instruction data of the input ports DI 0  through DI 3  are supplied to and stored in the registers R 5  through R 8 , respectively. Further, it is indicated that data of the registers R 1 , R 5 , R 6 , and R 7  are supplied to and output from the output ports D 0  through D 3 , respectively, and that the full flags FF being zero are output. For further information about what the third  15  through fifth rows indicate, relevant entries in the table of FIG. 3B should be referred to. 
     FIG. 3C shows a control-logic table of mode #2. The mode #2 corresponds to a case in which the number of valid data items is 2, and the registers R 1  and R 2  hold valid instruction data. The  20  first row shows a case in which the output-request number SO (SO 0  through SO 3 ) is zero. This row indicates that data of the registers R 1 , R 2 , R 5 , and R 6  are supplied to and stored in the registers R 1  through R 4 , respectively, and that instruction data of the input ports DI 0  through DI 3  are supplied to and stored in the registers R 5  through R 8 , respectively. Also, it is indicated that data of the registers R 1 , R 2 , RS, and R 6  are supplied to and output from the output ports D 0  through D 3 , respectively, and the full figs FF being zero are output. 
     The second row shows when the output-request number SO (SO 0  through SO 3 ) is 1. This row indicates that data of the registers R 2 , R 5 , R 6 , and R 7  are supplied to and stored in the registers R 1  through R 4 , respectively, and that instruction data of the input ports DI 0  through DI 3  are supplied to and stored in the registers R 5  through R 8 , respectively. Further, it is indicated that data of the registers R 1 , R 2 , R 5 , and R 6  are supplied to and output from the output ports D 0  through D 3 , respectively, and that full flags FF being zero are output. For further information about what the third through fifth rows indicate, relevant entries in the table of FIG. 3C should be referred to. 
     FIG. 3D shows the control-logic table of mode #3. Mode #3 corresponds to a case in which the number of valid data items is 3, and the registers RI, R 2 , and R 3  hold valid instruction data. The first row shows when the output-request number SO (SO 0  through SO 3 ) is zero. This row indicates that data of the registers R 1 , R 2 , R 3 , and R 5  are supplied to and stored in the registers R 1  through R 4 , respectively, and instruction data of the input ports DI 0  through DI 3  are supplied to and stored in the registers R 5  through R 8 , respectively. Also, it is indicated that data of the registers R 1 , R 2 , R 3  and R 5  are supplied to and output from the output ports D 0  through D 3 , respectively, and that full flags FF being zero are output. 
     The second row shows a case in which the output-request number SO (SO 0  through SO 3 ) is 1. This row indicates that data of the registers R 2 , R 3 , R 5 , and R 6  are supplied to and stored in the registers R 1  through R 4 , respectively, and that instruction data of the input ports DI 0  through DI 3  are supplied to and stored in the registers R 5  through R 8 , respectively. Further, it is indicated that data of the registers R 1 , R 2 , R 3  and RS are supplied to and output from the output ports D 0  through D 3 , respectively, and that the full flags FF being zero are output. For further information about what the third through fifth rows indicate, relevant entries in the table of FIG. 3D should be referred to. 
     FIG. 3E shows a control-logic table of mode #4. Mode #4 corresponds to a case where the number of valid data items is 4, and the registers R 1 , R 2 , R 3  and R 4  hold valid instruction data. It should be noted that positions of the valid data items are different from those of the mode #4 shown in FIG.  3 A. The first row shows a case in which the output-request number SO (SO 0  through SO 3 ) is zero. This row indicates that data of the registers R 1 , R 2 , R 3  and R 4  are supplied to and stored in the registers R 1  through R 4 , respectively, and that instruction data of the input ports DI 0  through DI 3  are supplied to and stored in the registers R 5  through R 8 , respectively. Also, it is indicated that data of the registers R 1 , R 2 , R 3  and R 4  are supplied to and output from the output ports D 0  through D 3 , respectively, and that full flags FF being zero are output. 
     The second row shows a case in which the output-request number SO (SO 0  through SO 3 ) is 1. This row indicates that data of the registers R 2 , R 3 , R 4  and R 5  are supplied to and stored in the registers R 1  through R 4 , respectively, and that instruction data of the input ports DI 0  through DI 3  are supplied to and stored in the registers R 5  through R 8 , respectively. Further, it is indicated that data of the registers R 1 , R 2 , R 3  and R 4  are supplied to and output from the output ports D 0  through D 3 , respectively, and that full flags FF being zero are output. For further information about what the third through fifth rows indicate, relevant entries in the table of FIG. 3E should be referred to. 
     FIG. 3F shows a control-logic table of mode #5. Mode #5 corresponds to a case in which the number of valid data items is 5, and the registers R 1 , R 2 , R 3 , R 4 , and R 8  hold valid instruction data. The first row shows a case when the output-request number SO (SO 0  through SO 3 ) is zero. This row indicates that data of the registers R 1 , R 2 , R 3  and R 4  are supplied to and stored in the registers R 1  through R 4 , respectively, and that instruction data of the input ports DI 0  through DI 2  and the register R 8  are supplied to and stored in the registers R 5  through RB, respectively. Also, it is indicated that data of the registers R 1 , R 2 , R 3  and R 4  are supplied to and output from the output ports D 0  through D 3 , respectively, and that full flag FF being one (i.e., the full flag FF 3  being one indicating that the register R 8  is full) is output. 
     The second row shows when the output-request number SO (SO 0  through SO 3 ) is 1. This row indicates that data of the registers R 2 , R 3 , R 4 , and R 8  are supplied to and stored in the registers R 1  through R 4 , respectively, and that instruction data of the input ports DI 0  through DI 3  are supplied to and stored in the registers R 5  through R 8 , respectively. Further, it is indicated that data of the registers R 1 , R 2 , R 3  and R 4  are supplied to and output from the output ports D 0  through D 3 , respectively, and that the full flags FF being zero are output. For further information about what the third through fifth rows indicate, relevant entries in the table of FIG. 3F should be referred to. 
     FIG. 4A shows a control-logic table of mode #6. The mode #6 corresponds to a case in which the number of valid data items is 6, and the registers R 1 , R 2 , R 3 , R 4 , R 7  and R 8  hold valid instruction data. The first row shows a case in which the output-request number SO (SO 0  through SO 3 ) is zero. This row indicates that data of the registers R 1 , R 2 , R 3  and R 4  are supplied to and stored in the registers R 1  through R 4 , respectively, and that instruction data of the input ports DI 0  and DI 1  and the registers R 7  and R 8  are supplied to and stored in the registers R 5  through R 8 , respectively. Also, it is indicated that data of the registers R 1 , R 2 , R 3  and R 4  are supplied to and output from the output ports D 0  through D 3 , respectively, and that full flags FF being one (i.e., the full flags FF 2  and FF 3  being one indicating that the registers R 7  and R 8  are full) are output. 
     The second row shows a case in which the output-request number SO (SO 0  through SO 3 ) is 1. This row indicates that data of registers R 2 , R 3 , R 4  and R 7  are supplied to and stored in registers R 1  through R 4 , respectively, and that instruction data of the input ports DI 0  through DI 2  and the register R 8  are supplied to and stored in the registers R 5  through R 8 , respectively. Further, it is indicated that data of registers R 1 , R 2 , R 3  and R 4  are supplied to and output from the output ports D 0  through D 3 , respectively, and that full flag FF being one (i.e., the full flag FF 3  being one indicating that the register R 8  is full) is output. For further information about what the third through fifth rows indicate, relevant entries in the table of FIG. 4A should be referred to. 
     FIG. 4B shows a control-logic table of mode #7. Mode #7 corresponds to a case in which the number of valid data items is 7, and the registers R 1 , R 2 , R 3 , R 4 , R 6 , R 7  and R 8  hold valid instruction data. The first row shows a case when the output-request number SO (SO 0  through SO 3 ) is zero. This row indicates that data of registers R 1 , R 2 , R 3  and R 4  are supplied to and stored in registers R 1  through R 4 , respectively, and that instruction data of the input port DI 0  and the registers R 6  through R 8  are supplied to and stored in the registers R 5  through R 8 , respectively. Also, it is indicated that data of registers R 1 , R 2 , R 3  and R 4  are supplied to and output from the output ports D 0  through D 3 , respectively, and full flags FF being one (i.e., the full flags FF 1  through FF 3  being one indicating that the registers R 6  through R 8  are full) are output. 
     The second row shows a case in which the output-request number SO (SO 0  through SO 3 ) is 1. This row indicates that data of the registers R 2 , R 3 , R 4 , and R 6  are supplied to and stored in registers R 1  through R 4 , respectively, and instruction data of the input ports DI 0  and DI 1  and registers R 7  and RB are supplied to and stored in registers R 5  through R 8 , respectively. Further, it is indicated that data of registers R 1 , R 2 , R 3  and R 4  are supplied to and output from the output ports D 0  through D 3 , respectively, and that full flags FF being one (i.e., the full flags FF 2  and FF 3  being one indicating that the registers R 7  and R 8  are full) are output. For further information about what the third through fifth rows indicate, relevant entries in the table of FIG. 4B should be referred to. 
     FIG. 4C shows a control-logic table in the case of a mode #8. Mode #8 corresponds to a case in which the number of valid data items is 8, and the registers R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7  and R 8  hold valid instruction data. The first row shows a case in which the output-request number SO (SO 0  through SO 3 ) is zero. This row indicates that data of the registers R 1 , R 2 , R 3  and R 4  are supplied to and stored in the registers R 1  through R 4 , respectively, and that instruction data of the registers R 5  through R 8  are supplied to and stored in the registers R 5  through R 8 , respectively. Also, it is indicated that data of the registers R 1 , R 2 , R 3  and P 4  are supplied to and output from the output ports D 0  through D 3 , respectively, and that full flags FF being one (i.e., full flags FF 0  through FF 3  being one indicating that registers RS through R 8  are full) are output. 
     The second row shows a case in which the output-request number SO (SO 0  through SO 3 ) is 1. This row indicates that data of registers R 2 , R 3 , R 4  and R 5  are supplied to and stored in registers R 1  through R 4 , respectively, and that instruction data of the input port DI 0  and the registers R 6  through P 8  are supplied to and stored in the registers R 5  through R 8 , respectively. Further, it is indicated that data of registers R 1 , R 2 , R 3  and R 4  are supplied to and output from the output ports D 0  through D 3 , respectively, and that full flags FF being one (i.e., full flags FF 1  through FF 3  being one indicating that registers R 6  through R 8  are full) are output. For further information about what the third through fifth rows indicate, relevant entries in the table of FIG. 4C should be referred to. 
     FIG. 4D shows a control-logic table of mode #5. Mode #5 corresponds to a case in which the number of valid data items is 5, and the registers R 1 , R 5 , R 6 , R 7  and R 8  hold valid instruction data. It should be noted that the positions of valid data items are different from those of the mode #5 shown in FIG.  3 F. The first row shows a case in which the output-request number SO (SO 0  through SO 3 ) is zero. This row indicates that data of registers R 1 , R 5 , R 6  and R 7  are supplied to and stored in the registers R 1  through R 4 , respectively, and that instruction data of the input ports DI 0  through DI 2  and the register R 8  are supplied to and stored in the registers R 5  through R 8 , respectively. Also, it is indicated that data of the registers R 1 , R 5 , R 6  and R 7  are supplied to and output from the output ports D 0  through D 3 , respectively, and that full flag FF being one (i.e., full flag FF 3  being one indicating that the register R 8  is full) is output. 
     The second row shows a case in which the output-request number SO (SO 0  through SO 3 ) is 1. This row indicates that data of the registers R 5 , R 6 , R 7 , and R 8  are supplied to and stored in the registers R 1  through R 4 , respectively, and that instruction data of the input ports DI 0  through DI 3  are supplied to and stored in the registers R 5  through R 8 , respectively. Further, it is indicated that data of the registers R 1 , R 5 , R 6 , and R 7  are supplied to and output from the output ports D 0  through D 3 , respectively, and that the full flags FF being zero are output. For further information about what the third through fifth rows indicate, relevant entries in the table of FIG. 4D should be referred to. 
     FIG. 4E shows a control-logic table of a mode #6. The mode #6 corresponds to a case in which the number of valid data items is 6, and the registers R 1 , R 2 , R 5 , R 6 , R 7 , and R 8  hold valid instruction data. It should be noted that the positions of valid data items are different from those of the mode #6 shown in FIG.  4 A. The first row shows a case in which the output-request number SO (SO 0  through SO 3 ) is zero. This row indicates that data of the registers R 1 , R 2 , R 5 , and R 6  are supplied to and stored in the registers R 1  through R 4 , respectively, and that instruction data of the input ports DI 0  and DI 1  and the registers R 7  and R 8  are supplied to and stored in the registers R 5  through R 8 , respectively. Also, it is indicated that data of the registers R 1 , R 2 , R 5 , and R 6  are supplied to and output from the output ports D 0  through D 3 , respectively, and that the full flags FF being one (i.e., full flags FF 2  and FF 3  being one indicating that registers R 7  and R 8  are full) are output. 
     The second row shows a case in which the output-request number SO (SO 0  through SO 3 ) is 1. This row indicates that data of the registers R 2 , R 5 , R 6 , and R 7  are supplied to and stored in the registers R 1  through R 4 , respectively, and that instruction data of the input ports DI 0  through DI 2  and the register R 8  are supplied to and stored in the registers R 5  through R 8 , respectively. Further, it is indicated that data of the registers R 1 , R 2 , RS, and R 6  are supplied to and output from the output ports D 0  through D 3 , respectively, and that the full flag FF being one (i.e., full flag FF 3  being one indicating that the register R 8  is full) is output. For further information about what the third through fifth rows indicate, relevant entries in the table of FIG. 4E should be referred to. 
     FIG. 4F shows a control-logic table in the case of mode #7. The mode #7 corresponds to a case in which the number of valid data items is 7, and the registers R 1 , R 2 , R 3 , RS, R 6 , R 7 , and R 8  hold valid instruction data. It should be noted that the positions of valid data items are different from those of the mode #7 shown in FIG.  4 B. The first row shows a case in which the output-request number SO (SO 0  through SO 3 ) is zero. This row indicates that data of the registers R 1 , R 2 , R 3 , and R 5  are supplied to and stored in the registers R 1  through R 4 , respectively, and that instruction data of the input port DI 0  and the registers R 6  through R 8  are supplied to and stored in the registers R 5  through R 8 , respectively. Also, it is indicated that data of the registers R 1 , R 2 , R 3 , and R 5  are supplied to and output from the output ports D 0  through D 3 , respectively, and that the full flags FF being one (i.e., full flags FF 1  through FF 3  being one indicating that the registers R 6  through R 8  are full) are output. 
     The second row shows a case in which the output-request number SO (SO 0  through SO 3 ) is 1. This row indicates that data of the registers R 2 , R 3 , R 5 , and R 6  are supplied to and stored in the registers R 1  through R 4 , respectively, and that instruction data of the input ports DI 0  and DI 1  and the registers R 7  and R 8  are supplied to and stored in the registers R 5  through RB, respectively. Further, it is indicated that data of the registers R 1 , R 2 , R 3 , and R 5  are supplied to and output from the output ports D 0  through D 3 , respectively, and that the full flags FF being one (i.e., full flags FF 2  and FF 3  being one indicating that the registers R 7  and R 8  are full) are output. For further information about what the third through fifth rows indicate, relevant entries in the table of FIG. 4F should be referred to. 
     Following describes the operation of the FIFO circuit of FIG. 2 with respect to timing charts of FIG.  5 . 
     As shown in a phase  1  of FIG. 5, initial settings are such that no valid data is held. In this case, empty flags EF 0  through EF 3  are all “1” so that the control-logic table of the mode #0 shown in FIG. 3A will be selected. Further, the input-request number is 4 (SI=1111), and the output-request number is 1 (SO=1000). In this case, the control circuit  26  controls in accordance with the conditions set forth in the second row of the control-logic table of the mode #0. 
     At a rising edge of a clock signal clock, instruction data (data 1 through 4) supplied to the input ports DI 0  through DI 3  are stored in the registers R 5  through R 8 . The instruction data of the registers R 5  through R 8  are then supplied to the output ports D 0  through D 3 , and the instruction data (data 1) is output from the output port D 0  in accordance with the output-request number of 1. The selector circuit  22  is always controlled in advance to select the number of instruction data equal to the output-request number. Namely, no instruction data is output from the output ports D 1  through D 3  during phase  1 . 
     Then, the operation enters a phase  2  in response to a rising edge of the clock signal clock. Since the instruction data are stored in the registers R 5  through RB, the control-logic table of mode #4 (valid data positions: R 5 , R 6 , R 7 , and R 8 ) shown in FIG. 3A is referred to. With the output-request number being one (SO=1000), the second row of the table is selected. As is prescribed in the second row, the contents of the registers R 6  through R 8  are moved to the registers R 1  through R 3 , respectively, via the shifter  20 . In the middle of the phase  2 , external conditions are changed, with the new conditions being the output-request number is 2 (SO=1100), and four instruction data items (data 5 through 8) are supplied as input data. 
     In response to a rising edge of the clock signal clock, the operation enters a phase  3 . Since valid instruction data are stored in the registers R 1 , R 2 , R 3 , R 5 , R 6 , R 7 , and R 8 , the control-logic table of mode #7 shown in FIG. 4F is referred to. With the output-request number being  2 , the third row of the control-logic table of mode #7 is consulted, so that the contents of the registers R 1  and R 2  are output from the output ports D 0  and D 1  respectively. Further, the data of the register R 3  is moved to the register R 1 , and the data of the registers R 5  through R 7  are moved to the registers R 2  through R 4 , respectively, via the shifter  20 . The data of the register R 8  stays therein. In this embodiment, a data-output order is determined according to the register numbers. Because of this limitation, when the register R 5  receives next instruction data, the contents of the register R 5  is regarded as having been input before the contents of the register R 8 . In order to avoid this, the full flag FF being one is output to an exterior of the circuit, thereby invalidating the input-request-number signals SI 0  through SI 3  that are input to the circuit. After this, the output-request number is 2 (SO=1100), and four instruction data items (data 9 through 12) are input. In response to a rising edge of the clock signal clock, the operation enters a phase  4 . Since valid instruction data are stored in the registers R 1 , R 2 , R 3 , R 4 , and R 8 , the control-logic table of mode #5 shown in FIG. 3F is referred to. With the output-request number being 2, the third row of the control-logic table of mode #5 is consulted, so that the contents of the registers R 1  and R 2  are output from the output ports D 0  and D 1 , respectively. Further, the data of the registers R 3 , R 4 , and R 8  are moved to the registers R 1  through R 3 , respectively. The full flags FF in this case are zero. 
     In response to a rising edge of the clock signal clock, the operation enters a phase  5 . Now that the full flags FF are zero, the registers R 5  through RB store therein instruction data (data 9 through 12) supplied to the input ports DI 0  through DI 3  wherein these data were stopped from being stored during the phase  4 . Since valid instruction data are stored in the registers R 1 , R 2 , R 3 , R 5 , R 6 , R 7 , and R 8 , the control-logic table of mode #7 shown in FIG. 4F is referred to. With the output-request number being 4 (SO=1111) at this time, the fifth row of the control-logic table of mode #7 is consulted, so that the instruction data (data 6, 7, 8, 9) of the registers R 1 , R 2 , R 3 , and R 5  are output from the output ports D 0 , D 1 , D 2 , and D 3 , respectively. Further, the data of the registers R 6 , R 7 , R 8 , and R 4  (R 4  being a dummy) are moved to the registers R 1  through R 4 , respectively. The full flags FF in this case are zero. 
     Thereafter, the input-request number becomes zero (DI=0000), and the output-request number remains to be 4 (SO=1111). As the operation enters a phase  6  in response to a rising edge of the clock signal clock, the control circuit  26  stores control data therein indicative of an invalid status of the registers R 5  through R 8 . Since valid instruction data are stored in the registers R 1 , R 2 , and R 3 , the control-logic table of mode #3 shown in FIG. 3D is consulted. With the output-request number being 4, the fifth row of the control-logic table of mode #3 is referred to, and the contents of the registers R 1 , R 2 , R 3 , and R 4  are output from the output ports D 0 , D 1 , D 2 , and D 3 , respectively. In this case, however, empty flags EF 0 , EF 1 , and EF 2  being zero are output, indicating that the output data of the output ports D 0 , D 1 , and D 2  are valid. Further, the empty flag EF 3  being one is output, indicating that the output data of the output port D 3  is invalid. 
     In this embodiment, the number of tri-state buffers connected to the input port D 0  is 2, and the number of tri-state buffers connected to the input port D 1  is 3. The number of tri-state buffers connected to the input port D 2  is 4 and the number of tri-state buffers connected to the input port D 3  is 5. This is a significant reduction in the numbers of tri-state buffers compared to the related-art configuration. 
     In this manner, the shifter  20  rearranges data supplied from the input register  18  so as to shift the data inside the shift register  24 . Thus, the present invention can reduce the number of tri-state buffers connecting the input register  18  and the shift register  24  to the output ports D 0  through D 3  inside the selector circuit  22 . As a result, parasitic capacitance of each of the output ports D 0  through D 3  is lowered to help to achieve high-speed operation. 
     FIG. 6 is a block diagram of another exemplary embodiment of a FIFO circuit according to the preset invention. In the figure, the same elements as those of FIG. 2 are referred to by the same numerals. In FIG. 6, instruction data coming to the input ports DI 0  through DI 3  are supplied to the registers R 5  through R 8 , respectively. The registers R 5  through R 8  together form the input register  18 , and each has a one-stage configuration. 
     The register R 5  is connected to a multiplexer  30 , and is connected to the output ports D 0  through D 3  via the respective tri-state buffers B 1  through B 4  provided in the selector circuit  22 . The register R 6  is connected to the multiplexer  30 , and is connected to the output ports D 1  through D 3  via the respective tri-state buffers B 5  through B 7  provided in the selector circuit  22 . 
     The register R 7  is connected to the multiplexer  30 , and is connected to the output ports D 2  and D 3  via the respective tri-state buffers B 8  and B 9  provided in the selector circuit  22 . The register R 8  is connected to the multiplexer  30 , and is connected to the output port D 3  via the tri-state buffer B 10  provided in the selector circuit  22 . 
     The multiplexer  30  receives instruction data from the registers R 5  through R 8  as well as from registers R 1  through R 4  of a register  34 , and supplies the instruction data to the registers R 1  through R 4  after selecting the data. The registers R 1  through R 4  together forming the register  34  are each connected to the output ports D 0  through D 3 , respectively, via the respective tri-state buffers B 11  through B 14  provided in the selector circuit  22 . 
     The control circuit  26  has an internal status (valid data positions) thereof initialized by a reset signal RST provided from an external source, and controls valid data positions of the registers R 1  through R 8 . Further, the control circuit  26  controls the writing of data in the registers R 5  through R 8 , the shift operation of the multiplexer  30 , the shift operation of the register  34 , and the outputting operation of the tri-state buffers B 1  through B 14  of the selector circuit  22  based on input-request-number signals (number of data items) SI 0  through SI 3  and output-request-number signals (number of data items) SO 0  through SO 3  as well as based on the valid data positions. Through these controls, data items as many as the output-request number are output from the output ports D 0  through D 3 . Further, the control circuit  26  generates empty flags EF 0  through EF 3  and full flags FF 0  through FF 3 . 
     Here, data is output from the output port D 0  when the output-request number is 1, and data is output from the output ports D 0  and D 1  when the output-request number is 2. By the same token, the output ports D 0  through D 2  output data when the output-request number is 3 and the output ports D 0  through D 3  output data when the output-request number is 4. 
     In this exemplary embodiment, the multiplexer  30  and the register  34  provide the same operation as the shifter  20  and the register  34  of first exemplary embodiment. Because of this, the control operation of the control circuit  26  is identical to that of the first exemplary embodiment, and is performed based on the control-logic tables shown in FIGS. 3A-3F and FIGS. 4A-4F. 
     In this exemplary embodiment, like the first exemplary embodiment, the number of tri-state buffers connected to the input port D 0  is 2, and the number of tri-state buffers connected to the input port D 1  is 3. The number of tri-state buffers connected to the input port D 2  is 4 and the number of tri-state buffers connected to the input port D 3  is 5. This is a significant reduction in the numbers of tri-state buffers compared to the related-art configuration. 
     In this manner, the multiplexer  30  rearranges data supplied from the input register  18  and the register  34 . Thus, the present invention can reduce the number of buffers connecting the input register  18  and the register  34  to the output ports D 0  through D 3  inside the selector circuit  22 . As a result, parasitic capacitance of each of the output ports D 0  through D 3  is lowered, helping to achieve high-speed operation. 
     FIG. 7 is a block diagram of a third exemplary embodiment of a FIFO circuit according to the present invention. In the figure, the same elements as those of FIG. 6 are referred to by the same numerals. In FIG. 7, instruction data coming to the input ports DI 0  through DI 3  are supplied to the registers R 5  through R 8 , respectively. The registers R 5  through R 8  together form the input register  18 , and each has a one-stage configuration. 
     Each of the registers R 5  through R 8  includes a D flip-flop  40  for latching data, a buffer  41  for looping back an output of the D flip-flop  40 , and a multiplexer  42  for selecting data from the input port or data from the buffer  41 . 
     The register R 5  is connected to multiplexers  30   a  through  30   d  of the multiplexer  30 , and is connected to the output ports DO through D 3  via respective demultiplexers  43  through  46  together forming the selector circuit  22 . The register R 6  is connected to the multiplexers  30   a  through  30   d  of the multiplexer  30 , and is connected to the output ports D 1  through D 3  via the respective multiplexers  33  through  36  of the selector circuit  22 . 
     The register R 7  is connected to the multiplexers  30   a  through  30   d  of the multiplexer  30 , and is connected to the output ports D 2  and D 3  via the respective demultiplexers  45  and  46  of the selector circuit  22 . The register R 8  is connected to the multiplexers  30   a  through  30   d  of the multiplexer  30 , and is connected to the output port D 3  via the multiplexer  46  of the selector circuit  22 . 
     The multiplexer  30  is comprised of the multiplexers  30   a  through  30   d  corresponding to the respective registers R 1  through R 4  of the register  34 . The multiplexer  30  selects instruction data supplied from the registers R 5  through R 8  and the registers R 1  through R 4  of the register  34 , and supplies the selected data to the registers R 1  through R 4  of the register  34 . The registers R 1  through R 4  of the register  34  are connected to the output ports D 0  through D 3 , respectively, via the respective multiplexers  43  through  46  provided in the selector circuit  22 . Each of the multiplexers  43  through  46  selects a signal under the control of a control circuit  47 , and outputs the selected signal from a corresponding one of the output ports D 0  through D 3 . Control-logic tables that the control circuit  47  uses are the same as those of FIGS. 3A-3F and FIGS. 4A-4F. Namely, the multiplexer  42  of the registers R 5  through R 8  makes a selection according to entries provided in the field third form the left in a relevant table. Further, the multiplexers  30   a  through  30   d  make a selection according to entries provided in the field second from the left, and the multiplexers  43  through  46  make a selection according to entries provided in the field fourth from the left. 
     FIG. 8 is a block diagram of an exemplary embodiment of the control circuit  47 . In the figure, a signal valid in, which indicates a valid status of input data when it is 1, is supplied to an AND circuit  49 . The AND circuit  49  performs an AND operation between the signal valid_in and an inverse of a full flag FF that is supplied from a control-signal-generation unit  48 . An output of the AND circuit  49  is supplied to registers R 15  through R 18 , which have a configuration parallel to that of the registers R 5  through R 8 . Each of the registers R 15  through R 18  includes a D flip-flop  60  for latching data, a buffer  61  for looping back an output of the D flip-flop  60 , and a multiplexer  62  for selecting data from an input port or data from the buffer  61 . 
     The register R 15  is connected to multiplexers  50   a  through  50   d  of a multiplexer  50 , and is connected to multiplexers  53  through  56  together forming a selector circuit. The register R 16  is connected to the multiplexers  50   a  through  50   d , and is connected to the three multiplexers  54  through  56 . The register R 17  is connected to the multiplexers  50   a  through  50   d , and is connected to the two multiplexers  55  and  56 . The register R 18  is connected to the multiplexers  50   a  through  50   d , and is connected to the multiplexer  56 . 
     The multiplexer  50  is comprised of the multiplexers  50   a  through  50   d  corresponding to respective registers R 11  through R 14 . The multiplexer  50  selects instruction data supplied from the registers R 15  through R 18  and the registers R 11  through R 14 , and supplies the selected data to the registers R 11  through R 14 . The registers R 11  through R 14  are connected to the respective multiplexers  53  through  56 . Each of the multiplexers  53  through  56  selects a signal under the control of the control-signal-generation unit  48 , and outputs a corresponding one of valid-data-position signals valid 0  through valid 3 . Control-logic tables that the control-signal-generation unit  48  uses are the same as those of FIGS. 3A-3F and FIGS. 4A-4F. Namely, the multiplexer  62  of the registers R 15  through R 18  makes a selection according to entries provided in the field third from the left in a relevant table. Further, the multiplexers  50   a  through  50   d  make a selection according to entries provided in the field second from the left, and the multiplexers  53  through  56  make a selection according to entries provided in the field fourth from the left. 
     Following describes the operation of the FIFO circuit of FIG. 7 with reference to the timing chart of FIG.  9 . 
     As illustrated in a phase  1  of FIG. 9, initial settings are such that no valid data is held. In this case, valid 0  through valid 3  are all zero, so that the control-logic table of the mode #0 shown in FIG. 3A will be selected. Further, the output-request number is 1 (SO=1000), so that the control circuit attends to control in accordance with the conditions set forth in the second row of the control-logic table of the mode #0. 
     At a rising edge of a clock signal clock after the signal valid_in indicative of valid data input becomes 1, instruction data (data 1 through 4) supplied to the input ports DI 0  through DI 3  are stored in the registers R 5  through RB. The instruction data of the registers R 5  through R 8  are then supplied to the output ports D 0  through D 3 , and the instruction data (data 1) is output from the output port D 0  in accordance with the output-request number of 1. The selector circuit is always controlled in advance to select the number of instruction data items equal to the output-request number. Namely, no instruction data is output from the output ports D 1  through D 3  during the phase  1 . 
     Then, the operation enters a phase  2  in response to a rising edge of the clock signal clock. Since the instruction data are stored in the registers R 5  through R 8 , the control-logic table of the mode #4 (valid data positions: R 5 , R 6 , R 7 , and R 8 ) shown in FIG. 3A is referred to. With the output-request number being one (SO=1000), the second row of the table is selected. As is illustrated in the second row, the contents of the registers R 6  through R 8  are moved to the registers R 1  through R 3 , respectively. In the middle of the phase  2 , external conditions are changed, with the new conditions being that the output-request number is 2 (SO=1100), and four instruction data items (data 5 through 8) are supplied as input data. 
     In response to a rising edge of the clock signal clock, the operation enters a phase  3 . Since valid instruction data are stored in the registers R 1 , R 2 , R 3 , R 5 , R 6 , R 7 , and R 8 , the control-logic table of the mode #7 shown in FIG. 4F is referred to. With the output-request number being 2, the third row of the control-logic table of mode #7 is consulted, so that the contents of the registers R 1  and R 2  are output from the output ports D 0  and D 1 , respectively. Further, the data of the register R 3  is moved to the register R 1  and the data of the registers R 5  through R 7  are moved to the registers R 2  through R 4 , respectively. The data in the register R 8  stays therein. In this embodiment, a data-output order is determined according to the register numbers. Because of this limitation, when the register R 5  receives next instruction data, the contents of the register R 5  is regarded as having been input before the contents of the register R 8 . In order to avoid this, the full flag FF being one is output to an exterior of the circuit, thereby invalidating the valid-data-indication signal valid in. 
     After this, the output-request number is 2 (SO=1100), and four instruction data items (data 9 through 12) are input. In response to a rising edge of the clock signal clock, the operation enters a phase  4 . Since valid instruction data are stored in the registers R 1 , R 2 , R 3 , R 4 , and R 8 , the control-logic table of the mode #5 shown in FIG. 3F is referred to. With the output-request number being 2, the third row of the control-logic table of the mode #5 is consulted, so that the contents of the registers R 1  and R 2  are output from the output ports D 0  and D 1 , respectively. Further, the data of the registers R 3 , R 4 , and R 8  are moved to the registers R 1  through R 3 , respectively. The full flags FF in this case are zero. 
     In response to a rising edge of the clock signal clock, the operation enters a phase  5 . Now that the full flags FF are zero, the registers R 5  through R 8  store therein instruction data (data 9 through 12) supplied to the input ports DI 0  through DI 3  wherein these data were stopped from being stored during the phase  4 . Since valid instruction data are stored in the registers R 1 , R 2 , R 3 , R 5 , R 6 , R 7 , and R 8 , the control-logic table of the mode #7 shown in FIG. 4F is referred to. With the output-request number being 4 (SO=1111) at this time, the fifth row of the control-logic table of the mode #7 is consulted, so that the instruction data (data 6, 7, 8, 9) of the registers R 1 , R 2 , R 3 , and R 5  are output from the output ports D 0 , D 1 , D 2 , and D 3 , respectively. Further, the data of the registers R 6 , R 7 , R 8 , and R 4  (R 4  being a dummy) are moved to the registers R 1  through R 4 , respectively. The full flags FF in this case are zero. 
     Thereafter, the valid-input-indication signal valid_in becomes zero, and the output-request number remains 4 (SO=1111). As the operation enters a phase  6  in response to a rising edge of the clock signal clock, the control circuit stores control data therein indicative of an invalid status of the registers R 5  through R 8 . Since valid instruction data are stored in the registers R 1 , R 2 , and R 3 , the control-logic table of the mode #3 shown in FIG. 3D is consulted. With the output-request number being 4, the fifth row of the control-logic table of the mode #3 is referred to, and the contents of the registers R 1 , R 2 , R 3 , and R 4  are output from the output ports D 0 , D 1 , D 2 , and D 3 , respectively. In this case, however, the signals valid 0 , valid 1 , and valid 2  being one are output, indicating that the output data of the output ports D 0 , D 1 , and D 2  are valid. Further, the signal valid 3  being zero is output, indicating that the output data of the output port D 3  is invalid. 
     In this third exemplary embodiment, like the second exemplary embodiment, the multiplexer  30  rearranges and shifts data supplied from the input register  18 . Thus, the present invention can reduce the number of buffers connecting the input register  18  and the register  34  to the output ports D 0  through D 3  inside the selector circuit  22 . As a result, parasitic capacitance of each of the output ports D 0  through D 3  is lowered, helping to achieve high-speed operation. 
     FIG. 10 is a block diagram of a fourth exemplary embodiment of a FIFO circuit according to the present invention. In the figure, the same elements as those of FIG. 7 are referred to by the same numerals. In FIG. 10, instruction data coming to the input ports DI 0  through DI 3  are supplied to the registers R 5  through R 8 , respectively. The registers R 5  through R 8  together form the input register  18  each has a one-stage configuration. The instruction data input to the input port DI 0  is supplied to multiplexers  70   b  through  70   d  that form part of a multiplexer  70 . Further, the instruction data of the input port DI 1  is supplied to the multiplexers  70   c  and  70   d , and the instruction data of the input port DI 2  is supplied to the multiplexer  70   d.    
     Each of the registers R 5  through R 8  includes the D flipflop  40  for latching data, the buffer  41  for looping back an output of the D flip-flop  40 , and the multiplexer  42  for selecting data from the input port or data from the buffer  41 . The register R 5  is connected to the multiplexers  70   a  through  70   d  of the multiplexer  70 , and is connected to a multiplexer  73  forming part of a selector circuit  72 . The register R 6  is connected to the multiplexers  70   a  through  70   d  of the multiplexer  70 , and is connected to the multiplexer  74  provided in the selector circuit  72 . 
     The register R 7  is connected to the multiplexers  70   a  through  70   d  of the multiplexer  70 , and is connected to the multiplexer  75  of the selector circuit  72 . The register R 8  is connected to multiplexers  70   a  through  70   d  of the multiplexer  70 , and is connected to the multiplexer  76  of selector circuit  72 . 
     Multiplexer  70  is comprised of the multiplexers  70   a  through  70   d  corresponding to the respective registers R 1  through R 4  of the register  34 . The multiplexer  70  selects instruction data supplied from the input ports DI 0  through DI 2 , the registers R 5  through R 8 , and the registers R 1  through R 4  of the register  34 , and supplies the selected data to the registers R 1  through R 4  of the register  34 . The registers R 1  through R 4  of the register  34  are connected to the output ports D 0  through D 3 , respectively, via the respective multiplexers  73  through  76  provided in the selector circuit  72 . Each of the multiplexers  73  through  76  selects a signal under the control of a control circuit  77 , and outputs the selected signal from a corresponding one of the output ports D 0  through D 3 . Control-logic tables used by the control circuit  77  are shown in FIGS. 12A-12E and FIGS. 13A-13E. These control-logic tables are provided in the same format as those of FIGS. 3A-3F and FIGS. 4A-4F. Namely, the multiplexer  42  of the registers R 5  through R 8  makes a selection according to entries provided in the field third from the left in a relevant table. Further, the multiplexers  70   a  through  70   d  make a selection according to entries provided in the field second from the left, and the multiplexers  73  through  76  make a selection according to entries provided in the field fourth from the left. Also, table entries of zero such as those found in the field third from the left in the table of FIG. 12B indicate no data changes. 
     FIG. 11 is a block diagram of an exemplary embodiment of the control circuit  77 . In the figure, a signal valid_in, which indicates a valid status of input data when it is 1, is supplied to an AND circuit  79   a . The AND circuit  79   a  performs an AND operation between the signal valid_in and an inverse of a full flag FF that is supplied from a control-signal-generation unit  78 . An output of the AND circuit  79   a  is supplied to registers R 15  through R 17  via AND circuits  79   b  through  79   d , respectively, and, also, is supplied to a register R 18  directly without having an intervening AND circuit. The AND circuits  79   b  through  79   d  receive signals CAN 5  through CAN 7 , respectively, from the control-signal-generation unit  78 . Each of the registers R 15  through R 18  includes the D flip-flop  60  for latching data, the buffer  61  for looping back an output of the D flip-flop  60 , and the multiplexer  62  for selecting data from an input port or data from the buffer  61 . 
     The register R 15  is connected to multiplexers  80   a  through  80   d  of a multiplexer  80 , and is connected to a multiplexer  83  serving as a selector circuit. The register R 16  is connected to the multiplexers  80   a  through  80   d , and is connected to a multiplexer  84 . The register R 17  is connected to the multiplexers  80   a  through  80   d , and is connected to a multiplexer  85 . The register R 18  is connected to the multiplexers  80   a  through  80   d , and is connected to a multiplexer  86 . 
     The multiplexer  80  comprises multiplexers  80   a  through  80   d  corresponding to respective registers R 11  through R 14 . The multiplexer  80  selects instruction data supplied from the registers R 15  through R 18  and the registers R 11  through R 14 , and supplies the selected data to the registers R 11  through R 14 . The registers R 11  through R 14  are connected to the respective multiplexers  83  through  86 . Each of the multiplexers  83  through  86  selects a signal under the control of the control-signal-generation unit  78 , and outputs a corresponding one of the valid-data-position signals vali 0   d  through valid 3 . Control-logic tables used by the control-signal-generation unit  78  are the same as those of FIGS. 12A-12E and FIGS. 13A-13E. Namely, the multiplexer  62  of the registers R 15  through R 18  makes a selection according to entries provided in the field third from the left in a relevant table. Further, the multiplexers  80   a  through  80   d  make a selection according to entries provided in the field second from the left, and the multiplexers  83  through  86  make a selection according to entries provided in the field fourth from the left. 
     If the number of data items stored in the registers  18  and  34  exceeds the number of output ports, instruction data is stored in the register  18 . In order to maintain a correct data-output order in relation to previous input data, the multiplexer  70  stores the data of the register  18  in the register  34  by arranging the data to follow valid data already stored in the register  34 . If the register  34  becomes full, data that is late in an order of data output is left in the register  18 . The selector circuit  72  selects data from the register  34  in the order of data output and outputs the selected data. If the number of data items stored in the register  34  is below the number of the output ports, input data is stored in the register  34  by the multiplexer  70  such that the input data comes after the valid data already stored in the register  34 . This maintains a correct order of data output in relation to the previous input data. If the register  34  becomes full, the data that is late in the order of data output is stored in the register  18 . 
     Following describes the operation of the FIFO circuit of FIG. 10 with reference to the timing chart of FIG.  9 . 
     As shown in a phase  1  of FIG. 9, initial settings are such that no valid data is held. In this case, valid 0  through valid 3  are all zero, so that the control-logic table of the mode #0 shown in FIG. 12A will be selected. Further, the output-request number is 1 (SO=1000), so that the control circuit controls in accordance with the conditions set forth in the second row of the control-logic table of the mode #0. 
     At a rising edge of a clock signal clock after the signal valid_in indicative of valid data input becomes 1, instruction data (data 1 through 4) supplied to the input ports DI 0  through DI 3  are stored in the registers R 5  through R 8 . The instruction data of the registers R 5  through R 8  are then supplied to the output ports D 0  through D 3 , and the instruction data (data 1), is output from the output port D 0  in accordance with the output-request number of 1. The selector circuit is always controlled in advance to select as many instruction data items as the output-request number. Namely, no instruction data is output from the output ports D 1  through D 3  during the phase  1 . 
     Then, the operation enters a phase  2  in response to a rising edge of the clock signal clock. Since the instruction data are stored in the registers R 5  through R 8 , the control-logic table of the mode #4 (valid data positions: R 5 , R 6 , R 7 , and R 8 ) shown in FIG. 12A is referred to. With the output-request number being one (SO=1000), the second row of the table is selected. As is described in the second row, the contents of the registers R 6  through R 8  are moved to the registers R 1  through R 3 , respectively. The data coming to the register R 5  is directed to the register R 4 , so that the signal CAN 5  invalidates the data of the register R 5 . In the middle of the phase  2 , external conditions are changed, with the new conditions being the output-request number is 2 (SO=1100) and four instruction data items (data 5 through 8) are supplied as input data. 
     In response to a rising edge of the clock signal clock, the operation enters a phase  3 . Since valid instruction data are stored in the registers R 1 , R 2 , R 3 , R 5 , R 6 , R 7 , and R 8 , the control-logic table of the mode #7 shown in FIG. 13D is referred to. With the output-request number being 2, the third row of the control-logic table of the mode #7 is consulted, so that the contents of the registers R 1  and R 2  are output from the output ports D 0  and D 1 , respectively. Further, the data of the register R 3  is moved to the register R 1  and the data of the registers R 5  through R 7  are moved to the registers R 2  through R 4 , respectively. The data in the register R 8  stays therein. In this embodiment, a data-output order is determined according to the register numbers. Because of this limitation, when the register R 5  receives next instruction data, the contents of the register R 5  is regarded as having been input before the contents of the register R 8 . In order to avoid this, the full flag FF being one is output to an exterior of the circuit, thereby invalidating the valid-data-indication signal valid in. 
     After this, the output-request number is 2 (SO=1100) and four instruction data items (data 9 through 12) are input. In response to a rising edge of the clock signal clock, the operation enters a phase  4 . Since valid instruction data are stored in the registers R 1 , R 2 , R 3 , R 4 , and R 8 , the control-logic table of the mode #5 shown in FIG. 13B is referred to. With the output-request number being 2, the third row of the control-logic table of the mode #5 is consulted, so that the contents of the registers R 1  and R 2  are output from the output ports D 0  and D 1 , respectively. Further, the data of the registers R 3 , R 4 , and R 8  are moved to the registers R 1  through R 3 , respectively. The full flags FF in this case are zero. 
     In response to a rising edge of the clock signal clock, the operation enters a phase  5 . Now that the full flags FF are zero, the registers R 5  through R 8  store therein instruction data (data 9 through 12) supplied to the input ports DI 0  through DI 3  wherein these data were stopped from being stored during the phase  4 . Since valid instruction data are stored in the registers R 1 , R 2 , R 3 , R 5 , R 6 , R 7 , and R 8 , the control-logic table of the mode #7 shown in FIG. 13D is referred to. With the output-request number being 4 (SO=1111) at this time, the fifth row of the control-logic table of the mode #7 is consulted, so that the instruction data (data 6. 7, 8, 9) of the registers R 1 , R 2 , R 3 , and R 5  are output from the output ports D 0 , D 1 , D 2 , and D 3 , respectively. Further, the data of the registers R 6 , R 7 , R 8 , and R 4  (R 4  being a dummy) are moved to the registers R 1  through R 4 , respectively. The full flags FF in this case are zero. 
     Thereafter, the valid-input-indication signal valid_in, becomes zero, and the output-request number remains 4 (SO=1111). As the operation enters a phase  6  in response to a rising edge of the clock signal clock, the control circuit stores control data therein indicative of an invalid status of the registers R 5  through R 8 . Since valid instruction data are stored in the registers R 1 , R 2 , and R 3 , the control-logic table of the mode #3 shown in FIG. 12E is consulted. With the output-request number being  4 , the fifth row of the control-logic table of the mode #3 is referred to, and the contents of the registers R 1 , R 2 , R 3 , and R 4  are output from the output ports D 0 , D 1 , D 2 , and D 3 , respectively. In this case, however, the signals valid 0 , valid 1 , and valid 2  being one are output, indicating that the output data of the output ports D 0 , D 1 , and D 2  are valid. Further, the signal valid 3  being zero is output, indicating that the output data of the output port D 3  is invalid. 
     In this fourth exemplary embodiment, the circuit configuration is such that the selector circuit  72  selects data to be output from the output ports D 0  through D 3  between the register  34  and the input register  18 . Such a choice between two alternatives reduces the load on the output signals, thereby providing a circuit suitable for high-speed operation. It should be noted, however, that the load on the input signals of the multiplexer  70  is heavier than in the third embodiment. 
     FIG. 14 is a block diagram of a fifth exemplary embodiment of a FIFO circuit according to the present invention. The configuration of FIG. 14 differs from that of FIG. 7 only in that a control circuit  87  is used in place of the control circuit  47 . In FIG. 14, the same elements as those of FIG. 7 are referred to by the same numerals, and a description thereof will be omitted. Control-logic tables used by the control circuit  87  are shown in FIGS. 16A-16F, FIGS. 17A-17F, FIGS. 18A-18F, and FIGS. 19A-19F. Namely, the multiplexer  42  of the registers R 5  through R 8  makes a selection as required by entries provided in the field third from the left in a relevant table. Further, the multiplexers  30   a  through  30   d  make a selection according to entries provided in the field second from the left and the multiplexers  43  through  46  make a selection according to entries provided in the field fourth from the left. 
     FIG. 15 is a block diagram of an exemplary embodiment of the control circuit  87 . Differences between FIG.  15  and FIG. 9 are that full flags FF 0  through FF 3  are provided to indicate a status of the registers R 5  through R 8 , and that signals valid_in 0  through valid_in 3 , are provided to make it possible to individually invalidate signals indicative of valid data input when the registers R 5  through R 8  are full. 
     In FIG. 15, the signals valid_in 0  through valid_in 3 , each of which indicates a valid status of input data when it is 1, are supplied to AND circuits  49   a  through  49   d , respectively. The AND circuit  49   a  through  49   d  perform an AND operation between the signals valid_in 0  through valid_in 3  and inverses of full flags FF 0  through FF 3  that are supplied from a control-signal-generation unit  88 . Outputs of the AND circuits  49   a  through  49   d  are supplied to the registers R 15  through R 18 , respectively. Each of the registers R 15  through R 18  includes the D flip-flop  60  for latching data, the buffer  61  for looping back an output of the D flip-flop  60 , and the multiplexer  62  for selecting data from an input port or data from the buffer  61 . 
     The register R 15  is connected to the multiplexers  50   a  through  50   d  of the multiplexer  50  and is connected to the multiplexers  53  through  56  serving as a selector circuit. The register R 16  is connected to the multiplexers  50   a  through  50   d , and is connected to the three multiplexers  54  through  56 . 
     The register R 17  is connected to the multiplexers  50   a  through  50   d , and is connected to the two multiplexers  55  and  56 . The register R 18  is connected to the multiplexers  50   a  through  50   d , and is connected to the multiplexer  56 . 
     The multiplexer  50  comprises the multiplexers  50   a  through  50   d  corresponding to the respective registers R 11  through R 14 . The multiplexer  50  selects instruction data supplied from the registers R 15  through R 18  and the registers R 11  through R 14 , and supplies the selected data to the registers R 11  through R 14 . The registers R 11  through R 14  are connected to the respective multiplexers  53  through  56 . Each of the multiplexers  53  through  56  selects a signal under the control of the control-signal-generation unit  88 , and outputs a corresponding one of valid-data-position signals valid 0  through valid 3 . Control-logic tables used by the control-signal-generation unit  88  are shown in FIGS. 16A-16F through FIGS. 19A-19F. Namely, the multiplexer  62  of the registers R 15  through R 18  makes a selection according to entries provided in the field third from the left in a relevant table. Further, the multiplexers  50   a  through  50   d  make a selection according to entries provided in the field second from the left, and the multiplexers  53  through  56  make a selection according to entries provided in the field fourth from the left. Further, the rightmost field of any given FIGS. 16A-16F through FIGS. 19A-19F control-logic table shows a value of a pointer  90 . 
     Following describes the operation of the FIFO circuit of FIG. 14 with reference to the timing chart of FIG.  20 . 
     As shown in a phase  1  of FIG. 20, initial settings are such that no valid data is held. In this, case, valid 0  through valid 3  are all zero, so that the control-logic table of the mode #0 shown in FIG. 16A will be selected. Further, the output-request number is 1 (SO=1000), so that the control circuit controls in accordance with the conditions set forth in the second row of the control-logic table of the mode #0. As a result, the pointer is set to 5. 
     At a rising edge of a clock signal clock after the valid-input-indication signals valid_in 0  through valid_in 3  become 1, instruction data (data 1 through 4) supplied to the input ports DI 0  through DI 3  are stored in the registers R 5  through R 8 . The instruction data of the registers R 5  through R 8  are then supplied to the output ports D 0  through D 3 , and the instruction data (data 1) is output from the output port D 0  in accordance with the output-request number of 1. The selector circuit is always controlled in advance to select as many instruction data items as the output-request number. No instruction data is output from the output ports D 1  through D 3  during phase  1 . 
     Then, the operation enters a phase  2  in response to a rising edge of the clock signal clock. Since the instruction data are stored in the registers R 5  through R 8 , the control-logic table of the mode #4 (valid data positions: R 5 , R 6 , R 7 , and R 8 ) shown in FIG. 16A is-referred to. With the output-request number being one (SO=1000), the second row of the table is selected. As is described in the second row, the contents of the registers R 6  through R 8  are moved to the registers R 1  through R 3 , respectively. In the middle of phase  2 , external conditions are changed, with the new conditions that the output-request number is 2 (SO=1100), and four instruction data items (data 5 through 8) are supplied as input data. 
     In response to a rising edge of the clock signal clock, the operation enters a phase  3 . Since valid instruction data are stored in the registers R 1 , R 2 , R 3 , R 5 , R 6 , R 7 , and R 8 , the control-logic table of the mode #7 shown in FIG. 18C is referred to. With the output-request number being 2, the third row of the control-logic table of the mode #7 is consulted, so that the contents of the registers R 1  and R 2  are output from the output ports D 0  and D 1 , respectively. Further, the data of the register R 3  is moved to the register R 1 , and the data of the registers R 5  through R 7  are moved to the registers R 2  through R 4 , respectively. The data in the register R 8  stays therein. In this embodiment, a data-output order is determined according to the register numbers. Because of this limitation, when the register R 5  receives next instruction data, the contents of the register R 5  is regarded as having been input before the contents of the register R 8 . In order to avoid this, the pointer is changed to R 8 . In order to indicate that input to the input port DI 3  is not acceptable when considering a need to prevent rewriting of the data of R 8 , the full flag FF 3  being one is supplied to the exterior of the circuit. Moreover the AND circuit  49   d  invalidates the valid-input-indication signal valid_in 3 . 
     In and after the phase  4 , the number of data items stored in the eight registers is eight as long as the number of input data items does fall below the number of output data items. This insures an efficient use of the registers R 1  through R 8 . 
     In this fifth embodiment, the pointer is used to indicate which one of the-registers R 5  through R 8  of the input register  18  stores a data item that needs to be output first. In the input register  18 , data items are stored in the registers R 5 , R 6 , R 7 , and R 8  in this order by following the order in which the data items are output. In order to maintain a correct order, all the data in the input register should be out by the time the next data is put in the register R 5  after storing one round of data. Since the pointer indicates a data place where the data is to be output first, a correct order is maintained even if the next data is stored in the register R 5  after one round of data storing. This achieves efficient use of the registers R 1  through R 8 . 
     It should be noted that the register  34  corresponds to an intermediate register.