Abstract:
A drive circuit for a synchronous rectifier has a transformer having a main secondary winding and an auxiliary secondary winding. A first switch and a second switch each have a pair of terminals, a terminal of the first switch being connected to the first end of the main winding, a terminal of the second switch being connected to the second end of the main winding, and each remaining terminal of the first and second switch being connected together. A third switch connects between the second end of the main winding and the first end of the auxiliary winding, wherein the third switch periodically closes to connect the main winding and the auxiliary winding in series, a drive voltage being developed by the connected main and auxiliary windings being used to control at least one of the first switch and second switch.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates generally to switching power supplies having synchronous rectifiers, and more particularly to self-driven synchronous rectifiers.  
       BACKGROUND OF THE INVENTION  
       [0002]     In a forward converter topology, it is known to drive a synchronous rectifier and a free-wheeling MOSFET directly from a secondary output of a transformer. However, in low output voltages or high density applications, designers prefer a circuit having better efficiency than such configurations typically provide.  
         [0003]     Driving the synchronous rectifier and free-wheeling MOSFET directly from the sole secondary winding of the transformer may be acceptable in a DC-DC converter providing a high output voltage, but a DC-DC converter with a low output voltage generally requires a different driving scheme to improve efficiency. An example of a different driving scheme includes using a transformer having a main secondary winding and at least one auxiliary secondary winding that has a higher turns ratio than a main secondary winding. The auxiliary winding having the higher turns ratio is used to provide a drive voltage for the synchronous rectifier and the free-wheeling MOSFET. However, using a transformer with a turns ratio greater than 1:1 is undesirable in a DC-DC converter design that uses a planar transformer and/or is of compact physical dimensions such as an industry standard ⅛ or 1/16 brick form factor.  
         [0004]     Generating a bias voltage is another issue that may arise in a design using a planar transformer and/or a compact design. Again, with a large transformer having a high secondary output voltage, the bias voltage can be tapped from the main secondary transformer winding. In a low output voltage application, however, another solution is needed.  
       SUMMARY OF THE INVENTION  
       [0005]     This invention is directed to a drive circuit having a transformer with a main secondary winding and an auxiliary secondary winding. A first switch and a second switch each have at least a pair of terminals, a terminal of the first switch being connected to the first end of the main winding, a terminal of the second switch being connected to the second end of the main winding, and a remaining terminal of the first and second switch being connected together. A third switch connects between the second end of the main winding and the first end of the auxiliary winding, wherein the third switch periodically closes to connect the main winding and the auxiliary winding in series, a drive voltage being developed by the connected main and auxiliary windings being used to control at least one of the first switch and second switch.  
         [0006]     In another aspect, a drive circuit is provided having a transformer with a secondary side with a main winding and an auxiliary winding, and a means for periodically series connecting the main winding and the auxiliary winding. A first switch and a second switch have a terminal that connects to a respective end of the main winding, the first and second switches being connected across the periodically series connected main and auxiliary windings. A drive voltage is developed across the periodically series connected main and auxiliary windings and used to control at least one of the first switch and second switch.  
         [0007]     Yet another aspect provides, in a switching power supply having a transformer with a main secondary winding and an auxiliary secondary winding and a synchronous rectifier circuit connected to the main secondary winding, a method for driving the synchronous rectifier circuit. The method includes periodically connecting the main and auxiliary secondary windings in series to develop a drive voltage across them, and applying the drive voltage to the synchronous rectifier circuit.  
         [0008]     In a further aspect, a bias supply circuit for a self-driven synchronous rectifier arrangement is provided. The bias supply circuit includes a transformer having a main secondary winding and an auxiliary secondary winding, and an energy storage device charged by the main secondary winding and the auxiliary secondary winding.  
         [0009]     Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]     The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein:  
         [0011]      FIG. 1  depicts a schematic diagram of a driver circuit of the present invention;  
         [0012]      FIGS. 2   a ,  2   b , and  2   c  depict waveforms of gate drive signals in the circuit of  FIG. 1 .  
         [0013]      FIG. 3  depicts a graph of an efficiency of the circuit in  FIG. 1 ; and  
         [0014]      FIG. 4  depicts another of various embodiments of a driver circuit of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0015]     The following description is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses.  
         [0016]      FIG. 1  shows one of various embodiments of a self driven synchronous rectifier circuit  10 . A transformer T 1  has a primary winding  12  with terminals  1  and  2 , main secondary winding  14  with terminals  3  and  4 , and an auxiliary secondary winding  16  with terminals  5  and  6 . Transformer T 1  may be a planar transformer with secondary windings  14 ,  16  each having a turns ratio of 1:1. Terminal  3  of the main secondary winding and terminal  5  of the auxiliary secondary winding are electrically in phase as indicated by the phase dots. A supply voltage +VIN is applied to terminal  1 . Terminal  2  connects to a supply voltage reference −VIN through a switching transistor Q 1 . Terminal  2  also connects to supply voltage reference −VIN through a capacitor C 2  connected in series with a second switching transistor Q 2 . Supply voltage +VIN is a positive DC voltage.  
         [0017]     Transistors Q 1  and Q 2  are controlled by a control circuit which is known in the art and not shown. The control circuit provides a pulse width modulated (PWM) control signal to a gate of transistor Q 1 . A gate of transistor Q 2  receives a logical complement of the PWM control signal. A period when the PWM control signal turns on transistor Q 1  will be referred to as a positive period. A period when the complement of the PWM control signal turns on transistor Q 2  will be referred to as a negative period. During the positive period, transistor Q 1  turns on and transistor Q 2  turns off, allowing current to flow through primary winding  12 . During the negative period, transistor Q 1  turns off and transistor Q 2  turns on, thereby connecting pin  2  of the primary winding to the supply reference voltage −VIN through capacitor C 2 . A capacitor C 1  provides a simple low pass filter for the supply voltage +VIN.  
         [0018]     Attention will now be turned to the circuitry connected to the secondary side of transformer T 1 . Terminal  3  of main secondary winding  14  connects to a drain of transistor Q 4 . An output filter comprises an inductor L 1  and a capacitor C 5 . A source of transistor Q 4  connects to an output voltage reference −VOUT and to a source of a transistor Q 3 . A drain of transistor Q 3  connects to terminal  4  of main secondary winding  14 . A gate of transistor Q 4  connects to terminal  6  of auxiliary secondary winding  16 . A gate of transistor Q 3  connects to terminal  3  of main secondary winding  14 . Transistor Q 4  may also be referred to as a free wheeling transistor, and transistor Q 3  may also be referred to as a synchronous rectifier.  
         [0019]     An output node +VOUT is taken across capacitor C 5 . A resistor R represents an electrical load. An output voltage is provided across the output node +VOUT and and an output reference node −VOUT. The output reference node −VOUT connects to the source of transistor Q 3  and to the source of transistor Q 4 .  
         [0020]     One terminal of a capacitor C 4  connects to the output reference node −VOUT. The other terminal of capacitor C 4  connects to a cathode of a rectifier CR 2  and a cathode of a rectifier CR 3 . An anode of rectifier CR 2  connects to terminal  3  of main secondary winding  14 . An anode of rectifier CR 3  connects to terminal  6  of auxiliary secondary winding  16 .  
         [0021]     A transistor Q 5 A has a source connected to terminal  4  of main secondary winding  14 . A drain of transistor Q 5 A connects to terminal  5  of auxiliary secondary winding  16 . A gate of transistor Q 5 A connects to terminal  6  of auxiliary secondary winding  16 .  
         [0022]     A transistor Q 5 B has a drain connected to terminal  6  of auxiliary secondary winding  16 . A source of transistor Q 5 B connects to the output reference node −VOUT. A gate of transistor Q 5 B connects to terminal  3  of main secondary winding  14 . Transistor Q 5 A and transistor Q 5 B may be implemented using a single package containing dual independent N-channel MOSFETs. One or both of transistor Q 5 A and transistor Q 5 B may also be implemented by other means for periodically series connecting the main winding and the auxiliary winding, such as a digitally controlled switch, bipolar device, or field-effect device.  
         [0023]     The operation of the circuitry on the secondary side of transformer T 1  will now be described. During the positive period, a positive voltage appears at terminal  3  of main secondary winding  14  and at terminal  5  of auxiliary secondary winding  16 . A negative voltage appears at terminal  4  of main secondary winding  14  and at terminal  6  of auxiliary secondary winding  16 . The positive and negative polarities are with respect to the output reference node −VOUT.  
         [0024]     The negative voltage at terminal  6  of auxiliary secondary winding  16  turns off transistor Q 4  and transistor Q 5 A. The positive voltage at terminal  3  of main secondary winding  14  turns on transistor Q 3 . When transistor Q 3  turns on, current flows from terminal  3  of main secondary winding  14  through inductor L 1  and through resistor R. A portion of the current flow charges capacitor C 5 . Current returns from resistor R and capacitor C 5  through transistor Q 3  to terminal  4  of the main secondary winding  14 . The positive voltage appearing at terminal  3  of the main secondary winding  14  also turns on transistor Q 5 B. Transistor Q 5 B discharges the gate of transistor Q 4 , which quickly turns transistor Q 4  off at a beginning of the positive period. Capacitor C 4  charges through rectifier CR 2  during the positive period.  
         [0025]     During the negative period a negative voltage appears at terminal  3  of main secondary winding  14  and at terminal  5  of auxiliary secondary winding  16 . A positive voltage appears at terminal  4  of main secondary winding  14  and at terminal  6  of auxiliary secondary winding  16 . The positive and negative polarities are with respect to the output reference node −VOUT.  
         [0026]     The negative voltage at terminal  3  of main secondary winding  14  turns off transistor Q 3  and transistor Q 5 B. The positive voltage at terminal  6  of auxiliary secondary winding  16  turns on transistor Q 5 A. When transistor Q 5 A turns on, it connects main secondary winding  14  and auxiliary secondary winding  16  in series. A magnitude of the positive voltage at terminal  6  of auxiliary secondary winding  16  is therefore equal to a sum of the voltage across terminals  3  and  4  of main secondary winding  14  and the voltage across terminals  5  and  6  of auxiliary secondary winding  16 . This high positive voltage at terminal  6  of auxiliary secondary winding  16  provides an gate-source drive voltage sufficient for transistor Q 4  to turn on. When transistor Q 4  is turned on it provides a freewheel path for inductor L 1 .  
         [0027]     During the negative period, the high positive voltage at terminal  6  of auxiliary secondary winding  16  also charges capacitor C 4  through rectifier CR 3 . Capacitor C 4  is therefore charged during the positive and negative periods and provides a bias voltage for a secondary circuit (not shown).  
         [0028]      FIGS. 2A, 2B , and  2 C show the gate-source waveforms of an implementation of the circuit of  FIG. 1  at supply voltages +VIN of 36V, 48V, and 75V, respectively. The circuit of  FIG. 1  was designed in a ⅛ brick form factor and provides a maximum output voltage of 1.2V and maximum output current (lomax) of 25 A. The maximum duty cycle was 42% and the switching frequency was 475 KHz. Transistors Q 3  and Q 4  were implemented with Si7868 power MOSFETs available from Vishay. During the positive period  18 , transistor Q 3  is provided with a gate-source voltage of about 0.9V at 36V+VIN ( FIG. 2   a ), 1.2V at 48V+VIN ( FIG. 2   b ), and 1.8V at 75V+VIN ( FIG. 2   c ). During the negative period  20 , transistor Q 4  is provided with a gate-source voltage of about 5V at 36V+VIN, 4V at 48V+VIN, and 3.5V at 75V+VIN.  
         [0029]      FIG. 3  shows overall efficiencies of the circuit having the gate-source waveforms of  FIG. 2 . A vertical axis  30  represents efficiency. A horizontal axis  32  represents output current as a percentage of lomax. The plotted family of curves show the efficiency of the circuit at each supply voltage +VIN of 36V, 48V, and 75V. The efficiency of the circuit is improved over the prior art by 2-5% at full load over the range of +VIN.  
         [0030]      FIG. 4  shows one of various embodiments is shown suitable for use with a transformer T 2  having an auxiliary secondary winding  16 ′. The auxiliary secondary winding  16 ′ has a secondary-to-primary turns ratio greater than 1:1, such as 2:1. It should be noted that like reference numerals will be used to describe similar elements to that of  FIG. 1 . The circuit  40  provides generally similar gate-source waveforms and efficiencies as the circuit of  FIG. 1 .  
         [0031]     Terminal  3  of a main secondary winding  14  connects to a drain of a transistor Q 4 . An output filter comprises an inductor L 1  and a capacitor C 5 . A source of transistor Q 4  connects to an output voltage reference −VOUT and to a source of a transistor Q 3 . A drain of transistor Q 3  connects to terminal  4  of main secondary winding  14 . A gate of transistor Q 4  connects to terminal  6  of auxiliary secondary winding  16 ′. A gate of transistor Q 3  connects to terminal  3  of main secondary winding  14 . In an alternative configuration suitable for use with a PWM duty cycle greater than 50%, the gate of transistor Q 3  connects instead to terminal  5  of auxiliary secondary winding  16 ′. Transistor Q 4  may also be referred to as a free wheeling transistor, and transistor Q 3  may be referred to as a synchronous rectifier.  
         [0032]     A resistor R represents an electrical load and is in parallel with Capacitor C 5 . An output voltage is provided across the +VOUT and −VOUT terminals. The output reference terminal −VOUT connects to the source of transistor Q 3  and to the source of transistor Q 4 .  
         [0033]     One terminal of a capacitor C 4  connects to the output reference node −VOUT. The other terminal of capacitor C 4  connects to a cathode of a rectifier CR 2  and a cathode of a rectifier CR 3 . An anode of rectifier CR 2  connects to terminal  3  of main secondary winding  14 , and an anode of rectifier CR 3  connects to terminal  6  of auxiliary secondary winding  16 ′.  
         [0034]     A transistor Q 5 B has a source connected to the source of transistor Q 4  and a drain connected to the gate of transistor Q 4 . A gate of transistor Q 5 B connects to terminal  3  of main secondary winding  14 . A transistor Q 5 C has a source connected to the output reference node −VOUT and a drain connected to terminal  5  of auxiliary secondary winding  16 ′. A gate of transistor Q 5 C connects to terminal  6  of auxiliary secondary winding  16 ′.  
         [0035]     The operation of the circuitry on the secondary side of transformer T 2  will now be described. One skilled in the art will recognize that the circuitry on the primary side of transformer T 2  operates as described with respect to  FIG. 1 . During the positive period, a positive voltage appears at terminal  3  of main secondary winding  14  and at terminal  5  of auxiliary secondary winding  16 ′. A negative voltage appears at terminal  4  of main secondary winding  14  and at terminal  6  of auxiliary secondary winding  16 ′. The positive and negative polarities are with respect to the output reference node −VOUT.  
         [0036]     The negative voltage at terminal  6  of auxiliary secondary winding  16 ′ turns off transistor Q 4  and transistor Q 5 C. The positive voltage at terminal  3  of main secondary winding  14  turns on transistor Q 3 . When transistor Q 3  turns on, current flows from terminal  3  of main secondary winding  14  through inductor L 1  and through resistor R. A portion of the current flow charges capacitor C 5 . Current returns from resistor R through transistor Q 3  to terminal  4  of the main secondary winding  14 . The positive voltage appearing at terminal  3  of the main secondary winding  14  also turns on transistor Q 5 B. Transistor Q 5 B discharges the gate of transistor Q 4 , which quickly turns transistor Q 4  off at a beginning of the positive period. Capacitor C 4  charges through rectifier CR 2  during the positive period.  
         [0037]     During the negative period a negative voltage appears at terminal  3  of main secondary winding  14  and at terminal  5  of auxiliary secondary winding  16 ′. A positive voltage appears at terminal  4  of main secondary winding  14  and at terminal  6  of auxiliary secondary winding  16 ′. The positive and negative polarities are with respect to the output reference node −VOUT.  
         [0038]     The negative voltage at terminal  3  of main secondary winding  14  turns off transistor Q 3  and transistor Q 5 B. The positive voltage at terminal  6  of auxiliary secondary winding  16 ′ turns on transistor Q 5 C. When transistor Q 5 C turns on, it provides a current path for the auxiliary secondary winding  16 ′ to charge capacitor C 4  through rectifier CR 3 . Capacitor C 4  is therefore charged during the positive and negative periods and provides a bias voltage for a secondary circuit (not shown).  
         [0039]     Since auxiliary secondary winding  16 ′ has a turns ratio greater than 1:1, terminal  6  of auxiliary secondary winding  16 ′ generates ample voltage to turn on transistor Q 4 . When transistor Q 4  is turned on it provides a freewheel path for inductor L 1 .  
         [0040]     The description of the invention is merely exemplary in nature and, thus, variations that do not depart from the gist of the invention are intended to be within the scope of the invention. Such variations are not to be regarded as a departure from the spirit and scope of the invention.