Abstract:
A system is disclosed for a voltage controlled oscillator (“VCO”) having a large frequency range and a low gain. Passive or active circuitry is introduced between at least one VCO cell in the voltage controlled oscillator and the voltage source for the VCO cell which reduces a gain value for the VCO to maintain stability of the system.

Description:
BACKGROUND 
       [0001]    The Voltage controlled oscillator (“VCO”) plays an important role in the operation of a Phase Lock Loop (“PLL”). A typical PLL generates an output signal the phase of which is related to the phase of a reference signal (the input signal). 
         [0002]    As is known in the art, the gain of a VCO (K VCO ) is defined as the operational frequency range divided by the control voltage range, typically in the units of MHz/V. While having a large K VCO  is generally desirable (for example, a large K VCO  may allow the VCO to be used in a diverse variety of applications), if K VCO  becomes too large then stability and/or noise performance of the VCO will degrade which reduces the effectiveness of the VCO. With modern VCO applications, the value of voltage source V DD  is reduced which consequently reduces the operating range of the control voltage signal V C  and therefore increases K VCO . Additionally, modern VCO applications require higher operational speed and data rate thereby increasing the operational frequency range of the VCO which, consequently, increases K VCO  even further. The result is that K VCO  becomes too large to maintain the necessary stability and/or noise performance requirements. 
         [0003]    Therefore, there is a need to have a VCO with a larger operational frequency range will maintaining a low K VCO  to maintain stability and/or noise performance of the VCO. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]      FIG. 1  is a simplified schematic drawing of a phase lock loop with a voltage controlled oscillator. 
           [0005]      FIG. 2  is a simplified schematic drawing of a phase lock loop with a voltage controlled oscillator according to an embodiment of the present subject matter. 
           [0006]      FIG. 3  is a simplified schematic drawing of a phase lock loop with a voltage controlled oscillator according to another embodiment of the present subject matter. 
           [0007]      FIG. 4  is a simplified schematic drawing of a phase lock loop with a voltage controlled oscillator according to yet another embodiment of the present subject matter. 
           [0008]      FIG. 5A  is an exemplary schematic circuit diagram of a portion of a voltage controlled oscillator according to an embodiment of the present subject matter. 
           [0009]      FIG. 5B  is an exemplary schematic circuit diagram of a portion of a voltage controlled oscillator according to another embodiment of the present subject matter. 
       
    
    
     DETAILED DESCRIPTION 
       [0010]    With reference to the figures where like elements have been given like numerical designations to facilitate an understanding of the present subject matter, various embodiments of a system and method for compensating for timing misalignments are described. In order to more fully understand the present subject matter, a brief description of applicable circuitry will be helpful. 
         [0011]    An exemplary PLL  11  is shown in  FIG. 1 . The PLL  11  includes a phase-frequency detector  20 , a charge pump  30 , a low pass filter  40 , a differential VCO  150 , and a divider circuit  60 . The low pass filter  40  includes a first capacitor, denoted C P , and a second capacitor, denoted C Z , which is arranged in series with a resistor, denoted R Z . Typically, the capacitance of capacitor C Z  is ten times the capacitance of capacitor C P . 
         [0012]    The VCO  150  includes one or more VCO cells; as shown, VCO  150  is a four stage VCO and has four VCO cells numbered  151 ,  152 ,  153 , and  154 . One of skill in the art will readily understand that a typical VCO in a PLL may contain more or fewer than four stages. The VCO cells in VCO  150  are cascaded and looped and each VCO cell provides a time delay T d  which is typically in the picosecond range. The output of differential VCO  150 , denoted f OUT , can be determined by the equation: 
         [0000]    
       
         
           
             
               f 
               OUT 
             
             = 
             
               1 
               
                 2 
                 × 
                 M 
                 × 
                 
                   T 
                   d 
                 
               
             
           
         
       
       
         
           
             where M=the number of stages in the VCO 
           
         
       
     
         [0014]    In the PLL  11 , the charge pump  30 , the low pass filter  40 , and the VCO cells  151 - 154  are each connected to a voltage source denoted V DD . Certain details of VCO cell  151  are shown which include a first CMOS (complementary metal oxide semiconductor)  111  which includes a first PMOS (a p-channel MOSFET (metal oxide semiconductor field effect transistor))  111   a,  and a second CMOS  112  which includes a second PMOS  112   a . CMOS  111  and CMOS  112  are connected between voltage source V DD  and ground, as shown. 
         [0015]    In operation, phase-frequency detector  20  receives a reference signal, denoted f REF , and compares a feedback signal, denoted f FDBK , to f REF . Alternatively, the frequency control signal may be derived from a comparison of the phase of the reference signal with the phase of the feedback signal. Based on the results of the comparison of f FDBK  to f REF , the phase-frequency detector  20  provides a frequency control signal to charge pump  30 . As is known in the art, if f FDBK  is greater than f REF , the frequency control signal DN will be supplied to charge pump  30 , whereas if f FDBK  is less than f REF , the frequency control signal UP will be supplied to charge pump  30 . The charge pump  30  receives the appropriate frequency control signal and generates therefrom a control current signal, denoted I CP , as is known in the art. The control current signal I CP  is operated on by low pass filter  40  to thereby generate a control voltage signal, denoted V C . 
         [0016]    The control voltage signal V C  is applied to the gate terminal of each of PMOS  111   a  and PMOS  112   a,  as is known in the art. PMOS  111   a  and PMOS  112   a  are controlled by the control voltage signal V C  such that the current through PMOS  111   a  and PMOS  112   a  changes in response thereto. For example, as is known in the art, a higher current through PMOS  111   a  and PMOS  112   a  causes the delay value T d  of VCO cell  151  to decrease which causes the output of the VCO  150 , f OUT , to increase. Likewise, a lower current through PMOS  111   a  and PMOS  112   a  causes the delay value T d  of VCO cell  151  to increase which causes the output of the VCO  150 , f OUT , to decrease. As stated above, VCO  150  provides an output f OUT  which is input to divider circuit  60 . Divider circuit  60  divides f OUT  by a predetermined value N, as is known in the art, to produce feedback signal f FDBK . 
         [0017]      FIG. 2  is a simplified schematic drawing of a phase lock loop  12  with a voltage controlled oscillator  250  according to an embodiment of the present subject matter. Similar to PLL  11  in  FIG. 1 , PLL  12  also includes a phase-frequency detector  20 , a charge pump  30 , a low pass filter  40 , and a divider circuit  60 , each as described above with respect to  FIG. 1 . The VCO  250  includes a VCO cell  251  which contains PMOS  111   a  and PMOS  112   a  where PMOS  111   a  and  112   a  are controlled by the control voltage signal V C  applied to the gate terminals thereof such that the current through PMOS  111   a  and PMOS  112   a  changes in response thereto. A terminal of PMOS  111   a  is connected to voltage source V DD  through resistor R 1  and switch S 1  where R 1  and S 1  are connected in parallel. Likewise, a terminal of PMOS  112   a  is connected to voltage source V DD  through resistor R 2  and switch S 2  where R 2  and S 2  are connected in parallel. Switches S 1  and S 2  may each be operated automatically based on an electrical control signal as is known in the art. In an embodiment, each VCO cell  252 - 254  of VCO  250  is configured in a similar way to the configuration described above for VCO cell  251 . 
         [0018]    For high data rate applications where a large operational frequency range of the VCO  250  is desirable, switches S 1  and S 2  are closed and therefore resistors R 1  and R 2 , respectively, are shorted out. Thus, VCO  250  operates in a similar manner as described above for VCO  150  in  FIG. 1 . In this configuration, the transconductance of, for example, PMOS  111   a  in VCO cell  251  is the same as the transconductance of PMOS  111   a  in VCO cell  151  in  FIG. 1 , and may be a predetermined value G m1 . As is known in the art, the transconductance is representative of a current change in a PMOS device due to a change in a voltage of control voltage signal V C  for the PMOS device. Similarly, in this configuration, the transconductance of, for example, PMOS  112   a  in VCO cell  251  is the same as the transconductance of PMOS  112   a  in VCO cell  151  in  FIG. 1 , and may be a predetermined value G m2 . In an embodiment, G m1  and/or G m2  may be in the range of milliamps/volt. 
         [0019]    For low data rate applications, switches S 1  and S 2  in  FIG. 2  are open thus placing resistors R 1  and R 2 , respectively, in between voltage source V DD  and PMOS  111   a  and PMOS  112   a,  respectively. One of the effects of this configuration is that the transconductance for PMOS  111   a  in VCO cell  251  is reduced to G′ m2  as follows: 
         [0000]    
       
         
           
             
               G 
               
                 m 
                  
                 
                     
                 
                  
                 1 
               
               ′ 
             
             = 
             
               
                 G 
                 
                   m 
                    
                   
                       
                   
                    
                   1 
                 
               
                
               
                 ( 
                 
                   1 
                   
                     1 
                     + 
                     
                       
                         G 
                         
                           m 
                            
                           
                               
                           
                            
                           1 
                         
                       
                        
                       
                         R 
                         1 
                       
                     
                   
                 
                 ) 
               
             
           
         
       
     
         [0000]    where R 1  is the resistance value for resistor R 1  in  FIG. 2 . Thus, the current change in PMOS  111   a  is reduced for a given change in control voltage signal V C . Likewise, the transconductance for PMOS  112   a  in VCO cell  251  is reduced to G′ m2  as follows: 
         [0000]    
       
         
           
             
               G 
               
                 m 
                  
                 
                     
                 
                  
                 2 
               
               ′ 
             
             = 
             
               
                 G 
                 
                   m 
                    
                   
                       
                   
                    
                   2 
                 
               
                
               
                 ( 
                 
                   1 
                   
                     1 
                     + 
                     
                       
                         G 
                         
                           m 
                            
                           
                               
                           
                            
                           2 
                         
                       
                        
                       
                         R 
                         2 
                       
                     
                   
                 
                 ) 
               
             
           
         
       
     
         [0020]    where R 2  is the resistance value for resistor R 2  in  FIG. 2 . Thus, the current change in PMOS  112   a  is reduced for a given change in control voltage signal V C . In an embodiment, R 1 =R 2  and G m1 =G m2  so that G′ m1 =G′ m2 . Due to the insertion of R 1  and R 2  between V DD  and PMOS  111   a  and  112   a,  the current into the VCO  250  is reduced thus reducing the operational frequency range of VCO  250  which, consequently, reduces K VCO . 
         [0021]      FIG. 3  is a simplified schematic drawing of a phase lock loop  13  with a voltage controlled oscillator  350  according to another embodiment of the present subject matter. Similar to PLL  11  in  FIG. 1 , PLL  13  also includes a phase-frequency detector  20 , a charge pump  30 , a low pass filter  40 , and a divider circuit  60 , each as described above with respect to  FIG. 1 . 
         [0022]    The VCO  350  includes a VCO cell  351  which contains PMOS  311   a,  PMOS  311   b,  PMOS  312   a,  and PMOS  312   b.  PMOS  311   a  and  311   b  are connected in parallel to voltage source V DD . Likewise, PMOS  312   a  and  312   b  are connected in parallel to voltage source V DD . PMOS  311   a  and  312   a  are controlled by the control voltage signal V C  applied to the gate terminals thereof such that the current through PMOS  311   a  and PMOS  312   a  changes in response thereto. PMOS  311   b  and  312   b  are controlled by the control voltage signal V Z  applied to the gate terminals thereof such that the current through PMOS  311   b  and PMOS  312   b  changes in response thereto. Control voltage signal V Z  is taken from the junction between capacitor C Z  and resistor R Z  in low pass filter  40 . In an embodiment, the capacitance of C Z  is approximately ten times the capacitance of C P . Thus, the voltage of the junction between C Z  and R Z , i.e., V Z , is relatively static in comparison to the voltage of V C . In an embodiment, each VCO cell  352 - 354  of VCO  350  is configured in a similar way to the configuration described above for VCO cell  351 . 
         [0023]    In an embodiment, a ratio of the physical size (e.g., the physical length or width) of PMOS  311   b  to PMOS  311   a  is K:1, where K&gt;1. In a particular embodiment, K=4. Similarly, a ratio of PMOS  312   b  to PMOS  312   a  is also K:1. A comparison of VCO cell  251  in  FIG. 2  (in the configuration where switches S 1  and S 2  are shut) with VCO cell  351  in  FIG. 3  reveals that replacing PMOS  111   a  in VCO cell  251  with PMOS  311   a  and  311   b  (connected as shown in  FIG. 3 ) and replacing PMOS  112   a  in VCO cell  251  with PMOS  312   a  and  312   b  (connected as shown in  FIG. 3 ) results in VCO cell  351 . As discussed above with respect to  FIG. 2 , the transconductance for PMOS  111   a  (in the configuration where switches S 1  and S 2  are shut) is equal to a predetermined value G m1 , and the transconductance for PMOS  112   a  (for this configuration) is equal to a predetermined value G m2 . For PMOS  311   a,  it can be seen that the transconductance is equal to 
         [0000]    
       
         
           
             
               
                 G 
                 
                   m 
                    
                   
                       
                   
                    
                   1 
                 
               
                
               
                 ( 
                 
                   1 
                   
                     1 
                     + 
                     K 
                   
                 
                 ) 
               
             
             , 
           
         
       
     
         [0000]    which is less than G m1  while for PMOS  312   a,  the transconductance is equal to 
         [0000]    
       
         
           
             
               G 
               
                 m 
                  
                 
                     
                 
                  
                 2 
               
             
              
             
               ( 
               
                 1 
                 
                   1 
                   + 
                   K 
                 
               
               ) 
             
           
         
       
     
         [0000]    which is less than G m2 . Therefore, the current into the VCO  350  is reduced thus reducing the operational frequency range of VCO  350  which, consequently, reduces K VCO  of VCO  350 . The reduction in K VCO  is by a factor of 
         [0000]    
       
         
           
             
               ( 
               
                 1 
                 
                   1 
                   + 
                   K 
                 
               
               ) 
             
             . 
           
         
       
     
         [0000]    However, the operational frequency range of VCO  350  is not reduced since the charge in capacitor C Z  can adjust while PLL  13  is operating in a long-term non-linear mode. 
         [0024]      FIG. 4  is a simplified schematic drawing of a phase lock loop  14  with a voltage controlled oscillator  450  according to yet another embodiment of the present subject matter. As can be seen from a comparison of  FIGS. 2 and 3  with  FIG. 4 ,  FIG. 4  is a combination of some components in  FIGS. 2 and 3 , e.g., VCO  450  includes a VCO cell  451  which contains PMOS  311   a,  PMOS  311   b,  PMOS  312   a,  and PMOS  312   b.  PMOS  311   a  and  311   b  are connected in parallel and are connected to voltage source V DD  through resistor R 1  and switch S 1  where R 1  and S 1  are connected in parallel. Likewise, PMOS  312   a,  and PMOS  312   b  are connected in parallel and are connected to voltage source V DD  through resistor R 2  and switch S 2  where R 2  and S 2  are connected in parallel. PMOS  311   a  and  312   a  are controlled by the control voltage signal V C  applied to the gate terminals thereof such that the current through PMOS  311   a  and PMOS  312   a  changes in response thereto. PMOS  311   b  and  312   b  are controlled by the control voltage signal V Z  applied to the gate terminals thereof such that the current through PMOS  311   b  and PMOS  312   b  changes in response thereto. Control voltage signal V Z  is taken from the junction between capacitor C Z  and resistor R Z  in low pass filter  40 . 
         [0025]    For low data rate applications, switches S 1  and S 2  are open thus placing resistors R 1  and R 2 , respectively, in between voltage source V DD  and PMOS  311   a  and  311   b  and PMOS  312   a  and  312   b,  respectively. Therefore, the operation of VCO  450  is a combination of the operating characteristics described above with respect to  FIG. 2  (with switches S 1  and S 2  open) and  FIG. 3 . The insertion of the resistors R 1  and R 2  between V DD  and PMOS  311   a  and  311   b  and PMOS  312   a  and  312   b  reduces the current into VCO  450  which reduces the operational frequency range of VCO  450  and, consequently, reduces K VCO  of VCO  450 . Additionally, the ratio of PMOS  311   b  to PMOS  311   a  is K:1, where K&gt;1 and, similarly, a ratio of PMOS  312   b  to PMOS  312   a  is also K:1. Consequently, as described above with respect to  FIG. 3 , this has the effect of reducing the current into VCO  450  which reduces the operational frequency range of VCO  450  and, consequently, reduces K VCO  of VCO  450 . Thus, K VCO  of VCO  450  is lower than K VCO  of either VCO  250  in  FIG. 2  or VCO  350  in  FIG. 3 . 
         [0026]    While the above embodiments in  FIGS. 2 through 4  discuss the use of PMOS, the present inventive subject matter contemplates the use of NMOS as well.  FIG. 5A  is an exemplary schematic circuit diagram of a portion of a voltage controlled oscillator, such as VCO  350  in  FIG. 3 , including PMOS  311   a  and PMOS  311   b.  As described above, the ratio of PMOS  311   b  to PMOS  311   a  is K:1, as shown. Also, PMOS  311   a  is controlled by control voltage signal V C  while PMOS  311   b  is controlled by control voltage signal V Z . For the sake of simplicity, PMOS  312   a  and PMOS  312   b,  along with other circuit devices, are not shown in  FIG. 5A . 
         [0027]      FIG. 5B  is an exemplary schematic circuit diagram of a portion of a voltage controlled oscillator, such as VCO  350  in  FIG. 3 , where NMOS (an n-channel MOSFET) devices are used instead of PMOS devices. NMOS  311   c  is controlled by control voltage signal V C  while NMOS  311   d  is controlled by control voltage signal V Z . The ratio of NMOS  311   c  to NMOS  311   d  is 1:K. In an embodiment, NMOS devices would also be used to replace PMOS  312   a  and PMOS  312   b  in VCO  350  in  FIG. 3 . 
         [0028]    According to embodiments of the present subject matter, a circuit includes a voltage controlled oscillator (“VCO”) having a VCO cell which includes a first CMOS circuit including a first PMOS device having a gate terminal which receives a control voltage signal, and having a second terminal operatively connected to a first resistor where the first resistor is operatively connected to a first voltage source, and a second CMOS circuit including a second PMOS device having a gate terminal which receives the control voltage signal, and having a second terminal operatively connected to a second resistor where the second resistor is operatively connected to the first voltage source, and the VCO further having an output terminal and providing an output frequency signal thereon. 
         [0029]    In other embodiments of the present subject matter, the circuit above includes a first switch operatively connected in parallel with the first resistor. In yet other embodiments, the circuit further includes a second switch operatively connected in parallel with the second resistor. In still further embodiments, the circuit has an operational parameter D for the first PMOS device which is equal to a predetermined number G when said first switch is closed and the operational parameter D is equal to 
         [0000]    
       
         
           
             G 
              
             
               ( 
               
                 1 
                 
                   1 
                   + 
                   GR 
                 
               
               ) 
             
           
         
       
     
         [0000]    when the first switch is open, where the operational parameter D is representative of a current change in the first PMOS device due to a change in a voltage of the control voltage signal, and where R is a resistance value for the first resistor. 
         [0030]    In still other embodiments, the circuit includes a phase-frequency detector which detects a difference between a reference frequency signal and a feedback frequency signal to thereby produce a frequency control signal, a charge pump which receives the frequency control signal and generates a control current signal therefrom, and a low pass filter operatively connected to the charge pump where the low pass filter integrates the control current signal and generates the control voltage signal therefrom. In yet still other embodiments, this circuit further includes a divider circuit operatively connected to the output terminal of the VCO and to the phase-frequency detector, where the divider circuit reduces a frequency of the output frequency signal to thereby generate the feedback frequency signal. In some embodiments, the phase-frequency detector detects a difference between a phase of a reference signal and a phase of a feedback signal to thereby produce a frequency control signal. 
         [0031]    In accordance with additional embodiments of the present subject matter, a circuit includes a phase-frequency detector which detects a difference between a reference frequency signal and a feedback frequency signal to thereby produce a frequency control signal, a charge pump which receives the frequency control signal and generates a control current signal therefrom, a low pass filter operatively connected to the charge pump where the low pass filter integrates the control current signal and generates a first control voltage signal therefrom, and where the low pass filter includes a first capacitor operatively connected to a first resistor, and an output terminal operatively connected to a junction between the first capacitor and the first resistor, where a second control voltage signal is applied to the output terminal. Additionally, the VCO includes a first PMOS device having a gate terminal which receives the first control voltage signal, a second PMOS device having a gate terminal which receives the first control voltage signal, a third PMOS device having a gate terminal which receives the second control voltage signal, and a fourth PMOS device having a gate terminal which receives the second control voltage signal. Also, the VCO further includes an output terminal on which an output frequency signal is placed. Furthermore, the VCO includes a divider circuit operatively connected to the output terminal of the VCO and to the phase-frequency detector, where the divider circuit reduces a frequency of the output frequency signal to thereby generate the feedback frequency signal. 
         [0032]    In further embodiments of the above circuit, a first ratio of the third PMOS device to the first PMOS device is K:1, wherein K is a predetermined value and wherein K&gt;1. In still further embodiments, a second ratio of the fourth PMOS device to the second PMOS device is K:1. In yet further embodiments, a second terminal of the first PMOS device is operatively connected to a second terminal of the third PMOS device. In some embodiments, the said phase-frequency detector detects a difference between a phase of a reference signal and a phase of a feedback signal to thereby produce the frequency control signal. 
         [0033]    In other embodiments, the second terminal of the first PMOS device is operatively connected to a second resistor where the second resistor is operatively connected to a first voltage source. Yet other embodiments include a first switch operatively connected in parallel with the second resistor. In still other embodiments, a second terminal of the second PMOS device is operatively connected to a second terminal of the fourth PMOS device. In still other embodiments, the second terminal of the second PMOS device is operatively connected to a third resistor where the third resistor is operatively connected to the first voltage source. In yet still other embodiments, a second switch is operatively connected in parallel with the third resistor. 
         [0034]    According to yet another embodiment of the present subject matter, a VCO circuit includes a phase-frequency detector which detects a difference between a reference frequency signal and a feedback frequency signal to thereby produce a frequency control signal, a charge pump which receives the frequency control signal and generates a control current signal therefrom, a low pass filter operatively connected to the charge pump where the low pass filter integrates the control current signal and generates a first control voltage signal therefrom, and where the low pass filter includes a first capacitor operatively connected to a first resistor, and an output terminal operatively connected to a junction between the first capacitor and the first resistor, where a second control voltage signal is applied to the output terminal. Additionally, the VCO includes a first NMOS device having a gate terminal which receives the first control voltage signal, a second NMOS device having a gate terminal which receives the first control voltage signal, a third NMOS device having a gate terminal which receives the second control voltage signal, a fourth NMOS device having a gate terminal which receives the second control voltage signal. Also, the VCO further includes an output terminal on which an output frequency signal is placed. Furthermore, the VCO includes a divider circuit operatively connected to the output terminal of the VCO and to the phase-frequency detector, where the divider circuit reduces a frequency of the output frequency signal to thereby generate the feedback frequency signal. 
         [0035]    In certain further embodiments of the above circuit, a first ratio of the first NMOS device to the third NMOS device is K:1, where K is a predetermined value and where K&gt;1. In still further embodiments, a second ratio of the second NMOS device to the fourth NMOS device is K:1. 
         [0036]    While some embodiments of the present subject matter have been described, it is to be understood that the embodiments described are illustrative only and that the scope of the invention is to be defined solely by the appended claims when accorded a full range of equivalence, many variations and modifications naturally occurring to those of skill in the art from a perusal hereof.