Abstract:
A charge transfer device has one or more charge injection areas each having an input diffusion layer and two or more input gate electrodes. An input signal is applied to the input diffusion layer, a clock voltage is applied to one of the input gates and an input reference voltage is applied to the other input gate to inject a signal charge proportional to a difference between the input reference voltage and the input signal, and the signal charge is sequentially transferred. A magnitude of the input reference voltage is changed in accordance with a magnitude of a maximum value of the input signal so that transfer of charges which do not contribute to signal component is suppressed and a transfer efficiency is improved.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a signal transfer system which prevents charges which do not change with time from being injected as signal charges in order to prevent saturation of transfer charges and which is particularly suitable to a tapped, charge coupled device (CCD). 
     As is well known, a CCD has a semiconductor substrate and electrodes insulated from the substrate and serially transfers signal charges of minority carriers stored in potential wells formed in the semiconductor substrate beneath the electrodes, in a longitudinal direction of a channel by applying a multiphase voltage to the electrodes. It has many applications in the field of signal processing such as a delay line for an analog signal. 
     Two methods for injecting signal charges to the CCD, are the diode cutoff method and the potential balance method which are disclosed in a Japanese version of &#34;Charge Transfer Devices&#34; by C. H. Sequin and M. F. Tompsett, in Bell Telephone Lab. in U.S.A., published Feb. 20, 1978, pages 42-46. However, neither of those methods teaches an efficient way to transfer charges nor suppression of transfer of spurious charges other than signal charges. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a signal transfer system having an improved transfer efficiency for charges used as signal components. 
     In accordance with the present invention, there is provided means for shifting the load line of an input signal in accordance with a change of a direct current component (mean value) or a peak value of an input signal waveform applied to a charge transfer device so that a peak of the input signal is held at a level which prevents charges which are not a function of the input signal useless from being injected. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a circuit diagram of a first embodiment of the present invention, 
     FIG. 2 shows waveforms for illustrating phase relations among clocks, 
     FIG. 3 illustrates transfer of charges, 
     FIG. 4 shows the relationship between an input signal and a signal actually inputted to a charge transfer device, 
     FIG. 5 shows a relation between a control voltage and an input signal, 
     FIG. 6 shows a circuit diagram of a second embodiment of the present invention, 
     FIG. 7 shows waveforms of an input signal and an input clock signal, 
     FIG. 8 shows waveforms for illustrating phase relations among clocks, 
     FIG. 9 illustrates transfer of charges, and 
     FIG. 10 shows a circuit diagram of a main portion of a third embodiment of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 shows a circuit diagram of one embodiment of the present invention. In FIG. 1 numeral 1 denotes a signal source, numeral 2 denotes a gate clock source, numeral 10 denotes a p-type silicon substrate, numeral 11 denotes an oxidized silicon layer, numeral 12 denotes an n-type diffusion layer and numerals 13-22 denote gate electrodes which are usually made of aluminum or poly-crystalline silicon. The oxidized silicon layer 11 insulates the substrate 10 from the gate electrodes 13-22. V in  denotes an input signal voltage applied to the diffusion layer 12, V DD  denotes a direct voltage, φ G  denotes a gate clock, V in  min denotes an input reference direct bias voltage applied to the gate 14, and φ 1  and φ 2  denote charge transfer clocks. The n-MOSFET&#39;s 51 and 53 and a load resistor 61 form a peak voltage detection circuit 80A, and n-MOSFET&#39;s 55 and 57 and a load resistor 63 form a gain control circuit 80. 
     The diode cutoff method is first explained. To this end, let us assume that the input reference voltage V in  min is not applied to the electrode 14, that is, the electrode 14 is connected to a fixed power supply of a voltage V CC . 
     FIG. 2 shows amplitudes and phases of the clocks φ 1 , φ 2  and φ G  shown in FIG. 1. FIGS. 3(a), 3(b), 3(c) and 3(d) illustrate an operation of the CCD input area shown in FIG. 1 FIG. 3(a) is a diagram in the vicinity of a substrate surface of the input area and FIGS. 3(b) and 3(c) illustrate potentials in the substrate beneath the gate electrodes 13-22 and movement of charges at times t 1 , t 2  and t 3  shown in FIG. 2. The input signal is applied to the n+-type diffusion layer 12 and the gate electrode 18 is opened at the time t 1  by the gate clock φ G  so that a charge proportional to the amplitude of the input signal is filled under the gate electrode 14 to which the input reference voltage V CC  is applied. At the time t 2 , the gate electrode 18 is closed by the gate clock φ G  and a signal charge Q sig  is stored in a potential well formed by the gate electrodes 18, 14 and 19. This signal charge is transferred sequentially by the transferring clocks φ 1  and φ 2  after the time t 3  as shown in FIG. 3(d). The above operation is repeated so that signal charges Q sig  representing the amplitudes of the input signal voltages V in  are sequentially inputted to the CCD. The relationship between an internal potential φ in  and the signal charge Q sig  is shown in FIG. 4, where φ in  is an internal potential under the n-type diffusion layer 12 and φ cc  is an internal potential under the gate electrode 14. When φ in  &gt;φ cc , the internal potential under the gate electrode 14 in FIG. 3(b) is smaller than the internal potential φ in  under the n-type diffusion layer 12 and hence the charge is not filled under the gate electrode 14 at the time t 1 . Accordingly, Q sig  =0 at the time. When φ o  ≦φ in  &lt;φ cc , Q sig  changes linearly with respect to φ in . When φ in  &lt;φ o , Q sig  is larger than a maximum stored charge Q max  in the potential well at the transfer area of the CCD, saturation occurs. Accordingly, in order to secure a dynamic range, the mean value of the input signal is set such that the internal potential under the n-type diffusion layer 12 assumes φ DC  shown in FIG. 4. 
     When a signal shown by a broken line in FIG. 4 is transferred under such a condition, Q&#39; o  -Q o  is transferred as a spurious charge. Thus, in a charge transfer device like a tapped CCD delay line in which charges supplied from respective taps to a main transfer path are combined in the main transfer path, spurious charges from the respective taps are combined and the main transfer path saturates. 
     As a result, in the circuit of FIG. 1, the voltage of the electrode 14 is controlled in accordance with a peak value of the input voltage V in  and a load line (L in FIG. 4) is shifted so that the charge corresponding to the peak value always assumes a minimum charge Q o . 
     V&#39; in  is an input signal to the gain control circuit 80, V&#39; in  min is a minimum voltage of the input signal V&#39; in , V con  is a control voltage to control the gain of the gain control circuit 80 and the gain of the peak voltage detection current 80A, and V 10  and V 20  are direct voltages. FIG. 5 shows a relation between the output (or input to the CCO voltage V in  of the gain control circuit 80 and the control voltage V con . In FIG. 5, curve 1 shows a waveform of the output voltage V in  when the control voltage V con  is V 1 , curve 2 shows a waveform of the output voltage V in  when the control voltage V con  is V 2 , and V G1  is a maximum voltage of the waveform 1. In the Peak voltage detection circuit 80A, the control voltage V con  is applied to the gate of the n-MOSFET 51 and the minimum voltage V&#39; in  min of the input signal V&#39; in  is applied to the gate of the n-MOSFET 53. By selecting the resistance of the resistor 61 to be equal to that of the resistor 63, the peak voltage detection circuit 80A produces an output voltage which substantially follows a curve designated by the parameter V&#39; in  min in FIG. 5. Thus, the output voltage V in  min is always coincident with the maximum of the output signal V in  of the gain control circuit 80. The bias voltages V 10  and V 20  are selected such that a difference therebetween is equal to a difference between the potential under the diffusion layer 12 and the potential under the gate electrode 14. 
     Since the voltage applied to the gate electrode 14 changes in accordance with the peak value of the input voltage V in , the load line also changes as shown by L and L&#39; in accordance with the peak value of the input voltage V in  so that the minimum value of the transfer charge is always maintained at Q o . From a standpoint of high transfer efficiency, it is desirable that the minimum charge Q o  is zero, but a certain direct current component is added in order to eliminate an influence by a non-linear portion of a rising region of the load line. 
     FIG. 6 shows a circuit diagram for the potential balance method. In FIG. 6 numeral 3 denotes a signal source, numeral 4 denotes a clock source, numeral 60 denotes a p-type silicon substrate, numeral 61 denotes an oxidized silicon layer, numeral 62 denotes an n+-type diffusion layer, and numerals 163-172 denote gate electrodes, which are made of aluminum or polycrystalline silicon. The oxidized silicon layer 61 insulates the substrate from the gate electrodes 163-172. V in  is an input signal voltage, V DD , V&#39; CC  and V c  are direct voltages, φ 1  and φ 2  are charge transfer clocks, SP is a sampling clock and φ&#39; G  is a signal charge inputting clock. Numerals 80A&#39; and 80&#39; denote circuits which are similar to the peak voltage detection circuit 80A&#39; and the gain control circuit 80 shown in FIG. 1, and resistors 61 and 63 have the same resistance. Thus, the output voltage of the DC control circuit 80A is equal to the minimum output voltage of the gain control circuit 80&#39;. 
     In a switching circuit 100 comprising n-MOSFET&#39;s 96 and 97 and a p-MOSFET 98, the n-MOSFET 97 and the p-MOSFET 98 conduct and the n-MOSFET 96 does not conduct when the clock φ&#39; G  is at a high level. Thus, a voltage of an output clock φ&#34; G  is equal to the output voltage of the peak voltage detection circuit 80A&#39;. On the other hand, when the clock φ&#39; G  is at a low level, the n-MOSFET 96 conducts and the n-MOSFET 97 and the p-MOSFET 98 do not conduct, and the voltage of the clock φ&#34; G  is zero. Accordingly, the waveform of the clock φ&#34; G  assumes a waveform shown in FIG. 7. 
     In order to explain the potential balance method, let us assume that the clock φ&#39; G  is applied directly to the gate electrode 69. 
     FIG. 8 shows amplitudes and phases of the clocks φ 1 , φ 2 , SP and φ&#39; G  shown in FIG. 6. FIGS. 9(a), 9(b), 9(c) and 9(d) illustrate an operation of a charge injection area. FIG. 9(a) shows a diagram in the vicinity of the substrate surface in the input area shown in FIG. 6 and FIGS. 9(b)-9(d) show potentials in the substrate under the gate electrodes 163-172 and the movement of the charges at times t&#39; 0  -t&#39; 3  shown in FIG. 8. At the time t&#39; 0 , the internal potential under the n+-type diffusion layer 62 is at a level shown by a chain line in FIG. 9(b). At the time t&#39; 1 , the voltage of the sampling clock SP changes from V SPL  to V SPH  and the internal potential under the n-type diffusion layer 62 changes to a level shown by a solid line in FIG. 9(b) and a charge representing the magnitude of the input signal voltage V in  applied to the gate electrode 68 is stored in a potential well formed by the gate electrodes 64, 68 and 69. At the time t 2  &#39;, the voltage of the signal charge inputting clock φ&#39; G  applied to the gate electrode 69 changes from 0 to V G , and a signal charge Q sig  which is proportional to V G  -V in  is stored in a potential well formed by the gate electrodes 65, 69 and 70 as shown in FIG. 9(c). Thereafter, the signal charge Q sig  is sequentially transferred by the transfer clocks φ 1  and φ 2  as shown in FIG. 9(d). The above operation is repeated so that signal charges Q sig  representing the magnitudes of the input signal voltages V in  are sequentially injected to the CCD. 
     Since the load line shown in FIG. 4 is shifted by the clock voltage applied to the gate electrode 69, when the clock φ&#34; G  is applied to the gate electrode 69, the load line is shifted in accordance with the peak value of the input signal in the same manner as the previous embodiment so that the spurious charges are not injected. 
     If the signal applied to the charge transfer device has a constant amplitude and a varying direct current component, the spurious charge transfer can be reduced by a circuit shown in FIG. 10. 
     FIG. 10 shows a main portion of a third embodiment of the present invention. Numeral 150 denotes a pnp transistor, numeral 151 denotes a resistor, numeral 152 denotes a potentiometer, numeral 153 denotes a capacitor, and numeral 154 denotes a switch (actually a transistor because of a high drive frequency) which is set to an upper contact when the clock φ&#39; G  shown in FIG. 7 is at a high level and set to a lower contact when it is at a low level. The capacitor 153 serves to eliminate an AC component of the input signal V in , and the potentiometer 152 is initially set such that the high level of the output signal φ G  &#39; of the switching circuit 154 assumes the voltage satisfying the relationship between the internal potential φ DC  and φ cc  shown in FIG. 4. 
     Assume that the high level of the clock φ G  is equal to V G  when the direct-current component of the input signal voltage V in  is V in  DC. Then, the high level of the clock φ G  &#34; is smaller than V G  when the direct-current component of the input signal voltage V in  is smaller than V in  DC because the base voltage of the transistor 150 falls. Accordingly, the high level of the clock φ G  actually applied to the gate electrode 169 is proportional to the direct-current component of the input signal voltage V in .