Abstract:
The invention relates to the field of electronic circuit design technology, more particularly, to an AMOLED panel test circuit, by integrating the second test unit, the first test unit and the data line output unit together, and respectively achieves the test of the first test unit and the second test unit of the panel through switching on and off the transistor, avoids the problem that one of the test circuit needs to pass around the end of the panel because the test circuit is not integrated in prior art, which causes big line impedance, and increases the detection rate, and saves the cost.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application claims priority to and the benefit of Chinese Patent Application No. CN 201510443539.9, filed on Jul. 24, 2015, the entire content of which is incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    Field of the Invention 
         [0003]    The invention relates to the field of electronic circuit design technology, more particularly, to an AMOLED panel test circuit. 
         [0004]    Description of the Related Art 
         [0005]    AMOLED (Active-matrix organic light emitting diode, AMOLED for short) is a currently widely used display light emitting device, with the development of the technology, AMOLED technology matures gradually, and derives a lot of different types, such as AMOLED, Super AMOLED, Super AMOLED Plus, and Super AMOLED Advanced etc. 
         [0006]    With the maturity of AMOLED technology, the cost of AMOLED gradually decreases, high efficient test during the testing and productive process becomes particularly important, timely testing and timely solving not only improves the yield of the production, but also saves time and improves the efficiency. 
         [0007]    In current AMOLED, panel display test circuit and array substrate test circuit are separated: the array substrate test circuit tests the performance of the substrate before plating OLED, while the panel display test circuit tests the performance of the sub display test circuits after cutting. The array substrate test circuit tests the condition of every data line, while the panel display test circuit tests the same signals (e.g., monochrome red or green), using the way of shorting bar. With the increasing of PPI (pixels per inch), and by the method of rendering, a data line has different colors (like red and green) , then the signal of the data line is AC (alternating current) signal, the load of the panel display test circuit can&#39;t be too large, otherwise the panel display test circuit can&#39;t be driven, however currently, the panel display test circuit needs to pass around the end of the display panel, hence the line impedance is very large, and cause of that, testing AMOLED display panel efficiently and accurately becomes a big problem for those skilled in the art. 
       SUMMARY OF THE INVENTION 
       [0008]    In view of the above-mentioned problem, the invention provides an AMOLED panel test circuit, to achieve the test of the data line test unit by connecting the control unit and the data line test unit, and achieve the test of the display panel test unit by connecting the data line test unit and the display panel test unit, the technical solution specifically is:
       an AMOLED panel test circuit, comprising:   a data line output unit, comprising a plurality of data line output modules, each of the data line output modules comprising a plurality of groups of data line pairs, one end of each data line of each of the data line pairs being coupled to one end of each of the other data line of the data line pairs to form a joint, and the other uncoupled ends of each of the data lines of each of the data line pairs of the data line output modules being used to provide output data;   a first test unit, comprising a plurality of sub-control units, each of the sub-control units comprising a plurality of branches, each of the branches exclusively corresponding to one group of the data line pair of the data line output modules, the branch being connected to the joint of the data line pair corresponding to the branch;   a second test unit, comprising a plurality of input signal lines, each of the input signal lines exclusively corresponding to one group of the data line pair of the data line output modules, the input signal line being connected to the joint of the data line pair corresponding to the input signal line.       
 
         [0013]    The above-mentioned AMOLED panel test circuit, wherein the ejoint of the adjacent two data line output modules of the data line output unit are connected through a transistor, and the transistor is in the second test unit. 
         [0014]    The above-mentioned AMOLED panel test circuit, wherein during working stage that the first test unit tests the data line output unit, output from the input signal lines of the second test unit are invalid. 
         [0015]    The above-mentioned AMOLED panel test circuit, wherein each of the data line output modules only switches one of the transistors on to make each of the data line output modules only provide output data provided by one data line pair. 
         [0016]    The above-mentioned AMOLED panel test circuit, wherein the transistors of each data line output module connecting to the data lines are all switched on, to make all the data lines of each of the data line output modules output data. 
         [0017]    The above-mentioned AMOLED panel test circuit, wherein the sub-control units are switched off, to make the second test unit test the data line output unit. 
         [0018]    The above-mentioned AMOLED panel test circuit, wherein the sub-control units are switched off, and the transistors are switched on to make the second test unit test the data line output unit. 
         [0019]    The above-mentioned AMOLED panel test circuit, wherein the transistor, connecting to one of the data line pairs, of the data line output modules, to make only one of the data line pairs of each of the data line output modules provide output data. 
         [0020]    The above-mentioned AMOLED panel test circuit, wherein the transistors of the second test unit are all switched on, to make the data lines of the data line output modules all provide output data. 
         [0021]    An AMOLED panel test circuit, comprising:
       a data line output unit, comprising a plurality of data line output modules, each of the data line output modules comprising a plurality of groups of data line pairs, one end of each data line of each of the data line pairs being coupled to one end of each of the other data line of the data line pairs to form a joint, the other ends not coupled with other data lines being used to provide output data;   a first test unit, comprising a plurality of sub-control units, each of the sub-control units comprising a plurality of branches, each of the branches exclusively corresponding to one data line pair of the data line output modules, each of the branches connecting to the joint of the data line pair corresponding to the branch; and   a second test unit, comprising a plurality of input signal lines, each of the input signal lines exclusively corresponding to a data line pair of the data line output modules, each of the input signal lines being connected to the joint of the data line pair corresponding to it through a transistor.       
 
         [0025]    The above-mentioned AMOLED panel test circuit, wherein the joint of a data line pair of a data line output module of the data line output unit and the joint of a data line pair of the data line output module adjacent to said data line output module are connected to a level line through a transistor, wherein the level line controls on and off state of the transistor. 
         [0026]    The above-mentioned AMOLED panel test circuit, wherein output from the second test unit are invalid, to make the first test unit test the data line output unit. 
         [0027]    The above-mentioned AMOLED panel test circuit, wherein the data line output module switches one of the transistors on, to make each of the data line output modules provide output data provided by one data line pair. 
         [0028]    The above-mentioned AMOLED panel test circuit, wherein the transistors of the data line output modules connecting to the data lines are all switched on, to make data lines of the data line output modules all output data. 
         [0029]    The above-mentioned AMOLED panel test circuit, wherein the sub-control units are switched off, to make the second test unit test the data line output unit. 
         [0030]    The above-mentioned AMOLED panel test circuit, wherein the sub-control units are switched off, the input signal lines are all used to input signal, to make the second test unit test working stage of the data line output unit. 
         [0031]    The above-mentioned AMOLED panel test circuit, wherein by controlling the level line connecting to the data line pair, the transistor connecting to the level line are switched on, to make only one data line pair of each of the data line output modules provide output data. 
         [0032]    The above-mentioned AMOLED panel test circuit, wherein by controlling the level lines of the second test unit, all the transistors are switched on, to make the data lines of each of the data line output module of the data line output unit all provide output data. 
         [0033]    The advantages and beneficial effects of the invention: 
         [0034]    The invention integrates the second test unit, the first test unit and the data line output unit together, and respectively completes the test of the first test unit and the second test unit of the panel through switching on and off of the transistor, so as to avoid the problem that one of the test circuit needs to pass around the end of the panel because the test circuit is not integrated in prior art, which causes big line impedance, and increasing the detection rate, and save the cost. 
     
    
     
       BRIEF DESCRIPTIONS OF THE DRAWINGS 
         [0035]    The accompanying drawings, together with the specification, illustrate exemplary embodiments of the present disclosure, and, together with the description, serve to explain the principles of the present invention. 
           [0036]      FIG. 1  is a structure diagram of AMOLED panel test circuit of the invention; 
           [0037]      FIG. 2  is another structure diagram of AMOLED panel test circuit of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0038]    The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout. 
         [0039]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” or “includes” and/or “including” or “has” and/or “having” when used herein, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof. 
         [0040]    Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
         [0041]    As used herein, “around”, “about” or “approximately” shall generally mean within  20  percent, preferably within 10 percent, and more preferably within 5 percent of a given value or range. Numerical quantities given herein are approximate, meaning that the term “around”, “about” or “approximately” can be inferred if not expressly stated. 
         [0042]    As used herein, the term “plurality” means a number greater than one. 
         [0043]    Hereinafter, certain exemplary embodiments according to the present disclosure will be described with reference to the accompanying drawings. 
         [0044]    Referring to the structure shown in  FIG. 1 , the invention discloses an AMOLED panel test circuit, wherein the AMOLED panel test circuit comprises a first test unit  1 , a data line output unit  3  and a second test unit  2 , wherein: 
         [0045]    The data line output unit  3  has one or more data line output modules (such as but not limited to, the data line output module  31  and the data line output module  32  listed in  FIG. 1 ), each data line output module comprises one or more groups of data line pairs, one end of each data line of the data line pairs is coupled to one end of each of the other data line of the data line pairs to form a joint, and the other end, not coupled with other data lines, of each pair of the data lines of the data line output modules is used to provide output data. 
         [0046]    The first test unit  1  comprises one or more sub-control units; each sub-control unit comprises one or more branches; each branch corresponds to a data line pair; the branch is connected to the joint of the data line pair corresponding to the branch. The second test unit  2  comprises one or more input signal lines, the input signal lines correspond to the data line pairs of the data line output modules, the input signal line connects to the joint of the data line pair corresponding to the input signal line. 
         [0047]    As a preferred embodiment of the invention, the first test unit  1  of the AMOLED panel test circuit comprises four sub-control units; each sub-control unit comprises a transistor to control the switching-on or switching-off of the sub-control unit, each sub-control unit comprises a plurality of branches, each branch comprises a transistor; through the control of the sub-control units, all the data lines of the data line output unit are enabled to output data, or one or some of the data lines of the data line output unit are enabled to output data, and during the control process, the transistors of the second test unit are all switched off; when testing the second test unit, the transistors of the sub-control units of the first test unit and transistors of the branches are all switched off, through the control of transistors of the second test unit, the data lines of the data line output unit all or partly are enabled to output data. 
         [0048]    The following lists specific embodiments for illustrating: 
         [0049]    In a preferred embodiment of the invention, the input signal end PAD 1  of the first test unit are connected to the transistors as 21 , as 22 , as 23 , as 24  of the four sub-control units, and each transistor controls the data line output module exclusively corresponding to it by controlling the three transistors, namely the transistor as 21  controls the data line output module  31  by controlling the transistor M 1 , the transistor M 2 , and the transistor M 3 ; the transistor as 22  controls the data line output module  32  by controlling the transistor M 4 , the transistor M 5 , and the transistor M 6 , and so on so forth; the invention elaborates the first data line output module  31  and the second data line output module  32 , and principles of the subsequent multiple data line output modules are the same as the first data line output module  31  and the second data line output module  32 , so not repeat here. 
         [0050]    In a preferred embodiment of the invention, the data line output unit comprises four data line output modules, each data line output module comprises six data lines, namely three data line pairs; each data line pair is exclusively and correspondingly connected to a branch; for example the data line pair made up by the data line D 1  and the data line D 4  is exclusively and correspondingly connected to the branch which the transistor M 1  is connected to, the branch, which the transistor M 2  is connected to, is connected to the data line pair made up by the data line D 2  and the data line D 5 ; and so on so forth. 
         [0051]    In a preferred embodiment of the invention, the input signal lines  101 ,  102  and  103  included in the display panel test unit are respectively input signals DR, DG and DB; a transistor SW 2  is connected between the joint of first data line D 1  and the forth data line D 4  of the first data line output module  31  and the joint of the first data line D 7  and the forth data line D 10  of the second data line output module  32 ; and the first data line and the forth data line of the data line output module  31  and the data line output module  32 , which are connected with each other, are connected to the input signal line  101 , to input DR signal; likewise, a transistor SW 3  is connected between the connecting data line D 2  and the data line D 5  and the connecting data line D 8  and the data line D 11  of the second data line output module, and the second data line and the fifth data line are connected to the input signal line  103 , to input DG signal; a transistor SW 1  is connected between the data line D 3 , the data line D 6  and the data line D 9 , the data line D 12 , and the third data line and the sixth data line are connected to the input signal line  103 , to input DB signal. 
         [0052]    Firstly, input signals through the input signal end PAD 1 , switch off the transistor SW 1  through ps 1 , switch off the transistor SW 2  through ps 2  and switch off the transistor SW 3  through ps 3 , and each data line can receive signal from the input signal end PAD 1  and output the signal. 
         [0053]    Then control each data line to individually output signals received from the input signal end PAD 1 ; here list several specific examples to elaborate: 
         [0054]    Firstly, limit the data line D 1  to individually output signal, since the test at this point is the test for the first test unit, so now continue to switch the transistor SW 1  off, the transistor SW 2  off and the transistor SW 3  off, to switch the transistor as 21  on, to switch the transistor as 22  off, the transistor as 23  off and the transistor as 24  off, then the branch controlled by the transistor M 4 , the transistor M 5  and the transistor M 6 , which is controlled by the transistor as 22 , is switched off, the branch controlled by the transistor M 7 , the transistor M 8  and the transistor M 9 , which is controlled by the transistor as 23 , is switched off; the branch controlled by the transistor M 10 , the transistor M 11  and the transistor M 12 , which is controlled by the transistor as 24 , is switched off, at this point only the data lines of the first data line output module output data, since the output signal from the first data line D 1  is only needed, only the transistor as 11  connecting to the first data line of the first data line output module is switched on, which is to make the first data line D 1  individually output signals; similarly, if to make the data line D 8  of the second data line output module individually output signal is needed, it only needs to switch the transistor as 22  and the transistor as 12  on, and switch the other transistors of the first test unit off, so as to achieve the limitation of making the second data line D 8  of the second data line output module individually output signal. 
         [0055]    By parity of reasoning, by achieving the individual outputting signal of each data line of the data line output module, the test for the first test unit is achieved. 
         [0056]    To continue to test the second test unit, switch all transistors of the first test unit  3  on, and switch off the transistor as 21  (or switch off the transistor Ml, M 2 , and M 3  controlled by the transistor as 21 ), the transistor as 22  (or switch off the transistor M 4 , M 5  and M 6  controlled by the transistor as 22 ), the transistor as 23  (or switch off the transistor M 7 , M 8  and M 9  controlled by the transistor as 23 ), the transistor as 24  (or switch off the transistor M 10 , M 11  and M 12  controlled by the transistor as 24 ) of the first test unit, switch on the transistor SW 1 , the transistor SW 2  and the transistor SW 3  of the second test unit; at this point, the input signal line  101  is connected to the first data line and the fourth data line of each data line output module, as shown in figure, the input signal line  101  is connected with the first data line D 1  of the first data line output module to the node NA 1 , and with the forth data line D 4  of the first data line output module to the node NA 2 , and with the first data line D 7  of the second data line output module to the node NB 1 , and with the forth data line D 10  of the second data line output module to the node NB 2 ; after inputting signal DR to the input signal line  101  of the second test unit, the first data line and the forth data line of each data line output module can output the input signal DR. 
         [0057]    Similarly, the input signal line  102  connects with the second data line D 1  of the first data line output module to the node NA 3 , and with the fifth data line D 4  of the first data line output module to the node NA 4 , and with the second data line D 7  of the second data line output module to the node NB 3 , and with the fifth data line D 10  of the second data line output module to the node NB 4 ; after inputting signal DG to the input signal line  102  of the second test unit, the second data line and the fifth data line of each data line output module can output the signal DG, which is input to the input signal line  102 . 
         [0058]    Similarly, the input signal line  103  connects with the third data line D 1  of the first data line output module to the node NA 5 , and with the sixth data line D 4  of the first data line output module to the node NA 6 , and with the third data line D 7  of the second data line output module to the node NB 5 , and with the sixth data line D 10  of the second data line output module to the node NB 6 ; after inputting signal DB to the input signal line  103  of the second test unit, the third data line and the sixth data line of each data line output module can output the input signal DB. 
         [0059]    Namely, after respectively inputting signals DR, DG and DB to the input signal lines  101 ,  102  and  103 , then input signal lines having the same signal are connected together (such as D 1 , D 4 , D 7 , D 10  . . . Are connected together; D 2 , D 5 , D 8 , D 11  . . . are connected together; D 3 , D 6 , D 9 , D 12  . . . are connected together); at this point, to display red, green and blue image is achieved, and the test for the display panel test unit is complete. 
         [0060]    Referring to the structure shown in  FIG. 2 , the invention discloses another circuit structure which can achieve the same purpose of the above-mentioned embodiments, more specifically, the circuit structure comprises a first test unit  1 , a data line output unit  3  and a second test unit  2 , wherein:
       the data line output unit  3  has one or more data line output modules, each data line output module comprises one or more groups of data line pairs, one end of each data line of each of the data line pairs is coupled to one end of each of the other data line of the data line pairs to form a joint, and the other uncoupled end of each pair of the data lines of the data line output modules is used to provide output data.       
 
         [0062]    The first test unit  1  comprises one or more sub-control units, each sub-control unit comprises one or more branches, each branch corresponds to the data line pair of the data line output modules, each branch connects to the joint of the data line pair corresponding to the branch. The second test unit  2  comprises one or more input signal lines, each input signal line corresponds to a plurality of data line pairs of the data line output modules, the input signal line is connected to the joint of the data line pair corresponding to the input signal line. 
         [0063]    Since the circuit structure is exactly the same as the connection of the first test unit and the data line output unit of the preferred embodiments of the above-mentioned circuit structure, and only the second test unit is slightly changed, and the connecting way of the first test unit and the data line output unit which is the same as the above mentioned circuit structure, which is not repeated here. 
         [0064]    The following lists specific embodiments for elaborating: 
         [0065]    As shown in  FIG. 2 , the first data line D 1  and the fourth data line D 4  of the first data line output module  31  are connected to the input signal line  101  through the transistor SW 1 , the second data line D 2  and the fifth data line D 5  of the first data line output module are connected to the input signal line  102  through the transistor SW 2 , the third data line D 3  and the sixth data line D 6  of the first data line output module are connected to the input signal line  103  through the transistor SW 3 ; similarly, the first data line D 7  and the fourth data line D 10  of the second data line output module are connected to the input signal line  101  through the transistor SW 4 , the second data line D 8  and the fifth data line D 11  of the second data line output module are connected to the input signal line  102  through the transistor SW 5 , the third data line D 9  and the sixth data line D 12  of the second data line output module are connected to the input signal line  103  through the transistor SW 6 , wherein the input signal lines  101 ,  102  and  103  respectively input the signals DR, DG and DB. 
         [0066]    Firstly, the input signal end PAD 1  inputs signals to the  24  data lines of the data line output unit, then switch on the transistor as 21 , the transistor as 22 , the transistor as 23  and the transistor as 24  of the first test unit, so the transistors of the branches controlled by each transistor of the 4 transistors are switched on, namely the transistors M 1 , M 2 , . . . M 11 , M 12  are all switched on; and switch off the transistors SW 1 , SW 2 , . . . SW 4 , SW 5  . . . of the second test unit by the level lines ps 1 , ps 2  and ps 3 , so all transistors as 11 , as 12  . . . of the data line output unit connecting to data lines are switched on, then the input signal end PAD 1  inputs signals to each data line, and each data line of the data line output unit outputs signals. 
         [0067]    Here the input signal end PAD 1  inputs signals to each data line will be listed as a few examples to illustrate. 
         [0068]    Firstly, the input signal end PAD 1  individually inputs signals to the second data line D 2  of the first data line output module; then continue to switch off the transistors SW 1 , SW 2 , . . . SW 4 , SW 5  . . . of the second test unit, switch on the transistor as 21 , and switch off the transistor as 22 , the transistor as 23  and the transistor as 24 , so the transistors M 1 , M 2  and M 3  are all switched on, and the branches controlled by the transistors M 4 , M 5 , . . . M 11 , M 12  are all switched off; at this point, only the data lines of the first data line output module have input signal; when the transistors as 11, the transistor as 13 , the transistor as 14 , the transistor as 15  and the transistor as 16  of the first data line output module are switched off, only the second data line D 2  of the first data line output module has input signals; similarly, if we just need to input signals to the third data line D 9  of the second data line output module, switch on the transistor as 22 , and switch off the transistor as 21 , the transistor as 23  and the transistor as 24 , so the transistors M 4 , M 5  and M 6  are all switched on, and the branches controlled by the transistors Ml, M 2 , M 3 , M 6 , M 7 , . . . M 11 , M 12  are all switched off, at this point, only data lines of the second data line output module have input signals, when switch off the transistors as 11 , the transistor as 12 , the transistor as 14 , the transistor as 15  and the transistor as 16  of the second data line output module, only the third data line D 9  of the second data line output module has input signal. 
         [0069]    Continue to test the second test unit; input the signal DR to the input signal line  101 , input the signal DG to the input signal line  102 , and input the signal DB to the input signal line  103 ; if we just need to output display signal to the first data line and the fourth data line of each data line output module, we just need to switch on the transistors like the transistor SW 1  and SW 4  connecting to the first data line and the fourth data line by the control of the level line ps 1 , and switch off transistors like the transistor SW 2 , SW 3 , SW 5  and SW 6  connecting to the second data line and the fifth data line by the control of the level lines ps 2  and ps 3 , then only the first data line and the fourth data line output signal. 
         [0070]    Similarly, if we just need to output display signals to the second data line and the fifth data line of each data line output module, we just need to switch on transistors like the transistor SW 2  and SW 5  connecting to the second data line and the fifth data line by the control of the level line ps 2 , and switch off transistors like the transistor SW 1  and SW 4  connecting to the first data line and the fourth data line by the control of the level line ps 1 , and switch off transistors like the transistor SW 3  and SW 6  connecting to the third data line and the sixth data line by the control of the level line ps 3 ; if we just need to output display signals to the third data line and the sixth data line of each data line output module, we just need to switch on transistors like the transistor SW 3  and SW 6  connecting to the third data line and the sixth data line by the control of the level line ps 3 , and switch off other transistors of the second test unit by the control of level lines; and if we need to output display signals to all data lines of the data line output unit to let them output signals, we just need to input the signal DR to the input signal line  101 , input the signal DG to the input signal line  102 , and input the signal DB to the input signal line  103 , and meanwhile switch on transistors like the transistor SW 1  and SW 4  connecting to the first data line and the fourth data line by the control of the level line ps 1 , and switch on transistors like the transistor SW 2  and SW 5  connecting to the second data line and the fifth data line by the control of the level line ps 2 , and switch on transistors like the transistor SW 3  and SW 6  connecting to the third data line and the sixth data line by the control of the level line ps 3 , then we can achieve displaying red, green and blue image. 
         [0071]    In conclusion, the invention integrates the second test unit, the first test unit and the data line output unit together, and respectively achieves the test of the first test unit and the second test unit of the panel through switching on and off of the transistor, so as to avoid the problem that one of the test circuit needs to pass around the end of the panel because the test circuit is not integrated in prior art, which causes big line impedance, and to increase the detection rate, and save the cost. 
         [0072]    The foregoing is only the preferred embodiments of the invention, not thus limiting embodiments and scope of the invention, those skilled in the art should be able to realize that the schemes obtained from the content of specification and figures of the invention are within the scope of the invention.