Abstract:
Regardless of data values stored on data memory cells, all read operations on the data memory cells are disallowed. For example, current flow is disallowed through a string of the data memory cells and one or more select line memory cells. The particular select value stored in a first select line memory cell in the string, for example coupled to a ground select line or a string select line, determines whether the string is enabled or disabled.

Description:
PRIORITY APPLICATION 
       [0001]    This application is a continuation of U.S. patent application Ser. No. 13/289,944, filed 4 Nov. 2011 and is incorporated herein by reference. 
     
    
     BACKGROUND 
       [0002]    1. Field of the Invention 
         [0003]    This technology relates to indicating bad memory areas, such as bad memory blocks. 
         [0004]    2. Description of Related Art 
         [0005]    Present approaches to store bad block information require extra memory cells that consume extra area on an integrated circuit, or fuses that also consume extra area on an integrated circuit. 
       SUMMARY 
       [0006]    One aspect of the technology is an integrated circuit apparatus, comprising a plurality of memory cells, a plurality of word lines, and a first select line. 
         [0007]    The plurality of memory cells are arranged between a first end and a second end of a string. The string includes data memory cells and one or more select line memory cells. In one embodiment, the first end of the string is electrically connected to a bit line and the second end of the string is electrically connected to a common source line. In another embodiment, one or both ends of the string is a virtual ground. The virtual ground is positioned at an intermediate node of a series of connected memory cells. When the virtual ground is set to ground, for example, the virtual ground divides the series of connected memory cells into different strings on either side of the virtual ground node. 
         [0008]    The plurality of word lines are between the first end and the second end of the string. Word lines in the plurality are coupled to corresponding data memory cells in the string. The data memory cells store data accessed by a read operation. 
         [0009]    The first select line is coupled to a first select line memory cell in the string. The first select line is between the first end and the second end of the string. In one embodiment, the first select line is between the plurality of word lines and one of the first end and the second end of the string. In one embodiment, the first select line is one of a ground select line and a string select line. In this case the select line memory cell is a transistor coupled to the ground select line or a transistor coupled to the string select line. 
         [0010]    The control circuitry applies a bias arrangement that stores a first select value in the first select line memory cell. The first select value disallows all read operations on the data memory cells. This can disallow current flow through the string, regardless of data values stored on the data memory cells. For example, current flow through the string is disallowed in a read operation, regardless of any data value stored by the memory cell selected for reading. 
         [0011]    In contrast, in a typical read operation, current flows through the string depending on the data value and corresponding threshold voltage range stored on the data memory cell in the string undergoing a read operation. 
         [0012]    In some embodiments the string is a NAND string. 
         [0013]    In one embodiment, the first select value in the first select line memory cell indicates that the string of the memory cells is a bad memory area. In one embodiment, the first select value in the first select line memory cell corresponds to a first threshold voltage range—such as high threshold voltage Vt—in the first select line memory cell that prevents current from flowing through the first select line memory cell, despite the control circuitry applying a pass voltage of a read bias arrangement to the first select line. However, the pass voltage is sufficient to allow current to flow for other select values in the first select line memory cell, such as a second select corresponding to a low threshold voltage Vt. 
         [0014]    The first select line memory cell can store the second select value, for example corresponding to a low threshold voltage Vt. In one embodiment, responsive to the first select line memory cell storing the second select value different from the first select value, current is allowed to flow through the first select line memory cell, when the control circuitry performs the read operation on a selected one of the data memory cells by applying a read bias arrangement. In one embodiment, the read bias arrangement includes a read voltage to a selected word line coupled to the selected one of the data memory cells, and a pass voltage to the first select line and to other word lines coupled to unselected ones of the data memory cells. In one embodiment, the first select value corresponds to a first threshold voltage range (such as high threshold voltage Vt) in the first select line memory cell that prevents current from flowing through the first select line memory cell responsive to the control circuitry applying a pass voltage of the read bias arrangement to the first select line, and the second select value corresponds to a second threshold voltage range (such as low threshold voltage Vt) in the first select line memory cell that allows current to flow through the first select line memory cell responsive to the control circuitry applying the pass voltage of the read bias arrangement to the first select line. 
         [0015]    One embodiment further comprises a second select line. For example, the first and second select lines are the ground select line and the string select line. In one embodiment, the second select line is between the first end and the second end of the string. The second select line is coupled to a second select line memory cell of the one or more select line memory cells, and the second select line memory cell selectively stores the first select value that disallows all read operations on the data memory cells from causing current flow through the string. 
         [0016]    Another aspect of the technology is a method, comprising:
       regardless of data values stored on data memory cells, disallowing all read operations on a string of the data memory cells and one or more select line memory cells, by storing a first select value in a first select line memory cell in the string, wherein the data memory cells are accessed by a plurality of word lines between a first end and a second end of the string and the first select line memory cell is accessed by a first select line between the first end and the second end of the string.       
 
         [0018]    Other embodiments are described herein. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0019]      FIG. 1  is an example of a transistor having a threshold voltage that indicates whether a particular part of a memory array is bad, with a bad block enable signal. 
           [0020]      FIG. 2  is another example of a transistor having a threshold voltage that indicates whether a particular part of a memory array is bad, with a bad block enable signal. 
           [0021]      FIG. 3  is an example of a fuse structure having that indicates whether a particular part of a memory array is bad, with a bad block enable signal. 
           [0022]      FIG. 4  is a block diagram of a memory array with extra memory cells that indicate, upon power on or reset, whether particular parts of a memory array are bad, with multiple bad block enable signals. 
           [0023]      FIG. 5  is a timing diagram of supply voltage and the power on reset signal for the memory array of  FIG. 4 . 
           [0024]      FIG. 6  is a block diagram of a block decoder that processes an address signal and a bad block enable signal, to generate a select signal that enables a memory area. 
           [0025]      FIG. 7  is a more detailed block diagram of a block decoder that processes an address signal and a bad block enable signal, to generate a select signal that enables a memory area. 
           [0026]      FIG. 8  is a circuit diagram showing that the select signal enables a memory area. 
           [0027]      FIG. 9  is a circuit diagram showing that a select memory cell coupled to a ground select line is programmed to disable a memory area. 
           [0028]      FIG. 10  is a circuit diagram showing that a select memory cell coupled to a ground select line, shown in  FIG. 9 , disables a memory area disallows a read operation. 
           [0029]      FIG. 11  is a circuit diagram showing that a select memory cell coupled to a string select line is programmed to disable a memory area. 
           [0030]      FIG. 12  is a circuit diagram showing that a select memory cell coupled to a string select line, shown in  FIG. 11 , disables a memory area and disallows a read operation. 
           [0031]      FIG. 13  is a circuit diagram showing that select memory cells coupled to a string select line and a ground select line are programmed to disable a memory area. 
           [0032]      FIG. 14  is a circuit diagram showing that select memory cells coupled to a string select line and a ground select line, shown in  FIG. 13 , disable a memory area and disallow a read operation. 
           [0033]      FIG. 15  is a circuit diagram showing that select memory cells coupled to a string select line and a ground select line enable a memory area, and allow a read operation to be performed on a data memory cell storing a high threshold voltage. 
           [0034]      FIG. 16  is a circuit diagram showing that select memory cells coupled to a string select line and a ground select line enable a memory area, and allow a read operation to be performed on a data memory cell storing a low threshold voltage. 
           [0035]      FIG. 17  is a block diagram of an integrated circuit with a memory array that indicates bad memory areas using memory cells accessed by SSL and/or GSL lines. 
       
    
    
     DETAILED DESCRIPTION 
       [0036]      FIG. 1  is an example of a transistor having a threshold voltage that indicates whether a particular part of a memory array is bad, with a bad block enable signal. 
         [0037]    The p-type transistor MP 0  and n-type transistor MN 0  are in series between supply voltage VDD and ground GND. The p-type transistor MP 1  and n-type transistor MN 1  are in series between supply voltage VDD and ground GND. 
         [0038]    The shared node coupled to the drain terminals of p-type transistor MP 0  and n-type transistor MN 0  is coupled to the gate of p-type transistor MP 1 . The shared node coupled to the drain terminals of p-type transistor MP 1  and n-type transistor MN 1  is coupled to the gate of p-type transistor MP 0 , and outputs the bad block enable signal BBEN. The gates of n-type transistors MN 0  and MN 1  are coupled to the supply voltage VDD. 
         [0039]    When n-type transistor MN 0  stores a high threshold voltage Vt, then bad block enable signal BBEN is GND. When n-type transistor MN 1  stores a high threshold voltage Vt, then bad block enable signal BBEN is VDD. 
         [0040]    The example in  FIG. 1  consumes the chip area required by the extra transistors as shown, for each memory area that requires a BBEN signal. 
         [0041]      FIG. 2  is another example of a transistor having a threshold voltage that indicates whether a particular part of a memory array is bad, with a bad block enable signal. 
         [0042]    The p-type transistor MP 0  and n-type transistor MN 0  are in series between supply voltage VDD and ground GND. The p-type transistor MP 1  and n-type transistor MN 1  are in series between supply voltage VDD and ground GND. 
         [0043]    The shared node coupled to the drain terminals of p-type transistor MP 0  and n-type transistor MN 0  is coupled to the gate of n-type transistor MN 1 . The shared node coupled to the drain terminals of p-type transistor MP 1  and n-type transistor MN 1  is coupled to the gate of n-type transistor MN 0 , and outputs the bad block enable signal BBEN. The gates of p-type transistors MP 0  and MP 1  are coupled to the ground GND. 
         [0044]    When p-type transistor MP 0  stores a high threshold voltage Vt, then bad block enable signal BBEN is VDD. When p-type transistor MP 1  stores a high threshold voltage Vt, then bad block enable signal BBEN is GND. 
         [0045]    The example in  FIG. 2  also consumes the chip area required by the extra transistors as shown, for each memory area that requires a BBEN signal. 
         [0046]      FIG. 3  is an example of a fuse structure having that indicates whether a particular part of a memory array is bad, with a bad block enable signal. 
         [0047]    Fuses F 0  and F 1  are in series between supply voltage VDD and ground GND. The node between the fuses F 0  and F 1  outputs the bad block enable signal BBEN. The fuse can be polysilicon or metal material. If fuse F 0  is cut, for example by a laser, the bad block enable signal BBEN is ground GND. If fuse F 1  is cut, for example by a laser, the bad block enable signal BBEN is the supply voltage VDD. 
         [0048]    The example in  FIG. 3  also consumes the chip area required by the extra fuses as shown, for each memory area that requires a BBEN bad block enable signal. 
         [0049]      FIG. 4  is a block diagram of a memory array with extra memory cells that indicate, upon power on or reset, whether particular parts of a memory array are bad, with multiple bad block enable signals.  FIG. 5  is a timing diagram of supply voltage and the power on reset signal for the memory array of  FIG. 4 . 
         [0050]    When the integrated circuit powers on, the supply voltage VDD ramps up from 0 V to VDD. The POR power on reset signal ramps up from 0 V to an intermediate value, and then activates the POR power on reset signal. The POR power on reset signal is received by the memory array, and activates the extra memory cells that store bad block data. Also activated is sense amplifier circuitry to output the BBEN bad block enable signal. The BBEN[k:0] bad block enable signal is multiple bits wide, to indicate the bad block status of multiple memory blocks. 
         [0051]      FIG. 6  is a block diagram of a block decoder that processes an address signal and a bad block enable signal, to generate a select signal that enables a memory area. 
         [0052]    A bad block enable signal BBEN and address signal Add[m:0] is received by the block decoder BLKDEC. The block decoder BLKDEC output the SELH signal to enable or disable a memory area such as a block. 
         [0053]      FIG. 7  is a more detailed block diagram of a block decoder, such as the block decoder of  FIG. 6 , that processes an address signal and a bad block enable signal, to generate a select signal that enables a memory area. 
         [0054]    A memory element, such as two inverters connected so that the input of one is connected to the output of the other, stores the incoming bad block enable signal BBEN. The output of the memory element is connected to the gate of n-type transistor MO. The n-type transistor MO is connected in series with other transistors that receive address decode signals. 
         [0055]    The n-type transistor MO and the n-type address decode transistors are in series with p-type transistors coupled to supply voltage VDD. When bad block enable signal BBEN is high, n-type transistor MO turns off, and the series of n-type transistors will not couple to ground regardless of the address decode results. The node between the p-type pull up transistors, which remains high at the supply voltage VDD, is coupled to an inverter input. The inverter output is low, and is provided to the input of a level shifter. The output of the level shifter SELH stays low, providing low gate voltage such that pass transistors remain off that would otherwise pass signals such as SSL, WL, and GSL to the memory array. 
         [0056]    When bad block enable signal BBEN is low, n-type transistor MO turns on, and the series of n-type transistors turn on depending the address decode results. With matching address decode signals, the node between the p-type pull up transistors, which is pulled down to ground, is coupled to an inverter input. The inverter output is high, and is provided to the input of a level shifter. The output of the level shifter SELH is high, providing sufficient gate voltage to turn on pass transistors that pass signals such as SSL, WL, and GSL to the memory array. 
         [0057]      FIG. 8  is a circuit diagram showing that the select signal enables a memory area. 
         [0058]    The output of the level shifter SELH is connected to pass transistors that pass signals such as SSL, WL, and GSL to the memory array. At the top of the figure, global string select line signal GSSL is coupled to a local string select line signal SSL by a pass transistor that is turned on by the output of the level shifter SELH. At the middle of the figure, global word line signals GWL[n:0] are coupled to a local word line signals WL[n:0] by pass transistors that are turned on by the output of the level shifter SELH. At the bottom of the figure, global ground select line signal GGSL is coupled to a local ground select line signal GSL by a pass transistor that is turned on by the output of the level shifter SELH. 
         [0059]      FIG. 9  is a circuit diagram showing that a select memory cell coupled to a ground select line is programmed to disable a memory area. 
         [0060]    Two NAND strings of memory cells are connected in series. The left NAND string is connected between bit line BL 0  and common source line CSL 0 . The right NAND string is connected between bit line BL 1  and common source line CSL 1 . The memory cells are accessed by word lines WL 0 , WL 1 , . . . WLn. String select line transistors connect the top end of the left NAND string to bit line BL 0 , and the top of the right NAND string to bit line BL 1 . Ground select line transistors connect the bottom end of the left NAND string to common source line CSL 0 , and the bottom end of the right NAND string to common source line CSL 1 . 
         [0061]    String select line SSL and word lines WL 0 , WL 1 , . . . WLn receive a pass voltage. Ground select line GSL receives a program voltage. The ground select line transistors are programmed to a high threshold voltage Vt, for example by FN programming. The string select line transistors are not programmed and remain at low threshold voltage Vt. 
         [0062]    In various embodiments, all NAND strings in a block are programmed as shown, multiple selected NAND strings are programmed as shown, or a single selected NAND strings is programmed as shown. 
         [0063]      FIG. 10  is a circuit diagram showing that a select memory cell coupled to a ground select line, shown in  FIG. 9 , disables a memory area disallows a read operation. 
         [0064]    A selected word line WL 1 , coupled to selected transistors for a read operation, receives a read voltage. The ground select line GSL, string select line SSL, and other unselected word lines WL 0 , WL 2 , . . . WLn receive a pass voltage. The high threshold voltage Vt which was programmed to the ground select line transistors causes the ground select line transistors to remain off when the ground select line GSL receives a pass voltage. The other transistors receiving the pass voltage are on. The NAND string fails to conduct current, regardless of the data value stored on the transistors coupled to word line WL 1 . 
         [0065]    In various embodiments, all NAND strings in a block are read as shown, multiple selected NAND strings are read as shown, or a single selected NAND strings is read as shown. 
         [0066]      FIG. 11  is a circuit diagram showing that a select memory cell coupled to a string select line is programmed to disable a memory area. 
         [0067]    The NAND strings of memory cells are connected as in  FIG. 9 . Ground select line GSL and word lines WL 0 , WL 1 , . . . WLn receive a pass voltage. String select line SSL receives a program voltage. The string select line transistors are programmed to a high threshold voltage Vt, for example by FN programming. The ground select line transistors are not programmed and remain at low threshold voltage Vt. 
         [0068]    In various embodiments, all NAND strings in a block are programmed as shown, multiple selected NAND strings are programmed as shown, or a single selected NAND strings is programmed as shown. 
         [0069]      FIG. 12  is a circuit diagram showing that a select memory cell coupled to a string select line, shown in  FIG. 11 , disables a memory area and disallows a read operation. 
         [0070]    A selected word line WL 1 , coupled to selected transistors for a read operation, receives a read voltage. The ground select line GSL, string select line SSL, and other unselected word lines WL 0 , WL 2 , . . . WLn receive a pass voltage. The high threshold voltage Vt which was programmed to the string select line transistors causes the string select line transistors to remain off when the string select line SSL receives a pass voltage. The other transistors receiving the pass voltage are on. The NAND string fails to conduct current, regardless of the data value stored on the transistors coupled to word line WL 1 . 
         [0071]    In various embodiments, all NAND strings in a block are read as shown, multiple selected NAND strings are read as shown, or a single selected NAND strings is read as shown. 
         [0072]      FIG. 13  is a circuit diagram showing that select memory cells coupled to a string select line and a ground select line are programmed to disable a memory area. 
         [0073]    The NAND strings of memory cells are connected as in  FIG. 9 . Both the string select line transistors and the ground select line transistors are programmed to a high threshold voltage Vt, for example by FN programming. For example, programming as shown in  FIG. 9  is followed by programming as shown in  FIG. 11 , or programming as shown in  FIG. 11  is followed by programming as shown in  FIG. 9 . 
         [0074]    In various embodiments, all NAND strings in a block are programmed as shown, multiple selected NAND strings are programmed as shown, or a single selected NAND strings is programmed as shown. 
         [0075]      FIG. 14  is a circuit diagram showing that select memory cells coupled to a string select line and a ground select line, shown in  FIG. 13 , disable a memory area and disallow a read operation. 
         [0076]    A selected word line WL 1 , coupled to selected transistors for a read operation, receives a read voltage. The ground select line GSL, string select line SSL, and other unselected word lines WL 0 , WL 2 , . . . WLn receive a pass voltage. The high threshold voltage Vt which was programmed to the string select line transistors causes the string select line transistors to remain off when the string select line SSL receives a pass voltage. The high threshold voltage Vt which was programmed to the ground select line transistors causes the ground select line transistors to remain off when the ground select line GSL receives a pass voltage. The other transistors receiving the pass voltage are on. The NAND string fails to conduct current, regardless of the data value stored on the transistors coupled to word line WL 1 . 
         [0077]    In various embodiments, all NAND strings in a block are read as shown, multiple selected NAND strings are read as shown, or a single selected NAND strings is read as shown. 
         [0078]      FIG. 15  is a circuit diagram showing that select memory cells coupled to a string select line and a ground select line enable a memory area, and allow a read operation to be performed on a data memory cell storing a high threshold voltage. 
         [0079]    A selected word line WL 1 , coupled to selected transistors for a read operation, receives a read voltage. The ground select line GSL, string select line SSL, and other unselected word lines WL 0 , WL 2 , . . . WLn receive a pass voltage. The transistors receiving the pass voltage are on. The NAND string fails to conduct current, because the data value stored on the transistors coupled to word line WL 1  are associated with a high threshold voltage Vt. In other embodiments, only some or one of the transistors coupled to word line WL 1  are associated with a high threshold voltage Vt. 
         [0080]    In various embodiments, all NAND strings in a block are read as shown, multiple selected NAND strings are read as shown, or a single selected NAND strings is read as shown. 
         [0081]      FIG. 16  is a circuit diagram showing that select memory cells coupled to a string select line and a ground select line enable a memory area, and allow a read operation to be performed on a data memory cell storing a low threshold voltage. 
         [0082]    A selected word line WL 1 , coupled to selected transistors for a read operation, receives a read voltage. The ground select line GSL, string select line SSL, and other unselected word lines WL 0 , WL 2 , . . . WLn receive a pass voltage. The transistors receiving the pass voltage are on. The NAND string conduct current, because the data value stored on the transistors coupled to word line WL 1  are associated with a low threshold voltage Vt. In other embodiments, only some or one of the transistors coupled to word line WL 1  are associated with a low threshold voltage Vt. 
         [0083]    In various embodiments, all NAND strings in a block are read as shown, multiple selected NAND strings are read as shown, or a single selected NAND strings is read as shown. 
         [0084]      FIG. 17  is a block diagram of an integrated circuit with a memory array that indicates bad memory areas using memory cells accessed by SSL and/or GSL lines. 
         [0085]    An integrated circuit  1750  includes a memory array  1700 . A word line decoder  1701  is coupled to and in electrical communication with a plurality of word lines  1702  arranged along rows in the memory array  1700 . A bit line (column) decoder  1703  is in electrical communication with a plurality of bit lines  1704  arranged along columns in the array  1700 . Addresses are supplied on bus  1705  to the word line decoder  1701  and bit line decoder  1703 . In some embodiments the decoding circuitry for a memory block selects a GSL and/or SSL cell and one or more of the WL cells. Sense circuitry (sense amplifiers) and data-in structures in block  1706 , including voltage and/or current sources are coupled to bit line decoder  1703  via data bus  1707 . Data is supplied via a data-in line  1711  from input/output ports on integrated circuit  1750 , or from other data sources internal or external to integrated circuit  1750 , to data-in structures in block  1706 . Other circuitry may be included on integrated circuit  1750 , such as a general purpose processor or special purpose application circuitry, or a combination of modules providing system-on-a-chip functionality supported by array  1700 . Data is supplied via a data-out line  1715  from the sense amplifiers in block  1706  to input/output ports on integrated circuit  1750 , or to other data destinations internal or external to integrated circuit  1750 . 
         [0086]    A controller  1709  implemented in this example, using a bias arrangement state machine, controls the data stored in the memory cells accessed by SSL and GSL transistors, bias circuitry voltage and current sources  1708  for the application of bias arrangements including read, program, erase, erase verify and program verify voltages and/or currents for the word lines and bit lines. Controller  1709  may be implemented using special-purpose logic circuitry as known in the art. In alternative embodiments, controller  1709  comprises a general-purpose processor, which may be implemented on the same integrated circuit to execute a computer program to control the operations of the device. In yet other embodiments, a combination of special-purpose logic circuitry and a general-purpose processor may be utilized for implementation of controller  1709 . 
         [0087]    In some embodiments, the GSL and SSL cells replace a bad block table. 
         [0088]    Example memory cells are floating gate memory cells. Another type of memory cell can be referred to as a charge trapping memory cell, which uses a dielectric charge trapping layer in place of the floating gate. 
         [0089]    An example memory cell consists of a field effect transistor FET structure having a source and drain separated by a channel, and a gate separated from the channel by a charge storage structure including a tunnel dielectric layer, the charge storage layer (floating gate or dielectric), and a blocking dielectric layer. According to the charge trapping memory designs referred to as SONOS devices, the source, drain and channel are formed in a silicon substrate (S), the tunnel dielectric layer is formed of silicon oxide ( 0 ), the charge storage layer is formed of silicon nitride (N), the blocking dielectric layer is formed of silicon oxide ( 0 ), and the gate comprises polysilicon (S). 
         [0090]    Data is stored in a memory device by controlling the amount of charge trapped in the charge storage structure. The amount of charge stored sets a threshold voltage for the memory cell in memory devices, which allows the data to be read. An example programming mechanism is Fowler-Nordheim programming. 
         [0091]    In some embodiments the structure of the GSL and SSL cells is the same as the WL cells. In other embodiments the structure of the GSL and SSL cells is different from the WL cells. In yet other embodiments the structure of the GSL and SSL cells vary from the structure of the WL cells in that the transistor width and/or length are different. 
         [0092]    While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.