Abstract:
ESD protection circuit is provided, which includes a detection circuit, a trigger circuit and a clamp circuit. The detection circuit includes two stacked capacitors reflecting occurrence of ESD events. The trigger circuit includes three stacked transistors controlling triggering of the clamp circuit according to operation of the detection circuit. The clamp circuit includes two stacked transistors conducting ESD path when triggered.

Description:
This application claims the benefit of Taiwan application Serial No. 100102008, filed Jan. 19, 2011, the subject matter of which is incorporated herein by reference. 
     FIELD OF THE INVENTION 
     The present invention relates to an ESD protection circuit, and more particularly, to an ESD protection circuit applicable to high supply voltage with stack architecture of advanced devices. 
     BACKGROUND OF THE INVENTION 
     Semiconductor chips (dices, integrated circuits) are the most important building hardware in modern information society. Circuitry functional blocks of different functions are integrated into a chip, and different circuitry functional blocks have different requirements of supply voltage(s); therefore, different power domains are arranged inside the chip for providing different supply voltages. For example, input/output circuits of a chip for exchanging data and signals with external via input/output (I/O) pads need higher supply voltage of, e.g., 3.3 Volts; on the other hand, core circuit of a chip, such as logic operation circuitry, operates in lower supply voltage of, e.g., 1.8 Volts. Power required for chip operation is drained from external via power pads of a chip, and different supply voltages are transmitted to circuitry functional blocks of different power domains by various power rails inside the chip. 
     As semiconductor manufacture process evolves toward advanced process of deep sub-micron, advanced devices (e.g., transistors) of smaller area, lower power consumption and higher speed are utilized to construct circuitry functional blocks inside a chip. However, due to low voltage tolerance of advanced devices, advanced devices are suitable for circuitry functional blocks of low supply voltage rather than circuitry functional blocks of high supply voltage. 
     To prevent chip damage caused by electro-static discharge (ESD) during transportation, processing, assembly and testing, ESD protection mechanism is arranged in a chip, and the externally exposed power pads and I/O pads of a chip are key spots for implementation of the ESD protection mechanism. For example, an ESD protection circuit can be arranged between a first power rail and a second power rail, in cooperation with a conductive discharge path arranged between an I/O pad and the first power rail. With such arrangement, when an ESD event occurs between the I/O pad and a power pad of the second power rail, current of ESD can be conducted from the I/O pad to the first power rail by the discharge path, and then be conducted to the second power rail by the ESD protection circuit, so the current of ESD flows out of the chip via the power pad of the second power rail with other circuitry functional blocks bypassed, thus ESD protection is achieved. 
     In an ESD protection circuit of a prior art, two staked transistors are included; source-drain channels of the two transistors are serially connected between power rails of 3.3 Volts and 0 Volts (ground), and a gate is coupled to a power rail of 1.8 Volts. To work with such ESD protection circuit, an I/O circuit needs two p-channel metal-oxide-semiconductor (MOS) transistors stacked between the 3.3 Volts power rail and an I/O pad, and another two n-channel MOS transistors stacked between the I/O pad and the 0 Volts power rail. These two pairs of stacked transistors are not only used to drive signal output, but also used to conduct the I/O pad to the 3.3 Volts power rail or the 0 Volts power rail during ESD events. 
     A shortcoming of the prior art is that the ESD protection demands larger layout area to implement the two pairs of stacked MOS transistors, and therefore degrades chip integrity and enlarges total area of chip. 
     In an ESD protection circuit of another prior art, serial resistor-capacitor is arranged between the 3.3 Volts power rail and the 0 Volts power rail to detect whether ESD event occurs, a voltage at a node between the resistor and the capacitor is inverted by an inverter to control conduction of a clamp transistor. The inverter operates between the 3.3 Volts power rail and the 0 Volts power rail; a drain and a source of the clamp transistor are also coupled between the 3.3 Volts power rail and the 0 Volts power rail, and a gate is controlled by the inverter. 
     From the aforementioned description, it is recognized that these ESD protection circuits of prior arts need to operate under high supply voltage of 3.3 Volts, and are difficult to be implemented by advanced devices. 
     SUMMARY OF THE INVENTION 
     An objective of the invention is providing an ESD protection circuit having a first, a second and a third supply terminals, and including a detection circuit, a trigger circuit and a clamp circuit. The first, second and third supply terminals are arranged to couple to a first supply voltage, a second supply voltage and a base supply voltage, respectively. The first supply voltage is higher than the second supply voltage. 
     The detection circuit has a first respond terminal and a second respond terminal, and includes a first capacitor, a second capacitor, a first resistance circuit and a resistor. The first capacitor is coupled between the first respond terminal and the second respond terminal, the second capacitor is coupled between the second respond terminal and the third supply terminal. The first resistance circuit is coupled between the first supply terminal and the first respond terminal for providing a first equivalent resistance between the first supply terminal and the first respond terminal. The resistor is coupled between the second supply terminal and the second respond terminal. 
     The trigger circuit has a first trigger terminal and a second trigger terminal, and includes a first, a second and a third trigger transistors. The first trigger transistor is coupled between the first respond terminal, the first supply terminal and the first trigger terminal; the second trigger transistor is coupled between the second respond terminal, the first trigger terminal and the second trigger terminal; the third transistor is coupled between the second respond terminal, the second trigger terminal and the third supply terminal. 
     The clamp circuit has a first controlled terminal and a second controlled terminal respectively coupled to the first trigger terminal and the second trigger terminal, and includes a first clamp transistor, a second clamp transistor and a second resistance circuit. The first clamp transistor has a first gate, a first drain and a first source respectively coupled to the first controlled terminal, the first supply terminal and a first node. The second clamp transistor has a second gate, a second drain and a second source respectively coupled to the second controlled terminal, the first node and the third supply terminal. The second resistance circuit is coupled between the first controlled terminal and the second supply terminal for providing a second equivalent resistance between the first controlled terminal and the second supply terminal. 
     In the detection circuit, the first capacitor can be implemented by a p-channel MOS transistor having a first capacitor gate, a first capacitor source and a first capacitor drain respectively coupled to the second respond terminal, the first respond terminal and the first respond terminal. The second capacitor can be implemented by an n-channel MOS transistor having a second capacitor gate, a second capacitor source and a second capacitor drain respectively coupled to the second respond terminal, the third supply terminal and the third supply terminal. 
     In the trigger circuit, the first trigger transistor and the second trigger transistor can be p-channel MOS transistors, and the third trigger transistor can be an n-channel MOS transistor. 
     In the clamp circuit, the first clamp transistor and the second clamp transistor can be n-channel MOS transistors. 
     Numerous objects, features and advantages of the present invention will be readily apparent upon a reading of the following detailed description of embodiments of the present invention when taken in conjunction with the accompanying drawings. However, the drawings employed herein are for the purpose of descriptions and should not be regarded as limiting. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which: 
         FIG. 1  to  FIG. 3  respectively illustrate ESD protection circuits according to different embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Please refer to  FIG. 1  illustrating an ESD protection circuit  10   a  according to an embodiment of the invention. Nodes np 1 , np 2  and np 3  are supply terminals coupled to power rails PR 1 , PR 2  and PR 3  corresponding to supply voltages Vdd 1 , Vdd 2  and G for coupling the supply voltages Vdd 1 , Vdd 2  and G, respectively; wherein the supply voltage Vdd 1  is higher than the supply voltage Vdd 2 . For example, the supply voltages Vdd 1  and Vdd 2  can respectively be 3.3 Volts and 1.8 Volts, and the supply voltage G is ground supply voltage of 0 Volts. The ESD protection circuit  10   a  includes a detection circuit  12 , a trigger circuit  14  and a clamp circuit  16 . 
     The detection circuit  12  has nodes na 1  and na 2  as two respond terminals, and includes transistors MC 1  and MC 2 , a resistance circuit  17  and a resistor R 2 . The transistor MC 1  can be a p-channel MOS transistor has a gate coupled to the node na 2 , and has a source and a drain commonly coupled to the node na 1  for implementing a capacitor. The transistor MC 2  can be an n-channel MOS transistor has a gate coupled to the node na 2 , and has a source and a drain commonly coupled to the node np 3  for implementing another capacitor. The resistance circuit  17  includes a resistor R 1  coupled between the nodes np 1  and na 1 . The resistor R 2  is coupled between the nodes np 2  and na 2 . 
     The trigger circuit  14  has nodes nb 1  and nb 2  as two trigger terminals, and includes three transistors M 1 , M 2  and M 3 . The transistor M 1  and M 2  can be p-channel MOS transistors, the transistor M 3  can be an n-channel MOS transistor. A gate, a source and a drain of the transistor M 1  are respectively coupled to the nodes na 1 , np 1  and nb 1 , and a bulk is coupled to the node np 1 . A gate, a source and a drain of the transistor M 2  are respectively coupled to the nodes na 2 , nb 1  and nb 2 , and a bulk is coupled to the node np 1 . A gate, a source and a drain of the transistor M 3  are respectively coupled to the nodes na 2 , np 3  and nb 2 . 
     The clamp circuit  16  is coupled to the trigger circuit  14  at the nodes nb 1  and nb 2  which are also two controlled terminals, and includes two transistors N 1 , N 2  and a resistance circuit  18 . The transistors N 1  and N 2  can be n-channel MOS transistors; a gate, a drain and a source of the transistor N 1  are respectively coupled to the nodes nb 1 , np 1  and nc, a gate, a drain and a source of the transistor N 2  are respectively coupled to the nodes nb 2 , nc and np 3 . The resistance circuit  18  includes a resistor R 3  coupled between the nodes nb 1  and np 2 . 
     The ESD protection circuit  10   a  can be applied to a chip; with the ESD protection circuit  10   a  being adopted, only a simple a diode D 1  is used for implementing an ESD discharge path between a pad Pd (e.g., an I/O pad) and the power rail PR 1 ; there is no need to use stacked driving transistors in I/O circuit of the pad Pd. An anode and a cathode of the diode D 1  are respectively coupled to the pad Pd and the power rail PR 1 . Similarly, only a diode D 2  is installed between the power rail PR 3  and the pad Pd, with an anode and a cathode of the diode D 2  respectively coupled to the power rail PR 3  and the pad Pd. 
     ESD protection implemented by the ESD protection circuit  10   a  can be exemplarily described as follows. When an ESD event occurs between the pad Pd and the power rail PR 3  with a rapid voltage ramp at the pad Pd, the diode D 1  conducts, so the voltage at the power rail PR 1  also rises following the voltage at the pad Pd. In the detection circuit  12 , because the capacitor-resistor network of the transistors MC 1 , MC 2  and the resistors R 1 , R 2  does not instantaneously respond to the rapid voltage ramp of the power rail PR 1 , the voltages at the nodes na 1  and na 2  will maintain a low level (comparing to high level voltage of the power rail PR 1 ). Therefore, the transistors M 1  and M 2  turn on, and the high voltage of the power rail PR 1  is conducted to the nodes nb 1  and nb 2 , so the transistors N 1  and N 2  are triggered to turn on. The turned-on transistors N 1  and N 2  conducts the power rail PR 1  to the power rail PR 3 , such that ESD discharge current is conducted to the power rail PR 3  and flows out of the chip. In this way, ESD current will not flow to other circuitry functional blocks (not shown in  FIG. 1 ) in the chip to cause chip damage. 
     Contrary to ESD events, when the chip powers on for normal operation, the transistors N 1  and N 2  in the ESD protection circuit  10   a  will not turn on, so the power rail PR 1  is not erroneously conducted to the power rail PR 3 . During power-on of the chip, the voltages of the power rails PR 1  and PR 2  slowly rise to the supply voltages Vdd 1  and Vdd 2  respectively, so the capacitor-resistor network in the detection circuit  12  can fully respond, and the voltage at the node na 1  can track the voltage of the power rail PR 1 . Therefore, the transistor M 1  does not turn on. Similarly, the voltage at the node na 2  also tracks the voltage of the power rail PR 2 , so the transistor M 2  does not turn on. On the other hand, the transistor M 3  turns on to conduct the node nb 2  to the supply voltage G, such that the transistor N 2  remains off without conducting. Therefore, conduction between the power rails PR 1  and PR 3  is prevented. 
     When the voltages of the power rails PR 1  and PR 2  are steadily kept at the supply voltages Vdd 1  and Vdd 2  for normal operation of the chip, the voltage at the node na 2  is kept at the supply voltage Vdd 2  through the resistor R 2 , and the voltage at the node na 1  is kept at the supply voltage Vdd 1  through the resistor R 1 . Because a stack architecture of three transistors is adopted in the trigger circuit  14 , the voltages at the nodes nb 1  and nb 2  can be different; the voltage at the node nb 1  is kept at the supply voltage Vdd 2  by the resistor R 3 , and the voltage at the node nb 2  matches the supply voltage G due to conduction of the transistor M 3 . Therefore, gate-source voltage differences, gate-drain voltage differences and source-drain voltage differences of the transistors M 1 , M 2  and M 3  are kept below respect voltage tolerance of advanced devices. Accordingly, the ESD protection circuit  10   a  can be composed by advanced devices. 
     Please refer to  FIG. 2  illustrating an ESD protection circuit  10   b  according to another embodiment of the invention. The ESD protection circuit  10   n  includes a detection circuit  12 ′, as well as the trigger circuit  14  and the clamp circuit  16  of  FIG. 1 . Similar to the detection circuit  12 , the detection circuit  12 ′ includes two transistors MC 1  and MC 2  as two capacitors, as well as a resistor R 2 . For a difference, a resistance circuit  17 ′ in the detection circuit  12 ′ adopts a transistor MP to provide a variable equivalent resistance between the nodes np 1  and na 1 . The transistor MP can be a p-channel MOS transistor with a long channel; a gate, a source and a drain of the transistor MP are respectively coupled to the nodes nb 1 , np 1  and na 1 , and a bulk is coupled to the node np 1 . 
     When ESD event occurs, the transistor MP provides a high equivalent resistance between the nodes np 1  and na 1 . During normal operation of the chip, the transistor MP provides a low equivalent resistance between the nodes np 1  and na 1 , so the voltage at the node na 1  can approach (and track) the supply voltage Vdd 1  at the node np 1 , and leakage current drained from the power rail PR 1  by the transistors M 1  to M 3  is reduced. 
     Please refer to  FIG. 3  illustrating an ESD protection circuit  10   c  according to another embodiment of the invention. The ESD protection circuit  10   c  adopts the detection circuit  12  and the trigger circuit  14  of  FIG. 1 , and also includes a clamp circuit  16 ′. Similar to the clamp circuit  16  of  FIG. 1 , the clamp circuit  16 ′ includes two transistors N 1  and N 2 ; for a difference, a resistance circuit  18 ′ in the clamp circuit  16 ′ adopts a transistor MN, which is a native device, to provide a variable equivalent resistance between the nodes nb 1  and np 2 . The transistor MN can be a MOS transistor of long channel; there are no carriers doped in the channel, so a threshold voltage for turning on the transistor MN is lowered to 0 Volts. A gate of the transistor MN is coupled to the node na 2 ; a source and a drain are coupled between the nodes np 2  and nb 1 . 
     During ESD event, the transistor MN provides a high equivalent resistance between the nodes np 2  and nb 1 . During normal operation of the chip, the transistor MN provides a low equivalent resistance between the nodes np 2  and nb 1  to absorb leakage current of the transistor M 1 , as well as displacement current through large capacitor between drain and gate of the transistor N 1 , therefore the voltage at the node nb 2  is ensured to closely approach the supply voltage G. 
     To sum up, comparing to prior arts, the invention loosens I/O circuit design constrains which are set for ESD protection mechanism, simplifies circuit architecture of 10 circuits, and reduces layout area of 10 circuits; in addition, the invention is suitable to be composed by advanced devices. 
     While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.