Abstract:
The present invention provides an integrated circuit (I.C.) with a de-coupling circuit. The de-coupling circuit includes a voltage divider that includes first and second divider elements. The first and second divider elements are coupled to positive and negative supply voltages, respectively. The first and second divider elements are coupled therebetween at a central node. The de-coupling circuit further includes a PMOSFET transistor and a NMOSFET transistor that have their gates coupled at the node. The PMOSFET and NMOSFET transistors have their sources, drains, and bulks thereof coupled to the positive and negative supply voltages, respectively.

Description:
BACKGROUND OF THE INVENTION 
     (1) Field of the Invention 
     The present invention generally relates to the field of electronic circuits. More specifically, the present invention relates to de-coupling circuits. 
     (2) Background Information 
     De-coupling capacitors are known in the art. Such capacitors may be used for de-coupling high-frequency noise voltages from a load circuit that may receive current from a power source. The noise is typically caused by the load current demand as well as the current source capability of the power supply circuit. 
     De-coupling of higher voltages may raise particular problems in the case where it is performed on-die by way of devices designed for a low-voltage process. Higher voltages may not be directly applied to on-die devices in a low voltage process because, as the applied voltage is increased, the devices to which the voltage is applied start degrading. In the case where the on-die de-coupling device is a transistor, the respective transistor may be degraded when operated beyond a prescribed range, i.e. when a higher voltage is applied thereto. In a particular instance, the behavior of a transistor in a Complementary Metal Oxide Semiconductor (CMOS) process depends upon the electric field to which the channel of the transistor may be subjected when a certain voltage is applied at the gate of the transistor. If a device such as a transistor is designed for a 3.3 volts process, and one needs to de-couple 4.6 volts, the gate oxide of the transistor operated at 4.6 volts may degrade over time, thus changing the characteristics of the device and consequently influencing the functionality of the device. 
     Accordingly, it is desirable to provide a reliable on-die de-coupling circuit using devices in a low-voltage process that in combination are able to handle higher voltages. It is desirable that the higher voltages applied to such de-coupling circuits do not cause a degradation of the on-die devices. It is also desirable that the de-coupling circuit consumes very little power. 
     SUMMARY OF THE INVENTION 
     In one embodiment the present invention includes an integrated circuit (I.C.) with a de-coupling circuit. The de-coupling circuit includes a voltage divider that includes first and second divider elements. The first and second divider elements are coupled to positive and negative supply voltages, respectively. The first and second divider elements are coupled therebetween at a node. The de-coupling circuit further includes a PMOS transistor and a NMOS transistor that have their gates coupled at the node. The PMOS and NMOS transistors have their sources, drains, and bulks thereof coupled to the positive and negative supply voltages, respectively. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features, aspects, and advantages of the present invention will become more fully apparent from the following Detailed Description, appended claims, and accompanying drawings in which: 
     FIG. 1 illustrates one embodiment of a de-coupling circuit according to the present invention; 
     FIG. 2 illustrates an alternative embodiment of the de-coupling circuit according to the present invention; 
     FIG. 3 illustrates a second alternative embodiment of the de-coupling circuit according to the present invention; and 
     FIG. 4 illustrates a circuit utilizing a de-coupling circuit according to the present invention. 
    
    
     DETAILED DESCRIPTION 
     In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. However, one having ordinary skill in the art should recognize that the invention may be practiced without these specific details. In some instances, well-known circuits, structures, and techniques have not been shown in detail to avoid obscuring the present invention. 
     FIG. 1 illustrates a de-coupling circuit  100  according to the present invention. The de-coupling circuit according to the present invention includes a divided de-coupling capacitive device  102  coupled between first and second terminals  106  and  108  (hereinafter referred to as “positive terminal  106  and negative terminal  108 ”). These terminals may be the positive and negative terminals of a power supply. Terminal  108  may be coupled to ground. 
     In one embodiment according to the present invention described herein, the divided de-coupling capacitor is an on-die de-coupling capacitor that includes capacitive devices  112  and  114  used in a low-voltage process for higher voltages. Moreover, in the embodiment of the present invention described herein capacitive devices  112  and  114  are implemented by way of PMOS device  112  and channel Metal Oxide Semiconductor Field Effect Transistor (PMOSFET) device  114 . PMOSFET device  112  has a source and drain thereof coupled together and to the positive terminal  106 . A gate of PMOSFET device  112  is coupled to a common node  110 . A gate of NMOSFET device  114  is coupled to common node  110 . A source and drain of NMOSFET device  114  are commonly coupled to the negative terminal  108 . Transistors  114  and  112  connected in the configuration shown in the figure make up two capacitors that are coupled therebetween in series: the first capacitor is formed by the gate, the channel and the oxide of the transistor  112 ; and the second capacitor is formed by the gate, the channel, and the oxide of transistor  114 . The capacitors provided by transistors  112  and  114  perform optimally when transistors  112  and  114  are in full conduction. 
     The de-coupling circuit  110  further includes voltage divider  104 . Voltage divider  104  includes first and second divider elements  122  and  124 . In one embodiment according to the present invention, the voltage divider elements  122  and  124  are implemented by way of two substantially identical diodes  122  and  124  coupled in series. These diodes are coupled such that when a positive voltage is applied between terminals  106  and  108 , the diodes are reversed biased. In one embodiment of the de-coupling circuit  110  according to the present invention, a reverse saturation current flowing through the diodes maintains central common node  110  at about half the voltage applied between terminals  106  and  108 , thereby insuring that both capacitors formed by way of transistors  112  and  114  have applied thereon approximately half the voltage applied between terminals  106  and  108 . The effective total capacitance of this configuration has a capacitance value approximately equal to half a capacitance of the gate oxide area corresponding to each transistor. 
     The configuration illustrated in FIG. 1 is particularly useful when the voltage applied between terminals  106  and  108  is higher than the process limitation for the voltage to be applied to a certain on-die device. For example, when the voltage to be de-coupled (voltage applied between terminals  106  and  108 ) is far higher than the process voltage, the voltage divider divides this voltage in half across each capacitor, and, therefore, each capacitor receives a lower voltage thereacross due to the identity of reverse-biased diodes  122  and  124 . A divider that divides the voltage in two is preferable, as the voltage between terminals  106  and  108  is equally divided between the two capacitors  112  and  114 . This reduces the possibility of an un-even distribution of voltages across the capacitors  112  and  114 . Such un-even distribution may be harmful to the capacitor that would receive a higher voltage thereacross if such voltage is higher than the process voltage. 
     Note that the present invention may be implemented with metal capacitors instead of transistors  112  and  114 . However, metal capacitors take a large area. Therefore transistor capacitances are preferable due to the smaller area they take up. Moreover, the voltage divider may be implemented by using two resistors of exactly the same size. Resistors, however, consume a significant amount of current, which is not desirable in low-power designs. The structures shown in FIG. 1 with the two reverse-bias diodes consume very little current because the reverse saturation current is very small. The implementation of the present invention consumes extremely low power and insures that the two capacitors are operated in safe regions. 
     FIG. 2 illustrates a second embodiment  200  of the present invention where both transistors  112  and  113  are PMOSFET transistors coupled in parallel with diodes  122  and  124 . In this embodiment, transistor  112  is coupled just like transistor  112  of FIG.  1 . PMOSFET transistor  113  has a source and drain thereof coupled to the common central node  110  whereas the gate of transistor  113  is coupled to the negative supply voltage (ground in the embodiment described herein). 
     FIG. 3 illustrates an alternative embodiment  300  of the de-coupling circuit according to the present invention. In this embodiment, diodes  123  and  125  are implemented by way of matched PMOSFET transistors  123  and  125  that are diode-connected. The combination of these transistors maintain the node  110  at approximately one-half the voltage difference between the voltages at terminals  106  and  108 . These transistors have high impedances as their gate nodes are connected in a fashion that ensures that V GS , the gate-to-source Voltage is Ø (zero) volts, ensuring that the channels of these transistors are turned off. The sub-threshold conduction in devices  123  and  125  emulates the behavior of high value resistances. Transistors  112  and  114  form the de-coupling divided capacitor. 
     FIG. 4 illustrates a block diagram  400  of a load circuit  402  that is coupled to a power supply  404  and to a de-coupling circuit  100  according to the present invention. 
     In the foregoing specification, the invention has been described with reference to specific embodiments thereof. It will however be evident that various modifications and changes can be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. Therefore, the scope of the invention should be limited only by the appended claims.