Abstract:
A vertical bidirectional switch of the type having its control referenced to the rear surface, including on its rear surface a first main electrode and on its front surface a second main electrode and a gate electrode, this switch being controllable by a positive voltage between its gate and its first electrode, wherein the gate electrode is arranged on the front surface of a via crossing the chip in which the switch is formed.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a U.S. National Stage patent application based on International patent application number PCT/FR2011/050935, filed on Apr. 22, 2011, which application claims the priority benefit of French patent application number 10/53326, filed on Apr. 29, 2010, which applications are hereby incorporated by reference to the maximum extent allowable by law. 
       BACKGROUND 
       [0002]    2. Technical Field 
         [0003]    The present disclosure relates to a bidirectional switch formed of a semiconductor chip comprising a main electrode on each surface of the chip and a control electrode on the front surface of the chip, this control electrode or gate being controlled by a voltage referenced to the voltage of the rear surface electrode. 
         [0004]    2. Discussion of the Related Art 
         [0005]    Such components are different from unidirectional thyristors and from bidirectional triacs in which the gate signal is controlled by reference to the front surface electrode. Having the gate electrode referenced to the rear surface is advantageous in that it is convenient to connect the rear surface comprising a single electrode to a ground plate or a radiator, which enables the gate signal to be referenced to a fixed voltage, for example, the ground, while in many applications, the main front surface electrode is connected to the mains voltage, which make it necessary to provide isolation systems to deliver a voltage between a control signal and a variable potential. 
         [0006]    The applicant, which has created the concept of bidirectional switch referenced to the rear surface, sold under trade name “ACS”, has conducted many studies on these components. U.S. Pat. Nos. 6,034,381, 6,593,600, and 6,927,427 will especially be mentioned. Further, previously, the applicant had provided to connect multiple unidirectional components (thyristors) in parallel with a common cathode, the gates being referenced to the cathode, as described in U.S. Pat. No. 5,914,502. 
         [0007]    The various known architectures of bidirectional rear surface referenced switches, when controllable in Q 1  and Q 4  modes, that is, when the gate is positive with respect to the rear surface electrode, have the disadvantage of involving a transistor or a lateral thyristor for their turning-on. This sets, on the one hand, an issue in terms of surface area assigned to the gate, and on the other hand, possible latch-up problems when an abrupt voltage variation is applied between the main electrodes (dV/dt turn-on). 
       SUMMARY 
       [0008]    It is thus desired to form a bidirectional switch in which the gate electrode is referenced to the rear surface, having a particularly simple and low-bulk control structure, and which is less sensitive to latch-ups due to abrupt voltage variations between its main electrodes. 
         [0009]    An embodiment provides a vertical bidirectional switch of the type having its control referenced to the rear surface, comprising, on its rear surface, a first main electrode and on its front surface a second main electrode and a gate electrode, this switch being controllable by a positive voltage between its gate and its first electrode, wherein the gate electrode is arranged on the front surface of a via crossing the chip in which the switch is formed. 
         [0010]    According to an embodiment, the bidirectional switch comprises a semiconductor substrate of a first conductivity type surrounded with a wall of the second conductivity type, on the front surface side, a well of the second conductivity type in substantially half of which is formed a first region of the first conductivity type, a via of the second conductivity type running from the front surface to the rear surface of the substrate, arranged between the first region and the wall, this via being in contact with the gate electrode, on the rear surface side, a layer of the second conductivity type in which is formed a second region of the first conductivity type substantially in front of the portion of the well which is not taken up by the first region, an insulating layer being arranged on the rear surface, around the via region. The layer of the second conductivity type is interrupted and said insulating layer is arranged so that, when a positive voltage is applied between the gate electrode and the first main electrode, a current flows in said layer of the second conductivity type under the substrate. 
         [0011]    According to an embodiment, a third region of the first conductivity type is formed on the rear surface side so that said current flows in a pinched region. 
         [0012]    According to an embodiment, the bidirectional switch further comprises a fourth region of the first conductivity type arranged in the well on the front surface side and connected to the gate electrode, whereby the switch is controllable in all four quadrants. 
         [0013]    According to an embodiment, the first conductivity type is type N. 
         [0014]    The foregoing and other objects, features, and advantages will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]      FIG. 1A  is a simplified top view of a bidirectional switch according to an embodiment; 
           [0016]      FIG. 1B  is a simplified cross-section view along line B-B of  FIG. 1A  and is further intended to illustrate the operation in quadrant Q 1 ; 
           [0017]      FIG. 1C  is a cross-section view similar to that of  FIG. 1B  intended to illustrate the operation in quadrant Q 4 ; 
           [0018]      FIG. 2  is a top view of an alternative embodiment in which the bidirectional switch is likely to be controlled in quadrants Q 2  and Q 3  in addition to quadrants Q 1  and Q 4 ; and 
           [0019]      FIG. 3  is a top view illustrating an alternative topology of a component according to an embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0020]    As usual in the representation of semiconductor components, the various drawings are not to scale. 
         [0021]    As shown in the top view of  FIG. 1A  and the cross-section view of  FIG. 1B , a bidirectional switch is formed from a lightly-doped N-type substrate  1  surrounded with a P-type peripheral wall  3 . Of course, during the manufacturing, substrate  1  corresponds to a chip of a silicon wafer. 
         [0022]    A P-type well  5  extends in a substantially central position on the upper surface (or front surface) side of substrate  1 . A heavily-doped N-type region  7  (N + ) is formed in substantially half of well  5 . The lower surface (or area surface) of the substrate is mainly taken up by a P-type layer  9  having limits which will be discussed hereafter in relation with the discussion of the switch operation. A heavily-doped N-type region  11  is formed in layer  9  facing the portion of P well  5  in which region  7  is not formed. Thus, the power portion of the component comprises two thyristors in antiparallel respectively comprising regions and layers  5 - 1 - 9 - 11  and  7 - 5 - 1 - 9 . 
         [0023]    A P-type via  14  crosses substrate  1  to reach P-type layer  9 . This via is arranged in substrate  1  in front of one side of N region  7  and may, for example, correspond to a drive-in region. Further, an N + -type ring  16  surrounding P well  5  and forming a channel stop region may be provided. On the lower surface side, an insulating layer  18  extends under the portion of N region  1  arranged between via  14  and peripheral well  3  and extends towards the center of the component. Further, a heavily-doped N-type region  19  is arranged in layer  9  on the lower surface side substantially between the emerging portion of via  14  and the projection of N + -type region  7 . 
         [0024]    A main electrode metallization A 1  covers the entire lower surface. A main electrode metallization A 2  covers all the regions of P well  5  and of N +  region  7  and a gate metallization G covers the upper surface of via  14 . For simplification, these metallizations are not shown in  FIG. 1A  and only appear in  FIG. 1B . Further, in  FIG. 1B , the insulating layers which cover the front surface outside of the areas of contact with the metallizations have not been shown. 
         [0025]    For bidirectional switches, four turn-on quadrants are defined. It is still assumed that electrode A 1  is grounded. First quadrant Q 1  corresponds to a positive A 2  and a positive G, second quadrant Q 2  corresponds to a positive A 2  and a negative G, third quadrant Q 3  corresponds to a negative A 2  and to a negative G, and fourth conduction quadrant Q 4  corresponds to a negative A 2  and a negative G. The previously-described component is capable of operating in the first and fourth quadrants, the component being capable of being turned on by application to the gate electrode of a positive signal with respect to electrode A 1 , whatever the biasing of electrode A 2 . 
         [0026]    In  FIG. 1B , the turn-on mode in quadrant Q 1 , that is, when electrode A 2  is positive with respect to electrode A 1 , has been indicated by arrows in dotted lines. The positive gate terminal with respect to electrode A 1  causes the flowing of a current I 1  from electrode G to electrode A 1 , which runs vertically through via  14 , then horizontally (leftwards in the drawing) in a portion of P layer  9  between N substrate  1  above insulating layer  18  and N region  19 , if present. The current cannot directly flow towards peripheral wall  3  due to the fact that P layer  9  does not extend under the portion of substrate  1  located outside of the emerging portion of via  14 . The flowing of a current in the pinched region of P-type layer  9  between insulating layer  18  and region  19  and substrate  1  makes the junction between P layer  9  and region  19  conductive and electrons are injected into the substrate along arrow  12 . This results in a hole injection through P well  5  into the substrate (arrow  13 ) to ensure the balance and the conduction starts in the vertical thyristor comprising layers and regions  5 - 1 - 9 - 11 , as indicated by arrow  14 . 
         [0027]    It should be noted that this turning-on does not correspond to the turning-on of a transistor or of a lateral thyristor and no turning-on can occur due to a fast overvoltage between electrodes A 2  and A 1 . The component, in this embodiment, is thus particularly insensitive to the parasitic dV/dt turn-on. 
         [0028]      FIG. 1C  illustrates the turning-on in mode Q 4 , that is, when electrode A 2  is negative with respect to electrode A 1 . Initially, the same current I 1  as indicated previously flows through via  14 . Similarly, this causes an injection of electrons  12  into the substrate. The PN junction between via  14  and substrate  1  which tends to become conductive causes the injection of holes from region  14  to P well  5  (arrow I 3 ). These holes direct towards negative electrode A 2  in P region  5  (arrow I 4 ) and this, conventionally, unlocks vertical thyristor  7 - 5 - 1 - 9  (arrow I 5 ). 
         [0029]      FIG. 2  shows a variation of the embodiment of  FIG. 1 . In addition to the elements already shown and described in relation with  FIG. 1 , two N +  regions  21 ,  22  (a single one would actually be necessary) formed in the upper portion of peripheral insulating wall  3  are present. These N +  regions may be connected by a metallization to gate via  14  and form gates that can turn on the bidirectional switch in quadrants Q 2  and Q 3 , similarly to what is described in at least some of the US patents mentioned at the beginning of the present description. A switch controllable in the four quadrants is thus obtained. 
         [0030]      FIG. 3  shows an alternative embodiment of the structure illustrated in top view in  FIGS. 1 and 2 . This variation only is a topological variation: gate via  14  is placed in a corner of the structure and gate  21  is placed in another corner of the structure, via  14  facing N +  portion  7  which, this time, cuts P well  5  diagonally. 
         [0031]    Of course, the present invention is likely to have many alternative embodiments which will readily occur to those skilled in the art, especially after reading of the previously-mentioned prior patents of the applicant which will be considered herein as known. Thus, no detailed example of doping levels, of layer thicknesses, and of dimensions has been given herein, these values being simple to determine by those skilled in the art. 
         [0032]    Such alterations, modifications, and improvements are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only and is not intended as limiting. The invention is limited only as defined in the following claims and the equivalents thereto.