Abstract:
An integrated power module having a depletion mode device and an enhancement mode device that is configured to prevent an accidental on-state condition for the depletion mode device during a gate signal loss is disclosed. In particular, the disclosed integrated power module is structured to provide improved isolation and thermal conductivity. The structure includes a substrate having a bottom drain pad for the depletion mode device disposed on the substrate and an enhancement mode device footprint-sized cavity that extends through the substrate to the bottom drain pad. A thermally conductive and electrically insulating slug substantially fills the cavity to provide a higher efficient thermal path between the enhancement mode device and the bottom drain pad for the depletion mode device.

Description:
RELATED APPLICATIONS 
       [0001]    This application claims the benefit of U.S. provisional patent application No. 62/046,236, filed Sep. 5, 2014, the disclosure of which is incorporated herein by reference in its entirety. 
     
    
     FIELD OF THE DISCLOSURE 
       [0002]    The present disclosure is directed to power electronics. In particular, the present disclosure provides an integrated power module with improved electrical isolation and improved thermal conductivity. 
       BACKGROUND 
       [0003]    There are at least three standard methods of packaging multi-chip power modules. One popular method incorporates direct bonded copper (DBC) substrates that comprise a ceramic tile with copper bonded to top and/or bottom sides of the ceramic tile. Alumina (Al 2 O 3 ), aluminum nitride (AlN), and beryllium oxide (BeO) are materials that are usable as the ceramic tile. DBC substrates are known for their high thermal conductivity and excellent electrical isolation. DBC substrates comprising AlN and copper have a thermal conductivity of at least 150 Watts per meter Kelvin (W/mK). However, DBC substrates have disadvantages of high cost, large design rules, and a limitation of only one electrical conductor routing layer. 
         [0004]    Another multi-chip packaging method utilizes leadframe technology with either DBC isolation or a cascode-stacked die technique. However, present leadframe technology not well suited for multiple die structures that are coplanar. In particular, present leadframe technology can be compromised thermally and/or mechanically when attempted to be used for coplanar multi-chip structures. 
         [0005]    Yet another standard multi-chip packaging technology incorporates laminate printed circuit board (PCB) technology. An advantage of laminate PCB technology is low cost, integration flexibility, and electrical conductor routing. However, a significant disadvantage of PCB technology is low thermal performance if there are multiple dies requiring high power dissipation that cannot utilize electrically conducting thermal vias due to unequal electrical potentials on both sides of the vias. 
         [0006]    What is needed is an integrated power module with improved electrical isolation and improved thermal conductivity that is structured to realize the advantages of each of the above multi-chip packaging methods while avoiding the discussed limitations of those methods. 
       SUMMARY 
       [0007]    An integrated power module having a depletion mode device and an enhancement mode device that is configured to prevent an accidental on-state condition for the depletion mode device during a gate signal loss is disclosed. In particular, the disclosed integrated power module is structured to provide improved isolation and thermal conductivity. The structure includes a substrate having a bottom drain pad for the depletion mode device disposed on the substrate and an enhancement mode device footprint-sized cavity that extends through the substrate to the bottom drain pad. A thermally conductive and electrically insulating slug substantially fills the cavity to provide a higher efficient thermal path between the enhancement mode device and the bottom drain pad for the depletion mode device. 
         [0008]    In at least one exemplary embodiment, a depletion mode device footprint-sized cavity in the substrate is substantially filled with a thermally conductive and electrically conductive slug that provides a higher efficient thermal path between the depletion mode device and the bottom drain pad for the depletion mode device. In yet another exemplary embodiment, the depletion mode device footprint-sized cavity is substantially filled with a thermally conductive and electrically insulating slug that provides a higher efficient thermal path between the depletion mode device and the bottom drain pad for the depletion mode device. In this case electrical connectivity is established with vias from a top-side depletion mode device drain pad to the bottom drain pad for the depletion mode device. 
         [0009]    Those skilled in the art will appreciate the scope of the disclosure and realize additional aspects thereof after reading the following detailed description in association with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure. 
           [0011]      FIG. 1  is an electrical schematic for a cascode topology for an integrated power module of the present disclosure that incorporates an enhancement mode device to ensure that a depletion mode device maintains an off-state in the event of a gate signal failure. 
           [0012]      FIG. 2  is a top x-ray view of an exemplary embodiment of the integrated power module of the present disclosure that has improved electrical isolation and improved thermal conductivity. 
           [0013]      FIG. 3  is a backside view of the exemplary embodiment of  FIG. 1 . 
           [0014]      FIG. 4  is a cross-sectional view of  FIGS. 2 and 3 . 
           [0015]      FIG. 5  is a cross-sectional view of another exemplary embodiment that uses direct bonded copper (DBC) slugs to transfer heat away from the depletion mode device and the enhancement mode device. 
       
    
    
     DETAILED DESCRIPTION 
       [0016]    The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the disclosure and illustrate the best mode of practicing the disclosure. Upon reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. 
         [0017]    The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the disclosure and illustrate the best mode of practicing the disclosure. Upon reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. 
         [0018]    It will be understood that when an element such as a layer, region, or substrate is referred to as being “over,” “on,” “in,” or extending “onto” another element, it can be directly over, directly on, directly in, or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over,” “directly on,” “directly in,” or extending “directly onto” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. 
         [0019]    Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. 
         [0020]    Discrete high voltage and high power semiconductor devices are predominantly normally-off, meaning that they are enhancement mode devices. The reason enhancement mode devices are favored is due to safety since an enhancement mode device will not accidently turn during a gate signal failure. However, high performance depletion mode devices have recently been developed. As a result of the nature of the depletion mode, high performance depletion mode devices are inherently normally-on and can present a danger in an event of gate signal failure such as the gate signal falling to a voltage less than needed to maintain the off-state of the depletion mode device. For example, the depletion mode device would accidently turn on if its gate voltage were to inadvertently drop to zero volts while in an off-state. As such, high performance depletion mode devices require auxiliary components and/or topologies to maintain a normally-off condition in the event of gate signal failure. 
         [0021]      FIG. 1  is an electrical schematic of a cascode topology for an integrated power module  10  of the present disclosure that ensures that a depletion mode device  12  maintains an off-state in the event of a gate signal failure. In this case, an enhancement mode device  14  maintains control of an off-state for the depletion mode device  12  in the event of gate signal failure. Specifically, an off-state for the enhancement mode device  14  maintains a drain to source voltage drop across the depletion mode device  12  that is reflected across a gate-source junction of the of the enhancement mode device  14 , which in turn pinches the depletion mode device  12  to an off-state. In the exemplary embodiment of  FIG. 1 , the depletion mode device  12  is typically a gallium nitride (GaN) on silicon (Si) high electron mobility transistor (HEMT). The enhancement mode device  12  is typically a low voltage Si metal oxide semiconductor field effect transistor (MOSFET). 
         [0022]    Typically, discrete transistors have three leads, which are a gate lead, a source lead, and a drain lead. It is desirable that the integrated power module  10  also adhere to this three lead convention. As such, the topology of the integrated power module  10  is configured to convert six internal connections into a conventional three leaded external topology that provides gate, source, and drain leads. However, adhering to the conventional three leaded external topology presents a problem of providing maximum heat transfer from inside the integrated power module  10  to external the integrated power module  10 . Simply put, a three leaded device conversion of a six leaded multi-chip device cannot transfer as much heat as a single chip three leaded device of the same size because significant thermal paths are disrupted in a six leaded multi-chip device. 
         [0023]    The disruption of thermal paths inside the integrated power module  10  is due to a need for electrical isolation between parts of the depletion mode device  12  and parts of the enhancement mode device  14  that are at different voltage potentials. This thermal challenge is most pronounced for lateral devices such as devices with a GaN on silicon carbide (SiC) die and a GaN on Si die, both of which need backside electrical isolation. Moreover, it is desirable that a first die comprising the depletion mode device  12  and a second die comprising the enhancement mode device  14  be substantially coplanar. 
         [0024]      FIG. 2  is a top x-ray view of an exemplary embodiment of the integrated power module  10  of the present disclosure that has improved electrical isolation and improved thermal conductivity. The integrated power module  10  includes a substrate  16  that supports the depletion mode device  12  and the enhancement mode device  14 . The substrate  16  is a printed circuit type laminate that typically includes copper traces that route power and signals to and from the depletion mode device  12  and the enhancement mode device  14 . In at least one embodiment, the substrate  16  is made of material formulated to provide substantially low dielectric losses for gigahertz radio frequency operation of the depletion mode device  12  and the enhancement mode device  14 . 
         [0025]    A top-side depletion device (top d-drain) pad  18  is disposed onto a top-side of the substrate  16  to which a drain contact (drain- 1 ) of the depletion mode device  12  is electrically coupled. Further still, a top-side enhancement device (top e-drain) pad  20  is also disposed onto the top-side of the substrate  16  to which a drain contact (drain- 2 ) of the enhancement mode device  14  is electrically coupled. The top e-drain pad  20  is spaced from the top d-drain pad  18  to electrically isolate the top d-drain pad  18  from the top e-drain pad  20 . Inter-device bond wires  24  couple selected terminals between the depletion mode device  12  and enhancement mode device  14 . Extra-device bond wires  26  couple gate and source contacts on the enhancement mode device  14  to gate and source leads disposed onto the substrate  16 . 
         [0026]      FIG. 3  depicts a bottom-side depletion device drain (bottom d-drain) pad  22  to which a thermally and electrically conductive slug (TECS)  28  is bonded to create a higher efficient thermal path between the depletion mode device  12  and the bottom d-drain pad  22 . An external heatsink (not shown) can be coupled to the bottom d-drain pad  22  using a fastener and a paste type thermal compound. 
         [0027]    In the exemplary embodiment of  FIG. 2  and  FIG. 3 , the substrate  16  includes a first cavity wherein the TECS  28  is inserted. In at least one embodiment, the TECS  28  has a thermal resistivity that is at least  10  times lower than the thermal resistivity of the substrate  16  and an electrical resistivity that is substantially equal to or less than the electrical resistivity of the bottom d-drain pad  22 . In the exemplary embodiment of the integrated power module  10  depicted in  FIG. 2  and  FIG. 3 , the TECS  28  is made of a material such as copper that is both thermally and electrically conductive. 
         [0028]      FIG. 4  is a cross-sectional view of the integrated power module  10  depicted in  FIG. 2  and  FIG. 3 . This cross-sectional view shows the TECS  28  embedded within the substrate  16  and bonded to the substrate  16  using non-conductive epoxy  32 . A first plating  34  that is electrically conductive is disposed over the top d-drain pad  18  to electrically and thermally couple the drain of the depletion mode device  12  to the top d-drain pad  18  after the TECS  28  is embedded within the substrate  16 . The drain contact drain- 1  of the depletion mode device  12  is soldered or welded to the first plating  34  at a location substantially centered over the TECS  28 . Bonding of the TECS  28  to the bottom d-drain pad  22  is achieved using soldering or welding. Moreover, in the exemplary embodiment, the TECS  28  has an area that is at least equal to an area taken up by the largest surface of the depletion mode device  12 . However, it is to be understood that the TECS  28  can have a slightly smaller surface area than area taken up by the largest surface of the depletion mode device without deviating from scope of the present disclosure. 
         [0029]    A second cavity is provided within the substrate  16  wherein a thermally conductive only slug (TCOS)  30  is inserted. Typically, the TCOS  30  has a thermal resistivity that is at least 2 times lower than the thermal resistivity of the substrate  16  that is bonded between the e-drain pad  20  and the enhancement mode device  14 . The TCOS  30  is bonded to the substrate  16  with the second cavity using a non-conductive epoxy  32 . Once securely embedded within the substrate  16 , the TCOS  30  provides a highly efficient thermal path between the enhancement mode device  14  and the bottom d-drain pad  22 . A second plating  36  that is electrically conductive is disposed over the top e-drain pad  20  to electrically and thermally couple the drain contact (drain- 2 ) of the enhancement mode device  14  to the e-drain pad  20  after the TECS  28  is embedded within the substrate  16 . 
         [0030]    In the exemplary case of  FIGS. 2-4 , the TCOS  30  is electrically isolating, yet also thermally conductive. A second drain contact drain- 2  of the enhancement mode device  14  is soldered or welded to the second plating  36  at a location substantially centered over the TCOS  30 . In this and other embodiments, the first cavity and second cavity can be rectangular holes that are routed within the substrate  16 . However, other geometries such as ovals and rounded rectangles are also usable as cavity shapes without deviating from the objectives of the present disclosure. 
         [0031]    In at least some embodiments, the TCOS  30  is a direct bonded copper (DBC structure) having a ceramic substrate  38  with top-side copper  40  and bottom-side copper  42  as best seen in  FIG. 4 . The ceramic substrate  26  can be, but is not limited materials such as Alumina (Al 2 O 3 ), aluminum nitride (AlN), and Beryllium oxide (BeO). Vias  44  provide electrical connections source and gate leads disposed on the top-side and bottom-side of the substrate  16 . 
         [0032]      FIG. 5  is a cross-sectional view of an exemplary embodiment of another integrated power module  46  of the present disclosure that has improved electrical isolation and improved thermal conductivity. This exemplary embodiment replaces the TECS  28  of the integrated power module  10  with another TCOS  30 . In this case, vias  48  provide electrical connections between the top d-drain pad  18  and the bottom d-drain pad  22 . 
         [0033]    Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.