Abstract:
A transmitter for transmitting data in response to N clock signals with the same period T is provided. Every two adjacent clock signals have a phase difference of T/N therebetween. The transmitter includes a clock synthesizer and a multiplexer. The clock synthesizer sequentially generates N select signals in response to level-switch states of the N clock signals, respectively, during the period T. The multiplexer is electrically connected to the clock synthesizer for selecting one of N input data signals to be outputted in response to a corresponding one of the N select signals in turn. A method for transmitting data with eliminated duty-cycle effect is also disclosed.

Description:
FIELD OF THE INVENTION 
   The present invention relates to a high speed data transmitter, and more particularly to a transmitter for transmitting data at a high transmission rate in response to a low frequency clock signal. The present invention also relates to a method for transmitting data. 
   BACKGROUND OF THE INVENTION 
   In a typical computer system, a core logic circuit such as a chipset, is widely used to control data flows among a central processing unit (CPU), a system memory and a plurality of input/output (I/O) devices. Recently, the processing frequency of the core logic circuit is increasingly improved. The speeds of data flows on the I/O buses, however, could not catch up with the step of the chipset. The major factors include the design of transmitters/receivers, type of package, construction of substrates and routing of circuit boards, for example. Therefore, the limitation of the I/O buses on bandwidth is required to be overcome. 
   A Double Data Rate (DDR) transmitter  10 , with reference to  FIGS. 1(   a ) and  1 ( b ), was developed to meet these needs. The DDR transmitter  10  outputs data at both the rising and falling edges of a clock signal CK_ 0 . Since data transmission are performed twice for each cycle of the clock signal CK_ 0 , the data throughput doubles. 
   The transmitter  10  principally comprises two flip-flop devices  12  and  14 , a multiplexer  16  and a pad circuit  18 . First, three clock signals CK_ 90 , CK_ 180  and CK_ 270  having the same frequency as the clock signal CK_ 0  are generated by a phase-locked loop circuit (not shown). The phase differences between these clock signals CK_ 90 , CK_ 180  and CK_ 270  and the clock signal CK_ 0  are 90, 180 and 270 degrees, respectively. The flip-flop device  14  is latched in response to the rising edge of the clock signal CK_ 90 , and sequentially outputs low-bit data DL including the first, the third, . . . , and the (2J+1) data as output data DXL, where J is an integer. The flip-flop device  12  is latched in response to the rising edge of the clock signal CK_ 270 , and sequentially outputs high-bit data DH including the second, the fourth . . . , and the (2J)th data as output data DXH. The multiplexer  16  selects one of the two output data DXH and DXL from the flip-flop devices  12  and  14 , respectively, to be outputted as output data TX_D to the pad circuit  18 . The multiplexer  16  allows the output data DXH and DXL to be alternately outputted in response to a select signal, i.e. the clock signal CK_ 0 . When the clock signal CK_ 0  turns to a low level, the low-bit data DXL is selected as the output data TX_D. On the other hand, when the clock signal CK_ 0  turns to a high level, the multiplexer  16  selects the high-bit data DXH to be the output data TX_D. Therefore, the data TX_D is outputted at a double data rate. 
   As is known, the valid data bit time for transmitting data on an I/O bus depends on the clock signal. In order to obtain precise and uniform valid data bit time, it is important to acquire a clock signal with a balanced duty cycle, i.e. 50%. The clock signal for the present purpose is generally provided by a clock generator and outputted by a phase-locked loop circuit. The clock signal of a 50% duty cycle provides the data flowing through the bus a unified data bit time. Unfortunately, it is difficult to control the duty cycle of the clock signal to be exactly 50% all the time. In general, the duty cycle of the clock signal outputted by the phase-locked loop circuit has a variation between about 48% and about 52%. Therefore, the use of the clock signal CK_ 0  with unbalanced duty cycle as a select signal of the multiplexer  16  will lead to inconsistent data bit time on the I/O bus. Thus, the setup/hold time margin will greatly decrease. Furthermore, when the data transfer speed on the bus is required to be higher and higher, it is even difficult to design a phase-locked loop circuit capable of providing various clock signals with a variety of phase differences. 
   SUMMARY OF THE INVENTION 
   Therefore, it is an object of the present invention to provide a transmitter and a method for transmitting data with eliminated duty-cycle effect. 
   In accordance with an aspect of the present invention, there is provided a transmitter for transmitting data in response to N clock signals with the same period T, in which every two adjacent clock signals have a phase difference of T/N therebetween. The transmitter includes a clock synthesizer and a multiplexer. The clock synthesizer sequentially generates N select signals in response to level-switch states of the N clock signals, respectively, during the period T. The multiplexer is electrically connected to the clock synthesizer for selecting one of N input data signals to be outputted in response to a corresponding one of the N select signals in turn. 
   In an embodiment, the level-switch states are all rising edges or all falling edges. 
   In an embodiment, each of the N select signals is kept at a high level for a time period of T/N, during which the selected one of the N input data signals is allowed to be outputted by the multiplexer. 
   In an embodiment, the N clock signals are generated by a phase-locked loop circuit according to a reference clock signal with a period of T/2. 
   Preferably, N=4. 
   Preferably, the transmitter further includes N flip-flop devices electrically connected to the multiplexer for sequentially latching and outputting the N input data signals to the multiplexer in response to the level-switch states of the N clock signals, respectively. 
   In accordance with another aspect of the present invention, there is provided a transmitter for transmitting data in response to N clock signals derived from a reference clock signal of a first period. The transmitter includes a clock synthesizer and a multiplexer. The clock synthesizer generates N select signals in response to the N clock signals, respectively, during a second period correlating to the first period of the reference clock signal. The multiplexer is electrically connected to the clock synthesizer and receiving N input data signals, wherein the N input data signals are sequentially selected to be outputted in response to the N select signals sequentially generated, respectively. 
   In an embodiment, each of the N select signals is generated in response to a rising edge or a falling edge of one of the N clock signals. 
   Preferably, The first period is T/2, and the second period is T. 
   Preferably, N=4, and each of the N select signals is kept at a high level for a third period of T/4. 
   Preferably, the transmitter further comprises N flip-flop devices electrically connected to the multiplexer, and receiving the N clock signals and the N input data signals, wherein the N input data signals are latched successively in response to level-switch states of the N clock signals occurring in series and transmitted to the multiplexer. 
   In accordance with another aspect of the present invention, there is provided a method for transmitting data. Firstly, N clock signals in response to a reference clock signal of a first period are provided. During a second period correlating to the first period of the reference clock signal, N select signals are sequentially generated in response to the N clock signals, respectively. Then, N input data signals are received, wherein the N input data signals are sequentially selected to be outputted in response to the N select signals sequentially generated, respectively. Preferably, the method further includes a step of receiving the N clock signals and the N input data signals, wherein the N input data signals are latched successively in response to level-switch states of the N clock signals occurring in series. 
   The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which: 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1(   a ) is a functional block diagram of a typical Double Data Rate (DDR) transmitter; 
       FIG. 1(   b ) is a timing waveform diagram illustrating the related signals processed in the DDR transmitter of  FIG. 1(   a ); 
       FIG. 2(   a ) is a functional block diagram of a data transmitter according to a preferred embodiment of the present invention; 
       FIG. 2(   b ) is a timing waveform diagram illustrating the related signals processed in the data transmitter of  FIG. 2(   a ); 
       FIG. 3(   a ) is a circuit diagram of an exemplified clock synthesizer of the data transmitter of  FIG. 2(   a ); and 
       FIG. 3(   b ) is a timing waveform diagram illustrating the synthesis of the select signal S 1  in the clock synthesizer of  FIG. 3(   a ). 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 2(   a ) is a functional block diagram illustrating a data transmitter according to a preferred embodiment of the present invention, and the timing waveform diagram of the processed signals is shown in  FIG. 2(   b ). The data transmitter of the present invention principally comprises four flip-flop devices  20 ,  22 ,  24  and  26 , a multiplexer  32 , a pad circuit  34  and a clock synthesizer  36 . First, a reference clock signal CK having a period of T/2 is provided. Then, four clock signals CK 2 _ 0 , CK 2 _ 90 , CK 2 _ 180  and CK 2 _ 270  having half the frequency of the reference clock signal CK, i.e. each having a time period of T, are generated by a phase-locked loop circuit (not shown) in advance. The phase differences between the clock signals CK 2 _ 90 , CK 2 _ 180  and CK 2 _ 270  and the clock signal CK 2 _ 0  are 90, 180 and 270 degrees, respectively. The input ends D 1 , D 2 , D 3  and D 4  of the flip-flop devices  20 ,  22 ,  24  and  26  receive data from the lowest to the highest bytes. After being processed, these data sets are transmitted to the multiplexer  32  via output ends TX_D 1 , TX_D 2 , TX_D 3  and TX_D 4 , respectively. 
   The four clock signals CK 2 _ 0 , CK 2 _ 90 , CK 2 _ 180  and CK 2 _ 270  are further inputted to the clock synthesizer  36  to sequentially generate four select signals S 1 , S 2 , S 3  and S 4 . As shown in  FIG. 2(   b ), each of the select signals S 1 , S 2 , S 3  and S 4  is interlacingly kept at a high level for a time period of T/4. The high level duration of the select signal S 1  appears only between the rising edges of the adjacent clock signals CK 2 _ 0  and CK 2 _ 90 , the high level duration of the select signal S 2  appears only between the rising edges of the adjacent clock signals CK 2 _ 90  and CK 2 _ 180 , the high level duration of the select signal S 3  appears only between the rising edges of the adjacent clock signals CK 2 _ 180  and CK 2 _ 270 , and the high level duration of the select signal S 4  appears only between the rising edges of the adjacent clock signals CK 2 _ 270  and CK 2 _ 0 . In response to the high-level states of the select signal S 1 , S 2 , S 3  and S 4 , data transmission is coordinated in a manner as described hereinafter. 
   At the rising edge of the clock signal CK 2 _ 270 , the data inputted through the input ends D 1  and D 2  will be latched by the first and the second flip-flop devices  20  and  22 . Likewise, the data inputted through the input ends D 3  and D 4  will be latched by the third and the fourth flip-flop devices  24  and  26  at the rising edge of the clock signal CK 2 _ 90 . In other words, the flip-flop device  20 , in response to the rising edges of the clock signal CK 2 _ 270 , sequentially latches and outputs the data signals including the first, the fifth, the ninth, . . . , and the (4k+1)th data, to the first output end TX_D 1 , where k is an integer. The flip-flop device  22  in response to the rising edges of the clock signal CK 2 _ 270 , sequentially latches and outputs the data signals including the second, the sixth, the tenth, . . . , and the (4k+2)th data, to the second output end TX_D 2 . Similarly, the flip-flop device  24  and  26  in response to the rising edges of the clock signal CK 2 _ 90 , sequentially latch and output the data signals including the third, the seventh, the eleventh, . . . , and the (4k+3)th data, to a third output end TX_D 3  and the data signals including the fourth, the eighth, the twelfth, . . . , and the (4k)th data, to a fourth output end TX_D 4 , respectively. The multiplexer  32  has four input ends electrically connected to the four output ends TX_D 1 , TX_D 2 , TX_D 3  and TX_D 4  of the flip-flop devices  20 ,  22 ,  24  and  26 , respectively, and has an output end TX_D electrically connected to the pad circuit  34 . The multiplexer  32  allows the data to be outputted in sequence in response to the four select signals S 1 , S 2 , S 3  and S 4  in turn. For example, when the select signal S 1  is at the high level, the data D 1  latched by the flip-flop device  20  and outputted to the multiplexer  32  via the end TX_D 1  is selected to be outputted to the pad circuit  34  via the end TX_D. When the select signal S 2  is at the high level, the data D 2  latched by the flip-flop device  22  and outputted to the multiplexer  32  via the end TX_D 2  is selected to be outputted to the pad circuit  34  via the end TX_D, and so on. 
     FIGS. 3(   a ) and  3 ( b ) illustrate the synthesis of the select signal by an exemplified clock synthesizer. The clock synthesizer includes four inverters  52 ,  54 ,  56  and  62 , a NAND gate  60 , and two transmission gates  58  and  64 . Take the select signal S 1  as an example. The clock signal CK 2 _ 0  is transferred through the serially interconnected inverters  52  and  54  into the NAND gate  60 , and another clock signal CK 2 _ 90  is transferred through the serially interconnected inverter  56  and transmission gate  58  into the NAND gate  60 . Being operated by the NAND gate  60 , the signal is outputted to another inverter  62  and another transmission gate  64  to generate the select signal S 1  and the complementary signal  S 1   . The transmission gate  58  and  64  are utilized to compensate the delays of the inverter  54  and  62 , respectively. With such configuration, the select signal S 1  is synthesized in response to the two clock signals CK 2 _ 0  and CK 2 _ 90 . Similarly, the select signals S 2 , S 3  and S 4  are synthesized in response to two adjacent clock signals CK 2 _ 90  and CK 2 _ 180 , CK 2 _ 180  and CK 2 _ 270 , and CK 2 _ 270  and CK 2 _ 0 , respectively. 
   Since the select signals are determined by means of precise clock signals generated by phase-locked loop circuit, the problem of unbalanced duty cycle can be overcome, and precise and uniform valid data bit time can be achieved according to the present invention. Furthermore, due to the reduced frequency of the clock signal, a phase-locked loop circuit is capable of processing relatively long bit length of data. Therefore, the data transmitter of the present invention is advantageous when the data transfer speed on the I/O bus is higher and higher. 
   The present invention is illustrated by sequentially generating the select signals in response to rising edges of clock signals. Nevertheless, the select signals can be also generated in response to falling edges of clock signals. 
   While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.