Abstract:
A method for fabricating a semiconductor device includes forming a silicon-containing layer; forming a metal-containing layer over the silicon-containing layer; forming an undercut prevention layer between the silicon containing layer and the metal containing layer; etching the metal-containing layer; and forming a conductive structure by etching the undercut prevention layer and the silicon-containing layer.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application claims priority of Korean Patent Application No. 10-2012-0081835, filed on Jul. 26, 2012, which is incorporated herein by reference in its entirety. 
     BACKGROUND 
     1. Field 
     Exemplary embodiments of the present invention relate to a semiconductor fabricating process, and more particularly, to a conductive structure including a silicon-containing layer and a metal-containing layer. 
     2. Description of the Related Art 
     Recently, semiconductor memory devices such as DRAM are operating at a high-speed. Therefore, a low-resistance material is used as the material of a gate electrode or a bit line. For example, when a metal-containing layer is formed as the material of the gate electrode or the bit line, it may be possible to implement a structure favorable to a high-speed operation. The metal-containing layer may include a stacked layer of two or more selected from titanium nitride (TIN), tungsten (W), tungsten nitride (WN), tungsten silicon nitride (WSiN), and tungsten silicide (WSi x ). Among the materials, TiN, WN, WSiN, or WSi x  may serve as a diffusion barrier. For example, when a polysilicon layer and a tungsten layer are stacked, TiN, WN, WSiN, or WSi x  may serve as a diffusion barrier between the polysilicon layer and the tungsten layer. 
       FIG. 1  is a diagram illustrating a gate structure formed by a conventional method. 
     Referring to  FIG. 1 , a gate dielectric layer  12  is formed over a semiconductor substrate  11 . A silicon-containing layer  13  and a metal-containing layer are stacked over the gate dielectric layer  12 . The metal-containing layer includes a diffusion barrier layer  14  and a metal layer  15 . 
     A mask pattern  16  is formed over a metal layer  15 , then by using the mask pattern  16  as an etch barrier, the metal-containing layer and the silicon-containing layer  13  are etched to form a gate structure. 
     In general, when the stacked structure of the silicon-containing layer  13  and the metal-containing layer is etched, a dry etch process such as reactive ion etching (RIE) is used. During the dry etch process, anisotropic etching must be performed for different kinds of materials. 
     During the etch process for the metal-containing layer, however, an undercut  17  may occur at the interface between the silicon-containing layer  13  and the metal-containing layer, because the silicon-containing layer  13  is more quickly etched. The undercut  17  occurs when the upper part of the silicon-containing layer  13  is etched. When the size of the undercut  17  further increases, the upper part of the silicon-containing layer  13  may be completely cut. Furthermore, when the undercut is severe, a part of the metal-containing layer may be lost (refer to reference numeral  18 ). 
     SUMMARY 
     Exemplary embodiments of the present invention are directed to a semiconductor structure capable of preventing an undercut of a lower material during an etch process for a metal-containing layer, and a method for fabricating a semiconductor device having the same. 
     In accordance with an embodiment of the present invention, a method for fabricating a semiconductor device includes forming a silicon-containing layer; forming a metal-containing layer over the silicon-containing layer; forming an undercut prevention layer between the silicon containing layer and the metal containing layer; etching the metal-containing layer; and forming a conductive structure by etching the undercut prevention layer and the silicon-containing layer. 
     In accordance with another embodiment of the present invention, a method for fabricating a semiconductor device includes forming an interlayer dielectric layer over a semiconductor substrate; forming a contact hole by etching the interlayer dielectric layer; forming a preliminary plug filling the contact hole, wherein the preliminary plug includes a silicon-containing layer and an undercut prevention layer formed over the silicon-containing layer; forming a metal-containing layer over the interlayer dielectric layer including the preliminary plug; and forming a bit line and a bit line contact plug by etching the metal-containing layer and the preliminary plug. 
     In accordance with yet another embodiment of the present invention, a method for fabricating a semiconductor device includes forming a first polysilicon layer; forming a tungsten-containing layer over the first polysilicon layer; forming a second polysilicon layer between the first polysilicon layer and the tungsten-containing layer, the second polysilicon layer containing at least one of carbon and nitrogen; etching the tungsten-containing layer; and etching the second polysilicon layer and the first polysilicon layer. 
     In accordance with still another embodiment of the present invention, a conductive structure of semiconductor device includes a first silicon-containing layer; a second silicon-containing layer formed over the first silicon-containing layer and containing at least one of carbon and nitrogen; and a tungsten-based metal-containing layer formed over the second silicon-containing layer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram illustrating a gate structure formed by a conventional method. 
         FIGS. 2A to 2D  are diagrams illustrating a method for forming a gate electrode in accordance with a first embodiment of the present invention. 
         FIGS. 3A to 3E  are diagrams illustrating a method for forming a gate electrode in accordance with a second embodiment of the present invention. 
         FIGS. 4A to 4I  are diagrams illustrating a method for forming a bit line in accordance with a third embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Exemplary embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention. 
     The drawings are not necessarily to scale and in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. It should be readily understood that the meaning of “on” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” not only means “directly on” something but also include the meaning of “on” something with an intermediate feature or a layer therebetween, and that “over” not only means the meaning of “over” something may also include the meaning it is “over” something with no intermediate feature or layer therebetween (i.e., directly on something). 
     The embodiments of the present invention provide a structure capable of preventing an undercut of a silicon-containing layer formed under a metal-containing layer. For this structure, chemical species capable of controlling an etch rate are contained in the upper part of the silicon-containing layer. The silicon-containing layer containing chemical species has a low etch rate to prevent the undercut of silicon-containing layer. For example, the silicon-containing layer doped with chemical species such as carbon or nitrogen, which has a very low etch rate, may be used. When chemical species are selectively injected at a position where an undercut of the silicon-containing layer is expected and a general silicon-containing layer is formed under the position, it may be possible to prevent an undercut of the silicon-containing layer from occurring, regardless of how an etch process for the metal-containing layer is performed. The position where an undercut is expected may correspond to ½ or ⅓ of the entire thickness of the silicon-containing layer, and may correspond to an arbitrary lower position from an interface with the metal-containing layer. 
     The structure using chemical species capable of controlling an etch rate to prevent the undercut may be applied to a method for forming a semiconductor structure including a silicon-containing layer and a metal-containing layer. The semiconductor structure may include a gate electrode, a bit line contact plug, and/or a bit line. 
       FIGS. 2A to 2D  are diagrams illustrating a method for forming a gate electrode in accordance with a first embodiment of the present invention. 
     Referring to  FIG. 2A , a semiconductor substrate  21  is prepared. The semiconductor substrate  21  may include an area where a transistor is to be formed. For example, the semiconductor substrate  21  may include an area where an NMOSFET is to be formed or an area where a PMOSFET is to be formed. Furthermore, the semiconductor substrate  21  may include both an area where an NMOSFET is to be formed and an area where a PMOSFET is to be formed. The semiconductor substrate  21  may include a substrate formed of silicon, germanium, or silicon germanium, and is not limited thereto. In addition, the entire or part of the semiconductor substrate  21  may be strained. Furthermore, although not illustrated, the semiconductor substrate  21  may include a well formed by a typical well formation process. 
     A gate dielectric layer  22  is formed over the semiconductor substrate  21 . The gate dielectric layer  22  may include silicon oxide, silicon oxynitride, or a high-k material. When the gate dielectric layer  22  includes a high-k material, an interface layer (not shown) may be further formed between the semiconductor substrate  21  and the gate dielectric layer  22 . The interface layer may include silicon oxide or silicon oxynitride. The high-k material has a larger dielectric constant than silicon oxide (SiO 2 ) having a dielectric constant of about 3.9. The high-k material has a larger physical thickness and a smaller equivalent oxide thickness (EOT) than SiO 2 . The high-k material used as the gate dielectric layer  22  includes a metal-containing material such as a metal oxide, a metal silicate, or a metal silicate nitride. The metal oxide includes an oxide containing a metal such as hafnium (Hf), aluminum (Al), lanthanum (La), or zirconium (Zr). The metal oxide may include hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (LaO 2 ), zirconium oxide (ZrO 2 ) or a combination thereof. The metal silicate includes a silicate containing a metal such as Hf or Zr. For example, the metal silicate may include hafnium silicate (HfSiO), zirconium silicate (ZrSiO x ) or a combination thereof. The metal silicate nitride may be obtained by containing nitrogen into a metal silicate. The metal silicate nitride may include hafnium silicate nitride (HfSiON). The process for forming the gate dielectric layer  22  may include a deposition process suitable for a material to be deposited. For example, the formation process may include chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), metal-organic CVD (MOCVD), atomic layer deposition (ALD), and plasma enhanced ALD (PEALD). 
     A silicon-containing layer  23 A is formed over the gate dielectric layer  22 . The silicon-containing layer  23 A may include a polysilicon layer. The polysilicon layer may be doped with an impurity. The impurity may include an N-type or P-type impurity. The N-type impurity may include phosphorus or arsenic (As), and the P-type impurity may include boron. The polysilicon layer doped with an N-type impurity becomes an N-type polysilicon gate. The polysilicon layer doped with a P-type impurity becomes a P-type polysilicon gate. The silicon-containing layer  23 A may be formed by CVD, ALD or the like. When the silicon-containing layer  23 A is deposited, an N-type impurity or P-type impurity may be in-situ doped by using an impurity containing gas and a silicon source gas. Furthermore, the silicon-containing layer  23 A may be formed in an undoped state, and then subsequently doped with an N-type impurity or P-type impurity. 
     An undercut prevention layer  24 A is formed over the silicon-containing layer  23 A. The undercut prevention layer  24 A may have a thickness corresponding to an area where an undercut may occur during a subsequent dry etching process. The undercut prevention layer  24 A may include a silicon-containing material. The undercut prevention layer  24 A may be formed of the same material as the silicon-containing layer  23 A. The undercut prevention layer  24 A may include polysilicon. In this embodiment of the present invention, a material for preventing an undercut is contained into the undercut prevention layer  24 A. That is, chemical species are injected into the undercut prevention layer  24 A, thereby reducing an etch rate during a subsequent dry etch process. Accordingly, an undercut may be prevented. The chemical species contained in the undercut prevention layer  24 A includes a material capable of controlling an etch rate. The chemical species may include carbon or nitrogen. In this case, carbon or nitrogen may be independently used as the chemical species, or carbon and nitrogen may be simultaneously used as the chemical species. Therefore, the undercut prevention layer  24 A contains at least one of carbon and nitrogen. The undercut prevention layer  24 A may include carbon-doped polysilicon, nitrogen-doped polysilicon, and carbon-nitrogen-doped polysilicon (SiCN). The undercut prevention layer  24 A may be formed by in-situ doping chemical species when polysilicon is deposited or ion-implanting chemical species after polysilicon is deposited. To dope or ion-implant carbon or nitrogen, a carbon containing gas or nitrogen containing gas may be further used. The carbon containing gas may include CH 4 , CH 2 , C 2 H 2  and the like. The nitrogen containing gas may include NH 3 , N 2  and the like. The thickness of the undercut prevention layer  24 A corresponds to a thickness at which an undercut may occur. For example, the undercut prevention layer  24 A may have a thickness of about 100 to 300 Å. 
     Since the undercut prevention layer  24 A containing chemical species is not etched even when the metal-containing layer  25 A is etched, an undercut may not occur. 
     The undercut prevention layer  24 A may further include an N-type impurity or P-type impurity in addition to the chemical species. Therefore, the silicon-containing layer  23 A may include a polysilicon layer doped with a first impurity, and the undercut prevention layer  24 A may include a polysilicon layer doped with a second impurity. Here, the first impurity may include an N-type impurity or P-type impurity, and the second impurity may include nitrogen, carbon, or a mixture of nitrogen and carbon. The polysilicon layer doped with the second impurity may further include an N-type impurity or P-type impurity implanted therein as the first impurity. 
     Referring to  FIG. 2B , a metal-containing layer is formed over the undercut prevention layer  24 A. The metal-containing layer may include a metal, a metal nitride, a metal silicide, and a metal silicon nitride. The metal-containing layer may include a stacked layer of two or more selected from a metal, a metal nitride, a metal silicide, and a metal silicon nitride. For example, the metal-containing layer may be formed by stacking tungsten silicide (WSi), tungsten nitride (WN), and tungsten (W). In another embodiment, the metal-containing layer may be formed by stacking WSi, tungsten silicon nitride (WSiN), and W. The metal-containing layer may include a diffusion barrier layer  25 A and a metal layer  26 A which are stacked therein. In this case, WSi, WN, and WSiN may be used as the diffusion barrier layer  25 A for preventing a reaction between the silicon-containing layer  23 A and the metal layer  26 A. 
     Through the above-described series of processes, a gate stack is formed, in which the silicon-containing layer  23 A, the undercut prevention layer  24 A, the diffusion barrier layer  25 A, and the metal layer  26 A are stacked. When a tungsten-containing material is used as the diffusion barrier layer  25 A and the metal layer  26 A, low resistance may be obtained even though the thickness is reduced, and parasitic capacitance may be reduced. As a comparative example, a titanium-containing material may be used as the metal-containing layer. However, since the titanium-containing material has larger resistance than the tungsten-containing material, the titanium-containing material has a limitation in reducing resistance. Furthermore, when the tungsten-containing material is applied, the undercut prevention effect may be improved more compared to when the titanium-containing material is applied. 
     Referring to  FIG. 2C , a mask pattern  27  is formed. The mask pattern  27  may include a material having a high etching selectivity with respect to the diffusion barrier layer  25 A, the metal layer  26 A, and the silicon-containing layer  23 A. The mask pattern  27  may be formed of photoresist. Furthermore, the mask pattern  27  may include a patterned hard mask layer. The hard mask layer may include an insulation layer such as oxide or nitride. 
     Using the mask pattern  27  as an etch mask, the diffusion barrier layer  25 A and the metal layer  26 A forming the metal-containing layer are etched. Accordingly, a metal electrode  202  is formed. The metal electrode  202  may include a diffusion barrier layer pattern  25  and a metal layer pattern  26 . The etch process for the metal-containing layer may include a dry etch process such as RIE. If the metal-containing layer is a tungsten-based layer, the etch process may be performed using SF 6 , Cl 2 , or a mixture of SF 6  and Cl 2 . In addition to SF 6 , a fluorine-based gas such as NF 3 , F 2 , HF or the like may be used. Furthermore, gases such as N 2  and O 2  may be further added during the etching process. As the above-described gases are used to etch the metal-containing layer, a vertical profile is formed. When the tungsten-based metal-containing layer is etched, a fluorine-based gas may be used as the main etching gas. Typically, the dry etch process includes a main etch process and an over etch process. The over etch process after the main etch process is performed in such a manner that residues of the etched material do not occur over the lower material. 
     During the above-described etch process, the etch rate of the metal-containing material is different from the etch rate of the silicon-containing material. For example, the undercut prevention layer  24 A has a larger etch rate compared to the metal-containing layer. Therefore, an undercut may occur in the undercut prevention layer  24 A. In this embodiment of the present invention, the undercut prevention layer  24 A containing chemical species for reducing an etch rate to prevent an undercut is formed to reduce the etch rate. Accordingly, an undercut may be prevented in the undercut prevention layer  24 A where an undercut is likely to occur during the etch process for the metal-containing layer. Furthermore, although the over etch process is sufficiently performed, an undercut may not occur. An undercut may occur in the diffusion barrier layer pattern  25  such as tungsten silicide among the materials used as the metal-containing layer. However, in this embodiment of the present invention, the undercut prevention layer  24 A is formed to prevent a loss of the diffusion barrier layer pattern  25 . 
     Referring to  FIG. 2D , the undercut prevention layer  24 A and the silicon-containing layer  23 A are etched using the mask pattern  27  as an etch mask. Accordingly, a silicon electrode  201  is formed. The silicon electrode  201  may include a silicon-containing layer pattern  23  and an undercut prevention layer pattern  24 . Therefore, the upper part of the silicon electrode  201  may have the undercut prevention layer pattern formed therein. The etch process for the undercut prevention layer  24 A and the silicon-containing layer  23 A may include a dry etch process such as RIE. For example, the etch process may be performed using SF 6 , HBr, Cl 2 , or a mixture thereof. In addition to SF 6 , a fluorine-based gas such as NF 3 , F 2 , HF or the like may be used. Furthermore, gases such as N 2  and O 2  may be further added during the etch process. As the above-described gases are used to etch the undercut prevention layer  24 A and the silicon-containing layer  23 A, a vertical profile is formed. Since the undercut prevention layer  24 A and the silicon-containing layer  23 A include polysilicon, HBr may be used as the main etching gas. Typically, the dry etch process includes a main etch process and an over etch process. The over etch process performed after the main etch process is performed in such a manner that residues of the etched material do not occur over the lower material. 
     During the etch process for the silicon-containing layer  23 A, an undercut may occur in the upper part of the silicon-containing layer  23 A. In this embodiment of the present invention, the undercut prevention layer  24 A containing chemical species for reducing a etch rate to prevent an undercut is formed over the silicon-containing layer so as to reduce the etch rate. Accordingly, although the over etch process is sufficiently performed, an undercut may not occur in the upper part of the silicon electrode  201 . During the over etch process for the silicon-containing layer  23 A, an undercut may occur in the diffusion barrier layer pattern  25  such as tungsten silicide among the materials used as the metal electrode  202 . However, in this embodiment of the present invention, the undercut prevention layer pattern  24  is formed to prevent a loss of the diffusion barrier layer pattern  25 . 
     As described above, when the silicon electrode  201  is formed, a gate electrode, which includes the silicon electrode  201  and the metal electrode  202  stacked therein, is formed over the gate dielectric layer  22 . Between the silicon electrode  201  and the metal electrode  202 , the undercut prevention layer pattern  24  is formed. The undercut prevention layer pattern  24  may function as the gate electrode as a part of the silicon electrode  201 . 
     Subsequently, the mask pattern  27  is removed. When the mask pattern  27  includes a hard mask layer, the mask pattern  27  may be left. Furthermore, an ion implant process may be performed to form source and drain regions. Furthermore, a gate spacer is formed on sidewalls of the gate electrode. Before the gate spacer is formed, lightly-doped source and drain regions may be formed, and after the gate spacer is formed, high-concentration source and drain regions may be formed. 
       FIGS. 3A to 3E  are diagrams illustrating a method for forming a gate electrode in accordance with a second embodiment of the present invention. 
     Referring to  FIG. 3A , a semiconductor substrate  31  is prepared. The semiconductor substrate  31  may include an area where a transistor is to be formed. For example, the semiconductor substrate  31  may include an area where an NMOSFET is to be formed or an area where a PMOSFET is to be formed. Furthermore, the semiconductor substrate  31  may include both an area where an NMOSFET is to be formed and an area where a PMOSFET is to be formed. The semiconductor substrate  31  may include a substrate formed of silicon, germanium, or silicon germanium, and is not limited thereto. Furthermore, the entire or part of the semiconductor substrate  31  may be strained. Furthermore, although not illustrated, the semiconductor substrate  31  may include a well formed by a typical well formation process. 
     A gate dielectric layer  32  is formed over the semiconductor substrate  31 . The gate dielectric layer  32  may include silicon oxide, silicon oxynitride, or a high-k material. When the gate dielectric layer  32  includes a high-k material, an interface layer may be further formed between the semiconductor substrate  31  and the gate dielectric layer  32 . The interface layer may include silicon oxide or silicon oxynitride. The high-k material has a larger dielectric constant than silicon oxide (SiO 2 ) having a dielectric constant of about 3.9. Furthermore, the high-k material has a larger physical thickness and a smaller EOT than SiO 2 . The high-k material used as the gate dielectric layer  32  includes a metal-containing material such as a metal oxide, a metal silicate, or a metal silicate nitride. The metal oxide includes an oxide containing a metal such as Hf, Al, La, or Zr. The metal oxide may include HfO 2 , Al 2 O 3 , LaO 2 , ZrO 2  or a combination thereof. The metal silicate includes a silicate containing a metal such as Hf or Zr. The metal silicate may include HfSiO, ZrSiO x , or a combination thereof. The metal silicate nitride may be obtained by incorporating nitrogen into a metal silicate. The metal silicate nitride may include HfSiON. The process for forming the gate dielectric layer  32  may include a suitable deposition process for a material to be deposited. For example, the formation process may include CVD, LPCVD, PECVD, MOCVD, ALD, and PEALD. 
     A silicon-containing layer  33 A is formed over the gate dielectric layer  32 . The silicon-containing layer  33 A may include a polysilicon layer. The polysilicon layer may be doped with an impurity. The impurity may include an N-type or P-type impurity. The N-type impurity may include phosphorus or As, and the P-type impurity may include boron. The polysilicon layer doped with an N-type impurity becomes an N-type polysilicon gate. The polysilicon layer doped with a P-type impurity becomes a P-type polysilicon gate. The silicon-containing layer  33 A may be formed by CVD, ALD or the like. When the silicon-containing layer  33 A is deposited, an N-type impurity or P-type impurity may be in-situ doped using an impurity containing gas and a silicon source gas. Furthermore, the silicon-containing layer  33 A may be formed in an undoped state, and then subsequently doped with an N-type impurity or P-type impurity through an ion implant process. 
     Referring to  FIG. 3B , an undercut prevention layer  35 A is formed in the upper part of the silicon-containing layer  33 A. The undercut prevention layer  35 A may have a thickness corresponding to an area where an undercut may occur during a subsequent dry etch process. To form the undercut prevention layer  35 A, chemical species injection may be performed. Through the chemical species injection, chemical species are doped or implanted into the upper part of the silicon-containing layer  33 A. Accordingly, the undercut prevention layer  35 A containing the chemical species is formed. The undercut prevention layer  35 A may include the same material as the silicon-containing layer  33 A. That is, the undercut prevention layer  35 A may include a silicon-containing material. The undercut prevention layer  35 A may include polysilicon. In this embodiment of the present invention, a material for preventing an undercut is injected into the undercut prevention layer  35 A. That is, the chemical species are contained in the undercut prevention layer  35 A to reduce the etch rate during the subsequent dry etch process. Accordingly, an undercut may be prevented. The chemical species injected into the undercut prevention layer  35 A include a material capable of controlling the etch rate. The chemical species may include carbon or nitrogen. In this case, carbon or nitrogen may be independently used as the chemical species, or carbon and nitrogen may be simultaneously used as the chemical species. Therefore, the undercut prevention layer  35 A may include at least one of carbon and nitrogen. The undercut prevention layer  35 A may include carbon-doped polysilicon, nitrogen-doped polysilicon, and carbon-nitrogen-doped polysilicon (SiCN). 
     The chemical species injection  34  may include doping and ion implantation. Furthermore, the chemical species injection  34  may include a heat treatment or plasma treatment in an atmosphere including at least one of carbon and nitrogen. To inject at least one of carbon and nitrogen, at least one of a carbon containing gas and nitrogen containing gas may be used. The carbon containing gas may include CH 4 , CH 2 , C 2 H 2  and the like. The nitrogen containing gas may include NH 3 , N 2  and the like. 
     The thickness of the undercut prevention layer  35 A corresponds to a thickness at which an undercut may occur. For example, the undercut prevention layer  35 A may have a thickness of about 100 to 300 Å. 
     Since the undercut prevention layer  35 A having the species injected therein is not etched even when the metal-containing layer  36 A is etched, an undercut may not occur. 
     The undercut prevention layer  35 A may further include an N-type or P-type impurity other than the chemical species. Therefore, the silicon-containing layer  33 A may include a polysilicon layer doped with a first impurity, and the undercut prevention layer  36 A may include a polysilicon layer doped with a second impurity. Here, the first impurity may include an N-type or P-type impurity, and the second impurity may include nitrogen, carbon, or a mixture of nitrogen and carbon. The polysilicon layer doped with the second impurity may further include an N-type or P-type impurity implanted therein as the first impurity. 
     Referring to  FIG. 3C , a metal-containing layer is formed over the undercut prevention layer  35 A. The metal-containing layer may include a metal, a metal nitride, a metal silicide, and a metal silicon nitride. The metal-containing layer may include a stacked layer of two or more selected from a metal, a metal nitride, a metal silicide, and a metal silicon nitride. For example, the metal-containing layer may be formed by stacking tungsten silicide, tungsten nitride, and tungsten. In another embodiment, the metal-containing layer may be formed by stacking tungsten silicide, tungsten nitride, and tungsten. The metal-containing layer may include a diffusion barrier layer  36 A and a metal layer  37 A, which are stacked therein. In this case, tungsten silicide, tungsten nitride, and tungsten silicon nitride may be used as the diffusion barrier layer  36 A for preventing a reaction between the silicon-containing layer  33 A and the metal layer  37 A. 
     Through the above-described series of processes, a gate stack is formed, in which the silicon-containing layer  33 A, the undercut prevention layer  35 A, the diffusion barrier layer  36 A, and the metal layer  37 A are stacked. 
     Referring to  FIG. 3D , a mask pattern  38  is formed. The mask pattern  38  may be formed of photoresist. Furthermore, the mask pattern  38  may include a patterned hard mask layer. The hard mask layer may include an insulation layer such as oxide or nitride. 
     Using the mask pattern  38  as an etch mask, the metal layer  37 A and the diffusion barrier layer  36 A forming the metal-containing layer are etched. Accordingly, a metal electrode  302  is formed. The metal electrode  302  may include a diffusion barrier layer pattern  36  and a metal layer pattern  37 . The etch process for the metal-containing layer may include a dry etch process such as RIE. If the metal-containing layer is tungsten-based layer, the etch process may be performed using SF 6 , Cl 2 , or a mixture of SF 6  and Cl 2 . In addition to SF 6 , a fluorine-based gas such as NF 3 , F 2 , HF or the like may be used. Furthermore, gases such as N 2  and O 2  may be further added during the etch process. As the above-described gases are used to etch the metal-containing layer, a vertical profile is formed. When the tungsten-based metal-containing layer is etched, a fluorine-based gas may be used as the main etching gas. Typically, the dry etch process includes a main etch process and an over etch process. The over etch process after the main etch process is performed in such a manner that residues of the etched material do not occur over the lower material. 
     During the above-described etch process, the etch rate of the metal-containing material is different from the etch rate of the silicon-containing material. For example, the silicon-containing layer  33 A has a larger etch rate compared to the metal-containing layer. Therefore, an undercut may occur in the upper part of the silicon-containing layer  33 A. In this embodiment of the present invention, the undercut prevention layer  35 A containing chemical species for reducing an etch rate to prevent an undercut is formed over the silicon-containing layer  33 A to reduce the etch rate. Accordingly, an undercut may not occur in the undercut prevention layer  35 A where an undercut is likely to occur during the etch process for the metal-containing layer. Furthermore, although the over etch process is sufficiently performed, an undercut may not occur. An undercut may occur in the diffusion barrier layer pattern  36  such as tungsten silicide among the materials used as the metal-containing layer. However, in this embodiment of the present invention, the undercut prevention layer  35 A is formed to prevent a loss of the diffusion barrier layer pattern  36 . 
     Referring to  FIG. 3E , the undercut prevention layer  24 A and the silicon-containing layer  23 A are etched by using the mask pattern  38  as an etch mask. Accordingly, a silicon electrode  301  is formed. The silicon electrode  301  may include a silicon-containing layer pattern  33  and an undercut prevention layer pattern  35 . Therefore, the upper part of the silicon electrode  301  may have the undercut prevention layer pattern  35  formed therein. The etch process for the undercut prevention layer  35 A and the silicon-containing layer  33 A may include a dry etch process such as RIE. For example, the etch process may be performed using SF 6 , HBr, Cl 2 , or a mixture thereof. In addition to SF 6 , a fluorine-based gas such as NF 3 , F 2 , HF or the like may be used. Furthermore, gases such as N 2  and O 2  may be further added during the etch process. As the above-described gases are used to etch the undercut prevention layer  35 A and the silicon-containing layer  33 A, a vertical profile is formed. Since the undercut prevention layer  35 A and the silicon-containing layer  33 A include polysilicon, HBr may be used as the main etch gas. Typically, the dry etch process includes a main etch process and an over etch process. The over etch process performed after the main etch process is performed in such a manner that residues of the etched material do not occur over the lower material. 
     During the etch process for the silicon-containing layer  33 A, an undercut may occur in the undercut prevention layer pattern  35 . In this embodiment of the present invention, the undercut prevention layer pattern  35  containing chemical species for reducing an etch rate to prevent an undercut is formed over the silicon-containing layer  33 A to reduce the etch rate. Accordingly, although the over etch process is sufficiently performed, an undercut may not occur in the upper part of the silicon electrode  301 . During the over etch process for the silicon-containing layer  33 A, an undercut may occur in the diffusion barrier layer pattern  36  such as tungsten silicide among the materials used as the metal electrode  302 . However, in this embodiment of the present invention, the undercut prevention layer pattern  35  is formed to prevent a loss of the diffusion barrier layer pattern  36 . 
     When the silicon electrode  301  is formed as described above, a gate electrode having the silicon electrode  301  and the metal electrode  302  stacked therein is formed over the gate dielectric layer  32 . Between the silicon electrode  301  and the metal electrode  302 , the undercut prevention layer pattern  35  is formed. The undercut prevention layer pattern  35  may function as the gate electrode as a pat of the silicon electrode  301 . 
     Subsequently, the mask pattern  38  is removed. When the mask pattern  38  includes a hard mask layer, the mask pattern  38  may be left. Furthermore, an ion implantation process may be performed to form a source and drain regions. Furthermore, a gate spacer is formed on both sidewalls of the gate electrode. Before the gate spacer is formed, lightly-doped source and drain regions may be formed, and after the gate spacer is formed, high-concentration source and drain regions may be formed. 
     In accordance with the first and second embodiments of the present invention, when the gate electrode is formed, the undercut prevention layer into which the chemical species such as carbon and nitrogen are injected is formed prior to an undercut in the upper part of the silicon-containing layer where an undercut is likely to occur. Therefore, it may be possible to prevent an undercut during the etch process of the metal-containing layer. 
     Hereafter, a method for forming a bit line in accordance with a third embodiment of the present invention will be described. 
       FIGS. 4A to 4I  are diagrams illustrating a method for forming a bit line in accordance with a third embodiment of the present invention. 
     Referring to  FIG. 4A , an isolation layer  42  is formed to define an active region in a semiconductor substrate  41 . Using a hard mask layer pattern  43  as an etch mask, the semiconductor substrate  41  is etched to form a gate trench  44 . A gate dielectric layer  45  is formed on the surface of the gate trench  44 . Then, a buried gate  46  is formed over the gate dielectric layer  45  so as to partially fill the gate trench  44 . The buried gate  46  may include a metal layer. The buried gate  46  is formed by the following process: a metal layer is deposited on the entire surface of the resultant structure so as to fill the gate trench  44 , and then a chemical mechanical polishing (CMP) process and an etch back process are sequentially performed. Accordingly, the buried gate  46  is formed to partially fill the gate trench  45 . 
     A capping layer  47  is formed over the buried gate  46 . The capping layer  47  may include nitride. The capping layer  47  serves to protect the buried gate  46 . The capping layer  47  may be formed by depositing nitride on the semiconductor substrate  41  including the buried gate  46  and performing an etch back process. Accordingly, the capping layer  47  is formed to fill the space over the buried gate  46 . In another embodiment, the capping layer  47  may be formed on the entire surface of the semiconductor substrate  41  to fill the space over the buried gate  46 . Furthermore, in another embodiment, a sealing layer may be further formed on the entire surface of the semiconductor substrate including the capping layer  47 . The sealing layer may include nitride. 
     Referring to  FIG. 4B , an interlayer dielectric layer  48  is formed on the entire surface of the resultant structure including the capping layer  47 . The Interlayer dielectric layer  48  may include oxide such as boron phosphorus silicate glass (BPSG). A first mask pattern  49  is formed over the interlayer dielectric layer  48 . Here, the first mask pattern  49  may define a hole. The first mask pattern  49  may be formed using a photoresist layer or hard mask layer. 
     The interlayer dielectric layer  48  and the hard mask layer pattern  43  are etched using the first mask pattern  49  as an etch mask. Accordingly, a bit line contact hole  50  is formed. As the hard mask layer pattern  43  is removed, the surface of the semiconductor substrate  41  to be contacted with a bit line is partially exposed. 
     Referring to  FIG. 4C , the first mask pattern  48  is removed. 
     Although not illustrated, a spacer may be formed on the sidewalls of the bit line contact hole  50 . The spacer may include oxide, nitride, or a stacked structure thereof. 
     Until the bit line contact hole  50  is filled, a silicon-containing layer  51 A is formed on the entire surface of the resultant structure. The silicon-containing layer  51 A may include a polysilicon layer. The polysilicon layer may be undoped or doped with an impurity. The impurity may include an N-type or P-type impurity. The N-type impurity may include phosphorous or As. The P-type impurity may include boron. The silicon-containing layer  51 A may be formed by CVD, ALD or the like. When the silicon-containing layer  51 A is deposited, an N-type or P-type impurity may be in-situ doped using an impurity containing gas and a silicon source gas. Furthermore, after the silicon-containing layer  51 A is formed in an undoped state, ion implantation may be used to dope an N-type or P-type impurity. 
     Referring to  FIG. 4D , the silicon-containing layer  51 A is selectively removed to form a silicon-containing layer pattern  51 B to fill the bit line contact hole. To form the silicon-containing layer pattern  51 B, a CMP or etch back process may be performed. The surface of the silicon-containing layer pattern  51 B may be recessed more than the surface of the interlayer dielectric layer  48 . 
     Referring to  FIG. 4E , an undercut prevention layer  52 A is formed on the entire surface of the resultant structure including the silicon-containing layer pattern  51 B. The undercut prevention layer  52 A may have a thickness corresponding to an area where an undercut is likely to occur during a subsequent dry etch process. The undercut prevention layer  52 A may be formed of the same material as the silicon-containing layer  51 A. For example, the undercut prevention layer  52 A may include a silicon-containing material. The undercut prevention layer  52 A may include polysilicon. In this embodiment of the present invention, a material for preventing an undercut is contained into the undercut prevention layer  52 A. That is, chemical species are contained in the undercut prevention layer  52 A to reduce an etch rate during a subsequent dry etch process. Accordingly, an undercut may be prevented. The chemical species contained in the undercut prevention layer  52 A may include a material capable of controlling the etch rate. The chemical species may include carbon or nitrogen. In this case, carbon and nitrogen may be independently or simultaneously used as the species. Therefore, the undercut prevention layer  52 A may contain at least one of carbon and nitrogen. The undercut prevention layer  52 A may include carbon-doped polysilicon, nitrogen-doped polysilicon, and carbon-nitrogen-doped polysilicon (SiCN). The undercut prevention layer  52 A may be formed by in-situ doping chemical species when polysilicon is deposited or ion-implanting chemical species after polysilicon is deposited. To dope or ion-implant carbon or nitride, a carbon containing gas or nitrogen containing gas may be further used. The carbon containing gas may include CH 4 , CH 2 , C 2 H 2  and the like. The nitrogen containing gas may include NH 3 , N 2  and the like. The thickness of the undercut prevention layer  52 A corresponds to a thickness at which an undercut may occur. For example, the undercut prevention layer  52 A may have a thickness of about 100 to 300 Å. 
     Since the undercut prevention layer  52 A containing chemical species is not etched even when the metal-containing layer is etched, an undercut may not occur. 
     The undercut prevention layer  52 A may further include an N-type or P-type impurity other than the chemical species. 
     Referring to  FIG. 4F , the undercut prevention layer  52 A is selectively removed to leave a preliminary undercut prevention layer pattern  52 B over the silicon-containing layer pattern  51 B. Accordingly, the undercut prevention layer is not left over the interlayer dielectric layer  48 . 
     The silicon-containing layer pattern  51 B and the preliminary undercut prevention layer pattern  52 B become a preliminary plug to fill the bit line contact hole. 
     Now shown in drawings, the preliminary plug may be formed by other processes. For example, the silicon-containing layer pattern  51 B is formed to fill the bit line contact hole  50 , and the chemical species are injected an upper part of the silicon-containing layer pattern  51 B to form an undercut prevention layer pattern  52 B. 
     Referring to  FIG. 4G , a diffusion barrier layer  53 A is formed over the preliminary undercut prevention layer pattern  52 B and the interlayer dielectric layer  48 . 
     A metal layer  54 A is formed over the diffusion barrier layer  53 A. The diffusion barrier layer  53 A and the metal layer  54 A may include a metal, a metal nitride, a metal silicide, and a metal silicon nitride. The diffusion barrier layer  53 A and the metal layer  54 A may include a stacked layer of two or more selected from a metal, a metal nitride, a metal silicide, and a metal silicon nitride. Also, the diffusion barrier layer  53 A and the metal layer  54 A may include a tungsten-containing material. For example, the diffusion barrier layer  53 A and the metal layer  54 A may be formed by stacking tungsten silicide, tungsten nitride, and tungsten. Furthermore, the diffusion barrier layer  53 A and the metal layer  54 A may be formed by stacking tungsten silicide, tungsten silicon nitride, and tungsten. In this case, tungsten silicide, tungsten nitride, and tungsten silicon nitride may be used as the diffusion barrier layer  53 A. 
     Through the above-described series of processes, a bit line stack is formed, in which the silicon-containing layer pattern  51 B, the preliminary undercut prevention layer pattern  52 B, the diffusion barrier layer  53 A, and the metal layer  54 A are formed. 
     Referring to  FIG. 4H , a second mask pattern  55  is formed. The second mask pattern  55  may be formed of photoresist. Furthermore, the second mask pattern  55  may include a patterned hard mask layer. The hard mask layer may include an insulation layer such as oxide or nitride. 
     Using the second mask pattern  55  as an etch mask, bit line patterning is performed. For example, the metal layer  54 A and the diffusion barrier layer  53 A are etched. Accordingly, a bit line  402  is formed. The bit line  402  includes a diffusion barrier layer pattern  53  and a metal layer pattern  54 . The etch process for the metal layer  54 A and the diffusion barrier layer  53 A may include dry etch such as RIE. If the metal layer  54 A and the diffusion barrier layer  53 A are tungsten-based layers, the etch process may be performed using SF 6 , Cl 2 , or a mixture thereof. In addition to SF 6 , a fluorine-based gas such as NF 3 , F 2 , HF or the like may be used. Furthermore, gases such as N 2  and O 2  may be further added during the etch process. As the above-described gases are used to etch the metal layer  54 A and the diffusion barrier layer  53 A, a vertical profile is formed. When the diffusion barrier layer  53 A and the tungsten-based metal layer  54 A are etched, a fluorine-based gas may be used as the main etching gas. Typically, the dry etch process includes a main etch process and an over etch process. The over etch process performed after the main etch process is performed in such a manner that residues of the etched material do not occur over the lower material. 
     During the above-described etch process, the etch rate of the metal-containing material is different from the etch rate of the silicon-containing material. For example, the silicon-containing layer pattern  51 B has a larger etch rate than the metal layer  54 A and the diffusion barrier layer  53 A. Therefore, an undercut may occur in the upper part of the silicon-containing layer pattern  51 B. In this embodiment of the present invention, the preliminary undercut prevention layer pattern  52 B containing the chemical species for reducing an etch rate to prevent an undercut is formed to reduce the etch rate in the upper part of the silicon-containing layer pattern  51 B. Accordingly, during the etch process for the metal layer  54 A and the diffusion barrier layer  53 A, an undercut may not occur in the preliminary undercut prevention layer pattern  52 B where an undercut is likely to occur. Furthermore, although an over etch process is sufficiently performed, an undercut may not occur. An undercut may occur in the material such as tungsten silicide among the materials used as the diffusion barrier layer  53 A. However, in this embodiment of the present invention, the preliminary undercut prevention layer pattern  52 B is formed to prevent a loss of tungsten silicide. 
     Referring to  FIG. 4I , the preliminary undercut prevention layer pattern  52 B and the silicon-containing layer pattern  51 B are etched by using the second mask pattern  55  as an etch mask. Accordingly, a bit line contact plug  40  is formed. The bit line contact plug  401  includes a silicon plug  51  and an undercut prevention layer pattern  52 . Therefore, the upper part of the bit line contact plug  401  may include the undercut prevention layer pattern  52  formed therein. The etch process for the preliminary undercut prevention layer pattern  52 B and the silicon-containing layer pattern  51 B may include a dry etch process such as RIE. For example, the etch process may be performed using SF 6 , HBr, Cl 2 , or a mixture thereof. In addition to SF 6 , a fluorine-based gas such as NF 3 , F 2 , HF or the like may be used. Furthermore, gases such as N 2  and O 2  may be further added during the etch process. As the above-described gases are used to etch the preliminary undercut prevention layer pattern  52 B and the silicon-containing layer pattern  51 B, a vertical profile is formed. Since the preliminary undercut prevention layer pattern  52 B and the silicon-containing layer pattern  51 B include polysilicon, HBr may be used as the main etching gas. Typically, the dry etch process includes a main etch process and an over etch process. The over etch process performed after the main etch process is performed in such a manner that residues of the etched material do not occur over the lower material. 
     During the etch process for the silicon-containing layer pattern  51 B, an undercut may occur in the upper part of the silicon-containing layer pattern  51 B. In this embodiment of the present invention, the undercut prevention layer pattern  52  containing the chemical species for reducing an etch rate to prevent an undercut is formed over the silicon plug  51  to reduce the etch rate. Accordingly, although an over etch process is sufficiently performed, an undercut may not occur. During the over etch process for the silicon plug  51 , an undercut may occur in the material such as tungsten silicide among the materials used as the diffusion barrier layer  53 . However, in this embodiment of the present invention, the undercut prevention layer pattern  52  is formed to prevent a loss of tungsten silicide. 
     Subsequently, the second mask pattern  55  is removed. When the second mask pattern  55  includes a hard mask layer, the second mask pattern  55  may be left. Then, a bit line spacer may be formed on the sidewalls of the bit line contact plug and the bit line. 
     In the third embodiment of the present invention, the GBL etch process has been described. The GBL etch process refers to an etch process for forming a gate of a peripheral area and a bit line of a cell area at the same time. The bit line formed in the cell area may have an inner GBL (IGBL) structure. The GBL etch process is to equalize the critical dimensions (CD) of a bit line contact plug and a bit line. In this case, a bit line contact hole has a smaller CD than the bit lines contact plug and the bit line. Accordingly, it may be possible to secure an overlay margin with a subsequent storage node contact (SNC). 
     In accordance with the embodiments of the present invention, as the undercut prevention layer into which the chemical species such as carbon or nitrogen are injected is previously formed in an area of the silicon-containing layer where an undercut is likely to occur, it may be possible to prevent an undercut during the etch process for the subsequent metal-containing layer. Since an undercut does not occur, a vertical profile may be formed. Furthermore, since the area of the silicon-containing layer is not reduced, it may be possible to prevent an increase in resistance of the semiconductor structure. 
     Furthermore, as the tungsten-based material is used to form a metal-containing layer, the thickness of the semiconductor structure may be reduced to implement low resistance, and parasitic capacitance may be reduced. 
     While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.