Abstract:
A graphics controller for high speed transmission for memory read commands. The graphics controller chip includes a logic circuit coupled to a first memory. The logic circuit is adapted to respond to a first issued command from a CPU by determining whether the condition that a first command is a memory read command is true. If the condition is true, the logic circuit causes the graphics controller chip to store the first command in the first memory and to begin carrying out the first command. If the condition is false, the logic circuit causes the graphics controller chip to check whether the graphics controller chip is ready to carry out the first command. If the graphics controller chip is not ready to carry out the first command, the logic circuit causes the graphics controller chip to continue checking and to send a signal to the CPU indicating that the graphics controller chip is ready to receive a second command from the CPU.

Description:
CONTINUING APPLICATION DATA 
     This application claims the benefit of U.S. Provisional Application No. 60/323,533 filed Sep. 18, 2001 under 35 U.S.C. §119(e). 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to a graphics controller for high speed transmission of memory read commands. More particularly, the present invention is directed to a graphics controller with a read/write state machine for accepting high speed transmission of memory read commands initiated by the CPU. 
     BACKGROUND OF THE INVENTION 
     A common practice in the art of computer architecture is to move frequently performed, computationally intensive operations from the CPU to a special purpose functional unit, such as a graphics controller. The graphics controller is typically a separate integrated circuit (“chip”). In a computer system with a graphics controller chip, the graphics controller handles various tasks associated with displaying images on a display (such as converting primitive data to pixels), freeing the CPU to perform other tasks. Moving graphics operations from the CPU to the graphics controller improves the performance of the computer system. In practice, however, the amount of improvement is generally not as great as expected. The reason is that the transfer of data between the CPU and the graphics controller becomes a bottleneck that places a limit on the amount of improvement that can be realized. To illustrate the effect of the data transfer bottleneck, consider that in a typical computer system the CPU theoretically requires only 2 bus clock cycles (“BCLKs”) to perform a memory write command and 4 BCLKs to perform a memory read command. In practice, however, writing to a prior art graphics controller requires 5 BCLKs and reading requires up to 8 BCLKs. During the 3-4 additional BCLKs that are required with a prior art graphics controller, the CPU does not perform any useful work. 
     The transfer of data between a CPU and a graphics controller involves a number of steps. These steps must be coordinated so that data is not transferred to the graphics controller faster than it can accept it and so that the CPU knows when the data it has requested is available. To regulate the flow of data from the CPU to the graphics controller, the graphics controller includes a read/write control circuit that can be defined as a read/write state machine. 
     The read/write state machine typically has four states: An “idle” state in which the graphics controller waits for a command from the CPU; a “pause” state in which the read/write state machine checks whether the graphics controller is ready to process the command; a “request” state in which the graphics controller begins processing the command; and, an “end” state in which the graphics controller finishes processing the command. The read/write state machine transitions from state to state in a fixed sequence for each memory cycle. When the read/write state machine receives a command, it transitions sequentially from the idle state to the pause state to the request state to the end state. From the end state, the read/write state machine returns to the idle state where it waits for the next command. While the read/write state machine may remain in a state for one clock period or longer, depending on the type and sequence of commands, the state transition sequence does not change. 
     A bottleneck occurs, for example, when the CPU issues a memory read command. The graphics controller requires more time to process the memory read command than the CPU requires to send a subsequent command. Because the CPU does not perform any useful work while it is waiting for the graphics controller to accept another command, the prior art read/write state machine degrades the overall performance of the computer system. 
     Accordingly, there is a need for a graphics controller that is capable of accepting high speed transmission of memory read commands initiated by a CPU. 
     BRIEF SUMMARY OF THE INVENTION 
     The invention disclosed herein is a graphics controller for high speed transmission for memory read commands. Within the scope of the invention, there is a graphics controller chip for use with an off-chip CPU issuing a plurality of commands. The graphics controller chip preferably comprises a logic circuit coupled to a first memory. The logic circuit is adapted to respond to a first issued command from a CPU by determining whether the condition that a first command is a memory read command is true. If the condition is true, the logic circuit causes the graphics controller chip to store the first command in the first memory and to begin carrying out the first command. If the condition is false, the logic circuit causes the graphics controller chip to check whether the graphics controller chip is ready to carry out the first command. If the graphics controller chip is not ready to carry out the first command, the logic circuit causes the graphics controller chip to continue checking and to send a signal to the CPU indicating that the graphics controller chip is ready to receive a second command from the CPU. 
     The foregoing and other objectives, features, and advantages of the invention will be more readily understood upon consideration of the following detailed description of the invention, taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
     FIG. 1 is a block diagram illustrating an exemplary prior art computer system including a CPU, a display, and a graphics controller. 
     FIG. 2 is a block diagram illustrating functional blocks, including a read/write controller and a local bus multiplexer, within the graphics controller of FIG.  1 . 
     FIG. 3 is a block diagram illustrating functional blocks, including a read/write state machine, within the read/write controller of FIG.  2 . 
     FIG. 4 is a state transition diagram for the read/write state machine of FIG.  3 . 
     FIG. 5 is a timing diagram illustrating memory read cycles of the computer system of FIG.  1 . 
     FIG. 6 is a block diagram illustrating a read/write controller, including a read/write state machine and a local bus multiplexer, within a graphics controller according to the present invention. 
     FIG. 7 is a state transition diagram for an embodiment of the read/write state machine of FIG.  6 . 
     FIG. 8 is a timing diagram illustrating memory read cycles of a computer system that includes the graphics controller of FIG.  6 . 
     FIG. 9 is a state transition diagram for a second embodiment of the read/write state machine of FIG.  6 . 
     FIG. 10 is a diagram of a circuit within the local bus multiplexer of FIG.  2 . 
     FIG. 11 is a diagram of a circuit within the local bus multiplexer of FIG.  6 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 illustrates a prior art computer system  20  including a graphics controller  24 , a CPU  22 , and a display  26 . The computer system  20  illustrates a preferred context for the present invention; however, other contexts for the invention are contemplated, but this is not-essential. As mentioned, the CPU  22  and the graphics controller  24  are typically separate chips. In addition, memory controllers of types other than the graphics controller  24  are contemplated. 
     The graphics controller  24  is coupled to the CPU  22  by a system bus  28 . The graphics controller  24  is coupled to the display  26  by a display bus  30 . To synchronize memory cycles between the CPU  22  and the graphics controller  24 , a bus clock  32  is coupled to the CPU  22  and to the graphics controller  24 . A graphics controller core  34 , a memory  36 , and memory clock (“MCLK”)  38  are included within the graphics controller  24 . The graphics controller core  34  is coupled to the memory  36  by a memory bus  40 . The memory clock  38  is coupled to the memory  36  and to the graphics controller core  34 . The memory  36  includes the shown display buffer  42 , but may also contain other types of data, such as audio data or video data. 
     FIG. 2 illustrates some of the functional blocks included within the graphics controller core  34 : a read/write controller (“R/W CNTRL”)  44 , a local bus multiplexer (“local bus mux”)  46 , a set of registers  48 , a look-up table (“LUT”)  50 , an SRAM controller (“SRAM CNTRL”)  56 , a display pipeline  60 , and a display interface  62 . The read/write controller  44  is coupled to the registers  48  via a register bus  52  and to the look-up table  50  via a look-up table bus  54 . The read/write controller  44 , the SRAM controller  56 , the local bus mux  46 , and the display pipeline  60  are coupled to each other via a graphics controller core bus  64 . Both the read/write controller  44  and the local bus mux  46  are coupled to the system bus  28 . The SRAM controller  56  is coupled to the memory  36  via the memory bus  40 . The display interface  62  is coupled to the display  28  via the display bus  30 . The registers  48  store configuration and other information. The look-up table  50  stores information needed for pixel processing. The SRAM controller  56  provides access and management functions for the memory  36 . 
     FIG. 3 is a block diagram illustrating functional blocks within the read/write controller  44  of FIG.  2 . The read/write controller  44  includes a CPU interface  66  and a bus buffer  68 . In addition, the CPU interface  66  includes a prior art read/write state machine  72 . The CPU interface  66  monitors and places signals on the system bus  28 . When the CPU issues a command, if the graphics controller  24  is ready to accept the command, the control, address, and data signals associated with the command are stored in the bus buffer  68 . The graphics controller  24  processes the command using the command information stored in the bus buffer  68 . If the CPU  22  issues a write command, the memory write data is copied from the bus buffer  68  and stored in the location in memory  36  that is specified by the address stored in bus buffer  68 . If the CPU  22  issues a read command, the requested memory read data is copied from the location in memory  36  that is specified by the address stored in bus buffer  68 , and stored in the local bus mux  46 . The local bus mux  46  stores the requested memory read data in flip-flop type registers. As explained below, the requested memory read data is stored on the rising edge of the bus clock  32  signal. The CPU  22  then obtains the requested memory read data by sampling the local bus mux  46  via the system bus  28 . The read/write state machine  72  is typically implemented as a logic circuit. 
     FIG. 10 is a diagram of a circuit within the local bus mux  46  of FIG. 2 that illustrates how memory read data is stored on the rising edge of the bus clock  32  signal. The shown circuit comprises a multiplexer  82  and a flip-flop type register  84 . If the signal MEM RD EN NEG is asserted, the requested memory read data designated by the signal SRAM RD DATA is transferred from the number  1  input of the multiplexer  82  to the D input of the flip-flop type register  84 . When the bus clock  32  signal goes high, memory read data is latched on the Q output of register  84 . 
     FIG. 4 provides a state transition diagram for the read/write state machine  72 . In FIG. 4, each bubble represents a state. The state and allowed transitions from one state to another are described below. 
     State 0—IDLE 
     In the state IDLE  74 , the read/write state machine  72  waits to receive a start signal (START). The IDLE  74  state is the initial state after start-up for the read/write state machine  72 . The CPU  22  issues a command by asserting control signals. The CPU interface  66  decodes the control signals to create the START signal that indicates that a memory cycle is requested and a command has therefore issued. When the read/write state machine  72  detects the START signal, a wait signal (WAIT#) is asserted and the read/write state machine  72  transitions to a state PAUSE  76 . The WAIT# signal tells the CPU  22  that the graphics controller  24  is busy. The WAIT# signal prevents the CPU  22  from issuing another command and causes the CPU  22  to begin inserting wait states. 
     State 1—PAUSE 
     In the state PAUSE  76 , the read/write state machine  72  checks to see whether the graphics controller  24  is ready to process another command. If a signal REQACTIVE# is asserted low, the graphics controller  24  has not yet finished processing a previous command and the read/write state machine  72  remains in the state PAUSE  76 . On the other hand, if the signal REQACTIVE# is not asserted, the graphics controller  24  has finished processing the previous command and the read/write state machine  72  transitions to a state REQUEST  78 . As the state machine transitions to the state REQUEST  78 , the read/write state machine  72  stores control, address, and data signals into the bus buffer  68  by asserting a buffer enable signal (BUF.EN). 
     State 3—REQUEST 
     In the state REQUEST  78 , the read/write state machine  72  generates the appropriate internal signals needed to process the command and monitors a signal REQACK. In addition, the signal WAIT# is de-asserted upon entering the state REQUEST  78  if the command is for a write cycle or a register read cycle. The signal REQACK indicates that the memory cycle is complete. If the signal REQACK is asserted, the read/write state machine  72  transitions to a state END  80 . 
     State 2—END 
     In the state END  80 , the signal WAIT# is removed if the command is for a memory read cycle. In addition, other internal functions are performed during the state END  80 . On the next BCLK, the read/write state machine  72  transitions from the state END  80  to the state IDLE  74 . 
     FIG. 5 shows a timing diagram illustrating exemplary read cycles of the system  20 . The timing diagram shows the signal produced by the bus clock  32 , the state of the read/write state machine  72 , and various signals described below. A first memory read cycle is initiated when the CPU  22  issues a command by placing address, data, and control signals on the system bus  28 . The control signals are decoded to assert the WAIT# and START signals. As shown in FIG. 3, the signal WAIT# is asserted before BCLK  1  and the signal START is asserted in BCLK  1 . The signal BUF.EN is asserted on the state transition from the state PAUSE  76  to the state REQUEST  78 . The signal BUF.EN signifies that the address, data, and control signals have been stored in the bus buffer  68  at the start of BCLK  3 . In addition, in BCLK  3 , the signal MEM REQ is asserted to direct the SRAM Controller  56  to fetch the requested information from memory  36 . During BCLK  4 , the requested information appears on the outputs of memory  36  as indicated by the signal designated SRAM RD DATA. In BCLK  6 , the requested information is transferred from the output of memory  36  to the local bus mux  46  as indicated by the signal BUS MUX RD DATA. In addition, the signal WAIT# is de-asserted. In BCLK  7 , the CPU  22  samples local bus mux  46  to obtain the requested information. The first command is completed during BCLK  8 . A second memory read cycle begins in BCLK  9 . As FIG. 5 shows, a disadvantage of read/write state machine  72  is that 8 BCLKS must elapse after the CPU  22  has issued a command before the graphics controller  24  can accept a subsequent command from the CPU  22 . In each memory read cycle, the CPU  22  is required to insert 5 wait states. 
     Having described a prior art computer system  20 , a graphics controller  124  according to the present invention for use in the computer system  20  is next described. Turning to FIG. 6, the graphics controller  124  includes a read/write controller  144 , a local bus multiplexer (“local bus mux”)  146 , and a graphics controller core bus  164 . The read/write controller  144  includes a CPU interface  166  and a bus buffer  168 . The CPU interface  166  includes a read/write state machine  172 . The bus buffer  168  stores control, address, and data signals presented on the system bus  28  when the CPU  22  issues a command. The graphics controller  124  uses the control, address, and data signals stored in the bus buffer  168  to process the memory read command. If the CPU  22  issues a read command, the requested information is copied from the location in the memory  36  that is specified by the address stored in bus buffer  168 , and stored in the local bus mux  146 . The local bus mux  146  stores the requested memory read data in transparent latch type registers. As explained below, the requested memory read data is stored on the falling edge of a signal used to clock the register. The CPU  22  then obtains the requested memory read data by sampling the local bus mux  146  via the system bus  28 . The read/write state machine  172  is typically implemented as a logic circuit. 
     FIG. 11 is a diagram of a circuit within the local bus mux  146  of FIG. 6 that illustrates how memory read data is stored on the falling edge of the signal used to clock the register. The shown circuit comprises a transparent latch  182 . In FIG. 11, the requested memory read data is designated by the signal SRAM RD DATA. When the signal MEM RD EN NEG is high, data on the D input of register  182  appears on the Q output. When the signal MEM RD EN NEG goes low, the memory read data is latched on the Q output of register  182 . 
     FIG. 7 shows an exemplary read/write state machine  172  according to the present invention. The names for the states and signals are exemplary. As shown in FIG. 7, the read/write state machine  172  has four states: IDLE  174 , PAUSE  176 , REQUEST  178 , and END  180 . Except for the differences noted below, the descriptions previously provided for the states IDLE  74 , PAUSE  76 , REQUEST  78 , and END  80  respectively describe the states IDLE  174 , PAUSE  176 , REQUEST  178 , and END  180 . 
     In addition, except for the differences noted below, read/write state machine  172  has the same state transitions as those previously described for read/write state machine  72 . The states of the read/write state machine  172  of the present invention differs from the prior art read/write state machine  172  as follows: 
     State 0—IDLE 
     When the read/write state machine  172  detects the signal START, the read/write state machine  172  determines whether the issued command is for a memory read cycle. If the issued command is for a memory read cycle, the BUF.EN signal is asserted to store the address, data, and control signals in the bus buffer  168 . In addition, the read/write state machine transitions to a state REQUEST  178 . If the issued command is not for a memory read cycle, the read/write state machine transitions to a state PAUSE  176 . 
     State 3—REQUEST 
     In the state REQUEST  174 , if the issued command is for a memory read cycle, the signal MEM REQ is asserted to direct the SRAM Controller  56  to fetch the requested information from memory  36 . In addition, in the state REQUEST  174 , the requested information appears on the outputs of memory  36  and is transferred to the local bus mux  146  where it is sampled by the CPU  22 . 
     FIG. 8 shows a timing diagram for exemplary read cycles in the computer system  20  that includes the graphics controller  124  according to the present invention. The timing diagram shows the signal produced by the bus clock  32 , the state of the read/write state machine  172 , and various signals. 
     A first memory read cycle is initiated when the CPU  22  issues a command by placing address, data, and control signals on the system bus  28 . The control signals are decoded to assert the WAIT# and START signals. As shown in FIG. 8, the signal WAIT# is asserted before BCLK  1  and the signal START is asserted in BCLK  1 . In BCLK  1 , the signal BUF.EN  1  is also asserted to store the address, data, and control signals in the bus buffer  168 . In BCLK  2 , the signal MEM REQ is asserted to direct the SRAM Controller  56  to fetch the requested information from memory  36 . During BCLK  3 , the requested information appears on the outputs of memory  36  as indicated by the signal designated SRAM RD DATA. In addition, during BCLK  3 , the requested information is transferred from the output of memory  36  to the local bus mux  146  on the falling edge of the signal MEM REQ EN NEG. In addition, the signal WAIT# is de-asserted. In BCLK  4 , the CPU  22  samples local bus mux  146  to obtain the requested information. The first command is completed during BCLK  5  and a second memory read cycle begins in BCLK  6 . As FIG. 8 shows, an advantage of read/write state machine  172  is that only 5 BCLKS must elapse after the CPU  22  has issued a read command before the graphics controller  24  can accept a subsequent command from the CPU  22 . In each memory read cycle, the CPU  22  is required to insert only 2 wait states. 
     The present invention may be used in conjunction with the subject matter that is disclosed in U.S. patent application Ser. No. 10/131,631, (“High Performance Graphics Controller”) which was filed concurrently herewith, now pending and incorporated by reference herein in its entirety. In addition, the invention may be used in conjunction with the subject matter that is disclosed in U.S. patent application Ser. No. 10/131,644 (“Graphics Controller for High Speed Transmission of Memory Write Commands”), which was filed concurrently herewith, also incorporated by reference herein in its entirety. The combination of the present invention with the subject matter of these two applications provides for further increased speed and efficiency in communications between a CPU and a graphics controller. 
     FIG. 9 shows a state diagram for a graphics controller for high speed transmission of memory read commands incorporating selected features of the aforementioned High Performance Graphics Controller and the Graphics Controller for High Speed Transmission of Memory Write Commands. An exemplary read/write state machine  272  is shown. The read/write state machine  272  comprises two idle states (IDL 1 , IDL 2 ), two pause states (PAU 1 , PAU 2 ), two request states (REQ 1 , REQ 2 ), and two end states (END 1 , END 2 ), according to the Graphics Controller for High Speed Transmission of Memory Write Commands. 
     State 0—IDL 1   
     In a state IDL 1   274 , the read/write state machine  272  waits to receive the start signal (START). The IDL 1   274  state is the initial state after start-up for the read/write state machine  272 . When the read/write state machine  272  detects the START signal, the wait signal (WAIT#) is asserted. The read/write state machine  272  stores control, address, and data signals into the bus buffer  168  by asserting a first buffer enable signal (BUF.EN 1 ). In addition, the read/write state machine  272  determines whether the issued command is for a memory read cycle. If the issued command is for a memory read cycle, the read/write state machine  272  transitions to a state REQ 1   278 . If the issued command is not for a memory read cycle, the read/write state machine  272  transitions to a state PAU 1   276 . 
     State 1—PAU 1   
     In the state PAU 1   276 , the read/write state machine  272  checks to see whether the graphics controller  124  is ready to process another command. If the graphics controller  124  has not yet finished processing a previous command, the read/write state machine  272  remains in the state PAU 1   276 . On the other hand, if the graphics controller  124  has finished processing the previous command, the read/write state machine  272  transitions to a state REQ 1   278 . 
     State 3—REQ 1   
     In the state REQ 1   278 , the read/write state machine  272  generates the appropriate internal signals needed to process the command. In addition, the read/write state machine  272  monitors for a signal that indicates that the command is complete and for the signal START. If the read/write state machine  272  detects a signal indicating that the command is complete, the read/write state machine  272  transitions to a state END 1   280 . If the read/write state machine  272  additionally detects that the signal START is asserted for a command that is for a write to the memory  36 , the registers  48 , or the look-up table  50 , the read/write state machine  272  asserts a second buffer enable signal (BUF.EN 2 ) and transitions to a state PAU 2   284 . The signal BUF.EN 2  causes control, address, and data signals to be stored into the bus buffer  168 . 
     State 2—END 1   
     In the state END 1   280 , internal functions are performed. In addition, the read/write state machine  272  checks to see whether a signal START has been asserted. If the signal START has been asserted and the issued command is for a write to the memory  36 , the registers  48 , or the look-up table  50 , the read/write state machine  272  transitions to the state PAU 2   284  and the signal BUF.EN 2  is asserted. On the other hand, if the signal START has been asserted and the issued command is for a memory read, the read/write state machine  272  transitions to the state PAU 1   276  and the signal BUF.EN 1  is asserted. If the signal START has not been asserted, the read/write state machine  272  transitions a state IDL 2   282 . 
     State 4—IDL 2   
     In the state IDL 2   282 , the read/write state machine  272  waits to receive the signal START. If the signal START is detected for a command that is for a write to the memory  36 , the registers  48 , or the look-up table  50 , the read/write state machine  272  asserts the signal buffer enable signal (BUF.EN  2 ) as it transitions to a state PAU 2   284 . If the signal START is detected for a command that is for a memory read, the read/write state machine  272  transitions to the state PAU 1   276  and asserts the first buffer enable signal (BUF.EN 1 ) as it makes the transition. In both of the foregoing transitions, the signal WAIT# is asserted. On the other hand, if the signal START is not detected, the read/write state machine  272  transitions to the state IDL 1   274  on the next BCLK. 
     State 5—PAU 2   
     In the state PAU 2   284 , the read/write state machine  272  checks to see whether the graphics controller  124  is ready to process another command. If a signal is detected that indicates that the graphics controller  124  has not yet finished processing a previous command, the read/write state machine  272  remains in the state PAU 2   284 . On the other hand, if such a signal is not detected, the read/write state machine  272  transitions to a state REQ 2   286 . 
     State 7—REQ 2   
     In the state REQ 1   278 , the read/write state machine  272  generates the appropriate internal signals needed to process the command. In addition, the read/write state machine  272  monitors for a signal that indicates that the command is complete and for the signal START. If the read/write state machine  272  detects a signal indicating the command is complete, the read/write state machine  272  transitions to a state END 2   288 . If the read/write state machine  272  additionally detects that the signal START is asserted for a command that is for a write to the memory  36 , the registers  48 , or the look-up table  50 , the read/write state machine  272  asserts the first buffer enable signal (BUF.EN  1 ) and transitions to a state PAU 1   276 . 
     State 6—END 2   
     In the state END 2   288 , internal functions are performed. In addition, the read/write state machine  272  checks to see whether a signal START has been asserted. If the signal START has been asserted and the issued command is for a write to the memory  36 , the registers  48 , or the look-up table  50 , the read/write state machine  272  transitions to the state PAU 1   276  and the signal BUF.EN 1  is asserted. On the other hand, if the signal START has been asserted and the issued command is for a memory read, the read/write state machine  272  transitions to the state IDL 1   274 . Similarly, if the signal START has not been asserted, the read/write state machine  272  transitions to the state IDL 1   274 . 
     Persons of ordinary skill in the art will readily appreciate that the read/write state machine  172  can be implemented in a number of different ways. The read/write state machine  172  is preferably implemented as a logic circuit. A read/write logic circuit may be constructed according to traditional design methods using a plurality of simple logic gates. As one skilled in the art will appreciate, the read/write logic circuit is preferably implemented by creating a source file in a hardware definition language such as VHDL or Verilog™ because the read/write logic circuit will typically require 200-300 simple logic gates. The read/write source file may by synthesized using an automated design tool to create a net-list. The net list may be used by an automated layout tool to create a read/write logic circuit for implementation in a graphics controller chip or other ASIC. Alternatively, the net-list may be used by a device programmer to create a fuse-map that can be used to program a PLA, PLD, or other similar programmable chip to implement the read/write logic circuit. 
     Moreover, while the present invention is preferably implemented in hardware, it will be understood that the read/write state machine  172  may be implemented in software as well. For example, the method of read/write state machine  172  may be embodied in a program of instructions that is stored on a medium that is read and executed by a machine to regulate the transmission of command information from a CPU to a memory controller. Any medium that can be read and executed by a machine, such as RAM, ROM, floppy disk, or fixed disk is contemplated. 
     The computer system  20  illustrates a preferred context for the present invention. As previously indicated, other contexts for the invention are contemplated. Any host device, such as a video decoder, an audio processor, a graphics controller, or a memory controller may be substituted for the CPU  22 . Moreover, the display  26  is preferably a Liquid Crystal Display; however, the present invention may be practiced without the display  26  or with any type of video display or other output device, such as a CRT display or a printer. Additionally, while the memory  36  is preferably synchronous random access memory (“SRAM”), any type of memory may be substituted for SRAM, such as DRAM. In addition, the system bus  28  may be replaced with separate busses for address, data, and control signals. Moreover, any alternative means for communicating address, data, and control information between the CPU  22  and the graphics controller  124  may be substituted for the system bus  28 . 
     The terms and expressions that have been employed in the foregoing specification are used as terms of description and not of limitation, and are not intended to exclude equivalents of the features shown and described or portions of them. The scope of the invention is defined and limited only by the claims that follow.