Abstract:
An array of memory cells configured to store at least one bit per one F 2  includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures.

Description:
TECHNICAL FIELD  
         [0001]    This invention relates to a one F 2  memory cell, arrays of such memory cells, electronic devices employing such memory cells and arrays, and methods related to such memory cells.  
         BACKGROUND OF THE INVENTION  
         [0002]    Various types of memory devices are used in electronic systems. Some types of memory device, such as DRAM (dynamic random access memory) provide large amounts of readable and writable data storage with modest power budget and in favorably small form factor, but are not as fast as other types of memory devices and provide volatile data storage capability. Volatile data storage means that the memory must be continuously powered in order to retain data, and the stored data are lost when the power is interrupted. Nonvolatile memories are capable of retaining data without requiring electrical power.  
           [0003]    Other types of memory can provide read-only or read-write capabilities and non-volatile data storage, but are much slower in operation. These include CD-ROM devices, CD-WORM devices, magnetic data storage devices (hard discs, floppy discs, tapes and so forth), magneto-optical devices and the like.  
           [0004]    Still other types of memory provide very high speed operation but also demand high power budgets. Static RAM or SRAM is an example of such memory devices.  
           [0005]    In most computer systems, different memory types are blended to selectively gain the benefits that each technology can offer. For example, read-only memories or ROM, EEPROM and the like are typically used to store limited amounts of relatively infrequently-accessed data such as a basic input-output system. These memories are employed to store data that, in response to a power ON situation, configure a processor to be able to load larger amounts of software such as an operating system from a high capacity non-volatile memory device such as a hard drive. The operating system and application software are typically read from the high capacity memory and corresponding images are stored in DRAM.  
           [0006]    As the processor executes instructions, some types of data may be repeatedly fetched from memory. As a result, some SRAM or other high speed memory is typically provided as “cache” memory in conjunction with the processor and may be included on the processor integrated circuit or chip and/or very near it.  
           [0007]    Several different kinds of memory device are involved in most modern computing devices, and in many types of appliances that include automated and/or programmable features (home entertainment devices, telecommunications devices, automotive control systems etc.). As system and software complexity increase, need for additional memory increases. Desire for portability, computation power and/or practicality result in increased pressure to reduce both power consumption and circuit area per bit.  
           [0008]    DRAMs have been developed to very high capacities in part because the memory cells can be manufactured to have a very small area, and the power draw per cell can also be made quite small. In turn, this allows memory integrated circuits to be made that incorporate millions of memory cells in each chip. Typical one-transistor, one-capacitor DRAM memory cells can be produced to have extremely small areal requirements.  
           [0009]    Such areas are often equal to about 3F×2F, or less, where “F” is defined as equal to one-half of minimum pitch (see FIG. 4, infra). Minimum pitch (i.e., “P”) is defined as equal to the smallest distance of a line width (i.e., “W”) plus width of a space immediately adjacent the line on one side of the line between the line and a next adjacent line in a repeated pattern within the array (i.e., “S”). Thus, in many implementations, the consumed area of a given DRAM cell is no greater than about 8F 2 .  
           [0010]    However, because DRAMs are volatile memory devices, they require “refresh” operations. In a refresh operation, data are read out of each memory cell, amplified and written back into the DRAM. As a first result, the DRAM circuit is usually not available for other kinds of memory operations during the refresh operation. Additionally, refresh operations are carried out periodically, resulting in times during which data cannot be readily extracted from or written to DRAMs. As a second result, some amount of electrical power is always needed to store data in DRAM devices.  
           [0011]    As a third result, boot operations for computers such as personal computers involve a period during which the computer cannot be used following power ON initiation. During this period, operating system instructions and associated data, and application instructions and associated data, are read from relatively slow, non-volatile memory, such as a conventional disc drive, are decoded by the processing unit and the resultant instructions and associated data are loaded into modules incorporating relatively rapidly-accessible, but volatile, memory such as DRAM. Other consequences flow from the properties of the memory systems included in various electronic devices and the increasingly complex software employed with them, however, these examples serve to illustrate ongoing needs.  
           [0012]    Needed are methods and apparatus relating to non-volatile memory providing high areal data storage capacity, reprogrammability, low power consumption and relatively high data access speed.  
         SUMMARY OF THE INVENTION  
         [0013]    In a first aspect, the present invention includes a method for making an array of memory cells configured to store at least one bit per one F 2 . The method includes doping a first region of a semiconductor substrate and incising the substrate to provide an array of substantially vertical edge surfaces. Pairs of the edge surfaces face one another and are spaced apart a distance equal to one half of a pitch of the array of edges. The method also includes doping second regions between the pairs of edge surfaces and disposing respective structures each providing an electronic memory function on at least some respective ones of the edge surfaces. The method also includes establishing electrical contacts to the first and second regions.  
           [0014]    In another aspect, the present invention includes a method for making an array of memory cells configured to store at least one bit per one F 2 . The method includes disposing substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array and establishing electrical contacts to memory cells including the vertical structures.  
           [0015]    In a further aspect, the present invention includes an array of memory cells configured to store at least one bit per one F 2  formed using vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the vertical structures.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]    Embodiments of the invention are described below with reference to the following accompanying drawings.  
         [0017]    [0017]FIG. 1 is a simplified side view, in section, of a semiconductor substrate portion at one stage in processing, in accordance with an embodiment of the present invention.  
         [0018]    [0018]FIG. 2 is a simplified side view, in section, of the substrate portion of FIG. 1 at a later stage in processing, in accordance with an embodiment of the present invention.  
         [0019]    [0019]FIG. 3 is a simplified side view, in section, of the substrate portion of FIG. 2 at a later stage in processing, in accordance with an embodiment of the present invention.  
         [0020]    [0020]FIG. 4 is a simplified plan view of a substrate portion showing a portion of a memory cell array, in accordance with an embodiment of the present invention.  
         [0021]    [0021]FIG. 5 is a simplified side view, in section, illustrating a relationship between the structures of FIGS.  1 - 3  and the plan view of FIG. 4, in accordance with an embodiment of the present invention.  
         [0022]    [0022]FIG. 6 is a simplified plan view of a memory cell array illustrating an interconnection arrangement for the memory cell array of FIG. 4, in accordance with an embodiment of the present invention.  
         [0023]    [0023]FIG. 7 is a simplified side view, in section, taken along section lines  7 - 7  of FIG. 6, illustrating part of an interconnection arrangement in accordance with an embodiment of the present invention.  
         [0024]    [0024]FIG. 8 is a simplified side view, in section, taken along section lines  8 - 8  of FIG. 6, illustrating part of an interconnection arrangement in accordance with an embodiment of the present invention.  
         [0025]    [0025]FIG. 9 is a simplified block diagram of a computer employing the inventive memory array associated with FIGS.  1 - 8 , in accordance with an embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0026]    This disclosure of embodiments in accordance with the present invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).  
         [0027]    As used herein, the terms “semiconductor substrate” or “semiconductive substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.  
         [0028]    [0028]FIG. 1 is a simplified side view, in section, of a semiconductor substrate portion  20  at one stage in processing, in accordance with an embodiment of the present invention. The portion  20  includes etched or incised recesses  22 , doped regions  24  and  26  and caps  28 . The etched recesses  22  form trenches extending along an axis into and out of the page of FIG. 1.  
         [0029]    In one embodiment, the doped regions  24  are implanted n+ regions. In one embodiment, the doped regions  24  are formed by a blanket implant. In one embodiment, the caps  28  are dielectric caps and may be formed using conventional silicon nitride and conventional patterning techniques. In one embodiment, the etched recesses  22  are then etched using conventional plasma etching techniques. In one embodiment, the doped regions  26  are then doped by implantation to form n+ regions. The etched or incised recesses  22  may be formed by plasma etching, laser-assisted techniques or any other method presently known or that may be developed. In one embodiment, the recesses  22  are formed to have substantially vertical sidewalls relative to a top surface of the substrate portion  20 . In one embodiment, substantially vertical means at 90 degrees to the substrate surface, plus or minus ten degrees.  
         [0030]    [0030]FIG. 2 provides a simplified side view, in section, of the substrate portion  20  of FIG. 1 at a later stage in processing, in accordance with an embodiment of the present invention. The portion  20  of FIG. 2 includes thick oxide regions  32 , ONO regions  34  formed on sidewalls  36  of the recesses  22 , gate material  38  and a conductive layer  40 . In one embodiment, the gate material  38  comprises conductively-doped polycrystalline silicon.  
         [0031]    In one embodiment, conventional techniques are employed to oxidize the doped regions  24  and  26  preferentially with respect to sidewalls  36 . As a result, the thick oxide regions  32  are formed at the same time as a thinner oxide  42  on the sidewalls  36 . These oxides also serve to isolate the doped regions  24  and  26  from what will become transistor channels along the sidewalls  36 . Other techniques for isolation may be employed. For example, in one embodiment, high density plasma grown oxides may be employed. In one embodiment, spacers may be employed.  
         [0032]    In one embodiment, conventional techniques are then employed to provide a nitride layer  44  and an oxide layer  46 , as is described, for example, in “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell”, by Boaz Eitan et al., IEEE Electron Device Letters, Vol. 21, No. 11, November 2000, pp. 543-545, IEEE Catalogue No. 0741-3106/00, or in “A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device” by T. Y. Chan et al., IEEE Electron Device Letters, Vol. EDL-8, No. 3, March, 1987, pp. 93-95, IEEE Catalogue No. 0741-3106/87/0300-0093.  
         [0033]    In one embodiment, the thin oxide  42 , nitride layer  44  and oxide layer  46  combine to form the ONO layer  34 , such as is employed in SONOS devices, while the polysilicon  38  forms a control gate. In operation, application of suitable electrical biases to the doped regions  24 ,  26  and the control gate  38  cause hot majority charge carriers to be injected into the nitride layer  44  and become trapped, providing a threshold voltage shift and thus providing multiple, alternative, measurable electrical states representing stored data. “Hot” charge carriers are not in thermal equilibrium with their environment. In other words, hot charge carriers represent a situation where a population of high kinetic energy charge carriers exist. Hot charge carriers may be electrons or holes.  
         [0034]    SONOS devices are capable of storing more than one bit per gate  38 . Typically, the hot carriers are injected into one side  47  or  47 ′ of the ONO layer  34 , adjacent a contact, such as the region  24  or the region  26 , that provides a high electrical field.  
         [0035]    By reversing the polarity of the potentials applied to the regions  24  and  26 , charge may be injected into the other side  47 ′ or  47  of the ONO layer  34 . Thus, four electronically-discriminable and distinct states can be easily provided with a single gate  38 . As a result, the structure shown in FIG. 2 is capable of storing at least four bits per gate  38 .  
         [0036]    [0036]FIG. 3 is a simplified side view, in section, of the substrate portion  20  of FIG. 1 at an alternative stage in processing, in accordance with an embodiment of the present invention. The embodiment shown in FIG. 3 includes the oxide regions  32  and  42 , but a floating gate  48  is formed on the thin oxide region  42 . A conventional oxide or nitride insulator  49  is formed on the floating gate  48 , followed by deposition of gate material  38 . Floating gate devices are known and operate by injecting hot charge carriers, which may comprise electrons or holes, into the floating gate  48 .  
         [0037]    Floating gate devices can be programmed to different charge levels that can be electrically distinct and distinguishable. As a result, it is possible to program more data than one bit into each floating gate device, and each externally addressable gate  38  thus corresponds to more than one stored bit. Typically, charge levels of 0, Q, 2Q and 3Q might be employed, where Q represents some amount of charge corresponding to a reliably-distinguishable output signal.  
         [0038]    [0038]FIG. 4 is a simplified plan view of a substrate portion showing a portion of a memory cell array  50 , in accordance with an embodiment of the present invention. FIG. 4 also provides examples of pitch P, width W, space S and minimum feature size F, as described in the Background. An exemplary memory cell area  52  can be seen to be about one F 2 , in contrast to prior art memory cells. Wordlines  54  are formed from the conductive layer  40 , and bitlines  56  and  58  are formed.  
         [0039]    [0039]FIG. 5 is a simplified side view, in section, illustrating a relationship between the structures of FIGS.  1 - 3  and the plan view of FIG. 4, in accordance with an embodiment of the present invention. The trenches  22  correspond to bitlines  56  and  58 , as is explained below in more detail with reference to FIGS.  6 - 8 .  
         [0040]    The density of memory arrays such as that described with reference to FIGS.  1 - 5  can require interconnection arrangements that differ from prior art memory arrays. One embodiment of a new type of interconnection arrangement useful with such memory systems is described below with reference to FIGS.  6 - 8 .  
         [0041]    [0041]FIG. 6 is a simplified plan view illustrating an interconnection arrangement  60  for the memory cell array  50  of FIG. 4, in accordance with an embodiment of the present invention. The interconnection arrangement  60  includes multiple patterned conductive layers  62  and  64 , separated by conventional interlevel dielectric material  65  (FIGS. 7 and 8). The views in FIGS.  6 - 8  have been simplified to show correspondence with the other Figs. and to avoid undue complexity. Shallow trench isolation regions  67  isolate selected portions from one another.  
         [0042]    [0042]FIG. 7 is a simplified side view, in section, taken along section lines  7 - 7  of FIG. 6, illustrating part of an interconnection arrangement in accordance with an embodiment of the present invention.  
         [0043]    [0043]FIG. 8 is a simplified side view, in section, taken along section lines  8 - 8  of FIG. 6, illustrating part of an interconnection arrangement in accordance with an embodiment of the present invention.  
         [0044]    With reference to FIGS.  6 - 8 , the patterned conductive layer  62  extends upward to nodes  70 ,  70 ′,  70 ″ and establishes electrical communication between the conductive layers  62  and selected portions of the doped region  24 . The patterned conductive layer  62  stops at the line denoted  72 ,  72 ′.  
         [0045]    Similarly, other portions of the patterned conductive layer  62  extend from the line denoted  74 ,  74 ′ and extend upward, providing electrical communication from nodes  76 ,  76 ′,  76 ″ to other circuit elements. The nodes  76 ,  76 ′,  76 ″ provide contact to selected portions of the doped region  24 .  
         [0046]    In contrast, patterned conductive layers  64  extend from top to bottom of FIG. 6 and electrically couple to nodes  78 ,  78 ′ and thus to doped region  26 .  
         [0047]    Such is but on example of a simplified interconnection arrangement suitable for use with the memory devices of FIGS.  1 - 5 . Other arrangements are possible.  
         [0048]    [0048]FIG. 9 is a simplified block diagram of a computer  100  employing the inventive memory array associated with FIGS.  1 - 8 , in accordance with an embodiment of the present invention. The computer  100  includes a memory  102 , including memory cells in accordance with the present invention, a processor  104  and a bus  106  coupling the memory  102  and processor  104 . An input device  108 , which may be a tactile input device, is coupled to the bus  106 , and an output device  110  is coupled to the bus  106 .  
         [0049]    The computer  100  may be employed in a broad variety of settings. For example, the tactile input device  108  could include voice and speech recognition capabilities, or could be part of a dashboard or control system for a vehicle, or could be a keyboard or mouse or combination thereof, or could be a dialing instruction input device for a telecommunications device such as a telephone or cellular telephone, or could be associated with some other type of appliance, such as a television, a washing machine or refrigerator, microwave oven or the like.  
         [0050]    Similarly, the output device  110  could be a visual display that is part of a dashboard or other control system for a vehicle, or an alphanumeric display for a computer (e.g., CRT, flat panel TFT display or the like), or a visual display associated with a telecommunications device, or could be associated with a home or industrial appliance. The output device  110  may include other capabilities for communication, such as an annunciator or speaker, Braille signaling capability and the like.  
         [0051]    In operation, a command sequence is initiated, either by a user associated with the device or a remote party (e.g., a caller using a telephone or a service provider initiating a data stream). The processor  104  executes the command sequence in accordance with instructions stored in the memory  102 , using portions of the memory  102  for temporary storage of intermediate results and other portions of the memory  102  for longer-term storage of other results or data (such as telephone numbers, elapsed miles etc.). Visual, aural and other types of output signals may be generated to advise the user of status of various aspects of the system in which the computer  100  is resident.  
         [0052]    In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.