Abstract:
An integrated circuit apparatus is provided with package-level connectivity, between internal electronic circuitry thereof and contact points on a package substrate thereof, without requiring top metal pads or bonding wires.

Description:
This application claims priority under 35 USC 119 to U.S. Provisional Application No. 61/234,473, which was filed on Aug. 17, 2009 and is incorporated herein by reference. 
    
    
     FIELD 
     This work relates generally to integrated circuits and, more particularly, to package-level connection to the internal circuitry of an integrated circuit. 
     BACKGROUND 
     Moore&#39;s law has affected the microchip world where many system applications have demanded more functionality and high performance in ever-smaller form factors. The manufacturing cost also has increased since the first process technology of the late 1950&#39;s. As shown in  FIG. 1 , connecting signals to a microchip  11  from package level requires some chip area for metal bond pads  10 . The pad size (area) must satisfy requirements of the packaging process and the minimum possible bonding wire diameter. In order to prevent mechanical damage and thermal stress in each corner of the microchip, dummy pads such as  12  are typically provided. 
     These kinds of factors require chip area to be sacrificed for bond pads. Along with the bond pad area, some space is provided between the pad and the chip edge to avoid cracks near the pad. 
     Wire bonding requires electrical connection to the pad, and thus a large enough metal pad area to permit safely connecting the bonding wire to the pad. This results in relatively large capacitive and inductive loading from the metal pad area and the bonding wire itself. Although internal transistor sizes have been steadily reduced by innovations in process technology, the pad size and bonding wire diameter have not kept pace with the shrink ratio of the transistors. Due to this unbalanced trend, the relative influence of the capacitive and inductive loading effect of the pad and bonding wire is increasing seriously. This is generally detrimental, and particularly so for high-speed applications. 
     It is therefore desirable to provide for reducing the capacitive and inductive loading, and the chip area sacrifices, associated with prior art integrated circuit chip connections at the package level. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  diagrammatically illustrates a conventional integrated circuit chip with wire bond pads. 
         FIGS. 2-6  diagrammatically illustrate integrated circuit apparatus with lateral pad arrangements according to various example embodiments of the present work. 
         FIG. 7  diagrammatically illustrates a stack of interconnected integrated circuit chips with lateral pads provided for packaging together according to example embodiments of the present work. 
         FIG. 8  diagrammatically illustrates an electronic circuit apparatus including an integrated circuit apparatus from one of  FIGS. 2-4  and  7  according to example embodiments of the present work. 
     
    
    
     DETAILED DESCRIPTION 
     Example embodiments of the present work provide lateral pads that replace the conventional wire bonding pads of  FIG. 1 . (Although the term “lateral pad” is used herein for expository purposes, it will be understood from the following description that “lateral pads” are not structured the same way as the conventional wire bonding pads shown in  FIG. 1 .) The present work exploits the fact that, when a conventional wafer is sawed (e.g., using a laser) into individual integrated circuit chips or dice, the lateral edges of each individual chip are available to provide access to the internal circuitry of the chip. 
       FIG. 2  illustrates lateral pad structures that are accessible at the lateral edges of a chip  100  according to example embodiments of the present work. The lateral pads designated at  101  are for general signals of the chip, such as address, data and control signals. The lateral pads designated at  102  are for power supply, and thus have relatively larger areas (to carry relatively higher current loads) than do the lateral pads  101 . No additional wafer processing steps are required to produce the lateral pads  101  and  102 . Metal paths on each chip are simply drawn out as needed to the location(s) on the wafer where sawing occurs. The wafer sawing operation (shown diagrammatically in  FIG. 2 ) then exposes the lateral pads  101  and  102  on the chip edge(s) produced by the sawing. The use of lateral pads eliminates processing steps required for conventional wire bonding pads, and the lateral pads do not consume circuit area on the chip as do conventional wire bonding pads. 
     Table I summarizes characteristics comparisons between lateral pad structure according to the present work and conventional wire bonding pad structure. 
     
       
         
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 Characteristic 
                 Lateral pad structure 
                 General pad structure 
               
               
                   
               
             
             
               
                 Physical pad 
                 Thickness of available 
                 Minimum requirement of 
               
               
                 area 
                 metal layers 
                 metal area based on 
               
               
                   
                   
                 process technology. 
               
               
                 Capacitive 
                 Very small (Allowable 
                 Pad and metal 
               
               
                 loading of pad 
                 metal thickness based 
                 connection part (at least 
               
               
                   
                 capacitive loading) 
                 1.0 pF) 
               
               
                 Inductive 
                 No bonding wire 
                 Inductive loading of 
               
               
                 loading from 
                 required. Instead of the 
                 bonding wire. 
               
               
                 bonding wire 
                 bonding wire, additional 
               
               
                   
                 metal line process is 
               
               
                   
                 performed. Substantially 
               
               
                   
                 no inductive loading. 
               
               
                 Pad metal 
                 Any metal layer 
                 Top metal layer 
               
               
                   
               
             
          
         
       
     
     As shown in Table 1 and explained below, lateral pads do not require conventional bonding wires, and thus eliminate the inductive loading associated with bonding wires. Moreover, as also shown in Table 1 and explained below, the physical size of the lateral pads is determined by the metal layer thicknesses provided by the process, which results in much less capacitive loading than is imposed by conventional wire bonding pads, whose physical size is determined by the minimum metal area requirements of the process and/or the minimum bonding wire diameter. These load reductions provided by lateral pads are particularly advantageous in terms of operating speed and power consumption. 
     As seen from Table 1, in various embodiments, any of the lateral pads  101  and  102  of  FIG. 2  may be part of any of the metal layers of the chip, as may be convenient to facilitate design. 
       FIG. 3  shows conductive connections at  205  between lateral pads  204  and respectively corresponding contact points  203  on a conventional package substrate  202  according to example embodiments of the present work. The dimensions in  FIG. 3  are not shown to scale. In some embodiments, each connection at  205  is provided by a metal mass whose width is approximately the same as the width of the corresponding lateral pad  204 , which is simply the metal width of the particular process used to produce the chip  201 . The size of the metal mass at  205  may be quite small compared to the size of conventional bonding wire. In some embodiments, the metal mass at  205  is provided by processing similar to the lead processing used for package mounting on conventional integrated circuit boards, the differences being the scale of the metal mass and the material used. In various embodiments, the metal at  205  may be the same as or different from process metal used in the wafer fabrication process. In various embodiments, the metal used at  205  depends on factors such as reliability and cost. As indicated above, any lateral pad may be part of any metal layer used in the chip. 
     It is common to use a back-grinding process to reduce wafer thickness in order to facilitate stacking multiple chips. However, because the size of the lateral pads depends only on the dimensions of the metal layers in the fabrication process technology, the use of lateral pads does not present technical issues in this environment. 
       FIGS. 4 and 5  illustrate further embodiments that use TSV (Through Silicon Via) processing to provide vias  405  that connect the lateral pad metals  404  to contact points  403  on a conventional package substrate  402  of a chip  401 .  FIG. 5  shows a cross-sectional detail of a portion  406  of  FIG. 4 . It will be noted that, in such TSV embodiments, the exposure of the lateral pad metal  404  at the edge of the chip  401  is not strictly necessary for the desired TSV connection to the contact points  403  of the package substrate  402 . 
       FIG. 6  diagrammatically illustrates metal paths  303  (on various different metal layers of the chip in some embodiments) extending from internal circuitry  301 ,  302  of a chip  300  to the edges of the chip, to provide lateral pads according to example embodiments of the present work. The length of the metal paths  303  is exaggerated for clarity of illustration. The actual length in some embodiments is less than 50 um. When the wafer is sawed, the metal paths  303  are exposed at the edges of the chip  300  after passivation, thereby forming the lateral pads. The metal mass for connecting the lateral pad to the contact on the substrate (see also  205   FIG. 2 ) may be deposited using any suitable conventional metal deposition process. The wafer is thin enough that the lateral void effect of deposition will be negligible. Some embodiments use a conventional physical vapor deposition (PVD) process to form the metal mass. The process is readily extended to multiple chip connections where the chips  201  are stacked vertically as shown at  71  in  FIG. 7 . 
     Referring to  FIGS. 3-5  and  7 , once the lateral pad structures are connected to the contact points on the package substrate, conventional integrated circuit packaging techniques may be used to package the illustrated integrated circuit apparatus. The result is a packaged integrated circuit apparatus whose internal circuitry is connected to the contact points of the package substrate in one of the manners shown in  FIGS. 3-5  and  7 , rather than by wires connected to bond pads on the top metal layer of the integrated circuit apparatus as in the prior art. The contact points on the package substrate are electrically accessible via external terminals (not explicitly shown in the drawings) of the packaged integrated circuit apparatus, which external terminals (e.g., pins) are connected to the contact points according to the particular packaging technique. 
     External circuitry may be connected to the packaged integrated circuit apparatus according to the present work in any manner that would be suitable for connecting the external circuitry to a conventional packaged integrated circuit apparatus.  FIG. 8  diagrammatically illustrates an example embodiment of the resulting electronic circuit apparatus. In  FIG. 8 , a packaged integrated circuit apparatus  81  may include a lateral pad arrangement of the type described above relative to one of  FIGS. 3-5  and  7 . External circuitry  82  is connected to the packaged integrated circuit apparatus  81  by any suitable connection structure  83 . The external circuitry  82  may contain one or more packaged integrated circuit apparatus, or circuitry other than packaged integrated circuit apparatus, or a combination of packaged integrated circuit apparatus and circuitry other than packaged integrated circuit apparatus. 
     Although example embodiments of the invention have been described above in detail, this does not limit the scope of the invention, which can be practiced in a variety of embodiments.