Abstract:
A reference current generating apparatus is provided which is capable of generating a reference current having no temperature dependency, without increasing a layout area. The reference current generating apparatus includes a constant current generating circuit having a differential amplifier, a constant current generating circuit connected to the constant current generating circuit and having a differential amplifier, and an output circuit connected to the constant current generating circuit for outputting first and second reference voltages. The constant current generating circuit generates a reference current by enabling selection of a mirror ratio of a transistor that conducts summing of a constant current proportional to a thermal voltage, and by enabling switching of a dividing voltage from a resistor to an input of the differential amplifier, to generate a constant current proportional to a diode voltage via a high impedance MOS gate.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention generally relates to a reference current generating apparatus for generating an electric reference current (which may hereinafter be referred to as a reference current), in order to generate an electric reference voltage (which may hereinafter be referred to as a reference voltage) in a semiconductor integrated circuit. More particularly, the present invention relates to a reference current generating apparatus which is capable of adjusting non-uniformity of a reference current which might occur due to, for example, an error in the accuracy of resistance ratio and the like which may occur during manufacture of the apparatus. 
     2. Description of the Related Art 
     A typical example of a conventional electric circuit for generating a reference current in order to generate a reference voltage is disclosed in Japanese Laid-open Patent Application Publication No. 2000-75947. A band gap reference circuit (BGR circuit) is shown in FIG. 3 of Japanese Laid-open Patent Application Publication No. 2000-75947, and includes an operational amplifier used to generate a reference current. The reference current is a combination of a constant current proportional to a thermal voltage, and a current proportional to a diode voltage. An operation bias current of the operational amplifier is generated using the reference current. 
     In addition, a band gap reference circuit is shown in FIG. 5 of Japanese Laid-open Patent Application Publication No. 2000-75947. The band gap reference circuit shown in FIG. 5 includes a current source transistor that generates reference current (1/R1*(Vbe+R1/R3*kT/q*LN(n)), which is proportional to 1/R1 of a band gap voltage (Vbe+R1/R3*kT/q*LN(n)) and which has no dependency on temperature. The band gap reference circuit generates a constant reference voltage (=R4/R1*[Vbe+R1/R3*kT/q*LN(n)] at a Vref terminal by flowing the reference current through a load resistor R4 (884 kΩ) connected to the current source transistor. The constant reference voltage is R4/R1 times as high as the band gap voltage, and has no dependency on temperature. It is to be understood that Vbe is a terminal voltage of a diode, R1 is a resistor of 2063 kΩ, R3 is a resistor of 393 kΩ, k is Boltzmann&#39;s constant, T is absolute temperature, q is units of electric charge, and n is diode capacitance ratio. 
     Nevertheless, the band gap reference circuit disclosed in Japanese Laid-open Patent Application Publication No. 2000-75947 has no means for adjusting error in specific accuracy which may occur due to mismatch of resistor R4 and resistor R1 in view of manufacture thereof, and an error in specific accuracy which may occur due to mismatch of resistor R3 and resistor R1 in view of manufacture thereof, due to mask misalignment, dispersion of impurity concentration and the like. This makes it difficult for individual elements to generate a constant reference voltage (=R4/R1*[Vbe+R1/R3*kT/q*LN(n)]) having no dependency on temperature. 
     In the meantime, FIG. 1 of U.S. Pat. No. 6,501,256 shows a means for adjusting a mismatch error in specific accuracy of resistors in view of manufacture thereof, in a band gap reference circuit for generating a reference current, by summing a constant current proportional to a thermal voltage and a current proportional to a diode voltage. 
     However, in order to adjust a mismatch error in specific accuracy of resistor R2 and resistor R1 due to manufacture thereof (resistance of an output resistor 170/R1*[Vbe+R1/R2*kT/q*LN(n)]), the resistance of resistor R2 in FIG. 1 of U.S. Pat. No. 6,501,256 is varied by selectively switching on or off MOS switches 312 through 328 that are connected in series to parallel unit resistors of the resistor R2, as shown in FIG. 3. It should also be understood that here Vbe is a terminal voltage of diode D2, R1 is resistor 122, R2 is resistor 124, k is Boltzmann&#39;s constant, T is absolute temperature, q is units of electric charge, and n is diode capacitance ratio. The on-resistance of the MOS switches has a temperature dependency, which is different from the temperature dependency of resistors r, 2r, . . . , 16r shown in FIG. 3. This has an effect on the constant reference voltage (the resistance of the output resistor 170/R1*[Vbe+R1/R2*kT/q*LN(n)]). It is accordingly difficult to generate a constant reference voltage having no temperature dependency. If the on-resistances of the MOS switches are designed to be greatly smaller than the parallel unit resistances of the resistor R2 in order to avoid this difficulty, a problem arises in that a layout area of the MOS switches becomes very large. 
     SUMMARY OF THE INVENTION 
     To overcome this problem, it is an object of the invention to provide a reference current generating apparatus which is capable of generating a reference current having no temperature dependency, without increasing layout area. 
     To achieve the above object, according to the present invention, there is provided a reference current generating apparatus for generating a reference current, including 
     a first constant current generator including a first current source transistor and a first diode connected to each other at a first connection node, a second current source transistor and a first resistor connected to each other at a second connection node, a second diode and the first resistor connected to each other at a third connection node, the second diode having a current capacity larger than a current capacity of the first diode, the first connection node and the second connection node respectively connected to inputs of a first differential amplifier that maintains the first and second connection nodes at an identical electric potential, gates of the first and second current source transistors connected to an output of the first differential amplifier, a transistor connected to the output of the first differential amplifier and that turns on the first and second current source transistors at a time when a power supply is turned on, and a third current source transistor connected to a second transistor by a fourth connection node and that biases the first differential amplifier via the fourth connection node; 
     a second constant current generator including a second differential amplifier having inputs, the third connection node connected to one of the inputs of the second differential amplifier, a fourth current source transistor and a second resistor connected to each other at a fifth connection node, the second resistor having a plurality of voltage dividing resistors connected in series to each other by dividing nodes, a voltage of a selected one of the dividing nodes of the second resistor being applied to another of the inputs of the second differential amplifier, gates of the fourth current source transistor and a fifth current source transistor are connected to an output of the second differential amplifier, a third transistor connected to the output of the second differential amplifier that turns on the fourth current source rasistor, the second transistor and a plurality of transistors forming a first current mirror connected to the fifth connection node via respective selected ones of the plurality of transistors to turn on the fourth current source transistor at the time when the power supply is turned on, and the fifth current source transistor connected to a fourth transistor by a sixth connection node and that biases the second differential amplifier via the sixth; and 
     an output circuit including a sixth current source transistor connected to the output of the second differential amplifier, a seventh connection node between the sixth current source transistor and a third resistor providing a first reference output, and the fourth transistor and a fifth transistor connected to each other and forming a second current mirror, and an eighth connection node between the fifth transistor and a fourth resistor providing a second reference output. 
     According to the present invention, there is provided a reference current generating apparatus in which a differential amplifier is used for summing a constant current proportional to a thermal voltage and a constant current proportional to a diode voltage, thereby generating a reference current. This reference current generating apparatus includes circuitry for adjusting a non-uniformity of the reference current, which might occur due to a mismatch error in specific accuracy of resistances, in view of the manufacture thereof. The circuitry enables selection of a mirror ratio of a MOS transistor configured to conduct summing of the constant current proportional to the thermal voltage, and also enables a voltage node, which is divided when a dividing voltage is applied to a high impedance MOS gate, to be selectively switched to an input of the differential amplifier that generates a constant current proportional to the diode voltage. 
     With this configuration, it is possible to prevent temperature dependency of on-resistance of MOS switches from having an effect on a generated reference current in a configuration where resistance is varied by on/off selection of MOS switches inserted in series with resistors. In addition, although it has been necessary in a conventional configuration to increase a size of a MOS switch so that on-resistance of a MOS transistor switch can be extremely smaller than the resistance of a resistor connected in series to the MOS transistor, the configuration of this invention can prevent an increase in layout area. 
     In addition, when it is configured so that non-uniformity of a reference current is adjusted by selection of a dividing voltage of a resistor connected in series to a diode for a diode voltage input side of a differential amplifier that generates a constant current proportional to a diode voltage, it is possible to further enhance accuracy of adjustment. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other aspects and features of the present invention will become readily apparent from the detailed description that follows, with reference to the accompanying drawings, in which: 
         FIG. 1  is a circuit diagram showing an example configuration of a constant current generating circuit in a reference voltage generating circuit according to an embodiment; 
         FIG. 2  is a circuit diagram showing another example configuration of the constant current generating circuit; 
         FIG. 3  is a block diagram showing a reference voltage generating circuit to which the principle of the present invention is applied; and 
         FIG. 4  is a circuit diagram showing another example configuration of the constant current generating circuit. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention will now be described by way of preferred, but non-limiting embodiments of the invention. The referenced drawings are presented for illustrative purposes only, and are not intended to limit the scope of the invention. 
     Now, a reference current generating circuit according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.  FIG. 3  shows an entire configuration of a reference current generating circuit to which the principles of the present invention are applied. Reference current generating circuit  10  includes a constant current generating circuit  14 , a constant current generating circuit  18  connected to the constant current generating circuit  14 , and an output circuit  20  connected to the constant current generating circuit  18 . The internal configuration of the constant current generating circuit  14  is shown in  FIG. 2 , and the internal configuration of the constant current generating circuit  18  is shown in  FIG. 1 . 
     As shown in  FIG. 2 , in the constant current generating circuit  14 , a differential amplifier  2  is connected between power terminal Vcc and ground GND. An output of differential amplifier  12  is connected to gates of P-channel MOS type transistors MP 1  and MP 2 . Each of the transistors MP 1  and MP 2  is a current source transistor. In the constant current generating circuit  14 , transistor MP 1  and a diode D 1  are connected in series via a connection node Va, between power terminal Vcc and ground GND, thereby forming a first current path. Connection node Va in the first current path is connected to one input of differential amplifier  12 . 
     Transistor MP 2  and a resistor R 3  are connected in series via a connection node Vb, between power terminal Vcc and ground GND. Diodes D 2 , having current capacity which is n times (n is a natural number greater than 2) as high as the current capacity of diode D 1 , are connected to the other terminal of resistor R 3 . Transistor MP 2 , resistor R 3  and diodes D 2  thereby form a second current path. Connection node Vb in the second current path is connected to the other input of differential amplifier  12 . The connection node V 2   b  between the resistor R 3  and the diodes D 2  is also connected to the constant current generating circuit  18  ( FIG. 3 ) via a connection line  200 . In addition, a P-channel MOS type transistor MP 6  and an N-channel MOS type transistor MN 2  are connected in series via a connection node  202 , between power terminal Vcc and ground GND. Connection node  202  is connected to a gate of transistor MN 2  and differential amplifier  12 . A bias current is applied to differential amplifier  12  through connection node  202 . 
     Differential amplifier  12  generates a constant current in proportion to a thermal voltage, and also a constant current in proportion to a diode voltage. An output of differential amplifier  12  has a positive temperature characteristic. Differential amplifier  12  drives the gates of transistors MP 1 , MP 2  and MP 6  ( FIG. 2 ) to maintain the connection nodes Va and Vb at the same potential. 
     Referring to  FIG. 2  again, an N-channel MOS type transistor MN 13  is additionally connected to a connection node V 1  between transistors MP 6  and MP 1 . Transistor MN 13  forces current source transistors MP 1  and MP 2  to be turned on according to a signal PONRST applied externally from outside constant current generating circuit  14  at the time of input of power. 
     Next, as shown in  FIG. 1 , in the constant current generating circuit  18 , a P-channel MOS type transistor MP 21  and a resistor R 1  are connected in series via a connection node Vc 2 , between power terminal Vcc and ground GND, thereby forming a third current path. The transistor MP 21  is a current source transistor. In addition, a P-channel MOS type transistor MP 26  and an N-channel MOS type transistor MN 22  are connected in series between power terminal Vcc and ground GND. A differential amplifier  16  has one differential input connected to connection line  200  (connection node V 2   b ) of constant current generating circuit  14  shown in  FIG. 2 , and drives current source transistors MP 21  and MP 26  to maintain the connection node V 2   b  and a connection node V 2   a  at the same potential. 
     The resistor R 1  in  FIG. 1  is connected between the transistor MP 21  and ground GND. The resistor R 1  includes a plurality of voltage dividing resistors R 1 - 0  to R 1 - 2  whose connection nodes Vc 0 , Vc 1  and Vc 2  are respectively connected to N-channel MOS type transistors MNtc 0 , MNtc 1  and MNtc 2 . The transistors MNtc 0  to MNtc 2  each serve to select one of the connection nodes Vc 0  to Vc 2  according to signals Trmc 0  to Trmc 2 , and to apply a voltage of the selected connection node to the connection node V 2   a  remaining at a high impedance state. The connection node V 2   a  is connected to the differential amplifier  16 . The resistor R 1  and the transistors MNtc 0  to MNtc 2  form a trimming circuit that adjusts a negative temperature coefficient in the diodes D 1  and D 2 . 
     The constant current generating circuit  18  in  FIG. 1  also includes a plurality of N-channel MOS type transistors MN 2   b   0 , MN 2   b   1  and MN 2   b   2  which are connected to the transistor MN 2  ( FIG. 2 ) via connection line  202 , and which form a current mirror. N-channel MOS type select transistors MNtb 0 , MNtb 1  and MNtb 2  are respectively connected between these transistors MN 2   b   0  to MN 2   b   1  and the connection node Vc 2 . In addition, a gate of transistor MP 21  is connected to differential amplifier  16  via a connection node V 21 . The differential amplifier  16  drives current source transistors MP 21  and MP 26  to maintain the connection node V 2   b  and connection node V 2   a  in the second current path at the same potential. An N-channel MOS type transistor MN 23  is additionally connected to connection node V 21  in  FIG. 1 , and transistor MN 23  forces current transistor MP 21  to be turned on by the signal PONRST applied externally from outside constant current generating circuit  18  at the time of input of power. 
     The connection node V 21  in  FIG. 1  is connected to a P-channel MOS type transistor MP 30  in output circuit  20  shown in  FIG. 3 . In output circuit  20 , current source transistor MP 30  and resistor R 4  are connected in series between power terminal Vcc and ground GND, thereby forming a fourth current path with a connection node between current source transistor MP 30  and resistor R 4  as output terminal Vref 1 . A reference voltage Vref 1  from ground GND is output from output terminal Vref 1 . 
     In addition, resistor R 5  and current source N-channel MOS type transistor MN 30  are connected in  FIG. 3  in series between power terminal Vcc and ground GND, and a gate of current source transistor MN 30  is connected to transistor MN 22  in constant current generating circuit  18  via a connection line  102 , thereby forming a current mirror. In addition, a connection node between resistor R 5  and current source transistor MN 30  is an output terminal Vref 2 , whereby transistor MN 30  and resistor R 5  form a fifth current path. A reference voltage Vref 2  from power terminal Vcc is output from output terminal Vref 2 . 
     In view of the above described configuration, operation of reference current generating circuit  10  will now be described. First, assuming that transistors MP 1 , MP 2  and MP 6  of constant current generating circuit  14  in  FIG. 2  have the same transistor size (W (gate width)/L (gate length)), the same current Ids as noted below flows into respective transistors MP 1 , MP 2  and MP 6 :
 
 Ids= 1 /R 3*[ kT/q*LN ( n )]  (1)
 
wherein, k is Boltzmann&#39;s constant, T is absolute temperature, q is units of electric charge, and n is diode capacitance ratio (aspect ratio). The current Ids depends on a thermal voltage and has a positive temperature coefficient proportional to the absolute temperature. In addition, as the same current Ids as the current Ids flowing into transistor MP 6  flows into transistor MN 2 , the above equation (1) may be established.
 
     Assuming that transistor MP 21  and transistor MP 26  of constant current generating circuit  18  in  FIG. 1  have the same transistor size (W/L), the same current Ids flows into respective MOS transistors MP 21  and MP 26 . Here, when a select signal is input to one of input terminals Trmb 0  to Trmb 2 , a current IdsMP 21  flowing into transistor MP 21  amounts to the sum of a current Ir 1  flowing through resistor R 1  and a current IdsMN 2   b  which is a combination of currents flowing into transistors MN 2   b   0  to MN 2   b   2  selected by input terminals Trmb 0  to Trmb 2 , as shown in equation (2):
 
 IdsMP 21= IdsMP 26= Ir 1+ IdsMN 2 b    (2).
 
     For example, when a high (H) level signal is applied to a selected one of the input terminals Trmc 0  to Trmc 2  in  FIG. 1 , and a low (L) level signal is applied to the remaining input terminals, one of the transistors MNtc 0  to MNtc 2  is selected and is turned on, and a voltage of the connection node V 2   a  becomes a voltage of the connection nodes Vc 0 , Vc 1  and Vc 2  of voltage dividing serial resistors R 1 - 0  to R 1 - 2  in resistor R 1 . 
     The voltage of connection node V 2   a  in  FIG. 1  becomes equal to input  200  of differential amplifier  16 . That is, connection node V 2   a  becomes equal to voltage V 2   b  of diodes D 2  in  FIG. 2 , according to a negative feedback operation through differential amplifier  16 , transistor MP 21  and resistor R 1 . Accordingly, the current Ir 1  flowing through resistor R 1  becomes Ir 1 =Vbe/(R 1 - 0 ) when input terminal Trmc 0  goes to a high level and input terminals Trmc 1  and Trmc 2  go to a low level. Likewise, the current Ir 1  flowing through resistor R 1  becomes Ir 1 =Vbe/(R 1 - 0 +R 1 - 1 ) when input terminal Trmc 1  goes to a high level and input terminals Trmc 0  and Trmc 2  go to a low level. Furthermore, the current Ir 1  becomes Ir 1 =Vbe/(R 1 - 0 +R 1 - 1 +R 1 - 2 ) when input terminal Trmc 2  goes to a high level and input terminals Trmc 0  and Trmc 1  go to a low level. Accordingly, the current Ir 1  can be expressed as follows:
 
 Ir 1=α* Vbe/R 1   (3),
 
wherein α is determined by selection via input terminals Trmc 0  to Trmc 2  and a division ratio of voltage dividing resistors R 1 - 0  to R 1 - 2  in resistor R 1 .
 
     As transistor MN 2  and transistors MN 2   b   0  to MN 2   b   2  in  FIGS. 1 and 2  form a current mirror, the sum IdsMN 2   b  of currents flowing into transistors MN 2   b   0  to MN 2   b   2  selected by input terminals Trmb 0  to Trmb 2  can be expressed as follows:
 
 IdsMN 2 b =β*(1/ R 3*[ kT/q*LN ( n )])   (4),
 
wherein β is determined by selection via input terminals Trmb 0  to Trmb 2  and a mirror ratio of transistors MN 2  and MN 2   b   0  to MN 2   b   2 .
 
     From the above equations (2), (3) and (4), the current IdsMP 26  flowing into transistor MP 26  can be expressed as shown in equation (5), and a reference current proportional to 1/R 1  of a band gap voltage (Vbe+R 1 /R 3 *kT/q*LN(n)) having no temperature dependency can be generated:
 
IdsMP26=α* Vbe/R 1+β*(1/ R 3*[ kT/q*LN ( n )])=1 /R 1 *{α*Vbe+β *( R 1 /R 3*[ kT/q*LN ( n )])}  (5).
 
     From the above equation (5), the voltage Vref 1  appearing at the output terminal Vref 1  of the output circuit  20  in  FIG. 3  can be expressed as follows:
 
 Vref 1= R 4* IdsMP 26= R 4/ R 1*{α* Vbe+ β*( R 1 /R 3*  [kT/q*LN ( n )])}  (6).
 
Accordingly, it is possible to generate at output terminal Vref 1  a constant reference voltage which is R 4 /R 1  times as high as the band gap voltage and which has no temperature dependency.
 
     In the mean time, assuming that the mirror ratio of transistor MN 22  and transistor MN 30  is one, from the above equation (5), the voltage Vref 2  appearing at output terminal Vref 2  can be expressed as follows:
 
 Vref 2= Vcc−R 5* IdsMP 26= Vcc−R 5/ R 1*{α* Vbe+ β*( R 1 /R 3*[ kT/q*LN ( n )])}  (7).
 
Accordingly, it is possible to generate at output terminal Vref 2  a constant reference voltage which is R 5 /R 1  times as high as the band gap voltage from power voltage Vcc and which has no temperature dependency.
 
     Next, a reference current generating circuit according to another embodiment will be described. This embodiment has the same configuration as the above-described first embodiment shown in  FIG. 3 , except that constant current generating circuit  14  of the first embodiment shown in detail in  FIG. 2 , is replaced by contact current generating circuit  400  shown in  FIG. 4 . Explanation of this second embodiment will thus focus on constant current generating circuit  400  shown in  FIG. 4 , and redundant explanation of the remaining aspects of reference current generating circuit  10  will be omitted for the sake of brevity. In this embodiment, the same components as in the first embodiment are denoted by the same reference numerals. 
     As shown in  FIG. 4 , in constant current generating circuit  400  according to this embodiment, a resistor R 3  in the second current path includes a plurality of voltage dividing resistors R 3 - 1  and R 3 - 2  connected in series. Transistors MNta 0 , MNta 1  and MNta 2  are connected between connection nodes Vb 0 , Vb 1  and Vb 2  of voltage dividing resistors R 3 - 1  and R 3 - 2  and input node V 2   b  of differential amplifier  16  in constant current generating circuit  18  shown in  FIG. 1 . Transistors MNta 0 , MNta 1  and MNta 2  select one of connection nodes Vb 0  to Vb 2 , transmitting a voltage of the selected connection node to connection node V 2   b . Signals Trma 0 , Trma 1  and Trma 2  for selecting a connection node are input to respective gates of transistors MNta 0 , MNta 1  and MNta 2 , and connection node V 2   b  is connected to one input of differential amplifier  16  via connection line  200 . 
     An operation of reference current generating circuit having constant current generating circuit  400  as shown in  FIG. 4  will now be described. Assuming that transistors MP 1 , MP 2  and MP 6  of constant current generating circuit  400  have the same transistor size (W (gate width)/L (gate length)), the same current Ids flows into respective transistors MP 1 , MP 2  and MP 6 :
 
 Ids= 1/ R 3*[ kT/q*LN ( n )]  (8).
 
As the same current Ids as the current Ids flowing into transistor MP 6  flows into transistor MN 2 , the above equation (8) may be established.
 
     Assuming that transistor MP 21  and transistor MP 26  in constant current generating circuit  18  shown in  FIG. 1  have the same transistor size (W/L), the same current Ids flows into respective transistors MP 21  and MP 26 . In addition, since the current Ids of the transistor MP 21  amounts to the sum of a current Ir 1  flowing through resistor R 1  and a current IdsMN 2   b , which is a combination of currents flowing into transistors MN 2   b   0  to MN 2   b   2  selected via the input nodes Trmb 0  to Trmb 2 , the current IdsMP 21  of transistor MP 21  is expressed as follows:
 
 IdsMP 21= IdsMP 26= Ir 1+ IdsMN 2 b    (9).
 
     Here, when a high (H) level signal is applied to a selected one of input nodes Trma 0  to Trma 2 , and a low (L) level signal is applied to the remaining input nodes, one of transistors MNta 0  to MNta 2  is selected and is turned on, and a voltage of the connection node V 2   b  becomes a voltage of the connection nodes Vb 0 , Vb 1  and Vb 2  of voltage dividing resistors R 3 - 1  and R 3 - 2  in resistor R 3 . From the above equation (8), connection nodes Vb 0 , Vb 1  and Vb 2  have respective voltages as follows:
 
Vb 0 =Vbe
 
 Vb 1= Vbe+R 3−2/ R 3*[ kT/q*LN ( n )]
 
 Vb 2= Vbe +( R 3−1+ R 3−2)/ R 3*[ kT/q*LN ( n )]= Vbe+[kT/q*LN ( n )].
 
Accordingly, the voltage of connection node V 2   b  is as follows: Vb 2 =Vbe when input node Trma 0  goes to a high level and input nodes Trma 1  and Trma 2  go to a low level, Vb 2 =Vbe+R 3 − 2 /R 3 *[kT/q*LN(n)] when input node Trma 1  goes to a high level and input nodes Trma 0  and Trma 2  go to a low level, and Vb 2 =Vbe+[kT/q*LN(n)] when the input node Trma 2  goes to a high level and input nodes Trma 0  and Trma 1  go to a low level.
 
     Accordingly, the voltage V 2   b  of connection node V 2   b  can be expressed as follows:
 
 Vb 2= Vbe+γ*[kT/q*LN ( n )]  (10),
 
wherein γ is 0 to 1 and is determined by selection of input nodes Trma 0  to Trma 2  and a division ratio of voltage dividing resistors R 3 - 1  and R 3 - 2  in resistor R 3 .
 
     Similarly, when a high level signal is applied to a selected one of the input nodes Trmc 0  to Trmc 2  of constant current generating circuit  18  and a low level signal is applied to the remaining input nodes, one of transistors MNtc 0  to MNtc 2  is selected and is turned on, and a voltage of connection node V 2   a  becomes a voltage of connection nodes Vc 0 , Vc 1  and Vc 2  of voltage dividing resistors R 1 - 0  to R 1 - 2  in resistor R 1 . 
     The voltage of connection node V 2   a  becomes equal to input  200  of differential amplifier  16 , that is the voltage V 2   b  of node V 2   b , according to a negative feedback operation through differential amplifier  16 , transistor MP 21  and resistor R 1 . Accordingly, the current Ir 1  flowing through resistor R 1  becomes Ir 1 =(Vbe+γ*[kT/q*LN(n)])/(R 1 - 0 ) when input terminal Trmc 0  goes to a high level and input terminals Trmc 1  and Trmc 2  go to a low level, becomes Ir 1 =(Vbe+γ*[kT/q*LN(n)])/(R 1 - 0 +R 1 - 1 ) when input terminal Trmc 1  goes to a high level and input terminals Trmc 0  and Trmc 2  go to a low level, and becomes Ir 1 =(Vbe+γ*[kT/q*LN(n)])/(R 1 - 0 +R 1 - 1 +R 1 - 2 ) when input terminal Trmc 2  goes to a high level and input terminals Trmc 0  and Trmc 1  go to a low level. 
     Accordingly, the current Ir 1  can be expressed as follows:
 
 Ir 1=α*( Vbe+γ*[kT/q*LN ( n )])/ R 1   (11),
 
wherein α is determined by selection via the input terminals Trmc 0  to Trmc 2  and a division ratio of voltage dividing resistors R 1 - 0  to R 1 - 2  in resistor R 1 .
 
     In addition, as transistor MN 2  and transistors MN 2   b   0  to MN 2   b   2  ( FIG. 1 ) form the current mirror, the sum IdsMN 2   b  of currents flowing into transistors MN 2   b   0  to MN 2   b   2  selected by the input nodes Trmb 0  to Trmb 2  can be expressed as follows:
 
 IdsMN 2 b =β*(1/ R 3*[ kT/q*LN ( n )])   (12),
 
wherein β is determined by selection via input terminals Trmb 0  to Trmb 2  and a mirror ratio of transistors MN 2  and transistors MN 2   b   0  to MN 2   b   2 .
 
     From the above equations (9), (11) and (12), the current IdsMP 26  can be expressed as follows in equation (13), and a reference current proportional to 1/R 1  of a band gap voltage (Vbe+R 1 /R 3 *kT/q*LN(n)) having no temperature dependency can be generated:
 
 IdsMP 26=α*( Vbe+γ*[kT/q*LN ( n )])/ R 1+β*(1/ R 3*[ kT/q*LN ( n )])=1/ R 1 *{α*Vbe+ (β* R 1/ R 3+γ*α)*[ kT/q*LN ( n )]}  (13).
 
     From the above equation (13), the voltage Vref 1  appearing at output terminal Vref 1  can be expressed as follows:
 
 Vref 1= R 4* IdsMP 26= R 4/ R 1*{α* Vbe +(β* R 1/ R 3+γ*α)*[ kT/q*LN ( n )[}  (14).
 
That is, it is possible to generate at the output terminal Vref 1  a constant reference voltage which is R 4 /R 1  times as high as the band gap voltage and that has no temperature dependency.
 
     In the mean time, assuming that the mirror ratio of transistor MN 22  and transistor MN 30  is one, from the above equation (13), the voltage Vref 2  appearing at output terminal Vref 2  can be expressed as follows:
 
 Vref 2= Vcc−R 5* IdsMP 26= Vcc−R 5/ R 1*{α* Vbe +(β* R 1 /R 3+γ*α)*[ kT/q*LN ( n )]}  (15).
 
That is, it is possible to generate at the output terminal Vref 2  a constant reference voltage which is R 5 /R 1  times as high as the band gap voltage from the power voltage Vcc and that has no temperature dependency.
 
     As described above, according to the second embodiment, since it is configured that dividing voltage nodes are selected by voltage dividing resistors connected in series to diodes at an diode voltage input side of a differential amplifier that generates a constant current proportional to a diode voltage in order to adjust non-uniformity or dispersion of a reference current, it is possible to further raise precision of adjustment, in addition to the effect of the first embodiment.