Abstract:
A circuit is provided and includes current sources, switches, a control module, and capacitances. The current sources adjust current flowing through a load. Each of the switches activates a respective one of the current sources. Kick-back voltages are generated at inputs of the current sources in response to the current sources being turned ON. A control module generates control signals to change states of the switches to alternate a direction in which the current flows through the load. A first capacitance is connected between a first pair of the current sources and a second pair of the current sources. A second capacitance is connected between the first pair of the current sources and a reference terminal. A third capacitance connected between the second pair of the current sources and the reference terminal. The first capacitance, the second capacitance, and the third capacitance reduce magnitudes of the kick-back voltages.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 12/778,248 (now U.S. Pat. No. 8,354,875) which claims the benefit of U.S. Provisional Application No. 61/178,696, filed on May 15, 2009. The disclosures of the above applications are incorporated herein by reference in their entirety. 
    
    
     FIELD 
     The present disclosure relates to Class B type circuits, and more particularly to biasing and control of Class B type circuits. 
     BACKGROUND 
     The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure. 
     Circuits may be classified as type A and B. The classification of the circuit is based in part on a portion of the input signal cycle during which the circuit conducts. 
     In Class A type circuits, 100% of the input signal is used. Where efficiency is not a consideration, most small signal linear amplifiers are designed as Class A type circuits. While Class A type circuits are typically more linear and less complex than other circuit types, they are relatively inefficient. 
     Class B type circuits use 50% of the input signal. In most Class B type circuits, there are two output devices that conduct alternately during half cycles. Some distortion may occur in Class B type circuits. While distortion is usually worse at higher frequencies, distortion may also occur at lower frequencies due to kickback. 
     Referring now to  FIG. 1 , an exemplary Class B type circuit  10  is shown. The circuit  10  includes controllable current sources  12 ,  14 ,  16  and  18 . During one half cycle, the current sources  12  and  18  supply current in a first direction across a load  20 . During a second half cycle, the current sources  14  and  16  provide current across the load  20  in an opposite direction. 
     Class B type circuits such as current digital to analog converters (DACs) do not work in differential arrangements. As a result, a large kick-back is usually seen at a control terminal of current sources in Class B type circuits if there is not enough voltage headroom to use cascode devices, which can cause distortion. 
     SUMMARY 
     A circuit is provided and includes current sources, switches, a control module, and capacitances. The current sources are configured to adjust current flowing through a load. Each of the switches is configured to activate a respective one of the current sources. Kick-back voltages are generated at inputs of the current sources in response to the current sources being turned ON. A control module is configured to generate control signals to change states of the switches to alternate a direction in which the current flows through the load. A first capacitance is connected between (i) a first pair of the current sources and (ii) a second pair of the current sources. A second capacitance is connected between (i) the first pair of the current sources and (ii) a reference terminal. A third capacitance connected between (i) the second pair of the current sources and (ii) the reference terminal. The first capacitance, the second capacitance, and the third capacitance reduce magnitudes of the kick-back voltages. 
     In other features, a method is provided and includes adjusting current flowing through a load via current sources. Control signals are generated to change states of switches to alternate a direction in which a current flows through the load. Kick-back voltages are generated at inputs of the current sources in response to the current sources being turned ON. Each of the switches is configured to activate a respective one of the current sources. The method further includes alternating current coupling, via a first capacitance, a first pair of the current sources to a second pair of the current sources. The first capacitance is connected between (i) the first pair of the current sources and (ii) the second pair of the current sources. Current is directed, via a second capacitance, away from the first pair of the current sources and to a reference terminal. Current is directed, via a third capacitance, away from the second pair of the current sources and to the reference terminal. Magnitudes of the kick-back voltages are reduced via the first capacitance, the second capacitance, and the third capacitance. 
     A circuit includes a first current source, a second current source, a third current source and a fourth current source. A load includes a first terminal connected to a first node between the first current source and the second current source and a second terminal connected to a second node between the third current source and the fourth current source. A bias control module includes a first output configured to output a first bias signal to the first and fourth current sources and a second output configured to provide a second bias signal to the second and third current sources. A capacitance is connected to the first and second outputs of the bias control module. 
     In other features, the bias control module includes a first bias circuit and a second bias circuit. A first switch and the first current source are connected between a voltage supply and the first node. A second switch and the second current source are connected between the first node and a reference potential. A third switch and the third current source are connected between the voltage supply and the second node. A fourth switch and the fourth current source are connected between the second node and the reference potential. 
     A circuit includes a Class B type circuit including a first input, a second input, a first output and a second output. A bias control module includes a first output configured to output a first bias signal to the first input. A second output is configured to provide a second bias signal to the second input. A capacitance is connected to the first output and the second output of the bias control module. 
     In other features, a load is connected across the first output and the second output of the Class B type circuit. The bias control module includes a first bias circuit and a second bias circuit. 
     Further areas of applicability of the present disclosure will become apparent from the detailed description, the claims and the drawings. The detailed description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the disclosure. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       The present disclosure will become more fully understood from the detailed description and the accompanying drawings, wherein: 
         FIG. 1  is a functional block diagram and electrical schematic for a Class B type circuit according to the prior art; 
         FIG. 2  is a functional block diagram and electrical schematic of a Class B type circuit according to the present disclosure; 
         FIG. 3  is a functional block diagram and electrical schematic of another Class B type circuit according to the present disclosure; 
         FIG. 4  is a graph showing switch control signals and kickback signals; 
         FIG. 5  is a functional block diagram and electrical schematic of a portion of another Class B type circuit according to the present disclosure; and 
         FIG. 6  includes graphs illustrating current output. 
     
    
    
     DESCRIPTION 
     The following description is merely exemplary in nature and is in no way intended to limit the disclosure, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. As used herein, the phrase at least one of A, B, and C should be construed to mean a logical (A or B or C), using a non-exclusive logical OR. It should be understood that steps within a method may be executed in different order without altering the principles of the present disclosure. 
     As used herein, the term module may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality. 
     Referring now to  FIG. 2 , a Class B type circuit  100  according to the present disclosure is shown. The circuit  100  includes current sources  104 ,  106 ,  112  and  116 . The circuit  100  further includes switches  122 ,  126 ,  130  and  134  that switch the current sources  104 ,  106 ,  112  and  116 , respectively, on and off to alternate a direction of the current across a load  150 . 
     The circuit  100  includes a switching control module  140  that controls states of the switches  122 ,  126 ,  130  and  134 . A bias control module  142  generates control signals for biasing control terminals of transistors associated with the current sources  104 ,  106 ,  112  and  116 . 
     According to the present disclosure, AC coupling is provided between first and second outputs of the bias control module  142  to reduce kickback. More particularly, an AC coupling capacitor  146  is connected across first and second outputs of the bias control module  142 . 
     A load  150  has a first terminal connected to a first node  152  between the current sources  104 ,  106  and has a second terminal connected to a second node  154  between the current sources  112 ,  116 . The circuit  100  provides current across the load  150  in a first direction during a first-half cycle and in an opposite direction during a second-half cycle. 
     In more detail, the switch  122  and the current source  104  are connected between a voltage supply V DD  and the first node  152 . The current source  106  and the switch  126  are connected between the first node  152  and a reference potential V SS  such as ground. The switch  130  and the current source  112  are connected between the voltage supply V DD  and the second node  154 . The current source  116  and the switch  134  are connected between the second node  154  and the reference potential V SS . 
     In use, the current sources  104 ,  106 ,  112  and  116  are constantly biased during operation. The switches  122  and  134  are selectively turned on and off while the switches  126  and  130  are off and vice versa. In other words, current flows during one half cycle from the switch  122  and the current source  104  to the load  150  and to the current source  116  and the switch  134 . Subsequently during the next half cycle, current flows from the switch  130  and the current source  112  to the load  150  and to the current source  106  and the switch  126 . 
     In class-B type circuits, when the switches are turned on or off to generate current in one direction, the switches that control the supply of current in the opposite direction are always off. For example in  FIG. 2 , switches  122  and  134  are turned on and off to generate or stop current flow in first direction while switches  126  and  130  remain off. When switches  126  and  130  are active (turning on/off together), switches  122  and  134  remain off. 
     During operation, kickback at control terminals of the current sources  104 ,  106 ,  112  and  116  tends to occur. Kickback at the current source  104  is approximately opposite in magnitude to that experienced at the current source  116 . A similar situation exists for current sources  106  and  112  when the switches  126  and  130  transition from on to off, or from off to on. Placement of the AC coupling capacitor  146  across the control terminals of the current sources  104  and  116  and the control terminals of the current sources  106  and  112  tends to reduce distortion by canceling the kickback. 
     Referring now to  FIG. 3 , another Class B type circuit  200  according to the present disclosure is shown. The circuit  200  includes current sources  204 ,  208 ,  212  and  216 . The circuit  200  further includes switches  222 ,  226 ,  230  and  232 . While the switching control module is omitted in  FIG. 3 , the switching control module may be provided to control states of the switches  222 ,  226 ,  230  and  232 . 
     A bias control module  234  includes a first biasing circuit  235  and a second biasing circuit  243 . The first biasing circuit  235  generates control signals for biasing control terminals of transistors of the current sources  204  and  212 . The second biasing circuit  243  generates control signals for biasing control terminals of transistors of the current sources  208  and  216 . 
     The first biasing circuit  235  includes a first transistor  236 , a second transistor  238  and a current source  240 . A first terminal of the transistor  236  is connected to the voltage supply V DD . A second terminal of the transistor  236  is connected to a first terminal of the second transistor  238 . A second terminal of the transistor  238  is connected to a current source  240  and to a control terminal of the second transistor  238 . The control terminal of the second transistor  238  supplies a first bias signal to control terminals of transistors of the current sources  204  and  212 . 
     The second biasing circuit  243  includes a first transistor  252 , a second transistor  248  and a current source  244 . A second terminal of the first transistor  252  is connected to the reference potential V SS . A first terminal of the first transistor  252  is connected to a second terminal of the second transistor  248 . A first terminal of the second transistor  248  is connected to the current source  244  and to a control terminal of the second transistor  248 . The control terminal of the second transistor  248  supplies a second bias signal to control terminals of transistors of the current sources  208  and  216 . 
     AC coupling is provided between outputs of the bias control module  234  to reduce kickback according to the present disclosure. More particularly, AC coupling capacitor  260  is connected across first and second outputs of the bias control module  234 . A load  272  is connected to a first node  274  between the current sources  204  and  208  and to a second node  276  between the current sources  212  and  216 . The circuit  200  provides current across the load  272  in a first direction during a first-half cycle and in an opposite direction during a second-half cycle. 
     In more detail, the switch  222  and the current source  204  are connected between a voltage supply V DD  and the first node  274 . The current source  208  and the switch  226  are connected between the first node  274  and a reference potential V SS . The switch  230  and the current source  212  are connected between the voltage supply V DD  and the second node  276 . The current source  216  and the switch  232  are connected between the second node  276  and the reference potential V SS . 
     Parasitic capacitance C p  may be present at the control terminal of the second transistor  238  of the first biasing circuit  235 . Parasitic capacitance C n  may also be present at the control terminal of the second transistor  248  of the second biasing circuit  243 . 
     In use, the current sources  204 ,  208 ,  212  and  216  are constantly biased during operation. The switches  222  and  232  are selectively turned on and off while the switches  226  and  230  remain off and vice versa. In other words, current flows during one half cycle from the switch  222  and the current source  204  to the load  272  and to the current source  216  and the switch  232 . Subsequently during the next half cycle, current flows from the switch  230  and the current source  212  to the load  272  and to the current source  208  and the switch  226 . When creating a sinusoidal or other type of output in class-B type circuits, a first half cycle is generated by sequentially turning on/off the switches that control current in one direction while keeping the switches that control current in the opposite direction off. 
     As a result of the switches  222  and  226  and  230  and  232  being switched in the alternating pattern described above and below, kickback experienced at control terminals of the current sources  204  and  216  and  208  and  212  occurs, respectively. The kickback at the current source  204  is approximately opposite in magnitude to that experienced at the control terminals of the current source  216 . The kickback at the current source  208  is approximately opposite in magnitude to that experienced at the control terminals of the current source  212 . As a result, placement of the AC coupling capacitor  260  across the control terminals of the current sources  204  and  216  and the control terminals of the current sources  208  and  212  tends to improve distortion by canceling the kickback. 
     In some implementations, the transistors  204 ,  212 ,  222 ,  230 ,  236  and  238  are P-type metal oxide semiconductor field effect transistors (MOSFET). In some implementations, the transistors  208 ,  216 ,  226 ,  232 ,  248  and  252  are N-type MOSFET transistors. 
     In class-B type push-pull circuits such as DACs, kick-back at the P-type current source bias node (designated as P bias in  FIG. 3 ) is opposite to kick-back at N type current source bias node (designated as N bias  in  FIG. 3 ). The amplitude of kick-back at the P-type current sources is K p . The amplitude of kick-back at the N-type current sources is (−K n ), where K p  and K n &gt;O. Using an AC-coupling capacitor (C bias ), the kick-back at P-type current sources can be reduced to: 
                      K   p          -       (       C   bias         C   bias     +     C   p         )     *          K   n              ,         
where C p  is the parasitic capacitance from the gate of P-type current sources to the supply. The same is true for N-type current sources, where kick-back is reduced to:
 
                      K   n          -       (       C   bias         C   bias     +     C   n         )     *          K   p              ,         
where C n  is the parasitic capacitance from gates of N-type current sources to the ground.
 
     As can be appreciated, the present disclosure reduces kickback and distortion utilizing AC coupling. While it is anticipated that the AC coupling described herein may provide approximately 10 dB of improvement in distortion, other applications may experience more or less improvement. The load can be any type of impedance including resistors, capacitors, inductors and combinations thereof. 
     Referring now to  FIG. 4 , switch control signals and kickback signals are shown. When the switch control signals for the PMOS transistor  222  goes low and the NMOS transistor  232  goes high, there is kickback at the gate of the PMOS transistor  204  and the NMOS transistor  216 . When the switch control signals for the PMOS transistor  230  goes high and the NMOS transistor  226  goes low, there is kickback at the gate of the PMOS transistor  212  and the NMOS transistor  208 . 
     Referring now to  FIG. 5 , in some implementations the transistors may include multiple transistors. For example, the transistors  204  and  222  in  FIG. 3  may include transistors  204 - 1 ,  204 - 2 , . . . , and  204 -K and  222 - 1 ,  222 - 2 , . . . , and  222 -K, respectively. K is an integer greater than one. Likewise, the transistors  216  and  232  in  FIG. 3  may include transistors  216 - 1 ,  216 - 2 , . . . , and  216 -K and  232 - 1 ,  232 - 2 , . . . , and  232 -K, respectively. The transistors  208  and  226  and  212  and  230  may be implemented in an analogous manner. 
     Referring now to  FIG. 6 , graphs illustrating current output to generate a sinusoidal waveform are shown. In this example implementation, K=5. The current sources ( 204 ,  208 ,  212  and  216 ) are biased on. The switches  226  and  230  are off during Phase 1 and Phase 3. The switches  222  and  232  are off during Phase 2 and 4. 
     During Phase 1, switches  222 - 1 ,  222 - 2 , . . . ,  222 - 5  and  232 - 1 ,  232 - 2 , . . . , and  232 - 5  are sequentially turned on and then sequentially turned off. For example, the switches can be turned off in reverse order although other approaches may be used in a particular application. This approach generates a stepped current waveform (having a sinusoidal shape) in a first direction during Phases 1 and 3 as shown. The other switches  230  and  226  are operated in a similar manner during Phases 2 and 4 to generate a stepped current waveform (having a sinusoidal shape) in a second direction. 
     As can be appreciated, the output sees a generally sinusoidal output as shown. Other output waveforms may be generated, different timing may be used and/or additional or fewer transistors can be used in other implementations. 
     The broad teachings of the disclosure can be implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since other modifications will become apparent upon a study of the drawings, the specification, and the following claims.