Abstract:
An automatic interface identification technique for an apparatus capable of supporting both USB and PS/2 interfaces comprises connecting a detector to first and second ports provided for the apparatus connected to a host computer through a USB or PS/2 interface. The detector has an interface detect function including a logic confirming mechanism and an interface identifying algorithm and a mode select function receiving first and second control signals such that the logic confirming mechanism is connected to the first and second ports by the interface detect function to detect the logic states of the first and second ports in association with the interface identifying algorithm to thereby correctly identify a USB or PS/2 interface is connected and to further determine USB or PS/2 mechanism in response to signal transmissions.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates generally to a communication interface, and more particularly to an apparatus and method for automatically identifying between USB and PS/2 interface. 
   2. Related Art 
   USB is a standard interface for the connections or communications between computer systems and their peripherals. Although currently more and more peripherals support USB interfaces, those with low transmission rate, such as keyboard and mouse, will be more accepted in the market if they can support conventional PS/2 interfaces as well. 
     FIG. 1  is a system block diagram to show a host computer  10  connected to a peripheral  12 , such as microcontroller unit (MCU), that supports USB and PS/2 transmission function and includes a mechanism  14  capable of handling USB transmission specification and a mechanism  16  capable of handling PS/2 transmission specification both connected to the host computer  10  but exclusive to each other at same time through first and second ports  18  and  20 . The first port  18  is provided for the transmission of the signal D+ of USB interface or the clock of PS/2 interface, and the second port  20  is for the transmission of the signal D− of USB interface or data signal of PS/2 interface. The USB mechanism  14  needs a USB transceiver  22  to be connected to the first and second ports  18  and  20  with connection of the receiver signal RxD+ port  24  and RxD− port  26  and the transmitter signal TxD+ port  28  and TxD− port  30  to and from the USB mechanism  14 , and the PS/2 mechanism  16  is directly connected to the first and the second ports  18  and  20  with its clock port  32  and data port  34 . 
   To ensure the peripheral  12  to communicate with the host computer  10  with the same transmission interface specification, the USB or PS/2 interface must be identified according to the logic states of the first and second ports  18  and  20  when it is initially connected to the host computer, and then the USB or PS/2 transmission mechanisms  14  or  16  is responsible to interactive to the host computer  10 . 
   USB interface standard covers low-speed device and high-speed device.  FIG. 2  shows the connection of a USB low-speed device  38  to a host computer  36  through a cable  40  on their respective D+ ports  42  and  46  and D− ports  44  and  48 . At the side of the host computer  36 , there are two 15 KΩ pull-down resistors Rpd connected from the D+ signal port  42  and D− signal port  44  to ground, and at the side of the low-speed device  38  a 1.5 KΩ pull-up resistor Rpu connected between supply voltage 3.3 V and the D− signal port  48 . On the other hand, the only difference between USB full-speed device and the above-mentioned low-speed device is that the pull-up resistor Rpu is connected to the D+ signal port for full-speed device. 
   Conventionally, the identification of USB and PS/2 interface utilizes the characteristics of the direct connection of the pull-down resistor Rpd on the USB port of the host computer. Referring to FIG.  1  and  FIG. 2  at same time, in accordance with USB interface standard, when the peripheral  12  is connected to the host computer  10 , initially the pull-up resistor Rpu will not be connected onto the port, as a result, if the first and second ports  18  and  20  are both logic “0” at this time, it is determined a USB interface is connected thereto, otherwise, it is a PS/2 interface. The drawback of this method is that the PS/2 port at the side of the host computer  10  may be floating or in high impedance, which will result in uncertain level of the D+ and D− ports  18  and  20  when the peripheral  12  is connected thereto and, as a result, the misjudgment of the interface type. 
   Therefore, it is desired an apparatus and method to correctly and automatically identify between USB and PS/2 interface. 
   SUMMARY OF THE INVENTION 
   One object of the present invention is to provide an apparatus and method for automatically identifying between USB and PS/2 interface, by which a detector is connected to a first and second ports that are provided to be connected to a host computer through USB or PS/2 interface. The detector includes two functions, mode selection and interface detection. The interface detection includes a logic confirming mechanism and an interface identifying algorithm. The mode selection includes receiving a first and second control signals for the selection of USB or PS/2 mode, such that the logic confirming mechanism is correctly configured for the first and second ports. By detecting the logic states of the first and second ports by the interface detection and in association with the interface identifying algorithm, it can be correctly identified which interface between USB and PS/2 is connected thereto, and thereby to determine to support the signal transmission in USB or PS/2 mode. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects, features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings, in which: 
       FIG. 1  is a system block diagram to illustrate a host computer connected to a peripheral that supports USB and PS/2; 
       FIG. 2  shows the connection of a USB low-speed device with a host computer; 
       FIG. 3  is the composition of a USB transceiver; 
       FIG. 4  is an embodiment mode operation device; 
       FIG. 5  is the logic table of the circuit shown in  FIG. 4 ; 
       FIG. 6  is a basic flow chart of USB and PS/2 identification; and 
       FIG. 7  is another embodiment circuit for the mode operation device. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The system block diagram according to the present invention is the same as that shown in  FIG. 1 , and the specification as shown in  FIG. 2  shall be also followed in case of applications on USB low-speed devices. However, one embodiment arrangement in a USB transceiver of the present invention is shown in  FIG. 3 , which includes a mode operation device  50  to receive two control signals M USB  and M PS/2  and its two ports  52  and  54  are connected to D+ or PS/2 Clk port  18  and D− or PS/2 Data port  20 , respectively. As in the prior art schemes, the transceiver also includes a differential receiver  56 , single-input receivers  58  and  60 , and USB output buffers  62  and  64  to receive and transmit USB signals. The mode operation device  50  includes a detector to detect the logic states of the ports  18  and  20  to further identify USB or PS/2 interface. 
     FIG. 4  is an embodiment circuit of the mode operation device  50  that includes a mode selector  68 , a mode detector  70 , a PS/2 mode device  72 , and a USB mode device  74 , by which the mode selector  68  produces three mode signals SW 0 , SW 1  and SW 2  according to the control signals M USB  and M PS/2  on its inputs, and the mode detector  70  includes switches  76  and  78  under the control of the detect mode signal SW 0  to connect resistors  80  and  82  to supply voltage 5V, respectively. In this embodiment, the resistors  80  and  82  are both 200 KΩ for the function of logic confirmation. The PS/2 mode device  72  includes switches  84  and  86  under the control of the PS/2 mode signal SW 1  to connect pull-up resistors  88  and  90  to supply voltage 5V, and the pull-up resistors  88  and  90  for the PS/2 interface are both about 4.7 KΩ. The USB mode device  74  includes a switch  92  under the control of the USB mode signal SW 2  to connect a pull-up resistor  94  to supply voltage 3.3V, and the pull-up resistor  94  for the USB interface is about 1.5 KΩ. The logic table of this circuit is shown in FIG.  5 . 
   In detect mode, the control signals M USB  and M PS/2  are both set to logic “0” and the detect mode signal SW 0  at the moment is at high state and the others SW 1  and SW 2  are at low state. In PS/2 mode, the control signal M USB  is logic “0” and the control signal M PS/2  is logic “1”, and at this moment the PS/2 mode signal SW 1  is at high state and the others SW 1  and SW 2  are at low state. In USB mode, the control signal M USB  is logic “1” and the control signal M PS/2  is logic “0”, and at the moment the USB mode signal SW 2  is at high state and the others SW 0  and SW 1  are at low state. The mode signals SW 0 , SW 1  and SW 2  at high state mean that the corresponding switches they control are turned on. 
   In this embodiment circuit, independent resistors  80 ,  82 ,  88 ,  90 , and  94  are used for the pull-up resistors of the various mode devices  70 ,  72  and  74 , while in other embodiment circuits, a resistor network may be used and is configured by a control circuit to obtain the required equivalent resistance under different modes. 
   Application of the circuit shown in  FIG. 4  to the system of  FIG. 1  has an embodiment process shown in FIG.  6 . After power supply is turned on or the system is reset in step S 10 , initialization in step S 12  sets up in detect mode and the D+/D− input, then it enters into detect status S 14 . In step S 16  the logic state of D+/Clk port  18  is detected, and it goes to step S 18  if low state is detected, otherwise to step S 20  if high state is detected. In step S 18  the logic state of D−/Data port  20  is detected, and it jumps back to step S 16  if high state is detected, otherwise it goes to USB recheck status S 22  if low state is detected. In step  20  the logic state of D−/Data port  20  is detected, and it jumps back to step S 16  if low state is detected, otherwise it goes to PS/2 recheck status S 24  if high state is detected. In USB recheck status S 22 , a short time delay is introduced in step S 26 , and the logic state of D+/Clk port  18  is detected again in step S 28  to jump back to step S 16  if high state is detected and to step S 30  if low state is detected. If high state is detected on the D−/Data port  20  in step  30 , it will jump back to step S 16 , otherwise it goes to step S 32  if low state is detected, and USB mode is set up in step  32 . In PS/2 recheck status S 24 , a short time delay is introduced in step S 34 , and then the logic state of D+/Clk port  18  is detected in step S 36  to jump back to step S 16  if low state is detected, otherwise to go to step S 38  if high state is detected. Then the logic state of D−/Data port  20  is detected again in step  38 , and it jumps back to step S 16  if low state is detected, otherwise to step S 40  if high state is detected to set up PS/2 mode. 
   The operational principle of the circuit shown in  FIG. 4  is now further described. When the peripheral  12  is connected to the computer interface at beginning, the peripheral  12  sets up the control signals M USB  and M PS/2  to logic “0”, i.e., under detect mode, in this manner 200 KΩ pull-up resistors  80  and  82  are connected to the D+ and D− ports  52  and  54 . In case D+ and D− ports  52  and  54  are detected at high states, i.e., logic “1”, the interface is identified as PS/2 and the peripheral  12  set up the control signals M USB  and M PS/2  to logic “0” and “1”, respectively, i.e., into PS/2 mode, and 4.7 KΩ pull-up resistors  88  and  90  are connected to the D+ and D− ports  52  and  54 , respectively. In contrast, if the D+ and D− ports  52  and  54  are detected at low states, i.e., logic “0”, the interface is identified as USB, and then the peripheral  12  sets up the control signals M USB  and M PS/2  to logic “1” and “0”, i.e., into USB mode, and 1.5 KΩ pull-up resistor  94  is connected to the D− port  54  for USB low-speed device. 
   Although the mode detector  70  of  FIG. 4  uses resistors  80  and  82  to connect to the ports  52  and  54 , other devices able to offer logic confirmation are also applicable.  FIG. 7  is another embodiment circuit for the mode operation device  50 , in which small current sources  96  and  98  are used to replace the resistors  80  and  82 . In detect mode, if USB interface is at the side of the host computer  10 , the current will flow from the current sources  96  and  98  to the pull-down resistor Rpd on the ports  42  and  44  of the host computer  10 , and thereby the ports  52  and  54  are detected at logic “0”. On the contrary, if PS/2 interface is at the side of the host computer  10 , no current will flow from the current sources  96  and  98  to the ports  42  and  44  of the host computer  10 , and, as a result, the ports  52  and  54  will be detected at logic “1”. In other words, logic confirmation can be made by use of the resistors  80  and  82  in  FIG. 4  or the current sources  96  and  98  in  FIG. 6 , which avoids interface misjudgment resulted from floating on the ports  42  and  44  of the host computer  10 , and similar effects will be produced by use of other devices with voltage dividing or current injection. 
   While the present invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and scope thereof as set forth in the appended claims.