Abstract:
A charge pump and a voltage doubler are provided. The charge pump minimizes the difference in voltage between the terminals of a MOS transistor by serially connecting PMOS and NMOS transistors inside the charge pump circuit. The charge pump is able to provide a higher voltage while avoiding a large voltage difference at the gate-source, gate-base and gate-drain interfaces.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
   This application claims the priority benefit of Taiwan application serial no. 91135002, filed Dec. 3, 2002. 
   BACKGROUND OF THE INVENTION 
   1. Field of Invention 
   The present invention relates to a charge pump and a voltage doubler using the same. More particularly, the present invention relates to a charge pump comprising low-pressure fabricated metal-oxide-semiconductor (MOS) devices and a voltage doubler using the same. 
   2. Description of Related Art 
     FIG. 1A  is a circuit diagram of a conventional charge pump. As shown in  FIG. 1A , the charge pump  10  comprises two N-type metal oxide semiconductor (NMOS) transistors  102  and  104  and two capacitors  112  and  114 . One source/drain terminal of the NMOS transistor  102  is electrically coupled to an input voltage V IN  terminal while the other source/drain terminal of the NMOS transistor  102  is electrically coupled to one terminal  112   a  of the capacitor  112 . The substrate terminal of the NMOS transistor  102  is connected to ground and the gate terminal of the NMOS transistor  102  is connected to one terminal  114   a  of the capacitor  114 . Voltage at the capacitor terminal  114   a  serves as an output voltage V 01 , of the charge pump  10 . Similarly, one source/drain terminal of the NMOS transistor  104  is electrically coupled to the input voltage V IN  terminal while the other source/drain terminal of the NMOS transistor  104  is electrically coupled to the capacitor terminal  114   a . The substrate terminal of the NMOS transistor  104  is connected to ground and the gate terminal of the NMOS transistor  104  is electrically connected to the capacitor terminal  112   a . Voltage at the capacitor terminal  112   a  serves as another output voltage V 02  of the charge pump  10 . In addition, the other terminal  112   b  of the capacitor  112  receives a clocking signal CK and the other terminal  114   b  of the capacitor  114  receives an inverse clocking signal CK′ during operation. 
   Initially, voltage difference at the two terminals of both capacitors  112  and  114  is at 0V. Assume that the clocking signal CK is a signal having a voltage between 0 to V 1  during operation, the voltage V 1  is identical or greater than V IN  and the clocking signal CK is at a high potential level initially. At the beginning of operation, voltage difference between the ends of the capacitor  112  is maintained at 0V due to the capacitor property. Hence, voltage at the capacitor terminal  112   a  is raised to V 1 . Under this condition, because the inverted clocking signal CK′ is at 0V, the charge pump  10  outputs a voltage V 01  of 0V and a voltage V 02  of V 1 . Thereafter, since V 1 ≧V IN , the NMOS transistor  104  conducts and hence V IN  gradually charges up the capacitor  114 . Consequently, after the passage of some time, voltage at the capacitor terminal  114   a  is raised to a level almost identical to V IN . 
   When phase of the clocking signal CK reverses back to 0V (that is, phase of the inverted clocking signal CK′ reverses back to V 1 ), voltage difference between the terminals  112   a  and  112   b  of the capacitor  112  is maintained during a transient period. Consequently, the capacitor terminal  112   a  returns to 0V. Similarly, because the voltage difference between the terminals  114   a  and  114   b  of the capacitor  114  is maintained during a transient period when phase of the inverted clocking signal CK′ reverses, voltage at the capacitor terminal  114   a  is pushed up to V IN +V 1 . In other words, during the transient phase inversion of the clocking signal CK, the output voltage V 01  is V IN +V 1  and the output voltage V 02  is at 0V. Under this condition, the NMOS  104  is cut off and the NMOS transistor  102  conducts because the gate voltage (equivalent to the output voltage V 01 ) is greater than the input voltage V IN . Thus, voltage at the capacitor terminal  112   a  gradually rises from 0V towards V IN . 
   For the same reason, during the transient period when the phase of the clocking signal CK reverses, the output voltage V 01  drops back to V IN  while the output voltage V 02  rises up towards V IN +V,. In subsequent operations, the output voltages V 01  and V 02  will fluctuate in cycles between V IN  and V IN +V 1 . 
   However, for this type of circuit, the biggest voltage difference sustainable by the gate-substrate of the NMOS transistors  102  and  104  is V IN +V 1 . Therefore, the NMOS transistors  102  and  104  must be able to withstand a voltage greater than V IN +V 1 . In other words, the gate-substrate interface of the NMOS transistors  102  and  104  must be able to withstand a voltage difference equivalent to the output voltage value. 
   A voltage doubler that uses this type of charge pump was first disclosed in the article ‘A High-Efficiency CMOS Voltage Doubler’ of the IEEE Journal of Solid State Circuits, Vol. 33, No. 3, March 1998 by Philippe Deval and Mechel J. Declercq.  FIG. 1B  is a circuit diagram of the voltage doubler that uses the conventional charge pump design shown in  FIG. 1A . The clocking signal CK varies cyclically between V IN  and 0V during operation. Hence, the output voltage V OUT  approaches 2*V IN . Similarly, the gate-substrate interface of the NMOS transistor  122  and  124  must be able to sustain a voltage difference of at least 2*V IN . In  FIG. 1B , a clock signal CK is connected to a terminal  132   b  of the capacitor  132 . The another terminal  132   a  of the capacitor  132  is connected to the NMOS transistor  122 . Similarly, an inverted clock signal CK′ is connected to a terminal  134   b  of the capacitor  134 . The another terminal  134   a  of the capacitor  134  is connected to the NMOS transistor  124 . In addition, the PMOS transistors  140 ,  142 ,  144 , and  146  form a circuit, as shown in  FIG. 1B , which has two terminals coupled to the terminals  132   a  and  134   a  and a voltage output terminal V OUT . The voltage output terminal is also coupled to a ground via a capacitor  152 . In addition all the substrates of the PMOS transistors  140 ,  142 ,  144 , and  146  are coupled to the around via a capacitor  150 . 
   SUMMARY OF THE INVENTION 
   Accordingly, one object of the present invention is to provide a charge pump and a voltage doubler using the same. Through the serial connection of a P-type metal oxide semiconductor (PMOS) transistor with an N-type metal oxide semiconductor (NMOS) transistor, metal oxide semiconductor (MOS) devices within the charge pump are subjected to a lower voltage differential at the gate-source, gate-substrate and gate-drain interface. Nevertheless, the same degree of voltage push-up as in the conventional technique is provided. 
   To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a charge pump. The charge pump has a voltage source, a signal source, a first and a second control signal generation unit, a first and a second output voltage generation unit and a first and a second capacitor. The voltage source provides an input voltage and the signal source provides a clocking signal and an inverted clocking signal for operation. 
   The first control signal generation unit receives an input voltage, the inverted clocking signal and a ground voltage and outputs a set of first control signals whose voltage levels are determined by the inverted clocking signal. The second control signal generation unit receives an input voltage, the clocking signal and a ground voltage and outputs a set of second control signals whose voltage levels are determined by the clocking signal. 
   The first output voltage generation unit has a first output terminal. The first output voltage generation unit receives the input voltage and the first control signal and determines if the circuit between the input voltage and the first output terminal becomes electrically conductive according to the first control signal. Similarly, the second output voltage generation unit has a second output terminal. The second output voltage generation unit receives the input voltage and the second control signal and determines if the circuit between the input voltage and the second output terminal becomes electrically conductive according to the second control signal. 
   A first capacitor terminal of the first capacitor receives the clocking signal. The other capacitor terminal of the first capacitor outputs the first output voltage and the capacitor terminal couples electrically with the first output terminal. A first capacitor terminal of the second capacitor receives the inverted clocking signal. The other capacitor terminal of the second capacitor outputs the second output voltage and the capacitor terminal couples electrically with the second output terminal. 
   In brief, voltage differential at the gate-substrate, gate-drain and gate source interface of various MOS devices inside the charge pump of this invention is smaller than the voltage differential at the same interfaces inside the MOS devices of a conventional charge pump. Hence, a low pressure CMOS fabrication process can be used to fabricate MOS devices having a voltage push-up capacity identical to the conventional technique but with a longer working life. 
   It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. 
       FIG. 1A  is a circuit diagram of a conventional charge pump. 
       FIG. 1B  is a circuit diagram of the voltage doubler that uses the conventional charge pump design shown in  FIG. 1A . 
       FIG. 2  is a block diagram showing the circuit of a charge pump according to one preferred embodiment of this invention. 
       FIG. 3  is a block diagram showing the circuit of a voltage doubler according to one preferred embodiment of this invention. 
       FIG. 4  is an actual circuit diagram of a charge pump according to another preferred embodiment of this invention. 
       FIG. 5  is an actual circuit diagram of a voltage doubler according to another preferred embodiment of this invention. 
   

   DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. 
     FIG. 2  is a block diagram showing the circuit of a charge pump according to one preferred embodiment of this invention. As shown in  FIG. 2 , the charge pump includes two control signal generation units  202  and  204 , two output voltage generation units  206  and  208  and two capacitors  230  and  232 . The control signal generation unit  202  receives an input voltage V IN  from a voltage source (not shown), a ground voltage and an inverted clocking signal CK′ from a signal source (not shown), and generates a first control signal. The control signal generation unit  204  receives the input voltage V IN , a ground voltage and a clocking signal CK from a signal source (not shown), and generates a second control signal. The clocking signal CK and the inverted clocking signal CK′ have a phase inversion relationship. 
   In this embodiment, voltage level of the first control signal from the control signal generation unit  202  is determined by the inverted clocking signal CK′. In other words, the inverted clocking signal CK′ at a low potential may prompt the control signal generation unit  202  to produce a high or a low first control signal according to the circuit design. Conversely, the inverted clocking signal CK′ at a high potential may also prompt the control signal generation unit  202  to produce a high or a low first control signal. In a similar way, the relationship between the control signal generation unit  204  and the second control signal closely matches the relationship between the control signal generation unit  202  and the first control signal. 
   The output voltage generation unit  206  receives the voltage V IN  and the first control signal and outputs via an output terminal  220 . The output voltage generation unit  208  receives the voltage V IN  and the second control signal and outputs via an output terminal  222 . For the output voltage generation unit  206 , whether the input voltage V IN  is connected to the first output terminal  220  by an internal circuit depends on the voltage level of the first control signal. For example, if the first control signal is at a high potential, the circuit between the input voltage V IN  and the first output terminal  220  is connected. On the other hand, if the first control signal is at a low potential, circuit connection between the input voltage V IN  and the first output terminal  220  is cut. Similarly, for the output voltage generation unit  208 , if the second control signal is at a high potential, the circuit between the input voltage V IN  and the second output terminal  222  is connected. On the contrary, if the second control signal is at a low potential, circuit connection between the input voltage V IN  and the second output terminal  222  is cut. Obviously, contrary or different response to the control signal for the output voltage generation units  206  and  208  is also possible. 
   The charge pump circuit in  FIG. 2  further includes two capacitors  230  and  232 . One end of the capacitor  230  receives the clocking signal CK while the other end of the capacitor  230  couples electrically to the first output terminal  220 . Meanwhile, the first output voltage is output from the output terminal V OUT1 . Similarly, one end of the capacitor  232  receives the inverted clocking signal CK′ while the other end of the capacitor  232  couples electrically with the second output terminal  222 . The second output voltage is output from the output terminal V OUT2 . 
     FIG. 3  is a block diagram showing the circuit of a voltage doubler according to one preferred embodiment of this invention. In  FIG. 3 , the charge pump structure and operating method is similar the one shown in  FIG. 2  and hence detailed description is omitted. In general, the largest voltage from the output terminals V OUT1  and V OUT2  is roughly twice that of the input voltage V IN . Hence, voltage doubling is obtained if the output voltage switching unit  340  picks up the one having the highest voltage to be the output voltage at the output terminal V 0  among the output terminals V OUT1  and V OUT2 . In  FIG. 3 , the charge pump circuit  32 , like in  FIG. 2 , includes two capacitors  330  and  332 . One end of the capacitor  330  receives the clocking signal CK while the other end of the capacitor  330  couples electrically to the first output terminal  220  of the output voltage generation unit  206 . Meanwhile, the first output voltage at the first output terminal  220  is output from the output terminal V OUT1 . Similarly, one end of the capacitor  332  receives the inverted clocking signal CK′ while the other end of the capacitor  332  couples electrically with the second output terminal  322  of the output voltage generation unit  308 . The second output voltage at the second output terminal  322  is output from the output terminal V OUT2 . The control signal generation units  302  and  304  are similar to the control signal generation units  202  and  204  in  FIG. 2 . 
   In the following, circuit elements inside a charge pump and an output voltage switching unit are further disclosed. Note that the circuit elements and structure in the subsequent embodiment is just one among many possible arrangements and hence should by no means restrict the scope of this invention. 
     FIG. 4  is an actual circuit diagram of a charge pump according to another preferred embodiment of this invention. As shown in  FIG. 4 , the charge pump includes P-type metal oxide semiconductor (PMOS) transistors  402 ,  404 ,  406  and  408 , N-type metal oxide semiconductor (NMOS) transistors  412 ,  414 ,  416  and  418  and capacitors  430  and  440 . In addition, the charge pump receives an input voltage V IN  from a voltage source (not shown) and a clocking signal CK and an inverted signal CK′ from a signal source (not shown). 
   One capacitor terminal (or the first terminal of the first capacitor) of the capacitor  430  (or the first capacitor) receives the clocking signal CK. The other capacitor terminal (or the second terminal of the first capacitor) of the capacitor  430  connects with an output terminal V OUT1  for outputting the first output voltage. One capacitor terminal (or the first capacitor terminal of the second capacitor) receives the inverted clocking signal CK′. The other capacitor terminal (or the second capacitor terminal of the second capacitor) of the capacitor  440  (or the second capacitor) connects with another output terminal V OUT2  for outputting the second output voltage. 
   One source/drain terminal (or the first source/drain terminal of the first PMOS transistor) of the PMOS transistor  402  (or the first PMOS transistor) is electrically connected to the capacitor  430  and the substrate (or the substrate of the first PMOS transistor) of the PMOS transistor  402 . The other source/drain terminal (or the second source/drain terminal of the first PMOS transistor) of the PMOS transistor  402  is electrically connected to a voltage source for receiving an input voltage V IN . Similarly, one source/drain terminal (or the first source/drain terminal of the second PMOS transistor) of the PMOS transistor  404  (or the second PMOS transistor) is electrically connected to the capacitor  430  and the substrate (or the substrate of the second PMOS transistor) of the PMOS transistor  404 . The other source/drain terminal (or the second source/drain terminal of the second PMOS transistor) of the PMOS transistor  404  is electrically connected to the gate (or the gate of the first PMOS transistor) or the PMOS transistor  402 . Furthermore, the gate (or the gate of the second PMOS transistor) of the PMOS transistor  404  is electrically connected to the voltage source for receiving the input voltage V IN . 
   One source/drain terminal (or the first source/drain terminal of the third PMOS transistor) of the PMOS transistor  406  (or the third PMOS transistor) is electrically connected to the capacitor  440  and the substrate (or the substrate of the third PMOS transistor) of the PMOS transistor  406 . The other source/drain terminal (or the second source/drain terminal of the third PMOS transistor) of the PMOS transistor  406  is electrically connected to the voltage source for receiving an input voltage V IN . Similarly, one source/drain terminal (or the first source/drain terminal of the fourth PMOS transistor) of the PMOS transistor  408  (or the fourth PMOS transistor) is electrically connected to the capacitor  440  and the substrate (or the substrate of the fourth PMOS transistor) of the PMOS transistor  408 . The other source/drain terminal (or the second source/drain terminal of the fourth PMOS transistor) of the PMOS transistor  408  is electrically connected to the gate (or the gate of the third PMOS transistor) of the PMOS transistor  406 . Furthermore, the gate (or the gate of the fourth transistor) of the PMOS transistor  408  is electrically connected to the voltage source for receiving the input voltage V IN . 
   The gate (or the gate of the first NMOS transistor) of the NMOS transistor  412  (or the first NMOS transistor) is electrically connected to the voltage source for receiving the input voltage V IN . One source/drain terminal (or the second source/drain terminal of the first NMOS transistor) of the NMOS transistor  412  is electrically connected to the gate of the PMOS transistor  402 . The substrate (or the substrate of the first NMOS transistor) is connected to a ground. One source/drain terminal (or the first source/drain terminal of the second NMOS transistor) of the NMOS transistor  414  (or the second NMOS transistor) and the substrate (or the substrate of the second NMOS transistor) of the NMOS transistor  414  are connected to a ground. The other source/drain terminal (or the second source/drain terminal of the second NMOS transistor) of the NMOS transistor  414  is electrically connected to a source/drain terminal (or the first source/drain terminal of the first NMOS transistor) of the NMOS transistor  412 . The gate (or the gate of the second NMOS transistor) of the NMOS transistor  414  receives the inverted clocking signal CK′. The gate (or the gate of the third NMOS transistor) of the NMOS transistor  416  (or the third NMOS transistor) is electrically connected to the voltage source for receiving the input voltage V IN . A source/drain terminal (or the second source/drain terminal of the third NMOS transistor) of the NMOS transistor  416  is electrically connected to the gate of the PMOS transistor  406 . The substrate (or the substrate of the third NMOS transistor) of the NMOS transistor  416  is electrically connected to a ground. A source/drain terminal (or the first source/drain terminal of the fourth NMOS transistor) of the NMOS transistor  418  (or the fourth NMOS transistor) and the substrate (the substrate of the fourth NMOS transistor) of the NMOS transistor  418  are electrically connected to a ground. The other source/drain terminal (or the second source/drain terminal of the fourth NMOS transistor) of the NMOS transistor  418  is electrically connected to the source/drain terminal (or the first source/drain terminal of the third NMOS transistor) of the NMOS transistor  416 . Furthermore, the gate (or the gate of the fourth NMOS transistor) of the NMOS transistor  418  receives the clocking signal CK. 
   To explain the operation of the charge pump according to this invention, assume the first and the second output voltage is at 0V initially. In addition, assume the fluctuation range of the clocking signal CK and the inverted clocking signal CK′ is between 0 to V IN  volts and that the initial voltage value of the clocking signal CK is 0 and the initial voltage value of the inverted clocking signal CK′ is at V IN . 
   At the very beginning, because the voltage value of the inverted clocking signal CK′ is at V IN , the NMOS transistor  414  conducts and hence the source/drain terminal of the NMOS transistor  414  and the source/drain terminal of the NMOS transistor  412  are at 0V. Since the gate terminal of the NMOS transistor  412  receives the input voltage V IN , the NMOS transistor  412  conducts and hence the source/drain terminal of the NMOS transistor  412 , the source/drain terminal of the PMOS transistor  404  and the gate terminal of the PMOS transistor  402  are at 0V. Because the gate terminal of the PMOS transistor  404  is at V IN  while the source/drain is at 0V, the PMOS transistor  404  is non-conductive. On the contrary, because the source/drain terminal of the PMOS transistor  402  receives the input voltage V IN  while the gate is at 0V, the PMOS transistor  402  conducts and hence the input voltage starts to charge up the capacitor  430 . Since the clocking signal CK is at a 0V, voltage difference between the terminals of the capacitor  430  approaches V IN  if sufficient time is given. In other words, the first output voltage from the output terminal V OUT1  approaches the input voltage V IN . 
   Conversely, because the clocking signal CK is at 0V, the NMOS transistor  418  is non-conductive. Since the gate terminal of the NMOS transistor  416  receives the input voltage V IN , the NMOS transistor  416  conducts and hence the voltage value at the source/drain terminal of the PMOS transistor  416 , the source/drain terminal of the PMOS transistor  406  and the gate of the PMOS transistor  406  approach V IN . Since the voltage value at the gate terminal of the PMOS transistor  408  is V IN , which is at a high level causing the PMOS transistor  408  to be non-conductive. Similarly, because the input voltage V IN received by the source/drain terminal of the PMOS transistor  406  is close to the voltage received by the gate terminal, the PMOS transistor  406  is non-conductive. Therefore, the second output voltage from the output terminal V OUT2  is roughly identical to the inverted clocking signal CK′. In other words, the second output voltage from the output terminal V OUT2  approaches V IN . 
   When the clocking signal CK reverses, that is, the voltage value of the clocking signal CK becomes V IN  while the voltage value of the inverted clocking signal CK′ becomes 0, both the PMOS transistor  402  and the PMOS transistor  404  are non-conductive according to the aforementioned derivation at the output terminal V OUT2 . Hence, due to the transient maintenance of existing voltage differential between the terminals of the capacitor  430 , the first output voltage at the output terminal V OUT1  is pushed up to V IN +V IN , that is, 2*V IN , transiently. Furthermore, because both the PMOS transistors  402  and  404  are non-conductive, the 2*V IN  voltage at the output terminal V OUT1  can be maintained. On the other hand, when the voltage value of the inverted clocking signal CK′ is 0, voltage differential between the two terminals of the capacitor  440  is maintained transiently. Hence, voltage at the capacitor terminal will drop to 0V simultaneously. However, because the PMOS transistors  406  and  408  will conduct, the input voltage V IN  will continue to charge up the output terminal V OUT2  until the voltage at the output terminal V OUT2  almost reaches V IN  if sufficient time is allowed. 
   Thereafter, as the clocking signal CK reverses, the PMOS transistor  402  and  404  will be conductive. Thus, voltage at the output terminal V OUT1  is maintained at V IN . On the other hand, because the PMOS transistors  406  and  408  are non-conductive, voltage at the output terminal V OUT2 is maintained at V IN . Under the condition that the capacitor  440  receives a voltage V IN  from the inverted clocking signal CK′, the second output voltage from the output terminal V OUT2  is 2*V IN . 
   Henceforth, the first output voltage and the second output voltage from the output terminals V OUT1  and V OUT2  will fluctuate cyclically between V IN  and 2*V IN . Yet, the gate-substrate interface inside the PMOS transistors  402 ,  404 ,  406  and  408  only has to withstand a voltage differential of V IN  instead of a voltage differential of 2*V IN  in a conventional circuit. 
     FIG. 5  is an actual circuit diagram of a voltage doubler according to another preferred embodiment of this invention. As shown in  FIG. 5 , the charge pump  52  is structurally similar to the one in  FIG. 4  and hence detailed description of its operation is not repeated here. The elements of  502 – 508 ,  512 – 518 ,  530  and  540  are similar to the elements  402 – 408 ,  412 – 418 ,  430 , and  440  in FIG  4 . The charge pump  52  with an application as an example has output terminals similar to the first output terminal V OUT1  and the second output terminal V OUT2  as shown in  FIG. 4 , and numbered in  FIG. 5  as  550  and  552 , respectively. In the same way, when the voltage of the clocking signal and the inverted clocking signal oscillates between 0 and V IN , voltage at the first output terminal V OUT1  and the second output terminal V OUT2  oscillates at a voltage between V IN  and 2*V IN . In the following, operation of the circuit outside the charge pump  52  is explained in detail. 
   Aside from the charge pump  52 , the circuit in  FIG. 5  further includes four PMOS transistors  562 ,  564 ,  566  and  568 , a substrate capacitor  570  and an output capacitor  580 . One source/drain terminal (or the first source/drain terminal of the fifth PMOS transistor) of the PMOS transistor  562  (or the fifth PMOS transistor) is electrically connected to the aforementioned second output terminal V OUT2  of the charge pump  52 . The other source/drain terminal (or the second source/drain terminal of the fifth PMOS transistor) of the PMOS transistor  562  is electrically connected to the substrate (or the substrate of the fifth PMOS transistor) of the PMOS transistor  562 . The gate (or the gate of the fifth PMOS transistor) of the PMOS transistor  562  is electrically connected to the aforementioned first output voltage terminal V OUT1  of the charge pump  52 . One source/drain terminal (or the first source/drain terminal of the sixth PMOS transistor) of the PMOS transistor  564  (or the sixth PMOS transistor) is electrically connected to the first output terminal V OUT1 . The other source/drain terminal (or the second source/drain terminal of the sixth PMOS transistor) of the PMOS transistor  564  is electrically connected to the substrate (or the substrate of the sixth PMOS transistor) of the PMOS transistor  564 . The gate (or the gate of the sixth PMOS transistor) of the PMOS transistor  564  is electrically connected to the second output terminal V OUT2 . 
   In addition, one source/drain terminal (or the first source/drain terminal of the seventh PMOS transistor) of the PMOS transistor  566  (or the seventh PMOS transistor) is electrically connected to the second output terminal V OUT2 . The other source/drain terminal (or the second source/drain terminal of the seventh PMOS transistor) of the PMOS transistor  566  is electrically connected to a final output terminal  590  for outputting a final output voltage V 0 . The substrate (or the substrate of the seventh PMOS transistor) of the PMOS transistor  566  is electrically connected to the substrate and source/drain terminal of the PMOS transistor  562 . The gate (or the gate of the seventh PMOS transistor) of the PMOS transistor  566  is electrically connected to the first output voltage terminal V OUT . One source/drain terminal (or the first source/drain terminal (or the eighth PMOS transistor) of the PMOS transistor  568  (or the eighth PMOS transistor) is electrically connected to the first output voltage terminal V OUT1 . The other source/drain terminal (or the second source/drain terminal of the eighth PMOS transistor) of the PMOS transistor  568  is electrically connected to the final output terminal  590 . The substrate (or the substrate of the eighth PMOS transistor) of the PMOS transistor  568  is electrically connected to the substrate of the PMOS transistor  564 . The gate (or the gate of the eighth PMOS transistor) of the PMOS transistor  568  is electrically connected to the second output voltage terminal V OUT2 . 
   Finally, one end of the substrate capacitor  570  is electrically connected to a ground while the other end of the substrate capacitor  570  is electrically connected to the substrates of the PMOS transistors  562 ,  564 ,  566  and  568 . One end of the output capacitor  580  is electrically connected to a ground while the other end is electrically connected to the output terminal  590 . 
   Assume the first output voltage V OUT1  is at V IN  and the second output voltage V OUT2  is at 2*V IN  after oscillation in the first output voltage V OUT1 , and the second output voltage V OUT2  is stabilized. Under these conditions, the PMOS transistors  562  and  566  are conductive while the PMOS transistors  564  and  568  are non-conductive so that the second output voltage V OUT2  (at a voltage 2*V IN ) charges up the output capacitor  580 . When the second output voltage V OUT2  becomes V IN , the PMOS transistors  562  and  566  are non-conductive while the PMOS transistor  564  and  568  are conductive so that the first output voltage V OUT1  (at a voltage 2*V IN ) charges up the output capacitor  580 . Accordingly, if sufficient waiting time is allowed, the final output voltage V 0  at the output terminal  590  will stabilize at a value double that of the input voltage, that is, 2*V IN . 
   Although MOS transistors are used in the circuit of this invention, similar devices such as metal-oxide-semiconductor field effect transistor (MOSFET), enhanced metal-oxide-semiconductor field effect transistor (enhanced MOSFET) or complementary metal-oxide-semiconductor (CMOS) are also applicable. 
   In summary, the voltage difference at the gate-substrate, gate-drain and gate-source interface inside the charge pump of this invention is smaller than the conventional circuit. In particular, peak voltage difference between the gate-substrate is only half the value in the conventional circuit. Consequently, a low pressure CMOS fabrication process can be used to fabricate MOS devices having a voltage push-up capacity identical to the conventional technique but with a longer working life. 
   It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.