Abstract:
A CMOS circuit maintains a constant slew rate over a range of environmental or process conditions. The circuit includes an output stage having a slew rate that is a function of the switching characteristic of the output stage and a bias current. A current adjustment stage adjusts the bias current in view of the switching characteristic to maintain a substantially constant slew rate. The slew rate of the output stage may be tuned to a desired level. A clamp may also be used to limit the voltage variations at the output stage.

Description:
TECHNICAL FIELD 
     This invention relates to CMOS circuits, and more particularly to techniques for maintaining a constant slew rate within a CMOS circuit. 
     BACKGROUND 
     Complementary metal oxide semiconductor (CMOS) circuits are subject to a slew rate that typically varies with environmental conditions and/or process parameters. A slew rate that varies over a large range is typically undesirable for many applications such as an Ethernet line driver. Therefore, CMOS circuits are typically modified to maintain a substantially constant slew rate. 
     Many techniques have been employed to maintain a substantially constant slew rate. A few of these techniques include trimming the circuit with fuses, the use of an oversampled waveform synthesizer, or using a replica bias circuit that is slaved to a phase locked loop. However, each of the previous techniques has disadvantages including, but not limited to, increasing the complexity of the circuit and having a corresponding increase in manufacturing cost. 
     Each transistor that is fabricated on the same integrated circuit chip typically has similar switching characteristics and behavior. This results from all of the devices on the same chip being fabricated at the same time with the same process parameters. As such, the circuits operate in a matched manner over wide variations in power supply voltage, process parameters (threshold voltage, channel length, etc.), and temperature. This consistent behavior allows the circuit of the present invention to control the relative current flow as will be described below. 
    
    
     DESCRIPTION OF DRAWINGS 
     Features and advantages of the present invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings. 
     FIG. 1 is a schematic diagram of the CMOS circuit to achieve a constant slew rate according to the present invention. 
     FIG. 2 is a graph of the variation of the I bias /V on  ratio over a range of beta conditions for the circuit of FIG.  1 . 
    
    
     DETAILED DESCRIPTION 
     A circuit  100  for maintaining a constant slew rate is disclosed in FIG.  1 . The circuit  100  includes a resistor  107 , transistors  105 ,  110 ,  125 ,  130 ,  150 ,  155 , current mirrors  115 ,  120 , a clamp  135 , and capacitors  140 ,  145 . The gate of the transistor  105  is connected to a bias voltage V bias  and to a first terminal of the resistor  107 . The drain of the transistor  105  is connected to a control voltage V cc . The source of the transistor  105  is connected to the source of the transistor  110  and to circuit ground. The gate of the transistor  110  is connected to a second terminal of the resistor  107  and to circuit ground. The drain of the transistor  110  is connected to the current mirror  115  and to circuit ground. 
     The drain of the transistor  125  is connected to the, current mirror  115 , to the clamp  135 , to the first terminal of the capacitor  140 , and to the gate of the transistor  155 . The gate of the transistor  125  is connected to a data input terminal. The source of the transistor  125  is connected to the source of the transistor  130  and to the current mirror  120 . The current mirror  120  is connected to the current mirror  115 . 
     The drain of the transistor  130  is connected to the current mirror  115 , to the clamp  135 , to the first terminal of the capacitor  145 , and to the gate of the transistor  150 . The gate of the transistor  130  is connected to the data input terminal. 
     The second terminals of the capacitors  140 ,  145  are connected to circuit ground. The drain of the transistor  150  is connected to a circuit output terminal  160 . The drain of the transistor  155  is connected to a circuit output terminal  165 . The source of the transistor  150  is connected to the source of the transistor  155  and to circuit ground. 
     The circuit  100  maintains a relatively constant slew rate by adjusting I bias  with the switching characteristic (V on ) of the transistors  150 ,  155 . The adjustments of I bias  are made in the current adjustment stage  102 . In the current adjustment stage  102 , a bias voltage V bias  is applied to the gate the transistor  105 , and another bias voltage V X  is applied to the gate of the transistor  110 . The bias voltage V X  is equal to the bias voltage V bias  minus the voltage drop across the resistor  107 . The bias voltages V bias  and V X  determines the transitions of the transistors  105  and  110 , respectively. 
     For a given temperature, the transistors  105 ,  110  have a specific switching characteristic V on . The switching characteristic V on  varies as a function of temperature and may also be affected during the fabrication process. For example, at a first temperature, the switching characteristic V on  may result in a large amount of current I 2  flowing through the transistor  105 , while a small amount of current I 1  flows through the transistor  110 . At the first temperature, the total amount of amount of current I t  flowing through the transistors  105 ,  110  may be split so that approximately 80% of the current is supplied by I 2  and approximately 20% of the current is supplied by I 1 . 
     As the temperature increases, the switching characteristic V on  is modified so more current I 1  flows through the transistor  110 . For example, at a second temperature which is higher than the first temperature, the amount of current I t  flowing through both transistors  105 ,  110  may be split so that 60% of the current is supplied by I 2  and 40% of the current is supplied by I 1 . As described above, each transistor fabricated on the same integrated circuit chip typically has similar switching characteristics and behavior. The switching characteristics of the transistors  105 ,  110  are therefore matched to the switching characteristics of the transistors  150 ,  155 . Therefore, the change in relative current flow through the transistors  105 ,  110  is approximately the same as the change in relative current flow through the transistors  150 ,  155  for similar environmental and process conditions. 
     The current I bias  is equal to the current I 1  combined with the current I X . The current Ix is maintained as a constant, and therefore any change in the current I 1  results in a corresponding change to the current I bias . Thus, as the switching characteristics V on  of the transistors  105 ,  110  adjusts the current I 1 , the current I bias  will also adjust. 
     The input stage  112  of the circuit  100  receives data input signals at the gates of the transistors  125 ,  130 . The data input signals are typically digital signals. The input data signals control the switching of the transistors  125 ,  130 . A current mirror  115  supplies the current I bias  to the drains of each of the transistors  125 ,  130 . The sources of the transistors are connected together to supply a current  2 I bias  to the current mirror  120 . 
     A voltage {overscore (A)} exists at the drain of the transistor  125 . A voltage A exists at the drain of the transistor  130 . When the input data signals cause the voltages {overscore (A)} and A to be equal, current is divided so that it flows equally through the transistors  150 ,  155 . As the input data signals change, the voltages {overscore (A)} and A also change. The variation in the voltages {overscore (A)} and A cause differing amounts of current to flow through the transistors  150 ,  155 . 
     The tuning stage  132  of the circuit adjusts and limits the slew rate. The tuning stage  132  includes the capacitors  140 ,  145  and the clamp  135 . The capacitors  140 ,  145  are preferably metal or gate oxide capacitors that have small dependence on process variation and no dependence on temperature deviation. 
     Because the input data signals are digital, the transistors  125 ,  130  can switch very fast. The capacitors  140 ,  145  are used to slow down the speed at which the transistors  125 ,  130  switch. The amount of time needed to charge the capacitors  140 ,  145  slows down the switching time of the transistors  125 ,  130 , and thus controls the slew rate. The value of the capacitors  140 ,  145  may be selected to tune the slew rate. For example, a slew rate of approximately 4 nanoseconds may be desired. With the digital input signal, the transistors  125 ,  130  switch at a rate in the picosecond range. By selecting the appropriate value for the capacitors  140 ,  145 , the switching rate of the transistors  125 ,  130  may be adjusted until the desired slew rate is obtained. 
     The tuning stage  132  also ensures the voltage swing at the gates of the transistors  150 ,  155  does not become too large. As stated above, if the voltages {overscore (A)} and A are equal, current flows equally through the transistors  150 ,  155 . After the transistors  150 ,  155  fully switch, it is not desirable for the voltages {overscore (A)} and A further separate. Therefore, after the transistors  150 ,  155  are fully switched, the clamp  135  limits the value of the voltages {overscore (A)} and A to ensure the variation does not become too large. 
     The output stage  147  provides output signals  160 ,  165  from the circuit  100 . The output signal  160  is at the drain of the transistor  150  and the output signal  165  is at the drain of the transistor  155 . The output signals  160 ,  165  are determined by the current flow through the transistors  150 ,  155 . The sources of the transistors  150 ,  155  are tied together, and the combined current from the sources is represented by I tail . 
     The current I bias  tracks the switching characteristic V on  of the transistors  150 ,  155  such that the output currents  160 ,  165  has a rise time that is nearly independent of process and temperature variations. The slew rate of the output  160 ,  165  is shown in given by:            I   out     T     ∝                    I   bias          I   tail         C                   V   on                                
     The variable V on  is the switching characteristic of the transistors  150 ,  155 . Because I tail  can be a constant current, and C (the capacitors  140 ,  145 ) can be implemented with metal or gate oxide capacitors that have small dependence on process variation and no dependence on temperature deviation, the ratio of I bias /V on  becomes the dominant component of the slew rate. The I bias /V on  ratio is defined by:            I   bias       V   on       =           β     I   t              (         I   t     2     +     I   x       )       -     V                 β                       1   2     -         V   2        β       4        I   t                           where                   V   on       =           I   t     β       =       V   gs     -     V   t                                
     The variable beta (β) defines the variations due to process and temperature. For a typical CMOS fabrication process, a beta range of 4 is equivalent to the full range of process variation (from slow to fast process corners) and the full range of temperature (from 0 to 130° C.). For beta varying by a factor of four due to process and temperature, and assuming I t =1 ampere, V=0.5 volts, and V on  varies form 0.5 to 1.0 volt, the slew rate is as follows:          For                 β     =       1                     I   bias       V   on         =     X   +   0.169                 For                 β     =       4                     I   bias       V   on         =     2      X                              
     Therefore, if I X =a constant current of 0.169, the I bias /V on  ratio is:            I   bias       V   on       =       0.669                   β       -       β   2                         1   2     -     β   16                                    
     This equation is present graphically in FIG.  2 . In FIG. 2, the I bias /V on  ratio is shown to only vary slightly over the beta range of 1 to 4. For the beta range of 1 to 4, the I bias /V on  ratio only changes by approximately 6%. Because the I bias /V on  ratio is the dominant component of the slew rate, the slew rate also does not vary significantly over the beta range. 
     Numerous variations and modifications of the invention will become readily apparent to those skilled in the art. Accordingly, the invention may be embodied in other specific forms without departing from its spirit or essential characteristics.