Abstract:
A resistive memory device requires a power supply having a reduced number of voltage taps and reduced power consumption. In accordance with one exemplary embodiment, one or more voltages used by a reference circuit which are normally supplied by different taps of a power supply are generated by corresponding power circuits. In accordance with a second exemplary embodiment, the power circuits are coupled to the bit lines and replace the reference circuit in a manner to improve sensing margin.

Description:
FIELD OF INVENTION  
       [0001]     The present invention relates generally to resistive memories. More specifically, the present invention relates to a method and apparatus for eliminating a power supply tap for supplying one or more reference voltages ordinarily used for sensing the state of a resistive memory cell.  
       BACKGROUND OF THE INVENTION  
       [0002]      FIG. 1  is an illustration of a resistive memory cell  100  in relationship to a bit line  121 , a word line  122 , and a cell plate  110 . The resistive memory cell  100  includes an access transistor  101  having one source/drain coupled to the bit line  121 , a gate coupled to the word line  122 , and another source/drain coupled to a bi-stable resistive material element  102 . The bi-stable resistive material element  102  is also coupled a cell plate  110 , which is typically shared among a plurality of resistive memory cells  100 . The cell plate  110  is also coupled to a source of cell plate voltage designated as CPIN.  
         [0003]     The bi-stable resistive material  102  can be any type of material that can be set to at least two different resistive states. The memory cell  100  may be classified based on the type of bi-stable resistive material  102 . For example, in programmable conductor random access memory (PCRAM) cell the bi-stable resistive material  102  is typically a type of chalcogenide glass, while MRAM cells, phase-change cells, polymer memory cells, and other types of resistive memory cells employ other corresponding types of bi-stable resistive material  102 .  
         [0004]     By way of example, the illustrated resistive memory cell  100  is a PCRAM cell, in which the bi-stable resistive material element  102  may be respectively set to a first resistive state (e.g., approximately 10K ohm) or a second resistive state (e.g., approximately 10M ohm), via a first programming voltage (e.g. approximately 0.25 volt) and a second programming voltage (e.g., approximately −0.25 volt). The resistive memory cell  100  may be read by pre-charging the bit line  121  to a predetermined voltage while the access transistor  101  is non-conducting, and then causing the access transistor  101  to become conducting, thereby discharging the bit line  121  through the resistive memory cell  100  to the cell plate  110  for a predetermined time. If the voltage across the bi-stable resistive material  102  is of a magnitude less than the magnitude of the programming voltages, the read process will not alter the state of the bi-stable resistive material  102 . The discharge rate is based on the state of the bi-stable resistive material  102 .  
         [0005]     A combination of cell plate voltage, bit line pre-charge voltage, and bi-stable resistive material  102  resistance may be chosen such that, when discharged, bit line  121  can be sensed using sensing circuits. Typically each sensing circuit is also coupled to a reference bit line, which is charged to a predetermined voltage. The predetermined voltage is set to an intermediate value between the two possible voltages of the bit line  121  being associated with the memory cell being read. The operation of the sensing circuit pulls the bit line having the higher voltage to an even higher voltage and pulls the bit line having the lower voltage down to a lower voltage (e.g., ground). Thus, after the operation of the sensing circuit, a comparator coupled to both bit lines can be used to output a digital signal corresponding to the state of the memory cell being read.  
         [0006]      FIGS. 2A and 2B  illustrate examples of portions of two resistive memory devices  200 . Each memory device  200  includes a plurality of resistive memory cells  100 , organized into an array by a plurality of word lines  122   a - 122   f  and a plurality of bit lines  121   a - 121   d . Each word line (generally referred to by numeral  122 ) and each bit line (generally referred to by numeral  121 ) are identical. The alphanumeric suffixes at the end of each word line  122  and bit line  121  are for distinguishing between individual word lines  122  and bit lines  121  in  FIGS. 2A and 2B .  
         [0007]     Due to space limitations, only a limited number of word lines  122 , bit lines  121 , and memory cells  100  are illustrated. However, it should be appreciated that actual memory devices typically include many more word lines  122 , bit lines  121 , and cells  100 .  FIGS. 2A and 2B  also illustrate a plurality of sensing circuits  300 , which are used for reading information stored in the memory cells  100 .  
         [0008]      FIG. 2A  is an illustration of an open architecture, where each sensing circuit  300  is associated with two bit lines (e.g., bit lines  121   a  and  121   b ) each associated with a different memory array  210 . In contrast,  FIG. 2B  is an illustration of a folded architecture, where each sensing circuit  300  is still associated with two bit lines (e.g.,  121   a ,  121   b ). However, in  FIG. 2B  these two bit lines are associated with alternating (i.e., odd/even) memory cells  100  of a same memory array  210 .  
         [0009]      FIG. 3  is a more detailed illustration of a sensing circuit  300 . The sensing circuit  300  includes an equalization circuit  310 , a reference setting circuit  320 , a switching circuit  330 , and a sense amplifier  340 . A multi-tap power supply  360  provides power at Veq, DVC2, Vref, and Vcc voltage levels to the sensing circuit  300 . A control circuit  350  provides control signals EQ, REFE, REFO, and SA_ISO to the sensing circuit  300 . The use of these voltages and control signals are described in greater detail below.  
         [0010]     The equalization circuit  310  includes two input nodes A 1  and A 2 , each coupled to a respective bit line  121 . One of the two bit lines  121  is a bit line connected to a memory cell  100  which will be read. The other bit line is another bit line  121  which is coupled to the same sensing circuit  300  as the bit line connected to the memory cell to be read. For the description below, it is assumed that bit line  121   a  is coupled to node A 1  and is the bit line connected to the memory cell  100  to be read, while bit line  121   b  is coupled to node A 2  and is the other bit line (also known as the reference bit line). However, one skilled in the art would recognize that the roles of the bit lines may be changed depending on which memory cell is being read. The equalization circuit  310  also includes two output nodes A 3  and A 4 , which are respectively coupled to input nodes A 5  and A 6  of the reference setting circuit  320 . Additionally, the equalization circuit  310  accepts, from a control circuit  350  the EQ control signal at node C 1 . In addition, the equalization circuit  310  accepts the equalization voltage Veq voltage at node P 1 .  
         [0011]     The function of the equalization circuit  310  is to equalize the voltages of the bit lines  121   a ,  121   b  respectively coupled to nodes A 1 , A 2  to the Veq voltage level. The sense process performed by the sensing circuit  300  begins with the operation of the equalization circuit  310 , in which the EQ control signal, which is typically asserted low, is temporarily asserted high. While the EQ control signal is asserted high, bit lines  121   a  and  121   b  are coupled to each other and also coupled to the Veq voltage. After a short time, both bit lines are charged to the Veq voltage. The EQ control signal is then returned to a low state, thereby decoupling bit lines  121   a  and  121   b  from each other and from the Veq voltage. The parasitic capacitance on the bit lines  121   a ,  121   b  holds the bit line voltage at the Veq level.  
         [0012]     The reference setting circuit  320  is used to change the voltage on one of the two bit lines  121   a ,  121   b  from the Veq voltage to a predetermined voltage Vref. The control circuit  350  temporarily asserts high one of control signals REFE (at node C 2 ) and REFO (at node C 3 ) to select the bit line having the memory cell  100  to be read as the bit line for changing the voltage. The reference setting circuit  320  also accepts power at the DVC2 (at node P 2 ) and Vref (at node P 3 ) voltages.  
         [0013]     The isolation circuit  330 , is a switch for controllably coupling or decoupling the sense amplifier  340  from the reference setting circuit  320 , and the from the bit lines coupled to nodes A 1  and A 2 . The isolation circuit  320  accepts the SA_ISO control signal, which is normally asserted low to isolate the sense amplifier  340  from the reference setting circuit  320 .  
         [0014]     After the reference setting circuit  320  has set bit line  121   b  to the predetermined voltage Vref, and while the SA_ISO control signal is asserted low, the word line  122  associated with the memory cell  100  to be read is asserted high for a predetermined time and then asserted low. During the predetermined time, the access transistor  101  of the memory cell  100  is set to a conductive state, thereby causing the bit line  121   a  associated with the memory cell  100  being read to discharge through the cell plate  110 . As a result, the bit line  121   a  associated with the memory cell  100  being read is now at a lower voltage. Depending upon the state of the memory cell  100 , the lower voltage is either at a first lower voltage which is higher in voltage than the Vref voltage, or a second lower voltage which is lower in voltage than the Vref voltage.  
         [0015]     The SA_ISO control signal is then asserted high to couple the sense amplifier  340  to both bit lines  121   a ,  121   b . The sense amplifier  340  is also respectively coupled to a Vcc power supply voltage and a ground potential voltage at nodes P 4  and P 5 . Bit line  121   a  has either a slightly higher or lower voltage than bit line  121   b , based on the state of memory cell  100 . The sense amplifier  340  magnifies the voltage difference by pulling the lower voltage bit line to ground and pulling the higher voltage bit line to a higher voltage. When the sense amplifier has completed this operation, a comparator (not illustrated) associated with the sense amplifier  340  can be used to output a high or low logical state corresponding to the state of the memory cell  100  at node  01 .  
         [0016]     As described above, the sensing circuit  300  is coupled to a variety of voltages supplied by a power supply. These include the Veq, DVC2, Vref, and Vcc voltages. The requirement to provide each additional voltage from a power supply  360  makes the power supply more complicated. Accordingly, there is a need and desire to reduce the number of power supply taps required by the sensing circuit of a resistive memory, thereby reducing power consumption.  
       SUMMARY OF THE INVENTION  
       [0017]     Exemplary embodiments of the method and apparatus of the present invention provide for reducing the number of power supply taps required to sense a resistive memory. In accordance with one exemplary embodiment, one or more voltages used by a reference circuit which are normally supplied by different taps of a power supply are generated by corresponding power circuits. In accordance with a second exemplary embodiment, the power circuits are coupled to the bit lines and replace the reference circuit. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]     The foregoing and other advantages and features of the invention will become more apparent from the detailed description of exemplary embodiments of the invention given below with reference to the accompanying drawings, in which:  
         [0019]      FIG. 1  illustrates a resistive memory cell;  
         [0020]      FIG. 2A  illustrates a first example of a portion of a resistive memory device;  
         [0021]      FIG. 2B  illustrates a second example of a portion of a resistive memory device;  
         [0022]      FIG. 3  illustrates a sensing circuit, including its equalization circuit, reference setting circuit, isolation circuit, and sense amplifier components;  
         [0023]      FIG. 4  illustrates a first exemplary embodiment of the present invention, including a sensing circuit and two power circuits;  
         [0024]      FIGS. 5A and 5B  illustrate two exemplary embodiments of the power circuits of  FIG. 4 ;  
         [0025]      FIG. 6  illustrates a second exemplary embodiment of the present invention, including a modified sensing circuit and two power circuits;  
         [0026]      FIG. 7  illustrates an exemplary memory device; and  
         [0027]      FIG. 8  illustrates a processor based system having a memory device constructed in accordance with the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0028]     Now referring to the drawings, where like reference numerals designate like elements, there is shown in  FIG. 4 , a first exemplary embodiment of the present invention.  FIG. 4  illustrates a sensing circuit  300 , a control circuit  350 , a modified power supply  360 ′ and two power circuit  500   a ,  500   b . The sensing circuit  300  of  FIG. 4  is identical to the sensing circuit  300  of  FIG. 3 . The control circuit  350 ′, however, is a modified version of the control circuit  350  of  FIG. 3 , and is discussed in greater detail below with respect to  FIG. 7 . The power supply  360 ′ may be a simplified power supply, which does not supply the Vref or DVC2 voltages described above, as these voltages are now respectively generated by power circuits  500   a ,  500   b.    
         [0029]      FIGS. 5A and 5B  respectively illustrate a first and second embodiments of the two power circuits  500   a ,  500   b  (denoted generally by numeral  500 ). As will be evident from the description of each embodiment, each power circuit  500  can be configured to generate different voltages. For example, the same power circuit  500  can be configured to generate the DVC2 or Vref voltages.  
         [0030]     In  FIG. 5A , a control circuit  501  receives power in the form of the Vcc voltage at node P 1 . The control circuit  501  also receives one or more control signals at node C 1 . Responsive to the one or more control signals asserted at node C 1 , the control circuit  501  creates either a positive magnitude pulse W 1  or a negative magnitude pulse W 2 . Pulses W 1  or W 2  are output from the control circuit  501  and received by a driver  502 , which is used to charge a capacitor  503 . By varying the magnitude and/or pulse width, and/or by selecting between a positive W 1  or negative W 2  magnitude pulse, in response to the state of the control signal(s) received at node C 1 , the control circuit  501  can cause the driver  502  to charge capacitor  503  with different levels of charge, thereby configuring the capacitor  503  to couple either the Vref, DVC2, or any other desired voltage at node P 2 . In one exemplary embodiment, the cell plate of the resistive memories are maintained at 1.2 volts, the DVC2 voltage is 1.0 volt, and the Vref voltage is 1.1 volts. However, it should be recognized that the invention may be practiced using different voltage parameters.  
         [0031]     The pulse width and/or magnitude of the pulses may be varied to change the total amount of charge transferred by the driver  502  to the capacitor  503 , thereby changing the magnitude of the voltage coupled to P 2 . Similarly, by permitting the control circuit  501  to produce either a positive going pulse W 1  or a negative going pulse W 2 , the voltage at P 2  can be used to either pull up or down the existing bit line voltage. The parameters for the pulse width, pulse magnitude, and the selection between a positive going W 1  or negative going W 2  pulse may be performed by asserting the appropriate control signals at node C 1 . Since many of these parameters are process dependent, they may vary for each memory chip. Thus, a memory device incorporating the invention may include a calibration circuit that calibrates the pulse parameters during start-up and/or reset.  
         [0032]     In  FIG. 5B , the order of the control circuit  501  and the driver  502  are reversed. The driver  502  is supplied a positive going W 1  or negative going W 2  pulse of the Vcc voltage, which is then supplied to a control circuit  501 . As with the embodiment of  FIG. 5A , the control circuit  501  accepts one or more control signals at node C 1 . Because there is no driver stage between control circuit  501  and the capacitor  503 , the control circuit  501  of  FIG. 5B  is more limited in its capabilities in comparison to the circuit  501  of  FIG. 5A . However, the circuit  501  in  FIG. 5B  can be used to trim the magnitude or pulse width of the pulses W 1 , W 2 , thereby reducing the magnitude of the voltage output at node P 2 .  
         [0033]      FIG. 6  is an illustration of a sensing circuit  300 ′ according to another exemplary embodiment of the invention. More specifically, in  FIG. 6 , the sensing circuit  300  of  FIG. 5  has been replaced with a modified sensing circuit  300 ′. The modified sensing circuit  300 ′ differs from the sensing circuit  300  of  FIGS. 3-4  in that the reference setting circuit  320  ( FIGS. 3-4 ) has been eliminated. As a result, the equalization circuit  310  now directly couples to the isolation circuit  330 . Power circuits  500   a ,  500   b  are now respectively coupled to one of the two bit lines associated with the sensing circuit  300 ′. The control circuit  350 ′ is a modified version of the control circuit  350  ( FIG. 3 ), and is discussed in greater detail below with respect to  FIG. 7 .  
         [0034]     The power circuits  500   a ,  500   b  are now also coupled to the REFE and REFO control signals. In the illustrated configuration, the power circuits  500   a  and  500   b  are respectively being used to generate voltages which will be coupled to both bit lines. For example, power circuit  500   a  can be configured via control signals REFE and REFO to set a particular a bit line (e.g., bit line  121   a ) to the Vref voltage. At the same time, power circuit  500   b  can be configured to either idle, if the previously applied Veq voltage is deemed suitable for the forthcoming sensing operation, or to supply a specific voltage to the other bit line (e.g., bit line  121   b ). The power circuits  500   a  and  500   b  of  FIG. 6  are essentially identical to the power circuit  500  illustrated by  FIGS. 5A and 5B , but require a somewhat more complex control circuit  501  for responding to the REFE and REFO control signals.  
         [0035]      FIG. 7  illustrates in block diagram form the organization of a memory device  200 ′ constructed in accordance with the principles of the invention. The memory device  200 ′ includes a plurality of memory arrays  210   a ,  210   b , sensing circuits  300   a / 300 ′ a - 300   d / 300   d ′, and power circuits  500   a - 500   h . More specifically, each array (e.g.,  210   a ) is associated with a respective sensing circuit (e.g.,  300   a / 300   a ′ and  300   b / 300   b ′). Each sensing circuit (e.g.,  300   a / 300   a ′) is respectively associated with a pair of power circuits (e.g.,  500   a  and  500   b ). A single control circuit  350 ′ is used. When processing a read transaction, the control circuit  350 ′ identifies the sensing circuit (e.g.,  300   a / 300   a ′) associated with the cell to be read and activates only the power circuits (e.g.,  500   a  and  500   b ) associated with that sensing circuit. The memory device  200 ′ also includes a conventional power supply  360 ′ for supplying the Vcc and Veq voltages to the plurality of sensing circuits. However, the conventional power supply  360 ′ and its connections are not illustrated in order to avoid cluttering the figure.  
         [0036]     The present invention is therefore directed to the use of one or more power circuits for producing from an existing power supply voltage tap, one or more voltages necessary for sensing the state of the resistive memory cell. More specifically, one or more power circuits are supplied at least one control signal and the Vcc voltage. A pulse train is driven by a driver and controlled by a control circuit to charge a capacitor. The level of charge stored on the capacitor permits the Vcc voltage to generate a variety of voltages, which can subsequently be supplied to various components of a sensing circuit, thereby eliminating the need for the power supply itself to include voltage taps at these voltage levels.  
         [0037]      FIG. 8  illustrates a processor based system  800 . The system  800  is exemplary of a digital system. Without being limited, system  800  could be a part of a computer system, camera, scanner, machine vision system, vehicle or personal navigation system, portable telephone with camera, video phone, surveillance system, auto focus system, optical tracking system, image stabilization system, motion detection system, or other digital system. System  800  generally comprises a bus  820 . Coupled to the bus  820  are a processor, such as CPU  802 , a memory, such the memory  200 ′ of  FIG. 7 , and a plurality of I/O device  806   a ,  806   b.    
         [0038]     It should be appreciated that other embodiments of the invention include a method of manufacturing the circuit  700 . For example, in one exemplary embodiment, a method of manufacturing a power supply circuit include the steps of providing, over a portion of a substrate corresponding to a single integrated circuit, control circuit coupled to a driver, and a capacitor coupled to either the drive or the control circuit.  
         [0039]     While the invention has been described in detail in connection with the exemplary embodiments, it should be understood that the invention is not limited to the above disclosed embodiments. Rather, the invention can be modified to incorporate any number of variations, alternations, substitutions, or equivalent arrangements not heretofore described, but which are commensurate with the spirit and scope of the invention. Accordingly, the invention is not limited by the foregoing description or drawings, but is only limited by the scope of the appended claims.