Abstract:
A semiconductor circuit designing apparatus includes a circuit design unit executing and an inspection item database section. The circuit design unit executes a logical design of a semiconductor integrated circuit. In the inspection item database section a circuit feature of the semiconductor integrated circuit corresponds to an inspection item of a inspection to be executed before a layout design of the semiconductor integrated circuit is executed. The circuit design unit generates a target circuit feature information indicating the circuit feature of a target semiconductor integrated circuit of the semiconductor integrated circuit of which the logical design should be executed. The circuit design unit obtains a target inspection item of the inspection item corresponding to the target circuit feature information from the inspection item database section. The circuit design unit executes the logical design of the target semiconductor integrated circuit in reference to the target inspection item.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a semiconductor circuit designing apparatus and a semiconductor circuit designing method. More particularly, the present invention relates to a semiconductor circuit designing apparatus and a semiconductor circuit designing method, which are used in a silicon interface field of an ASIC development so as to further reduce the number of steps in a circuit design and a layout design.  
           [0003]    2. Description of the Related Art  
           [0004]    In a field of a semiconductor design, a division between a circuit design and a layout design is advanced as a circuit becomes large and complex, and the respective automations are advanced. In such division, an acceptance inspection is executed for examining whether or not a circuit information interfaced so as to minimize a backward motion of a step is reasonable. Inspection items for such an acceptance inspection are different depending on a circuit feature, such as a circuit configuration, a test simplifying method to be used and the like. So, the items of the acceptance inspection to be executed are determined depending on the circuit feature.  
           [0005]    A layout designer carries out all necessary acceptance inspections for each model, on the basis of the circuit information prepared by the circuit designer. So, a number of steps are needed in order to execute the acceptance inspection and confirm the result. Or, there may be a case that an acceptance inspection on the layout designer side is omitted by inquiring the executed inspection items of the circuit designer. However, an answer (entry) miss on the circuit designer side, a misunderstanding or the like causes an erroneous result to be reported, which results in the backward motion of the step (iteration) in many cases.  
           [0006]    A known drawing validation system disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 10-198708) includes a first memory for storing a data indicative of a drawing, a second memory for storing a data indicative of a predetermined condition and a judging unit for judging whether or not the drawing agrees with the predetermined condition. Such a drawing validation system can automatically validate whether or not an item specified on the basis of a know-how and an experience of the circuit designer is accurately reflected to thereby prepare a drawing of a layout of a printed circuit board, without any manual work. Thus, it is possible to prepare the drawing with high quality in a short time.  
           [0007]    This drawing validation system relates to a determination of an inspection item and an inspection execution in a single drawing validation system to be used by the layout designer. Its applicable department is limited to the layout designer side. Thus, it does not disclose a method to be used for the circuit designer to avoid a problem.  
           [0008]    Japanese Laid Open Patent Application (JP-A-Heisei, 10-79435) discloses the following semiconductor development information integrating apparatus. In a semiconductor information managing apparatus, the electronic data based on a photo-mask specification prepared in a semiconductor design and the electronic data in respective manufacturing processes prepared in a semiconductor manufacturing process are stored and managed in a same data or a plurality of databases as an integrated semiconductor information. Thus, the information with regard to a CAD apparatus, a semiconductor manufacturing electronic terminal and a semiconductor manufacturing apparatus are shared.  
         SUMMARY OF THE INVENTION  
         [0009]    The present invention is accomplished in view of the above mentioned problems. Therefore, an object of the present invention is to provide a semiconductor circuit designing apparatus and a semiconductor circuit designing method, in which an iteration, such as a re-design and the like, caused by a design trouble can be reduced.  
           [0010]    Another object of the present invention is to provide a semiconductor circuit designing apparatus and a semiconductor circuit designing method, in which inspection items can be reduced.  
           [0011]    Still another object of the present invention is to provide a semiconductor circuit designing apparatus and a semiconductor circuit designing method, in which a burden of a number of steps on a circuit designer can be reduced.  
           [0012]    Still another object of the present invention is to provide a semiconductor circuit designing apparatus and a semiconductor circuit designing method, in which a burden of a number of steps on a layout designer can be reduced.  
           [0013]    In order to achieve an aspect of the present invention, a semiconductor circuit designing apparatus, includes: a circuit design unit executing a logical design of a semiconductor integrated circuit; and an inspection item database section in which a circuit feature of the semiconductor integrated circuit corresponds to an inspection item of a inspection to be executed before a layout design of the semiconductor integrated circuit is executed, and wherein the circuit design unit generates a target circuit feature information indicating the circuit feature of a target semiconductor integrated circuit of the semiconductor integrated circuit of which the logical design should be executed, and wherein the circuit design unit obtains a target inspection item of the inspection item corresponding to the target circuit feature information from the inspection item database section, and wherein the circuit design unit executes the logical design of the target semiconductor integrated circuit in reference to the target inspection item.  
           [0014]    In this case, the semiconductor circuit designing apparatus further includes: a model development history database section in which an ID data of the circuit design unit corresponds to the number of times the circuit design unit failed the inspection of the inspection item previously, and wherein the target inspection item is determined such that the inspection item of which the number of times is smaller than a predetermined value is withdrawn from the target inspection item.  
           [0015]    Also in this case, the semiconductor circuit designing apparatus further includes: a layout design unit executing the layout design, and wherein the circuit design unit executes the inspection of the target semiconductor integrated circuit of which the layout design is executed, with regard to the target inspection item, and wherein the circuit design unit provides a result of the inspection with the target semiconductor integrated circuit to the layout design unit.  
           [0016]    Further in this case, the semiconductor circuit designing apparatus further includes: a layout design unit executing the layout design, and wherein the circuit design unit executes the inspection of the target semiconductor integrated circuit of which the layout design is executed, with regard to the target inspection item, and wherein the circuit design unit provides a result of the inspection with the target semiconductor integrated circuit to the layout design unit.  
           [0017]    In this case, when the provided result of the inspection has no problem, the layout design unit stores the ID data of the circuit design unit and the number of times the circuit design unit failed the inspection of the target inspection item in the model development history database section.  
           [0018]    Also in this case, the inspection item database section belongs to the circuit design unit.  
           [0019]    Further in this case, the inspection item database section belongs to the circuit design unit.  
           [0020]    In this case, the inspection item database section belongs to the layout design unit.  
           [0021]    Also in this case, the inspection item database section belongs to the layout design unit.  
           [0022]    Further in this case, the inspection item database section belongs to the layout design unit.  
           [0023]    In this case, the layout design unit includes a plurality of layout design sections, and wherein the inspection item database section belongs to at least one of the plurality of layout design sections.  
           [0024]    Also in this case, the semiconductor circuit designing apparatus further includes: a data center provided to be different from the circuit design unit and the layout design unit, and wherein the inspection item database section belongs to the data center.  
           [0025]    In order to achieve another aspect of the present invention, a semiconductor circuit designing method, includes: (a) providing a inspection item database section in which a circuit feature of a semiconductor integrated circuit in which a logical design should be executed corresponds to an inspection item of a inspection to be executed before a layout design of the semiconductor integrated circuit is executed; (b) notifying a circuit designer executing the logical design of the semiconductor integrated circuit of the inspection item corresponding to the semiconductor integrated circuit retrieved from the inspection item database section; and (c) executing the logical design of the semiconductor integrated circuit by the circuit designer in reference to the notified inspection item.  
           [0026]    In this case, the semiconductor circuit designing method, further includes: (d) providing the semiconductor integrated circuit in which the notified inspection item is passed to a layout designer executing the layout design.  
           [0027]    In order to achieve still another aspect of the present invention, the semiconductor circuit designing method, includes: (e) providing a circuit design unit executing a logical design of a semiconductor integrated circuit; and (f) providing an inspection item database section in which a circuit feature of the semiconductor integrated circuit corresponds to an inspection item of a inspection to be executed before a layout design of the semiconductor integrated circuit is executed, and wherein the circuit design unit generates a target circuit feature information indicating the circuit feature of a target semiconductor integrated circuit of the semiconductor integrated circuit of which the logical design should be executed, and wherein the circuit design unit obtains a target inspection item of the inspection item corresponding to the target circuit feature information from the inspection item database section, and wherein the circuit design unit executes the logical design of the target semiconductor integrated circuit in reference to the target inspection item.  
           [0028]    In this case, the semiconductor circuit designing method further includes: (g) providing a model development history database section in which an ID data of the circuit design unit corresponds to the number of times the circuit design unit failed the inspection of the inspection item previously, and wherein the target inspection item is determined such that the inspection item of which the number of times is smaller than a predetermined value is withdrawn from the target inspection item.  
           [0029]    Also in this case, the semiconductor circuit designing method further includes: (h) providing a layout design unit executing the layout design, and wherein the circuit design unit executes the inspection of the target semiconductor integrated circuit of which the layout design is executed, with regard to the target inspection item, and wherein the circuit design unit provides a result of the inspection with the target semiconductor integrated circuit to the layout design unit.  
           [0030]    Further in this case, the semiconductor circuit designing method further includes: (i) providing a layout design unit executing the layout design, and wherein the circuit design unit executes the inspection of the target semiconductor integrated circuit of which the layout design is executed, with regard to the target inspection item, and wherein the circuit design unit provides a result of the inspection with the target semiconductor integrated circuit to the layout design unit.  
           [0031]    In this case, when the provided result of the inspection has no problem, the layout design unit stores the ID data of the circuit design unit and the number of times the circuit design unit failed the inspection of the target inspection item in the model development history database section.  
           [0032]    Also in this case, the inspection item database section belongs to the circuit design unit. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0033]    [0033]FIG. 1 is a block diagram showing a configuration of a semiconductor design system according to a embodiment of the present invention;  
         [0034]    [0034]FIG. 2 is a table of a check sheet of a semiconductor design system according to a embodiment of the present invention;  
         [0035]    [0035]FIG. 3 is a table of a inspection item database of a semiconductor design system according to a embodiment of the present invention;  
         [0036]    [0036]FIG. 4 is a table of a model development history database of a semiconductor design system according to a embodiment of the present invention;  
         [0037]    [0037]FIG. 5 is a flow chart of semiconductor design method according to a embodiment of the present invention;  
         [0038]    [0038]FIG. 6 is a flow chart of semiconductor design method according to a embodiment of the present invention;  
         [0039]    [0039]FIG. 7 is a flow chart of semiconductor design method according to another embodiment of the present invention;  
         [0040]    [0040]FIG. 8 is a flow chart of semiconductor design method according to another embodiment of the present invention;  
         [0041]    [0041]FIG. 9 is a flow chart of semiconductor design method according to still another embodiment of the present invention;  
         [0042]    [0042]FIG. 10 is a flow chart of semiconductor design method according to still another embodiment of the present invention;  
         [0043]    [0043]FIG. 11 is a block diagram showing a configuration of a semiconductor design system according to another embodiment of the present invention;  
         [0044]    [0044]FIG. 12 is a flow chart of semiconductor design method according to yet still another embodiment of the present invention;  
         [0045]    [0045]FIG. 13 is a flow chart of semiconductor design method according to yet still another embodiment of the present invention; and  
         [0046]    [0046]FIG. 14 is a block diagram showing a configuration of a semiconductor design system according to still another embodiment of the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0047]    With reference to the attached drawings, an embodiment of a semiconductor designing system according to the present invention, a plurality of engineering workstations (hereafter, abbreviated as [EWS]) are connected to each other. The plurality of EWS are provided with a circuit design EWS 1  and a layout design EWS 2 . They are connected to each other through a network  3 .  
         [0048]    The circuit design EWS 1  is installed for each circuit designer and used for a circuit design. For example, the circuit design EWS 1  belongs to a circuit designer A, and a circuit design EWS 1 ′ belongs to a circuit designer B. Circuit designers ID different from each other are assigned to the circuit designers. The circuit designer ID is used to identify the circuit designer and identify a right under which the circuit designer accesses the layout design EWS 2 . The circuit designer is one person or a plurality of persons attached to one group. That group is an enterprise, a department within an enterprise, a design group within a department or the like. The circuit design EWS 1  has a check sheet  4 . The check sheet  4  is an interface file in which a circuit feature of a semiconductor integrated circuit, an inspection item and an inspection result are noted. The check sheet  4  is prepared for each circuit design.  
         [0049]    The layout design EWS 2  belongs to a layout designer, and it is used for the layout design. The layout designer gives the circuit designer ID to each circuit designer. The layout design EWS 2  has an inspection item database  6  and a model development history database  7 . The inspection item database  6  is noted while a circuit feature and an inspection item necessary for the circuit feature are correlated to each other. The model development history database  7  is noted while a circuit designer ID of a designing circuit designer, a circuit feature of a previously designed semiconductor integrated circuit and a frequency of errors occurring in the development step are correlated to each other.  
         [0050]    [0050]FIG. 2 shows an actual example of the check sheet  4 . The circuit feature, the inspection item and an inspection result are noted in the check sheet  4 . A technology, a condition, a model name, a package, a number of pins, a presence or absence of a usage of a test simplifying method are noted as the circuit feature. The test simplifying method uses a scan, a boundary scan and RAM. A net list check, a pattern check, a scan check, a timing check and the like are noted as the inspection items.  
         [0051]    In the semiconductor integrated circuit according to this embodiment on which the acceptance inspection is performed, the technology is CMOS9HD, the condition is 3.3 V, the model name is 65956E00, the package is TBG, and the number of pins is 420 pins. Moreover, the scan manner of the test simplifying method is used without using the boundary scan and the RAM. The inspection items necessary for this semiconductor integrated circuit are the net list check, the pattern check, the scan check and the timing check. As the inspection result, there is no error in the net list check, there are two errors in the pattern check, the scan check is not executed, and there is no error in the timing check.  
         [0052]    [0052]FIG. 3 shows an actual example of the inspection item database  6 . As for the semiconductor integrated circuit, the inspection items are different depending on the circuit feature. The inspection items necessary for the respective circuit features of the semiconductor integrated circuit are noted in the inspection item database  6 . As the circuit feature, there are a basic configuration, a usage of the scan, a usage of the boundary scan, a usage of the RAM, a test bus configuration and the like. As the inspection items, there are the net list check, the pattern check, the scan check, the boundary scan check, the timing check, a test terminal check and a RAM check.  
         [0053]    If the semiconductor integrated circuit on which the acceptance inspection is performed is designed by only the basic configuration, the inspection items in the acceptance inspection that must be executed are the net list check, the pattern check and the timing check. If the semiconductor integrated circuit on which the acceptance inspection is performed employs the scan manner that is the test simplifying method, the inspection items in the acceptance inspection that must be executed are the net list check, the pattern check, the scan check and the timing check.  
         [0054]    If the semiconductor integrated circuit on which the acceptance inspection is performed employs the boundary scan manner that is the test simplifying method, the inspection items in the acceptance inspection that must be executed are the net list check, the pattern check, the boundary scan check and the timing check. If the semiconductor integrated circuit on which the acceptance inspection is performed employs the RAM, they are the net list check, the pattern check, the timing check and the RAM check. If the semiconductor integrated circuit on which the acceptance inspection is performed has the test bus configuration, the inspection items in the acceptance inspection that must be executed are the net list check, the pattern check, the timing check and the test terminal check.  
         [0055]    Such an inspection item database  6  clarifies the inspection items in the acceptance inspection to be executed. This results in the sure execution of the acceptance inspection.  
         [0056]    [0056]FIG. 4 shows an actual example of the model development history database  7 . In the model development history database  7 , the designer ID, the circuit feature and the inspection result are noted while they are correlated to each other, for each semiconductor integrated circuit.  
         [0057]    For example, in a case of a semiconductor integrated circuit having a model name of 6595E00 that is designed by a circuit designer whose circuit designer ID is AAA, its technology is COMS9HD, its condition is COMS3,3V, and its package is TBG. As the various inspection results of this semiconductor integrated circuit, there is no error in the net list check, there are two errors in the pattern check, the scan check is not executed, and there is no error in the timing check, in the acceptance inspection executed on September 11.  
         [0058]    In a re-acceptance inspection executed on September 14, there is no error in the net list check, there is no error in the pattern check, the scan check is not executed, and there is no timing check. In a back annotation executed on September 18, there is no error in the net list check, there are two errors in the pattern check, there is no error in the scan check, and there is no error in the timing check.  
         [0059]    [0059]FIGS. 5, 6 show the operation of the semiconductor designing system according to the present invention. At first, a circuit designer inputs a circuit designer ID to the circuit design EWS 1  (Step S 1 ). The circuit design EWS 1  sends the input circuit designer ID through the network  3  to the layout design EWS 2 .  
         [0060]    The layout design EWS 2  judges an allowance or rejection of an access in accordance with the circuit designer ID (Step S 2 ). If it is judged that there is no problem in the circuit designer ID, the access is allowed, and the layout design EWS 2  reports its fact to the circuit design EWS 1 . If the access is allowed, the circuit designer inputs to the circuit design EWS 1  the circuit feature of a semiconductor integrated circuit to be designed. The circuit design EWS 1  sends the circuit feature to the layout design EWS 2  (Step S 3 ).  
         [0061]    The layout design EWS 2  obtains the circuit designer ID and the circuit feature, retrieves an inspection item to be inspected on the basis of the inspection item database  6 , and retrieves a previous error of the circuit designer designing the semiconductor integrated circuit on the basis of the model development history database  7  (Step S 4 ). The layout design EWS 2  determines an inspection item to be executed at this time on the basis of the retrieved inspection item and error (Step S 5 ).  
         [0062]    For example, if there is an inspection item having no problem in five models finally developed by the circuit designer, an execution of the inspection item is exempted. If there is an item in which an error is recorded in the model development history database, the item is determined to be an inspection item to be executed. Such exemption enables the number of inspection items to be reduced on the basis of the experience and the level of the circuit designer. Thus, the burden on the circuit designer is relaxed. If the circuit designer is composed of a plurality of designers, the exempted inspection items are greater to further relax the burden on the circuit designer.  
         [0063]    The layout design EWS 2  sends the determined execution inspection item to the circuit design EWS 1 . The circuit design EWS 1  receives the execution inspection item from the layout design EWS 2 , and writes the inspection items and the circuit feature of the semiconductor integrated circuit to the check sheet  4  (Step S 6 ). The circuit design EWS 1  displays a previous error content received from the layout design EWS 2  on a screen. The circuit designer designs a logical circuit while paying attention to the previous error content and the execution inspection item (Step S 7 ). Since the item to which the attention must be paid can be obtained at an initial stage of a logical design, the circuit designer can avoid a logical design unsuitable for a layout design and accordingly avoid the re-design (iteration).  
         [0064]    If the design of the logical circuit is completed, a logical validation of the logical design is executed (Step S 8 ). If any trouble is discovered in the logical validation, the logical design is again carried out. After the completion of the logical design, the circuit design EWS 1  checks the acceptance inspection item noted in the check sheet  4  (Step S 9 ). The inspection result is additionally written to the check sheet  4 . If there is a rejected item among the inspection items noted in the check sheet  4 , the logical design is again carried out. Such re-design can prevent an unnecessary iteration in advance. If there is no problem in all the items among the acceptance inspection items, the circuit design EWS 1  sends the check sheet  4  together with the design data such as a circuit connection information, a pattern and the like to the layout design EWS 2  (Step S 10 ).  
         [0065]    The layout design EWS 2  compares the execution inspection items noted in the check sheet  4  with the executed result, in response to the reception of the check sheet  4 . If there is an inspection item in which the executed result is not noted in the inspection items to be executed, it is judged as a non-execution, and it is returned back to the circuit designer, and the inspection of the non-execution item is requested (Step S 11 ). If there is a result unsuitable for the layout as the result of the acceptance inspection, it is returned back to the circuit designer, and the improvement based on the re-design is requested (Step S 12 ). If the layout has no problem in all the inspection items, the inspection result together with the circuit feature and the circuit designer ID is written to the model development history database  7 .  
         [0066]    After that, the layout designer designs the layout (Step S 13 ). After the design of the layout, a back annotation is carried out (Step S 14 ). In the back annotation, it is confirmed whether or not the semiconductor integrated circuit carries out a desirably functional operation at a delay after the layout, and additionally writes its result to the model development history database  7 . If the result of the back annotation is NG, it is returned back to the circuit designer, and the improvement based on the re-design is requested. If the result of the back annotation is OK, an EB process is carried out (Step S 15 ).  
         [0067]    By the way, the back annotation may be executed by the circuit designer. At this time, after the design of the layout, the layout design data is sent from the layout design EWS 2  to the circuit design EWS 1 , and the circuit design EWS 1  executes the back annotation. If the back annotation is NG, the logical design is again carried out. If the back annotation is OK, the circuit design EWS 1  sends its fact to the layout design EWS 2 . The layout designer carries out the EB process, in response to the report of the back annotation OK.  
         [0068]    Due to the correspondent consideration between the previous error and problem and the circuit feature and the circuit designer, the circuit designer can obtain the items to be considered at the time of the logical design prior to the designing and thereby avoid the problem at the stage of the logical design. Also, since the circuit designer executes the acceptance inspection, the acceptance inspection of the layout designer is not required, which reduces the number of steps in the layout designer. Moreover, it is possible to reduce the request of the re-design to the circuit designer from the layout designer side caused by the defective result of the acceptance inspection. Such dispersion of the process can attain a further reduction in TAT.  
         [0069]    [0069]FIGS. 7, 8 show another operation of the semiconductor designing system according to the present invention. At first, a circuit designer inputs a circuit designer ID to the circuit design EWS 1  (Step S 21 ). The circuit design EWS 1  sends the input circuit designer ID through the network  3  to the layout design EWS 2 .  
         [0070]    The layout design EWS 2  judges an allowance or rejection of an access in accordance with the circuit designer ID (Step S 22 ). If it is judged that there is no problem in the circuit designer ID, the access is allowed, and the layout EWS 2  reports its fact to the circuit design EWS 1 . If the access is allowed, the circuit designer inputs to the circuit design EWS 1  the circuit feature of a semiconductor integrated circuit to be designed (Step S 23 ). The circuit design EWS 1  sends the circuit feature to the layout design EWS 2 .  
         [0071]    The layout design EWS 2  obtains the circuit designer ID and the circuit feature, and retrieves an inspection item to be inspected on the basis of the inspection item database  6 , and then retrieves a previous error of the circuit designer designing the semiconductor integrated circuit on the basis of the model development history database  7  (Step S 24 ). The layout design EWS 2  determines an inspection item to be executed at this time on the basis of the retrieved inspection item and error (Step S 5 ). For example, if there is an inspection item having no problem in five models finally developed by the circuit designer, an execution of the inspection item is exempted. If there is an item in which an error is recorded in the model development history database, the item is determined to be an inspection item to be executed. The layout design EWS 2  sends the determined inspection item to the circuit design EWS 1 .  
         [0072]    The circuit design EWS 1  receives the execution inspection item from the layout design EWS 2 , and writes the inspection items and the circuit feature of the semiconductor integrated circuit to the check sheet  4  (Step S 26 ). The circuit design EWS 1  displays a previous error content received from the layout design EWS 2  on the screen. The circuit designer designs a logical circuit while paying attention to the previous error content (Step S 27 ). If the design of the logical circuit is completed, a logical validation of the logical design is executed (Step S 28 ). If any trouble is discovered in the logical validation, the logical design is again carried out.  
         [0073]    After the completion of the logical design, the circuit design EWS 1  checks the acceptance inspection item noted in the check sheet  4  (Step S 29 ). The inspection result is additionally written to the check sheet  4 . If there is a rejected item among the inspection items noted in the check sheet  4 , the logical design is again carried out. If there is no problem in all the items among the acceptance inspection items, the circuit design EWS 1  sends the check sheet  4  together with the design data such as a circuit connection information, a pattern and the like to the layout design EWS 2  (Step S 30 ).  
         [0074]    The layout design EWS 2  compares the execution inspection items noted in the check sheet  4  with the executed result, in response to the reception of the check sheet  4  (Step S 31 ). If there is an inspection item in which the executed result is not noted in the inspection items to be executed, it is judged as a non-execution, and its inspection item is inspected (Step S 32 ). If there is a result unsuitable for the layout as the result of the acceptance inspection, it is returned back to the circuit designer, and the improvement based on the re-design is requested (Step S 33 ). If the layout has no problem in all the inspection items, the inspection result together with the circuit feature and the circuit designer ID is written to the model development history database  7 .  
         [0075]    After that, the layout designer designs the layout (Step S 34 ). After the design of the layout, the back annotation is carried out (Step S 35 ). The layout design EWS 2  additionally writes the result of the back annotation to the model development history database  7 . If the result of the back annotation is NG, it is returned back to the circuit designer, and the improvement based on the re-design is requested. The back annotation may be executed by the circuit designer, similarly to the above-mentioned embodiment. If the result of the back annotation is OK, the EB process is carried out (Step S 36 ).  
         [0076]    Since the inspection result of the acceptance inspection executed by the circuit designer is written to the check sheet  4 , it is not necessary that the same inspection item is again executed in an acceptance inspection on a layout designer side. Moreover, since the number of steps in the acceptance inspection can be reduced, the circuit designer can be devoted entirely to the logical design.  
         [0077]    [0077]FIGS. 9, 10 show the operation of the semiconductor designing system according to the present invention. At first, a circuit designer inputs a circuit designer ID to the circuit design EWS 1  (Step S 61 ). The circuit design EWS 1  sends the input circuit designer ID through the network  3  to the layout design EWS 2 .  
         [0078]    The layout design EWS 2  judges an allowance or rejection of an access in accordance with the circuit designer ID (Step S 62 ). If it is judged that there is no problem in the circuit designer ID, the access is allowed, and the layout EWS 2  reports its fact to the circuit design EWS 1 . If the access is allowed, the circuit designer inputs to the circuit design EWS 1  the circuit feature of a semiconductor integrated circuit to be designed. The circuit design EWS 1  sends the circuit feature to the layout design EWS 2  (Step S 63 ).  
         [0079]    The layout design EWS 2  obtains the circuit designer ID and the circuit feature, and retrieves an inspection item to be inspected on the basis of the inspection item database  6 , and then retrieves a previous error of the circuit designer designing the semiconductor integrated circuit on the basis of the model development history database  7  (Step S 64 ). The layout design EWS 2  determines an inspection item to be executed at this time on the basis of the retrieved inspection item and error (Step S 65 ). For example, if there is an inspection item having no problem in five models finally developed by the circuit designer, an execution of the inspection item is exempted. If there is an item in which an error is recorded in the model development history database, the item is determined to be an inspection item to be executed. The layout design EWS 2  sends the determined inspection item to the circuit design EWS 1 .  
         [0080]    The circuit design EWS 1  receives the execution inspection item from the layout design EWS 2 , and writes the inspection items and the circuit feature of the semiconductor integrated circuit to the check sheet  4  (Step S 66 ). The circuit design EWS 1  displays a previous error content received from the layout design EWS 2  on the screen. The circuit designer designs a logical circuit while paying attention to the previous error content (Step S 67 ). If the design of the logical circuit is completed, a logical validation of the logical design is executed (Step S 68 ). If any trouble is discovered in the logical validation, the logical design is again carried out.  
         [0081]    The circuit design EWS 1  examines whether or not there is an item equivalent to the inspection item of the acceptance inspection to be executed among the inspection items in the logical validation. If the equivalent item is included, the inspection result of that item is written to the check sheet  4  (Step S 69 ). Such representation can protect the same inspection from being doubly executed, which can reduce the number of steps in the circuit designer. After that, the circuit design EWS 1  checks the acceptance inspection items noted in the check sheet  4  (Step S 70 ), and additionally writes the inspection result to the check sheet  4 .  
         [0082]    If there is a rejected item among the inspection items noted in the check sheet  4 , the logical design is again carried out. If there is no problem in all the items among the acceptance inspection items, the circuit design EWS 1  sends the check sheet  4  together with the design data such as the circuit connection information, the pattern and the like to the layout design EWS 2  (Step S 71 ).  
         [0083]    The layout design EWS 2  compares the execution inspection items noted in the check sheet  4  with the executed result, in response to the reception of the check sheet  4 . If there is an inspection item in which the executed result is not noted in the inspection items to be executed, it is judged as a non-execution, and it is returned back to the circuit designer, and the inspection of the non-execution item is requested (Step S 72 ). If there is a result unsuitable for the layout as the inspection result of the acceptance inspection, it is returned back to the circuit designer, and the improvement based on the re-design is requested (Step S 73 ). If the layout has no problem in all the inspection items, the inspection result together with the circuit feature and the circuit designer ID is written to the model development history database  7 .  
         [0084]    After that, the layout designer designs the layout (Step S 74 ). After the design of the layout, the back annotation is carried out (Step S 75 ). In the back annotation, it is confirmed whether or not the semiconductor integrated circuit carries out a desirably functional operation at a delay after the layout, and additionally writes its result to the model development history database  7 . If the result of the back annotation is NG, it is returned back to the circuit designer, and the improvement based on the re-design is requested. If the result of the back annotation is OK, the EB process is carried out (Step S 76 ).  
         [0085]    [0085]FIG. 11 shows another embodiment of the semiconductor designing system according to the present invention. A circuit design EWS 1  has a check sheet  4  and an inspection item database  6 . A layout design EWS 2  has a model development history database  7 . At this time, the check sheet  4  is different from the previous embodiment. A circuit feature and an inspection result are written thereto, or only an inspection item to be executed and its inspection result are written thereto.  
         [0086]    [0086]FIGS. 12, 13 show the operation of the semiconductor designing system according to another embodiment of the present invention. At first, the circuit designer inputs to the circuit design EWS 1  the circuit feature of the semiconductor integrated circuit to be designed (Step S 41 ). The circuit design EWS 1  retrieves an error when previously designing the semiconductor integrated circuit, on the basis of the model development history database  7  (Step S 42 ). The circuit design EWS 1  determines an inspection item to be executed at this time, in accordance with the retrieved inspection item (Step S 43 ).  
         [0087]    The circuit design EWS 1  writes to the check sheet  4  the circuit feature of the semiconductor integrated circuit and the inspection item to be executed (Step S 44 ), and displays the previous error content on the screen. The circuit designer designs the logical circuit while paying attention to the previous error content (Step S 45 ). If the design of the logical circuit is completed, a logical validation of the logical circuit is carried out (Step S 46 ). If any trouble is discovered in the logical validation, the logical design is again carried out.  
         [0088]    After the completion of the logical design, the circuit design EWS 1  checks the acceptance inspection item noted in the check sheet  4  (Step S 47 ). The inspection result is additionally written to the check sheet  4 . If there is a rejected item among the inspection items noted in the check sheet  4 , the logical design is again carried out. If there is no problem in all the items among the acceptance inspection items, the circuit designer inputs a circuit designer ID to the circuit design EWS 1  (Step S 48 ). The circuit design EWS 1  sends the input circuit designer ID through the network  3  to the layout design EWS 2 .  
         [0089]    The layout design EWS 2  judges an allowance or rejection of an access in accordance with the circuit designer ID (Step S 49 ). If it is judged that there is no problem in the circuit designer ID, the access is allowed, and the layout EWS 2  reports its fact to the circuit design EWS 1 . In the circuit designer, if the access is allowed, the circuit design EWS 1  sends to the circuit design EWS 2  the check sheet  4  together with the design data, such as the circuit connection information, the pattern and the like (Step S 50 ).  
         [0090]    The layout design EWS 2  compares the execution inspection items noted in the check sheet  4  with the executed result, in response to the reception of the check sheet  4  (Step S 51 ). If there is an inspection item in which the executed result is not noted in the inspection items to be executed, it is judged as a non-execution, and it is returned back to the circuit designer, and the inspection of the non-execution item is requested. If there is a result unsuitable for the layout as the result of the acceptance inspection, it is returned back to the circuit designer, and the improvement based on the re-design is requested (Step S 52 ). If the layout has no problem in all the inspection items, the inspection result together with the circuit feature and the circuit designer ID is written to the model development history database  7 .  
         [0091]    After that, the layout designer designs the layout (Step S 53 ). After the design of the layout, the back annotation is carried out (Step S 54 ). In the back annotation, it is confirmed whether or not the semiconductor integrated circuit carries out a desirably functional operation at a delay after the layout, and additionally writes its result to the model development history database  7 . If the result of the back annotation is NG, it is returned back to the circuit designer, and the improvement based on the re-design is requested. If the result of the back annotation is OK, the EB process is carried out (Step S 55 ).  
         [0092]    Such a semiconductor circuit designing system can clarify the inspection item to be executed without any intervention of the network  3  by the circuit design EWS 1 . In the logical design in which the previous error is not displayed and the inspection item is not exempted, a communication between the circuit design EWS 1  and the layout design EWS 2  is small and efficient. By the way, the inspection item database may be simultaneously installed in both the circuit design EWS 1  and the layout design EWS 2 . In this case, the semiconductor circuit designing system is operated as shown in FIGS. 12, 13, similarly to this embodiment.  
         [0093]    Another embodiment of the semiconductor designing system according to the present invention has a plurality of layout designs EWS. As shown in FIG. 14, a layout design EWS 2  belongs to a layout designer A, and a layout design EWS 2 ′ belongs to a layout designer B. The semiconductor designing system according to another embodiment of the present invention further includes a data center  8 . The data center  8  is connected to the network  3 , and it has a inspection item database  6  and a model development history database  7 .  
         [0094]    The circuit EWS 1  obtains the data of the inspection item database  6  through the network  3  from the data center  8 . The layout EWS 2  obtains the data of the inspection item database  6  or the model development history database  7  through the network  3  from the data center  8 . The layout EWS 2  further updates the data of the model development history database  7  through the network  3 .  
         [0095]    If each of the plurality of layouts EWS has the inspection item database  6  and the model development history database  7 , the database is managed by each layout EWS 2 , and the database is updated by each layout EWS 2 . In the semiconductor designing system according to another embodiment of the present invention, the inspection item database  6  or the model development history database  7  is unitarily managed. It is easy to update the inspection item database  6  or the model development history database  7 .  
         [0096]    By the way, a layout EWS 2  that is a part of the plurality of layouts EWS 2  may also hold the function of the data center without separately installing the data center  8 .  
         [0097]    The semiconductor circuit designing apparatus and the semiconductor circuit designing method according to the present invention can avoid the occurrence of the problem in the later step in advance by providing the inspection items in the acceptance inspection to the circuit designer.  
         [0098]    The present application claims priority under 35 U.S.C. § 119 to Japanese Patent Application No. 2000-354306, filed at day of Nov. 21, 2000, entitled “A semiconductor circuit designing apparatus and a semiconductor circuit designing method”. The contents of that application are incorporated herein by reference in their entirety.