Abstract:
A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the top interconnection metal layer. The semiconductor chip also includes at least an interconnection metal layer, at least a second via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor substrate.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     This is a continuation application of U.S. patent application Ser. No. 10/904,431, filed Nov. 10, 2004. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to the field of semiconductor integrated circuits, and more particularly, to a semiconductor chip capable of implementing wire bonding over active circuits (also referred to as “BOAC”).  
         [0004]     2. Description of the Prior Art  
         [0005]     Accompanying progress of the semiconductor technology, critical dimensions of integrated circuits are continually shrunk. Therefore, bonding pads which spread around on a chip are obstacles for reducing the chip size. For this reason, implementing wire bonding over active circuits is a trend for chips design and manufacturing.  
         [0006]      FIG. 1  is a schematic cross-sectional diagram of a BOAC integrated circuit structure according to the prior art. As shown in  FIG. 1 , a BOAC integrated circuit structure  10  of the prior art has a plurality of active circuits on a semiconductor substrate  12 . The plurality of active circuits include input/output (I/O) devices/circuits or electrostatic discharge (ESD) devices/circuits, and are made up of metal-oxide-semiconductor field-effect transistors (MOSFET)  14 ,  16 , and  18 , shallow trench isolations (STI)  20  and  22 , ion diffusion regions  24 ,  26 ,  28 , and  30 , an inter-layer dielectric (ILD)  32 , inter-metal dielectrics (IMD)  34 ,  36  and  38 , and interconnection metal layers  40 ,  42 ,  44 ,  46 ,  48 ,  50 , and  52 . A portion of the surface of the top interconnection metal layer  52  is covered by a barrier layer  54 , a protection layer  56 , and a bondable metal pad  58 .  
         [0007]     According to  FIG. 1 , in the BOAC integrated circuit structure  10  of the prior art, the top interconnection metal layer  52  is set over the covering region of the bondable metal pad  58  and electrically links with lower active circuits formed underneath through an outside wire. Therefore, mechanical stresses press on the bondable metal pad  58  directly during bonding, and bonds between the bondable metal pad  58 , the barrier layer  54 , and the top interconnection metal layer  52  and the lower integrated circuits are destroyed. Moreover, the outside wire, which is formed for electrically linking the top interconnection metal layer  52  and the lower active circuits, is unfavorable for chip size shrinkage.  
       SUMMARY OF THE INVENTION  
       [0008]     It is therefore a primary objective of the present invention to provide a BOAC integrated circuit structure which disposes at least a first via plug linking a bondable metal pad with a top interconnection metal layer and at least a second via plug linking a bonding pad structure with an interconnection metal layer beneath the bondable metal pad.  
         [0009]     According to the objective of the present invention, a BOAC integrated circuit structure of the present invention includes a bonding pad structure. The bonding pad structure includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric located between the bondable metal pad and the top interconnection metal layer, and at least a first via plug disposed beneath the bondable metal pad in a stress-buffering dielectric for electrically linking the bondable metal pad with the top interconnection metal layer. Moreover, the BOAC integrated circuit structure further includes at least an interconnection metal layer, at least a second via plug disposed beneath the bonding pad structure for electrically linking the bonding pad structure with the interconnection metal layer, and an active circuit disposed beneath the bonding pad structure on a semiconductor substrate.  
         [0010]     Since the BOAC integrated circuit structure of the present invention further includes the stress-buffering dielectric between the bondable metal pad and the top interconnection metal layer, mechanical stresses pressing on the top interconnection metal layer directly during bonding will be reduced. Additionally, the integrated circuit will not be damaged. In the present invention, since the first via plug linking the bondable metal pad with the top interconnection metal layer and the second via plug linking the bonding pad structure with the interconnection metal layer beneath the bondable metal pad are disposed beneath the bondable metal pad, the wiring area will be diminished and the chip size will be shrunk. Moreover, since the wire between the bondable metal pad and the lower active circuit of the present invention is shorter, the electric characteristics will be better.  
         [0011]     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]      FIG. 1  is a schematic cross-sectional diagram of a BOAC integrated circuit structure according to the prior art.  
         [0013]      FIG. 2  is a schematic cross-sectional diagram of a BOAC integrated circuit structure according to a first embodiment of the present invention.  
         [0014]      FIG. 3  is a schematic cross-sectional diagram of a BOAC integrated circuit structure according to a second embodiment of the present invention.  
         [0015]      FIG. 4  is a top view of the metal frame according to the second embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0016]     Please refer to  FIG. 2 .  FIG. 2  is a schematic cross-sectional diagram of a BOAC integrated circuit structure according to a first embodiment of the present invention. As shown in  FIG. 2 , a BOAC integrated circuit structure  60  of the present invention includes a bonding pad structure  62  and an active circuit region  64 . The bonding pad structure  62  further includes a bondable metal pad  66 , a top interconnection metal layer  68 , first via plugs  70  and  72  located beneath a section of the bondable metal pad  66  that is covered by a protection layer  74  and electrically linking the bondable metal pad  66  with the top interconnection metal layer  68 , and a stress-buffering dielectric  76  located between the bondable metal pad  66  and the top interconnection metal layer  68 .  
         [0017]     The active circuit region  64  may include input/output (I/O) devices/circuits or electrostatic discharge (ESD) devices/circuits on a semiconductor substrate  77 , and are made up of metal-oxide-semiconductor field-effect transistors (MOSFET)  78 ,  80 , and  82 , shallow trench isolations (STI)  84  and  86 , ion diffusion regions  88 ,  90 ,  92 ,  94 , and  96 , an inter-layer dielectric (ILD)  98 , inter-metal dielectrics (IMD)  100 ,  102 ,  104  and  106 , and interconnection metal layers  108 ,  110 ,  112 ,  114 ,  116 ,  118 , and  120 . For the sake of simplicity, an integrated circuit having five levels of metal interconnections is taken as an example and is illustrated in  FIG. 2 . However, a person skilled in the art will appreciate that the number of metal interconnections should not be limited thereto. For example, the present invention can also be applied in integrated circuits with six, seven, or even higher levels of metal interconnections.  
         [0018]     As shown in  FIG. 2 , the interconnection metal layers  108  and  110  are defined in the inter-layer dielectric  98  and electrically link with the metal-oxide-semiconductor field-effect transistors (MOSFET)  78 ,  80 , and  82 , the shallow trench isolations (STI)  84  and  86 , the ion diffusion regions  88 ,  90 ,  92 ,  94 , and  96  by a contact plug  121 . The inter-layer dielectric  98  is silicon oxide (SiO2), fluoride silicate glass (FSG), or other low dielectric constant materials. According to the first embodiment of the present invention, the top interconnection metal layer  68 , the interconnection metal layers  108 ,  110 ,  112 ,  114 ,  116 ,  118 , and  120  are interconnection copper metal layers and are manufactured by a standard copper damascene process or dual damascene process.  
         [0019]     As shown in  FIG. 2 , the interconnection metal layers  112 ,  114 , and  116  are defined in the inter-metal dielectric  100  by a copper damascene process, and a via plug  122 , which electrically links the interconnection metal layer  108  with the interconnection metal layer  112 , and the interconnection metal layers  112  are made by a copper damascene process simultaneously in the inter-metal dielectric  100 . The inter-metal dielectric  100  is formed by low dielectric constant materials or ultra-low dielectric constant materials. Here, the said ultra-low dielectric constant materials are dielectrics having a dielectric constant less than 2.5, and the structure is usually porous and fragile. The interconnection metal layers  118  is defined in the inter-metal dielectric  102  by a copper damascene process, and a via plug  124 , which electrically links the interconnection metal layer  114  with the interconnection metal layer  118 , is made by a copper damascene process in the inter-metal dielectric  102 . The inter-metal dielectric  102  is formed by low dielectric constant materials. The interconnection metal layer  120  is defined in the inter-metal dielectric  104  by a copper damascene process, and via plugs  126 ,  128 , and  130  which electrically link the interconnection metal layer  118  with the interconnection metal layer  120 , are made by a copper damascene process in the inter-metal dielectric  104 . The inter-metal dielectric  104  is formed by low dielectric constant materials. The top interconnection metal layer  68  is defined in the inter-metal dielectric  106  by a copper damascene process. A plurality of second via plugs  132 ,  134 , and  136 , located beneath a section of the bondable metal pad  66  that is covered by the protection layer  74 , electrically link the top interconnection metal layer  74  with the interconnection metal layer  120  and are defined in the inter-metal dielectric  106  by a copper damascene process. The inter-metal dielectric  106  is formed by low dielectric constant materials.  
         [0020]     The bondable metal pad  66  is covered on the stress-buffering dielectric  76 , and the first via plugs  70  and  72  electrically linking the top interconnection metal layer  68  with the bondable metal pad  66  are defined in the stress-buffering dielectric  76 . Since the stress-buffering dielectric  76  is made of silicon oxide or other less porous and denser dielectric materials, the stress-buffering dielectric  76  is denser than each inter-metal dielectric and is able to absorb the stress generated during bonding. As above, in the first embodiment of the present invention, the bondable metal pad  66  and the first via plugs  70  and  72  are made of aluminum and are formed by a traditional aluminum wiring process. The protection layer  74  on the top of the BOAC integrated circuit structure  60  is silicon nitride (SiN), polyimide, or other protection materials that have the same utility. The protection layer  74  further includes bonding opening exposing a portion of the top surface of the bondable metal pad  66  to form a bonding window region  138 .  
         [0021]      FIG. 3  is a schematic cross-sectional diagram of a BOAC integrated circuit structure according to a second embodiment of the present invention. As shown in  FIG. 3 , the first via plugs  70  and  72  linking the bondable metal pad  66  with the top interconnection metal layer  68  can be equally disposed beneath the bonding window region  138  in the stress-buffering layer  76  depending on the size of the bonding window region  138 . Moreover, the region beneath the bonding window region  138  may further include a metal frame  140  made of copper in any inter-metal dielectric under the top interconnection metal layer  68  such as the inter-metal dielectric  104 . The metal frame  140  serves as a reinforcement supporting structure. During bonding, a part of the mechanical stress exerted on the bondable metal pad  66  is absorbed by the stress-buffering dielectric layer  76  and is offset by the metal frame  140 .  FIG. 4  is a top view of the metal frame  140  according to the second embodiment of the present invention. As shown in  FIG. 4 , the metal frame  140  is located in the inter-metal dielectric  104 .  
         [0022]     In comparison with the prior art, in the present invention, since the first via plug linking the bondable metal pad with the top interconnection metal layer and the second via plug linking the bonding pad structure with the interconnection metal layer are disposed beneath the bondable metal pad, the wiring area will be diminished and the chip size will be shrunk. Moreover, since the BOAC integrated circuit structure of the present invention further includes the stress-buffering dielectric between the bondable metal pad and the top interconnection metal layer, mechanical stresses pressing on the top interconnection metal layer directly during bonding will be reduced. Additionally, the integrated circuit will not be damaged. The present further includes the metal frame serving as a reinforcement supporting structure. Since the wire between the bondable metal pad and the lower active circuit of the present invention is shorter, the electric characteristics will be better.  
         [0023]     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.