Abstract:
A memory cell with a charge storage structure is read by measuring current between the substrate region of the memory cell and one of the current carrying nodes of the memory cell. The read operation decreases the coupling between different parts of the charge storage structure when other parts of the charge storage structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation. Example arrangements are a series of memory cells, and an array of series of memory cells.

Description:
RELATED APPLICATIONS  
       [0001]     The present application is related to U.S. patent application Ser. No. ______, filed ______ (MXIC 1632-2); U.S. patent application Ser. No. ______, filed ______ (MXIC 1633-1); and U.S. patent application Ser. No. ______, filed ______ (MXIC 1634-1). The present application is a continuation-in-part of U.S. patent application Ser. No. 10/973,593 filed 26 Oct. 2004 (MXIC 1609-2) and U.S. patent application Ser. No. 10/973,176 filed 26 Oct. 2004 (MXIC 1608-2), which claim the benefit of U.S. Provisional Application No. 60/608,455 filed 9 Sep. 2004 (MXIC 1609-1) and U.S. Provisional Application No. 60/608,528 filed 9 Sep. 2004 (MXIC 1608-1). All these applications are incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to electrically programmable and erasable non-volatile memory, and more particularly to charge storage memory with a bias arrangement that reads the contents of the charge storage structure of the memory cell with great sensitivity.  
         [0004]     2. Description of Related Art  
         [0005]     Electrically programmable and erasable non-volatile memory technologies based on charge storage structures known as EEPROM and flash memory are used in a variety of modern applications. A number of memory cell structures are used for EEPROM and flash memory. As the dimensions of integrated circuits shrink, greater interest is arising for memory cell structures based on charge trapping dielectric layers, because of the scalability and simplicity of the manufacturing processes. Various memory cell structures based on charge trapping dielectric layers include structures known by the industry names PHINES, NROM, and SONOS, for example. These memory cell structures store data by trapping charge in a charge trapping dielectric layer, such as silicon nitride. As more net negative charge is trapped, the threshold voltage of the memory cell increases. The threshold voltage of the memory cell is reduced by removing negative charge from, or adding positive charge to, the charge trapping layer.  
         [0006]     Conventional memory cell structures rely on the reverse read operation to determine the contents of the memory structure. However, the reverse read technique effectively couples together multiple locations of the charge trapping structure, even when only a portion of the charge trapping structure contains data of interest. This dependence constrains the utility of using the charge trapping structure as nonvolatile memory, by narrowing the sensing window of currents measured from the reverse read technique. Less data are stored in the charge trapping structure than otherwise possible.  
         [0007]     Power consumption is another area of potential improvement. Portable electronic devices such as music players, cell phones, and wireless devices, have a limited source of power available. The reverse read operation is a source of power drain contributing to power consumption. Similarly, such power consumption occurs in read operations that rely on contrasting levels of lateral current flow through a channel formed in the memory cell.  
         [0008]     Thus, a need exists for a nonvolatile memory cell that can be read without suffering substantial coupling between multiple locations of the charge storage structure, even when only a portion of the charge storage structure contains data of interest. Alternately, a need exists for a read operation that reduces power consumption, compared to the reverse read operation.  
       SUMMARY OF THE INVENTION  
       [0009]     A method of operating a nonvolatile memory array, an architecture for an integrated circuit including such a memory array, and an architecture for an integrated circuit including a column nonvolatile memory cells, are disclosed.  
         [0010]     A nonvolatile memory integrated circuit includes a nonvolatile memory array storing data as charge storage states, bit lines, and word lines providing gate voltage. The nonvolatile memory array includes columns of memory cells. Each memory cell has a substrate region including first and second current carrying nodes, a charge storage structure, and one or more dielectric structures. The dielectric structure is positioned about the charge storage structure, such that the dielectric structure is interposed somewhere between the charge storage structure and the substrate region, and somewhere between the charge storage structure and the source of gate voltage.  
         [0011]     The bit lines each have a corresponding column of memory cells, such that a particular bit line is used to access data on the corresponding column of memory cells. During some memory operation, a bit line is electrically connected to the first end of the corresponding column of memory cells. During some memory operation, the same bit line is electrically connected to the second end of the corresponding column of memory cells. For example, during a program operation, the same bit line is electrically connected to the first end and the second end of the corresponding column. In another example, during a read operation, the same bit line is electrically connected to the first end and the second end of the corresponding column. The read operation can be performed to determine at least one of the charge storage states by measuring a band-to-band current component.  
         [0012]     In some embodiments additional memory operations are performed on the nonvolatile memory array. During these additional memory operations, a bit line is electrically connected to the first end of the corresponding column of nonvolatile memory cells, and the second end of the same column of nonvolatile memory cells floats.  
         [0013]     In some embodiments, the substrate region is a well in a semiconductor substrate. In other embodiments, the substrate region is simply the semiconductor substrate.  
         [0014]     Other embodiments of the technology described above include a method for operating the nonvolatile memory array, and a column of the nonvolatile memory according to the described technology.  
         [0015]     Some embodiments include first pass transistors and second pass transistors. During some memory operation, a bit line is electrically connected to the first end of the corresponding column of memory cells via a first pass transistor. During some memory operation, the same bit line is electrically connected to the second end of the corresponding column of memory cells via a second pass transistor.  
         [0016]     In one embodiment, the nonvolatile memory cell has a split gate design, and includes a second gate. In memory operations, the different gates each apply a potential to the substrate region. With this split gate design, the logic applies erase and programming bias arrangements to change the charge storage state by injecting electrons into and ejecting electrons from corresponding parts of the charge storage structures.  
         [0017]     In other embodiments, the nonvolatile memory cell has a floating gate design or a nanocrystal design. With this floating gate design or nanocrystal design, the logic applies erase and programming bias arrangements to change the charge storage state by injecting electrons into and ejecting electrons from corresponding parts of the charge storage structures.  
         [0018]     In another embodiments, the nonvolatile memory cell has a charge trapping material design. With this charge trapping material design, the logic applies erase and programming bias arrangements to change the charge storage state by injecting electrons into and injection holes into corresponding parts of the charge storage structures.  
         [0019]     During a read operation, the measured current flowing between the first current carrying node and/or the second current carrying node, and the substrate region, includes a band-to-band tunneling current, flowing between the substrate region and at least one of the first current carrying node and/or the second current carrying node to determine the charge storage state. To induce the measured current flowing between the first current carrying node and/or the second current carrying node, and the substrate region, the read bias arrangement causes a first voltage difference between the gate and the first current carrying node and/or the second current carrying node, and a second voltage difference between the first current carrying node and/or the second current carrying node and the substrate region.  
         [0020]     Because the read operation does not require a current to flow between the first and second current carrying nodes of the measured nonvolatile memory cells, the read bias arrangement allows for one region of the first and second current carrying regions to be floated, while the other region of the first and second current carrying regions is biased to have a voltage difference with the substrate region.  
         [0021]     The measured current flowing between the first and/or second current carrying regions, and the substrate region, includes a band-to-band tunneling current, flowing between the substrate region and at least one of the first and second current carrying regions to determine the charge storage state. To induce the measured current flowing between the first and/or second current carrying regions, and the substrate region, the read bias arrangement causes a first voltage difference between the gate and the first and/or second current carrying regions, and a second voltage difference between the first and/or second current carrying regions and the substrate region.  
         [0022]     The voltage difference between the gate and at least one of the first and second current carrying regions creates an electric field which causes band bending in the same region(s). The degree of band bending is affected by the charge storage state of the charge trapping structure, resulting in a band-to-band tunneling current in at least one of the first and second current carrying regions that varies with the charge storage state. In some embodiments, the bias arrangement applies a reverse bias voltage difference between the substrate region and the first or second current carrying regions, and floats the other of the first or second current carrying region.  
         [0023]     In some embodiments, the substrate region is a well in a semiconductor substrate. In other embodiments, the substrate region is simply the semiconductor substrate.  
         [0024]     Other embodiments of the technology described above include a column of nonvolatile memory cells according to the described technology, and a method of operating the column.  
         [0025]     Other aspects and advantages of the technology presented herein can be understood with reference to the figures, the detailed description and the claims, which follow.  
         [0026]     Various embodiments include memory cells with an n-type channel, memory cells with a p-type channel, or memory cells with an n-type channel and memory cells with a p-type channel. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0027]      FIG. 1A  is a simplified diagram of a charge trapping memory cell, showing a read operation being performed on the portion of the charge trapping structure corresponding to the source side.  
         [0028]      FIG. 1B  is a simplified diagram of a charge trapping memory cell, showing a read operation being performed on the portion of the charge trapping structure corresponding to the drain side.  
         [0029]      FIG. 2A  is a graph showing the sensing window of a typical nonvolatile memory cell.  
         [0030]      FIG. 2B  is a graph showing the sensing window of a memory cell as a program operation is performed on different parts of the charge trapping structure of the memory cell.  
         [0031]      FIG. 3A  is a simplified diagram of a charge trapping memory cell, showing channel hot electron injection being performed on one portion of the charge trapping structure.  
         [0032]      FIG. 3B  is a simplified diagram of a charge trapping memory cell, showing channel hot electron injection being performed on another portion of the charge trapping structure.  
         [0033]      FIG. 4A  is a simplified diagram of a charge trapping memory cell, showing band to band hot hole injection being performed on one portion of the charge trapping structure.  
         [0034]      FIG. 4B  is a simplified diagram of a charge trapping memory cell, showing band to band hot hole injection being performed on another portion of the charge trapping structure.  
         [0035]      FIG. 5  is a diagram of an erase operation via one bias arrangement being performed on a column of nonvolatile memory cells interconnected in a NOR arrangement.  
         [0036]      FIG. 6  is a diagram of an erase operation via another bias arrangement being performed on a column of nonvolatile memory cells interconnected in a NOR arrangement.  
         [0037]      FIG. 7A  is a simplified diagram of a charge trapping memory cell, showing an erase operation being performed on the charge trapping structure, corresponding to  FIG. 5 .  
         [0038]      FIG. 7B  is a simplified diagram of a charge trapping memory cell, showing an erase operation being performed on the charge trapping structure, corresponding to  FIG. 6 .  
         [0039]      FIG. 8  is a diagram of a program operation being performed on a column of nonvolatile memory cells interconnected in a NOR arrangement, adding holes to one part of a memory cell.  
         [0040]      FIG. 9  is a diagram of a program operation being performed on a column of nonvolatile memory cells interconnected in a NOR arrangement, adding holes to another part of a memory cell.  
         [0041]      FIG. 10  is a diagram of a read operation being performed on a column of nonvolatile memory cells interconnected in a NOR arrangement, reading one part of a memory cell.  
         [0042]      FIG. 11  is a diagram of a read operation being performed on a column of nonvolatile memory cells interconnected in a NOR arrangement, reading another part of a memory cell.  
         [0043]      FIG. 12  is a diagram of an erase operation via one bias arrangement being performed on nonvolatile memory cells interconnected in a virtual ground array arrangement.  
         [0044]      FIG. 13  is a diagram of an erase operation via another bias arrangement being performed on nonvolatile memory cells interconnected in a virtual ground array arrangement.  
         [0045]      FIG. 14  is a diagram of a program operation being performed on a virtual ground array arrangement of nonvolatile memory cells, adding holes to a part of the virtual ground array.  
         [0046]      FIG. 15  is a diagram of a read operation being performed on a virtual ground array arrangement of nonvolatile memory cells.  
         [0047]      FIG. 16  is a diagram of an erase operation via one bias arrangement being performed on an array of nonvolatile memory cells interconnected as columns of cells arranged in series.  
         [0048]      FIG. 17  is a diagram of an erase operation via another bias arrangement being performed on an array of nonvolatile memory cells interconnected as columns of cells arranged in series.  
         [0049]      FIG. 18  is a diagram of an erase operation via one bias arrangement being performed on an array of nonvolatile memory cells interconnected as columns of cells arranged in series with a floating end.  
         [0050]      FIG. 19  is a diagram of an erase operation via another bias arrangement being performed on an array of nonvolatile memory cells interconnected as columns of cells arranged in series with a floating end.  
         [0051]      FIG. 20  is a diagram of a program operation being performed on an array of nonvolatile memory cells interconnected as columns of cells arranged in series.  
         [0052]      FIG. 21  is a diagram of a program operation being performed on an array of nonvolatile memory cells interconnected as columns of cells arranged in series with a floating end.  
         [0053]      FIG. 22  is a diagram of a read operation being performed on an array of nonvolatile memory cells interconnected as columns of cells arranged in series, via one end of the series.  
         [0054]      FIG. 23  is a diagram of a read operation being performed on an array of nonvolatile memory cells interconnected as columns of cells arranged in series, via another end of the series.  
         [0055]      FIG. 24  is a diagram of a read operation being performed on an array of nonvolatile memory cells interconnected as columns of cells arranged in series, via both ends of the series.  
         [0056]      FIG. 25  is a diagram of a read operation being performed on an array of nonvolatile memory cells interconnected as columns of cells arranged in series with a floating end.  
         [0057]      FIG. 26  is a diagram of an erase operation via one bias arrangement being performed on nonvolatile memory cells interconnected as a column of cells arranged in series.  
         [0058]      FIG. 27  is a diagram of an erase operation via another bias arrangement being performed on nonvolatile memory cells interconnected as a column of cells arranged in series.  
         [0059]      FIG. 28  is a diagram of an erase operation via one bias arrangement being performed on nonvolatile memory cells interconnected as a column of cells arranged in series with a floating end.  
         [0060]      FIG. 29  is a diagram of an erase operation via another bias arrangement being performed on nonvolatile memory cells interconnected as a column of cells arranged in series with a floating end.  
         [0061]      FIG. 30  is a diagram of a program operation being performed on nonvolatile memory cells interconnected as a column of cells arranged in series.  
         [0062]      FIG. 31  is a diagram of a program operation being performed on nonvolatile memory cells interconnected as a column of cells arranged in series with a floating end.  
         [0063]      FIG. 32  is a diagram of a read operation being performed on nonvolatile memory cells interconnected as a column of cells arranged in series, via one end of the series.  
         [0064]      FIG. 33  is a diagram of a read operation being performed on nonvolatile memory cells interconnected as a column of cells arranged in series, via another end of the series.  
         [0065]      FIG. 34  is a diagram of a read operation being performed on nonvolatile memory cells interconnected as a column of cells arranged in series, via both ends of the series.  
         [0066]      FIG. 35  is a diagram of a read operation being performed on nonvolatile memory cells interconnected as a column of cells arranged in series with a floating end.  
         [0067]      FIGS. 36A-36C  are simplified diagrams of other nonvolatile memory cells with various charge storage structures.  
         [0068]      FIG. 37  is a simplified diagram of an integrated circuit with an array of charge trapping memory cells and control circuitry. 
     
    
     DETAILED DESCRIPTION  
       [0069]      FIG. 1A  is a simplified diagram of a charge trapping memory cell, showing a read operation being performed on the portion of the charge trapping structure corresponding to the source side. The p-doped substrate region  170  includes n+ doped source and drain regions  150  and  160 . The remainder of the memory cell includes a bottom dielectric structure  140  on the substrate, a charge trapping structure  130  on the bottom dielectric structure  140  (bottom oxide), a top dielectric structure  120  (top oxide) on the charge trapping structure  130 , and a gate  110  on the oxide structure  120 . Representative top dielectrics include silicon dioxide and silicon oxynitride having a thickness of about 5 to 10 nanometers, or other similar high dielectric constant materials including for example Al 2 O 3 . Representative bottom dielectrics include silicon dioxide and silicon oxynitride having a thickness of about 3 to 10 nanometers, or other similar high dielectric constant materials. Representative charge trapping structures include silicon nitride having a thickness of about 3 to 9 nanometers, or other similar high dielectric constant materials, including metal oxides such as Al 2 O 3 , HfO 2 , and others.  
         [0070]     The memory cell for SONOS-like cells has, for example, a bottom oxide with a thickness ranging from 2 nanometers to 10 nanometers, a charge trapping layer with a thickness ranging from 2 nanometers to 10 nanometers, and a top oxide with a thickness ranging from 2 nanometers to 15 nanometers. Other charge trapping memory cells are PHINES and NROM.  
         [0071]     In some embodiments, the gate comprises a material having a work function greater than the intrinsic work function of n-type silicon, or greater than about 4.1 eV, and preferably greater than about 4.25 eV, including for example greater than about 5 eV. Representative gate materials include p-type poly, TiN, Pt, and other high work function metals and materials. Other materials having a relatively high work function suitable for embodiments of the technology include metals including but not limited to Ru, Ir, Ni, and Co, metal alloys including but not limited to Ru—Ti and Ni—T, metal nitrides, and metal oxides including but not limited to RuO 2 . High work function gate materials result in higher injection barriers for electron tunneling than that of the typical n-type polysilicon gate. The injection barrier for n-type polysilicon gates with silicon dioxide as the top dielectric is around 3.15 eV. Thus, embodiments of the present technology use materials for the gate and for the top dielectric having an injection barrier higher than about 3.15 eV, such as higher than about 3.4 eV, and preferably higher than about 4 eV. For p-type polysilicon gates with silicon dioxide top dielectrics, the injection barrier is about 4.25 eV, and the resulting threshold of a converged cell is reduced about 2 volts relative to a cell having an n-type polysilicon gate with a silicon dioxide top dielectric.  
         [0072]     In the diagram of  FIG. 1A , the source side of the memory cell stores added electrons, for example via a channel reset operation injecting electrons via Fowler-Nordheim tunneling from the gate  110  or the substrate  170 , or some other charge movement process such as channel hot electron injection or channel initiated secondary electron injection. The drain side of the memory cell stores added holes, for example via band-to-band hole injection into the drain side of the charge trapping structure  130 .  
         [0073]     In the bias arrangement of  FIG. 1A  for reading the source side of the charge trapping structure  130 , the voltage of the gate  110  is −10 V, the voltage of the source  150  is 2 V, the voltage of the drain  160  is floating, and the voltage of the substrate  170  is 0 V. The memory cell of  FIG. 11B  is similar to memory cell of  FIG. 1A , except that a read operation is being performed on the drain side of the charge trapping structure rather than on the source side. In the bias arrangement of  FIG. 1B  for reading the drain side of the charge trapping structure  130 , the voltage of the gate  110  is −10 V, the voltage of the source  150  is floating, the voltage of the drain  160  is 2 V, and the voltage of the substrate  170  is 0 V. The bias arrangement is determined among the various terminals, such that the energy bands bend sufficiently to cause band-to-band current in the n+ doped source  150  ( FIG. 1A ) or the n+ doped drain  160  ( FIG. 1B ), but to keep the potential difference between the substrate  170  and the source  150  ( FIG. 1A ) or the drain  160  ( FIG. 1B ) low enough such that programming or erasing does not occur, as discussed in connection with  FIGS. 3A, 3B ,  4 A,  4 B,  7 A, and  7 B.  
         [0074]     In this bias arrangements of  FIGS. 1A and 1B , the area of the junction between the p doped substrate  170 , and either the n+ doped source  150  or the n+ doped drain  160 , displays the behavior of a reverse biased p-n junction. However, the gate voltage causes the energy bands to bend sufficiently such that band-to-band tunneling occurs through the n+ doped source  150  ( FIG. 1A ) or the n+ doped drain  160  ( FIG. 1 ). The high doping concentration in the source  150  or the drain  160 , the resulting high charge density of the space charge region, and the accompanying short length of the space charge region over which the voltage changes, contribute to the sharp energy band bending. Electrons in the valence band tunnel through the forbidden gap to the conduction band and drift down the potential hill, deeper into either the n+ doped source  150  ( FIG. 1A ) or the n+ doped drain  160  ( FIG. 1B ). Similarly, holes drift up the potential hill, away from either the n+ doped source  150  ( FIG. 1A ) or the n+ doped drain  160  ( FIG. 1B ), and toward the p doped substrate  170 .  
         [0075]     The voltage of the gate  110  controls the voltage of the portion of the substrate  170  by the bottom dielectric structure  140  (bottom oxide). In turn, the voltage of the portion of the substrate  170  by the bottom dielectric structure  140  (bottom oxide) controls the degree of band bending between the bottom dielectric structure  140  (bottom oxide), and either the n+ doped source  150  ( FIG. 1A ) or the n+ doped drain  160  ( FIG. 1B ). As the voltage of the gate  110  becomes more negative, the voltage of the portion of the substrate  170  by the bottom dielectric structure  140  (bottom oxide) becomes more negative, resulting in deeper band bending in either the n+ doped source  150  ( FIG. 1A ) or the n+ doped drain  160  ( FIG. 1B ). More band-to-band current flows, as a result of at least some combination of 1) an increasing overlap between occupied electron energy levels on one side of the bending energy bands, and unoccupied electron energy levels on the other side of bending energy bands, and 2) a narrower barrier width between the occupied electron energy levels and the unoccupied electron energy levels (Sze,  Physics of Semiconductor Devices,  1981).  
         [0076]     As mentioned above, the drain side of the charge trapping structure  130  is occupied by relatively more holes, whereas the source side of the charge trapping structure  130  is occupied by relatively more electrons than the drain side of the charge trapping structure  130 . As a result, in accordance with Gauss&#39;s Law, when −10 V is applied to the gate  110 , the bottom dielectric structure  140  (bottom oxide) is biased more negatively on the source side than on the drain side. Thus, more current flows between the source  150  and the substrate  170  in the bias arrangement shown in  FIG. 1A  for reading the source side of the charge trapping structure  130  than flows between the drain  160  and the substrate  170  in the bias arrangement shown in  FIG. 1B  for reading the drain side of the charge trapping structure  130 .  
         [0077]     The difference in the bias arrangements of  FIGS. 1A and 1B  for reading, and the bias arrangement of  FIGS. 3A, 3B ,  4 A, and  4 B for programming and erasing, show a careful balance. For reading, the potential difference between the source region and the drain region should not cause a substantial number of carriers to transit the tunnel oxide and affect the charge storage state. In contrast, for programming and erasing, the potential difference between the source region and the drain region is sufficient to cause a substantial number of carriers to transit the tunnel oxide and affect the charge storage state.  
         [0078]      FIG. 2A  is a graph showing the sensing window of a typical nonvolatile memory cell. In  FIG. 2A , the memory cell read by a reverse read operation has a relatively narrow sensing window  250  due to the second bit effect. During the time interval  230 , as the first bit is undergoing programming, the read current curve of the first bit  210  increases from a lowest level  260  to a high level  264 . Consequently, the programming of the first bit during the time interval  230  substantially affects the read current curve of the second bit  220 , which increases from a lowest level  260  to a low level  262 . During the time interval  240 , as the second bit is undergoing programming, the read current curve of the second bit  220  increases from a low level  262  to a highest level  266 . Consequently, the programming of the second bit during the time interval  240  substantially affects the read current curve of the first bit  210 , which increases from a high level  264  to a highest level  266 . Thus, when performing a reverse read operation on a memory cell on one bit, the resulting read current is substantially affected by the programmed or erased status of the other bit, because for a given gate voltage it becomes more difficult during the reverse read operation to force the substrate portion under the other bit into depletion and inversion, and to punch through the portion of the substrate under the other bit.  
         [0079]      FIG. 2B  is a graph showing the sensing window of a memory cell as a program operation is performed on different parts of the charge trapping structure of the memory cell. In the graph of  FIG. 2B , the first and second charge trapping parts undergo programming. Curve  210  represents the read current of the first charge trapping part. Curve  220  represents the read current of the second charge trapping part. The sensing window  250  shown in  FIG. 2B  is relatively wide, because the band-to-band read operation is local to either the first terminal or the second terminal. The read current resulting from a band-to-band read operation performed on the first charge trapping part is relatively insensitive to the logical state of the second charge trapping part, and the read current resulting from a band-to-band read operation performed on the second charge trapping part is relatively insensitive to the logical state of the first charge trapping part. The band-to-band read operation is relatively free of the second charge trapping part effect which characterizes the reverse read operation, where the read current resulting from a read operation performed on one side of the charge trapping structure is relatively dependent on the data stored on the other side of the charge trapping structure.  
         [0080]     Each charge trapping part can store one bit or multiple bits. For example, if each charge trapping part stores two bits, then there are four discrete levels of charge.  
         [0081]      FIGS. 3A and 3B  are simplified diagrams of a charge trapping memory cell, showing channel hot electron injection being performed on different portions of the charge trapping structure. In the bias arrangement of  FIG. 3A  for adding electrons  134  to the source side of the charge trapping structure  130 , the voltage of the gate  110  is 10 V, the voltage of the source  150  is 5 V, the voltage of the drain  160  is 0 V, and the voltage of the substrate  170  is 0 V. The memory cell of  FIG. 3B  is similar to memory cell of  FIG. 3A , except that electrons  134  are added to the drain side of the charge trapping structure rather than on the source side. In the bias arrangement of  FIG. 3B , the voltage of the gate  110  is 10 V, the voltage of the source  150  is 0 V, the voltage of the drain  160  is 5 V, and the voltage of the substrate  170  is 0 V.  
         [0082]      FIGS. 4A and 4B  are simplified diagrams of a charge trapping memory cell, showing band to band hot hole injection being performed on different portions of the charge trapping structure. In the bias arrangement of  FIG. 4A  for adding holes  433  to the drain side of the charge trapping structure  130 , the voltage of the gate  110  is −6 V, the voltage of the source  150  is 0 V, the voltage of the drain  160  is 5 V, and the voltage of the substrate  170  is 0 V. The memory cell of  FIG. 4B  is similar to memory cell of  FIG. 4A , except that holes  433  are added to the drain side of the charge trapping structure rather than on the source side. In the bias arrangement of  FIG. 4B , the voltage of the gate  110  is −6 V, the voltage of the source  150  is 5 V, the voltage of the drain  160  is 0 V, and the voltage of the substrate  170  is 0 V. In the simplified diagrams of  FIGS. 4A and 4B , the stored charge  433  in the charge trapping structure, electrons are symbolically shown smaller than the holes to show that the injected holes have erased previously programmed holes.  
         [0083]     In some embodiments, programming refers to making more positive the net charge stored in the charge trapping structure, such as by the addition of holes to or the removal of electrons from the charge trapping; and erasing refers to making more negative the net charge stored in the charge trapping structure, such as by the removal of holes from or the addition of electrons to the charge trapping structure. However, in other embodiments programming refers to making the net charge stored in the charge trapping structure more negative, and erasing refers to making the net charge stored in the charge trapping structure more positive. Various charge movement mechanisms are sued, such as band-to-band tunneling induced hot carrier injection, E-field induced tunneling, channel hot carrier injection, channel initiated substrate carrier injection, and direct tunneling from the substrate.  
         [0084]      FIGS. 5 and 6  are diagrams of an erase operation being performed on a column of nonvolatile memory cells interconnected in a NOR arrangement. In the bias arrangement of  FIG. 5  for erasing the NOR memory column, the voltages of the word lines  510 ,  520 ,  530 , and  540  are −8 V; the voltage of the bit lines  504  and  506  are floating, and the voltage of the substrate  502  is 10 V. In the bias arrangement of  FIG. 6  for erasing the NOR memory column, the voltages of the word lines  510 ,  520 ,  530 , and  540  are 8 V; the voltage of the bit lines  504  and  506  are floating, and the voltage of the substrate  502  is −10 V. The bias arrangements of  FIGS. 5 and 6  differ in that the electrons tunnel in an overall direction from the gate to the substrate in  FIG. 5 , and from the substrate to the gate in  FIG. 6 .  
         [0085]      FIGS. 7A and 7B  are simplified diagrams of a charge trapping memory cell, showing an erase operation being performed on the charge trapping structure, corresponding to  FIGS. 5 and 6 . In the bias arrangement of  FIG. 7A  for erasing the memory cell, the voltage of the gate  110  is −8 V, the voltage of the source  150  and the drain  160  is floating, and the voltage of the substrate  170  is 10 V. The erase operation of  FIG. 7A  corresponds to the erase operation on the NOR memory column of  FIG. 5 . The memory cell of  FIG. 7B  is similar to memory cell of  FIG. 7A , except for the direction of movement of the electrons. In the bias arrangement of  FIG. 7B , the voltage of the gate  110  is 8 V, the voltage of the source  150  and the drain  160  is floating, and the voltage of the substrate  170  is −10 V. The erase operation of  FIG. 7B  corresponds to the erase operation on the NOR-connected memory column of  FIG. 6 . The erase operations of  FIGS. 7A and 7B , and the electron injection operation of  FIGS. 3A and 3B  are alternative electron movement mechanisms.  
         [0086]      FIGS. 8 and 9  are diagrams of a program operation being performed on a column of nonvolatile memory cells interconnected in a NOR arrangement. In the bias arrangement of  FIG. 8 , the voltage of the word lines  510 ,  530 ,  540  are 0 V; the voltage of the word line  520  is −5 V; the voltage of the bit line  504  is floating or 0 V; the voltage of the bit line  506  is 5 V; and the voltage of the substrate  502  is 0 V. A hole is symbolically shown being programmed from the bit line  506  into the memory cell controlled by word line  520 . In the bias arrangement of  FIG. 9 , the voltages of the bit lines  504  and  506  are switched, such that the voltage of the bit line  504  is floating or 0 V, and the voltage of the bit line  506  is 5 V. A hole is symbolically shown being programmed from the bit line  504  into the memory cell controlled by word line  520 . Thus, the bias arrangement of the bit lines controls the portion of the charge trapping structure that is programmed for a particular memory cell. The operation to add holes to a single cell of  FIGS. 4A and 4B  is similar to the program operation being performed on the NOR-connected memory column of  FIGS. 8 and 9 .  
         [0087]      FIGS. 10 and 11  are diagrams of a read operation being performed on a column of nonvolatile memory cells interconnected in a NOR arrangement. In the bias arrangement of  FIG. 10 , the voltage of the word lines  510 ,  530 ,  540  are 0 V; the voltage of the word line  520  is −10 V; the voltage of the bit line  504  is 2 V; the voltage of the bit line  506  is floating or 0 V; and the voltage of the substrate  502  is 0 V. A current is symbolically shown flowing from the bit line  504 , through the node of the memory cell controlled by word line  520 , and into the substrate  502 . In the bias arrangement of  FIG. 11 , the voltages of the bit lines are switched, such that the voltage of the bit line  504  is floating or 0 V, and the voltage of the bit line  506  is 2 V. A current is symbolically shown flowing from the bit line  506 , through the node of the memory cell controlled by word line  520 , and into the substrate  502 . Thus, the bias arrangement of the bit lines controls the portion of the charge trapping structure that is read for a particular memory cell. The read operation being performed on the single cell of  FIGS. 1A and 1B  is similar to the read operation being performed on the NOR-connected memory column of  FIGS. 10 and 11 .  
         [0088]      FIGS. 12 and 13  are diagrams of an erase operation being performed on nonvolatile memory cells interconnected in a virtual ground array arrangement. In the bias arrangement of  FIG. 12 , the voltage of the word lines  1210 ,  1220 ,  1230 , and  1240  are −8 V; the voltage of the bit lines  1203 ,  1204 ,  1205 , and  1206  is floating; and the voltage of the substrate  1202  is 10 V. The virtual ground array of  FIG. 13  is similar to the virtual ground array of  FIG. 12 , except for the direction of movement of the electrons. In the bias arrangement of  FIG. 13 , the voltage of the word lines  1210 ,  1220 ,  1230 , and  1240  are 8 V; the voltage of the bit lines  1203 ,  1204 ,  1205 , and  1206  is floating; and the voltage of the substrate  1202  is −10 V. The erase operation of  FIG. 7A  corresponds to the erase operation on the virtual ground array of  FIG. 12 . The erase operation of  FIG. 7B  corresponds to the erase operation on the virtual ground array of  FIG. 13 .  
         [0089]      FIG. 14  is a diagram of a program operation being performed on a virtual ground array arrangement of nonvolatile memory cells. In the bias arrangement of  FIG. 14 , the voltage of the word lines  1210 ,  1230 , and  1240  are 0 V; the voltage of the word line  1220  is −5 V; the voltage of the bit lines  1203 ,  1204  and  1206  is floating; the voltage of the bit line  1206  is 5 V; and the voltage of the substrate  1202  is 0 V. Holes are symbolically shown being programmed from the bit line  1205  into the parts of the memory cells controlled by word line  1220  and bit line  1205 . The operation to add holes of  FIGS. 4A and 4B  is similar to the program operation of  FIG. 14 .  
         [0090]      FIG. 15  is a diagram of a read operation being performed on a virtual ground array arrangement of nonvolatile memory cells. In the bias arrangement of  FIG. 15 , the voltage of the word lines  1210 ,  1230 , and  1240  is 0 V; the voltage of the word line  1220  is −10 V; the voltage of the bit line  1204  is 2 V; the voltage of the bit lines  1203 ,  1205 , and  1206  is floating; and the voltage of the substrate  1202  is 0 V. A current is symbolically shown flowing from the bit line  1204 , through the memory cells controlled by word line  1220  and bit line  1204 , and into the substrate  1202 . The read operation being performed in  FIGS. 1A and 1B  is similar to the read operation of  FIG. 15 . In some embodiments, a subset of all the bit lines are read.  
         [0091]      FIGS. 16 and 17  are diagrams of an erase operation performed on an array of nonvolatile memory cells interconnected as columns of cells arranged in series. In the bias arrangement of  FIG. 16 , the voltage of the word lines  1620 ,  1630 ,  1640 ,  1650 ,  1660 ,  1670 , and  1680  is −20 V; the voltage of the word lines  1610  and  1690  is floating; the voltage of the bit lines  1603 ,  1604 ,  1605 ,  1606 , and  1607  is floating; and the voltage of the substrate  1602  is 0 V. The memory array of  FIG. 17  is similar to the memory array of  FIG. 16 , except for the direction of movement of the electrons. In the bias arrangement of  FIG. 17 , the voltage of the word lines  1620 ,  1630 ,  1640 ,  1650 ,  1660 ,  1670 , and  1680  is 0 V; the voltage of the word lines  1610  and  1690  is floating; the voltage of the bit lines  1603 ,  1604 ,  1605 ,  1606 , and  1607  is floating; and the voltage of the substrate  1602  is −20 V. The erase operation of  FIG. 7A  is similar to the erase operation on the virtual ground array of  FIG. 16 . The erase operation of  FIG. 7B  is similar to the erase operation on the virtual ground array of  FIG. 17 .  
         [0092]      FIGS. 18 and 19  are diagrams of an erase operation being performed on an array of nonvolatile memory cells interconnected as columns of cells arranged in series with a floating end. In the bias arrangement of  FIG. 18 , the voltage of the word lines  1820 ,  1830 ,  1840 ,  1850 ,  1860 ,  1870 , and  1880  is −20 V; the voltage of the word line  1810  is floating; the voltage of the bit lines  1803 ,  1804 ,  1805 ,  1806 , and  1807  is floating; and the voltage of the substrate  1802  is 0 V. The memory array of  FIG. 18  is similar to the memory array of  FIG. 19 , except for the direction of movement of the electrons. In the bias arrangement of  FIG. 19 , the voltage of the word lines  1820 ,  1830 ,  1840 ,  1850 ,  1860 ,  1870 , and  1880  is 0 V; the voltage of the word line  1810  is floating; the voltage of the bit lines  1803 ,  1804 ,  1805 ,  1806 , and  1807  is floating; and the voltage of the substrate  1802  is −20 V. The erase operation of  FIG. 7A  is similar to the erase operation on the memory array of  FIG. 18 . The erase operation of  FIG. 7B  is similar to the erase operation on the memory array of  FIG. 19 .  
         [0093]      FIG. 20  is a diagram of a program operation being performed on an array of nonvolatile memory cells interconnected as columns of cells arranged in series. In the bias arrangement of  FIG. 20 , the voltage of the word lines  1620 ,  1630 ,  1640 ,  1650 ,  1660 ,  1670 , and  1680  are 10 V; the voltage of the word lines  1610  and  1690  is 3 V; the voltage of the bit lines  1603 ,  1605 , and  1606  is 0 V; the voltage of the bit lines  1604  and  1607  is 3 V; and the voltage of the substrate  1602  is 0 V. Electrons are programmed from the bit lines  1603 ,  1605 , and  1606  into the memory cells controlled by both the word line  1640  and the bit lines  1603 ,  1605 , and  1606 .  
         [0094]      FIG. 21  is a diagram of a program operation being performed on an array of nonvolatile memory cells interconnected as columns of cells arranged in series with a floating end. In the bias arrangement of  FIG. 20 , the voltage of the word lines  1820 ,  1830 ,  1840 ,  1850 ,  1860 ,  1870 , and  1880  are 10 V; the voltage of the word line  1810  is 3 V; the voltage of the bit lines  1803 ,  1805 , and  1806  is 0V; the voltage of the bit lines  1804  and  1807  is 3 V; and the voltage of the substrate  1802  is 0 V. Electrons are programmed from the bit lines  1803 ,  1805 , and  1806  into the memory cells controlled by both the word line  1840  and the bit lines  1803 ,  1805 , and  1806 .  
         [0095]      FIGS. 22, 23 , and  24  are diagrams of a read operation being performed on an array of nonvolatile memory cells interconnected as columns of cells arranged in series. In the bias arrangement of  FIG. 22 , the voltage of the word line  1610  is 3 V; the voltage of the word lines  1620  and  1630  is 10 V; the voltage of the word line  1640  is −10 V; the voltage of the word lines  1650 ,  1660 ,  1670 ,  1680 , and  1690  is 0 V; the voltage of the bit lines  1603 ,  1604 ,  1605 ,  1606 , and  1607  is 3 V; and the voltage of the substrate  1602  is 0 V. Currents are symbolically shown flowing from the bit lines  1603 ,  1604 ,  1605 ,  1606 , and  1607  via the pass transistor row controlled by word line  1610 ; through the memory cells controlled by word line  1640 ; and into the substrate  1602 . In the bias arrangement of  FIG. 23 , the voltage of the word lines  1610 ,  1620 , and  1630  is 0 V; the voltage of the word line  1640  is −10 V; the voltage of the word lines  1650 ,  1660 ,  1670 , and  1680  is 10 V; the voltage of the word line  1690  is 3 V; the voltage of the bit lines  1603 ,  1604 ,  1605 ,  1606 , and  1607  is 3 V; and the voltage of the substrate  1602  is 0 V. Currents are symbolically shown flowing from the bit lines  1603 ,  1604 ,  1605 ,  1606 , and  1607  via the pass transistor row controlled by word line  1690 ; through the memory cells controlled by word line  1640 ; and into the substrate  1602 . In the bias arrangement of  FIG. 24 , the voltage of the word lines  1610  and  1690  is 3 V; the voltage of the word lines  1620 ,  1630 ,  1650 ,  1660 ,  1670 , and  1680  is 10 V; the voltage of the word line  1640  is −10 V; the voltage of the bit lines  1603 ,  1604 ,  1605 ,  1606 , and  1607  is 3 V; and the voltage of the substrate  1602  is 0 V. Currents are symbolically shown flowing from the bit lines  1603 ,  1604 ,  1605 ,  1606 , and  1607  via the pass transistor rows controlled by word lines  1610  and  1690 ; through the memory cells controlled by word line  1640 ; and into the substrate  1602 . The read operation being performed in  FIGS. 1A and 1B  is similar to the read operations of  FIGS. 22, 23 , and  24 . The read current in  FIG. 24  flows through both current terminals of the memory cells controlled by word line  1640  into the substrate  1602 , whereas the read current in  FIGS. 22 and 23  flows through one current terminal of the memory cells controlled by word line  1640  into the substrate  1602 . Thus the read current in  FIG. 24  is larger than the read current in  FIGS. 22 and 23 . In some embodiments, a subset of all the bit lines are read.  
         [0096]      FIG. 25  is a diagram of a read operation being performed on an array of nonvolatile memory cells interconnected as columns of cells arranged in series with a floating end. In the bias arrangement of  FIG. 25 , the voltage of the word line  1810  is 3 V; the voltage of the word lines  1820  and  1830  is 10 V; the voltage of the word line  1840  is −10 V; the voltage of the word lines  1850 ,  1860 ,  1870 , and  1880  is 0 V; the voltage of the bit lines  1803 ,  1804 ,  1805 ,  1806 , and  1807  is 3 V; and the voltage of the substrate  1802  is 0 V. Currents are symbolically shown flowing from the bit lines  1803 ,  1804 ,  1805 ,  1806 , and  1807  via the pass transistor row controlled by word line  1810 ; through the memory cells controlled by word line  1840 ; and into the substrate  1802 . In some embodiments, a subset of all the bit lines are read.  
         [0097]      FIGS. 26 and 27  are diagrams of an erase operation being performed on nonvolatile memory cells interconnected as a column of cells arranged in series. In the bias arrangement of  FIG. 26 , the voltage of the gate of memory cells  2620 ,  2630 ,  2640 ,  2650 ,  2660 ,  2670 , and  2680  is −20 V; the voltage of the gate of memory cells  2610  and  2690  is floating; the voltage of the bit line  2603  is floating; and the voltage of the substrate  2602  is 0 V. The memory column of  FIG. 27  is similar to the memory array of  FIG. 26 , except for the direction of movement of the electrons. In the bias arrangement of  FIG. 27 , the voltage of the gate of memory cells  2620 ,  2630 ,  2640 ,  2650 ,  2660 ,  2670 , and  2680  is 0 V; the voltage of the gate of memory cells  2610  and  2690  is floating; the voltage of the bit line  2603  is floating; and the voltage of the substrate  2602  is −20 V. The erase operation of  FIG. 7A  is similar to the erase operation on the memory column of  FIG. 26 . The erase operation of  FIG. 7B  is similar to the erase operation on the memory column of  FIG. 17 .  
         [0098]      FIGS. 28 and 29  are diagrams of an erase operation being performed on nonvolatile memory cells interconnected as a column of cells arranged in series with a floating end. In the bias arrangement of  FIG. 28 , the voltage of the gate of memory cell  2810  is floating; the voltage of the gates of memory cells  2820 ,  2830 ,  2840 ,  2850 ,  2860 ,  2870 , and  2880  is −20 V; the voltage of the bit line  2803  is floating; and the voltage of the substrate  2802  is 0 V. The memory column of  FIG. 29  is similar to the memory column of  FIG. 29 , except for the direction of movement of the electrons. In the bias arrangement of  FIG. 29 , the voltage of the gate of memory cell  2810  is floating; the voltage of the gates of memory cells  2820 ,  2830 ,  2840 ,  2850 ,  2860 ,  2870 , and  2880  is 0 V; the voltage of the bit line  2803  is floating; and the voltage of the substrate  2802  is −20 V. The erase operation of  FIG. 7A  is similar to the erase operation on the memory column of  FIG. 28 . The erase operation of  FIG. 7B  is similar to the erase operation on the memory column of  FIG. 29 .  
         [0099]      FIG. 30  is a diagram of a program operation being performed on nonvolatile memory cells interconnected as a column of cells arranged in series. In the bias arrangement of  FIG. 30 , the voltage of the gates of memory cells  2610  and  2690  is 3 V; the voltage of the gates of memory cells  2620 ,  2630 ,  2650 ,  2660 ,  2670 , and  2680  are 10 V; the voltage of the gate of memory cell  2640  is 20 V; the voltage of the bit line  2603  is 0 V; and the voltage of the substrate  2602  is 0 V. Electrons are programmed from the bit line  2603  into the memory cell controlled by the word line  2640 .  
         [0100]      FIG. 31  is a diagram of a program operation being performed on nonvolatile memory cells interconnected as a column of cells arranged in series with a floating end. In the bias arrangement of  FIG. 31 , the voltage of the gate of memory cell  2810  is 3 V; the voltage of the gates of memory cells  2820 ,  2830 ,  2850 ,  2860 ,  2870 , and  2880  are 10 V; the voltage of the gate of memory cell  2840  is 20 V; the voltage of the bit line  2803  is 0 V; and the voltage of the substrate  2802  is 0 V. Electrons are programmed from the bit line  2803  into the memory cell controlled by the word line  2840 .  
         [0101]      FIGS. 32, 33 , and  34  are diagrams of a read operation being performed on memory cells interconnected as a column of cells arranged in series. In the bias arrangement of  FIG. 32 , the voltage of the gate of memory cell  2610  is 3 V; the voltage of the gates of memory cells  2620  and  2630  is 10 V; the voltage of the gate of memory cell  2640  is −10 V; the voltage of the gates of memory cells  2650 ,  2660 ,  2670 ,  2680 , and  2690  is 0 V; the voltage of the bit line  2603  is 3 V; and the voltage of the substrate  2602  is 0 V. Current is symbolically shown flowing from the bit line  2603  via the pass transistor  2610 ; through the memory cell  2640 ; and into the substrate  2602 . In the bias arrangement of  FIG. 33 , the voltage of the gates of memory cells  2610 ,  2620 , and  2630  is 0 V; the voltage of the gate of memory cell  2640  is −10 V; the voltage of the gates of memory cells  2650 ,  2660 ,  2670 , and  2680  is 10 V; the voltage of the word line  2690  is 3 V; the voltage of the bit line  2603  is 3 V; and the voltage of the substrate  2602  is 0 V. Current is symbolically shown flowing from the bit line  2603  via the pass transistor  2690 ; through the memory cell  2640 ; and into the substrate  2602 . In the bias arrangement of  FIG. 34 , the voltage of the gates of memory cells  2610  and  2690  is 3 V; the voltage of the gates of memory cells  2620 ,  2630 ,  2650 ,  2660 ,  2670 , and  2680  is 10 V; the voltage of the gate of memory cell  2640  is −10 V; the voltage of the bit line  2603  is 3 V; and the voltage of the substrate  2602  is 0 V. Current is symbolically shown flowing from the bit line  2603  via the pass transistors  2610  and  2690 ; through the memory cell  2640 ; and into the substrate  2602 . The read operation being performed in  FIGS. 1A and 1B  is similar to the read operations of  FIGS. 32, 33 , and  34 . The read current in  FIG. 34  flows through both current terminals of the memory cell  2640  into the substrate  2602 , whereas the read current in  FIGS. 32 and 33  flows through one current terminal of the memory cell  2640  into the substrate  2602 . Thus the read current in  FIG. 34  is larger than the read current in  FIGS. 32 and 33 .  
         [0102]      FIG. 35  is a diagram of a read operation being performed on nonvolatile memory cells interconnected as a column of cells arranged in series with a floating end. In the bias arrangement of  FIG. 35 , the voltage of the gate of memory cell  2810  is 3 V; the voltage of the gates of memory cells  2820  and  2830  is 10 V; the voltage of the gate of memory cell  2840  is −10 V; the voltage of the gates of memory cells  2850 ,  2860 ,  2870 , and  2880  is 0 V; the voltage of the bit line  2803  is 3 V; and the voltage of the substrate  2802  is 0 V. Current is symbolically shown flowing from the bit line  2803  via the pass transistor  2810 ; through the memory cell  2840 ; and into the substrate  2802 .  
         [0103]      FIGS. 36A-36C  show simplified diagrams of other nonvolatile memory cells with various charge storage structures.  FIG. 36A  shows the structure of a split gate memory cell, with a first gate  1020 , a second gate  1010 , a charge storage structure  1030 , and oxide  1040 .  FIG. 36B  shows a nonvolatile memory cell resembling the nonvolatile memory cell of  FIG. 1 , but with a floating gate  1030 , often made of polysilicon.  FIG. 36C  shows a nonvolatile memory cell resembling the nonvolatile memory cell of  FIG. 1 , but with a nanoparticle charge storage structure  1030 .  
         [0104]      FIG. 37  is a simplified diagram of an integrated circuit with an array of charge trapping memory cells and control circuitry. The integrated circuit  3750  includes a memory array  3700  implemented using nonvolatile memory cells, on a semiconductor substrate. The memory cells of array  3700  may be interconnected in parallel, in series, or in a virtual ground array. A row decoder  3701  is coupled to a plurality of word lines  3702  arranged along rows in the memory array  3700 . A column decoder  3703  is coupled to a plurality of bit lines  3704  arranged along columns in the memory array  3700 . Addresses are supplied on bus  3705  to column decoder  3703  and row decoder  3701 . Sense amplifiers and data-in structures in block  3706  are coupled to the column decoder  3703  via data bus  3707 . Data is supplied via the data-in line  3711  from input/output ports on the integrated circuit  3750 , or from other data sources internal or external to the integrated circuit  3750 , to the data-in structures in block  3706 . Data is supplied via the data-out line  3715  from the sense amplifiers in block  3706  to input/output ports on the integrated circuit  3750 , or to other data destinations internal or external to the integrated circuit  3750 . A bias arrangement state machine  3709  controls the application of bias arrangement supply voltages  3708 , such as for the erase verify and program verify voltages, and the arrangements for programming, erasing, and reading the memory cells, such as with the band-to-band currents.  
         [0105]     In other embodiments, the select transistors are omitted.  
         [0106]     While the present invention is disclosed by reference to the technology and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.