Abstract:
An integrated circuit (IC) includes an active region; a pair of active field effect transistors (FETs) in the active region; and an isolation FET located between the pair of active FETs in the active region, the isolation FET configured to provide electrical isolation between the pair of active FETs, wherein the isolation FET has at least one different physical parameter or electrical parameter from the pair of active FETs.

Description:
BACKGROUND 
       [0001]    This disclosure relates generally to the field of integrated circuit (IC) manufacturing, and more specifically to an isolation gate for electrical isolation between semiconductor devices on an IC. 
         [0002]    ICs are formed by connecting isolated active devices, which may include semiconductor devices such as field effect transistors (FETs), through specific electrical connection paths to form logic or memory circuits. Therefore, electrical isolation between active devices is important in IC fabrication. A shallow trench isolation (STI) region may be formed in the IC substrate between two active devices to electrically isolate the active devices. An STI region may be formed by forming a trench in the substrate between the active devices by etching, and then filling the trench with an insulating material, such as an oxide. After the STI trench is filled with the insulating material, the surface profile of the STI region may be planarized by, for example, chemical mechanical polishing (CMP). 
         [0003]    Edge FETs may have increased non-uniformity due to effects such as different size source/drain (S/D) regions. Placement variation of the gate to silicon edge affects the S/D region size. This variation in S/D region can affect doping profiles, strain levels, and epitaxial growth rates. Dummy gates may be formed at the transition region between an STI and the active silicon to assist with maintaining device uniformity. The dummy gates are formed at each silicon edge; i.e., one dummy gate is located on either edge of the STI region, as is shown in IC  100  of  FIG. 1 .  FIG. 1  illustrates a cross section of an IC  100  having dual dummy gates  103   a - b  and STI region  104  between active gates  102   a - b . Active gates  102   a - b  are on active regions  101   a - b . Active regions  101   a - b  each include a source, a channel, and a drain region for each of the active gates  102   a - b , respectively, to form two active FETs. The devices including active regions  101   a - b , with respective active gates  102   a - b , are electrically isolated by STI region  104 . STI region  104  is filled with an insulating material such as an oxide. An IC such as IC  100  with dual dummy gates  103   a - b  has a spacing between active regions  101   a - b  that is about two device pitches. Such spacing between active devices results in an IC having a relatively low device density. 
       SUMMARY 
       [0004]    In one aspect, an IC includes an active region; a pair of active field effect transistors (FETs) in the active region; and an isolation FET located between the pair of active FETs in the active region, the isolation FET configured to provide electrical isolation between the pair of active FETs, wherein the isolation FET has at least one different physical parameter or electrical parameter from the pair of active FETs. 
         [0005]    In another aspect, a method of making an IC includes forming an isolation field effect transistor (FET) in an active region of the IC, the isolation FET being located between a pair of active FETs and configured to provide electrical isolation between the pair of active FETs, wherein the isolation FET has at least one different physical parameter or electrical parameter from the pair of active FETs. 
         [0006]    Additional features are realized through the techniques of the present exemplary embodiment. Other embodiments are described in detail herein and are considered a part of what is claimed. For a better understanding of the features of the exemplary embodiment, refer to the description and to the drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0007]    Referring now to the drawings wherein like elements are numbered alike in the several FIGURES: 
           [0008]      FIG. 1  a cross section of an embodiment of a prior art IC with dual dummy gates and an STI between active devices. 
           [0009]      FIG. 2  illustrates a cross section of an embodiment of an IC with an isolation FET between active devices. 
           [0010]      FIG. 3  illustrates a top view of an embodiment of an IC with an isolation FET between active devices. 
           [0011]      FIG. 4  illustrates a cross section of an embodiment of an IC with dual isolation FETs between active devices. 
           [0012]      FIG. 5  illustrates a top view of an embodiment of an IC with dual isolation FETs between active devices. 
       
    
    
     DETAILED DESCRIPTION 
       [0013]    Embodiments of an isolation FET for an IC are provided, with exemplary embodiments being discussed below in detail. An isolation gate for an isolation FET may be formed on an active region of an IC between two active gates in place of an STI and dual dummy gates. The isolation FET acts to electrically isolate the active devices from one another. Formation of isolation gates between the active gates may provide relatively uniform gate dimensions for an IC. The active device density of the IC may also be increased by use of isolation FETs; the area necessary for a chip with a single isolation FET between active devices may be reduced by about 20% in some embodiments as compared to an IC with STI regions and dual dummy gates. Strain uniformity, doping profiles, epitaxial growth rates are examples of device parameters of the IC that may be improved, due to the absence of STI regions between active devices. All devices in the IC may have uniform strain, with source/drain regions that are uniform in height, which reduces the complexity of forming source/drain contacts on the IC. Isolation gates may be used in an IC that includes any appropriate type of semiconductor devices, for example, FETs or FinFETs. 
         [0014]    An isolation gate acts as an FET gate for a portion of the active region of the IC to form the isolation FET. The isolation FET includes a source, a channel, and a drain that are located underneath the isolation gate in the active region of the IC. The isolation FET stays turned off during IC operation to provide isolation between the active devices located on either side of the isolation gate. This may be achieved by engineering the relative threshold voltage (Vt) of the isolation FET versus the Vt of the active devices. The Vt of a FET is a voltage that is applied to the FET gate at which the FET changes state between on and off. The isolation gate is formed such that the isolation FET has a Vt that is higher than the Vt of the active devices. The isolation gate does not experience any voltages that are higher than the Vt of the isolation FET during IC operation, allowing the isolation FET to stay turned off. 
         [0015]    The Vt of the isolation FET may be raised relative to the active devices in any appropriate manner. Modification of one or more physical or electrical characteristics of the isolation FET may be performed to raise the isolation FET Vt. Additionally or alternately, modification one or more physical or electrical characteristics of the active devices may be performed to lower the active device Vt, while not lowering the Vt of the isolation FET. Some example characteristics in which the isolation FET may differ from the active FETs include: inclusion of source/drain extensions, omission of source/drain extensions, source/drain doping levels, gate dielectric thickness, gate length, strain, gate workfunction, silicided source/drains, or lack of silicided source/drains. An isolation gate may also be connected to a voltage source selected to keep the isolation FET in the off state during IC operation. 
         [0016]      FIG. 2  illustrates a cross section of an embodiment of an IC  200  with an isolation gate  203  between active gate  202   a - b  on active region  201 . Active region  201  includes various source, drain, and channel regions that form two active FETs, each gated by one of active gates  202   a - b , and an isolation FET gated by isolation gate  203 . The isolation FET gated by isolation gate  203  is configured such that the isolation FET stays turned off during operation of IC  200 , providing isolation between the active FETs gated by active gates  202   a - b ; this may be achieved by one or more of the following techniques. The Vt of the isolation FET gated by isolation gate  203  may be raised by implantation of the isolation gate  203  with a substance selected to raise the Vt of the isolation FET. The isolation FET may be masked during an extension implant of the active gates  202   a - b  to lower the Vt of the active FETs. The active gates  202   a - b  may be implanted with a substance selected to lower the Vt of the active FETs while not lowering the Vt of the isolation gate  203 . The active FETs may include source/drain extensions that are not present in the isolation FET. The isolation gate  203  may be formed with a thicker dielectric layer than the active gates  202   a - b , so as to raise the Vt of the isolation FET, and to reduce gate leakage and capacitance between the active FETs. The isolation gate  203  may have a longer gate length (indicated by line  204 ) than the active gates  202   a - b , which may act to raise the Vt of the isolation FET. The isolation gate  203  workfunction may be higher than the active gate  202   a - b  workfunction, giving the isolation FET a higher Vt. The isolation gate  203  workfunction type may be selected such that the isolation FET is of an opposite type (n-type or p-type) to the active FETs. Strain may be induced in the active FETs to lower the active FET Vt. The strain may be of any appropriate type, including but not limited to epitaxial strain, oxidation strain, nitride strain, or implant strain. Any appropriate type of strain may be applied to the active FETs so as to lower the active FET Vt. Any appropriate combination of the above techniques may be applied to an isolation FET or an active FET to ensure that the isolation FET stays turned off during the operation of the IC. 
         [0017]      FIG. 3  illustrates a top view of an embodiment of an IC  300  with an isolation gate  303  between active gates  302   a - b  in active regions  301   a - b . The IC  300  includes two active regions,  301   a - b , separated by STI regions  304 . Active region  301   a  may have a type (n-type or p-type) that is opposite a type of active region  301   b  in some embodiments. Active regions  301   a - b  include various source, drain, and channel regions. Isolation gate  303  forms an isolation FET in each of active regions  301   a - b , and active gates  302   a - b  each form an active FET in each of active regions  301   a - b  on either side of the isolation FETs. The isolation FETs gated by isolation gate  303  provides isolation between the active FETs gated by active gates  302   a - b  by staying turned off during operation of IC  300 ; this may be achieved by applying one or more of the techniques discussed above with respect to  FIG. 2  to the active FETs gated by active gates  302   a - b  and/or the isolation FETs gated by isolation gate  303 . STI regions  304  may include trenches filled with an insulating material, and are only necessary between active regions  301   a - b , not between active devices within active regions  301   a - b . ICs  200  and  300  may exhibit relatively high device density, and may have improved strain uniformity and manufacturability versus an IC that includes STI regions between active devices in the active regions due to the absence of STI regions between active devices in the active regions. 
         [0018]    Dual isolation gates may be formed between active devices in some embodiments for ICs that require very low leakage conditions between active devices.  FIG. 4  illustrates a cross section of an embodiment of an IC  400  with two isolation gates  403   a - b  located between active gates  402   a - b  on active region  401 . Active region  401  includes source, drain, and channel regions that form two active FETs, each active FET gated by one of active gates  402   a - b , and two isolation FETs, each isolation FET gated by one of isolation gates  403   a - b . The isolation FETs gated by isolation gates  403   a - b  provide isolation between the active FETs gated by active gates  402   a - b  by staying turned off during operation of IC  400 ; this may be achieved by applying one or more of the techniques discussed above with respect to  FIG. 2  to the active FETs gated by active gates  402   a - b  and/or the isolation FETs gated by isolation gates  403   a - b.    
         [0019]      FIG. 5  illustrates a top view of an embodiment of an IC  500  with two isolation gates  503   a - b  between active gates  502   a - b  in active regions  501   a - b . The IC  500  includes two active regions,  501   a - b , separated by STI regions  504 . Active region  501   a  may have a type (n-type or p-type) that is opposite a type of active region  501   b  in some embodiments. Active regions  501   a - b  include various source, drain, and channel regions gated by isolation gates  503   a - b  and active gates  502   a - b . Isolation gates  503   a - b  each form an isolation FET in each of active regions  501   a - b , and active gates  502   a - b  each form an active FET in each of active regions  301   a - b  on either side of the isolation FETs. The isolation FETs gated by isolation gates  503   a - b  provide isolation between the active FETs gated by active gates  502   a - b  by staying turned off during operation of IC  500 ; this may be achieved by applying one or more of the techniques discussed above with respect to  FIG. 2  to the active FETs gated by active gates  502   a - b  and/or the isolation FETs gated by isolation gates  503   a - b . STI regions  504  may include trenches filled with an insulating material, and are only necessary between active regions  501   a - b , not between active devices. ICs  400  and  500  with dual isolation gates may have low electrical leakage between active devices, and improved strain uniformity and manufacturability versus an IC that includes STI regions between active devices in the active regions due to the absence of STI regions between active devices in the active regions. 
         [0020]    The technical effects and benefits of exemplary embodiments include increased device density and uniformity in an IC. 
         [0021]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
         [0022]    The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.