Abstract:
An electronic device for driving an actuator device for a hard disk and a motor for turning the hard disk, the device having a first driving circuit connected to the rotation motor and integrated in a chip of semiconductor material having a substrate defining a reference-potential region, a second driving circuit integrated in the chip and connected to a first actuation stage of the actuator device, and a third driving circuit integrated in the chip and connected to a second actuation stage of the actuator device. The actuator device supports a read/write transducer of the hard disk. The first actuation stage performs a rough displacement of the read/write transducer, while the second actuation stage performs a finer displacement of the same read/write transducer.

Description:
TECHNICAL FIELD  
         [0001]    The present invention pertains to hard disk drives, and, more importantly, to an electronic device for driving an actuator device for a hard disk and for driving a motor that turns the hard disk.  
         BACKGROUND OF THE INVENTION  
         [0002]    As is known, rather complex electronic devices are used for driving hard disks, commonly referred to as “COMBOs”, which comprise circuits dedicated to driving the motor that turns the hard disk and to driving the actuator device of the hard disk itself, A/D and D/A converters, digital circuits, power blocks, and so on.  
           [0003]    In greater detail, FIG. 1 shows a hard disk  1 , which is positioned inside a container  2  and is provided with a plurality of tracks for data storage. The hard disk  1  is connected by means of a hub  4  to a shaft  5 , which is in turn connected to an electric motor  6  (“spindle”), which causes rotation of the hard disk  1  about the shaft  5  at a constant rate. The electric motor  6  is driven by an electronic device  7 , connected to the motor itself by means of a first flexible cable  8 .  
           [0004]    In addition, the electronic device  7  drives, via a second flexible cable  9  and a third flexible cable  10 , respectively a first actuation stage  11  and a second actuation stage  12  of an actuator device  13 .  
           [0005]    In detail, the first actuation stage  11  consists of an induction motor (also referred to as “voice coil motor”) to which a suspension  15  formed by a lamina is fixed in cantilever fashion. The suspension  15  ends with a flexible portion  16  which carries, at its free end, a read/write transducer  17  (“slider”) and a pair of actuators  18   a  and  18   b  made of piezoelectric material, one set on one side, and the other set on the other side, of the floating end of the flexible portion  16 . The flexible portion  16  and the piezoelectric actuators  18   a,    18   b  constitute the second actuation stage  12  of the actuator device  13 . In particular, each piezoelectric actuator  18   a,    18   b  consists of a chip of piezoelectric material set between two metal plates that form the two electrodes of the actuator; one electrode is connected to the flexible portion  16  (ground), whilst the other is floating.  
           [0006]    Advantageously, the read/write transducer  17  is fixed to the flexible portion  16  by means of a gimbal  19 . In addition, the read/write transducer  17  supports a read/write head  20  which constitutes the reading and writing device proper of the hard disk  1 .  
           [0007]    The first actuation stage  11  displaces the ensemble made up of the suspension  15  and of the read/write transducer  17  through the hard disk  1  during track search (rough displacement), whilst the second actuation stage  12  carries out fine control of the position of the read/write transducer  17 , following the track (finer regulation).  
           [0008]    In particular, the flexible portion  16  converts the mechanical deformation undergone by the piezoelectric actuators  18   a,    18   b  as a result of a potential applied to their floating electrodes into a linear displacement of the read/write transducer  17 . To a first approximation, apart from hysteresis phenomena due to a non-unique relation between the potential applied to the floating electrodes of the piezoelectric actuators  18   a,    18   b  and the mechanical deformation undergone by the piezoelectric actuators themselves, we will find that for positive potentials applied to the floating electrodes there is obtained a displacement of the read/write transducer  17  in a first direction, whilst for negative potentials applied to the floating electrodes, the read/write transducer  17  is displaced in a second direction opposite to the first.  
           [0009]    For this purpose, each piezoelectric actuator  18   a,    18   b  is driven by means of an amplifier circuit which is included in the electronic device  7  and has both positive and negative output dynamics with respect to the ground of the actuator. Typically, amplifier circuits are used with output dynamics of dozens of volts (e.g., from ±12 V up to ±40 V).  
           [0010]    In general, these amplifier circuits are integrated using junction-isolation techniques, exploiting reverse-biased junctions to obtain isolation of the various components making up the amplifier circuit itself. In order to prevent forward biasing of these junctions, the substrate of semiconductor material, in which the amplifier circuit is integrated, must necessarily be connected to the largest negative potential among those applied to the amplifier circuit itself (a potential which, as has been said previously, may even reach ±40 V).  
           [0011]    At present, this requirement prevents these amplifier circuits from being integrated in one and the same chip of semiconductor material in which the other circuits making up the electronic device  7  are made. In fact, this chip, on account of the presence of power blocks, requires a substrate electrically connected to ground. Given that the two requirements mentioned above (substrate connected to the largest negative potential and substrate connected to ground) are mutually incompatible, it is not feasible to have an electronic device  7  that works properly and is integrated in one and the same chip of semiconductor material together with the amplifier circuits.  
           [0012]    The technical problem that lies at the root of the present invention is to provide an electronic device that will overcome the limitations specified above with reference to the known art.  
         SUMMARY OF THE INVENTION  
         [0013]    The disclosed embodiment of the invention is directed to an electronic device for driving an actuator device for a hard disk and a motor for turning the hard disk that includes a first driving circuit connected to the rotation motor and integrated in a chip of semiconductor material that has a substrate defining a reference-potential region; a second driving circuit integrated in the chip and connected to the first actuation stage; and a third driving circuit integrated in the chip and connected to the second actuation stage of the actuator device. Ideally, the third driving circuit has two amplifier circuits integrated in the chip, each connected to a respective piezoelectric actuator, each of the amplifier circuits driving a respective piezoelectric actuator to control displacements of a read/write transducer.  
           [0014]    In accordance with another embodiment of the invention, a hard disk system is provided that includes an actuator device for a hard disk and a motor for turning the hard disk, the actuator device supporting a read/write transducer and including a first actuation stage and a second actuation stage that respectively control a first displacement and a second displacement of the read/write transducer, and the electronic device including a first driving circuit connected to the motor and integrated in a chip of semiconductor material that has a substrate defining a reference-potential region; a second driving circuit integrated in the chip and connected to the first actuation stage; and a third driving circuit integrated in the chip and connected to the second actuation stage of the actuator device. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]    The characteristics and advantages of the electronic device according to the invention will emerge from the ensuing description of an example of embodiment, which is given merely to provide a non-limiting illustration, with reference to the attached drawings.  
         [0016]    In the said drawings:  
         [0017]    [0017]FIG. 1 is a perspective view of a hard disk;  
         [0018]    [0018]FIG. 2 is a block diagram of an electronic device for driving the hard disk of FIG. 1 according to an embodiment of the invention;  
         [0019]    [0019]FIG. 3 represents the circuit of one of the blocks of FIG. 2; and  
         [0020]    [0020]FIG. 4 is a cross section through a chip incorporating a portion of the electronic device of FIG. 2. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0021]    An electronic device  100 , illustrated in FIG. 2, is integrated in a single chip  50  of semiconductor material having a substrate  200  defining a reference-potential region GND (ground). The chip  50  comprises a first driving circuit  101  and a second driving circuit  102 , of a type in itself known and hence not illustrated in detail in FIG. 2, driving, via the first and the second flexible cables  8  and  9 , respectively, the electric motor  6  for turning the hard disk  1 , and the first actuation stage  11  of the actuator device  13 .  
         [0022]    The electronic device  100  further comprises, integrated in the selfsame chip  50 , a third driving circuit  103 , driving, via the third flexible cable  10 , the second actuation stage  12  of the actuator device  13 , and a logic control circuit  180  receiving at input  190  an activation signal and generating at output three control signals S 1 , S 2 , S 3  for the first, second and third driving circuits  101 ,  102 ,  103 , respectively.  
         [0023]    In particular, the third driving circuit  103  comprises a first amplifier circuit  104  for driving the piezoelectric actuator  18   a  and a second amplifier circuit  105  for driving the piezoelectric actuator  18   b.    
         [0024]    Since the first and second amplifier circuits  104  and  105  are identical, i.e., they have the same structure and operate in the same way, the amplifier circuit  104  alone will be described in what follows.  
         [0025]    With reference to FIG. 3, the amplifier circuit  104  comprises a differential input stage  106  connected between a first supply line  107 , which is set at a positive voltage V P , and the reference potential GND, and has a first, non-inverting, input  113 , and a second, inverting, input  114 , receiving the control signal S 3 . The differential input stage  106  comprises a first PMOS input transistor  115  and a second PMOS input transistor  116 , and a third NMOS input transistor  117  and a fourth NMOS input transistor  118 . In detail, the first input transistor  115  has a source terminal connected to a first circuit node  150 , a drain terminal connected to the reference potential GND via the fourth input transistor  118 , and a gate terminal connected to the non-inverting input of the differential input stage  106 . The second input transistor  116  has a source terminal connected to the first circuit node  150 , drain terminal connected to the reference potential GND via the third input transistor  117 , and gate terminal connected to the inverting input of the differential input stage  106 . The third input transistor  117  is diode-connected (i.e., it has its drain terminal and gate terminal short-circuited) and has a drain terminal connected to the drain terminal of the second input transistor  116 , and a source terminal connected to the reference potential GND, and a gate terminal. Also the fourth input transistor  118  is diode-connected (i.e., it has drain terminal and gate terminal short-circuited) and has a drain terminal connected to the drain terminal of the first input transistor  115 , a source terminal connected to the reference potential GND, and a gate terminal. The differential input stage  106  moreover comprises a first reference current generator I 1  connected between the first circuit node  150  and the first supply line  107 .  
         [0026]    The amplifier circuit  104  further comprises a driving stage  120  cascade-connected to the differential input stage  106  and a final stage  108  cascade-connected to the driving stage  120 .  
         [0027]    The driving stage  120  comprises a first NMOS transistor  121  and a second NMOS transistor  122 . In detail, the first driving transistor  121  has a source terminal connected to the reference potential GND, a drain terminal connected to a second circuit node  151 , and a gate terminal connected to the gate terminal of the third input transistor  117 . The second driving transistor  122  has a gate terminal connected to the gate terminal of the fourth input transistor  118 , a source terminal connected to the reference potential GND, and a drain terminal connected to an input branch  123  of a current-mirror circuit  125  having an output branch  124  connected to a third circuit node  152 .  
         [0028]    The final stage  108  comprises a first PMOS output transistor  110  having a source terminal connected to the first supply line  107 , a drain terminal connected to an output node  111  of the amplifier circuit  104 , and a gate terminal connected to the second circuit node  151 . The final stage  108  moreover comprises a second, NMOS, output transistor  112  having a drain terminal connected to the output node  111  of the driving circuit  104 , a source terminal connected to a second supply line  109 , set at a negative potential V N , and a gate terminal connected to the third circuit node  152 . The output node  111  of the amplifier circuit  104  is connected to the first piezoelectric actuator  18   a  via the flexible cable  10 .  
         [0029]    In addition, the driving circuit  104  comprises a first biasing transistor  130  and a second biasing transistor  131 . The first biasing transistor  130  is diode-connected (i.e., it has its drain terminal and source terminal short-circuited) and has a drain terminal connected to the reference potential GND via a second reference current generator I 2 , gate terminal connected to the second circuit node  151  via a first resistor  132 , and a source terminal connected to the first supply line  107 .  
         [0030]    The second biasing transistor  131  is diode-connected (i.e., it has drain terminal and gate terminal short-circuited) and has a drain terminal connected to the first supply line  107  via a third reference current generator I 3 , a gate terminal connected to the third circuit node  152  via a second resistor  133 , and a source terminal connected to the second supply line  109 .  
         [0031]    In addition, between the first supply line  107  and the second circuit node  151 , a fourth reference current generator I 4  is connected, and between the third circuit node  152  and the second supply line  109 , a fifth reference current generator  15  is connected.  
         [0032]    Operation of the electronic device  100 , and in particular of the driving circuit  104 , is described below.  
         [0033]    In resting conditions, i.e., when the logic control circuit  180  does not generate the control signal S 3 , the inputs  113  and  114  of the differential input stage  106  are balanced. Consequently, the current of I 4  flows in the first driving transistor  121 , and the current of I 2  flows in the first biasing transistor  130 . Likewise, in the second driving transistor  122  there flows the current of I 5  (which is reversed by means of the current mirror  125 ), and in the second biasing transistor  131  there flows the current of I 3 . No current flows in the first and second resistors  132 ,  133 , and the voltage drop across them is zero. Consequently, the voltage between the gate terminal and the source terminal of the first biasing transistor  130  is equal to the voltage present between the gate terminal and the source terminal of the first output transistor  110 . In these conditions, the current of I 2  is repeated in the first output transistor  110  through the current mirror that the latter forms with the first biasing transistor  130 . Likewise, the voltage present between the gate terminal and the source terminal of the second biasing transistor  131  is equal to the voltage present between the gate terminal and the source terminal of the output transistor  112 . In these conditions, the current of I 3  is repeated in the second output transistor  112  via the current mirror that the latter forms with the second biasing transistor  131 .  
         [0034]    When the logic control circuit  180  generates the control signal S 3 , the differential input stage  106  unbalances. If, for example, the control signal S 3  is such as to cause a decrease in the voltage present on the inverting input  114  and an increase in the voltage present on the non-inverting input  113 , the current flowing in the second and third input transistors  116 ,  117  increases, and the current flowing in the first and fourth input transistors  115 ,  118  decreases. These currents are repeated, respectively, in the first driving transistor  121  and in the second driving transistor  122 . The first driving transistor  121  thus carries a current greater than the current of I 4 , whilst the second driving transistor  122  carries a current smaller than the current of I 5 . This results in a decrease in the voltage on the second and third circuit nodes  151  and  152 , and in a non-zero voltage drop across the first and second resistors  132  and  133 . In these conditions, the voltage present between the gate terminal and the source terminal of the first output transistor  110  is higher than the voltage present between the gate terminal and the source terminal of the first biasing transistor  130 . Consequently, in the output transistor  110  there flows a current greater than the current of I 2 . The first output transistor  110  thus tends to close, connecting the output node  111  to the supply line  107 . In addition, the voltage present between the gate terminal and the source terminal of the second output transistor  112  is lower than the voltage present between the gate terminal and the source terminal of the second biasing transistor  131 . Consequently, in the output transistor  112  there flows a current smaller than the current of I 3 , and the second output transistor  112  tends to open, isolating the output node  111  from the second supply line  109 . Vice versa, when the control signal S 3  is such as to increase the voltage present on the inverting input  114  and to decrease the voltage present on the non-inverting input  113 , the current flowing in the second and third input transistors  116 ,  117  decreases, and the current flowing in the first and fourth input transistors  115 ,  118  increases. These currents are repeated, respectively, in the first driving transistor  121  and in the second driving transistor  122 . The first driving transistor  121  thus carries a current smaller than the current  14 , whilst the second driving transistor  122  carries a current greater than the current of I 5 . This results in a voltage increase on the second and third circuit nodes  151  and  152 , and in a non-zero voltage drop, of opposite sign, across the first and second resistors  132  and  133 . In these conditions, in the first output transistor  110  there flows a current smaller than the current of I 2 , and the first output transistor  110  tends to open, isolating the output node  111  from the supply line  107 . In the second output transistor  112  there flows instead a current greater than the current  13 , and the second output transistor  112  tends to open, connecting the output node  111  to the second supply line  109 .  
         [0035]    In order to integrate the amplifier circuit  104  in the chip  50 , the second output transistor  112 , the second driving transistor  131 , the second resistor  133 , and the fifth reference current generator I 5 , i.e., all the components of the amplifier circuit  104  that are set at a negative potential V N , are made in a double-insulation integrated structure referred to as “collection-free” structure. The presence of this double insulation enables the substrate  200  to be biased to ground without any of the junctions that make up the above-mentioned components being forward-biased.  
         [0036]    In particular, FIG. 4 shows a cross section of the chip  50  incorporating the second output transistor  112 . In detail, the second output transistor  112  has a drain region  201  having an N + -type conductivity, which is made in a first well  202  having an N-type conductivity. The first well  202  is enclosed in a second well  203  having a P-type conductivity, which is in turn enclosed in a third well  204  having an N-type conductivity. The second well  203  comprises a first buried region  205 , which is set at a negative potential V N  and is formed beneath the first well  202 . The second well  203  further comprises a first deep region  206 , having an elongated annular shape, only two portions of which may be seen in FIG. 4. The first deep region  206  extends as far as the first buried region  205  so as to connect it to a surface  207  of the chip  50  and to isolate the first well  202  completely from the substrate  200 .  
         [0037]    Likewise, the third well  204  comprises a second buried region  208  having an N − -type conductivity formed beneath the second well  203 , and a second deep region  209  having an elongated annular shape, only two portions of which may be seen in FIG. 4. The second deep region  209  extends as far as the second buried region  208  so as to connect it to the surface  207  of the chip  50  and to isolate the second well  203  completely from the substrate  200 . In particular, the third well  204  is set at a potential higher than or equal to the reference potential GND.  
         [0038]    Again with reference to FIG. 4, the second deep region  209  houses a source region  210  of the second output transistor  112  having an N+-type conductivity. The latter transistor moreover comprises a gate region  211  which extends above the first well  204  and the second deep region  209 . A thick oxide portion  212  and a thin oxide portion  215  isolate the gate region  211  from the first well  204 .  
         [0039]    What has been described previously can be equally applied to the amplifier circuit  105  driving the piezoelectric actuator  18   b.  In particular, the components of the amplifier circuit  105  set at a negative potential V N  are made in a double-isolation integrated structure equivalent to the one illustrated previously.  
         [0040]    The advantages that may be achieved with the electronic device illustrated are described below. In the first place, it is possible to integrate the electronic device  100  in a single chip  50 , instead of in two distinct chips as in the known device. Consequently, the electronic device  100  has reduced dimensions, shorter assembly times and contained costs. In particular, the costs involved in the testing phase are considerably reduced, in that testing is carried out on a single chip, and not on two distinct chips. It is moreover possible to verify the efficiency of the electronic device  100  as a whole.  
         [0041]    The electronic device  100  moreover enables saving of silicon area. In fact, many circuits that implement general functions, such as voltage-regulating circuits, biasing circuits, and circuits for protection against electrostatic discharges (ESDs), can be integrated within the single chip  50 , in that they do not have to be shared any longer between two distinct chips. All this also enables saving of the area in the printed circuit on which the electronic device  100  is soldered.  
         [0042]    As compared to the known device, the electronic device  100  moreover presents greater reliability and immunity from external disturbance, in that the interconnections between the device itself and the amplifier circuits  104  and  105  are provided inside the chip  50 , and not on the printed circuit; greater speed, in that the said interconnections have fewer parasitic components, and hence higher driving frequencies may be used; and a lower consumption, in that, as has already been mentioned previously, certain circuit blocks are shared, and hence it is not necessary to duplicate them.  
         [0043]    Finally, it is clear that numerous modifications and variations may be made to the electronic device described herein, all falling within the scope of the inventive idea, as defined in the attached claims.  
         [0044]    For example, all the components of the amplifier circuits  104  and  105  to which the negative potential V N  is applied can be integrated using structures that are equivalent to the one that has been described previously, such as triple-well structures, or using SOI wafers.