Abstract:
A method of forming one or more capacitors on or in a substrate and a capacitor structure resulting therefrom is disclosed. The method includes forming a trench in the substrate, lining the trench with a first copper-barrier layer, and substantially filling the trench with a first copper layer. The first copper layer is substantially chemically isolated from the substrate by the first copper-barrier layer. A second copper-barrier layer is formed over the first copper layer and a first dielectric layer is formed over the second copper-barrier layer. The dielectric layer is substantially chemically isolated from the first copper layer by the second copper-barrier layer. A third copper-barrier layer is formed over the dielectric layer and a second copper layer is formed over the third copper-barrier layer. The second copper layer is formed in a non-damascene process.

Description:
TECHNICAL FIELD 
       [0001]    The present invention relates generally to electronic devices, and more particularly to dual-copper plate capacitors integrated with solid state integrated circuit devices. 
       BACKGROUND ART 
       [0002]    Semiconductor device performance improvements have historically been achieved by reducing device dimensions. The device miniaturization trend has progressed to a point where contemporary integrated circuits (ICs) are fabricated with deep sub-micron device feature sizes. The trend has placed increased emphasis on miniaturization of discrete passive components that are required to function with miniaturized active devices. 
         [0003]    In addition to reduced feature sizes, recent trends have focused on replacing conventional aluminum with copper as the conductive medium. As wire widths in integrated circuits continue to shrink, the electrical conductivity of the wiring material itself becomes increasingly important. In this regard, aluminum, which has been the material of choice since the integrated circuit art began, is becoming less attractive than conductors such as gold, silver, and especially copper. Copper is also more resistant than aluminum to electromigration, a property that grows in importance as wire widths decrease. Electromigration is a mass transport effect caused by electrons in electrical current flow colliding with stationary atoms. The collision can push the stationary atoms in the direction of the electron flow. Effects of electromigration are most pronounced in narrow passages (i.e., areas of increased current density) and can lead to a contact void. 
         [0004]    As a result of its numerous electrical advantages over aluminum, copper has found increased application in the creation of discrete components, most notably discrete capacitors that are formed within of above the surface of a semiconductor-based IC. Copper provides improved conductivity and reliability but does provide a process challenge where a layer of copper must be patterned and etched, partially due to the fact that copper does not readily form volatile species during the etching process. To overcome the etch problem, other methods of creating interconnect lines using copper have been proposed, including depositing copper patterns using selective electroless plating. 
         [0005]    A limit on the speed of advanced ICs is set by a signal propagation delay in conductive interconnect lines, which is determined by the time constant of the lines. The time constant is the product of the resistance, R, of the line and the capacitance, C, between the line and all adjacent lines; hence, an RC time constant. Using a lower resistivity conductive material decreases interconnect RC time constant delays resulting in an overall increase in device speed. 
         [0006]    Resistance, R, of a structure is determined by the following equation 
         [0000]    
       
         
           
             R 
             = 
             
               
                 ρ 
                  
                 
                     
                 
                  
                 L 
               
               WT 
             
           
         
       
     
         [0000]    where ρ is the resistivity of a conductive material, L is the length of the conductive material, W is the width of the conductive material, and T is the thickness of the conductive material. 
         [0007]    The limited availability of low-loss integrated capacitor structures has long hindered the development of integrated circuits such as passive filters, voltage controlled oscillators (VCO), matching networks, and transformers. Contemporary portable communications environments strive to achieve more fully integrated circuits that operate at radio frequencies (RF) and microwave frequencies. Recent trends indicate a push to integrate entire receivers onto a single substrate. Planar capacitors fabricated from high resistivity materials tend to suffer from high losses and low quality factors (Q factors) at radio frequencies. The losses and low Q factors are generally attributable to dielectric losses incurred from parasitic capacitances and resistive losses due to the use of thin conductors with relatively high resistance. The Q factor is defined as 
         [0000]    
       
         
           
             Q 
             = 
             
               
                 E 
                 s 
               
               
                 E 
                 l 
               
             
           
         
       
     
         [0000]    where E s  is energy that is stored in the reactive portion of the component and E l  is energy that is lost in the reactive portion of the component. 
         [0008]    For high frequency signals, such as signals in the 10 GHz to 100 GHz range, the value of the Q factor obtained from silicon-based capacitors is significantly degraded. For applications in this high frequency range, monolithic capacitors have been researched using a base substrate other than silicon for the creation of the capacitors. Such monolithic capacitors have, for instance, been created using sapphire or GaAs as a base. These capacitors have a considerably lower parasitic capacitance than their silicon counterparts and therefore provide higher frequencies of resonance of an RC circuit. Where, however, more complex applications are required, the need still exists to create capacitors using silicon as a substrate base. 
         [0009]    With reference to  FIG. 1 , a cross-sectional view of a prior art capacitor  100  forms a portion of an integrated circuit. A substrate  101  having a dielectric layer  103  is coated with thin layers of metal, such as a titanium (Ti)/titanium-nitride (TiN)/aluminum (Al)/TiN (i.e., Ti/TiN/Al/TiN) film stack. The thin layers of metal, after appropriate etching, serve as a bottom plate  105  of the capacitor  100 . The bottom plate  105  is covered with a metal-insulator-metal (MIM) dielectric layer  107 , followed by a capacitor top plate  109 . The MIM dielectric layer  107  and top plate  103  may each be etched as shown. The top plate  109  is frequently comprised of either a Ti/TiN/Al/TiN metal film stack (i.e., the same type of metal film stack as the bottom plate  105 ) or may be comprised of Ti, tantalum (Ta), or tantalum nitride (TaN). Conductive lines (not shown) are provided to each of the capacitor plates  105 ,  109  by either additive or subtractive metal patterning processes. 
         [0010]    In  FIG. 2 , an alternative prior art construction of an integrated circuit capacitor  200  includes a substrate  201 , a copper-barrier layer  203 , and portions of electroplated or sputtered first  205 A and second  205 B copper lines. In a typical damascene process, the copper-barrier layer  203  prevents migration of copper molecules into surrounding areas of the substrate  201 . The copper-barrier layer  203  is formed from a material having high electrical conductivity while maintaining a low copper diffusivity to chemically isolate a copper conductor from the substrate  201 . The copper-barrier layer  203  further provides for adhesion of the subsequently formed copper lines  205 A,  205 B. A blanket dielectric layer  207  is deposited over the substrate  201  and exposed portions of the first  205 A and second  205 B copper lines. A portion of the blanket dielectric layer  207  is etched to expose the second copper line  205 B. The second copper line  205 B forms the bottom plate of the integrated circuit capacitor  200 . A Ta layer  209  is deposited followed by a MIM dielectric layer  211 . A top plate  213  of the capacitor  200  is formed over the MIM dielectric layer  211 . The top plate  213  is comprised of a Ti/TiN/Al/TiN metal film stack. Alternatively, the top plate  213  is comprised of Ti, Ta, or TaN. Conductive lines (not shown) are provided to each of the capacitor plates  205 B,  213  by either additive or subtractive metal processes. 
         [0011]    Either of the prior art alternatives described with reference to  FIGS. 1  or  2  have good linearity due to the planar design of each. The good linearity generally makes MIM planar capacitors a preferred choice in integrated circuit designs and specifically in radio-frequency applications. 
         [0012]    However, the prior art alternatives also share similar limitations. RF applications also require a high Q factor. The Q factor, as shown above, is strongly dependent on the resistivity of the capacitor conducting plates. Since all of the materials listed in the prior art structures (e.g., Ti, TiN, Ta, Al, etc.) have a higher resistivity than copper, the Q factor will be low unless both conducting plates are fabricated from copper. Although some dual copper plate capacitor integrated circuit designs do exist, each is plagued by expensive damascene process steps required for each of the capacitor plates. 
         [0013]    Therefore, what is needed is a dual copper plate integrated circuit capacitor and a process for producing the same which is readily and economically integrated into a typical fabrication process flow. 
       SUMMARY 
       [0014]    In an exemplary embodiment, the present invention is a method of forming one or more integrated circuit capacitors on a substrate. The method includes forming a trench in the substrate, lining the trench with a first copper-barrier layer, and substantially filling the trench with a first copper layer. The first copper layer is substantially chemically isolated from the substrate by the first copper-barrier layer. A second copper-barrier layer is formed over the first copper layer and a first dielectric layer is formed over the second copper-barrier layer. The dielectric layer is substantially chemically isolated from the first copper layer by the second copper-barrier layer. A third copper-barrier layer is formed over the dielectric layer and a second copper layer is formed over the third copper-barrier layer. The second copper layer is formed in a non-damascene process. 
         [0015]    In another exemplary embodiment, the present invention is a method of forming one or more integrated circuit capacitors on a substrate where the method includes forming a trench in a substrate, lining the trench with a first copper-barrier layer, and substantially filling the trench with a first copper layer. The first copper layer is substantially chemically isolated from the substrate by the first copper-barrier layer. A second copper-barrier layer is formed over the first copper layer and a first dielectric layer is formed over the second copper-barrier layer. The dielectric layer is substantially chemically isolated from the first copper layer by the second copper-barrier layer. A third copper-barrier layer is formed over the dielectric layer and a second copper layer is formed over the third copper-barrier layer. The second copper layer is formed in a non-damascene process. An etch mask located substantially over the trench is applied, and patterned. Portions of the second copper-barrier layer, the first dielectric layer, the third copper-barrier layer, and the second copper layer which are not underlying the etch mask are etched. A dielectric cap layer is formed over the second copper layer. The second copper layer is isotropically etched and partially undercut. The undercut allows portions of the dielectric cap layer which are unsupported by the second copper layer to collapse over edges of the second copper layer. 
         [0016]    In another exemplary embodiment, the present invention is an integrated circuit capacitor comprising a trench fabricated in a base substrate, a first copper-barrier layer substantially lining the trench, a first copper plate fabricated over the first copper-barrier layer and substantially filling the trench, a second copper-barrier layer formed over an uppermost portion of the first copper plate, and a first dielectric layer formed over the second copper-barrier layer. The first dielectric layer is configured to be in electrical communication with the first copper plate. A third copper-barrier layer is formed over the first dielectric layer and a second copper plate is fabricated over the third copper-barrier layer. The second copper plate is formed by a non-damascene process and is configured to be in electrical communication with the first dielectric layer. 
         [0017]    In another exemplary embodiment, the present invention is an integrated circuit capacitor comprising a first copper-barrier layer substantially formed over a base substrate and a first copper plate fabricated over the first copper-barrier layer. The first copper layer is substantially chemically isolated from the substrate by the first copper-barrier layer. A second copper-barrier layer is formed over an uppermost portion of the first copper plate and a first dielectric layer is formed over the second copper-barrier layer. The first dielectric layer is configured to be in electrical communication with the first copper plate and further is chemically isolated from the first copper plate by the second copper-barrier layer. A third copper-barrier layer is formed over the first dielectric layer and a second copper plate is fabricated over the third copper-barrier layer. The second copper plate is substantially chemically isolated from the first dielectric layer; the second copper plate further being formed by a non-damascene process and configured to be in electrical communication with the first dielectric layer. 
         [0018]    In another exemplary embodiment, the present invention is a n integrated circuit capacitor comprising a trench fabricated in a base substrate, a first copper-barrier layer substantially lining the trench, a first copper plate fabricated over the first copper-barrier layer and substantially filling the trench, a second copper-barrier layer formed over an uppermost portion of the first copper plate, and a first dielectric layer formed over the second copper-barrier layer. The first dielectric layer is configured to be in electrical communication with the first copper plate. A third copper-barrier layer is formed over the first dielectric layer and a second copper plate is fabricated over the third copper-barrier layer. The second copper plate is formed by a non-damascene process and configured to be in electrical communication with the first dielectric layer. A collapsed dielectric cap layer substantially surrounds the second copper plate except for a surface of the second copper plate nearest to the third copper-barrier layer. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0019]      FIG. 1  is a cross-sectional view of an integrated circuit capacitor fabricated in accordance with the prior art. 
           [0020]      FIG. 2  is a cross-sectional view of an integrated circuit capacitor fabricated in a copper damascene process in accordance with the prior art. 
           [0021]      FIGS. 3A-3P  are cross-sectional views of various stages of processing steps of a capacitor having both plates fabricated from copper in accordance with various exemplary embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0022]    With reference to  FIG. 3A , a base substrate  301  may be a silicon wafer. Alternatively, another elemental Group IV semiconductor or compound semiconductor (e.g., Groups III-V or II-VI) in either wafer or non-wafer forms may be selected for the base substrate  301 . Further, the base substrate  301  may be fabricated from silicon-on-insulator or a variety of other base materials known to those of skill in the art. 
         [0023]    The base substrate  301  may have fabricated thereon a plurality of active integrated circuit devices (not shown). Methods of fabrication of the plurality of active integrated circuit devices are known in the art. The base substrate  301  includes trenches which have a copper-barrier layer  303 . The copper-barrier layer  303  substantially lines the trench prevents migration of copper molecules into surrounding areas of the base substrate  301 . The copper-barrier layer  303  is formed from a material having a high electrical conductivity while maintaining a low copper diffusivity to chemically isolate any subsequently formed copper conductors from the base substrate  301 . The copper-barrier layer  303  is frequently a single or bi-layer deposition from materials including cobalt-based alloys, ruthenium-based alloys, silicon nitride, silicon-copper-nitride, tantalum, and tantalum nitride. In a specific exemplary embodiment, the copper-barrier layer  303  is 300 Å of tantalum followed by a 400 Å to 600 Å copper seed layer. The copper seed layer is commonly used although ruthenium-based seedless layers are beginning to emerge in the art. If employed, the seed-layer provides a low-resistance conductor for plating current that drives a subsequent electroplating process and also facilitates film nucleation. The copper-barrier layer  303  further provides for adhesion of subsequently formed first  305 A and second  305 B copper fill areas. 
         [0024]    In this exemplary embodiment, the first copper fill area  305 A is not necessarily a part of the present invention. The first copper fill area  305 A may simply be a copper conducting line proximate to the capacitor of the present invention or, alternatively, may be a copper conducting line which serves to electrically connect the second copper fill area  305 B to other portions of the integrated circuit (not shown). Regardless, the second copper fill area  305 B forms at least a portion of a bottom plate of the MIM capacitor. Further, the copper-barrier layer  303  and the second copper fill area  305 B do not need to be formed in a trench. Consequently, in an alternative embodiment, the barrier layer  303  and the second copper fill area  305 B may be formed in a planar fashion over an uppermost surface of the substrate  301 . 
         [0025]    As is known in the art, copper has superior properties over Al, Xi, Ta, and various other metallic materials in terms of both an inherently lower electrical resistivity and a pronounced resistance to electromigration. However, there are few volatile copper compounds. Consequently, copper can ordinarily not be patterned by typical subtractive patterning techniques such as photoresist masking and plasma etching typically used with other metallic materials. Copper processing thus typically uses an additive patterning process referred to as copper damascene processing. 
         [0026]    In a copper damascene process, either an underlying dielectric layer and/or base substrate is patterned and etched (using standard photolithographic processes) with open trenches or openings v/here a conductor will be formed. A thick coating of copper is added such that the copper significantly overfills the trenches or openings. A chemical mechanical planarization (CMP) process removes the copper to a level coplanar with surrounding local features. Frequently, the surrounding local features are chosen to be a dielectric material, such as silicon dioxide (SiO 2 ), which serves as a hard etch-stop material to determine an end-point to the CMP process step. Copper contained within the trenches or openings is not removed and becomes the patterned conductor. Any surrounding dielectric material may be etched or left in place depending upon subsequent processes. 
         [0027]    In  FIG. 3B , a first dielectric layer  307 A is formed over uppermost portions of the base substrate  301  and the first  305 A and second  305 B copper fill areas. In a specific exemplary embodiment, the dielectric layer  307 A is a deposited silicon nitride (Si 3 N 4 ) layer, 500 Å to 1000 Å in thickness. Other types of dielectric materials may also be used such as, for example, a chemical vapor deposition (CVD) deposited silicon dioxide layer. 
         [0028]    A bottom anti-reflective coating (BARC) layer  309  may be formed over the dielectric layer  307 A ( FIG. 3C ), followed by a coated layer of photoresist. The photoresist is photolithographically exposed, developed, and etched, forming a patterned photoresist layer  311 . Portions of the BARC layer  309  and the dielectric layer  309 A are anisotropic ally etched, stopping on the second copper fill area  305 B. The patterned photoresist layer  311  and any remaining portions of the BARC layer  309  are removed, leaving a patterned dielectric layer  307 B ( FIG. 3D ). A wet clean may be performed to remove any oxide formation from exposed portions of the second copper fill area  305 B. 
         [0029]    With reference to  FIG. 3E , a second copper-barrier layer  313 A is formed. In a specific exemplary embodiment, the second copper-barrier layer is a deposited Ta layer, 200 Å to 500 Å thick. Exposed surfaces of tantalum quickly oxidize. An optional oxygen plasma treatment may be used to enhance the effective dielectric constant. 
         [0030]    In  FIG. 3F , an MIM dielectric layer  315 A is formed. The MIM dielectric layer may be comprised of, for example, Si 3 N 4  or one or more other high-k dielectric materials. High-k dielectric materials are known in the art and include films such as tantalum pentoxide (Ta 2 O 5 ), zirconium oxide (ZrO 2 ), hafnium oxide (HfO 2 ), and lead-zirconate-titanate (PZT). However, other dielectric materials may readily be employed as well to form the MIM dielectric layer  315 A. In a specific exemplary embodiment, the MIM dielectric layer  315 A can range from 20 Å to 1000 Å in thickness. 
         [0031]    In  FIG. 3G , a third copper-barrier layer  317 A is formed followed by a combined copper-seed/copper layer  319 A and a dielectric cap layer  321 A. In a specific exemplary embodiment, the third copper-barrier layer  317 A is a Ta layer, 100 Å to 300 Å in thickness, the combined copper-seed/copper layer  319 A is 600 Å to 2500 Å thick, and the dielectric cap layer  321 A is Si 3 N 4  300 Å to 1000 Å in thickness. Alternatively, the combined copper-seed/copper layer  319 A may be comprised of, for example, a sputtered or electroplated copper layer only without a copper-seed layer. In either form of the copper layer  319 A, the fabrication process is non-damascene in nature. For example, a CMP step is not required after formation of the copper layer  319 A. Consequently, the copper layer  319 A will not have any types of fine striations on either face as may be found in a damascene process (although such striations would have little or no effect on the present invention). 
         [0032]    With reference to  FIG. 3H , a sequence of lithography to form a MIM top plate commences. A second BARC layer  323 A is formed over the dielectric cap layer  321 A. A photoresist layer is formed over the second BARC layer  323 A. The photoresist layer is exposed, developed, and etched, forming a MIM top plate patterned photoresist layer  325 . The patterned photoresist layer  325  serves as an etch mask and protects underlying materials while portions of both the second BARC layer  323 A and the dielectric cap layer  321 A are each etched ( FIG. 3I ) forming an etched second BARC layer  323 B and etched dielectric cap layer  321 B, respectively. 
         [0033]    An isotropic copper wet etch chemistry is employed to etch the combined copper-seed/copper layer  319 A, thus slightly undercutting the etched dielectric cap layer  323 B and forming a copper MIM top plate  319 B ( FIG. 3J ). Although not required to practice or produce the MIM capacitor of the present invention, shortly after the etched copper is approximately equal to the thickness of the copper seed layer, the dielectric cap layer  3213  collapses, forming a collapsed dielectric layer  321 C. The collapsed dielectric layer  321 C protects the underlying MIM top plate  319 B from subsequent etching. In a specific exemplary embodiment, the isotropic copper wet etch chemistry is selected to have an etch rate of less than 5000 Å per minute with a higher selectivity to BARC, photoresist, and copper. 
         [0034]    Alternatively, an anisotropic dry etch such as, for example, a reactive-ion etch (RIE), may be used instead of the isotropic wet etch. Various combinations of chemicals may be incorporated to increase selectivity of the RIE such that, for example, silicon nitride is more readily etched than any adjacent non-silicon nitride layers. Such selectivity enhancements are known in the art. With the anisotropic dry etch, the etched dielectric cap layer  323 B will not be undercut sufficiently to form the collapsed dielectric layer  321 C. However, the collapsed dielectric layer  321 C is not necessary to either practice or fabricate the present invention. 
         [0035]    With reference to  FIG. 3K , portions of each of the remaining layers overlying the patterned dielectric layer  307 B, namely, the second copper-barrier layer  313 A, the MIM dielectric layer  315 A, and the third copper-barrier layer  317 A, are etched thus forming an etched second copper-barrier layer  313 B, an etched MIM dielectric layer  315 B, and an etched third copper-barrier layer  317 B. Note, also the patterned dielectric layer  307 B may be partially etched, depending on the material selected to form the patterned dielectric layer  307 B and the etchant selected, thus forming an etched patterned dielectric layer  307 C. Consequently, the etched patterned dielectric layer  307 C serves as an etch-stop layer. In a specific exemplary embodiment, RIE is selected to etch portions of the layers overlying the patterned dielectric layer  307 B. 
         [0036]    The MIM top plate patterned photoresist layer  325  and the etched second BARC layer  323 B are removed in  FIG. 3L  by, for example, an oxygen-plasma ashing step. Construction of the high-Q planar MIM capacitor is substantially complete. Steps for producing a top-plate electrode commence with  FIG. 3M  in which a multi-layer dielectric is formed over the completed MIM capacitor in preparation for a dual-damascene electrode process. Each of the first  327 A, second  329 A, third  331 A, and fourth  333 A dielectric layers are chosen so as to allow a selective etchant to be used in which one layer is etched faster than one or more adjacent layers. For example, in a specific exemplary embodiment, the first dielectric layer  327 A is selected to be Si 3 N 4  ranging from 200 Å to 1000 Å in thickness, the second dielectric layer  329 A is selected to be a deposited oxide ranging from 2000 Å to 8000 Å in thickness, the third dielectric layer  331 A is selected to be Si 3 N 4  ranging from 100 Å to 700 Å in thickness, and the fourth dielectric layer  333 A is selected to be a deposited oxide ranging from 0.5 μm to 1 μm in thickness. One of skill in the art will recognize, however, that the ranges given are approximate and may vary depending upon factors such as particular films chosen and specific process parameters employed. 
         [0037]    In  FIG. 3N , a chemical-mechanical planarization step planarizes the fourth dielectric layer  333 A creating a planarized dielectric layer  333 B. In  FIG. 3O , A fifth dielectric layer  335  is formed over the planarized dielectric layer  333 B. A thickness range of the fifth dielectric layer  335  may be, for example, 300 Å to over 1000 Å in thickness. 
         [0038]    In a specific exemplary embodiment, the fifth dielectric layer  335  is a Si 3 N 4  hard mask. In this embodiment, the hard mask acts (1) as a complementary anti-reflection dielectric during subsequent via and trench lithography steps; and (2) to protect the planarized dielectric layer  333 B during a subsequent etch of the first dielectric layer  327 A. The etch of the first dielectric layer  327 A is generally performed after the transfer of the trench pattern into the fifth dielectric layer  335  and the planarized dielectric layer  333 B and oxygen-plasma ashing of a trench lithography BARC/photoresist stack (not shown). The first dielectric layer  327 A etch is a self-aligned etch without the protection of the removed BARC/photoresist stack. Therefore, the Si 3 N 4  hard mask is mainly a sacrificial layer and is used to preserve the trench depth in the underlying oxide. 
         [0039]    With reference to  FIG. 3P , the overlying multi-layer film stack is etched forming etched first  327 B, second  329 B, third  331 B, and fourth  333 B dielectric layers. The various layers define a trench bottom/via top wherein the via extends to electrically contact the copper MIM top plate  319 B. Via and trench walls are lined with a copper-barrier layer  337  and a dual-damascene electroplated copper layer  339  simultaneously fills the via and the trench, thus completing the electrode connection to the copper MIM top plate  319 B. As is known in the art, growth of the electroplated copper layer  339  is polycrystalline. Grain size within the copper layer  339  is dependent on factors such as texture (i.e., microroughness) of underlying layers, parameters of growth conditions such as temperature, plating voltages, etc., as well as dimensions of trenches to be filled (e.g., dimensions of grooves or vias). Grain size and consequently overall resistivity of the copper trench/via may be controlled through appropriate anneal steps as needed. 
         [0040]    In the foregoing specification, the present invention has been described with reference to specific embodiments thereof. It will, however, be evident to a skilled artisan that various modifications and changes can be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. For example, skilled artisans will appreciate that many types of deposition technology, such as sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), electron beam evaporation (EBE), electrochemical deposition (ECD), thermal evaporation, and others may readily be employed for various layers described. Further, the substrate type may be selected based upon an intended use of a finalized product. For example, an ASIC used as an integrated circuit for a computer may be formed on a silicon wafer. In an RF integrated circuit used for lightweight applications or flexible circuit applications, such as a cellular telephone or personal data assistant (PDA), the integrated circuit may be formed on a polyethyleneterephthalate (PET) substrate deposited with silicon dioxide and polysilicon followed by an excimer laser annealing (ELA) anneal step. Skilled artisans will appreciate that other types of semiconducting and insulating materials other than those listed may be employed. For example, a BARC layer may improve processing and edge wall definition of photoresist layer used as etch masks, but the BARC layer is not required. Additional particular process fabrication and deposition techniques, such as low pressure chemical vapor deposition (LPCVD), ultra-high, vacuum CVD (UHCVD), and low pressure tetra-ethoxysilane (LPTEOS) may be readily employed for various layers and still be within the scope of the present invention. Although the exemplary embodiments describe particular types of dielectric and semiconductor materials, one skilled in the art will realize that other types of materials and arrangements of materials may also be effectively utilized and achieve the same or similar advantages. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.