Abstract:
A thin film transistor (TFT) and an organic light emitting diode (OLED) display device. The TFT and the OLED display device include a substrate, a buffer layer disposed on the substrate, a semiconductor layer disposed on the buffer layer, a gate electrode insulated from the semiconductor layer, a gate insulating layer insulating the semiconductor layer from the gate electrode, and source and drain electrodes insulated from the gate electrode and partially connected to the semiconductor layer, wherein the semiconductor layer is formed from a polycrystalline silicon layer crystallized by a metal catalyst and the metal catalyst is removed by gettering using an etchant. In addition, the OLED display device includes an insulating layer disposed on the entire surface of the substrate, a first electrode disposed on the insulating layer and electrically connected to one of the source and drain electrodes, an organic layer, and a second electrode.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims the benefit of Korean Patent Application No. 2009-18201, filed Mar. 3, 2009 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    Aspects of the present invention relate to a thin film transistor (TFT), a method of fabricating the same, and an organic light emitting diode (OLED) display device including the same. More particularly, aspects of the present invention relate to a TFT, a method of fabricating the same, and an OLED display device including the same, where the fabrication process can remove most of a metal catalyst remaining in a semiconductor layer formed from a polycrystalline silicon layer crystallized using the metal catalyst by gettering using a metal etchant. 
         [0004]    2. Description of the Related Art 
         [0005]    Thin film transistors (TFTs) have been typically used as active elements of active matrix liquid crystal display (AMLCD) devices, and switching and driving elements of organic light emitting diode (OLED) display devices. In these cases, it is necessary to control the characteristics of the TFTs according to the required characteristics of the elements of the particular devices. One of the important factors which determine the characteristics of the TFTs is leakage current. 
         [0006]    In general, in a TFT having a semiconductor layer formed of a polycrystalline silicon layer which is crystallized by a crystallization method that does not use a metal catalyst, the leakage current tends to increase when the width of a channel region increases and tends to decrease when the length of the channel region increases. However, even though the length of the channel region is increased in order to reduce the leakage current, the effect is minor. Moreover, in a display device, if the length of the channel region is increased, the size of the entire device is also increased, and the aperture ratio is reduced. Thus, the length of the channel region is limited. 
         [0007]    Recently, methods of crystallizing an amorphous silicon layer using a metal catalyst have been extensively studied, since the methods have advantages in that the crystallization can be achieved at a lower temperature over a shorter crystallization time than in a solid phase crystallization (SPC) method. Also, a broader range of process conditions can be used and the reproducibility is higher than in an excimer laser crystallization (ELC) method. However, in a TFT using a polycrystalline silicon layer that has been crystallized using a metal catalyst as a semiconductor layer, the leakage current of the TFT as a function of changes in the length or width of the channel region changes without a clear tendency, unlike the tendency that other TFTs demonstrate. Accordingly, a TFT having a semiconductor layer formed of a polycrystalline silicon layer crystallized using a metal catalyst has problems in that the leakage current as a function of the size of the channel region of the semiconductor layer cannot be estimated, and the size of the channel region of the semiconductor layer, which will be used to control the leakage current, cannot be determined. 
       SUMMARY OF THE INVENTION 
       [0008]    Aspects of the present invention provide a thin film transistor (TFT), a method of fabricating the same, and an organic light emitting diode (OLED) display device including the same, where the fabrication process can remove most of a metal catalyst remaining in a semiconductor layer formed of a polycrystalline silicon layer crystallized using the metal catalyst by gettering using a metal etchant, thus improving the characteristics of the TFT. 
         [0009]    According to an exemplary embodiment of the present invention, a TFT includes: a substrate; a buffer layer disposed on the substrate; a semiconductor layer disposed on the buffer layer; a gate electrode insulated from the semiconductor layer; a gate insulating layer insulating the semiconductor layer from the gate electrode; and source and drain electrodes insulated from the gate electrode and partially connected to the semiconductor layer, wherein the semiconductor layer comprises at least one groove. 
         [0010]    According to another exemplary embodiment of the present invention, an OLED display device includes: a substrate; a buffer layer disposed on the substrate; a semiconductor layer disposed on the buffer layer; a gate electrode insulated from the semiconductor layer; a gate insulating layer insulating the semiconductor layer from the gate electrode; source and drain electrodes insulated from the gate electrode and partially connected to the semiconductor layer; an insulating layer disposed on the entire surface of the substrate; a first electrode disposed on the insulating layer and electrically connected to one of the source and drain electrodes; an organic layer; and a second electrode, wherein the semiconductor layer comprises at least one groove. 
         [0011]    Additional aspects and/or advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    These and/or other aspects and advantages of the invention will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which: 
           [0013]      FIGS. 1A to 1D  are cross-sectional views illustrating a crystallization process for a polycrystalline silicon layer according to an exemplary embodiment of the present invention; 
           [0014]      FIGS. 2A and 2B  are cross-sectional views illustrating gettering on a polycrystalline silicon layer according to another exemplary embodiment of the present invention; 
           [0015]      FIG. 2C  is a photograph of the surface of a polycrystalline silicon layer taken after gettering according to the embodiment of  FIGS. 2A and 2B ; 
           [0016]      FIGS. 2D to 2F  are graphs of metal catalyst concentrations of polycrystalline silicon layers to which gettering has been applied, according to the embodiment of  FIGS. 2A and 2B ; 
           [0017]      FIGS. 3A to 3C  are cross-sectional views illustrating a process of fabricating a top-gate TFT according to another exemplary embodiment of the present invention; 
           [0018]      FIGS. 4A to 4C  are cross-sectional views illustrating a process of fabricating a bottom-gate TFT according to another exemplary embodiment of the present invention; and 
           [0019]      FIG. 5  is a cross-sectional view of an OLED display device according to another exemplary embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0020]    Reference will now be made in detail to the present embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below in order to explain the present invention by referring to the figures. 
         [0021]      FIGS. 1A to 1D  are cross-sectional views illustrating a crystallization process for a polycrystalline silicon layer according to an exemplary embodiment of the present invention. First, as illustrated in  FIG. 1A , a buffer layer  110  is formed on a substrate  100  that is formed of glass or plastic. The buffer layer  110  is an insulating layer and may be formed of a silicon dioxide layer, a silicon nitride layer, or a combination thereof, by chemical vapor deposition (CVD) or physical vapor deposition (PVD). The buffer layer  110  serves to prevent diffusion of moisture or impurities generated in the substrate  100  and to adjust the heat transfer rate during crystallization, thereby facilitating crystallization of an amorphous silicon layer. However, the buffer layer  110  is not required in all aspects of the present invention. 
         [0022]    Subsequently, an amorphous silicon layer  120  is formed on the buffer layer  110 . The amorphous silicon layer  120  may be deposited by CVD or PVD. During or after the formation of the amorphous silicon layer  120 , a dehydrogenation process may be performed to reduce the concentration of hydrogen. 
         [0023]    Then, the amorphous silicon layer  120  is crystallized into a polycrystalline silicon layer. According to aspects of the present invention, the amorphous silicon layer is crystallized into a polycrystalline silicon layer by a crystallization method using a metal catalyst, such as a metal induced crystallization (MIC) technique, a metal induced lateral crystallization (MILC) technique, or a super grain silicon (SGS) technique. However, the crystallization techniques are not limited thereto. 
         [0024]    The SGS technique is a method of crystallizing an amorphous silicon layer  120  in which the concentration of the metal catalyst diffused into the amorphous silicon layer  120  is lowered in order to control the grain size of the polycrystalline silicon to be within the range of several μm to several hundreds of μm. To lower the concentration of the metal catalyst diffused into the amorphous silicon layer  120 , a diffusion layer  130  (see  FIG. 1B ) may be formed on the amorphous silicon layer  120 , and a metal catalyst layer  140  (see  FIG. 1B ) may be formed on the diffusion layer  130  and annealed to diffuse the metal catalyst into the amorphous silicon layer  120 . Alternatively, the concentration of the metal catalyst diffused in the amorphous silicon layer  120  may be lowered by forming the metal catalyst layer  140  at a low concentration without forming the diffusion layer on the amorphous silicon layer  120 . 
         [0025]    In an exemplary embodiment of the present invention, the polycrystalline silicon layer may be formed by an SGS crystallization technique, which will now be described.  FIG. 1B  is a cross-sectional view illustrating a process of forming a diffusion layer  130  and a metal catalyst layer  140  on the amorphous silicon layer  120 . The diffusion layer  130  is formed on the amorphous silicon layer  120 . The diffusion layer  130  may be formed of a silicon nitride layer or a silicon dioxide layer, into which a metal catalyst formed in the following process may diffuse through annealing, and may be formed in a double-layered structure of the silicon nitride layer and the silicon dioxide layer. Moreover, in the case where the diffusion layer  130  is formed in the double-layered structure, any one of the layers may be patterned to adjust the position where the metal catalyst is diffused. The diffusion layer  130  may be formed by any suitable deposition method such as, for example, CVD or PVD. 
         [0026]    In the example shown, the diffusion layer  130  may be formed to a thickness of 1 through 2,000 Å. When the thickness of the diffusion layer  130  is less than 1 Å, it may be difficult to control the amount of metal catalyst that diffuses through the diffusion layer  130 . When the thickness of the diffusion layer  130  is more than 2,000 Å, the amount of metal catalyst diffused into the amorphous silicon layer  120  may be too small, and thus it is difficult to crystallize the amorphous silicon layer  120  into a polycrystalline silicon layer. 
         [0027]    Subsequently, a metal catalyst is deposited on the diffusion layer  130  to form a metal catalyst layer  140 . The metal catalyst may be selected from the group consisting of nickel (Ni), palladium (Pd), silver (Ag), gold (Au), aluminum (Al), tin (Sn), antimony (Sb), copper (Cu), terbium (Tb), and cadmium (Cd), and preferably the metal catalyst may be Ni. The metal catalyst layer  140  may be formed to have a surface density of 10 11  through 10 15  atoms/cm 2  on the diffusion layer  130 . When the metal catalyst layer  140  is formed with a surface density of less than 1011 atoms/cm 2 , the number of seeds, which act as nuclei for crystallization, may be too small, and thus it may be difficult to crystallize the amorphous silicon layer into a polycrystalline silicon layer by the SGS crystallization technique. When the metal catalyst layer  140  is formed with a surface density of more than 1015 atoms/cm 2 , the amount of metal catalyst diffused into the amorphous silicon layer  120  is too large, and thus the grains produced in the polycrystalline silicon layer are smaller in size. Moreover, the amount of metal catalyst remaining in the polycrystalline silicon layer also increases, and thus the characteristics of a semiconductor layer formed by patterning the polycrystalline silicon layer may be poorer. 
         [0028]      FIG. 1C  is a cross-sectional view illustrating a process of diffusing the metal catalyst through the diffusion layer  130  to an interface of the amorphous silicon layer  120  by annealing the substrate  110 . Referring to  FIG. 1C , the substrate  100 , on which the buffer layer  110 , the amorphous silicon layer  120 , the diffusion layer  130 , and the metal catalyst layer  140  are formed, is annealed to move some of the metal catalyst of the metal catalyst layer  140  to the surface of the amorphous silicon layer  120 . That is, only a very small amount of metal catalyst  140   b  from the metal catalyst layer  140  diffuses through the diffusion layer  130  to the surface of the amorphous silicon layer  120  during the annealing, and most of the metal catalyst  140   a  does not reach the amorphous silicon layer  120 , or does not pass at all through the diffusion layer  130 . Thus, the amount of metal catalyst  140   b  reaching the surface of the amorphous silicon layer  120  is determined by the diffusion blocking ability of the diffusion layer  130 , which is closely related to the thickness of the diffusion layer  130 . That is, as the thickness of the diffusion layer  130  increases, the diffused amount of the metal catalyst  140   b  decreases, and thus the produced grains become larger. On the other hand, if the thickness of the diffusion layer  130  decreases, the diffused amount of the metal catalyst  140   b  increases, and thus the produced grains become smaller. 
         [0029]    The annealing process may be performed at a temperature of about 200 to about 900° C., preferably at a temperature of about 350 to about 500° C. for several seconds to several hours to diffuse the metal catalyst. Under the annealing conditions described above, it is possible to prevent deformation of the substrate  100  caused by excessive annealing, and to lower production costs and increase yield. The annealing process may be one of a furnace process, a rapid thermal annealing (RTA) process, a UV process, and a laser process. 
         [0030]      FIG. 1D  is a cross-sectional view illustrating a process of crystallizing the amorphous silicon layer  120  into a polycrystalline silicon layer  160  by using the diffused metal catalyst. Referring to  FIG. 1D , the amorphous silicon layer  120  is crystallized into a polycrystalline silicon layer  160  by the metal catalysts  140   b  that have diffused to the surface of the amorphous silicon layer  120  through the diffusion layer  130 . That is, the diffused metal catalyst  140   b  is bonded to silicon of the amorphous silicon layer  120  to form metal silicides, which form seeds, i.e., nuclei for crystallization, and thus the amorphous silicon layer  120  is crystallized into the polycrystalline silicon layer  160 . 
         [0031]    As illustrated in  FIG. 1D , the annealing process is performed without removing the diffusion layer  130  and the metal catalyst layer  140 . Alternatively, the polycrystalline silicon layer may be formed by diffusing the metal catalyst  140   b  onto the amorphous silicon layer  120  to form metal silicides, which are nuclei for crystallization, removing the diffusion layer  130  and the metal catalyst layer  140 , and then annealing the bared amorphous silicon layer  120 . 
         [0032]      FIGS. 2A and 2B  are cross-sectional views illustrating gettering on a polycrystalline silicon layer according to another exemplary embodiment of the present invention. First, as illustrated in  FIG. 2A , a buffer layer  210  and a polycrystalline silicon layer  220  crystallized using the metal catalyst according to  FIGS. 1A through 1D  have been formed on a substrate  200 . Here, the exemplary gettering that follows is performed on the substrate  200 , from which the diffusion layer  130  and the metal catalyst layer  140  illustrated in  FIG. 1D  have been deleted from  FIGS. 2A and 2B  for purposes of explanation. 
         [0033]    The polycrystalline silicon layer  220  contains residual metal catalysts  140   a  and  140   b,  and the concentration of the residual metal catalysts  140   a  and  140   b  after the crystallization is about 1×10 13  to 5×10 14  atoms/cm 2 . The polycrystalline silicon layer  220  is etched with an etchant. 
         [0034]    The etchant used is to remove nickel or nickel silicide and includes a mixture of 25% hydrochloric acid (HCl), 10% acetic acid (CH 3 COOH), and ironicchloride at various concentrations. Moreover, buffered oxide etch (BOE) such as HF or NH 4 F may be used. When the etchant is used to etch the polycrystalline silicon layer  220  for about 2 minutes, the residual metal catalysts are dissolved in the etchant, thus allowing the gettering process to proceed. 
         [0035]    Referring to  FIG. 2B , when the substrate  200  on which the polycrystalline silicon layer  220  has been formed is etched, the residual metal catalysts  140   a  and  140   b  present in the polycrystalline silicon layer  220  are removed. Especially, the metal silicide  140   a  at the grain interface is dissolved in the etchant and removed, and thus grooves or indentations “a” are formed. The formed indentations “a” have various sizes according to the initial concentration of the metal catalyst and the temperature and time of the crystallization annealing process. The indentations “a” may have sizes in the range of about 200 to about 1,000 nm, and fine holes may be formed. 
         [0036]      FIG. 2C  is a photograph of the surface of the polycrystalline silicon layer  220  taken after gettering with the etchant as illustrated in  FIG. 2B , from which it can be seen that the indentations “a” are formed after the aggregated metal catalyst and metal silicide  140   a  are removed. 
         [0037]      FIGS. 2D to 2F  are graphs of metal catalyst concentrations of the polycrystalline silicon layers to which gettering has been applied, in which the crystallization is performed using nickel as the metal catalyst.  FIG. 2D  shows the concentration of nickel catalyst of the polycrystalline silicon layer measured before gettering,  FIG. 2E  shows the concentration of nickel catalyst of the polycrystalline silicon layer measured after gettering for 1 minute, and  FIG. 2F  shows the concentration of nickel catalyst of the polycrystalline silicon layer measured after gettering for 2 minutes. 
         [0038]    Referring to  FIGS. 2D to 2F , when comparing the amounts of nickel catalyst before and after gettering for 1 and 2 minutes, it can be seen that the amount of nickel catalyst on the surface of the polycrystalline silicon layer is reduced after gettering has been applied for 1 minute (B) and the amount of nickel catalyst is also reduced after gettering has been applied for 2 minutes (C). 
         [0039]    Although the grooves are formed on the surface of the polycrystalline silicon layer after gettering, the grooves have no significant effect on the characteristics of a semiconductor layer formed from the polycrystalline silicon layer. 
         [0040]    Table 1 shows the characteristics of the semiconductor layer formed from the polycrystalline silicon layer  160  after gettering. 
         [0000]    
       
         
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 Number 
                 Threshold 
                 Off-current 
               
               
                 of indentations 
                 voltage (Vth)(V) 
                 (Ioff)(A/μm) 
               
               
                   
               
             
             
               
                 4 
                 2.01 
                 2 × 10 −11   
               
               
                 6 
                 1.99 
                 1 × 10 −11   
               
               
                 8 
                 1.98 
                 1 × 10 −11   
               
               
                   
               
             
          
         
       
     
         [0041]    It can be seen from Table 1 that although the indentations “a” are present on the surface of the polycrystalline silicon layer, the threshold voltage (Vth) characteristics and the off-current (Ioff) characteristics are excellent. Thus, it is possible to effectively remove the metal catalyst by the above-described gettering. 
         [0042]      FIGS. 3A to 3C  are cross-sectional views illustrating a process of fabricating a top-gate TFT according to another exemplary embodiment of the present invention using the process of fabricating the polycrystalline silicon layer. Referring to  FIG. 3A , a buffer layer  310  may be formed on a substrate  300  that is formed of glass, stainless steel, or plastic. The buffer layer  310  is an insulating layer and may be formed of a silicon dioxide layer, a silicon nitride layer, or a combination thereof. The buffer layer  310  serves to prevent diffusion of moisture or impurities generated in the substrate  300  and to adjust the heat transfer rate during crystallization, thereby facilitating crystallization of an amorphous silicon layer. 
         [0043]    Subsequently, to form a polycrystalline silicon layer  320   a,  an amorphous silicon layer is formed on the buffer layer  310 . In the same manner as the exemplary embodiment of  FIGS. 1A to 1D , the amorphous silicon layer is crystallized into a polycrystalline silicon layer  320   a  using a metal catalyst. Then, the polycrystalline silicon layer  320   a  is subjected to the above-described gettering of  FIGS. 2A and 2B  using a metal etchant to remove residual metal catalysts, thereby forming a polycrystalline silicon layer  320   a  having indentations “a” formed with the metal catalyst. 
         [0044]    Referring to  FIG. 3B , a semiconductor layer  320  is formed on the buffer layer  310  by patterning the polycrystalline silicon layer  320   a.  Then, a gate insulating layer  330  is formed on the entire surface of the substrate  300  including the semiconductor layer  320 . The gate insulating layer  330  may be a silicon dioxide layer, a silicon nitride layer, or a combination thereof. 
         [0045]    Subsequently, a metal layer for a gate electrode (not shown) is formed on the gate insulating layer  330  using a single layer of aluminum (Al) or an Al alloy such as aluminum-neodymium (Al—Nd), or a multi-layer having an Al alloy stacked on a chrome (Cr) or molybdenum (Mo) alloy, and a gate electrode  340  is formed to correspond to a channel region of the semiconductor layer  320  by etching the metal layer for a gate electrode using a photolithography process. 
         [0046]    Then, referring to  FIG. 3C , an interlayer insulating layer  350  is formed on the entire surface of the substrate  300  including the gate electrode  340 . Here, the interlayer insulating layer  350  may be formed of a silicon dioxide layer, a silicon nitride layer, or a combination thereof. 
         [0047]    Next, the interlayer insulating layer  350  and the gate insulating layer  330  are etched to form contact holes exposing source and drain regions of the semiconductor layer  320 . Source and drain electrodes  360  and  361  connected to the source and drain regions through the contact holes are formed. In this case, the source and drain electrodes  360  and  361  may be formed of one selected from the group consisting of molybdenum (Mo) or a molybdenum (Mo) alloy, chromium (Cr), tungsten (W) or a (W) tungsten alloy, molybdenum-tungsten (MoW), aluminum (Al) or an aluminum alloy, aluminum-neodymium (Al—Nd), titanium (Ti), titanium-nitride (TiN), or copper (Cu) or a copper (Cu) alloy. Further examples include an alloy of molybdenum-tungsten (MoW), an alloy of aluminum-neodymium (AlNd), or titanium-nitride (TiN). Thus, a TFT including the semiconductor layer  320 , the gate electrode  340 , and the source and drain electrodes  360  and  361  is completed. 
         [0048]      FIGS. 4A to 4C  are cross-sectional views illustrating a process of fabricating a bottom-gate TFT according to another exemplary embodiment of the present invention using the process of fabricating the polycrystalline silicon layer. Except for particular descriptions below, the process will be described with reference to the descriptions in the above exemplary embodiment. 
         [0049]    Referring to  FIG. 4A , a buffer layer  410  is formed on a substrate  400 . To form a gate electrode  420 , a metal layer is formed on the buffer layer  410 , and a gate electrode  420  is formed by etching the metal layer for a gate electrode using a photolithography process. Then, a gate insulating layer  430  is formed on the substrate  400  including the gate electrode  420 . 
         [0050]    Subsequently, referring to  FIG. 4B , an amorphous silicon layer is formed on the gate insulating layer  430  and then crystallized into a polycrystalline silicon layer  440   a  using a metal catalyst in the same manner as the exemplary embodiment of  FIGS. 1A through 1D . The polycrystalline silicon layer  440   a  is subjected to the gettering described in the exemplary embodiment of  FIGS. 2A and 2B  such that the metal catalyst in the polycrystalline silicon layer  440   a  is removed by the gettering, and thus grooves “a” remain. 
         [0051]    Referring to  FIG. 4C , a semiconductor layer  440  is formed by patterning the polycrystalline silicon layer  440   a.  Then, source and drain conductive layers are formed on the semiconductor layer  440  and patterned to form source and drain electrodes  450  and  451 . In this case, the source and drain electrodes  450  and  451  may be formed of one selected from the group consisting of molybdenum (Mo or a molybdenum (Mo) alloy, chromium (Cr), tungsten (W) or a (W) tungsten alloy, molybdenum-tungsten (MoW), aluminum (Al) or an aluminum alloy, aluminum-neodymium (Al—Nd), titanium (Ti), titanium-nitride (TiN), or copper (Cu) or a copper (Cu) alloy. Further examples include an alloy of molybdenum-tungsten (MoW), an alloy of aluminum-neodymium (AlNd), or titanium-nitride (TiN). Thus, a TFT including the semiconductor layer  440 , the gate electrode  420 , and the source and drain electrodes  450  and  451  is completed. 
         [0052]      FIG. 5  is a cross-sectional view of an OLED display device including a top-gate TFT according to another exemplary embodiment of the present invention. Referring to  FIG. 5 , an insulating layer  365  is formed on the entire surface of the substrate  300  including the TFT according to the exemplary embodiment of  FIGS. 3A to 3C . The insulating layer  365  may be an inorganic layer formed of a material selected from the group consisting of silicon dioxide, silicon nitride, and silicate on glass, or an organic layer formed of a polymer selected from the group consisting of a polyimide, a poly(benzocyclobutene), and a polyacrylate. Also, the insulating layer  365  may be formed by stacking the inorganic layer and the organic layer. 
         [0053]    A via hole exposing the source or drain electrode  360  or  361  is formed by etching the insulating layer  365 . A first electrode  370  connected to one of the source and drain electrodes  360  and  361  through the via hole is formed. The first electrode  370  may be an anode or a cathode. When the first electrode  370  is an anode, the anode may be formed of a transparent conductive layer formed of ITO, IZO, or ITZO, and when the first electrode  370  is a cathode, the cathode may be formed of Mg, Ca, Al, Ag, Ba, or an alloy thereof. 
         [0054]    Subsequently, a pixel defining layer  375  having an opening that partially exposes the surface of the first electrode  370  is formed on the first electrode  370 , and an organic layer  380  including an emission layer is formed on the exposed first electrode  370 . The organic layer  380  may further include at least one of a hole injection layer, a hole transport layer, a hole blocking layer, an electron blocking layer, an electron injection layer, and an electron transport layer. Then, a second electrode  385  is formed on the organic layer  380 . Thus, an OLED display device according to the exemplary embodiment of the present invention is completed. 
         [0055]    According to aspects of the present invention as described above, it is possible to remove most of a metal catalyst remaining in a semiconductor layer formed from a polycrystalline silicon layer crystallized using the metal catalyst by gettering using a metal etchant, and thus a TFT having excellent electrical characteristics, a method of fabricating the same, and an OLED display device including the same may be provided. 
         [0056]    Although a few exemplary embodiments of the present invention have been shown and described, it would be appreciated by those skilled in the art that changes may be made in this exemplary embodiment without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.