Abstract:
A driver circuit drives at least one power switch, which circuit comprises a final stage including a complementary pair of power transistors connected to said switch at a common output node. Advantageously, this circuit comprises a respective power-on buffer stage, connected in upstream of each of the power transistors, and a power-on detector associated with each power transistor, the detector associated with one of the power transistors being connected to the buffer stage of the complementary one of the transistors to prevent the power transistors from being turned on simultaneously.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a driver circuit, useful to drive a power switch incorporated in a voltage regulator of the switching type. 
     More particularly, the invention relates to a driver circuit for driving at least one power switch and comprising a final stage that includes a complementary pair of power transistors connected to a control input of said power switch at a common output node. 
     2. Description of the Related Art 
     Voltage regulators of the switching type are widely utilized in many applications on account of their action being effective and accurate. The basic components of a regulator of this type are: one or more power switches, a driver for driving each power switch, passive energy storage elements (capacitors, coils), and a (power management) controller for the control voltage of the driver. 
     In most of the applications, the power switches are formed of discrete components, such as field-effect power transistors, whereas the controller and the drivers are integrated circuits. The drivers and the controller may either be included in the same integrated circuit or in two separate integrated circuits. 
     By providing discrete power switches, different technologies can be used and optimized to fill individual demands. For example, the aim of the switches is the one of minimizing switching and conduction losses, whereas the one of the controller and the drivers is the one of using a broad range of integrated components can be used. 
     It is essential to the overall system efficiency that the power switches be driven in an optimum manner, meaning that in general it should be possible to turn them on/off at a high speed using all the available voltage. This is true in particular for the so-called hard switching systems. 
     A problem that is often encountered in the design of driver circuits is that supply voltages (VCC) must be used that are optimized for the power switches but not for the components available to make the drivers. 
     More generally, the problem that must often be addressed is the one of how to produce fast and efficient drivers, which can operate on higher supply voltages than the highest supply voltages accepted by the devices in which they are incorporated. 
     A typical example of a power switch driver is shown in FIG. 1 of the accompanying drawings. Such driver  1  comprises: a level translator  2  for translation from a first logic voltage, e.g. of 3.3V or 5V, to a power supply voltage VDRV; a pre-driver stage  3  that is referenced to the supply voltage VDRV; and two power switches  4  and  5  operative to respectively close and open an external power switch Mext. 
     As it is shown in FIG. 2, the power switches  4 ,  5  may be MOSFET transistors. In particular, the MOSFET transistor for turning on the external switch Mext may be a P-channel transistor M 1 , and that for turning off the same external switch may be an N-channel transistor M 2 . 
     The external switch Mext usually has a high capacitive load, so that to have it turned on and off rapidly, the transistors M 1 , M 2  have to be large ones in order to deliver and/or take in high current peaks. The pre-driver stage, in its turn, should be adequately dimensioned to drive large MOS transistors with high capacitances. 
     The pre-driver stage  3  is to quickly turn on/off the transistors M 1  and M 2  in complementary manner to avoid cross-conduction, i.e. prevent M 1  and M 2  from being simultaneously conductive during the switchings. Also, the stage  3  should keep power consumption down, at the same time as it should limit the control voltages of the switches  4  and  5 , as well as of all of its components. 
     Commercially available regulators mostly use a discrete N-channel MOS transistor as a power switch, since it can easily be driven in a simple manner. 
     A straightforward solution is provided by the embodiment of FIG. 3, where a driver formed of a succession of inverters  7 ,  8 ,  9 , of progressively larger size is shown. This structure is known as a “horn”, and has an advantage in that it is extremely fast and inherently overcomes the cross-conduction problem. Unfortunately, to provide the power MOS transistor with sufficient overdrive to lessen its conduction resistance, the supply voltage to the driver has to be selected above the highest gate-source voltage of the MOS transistors in the inverter. 
     A prior technical solution allowing the driver to be supplied a higher voltage than the maximum gate-source voltage is illustrated by the schematic of FIG.  4 . This prior solution provides separate drives for the transistors M 1  and M 2 , respectively. Here again, the drive should be appropriate to avoid cross-conduction. The drive signal, moreover, is transferred by turning on/off certain current generators  10  and using clamping structures  11  to limit the gate-source voltage of the power transistor. The difficulty lies here in the static draw of the clamping structures  11  and the signal transfer speed being interlinked. For fast turning on and off, the currents from the generators  10  must be large, and these currents are statically absorbed by the clamping structures  11  after the transition. 
     Turning off the transistors M 1 , M 2  is far more easily effected than turning them on. The gates and sources of the transistors M 1  and M 2  may be simply short-circuited through an additional MOS transistor  13 , that has much smaller dimensions than the ones of the previous M 1  and M 2 . This additional transistor is in its turn driven by a clamping generator  12 , but with a much smaller current than that used for turning on the transistors M 1  and M 2 . 
     To avoid cross-conduction, the power-on and power-off signals may be phase shifted by means of fixed delay blocks  14 ,  15 , as shown in FIG.  5 . 
     A major disadvantage of this prior solution is that the delays must be stretched to prevent malfunction due to process spread and changes in the working conditions. 
     Shown schematically in FIG. 6 is another prior solution wherein the power-on signals to the transistors M 1  and M 2  are conditioned logically, each according to the state of the other of the transistors, M 2  and M 1 . 
     Not even this prior solution can be very effective when the drivers are supplied a low voltage to allow standard logic gates  16  to be used, for otherwise the circuits would become excessively complicated. 
     An improvement on the last-mentioned solution is disclosed in the European Patent Application No. 99830666.6, in the name of STMicroelectronics S.r.l., wherein a large current is used for turning on/off the transistors M 1  and M 2 . This current is reduced after switching. However, the pre-driver stage  3  is to supply a current throughout the charge/discharge phase of the gate of the external transistor Mext, as well as during the phase of charging/discharging the gates of transistors M 1  and M 2 , due to a parasitic capacitor forming between the gate and the drain of each transistor, M 1  and M 2 . 
     Thus, the current in this prior solution is not reduced immediately after having charged the gates of the transistors M 1 , M 2 , but rather after a predetermined time lapse, taken to be adequate to ensure completion of the transition at the driver output. This is schematically shown in the embodiment of FIG.  7 . 
     The current loop is digitally implemented, i.e. a digital count starts as soon as current is flowed through the clamp of transistor M 1 , the current being reduced at the end of the count. This solution, therefore, becomes critical wherever the external transistor Mext is a component unknown beforehand, and involves excessive time and power consumption. 
     A further attempt at solving the driving problems mentioned above is illustrated schematically by the embodiment of FIG.  8 . The signal transition is effected by driving a small current generator  17  and a clamp, the latter driving a buffer in the form of an operational amplifier  18 , e.g. a compensated two-stage Miller amplifier. 
     Not even this prior solution is devoid of drawbacks as regards the switching speed of the operational amplifier, which speed is limited by the SR on the Miller compensation capacitor. 
     Here again, power-off can be readily obtained by means of a small switch toward ground or the supply. Consequently, a buffer used for driving the transistors M 1  and M 2  into the ‘on’ state has usually to be asymmetrical, and will be turned on or enabled only during the power-on phases. 
     BRIEF SUMMARY OF THE INVENTION 
     An embodiment of this invention provides a novel driver circuit, particularly for a power switch, with appropriate structural and functional features to overcome the aforementioned drawbacks of the prior art. 
     Briefly, the driver circuit ensures high speed for the power-on and power-off edges, minimizes power consumption, and avoids stressing the gate of the power transistor. 
     The driver circuit associates, with each power transistor in the complementary pair, a respective power-on buffer stage, each buffer stage being enabled by the ‘off’ state of its complementary transistor. 
     This approach allows the transistors of the output stage to be turned on with no limitations on current and with a short delay time. 
     The features and advantages of a driver circuit according to the invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
     FIG. 1 shows a schematic view of a power switch driver according to the prior art. 
     FIG. 2 shows a schematic view of the driver circuit of FIG. I in further detail. 
     FIG. 3 shows a schematic view of another conventional power switch driver. 
     FIG. 4 shows a schematic view of a further conventional driver circuit. 
     FIG. 5 shows a schematic view of an improvement in the design of FIG.  4 . 
     FIGS. 6,  7  and  8  show a schematic view of respective conventional power switch drivers. 
     FIG. 9 shows a schematic view of a driver circuit according to the invention. 
     FIG. 10 shows a schematic view of a detail of the circuit of FIG.  9 . 
     FIG. 11 is another detail view of FIG.  10 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     With reference to the drawing views, in particular to the embodiment shown in FIG. 9, a driver circuit according to the invention is generally shown at  20  in schematic form and is useful to drive a power switch, e.g. a MOS power transistor Mext outside the circuit. 
     More particularly but not exclusively, the circuit  20  is used to drive a power transistor that is incorporated in a switching type of voltage regulator. 
     The driver  20  includes an output stage  12  comprising a complementary pair of power transistors M 1  and M 2  being connected, at a common node OUT, to the gate terminal of the external transistor Mext and adapted to charge and discharge the external transistor Mext. 
     Provided upstream of each of the transistors M 1 , M 2  is a respective power-on buffer stage  23 ,  24 , also referenced Buff 1 , Buff 2 . In other words, the buffers Buff 1  and Buff 2  are buffers for turning on M 1  and M 2 , respectively. 
     Connected in parallel with each of the buffer stages, Buff 1  and Buff 2 , is a respective transistor, Moff 1  and Moff 2 , for turning off the power transistors M 1  and M 2 . 
     Connected to the power transistors M 1  and M 2  respective power-on detectors consisting, preferably, of a sense transistor, Ms 1  and Ms 2 . This detector is structured to detect the power-on state of a corresponding one of the power transistors, M 1  or M 2 , and pass the information to the buffer stage,  23  or  24 , associated with the other of the power transistors. In this way, the transistors M 1  and M 2  cannot be turned on simultaneously. 
     The power-off transistors Moff 1  and Moff 2  are relatively small, and can be turned on by means of passive clampers, shown at  21  and  22  in the Figure. However, it is not necessary to control their output current because this would be nulled (Vds=0) once the transition is over. 
     The buffers Buff 1  and Buff 2  are driven by means of an enable current  1 , the buffers Buff 1  and Buff 2  being complementary of each other. 
     Advantageously, the MOS sense transistor Ms 1  is connected to the buffer Buff 2  and prevents this complementary buffer Buff 2  from being turned on while the transistor M 1  is ‘on’. 
     Likewise, the sense MOS transistor Ms 2  is connected to the buffer Buff 1  and prevents this complementary buffer Buff 1  from being turned on while the transistor M 2  is ‘on’. 
     The residual current in the transistor M 1 , allowing the buffer Buff 2  to be turned on, is dependent on the dimensional ratio of the transistors M 1  and Ms 1 , and on the construction of the buffer Buff 2 . 
     Likewise, the residual current in the transistor M 2 , allowing the buffer Buff 1  to be turned on, is dependent on the dimensional ratio of the transistors M 2  and Ms 2 , and on the construction of the buffer Buff 1 . 
     A general diagram of the buffer Buff 1 ,  23 , is shown in FIG.  10 . The basic components of the buffer  23  are the following: 
     an output MOS transistor Q 1  connected to turn on the transistor M 1 ; 
     a generator G 1  generating a current  2 I, which may be regarded as a pull-up current, adapted to turn on the transistor Q 1 ; 
     a generator G 2  generating a pull-down current I; 
     a damper CLQ connected to the gate terminal of the transistor Q 1 ; 
     a generator for generating a reference voltage Vref, and an error amplifier, represented by the transistor Q 2 , for computing the difference between an output voltage and a clamping voltage sought; 
     a generator G 3  generating a pull-down current I 1 ; 
     a generator G 4  generating a current  2 I 1 ; 
     a translinear link comprising transistors Qm 3 , Qm 2  and Qm 1 , and a pair of current mirrors comprising respective transistors Qg 1 , Qg 2  and Qg 3 , Qg 4 . 
     While the transistor M 1  is ‘off’, the buffer  23  is also ‘off’. During this power-off phase, the control generator G 1  is ‘off’, the other generator G 2  holding the transistor Q 1  in the ‘off’ state. 
     Likewise, the generator G 4  is ‘off’ and the other generator G 3  holds all the translinear link transistors Qm 1 , Qm 2 , Qm 3  in the ‘off’ state. 
     With the generator G 1  turned on, the transistor Qm 3  is ‘off’, and the gate of the output transistor Q 1 , i.e. the node at a potential VGQ 1 , goes up. The output transistor Q 1  draws a large current from the output node, quickly turning on the power transistor M 1 . 
     The generator G 4  is turned on concurrently with the generator G 1 , so that the diode-connected MOS transistors, represented by Qm 1  and Qm 2 , are caused to conduct. As the gate of the transistor M 1 , i.e. the node at a potential VGM 1 , drops with respect to the supply voltage by an amount equal to the voltage Vref plus the threshold voltage of the transistor Qm 3 , the transistor Q 2  goes ‘on’ and closes the feedback. The controlled quantity is a voltage Vgs(M 1 ). 
     The drain current of the transistor Q 2  is mirrored by the mirror comprising the transistors Qg 1 , Qg 2  and by the other mirror comprising the transistors Qg 3 , Qg 4 , thus bringing the potential VGQ 1  down and causing the transistor Qm 3  to conduct. 
     The buffer circuit  23  attains equilibrium when the sum of the currents at the node VGQ 1  is zero. In equilibrium, the transistor Qm 3  is turned on. The currents I 1  and I, and the dimensions of the MOS transistors Qm 1 , Qm 2 , Qm 3 , Q 1 , Qg 1 , Qg 2 , Qg 3  and Qg 4  may be selected to satisfy the following relation: 
     
       
           Id ( Qm   3 )= Id ( Qg   4 )= I   1   
       
     
     The current Id(Q 1 ) equals Id(Q 2 ) and is the same order of magnitude as the current I 1 , which is much smaller than the inrush current of Q 1 . Voltage VGQ 1  is lower than the operating voltage of the damper CLQ, which is therefore held ‘off’. 
     The damper CLQ is only used at power-on, before the feedback comes into effect, to protect the gate-source of the output transistor Q 1 . 
     The transistor Q 2  also functions as a damper on the voltage drop Vgs(M 1 ) before the feedback comes into effect. 
     The construction of the buffer stage  23  includes two gain nodes VGM 1  and VGQ 1 . With the transistor Qm 3  turned on, the impedance at the node at potential VGQ 1  is sure to be low and the corresponding pole sufficiently high to ensure stability. 
     By having no compensating capacitors connected to the node at potential VGQ 1 , the buffer  23  will exhibit a high slew rate and be very fast. 
     As a safeguard against cross conduction, a resistor Rp is connected, as shown in FIG. 11, between the node at potential VGQ 1  (gate of Q 1 ) and the node at potential VGQI 1  (connected to the linear link). 
     Advantageously, the drain of the sense transistor Ms 2  is connected to the node at potential VGQ 1 , as clearly shown in FIG.  11 . 
     When the buffer  24  is turned on, and the transistor M 2  is still ‘on’, VGQ 1 =0 and the resistor Rp will limit the current through the transistor Qm 3 . 
     In this situation, it is: 
     
       
           Id ( Ms   2 )= I+Id ( Qm   3 ) 
       
     
     and this value multiplied by the dimensional ratio of M 2  to Ms 2  gives the maximum cross-conduction current in the power transistors M 1  and M 2 . 
     The above considerations hold true also for the buffer  24  associated with the sense transistor Ms 1 . The construction of the buffer  24  is the same as that of the buffer  23  discussed hereinabove except that the polarities of the elements are reversed because the power transistor M 2  driven by the buffer  24  is complementary to the power transistor M 1  driven by the buffer  23 . Accordingly, the buffer  24  will be no further described. 
     The buffer  23  shows certain oscillations concurrently as the output voltage VOUT goes up. In this situation, the Miller capacitor of the transistor M 1  is being charged, and the transistor Q 1  is to supply the necessary current. The loop of buffer  23  may show some instability if the supply current is much larger than the equilibrium current. However, the oscillations are harmless because the current from the transistor M 1  is unidirectional and cannot discharge the gate of the external power transistor Mext. The amplitude of these oscillations is greater at the node at potential VGQ 1 , and is near-monotonic at the node at potential VGM 1 , the output voltage VOUT being actually monotonic. 
     The driver circuit  20  offers a number of advantages, of which the fact that high switching speeds can be achieved at a reduced overall power consumption of the circuit is foremost. 
     Furthermore, the gate terminal of the power transistor is protected in a more effective manner and with less problems of reliability. 
     The power consumption of the driver circuit, moreover, is unrelated to the size of the switch. 
     Changes can be made to the invention in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims, but should be construed to include all methods and devices that are in accordance with the claims. Accordingly, the invention is not limited by the disclosure, but instead its scope is to be determined by the following claims.