Abstract:
A self clocking data extraction method is shown that is tolerant of timing jitter, data skew and the presence of multiple edges per data bit. The data is sampled when the following criterion are met: There is at least one edge across any track (the clock assures this criteria is met), followed by no edges in any track for a defined period of time (T), and all edge activity must occur in a period of time less than T (to keep from detecting false samples). This method enables the handling of trace data signals with poor electrical characteristics that can not be recorded by methods known in the prior art.

Description:
CLAIM OF PRIORITY 
       [0001]    This application claims priority under 35 U.S.C. 119(e)(1) to U.S. Provisional Application No. 61/584,950 filed Jan. 10, 2012. 
     
    
     TECHNICAL FIELD OF THE INVENTION 
       [0002]    The technical field of this invention is self clocking data extraction. 
       BACKGROUND OF THE INVENTION 
       [0003]    In a system where data is transferred from point A to point B using Double Data Rate (DDR) format, and signal quality is diminished by signal modulation, transmission line effects, and/or signal coupling, it may be difficult or impossible to transfer data reliably using conventional DDR data extraction schemes. One such environment is trace data collection within development systems. Often the electrical characteristics of the data path are compromised by poor board layout (transmission line stubs or impedance out of spec), miss-match of driver, transmission line, connector impedances, or signal coupling. These systems provide a harsh environment for reliable data extraction. 
       SUMMARY OF THE INVENTION 
       [0004]    A self clocking data extraction method is shown that is more tolerant of timing jitter, data skew and the presence of multiple edges per data bit. This invention enables the handling of trace data signals with poor electrical characteristics that cannot be recorded by methods known in the prior art. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]    These and other aspects of this invention are illustrated in the drawings, in which: 
           [0006]      FIG. 1  shows poorly implemented DDR signaling; 
           [0007]      FIG. 2  shows DDR data extraction in the prior art; 
           [0008]      FIG. 3  shows the timing variations in DDR signaling; 
           [0009]      FIG. 4  shows oversampled data synchronous to the bit period; 
           [0010]      FIG. 5  illustrates the edge detection used in the invention; 
           [0011]      FIG. 6  shows the creation of the data values; and 
           [0012]      FIG. 7  illustrates an apparatus constructed to practice this invention. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0013]    Historically DDR data extraction relies on excellent=signal quality, constant or near constant skew between signals, and in some cases auto calibration which places data strobes at the optimal position in bit periods. Extraction becomes unreliable when signals transition multiple times within a bit period or have skew which is changes over one or more bit periods. 
         [0014]    In a poorly implemented system, the DDR signaling may look like that shown in  FIG. 1 . Further some of these signals may be skewed in relation to each other (not shown in the figure). 
         [0015]    A common characteristic of the poor signaling shown in  FIG. 1  is that both the clock and data signals reach a stable value  101  at some point (generally towards the end of the bit period). This characteristic together the fact that the clock will have at least one edge during a bit period enables the use the following data extraction criteria. The data is sampled when the following criterion is met:
       There is at least one edge  201  across any track (the clock assures this criteria is met) followed by   There are no edges  202  in any track for a defined period of time Y.       
 
         [0018]    All edge activity must occur in a period of time less than T (to keep from detecting false samples) 
         [0019]    This is shown in  FIG. 2 . 
         [0020]    Note that the sampling point  301  can vary dramatically from bit to bit depending on the skew of the signals, the signals that do not change, or dynamic changes induced in edge position (those induced by ground and power supply fluctuations or other phenomenon). This is illustrated in  FIG. 3 . Note the following:
       The skew between DDR Data[n] and DDR Data[ 0 ];   The operation when no data bits change; and   The changes in the position of sample_data  302 .       
 
         [0024]    Two types of implementations are described in the following paragraphs:
       Oversampled data is created synchronous to the bit period; and   Oversampled data is created asynchronous to the bit period.       
 
         [0027]    Either version may be implemented with oversampling created with either clocked oversampling or oversampled values created with a combination of registers and delay lines. 
         [0028]    A digital view of the incoming signals over time is created as shown in  FIG. 4  with the series of sampled values  401  either synchronous or asynchronous to the incoming data&#39;s bit period. 
         [0029]    In example one, sampled data is created synchronous to the bit period of the incoming data. In this example 32 samples  402  are exactly one bit period. The choice of a 32 samples in a group is arbitrary and can be different. For each group of 32 samples, samples n and n+1 are compared with a difference in these values defining a signal edge (change in state). When jitter is considered, no more than two data bits can be extracted from any group of 32 samples. Thirty-three 33 samples (32 of the current group+the last sample of the prior group) are used to detect edges. The edge detection method is used as shown in  FIG. 5 . 
         [0030]    The extract data hardware identifies the bits in the series of sampled values of each channel that are to be used as data. Sample_data[15:00] is used to extract data in Window A while sample data[31:16] is used to extract data in Window B. The sampled data[n] is Logically ANDed with delayed versions of the sample value[n]. The ANDed results[15:00] are logically ORed to create the extracted data in Window A. Likewise the ANDed results[31:16] are logically ORed to create the extracted data in Window B. 
         [0031]    There are four possibilities each clock period:
       Window A and Window B both produce data bits (data[m]=DB, DA;   Window A produces a data bit/Window B produces no data bit (data[m]=NULL, DA);   Window A produces a data bit/Window B produces no data bit (data[m]=NULL, DB); and   Window A and Window B produce no data bits (data [m]=NULL, NULL)       
 
         [0036]    The number of data values produced is two when sample_data[15:00] is non-zero and sample_data[31:16] is non-zero. If only one of these values is non-zero then only one data bit is produced. When both are zero no data is produced. A data value is created by stacking the extracted data bits as shown in  FIG. 6 . 
         [0037]    In another example we will group 32 samples to demonstrate DDR extraction with an unknown bit period. The 32 samples are divided into four windows of 8 samples for data extraction purposes. The sample period must be high enough to assure that only one sample data value falls into a window at all times. In this example this requires the eight or more samples per incoming bit period. Oversampled data sample positions m and m+1 are compared with a difference defining an edge. Thirty-three 33 samples (32 of the current samples+the last sample of the prior group) are used to detect edges. 
         [0038]    Again the choice of a 32 samples in a group is arbitrary and the number of samples per window can be different. This implementation operates in the same manner as when the bit period is known, but with zero to four data values created from each group of 32 samples. Data extraction using sample_data is handled as follows:
       Sample_data[07:00] is used to extract data in Window A;   Sample_data[15:08] is used to extract data in Window B;       
 
         [0041]    Sample_data[23:16] is used to extract data in Window C; and
       Sample_data[31:24] is used to extract data in Window D.       
 
         [0043]    The data extraction step logically ANDs the sample_data[n] with delayed versions of the sample value[n] within a window. The ANDed results are logically ORed to create the extracted data within this window. 
         [0044]    The extraction with non-DDR data can be done in the same manner as DDR data by qualifying the generation by a logic 0 clock value when data is to be sampled on this clock edge and by a logic 1 value when data is to be sampled on this clock edge. 
         [0045]      FIG. 7  is a block diagram of an apparatus practicing this invention. Plural edge detectors  100  to  109  service corresponding input signals on channel[ 0 ] to channel[n]. 
         [0046]    Representative edge detector  109  is shown as including delay line  111  which can be digital or analog and produces a plurality of delayed signals on tap[ 0 ] to tap[n]. Change in state detector  112  detects edges in the corresponding input channel. This is supplied to OR gate  120  as the edge[n] signal. OR gate  120  receives such an edge signal for each input channel. 
         [0047]    The output of OR gate  120  drives delay line  130 . Delay line  130  produces a plurality of delayed signals including tap[m]. Stable detector  140  determines when a predetermined number of stable states occurs. AND gate  150  receives the tap[m] signal from delay line  130  and the stability signal stable detector  140 . The output of AND gate  150  is the sample_now signal. Data FIFO acquires the corresponding signal from each edge detector  100  to  109  upon occurrence of the sample_now signal.