Abstract:
A semiconductor device production method includes: forming a semiconductor region including a first region, a second region connecting with the first region and having a width smaller than that of the first region, and a third region connecting with the second region and having a width smaller than that of the second region; forming a gate electrode including a first part crossing the third region and a second part extending from the first part across the first region; forming a side wall insulation film on the gate electrode to cover part of the second region while exposing the remaining part of the second region; implanting a second conductivity type impurity into the first region and the remaining part of the second region; performing heat treatment; removing part of the side wall insulation film, and forming a silicide layer on the first region and the remaining part of the second region.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2010-256762, filed on Nov. 17, 2010, the entire contents of which are incorporated herein by reference. 
       FIELD 
       [0002]    The embodiments discussed herein are related to a semiconductor device production method and a semiconductor device. 
       BACKGROUND 
       [0003]    Dynamic threshold voltage MOS (DTMOS) transistors, i.e. MOS transistors with a gate electrode electrically connected to the body (well), have been developed (see, for instance, Japanese Unexamined Patent Publication (Kokai) No. 2002-299633). A DTMOS transistor can operate at a high speed at a low voltage due to a decrease in threshold voltage caused by applying a voltage to the well. 
       SUMMARY 
       [0004]    According to an aspect of the invention, a semiconductor device production method includes: forming an element-separating insulation film in a semiconductor substrate to define a semiconductor region that includes a first region, a second region connecting with the first region and having a width smaller than a width of the first region, and a third region connecting with the second region and having a width smaller than the width of the second region; implanting a first conductivity type impurity into the semiconductor region to form a well region; forming a gate insulation film on the well region; forming, on the gate insulation film, a gate electrode that includes a first part crossing the third region in width direction of the third region and a second part extending from the first part across the first region; forming a side wall insulation film on the lateral face of the gate electrode to cover part of the second region while exposing the remaining part of the second region; implanting a second conductivity type impurity that has a conductivity type opposite to the first conductivity type into the first region and the remaining part of the second region using the gate electrode and the side wall insulation film as mask; performing heat treatment to diffuse the second conductivity type impurity; removing part of the side wall insulation film using a chemical, and forming a silicide layer on the first region and the remaining part of the second region after the removing of part of the side wall insulation film using the chemical. 
         [0005]    The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims. 
         [0006]    It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0007]      FIGS. 1P ,  1 A,  1 B,  1 C to  12 P,  12 A,  12 B, and  12 C are schematic plan views and schematic cross-sectional views illustrating main steps of producing a DTMOS transistor according an embodiment. 
           [0008]      FIG. 13  is a schematic plan view of the DTMOS transistor of Comparative example 1. 
           [0009]      FIG. 14  is a schematic plan view of the DTMOS transistor of Comparative example 2. 
           [0010]      FIGS. 15P , and  15 A 1  to  15 A 4  are a schematic plan view and schematic cross-sectional views of the DTMOS transistor of Comparative example 2. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0011]    Before describing the DTMOS transistor according to an embodiment of the invention, the DTMOS transistors of Comparative examples 1 and 2 are illustrated first. 
         [0012]      FIG. 13  is a schematic plan view of the DTMOS transistor of Comparative example 1. An n-type MOS transistor is taken as an example for description. An element-separating insulation film  102  is formed on the silicon substrate, and a rectangular semiconductor region  105  is defined inside the surrounding element-separating insulation film  102 . A p-type well is formed over the entire semiconductor region  105 . 
         [0013]    A gate electrode structure  107  of electrically conductive material is formed in the semiconductor region  105 . The gate electrode structure  107  consists of a boundary portion  107   a  and a gate electrode portion  107   b , and has a T shape with the boundary portion  107   a  and the gate electrode portion  107   b  representing the horizontal and the vertical segment, respectively. The boundary portion  107   a  extends across the semiconductor region  105  to define the contact region  105   a , which is located on one side (upper side in the diagram) of the boundary portion  107   a , and the transistor region  105   b , which is located on the other side (lower side in the diagram) of the boundary portion  107   a.    
         [0014]    The gate electrode portion  107   b  extends across the transistor region  105   b  to form the gate electrode of the MOS transistor. N-type impurity has been added in each part of the transistor region  105   b  separated by the gate electrode portion  107   b  to form source/drain regions. The contact plugs  118   t  are electrically connected to source/drain regions. 
         [0015]    The contact region  105   a  contains doped p-type impurity. The n-type impurity implanting window IWn and the p-type impurity implanting window IWp are shown by broken lines. The n-type impurity doped region and the p-type impurity doped region are separated at the center of the boundary portion  107   a.    
         [0016]    A contact plug  118  that is electrically connected to the p-type well is located on the contact region  105   a . The contact plug  118  extends upward to the boundary portion  107   a , and a voltage can be applied to both the p-type well and the gate electrode structure  107  via the contact plug  118 . The DTMOS transistor of Comparative example 1 is thus configured. 
         [0017]    The region  107 C (indicated by upper-right diagonal lines), which is the n-type impurity doped part of the boundary portion  107   a  located on the semiconductor region  105 , forms a capacitor electrode and develops a parasitic capacitance for the MOS transistor formed in the transistor region  105   b . A smaller parasitic capacitance is more preferable. 
         [0018]      FIG. 14  is a schematic plan view of the DTMOS transistor of Comparative example 2. The differences from Comparative example 1 are described below. In Comparative example 2, the shape of the semiconductor region  205  is different from that of the semiconductor region  105  of Comparative example 1. 
         [0019]    The semiconductor region  205  of Comparative example 2 consists of a rectangular first region  203  and a second region  204  extending from the width-direction center part of the first region  203 . The second region  204  is narrower than the first region  203 . The second region  204  has a constant width. 
         [0020]    The gate electrode structure  207  has a T shape as in the case of Comparative example 1. The boundary portion  207   a  extends across the second region  204  to separate the semiconductor region  205  into two parts, namely, the contact region  205   a  located on one side (upper side in the diagram) of the boundary portion  207   a  and the transistor region  205   b  located on the other side (lower side in the diagram) of the boundary portion  207   a.    
         [0021]    The first region  203  contains contact plugs  218   t  that are electrically connected to source/drain regions. The contact region  205   a  contains a contact plug  218  that is electrically connected to the p-type well and the boundary portion  207   a.    
         [0022]    In Comparative example 2, the second region  204  has a smaller width than the first region  203 , and the boundary portion  207   a  extends across the second region  204  of the semiconductor region  205 . This serves to shorten the part of the boundary portion  207   a  that exists on the semiconductor region  205 . Accordingly, this reduces the size of the capacitor electrode region  207 C which generates a parasitic capacitance. Thus, this serves to reduce the parasitic capacitance. 
         [0023]    Problems with the DTMOS transistor of Comparative example 2 are described below with reference to  FIGS. 15P , and  15 A 1  to  15 A 4 . 
         [0024]      FIG. 15P  is a schematic plan view of the DTMOS transistor of Comparative example 2.  FIG. 15P  illustrates the side wall insulation film  209  formed on the lateral face of the gate electrode structure  207 , viewed from the transistor side. The side wall insulation film  209  acts as mask for impurity implantation (SD implantation) to form source/drain regions. The broken line  209   a  in  FIG. 15P  indicates the position of the edge of the side wall insulation film  209  during the SD implantation. 
         [0025]    After the SD implantation, silicide layers are formed over some parts including the source/drain region. Before the silicide layer formation, chemical treatment is carried out to remove natural oxide film from the substrate surface. As this chemical treatment proceeds, the side wall insulation film  209  is etched. The continuous line  209   b  in  FIG. 15P  indicates the position of the edge of the side wall insulation film  209  that has been etched by the chemical treatment. 
         [0026]    FIGS.  15 A 1  to  15 A 4  are views of the AA′ cross section that crosses the second region  204  between the first region  203  and the boundary portion  207   a  as seen in  FIG. 15P , and illustrate major steps of producing the DTMOS of Comparative example 2. 
         [0027]    FIG.  15 A 1  illustrates the SD implantation step. Before the SD implantation, n-type impurity has been implanted in the p-type well pw using the gate electrode portion  207   b  as mask to form an extension region  208 . 
         [0028]    After the formation of the extension region  208 , the side wall insulation film  209  is formed on the lateral face of the gate electrode portion  207   b . The gate electrode portion  207   b  is narrower than the second region  204 , but the entire width of the side wall insulation film  209  (distance from one edge  209   a  to the other edge  209   a  with the gate electrode portion  207   b  between them) during the SD implantation is larger than that of the second region  204 . Thus, the edge  209   a  of the side wall insulation film  209  is located on the element-separating insulation film  202  outside the second region  204 . 
         [0029]    The n-type impurity that is implanted during the SD implantation between the first region  203  and the boundary portion  207   a  enters the element-separating insulation film  202 , instead of the semiconductor region, to form an impurity-implanted insulation film portion  202   n.    
         [0030]    FIG.  15 A 2  illustrates the impurity-activation annealing step. The n-type impurity implanted in the insulation film portion  202   n  in the SD implantation step does not diffuse significantly during the activation annealing step. 
         [0031]    FIG.  15 A 3  illustrates the chemical treatment step to remove natural oxide film. As the chemical treatment proceeds, the side wall insulation film  209  is etched to expose the extension region  208  located on the second region  204 . 
         [0032]    FIG.  15 A 4  illustrates the silicide formation step. A silicide layer  214  is formed on the exposed second region  204 , overlapping the extension region  208 , and at the same time the silicide layer  214   g  is formed on top of the gate electrode portion  207   b.    
         [0033]    The silicide layer  214  formed on the second region  204  extends down more deeply than the extension region  208 . This causes the p-type well pw and the silicide layer  214  to come in contact, leading to an increased junction leak. In  FIG. 15P , the silicide layer  214  formed between the first region  203  and the boundary portion  207   a  and extending more deeply than the extension region  208  is indicated by upper-right diagonal lines. 
         [0034]    In the first region  203  during the SD implantation, the impurity is implanted in the p-type well outside the side wall insulation film  209  to form source/drain regions that are higher in concentration and extend more deeply than the extension region  208 . Furthermore, the impurity implanted in the source/drain region is diffused by the activation annealing. In the first region  203 , it is possible to form a silicide layer shallower than the region dosed with the impurity by SD implantation. This serves to reduce the above-mentioned junction leak in the first region  203 . 
         [0035]    Described below is the DTMOS transistor according to an embodiment of the invention.  FIGS. 1P ,  1 A,  1 B,  1 C to  12 P,  12 A,  12 B, and  12 C are schematic plan views and schematic cross-sectional views illustrating main steps of producing the DTMOS transistor according to the embodiment. Here, “P” denotes the plan view and “A”, “B”, and “C” denote the cross-sectional views of the AA′, BB′, and CC′ cross sections, respectively, indicated in the plan view. Many DTMOS transistors of the same structure are formed simultaneously at regular intervals on one wafer, though diagramed and described below is only one DTMOS transistor to represent them. The formation of an n-type MOS transistor is described as a typical case. 
         [0036]    See  FIGS. 1P , and  1 A to  1 C. On a semiconductor substrate  1 , for instance a p-type silicon substrate, an element-separating insulation film  2  is formed by, for instance, shallow trench isolation (STI) to define a semiconductor region  5  surrounded by the element-separating insulation film  2 . The element-separating insulation film  2  formed by STI has a thickness of, for instance, about 300 nm to 400 nm. 
         [0037]    The semiconductor region  5  includes a first region  3  and a second region  4 . The first region  3  has, for instance, a rectangular shape with a width w 3  of about 300 nm to 500 nm. The second region  4  extends from the width-direction center part of the first region  3 , and has a smaller width than the first region  3 . 
         [0038]    In this embodiment, the second region  4  consists of a main portion  4   a  and a connection portion  4   b  that connects the main portion  4   a  to the first region  3 . The main portion  4   a  has a rectangular shape with a smaller width than that of the first region  3 , and the connection portion  4   b  has a trapezoidal shape with its width increasing towards the first region  3 . The main portion  4   a  has a width w 4   a  of, for instance, about 100 nm to 150 nm, and the connection portion  4   b  has a width  4   wb  of, for instance, about 200 nm to 250 nm at its center. 
         [0039]    See  FIGS. 2P , and  2 A to  2 C. A resist pattern RP 1  that has an implantation window IW 1  that exposes the entire semiconductor region  5  is formed. Using the resist pattern RP 1  as mask, phosphorus, for instance, is implanted under the conditions of an accelerating energy of 300 keV to 400 keV and a dose of 5×10 12  cm −2  to 5×10 13  cm −2  to form an n-type well nw that is deeper than the element-separating insulation film  2 . 
         [0040]    Then, for instance, boron is implanted under the conditions of an accelerating energy of 30 keV to 60 keV and a dose of 5×10 12  cm −2  to 5×10 13  cm −2  to form a p-type well pw that is shallower than the element-separating insulation film  2 . Furthermore, for instance, boron is implanted under the conditions of an accelerating energy of 5 keV to 20 keV and a dose of 5×10 12  cm −2  to 5×10 13  cm −2  for channel implantation. Subsequently, the resist pattern RP 1  is removed. 
         [0041]    An n-type DTMOS transistor is produced in the p-type well pw in each of the semiconductor regions  5  formed on the same wafer. These DTMOS transistors are electrically separated from each other by the n-type well nw. 
         [0042]    See  FIGS. 3P , and  3 A to  3 C. For instance, a silicon oxide film with a thickness of 1 nm to 2 nm is grown by thermal oxidation on the semiconductor region  5  to form a gate insulation film  6 . Then, for instance, a polysilicon film with a thickness of 70 nm to 150 nm is deposited by chemical vapor deposition (CVD) over the entire substrate  1 . 
         [0043]    A resist pattern that has the same shape as the intended gate electrode structure  7  is formed on the polysilicon film, and this resist pattern is used as mask to pattern the polysilicon film, leaving the gate electrode structure  7 . This etching also removes the gate insulation film  6  located outside the gate electrode structure  7 . Subsequently, this resist pattern is removed. 
         [0044]    The gate electrode structure  7  (the gate electrode  7 ) includes a boundary portion  7   a  and a gate electrode portion  7   b . The boundary portion  7   a  extends across the main portion  4   a  of the second region  4  in the width direction to separate the semiconductor region  5  into two parts, namely the contact region  5   a  located on one side (upper side in the diagram) of the boundary portion  7   a  and the transistor region  5   b  located on the other side (lower side in the diagram) of the boundary portion  7   a.    
         [0045]    The portion of the second region  4  that is included in the transistor region  5   b  (i.e. the part of the main portion  4   a  that is located on the first region  3  side of the boundary region  7   a , and the connection portion  4   b ) is hereinafter referred to as the collateral transistor region  4   c . The transistor region  5   b  includes the first region  3  and the collateral transistor region  4   c . Hereinafter, as compared with the collateral transistor region  4   c , the first region  3  is occasionally referred to as the main transistor region  3 . The boundary portion  7   a  has a width of, for instance, 100 nm to 200 nm (the direction laterally crossing the main portion  4   a  is defined as the length direction). 
         [0046]    The gate electrode portion  7   b  extends across the transistor region  5   b  from the length-direction center part of the boundary portion  7   a  to form the gate electrode of a MOS transistor to be formed in the transistor region  5   b . Here, the direction perpendicular to the extending direction of the gate electrode portion  7   b  is defined as the width direction of the main transistor region  3 . The width of the gate electrode portion  7   b  (gate length) is, for instance, 50 nm. The width of the gate electrode portion  7   b  is smaller than that of the main portion  4   a  and connection portion  4   b  of the second region  4 , and included in the width of the collateral transistor region  4   c . The boundary portion  7   a  and the gate electrode portion  7   b  form a T-shape gate electrode structure  7 . 
         [0047]    The AA′ cross section crosses the contact region  5   a , and the BB′ cross section crosses the connection portion  4   b  of the collateral transistor region  4   c . The CC′ cross section crosses the main transistor region  3 . 
         [0048]    In the DTMOS transistor of this embodiment, as in the case of Comparative example 2, the boundary portion  7   a  extends across the second region  4 , which is narrower than the first region  3 , of the semiconductor region  5 . This is intended to reduce the parasitic capacitance. 
         [0049]    See  FIGS. 4P , and  4 A to  4 C. A resist pattern RP 2  that has an implantation window IW 2  that exposes the transistor region  5   b  of the semiconductor region  5  and covers the contact region  5   a  is formed. The contact-side edge of the implantation window IW 2  (and the boundary between the implantation window IW 3  for n-type impurity implantation and the implantation window IW 4  for p-type impurity implantation described later with reference to  FIG. 6P  etc. and  FIG. 7P  etc., respectively) is located at a position within the width, for instance at the center of the width, of the boundary portion  7   a.    
         [0050]    Using the resist pattern RP 2  and the gate electrode structure  7  as mask, boron, for instance, is implanted under the conditions of an accelerating energy of 5 keV to 20 keV and a dose of 5×10 12  cm −2  to 5×10 13  cm −2 , or indium, for instance is implanted under the conditions of an accelerating energy of 20 keV to 70 keV and a dose of 5×10 12  cm −2  to 5×10 13  cm −2 , in order to perform pocket implantation. 
         [0051]    Then, for instance, arsenic is implanted under the conditions of an accelerating energy of 1 keV to 4 keV and a dose of 5×10 14  cm −2  to 5×10 15  cm −2  to form an extension region  8 . Subsequently, the resist pattern RP 2  is removed. 
         [0052]    See  FIGS. 5P , and  5 A to  5 C. To cover the gate electrode structure  7 , for instance, a silicon oxide film with a thickness of 50 nm to 100 nm is deposited by CVD (film forming temperature 400° C. to 600° C.) over the entire surface of the substrate  1 . This silicon oxide film is etched by anisotropic dry etching, leaving the side wall insulation film  9  on the lateral face of the gate electrode structure  7 . The side wall insulation film  9  has a thickness of, for instance, 50 nm to 100 nm. Here, the side wall insulation film  9  may be formed of, for instance, nitride silicon, instead of silicon oxide, produced by CVD (film forming temperature 400° C. to 600° C.). 
         [0053]    As seen from  FIG. 5P , the entire width of the side wall insulation film  9  (distance from one edge to the other with the gate electrode structure  7  between them) is large on the boundary portion  7   a , decreases near the joint between the boundary portion  7   a  and the gate electrode portion  7   b , and becomes constant as the gate electrode portion  7   b  extends. On the extended segment of the gate electrode portion  7   b , the overall width of the side wall insulation film  9  is larger than that of the main portion  4   a  of the second region  4 . 
         [0054]    In the connection portion  4   b , on the other hand, the collateral transistor region  4   c  increases in width towards the main transistor region  3 . As the width of the collateral transistor region  4   c  increases, the edge of the side wall insulation film  9  and that of the collateral transistor region  4   c  intersect each other. The overall width of the side wall insulation film  9  is larger than that of the second region  4  on the contact side of the intersection IS, while the overall width of the side wall insulation film  9  is smaller than that of the second region  4  on the transistor side of the intersection IS. As a result, in the connection portion  4   b  to the first region  3 , the second region  4  has an exposed region PA protruding from the side wall insulation film  9 . 
         [0055]    The BB′ cross section in  FIG. 5B  is located slightly away from the intersection IS towards the contact where the overall width of the side wall insulation film  9  is larger than that of the second region  4 . In the BB′ cross section, the outer edge of the side wall insulation film  9  is on the element-separating insulation film  2 . 
         [0056]    See  FIGS. 6P , and  6 A to  6 C. A resist pattern RP 3  that has an implantation window IW 3  that exposes the transistor region  5   b  and covers the contact region  5   a  is formed. 
         [0057]    Using the resist pattern RP 3 , the gate electrode structure  7 , and the side wall insulation film  9  as mask, phosphorus, for instance, is implanted (SD implantation) under the conditions of an accelerating energy of 4 keV to 10 keV and a dose of 2×10 15  cm −2  to 1×10 16  cm −2  to form source/drain regions  10  that are n +  type regions higher in concentration and deeper than the extension region  8 . 
         [0058]    The impurity is implanted in the protruding region PA of the collateral transistor region  4   c . The impurity-implanted region formed by SD implantation in the protruding region PA is also called a source/drain region  10 . 
         [0059]    Here, the n-type impurity is implanted in those parts of the gate electrode structure  7  and the side wall insulation film  9  which are exposed in the implantation window IW 3  and used as mask. Subsequently, the resist pattern RP 3  is removed. 
         [0060]    As seen from  FIGS. 6C and 6P , in the main transistor region  3 , the n-type impurity is implanted in the p-type well pw outside the side wall insulation film  9  to form source/drain regions  10 . At the same time, the n-type impurity is also implanted in the element-separating insulation film  2  outside the p-type well pw to form an insulation film portion  2   n  that contains the n-type impurity. 
         [0061]    As seen from  FIGS. 6B and 6P , in the BB′ cross section, the outer edge of the side wall insulation film  9  is located on the element-separating insulation film  2  and therefore, the n-type impurity is implanted in the element-separating insulation film  2  outside the side wall insulation film  9  to form an insulation film portion  2   n  that contains the n-type impurity. 
         [0062]    See  FIGS. 7P , and  7 A to  7 C. A resist pattern RP 4  that has an implantation window IW 4  that exposes the contact region  5   a  and covers the transistor region  5   b  is formed. Using the resist pattern RP 4 , the gate electrode structure  7 , and the side wall insulation film  9  as mask, boron, for instance, is implanted under the conditions of an accelerating energy of 2 keV to 5 keV and a dose of 2×10 15  cm −2  to 1×10 16  cm −2 . 
         [0063]    As seen from  FIGS. 7A and 7P , a p +  type region  11  is formed in the p-type well pw in the contact region  5   a . The p-type impurity is also implanted in the element-separating insulation film  2  outside the p-type well pw to form an insulation film portion  2   p  that contains the p-type impurity. Here, the p-type impurity is implanted in those parts of the gate electrode structure  7  and the side wall insulation film  9  which are exposed in the implantation window IW 4  and used as mask. Subsequently, the resist pattern RP 4  is removed. 
         [0064]    Note that only an n-type MOS transistor is formed in the present embodiment, but it is also possible to form an n-type MOS transistor and a p-type MOS transistor simultaneously on one wafer. In this case, a p +  type region  11  can be formed by applying the p-type impurity implantation step performed here to form a source/drain region in the p-type MOS transistor. 
         [0065]    See  FIGS. 8P , and  8 A to  8 C. By using the rapid thermal annealing (RTA) method, heat treatment is carried out at, for instance, 1,000° C. to 1,100° C. for a period of 3 seconds or shorter to achieve activation annealing of the implanted n-type and p-type impurities. This activation annealing works to diffuse the implanted impurity over a distance of, for instance, 30 nm to 60 nm. 
         [0066]    The n-type impurity implanted in the source/drain region  10  and the p-type impurity implanted in the p +  type region  11  are diffused to cause the source/drain region  10  and the p +  type region  11  to expand in the in-plane direction and the depth direction, respectively. The expanded parts resulting from the diffusion in the source/drain region  10  and the p +  type region  11  are hereinafter referred to as diffusion region  10   d  and diffusion region  11   d , respectively. 
         [0067]    As the diffusion region  10   d  and the diffusion region  11   d  expand under the side wall insulation film  9 , the edge shape of the diffusion region  10   d  and the diffusion region  11   d  are conformal to the edge shape of the side wall insulation film  9 . In  FIG. 8P , the diffusion region  10   d  and the diffusion region  11   d  expanding below the side wall insulation film  9  are indicated by upper-right and upper-left diagonal lines, respectively. The directions of diffusion of the impurity are indicated by arrows. 
         [0068]    As seen from  FIGS. 8C and 8P , in the main transistor region  3 , the impurity is implanted in the area laterally outside the side wall insulation film  9  to form source/drain regions  10 , and the impurity diffuses in the horizontal direction to get under the side wall insulation film  9 . 
         [0069]    As seen from  FIGS. 8B and 8P , no source/drain region  10  is formed outside the side wall insulation film  9  at the position of the BB′ cross section of the collateral transistor region  4   c . Consequently, it is impossible for impurity diffusion to take place from source/drain regions  10  outside the side wall insulation film  9 . Here, the impurity implanted in the element-separating insulation film portion  2   n  does not diffuse significantly. 
         [0070]    However, a protruding region PA is formed in the collateral transistor region  4   c  at a position slightly away from the BB′ cross section towards the main transistor region  3 , and the protruding region PA also contains the impurity doped by SD implantation. The impurity implanted in the protruding region PA diffuses upward in the diagram along the edge of the collateral transistor region  4   c , allowing a diffusion region  10   d  to be formed at the position of the BB′ cross section. 
         [0071]    See  FIGS. 9P , and  9 A to  9 C. As pretreatment for the later step of silicide layer formation, natural silicon oxide film formed on the surface of the substrate  1  is removed by chemical treatment with, for instance, dilute hydrofluoric acid. This chemical treatment causes etching of the side wall insulation film  9 . Etching under conditions for 6 nm reduction of thermal oxide, for instance, effects about 25 nm to 30 nm reduction of the high impurity concentration side wall insulation film  9  produced at a low temperature. 
         [0072]    Here, the degree of reduction caused by etching of the side wall insulation film  9  depends on the film type, film forming temperature, quantity of implanted impurity, and impurity type. For instance, a film containing phosphorus implanted up to a high concentration during n-type MOS transistor formation is likely to be etched easily, while on the other hand, a film containing boron implanted during p-type MOS transistor formation is likely to be difficult to etch. 
         [0073]    For instance, a side wall insulation film formed at a low temperature of 400° C. to 600° C. is etched more easily than one formed a high temperature of, for instance, 700° C. to 800° C. A side wall insulation film difficult to etch can be produced at an increased film forming temperature of 700° C. or so, but this causes the impurity to diffuse, leading to a transistor with inferior performance. It is preferable that a low process temperature is maintained during the steps from impurity implantation to activation annealing. 
         [0074]    In  FIG. 9P  and other diagrams, the shape of the original side wall insulation film  9  is indicated by a broken line, while the shape of the reduced side wall insulation film  9  is indicated by a continuous line. As seen from  FIG. 9P , the outline of the reduced side wall insulation film  9  is conformal to the outline of the original side wall insulation film  9 . 
         [0075]    As the side wall insulation film  9  reduces, part of the contact region  5   a  and the transistor region  5   b , originally covered by the side wall insulation film  9 , is exposed. The chemical treatment to remove natural oxide film is performed under conditions where the degree of reduction of the side wall insulation film  9  is smaller than the degree of diffusion of the impurity in the transistor region  5   b  in particular. Thus, in the transistor region  5   b  in particular, the exposed portion EX resulting from the reduction of the side wall insulation film  9  is within the diffusion region  10   d  where the impurity has diffused from the source/drain regions  10 . 
         [0076]    As seen from  FIGS. 9B and 9P , the protruding region PA located outside the side wall insulation film  9  enlarges as the side wall insulation film  9  reduces, and the BB′ cross section after the etching of the side wall insulation film  9  crosses the enlarged portion of the protruding region PA. The enlarged portion of the protruding region PA is within the impurity diffusion region  10   d.    
         [0077]    See  FIGS. 10P , and  10 A to  10 C. A metal film to produce a silicide layer is formed over the entire surface of the substrate  1  to cover the gate electrode structure  7  and the side wall insulation film  9 . For instance, sputtering is performed to deposit a cobalt film  12  up to a thickness of 5 nm, followed by further deposition of a titanium nitride film  13  up to a thickness of 15 nm on the cobalt film  12 . 
         [0078]    See  FIGS. 11P , and  11 A to  11 C. A silicide layer is produced by carrying out heat treatment by RTA at, for instance, 550° C. for about 30 seconds. Then, wet etching with a mixture of sulfuric acid and hydrogen peroxide (SPM solution) is carried out to remove the unreacted parts of the titanium nitride film  13  and the cobalt film  12 , leaving the silicide layer  14  formed on the semiconductor region  5  and the silicide layer  14   g  formed on the gate electrode structure  7 . After removing the unreacted parts, additional RTA heat treatment is performed for about 30 seconds in a nitrogen atmosphere of about 700° C. to reduce the resistance of the silicide layers  14  and  14   g.    
         [0079]    The silicide layer  14  covers the entire exposed part of the semiconductor region  5  located outside the side wall insulation film  9 . In the vicinity of the side wall insulation film  9 , the silicide layer  14  is located on the diffusion region  10   d  in the transistor region  5   b  and on the diffusion region  11   d  in the contact region  5   a . Note that the description here addresses cobalt silicide as material of the silicide layer, but others such as nickel silicide may be used instead. 
         [0080]    As seen from  FIGS. 11B and 11P , in the region PA where the connection portion  4   b  is exposed, the silicide layer  14  may be formed on the diffusion region  10   d.    
         [0081]    The diffusion region  10   d  and diffusion region  11   d  are formed more deeply in the substrate  1  than the silicide layer  14 . This reduces the junction leak that can result from the silicide layer  14  reaching the p-type well pw in the entire transistor region  5   b , particularly in the collateral transistor region  4   c.    
         [0082]    See  FIGS. 12P , and  12 A to  12 C. An etching stopper film  15  is formed by depositing, for instance, nitride silicon by CVD up to a thickness of 50 nm to 100 nm over the entire substrate  1  to cover the gate electrode structure  7  and the side wall insulation film  9 . An interlayer insulation film  16  is formed by depositing, for instance, silicon oxide by CVD up to a thickness of 300 nm to 600 nm on the etching stopper film  15 . 
         [0083]    After planarizing the top surface of the interlayer insulation film  16  by chemical mechanical polishing (CMP), photolithography and etching are carried out to form contact holes  17   t  and  17 . The contact hole  17   t  is located on the main transistor region  3  and the contact hole  17  extends from the contact region  5   a  to the boundary portion  7   a.    
         [0084]    Subsequently, contact plugs  18   t  and  18  of tungsten are formed in the contact holes  17   t  and  17  with a titanium nitride film between them. The contact plugs  18   t  are electrically connected to the source/drain regions  10  of the MOS transistor. The contact plug  18  is electrically connected to the p-type well pw and the gate electrode structure  7 . Thus, a DTMOS transistor of the embodiment is formed. 
         [0085]    As described above, in the embodiment, a region PA protruding outward from the side wall insulation film  9  is formed in the connection portion  4   b  that connects the second region  4  to the first region  3 . To produce this protruding region PA, the width of the second region  4  (the collateral transistor region  4   c ) between the boundary portion  7   a  and the first region  3  is increased towards the first region  3 . Impurity is added to the protruding region PA by SD implantation, and the impurity implanted in the protruding region PA is diffused by activation annealing. 
         [0086]    Consequently, in the collateral transistor region  4   c , the semiconductor region EX exposed as a result of reduction of the side wall insulation film  9  can be easily confined within the diffusion region  10   d  of the impurity implanted by SD implantation, serving to reduce the junction leak attributable to the silicide layer  14  formed outside the side wall insulation film  9 . 
         [0087]    Note that the description here addresses an embodiment for formation of an n-type MOS transistor, but a p-type MOS transistor can be produced by a similar procedure by reversing the conductivity types. 
         [0088]    All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.