Abstract:
Signal delivery delay margin of a bypass flip-flop circuit is stabilized during high-frequency operation. An input controller for logically operating a bypass signal and a clock produces first and second output signals having different states depending on whether or not the bypass signal is activated. A latch circuit latches input data based on the first and second output signals. A latch controller logically operates the bypass signal and input data to generate a third output signal having a different state depending on whether or not the bypass signal is activated. An output controller is switched in response to the states of the first and second output signals for logically combining an output signal selected from the latch circuit and the third output signal to provide the output signal.

Description:
FIELD OF THE INVENTION 
   The present invention relates to a flip-flop circuit; and, more particularly, to a technology capable of achieving a stable signal delivery during a high-frequency operation by improving a signal delivery delay margin of a bypass flip-flop circuit. 
   DESCRIPTION OF RELATED ART 
   Latches and flip-flops generally have been used as storage devices for storing data in digital circuits. Among those devices, the flip-flops are utilized for sequential devices that sample inputs thereto and modify their outputs at a time determined by a clock signal. In contrast, the latches are used as sequential devices that continuously observe all inputs thereto and alter their outputs at any time regardless of the clock signal. 
     FIGS. 1A and 1B  are circuit diagrams of conventional bypass flip-flops. 
   Each of the conventional flip-flop circuits includes first and second latch portions  10  and  20 , and a bypass portion  30 . 
   The first latch portion  10  is provided with a transmission gate T 1  for selectively outputting data DATA in response to clocks CLKB and CLK, and a latch R 1  for latching an output of the transmission gate T 1 . The second latch portion  20  is provided with a transmission gate T 2  for selectively outputting an output of the first latch portion  10  in response to the clocks CLKB and CLK, and a latch R 2  for latching an output of the transmission gate T 2 . 
   The bypass portion  30  is composed of an inverter IV 1  and two transmission gates T 3  and T 4 , and selectively outputs latched data DATA or non-latched data DATA based on a logic state of a bypass signal BYPASS. In other words, if the bypass signal BYPASS is logic high, the transmission gate T 4  is turned on to provide the non-latched data DATA as an output signal OUT; and if the bypass signal BYPASS is logic low, the transmission gate T 3  is turned on to generate the latched data DATA as the output signal OUT. 
   The conventional flip-flop circuit having the structure described above outputs the data by using a multiplexer (not shown) prepared at its last stage, without control of the clocks. In this case, however, a signal path using the clocks CLK and CLKB is required to pass through the transmission gates T 1  and T 2  unnecessarily. In particular, if the size of a driver at the last stage is large, the size of each of the transmission gates T 1  and T 2  becomes large, thus causing large loading due to increase of junction capacitance. 
   Hence, a driver  40  is added and operated for more stable signal delivery, as shown in  FIG. 1B . In such case, since a signal must pass through a total of one transmission gate and two-stage inverters IV 2  and IV 3  to transmit input data, there may be a time delay for the signal transmission during a high-frequency operation. 
   For example, if the conventional bypass flip-flop circuit operates at a frequency of 1 GHz, it is assumed that the data DATA is output at a rising edge of the clock CLK. In this case, the signal is required to go through total three inverters and one transmission gate. Accordingly, in a worst case, an approximate total delay time comes to 700 ps, which is 200 ps at each inverter plus 100 ps at the transmission gate. 
   Consequently, there remains 300 ps in a flight time margin of 1 ns. Considering a set-up time 100 ps of circuit that takes such data, a time to transfer along a metal line is limited to 200 ps. Thus the conventional bypass flip-flop circuit is limited in terms of operating frequency. 
   SUMMARY OF THE INVENTION 
   It is, therefore, a primary object of the present invention to provide a flip-flop circuit capable of achieving its stability in a high impedance state by using a feedback inverter of a latch. 
   In accordance with an aspect of the present invention, there is provided a flip-flop circuit including: an input controller for logically operating a bypass signal and a clock to produce first and second output signals having different logic states depending on whether or not the bypass signal is activated; a latch circuit for latching input data based on the first and second output signals; a latch controller for logically operating the bypass signal and the input data to generate a third output signal having a different logic state depending on whether or not the bypass signal is activated; and an output controller switched in response to the logic states of the first and second output signals for selectively outputting the signal provided from the latch circuit, and logically combining the output signal and the third output signal to provide the output signal. 
   Other objectives and advantages of the invention will be understood by the following description and will also be appreciated by the disclosed embodiments of the invention. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which: 
       FIGS. 1A and 1B  are circuit diagrams of conventional bypass flip-flop circuits; 
       FIG. 2  is a circuit diagram of a flip-flop circuit in accordance with an embodiment of the present invention; and 
       FIG. 3  is a circuit diagram of a flip-flop circuit in accordance with another embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Hereinafter, a flip-flop circuit in accordance with the present invention will be described in detail with reference to the accompanying drawings. 
     FIG. 2  is a circuit diagram of a bypass flip-flop circuit in accordance with an embodiment of the present invention. 
   The bypass flip-flop circuit of the present invention includes an input controller  100 , a latch portion  110 , an output controller  120  and a latch controller  130 . 
   As shown in  FIG. 2 , the input controller  100  is provided with NOR gates NOR 1  and NOR 2  for logically operating clocks CLK and CLKB and a bypass signal BYPASS, respectively. The NOR gate NOR 1  NOR-operates the clock CLKB and the bypass signal BYPASS, and the NOR gate NOR 2  NOR-operates the clock CLK and the bypass signal BYPASS. 
   The latch portion  110  is composed of a transmission gate T 5  and a latch R 3 . The transmission gate T 5  selectively allows an output of data DATA depending on outputs of the NOR gates NOR 1  and NOR 2 . Applied to an NMOS gate of the transmission gate T 5  is an output of the NOR gate NOR 2 , and applied to a PMOS gate thereof is an output of the NOR gate NOR 1 . The latch R 3  latches an output of the transmission gate T 5  for a certain time. 
   The output controller  120  is provided with transmission gates T 6  and T 20 , an inverter IV 4 , a latch R 1  and a NAND gate ND 1 . The transmission gate T 6  is switched contemporaneously with the transmission gate T 5  and selectively passes an output of the latch portion  110  according to output states of the NOR gates NOR 1  and NOR 2 . Input to an NMOS gate of the transmission gate T 6  is an output of the NOR gate NOR 1 , and input to a PMOS gate thereof is an output of the NOR gate NOR 2 . Input to an NMOS gate of the transmission gate T 20  is the bypass signal BYPASS, and input to a PMOS gate thereof is an inverted signal of the bypass signal BYPASS. The inverter IV 4  inverts an output of the transmission gate T 6  to produce an output signal OUT. The NAND gate ND 1  NAND-operates an output of a NAND gate ND 2  included in the latch controller  130  and the output signal OUT to feedback an output signal to an input terminal of the inverter IV 4 . 
   The latch controller  130  is provided with inverters IV 5  and IV 6  and the NAND gate ND 2 . The inverter IV 5  inverts the data DATA and the inverter IV 6  inverts the bypass signal BYPASS. The NNAD gate ND 2  NAND-operates an output of the inverter IV 5  and the bypass signal BYPASS to delivery an output signal to the latch R 1  contained in the output controller  120 . 
   Hereinafter, an operation of the present invention having the construction as mentioned above will be described in detail. 
   If the bypass signal BYPASS is logic high, the input controller  100  outputs a logic low signal regardless of the clocks CLK and CLKB. In response to the logic low signal, the transmission gates T 5  and T 6  are all turned off and thus an output of the latch controller  130  becomes logic high, thus outputting the data DATA. 
   On the other hand, if the bypass signal BYPASS is logic low, the latch controller  130  outputs a logic high or low signal according to a level of the data DATA. In response to the logic high or low signal, the transmission gates T 5  and T 6  are selectively switched by the clocks CLK and CLKB regardless of whether the data DATA is of logic high or low, thus performing the same operation as the general flip-flop. 
   In other words, when the bypass signal BYPASS is logic low, if the clock CLK is logic low and the clock CLKB is logic high, the transmission gate T 5  is turned on for the latch R 3  to latch the data DATA. And, if the clock CLK is logic high and the clock CLKB is logic low, the transmission gate T 6  is turned on to invert the data applied to the latch portion  110  and provide inverted data as the output signal OUT. 
   As described above, the present invention outputs the data DATA regardless the clocks CLK and CLKB if the bypass signal BYPASS is logic high, and provides the output signal OUT depending on the clocks CLK and CLKB regardless the data DATA if the bypass signal BYPASS is logic low. Therefore, the present invention can remove the transmission gate at the bypass stage, to avoid the problem of the prior art. Accordingly, a margin of the signal transfer time can be improved because no additional inverter stage is needed. 
   For example, if the bypass flip-flop circuit of the present invention operates at a frequency of 1 GHz, it is assumed that the data DATA is output at a rising edge of the clock CLK. In this case, a driving time of only one inverter IV 4  is required. Thus, assuming that a set-up time of the next stage is 100 ps and a delay time of the inverter is 200 ps, the present invention can obtain a margin of 700 ps, while the prior art obtains a margin of 200 ps. Accordingly, the present invention can improve a signal delay transfer margin totaling 350%, compared to the prior art. 
     FIG. 3  is a circuit diagram of a flip-flop circuit in accordance with another embodiment of the present invention. 
   As exemplified therein, the flip-flop circuit of the present invention includes an input controller  200 , a latch portion  210 , an output controller  220  and a latch controller  230 . 
   The input controller  200  is provided with NOR gates NOR 3  and NOR 4  for NOR-operating clocks CLK and CLKB and a bypass signal BYPASS. The NOR gate NOR 3  NOR-operates the clock CLKB and the bypass signal BYPASS. The NOR gate NOR 4  NOR-operates the clock CLK and the bypass signal BYPASS. 
   The latch portion  210  is composed of a transmission gate T 7  and a latch R 4 . The transmission gate T 7  selectively allows an output of data DATA depending on output states of the NOR gates NOR 3  and NOR 4 . Applied to an NMOS gate of the transmission gate T 7  is an output of the NOR gate NOR 4 , and applied to a PMOS gate thereof is an output of the NOR gate NOR 3 . The latch R 4  latches an output of the transmission gate T 7  for a certain time. 
   The output controller  220  is provided with a transmission gate T 8 , an inverter IV 7 , and PMOS transistors P 1  to P 3  and NMOS transistors N 1  to N 4 , which serve as a switching device. The transmission gate T 8  is switched contemporaneously with the transmission gate T 7  and selectively passes an output of the latch portion  210  according to output states of the NOR gates NOR 3  and NOR 4 . Input to an NMOS gate of the transmission gate T 8  is an output of the NOR gate NOR 3 , and input to a PMOS gate thereof is an output of the NOR gate NOR 4 . The inverter IV 7  inverts an output of the transmission gate T 8  to produce an output signal OUT. 
   The PMOS transistor P 1  is connected between a power supply voltage VDD input terminal and the PMOS transistor P 2  and accepts an output of the NOR gate NOR 3  via its gate. The PMOS transistor P 2  is coupled between the PMOS transistor P 1  and the NMOS transistor N 1  and receives an output of a NAND gate ND 3  included in the latch controller  230  via its gate. The PMOS transistor P 3  is connected in parallel with the PMOS transistor P 2  and takes the output signal OUT via its gate. The NMOS transistors N 1  to N 3  are connected in series between the PMOS transistor P 2  and a ground voltage VSS input terminal; and accepts via their gates an output of the NAND gate ND 3 , the output signal OUT and an output of the NOR gate NOR 4 , respectively. Te NMOS transistor N 4  is connected in parallel with the NMOS transistor N 2  and receives the bypass signal BYPASS via its gate. 
   The latch controller  230  is provided with inverters IV 8  and IV 9 , the NAND gate ND 3  and a latch R 10 . The inverter IV 8  inverts the data DATA and the inverter IV 6  inverts the bypass signal BYPASS. The NAND gate ND 3  NAND-operates outputs of the inverters IV 8  and IV 9  to provide an output signal to the gates of the PMOS transistor P 2  and the NMOS transistor N 1 . The latch R 10  latches the output of the NAND gate ND 3 . 
   Hereinafter, an operation of the present invention having the construction as described above will be described in detail. 
   If the bypass signal BYPASS is logic high, the input controller  200  outputs a logic low signal regardless of the clocks CLK and CLKB. In response to the logic low signal, the transmission gates T 7  and T 8  are turned off and thus an output of the latch controller  230  becomes logic high, regardless of a level of the data DATA. 
   In succession, the PMOS transistor P 1  and the NMOS transistor N 1  are turned on, and the NMOS transistor N 3  is maintained to be in the turn-off state. Thus, the data DATA can be output according to a selective switching operation of the PMOS transistor P 3  and the NMOS transistor N 2 . 
   If the bypass signal BYPASS is logic low, the latch controller  230  outputs a logic high or low signal relying on a level of the data DATA. In response to the logic high or low signal, the transmission gates T 7  and T 8  are selectively switched by the clocks CLK and CLKB regardless of whether the data DATA is logic high or low, thus performing the same operation as the general flip-flop. 
   In other words, when the bypass signal BYPASS is logic low, if the clock CLK is logic low and the clock CLKB is logic high, the transmission gate T 7  is turned on for the latch R 4  to latch the data DATA. At this time, if the data DATA is logic high, the output of the latch controller  230  becomes logic high, thus turning on the NMOS transistor N 1 . The output of the NOR gate NOR 4  becomes logic high and thus the NMOS transistor N 3  becomes logic high. In this state, if the output signal OUT is logic high, the NMOS transistor N 2  is turned on and an input of the inverter IV 7  becomes logic high; and if the output signal OUT is logic low, the input of the inverter IN 7  becomes logic high. 
   On the other hand, if the clock CLK is logic high and the clock CLKB is logic low, the transmission gate T 8  is turned on, which inverts data applied to the latch  210  and provides inverted data as the output signal OUT. 
   As described above, the present invention has an advantage in that it can achieve a stable signal transfer during a high-frequency operation by improving a signal transfer delay margin of a bypass flip-flop circuit. 
   The present application contains subject matter related to Korean patent application No. 2005-91665 &amp; 2005-134193, filed in the Korean Patent Office on Sep. 29 &amp; Dec. 29, 2005, the entire contents of which are incorporated herein by reference. 
   While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.