Abstract:
A method for correcting gradation of output data for reproducing a picture image, for use in a picture digital processing system wherein picture data is processed by using one or a plurality of lookup table memories aligned in series, wherein a variable number of lower bits of input data to be input to the lookup table memory, the number of the lower bits of the input data being varied depending on the input data and the input-output characteristics of the one lookup table memory or the total input-output characteristics of the plurality of lookup table memories, is added as correction data to data output by the one or the plurality of lookup table memories.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a method for correcting gradation of output data for reproducing a picture image so as to compensate for the drop in resolving power of gradation of the output data, or the smoothness of gradation of the reproduction picture, for use in a picture digital processing system wherein picture data is processed by using one or a plurality of lookup table memories aligned in series. 
     In conventional picture digital processing using lookup table memories aligned in series, especially including at least one lookup table memory having non-linear input-output characteristics, the resolving power of the gradation of output data deteriorates, with a result that gradation of the reproduced picture deteriorates. 
     There are shown in FIGS. 1 and 2 input-output characteristics curves A and B of conventional lookup table memories which are aligned in series and are used for a conventional picture digital processing system. 
     There are shown in FIGS. 3 and 4 parts of the input-output characteristics curves A and B of FIGS. 1 and 2, which are enlarged to one least significant bit (LSB) unit scale. 
     First, when input data X 0 , X 1 , X 2 , . . are input to the lookup table memory of FIG. 3 at t 0 , t 1 , t 2 , . . , as shown in FIG. 5, the table outputs data Y 0 , Y 1 , Y 2 , . . , consecutively. Then, when the output data Y 0 , Y 1 , Y 2 , . . are input to the lookup table memory of FIG. 4, it outputs data Z 1 , Z 4 , Z 7 , . . , finally. However, as shown in FIG. 6, the resultant output data possess far lower resolving power than the original input data. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a method for correcting gradation of output data for reproducing a picture image, for use in a picture digital processing system wherein picture data is processed by using one or a plurality of lookup table memories aligned in series, free from the aforementioned defects and inconveniences. The invention can compensate for the drop in resolving power of gradation of the output data of the lookup table memories, and is capable of obtaining a reproduction picture having a fine and smooth gradation. 
     According to the present invention there is provided a method for correcting gradation of output data for reproducing a picture image, for use in a picture digital processing system wherein picture data is processed by using one or a plurality of lookup table memories aligned in series, the improvement which comprises the step of adding a variable number of lower bits of input data to be input to the lookup table memory, as correction data, the lower bit number of the input data being varied depending on the input data and the input-output characteristics of the one lookup table memory, or the total input-output characteristics of the plurality of lookup table memories, to output data from the one or the plurality of lookup table memories. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In order that the present invention may be better understood, preferred embodiments thereof will be described with reference to the accompanying drawings, in which: 
     FIGS. 1 and 2 are graphs showing input-output characteristics curves of conventional lookup table memories; 
     FIGS. 3 and 4 show parts of the input-output characteristics curves of FIGS. 1 and 2, which are enlarged; 
     FIG. 5 shows one embodiment of input data with reference to time, which is input to the lookup table memories of FIGS. 1 and 2; 
     FIG. 6 shows one embodiment of output data with reference to time, which is obtained finally in a conventional manner; 
     FIG. 7 is a block diagram of one embodiment of a circuit which performs a method according to the present invention; 
     FIG. 8 is a graph showing a total input-output characteristics curve of a lookup table memory group shown in FIG. 7; 
     FIG. 9 shows one embodiment of a discrimination circuit of FIG. 7; 
     FIG. 10 shows one embodiment of a bit shift circuit of FIG. 7; 
     FIG. 11 is a block diagram of another embodiment of a circuit which performs a method according to the present invention; and 
     FIGS. 12a and 12b show one embodiment of input data and output data of FIG. 11. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to the drawings there is shown in FIG. 7 one embodiment of a circuit which performs the method according to the present invention, comprising a shift register 1, a preset circuit 2, setting in advance values a 1 , a 2  and a 3  for dividing input data into a plurality of areas S 1 , S 2 , S 3  and S 4 , as shown in FIG. 8, a discrimination circuit 3 which compares the input data sent from the shift register 1 with the preset values of the preset circuit 2 and determines which area S 1 , S 2 , S 3  or S 4  the input data is included in, a bit shift circuit 4 which selects a correction signal having a proper bit number depending on the discrimination signal output by the discrimination circuit 3, a lookup table memory group 5, and an adder 6. 
     The reason why such a determination is required will be clear by considering one example where the resolving power of gradation is corrected by adding equally the lower three bits of the input data as correction data to the output data, output from the lookup table memory group 5, as follows. 
     When the input data is included in the area S1 where the variation of the output data with reference to the input data is approximately one bit, the correction data is added beyond the moving range of the main data, resulting in an excessive correction. On the other hand, when the input data is included in the area S4, where the variation of the output data with reference to the input data is very large, the correction data, that is, the lowest three bits is not enough, resulting in insufficient correction. 
     In accordance with the present invention, in order to overcome such disadvantages as excessive or insufficient correction, it is determined in the discrimination circuit 3 where the input data is included, that is, in which one of the table input-output characteristics areas of the lookup table memory group. Then the discrimination circuit 3 outputs a discrimination signal accordingly. Depending on the discrimination signal, correction data is added or subtracted to or from the data output from the lookup table memory, the correction data affecting a suitable number of least significant or lower bits of the output data, thereby compensating an excessive or insufficient correction. 
     Now, when input data of eight bits is first latched in the shift register 1 and then is output from it at a proper timing by a pulse signal generated by a timing pulse generator (not shown), the input data is compared in the discrimination circuit 3 with values preset in the preset circuit 2. Then, depending on the magnitudes of the comparison result, it is determined in which areas, obtained by dividing the input axes of the total input-output characteristics of the lookup table memory group 5 into a plurality of parts, the input data is included. 
     As shown in FIG. 9, the discrimination circuit 3 comprises comparators 7, 8 and 9, inverters 10, 11 and 12 and AND gates 13, 14, 15 and 16. 
     However, when the total input-output characteristics of the lookup table memory group 5 are expressed by a curve shown in FIG. 8, in the discrimination circuit 3 shown in FIG. 9, input data D 0  is compared with the preset values a 1 , a 2  and a 3  in the comparators 7, 8 and 9, respectively wherein 0&lt;a 1  &lt;a 2  &lt;a 3 . Then depending on the magnitudes between the input data D 0  and the preset values a 1 , a 2  and a 3 , one of the AND gates 13, 14, 15 and 16 outputs a discrimination signal of high level. 
     That is, when the input data D 0  satisfies the condition: D 0  &lt;a 1 , the comparators 7, 8 and 9 output low level signals, and thus the AND gate 16 outputs the discrimination signal. In the same manner as described above, when a 1  ≦D 0  &lt;a 2 , the AND gate 15 outputs a high signal; when a 2  ≦D 0  &lt;a 3 , the AND gate 14 outputs a high signal; and when a 3  ≦D 0 , the AND gate 13 outputs a high signal. The discrimination signal is fed to the bit shift circuit 4. 
     One embodiment of the bit shift circuit 4 is shown in FIG. 10, and comprises AND gates 17, 18 and 19, and inverters 20, 21 and 22. The fourth bit, the third bit and the second bit of the lower four bits of the input data of eight bits, which is output from the shift register 1 with proper timing, are connected to one input terminal of the AND gates 17, 18 and 19, respectively. 
     Now, when D 0  ≧a 3 , the AND gate 13 outputs a discrimination signal of high level and thus low level signals are fed to input terminals Q 1 , Q 2  and Q 3  of the inverters 20, 21 and 22 from the AND gates 14, 15 and 16 of the discrimination circuit 3, as shown in FIG. 10. Then the inverters 20, 21 and 22 invert the low level signals and output high level signals to the respective AND gates 17, 18 and 19. Hence, the bit shift circuit 4 outputs correction data corresponding to the lower four bits of the input data D 0 . 
     When a 2  ≦D 0  &lt;a 3 , the AND gate 14 outputs a discrimination signal of high level to the terminal Q 3 , and hence low level signals are input to the other terminals Q 1 , Q 2  and Q 4 . Accordingly, the bit shift circuit 4 outputs correction data corresponding to the lower three bits of the input data D 0 . When a 1  ≦D 0  &lt;a 2 , the bit shift circuit 4 outputs correction data corresponding to the lower two bits of the input data D 0  in the same manner as described above. 
     Further, when D 0  &lt;a 1 , the AND gate 16 outputs a discrimination signal of high level, and the bit shift circuit 4 outputs correction data corresponding to the lowermost one bit of the input data D 0 . In this case, the correction data is not so significant, and therefore it may be processed so that no correction data is output from the bit shift circuit 4, or that correction data corresponding to the lower two bits of the input data D 0  is output from the bit shift circuit 4. 
     It is readily understood from the above description that the bit shift circuit 4 controls the value of the correction data, i.e. the number of the lower bits of the input data to be added to the output data, output from the lookup table memory group 5, depending on the total input-output characteristics of the lookup table memory group 5 and the input data corresponding to the output data. 
     The correction data output from the bit shift circuit 4 is then sent to the adder 6 and is added to the output data output from the lookup table memory group 5, thereby compensating or recovering the decrease of resolving power of the gradation of the output data, which is caused in the lookup table memory group 5. 
     In FIG. 11 there is shown another embodiment of a circuit which performs a method according to the present invention, having basically the same construction as that shown in FIG. 7, except further comprising a central data generator 23, a comparator 24, a subtracter 25 and a complementary circuit 26, as hereinafter described in detail. 
     In the first embodiment described above the correction data output on the bit shift circuit 4 is directly added to the corresponding output data of the lookup table memory group 5, thereby compensating the decrease in resolving power of gradation of the output data, which loss of resolving power occurs in the lookup table memory group 5. However, in the second embodiment shown in FIG. 11, gradation corrections performed in the following manner. 
     In this embodiment, the correction data to be added to the output data of the lookup table memory group 5 is compared with the central data of a data region expressed by the bit number of the correction data, for example, the central data is 1000 when the bit number of the correction data is four bits. Then depending on the magnification between the two data, the correction data is properly added or subtracted from the output data of the lookup table memory group 5, thereby restoring the loss of resolving power in the gradation of the output data, which is lost in the lookup table memory group 5, as hereinafter described. 
     In FIG. 11 the numerals 1-6 denote the same elements as those of FIG. 7. The central data generator 23 outputs the central data of the data region expressed by the bit number of the correction data depending on the discrimination signal output from the discrimination circuit 3. 
     Hence, now, when the bit shift circuit 4 outputs correction data to the comparator 24, the comparator 24 compares the correction data with the central data, and then the substrate 25 performs the subtraction described above depending on the magnitude of the comparison result in the comparator 24. 
     The output data generated by the subtracter 25 is sent to the adder 6 via the complementary circuit 26 wherein the output data of the subtracter 25 is converted into the complement of &#34;2&#34; only when the central data is larger than the correction data, as described above. The adder 6 adds the data sent from the complementary circuit 26 to the corresponding output data output by the lookup table memory group 5. 
     Now, when the bit shift circuit 4 outputs the correction data shown in FIG. 12a, since the correction data which is added to or subtracted from the central data properly, is added to the output data in the adder 6, output data is obtained whose gradation is more similar to that of the input data. The result is different from the method of the first embodiment described above, the result being illustrated in FIG. 12b. 
     Although the present invention has been described in some details by way of illustration and example for purposes of clarity of understanding, it will, of course, be understood that various changes and modifications may be made in the form, details, and arrangements of the parts without departing from the scope of the present invention. 
     The method of the present invention can, of course, be applied to a picture digital processing system including only one lookup table memory.