Abstract:
An LC tank structure. The structure, including a set of wiring levels on top of a semiconductor substrate, the wiring levels stacked on top of each other from a lowest wiring level nearest the substrate to a highest wiring level furthest from the substrate; an inductor in the highest wiring level, the inductor confined within a perimeter of a region of the highest wiring level; and a varactor formed in the substrate, the varactor aligned completely under the perimeter of the region of the highest wiring level. The structure may additionally include an electric shield in a wiring level of the set of wiring levels between the lowest wiring level and the highest wiring level. Alternatively, the inductor includes a magnetic core and alternating electrically non-magnetic conductive metal coils and magnetic coils around the core.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to the field of LC tank devices for integrated circuits; more specifically, it relates to an LC tank device comprising an inductor and varactor on an integrated circuit chip.  
       BACKGROUND OF THE INVENTION  
       [0002]     Conventional LC tank devices require a protected area within which the inductor portion of the LC tank device is placed and the varactor portion of the LC tank device or any other devices of integrated circuits of integrated circuit chips are excluded in order to avoid, eddy currents and electric field coupling to elements of the integrated circuits. Thus large regions of prime chip area are effectively wasted and the parasitic capacitances of the long metal connections over the protection area between the inductor and the varactor reduce the quality (Q) value and the frequency tuning range of the LC tank. The horizontal metal connections dominate the total connection parasitic capacitances. In order to recover these presently unused regions and improve the performances of the integrated circuit chip, a new LC tank device is required.  
       SUMMARY OF THE INVENTION  
       [0003]     A first aspect of the present invention is a structure, comprising: a set of wiring levels on top of a semiconductor substrate, the wiring levels stacked on top of each other from a lowest wiring level nearest the substrate to a highest wiring level furthest from the substrate; an inductor in the highest wiring level, the inductor confined within a perimeter of a region of the highest wiring level; an electric shield in a wiring level of the set of wiring levels between the lowest wiring level and the highest wiring level; and a varactor formed in the substrate, the varactor aligned completely under the perimeter of the region of the highest wiring level.  
         [0004]     A second aspect of the present invention is a structure, comprising: a set of wiring levels on top of a semiconductor substrate, the wiring levels stacked on top of each other from a lowest wiring level nearest the substrate to a highest wiring level furthest from the substrate; an inductor in the highest wiring level, the inductor confined within a perimeter of a region of the highest wiring level, the inductor comprising a magnetic core and alternating electrically non-magnetic conductive metal coils and magnetic coils around the core; and a varactor formed in the substrate, the varactor aligned completely under the perimeter of the region of the highest wiring level. 
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0005]     The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:  
         [0006]      FIG. 1  is a cross-sectional view of an LC tank device according to a first embodiment of the present invention;  
         [0007]      FIG. 2  is a plan view of portions of the LC tank device according to the first embodiment of the present invention;  
         [0008]      FIG. 3  is a cross-sectional view of an LC tank device according to a second embodiment of the present invention;  
         [0009]      FIG. 4  is a plan view of portions of the LC tank device according to the second embodiment of the present invention;  
         [0010]      FIG. 5  is a cross-sectional view of an LC tank device according to a third embodiment of the present invention.  
         [0011]      FIG. 6  is a plan view of portions of the LC tank device according to the third embodiment of the present invention;  
         [0012]      FIG. 7  is a cross sectional view of an alternative magnetic core inductor for use with the third embodiment of the present invention;  
         [0013]      FIGS. 8A, 8B ,  9 ,  10  and  11  are alternative configurations for isolation layers for use with the first embodiment of the present invention  
         [0014]      FIG. 12  is a cross-sectional view of an LC tank device according to the first embodiment of the present invention, but using an alternative varactor;  
         [0015]      FIG. 13  is a schematic block diagram of a phase-lock-loop (PLL) circuit; and  
         [0016]      FIG. 14  is a circuit diagram of a voltage controlled oscillator (VCO) using an LC tank device according to the embodiments of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0017]     A common feature of the various embodiments of the present invention is elimination of the horizontal metal interconnections commonly found between elements of LC tank circuits of integrated circuit chips in order to minimize parasitic capacitances caused the horizontal metal connections.  
         [0018]      FIG. 1  is a cross-sectional view of an LC tank device according to a first embodiment of the present invention. Formed in a silicon substrate  100  (or a silicon layer on a silicon-on insulator (SOI) substrate) is an N-well region  105 . Formed in N-well region  105  are varactors  110 A and  110 B. Varactor  110 A comprises a lightly doped N-type region  115 A between a highly doped P region  120 A and the highly doped N-well  105 . Varactor  110 B comprises a lightly doped N-type region  115 B between a highly doped P region  120 B and the highly doped N-well  105 . Regions  115 A and  115 B as well as regions  120 A and  120 B are isolated from each other by shallow trench isolation (STI)  125 . Varactors  110 A and  110 B are examples of a typical p-n junction based varactor diode. Varactors  110 A and  110 B may be replaced with other varactor types such as hyper abrupt junction (HAVAR) varactors, MOS varactors (see  FIG. 12 ).  
         [0019]     Formed a top surface of substrate  105  is a first dielectric layer  130  which includes conductive metal vias  135 . Formed a top surface of first dielectric layer  130  is a second dielectric layer  140  which includes conductive metal vias  145 . Formed a top surface of second dielectric layer  140  is a third dielectric layer  150  which includes conductive metal vias  155 . Formed a top surface of third dielectric layer  150  is a fourth dielectric layer  160  which includes conductive metal vias  165 . Formed a top surface of fourth dielectric layer  160  is a fifth dielectric layer  170  which includes conductive metal vias  175 . While five dielectric layers are illustrated in  FIG. 1 , there may be more or less than five dielectric layers. The combination of a dielectric layer and its corresponding electrically conductive wires and electrically conductive vias is also called a wiring level and the dielectric layer is also called and interlevel dielectric (ILD). Dielectric layers  130 ,  140 ,  150 ,  160  and  170  and wires contained in them thus comprise wiring levels, with the lowest wiring level closest to substrate  100  and the highest wiring level furthest away from the substrate.  
         [0020]     Formed in fifth dielectric layer  170  is an inductor  180  and formed in second dielectric layer  140  is a patterned electric shield  185 . Patterned electric shield  185  is aligned between inductor  180  and varactors  110 A and  110 B. A first set of vias  135 ,  145 ,  155 ,  165  and  175  provide a continuous electrical path to N-well  105 . A second set of vias  135 ,  145 ,  155  and  175  provide a continuous electrical path to P region  120 A of varactor  110 A and a third set of vias  135 ,  145 ,  155  and  165  provide a continuous electrical path to P region  120 A of varactor  110 A. Thus an LC tank circuit  190 A includes varactors  110 A,  110 B, inductor  180  and patterned electric shield  185 . When wired, a varactor control signal (V CTR  signal) is applied to N-well  105  and ground is applied to patterned electric shield  185 .  
         [0021]     Inductor  180  is advantageously place in the highest wiring level (that furthest away from substrate  100 ) in order to reduce parasitic capacitance and thus increase the Q factor of the inductor though the inductor may be placed in a lower wiring level. Patterned electric shield  185  is patterned (includes gaps filled with the dielectric material of dielectric layer  140 ) and is advantageously placed in a low wiring level (a wiring level near to varactors  110 A and  110 B) in order to reduce eddy currents though the patterned shield may be placed in a higher wiring level.  
         [0022]      FIG. 2  is a plan view of portions of the LC tank device according to the first embodiment of the present invention. In  FIG. 2 , it can be seen that inductor  180  has the shape of a spiral coil and patterned electric shield  185  comprises a set of parallel wires. Patterned electric shield  185  cannot shield a DC magnetic field because of the unity permeability of metal, but can stop an AC magnetic field when the shield is grounded by forcing the electric field to a constant value.  
         [0023]     It should be noted, that varactors  110 A and  110 B are aligned within the perimeter defined by the outermost coils of inductor  185  and that patterned electric shield  185  overlaps the perimeter defined by the outermost coils of inductor  185 . In one example, inductor  180  and patterned electric shield  185  comprise aluminum (Al) or copper (Cu) or liner of tantalum/tantalum nitride (Ta/TaN) filled with a core of Cu. Semiconductor devices such as diodes, transistors, resistors and capacitors may be formed in the substrate or in the dielectric layers directly below patterned electric shield  185 .  
         [0024]      FIG. 3  is a cross-sectional view of an LC tank device according to a second embodiment of the present invention.  FIG. 3  is similar to  FIG. 1  except an LC tank device  190 B includes a magnetic shield  195  in place of patterned electric shield  185  of  FIG. 1 . Magnetic shield  195  is formed in fourth dielectric layer  160 . Magnetic shield  195  is a solid plate except for through holes for vias  165  and is advantageously placed in a high wiring level (a wiring level near to inductor  180 ) in order to maximize the number of wiring levels where normal integrated circuit wires may pass under the shield.  
         [0025]      FIG. 4  is a plan view of portions of the LC tank device according to the second embodiment of the present invention. In  FIG. 4 , it can be seen that inductor  180  has the shape of a spiral and magnetic shield  195  comprises a continuous region with no openings.  
         [0026]     It should be noted, that varactors  110 A and  110 B are aligned within the perimeter defined by the outermost coils of inductor  180  and that magnetic shield  195  overlaps the perimeter defined by the outermost coils of inductor  180 . In one example, inductor  180  comprise Al, Cu or a liner of Ta/TaN filled with a core of Cu and magnetic shield  195  comprises iron (Fe), nickel (Ni), Cu, molybdenum (Mo), manganese (Mn). MnFe 2 O 3 , Cu Fe 2 O 3 , Zn Fe 2 O 3 , Ni Fe 2 O 3 , other ferrites or other magnetic materials in either solid or paste form. Such magnetic materials and method of integrating them into integrated circuits is described in United States Patent Application Publication US2004/0263310 published on Dec. 30, 2004 which is hereby incorporated by reference in its entirety. Devices such as diodes, transistors, resistors and capacitors may be formed in the substrate or in the dielectric layers directly below magnetic shield  195 .  
         [0027]      FIG. 5  is a cross-sectional view of an LC tank device according to a third embodiment of the present invention.  FIG. 5  is similar to  FIG. 1  except an LC tank device  190 C includes a magnetic core inductor  200 A in place of inductor  180  of  FIG. 1  Magnetic core inductor  200 A comprises a loop coil conductor  205 A between an inner magnetic core  205 B, an outer magnetic loop  205 C and a magnetic plate  205 D under loop coil conductor  205 A, magnetic core  205 B and outer magnetic loop  205 C and there is no patterned shield. Magnetic plate  205 D includes through holes for vias  165 . Magnetic core inductor  200 A is formed in fourth and fifth dielectric layers  160  and  170 . Magnetic core inductor  200 A is advantageously placed in the highest wiring levels (the wiring levels furthest from substrate  100 ) in order to maximize the number of wiring levels where normal integrated circuit wires may pass under inductor  200 A. Loop conductor  205 A inner magnetic core  205 B, outer magnetic loop  205 C in fifth dielectric layer  170  are not electrically connected to each other or physically contacting each other. Magnetic plate  205 D in fourth dielectric layer  160  is in physical contact with inner magnetic core  205 B and outer magnetic loop  205 C.  
         [0028]      FIG. 6  is a plan view of portions of the LC tank device according to the third embodiment of the present invention. In  FIG. 6 , it can also be seen that loop conductor  205 A, inner magnetic core  205 B, outer magnetic loop  205 C are not electrically connected to each other or physically contacting each other.  
         [0029]     It should be noted, that varactors  110 A and  110 B are aligned within the perimeter defined by the outermost coils of core inductor  200 A. In one example, loop coil inductor  205 A comprises Al, Cu or liner of Ta/TaN filled with a core of Cu and magnetic core  205 B and magnetic loop coil  200 C each comprise same materials described for magnetic shield  195  of  FIGS. 3 and 4  and described supra. Devices such as diodes, transistors, resistors and capacitors may be formed in the substrate or in the dielectric layers directly below core inductor  205 A.  
         [0030]      FIG. 7  is a cross sectional view of an alternative magnetic core inductor for use with the third embodiment of the present invention. In  FIG. 7 , a core inductor  200 B comprises loop coil conductor  205 A between inner magnetic core  205 B and outer magnetic loop coil  205 C in the same plane and between a upper magnetic plate  205 E and a lower magnetic plate  205 F, all embedded in a dielectric layer  210 .  
         [0031]      FIGS. 8A, 8B ,  9 ,  10  and  11  are alternative configurations for shielding layers for use with the first embodiment of the present invention.  FIG. 8B  is a cross-section through line B-B of  FIG. 8A . In  FIGS. 8A and 8B , a patterned electric shield  185 A includes a wires  215 A in third dielectric layer  150  and wires  215 B in second dielectric layer  140 . Wires  215 A are aligned perpendicular to e wires  215 B.  
         [0032]     In  FIG. 9 , a patterned electric shield  185 B is similar to patterned electric shield  185 A of  FIGS. 8A and 8B  except wires  215 A are aligned parallel to and horizontally (as defined by the planes of dielectric layers  140  and  150 ) offset from wires  215 B.  
         [0033]     In  FIG. 10 , bars  215 C of a patterned electric shield  185 C are aligned radially around a central point “C” like the spokes of a wheel. There may be two sets of shields  185 C, one in each of two adjacent dielectric layers and they may be aligned so corresponding bars  215 C in each of the layers are aligned over each other or between each other.  
         [0034]     In  FIG. 11 , wedges  215 D of a patterned electric shield  185 C are aligned radially around central point “C” like the spokes of a wheel. There may be two sets of shields  185 D, one in each of two adjacent dielectric layers and they may be aligned so corresponding wedges  215 D in each of the layers are aligned over each other or between each other.  
         [0035]      FIG. 12  is a cross-sectional view of an LC tank device according to the first embodiment of the present invention, but using an alternative varactor (e.g. a MOSVAR). In  FIG. 12 , a varactor  220 A comprises the gate  225 A, gate dielectric  230 A, source/drain  235 A and source/drain  240 A of a first field effect transistor (FET) and varactor  220 B comprises the gate  225 B, gate dielectric  230 B, source/drain  235 B and source/drain  240 B of a second FET. The VCRR signal described supra, is connected to source/drain  240 A and source/drain  235 B via wires  245  and vias  145 ,  155 ,  165  and  175 . Varactors  220 A and  220 B may be used with all embodiments of the inductor and shielding of the present invention as illustrated in  FIGS. 1, 2 ,  3 ,  4 ,  5 ,  6   7 ,  8 A,  8 B,  9 ,  10  and  11  and described supra.  
         [0036]     The inductor of embodiments of the present invention may advantageously be used in a variety of integrated circuits including but not limited to PLL circuits, particularly the VCO circuit of PLL circuits as described infra.  
         [0037]      FIG. 13  is a schematic block diagram of a PLL circuit. In  FIG. 13 , a PLL circuit  250  includes a phase detector  255  connected to a charge pump  260  which in turn is connected to a VCO  265 , which in turn is connected to a forward frequency divider  270 . A feedback divider  275  is connected between forward frequency divider  270  and phase detector  255 . An input frequency signal FREQ IN is connected to phase detector  255  and phase locked output frequency signal FREQ OUT is outputted by forward divide  270 .  
         [0038]      FIG. 14  is a circuit diagram of a VCO using an LC tank device according to the embodiments of the present invention. In  FIG. 14 , VCO  265  comprises an inductor L 1  connected between nodes N 1  and N 2 . An input of a first inverter I 1  is connected to node N 1  and an input of a second inverter I 2  is connected to node N 2 . A first plate of a capacitor C 1  is connected to node N 1  and a second plate of capacitor C 1  is connected to a node VTR. A first plate of a capacitor C 2  is connected to node N 2  and a second plate of capacitor C 2  is connected to node VTR. Capacitors C 1  and C 2  represent the varactors described supra. The output of inverters I 1  is connected to N 2  and the output of I 2  is connected to N 1 .  
         [0039]     Thus, the present invention provides an LC tank device in which the varactor portion of the LC tank circuit and other devices and wires of circuits of an integrated circuit chip may be placed under the inductor.  
         [0040]     The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.