Abstract:
A Power Over Data Lines (PoDL) system includes Power Sourcing Equipment (PSE) supplying DC power and differential Ethernet data over a single twisted wire pair to a Powered Device (PD). Due to start-up perturbations, PD load current variations, and other causes, dV/dt noise is introduced in the power signal. Such noise may be misinterpreted as data unless mitigated somehow. Rather than increasing the values of the passive filtering components conventionally used for decoupling/coupling the power and data from/to the wire pair, active circuitry is provided in the PSE, PD, or both to limit dV/dt in the power signal. Such circuitry may be implemented on the same chip as the PSE controller or PD controller. Therefore, the sizes of the passive components in the decoupling/coupling networks may be reduced.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority to U.S. provisional application Ser. No. 61/993,526, filed May 15, 2014, by Andrew J. Gardner et al, assigned to the present assignee and incorporated by reference. 
    
    
     FIELD OF THE INVENTION 
     This invention relates to Power over Data Line (PoDL) systems, where DC power is transmitted over a pair of differential data lines. The invention more particularly relates to techniques for actively limiting the power signal&#39;s dV/dt coupled to the wire pair, which will reduce the passive filtering requirements at the PHY terminals. 
     BACKGROUND 
     In PoDL, DC power from Power Sourcing Equipment (PSE) is transmitted over a single twisted wire pair. The same twisted wire pair also transmits/receives differential data signals. In this way, the need for providing any external power source for the Powered Devices (PDs) can be eliminated. The standards for PoDL are set out in IEEE 802.3 and are well-known. 
     A conventional PoDL system uses a coupling network to couple the DC power and AC data to the twisted wire pair at the output of the PSE and uses an identical network to decouple the DC power and AC data from the twisted wire pair at the PD. 
       FIG. 1  illustrates conventional coupling/decoupling networks between a PSE  10  and a PD  12  in an Ethernet PoDL system. The PSE  10  includes a DC voltage source  13  and may include a differential data transceiver. The differential data may also be generated by any other circuit. The differential data is applied to differential terminals of the physical layer (PHY)  14  for application to the twisted wire pair  16 . The data portion of the PoDL system is not relevant to the present invention so is not described in detail. 
     The PD  12  includes a differential data portion that receives data from the PHY  18  terminals and processes the data accordingly. Such a data processing portion is not relevant to the invention. The PD load that receives the DC voltage and the data is represented by a resistor R PD . A capacitor C PD  helps smooth the voltage into the PD load. A DC-DC converter may be used in the PD to convert the received PoDL voltage to a target voltage for the PD load. 
     In the example of  FIG. 1 , DC power is delivered from the PSE  10  to the PD  12  through the single twisted wire pair  16  via a coupling network that conducts DC (or low frequency current), for power, between the DC voltage source  13  and the wire pair  16 , while simultaneously blocking the differential AC data (or high frequency current) from the DC voltage source  13 . Similarly, the PD  12  uses a decoupling network that decouples the transmitted DC voltage for powering the PD load, while conducting only the PHYs&#39; AC data to data terminals in the PD  12 . The ability of the coupling/decoupling networks to block the PHYs&#39; AC data over a very broad range of frequencies is a key requirement for PoDL Ethernet applications where the data rates may vary from 100 Mbps to 1 Gbps. In the example of  FIG. 1 , the capacitors C 1 -C 4  are intended to block DC in the data path, while the inductors L 1 -L 4  are intended to block AC in the power path. 
     In  FIG. 1 , inductors L 1 -L 4  are used to couple/decouple the DC flowing between the PSE  10  voltage source  13  and the PD  12  load to/from the wires  16 . The inductors L 1 -L 4  are AC blocking devices whose impedance is proportional to frequency. The constant of proportionality is referred to as the inductance L. The ability of a single inductor to impede AC over a broad range of frequencies depends on the magnitude of inductance, the inductor&#39;s ability to conduct DC current without losing its inductance, and its parasitic capacitance. 
     It is desirable to make the inductors L 1 -L 4  the minimum size necessary to pass the power signal but block the AC data signals. Similarly, it is desirable to make the capacitors C 1 -C 4  the minimum size necessary to block the power signal but pass the AC data signals. However, dV/dt noise in the power signal must also be blocked, and such dV/dt noise is fairly unpredictable. The dV/dt noise may affect data integrity. Therefore, the inductors L 1 -L 4  and capacitors C 1 -C 4  are typically larger than required to adequately pass or block the DC voltage and pass or block the AC data signals. Noise in the power signal may arise while the PSE being turned on, or from other equipment on the power supply bus, or from other sources. 
     Similarly, a rapid change in the PD load current (dl/dt) affects the voltage delivered by the PSE, where a high positive dl/dt will cause a rapid temporary decrease in the voltage, and where a high negative dl/dt will cause a rapid temporary increase in the voltage. Such dV/dt changes in voltage may affect data integrity. 
     Thus, what is needed in the field of PoDL is an improved network that combines or separates the power signal and the wide bandwidth AC data while limiting noise in the power signal caused by dV/dt or dI/dt. 
     SUMMARY 
     Various circuits, in either the PSE or the PD or both, are described that limit the time rate of change of the voltage in the power signal to reduce the possibility of adverse effects of noise in the power signal. The circuits are separate from the PSE&#39;s or PD&#39;s passive LC coupling/decoupling network. This eases the requirements for the inductors and capacitors in the PSE and PD coupling/decoupling networks, enabling much smaller passive components to be used (which are typically discrete components), resulting in reduced sizes and costs of the networks. 
     Accordingly, a PSE and/or a PD in a 1-Pair PoDL system is described that minimizes PHY transients, such as resulting from PSE start-up and/or PD load current changes, by actively controlling the time rate of change of the power signal. A PSE/PD with this feature results in a circuit that requires substantially smaller LC filters in order to deliver an equivalent level of performance. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a conventional PoDL-enabled Ethernet system using a single wire pair for supplying power and data to the PD. 
         FIG. 2  illustrates a technique, in accordance with one embodiment of the invention, for pre-conditioning the power signal in the PSE during start-up to remove dV/dt noise prior to reaching the coupling/decoupling network. 
         FIG. 3A  illustrates a technique, in accordance with another embodiment of the invention, for limiting dV/dt at the PD due to dI/dt by the PD load to lower noise in the power signal. 
         FIG. 3B  illustrates a differentiator circuit that may be used in the circuit of  FIG. 3A . 
         FIG. 4  illustrates another technique, in accordance with another embodiment of the invention, for limiting dV/dt at the PD due to dI/dt by the PD load to lower noise in the power signal. 
     
    
    
     Elements that are the same or equivalent are labeled with the same numeral. 
     DETAILED DESCRIPTION 
       FIG. 2  illustrates the power generating portion of a PSE  20  in a PoDL system. The PD (not shown) may be similar to the conventional PD  12  in  FIG. 1 , although the filter requirements in the PD&#39;s decoupling network of the PD are eased by the present invention. The differential data portion of the PoDL system is not relevant to the present invention and may be conventional. 
     An analysis of the PHYs&#39; terminal voltage response to a change in the PSE voltage dV PsE /dt can assume one of three forms depending on the circuit&#39;s damping ratio: under-damped, critically damped, or over-damped, but at steady state it can be shown that: 
                 V   PHY     =         ⅆ     V   PSE         ⅆ   t       ×       50   ⁢           ⁢   Ω   ×     C   PHY       2         ,         
where the impedance of the PHY is assumed to be 2×50Ω, and C PHY  is the capacitance of the PHY&#39;s DC blocking capacitors C 1 -C 4 .
 
     Hence a slew rate limitation on dV PSE /dt is required in order to constrain the magnitude of voltage perturbations at either PHY. 
     For the PSE, various circuit topologies may be used to limit the dV PSE /dt as needed in order to ensure that the magnitude of the resulting voltage transients at the PHY terminals are limited. 
       FIG. 2  illustrates circuit architecture in a PSE  20  where a low-side N-channel MOSFET M 3  is enhanced with a pull-up current I 1  by current source  22  only during start-up of the PSE  20 , when variations in the power signal voltage occur. During start-up, the switch  24  is opened to allow the current I 1  to pull-up the gate of the MOSFET M 3  to ramp up its conductivity between ground and the bottom terminal of inductor L 2 . At start-up, the dV/dt at the drain of the MOSFET M 3  is fairly large so current will be conducted by the capacitor C 5  between the drain and the gate to reduce the percentage of the current from the current source  22  applied to the gate. This limits the turn on time of the MOSFET M 3 . As dV/dt is reduced (and the current into the capacitor C 5  is reduced), the percentage of the current from the current source  22  applied to the gate is increased until the MOSFET M 3  is completely turned on (i.e., V PSE−  is approximately ground). Thus, capacitor C 5  provides feedback from the drain of MOSFET M 3  to the gate in order to limit dV/dt to less than approximately I(I 1 )/C 5 . This technique uses the well-known Miller effect for MOSFETs. The current source  22  or capacitor C 5  can be selected to ramp up the conductivity of the MOSFET M 3  at any desired rate to limit dV/dt. Limiting dV/dt preserves data integrity and eases the filtering requirements of the coupling/decoupling networks. 
     At the end of the start-up ramp, the switch  24  remains open and the current I 1  fully turns on the MOSFET M 3  to cause it to operate in its linear region. The capacitor C 5  then acts as an open circuit. The closing of the switch  24  is for discharging the gate to turn off the MOSFET M 3  to terminate the power signal to the PD. The added components may be fabricated on the same chip as the PSE controller, since capacitor C 5  can be small. 
     Many other types of circuits may be used in place of the limiting circuit of  FIG. 2  to limit the time rate of change of V PSE−  or V PSE+  during start-up or during any other time. 
     Further, if noise generated by the DC voltage source  13  is an issue, a voltage regulator may be included to smooth the voltage applied to the V PSE+  and V PSE−  terminals. 
       FIGS. 3A and 4  show circuits that limit dV/dt at the PD, caused by rapid changes in the PD load current during or after start-up. 
     For a PD, the relationship between V PD  (i.e., PD voltage after filtering by the decoupling network) and V PHY  (i.e., voltage across the wire pair) is the same as for the V PSE  and V PHY . Ignoring the effects of parasitic resistance, the steady state relationship between dV PD /dt and PD current I PD  is: 
     
       
         
           
             
               
                 ⅆ 
                 
                   V 
                   PD 
                 
               
               
                 ⅆ 
                 t 
               
             
             = 
             
               
                 - 
                 4 
               
               ⁢ 
               
                   
               
               ⁢ 
               L 
               × 
               
                 
                   
                     ⅆ 
                     2 
                   
                   ⁢ 
                   
                     I 
                     PD 
                   
                 
                 
                   ⅆ 
                   
                     t 
                     2 
                   
                 
               
             
           
         
       
     
     Hence, the second derivative of the PD current should be constrained in order to limit the magnitude of voltage transients seen at the PHYs&#39; terminals. 
     Circuit architectures that limit the time rate of change in PD current offer a means of limiting PHY voltage transients. 
       FIG. 3A  illustrates a circuit architecture where dV PD /dt in the PD  30  is limited. A PD load (not shown) is connected to the Vout terminals of a DC-DC converter. The converter converts the incoming PoDL voltage to a regulated target voltage (e.g., 5 volts) used by the PD load. Such a load may automatically go into or come out of a standby mode and quickly change its current. Such a rapid change in load current typically causes a rapid change in the PoDL voltage. 
     In  FIG. 3A , an input capacitor C IN  partially smoothes the voltage across the V PD+  and V PD−  lines. A differentiator circuit  32  detects the voltage across the V PD+  and V PD−  lines and outputs a voltage proportional to dV/dt. A common differentiator circuit is shown in  FIG. 3B . The values of R and C in the circuit of  FIG. 3B  are adjustable to obtain the desired ratio of Vout vs dV/dt. 
     The output of the differentiator circuit  32  is differenced with respect to a fixed slew limit reference voltage (a threshold voltage) by a difference amplifier  34 . The output of the amplifier  34  is fed into a negative input of a control amplifier  36  for a voltage-mode buck DC-DC converter, thus limiting the time rate of change of the converter&#39;s duty cycle so that the dV/dt of V PD ) does not exceed the threshold. 
     A fixed reference voltage REF is applied to the positive input of the control amplifier  36 . The output voltage V OUT  of the converter is applied to another negative input of the control amplifier  36 . 
     The analog output of the control amplifier  36  acts as a control signal for a pulse width modulator (PWM)  38 . The PWM  38  may be conventional and may compare the control voltage to a sawtooth waveform. When the PWM  38  output is low, the NMOS transistor M 1  turns off and the PMOS transistor M 2  turns on to start a new charging cycle for the inductor L 5 . An output capacitor C OUT  smoothes the output of the converter for the PD load. By limiting the change in duty cycle, such as when the PD load comes out of a standby mode to draw more current, there will be a smoother ramp-up of current into the load, at the expense of rapid output voltage regulation, as the converter tries to increase the charging time of the inductor L 5 . This smoother ramp-up of current dynamically reduces dV/dt across the V PD+  and V PD−  lines so that the dV/dt of the V PD+  and V PD−  lines does not exceed a threshold limit. This limits the dI/dt (and d 2 I PD /dt 2 ) of the PD load current. Thus, changes in the PD load (e.g., going in or out of a standby mode) will have a limited effect on the dV/dt so that the filtering requirements for the decoupling components C 3 , C 4 , L 3 , and L 4  are reduced. 
     Many other types of DC-DC converters may be used instead of the buck type shown in  FIG. 3A . 
     As shown in  FIG. 4 , another approach to limiting d 2 I PD/dt   2  involves directly limiting the slew rate of the DC-DC converter&#39;s control voltage in order to limit the time rate of change of the PWM duty cycle. Assuming that changes in V PD ) are small due to changes in I PD ), the relationship between d 2 I PD /dt 2  and a buck DC-DC converter&#39;s duty cycle is approximately: 
     
       
         
           
             
               
                 
                   ⅆ 
                   2 
                 
                 ⁢ 
                 
                   I 
                   PD 
                 
               
               
                 ⅆ 
                 
                   t 
                   2 
                 
               
             
             = 
             
               
                 
                   ⅆ 
                   DC 
                 
                 
                   ⅆ 
                   t 
                 
               
               × 
               
                 
                   V 
                   PD 
                 
                 
                   L 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   5 
                 
               
             
           
         
       
     
     Hence, it can be seen that directly limiting the time rate of change of the converter&#39;s duty cycle may be sufficient for limiting the magnitude of voltage transients at the PHYs. 
       FIG. 4  illustrates a voltage-mode buck converter where the loop amplifier&#39;s control voltage slew rate is limited by a slew rate limited amplifier  44  in order to limit the time rate of change of the PWM duty cycle, where the duty cycle is proportional to the control voltage. The output voltage V OUT  is applied to the negative input of the difference amplifier  46 , and a fixed reference voltage REF is applied to the positive input. The output of the difference amplifier  46  represents the deviation of V OUT  from a target voltage. The slew rate limited amplifier  44  is a transconductance amplifier that feeds back its output to its negative input terminal, and a slew capacitor C SLEW  determines the maximum rate of change at the output. The output supplies the control voltage to the PWM  38  to determine the duty cycle of the DC-DC converter. By controlling the time rate of change of the duty cycle, the dV/dt of the power signal is limited. Thus, data integrity is maintained by the lowered dV/dt in the power signal not being passed by the DC blocking capacitors C 3  and C 4 . 
     Many other types of circuits may be used to limit the slew rate of the duty cycle of the DC-DC converter in the PD to prevent sudden changes in the PD load from resulting in a problematic dV/dt in the power signal. 
     The terms PSE and PD are used throughout this disclosure to identify equipment that supplies power and equipment that receives the power, and such equipment/devices are not limited to Ethernet equipment/devices unless specified. 
     While particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that changes and modifications may be made without departing from this invention in its broader aspects and, therefore, the appended claims are to encompass within their scope all such changes and modifications.