Abstract:
An apparatus comprising a transform circuit, a first coder circuit, a second coder circuit, and a memory circuit. The transform circuit may be configured to generate (i) one or more first coefficients in response to a sample signal when in a first mode and (ii) the sample signal in response to the first coefficients when in a second mode. The first coder circuit may be configured to generate (i) a first bitstream signal in response to one or more second coefficients when in the first mode and (ii) the second coefficients in response to the first bitstream signal when in the second mode. The second coder circuit may be configured to generate (i) a second bitstream signal in response to one or more third coefficients when in the first mode and (ii) the third coefficients in response to the second bitstream signal when in the second mode. The memory circuit may be configured to store the first coefficients, the second coefficients, and the third coefficients. The memory may be configured to allow the transform circuit, the first coder circuit, and the second coder circuit to operate independently.

Description:
FIELD OF THE INVENTION 
     The present invention relates to video processing generally and, more particularly, to a method and/or apparatus for implementing a high performance context-adaptive video processor. 
     BACKGROUND OF THE INVENTION 
     For a conventional H.264 video processor, the CABAC (or CAVLC) stage often creates a bottleneck for the encode or decode process. In a conventional H.264 codec, the entropy coder is connected directly to the transform function circuit. Since the transform function circuit represents a data path that may operate on multiple pixels or coefficients in parallel, performance can be scaled up by operating on a number of pixels in parallel. Performance for the entropy coder is harder to scale up because of the difficulty to parallelize operations across symbols (i.e., only one symbol can be decoded at a time). In addition, the complexity of CABAC and CAVLC encoding or decoding uses multiple clock cycles to process one symbol. CABAC in particular takes more than 2 clock cycles per symbol on average to process. The extra clock cycles place an upper bound on the maximum bit rate that can be practically supported in a given process technology which is often less than the desired amount. Although CABAC encoding/decoding provides more efficient compression than CAVLC encoding/decoding, CABAC encoding/decoding is slower than CAVLC encoding/decoding due to the complexity. 
     It would be desirable to resolve encoding and/or decoding bottlenecks to achieve a high performance system. 
     SUMMARY OF THE INVENTION 
     The present invention concerns an apparatus comprising a transform circuit, a first coder circuit, a second coder circuit, and a memory circuit. The transform circuit may be configured to generate (i) one or more first coefficients in response to a sample signal when in a first mode and (ii) the sample signal in response to the first coefficients when in a second mode. The first coder circuit may be configured to generate (i) a first bitstream signal in response to one or more second coefficients when in the first mode and (ii) the second coefficients in response to the first bitstream signal when in the second mode. The second coder circuit may be configured to generate (i) a second bitstream signal in response to one or more third coefficients when in the first mode and (ii) the third coefficients in response to the second bitstream signal when in the second mode. The memory circuit may be configured to store the first coefficients, the second coefficients, and the third coefficients. The memory may be configured to allow the transform circuit, the first coder circuit, and the second coder circuit to operate independently. 
     The objects, features and advantages of the present invention include providing a video processor that may (i) provide high performance context-adaptive video processing (ii) provide high performance context-adaptive video processing; (iii) implement two entropy coders to resolve potential performance bottleneck issues, potentially doubling system performance; (iv) store coefficients in a memory between the transform and entropy coders to balance the load between two processing units across frames; (v) allow one coder to operate in decode mode and one to operate in encode mode to provide more flexibility; and/or (vi) improve performance in transcoding of full duplex scenarios. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
         FIG. 1  is a block diagram of a video processor in accordance with the present invention; 
         FIG. 2  is a more detailed block diagram of the video processor of  FIG. 1  illustrating an encode path and a decode path; 
         FIG. 3  is a schematic block diagram of a transform function; and 
         FIG. 4  is a schematic block diagram of a entropy coder. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention may implement two (or more) instances of CAVLC/CABAC coders that may be decoupled from a transform stage to improve performance and/or resolve potential bottlenecks. Each CAVLC/CABAC coder may operate independently from the transform stage. In one example, both coders may encode two different pictures at the same time when the transform stage is encoding another picture. In another example, both coders may decode two different pictures at the same time when the transform stage is decoding another picture. In another example, one coder may encode one picture, while the other coder may be decoding another picture, independently of whether the transform stage is encoding or decoding a different picture. 
     Referring to  FIG. 1 , a block diagram of a circuit  100  is shown in accordance with an embodiment of the present invention. The circuit  100  may be implemented as a video processor circuit. The circuit  100  generally comprises a block (or circuit)  102 , a block (or circuit)  104 , a block (or circuit)  106  and a block (or circuit)  108 . The circuit  102  may be implemented as a transform function circuit. The circuit  104  may be implemented as a memory circuit. In one example, the circuit  104  may be implemented as a DRAM memory circuit. In one example, the circuit  104  may be implemented as one or more memory circuits (or modules). The circuit  106  may be implemented as a coding circuit. The circuit  108  may also be implemented as a coding circuit. The circuit  102 , the circuit  106  and the circuit  108  have been described as blocks (or circuits). However, the circuit  102 , the circuit  106  and/or the circuit  108  may be implemented as hardware, software, or a combination of hardware and/or software. 
     The circuit  102  may have an input  120 , an output  122 , an output  124 , and an input  126 . The input  120  may receive the signal SAMPLES. The output  124  may present the signal COEFFICIENTS — 0. The output  122  may present the signal SAMPLES. The input  126  may receive the signal COEFFICIENTS — 0. 
     The circuit  104  may have an input  130 , an output  132 , an input  134 , an output  136 , an input  138 , and an output  140 . The input  130  may receive the signal COEFFICIENTS — 0. The output  132  may present the signal COEFFICIENTS — 0. The input  134  may receive the signal COEFFICIENTS — 2. The output  136  may present the signal COEFFICIENTS — 2. The input  138  may receive the signal COEFFICIENTS — 1. The output  140  may present the signal COEFFICIENTS — 1. 
     The circuit  106  may have an input  152 , an output  154 , an output  156  and an input  158 . The input  152  may receive the signal COEFFICIENTS — 1 when the coder  106  is in the encode mode. The output  154  may present the signal COEFFICIENTS — 1 when the coder  106  is in the decode mode. The output  156  may present the signal BITSTREAM — 1 when the coder  106  is in the encode mode. The input  158  may receive the signal BITSTREAM — 1 when the coder  106  is in the decode mode. 
     The circuit  108  may have an input  160 , an output  162 , an output  164 , and an input  166 . The input  160  may receive the signal COEFFICIENTS — 2 when the coder  108  is in the encode mode. The output  162  may present the signal COEFFICIENTS — 2 when the coder  108  is in the decode mode. The output  164  may present the signal BITSTREAM — 2 when the coder  108  is in the encode mode. The input  166  may receive the signal BITSTREAM — 2 when the coder  108  is in the decode mode. 
     The transform function circuit  102  may convert the input signal SAMPLES to/from the signal COEFFICIENTS — 0 when in a respective encode mode or decode mode. The signal SAMPLES may represent a number of video picture samples. The signal COEFFICIENTS — 0 may represent one or more quantized coefficients. The transform circuit  102  may convert from a spatial domain to a frequency domain. Alternately, the transform circuit  102  may convert quantized coefficients (e.g., the frequency domain) to picture samples (e.g., the spatial domain). The memory circuit  104  may be used as storage for the signal COEFFICIENTS — 0 (e.g., quantized coefficients). The entropy coder circuit  106  may be used to convert the signal COEFFICIENTS — 1 to/from the signal BITSTREAM — 1. The signal COEFFICIENTS — 1 may represent a number of quantized coefficients. 
     Referring to  FIG. 2 , a more detailed diagram of the video processor  100 ′ is shown.  FIG. 2  illustrates data flow in the encode mode and decode mode. A number of encode paths  202 ,  204 ,  206 ,  208 ,  210 , and  212  are shown as dash lines. A number of decode paths  214 ,  216 ,  218 ,  220 ,  222 , and  224  are shown as solid lines. Since the memory  104  may be used to store the signals COEFFICIENTS — 0, COEFFICIENTS — 1, and COEFFICIENTS — 2, the transform circuit  102 , the coder circuit  106  and the coder circuit  108  may operate independently. For example, the transform circuit  102  may encode or decode while the coder circuit  106  and the coder circuit  108  may encode or decode. 
     Referring to  FIG. 3 , a block diagram of the transform function circuit  102  is shown. The circuit  102  generally comprises a block (or circuit)  302 , a block (or circuit)  304 , a block (or circuit)  306 , a block (or circuit)  308 , a block (or circuit)  310 , a block (or circuit)  312 , a block (or circuit)  314 , a block (or circuit)  316 , a block (or circuit)  318 , a block (or circuit)  320 , a block (or circuit)  322 , a block (or circuit)  324 , and a block (or circuit)  326 . The circuit  302  may be implemented as a motion vector generation circuit. The circuit  304  may be implemented as an access reference picture circuit. The circuit  306  may be implemented as a motion compensation circuit. The circuit  308  may be implemented as an Inter prediction circuit. The circuit  310  may be implemented as an Intra prediction circuit. The circuit  312  may be implemented as a multiplexer circuit. The circuit  314  may be implemented as a subtraction circuit. The circuit  316  may be implemented as a Forward Transform circuit. The circuit  318  may be implemented as a Forward Quantizer circuit. The circuit  320  may be implemented as an Inverse Quantizer circuit. The circuit  322  may be implemented as an inverse transform circuit. The circuit  324  may be implemented as an addition circuit. The circuit  326  may be implemented as a Deblocking Filter circuit. The transform circuit  102  normally performs the majority of the encoding and/or decoding functions, with the exception of entropy coding/decoding, which is normally performed by the coder  106  and/or the coder  108 . 
     Referring to  FIG. 4 , a diagram of the entropy coder circuit  106  (or  108 ) is shown. The circuit  106  generally comprises a block (or circuit)  402 , a block (or circuit)  404 , a block (or circuit)  406 , and a block (or circuit)  408 . The circuit  402  may be implemented as a CAVLC encoder (Context-Adaptive Variable Length Coding). The circuit  404  may be implemented as a CABAC (Context-Adaptive Binary Arithmetic Coding) encoder. The circuit  406  may be implemented as a CAVLC decoder (Context-Adaptive Variable Length Coding). The circuit  408  may be implemented as a CABAC (Context-Adaptive Binary Arithmetic Coding) decoder. 
     The encoders  402  and  404  generally convert the signal COEFFICIENTS — 1 (e.g., the signal Quantized Coefficients) into the signal BITSTREAM — 1. The decoders  406  and  408  generally convert the signal BITSTREAM — 1 into the signal COEFFICIENTS — 1. While the coder  106  has been described, the coder  108  may have a similar implementation. 
     The coder  106  and the coder  108  may each be implemented as an H.264 compliant entropy coder. The coder  106  and the coder  108  may contain either a CAVLC block  402  (or  406 ), a CABAC block  404  (or  408 ), or both a CAVLC and a CABAC block. In one example, the Context Adaptive Variable Length Coding encoder  402  may be used to map input symbols to a series of variable length code words. Each code word may contain an integer number of bits. Frequently occurring symbols may be represented with short VLCs. Less common symbols may be represented with long VLCs. Over a sufficiently large number of encoded symbols, the VLCs lead to compression of data. Context Adaptive generally refers to using local spatial and/or temporal characteristics to decide how a symbol is coded. 
     In one example, the Context Adaptive Binary Arithmetic Coding encoder  404  may convert a sequence of data symbols into a single fractional number. An optimal fractional number of bits may be used to represent each symbol. Arithmetic coding may more closely approach theoretical maximum compression ratios. The principal advantage of arithmetic coding occurs when the transmitted number is not constrained to an integer number of bits for each transmitted symbol. Context adaptive normally refers to local spatial and/or temporal characteristics that may be used to decide how a symbol is coded. Compared to BAC, compression efficiency of VLC is poor for symbols with probabilities greater than 0.5, since the best compression that may be achieved occurs by representing these symbols with a single bit code. 
     The transform function circuit  102  may implement the following operations (or steps) during the encode mode: 
     1) The motion vector generation circuit  302  may generate motion vectors based on differences between a reference picture and a target picture; 
     2) the access reference picture circuit  304  may generate the signal REFERENCE_SAMPLES based on the motion vectors; 
     3) the perform motion compensation circuit  306  and the Inter-Prediction circuit  308  may operate on the signal REFERENCE_SAMPLES; 
     4) the select prediction circuit  312  may select between the Inter-Prediction circuit  308  and the Intra-Prediction circuit  310 ; 
     5) the subtract circuit  314  may subtract the signal TARGET_SAMPLES from the signal REFERENCE_SAMPLES received from the select prediction circuit  312 ; 
     6) the Forward Transform circuit  316  and the Forward Quantization circuit  318  may generate the signal COEFFICIENTS — 0 (e.g., one or more quantized coefficients); 
     7) the signal COEFFICIENTS — 0 may be presented to the Inverse Quantization circuit  320  and the inverse transform circuit  322 ; 
     8) the add circuit  324  may add the result of the inverse transform circuit  322  to the result of the select prediction circuit  312  to generate the signal RECONSTRUCTED_SAMPLES; 
     9) the signal RECONSTRUCTED_SAMPLES may be presented to the Intra Prediction circuit  310  and the Deblocking Filter Circuit  326 ; and 
     10) the result of the Deblocking Filter circuit  328  may be presented as the output signal SAMPLES to be displayed and used as a reference picture for later pictures. 
     During the decode mode, the above steps 1, 2, 3, 4, 7, 8, 9, and 10 may be applied with the motion vectors being determined from the bitstream. 
     To solve performance bottlenecks during encoding and/or decoding, the video processor circuit  100  uses entropy coder  106  and entropy coder  108 , which doubles the effective performance. The transform function circuit  102 , the entropy coder circuit  106  and the entropy coder circuit  108  are separated entities operating independently. The signal COEFFICIENTS — 0 are stored in the memory circuit  104 . This allows the entropy coder circuit  106  and the entropy coder circuit  108  to operate at the average bit rate for a sequence rather than the peak bit rate for a single macroblock without creating a performance bottleneck. The peak bit rate for a macroblock may be a factor of 30 higher than the maximum average bit rate for a sequence. In addition, the circuit  100  allows the entropy coder circuit  106  and the entropy coder circuit  108  to operate on different frames which is necessary to implement a parallel operation when there is a single slice per frame. 
     During encode mode, the signal SAMPLES from spatial domain is converted into frequency domain signal COEFFICIENTS — 0, then stored into the memory circuit  104 . The memory circuit  104  may also store macroblock header information and motion vector information, which may be coded by the entropy coder circuit  106  and/or the entropy coder circuit  108 . The entropy coder circuit  106  and the entropy coder circuit  108  may encode the signal COEFFICIENTS — 1 and the signal COEFFICIENTS — 2 in parallel. The transform function circuit  102  may work on one picture while the entropy coder circuit  106  and the entropy coder circuit  108  are each independently working on different previously transformed pictures. The frame processing time of the entropy coder circuit  106  and the entropy coder circuit  108  may be different, depending on the complexity of each frame. The load may be balanced between the entropy coder circuit  106  and the entropy coder circuit  108  by having each coder start processing the oldest remaining transformed picture when the processing of a previous picture is complete. 
     In some embodiments where the different pictures are part of the same program content (e.g., a single program encode mode), BITSTREAM — 1 and BITSTREAM — 2 may be subsequently combined by a multiplex operation of the circuit  100  to establish an output bitstream. The output bitstream may appear to a standard decoder as if encoded by a single entropy coder circuit  106  or entropy coder circuit  108 . In other embodiments where the different pictures are from different programs (e.g., a multiple program encode mode), the programs may be time shared in the signal SAMPLES, operated on by the transform function circuit  102  and stored in the memory circuit  104 . Thus, BITSTREAM — 1 and BITSTREAM — 2 may by presented from the circuit  100  independent of each other since each carries a separately encoded program. 
     During decode mode, BITSTREAM — 1 and BITSTREAM — 2 from two different pictures may be processed at the same time by the entropy coder circuit  106  and the entropy coder circuit  108 . Both decoded signals COEFFICIENTS — 1 and COEFFICIENTS — 2 of different pictures can be stored in the memory circuit  104 . The memory circuit  104  may also store macroblock header information and motion vector information, which may be generated by the entropy coder circuit  106  and/or the entropy coder circuit  108 . The macroblock header information and motion vector information stored in the memory circuit  104  is normally (i) generated from the coder circuit  106  or  108  when the coder circuit  106  or  108  is in decode mode (used by the transform circuit  102 ) and (ii) used by the coder circuit  106  or  108  when the coder circuit  106  or  108  is in the encode mode (generated from the transform circuit  102 ). At the same time, or substantially simultaneously, the transform function circuit  102  may work on the signal COEFFICIENTS — 0 from the earlier decoded picture. The frame processing time of the entropy coder circuit  106  and the entropy coder circuit  108  may be different, depending on the complexity of each frame, but the load can be balanced between the entropy coder circuit  106  and the entropy coder circuit  108  by having each coder circuit start processing the oldest remaining undecoded picture when the processing of a picture is complete. 
     In some embodiments where the different pictures are part of the same program content (e.g., a single program decode mode), a parser operation of the circuit  100  may separate an input bitstream into BITSTREAM — 1 and BITSTREAM — 2 before reception at the entropy coder circuit  106  and the entropy coder circuit  108 . After entropy decoding, the original picture sequence may be established in the signal COEFFICIENTS — 0 as the coefficients are read from the memory circuit  104  to the transform function circuit  102 . In other embodiments where the different pictures are from different programs (e.g., a multiple program decode mode), BITSTREAM — 1 and BITSTREAM — 2 may be separately received by the circuit  100 , entropy decoded by the entropy coder circuit  106  and the entropy coder circuit  108 , and the results stored in the memory circuit  104 . The resulting coefficients may be time multiplex in the signal COEFFICIENT — 0 to the transform function circuit  102  for additional processing in a time share manner. 
     During the encode/decode mode, the transform function circuit  102 , the memory circuit  104  and one of the entropy coder circuits (e.g.,  106 ) may encode an input program received at the input  120  to generate BITSTREAM — 1. For example, see encode paths  202 ,  204 ,  206  and  208  in  FIG. 2  In parallel, the other entropy coder circuit (e.g.,  108 ), the memory circuit  104  and the transform function circuit  102  may decode BITSTREAM — 2 to generate an output program at the output  122 . For example, see decode paths  218 ,  220 ,  222  and  224  in  FIG. 2 . As such, the transform function circuit  102  may time share between encoding the input program and decoding the output program. 
     While two coder circuits  106  and  108  have been described, additional coders may be implemented. For example, three or more coders may be implemented. Additionally, while the two coder circuits have been described as having a similar implementation, additional implementations may be implemented. For example, one coder circuit may be configured to handle the majority of processing, while another coder circuit may be configured to handle less processing (e.g., a special case, high priority frames, etc.). 
     As used herein, the term “simultaneously” is meant to describe events that share some common time period but the term is not meant to be limited to events that begin at the same point in time, end at the same point in time, or have the same duration. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.