Abstract:
Multiple thread functionality in a general purpose set theoretic processor (GPSTP) is implemented by addition of a thread memory for processing multiple interleaved data input streams to enable state save-and-restore functionality. The thread memory is functionally distributed among three parts of the GPSTP that change state during execution. The system structure minimizes the number of bits required to be saved and restored, and cell structures are configured implement the multi-thread functionality.

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
     The present application claims benefit under 35 USC 119(e) of U.S. provisional Application No. 60/862,726, filed on Oct. 24, 1007, entitled “MULTIPLE THREAD FUNCTIONALITY,” the content of which is incorporated herein by reference in its entirety. 
     The present application is related to and incorporates the contents of the following US application by reference in its entirety and which is not to be considered to be prior art: U.S. application Ser. No. 11/353,318, entitled “General Purpose Set Theoretic Processor”, filed Feb. 13, 2006. 
    
    
     BACKGROUND OF THE INVENTION 
     STATEMENT AS TO RIGHTS TO INVENTIONS MADE UNDER FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
     NOT APPLICABLE 
     REFERENCE TO A “SEQUENCE LISTING,” A TABLE, OR A COMPUTER PROGRAM LISTING APPENDIX SUBMITTED ON A COMPACT DISK 
     NOT APPLICABLE 
     This invention relates to improvements in a general purpose set theoretic processor (GPSTP). A GPSTP is a systolic (i.e., stimulus-response) processor consisting of N building block modules (BBMs), each of which is itself a systolic processor, as explained elsewhere. Each BBM has a recognition network and an aggregation network. The aggregation network as described in the related patent application Ser. No. 11/353,318 has two components of interest, an aggregation routing matrix and a threshold logic unit. The recognition network and the aggregation network are controlled by an external stimulus-response sequencer, also as explained elsewhere. In scan mode, the recognition network generates a 1024 bit response for every input stimulus-byte. 
     The prior GPSTP has certain limitations that inhibit its versatility. In certain modes of operation, a GPSTP must receive inputs (messages, documents) from data streams as segmented threads such that several segments must be assembled to form a whole thread. Such data streams are generated by a plurality of sources and multiplexed so that segments belonging to different entities are interleaved. Thus, there is a need to scan segments from a plurality of sources and to save the GPSTP state for each source while scanning segments from other sources and restoring the GPSTP state for a source when its next segment is scanned. The speed requirements for applications such as those in the above scenario make preserving state external to the GPSTP prohibitive. 
     The prior GPSTP occupied all of the space available on the highest capacity contemporary integrated circuit (IC) medium. The nature of the GPSTP concept demands total capacity from implementation media, requiring relatively large amounts of memory. So some means must be found to reduce the implementation resource required by the GPSTP while maintaining its capacity, functionality and speed. What is needed are improvements that address those limitations. 
     BRIEF SUMMARY OF THE INVENTION 
     According to the present invention, an improvement is provided for processing multiple interleaved data input streams in a general purpose set theoretic processor, wherein a thread memory is provided to enable state save-and-restore functionality. The thread memory is functionally distributed among three parts of the GPSTP that change state during execution. 
     In order to provide resources for thread memory of a GPSTP, one of the major components of the GPSTP is reorganized, reducing by two-thirds the number of memory bits and by one-half the number of logic gates it uses as compared to prior embodiments. This reorganization also results in more flexible and efficient use of the remaining resources. 
     Specifically according to the invention, a new sub-system is added to a GPSTP in order to minimize the number of bits required to be saved and restored, thereby making the throughput performance of the GPSTP comensurate with the prior GPSTP. A number of cell structures are modified to implement the multi-thread functionality. 
     The invention will be better understood upon reference to the following detailed description in connection with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a general purpose set theoretic processor according to the invention. 
         FIG. 2  is a block diagram of a detection cell according to the invention. 
         FIG. 3  is a block diagram of an activity routing cell illustrating specific inputs according to the invention. 
         FIG. 4  is a block diagram of a portion of a recognition network illustrating reconfigurable synchronization configuration according to with the invention. 
         FIG. 5  is a block diagram of selected details of a latch matrix, aggregation matrix and a threshold logic matrix of the aggregation network of  FIG. 1 . 
         FIG. 6  is a block diagram showing preferred inputs and outputs of a latch cell of a latch matrix. 
         FIG. 7  is a block diagram showing preferred inputs and outputs of an aggregation routing cell. 
         FIG. 8  is a block diagram showing preferred inputs and outputs of a threshold logic cell. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to  FIG. 1 , a general purpose set theoretic processor has a recognition network  10  with a latent response memory (MR)  12 , coupled via a recognition matrix (RM)  14 , to an activity matrix (AM)  16 , and at least one state save and restore memory (SSRM)  18  coupled to the recognition matrix  14 . As hereinafter explained, the SSRM  18  is one of three such added to implement the functions necessary for dealing with multiple threaded sources. 
     The latent response memory (MR)  12  is a 256×1024 random access memory. Each of its columns MR i  is connected to a detection cell DC i .  22   i  of the recognition matrix (RM)  14 . Each of its rows MR r  is loaded with the latent response specified by the current reference pattern to the stimulus-byte whose digital value is equal to the row number. On each input cycle, MR b  (the row whose number is equal to the input stimulus-byte) is conjunctively combined with the state of the recognition matrix (RM)  14  to produce a manifest response; each of its bits MRb,i is ANDed with the state of the corresponding detection cell DC i  to generate response R i , which is one bit of the manifest response. 
     The principal goal of the present invention is to provide a multiple thread capability in the GPSTP without diminishing capacity (i.e., number of detection cells  22   i ), the functionality or the throughput speed of the GPSTP. Modification of the latent response memory (MR)  12  ( FIG. 1 ) to use one column of  256  bits per detection cell instead of three such columns releases large numbers of memory cells to be used elsewhere, such as for the save and restore memory (SSRM)  18  ( FIG. 1 ), the latch save and restore memory (LSRM)  38  ( FIG. 1 ) and the threshold count save and restore memory. (TCSRM)  40  ( FIG. 1 ). In the prior GPSTP, three 256-bit columns of memory were required to store latent responses for each detection cell, one column each for auto-activation, for activation of other detection cells and for transmitting results to the aggregation network. Since it is rare that any detection cell requires more than one of these functions, and since in most cases where two functions are required (e.g., auto-activation and activation of other detection cells), it has been recognized that all of the same response bits can be used for both purposes, for most cases a single memory column can be used. This modification requires changes to the detection cell (DC)  22  ( FIG. 2 ) and the activation routing cell  24  ( FIG. 3 ), as well as to the latent response memory  12  ( FIG. 1 ) itself. 
     The save and restore memory (SSRM)  18  is typically a 256×1024-bit memory. When a source appears in the interleaved stimulus stream other than that being processed, the current recognition matrix state S=S 1 , S 2 , . . . , S 1024  is stored at row SSRM FN  (FN being the source or flow number). When the interrupted flow resumes, the current state for the in process flow is saved to SSRM FN′ , and the contents of SSRM FN  are retrieved and used to restore the state of the recognition matrix  14 . When an input block (e.g., a message) is complete, its final state is not saved, and the row in SSRM  18  that its saved state had occupied is released. Flow number management is performed in software external to the GPSTP. 
     According to present invention, only one MR column of 256 bits is used for each detection cell (DC)  22   i , providing a mechanism for linking detection cells in those cases when more than one of the three functions is needed for recognizing simplex stimuli. They are linked by means of activity routing cells (ARC i )  24   j,i  ( FIG. 4 ) in the activity matrix  24  ( FIG. 1 ) in the recognition network  10  ( FIG. 1 ). In the prior GPSTP, there was the mapping DC p →DC s  (predecessor DC p  activates successor DC s ) and the DC s  is configured to respond with all three functions. 
     Referring to  FIG. 4 , in the GPSTP  10  modified according to the present invention DCi  22   i →DCc  22   c  (read, “DCi and activates DCc”), DCi→DC s1    22   s1 , DCi→DC s2    22   s2 c , and DC c →DC s1 , DC c →DC s2 . The detection cell c DC c  is configured (via activity routing cell ARC 1,c    24   1,c ) to auto-activate whenever it is active, and its latent response to stimulus-byte b at input  15  is MR b,c    12   i =1. DC s1  is configured by ARC 1,c  ≧ 1,c  and ARC 1,s1  ≧ 1,s1 , and DC s2  is configured by ARC 1,c , ARC 1,s1 , and ARC 1,s2    24   1,s2  to activate under the same conditions as DC c . Further, DC s1  and DC s2  are configured to activate detection cells elsewhere in the recognition matrix. This linkage assures that the linked cells are always in the same state, thus assuring that the linked cells perform exactly as a single detection cell using three columns of memory as in the prior GPSTP. 
     The types of linkage paths are illustrated in  FIG. 4 . The bold dashed line represents the ARC configuration that enables DC i    22   i  to initiate synchronization of DC c    22   c  with DC s1    22   s1  and DC s2.    22   s2 . The bold solid line represents the ARC configuration that enables DC c  to synchronize the states of DC s1  and DC s2  with its own state. The bold dotted line represents an ARC configuration that enables DC s1  to activate one or more detection cells elsewhere in the recognition matrix. The bold dashed and dotted line represents an ARC configuration that enable DC s2 s to activate one or more detection cells elsewhere in the recognition matrix (RM)  14 . 
     The recognition matrix (RM)  14  is a 1×1024 set of detection cells DC i .  22   i . In the prior GPSTP, each DC i .  22   i  was connected to its immediate physical neighbor. According to the present invention, these cells have no direct connections among themselves and, except for physical proximity, they have no inherent order. The present invention connects detection cells via the activity matrix(AM)  16  according to the currently loaded reference pattern. Detection cells  22  of the present invention have a further input and further output in addition to those inputs and outputs found in the prior GPSTP. 
     The following transition functions are to be noted:
         SSRM FM,i  The state of DC i  is restored with value input from SSRM FM,i      S i  The current state of DC i  is output to SSRM FM,i  for preservation.       

     Detection cells are subject to two additional controls:
         SAV SAV is used to preserve state values of the recognition matrix RM, the latch matrix LM and the counts of the threshold logic cells in the aggregation network (AN)  30 .   RES RES recalls saves states and restores the GPSTP with them.       

     As with the prior GPSTP, the state S i  is the state of detection cell DC i .  22   i . State S i =1≡Active S i 0≡Inactive. 
     Referring to  FIG. 2 , the detection cell  22  itself has been simplified by removal of the auto-activation to the Activity Matrix  24 . The following are the cell&#39;s inputs, outputs, and logic equations. 
     Inputs:
         IS i  Initial state for DC 1      MR b,i  Latent Response for stimulus-byte b and DC i      UE j.i  Union of all signals in the Activation Matrix directed to activating DC i      SSRM FN,i  The restoration state for DC i  and source (flow) number FN.       

     Outputs:
         S i  The current State of DCi output to SSRM FN,i      R i  Manifest Response output to Latch Cell LC i  and to Activity Routing Cells ARC 1,i  thru ARC 10,i          

     Manifest Response:
 
Ri←C 1  &amp; S i  &amp; MR b,i  
 
     Initiate State:
 
S i ←INI &amp; IS i  
 
     Next State:
 
S i ←C 2  &amp; UE j.i  
 
     Restore Detection Cell State:
 
S i ←RES &amp; SSRM FN,j  
 
     Save Detection Cell State:
 
SSRM FN,j ←S i  &amp; SAV
 
     Referring again to  FIG. 1 , the activity matrix (AM)  16  is a rectangular array of potential pathways that can be used to connect the manifest response R i  of any detection cell (DC i )  22   i  to any set of detection cells. In the prior GPSTP, a detection cell could be configured to auto-activate on specified conditions. The present invention modifies the AM  16  so that a DC  22  can be connected to itself, as well as to any other detection cell. This modification removes the auto-activation function from the detection cell to the activity matrix, simplifying the DC. A reference pattern configures the AM  16  into a network of actual connections that allow a first DC  22  to activate other detection cells (including itself) for the next stimulus-byte input. If the DC  22  is not activated by itself or another detection cell, it is inactive for the next input cycle. 
     The AM  16  accrues no new inputs or outputs as a consequence of operation according to the present invention. Referring to  FIG. 3 , there is however one modification to the activity response cells (ARC j,i )  24   j,i, , namely, one additional connection in its internal logic. The AM  16  is a pure passive interconnection network which does not change between reference pattern loads. Thus it is not subject to any execution controls. 
     Its modification can be seen in a change to one logic equation. The equations for the Unified Enable output are:
 
Compare prior: UE j.i ←UE j+.i V(AFP j−1,i  &amp; FP j−1,i )V(ARP j−1,i  &amp; RP j+1,i ))
 
Present: UE j.i ←UE j+.i V(AFP j−1,i  &amp; FP j−1,i ) V ((ARP j−1,i  &amp; (R i  &amp; SRP j,i )) V (RPS j,i  &amp; RP j+1,i ))
 
Where:
         ARP j,i ≡Accept Reverse Propagation—incorporate the activation signal from ARC j,i+1  into UE j.i      RP j,i+1 ≡Reverse Propagation—Activation signal from ARC j,i+1      UE j+.i ≡Union of activation signals from ARC 10,i  thru ARC j+2,i  and all the activation signals routed through them   R i ≡Manifest Response from DC i      SRP j,i ≡Select Reverse Propagation—incorporate R i  activation signals routed from ARC j,i+1  through ARC j,i  into RP j,i      RPS j,i ≡Reverse propagation switch—pass activation signals from ARC j,i+1  Through ARC j,i  to ARC j,i−1          

     This embodiment incorporates the Manifest Response R i  into the activation (aka activity) signal fed into DC i , thereby enabling auto-activation through the AM  16  without auto-activation circuitry within each DC i . 
     The remaining ARC  24  equations are: 
     Forward Propagation
 
FP j.i ←(Ri &amp; SFP j,i )V (FPS j,i  &amp; FP j−1,i )
 
Reverse Propagation:
 
RP j.i ←(Ri &amp; SRP j,i )V (RPS j,i  &amp; RP j+1,i )
 
     The second major component of the GPSTP, an aggregation network (AN)  30  ( FIG. 1 ) has two major components: an aggregation routing matrix (AGRM)  32  and a threshold logic matrix(TLM)  34 . The RM/AGRM interface is a unidirectional connection of 1024 bits through latch matrix  36 . This connection brings the RM  14  manifest response to the AGRM  32  on every stimulus-byte input cycle. Internally, connections in the aggregation network  30  are all M-bit unidirectional, as shown. 
     The AGRM  32  maps selected detection cells  22  to one or more threshold logic cells (TLCj)  34   j . The TLCs  34   j  determine when satisfaction of conditions mapped to it is sufficient. 
     Referring to  FIG. 1 , according to the present invention, three more components are added, a latch matrix (LM)  36 , a latch state save and restore memory (LSSRM)  38 , and a threshold state save and restore memory (TCSRM)  40 . 
     Referring to  FIG. 5 , the LM  36  comprises a 1×1024 array of latch cells (LC i )  36   i , one LC i    36   i  for each DC i    22   i  The LSSRM  38  ( FIG. 1 ) is a 256×1024 random access memory. The latch matrix state (L 1  . . . L 1024 ) is saved to and restored from LSSRM  38  in the same manner as the recognition matrix  14  ( FIG. 1 ) is saved to and restored from the SSRM  18 . 
     On each stimulus-byte input, the selected LCi ( FIG. 6 ) accepts the manifest response Ri from DCi. It passes every R i =1 through to the i th  row of aggregation routing cells AGRC 1,i  . . . AGRC m,i ,  32   1,i  . . .  32   M,i  ( FIG. 7 ). It sends R′ i =1 to AGRC 1,i  . . . AGRC M,i ,  32   1,i  . . .  32   M,i  only on the first occurrence of R i =1, thereafter it sends R′ i =0. until it is reset either by load of a new reference pattern or by restoration from TCSRM FN,I   40   FN,I . 
     LC equations are given as follows: 
     Initialize
 
L i ←1
 
First Recognition:
 
R′ i ←C 1  &amp; R i  &amp; L i  
 
Latch State:
 
L i ←L i  V ((C 1  &amp; R i ) V INI) &amp; ((C 1  &amp; ˜R i ) V INI V (RES V LSRM FN,j ))
 
Save Latch State:
 
LSRM FN,j ←L i  &amp; SAV
 
Restore Latch State:
 
L i ←RES &amp; LSRM FN,j  
 
     The aggregation routing matrix (AGRM)  32  ( FIG. 5 ) is an M×1024 array of aggregation routing cells (AGRC M,i )  32   M,i . AGRC M,i s are used to route manifest response outputs from detection cells that are the last in a term (set of interconnected DCs  22  meant to recognize equivalent input stimuli). 
     Each Y/N switch of AGRC M,i    32   M,i  is set by the current reference pattern and does not change until a different reference pattern is loaded. The state Y/N j,i  determines whether a particular R i  (or R′ i ) is routed to TLC j    34   j . The latch/no-latch switch signal LNL j,i  is likewise set by the reference pattern and not changed until another is loaded. This switch determines whether Ri or R′i is routed. The AGRC  32  has no state that can change during scan execution. Once the switches are set, the AGRM  32  is a passive routing matrix, a set of static connections. Therefore it has nothing that needs to be saved and restored on change of source. 
     The threshold logic matrix (TLM)  35  ( FIG. 5 ) is a linear array of M×1 36-bit threshold logic counters (TLC)  35   i  ( FIG. 8 ). The value of the TLCs  35   i  is the third element of the GPSTP state and must be saved and restored at change of source. 
     The TCSRM  40  is a 256×1024 random access memory. The values of the TLCs  35   i  [(TLV 1,1  . . . L 1, 1024 ), (TL 2,1  . . . L 2, 1024 ) . . . (TL 32, 1  . . . L 32, 1024 )] are saved to TCSRM FN,1 . . . 32;  TCSRM FN,33 . . . 64;  . . . TCSRM FN,992 . . . 1024  and restored therefrom. 
     The invention has now been explained with reference to specific embodiments. Other embodiments are evident to those of ordinary skill in the art. It is therefore not intended that this invention be limited, except as indicated by the appended claims.