Abstract:
Disclosed is a method for testing multi-chip stacked packages. Initially, one or more substrate-less chip cubes are provided, each consisting of a plurality of chips such as chips stacked together having vertically connected with TSV&#39;s where there is a stacked gap between two adjacent chips. Next, the substrate-less chip cubes are adhered onto an adhesive tape where the adhesive tape is attached inside an opening of a tape carrier. Then, a filling encapsulant is formed on the adhesive tape to completely fill the chip stacked gaps. Next, the tape carrier is fixed on a wafer testing carrier in a manner to allow the substrate-less chip cubes to be loaded into a wafer tester without releasing from the adhesive tape. Accordingly, the probers of the wafer tester can be utilized to probe testing electrodes of the substrate-less chip cubes so that it is easy to integrate this testing method in TSV fabrication processes.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to a manufacture method of semiconductor devices, and more specifically to a method for testing multi-chip stacked packages. 
       BACKGROUND OF THE INVENTION 
       [0002]    Multi-chip packaging is an advanced high-density packaging technology to vertically stacking a plurality of dice within the same package. The existing packaging method is to stack individual chips onto a substrate followed by corresponding packaging and testing processes. However, using a substrate increases overall package thickness and footprint. 
         [0003]    In order to reduce the dimension of a multi-chip package, there is an attempt to stack a plurality of chips using wafer-to-wafer bonding to manufacture a substrate-less chip cube such as related technology revealed in US Patent No. 2011/0074017. However, bad chips are always randomly present within a wafer, therefore, wafer-to-wafer bonding would cause overall packaging yield of substrate-less chip cubes to drop. Moreover, when a substrate is eliminated, the pitch between the external electrical electrodes or/and the testing electrodes of a chip cube is shrunk from a few hundred micrometer down below a hundred micrometer so that the existing pogo pins of a tester for conventional semiconductor packages can not be used. There are two solutions to resolve the shrunk pitch issue. The first one is to directly SMT bond the substrate-less chip cube onto a board without any testing followed by a module test without ensuring the electrical joints between the stacked chips good or bad. The other one is to directly mount the substrate-less chip cube onto an interposer (normally made of Si) with fan-out circuitry and fan-out electrodes then load the interposer into a tester having pogo pins to perform testing where the overall testing cost is quite complicated and expensive. 
       SUMMARY OF THE INVENTION 
       [0004]    The main purpose of the present invention is to provide a method for testing multi-chip stacked packages to achieve fine-pitch probing of substrate-less chip cubes which can easily be integrated into TSV packaging processes. 
         [0005]    The second purpose of the present invention is to provide a method for testing multi-chip stacked packages to test one or more substrate-less chip cubes before SMT on boards and to reduce the number of adhering steps of adhesive tapes to achieve lower packaging cost and to prevent SMT bonding bad substrate-less chip cube on boards. 
         [0006]    According to the present invention, a method for testing multi-chip stacked packages is revealed. Firstly, one or more substrate-less chip cubes are provided, each of which consisting of a plurality of vertically stacked chips where a stacked gap is formed between two adjacent chips and each substrate-less chip cube has a plurality of testing electrodes disposed on a top chip surface. Then, the substrate-less chip cubes are attached onto an adhesive tape where the testing electrodes are away from the adhesive tape with the adhesive tape attached inside an opening of a tape carrier. Then, a filling encapsulant is disposed on the adhesive tape to fully fill the stacked gaps between adjacent chips. Then, the tape carrier is fixed on a wafer testing carrier so that the substrate-less chip cubes can be loaded into a wafer tester without releasing from the adhesive tape. Finally, a plurality of testing probes of a probe card mounted on the probe head of a wafer tester probe on the testing electrodes to electrically test the substrate-less chip cubes. 
     
    
     
       DESCRIPTION OF THE DRAWINGS 
         [0007]      FIGS. 1A to 1I  are cross-sectional component views illustrating main processing steps of the method for testing multi-chip stacked packages according to the preferred embodiment of the present invention. 
           [0008]      FIGS. 2A and 2B  are a top view and a cross-sectional view of a wafer testing carrier utilized in the method for testing multi-chip stacked packages according to the preferred embodiment of the present invention. 
           [0009]      FIGS. 3A and 3B  are a top view and a cross-sectional view of another wafer testing carrier utilized in the method according to a variant embodiment of the preferred embodiment of the present invention. 
           [0010]      FIG. 4  is a top view illustrating a tape carrier loaded on the wafer testing carrier of  FIG. 2A  according to the preferred embodiment of the present invention. 
           [0011]      FIG. 5  is a three-dimensional view of a wafer tester implemented in the method for testing multi-chip stacked packages according to the preferred embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0012]    With reference to the attached drawings, the present invention is described by means of the embodiment(s) below where the attached drawings are simplified for illustration purposes only to illustrate the structures or methods of the present invention by describing the relationships between the components and assembly in the present invention. Therefore, the components shown in the figures are not expressed with the actual numbers, actual shapes, actual dimensions, nor with the actual ratio. Some of the dimensions or dimension ratios have been enlarged or simplified to provide a better illustration. The actual numbers, actual shapes, or actual dimension ratios can be selectively designed and disposed and the detail component layouts may be more complicated. 
         [0013]    According to the preferred embodiment of the present invention, the method for testing multi-chip stacked packages is revealed where cross-sectional component views of each processing step of the method for testing multi-chip stacked packages is illustrated in  FIG. 1A  to  FIG. 1I . 
         [0014]      FIG. 1A  and  FIG. 1B  illustrate the manufacture processing flow of the substrate-less chip cubes  100 . Firstly, as shown in  FIG. 1A , a plurality of chips  110  are formed from dicing a wafer where a plurality of testing electrodes  130  and a plurality of external electrodes  131  are disposed on a top chip surface of each chip  110 . During dicing and after dicing, the chips  110  are adhered on a dicing tape  210  where the dicing tape  210  is adhered to a wafer frame (not shown in the figures). During dicing processes, a dicing blade  220  cuts through the scribe lines of a wafer to form individual chips  110 . After wafer testing, known good dices  110  are sorted and collected. As shown in  FIG. 1B , a plurality of chips  110  are vertically stacked on a chip carrier  230  to form one or more substrate-less chip cubes  100  where a stacked gap  120  is formed between two adjacent chips  110  and a plurality of testing electrodes  130  are disposed a top chip surface of each substrate-less chip cube  100  where the testing electrodes  130  may be metal pads or bumps. In this embodiment, the testing electrodes  130  are central pads exposed from the topmost active surface of the top chip  110 . Moreover, a plurality of external electrodes  131  are disposed on the top chip surface of the topmost chip  110  such as copper pillars, solder balls, or metal bumps where normally the pitch between the testing electrodes  130  is larger than the pitch between the external electrodes  131 , the testing electrodes  130  are electrically connected with the corresponding external electrodes  131 . In the present embodiment, the pitch between the testing electrodes ranges from 60 um to 100 um and the pitch between external electrodes  131  ranges from 30 um to 60 um. In a various embodiment, the external electrodes  131  can be eliminated and the testing electrodes  130  can be used also as the external electrodes  131 . As shown in  FIG. 1B , in the present embodiment, each chip  110  has a plurality of TSVs (through silicon vias)  111  inside which are electrically connected to the external electrodes  131  where the TSVs  111  and the external electrodes  131  may be vertically connected and RDL (not shown in the figures) is implemented to electrically connect to the testing electrodes  130 . Furthermore, a plurality of interconnecting electrodes  140  are disposed between the stacked gaps  120  of the substrate-less chip cubes  100  to electrically connect the TSVs  111 . The interconnecting electrodes  140  can be formed by the external electrodes  131  of the chips  110  before chip stacking or by additionally disposed components such as the combination of metal pillars and solder paste. 
         [0015]    Then, as shown in  FIG. 1C , the substrate-less chip cubes  100  are attached onto an adhesive tape  252  where the testing electrodes  130  are away from the adhesive tape  252 . The adhesive tape  252  has adhesive to adhere the substrate-less chip cubes  100 . The adhesive tape  252  is also attached inside an opening  251  of a tape carrier  250  as shown in  FIG. 1F  where normally the tape carrier  250  is strip-like metal frame. The step of disposing the adhesive tape  252  on the tape carrier  250  can be performed before or after the step of forming a filling encapsulant. In the present embodiment, the step of disposing the adhesive tape  252  disposed on the tape carrier  250  is performed after dispensing and before curing the filling encapsulant where the tape carrier  250  is implemented as a loading carrier to transfer the substrate-less chip cubes  100  into a baking oven. 
         [0016]    Then, as shown in  FIG. 1C  again, a filling encapsulant  150  is provided by a dispensing needle  240  where the filling encapsulant  150  is formed on top of the adhesive tape  252  and the filling encapsulant  150  is able to completely fill the stacked gaps  120  under appropriate temperatures with appropriate time to create capillary attraction and encapsulate the interconnecting electrodes  140  as shown in  FIG. 1D . Then, the filling encapsulant  150  is thermally cured by a baking oven. 
         [0017]    As shown from  FIG. 1D  to  FIG. 1E , in the aforementioned described step of forming the filling encapsulant  150  includes a de-bleeding step of removing a bleeding portion  151  of the filling encapsulant  150  exceeding the footprints of the substrate-less chip cubes  100  to make the substrate-less chip cubes  100  more like a cube. The aforementioned described step of removing bleeding can be performed before or after curing the filling encapsulant  150 . For example, when the de-bleeding step is performed after curing the filling encapsulant  150 , the bleeding  151  can be removed by a laser cutting tool. In the present embodiment, the aforementioned described de-bleeding step can be performed before curing the filling encapsulant  150  by exposure and development. As shown in  FIG. 1E , preferably, after the de-bleeding step, the filling encapsulant  150  still encapsulates a plurality of sidewalls  112  of the chips  110  to effectively protect the chips  110  stacked in the substrate-less chip cubes  100 . 
         [0018]    Then, as shown in  FIG. 1G , the tape carrier  250  is fixed on a wafer testing carrier  260  to allow the substrate-less chip cubes  100  without releasing from the adhesive tape  252  to be loaded into a wafer tester  270  as shown in  FIG. 1H . As shown in  FIG. 4 , the wafer testing carrier  260  can be larger than the tape carrier  250  where both can have different shapes where the wafer testing carrier  260  can carry the tape carrier  250  to form interchangeable modularized jigs. In the present embodiment, the wafer testing carrier  260  is a round disc having a ring looked like a conventional wafer frame. However, in the present embodiment, the major difference between the wafer testing carrier  260  and the conventional wafer frame is that there is no opening penetrating through the wafer testing carrier  260  and there is no dicing tape to adhere a wafer through the wafer testing carrier  260 . The shape of the tape carrier  250  can be strip-like such as substrate strips for transferring substrates. 
         [0019]    As shown in  FIG. 2A  and  FIG. 2B , in the present embodiment, the wafer testing carrier  260  may have a disc-like major body  261  made of hard materials such as copper, iron, or alloy to provide a hard placing surface  263  for carrying the tape carrier  250 . To be more specific, the wafer testing carrier  260  has a plurality of fixing kits  262  disposed on the placing surface  263  of the major body  261  to position the tape carrier  250 . As shown in  FIG. 4 , the clamps  262  can clamp a plurality of corners  253  of the tape carrier  250  where the tape carrier  250  has an adhesive tape  252  adhered the substrate-less chip cubes  100 . Therefore, the substrate-less chip cubes  100  accompanied with the tape carrier  250  can be loaded into a wafer tester  270  though the wafer testing carrier  260  without releasing from the adhesive tape  252 . 
         [0020]    As shown in  FIG. 3A  and  FIG. 3B , in a various embodiment, the major body  261  of the wafer testing carrier  260  further has a fitting window  264  sunk from the placing surface  263  with a shape matching to the shape of a tape carrier  250 . When the tape carrier  250  is installed on the placing surface  263 , the bottom portion of the tape carrier  250  is partially embedded into the fitting window  264  to achieve fixing the tape carrier  250  on the wafer testing carrier  260 . 
         [0021]    Then, as shown in  FIG. 1H , the wafer testing carrier  260  is loaded inside the wafer tester  270 , and a plurality of testing probes  271  inside the wafer tester  270  can probe on the testing electrodes  130  to electrically test the substrate-less chip cubes  100  where the testing probes  271  are installed on a probe card  275 . As shown in  FIG. 5 , the wafer tester  270  includes a loading zone  272 , a loading lock  273 , and a testing zone  274  where wafer frames can be loaded and unloaded in the loading zone  272  and then transferred to the testing zone  274  after alignment check in the loading lock  273 . The afore probe card  275  including the testing probes  271  is disposed in the testing zone  274  for electrical testing the testing electrodes  130  disposed on wafer surfaces. Since the wafer testing carrier  260  can meet the dimension of wafer frames and can directly be loaded into the loading lock  273  so that the testing probes  271  inside the testing zone  274  can probe the testing electrodes  130  of the substrate-less chip cubes  100  without releasing from the adhesive tape  252 , without another transferring the substrate-less chip cubes  100  to another adhesive tape  252  and without changing the tape carrier  250  to reduce the testing cost, to increase the testing efficiency of wafer-level testing of multi-chip packages, and to meet the requirement of fine-pitch probing so that the substrate-less chip cubes  100  can be tested without disposed on an interposer with fan-out circuitry and fan-out electrodes to confirm the electrical connection between the stacked chips  110 , i.e., the electrical connection between interconnecting electrodes  140 . Furthermore, the method for testing multi-chip stacked packages of the present invention allows directly sorting the substrate-less chip cubes  100  inside the wafer tester  270  to sort out or remove bad substrate-less chip cube  100 . 
         [0022]    As shown in  FIG. 1I , after testing, the method for testing multi-chip stacked packages further comprises the step of releasing the tape carrier  250  from the wafer testing carrier  260  so that the wafer testing carrier  260  can be recycled. Moreover, the following steps may comprise marking, packing, and so on. 
         [0023]    Therefore, the method for testing multi-chip stacked packages of the present invention can be implemented in the existing wafer tester to achieve probing of fine-pitch electrodes of the substrate-less chip cubes  100  without an interposer to provide good substrate-less chip cubes  100  and to sort out good and bad substrate-less chip cubes  100  to reduce the number of adhering processes of the adhesive tape to achieve lower packaging cost and to prevent SMT bad substrate-less chip cube on boards. 
         [0024]    The above description of embodiments of this invention is intended to be illustrative but not limited. Other embodiments of this invention will be obvious to those skilled in the art in view of the above disclosure which still will be covered by and within the scope of the present invention even with any modifications, equivalent variations, and adaptations.