Abstract:
A semiconductor die and method of making it are provided. The die includes a first via extending through the entire thickness of the die and a first via electrode disposed inside the via electrically connecting an electrode at a top surface of the die with another electrode disposed at a bottom surface of the die.

Description:
RELATED APPLICATIONS  
       [0001]     The present application claims priority from U.S. Provisional Application 60/719,617, filed on Sep. 22, 2005, the disclosure of which is incorporated in full by reference herein. 
     
    
     FIELD OF THE INVENTION  
       [0002]     This invention relates to semiconductor devices, and more specifically, to a flip chip type power semiconductor device.  
       BACKGROUND AND SUMMARY OF THE INVENTION  
       [0003]     It is well known that the electrodes of a flip chip device are disposed on the same surface of the die so that the device can be soldered or otherwise conductively connected to pads on a support surface such as a printed circuit board. U.S. Pat. No. 6,653,740, issued Nov. 25, 2003 and assigned to the assignee of the present application, discloses a vertical conduction flip chip MOSFET with a drain electrode on the top of the die connected to the drift region through a trench filled with a conductive material. The device disclosed in U.S. Pat. No. 6,653,740, is formed in a epitaxial silicon that is disposed on a float zone type substrate. Such a device is typically about 500 μm thick.  
         [0004]     In the recent years, vertical conduction (power electrodes on opposite sides of the die) power semiconductor devices being less than 200 microns thick (otherwise referred to as thin die) have gained popularity due to their cost advantage and low resistivity, among other characteristics.  
         [0005]     It is desirable to have a thin power semiconductor device having all electrodes on the same surface.  
       SUMMARY OF THE INVENTION  
       [0006]     A semiconductor die according to the present invention includes is a vertical conduction power semiconductor device having a first via extending through an entire thickness of the semiconductor body thereof and a first via electrode disposed inside the via electrically connecting a power electrode at a top surface of the die with another power electrode disposed at a bottom, opposite surface of the die.  
         [0007]     According to an aspect of the present invention, the die is a vertical conduction flip chip MOSFET that is less than 200 micrometers thick.  
         [0008]     In another embodiment, an oxide material, a nitride material or a copper material may be disposed inside the via such that, the via electrode is closer to a side wall of the via than the at least one material.  
         [0009]     A process for fabricating a flip chip device according to the present invention includes depositing on a die a mask to define an area for a trench; etching the die to a depth less than the entire thickness of the die to form a trench; adding a metal via electrode into the entire depth of the trench; grinding the die to a final thickness to expose the trench at the bottom surface of the die in order to form a via; forming a power electrode electrically connected to the metal via electrode, and forming a back metal on the bottom surface of the die electrically connected to the metal via electrode. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]      FIG. 1  shows a top plan view of a flip chip die made in accordance with the invention, showing drain, gate and source pads all on the same surface.  
         [0011]      FIG. 2  shows a cross-sectional view of a device according to the first embodiment of the present invention viewed along line  2 - 2  in  FIG. 1  in the direction of the arrows.  
         [0012]      FIG. 3  shows a portion of a die in cross-section, after an initial process step in which a trench is etched into the die.  
         [0013]      FIG. 4  shows the structure of  FIG. 3  after the trench is filled with front metal, or copper plating.  
         [0014]      FIG. 5  shows the structure of  FIG. 3  after the die is ground to its final thickness.  
         [0015]      FIGS. 6 and 7  show the detail of the drain via process before and after respectively the back grind, and show the added use of an oxide, nitride or copper plating plug in the center of the via according to the second embodiment of the present invention.  
         [0016]      FIG. 8  shows a portion of a device according to the present invention after the application of a solder resist passivation. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0017]     Aspects of the invention and the process for making the same will now be described with reference to  FIGS. 1-8 .  
         [0018]      FIG. 1  illustrates a top plan view of a die  10  configured as a flip chip in accordance with the present invention, including source pads  20 , gate pad  23 , gate bus  25  and drain pad  30  including a plurality of vias  31 - 35 . Note that a semiconductor device according to the present invention is a vertical conduction device (i.e. a device in which the current includes a vertical path from the top to the bottom such as a device illustrated by U.S. Pat. No. 6,653,740 the disclosure of which is incorporated by reference), which has been adapted for flip-chip mounting so that it may take advantage of the efficient arrangement and high current capability of a vertical conduction device, and the advantages of a flip chip mountable power semiconductor device.  
         [0019]     Referring to  FIG. 2 , a semiconductor device according to the present invention is a power MOSFET which includes a via  12  (preferably a plurality of vias) with a via electrode  18  disposed therein. Via electrode  18  electrically connects back drain electrode  45  formed on a bottom surface  15  of semiconductor body  11  to front drain electrode  42 . In the preferred embodiment, via electrode  18  is electrically connected to semiconductor body  11 . Note that according to an aspect of the present invention, via  12  is formed outside the termination region (i.e. is inside the street region) in order to prevent shorting between the source and the drain.  
         [0020]     A process for manufacturing a device according to the present invention will now be described with reference to  FIGS. 3-5 . It will be noted that the processing steps described refer to the die  10 ; however, it will be understood that typically a wafer (not shown) comprising more than one such die will be manufactured at the same time using similar processing steps.  
         [0021]     Referring to  FIG. 3 , a trench  12 ′ is etched into a die  10  using preferably a photo resist mask  41  that defines the area to be etched.  
         [0022]     Referring to  FIG. 4 , trench  12 ′ is filled with metal or copper is plated on the walls and preferably the bottom of trench  12 ′ to define via electrode  18  inside trench  12 ′ and preferably at the same time drain electrode  30  on the top surface of body  11 . It should be understood that via electrode  18  need not be made of the same material as drain electrode  30  formed at the top surface of die  10 .  
         [0023]     Referring next to  FIG. 5 , according to one aspect of the present invention, in a grinding step, semiconductor body  11  is ground from the back until at least the bottom of trench  12 ′ is reached, whereby trench  12 ′ is transformed into via  12 . Note that to form a thin power semiconductor die semiconductor body  11  is ground to a thickness of at least less than 200 μm, preferably to 75 μm and most preferably to a thickness of 50 μm or less when possible. After grinding, back metal is deposited on back surface  15  of body  11  by sputtering or the like to form back drain electrode  45 . Back drain electrode  45  can help render structural rigidity to the thin die, improve heat dissipation from the back of the die, and allow access for electrical connection to the back of the die.  
         [0024]     Referring to  FIGS. 6 and 7 , in an alternative embodiment the sidewalls of trench  12 ′ are plated leaving trench  12 ′ otherwise void, and a dielectric material, such as an oxide or nitride, is then deposited inside trench  12 ′ next to via electrode  18  which is lining the sidewall and preferably the bottom of trench  12 ′ to form plug  13 . Thereafter, body  11  is ground as described earlier.  FIG. 7  shows trench  12 ′ after the grinding step to expose the bottom of trench  12 A at the bottom surface  15  of die  10  and form a via  12  according to the present invention. Next, back drain electrode  45  is formed as described earlier. Plug  13  may advantageously protect via electrode  18  to provide resistance to wear or may serve as an insulation material.  
         [0025]     Alternatively, plug  13  may be formed with a conductive material such as copper. It is to be understood that when a copper plating material is used to form plug  13 , it will augment the conductivity of via electrode  18 .  
         [0026]     Referring now to  FIG. 8 , a passivation body  47  may be applied at least to the front face of the device. Passivation body may include openings therein to allow access to drain electrode  30 , source electrodes  20 , and gate electrode  23 , but may function as a solder resist in order to prevent the encroachment of solder from one electrode to another during solder reflow. A suitable material for passivation body  47  may be solder resist epoxy or the like polymer.  
         [0027]     Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein.