Abstract:
A bias circuit for an operating transistor has a first resistor disposed in a path for supplying a bias current to a base of the operating transistor, a first transistor for applying the bias current flowing to the first resistor, a second transistor for applying a corresponding current corresponding to the bias current supplied via at least one current mirror circuit, a third transistor having bases connected in common with the first transistor for applying the corresponding current, a second resistor for applying the corresponding current and obtaining a voltage drop corresponding to a voltage drop at the first resistor, and a fourth transistor receiving a reference voltage at an emitter side and having a base connected to an emitter side of the third transistor.

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
       [0001]    The entire disclosure of Japanese Patent Application No. 2011-140161 filed on Jun. 24, 2011, including specification, claims, drawings, and abstract, is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    The present invention relates to a bias circuit for supplying a bias current to a base of an operating transistor. 
         [0004]    2. Background Art 
         [0005]    Heretofore, a differential amplifier or the like has a pair of differential transistors Q 51  and Q 52  with emitters connected in common as shown in  FIG. 4  and connected to a constant current circuit. Then, the differential transistors Q 51  and Q 52  input a signal and are supplied with bias currents from a bias circuit to enable an operation in accordance with the input signal. 
         [0006]      FIG. 4  includes a power supply V 51  and resistors R 51  and R 52 , where an output voltage of the power supply V 51  is supplied as a bias voltage via the resistors R 51  and R 52  to bases of the differential transistors Q 51  and Q 52 . 
         [0007]    However, bipolar transistors have temperature dependent parameters, such as base-emitter voltage VBE and DC current gain h FE . Therefore, when the bias circuit shown in  FIG. 4  is used, the emitter voltages of the differential transistors Q 51  and Q 52  are temperature dependent.
   Patent Document 1: Japanese Patent Laid-Open Publication No. Hei 8-340224   
 
         [0009]    When operating an application with a relatively narrow dynamic range (D-range) over a wide temperature range, such as a mixer circuit or a circuit where low voltage operation is required, it is necessary to ensure dynamic range with temperature-independent operating points (emitter, collector voltages). 
       SUMMARY OF THE INVENTION 
       [0010]    According to one or more embodiments of the present invention, a bias circuit for an operating transistor includes a first resistor arranged in a path for supplying a bias current to a base of the operating transistor, a first transistor for applying the bias current flowing to the first resistor, a second transistor for applying a corresponding current corresponding to the bias current via at least one current mirror circuit, a third transistor having bases connected in common with the first transistor for applying the corresponding current, a second resistor for applying the corresponding current and obtaining a voltage drop corresponding to a voltage drop at the first resistor, and a fourth transistor receiving a reference voltage at an emitter side and having a base connected to an emitter side of the third transistor, wherein 1VBE of the operating transistor is canceled by 1VBE of the fourth transistor and 1VBE of the second transistor is canceled by 1VBE of the third transistor thereby setting the reference voltage to an emitter side of the operating transistor. 
         [0011]    According to one or more embodiments of the present invention, the first resistor is arranged between an emitter of the first transistor and the base of the operating transistor and arrange the second resistor between the emitter of the third transistor and the base of the fourth transistor. 
         [0012]    According to one or more embodiments of the present invention, setting the emitter voltage of the operating transistor to a reference voltage enables the temperature dependence of the emitter voltage to be suppressed. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]      FIG. 1  shows a configuration of a bias circuit of an according to one or more embodiments of the present invention. 
           [0014]      FIG. 2  shows a temperature characteristic of the bias circuit. 
           [0015]      FIG. 3  shows a configuration of a bias circuit according to one or more embodiments of the present invention. 
           [0016]      FIG. 4  shows a configuration of a conventional bias circuit. 
       
    
    
     DETAILED DESCRIPTION 
       [0017]    Embodiments of the present invention will be described hereinafter with reference to the attached drawings. In embodiments of the invention, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to one of ordinary skill in the art that the invention may be practiced without these specific details. In other instances, well-known features have not been described in detail to avoid obscuring the invention. 
         [0018]      FIG. 1  shows a circuit configuration including a bias circuit according to one or more embodiments of the present invention. 
         [0019]    NPN-type differential transistors Q 8  and Q 9  have emitters connected in common and connected to ground via a constant current circuit CC 2 . Here, Ve is the emitter voltage of the differential transistors Q 8  and Q 9 . The differential transistors Q 8  and Q 9  are part of a differential amplifier and to bases of the differential transistors Q 8  and Q 9  are supplied a signal Vin_P and a signal Vin_N, which are a pair of complementary signals. Then, to the bases of the differential transistors Q 8  and Q 9  are supplied bias currents respectively via resistors R 3  and R 4 . 
         [0020]    A current value Ib, which is the sum of the currents flowing to the resistors R 3  and R 4 , is a base current (bias current) of the differential transistors Q 8  and Q 9  when the signals Vin_P and Vin_N are absent. The current value Ib is basically determined by the resistance values R 3  and R 4  and set to an appropriate value (suitable bias current value for the differential amplifier) as required by the differential transistors Q 8  and Q 9 . 
         [0021]    The lower terminals of the resistors R 3  and R 4  are respectively connected to the differential transistors Q 8  and Q 9  and the upper terminals thereof are connected to a power supply VCC via transistors Q 7  and Q 6 . Namely, an emitter of the PNP transistor Q 6  is connected to VCC, a collector is connected to a collector of the NPN transistor Q 7 , and an emitter of the transistor Q 7  is connected to the upper terminals of the resistors R 3  and R 4 . 
         [0022]    The transistor Q 6  is shorted between the collector and base and to the base is connected a base of a PNP transistor Q 5 , which has an emitter connected to VCC. Therefore, the transistor Q 6  and the transistor Q 5  form a current mirror so that a current in accordance with (for example, identical to) the current flowing to the transistor Q 6  flows to the transistor Q 5 . 
         [0023]    To a collector of the transistor Q 5  is connected a collector of an NPN transistor Q 4 , which has an emitter connected to ground. The transistor Q 4  is shorted between the collector and base and to the base of the transistor Q 4  is connected a base of an NPN transistor Q 3 , which has an emitter connected to ground. Therefore, the transistor Q 4  and the transistor Q 3  form a current mirror. The current flowing to the transistor Q 5  flows to the transistor Q 4  and a current Ib′ in accordance with the current flowing to the transistor Q 4  also flows to the transistor Q 3 . For example, if the emitter area of the transistor Q 3  is N times that of the transistor Q 4 , the result is Ib′=N·Ib so that a current that is N times that of Ib flows to the transistor Q 3 . 
         [0024]    A collector of the transistor Q 3  is connected to an emitter of an NPN transistor Q 2  via a resistor R 2  and a collector of the NPN transistor Q 2  is connected to VCC. Therefore, the same current as that to the transistor Q 3  flows to the transistor Q 2  and the resistor R 2 . 
         [0025]    Furthermore, a collector of an NPN transistor Q 1  is connected to the power supply VCC via a constant current circuit CC 1  and an emitter of the transistor Q 1  is connected to ground via a resistor R 1 . 
         [0026]    Then, to a connection point between a collector of the transistor Q 1  and the constant current circuit CC 1  is connected bases of the transistor Q 2  and the transistor Q 7  and a base of the transistor Q 1  is connected to a connection point between the resistor R 2  and the collector of the transistor Q 3 . 
         [0027]    Therefore, a constant current flowing to the constant current circuit CC 1  flows to the resistor R 1  and the upper side voltage of the resistor R 1  is determined by a reference voltage Vref, which becomes the emitter voltage of the transistor Q 1 . As a result, the lower side voltage of the resistor R 2  becomes the reference voltage Vref increased by 1VBE of the transistor Q 1 , or voltage Vref+1VBE. If the current flowing to the resistor R 2  is Ib′, the upper side voltage of the resistor R 2  becomes Vref+1VBE+Ib′·R 2 . Then, the voltage Vref+1VBE+Ib′·R 2  becomes the emitter side voltage of the transistor Q 2  and the transistor Q 7  and the emitter of the transistor Q 7  is connected via the resistors R 3  and R 4  to the bases of the differential transistors Q 8  and Q 9  so that the voltage of the emitter of the differential transistors Q 8  and Q 9  is the voltage Vref+1VBE+Ib′·R 2  minus the voltage drop of the resistor R 3  or R 4  decreased by 1VBE. 
         [0028]    If the voltage drop at the resistor R 2  and the respective voltage drops at the resistors R 3  and R 4  are equal, the 1VBE at the differential transistors Q 8  and Q 9  is compensated by 1VBE of the transistor Q 1  so that the emitter voltage Ve of the differential transistors Q 8  and Q 9  becomes the reference voltage Vref, which is temperature independent. 
         [0029]    Namely, in the circuit of  FIG. 1 , the current Ib flowing to the transistor Q 7  is transmitted by the current mirror circuit so that the current Ib′ corresponding to Ib flows to the transistor Q 2 . Then, the voltage drop portion generated at the resistors R 3  and R 4  is canceled by the resistor R 2 . Therefore, if the VBE of the transistors Q 1 , Q 2 , Q 7 , Q 8 , and Q 9  are equal, Vref=Ve results and the emitter voltage Ve of the differential transistors Q 8  and Q 9  can be made temperature independent. It should be noted Vref is easily made temperature independent by using, for example, a bandgap circuit. 
         [0030]    Here, a relationship of the resistors R 2 , R 3 , R 4  and Ib and Ib′ is shown next. Here, N indicates a current ratio of Ib and Ib′. 
         [0000]    
       
         
           
             
               
                 
                   Expression 
                    
                   
                       
                   
                    
                   1 
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   
                     
                       
                         
                           R 
                            
                           
                               
                           
                            
                           
                             3 
                             · 
                             R 
                           
                            
                           
                               
                           
                            
                           4 
                         
                         
                           
                             R 
                              
                             
                                 
                             
                              
                             3 
                           
                           + 
                           
                             R 
                              
                             
                                 
                             
                              
                             4 
                           
                         
                       
                       · 
                       Ib 
                     
                     = 
                     
                       R 
                        
                       
                           
                       
                        
                       
                         2 
                         · 
                         
                           Ib 
                           ′ 
                         
                       
                     
                   
                   , 
                   
                     
                       N 
                       · 
                       Ib 
                     
                     = 
                     
                       Ib 
                       ′ 
                     
                   
                 
               
               
                 
                   ( 
                   
                     2 
                      
                     
                       - 
                     
                      
                     1 
                   
                   ) 
                 
               
             
           
         
       
     
         [0031]    Expression 2-1 can be arranged to yield expression 2-2. The expression indicates that R 2  can be arbitrarily selected depending on the base bias resistors R 3  and R 4  and the current ratio N. 
         [0000]    
       
         
           
             
               
                 
                   Expression 
                    
                   
                       
                   
                    
                   2 
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   
                     R 
                      
                     
                         
                     
                      
                     2 
                   
                   = 
                   
                     
                       R 
                        
                       
                           
                       
                        
                       
                         3 
                         · 
                         R 
                       
                        
                       
                           
                       
                        
                       4 
                     
                     
                       N 
                       · 
                       
                         ( 
                         
                           
                             R 
                              
                             
                                 
                             
                              
                             3 
                           
                           + 
                           
                             R 
                              
                             
                                 
                             
                              
                             4 
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     2 
                      
                     
                       - 
                     
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                     2 
                   
                   ) 
                 
               
             
           
         
       
     
         [0032]    Here, the operation was confirmed by simulation regarding the bias circuit shown in  FIG. 1 . The simulation employs a commercially available simulation program using Abic, which is a time-series analysis program, and the parameters in expression 2-2 were respectively set as N=1, R 2 =10 kΩ, R 3 =20 kΩ, and R 4 =20 kΩ. 
         [0033]      FIG. 2  shows a simulation result at a temperature range of −50° C. to 150° C. The dotted line shown in the figure is the emitter voltage Ve of the differential transistor when a bias circuit of the prior art shown in  FIG. 4  is used. In this manner, the emitter voltage Ve (b) fluctuates approximately 486 mV. On the other hand, the emitter voltage Ve (a) of the differential transistor when the bias circuit according to one or more embodiments of the present invention is used is shown as a solid line. In this case, the fluctuation is approximately 13 mV showing that the fluctuation is reduced considerably. 
         [0034]      FIG. 3  shows an example modified circuit. The circuit of  FIG. 3  is operational even when the power supply VCC is a lower voltage. Namely, by configuring the collector side of the transistor Q 7  as a loopback current mirror circuit, the circuit is characterized by enabling operation at a lower voltage than the circuit shown in  FIG. 1 . 
         [0035]    The collector of the transistor Q 7  is connected to VCC via a resistor R 7 . Then, an emitter of a PNP transistor Q 13  is connected to a connection point between the collector of the transistor Q 7  and the resistor R 7  and a collector of an NPN transistor Q 15 , which has an emitter connected to ground, is connected to a collector of the transistor Q 13 . The transistor Q 15  is shorted between the collector and a base and to the base is connected a base of an NPN transistor Q 14 , which has an emitter connected to ground. Therefore, the transistors Q 15  and Q 14  form a current mirror. Then, a collector of the transistor Q 14  is connected to the collector of the transistor Q 4 . 
         [0036]    To the collector of the transistor Q 4  is connected a collector of a PNP transistor Q 10  and an emitter of the transistor Q 10  is connected to VCC via the resistor R 5 . 
         [0037]    Furthermore, to the power supply VCC is connected an emitter of a PNP transistor Q 11  via a resistor R 6  and a collector of the transistor Q 11  is connected to ground via a constant current circuit CC 3 , which applies a constant current Iref. The transistor Q 11  is shorted between the collector and a base and the base is connected to a base of the transistor Q 10 . Furthermore, to the base of the transistor Q 11  is also connected in common a base of the transistor Q 13 . 
         [0038]    In this circuit, a voltage V R7  across the terminals of the resistor R 7  is derived from the following expression. Namely, since the constant current Iref, which flows to the constant current circuit CC 3 , flows to the resistor R 6 , the voltage drop V R7  at the resistor R 7  becomes a voltage where the voltage drop Iref·R 6  of the resistor R 6  is subtracted from VCC, a base emitter voltage VBE 11  of the transistor Q 11  is further subtracted, and a base emitter voltage VBE 13  of the transistor Q 13  is added. The current flowing to the transistor Q 13  is set as Ifc. Furthermore, Is is the saturation current and V T  is the thermal voltage. 
         [0000]    
       
         
           
             
               
                 
                   Expression 
                    
                   
                       
                   
                    
                   3 
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   
                     
                       
                         
                           V 
                           
                             R 
                              
                             
                                 
                             
                              
                             7 
                           
                         
                         = 
                           
                          
                         
                           Vcc 
                           - 
                           
                             ( 
                             
                               Vcc 
                               - 
                               
                                 
                                   Iref 
                                   · 
                                   R 
                                 
                                  
                                 
                                     
                                 
                                  
                                 6 
                               
                               - 
                               
                                 V 
                                 
                                   BE 
                                    
                                   
                                       
                                   
                                    
                                   11 
                                 
                               
                               + 
                               
                                 V 
                                 
                                   BE 
                                    
                                   
                                       
                                   
                                    
                                   13 
                                 
                               
                             
                             ) 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                          
                         
                           
                             
                               Iref 
                               · 
                               R 
                             
                              
                             
                                 
                             
                              
                             6 
                           
                           + 
                           
                             
                               V 
                               T 
                             
                             · 
                             
                               ln 
                                
                               
                                 ( 
                                 
                                   Iref 
                                   / 
                                   
                                     ( 
                                     Is 
                                     ) 
                                   
                                 
                                 ) 
                               
                             
                           
                           - 
                           
                             
                               V 
                               T 
                             
                             · 
                             
                               ln 
                                
                               
                                 ( 
                                 
                                   Ifc 
                                   / 
                                   
                                     ( 
                                     Is 
                                     ) 
                                   
                                 
                                 ) 
                               
                             
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                          
                         
                           
                             
                               Iref 
                               · 
                               R 
                             
                              
                             
                                 
                             
                              
                             6 
                           
                           + 
                           
                             
                               V 
                               T 
                             
                             · 
                             
                               ln 
                                
                               
                                 ( 
                                 
                                   Iref 
                                   / 
                                   Ifc 
                                 
                                 ) 
                               
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     3 
                      
                     
                       - 
                     
                      
                     1 
                   
                   ) 
                 
               
             
           
         
       
     
         [0039]    Furthermore, with current I R7  flowing to the resistor R 7 , Ib′ is derived from the following expression. Here, the current ratio of transistors Q 3 :Q 4  is N (the current flowing to the transistor Q 3  is N times the current flowing to the transistor Q 4 ). 
         [0000]    
       
         
           
             
               
                 
                   Expression 
                    
                   
                       
                   
                    
                   4 
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   
                     
                       Ifc 
                       + 
                       Ib 
                     
                     = 
                     
                       
                         I 
                         
                           R 
                            
                           
                               
                           
                            
                           7 
                         
                       
                       = 
                       
                         
                           
                             V 
                             
                               R 
                                
                               
                                   
                               
                                
                               7 
                             
                           
                           
                             R 
                              
                             
                                 
                             
                              
                             7 
                           
                         
                         = 
                         
                           
                             
                               
                                 R 
                                  
                                 
                                     
                                 
                                  
                                 6 
                               
                               
                                 R 
                                  
                                 
                                     
                                 
                                  
                                 7 
                               
                             
                              
                             Iref 
                           
                           + 
                           
                             
                               V 
                               T 
                             
                             · 
                             
                               
                                 ln 
                                  
                                 
                                   ( 
                                   
                                     Iref 
                                     / 
                                     Ifc 
                                   
                                   ) 
                                 
                               
                               
                                 R 
                                  
                                 
                                     
                                 
                                  
                                 7 
                               
                             
                           
                         
                       
                     
                   
                    
                   
                     
 
                   
                    
                   
                     Ifc 
                     = 
                     
                       
                         
                           
                             R 
                              
                             
                                 
                             
                              
                             6 
                           
                           
                             R 
                              
                             
                                 
                             
                              
                             7 
                           
                         
                          
                         Iref 
                       
                       + 
                       
                         
                           V 
                           T 
                         
                         · 
                         
                           
                             ln 
                              
                             
                               ( 
                               
                                 Iref 
                                 / 
                                 Ifc 
                               
                               ) 
                             
                           
                           
                             R 
                              
                             
                                 
                             
                              
                             7 
                           
                         
                       
                       - 
                       Ib 
                     
                   
                    
                   
                     
 
                   
                    
                   
                     
                       Ib 
                       ′ 
                     
                     = 
                     
                       N 
                        
                       
                         ( 
                         
                           Iref 
                           - 
                           
                             ( 
                             
                               
                                 
                                   
                                     R 
                                      
                                     
                                         
                                     
                                      
                                     6 
                                   
                                   
                                     R 
                                      
                                     
                                         
                                     
                                      
                                     7 
                                   
                                 
                                  
                                 Iref 
                               
                               + 
                               
                                 
                                   V 
                                   T 
                                 
                                 · 
                                 
                                   
                                     ln 
                                      
                                     
                                       ( 
                                       
                                         Iref 
                                         / 
                                         Ifc 
                                       
                                       ) 
                                     
                                   
                                   
                                     R 
                                      
                                     
                                         
                                     
                                      
                                     7 
                                   
                                 
                               
                               - 
                               Ib 
                             
                             ) 
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     3 
                      
                     
                       - 
                     
                      
                     2 
                   
                   ) 
                 
               
             
           
         
       
     
         [0040]    Here, setting R 6 =R 7  and Iref/Ifc≈1, Ib′ is expressed as follows. 
         [0000]      Expression 5 
         [0000]        Ib′=N·Ib   (3-3)
 
         [0041]    In this manner, expression 3-3 is the same as expression 2-1 showing that the same operation as that of the bias circuit shown in  FIG. 1  can also be obtained from the bias circuit shown in  FIG. 3 . 
         [0042]    According to the circuit of  FIG. 3 , only one transistor, transistor Q 7 , is found between the transistors Q 8  and Q 9  and the power supply VCC. Therefore, operation becomes possible even when the power supply VCC becomes a low voltage. 
         [0043]    Although a PNP transistor, which has a collector connected to the power supply VCC, is used here in the constant current circuit CC 1 , the voltage drop at the PNP transistor is the emitter-collector voltage and this voltage drop can be decreased considerably. Then, the voltage at the base of the transistor Q 7 , lowered by an amount of 1VBE of the transistor Q 7  can be set to the upper voltage of the resistors R 3  and R 4  to enable the circuit to be operational even when the voltage of the power supply VCC drops. 
         [0044]    In this manner, according to the bias circuit according to one or more embodiments of the present invention, the temperature dependency of the emitter voltage of the differential transistors Q 8  and Q 9  can be suppressed to a low level. As an example, the capability of limiting the emitter voltage to a fluctuation of 13 mV or less across a temperature range of −50° C. to 150° C. was demonstrated. Therefore, in a mixer or a circuit where low voltage operation is required, it becomes possible to ensure dynamic range with temperature-independent operating points and operation across a wide temperature range. 
         [0045]    Furthermore, by adopting the configuration of  FIG. 3 , the circuit also becomes suitable for instances where low voltage operation is required. 
         [0046]    While embodiments of the present invention are described, it will be understood that various modifications may be made thereto, and it is intended that the appended claims cover all such modifications as fall within the true spirit and scope of the invention. 
         [0047]    While the invention has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be devised which do not depart from the scope of the invention as disclosed herein. Accordingly, the scope of the invention should be limited only by the attached claims.