Abstract:
A dual-polycide semiconductor structure and method for forming the same having reduced dopant cross-diffusion. A conductive layer is formed over a polysilicon layer having a first region doped with a first dopant and a second region adjoining the first region at an interface doped with a second dopant. A region of discontinuity is then formed in the conductive layer located away from the interface. The conductive layer formed over the polysilicon gate overlaps the interface to provide electrical continuity between the first and second regions of the polysilicon gate, but also includes a region of discontinuity to reduce dopant cross-diffusion.

Description:
TECHNICAL FIELD  
         [0001]    The present invention relates generally to integrated circuits, and more specifically, to a structure and a method for forming a dual-polycide semiconductor structure in an integrated circuit.  
         BACKGROUND OF THE INVENTION  
         [0002]    It is generally accepted that it is desirable to have integrated circuits that are smaller and more power efficient. This is true with respect to many semiconductor devices. For example, with memory devices, having smaller memory cell sizes allows for greater memory density, and consequently, storage of more data in a similar sized device. Similarly, microprocessors having greater transistor density, that is, a smaller transistor feature size, generally have more computing power available. Thus, because of the advantages provided by smaller semiconductor devices, a significant amount of resources have been directed to developing fabrication methods, semiconductor structures, and fabrication and processing equipment to construct smaller devices.  
           [0003]    In an effort to minimize the size of a semiconductor structure and reduce the number of processing steps, such as in a static random access memory (SRAM) cell, dual-polycide gate structures having a first portion doped with n-type impurities and second portion doped with p-type impurities are used for the gates of the transistors of the memory cells. Dual-polycide gate structures enable the gates of a CMOS inverter to be formed without performing the processing steps typically required in forming each of the gates of the NMOS and PMOS transistors separately. Moreover, using one polycide structure to form the gates for both the NMOS and PMOS transistors of a CMOS inverter requires less space than having two physically separate gates.  
           [0004]    A schematic drawing of a conventional 6T SRAM cell is provided in FIG. 1 a,  and an example of a mask layout for the 6T SRAM cell is provided in FIG. 1 b.  As the cross-sectional view of FIG. 1 c  illustrates, a dual-polycide gate  100  includes a polysilicon layer  110  having a first region  112  doped with n-type impurities and a second region  114  doped with p-type impurities. The gate  100  further includes a silicide strap layer  116 , typically formed from tungsten silicide, that provides a relatively low resistance current path between the first region  112  and the second region  114 . Without the silicide strap layer  116 , the junction between the first and second regions  112  and  114  would behave like a pn-diode, which would be unacceptable in the present application.  
           [0005]    A problem, however, with using dual-polycide gate structures, such as the one illustrated in FIG. 1 c,  is cross-diffusion of dopants between the first and second regions  112  and  114  through the silicide strap layer  116 . It is well known that certain dopants, such as Arsenic, move relatively easily in silicides, such as tungsten silicide. For example, arsenic from the n-poly of the first region  112  migrates into the silicide strap layer  116  and cross-diffuses into the p-poly of the second region  114 . Cross-diffusion causes polysilicon depletion, that is, the polysilicon no longer behaves like metal electrodes. This consequently leads to adverse effects such as gate threshold voltage shift and lower drive capability.  
           [0006]    One approach that has been taken to address the issues of cross-diffusion in a polycide gate has been to form separate gates for the different transistors. Physically separating the gates of the different transistors assures that cross-diffusion of dopants cannot take place. This approach typically requires that separate contacts are formed to electrically connect to each of the gates. However, as previously mentioned, increasing the memory cell size to accommodate the additional contacts is typically undesirable, and in some instances, the memory cell design rule limits may not allow for the use of separate contacts. Therefore, there is a need for a dual-polycide semiconductor structure and a method that reduces cross-diffusion of dopants across the dopant boundary.  
         SUMMARY OF THE INVENTION  
         [0007]    Embodiments of the present invention are directed to a dual-polycide semiconductor structure and method for forming the same having reduced dopant cross-diffusion. In a semiconductor structure that includes a polysilicon layer having a first region that is doped with a first dopant and a second region adjoining the first region at an interface that is doped with a second dopant, embodiments of the present invention include forming a conductive layer over the polysilicon layer that overlaps the interface, and then removing a portion of the conductive layer to form a region of discontinuity located at a minimum distance away from the interface. Thus, the conductive layer formed over the polysilicon gate overlaps the interface to provide a low resistance current path between the first and second regions of the polysilicon gate, but also includes a region of discontinuity to reduce dopant cross-diffusion from one region to the other. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]    [0008]FIGS. 1 a - 1   c  are schematic drawings of a conventional SRAM cell, a layout view, and a cross-sectional view of the conventional SRAM cell.  
         [0009]    [0009]FIGS. 2 a - 2   c  are cross-sectional drawings of a SRAM cell including embodiments of the present invention, and a corresponding layout drawing.  
         [0010]    [0010]FIGS. 3 a - 3   c  are cross-sectional drawings and a corresponding layout drawing of the SRAM cell of FIGS. 2 a - 2   c  during the processing thereof.  
         [0011]    [0011]FIGS. 4 a  and  4   b  are cross-sectional drawings of the SRAM cell of FIGS. 2 a  and  2   b  during the processing thereof.  
         [0012]    [0012]FIGS. 5 a - 5   c  are cross-sectional drawings and a corresponding layout drawing of the SRAM cell of FIGS. 2 a - 2   c  during the processing thereof.  
         [0013]    [0013]FIGS. 6 a  and  6   b  are cross-sectional drawings of the SRAM cell of FIGS. 2 a  and  2   b  during the processing thereof.  
         [0014]    [0014]FIG. 7 is a block diagram of a typical memory device that includes one or more dual-polycide structures according to an embodiment of the present invention.  
         [0015]    [0015]FIG. 8 is a functional block diagram of a computer system including a memory device having one or more dual-polycide structures according to an embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0016]    [0016]FIG. 2 illustrates an embodiment of the present invention as applied to an SRAM cell  200 . Specifically, FIG. 2 c  illustrates a SRAM cell layout incorporating strap layer cuts  222  and  224  that reduce dopant cross-diffusion in dual-polycide structures. With respect to the SRAM cell  200 , the dual-polycide structures represent the gates  202  and  204  of the cross-coupled CMOS inverters. FIGS. 2 a  and  2   b  illustrate cross-sectional views of the SRAM cell  200  at the locations indicated in FIG. 2 c.  A more detailed explanation of the formation of the dual-polycide structures of the SRAM cell  200  will be provided below with respect to FIGS.  3 - 6 . It will be appreciated that the lateral sizes and thickness of the various layers illustrated in the accompanying figures are not drawn to scale and these various layers or layer portions may have been enlarged or reduced to improve drawing legibility. It will be further appreciated that in the following description, many of the processing steps discussed are understood by those of ordinary skill in the art, and detailed descriptions thereof have been omitted for the purposes of unnecessarily obscuring the present invention.  
         [0017]    [0017]FIGS. 3 a  and  3   b  illustrate cross-sectional views, and FIG. 3 c  the corresponding layout, of the SRAM cell  200  following the formation of the dual-polycide gates  202  and  204 . As shown in FIG. 3 c,  conventional active regions  210  and  212  are formed prior to the formation of the gates  202  and  204  in the SRAM cell  200 . Additionally, a conventional n-well region  220  is formed prior to the gates  202  and  204  as well. It will be appreciated that the formation of the active regions  210  and  212 , the n-well region  220 , as well as other structures, such as oxide isolation regions, contact regions, and doped regions, are understood in the art and do not need to be described in greater detail herein in order to practice the invention.  
         [0018]    The structure following a gate etch is illustrated in FIGS. 3 a  and  3   b.  FIG. 3 a  and  3   b  show in greater detail the structure of the dual-polycide gates  202  and  204 . Each of the gates includes a polysilicon layer  203  and a tungsten silicide (WSi) layer  302  used as a strap layer. A tetraethyl orthosilicate (TEOS) glass layer  304  is formed over the WSi layer  302  as a cap layer for the gates  202  and  204 . Note that the dual doping of the polysilcon layer  203  for the gate  202  is apparent in FIG. 3 b.  Each of the gates  202  and  204  have a p-poly portion  203   a  that overlies the n-well region  220  and which is doped with a p-type dopant. The p-poly portions represent the gates for the p-channel pull-up transistors M 1  or M 3 . The gates  202  and  204  further have an n-poly portion  203   b  that is doped with a n-type dopant, and represent the gates for the n-channel pull-down transistors M 2  or M 4 . As mentioned previously, a junction diode is formed by the junction of the p-poly and n-poly portions  203   a  and  203   b,  thus, necessitating a conductive strap layer which is formed from the WSi layer  302 .  
         [0019]    [0019]FIGS. 4 a  and  4   b  illustrate cross-sectional views following masking steps for the formation of exhumed contacts (EC)  230  and  232  (FIG. 2 c ). As used herein, the term masking steps include various conventional processing steps, including applying photoresist (PR), exposing the PR, and developing the PR. The process of masking is well known in the art, and will not be discussed in any greater detail for the sake of brevity. In the embodiment of the invention presently being discussed, strap cut regions  222  and  224  are formed concurrently with the exhumed contacts  230  and  232 . As illustrated in FIGS. 4 a  and  4   b,  regions uncovered by photoresist  404  will be removed in a subsequent etch process forming the strap cut regions  222  and  224  and the exhumed contacts  230  and  232  (FIG. 2 c ). An advantage provided by this embodiment is that no additional steps need to be incorporated into the conventional fabrication process of an SRAM cell to employ the strap cuts according to the present invention. However, it will be appreciated that the mask for the exhumed contacts  230  and  232  will need to be modified to include the strap cut regions  222  and  224  for the present embodiment.  
         [0020]    [0020]FIGS. 5 a  and  5   b  illustrate cross-sectional views, and FIG. 5 c  illustrates a the corresponding layout, following an etching step to form the exhumed contacts  230  and  232  and the strap cut regions  222  and  224 . Typically, the EC etch is selective to polysilicon, and consequently, the TEOS and WSi layers are removed during the etch process. As shown in FIG. 5 a,  the etch step removes portions of TEOS and WSi layers  304  and  302  to expose a portion of the polysilicon layer  203   a  for the formation of the exhumed contact  230 . The strap cut region  222  is formed by the etch step as well. The TEOS and WSi layers that are positioned above the polysilicon layer of the gate  204  in FIG. 5 a  represent a surface located at a different depth than at which the cross-sectional view of FIG. 5 a  is taken. However, the TEOS and WSi layers have been shown for clarity.  
         [0021]    [0021]FIG. 5 b  illustrates the result of the EC etch along the gate  202 . Portions of the TEOS and WSi layers  304  and  302  are removed to form the strap cut region  224 , thereby exposing a region of the n-poly portion  203   b.  Significantly, the strap cut region  224  is offset from the junction of the p-poly and n-poly portions  203   a  and  203   b  such that the WSi strap layer  302  still provides a low resistance current path across the junction. However, because of the discontinuity in the WSi layer  302  created by the strap cut region  224 , the cross-diffusion of dopants is reduced compared to a conventional strap layer where the layer of conductive material is continuous. That is, by reducing the length of overlap of the WSi strap layer  302  across the junction of the p-poly and n-poly portions  203   a  and  203   b,  the degree of dopant cross-diffusion can be reduced, thus, reducing adverse effects caused by the cross-diffusion.  
         [0022]    Following the etching of the exhumed contacts  230  and  232 , and the strap cut regions  222  and  224 , the formation of conventional sidewalls or spacers is performed. The spacers are used as masks for device implant steps, such as the formation of lightly doped drain (LDD) regions, and further to electrically isolate the polysilicon and WSi of the gates  202  and  204  from conductive local interconnects that are formed in subsequent steps. The process by which the spacers are formed are well known in the art. One common manner in which the insulative spacers are formed includes a silicon nitride SiN deposition step followed by an anisotropic etch.  
         [0023]    [0023]FIGS. 6 a  and  6   b  illustrate cross-sectional views of the SRAM  200  following the formation of the spacers. As illustrated in FIG. 6 a,  spacers  610  are formed along the vertical surfaces of the structures of the gates  202  and  204 . With respect to the gate  204 , the spacers insulate the polysilicon and WSi layers  203 . However, with respect to the gate  202 , although the WSi layer  203  is insulated, an upper surface of the polysilicon layer  203   a  of the gate  202  remains exposed for electrical contact with a subsequently formed conductive local interconnect. As illustrated in FIG. 6 b,  the spacer  610  is formed within the strap cut region  224  to insulate the exposed portion of the n-poly portion  203   b.  It will be appreciated that the depth of any cleft formed in the spacer  610  can be adjusted by different means. For example, the width and depth of the strap cut region  224  can be modified, as well as the thickness of the deposited SiN layer and the amount of etchback to adjust the spacer  610 .  
         [0024]    After the spacers  610  are formed, conductive local interconnects (LI) are formed to electrically couple various regions of the SRAM cell  200 . Cross-sectional views of the resulting semiconductor structure are illustrated in FIGS. 2 a  and  2   b,  and the corresponding layout is illustrated in FIG. 2 c.  The local interconnect  240  couples the gate  204  to the active regions  210  and  212  at regions  254  and  256 , respectively, and represents the node A as indicated in the schematic shown in FIG. 1 a.  The local interconnect  242  couples the gate  202  to the active regions  210  and  212  at regions  250  and  252 , respectively, and represents the node B as indicated in the same schematic. The local interconnects are typically formed from a conductive material such as tungsten.  
         [0025]    It will be appreciated that the detailed description provided herein is sufficient to allow a person of ordinary skill to practice the present invention. Moreover, although embodiments of the present invention have been described with respect to an SRAM cell, some or all of the principles of the present invention can be applied to various semiconductor structures where a dual-polycide structure is desired.  
         [0026]    A memory device  700  that uses memory array  702  having dual-polycide structures according to one embodiment of the invention is shown in FIG. 7. The memory device  700  includes a command decoder  706  that receives memory command through a command bus  708  and generates corresponding control signals. A row or column address is applied to the memory device  700  through an address bus  720  and is decoded by a row address decoder  724  or a column address decoder  728 , respectively. Sense amplifiers  730  are coupled to the array  702  to provide read data to a data output buffer  734  that, in turn, applies the read data to a data bus  740 . Write data are applied to the memory array through a data input buffer  744 . The buffers  734 ,  744  comprise a data path.  
         [0027]    [0027]FIG. 8 is a block diagram of a computer system  800  including computing circuitry  802 . The computing circuitry  802  contains a memory  801  having dual-polycide structures according to embodiments of the present invention. The computing circuitry  802  performs various computing functions, such as executing specific software to perform specific calculations or tasks. In addition, the computer system  800  includes one or more input devices  804 , such as a keyboard or a mouse, coupled to the computer circuitry  802  to allow an operator to interface with the computer system. Typically, the computer system  800  also includes one or more output devices  806  coupled to the computer circuitry  802 , such output devices typically being a printer or a video terminal. One or more data storage devices  808  are also typically coupled to the computer circuitry  802  to store data or retrieve data from external storage media (not shown). Examples of typical storage devices  808  include hard and floppy disks, tape cassettes, and compact disc read-only memories (CD-ROMs). The computer circuitry  802  is typically coupled to the memory device  801  through appropriate address, data, and control busses to provide for writing data to and reading data from the memory device.  
         [0028]    It will be further appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. For example, embodiments of the present invention have been described as forming the strap cut regions  222  and  224  during an EC etch which is performed subsequent to the formation of the gates  202  and  204 . However, it will be appreciated that the EC etch and the formation of the strap cut regions  222  and  224  can be performed prior to the gate formation as well. Additionally, the formation of the strap cut regions  222  and  224  can be performed independently of the EC etch step without departing from the scope of the present invention as well. Accordingly, the invention is not limited except as by the appended claims.