Abstract:
The present invention implements structures and method for non-delayed clock dynamic logic circuit configurations with output and/or complementary output with reduced glitch and/or mitigating adverse charge-sharing effects for Complementary Oxide Semiconductor (CMOS) and/or mitigating parasitic bipolar action in Strained/Unstrained Silicon-On-Insulator (SOI) circuits, where insulator may be oxide, nitride of Silicon and the like or Sapphire and the like including a method of synthesis.

Description:
BACKGROUND OF THE INVENTION 
   1. Technical Field 
   The present invention generally relates to integrated circuits (ICs). More particularly, the present invention relates to ICs incorporating dynamic or domino logic circuits. 
   2. Glossary of Terms 
   Bulk-CMOS refers to Complementary Metal Oxide Semiconductor and refers to a design and fabrication technology for semiconductors. 
   SOI where Insulator is Oxide or nitride of Silicon and the like or Sapphire. The SOI field effect transistor n-type has a parallel parasitic bipolar NPN transistor associated with it. The drain of the n-type is equivalent to the collector of the parasitic bipolar transistor. The source of the n-type is equivalent to the emitter of the parasitic bipolar transistor. The body of the n-type becomes charged by induced leakage whenever the drain and source terminals are held at a high potential. If the source is dropped to a low potential the trapped charged in the body causes a current to flow from the base of the parasitic bipolar transistor. This causes a current to flow in the collector that is parallel to a current flowing in the drain. This action may discharge the drain node of a dynamic circuit and may result in erroneous evaluation. The SOI device may be strained by introducing another material with different atomic size than Silicon e.g. Germanium and the like. 
   A Metal Oxide Semiconductor (MOS) transistor has 2 electrodes referred to as the source and the drain and a control electrode as the gate. A transistor has a bulk connection which may be floating e.g. in SOI. 
   N-type is a Metal Oxide Semiconductor (MOS) transistor with electrons as majority carriers. 
   P-type is a Metal Oxide Semiconductor (MOS) transistor with holes as majority carriers 
   Primitives are technology independent gates e.g. AND gates, OR gates, NOT etc. 
   NAND gate is inversion of AND and NOR is inversion of OR. 
   A Register Transfer Level Description is a high level abstraction of a logic design. It comprises logic functions to be implemented in an integrated circuit. Interface constraints and a technology data-base may be specified. An example of a language that may be used for RTL description is VHDL or Verilog etc. 
   .lib is the well-known Synopsys library format. 
   Expressions are the product of parsing register transfer level statements and may be utilized as the starting point in a logic description. 
   Digital design Synthesis is used to mean the synthesis of a technology dependent model from a register transfer level description or from interconnected functional blocks to result in standard-cell mapped design from a target library, or result in a combination of standard-cell mapped design from a target library and a transistor level representation for part or all of the input design specification. 
   Under DeMorgan&#39;s theorem, a NAND gate with inverted inputs performs an OR function and a NOR gate with inverted inputs performs an AND function. 
   A short-circuit occurs when there is a path of zero or almost zero resistance between a first known voltage level and a second known voltage level. 
   A non-inverting node has no inversion e.g. AND, OR and the like or a combination of these. 
   An inverting node has inversion e.g. NAND, NOR, NOT and the like or a combination of these. 
   Domino logic circuits are discussed in “High-Speed Compact Circuits with CMOS”, Krambeck et al., IEEE Journal of Solid-State Circuits, Vol. SC-17, No. 3, June 1982, pp. 614-619, and “High-Speed CMOS Design Styles”, Kluwer Academic Publishers, Boston, 1998, pp. 93-98 and U.S. Pat. No. 5,291,076 issued to Bridges et. al. on Mar. 1, 1994 and U.S. Pat. No. 6,225,826 issued to Krishnamurthy et. al on May 1, 2001 and are dynamic in nature with precharge and evaluation clock to provide output and/or complementary output. 
   3. Description of the Related Art 
   Digital circuits often require true and complementary boolean logic functions. Dynamic or Domino circuits require conversion to non-inverting only stages and may result in some duplication resulting in increased area and power consumption. To avoid this duplication, a dual output implementation (including true and/or complementary versions of the domino stage) is used. 
   For example, A dynamic cascode switching arrangement as prior art of U.S. Pat. No. 5,291,076 issued to Bridges et. al. on Mar. 1, 1994 is depicted in  FIG. 1  of a precharge device  28 . Precharge device  28  is implemented as a NOR gate. This design allows precharge device  28  to have a large number of input signals without reducing its performance. Precharge device  28  has a CLOCK and a transistor tree  29  and two nodes  30  and  32 . Tree  29  is connected between nodes  30  and  32  and contains logic circuits operable to electrically short-circuit nodes  30  and  32  together given a predetermined set of inputs as will be described below. The transistor tree  29  contains three transistors Q 14 , Q 15 , and Q 16  connected in parallel between nodes  30  and  32 . The gates of transistors Q 14 , Q 15  and Q 16  are connected to the input signals A.sub. 1 , A.sub. 2  and A.sub. 3 , respectively. The drains of transistors Q 14 , Q 15 , and Q 16  are connected to node  30 . The sources of transistors Q 14 , Q 15 , and Q 16  are connected to node  32 . 
   Precharge device  28  also has two clocking transistors Q 17  and Q 18 , an evaluate transistor Q 19  and a screening transistor Q 20 . The gates of clocking transistors Q 17  and Q 18  and evaluate transistor Q 19  are connected to a periodic timing signal, CLOCK. The drains of clocking transistors Q 17  and Q 18  are connected to a voltage supply. V.sub.DD. The source of clocking transistor Q 17  is connected to node  30 . The source of clocking transistor Q 18  is connected to an output node  34 . Evaluate transistor Q 19  has its drain and source connected to node  32  and to ground, respectively. Screening transistor Q 20  has its gate connected to node  30 , its drain connected to output node  34  and its source connected to node  32 . 
   Precharge device  28  may have two latching transistors Q 21  and Q 22  to improve the resistance of precharge device  28  to inherent circuit instabilities. Both of the drains of latching transistors Q 21  and Q 22  are connected to V.sub.DD. The source and gate of latching transistor Q 21  are connected to nodes  30  and  34 , respectively. Conversely, the source and gate of latching transistor Q 22  are connected to nodes  34  and  30 , respectively. 
   The output of precharge device  28 , OUTPUT*, is generated by the voltage at node  34  inverted and buffered by an inverter  36 . An inverter  37  connected to node  30  generates the signal OUTPUT. As depicted, all transistors in precharge device  28  are n-channel devices with the exception of clocking transistors Q 17  and Q 18  and latching transistors Q 21  and Q 22 . Clocking transistors Q 17  and Q 18  and latching transistors Q 21  and Q 22  are p-channel devices. 
   Node  30  is discharged if any of the inputs A.sub. 1 , A.sub. 2 , and A.sub. 3  are a logic high which is input to inverter  36 . However, one skilled in the art will readily appreciate the wide variety of applications for precharge device  28  with suitably modified transistor trees. The precharge device  28 , has two stages, the precharge and evaluate stages correspond to a low and a high voltage on CLOCK, respectively. 
   In operation, precharge device  28  precharges nodes  30  and  34  to a known or predetermined voltage level when the input CLOCK is low. In the illustrated form, nodes  30  and  34  are precharged to V.sub.DD. The output from inverters  36  and  37  are therefore initially low. Transistor Q 20  causes a voltage drop between nodes  34  and  32  of V.sub.TH, one transistor threshold voltage. Node  32  is therefore initially at a voltage of (V.sub.DD−V.sub.TH). When the input CLOCK switches high, precharge device  28  evaluates the voltage present on node  30 . In the evaluation stage if inputs through transistors Q 14  or Q 15  or Q 16  result in a conductive path, the voltage at node  30  is discharged to a second known or predetermined voltage level through clocking transistor Q 19 . In the illustrated form, node  30  is discharged to ground, V.sub.SS. The voltage on node  32  also drops to ground, V.sub.SS as the input CLOCK places clocking transistor Q 19  in a conducting state. As the voltage on node  30  drops, screening transistor Q 20  ceases to conduct. The non conducting state of screening transistor Q 20  prevents node  34  from discharging, maintaining the low output from inverter  36 . The low voltage level on node  30 , however, causes OUTPUT to switch to high. 
   In case that inputs to transistors Q 14 , Q 15  or Q 16  do not result in a conductive path in the evaluation stage. The precharge device,  28  implemented as a NOR gate is the combination of inputs, A.sub. 1 , A.sub. 2 , and A.sub. 3  that does not discharge node  30 . In this state, precharge device  28  outputs a logic high signal through inverter  36 . 
   As described above, precharge device  28  precharges nodes  30  and  34  to V.sub.DD, precharges node  32  to (V.sub.DD−V.sub.TH) and outputs a logic low on inverters  36  and  37  when the input CLOCK is low. When the input CLOCK switches high, precharge device  28  evaluates the voltage present on node  30 . If the inputs do not result in the voltage at node  30  to be discharged to V.sub.SS, ground, a high voltage on node  30  places screening transistor Q 20  in a conducting state. Evaluate transistor Q 19  is placed in a conducting state by a high CLOCK signal. Node  34  then discharges to ground through screening transistor Q 20  and evaluate transistor Q 19 . Inverter  36  inverts the low voltage on node  34  and outputs a high logic level. Inverter  37  inverts the high voltage at node  30  and continues to output a low logic signal as Node  32  discharges to ground. 
   In the evaluation stage, one or more of decode transistors Q 14 , Q 15  or Q 16  may, discharge node  30  to V.sub.SS, ground. Node  30  discharges after a finite time which depends on the delay associated with the transistor tree  29 , evaluation transistor Q 19 , screening transistor Q 20 , capacitance on node  30  and the cascade switching arrangement. This finite discharge time for node  30  places latching transistor Q 22  into a non-conducting state during this finite time and is unable to supply voltage, V.sub.DD, to node  34 . The evaluate transistor Q 19  turns on as soon as the CLOCK goes from precharge to evaluate stage. Worst of all, the screening transistor Q 20  stays in the ON state for a finite time, giving rise to a glitch on node  34  and nothing to replenish it. Any additional keeper(s) if present also slow down this circuit due to contention on node  34 . Further, if node  34  discharges below a certain threshold, inverter  36  would erroneously treat the voltage at node  34  as a logic low resulting an erroneous value on OUTPUT*. Dynamic circuits such as precharge device  28  are particularly susceptible to such erroneous loss of precharge and glitches are not tolerated on OUTPUT* as it may be input to other precharge devices similar to  28 . 
   In another example, dynamic cascade switching arrangement prior art of U.S. Pat. No. 6,225,826 issued to Krishnamurthy et. al. on May 1, 2001 is depicted in  FIG. 2  and includes a domino stage  202  including a series of parallel nFET transistors (represented by M 42  and M 43 ) that receive a domino stage input signal A 1  . . . An. But without an evaluation transistor between the source(s) of A 1  . . . An and V.sub.SS whose gate may have been connected to the CLK. In the precharge phase, when CLK is low, a node N 1  is pulled high through a pFET transistor M 40  and a node N 2  is pulled high through a pFET transistor M 45 . With nodes N 1  and N 2  high, OUT and OUT* are low through inverters  210  and  212 . 
   In the evaluate phase, CLK is high so that transistors M 40  and M 45  are off, but transistor M 47  is on. If no bit of A 1  . . . An is high, node N 1  remains high and node N 2  is pulled low through transistors M 46  and M 47 . With node N 2  low, OUT* is pulled high through inverter  212 . If any of A 1  . . . An is high, node N 1  is pulled low after a finite time which depends on the delay associated with the transistor tree M 42  . . . M 43 , screening transistor M 44 , capacitance on node N 1  and the cascade switching arrangement. 
   This finite discharge time for node N 1  places latching transistor M 44  into a non-conducting state during this finite time and is unable to supply voltage, V.sub.DD, to node N 2 . The evaluate transistor M 47  turns on as soon as the CLOCK goes from precharge to evaluate stage. Worst of all, the screening transistor M 46  stays in the ON state for a finite time, giving rise to a glitch on node N 2  and nothing to replenish it. Any additional keeper(s) if present also slow down this circuit due to contention on node N 2 . Further, if node  34  discharges below a certain threshold, inverter  212  would erroneously treat the voltage at node N 2  as a logic low resulting an erroneous value on OUT*. Dynamic circuits such as precharge device  202  are particularly susceptible to such erroneous loss of precharge and glitches are not tolerated on OUT* as it may be input to other precharge devices similar to  202 . 
   A disadvantage of the prior art is the glitch problem makes the dynamic circuit very vulnerable to erroneous results as the loss of precharge cannot be compensated, while reducing the delay through this dynamic circuit. 
   Several prior art U.S. patents teach to delay the clock signal to generate a complementary output, e.g. U.S. Pat. No. 6,549,040 issued to Alvandpour et. al on Apr. 15, 2003, U.S. Pat. No. 6,225,826 issued to Krishnamurthy et. al. on May 1, 2001, U.S. Pat. No. 6,377,080 issued to Arnold on Apr. 23, 2002, U.S. Pat. No. 6,492,839 issued to Wang et. al on Dec. 10, 2002 and U.S. Pat. No. 5,892,372 issued to Ciraula et.al on Apr. 6, 1999. It is difficult to provide optimal delay within the semiconductor process variations, any extra delay with additional safety margin will slow down the circuit and shorter delay may result in glitch and race conditions. 
   SUMMARY OF THE INVENTION 
   It is, accordingly, an object of the present invention to reduce the glitch to a minimum, while keeping power consumption and delay through the circuit low to provide output signal and/or complementary output signal responsive to input signals. 
   It is also an object of the invention to mitigate adverse charge-sharing effects for Complementary Oxide Semiconductor (CMOS) and/or mitigating parasitic bipolar action in Strained/Unstrained Silicon-On-Insulator (SOI) circuits, where insulator may be oxide, nitride of Silicon and the like or Sapphire and the like including a method of synthesis. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying  FIGS. 1 to 11  of embodiments of the invention which, however, should not be taken to limit the invention to the specific embodiments described, but are for explanation and understanding only. 
       FIG. 1  depicts a schematic diagram of a prior art implemented with output and complementary output with potential of a glitch; 
       FIG. 2  depicts a schematic diagram of a prior art implemented with output and complementary output with potential of a glitch; 
       FIG. 3  depicts a schematic diagram of a precharge device constructed according to an embodiment of the disclosed invention; 
       FIG. 4  depicts a schematic diagram of a precharge device constructed according to another embodiment of the disclosed invention; 
       FIG. 5  depicts a schematic diagram of a precharge device constructed according to yet another embodiment of the disclosed invention; 
       FIG. 6  depicts a schematic diagram of a precharge device constructed according to yet another embodiment of the disclosed invention; 
       FIG. 7  depicts a partial schematic diagram of a glitch-reducing transistor which is incorporated in various embodiments of the invention depicted in  FIG. 3  to  FIG. 6 . 
       FIG. 8  depicts a timing diagram in graphical form of the precharge device depicted in  FIG. 4 ; 
       FIG. 9  depicts a partial schematic diagram of a transistor tree for bulk-CMOS which is incorporated in various embodiments of the invention depicted in  FIG. 3  to  FIG. 6 ; 
       FIG. 10  depicts a partial schematic diagram of a transistor tree for SOI which is incorporated in various embodiments of the invention depicted in  FIG. 3 ,  FIG. 5  and  FIG. 11 . 
       FIG. 11  depicts a schematic diagram with a transistor tree for SOI which is incorporated in a single output domino logic circuit. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 3  depicts a schematic diagram of a precharge device  300  constructed according to an embodiment of the present invention without cascode switching arrangement and with a glitch-reducing device  311  consisting of transistor M 34 . Precharge device  300  has a CLOCK and a transistor tree  305  where the tree  305  is connected between nodes  301  and  302  and may contain transistors in series or in parallel or series-parallel or parallel-series or any combination of these. 
   Precharge device  300  also has two clocking transistors M 30  and M 33 , and two separate evaluate transistor M 36  and M 37  and a screening transistor M 35 . The gates of clocking transistors M 30  and M 33  and the two evaluate transistors M 36  and M 37  are connected to a periodic timing signal, CLOCK. The drains of clocking transistors M 32  and M 33  are connected to a voltage supply. V.sub.DD. The source of clocking transistor M 30  is connected to node  301 . The source of clocking transistor M 33  is connected to node  303 . Evaluate transistor M 36  has its drain and source connected to node  302  and to V.sub.SS, ground, respectively. Evaluate transistor M 37  has its drain and source connected to node  304  and to V.sub.SS, ground, respectively Screening transistor M 35  has its gate connected to node  301 , its first electrode is connected to node  303  and it&#39;s second connected to node  304 . 
   In operation, precharge device  300  precharges nodes  301  and  303  to a known or predetermined voltage level when the input CLOCK is low. In the illustrated form, nodes  301  and  303  are precharged to V.sub.DD. The output from inverters  306  and  308  are therefore initially low. Transistor M 35  causes a voltage drop between nodes  303  and  304  of V.sub.TH, one transistor threshold voltage. Node  304  is therefore initially at a voltage of (V.sub.DD−V.sub.TH). The evaluation stage is marked by CLOCK going to a high potential value. 
   Precharge device  300  may have two latching transistors M 31  and M 32 , the M 31  latching transistor prevents the node  301  from floating when there is no conductive path between  301  and node  302  during the evaluation stage and also assists in reducing the effects of any charge sharing or leakage during this time. This leads to a high logic on OUT node  307  through the inverter  306  connected to node  301 . To reduce contention at node  301  when there is a conductive path between node  301  and  302  during the evaluation stage, M 31  should not be immediately in the ON state otherwise M 31  may try to pull the node  301  to V.sub.DD while simultaneously the node  301  is also being pulled to V.sub.SS resulting in increased power consumption as well as increased delay. In the preferred embodiment, the gate of M 31  is connected to node  303  through two (or in general a delay element) inverters  308  and  310  to provide such minimal delay for M 31  to turn ON. The glitch-reducing transistor M 34  has it&#39;s drain connected to V.sub.DD, and it&#39;s source and gate is connected to the node  303  (other configurations for the glitch-reducing transistor are described in  FIG. 7 ). When there is a conductive path between the node  301  and node  302  during the evaluation stage, the screening transistor M 35  is in the ON state during this finite time (which depends on the delay associated with the transistor tree  305 , evaluation transistors M 36  and M 37 , screening transistor M 35 , capacitance on node  301 ) and with evaluation transistor M 37  in the ON state during the evaluation stage, the voltage on the node  303  begins to be lowered while latching transistor M 32  is still in the OFF state. During this critical time, the glitch-reducing transistor instantly aids in trying to keep the voltage on the node  303  from being lowered compared to a situation when the glitch-reducing transistor were absent (more detailed description in  FIG. 9 ). As the voltage on the node  301  continues to be lowered, latching transistor M 32  then pulls node  303  all the way to V.sub.DD while the screening transistor M 35  also turns OFF. 
   The output of precharge device  300 , node  309  also referred to as OUT*, is generated by the voltage at node  303  inverted and buffered by an inverter  308 . An inverter  306  connected to node  301  generates the signal OUT also referred to as node  307 . As depicted, all transistors in precharge device  300  are n-channel devices with the exception of clocking transistors M 30  and M 33  and latching transistors M 31  and M 32 . Clocking transistors M 30  and M 33  and latching transistors M 31  and M 32  are p-channel devices. The evaluation transistor M 36  may not be needed if the transistor tree  305  has all paths between the nodes  301  and  302  which at least have one input which is output from other domino stage(s). 
     FIG. 4  depicts a schematic diagram of a precharge device  300  constructed according to another embodiment of the present invention without cascode switching arrangement and with a glitch-reducing device  409  consisting of transistor M 34 , and a single evaluation transistor M 46 . Precharge device  400  has a CLOCK and a transistor tree  405  where the tree  405  is connected between nodes  401  and  402  and may contain transistors in series or in parallel or series-parallel or parallel-series or any combination of these. 
   Precharge device  400  also has two clocking transistors M 40  and M 43 , and a single evaluate transistor M 46  and a screening transistor M 45 . The gates of clocking transistors M 40  and M 43  and the single evaluate transistor M 46  is connected to a periodic timing signal, CLOCK. The drains of clocking transistors M 42  and M 43  are connected to a voltage supply. V.sub.DD. The source of clocking transistor M 40  is connected to node  401 . The source of clocking transistor M 43  is connected to node  403 . Evaluate transistor M 46  has its drain and source connected to node  402  and to V.sub.SS, ground, respectively. Screening transistor M 45  has its gate connected to node  401 , one of it&#39;s electrode connected to node  402  and second electrode connected to node  403 . 
   In operation, precharge device  400  precharges nodes  401  and  403  to a known or predetermined voltage level when the input CLOCK is low. In the illustrated form, nodes  401  and  403  are precharged to V.sub.DD. The output from inverters  406  and  407  are therefore initially low. Transistor M 45  causes a voltage drop between nodes  403  and  402  of V.sub.TH, one transistor threshold voltage. Node  402  is therefore initially at a voltage of (V.sub.DD−V.sub.TH). As the screening transistor is in the ON state during the precharge stage, node  402  may potentially also precharge some of the transistors in the transistor tree  405 , and this may help in reducing the charge sharing effect on the node  401 . The evaluation stage is marked by CLOCK going to a high potential value. 
   Precharge device  400  may have two latching transistors M 41  and M 42 , the M 41  latching transistor prevents the node  401  from floating when there is no conductive path between  401  and node  402  during the evaluation stage and also assists in reducing the effects of any charge sharing or leakage during this time. This leads to a high logic on OUT node  406  through the inverter  404  connected to node  401 . To reduce contention at node  401  when there is a conductive path between node  401  and  402  during the evaluation stage, M 41  should not be immediately in the ON state otherwise M 41  may try to pull the node  401  to V.sub.DD while simultaneously the node  401  is also being pulled to V.sub.SS resulting in increased power consumption as well as increased delay. In the preferred embodiment, the gate of M 41  is connected to node  403  through two (or in general a delay element) inverters  407  and  410  to provide such minimal delay for M 41  to turn ON. The glitch-reducing transistor M 44  has it&#39;s drain connected to V.sub.DD, and it&#39;s source and gate is connected to the node  403  (other configurations for the glitch-reducing transistor are described in  FIG. 7 ). When there is a conductive path between the node  401  and node  402  during the evaluation stage, the screening transistor M 45  is in the ON state during this finite time (which depends on the delay associated with the transistor tree  405 , evaluation transistor M 46 , screening transistor M 45 , capacitance on node  401 ) and with evaluation transistor M 46  in the ON state during the evaluation stage, the voltage on the node  403  begins to be lowered while latching transistor M 42  is still in the OFF state. During this critical time, the glitch-reducing transistor instantly aids in trying to keep the voltage on the node  403  from being lowered compared to a situation when the glitch-reducing transistor were absent (more detailed description in  FIG. 9 ). As the voltage on the node  401  continues to be lowered, latching transistor M 42  then pulls node  403  all the way to V.sub.DD while the screening transistor M 45  also turns OFF. 
   The output of precharge device  400 , node  408  also referred to as OUT*, is generated by the voltage at node  403  inverted and buffered by an inverter  407 . An inverter  404  connected to node  401  generates the signal OUT also referred to as node  406 . As depicted, all transistors in precharge device  400  are n-channel devices with the exception of clocking transistors M 40  and M 43  and latching transistors M 41  and M 42 . Clocking transistors M 40  and M 43  and latching transistors M 41  and M 42  are p-channel devices. 
     FIG. 5  depicts a schematic diagram of a precharge device  500  constructed according to another embodiment of the present invention with cascode switching arrangement and with a glitch-reducing device  510  consisting of transistor M 54 . Precharge device  500  has a CLOCK and a transistor tree  505  where the tree  505  is connected between nodes  501  and  502  and may contain transistors in series or in parallel or series-parallel or parallel-series or any combination of these. 
   Precharge device  500  also has two clocking transistors M 50  and M 53 , and two separate evaluate transistor M 56  and M 57  and a screening transistor M 55 . The gates of clocking transistors M 50  and M 53  and the two evaluate transistors M 56  and M 57  are connected to a periodic timing signal, CLOCK. The drains of clocking transistors M 52  and M 53  are connected to a voltage supply. V.sub.DD. The source of clocking transistor M 50  is connected to node  501 . The source of clocking transistor M 53  is connected to node  503 . Evaluate transistor M 56  has its drain and source connected to node  502  and to V.sub.SS, ground, respectively. Evaluate transistor M 57  has its drain and source connected to node  504  and to V.sub.SS, ground, respectively Screening transistor M 55  has its gate connected to node  501 , its first electrode is connected to node  503  and it&#39;s second connected to node  504 . 
   In operation, precharge device  500  precharges nodes  501  and  503  to a known or predetermined voltage level when the input CLOCK is low. In the illustrated form, nodes  501  and  503  are precharged to V.sub.DD. The output from inverters  506  and  508  are therefore initially low. Transistor M 55  causes a voltage drop between nodes  503  and  504  of V.sub.TH, one transistor threshold voltage. Node  504  is therefore initially at a voltage of (V.sub.DD−V.sub.TH). The evaluation stage is marked by CLOCK going to a high potential value. 
   Precharge device  500  may have two latching transistors M 51  and M 52 , the M 51  latching transistor prevents the node  501  from floating when there is no conductive path between  501  and node  502  during the evaluation stage and also assists in reducing the effects of any charge sharing or leakage during this time. This leads to a high logic on OUT node  507  through the inverter  506  connected to node  501 . In the preferred embodiment, the gate of M 51  is connected to node  503  and this increases the capacitance on node  503  which may help in reducing the glitch on node  503  as discussed further. The glitch-reducing transistor M 54  has it&#39;s drain connected to V.sub.DD, and it&#39;s source and gate is connected to the node  503  (other configurations for the glitch-reducing transistor are described in  FIG. 7 ). When there is a conductive path between the node  501  and node  502  during the evaluation stage, the screening transistor M 55  is in the ON state during this finite time (which depends on the delay associated with the transistor tree  505 , evaluation transistors M 56  and M 57 , screening transistor M 55 , capacitance on node  501 ) and with evaluation transistor M 57  in the ON state during the evaluation stage, the voltage on the node  503  begins to be lowered while latching transistor M 52  is still in the OFF state. During this critical time, the glitch-reducing transistor instantly aids in trying to keep the voltage on the node  503  from being lowered compared to a situation when the glitch-reducing transistor were absent (more detailed description in  FIG. 9 ). As the voltage on the node  501  continues to be lowered, latching transistor M 52  then pulls node  503  all the way to V.sub.DD while the screening transistor M 55  also turns OFF. 
   The output of precharge device  500 , node  509  also referred to as OUT*, is generated by the voltage at node  503  inverted and buffered by an inverter  508 . An inverter  506  connected to node  501  generates the signal OUT also referred to as node  507 . As depicted, all transistors in precharge device  500  are n-channel devices with the exception of clocking transistors M 50  and M 53  and latching transistors M 51  and M 52 . Clocking transistors M 50  and M 53  and latching transistors M 51  and M 52  are p-channel devices. The evaluation transistor M 56  may not be needed if the transistor tree  505  has all paths between the nodes  501  and  502  which at least have one input which is output from other domino stage(s). 
     FIG. 6  depicts a schematic diagram of a precharge device  600  constructed according to another embodiment of the present invention without cascode switching arrangement and with a glitch-reducing device  609  consisting of transistor M 64  and a single evaluation transistor M 66 . Precharge device  600  has a CLOCK and a transistor tree  605  where the tree  605  is connected between nodes  601  and  602  and may contain transistors in series or in parallel or series-parallel or parallel-series or any combination of these. 
   Precharge device  600  also has two clocking transistors M 60  and M 63 , and a single evaluate transistor M 66  and a screening transistor M 65 . The gates of clocking transistors M 60  and M 63  and the single evaluate transistor M 66  is connected to a periodic timing signal, CLOCK. The drains of clocking transistors M 62  and M 63  are connected to a voltage supply. V.sub.DD. The source of clocking transistor M 60  is connected to node  601 . The source of clocking transistor M 63  is connected to node  603 . Evaluate transistor M 66  has its drain and source connected to node  602  and to V.sub.SS, ground, respectively. Screening transistor M 65  has its gate connected to node  601 , one of it&#39;s electrode connected to node  602  and second electrode connected to node  603 . 
   In operation, precharge device  600  precharges nodes  601  and  603  to a known or predetermined voltage level when the input CLOCK is low. In the illustrated form, nodes  601  and  603  are precharged to V.sub.DD. The output from inverters  606  and  607  are therefore initially low. Transistor M 65  causes a voltage drop between nodes  603  and  602  of V.sub.TH, one transistor threshold voltage. Node  602  is therefore initially at a voltage of (V.sub.DD−V.sub.TH). As the screening transistor is in the ON state during the precharge stage, node  602  may potentially also precharge some of the transistors in the transistor tree  605 , and this may help in reducing the charge sharing effect on the node  601 . The evaluation stage is marked by CLOCK going to a high potential value. 
   Precharge device  600  may have two latching transistors M 61  and M 62 , the M 61  latching transistor prevents the node  601  from floating when there is no conductive path between  601  and node  602  during the evaluation stage and also assists in reducing the effects of any charge sharing or leakage during this time. This leads to a high logic on OUT node  606  through the inverter  604  connected to node  601 . 
   In the preferred embodiment, the gate of M 61  is connected to node  603  thereby increasing the capacitance on the node  603  which may assist in reducing the glitch on the node  603 . The glitch-reducing transistor M 64  has it&#39;s drain connected to V.sub.DD, and it&#39;s source and gate is connected to the node  603  (other configurations for the glitch-reducing transistor are described in  FIG. 7 ). When there is a conductive path between the node  601  and node  602  during the evaluation stage, the screening transistor M 65  is in the ON state during this finite time (which depends on the delay associated with the transistor tree  605 , evaluation transistor M 66 , screening transistor M 65 , capacitance on node  601 ) and with evaluation transistor M 66  in the ON state during the evaluation stage, the voltage on the node  603  begins to be lowered while latching transistor M 62  is still in the OFF state. During this critical time, the glitch-reducing transistor instantly aids in trying to keep the voltage on the node  603  from being lowered compared to a situation when the glitch-reducing transistor were absent (more detailed description in  FIG. 9 ). As the voltage on the node  601  continues to be lowered, latching transistor M 62  then pulls node  603  all the way to V.sub.DD while the screening transistor M 65  also turns OFF. 
   The output of precharge device  600 , node  608  also referred to as OUT*, is generated by the voltage at node  603  inverted and buffered by an inverter  607 . An inverter  604  connected to node  601  generates the signal OUT also referred to as node  606 . As depicted, all transistors in precharge device  600  are n-channel devices with the exception of clocking transistors M 60  and M 63  and latching transistors M 61  and M 62 . Clocking transistors M 60  and M 63  and latching transistors M 61  and M 62  are p-channel devices. 
     FIG. 7  depicts more configurations in which the glitch-reducing device  311  of  FIG. 3  or  409  of  FIG. 4  or of  510   FIG. 5  or  609   FIG. 6  may be represented. More multiple configurations may be represented for the glitch-reducing device by those skilled in the art. Any one of these configurations may replace the glitch-reducing device in  FIGS. 3 ,  4 ,  5  and  6  with the node labeled  700  connected to the node  303  of  FIG. 3  or the node  403  of  FIG. 4  or the node  503  of  FIG. 5  or the node  603  of  FIG. 6   
     FIG. 8  depicts the voltages at node  403  of  FIG. 4  with or without glitch-reducing transistor M 44 .  FIG. 8  is divided into two parts named after and corresponding to the two states of precharge device  28 , precharge and evaluate. In the depicted embodiment of  FIG. 4 , the precharge and evaluate states correspond to a low and a high voltage on CLOCK, respectively. It will be noted that Node  403  of  FIG. 4  has a much smaller glitch when glitch-controlling transistor M 44  of  FIG. 4  is present compared to when it is absent. The glitch-reducing transistor M 44  assists in minimizing the glitch at such critical time interval when node  401  of  FIG. 4  is taking finite time to discharge, without adding contention to node  403  of  FIG. 4  and thus not increasing the delay or power consumption of circuit  400  of  FIG. 4 . As the glitch-reducing transistor M 44  of  FIG. 4  is assisting, M 45  of  FIG. 4  after the finite discharge time turns off and M 42  of  FIG. 4  turns on to restore node  403  of  FIG. 4  all the way to V.sub.DD under the conditions when transistor tree  405  of  FIG. 4  has a conductive path to V.sub.SS, ground and takes a finite time to discharge node  401  of  FIG. 4  to V.sub.SS, ground. This trend also applies to node  303  of  FIG. 3 , node  503  of  FIG. 5  and node  603  of  FIG. 6 . 
     FIG. 9  depicts the transistor tree  900  corresponding to  305  of  FIG. 3  or  405  of  FIG. 4  or  505  of  FIG. 5  or  605  of  FIG. 6  for bulk-CMOS where the node  901  corresponds to the node  301  of  FIG. 3  or  401  of  FIG. 4  or  501  of  FIG. 5  or  601  of  FIG. 6  and the node  902  of  FIG. 9  corresponds to the node  302  of  FIG. 3  or the node  402  of  FIG. 4  or the node  502  of  FIG. 5  or  602  of  FIG. 6 . The transistor tree  900  consists of a maximum of one parallel transistor network coupled to the node  901 . It is suited for bulk-CMOS and may be used even if only one output, namely  307  of  FIG. 3  or  406 , OUT in  FIG. 4  or  507  of  FIG. 5  or  606 , OUT in  FIG. 6  corresponding may be the only output of the domino circuit. 
   If the transistor network within the tree does not have high leakage, then this permits a larger capacitance on the node  301  of  FIG. 3  or the node  401  of  FIG. 4  or  501  of  FIG. 5  or  601  of  FIG. 6 , there allowing larger precharge available to share with the nodes of the transistor tree during evaluation stage when there is no conductive path between the nodes  301  and  302  in  FIG. 3  or the nodes  401  and  402  of  FIG. 4  or the nodes  501  and  502  in  FIG. 5  or the nodes  601  and  602  of  FIG. 6 , thereby reducing the effect of charge sharing. 
   Further, the transistor tree of  FIG. 9  is also suited for bulk-CMOS corresponding to  FIG. 11  for single output domino logic circuit In such case, evaluation transistor M 111  of  FIG. 11  for bulk-CMOS may instead be coupled between  902  and the second known potential. The node  901  is coupled to the node  1101  of  FIG. 11  for bulk-CMOS. Consider a transistor tree represented by a Boolean expression, 
   O=a*b+a*c+a*d where a, b, c and d are control electrodes to transistor(s) M 91  . . . M 92 , M 93 , etc. and O is the result of the expression and ‘*’ represents AND and ‘+’ represents OR. The common term is ‘a’ either picked graphically or by factoring this boolean expression and may be represented in an equivalent form by picking the largest term after factoring:
 
 O =( b+a+d )* a;  
 
   This then represents the transistor tree of  FIG. 9  for bulk-CMOS with the largest parallel part of the transistor tree is represented by b+a+d and M 93  represents ‘a’. 
   This transistor tree arrangement of  FIG. 10  is suited for strained or unstrained Silicon-On-Insulator (SOI) when output and/or complementary output are generated, namely  307 , OUT and/or  309 , OUT* in  FIG. 3  (or  507 , OUT and/or  509  in  FIG.5 ). Herein the drain of the evaluation transistor M 101  corresponding to M 36  of  FIG. 3  or M 56  of  FIG. 5  is connected to node  301  of  FIG. 3  (or node  501  of  FIG. 5 ) and it&#39;s source is connected to the drain end of the transistor tree instead of the evaluation transistor M 36  of  FIG. 3  (or M 56  of  FIG. 5 ). The gate of the evaluation transistor M 101  is connected to the CLOCK and the transistor tree may have zero or more series connected transistors on the drain end of the transistor tree and/or one parallel transistor network on the source end of the transistor tree which is connected to the second known potential for each and every path from the drain end of the transistor tree to the source end of the transistor tree which is coupled to the second known potential. The evaluate transistor M 101  ensures that the transistor tree is not precharged during the precharge stage, thereby eliminating the chance of any parasitic bipolar effects. The evaluate transistor M 101  being absent if each and every path from the drain end of the transistor tree to the source end of the transistor tree, the transistors in such path(s) have at least one control electrode of the transistor in such path(s) which is coupled to output from other precharge device(s). 
     FIG. 11  describes a precharge device for strained or unstrained Silicon-On-Insulator (SOI) where the insulator may be oxide or nitride or carbide of a combination of these and the like or Sapphire and the like and comprises of a first node,  1101  and a second node,  1114 ; and a transistor tree,  1104  operable to electrically short-circuit the second node,  1114  to the second known voltage level responsive to input signals; wherein the transistor tree comprising of a series-connected transistor network of zero or more transistors, e.g. M 112  coupled between the second node and the first terminal,  1115  of a two-terminal parallel-connected transistor network wherein the second terminal of the parallel-connected transistor is coupled to the second known voltage level for each and every path from the second node to the second known voltage level wherein the parallel-connected transistor network, M 113  . . . M 114  may be the largest possible while maintaining the equivalent boolean function for the precharge device; and an optional keeper transistor, M 113  comprising a first and a second control electrode and a control electrode, the first current electrode coupled to the first known voltage level, the second current electrode coupled to the first node,  1101  and the control electrode is coupled the output of an inverting buffer,  1113  wherein the inverting buffer input is coupled to the first node,  1101 ; and a clocking transistor, M 112  comprising a first and a second current electrode and a control electrode, the first current electrode coupled to the first known voltage level, the second current electrode coupled to the first node,  1101  and the control electrode coupled to the periodic clocking signal and an evaluate transistor, M 111  comprising a first and a second current electrode and a control electrode, with the first current electrode coupled to the first node,  1101  and the current second node is coupled to the second node,  1114  and the control electrode is coupled to the periodic clock signal, wherein the evaluate transistor being absent if each and every path from the second node to the second known voltage level through the transistor tree has at least one control electrode of the transistor in said path(s) which is coupled to output from other precharge device(s) and clocking circuitry for precharging the first node,  1101  to a first known voltage level during a first phase of a periodic clocking signal and for coupling the first node to the second node and evaluating the voltage on the first node to provide an output logic signal during a second phase of the periodic clocking signal responsive to input signals to the transistor tree potentially short-circuiting first and second node to the second known voltage level. 
   Further, the transistor tree arrangement of  FIG. 11  is also suited for strained or unstrained Silicon-On-Insulator (SOI) even if only one output, namely  307 , OUT in  FIG. 3  (or  507 , OUT in  FIG. 5 ). Herein the drain of the evaluation transistor M 111  corresponds to M 36  of  FIG. 3  or M 56  of  FIG. 5  is connected to node  301  of  FIG. 3  (or node  501  of  FIG. 5 ) and it&#39;s source is connected to the drain end of the transistor tree. The evaluation transistor M 36  of  FIG. 3  (or M 56  of  FIG. 5 ) is replaced with equivalent M 111  similar to  FIG. 11  in  FIG. 3  and  FIG. 5  The gate of the evaluation transistor M 111  is connected to the CLOCK and the transistor tree may have zero or more series connected transistors on the drain end of the transistor tree and/or one parallel transistor network on the source end of the transistor tree which is connected to the second known potential for each and every path from the drain end of the transistor tree to the source end of the transistor tree which is coupled to the second known potential. The evaluate transistor M 111  ensures that the transistor tree is not precharged during the precharge stage, thereby eliminating the chance of any parasitic bipolar effects. The evaluate transistor M 111  being absent if each and every path from the drain end of the transistor tree to the source end of the transistor tree, the transistors in such path(s) have at least one control electrode of the transistor in said path(s) which is coupled to output from other precharge device(s). Consider a transistor tree represented by an expression, 
   O=a*b+a*c+a*d where a, b, c and d are control electrodes to transistor(s) M 101  . . . M 102 , M 103 , etc. corresponding to  FIG. 10  or M 112  . . . M 114 , etc. corresponding to  FIG. 11  and O is the result of the expression and ‘*’ represents AND and ‘+’ represents OR. The common term is ‘a’ either picked graphically or by factoring this expression and may be represented in an equivalent form by picking the largest term after factoring:
 
 O=a *( b+a+d );
 
   This then represents the transistor tree of  FIG. 10  or  FIG. 11  for unstrained/strained SOI with the largest parallel part of the transistor tree is represented by b+a+d e.g. M 102  . . . M 103  of  FIG. 10  or M 113  . . . M 114  of  FIG. 11  while M 101  of  FIG. 10  represents ‘a’ or M 112  represents ‘a’ in  FIG. 11 . 
   The input logic may be synthesized by a process of technology mapping of the input logic circuit into domino logic circuit output where the user may specify the blocks to be converted to domino logic or by determining the critical paths and converting the logic in the critical path to domino logic. Prior art single output domino logic requires that the input logic not contain inverting logic which occurs from circuit components such as inverters, NAND gates, and NOR gates. Further, removal of trapped inverters may require logic duplication as taught in U.S. Pat. No. 5,903,467 issued to Puri et. al on May 11, 1999. The present invention also teaches methods of synthesis where logic duplication is not needed as such blocks may be converted to domino logic where output and/or complementary output is available, thereby considerably saving in delay, power consumption, area, glitch size and the like. 
   The Register Level Language (RTL) such Verilog may be parsed and partitioned to blocks of user-specified (or based on delay related data for a given process technology such as CMOS or SOI and the like) fan-in and/or maximum series connected transistor tree of  FIGS. 3-11 ; or 
   The Register Level Language (RTL) such Verilog may be parsed and mapped to blocks of user-specified (or based on delay related data for a given process technology such as CMOS or SOI and the like a library of cells e.g. .lib format and the like) fan-in and/or maximum series connected transistor tree of  FIGS. 3-11 ; or 
   Previously designed gates or equivalent logic description is collected into blocks subject to user-specified (or based on delay related data for a given process technology such as CMOS or SOI and the like with a library of cells e.g. .lib format and the like) fan-in or maximum series connected transistor tree) of  FIGS. 3-11 ; and 
   In an embodiment of synthesis an input and/or output phase assignment is conducted to convert each block into non-inverting logic, with the option of considering the power consumption as being proportional to signal probability p and if a block is transformed by DeMorgan&#39;s theorem, new signal probability is 1−p but the trapped inverters are not removed while removing the pairs of inverters in series with one another. The domino logic circuit is created where the domino single output non-inverting blocks are created for non-inverting blocks as of prior art domino logic. See, e.g., R. H. Krambeck, et al., “High-Speed Compact Circuits with CMOS,” IEEE Journal of Solid-State Circuits (June, 1982) SC-17(3):614-619 and the like along with improvements mentioned in  FIGS. 9-11 , and for blocks requiring both domino output polarities or only inverting output are implemented as in  FIGS. 3-10  which implement output and/or complementary or other forms of dual output domino logic of  FIGS. 1  or  2  and the like, thereby eliminating the need of logic duplication. 
   Further, the synthesis requires removing pairs of inverters in series with one another and creating non-inverting domino circuit for non-inverting only nodes and creating inverting domino circuit for inverting only nodes and creating precharge circuit with both inverting and non-inverting outputs where both inverting and non-inverting outputs are required for the node(s) and computing a signal probability at each node of the circuit which is proportional to power consumption and evaluating a power consumption for each circuit and choosing the circuit which results in an optimal combination of low power consumption of the circuit and/or with a delay time which is less than or equal to a predetermined delay time and/or low total transistor count and/or glitch severity and/or leakage and the like among said combinations. 
   In another embodiment of synthesis an input and/or output phase assignment is not conducted to convert each block into non-inverting logic rather the domino logic circuit is created where some blocks may have non-inverting domino output blocks only as of prior art domino logic. See, e.g., R. H. Krambeck, et al., “High-Speed Compact Circuits with CMOS,” IEEE Journal of Solid-State Circuits (June, 1982) SC-17(3):614-619 and the like along with improvements mentioned in  FIGS. 9-11 , while other blocks requiring only inverting output and/or both domino output polarities are implemented as in  FIGS. 3-10  which implement output and/or complementary or other forms of dual output domino logic of  FIGS. 1  or  2  and the like, with the option of considering the power consumption as being proportional to signal probability p and if a block is transformed by DeMorgan&#39;s theorem, new signal probability is 1−p while removing the pairs of inverters in series with one another. 
   Further, the synthesis requires removing pairs of inverters in series with one another and creating non-inverting domino circuit for non-inverting only nodes and creating inverting domino circuit for inverting only nodes and creating precharge circuit with both inverting and non-inverting outputs where both inverting and non-inverting outputs are required for the node(s) and computing a signal probability at each node of the circuit which is proportional to power consumption and evaluating a power consumption for each circuit and choosing the circuit which results in an optimal combination of low power consumption of the circuit and/or with a delay time which is less than or equal to a predetermined delay time and/or low total transistor count and/or glitch severity and/or leakage and the like among said combinations. 
   Although the present invention has been described with reference to a specific embodiment, further modifications and improvements will occur to those skilled in the art. For instance, the transistors may be implemented either as n-channel or p-channel devices as desired. These substitutions, and the requisite changes caused by them, will be obvious to one skilled in the art. It is to be understood therefore, that the invention encompasses all such modifications that do not depart from the spirit and scope of the invention as defined in the appended claims. Also, the designation of portions of the various transistors described above as “drain” or “source” is merely semantic given the bidirectional nature of CMOS circuits and is arbitrary given the other semiconductor media in which the disclosed invention may be practiced. These media include any material that provides three terminal switches (excluding bulk electrode) such as gallium arsenide, Bipolar, ECL, NMOS, strained or unstrained Silicon-On-Insulator (SOI) where the insulator may be oxide or nitride or carbide of a combination of these or Sapphire and BiCMOS. The claims therefore will describe the drain, source, and gate generically as a first current electrode, a second current electrode and a control electrode, respectively. 
   There may be intermediate structure (such as a buffer) or signals between two illustrated structures or within a structure (such as a conductor) that is illustrated as being continuous. The borders of the boxes in the figures are for illustrative purposes and not intended to be restrictive. 
   If the specification states a component, feature, structure, or characteristic “may”, “might”, or “could” be included, that particular component, feature, structure, or characteristic is not required to be included. Reference in the specification to “some embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments, of the invention. The various appearances “some embodiments” are not necessarily all referring to the same embodiments. 
   The various embodiments have described the periodic clock signal as being low or high during precharge, depending on the example. However, the logic could be changed so that periodic clock signal is in the opposite state during the precharge phase. A corresponding source follower configuration is another example. Additional keeper transistors may be included in various circuits. 
   The various transistors may be sized as desired and the timing signals may be adjusted to achieve desired results with a compromise between delay, power consumption, area, glitch size, leakage and the like. The transistors may be forward biased, zero biased, or reverse biased, and different transistors may have different biases and/or different threshold voltages due to gate to body connections with voltages below the forward-bias voltage of Silicon and the like and/or different threshold voltages as a result of selective implant and the timing signals may be adjusted to achieve desired results with a compromise between delay, power consumption, area, glitch size, leakage and the like 
   Those skilled in the art having the benefit of this disclosure will appreciate that many other variations from the foregoing description and drawings may be made within the scope of the present invention. Accordingly, it is the claims including any amendments thereto that define the scope of the invention.