Abstract:
Methods are described to prevent the inherent latchup problem of CMOS transistors in the sub-quarter micron range. Latchup is avoided by eliminating the low resistance between the V dd  and V ss  power rails caused by the latchup of parasitic and complementary bipolar transistor structure that are present in CMOS devices. These goals have been achieved without the use of guard rings by using a deep n-well to disconnect the pnp collector to npn base connection of two parasitic bipolar transistors, and by using a buried p-well to disconnect the npn collector to pnp base connection of those same two parasitic transistors. Further, the deep n-well is shorted to a supply voltage V dd , and the buried p-well is shorted to a reference voltage V ss  via both the P substrate and a P +  ground tab. The proposed methods do not require additional mask or processes.

Description:
RELATED PATENT APPLICATION 
     OTP (OPEN TRIGGER PATH) LATCHUP SCHEME USING BURIED-DIODE FOR SUB-QUARTER MICRON TRANSISTORS, title filing date: Oct. 30, 1998, Ser. No. 09/182,760 assigned to a common assignee, now U.S. Pat. No. 6,054,344, issued on Apr. 25, 2000. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to methods of producing integrated circuits on a semiconductor wafer, and more particularly to methods of fabricating complementary metal oxide semiconductor (CMOS) transistors without causing latchup. 
     2. Description of the Related Art 
     Latchup is a phenomenon of CMOS circuits and is well described by S. Wolf in  Silicon Processing for the VLSI Era,  Volume 2, by Lattice Press, copyright 1990, 6.4 LATCHUP IN CMOS, page 400: “A major problem in CMOS circuits is the inherent, self-destructive phenomenon known as latchup. Latchup is a phenomenon that establishes a very low-resistance path between the V DD  and V SS  power lines, allowing large currents to flow through the circuit. This can cause the circuit to cease functioning or even to destroy itself (due to heat damage caused by high power dissipation). 
     The susceptibility to latchup arises from the presence of complementary parasitic bipolar transistor structures, which result from the fabrication of the complementary MOS devices in CMOS structures. Since they are in close proximity to one another, the complementary bipolar structures can interact electrically to form device structures which behave like pnpn diodes.” 
     FIG. 1 shows a cross-sectional view of a p-well CMOS inverter with input V in , output V out , supply voltage (+)V dd , and reference voltage (−)V ss . The n-channel (NMOS) transistor is in the p-well. Q 1  is the lateral pnp parasitic transistor structure and Q 2  is the vertical npn parasitic transistor structure which results from the arrangement of NMOS and p-channel (PMOS) transistors. The lateral transistor Q 1  comprises the source S of the PMOS transistor (emitter), the n-substrate (base), and the p-well (collector). The vertical transistor Q 2  comprises the source S of the NMOS transistor (emitter), the p-well (base), and the n-substrate (collector). The region of each terminal is identified by a circle with an “n” or a “p”. Substrate current flows from (+)V dd  through the n-substrate, having a resistance R sub , to the collector of Q 2 . P-well current flows from the collector of Q 1  through the p-well, having resistance R p-well , to (−)V ss . 
     FIG. 2, is an equivalent circuit diagram of the parasitic transistors of FIG.  1 . Again the region of each transistor terminal is identified by a circle with an “n” or a “p”. In this circuit the base of each transistor is connected to the collector of the other transistor. Inspection of FIG. 2 shows that this circuit is the equivalent of a parasitic pnpn diode (from emitter of Q 1  to emitter of Q 2 ). A pnpn diode below a certain “trigger” voltage acts as a high impedance, but when biased beyond that “trigger” voltage will act as a low impedance device similar to a forward biased diode. This results in a current that depends on R sub  and R p-well  and can be destructive to the CMOS circuit. 
     Clearly, latchup is not a new problem, however, it is becoming much more severe as devices shrink to quarter and sub-quarter micron dimensions, because of the reduced well depth and inter-well spacing. The method of providing a guard ring only stabilizes the potential on the surface and, hence, is not efficient in preventing latchup in the bulk of the semiconductor. Latchup can be avoided by isolating n-wells from p-wells at the cost of consuming more silicon real estate. Quoting from S. Wolf in  Silicon Processing for the VLSI Era,  Volume 3, by Lattice Press, copyright 1995, 6.6 CMOS ISOLATION TECHNOLOGY, page 374: 
     “The large area penalty of p-channel-to-n-channel device isolation is the most important reason why CMOS technologies using conventional isolation methods cannot achieve as high a packing density as NMOS. Furthermore, while new techniques such as epitaxy greatly reduce latchup susceptibility as CMOS is scaled down, they generally do not suppress leakage currents in the parasitic MOS structures. Hence, the layout spacing between an n-channel and a p-channel device may be limited by isolation failure rather than by latchup.” 
     A large number of workers in the field have tackled the problem and found solutions which are suitable to one application or another, but the problem of latchup keeps on surfacing as transistor dimensions decrease in both the horizontal and vertical dimension. 
     U.S. Pat. No. 5,397,734 (Iguchi et al.) shows a method for fabrication a triple well construction. 
     U.S. Pat. No. 5,453,397 (Ema et al.) discloses a method capable of isolating fine pattern elements using LOCOS. 
     U.S. Pat. No. 5,470,766 (Lien) teaches a triple well with a p-region under FOX isolation regions. Lien addresses latch-up immunity for PMOS FETs. 
     U.S. Pat. No. 5,595,925 (Chen et al.) describes another triple well structure. 
     U.S. Pat. No. 5,604,150 (Mehrad) discloses a triple-well structure, where the channel-stop impurity is implanted using multiple doses at different energies. 
     U.S. Pat. No. 5,702,988 (Liang) teaches a method of forming a triple-well structure having n-well, p-well, and p-well in n-well regions. 
     None of the above-cited examples of the related art provide the combination of shallow trench isolation (STI) structures with a buried p-well, tieing the buried p-well to ground, and the deep n-well to Vdd to prevent latchup in deep sub-quarter micron technology. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide methods to prevent the inherent latchup problem of CMOS circuits by eliminating the low resistance between the Vdd and Vss power rails caused by the latchup of parasitic, complementary bipolar transistors which are present in CMOS devices. 
     Another object of the present invention is to eliminate the use of guard rings and their concomitant penalty in silicon real estate. 
     A further object of the present invention is to provide the above benefits without adding additional masks or processes. 
     A yet further object of the present invention is to provide the above benefits for sub-quarter micron transistors. 
     These objects have been achieved by using a deep n-well to disconnect the pnp collector to npn base connection of two parasitic bipolar transistors, and by using a buried p-well to disconnect the npn collector to pnp base connection of those same two parasitic transistors. Furthermore, the deep n-well is shorted to a supply voltage V dd , and the buried p-well is shorted to a reference voltage V ss  via both the P substrate and a P +  ground tab. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a cross-sectional view of a p-well CMOS inverter of conventional design of the prior art with parasitic bipolar transistors shown schematically. 
     FIG. 2 is an equivalent circuit diagram of the parasitic bipolar transistors of FIG.  1 . 
     FIGS. 3 through 6 are cross-sectional views of a process sequence of fabricating a CMOS semiconductor device according to the embodiment of the present invention. 
     FIG. 7 is a view of the cross-section  7 — 7  of FIG.  6 . 
     FIG. 8 is an equivalent circuit diagram of the parasitic bipolar transistors and of the four diodes of the CMOS transistor structure of FIG.  6 . 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring now to FIGS. 3 to  7 , we begin a description of the method of preventing latchup in complementary metal-oxide semiconductor (CMOS) transistors by opening the latchup path. FIG. 3 illustrates forming an n-well  106  and a deep n-well  108  on a p-substrate  102  of a semiconductor wafer  100 , where the deep n-well is touching the n-well, etching shallow trench isolation (STI) structure  112 ,  114 , and  116  to isolate n-well  106 , deep n-well  108 , and yet-to-be-formed p-well  120 . STI structure  112  is shown straddling the n-well and the deep n-well. 
     In FIG. 4, a p-well  120  is formed within deep n-well  108 , and a buried p-well  122  is formed below STI structure  112 . All three STI structures are filled with oxide in FIG. 5, PMOS transistors are created in n-well  106 , and NMOS transistors are created in p-well  120 . Next follow in FIG. 6 the implanting of an n +  region  144  in deep n-well  108 , and in FIG. 7, the implanting of a p +  ground tab  146  in STI structure  112  and contacting it with buried p-well  122 . See FIG. 7 for a cross-sectional side view of tab  146 , STI structure  112 , buried p-well  122 , and p-substrate  102 . Referring once more to FIG. 6, the method continues with connecting n +  region  144  to a supply voltage V dd , and connecting p +  ground tab  146  to a reference voltage V ss  (also see FIG.  7 ). 
     We now describe in FIG. 8 the equivalent circuit diagram of the CMOS structure of FIG.  6 . FIG. 8 has similarities with FIG. 2 of the prior art, except that diodes  82  to  85  have been added. Diodes  82  and  83  are joined at their cathodes (n-region) and tied to supply voltage V dd . Diodes  84  and  85  are joined at their anodes (p-region) and tied to reference voltage V ss . Both diode pairs are thus back-biased, i.e., not conducting. Diodes  82  and  83  represent the deep-well  108  and diodes  84  and  85  represent buried p-well  122 . By introducing deep n-well  108  and connecting it via n +  region  144  to supply voltage V dd , the junction from p-well  120  to deep n-well  108  (equal to diode  82 ) and the junction from buried p-well  122  to deep n-well  108  (equal to diode  83 ) act both as reverse biased diodes, and thus the connection (trigger path) between the base of parasitic transistor Q 2  and the collector of parasitic transistor Q 1  is opened. Similarly by introducing buried p-well  122  and connecting it to reference voltage V ss  via p +  ground tab  146  and by its contact with p-substrate  102 , the junction from buried p-well  122  to deep n-well  108  (equal to diode  84 ) and the junction from buried p-well  122  to n-well  106  (equal to diode  85 ) act both as reversed biased diodes, and thus the connection (trigger path) between the collector of parasitic transistor Q 2  and the base of parasitic transistor Q 1  is opened. By opening both trigger paths the latchup between Q 1  and Q 2  is eliminated. In addition since the p-region of diode  83  is connected to the reference voltage V ss , resistor R p-well  is effectively shorted, thereby tying the collector of Q 1  to V ss  as well. 
     Referring once again to FIG. 3, the method for manufacturing the present invention of preventing latchup in complementary metal-oxide semiconductor (CMOS) transistors begins with providing a semiconductor wafer  100  having a p-substrate  102 . Providing a photoresist  104  (of thickness B) on top of p-substrate  102 , and forming an n-well  106  (of thickness C) under photoresist  104  and forming a deep n-well  108  (of thickness A) in p-substrate  102  by implanting arsenic  110  in p-substrate  102 , where deep n-well  108  is formed adjacent to n-well  106 . N-well  106  and deep n-well  108  may also be implanted using phosphorus instead of arsenic  110 . N-wells  106  and  108  are (can be) implanted simultaneously, with their junction depth difference A−C equal to photoresist  104  thickness B. 
     The dose for arsenic and phosphorus ranges from 1×10 11  to 1×10 13  atoms/cm 2 . The implant energy for arsenic and phosphorus ranges from 80 to 300 keV. Next are etched a first shallow trench isolation (STI) structure  112 , straddling n-well  106  and deep n-well  108 , a second STI structure  114 , located within n-well  106 , and a third STI structure  116 , located within deep n-well  108 . 
     Referring now to FIG. 4, the method continues by covering semiconductor  100  with a second photoresist  118 , etching away second photoresist  118  from a to-be-formed p-well  120  and first and third STI structures  112  and  116 . Next follows the forming of p-well  120  (of thickness D) within deep n-well  108  and buried p-well  122  underneath first STI structure  112  by implanting boron  124 . Boron difluoride BF 2  may also be used for implanting the p-well  120  and buried p-well  122  instead of boron  124 . The dose for boron and boron difluoride ranges from 1×10 12  to 1×10 14  atoms/cm 2 . The implant energy for boron and boron difluoride ranges from 30 to 100 keV. 
     We continue the method with FIG. 5, by filling STI structures  112 ,  114 , and  116  with oxide, where STI  112  isolates deep n-well  108  and n-well  106 , where STI  114  isolates n-well  106  from other structure (not shown), and where STI  116  isolates p-well  120  from other structures (not shown), 
     adjusting an n-channel (NMOS) voltage threshold by ion implantation in selected areas of p-well  120 , 
     adjusting a p-channel (PMOS) voltage threshold by ion implantation in selected areas of n-well  106 , 
     growing a first set of gate oxide layers  126  in those selected areas of p-well  120 , 
     growing, simultaneously with the previous step, a second set of gate oxide layers  128  in those selected areas of n-well  106 , 
     forming an n +  polysilicon gate structure  130  on top of each of the first set of gate oxide layers  126 , 
     forming a p +  polysilicon gate structure  132  on top of each of the second set of gate oxide layers  128 , 
     implanting lightly doped n-drains (Nldd)  134  and  135  to either side of the n +  polysilicon gate structure  130 , 
     implanting lightly doped p-drains (Pldd)  136  and  137  to either side of the p +  polysilicon gate structure  132 , and 
     forming sidewall spacers  138  to either side of n +   130  and p +   132  polysilicon gate structures. 
     The method continues with FIG. 6 by implanting n +  drains and n +  sources  140  to either side of the n +  polysilicon gate structures  130 , 
     implanting, simultaneously with the previous step, an n +  region  144  in deep n-well  108 , 
     implanting p +  drains and p +  sources  142  to either side of the p +  polysilicon gate structures  132 , 
     and referring to FIG. 74 implanting, simultaneously with the previous step, a p +  ground tab  146  in the first STI structure  112 , where the p +  ground tab  146  contacts the buried p-well  122 , 
     connecting n +  region  144  to supply voltage V dd , and 
     connecting p +  ground tab  146  to reference voltage V ss . 
     Referring to FIG. 3, the thickness of dee p n-well, indicated by letter “A”, equals the combined thickness of photoresist  104 , indicated by letter “B” and n-well  106 , indicated by letter “C”. 
     Referring to FIG. 4, p-well  120  terminates under the third STI structure  116 , since structure  116  isolates p-well  120  from some other structure (not shown) . The thickness of p-well  120 , indicated by letter “D” equals the thickness of buried p-well  122 , indicated by letter “E”. The buried p-well  122  is in contact with the first STI layer  112 , n-well  106 , deep n-well  108 , and p-substrate  102 . 
     Referring to FIG. 5, nldd source  134  abuts against the third STI structure  116 , pldd drain  137  abuts against the first STI structure  112 , and pldd source  136  abuts against the second STI structure  114 . 
     Referring to FIGS. 6, the junction from p-well  120  to deep n-well  108  acts as a reverse biased diode since n-well  108  is biased at V dd . The junction from buried p-well  122  to deep n-well  108  acts as a reverse biased diode since n-well  108  is biased at V dd . The junction from buried p-well  122  to deep n-well  108  acts as a reverse biased diode since buried p-well  122  is biased at V ss . The junction from buried p-well  122  to n-well  106  acts as a reverse biased diode since buried p-well  108  is biased at V ss . Buried p-well  122  is connected to reference voltage V ss  also through p-substrate  102 . 
     The thickness of p-well  120  and buried p-well  122  ranges from 50 to 1000 nm. The deep n-well concentration ranges from 1×10 16  to 1×10 18  atoms/cm 3 . The buried p-well concentration ranges from 1×10 16  to 5×10 18  atoms/cm 2 . The depth of the shallow trench isolation (STI) structures ranges from 50 to 1000 nm. 
     The method of the present invention can claim the following advantages: 
     Both npn and pnp base current sources are eliminated by the reverse biased diodes, i.e., not latchup problem, 
     The use of guard rings is avoided, 
     Increased packing density, saving significant silicon real estate, 
     No additional masks are required, 
     No additional processes are required, 
     Lowered cost of manufacturing product. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.