Abstract:
In a lighting console which provides outputs to dimmers which include master controls for at least two scenes and channel controls for each of a plurality of channels with the channel controls including at least a first and second scene preset potentiometer, the channel controls and master controls cooperating to allow presetting, and which also includes a buss, with one of the preset potentiometers for each of a plurality of the channels connected to the buss and an output from the master controls being used through suitable amplifiers to drive the buss, a plurality of nondestructive current limiting fault isolating devices are provided for each scene, each connected between the master and at least one of the preset potentiometers for that scene. As a result, the effects of a fault causing abnormal currents to flow which develops after the fault isolating means will not disrupt the operation of channel potentiometers connected to other fault isolating means. In addition, the console permits the separation of the assignment selection of potentiometers and the assignment indication of that selection. The console also includes distributed multiplexing devices which reduces the back plane wiring requirements in the console.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to theater lighting in general and more particularly to a lighting console which provides increased capability of control, increased reliability, increased serviceability, and increased economy of interfacing manual and memory capabilities, particularly in portable use. 
     In the area of traditional performance lighting, separate manual consoles and memory consoles have been developed. For a background in the manual multi-scene console, reference can be made to U.S. Pat. No. 3,946,273. Descriptions of computer-based memory systems are well established in the patent art. 
     While each type has proved useful in certain applications, neither has been found completely satisfactory for the many applications in which both the adaptability provided by manual capability and some form of preset storage are both required. As a result, these applications have required the use of either both a manual console and a separate memory console and a separate memory console, at considerable expense and inconvenience to the operator, or of a new class of hybrid manual/memory console providing both multi-scene manual capability and increasingly elaborate memory and effects subsystems. Such consoles, which are based on traditional manual console design, have problems: 
     The number of channels to be ccntrolled in the manual scenes is so large that extensive mastering capabilities are required with a consequently large number of possible master assignments for each channel&#39;s potentiometers. No satisfactory control for making that assignment which satisfies all of the necessary electronic and human factors criteria is currently known in the art. 
     These manual sections must be interfaced increasingly with electronic storage systems which require and produce serial data systems which require and produce serial data streams. To date, parallel/serial conversion subsystems have been installed, requiring considerable additional interconnecting wiring. 
     The electronic complexity of such consoles; the amount of interconnecting wiring; and the degree to which various functions for a single channel are distributed in many different locations within the console have made such consoles less than fully reliable and very difficult to troubleshoot. 
     Furthermore, in addition to the need for a console which is reliable, particularly when transported with a touring production, there is a need for flexibility in console design. The ideal console should be as large or small as needed for the application without requiring a major electronic redesign and should give operational flexibility. 
     It is the object of the present invention to produce a console meeting all these needs. 
     SUMMARY OF THE INVENTION 
     The present invention provides a lighting console which achieves these and additional objects through number of unique features. 
     First, the console of the present invention, incorporates strip module construction. That is, each channel, i.e. discrete output to a light or group of lights to be separately controlled, is a separate plug-in module and contains the electronics associated with the channel. This gives ease of mechanical assembly, allows subsequent expansion, and permits the design of a console to any size requirement. Furthermore, field-servicing is quite simple, since repairs in the field can be accomplished by replacement of the whole strip module with a spare, and the failed strip module sent back to the shop for repair. 
     The second main feature of the present invention resides in distributed electronics. The strip modules, in addition to being mechanically separate, achieve a great degree of electrical independence. Through the use of various fault isolating techniques and separate control of power supply, a failure in one channel does not spread through the console, temporarily disabling or permanently damaging other channels or sections. This is accomplished by means of various fault-isolating resistors and amplifiers, the amplifiers being fed with their own power supply. This method of console construction gives the further advantage of permitting expansion, since the number of channels in a console is not limited to the power capabilities built into the master amplifiers as has been the case in the past. 
     The present console provides for the capability of assigning each channel potentiometer to any one of six modes: directly to the scene master; to the submasters, such as Sub A, Sub B, or Sub C; to an Independent buss, or to off. In the past, it had been the practice to combine the switching function and the indication of the selected mode in the same device. 
     However, no method satisfactory in all respects, has been achieved in the prior art. The present invention solves the master assignment problem by separating the indicating function and the switching function. Thus, in accordance with the present invention, each strip module; i.e. each channel, includes its own seven-segment LED displays driven through a logic device. By using this method, only one set of mode d can selection switches is required for the whole console along with only two &#34;Assign&#34; pushbuttons for each channel (assuming two scenes per channel and a separate assignment possible for each scene). With this arrangement, the operator selects the n desired assignment using the master mode selector switch bank, whereupon all the channel potentiometers to be assigned to that master are assigned by pressing their assign pushbuttons with an indication immediately thereof on associated LED displays. 
     The present invention also provides independent, control. The ability to switch a channel potentiometer to an r independent buss is an important feature in a lighting controller to simplify difficult cues and to speed an operator&#39;s response to the unexpected. Because of the speed with which it is generally necessary to enter independent, it is important ce that the method of doing so be fast and simple. In accordance with the present invention, independent control is provided for the potentiometers in each scene. It is entered by throwing a miniature switch located directly above the affected potentiometer. Furthermore, because of the manner in which the odes: independent control is implemented electronically, the normal, master assignment is unaffected. Simply restoring the independent control to its normal position returns the potentiometer to its normal assignment. It is also possible with the ce. present invention to change a potentiometer&#39;s assignment while in the independent mode. 
     Furthermore, the present console includes the ability to review the assignments of the channel potentiometers of the console and to display other data through what are known as &#34;show me&#34; buttons. 
     To determine which of the channel potentiometers is assigned to a given mode with particular speed, ease, and accuracy; it is simply necessary to select the appropriate mode on the master mode selector switch bank and then depress the &#34;show me&#34; button and the displays for all potentiometers assigned to other functions will go out. This allows the operator to immediately determine which potentiometers are assigned to that mode by simply noting which displays remain lit. Similarly, the capability is provided for locating, in the same manner, all of the channels in which independent has been selected and further includes the ability to review levels set in a memory system or other data. In the &#34;show me&#34; modes there is no effect on the actual assignment, this being only a display feature. 
     Also included in the console of the present invention are flash buttons. The flash button permits operation in four modes: safe or off; momentary flash of the channel to the level set by a central &#34;flash&#34; master potentiometer; electronically held, push-on/push-off action with a central reset button useful for setting up an additional &#34;preset&#34; at high speeds; and a &#34;kill&#34; mode in which depresing a channel&#39;s flash button flashes it to the level of the flash master while automatically blacking out all other channels. 
     The console of the present invention also provides additional features. Included is a channel kill switch which disables that channel&#39;s potentiometers and flash button. An auxiliary kill switch disables inputs tc the module from sources outside of it, such as the console&#39;s memory and effects sections and/or outboard units. This auxiliary kill switch may be used to temporarily delete a channel from stored presets without altering the matrix or memory. An indication through a light-emitting diode is provided when one or both of the kill switches is engaged. In addition, displays are provided to indicate whether the channel is being driven from inputs on the module or from off the module. In addition, there is an indication of the availability of inputs from an external memory board or the like. 
     In this last regard, the console of the present invention is adapted to interface with onboard or offboard matrix, memory, and effects units. In accordance with the present invention, each strip module has four inputs for levels originating outside the module, whether elsewhere in the console of the present invention or from outboard units. The console of the present invention has further distributed the components necessary for serial conversion to the strip modules, allowing the console of the present invention to both produce and accept serial data streams for use with onboard or outboard memory and effects units and for connection to the dimmers over a serial link, without the traditional necessity for a separate conversion subsystem and the interconnect wiring required to it, with considerable savings in cost and increase in reliability. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is an overall block diagram of the console of the present invention. 
     FIG. 1A is a more detailed block diagram of the master section of the console of the present invention. 
     FIG. 1B is a more detailed block diagram of a single channel strip module used in the console of the present invention. 
     FIGS. 2A and 2B are a detailed schematic-block diagram of a single channel in the console of the present invention. 
     FIG. 3 is a plan view of a portion of the console of the present invention. 
     FIG. 3A is a side view of a portion of the console. 
     FIG. 4 is a schematic diagram illustrating a typical prior art arrangement in consoles of this nature. 
     FIG. 5 is a similar drawing illustrating the manner in which fault isolation is achieved by the present invention. 
     FIG. 6 is a diagram showing the manner in which encoding and decoding of levels is done in a channel. 
     FIG. 7 illustrates a first embodiment of address decoder of the present invention. 
     FIGS. 8 and 8A illustrate a second embodiment of address decoder according to the present invention. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1 is an overall block diagram of the lighting control system of the present invention. At the right of the figure are shown a plurality of n lights 11 to be controlled. Typically, the device according to the present invention might have 64 channels, i.e., control 64 separate lights or groups of lights 11. For each of the lights 11, a dimmer 13 of conventional design is provided. Dimmers 13 receive AC power and provide it in a controlled manner, in accordance with the control input on a line 15, to their associated lights 11. The signal on line 15 is a DC voltage which controls an electronic circuit which in turn controls a triac, SCR or the like. The individual control signals on lines 15 are developed in individual control strip modules 17 on a lighting console 19, one such strip being provided for each channel. As will be seen in more detail below, each strip, in addition to other functions, permits selecting for each of two scenes, scene I and scene II, any one of five master, submaster control inputs developed in a master control portion 21. Master control 21 which will typically include a crossfader for crossfading between scenes I and II. These control outputs will, for example, be provided to scene I and scene II submaster potentiometers, the outputs of which are provided as the inputs to the control strips 17. Naturally, buffering and amplification as necessary will be provided. 
     FIGS. 1A and 1B are more detailed block diagrams of the lighting control system of the present invention. FIG. 1A illustrates the basic units contained in the master control 21 of FIG. 1. FIG. 1B illustrates the basic blocks contained in one control strip 17 of FIG. 1. 
     Referring now to FIG. 1A, the control signal is first generated from the output of a reference DC supply 101. The reference DC supply provides this output to a potentiometer 102 which is the grand master potentiometer. Its output is coupled through a grand master blackout switch 103 to a crossfader 105. It is also coupled to an amplifier 107 which provides an output on what is known as an independent bus 109. The crossfader 105, which comprises a pair of scene master potentiometers 111 and 113, provides outputs for the scenes I and II. One output for scene I is provided directly into an amplifier 115. Similarly one output from scene II is provided into an amplifier 117. Outputs are also provided through submaster A and B potentiometers 119 and 121 to amplifiers 123 and 125 for scene I and through submaster A and B potentiometers 127 and 129 to amplifiers 131 and 133 for scene II. Although only two potentiometers are shown for each scene, at this, the submaster, level, a greater number may be provided. 
     The present invention also includes encoding logic 135 accepting inputs from the master mode selector switch bank 137, 139 and 141; and providing a parallel output representing the mode selected on buss 143. 
     The system of the present invention is also usable with presently existing electronic memory systems. These may be full feature stand-alone memory boards well known in this art, or the simpler more specialized sutstitutes which are coming into increasing use. Memory units of this type produce serial output which provides all channel intensity data. When used with traditional consoles, serial to parallel conversion subsystems are required. The discrete outputs of the systems are connected with combining diodes at the channels using individual conductors. To be able to also provide this kind of information but without a large number of interconnecting wires which would otherwise be necessary is desirable. And, the arrangement of the present invention provides such. Thus, as illustrated by FIG. 1A the master control also includes a serial output matrix or memory unit 145, serial output chaser 147, and address generator 149 and provisions for coupling in an external signal on a line 151. In addition, the output from the grand master is coupled through a potentiometer 153 to an attenuator signal processor 155 providing its output on a line 157. Serial data from the channels is provided back on a line 159 which can be multiplexed to dimmers, for example, and is also fed back into the matrix or memory unit to permit storing information which is set up on the individual channels. 
     Unit 149 is an address generator providing parallel information on the address buss 161. This address information is used to synchronize the operation of the serial encoding and decoding circuitry distributed throughout the console. The address generator&#39;s output is further used to synchronize the operation of the matrix or memory unit 145 and the chase/effects unit 147 so that their serial analog outputs on lines 163 and 165 contain the correct channel&#39;s level during its sample interval. On one of these lines will be a series of levels such as shown by the waveform of line 169. Each sample interval is associated with a particular channel and the value on the serial line during that interval corresponds to the desired level for that channel. The serial outputs of the memory or matrix 145, the chase unit 147, and the input on line 151 from an external source of serially-encoded level information are combined through diodes in block 167. 
     Inputs from these sources are provided to the channel modules by means of bus 169 and the address information is distributed on bus 161 and may be treated as an additional scene or scenes. In the event that an external system is connected with the console by means of line 151 then the external system must be synchronized to the console&#39;s address generator 149 or the console&#39;s address buss 161 connected to that of the external system. 
     It will be apparent that the functions of address generation and master mode selection can also be accomplished by means of a microprocessor. Provision is made for external address information on a bus 162 which will be coupled through to bus 161 to synchronize with the analog information on line 151. An additional scene or scenes can be provided by means of the serial information just described and provided as outputs on line 169 and addresses on bus 161. 
     FIG. 1B shows how these various outputs are connected in each of the plurality of channels 17. For each of the two scenes, a direct and two submaster inputs are provided as inputs to switches 171 and 173 respectively. These switches are controlled by respective switching logic 175 and 177 receiving inputs from a master memory device 179 which in turn receives its input from the bus 143. The master memory 179 provides outputs on buses 181 and 183 to switching logic 177 and 175. It also provides an output on bus 185 to display logic 187 which drives displays 189 and 191 displaying respectively the selection for each of the two scenes. The output from switches 171 and 173 is coupled to switches 193 and 194. These switches respectively permit switching between one of the submasters or the direct crossfader output and the independent bus 109. The signal, whether it be from the independent bus or one of the master or submaster controls, is then coupled through an amplifier 195 or 197 to a respective scene preset pot (potentiometer) 199 or 201. These outputs are combined through diodes 203 and 205 into an output amplifier 207 which provides its output on line 209 to dimmers. This output is also coupled through a switch 211, enabled by an address decoder 213 coupled to the address bus 161, to provide serial analog output information on line 159 when that particular channel is being addressed by the address bus 161, permitting feedback to the matrix or memory unit 145 of FIG. 1A and/or serial dimmer control. 
     The serial analog input data on line 169 is sampled and held in a sample and hold device 215 which is enabled by the same output from address decoder 213. The attenuator control signal on line 157 is coupled into an attenuator 217, the output of which is coupled through a diode 219 to the amplifier 207. Furthermore, it is indicated that there may be a source 221 of other signals coupled through a diode 223 to amplifier 207. In addition, the address decoder output may be used to enable other digital logic 225. 
     In general, operation is as follows in setting up the assignment of channel potentiometers on the console. The first mode, for example, direct, might be selected using the master mode assignment switch bank 137, 139, 141 and that mode&#39;s designation encoded by the logic 135. Then all of the channels it is desired to connect to direct are selected by pressing the appropriate assign switches which will cause their master switches 175 and 177 to set their switches 171 and 173 to line 115a and 117a as required and keep them there. The same is done for the submasters A and B for example. When this is completed, each of the channel potentiometers will have been assigned to a particular master bus. In addition, display logic will display the assignment which has been selected. For example, in FIG. 1B, it is shown that scene I has been assigned to submaster A and scene II to submaster B. Subsequently, then as the crossfader, and subscene masters are operated, the proper channels will follow as desired. 
     In addition, when it is desired to input information of a serial nature, addresses are generated in serial, one address corresponding to each channel. This occurs on the address bus 161. At the same time, an analog level is coupled out to line 169, a separate level for each channel. These levels appear on line 169 of all channels at the input to the sample and hold circuits 215. However, only when the address of that channel is decoded by address decoder 213 does that channel sample its proper level to be provided as an output through the attenuator 217 to the output amplifier 207. The attenuation control signal on line 157 can be a pulse code modulated signal of the type described in U.S. Pat. No. 3,946,273. This will then be used to attenuate the signal output of the sample and hold circuit. Other types of attenuators can be used as will be seen below. 
     In FIG. 1B essentially all of the inputs are coupled through input resistors. The purpose of these resistors is to aid in fault isolation in a manner that will be seen below in connection with FIGS. 4 and 5. 
     In FIGS. 2A and 2B, which is a more detailed logic/schematic diagram of the channel electronics, the parts which are the same as those of FIG. 1B will be given the same reference numerals. The input previously described from the master controls including, for example, the independent input on line 109, the direct input on lines 115a and 117a, and the various submaster inputs are as before, with the exception that there are additional submaster inputs possible on lines 126a, 128a, 134a and 136a. These lines are inputs through input resistors, typically of 10K to analog switch modules 301 and 303, one switch being provided for each input. These correspond to the switches 171 and 173 of FIG. 1B. The output of the switch modules is coupled into the switches 193 and 194 which permit switching between the analog switch module outputs and the independent input. The respective outputs from switches 193 and 194 are coupled into the amplifiers 195 and 197. Each is coupled through an input resistor 305, typically 2.2K, with a resistor 307 provided to the ground, typically 100K. Each amplifier has negative feedback from its output to its inverting input through a feedback resistor 309, typically 10K, with a resistor to ground from the inverting input, typically 100K. Potentiometers 199 and 201 are typically 10K pots with an additional resistor 313 at the end of each coupling it to ground. These additional resistors have a low value, for example, of 390 ohms. The output amplifier 207 also has an input resistor 305, typically 2.2K, with a resistor 315 to ground, typically 200K. It has a feedback resistor 316, typically 2.2K. The output is coupled through a resistor 318, typically 10 ohms. 
     The junction between diodes 319 and 321 is coupled to +15 volts from a separate power supply 323 which includes a regulator 325, typically a 78L15 with capacitors 327 and 329 on each side in conventional fashion. This regulates the unregulated 18 volts to +15 volts. Similarly, a regulator 331 in a power supply 335 regulates 8 volts to +5 volts. Again capacitors 337 and 339 are provided. Amplifiers 195 and 197 which may be a dual operational amplifier pack are supplied from the regulated +15 voltage, i.e. they operate across +15 volts and ground. Similarly, the amplifier 207 is coupled across the regulated 15 volt supply and ground. 
     The input to the amplifier 207 from amplifiers 195 and 197, is through diodes 203 and 205. These inputs are coupled through a switch 341 designated a channel-kill switch. Channel-kill switch has another pole coupled through an LED 343 to the collector of a transistor 345 with an emitter resistor 347 to ground and a base resistor 349 which is coupled through diodes 351 and 353 to the outputs of the potentiometers 199 and 201 respectively. The movable contact of a second pole 341a of switch 341 is coupled to the 18 volt supply and thus provides power to the LED 343 which will be turned on so long as the channel-kill switch is not in the kill position and there is some output from one of the two scenes to turn on transistor 345. When switch 341a is in the kill position, the 18 volts is supplied through a resistor 355 to another LED 357 to indicate that position. LED 357 will also be lit if a switch 359 having its movable contact coupled to +18 volts is in a position indicating an auxiliary kill condition. The function of the auxiliary kill switch will be described in more detail below. 
     Which of the switches of the analog switch modules 301 and 303 are operated is determined by latch circuits 501 and 503. These latch circuits receive inputs from data bus 143. Each has three inputs labelled a, b, c. Similarly, there are outputs a, b and c coupled back respectively to the analog switch modules 301 and 303. Each of the latches 501 and 503 also has a clock input coupled respectively to an assign I switch 505 and an assign II switch 507. Pressing the assign I or assign II switches will cause the latch to set with whatever data is on the data bus 143 and continue supplying that data to the analog switches 301 or 303 until a change is made. 
     The outputs on lines a, b and c of each of the two latches 501 and 503 are also coupled through buffer amplifiers 509 to a field programmable logic array 511 which provides a plurality of seven-segment outputs utilized to drive LED displays 189 and 191. Only a single seven-segment output bus 513 coupled through resistors, typically 180 ohms, to the seven-segment displays is provided. The common input to each of the displays is supplied by a transistor, display 189 being supplied from transistor 515 and display 191 from transistor 516. Transistors 515 and 516 have their emitters coupled to the +5 volt supply. Each has a diode 517 between its base and emitter. The base of transistor 515 is coupled through a resistor 518 typically 7.5K to the Q input of a D-type flip-flop. Similarly, the base input of transistor 516 is coupled through an input resistor 519 to the Q output of D-type flip-flop 521. The D input of flip-flop 521 is coupled to its Q output and its clock input is coupled to an oscillator 523 comprising an amplifier 525 with a capacitor 527 coupled to its input terminal and a feedback resistor 529. The RC time constant of the capacitor 527 and resistor 529 which are respectively 0.05 microfarad and 100K ohms establish the frequency of oscillation. This frequency is chosen high enough so that the flicker in the displays 189 and 191 will not be perceptible to the eye. Thus, the output of the latches, in addition to being provided to the switches 301 and 303, is displayed on displays 189 and 191. 
     The logic array 511 has additional inputs. The Q output of flip-flop 521 is coupled through a buffer amplifier or inverter 531 to an input of the logic. This is necessary in order that as the two displays are switched by the transistors 515 and 516, the proper seven-segment data for the selected display is being provided at the output. In addition, there are three inputs each through a resistor 533 which carry out various control functions. These inputs are respectively what is called &#34;meter enable&#34; input on line 535, a &#34;show&#34; input on line 537 and a &#34;blink&#34; input on line 539. A clock signal for example at 1 Hz is provided on this input, line 539. In addition, the second pole of the individual switches 193 and 194 indicated respectively as 193a and 194a which couple 5 volts into the logic array 511 are also provided. Thus, when &#34;independent&#34; is selected an indication of this is provided as an input to the custom logic array. 
     An additional latch 541 is provided for storing and displaying additional data. For example, the data bus can be encoded to indicate a signal level which can be latched into latch 541 in response to a signal on line 543 from an inverter 545, the inverter being driven by input called &#34;select&#34; on line 547. This input is the output of the address decoder 213. When the &#34;meter enable&#34; signal is provided on line 535, rather than displaying the selected information, the value stored in the latch 541 will be provided. 
     In addition to the scene I and scene II controls, the embodiment of FIG. 2 also permits control by an auxiliary input on line 551, there being parallel inputs to each unit, a serial or addressed auxiliary input similar to what was shown on line 169 of FIG. 1B, and similarly a scene III parallel inputs on line 555 and a scene III serial input on line 169. In addition, there is the attenuation control input on line 157. 
     The auxiliary input on line 551 is coupled through an input resistor 557, typically a 1K resistor, and through a diode 559 and resistor 561, typically 15K, to the base of the transistor 563 having a resistor coupling its emitter to ground. Coupled in its collector path is an LED 567 having its anode coupled to the auxiliary kill switch 359. If the auxiliary kill switch is not in the kill position, and if there is a signal through diode 559, LED 567 will light. Similarly, the signal on line 555 is coupled through an input resistor 569, typically 1K, and a diode 571 and resistor 573 to the base of the transistor 575 similarly having a resistor, typically 1K, 577 coupling its emitter to ground with an LED 579 in its collector path also coupled to the auxiliary kill switch 359. Thus, if there is a signal on line 555, and if the auxiliary kill switch is not in the kill position, this LED will light. The signals on line 551 is also coupled through a diode 581 and another pole 359a of the auxiliary kill switch to the input resistor 305 of the output amplifier 207. Similarly, the input on line 555 is coupled through diode 583 and a switch 585 to auxiliary kill switch 359, thence to the output amplifier. Switch 585 is controlled by the signal line 157 through an input resistor 587 typically 10K. Switch 585 is an analog switch and is used for pulse width modulation of the incoming signal thereby attenuating the signal in the manner disclosed in the aforementioned U.S. Pat. No. 3,946,273. 
     When signals are provided on line 555 and 551 from a memory board or the like, a separate line is required for each channel. However it is also desirable to provide different levels to different channels on a single line. This is accomplished by means of sample and hold circuits 601 and 603 respectively, each sample and hold circuit includes an amplifier 605 having a negative feedback resistor 607 and an input resistor 609 with a capacitor 611 to grcund at the input to the input resistor 609. Each also includes an analog switch as its sample switch. Thus, there is shown a switch 613 for the sample and hold 601 and a switch 615 for the sample and hold 603. Switch 613 is coupled to line 553 through an input resistor 617, typically a 1K resistor. Similarly, switch 615 is coupled to line 69 through an input resistor 619, also typically 1K. the control input for the analog switches 613 and 615 is provided from the output of the address decoder 213 through an input resistor 621, typically 10K. With a signal on line 553 or line 163, when the address of the particular channel is detected by its address decoder, an output on line 547 occurs, closing the switches 613 and 615 and causing them to sample whatever is on line 553 and/or line 169. The switch then opens and that value remains stored. The outputs of the sample and hold circuits 601 and 603 are coupled in the same manner as the signals on lines 551 and 553. Thus, associated with the auxiliary sample and hold circuit 601 is a diode 559a coupling into the auxiliary LED indicator and a diode 581a coupling through the auxiliary kill switch 359a to the output. Similarly, diode 583a couples into the modulating switch 585 and diode 571a couples into the modulating switch 585 and diode 571a couples into the transistor 575 controlling LED 579. 
     The select output on line 547 is also coupled through a pair of inverters 621 and 622, a switch 623 having auxiliary contact 623a and a diode 625 to what is called the &#34;user defined output&#34; on line 627. This is a common bus shared by all channels and permits providing feedback information through the closure of switch 623. The auxiliary contact 623a is coupled to 18 volts and when closed couples the 18 volts through a resistor 629, typically 15K, to light an LED 631 indicating that it is closed. 
     Although the present embodiment is for a hardware device, it should be clear that many of the functions can also be performed with microprocessor. The present embodiment is also shown with level information distributed in serial analog form, although it will be clear that with the appropriate components, this information could be accepted, processed, and produced in digital form. Further, while the present embodiment shows the mode selected for a channel potentiometer stored at the module; it is clear that the mode selection could be recorded on a data carrier at a central location by either sampling the outputs of the channel latches or by deriving notice of assign switch closure by a method similar to the &#34;user defined switch&#34; 623 to create a duplicate record. This data carrier would allow the operator to recreate the control assignments for a given production by reading back the carrier into the console. Finally, it will be apparent that, when manufacturing volume permits, it will be desirable to replace the current, separate assign switches 505 and 507 with a mechanical, pressure, or capacitive switch integral with the window covering the displays in order to reduce panel area requirements and further improve operability. 
     Associated with each channel is what is called a flash or bump button 701. This is a switch capable of coupling either +15 volts or ground through an inverter 703 having a resistor 705, typically 10K, at its input with a capacitor 707, typically 0.01 F to ground. The output of the inverter 703 is the clock input to a D-type flip-flop 711. The Q output of flip-flop 711 is tied back to its D input. This means that absent any other signals, as it is clocked, it will change state at the clock rate. The Q output is coupled through a diode 713 to the junction of a resistor 715 and a base resistor 717 for a Darlington pair 719. Resistor 715 has its other end tied to ground. Typically resistor 715 is 100K and resistor 717 is 15K. Resistor 717 couples the output of the flip-flop 711 into Darlington pair 719 which drives an incandescent lamp 721 coupled to +24 volts, a current limiting resistor 723 also being provided in the path. The output at D-type flip-flop 711 is also an input to an analog switch 725, the output of which is coupled through diodes 727 and 729 to the transistor 345 for the channel LED and the channel kill switch 341 respectively. In addition, through diode 737, switch 701 directly drives switch 725 and Darlington pair 719. Switch 725 receives an input through an input resistor 731 from an input on line 733 designated the flash input. The flash input is a level to which the channel will be brought when the bump button is pressed to cause the circuit comprising inverter 703, resistor 705 and capacitor 707 to provide a debounced input to flip-flop 711 and directly to switch 725. The channel output will then receive a signal at the level of the flash input 733. Three possible modes of operation are possible. These are &#34;kill&#34;; &#34;momentary&#34; and &#34;alternate.&#34; By pressing switch on and off with flip-flop 711 held reset by a signal on an input line 739 B through resistor 741, typically 10 K, with a resistor 743, typically 100K, to ground, flashing is accomplished at the rate at which the switch is operated. In addition, there is a kill bus which is coupled through a diode 735 to the output of the inverter 703. This output can be used in the master section to &#34;kill&#34; all other channels but the one whose switch 701 is pressed, for example. When a reset signal is not present on line 739, alternate operation takes place. Each time switch 701 is pressed, flip-flop 711 changes state. 
     FIG. 3 is a plan view helpful in conjunction with FIG. 2 in understanding operation of the system. Shown are a plurality of strip modules 17, each containing all the circuits shown in FIG. 2. This modular construction adds flexibility to the system, permitting construction of the system with as many or as few channels as is desired. As illustrated by FIG. 3A, each module 17 has a board 900 with an edge connector 902. This plugs into a connector on a board 903 which is coupled to the master control and supplies all the signals shown as inputs to FIG. 2. The various controls discussed in connection with FIG. 2 are shown in FIG. 3. Thus, the preset potentiometers 199 and 201 which are typically sliding potentiometers for presetting scene I and scene II for the particular channel are shown. Also shown are the LED displays 189 and 191. The flash button, also referred to as the &#34;bump&#34; button, or switch 701 of FIG. 2 is also shown. The independent switches 193 and 194 are shown located directly below their respective seven-segment LED displays 189 and 191. 
     LED 579 indicating that a scene III input is present is visible at the top of the figure. LED 343 indicating a channel signal is present is located next to the channel kill switch 341. Similarly, the auxiliary LED 567 is located next to the auxiliary kill switch 359. The kill LED 357 is located between the two. 
     Also shown in FIG. 3 are some of the master controls. Shown are potentiometer controls 801 and 803 for controlling the voltage supplied respectively to the bump buttons 701, more particularly their lamps 721 seen in FIG. 3, and supplied to the various displays to control their brightness. Also shown are a series of push button switches corresponding generally to the switches 137, 139 and 141 of FIG. 1A. These switches include a direct switch 805, submaster A 807, submaster B 809, submaster C 811, and an off switch 813. These switches are electronically interlocked. The one of the switches selected is indicated on an LED display 815 and a corresponding output is provided on bus 143. In addition, there is a &#34;show me&#34; switch 817. This provides the output on line 537 of FIG. 2. There is a &#34;show me level&#34; switch 820 which corresponds to the meter enable line 535 of FIG. 2. There is a &#34;show me independent&#34; switch which also provides an output on 537 and also puts on bus 143 the address corresponding to independent. Finally, there are a pair of controls 823 and 825 which permit providing the various inputs flash, kill, and flash RS-modes on lines 733, 734 and 739 of FIG. 2 to control operation of the bump button 701. 
     In operation, when it is desired to set up the console, the operator presses one of the buttons 805, 807, 809 or 811. Pressing this button puts a corresponding output on the bus 143 which is provided to all of the three latches 501, 503 and 541 of FIG. 2. If a channel is to be assigned to that submaster, then the assign switch 505 or 507 for that channel is pressed storing that information in the associated latch and thereby controlling the analog switch. Once all the channels to be set up for direct are assigned by pressing their assign buttons 505 and/or 507, the next submaster is set in, for example A, and the process repeated for that, and then for B and C. At each of the channels, the potentiometers 199 and 201 are preset. The control assignment selected will appear on the respective display 189 or 191. When all selections have been made, one can press one of the buttons 805, 807, 809 and 811 and then press the &#34;show me&#34; button 817. This provides an input on the line 537 and causes the displays for all channels not assigned to the selected mode to go out. Those normally assigned to the selected mode but presently in independent will flash. Thus, if, as indicated on the LED display 815, submaster C is selected, all of the displays would go out except those which had selected C. 
     By throwing independent switch 193 or 194 it is possible to select independent rather than one of the submasters or the direct master control. Pushing the &#34;show independent&#34; will cause all of the channels except those assigned to independent to go out. Finally, pressing the &#34;show me level&#34; switch will cause the information latched in latch 541 to be displayed on the LED to show a level, for example, a level associated with scene III. Note that latch 541 is latched by a clock input from decoder 213. Thus, each channel can store separate level information in this latch. 
     Pushing one of the bump buttons 701 will cause the associated channel to be brought up immediately to the level set in on the flash bus 733. If there is no input on line 739, pressing the flash button will clock the flip-flop on causing it to latch and close the switch if the switch was off. It will, at the same time, feed this signal back through diode 735. The purpose of this, if &#34;kill&#34; is selected at the master section, is to kill all other channels. 
     Fault Isolation 
     As noted above, one of the important aspects of the system of the present invention is in the fault isolation which it provides. To understand the improvements in the fault isolation obtainable in accordance with the present invention, a typical prior art arrangement has been illustrated in FIG. 4. The illustrated embodiment is one in which there are two scenes with two master or submasters for each scene. However, in the simplest type of board, one would simply have a single scene master control, for example, master control 101. In the illustrated embodiment, this comprises a potentiometer 103, the output of which is amplified by an amplifier 105 receiving power from a power source 107. The output of amplifier 105 is placed on a bus 109 and feeds a set of potentiometers, one being provided for each channel, i.e. each light or group of lights. The simplest arrangement in the prior art consists of a potentiometer 111 coupled between this bus and ground the wiper of which provides an output on line 113 to a dimmer for that channel. The dimmer will be driven by the DC voltage produced at the master 101 attenuated by the setting of the channel potentiometer 111. Thus, the simplest type of system would consist of a master control 101 providing an output to a bus 109 with a plurality of potentiometers such as 111 providing outputs for the different channels. 
     However, in the illustrated embodiment, there is the possibility of an additional scene. Thus, there is also provided a potentiometer 103a providing its output to an amplifier 105a, this constituting another master control 101a. The output is provided to a bus 109a. Bus 109a through a switch 115a, to be described below, feeds a channel potentiometer 111a which has its other end connected to ground. In this case the wiper of the potentiometer provides an output line 113a which is coupled through a diode 117a to the final output on line 113c. Similarly, coupled to line 109c is a potentiometer 111b providing its output on line 113b through a diode 117b to the final output 113c. As indicated, the illustrated embodiment provides the possibility of two masters for each scene and thus there is also shown a master control 101b comprising potentiometer 103b and amplifier 105b associated with scene I, and another master 101c comprising potentiometer 103c and amplifier 105c associated with the scene II master. Switch 115a and a similar switch 115b permit selecting between one or the other of the scene I and scene II masters. 
     Also shown in FIG. 4 are additional controls for two more channels including switches 115c, 115d, 115e and 115f, potentiometers 111c-f, and diodes 117c-f. Also shown associated with the output 113e of the last channel are special input electronics 121. These combine special features having channel outputs through isolating diodes with the output of the two scene potentiometers. They can be the auxiliary or scene III inputs of FIG. 2. The last two channels having outputs on lines 113d and 113e are shown as having buffer amplifiers 123d and 123e associated therewith and each is shown as driving plurality of dimmers. 
     In the illustrated embodiment all of the amplifiers 105 and 105a-c and amplifiers 123d and 123e are fed from the same power supply 107. An examination of FIG. 4 should make it clear that the loss of one of the amplifiers 105a-c will result in the complete loss of that function to all channels. However, there are many kinds of faults, particularly short circuits in the channel level wiring attached to the buses 109 and 109a-c which can alter the load characteristics of the bus causing the amplifier to either temporarily disable due to current limiting or become permanently damaged. This can either result from faults in the switches 115a-115f in the potentiometers 111a-f, or wiring after the potentiometer when it is set at a high enough level to make the fault visible enough to the bus. Thus, there are shown on the drawing a number of black dots. Short circuits at these points can disable large parts of the console. These include a short at the output of the switch as shown by switch 115a, on the line leading to the switch as shown in connection with switch 115b, in the switch contact as shown by potentiometer 111d, which is set so high that there is very little resistance between the wiper and the amplifiers. Also, at the output of diode 117f the potentiometer of 111f of which is also at a high level a short can cause the massive failure. Also shown in connection with line 113c are two more black dots indicating that at either side of the connector leading to the dimmer a short circuit through diode 117b and potentiometer 111b can cause failure at the amplifier. 
     Other points on the diagram are shown by asterisks. These are essentially the amplifiers 105, 105a-c, 123d and 123e. Failure of these parts can also disable or cause failure in other sections of the console. For example, they can cause the power supply to current limit, thus affecting not only their own channel but other channels as well. 
     Thus, the present state of the art consoles are subject to serious failures which may be difficult to troubleshoot. 
     FIG. 5 illustrates the manner in which the present invention minimizes the effect of the faults. In this drawing, parts which are the same as those in FIG. 4 have been given the same reference numerals. In general, the present invention accomplishes fault isolation by means of three measures. The simplest of these is illustrated in connection with potentiometer 111. In series with the potentiometer a resistor 131 is provided Now, even with the potentiometer at its highest position, a short at line 113 will not result in a failure at amplifier 105. The value of resistor 131 must be very much lower than the impedance of the channel potentiometer. The master amplifier 105 must be capable of delivering a current which equals the normal operating current of the channel control times the number of channels plus allowance for the current draw of a faulted channel as limited by the resistor 131, times a number of channels to take into account plural faults. A failure occurring for example on the line 113 can be easily isolated and will be localized. 
     This same scheme is shown in connection with the potentiometers 111a and 111b in which case separate resistors 131a and b and 131c and d are provided. Because of this isolation, only if a fault actually occurs at the bus itself or on the side of the resistor connected to the bus will the failure propagate back to the master amplifier. 
     Although this arrangement can be used in many cases, the arrangement illustrated with the potentiometers 111c or 111e is preferred. In this case, buffer amplifiers 133a through 133d are provided. Buffer amplifiers 133a and b are connected directly to the buses 109b and 109a. The amplifiers 133c and 133d are connected through resistors 131e and 131f. The amplifiers provide additional isolation and furthermore relieve the power requirements on the master amplifier. The master amplifier need no longer drive all of the channel potentiometers. As a result a smaller, simpler, and less expensive and more reliable master amplifier can be used decreasing the chance of failure. Furthermore, added flexibility is provided with this design in that channels can be added afterwards since the master amplifier will still be capable of supplying additional channels each of which will have a high impedance amplifier at their input. In this arrangement, the power supply bus. The arrangement associated with potentiometers 111d and 111f avoids this. In these embodiments, the inputs to the switches 115d and 115f are coupled through resistors 131g through 131j. The outputs of the switches 113d and 113f are inputs to amplifiers 133e and 133f respectively. In this embodiment, the amplifiers rather than being supplied directly from the power supply bus are supplied from an isolated power supply bus 137 which in turn is supplied by a current limited supply 139. This may be simply a solid state voltage regulator with appropriate filtering capacitors. Now, a failure of amplifiers 133e and 133f will only affect their channel and will not propagate back to the power supply bus to affect the whole console. In FIG. 5, the same convention with respect to massive failures is indicated by a black dot and failure in amplifiers which may spread is indicated by an asterisk. A local failure in amplifier which will not spread is indicated by an open square, and a local failure otherwise by an open circle. With the last embodiment illustrated, it is apparent that the only failures which will be of a massive nature are those which occur on the buses. Any failures past the resistors 131g and h for example will be local in nature. Thus, in summary, the present invention takes three steps, alone or in combination, to achieve fault isolation. The first step is to provide isolating current limiting resistors such as resistor 31. The second step is to provide buffer amplifiers either alone or in addition to such resistors. The third step is to supply the buffer amplifers in a given channel from a separate current limited supply. 
     The channel illustrated in FIG. 2 incorporates all of these features. It has separate supplies for supplying both 5 and 15 volts, includes buffer amplifiers at the output of the master selector, these amplifiers having input resistors which assure further current limiting back to the master. In addition, it is noted that the unit illustrated by FIG. 2 is not only electrically but mechanically isolated, in the design of the present invention, which, of course, adds to the flexibility of the present system in providing from basic building blocks as many channels as are needed for a particular application. 
     With respect to separate current limited supplies and the other techniques just noted, although illustrated for a single channel, for reasons of economy these measures can be taken for groups of channels. Of course, the isolation will not be as good but it will still be superior to that provided in the present day state of the art equipment. 
     Encoding and Decoding 
     FIG. 6 shows a portion of the sample and hold circuit 603 of FIG. 2 and shows how, utilizing a precision half wave rectifier 803 one can, in addition to decoding, encode and output back to the memory board, for example. The encoder follows the switch 211 shown in FIG. 1B. Upon an input from address decoder 213 through resistor 621, switch 211 is closed. Whatever voltage is present at the input to the output amplifier 207 is also provided as an input to the encoding circuit which includes an amplifier 805 having in its output coupled through a positively poled diode 807, the output of which is coupled through a feedback resistor 811 to the inverting input of the amplifier. The non-inverting input of the amplifier which receives the input through the switch is coupled to ground through a resistor 813. This is a circuit well known for use, a precision halfwave rectifier. It is used here because it combines the effects of diode isolation with the current capability of a buffer. The output of this circuit on line 159 is fed to a bus shared by all channels. Although in this embodiment, both the decoding and encoding are enabled by the same output of the address decoder, it will be recognized that separate decoding and encoding enable pulses could be developed to separately drive switches 211 and 615. 
     FIG. 7 shows an example of a local address decoder. Inputs on bus 161 are coupled through fault isolating resistors to a binary decoder 815. This decoder which may simply comprise a series of gates receives inputs from a set of switches 817 which permit setting each of the inputs to either a &#34;0&#34; or a &#34;1&#34; indicated by inputs 819 and 820. When the address on the bus 116 matches that set in on the switches 817, there is coincidence and an output is developed on line 821. This is one input to an AND gate 823 which receives a clock input on line 825. The output of gate 823, 827 controls the switches 613 and 615 of FIG. 2 for example. 
     Another embodiment is shown by FIG. 8. In this device only two inputs are required, i.e., the bus 161 need only have two lines. Line B contains a start signal and line A a clock signal. These are inputs through input resistors to a clock and start input of a programmable delay unit. Programmable delay unit 831 has set into it, through a series of switches 833 which can be set to either a 1 input 835 or a 0 input 837, a desired delay. After receipt of the start pulse, the programmable delay unit counts a number of clock pulses specified by the programming inputs f-l through f-n set in by switches 833. When the number of clock periods counted equals the number set in the programming input, an output will appear on line 827. It remains in this state for no more than one clock period. The unit then remains inactive until another start pulse is received. The output on line 827 however will close the switches associated with the sample and hold circuits 601 and 603 long enough to carry out the necessary sampling. Traces E, F and G illustrate the outputs for three successive channels. The first output occurs after counting one clock pulse past the start signal. The output begins on the falling edge of the clock period and ends on the rising edge. Thus, there is a gap of the length of the clock pulse between that of one channel and the output for the next channel to allow data on the serial information bus to stabilize. These outputs are, of course, each generated by separate local pulse generators which form the decoder 213 of FIG. 1B and FIG. 2. 
     FIG. 8A shows the local pulse generator 831 in more detail. The logic &#34;1&#34; signal is provided by a positive voltage and the logic &#34;0&#34; signal 837 by ground. The inputs of switches 833 are provided as inputs to an up-down counter 840 set to countdown. The B signal is provided as a preset enable signal to the counter presetting it to the value set in on the switches. The clock signal on line A is coupled through an AND gate 842 into the clock input. Gate 842 is enabled by a D-type flip-flop 844. The start signal, in addition to presetting the counter 840 and enabling it, sets the flip-flop 844 so that its Q output becomes a &#34;1&#34; enabling AND gate 842. At this time, the output CO (zero count) is a logic &#34;1&#34; at the inverted output. The next clock pulse will be passed by AND gate 842 and counted in the counter 840. Counting continues until the value set in by switches 833 is counted down to zero. The output CO on the counter will then change state. When the clock pulse goes low, AND gate 846 will, after inversion at its input, have two logic &#34;1&#34; inputs and provide a logic &#34;1&#34; output. On the next clock pulse the count is counted down to all &#34;1s&#34; causing CO to change state and clock the D-type flip-flop. This will cause the &#34;0&#34; on its D input to be transferred to its output. This prevents any further counting by disabling gate 840. At this time the output of gate 846 also goes to logic &#34;0&#34; again. Thus, through this gating there is no overlap between two subsequent pulses. 
     Finally, with respect to the attenuation of the scene III signal, it is noted that in addition to the pulse width modulation discussed and described in the aforementioned patent, this attenuation can be done with a voltage controlled amplifier or with a digital attenuator, in which case the signal, rather than being on a single line 157, would be obtained from the data bus 143.