Abstract:
A bandgap reference circuit incorporates first, second, and third current sources, an operational amplifier coupled to the second and the third current sources, a voltage divider, a first resistor, and first, second, and third bipolar transistors. The second bipolar transistor has a base configured to receive a first voltage from the voltage divider. The third bipolar transistor has a base configured to receive a second voltage from the voltage divider. The first resistor is coupled between the third current source and the third bipolar transistor.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to reference circuits, and more specifically to a bandgap reference circuit. 
     2. Description of the Related Art 
     A bandgap reference circuit is used to generate a precise output voltage. The generated voltage is independent of process, voltage, and temperature. The band-gap reference circuit is widely used in various analogue and digital circuits that require a precise voltage for operation. 
       FIG. 1  illustrates one commonly used bandgap reference circuit  100 . 
     Referring to  FIG. 1 , the bandgap reference circuit  100  includes PMOS transistors M 1 , M 2 , and M 3 , an operational amplifier OP, resistors R 1  and R 2 , and bipolar transistors Q 1 , Q 2 , and Q 3 . If the base current is neglected, the output voltage VOUT of the bandgap reference circuit  100  can be expressed as:
 
 V OUT= VEB 3 +VT ×ln  N×R 2 /R 1  (1)
 
     Where VEB 3  is the emitter-base voltage of the bipolar transistor Q 3 , VT is the thermal voltage at room temperature, and N is the ratio of the current density of the transistor Q 2  to the current density of the transistor Q 1 . 
     As can be seen from the equation (1), by adjusting the ratio of resistors R 2 /R 1 , the conventional bandgap reference circuit  100  can provide a stable reference voltage VOUT having a zero temperature coefficient. The voltage level of the voltage VOUT is at around 1.25V, which is approximately equal to the silicon energy gap measured in electron volts, i.e., the silicon bandgap voltage. 
     SUMMARY OF THE INVENTION 
     An aspect of the present invention is to provide a bandgap reference circuit. 
     According to one embodiment of the present invention, the bandgap reference circuit comprises first, second, and third current sources, an operational amplifier coupled to the first, second and the third current sources, a voltage divider, a first resistor, and first, second, and third bipolar transistors. The first bipolar transistor has an emitter coupled to the first current source, a base and a collector coupled to a ground voltage. The voltage divider is coupled between the emitter and the base of the first bipolar transistor, wherein the voltage divider provides first and second voltages proportional to a base-emitter voltage of the first bipolar transistor. The second bipolar transistor has a base configured to receive the first voltage, an emitter coupled to the second current source, and a collector coupled to the ground voltage. The third bipolar transistor has a base configured to receive the second voltage, and a collector coupled to the ground voltage. The first resistor is coupled between the third current source and an emitter of the third bipolar transistor. The first, second, and third current sources are configured to provide currents proportional to absolute temperature (PTAT) currents. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention will be described according to the appended drawings in which: 
         FIG. 1  illustrates one commonly used bandgap reference circuit; 
         FIG. 2  shows a schematic diagram of a bandgap reference circuit according to one embodiment of the present invention; 
         FIG. 3  shows a schematic diagram of a bandgap reference circuit according to another embodiment of the present invention; and 
         FIG. 4  shows a schematic diagram of a bandgap reference circuit according to yet another embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 2  shows a schematic diagram of a bandgap reference circuit  200  according to one embodiment of the present invention. Referring to  FIG. 2 , the bandgap reference circuit  200  comprises a current source unit  22 , a voltage divider  24 , an operational amplifier OP, a resistor R 1 , and three bipolar transistors Q 1 , Q 2 , and Q 3 . In this embodiment, the current source unit  22  is constructed from three PMOS transistors M 1 , M 2 , and M 3 . These PMOS transistors M 1 , M 2 , and M 3  are electrically connected to a supply voltage VDD such that currents, labeled I 1 ,  12 , and  13 , are produced. Since the gates of the PMOS transistors M 1 , M 2 , and M 3  are connected to each other, the currents flowing through the PMOS transistors M 1 , M 2 , and M 3  depend on the W/L ratio of the transistors. 
     In this embodiment, a size ratio of the PMOS transistors M 1 , M 2 , and M 3  in the current source unit  22  is set to 2:1:1. Therefore, the current I 2  is substantially equal to the current I 3 , and the current I 1  has twice the magnitude of the current I 2 . 
     Referring to  FIG. 2 , the bipolar transistor Q 1  has an emitter coupled to a drain of the PMOS transistor M 1 , and a base and a collector both coupled to a ground voltage. The bipolar transistor Q 2  has an emitter coupled to a drain of the PMOS transistor M 2 , a base coupled to a voltage VB 3  from the voltage divider  24 , and a collector coupled to the ground voltage. The bipolar transistor Q 3  has a base coupled to a voltage VB 1  from the voltage divider  24  and a collector coupled to the ground voltage. The resistor R 1  is couple between a drain of the PMOS transistor M 3  and an emitter of the bipolar transistor Q 3 . 
     Referring to  FIG. 2 , the operational amplifier OP has a positive input terminal coupled to the drain of the PMOS transistor M 3 , a negative input terminal coupled to the drain of the PMOS transistor M 2 , and an output terminal coupled to the gates of the PMOS transistors M 1 , M 2 , and M 3 . The amplifier OP and the PMOS transistors M 2  and M 3  constitute a negative feedback loop which forces the voltages VD 1  and VD 3  to be substantially equal. Thus, the voltages VD 1  and VD 3  can be expresses as:
 
 VD 1= VD 3= VB 3+ VEB 2= VB 1+ VEB 3+ I 3× R 1  (2)
 
     Where VEB 2  is the emitter-base voltage of the bipolar transistor Q 2 , and VEB 3  is the emitter-base voltage of the bipolar transistor Q 3 . 
     Referring to  FIG. 2 , the voltage divider  24  is coupled to the emitter of the bipolar transistor Q 1 . In this embodiment, the voltage divider  24  is formed by three series connected resistors R 3 , R 4 , and R 5 . Therefore, the voltage divider  24  provides the voltages VB 1  and VB 3  proportional to a base-emitter voltage of the bipolar transistor Q 1 . Thus, the voltages VB 1  and VB 3  can be expressed as:
 
 VB 3= VEB 1× R 5/( R 3+ R 4+ R 5)  (3)
 
 VB 1= VEB 1×( R 4+ R 5)/( R 3+ R 4+ R 5)  (4)
 
     Where VEB 1  is the emitter-base voltage of the bipolar transistor Q 1 . 
     Accordingly, equation (2) can be re-arranged as:
 
 I 3× R 1= VEB 2− VEB 3+ VB 3− VB 1= VT ×ln  N−VEB 1× R 4/( R 3+ R 4+ R 5)  (5))
 
     Where VT is the thermal voltage at room temperature, and N is the ratio of the current density of the transistor Q 2  to the current density of the transistor Q 1 . In this embodiment, the currents flowing through the transistors Q 1 , Q 2 , and Q 3  are substantially equivalent 
     Thus, the current I 3  through the resistor R 1  can be expressed as:
 
 I 3= VT ×ln  N/R 1− VEB 1× R 4/( R 1×( R 3+ R 4+ R 5))  (6)
 
     Since the thermal voltage VT has a positive temperature coefficient of 0.085 mV/° C. and the emitter-base voltage of the transistor Q 1  has a negative temperature coefficient of −2 mV/° C., the current I 3  has a temperature dependency slope. Due to the factor −VEB 1 ×(R 4 /(R 3 +R 4 +R 5 )), the temperature dependency slope of the current I 3  increases faster with temperature increase when it is compared with the prior art. 
     As can be seen from equation (6), the net temperature coefficient of the current I 3  can be varied by choosing resistance values of the resistors R 1 , R 3 , R 4 , and R 5 , and the ratio of the current density of the transistor Q 2  to the current density of the transistor Q 1 . In addition, the base of the transistor Q 2  can be coupled to the voltage VB 1  from the voltage divider  24 , and the base of the transistor Q 3  can be coupled to the voltage VB 3  from the voltage divider  24  as shown in  FIG. 3 , such that the net temperature coefficient of the current I 3  is reduced compared with the circuit configuration of  FIG. 2 . 
     In order to provide a stable output reference voltage with a zero temperature coefficient, the bandgap reference circuit  200 ″ further comprises a resistor R 2  and a bipolar transistor Q 4  as shown in  FIG. 4 . Referring now to  FIG. 4 , the current source unit  22 ′ is constructed from the PMOS transistors M 1 , M 2 , M 3 , and M 4  with gates driven by the output of the amplifier OP. In this embodiment, the PMOS transistor M 4  and the PMOS transistor M 3  have substantially equal sizes. Therefore, the current I 4  flowing through the resistor R 2  is the same as the current I 3 , and can be expressed as:
 
 I 4= I 3= VT ×ln  N/R 1− VEB 1× R 4/( R 1×( R 3+ R 4+ R 5))  (7)
 
     With such circuit configuration, the voltage VREF can be expressed as:
 
 V REF= VEB 4 +I 4 ×R 2  (8)
 
     Where VEB 4  is the emitter-base voltage of the bipolar transistor Q 4 . 
     Substituting equation (7) into equation (8) gives:
 
 V REF= VEB 4+ VT ×ln  N×R 2/ R 1− VEB 1× R 2× R 4/( R 1×( R 3+ R 4+ R 6))  (9)
 
     Hence, if proper resistance values of the resistors R 1 , R 2 , R 3 , R 4 , and R 5  are selected, the output voltage VREF of the bandgap reference circuit  200 ″ will have a zero temperature coefficient and low sensitivity to temperature. 
     In addition, compared with the prior art, the bandgap reference circuit  200 ″ of  FIG. 4  can be operable at a lower supply voltage level. Recalling equation (1):
 
 V OUT= VEB 3+ VT ×ln  N×R 2/ R 1  (1)
 
     From equation (1) it can be seen that the output voltage of the conventional bandgap reference circuit is limited to 1.25V in order to obtain a zero temperature coefficient. However, from equation (9) it can be seen that the output voltage VOUT of the bandgap reference circuit of the invention can reduce by a voltage proportional to a base-emitter voltage of the first bipolar transistor Q 1 . In an exemplary embodiment, if the ratio N is selected to be 32, the resistance values of the resistors R 1 , R 2 , R 3 , R 4 , and R 5  are respectively selected to be 39KΩ, 225KΩ, 114KΩ, 4KΩ, and 84KΩ, the bandgap reference circuit of the invention can provide a lower output voltage VREF at around 1.11V. Thus, the operating supply voltage can be less than 1.35V by using this circuit. 
     In addition, the bandgap reference circuit of the invention can effectively reduce the DC offset due to the input offset of the operational amplifier. When considering the input offset VOS of the operational amplifier OP of  FIG. 1 , the equation (1) can be rewritten as:
 
 V OUT= VEB 3+ VT ×ln  N×R 2/ R 1+ VOS×R 2/ R 1  (10)
 
     Thus, the input offset VOS of the operational amplifier OP of  FIG. 1  is amplified by the ratio of the resistance of the resistor R 2  to the resistance of the resistor R 1 . When considering the input offset VOS of the operational amplifier OP of  FIG. 2  of the invention, the equation (9) is rewritten as:
 
 V REF= VEB 4+ VT ×ln  N×R 2/ R 1− VEB 1× R 2× R 4/( R 1×( R 3+ R 4+ R 5))+ VOS×R 2/ R 1  (11)
 
     Since the factor of −VEB 1 ×R 2 ×R 4 /(R 1 ×(R 3 +R 4 +R 5 )) is added to effect the temperature coefficient of the output voltage VREF, the ratio of the resistance of the resistor R 2  to the resistance of the resistor R 1  can be reduced in order to obtain the voltage VREF with a zero temperature coefficient. Therefore, the amplification factor of the input offset of the operational amplifier can be reduced by using the bandgap reference circuit of the invention. 
     The above-described embodiments of the present invention are intended to be illustrative only. Numerous alternative embodiments may be devised by those skilled in the art without departing from the spirit and scope of the invention as recited in the following claims.