Abstract:
A transmission/reception system includes first to N th  channels, where N is an integer equal to or greater than 3; a transmission chip suitable for transmitting first to (N−1) th  signals through the first to (N−1) th  channels and transmitting a correction signal generated by using the first to (N−1) th  signals to the N th  channel; and a reception chip suitable for receiving signals of the first to N th  channels and generating restored signals of the first to N th  channels by using the first to N th  channels.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application claims priority to Korean Patent Application No. 10-2013-0159266, filed on Dec. 19, 2013, which is incorporated herein by reference in its entirety. 
     
    
     BACKGROUND 
       [0002]    1. Field 
         [0003]    Exemplary embodiments of the present invention relate to a technology for transmitting and receiving signals, and more particularly to a technology for preventing a failure in transmitting and receiving signals caused by a failure in a transmission channel. 
         [0004]    2. Description of the Related Art 
         [0005]    The capacity and speed of semiconductor memories used as memory devices in electronic systems have been increasing and various attempts are being made to package and efficiently drive large-capacity memories in a limited area. 
         [0006]    To improve the integration degree, a three-dimensional (3D) structure technology in which a plurality of memory chips are stacked has evolved from a two-dimensional (2D) structure technology. The three-dimensionsal (3D) structure technology is in high demand because of its potential to deliver a high degree of integration (and high capacity), so that the size of the semiconductor chip may be reduced. 
         [0007]    A “Through Silicon Via” (“TSV”) scheme may be used as the 3D structure technology. The TSV scheme is a possible solution for overcoming deterioration in transmission speed that occurs in a module based on the distance from a controller, a weak point of data bandwidth, and variables of a package. According to the TSV scheme, a path penetrating through a plurality of memory chips is formed, and to communication is carried out between the stacked chips by forming electrodes in the path. 
         [0008]    When a failure occurs in a TSV, all the chips stacked in the semiconductor package may be useless. If all the chips have to be abandoned due to a failure occurring in the TSV, which is a very small structure, a significant amount of waste occurs. Therefore, there is a need to develop a technology to cope with TSV failures. 
       SUMMARY 
       [0009]    Exemplary embodiments of the present invention are directed to a technology for preventing a failure in transmitting and receiving signals that may be caused by a failure of a transmission channel between chips. 
         [0010]    In accordance with an embodiment of the present invention, a transmission/reception system includes first to N th  channels, a transmission chip suitable for transmitting first to (N−1) signals through the first to (N−1) th  channels and transmitting a correction signal generated by using the first to (N−1) th  signals to the N th  channel and a reception chip suitable for receiving signals of the first to N th  channels and generating restored signals of the first to N th  channels by using the first to N th  channels. 
         [0011]    In accordance with another embodiment of the present invention, a transmission chip includes a correction signal generation unit suitable for correcting first to (N−1) th  signals through an XOR operation and generating a correction signal, and first to N th  drivers suitable for transmitting the first to (N−1) th  signals and the correction signal to first to N th  channels. 
         [0012]    In accordance with another embodiment of the present invention, a reception chip includes first to N th  nodes suitable for receiving signals of first to N th  channels, a restoring unit suitable for generating restored signals of the first to N th  channels by using signals of the first to N th  nodes, and first to N th  feedback drivers suitable for driving the restored signals of the first to N th  channels generated from the restoring unit to the first to N th  nodes. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]      FIG. 1  is a block diagram illustrating a transmission/reception system in accordance with an embodiment of the present invention; 
           [0014]      FIG. 2  is a block diagram illustrating a transmission/reception system in accordance with another embodiment of the present invention; 
           [0015]      FIG. 3  is a block diagram illustrating the transmission/reception system shown in  FIG. 2  being stacked inside a semiconductor package  300 ; 
           [0016]      FIG. 4  is a block diagram illustrating the transmission/reception system shown in  FIG. 2  being formed over a printed circuit board  400 ; and 
           [0017]      FIG. 5  is a circuit diagram illustrating an N−1 inputs XOR gate. 
       
    
    
     DETAILED DESCRIPTION 
       [0018]    Exemplary embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In describing the present invention, widely-known structures and components irrelevant to the substance of the present invention will be omitted. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention. 
         [0019]      FIG. 1  is a block diagram illustrating a transmission/reception system in accordance with an embodiment of the present invention. 
         [0020]    Referring to  FIG. 1 , a transmission/reception system includes a transmission chip  110 , a reception chip  120  and channels CHANNEL_ 1  to CHANNEL_ 3 . 
         [0021]    The transmission chip  110  transmits a first signal SIGNAL_ 1  and a second signal SIGNAL_ 2  to a first channel CHANNEL_ 1  and a second channel CHANNEL_ 2  and transmits a correction signal SIGNAL_X generated by using the first signal SIGNAL_ 1  and the second signal SIGNAL_ 2  to a third channel CHANNEL_ 3 . The transmission chip  110  includes a correction signal generation unit  111  and first to third drivers  112 _ 1  to  112 _ 3 . The first signal SIGNAL_ 1  and the second signal SIGNAL_ 2  include information that is required for the transmission chip  110  to transmit to the reception chip  120 , and the correction signal SIGNAL_X is a signal for preventing a failure of transmission/reception of the signals SIGNAL_ 1  and SIGNAL_ 2 . 
         [0022]    The correction signal generation unit  111  generates the correction signal SIGNAL_X by performing an XOR operation on the first signal SIGNAL_ 1  and the second signal SIGNAL_ 2 . The correction signal generation unit  111  includes an XOR gate as shown in the drawing. The correction signal SIGNAL_X has a value of “0” when the number of signals having a value of “1” is an even number (e.g., the number of “1”=0 or 2) at the first signal SIGNAL_ 1  and the second signal SIGNAL_ 2 . The correction signal SIGNAL_X has a value of “1” when the number of signals having a value of “1” is an odd number (e.g., the number of “1”=1) at the first signal SIGNAL_ 1  and the second signal SIGNAL_ 2 . 
         [0023]    The first driver  112 _ 1  transmits the first signal SIGNAL_ 1  to the first channel CHANNEL_ 1  and the second driver  112 _ 2  transmits the second signal SIGNAL_ 2  to the second channel CHANNEL_ 2 . The third driver  112 _ 3  transmits the correction signal SIGNAL_X to the third channel CHANNEL_ 3 . 
         [0024]    The reception chip  120  receives the signals of the first to third channels CHANNEL_ 1  to CHANNEL_ 3  and generates restored signals REGENERATED_ 1 , REGENERATED_ 2  and REGENERATED_ 3  based on the received signals NODE_ 1  to NODE_ 3 . The reception chip  120  includes first to third nodes NODE_ 1  to NODE_ 3 , a restoring unit  121 , first to third feedback drivers  122 _ 1  to  122 _ 3  and first and second buffers  123 _ 1  and  123 _ 2 . 
         [0025]    The restoring unit  121  generates the restored signals REGENERATED_ 1 , REGENERATED_ 2  and REGENERATED_ 3  based on signals of nodes NODE_ 1 , NODE_ 2  and NODE_ 3  received from the channels CHANNEL_ 1 , CHANNEL_ 2  and CHANNEL_ 3 . The restoring unit  121  generates the third signal REGENERATED_ 3  restored by performing an XOR operation on signals of the first node NODE_ 1  and the second node NODE_ 2 . The restoring unit  121  generates the first signal REGENERATED_ 1  restored by performing an XOR operation on signals of the second node NODE_ 2  and the third node NODE_ 3 . The restoring unit  121  generates the second signal REGENERATED_ 2  restored by performing an XOR operation on signals of the third node NODE_ 3  and the first node NODE_ 1 . The restoring unit  121  includes XOR gates  121 _ 1 ,  121 _ 2  and  121 _ 3 . The restoring unit  121  accurately generates the restored signals REGENERATED_ 1 , REGENERATED_ 2  and REGENERATED_ 3  of the first to third channels even when one of the channels CHANNEL_ 1  to CHANNEL_ 3  has a failure. For example, when the first signal SIGNAL_ 1 , the second signal SIGNAL_ 2  and the correction signal SIGNAL_X have a level of (1,0,1), and the first signal SIGNAL_ 1  is not transmitted to the first node NODE_ 1  because the first channel CHANNEL_ 1  is opened, the restoring unit  121  generates the restored signal REGENERATED_ 1  of the first channel having a level of “1” by using the signals transmitted to the second node NODE_ 2  and the third node NODE  3 . 
         [0026]    The first to third feedback drivers  122 _ 1  to  122 _ 3  may feed back the restored signals REGENERATED_ 1  to REGENERATED_ 3  of the first to third channels CHANNEL_ 1  to CHANNEL_ 3 , to the first to third nodes NODE_ 1  to NODE_ 3 . The first to third feedback drivers  122 _ 1  to  122 _ 3  feed back the restored signals REGENERATED_ 1  to REGENERATED_ 3  to the nodes NODE_ 1  to NODE_ 3  when the channels CHANNEL_ 1  to CHANNEL_ 3  have a failure. For example, when the second signal SIGNAL_ 2  is not transmitted to the second node NODE_ 2  because the second channel CHANNEL_ 2  has a defect when being opened, the signal REGENERATED_ 2  of the second channel CHANNEL_ 2  restored by the second feedback driver  122 _ 2  is transmitted to the second node NODE_ 2 . When the first to third channels CHANNEL_ 1  to CHANNEL_ 3  are in normal condition, the first to third feedback drivers  122 _ 1  to  122 _ 3  may be designed to have a driving power which is too weak (not powerful enough) to change the logic levels of the first to third nodes NODE_ 1  to NODE_ 3  driven by the first to third channels CHANNEL_ 1  to CHANNEL_ 3 . For example, the restored signal REGENERATED_ 1  of the first channel is to be transmitted to the first node NODE_ 1  when the first channel CHANNEL_ 1  has an open defect, but there is no need for a proper logic level of the second node NODE_ 2  to be changed by the restored signal REGENERATED_ 2  of the second channel, which may temporarily have a wrong value due to a wrong value of the signal of the first node NODE_ 1 , when the second channel CHANNEL_ 2  is in a normal condition. 
         [0027]    The first buffer  123 _ 1  buffers a signal of the first node NODE_ 1 , and the second buffer  123 _ 2  buffers a signal of the second node NODE_ 2 . An output signal of the first buffer  123 _ 1  and an output signal of the second buffer  123 _ 2  are the signals used by internal circuits (not shown) of the reception chip  120 . The third node NODE_ 3  is used for correcting a failure of the signal that the reception chip  120  receives. Since the third node NODE_ 3  is not a node to receive a signal to be used by the internal circuits of the reception chip  120 , the third node NODE_ 3  does not need a buffer. 
         [0028]    Table 1 shows the logic level of each of the signals when the first signal SIGNAL_ 1  and the second signal SIGNAL_ 2  have a level of (1,0) and the second channel CHANNEL_ 2  has a failure. 
         [0000]    
       
         
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 SIGNAL_1 
                 SIGNAL_2 
                 SIGNAL_X 
               
               
                   
               
             
             
               
                 1 
                 0 
                 1 
               
               
                 NODE_1 
                 NODE_2 
                 NODE_3 
               
               
                 1 
                 fail −&gt;0 
                 1 
               
               
                 REGENERATED_1 
                 REGENERATED —— 2 
                 REGENERATED_3 
               
               
                 fail−&gt;1 
                 0 
                 fail−&gt;1 
               
               
                   
               
             
          
         
       
     
         [0029]    Referring to Table 1, although the second channel CHANNEL_ 2  has a failure, the failure of the second node NODE_ 2  is restored by the restored signal REGENERATED_ 2  of the second channel CHANNEL_ 2 . Furthermore, although the signals REGENERATED_ 1  of the first channel are restored due to the failure of the second channel CHANNEL_ 2  and an initial value of the restored signal REGENERATED_ 3  of the third channel has a failure, no failure occurs in the first node NODE_ 1  and the third node NODE_ 3  since the driving power of the first feedback driver  122 _ 1  and the third feedback driver  122 _ 3  is weak. 
         [0030]      FIG. 2  is a block diagram illustrating a transmission/reception system in accordance with another embodiment of the present invention. While  FIG. 1  shows that the three channels CHANNEL_ 1  to CHANNEL_ 3  are formed between the transmission chip  110  and the reception chip  120 ,  FIG. 2  shows that N channels CHANNEL_ 1  to CHANNEL_N are formed between a transmission chip  210  and a reception chip  220 . In describing the embodiment of the present invention shown in  FIG. 2 , a description of overlapping parts shown in  FIG. 1  is omitted. 
         [0031]    Referring to  FIG. 2 , a transmission/reception system includes a transmission chip  210 , a reception chip  220  and first to N th  channels CHANNEL_ 1  to CHANNEL_N. 
         [0032]    The transmission chip  210  transmits first to (N−1) th  signals SIGNAL_ 1  to SIGNAL_N−1 through first to (N−1) th  channels CHANNEL_ 1  to CHANNEL_N−1 and transmits a correction signal SIGNAL_X generated by using the first to (N−1) th  signals SIGNAL_ 1  to SIGNAL_N−1 to a N th  channel CHANNEL_N. The transmission chip  210  includes a correction signal generation unit  211  and first to N th  drivers  212 _ 1  to  212 _N. 
         [0033]    The correction signal generation unit  211  generates the correction signal SIGNAL_X by performing an XOR operation on the first to (N−1) th  signals SIGNAL_ 1  to SIGNAL_N−1. The correction signal SIGNAL_X has a value of “0” when the number of signals having a value of “1” among the first to (N−1) th  signals SIGNAL_ 1  to SIGNAL_N−1 is an even number. The correction signal SIGNAL_X has a value of “1” when the number of signals having a value of “1” among the first to (N−1) th  signals SIGNAL_ 1  to SIGNAL_N−1 is an odd number. The correction signal generation unit  211  includes an XOR gate to receive (N−1) signals SIGNAL_ 1  to SIGNAL N−1. An (N−1) th  input XOR gate is shown in  FIG. 5 . The (N−1) th  input XOR gate includes a plurality of 2 input XOR gates. 
         [0034]    The reception chip  220  receives signals of the first to N th  channels CHANNEL_ 1  to CHANNEL_N and generates restored signals REGENERATED_ 1  to REGENERATED_N of the first to N th  channels by using received signals NODE_ 1  to NODE_N. The reception chip  220  includes first to N th  nodes NODE_ 1  to NODE_N, a restoring unit  221 , first to N th  feedback drivers  222 _ 1  to  222 _N and first to (N−1) th  buffers  223 _ 1  to  223 _N−1. 
         [0035]    The restoring unit  221  generates the restored signals REGENERATED_ 1  to REGENERATED_N of the first to N th  channels by using signals of the first to N th  nodes NODE_ 1  to NODE_N. A restored signal of an M th  channel REGENERATED_M, where M is an integer from 1 to N, is generated by performing an XOR operation on the other signals, exclusive of a signal of an M th  node NODE_M, among the signals of the first to N th  nodes NODE_ 1  to NODE_N. For example, a restored signal REGENERATED_ 2  of a second channel is generated by performing the XOR operation on a signal of a first node NODE_ 1  and signals of third to N th  nodes NODE_ 3  to NODE_N. The restoring unit  221  includes N (N−1) input XOR gates  221 _ 1  to  221 _N. 
         [0036]    Just as in the embodiment of  FIG. 1 , in the embodiment of FIG.  2 , a failure in the transmission/reception of the signals may be prevented by the restoring unit  221  even though there is a failure in one of the channels CHANNEL_ 1  to CHANNEL_N. 
         [0037]      FIG. 3  is a block diagram illustrating the transmission/reception system shown in  FIG. 2 , stacked inside a semiconductor package  300 . 
         [0038]    Referring to  FIG. 3 , the transmission chip  210  and the reception chip  220  may be stacked inside the semiconductor package  300 . The channels CHANNEL_ 1  to CHANNEL_N may be formed by using Through Silicon Vias (TSVs). 
         [0039]      FIG. 4  is a block diagram illustrating the transmission/reception system shown in  FIG. 2 , formed over a printed circuit board  400 . 
         [0040]    Referring to  FIG. 4 , the transmission chip  210  and the reception chip  220  may be disposed over the printed circuit board  400 , and the channels CHANNEL_ 1  to CHANNEL_N may be formed by forming lines over the printed circuit board  400 . 
         [0041]    Exemplary embodiments of the transmission/reception system are described above with reference to the accompanying drawings  FIGS. 3 and 4 . The transmission/reception system may, however, be realized in different forms and should not be construed as limited to the embodiments set forth herein. 
         [0042]    While the present invention has been described with respect to the specific embodiments, it should be noted that the embodiments are for describing, not limiting, the present invention. Further, it should be noted that the present invention may be achieved in various ways through substitution, change, and modification, by those skilled in the art without departing from the scope of the present invention as defined by the following claims.