Abstract:
Embodiments of the invention provide a method, system, and program product for predicting a delay of a critical path. In one embodiment, the invention provides a method of predicting a delay of at least one critical path of an integrated circuit, the method comprising: determining a delay of at least one ring oscillator on the integrated circuit; and calculating a predicted delay for the at least one critical path delay based on a delay of components of the critical path at a corner condition, a wire delay of the at least one critical path, a delay of the at least one ring oscillator at a corner condition, and the determined delay of the at least one ring oscillator.

Description:
TECHNICAL FIELD 
       [0001]    The present invention relates generally to semiconductor chip and integrated circuit technologies and, more particularly, to the prediction of a critical path delay. 
       BACKGROUND OF THE INVENTION 
       [0002]    The increased power demands of semiconductor chips are becoming more difficult to overcome, particularly as chip densities increase. Adaptive voltage scaling (AVS) is one technique used to reduce power consumption. Unfortunately, efficient use of AVS requires accurate predictions of critical path performance, and particularly critical path delay, something that has proven difficult to achieve. 
       SUMMARY OF THE INVENTION 
       [0003]    Embodiments of the invention provide methods, systems, and program products for predicting a critical path delay. 
         [0004]    A first aspect of the invention provides a method of predicting a delay of at least one critical path of an integrated circuit, the method comprising: determining a delay of at least one ring oscillator on the integrated circuit; and calculating a predicted delay for the at least one critical path delay based on a delay of components of the critical path at a corner condition, a wire delay of the at least one critical path, a delay of the at least one ring oscillator at a corner condition, and the determined delay of the at least one ring oscillator. 
         [0005]    A second aspect of the invention provides a system comprising: at least one computing device configured for predicting a delay of at least one critical path of an integrated circuit by performing a method comprising: determining a delay through at least one ring oscillator on the integrated circuit; and calculating a predicted critical path delay based on a delay of components of the critical path at a corner condition, a wire delay of the at least one critical path, a delay of the at least one ring oscillator at a corner condition, and the determined delay of the at least one ring oscillator. 
         [0006]    A third aspect of the invention provides a program product stored on a computer-readable storage medium which, when executed, is operable to predict a delay of at least one critical path of an integrated circuit by performing a method comprising: determining a delay through at least one ring oscillator on the integrated circuit; and calculating a predicted critical path delay for the at least one critical path delay based on a delay of components of the critical path at a corner condition, a wire delay of the at least one critical path, a delay of the at least one ring oscillator at a corner condition, and the determined delay of the at least one ring oscillator. 
         [0007]    The illustrative aspects of the present invention are designed to solve the problems herein described and other problems not discussed, which are discoverable by a skilled artisan. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]    These and other features of this invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings that depict various embodiments of the invention, in which: 
           [0009]      FIG. 1  shows a plot of the delays of critical path components as a function of drain voltage. 
           [0010]      FIG. 2  shows a schematic of a critical path clock and ring oscillator frequency at a corner condition. 
           [0011]      FIG. 3  shows a flow diagram of a method according to one embodiment of the invention. 
           [0012]      FIG. 4  shows a schematic of an illustrative system according to an embodiment of the invention. 
       
    
    
       [0013]    It is noted that the drawings of the invention are not to scale. The drawings are intended to depict only typical aspects of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements among the drawings. 
       DETAILED DESCRIPTION OF THE INVENTION 
       [0014]    Turning now to the drawings,  FIG. 1  shows an illustrative plot of the delay (in nanoseconds) associated with various critical path components as a function of drain voltage (Vdd). As can be seen in  FIG. 1 , at drain voltages less than about 1.0, high-voltage threshold (HVT) components  6  exhibit a greater delay than medium-voltage threshold (SVT) components  4  or low-voltage threshold (UVT) components  2 . At drain voltages greater than about 1.0, however, UVT components  2  exhibit a greater delay than SVT components  4  or HVT components  6 . One difficulty in predicting performance of a critical path, then, and particularly in predicting a delay of a critical path, is the differences in delays attributable to HVT, SVT, and UVT components as drain voltage changes. That is, any predicted delay of a critical path should remain below an upper bound  10  of the delays of all components in order to be useful in maximizing chip efficiency, particularly the efficiencies afforded by adaptive voltage scaling (AVS). 
         [0015]    In one embodiment of the invention, performance of a critical path can be predicted, and chip efficiency improved, using static timing analysis data and real-time estimation of critical path performance using on-board ring oscillators.  FIG. 2  shows a schematic of a critical path clock and ring oscillator frequency at a corner condition. As can be seen in  FIG. 2 , the N cycles of the critical path clock during the period shown correspond to M cycles of the ring oscillator. Using this correspondence, the ring oscillator frequency may be used to estimate a delay in the critical path, the components of which are sensitive to chip parameters, such as process, voltage, and temperature. In other words, once the critical path clock to ring oscillator frequency is known at a corner condition, the ring oscillator frequency under other conditions can be used to predict a critical path delay under those other conditions. 
         [0016]    A predicted critical path delay can be calculated, in general, according to Equation 1 below. 
         [0000]    
       
         
           
             
               
                 
                   
                     D 
                     cp 
                   
                   = 
                   
                     ( 
                     
                       
                         [ 
                         
                           
                             D 
                             
                               C 
                               cc 
                             
                           
                           × 
                           
                             { 
                             
                               
                                 D 
                                 RO 
                               
                               
                                 D 
                                 
                                   RO 
                                   cc 
                                 
                               
                             
                             } 
                           
                         
                         ] 
                       
                       + 
                       
                         D 
                         W 
                       
                     
                     ) 
                   
                 
               
               
                 
                   Equation 
                    
                   
                       
                   
                    
                   1 
                 
               
             
           
         
       
     
         [0017]    In Equation 1, D cp  is the predicted critical path delay, D C   cc  is a delay of components of the at least one critical path at a corner condition, D RO  is the determined delay of the at least one ring oscillator, D RO   cc  is a nominal delay of the at least one ring oscillator at a corner condition, and D W  is a delay through wiring of the at least one critical path at a corner condition. Other than the D RO  value, which is determined in real-time, all other variables of Equation 1 may be derived from static timing analyses, such as an end point timing report. 
         [0018]    Typically, the components of a critical path will be segregated according to their voltage thresholds or some other characteristic relevant to the delay attributable to a component. Equation 2 below shows such an embodiment, in which components of the critical path are grouped into HVT, SVT, and UVT components. Other groupings of critical path components are possible, of course, and are within the scope of the present invention. 
         [0000]    
       
         
           
             
               
                 
                   
                     D 
                     cp 
                   
                   = 
                   
                     ( 
                     
                       
                         
                           
                             
                               [ 
                               
                                 
                                   D 
                                   
                                     HVTC 
                                     cc 
                                   
                                 
                                 × 
                                 
                                   { 
                                   
                                     
                                       D 
                                       HVTRO 
                                     
                                     
                                       D 
                                       
                                         HVTRO 
                                         cc 
                                       
                                     
                                   
                                   } 
                                 
                               
                               ] 
                             
                             + 
                           
                         
                       
                       
                         
                           
                             
                               [ 
                               
                                 
                                   D 
                                   
                                     SVTC 
                                     cc 
                                   
                                 
                                 × 
                                 
                                   { 
                                   
                                     
                                       D 
                                       SVTRO 
                                     
                                     
                                       D 
                                       
                                         SVTRO 
                                         cc 
                                       
                                     
                                   
                                   } 
                                 
                               
                               ] 
                             
                             + 
                           
                         
                       
                       
                         
                           
                             
                               [ 
                               
                                 
                                   D 
                                   
                                     HVTC 
                                     cc 
                                   
                                 
                                 × 
                                 
                                   { 
                                   
                                     
                                       D 
                                       UVTRO 
                                     
                                     
                                       D 
                                       UVTRO 
                                     
                                   
                                   } 
                                 
                               
                               ] 
                             
                             + 
                             
                               D 
                               W 
                             
                           
                         
                       
                     
                     ) 
                   
                 
               
               
                 
                   Equation 
                    
                   
                       
                   
                    
                   2 
                 
               
             
           
         
       
     
         [0019]    In Equation 2, D cp  is the predicted critical path delay, D HVTC   cc  is the delay of HVT components of the critical path at a corner condition, D HVTRO  is the measured delay of HVT ring oscillators, D HVTRO   cc  is the delay of the HVT ring oscillators at a corner condition, D SVTC   cc  is the delay of SVT components of the critical path at a corner condition, D SVTRO  is the measured delay of SVT ring oscillators, D SVTRO   cc  is the delay of the SVT ring oscillators at a corner condition, D UVTC   cc  is the delay of UVT components of the critical path at a corner condition, D UVTRO  is the measured delay of UVT ring oscillators, D UVTRO   cc  is the delay of the UVT ring oscillators at a corner condition, and DW is the wire delay of the critical path. Other than the calculated Dcp and the measured delays of the HVT, SVT, and UVT ring oscillators, all other values may be derived from static timing analysis. Thus, by monitoring on-board ring oscillator frequency, a critical path delay can be predicted in real-time without the need to monitor the critical path itself. In addition, because the predicted critical path delay is calculated in real-time, its value will change with changes in chip parameters, such as process, voltage, and temperature. This is particularly useful in improving chip performance and efficiency using AVS. 
         [0020]    In addition to the wire delay shown in Equation 2, other variables not directly attributable to critical path components may be accounted for in the predicted critical path delays calculated according to the various embodiments of the invention. For example, it may be necessary or desirable to add a timing margin to account for known or expected inaccuracies in the measurements of delays, whether at a corner condition or during real-time monitoring of ring oscillator frequencies. In other cases, it may be necessary or desirable to add a technology margin account, for example, for known or expected differences between expected and actual voltages applied to a chip. Each of these variables is shown in Equation 3, below, wherein a is a timing margin and β is a technology margin. 
         [0000]    
       
         
           
             
               
                 
                   
                     D 
                     cp 
                   
                   = 
                   
                     ( 
                     
                       
                         
                           
                             
                               [ 
                               
                                 
                                   D 
                                   
                                     HVTC 
                                     cc 
                                   
                                 
                                 × 
                                 
                                   { 
                                   
                                     
                                       D 
                                       HVTRO 
                                     
                                     
                                       D 
                                       
                                         HVTRO 
                                         cc 
                                       
                                     
                                   
                                   } 
                                 
                               
                               ] 
                             
                             + 
                           
                         
                       
                       
                         
                           
                             
                               [ 
                               
                                 
                                   D 
                                   
                                     SVTC 
                                     cc 
                                   
                                 
                                 × 
                                 
                                   { 
                                   
                                     
                                       D 
                                       SVTRO 
                                     
                                     
                                       D 
                                       
                                         SVTRO 
                                         cc 
                                       
                                     
                                   
                                   } 
                                 
                               
                               ] 
                             
                             + 
                           
                         
                       
                       
                         
                           
                             
                               [ 
                               
                                 
                                   D 
                                   
                                     HVTC 
                                     cc 
                                   
                                 
                                 × 
                                 
                                   { 
                                   
                                     
                                       D 
                                       UVTRO 
                                     
                                     
                                       D 
                                       
                                         UVTRO 
                                         cc 
                                       
                                     
                                   
                                   } 
                                 
                               
                               ] 
                             
                             + 
                             
                               D 
                               W 
                             
                             + 
                             α 
                             + 
                             β 
                           
                         
                       
                     
                     ) 
                   
                 
               
               
                 
                   Equation 
                    
                   
                       
                   
                    
                   3 
                 
               
             
           
         
       
     
         [0021]    As will be understood by one skilled in the art, in most cases, a predicted delay will be desired for not one, but many critical paths on a chip. As a consequence, what is most appropriate for purposes of AVS will typically be the longest predicted critical path delay. For example, the critical path slack (S cp ) can be calculated using the longest predicted critical path delay according to Equation 4 below, in which F sys  is the system frequency. 
         [0000]    
       
         
           
             
               
                 
                   
                     S 
                     cp 
                   
                   = 
                   
                     
                       ( 
                       
                         1 
                         
                           F 
                           sys 
                         
                       
                       ) 
                     
                     - 
                     
                       longest 
                        
                       
                           
                       
                        
                       
                         D 
                         cp 
                       
                     
                   
                 
               
               
                 
                   Equation 
                    
                   
                       
                   
                    
                   4 
                 
               
             
           
         
       
     
         [0022]    In addition, the critical path slack (S cp ) can be multiplied by the maximum delay to voltage coefficient (DVC) for the technology to yield the control feedback voltage adjust (CFV), as in Equation 5 below. 
         [0000]      CFV= S   cp ×DVC   Equation 5
 
         [0023]      FIG. 3  shows a flow diagram of a method according to an embodiment of the invention. At S 1 , component delay(s), wire delay, and ring oscillator delay(s) at a corner condition are obtained from static timing analyses. As noted above, these values can be obtained, for example, from an end point timing report. 
         [0024]    At S 2 , on-board ring oscillator delay(s) is/are determined in real-time. As noted above, this real-time determination accounts for chip parameters affecting critical path delay, such as process, voltage, and temperature. Using the values obtained at S 1  and the delay(s) determined at S 2 , a predicted critical path delay can be calculated at S 3 . 
         [0025]    While S 1  thorough S 3  are shown relative to a single critical path, as noted above, predicted critical path delays will typically be calculated for a plurality of critical paths using ring oscillator delays determined simultaneously or substantially simultaneously at S 2 . The critical path delay(s) calculated at S 3  may be calculated, for example, according to Equation 2 above. At S 4 , a timing margin and/or technology margin may optionally be added to the critical path delay(s) calculated at S 3 . For example, a timing margin and technology margin may be included in the calculated critical path delay(s) using Equation 3 above. 
         [0026]    Additional steps may be taken where the calculated critical path delay(s) will be used in AVS. At S 5 , the longest critical path calculated at S 3  (and/or S 4 ) is determined. At S 6  and S 7 , a critical path slack and control feedback voltage adjust, respectively, may be calculated, as described above. 
         [0027]      FIG. 4  shows an illustrative environment  116  for predicting a critical path delay according to an embodiment of the invention. Environment  116  includes a computer system  120  that can perform a process described herein in order to predict a critical path delay. In particular, computer system  120  is shown including a critical path delay prediction program  130 , which makes computer system  120  operable to predict a critical path delay by performing a process described herein. 
         [0028]    Computer system  120  is shown including a processing component  122  (e.g., one or more processors), a storage component  124  (e.g., a storage hierarchy), an input/output (I/O) component  126  (e.g., one or more I/O interfaces and/or devices), and a communications pathway  128 . In general, processing component  122  executes program code, such as critical path delay prediction program  130 , which is at least partially fixed in storage component  124 . While executing program code, processing component  122  can process data, which can result in reading and/or writing transformed data from/to storage component  124  and/or I/O component  126  for further processing. Communications pathway  128  provides a communications link between each of the components in computer system  120 . I/O component  126  can comprise one or more human I/O devices, which enable a human user  118  to interact with computer system  120  and/or one or more communications devices to enable a system user  118  to communicate with computer system  120  using any type of communications link. To this extent, critical path delay prediction program  130  can manage a set of interfaces (e.g., graphical user interface(s), application program interface, and/or the like) that enable human and/or system users  118  to interact with critical path delay prediction program  130 . Further, critical path delay prediction program  130  can manage (e.g., store, retrieve, create, manipulate, organize, present, etc.) the data, such as static timing analysis data  140  and/or ring oscillator delay data  142  using any solution. 
         [0029]    In any event, computer system  120  can comprise one or more general purpose computing articles of manufacture (e.g., computing devices) capable of executing program code, such as critical path delay predicition program  130 , installed thereon. As used herein, it is understood that “program code” means any collection of instructions, in any language, code or notation, that cause a computing device having an information processing capability to perform a particular action either directly or after any combination of the following: (a) conversion to another language, code or notation; (b) reproduction in a different material form; and/or (c) decompression. To this extent, critical path delay prediction program  130  can be embodied as any combination of system software and/or application software. 
         [0030]    Further, critical path delay prediction program  130  can be implemented using a set of modules  132 . In this case, a module  132  can enable computer system  120  to perform a set of tasks used by critical path delay prediction program  130 , and can be separately developed and/or implemented apart from other portions of critical path delay prediction program  130 . As used herein, the term “component” means any configuration of hardware, with or without software, which implements the actions described in conjunction therewith using any solution, while the term “module” means program code that enables a computer system  120 , such as a general purpose computing device, to implement the actions described in conjunction therewith using any solution. When fixed in a storage component  124  of a computer system  120  that includes a processing component  122 , a module is a substantial portion of a component that implements the actions. Regardless, it is understood that two or more components, modules, and/or systems may share some/all of their respective hardware and/or software. Further, it is understood that some of the functionality discussed herein may not be implemented or additional functionality may be included as part of computer system  120 . 
         [0031]    When computer system  120  comprises multiple computing devices, each computing device can have only a portion of critical path delay prediction program  130  fixed thereon (e.g., one or more modules  132 ). However, it is understood that computer system  120  and critical path delay prediction program  130  are only representative of various possible equivalent computer systems that may perform a process described herein. To this extent, in other embodiments, the functionality provided by computer system  120  and critical path delay prediction program  130  can be at least partially implemented by one or more computing devices that include any combination of general and/or specific purpose hardware with or without program code. In each embodiment, the hardware and program code, if included, can be created using standard engineering and programming techniques, respectively. 
         [0032]    Regardless, when computer system  120  includes multiple computing devices, the computing devices can communicate over any type of communications link. Further, while performing a process described herein, computer system  120  can communicate with one or more other computer systems, such as a system user  118 , using any type of communications link. In either case, the communications link can comprise any combination of various types of wired and/or wireless links; comprise any combination of one or more types of networks; and/or utilize any combination of various types of transmission techniques and protocols. 
         [0033]    As discussed herein, critical path delay prediction program  130  enables computer system  120  to predict a delay of a critical path. To this extent, critical path delay prediction program  130  is configured to enable computer system  120  to manage static timing analysis data  140  and ring oscillator delay data  142 , which computer system  120  can process to predict a critical path delay. In an embodiment of the invention, static timing analysis data  140  comprises a set of data representing the results of a static timing analysis of a critical path for which a delay will be predicted. 
         [0034]    In another embodiment, the invention provides a method that performs the process steps of the invention on a subscription, advertising, and/or fee basis. That is, a service provider could offer to predict a delay of a critical path, as described above. In this case, the service provider can create, maintain, support, etc., a computer infrastructure, such as computer system  120 , that performs the process steps of the invention for one or more customers. In return, the service provider can receive payment from the customer(s) under a subscription and/or fee agreement and/or the service provider can receive payment from the sale of advertising space to one or more third parties. 
         [0035]    In still another embodiment, the invention provides a method of generating a system for predicting a delay of a critical path. In this case, a computer infrastructure, such as computer system  120 , can be obtained (e.g., created, maintained, having made available to, etc.) and one or more systems for performing the process steps of the invention can be obtained (e.g., created, purchased, used, modified, etc.) and deployed to the computer infrastructure. To this extent, the deployment of each system can comprise one or more of (1) installing program code on a computer system, such as computer system  120 , from a computer-readable medium; (2) adding one or more computer systems to the computer infrastructure; and (3) incorporating and/or modifying one or more existing systems of the computer infrastructure, to enable the computer infrastructure to perform the process steps of the invention. 
         [0036]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a”, “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
         [0037]    The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.