Abstract:
Techniques for reducing a voltage swing are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for reducing a voltage swing comprising: a plurality of dynamic random access memory cells arranged in arrays of rows and columns, each dynamic random access memory cell including one or more memory transistors. The one or more memory transistors of the apparatus for reducing a voltage swing may comprise: a first region coupled to a source line, a second region coupled to a bit line, a first body region disposed between the first region and the second region, wherein the first body region may be electrically floating, and a first gate coupled to a word line spaced apart from, and capacitively coupled to, the first body region. The apparatus for reducing a voltage swing may also comprise a first voltage supply coupled to the source line configured to supply a first voltage and a second voltage to the source line, wherein a difference between the first voltage and the second voltage may be less than 3.5V.

Description:
FIELD OF THE DISCLOSURE 
     The present disclosure relates generally to semiconductor dynamic random access memory (“DRAM”) devices and, more particularly, to techniques for reducing a voltage swing in a semiconductor dynamic random access memory (“DRAM”) device. 
     BACKGROUND OF THE DISCLOSURE 
     There is a continuing trend to employ and/or fabricate advanced integrated circuits using techniques, materials, and devices that improve performance, reduce leakage current, and enhance overall scaling. Semiconductor-on-insulator (SOI) is a material which may be used to fabricate such integrated circuits. Such integrated circuits are known as SOI devices and may include, for example, partially depleted (PD) devices, fully depleted (FD) devices, multiple gate devices (for example, double or triple gate), and Fin-FET devices. 
     A semiconductor dynamic random access memory (“DRAM”) device may include an electrically floating body in which electrical charges may be stored. The electrical charges stored in the electrically floating body may represent a logic high or binary “1” data state or a logic low or binary “0” or data state. 
     In one conventional technique, a memory cell having one or more memory transistors may be read by applying a bias to a drain region of a memory transistor, as well as a bias to a gate of the memory transistor that is above a threshold voltage of the memory transistor. As such, conventional reading techniques sense an amount of channel current provided/generated in response to the application of the bias to the gate of the memory transistor to determine a state of the memory cell. For example, an electrically floating body region of the memory cell may have two or more different current states corresponding to two or more different logical states (e.g., two different current conditions/states corresponding to two different logics: binary “0” data state and binary “1” data state). 
     Also, conventional writing techniques for memory cells having an N-Channel type memory transistor typically result in an excess of majority charge carriers by channel impact ionization or by band-to-band tunneling (gate-induced drain leakage “GIDL”). The majority charge carriers may be removed via drain side hole removal, source side hole removal, or drain and source hole removal, for example, using back gate pulsing. 
     Often, conventional reading and writing techniques may lead to relatively large power consumption and large voltage swings which may cause disruptions to memory cells on unselected rows. Also, pulsing between positive and negative gate biases during read and write operations may reduce a net quantity of charge carriers in a body region of a memory cell in a semiconductor DRAM device, which, in turn, may gradually eliminate data stored in the memory cell. In the event that a negative voltage is applied to a gate of a memory cell transistor, thereby causing a negative gate bias, a channel of minority charge carriers beneath the gate may be eliminated. However, some of the minority charge carriers may remain “trapped” in interface defects. Some of the trapped minority charge carriers may recombine with majority charge carriers, which may be attracted to the gate, and the net charge in majority charge carriers located in the floating body region may decrease over time. This phenomenon may be characterized as charge pumping, which is a problem because the net quantity of charge carriers may be reduced in the memory cell, which, in turn, may gradually eliminate data stored in the memory cell. 
     In view of the foregoing, it may be understood that there are significant problems and shortcomings associated with reading from and/or writing to semiconductor dynamic random access memory (“DRAM”) devices using conventional current sensing technologies. 
     SUMMARY OF THE DISCLOSURE 
     Techniques for reducing a voltage swing are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for reducing a voltage swing comprising: a plurality of dynamic random access memory cells arranged in arrays of rows and columns, each dynamic random access memory cell including one or more memory transistors. The one or more memory transistors of the apparatus for reducing a voltage swing may comprise: a first region coupled to a source line, a second region coupled to a bit line, a first body region disposed between the first region and the second region, wherein the first body region may be electrically floating, and a first gate coupled to a word line spaced apart from, and capacitively coupled to, the first body region. The apparatus for reducing a voltage swing may also comprise a first voltage supply coupled to the source line configured to supply a first voltage and a second voltage to the source line, wherein a difference between the first voltage and the second voltage may be less than 3.5V. 
     In accordance with other aspects of this particular exemplary embodiment, the first voltage may be supplied during a holding operation. 
     In accordance with further aspects of this particular exemplary embodiment, the second voltage may be supplied during at least one of a writing operation and a reading operation. 
     In accordance with additional aspects of this particular exemplary embodiment, the first voltage may be approximately in a range of 0.5V to 1.5V. 
     In accordance with yet another aspect of this particular exemplary embodiment, the second voltage may be approximately in a range of 2.5V to 3.5V. 
     In accordance with still another aspect of this particular exemplary embodiment, the difference between the first voltage and the second voltage may be less than 2V. 
     In accordance with further aspects of this particular exemplary embodiment, the apparatus for reducing a voltage swing may further comprise a second voltage supply coupled to the bit line configured to supply a third voltage and a fourth voltage to the bit line. 
     In accordance with additional aspects of this particular exemplary embodiment, the third voltage may be supplied during a holding operation. 
     In accordance with another aspect of this particular exemplary embodiment, the fourth voltage may be supplied during at least one of a writing operation and a reading operation. 
     In accordance with other aspects of this particular exemplary embodiment, the third voltage may be approximately the same as the first voltage. 
     In accordance with further aspects of this particular embodiment, the fourth voltage may be approximately in a range of 0V to 0.5V. 
     In accordance with additional aspects of this particular exemplary embodiment, the apparatus for reducing a voltage swing may further comprise a third voltage supply coupled to the word line configured to supply a fifth voltage and a sixth voltage to the word line. 
     In accordance with yet another aspect of this particular exemplary embodiment, the fifth voltage may be supplied during a holding operation. 
     In accordance with other aspects of this particular exemplary embodiment, the sixth voltage may be supplied during at least one of a writing operation and a reading operation. 
     In accordance with further aspects of this particular embodiment, the fifth voltage may be approximately −1.2V. 
     In accordance with additional aspects of this particular exemplary embodiment, the sixth voltage may be approximately in a range of 0.5V to −0.5V. 
     In another particular exemplary embodiment, the techniques may be realized as a method for reducing a voltage swing comprising the steps of: arranging a plurality of dynamic random access memory cells in arrays of rows and columns, each dynamic random access memory cell including one or more memory transistors. The one or more memory transistors of the method for reducing a voltage swing may comprise: a first region coupled to a source line, a second region coupled to a bit line, a first body region disposed between the first region and the second region, wherein the first body region may be electrically floating and charged to a first predetermined voltage potential, and a first gate coupled to a word line spaced apart from, and capacitively coupled to, the first body region. The method for reducing a voltage swing may also comprise supplying a first voltage and a second voltage to the source line, wherein a difference between the first voltage and the second voltage may be less than 3.5V. 
     In accordance with other aspects of this particular exemplary embodiment, supplying a first voltage may be during a holding operation. 
     In accordance with further aspects of this particular embodiment, supplying a second voltage may be during at least one of a writing operation and a reading operation. 
     In accordance with additional aspects of this particular exemplary embodiment, the first voltage may be approximately in a range of 0.5V to 1.5V. 
     In accordance with yet another aspect of this particular exemplary embodiment, the second voltage may be approximately in a range of 2.5V to 3.5V. 
     In accordance with other aspects of this particular exemplary embodiment, the difference between the first voltage and the second voltage may be less than 2V. 
     In accordance with further aspects of this particular embodiment, the method for reducing a voltage swing may further comprise supplying a third voltage and a fourth voltage to the bit line. 
     In accordance with additional aspects of this particular exemplary embodiment, supplying a third voltage may be during a holding operation. 
     In accordance with yet another aspect of this particular exemplary embodiment, supplying a fourth voltage may be during at least one of a writing operation and a reading operation. 
     In accordance with other aspects of this particular exemplary embodiment, the third voltage may be approximately same as the first voltage. 
     In accordance with further aspects of this particular exemplary embodiment, at least one processor readable medium for storing a computer program of instructions configured to be readable by at least one processor for instructing the at least one processor to execute a computer process for performing the method for reducing a voltage swing. 
     In another particular exemplary embodiment, the techniques for reducing a voltage swing may be realized as an article of manufacture for reducing a voltage swing, the article of manufacture comprising: at least one processor readable medium, and instructions carried on the at least one medium, wherein the instructions are configured to be readable from the at least one medium by at least one processor. The at least one processor to operate so as to: arranging a plurality of dynamic random access memory cells in arrays of rows and columns, each dynamic random access memory cell. The one or more memory transistors may comprise: a first region coupled to a source line, a second region coupled to a bit line, a first body region disposed between the first region and the second region, wherein the first body region may be electrically floating and charged to a first predetermined voltage potential, a first gate coupled to a word line spaced apart from, and capacitively coupled to, the first body region. Also, the at least one processor may operate so as to: supplying a first voltage and a second voltage to the source line, wherein difference between the first voltage and the second voltage may be less than 3.5V. 
     The present disclosure will now be described in more detail with reference to exemplary embodiments thereof as shown in the accompanying drawings. While the present disclosure is described below with reference to exemplary embodiments, it should be understood that the present disclosure is not limited thereto. Those of ordinary skill in the art having access to the teachings herein will recognize additional implementations, modifications, and embodiments, as well as other fields of use, which are within the scope of the present disclosure as described herein, and with respect to which the present disclosure may be of significant utility. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       In order to facilitate a fuller understanding of the present disclosure, reference is now made to the accompanying drawings, in which like elements are referenced with like numerals. These drawings should not be construed as limiting the present disclosure, but are intended to be exemplary only. 
         FIG. 1A  shows a schematic representation of a semiconductor DRAM array including a plurality of memory cells in accordance with an embodiment of the present disclosure. 
         FIG. 1B  shows a three-dimensional view of a memory cell in accordance with an embodiment of the present disclosure. 
         FIG. 1C  shows a cross-sectional view along line C-C′ of the memory cell of  FIG. 1B  in accordance with an embodiment of the present disclosure. 
         FIGS. 2A and 2B  show a schematic charge relationship, for a given data state, of the floating body, source region, and drain regions of a memory cell in accordance with an embodiment of the present disclosure. 
         FIGS. 3A and 3B  show schematic block diagrams of embodiments of a semiconductor DRAM device including, memory cell arrays, data sense and write circuitry, memory cell selection, and control circuitry in accordance with an embodiment of the present disclosure. 
         FIG. 4  shows an exemplary embodiment of a memory array having a plurality of memory cells and employing a separate source line configuration for each row of memory cells in accordance with an embodiment of the present disclosure. 
         FIG. 5  shows a diagram of voltage control signals to implement a write operation for logic high or binary “1” data state into a memory cell in accordance with an embodiment of the present disclosure. 
         FIG. 6  shows a diagram of voltage control signals to implement a write operation for logic low or binary “0” data state into a memory cell in accordance with an embodiment of the present disclosure. 
         FIG. 7  shows a diagram of voltage control signals to implement a read operation of a memory cell in accordance with an embodiment of the present disclosure. 
         FIG. 8  shows control signal information (temporal and amplitude) to implement a read/write operation in accordance with an embodiment of the present disclosure. 
         FIG. 9  shows a schematic of a memory array implementing the structure and techniques having a common source line in accordance with an embodiment of the present disclosure. 
         FIG. 10  shows control signal information (temporal and amplitude) to implement a read/write operation in accordance with an embodiment of the present disclosure. 
         FIG. 11  shows a schematic circuit diagram of a voltage driver in accordance with an embodiment of the present disclosure. 
         FIG. 12  shows a diagram of voltage control signals to implement a write operation into a memory cell in accordance with an embodiment of the present disclosure. 
         FIG. 13  shows control signal information (temporal and amplitude) to implement a read/write operation in accordance with an embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
     There are many embodiments described and illustrated herein. In one aspect, the present disclosure is directed to a combination of reading/writing methods which allows relatively low power consumption and provides a relatively low voltage swing and thus reduces disruptions to unselected memory cells. 
     Referring to  FIGS. 1A ,  1 B, and  1 C, a semiconductor DRAM device  10  (e.g., a logic or discrete memory device) including one or more memory cells  12  including a memory transistor  14  having an electrically floating body (e.g., an N-channel type transistor or a P-channel type transistor). The memory transistor  14  includes a source region  20 , a drain region  22 , a body region  18  disposed between the source region  20  and the drain region  22 , wherein the body region  18  is electrically floating, and a gate  16  disposed over the body region  18 . Moreover, the body region  18  may be disposed on or above region  24 , which may be an insulation region (e.g., in an SOT material/substrate) or non-conductive region (e.g., in a bulk-type material/substrate). The insulation or non-conductive region  24  may be disposed on substrate  26 . 
     Data may be written into a selected memory cell  12  by applying suitable control signals to a selected word line  28 , a selected source line  30 , and/or a selected bit line  32 . The memory cell  12  may include (1) a first data state which is representative of a first amount of charges in the body region  18  of the memory transistor  14 , and (2) a second data state which is representative of a second amount of charges in the body region  18  of the memory transistor  14 . The semiconductor DRAM device  10  may further include data write circuitry (not shown), coupled to the memory cell  12 , to apply (i) first write control signals to the memory cell  12  to write the first data state therein and (ii) second write control signals to the memory cell  12  to write the second data state therein, wherein, in response to the first write control signals applied to the memory cell  12 , the memory transistor  14  may generate a first bipolar transistor current which substantially provides the first charge in the body region  18  of the memory transistor  14 . In response, charge carriers are accumulated in or emitted and/or ejected from electrically floating body region  18  wherein data states are defined by the amount of charge carriers accumulated within electrically floating body region  18 . The charge carriers accumulated on the electrically floating body  18  may represent a logic high (binary “1” data state) or a logic low or (binary “0” data state). 
     For example, the first write control signals may include a signal applied to the gate  16  and a signal applied to the source region  20  wherein the signal applied to the source region  20  may include a first voltage potential having a first amplitude and a second voltage potential having a second amplitude. In another exemplary embodiment, the first write control signals may include a signal applied to the gate  16  and a signal applied to the drain region  22  wherein the signal applied to the drain region  22  may include a first voltage potential having a first amplitude and a second voltage potential having a second amplitude. 
     Also, the second write signals may include a signal applied to the gate  16 , a signal applied to the source region  20 , and a signal applied to the drain region  22 . The signal applied to the drain region  22  may include a block voltage to prevent the first data state from being written into the memory transistor  14 . 
     In an exemplary embodiment, the memory cell  12  of semiconductor DRAM device  10  may operate by accumulating in or emitting/ejecting majority charge carriers  34  (e.g., electrons or holes) from the electrically floating body region  18  (e.g., N-Channel transistor illustrated in  FIGS. 2A and 2B ). In this regard, various write techniques may be employed to accumulate majority charge carriers  34  (in this example, holes) in electrically floating body  18  of the memory cell  12  by, for example, impact ionization near source region  20  and/or drain region  22  (See,  FIG. 2A ). The majority charge carriers  34  may be emitted or ejected from the electrically floating body  18  by, for example, forward biasing the source region  20 /electrically floating body  18  junction and/or the drain region  22 /electrically floating body  18  junction (See,  FIG. 2B ). 
     For example, a logic high (binary data state “1”) may correspond to, an increased concentration of majority charge carriers in the electrically floating body region  18  relative to an unwritten device and/or a device that is written with a logic low (binary data state “0”). In contrast, a logic low (binary “0” data state) may correspond to, for example, a reduced concentration of majority charge carriers in the electrically floating body region  18  relative to an unwritten device and/or a device that is written with a logic high (binary “1” data state). 
     The semiconductor DRAM device  10  may further include data sense circuitry (not shown), coupled to the memory cell  12 , to sense data state of the memory cell  12 . In response to read control signals applied to the memory cell  12 , the memory transistor  14  may generate a second bipolar transistor current which is representative of data state of the memory cell  12  and wherein the data sense circuitry may determine data state of the memory cell  12  at least substantially based on the second bipolar transistor current. 
     The read control signals may include a signal applied to the gate  16 , source region  20 , and drain region  22  to cause, force and/or induce the bipolar transistor current which is representative of data state of the memory cell  12 . The signal applied to the drain region  22  may include a positive voltage or a negative voltage. Indeed, one or more of the read control signals may include a constant or unchanging voltage amplitude. 
     In addition, the semiconductor DRAM device  10  may include a memory cell  12  array including a plurality of word lines (WL), a plurality of source lines (SL), a plurality of bit lines (BL), and a plurality of memory cells  12  arranged in a matrix of rows and columns. Each memory cell  12  may include a memory transistor  14 , wherein the memory transistor  14  may include a source region  20  coupled to an associated source line (SL), a drain region  22 , a body region  18  disposed between the source region  20 , and the drain region  22  coupled to an associated bit line (BL) wherein the body region  18  is electrically floating, and a gate  16  disposed over the body region  18  and coupled to an associated word line (WL). For example, the source region  20  of the memory transistor  14  of each memory cell  12  of a first row of memory cells may be connected to a first source line (SL). Also, the source region  20  of the memory transistor  14  of each memory cell  12  of a second row of memory cells is connected to the first source line (SL). In another exemplary embodiment, the source region  20  of the memory transistor  14  of each memory cell  12  of a second row of memory cells may be connected to a second source line (SL), and the source region  20  of the memory transistor  14  of each memory cell  12  of a third row of memory cells is connected to a third source line (SL). 
     Referring to  FIGS. 3A and 3B , show schematic block diagrams of a semiconductor DRAM device including, a memory cell array, data sense and write circuitry, memory cell selection and control circuitry in accordance with an embodiment of the present disclosure. The semiconductor DRAM device  10  may include an array having a plurality of memory cells  12  having a separate source line (SL) for each row of memory cells (a row of memory cells includes a common word line connected to the gates  16  of each memory cell  12  of the row), data write and sense circuitry  36 , and memory cell selection and control circuitry  38 . The data write and sense circuitry  36  may read data from and may write data to selected memory cells  12 . In an exemplary embodiment, data write and sense circuitry  36  may include a plurality of data sense amplifiers. Each data sense amplifier may receive at least one bit line (BL)  32  and an output of reference generator circuitry (for example, a current or voltage reference signal). For example, the data sense amplifier may be a cross-coupled type sense amplifier to sense the data state stored in memory cell  12  and/or write-back data into memory cell  12 . 
     The data sense amplifier may employ voltage and/or current sensing circuitry and/or techniques. In an exemplary embodiment, the data sense amplifier may employ a current sensing circuitry and/or techniques, a current sense amplifier may compare the current from the selected memory cell  12  to a reference current, for example, the current of one or more reference cells. From that comparison, it may be determined whether memory cell  12  contained a logic high (binary “1” data state, relatively more majority charge carriers  34  contained within the body region  18 ) or a logic low (binary “0” data state, relatively less majority charge carriers  34  contained within the body region  18 ). It may be appreciated by one having ordinary skill in the art, any type or form of data write and sense circuitry  36  (including one or more sense amplifiers, using voltage or current sensing techniques, to sense the data state stored in memory cell  12 ) to read the data stored in memory cells  12  and/or write data in memory cells  12  may be employed. 
     Also, memory cell selection and control circuitry  38  may select and/or enable one or more predetermined memory cells  12  to facilitate reading data therefrom and/or writing data thereto by applying control signals on one or more word lines (WL)  28  and/or source lines (SL)  30 . The memory cell selection and control circuitry  38  may generate such control signals using address data, for example, row address data. Moreover, memory cell selection and control circuitry  38  may include a word line decoder and/or driver. For example, memory cell selection and control circuitry  38  may include one or more different control/selection techniques (and circuitry therefor) to implement the memory cell selection technique. Such techniques, and circuitry therefor, are well known to those skilled in the art. Notably, all such control/selection techniques, and circuitry therefor, whether now known or later developed, are intended to fall within the scope of the present inventions. 
     In an exemplary embodiment, the semiconductor DRAM device  10  may implement a two step write operation whereby all the memory cells  12  of a given row are written to a predetermined data state by first executing a “clear” operation, whereby all of the memory cells  12  of the given row are written to logic low (binary “0” data state), and thereafter selected memory cells  12  of the row are selectively written to the predetermined data state (here logic high (binary “1” data state)). The present disclosure may also be implemented in conjunction with a one step write operation whereby selective memory cells of the selected row are selectively written to either logic high (binary “1” data state) or logic low (binary “0” data state) without first implementing a “clear” operation. 
     The memory array may employ any of the exemplary writing, holding, and/or reading techniques described herein. Moreover, exemplary voltage values for each of the control signals for a given operation (for example, writing, holding or reading), according to exemplary embodiments of the present disclosure, is also provided. 
     The memory transistors  14  may be comprised of N-channel, P-channel and/or both types of transistors. Indeed, circuitry that is peripheral to the memory array (for example, sense amplifiers or comparators, row and column address decoders, as well as line drivers (not illustrated herein) may include P-channel and/or N-channel type transistors. Where P-channel type transistors are employed as memory cells  12  in the memory array(s), suitable write and read voltages (for example, negative voltages) are well known to those skilled in the art in light of this disclosure. Accordingly, for sake of brevity, these discussions will not be repeated. 
     Referring to  FIG. 4 , shows an exemplary embodiment of a memory array having a plurality of memory cells and employing a separate source line configuration for each row of memory cells in accordance with an embodiment of the present disclosure. In an exemplary embodiment, memory cells  12  may be written using the two step operation wherein a given row of memory cells  12  are written to a first predetermined data state by first executing a “clear” operation (which, in this exemplary embodiment, a selected row  28   i  and/or all of the memory cells  12  of the given row are written or programmed to logic low (binary “0” date state)) and thereafter selected memory cells  12  may be written to a second predetermined data state (i.e., a selective write operation to the second predetermined data state). The “clear” operation may be performed by writing each memory cell  12  of the given row to a first predetermined data state (in this exemplary embodiment the first predetermined data state is logic low (binary “0” data state) using the inventive technique described above. 
     In particular, memory transistor  14  of each memory cell  12  of a given row (for example, memory cells  12   a - 12   d ) is controlled to store a majority charge carrier concentration in the electrically floating body region  18  of the transistor  14  which corresponds to a logic low (binary “0” data state). For example, control signals to implement a “clear” operation may be applied to the gate  16 , the source region  20 , and the drain region  22  of the memory transistor  14  of memory cells  12   a - 12   d . In an exemplary embodiment, a “clear operation” includes applying (i) 1.5V to the gate  16 , (ii) 0V to the source region  20 , and (iii) 0V to the drain region  22  of the memory transistor  14 . In response, the same logic state (for example, logic low (binary “0” data state)) may be stored in memory cells  12   a - 12   d  and the state of memory cells  12   a - 12   d  may be “cleared”. For example, it may be preferable to maintain the gate-to-source voltage below the threshold voltage of the transistor of memory cell  12  to further minimize or reduce power consumption. 
     Thereafter, selected memory cells  12  of a given row may be written to the second predetermined logic state. For example, the memory transistors  14  of certain memory cells  12  of a given row may be written to the second predetermined logic state in order to store the second predetermined logic state in memory cells  12 . For example, memory cells  12   b  and  12   c  may be written to logic high (binary “1” data state) (as shown in a second selected row  28   i+1 ), via an impact ionization effect and/or avalanche multiplication, by applying (i) −2.0V to the gate (via word line  28   i ), (ii) −2.0V to the source region (via source line  30   i ), and (iii) 1.5V to the drain region (via bit line  32   j+1  and  32   j+2 ). Particularly, such control signals may generate or provide a bipolar current in the electrically floating body region  18  of the memory transistor  14  of memory cell  12 . The bipolar current may cause or produce impact ionization and/or the avalanche multiplication phenomenon in the electrically floating body region  18  of the memory transistors  14  of memory cells  12   b  and  12   c . In this way, an excess of majority charge carriers may be provided and stored in the electrically floating body region  18  of the memory transistor  14  of memory cells  12   b  and  12   c  which corresponds to logic high (binary “1” data state). 
     In an exemplary embodiment, memory cells  12   a  and  12   d  (as shown in a second selected row  28   i+1 ) may be maintained at logic low (binary “0” data state) by applying a voltage to inhibit impact ionization to the drain region  22  of each memory cell  12   a  and  12   d . For example, applying 0V to the drain regions  22  of memory cells  12   a  and  12   d  (via bit lines  32   j  and  32   j+3 ) may inhibit impact ionization in memory cells  12   a  and  12   d  during the selective write operation for memory cells  12   b  and  12   c.    
     Also, memory cells  12  (as shown in a third selected row  28   i+3 ) may be selectively written to logic high (binary “1” data state) using the band-to-band tunneling (GIDL) method. As mentioned above, the band-to-band tunneling provides, produces and/or generates an excess of majority charge carriers in the electrically floating body  18  of the memory transistors  14  of each selected memory cell  12  (in this exemplary embodiment, memory cells  12   b  and  12   c ). For example, after implementing the “clear” operation, memory cells  12   b  and  12   c  may be written to logic high (binary “1” data state), via band-to-band tunneling, by applying (i) −3V to the gate  16  (via word line  28   i ), (ii) −0.5V to the source region  20  (via source line  30   i ), and (iii) 110V to the drain region  22  (via bit line  32   j+1  and  32   j+2 ). 
     A selected row of memory cells  12  may be read by applying a read control signals to the associated word line (WL)  28  and associated source lines (SL)  30  and sensing a signal (voltage and/or current) on associated bit lines (BL)  32 . In an exemplary embodiment, memory cells  12   a - 12   d  (e.g., as shown in a third selected row  28   i+3 ) may be read by applying (i) −0.5V to the gate  16  (via word line  28   i ) and (ii) 3.0V to the source region  20  (via source line  30   i ). The data write and sense circuitry  36  may read data state of the memory cells  12   a - 12   d  by sensing the response to the read control signals applied to word line  28   i  and source line  30   i . In response to the read control signals, memory cells  12   a - 12   d  may generate a bipolar transistor current which may be representative of data state of memory cells  12   a - 12   d . For example, memory cells  12   b  and  12   c  (which were earlier written to logic high (binary “1” data state)), in response to the read control signals, may generate a bipolar transistor current which is considerably larger than any channel current. In contrast, memory cells  12   a  and  12   d  (which were earlier programmed to logic low (binary “0” data state)), such control signals induce, cause and/or produce little to no bipolar transistor current (for example, a considerable, substantial or sufficiently measurable bipolar transistor current). The circuitry in data write and sense circuitry  36  to sense the data state (for example, a cross-coupled sense amplifier) senses the data state using primarily and/or based substantially on the bipolar transistor current. 
     Thus, in response to read control signals, the memory transistor  14  of each memory cell  12   a - 12   d  may generate a bipolar transistor current which is representative of the data state stored therein. The data sensing circuitry in data write and sense circuitry  36  may determine data state of memory cells  12   a - 12   d  based substantially on the bipolar transistor current induced, caused and/or produced in response to the read control signals. 
       FIG. 5  shows a diagram of voltage control signals to implement a write operation for logic high (binary “1” data state) into a memory cell  12  in accordance with an exemplary embodiment of the present disclosure. The control signals may be configured to provide a lower power consumption as well as a one step write whereby selective memory cells  12  of a selected row of memory cells  12  may be selectively written or programmed to either logic high (binary “1” data state) or logic low (binary “0” date state) without first implementing a “clear” operation. For example, the temporally varying control signals to implement the write logic high (binary “1” data state) operation include the voltage applied to the gate  16  (V gw“1” ) and the voltage applied to the drain region  22  (V dw“1” ). The binary “1” or “0” data states may be written to one or more selected memory cells  12  by applying appropriate bit line voltages. For example, during phase  1 , the drain voltage (V dw“1”1 ) may be applied to the drain region  22  (via, for example, the associated bit line) of the memory transistor  14  of the memory cell  12  before the gate voltage (V gw“1”1 ) may be applied to the gate  16  (via, for example, the associated word line), simultaneously thereto, or after the gate voltage (V gw“1”1 ) is applied to gate  16 . It is preferred that the drain voltage (V dw“1”1 ) include an amplitude which may be sufficient to maintain a bipolar current that is suitable for programming the memory cell  12  to logic high (binary “1” data state). From a relative timing perspective, it is preferred that the drain voltage (V dw“1”1 ) extend beyond/after or continue beyond the conclusion of the gate voltage (V gw“1”1 ), or extend beyond/after or continue beyond the time the gate voltage (V gw“1”1 ) is reduced, as illustrated in  FIG. 5  (see, Δt&gt;0). Therefore, majority charge carriers may be generated in the electrically floating body region  18  via a bipolar current and majority charge carriers may accumulate (and be stored) in a portion of the electrically floating body region  18  of the memory transistor  14  of the memory cell  12  that may be juxtaposed or near the gate dielectric (which is disposed between the gate  16  and the electrically floating body region  18 ). 
     Also illustrated in  FIG. 5 , during phase  2  of the writing operation, the gate voltage (V gw“1”2 ) may be equal to (or substantially equal to) the voltage applied to the gate  16  to implement a hold operation (V gh ) and the drain bias (V dw“1”2 ) may be equal to (or substantially equal to) the voltage applied to the drain region to implement a hold operation (V dh ). 
       FIG. 6  shows a diagram of voltage control signals to implement a write operation for logic low (binary “0” data state) into a memory cell in accordance with an embodiment of the present disclosure. The temporally varying control signals that may be implemented to write logic low (binary “0” data state) may include the voltage applied to the gate  16  (V gw“0” ) and the voltage applied to the drain region  22  (V dw“0” ). For example, during phase  1 , the control signal applied to the drain region  22  (V dw“0”1 ) may be applied before the control signal is applied to the gate  16  (V gw“0”1 ), or simultaneously thereto, or after the control signal is applied to the gate  16 . Particularly, the drain voltage (V dw“0”1 ) may include an amplitude which may be insufficient to maintain a bipolar current that is suitable for writing the memory cell  12  to logic high (binary “1” data state). From a relative timing perspective, it may be preferred that the drain voltage (V dw“0”1 ) extend beyond/after or continue beyond the conclusion of the gate voltage (V gw“0”1 ), or extend beyond/after or continue beyond the time the gate voltage (V gw“0”1 ) is reduced, as illustrated in  FIG. 6  (see, Δt&gt;0). For example, majority charge carriers may be generated in the electrically floating body region  18  via a bipolar current and majority charge carriers may be accumulated (and be stored) in a portion of the electrically floating body region  18  of the memory transistor  14  of the memory cell  12  that is juxtaposed or near the gate dielectric (which is disposed between the gate  16  and the electrically floating body region  18 ). 
     Like phase  2  of the write logic high (binary “1” data state) described above, during phase  2  of the write operation for logic low (binary “0” data state), the gate voltage (V gw“0”2 ) may be equal to (or substantially equal to) the voltage applied to the gate  16  to implement a hold operation (V gh ) and the drain bias (V dw“0”2 ) may be equal to (or substantially equal to) the voltage applied to the drain region  22  to implement a hold operation (V dh ). 
     In the preceding discussion pertaining to an exemplary write operation, the reference to a first phase and a second phase of a write operation was used for explanation purposes to highlight changes in voltage conditions of control signals in the exemplary embodiments. It may be advantageous, when writing binary “1” and “0” data states, to apply constant or non-changing voltages to gate  16 , drain region  22 , and/or source region  20  during or through what has been labeled as write phases  1  and  2 . 
       FIG. 7  shows a diagram of voltage control signals to implement a read operation of a memory cell in accordance with an embodiment of the present disclosure. For example, read control signals may be applied to the drain region  22  and the gate  16 . The voltage applied to the drain region  22  (V dr ) may be applied to drain region  22  before application of the voltage applied to the gate  16  (V gr ), simultaneously thereto, or after the voltage is applied to the gate  16 . Further, the drain voltage (V dr ) may cease or terminate before the gate voltage (V gr ), simultaneously thereto (as illustrated in  FIG. 7 ), or after the gate voltage (V gr ) may conclude or cease. 
     In an exemplary embodiment, during the read operation, a bipolar current is generated in memory cells  12  storing logic high (binary “1” data state) and little to no bipolar current is generated in memory cells  12  storing logic low (binary “0” data state). The data state may be determined primarily by, sensed substantially using and/or based substantially on the bipolar transistor current that is responsive to the read control signals and significantly less by the interface channel current component, which is less significant and/or negligible relatively to the bipolar component. 
     The writing and reading techniques described herein may be employed in conjunction with a plurality of memory cells  12  arranged in an array of memory cells. A memory array implementing the structure and techniques of the present inventions may be controlled and configured including a plurality of memory cells  12  having a separate source line (SL) for each row of memory cells  12  (a row of memory cells includes a common word line). The exemplary layouts or configurations (including exemplary control signal voltage values), in accordance to one or more exemplary embodiments of the present disclosure are shown, each consisting of the control signal waveforms and exemplary array voltages during one-step writing phase  1 , phase  2 , and reading. 
     Referring to  FIG. 8 , shows control signal information (temporal and amplitude) to implement a read/write operation in accordance with an embodiment of the present disclosure. For example, the temporally varying control signals to implement a write operation may include (i) a voltage applied to the gate  16  (V gw ) via the associated word line (WL), (ii) a voltage applied to the source region  20  (V sw ) via the source line (SL), and (iii) a voltage applied to the drain region  22  (V dw ) via the associated bit line (BL). The binary “1” or “0” data states may be written to one or more selected memory cells  12  by applying appropriate bit line voltages. In an exemplary embodiment, logic high (binary “1” data state) may be written into a memory cell  12  by applying drain voltage (V dw“1” ) having an amplitude of 0.5V, and logic low (binary “0” data state) may be written into a memory cell  12  by applying the drain voltage (V dw“0” ) having an amplitude of 0V. In addition, during phase  1  of the write operation, the source voltage (V sw1 ) may include an amplitude of −2.5V and the gate voltage (V gw1 ) may include an amplitude of 2.5V. During phase  2  of the write operation, the source voltage (V sw2 ) may include an amplitude of −2.2V and the gate voltage (V gw2 ) may include an amplitude of −3.3V. For example, under these conditions, a bipolar current that is suitable for writing the memory cell  12  to logic high (binary “1” data state) may be provided. Moreover, under these conditions, little to no bipolar current is generated for writing the memory cell to logic low (binary “0” data state). 
     A row of memory cells (e.g.,  12   a - 12   d ) may be read in series and/or in parallel. In this embodiment, memory cells  12  are read by applying the following read control signals: (i) a voltage applied to the gate  16  (V gr ) via the associated word line (WL) and (ii) a voltage applied to the source (V sr ) via the source line (SL). The logic state of each memory cell (e.g.,  12   a - 12   d ) may be sensed, determined and/or sampled on the associated bit line (BL) ( 32   j - 32   j+3 , respectively). In particular, during the read operation, the gate voltage (V gr ) may include an amplitude of 0.5V and the source voltage (V sr ) may include an amplitude of 3.0V. 
     Notably, during the read operation, a bipolar current may be generated in memory cells  12  storing logic high (binary “1” data state) and little to no bipolar current may be generated in memory cells  12  storing logic low (binary “1” data state). The data state may be determined primarily by, sensed substantially using and/or based substantially on the bipolar transistor current that is responsive to the read control signals and significantly less by the interface channel current component, which is less significant and/or negligible relatively to the bipolar component. 
     Accordingly, the illustrated/exemplary voltage levels to implement the write and read operations are merely exemplary. The indicated voltage levels may be relative or absolute. Alternatively, the voltages indicated may be relative in that each voltage level, for example, may be increased or decreased by a given voltage amount (e.g., each voltage may be increased or decreased by 0.5V, 1.0V and 2.0V) whether one or more of the voltages (e.g., the source region voltage, the drain region voltage or gate voltage) become or are positive and negative. 
     Referring to  FIGS. 9 and 10 , show a schematic of a memory array implementing the structure and techniques having a common source line (SL) in accordance with an exemplary embodiment of the present disclosure. As mentioned above, the present disclosure may be implemented in any memory array architecture having a plurality of memory cells that employ memory transistors. For example, as illustrated in  FIGS. 9 and 10 , a memory array implementing the structure and techniques of the present disclosure may be controlled and configured having a common source line (SL) for every two rows of memory cells  12  (a row of memory cells  12  includes a common word line (WL)). An example (including exemplary control signal voltage values) according to certain aspects of the present disclosure may be also shown that consists of the control signal waveforms and exemplary array voltages during one-step writing phase  1 , phase  2 , and reading. 
     For example, the temporally varying control signals to implement the write operation may include (i) a voltage applied to the gate (V gw ) via the associated word line (WL) and (ii) a voltage applied to the drain region (V dw ) via the associated bit line (BL). The binary “1” or “0” data states may be written to one or more selected memory cells  12  by applying appropriate bit line voltages. Thereby, logic high (binary “1” data state) may be written into a memory cell  12  by applying drain voltage (V dw“1” ) having (i) an amplitude of 3V during phase  1  and (ii) an amplitude of 2.7V during phase  2 . Conversely, logic low (binary “0” data state) may be written into a memory cell by applying the drain voltage (V dw“0” ) having (i) an amplitude of 2.5V during phase  1  and (ii) an amplitude of 2.2V during phase  2 . In addition, during phase  1  of the write operation, the gate voltage (V gw1 ) may include an amplitude of 0V. During phase  2  of the write operation, the gate voltage (V gw2 ) may include an amplitude of −1.5V. The voltage applied to the source lines (SL) (and, as such, the source regions  20  of the memory transistors  14  of the row of memory cells  12 ) may be 0V. Under these conditions, a bipolar current that may be suitable for writing the memory cell to logic high (binary “1” data state) is provided. Moreover, little to no bipolar current is generated for programming the memory cell to logic low (binary “0” data state). 
     As noted above, in the preceding discussions pertaining to an exemplary write operation, the reference to a first phase and a second phase of a write operation was used for explanation purposes to highlight changes in voltage conditions of control signals in the exemplary embodiments. It may be advantageous, when writing binary “1” or “0” data states, to apply constant or non-changing voltages to gate  16 , drain region  22 , and/or source region  20  during or through what has been labeled as write phases  1  and  2 . 
     A row of memory cells (for example,  12   a - 12   d ) may be read in series and/or parallel. The memory cells  12  may be read by applying the following read control signals: (i) a voltage applied to the gate (V gr ) via the associated word line (WL) and (ii) a voltage applied to the drain (V dr ) via the associated bit line (BL). The logic state of each memory cell  12  (for example,  12   a - 12   d ) is sensed, determined, and/or sampled on the associated bit line (BL) ( 32   j - 32   j+3 , respectively). In particular, during the read operation, the gate voltage (V gr ) may include an amplitude of −0.5V and the drain voltage (V dr ) may include an amplitude of 3V. The voltage applied to the source lines (SL) (and, as such, the source regions  20  of the memory transistors  14  of the row of memory cells  12 ) is 0V. 
     As noted above, during the read operation, a bipolar current may be generated in those memory cells  12  storing logic high (binary “1” data state) and little to no bipolar current may be generated in those memory cells  12  storing logic low (binary “0” data state). The data state may be determined primarily by, sensed substantially using, and/or based substantially on the bipolar transistor current that is responsive to the read control signals and significantly less by the interface channel current component, which may be less significant and/or negligible relatively to the bipolar component. 
     It may be advantageous to employ a “holding” operation or condition for de-selected memory cells  12  (e.g., idle memory cells  12 ) in memory cell array to minimize and/or reduce the impact of the write/read operations for selected memory cells  12  (e.g., memory cells  12  being written to and/or read from) connected to word lines  28   i ,  28   i+1 ,  28   i+2 ,  28   i+3  and  28   i+4 . Referring to again to  FIGS. 4 and 9 , a holding voltage may be applied to the gates  16  of the memory transistors  14  of the de-selected memory cells  12  of memory cell array  10  (for example, memory cells  12  connected to word lines  28   i+1 ,  28   i+2 ,  28   i+3 , and  28   i+4 ). In a preferred exemplary embodiment, a holding voltage applied to the de-selected memory cells  12  may be approximate to an operation voltage applied to the selected memory cells  12  to perform the write/read operations. By applying a holding voltage approximate to an operation voltage for performing the write/read operations, the voltage swing between the holding voltage and the operation voltage may be reduced. By reducing the voltage swing between the holding voltage and the operation voltage, a power consumption may be reduced because (i) only voltage applied to selected bit lines (e.g., associated with the selected memory cells  12 ) may be varied, and (ii) the source line voltage swing (e.g., between holding condition and write/read operations) may be reduced. In addition, by reducing the voltage swing between the holding voltage and the operation voltage, a circuit size may be reduced, for example, reducing one or more components (e.g., reduce a number of transistors cascoded in series) for a source line driver. 
     Referring to  FIG. 11 , shows a schematic diagram of a voltage driver  110  in accordance with an embodiment of the present disclosure. In an exemplary embodiment, the voltage driver  110  may be arranged in an inverter circuit configuration and/or other circuit configurations having one or more transistors cascoded in series for generating one or more voltage potentials. As illustrated in  FIG. 11 , a ground (VSS) may be coupled to the voltage driver  110 . Conventionally, the ground (VSS) may be held at 0V during a holding operation or condition. In an exemplary embodiment, the voltage swing between the holding voltage and the operation voltage may be reduced by raising the voltage applied to the switch low supply (VSLHD) to a higher voltage (e.g., VSLHD&gt;0V) or a voltage potential similar to the operation voltage. For example, the voltage driver  110  may apply a holding voltage approximately in a range of 0.5V to 1.5V to the source region  20  and/or drain region  22  of each memory transistor  14  of the one or more de-selected memory cells  12  connected to word lines (WL)  28   i+1 ,  28   i+2 ,  28   i+3 , and  28   i+4 . 
     Referring to  FIG. 12 , shows a diagram of voltage control signals to implement a program or write operation into a memory cell in accordance with an embodiment of the present disclosure. The control signals may be configured to provide a low voltage swing between a holding operation or condition and/or a write operation and thus lower power consumption as well. For example, the temporally varying control signals to implement the write operation may include a voltage applied to the source region  20  (V sw ) a voltage applied to the gate (V gw ) and a voltage applied to the drain region  22  (V dw ). The binary “1” or “0” data states may be written to one or more selected memory cells  12  by applying appropriate bit line voltages. For example, a voltage swing between a holding voltage and a writing voltage may be reduced by raising the holding voltage and thus reducing power consumption. Also, during the holding operation or condition, a voltage applied to the source line (SL) and a voltage applied to the bit line (BL) may be the same as the voltage applied during a write operation in order to reduce the voltage swing. As illustrated in  FIG. 12 , during an initial holding operation or condition, the voltage applied to the source line (SL) and the voltage applied to the bit line (BL) may be 0.5V. Also during the initial holding operation or condition, a voltage may be in the range of −0.2V to −1.8V and applied to the word line (WL). 
     During a write logic low (binary “0” data state) phase, the control signal applied to the drain region  22  (V dw“0” ) may be applied before the control signal is applied to the gate  16  (V gw“0” ), or simultaneously thereto, or after the control signal is applied to the gate  16 . As shown in  FIG. 12 , by maintaining the holding voltage at 0.5V, the voltage swing between the control signal applied to the drain region  22  during the write operation and the control signal applied during the holding voltage may be reduced. The drain voltage (V dw“0” ) may include an amplitude which is insufficient to maintain a bipolar current that is suitable for writing the memory cell to logic high (binary “1” data state). From a relative timing perspective, it may be preferred that the drain voltage (V dw“0”1 ) extend beyond/after or continue beyond the conclusion of the gate voltage (V gw“0”1 ), or extend beyond/after or continue beyond the time the gate voltage (V gw“0”1 ) is reduced, as illustrated in  FIG. 12 . For example, majority charge carriers may be generated in the electrically floating body region  18  via a bipolar current and majority charge carriers may accumulate (and be stored) in a portion of the electrically floating body region  18  of the memory transistor  14  of the memory cell  12  that is juxtaposed or near the gate dielectric (which is disposed between the gate  16  and the electrically floating body region  18 ). 
     During a write logic high (binary “1” data phase) phase, the drain voltage (V dw“1” ) may be applied to the drain region  22  (via, for example, the associated bit line (BL)) of the memory transistor  14  of the memory cell  12  before the gate voltage (V gw“1” ) may be applied to the gate  16  (via, for example, the associated word line), simultaneously thereto, or after the gate voltage (V gw“1” ) is applied to gate  16 . As shown in  FIG. 12 , by maintaining the holding voltage at 0.5V, the voltage swing between the control signal applied to the drain region  22  during the writing operation and the control signal applied during the holding voltage may be reduced. It is preferred that the drain voltage (V dw“1” ) include an amplitude which may be sufficient to maintain a bipolar current that is suitable for programming the memory cell  12  to logic high (binary “1” data state). From a relative timing perspective, it is preferred that the drain voltage (V dw“1” ) extend beyond/after or continue beyond the conclusion of the gate voltage (V gw“1” ), or extend beyond/after or continue beyond the time the gate voltage (V gw“1” ) is reduced. Therefore, majority charge carriers may be generated in the electrically floating body region  18  via a bipolar current and majority charge carriers may be accumulated (and be stored) in a portion of the electrically floating body region  18  of the memory transistor  14  of the memory cell  12  that may be juxtaposed or near the gate dielectric (which is disposed between the gate  16  and the electrically floating body region  18 ). 
     During a mask write phase, the drain voltage (V dw“msk” ) may be applied to the drain region  22  (via, for example, the associated bit line) of the memory transistor  14  of the memory cell  12  before the gate voltage (V gw“1” ) may be applied to the gate  16  (via, for example, the associated word line), simultaneously thereto, or after the gate voltage (V gw“1” ) is applied to gate  16 . As shown in  FIG. 12 , by maintaining the holding voltage at 0.5V, the voltage swing between the control signal applied to the drain region  22  during the mask writing operation and control signal applied during the holding voltage may be reduced. 
     Referring to  FIG. 13 , shows control signal information (temporal and amplitude) to implement a write/read operation in accordance with an embodiment of the present disclosure. For example, the temporally varying control signals to implement a holding operation or condition may include (i) a voltage applied to the gate  16  via the associated word line (VWL HD ), (ii) a voltage applied to the source region  20  via the source line (VSL HD ), and (iii) a voltage applied to the drain region  22  via the associated bit line (VBL HD ). In an exemplary embodiment, in order to reduce a voltage swing between the holding voltage (e.g., for de-selected cells  12 ) and the operation voltage (e.g., for selected cells  12 ), a holding voltage applied to the word line (VWL HD ) may be −1.2V, a holding voltage applied to the source line (VSL HD ) may be 1.1V, and a holding voltage applied to the bit line (VBL HD ) may be 1.1V. 
     For example, the temporally varying control signals to implement a write operation may include (i) a voltage applied to the gate  16  via the associated word line (VWL WR ), (ii) a voltage applied to the source region  20  via the source line (VSL WR ), and (iii) a voltage applied to the drain region  22  via the associated bit line (VBL WR ). In an exemplary embodiment, binary “1” or “0” data states may be written to one or more selected memory cells  12  by applying appropriate bit line voltages. In an exemplary embodiment, logic high (binary “1” data state) may be written into a memory cell  12  by applying drain voltage (VBL WR“1” ) having an amplitude of 0.0V, and logic low (binary “0” data state) may be written into a memory cell  12  by applying the drain voltage (VBL WR“0” ) having an amplitude of 0.5V. Moreover, a mask writing operation may be employed by applying an appropriate bit line voltage (VBLMSK WR ). For example, a mask voltage applied to the bit line (VBLMSK WR ) may be 1.1V. In addition, during the writing operation, the voltage applied to the source voltage (VSL) may include an amplitude of 2.5V and the gate voltage (VWL WR ) may include an amplitude of 0.3V. Moreover, a control voltage may be applied to the word line (VWL MID ) in order to control a writing operation (e.g., writing a logic “1”). For example, the control voltage applied to the word line (VWL MID ) may be approximately −0.9V. 
     Also, the temporally varying control signals to implement a read operation may include (i) a voltage applied to the gate  16  via the associated word line (VWL RD ), (ii) a voltage applied to the source region  20  via the source line (VSL RD ), and (iii) a voltage applied to the drain region  22  via the associated bit line (VBL RD ). A row of memory cells (e.g.,  12   a - 12   d ) may be read in series and/or in parallel. The logic state of each memory cell (e.g.,  12   a - 12   d ) may be sensed, determined, and/or sampled on the associated bit line ( 32   j - 32   j+3 , respectively). In particular, during the read operation, the gate voltage (VWL RD ) may include an amplitude of 0.5V, the source voltage (VSL RD ) may include an amplitude of 2.5V, and the drain voltage (VBL RD ) may include an amplitude of 0V. Also, a mask read operation may be executed by applying a drain voltage (VBLMSK RD ) of approximately 1.1V. 
       FIG. 13  also illustrates a voltage applied to a word line (VWL GDL ) in order to reduce band-to-band tunneling (gate-induced drain leakage “GIDL”), as described above. For example, the voltage applied to the word line (VWL GDL ) may be approximately −0.9V. 
     Accordingly, the illustrated/exemplary voltage levels to implement the hold, write, and read operations are merely exemplary. The indicated voltage levels may be relative or absolute. Alternatively, the voltages indicated may be relative in that each voltage level, for example, may be increased or decreased by a given voltage amount (e.g., each voltage may be increased or decreased by 0.5V, 1.0V and 2.0V) whether one or more of the voltages (e.g., the source region voltage, the drain region voltage or gate voltage) become or are positive and negative. 
     At this point it should be noted that reducing a voltage swing in accordance with the present disclosure as described above typically involves the processing of input data and the generation of output data to some extent. This input data processing and output data generation may be implemented in hardware or software. For example, specific electronic components may be employed in a semiconductor DRAM device or similar or related circuitry for implementing the functions associated with reducing a voltage swing in accordance with the present disclosure as described above. Alternatively, one or more processors operating in accordance with instructions may implement the functions associated with reducing a voltage swing in accordance with the present disclosure as described above. If such is the case, it is within the scope of the present disclosure that such instructions may be stored on one or more processor readable media (e.g., a magnetic disk or other storage medium), or transmitted to one or more processors via one or more signals embodied in one or more carrier waves. 
     The present disclosure is not to be limited in scope by the specific embodiments described herein. Indeed, other various embodiments of and modifications to the present disclosure, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. Thus, such other embodiments and modifications are intended to fall within the scope of the present disclosure. Further, although the present disclosure has been described herein in the context of a particular implementation in a particular environment for a particular purpose, those of ordinary skill in the art will recognize that its usefulness is not limited thereto and that the present disclosure may be beneficially implemented in any number of environments for any number of purposes. Accordingly, the claims set forth below should be construed in view of the full breadth and spirit of the present disclosure as described herein.