Abstract:
A ferroelectric memory device includes a plurality of sets of bit lines which are connected to differential sense amplifiers and to a plurality of memory cells. Each memory cell contains one ferroelectric capacitor and one transistor, with a first electrode of the ferroelectric capacitor being connected to a plate line and the second electrode of the ferroelectric capacitor being connected to the source of the transistor. The gate of the transistor is connected to a word line and the drain is connected to a bit line. The memory cells generate a reference voltage which is provided to the differential sense amplifiers as a reference voltage for comparison with an data stored in the memory cells.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a ferroelectric memory device having a plurality of sets of bit lines, to which are connected a plurality of memory cells made up of one capacitor using a ferroelectric film and one MOS transistor, and differential sense amplifiers that can be connected to said bit lines. The ferroelectric memory device stores information by making the direction of polarization of the ferroelectric film correspond to binary information. 
     2. Description of the Related Art 
     In a ferroelectric memory device using a one-transistor one-capacitor type (lTlC type) memory cell, a reference voltage must be generated to determine whether data read from the memory cell is logic “0” or logic “1”. One type of device employs a dummy cell. One example of such a dummy cell construction is disclosed in Japanese Patent Laid-open No. 192476/95 and Japanese Patent Laid-open No. 93978/95. In this method, dummy cells are prepared in which logic “1” and “0” are respectively written to two ferroelectric capacitors, data are read from both dummy cells, and the reference potential is generated by averaging their values. 
     The method disclosed in Japanese Patent Laid-open No. 93978/95 will be described with reference to FIG.  1 . In the figure, logic “1” and “0” are written in dummy cells DMCa 1  and DMCa 2 , respectively. After precharging bit lines BLa 1  and BLa 2 , dummy cells DMCa 1  and DMCa 2  are selected by word lines DWLa 1  and DWLa 2 , and signal potentials corresponding to “1” and “0” are generated on bit lines BLa 1  and BLa 2 . Thereafter, transistor TSW 1  is rendered conductive by a bit line short-circuit signal to generate a voltage on the bit line corresponding to the midpoint between “1” and “0”. If a read from memory cell MCa 1  takes place after rendering transistor TSW 1  non-conductive and again precharging bit line BLa 1 , then bit line BLa 1  becomes a potential corresponding to “1” or “0” read from memory cell MCa 1  and bit line BLa 2  becomes a potential corresponding to the midpoint between “1” and “0”, thereby providing a one-transistor one-capacitor type ferroelectric memory device. Japanese Patent Laid-open No. 192476/95 discloses a construction in which the reference potential generated in a dummy cell is stored in an electronic memory unit to avoid subsequent generation of the reference potential. Thus, deterioration of the dummy cell due to film fatigue can be suppressed. 
     Other examples of dummy cell construction are disclosed in, for example, Japanese Patent Laid-open No. 301093/90 and U.S. Pat. No. 4,873,664 in which the size of the ferroelectric capacitor of dummy cells is made different from that of memory cells, in order to generate a reference potential. 
     The method disclosed in Japanese Patent Laid-open No. 301093/90 will be next described with reference to FIG.  2 . In the figure, a signal potential is generated on bit line BLal by selecting memory cell MCa 1  by means of word line WLa 1  and by driving plate line PLa 1 . Dummy cell DMCa 1  is selected by word line DWLa 1 , and a reference potential is generated on bit line BLa 2  by driving plate line DPLa  1 . The capacitor size in the dummy cell is made smaller than that of the memory cell, and moreover, the polarization direction is set such that polarization inversion always occurs when a reference potential is generated. In addition, CFa 1  is selected such that its capacitance when polarization is not inverted is smaller than the capacitance of DCFa 1  during polarization inversion. The capacitance of DCFa 1  is therefore smaller than the capacitance of CFa 1  during polarization inversion and greater than the capacitance when polarization is not inverted. A signal potential can thus be generated at BLa 2  that corresponds to the midpoint between logic “1” and “0”. Although the size of DCFa 1  is made smaller than that of CFa 1  in the above-described method, as disclosed in U.S. Pat. No. 4,873,664, the same effect can be obtained by both making DCFa 1  bigger than that of CFa 1  and by setting the direction of polarization such that polarization inversion never occurs when the reference potential is generated. 
     Another example of a dummy cell construction is described in Japanese Patent Laid-open No. 114741/93. In this example, a capacitor using a normal dielectric is employed as the capacitor of the dummy cell, and the accumulated charge of the dummy cell capacitor is used to boost the read-out signal potential such that the precharge potential is a potential corresponding to the midpoint between logic “1” and “0”. 
     This method will be described is detail with reference to FIG.  3 . In the figure, VCC/2 is supplied from the outside to one terminal of memory capacitor CFa 1 . Memory cell MCa 1  is selected by word line WLa 1 , and the signal potential is generated on bit line BLa 1 . Dummy cell capacitor DCa 1  is selected by dummy cell word line DWLa 1 , and boosts the potential of bit line BLa 1 . During a read operation, bit lines BLa 1  and Bla 2  are first precharged to VCC, following which word line WLa 1  is selected and data are read into the bit lines. Dummy cell word line DWLa 1  is then selected and the bit line potential is boosted. The capacitance used for the dummy cell at this time is such that the bit line potential when boosted is higher than the precharged potential when data is logic “1” and lower than the precharged potential when data is logic “0”. As a result, the precharge potential of BLa 2  is used as the reference potential, data can be sensed by sense amplifier SA. 
     In another method of generating a reference voltage, a reference voltage is generated in a memory cell without using a dummy cell. As an example, U.S. Pat. No. 5,086,412 discloses one such reference voltage self-generating system. According to this form, reads are carried out twice consecutively from the same memory cell, the charge read the second time being taken as the reference voltage. Explanation is presented using FIG. 4, FIG. 5, and FIG.  6  and citing the above-described U.S. Pat. No. 5,086,412. Memory cell MCa 1  is selected by word line WLa 1  after precharging bit line BLa 1 , and when plate line PLa 1  is strobed (returning to the initial state after the plate line is strobed), a charge ΔQ 1  is read on bit line BLa 1  by the transition from state A by way of state B to reach state C of FIG. 5 when the data is logic “1”. When the data is logic “0”, ΔQ 0 =0 is read on bit line BLa 1  because the transition is from state C to state B and then back to state C. The read charge is held in a sample &amp; hold circuit by making TG 1  “H”. A second read is then carried out with respect to the same cell. Because memory cell MCa 1  has been subjected to a destructive read, the second read charge is sure to be ΔQ 0 , and the charge at the second read is therefore the reference. The charge read with TG 2  at “H” is held in the sample &amp; hold circuit and data are subsequently sensed by differential sense amplifier with TG 3  as “H”. In addition, bias capacitor CBIAS is added to the reference-side bit line BLR of the differential sense amplifier to enable a correct reading operation even in a case in which ΔQ 0 =0 for both the first and second read charges. The addition of this bias capacitor CBIAS has the effect of adding an offset between the two inputs of the differential sense amplifier by changing the impedance of the bit line, thereby enabling a 1-transistor 1-capacitor type ferroelectric memory device that does not require a dummy cell. 
     The hysteresis characteristic of the ferroelectric shown in FIG. 22 deteriorates with increase in retention time or with ferroelectric film fatigue depending on the number of times the memory cell is accessed. In other words, the hysteresis loop of the ferroelectric film of a memory cell in which the hysteresis loop is repeatedly reversed decreases due to fatigue. FIG. 23 shows the effect upon the read bit line voltage brought about by increase in the number of access times due to this fatigue effect. In other words, in “1” reads, which accompany polarization inversion, the read voltage decreases with increase in the number of read operations, but the read voltage is fixed and unaffected by the number of read operations for “0” reads, in which polarization inversion does not occur. In addition, the “1” and “0” read bit line voltage changes according to the number of times of access as shown in FIG.  24  and FIG. 25 in cases in which the deterioration of hysteresis is imprinted, i.e., when voltage of only one direction is applied to the ferroelectric. In other words, when the bit line capacitance CB is large, “1” and “0” read voltage decreases with increase in the number of read operations. When the bit line capacitance CB is small, the “1” read voltage increases with the number of times of access, and the “0” read voltage decreases with the number of times of access. 
     Furthermore, the read bit line voltage also changes with increase in the retention time of data as shown in FIG. 26, the read voltage decreasing with retention time for “1” reads that accompany polarization inversion, and the read voltage being fixed with no dependency on retention time during “0” reads. 
     With regard to the first of the methods in which the reference voltage is generated using dummy cells, i.e., a method in which data are read from two dummy cells in which “1” and “0” are respectively written, the values averaged, and the reference voltage generated as shown in FIG. 1, there is a problem that an accurate reference voltage cannot be generated due to the difference in frequency of access between memory cells and dummy cells over a great number of times of use. The same problem exists for Japanese Patent Laid-open No. 192476/95. The same problem also exists with regard to the second dummy cell method, i.e., the method shown in FIG. 2 in which the size of the dummy cell capacitor is made to differ from that of the memory cell capacitor and this difference then used to generate a reference voltage. Moreover, this problem cannot be avoided even in the third dummy cell method, i.e., the method shown in FIG. 3 in which a normal dielectric film is used in the dummy cell capacitor. 
     In addition, the difficulty of designing the dummy cell capacitor size can be raised as another problem in the second dummy cell method (FIG.  2 ). This problem arises because the dummy cell capacitor size is determined by estimating the capacitance during inversion and non-inversion of polarization of the dummy cell capacitor based on an advance estimate of the capacitance of the memory cell capacitor. This problem also exists for the third dummy cell method, i.e., the case in which a normal dielectric film is used in the dummy cell capacitor as shown in FIG.  3 . 
     As yet another problem in the method of FIG. 4 in which reference voltage is generated within cells themselves without employing dummy cells, a precise reference voltage cannot be generated and the read margin of logic “1” becomes narrow. In concrete terms, the actual read charge for logic “1” is lower than ΔQ 1  in FIG. 5, and the charge that contributes to the reference voltage is greater than ΔQ 0 , resulting in the problem that the read margin of logic “1” becomes narrow in the unaltered prior-art example. This problem occurs because the effect of bit line capacitance is not considered among the principles of read-out in the prior-art example shown in FIG.  5 . The read operation of the prior art is next investigated again with proper consideration given to the bit line capacitance using FIG.  7 . In the figure, the straight line represents the load line arising from the bit line capacitance. When logic “1” is read, ΔQ 1  makes a transition on hysteresis from state A through B and actually reaching C, ΔQ 1  becoming the charge that is read and thus becoming a value lower than ΔQ 1  shown in FIG.  5 . After reading of logic “1”, moreover, the state makes a transition to C rather than to E as explained in the prior-art example, and the reference therefore becomes ΔQref 1 , which is greater than ΔQ 0  in a subsequent reference read. As a result, in some cases ΔQ 1 ≈ΔQref 1 , i.e., the charge at “1” reads and reference reads become nearly equal and the read margin narrows. In addition, a bias capacitor is provided in the prior-art method to correctly read logic “0”, thus establishing an offset between ΔQ 0  and ΔQref 0 . In states in which ΔQ 1 ≈ΔQref 1 , however, this offset causes erroneous operation in which a “1” read is read as “0”, and a correct read operation therefore cannot be expected in the prior-art method. 
     Yet another problem in the method shown in FIG. 4, in which the reference voltage is generated without using dummy cells, is slow access speed. This problem is caused by the large number of transitions of the plate line. In concrete terms, the plate line must make a transition from “L” to “H” and from “H” to “L” four times for a read of data from a memory cell and twice for rewriting in the prior-art example. The time constant is great because plate line wiring is generally long and a plurality of memory cells are connected. High-speed access therefore cannot be expected in the methods of the prior art. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a ferroelectric memory device having a highly reliable high-speed read circuit that solves the aforementioned problems relating to the method of generating a reference voltage that is necessary in a one-transistor one-capacitor type memory cell. 
     In the memory cell of the present invention, the first electrode of a capacitor using ferroelectric film is connected to a plate line, the second electrode is connected to the source of a MOS transistor, the gate of the MOS transistor is connected to the word line, and the drain is connected to the bit line. The memory cell includes means for self-generation of a reference voltage, and a sense amplifier senses memory cell data using the reference voltage self-generated by said memory cell as a standard. 
     According to the present invention, a precise voltage between logic “1” and “0” can always be generated as the reference voltage despite deterioration of the characteristics of the ferroelectric film and change in the read voltage, thereby eliminating the problem of inaccuracies in the reference voltage arising from variations that arise from fatigue of the ferroelectric film characteristic, imprint, or retention time. 
     Furthermore, logic “0” is written immediately prior to reading of the reference voltage, and a precise reference voltage can therefore always be generated and the read margin can always be maximized. 
     In addition, the number of times that the plate line voltage makes a transition from “L” to “H” or from “H” to “L” can be reduced from six to four as compared to the examples of the prior art, thereby allowing faster operation than in examples of the prior art. 
     Finally, the present invention eliminates the difficulties of designing dummy cell capacitor size because dummy cells are not necessary. 
     The above and other objects, features, and advantages of the present invention will become apparent from the following description based on the accompanying drawings which illustrate examples of preferred embodiments of the present invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of the prior art disclosed in Japanese Patent Laid-open No. 93978/95; 
     FIG. 2 is a circuit diagram of the prior art disclosed in Japanese Patent Laid-open No. 301093/90; 
     FIG. 3 is a circuit diagram of the prior art disclosed in Japanese Patent Laid-open No. 114741/93; 
     FIG. 4 is a circuit diagram of the prior art disclosed in U.S. Pat. No. 5,086,412; 
     FIG. 5 is a graph for explaining the method of generating reference voltage of FIG. 4; 
     FIG. 6 is a circuit diagram of the sense amplifier used in FIG. 4; 
     FIG. 7 is a graph for explaining the method of generating reference voltage of FIG. 4; 
     FIG. 8 is a circuit diagram of the ferroelectric memory device according to the first embodiment of the present invention; 
     FIG. 9 is a circuit diagram of the sense amplifier used in the ferroelectric memory device of FIG. 8; 
     FIG. 10 is a graph for explaining the operation of the first embodiment; 
     FIG. 11 is a timing chart showing the operation of the first embodiment; 
     FIG. 12 is a circuit diagram of the ferroelectric memory device according to the second embodiment of the present invention; 
     FIG. 13 is a graph for explaining the operation of the second embodiment; 
     FIG. 14 is a timing chart showing the operation of the second embodiment; 
     FIG. 15 is a circuit diagram of the ferroelectric memory device according to the third embodiment of the present invention; 
     FIG. 16 is a graph for explaining the operation of the third embodiment; 
     FIG. 17 is a timing chart showing the operation of the third embodiment; 
     FIG. 18 is a circuit diagram of the ferroelectric memory device according to the fourth embodiment of the present invention; 
     FIG. 19 is a graph for explaining the operation of the fourth embodiment; 
     FIG. 20 is a timing chart showing the operation of the fourth embodiment; 
     FIG. 21 is a circuit diagram of the ferroelectric memory device according to the fifth embodiment of the present invention; 
     FIG. 22 is a graph showing the hysteresis characteristic of a ferroelectric; 
     FIG. 23 is a graph showing the change in polarization charge of the ferroelectric with respect to the number of read-out operations; 
     FIG. 24 is a graph showing the change in polarization charge of the ferroelectric with respect to the number of read-out operations; 
     FIG. 25 is a graph showing the change in polarization charge of the ferroelectric with respect to the number of read-out operations; and 
     FIG. 26 is a graph showing the change in polarization charge of the ferroelectric with respect to retention time. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring now to FIG. 8, there is shown a ferroelectric memory device according to the first embodiment of the present invention. 
     Bit lines BL 11  and BL 21  and sense amplifier SA 1  that amplifies the potential difference of both bit lines and senses data are connected at one end of two adjacent bit lines BL 1  and BL 2  by way of four MOS transistors controlled by signals TG 1 , TG 2 , TG 3 , and TG 4 . Bit line BL 21  connected to sense amplifier SA 1  is longer than bit line BL 11  by an amount L. Bit lines BL 1  and BL 2  are precharged to the ground potential by bit line precharge signal PBLG 1 , and bit lines BL 11  and BL 21  are precharged to the ground potential by bit line precharge signal PBLG 0 . 
     Memory cell MC 1  is made up of ferroelectric capacitor CF 1  and cell transistor TC 1 . One terminal of ferroelectric capacitor CF 1  is connected to plate line PL 1 , and the other terminal is connected to either the source terminal or drain terminal of cell transistor TC 1 . The other source or drain terminal of cell transistor TC 1  is connected to bit line BL 2 , and the gate terminal is connected to word line WL 1 . The other memory cell MC 2  is of the same circuit configuration, and its construction and element size are also the same. 
     Sense amplifier SA 1  is a normal latch-type sense amplifier with MOS transistors controlled by signals SAPO and SAN 0  to prevent leakage of read charges to bit lines BL 1  and BL 2  when inactive. 
     The read operation of the circuit of FIG. 8 will be next explained with reference to FIGS. 10 and 11. Bit lines BL 1 , BL 2 , BL 11 , and BL 21  are first precharged to the ground potential by making bit line precharge signals PBLG 0  and PBLG 1  the “H” level. Next, data is read to bit lines BL 2  and BL 21  by making word line WL 1  “H” to select memory cell MC 1 , making plate line PL 1  “H” and holding, and making signal TG 2  “H”. When the data read from memory cell MC 1  is “1”, memory cell MC 1  transitions from state A to state C, and the bit line voltage becomes VBL 1 . When the data is logic “0”, memory cell MC 1  transitions from state B to state D and the bit line voltage becomes VBL 0 . Next, signal TG 2  is made “L” and bit line precharge signal PBLG 1  is made “H” to again precharge bit lines BL 1  and BL 2  to the ground potential. At this time, “0” is written to memory cell MC 1  because plate line PL 1  remains unchanged at “H”. Memory cell MC 1  hereupon transitions to state E, following which plate line PL 1  is made “L”, bit line precharge signal PBLG 1  is made “L”, to make the memory cell transition to state B. 
     Next, plate line PL 1  is made “H”, signal TG 3  is made “H”, to read the reference voltage from memory cell MC 1  to bit lines BL 2  and BL 11 . The capacitance of bit line BL 11 , however, is lower than that of bit line BL 21  by an amount CL, and memory cell MC 1  transitions from state B to state F and becomes bit line voltage Vref. Signal TG 3  is then made “L”. 
     Sense amplifier SA 1  is then activated to sense data by making signals SAP and SAN 0  “H” and making signal SAP 0  “L”. Reference voltage Vref is held in bit line BL 11  and voltage VBL 1  or VBL 0  corresponding to logic “1” or “0” is held in bit line BL 21 , whereby a difference between the voltage which is either VBL 1  or VBL 0  and the reference voltage V ref  is correctly amplified by sense amplifier SA 1  and to thereby correctly sense the data. 
     Data is next rewritten to memory cell MC 1  by making signal TG 2  “H” and plate line PL 1  “L”, following which sense amplifier SA 1  is deactivated by making signals SAP and SAN 0  “L” and making signal SAP 0  “H”. Bit line precharge signals PBLG 0  and PBLG 1  are then made “H” to discharge the bit line, and word line WL 1  is finally made “L” to complete the read operation. Regarding the load of bit line capacitance CL in this embodiment, the length of bit line BL 21  may be made the same as bit line BL 11  to add a capacitor having a capacitance of CL to bit line BL 21 . 
     FIG. 12 shows the second embodiment of the present invention. The constructions of memory cell MC 1 , sense amplifier SA 1 , and the four MOS transistors controlled by signals TG 1 , TG 2 , TG 3 , and TG 4  are the same as in the first embodiment. However, an offset-adding circuit OAC made up of four NMOS transistors controlled by signals OS 1  and OS 2  is connected to bit lines BL 11  and BL 21  as a means of providing an offset between the data of the first read and the reference voltage of the second read. 
     The read operation of the circuit of FIG. 12 will be next explained with reference to FIGS. 13 and 14. Bit lines BL 1 , BL 2 , BL 11 , and BL 21  are first precharged to the ground potential by making bit line precharge signals PBLGO and PBLG 1  “H”. Data is then read to bit lines BL 2  and BL 21  by making word line WL 1  “H” to select memory cell MC 1 , making plate line PL 1  “H”, and making signal TG 2  “H”. When the data read from memory cell MCi is “1”, memory cell MC 1  transitions from state A to state C and the bit line voltage becomes VBL 1 . When the data is logic “0”, memory cell MC 1  transitions from state B to state D and the bit line voltage becomes VBL 0 . Next, bit lines BL 1  and BL 2  are again precharged by making signal TG 2  “L” and bit line precharge signal PBLG 1  “H”. Logic “0” is then written to memory cell MC 1  because plate line PL 1  remains unchanged at “H”. Memory cell MC 1  then transitions to state E. After next making plate line PL 1  “L”, bit line precharge signal BLG 1  is made “L” to make memory cell MC 1  transition to state B. 
     Plate line PL 1  is next made “H” and signal TG 3  is made “H” to read the reference voltage from memory cell MC 1  to bit lines BL 2  and BL 11 . Memory cell MC 1  then transitions from state B to state D, and the bit line voltage becomes VBL 0 . TG 3  is then made “L”. 
     Sense amplifier SA 1  is next activated by making signals SAP, SAN 0 , and OS 2  “H” and making signal SAP 0  “L”, to sense the data. At this time, VBL 0  is held in bit line BL 11  as the reference voltage and voltage VBL 1  or VBL 0  corresponding to logic “1” or “0” is held in bit line BL 21 . Changing OS 2  to “H” is equivalent to increasing the size of W of the NMOS transistor on the bit line BL 21  side of sense amplifier SA 1 , thereby enabling the establishment of an offset between the voltage of bit line BL 11  and the voltage of bit line BL 21 , and sense amplifier SA 1  can thus operate appropriately and correctly sense the data. The data are then rewritten as in the first embodiment to complete the read operation. 
     FIG. 15 shows the third embodiment of the present invention. The constitutions of memory cell MC 1 , sense amplifier SA 1 , and the four MOS transistors controlled by signals TG 1 , TG 2 , TG 3 , and TG 4  are equivalent to those of the first embodiment. 
     The read operation of the circuit of FIG. 15 will be next explained with reference FIGS. 16 and 17. In FIG. 15, the present invention is implemented without the increase L in bit line length of FIG. 8 or providing the offst-adding circuit in FIG.  12 . The circuit operation is substantially the same as that of the first embodiment. In a case in which memory cell MC 1  is selected, however, signals TG 2  and TG 3  are made “H” simultaneously during a data read. Memory cell MC 1  thus transitions from state A to state C when data is logic “1” and transitions from state B to state D when the data is logic “0”. In addition, only signal TG 3  is made “H” during a reference read. This is equivalent to lightening the load line and memory cell MC 1  transitions from state B to state F. Voltage VBL 1  or VBL 0  corresponding to logic “1” or logic “0” is accordingly held in bit line BL 21  and reference voltage Vref is held in bit line BL 11 , thereby enabling a correct read operation. As a result, in the present embodiment, the inexistence of imbalance in the capacitance of the two bit lines BL 11  and BL 21  eliminates any drop in sensitivity of sense amplifier SA 1 , and in addition, eliminates the need to provide a special circuit for adding an offset, thereby simplifying the construction. In this embodiment, moreover, signals TG 1  and TG 2  may be made “H” simultaneously during data reads, and only signal TG 3  may be made “H” curing reference reads. 
     FIG. 18 shows the fourth embodiment of the present invention. The constitutions of memory cell MC 1 , sense amplifier SA 1 , and the four MOS transistors controlled by signals TG 1 , TG 2 , TG 3 , and TG 4  are equivalent to those of the first embodiment. In addition, MOS transistors controlled by signals TG 5  and TG 6  are provided between bit lines BL 1  and BL 2  in this embodiment so as to divide the memory cell array into two portions. In this way, a capacitance CBL 10 , which is a capacitance between CBL 11  and CBL 2  in the third embodiment, can be produced, thereby providing the optimum added capacitance. 
     The read operation of the circuit of FIG. 18 will be next explained with reference to FIGS. 19 and 20. The circuit operation is substantially the same as that of the third embodiment, signals TG 1  and TG 2  being made “H” simultaneously during a data read, and only signal TG 3  being made “H” during a reference read. The present embodiment differs from the third embodiment in that signal TG 5  is always “H” and signal TG 6  is “L” when memory cell MC 1  is selected. Voltage VBL 1  or VBL 0  corresponding to logic “1” or logic “0” is accordingly held in bit line BL 21 , and reference voltage Vref is held in bit line BL 11 , thereby enabling correct read operations. In this embodiment, either signal TG 4  or TG 6 , or both, may be “H” during the first read. The load capacity can thus be changed in this embodiment, and this can be used to allow screening of memory cell MC 1 . When memory cell MC 1  is selected, signals TG 4  and TG 6  are both made “L” during a normal read, but both are made “H” during screening, thereby narrowing the “1” read margin (VBL 1 -Vref). Since logic “1” cannot be read in cells in which the hysteresis characteristic has deteriorated, this arrangement enables detection of cells in which the hysteresis characteristic has deteriorated. 
     FIG. 21 shows the fifth embodiment of the present invention. The constitutions of memory cell MC 1 , sense amplifier SA 1 , and the four MOS transistors controlled by signals TG 1 , TG 2 , TG 3 , and TG 4  are essentially the same as those in the first embodiment. The constitution of memory cell array MC 1 , however, is of an open bit line configuration, in contrast to the folded bit line configuration of the first, second, third, and fourth embodiments. 
     The read operation of the circuit of FIG. 21, is equivalent to that of the third embodiment. When memory cell MC 1  is selected, therefore, signals TG 2  and TG 3  are simultaneously made “H” during a data read, and only signal TG 3  is made “H” during a reference voltage read. In addition, signals TG 1  and TG 2  are simultaneously made “H” during a data read, and only signal TG 3  may be made “H” during a reference read. This embodiment enables a smaller memory cell array. The open bit line configurations cannot be employed in DRAM due to the problem of noise, but in this embodiment, which is a two-read system, the problem of noise inherent in the open bit line configuration is eliminated because the two bit lines BL 1  and BL 2  need not be used simultaneously. The present embodiment therefore enables the use of the open bit line configuration of this invention, and a 2T2C cell of folded configuration of the prior art can therefore be made a folded 1T1C cell by means of the present invention, and by further making this an open bit line 1T1C cell, the present invention has the merit of greatly reducing the chip area. 
     While preferred embodiments of the present invention have been described using specific terms, such description is for illustrative purposes only, and it is to be understood that changes and variations may be made without departing from the spirit or scope of the following claims.